diff --git a/.checkpatch.conf b/.checkpatch.conf
index e2783af81d..511019b260 100644
--- a/.checkpatch.conf
+++ b/.checkpatch.conf
@@ -1,3 +1,7 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
 # Not Linux, so don't expect a Linux tree.
 --no-tree
 
@@ -9,3 +13,19 @@
 --ignore C99_COMMENT_TOLERANCE
 
 --ignore VSPRINTF_POINTER_EXTENSION
+
+# Shorter KConfig descriptions are OK.
+--min-conf-desc-length=2
+
+# Zephyr has a function named "printk" with different facilities than
+# the printk in the Linux kernel this check is made for.
+--ignore PRINTK_WITHOUT_KERN_LEVEL
+
+# Zephyr coding style requires braces even when not explicitly
+# required (unlike the Linux kernel).  In the interest of making code
+# easier to upstream into the Zephyr tree, we should do the same.
+# Tell checkpatch to ignore Linux style here.
+--ignore BRACES
+
+# Zephyr uses ENOSYS to indicate unsupported API calls
+--ignore ENOSYS
diff --git a/.clang-format b/.clang-format
index ee759ab79c..78649d65ca 100644
--- a/.clang-format
+++ b/.clang-format
@@ -66,11 +66,16 @@ DerivePointerAlignment: false
 DisableFormat: false
 ExperimentalAutoDetectBinPacking: false
 FixNamespaceComments: false
-IncludeBlocks: Preserve
+IncludeBlocks: Regroup
 IncludeCategories:
-  - Regex: '.*'
+  - Regex: '^".*\.h"$'
+    Priority: 0
+  - Regex: '^<(assert|complex|ctype|errno|fenv|float|inttypes|limits|locale|math|setjmp|signal|stdarg|stdbool|stddef|stdint|stdio|stdlib|string|tgmath|time|wchar|wctype)\.h>$'
     Priority: 1
-IncludeIsMainRegex: '(Test)?$'
+  - Regex: '^\<zephyr/.*\.h\>$'
+    Priority: 2
+  - Regex: '.*'
+    Priority: 3
 IndentCaseLabels: false
 IndentPPDirectives: None
 IndentWidth: 8
@@ -98,7 +103,6 @@ PenaltyReturnTypeOnItsOwnLine: 60
 
 PointerAlignment: Right
 ReflowComments: true
-SortIncludes: false
 SortUsingDeclarations: false
 SpaceAfterCStyleCast: false
 SpaceAfterTemplateKeyword: true
diff --git a/.clangd b/.clangd
new file mode 100644
index 0000000000..a2f9a678e5
--- /dev/null
+++ b/.clangd
@@ -0,0 +1,10 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CompileFlags:
+  # Remove gcc-specific flags for clangd
+  Remove: [
+  -fno-reorder-functions,
+  -mfp16-format=ieee,
+  ]
diff --git a/.flake8 b/.flake8
new file mode 100644
index 0000000000..f5d6acc820
--- /dev/null
+++ b/.flake8
@@ -0,0 +1,8 @@
+[flake8]
+extend-ignore = E203
+exclude =
+    .hypothesis,
+    .pytest_cache,
+    __pycache__,
+    build,
+    dist
diff --git a/.github/workflows/lint.yml b/.github/workflows/lint.yml
new file mode 100644
index 0000000000..acde12f6b1
--- /dev/null
+++ b/.github/workflows/lint.yml
@@ -0,0 +1,39 @@
+name: lint code in pull request
+
+on:
+  pull_request:
+  push:
+
+jobs:
+  build:
+    name: lint new changes
+    runs-on: ubuntu-latest
+    steps:
+      - name: Checkout code
+        uses: actions/checkout@v4
+        with:
+          fetch-depth: 0
+      - name: get checkpatch
+        run: |
+          wget "https://raw.githubusercontent.com/torvalds/linux/master/scripts/checkpatch.pl"
+          wget "https://raw.githubusercontent.com/torvalds/linux/master/scripts/spelling.txt"
+          chmod +x checkpatch.pl
+
+      - name: checkpatch
+        run: |
+          git diff origin/${{ github.base_ref }} | ./checkpatch.pl --mailback --no-tree --ignore MAINTAINERS,FILE_PATH_CHANGES,SPDX_LICENSE_TAG - > checkpatch.txt || true
+          exit=0
+          if [ -s checkpatch.txt ]; then
+            errors=$(cat checkpatch.txt)
+            errors="${errors//'%'/'%25'}"
+            errors="${errors//$'\n'/'%0A'}"
+            errors="${errors//$'\r'/'%0D'}"
+            echo "::error file=Checkpatch.txt::$errors"
+            exit=1
+          fi
+          if [ $exit = 1 ]; then
+            exit 1;
+          fi
+      - name: output
+        run: |
+          cat checkpatch.txt
diff --git a/.github/workflows/lotus-azalea-build.yml b/.github/workflows/lotus-azalea-build.yml
new file mode 100644
index 0000000000..16feebed44
--- /dev/null
+++ b/.github/workflows/lotus-azalea-build.yml
@@ -0,0 +1,83 @@
+name: build lotus, azalea firmware
+
+on:
+  push:
+    branches:
+      - fwk-*
+      - pr-*
+
+jobs:
+  build:
+    name: Build lotus/azalea
+    runs-on: [marigold-builders]
+
+    strategy:
+      # Only build one at a time because we have only one working directory
+      max-parallel: 1
+      matrix:
+        platform: [
+          # c1488028cf525335b95b277112795219dc6b7688 is bad and won't build with our lotus EC branch
+          { name: lotus, folder: marigold1, ver: "0.0.0", sha_len: 7, zephyr_ref: "lotus-zephyr", cmsis_ref: "c1488028cf525335b95b277112795219dc6b7688^", remote: "github-private" },
+          { name: azalea, folder: marigold1, ver: "0.0.0", sha_len: 7, zephyr_ref: "lotus-zephyr", cmsis_ref: "c1488028cf525335b95b277112795219dc6b7688^", remote: "github-private" },
+        ]
+
+
+    # Build not in $GITHUB_HOME but in the chroot env
+    defaults:
+      run:
+        working-directory: /${{ matrix.platform.folder }}/ec_home/chromiumos
+
+    steps:
+      # Need to use git
+      #- name: Checkout EC code
+      #  uses: actions/checkout@v4
+      #  with:
+      #    path: /lotus/ec_home/chromiumos/src/platform/ec
+
+      #- name: Checkout Zephyr code
+      #  uses: actions/checkout@v2
+      #    path: /lotus/ec_home/chromiumos/src/third_party/zephyr/main
+      #    ref: lotus-zephyr
+      #    repository: ssh://git@github.com/FrameworkComputer/zephyr-ec
+
+      # Need to manually checkout
+      # actions/checkout@v4 complains:
+      # Error: Repository path '/lotus/ec_home/chromiumos/src/platform/ec' is not under '/data/ec_home/actions-runner/_work/ec/ec'
+      # See: https://github.com/actions/checkout/issues/197
+      - name: Manual checkout
+        run: |
+          pushd src/platform/ec
+          git fetch ${{ matrix.platform.remote }}
+          git clean -ffdx
+          # TODO: Doesn't work with on PR, only push
+          git reset --hard ${{ matrix.platform.remote }}/$GITHUB_REF_NAME
+          popd
+
+          pushd src/third_party/zephyr/main
+          git fetch ${{ matrix.platform.remote }}
+          git clean -ffdx
+          git reset --hard ${{ matrix.platform.remote }}/${{ matrix.platform.zephyr_ref }}
+          popd
+
+          pushd src/third_party/zephyr/cmsis
+          git fetch cros
+          git clean -ffdx
+          git reset --hard ${{ matrix.platform.cmsis_ref }}
+          popd
+
+      - name: Build ${{ matrix.platform.name }}
+        run: |
+          cros_sdk zmake build ${{ matrix.platform.name }}
+          echo Built ${{ matrix.platform.name }} EC
+
+      - name: File sha256
+        run: sha256sum src/platform/ec/build/zephyr/${{ matrix.platform.name }}/output/ec.bin
+
+      - name: Generate artifact version
+        run: |
+          echo "VERSIONINFO=$(date -u +'%Y-%m-%d-%H-%M-%S')_$GITHUB_SHA" >> $GITHUB_ENV
+
+      - uses: actions/upload-artifact@v4
+        with:
+          name: ${{ matrix.platform.name }}.${{ env.VERSIONINFO }}
+          path: /${{ matrix.platform.folder }}/ec_home/chromiumos/src/platform/ec/build/zephyr/${{ matrix.platform.name }}/output
diff --git a/.gitignore b/.gitignore
index 6532cf43ee..bc93291213 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,13 +1,42 @@
 build/
-private*/
+/private*/
 # A "local" directory for hiding scripts and artifacts from git.
 local/
 *~
 *.swp
-*.pyc
 tags
 TAGS
+/ctags
 cscope.*
 .tests-passed
 .failedboards/
 .sizes.txt
+.gdb_history
+# Git commit message template (see https://crbug.com/gerrit/10963)
+.gitmessage
+
+# Clion IDE
+.idea/
+
+# VSCode IDE
+.vscode/*
+!.vscode/README.md
+!.vscode/settings.json.default
+*.code-workspace
+
+# Python ignores
+*.pyc
+__pycache__
+*.egg-info
+.hypothesis/
+zephyr/zmake/.coverage
+zephyr/zmake/htmlcov/
+zephyr/zmake/coverage.json
+
+# Clangd language server
+.cache/clangd/index/*
+compile_commands.json
+
+# Twister test output directories
+twister-out*
+flash.bin
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
new file mode 100644
index 0000000000..762c43ba88
--- /dev/null
+++ b/.gitlab-ci.yml
@@ -0,0 +1,514 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+image: jbettis/ubuntu-26apr23
+
+# You can update that image using this repo:
+#   https://gitlab.com/zephyr-ec/gitlab-ci-runner/-/tree/main
+
+# Only run on main and coverage branches
+workflow:
+  rules:
+    - if: ($CI_COMMIT_BRANCH == "main" || $CI_COMMIT_BRANCH == "coverage")
+
+# The directory structure is:
+#
+# ${CI_PROJECT_DIR}
+#    |_ ec_dir/           - EC repo (${EC_DIR})
+#        |_ build/        - make and zmake artifacts (${BUILD_DIR})
+#        |_ twister-out/  - Twister artifacts (${TWISTER_OUT_DIR})
+#    |_ modules/          - Additional Zephyr modules (${MODULES_DIR})
+#    |   |_ cmsis/
+#    |   |_ hal_stm32/
+#    |   |_ nanopb/
+#    |   |_ cryptoc/
+#    |   |_ boringssl/
+#    |_ zephyr/
+#        |_ main/         - Zephyr repo (${ZEPHYR_BASE})
+#
+# On Gitlab builds, ${CI_PROJECT_DIR} is at /builds/zephyr-ec/ec. On local
+# builds, it will be /builds/0/project-0.
+
+before_script:
+  - echo "CI_PROJECT_DIR is at ${CI_PROJECT_DIR}"
+  # Move freshly-checked out ec code to subdirectory
+  - cd ${CI_PROJECT_DIR}
+  - mkdir -p ec_dir
+  - find . -mindepth 1 -maxdepth 1 -name ec_dir -o -print0 | xargs -0 -I {} mv {} ec_dir
+  - export EC_DIR="${CI_PROJECT_DIR}/ec_dir"
+  - export MODULES_DIR="$CI_PROJECT_DIR/modules"
+  - export ZEPHYR_BASE="${CI_PROJECT_DIR}/zephyr/main"
+  - export REPO_BASE="${CI_PROJECT_DIR}/repo"
+  - git config --global --add safe.directory '*'
+  # Get Zephyr repo and modules
+  - checkout_at_date() {
+            local url="$1" ;
+            local branch="$2" ;
+            local path="$3" ;
+            local date="$4" ;
+            local retries=5 ;
+
+            while [ ${retries} -gt 0 ] ; do
+              rm -rf "${path}" ;
+              mkdir -p "${path}" ;
+              if git clone --depth 1 -b "${branch}" "${url}" "${path}"; then
+                break ;
+              else
+                echo "git clone failed will retry ${retries} times";
+              fi ;
+              retries="$(( ${retries} - 1 ))" ;
+            done ;
+            cd "${path}" ;
+            rev="$(git rev-list -n 1 --before="${date}" "${branch}")" ;
+            depth=1 ;
+            while [ -z "${rev}" ] ; do
+              depth="$(( ${depth} + 100 ))" ;
+              git fetch --depth="${depth}" ;
+              rev="$(git rev-list -n 1 --before="${date}" "${branch}")" ;
+            done ;
+            git checkout -d "${rev}" ;
+    }
+  - repo_clone_at_data() {
+            local repo="$1" ;
+            local branch="$2" ;
+            local path="$3" ;
+            local date="$4" ;
+
+            mkdir -p "${REPO_BASE}" ;
+            cd "${REPO_BASE}" ;
+            repo init -u https://chromium.googlesource.com/chromiumos/manifest -b main ;
+            repo sync "${repo}" ;
+
+            mkdir -p "${path}" ;
+            cp -rTLf "${repo}" "${path}" ;
+
+            cd "${path}" ;
+            rev="$(git rev-list -n 1 --before="${date}" "${branch}")" ;
+            depth=1 ;
+            while [ -z "${rev}" ] ; do
+              depth="$(( ${depth} + 100 ))" ;
+              git fetch --depth="${depth}" ;
+              rev="$(git rev-list -n 1 --before="${date}" "${branch}")" ;
+            done ;
+            git checkout -d "${rev}" ;
+            rev="$(git rev-list -n 1 --before="${date}" "${branch}")" ;
+    }
+  - ec_commit_date="$(cd ${EC_DIR} ; git log -1 HEAD --format=%cd --date=iso)"
+  - checkout_at_date "https://chromium.googlesource.com/chromium/tools/depot_tools.git" "main" "${CI_PROJECT_DIR}/depot_tools" "${ec_commit_date}"
+  - export PATH="${CI_PROJECT_DIR}/depot_tools:$PATH"
+  - checkout_at_date "https://chromium.googlesource.com/chromiumos/third_party/zephyr" "main" "${ZEPHYR_BASE}" "${ec_commit_date}"
+  - checkout_at_date "https://chromium.googlesource.com/chromiumos/third_party/zephyr/cmsis" "chromeos-main" "${MODULES_DIR}/cmsis" "${ec_commit_date}"
+  - checkout_at_date "https://chromium.googlesource.com/chromiumos/third_party/zephyr/hal_stm32" "chromeos-main" "${MODULES_DIR}/hal_stm32" "${ec_commit_date}"
+  - checkout_at_date "https://chromium.googlesource.com/chromiumos/third_party/zephyr/nanopb" "main" "${MODULES_DIR}/nanopb" "${ec_commit_date}"
+  - checkout_at_date "https://chromium.googlesource.com/chromiumos/third_party/cryptoc" "main" "${MODULES_DIR}/cryptoc" "${ec_commit_date}"
+  - repo_clone_at_data "src/third_party/boringssl" "m/main" "${MODULES_DIR}/boringssl" "${ec_commit_date}"
+  # Add a symlink so the ec appears in modules directory (hack to make zmake work)
+  - ln -s "${EC_DIR}" "${MODULES_DIR}/ec"
+  # Install Python and packages
+  - python3 -V  # Print out python version for debugging
+  - python3 -m pip install "${EC_DIR}/zephyr/zmake[tests]" --user
+  - python3 -m pip install natsort
+  - export PATH="$PATH:$HOME/.local/bin"
+  - export PYTHONIOENCODING=utf-8
+  # Build directory
+  - export BUILD_DIR=${EC_DIR}/build
+  - export TWISTER_OUT_DIR=${EC_DIR}/twister-out
+
+# Users of this template must set:
+# $PROJECT to the project to build. E.g., "lazor"
+.build_template: &build_template
+  stage: build
+  needs: []
+  script:
+    - zmake --zephyr-base "${ZEPHYR_BASE}"
+      --modules-dir "${MODULES_DIR}" -l DEBUG build
+      -B "${BUILD_DIR}" -t ${TOOLCHAIN:-zephyr}
+      "${PROJECT}"
+    - for b in "${BUILD_DIR}/${PROJECT}"/build-* ; do
+        bdir=$(basename ${b}) ;
+        if ninja -C ${b} ram_report >"${BUILD_DIR}/${PROJECT}/output/${bdir}_ram_report.txt" ; then
+          cp ${b}/ram.json "${BUILD_DIR}/${PROJECT}/output/${bdir}_ram.json" ;
+        else
+          echo "Ram report failed" ;
+        fi ;
+        if ninja -C ${b} rom_report >"${BUILD_DIR}/${PROJECT}/output/${bdir}_rom_report.txt" ; then
+          cp ${b}/rom.json "${BUILD_DIR}/${PROJECT}/output/${bdir}_rom.json" ;
+        else
+          echo "Rom report failed" ;
+        fi ;
+      done
+    - ls "${BUILD_DIR}/${PROJECT}" "${BUILD_DIR}/${PROJECT}/output"
+  artifacts:
+    paths:
+      - ec_dir/build/${PROJECT}/output/*
+    expire_in: 1 week
+
+# Users of this template must set:
+# $PROJECT to the project to build. E.g., "lazor"
+# Builds the project with coverage enabled, removes the non-ec files.
+# Then merges with the tests, excludes all files not used by this project,
+# and generates a report.
+# NOTE: If you change the lcov -r command below, also edit the one in
+# merged_coverage
+.coverage_template: &coverage_template
+  stage: test
+  needs:
+    - "merged_coverage"
+    - "zephyr_coverage"
+  script:
+    - cd ${EC_DIR}
+    - zmake --zephyr-base "${ZEPHYR_BASE}"
+      --modules-dir "${MODULES_DIR}" -l DEBUG build --coverage
+      -B "${BUILD_DIR}" -t ${TOOLCHAIN:-zephyr}
+      "${PROJECT}"
+    - lcov --rc lcov_branch_coverage=1 -o "${BUILD_DIR}/${PROJECT}/output/merged.info"
+      -a "${BUILD_DIR}/${PROJECT}/output/zephyr.info"
+      -a "${BUILD_DIR}/merged.info"
+    - lcov --rc lcov_branch_coverage=1
+      -o "${BUILD_DIR}/${PROJECT}/output/no_zephyr.info"
+      -r "${BUILD_DIR}/${PROJECT}/output/zephyr.info" "${ZEPHYR_BASE}/**"
+      "${MODULES_DIR}/**"
+      "${EC_DIR}/zephyr/drivers/**" "${EC_DIR}/zephyr/include/drivers/**"
+      "${EC_DIR}/zephyr/shim/chip/**" "${EC_DIR}/zephyr/shim/core/**"
+      "/usr/include/**"
+      "${EC_DIR}/build/**" "${EC_DIR}/twister-out*/**"
+      "${EC_DIR}/test/**"
+      "${EC_DIR}/zephyr/shim/chip/npcx/npcx_monitor/**"
+      "${EC_DIR}/zephyr/emul/**" "${EC_DIR}/zephyr/test/**"
+      "**/testsuite/**" "**/subsys/emul/**"
+    - util/lcov_stencil.py -o "${BUILD_DIR}/${PROJECT}/output/prefiltered.info"
+      "${BUILD_DIR}/${PROJECT}/output/no_zephyr.info"
+      "${BUILD_DIR}/${PROJECT}/output/merged.info"
+    - lcov --rc lcov_branch_coverage=1
+      -o "${BUILD_DIR}/${PROJECT}/output/filtered_no_zephyr.info"
+      -r "${BUILD_DIR}/${PROJECT}/output/prefiltered.info"
+      "${ZEPHYR_BASE}/**" "${MODULES_DIR}/**"
+      "${EC_DIR}/zephyr/drivers/**" "${EC_DIR}/zephyr/include/drivers/**"
+      "${EC_DIR}/zephyr/shim/chip/**" "${EC_DIR}/zephyr/shim/core/**"
+      "/usr/include/**"
+      "${EC_DIR}/build/**" "${EC_DIR}/twister-out*/**"
+      "${EC_DIR}/zephyr/shim/chip/npcx/npcx_monitor/**"
+      "${EC_DIR}/test/**"
+      "${EC_DIR}/include/tests/**"
+      "${EC_DIR}/private/test/**"
+      "${EC_DIR}/private/fingerprint/*/mcutest/**"
+      "${EC_DIR}/zephyr/test/**"
+      "${EC_DIR}/include/mock/**"
+      "${EC_DIR}/common/mock/**"
+      "${EC_DIR}/board/host/**"
+      "${EC_DIR}/chip/host/**"
+      "${EC_DIR}/core/host/**"
+      "${EC_DIR}/zephyr/emul/**"
+      "${EC_DIR}/zephyr/mock/**"
+      "${EC_DIR}/zephyr/program/dev/**"
+      "**/*_test.c"
+      "**/*_test.h"
+      "**/*_emul.c"
+      "**/*_emul.h"
+      "${EC_DIR}/include/test_util.h"
+      "${EC_DIR}/common/test_util.c"
+      "${EC_DIR}/zephyr/shim/src/test_util.c"
+      "${EC_DIR}/zephyr/shim/src/ztest_system.c"
+      "${EC_DIR}/driver/tcpm/it8xxx2.c"
+    - /usr/bin/genhtml --branch-coverage -q
+      -o "${BUILD_DIR}/${PROJECT}/output/filtered_no_zephyr_rpt"
+      -t "${PROJECT} coverage w/o zephyr"
+      -p ${EC_DIR}
+      -s "${BUILD_DIR}/${PROJECT}/output/filtered_no_zephyr.info"
+  artifacts:
+    paths:
+      - ec_dir/build/${PROJECT}/output/*.info
+      - ec_dir/build/${PROJECT}/output/*_rpt
+    expire_in: 1 week
+    when: always
+  coverage: '/lines\.*: \d+\.\d+%/'
+
+herobrine:
+  variables:
+    PROJECT: "herobrine"
+  <<: *build_template
+
+herobrine_coverage:
+  variables:
+    PROJECT: "herobrine"
+  <<: *coverage_template
+
+nivviks_coverage:
+  variables:
+    PROJECT: "nivviks"
+  <<: *coverage_template
+
+nereid_coverage:
+  variables:
+    PROJECT: "nereid"
+  <<: *coverage_template
+
+it8xxx2_evb:
+  variables:
+    PROJECT: "it8xxx2_evb"
+  <<: *build_template
+
+kingler:
+  variables:
+    PROJECT: "kingler"
+  <<: *build_template
+
+kingler_coverage:
+  variables:
+    PROJECT: "kingler"
+  <<: *coverage_template
+
+krabby:
+  variables:
+    PROJECT: "krabby"
+  <<: *build_template
+
+krabby_coverage:
+  variables:
+    PROJECT: "krabby"
+  <<: *coverage_template
+
+lazor:
+  variables:
+    PROJECT: "lazor"
+  <<: *build_template
+
+npcx7_evb:
+  variables:
+    PROJECT: "npcx7"
+  <<: *build_template
+
+npcx9_evb:
+  variables:
+    PROJECT: "npcx9"
+  <<: *build_template
+
+skyrim:
+  variables:
+    PROJECT: "skyrim"
+  <<: *build_template
+
+skyrim_coverage:
+  variables:
+    PROJECT: "skyrim"
+  <<: *coverage_template
+
+winterhold:
+  variables:
+    PROJECT: "winterhold"
+  <<: *build_template
+
+winterhold_coverage:
+  variables:
+    PROJECT: "winterhold"
+  <<: *coverage_template
+
+frostflow:
+  variables:
+    PROJECT: "frostflow"
+  <<: *build_template
+
+frostflow_coverage:
+  variables:
+    PROJECT: "frostflow"
+  <<: *coverage_template
+
+crystaldrift:
+  variables:
+    PROJECT: "crystaldrift"
+  <<: *build_template
+
+crystaldrift_coverage:
+  variables:
+    PROJECT: "crystaldrift"
+  <<: *coverage_template
+
+markarth:
+  variables:
+    PROJECT: "markarth"
+  <<: *build_template
+
+markarth_coverage:
+  variables:
+    PROJECT: "markarth"
+  <<: *coverage_template
+
+rex:
+  variables:
+    PROJECT: "rex"
+  <<: *build_template
+
+rex_coverage:
+  variables:
+    PROJECT: "rex"
+  <<: *coverage_template
+
+geralt:
+  variables:
+    PROJECT: "geralt"
+  <<: *build_template
+
+geralt_coverage:
+  variables:
+    PROJECT: "geralt"
+  <<: *coverage_template
+
+myst:
+  variables:
+    PROJECT: "myst"
+  <<: *build_template
+
+myst_coverage:
+  variables:
+    PROJECT: "myst"
+  <<: *coverage_template
+
+ec_coverage:
+  stage: test
+  needs: []
+  script:
+    - cd ${EC_DIR}
+    - make -j$(nproc) BORINGSSL_DIR="${MODULES_DIR}/boringssl"
+      CRYPTOC_DIR="${MODULES_DIR}/cryptoc"
+      CROSS_COMPILE_arm=/opt/zephyr-sdk/arm-zephyr-eabi/bin/arm-zephyr-eabi-
+      CROSS_COMPILE_host=/usr/bin/
+      test-coverage
+  artifacts:
+    paths:
+      - ec_dir/build/coverage/coverage_rpt/*
+      - ec_dir/build/coverage/lcov.info
+    expire_in: 1 week
+  coverage: '/lines\.*: \d+\.\d+%/'
+
+zephyr_coverage:
+  stage: test
+  needs: []
+  script:
+    - python3 ${EC_DIR}/twister --coverage --outdir "${TWISTER_OUT_DIR}"
+      -v -i -x=ALLOW_WARNINGS=ON
+  artifacts:
+    paths:
+      - ec_dir/twister-out/coverage.info
+    expire_in: 1 week
+  coverage: '/lines\.*: \d+\.\d+%/'
+
+zephyr_boards_coverage:
+  stage: build
+  needs: []
+  parallel: 5
+  script:
+    - cd ${EC_DIR}
+    - projects=( $(zmake --zephyr-base "${ZEPHYR_BASE}"
+      --modules-dir "${MODULES_DIR}" list-projects |
+      split -n r/"${CI_NODE_INDEX}"/"${CI_NODE_TOTAL}") )
+    - zmake --zephyr-base "${ZEPHYR_BASE}"
+      --modules-dir "${MODULES_DIR}" -l DEBUG build
+      --coverage --delete-intermediates "${projects[@]}"
+    - mv build/zephyr/all_builds.info "build/zephyr/all_builds${CI_NODE_INDEX}.info"
+  artifacts:
+    paths:
+      - ec_dir/build/zephyr/all_builds*.info
+    expire_in: 1 week
+  coverage: '/lines\.*: \d+\.\d+%/'
+
+# NOTE: If you change the lcov -r command below, also edit the one in
+# .coverage_template
+merged_coverage:
+  stage: test
+  needs: ["ec_coverage", "zephyr_coverage", "zephyr_boards_coverage"]
+  script:
+    # build_dir / "all_tests.info" -> "${BUILD_DIR}/merged.info"
+    - lcov --rc lcov_branch_coverage=1 -o "${BUILD_DIR}/merged.info"
+      -a "${BUILD_DIR}/coverage/lcov.info" -a "${TWISTER_OUT_DIR}/coverage.info"
+    - printf ' -a %s' ${BUILD_DIR}/zephyr/all_builds[0-9]*.info | xargs -x
+      lcov --rc lcov_branch_coverage=1 -o "${BUILD_DIR}/zephyr/zephyr_merged.info"
+      -a "${BUILD_DIR}/merged.info"
+    - lcov --rc lcov_branch_coverage=1
+      -o "${BUILD_DIR}/all_builds_filtered.info"
+      -r "${BUILD_DIR}/zephyr/zephyr_merged.info"
+      "${EC_DIR}/build/**" "${EC_DIR}/twister-out*/**" "/usr/include/**"
+      "/usr/lib/**"
+      "${EC_DIR}/test/**"
+      "${EC_DIR}/include/tests/**"
+      "${EC_DIR}/private/test/**"
+      "${EC_DIR}/private/fingerprint/*/mcutest/**"
+      "${EC_DIR}/zephyr/test/**"
+      "${ZEPHYR_BASE}/main/subsys/testsuite/**"
+      "${EC_DIR}/include/mock/**"
+      "${EC_DIR}/common/mock/**"
+      "${EC_DIR}/board/host/**"
+      "${EC_DIR}/chip/host/**"
+      "${EC_DIR}/core/host/**"
+      "${EC_DIR}/zephyr/emul/**"
+      "${EC_DIR}/zephyr/mock/**"
+      "${EC_DIR}/zephyr/program/dev/**"
+      "${ZEPHYR_BASE}/main/subsys/emul/**"
+      "**/*_test.c"
+      "**/*_test.h"
+      "**/*_emul.c"
+      "**/*_emul.h"
+      "${EC_DIR}/include/test_util.h"
+      "${EC_DIR}/common/test_util.c"
+      "${EC_DIR}/zephyr/shim/src/test_util.c"
+      "${EC_DIR}/zephyr/shim/src/ztest_system.c"
+    - /usr/bin/genhtml --branch-coverage -q
+      -o "${BUILD_DIR}/all_builds_filtered_rpt"
+      -t "All boards and tests merged"
+      -p ${EC_DIR}
+      -s "${BUILD_DIR}/all_builds_filtered.info"
+  artifacts:
+    paths:
+      - ec_dir/build/*.info
+      - ec_dir/build/*_rpt
+    expire_in: 1 week
+  coverage: '/lines\.*: \d+\.\d+%/'
+
+testall:
+  stage: test
+  needs: []
+  script:
+    - python3 ${EC_DIR}/twister --outdir "${TWISTER_OUT_DIR}" -v -i
+      -x=ALLOW_WARNINGS=ON
+
+# The download url changed. Disable until we can figure it out.
+# twister_coverage:
+#   stage: test
+#   needs: []
+#   script:
+#     - mkdir -p ${BUILD_DIR}/zephyr_codecov
+#     - for commitid in $(cd "${ZEPHYR_BASE}" ; git fetch --depth=100 ; git log | awk '/GitOrigin-RevId:/ {print $2}') ; do
+#         echo "COMMITID = ${commitid?}" ;
+#         if wget -O /tmp/coverage.html "https://app.codecov.io/gh/zephyrproject-rtos/zephyr/commit/${commitid?}" ; then
+#           downloadurl=$(sed -e '/download\/build/!d' -e 's|^.*href="|https://codecov.io|' -e 's|".*$||' /tmp/coverage.html | head -1) ;
+#           echo "DOWNLOADURL = ${downloadurl?}" ;
+#           wget -O ${BUILD_DIR}/zephyr_codecov/merged.info.raw "${downloadurl?}" ;
+#           sed <${BUILD_DIR}/zephyr_codecov/merged.info.raw >${BUILD_DIR}/zephyr_codecov/merged.info
+#             -e '1,/<<<<<< network/d' -e '/<<<<<< EOF/,$d' ;
+#           sed <${BUILD_DIR}/zephyr_codecov/merged.info >${BUILD_DIR}/zephyr_codecov/fixed.info
+#             -e "s|/__w/zephyr/zephyr|${ZEPHYR_BASE}|"
+#             -e "s|/__w/zephyr/modules/hal/cmsis|${MODULES_DIR}/cmsis|"
+#             -e "s|/__w/zephyr/modules|${MODULES_DIR}|" ;
+#           break ;
+#         fi ;
+#       done
+#     - lcov --rc lcov_branch_coverage=1 --summary ${BUILD_DIR}/zephyr_codecov/fixed.info
+#   artifacts:
+#     paths:
+#       - ec_dir/build/zephyr_codecov/fixed.info
+#     expire_in: 1 week
+#   coverage: '/lines\.*: \d+\.\d+%/'
+
+zmake_coverage:
+  stage: test
+  needs: []
+  script:
+    - cd ${EC_DIR}/zephyr/zmake
+    - coverage run --source=zmake -m pytest .
+    - coverage report
+    - coverage html
+  artifacts:
+    paths:
+      - ec_dir/zephyr/zmake/htmlcov/*
+    expire_in: 1 week
+  coverage: '/^TOTAL.+?(\d+\%)$/'
diff --git a/.vscode/README.md b/.vscode/README.md
new file mode 100644
index 0000000000..1e83806519
--- /dev/null
+++ b/.vscode/README.md
@@ -0,0 +1,3 @@
+# VSCode Setting
+
+See [docs/ide-support.md](/docs/ide-support.md).
diff --git a/.vscode/settings.json.default b/.vscode/settings.json.default
new file mode 100644
index 0000000000..2c9497413a
--- /dev/null
+++ b/.vscode/settings.json.default
@@ -0,0 +1,36 @@
+/* Copy this file to settings.json to active these defaults. */
+{
+   "editor.rulers": [
+      80
+   ],
+   /* C, Makefiles, ASM, Linkerfiles, Properties */
+   "editor.insertSpaces": false,
+   "editor.tabSize": 8,
+   "python.formatting.provider": "black",
+   /* Some exceptions based on current trends */
+   "[markdown]": {
+      "editor.insertSpaces": true,
+      "editor.tabSize": 2
+   },
+   "[python]": {
+      "editor.insertSpaces": true,
+      "editor.tabSize": 4
+   },
+   "[shellscript]": {
+      "editor.insertSpaces": true,
+      "editor.tabSize": 2
+   },
+   "[yaml]": {
+      "editor.insertSpaces": true,
+      "editor.tabSize": 2
+   },
+   "files.associations": {
+      "Makefile.*": "makefile",
+      "*.inc": "c",
+      "*.wrap": "c",
+      "*.tasklist": "c",
+      "*.irqlist": "c",
+      "*.mocklist": "c",
+      "*.testlist": "c"
+   }
+}
\ No newline at end of file
diff --git a/BUILD.bazel b/BUILD.bazel
new file mode 100644
index 0000000000..a814a38237
--- /dev/null
+++ b/BUILD.bazel
@@ -0,0 +1,231 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+load(
+    "@cros_firmware//platform/rules_cros_firmware/cros_firmware:ec.bzl",
+    "ec_binary",
+)
+
+ec_binary(
+    name = "adlrvp_mchp",
+)
+
+ec_binary(
+    name = "adlrvp_npcx",
+    extra_modules = ["cmsis"],
+)
+
+ec_binary(
+    name = "brya",
+    extra_modules = ["cmsis"],
+)
+
+ec_binary(
+    name = "craask",
+    extra_modules = ["cmsis"],
+)
+
+ec_binary(
+    name = "crystaldrift",
+    extra_modules = ["cmsis"],
+)
+
+ec_binary(
+    name = "dev-posix",
+)
+
+ec_binary(
+    name = "evoker",
+    extra_modules = ["cmsis"],
+)
+
+ec_binary(
+    name = "frostflow",
+    extra_modules = ["cmsis"],
+)
+
+ec_binary(
+    name = "geralt",
+)
+
+ec_binary(
+    name = "gothrax",
+)
+
+ec_binary(
+    name = "herobrine",
+    extra_modules = ["cmsis"],
+)
+
+ec_binary(
+    name = "hoglin",
+    extra_modules = ["cmsis"],
+)
+
+ec_binary(
+    name = "it8xxx2_evb",
+)
+
+ec_binary(
+    name = "joxer",
+)
+
+ec_binary(
+    name = "kingler",
+    extra_modules = ["cmsis"],
+)
+
+ec_binary(
+    name = "krabby",
+)
+
+ec_binary(
+    name = "lazor",
+    extra_modules = ["cmsis"],
+)
+
+ec_binary(
+    name = "magikarp",
+)
+
+ec_binary(
+    name = "markarth",
+    extra_modules = ["cmsis"],
+)
+
+ec_binary(
+    name = "minimal-it8xxx2",
+)
+
+ec_binary(
+    name = "minimal-npcx9",
+    extra_modules = ["cmsis"],
+)
+
+ec_binary(
+    name = "minimal-posix",
+)
+
+ec_binary(
+    name = "mtlrvpp_mchp",
+    extra_modules = ["cmsis"],
+)
+
+ec_binary(
+    name = "mtlrvpp_npcx",
+)
+
+ec_binary(
+    name = "myst",
+    extra_modules = ["cmsis"],
+)
+
+ec_binary(
+    name = "nereid",
+)
+
+ec_binary(
+    name = "nereid_cx",
+)
+
+ec_binary(
+    name = "nivviks",
+    extra_modules = ["cmsis"],
+)
+
+ec_binary(
+    name = "npcx7",
+    extra_modules = ["cmsis"],
+)
+
+ec_binary(
+    name = "npcx9",
+    extra_modules = ["cmsis"],
+)
+
+ec_binary(
+    name = "pujjo",
+    extra_modules = ["cmsis"],
+)
+
+ec_binary(
+    name = "rex",
+    extra_modules = ["cmsis"],
+)
+
+ec_binary(
+    name = "rex-ish-ec",
+    extra_modules = ["cmsis"],
+)
+
+ec_binary(
+    name = "screebo",
+    extra_modules = ["cmsis"],
+)
+
+ec_binary(
+    name = "skyrim",
+    extra_modules = ["cmsis"],
+)
+
+ec_binary(
+    name = "starmie",
+)
+
+ec_binary(
+    name = "steelix",
+    extra_modules = ["cmsis"],
+)
+
+ec_binary(
+    name = "tentacruel",
+)
+
+ec_binary(
+    name = "uldren",
+    extra_modules = ["cmsis"],
+)
+
+ec_binary(
+    name = "villager",
+    extra_modules = ["cmsis"],
+)
+
+ec_binary(
+    name = "voltorb",
+    extra_modules = ["cmsis"],
+)
+
+ec_binary(
+    name = "winterhold",
+    extra_modules = ["cmsis"],
+)
+
+ec_binary(
+    name = "xivu",
+    extra_modules = ["cmsis"],
+)
+
+ec_binary(
+    name = "xivur",
+    extra_modules = ["cmsis"],
+)
+
+ec_binary(
+    name = "yaviks",
+)
+
+ec_binary(
+    name = "yavilla",
+)
+
+ec_binary(
+    name = "zoglin",
+    extra_modules = ["cmsis"],
+)
+
+ec_binary(
+    name = "zombie",
+    extra_modules = ["cmsis"],
+)
diff --git a/CMakeLists.txt b/CMakeLists.txt
new file mode 100644
index 0000000000..34e81f2be9
--- /dev/null
+++ b/CMakeLists.txt
@@ -0,0 +1,29 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Note: this cmake system implements only a zephyr module, and is not
+# intended to build a complete EC.  To build projects in platform/ec,
+# you should continue to use the Makefile system.
+#
+# Googlers can find the design doc at go/zephyr-shim.
+
+if(NOT DEFINED ZEPHYR_CURRENT_MODULE_DIR)
+  message(FATAL_ERROR "This Cmake system implements only a Zephyr module, and
+          should not be invoked directly.  Please continue to use the Makefile
+          system for non-Zephyr builds.")
+endif()
+
+set(PLATFORM_EC "${ZEPHYR_CURRENT_MODULE_DIR}" CACHE PATH
+    "Path to the platform/ec repo.")
+
+set(PLATFORM_EC_PROGRAM_DIR "${PLATFORM_EC}/zephyr/program" CACHE PATH
+  "Path to the root directory containing all Zephyr EC programs and projects.")
+
+if(NOT EXISTS "${PLATFORM_EC}/zephyr/module.yml")
+  message(FATAL_ERROR "Failed to resolve PLATFORM_EC at
+          ${PLATFORM_EC}/zephyr/module.yml")
+endif()
+
+add_subdirectory(zephyr)
+add_subdirectory(common)
diff --git a/CPPLINT.cfg b/CPPLINT.cfg
new file mode 100644
index 0000000000..d260909910
--- /dev/null
+++ b/CPPLINT.cfg
@@ -0,0 +1,4 @@
+set noparent
+# Disable cpplint, since EC is a C project that follows Linux kernel style.
+# cpplint is called by "cros lint".
+exclude_files=.*
diff --git a/DIR_METADATA b/DIR_METADATA
new file mode 100644
index 0000000000..526b1dd7ed
--- /dev/null
+++ b/DIR_METADATA
@@ -0,0 +1,17 @@
+# Metadata information for this directory.
+#
+# For more information on DIR_METADATA files, see:
+#   https://source.chromium.org/chromium/infra/infra/+/main:go/src/infra/tools/dirmd/README.md
+#
+# For the schema of this file, see Metadata message:
+#   https://source.chromium.org/chromium/infra/infra/+/main:go/src/infra/tools/dirmd/proto/dir_metadata.proto
+
+buganizer {
+  component_id: 167114  # ChromeOS > Platform > Enablement > Firmware > EC
+}
+
+buganizer_public {
+  component_id: 960650  # ChromeOS Public Tracker > Core Systems > Firmware > EC
+}
+
+team_email: "cros-ec@google.com"
diff --git a/Kconfig b/Kconfig
new file mode 100644
index 0000000000..d3705151e3
--- /dev/null
+++ b/Kconfig
@@ -0,0 +1,6 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+rsource "zephyr/Kconfig"
+rsource "common/Kconfig"
diff --git a/LICENSE b/LICENSE
index da112abc64..a55bf15b9d 100644
--- a/LICENSE
+++ b/LICENSE
@@ -1,4 +1,4 @@
-// Copyright 2010 The Chromium OS Authors. All rights reserved.
+// Copyright 2010 The ChromiumOS Authors
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
@@ -10,7 +10,7 @@
 // copyright notice, this list of conditions and the following disclaimer
 // in the documentation and/or other materials provided with the
 // distribution.
-//    * Neither the name of Google Inc. nor the names of its
+//    * Neither the name of Google LLC nor the names of its
 // contributors may be used to endorse or promote products derived from
 // this software without specific prior written permission.
 //
diff --git a/Makefile b/Makefile
index 1db6de37b2..812b5dc2c4 100644
--- a/Makefile
+++ b/Makefile
@@ -1,4 +1,4 @@
-# Copyright 2011 The Chromium OS Authors. All rights reserved.
+# Copyright 2011 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -13,7 +13,7 @@
 # This is used to exclude build targets that depend on sanitizers such as
 # fuzzers on architectures that don't support sanitizers yet (e.g. arm).
 ARCH?=amd64
-BOARD ?= bds
+BOARD ?= elm
 
 # Directory where the board is configured (includes /$(BOARD) at the end)
 BDIR:=$(wildcard board/$(BOARD))
@@ -50,6 +50,8 @@ EMPTY=
 ifdef CTS_MODULE
 # CTS builds need different directories per board per suite.
 out?=build/$(BOARD)/cts_$(CTS_MODULE)
+else ifdef TEST_COVERAGE
+out?=build/coverage/initial-$(BOARD)
 else
 out?=build/$(BOARD)
 endif
@@ -113,6 +115,12 @@ CFLAGS_BASEBOARD=
 endif
 include chip/$(CHIP)/build.mk
 
+# The toolchain must be set before referencing any toolchain-related variables
+# (CC, CPP, CXX, etc.) so that the correct toolchain is used. The CORE variable
+# is set in the CHIP build file, so this include must come after including the
+# CHIP build file.
+include core/$(CORE)/toolchain.mk
+
 # Create uppercase config variants, to avoid mixed case constants.
 # Also translate '-' to '_', so 'cortex-m' turns into 'CORTEX_M'.  This must
 # be done before evaluating config.h.
@@ -128,7 +136,7 @@ UC_PROJECT:=$(call uppercase,$(PROJECT))
 # Transform the configuration into make variables.  This must be done after
 # the board/baseboard/project/chip/core variables are defined, since some of
 # the configs are dependent on particular configurations.
-includes=include core/$(CORE)/include $(dirs) $(out) fuzz test
+includes=include core/$(CORE)/include include/driver $(dirs) $(out) fuzz test third_party
 ifdef CTS_MODULE
 includes+=cts/$(CTS_MODULE) cts
 endif
@@ -148,6 +156,7 @@ endif
 _tsk_lst_flags+=-I$(BDIR) -DBOARD_$(UC_BOARD)=$(EMPTY) -I$(BASEDIR) \
 		-DBASEBOARD_$(UC_BASEBOARD)=$(EMPTY) \
 		-D_MAKEFILE=$(EMPTY) -imacros $(_tsk_lst_file)
+-include private/task_list_flags.mk
 
 _tsk_lst_ro:=$(shell $(CPP) -P -DSECTION_IS_RO=$(EMPTY) \
 	$(_tsk_lst_flags) include/task_filter.h)
@@ -210,7 +219,8 @@ _mock_cfg := $(foreach t,$(_mock_lst) ,HAS_MOCK_$(t))
 CPPFLAGS += $(foreach t,$(_mock_cfg),-D$(t)=$(EMPTY))
 $(foreach c,$(_mock_cfg),$(eval $(c)=y))
 
-ifneq "$(CONFIG_COMMON_RUNTIME)" "y"
+ifneq ($(CONFIG_COMMON_RUNTIME),y)
+ifneq ($(CONFIG_DFU_BOOTMANAGER_MAIN),ro)
 	_irq_list:=$(shell $(CPP) $(CPPFLAGS) -P -Ichip/$(CHIP) -I$(BASEDIR) \
 		-I$(BDIR) -D"ENABLE_IRQ(x)=EN_IRQ x" \
 		-imacros chip/$(CHIP)/registers.h \
@@ -218,6 +228,7 @@ ifneq "$(CONFIG_COMMON_RUNTIME)" "y"
 	CPPFLAGS+=$(foreach irq,$(_irq_list),\
 		    -D"irq_$(irq)_handler_optional=irq_$(irq)_handler")
 endif
+endif
 
 # Compute RW firmware size and offset
 _rw_off_str:=$(shell echo "CONFIG_RW_MEM_OFF" | $(CPP) $(CPPFLAGS) -P \
@@ -255,7 +266,13 @@ include $(BASEDIR)/build.mk
 ifneq ($(BASEDIR),$(BDIR))
 include $(BDIR)/build.mk
 endif
+ifeq ($(USE_BUILTIN_STDLIB), 1)
+include builtin/build.mk
+else
+include libc/build.mk
+endif
 include chip/$(CHIP)/build.mk
+include core/build.mk
 include core/$(CORE)/build.mk
 include common/build.mk
 include driver/build.mk
@@ -273,6 +290,12 @@ include test/build.mk
 include util/build.mk
 include util/lock/build.mk
 
+
+ifeq ($(CONFIG_BORINGSSL_CRYPTO), y)
+include third_party/boringssl/common/build.mk
+include crypto/build.mk
+endif
+
 includes+=$(includes-y)
 
 # Wrapper for fetching all the sources relevant to this build
@@ -294,6 +317,11 @@ ifneq ($(PBDIR),)
 all-obj-$(1)+=$(call objs_from_dir_p,$(PBDIR),board-private,$(1))
 endif
 all-obj-$(1)+=$(call objs_from_dir_p,common,common,$(1))
+ifeq ($(USE_BUILTIN_STDLIB), 1)
+all-obj-$(1)+=$(call objs_from_dir_p,builtin,builtin,$(1))
+else
+all-obj-$(1)+=$(call objs_from_dir_p,libc,libc,$(1))
+endif
 all-obj-$(1)+=$(call objs_from_dir_p,driver,driver,$(1))
 all-obj-$(1)+=$(call objs_from_dir_p,power,power,$(1))
 ifdef CTS_MODULE
@@ -304,17 +332,61 @@ all-obj-$(1)+=$(call objs_from_dir_p,fuzz,$(PROJECT),$(1))
 else
 all-obj-$(1)+=$(call objs_from_dir_p,test,$(PROJECT),$(1))
 endif
+ifeq ($(CONFIG_BORINGSSL_CRYPTO), y)
+all-obj-$(1)+= \
+    $(call objs_from_dir_p,third_party/boringssl/common,boringssl,$(1))
+all-obj-$(1)+= $(call objs_from_dir_p,crypto,crypto,$(1))
+endif
 endef
 
 # Get all sources to build
 $(eval $(call get_sources,y))
 $(eval $(call get_sources,ro))
 
+# The following variables are meant to be initialized in the baseboard or
+# board's build.mk. They will later be appended to in util/build.mk with
+# utils that should be generated for all boards.
+#
+# build-util-bin-y - Utils for the system doing the "build".
+#                    For example, the 64-bit x86 GNU/Linux running make.
+#                    These are often program that are needed by the build
+#                    system to generate code for use in firmware.
+# host-util-bin-y  - Utils for the target platform on top of the EC.
+#                    For example, the 32-bit x86 Chromebook.
+# build-util-art-y - Build ?artifacts? for the system doing the "build"
+#
+# The util targets added to these variable will pickup extra build objects
+# from their optional <util_name>-objs make variable.
+#
+# See commit bc4c1b4 for more context.
+build-utils := $(call objs_from_dir,$(out)/util,build-util-bin)
+ifeq ($(BOARD),host)
+host-utils := $(call objs_from_dir,$(out)/util,host-util-bin)
+host-utils-cxx := $(call objs_from_dir,$(out)/util,host-util-bin-cxx)
+endif
+build-art := $(call objs_from_dir,$(out),build-util-art)
+# Use the util_name with an added .c AND the special <util_name>-objs variable.
+build-srcs := $(foreach u,$(build-util-bin-y),$(sort $($(u)-objs:%.o=util/%.c) \
+                $(wildcard util/$(u).c)))
+host-srcs := $(foreach u,$(host-util-bin-y),$(sort $($(u)-objs:%.o=util/%.c) \
+               $(wildcard util/$(u).c)))
+host-srcs-cxx := $(foreach u,$(host-util-bin-cxx-y), \
+	$(sort $($(u)-objs:%.o=util/%.cc) $(wildcard util/$(u).cc)))
+
 dirs=core/$(CORE) chip/$(CHIP) $(BASEDIR) $(BDIR) common fuzz power test \
 	cts/common cts/$(CTS_MODULE) $(out)/gen
 dirs+= private private-kandou $(PDIR) $(PBDIR)
 dirs+=$(shell find common -type d)
 dirs+=$(shell find driver -type d)
+ifeq ($(USE_BUILTIN_STDLIB), 1)
+dirs+=builtin
+else
+dirs+=libc
+endif
+ifeq ($(CONFIG_BORINGSSL_CRYPTO), y)
+dirs+=third_party/boringssl/common
+dirs+=crypto
+endif
 common_dirs=util
 
 ifeq ($(custom-ro_objs-y),)
@@ -352,6 +424,7 @@ def_all_deps+=ro
 endif
 all_deps?=$(def_all_deps)
 all: $(all_deps)
+compile-only: $(ro-objs) $(rw-objs)
 
 ro: override BLD:=RO
 ro: $(libsharedobjs_elf-y) $(out)/RO/$(PROJECT).RO.flat
diff --git a/Makefile.ide b/Makefile.ide
new file mode 100644
index 0000000000..a87ea0b809
--- /dev/null
+++ b/Makefile.ide
@@ -0,0 +1,143 @@
+# -*- makefile -*-
+# vim: set filetype=make :
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Embedded Controller firmware build system - IDE support
+#
+# One caveat with this approach is that we still don't capture modified make
+# variables that are associated with a specific build target, like the following:
+#
+# $(out)/RW/common/blah.o: CFLAGS += -g
+#
+# This is because our compile commands json targets will not match this rule.
+
+# If env EXTERNAL_TRUNK_PATH is defined, we use this to build the
+# absolute path to the ec directory. Otherwise, we just take the abspath of ".".
+ide-ec-path-ext = \
+	$(if $(EXTERNAL_TRUNK_PATH),$(EXTERNAL_TRUNK_PATH)/src/platform/ec)
+ide-ec-path-abs = $(abspath .)
+ide-ec-path = $(or $(ide-ec-path-ext),$(ide-ec-path-abs))
+
+# Clang doesn't support these GCC options.
+ide-filters = -mno-sched-prolog -fconserve-stack
+
+# The complete compile_commands.json targets.
+ide-compile-cmds-y                        = $(out)/RW/compile_commands.json
+ide-compile-cmds-$(CONFIG_FW_INCLUDE_RO) += $(out)/RO/compile_commands.json
+ide-compile-cmds-y                       += $(out)/util/compile_commands.json
+
+# All individual <src_file>.compile_cmds.json targets.
+ide-rw-objs = $(rw-objs:.o=.compile_cmd.json)
+ide-ro-objs = $(ro-objs:.o=.compile_cmd.json)
+
+ide-build-utils    = $(build-utils:=.compile_cmd.json)
+ide-host-utils     = $(host-utils:=.compile_cmd.json)
+ide-host-utils-cxx = $(host-utils-cxx:=.compile_cmd.json)
+
+ide-utils = $(ide-build-utils) $(ide-host-utils) $(ide-host-utils-cxx)
+
+# The all-ide-compile-cmds target takes about 2 minutes using 8 cores when all
+# work is replaced by the |true| command. Thus, the build system itself
+# takes 2m independent of the text manipulation.
+.PHONY: all-ide-compile-cmds
+all-ide-compile-cmds: $(foreach b, $(BOARDS), ide-compile-cmds-$(b))
+ide-compile-cmds-%:
+	$(MAKE) BOARD=$* V=$(V) ide-compile-cmds
+
+.PHONY: ide-compile-cmds
+ide-compile-cmds: $(ide-compile-cmds-y)
+
+# All but the last file/json-object need to have a trailing comma.
+#
+# The first sed line prepends 4 spaces to all lines and then adds a
+# comma + implicit-newline to the end of the last line of the file.
+# The second sed line prepends 4 spaces to all lines and then adds an
+# implicit new line.
+cmd_combine_compile_cmd_json =                                                 \
+	printf '[\n'                                                      >$@ ;\
+	echo $^ | xargs -n1 | head -n-1 | xargs -n1 sed 's/^/    /;$$s/$$/,/'  \
+									 >>$@ ;\
+	sed 's/^/    /' $(lastword $^)                                   >>$@ ;\
+	printf ']\n'                                                     >>$@ ;
+
+$(out)/RW/compile_commands.json: override BLD := RW
+$(out)/RW/compile_commands.json: private objs := $(rw-objs)
+$(out)/RW/compile_commands.json: $(ide-rw-objs)
+$(out)/RW/compile_commands.json: $(ide-utils)
+	$(call quiet,combine_compile_cmd_json,COMBINE)
+$(out)/RO/compile_commands.json: override BLD := RO
+$(out)/RO/compile_commands.json: private objs := $(ro-objs)
+$(out)/RO/compile_commands.json: $(ide-ro-objs)
+$(out)/RO/compile_commands.json: $(ide-utils)
+	$(call quiet,combine_compile_cmd_json,COMBINE)
+$(out)/util/compile_commands.json: $(ide-utils)
+	$(call quiet,combine_compile_cmd_json,COMBINE)
+
+# Quote all words and add a comma between words.
+# The quotes are applied as \", so that they will escape shell removal.
+#
+# $(1) - The space separated list of words.
+ide-comma = ,
+ide-space = $() $()
+ide-esc-quoted = $(patsubst %,\"%\",$(1))
+cmd_json_list = $(subst $(ide-space),$(ide-comma)$(ide-space),$(ide-esc-quoted))
+
+# Replace any ".compile_cmd.json" with ".o" and filter out $(ide-filters) words.
+# The replace is needed because we are invoking build commands from within our
+# make rules that have targets set to files of type .compile_cmd.json.
+# The compile commands will use special variables that pull this name into
+# the command.
+#
+# $(1) - The compilation command.
+# $(2) - The original target extension, like ".o" or "".
+cmd_rep_filter = $(subst .compile_cmd.json,$(2),$(filter-out $(ide-filters),$(1)))
+
+# Form a compile command JSON block.
+#
+# $(1) - Used by quiet function, but it is this command name.
+# $(2) - Used by quiet function, but it is the pretty action label.
+# $(3) - The compilation command to place in the JSON blob.
+# $(4) - The original target extension, like ".o" or "".
+# $(5) - The source file this compile command applies to.
+cmd_to_compile_cmd_json =                                                      \
+	printf '{\n'                                                     >$@  ;\
+	printf '    "arguments": [\n'                                   >>$@  ;\
+	printf '        %s\n'                                                  \
+	  $(call cmd_json_list,$(call cmd_rep_filter,$(3),$(4)))        >>$@  ;\
+	printf '    ],\n'                                               >>$@  ;\
+	printf '    "directory": "$(ide-ec-path)",\n'                   >>$@  ;\
+	printf '    "file": "$(5)"\n'                                   >>$@  ;\
+	printf '}\n'                                                    >>$@  ;
+
+# Disable ccache, since this is only going to control whether the ccache
+# executable shows in the compile_commands.json file.
+%.compile_cmd.json: CCACHE :=
+
+$(out)/RO/%.compile_cmd.json:%.c
+	$(call quiet,to_compile_cmd_json,JSON   ,$(cmd_c_to_o),.o,$<)
+$(out)/RW/%.compile_cmd.json:%.c
+	$(call quiet,to_compile_cmd_json,JSON   ,$(cmd_c_to_o),.o,$<)
+
+$(out)/RO/%.compile_cmd.json:%.cc
+	$(call quiet,to_compile_cmd_json,JSON   ,$(cmd_cxx_to_o),.o,$<)
+$(out)/RW/%.compile_cmd.json: %.cc
+	$(call quiet,to_compile_cmd_json,JSON   ,$(cmd_cxx_to_o),.o,$<)
+
+$(out)/RO/%.compile_cmd.json:%.S
+	$(call quiet,to_compile_cmd_json,JSON   ,$(cmd_c_to_o),.o,$<)
+$(out)/RW/%.compile_cmd.json:%.S
+	$(call quiet,to_compile_cmd_json,JSON   ,$(cmd_c_to_o),.o,$<)
+
+$(ide-build-utils): $(out)/%.compile_cmd.json:$(build-srcs)
+	$(call quiet,to_compile_cmd_json,JSON   ,$(cmd_c_to_build),\
+		$(EMPTY),$*.c)
+
+$(ide-host-utils): $(out)/%.compile_cmd.json:$(host-srcs)
+	$(call quiet,to_compile_cmd_json,JSON   ,$(cmd_c_to_host),\
+		$(EMPTY),$*.c)
+
+$(ide-host-utils-cxx): $(out)/%.compile_cmd.json:$(host-srcs-cxx)
+	$(call quiet,to_compile_cmd_json,JSON   ,$(cmd_cxx_to_host),\
+		$(EMPTY),$*.cc)
diff --git a/Makefile.rules b/Makefile.rules
index e8c9ebec62..16c24e16f7 100644
--- a/Makefile.rules
+++ b/Makefile.rules
@@ -1,6 +1,6 @@
 # -*- makefile -*-
 # vim: set filetype=make :
-# Copyright 2012 The Chromium OS Authors. All rights reserved.
+# Copyright 2012 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -10,12 +10,6 @@
 FLATSIZE_FILE ?= .sizes.txt
 BUILD_DIR := $(firstword $(subst /, ,$(out)))
 
-build-utils := $(foreach u,$(build-util-bin),$(out)/util/$(u))
-host-utils := $(foreach u,$(host-util-bin),$(out)/util/$(u))
-build-art := $(foreach u,$(build-util-art),$(out)/$(u))
-build-srcs := $(foreach u,$(build-util-bin),$(sort $($(u)-objs:%.o=util/%.c) $(wildcard util/$(u).c)))
-host-srcs := $(foreach u,$(host-util-bin),$(sort $($(u)-objs:%.o=util/%.c) $(wildcard util/$(u).c)))
-
 # Don't do a build test on the following boards:
 skip_boards = OWNERS cr50 host
 boards := $(filter-out $(skip_boards),$(notdir $(wildcard board/* private*/board/*)))
@@ -34,25 +28,30 @@ _dir_create := $(foreach d,$(dirs) $(dirs-y),\
 # Note: if cmd_* includes a $(MAKE) invocation, use the '+' prefix
 # to inherit parallel make execution: "+$(call quiet,...)"
 ifeq ($(V),0)
+# V=0
 Q := @
 echo = echo -n;
 quiet = echo -n; $(cmd_$(1))
 silent = 1>/dev/null
 silent_err = 2>/dev/null
 MAKEFLAGS += --no-print-directory
-else
-echo = echo $(1);
-ifeq ($(V),)
+else ifeq ($(V),)
+# V=
 Q := @
-quiet = @echo '  $(2)' $(patsubst $(out)/%,%,$@) ; $(cmd_$(1))
+echo = echo $(1);
+echo-cmd = $(if $(quiet_cmd_$(1)), \
+		$(quiet_cmd_$(1)), \
+		$(2) $(patsubst $(out)/%,%,$@))
+quiet = @echo ' $(echo-cmd)' ; $(cmd_$(1))
 silent = 1>/dev/null
 silent_err = 2>/dev/null
 MAKEFLAGS += --no-print-directory
 else
+# V=*
 Q :=
+echo = echo $(1);
 quiet = $(cmd_$(1))
 endif
-endif
 
 # Provide an option to use a consistent ec_version.h file when
 # compiling, which is useful to verify that a commit does not modify
@@ -87,15 +86,24 @@ cmd_elf_to_hex = $(OBJCOPY) -O ihex $< $@
 cmd_bin_to_hex = $(OBJCOPY) -I binary -O ihex \
 	--change-addresses $(_program_memory_base) $^ $@
 cmd_smap = $(NM) $< | sort > $@
-cmd_elf = $(CC) $(objs) $(libsharedobjs_elf-y) $(LDFLAGS) \
+cmd_elf = $(COMPILER) $(objs) $(libsharedobjs_elf-y) $(LDFLAGS) \
 	-o $@ -Wl,-T,$< -Wl,-Map,$(patsubst %.elf,%.map,$@)
+ifeq ($(cc-name),gcc)
+cmd_elf+= -flto-partition=one
+endif
+ifneq ($(MEMSIZE_FLAGS),)
+cmd_elf+= $(MEMSIZE_FLAGS) >$@.memsize.txt
+endif
+
 cmd_fuzz_exe = $(CXX) $^ $(HOST_TEST_LDFLAGS) $(LDFLAGS_EXTRA) -o $@
 cmd_run_fuzz = build/host/$*/$*.exe -seed=1 -runs=1 $(silent) \
 	$(silent_err) || (echo "Test $* failed!" && false)
-cmd_exe = $(CC) $(ro-objs) $(HOST_TEST_LDFLAGS) $(LDFLAGS_EXTRA) -o $@
-cmd_c_to_o = $(CC) $(C_WARN) $(CFLAGS) -MMD -MP -MF $@.d -c $< \
+cmd_exe = $(CXX) $(ro-objs) $(HOST_TEST_LDFLAGS) $(LDFLAGS_EXTRA) -o $@
+cmd_c_to_o = $(CC) -std=gnu11 $(C_WARN) $(CFLAGS) -MMD -MP -MF $@.d -c $< \
+		-MT $(@D)/$(@F) -o $(@D)/$(@F)
+cmd_c_to_s = $(CC) -S $(C_WARN) $(CFLAGS) -fno-lto -MMD -MP -MF $@.d -c $< \
 		-MT $(@D)/$(@F) -o $(@D)/$(@F)
-cmd_cxx_to_o = $(CXX) -std=c++11 $(CFLAGS) $(CXXFLAGS) -MMD -MP -MF $@.d -c $< \
+cmd_cxx_to_o = $(CXX) -std=gnu++17 $(CFLAGS) $(CXXFLAGS) -MMD -MP -MF $@.d -c $< \
 		      -MT $(@D)/$(@F) -o $(@D)/$(@F)
 cmd_c_to_build = $(BUILDCC) $(BUILD_CFLAGS) \
 	         $(sort $(foreach c,$($(*F)-objs),util/$(c:%.o=%.c)) $(wildcard $*.c)) \
@@ -105,11 +113,12 @@ cmd_c_to_vif = $(BUILDCC) $(BUILD_CFLAGS) $(STANDALONE_FLAGS) \
 		-MMD -MF $@.d -c $< -flto -MT $@ -o $@
 cmd_c_to_host = $(HOSTCC) $(HOST_CFLAGS) -MMD -MF $@.d -MT $@ -o $@ \
 	         $(sort $(foreach c,$($(*F)-objs),util/$(c:%.o=%.c)) $(wildcard $*.c)) $(HOST_LDFLAGS)
-cmd_cxx_to_host = $(HOSTCXX) -std=c++0x $(COMMON_WARN) $(HOST_CXXFLAGS)\
-	-I ./$($(notdir $@)_ROOT) -o $@ $(filter %.cc,$^) $($(notdir $@)_LIBS)
+cmd_cxx_to_host = $(HOSTCXX) -std=gnu++17 $(HOST_CXXFLAGS) \
+		-MMD -MF $@.d -MT $@ -o $@ \
+		$(sort $(foreach c,$($(*F)-objs),util/$(c:%.o=%.cc)) $(wildcard $*.cc)) $(HOST_LDFLAGS)
 cmd_o_to_a = $(AR) rcs $@ $^
 cmd_host_test = $(MAKE) BOARD=host PROJECT=$* \
-	V=$(V) out=build/host/$* TEST_BUILD=y EMU_BUILD=y CROSS_COMPILE= \
+	V=$(V) out=build/host/$* TEST_BUILD=y EMU_BUILD=y \
 	$(if $(TEST_SCRIPT),TEST_SCRIPT=$(TEST_SCRIPT)) $(TEST_FLAG) \
 	build/host/$*/$*.exe
 cmd_coverage_test = $(subst build/host,build/coverage,$(cmd_host_test))
@@ -118,12 +127,13 @@ cmd_run_coverage_test = ./util/run_host_test --coverage $* $(silent)
 # generate new version.h, compare if it changed and replace if so
 cmd_version = ./util/getversion.sh > $@.tmp && \
 	cmp -s $@.tmp $@ && rm -f $@.tmp || mv $@.tmp $@
-cmd_vif = $(out)/util/genvif -b $(BOARD) -o $(out)
+cmd_vif = $(out)/util/genvif -b $(BOARD) -o $(out) \
+	  -v board/$(BOARD)/vif_override.xml
 cmd_mv_from_tmp = mv $(out)/$*.bin.tmp $(out)/$*.bin
 cmd_extractrw-y = dd if=$(out)/$(PROJECT).bin.tmp of=$(out)/$(PROJECT).RW.bin \
 	       bs=1 count=$(_rw_size) skip=$(_rw_off) $(silent_err)
 cmd_copyrw-y = cd $(out) && cp RW/$(PROJECT).RW.flat RW/$(PROJECT).RW.bin
-cmd_sharedlib_elf = $(CC) $(libsharedobjs_deps) \
+cmd_sharedlib_elf = $(COMPILER) $(libsharedobjs_deps) \
 	-Wl,-T,common/ec.$(SHOBJLIB).ld $(LDFLAGS) \
 	-o $(out)/$(SHOBJLIB)/$(SHOBJLIB).elf \
 	-Wl,-Map,$(out)/$(SHOBJLIB)/$(SHOBJLIB).map
@@ -143,11 +153,6 @@ cmd_emmc_bootblock = $(out)/util/gen_emmc_transfer_data \
 cmd_ipi_table = $(out)/util/gen_ipi_table $@
 cmd_cp_script = cp "$<" "$@" && chmod +x "$@"
 
-cmd_libcryptoc_make = $(MAKE) -C $(CRYPTOCLIB) \
-	obj=$(realpath $(out))/cryptoc \
-	SUPPORT_UNALIGNED=1
-cmd_libcryptoc = $(cmd_libcryptoc_make) -q || $(cmd_libcryptoc_make)
-
 # commands for RSA signature: rwsig does not need to sign the whole image
 # (it signs the RW part separately). usbpd1 type needs to sign the final image.
 ifeq ($(CONFIG_RWSIG_TYPE_RWSIG),)
@@ -163,7 +168,7 @@ cmd_rsasign_rwsig = futility sign --type rwsig \
 
 # commands to build optional xref files
 cmd_deps_to_list = cat $(deps) | tr -d ':\\' | tr ' ' '\012' \
-	| egrep '\.[chS]$$' | sort | uniq > $@
+	| grep -E '\.[chS]$$' | sort | uniq > $@
 cmd_etags = etags -o $@ $(shell cat $<)
 cmd_ctags = ctags -o $@ $(shell cat $<)
 targ_if_prog = $(if $(shell which $(1) 2>/dev/null),$(2),)
@@ -198,8 +203,13 @@ build_boards: | $(FAILED_BOARDS_DIR)
 	@rm -f $(FAILED_BOARDS_DIR)/*
 	$(MAKE) try_build_boards
 
+.PHONY: check_undef
+check_undef:
+	$(call quiet,check_undef)
+
 .PHONY: buildall_only
-buildall_only: build_boards build_cros_ec_commands
+buildall_only: build_boards build_cros_ec_commands check_undef
+	$(MAKE) BOARD=host utils
 	$(MAKE) build_cts
 	$(MAKE) buildfuzztests
 
@@ -230,6 +240,48 @@ print-boards:
 	$(call cmd_pretty_print_list,\
 		$(sort $(boards)))
 
+# The zephyr path can be overridden on invocation, as in the following example:
+# $ make ZEPHYR_BASE=~/zephyr/main BOARD=dartmonkey
+ZEPHYR_BASE ?= $(abspath ../../../src/third_party/zephyr/main)
+export ZEPHYR_BASE
+
+ifeq ($(ALLOW_CONFIG),)
+
+# These are options defined by both ECOS and Zephyr. We need to tolerate this
+# rather than begging the user to drop them from config_allowed since when the
+# Zephyr Kconfig is not available (-I argument below does not point to the right
+# place), they will not be considered a problem.
+# You may add new options here if needed, although this should only occur if
+# Zephyr upstream happens to add the same option, since we are requiring new
+# ECOS options to have a corresponding Kconfig anyway.
+conflicting_options := \
+	ADC \
+	AUDIO_CODEC \
+	DAC \
+	DMA \
+	EEPROM \
+	I2C_BITBANG \
+	INA219 \
+	MPU \
+	PECI \
+	PS2 \
+	SMBUS \
+	SPI \
+	UART_CONSOLE
+
+cmd_check_allowed = ./util/kconfig_check.py -c ${config} \
+	 -a util/config_allowed.txt -p PLATFORM_EC_ -s "" \
+	 -I "${ZEPHYR_BASE}" \
+	 $(foreach opt,$(conflicting_options),-i $(opt)) check
+cmd_check_undef = ./util/kconfig_check.py -s "" -I "${ZEPHYR_BASE}" \
+	check_undef
+else
+cmd_check_allowed = true
+cmd_check_undef = true
+endif
+quiet_cmd_check_allowed = CHECK_ALLOWED ${config}
+quiet_cmd_check_undef = CHECK_UNDEF
+
 # Print any important notices at the end of the build.
 .PHONY: notice
 notice: $(config)
@@ -240,6 +292,7 @@ ifeq ($(TEST_BUILD),)
 	@echo "directory!  Otherwise, you won't be able to enter any commands."
 endif # not a TEST_BUILD
 endif # CONFIG_EXPERIMENTAL_CONSOLE=y
+	$(call quiet,check_allowed)
 
 proj-%: | $(FAILED_BOARDS_DIR)
 	@touch $(FAILED_BOARDS_DIR)/$*
@@ -266,13 +319,21 @@ hex: $(hex-y)
 utils-art: $(build-art)
 
 .PHONY: utils-host
-utils-host: $(host-utils)
+ifeq ($(BOARD),host)
+utils-host: $(host-utils) $(host-utils-cxx)
+else
+utils-host:
+	$(error Building utils-host not supported when BOARD is not "host")
+endif
 
 .PHONY: utils-build
 utils-build: $(build-utils)
 
 .PHONY: utils
-utils: utils-host utils-build utils-art
+utils: utils-build utils-art
+ifeq ($(BOARD),host)
+utils: utils-host
+endif
 
 # On board test binaries
 test-targets=$(foreach t,$(test-list-y),test-$(t))
@@ -334,8 +395,7 @@ run-fuzz-test-targets=$(foreach t,$(fuzz-test-list-host),run-$(t))
 
 $(fuzz-test-targets): TEST_FLAG=TEST_FUZZ=y TEST_ASAN=$(TEST_ASAN) \
 	TEST_MSAN=$(TEST_MSAN) TEST_UBSAN=$(TEST_UBSAN) \
-	CROSS_COMPILE=$(shell echo $(HOSTCC) | grep -v ccache | \
-		sed -e 's/[^-]*$$//')
+	CROSS_COMPILE=$(HOST_CROSS_COMPILE)
 $(fuzz-test-targets): host-%: | $(FAILED_BOARDS_DIR)
 	@touch $(FAILED_BOARDS_DIR)/test-$*
 	+$(call quiet,host_test,BUILD  )
@@ -359,7 +419,7 @@ hosttests: $(host-test-targets)
 runhosttests: TEST_FLAG=TEST_HOSTTEST=y
 runhosttests: $(run-test-targets)
 runfuzztests: $(run-fuzz-test-targets)
-runtests: runhosttests runfuzztests
+runtests: runhosttests runfuzztests run-genvif_test
 
 # Automatically enumerate all suites.
 cts_excludes := common
@@ -394,14 +454,21 @@ $(foreach b, $(cts_boards), \
 	) \
 )
 
+cov-boards=lazor volteer
 cov-test-targets=$(foreach t,$(cov-test-list-host),build/coverage/$(t).info)
+cov-initial-targets=$(foreach t,$(cov-boards),build/coverage/initial-$(t).info)
 bldversion=$(shell (./util/getversion.sh ; echo VERSION) | $(CPP) -P -)
 
-# lcov fails when multiple instances run at the same time.
-# We need to run them sequentially by using flock
-cmd_lcov=flock /tmp/ec-lcov-lock -c "lcov -q -o $@ -c -d build/coverage/$*"
-cmd_report_cov=genhtml -q -o build/coverage/coverage_rpt -t \
-	       "EC Unittest "$(bldversion) $^
+cmd_lcov=lcov --rc lcov_branch_coverage=1 --gcov-tool \
+	$(HOSTGCOV) -q -o $@ -c -d build/coverage/$* -t $* \
+	--exclude '*/ec/test/*' --exclude '*/ec/include/tests/*'
+cmd_lcov-initial=lcov --rc lcov_branch_coverage=1 --gcov-tool \
+	$(GCOV) -q -o $@ -c -d build/coverage/initial-$* \
+	-i -t $* --exclude '*/ec/test/*' --exclude '*/ec/include/tests/*'
+cmd_merge_cov=lcov --rc lcov_branch_coverage=1 -o build/coverage/lcov.info \
+	$(foreach info,$^,-a ${info})
+cmd_report_cov=genhtml --branch-coverage -q -o build/coverage/coverage_rpt -t \
+	       "EC Unittest "$(bldversion) -s $^
 
 # Unless V is set to 0 we always want the 'size:' target to report its output,
 # there is no point in generating a short form command trace when calculating
@@ -411,9 +478,9 @@ ifeq ($(V),0)
 cmd_size=
 else
 cmd_size=$(Q)awk '\
-  /__flash_used =/ {flash_used = strtonum($$1)} \
-  /^FLASH/ {flash_size = strtonum($$3)} \
-  /__ram_free =/ {ram_free = strtonum($$1)} \
+  /__flash_used/ {flash_used = strtonum("0x" $$1)} \
+  /__flash_size/ {flash_size = strtonum("0x" $$1)} \
+  /__ram_free/ {ram_free = strtonum("0x" $$1)} \
   END {room_free = flash_size - flash_used; \
        print ram_free > "$(out)/$(1)/space_free_ram.txt"; \
        printf "  *** "; \
@@ -423,7 +490,7 @@ cmd_size=$(Q)awk '\
        } \
        printf ("%s bytes in RAM still available on $(BOARD) $(1) ****\n", \
            ram_free) \
-  }' $(out)/$(1)/$(PROJECT).$(1).map
+  }' $(out)/$(1)/$(PROJECT).$(1).smap
 endif
 
 # List the smallest free flash spaces
@@ -437,12 +504,21 @@ cmd_stats= \
 	printf "%-10s: %6d\n" $$board $$size; \
   done
 
+.DELETE_ON_ERROR: build/coverage/initial-%.info build/coverage/%.info
+build/coverage/initial-%.info:
+	$(MAKE) TEST_COVERAGE=y BOARD=$* compile-only
+	$(call quiet,lcov-initial,COV    )
 build/coverage/%.info: run-coverage-%
 	$(call quiet,lcov,COV    )
 
-.PHONY: coverage
+.PHONY: coverage test-coverage
 coverage: TEST_FLAG=TEST_COVERAGE=y
-coverage: $(cov-test-targets)
+coverage: $(cov-test-targets) $(cov-initial-targets)
+	$(call quiet,merge_cov,MERGE  )
+	$(call quiet,report_cov,REPORT )
+test-coverage: TEST_FLAG=TEST_COVERAGE=y
+test-coverage: $(cov-test-targets)
+	$(call quiet,merge_cov,MERGE  )
 	$(call quiet,report_cov,REPORT )
 
 $(out)/libec.a: $(ro-objs)
@@ -463,7 +539,7 @@ $(out)/%.bin: $(out)/%.obj
 			$(call quiet,copyrw-y,COPY_RW))
 	$(call quiet,mv_from_tmp,MV     )
 
-$(out)/$(BOARD)_vif.txt: $(out)/util/genvif
+$(out)/$(BOARD)_vif.xml: $(out)/util/genvif board/$(BOARD)/vif_override.xml
 	$(call quiet,vif,VIF    )
 
 flat-y := $(out)/RW/$(PROJECT).RW.flat
@@ -554,6 +630,11 @@ $(out)/RO/%.o:%.c
 $(out)/RW/%.o:%.c
 	$(call quiet,c_to_o,CC     )
 
+$(out)/RO/%.s:%.c
+	$(call quiet,c_to_s,CC     )
+$(out)/RW/%.s:%.c
+	$(call quiet,c_to_s,CC     )
+
 $(out)/RO/%.o:%.cc
 	$(call quiet,cxx_to_o,CXX    )
 $(out)/RW/%.o:%.cc
@@ -616,6 +697,9 @@ $(build-utils): $(out)/%:$(build-srcs)
 $(host-utils): $(out)/%:$(host-srcs)
 	$(call quiet,c_to_host,HOSTCC )
 
+$(host-utils-cxx): $(out)/%:$(host-srcs-cxx)
+	$(call quiet,cxx_to_host,HOSTCXX )
+
 $(out)/cscope.files: $(out)/$(PROJECT).bin
 	$(call quiet,deps_to_list,SH     )
 
@@ -642,14 +726,14 @@ $(npcx-monitor-fw-bin):$(npcx-monitor-fw).c npx-monitor-dir
 	$(Q)$(OBJCOPY) -O binary $(out)/$(npcx-monitor-fw).elf $@
 
 $(out)/$(npcx-monitor-hdr)_ro.o:$(npcx-monitor-hdr).c npx-monitor-dir
-	$(Q)$(CC) $(CFLAGS) -DSECTION_IS_RO=$(EMPTY) -MMD -c $< -MT $@ -o $@
+	$(Q)$(CC) $(CFLAGS) -DSECTION_IS_RO=$(EMPTY) -MMD -fno-lto -c $< -MT $@ -o $@
 
 $(npcx-monitor-hdr-ro-bin):$(out)/$(npcx-monitor-hdr)_ro.o
 	$(if $(V),,@echo '  EXTBIN ' $(subst $(out)/,,$@) ; )
 	$(Q)$(OBJCOPY) -O binary $< $@
 
 $(out)/$(npcx-monitor-hdr)_rw.o:$(npcx-monitor-hdr).c npx-monitor-dir
-	$(Q)$(CC) $(CFLAGS) -MMD -c $< -MT $@ -o $@
+	$(Q)$(CC) $(CFLAGS) -MMD -fno-lto -c $< -MT $@ -o $@
 
 $(npcx-monitor-hdr-rw-bin):$(out)/$(npcx-monitor-hdr)_rw.o
 	$(if $(V),,@echo '  EXTBIN ' $(subst $(out)/,,$@) ; )
@@ -676,6 +760,14 @@ flash_ec: $(out)/ec.bin
 flash_dfu: $(out)/ec.bin
 	sudo ./$(BDIR)/dfu $(out)/ec.bin
 
+.PHONY: print-all-baseboards
+print-all-baseboards: $(foreach b, $(BOARDS), print-baseboard-$(b))
+print-baseboard-%:
+	@$(MAKE) BOARD=$* V=$(V) print-one-baseboard
+.PHONY: print-one-baseboard
+print-one-baseboard:
+	@echo "${BOARD}=${BASEBOARD}"
+
 # Deprecated, use print-make-vars instead
 .PHONY: print-baseboard
 print-baseboard:
@@ -732,41 +824,57 @@ endif
 .PHONY: help
 help:
 	@echo "Google Chromium EC build"
+	@echo ""
 	@echo "Common Targets:"
 	@echo "  all   [BOARD=]       - Build a single board (Default target)"
 	@echo "  clean [BOARD=]       - Clean a single board"
-	@echo "  buildall             - Build and test all boards"
+	@echo "  buildall             - Build all boards and build/run host unit tests"
+	@echo "  buildall_only        - Build all boards and host unit tests"
+	@echo "  build_boards         - Build all boards"
 	@echo "  clobber              - Clean all boards"
 	@echo "  proj-<boardname>     - Build a single board (similar to 'all BOARD=boardname')"
 	@echo "  savesizes            - Save the filesizes of currently built boards for comparison"
 	@echo "  newsizes             - Compare previously saved filesizes against new sizes"
-	@echo "  utils                - Build all host utilities"
+	@echo "  utils [BOARD=]       - Build all host side utilities"
+	@echo "  dis   [BOARD=]       - Generate the complete disassembly of the RO and RW images"
+	@echo "  hex   [BOARD=]       - Generate an Intel hex formated output binary"
 	@echo ""
-	@echo "  tests [BOARD=]       - Build all unit tests for a specific board"
+	@echo "  tests [BOARD=]       - Build all on-device unit tests for a specific board"
 	@echo "  hosttests            - Build all host unit tests"
 	@echo "  runhosttests         - Build and run all host unit tests"
 	@echo "  coverage             - Build and run all host unit tests for code coverage"
 	@echo "  buildfuzztests       - Build all host fuzzers"
 	@echo "  runfuzztests         - Build and run all host fuzzers for one round"
+	@echo "  analyzestack [BOARD=]- Run max stack size analysis"
 	@echo ""
 	@echo "  flash     [BOARD=]   - Use OpenOCD to flash the latest image"
 	@echo "  flash_ec  [BOARD=]   - Use flash_ec to flash the latest image"
 	@echo "  flash_dfu [BOARD=]   - Use DFU to flash the latest image"
 	@echo ""
-	@echo "  print-tests          - Prints all device specific test targets"
-	@echo "  print-host-tests     - Prints all host test targets"
-	@echo "  print-host-fuzzers   - Prints all host fuzz targets"
-	@echo "  print-boards         - Prints all boards"
-	@echo "  print-configs  [BOARD=]      - Print CONFIG_* options for the target board"
-	@echo "  print-defines  [BOARD=]      - Print forced defines passed to the compiler"
-	@echo "  print-includes [BOARD=]      - Print include paths passed to the compiler"
+	@echo "  print-tests     [BOARD=]     - Print on-device test targets"
+	@echo "  print-host-tests             - Print all host unit test targets"
+	@echo "  print-host-fuzzers           - Print all host fuzz targets"
+	@echo "  print-boards                 - Print all boards"
+	@echo "  print-configs   [BOARD=]     - Print CONFIG_* options for the target board"
+	@echo "  print-defines   [BOARD=]     - Print forced defines passed to the compiler"
+	@echo "  print-includes  [BOARD=]     - Print include paths passed to the compiler"
+	@echo "  print-baseboard [BOARD=]     - Print include paths passed to the compiler"
+	@echo "  print-make-vars [BOARD=]     - Print chip/core/board make variables for a board"
+	@echo ""
 	@echo "Common Variables:"
 	@echo "  V=1                  - Show make output"
 	@echo "  BOARD=               - Set the board name to build (Default is $(BOARD))"
+	@echo "  STATIC_VERSION=1     - Force a constant version string for reproducable builds"
+	@echo "  BUILDCC_PREFIX=      - Set the compiler prefix for the system doing "
+	@echo "     the build (defaults to 'x86_64-pc-linux-gnu-')."
 	@echo "  CROSS_COMPILE=       - Set the compiler for the board"
 	@echo "  CROSS_COMPILE_arch=  - Set the compiler for arch"
 	@echo "     The board picks its CROSS_COMPILE_arch if CROSS_COMPILE is not set."
 	@echo "     arch may be one of 'arm', 'i386', 'nds32'."
+	@echo "  HOST_CROSS_COMPILE=  - Set the compiler for the target platform on top of"
+	@echo "     the EC. For example, this may be 32-bit x86 linux ('i686-pc-linux-gnu-'),"
+	@echo "     64-bit x86 linux ('x86_64-pc-linux-gnu-'), or maybe 64-bit ARM linux"
+	@echo "     ('aarch64-cros-linux-gnu-')."
 	@echo "Example:"
 	@echo "  make BOARD=reef CROSS_COMPILE_arm='arm-eabi-'"
 
@@ -874,6 +982,12 @@ build_cros_ec_commands: $(out_cros_ec_commands)
 $(out_cros_ec_commands): include/ec_commands.h util/make_linux_ec_commands_h.sh
 	util/make_linux_ec_commands_h.sh $< $@
 
+# Include IDE configurations targets.
+include Makefile.ide
+
+# Pull in special rules/targets for third_party software
+-include third_party/rules.mk
+
 .SECONDARY:
 
 -include $(deps)
diff --git a/Makefile.toolchain b/Makefile.toolchain
index 01252ba14f..a4ed9fb1de 100644
--- a/Makefile.toolchain
+++ b/Makefile.toolchain
@@ -1,12 +1,15 @@
 # -*- makefile -*-
-# Copyright 2012 The Chromium OS Authors. All rights reserved.
+# Copyright 2012 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
-# Toolchain configuration build system
-#
-
 # Toolchain configuration
+#
+# BUILD - Refers to the system doing the "build".
+#         For example, you would compile servo_ectool to run on your local
+#         build machine.
+# HOST  - Refers to target platform on top of the EC.
+#         For example, you would compile ectool to run on the Chrome OS device.
 
 min_make_version:=3.82
 make_version_ok:=$(filter $(min_make_version), \
@@ -20,34 +23,125 @@ ifneq ($(TEST_FUZZ)$(TEST_ASAN)$(TEST_MSAN)$(TEST_UBSAN),)
 CC=clang
 endif
 
+# When set to 1, use the subset of the C standard library implemented in EC
+# (the "builtin" directory).
+# When set to 0, link against the toolchain's implementation of the C standard
+# library.
+USE_BUILTIN_STDLIB:=1
+
+# When set to 1, link with the C++ compiler.
+# When set to 0, link with the C compiler.
+USE_CXX_COMPILER:=0
+
+# Boards that compile with clang by default.
+# We can't use a config for this since the config generation uses the compiler.
+CLANG_BOARDS:= \
+	bloonchipper \
+	dartmonkey \
+	hatch_fp \
+	helipilot \
+	nami_fp \
+	nocturne_fp \
+	nucleo-dartmonkey \
+	nucleo-h743zi \
+	nucleo-f412zg \
+
+ifeq ($(filter $(BOARD), $(CLANG_BOARDS)), $(BOARD))
+CC=clang
+USE_BUILTIN_STDLIB:=0
+USE_CXX_COMPILER:=1
+# b/144957935: Generate exception on signed integer overflow.
+COMMON_WARN+=-ftrapv
+endif
+
+ifeq ($(USE_CXX_COMPILER), 1)
+COMPILER=$(CXX)
+else
+COMPILER=$(CC)
+endif
+
+# Set the prefix for the compiler if specified (e.g., "x86_64-pc-linux-gnu-").
+ifeq ($(origin BUILDCC_PREFIX),undefined)
+# If building with Portage use the environment variable it provides.
+# https://wiki.gentoo.org/wiki/Embedded_Handbook/General/Introduction#Environment_variables
+ifneq ($(CBUILD),)
+BUILDCC_PREFIX:=$(CBUILD)-
+else
+BUILDCC_PREFIX:=x86_64-pc-linux-gnu-
+endif
+endif
+
 # Extract cc-name
-cc-name:=$(shell $(CC) -v 2>&1 | grep -q "clang version" && echo clang || echo gcc)
+cc-name:=$(shell $(BUILDCC_PREFIX)$(CC) -v 2>&1 | grep -q "clang version" && echo clang || echo gcc)
+
+# Assume we want to use same compiler for both C and C++
+ifeq ($(cc-name),gcc)
+cxx-name:=g++
+else
+cxx-name:=clang++
+endif
 
 # Try not to assume too much about optional tools and prefixes
 CCACHE:=$(shell which ccache 2>/dev/null)
 ifeq ($(origin HOST_CROSS_COMPILE),undefined)
-HOST_CROSS_COMPILE:=$(if $(shell which x86_64-pc-linux-gnu-gcc 2>/dev/null),x86_64-pc-linux-gnu-,)
+# If building with Portage use the environment variable it provides.
+# https://wiki.gentoo.org/wiki/Embedded_Handbook/General/Introduction#Environment_variables
+ifneq ($(CHOST),)
+HOST_CROSS_COMPILE:=$(CHOST)-
+else
+HOST_CROSS_COMPILE:=$(if $(shell which x86_64-pc-linux-gnu-$(cc-name) 2>/dev/null),x86_64-pc-linux-gnu-,)
+endif
 endif
 
 AR=$(CROSS_COMPILE)ar
 CC=$(CCACHE) $(CROSS_COMPILE)$(cc-name)
 CPP=$(CC) -E
-CXX=$(CROSS_COMPILE)clang++
+CXX=$(CROSS_COMPILE)$(cxx-name)
 LD=$(CROSS_COMPILE)ld
 NM=$(CROSS_COMPILE)nm
 OBJCOPY=$(CROSS_COMPILE)objcopy
 OBJDUMP=$(CROSS_COMPILE)objdump
 ADDR2LINE=$(CROSS_COMPILE)addr2line
 PKG_CONFIG?=pkg-config
-BUILDCC?=$(CCACHE) gcc
-HOSTCC?=$(CCACHE) $(HOST_CROSS_COMPILE)gcc
-HOSTCXX?=$(CCACHE) $(HOST_CROSS_COMPILE)g++
+BUILD_PKG_CONFIG?=$(PKG_CONFIG)
+BUILDCC?=$(CCACHE) $(BUILDCC_PREFIX)$(cc-name)
+HOSTCC?=$(CCACHE) $(HOST_CROSS_COMPILE)$(cc-name)
+HOSTCXX?=$(CCACHE) $(HOST_CROSS_COMPILE)clang++
+HOST_PKG_CONFIG?=$(HOST_CROSS_COMPILE)pkg-config
 PROTOC?=protoc
+GCOV=$(CROSS_COMPILE)gcov
+ifeq ($(cc-name),gcc)
+HOSTGCOV=$(HOST_CROSS_COMPILE)gcov
+else
+HOSTGCOV=$(CURDIR)/util/llvm-gcov.sh
+endif
 
-C_WARN = -Wstrict-prototypes -Wdeclaration-after-statement -Wno-pointer-sign
-COMMON_WARN = -Wall -Wundef -Werror -Werror-implicit-function-declaration \
+C_WARN = -Wstrict-prototypes -Wno-pointer-sign
+C_WARN += -Werror-implicit-function-declaration
+COMMON_WARN += -Wall -Wundef \
 	-Wno-trigraphs -Wno-format-security -Wno-address-of-packed-member \
-	-fno-common -fno-strict-aliasing -fno-strict-overflow
+	-fno-common -fno-strict-aliasing -fno-strict-overflow -Wimplicit-fallthrough
+# See https://www.chromium.org/chromium-os/build/c-exception-support
+COMMON_WARN+=-fno-exceptions -fno-unwind-tables -fno-asynchronous-unwind-tables
+
+ifndef ALLOW_WARNINGS
+COMMON_WARN+=-Werror
+ifeq ($(cc-name),clang)
+COMMON_WARN+=-Werror=uninitialized
+endif
+ifeq ($(cc-name),gcc)
+COMMON_WARN+=-Werror=maybe-uninitialized
+endif
+endif
+
+ifeq ($(cc-name),clang)
+# TODO(b/172020503): Re-enabling this warning requires a large CL.
+C_WARN+= -Wno-ignored-attributes
+# TODO(b/172020503): Re-enabling this warning requires the following large CLs:
+# https://crrev.com/c/3223973
+# https://crrev.com/c/3227261
+COMMON_WARN+= -Wno-unused-function
+endif
 
 UBSAN_FLAGS=-fsanitize=array-bounds,vla-bound \
 	-fno-sanitize=vptr \
@@ -57,8 +151,9 @@ CFLAGS_WARN = $(COMMON_WARN) $(C_WARN)
 CXXFLAGS_WARN = $(COMMON_WARN)
 CFLAGS_DEBUG= -g
 CFLAGS_DEBUG+=$(CFLAGS_DEBUG_CHIP)
-CFLAGS_INCLUDE=$(foreach i,$(includes),-I$(i) ) -I.
+CFLAGS_INCLUDE=$(foreach i,$(filter-out builtin, $(includes)),-I$(i) ) -I.
 CFLAGS_TEST=$(if $(TEST_BUILD),-DTEST_BUILD=$(EMPTY) \
+                               -DTEST_LEGACY_BUILD=$(EMPTY) \
                                -DTEST_TASKFILE=$(PROJECT).tasklist,) \
             $(if $(CTS_MODULE), $(CFLAGS_CTS)) \
             $(if $(EMU_BUILD),-DEMU_BUILD=$(EMPTY)) \
@@ -66,11 +161,11 @@ CFLAGS_TEST=$(if $(TEST_BUILD),-DTEST_BUILD=$(EMPTY) \
             $(if $(TEST_ASAN),-fsanitize=address) \
             $(if $(TEST_MSAN),-fsanitize=memory) \
             $(if $(TEST_UBSAN),$(UBSAN_FLAGS)) \
-            $(if $(TEST_FUZZ),-fsanitize=fuzzer-no-link \
-                       -fno-experimental-new-pass-manager -DTEST_FUZZ=$(EMPTY))
+            $(if $(TEST_FUZZ),-fsanitize=fuzzer-no-link -fno-PIE \
+		-DTEST_FUZZ=$(EMPTY))
 CFLAGS_COVERAGE=$(if $(TEST_COVERAGE),--coverage \
 				      -DTEST_COVERAGE=$(EMPTY),)
-CFLAGS_HOSTTEST=$(if $(TEST_HOSTTEST),-DTEST_HOSTTEST=$(EMPTY),)
+CFLAGS_HOSTTEST=$(if $(TEST_HOSTTEST),-DTEST_HOSTTEST=$(EMPTY),) -Iinclude/driver
 CFLAGS_DEFINE=-DOUTDIR=$(out)/$(BLD) -DCHIP=$(CHIP) -DBOARD_TASKFILE=$(_tsk_lst_file) \
               -DBOARD=$(BOARD) -DCORE=$(CORE) -DPROJECT=$(PROJECT) \
               -DCHIP_VARIANT=$(CHIP_VARIANT) -DCHIP_FAMILY=$(UC_CHIP_FAMILY) \
@@ -92,30 +187,46 @@ HOST_CPPFLAGS=$(CFLAGS_DEFINE) $(CFLAGS_INCLUDE) $(CFLAGS_TEST) \
 	 $(EXTRA_CFLAGS) $(CFLAGS_COVERAGE) $(CFLAGS_HOSTTEST) $(LATE_CFLAGS_DEFINE) \
 	 -DSECTION_IS_$(BLD)=$(EMPTY) -DSECTION=$(BLD) $(CPPFLAGS_$(BLD))
 ifneq ($(BOARD),host)
+CPPFLAGS+=-fno-PIC
+ifeq ($(USE_BUILTIN_STDLIB), 1)
 CPPFLAGS+=-ffreestanding -fno-builtin -nostdinc -nostdlib
 CPPFLAGS+=-Ibuiltin/
+endif
 else
 CPPFLAGS+=-Og
 endif
 CPPFLAGS+= -DCHROMIUM_EC=$(EMPTY)
 CFLAGS=$(CPPFLAGS) $(CFLAGS_CPU) $(CFLAGS_DEBUG) $(COMMON_WARN) $(CFLAGS_y)
-CFLAGS+= -ffunction-sections -fshort-wchar
+CFLAGS+= -ffunction-sections
 CFLAGS+= -fno-delete-null-pointer-checks
+CFLAGS+= -fno-PIC
 ifneq ($(cc-name),clang)
 CFLAGS+= -ffat-lto-objects
 CFLAGS+= -fconserve-stack
 endif
+CXXFLAGS=$(CXXFLAGS_WARN)
 CXXFLAGS+=-DPROTOBUF_INLINE_NOT_IN_HEADERS=0
+ifeq ($(USE_BUILTIN_STDLIB), 1)
+CPPFLAGS+=-DUSE_BUILTIN_STDLIB
+endif
 
+ifeq ($(LIBFTDI_NAME),)
 FTDIVERSION:=$(shell $(PKG_CONFIG) --modversion libftdi1 2>/dev/null)
 ifneq ($(FTDIVERSION),)
   LIBFTDI_NAME=ftdi1
 else
   LIBFTDI_NAME=ftdi
 endif
+endif
+
+LIBFTDIUSB_HOST_CFLAGS:=$(shell $(HOST_PKG_CONFIG) --cflags lib${LIBFTDI_NAME} libusb-1.0)
+LIBFTDIUSB_HOST_LDLIBS:=$(shell $(HOST_PKG_CONFIG) --libs   lib${LIBFTDI_NAME} libusb-1.0)
+
+LIBFTDIUSB_BUILD_CFLAGS:=$(shell $(BUILD_PKG_CONFIG) --cflags lib${LIBFTDI_NAME} libusb-1.0)
+LIBFTDIUSB_BUILD_LDLIBS:=$(shell $(BUILD_PKG_CONFIG) --libs   lib${LIBFTDI_NAME} libusb-1.0)
 
-LIBFTDIUSB_CFLAGS:=$(shell $(PKG_CONFIG) --cflags lib${LIBFTDI_NAME} libusb-1.0)
-LIBFTDIUSB_LDLIBS:=$(shell $(PKG_CONFIG) --libs   lib${LIBFTDI_NAME} libusb-1.0)
+LIBEC_HOST_CFLAGS:=$(shell $(HOST_PKG_CONFIG) --cflags libec)
+LIBEC_HOST_LDLIBS:=$(shell $(HOST_PKG_CONFIG) --libs libec)
 
 ifeq ($(TEST_FUZZ),y)
 LIBPROTOBUF_CFLAGS:=$(shell $(PKG_CONFIG) --cflags protobuf)
@@ -127,22 +238,37 @@ LIBPROTOBUF_MUTATOR_LDLIBS:=$(shell $(PKG_CONFIG) --libs libprotobuf-mutator) \
 	${LIBPROTOBUF_LDLIBS}
 endif
 
-BUILD_CFLAGS=$(LIBFTDIUSB_CFLAGS) $(BUILD_CPPFLAGS) -O3 $(CFLAGS_DEBUG)
+BUILD_CFLAGS=$(LIBFTDIUSB_BUILD_CFLAGS) $(BUILD_CPPFLAGS) -O3 $(CFLAGS_DEBUG)
 BUILD_CFLAGS+=$(CFLAGS_WARN)
 BUILD_CFLAGS+=-DCHROMIUM_EC=$(EMPTY)
 HOST_CFLAGS=$(HOST_CPPFLAGS) -O3 $(CFLAGS_DEBUG) $(CFLAGS_WARN) \
 	    -DHOST_TOOLS_BUILD=$(EMPTY)
-HOST_CFLAGS+=$(LIBFTDIUSB_CFLAGS)
+HOST_CFLAGS+=$(LIBFTDIUSB_HOST_CFLAGS)
 HOST_CFLAGS+=-DCHROMIUM_EC=$(EMPTY)
+HOST_CXXFLAGS=$(HOST_CFLAGS) -Wno-c99-designator
+HOST_CXXFLAGS+=$(LIBEC_HOST_CFLAGS)
 ifneq (${SYSROOT},)
   LDFLAGS_EXTRA+=--sysroot=${SYSROOT}
 endif
-LDFLAGS=-nostdlib -g -Wl,-X -Wl,--gc-sections -Wl,--build-id=none \
+LDFLAGS=-g -no-pie -Wl,-X -Wl,--gc-sections -Wl,--build-id=none \
 	$(LDFLAGS_EXTRA) $(CFLAGS_CPU)
-BUILD_LDFLAGS=$(LIBFTDIUSB_LDLIBS)
-HOST_LDFLAGS=$(LIBFTDIUSB_LDLIBS)
+ifeq ($(USE_BUILTIN_STDLIB), 1)
+LDFLAGS+=-nostdlib
+else
+LDFLAGS+=-lnosys
+endif
+MEMSIZE_FLAGS=
+ifeq ($(cc-name),gcc)
+MEMSIZE_FLAGS+=-Wl,--print-memory-usage
+endif
+BUILD_LDFLAGS=$(LIBFTDIUSB_BUILD_LDLIBS)
+HOST_LDFLAGS=$(LIBFTDIUSB_HOST_LDLIBS)
+ifneq (${HOST_SYSROOT},)
+  HOST_LDFLAGS+=--sysroot=${HOST_SYSROOT}
+endif
+HOST_LDFLAGS+=$(LIBEC_HOST_LDLIBS)
 HOST_TEST_LDFLAGS=-Wl,-T core/host/host_exe.lds -lrt -pthread -rdynamic -lm\
-		  -fuse-ld=bfd \
+		  -no-pie -flto\
 		  $(if $(TEST_COVERAGE), --coverage,) \
 		  $(if $(TEST_ASAN), -fsanitize=address) \
 		  $(if $(TEST_MSAN), -fsanitize=memory) \
diff --git a/PRESUBMIT.cfg b/PRESUBMIT.cfg
index 5d83f2b980..c925185270 100644
--- a/PRESUBMIT.cfg
+++ b/PRESUBMIT.cfg
@@ -1,22 +1,41 @@
 [Hook Overrides]
+black_check: true
+clang_format_check: true
 branch_check: true
 checkpatch_check: true
 kerneldoc_check: true
-signoff_check: true
 
 # We are using Linux style indentation with tabs
 # The indentation is checked by checkpatch not the python script
 tab_check: false
 
 [Hook Overrides Options]
-checkpatch_check: --no-tree --ignore=MSLEEP,VOLATILE,SPDX_LICENSE_TAG
+black_check: --include_regex=^util/chargen$
+branch_check: --optional
+checkpatch_check: --no-tree --no-signoff --ignore=MSLEEP,VOLATILE,SPDX_LICENSE_TAG
 kerneldoc_check: --include_regex=\bec_commands\.h$
+keyword_check: --block=zassume_
 
 cros_license_check :
+  --exclude_regex=^third_party/bmi220/
+  --exclude_regex=^third_party/bmi260/
+  --exclude_regex=^third_party/boringssl/
+  --exclude_regex=^third_party/incbin/
+  --exclude_regex=^third_party/libaeabi-cortexm0/
   --exclude_regex=^third_party/linux/
+  --exclude_regex=^third_party/sha2/
+  --exclude_regex=^third_party/unacl-curve25519/
 
 [Hook Scripts]
-presubmit_check = util/presubmit_check.sh
+cros lint = cros lint ${PRESUBMIT_FILES}
+check_cprints = util/check_cprints.py --commit ${PRESUBMIT_COMMIT} ${PRESUBMIT_FILES}
+check_ztest = util/check_ztest.py --commit ${PRESUBMIT_COMMIT} ${PRESUBMIT_FILES}
 config_option_check = util/config_option_check.py
 host_command_check = util/host_command_check.sh
 ec_commands_h = util/linux_ec_commands_h_check.sh
+migrated_files = util/migrated_files.sh ${PRESUBMIT_FILES}
+twister_test_tags = util/twister_tags.py --validate-files ${PRESUBMIT_FILES}
+check_zephyr_project_config = util/check_zephyr_project_config.py -d ${PRESUBMIT_FILES}
+zephyr_check_compliance = util/zephyr_check_compliance.py ${PRESUBMIT_COMMIT}
+zephyr_check_testcase_yaml = ./util/zephyr_check_testcase_yaml.py --commit ${PRESUBMIT_COMMIT} ${PRESUBMIT_FILES}
+low_coverage_reason = ./util/check_low_coverage_reason.py ${PRESUBMIT_COMMIT}
diff --git a/README.md b/README.md
index e3274487de..dacff1d4cc 100644
--- a/README.md
+++ b/README.md
@@ -2,13 +2,20 @@
 
 [TOC]
 
+> **Note** - This document covers the legacy Chrome EC implementation. The
+> legacy EC implementation is used by all Chromebook reference designs prior to
+> July 2021. On newer Chromebook designs, the EC implementation is based on the
+> Zephyr RTOS. Refer to the [Zephyr EC Introduction](./docs/zephyr/README.md)
+> for details on the Zephyr EC implementation.
+
 ## Introduction
 
 The Chromium OS project includes open source software for embedded controllers
 (EC) used in recent ARM and x86 based Chromebooks. This software includes a
 lightweight, multitasking OS with modules for power sequencing, keyboard
 control, thermal control, battery charging, and verified boot. The EC software
-is written in C and supports [a variety of micro-controllers](https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/).
+is written in C and supports
+[a variety of micro-controllers](https://chromium.googlesource.com/chromiumos/platform/ec/+/main/chip/).
 
 This document is a guide to help make you familiar with the EC code, current
 features, and the process for submitting code patches.
@@ -25,8 +32,8 @@ and [video](http://youtu.be/Ie7LRGgCXC8) from the
     (inclusive). See the
     [Chrome OS devices](http://dev.chromium.org/chromium-os/developer-information-for-chrome-os-devices)
     page for a list.
-1.  A Linux development environment. Ubuntu 14.04 Trusty (x86_64) is well
-    supported. Linux in a VM may work if you have a powerful host machine.
+1.  A Linux development environment. The latest Debian Stable (x86_64) is commonly used.
+    Linux in a VM may work if you have a powerful host machine.
 1.  A [servo debug board](http://dev.chromium.org/chromium-os/servo) (and
     header) is highly recommended for serial console and JTAG access to the EC.
 1.  A sense of adventure!
@@ -40,8 +47,8 @@ documentation due to historical reasons. If you just see the term "EC", it
 probably refers to "the" EC (i.e. the first one that existed). Most Chrome OS
 devices have an MCU, known as "the EC" that controls lots of things (key
 presses, turning the AP on/off). The OS that was written for "the" EC is now
-running on several different MCUs on Chrome OS devices with various tweaks
-(e.g. the FPMCU, the touchpad one that can do palm rejection, etc.). It's quite
+running on several different MCUs on Chrome OS devices with various tweaks (e.g.
+the FPMCU, the touchpad one that can do palm rejection, etc.). It's quite
 confusing, so try to be specific and use terms like FPMCU to distinguish the
 fingerprint MCU from "the EC".
 
@@ -97,21 +104,18 @@ I2C/onewire LED controllers, and I2C temperature sensors.
 **util** - Host utilities and scripts for flashing the EC. Also includes
 “ectool” used to query and send commands to the EC from userspace.
 
-**test** - Unit tests for EC components. These can be run locally in
-           a mock "host" environment or compiled for a target board.
-           If building for a target board, the test must be flashed and
-           run manually on the device.
-           All unit tests and fuzzers are build/run using the local
-           host environment during a `buildall`.
-           To run all unit tests locally, run `make runhosttests -j`.
-           To build a specific unit test for a specific board, run
-           `make test-<test_name> BOARD=<board_name>`.
-           Please contribute new tests if writing new functionality.
-           Please run `make help` for more detail.
-
-**fuzz** - Fuzzers for EC components. These fuzzers are expected to
-           run in the mock host environment. They follow the same rules
-           as unit tests, as thus use the same commands to build and run.
+**test** - Unit tests for EC components. These can be run locally in a mock
+"host" environment or compiled for a target board. If building for a target
+board, the test must be flashed and run manually on the device. All unit tests
+and fuzzers are build/run using the local host environment during a `buildall`.
+To run all unit tests locally, run `make runhosttests -j`. To build a specific
+unit test for a specific board, run `make test-<test_name> BOARD=<board_name>`.
+Please contribute new tests if writing new functionality. Please run `make help`
+for more detail.
+
+**fuzz** - Fuzzers for EC components. These fuzzers are expected to run in the
+mock host environment. They follow the same rules as unit tests, as thus use the
+same commands to build and run.
 
 ## Firmware Branches
 
@@ -119,7 +123,7 @@ Each Chrome device has a firmware branch created when the read-only firmware is
 locked down prior to launch. This is done so that updates can be made to the
 read-write firmware with a minimal set of changes from the read-only. Some
 Chrome devices only have build targets on firmware branches and not on
-cros/master. Run “`git branch -a | grep firmware`” to locate the firmware branch
+cros/main. Run “`git branch -a | grep firmware`” to locate the firmware branch
 for your board. Note that for devices still under development, the board
 configuration may be on the branch for the platform reference board.
 
@@ -153,11 +157,11 @@ branch1...branch2 as needed):
 git log --left-right --graph --cherry-pick --oneline branch1...branch2
 ```
 
-For example, to see the difference between cros/master and the HEAD of the
-current branch:
+For example, to see the difference between cros/main and the HEAD of the current
+branch:
 
 ```bash
-git log --left-right --graph --cherry-pick --oneline cros/master...HEAD
+git log --left-right --graph --cherry-pick --oneline cros/main...HEAD
 
 # Note: Use three dots “...” or it won’t work!
 ```
@@ -171,11 +175,11 @@ Building directly from the EC repository:
 
 ```bash
 cros_sdk
-cd ~/trunk/src/platform/ec
+cd ~/chromiumos/src/platform/ec
 make -j BOARD=<boardname>
 ```
 
-Where **<boardname>** is replaced by the name of the board you want to build an
+Where `<boardname>` is replaced by the name of the board you want to build an
 EC binary for. For example, the boardname for the Chromebook Pixel is “link”.
 The make command will generate an EC binary at `build/<boardname>/ec.bin`. The
 `-j` tells make to build multi-threaded which can be much faster on a multi-core
@@ -206,8 +210,16 @@ The generated EC binary from emerge is found at:
 (chroot) $ /build/<boardname>/firmware/ec.bin
 ```
 
+or
+
+```
+(chroot) $ /build/<boardname>/firmware/<devicename>/ec.bin
+```
+
+The `devicename` is the name of a device (also referred as board or variant) which belongs to a family of baseboard. `boardname` is the baseboard name in this case. Example : `/build/dedede/firmware/madoo/ec.bin`
+
 The ebuild file used by Chromium OS is found
-[here](https://chromium.googlesource.com/chromiumos/overlays/chromiumos-overlay/+/master/chromeos-base/chromeos-ec/chromeos-ec-9999.ebuild):
+[here](https://chromium.googlesource.com/chromiumos/overlays/chromiumos-overlay/+/main/chromeos-base/chromeos-ec/chromeos-ec-9999.ebuild):
 
 ```bash
 (chroot) $ ~/trunk/src/third_party/chromiumos-overlay/chromeos-base/chromeos-ec/chromeos-ec-9999.ebuild
@@ -245,6 +257,14 @@ If you build Chrome OS with `build_packages` the firmware image will be at:
 (chroot) $ /build/<boardname>/firmware/ec.bin
 ```
 
+or
+
+```
+(chroot) $ /build/<boardname>/firmware/<devicename>/ec.bin
+```
+
+The `devicename` is the name of a device (also referred as board or variant) which belongs to a family of baseboard. `boardname` is the baseboard name in this case. Example : `/build/dedede/firmware/madoo/ec.bin`
+
 Specifying `--image` is optional. If you leave off the `--image` argument, the
 `flash_ec` script will first look for a locally built `ec.bin` followed by one
 generated by `emerge`.
@@ -274,11 +294,11 @@ and turn on other developer-friendly flags (note that write protect must be
 disabled for this to work):
 
 ```bash
-(chroot) $ /usr/share/vboot/bin/set_gbb_flags.sh 0x239
+# futility gbb --set --flash --flags=0x239
 ```
 
 ```bash
-(chroot) $ reboot
+# reboot
 ```
 
 This turns on the following flags:
@@ -289,8 +309,15 @@ This turns on the following flags:
 *   `GBB_FLAG_DISABLE_FW_ROLLBACK_CHECK`
 *   `GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC`
 
+
+Alternatively, if the OS cannot be accessed, the same flag can be set over a servo with:
+
+```bash
+$ sudo futility gbb -s --flags=0x239 --servo
+```
+
 The `GBB` (Google Binary Block) flags are defined in the
-[vboot_reference source](https://chromium.googlesource.com/chromiumos/platform/vboot_reference/+/master/firmware/include/gbb_header.h).
+[vboot_reference source](https://chromium.googlesource.com/chromiumos/platform/vboot_reference/+/main/firmware/2lib/include/2struct.h).
 A varying subset of these flags are implemented and/or relevant for any
 particular board.
 
@@ -391,7 +418,7 @@ in priority order if more than one callback needs to be run. There are also
 hooks for running functions periodically: `HOOK_TICK` (fires every
 `HOOK_TICK_INVERVAL` ms which varies by EC chip) and `HOOK_SECOND`. See
 hook_type in
-[include/hooks.h](https://chromium.googlesource.com/chromiumos/platform/ec/+/master/include/hooks.h)
+[include/hooks.h](https://chromium.googlesource.com/chromiumos/platform/ec/+/main/include/hooks.h)
 for a complete list.
 
 ### Deferred Functions
@@ -432,7 +459,7 @@ void some_interrupt(enum gpio_signal signal)
 While there is no heap, there is a shared memory buffer that can be borrowed
 temporarily (ideally before a context switch). The size of the buffer depends on
 the EC chip being used. The buffer can only be used by one task at a time. See
-[common/shared_mem.c](https://chromium.googlesource.com/chromiumos/platform/ec/+/master/common/shared_mem.c)
+[common/shared_mem.c](https://chromium.googlesource.com/chromiumos/platform/ec/+/main/common/shared_mem.c)
 for more information. At present (May 2014), this buffer is only used by debug
 commands.
 
@@ -463,13 +490,13 @@ Other style notes:
     not use globals to pass information between modules without accessors. For
     module scope, accessors are not needed.
 1.  If you add a new `#define` config option to the code, please document it in
-    [include/config.h](https://chromium.googlesource.com/chromiumos/platform/ec/+/master/include/config.h)
+    [include/config.h](https://chromium.googlesource.com/chromiumos/platform/ec/+/main/include/config.h)
     with an `#undef` statement and descriptive comment.
 1.  The Chromium copyright header must be included at the top of new files in
     all contributions to the Chromium project:
 
     ```
-    /* Copyright <year> The Chromium OS Authors. All rights reserved.
+    /* Copyright <year> The ChromiumOS Authors
      * Use of this source code is governed by a BSD-style license that can be
      * found in the LICENSE file.
      */
@@ -489,7 +516,7 @@ Prior to uploading a new change for review, please run the EC unit tests with:
 
 These commands will build and run unit tests in an emulator on your host.
 
-Pre-submit checks are run when you try to upload a change-list. If you wish to
+Pre-upload checks are run when you try to upload a change-list. If you wish to
 run these checks manually first, commit your change locally then run the
 following command from within the chroot and while in the `src/platform/ec`
 directory:
@@ -498,14 +525,16 @@ directory:
 (chroot) $ ~/trunk/src/repohooks/pre-upload.py
 ```
 
-The pre-submit checks include checking the commit message. Commit messages must
-have a `BUG`, `BRANCH`, and `TEST` line along with `Signed-off-by: First Last
-<name@company.com>`. The signed-off-by line is a statement that you have written
-this code and it can be contributed under the terms of the `LICENSE` file.
+The pre-upload checks include checking the commit message.  Commit messages must
+have a `BUG` and `TEST`.  You may also optionally include a `BRANCH` line with a
+list of board names for which the CL should be cherry-picked back to old
+branches for.
 
 Please refer to existing commits (`git log`) to see the proper format for the
-commit message. If you have configured git properly, running `git commit` with
-the `-s` argument will add the Signed-off-by line for you.
+commit message.
+
+Note that code you submit must adhere to the [ChromeOS EC Firmware Test
+Requirements].
 
 ## Debugging
 
@@ -608,8 +637,8 @@ If the version is: `rambi_v1.6.68-a6608c8`:
 
 The branch numbers (as of May 2014) are:
 
-*   v1.0.0 cros/master
-*   v1.1.0 cros/master
+*   v1.0.0 cros/main
+*   v1.1.0 cros/main
 *   v1.2.0 cros/firmware-link-2695.2.B
 *   v1.3.0 cros/firmware-snow-2695.90.B
 *   v1.4.0 cros/firmware-skate-3824.129.B
@@ -640,3 +669,22 @@ cheese_v1.1.1755-4da9520
 ```
 
 [Firmware Write Protection]: ./docs/write_protection.md
+
+## CQ builder
+
+To test the cq builder script run these commands:
+
+### firmware-ec-cq
+```
+rm -rf /tmp/artifact_bundles /tmp/artifact_bundle_metadata \
+  ~/chromiumos/src/platform/ec/build
+./firmware_builder.py --metrics /tmp/metrics_build build && \
+./firmware_builder.py --metrics /tmp/metrics_test test && \
+./firmware_builder.py --metrics /tmp/metrics_bundle bundle && \
+echo PASSED
+cat /tmp/artifact_bundle_metadata
+cat /tmp/metrics_build
+ls -l /tmp/artifact_bundles/
+```
+
+[ChromeOS EC Firmware Test Requirements]: ./docs/chromeos-ec-firmware-test-requirements.md
diff --git a/baseboard/asurada/baseboard.c b/baseboard/asurada/baseboard.c
new file mode 100644
index 0000000000..7ff873963d
--- /dev/null
+++ b/baseboard/asurada/baseboard.c
@@ -0,0 +1,120 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Asurada baseboard-specific configuration */
+
+#include "adc.h"
+#include "button.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "driver/accel_lis2dw12.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "driver/als_tcs3400.h"
+#include "driver/bc12/mt6360.h"
+#include "driver/charger/isl923x.h"
+#include "driver/ppc/syv682x.h"
+#include "driver/tcpm/it83xx_pd.h"
+#include "driver/temp_sensor/thermistor.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "it5205_sbu.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "motion_sense.h"
+#include "power.h"
+#include "power_button.h"
+#include "regulator.h"
+#include "spi.h"
+#include "switch.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "temp_sensor.h"
+#include "timer.h"
+#include "uart.h"
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* Wake-up pins for hibernate */
+enum gpio_signal hibernate_wake_pins[] = {
+	GPIO_AC_PRESENT,
+	GPIO_LID_OPEN,
+	GPIO_POWER_BUTTON_L,
+};
+int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
+
+/*
+ * I2C channels (A, B, and C) are using the same timing registers (00h~07h)
+ * at default.
+ * In order to set frequency independently for each channels,
+ * We use timing registers 09h~0Bh, and the supported frequency will be:
+ * 50KHz, 100KHz, 400KHz, or 1MHz.
+ * I2C channels (D, E and F) can be set different frequency on different ports.
+ * The I2C(D/E/F) frequency depend on the frequency of SMBus Module and
+ * the individual prescale register.
+ * The frequency of SMBus module is 24MHz on default.
+ * The allowed range of I2C(D/E/F) frequency is as following setting.
+ * SMBus Module Freq = PLL_CLOCK / ((IT83XX_ECPM_SCDCR2 & 0x0F) + 1)
+ * (SMBus Module Freq / 510) <=  I2C Freq <= (SMBus Module Freq / 8)
+ * Channel D has multi-function and can be used as UART interface.
+ * Channel F is reserved for EC debug.
+ */
+
+/* I2C ports */
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "bat_chg",
+	  .port = IT83XX_I2C_CH_A,
+	  .kbps = 100,
+	  .scl = GPIO_I2C_A_SCL,
+	  .sda = GPIO_I2C_A_SDA },
+	{ .name = "sensor",
+	  .port = IT83XX_I2C_CH_B,
+	  .kbps = 400,
+	  .scl = GPIO_I2C_B_SCL,
+	  .sda = GPIO_I2C_B_SDA },
+	{ .name = "usb0",
+	  .port = IT83XX_I2C_CH_C,
+	  .kbps = 400,
+	  .scl = GPIO_I2C_C_SCL,
+	  .sda = GPIO_I2C_C_SDA },
+	{ .name = "usb1",
+	  .port = IT83XX_I2C_CH_E,
+	  .kbps = 400,
+	  .scl = GPIO_I2C_E_SCL,
+	  .sda = GPIO_I2C_E_SDA },
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+int board_allow_i2c_passthru(const struct i2c_cmd_desc_t *cmd_desc)
+{
+	return (cmd_desc->port == I2C_PORT_VIRTUAL_BATTERY);
+}
+
+const struct cc_para_t *board_get_cc_tuning_parameter(enum usbpd_port port)
+{
+	const static struct cc_para_t
+		cc_parameter[CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT] = {
+			{
+				.rising_time =
+					IT83XX_TX_PRE_DRIVING_TIME_1_UNIT,
+				.falling_time =
+					IT83XX_TX_PRE_DRIVING_TIME_2_UNIT,
+			},
+			{
+				.rising_time =
+					IT83XX_TX_PRE_DRIVING_TIME_1_UNIT,
+				.falling_time =
+					IT83XX_TX_PRE_DRIVING_TIME_2_UNIT,
+			},
+		};
+
+	return &cc_parameter[port];
+}
diff --git a/baseboard/asurada/baseboard.h b/baseboard/asurada/baseboard.h
new file mode 100644
index 0000000000..a8b62ccf59
--- /dev/null
+++ b/baseboard/asurada/baseboard.h
@@ -0,0 +1,195 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Asurada board configuration */
+
+#ifndef __CROS_EC_BASEBOARD_H
+#define __CROS_EC_BASEBOARD_H
+
+/* IT81202-bx config */
+/*
+ * NOTE: we need to make correct VCC voltage selection here if EC's VCC isn't
+ * connect to 1.8v on other versions.
+ */
+#define CONFIG_IT83XX_VCC_1P8V
+
+/*
+ * On power-on, H1 releases the EC from reset but then quickly asserts and
+ * releases the reset a second time. This means the EC sees 2 resets:
+ * (1) power-on reset, (2) reset-pin reset. This config will
+ * allow the second reset to be treated as a power-on.
+ */
+#define CONFIG_BOARD_RESET_AFTER_POWER_ON
+#define CONFIG_CHIPSET_MT8192
+#define CONFIG_EXTPOWER_GPIO
+#define CONFIG_HIBERNATE_WAKE_PINS_DYNAMIC
+#define CONFIG_POWER_SLEEP_FAILURE_DETECTION
+#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
+
+/* Chipset */
+#define CONFIG_CMD_AP_RESET_LOG
+#define CONFIG_CMD_POWERINDEBUG
+#define CONFIG_HOST_COMMAND_STATUS
+#define CONFIG_LOW_POWER_IDLE
+#define CONFIG_LOW_POWER_S0
+#define CONFIG_POWER_BUTTON
+#define CONFIG_POWER_COMMON
+#define CONFIG_PWM
+#define CONFIG_VBOOT_HASH
+#define CONFIG_VOLUME_BUTTONS
+#define CONFIG_WP_ACTIVE_HIGH
+
+/* Battery */
+#define CONFIG_BATTERY_CUT_OFF
+#define CONFIG_BATTERY_FUEL_GAUGE
+#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL
+#define CONFIG_BATTERY_SMART
+
+/* BC12 */
+#define CONFIG_BC12_DETECT_MT6360
+#define CONFIG_BC12_DETECT_PI3USB9201
+#undef CONFIG_BC12_SINGLE_DRIVER
+#define CONFIG_USB_CHARGER
+
+/* Charger */
+#define ADC_AMON_BMON ADC_CHARGER_AMON_R /* ADC name remap */
+#define ADC_PSYS ADC_CHARGER_PMON /* ADC name remap */
+#define CONFIG_CHARGE_MANAGER
+#define CONFIG_CHARGER
+#define CONFIG_CHARGE_RAMP_HW
+#define CONFIG_CHARGER_DISCHARGE_ON_AC
+#define CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT 512
+#define CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT 512
+#define CONFIG_CHARGER_ISL9238C
+#define CONFIG_CHARGER_MAINTAIN_VBAT
+#define CONFIG_CHARGER_OTG
+#define CONFIG_CHARGER_PSYS
+#define CONFIG_CHARGER_PSYS_READ
+#define CONFIG_CHARGER_SENSE_RESISTOR 10 /* BOARD_RS2 */
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 /* BOARD_RS1 */
+#define CONFIG_CMD_CHARGER_ADC_AMON_BMON
+
+/* Keyboard */
+#define CONFIG_CMD_KEYBOARD
+#define CONFIG_KEYBOARD_COL2_INVERTED
+#define CONFIG_KEYBOARD_PROTOCOL_MKBP
+#define CONFIG_MKBP_USE_GPIO
+
+/* I2C */
+#define CONFIG_I2C
+#define CONFIG_I2C_CONTROLLER
+#define CONFIG_I2C_PASSTHRU_RESTRICTED
+#define CONFIG_I2C_VIRTUAL_BATTERY
+#define I2C_PORT_CHARGER IT83XX_I2C_CH_A
+#define I2C_PORT_BATTERY IT83XX_I2C_CH_A
+#define I2C_PORT_POWER IT83XX_I2C_CH_A
+#define I2C_PORT_ACCEL IT83XX_I2C_CH_B
+#define I2C_PORT_PPC0 IT83XX_I2C_CH_C
+#define I2C_PORT_PPC1 IT83XX_I2C_CH_E
+#define I2C_PORT_USB_MUX0 IT83XX_I2C_CH_C
+#define I2C_PORT_USB_MUX1 IT83XX_I2C_CH_E
+#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
+#define CONFIG_SMBUS_PEC
+
+/* LED */
+#define CONFIG_LED_COMMON
+
+/* PD / USB-C / PPC */
+#define CONFIG_CMD_PPC_DUMP
+#define CONFIG_HOSTCMD_PD_CONTROL
+#define CONFIG_IT83XX_TUNE_CC_PHY
+#define CONFIG_USB_MUX_VIRTUAL
+#define CONFIG_USBC_PPC
+#define CONFIG_USBC_PPC_DEDICATED_INT
+#define CONFIG_USBC_PPC_POLARITY
+#define CONFIG_USBC_PPC_SYV682C
+#define CONFIG_USBC_PPC_VCONN
+#define CONFIG_USBC_SS_MUX
+#define CONFIG_USBC_VCONN
+#define CONFIG_USBC_VCONN_SWAP
+#define CONFIG_USB_DRP_ACC_TRYSRC
+#define CONFIG_USB_MUX_IT5205 /* C0 */
+#define CONFIG_USB_MUX_PS8743 /* C1 */
+#define CONFIG_USB_PD_ALT_MODE
+#define CONFIG_USB_PD_ALT_MODE_DFP
+#define CONFIG_USB_PD_DECODE_SOP
+#define CONFIG_USB_PD_DISCHARGE
+#define CONFIG_USB_PD_DISCHARGE_PPC
+#define CONFIG_USB_PD_DP_HPD_GPIO
+#define CONFIG_USB_PD_DP_HPD_GPIO_CUSTOM
+#define CONFIG_USB_PD_DUAL_ROLE
+#define CONFIG_USB_PD_FRS_PPC
+#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 2
+#define CONFIG_USB_PD_LOGGING
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#define CONFIG_USB_PD_REV30
+#define CONFIG_USB_PD_TCPC_LOW_POWER
+#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP
+#define CONFIG_USB_PD_TCPM_TCPCI
+#define CONFIG_USB_PD_TCPMV2
+#define CONFIG_USB_PD_TRY_SRC
+#define CONFIG_USB_PD_VBUS_DETECT_PPC
+#define CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT
+#define CONFIG_USB_PID 0x5053
+#define CONFIG_USB_POWER_DELIVERY
+
+/* USB-A */
+#define CONFIG_USB_PORT_POWER_DUMB
+#define CONFIG_USB_PORT_POWER_DUMB_CUSTOM_HOOK
+#define USB_PORT_COUNT USBA_PORT_COUNT
+
+/* UART */
+#undef CONFIG_UART_TX_BUF_SIZE
+#define CONFIG_UART_TX_BUF_SIZE 4096
+
+/* Sensor */
+#ifdef HAS_TASK_MOTIONSENSE
+#define CONFIG_CMD_ACCEL_INFO
+#define CONFIG_CMD_ACCELS
+
+#define CONFIG_ACCEL_FIFO
+#define CONFIG_ACCEL_FIFO_SIZE 256
+#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
+#endif
+
+/* SPI / Host Command */
+#define CONFIG_SPI
+
+/* MKBP */
+#define CONFIG_MKBP_EVENT
+
+#define CONFIG_KEYBOARD_PROTOCOL_MKBP
+#define CONFIG_MKBP_USE_GPIO
+
+/* Voltage regulator control */
+#define CONFIG_HOSTCMD_REGULATOR
+
+/* Define the host events which are allowed to wakeup AP in S3. */
+#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK                   \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |    \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |        \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT) |     \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |     \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+/* And the MKBP events */
+#define CONFIG_MKBP_EVENT_WAKEUP_MASK \
+	(BIT(EC_MKBP_EVENT_KEY_MATRIX) | BIT(EC_MKBP_EVENT_HOST_EVENT))
+
+#include "baseboard_common.h"
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "power/mt8192.h"
+#include "registers.h"
+
+void board_reset_pd_mcu(void);
+enum board_sub_board board_get_sub_board(void);
+void usb_a0_interrupt(enum gpio_signal signal);
+
+#endif /* !__ASSEMBLER__ */
+#endif /* __CROS_EC_BASEBOARD_H */
diff --git a/baseboard/asurada/baseboard_common.h b/baseboard/asurada/baseboard_common.h
new file mode 100644
index 0000000000..4b8892e5b7
--- /dev/null
+++ b/baseboard/asurada/baseboard_common.h
@@ -0,0 +1,44 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Asurada baseboard-specific onfiguration common to ECOS and Zephyr */
+
+#ifndef __CROS_EC_BASEBOARD_COMMON_H
+#define __CROS_EC_BASEBOARD_COMMON_H
+
+/* GPIO name remapping */
+#define GPIO_EN_HDMI_PWR GPIO_EC_X_GPIO1
+#define GPIO_USB_C1_FRS_EN GPIO_EC_X_GPIO1
+#define GPIO_USB_C1_PPC_INT_ODL GPIO_X_EC_GPIO2
+#define GPIO_PS185_EC_DP_HPD GPIO_X_EC_GPIO2
+#define GPIO_USB_C1_DP_IN_HPD GPIO_EC_X_GPIO3
+#define GPIO_PS185_PWRDN_ODL GPIO_EC_X_GPIO3
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+
+enum board_sub_board {
+	SUB_BOARD_NONE = -1,
+	SUB_BOARD_TYPEC,
+	SUB_BOARD_HDMI,
+	SUB_BOARD_COUNT,
+};
+
+/**
+ * board_get_version() - Get the board version
+ *
+ * Read the ADC to obtain the board version
+ *
+ * @return board version in the range 0 to 14 inclusive
+ */
+int board_get_version(void);
+
+void ppc_interrupt(enum gpio_signal signal);
+void bc12_interrupt(enum gpio_signal signal);
+void x_ec_interrupt(enum gpio_signal signal);
+
+#endif /* !__ASSEMBLER__ */
+#endif /* __CROS_EC_BASEBOARD_COMMON_H */
diff --git a/baseboard/asurada/board_chipset.c b/baseboard/asurada/board_chipset.c
new file mode 100644
index 0000000000..24754f597f
--- /dev/null
+++ b/baseboard/asurada/board_chipset.c
@@ -0,0 +1,24 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Asurada baseboard-chipset specific configuration */
+
+#include "common.h"
+#include "gpio.h"
+#include "hooks.h"
+
+/* Called on AP S3 -> S0 transition */
+static void board_chipset_resume(void)
+{
+	gpio_set_level(GPIO_EC_BL_EN_OD, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S0 -> S3 transition */
+static void board_chipset_suspend(void)
+{
+	gpio_set_level(GPIO_EC_BL_EN_OD, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
diff --git a/baseboard/asurada/board_id.c b/baseboard/asurada/board_id.c
new file mode 100644
index 0000000000..9a316d8d40
--- /dev/null
+++ b/baseboard/asurada/board_id.c
@@ -0,0 +1,94 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc.h"
+#include "common.h"
+#include "console.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "timer.h"
+#include "util.h"
+
+/**
+ * Conversion based on following table:
+ *
+ * ID | Rp   | Rd   | Voltage
+ *    | kOhm | kOhm | mV
+ * ---+------+------+--------
+ *  0 | 51.1 |  2.2 | 136.2
+ *  1 | 51.1 | 6.81 | 388.1
+ *  2 | 51.1 |   11 | 584.5
+ *  3 | 57.6 |   18 | 785.7
+ *  4 | 51.1 |   22 | 993.2
+ *  5 | 51.1 |   30 | 1220.7
+ *  6 | 51.1 | 39.2 | 1432.6
+ *  7 |   56 |   56 | 1650.0
+ *  8 |   47 | 61.9 | 1875.8
+ *  9 |   47 | 80.6 | 2084.5
+ * 10 |   56 |  124 | 2273.3
+ * 11 | 51.1 |  150 | 2461.5
+ * 12 |   47 |  200 | 2672.1
+ * 13 |   47 |  330 | 2888.6
+ * 14 |   47 |  680 | 3086.7
+ */
+const static int voltage_map[] = {
+	136,  388,  584,  785,	993,  1220, 1432, 1650,
+	1875, 2084, 2273, 2461, 2672, 2888, 3086,
+};
+
+const int threshold_mv = 100;
+
+/**
+ * Convert ADC value to board id using the voltage table above.
+ *
+ * @param ch	ADC channel to read, usually ADC_BOARD_ID_0 or ADC_BOARD_ID_1.
+ *
+ * @return	a non-negative board id, or negative value if error.
+ */
+static int adc_value_to_numeric_id(enum adc_channel ch)
+{
+	int mv;
+
+	gpio_set_level(GPIO_EN_EC_ID_ODL, 0);
+	/* Wait to allow cap charge */
+	msleep(10);
+
+	mv = adc_read_channel(ch);
+	if (mv == ADC_READ_ERROR)
+		mv = adc_read_channel(ch);
+
+	gpio_set_level(GPIO_EN_EC_ID_ODL, 1);
+
+	if (mv == ADC_READ_ERROR)
+		return -EC_ERROR_UNKNOWN;
+
+	for (int i = 0; i < ARRAY_SIZE(voltage_map); i++) {
+		if (IN_RANGE(mv, voltage_map[i] - threshold_mv,
+			     voltage_map[i] + threshold_mv - 1))
+			return i;
+	}
+
+	return -EC_ERROR_UNKNOWN;
+}
+
+static int version = -1;
+
+/* b/163963220: Cache ADC value before board_hibernate_late() reads it */
+static void board_version_init(void)
+{
+	version = adc_value_to_numeric_id(ADC_BOARD_ID_0);
+	if (version < 0) {
+		ccprints("WARN:BOARD_ID_0");
+		ccprints("Assuming board id = 0");
+
+		version = 0;
+	}
+}
+DECLARE_HOOK(HOOK_INIT, board_version_init, HOOK_PRIO_INIT_ADC + 1);
+
+__override int board_get_version(void)
+{
+	return version;
+}
diff --git a/baseboard/asurada/build.mk b/baseboard/asurada/build.mk
new file mode 100644
index 0000000000..ac4f1489d2
--- /dev/null
+++ b/baseboard/asurada/build.mk
@@ -0,0 +1,15 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Baseboard specific files build
+#
+
+baseboard-y=baseboard.o
+baseboard-y+=board_chipset.o
+baseboard-y+=board_id.o
+baseboard-y+=hibernate.o
+baseboard-y+=regulator.o
+baseboard-y+=usbc_config.o
+baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
diff --git a/baseboard/asurada/hibernate.c b/baseboard/asurada/hibernate.c
new file mode 100644
index 0000000000..21c2de41e3
--- /dev/null
+++ b/baseboard/asurada/hibernate.c
@@ -0,0 +1,40 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charger.h"
+#include "driver/charger/isl923x_public.h"
+#include "gpio.h"
+#include "system.h"
+
+/* Hayato board specific hibernate implementation */
+__override void board_hibernate_late(void)
+{
+	/*
+	 * Turn off PP5000_A. Required for devices without Z-state.
+	 * Don't care for devices with Z-state.
+	 */
+	gpio_set_level(GPIO_EN_PP5000_A, 0);
+
+	/*
+	 * GPIO_EN_SLP_Z not implemented in rev0/1,
+	 * fallback to usual hibernate process.
+	 */
+	if (board_get_version() <= 1) {
+		if (IS_ENABLED(BOARD_ASURADA) ||
+		    (IS_ENABLED(CONFIG_ZEPHYR) &&
+		     IS_ENABLED(CONFIG_BOARD_ASURADA)))
+			return;
+	}
+
+	gpio_set_level(GPIO_EN_SLP_Z, 1);
+
+	/* should not reach here */
+	__builtin_unreachable();
+}
+
+void board_hibernate(void)
+{
+	isl9238c_hibernate(CHARGER_SOLO);
+}
diff --git a/board/asurada/it5205_sbu.c b/baseboard/asurada/it5205_sbu.c
similarity index 89%
rename from board/asurada/it5205_sbu.c
rename to baseboard/asurada/it5205_sbu.c
index 9ee59a5cc3..fc2cefd208 100644
--- a/board/asurada/it5205_sbu.c
+++ b/baseboard/asurada/it5205_sbu.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -12,8 +12,8 @@
 #include "timer.h"
 #include "usb_mux.h"
 
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USB, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args)
 
 #define OVP_RETRY_DELAY_US_MIN (100 * MSEC)
 
diff --git a/board/asurada/it5205_sbu.h b/baseboard/asurada/it5205_sbu.h
similarity index 83%
rename from board/asurada/it5205_sbu.h
rename to baseboard/asurada/it5205_sbu.h
index 8dc59520dd..2a17506cad 100644
--- a/board/asurada/it5205_sbu.h
+++ b/baseboard/asurada/it5205_sbu.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/baseboard/asurada/regulator.c b/baseboard/asurada/regulator.c
new file mode 100644
index 0000000000..0487f8faa6
--- /dev/null
+++ b/baseboard/asurada/regulator.c
@@ -0,0 +1,45 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "bc12/mt6360_public.h"
+#include "common.h"
+
+/* SD Card */
+int board_regulator_get_info(uint32_t index, char *name, uint16_t *num_voltages,
+			     uint16_t *voltages_mv)
+{
+	enum mt6360_regulator_id id = index;
+
+	return mt6360_regulator_get_info(id, name, num_voltages, voltages_mv);
+}
+
+int board_regulator_enable(uint32_t index, uint8_t enable)
+{
+	enum mt6360_regulator_id id = index;
+
+	return mt6360_regulator_enable(id, enable);
+}
+
+int board_regulator_is_enabled(uint32_t index, uint8_t *enabled)
+{
+	enum mt6360_regulator_id id = index;
+
+	return mt6360_regulator_is_enabled(id, enabled);
+}
+
+int board_regulator_set_voltage(uint32_t index, uint32_t min_mv,
+				uint32_t max_mv)
+{
+	enum mt6360_regulator_id id = index;
+
+	return mt6360_regulator_set_voltage(id, min_mv, max_mv);
+}
+
+int board_regulator_get_voltage(uint32_t index, uint32_t *voltage_mv)
+{
+	enum mt6360_regulator_id id = index;
+
+	return mt6360_regulator_get_voltage(id, voltage_mv);
+}
diff --git a/baseboard/asurada/usb_pd_policy.c b/baseboard/asurada/usb_pd_policy.c
new file mode 100644
index 0000000000..afec537330
--- /dev/null
+++ b/baseboard/asurada/usb_pd_policy.c
@@ -0,0 +1,237 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "adc.h"
+#include "atomic.h"
+#include "baseboard_common.h"
+#include "charge_manager.h"
+#include "chipset.h"
+#include "console.h"
+#include "gpio.h"
+#include "timer.h"
+#include "usb_dp_alt_mode.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+
+#if CONFIG_USB_PD_3A_PORTS != 1
+#error Asurada reference must have at least one 3.0 A port
+#endif
+
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+
+int svdm_get_hpd_gpio(int port)
+{
+	/* HPD is low active, inverse the result */
+	return !gpio_get_level(GPIO_EC_DPBRDG_HPD_ODL);
+}
+
+void svdm_set_hpd_gpio(int port, int en)
+{
+	/*
+	 * HPD is low active, inverse the en
+	 * TODO: C0&C1 shares the same HPD, implement FCFS policy.
+	 */
+	gpio_set_level(GPIO_EC_DPBRDG_HPD_ODL, !en);
+}
+
+/**
+ * Is the port fine to be muxed its DisplayPort lines?
+ *
+ * Only one port can be muxed to DisplayPort at a time.
+ *
+ * @param port	Port number of TCPC.
+ * @return	1 is fine; 0 is bad as other port is already muxed;
+ */
+static int is_dp_muxable(int port)
+{
+	int i;
+
+	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+		if (i != port) {
+			if (usb_mux_get(i) & USB_PD_MUX_DP_ENABLED)
+				return 0;
+		}
+	}
+
+	return 1;
+}
+
+__override int svdm_dp_attention(int port, uint32_t *payload)
+{
+	int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]);
+	int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]);
+#ifdef CONFIG_USB_PD_DP_HPD_GPIO
+	int cur_lvl = svdm_get_hpd_gpio(port);
+#endif /* CONFIG_USB_PD_DP_HPD_GPIO */
+	mux_state_t mux_state;
+
+	dp_status[port] = payload[1];
+
+	if (!is_dp_muxable(port)) {
+		/* TODO(waihong): Info user? */
+		CPRINTS("p%d: The other port is already muxed.", port);
+		return 0; /* nak */
+	}
+
+	if (lvl)
+		gpio_set_level_verbose(CC_USBPD, GPIO_DP_AUX_PATH_SEL, port);
+
+	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && (irq || lvl))
+		/*
+		 * Wake up the AP.  IRQ or level high indicates a DP sink is now
+		 * present.
+		 */
+		if (IS_ENABLED(CONFIG_MKBP_EVENT))
+			pd_notify_dp_alt_mode_entry(port);
+
+	/* Its initial DP status message prior to config */
+	if (!(dp_flags[port] & DP_FLAGS_DP_ON)) {
+		if (lvl)
+			dp_flags[port] |= DP_FLAGS_HPD_HI_PENDING;
+		return 1;
+	}
+
+#ifdef CONFIG_USB_PD_DP_HPD_GPIO
+	if (irq && !lvl) {
+		/*
+		 * IRQ can only be generated when the level is high, because
+		 * the IRQ is signaled by a short low pulse from the high level.
+		 */
+		CPRINTF("ERR:HPD:IRQ&LOW\n");
+		return 0; /* nak */
+	}
+
+	if (irq && cur_lvl) {
+		uint64_t now = get_time().val;
+		/* wait for the minimum spacing between IRQ_HPD if needed */
+		if (now < svdm_hpd_deadline[port])
+			usleep(svdm_hpd_deadline[port] - now);
+
+		/* generate IRQ_HPD pulse */
+		svdm_set_hpd_gpio(port, 0);
+		/*
+		 * b/171172053#comment14: since the HPD_DSTREAM_DEBOUNCE_IRQ is
+		 * very short (500us), we can use udelay instead of usleep for
+		 * more stable pulse period.
+		 */
+		udelay(HPD_DSTREAM_DEBOUNCE_IRQ);
+		svdm_set_hpd_gpio(port, 1);
+	} else {
+		svdm_set_hpd_gpio(port, lvl);
+	}
+
+	/* set the minimum time delay (2ms) for the next HPD IRQ */
+	svdm_hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
+#endif /* CONFIG_USB_PD_DP_HPD_GPIO */
+
+	mux_state = (lvl ? USB_PD_MUX_HPD_LVL : USB_PD_MUX_HPD_LVL_DEASSERTED) |
+		    (irq ? USB_PD_MUX_HPD_IRQ : USB_PD_MUX_HPD_IRQ_DEASSERTED);
+	usb_mux_hpd_update(port, mux_state);
+
+#ifdef USB_PD_PORT_TCPC_MST
+	if (port == USB_PD_PORT_TCPC_MST)
+		baseboard_mst_enable_control(port, lvl);
+#endif
+
+	/* ack */
+	return 1;
+}
+
+__override void svdm_exit_dp_mode(int port)
+{
+#ifdef CONFIG_USB_PD_DP_HPD_GPIO
+	svdm_set_hpd_gpio(port, 0);
+#endif /* CONFIG_USB_PD_DP_HPD_GPIO */
+	usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
+					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+
+#ifdef USB_PD_PORT_TCPC_MST
+	if (port == USB_PD_PORT_TCPC_MST)
+		baseboard_mst_enable_control(port, 0);
+#endif
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	static atomic_t vbus_prev[CONFIG_USB_PD_PORT_MAX_COUNT];
+	int vbus;
+
+	if ((IS_ENABLED(BOARD_HAYATO) && board_get_version() < 4) ||
+	    (IS_ENABLED(BOARD_SPHERION) && board_get_version() < 1))
+		return ppc_is_vbus_present(port);
+
+	/*
+	 * (b:181203590#comment20) TODO(yllin): use
+	 *  PD_VSINK_DISCONNECT_PD for non-5V case.
+	 */
+	vbus = adc_read_channel(board_get_vbus_adc(port)) >=
+	       PD_V_SINK_DISCONNECT_MAX;
+
+#ifdef CONFIG_USB_CHARGER
+	/*
+	 * There's no PPC to inform VBUS change for usb_charger, so inform
+	 * the usb_charger now.
+	 */
+	if (!!(vbus_prev[port] != vbus))
+		usb_charger_vbus_change(port, vbus);
+
+	if (vbus)
+		atomic_or(&vbus_prev[port], 1);
+	else
+		atomic_clear(&vbus_prev[port]);
+#endif
+	return vbus;
+}
+
+void pd_power_supply_reset(int port)
+{
+	int prev_en;
+
+	prev_en = ppc_is_sourcing_vbus(port);
+
+	/* Disable VBUS. */
+	ppc_vbus_source_enable(port, 0);
+
+	/* Enable discharge if we were previously sourcing 5V */
+	if (prev_en)
+		pd_set_vbus_discharge(port, 1);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_check_vconn_swap(int port)
+{
+	/* Allow Vconn swap if AP is on. */
+	return chipset_in_state(CHIPSET_STATE_SUSPEND | CHIPSET_STATE_ON);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	/* Disable charging. */
+	rv = ppc_vbus_sink_enable(port, 0);
+	if (rv)
+		return rv;
+
+	pd_set_vbus_discharge(port, 0);
+
+	/* Provide Vbus. */
+	rv = ppc_vbus_source_enable(port, 1);
+	if (rv)
+		return rv;
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+int board_vbus_source_enabled(int port)
+{
+	return ppc_is_sourcing_vbus(port);
+}
diff --git a/baseboard/asurada/usbc_config.c b/baseboard/asurada/usbc_config.c
new file mode 100644
index 0000000000..391b9134c5
--- /dev/null
+++ b/baseboard/asurada/usbc_config.c
@@ -0,0 +1,435 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Asurada baseboard-specific USB-C configuration */
+
+#include "adc.h"
+#include "baseboard_common.h"
+#include "bc12/mt6360_public.h"
+#include "bc12/pi3usb9201_public.h"
+#include "button.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "charger/isl923x_public.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "ppc/syv682x_public.h"
+#include "spi.h"
+#include "switch.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "tcpm/it8xxx2_pd_public.h"
+#include "uart.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_mux/it5205_public.h"
+#include "usb_mux/ps8743_public.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_ppc.h"
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+};
+
+/* Baseboard */
+
+static void baseboard_init(void)
+{
+	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
+	gpio_enable_interrupt(GPIO_AP_XHCI_INIT_DONE);
+}
+DECLARE_HOOK(HOOK_INIT, baseboard_init, HOOK_PRIO_DEFAULT - 1);
+
+/* Sub-board */
+
+enum board_sub_board board_get_sub_board(void)
+{
+	static enum board_sub_board sub = SUB_BOARD_NONE;
+
+	if (sub != SUB_BOARD_NONE)
+		return sub;
+
+	/* HDMI board has external pull high. */
+	if (gpio_get_level(GPIO_EC_X_GPIO3)) {
+		sub = SUB_BOARD_HDMI;
+		/* Only has 1 PPC with HDMI subboard */
+		ppc_cnt = 1;
+		/* EC_X_GPIO1 */
+		gpio_set_flags(GPIO_EN_HDMI_PWR, GPIO_OUT_HIGH);
+		/* X_EC_GPIO2 */
+		gpio_set_flags(GPIO_PS185_EC_DP_HPD, GPIO_INT_BOTH);
+		/* EC_X_GPIO3 */
+		gpio_set_flags(GPIO_PS185_PWRDN_ODL, GPIO_ODR_HIGH);
+	} else {
+		sub = SUB_BOARD_TYPEC;
+		/* EC_X_GPIO1 */
+		gpio_set_flags(GPIO_USB_C1_FRS_EN, GPIO_OUT_LOW);
+		/* X_EC_GPIO2 */
+		gpio_set_flags(GPIO_USB_C1_PPC_INT_ODL,
+			       GPIO_INT_BOTH | GPIO_PULL_UP);
+		/* EC_X_GPIO3 */
+		gpio_set_flags(GPIO_USB_C1_DP_IN_HPD, GPIO_OUT_LOW);
+	}
+
+	CPRINTS("Detect %s SUB", sub == SUB_BOARD_HDMI ? "HDMI" : "TYPEC");
+	return sub;
+}
+
+static void sub_board_init(void)
+{
+	board_get_sub_board();
+}
+DECLARE_HOOK(HOOK_INIT, sub_board_init, HOOK_PRIO_INIT_I2C - 1);
+
+/* Detect subboard */
+static void board_tcpc_init(void)
+{
+	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
+	/* C1: GPIO_USB_C1_PPC_INT_ODL & HDMI: GPIO_PS185_EC_DP_HPD */
+	gpio_enable_interrupt(GPIO_X_EC_GPIO2);
+
+	/* If this is not a Type-C subboard, disable the task. */
+	if (board_get_sub_board() != SUB_BOARD_TYPEC)
+		task_disable_task(TASK_ID_PD_C1);
+}
+/* Must be done after I2C and subboard */
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
+
+/* PPC */
+struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.i2c_port = I2C_PORT_PPC0,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.drv = &syv682x_drv,
+		.frs_en = GPIO_USB_C0_FRS_EN,
+	},
+	{
+		.i2c_port = I2C_PORT_PPC1,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.drv = &syv682x_drv,
+		.frs_en = GPIO_USB_C1_FRS_EN,
+	},
+};
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/* BC12 */
+const struct mt6360_config_t mt6360_config = {
+	.i2c_port = I2C_PORT_POWER,
+	.i2c_addr_flags = MT6360_PMU_I2C_ADDR_FLAGS,
+};
+
+const struct pi3usb9201_config_t
+		pi3usb9201_bc12_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	/* [0]: unused */
+	[1] = {
+		.i2c_port = I2C_PORT_PPC1,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	}
+};
+
+struct bc12_config bc12_ports[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{ .drv = &mt6360_drv },
+	{ .drv = &pi3usb9201_drv },
+};
+
+void bc12_interrupt(enum gpio_signal signal)
+{
+	if (signal == GPIO_USB_C0_BC12_INT_ODL)
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+	else
+		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+}
+
+static void board_sub_bc12_init(void)
+{
+	if (board_get_sub_board() == SUB_BOARD_TYPEC)
+		gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L);
+	else
+		/* If this is not a Type-C subboard, disable the task. */
+		task_disable_task(TASK_ID_USB_CHG_P1);
+}
+/* Must be done after I2C and subboard */
+DECLARE_HOOK(HOOK_INIT, board_sub_bc12_init, HOOK_PRIO_INIT_I2C + 1);
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	if (signal == GPIO_USB_C0_PPC_INT_ODL)
+		/* C0: PPC interrupt */
+		syv682x_interrupt(0);
+}
+
+__override uint8_t board_get_usb_pd_port_count(void)
+{
+	if (board_get_sub_board() == SUB_BOARD_TYPEC)
+		return CONFIG_USB_PD_PORT_MAX_COUNT;
+	else
+		return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
+}
+
+/* USB-A */
+const int usb_port_enable[] = {
+	GPIO_EN_PP5000_USB_A0_VBUS,
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
+
+void usb_a0_interrupt(enum gpio_signal signal)
+{
+	enum usb_charge_mode mode = gpio_get_level(signal) ?
+					    USB_CHARGE_MODE_ENABLED :
+					    USB_CHARGE_MODE_DISABLED;
+
+	for (int i = 0; i < USB_PORT_COUNT; i++)
+		usb_charge_set_mode(i, mode, USB_ALLOW_SUSPEND_CHARGE);
+}
+
+static int board_ps8743_mux_set(const struct usb_mux *me, mux_state_t mux_state)
+{
+	int rv = EC_SUCCESS;
+	int reg = 0;
+
+	rv = ps8743_read(me, PS8743_REG_MODE, &reg);
+	if (rv)
+		return rv;
+
+	/* Disable FLIP pin, enable I2C control. */
+	reg |= PS8743_MODE_FLIP_REG_CONTROL;
+	/* Disable CE_USB pin, enable I2C control. */
+	reg |= PS8743_MODE_USB_REG_CONTROL;
+	/* Disable CE_DP pin, enable I2C control. */
+	reg |= PS8743_MODE_DP_REG_CONTROL;
+
+	/*
+	 * DP specific config
+	 *
+	 * Enable/Disable IN_HPD on the DB.
+	 */
+	gpio_set_level(GPIO_USB_C1_DP_IN_HPD,
+		       mux_state & USB_PD_MUX_DP_ENABLED);
+
+	return ps8743_write(me, PS8743_REG_MODE, reg);
+}
+
+const struct usb_mux_chain usbc0_virtual_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = 0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+
+const struct usb_mux_chain usbc1_virtual_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = 1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX0,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+			},
+		.next = &usbc0_virtual_mux,
+	},
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_USB_MUX1,
+				.i2c_addr_flags = PS8743_I2C_ADDR0_FLAG,
+				.driver = &ps8743_usb_mux_driver,
+				.board_set = &board_ps8743_mux_set,
+			},
+		.next = &usbc1_virtual_mux,
+	},
+};
+
+void board_overcurrent_event(int port, int is_overcurrented)
+{
+	/* TODO: check correct operation for Asurada */
+}
+
+/* TCPC */
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_EMBEDDED,
+		/* TCPC is embedded within EC so no i2c config needed */
+		.drv = &it8xxx2_tcpm_drv,
+		/* Alert is active-low, push-pull */
+		.flags = 0,
+	},
+	{
+		.bus_type = EC_BUS_TYPE_EMBEDDED,
+		/* TCPC is embedded within EC so no i2c config needed */
+		.drv = &it8xxx2_tcpm_drv,
+		/* Alert is active-low, push-pull */
+		.flags = 0,
+	},
+};
+
+uint16_t tcpc_get_alert_status(void)
+{
+	/*
+	 * C0 & C1: TCPC is embedded in the EC and processes interrupts in the
+	 * chip code (it83xx/intc.c)
+	 */
+	return 0;
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * C0 & C1: TCPC is embedded in the EC and processes interrupts in the
+	 * chip code (it83xx/intc.c)
+	 */
+}
+
+void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
+{
+	/*
+	 * We ignore the cc_pin and PPC vconn because polarity and PPC vconn
+	 * should already be set correctly in the PPC driver via the pd
+	 * state machine.
+	 */
+}
+
+int board_set_active_charge_port(int port)
+{
+	int i;
+	int is_valid_port = port == 0 || (port == 1 && board_get_sub_board() ==
+							       SUB_BOARD_TYPEC);
+
+	if (!is_valid_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTS("Disabling all charger ports");
+
+		/* Disable all ports. */
+		for (i = 0; i < ppc_cnt; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (ppc_vbus_sink_enable(i, 0))
+				CPRINTS("Disabling C%d as sink failed.", i);
+		}
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (ppc_is_sourcing_vbus(port)) {
+		CPRINTS("Skip enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTS("New charge port: C%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < ppc_cnt; i++) {
+		if (i == port)
+			continue;
+
+		if (ppc_vbus_sink_enable(i, 0))
+			CPRINTS("C%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTS("C%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+/**
+ * Handle PS185 HPD changing state.
+ */
+int debounced_hpd;
+
+static void ps185_hdmi_hpd_deferred(void)
+{
+	const int new_hpd = gpio_get_level(GPIO_PS185_EC_DP_HPD);
+
+	/* HPD status not changed, probably a glitch, just return. */
+	if (debounced_hpd == new_hpd)
+		return;
+
+	debounced_hpd = new_hpd;
+
+	gpio_set_level(GPIO_EC_DPBRDG_HPD_ODL, !debounced_hpd);
+	CPRINTS(debounced_hpd ? "HDMI plug" : "HDMI unplug");
+}
+DECLARE_DEFERRED(ps185_hdmi_hpd_deferred);
+
+#define PS185_HPD_DEBOUCE 250
+
+static void hdmi_hpd_interrupt(enum gpio_signal signal)
+{
+	hook_call_deferred(&ps185_hdmi_hpd_deferred_data, PS185_HPD_DEBOUCE);
+}
+
+/* HDMI/TYPE-C function shared subboard interrupt */
+void x_ec_interrupt(enum gpio_signal signal)
+{
+	int sub = board_get_sub_board();
+
+	if (sub == SUB_BOARD_TYPEC)
+		/* C1: PPC interrupt */
+		syv682x_interrupt(1);
+	else if (sub == SUB_BOARD_HDMI)
+		hdmi_hpd_interrupt(signal);
+	else
+		CPRINTS("Undetected subboard interrupt.");
+}
+
+int ppc_get_alert_status(int port)
+{
+	if (port == 0)
+		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
+	if (port == 1 && board_get_sub_board() == SUB_BOARD_TYPEC)
+		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
+
+	return 0;
+}
+
+#ifdef CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT
+enum adc_channel board_get_vbus_adc(int port)
+{
+	if (port == 0)
+		return ADC_VBUS_C0;
+	if (port == 1)
+		return ADC_VBUS_C1;
+	CPRINTSUSB("Unknown vbus adc port id: %d", port);
+	return ADC_VBUS_C0;
+}
+#endif /* CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT */
diff --git a/baseboard/brask/baseboard.c b/baseboard/brask/baseboard.c
new file mode 100644
index 0000000000..33a3d9acf4
--- /dev/null
+++ b/baseboard/brask/baseboard.c
@@ -0,0 +1,12 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "gpio_signal.h"
+
+/* Wake up pins */
+const enum gpio_signal hibernate_wake_pins[] = {};
+const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
diff --git a/baseboard/brask/baseboard.h b/baseboard/brask/baseboard.h
new file mode 100644
index 0000000000..8f10ebb8aa
--- /dev/null
+++ b/baseboard/brask/baseboard.h
@@ -0,0 +1,215 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Brask baseboard configuration */
+
+#ifndef __CROS_EC_BASEBOARD_H
+#define __CROS_EC_BASEBOARD_H
+
+/*
+ * By default, enable all console messages excepted HC
+ */
+#define CC_DEFAULT (CC_ALL & ~(BIT(CC_HOSTCMD)))
+
+/* NPCX9 config */
+#define NPCX9_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */
+/*
+ * This defines which pads (GPIO10/11 or GPIO64/65) are connected to
+ * the "UART1" (NPCX_UART_PORT0) controller when used for
+ * CONSOLE_UART.
+ */
+#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 for UART1 */
+
+/* CrOS Board Info */
+#define CONFIG_CBI_EEPROM
+#define CONFIG_BOARD_VERSION_CBI
+#define CONFIG_CRC8
+
+/* EC Defines */
+#define CONFIG_LTO
+#define CONFIG_FPU
+
+/* Verified boot configs */
+#define CONFIG_VBOOT_EFS2
+#define CONFIG_VBOOT_HASH
+#define CONFIG_VSTORE
+#define CONFIG_VSTORE_SLOT_COUNT 1
+
+/* Work around double CR50 reset by waiting in initial power on. */
+#define CONFIG_BOARD_RESET_AFTER_POWER_ON
+
+/* Host communication */
+#define CONFIG_HOST_INTERFACE_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S5
+#define CONFIG_HOST_INTERFACE_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST
+
+/* LED */
+#define CONFIG_LED_COMMON
+
+/* Common charger defines */
+#define CONFIG_CHARGE_MANAGER
+
+/* USBC BC1.2 */
+#define CONFIG_USB_CHARGER
+#define CONFIG_BC12_DETECT_PI3USB9201
+
+/* Support Barrel Jack */
+#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT
+#define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1
+#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 45000
+
+/* Chipset config */
+#define CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540
+#define CONFIG_CHIPSET_RESET_HOOK
+#define CONFIG_CHIPSET_CAN_THROTTLE
+#define CONFIG_CPU_PROCHOT_ACTIVE_LOW
+#define CONFIG_EXTPOWER_GPIO
+#define CONFIG_POWER_S0IX
+#define CONFIG_POWER_S4_RESIDENCY
+#define CONFIG_POWER_SLEEP_FAILURE_DETECTION
+#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
+#define CONFIG_CHIPSET_X86_RSMRST_AFTER_S5
+
+/*
+ * TODO(b/191742284): When DAM enabled coreboot image is flashed on top of DAM
+ * disabled coreboot, S5 exit is taking more than 4 seconds, then EC triggers
+ * system shutdown. This WA deselects CONFIG_BOARD_HAS_RTC_RESET to prevent
+ * EC from system shutdown.
+ */
+/* #define CONFIG_BOARD_HAS_RTC_RESET */
+
+#define CONFIG_CMD_AP_RESET_LOG
+#define CONFIG_HOSTCMD_AP_RESET
+
+/* ADL has new low-power features that requires extra-wide virtual wire
+ * pulses. The EDS specifies 100 microseconds. */
+#undef CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US
+#define CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US 100
+
+/* Buttons */
+#define CONFIG_DEDICATED_RECOVERY_BUTTON
+#define CONFIG_EMULATED_SYSRQ
+#define CONFIG_POWER_BUTTON
+#define CONFIG_POWER_BUTTON_IGNORE_LID
+#define CONFIG_POWER_BUTTON_INIT_IDLE
+#define CONFIG_POWER_BUTTON_X86
+#undef CONFIG_BUTTON_DEBOUNCE
+#define CONFIG_BUTTON_DEBOUNCE (100 * MSEC)
+
+/* Matrix Keyboard Protocol */
+#define CONFIG_MKBP_EVENT
+#define CONFIG_MKBP_INPUT_DEVICES
+#define CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT
+
+/* Thermal features */
+#define CONFIG_DPTF
+#define CONFIG_THROTTLE_AP
+
+#define CONFIG_PWM
+
+/* Enable I2C Support */
+#define CONFIG_I2C
+#define CONFIG_I2C_CONTROLLER
+
+/* UART COMMAND */
+#define CONFIG_CMD_CHARGEN
+
+/* USB Type C and USB PD defines */
+/* Enable the new USB-C PD stack */
+#define CONFIG_USB_PD_TCPMV2
+#define CONFIG_USB_DRP_ACC_TRYSRC
+#define CONFIG_USB_PD_REV30
+
+#define CONFIG_CMD_HCDEBUG
+#define CONFIG_CMD_PPC_DUMP
+#define CONFIG_CMD_TCPC_DUMP
+
+#define CONFIG_USB_POWER_DELIVERY
+#define CONFIG_USB_PD_ALT_MODE
+#define CONFIG_USB_PD_ALT_MODE_DFP
+#define CONFIG_USB_PD_ALT_MODE_UFP
+#define CONFIG_USB_PD_DISCHARGE_PPC
+#define CONFIG_USB_PD_DUAL_ROLE
+#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+#define CONFIG_USB_PD_TCPC_LOW_POWER
+#define CONFIG_USB_PD_TCPM_TCPCI
+#define CONFIG_USB_PD_TCPM_NCT38XX
+
+#define CONFIG_USB_PD_TCPM_MUX
+#define CONFIG_HOSTCMD_PD_CONTROL /* Needed for TCPC FW update */
+#define CONFIG_CMD_USB_PD_PE
+
+/*
+ * The PS8815 TCPC was found to require a 50ms delay to consistently work
+ * with non-PD chargers.  Override the default low-power mode exit delay.
+ */
+#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
+#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (50 * MSEC)
+
+/* Enable USB3.2 DRD */
+#define CONFIG_USB_PD_USB32_DRD
+
+#define CONFIG_USB_PD_TRY_SRC
+#define CONFIG_USB_PD_VBUS_DETECT_TCPC
+
+#define CONFIG_USBC_PPC
+#define CONFIG_USBC_PPC_POLARITY
+#define CONFIG_USBC_PPC_SBU
+#define CONFIG_USBC_PPC_VCONN
+#define CONFIG_USBC_PPC_DEDICATED_INT
+
+#define CONFIG_USBC_SS_MUX
+#define CONFIG_USB_MUX_VIRTUAL
+
+#define CONFIG_USBC_VCONN
+#define CONFIG_USBC_VCONN_SWAP
+
+/* Enabling SOP* communication */
+#define CONFIG_CMD_USB_PD_CABLE
+#define CONFIG_USB_PD_DECODE_SOP
+
+/*
+ * USB ID
+ * This is allocated specifically for Brask
+ * http://google3/hardware/standards/usb/
+ */
+#define CONFIG_USB_PID 0x5058
+/* Device version of product. */
+#define CONFIG_USB_BCD_DEV 0x0000
+
+/* Remove predefined features */
+#undef CONFIG_HIBERNATE
+#undef CONFIG_KEYBOARD_BOOT_KEYS
+#undef CONFIG_KEYBOARD_RUNTIME_KEYS
+#undef CONFIG_LID_SWITCH
+#undef CONFIG_KEYBOARD_VIVALDI
+
+#ifndef __ASSEMBLER__
+
+#include "baseboard_usbc_config.h"
+#include "common.h"
+#include "extpower.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+/*
+ * Configure run-time data structures and operation based on CBI data. This
+ * typically includes customization for changes in the BOARD_VERSION and
+ * FW_CONFIG fields in CBI. This routine is called from the baseboard after
+ * the CBI data has been initialized.
+ */
+__override_proto void board_cbi_init(void);
+
+/*
+ * Initialize the FW_CONFIG from CBI data. If the CBI data is not valid, set the
+ * FW_CONFIG to the board specific defaults.
+ */
+__override_proto void board_init_fw_config(void);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BASEBOARD_H */
diff --git a/baseboard/brask/baseboard_usbc_config.h b/baseboard/brask/baseboard_usbc_config.h
new file mode 100644
index 0000000000..8ebf4f9b6a
--- /dev/null
+++ b/baseboard/brask/baseboard_usbc_config.h
@@ -0,0 +1,19 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* brask family-specific USB-C configuration */
+
+#ifndef __CROS_EC_BASEBOARD_USBC_CONFIG_H
+#define __CROS_EC_BASEBOARD_USBC_CONFIG_H
+
+#include "gpio_signal.h"
+
+/* Common definition for the USB PD interrupt handlers. */
+void bc12_interrupt(enum gpio_signal signal);
+void ppc_interrupt(enum gpio_signal signal);
+void retimer_interrupt(enum gpio_signal signal);
+void tcpc_alert_event(enum gpio_signal signal);
+
+#endif /* __CROS_EC_BASEBOARD_USBC_CONFIG_H */
diff --git a/baseboard/brask/build.mk b/baseboard/brask/build.mk
new file mode 100644
index 0000000000..4b540d94ad
--- /dev/null
+++ b/baseboard/brask/build.mk
@@ -0,0 +1,12 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Brask baseboard specific files build
+#
+
+baseboard-y=
+baseboard-y+=baseboard.o
+baseboard-y+=cbi.o
+baseboard-y+=usb_pd_policy.o
diff --git a/baseboard/brask/cbi.c b/baseboard/brask/cbi.c
new file mode 100644
index 0000000000..0ff0e4c7f7
--- /dev/null
+++ b/baseboard/brask/cbi.c
@@ -0,0 +1,58 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "hooks.h"
+
+#include <stdint.h>
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+
+static uint8_t board_id;
+
+uint8_t get_board_id(void)
+{
+	return board_id;
+}
+
+__overridable void board_cbi_init(void)
+{
+}
+
+__overridable void board_init_fw_config(void)
+{
+}
+
+__overridable void board_init_ssfc(void)
+{
+}
+
+/*
+ * Read CBI from I2C EEPROM and initialize variables for board variants.
+ */
+static void cbi_init(void)
+{
+	uint32_t cbi_val;
+
+	/* Board ID */
+	if (cbi_get_board_version(&cbi_val) != EC_SUCCESS ||
+	    cbi_val > UINT8_MAX)
+		CPRINTS("CBI: Read Board ID failed");
+	else
+		board_id = cbi_val;
+
+	CPRINTS("Board ID: %d", board_id);
+
+	board_init_fw_config();
+
+	board_init_ssfc();
+
+	/* Allow the board project to make runtime changes based on CBI data */
+	board_cbi_init();
+}
+DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_FIRST);
diff --git a/baseboard/brask/cbi.h b/baseboard/brask/cbi.h
new file mode 100644
index 0000000000..219718763f
--- /dev/null
+++ b/baseboard/brask/cbi.h
@@ -0,0 +1,38 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* brask family-specific CBI functions, shared with Zephyr */
+
+#ifndef __CROS_EC_BASEBOARD_CBI_H
+#define __CROS_EC_BASEBOARD_CBI_H
+
+#include "common.h"
+
+/*
+ * Return the board revision number.
+ */
+uint8_t get_board_id(void);
+
+/**
+ * Configure run-time data structures and operation based on CBI data. This
+ * typically includes customization for changes in the BOARD_VERSION and
+ * FW_CONFIG fields in CBI. This routine is called from the baseboard after
+ * the CBI data has been initialized.
+ */
+__override_proto void board_cbi_init(void);
+
+/**
+ * Initialize the FW_CONFIG from CBI data. If the CBI data is not valid, set the
+ * FW_CONFIG to the board specific defaults.
+ */
+__override_proto void board_init_fw_config(void);
+
+/**
+ * Initialize the SSFC from CBI data. If the CBI data is not valid, set the
+ * SSFC to the board specific defaults.
+ */
+__override_proto void board_init_ssfc(void);
+
+#endif /* __CROS_EC_BASEBOARD_CBI_H */
diff --git a/baseboard/brask/usb_pd_policy.c b/baseboard/brask/usb_pd_policy.c
new file mode 100644
index 0000000000..e20ad13f98
--- /dev/null
+++ b/baseboard/brask/usb_pd_policy.c
@@ -0,0 +1,228 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Shared USB-C policy for Brask boards */
+
+#include "charge_manager.h"
+#include "chipset.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "timer.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tbt.h"
+#include "usb_pd_tcpm.h"
+#include "usb_pd_vdo.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#include <stddef.h>
+#include <stdint.h>
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+int pd_check_vconn_swap(int port)
+{
+	/* Only allow vconn swap after the PP5000_Z1 rail is enabled */
+	return gpio_get_level(GPIO_SEQ_EC_DSW_PWROK);
+}
+
+void pd_power_supply_reset(int port)
+{
+	int prev_en;
+
+	prev_en = ppc_is_sourcing_vbus(port);
+
+	/* Disable VBUS. */
+	ppc_vbus_source_enable(port, 0);
+
+	/* Enable discharge if we were previously sourcing 5V */
+	if (prev_en)
+		pd_set_vbus_discharge(port, 1);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	/* Disable charging. */
+	rv = ppc_vbus_sink_enable(port, 0);
+	if (rv)
+		return rv;
+
+	pd_set_vbus_discharge(port, 0);
+
+	/* Provide Vbus. */
+	rv = ppc_vbus_source_enable(port, 1);
+	if (rv)
+		return rv;
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+int board_vbus_source_enabled(int port)
+{
+	/* Ignore non-PD ports (the barrel jack). */
+	if (port >= CONFIG_USB_PD_PORT_MAX_COUNT)
+		return 0;
+	return ppc_is_sourcing_vbus(port);
+}
+
+#ifdef CONFIG_USB_PD_TBT_COMPAT_MODE
+/* ----------------- Vendor Defined Messages ------------------ */
+/* Responses specifically for the enablement of TBT mode in the role of UFP */
+
+#define OPOS_TBT 1
+
+static const union tbt_mode_resp_device vdo_tbt_modes[1] = { {
+	.tbt_alt_mode = 0x0001,
+	.tbt_adapter = TBT_ADAPTER_TBT3,
+	.intel_spec_b0 = 0,
+	.vendor_spec_b0 = 0,
+	.vendor_spec_b1 = 0,
+} };
+
+static const uint32_t vdo_idh = VDO_IDH(1, /* Data caps as USB host     */
+					0, /* Not a USB device   */
+					IDH_PTYPE_PERIPH, 1, /* Supports alt
+								modes */
+					USB_VID_GOOGLE);
+
+static const uint32_t vdo_idh_rev30 =
+	VDO_IDH_REV30(1, /* Data caps as USB host     */
+		      0, /* Not a USB device   */
+		      IDH_PTYPE_PERIPH, 1, /* Supports alt modes */
+		      IDH_PTYPE_DFP_HOST, USB_TYPEC_RECEPTACLE, USB_VID_GOOGLE);
+
+static const uint32_t vdo_product =
+	VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV);
+
+/* TODO(b/168890624): add USB4 to capability once USB4 response implemented */
+static const uint32_t vdo_ufp1 = VDO_UFP1(
+	(VDO_UFP1_CAPABILITY_USB20 | VDO_UFP1_CAPABILITY_USB32),
+	USB_TYPEC_RECEPTACLE, VDO_UFP1_ALT_MODE_TBT3, USB_R30_SS_U40_GEN3);
+
+static const uint32_t vdo_dfp =
+	VDO_DFP((VDO_DFP_HOST_CAPABILITY_USB20 | VDO_DFP_HOST_CAPABILITY_USB32 |
+		 VDO_DFP_HOST_CAPABILITY_USB4),
+		USB_TYPEC_RECEPTACLE, 1 /* Port 1 */);
+
+static int svdm_tbt_compat_response_identity(int port, uint32_t *payload)
+{
+	/* TODO(b/154962766): Get an XID */
+	payload[VDO_I(CSTAT)] = VDO_CSTAT(0);
+	payload[VDO_I(PRODUCT)] = vdo_product;
+
+	if (pd_get_rev(port, TCPCI_MSG_SOP) == PD_REV30) {
+		/* PD Revision 3.0 */
+		payload[VDO_I(IDH)] = vdo_idh_rev30;
+		payload[VDO_I(PTYPE_UFP1_VDO)] = vdo_ufp1;
+		/* TODO(b/181620145): Customize for brya */
+		payload[VDO_I(PTYPE_UFP2_VDO)] = 0;
+		payload[VDO_I(PTYPE_DFP_VDO)] = vdo_dfp;
+		return VDO_I(PTYPE_DFP_VDO) + 1;
+	}
+
+	/* PD Revision 2.0 */
+	payload[VDO_I(IDH)] = vdo_idh;
+	return VDO_I(PRODUCT) + 1;
+}
+
+static int svdm_tbt_compat_response_svids(int port, uint32_t *payload)
+{
+	payload[1] = VDO_SVID(USB_VID_INTEL, 0);
+	return 2;
+}
+
+static int svdm_tbt_compat_response_modes(int port, uint32_t *payload)
+{
+	if (PD_VDO_VID(payload[0]) == USB_VID_INTEL) {
+		memcpy(payload + 1, vdo_tbt_modes, sizeof(vdo_tbt_modes));
+		return ARRAY_SIZE(vdo_tbt_modes) + 1;
+	} else {
+		return 0; /* NAK */
+	}
+}
+
+/* Track whether we've been enabled to ACK TBT EnterModes requests */
+static bool tbt_ufp_ack_allowed[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+__override enum ec_status
+board_set_tbt_ufp_reply(int port, enum typec_tbt_ufp_reply reply)
+{
+	/* Note: Host command has already bounds-checked port */
+	if (reply == TYPEC_TBT_UFP_REPLY_ACK)
+		tbt_ufp_ack_allowed[port] = true;
+	else if (reply == TYPEC_TBT_UFP_REPLY_NAK)
+		tbt_ufp_ack_allowed[port] = false;
+	else
+		return EC_RES_INVALID_PARAM;
+
+	return EC_RES_SUCCESS;
+}
+
+static int svdm_tbt_compat_response_enter_mode(int port, uint32_t *payload)
+{
+	mux_state_t mux_state = 0;
+
+	/* Do not enter mode while CPU is off. */
+	if (chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF))
+		return 0; /* NAK */
+
+	/* Do not enter mode while policy disallows it */
+	if (!tbt_ufp_ack_allowed[port])
+		return 0; /* NAK */
+
+	if ((PD_VDO_VID(payload[0]) != USB_VID_INTEL) ||
+	    (PD_VDO_OPOS(payload[0]) != OPOS_TBT))
+		return 0; /* NAK */
+
+	mux_state = usb_mux_get(port);
+	/*
+	 * Ref: USB PD 3.0 Spec figure 6-21 Successful Enter Mode sequence
+	 * UFP (responder) should be in USB mode or safe mode before entering a
+	 * Mode that requires the reconfiguring of any pins.
+	 */
+	if ((mux_state & USB_PD_MUX_USB_ENABLED) ||
+	    (mux_state & USB_PD_MUX_SAFE_MODE)) {
+		pd_ufp_set_enter_mode(port, payload);
+		set_tbt_compat_mode_ready(port);
+
+		/*
+		 * Ref: Above figure 6-21: UFP (responder) should be in the new
+		 * mode before sending the ACK.  However, our mux set sequence
+		 * may exceed tVDMEnterMode, so wait as long as we can
+		 * before sending the reply without violating that timer.
+		 */
+		if (!usb_mux_set_completed(port))
+			usleep(PD_T_VDM_E_MODE / 2);
+
+		CPRINTS("UFP Enter TBT mode");
+		return 1; /* ACK */
+	}
+
+	CPRINTS("UFP failed to enter TBT mode(mux=0x%x)", mux_state);
+	return 0;
+}
+
+const struct svdm_response svdm_rsp = {
+	.identity = &svdm_tbt_compat_response_identity,
+	.svids = &svdm_tbt_compat_response_svids,
+	.modes = &svdm_tbt_compat_response_modes,
+	.enter_mode = &svdm_tbt_compat_response_enter_mode,
+	.amode = NULL,
+	.exit_mode = NULL,
+};
+#endif /* CONFIG_USB_PD_TBT_COMPAT_MODE */
diff --git a/baseboard/brya/baseboard.c b/baseboard/brya/baseboard.c
new file mode 100644
index 0000000000..e65a384578
--- /dev/null
+++ b/baseboard/brya/baseboard.c
@@ -0,0 +1,45 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "chipset.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "gpio_signal.h"
+#include "keyboard_scan.h"
+#include "tablet_mode.h"
+
+/* Wake up pins */
+const enum gpio_signal hibernate_wake_pins[] = {
+	GPIO_ACOK_OD,
+	GPIO_GSC_EC_PWR_BTN_ODL,
+	GPIO_LID_OPEN,
+};
+const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
+
+/* This callback disables keyboard when convertibles are fully open */
+__override void lid_angle_peripheral_enable(int enable)
+{
+	/*
+	 * If the lid is in tablet position via other sensors,
+	 * ignore the lid angle, which might be faulty then
+	 * disable keyboard.
+	 */
+#ifdef CONFIG_TABLET_MODE
+	if (tablet_get_mode())
+		enable = 0;
+#endif
+
+	if (enable) {
+		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
+	} else {
+		/*
+		 * When the chipset is on, the EC keeps the keyboard enabled and
+		 * Ensure that the chipset is off before disabling the keyboard.
+		 * the AP decides whether to ignore input devices or not.
+		 */
+		if (!chipset_in_state(CHIPSET_STATE_ON))
+			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
+	}
+}
diff --git a/baseboard/brya/baseboard.h b/baseboard/brya/baseboard.h
new file mode 100644
index 0000000000..22a07d761d
--- /dev/null
+++ b/baseboard/brya/baseboard.h
@@ -0,0 +1,260 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Brya baseboard configuration */
+
+#ifndef __CROS_EC_BASEBOARD_H
+#define __CROS_EC_BASEBOARD_H
+
+/*
+ * By default, enable all console messages excepted HC, ACPI and event:
+ * The sensor stack is generating a lot of activity.
+ */
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
+#undef CONFIG_HOSTCMD_DEBUG_MODE
+#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
+
+/* NPCX9 config */
+#define NPCX9_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */
+/*
+ * This defines which pads (GPIO10/11 or GPIO64/65) are connected to
+ * the "UART1" (NPCX_UART_PORT0) controller when used for
+ * CONSOLE_UART.
+ */
+#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 for UART1 */
+
+/* EC Defines */
+#define CONFIG_LTO
+#define CONFIG_CBI_EEPROM
+#define CONFIG_BOARD_VERSION_CBI
+#define CONFIG_CRC8
+#define CONFIG_DPTF
+#define CONFIG_FPU
+
+/* Verified boot configs */
+#define CONFIG_VBOOT_EFS2
+#define CONFIG_VBOOT_HASH
+#define CONFIG_VSTORE
+#define CONFIG_VSTORE_SLOT_COUNT 1
+
+#define CONFIG_HIBERNATE_PSL
+
+/* Work around double CR50 reset by waiting in initial power on. */
+#define CONFIG_BOARD_RESET_AFTER_POWER_ON
+
+/* Host communication */
+#define CONFIG_HOST_INTERFACE_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S5
+
+/*
+ * TODO(b/179648721): implement sensors
+ */
+#define CONFIG_TABLET_MODE
+#define CONFIG_TABLET_MODE_SWITCH
+#define CONFIG_GMR_TABLET_MODE
+
+#define CONFIG_MKBP_EVENT
+/* GPIO is needed for EC events to show up in eventlog - b/222375516 */
+#define CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT
+#define CONFIG_MKBP_INPUT_DEVICES
+
+/* LED */
+#define CONFIG_LED_COMMON
+
+/* Common charger defines */
+#define CONFIG_CHARGE_MANAGER
+#define CONFIG_CHARGER
+#define CONFIG_CHARGER_DISCHARGE_ON_AC
+#define CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT 512
+
+#define CONFIG_CMD_CHARGER_DUMP
+
+#define CONFIG_USB_CHARGER
+#define CONFIG_BC12_DETECT_PI3USB9201
+
+/*
+ * Don't allow the system to boot to S0 when the battery is low and unable to
+ * communicate on locked systems (which haven't PD negotiated)
+ */
+#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT 15000
+#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 15001
+
+/* Common battery defines */
+#define CONFIG_BATTERY_SMART
+#define CONFIG_BATTERY_FUEL_GAUGE
+#define CONFIG_BATTERY_CUT_OFF
+#define CONFIG_BATTERY_PRESENT_CUSTOM
+#define CONFIG_BATTERY_HW_PRESENT_CUSTOM
+#define CONFIG_BATTERY_REVIVE_DISCONNECT
+#define CONFIG_CMD_BATT_MFG_ACCESS
+/*
+ * Enable support for battery hostcmd, supporting longer strings.
+ * support for EC_CMD_BATTERY_GET_STATIC version 1.
+ */
+#define CONFIG_BATTERY_V2
+#define CONFIG_BATTERY_COUNT 1
+#define CONFIG_HOSTCMD_BATTERY_V2
+
+/* Chipset config */
+#define CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540
+#define CONFIG_CHIPSET_X86_RSMRST_AFTER_S5
+
+#define CONFIG_CHIPSET_RESET_HOOK
+#define CONFIG_CPU_PROCHOT_ACTIVE_LOW
+#define CONFIG_EXTPOWER_GPIO
+#define CONFIG_POWER_BUTTON
+#define CONFIG_POWER_BUTTON_X86
+#define CONFIG_POWER_S0IX
+#define CONFIG_POWER_S4_RESIDENCY
+#define CONFIG_POWER_SLEEP_FAILURE_DETECTION
+#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
+#define CONFIG_LOW_POWER_IDLE
+
+#define CONFIG_HOST_INTERFACE_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST
+
+#define CONFIG_BOARD_HAS_RTC_RESET
+#undef CONFIG_S5_EXIT_WAIT
+#define CONFIG_S5_EXIT_WAIT 10
+
+#define CONFIG_CMD_AP_RESET_LOG
+#define CONFIG_HOSTCMD_AP_RESET
+
+/* ADL has new lower-power features that require extra-wide virtual wire
+ * pulses. The EDS specifies 100 microseconds. */
+#undef CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US
+#define CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US 100
+
+/* Buttons / Switches */
+#define CONFIG_VOLUME_BUTTONS
+#define CONFIG_SWITCH
+
+/* Common Keyboard Defines */
+#define CONFIG_CMD_KEYBOARD
+
+#define CONFIG_KEYBOARD_COL2_INVERTED
+#define CONFIG_KEYBOARD_KEYPAD
+#define CONFIG_KEYBOARD_PROTOCOL_8042
+#ifdef CONFIG_KEYBOARD_VIVALDI
+#define CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2
+#else
+#define CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI3
+#endif
+
+/* Thermal features */
+#define CONFIG_THROTTLE_AP
+#define CONFIG_CHIPSET_CAN_THROTTLE
+
+#define CONFIG_PWM
+
+/* Enable I2C Support */
+#define CONFIG_I2C
+#define CONFIG_I2C_CONTROLLER
+
+/* EDP back-light control defines */
+#define CONFIG_BACKLIGHT_LID
+
+/* UART COMMAND */
+#define CONFIG_CMD_CHARGEN
+
+/* USB Type C and USB PD defines */
+/* Enable the new USB-C PD stack */
+#define CONFIG_USB_PD_TCPMV2
+#define CONFIG_USB_DRP_ACC_TRYSRC
+#define CONFIG_USB_PD_REV30
+
+#define CONFIG_CMD_HCDEBUG
+#define CONFIG_CMD_PPC_DUMP
+#define CONFIG_CMD_TCPC_DUMP
+
+#define CONFIG_USB_POWER_DELIVERY
+#define CONFIG_USB_PD_ALT_MODE
+#define CONFIG_USB_PD_ALT_MODE_DFP
+#define CONFIG_USB_PD_ALT_MODE_UFP
+#define CONFIG_USB_PD_DISCHARGE_PPC
+#define CONFIG_USB_PD_DUAL_ROLE
+#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+#define CONFIG_USB_PD_TCPC_LOW_POWER
+#define CONFIG_USB_PD_TCPM_TCPCI
+#define CONFIG_USB_PD_TCPM_NCT38XX
+
+#define CONFIG_USB_PD_TCPM_MUX
+#define CONFIG_HOSTCMD_PD_CONTROL /* Needed for TCPC FW update */
+#define CONFIG_CMD_USB_PD_PE
+
+/*
+ * The PS8815 TCPC was found to require a 50ms delay to consistently work
+ * with non-PD chargers.  Override the default low-power mode exit delay.
+ */
+#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
+#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (50 * MSEC)
+
+/* Enable USB3.2 DRD */
+#define CONFIG_USB_PD_USB32_DRD
+
+#define CONFIG_USB_PD_TRY_SRC
+#define CONFIG_USB_PD_VBUS_DETECT_TCPC
+
+#define CONFIG_USBC_PPC
+/* Note - SN5S330 support automatically adds
+ * CONFIG_USBC_PPC_POLARITY
+ * CONFIG_USBC_PPC_SBU
+ * CONFIG_USBC_PPC_VCONN
+ */
+#define CONFIG_USBC_PPC_DEDICATED_INT
+
+#define CONFIG_USBC_SS_MUX
+#define CONFIG_USB_MUX_VIRTUAL
+
+#define CONFIG_USBC_VCONN
+#define CONFIG_USBC_VCONN_SWAP
+
+/* Enabling SOP* communication */
+#define CONFIG_CMD_USB_PD_CABLE
+#define CONFIG_USB_PD_DECODE_SOP
+
+/*
+ * USB ID
+ * This is allocated specifically for Brya
+ * http://google3/hardware/standards/usb/
+ */
+#define CONFIG_USB_PID 0x504F
+/* Device version of product. */
+#define CONFIG_USB_BCD_DEV 0x0000
+
+/*
+ * These stack sizes were determined using "make analyzestack" for brya
+ * and include about 15% headroom. Sizes are rounded to multiples of 64
+ * bytes. Task stack sizes not listed here use more generic values (see
+ * ec.tasklist).
+ */
+#define BASEBOARD_CHARGER_TASK_STACK_SIZE 1088
+#define BASEBOARD_CHG_RAMP_TASK_STACK_SIZE 1088
+#define BASEBOARD_CHIPSET_TASK_STACK_SIZE 1152
+#define BASEBOARD_PD_INT_TASK_STACK_SIZE 800
+#define BASEBOARD_PD_TASK_STACK_SIZE 1216
+#define BASEBOARD_POWERBTN_TASK_STACK_SIZE 1088
+#define BASEBOARD_RGBKBD_TASK_STACK_SIZE 2048
+
+#ifndef __ASSEMBLER__
+
+#include "baseboard_usbc_config.h"
+#include "cbi.h"
+#include "common.h"
+#include "extpower.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+/*
+ * Check battery disconnect state.
+ * This function will return if battery is initialized or not.
+ * @return true - initialized. false - not.
+ */
+__override_proto bool board_battery_is_initialized(void);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BASEBOARD_H */
diff --git a/baseboard/brya/baseboard_usbc_config.h b/baseboard/brya/baseboard_usbc_config.h
new file mode 100644
index 0000000000..17f1fe6b06
--- /dev/null
+++ b/baseboard/brya/baseboard_usbc_config.h
@@ -0,0 +1,21 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* brya family-specific USB-C configuration */
+
+#ifndef __CROS_EC_BASEBOARD_USBC_CONFIG_H
+#define __CROS_EC_BASEBOARD_USBC_CONFIG_H
+
+#include "gpio_signal.h"
+
+/* Common definition for the USB PD interrupt handlers. */
+#ifdef CONFIG_USB_CHARGER
+void bc12_interrupt(enum gpio_signal signal);
+#endif
+void ppc_interrupt(enum gpio_signal signal);
+void retimer_interrupt(enum gpio_signal signal);
+void tcpc_alert_event(enum gpio_signal signal);
+
+#endif /* __CROS_EC_BASEBOARD_USBC_CONFIG_H */
diff --git a/baseboard/brya/battery_presence.c b/baseboard/brya/battery_presence.c
new file mode 100644
index 0000000000..ad055c1d12
--- /dev/null
+++ b/baseboard/brya/battery_presence.c
@@ -0,0 +1,70 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Common battery presence checking for Brya family.
+ * Each board should implement board_battery_info[] to define the specific
+ * battery packs supported.
+ */
+#include "battery.h"
+#include "battery_smart.h"
+#include "common.h"
+
+#include <stdbool.h>
+
+static enum battery_present batt_pres_prev = BP_NOT_SURE;
+
+__overridable bool board_battery_is_initialized(void)
+{
+	int batt_status;
+
+	return battery_status(&batt_status) != EC_SUCCESS ?
+		       false :
+		       !!(batt_status & STATUS_INITIALIZED);
+}
+
+/*
+ * Physical detection of battery.
+ */
+static enum battery_present battery_check_present_status(void)
+{
+	enum battery_present batt_pres;
+
+	if (battery_is_cut_off())
+		return BP_NO;
+
+	/* Get the physical hardware status */
+	batt_pres = battery_hw_present();
+
+	/*
+	 * If the battery is not physically connected, then no need to perform
+	 * any more checks.
+	 */
+	if (batt_pres == BP_NO)
+		return BP_NO;
+
+	/*
+	 * If the battery is present now and was present last time we checked,
+	 * return early.
+	 */
+	if ((batt_pres == BP_YES) && (batt_pres == batt_pres_prev))
+		return BP_YES;
+
+	/*
+	 * Check battery initialization. If the battery is not initialized,
+	 * then return BP_NOT_SURE. Battery could be in ship
+	 * mode and might require pre-charge current to wake it up. BP_NO is not
+	 * returned here because charger state machine will not provide
+	 * pre-charge current assuming that battery is not present.
+	 */
+	if (!board_battery_is_initialized())
+		return BP_NOT_SURE;
+
+	return BP_YES;
+}
+
+enum battery_present battery_is_present(void)
+{
+	batt_pres_prev = battery_check_present_status();
+	return batt_pres_prev;
+}
diff --git a/baseboard/brya/build.mk b/baseboard/brya/build.mk
new file mode 100644
index 0000000000..c6e93c63f2
--- /dev/null
+++ b/baseboard/brya/build.mk
@@ -0,0 +1,14 @@
+# -*- makefile -*-
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Brya baseboard specific files build
+#
+
+baseboard-y=
+baseboard-y+=baseboard.o
+baseboard-y+=battery_presence.o
+baseboard-y+=cbi.o
+baseboard-$(HAS_TASK_PROCHOT)+=prochot.o
+baseboard-y+=usb_pd_policy.o
diff --git a/baseboard/brya/cbi.c b/baseboard/brya/cbi.c
new file mode 100644
index 0000000000..f6e5034561
--- /dev/null
+++ b/baseboard/brya/cbi.c
@@ -0,0 +1,58 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "hooks.h"
+
+#include <stdint.h>
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+
+static uint8_t board_id;
+
+uint8_t get_board_id(void)
+{
+	return board_id;
+}
+
+__overridable void board_cbi_init(void)
+{
+}
+
+__overridable void board_init_fw_config(void)
+{
+}
+
+__overridable void board_init_ssfc(void)
+{
+}
+
+/*
+ * Read CBI from I2C EEPROM and initialize variables for board variants.
+ */
+static void cbi_init(void)
+{
+	uint32_t cbi_val;
+
+	/* Board ID */
+	if (cbi_get_board_version(&cbi_val) != EC_SUCCESS ||
+	    cbi_val > UINT8_MAX)
+		CPRINTS("CBI: Read Board ID failed");
+	else
+		board_id = cbi_val;
+
+	CPRINTS("Board ID: %d", board_id);
+
+	board_init_fw_config();
+
+	board_init_ssfc();
+
+	/* Allow the board project to make runtime changes based on CBI data */
+	board_cbi_init();
+}
+DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_FIRST);
diff --git a/baseboard/brya/cbi.h b/baseboard/brya/cbi.h
new file mode 100644
index 0000000000..37e02806bd
--- /dev/null
+++ b/baseboard/brya/cbi.h
@@ -0,0 +1,38 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* brya family-specific CBI functions, shared with Zephyr */
+
+#ifndef __CROS_EC_BASEBOARD_CBI_H
+#define __CROS_EC_BASEBOARD_CBI_H
+
+#include "common.h"
+
+/*
+ * Return the board revision number.
+ */
+uint8_t get_board_id(void);
+
+/**
+ * Configure run-time data structures and operation based on CBI data. This
+ * typically includes customization for changes in the BOARD_VERSION and
+ * FW_CONFIG fields in CBI. This routine is called from the baseboard after
+ * the CBI data has been initialized.
+ */
+__override_proto void board_cbi_init(void);
+
+/**
+ * Initialize the FW_CONFIG from CBI data. If the CBI data is not valid, set the
+ * FW_CONFIG to the board specific defaults.
+ */
+__override_proto void board_init_fw_config(void);
+
+/**
+ * Initialize the SSFC from CBI data. If the CBI data is not valid, set the
+ * SSFC to the board specific defaults.
+ */
+__override_proto void board_init_ssfc(void);
+
+#endif /* __CROS_EC_BASEBOARD_CBI_H */
diff --git a/baseboard/brya/charger_bq25720.c b/baseboard/brya/charger_bq25720.c
new file mode 100644
index 0000000000..827152e115
--- /dev/null
+++ b/baseboard/brya/charger_bq25720.c
@@ -0,0 +1,82 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/charger/bq25710.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+#ifndef CONFIG_ZEPHYR
+/* Charger Chip Configuration */
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = BQ25710_SMBUS_ADDR1_FLAGS,
+		.drv = &bq25710_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CHARGER_NUM);
+#endif
+
+int board_set_active_charge_port(int port)
+{
+	int is_valid_port = board_is_usb_pd_port_present(port);
+	int i;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTSUSB("Disabling all charger ports");
+
+		/* Disable all ports. */
+		for (i = 0; i < ppc_cnt; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (ppc_vbus_sink_enable(i, 0))
+				CPRINTSUSB("Disabling C%d as sink failed.", i);
+		}
+
+		return EC_SUCCESS;
+	} else if (!is_valid_port) {
+		return EC_ERROR_INVAL;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (ppc_is_sourcing_vbus(port)) {
+		CPRINTFUSB("Skip enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTSUSB("New charge port: C%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < ppc_cnt; i++) {
+		if (i == port)
+			continue;
+
+		if (ppc_vbus_sink_enable(i, 0))
+			CPRINTSUSB("C%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTSUSB("C%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/baseboard/brya/prochot.c b/baseboard/brya/prochot.c
new file mode 100644
index 0000000000..f89ec5a263
--- /dev/null
+++ b/baseboard/brya/prochot.c
@@ -0,0 +1,266 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "adc.h"
+#include "battery.h"
+#include "battery_smart.h"
+#include "charge_manager.h"
+#include "charger.h"
+#include "console.h"
+#include "driver/charger/bq257x0_regs.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "math_util.h"
+#include "task.h"
+
+/* Console output macros */
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+
+#define ADT_RATING_W (PD_MAX_POWER_MW / 1000)
+#define PROCHOT_EVENT_200MS_TICK TASK_EVENT_CUSTOM_BIT(0)
+
+struct batt_para {
+	int battery_continuous_discharge_mw;
+	int battery_design_mWh;
+	int flags;
+	int state_of_charge;
+};
+
+struct batt_para batt_params;
+
+static int cal_sys_watt(void)
+{
+	int adapter_voltage_v;
+	int IDPM;
+	int Vacpacn;
+	int V_iadpt;
+	int W_adpt;
+
+	Vacpacn = adc_read_channel(ADC_IADPT);
+
+	/* the ratio selectable through IADPT_GAIN bit. */
+	V_iadpt = Vacpacn * 1000 / 40;
+
+	IDPM = V_iadpt / CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC;
+
+	adapter_voltage_v = charge_manager_get_charger_voltage() / 1000;
+
+	W_adpt = IDPM * adapter_voltage_v * PROCHOT_ADAPTER_WATT_RATIO / 100;
+
+	return W_adpt;
+}
+
+static int get_batt_parameter(void)
+{
+	int battery_voltage;
+	int battery_current;
+	int battery_design_voltage_mv;
+	int battery_design_capacity_mAh;
+	int rv = 0;
+
+	batt_params.flags = 0;
+
+	/* read battery voltage */
+	if (sb_read(SB_VOLTAGE, &battery_voltage))
+		batt_params.flags |= BATT_FLAG_BAD_VOLTAGE;
+
+	/* Battery_current sometimes return a very huge number
+	 * and cause prochot keep toggling so add (int16_t) to guard it.
+	 */
+	if (sb_read(SB_CURRENT, &battery_current))
+		batt_params.flags |= BATT_FLAG_BAD_CURRENT;
+	else
+		battery_current = (int16_t)battery_current;
+
+	/* calculate battery wattage and convert to mW */
+	batt_params.battery_continuous_discharge_mw =
+		(battery_voltage * battery_current) / 1000;
+
+	rv |= sb_read(SB_DESIGN_VOLTAGE, &battery_design_voltage_mv);
+	rv |= sb_read(SB_DESIGN_CAPACITY, &battery_design_capacity_mAh);
+	batt_params.battery_design_mWh =
+		(battery_design_voltage_mv * battery_design_capacity_mAh) /
+		1000;
+
+	if (sb_read(SB_RELATIVE_STATE_OF_CHARGE, &batt_params.state_of_charge))
+		batt_params.flags |= BATT_FLAG_BAD_STATE_OF_CHARGE;
+
+	return (batt_params.flags || rv);
+}
+
+static int get_chg_watt(void)
+{
+	int adapter_current_ma;
+	int adapter_voltage_mv;
+	int adapter_wattage;
+
+	/* Get adapter wattage */
+	adapter_current_ma = charge_manager_get_charger_current();
+	adapter_voltage_mv = charge_manager_get_charger_voltage();
+	adapter_wattage = adapter_current_ma * adapter_voltage_mv / 1000 / 1000;
+
+	return adapter_wattage;
+}
+
+static int set_register_charge_option(void)
+{
+	int reg;
+	int rv;
+
+	rv = i2c_read16(I2C_PORT_CHARGER, BQ25710_SMBUS_ADDR1_FLAGS,
+			BQ25710_REG_CHARGE_OPTION_0, &reg);
+	if (rv == EC_SUCCESS) {
+		reg = SET_BQ_FIELD(BQ257X0, CHARGE_OPTION_0, IADP_GAIN, 1, reg);
+		/* if AC only, disable IDPM,
+		 * because it will cause charger keep asserting PROCHOT
+		 */
+		if (!battery_hw_present())
+			reg = SET_BQ_FIELD(BQ257X0, CHARGE_OPTION_0, EN_IDPM, 0,
+					   reg);
+		else
+			reg = SET_BQ_FIELD(BQ257X0, CHARGE_OPTION_0, EN_IDPM, 1,
+					   reg);
+	} else {
+		CPRINTS("Failed to read bq25720");
+		return rv;
+	}
+
+	return i2c_write16(I2C_PORT_CHARGER, BQ25710_SMBUS_ADDR1_FLAGS,
+			   BQ25710_REG_CHARGE_OPTION_0, reg);
+}
+
+static void assert_prochot(void)
+{
+	int adapter_wattage;
+	int adpt_mw;
+	int total_W;
+
+	/* Set 0x12 bit4=1 */
+	if (set_register_charge_option()) {
+		CPRINTS("Failed to set bq25720");
+		return;
+	}
+
+	/* Calculate actual system W */
+	adpt_mw = cal_sys_watt();
+
+	/* If any battery flag is set and no AC, skip this cycle and hope
+	 * the next cycle succeeds
+	 */
+	if (get_batt_parameter() && !extpower_is_present())
+		return;
+
+	/* When battery is discharging, the battery current will be negative */
+	if (batt_params.battery_continuous_discharge_mw < 0) {
+		total_W = adpt_mw +
+			  ABS(batt_params.battery_continuous_discharge_mw);
+	} else {
+		/* we won't assert prochot when battery is charging. */
+		total_W = adpt_mw;
+	}
+	total_W /= 1000;
+
+	/* Get adapter wattage */
+	adapter_wattage = get_chg_watt();
+
+	/*
+	 * no AC, don't assert PROCHOT.
+	 * If AC exists, PROCHOT will only be asserted when the battery
+	 * is physical present and the battery wattage is over 95% of
+	 * the max continue discharge current of battery spec.
+	 * When the battery wattage is lower than 85% of the max
+	 * continue discharge current of battery spec, PROCHOT will be
+	 * deasserted.
+	 */
+	if (!extpower_is_present()) {
+		if (!battery_hw_present()) {
+			gpio_set_level(GPIO_EC_PROCHOT_ODL, 1);
+		} else {
+			batt_params.battery_continuous_discharge_mw = ABS(
+				batt_params.battery_continuous_discharge_mw);
+			if ((batt_params.battery_continuous_discharge_mw /
+			     1000) > BATT_MAX_CONTINUE_DISCHARGE_WATT *
+					     PROCHOT_ASSERTION_BATTERY_RATIO /
+					     100)
+				gpio_set_level(GPIO_EC_PROCHOT_ODL, 0);
+			else if ((batt_params.battery_continuous_discharge_mw /
+				  1000) <
+				 BATT_MAX_CONTINUE_DISCHARGE_WATT *
+					 PROCHOT_DEASSERTION_BATTERY_RATIO /
+					 100)
+				gpio_set_level(GPIO_EC_PROCHOT_ODL, 1);
+		}
+		return;
+	}
+
+	if (adapter_wattage >= ADT_RATING_W) {
+		/* if adapter >= 60W */
+		/* if no battery or battery < 10% */
+		if (!battery_hw_present() ||
+		    batt_params.state_of_charge <= 10) {
+			if (total_W >
+			    ADT_RATING_W * PROCHOT_ASSERTION_PD_RATIO / 100)
+				gpio_set_level(GPIO_EC_PROCHOT_ODL, 0);
+			else if (total_W <=
+				 ADT_RATING_W * PROCHOT_DEASSERTION_PD_RATIO /
+					 100)
+				gpio_set_level(GPIO_EC_PROCHOT_ODL, 1);
+		} else {
+			/* AC + battery */
+			if (total_W >
+			    (ADT_RATING_W + BATT_MAX_CONTINUE_DISCHARGE_WATT))
+				gpio_set_level(GPIO_EC_PROCHOT_ODL, 0);
+			else if (total_W <
+				 (ADT_RATING_W +
+				  BATT_MAX_CONTINUE_DISCHARGE_WATT) *
+					 PROCHOT_DEASSERTION_PD_BATTERY_RATIO /
+					 100)
+				gpio_set_level(GPIO_EC_PROCHOT_ODL, 1);
+		}
+	} else {
+		/* if adapter < 60W */
+		/* if no battery or battery < 10% */
+		if (!battery_hw_present() ||
+		    batt_params.state_of_charge <= 10) {
+			if (total_W > (adapter_wattage *
+				       PROCHOT_ASSERTION_ADAPTER_RATIO / 100))
+				gpio_set_level(GPIO_EC_PROCHOT_ODL, 0);
+			else if (total_W <=
+				 (adapter_wattage *
+				  PROCHOT_DEASSERTION_ADAPTER_RATIO / 100))
+				gpio_set_level(GPIO_EC_PROCHOT_ODL, 1);
+		} else {
+			/* AC + battery */
+			if (total_W > (adapter_wattage +
+				       BATT_MAX_CONTINUE_DISCHARGE_WATT))
+				gpio_set_level(GPIO_EC_PROCHOT_ODL, 0);
+			else if (total_W <
+				 (adapter_wattage +
+				  (BATT_MAX_CONTINUE_DISCHARGE_WATT *
+				   PROCHOT_DEASSERTION_ADAPTER_BATT_RATIO /
+				   100)))
+				gpio_set_level(GPIO_EC_PROCHOT_ODL, 1);
+		}
+	}
+}
+
+/* Called by hook task every 200 ms */
+static void control_prochot_tick(void)
+{
+	task_set_event(TASK_ID_PROCHOT, PROCHOT_EVENT_200MS_TICK);
+}
+DECLARE_HOOK(HOOK_TICK, control_prochot_tick, HOOK_PRIO_DEFAULT);
+
+void prochot_task(void *u)
+{
+	uint32_t evt;
+
+	while (1) {
+		evt = task_wait_event(-1);
+
+		if (evt & PROCHOT_EVENT_200MS_TICK)
+			assert_prochot();
+	}
+}
diff --git a/baseboard/brya/relevant-paths.txt b/baseboard/brya/relevant-paths.txt
new file mode 100644
index 0000000000..6133d9947f
--- /dev/null
+++ b/baseboard/brya/relevant-paths.txt
@@ -0,0 +1,27 @@
+# Here you can place files of interest to be included in the commit message for
+# merge commits to firmware-brya-14505.B
+#
+# Brya branching strategy is to merge all changes from ToT on a weekly basis.
+# No separate cherry-picks allowed for EC repo in the firmware branch.
+# How to perform a merge:
+# $ cd /path/to/src/platform/ec
+# $ git checkout cros/main
+# $ util/update_release_branch.py --baseboard brya --relevant_paths_file
+#   baseboard/brya/relevant-paths.txt firmware-brya-14505.B-main
+# $ make buildall
+# $ repo upload --cbr . --no-verify
+# Remove the cq-orchestrator line form the commit message
+# Assign one of Brya EC owners as a reviewer
+#
+driver/bc12/pi3usb9201_public.*
+driver/charger/bq25710.*
+driver/ppc/nx20p348x.*
+driver/ppc/syv682x_public.*
+driver/retimer/bb_retimer_public.*
+driver/tcpm/nct38xx.*
+driver/tcpm/ps8xxx_public.*
+driver/tcpm/tcpci.*
+include/power/alderlake*
+include/intel_x86.h
+power/alderlake*
+power/intel_x86.c
diff --git a/baseboard/brya/usb_pd_policy.c b/baseboard/brya/usb_pd_policy.c
new file mode 100644
index 0000000000..377ef0462e
--- /dev/null
+++ b/baseboard/brya/usb_pd_policy.c
@@ -0,0 +1,244 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Shared USB-C policy for Brya boards */
+
+#include "charge_manager.h"
+#include "chipset.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "timer.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tbt.h"
+#include "usb_pd_tcpm.h"
+#include "usb_pd_vdo.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#include <stddef.h>
+#include <stdint.h>
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+int pd_check_vconn_swap(int port)
+{
+	/* Only allow vconn swap after the PP5000_Z1 rail is enabled */
+	return gpio_get_level(GPIO_SEQ_EC_DSW_PWROK);
+}
+
+void pd_power_supply_reset(int port)
+{
+	int prev_en;
+
+	prev_en = ppc_is_sourcing_vbus(port);
+
+	/* Disable VBUS. */
+	ppc_vbus_source_enable(port, 0);
+
+	/* Enable discharge if we were previously sourcing 5V */
+	if (prev_en)
+		pd_set_vbus_discharge(port, 1);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	/* Disable charging. */
+	rv = ppc_vbus_sink_enable(port, 0);
+	if (rv)
+		return rv;
+
+	pd_set_vbus_discharge(port, 0);
+
+	/* Provide Vbus. */
+	rv = ppc_vbus_source_enable(port, 1);
+	if (rv)
+		return rv;
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+int board_vbus_source_enabled(int port)
+{
+	/* BJ port is always sink. */
+	if (port >= CONFIG_USB_PD_PORT_MAX_COUNT)
+		return 0;
+	return ppc_is_sourcing_vbus(port);
+}
+
+#ifdef CONFIG_USB_PD_TBT_COMPAT_MODE
+/* ----------------- Vendor Defined Messages ------------------ */
+/* Responses specifically for the enablement of TBT mode in the role of UFP */
+
+#define OPOS_TBT 1
+
+static const union tbt_mode_resp_device vdo_tbt_modes[1] = { {
+	.tbt_alt_mode = 0x0001,
+	.tbt_adapter = TBT_ADAPTER_TBT3,
+	.intel_spec_b0 = 0,
+	.vendor_spec_b0 = 0,
+	.vendor_spec_b1 = 0,
+} };
+
+static const uint32_t vdo_idh = VDO_IDH(1, /* Data caps as USB host     */
+					0, /* Not a USB device   */
+					IDH_PTYPE_PERIPH, 1, /* Supports alt
+								modes */
+					USB_VID_GOOGLE);
+
+static const uint32_t vdo_idh_rev30 =
+	VDO_IDH_REV30(1, /* Data caps as USB host     */
+		      0, /* Not a USB device   */
+		      IDH_PTYPE_PERIPH, 1, /* Supports alt modes */
+		      IDH_PTYPE_DFP_HOST, USB_TYPEC_RECEPTACLE, USB_VID_GOOGLE);
+
+static const uint32_t vdo_product =
+	VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV);
+
+/* TODO(b/168890624): add USB4 to capability once USB4 response implemented */
+static const uint32_t vdo_ufp1 = VDO_UFP1(
+	(VDO_UFP1_CAPABILITY_USB20 | VDO_UFP1_CAPABILITY_USB32),
+	USB_TYPEC_RECEPTACLE, VDO_UFP1_ALT_MODE_TBT3, USB_R30_SS_U40_GEN3);
+
+static const uint32_t vdo_dfp =
+	VDO_DFP((VDO_DFP_HOST_CAPABILITY_USB20 | VDO_DFP_HOST_CAPABILITY_USB32 |
+		 VDO_DFP_HOST_CAPABILITY_USB4),
+		USB_TYPEC_RECEPTACLE, 1 /* Port 1 */);
+
+static int svdm_tbt_compat_response_identity(int port, uint32_t *payload)
+{
+	/*
+	 * For PD 3.1 compliance test TEST.PD.VDM.SRC.2,
+	 * we should return NAK if we cannot recognized the incoming SVID.
+	 */
+	if (PD_VDO_VID(payload[0]) == USB_SID_PD) {
+		/* TODO(b/154962766): Get an XID */
+		payload[VDO_I(CSTAT)] = VDO_CSTAT(0);
+		payload[VDO_I(PRODUCT)] = vdo_product;
+
+		if (pd_get_rev(port, TCPCI_MSG_SOP) == PD_REV30) {
+			/* PD Revision 3.0 */
+			payload[VDO_I(IDH)] = vdo_idh_rev30;
+			payload[VDO_I(PTYPE_UFP1_VDO)] = vdo_ufp1;
+			/* TODO(b/181620145): Customize for brya */
+			payload[VDO_I(PTYPE_UFP2_VDO)] = 0;
+			payload[VDO_I(PTYPE_DFP_VDO)] = vdo_dfp;
+			return VDO_I(PTYPE_DFP_VDO) + 1;
+		}
+
+		/* PD Revision 2.0 */
+		payload[VDO_I(IDH)] = vdo_idh;
+		return VDO_I(PRODUCT) + 1;
+	} else {
+		return 0; /* NAK */
+	}
+}
+
+static int svdm_tbt_compat_response_svids(int port, uint32_t *payload)
+{
+	/*
+	 * For PD 3.1 compliance test TEST.PD.VDM.SRC.2,
+	 * we should return NAK if we cannot recognized the incoming SVID.
+	 */
+	if (PD_VDO_VID(payload[0]) == USB_SID_PD) {
+		payload[1] = VDO_SVID(USB_VID_INTEL, 0);
+		return 2;
+	} else {
+		return 0; /* NAK */
+	}
+}
+
+static int svdm_tbt_compat_response_modes(int port, uint32_t *payload)
+{
+	if (PD_VDO_VID(payload[0]) == USB_VID_INTEL) {
+		memcpy(payload + 1, vdo_tbt_modes, sizeof(vdo_tbt_modes));
+		return ARRAY_SIZE(vdo_tbt_modes) + 1;
+	} else {
+		return 0; /* NAK */
+	}
+}
+
+/* Track whether we've been enabled to ACK TBT EnterModes requests */
+static bool tbt_ufp_ack_allowed[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+__override enum ec_status
+board_set_tbt_ufp_reply(int port, enum typec_tbt_ufp_reply reply)
+{
+	/* Note: Host command has already bounds-checked port */
+	if (reply == TYPEC_TBT_UFP_REPLY_ACK)
+		tbt_ufp_ack_allowed[port] = true;
+	else if (reply == TYPEC_TBT_UFP_REPLY_NAK)
+		tbt_ufp_ack_allowed[port] = false;
+	else
+		return EC_RES_INVALID_PARAM;
+
+	return EC_RES_SUCCESS;
+}
+
+static int svdm_tbt_compat_response_enter_mode(int port, uint32_t *payload)
+{
+	mux_state_t mux_state = 0;
+
+	/* Do not enter mode while CPU is off. */
+	if (chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF))
+		return 0; /* NAK */
+
+	/* Do not enter mode while policy disallows it */
+	if (!tbt_ufp_ack_allowed[port])
+		return 0; /* NAK */
+
+	if ((PD_VDO_VID(payload[0]) != USB_VID_INTEL) ||
+	    (PD_VDO_OPOS(payload[0]) != OPOS_TBT))
+		return 0; /* NAK */
+
+	mux_state = usb_mux_get(port);
+	/*
+	 * Ref: USB PD 3.0 Spec figure 6-21 Successful Enter Mode sequence
+	 * UFP (responder) should be in USB mode or safe mode before entering a
+	 * Mode that requires the reconfiguring of any pins.
+	 */
+	if ((mux_state & USB_PD_MUX_USB_ENABLED) ||
+	    (mux_state & USB_PD_MUX_SAFE_MODE)) {
+		pd_ufp_set_enter_mode(port, payload);
+		set_tbt_compat_mode_ready(port);
+
+		/*
+		 * Ref: Above figure 6-21: UFP (responder) should be in the new
+		 * mode before sending the ACK.  However, our mux set sequence
+		 * may exceed tVDMEnterMode, so wait as long as we can
+		 * before sending the reply without violating that timer.
+		 */
+		if (!usb_mux_set_completed(port))
+			usleep(PD_T_VDM_E_MODE / 2);
+
+		CPRINTS("UFP Enter TBT mode");
+		return 1; /* ACK */
+	}
+
+	CPRINTS("UFP failed to enter TBT mode(mux=0x%x)", mux_state);
+	return 0;
+}
+
+const struct svdm_response svdm_rsp = {
+	.identity = &svdm_tbt_compat_response_identity,
+	.svids = &svdm_tbt_compat_response_svids,
+	.modes = &svdm_tbt_compat_response_modes,
+	.enter_mode = &svdm_tbt_compat_response_enter_mode,
+	.amode = NULL,
+	.exit_mode = NULL,
+};
+#endif /* CONFIG_USB_PD_TBT_COMPAT_MODE */
diff --git a/baseboard/cherry/baseboard.c b/baseboard/cherry/baseboard.c
new file mode 100644
index 0000000000..c162331f89
--- /dev/null
+++ b/baseboard/cherry/baseboard.c
@@ -0,0 +1,524 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Cherry baseboard-specific configuration */
+
+#include "adc.h"
+#include "button.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "driver/accelgyro_icm42607.h"
+#include "driver/bc12/mt6360.h"
+#include "driver/bc12/pi3usb9201.h"
+#include "driver/charger/isl923x.h"
+#include "driver/ppc/rt1718s.h"
+#include "driver/ppc/syv682x.h"
+#include "driver/tcpm/it83xx_pd.h"
+#include "driver/tcpm/rt1718s.h"
+#include "driver/temp_sensor/thermistor.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "regulator.h"
+#include "spi.h"
+#include "switch.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "temp_sensor.h"
+#include "timer.h"
+#include "uart.h"
+#include "usb_charge.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usb_tc_sm.h"
+#include "usbc_ppc.h"
+
+static void bc12_interrupt(enum gpio_signal signal);
+static void ppc_interrupt(enum gpio_signal signal);
+static void xhci_init_done_interrupt(enum gpio_signal signal);
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+
+/* Wake-up pins for hibernate */
+enum gpio_signal hibernate_wake_pins[] = {
+	GPIO_AC_PRESENT,
+	GPIO_LID_OPEN,
+	GPIO_POWER_BUTTON_L,
+};
+int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
+
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+};
+
+/* Override default setting, called after charger_chips_init */
+static void baseboard_charger_init(void)
+{
+	/* b/198707662#comment9 */
+	int reg = (4096 / ISL9238_INPUT_VOLTAGE_REF_STEP)
+		  << ISL9238_INPUT_VOLTAGE_REF_SHIFT;
+
+	i2c_write16(I2C_PORT_CHARGER, ISL923X_ADDR_FLAGS,
+		    ISL9238_REG_INPUT_VOLTAGE, reg);
+}
+DECLARE_HOOK(HOOK_INIT, baseboard_charger_init, HOOK_PRIO_DEFAULT + 2);
+
+__override void board_hibernate_late(void)
+{
+	/*
+	 * Turn off PP5000_A. Required for devices without Z-state.
+	 * Don't care for devices with Z-state.
+	 */
+	gpio_set_level(GPIO_EN_PP5000_A, 0);
+	gpio_set_level(GPIO_EN_SLP_Z, 1);
+
+	/* should not reach here */
+	__builtin_unreachable();
+}
+
+void board_hibernate(void)
+{
+	isl9238c_hibernate(CHARGER_SOLO);
+}
+
+static void board_tcpc_init(void)
+{
+	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_INT_ODL);
+}
+/* Must be done after I2C */
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
+
+void rt1718s_tcpc_interrupt(enum gpio_signal signal)
+{
+	schedule_deferred_pd_interrupt(1);
+}
+
+/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
+const struct adc_t adc_channels[] = {
+	/* Convert to mV (3000mV/1024). */
+	{ "VBUS", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0, CHIP_ADC_CH0 },
+	{ "BOARD_ID_0", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH1 },
+	{ "BOARD_ID_1", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH2 },
+	/* AMON/BMON gain = 17.97 */
+	{ "CHARGER_AMON_R", ADC_MAX_MVOLT * 1000 / 17.97, ADC_READ_MAX + 1, 0,
+	  CHIP_ADC_CH3 },
+	{ "CHARGER_PMON", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH6 },
+	{ "TEMP_SENSOR_CHG", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH7 },
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_CHARGER] = {
+		.name = "Charger",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_CHARGER,
+	},
+};
+
+/* PPC */
+struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.i2c_port = I2C_PORT_PPC0,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.drv = &syv682x_drv,
+		.frs_en = GPIO_USB_C0_FRS_EN,
+	},
+	{
+		.i2c_port = I2C_PORT_PPC1,
+		.i2c_addr_flags = RT1718S_I2C_ADDR1_FLAGS,
+		.drv = &rt1718s_ppc_drv,
+	},
+};
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/* BC12 */
+const struct mt6360_config_t mt6360_config = {
+	.i2c_port = 0,
+	.i2c_addr_flags = MT6360_PMU_I2C_ADDR_FLAGS,
+};
+
+__maybe_unused const struct pi3usb9201_config_t
+		pi3usb9201_bc12_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	[0] = {
+		.i2c_port = I2C_PORT_USB0,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	}
+	/* [1]: unused */
+};
+
+struct bc12_config bc12_ports[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+#ifdef CONFIG_BC12_DETECT_PI3USB9201
+	{ .drv = &pi3usb9201_drv },
+#elif defined(CONFIG_BC12_DETECT_MT6360)
+	{ .drv = &mt6360_drv },
+#else
+#error must pick one of PI3USB9201 or MT6360 for port 0
+#endif
+	{ .drv = &rt1718s_bc12_drv },
+};
+
+static void bc12_interrupt(enum gpio_signal signal)
+{
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+
+static void ppc_interrupt(enum gpio_signal signal)
+{
+	syv682x_interrupt(0);
+}
+
+/* Called on AP S3 -> S0 transition */
+static void board_chipset_resume(void)
+{
+	gpio_set_level(GPIO_EC_BL_EN_OD, 1);
+	gpio_set_level(GPIO_DP_DEMUX_EN, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S0 -> S3 transition */
+static void board_chipset_suspend(void)
+{
+	gpio_set_level(GPIO_EC_BL_EN_OD, 0);
+	gpio_set_level(GPIO_DP_DEMUX_EN, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
+
+/* USB-A */
+const int usb_port_enable[] = {
+	GPIO_EN_PP5000_USB_A0_VBUS_X,
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
+
+__maybe_unused void xhci_init_done_interrupt(enum gpio_signal signal)
+{
+	enum usb_charge_mode mode = gpio_get_level(signal) ?
+					    USB_CHARGE_MODE_ENABLED :
+					    USB_CHARGE_MODE_DISABLED;
+
+	for (int i = 0; i < USB_PORT_COUNT; i++)
+		usb_charge_set_mode(i, mode, USB_ALLOW_SUSPEND_CHARGE);
+
+	/*
+	 * Trigger hard reset to cycle Vbus on Type-C ports, recommended by
+	 * USB 3.2 spec 10.3.1.1.
+	 */
+	if (gpio_get_level(signal)) {
+		for (int i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+			if (tc_is_attached_src(i))
+				pd_dpm_request(i, DPM_REQUEST_HARD_RESET_SEND);
+		}
+	}
+}
+
+/*
+ * I2C channels (A, B, and C) are using the same timing registers (00h~07h)
+ * at default.
+ * In order to set frequency independently for each channels,
+ * We use timing registers 09h~0Bh, and the supported frequency will be:
+ * 50KHz, 100KHz, 400KHz, or 1MHz.
+ * I2C channels (D, E and F) can be set different frequency on different ports.
+ * The I2C(D/E/F) frequency depend on the frequency of SMBus Module and
+ * the individual prescale register.
+ * The frequency of SMBus module is 24MHz on default.
+ * The allowed range of I2C(D/E/F) frequency is as following setting.
+ * SMBus Module Freq = PLL_CLOCK / ((IT83XX_ECPM_SCDCR2 & 0x0F) + 1)
+ * (SMBus Module Freq / 510) <=  I2C Freq <= (SMBus Module Freq / 8)
+ * Channel D has multi-function and can be used as UART interface.
+ * Channel F is reserved for EC debug.
+ */
+
+/* I2C ports */
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "bat_chg",
+	  .port = IT83XX_I2C_CH_A,
+	  .kbps = 100,
+	  .scl = GPIO_I2C_A_SCL,
+	  .sda = GPIO_I2C_A_SDA },
+	{ .name = "sensor",
+	  .port = IT83XX_I2C_CH_B,
+	  .kbps = 400,
+	  .scl = GPIO_I2C_B_SCL,
+	  .sda = GPIO_I2C_B_SDA },
+	{ .name = "usb0",
+	  .port = IT83XX_I2C_CH_C,
+	  .kbps = 400,
+	  .scl = GPIO_I2C_C_SCL,
+	  .sda = GPIO_I2C_C_SDA },
+	{ .name = "usb1",
+	  .port = IT83XX_I2C_CH_E,
+	  .kbps = 1000,
+	  .scl = GPIO_I2C_E_SCL,
+	  .sda = GPIO_I2C_E_SDA },
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+int board_allow_i2c_passthru(const struct i2c_cmd_desc_t *cmd_desc)
+{
+	return (cmd_desc->port == I2C_PORT_VIRTUAL_BATTERY);
+}
+
+/* TCPC */
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_EMBEDDED,
+		/* TCPC is embedded within EC so no i2c config needed */
+		.drv = &it8xxx2_tcpm_drv,
+		/* Alert is active-low, push-pull */
+		.flags = 0,
+	},
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB1,
+			.addr_flags = RT1718S_I2C_ADDR1_FLAGS,
+		},
+		.drv = &rt1718s_tcpm_drv,
+	},
+};
+
+__override int board_rt1718s_init(int port)
+{
+	static bool gpio_initialized;
+
+	if (!system_jumped_late() && !gpio_initialized) {
+		/* set GPIO 1~3 as push pull, as output, output low. */
+		rt1718s_gpio_set_flags(port, RT1718S_GPIO1, GPIO_OUT_LOW);
+		rt1718s_gpio_set_flags(port, RT1718S_GPIO2, GPIO_OUT_LOW);
+		rt1718s_gpio_set_flags(port, RT1718S_GPIO3, GPIO_OUT_LOW);
+		gpio_initialized = true;
+	}
+
+	/* gpio 1/2 output high when receiving frx signal */
+	RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_GPIO1_VBUS_CTRL,
+					  RT1718S_GPIO_VBUS_CTRL_FRS_RX_VBUS,
+					  0xFF));
+	RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_GPIO2_VBUS_CTRL,
+					  RT1718S_GPIO_VBUS_CTRL_FRS_RX_VBUS,
+					  0xFF));
+
+	/* Turn on SBU switch */
+	RETURN_ERROR(
+		rt1718s_update_bits8(port, RT1718S_RT2_SBU_CTRL_01,
+				     RT1718S_RT2_SBU_CTRL_01_SBU_VIEN |
+					     RT1718S_RT2_SBU_CTRL_01_SBU2_SWEN |
+					     RT1718S_RT2_SBU_CTRL_01_SBU1_SWEN,
+				     0xFF));
+	/* Trigger GPIO 1/2 change when FRS signal received */
+	RETURN_ERROR(rt1718s_update_bits8(
+		port, RT1718S_FRS_CTRL3,
+		RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO2 |
+			RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO1,
+		RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO2 |
+			RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO1));
+	/* Set FRS signal detect time to 46.875us */
+	RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_FRS_CTRL1,
+					  RT1718S_FRS_CTRL1_FRSWAPRX_MASK,
+					  0xFF));
+
+	return EC_SUCCESS;
+}
+
+const struct cc_para_t *board_get_cc_tuning_parameter(enum usbpd_port port)
+{
+	const static struct cc_para_t cc_parameter = {
+		.rising_time = IT83XX_TX_PRE_DRIVING_TIME_1_UNIT,
+		.falling_time = IT83XX_TX_PRE_DRIVING_TIME_2_UNIT,
+	};
+
+	if (port == USBPD_PORT_A)
+		return &cc_parameter;
+	return NULL;
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	/*
+	 * C0 TCPC is embedded in the EC and processes interrupts in the
+	 * chip code (it83xx/intc.c)
+	 */
+	if (!gpio_get_level(GPIO_USB_C1_INT_ODL))
+		return PD_STATUS_TCPC_ALERT_1;
+	return 0;
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * C0: The internal TCPC on ITE EC does not have a reset signal,
+	 * but it will get reset when the EC gets reset.
+	 */
+	/* C1: Add code if TCPC chips need a reset */
+}
+
+void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
+{
+	/*
+	 * We ignore the cc_pin and PPC vconn because polarity and PPC vconn
+	 * should already be set correctly in the PPC driver via the pd
+	 * state machine.
+	 */
+}
+
+int board_set_active_charge_port(int port)
+{
+	int i;
+	bool is_valid_port = (port == 0 || port == 1);
+
+	if (!is_valid_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTS("Disabling all charger ports");
+
+		/* Disable all ports. */
+		for (i = 0; i < ppc_cnt; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (ppc_vbus_sink_enable(i, 0))
+				CPRINTS("Disabling C%d as sink failed.", i);
+		}
+		rt1718s_gpio_set_level(1, GPIO_EN_USB_C1_VBUS_L, 1);
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (ppc_is_sourcing_vbus(port)) {
+		CPRINTS("Skip enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTS("New charge port: C%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < ppc_cnt; i++) {
+		if (i == port)
+			continue;
+
+		if (ppc_vbus_sink_enable(i, 0))
+			CPRINTS("C%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTS("C%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	rt1718s_gpio_set_level(1, GPIO_EN_USB_C1_VBUS_L, !(port == 1));
+
+	return EC_SUCCESS;
+}
+
+int ppc_get_alert_status(int port)
+{
+	if (port == 0)
+		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
+
+	/* TODO: add rt1718s */
+	return 0;
+}
+/* SD Card */
+int board_regulator_get_info(uint32_t index, char *name, uint16_t *num_voltages,
+			     uint16_t *voltages_mv)
+{
+	enum mt6360_regulator_id id = index;
+
+	return mt6360_regulator_get_info(id, name, num_voltages, voltages_mv);
+}
+
+int board_regulator_enable(uint32_t index, uint8_t enable)
+{
+	enum mt6360_regulator_id id = index;
+
+	return mt6360_regulator_enable(id, enable);
+}
+
+int board_regulator_is_enabled(uint32_t index, uint8_t *enabled)
+{
+	enum mt6360_regulator_id id = index;
+
+	return mt6360_regulator_is_enabled(id, enabled);
+}
+
+int board_regulator_set_voltage(uint32_t index, uint32_t min_mv,
+				uint32_t max_mv)
+{
+	enum mt6360_regulator_id id = index;
+
+	return mt6360_regulator_set_voltage(id, min_mv, max_mv);
+}
+
+int board_regulator_get_voltage(uint32_t index, uint32_t *voltage_mv)
+{
+	enum mt6360_regulator_id id = index;
+
+	return mt6360_regulator_get_voltage(id, voltage_mv);
+}
+
+static void baseboard_init(void)
+{
+	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
+#ifndef BOARD_CHERRY
+	gpio_enable_interrupt(GPIO_AP_XHCI_INIT_DONE);
+#endif
+}
+DECLARE_HOOK(HOOK_INIT, baseboard_init, HOOK_PRIO_DEFAULT - 1);
+
+__override int board_rt1718s_set_frs_enable(int port, int enable)
+{
+	if (port == 1)
+		/*
+		 * Use set_flags (implemented by a single i2c write) instead
+		 * of set_level (= i2c_update) to save one read operation in
+		 * FRS path.
+		 */
+		rt1718s_gpio_set_flags(port, GPIO_EN_USB_C1_FRS,
+				       enable ? GPIO_OUT_HIGH : GPIO_OUT_LOW);
+	return EC_SUCCESS;
+}
+
+__override int board_get_vbus_voltage(int port)
+{
+	int voltage = 0;
+
+	switch (port) {
+	case 0:
+		voltage = adc_read_channel(ADC_VBUS);
+		break;
+	case 1:
+		rt1718s_get_adc(port, RT1718S_ADC_VBUS1, &voltage);
+		break;
+	default:
+		return 0;
+	}
+
+	return voltage;
+}
diff --git a/baseboard/cherry/baseboard.h b/baseboard/cherry/baseboard.h
new file mode 100644
index 0000000000..e49222fc9e
--- /dev/null
+++ b/baseboard/cherry/baseboard.h
@@ -0,0 +1,246 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Cherry board configuration */
+
+#ifndef __CROS_EC_BASEBOARD_H
+#define __CROS_EC_BASEBOARD_H
+
+/* IT81202-bx config */
+/*
+ * NOTE: we need to make correct VCC voltage selection here if EC's VCC isn't
+ * connect to 1.8v on other versions.
+ */
+#define CONFIG_IT83XX_VCC_1P8V
+#define CONFIG_IT83XX_I2C_CMD_QUEUE
+
+/*
+ * On power-on, H1 releases the EC from reset but then quickly asserts and
+ * releases the reset a second time. This means the EC sees 2 resets:
+ * (1) power-on reset, (2) reset-pin reset. This config will
+ * allow the second reset to be treated as a power-on.
+ */
+#define CONFIG_BOARD_RESET_AFTER_POWER_ON
+#define CONFIG_CHIPSET_MT8192
+#define CONFIG_EXTPOWER_GPIO
+#define CONFIG_HIBERNATE_WAKE_PINS_DYNAMIC
+#define CONFIG_POWER_SLEEP_FAILURE_DETECTION
+#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
+
+/* Chipset */
+#define CONFIG_CMD_AP_RESET_LOG
+#undef CONFIG_CMD_POWERINDEBUG
+#define CONFIG_HOST_COMMAND_STATUS
+#define CONFIG_LOW_POWER_IDLE
+#define CONFIG_POWER_BUTTON
+#define CONFIG_POWER_COMMON
+#define CONFIG_PWM
+#define CONFIG_PWM_KBLIGHT
+#define CONFIG_VBOOT_HASH
+#define CONFIG_VOLUME_BUTTONS
+#define CONFIG_WP_ACTIVE_HIGH
+
+/* Battery */
+#define CONFIG_BATTERY_CUT_OFF
+#define CONFIG_BATTERY_FUEL_GAUGE
+#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL
+#define CONFIG_BATTERY_SMART
+
+/* BC12 */
+#ifdef BOARD_CHERRY
+#define CONFIG_BC12_DETECT_PI3USB9201
+#endif
+#define CONFIG_BC12_DETECT_MT6360
+#undef CONFIG_BC12_SINGLE_DRIVER
+#define CONFIG_USB_CHARGER
+
+/* CBI */
+#define CONFIG_BOARD_VERSION_CBI
+#define CONFIG_CBI_EEPROM
+#define CONFIG_CMD_CBI
+#define I2C_PORT_EEPROM IT83XX_I2C_CH_A
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+
+/* Charger */
+#define ADC_AMON_BMON ADC_CHARGER_AMON_R /* ADC name remap */
+#define ADC_PSYS ADC_CHARGER_PMON /* ADC name remap */
+#define CONFIG_CHARGE_MANAGER
+#define CONFIG_CHARGER
+#define CONFIG_CHARGE_RAMP_HW
+#define CONFIG_CHARGER_DISCHARGE_ON_AC
+#define CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT 512
+#define CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT 512
+#define CONFIG_CHARGER_ISL9238C
+#define CONFIG_CHARGER_MAINTAIN_VBAT
+/* Not used in boot flow, set to 0 to suppress system_can_boot_ap warning */
+#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 0
+#define CONFIG_CHARGER_OTG
+#define CONFIG_CHARGER_PSYS
+#define CONFIG_CHARGER_PSYS_READ
+#define CONFIG_CHARGER_SENSE_RESISTOR 10 /* BOARD_RS2 */
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 /* BOARD_RS1 */
+#define CONFIG_CMD_CHARGER_ADC_AMON_BMON
+
+/* Keyboard */
+#define CONFIG_CMD_KEYBOARD
+#define CONFIG_KEYBOARD_COL2_INVERTED
+#define CONFIG_KEYBOARD_PROTOCOL_MKBP
+#define CONFIG_MKBP_USE_GPIO
+
+/* I2C */
+#define CONFIG_I2C
+#define CONFIG_I2C_CONTROLLER
+#define CONFIG_I2C_PASSTHRU_RESTRICTED
+#define CONFIG_I2C_VIRTUAL_BATTERY
+#define I2C_PORT_CHARGER IT83XX_I2C_CH_A
+#define I2C_PORT_BATTERY IT83XX_I2C_CH_A
+#define I2C_PORT_ACCEL IT83XX_I2C_CH_B
+#define I2C_PORT_PPC0 IT83XX_I2C_CH_C
+#define I2C_PORT_PPC1 IT83XX_I2C_CH_E
+#define I2C_PORT_USB0 IT83XX_I2C_CH_C
+#define I2C_PORT_USB1 IT83XX_I2C_CH_E
+#define I2C_PORT_USB_MUX0 IT83XX_I2C_CH_C
+#define I2C_PORT_USB_MUX1 IT83XX_I2C_CH_E
+#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
+#define CONFIG_SMBUS_PEC
+
+/* LED */
+#define CONFIG_LED_COMMON
+
+/* PD / USB-C / PPC */
+#define CONFIG_BC12_DETECT_RT1718S
+#define CONFIG_CMD_PPC_DUMP
+#define CONFIG_HOSTCMD_PD_CONTROL
+#define CONFIG_IT83XX_TUNE_CC_PHY
+#define CONFIG_USBC_PPC
+#define CONFIG_USBC_PPC_DEDICATED_INT
+#define CONFIG_USBC_PPC_POLARITY
+#define CONFIG_USBC_PPC_RT1718S
+#define CONFIG_USBC_PPC_SYV682X
+#define CONFIG_USBC_PPC_VCONN
+#define CONFIG_USBC_SS_MUX
+#define CONFIG_USBC_VCONN
+#define CONFIG_USBC_VCONN_SWAP
+#define CONFIG_USB_DRP_ACC_TRYSRC
+#define CONFIG_USBC_RETIMER_PS8802 /* C0 */
+#define CONFIG_USB_MUX_ANX3443 /* C1 */
+#define CONFIG_USB_PD_ALT_MODE
+#define CONFIG_USB_PD_ALT_MODE_DFP
+#define CONFIG_USB_PD_DECODE_SOP
+#define CONFIG_USB_PD_DISCHARGE
+#define CONFIG_USB_PD_DISCHARGE_PPC
+#define CONFIG_USB_PD_DPS
+#define CONFIG_USB_PD_DP_HPD_GPIO
+#define CONFIG_USB_PD_DP_HPD_GPIO_CUSTOM
+#define CONFIG_USB_PD_DUAL_ROLE
+#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+#define CONFIG_USB_PD_FRS_PPC
+#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1
+#define CONFIG_USB_PD_LOGGING
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#define CONFIG_USB_PD_PPC
+#define CONFIG_USB_PD_REV30
+#define CONFIG_USB_PD_TCPC_LOW_POWER
+#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP
+#define CONFIG_USB_PD_TCPM_RT1718S
+#define CONFIG_USB_PD_TCPM_TCPCI
+#define CONFIG_USB_PD_TCPMV2
+#define CONFIG_USB_PD_TRY_SRC
+#define CONFIG_USB_PD_VBUS_DETECT_PPC
+#define CONFIG_USB_PD_VBUS_MEASURE_BY_BOARD
+#define CONFIG_USB_PID 0x5054
+#define CONFIG_USB_POWER_DELIVERY
+
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 60000
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
+
+/* USB-A */
+#define CONFIG_USB_PORT_POWER_DUMB
+#ifndef BOARD_CHERRY
+#define CONFIG_USB_PORT_POWER_DUMB_CUSTOM_HOOK
+#endif
+#define USB_PORT_COUNT USBA_PORT_COUNT
+
+/* UART */
+#undef CONFIG_UART_TX_BUF_SIZE
+#define CONFIG_UART_TX_BUF_SIZE 4096
+
+/* Sensor */
+#define CONFIG_CMD_ACCEL_INFO
+#define CONFIG_CMD_ACCELS
+
+#define CONFIG_ACCEL_FIFO
+#define CONFIG_ACCEL_FIFO_SIZE 256
+#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
+
+/* SPI / Host Command */
+#define CONFIG_SPI
+
+/* MKBP */
+#define CONFIG_MKBP_EVENT
+
+#define CONFIG_KEYBOARD_PROTOCOL_MKBP
+#define CONFIG_MKBP_USE_GPIO
+
+/* Vboot Config */
+#define CONFIG_CRC8
+#define CONFIG_VBOOT_EFS2
+#define CONFIG_VBOOT_HASH
+#define CONFIG_VSTORE
+#define CONFIG_VSTORE_SLOT_COUNT 1
+
+/* Voltage regulator control */
+#define CONFIG_HOSTCMD_REGULATOR
+
+/* Define the host events which are allowed to wakeup AP in S3. */
+#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK                   \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |    \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |        \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT) |     \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |     \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+/* And the MKBP events */
+#define CONFIG_MKBP_EVENT_WAKEUP_MASK \
+	(BIT(EC_MKBP_EVENT_KEY_MATRIX) | BIT(EC_MKBP_EVENT_HOST_EVENT))
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "power/mt8192.h"
+#include "registers.h"
+
+enum adc_channel {
+	ADC_VBUS, /* ADC 0 */
+	ADC_BOARD_ID, /* ADC 1 */
+	ADC_SKU_ID, /* ADC 2 */
+	ADC_CHARGER_AMON_R, /* ADC 3 */
+	ADC_CHARGER_PMON, /* ADC 6 */
+	ADC_TEMP_SENSOR_CHARGER, /* ADC 7 */
+
+	/* Number of ADC channels */
+	ADC_CH_COUNT,
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_CHARGER,
+	TEMP_SENSOR_COUNT,
+};
+
+void board_reset_pd_mcu(void);
+void rt1718s_tcpc_interrupt(enum gpio_signal signal);
+
+/* RT1718S gpio to pin name mapping */
+#define GPIO_EN_USB_C1_VBUS_L RT1718S_GPIO1
+#define GPIO_EN_USB_C1_5V_OUT RT1718S_GPIO2
+#define GPIO_EN_USB_C1_FRS RT1718S_GPIO3
+
+#endif /* !__ASSEMBLER__ */
+#endif /* __CROS_EC_BASEBOARD_H */
diff --git a/baseboard/cherry/build.mk b/baseboard/cherry/build.mk
new file mode 100644
index 0000000000..74609511c3
--- /dev/null
+++ b/baseboard/cherry/build.mk
@@ -0,0 +1,10 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Baseboard specific files build
+#
+
+baseboard-y=baseboard.o
+baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
diff --git a/baseboard/cherry/usb_pd_policy.c b/baseboard/cherry/usb_pd_policy.c
new file mode 100644
index 0000000000..450f5c06d7
--- /dev/null
+++ b/baseboard/cherry/usb_pd_policy.c
@@ -0,0 +1,253 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "adc.h"
+#include "atomic.h"
+#include "charge_manager.h"
+#include "chipset.h"
+#include "driver/tcpm/rt1718s.h"
+#include "driver/tcpm/tcpci.h"
+#include "gpio.h"
+#include "timer.h"
+#include "usb_dp_alt_mode.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+
+#if CONFIG_USB_PD_3A_PORTS != 1
+#error Cherry reference must have at least one 3.0 A port
+#endif
+
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+
+/* The port that the aux channel is on. */
+static enum {
+	AUX_PORT_NONE = -1,
+	AUX_PORT_C0 = 0,
+	AUX_PORT_C1HDMI = 1,
+} aux_port = AUX_PORT_NONE;
+
+static void aux_switch_port(int port)
+{
+	if (port != AUX_PORT_NONE)
+		gpio_set_level_verbose(CC_USBPD, GPIO_DP_PATH_SEL, !port);
+	aux_port = port;
+}
+
+static void aux_display_disconnected(int port)
+{
+	/* Gets the other port. C0 -> C1, C1 -> C0. */
+	int other_port = !port;
+
+	/* If the current port is not the aux port, nothing needs to be done. */
+	if (aux_port != port)
+		return;
+
+	/* If the other port is connected to a external display, switch aux. */
+	if (dp_status[other_port] & DP_FLAGS_DP_ON)
+		aux_switch_port(other_port);
+	else
+		aux_switch_port(AUX_PORT_NONE);
+}
+
+int svdm_get_hpd_gpio(int port)
+{
+	/* HPD is low active, inverse the result */
+	return !gpio_get_level(GPIO_EC_AP_DP_HPD_ODL);
+}
+
+void svdm_set_hpd_gpio(int port, int en)
+{
+	/*
+	 * Cherry can only output to 1 display port at a time.
+	 * This implements FCFS policy by changing the aux channel. If a
+	 * display is connected to the either port (says A), and the port A
+	 * will be served until the display is disconnected from port A.
+	 * It won't output to the other display which connects to port B.
+	 */
+	if (en) {
+		if (aux_port == AUX_PORT_NONE)
+			aux_switch_port(port);
+	} else {
+		aux_display_disconnected(port);
+	}
+	/*
+	 * HPD is low active, inverse the en
+	 */
+	gpio_set_level_verbose(CC_USBPD, GPIO_EC_AP_DP_HPD_ODL, !en);
+}
+
+__override int svdm_dp_attention(int port, uint32_t *payload)
+{
+	int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]);
+	int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]);
+#ifdef CONFIG_USB_PD_DP_HPD_GPIO
+	int cur_lvl = svdm_get_hpd_gpio(port);
+#endif /* CONFIG_USB_PD_DP_HPD_GPIO */
+	mux_state_t mux_state;
+
+	dp_status[port] = payload[1];
+
+	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && (irq || lvl))
+		/*
+		 * Wake up the AP.  IRQ or level high indicates a DP sink is now
+		 * present.
+		 */
+		if (IS_ENABLED(CONFIG_MKBP_EVENT))
+			pd_notify_dp_alt_mode_entry(port);
+
+	/* Its initial DP status message prior to config */
+	if (!(dp_flags[port] & DP_FLAGS_DP_ON)) {
+		if (lvl)
+			dp_flags[port] |= DP_FLAGS_HPD_HI_PENDING;
+		return 1;
+	}
+
+#ifdef CONFIG_USB_PD_DP_HPD_GPIO
+	if (irq && !lvl) {
+		/*
+		 * IRQ can only be generated when the level is high, because
+		 * the IRQ is signaled by a short low pulse from the high level.
+		 */
+		CPRINTF("ERR:HPD:IRQ&LOW\n");
+		return 0; /* nak */
+	}
+
+	if (irq && cur_lvl) {
+		uint64_t now = get_time().val;
+		/* wait for the minimum spacing between IRQ_HPD if needed */
+		if (now < svdm_hpd_deadline[port])
+			usleep(svdm_hpd_deadline[port] - now);
+
+		/* generate IRQ_HPD pulse */
+		svdm_set_hpd_gpio(port, 0);
+		/*
+		 * b/171172053#comment14: since the HPD_DSTREAM_DEBOUNCE_IRQ is
+		 * very short (500us), we can use udelay instead of usleep for
+		 * more stable pulse period.
+		 *
+		 * Note that this should be the only difference between our code
+		 * and common code.
+		 */
+		udelay(HPD_DSTREAM_DEBOUNCE_IRQ);
+		svdm_set_hpd_gpio(port, 1);
+	} else {
+		svdm_set_hpd_gpio(port, lvl);
+	}
+
+	/* set the minimum time delay (2ms) for the next HPD IRQ */
+	svdm_hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
+#endif /* CONFIG_USB_PD_DP_HPD_GPIO */
+
+	mux_state = (lvl ? USB_PD_MUX_HPD_LVL : USB_PD_MUX_HPD_LVL_DEASSERTED) |
+		    (irq ? USB_PD_MUX_HPD_IRQ : USB_PD_MUX_HPD_IRQ_DEASSERTED);
+	usb_mux_hpd_update(port, mux_state);
+
+#ifdef USB_PD_PORT_TCPC_MST
+	if (port == USB_PD_PORT_TCPC_MST)
+		baseboard_mst_enable_control(port, lvl);
+#endif
+
+	/* ack */
+	return 1;
+}
+
+__override void svdm_exit_dp_mode(int port)
+{
+	dp_flags[port] = 0;
+	dp_status[port] = 0;
+#ifdef CONFIG_USB_PD_DP_HPD_GPIO
+	if (aux_port == port)
+		svdm_set_hpd_gpio(port, 0);
+#endif /* CONFIG_USB_PD_DP_HPD_GPIO */
+	usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
+					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+#ifdef USB_PD_PORT_TCPC_MST
+	if (port == USB_PD_PORT_TCPC_MST)
+		baseboard_mst_enable_control(port, 0);
+#endif
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	static atomic_t vbus_prev[CONFIG_USB_PD_PORT_MAX_COUNT];
+	int vbus;
+
+	/*
+	 * Use ppc_is_vbus_present for all ports on Cherry, and
+	 * port 1 on other devices.
+	 */
+	if (IS_ENABLED(BOARD_CHERRY) || port == 1)
+		return ppc_is_vbus_present(port);
+
+	/* b/181203590: use ADC for port 0 (syv682x) */
+	vbus = (adc_read_channel(ADC_VBUS) >= PD_V_SINK_DISCONNECT_MAX);
+
+#ifdef CONFIG_USB_CHARGER
+	/*
+	 * There's no PPC to inform VBUS change for usb_charger, so inform
+	 * the usb_charger now.
+	 */
+	if (!!(vbus_prev[port] != vbus))
+		usb_charger_vbus_change(port, vbus);
+
+	if (vbus)
+		atomic_or(&vbus_prev[port], 1);
+	else
+		atomic_clear(&vbus_prev[port]);
+#endif
+	return vbus;
+}
+
+void pd_power_supply_reset(int port)
+{
+	/* Disable VBUS. */
+	ppc_vbus_source_enable(port, 0);
+
+	/* Enable discharge if we were previously sourcing 5V */
+	pd_set_vbus_discharge(port, 1);
+
+	if (port == 1)
+		rt1718s_gpio_set_level(port, GPIO_EN_USB_C1_5V_OUT, 0);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_check_vconn_swap(int port)
+{
+	/* Allow Vconn swap if AP is on. */
+	return chipset_in_state(CHIPSET_STATE_SUSPEND | CHIPSET_STATE_ON);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	/* Disable charging. */
+	rv = ppc_vbus_sink_enable(port, 0);
+	if (rv)
+		return rv;
+
+	pd_set_vbus_discharge(port, 0);
+
+	/* Provide Vbus. */
+	rv = ppc_vbus_source_enable(port, 1);
+	if (rv)
+		return rv;
+
+	if (port == 1)
+		rt1718s_gpio_set_level(port, GPIO_EN_USB_C1_5V_OUT, 1);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+int board_vbus_source_enabled(int port)
+{
+	return ppc_is_sourcing_vbus(port);
+}
diff --git a/baseboard/dedede/baseboard.c b/baseboard/dedede/baseboard.c
index 87eba1771b..22034a09bd 100644
--- a/baseboard/dedede/baseboard.c
+++ b/baseboard/dedede/baseboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,16 +8,24 @@
 #include "adc.h"
 #include "board_config.h"
 #include "cbi_fw_config.h"
+#include "charger/isl923x_public.h"
+#include "charger/sm5803.h"
 #include "chipset.h"
 #include "common.h"
+#include "console.h"
 #include "extpower.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "host_command.h"
-#include "intel_x86.h"
+#include "power/icelake.h"
+#include "power/intel_x86.h"
 #include "system.h"
 #include "usb_pd.h"
 
+/* Console output macros */
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
 /******************************************************************************/
 /*
  * PWROK signal configuration, see the PWROK Generation Flow Diagram in the
@@ -73,7 +81,6 @@ const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[] = {
 };
 const int pwrok_signal_deassert_count = ARRAY_SIZE(pwrok_signal_deassert_list);
 
-
 /*
  * Dedede does not use hibernate wake pins, but the super low power "Z-state"
  * instead in which the EC is powered off entirely.  Power will be restored to
@@ -104,7 +111,7 @@ __override void board_after_rsmrst(int rsmrst)
  * can call this function once it detects a VBUS presence change with which we
  * can trigger the HOOK_AC_CHANGE hook.
  */
-__override void board_vbus_present_change(void)
+__override void board_check_extpower(void)
 {
 	static int last_extpower_present;
 	int extpower_present = extpower_is_present();
@@ -115,7 +122,7 @@ __override void board_vbus_present_change(void)
 	last_extpower_present = extpower_present;
 }
 
-uint32_t pp3300_a_pgood;
+atomic_t pp3300_a_pgood;
 __override int intel_x86_get_pg_ec_dsw_pwrok(void)
 {
 	/*
@@ -124,12 +131,25 @@ __override int intel_x86_get_pg_ec_dsw_pwrok(void)
 	 * read the ADC values during an interrupt, therefore, this power good
 	 * value is updated via ADC threshold interrupts.
 	 */
+	if (chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_SUSPEND)) {
+		/*
+		 * The ADC interrupts are disabled in suspend for PP3000_A,
+		 * therefore this value may be stale. Assume that the PGOOD
+		 * follows the enable signal for this case only.
+		 */
+		if (!gpio_get_level(GPIO_EN_PP3300_A)) {
+			CPRINTS("EN_PP3300_A is low, assuming PG is low!");
+			atomic_clear(&pp3300_a_pgood);
+		} else {
+			atomic_or(&pp3300_a_pgood, 1);
+		}
+	}
 	return pp3300_a_pgood;
 }
 
 /* Store away PP300_A good status before sysjumps */
-#define BASEBOARD_SYSJUMP_TAG	0x4242 /* BB */
-#define BASEBOARD_HOOK_VERSION	1
+#define BASEBOARD_SYSJUMP_TAG 0x4242 /* BB */
+#define BASEBOARD_HOOK_VERSION 1
 
 static void pp3300_a_pgood_preserve(void)
 {
@@ -146,13 +166,13 @@ static void baseboard_prepare_power_signals(void)
 	stored = (const int *)system_get_jump_tag(BASEBOARD_SYSJUMP_TAG,
 						  &version, &size);
 	if (stored && (version == BASEBOARD_HOOK_VERSION) &&
-					(size == sizeof(pp3300_a_pgood)))
+	    (size == sizeof(pp3300_a_pgood)))
 		/* Valid PP3300 status found, restore before CHIPSET init */
 		pp3300_a_pgood = *stored;
 
 	/* Restore pull-up on PG_PP1050_ST_OD */
 	if (system_jumped_to_this_image() &&
-					gpio_get_level(GPIO_RSMRST_L_PGOOD))
+	    gpio_get_level(GPIO_PG_EC_RSMRST_ODL))
 		board_after_rsmrst(1);
 }
 DECLARE_HOOK(HOOK_INIT, baseboard_prepare_power_signals, HOOK_PRIO_FIRST);
@@ -170,8 +190,8 @@ __override int intel_x86_get_pg_ec_all_sys_pwrgd(void)
 	 * PGOOD.
 	 */
 	return gpio_get_level(GPIO_PG_PP1050_ST_OD) &&
-		gpio_get_level(GPIO_PG_DRAM_OD) &&
-		gpio_get_level(GPIO_PG_VCCIO_EXT_OD);
+	       gpio_get_level(GPIO_PG_DRAM_OD) &&
+	       gpio_get_level(GPIO_PG_VCCIO_EXT_OD);
 }
 
 __override int power_signal_get_level(enum gpio_signal signal)
@@ -182,13 +202,12 @@ __override int power_signal_get_level(enum gpio_signal signal)
 	if (signal == GPIO_PG_EC_ALL_SYS_PWRGD)
 		return intel_x86_get_pg_ec_all_sys_pwrgd();
 
-	if (IS_ENABLED(CONFIG_HOSTCMD_ESPI)) {
+	if (IS_ENABLED(CONFIG_HOST_INTERFACE_ESPI)) {
 		/* Check signal is from GPIOs or VWs */
 		if (espi_signal_is_vw(signal))
-			return espi_vw_get_wire(signal);
+			return espi_vw_get_wire((enum espi_vw_signal)signal);
 	}
 	return gpio_get_level(signal);
-
 }
 
 void baseboard_all_sys_pgood_interrupt(enum gpio_signal signal)
@@ -199,13 +218,14 @@ void baseboard_all_sys_pgood_interrupt(enum gpio_signal signal)
 	 * driver to.
 	 * Early protos do not pull VCCST_PWRGD below Vil in hardware logic,
 	 * so we need to do the same for this signal.
-	 * Pull EN_VCCIO_EXT to LOW, which ensures VCCST_PWRGD remains LOW during
-	 * SLP_S3_L assertion.
+	 * Pull EN_VCCIO_EXT to LOW, which ensures VCCST_PWRGD remains LOW
+	 * during SLP_S3_L assertion.
 	 */
 	if (!gpio_get_level(GPIO_SLP_S3_L)) {
 		gpio_set_level(GPIO_ALL_SYS_PWRGD, 0);
 		gpio_set_level(GPIO_EN_VCCIO_EXT, 0);
 		gpio_set_level(GPIO_EC_AP_VCCST_PWRGD_OD, 0);
+		gpio_set_level(GPIO_EC_AP_PCH_PWROK_OD, 0);
 	}
 	/* Now chain off to the normal power signal interrupt handler. */
 	power_signal_interrupt(signal);
@@ -213,31 +233,56 @@ void baseboard_all_sys_pgood_interrupt(enum gpio_signal signal)
 
 void baseboard_chipset_startup(void)
 {
+#ifdef CONFIG_PWM_KBLIGHT
 	/* Allow keyboard backlight to be enabled */
 	gpio_set_level(GPIO_EN_KB_BL, 1);
+#endif
 }
 DECLARE_HOOK(HOOK_CHIPSET_STARTUP, baseboard_chipset_startup,
 	     HOOK_PRIO_DEFAULT);
 
 void baseboard_chipset_shutdown(void)
 {
+#ifdef CONFIG_PWM_KBLIGHT
 	/* Turn off the keyboard backlight if it's on. */
 	gpio_set_level(GPIO_EN_KB_BL, 0);
+#endif
 }
 DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, baseboard_chipset_shutdown,
 	     HOOK_PRIO_DEFAULT);
 
 void board_hibernate_late(void)
 {
+	volatile uint32_t busy = 0;
+
 	/* Disable any pull-ups on C0 and C1 interrupt lines */
 	gpio_set_flags(GPIO_USB_C0_INT_ODL, GPIO_INPUT);
+#if CONFIG_USB_PD_PORT_MAX_COUNT > 1
 	gpio_set_flags(GPIO_USB_C1_INT_ODL, GPIO_INPUT);
-
+#endif
 	/*
 	 * Turn on the Z state.  This will not return as it will cut power to
 	 * the EC.
 	 */
 	gpio_set_level(GPIO_EN_SLP_Z, 1);
+
+	/*
+	 * Interrupts are disabled at this point, so busy-loop to consume some
+	 * time (something on the order of at least 1 second, depending on EC
+	 * chip being used)
+	 */
+	while (busy < 100000)
+		busy++;
+
+	/*
+	 * Still awake despite turning on zombie state?  Reset with AP off is
+	 * the best we can do in this situation.
+	 */
+	system_reset(SYSTEM_RESET_LEAVE_AP_OFF);
+
+	/* Await our reset */
+	while (1)
+		;
 }
 
 int board_is_i2c_port_powered(int port)
@@ -249,21 +294,28 @@ int board_is_i2c_port_powered(int port)
 	return chipset_in_state(CHIPSET_STATE_ANY_OFF) ? 0 : 1;
 }
 
-int extpower_is_present(void)
+#if defined(CONFIG_CHARGER_RAA489000) || defined(CONFIG_CHARGER_SM5803)
+__overridable int extpower_is_present(void)
 {
-	int vbus_present = 0;
 	int port;
+	int rv;
+	bool acok;
+	enum ec_error_list (*check_acok)(int port, bool *acok);
+
+	if (IS_ENABLED(CONFIG_CHARGER_RAA489000))
+		check_acok = raa489000_is_acok;
+	else if (IS_ENABLED(CONFIG_CHARGER_SM5803))
+		check_acok = sm5803_is_acok;
+
+	for (port = 0; port < board_get_usb_pd_port_count(); port++) {
+		rv = check_acok(port, &acok);
+		if ((rv == EC_SUCCESS) && acok)
+			return 1;
+	}
 
-	/*
-	 * Boards define pd_snk_is_vbus_provided() with something appropriate
-	 * for their hardware
-	 */
-	for (port = 0; port < board_get_usb_pd_port_count(); port++)
-		if (pd_get_power_role(port) == PD_ROLE_SINK)
-			vbus_present |= pd_snk_is_vbus_provided(port);
-
-	return vbus_present;
+	return 0;
 }
+#endif
 
 __override uint32_t board_override_feature_flags0(uint32_t flags0)
 {
diff --git a/baseboard/dedede/baseboard.h b/baseboard/dedede/baseboard.h
index 42fad27e71..6cb781add6 100644
--- a/baseboard/dedede/baseboard.h
+++ b/baseboard/dedede/baseboard.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,79 +8,110 @@
 #ifndef __CROS_EC_BASEBOARD_H
 #define __CROS_EC_BASEBOARD_H
 
+#define CONFIG_LTO
+
+/* Free up additional flash space. */
+#undef CONFIG_CMD_I2C_SCAN
+#undef CONFIG_CMD_I2C_XFER
+
 /*
  * By default, enable all console messages excepted HC, ACPI and event:
  * The sensor stack is generating a lot of activity.
  */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
-#define CONFIG_SUPPRESSED_HOST_COMMANDS \
-	EC_CMD_CONSOLE_SNAPSHOT, EC_CMD_CONSOLE_READ, EC_CMD_USB_PD_DISCOVERY,\
-	EC_CMD_USB_PD_POWER_INFO, EC_CMD_PD_GET_LOG_ENTRY, \
-	EC_CMD_MOTION_SENSE_CMD, EC_CMD_GET_NEXT_EVENT
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
+#undef CONFIG_HOSTCMD_DEBUG_MODE
+#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
 
 /*
  * Variant EC defines. Pick one:
  * VARIANT_DEDEDE_EC_NPCX796FC
  */
-#if defined(VARIANT_DEDEDE_EC_NPCX796FC)
-	/* NPCX7 config */
-	#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
-	#define NPCX_TACH_SEL2    0  /* No tach. */
-
-	/* Internal SPI flash on NPCX7 */
-	#define CONFIG_FLASH_SIZE (512 * 1024)
-	#define CONFIG_SPI_FLASH_REGS
-	#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
-#elif defined(VARIANT_DEDEDE_EC_IT8320)
-	#define I2C_PORT_EEPROM		IT83XX_I2C_CH_A
-	#define I2C_PORT_BATTERY	IT83XX_I2C_CH_B
-	#define I2C_PORT_SENSOR		IT83XX_I2C_CH_C
-	#define I2C_PORT_SUB_USB_C1	IT83XX_I2C_CH_E
-	#define I2C_PORT_USB_C0		IT83XX_I2C_CH_F
-
-	#define I2C_ADDR_EEPROM_FLAGS	0x50
-
-	#define CONFIG_ADC_VOLTAGE_COMPARATOR	/* ITE ADC thresholds */
-
-	#undef CONFIG_UART_TX_BUF_SIZE		/* UART */
-	#define CONFIG_UART_TX_BUF_SIZE 4096
+#if defined(VARIANT_DEDEDE_EC_NPCX796FC) || defined(VARIANT_KEEBY_EC_NPCX797FC)
+/* NPCX7 config */
+#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */
+#define NPCX_TACH_SEL2 0 /* No tach. */
+
+/* Internal SPI flash on NPCX7 */
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
+#define CONFIG_SPI_FLASH_REGS
+#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
+#elif defined(VARIANT_DEDEDE_EC_IT8320) || defined(VARIANT_KEEBY_EC_IT8320)
+/* IT83XX config */
+#define CONFIG_IT83XX_VCC_1P8V
+/* I2C Bus Configuration */
+#define I2C_PORT_EEPROM IT83XX_I2C_CH_A
+#define I2C_PORT_BATTERY IT83XX_I2C_CH_B
+#define I2C_PORT_SENSOR IT83XX_I2C_CH_C
+#define I2C_PORT_SUB_USB_C1 IT83XX_I2C_CH_E
+#define I2C_PORT_USB_C0 IT83XX_I2C_CH_F
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+
+#define CONFIG_ADC_VOLTAGE_COMPARATOR /* ITE ADC thresholds */
+
+#undef CONFIG_UART_TX_BUF_SIZE /* UART */
+#define CONFIG_UART_TX_BUF_SIZE 4096
+
+/*
+ * Limit maximal ODR to 125Hz, the EC is using ~5ms per sample at
+ * 48MHz core cpu clock.
+ */
+#define CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ 125000
 #else
-#error "Must define a VARIANT_DEDEDE_EC!"
+#error "Must define a VARIANT_[DEDEDE|KEEBY]_EC!"
+#endif
+
+/*
+ * The key difference between Keeby and Dedede is that Keeby variants don't have
+ * a connection to H1 and therefore do not use EFS2.
+ */
+#if defined(VARIANT_KEEBY_EC_NPCX797FC) || defined(VARIANT_KEEBY_EC_IT8320)
+#define KEEBY_VARIANT 1
+#else
+#define KEEBY_VARIANT 0
 #endif
 
 /*
  * Remapping of schematic GPIO names to common GPIO names expected (hardcoded)
  * in the EC code base.
  */
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_EC_INT_L		GPIO_EC_AP_MKBP_INT_L
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_U
-#define GPIO_ENTERING_RW	GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2		GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN	GPIO_ECH1_PACKET_MODE
-#define GPIO_PCH_DSW_PWROK	GPIO_EC_AP_DPWROK
-#define GPIO_PCH_PWRBTN_L	GPIO_EC_AP_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L	GPIO_EC_AP_RSMRST_L
-#define GPIO_PCH_RTCRST		GPIO_EC_AP_RTCRST
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_PCH_WAKE_L		GPIO_EC_AP_WAKE_ODL
-#define GPIO_PG_EC_RSMRST_ODL	GPIO_RSMRST_PWRGD_L
-#define GPIO_POWER_BUTTON_L	GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD	GPIO_RSMRST_PWRGD_L
-#define GPIO_SYS_RESET_L	GPIO_SYS_RST_ODL
-#define GPIO_USB_C0_DP_HPD	GPIO_EC_AP_USB_C0_HPD
-#define GPIO_USB_C1_DP_HPD	GPIO_EC_AP_USB_C1_HDMI_HPD
-#define GPIO_VOLUME_UP_L	GPIO_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L	GPIO_VOLDN_BTN_ODL
-#define GPIO_WP			GPIO_EC_WP_OD
-#define GMR_TABLET_MODE_GPIO_L	GPIO_LID_360_L
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_AP_MKBP_INT_L
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_U
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#if !KEEBY_VARIANT
+#define GPIO_PACKET_MODE_EN GPIO_ECH1_PACKET_MODE
+#endif
+#define GPIO_PCH_DSW_PWROK GPIO_EC_AP_DPWROK
+#define GPIO_PCH_PWRBTN_L GPIO_EC_AP_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_AP_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_AP_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L
+#define GPIO_PCH_WAKE_L GPIO_EC_AP_WAKE_ODL
+#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_PWRGD_L
+#if KEEBY_VARIANT
+#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL
+#else
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+#endif
+#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_PWRGD_L
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_USB_C0_DP_HPD GPIO_EC_AP_USB_C0_HPD
+#define GPIO_USB_C1_DP_HPD GPIO_EC_AP_USB_C1_HDMI_HPD
+#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL
+#define GPIO_WP GPIO_EC_WP_OD
+#define GPIO_TABLET_MODE_L GPIO_LID_360_L
 
 /* Common EC defines */
 
 /* Work around double CR50 reset by waiting in initial power on. */
+#if !KEEBY_VARIANT
 #define CONFIG_BOARD_RESET_AFTER_POWER_ON
+#endif
 
 /* Optional console commands */
 #define CONFIG_CMD_CHARGER_DUMP
@@ -92,20 +123,27 @@
 /* Enable i2ctrace command */
 #define CONFIG_I2C_DEBUG
 
+/* Assert CCD when a debug device is connected */
+#if !KEEBY_VARIANT
+#define CONFIG_ASSERT_CCD_MODE_ON_DTS_CONNECT
+#endif
+
 /* EC Modules */
 #define CONFIG_ADC
 #define CONFIG_CRC8
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 #define CONFIG_HOSTCMD_EVENTS
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_CONTROLLER
 #define CONFIG_I2C_BUS_MAY_BE_UNPOWERED
 #define CONFIG_LOW_POWER_IDLE
 #define CONFIG_POWER_PP5000_CONTROL
 #define CONFIG_VBOOT_HASH
 #define CONFIG_VSTORE
 #define CONFIG_VSTORE_SLOT_COUNT 1
+#if !KEEBY_VARIANT
 #define CONFIG_VBOOT_EFS2
+#endif
 
 /* Battery */
 #define CONFIG_BATTERY_CUT_OFF
@@ -120,32 +158,42 @@
 #define CONFIG_WP_ACTIVE_HIGH
 
 /* CBI */
-#define CONFIG_CROS_BOARD_INFO
+#define CONFIG_CBI_EEPROM
 #define CONFIG_BOARD_VERSION_CBI
+#if KEEBY_VARIANT
+#define CONFIG_EEPROM_CBI_WP
+#endif
 
 /* Charger */
 #define CONFIG_CHARGE_MANAGER
 #define CONFIG_CHARGER
 #define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT 256
-#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 1
+#define CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT 256
+#define CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT 256
 #define CONFIG_USB_CHARGER
 #define CONFIG_TRICKLE_CHARGING
 
 /* Keyboard */
 #define CONFIG_KEYBOARD_COL2_INVERTED
 #define CONFIG_KEYBOARD_PROTOCOL_8042
+#define CONFIG_MKBP_INPUT_DEVICES
 
 /* Backlight */
 #define CONFIG_BACKLIGHT_LID
-#define GPIO_ENABLE_BACKLIGHT   GPIO_EN_BL_OD
+#define GPIO_ENABLE_BACKLIGHT GPIO_EN_BL_OD
 
 /* LED */
 #define CONFIG_LED_COMMON
 
+/* Sensors */
+#define CONFIG_MKBP_EVENT
+#define CONFIG_MKBP_EVENT_WAKEUP_MASK 0
+#define CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT
+
 /* SoC */
 #define CONFIG_BOARD_HAS_RTC_RESET
 #define CONFIG_CHIPSET_JASPERLAKE
+#define CONFIG_CHIPSET_RESET_HOOK
 #define CONFIG_POWER_BUTTON
 #define CONFIG_POWER_BUTTON_X86
 #define CONFIG_POWER_COMMON
@@ -161,13 +209,17 @@
 #define CONFIG_USBC_VCONN
 #define CONFIG_USBC_VCONN_SWAP
 
+/* Temp Sensor */
+#define CONFIG_TEMP_SENSOR_POWER
+#define GPIO_TEMP_SENSOR_POWER GPIO_EN_PP3300_A
+#define CONFIG_TEMP_SENSOR_FIRST_READ_DELAY_MS 500
+
 /* USB PD */
 #define CONFIG_USB_PD_ALT_MODE
 #define CONFIG_USB_PD_ALT_MODE_DFP
 #define CONFIG_USB_PD_DP_HPD_GPIO
 #define CONFIG_USB_PD_DUAL_ROLE
 #define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT TYPEC_RP_3A0
 #define CONFIG_USB_PD_REV30
 #define CONFIG_USB_PD_TCPM_MUX
 #define CONFIG_USB_PD_TCPM_TCPCI
@@ -175,41 +227,43 @@
 /* #define CONFIG_USB_PD_VBUS_DETECT_CHARGER */
 #define CONFIG_USB_PD_VBUS_MEASURE_CHARGER
 #define CONFIG_USB_PD_DECODE_SOP
+#if KEEBY_VARIANT
+#define CONFIG_USB_PID 0x5059
+#else
 #define CONFIG_USB_PID 0x5042
+#endif
 #define CONFIG_USB_POWER_DELIVERY
 #define CONFIG_USB_PD_TCPMV2
 #define CONFIG_USB_DRP_ACC_TRYSRC
 #define CONFIG_HOSTCMD_PD_CONTROL
 
+#if !KEEBY_VARIANT
 /* UART COMMAND */
 #define CONFIG_CMD_CHARGEN
+#endif
 
 /* Define typical operating power and max power. */
-#define PD_MAX_VOLTAGE_MV     20000
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_POWER_MW       45000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_POWER_MW 45000
 #define PD_OPERATING_POWER_MW 15000
 
 /* TODO(b:147314141): Verify these timings */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000	/* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	250000	/* us */
-#define PD_VCONN_SWAP_DELAY		5000	/* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
+
+/* System safe mode for improved panic debugging */
+#define CONFIG_SYSTEM_SAFE_MODE
 
 #ifndef __ASSEMBLER__
 
+#include "atomic_t.h"
 #include "common.h"
 #include "gpio_signal.h"
 
 /* Common enums */
 #if defined(VARIANT_DEDEDE_EC_NPCX796FC)
-#elif defined(VARIANT_DEDEDE_EC_IT8320)
-	enum board_vcmp {
-		VCMP_SNS_PP3300_LOW,
-		VCMP_SNS_PP3300_HIGH,
-		VCMP_COUNT
-	};
-#else
-#error "Must define a VARIANT_DEDEDE_EC!"
+#elif defined(VARIANT_DEDEDE_EC_IT8320) || defined(VARIANT_KEEBY_EC_IT8320)
+enum board_vcmp { VCMP_SNS_PP3300_LOW, VCMP_SNS_PP3300_HIGH, VCMP_COUNT };
 #endif
 
 /* Interrupt handler for signals that are used to generate ALL_SYS_PGOOD. */
@@ -222,7 +276,7 @@ void board_reset_pd_mcu(void);
  * Bit to indicate if the PP3000_A rail's power is good. Will be updated by ADC
  * interrupt.
  */
-extern uint32_t pp3300_a_pgood;
+extern atomic_t pp3300_a_pgood;
 
 #endif /* !__ASSEMBLER__ */
 #endif /* __CROS_EC_BASEBOARD_H */
diff --git a/baseboard/dedede/build.mk b/baseboard/dedede/build.mk
index e86d1976ed..af71eb2222 100644
--- a/baseboard/dedede/build.mk
+++ b/baseboard/dedede/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -8,4 +8,6 @@
 
 baseboard-y=baseboard.o cbi_fw_config.o
 baseboard-$(VARIANT_DEDEDE_EC_NPCX796FC)+=variant_ec_npcx796fc.o
+baseboard-$(VARIANT_KEEBY_EC_NPCX797FC)+=variant_ec_npcx796fc.o
 baseboard-$(VARIANT_DEDEDE_EC_IT8320)+=variant_ec_it8320.o
+baseboard-$(VARIANT_KEEBY_EC_IT8320)+=variant_ec_it8320.o
diff --git a/baseboard/dedede/cbi_fw_config.c b/baseboard/dedede/cbi_fw_config.c
index 62b582e3b9..612c51700d 100644
--- a/baseboard/dedede/cbi_fw_config.c
+++ b/baseboard/dedede/cbi_fw_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -33,20 +33,38 @@ enum fw_config_db get_cbi_fw_config_db(void)
 	return ((cached_fw_config & FW_CONFIG_DB_MASK) >> FW_CONFIG_DB_OFFSET);
 }
 
+enum fw_config_stylus get_cbi_fw_config_stylus(void)
+{
+	return ((cached_fw_config & FW_CONFIG_STYLUS_MASK) >>
+		FW_CONFIG_STYLUS_OFFSET);
+}
+
 enum fw_config_kblight_type get_cbi_fw_config_kblight(void)
 {
-	return ((cached_fw_config & FW_CONFIG_KB_BL_MASK)
-			>> FW_CONFIG_KB_BL_OFFSET);
+	return ((cached_fw_config & FW_CONFIG_KB_BL_MASK) >>
+		FW_CONFIG_KB_BL_OFFSET);
 }
 
 enum fw_config_tablet_mode_type get_cbi_fw_config_tablet_mode(void)
 {
-	return ((cached_fw_config & FW_CONFIG_TABLET_MODE_MASK)
-			>> FW_CONFIG_TABLET_MODE_OFFSET);
+	return ((cached_fw_config & FW_CONFIG_TABLET_MODE_MASK) >>
+		FW_CONFIG_TABLET_MODE_OFFSET);
 }
 
 int get_cbi_fw_config_keyboard(void)
 {
-	return ((cached_fw_config & FW_CONFIG_KB_LAYOUT_MASK)
-			>> FW_CONFIG_KB_LAYOUT_OFFSET);
+	return ((cached_fw_config & FW_CONFIG_KB_LAYOUT_MASK) >>
+		FW_CONFIG_KB_LAYOUT_OFFSET);
+}
+
+enum fw_config_numeric_pad_type get_cbi_fw_config_numeric_pad(void)
+{
+	return ((cached_fw_config & FW_CONFIG_KB_NUMPAD_MASK) >>
+		FW_CONFIG_KB_NUMPAD_OFFSET);
+}
+
+enum fw_config_hdmi_type get_cbi_fw_config_hdmi(void)
+{
+	return ((cached_fw_config & FW_CONFIG_HDMI_MASK) >>
+		FW_CONFIG_HDMI_OFFSET);
 }
diff --git a/baseboard/dedede/cbi_fw_config.h b/baseboard/dedede/cbi_fw_config.h
index 8c10df03e3..80712f2849 100644
--- a/baseboard/dedede/cbi_fw_config.h
+++ b/baseboard/dedede/cbi_fw_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,10 +18,24 @@ enum fw_config_db {
 	DB_2C,
 	DB_1C_LTE,
 	DB_1A_HDMI,
+	DB_1C_1A,
+	DB_LTE_HDMI,
+	DB_1C_1A_LTE,
 	DB_1C,
+	DB_1A_HDMI_LTE,
 };
-#define FW_CONFIG_DB_OFFSET			0
-#define FW_CONFIG_DB_MASK			GENMASK(3, 0)
+#define FW_CONFIG_DB_OFFSET 0
+#define FW_CONFIG_DB_MASK GENMASK(3, 0)
+
+/*
+ * Stylus (1 bit)
+ */
+enum fw_config_stylus {
+	STYLUS_ABSENT = 0,
+	STYLUS_PRESENT = 1,
+};
+#define FW_CONFIG_STYLUS_OFFSET 4
+#define FW_CONFIG_STYLUS_MASK GENMASK(4, 4)
 
 /*
  * Keyboard backlight (1 bit)
@@ -30,8 +44,18 @@ enum fw_config_kblight_type {
 	KB_BL_ABSENT = 0,
 	KB_BL_PRESENT = 1,
 };
-#define FW_CONFIG_KB_BL_OFFSET			8
-#define FW_CONFIG_KB_BL_MASK			GENMASK(8, 8)
+#define FW_CONFIG_KB_BL_OFFSET 8
+#define FW_CONFIG_KB_BL_MASK GENMASK(8, 8)
+
+/*
+ * Keyboard numeric pad (1 bit)
+ */
+enum fw_config_numeric_pad_type {
+	NUMERIC_PAD_ABSENT = 0,
+	NUMERIC_PAD_PRESENT = 1,
+};
+#define FW_CONFIG_KB_NUMPAD_OFFSET 9
+#define FW_CONFIG_KB_NUMPAD_MASK GENMASK(9, 9)
 
 /*
  * Tablet Mode (1 bit)
@@ -40,15 +64,28 @@ enum fw_config_tablet_mode_type {
 	TABLET_MODE_ABSENT = 0,
 	TABLET_MODE_PRESENT = 1,
 };
-#define FW_CONFIG_TABLET_MODE_OFFSET		10
-#define FW_CONFIG_TABLET_MODE_MASK		GENMASK(10, 10)
+#define FW_CONFIG_TABLET_MODE_OFFSET 10
+#define FW_CONFIG_TABLET_MODE_MASK GENMASK(10, 10)
+
+#define FW_CONFIG_KB_LAYOUT_OFFSET 12
+#define FW_CONFIG_KB_LAYOUT_MASK GENMASK(13, 12)
 
-#define FW_CONFIG_KB_LAYOUT_OFFSET		12
-#define FW_CONFIG_KB_LAYOUT_MASK		GENMASK(13, 12)
+/*
+ * Hdmi (1 bit)
+ */
+enum fw_config_hdmi_type {
+	HDMI_ABSENT = 0,
+	HDMI_PRESENT = 1,
+};
+#define FW_CONFIG_HDMI_OFFSET 17
+#define FW_CONFIG_HDMI_MASK GENMASK(17, 17)
 
 enum fw_config_db get_cbi_fw_config_db(void);
+enum fw_config_stylus get_cbi_fw_config_stylus(void);
 enum fw_config_kblight_type get_cbi_fw_config_kblight(void);
 enum fw_config_tablet_mode_type get_cbi_fw_config_tablet_mode(void);
+enum fw_config_numeric_pad_type get_cbi_fw_config_numeric_pad(void);
+enum fw_config_hdmi_type get_cbi_fw_config_hdmi(void);
 
 int get_cbi_fw_config_keyboard(void);
 
diff --git a/baseboard/dedede/variant_ec_it8320.c b/baseboard/dedede/variant_ec_it8320.c
index d7e2785c4a..f03af6ccd9 100644
--- a/baseboard/dedede/variant_ec_it8320.c
+++ b/baseboard/dedede/variant_ec_it8320.c
@@ -1,9 +1,9 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-/* Common code for VARIANT_DEDEDE_IT8320 configuration */
+/* Common code for VARIANT_[DEDEDE|KEEBY]_IT8320 configuration */
 
 #include "adc_chip.h"
 #include "atomic.h"
@@ -16,11 +16,11 @@
 #include "power.h"
 #include "registers.h"
 
-#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
 
 static void pp3300_a_pgood_low(void)
 {
-	deprecated_atomic_clear_bits(&pp3300_a_pgood, 1);
+	atomic_clear_bits(&pp3300_a_pgood, 1);
 
 	/* Disable low interrupt while asserted */
 	vcmp_enable(VCMP_SNS_PP3300_LOW, 0);
@@ -37,7 +37,7 @@ static void pp3300_a_pgood_low(void)
 
 static void pp3300_a_pgood_high(void)
 {
-	deprecated_atomic_or(&pp3300_a_pgood, 1);
+	atomic_or(&pp3300_a_pgood, 1);
 
 	/* Disable high interrupt while asserted */
 	vcmp_enable(VCMP_SNS_PP3300_HIGH, 0);
@@ -73,34 +73,42 @@ const struct vcmp_t vcmp_list[] = {
 BUILD_ASSERT(ARRAY_SIZE(vcmp_list) <= CHIP_VCMP_COUNT);
 BUILD_ASSERT(ARRAY_SIZE(vcmp_list) == VCMP_COUNT);
 
+#if !defined(BOARD_DIBBI) && !defined(BOARD_TARANZA) && !defined(BOARD_BOXY)
 /* I2C Ports */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		"eeprom", I2C_PORT_EEPROM, 400, GPIO_EC_I2C_EEPROM_SCL,
-		GPIO_EC_I2C_EEPROM_SDA
-	},
-
-	{
-		"battery", I2C_PORT_BATTERY, 100, GPIO_EC_I2C_BATTERY_SCL,
-		GPIO_EC_I2C_BATTERY_SDA
-	},
-
-	{
-		"sensor", I2C_PORT_SENSOR, 400, GPIO_EC_I2C_SENSOR_SCL,
-		GPIO_EC_I2C_SENSOR_SDA
-	},
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_EEPROM_SCL,
+	  .sda = GPIO_EC_I2C_EEPROM_SDA },
+
+	{ .name = "battery",
+	  .port = I2C_PORT_BATTERY,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_BATTERY_SCL,
+	  .sda = GPIO_EC_I2C_BATTERY_SDA },
+
+#if defined(HAS_TASK_MOTIONSENSE) || defined(BOARD_SHOTZO)
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_SENSOR_SCL,
+	  .sda = GPIO_EC_I2C_SENSOR_SDA },
+#endif
 
 #if CONFIG_USB_PD_PORT_MAX_COUNT > 1
-	{
-		"sub_usbc1", I2C_PORT_SUB_USB_C1, 1000,
-		GPIO_EC_I2C_SUB_USB_C1_SCL, GPIO_EC_I2C_SUB_USB_C1_SDA
-	},
+	{ .name = "sub_usbc1",
+	  .port = I2C_PORT_SUB_USB_C1,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_SUB_USB_C1_SCL,
+	  .sda = GPIO_EC_I2C_SUB_USB_C1_SDA },
 #endif
 
-	{
-		"usbc0", I2C_PORT_USB_C0, 1000, GPIO_EC_I2C_USB_C0_SCL,
-		GPIO_EC_I2C_USB_C0_SDA
-	},
+	{ .name = "usbc0",
+	  .port = I2C_PORT_USB_C0,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C0_SCL,
+	  .sda = GPIO_EC_I2C_USB_C0_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
+#endif
diff --git a/baseboard/dedede/variant_ec_npcx796fc.c b/baseboard/dedede/variant_ec_npcx796fc.c
index ae7890c473..366fca878e 100644
--- a/baseboard/dedede/variant_ec_npcx796fc.c
+++ b/baseboard/dedede/variant_ec_npcx796fc.c
@@ -1,11 +1,11 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-/* Common code for VARIANT_DEDEDE_NPCX796FC configuration */
+/* Common code for VARIANT_[DEDEDE|KEEBY]_NPCX79[6/7]FC configuration */
 
-#include "adc_chip.h"
+#include "adc.h"
 #include "atomic.h"
 #include "chipset.h"
 #include "common.h"
@@ -21,12 +21,12 @@
 #include "timer.h"
 
 /* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 void pp3300_a_pgood_high(void)
 {
-	deprecated_atomic_or(&pp3300_a_pgood, 1);
+	atomic_or(&pp3300_a_pgood, 1);
 
 	/* Disable this interrupt while it's asserted. */
 	npcx_adc_thresh_int_enable(NPCX_ADC_THRESH1, 0);
@@ -42,7 +42,7 @@ void pp3300_a_pgood_high(void)
 
 void pp3300_a_pgood_low(void)
 {
-	deprecated_atomic_clear_bits(&pp3300_a_pgood, 1);
+	atomic_clear_bits(&pp3300_a_pgood, 1);
 
 	/* Disable this interrupt while it's asserted. */
 	npcx_adc_thresh_int_enable(NPCX_ADC_THRESH2, 0);
@@ -79,7 +79,7 @@ static void set_up_adc_irqs(void)
 	npcx_adc_thresh_int_enable(NPCX_ADC_THRESH1, 1);
 	npcx_adc_thresh_int_enable(NPCX_ADC_THRESH2, 1);
 }
-DECLARE_HOOK(HOOK_INIT, set_up_adc_irqs, HOOK_PRIO_INIT_ADC+1);
+DECLARE_HOOK(HOOK_INIT, set_up_adc_irqs, HOOK_PRIO_INIT_ADC + 1);
 
 static void disable_adc_irqs_deferred(void)
 {
@@ -101,10 +101,11 @@ static void disable_adc_irqs_deferred(void)
 DECLARE_DEFERRED(disable_adc_irqs_deferred);
 
 /*
- * The ADC interrupts are only needed for booting up.  The assumption is that
- * the PP3300_A rail will not go down during runtime.  Therefore, we'll disable
- * the ADC interrupts shortly after booting up and also after shutting down.
+ * The assumption is that the PP3300_A rail will not go down during runtime.
+ * Therefore, we'll disable the ADC interrupts shortly after booting up
+ * and also after shutting down.
  */
+static void enable_adc_irqs(void);
 static void disable_adc_irqs(void)
 {
 	int delay = 200 * MSEC;
@@ -114,8 +115,10 @@ static void disable_adc_irqs(void)
 	 * to G3.  Therefore, we'll postpone disabling the ADC IRQs until after
 	 * this occurs.
 	 */
-	if (chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF))
+	if (chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF)) {
 		delay = 15 * SECOND;
+		enable_adc_irqs();
+	}
 	hook_call_deferred(&disable_adc_irqs_deferred_data, delay);
 }
 DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, disable_adc_irqs, HOOK_PRIO_DEFAULT);
@@ -138,11 +141,11 @@ DECLARE_HOOK(HOOK_CHIPSET_RESUME, disable_adc_irqs, HOOK_PRIO_DEFAULT);
  */
 static void enable_adc_irqs(void)
 {
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
+	if (chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF)) {
 		CPRINTS("%s", __func__);
 		hook_call_deferred(&disable_adc_irqs_deferred_data, -1);
-		npcx_set_adc_repetitive(adc_channels[ADC_VSNS_PP3300_A].input_ch,
-					1);
+		npcx_set_adc_repetitive(
+			adc_channels[ADC_VSNS_PP3300_A].input_ch, 1);
 		npcx_adc_thresh_int_enable(NPCX_ADC_THRESH1, 1);
 		npcx_adc_thresh_int_enable(NPCX_ADC_THRESH2, 1);
 	}
@@ -158,31 +161,45 @@ static void enable_adc_irqs_via_lid(void)
 DECLARE_HOOK(HOOK_LID_CHANGE, enable_adc_irqs_via_lid, HOOK_PRIO_DEFAULT);
 
 /* I2C Ports */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		"eeprom", I2C_PORT_EEPROM, 1000, GPIO_EC_I2C_EEPROM_SCL,
-		GPIO_EC_I2C_EEPROM_SDA
-	},
-
-	{
-		"battery", I2C_PORT_BATTERY, 100, GPIO_EC_I2C_BATTERY_SCL,
-		GPIO_EC_I2C_BATTERY_SDA
-	},
-
-	{
-		"sensor", I2C_PORT_SENSOR, 400, GPIO_EC_I2C_SENSOR_SCL,
-		GPIO_EC_I2C_SENSOR_SDA
-	},
-
-	{
-		"usbc0", I2C_PORT_USB_C0, 1000, GPIO_EC_I2C_USB_C0_SCL,
-		GPIO_EC_I2C_USB_C0_SDA
-	},
-
-	{
-		"sub_usbc1", I2C_PORT_SUB_USB_C1, 1000,
-		GPIO_EC_I2C_SUB_USB_C1_SCL, GPIO_EC_I2C_SUB_USB_C1_SDA
-	},
+__attribute__((weak)) const struct i2c_port_t i2c_ports[] = {
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_EEPROM_SCL,
+	  .sda = GPIO_EC_I2C_EEPROM_SDA },
+
+	{ .name = "battery",
+	  .port = I2C_PORT_BATTERY,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_BATTERY_SCL,
+	  .sda = GPIO_EC_I2C_BATTERY_SDA },
+
+#ifdef HAS_TASK_MOTIONSENSE
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_SENSOR_SCL,
+	  .sda = GPIO_EC_I2C_SENSOR_SDA },
+#endif
+
+	{ .name = "usbc0",
+	  .port = I2C_PORT_USB_C0,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C0_SCL,
+	  .sda = GPIO_EC_I2C_USB_C0_SDA },
+#if CONFIG_USB_PD_PORT_MAX_COUNT > 1
+	{ .name = "sub_usbc1",
+	  .port = I2C_PORT_SUB_USB_C1,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_SUB_USB_C1_SCL,
+	  .sda = GPIO_EC_I2C_SUB_USB_C1_SDA },
+#endif
+#ifdef BOARD_BUGZZY
+	{ .name = "lcd",
+	  .port = I2C_PORT_LCD,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_LCD_SCL,
+	  .sda = GPIO_EC_I2C_LCD_SDA },
+#endif
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
diff --git a/baseboard/dragonegg/baseboard.c b/baseboard/dragonegg/baseboard.c
deleted file mode 100644
index 5841bef1b1..0000000000
--- a/baseboard/dragonegg/baseboard.c
+++ /dev/null
@@ -1,369 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* DragonEgg family-specific configuration */
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "chipset.h"
-#include "console.h"
-#include "driver/bc12/max14637.h"
-#include "driver/charger/bq25710.h"
-#include "driver/ppc/nx20p348x.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/ppc/syv682x.h"
-#include "driver/tcpm/it83xx_pd.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/tcpm.h"
-#include "driver/tcpm/tusb422.h"
-#include "espi.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "icelake.h"
-#include "keyboard_scan.h"
-#include "power.h"
-#include "timer.h"
-#include "util.h"
-#include "tcpci.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define USB_PD_PORT_ITE_0	0
-#define USB_PD_PORT_ITE_1	1
-#define USB_PD_PORT_TUSB422_2	2
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-/******************************************************************************/
-/* Keyboard scan setting */
-struct keyboard_scan_config keyscan_config = {
-	/*
-	 * F3 key scan cycle completed but scan input is not
-	 * charging to logic high when EC start scan next
-	 * column for "T" key, so we set .output_settle_us
-	 * to 80us from 50us.
-	 */
-	.output_settle_us = 80,
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-/******************************************************************************/
-/* Wake up pins */
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_LID_OPEN,
-	GPIO_AC_PRESENT,
-	GPIO_POWER_BUTTON_L,
-};
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-/* I2C port map configuration */
-/* TODO(b/111125177): Increase these speeds to 400 kHz and verify operation */
-const struct i2c_port_t i2c_ports[] = {
-	{"eeprom", IT83XX_I2C_CH_A, 100, GPIO_I2C0_SCL, GPIO_I2C0_SDA},
-	{"sensor", IT83XX_I2C_CH_B, 100, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"usbc12",  IT83XX_I2C_CH_C, 100, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-	{"usbc0",  IT83XX_I2C_CH_E, 100, GPIO_I2C4_SCL, GPIO_I2C4_SDA},
-	{"power",  IT83XX_I2C_CH_F, 100, GPIO_I2C5_SCL, GPIO_I2C5_SDA}
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* Charger Chips */
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = BQ25710_SMBUS_ADDR1_FLAGS,
-		.drv = &bq25710_drv,
-	},
-};
-
-/******************************************************************************/
-/* PWROK signal configuration */
-/*
- * On Dragonegg the ALL_SYS_PWRGD, VCCST_PWRGD, PCH_PWROK, and SYS_PWROK
- * signals are handled by the board. No EC control needed.
- */
-const struct intel_x86_pwrok_signal pwrok_signal_assert_list[] = {};
-const int pwrok_signal_assert_count = ARRAY_SIZE(pwrok_signal_assert_list);
-
-const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[] = {};
-const int pwrok_signal_deassert_count = ARRAY_SIZE(pwrok_signal_assert_list);
-
-/******************************************************************************/
-/* Chipset callbacks/hooks */
-
-/* Called on AP S5 -> S3 transition */
-static void baseboard_chipset_startup(void)
-{
-	/* TODD(b/111121615): Need to fill out this hook */
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, baseboard_chipset_startup,
-	     HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0iX -> S0 transition */
-static void baseboard_chipset_resume(void)
-{
-	/* TODD(b/111121615): Need to fill out this hook */
-	/* Enable display backlight. */
-	gpio_set_level(GPIO_EDP_BKTLEN_OD, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, baseboard_chipset_resume, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0 -> S0iX transition */
-static void baseboard_chipset_suspend(void)
-{
-	/* TODD(b/111121615): Need to fill out this hook */
-	/* Enable display backlight. */
-	gpio_set_level(GPIO_EDP_BKTLEN_OD, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, baseboard_chipset_suspend,
-	     HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S5 transition */
-static void baseboard_chipset_shutdown(void)
-{
-	/* TODD(b/111121615): Need to fill out this hook */
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, baseboard_chipset_shutdown,
-	     HOOK_PRIO_DEFAULT);
-
-void board_hibernate(void)
-{
-	int timeout_ms = 20;
-	/*
-	 * Disable the TCPC power rail and the PP5000 rail before going into
-	 * hibernate. Note, these 2 rails are powered up as the default state in
-	 * gpio.inc.
-	 */
-	gpio_set_level(GPIO_EN_PP5000, 0);
-	/* Wait for PP5000 to drop before disabling PP3300_TCPC */
-	while (gpio_get_level(GPIO_PP5000_PG_OD) && timeout_ms > 0) {
-		msleep(1);
-		timeout_ms--;
-	}
-	if (!timeout_ms)
-		CPRINTS("PP5000_PG didn't go low after 20 msec");
-	gpio_set_level(GPIO_EN_PP3300_TCPC, 0);
-}
-/******************************************************************************/
-/* USB-C TPCP Configuration */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_ITE_0] = {
-		.bus_type = EC_BUS_TYPE_EMBEDDED,
-		/* TCPC is embedded within EC so no i2c config needed */
-		.drv = &it83xx_tcpm_drv,
-		/* Alert is active-low, push-pull */
-		.flags = 0,
-	},
-
-	[USB_PD_PORT_ITE_1] = {
-		.bus_type = EC_BUS_TYPE_EMBEDDED,
-		/* TCPC is embedded within EC so no i2c config needed */
-		.drv = &it83xx_tcpm_drv,
-		/* Alert is active-low, push-pull */
-		.flags = 0,
-	},
-
-	[USB_PD_PORT_TUSB422_2] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USBC1C2,
-			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
-		},
-		.drv = &tusb422_tcpm_drv,
-		/* Alert is active-low, push-pull */
-		.flags = 0,
-	},
-};
-
-/******************************************************************************/
-/* USB-C PPC Configuration */
-struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_ITE_0] = {
-		.i2c_port = I2C_PORT_USBC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-
-	[USB_PD_PORT_ITE_1] = {
-		.i2c_port = I2C_PORT_USBC1C2,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv
-	},
-
-	[USB_PD_PORT_TUSB422_2] = {
-		.i2c_port = I2C_PORT_USBC1C2,
-		.i2c_addr_flags = NX20P3481_ADDR2_FLAGS,
-		.drv = &nx20p348x_drv,
-	},
-};
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_ITE_0] = {
-		.usb_port = USB_PD_PORT_ITE_0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-	},
-
-	[USB_PD_PORT_ITE_1] = {
-		.usb_port = USB_PD_PORT_ITE_1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-	},
-
-	[USB_PD_PORT_TUSB422_2] = {
-		.usb_port = USB_PD_PORT_TUSB422_2,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-	},
-};
-
-/******************************************************************************/
-/* BC 1.2 chip Configuration */
-const struct max14637_config_t max14637_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.chip_enable_pin = GPIO_USB_C0_BC12_VBUS_ON_ODL,
-		.chg_det_pin = GPIO_USB_C0_BC12_CHG_MAX,
-		.flags = MAX14637_FLAGS_ENABLE_ACTIVE_LOW,
-	},
-	{
-		.chip_enable_pin = GPIO_USB_C1_BC12_VBUS_ON_ODL,
-		.chg_det_pin = GPIO_USB_C1_BC12_CHG_MAX,
-		.flags = MAX14637_FLAGS_ENABLE_ACTIVE_LOW,
-	},
-	{
-		.chip_enable_pin = GPIO_USB_C2_BC12_VBUS_ON_ODL,
-		.chg_det_pin = GPIO_USB_C2_BC12_CHG_MAX,
-		.flags = MAX14637_FLAGS_ENABLE_ACTIVE_LOW,
-	},
-};
-
-/* Power Delivery and charging functions */
-
-void baseboard_tcpc_init(void)
-{
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPPC_INT_L);
-	gpio_enable_interrupt(GPIO_USB_C2_TCPPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C2_TCPC_INT_ODL);
-
-}
-DECLARE_HOOK(HOOK_INIT, baseboard_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-	/*
-	 * Since C0/C1 TCPC are embedded within EC, we don't need the PDCMD
-	 * tasks.The (embedded) TCPC status since chip driver code will
-	 * handles its own interrupts and forward the correct events to
-	 * the PD_C0 task. See it83xx/intc.c
-	 */
-
-	if (!gpio_get_level(GPIO_USB_C2_TCPC_INT_ODL))
-		status = PD_STATUS_TCPC_ALERT_2;
-
-	return status;
-}
-
-/**
- * Reset all system PD/TCPC MCUs -- currently only called from
- * handle_pending_reboot() in common/power.c just before hard
- * resetting the system. This logic is likely not needed as the
- * PP3300_A rail should be dropped on EC reset.
- */
-void board_reset_pd_mcu(void)
-{
-	/*
-	 * C0 & C1: The internal TCPC on ITE EC does not have a reset signal,
-	 * but it will get reset when the EC gets reset.
-	 */
-}
-void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
-{
-	/*
-	 * We ignore the cc_pin because the polarity should already be set
-	 * correctly in the PPC driver via the pd state machine.
-	 */
-	if (ppc_set_vconn(port, enabled) != EC_SUCCESS)
-		cprints(CC_USBPD, "C%d: Failed %sabling vconn",
-			port, enabled ? "en" : "dis");
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_valid_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	int i;
-
-	if (!is_valid_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	if (port == CHARGE_PORT_NONE) {
-		CPRINTSUSB("Disabling all charger ports");
-
-		/* Disable all ports. */
-		for (i = 0; i < ppc_cnt; i++) {
-			/*
-			 * Do not return early if one fails otherwise we can
-			 * get into a boot loop assertion failure.
-			 */
-			if (ppc_vbus_sink_enable(i, 0))
-				CPRINTSUSB("Disabling C%d as sink failed.", i);
-		}
-
-		return EC_SUCCESS;
-	}
-
-	/* Check if the port is sourcing VBUS. */
-	if (ppc_is_sourcing_vbus(port)) {
-		CPRINTFUSB("Skip enable C%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	CPRINTSUSB("New charge port: C%d", port);
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < ppc_cnt; i++) {
-		if (i == port)
-			continue;
-
-		if (ppc_vbus_sink_enable(i, 0))
-			CPRINTSUSB("C%d: sink path disable failed.", i);
-	}
-
-	/* Enable requested charge port. */
-	if (ppc_vbus_sink_enable(port, 1)) {
-		CPRINTSUSB("C%d: sink path enable failed.", port);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
-}
diff --git a/baseboard/dragonegg/baseboard.h b/baseboard/dragonegg/baseboard.h
deleted file mode 100644
index dccabccbde..0000000000
--- a/baseboard/dragonegg/baseboard.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* DragonEgg board configuration */
-
-#ifndef __CROS_EC_BASEBOARD_H
-#define __CROS_EC_BASEBOARD_H
-
-/* EC console commands  */
-#define CONFIG_CMD_BATT_MFG_ACCESS
-
-#define CONFIG_CHIPSET_ICELAKE
-#define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_EXTPOWER_GPIO
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_HOST_EVENT
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_X86
-#define CONFIG_POWER_PP5000_CONTROL
-/* TODO(b/111155507): Don't enable SOiX for now */
-/* #define CONFIG_POWER_S0IX */
-/* #define CONFIG_POWER_TRACK_HOST_SLEEP_STATE */
-
-/* EC Defines */
-#define CONFIG_ADC
-#define CONFIG_PWM
-#define CONFIG_VBOOT_HASH
-#define CONFIG_VSTORE
-#define CONFIG_VSTORE_SLOT_COUNT 1
-
-/* CBI */
-/*
- * TODO (b/117174246): When EEPROMs are programmed, can use EEPROM for board
- * version. But for P0/P1 boards rely on GPIO signals.
- */
-/* #define CONFIG_BOARD_VERSION_CBI */
-#define CONFIG_CROS_BOARD_INFO
-#define CONFIG_CRC8
-
-/* Common Keyboard Defines */
-#define CONFIG_CMD_KEYBOARD
-#define CONFIG_KEYBOARD_BOARD_CONFIG
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-#define CONFIG_KEYBOARD_COL2_INVERTED
-#define CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2
-
-/* Common charger defines */
-#define CONFIG_CHARGE_MANAGER
-#define CONFIG_CHARGE_RAMP_HW
-#define CONFIG_CHARGER
-#define CONFIG_CHARGER_BQ25710
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT 512 /* Allow low-current USB charging */
-#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 1
-#define CONFIG_CHARGER_NARROW_VDC
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
-
-/* Common battery defines */
-#define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY  "LION"
-#define CONFIG_BATTERY_FUEL_GAUGE
-#define CONFIG_BATTERY_HW_PRESENT_CUSTOM
-#define CONFIG_BATTERY_PRESENT_CUSTOM
-#define CONFIG_BATTERY_REVIVE_DISCONNECT
-#define CONFIG_BATTERY_SMART
-
-/* BC 1.2 Detection */
-#define CONFIG_BC12_DETECT_MAX14637
-#define CONFIG_USB_CHARGER
-
-/* USB Type C and USB PD defines */
-#undef CONFIG_USB_PD_TCPC_LOW_POWER
-#undef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_VBUS_DETECT_PPC
-#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP	/* C0 & C1 TCPC: ITE EC */
-#define CONFIG_USB_PD_TCPM_TUSB422	/* C1 TCPC: TUSB422 */
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV1
-#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 2
-
-/*
- * TODO (b/111281797): DragonEgg has 3 ports. Only adding support for the port
- * on the MLB for now. In addition, this config option will likely move to
- * board.h as it likely board dependent and not same across all follower boards.
- */
-#define CONFIG_USB_PD_PORT_MAX_COUNT 3
-#define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT TYPEC_RP_3A0
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_DISCHARGE_PPC
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_PD_VBUS_DETECT_PPC
-/*
- * TODO(b/113541930): ADC measurements are available for port 0 and 1, but not
- * port 2.
- */
-#define CONFIG_USB_PD_VBUS_MEASURE_NOT_PRESENT
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_MUX_VIRTUAL
-#define CONFIG_USBC_PPC_SN5S330		/* C0 PPC */
-#define CONFIG_USBC_PPC_SYV682X		/* C1 PPC */
-#define CONFIG_USBC_PPC_NX20P3481		/* C2 PPC */
-#define CONFIG_USBC_PPC_VCONN
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-
-#define CONFIG_HOSTCMD_PD_CONTROL
-#define CONFIG_CMD_PPC_DUMP
-
-/* TODO(b/111281797): Use correct PD delay values */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000	/* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	250000	/* us */
-#define PD_VCONN_SWAP_DELAY		5000	/* us */
-
-/* TODO(b/111281797): Use correct PD power values */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		45000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
-
-/* I2C Bus Configuration */
-#define CONFIG_I2C
-#define CONFIG_I2C_MASTER
-#define I2C_PORT_BATTERY	IT83XX_I2C_CH_F	/* Shared bus */
-#define I2C_PORT_CHARGER	IT83XX_I2C_CH_F	/* Shared bus */
-#define I2C_PORT_SENSOR		IT83XX_I2C_CH_B
-#define I2C_PORT_USBC0		IT83XX_I2C_CH_E
-#define I2C_PORT_USBC1C2	IT83XX_I2C_CH_C
-#define I2C_PORT_EEPROM		IT83XX_I2C_CH_A
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-
-#ifndef __ASSEMBLER__
-
-/* Forward declare common (within DragonEgg) board-specific functions */
-void board_reset_pd_mcu(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BASEBOARD_H */
diff --git a/baseboard/dragonegg/battery.c b/baseboard/dragonegg/battery.c
deleted file mode 100644
index 0c4ec32903..0000000000
--- a/baseboard/dragonegg/battery.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery.h"
-#include "battery_fuel_gauge.h"
-#include "battery_smart.h"
-#include "gpio.h"
-#include "system.h"
-
-static enum battery_present batt_pres_prev = BP_NOT_SURE;
-
-enum battery_present battery_hw_present(void)
-{
-	enum battery_present bp;
-	/* The GPIO is low when the battery is physically present */
-	/*
-	 * TODO(b/111704193): The signal GPIO_EC_BATT_PRES_ODL has an issue
-	 * where it's floating (?) at ~2V when it should be low when the battery
-	 * is connected. The signal will read correctly following a cold reset
-	 * and the battery is connected, but following a warm reboot, it reads
-	 * high. In order to allow charging to work, replacing this with the a
-	 * check that the Operation Status register can be read. Once the HW
-	 * issue is resolved then change this back to checking the physical
-	 * presence pin.
-	 *
-	 */
-
-	if (system_get_board_version() == 0)
-		/* P0 boards can't use gpio signal */
-		bp = (battery_get_disconnect_state() ==
-		      BATTERY_DISCONNECT_ERROR) ? BP_NO : BP_YES;
-	else
-		/* P1 boards can read presence from gpio signal */
-		bp = gpio_get_level(GPIO_EC_BATT_PRES_ODL) ? BP_NO : BP_YES;
-
-	return bp;
-}
-
-static int battery_init(void)
-{
-	int batt_status;
-
-	return battery_status(&batt_status) ? 0 :
-		!!(batt_status & STATUS_INITIALIZED);
-}
-
-/*
- * Physical detection of battery.
- */
-static enum battery_present battery_check_present_status(void)
-{
-	enum battery_present batt_pres;
-
-	/* Get the physical hardware status */
-	batt_pres = battery_hw_present();
-
-	/*
-	 * If the battery is not physically connected, then no need to perform
-	 * any more checks.
-	 */
-	if (batt_pres != BP_YES)
-		return batt_pres;
-
-	/*
-	 * If the battery is present now and was present last time we checked,
-	 * return early.
-	 */
-	if (batt_pres == batt_pres_prev)
-		return batt_pres;
-
-	/*
-	 * Ensure that battery is:
-	 * 1. Not in cutoff
-	 * 2. Initialized
-	 */
-	if (battery_is_cut_off() != BATTERY_CUTOFF_STATE_NORMAL ||
-	    battery_init() == 0) {
-		batt_pres = BP_NO;
-	}
-
-	return batt_pres;
-}
-
-enum battery_present battery_is_present(void)
-{
-	batt_pres_prev = battery_check_present_status();
-	return batt_pres_prev;
-}
diff --git a/baseboard/dragonegg/build.mk b/baseboard/dragonegg/build.mk
deleted file mode 100644
index 7f3c8a3669..0000000000
--- a/baseboard/dragonegg/build.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-# -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# DragonEgg baseboard specific files build
-#
-
-baseboard-y=baseboard.o
-baseboard-$(CONFIG_BATTERY_SMART)+=battery.o
-baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
diff --git a/baseboard/dragonegg/usb_pd_policy.c b/baseboard/dragonegg/usb_pd_policy.c
deleted file mode 100644
index cc1cfd5aca..0000000000
--- a/baseboard/dragonegg/usb_pd_policy.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Shared USB-C policy for DragonEgg boards */
-
-#include "charge_manager.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "system.h"
-#include "tcpci.h"
-#include "tcpm.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_check_vconn_swap(int port)
-{
-	/* Only allow vconn swap if pp5000_A rail is enabled */
-	return gpio_get_level(GPIO_EN_PP5000);
-}
-
-__override void pd_execute_data_swap(int port,
-				     enum pd_data_role data_role)
-{
-	/* On DragonEgg, only the first port can act as OTG */
-	if (port == 0)
-		gpio_set_level(GPIO_CHG_VAP_OTG_EN, (data_role == PD_ROLE_UFP));
-}
-
-void pd_power_supply_reset(int port)
-{
-	int prev_en;
-
-	prev_en = ppc_is_sourcing_vbus(port);
-
-	/* Disable VBUS. */
-	ppc_vbus_source_enable(port, 0);
-
-	/* Enable discharge if we were previously sourcing 5V */
-	if (prev_en)
-		pd_set_vbus_discharge(port, 1);
-
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	/* Give back the current quota we are no longer using */
-	charge_manager_source_port(port, 0);
-#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	int rv;
-
-	/* Disable charging. */
-	rv = ppc_vbus_sink_enable(port, 0);
-	if (rv)
-		return rv;
-
-	pd_set_vbus_discharge(port, 0);
-
-	/* Provide Vbus. */
-	rv = ppc_vbus_source_enable(port, 1);
-	if (rv)
-		return rv;
-
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	/* Ensure we advertise the proper available current quota */
-	charge_manager_source_port(port, 1);
-#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_USB_PD_VBUS_DETECT_PPC
-int pd_snk_is_vbus_provided(int port)
-{
-	/*
-	 * TODO(b/112661747): Until per port VBUS detection methods are
-	 * supported, DragonEgg needs to have CONFIG_USB_PD_VBUS_DETECT_PPC
-	 * defined, but the nx20p3481 PPC on port 2 does not support VBUS
-	 * detection. In the meantime, check specifically for port 2, and rely
-	 * on the TUSB422 TCPC for VBUS status. Note that the tcpm method can't
-	 * be called directly here as it's not supported unless
-	 * CONFIG_USB_PD_VBUS_DETECT_TCPC is defined.
-	 */
-	int reg;
-
-	if (port == 2) {
-		if (tcpc_read(port, TCPC_REG_POWER_STATUS, &reg))
-			return 0;
-		return reg & TCPC_REG_POWER_STATUS_VBUS_PRES ? 1 : 0;
-	}
-	return ppc_is_vbus_present(port);
-}
-#endif
-
-int board_vbus_source_enabled(int port)
-{
-	return ppc_is_sourcing_vbus(port);
-}
diff --git a/baseboard/goroh/baseboard.c b/baseboard/goroh/baseboard.c
new file mode 100644
index 0000000000..554437ab6e
--- /dev/null
+++ b/baseboard/goroh/baseboard.c
@@ -0,0 +1,267 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Goroh baseboard-specific configuration */
+
+#include "adc.h"
+#include "adc_chip.h"
+#include "baseboard_usbc_config.h"
+#include "button.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "driver/accel_lis2dw12.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "driver/als_tcs3400.h"
+#include "driver/charger/isl923x.h"
+#include "driver/ppc/syv682x.h"
+#include "driver/tcpm/it83xx_pd.h"
+#include "driver/temp_sensor/thermistor.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "motion_sense.h"
+#include "power.h"
+#include "power_button.h"
+#include "spi.h"
+#include "switch.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "temp_sensor.h"
+#include "timer.h"
+#include "uart.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_ppc.h"
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+
+/* Wake-up pins for hibernate */
+enum gpio_signal hibernate_wake_pins[] = {
+	GPIO_ACOK_OD,
+	GPIO_LID_OPEN,
+	GPIO_POWER_BUTTON_L,
+};
+int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
+
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+};
+
+/* BC12 skeleton to make build happy. */
+struct bc12_config bc12_ports[CHARGE_PORT_COUNT] = {};
+
+const int usb_port_enable[USB_PORT_COUNT] = {};
+
+/* Called on AP S3 -> S0 transition */
+static void board_chipset_resume(void)
+{
+	gpio_set_level(GPIO_EC_BL_EN_OD, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S0 -> S3 transition */
+static void board_chipset_suspend(void)
+{
+	gpio_set_level(GPIO_EC_BL_EN_OD, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
+
+/* USB Mux */
+
+/*
+ * I2C channels (A, B, and C) are using the same timing registers (00h~07h)
+ * at default.
+ * In order to set frequency independently for each channels,
+ * We use timing registers 09h~0Bh, and the supported frequency will be:
+ * 50KHz, 100KHz, 400KHz, or 1MHz.
+ * I2C channels (D, E and F) can be set different frequency on different ports.
+ * The I2C(D/E/F) frequency depend on the frequency of SMBus Module and
+ * the individual prescale register.
+ * The frequency of SMBus module is 24MHz on default.
+ * The allowed range of I2C(D/E/F) frequency is as following setting.
+ * SMBus Module Freq = PLL_CLOCK / ((IT83XX_ECPM_SCDCR2 & 0x0F) + 1)
+ * (SMBus Module Freq / 510) <=  I2C Freq <= (SMBus Module Freq / 8)
+ * Channel D has multi-function and can be used as UART interface.
+ * Channel F is reserved for EC debug.
+ */
+
+/* I2C ports */
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "bat_chg",
+	  .port = IT83XX_I2C_CH_A,
+	  .kbps = 100,
+	  .scl = GPIO_I2C_A_SCL,
+	  .sda = GPIO_I2C_A_SDA },
+	{ .name = "sensor",
+	  .port = IT83XX_I2C_CH_B,
+	  .kbps = 400,
+	  .scl = GPIO_I2C_B_SCL,
+	  .sda = GPIO_I2C_B_SDA },
+	{ .name = "usb0",
+	  .port = IT83XX_I2C_CH_C,
+	  .kbps = 400,
+	  .scl = GPIO_I2C_C_SCL,
+	  .sda = GPIO_I2C_C_SDA },
+	{ .name = "usb1",
+	  .port = IT83XX_I2C_CH_E,
+	  .kbps = 400,
+	  .scl = GPIO_I2C_E_SCL,
+	  .sda = GPIO_I2C_E_SDA },
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+int board_allow_i2c_passthru(const struct i2c_cmd_desc_t *cmd_desc)
+{
+	return (cmd_desc->port == I2C_PORT_VIRTUAL_BATTERY);
+}
+
+void board_overcurrent_event(int port, int is_overcurrented)
+{
+	/* TODO: check correct operation for GOROH */
+}
+
+const struct cc_para_t *board_get_cc_tuning_parameter(enum usbpd_port port)
+{
+	const static struct cc_para_t
+		cc_parameter[CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT] = {
+			{
+				.rising_time =
+					IT83XX_TX_PRE_DRIVING_TIME_1_UNIT,
+				.falling_time =
+					IT83XX_TX_PRE_DRIVING_TIME_2_UNIT,
+			},
+			{
+				.rising_time =
+					IT83XX_TX_PRE_DRIVING_TIME_1_UNIT,
+				.falling_time =
+					IT83XX_TX_PRE_DRIVING_TIME_2_UNIT,
+			},
+		};
+
+	return &cc_parameter[port];
+}
+
+void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
+{
+	/*
+	 * We ignore the cc_pin and PPC vconn because polarity and PPC vconn
+	 * should already be set correctly in the PPC driver via the pd
+	 * state machine.
+	 */
+}
+
+int board_set_active_charge_port(int port)
+{
+	int i;
+	int is_valid_port = ((port == 0) || (port == 1));
+
+	if (!is_valid_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTS("Disabling all charger ports");
+
+		/* Disable all ports. */
+		for (i = 0; i < ppc_cnt; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (ppc_vbus_sink_enable(i, 0))
+				CPRINTS("Disabling C%d as sink failed.", i);
+		}
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (ppc_is_sourcing_vbus(port)) {
+		CPRINTS("Skip enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTS("New charge port: C%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < ppc_cnt; i++) {
+		if (i == port)
+			continue;
+
+		if (ppc_vbus_sink_enable(i, 0))
+			CPRINTS("C%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTS("C%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+int ppc_get_alert_status(int port)
+{
+	if (port == 0)
+		return gpio_get_level(GPIO_USB_C0_FAULT_ODL) == 0;
+	if (port == 1)
+		return gpio_get_level(GPIO_USB_C1_FAULT_ODL) == 0;
+
+	return 0;
+}
+
+/* Lid */
+#ifndef TEST_BUILD
+/* This callback disables keyboard when convertibles are fully open */
+void lid_angle_peripheral_enable(int enable)
+{
+	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
+
+	if (enable) {
+		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
+	} else {
+		/*
+		 * Ensure that the chipset is off before disabling the keyboard.
+		 * When the chipset is on, the EC keeps the keyboard enabled and
+		 * the AP decides whether to ignore input devices or not.
+		 */
+		if (!chipset_in_s0)
+			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
+	}
+}
+#endif
+
+/* Called on AP S5 -> S3 transition */
+static void board_chipset_startup(void)
+{
+	gpio_set_level(GPIO_EN_USB_C1_MUX_PWR, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S3 -> S5 transition */
+static void board_chipset_shutdown(void)
+{
+	gpio_set_level(GPIO_EN_USB_C1_MUX_PWR, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
diff --git a/baseboard/goroh/baseboard.h b/baseboard/goroh/baseboard.h
new file mode 100644
index 0000000000..594686f0bf
--- /dev/null
+++ b/baseboard/goroh/baseboard.h
@@ -0,0 +1,195 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Goroh board configuration */
+
+#ifndef __CROS_EC_BASEBOARD_H
+#define __CROS_EC_BASEBOARD_H
+
+/* IT81202-bx config */
+/*
+ * NOTE: we need to make correct VCC voltage selection here if EC's VCC isn't
+ * connect to 1.8v on other versions.
+ */
+#define CONFIG_IT83XX_VCC_1P8V
+
+/*
+ * On power-on, H1 releases the EC from reset but then quickly asserts and
+ * releases the reset a second time. This means the EC sees 2 resets:
+ * (1) power-on reset, (2) reset-pin reset. This config will
+ * allow the second reset to be treated as a power-on.
+ */
+#define CONFIG_BOARD_RESET_AFTER_POWER_ON
+#define CONFIG_CHIPSET_FALCONLITE
+#define CONFIG_EXTPOWER_GPIO
+#define CONFIG_HIBERNATE_WAKE_PINS_DYNAMIC
+
+/* EC defines */
+#define CONFIG_CBI_EEPROM
+
+/* Chipset */
+#define CONFIG_CMD_AP_RESET_LOG
+#define CONFIG_HOSTCMD_AP_RESET
+#define CONFIG_HOST_COMMAND_STATUS
+#define CONFIG_LOW_POWER_IDLE
+#define CONFIG_LOW_POWER_S0
+#define CONFIG_POWER_BUTTON
+#define CONFIG_POWER_COMMON
+#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
+#define CONFIG_PWM
+#define CONFIG_VBOOT_HASH
+#define CONFIG_VOLUME_BUTTONS
+#define CONFIG_WP_ACTIVE_HIGH
+
+/* Battery */
+#define CONFIG_BATTERY_CRITICAL_SHUTDOWN_CUT_OFF
+#define CONFIG_BATTERY_CUT_OFF
+#define CONFIG_BATTERY_FUEL_GAUGE
+#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL
+#define CONFIG_BATTERY_SMART
+
+/* Charger */
+#define ADC_AMON_BMON ADC_CHARGER_AMON_R /* ADC name remap */
+#define ADC_PSYS ADC_CHARGER_PMON /* ADC name remap */
+#define CONFIG_CHARGE_MANAGER
+#define CONFIG_CHARGER
+#define CONFIG_CHARGE_RAMP_HW
+#define CONFIG_CHARGER_DISCHARGE_ON_AC
+#define CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT 512
+#define CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT 512
+#define CONFIG_CHARGER_ISL9238C
+#define CONFIG_CHARGER_MAINTAIN_VBAT
+#define CONFIG_CHARGER_OTG
+#define CONFIG_CHARGER_PSYS
+#define CONFIG_CHARGER_SENSE_RESISTOR 10 /* BOARD_RS2 */
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 /* BOARD_RS1 */
+
+/* Keyboard */
+#define CONFIG_CMD_KEYBOARD
+#define CONFIG_KEYBOARD_COL2_INVERTED
+#define CONFIG_KEYBOARD_PROTOCOL_MKBP
+#define CONFIG_MKBP_USE_GPIO
+#define CONFIG_KEYBOARD_BACKLIGHT
+#define CONFIG_PWM_KBLIGHT
+#define CONFIG_KBLIGHT_ENABLE_PIN
+#define GPIO_EN_KEYBOARD_BACKLIGHT GPIO_EN_PPVAR_KB_BL_X
+
+/* I2C */
+#define CONFIG_I2C
+#define CONFIG_I2C_CONTROLLER
+#define CONFIG_I2C_PASSTHRU_RESTRICTED
+#define CONFIG_I2C_VIRTUAL_BATTERY
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+#define I2C_PORT_EEPROM IT83XX_I2C_CH_A
+#define I2C_PORT_CHARGER IT83XX_I2C_CH_A
+#define I2C_PORT_BATTERY IT83XX_I2C_CH_A
+#define I2C_PORT_ACCEL IT83XX_I2C_CH_B
+#define I2C_PORT_USB_C0 IT83XX_I2C_CH_C
+#define I2C_PORT_USB_C1 IT83XX_I2C_CH_E
+#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
+#define CONFIG_SMBUS_PEC
+
+/* LED */
+#define CONFIG_LED_COMMON
+
+/* PD / USB-C / PPC */
+#define CONFIG_CMD_PPC_DUMP
+#define CONFIG_HOSTCMD_PD_CONTROL
+#define CONFIG_IT83XX_TUNE_CC_PHY
+#define CONFIG_USB_MUX_VIRTUAL
+#define CONFIG_USBC_PPC
+#define CONFIG_USBC_PPC_DEDICATED_INT
+#define CONFIG_USBC_PPC_POLARITY
+#define CONFIG_USBC_PPC_SYV682C
+#define CONFIG_USBC_PPC_VCONN
+#define CONFIG_USBC_SS_MUX
+#define CONFIG_USBC_VCONN
+#define CONFIG_USBC_VCONN_SWAP
+#define CONFIG_USB_DRP_ACC_TRYSRC
+#define CONFIG_USBC_RETIMER_PS8818 /* C1 */
+#define CONFIG_USB_PD_ALT_MODE
+#define CONFIG_USB_PD_ALT_MODE_DFP
+#define CONFIG_USB_PD_DECODE_SOP
+#define CONFIG_USB_PD_DISCHARGE
+#define CONFIG_USB_PD_DISCHARGE_PPC
+#define CONFIG_USB_PD_DP_HPD_GPIO
+#define CONFIG_USB_PD_DP_HPD_GPIO_CUSTOM
+#define CONFIG_USB_PD_DUAL_ROLE
+#define CONFIG_USB_PD_FRS_PPC
+#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 2
+#define CONFIG_USB_PD_LOGGING
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#define CONFIG_USB_PD_REV30
+#define CONFIG_USB_PD_VBUS_MEASURE_CHARGER
+#define CONFIG_USB_PD_TCPC_LOW_POWER
+#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP
+#define CONFIG_USB_PD_TCPM_TCPCI
+#define CONFIG_USB_PD_TCPMV2
+#define CONFIG_USB_PD_TRY_SRC
+#define CONFIG_USB_PD_VBUS_DETECT_PPC
+#define CONFIG_USB_PID 0x5566 /* TODO: update PID */
+#define CONFIG_USB_POWER_DELIVERY
+
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 60000
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
+
+/* USB-A */
+#define CONFIG_USB_PORT_POWER_DUMB
+#define USB_PORT_COUNT USBA_PORT_COUNT
+
+/* UART */
+#undef CONFIG_UART_TX_BUF_SIZE
+#define CONFIG_UART_TX_BUF_SIZE 4096
+
+/* Sensor */
+#ifdef HAS_TASK_MOTIONSENSE
+#define CONFIG_CMD_ACCEL_INFO
+#define CONFIG_CMD_ACCELS
+
+#define CONFIG_ACCEL_FIFO
+#define CONFIG_ACCEL_FIFO_SIZE 256
+#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
+#endif
+#define CONFIG_LID_SWITCH
+
+/* Fan */
+#define CONFIG_FANS 1
+
+/* SPI / Host Command */
+#define CONFIG_SPI
+
+/* MKBP */
+#define CONFIG_MKBP_EVENT
+
+#define CONFIG_KEYBOARD_PROTOCOL_MKBP
+#define CONFIG_MKBP_USE_GPIO
+
+/* Define the host events which are allowed to wakeup AP in S3. */
+#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK                   \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |    \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |        \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |     \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+/* GPIO name remapping */
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "power/falconlite.h"
+#include "registers.h"
+
+int board_get_version(void);
+void board_reset_pd_mcu(void);
+#endif /* !__ASSEMBLER__ */
+#endif /* __CROS_EC_BASEBOARD_H */
diff --git a/baseboard/goroh/baseboard_usbc_config.h b/baseboard/goroh/baseboard_usbc_config.h
new file mode 100644
index 0000000000..7da00c17d6
--- /dev/null
+++ b/baseboard/goroh/baseboard_usbc_config.h
@@ -0,0 +1,15 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* goroh family-specific USB-C configuration */
+
+#ifndef __CROS_EC_BASEBOARD_USBC_CONFIG_H
+#define __CROS_EC_BASEBOARD_USBC_CONFIG_H
+
+#include "gpio_signal.h"
+
+/* Common definition for the USB PD interrupt handlers. */
+void ppc_interrupt(enum gpio_signal signal);
+#endif /* __CROS_EC_BASEBOARD_USBC_CONFIG_H */
diff --git a/baseboard/goroh/board_id.c b/baseboard/goroh/board_id.c
new file mode 100644
index 0000000000..7bc77d5229
--- /dev/null
+++ b/baseboard/goroh/board_id.c
@@ -0,0 +1,94 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc.h"
+#include "common.h"
+#include "console.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "timer.h"
+#include "util.h"
+
+/**
+ * Conversion based on following table:
+ *
+ * ID | Rp   | Rd   | Voltage
+ *    | kOhm | kOhm | mV
+ * ---+------+------+--------
+ *  0 | 51.1 |  2.2 | 136.2
+ *  1 | 51.1 | 6.81 | 388.1
+ *  2 | 51.1 |   11 | 584.5
+ *  3 | 57.6 |   18 | 785.7
+ *  4 | 51.1 |   22 | 993.2
+ *  5 | 51.1 |   30 | 1220.7
+ *  6 | 51.1 | 39.2 | 1432.6
+ *  7 |   56 |   56 | 1650.0
+ *  8 |   47 | 61.9 | 1875.8
+ *  9 |   47 | 80.6 | 2084.5
+ * 10 |   56 |  124 | 2273.3
+ * 11 | 51.1 |  150 | 2461.5
+ * 12 |   47 |  200 | 2672.1
+ * 13 |   47 |  330 | 2888.6
+ * 14 |   47 |  680 | 3086.7
+ */
+const static int voltage_map[] = {
+	136,  388,  584,  785,	993,  1220, 1432, 1650,
+	1875, 2084, 2273, 2461, 2672, 2888, 3086,
+};
+
+const int threshold_mv = 100;
+
+/**
+ * Convert ADC value to board id using the voltage table above.
+ *
+ * @param ch	ADC channel to read, usually ADC_BOARD_ID_0 or ADC_BOARD_ID_1.
+ *
+ * @return	a non-negative board id, or negative value if error.
+ */
+static int adc_value_to_numeric_id(enum adc_channel ch)
+{
+	int mv;
+
+	gpio_set_level(GPIO_EN_EC_ID_ODL, 0);
+	/* Wait to allow cap charge */
+	msleep(10);
+
+	mv = adc_read_channel(ch);
+	if (mv == ADC_READ_ERROR)
+		mv = adc_read_channel(ch);
+
+	gpio_set_level(GPIO_EN_EC_ID_ODL, 1);
+
+	if (mv == ADC_READ_ERROR)
+		return -EC_ERROR_UNKNOWN;
+
+	for (int i = 0; i < ARRAY_SIZE(voltage_map); i++) {
+		if (IN_RANGE(mv, voltage_map[i] - threshold_mv,
+			     voltage_map[i] + threshold_mv - 1))
+			return i;
+	}
+
+	return -EC_ERROR_UNKNOWN;
+}
+
+static int version = -1;
+
+/* b/163963220: Cache ADC value before board_hibernate_late() reads it */
+static void board_version_init(void)
+{
+	version = adc_value_to_numeric_id(ADC_BOARD_ID);
+	if (version < 0) {
+		ccprints("WARN:BOARD_ID_0");
+		ccprints("Assuming board id = 0");
+
+		version = 0;
+	}
+}
+DECLARE_HOOK(HOOK_INIT, board_version_init, HOOK_PRIO_INIT_ADC + 1);
+
+int board_get_version(void)
+{
+	return version;
+}
diff --git a/baseboard/goroh/build.mk b/baseboard/goroh/build.mk
new file mode 100644
index 0000000000..6a3a386efb
--- /dev/null
+++ b/baseboard/goroh/build.mk
@@ -0,0 +1,12 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Baseboard specific files build
+#
+
+baseboard-y+=baseboard.o
+baseboard-y+=board_id.o
+baseboard-y+=usbc_config.o
+baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
diff --git a/baseboard/goroh/usb_pd_policy.c b/baseboard/goroh/usb_pd_policy.c
new file mode 100644
index 0000000000..e92ced5e89
--- /dev/null
+++ b/baseboard/goroh/usb_pd_policy.c
@@ -0,0 +1,92 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "charge_manager.h"
+#include "chipset.h"
+#include "gpio.h"
+#include "timer.h"
+#include "usb_dp_alt_mode.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+
+#if CONFIG_USB_PD_3A_PORTS != 1
+#error Goroh reference must have at least one 3.0 A port
+#endif
+
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+
+void svdm_set_hpd_gpio(int port, int en)
+{
+	if (port == 0) {
+		gpio_set_level(GPIO_USB_C0_HPD_3V3, en);
+	} else if (port == 1) {
+		gpio_set_level(GPIO_USB_C1_HPD_3V3, en);
+		gpio_set_level(GPIO_USB_C1_HPD_IN, en);
+	}
+}
+
+int svdm_get_hpd_gpio(int port)
+{
+	if (port == 0)
+		return gpio_get_level(GPIO_USB_C0_HPD_3V3);
+	else
+		return gpio_get_level(GPIO_USB_C1_HPD_3V3);
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	return ppc_is_vbus_present(port);
+}
+
+void pd_power_supply_reset(int port)
+{
+	int prev_en;
+
+	prev_en = ppc_is_sourcing_vbus(port);
+
+	/* Disable VBUS. */
+	ppc_vbus_source_enable(port, 0);
+
+	/* Enable discharge if we were previously sourcing 5V */
+	if (prev_en)
+		pd_set_vbus_discharge(port, 1);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_check_vconn_swap(int port)
+{
+	/* Allow Vconn swap if AP is on. */
+	return chipset_in_state(CHIPSET_STATE_SUSPEND | CHIPSET_STATE_ON);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	/* Disable charging. */
+	rv = ppc_vbus_sink_enable(port, 0);
+	if (rv)
+		return rv;
+
+	pd_set_vbus_discharge(port, 0);
+
+	/* Provide Vbus. */
+	rv = ppc_vbus_source_enable(port, 1);
+	if (rv)
+		return rv;
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+int board_vbus_source_enabled(int port)
+{
+	return ppc_is_sourcing_vbus(port);
+}
diff --git a/baseboard/goroh/usbc_config.c b/baseboard/goroh/usbc_config.c
new file mode 100644
index 0000000000..f604a090d1
--- /dev/null
+++ b/baseboard/goroh/usbc_config.c
@@ -0,0 +1,159 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Goroh family-specific USB-C configuration */
+#include "common.h"
+#include "compile_time_macros.h"
+#include "config.h"
+#include "console.h"
+#include "driver/ppc/syv682x_public.h"
+#include "driver/retimer/ps8818_public.h"
+#include "driver/tcpm/it8xxx2_pd_public.h"
+#include "driver/tcpm/tcpci.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
+
+#ifdef CONFIG_BRINGUP
+#define GPIO_SET_LEVEL(pin, lvl) gpio_set_level_verbose(CC_USBPD, pin, lvl)
+#else
+#define GPIO_SET_LEVEL(pin, lvl) gpio_set_level(pin, lvl)
+#endif
+
+/* PPC */
+struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.drv = &syv682x_drv,
+	},
+	{
+		.i2c_port = I2C_PORT_USB_C1,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.drv = &syv682x_drv,
+	},
+};
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/* USB Mux */
+static int goroh_usb_c0_init_mux(const struct usb_mux *me)
+{
+	return virtual_usb_mux_driver.init(me);
+}
+
+static int goroh_usb_c0_set_mux(const struct usb_mux *me, mux_state_t mux_state,
+				bool *ack_required)
+{
+	/*
+	 * b/188376636: Inverse C0 polarity.
+	 * Goroh rev0 CC1/CC2 SBU1/SBU2 are reversed.
+	 * We report inversed polarity to the SoC and SoC we reverse the SBU
+	 * accordingly.
+	 */
+	mux_state = mux_state ^ USB_PD_MUX_POLARITY_INVERTED;
+
+	return virtual_usb_mux_driver.set(me, mux_state, ack_required);
+}
+
+static int goroh_usb_c0_get_mux(const struct usb_mux *me,
+				mux_state_t *mux_state)
+{
+	return virtual_usb_mux_driver.get(me, mux_state);
+}
+
+static struct usb_mux_driver goroh_usb_c0_mux_driver = {
+	.init = goroh_usb_c0_init_mux,
+	.set = goroh_usb_c0_set_mux,
+	.get = goroh_usb_c0_get_mux,
+};
+
+static const struct usb_mux_chain goroh_usb_c1_ps8818_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.i2c_port = I2C_PORT_USB_C1,
+			.i2c_addr_flags = PS8818_I2C_ADDR0_FLAGS,
+			.driver = &ps8818_usb_retimer_driver,
+		},
+	.next = NULL,
+};
+
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	[USBC_PORT_C0] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &goroh_usb_c0_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+	},
+	[USBC_PORT_C1] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &goroh_usb_c1_ps8818_retimer,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
+
+/* TCPC */
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_EMBEDDED,
+		/* TCPC is embedded within EC so no i2c config needed */
+		.drv = &it8xxx2_tcpm_drv,
+		/* Alert is active-low, push-pull */
+		.flags = 0,
+	},
+	{
+		.bus_type = EC_BUS_TYPE_EMBEDDED,
+		/* TCPC is embedded within EC so no i2c config needed */
+		.drv = &it8xxx2_tcpm_drv,
+		/* Alert is active-low, push-pull */
+		.flags = 0,
+	},
+};
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	if (signal == GPIO_USB_C0_FAULT_ODL)
+		/* C0: PPC interrupt */
+		syv682x_interrupt(0);
+	else
+		/* C1: PPC interrupt */
+		syv682x_interrupt(1);
+}
+
+static void board_tcpc_init(void)
+{
+	gpio_enable_interrupt(GPIO_USB_C0_FAULT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_FAULT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * C0 & C1: TCPC is embedded in the EC and processes interrupts in the
+	 * chip code (it83xx/intc.c)
+	 */
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	/*
+	 * C0 & C1: TCPC is embedded in the EC and processes interrupts in the
+	 * chip code (it83xx/intc.c)
+	 */
+	return 0;
+}
diff --git a/baseboard/grunt/baseboard.c b/baseboard/grunt/baseboard.c
index a6192e8789..10e66c50dc 100644
--- a/baseboard/grunt/baseboard.c
+++ b/baseboard/grunt/baseboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,11 +6,9 @@
 /* Grunt family-specific configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "button.h"
 #include "charge_manager.h"
 #include "charge_state.h"
-#include "charge_state_v2.h"
 #include "common.h"
 #include "compile_time_macros.h"
 #include "console.h"
@@ -39,43 +37,38 @@
 #include "switch.h"
 #include "system.h"
 #include "task.h"
-#include "tcpci.h"
+#include "tcpm/tcpci.h"
 #include "temp_sensor.h"
-#include "thermistor.h"
+#include "temp_sensor/thermistor.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0
-	},
-	[ADC_TEMP_SENSOR_SOC] = {
-		"SOC", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0
-	},
-	[ADC_VBUS] = {
-		"VBUS", NPCX_ADC_CH8, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0
-	},
-	[ADC_SKU_ID1] = {
-		"SKU1", NPCX_ADC_CH9, ADC_MAX_VOLT, ADC_READ_MAX+1, 0
-	},
-	[ADC_SKU_ID2] = {
-		"SKU2", NPCX_ADC_CH4, ADC_MAX_VOLT, ADC_READ_MAX+1, 0
-	},
+	[ADC_TEMP_SENSOR_CHARGER] = { "CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				      ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_SOC] = { "SOC", NPCX_ADC_CH1, ADC_MAX_VOLT,
+				  ADC_READ_MAX + 1, 0 },
+	[ADC_VBUS] = { "VBUS", NPCX_ADC_CH8, ADC_MAX_VOLT * 10,
+		       ADC_READ_MAX + 1, 0 },
+	[ADC_SKU_ID1] = { "SKU1", NPCX_ADC_CH9, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+			  0 },
+	[ADC_SKU_ID2] = { "SKU2", NPCX_ADC_CH4, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+			  0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* Power signal list.  Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
-	{GPIO_PCH_SLP_S3_L,	POWER_SIGNAL_ACTIVE_HIGH, "SLP_S3_DEASSERTED"},
-	{GPIO_PCH_SLP_S5_L,	POWER_SIGNAL_ACTIVE_HIGH, "SLP_S5_DEASSERTED"},
-	{GPIO_S0_PGOOD,		POWER_SIGNAL_ACTIVE_HIGH, "S0_PGOOD"},
-	{GPIO_S5_PGOOD,		POWER_SIGNAL_ACTIVE_HIGH, "S5_PGOOD"},
+	{ GPIO_PCH_SLP_S3_L, POWER_SIGNAL_ACTIVE_HIGH, "SLP_S3_DEASSERTED" },
+	{ GPIO_PCH_SLP_S5_L, POWER_SIGNAL_ACTIVE_HIGH, "SLP_S5_DEASSERTED" },
+	{ GPIO_S0_PGOOD, POWER_SIGNAL_ACTIVE_HIGH, "S0_PGOOD" },
+	{ GPIO_S5_PGOOD, POWER_SIGNAL_ACTIVE_HIGH, "S5_PGOOD" },
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
@@ -107,7 +100,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = I2C_PORT_TCPC1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
 		},
 		.drv = &ps8xxx_tcpm_drv,
 		/* Alert is active-low, push-pull */
@@ -156,7 +149,8 @@ void board_tcpc_init(void)
 	 * HPD pulse to enable video path
 	 */
 	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		usb_mux_hpd_update(port, 0, 0);
+		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
 DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
 
@@ -197,7 +191,7 @@ static void anx74xx_cable_det_handler(void)
 	 * and if in normal mode, then there is no need to trigger a tcpc reset.
 	 */
 	if (cable_det && !reset_n)
-		task_set_event(TASK_ID_PD_C0, PD_EVENT_TCPC_RESET, 0);
+		task_set_event(TASK_ID_PD_C0, PD_EVENT_TCPC_RESET);
 }
 DECLARE_DEFERRED(anx74xx_cable_det_handler);
 
@@ -278,45 +272,48 @@ static uint32_t sku_id;
 static int ps8751_tune_mux(const struct usb_mux *me)
 {
 	/* Tune USB mux registers for treeya's port 1 Rx measurement */
-	if ((sku_id >= 0xa0) && (sku_id <= 0xaf))
+	if (((sku_id >= 0xa0) && (sku_id <= 0xaf)) || sku_id == 0xbe ||
+	    sku_id == 0xbf)
 		mux_write(me, PS8XXX_REG_MUX_USB_C2SS_EQ, 0x40);
 
 	return EC_SUCCESS;
 }
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 #ifdef VARIANT_GRUNT_TCPC_0_ANX3429
 	[USB_PD_PORT_ANX74XX] = {
-		.usb_port = USB_PD_PORT_ANX74XX,
-		.driver = &anx74xx_tcpm_usb_mux_driver,
-		.hpd_update = &anx74xx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_ANX74XX,
+			.driver = &anx74xx_tcpm_usb_mux_driver,
+			.hpd_update = &anx74xx_tcpc_update_hpd_status,
+		},
 	},
 #elif defined(VARIANT_GRUNT_TCPC_0_ANX3447)
 	[USB_PD_PORT_ANX74XX] = {
-		.usb_port = USB_PD_PORT_ANX74XX,
-		.driver = &anx7447_usb_mux_driver,
-		.hpd_update = &anx7447_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_ANX74XX,
+			.driver = &anx7447_usb_mux_driver,
+			.hpd_update = &anx7447_tcpc_update_hpd_status,
+		},
 	},
 #endif
 	[USB_PD_PORT_PS8751] = {
-		.usb_port = USB_PD_PORT_PS8751,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-		.board_init = &ps8751_tune_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_PS8751,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			.board_init = &ps8751_tune_mux,
+		},
 	}
 };
 
 struct ppc_config_t ppc_chips[] = {
-	{
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	{
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
+	{ .i2c_port = I2C_PORT_TCPC0,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
+	{ .i2c_port = I2C_PORT_TCPC1,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
 };
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
@@ -337,8 +334,8 @@ int ppc_get_alert_status(int port)
 
 void board_overcurrent_event(int port, int is_overcurrented)
 {
-	enum gpio_signal signal = (port == 0) ? GPIO_USB_C0_OC_L
-					      : GPIO_USB_C1_OC_L;
+	enum gpio_signal signal = (port == 0) ? GPIO_USB_C0_OC_L :
+						GPIO_USB_C1_OC_L;
 	/* Note that the levels are inverted because the pin is active low. */
 	int lvl = is_overcurrented ? 0 : 1;
 
@@ -370,7 +367,6 @@ const struct charger_config_t chg_chips[] = {
 	},
 };
 
-
 const int usb_port_enable[USB_PORT_COUNT] = {
 	GPIO_EN_USB_A0_5V,
 	GPIO_EN_USB_A1_5V,
@@ -392,7 +388,6 @@ static void baseboard_chipset_resume(void)
 {
 	/* Allow display backlight to turn on. See above backlight comment */
 	gpio_set_level(GPIO_ENABLE_BACKLIGHT_L, 0);
-
 }
 DECLARE_HOOK(HOOK_CHIPSET_RESUME, baseboard_chipset_resume, HOOK_PRIO_DEFAULT);
 
@@ -468,21 +463,8 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	/*
-	 * Limit the input current to 95% negotiated limit,
-	 * to account for the charger chip margin.
-	 */
-	charge_ma = charge_ma * 95 / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
-}
-
 /* Keyboard scan setting */
-struct keyboard_scan_config keyscan_config = {
+__override struct keyboard_scan_config keyscan_config = {
 	/*
 	 * F3 key scan cycle completed but scan input is not
 	 * charging to logic high when EC start scan next
@@ -512,19 +494,19 @@ struct keyboard_scan_config keyscan_config = {
  * Murata page for part NCP15WB473F03RC. Vdd=3.3V, R=30.9Kohm.
  */
 static const struct thermistor_data_pair thermistor_data[] = {
-	{ 2761 / THERMISTOR_SCALING_FACTOR, 0},
-	{ 2492 / THERMISTOR_SCALING_FACTOR, 10},
-	{ 2167 / THERMISTOR_SCALING_FACTOR, 20},
-	{ 1812 / THERMISTOR_SCALING_FACTOR, 30},
-	{ 1462 / THERMISTOR_SCALING_FACTOR, 40},
-	{ 1146 / THERMISTOR_SCALING_FACTOR, 50},
-	{ 878 / THERMISTOR_SCALING_FACTOR, 60},
-	{ 665 / THERMISTOR_SCALING_FACTOR, 70},
-	{ 500 / THERMISTOR_SCALING_FACTOR, 80},
-	{ 434 / THERMISTOR_SCALING_FACTOR, 85},
-	{ 376 / THERMISTOR_SCALING_FACTOR, 90},
-	{ 326 / THERMISTOR_SCALING_FACTOR, 95},
-	{ 283 / THERMISTOR_SCALING_FACTOR, 100}
+	{ 2761 / THERMISTOR_SCALING_FACTOR, 0 },
+	{ 2492 / THERMISTOR_SCALING_FACTOR, 10 },
+	{ 2167 / THERMISTOR_SCALING_FACTOR, 20 },
+	{ 1812 / THERMISTOR_SCALING_FACTOR, 30 },
+	{ 1462 / THERMISTOR_SCALING_FACTOR, 40 },
+	{ 1146 / THERMISTOR_SCALING_FACTOR, 50 },
+	{ 878 / THERMISTOR_SCALING_FACTOR, 60 },
+	{ 665 / THERMISTOR_SCALING_FACTOR, 70 },
+	{ 500 / THERMISTOR_SCALING_FACTOR, 80 },
+	{ 434 / THERMISTOR_SCALING_FACTOR, 85 },
+	{ 376 / THERMISTOR_SCALING_FACTOR, 90 },
+	{ 326 / THERMISTOR_SCALING_FACTOR, 95 },
+	{ 283 / THERMISTOR_SCALING_FACTOR, 100 }
 };
 
 static const struct thermistor_info thermistor_info = {
@@ -536,8 +518,8 @@ static const struct thermistor_info thermistor_info = {
 static int board_get_temp(int idx, int *temp_k)
 {
 	/* idx is the sensor index set below in temp_sensors[] */
-	int mv = adc_read_channel(
-		idx ? ADC_TEMP_SENSOR_SOC : ADC_TEMP_SENSOR_CHARGER);
+	int mv = adc_read_channel(idx ? ADC_TEMP_SENSOR_SOC :
+					ADC_TEMP_SENSOR_CHARGER);
 	int temp_c;
 
 	if (mv < 0)
@@ -549,9 +531,9 @@ static int board_get_temp(int idx, int *temp_k)
 }
 
 const struct temp_sensor_t temp_sensors[] = {
-	{"Charger", TEMP_SENSOR_TYPE_BOARD, board_get_temp, 0},
-	{"SOC", TEMP_SENSOR_TYPE_BOARD, board_get_temp, 1},
-	{"CPU", TEMP_SENSOR_TYPE_CPU, sb_tsi_get_val, 0},
+	{ "Charger", TEMP_SENSOR_TYPE_BOARD, board_get_temp, 0 },
+	{ "SOC", TEMP_SENSOR_TYPE_BOARD, board_get_temp, 1 },
+	{ "CPU", TEMP_SENSOR_TYPE_CPU, sb_tsi_get_val, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -606,7 +588,7 @@ struct motion_sensor_t motion_sensors[] = {
 	 .drv_data = &g_bmi160_data,
 	 .port = I2C_PORT_SENSOR,
 	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 2, /* g, enough for laptop */
+	 .default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
 	 .rot_standard_ref = NULL,
 	 .min_frequency = BMI_ACCEL_MIN_FREQ,
 	 .max_frequency = BMI_ACCEL_MAX_FREQ,
@@ -645,22 +627,20 @@ unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
 #endif /* HAS_TASK_MOTIONSENSE */
 
-#ifndef TEST_BUILD
-void lid_angle_peripheral_enable(int enable)
+__override void lid_angle_peripheral_enable(int enable)
 {
 	if (board_is_convertible())
 		keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
 }
-#endif
 
 static const int sku_thresh_mv[] = {
 	/* Vin = 3.3V, Ideal voltage, R2 values listed below */
 	/* R1 = 51.1 kOhm */
-	200,  /* 124 mV, 2.0 Kohm */
-	366,  /* 278 mV, 4.7 Kohm */
-	550,  /* 456 mV, 8.2  Kohm */
-	752,  /* 644 mV, 12.4 Kohm */
-	927,  /* 860 mV, 18.0 Kohm */
+	200, /* 124 mV, 2.0 Kohm */
+	366, /* 278 mV, 4.7 Kohm */
+	550, /* 456 mV, 8.2  Kohm */
+	752, /* 644 mV, 12.4 Kohm */
+	927, /* 860 mV, 18.0 Kohm */
 	1073, /* 993 mV, 22.0 Kohm */
 	1235, /* 1152 mV, 27.4 Kohm */
 	1386, /* 1318 mV, 34.0 Kohm */
@@ -707,10 +687,9 @@ static uint32_t board_get_adc_sku_id(void)
 
 static int board_get_gpio_board_version(void)
 {
-	return
-		(!!gpio_get_level(GPIO_BOARD_VERSION1) << 0) |
-		(!!gpio_get_level(GPIO_BOARD_VERSION2) << 1) |
-		(!!gpio_get_level(GPIO_BOARD_VERSION3) << 2);
+	return (!!gpio_get_level(GPIO_BOARD_VERSION1) << 0) |
+	       (!!gpio_get_level(GPIO_BOARD_VERSION2) << 1) |
+	       (!!gpio_get_level(GPIO_BOARD_VERSION3) << 2);
 }
 
 static int board_version;
@@ -724,7 +703,7 @@ static void cbi_init(void)
 	 * Use board version and SKU ID from CBI EEPROM if the board supports
 	 * it and the SKU ID set via resistors + ADC is not valid.
 	 */
-#ifdef CONFIG_CROS_BOARD_INFO
+#ifdef CONFIG_CBI_EEPROM
 	if (sku_id == 0 || sku_id == 0xff) {
 		uint32_t val;
 
@@ -748,7 +727,7 @@ static void cbi_init(void)
  */
 DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_ADC + 1);
 
-uint32_t system_get_sku_id(void)
+__override uint32_t board_get_sku_id(void)
 {
 	return sku_id;
 }
@@ -766,9 +745,10 @@ int board_is_convertible(void)
 {
 	/* Grunt: 6 */
 	/* Kasumi360: 82 */
-	/* Treeya360: a8-af */
+	/* Treeya360: a8-af, be, bf*/
 	return (sku_id == 6 || sku_id == 82 ||
-		((sku_id >= 0xa8) && (sku_id <= 0xaf)));
+		((sku_id >= 0xa8) && (sku_id <= 0xaf)) || sku_id == 0xbe ||
+		sku_id == 0xbf);
 }
 
 int board_is_lid_angle_tablet_mode(void)
@@ -782,11 +762,11 @@ __override uint32_t board_override_feature_flags0(uint32_t flags0)
 	 * Remove keyboard backlight feature for devices that don't support it.
 	 * All Treeya and Treeya360 models do not support keyboard backlight.
 	 */
-	if (sku_id == 16 || sku_id == 17 ||
-	    sku_id == 20 || sku_id == 21 ||
-	    sku_id == 32 || sku_id == 33 ||
-	    sku_id == 40 || sku_id == 41 ||
-	    ((sku_id >= 0xa0) && (sku_id <= 0xaf)))
+	if (sku_id == 16 || sku_id == 17 || sku_id == 20 || sku_id == 21 ||
+	    sku_id == 32 || sku_id == 33 || sku_id == 40 || sku_id == 41 ||
+	    sku_id == 44 || sku_id == 45 ||
+	    ((sku_id >= 0xa0) && (sku_id <= 0xaf)) || sku_id == 0xbe ||
+	    sku_id == 0xbf)
 		return (flags0 & ~EC_FEATURE_MASK_0(EC_FEATURE_PWM_KEYB));
 	else
 		return flags0;
@@ -803,4 +783,20 @@ void board_hibernate(void)
 	 */
 	ppc_vbus_source_enable(0, 0);
 	ppc_vbus_sink_enable(0, 1);
+	/*
+	 * PPC1 therefore now needs to be configured the same way as PPC0,
+	 * to mimic the previous dead-battery behavior and allow wake on AC
+	 * plug.
+	 */
+	if (!IS_ENABLED(CONFIG_HIBERNATE_PSL)) {
+		ppc_vbus_source_enable(1, 0);
+		ppc_vbus_sink_enable(1, 1);
+	}
+
+	/*
+	 * If CCD not active, set port 0 SBU_EN=0 to avoid power leakage during
+	 * hibernation (b/175674973).
+	 */
+	if (gpio_get_level(GPIO_CCD_MODE_ODL))
+		ppc_set_sbu(0, 0);
 }
diff --git a/baseboard/grunt/baseboard.h b/baseboard/grunt/baseboard.h
index 589c2454ed..30ffb885a2 100644
--- a/baseboard/grunt/baseboard.h
+++ b/baseboard/grunt/baseboard.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,19 +8,19 @@
 #ifndef __CROS_EC_BASEBOARD_H
 #define __CROS_EC_BASEBOARD_H
 
-#if (defined(VARIANT_GRUNT_TCPC_0_ANX3429) \
-	+ defined(VARIANT_GRUNT_TCPC_0_ANX3447)) != 1
+#if (defined(VARIANT_GRUNT_TCPC_0_ANX3429) + \
+     defined(VARIANT_GRUNT_TCPC_0_ANX3447)) != 1
 #error Must choose VARIANT_GRUNT_TCPC_0_ANX3429 or VARIANT_GRUNT_TCPC_0_ANX3447
 #endif
 
 /* NPCX7 config */
-#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
-#define NPCX_TACH_SEL2    0  /* No tach. */
-#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
+#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */
+#define NPCX_TACH_SEL2 0 /* No tach. */
+#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */
 
 /* Internal SPI flash on NPCX7 */
 /* Flash is 1MB but reserve half for future use. */
-#define CONFIG_FLASH_SIZE (512 * 1024)
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
 #define CONFIG_SPI_FLASH_REGS
 #define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
 
@@ -34,14 +34,13 @@
 #define CONFIG_ADC
 #define CONFIG_BACKLIGHT_LID
 #define CONFIG_BACKLIGHT_LID_ACTIVE_LOW
-#define CONFIG_BOARD_VERSION_CUSTOM
 #define CONFIG_CMD_AP_RESET_LOG
 #define CONFIG_HIBERNATE_PSL
-#define CONFIG_HOSTCMD_LPC
+#define CONFIG_HOST_INTERFACE_LPC
 #define CONFIG_HOSTCMD_SKUID
 #define CONFIG_I2C
 #define CONFIG_I2C_BUS_MAY_BE_UNPOWERED
-#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_CONTROLLER
 #define CONFIG_LOW_POWER_IDLE
 #define CONFIG_LOW_POWER_S0
 #define CONFIG_LTO
@@ -73,7 +72,10 @@
  *
  * See also b/111214767
  */
-#define CONFIG_CHARGER_INPUT_CURRENT 512
+#define CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT 512
+#define CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT 512
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 5
 #define CONFIG_CHARGER_ISL9238
 #define CONFIG_CHARGER_SENSE_RESISTOR 10
 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 20
@@ -86,7 +88,7 @@
  * ACOK from ISL9238 sometimes has a negative pulse after connecting
  * USB-C power. We want to ignore it. b/77455171
  */
-#undef  CONFIG_EXTPOWER_DEBOUNCE_MS
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
 #define CONFIG_EXTPOWER_DEBOUNCE_MS 200
 #define CONFIG_EXTPOWER_GPIO
 #define CONFIG_POWER_COMMON
@@ -102,7 +104,6 @@
  */
 #define CONFIG_BOARD_RESET_AFTER_POWER_ON
 
-#define CONFIG_KEYBOARD_BOARD_CONFIG
 #define CONFIG_KEYBOARD_COL2_INVERTED
 #define CONFIG_KEYBOARD_PROTOCOL_8042
 
@@ -140,21 +141,13 @@
 #define CONFIG_USB_PORT_POWER_DUMB
 #define USB_PORT_COUNT 2
 
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
 
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		45000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
-
-/*
- * Minimum conditions to start AP and perform swsync.  Note that when the
- * charger is connected via USB-PD analog signaling, the boot will proceed
- * regardless.
- */
-#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 3
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 45000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /*
  * Require PD negotiation to be complete when we are in a low-battery condition
@@ -167,15 +160,15 @@
 #undef CONFIG_PORT80_HISTORY_LEN
 #define CONFIG_PORT80_HISTORY_LEN 256
 
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_POWER
-#define I2C_PORT_POWER		NPCX_I2C_PORT0_0
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT1_0
-#define I2C_PORT_TCPC1		NPCX_I2C_PORT2_0
-#define I2C_PORT_THERMAL_AP	NPCX_I2C_PORT3_0
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT7_0
+#define I2C_PORT_BATTERY I2C_PORT_POWER
+#define I2C_PORT_CHARGER I2C_PORT_POWER
+#define I2C_PORT_POWER NPCX_I2C_PORT0_0
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT1_0
+#define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0
+#define I2C_PORT_THERMAL_AP NPCX_I2C_PORT3_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT7_0
 /* Accelerometer and Gyroscope are the same device. */
-#define I2C_PORT_ACCEL		I2C_PORT_SENSOR
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
 
 /* Sensors */
 #define CONFIG_MKBP_EVENT
@@ -193,13 +186,12 @@
 #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
 #endif /* VARIANT_GRUNT_NO_SENSORS */
 
-#define USB_PD_PORT_ANX74XX	0
-#define USB_PD_PORT_PS8751	1
+#define USB_PD_PORT_ANX74XX 0
+#define USB_PD_PORT_PS8751 1
 
 #ifndef __ASSEMBLER__
 
 #include "gpio_signal.h"
-#include "math_util.h"
 #include "registers.h"
 
 enum adc_channel {
@@ -233,23 +225,6 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-/*
- * Matrix to rotate accelerators into the standard reference frame.  The default
- * is the identity which is correct for the reference design.  Variations of
- * Grunt may need to change it for manufacturability.
- * For the lid:
- *  +x to the right
- *  +y up
- *  +z out of the page
- *
- * The principle axes of the body are aligned with the lid when the lid is in
- * the 180 degree position (open, flat).
- *
- * Boards within the Grunt family may need to modify this definition at
- * board_init() time.
- */
-extern mat33_fp_t grunt_base_standard_ref;
-
 /* Sensors without hardware FIFO are in forced mode */
 #define CONFIG_ACCEL_FORCE_MODE_MASK (1 << LID_ACCEL)
 
diff --git a/baseboard/grunt/build.mk b/baseboard/grunt/build.mk
index cb9d607c36..c8a02aa85d 100644
--- a/baseboard/grunt/build.mk
+++ b/baseboard/grunt/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/baseboard/grunt/usb_pd_policy.c b/baseboard/grunt/usb_pd_policy.c
index 4b28081785..9cae485bc9 100644
--- a/baseboard/grunt/usb_pd_policy.c
+++ b/baseboard/grunt/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,11 +17,11 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
-#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\
-			 PDO_FIXED_COMM_CAP)
+#define PDO_FIXED_FLAGS \
+	(PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP | PDO_FIXED_COMM_CAP)
 
 int pd_check_vconn_swap(int port)
 {
@@ -96,7 +96,7 @@ mux_state_t svdm_dp_mux_mode(int port)
 
 __override int svdm_dp_config(int port, uint32_t *payload)
 {
-	int opos = pd_alt_mode(port, TCPC_TX_SOP, USB_SID_DISPLAYPORT);
+	int opos = pd_alt_mode(port, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT);
 	int mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]);
 	int pin_mode = pd_dfp_dp_get_pin_mode(port, dp_status[port]);
 	mux_state_t mux_mode = svdm_dp_mux_mode(port);
@@ -116,13 +116,13 @@ __override int svdm_dp_config(int port, uint32_t *payload)
 	 */
 	if (mux_mode == USB_PD_MUX_DP_ENABLED)
 		usb_mux_set(port, USB_PD_MUX_NONE, USB_SWITCH_CONNECT,
-			    pd_get_polarity(port));
+			    polarity_rm_dts(pd_get_polarity(port)));
 
-	payload[0] = VDO(USB_SID_DISPLAYPORT, 1,
-			 CMD_DP_CONFIG | VDO_OPOS(opos));
-	payload[1] = VDO_DP_CFG(pin_mode,      /* pin mode */
-				1,             /* DPv1.3 signaling */
-				2);            /* UFP connected */
+	payload[0] =
+		VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_CONFIG | VDO_OPOS(opos));
+	payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */
+				1, /* DPv1.3 signaling */
+				2); /* UFP connected */
 	return 2;
 };
 
@@ -132,7 +132,7 @@ __override void svdm_dp_post_config(int port)
 	/* Connect the SBU and USB lines to the connector. */
 	ppc_set_sbu(port, 1);
 	usb_mux_set(port, svdm_dp_mux_mode(port), USB_SWITCH_CONNECT,
-		    pd_get_polarity(port));
+		    polarity_rm_dts(pd_get_polarity(port)));
 
 	dp_flags[port] |= DP_FLAGS_DP_ON;
 	if (!(dp_flags[port] & DP_FLAGS_HPD_HI_PENDING))
@@ -142,7 +142,8 @@ __override void svdm_dp_post_config(int port)
 
 	/* set the minimum time delay (2ms) for the next HPD IRQ */
 	svdm_hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
-	usb_mux_hpd_update(port, 1, 0);
+	usb_mux_hpd_update(port,
+			   USB_PD_MUX_HPD_LVL | USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
 
 #endif /* CONFIG_USB_PD_ALT_MODE_DFP */
diff --git a/baseboard/guybrush/base_fw_config.h b/baseboard/guybrush/base_fw_config.h
new file mode 100644
index 0000000000..a9504a6b45
--- /dev/null
+++ b/baseboard/guybrush/base_fw_config.h
@@ -0,0 +1,51 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _GUYBRUSH_BASE_FW_CONFIG__H_
+#define _GUYBRUSH_BASE_FW_CONFIG__H_
+
+#define UNINITIALIZED_FW_CONFIG 0xFFFFFFFF
+
+#include <stdbool.h>
+#include <stdint.h>
+
+/*
+ * Takes a bit offset and bit width and returns the fw_config field at that
+ * offset and width. Returns -1 if an error occurs.
+ */
+int get_fw_config_field(uint8_t offset, uint8_t width);
+
+/*
+ * Each Guybrush board variant will define a board specific fw_config schema.
+ * Below is the schema agnostic interface for fw_config fields.
+ * Fields that are not applicable outside a specific Guybrush variant do not
+ * need to be included here.
+ */
+
+enum board_usb_a1_retimer {
+	USB_A1_RETIMER_UNKNOWN,
+	USB_A1_RETIMER_PS8811,
+	USB_A1_RETIMER_ANX7491
+};
+
+enum board_usb_c1_mux {
+	USB_C1_MUX_UNKNOWN,
+	USB_C1_MUX_PS8818,
+	USB_C1_MUX_ANX7451
+};
+
+enum board_form_factor {
+	FORM_FACTOR_UNKNOWN,
+	FORM_FACTOR_CLAMSHELL,
+	FORM_FACTOR_CONVERTIBLE
+};
+
+bool board_has_kblight(void);
+enum board_usb_a1_retimer board_get_usb_a1_retimer(void);
+enum board_usb_c1_mux board_get_usb_c1_mux(void);
+enum board_form_factor board_get_form_factor(void);
+bool board_is_convertible(void);
+
+#endif /* _GUYBRUSH_BASE_FW_CONFIG__H_ */
diff --git a/baseboard/guybrush/base_gpio.inc b/baseboard/guybrush/base_gpio.inc
new file mode 100644
index 0000000000..82b042f890
--- /dev/null
+++ b/baseboard/guybrush/base_gpio.inc
@@ -0,0 +1,148 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* GSC Signals */
+GPIO_INT(EC_WP_L,		PIN(5, 0), GPIO_INT_BOTH,			switch_interrupt)	/* Write Protect Enabled */
+GPIO(CCD_MODE_ODL,		PIN(C, 6), GPIO_ODR_HIGH)						/* Case Closed Debug Mode */
+GPIO(EC_GSC_PACKET_MODE,	PIN(B, 1), GPIO_OUT_LOW)						/* GSC Packet Mode */
+ALTERNATE(			PIN_MASK(6, BIT(4) | BIT(5)), 0,		MODULE_UART, 0) 	/* UART_EC_TX_GSC_DBG_RX_R, UART_GSC_DBG_TX_EC_RX_R */
+
+/* Power Signals */
+GPIO_INT(MECH_PWR_BTN_ODL,	PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW, 	power_button_interrupt)	/* Mechanical Power Button */
+GPIO_INT(EC_PWR_BTN_ODL,	PIN(0, 1), GPIO_INT_BOTH, 			power_button_interrupt) /* Power Button */
+GPIO_INT(SLP_S3_L,		PIN(6, 1), GPIO_INT_BOTH,			baseboard_en_pwr_s0)	/* Sleep S3 */
+GPIO_INT(SLP_S5_L,		PIN(7, 2), GPIO_INT_BOTH,			power_signal_interrupt) /* Sleep S5 */
+GPIO_INT(SLP_S3_S0I3_L,		PIN(7, 4), GPIO_INT_BOTH,			power_signal_interrupt) /* Sleep S0ix */
+GPIO_INT(PG_PWR_S5,		PIN(C, 0), GPIO_INT_BOTH,			baseboard_en_pwr_s0)	/* S5 Power OK */
+GPIO_INT(PG_PCORE_S0_R_OD,	PIN(B, 6), GPIO_INT_BOTH, 			power_signal_interrupt) /* S0 Power OK */
+GPIO_INT(ACOK_OD,		PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	extpower_interrupt)	/* AC Power Present */
+GPIO_INT(EC_PCORE_INT_ODL,	PIN(F, 0), GPIO_INT_BOTH | GPIO_PULL_UP,	power_signal_interrupt)	/* Power Core Interrupt */
+GPIO_INT(PG_GROUPC_S0_OD,	PIN(A, 3), GPIO_INT_BOTH, 			baseboard_en_pwr_pcore_signal)	/* Power Group C S0 */
+GPIO_INT(PG_LPDDR4X_S3_OD,	PIN(9, 5), GPIO_INT_BOTH, 			baseboard_en_pwr_pcore_signal)	/* Power Group LPDDR4 S3 */
+GPIO(EN_PWR_S5,			PIN(B, 7), GPIO_OUT_LOW)						/* Enable S5 Power */
+GPIO(EN_PWR_S0_R,		PIN(F, 1), GPIO_OUT_LOW)
+GPIO(EN_PWR_PCORE_S0_R,		PIN(E, 1), GPIO_OUT_LOW)
+ALTERNATE(/*MECH_PWR_BTN_ODL*/	PIN_MASK(D, BIT(2)), 0,				MODULE_PMU, 0)		/* PSL - Mechanical Power Button */
+ALTERNATE(/*LID_OPEN*/		PIN_MASK(0, BIT(2)), 0, 			MODULE_PMU, 0)		/* PSL - Lid Open */
+ALTERNATE(/*ACOK_OD*/		PIN_MASK(0, BIT(0)), 0,				MODULE_PMU, 0)		/* PSL - AC Power Present */
+
+/* SOC Signals */
+GPIO(EC_ENTERING_RW,		PIN(6, 6), GPIO_OUT_LOW) 						/* Tell SOC we entered RW */
+GPIO(EC_SYS_RST_L,		PIN(7, 6), GPIO_ODR_HIGH)						/* Cold Reset SOC */
+GPIO(EC_SOC_RSMRST_L,		PIN(C, 5), GPIO_OUT_LOW)						/* Resume Reset SOC */
+GPIO(EC_CLR_CMOS,		PIN(A, 1), GPIO_OUT_LOW)						/* Clear SOC CMOS */
+GPIO(EC_MEM_EVENT,		PIN(A, 5), GPIO_OUT_LOW)						/* Memory Thermal Event to SOC*/
+GPIO(EC_SOC_PWR_BTN_L,		PIN(6, 3), GPIO_OUT_HIGH)						/* Power Button to SOC */
+GPIO(EC_SOC_PWR_GOOD,		PIN(D, 3), GPIO_OUT_LOW)						/* Power Good to SOC */
+GPIO(EC_SOC_WAKE_L,		PIN(0, 3), GPIO_OUT_HIGH)						/* Wake SOC */
+GPIO(EC_SOC_INT_L,		PIN(8, 3), GPIO_OUT_HIGH)						/* Matrix Keyboard Protocol Event to SOC */
+GPIO(PROCHOT_ODL,		PIN(D, 5), GPIO_ODR_HIGH)						/* Force SOC into HTC-active state */
+GPIO(SOC_ALERT_EC_L,		PIN(E, 2), GPIO_INPUT)							/* Sideband-Temperature Iterrupt */
+GPIO(SOC_THERMTRIP_ODL, 	PIN(E, 5), GPIO_INPUT)							/* Temperature Trip Sensor */
+
+/* USB Signals */
+GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(E, 0), GPIO_INT_FALLING,			tcpc_alert_event)
+GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(C, 7), GPIO_INT_FALLING,			tcpc_alert_event)
+GPIO_INT(USB_C0_PPC_INT_ODL,	PIN(7, 5), GPIO_INT_FALLING,			ppc_interrupt)
+GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(D, 4), GPIO_INT_FALLING,			ppc_interrupt)
+GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(A, 4), GPIO_INT_FALLING | GPIO_PULL_UP,	bc12_interrupt)
+GPIO_INT(USB_C1_BC12_INT_ODL, 	PIN(9, 6), GPIO_INT_FALLING | GPIO_PULL_UP,	bc12_interrupt)
+GPIO(USB_C0_C1_FAULT_ODL,	PIN(7, 3), GPIO_ODR_HIGH)						/* C0/C1 Fault to SOC */
+GPIO(USB_C0_TCPC_RST_L,		PIN(3, 4), GPIO_OUT_HIGH)						/* C0 TCPC Reset */
+GPIO(USB_C1_TCPC_RST_L,		PIN(3, 7), GPIO_OUT_HIGH)						/* C1 TCPC Reset */
+GPIO(USB_C0_HPD,		PIN(F, 5), GPIO_OUT_LOW)						/* C0 DP Hotplug Detect */
+GPIO(USB_C1_HPD,		PIN(F, 4), GPIO_OUT_LOW)						/* C1 DP Hotplug Detect */
+
+/* Sensor Signals */
+GPIO(3AXIS_INT_L,		PIN(A, 2), GPIO_INPUT | GPIO_PULL_DOWN)					/* 3 Axis Accel */
+GPIO_INT(LID_OPEN,		PIN(0, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	lid_interrupt)		/* Lid Open */
+GPIO_INT(VOLDN_BTN_ODL,		PIN(A, 7), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)	/* Volume Down */
+GPIO_INT(VOLUP_BTN_ODL,		PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, 	button_interrupt)	/* Volume Up */
+GPIO(EC_BATT_PRES_ODL,		PIN(9, 4), GPIO_INPUT)							/* Battery Present */
+ALTERNATE(/*TEMP_SOC|CHRG|MEM*/	PIN_MASK(4, BIT(3) | BIT(4) | BIT(5)), 0, 	MODULE_ADC, 0)		/* SOC, Charger and Memory Temperature */
+ALTERNATE(			PIN_MASK(4, BIT(1) | BIT(2)), 0,		MODULE_ADC, 0)		/* EC_ADC_CORE_IMON1, EC_ADC_SOC_IMON2 */
+
+/* LED Signals */
+GPIO(EC_DISABLE_DISP_BL,	PIN(A, 6), GPIO_OUT_HIGH)						/* Disable Display Backlight */
+
+/* Fan Signals */
+ALTERNATE(			PIN_MASK(C, BIT(3)), 0, 			MODULE_PWM, 0)		/* EC_FAN_PWM - Fan PWM */
+ALTERNATE(			PIN_MASK(4, BIT(0)), 0, 			MODULE_PWM, 0)		/* EC_FAN_SPEED - Fan Speed */
+
+/* I2C Signals -- i2c pins need to be exposed as GPIO for bit banging, even though set to alternate mode below */
+GPIO(EC_I2C_USB_A0_C0_SCL,	PIN(B, 5), GPIO_INPUT)
+GPIO(EC_I2C_USB_A0_C0_SDA,	PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_A1_C1_SCL,	PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_A1_C1_SDA,	PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_BATT_SCL,		PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_BATT_SDA,		PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_USBC_MUX_SCL,	PIN(D, 1), GPIO_INPUT)
+GPIO(EC_I2C_USBC_MUX_SDA,	PIN(D, 0), GPIO_INPUT)
+GPIO(EC_I2C_POWER_SCL,		PIN(F, 3), GPIO_INPUT)
+GPIO(EC_I2C_POWER_SDA,		PIN(F, 2), GPIO_INPUT)
+GPIO(EC_I2C_CBI_SCL,		PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_CBI_SDA,		PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,		PIN(E, 4), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SENSOR_SDA,		PIN(E, 3), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SOC_SIC,		PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_SOC_SID,		PIN(B, 2), GPIO_INPUT)
+
+ALTERNATE(			PIN_MASK(B, BIT(4) | BIT(5)), 0, 		MODULE_I2C, 0)		/* I2C0 */
+ALTERNATE(			PIN_MASK(9, BIT(0) | BIT(1) | BIT(2)), 0, 	MODULE_I2C, 0)		/* I2C1 SCL / I2C2 */
+ALTERNATE(			PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)					/* I2C1 SDA */
+ALTERNATE(			PIN_MASK(D, BIT(0) | BIT(1)), 0, 		MODULE_I2C, 0)		/* I2C3 */
+ALTERNATE(			PIN_MASK(F, BIT(2) | BIT(3)), 0, 		MODULE_I2C, 0)		/* I2C4 */
+ALTERNATE(			PIN_MASK(3, BIT(3) | BIT(6)), 0, 		MODULE_I2C, 0)		/* I2C5 */
+ALTERNATE(			PIN_MASK(E, BIT(3) | BIT(4)), 0, 		MODULE_I2C, 0)		/* I2C6 */
+ALTERNATE(			PIN_MASK(B, BIT(2) | BIT(3)), 0, 		MODULE_I2C, 0)		/* I2C7 */
+
+/* Keyboard Signals */
+GPIO(EN_KB_BL, 			PIN(9, 7), GPIO_OUT_HIGH)						/* Enable Keyboard Backlight */
+ALTERNATE(/*PWM_KB_BL*/ 	PIN_MASK(C, BIT(2)), 0, 			MODULE_PWM, 0)		/* Keyboard Backlight Level */
+ALTERNATE(/*KSI_00-01*/		PIN_MASK(3, BIT(0) | BIT(1)), 0, 		MODULE_KEYBOARD_SCAN, GPIO_INPUT)
+ALTERNATE(/*KSI_02-07*/		PIN_MASK(2, GENMASK(7, 2)), 0, 			MODULE_KEYBOARD_SCAN, GPIO_INPUT)
+ALTERNATE(/*KSO_00-01*/		PIN_MASK(2, BIT(0) | BIT(1)), 0, 		MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)
+GPIO(EC_KSO_02_INV, 		PIN(1, 7), GPIO_OUT_LOW)						/* KSO_02 inverted */
+ALTERNATE(/*KSO_03-09*/		PIN_MASK(1, GENMASK(6, 0)), 0,			MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)
+ALTERNATE(/*KSO_10-13*/		PIN_MASK(0, GENMASK(7, 4)), 0, 			MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)
+ALTERNATE(/*KSO_14*/		PIN_MASK(8, BIT(2)), 0, 			MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)
+
+#if 0
+/*
+ * SOC eSPI Bus
+ * These signals do not need to be explicitly configured.
+ * Leaving here so all signals are documented.
+ */
+GPIO(ESPI_SOC_CLK,		PIN(5, 5), GPIO_DEFAULT)
+GPIO(ESPI_SOC_CS_EC_L,		PIN(5, 3), GPIO_DEFAULT)
+GPIO(ESPI_SOC_D0_EC,		PIN(4, 6), GPIO_DEFAULT)
+GPIO(ESPI_SOC_D1_EC,		PIN(4, 7), GPIO_DEFAULT)
+GPIO(ESPI_SOC_D2_EC,		PIN(5, 1), GPIO_DEFAULT)
+GPIO(ESPI_SOC_D3_EC,		PIN(5, 2), GPIO_DEFAULT)
+GPIO(EC_ESPI_RST_L,		PIN(5, 4), GPIO_DEFAULT)
+GPIO(ESPI_EC_ALERT_SOC_L,	PIN(5, 7), GPIO_DEFAULT)
+#endif
+
+/* TCPC C0 */
+IOEX(USB_C0_TCPC_FASTSW_CTL_EN, EXPIN(USBC_PORT_C0, 0, 4), GPIO_OUT_LOW)
+IOEX(USB_C0_PPC_EN_L,		EXPIN(USBC_PORT_C0, 1, 0), GPIO_OUT_LOW)
+IOEX(USB_C0_PPC_ILIM_3A_EN,	EXPIN(USBC_PORT_C0, 1, 1), GPIO_OUT_LOW)
+IOEX_INT(USB_C0_SBU_FAULT_ODL,	EXPIN(USBC_PORT_C0, 1, 2), GPIO_INT_FALLING,	sbu_fault_interrupt)
+IOEX(EN_PP5000_USB_A0_VBUS,	EXPIN(USBC_PORT_C0, 1, 5), GPIO_OUT_LOW)
+IOEX(USB_A0_LIMIT_SDP,		EXPIN(USBC_PORT_C0, 1, 6), GPIO_OUT_LOW)
+IOEX(USB_C0_SBU_FLIP,		EXPIN(USBC_PORT_C0, 1, 7), GPIO_OUT_LOW)
+
+/* TCPC C1 */
+IOEX(USB_A1_RETIMER_EN,		EXPIN(USBC_PORT_C1, 0, 0), GPIO_OUT_LOW)
+IOEX(USB_A1_RETIMER_RST,	EXPIN(USBC_PORT_C1, 0, 1), GPIO_OUT_LOW)
+IOEX(USB_C1_IN_HPD,		EXPIN(USBC_PORT_C1, 0, 3), GPIO_OUT_LOW)
+IOEX(USB_C1_TCPC_FASTSW_CTL_EN, EXPIN(USBC_PORT_C1, 0, 4), GPIO_OUT_LOW)
+IOEX(USB_C1_PPC_EN_L,		EXPIN(USBC_PORT_C1, 1, 0), GPIO_OUT_LOW)
+IOEX(USB_C1_PPC_ILIM_3A_EN,	EXPIN(USBC_PORT_C1, 1, 1), GPIO_OUT_LOW)
+IOEX_INT(USB_C1_SBU_FAULT_ODL,	EXPIN(USBC_PORT_C1, 1, 2), GPIO_INT_FALLING,	sbu_fault_interrupt)
+IOEX(EN_PP5000_USB_A1_VBUS_DB,	EXPIN(USBC_PORT_C1, 1, 5), GPIO_OUT_LOW)
+IOEX(USB_A1_LIMIT_SDP_DB,	EXPIN(USBC_PORT_C1, 1, 6), GPIO_OUT_LOW)
diff --git a/baseboard/guybrush/baseboard.c b/baseboard/guybrush/baseboard.c
new file mode 100644
index 0000000000..b65aa5ba8b
--- /dev/null
+++ b/baseboard/guybrush/baseboard.c
@@ -0,0 +1,1031 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Guybrush family-specific configuration */
+
+#include "base_fw_config.h"
+#include "battery_fuel_gauge.h"
+#include "charge_manager.h"
+#include "charge_ramp.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "chip/npcx/ps2_chip.h"
+#include "chip/npcx/pwm_chip.h"
+#include "chipset.h"
+#include "cros_board_info.h"
+#include "driver/ppc/aoz1380_public.h"
+#include "driver/ppc/nx20p348x.h"
+#include "driver/retimer/anx7491.h"
+#include "driver/retimer/ps8811.h"
+#include "driver/retimer/ps8818_public.h"
+#include "driver/tcpm/nct38xx.h"
+#include "driver/usb_mux/amd_fp6.h"
+#include "driver/usb_mux/anx7451.h"
+#include "fan.h"
+#include "fan_chip.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "ioexpander.h"
+#include "isl9241.h"
+#include "keyboard_scan.h"
+#include "nct38xx.h"
+#include "pi3usb9201.h"
+#include "power.h"
+#include "pwm.h"
+#include "usb_mux.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_ppc.h"
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+#define CPRINTSCHIP(format, args...) cprints(CC_CHIPSET, format##args)
+
+static void reset_nct38xx_port(int port);
+
+/* Wake Sources */
+const enum gpio_signal hibernate_wake_pins[] = {
+	GPIO_LID_OPEN,
+	GPIO_AC_PRESENT,
+	GPIO_POWER_BUTTON_L,
+};
+const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
+
+/* Power Signal Input List */
+const struct power_signal_info power_signal_list[] = {
+	[X86_SLP_S0_N] = {
+		.gpio = GPIO_PCH_SLP_S0_L,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "SLP_S0_DEASSERTED",
+	},
+	[X86_SLP_S3_N] = {
+		.gpio = GPIO_PCH_SLP_S3_L,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "SLP_S3_DEASSERTED",
+	},
+	[X86_SLP_S5_N] = {
+		.gpio = GPIO_PCH_SLP_S5_L,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "SLP_S5_DEASSERTED",
+	},
+	[X86_S0_PGOOD] = {
+		.gpio = GPIO_S0_PGOOD,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "S0_PGOOD",
+	},
+	[X86_S5_PGOOD] = {
+		.gpio = GPIO_S5_PGOOD,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "S5_PGOOD",
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
+
+const struct i2c_port_t i2c_ports[] = {
+	{
+		.name = "tcpc0",
+		.port = I2C_PORT_TCPC0,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_USB_A0_C0_SCL,
+		.sda = GPIO_EC_I2C_USB_A0_C0_SDA,
+	},
+	{
+		.name = "tcpc1",
+		.port = I2C_PORT_TCPC1,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_USB_A1_C1_SCL,
+		.sda = GPIO_EC_I2C_USB_A1_C1_SDA,
+	},
+	{
+		.name = "battery",
+		.port = I2C_PORT_BATTERY,
+		.kbps = 100,
+		.scl = GPIO_EC_I2C_BATT_SCL,
+		.sda = GPIO_EC_I2C_BATT_SDA,
+	},
+	{
+		.name = "usb_mux",
+		.port = I2C_PORT_USB_MUX,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_USBC_MUX_SCL,
+		.sda = GPIO_EC_I2C_USBC_MUX_SDA,
+	},
+	{
+		.name = "charger",
+		.port = I2C_PORT_CHARGER,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_POWER_SCL,
+		.sda = GPIO_EC_I2C_POWER_SDA,
+	},
+	{
+		.name = "eeprom",
+		.port = I2C_PORT_EEPROM,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_CBI_SCL,
+		.sda = GPIO_EC_I2C_CBI_SDA,
+	},
+	{
+		.name = "sensor",
+		.port = I2C_PORT_SENSOR,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_SENSOR_SCL,
+		.sda = GPIO_EC_I2C_SENSOR_SDA,
+	},
+	{
+		.name = "soc_thermal",
+		.port = I2C_PORT_THERMAL_AP,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_SOC_SIC,
+		.sda = GPIO_EC_I2C_SOC_SID,
+	},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = ISL9241_ADDR_FLAGS,
+		.drv = &isl9241_drv,
+	},
+};
+
+const struct tcpc_config_t tcpc_config[] = {
+	[USBC_PORT_C0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TCPC0,
+			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+	},
+	[USBC_PORT_C1] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TCPC1,
+			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
+BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
+
+const int usb_port_enable[USBA_PORT_COUNT] = {
+	IOEX_EN_PP5000_USB_A0_VBUS,
+	IOEX_EN_PP5000_USB_A1_VBUS_DB,
+};
+
+static void baseboard_interrupt_init(void)
+{
+	/* Enable Power Group interrupts. */
+	gpio_enable_interrupt(GPIO_PG_GROUPC_S0_OD);
+	gpio_enable_interrupt(GPIO_PG_LPDDR4X_S3_OD);
+
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
+
+	/* Enable BC 1.2 interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
+
+	/* Enable SBU fault interrupts */
+	ioex_enable_interrupt(IOEX_USB_C0_SBU_FAULT_ODL);
+	ioex_enable_interrupt(IOEX_USB_C1_SBU_FAULT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, baseboard_interrupt_init, HOOK_PRIO_INIT_I2C + 1);
+
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C0] = {
+		/* Device does not talk I2C */
+		.drv = &aoz1380_drv
+	},
+
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_TCPC1,
+		.i2c_addr_flags = NX20P3483_ADDR1_FLAGS,
+		.drv = &nx20p348x_drv
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_TCPC0,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_TCPC1,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
+
+static int fsusb42umx_set_mux(const struct usb_mux *, mux_state_t);
+
+__overridable int board_c1_ps8818_mux_set(const struct usb_mux *me,
+					  mux_state_t mux_state)
+{
+	CPRINTSUSB("C1: PS8818 mux using default tuning");
+	return 0;
+}
+
+const struct usb_mux usbc1_ps8818 = {
+	.usb_port = USBC_PORT_C1,
+	.i2c_port = I2C_PORT_TCPC1,
+	.flags = USB_MUX_FLAG_RESETS_IN_G3,
+	.i2c_addr_flags = PS8818_I2C_ADDR0_FLAGS,
+	.driver = &ps8818_usb_retimer_driver,
+	.board_set = &board_c1_ps8818_mux_set,
+};
+
+__overridable int board_c1_anx7451_mux_set(const struct usb_mux *me,
+					   mux_state_t mux_state)
+{
+	CPRINTSUSB("C1: ANX7451 mux using default tuning");
+	return 0;
+}
+
+const struct usb_mux usbc1_anx7451 = {
+	.usb_port = USBC_PORT_C1,
+	.i2c_port = I2C_PORT_TCPC1,
+	.flags = USB_MUX_FLAG_RESETS_IN_G3,
+	.i2c_addr_flags = ANX7491_I2C_ADDR3_FLAGS,
+	.driver = &anx7451_usb_mux_driver,
+	.board_set = &board_c1_anx7451_mux_set,
+};
+
+/* Filled in by setup_mux based on fw_config */
+struct usb_mux_chain usbc1_mux1;
+
+struct usb_mux_chain usb_muxes[] = {
+	[USBC_PORT_C0] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.i2c_port = I2C_PORT_USB_MUX,
+			.i2c_addr_flags = AMD_FP6_C0_MUX_I2C_ADDR,
+			.driver = &amd_fp6_usb_mux_driver,
+			.board_set = &fsusb42umx_set_mux,
+		},
+	},
+	[USBC_PORT_C1] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.i2c_port = I2C_PORT_USB_MUX,
+			.i2c_addr_flags = AMD_FP6_C4_MUX_I2C_ADDR,
+			.driver = &amd_fp6_usb_mux_driver,
+		},
+		.next = &usbc1_mux1,
+	}
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
+
+struct ioexpander_config_t ioex_config[] = {
+	[USBC_PORT_C0] = {
+		.i2c_host_port = I2C_PORT_TCPC0,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_host_port = I2C_PORT_TCPC1,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ioex_config) == USBC_PORT_COUNT);
+BUILD_ASSERT(CONFIG_IO_EXPANDER_PORT_COUNT == USBC_PORT_COUNT);
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/*
+	 * F3 key scan cycle completed but scan input is not
+	 * charging to logic high when EC start scan next
+	 * column for "T" key, so we set .output_settle_us
+	 * to 80us
+	 */
+	.output_settle_us = 80,
+	.debounce_down_us = 6 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 1500,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = SECOND,
+	.actual_key_mask = {
+		0x3c, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
+		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
+	},
+};
+
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_FAN] = {
+		.channel = 0,
+		.flags = PWM_CONFIG_OPEN_DRAIN,
+		.freq = 25000,
+	},
+	[PWM_CH_KBLIGHT] = {
+		.channel = 1,
+		.flags = PWM_CONFIG_DSLEEP,
+		.freq = 100,
+	},
+	[PWM_CH_LED_CHRG] = {
+		.channel = 2,
+		.flags = PWM_CONFIG_DSLEEP,
+		.freq = 100,
+	},
+	[PWM_CH_LED_FULL] = {
+		.channel = 3,
+		.flags = PWM_CONFIG_DSLEEP,
+		.freq = 100,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+const struct mft_t mft_channels[] = {
+	[MFT_CH_0] = {
+		.module = NPCX_MFT_MODULE_1,
+		.clk_src = TCKC_LFCLK,
+		.pwm_id = PWM_CH_FAN,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
+
+/*
+ * USB C0 port SBU mux use standalone FSUSB42UMX
+ * chip and it needs a board specific driver.
+ * It is called through the C0 mux's board_set.
+ */
+static int fsusb42umx_set_mux(const struct usb_mux *me, mux_state_t mux_state)
+{
+	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
+		ioex_set_level(IOEX_USB_C0_SBU_FLIP, 1);
+	else
+		ioex_set_level(IOEX_USB_C0_SBU_FLIP, 0);
+
+	return EC_SUCCESS;
+}
+
+static void setup_mux(void)
+{
+	switch (board_get_usb_c1_mux()) {
+	case USB_C1_MUX_PS8818:
+		CPRINTSUSB("C1: Setting PS8818 mux");
+		usbc1_mux1.mux = &usbc1_ps8818;
+		break;
+	case USB_C1_MUX_ANX7451:
+		CPRINTSUSB("C1: Setting ANX7451 mux");
+		usbc1_mux1.mux = &usbc1_anx7451;
+		break;
+	default:
+		CPRINTSUSB("C1: Mux is unknown");
+		usb_muxes[USBC_PORT_C1].next = NULL;
+	}
+}
+DECLARE_HOOK(HOOK_INIT, setup_mux, HOOK_PRIO_INIT_I2C);
+
+int board_set_active_charge_port(int port)
+{
+	int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int i;
+	int rv;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTSUSB("Disabling all charger ports");
+
+		/* Disable all ports. */
+		for (i = 0; i < ppc_cnt; i++) {
+			/*
+			 * If this port had booted in dead battery mode, go
+			 * ahead and reset it so EN_SNK responds properly.
+			 */
+			if (nct38xx_get_boot_type(i) ==
+			    NCT38XX_BOOT_DEAD_BATTERY) {
+				reset_nct38xx_port(i);
+				pd_set_error_recovery(i);
+			}
+
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (ppc_vbus_sink_enable(i, 0))
+				CPRINTSUSB("Disabling C%d as sink failed.", i);
+		}
+
+		return EC_SUCCESS;
+	} else if (!is_valid_port) {
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * Check if we can reset any ports in dead battery mode
+	 *
+	 * The NCT3807 may continue to keep EN_SNK low on the dead battery port
+	 * and allow a dangerous level of voltage to pass through to the initial
+	 * charge port (see b/183660105).  We must reset the ports if we have
+	 * sufficient battery to do so, which will bring EN_SNK back under
+	 * normal control.
+	 */
+	rv = EC_SUCCESS;
+	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+		if (nct38xx_get_boot_type(i) == NCT38XX_BOOT_DEAD_BATTERY) {
+			CPRINTSUSB("Found dead battery on %d", i);
+			/*
+			 * If we have battery, get this port reset ASAP.
+			 * This means temporarily rejecting charge manager
+			 * sets to it.
+			 */
+			if (pd_is_battery_capable()) {
+				reset_nct38xx_port(i);
+				pd_set_error_recovery(i);
+
+				if (port == i)
+					rv = EC_ERROR_INVAL;
+			} else if (port != i) {
+				/*
+				 * If other port is selected and in dead battery
+				 * mode, reset this port.  Otherwise, reject
+				 * change because we'll brown out.
+				 */
+				if (nct38xx_get_boot_type(port) ==
+				    NCT38XX_BOOT_DEAD_BATTERY) {
+					reset_nct38xx_port(i);
+					pd_set_error_recovery(i);
+				} else {
+					rv = EC_ERROR_INVAL;
+				}
+			}
+		}
+	}
+
+	if (rv != EC_SUCCESS)
+		return rv;
+
+	/* Check if the port is sourcing VBUS. */
+	if (tcpm_get_src_ctrl(port)) {
+		CPRINTSUSB("Skip enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTSUSB("New charge port: C%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < ppc_cnt; i++) {
+		if (i == port)
+			continue;
+
+		if (ppc_vbus_sink_enable(i, 0))
+			CPRINTSUSB("C%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTSUSB("C%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+int board_is_i2c_port_powered(int port)
+{
+	switch (port) {
+	case I2C_PORT_USB_MUX:
+	case I2C_PORT_SENSOR:
+		/* USB mux and sensor i2c bus is unpowered in Z1 */
+		return chipset_in_state(CHIPSET_STATE_HARD_OFF) ? 0 : 1;
+	case I2C_PORT_THERMAL_AP:
+		/* SOC thermal i2c bus is unpowered in S0i3/S3/S5/Z1 */
+		return chipset_in_state(CHIPSET_STATE_ANY_OFF |
+					CHIPSET_STATE_ANY_SUSPEND) ?
+			       0 :
+			       1;
+	default:
+		return 1;
+	}
+}
+
+/*
+ * In the AOZ1380 PPC, there are no programmable features.  We use
+ * the attached NCT3807 to control a GPIO to indicate 1A5 or 3A0
+ * current limits.
+ */
+int board_aoz1380_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	int rv;
+
+	/* Use the TCPC to set the current limit */
+	rv = ioex_set_level(IOEX_USB_C0_PPC_ILIM_3A_EN,
+			    (rp == TYPEC_RP_3A0) ? 1 : 0);
+
+	return rv;
+}
+
+void sbu_fault_interrupt(enum ioex_signal signal)
+{
+	int port = (signal == IOEX_USB_C0_SBU_FAULT_ODL) ? 0 : 1;
+
+	CPRINTSUSB("C%d: SBU fault", port);
+	pd_handle_overcurrent(port);
+}
+
+static void set_ac_prochot(void)
+{
+	isl9241_set_ac_prochot(CHARGER_SOLO, GUYBRUSH_AC_PROCHOT_CURRENT_MA);
+}
+DECLARE_HOOK(HOOK_INIT, set_ac_prochot, HOOK_PRIO_DEFAULT);
+
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	int port;
+
+	switch (signal) {
+	case GPIO_USB_C0_TCPC_INT_ODL:
+		port = 0;
+		break;
+	case GPIO_USB_C1_TCPC_INT_ODL:
+		port = 1;
+		break;
+	default:
+		return;
+	}
+
+	schedule_deferred_pd_interrupt(port);
+}
+
+static void reset_nct38xx_port(int port)
+{
+	int rv;
+	int saved_state[IOEX_COUNT] = { 0 };
+	enum gpio_signal reset_gpio_l = (port == USBC_PORT_C0) ?
+						GPIO_USB_C0_TCPC_RST_L :
+						GPIO_USB_C1_TCPC_RST_L;
+
+	if (port < 0 || port >= USBC_PORT_COUNT) {
+		CPRINTSUSB("%s invalid port %d", __func__, port);
+		return;
+	}
+
+	/* Save ioexpander GPIO state */
+	rv = ioex_save_gpio_state(port, saved_state, ARRAY_SIZE(saved_state));
+	if (rv) {
+		CPRINTSUSB("%s failed to save ioex state rv=%d", __func__, rv);
+		return;
+	}
+
+	gpio_set_level(reset_gpio_l, 0);
+	msleep(NCT38XX_RESET_HOLD_DELAY_MS);
+	gpio_set_level(reset_gpio_l, 1);
+	nct38xx_reset_notify(port);
+	if (NCT3807_RESET_POST_DELAY_MS != 0)
+		msleep(NCT3807_RESET_POST_DELAY_MS);
+
+	/* Re-init ioex after resetting the TCPC */
+	ioex_init(port);
+	/* Restore ioexpander GPIO state */
+	rv = ioex_restore_gpio_state(port, saved_state,
+				     ARRAY_SIZE(saved_state));
+	if (rv) {
+		CPRINTSUSB("%s failed to restore ioex state rv=%d", __func__,
+			   rv);
+		return;
+	}
+}
+
+void board_reset_pd_mcu(void)
+{
+	/* Reset TCPC0 */
+	reset_nct38xx_port(USBC_PORT_C0);
+
+	/* Reset TCPC1 */
+	reset_nct38xx_port(USBC_PORT_C1);
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	/*
+	 * Check which port has the ALERT line set and ignore if that TCPC has
+	 * its reset line active.
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL)) {
+		if (gpio_get_level(GPIO_USB_C0_TCPC_RST_L) != 0)
+			status |= PD_STATUS_TCPC_ALERT_0;
+	}
+
+	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL)) {
+		if (gpio_get_level(GPIO_USB_C1_TCPC_RST_L) != 0)
+			status |= PD_STATUS_TCPC_ALERT_1;
+	}
+
+	return status;
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		aoz1380_interrupt(USBC_PORT_C0);
+		break;
+
+	case GPIO_USB_C1_PPC_INT_ODL:
+		nx20p348x_interrupt(USBC_PORT_C1);
+		break;
+
+	default:
+		break;
+	}
+}
+
+void bc12_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_BC12_INT_ODL:
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+		break;
+
+	case GPIO_USB_C1_BC12_INT_ODL:
+		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+		break;
+
+	default:
+		break;
+	}
+}
+
+/**
+ * Return if VBUS is sagging too low
+ */
+int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
+{
+	int voltage = 0;
+	int rv;
+
+	rv = charger_get_vbus_voltage(port, &voltage);
+
+	if (rv) {
+		CPRINTSUSB("%s rv=%d", __func__, rv);
+		return 0;
+	}
+
+	/*
+	 * b/168569046: The ISL9241 sometimes incorrectly reports 0 for unknown
+	 * reason, causing ramp to stop at 0.5A. Workaround this by ignoring 0.
+	 * This partly defeats the point of ramping, but will still catch
+	 * VBUS below 4.5V and above 0V.
+	 */
+	if (voltage == 0) {
+		CPRINTSUSB("%s vbus=0", __func__);
+		return 0;
+	}
+
+	if (voltage < BC12_MIN_VOLTAGE)
+		CPRINTSUSB("%s vbus=%d", __func__, voltage);
+
+	return voltage < BC12_MIN_VOLTAGE;
+}
+
+/**
+ * b/175324615: On G3->S5, wait for RSMRST_L to be deasserted before asserting
+ * PCH_PWRBTN_L.
+ */
+void board_pwrbtn_to_pch(int level)
+{
+	timestamp_t start;
+	const uint32_t timeout_rsmrst_rise_us = 30 * MSEC;
+
+	/* Add delay for G3 exit if asserting PWRBTN_L and RSMRST_L is low. */
+	if (!level && !gpio_get_level(GPIO_PCH_RSMRST_L)) {
+		start = get_time();
+		do {
+			usleep(200);
+			if (gpio_get_level(GPIO_PCH_RSMRST_L))
+				break;
+		} while (time_since32(start) < timeout_rsmrst_rise_us);
+
+		if (!gpio_get_level(GPIO_PCH_RSMRST_L))
+			ccprints("Error pwrbtn: RSMRST_L still low");
+
+		msleep(G3_TO_PWRBTN_DELAY_MS);
+	}
+	gpio_set_level(GPIO_PCH_PWRBTN_L, level);
+}
+
+void board_hibernate(void)
+{
+	int port;
+	enum ec_error_list ret;
+
+	/*
+	 * If we are charging, then drop the Vbus level down to 5V to ensure
+	 * that we don't get locked out of the 6.8V OVLO for our PPCs in
+	 * dead-battery mode. This is needed when the TCPC/PPC rails go away.
+	 * (b/79218851, b/143778351, b/147007265)
+	 */
+	port = charge_manager_get_active_charge_port();
+	if (port != CHARGE_PORT_NONE) {
+		pd_request_source_voltage(port, SAFE_RESET_VBUS_MV);
+
+		/* Give PD task and PPC chip time to get to 5V */
+		msleep(SAFE_RESET_VBUS_DELAY_MS);
+	}
+
+	/* Try to put our battery fuel gauge into sleep mode */
+	ret = battery_sleep_fuel_gauge();
+	if ((ret != EC_SUCCESS) && (ret != EC_ERROR_UNIMPLEMENTED))
+		cprints(CC_SYSTEM, "Failed to send battery sleep command");
+}
+
+__overridable enum ec_error_list
+board_a1_ps8811_retimer_init(const struct usb_mux *me)
+{
+	return EC_SUCCESS;
+}
+
+static int baseboard_a1_ps8811_retimer_init(const struct usb_mux *me)
+{
+	int rv;
+	int tries = 2;
+
+	do {
+		int val;
+
+		rv = ps8811_i2c_read(me, PS8811_REG_PAGE1,
+				     PS8811_REG1_USB_BEQ_LEVEL, &val);
+	} while (rv && --tries);
+
+	if (rv) {
+		CPRINTSUSB("A1: PS8811 retimer not detected!");
+		return rv;
+	}
+	CPRINTSUSB("A1: PS8811 retimer detected");
+	rv = board_a1_ps8811_retimer_init(me);
+	if (rv)
+		CPRINTSUSB("A1: Error during PS8811 setup rv:%d", rv);
+	return rv;
+}
+
+/* PS8811 is just a type-A USB retimer, reusing mux structure for convience. */
+const struct usb_mux usba1_ps8811 = {
+	.usb_port = USBA_PORT_A1,
+	.i2c_port = I2C_PORT_TCPC1,
+	.i2c_addr_flags = PS8811_I2C_ADDR_FLAGS3,
+	.board_init = &baseboard_a1_ps8811_retimer_init,
+};
+
+__overridable enum ec_error_list
+board_a1_anx7491_retimer_init(const struct usb_mux *me)
+{
+	return EC_SUCCESS;
+}
+
+static int baseboard_a1_anx7491_retimer_init(const struct usb_mux *me)
+{
+	int rv;
+	int tries = 2;
+
+	do {
+		int val;
+
+		rv = i2c_read8(me->i2c_port, me->i2c_addr_flags, 0, &val);
+	} while (rv && --tries);
+	if (rv) {
+		CPRINTSUSB("A1: ANX7491 retimer not detected!");
+		return rv;
+	}
+	CPRINTSUSB("A1: ANX7491 retimer detected");
+	rv = board_a1_anx7491_retimer_init(me);
+	if (rv)
+		CPRINTSUSB("A1: Error during ANX7491 setup rv:%d", rv);
+	return rv;
+}
+
+/* ANX7491 is just a type-A USB retimer, reusing mux structure for convience. */
+const struct usb_mux usba1_anx7491 = {
+	.usb_port = USBA_PORT_A1,
+	.i2c_port = I2C_PORT_TCPC1,
+	.i2c_addr_flags = ANX7491_I2C_ADDR0_FLAGS,
+	.board_init = &baseboard_a1_anx7491_retimer_init,
+};
+
+void baseboard_a1_retimer_setup(void)
+{
+	struct usb_mux a1_retimer;
+	switch (board_get_usb_a1_retimer()) {
+	case USB_A1_RETIMER_ANX7491:
+		a1_retimer = usba1_anx7491;
+		break;
+	case USB_A1_RETIMER_PS8811:
+		a1_retimer = usba1_ps8811;
+		break;
+	default:
+		CPRINTSUSB("A1: Unknown retimer!");
+		return;
+	}
+	a1_retimer.board_init(&a1_retimer);
+}
+DECLARE_DEFERRED(baseboard_a1_retimer_setup);
+
+static void baseboard_chipset_suspend(void)
+{
+	ioex_set_level(IOEX_USB_A1_RETIMER_EN, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, baseboard_chipset_suspend,
+	     HOOK_PRIO_DEFAULT);
+
+static void baseboard_chipset_resume(void)
+{
+	ioex_set_level(IOEX_USB_A1_RETIMER_EN, 1);
+	/* Some retimers take several ms to be ready, so defer setup call */
+	hook_call_deferred(&baseboard_a1_retimer_setup_data, 20 * MSEC);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, baseboard_chipset_resume, HOOK_PRIO_DEFAULT);
+
+void board_overcurrent_event(int port, int is_overcurrented)
+{
+	switch (port) {
+	case USBC_PORT_C0:
+	case USBC_PORT_C1:
+		gpio_set_level(GPIO_USB_C0_C1_FAULT_ODL, !is_overcurrented);
+		break;
+
+	default:
+		break;
+	}
+}
+
+static void baseboard_set_en_pwr_pcore(void)
+{
+	/*
+	 * EC must AND signals PG_LPDDR4X_S3_OD, PG_GROUPC_S0_OD, and
+	 * EN_PWR_S0_R.
+	 */
+	gpio_set_level(GPIO_EN_PWR_PCORE_S0_R,
+		       gpio_get_level(GPIO_PG_LPDDR4X_S3_OD) &&
+			       gpio_get_level(GPIO_PG_GROUPC_S0_OD) &&
+			       gpio_get_level(GPIO_EN_PWR_S0_R));
+}
+
+void baseboard_en_pwr_pcore_signal(enum gpio_signal signal)
+{
+	baseboard_set_en_pwr_pcore();
+}
+
+static void baseboard_check_groupc_low(void)
+{
+	/* Warn if we see unexpected sequencing here */
+	if (!gpio_get_level(GPIO_EN_PWR_S0_R) &&
+	    gpio_get_level(GPIO_PG_GROUPC_S0_OD))
+		CPRINTSCHIP("WARN: PG_GROUPC_S0_OD high while EN_PWR_S0_R low");
+}
+DECLARE_DEFERRED(baseboard_check_groupc_low);
+
+void baseboard_en_pwr_s0(enum gpio_signal signal)
+{
+	/* EC must AND signals SLP_S3_L and PG_PWR_S5 */
+	gpio_set_level(GPIO_EN_PWR_S0_R,
+		       gpio_get_level(GPIO_SLP_S3_L) &&
+			       gpio_get_level(GPIO_PG_PWR_S5));
+
+	/*
+	 * If we set EN_PWR_S0_R low, then check PG_GROUPC_S0_OD went low as
+	 * well some reasonable time later
+	 */
+	if (!gpio_get_level(GPIO_EN_PWR_S0_R))
+		hook_call_deferred(&baseboard_check_groupc_low_data,
+				   100 * MSEC);
+
+	/* Change EN_PWR_PCORE_S0_R if needed */
+	baseboard_set_en_pwr_pcore();
+
+	/* Now chain off to the normal power signal interrupt handler. */
+	power_signal_interrupt(signal);
+}
+
+#if defined(SECTION_IS_RW) && defined(CONFIG_POWER_SLEEP_FAILURE_DETECTION)
+
+/**
+ * S0ix Hang Recovery Fallback Routines.
+ *
+ * Only runs in RW to de-risk an unrecoverable boot loop in RO.
+ * power_board_s0ix_hang_detected is triggered by the common host_sleep S0ix
+ * hang detection. The default behavior is to send a wake event. Additional
+ * hang recovery fallback remedies are defined here.
+ * S3 sleep is not supported on guybrush, so not handled here.
+ */
+
+/* This timeout begins after CONFIG_SLEEP_TIMEOUT_MS */
+#define HARD_SLEEP_HANG_TIMEOUT 10000
+
+/* These counters are reset whenever there's a successful resume */
+static int soft_sleep_hang_count;
+static int hard_sleep_hang_count;
+
+/* Shutdown or reset on hard hang */
+static int shutdown_on_hard_hang;
+
+static void board_handle_hard_sleep_hang(void);
+DECLARE_DEFERRED(board_handle_hard_sleep_hang);
+
+static void stop_hard_hang_timer(void);
+
+__override void power_board_handle_sleep_hang(enum sleep_hang_type hang_type)
+{
+	soft_sleep_hang_count += 1;
+
+	/* Avoid race condition */
+	stop_hard_hang_timer();
+
+	if (hang_type == SLEEP_HANG_S0IX_SUSPEND)
+		ccprints("S0ix suspend sleep hang detected!");
+	else if (hang_type == SLEEP_HANG_S0IX_RESUME)
+		ccprints("S0ix resume sleep hang detected!");
+
+	ccprints("Consecutive sleep hang count: soft=%d hard=%d",
+		 soft_sleep_hang_count, hard_sleep_hang_count);
+
+	if (hard_sleep_hang_count == 0) {
+		/* Try an AP reset first */
+		shutdown_on_hard_hang = false;
+		ccprints("AP will be force reset in %dms if hang persists",
+			 HARD_SLEEP_HANG_TIMEOUT);
+	} else {
+		/* Avoid reboot loop that drains battery and just shutdown */
+		shutdown_on_hard_hang = true;
+		ccprints("Consecutive(%d) hard sleep hangs detected!",
+			 hard_sleep_hang_count);
+		ccprints("AP will be force shutdown in %dms if hang persists",
+			 HARD_SLEEP_HANG_TIMEOUT);
+	}
+
+	hook_call_deferred(&board_handle_hard_sleep_hang_data,
+			   HARD_SLEEP_HANG_TIMEOUT * MSEC);
+}
+
+/**
+ * Reboot or shutdown when hard sleep hang detected.
+ * This timer is stopped on suspend, resume, reset or shutdown events.
+ */
+static void board_handle_hard_sleep_hang(void)
+{
+	hard_sleep_hang_count += 1;
+	/* Avoid race condition */
+	stop_hard_hang_timer();
+
+	if (shutdown_on_hard_hang) {
+		ccprints("Very hard S0ix sleep hang detected!!! "
+			 "Shutting down AP now!");
+		chipset_force_shutdown(CHIPSET_SHUTDOWN_BOARD_CUSTOM);
+	} else {
+		ccprints("Hard S0ix sleep hang detected!! Resetting AP now!");
+		/* If AP reset does not break hang, force a shutdown */
+		shutdown_on_hard_hang = true;
+		ccprints("AP will be shutdown in %dms if hang persists",
+			 HARD_SLEEP_HANG_TIMEOUT);
+		hook_call_deferred(&board_handle_hard_sleep_hang_data,
+				   HARD_SLEEP_HANG_TIMEOUT * MSEC);
+		chipset_reset(CHIPSET_RESET_HANG_REBOOT);
+	}
+}
+
+/**
+ * Reset hang counters whenever a resume is successful
+ */
+static void reset_hang_counters(void)
+{
+	if (hard_sleep_hang_count || soft_sleep_hang_count)
+		ccprints("Successful S0ix resume after consecutive hangs: "
+			 "soft=%d hard=%d",
+			 soft_sleep_hang_count, hard_sleep_hang_count);
+	hard_sleep_hang_count = 0;
+	soft_sleep_hang_count = 0;
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, reset_hang_counters, HOOK_PRIO_DEFAULT);
+
+/**
+ * Hard hang detection timers are stopped on any suspend, resume, reset or
+ * shutdown event.
+ */
+static void stop_hard_hang_timer(void)
+{
+	hook_call_deferred(&board_handle_hard_sleep_hang_data, -1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, stop_hard_hang_timer, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, stop_hard_hang_timer, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_RESET, stop_hard_hang_timer, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, stop_hard_hang_timer, HOOK_PRIO_DEFAULT);
+
+#endif /* SECTION_IS_RW && CONFIG_POWER_SLEEP_FAILURE_DETECTION */
diff --git a/baseboard/guybrush/baseboard.h b/baseboard/guybrush/baseboard.h
new file mode 100644
index 0000000000..5e97bf1585
--- /dev/null
+++ b/baseboard/guybrush/baseboard.h
@@ -0,0 +1,358 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Guybrush baseboard configuration */
+
+#ifndef __CROS_EC_BASEBOARD_H
+#define __CROS_EC_BASEBOARD_H
+
+/* NPCX9 config */
+#define CONFIG_PORT80_4_BYTE
+#define NPCX9_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */
+#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */
+
+/* Optional features */
+#define CONFIG_ASSERT_CCD_MODE_ON_DTS_CONNECT
+#define CONFIG_LTO /* Link-Time Optimizations to reduce code size */
+
+/* Detect sleep hang after 10s */
+#undef CONFIG_SLEEP_TIMEOUT_MS
+#define CONFIG_SLEEP_TIMEOUT_MS 10000
+
+#undef CONFIG_UART_TX_BUF_SIZE
+#define CONFIG_UART_TX_BUF_SIZE 4096
+
+/* Vboot Config */
+#define CONFIG_CRC8
+#define CONFIG_VBOOT_EFS2
+#define CONFIG_VBOOT_HASH
+#define CONFIG_VSTORE
+#define CONFIG_VSTORE_SLOT_COUNT 1
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+
+/* CBI Config */
+#define CONFIG_CBI_EEPROM
+#define CONFIG_BOARD_VERSION_CBI
+
+/* Power Config */
+#define CONFIG_CHIPSET_X86_RSMRST_DELAY
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
+#define CONFIG_EXTPOWER_DEBOUNCE_MS 200
+#define CONFIG_EXTPOWER_GPIO
+#define CONFIG_HIBERNATE_PSL
+#define CONFIG_LOW_POWER_IDLE
+#define CONFIG_POWER_BUTTON
+#define CONFIG_POWER_BUTTON_TO_PCH_CUSTOM
+#define CONFIG_POWER_BUTTON_X86
+#define CONFIG_POWER_COMMON
+#define CONFIG_POWER_S0IX
+#define CONFIG_POWER_SLEEP_FAILURE_DETECTION
+#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
+#define G3_TO_PWRBTN_DELAY_MS 16
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_EN_PWR_A GPIO_EN_PWR_S5
+#define GPIO_PCH_PWRBTN_L GPIO_EC_SOC_PWR_BTN_L
+#define GPIO_PCH_RSMRST_L GPIO_EC_SOC_RSMRST_L
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S3_S0I3_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L
+#define GPIO_PCH_SYS_PWROK GPIO_EC_SOC_PWR_GOOD
+#define GPIO_PCH_WAKE_L GPIO_EC_SOC_WAKE_L
+#define GPIO_POWER_BUTTON_L GPIO_MECH_PWR_BTN_ODL
+#define GPIO_S0_PGOOD GPIO_PG_PCORE_S0_R_OD
+#define GPIO_S5_PGOOD GPIO_PG_PWR_S5
+#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L
+#define SAFE_RESET_VBUS_DELAY_MS 900
+#define SAFE_RESET_VBUS_MV 5000
+/*
+ * On power-on, H1 releases the EC from reset but then quickly asserts and
+ * releases the reset a second time. This means the EC sees 2 resets:
+ * (1) power-on reset, (2) reset-pin reset. This config will
+ * allow the second reset to be treated as a power-on.
+ */
+#define CONFIG_BOARD_RESET_AFTER_POWER_ON
+
+/* Thermal Config */
+#define CONFIG_ADC
+#define CONFIG_AMD_SB_RMI
+#define CONFIG_AMD_STT
+#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
+#define CONFIG_THROTTLE_AP
+#define CONFIG_TEMP_SENSOR_SB_TSI
+#define CONFIG_THERMISTOR
+#define CONFIG_CPU_PROCHOT_ACTIVE_LOW
+#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL
+
+/* Flash Config */
+/* See config_chip-npcx9.h for SPI flash configuration */
+#undef CONFIG_SPI_FLASH /* Don't enable external flash interface */
+#define GPIO_WP_L GPIO_EC_WP_L
+
+/* Host communication */
+#define CONFIG_CMD_APTHROTTLE
+#define CONFIG_CMD_CHARGEN
+#define CONFIG_HOST_INTERFACE_ESPI
+#define CONFIG_MKBP_EVENT
+#define CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT
+#define GPIO_EC_INT_L GPIO_EC_SOC_INT_L
+
+/* Chipset config */
+#define CONFIG_CHIPSET_CEZANNE
+#define CONFIG_CHIPSET_CAN_THROTTLE
+#define CONFIG_CHIPSET_RESET_HOOK
+
+/* Keyboard Config */
+#define CONFIG_MKBP_INPUT_DEVICES
+#define CONFIG_KEYBOARD_BACKLIGHT
+
+#define CONFIG_KEYBOARD_COL2_INVERTED
+#define CONFIG_KEYBOARD_PROTOCOL_8042
+#define CONFIG_KEYBOARD_VIVALDI
+#define CONFIG_KBLIGHT_ENABLE_PIN
+#define GPIO_EN_KEYBOARD_BACKLIGHT GPIO_EN_KB_BL
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+
+/* Sensors */
+#ifdef HAS_TASK_MOTIONSENSE
+
+#define CONFIG_TABLET_MODE
+#define CONFIG_GMR_TABLET_MODE
+#define GPIO_TABLET_MODE_L GPIO_TABLET_MODE
+#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_UPDATE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+
+/* Enable sensor fifo, must also define the _SIZE and _THRES */
+#define CONFIG_ACCEL_FIFO
+/* FIFO size is a power of 2. */
+#define CONFIG_ACCEL_FIFO_SIZE 256
+/* Depends on how fast the AP boots and typical ODRs. */
+#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
+
+/* Sensors without hardware FIFO are in forced mode */
+#define CONFIG_ACCEL_FORCE_MODE_MASK (1 << LID_ACCEL)
+#endif /* HAS_TASK_MOTIONSENSE */
+
+/* Backlight config */
+#define CONFIG_BACKLIGHT_LID
+#define CONFIG_BACKLIGHT_LID_ACTIVE_LOW
+#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_DISABLE_DISP_BL
+
+/* Battery Config */
+#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL
+#define CONFIG_BATTERY_CUT_OFF
+#define CONFIG_BATTERY_FUEL_GAUGE
+#define CONFIG_BATTERY_REVIVE_DISCONNECT
+#define CONFIG_BATTERY_SMART
+#define CONFIG_BATTERY_V2
+#define CONFIG_BATTERY_COUNT 1
+#define CONFIG_HOSTCMD_BATTERY_V2
+#define CONFIG_BC12_DETECT_PI3USB9201
+/* Enable PEC to detect potential corruption on read (b/230520109) */
+#define CONFIG_SMBUS_PEC
+
+/* Charger Config */
+#define CONFIG_CHARGER
+#define CONFIG_CHARGE_MANAGER
+#define CONFIG_CHARGER_DISCHARGE_ON_AC
+#define CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT 512
+#define CONFIG_CHARGER_ISL9241
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20
+
+/*
+ * EC will boot AP to depthcharge if: (BAT >= 2%) || (AC >= 65W)
+ * CONFIG_CHARGER_LIMIT_* is not set, so there is no additional restriction on
+ * Depthcharge to boot OS.
+ */
+#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 65000
+
+/*
+ * We would prefer to use CONFIG_CHARGE_RAMP_HW to enable legacy BC1.2 charging
+ * but that feature of ISL9241 is broken (b/160287056) so we have to use
+ * CONFIG_CHARGE_RAMP_SW instead.
+ */
+#define CONFIG_CHARGE_RAMP_SW
+
+/* USB Type C and USB PD config */
+#define CONFIG_USB_PD_REV30
+#define CONFIG_USB_PD_TCPMV2
+#define CONFIG_USB_PD_DECODE_SOP
+#define CONFIG_USB_DRP_ACC_TRYSRC
+#define CONFIG_HOSTCMD_PD_CONTROL
+#define CONFIG_CMD_TCPC_DUMP
+#define CONFIG_USB_CHARGER
+#define CONFIG_USB_POWER_DELIVERY
+#define CONFIG_USB_PD_5V_EN_CUSTOM
+#define CONFIG_USB_PD_ALT_MODE
+#define CONFIG_USB_PD_ALT_MODE_DFP
+#define CONFIG_USB_PD_DISCHARGE_TCPC
+#define CONFIG_USB_PD_DP_HPD_GPIO
+#define CONFIG_USB_PD_DUAL_ROLE
+#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+#define CONFIG_USB_PD_FRS_TCPC
+#define CONFIG_USB_PD_LOGGING
+#define CONFIG_USB_PD_TCPC_LOW_POWER
+#define CONFIG_USB_PD_TCPM_MUX
+#define CONFIG_USB_PD_TCPM_NCT38XX
+#define CONFIG_USB_PD_TCPM_TCPCI
+#define CONFIG_USB_PD_VBUS_DETECT_TCPC
+#define CONFIG_USBC_PPC
+#define CONFIG_USBC_PPC_SBU
+#define CONFIG_USBC_PPC_AOZ1380
+#define CONFIG_USBC_RETIMER_PI3HDX1204
+#define CONFIG_USBC_SS_MUX
+#define CONFIG_USBC_SS_MUX_DFP_ONLY
+#define CONFIG_USBC_VCONN
+#define CONFIG_USBC_VCONN_SWAP
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#define CONFIG_USBC_PPC_NX20P3483
+#define CONFIG_USBC_RETIMER_PS8811
+#define CONFIG_USBC_RETIMER_PS8818
+#define CONFIG_USB_MUX_RUNTIME_CONFIG
+#define CONFIG_USB_MUX_AMD_FP6
+
+#define GPIO_USB_C0_DP_HPD GPIO_USB_C0_HPD
+#define GPIO_USB_C1_DP_HPD GPIO_USB_C1_HPD
+
+#define CONFIG_IO_EXPANDER
+#define CONFIG_IO_EXPANDER_NCT38XX
+#define CONFIG_IO_EXPANDER_PORT_COUNT USBC_PORT_COUNT
+
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+
+/* USB-A config */
+#define USB_PORT_COUNT USBA_PORT_COUNT
+#define CONFIG_USB_PORT_POWER_SMART
+#define CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY
+#define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_CDP
+#define CONFIG_USB_PORT_POWER_SMART_INVERTED
+
+#define GPIO_USB1_ILIM_SEL IOEX_USB_A0_LIMIT_SDP
+#define GPIO_USB2_ILIM_SEL IOEX_USB_A1_LIMIT_SDP_DB
+
+/* Round up 5000 max current to multiple of 128mA for ISL9241 AC prochot. */
+#define GUYBRUSH_AC_PROCHOT_CURRENT_MA 5120
+
+/*
+ * USB ID - This is allocated specifically for Guybrush
+ */
+#define CONFIG_USB_PID 0x504D
+
+/* BC 1.2 */
+/*
+ * For legacy BC1.2 charging with CONFIG_CHARGE_RAMP_SW, ramp up input current
+ * until voltage drops to 4.5V. Don't go lower than this to be kind to the
+ * charger (see b/67964166).
+ */
+#define BC12_MIN_VOLTAGE 4500
+
+/* I2C Bus Configuration */
+#define CONFIG_I2C
+#define CONFIG_I2C_BUS_MAY_BE_UNPOWERED
+#define CONFIG_I2C_CONTROLLER
+#define CONFIG_I2C_UPDATE_IF_CHANGED
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0
+#define I2C_PORT_TCPC1 NPCX_I2C_PORT1_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_MUX NPCX_I2C_PORT3_0
+#define I2C_PORT_POWER NPCX_I2C_PORT4_1
+#define I2C_PORT_CHARGER I2C_PORT_POWER
+#define I2C_PORT_EEPROM NPCX_I2C_PORT5_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT6_1
+#define I2C_PORT_THERMAL_AP NPCX_I2C_PORT7_0
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+
+/* Volume Button Config */
+#define CONFIG_VOLUME_BUTTONS
+#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL
+
+/* Fan Config */
+#define CONFIG_FANS FAN_CH_COUNT
+
+/* LED Config */
+#define CONFIG_PWM
+#define CONFIG_PWM_KBLIGHT
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+/* Power input signals */
+enum power_signal {
+	X86_SLP_S0_N, /* SOC  -> SLP_S3_S0I3_L */
+	X86_SLP_S3_N, /* SOC  -> SLP_S3_L */
+	X86_SLP_S5_N, /* SOC  -> SLP_S5_L */
+
+	X86_S0_PGOOD, /* PMIC -> S0_PWROK_OD */
+	X86_S5_PGOOD, /* PMIC -> S5_PWROK */
+
+	/* Number of X86 signals */
+	POWER_SIGNAL_COUNT,
+};
+
+/* USB-C ports */
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
+
+/* USB-A ports */
+enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT };
+
+/* TMP112 sensors */
+enum tmp112_sensor {
+	TMP112_SOC,
+	TMP112_AMB,
+	TMP112_COUNT,
+};
+
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
+
+/* PWM Channels */
+enum pwm_channel {
+	PWM_CH_FAN = 0,
+	PWM_CH_KBLIGHT,
+	PWM_CH_LED_CHRG,
+	PWM_CH_LED_FULL,
+	PWM_CH_COUNT
+};
+
+/* Fan Channels */
+enum fan_channel {
+	FAN_CH_0 = 0,
+	/* Number of FAN channels */
+	FAN_CH_COUNT,
+};
+enum mft_channel {
+	MFT_CH_0 = 0,
+	/* Number of MFT channels */
+	MFT_CH_COUNT,
+};
+
+/* Common definition for the USB PD interrupt handlers. */
+void tcpc_alert_event(enum gpio_signal signal);
+void bc12_interrupt(enum gpio_signal signal);
+void ppc_interrupt(enum gpio_signal signal);
+void sbu_fault_interrupt(enum ioex_signal signal);
+
+void baseboard_en_pwr_pcore_signal(enum gpio_signal signal);
+void baseboard_en_pwr_s0(enum gpio_signal signal);
+
+int board_get_soc_temp_k(int idx, int *temp_k);
+
+/* CBI utility functions */
+uint32_t get_sku_id(void);
+uint32_t get_board_version(void);
+uint32_t get_fw_config(void);
+/* Board callback after CBI has been initialized */
+__overridable void board_cbi_init(void);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BASEBOARD_H */
diff --git a/baseboard/guybrush/build.mk b/baseboard/guybrush/build.mk
new file mode 100644
index 0000000000..8110e6e6c4
--- /dev/null
+++ b/baseboard/guybrush/build.mk
@@ -0,0 +1,15 @@
+# -*- makefile -*-
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Guybrush baseboard specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx9
+CHIP_VARIANT:=npcx9m3f
+
+baseboard-y=baseboard.o
+baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
+baseboard-$(CONFIG_CBI_EEPROM)+=cbi.o
diff --git a/baseboard/guybrush/cbi.c b/baseboard/guybrush/cbi.c
new file mode 100644
index 0000000000..1baf506297
--- /dev/null
+++ b/baseboard/guybrush/cbi.c
@@ -0,0 +1,94 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Guybrush CrOS Board Info(CBI) utilities */
+
+#include "base_fw_config.h"
+#include "common.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "hooks.h"
+
+uint32_t get_sku_id(void)
+{
+	static uint32_t sku_id;
+
+	if (sku_id == 0) {
+		uint32_t val;
+
+		if (cbi_get_sku_id(&val) != EC_SUCCESS)
+			return 0;
+		sku_id = val;
+	}
+	return sku_id;
+}
+
+uint32_t get_board_version(void)
+{
+	static uint32_t board_version;
+
+	if (board_version == 0) {
+		uint32_t val;
+
+		if (cbi_get_board_version(&val) != EC_SUCCESS)
+			return -1;
+		board_version = val;
+	}
+	return board_version;
+}
+
+uint32_t get_fw_config(void)
+{
+	static uint32_t fw_config = UNINITIALIZED_FW_CONFIG;
+
+	if (fw_config == UNINITIALIZED_FW_CONFIG) {
+		uint32_t val;
+
+		if (cbi_get_fw_config(&val) != EC_SUCCESS)
+			return UNINITIALIZED_FW_CONFIG;
+		fw_config = val;
+	}
+	return fw_config;
+}
+
+int get_fw_config_field(uint8_t offset, uint8_t width)
+{
+	uint32_t fw_config = get_fw_config();
+
+	if (fw_config == UNINITIALIZED_FW_CONFIG)
+		return -1;
+
+	return (fw_config >> offset) & ((1 << width) - 1);
+}
+
+__overridable void board_cbi_init(void)
+{
+}
+
+static void cbi_init(void)
+{
+	uint32_t board_ver = get_board_version();
+	uint32_t sku_id = get_sku_id();
+	uint32_t fw_config = get_fw_config();
+
+	if (board_ver != 0)
+		ccprints("Board Version: %d (0x%x)", board_ver, board_ver);
+	else
+		ccprints("Board Version: not set in cbi");
+
+	if (sku_id != 0)
+		ccprints("SKU ID: %d (0x%x)", sku_id, sku_id);
+	else
+		ccprints("SKU ID: not set in cbi");
+
+	if (fw_config != UNINITIALIZED_FW_CONFIG)
+		ccprints("FW Config: %d (0x%x)", fw_config, fw_config);
+	else
+		ccprints("FW Config: not set in cbi");
+
+	/* Allow the board project to make runtime changes based on CBI data */
+	board_cbi_init();
+}
+DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1);
diff --git a/baseboard/guybrush/usb_pd_policy.c b/baseboard/guybrush/usb_pd_policy.c
new file mode 100644
index 0000000000..8acb2c7a23
--- /dev/null
+++ b/baseboard/guybrush/usb_pd_policy.c
@@ -0,0 +1,92 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Shared USB-C policy for Zork boards */
+
+#include "charge_manager.h"
+#include "chipset.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "ioexpander.h"
+#include "system.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+int pd_check_vconn_swap(int port)
+{
+	/*
+	 * Do not allow vconn swap 5V rail is off
+	 * S5_PGOOD depends on PG_PP5000_S5 being asserted,
+	 * so GPIO_S5_PGOOD is a reasonable proxy for PP5000_S5
+	 */
+	return gpio_get_level(GPIO_S5_PGOOD);
+}
+
+void pd_power_supply_reset(int port)
+{
+	/* Disable VBUS. */
+	ppc_vbus_source_enable(port, 0);
+
+	/* Enable discharge if we were previously sourcing 5V */
+	if (IS_ENABLED(CONFIG_USB_PD_DISCHARGE))
+		pd_set_vbus_discharge(port, 1);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	/* Disable charging. */
+	rv = ppc_vbus_sink_enable(port, 0);
+	if (rv)
+		return rv;
+
+	if (IS_ENABLED(CONFIG_USB_PD_DISCHARGE))
+		pd_set_vbus_discharge(port, 0);
+
+	/* Provide Vbus. */
+	rv = ppc_vbus_source_enable(port, 1);
+	if (rv)
+		return rv;
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+__override int board_pd_set_frs_enable(int port, int enable)
+{
+	/*
+	 * Both PPCs require the FRS GPIO to be set as soon as FRS capability
+	 * is established.
+	 */
+	if (port == 0)
+		ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN, enable);
+	else if (port == 1)
+		ioex_set_level(IOEX_USB_C1_TCPC_FASTSW_CTL_EN, enable);
+
+	return EC_SUCCESS;
+}
+
+/* Used by Vbus discharge common code with CONFIG_USB_PD_DISCHARGE */
+int board_vbus_source_enabled(int port)
+{
+	return tcpm_get_src_ctrl(port);
+}
+
+/* Used by USB charger task with CONFIG_USB_PD_5V_EN_CUSTOM */
+int board_is_sourcing_vbus(int port)
+{
+	return board_vbus_source_enabled(port);
+}
diff --git a/baseboard/hatch/baseboard.c b/baseboard/hatch/baseboard.c
index 367f83e8d2..b342cd74ed 100644
--- a/baseboard/hatch/baseboard.c
+++ b/baseboard/hatch/baseboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,7 +7,7 @@
 #include "atomic.h"
 #include "battery_fuel_gauge.h"
 #include "charge_manager.h"
-#include "charge_state_v2.h"
+#include "charge_state.h"
 #include "chipset.h"
 #include "console.h"
 #include "cros_board_info.h"
@@ -26,16 +26,16 @@
 #include "power.h"
 #include "stdbool.h"
 #include "system.h"
-#include "tcpci.h"
+#include "tcpm/tcpci.h"
 #include "timer.h"
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /******************************************************************************/
 /* Wake up pins */
@@ -52,25 +52,65 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 /* I2C port map configuration */
 const struct i2c_port_t i2c_ports[] = {
 #ifdef CONFIG_ACCEL_FIFO
-	{"sensor",  I2C_PORT_SENSOR,  100, GPIO_I2C0_SCL, GPIO_I2C0_SDA},
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 100,
+	  .scl = GPIO_I2C0_SCL,
+	  .sda = GPIO_I2C0_SDA },
 #endif
-	{"ppc0",    I2C_PORT_PPC0,    100, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
+	{ .name = "ppc0",
+	  .port = I2C_PORT_PPC0,
+	  .kbps = 100,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
 #if CONFIG_USB_PD_PORT_MAX_COUNT > 1
-	{"tcpc1",   I2C_PORT_TCPC1,   400, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
+	{ .name = "tcpc1",
+	  .port = I2C_PORT_TCPC1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
 #endif
-	{"tcpc0",   I2C_PORT_TCPC0,   400, GPIO_I2C3_SCL, GPIO_I2C3_SDA},
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
 #ifdef BOARD_AKEMI
-	{"thermal", I2C_PORT_THERMAL, 400, GPIO_I2C4_SCL, GPIO_I2C4_SDA},
+	{ .name = "thermal",
+	  .port = I2C_PORT_THERMAL,
+	  .kbps = 400,
+	  .scl = GPIO_I2C4_SCL,
+	  .sda = GPIO_I2C4_SDA },
 #endif
 #ifdef BOARD_JINLON
-	{"thermal", I2C_PORT_THERMAL, 100, GPIO_I2C4_SCL, GPIO_I2C4_SDA},
+	{ .name = "thermal",
+	  .port = I2C_PORT_THERMAL,
+	  .kbps = 100,
+	  .scl = GPIO_I2C4_SCL,
+	  .sda = GPIO_I2C4_SDA },
 #endif
 #ifdef BOARD_MUSHU
-	{"f75303_temp", I2C_PORT_THERMAL, 100, GPIO_I2C0_SCL, GPIO_I2C0_SDA},
-	{"gpu_temp", I2C_PORT_GPU, 100, GPIO_I2C4_SCL, GPIO_I2C4_SDA},
+	{ .name = "f75303_temp",
+	  .port = I2C_PORT_THERMAL,
+	  .kbps = 100,
+	  .scl = GPIO_I2C0_SCL,
+	  .sda = GPIO_I2C0_SDA },
+	{ .name = "gpu_temp",
+	  .port = I2C_PORT_GPU,
+	  .kbps = 100,
+	  .scl = GPIO_I2C4_SCL,
+	  .sda = GPIO_I2C4_SDA },
 #endif
-	{"power",   I2C_PORT_POWER,   100, GPIO_I2C5_SCL, GPIO_I2C5_SDA},
-	{"eeprom",  I2C_PORT_EEPROM,  100, GPIO_I2C7_SCL, GPIO_I2C7_SDA},
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_I2C5_SCL,
+	  .sda = GPIO_I2C5_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 100,
+	  .scl = GPIO_I2C7_SCL,
+	  .sda = GPIO_I2C7_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -93,14 +133,6 @@ __attribute__((weak)) bool board_has_kb_backlight(void)
 	return true;
 }
 
-/* Called on AP S5 -> S3 transition */
-static void baseboard_chipset_startup(void)
-{
-	/* TODD(b/122266850): Need to fill out this hook */
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, baseboard_chipset_startup,
-	     HOOK_PRIO_DEFAULT);
-
 /* Called on AP S0iX -> S0 transition */
 static void baseboard_chipset_resume(void)
 {
@@ -118,14 +150,6 @@ static void baseboard_chipset_suspend(void)
 DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, baseboard_chipset_suspend,
 	     HOOK_PRIO_DEFAULT);
 
-/* Called on AP S3 -> S5 transition */
-static void baseboard_chipset_shutdown(void)
-{
-
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, baseboard_chipset_shutdown,
-	     HOOK_PRIO_DEFAULT);
-
 void board_hibernate(void)
 {
 	int port;
@@ -134,7 +158,7 @@ void board_hibernate(void)
 	 * To support hibernate from ectool, keyboard, and console,
 	 * ensure that the AP is fully shutdown before hibernating.
 	 */
-#ifdef HAS_TASK_CHIPSET
+#ifdef CONFIG_AP_POWER_CONTROL
 	chipset_force_shutdown(CHIPSET_SHUTDOWN_BOARD_CUSTOM);
 #endif
 
@@ -158,17 +182,13 @@ void board_hibernate(void)
 /******************************************************************************/
 /* USB-C PPC Configuration */
 struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.i2c_port = I2C_PORT_PPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
+	[USB_PD_PORT_TCPC_0] = { .i2c_port = I2C_PORT_PPC0,
+				 .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+				 .drv = &sn5s330_drv },
 #if CONFIG_USB_PD_PORT_MAX_COUNT > 1
-	[USB_PD_PORT_TCPC_1] = {
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
+	[USB_PD_PORT_TCPC_1] = { .i2c_port = I2C_PORT_TCPC1,
+				 .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+				 .drv = &sn5s330_drv },
 #endif
 };
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
@@ -226,8 +246,8 @@ uint16_t tcpc_get_alert_status(void)
 	return status;
 }
 
-static void reset_pd_port(int port, enum gpio_signal reset_gpio,
-			  int hold_delay, int finish_delay)
+static void reset_pd_port(int port, enum gpio_signal reset_gpio, int hold_delay,
+			  int finish_delay)
 {
 	int level = !!(tcpc_config[port].flags & TCPC_FLAGS_RESET_ACTIVE_HIGH);
 
@@ -264,8 +284,7 @@ void board_reset_pd_mcu(void)
 
 int board_set_active_charge_port(int port)
 {
-	int is_valid_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	int i;
 
 	if (!is_valid_port && port != CHARGE_PORT_NONE)
@@ -321,39 +340,30 @@ int ppc_get_alert_status(int port)
 	if (port == USB_PD_PORT_TCPC_0)
 		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
 	return port == USB_PD_PORT_TCPC_0 ?
-		gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0 :
+		       gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0 :
 #if CONFIG_USB_PD_PORT_MAX_COUNT > 1
-		gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
+		       gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
 #else
-		EC_SUCCESS;
+		       EC_SUCCESS;
 #endif
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
-}
-
 #ifdef USB_PD_PORT_TCPC_MST
 void baseboard_mst_enable_control(enum mst_source src, int level)
 {
-	static uint32_t mst_input_levels;
+	static atomic_t mst_input_levels;
 
 	if (level)
-		deprecated_atomic_or(&mst_input_levels, 1 << src);
+		atomic_or(&mst_input_levels, 1 << src);
 	else
-		deprecated_atomic_clear_bits(&mst_input_levels, 1 << src);
+		atomic_clear_bits(&mst_input_levels, 1 << src);
 
 	gpio_set_level(GPIO_EN_MST, mst_input_levels ? 1 : 0);
 }
 #endif
 
 /* Enable or disable input devices, based on chipset state */
-#ifndef TEST_BUILD
-void lid_angle_peripheral_enable(int enable)
+__override void lid_angle_peripheral_enable(int enable)
 {
 	if (board_is_convertible()) {
 		if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
@@ -361,7 +371,6 @@ void lid_angle_peripheral_enable(int enable)
 		keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
 	}
 }
-#endif
 
 static uint8_t sku_id;
 static uint8_t board_id;
diff --git a/baseboard/hatch/baseboard.h b/baseboard/hatch/baseboard.h
index 00ce1e0dac..4aee5200de 100644
--- a/baseboard/hatch/baseboard.h
+++ b/baseboard/hatch/baseboard.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,21 +8,22 @@
 #ifndef __CROS_EC_BASEBOARD_H
 #define __CROS_EC_BASEBOARD_H
 
+#include "compiler.h"
 #include "stdbool.h"
 
 /*
  * By default, enable all console messages excepted HC, ACPI and event:
  * The sensor stack is generating a lot of activity.
  */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
 #undef CONFIG_HOSTCMD_DEBUG_MODE
 #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
 
 /* NPCX7 config */
-#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
-#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
+#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */
+#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */
 /* Internal SPI flash on NPCX796FC is 512 kB */
-#define CONFIG_FLASH_SIZE (512 * 1024)
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
 #define CONFIG_SPI_FLASH_REGS
 #define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
 #define CONFIG_I2C
@@ -34,7 +35,7 @@
 #define CONFIG_ADC
 #define CONFIG_BOARD_VERSION_CBI
 #define CONFIG_CRC8
-#define CONFIG_CROS_BOARD_INFO
+#define CONFIG_CBI_EEPROM
 #define CONFIG_DPTF
 #define CONFIG_HIBERNATE_PSL
 #define CONFIG_LED_ONOFF_STATES
@@ -95,30 +96,31 @@
 #define CONFIG_CHARGER
 #define CONFIG_CHARGER_BQ25710
 #define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT 512 /* Allow low-current USB charging */
+/* Allow low-current USB charging */
+#define CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT 512
+#define CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT 512
+#undef CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON
 #define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 1
-#define CONFIG_CHARGER_NARROW_VDC
 #define CONFIG_CHARGE_RAMP_HW
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10
 /*
  * Don't allow the system to boot to S0 when the battery is low and unable to
  * communicate on locked systems (which haven't PD negotiated)
  */
 #define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT 15000
-#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC 1
 #define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 15001
 
 /* Common battery defines */
 #define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY  "LION"
+#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
 #define CONFIG_BATTERY_FUEL_GAUGE
 #define CONFIG_BATTERY_HW_PRESENT_CUSTOM
 #define CONFIG_BATTERY_PRESENT_CUSTOM
 #define CONFIG_BATTERY_REVIVE_DISCONNECT
 #define CONFIG_BATTERY_SMART
-#undef  CONFIG_BATT_HOST_FULL_FACTOR
-#define CONFIG_BATT_HOST_FULL_FACTOR	100
+#undef CONFIG_BATT_HOST_FULL_FACTOR
+#define CONFIG_BATT_HOST_FULL_FACTOR 100
 
 /* USB Type C and USB PD defines */
 #define CONFIG_USB_POWER_DELIVERY
@@ -153,9 +155,9 @@
 /* Include CLI command needed to support CCD testing. */
 #define CONFIG_CMD_CHARGEN
 
-#define USB_PD_PORT_TCPC_0	0
+#define USB_PD_PORT_TCPC_0 0
 #if CONFIG_USB_PD_PORT_MAX_COUNT > 1
-#define USB_PD_PORT_TCPC_1	1
+#define USB_PD_PORT_TCPC_1 1
 #endif
 
 /* BC 1.2 */
@@ -167,33 +169,32 @@
 #endif
 
 /* TODO(b/122273953): Use correct PD delay values */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000	/* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	250000	/* us */
-#define PD_VCONN_SWAP_DELAY		5000	/* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* TODO(b/122273953): Use correct PD power values */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* I2C Bus Configuration */
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_PPC0		NPCX_I2C_PORT1_0
-#define I2C_PORT_TCPC1		NPCX_I2C_PORT2_0
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT3_0
-#define I2C_PORT_THERMAL	NPCX_I2C_PORT4_1
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_POWER
+#define CONFIG_I2C_CONTROLLER
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_PPC0 NPCX_I2C_PORT1_0
+#define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT3_0
+#define I2C_PORT_THERMAL NPCX_I2C_PORT4_1
+#define I2C_PORT_POWER NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+#define I2C_PORT_BATTERY I2C_PORT_POWER
+#define I2C_PORT_CHARGER I2C_PORT_POWER
 
 /* Other common defines */
 #define CONFIG_BACKLIGHT_LID
-#define GPIO_ENABLE_BACKLIGHT   GPIO_EDP_BKLTEN_OD
+#define GPIO_ENABLE_BACKLIGHT GPIO_EDP_BKLTEN_OD
 
 #define PP5000_PGOOD_POWER_SIGNAL_MASK POWER_SIGNAL_MASK(X86_PP5000_A_PGOOD)
 
@@ -213,6 +214,8 @@ void board_reset_pd_mcu(void);
 void baseboard_mst_enable_control(enum mst_source, int level);
 bool board_is_convertible(void);
 
+FORWARD_DECLARE_ENUM(battery_present);
+
 /* Check with variant about battery presence. */
 enum battery_present variant_battery_present(void);
 
diff --git a/baseboard/hatch/battery.c b/baseboard/hatch/battery.c
index 063aa3721d..5ae92e8ec8 100644
--- a/baseboard/hatch/battery.c
+++ b/baseboard/hatch/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -32,8 +32,9 @@ static int battery_init(void)
 {
 	int batt_status;
 
-	return battery_status(&batt_status) ? 0 :
-		!!(batt_status & STATUS_INITIALIZED);
+	return battery_status(&batt_status) ?
+		       0 :
+		       !!(batt_status & STATUS_INITIALIZED);
 }
 
 /*
diff --git a/baseboard/hatch/build.mk b/baseboard/hatch/build.mk
index 864225f605..f98ffdcb3f 100644
--- a/baseboard/hatch/build.mk
+++ b/baseboard/hatch/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/baseboard/hatch/usb_pd_policy.c b/baseboard/hatch/usb_pd_policy.c
index c0c75f9cdb..6abb6e4454 100644
--- a/baseboard/hatch/usb_pd_policy.c
+++ b/baseboard/hatch/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,15 +12,15 @@
 #include "ec_commands.h"
 #include "gpio.h"
 #include "system.h"
-#include "tcpci.h"
-#include "tcpm.h"
+#include "tcpm/tcpci.h"
+#include "tcpm/tcpm.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
diff --git a/baseboard/herobrine/baseboard.c b/baseboard/herobrine/baseboard.c
new file mode 100644
index 0000000000..fca6e9c66d
--- /dev/null
+++ b/baseboard/herobrine/baseboard.c
@@ -0,0 +1,13 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Herobrine baseboard-specific configuration */
+
+#include "i2c.h"
+
+int board_allow_i2c_passthru(const struct i2c_cmd_desc_t *cmd_desc)
+{
+	return (cmd_desc->port == I2C_PORT_VIRTUAL_BATTERY);
+}
diff --git a/baseboard/herobrine/baseboard.h b/baseboard/herobrine/baseboard.h
new file mode 100644
index 0000000000..72b8b02b04
--- /dev/null
+++ b/baseboard/herobrine/baseboard.h
@@ -0,0 +1,217 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Herobrine baseboard configuration */
+
+#ifndef __CROS_EC_BASEBOARD_H
+#define __CROS_EC_BASEBOARD_H
+
+/*
+ * By default, enable all console messages excepted event and HC:
+ * The sensor stack is generating a lot of activity.
+ * They can be enabled through the console command 'chan'.
+ */
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_HOSTCMD)))
+
+/* NPCX7 config */
+#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */
+#define NPCX_TACH_SEL2 0 /* No tach. */
+#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */
+
+/* Internal SPI flash on NPCX7 */
+#define CONFIG_SPI_FLASH_REGS
+#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
+
+/* EC Modules */
+#define CONFIG_I2C
+#define CONFIG_I2C_CONTROLLER
+#define CONFIG_I2C_VIRTUAL_BATTERY
+#define CONFIG_I2C_PASSTHRU_RESTRICTED
+#define CONFIG_LED_COMMON
+#define CONFIG_LOW_POWER_IDLE
+#define CONFIG_ADC
+#define CONFIG_BACKLIGHT_LID
+#define CONFIG_FPU
+#define CONFIG_PWM
+#define CONFIG_PWM_DISPLIGHT
+#define CONFIG_HIBERNATE_PSL
+
+#define CONFIG_VBOOT_HASH
+
+#undef CONFIG_PECI
+
+#define CONFIG_HOST_INTERFACE_SHI
+#define CONFIG_HOST_COMMAND_STATUS
+#define CONFIG_HOSTCMD_SECTION_SORTED
+#define CONFIG_KEYBOARD_COL2_INVERTED
+#define CONFIG_MKBP_USE_GPIO
+
+#define CONFIG_BOARD_VERSION_GPIO
+#define CONFIG_CBI_GPIO
+#define CONFIG_CRC8
+#define CONFIG_POWER_BUTTON
+#define CONFIG_VOLUME_BUTTONS
+#define CONFIG_EMULATED_SYSRQ
+#define CONFIG_CMD_BUTTON
+#define CONFIG_SWITCH
+#define CONFIG_LID_SWITCH
+#define CONFIG_EXTPOWER_GPIO
+
+/*
+ * On power-on, H1 releases the EC from reset but then quickly asserts and
+ * releases the reset a second time. This means the EC sees 2 resets:
+ * (1) power-on reset, (2) reset-pin reset. This config will
+ * allow the second reset to be treated as a power-on.
+ */
+#define CONFIG_BOARD_RESET_AFTER_POWER_ON
+
+/* Increase console output buffer since we have the RAM available. */
+#undef CONFIG_UART_TX_BUF_SIZE
+#define CONFIG_UART_TX_BUF_SIZE 4096
+
+/* Battery */
+#define CONFIG_BATTERY_CUT_OFF
+#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BATT_PRES_ODL
+#define CONFIG_BATTERY_SMART
+
+/* Charger */
+#define CONFIG_CHARGER
+#define CONFIG_CHARGE_MANAGER
+#define CONFIG_CHARGER_ISL9238
+#define CONFIG_CHARGER_PROFILE_OVERRIDE
+#define CONFIG_CHARGE_RAMP_HW
+#define CONFIG_USB_CHARGER
+#define CONFIG_CMD_CHARGER_ADC_AMON_BMON
+#define CONFIG_CHARGER_PSYS
+#define CONFIG_CHARGER_PSYS_READ
+#define CONFIG_CHARGER_DISCHARGE_ON_AC
+
+#define CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT 512
+#define CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT 512
+#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 10000
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20
+
+/*
+ * USB ID
+ *
+ * This is allocated specifically for Herobrine
+ * http://google3/hardware/standards/usb/
+ */
+#define CONFIG_USB_PID 0x5055
+
+/* USB */
+#define CONFIG_USB_POWER_DELIVERY
+#define CONFIG_USB_PD_TCPMV2
+#define CONFIG_USB_DRP_ACC_TRYSRC
+#define CONFIG_USB_PD_DECODE_SOP
+#define CONFIG_HOSTCMD_PD_CONTROL
+#define CONFIG_USB_PD_ALT_MODE
+#define CONFIG_USB_PD_ALT_MODE_DFP
+#define CONFIG_USB_PD_DISCHARGE_PPC
+#define CONFIG_USB_PD_DUAL_ROLE
+#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+#define CONFIG_USB_PD_TCPC_LOW_POWER
+#define CONFIG_USB_PD_LOGGING
+#define CONFIG_USB_PD_TCPM_MUX
+#define CONFIG_USB_PD_TCPM_TCPCI
+#define CONFIG_CMD_TCPC_DUMP
+#define CONFIG_USB_PD_TRY_SRC
+#define CONFIG_USB_PD_VBUS_DETECT_TCPC
+#define CONFIG_USB_PD_5V_EN_CUSTOM
+#define CONFIG_USBC_SS_MUX
+#define CONFIG_USBC_SS_MUX_DFP_ONLY
+#define CONFIG_USBC_VCONN
+#define CONFIG_USBC_VCONN_SWAP
+
+/* RTC */
+#define CONFIG_CMD_RTC
+#define CONFIG_HOSTCMD_RTC
+
+/* Sensors */
+/* Enable sensor fifo, must also define the _SIZE and _THRES */
+#define CONFIG_ACCEL_FIFO
+/* FIFO size is a power of 2. */
+#define CONFIG_ACCEL_FIFO_SIZE 256
+/* Depends on how fast the AP boots and typical ODRs. */
+#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
+#define CONFIG_CMD_ACCELS
+#define CONFIG_CMD_ACCEL_INFO
+
+/* PD */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
+
+#define PD_OPERATING_POWER_MW 10000
+#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
+
+/* Chipset */
+#define CONFIG_CHIPSET_SC7280
+#define CONFIG_CHIPSET_RESET_HOOK
+#define CONFIG_CHIPSET_RESUME_INIT_HOOK
+#define CONFIG_POWER_COMMON
+#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
+#define CONFIG_POWER_SLEEP_FAILURE_DETECTION
+#define CONFIG_CMD_AP_RESET_LOG
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_LID_OPEN GPIO_LID_OPEN_EC
+#define GPIO_SHI_CS_L GPIO_AP_EC_SPI_CS_L
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_BATT_PRES_ODL GPIO_EC_BATT_PRES_ODL
+#define GPIO_ENABLE_BACKLIGHT GPIO_EC_BL_DISABLE_L
+#define GPIO_BOARD_VERSION1 GPIO_BRD_ID0
+#define GPIO_BOARD_VERSION2 GPIO_BRD_ID1
+#define GPIO_BOARD_VERSION3 GPIO_BRD_ID2
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+
+/* I2C Ports */
+#define I2C_PORT_BATTERY I2C_PORT_POWER
+#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
+#define I2C_PORT_CHARGER I2C_PORT_POWER
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
+#define I2C_PORT_POWER NPCX_I2C_PORT0_0
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT1_0
+#define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0
+#define I2C_PORT_WLC NPCX_I2C_PORT3_0
+#define I2C_PORT_RTC NPCX_I2C_PORT4_1
+#define I2C_PORT_EEPROM NPCX_I2C_PORT5_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT7_0
+
+/* UART */
+#define CONFIG_CMD_CHARGEN
+
+/* Define the host events which are allowed to wake AP up from S3 */
+#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK                   \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |        \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |    \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |    \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT) |     \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC) |             \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |     \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_DEVICE))
+
+/* And the MKBP events */
+#ifdef HAS_TASK_KEYSCAN
+#define CONFIG_MKBP_EVENT_WAKEUP_MASK                                    \
+	(BIT(EC_MKBP_EVENT_KEY_MATRIX) | BIT(EC_MKBP_EVENT_HOST_EVENT) | \
+	 BIT(EC_MKBP_EVENT_SENSOR_FIFO))
+#else
+#define CONFIG_MKBP_EVENT_WAKEUP_MASK \
+	(BIT(EC_MKBP_EVENT_HOST_EVENT) | BIT(EC_MKBP_EVENT_SENSOR_FIFO))
+#endif
+
+#endif /* __CROS_EC_BASEBOARD_H */
diff --git a/baseboard/herobrine/build.mk b/baseboard/herobrine/build.mk
new file mode 100644
index 0000000000..67c2e2143f
--- /dev/null
+++ b/baseboard/herobrine/build.mk
@@ -0,0 +1,11 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Baseboard specific files build
+#
+
+baseboard-y+=baseboard.o
+baseboard-y+=usbc_config.o
+baseboard-y+=usb_pd_policy.o
diff --git a/baseboard/herobrine/usb_pd_policy.c b/baseboard/herobrine/usb_pd_policy.c
new file mode 100644
index 0000000000..9fa725c845
--- /dev/null
+++ b/baseboard/herobrine/usb_pd_policy.c
@@ -0,0 +1,259 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "chipset.h"
+#include "console.h"
+#include "gpio.h"
+#include "system.h"
+#include "usb_mux.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+int pd_check_vconn_swap(int port)
+{
+	/* In G3, do not allow vconn swap since PP5000 rail is off */
+	return gpio_get_level(GPIO_EN_PP5000);
+}
+
+static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT];
+#if CONFIG_USB_PD_PORT_MAX_COUNT == 1
+static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5 };
+#else
+static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5,
+							 TYPEC_RP_1A5 };
+#endif
+
+static void board_vbus_update_source_current(int port)
+{
+	/* Both port are controlled by PPC SN5S330. */
+	ppc_set_vbus_source_current_limit(port, vbus_rp[port]);
+	ppc_vbus_source_enable(port, vbus_en[port]);
+}
+
+void pd_power_supply_reset(int port)
+{
+	int prev_en;
+
+	prev_en = vbus_en[port];
+
+	/* Disable VBUS */
+	vbus_en[port] = 0;
+	board_vbus_update_source_current(port);
+
+	/* Enable discharge if we were previously sourcing 5V */
+	if (prev_en)
+		pd_set_vbus_discharge(port, 1);
+
+	/* notify host of power info change */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	/* Disable charging */
+	board_vbus_sink_enable(port, 0);
+
+	pd_set_vbus_discharge(port, 0);
+
+	/* Provide VBUS */
+	vbus_en[port] = 1;
+	board_vbus_update_source_current(port);
+
+	/* notify host of power info change */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS; /* we are ready */
+}
+
+int board_vbus_source_enabled(int port)
+{
+	return vbus_en[port];
+}
+
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	vbus_rp[port] = rp;
+	board_vbus_update_source_current(port);
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	return tcpm_check_vbus_level(port, VBUS_PRESENT);
+}
+
+/* ----------------- Vendor Defined Messages ------------------ */
+#ifdef CONFIG_USB_PD_ALT_MODE_DFP
+__override int svdm_dp_config(int port, uint32_t *payload)
+{
+	int opos = pd_alt_mode(port, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT);
+	uint8_t pin_mode = get_dp_pin_mode(port);
+
+	if (!pin_mode)
+		return 0;
+
+	/*
+	 * Defer setting the usb_mux until HPD goes high, svdm_dp_attention().
+	 * The AP only supports one DP phy. An external DP mux switches between
+	 * the two ports. Should switch those muxes when it is really used,
+	 * i.e. HPD high; otherwise, the real use case is preempted, like:
+	 *  (1) plug a dongle without monitor connected to port-0,
+	 *  (2) plug a dongle without monitor connected to port-1,
+	 *  (3) plug a monitor to the port-1 dongle.
+	 */
+
+	payload[0] =
+		VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_CONFIG | VDO_OPOS(opos));
+	payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */
+				1, /* DPv1.3 signaling */
+				2); /* UFP connected */
+	return 2;
+};
+
+__override void svdm_dp_post_config(int port)
+{
+	dp_flags[port] |= DP_FLAGS_DP_ON;
+}
+
+/**
+ * Is the port fine to be muxed its DisplayPort lines?
+ *
+ * Only one port can be muxed to DisplayPort at a time.
+ *
+ * @param port	Port number of TCPC.
+ * @return	1 is fine; 0 is bad as other port is already muxed;
+ */
+static int is_dp_muxable(int port)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
+		if (i != port) {
+			if (usb_mux_get(i) & USB_PD_MUX_DP_ENABLED)
+				return 0;
+		}
+
+	return 1;
+}
+
+__override int svdm_dp_attention(int port, uint32_t *payload)
+{
+	enum gpio_signal hpd = GPIO_DP_HOT_PLUG_DET;
+	int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]);
+	int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]);
+	int cur_lvl = gpio_get_level(hpd);
+	mux_state_t mux_state;
+
+	dp_status[port] = payload[1];
+
+	if (!is_dp_muxable(port)) {
+		/* TODO(waihong): Info user? */
+		CPRINTS("p%d: The other port is already muxed.", port);
+		return 0;
+	}
+
+	/*
+	 * Initial implementation to handle HPD. Only the first-plugged port
+	 * works, i.e. sending HPD signal to AP. The second-plugged port
+	 * will be ignored.
+	 *
+	 * TODO(waihong): Continue the above case, if the first-plugged port
+	 * is then unplugged, switch to the second-plugged port and signal AP?
+	 */
+	if (lvl) {
+		/*
+		 * Enable and switch the DP port selection mux to the
+		 * correct port.
+		 *
+		 * TODO(waihong): Better to move switching DP mux to
+		 * the usb_mux abstraction.
+		 */
+		gpio_set_level(GPIO_DP_MUX_SEL, port == 1);
+		gpio_set_level(GPIO_DP_MUX_OE_L, 0);
+
+		/* Connect the SBU lines in PPC chip. */
+		if (IS_ENABLED(CONFIG_USBC_PPC_SBU))
+			ppc_set_sbu(port, 1);
+
+		/*
+		 * Connect the USB SS/DP lines in TCPC chip.
+		 *
+		 * When mf_pref not true, still use the dock muxing
+		 * because of the board USB-C topology (limited to 2
+		 * lanes DP).
+		 */
+		usb_mux_set(port, USB_PD_MUX_DOCK, USB_SWITCH_CONNECT,
+			    polarity_rm_dts(pd_get_polarity(port)));
+	} else {
+		/* Disconnect the DP port selection mux. */
+		gpio_set_level(GPIO_DP_MUX_OE_L, 1);
+		gpio_set_level(GPIO_DP_MUX_SEL, 0);
+
+		/* Disconnect the SBU lines in PPC chip. */
+		if (IS_ENABLED(CONFIG_USBC_PPC_SBU))
+			ppc_set_sbu(port, 0);
+
+		/* Disconnect the DP but keep the USB SS lines in TCPC chip. */
+		usb_mux_set(port, USB_PD_MUX_USB_ENABLED, USB_SWITCH_CONNECT,
+			    polarity_rm_dts(pd_get_polarity(port)));
+	}
+
+	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && (irq || lvl))
+		/*
+		 * Wake up the AP.  IRQ or level high indicates a DP sink is now
+		 * present.
+		 */
+		pd_notify_dp_alt_mode_entry(port);
+
+	/* Configure TCPC for the HPD event, for proper muxing */
+	mux_state = (lvl ? USB_PD_MUX_HPD_LVL : USB_PD_MUX_HPD_LVL_DEASSERTED) |
+		    (irq ? USB_PD_MUX_HPD_IRQ : USB_PD_MUX_HPD_IRQ_DEASSERTED);
+	usb_mux_hpd_update(port, mux_state);
+
+	/* Signal AP for the HPD event, through GPIO to AP */
+	if (irq & cur_lvl) {
+		uint64_t now = get_time().val;
+		/* Wait for the minimum spacing between IRQ_HPD if needed */
+		if (now < svdm_hpd_deadline[port])
+			usleep(svdm_hpd_deadline[port] - now);
+
+		/* Generate IRQ_HPD pulse */
+		gpio_set_level(hpd, 0);
+		usleep(HPD_DSTREAM_DEBOUNCE_IRQ);
+		gpio_set_level(hpd, 1);
+
+		/* Set the minimum time delay (2ms) for the next HPD IRQ */
+		svdm_hpd_deadline[port] =
+			get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
+	} else if (irq & !lvl) {
+		CPRINTF("ERR:HPD:IRQ&LOW\n");
+		return 0;
+	} else {
+		gpio_set_level(hpd, lvl);
+		/* Set the minimum time delay (2ms) for the next HPD IRQ */
+		svdm_hpd_deadline[port] =
+			get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
+	}
+
+	return 1;
+}
+
+__override void svdm_exit_dp_mode(int port)
+{
+	if (is_dp_muxable(port)) {
+		/* Disconnect the DP port selection mux. */
+		gpio_set_level(GPIO_DP_MUX_OE_L, 1);
+		gpio_set_level(GPIO_DP_MUX_SEL, 0);
+
+		/* Signal AP for the HPD low event */
+		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+		gpio_set_level(GPIO_DP_HOT_PLUG_DET, 0);
+	}
+}
+#endif /* CONFIG_USB_PD_ALT_MODE_DFP */
diff --git a/baseboard/herobrine/usbc_config.c b/baseboard/herobrine/usbc_config.c
new file mode 100644
index 0000000000..a5df0a0d4c
--- /dev/null
+++ b/baseboard/herobrine/usbc_config.c
@@ -0,0 +1,61 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Herobrine family-specific USB-C configuration */
+
+#include "charge_state.h"
+#include "charger.h"
+#include "charger/isl923x_public.h"
+#include "console.h"
+#include "usb_pd.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+};
+
+int charger_profile_override(struct charge_state_data *curr)
+{
+	int usb_mv;
+	int port;
+
+	if (curr->state != ST_CHARGE)
+		return 0;
+
+	/* Lower the max requested voltage to 5V when battery is full. */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
+	    !(curr->batt.flags & BATT_FLAG_BAD_STATUS) &&
+	    !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
+	    (curr->batt.status & STATUS_FULLY_CHARGED))
+		usb_mv = 5000;
+	else
+		usb_mv = PD_MAX_VOLTAGE_MV;
+
+	if (pd_get_max_voltage() != usb_mv) {
+		CPRINTS("VBUS limited to %dmV", usb_mv);
+		for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++)
+			pd_set_external_voltage_limit(port, usb_mv);
+	}
+
+	return 0;
+}
+
+enum ec_status charger_profile_override_get_param(uint32_t param,
+						  uint32_t *value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+enum ec_status charger_profile_override_set_param(uint32_t param,
+						  uint32_t value)
+{
+	return EC_RES_INVALID_PARAM;
+}
diff --git a/baseboard/honeybuns/baseboard.c b/baseboard/honeybuns/baseboard.c
index bb0a1c832d..430eb488e7 100644
--- a/baseboard/honeybuns/baseboard.c
+++ b/baseboard/honeybuns/baseboard.c
@@ -1,48 +1,492 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Honeybuns family-specific configuration */
 #include "console.h"
+#include "cros_board_info.h"
+#include "driver/mp4245.h"
+#include "driver/tcpm/tcpm.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "i2c.h"
+#include "system.h"
+#include "task.h"
 #include "timer.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+#include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
-/******************************************************************************/
-__overridable const struct power_seq board_power_seq[] = { };
+#define POWER_BUTTON_SHORT_USEC (300 * MSEC)
+#define POWER_BUTTON_LONG_USEC (5000 * MSEC)
+#define POWER_BUTTON_DEBOUNCE_USEC (30)
+
+#define BUTTON_EVT_CHANGE BIT(0)
+#define BUTTON_EVT_INFO BIT(1)
+
+enum power { POWER_OFF, POWER_ON };
 
-__overridable const size_t board_power_seq_count =
-	ARRAY_SIZE(board_power_seq);
+enum button {
+	BUTTON_RELEASE,
+	BUTTON_PRESS,
+	BUTTON_PRESS_POWER_ON,
+	BUTTON_PRESS_SHORT,
+	BUTTON_PRESS_LONG,
+};
+
+#define LED_ON_OFF_BIT BIT(0)
+#define LED_COLOR_BIT BIT(2)
+#define LED_FLASH_SEQ_LENGTH 8
 
-static void board_power_sequence(void)
+enum led_color {
+	GREEN,
+	YELLOW,
+	OFF,
+};
+
+static enum power dock_state;
+#ifdef SECTION_IS_RW
+static int button_level;
+static int button_level_pending;
+static int dock_mf;
+static int led_count;
+#endif
+
+/******************************************************************************/
+
+__maybe_unused static void board_power_sequence(int enable)
 {
 	int i;
 
-	for(i = 0; i < board_power_seq_count; i++) {
-		gpio_set_level(board_power_seq[i].signal,
-			       board_power_seq[i].level);
-		msleep(board_power_seq[i].delay_ms);
+	if (enable) {
+		for (i = 0; i < board_power_seq_count; i++) {
+			gpio_set_level(board_power_seq[i].signal,
+				       board_power_seq[i].level);
+			CPRINTS("power seq: rail = %d", i);
+			if (board_power_seq[i].delay_ms)
+				msleep(board_power_seq[i].delay_ms);
+		}
+	} else {
+		for (i = board_power_seq_count - 1; i >= 0; i--) {
+			gpio_set_level(board_power_seq[i].signal,
+				       !board_power_seq[i].level);
+			CPRINTS("sequence[%d]: level = %d", i,
+				!board_power_seq[i].level);
+		}
 	}
+
+	dock_state = enable;
+	CPRINTS("board: Power rails %s", dock_state ? "on" : "off");
 }
 
 /******************************************************************************/
 /* I2C port map configuration */
 const struct i2c_port_t i2c_ports[] = {
-	{"usbc",   I2C_PORT_USBC,   400, GPIO_EC_I2C1_SCL, GPIO_EC_I2C1_SDA},
-	{"usb_mst",  I2C_PORT_MST,  400, GPIO_EC_I2C2_SCL, GPIO_EC_I2C2_SDA},
-	{"eeprom",  I2C_PORT_EEPROM,  400, GPIO_EC_I2C3_SCL, GPIO_EC_I2C3_SDA},
+	{ .name = "i2c1",
+	  .port = I2C_PORT_I2C1,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C1_SCL,
+	  .sda = GPIO_EC_I2C1_SDA },
+	{ .name = "i2c3",
+	  .port = I2C_PORT_I2C3,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C3_SCL,
+	  .sda = GPIO_EC_I2C3_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
+#ifdef SECTION_IS_RW
+static void baseboard_set_led(enum led_color color)
+{
+	/*
+	 * TODO(b/164157329): The power button feature should be connected to a
+	 * 2 color LED which is part of the button. Currently, the power button
+	 * LED is a single color LED which is controlled by on the of the power
+	 * rails. Using the status LED now to demonstrate the LED behavior
+	 * associated with a power button press.
+	 */
+	CPRINTS("led: color = %d", color);
+
+	/* Not all boards may have LEDs under EC control */
+#if defined(GPIO_PWR_BUTTON_RED) && defined(GPIO_PWR_BUTTON_GREEN)
+	if (color == OFF) {
+		gpio_set_level(GPIO_PWR_BUTTON_RED, 1);
+		gpio_set_level(GPIO_PWR_BUTTON_GREEN, 1);
+	} else if (color == GREEN) {
+		gpio_set_level(GPIO_PWR_BUTTON_RED, 1);
+		gpio_set_level(GPIO_PWR_BUTTON_GREEN, 0);
+	} else if (color == YELLOW) {
+		gpio_set_level(GPIO_PWR_BUTTON_RED, 0);
+		gpio_set_level(GPIO_PWR_BUTTON_GREEN, 0);
+	}
+#endif
+}
+
+static void baseboard_led_callback(void);
+DECLARE_DEFERRED(baseboard_led_callback);
+
+static void baseboard_led_callback(void)
+{
+	/*
+	 * Flash LED on transition using a simple 3 bit counter. Bit 0 controls
+	 * LED on/off and bit 2 controls which color to set during the on phase.
+	 */
+	int color = led_count & LED_COLOR_BIT ? dock_mf : dock_mf ^ 1;
+
+	/*
+	 * TODO(b/164157329): This function implements a simple flashing
+	 * transition when the MF preference bit is changed via a long power
+	 * button press sequence. This might need to move to the board function
+	 * if not required/desired on all variants.
+	 */
+
+	if (led_count & LED_ON_OFF_BIT)
+		baseboard_set_led(color);
+	else
+		baseboard_set_led(OFF);
+
+	/* Flash sequence is 8 steps */
+	if (++led_count < LED_FLASH_SEQ_LENGTH)
+		hook_call_deferred(&baseboard_led_callback_data, 150 * MSEC);
+}
+
+static void baseboard_change_mf_led(void)
+{
+	led_count = 0;
+	baseboard_led_callback();
+}
+
+void baseboard_set_mst_lane_control(int mf)
+{
+	/*
+	 * The parameter mf reflects the desired lane control value. If the
+	 * current value does not match the desired, then the MST hub must first
+	 * be put into reset, so the MST hub will latch in the correct value
+	 * when it's taken out of reset.
+	 */
+	if (mf != gpio_get_level(GPIO_MST_HUB_LANE_SWITCH)) {
+		/* put MST into reset */
+		gpio_set_level(GPIO_MST_RST_L, 0);
+		msleep(1);
+		gpio_set_level(GPIO_MST_HUB_LANE_SWITCH, mf);
+		CPRINTS("MST: lane control = %s", mf ? "high" : "low");
+		msleep(1);
+		/* lane control is set, take MST out of reset */
+		gpio_set_level(GPIO_MST_RST_L, 1);
+	}
+}
+
+static void baseboard_enable_mp4245(void)
+{
+	int mv;
+	int ma;
+
+	mp4245_set_voltage_out(5000);
+	mp4245_votlage_out_enable(1);
+	msleep(MP4245_VOUT_5V_DELAY_MS);
+	mp3245_get_vbus(&mv, &ma);
+	CPRINTS("mp4245: vout @ %d mV enabled", mv);
+}
+
+#endif /* SECTION_IS_RW */
+
 static void baseboard_init(void)
 {
+#ifdef SECTION_IS_RW
+	uint32_t fw_config;
+#endif
+
 	/* Turn on power rails */
-	board_power_sequence();
+	board_power_sequence(1);
 	CPRINTS("board: Power rails enabled");
+
+#ifdef SECTION_IS_RW
+	/* Force TC state machine to start in TC_ERROR_RECOVERY */
+	system_clear_reset_flags(EC_RESET_FLAG_POWER_ON);
+	/* Make certain SN5S330 PPC does full initialization */
+	system_set_reset_flags(EC_RESET_FLAG_EFS);
+
+	/*
+	 * Dock multi function (mf) preference is stored in bit 0 of fw_config
+	 * field of the CBI. If this value is programmed, then make sure the
+	 * MST_LANE_CONTROL gpio matches the mf bit.
+	 */
+	if (!cbi_get_fw_config(&fw_config)) {
+		dock_mf = CBI_FW_MF_PREFERENCE(fw_config);
+		baseboard_set_mst_lane_control(dock_mf);
+	} else {
+		dock_mf = dock_get_mf_preference();
+		cbi_set_fw_config(dock_mf);
+		CPRINTS("cbi: setting default result = %s",
+			cbi_get_fw_config(&fw_config) ? "pass" : "fail");
+	}
+
+#ifdef GPIO_USBC_UF_ATTACHED_SRC
+	/* Configure UF usbc ppc and check usbc state */
+	baseboard_config_usbc_usb3_ppc();
+#endif /* GPIO_USBC_UF_ATTACHED_SRC */
+
+	/* Enable power button interrupt */
+	gpio_enable_interrupt(GPIO_PWR_BTN);
+	/* Set dock mf preference LED */
+	baseboard_set_led(dock_mf);
+	/* Setup VBUS to default value */
+	baseboard_enable_mp4245();
+
+#else
+	/* Set up host port usbc to present Rd on CC lines */
+	if (baseboard_usbc_init(USB_PD_PORT_HOST))
+		CPRINTS("usbc: Failed to set up sink path");
+	else
+		CPRINTS("usbc: sink path configure success!");
+#endif /* SECTION_IS_RW */
 }
-DECLARE_HOOK(HOOK_INIT, baseboard_init, HOOK_PRIO_DEFAULT);
+/*
+ * Power sequencing must run before any other chip init is attempted, so run
+ * power sequencing as soon as I2C bus is initialized.
+ */
+DECLARE_HOOK(HOOK_INIT, baseboard_init, HOOK_PRIO_INIT_I2C + 1);
+
+#ifdef SECTION_IS_RW
+static void baseboard_power_on(void)
+{
+	int port_max = board_get_usb_pd_port_count();
+	int port;
+
+	CPRINTS("pwrbtn: power on: mf = %d", dock_mf);
+	/* Adjust system flags to full PPC init occurs */
+	system_clear_reset_flags(EC_RESET_FLAG_POWER_ON);
+	system_set_reset_flags(EC_RESET_FLAG_EFS);
+	/* Enable power rails and release reset signals */
+	board_power_sequence(1);
+	/* Set VBUS to 5V and enable output from mp4245 */
+	baseboard_enable_mp4245();
+	/* Set dock mf preference LED */
+	baseboard_set_led(dock_mf);
+	/*
+	 * Lane control (realtek MST) must be set prior to releasing MST
+	 * reset.
+	 */
+	baseboard_set_mst_lane_control(dock_mf);
+	/*
+	 * When the power to the PPC is turned off, then back on, the PPC will
+	 * default into dead battery mode. Dead battery resistors are disabled
+	 * as part of the full PPC intializaiton sequence. This is required to
+	 * force a detach event with port parter which can be attached as usbc
+	 * source when honeybuns power rails are off.
+	 */
+	for (port = 0; port < port_max; port++) {
+		ppc_init(port);
+		msleep(1000);
+		/* Inform TC state machine that it can resume */
+		pd_set_suspend(port, 0);
+	}
+	/* Enable usbc interrupts */
+	board_enable_usbc_interrupts();
+
+#ifdef GPIO_USBC_UF_ATTACHED_SRC
+	baseboard_config_usbc_usb3_ppc();
+#endif
+}
+
+static void baseboard_power_off(void)
+{
+	int port_max = board_get_usb_pd_port_count();
+	int port;
+
+	CPRINTS("pwrbtn: power off");
+	/* Put ports in TC suspend state */
+	for (port = 0; port < port_max; port++)
+		pd_set_suspend(port, 1);
+
+	/* Disable ucpd peripheral (prevents interrupts) */
+	tcpm_release(USB_PD_PORT_HOST);
+	/* Disable PPC/TCPC interrupts */
+	board_disable_usbc_interrupts();
+
+#ifdef GPIO_USBC_UF_ATTACHED_SRC
+	/* Disable PPC interrupts for PS8803 managed port */
+	baseboard_usbc_usb3_enable_interrupts(0);
+#endif
+	/* Set dock power button/MF preference LED */
+	baseboard_set_led(OFF);
+	/* Go into power off state */
+	board_power_sequence(0);
+}
+
+static void baseboard_toggle_mf(void)
+{
+	uint32_t fw_config;
+
+	if (!cbi_get_fw_config(&fw_config)) {
+		/* Update the user MF preference stored in CBI */
+		fw_config ^= CBI_FW_MF_MASK;
+		cbi_set_fw_config(fw_config);
+		/* Update variable used to track user MF preference */
+		dock_mf = CBI_FW_MF_PREFERENCE(fw_config);
+		/* Flash led for visual indication of user MF change */
+		baseboard_change_mf_led();
+
+		/*
+		 * Suspend, then release host port to force new MF setting to
+		 * take effect.
+		 */
+		pd_set_suspend(USB_PD_PORT_HOST, 1);
+		msleep(250);
+		pd_set_suspend(USB_PD_PORT_HOST, 0);
+	}
+}
+
+/*
+ * Main task entry point for UCPD task
+ */
+void power_button_task(void *u)
+{
+	int timer_us = POWER_BUTTON_DEBOUNCE_USEC * 4;
+	enum button state = BUTTON_RELEASE;
+	uint32_t evt;
+
+	/*
+	 * Capture current button level in case it's being pressed when the dock
+	 * is powered on. Note timer_us is initialized for debounce time to
+	 * double check.
+	 */
+	button_level = gpio_get_level(GPIO_PWR_BTN);
+
+	while (1) {
+		evt = task_wait_event(timer_us);
+		timer_us = -1;
+
+		if (evt == BUTTON_EVT_INFO) {
+			/* Only used for console command for debug */
+			CPRINTS("pwrbtn: pwr = %d, state = %d, level = %d",
+				dock_state, state, button_level);
+			continue;
+		}
+
+		switch (state) {
+		case BUTTON_RELEASE:
+			/*
+			 * Default wait state: Only need to check if the button
+			 * is pressed and start the short press timer.
+			 */
+			if (evt & BUTTON_EVT_CHANGE &&
+			    button_level == BUTTON_PRESSED_LEVEL) {
+				state = BUTTON_PRESS;
+				timer_us = (POWER_BUTTON_SHORT_USEC -
+					    POWER_BUTTON_DEBOUNCE_USEC);
+			}
+			break;
+		case BUTTON_PRESS:
+			/*
+			 * Validate short press by ensuring that button is still
+			 * pressed after short press timer expires.
+			 */
+			if (evt & BUTTON_EVT_CHANGE &&
+			    button_level == BUTTON_RELEASED_LEVEL) {
+				state = BUTTON_RELEASE;
+			} else {
+				/* Start long press timer */
+				timer_us = POWER_BUTTON_LONG_USEC -
+					   POWER_BUTTON_SHORT_USEC;
+				/*
+				 * If dock is currently off, then change to the
+				 * power on state. If dock is already on, then
+				 * advance to short press state.
+				 */
+				if (dock_state == POWER_OFF) {
+					baseboard_power_on();
+					state = BUTTON_PRESS_POWER_ON;
+				} else {
+					state = BUTTON_PRESS_SHORT;
+				}
+			}
+			break;
+		case BUTTON_PRESS_POWER_ON:
+			/*
+			 * Short press recognized and dock was just powered
+			 * on. If button is no longer pressed, then just return
+			 * to the default state. Else, button is still pressed
+			 * after long press timer has expired.
+			 */
+			if (evt & BUTTON_EVT_CHANGE &&
+			    button_level == BUTTON_RELEASED_LEVEL) {
+				state = BUTTON_RELEASE;
+			} else {
+				state = BUTTON_PRESS_LONG;
+				baseboard_toggle_mf();
+			}
+			break;
+		case BUTTON_PRESS_SHORT:
+			/*
+			 * Short press was recognized and dock power state was
+			 * already on. If button is now released, then turn dock
+			 * off.
+			 */
+			if (evt & BUTTON_EVT_CHANGE &&
+			    button_level == BUTTON_RELEASED_LEVEL) {
+				state = BUTTON_RELEASE;
+				baseboard_power_off();
+			} else {
+				state = BUTTON_PRESS_LONG;
+				baseboard_toggle_mf();
+			}
+			break;
+		case BUTTON_PRESS_LONG:
+			if (evt & BUTTON_EVT_CHANGE &&
+			    button_level == BUTTON_RELEASED_LEVEL) {
+				state = BUTTON_RELEASE;
+			}
+			break;
+		}
+	}
+}
+
+static void baseboard_power_button_debounce(void)
+{
+	int level = gpio_get_level(GPIO_PWR_BTN);
+
+	/* Sanity check, level should be same after debounce interval */
+	if (level != button_level_pending)
+		return;
+
+	button_level = level;
+	task_set_event(TASK_ID_POWER_BUTTON, BUTTON_EVT_CHANGE);
+}
+DECLARE_DEFERRED(baseboard_power_button_debounce);
+
+void baseboard_power_button_evt(int level)
+{
+	button_level_pending = level;
+
+	hook_call_deferred(&baseboard_power_button_debounce_data,
+			   POWER_BUTTON_DEBOUNCE_USEC);
+}
+
+static int command_pwr_btn(int argc, const char **argv)
+{
+	if (argc == 1) {
+		task_set_event(TASK_ID_POWER_BUTTON, BUTTON_EVT_INFO);
+		return EC_SUCCESS;
+	}
+
+	if (!strcasecmp(argv[1], "on")) {
+		baseboard_power_on();
+	} else if (!strcasecmp(argv[1], "off")) {
+		baseboard_power_off();
+	} else if (!strcasecmp(argv[1], "mf")) {
+		baseboard_toggle_mf();
+	} else {
+		return EC_ERROR_PARAM1;
+	}
+
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(pwr_btn, command_pwr_btn, "<on|off|mf>",
+			"Simulate Power Button Press");
+
+#endif
diff --git a/baseboard/honeybuns/baseboard.h b/baseboard/honeybuns/baseboard.h
index 0703ea0b33..a2dc18ccdb 100644
--- a/baseboard/honeybuns/baseboard.h
+++ b/baseboard/honeybuns/baseboard.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,14 +11,58 @@
 /* EC Defines */
 #define CONFIG_CRC8
 
-/* TODO Define FLASH_PSTATE_LOCKED prior to building MP FW. */
-#undef CONFIG_FLASH_PSTATE_LOCKED
+/* Flash Lyaout */
+/*
+ * Flash layout: we redefine the sections offsets and sizes as we will use
+ * RO/RW regions of different sizes.
+ */
+#undef _IMAGE_SIZE
+#undef CONFIG_ROLLBACK_OFF
+#undef CONFIG_ROLLBACK_SIZE
+#undef CONFIG_FLASH_PSTATE
+#undef CONFIG_FW_PSTATE_SIZE
+#undef CONFIG_FW_PSTATE_OFF
+#undef CONFIG_SHAREDLIB_SIZE
+#undef CONFIG_RO_MEM_OFF
+#undef CONFIG_RO_STORAGE_OFF
+#undef CONFIG_RO_SIZE
+#undef CONFIG_RW_MEM_OFF
+#undef CONFIG_RW_STORAGE_OFF
+#undef CONFIG_RW_SIZE
+#undef CONFIG_EC_PROTECTED_STORAGE_OFF
+#undef CONFIG_EC_PROTECTED_STORAGE_SIZE
+#undef CONFIG_EC_WRITABLE_STORAGE_OFF
+#undef CONFIG_EC_WRITABLE_STORAGE_SIZE
+#undef CONFIG_WP_STORAGE_OFF
+#undef CONFIG_WP_STORAGE_SIZE
+
+#define CONFIG_FLASH_PSTATE
+/* Do not use a dedicated PSTATE bank */
+#undef CONFIG_FLASH_PSTATE_BANK
+
+#define CONFIG_SHAREDLIB_SIZE 0
+
+#define CONFIG_RO_MEM_OFF 0
+#define CONFIG_RO_STORAGE_OFF 0
+#define CONFIG_RO_SIZE (64 * 1024)
+
+#define CONFIG_RW_MEM_OFF (CONFIG_RO_SIZE + CONFIG_RO_MEM_OFF)
+#define CONFIG_RW_STORAGE_OFF 0
+#define CONFIG_RW_SIZE \
+	(CONFIG_FLASH_SIZE_BYTES - (CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF))
+
+#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF
+#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE
+#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE
+
+#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
+#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
 
 /* 48 MHz SYSCLK clock frequency */
 #define CPU_CLOCK 48000000
-#define CONFIG_STM_HWTIMER32
 #define TIM_CLOCK32 2
-#define TIM_CLOCK_MSB  3
+#define TIM_CLOCK_MSB 3
 #define TIM_CLOCK_LSB 15
 #define TIM_WATCHDOG 7
 
@@ -35,23 +79,135 @@
 #define CONFIG_UART_TX_DMA_PH DMAMUX_REQ_USART3_TX
 
 /* CBI Configs */
-#define I2C_ADDR_EEPROM_FLAGS   0x50
-#define CONFIG_CROS_BOARD_INFO
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+#define CONFIG_CBI_EEPROM
 #define CONFIG_BOARD_VERSION_CBI
 #define CONFIG_CMD_CBI
+#define CONFIG_EEPROM_CBI_WP
+#define CONFIG_BYPASS_CBI_EEPROM_WP_CHECK
+#define GPIO_EC_CBI_WP GPIO_EC_FLASH_WP_ODL
+#define CBI_FW_MF_MASK BIT(0)
+#define CBI_FW_MF_PREFERENCE(val) (val & (CBI_FW_MF_MASK))
 
+/* USB Configuration */
+#define CONFIG_USB
+#define CONFIG_STREAM_USB
+#define CONFIG_USB_UPDATE
+#define CONFIG_USB_SERIALNO
+#define DEFAULT_SERIALNO "Uninitialized"
+#define CONFIG_MAC_ADDR
+#define DEFAULT_MAC_ADDR "Uninitialized"
+#define CONFIG_USB_MS_EXTENDED_COMPAT_ID_DESCRIPTOR
+
+/* USB endpoint indexes (use define rather than enum to expand them) */
+#define USB_EP_CONTROL 0
+#define USB_EP_UPDATE 1
+#define USB_EP_COUNT 2
+
+#define USB_IFACE_UPDATE 0
+#define USB_IFACE_COUNT 1
+
+#ifndef __ASSEMBLER__
+/* USB string indexes */
+enum usb_strings {
+	USB_STR_DESC = 0,
+	USB_STR_VENDOR,
+	USB_STR_PRODUCT,
+	USB_STR_SERIALNO,
+	USB_STR_VERSION,
+	USB_STR_UPDATE_NAME,
+	USB_STR_COUNT
+};
+#endif
+
+/* RW Specific Config Options */
+#ifdef SECTION_IS_RW
+/* No AP on any honeybuns variants */
+#undef CONFIG_USB_PD_HOST_CMD
 
 /* USB Type C and USB PD defines */
+#define CONFIG_USB_POWER_DELIVERY
+#define CONFIG_USB_PD_TCPMV2
+#define CONFIG_USB_DRP_ACC_TRYSRC
+#define CONFIG_USB_PD_ALT_MODE
+#define CONFIG_USB_PD_ALT_MODE_DFP
+#define CONFIG_USB_PD_CUSTOM_PDO
+#define CONFIG_USB_PD_ALT_MODE_UFP_DP
+#define CONFIG_USB_PD_DUAL_ROLE
+#define CONFIG_USB_PD_REV30
+/*
+ * Source current limit pull options. Honeybuns always wants TYPEC_RP_3A0
+ * current limits for the usbc host port (C0). For port C1, some variants are
+ * designed with a 1.5A current limit. This variation is handled via
+ * BOARD_C1_1A5_LIMIT which would be set in a variant's board.h file.
+ *
+ * CONFIG_USB_PD_3A_PORTS should be left at 0 as this will disable DPM from
+ * doing any dynamic current limit management.
+ */
+#undef CONFIG_USB_PD_PULLUP
+#define CONFIG_USB_PD_PULLUP TYPEC_RP_3A0
+#define CONFIG_USB_PD_3A_PORTS 0
+#define CONFIG_USB_PD_TCPM_MUX
+#define CONFIG_USB_PD_TCPM_PS8805
+#define CONFIG_USB_PD_TCPM_STM32GX
+#define CONFIG_USB_PD_TCPM_TCPCI
+#define CONFIG_USB_PD_DECODE_SOP
+#define CONFIG_USB_PD_VBUS_DETECT_PPC
+#define CONFIG_USB_PD_DISCHARGE_PPC
+#define CONFIG_USBC_PPC_SN5S330
+#define CONFIG_USBC_PPC_VCONN
+#define CONFIG_USBC_PPC_DEDICATED_INT
+#define CONFIG_USBC_VCONN
+#define CONFIG_USBC_VCONN_SWAP
+#define CONFIG_USBC_SS_MUX
+
+#define CONFIG_HAS_TASK_PD_INT
+#define CONFIG_STM32G4_UCPD_DEBUG
+#define CONFIG_CMD_PPC_DUMP
+#define CONFIG_CMD_TCPC_DUMP
+
+#define CONFIG_MP4245
+#define USB_HUB_OCP_RESET_MSEC (10 * MSEC)
+
+#else /* RO Specific Config Options */
+
+/* RWSIG Config Options */
+/* Sign and switch to RW partition on boot. */
+#define CONFIG_RWSIG
+#define CONFIG_RSA
+#define CONFIG_SHA256_UNROLLED
+#undef CONFIG_RWSIG_JUMP_TIMEOUT
+#define CONFIG_RWSIG_JUMP_TIMEOUT (7000 * MSEC)
+
+/* Don't build PD console command for RO */
+#undef CONFIG_CMD_PD
+#undef CONFIG_USB_PD_CONSOLE_CMD
+#undef CONFIG_USB_PD_HOST_CMD
+/* Make sure these files aren't built in RO */
+#undef CONFIG_USB_PRL_SM
+#undef CONFIG_USB_TYPEC_SM
+#undef CONFIG_USB_PE_SM
+
+#endif /* SECTION_IS_RW */
 
-/* BC 1.2 */
+#define CONFIG_RWSIG_TYPE_RWSIG
+#define CONFIG_RSA_KEY_SIZE 3072
+#define CONFIG_RSA_EXPONENT_3
+#define CONFIG_SHA256
+
+/* Define typical operating power and max power. */
+#define PD_MAX_VOLTAGE_MV 5000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_POWER_MW 15000
+#define PD_OPERATING_POWER_MW 15000
+
+/* TODO(b:147314141): Verify these timings */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* I2C Bus Configuration */
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
-#define I2C_PORT_USBC		0
-#define I2C_PORT_MST		1
-#define I2C_PORT_EEPROM	2
-
+#define CONFIG_I2C_CONTROLLER
 
 /*
  * Macros for GPIO signals used in common code that don't match the
@@ -59,8 +215,8 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_ENTERING_RW	GPIO_EC_ENTERING_RW
-#define GPIO_WP_L		GPIO_EC_WP_L
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_WP_L GPIO_EC_WP_L
 
 #ifndef __ASSEMBLER__
 
@@ -69,13 +225,103 @@
 
 struct power_seq {
 	enum gpio_signal signal; /* power/reset gpio_signal to control */
-	int level;               /* level to set in power sequence */
-	unsigned int delay_ms;   /* delay (in msec) after setting gpio_signal */
+	int level; /* level to set in power sequence */
+	unsigned int delay_ms; /* delay (in msec) after setting gpio_signal */
 };
 
+enum mf_preference {
+	MF_OFF = 0,
+	MF_ON,
+};
+
+/*
+ * This is required as adc_channel is included in adc.h which ends up being
+ * included when TCPMv2 functions are included
+ */
+enum adc_channel { ADC_CH_COUNT };
+
 extern const struct power_seq board_power_seq[];
 extern const size_t board_power_seq_count;
 
+void baseboard_power_button_evt(int level);
+
+/*
+ * Configure the host port to present Rd on both CC lines. This function is
+ * called in RO which does not otherwise have usbc/usb-pd support.
+ *
+ * @return true - initialized. false - not.
+ */
+int baseboard_usbc_init(int port);
+
+/*
+ * Get a board's desired multi-function (MF) prefernce. This allows for board
+ * specific policy.
+ *
+ * @return 1 if multi function (DP + USB3) is preferred, 0 otherwise
+ */
+int dock_get_mf_preference(void);
+
+/*
+ * Initialize and configure PPC used for USB3 only port
+ *
+ * @return EC success if PPC initialization is successful
+ */
+int baseboard_config_usbc_usb3_ppc(void);
+
+/*
+ * Called from interrupt handler for PS8803 attached.src gpio. This gpio signal
+ * will be set high by the PS8803 when it's in the attached.src state and low
+ * otherwise. For boards wich have a PPC on this port, this signal is used to
+ * enable/disable VBUS in the PPC.
+ */
+void baseboard_usb3_check_state(void);
+
+/*
+ * Set MST_LANE_CONTROL gpio to match the DP pin configuration selected
+ * by the host in the DP Configure SVDM message.
+ *
+ * @param dock_mf 1 -> 2 lanes DP, 0 -> 4 lanes DP
+ */
+void baseboard_set_mst_lane_control(int dock_mf);
+
+/*
+ * Control enable/disable for interrupts used for usb3 only usbc port.
+ *
+ * @param enable -> 1 for enable, 0 for disable
+ */
+void baseboard_usbc_usb3_enable_interrupts(int enable);
+
+/*
+ * Called from interrupt handler for PPC used on usb3 only port.
+ *
+ */
+void baseboard_usbc_usb3_irq(void);
+
+/**
+ * Determine if VBUS is present or not.
+ *
+ * @param port: The Type-C port number.
+ * @return 1 if VBUS is present, 0 if not.
+ */
+int c1_ps8805_is_vbus_present(int port);
+
+/**
+ * Is the port sourcing Vbus?
+ *
+ * @param port: The Type-C port number.
+ * @return 1 if sourcing Vbus, 0 if not.
+ */
+int c1_ps8805_is_sourcing_vbus(int port);
+
+/**
+ * Turn on/off VBUS for port C1
+ *
+ * @param port: The Type-C port number.
+ * @param enable: 1: Turn on VBUS, 0: turn off VBUS.
+ * @return EC_SUCCESS on success, error otherwise.
+ */
+int c1_ps8805_vbus_source_enable(int port, int enable);
+
 #endif /* !__ASSEMBLER__ */
 
 #endif /* __CROS_EC_BASEBOARD_H */
diff --git a/baseboard/honeybuns/build.mk b/baseboard/honeybuns/build.mk
index 2a572df114..57e93b0587 100644
--- a/baseboard/honeybuns/build.mk
+++ b/baseboard/honeybuns/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -7,3 +7,5 @@
 #
 
 baseboard-y=baseboard.o
+baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
+baseboard-y+=usbc_support.o
diff --git a/baseboard/honeybuns/usb_pd_policy.c b/baseboard/honeybuns/usb_pd_policy.c
new file mode 100644
index 0000000000..f2e13d9ed9
--- /dev/null
+++ b/baseboard/honeybuns/usb_pd_policy.c
@@ -0,0 +1,618 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "chip/stm32/ucpd-stm32gx.h"
+#include "common.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "driver/mp4245.h"
+#include "driver/tcpm/tcpci.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "task.h"
+#include "timer.h"
+#include "usb_common.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_dp_ufp.h"
+#include "usb_tc_sm.h"
+#include "usbc_ppc.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+#define MP4245_VOLTAGE_WINDOW BIT(2)
+#define MP4245_VOLTAGE_WINDOW_MASK (MP4245_VOLTAGE_WINDOW - 1)
+
+#define PDO_FIXED_FLAGS                                                   \
+	(PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP | PDO_FIXED_COMM_CAP | \
+	 PDO_FIXED_UNCONSTRAINED)
+
+/* Voltage indexes for the PDOs */
+enum volt_idx {
+	PDO_IDX_5V = 0,
+	PDO_IDX_9V = 1,
+	PDO_IDX_15V = 2,
+	PDO_IDX_20V = 3,
+	PDO_IDX_COUNT
+};
+
+/* PDOs */
+const uint32_t pd_src_host_pdo[] = {
+	[PDO_IDX_5V] = PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS),
+	[PDO_IDX_9V] = PDO_FIXED(9000, 3000, 0),
+	[PDO_IDX_15V] = PDO_FIXED(15000, 3000, 0),
+	[PDO_IDX_20V] = PDO_FIXED(20000, 3000, 0),
+};
+BUILD_ASSERT(ARRAY_SIZE(pd_src_host_pdo) == PDO_IDX_COUNT);
+
+#ifdef BOARD_C1_1A5_LIMIT
+const uint32_t pd_src_display_pdo[] = {
+	[PDO_IDX_5V] = PDO_FIXED(5000, 1500, PDO_FIXED_FLAGS),
+};
+#else
+const uint32_t pd_src_display_pdo[] = {
+	[PDO_IDX_5V] = PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS),
+};
+#endif
+
+const uint32_t pd_snk_pdo[] = {
+	[PDO_IDX_5V] = PDO_FIXED(5000, 0, PDO_FIXED_FLAGS),
+};
+const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
+
+static int src_host_pdo_cnt_override;
+
+#define PD_DR_SWAP_ATTEMPT_MAX 3
+static int pd_dr_swap_attempt_count[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+static int command_hostpdo(int argc, const char **argv)
+{
+	char *e;
+	int limit;
+
+	if (argc >= 2) {
+		limit = strtoi(argv[1], &e, 10);
+		if ((limit < 0) || (limit > PDO_IDX_COUNT))
+			return EC_ERROR_PARAM1;
+
+		src_host_pdo_cnt_override = limit;
+	}
+	ccprintf("src host pdo override = %d\n", src_host_pdo_cnt_override);
+
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(hostpdo, command_hostpdo, "<0|1|2|3|4>",
+			"Limit number of PDOs for C0");
+
+int dpm_get_source_pdo(const uint32_t **src_pdo, const int port)
+{
+	int pdo_cnt = 0;
+
+	if (port == USB_PD_PORT_HOST) {
+		*src_pdo = pd_src_host_pdo;
+		pdo_cnt = ARRAY_SIZE(pd_src_host_pdo);
+		/*
+		 * This override is only active via a console command. Only used
+		 * for debug to limit the level of VBUS offered to port partner
+		 * if desired. The console command only allows 0 ->
+		 * PDO_IDX_COUNT for this value.
+		 */
+		if (src_host_pdo_cnt_override)
+			pdo_cnt = src_host_pdo_cnt_override;
+	} else {
+		*src_pdo = pd_src_display_pdo;
+		pdo_cnt = ARRAY_SIZE(pd_src_display_pdo);
+	}
+
+	return pdo_cnt;
+}
+
+/*
+ * Default Port Discovery DR Swap Policy.
+ *
+ * 1) If port == 0 and port data role is DFP, transition to pe_drs_send_swap
+ * 2) If port == 1 and port data role is UFP, transition to pe_drs_send_swap
+ */
+__override bool port_discovery_dr_swap_policy(int port, enum pd_data_role dr,
+					      bool dr_swap_flag)
+{
+	/*
+	 * Port0: test if role is DFP
+	 * Port1: test if role is UFP
+	 */
+	enum pd_data_role role_test = (port == USB_PD_PORT_HOST) ? PD_ROLE_DFP :
+								   PD_ROLE_UFP;
+
+	/*
+	 * Request data role swap if not in the port's desired data role and if
+	 * the attempt count is less than the max allowed. This function is
+	 * called for each PE run once in a PD contract. If the port partner
+	 * rejects data role swap requests (eg compliance tester), want to limit
+	 * how many DR swap requests are attempted.
+	 */
+	if (dr == role_test &&
+	    (pd_dr_swap_attempt_count[port]++ < PD_DR_SWAP_ATTEMPT_MAX))
+		return true;
+
+	/* Do not perform a DR swap */
+	return false;
+}
+
+/*
+ * Default Port Discovery VCONN Swap Policy.
+ *
+ * 1) No need to Vconn swap.  This board does not require any cable information.
+ */
+__override bool port_discovery_vconn_swap_policy(int port, bool vconn_swap_flag)
+{
+	return false;
+}
+
+int pd_check_vconn_swap(int port)
+{
+	/*TODO: Dock is the Vconn source */
+	return 1;
+}
+
+void pd_power_supply_reset(int port)
+{
+	int prev_en;
+
+	if (port < 0 || port >= CONFIG_USB_PD_PORT_MAX_COUNT)
+		return;
+
+	if (IS_ENABLED(BOARD_C1_NO_PPC) && port) {
+		prev_en = c1_ps8805_is_sourcing_vbus(port);
+		/* Disable VBUS via PPC. */
+		c1_ps8805_vbus_source_enable(port, 0);
+	} else {
+		prev_en = ppc_is_sourcing_vbus(port);
+		/* Disable VBUS via PPC. */
+		ppc_vbus_source_enable(port, 0);
+	}
+
+	/* Enable discharge if we were previously sourcing 5V */
+	if (prev_en)
+		pd_set_vbus_discharge(port, 1);
+
+	if (port == USB_PD_PORT_HOST) {
+		int mv;
+		int ma;
+		int unused_mv;
+
+		/*
+		 * Because VBUS on C0 is turned on/off via the PPC, the
+		 * voltage from the mp4245 does not need to be turned off, or
+		 * set to 0V. Instead, reset VBUS voltage to default value
+		 * (fixed 5V SRC_CAP) so VBUS is ready to be applied at the next
+		 * attached.src condition.
+		 */
+		pd_extract_pdo_power(pd_src_host_pdo[0], &ma, &mv, &unused_mv);
+		mp4245_set_voltage_out(mv);
+		/* Ensure voltage is back to 5V */
+		pd_transition_voltage(1);
+	}
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	/*
+	 * Note: For host port, the mp4245 output voltage is set for 5V by
+	 * default and each time VBUS is turned off. VOUT from the mp4245 is
+	 * left enabled as there is a switch (either PPC or discrete) to turn
+	 * VBUS on/off on the wire.
+	 */
+	if (IS_ENABLED(BOARD_C1_NO_PPC) && port)
+		rv = c1_ps8805_vbus_source_enable(port, 1);
+	else
+		rv = ppc_vbus_source_enable(port, 1);
+
+	if (rv)
+		return rv;
+
+	return EC_SUCCESS;
+}
+
+void pd_transition_voltage(int idx)
+{
+	int port = TASK_ID_TO_PD_PORT(task_get_current());
+	int mv;
+	int target_mv;
+	int mv_average = 0;
+	int ma;
+	int vbus_hi;
+	int vbus_lo;
+	int i;
+	int mv_buffer[MP4245_VOLTAGE_WINDOW];
+
+	/* Only C0 can provide more than 5V */
+	if (port != USB_PD_PORT_HOST)
+		return;
+
+	/*
+	 * Set the VBUS output voltage and current limit to the values specified
+	 * by the PDO requested by sink. Note that USB PD uses idx = 1 for 1st
+	 * PDO of SRC_CAP which must always be 5V fixed supply.
+	 */
+	pd_extract_pdo_power(pd_src_host_pdo[idx - 1], &ma, &target_mv, &mv);
+
+	/* Initialize sample delay buffer */
+	for (i = 0; i < MP4245_VOLTAGE_WINDOW; i++)
+		mv_buffer[i] = 0;
+
+	/* Set VBUS level to value specified in the requested PDO */
+	mp4245_set_voltage_out(target_mv);
+	/* Wait for vbus to be within ~5% of its target value */
+	vbus_hi = target_mv + (target_mv >> 4);
+	vbus_lo = target_mv - (target_mv >> 4);
+
+	for (i = 0; i < 20; i++) {
+		/* Read current sample */
+		mv = 0;
+		mp3245_get_vbus(&mv, &ma);
+		/* Add new sample to cicrcular delay buffer */
+		mv_buffer[i & MP4245_VOLTAGE_WINDOW_MASK] = mv;
+		/*
+		 * Don't compute average until sample delay buffer is
+		 * full.
+		 */
+		if (i >= (MP4245_VOLTAGE_WINDOW_MASK)) {
+			int sum = 0;
+			int j;
+
+			/* Sum the voltage samples */
+			for (j = 0; j < MP4245_VOLTAGE_WINDOW; j++)
+				sum += mv_buffer[j];
+			/* Add rounding */
+			sum += MP4245_VOLTAGE_WINDOW / 2;
+			mv_average = sum / MP4245_VOLTAGE_WINDOW;
+			/*
+			 * Check if average is within the target
+			 * voltage range.
+			 */
+			if ((mv_average >= vbus_lo) &&
+			    (mv_average <= vbus_hi)) {
+				CPRINTS("usbc[%d]: VBUS to %d mV in %d steps",
+					port, target_mv, i);
+				return;
+			}
+		}
+
+		/*
+		 * The voltage ramp from 5V to 20V requires ~30
+		 * msec. The max loop count and this sleep time gives plenty
+		 * of time for this change.
+		 */
+		msleep(2);
+	}
+
+	CPRINTS("usbc[%d]: Vbus transition timeout: target = %d, measure = %d",
+		port, target_mv, mv_average);
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	if (IS_ENABLED(BOARD_C1_NO_PPC) && port)
+		return c1_ps8805_is_vbus_present(port);
+	else
+		return ppc_is_vbus_present(port);
+}
+
+__override bool pd_check_vbus_level(int port, enum vbus_level level)
+{
+	if (level == VBUS_PRESENT)
+		return pd_snk_is_vbus_provided(port);
+	else
+		return !pd_snk_is_vbus_provided(port);
+}
+
+int board_vbus_source_enabled(int port)
+{
+	if (IS_ENABLED(BOARD_C1_NO_PPC) && port)
+		return c1_ps8805_is_sourcing_vbus(port);
+	else
+		return ppc_is_sourcing_vbus(port);
+}
+
+void pd_set_input_current_limit(int port, uint32_t max_ma,
+				uint32_t supply_voltage)
+{
+}
+
+int pd_check_data_swap(int port, enum pd_data_role data_role)
+{
+	int swap = 0;
+
+	if (port == 0)
+		swap = (data_role == PD_ROLE_DFP);
+	else if (port == 1)
+		swap = (data_role == PD_ROLE_UFP);
+
+	return swap;
+}
+
+int pd_check_power_swap(int port)
+{
+	if (pd_get_power_role(port) == PD_ROLE_SINK)
+		return 1;
+
+	return 0;
+}
+
+#ifdef BOARD_C1_1A5_LIMIT
+__override int typec_get_default_current_limit_rp(int port)
+{
+	int rp = TYPEC_RP_USB;
+
+	if (port == USB_PD_PORT_HOST)
+		rp = TYPEC_RP_3A0;
+	else if (port == USB_PD_PORT_DP)
+		rp = TYPEC_RP_1A5;
+
+	return rp;
+}
+#endif
+
+static void usb_tc_connect(void)
+{
+	int port = TASK_ID_TO_PD_PORT(task_get_current());
+
+	/* Clear data role swap attempt counter at each usbc attach */
+	pd_dr_swap_attempt_count[port] = 0;
+
+	/*
+	 * The EC needs to indicate to the USB hub when the host port is
+	 * attached so that the USB-EP can be properly enumerated. GPIO_BPWR_DET
+	 * is used for this purpose.
+	 */
+	if (port == USB_PD_PORT_HOST)
+		gpio_set_level(GPIO_BPWR_DET, 1);
+}
+DECLARE_HOOK(HOOK_USB_PD_CONNECT, usb_tc_connect, HOOK_PRIO_DEFAULT);
+
+static void usb_tc_disconnect(void)
+{
+	int port = TASK_ID_TO_PD_PORT(task_get_current());
+
+	/* Only the host port disconnect is relevant */
+	if (port == USB_PD_PORT_HOST)
+		gpio_set_level(GPIO_BPWR_DET, 0);
+}
+DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, usb_tc_disconnect, HOOK_PRIO_DEFAULT);
+
+__override bool pd_can_charge_from_device(int port, const int pdo_cnt,
+					  const uint32_t *pdos)
+{
+	/*
+	 * This function is called to determine if this port can be charged by
+	 * the port partner. We always want to be a power role source, so always
+	 * return false.
+	 */
+
+	return false;
+}
+
+static int vdm_is_dp_enabled(int port)
+{
+	mux_state_t mux_state = usb_mux_get(port);
+
+	return !!(mux_state & USB_PD_MUX_DP_ENABLED);
+}
+
+/* ----------------- Vendor Defined Messages ------------------ */
+
+const uint32_t vdo_idh = VDO_IDH(0, /* data caps as USB host */
+				 1, /* data caps as USB device */
+				 IDH_PTYPE_HUB, /* UFP product type usbpd hub */
+				 1, /* supports alt modes */
+				 USB_VID_GOOGLE);
+
+static const uint32_t vdo_idh_rev30 = VDO_IDH_REV30(
+	0, /* Data caps as USB host     */
+	1, /* Data caps as USB device   */
+	IDH_PTYPE_HUB, 1, /* Supports alt modes */
+	IDH_PTYPE_DFP_UNDEFINED, USB_TYPEC_RECEPTACLE, USB_VID_GOOGLE);
+
+const uint32_t vdo_product = VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV);
+
+static const uint32_t vdo_ufp1 =
+	VDO_UFP1((VDO_UFP1_CAPABILITY_USB20 | VDO_UFP1_CAPABILITY_USB32),
+		 USB_TYPEC_RECEPTACLE, VDO_UFP1_ALT_MODE_RECONFIGURE,
+		 USB_R30_SS_U32_U40_GEN2);
+
+static int svdm_response_identity(int port, uint32_t *payload)
+{
+	int vdo_count;
+
+	/* Verify that SVID is PD SID */
+	if (PD_VDO_VID(payload[0]) != USB_SID_PD) {
+		return 0;
+	}
+
+	/* Cstat and Product VDOs don't depend on spec revision */
+	payload[VDO_INDEX_CSTAT] = VDO_CSTAT(0);
+	payload[VDO_INDEX_PRODUCT] = vdo_product;
+
+	if (pd_get_rev(port, TCPCI_MSG_SOP) == PD_REV30) {
+		/* PD Revision 3.0 */
+		payload[VDO_INDEX_IDH] = vdo_idh_rev30;
+		payload[VDO_INDEX_PTYPE_UFP1_VDO] = vdo_ufp1;
+		vdo_count = VDO_INDEX_PTYPE_UFP1_VDO;
+	} else {
+		payload[VDO_INDEX_IDH] = vdo_idh;
+		vdo_count = VDO_INDEX_PRODUCT;
+	}
+
+	/* Adjust VDO count for VDM header */
+	return vdo_count + 1;
+}
+
+static int svdm_response_svids(int port, uint32_t *payload)
+{
+	/* Verify that SVID is PD SID */
+	if (PD_VDO_VID(payload[0]) != USB_SID_PD) {
+		return 0;
+	}
+
+	payload[1] = USB_SID_DISPLAYPORT << 16;
+	/* number of data objects VDO header + 1 SVID for DP */
+	return 2;
+}
+
+#define OPOS_DP 1
+
+const uint32_t vdo_dp_modes[1] = {
+	VDO_MODE_DP(/* Must support C and E. D is required for 2 lanes */
+		    MODE_DP_PIN_C | MODE_DP_PIN_D | MODE_DP_PIN_E,
+		    0, /* DFP pin
+			  cfg
+			  supported
+			*/
+		    0, /* usb2.0 signalling in AMode may be req */
+		    CABLE_RECEPTACLE, /* its a receptacle */
+		    MODE_DP_V13, /* DPv1.3 Support, no Gen2 */
+		    MODE_DP_SNK) /* Its a sink only */
+};
+
+static int svdm_response_modes(int port, uint32_t *payload)
+{
+	if (PD_VDO_VID(payload[0]) == USB_SID_DISPLAYPORT) {
+		memcpy(payload + 1, vdo_dp_modes, sizeof(vdo_dp_modes));
+		return ARRAY_SIZE(vdo_dp_modes) + 1;
+	} else {
+		return 0; /* nak */
+	}
+}
+
+static int amode_dp_status(int port, uint32_t *payload)
+{
+	int opos = PD_VDO_OPOS(payload[0]);
+	int hpd = gpio_get_level(GPIO_DP_HPD);
+	int mf = dock_get_mf_preference();
+
+	if (opos != OPOS_DP)
+		return 0; /* nak */
+
+	payload[1] = VDO_DP_STATUS(0, /* IRQ_HPD */
+				   (hpd == 1), /* HPD_HI|LOW */
+				   0, /* request exit DP */
+				   0, /* request exit USB */
+				   mf, /* MF pref */
+				   vdm_is_dp_enabled(port), 0, /* power low */
+				   0x2);
+	return 2;
+}
+
+static void svdm_configure_demux(int port, int enable, int mf)
+{
+	mux_state_t demux = usb_mux_get(port);
+
+	if (enable) {
+		demux |= USB_PD_MUX_DP_ENABLED;
+		/* 4 lane mode if MF is not preferred */
+		if (!mf)
+			demux &= ~USB_PD_MUX_USB_ENABLED;
+		/*
+		 * Make sure the MST_LANE_CONTROL gpio is set to match the DP
+		 * pin configuration selected by the host. Note that the mf
+		 * passed into this function reflects the pin configuration
+		 * selected by the host and not the user mf preference which is
+		 * stored in bit 0 of CBI fw_config.
+		 */
+		baseboard_set_mst_lane_control(mf);
+		CPRINTS("DP[%d]: DFP-D selected pin config %s", port,
+			mf ? "D" : "C");
+	} else {
+		demux &= ~USB_PD_MUX_DP_ENABLED;
+		demux |= USB_PD_MUX_USB_ENABLED;
+	}
+
+	/* Configure demux for 2/4 lane DP and USB3 configuration */
+	usb_mux_set(port, demux, USB_SWITCH_CONNECT, pd_get_polarity(port));
+}
+
+static int amode_dp_config(int port, uint32_t *payload)
+{
+	uint32_t dp_config = payload[1];
+	int mf;
+
+	/*
+	 * Check pin assignment selected by DFP_D to determine if 2 lane or 4
+	 * lane DP ALT-MODe is required. (note PIN_C is for 4 lane and PIN_D is
+	 * for 2 lane mode).
+	 */
+	mf = ((dp_config >> 8) & 0xff) == MODE_DP_PIN_D ? 1 : 0;
+	/* Configure demux for DP mode */
+	svdm_configure_demux(port, 1, mf);
+	/* Notify hpd->pd conv that a DP_CONFIG message has been received */
+	pd_ufp_enable_hpd_send(port);
+
+	return 1;
+}
+
+static int svdm_enter_mode(int port, uint32_t *payload)
+{
+	int rv = 0; /* will generate a NAK */
+
+	/* SID & mode request is valid */
+	if ((PD_VDO_VID(payload[0]) == USB_SID_DISPLAYPORT) &&
+	    (PD_VDO_OPOS(payload[0]) == OPOS_DP)) {
+		/* Store valid object position to indicate mode is active */
+		pd_ufp_set_dp_opos(port, OPOS_DP);
+
+		/* Entering ALT-DP mode, enable DP connection in demux */
+		usb_pd_hpd_converter_enable(1);
+
+		/* ACK response has 1 VDO */
+		rv = 1;
+	}
+
+	CPRINTS("svdm_enter[%d]: svid = %x, ret = %d", port,
+		PD_VDO_VID(payload[0]), rv);
+
+	return rv;
+}
+
+static int svdm_exit_mode(int port, uint32_t *payload)
+{
+	int opos = pd_ufp_get_dp_opos(port);
+
+	if ((PD_VDO_VID(payload[0]) == USB_SID_DISPLAYPORT) &&
+	    (opos == OPOS_DP)) {
+		/* Clear mode active object position */
+		pd_ufp_set_dp_opos(port, 0);
+		/* Configure demux to disable DP mode */
+		svdm_configure_demux(port, 0, 0);
+		usb_pd_hpd_converter_enable(0);
+
+		return 1;
+	} else {
+		CPRINTF("Unknown exit mode req:0x%08x\n", payload[0]);
+		return 0;
+	}
+}
+
+static struct amode_fx dp_fx = {
+	.status = &amode_dp_status,
+	.config = &amode_dp_config,
+};
+
+const struct svdm_response svdm_rsp = {
+	.identity = &svdm_response_identity,
+	.svids = &svdm_response_svids,
+	.modes = &svdm_response_modes,
+	.enter_mode = &svdm_enter_mode,
+	.amode = &dp_fx,
+	.exit_mode = &svdm_exit_mode,
+};
+
+int pd_custom_vdm(int port, int cnt, uint32_t *payload, uint32_t **rpayload)
+{
+	/* We don't support, so ignore this message */
+	return 0;
+}
diff --git a/baseboard/honeybuns/usbc_support.c b/baseboard/honeybuns/usbc_support.c
new file mode 100644
index 0000000000..9c94f3f0ba
--- /dev/null
+++ b/baseboard/honeybuns/usbc_support.c
@@ -0,0 +1,474 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* USBC functions for RO */
+
+#include "common.h"
+#include "console.h"
+#include "driver/tcpm/ps8xxx.h"
+#include "driver/tcpm/tcpci.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "registers.h"
+#include "sn5s330.h"
+#include "system.h"
+#include "timer.h"
+#include "ucpd-stm32gx.h"
+#include "usb_charge.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+
+enum usbc_states {
+	UNATTACHED_SNK,
+	ATTACH_WAIT_SNK,
+	ATTACHED_SNK,
+};
+
+/* Variables used to manage the simple usbc state machine */
+static int usbc_port;
+static int usbc_state;
+static int usbc_vbus;
+static enum tcpc_cc_voltage_status cc1_v;
+static enum tcpc_cc_voltage_status cc2_v;
+
+__maybe_unused static __const_data const char *const usbc_state_names[] = {
+	[UNATTACHED_SNK] = "Unattached.SNK",
+	[ATTACH_WAIT_SNK] = "AttachWait.SNK",
+	[ATTACHED_SNK] = "Attached.SNK",
+};
+
+static int read_reg(uint8_t port, int reg, int *regval)
+{
+	return i2c_read8(ppc_chips[port].i2c_port,
+			 ppc_chips[port].i2c_addr_flags, reg, regval);
+}
+
+static int write_reg(uint8_t port, int reg, int regval)
+{
+	return i2c_write8(ppc_chips[port].i2c_port,
+			  ppc_chips[port].i2c_addr_flags, reg, regval);
+}
+
+static int baseboard_ppc_enable_sink_path(int port)
+{
+	int regval;
+	int status;
+	int retries;
+
+	/*
+	 * It seems that sometimes setting the FUNC_SET1 register fails
+	 * initially.  Therefore, we'll retry a couple of times.
+	 */
+	retries = 0;
+	do {
+		status = write_reg(port, SN5S330_FUNC_SET1, SN5S330_ILIM_3_06);
+		if (status) {
+			retries++;
+			msleep(1);
+		} else {
+			break;
+		}
+	} while (retries < 10);
+
+	/* Turn off dead battery resistors, turn on CC FETs */
+	status = read_reg(port, SN5S330_FUNC_SET4, &regval);
+	if (!status) {
+		regval |= SN5S330_CC_EN;
+		status = write_reg(port, SN5S330_FUNC_SET4, regval);
+	}
+	if (status) {
+		return status;
+	}
+
+	/* Enable sink path via PP2 */
+	status = read_reg(port, SN5S330_FUNC_SET3, &regval);
+	if (!status) {
+		regval &= ~SN5S330_PP1_EN;
+		regval |= SN5S330_PP2_EN;
+		status = write_reg(port, SN5S330_FUNC_SET3, regval);
+	}
+	if (status) {
+		return status;
+	}
+
+	return EC_SUCCESS;
+}
+
+static void baseboard_ucpd_apply_rd(int port)
+{
+	uint32_t cfgr1_reg;
+	uint32_t moder_reg;
+	uint32_t cr;
+
+	/* Ensure that clock to UCPD is enabled */
+	STM32_RCC_APB1ENR2 |= STM32_RCC_APB1ENR2_UPCD1EN;
+
+	/* Make sure CC1/CC2 pins PB4/PB6 are set for analog mode */
+	moder_reg = STM32_GPIO_MODER(GPIO_B);
+	moder_reg |= 0x3300;
+	STM32_GPIO_MODER(GPIO_B) = moder_reg;
+	/*
+	 * CFGR1 must be written when UCPD peripheral is disabled. Note that
+	 * disabling ucpd causes the peripheral to quit any ongoing activity and
+	 * sets all ucpd registers back their default values.
+	 */
+
+	cfgr1_reg = STM32_UCPD_CFGR1_PSC_CLK_VAL(UCPD_PSC_DIV - 1) |
+		    STM32_UCPD_CFGR1_TRANSWIN_VAL(UCPD_TRANSWIN_CNT - 1) |
+		    STM32_UCPD_CFGR1_IFRGAP_VAL(UCPD_IFRGAP_CNT - 1) |
+		    STM32_UCPD_CFGR1_HBITCLKD_VAL(UCPD_HBIT_DIV - 1);
+	STM32_UCPD_CFGR1(port) = cfgr1_reg;
+
+	/* Enable ucpd  */
+	STM32_UCPD_CFGR1(port) |= STM32_UCPD_CFGR1_UCPDEN;
+
+	/* Apply Rd to both CC lines */
+	cr = STM32_UCPD_CR(port);
+	cr |= STM32_UCPD_CR_ANAMODE | STM32_UCPD_CR_CCENABLE_MASK;
+	STM32_UCPD_CR(port) = cr;
+
+	/*
+	 * After exiting reset, stm32gx will have dead battery mode enabled by
+	 * default which connects Rd to CC1/CC2. This should be disabled when EC
+	 * is powered up.
+	 */
+	STM32_PWR_CR3 |= STM32_PWR_CR3_UCPD1_DBDIS;
+}
+
+static void baseboard_ucpd_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
+				  enum tcpc_cc_voltage_status *cc2)
+{
+	int vstate_cc1;
+	int vstate_cc2;
+	int anamode;
+	uint32_t sr;
+
+	/*
+	 * cc_voltage_status is determined from vstate_cc bit field in the
+	 * status register. The meaning of the value vstate_cc depends on
+	 * current value of ANAMODE (src/snk).
+	 *
+	 * vstate_cc maps directly to cc_state from tcpci spec when ANAMODE = 1,
+	 * but needs to be modified slightly for case ANAMODE = 0.
+	 *
+	 * If presenting Rp (source), then need to to a circular shift of
+	 * vstate_ccx value:
+	 *     vstate_cc | cc_state
+	 *     ------------------
+	 *        0     ->    1
+	 *        1     ->    2
+	 *        2     ->    0
+	 */
+
+	/* Get vstate_ccx values and power role */
+	sr = STM32_UCPD_SR(port);
+	/* Get Rp or Rd active */
+	anamode = !!(STM32_UCPD_CR(port) & STM32_UCPD_CR_ANAMODE);
+	vstate_cc1 = (sr & STM32_UCPD_SR_VSTATE_CC1_MASK) >>
+		     STM32_UCPD_SR_VSTATE_CC1_SHIFT;
+	vstate_cc2 = (sr & STM32_UCPD_SR_VSTATE_CC2_MASK) >>
+		     STM32_UCPD_SR_VSTATE_CC2_SHIFT;
+
+	/* Do circular shift if port == source */
+	if (anamode) {
+		if (vstate_cc1 != STM32_UCPD_SR_VSTATE_RA)
+			vstate_cc1 += 4;
+		if (vstate_cc2 != STM32_UCPD_SR_VSTATE_RA)
+			vstate_cc2 += 4;
+	} else {
+		if (vstate_cc1 != STM32_UCPD_SR_VSTATE_OPEN)
+			vstate_cc1 = (vstate_cc1 + 1) % 3;
+		if (vstate_cc2 != STM32_UCPD_SR_VSTATE_OPEN)
+			vstate_cc2 = (vstate_cc2 + 1) % 3;
+	}
+
+	*cc1 = vstate_cc1;
+	*cc2 = vstate_cc2;
+}
+
+static int baseboard_rp_is_present(enum tcpc_cc_voltage_status cc1,
+				   enum tcpc_cc_voltage_status cc2)
+{
+	return (cc1 >= TYPEC_CC_VOLT_RP_DEF || cc2 >= TYPEC_CC_VOLT_RP_DEF);
+}
+
+static void baseboard_usbc_check_connect(void);
+DECLARE_DEFERRED(baseboard_usbc_check_connect);
+
+static void baseboard_usbc_check_connect(void)
+{
+	enum tcpc_cc_voltage_status cc1;
+	enum tcpc_cc_voltage_status cc2;
+	int ppc_reg;
+	enum usbc_states enter_state = usbc_state;
+
+	/*
+	 * In RO, the only usbc related requirement is to enable the stm32g4
+	 * USB-EP to be enumerated by the host attached to C0. To prevent D+
+	 * being pulled high prior to VBUS presence, the EC uses GPIO_BPWR_DET
+	 * to signal the USB hub that VBUS is present. Therefore, we need a
+	 * simple usbc state machine to detect an attach (Rp and VBUS) event so
+	 * this GPIO signal is properly controlled in RO.
+	 *
+	 * Note that RO only runs until the RWSIG timer expires and jumps to RW,
+	 * and in RW, the full usb-pd stack is initialized and run.
+	 */
+
+	/* Get current CC voltage levels */
+	baseboard_ucpd_get_cc(usbc_port, &cc1, &cc2);
+	/* Update VBUS state */
+	if (!read_reg(usbc_port, SN5S330_INT_STATUS_REG3, &ppc_reg))
+		usbc_vbus = ppc_reg & SN5S330_VBUS_GOOD;
+
+	switch (usbc_state) {
+	case UNATTACHED_SNK:
+		/*
+		 * Require either CC1 or CC2 to have a valid Rp CC voltage level
+		 * to advance to ATTACH_WAIT_SNK.
+		 */
+		if (baseboard_rp_is_present(cc1, cc2))
+			usbc_state = ATTACH_WAIT_SNK;
+		break;
+	case ATTACH_WAIT_SNK:
+		/*
+		 * This state handles debounce by ensuring the CC voltages are
+		 * the same between two state machine iterations. If this
+		 * condition is met, and VBUS is present, then advance to
+		 * ATTACHED_SNK and set GPIO_BPWR_DET.
+		 *
+		 * If Rp voltage is no longer detected, then return to
+		 * UNATTACHED_SNK.
+		 */
+		if (usbc_vbus && cc1 == cc1_v && cc2 == cc2_v) {
+			usbc_state = ATTACHED_SNK;
+			gpio_set_level(GPIO_BPWR_DET, 1);
+		} else if (!baseboard_rp_is_present(cc1, cc2)) {
+			usbc_state = UNATTACHED_SNK;
+		}
+		break;
+	case ATTACHED_SNK:
+		/*
+		 * In this state, only checking for VBUS going away to indicate
+		 * a detach event and inform the USB hub via GPIO_BPWR_DET.
+		 */
+		if (!usbc_vbus) {
+			usbc_state = UNATTACHED_SNK;
+			gpio_set_level(GPIO_BPWR_DET, 0);
+		}
+		break;
+	}
+
+	/* Save CC voltage for debounce check */
+	cc1_v = cc1;
+	cc2_v = cc2;
+
+	if (enter_state != usbc_state)
+		CPRINTS("%s: cc1 = %d, cc2 = %d vbus = %d",
+			usbc_state_names[usbc_state], cc1, cc2, usbc_vbus);
+
+	hook_call_deferred(&baseboard_usbc_check_connect_data,
+			   PD_T_TRY_CC_DEBOUNCE);
+}
+
+int baseboard_usbc_init(int port)
+{
+	int rv;
+
+	/* Initialize ucpd and apply Rd to CC lines */
+	baseboard_ucpd_apply_rd(port);
+	/* Initialize ppc to enable sink path */
+	rv = baseboard_ppc_enable_sink_path(port);
+	if (rv)
+		CPRINTS("ppc init failed!");
+	/* Save host port value */
+	usbc_port = port;
+	/* Start RO usbc attach state machine */
+	gpio_set_level(GPIO_BPWR_DET, 0);
+	/* Start simple usbc state machine */
+	baseboard_usbc_check_connect();
+
+	return rv;
+}
+
+#ifdef SECTION_IS_RW
+int c1_ps8805_is_vbus_present(int port)
+{
+	int vbus;
+
+	vbus = tcpm_check_vbus_level(port, VBUS_PRESENT);
+
+	return vbus;
+}
+
+int c1_ps8805_is_sourcing_vbus(int port)
+{
+	int rv;
+	int level;
+
+	rv = ps8805_gpio_get_level(port, PS8805_GPIO_1, &level);
+	if (rv)
+		return 0;
+
+	return level;
+}
+
+int c1_ps8805_vbus_source_enable(int port, int enable)
+{
+	return ps8805_gpio_set_level(port, PS8805_GPIO_1, enable);
+}
+
+__override bool usb_ufp_check_usb3_enable(int port)
+{
+	/* USB3.1 mux should be enabled based on UFP data role */
+	return port == USB_PD_PORT_HOST;
+}
+
+#ifdef GPIO_USBC_UF_ATTACHED_SRC
+static int ppc_ocp_count;
+
+static void baseboard_usb3_manage_vbus(void)
+{
+	int level = gpio_get_level(GPIO_USBC_UF_ATTACHED_SRC);
+
+	/*
+	 * GPIO_USBC_UF_MUX_VBUS_EN is an output from the PS8803 which tracks if
+	 * C2 is attached. When it's attached, this signal will be high. Use
+	 * this level to control PPC VBUS on/off.
+	 */
+	ppc_vbus_source_enable(USB_PD_PORT_USB3, level);
+	CPRINTS("C2: State = %s", level ? "Attached.SRC " : "Unattached.SRC");
+
+	/* Reset OCP event counter for detach */
+	if (!level) {
+		ppc_ocp_count = 0;
+
+#ifdef GPIO_USB_HUB_OCP_NOTIFY
+		/*
+		 * In the case of an OCP event on this port, the usb hub should
+		 * be notified via a GPIO signal. Following, an OCP, the
+		 * attached.src state for the usb3 only port is checked again.
+		 * If it's attached, then make sure the OCP notify signal is
+		 * reset.
+		 */
+		gpio_set_level(GPIO_USB_HUB_OCP_NOTIFY, 1);
+#endif
+	}
+}
+DECLARE_DEFERRED(baseboard_usb3_manage_vbus);
+
+void baseboard_usb3_check_state(void)
+{
+	hook_call_deferred(&baseboard_usb3_manage_vbus_data, 0);
+}
+
+void baseboard_usbc_usb3_enable_interrupts(int enable)
+{
+	if (enable) {
+		/* Enable VBUS control interrupt for C2 */
+		gpio_enable_interrupt(GPIO_USBC_UF_ATTACHED_SRC);
+		/* Enable PPC interrupt */
+		gpio_enable_interrupt(GPIO_USBC_UF_PPC_INT_ODL);
+	} else {
+		/* Disable VBUS control interrupt for C2 */
+		gpio_disable_interrupt(GPIO_USBC_UF_ATTACHED_SRC);
+		/* Disable PPC interrupt */
+		gpio_disable_interrupt(GPIO_USBC_UF_PPC_INT_ODL);
+	}
+}
+
+int baseboard_config_usbc_usb3_ppc(void)
+{
+	int rv;
+
+	/*
+	 * This port is not usb-pd capable, but there is a ppc which must be
+	 * initialized, and keep the VBUS switch enabled.
+	 */
+	rv = ppc_init(USB_PD_PORT_USB3);
+	if (rv)
+		return rv;
+
+	/* Need to set current limit to 3A to match advertised value */
+	ppc_set_vbus_source_current_limit(USB_PD_PORT_USB3, TYPEC_RP_3A0);
+	/* Reset OCP event counter */
+	ppc_ocp_count = 0;
+
+	/* Check state at init time */
+	baseboard_usb3_manage_vbus();
+
+	/* Enable attached.src and PPC interrupts */
+	baseboard_usbc_usb3_enable_interrupts(1);
+
+	return EC_SUCCESS;
+}
+
+static void baseboard_usbc_usb3_handle_interrupt(void)
+{
+	int port = USB_PD_PORT_USB3;
+
+	/*
+	 * SN5S330's /INT pin is level, so process interrupts until it
+	 * deasserts if the chip has a dedicated interrupt pin.
+	 */
+	while (gpio_get_level(GPIO_USBC_UF_PPC_INT_ODL) == 0) {
+		int rise = 0;
+		int fall = 0;
+
+		read_reg(port, SN5S330_INT_TRIP_RISE_REG1, &rise);
+		read_reg(port, SN5S330_INT_TRIP_FALL_REG1, &fall);
+
+		/* Notify the system about the overcurrent event. */
+		if (rise & SN5S330_ILIM_PP1_MASK) {
+			CPRINTS("usb3_ppc: VBUS OC!");
+			gpio_set_level(GPIO_USB_HUB_OCP_NOTIFY, 0);
+			if (++ppc_ocp_count < 5)
+				hook_call_deferred(
+					&baseboard_usb3_manage_vbus_data,
+					USB_HUB_OCP_RESET_MSEC);
+			else
+				CPRINTS("usb3_ppc: VBUS OC limit reached!");
+		}
+
+		/* Clear the interrupt sources. */
+		write_reg(port, SN5S330_INT_TRIP_RISE_REG1, rise);
+		write_reg(port, SN5S330_INT_TRIP_FALL_REG1, fall);
+
+		read_reg(port, SN5S330_INT_TRIP_RISE_REG2, &rise);
+		read_reg(port, SN5S330_INT_TRIP_FALL_REG2, &fall);
+
+		/*
+		 * VCONN may be latched off due to an overcurrent.  Indicate
+		 * when the VCONN overcurrent happens.
+		 */
+		if (rise & SN5S330_VCONN_ILIM)
+			CPRINTS("usb3_ppc: VCONN OC!");
+
+		/*
+		 * CC overvoltage event. There is not action to take here, but
+		 * log the event.
+		 */
+		if (rise & SN5S330_CC1_CON || rise & SN5S330_CC2_CON)
+			CPRINTS("usb3_ppc: CC OV!");
+
+		/* Clear the interrupt sources. */
+		write_reg(port, SN5S330_INT_TRIP_RISE_REG2, rise);
+		write_reg(port, SN5S330_INT_TRIP_FALL_REG2, fall);
+	}
+}
+DECLARE_DEFERRED(baseboard_usbc_usb3_handle_interrupt);
+
+void baseboard_usbc_usb3_irq(void)
+{
+	hook_call_deferred(&baseboard_usbc_usb3_handle_interrupt_data, 0);
+}
+
+#endif /* defined(GPIO_USBC_UF_ATTACHED_SRC) */
+#endif /* defined(SECTION_IS_RW) */
diff --git a/baseboard/intelrvp/README.md b/baseboard/intelrvp/README.md
index b72d653d33..3405633132 100644
--- a/baseboard/intelrvp/README.md
+++ b/baseboard/intelrvp/README.md
@@ -1,25 +1,41 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
 This folder is for the baseboard for the board specific files which use Intel
 Reference Validation Platform (RVP) for developing the EC and other peripherals
 which can be hooked on EC or RVP.
 
 This baseboard follows the Intel Modular Embedded Controller Card (MECC)
-specification for pinout and these pin definitions remain same on all the
-RVPs. Chrome MECC spec is standardized for Icelake and successor RVPs hence
-this baseboard code is applicable to Icelake and its successors only.
+specification for pinout and these pin definitions remain same on all the RVPs.
+Chrome MECC spec is standardized for Icelake and successor RVPs hence this
+baseboard code is applicable to Icelake and its successors only.
 
 Following hardware features are supported on MECC header by RVP and can be
 validated by software by MECC.
-1. Power to MECC is provide by RVP (battery + DC Jack + Type C)
-2. Power control pins for Intel SOC are added
-3. Servo V2 header need to be added by MECC
-4. Google H1 chip need to be added by MECC (optional for EC vendors)
-4. 2 Type-C port support (SRC/SNK/BC1.2/MUX/Rerimer)
-5. 6 Temperature sensors
-6. 4 ADC
-7. 4 I2C Channels
-8. 1 Fan control
+
+## MECC version 1.0 features
+
+1.  Power to MECC is provided by RVP (battery + DC Jack + Type C)
+2.  Power control pins for Intel SOC are added
+3.  Servo V2 header need to be added by MECC
+4.  Google H1 chip need to be added by MECC (optional for EC vendors)
+5.  4 Type-C port support (SRC/SNK/MUX/Rerimer) as Add In Card (AIC) on
+    RVP
+6.  Optional 2 Type-C port routed to MECC for integrated TCPC support
+7.  6 I2C Channels
+8.  2 SMLINK Channels
+9.  2 I3C channels
+
+## MECC version 1.1 features
+
+1.  Power to MECC is provided by RVP (battery + DC Jack + Type C)
+2.  Power control pins for Intel SOC are added
+3.  Servo V2 header is added on RVP as an AIC
+4.  Google H1 chip is added on RVP as an AIC
+5.  4 Type-C port support (SRC/SNK/MUX/Rerimer) as an (AIC)
+6.  Optional 2 Type-C port routed to MECC for integrated TCPC support
+7.  6 I2C Channels
+8.  2 SMLINK Channels
+9.  2 I3C channels
+10. 1 Fan control
+11. 4 ADC based temperature sensors
+12. PECI control
+13. I2C based Keyboard is added on RVP as an AIC
+14. Both Google & Intel CCD support is added on RVP on Type-C port 0
diff --git a/baseboard/intelrvp/adlrvp.c b/baseboard/intelrvp/adlrvp.c
new file mode 100644
index 0000000000..5f307ac066
--- /dev/null
+++ b/baseboard/intelrvp/adlrvp.c
@@ -0,0 +1,603 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel ADLRVP board-specific common configuration */
+
+#include "battery.h"
+#include "battery_fuel_gauge.h"
+#include "bq25710.h"
+#include "charger.h"
+#include "common.h"
+#include "driver/retimer/bb_retimer_public.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "ioexpander.h"
+#include "isl9241.h"
+#include "pca9675.h"
+#include "power/icelake.h"
+#include "sn5s330.h"
+#include "system.h"
+#include "task.h"
+#include "tusb1064.h"
+#include "usb_mux.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ##args)
+
+/* TCPC AIC GPIO Configuration */
+const struct tcpc_aic_gpio_config_t tcpc_aic_gpios[] = {
+	[TYPE_C_PORT_0] = {
+		.tcpc_alert = GPIO_USBC_TCPC_ALRT_P0,
+		.ppc_alert = GPIO_USBC_TCPC_PPC_ALRT_P0,
+		.ppc_intr_handler = sn5s330_interrupt,
+	},
+#if defined(HAS_TASK_PD_C1)
+	[TYPE_C_PORT_1] = {
+		.tcpc_alert = GPIO_USBC_TCPC_ALRT_P1,
+		.ppc_alert = GPIO_USBC_TCPC_PPC_ALRT_P1,
+		.ppc_intr_handler = sn5s330_interrupt,
+	},
+#endif
+#if defined(HAS_TASK_PD_C2)
+	[TYPE_C_PORT_2] = {
+		.tcpc_alert = GPIO_USBC_TCPC_ALRT_P2,
+		.ppc_alert = GPIO_USBC_TCPC_PPC_ALRT_P2,
+		.ppc_intr_handler = sn5s330_interrupt,
+	},
+#endif
+#if defined(HAS_TASK_PD_C3)
+	[TYPE_C_PORT_3] = {
+		.tcpc_alert = GPIO_USBC_TCPC_ALRT_P3,
+		.ppc_alert = GPIO_USBC_TCPC_PPC_ALRT_P3,
+		.ppc_intr_handler = sn5s330_interrupt,
+	},
+#endif
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_aic_gpios) == CONFIG_USB_PD_PORT_MAX_COUNT);
+
+/* USB-C PPC configuration */
+struct ppc_config_t ppc_chips[] = {
+	[TYPE_C_PORT_0] = {
+		.i2c_port = I2C_PORT_TYPEC_0,
+		.i2c_addr_flags = I2C_ADDR_SN5S330_TCPC_AIC_PPC,
+		.drv = &sn5s330_drv,
+	},
+#if defined(HAS_TASK_PD_C1)
+	[TYPE_C_PORT_1] = {
+		.i2c_port = I2C_PORT_TYPEC_1,
+		.i2c_addr_flags = I2C_ADDR_SN5S330_TCPC_AIC_PPC,
+		.drv = &sn5s330_drv
+	},
+#endif
+#if defined(HAS_TASK_PD_C2)
+	[TYPE_C_PORT_2] = {
+		.i2c_port = I2C_PORT_TYPEC_2,
+		.i2c_addr_flags = I2C_ADDR_SN5S330_TCPC_AIC_PPC,
+		.drv = &sn5s330_drv,
+	},
+#endif
+#if defined(HAS_TASK_PD_C3)
+	[TYPE_C_PORT_3] = {
+		.i2c_port = I2C_PORT_TYPEC_3,
+		.i2c_addr_flags = I2C_ADDR_SN5S330_TCPC_AIC_PPC,
+		.drv = &sn5s330_drv,
+	},
+#endif
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == CONFIG_USB_PD_PORT_MAX_COUNT);
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/* USB-C retimer Configuration */
+struct usb_mux bb_retimer0_usb_mux = {
+	.usb_port = TYPE_C_PORT_0,
+	.driver = &bb_usb_retimer,
+	.hpd_update = bb_retimer_hpd_update,
+	.i2c_port = I2C_PORT_TYPEC_0,
+	.i2c_addr_flags = I2C_PORT0_BB_RETIMER_ADDR,
+};
+struct usb_mux_chain usbc0_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = TYPE_C_PORT_0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+#if defined(HAS_TASK_PD_C1)
+struct usb_mux bb_retimer1_usb_mux = {
+	.usb_port = TYPE_C_PORT_1,
+	.driver = &bb_usb_retimer,
+	.hpd_update = bb_retimer_hpd_update,
+	.i2c_port = I2C_PORT_TYPEC_1,
+	.i2c_addr_flags = I2C_PORT1_BB_RETIMER_ADDR,
+};
+struct usb_mux_chain usbc1_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = TYPE_C_PORT_1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+#endif
+#if defined(HAS_TASK_PD_C2)
+struct usb_mux bb_retimer2_usb_mux = {
+	.usb_port = TYPE_C_PORT_2,
+	.driver = &bb_usb_retimer,
+	.hpd_update = bb_retimer_hpd_update,
+	.i2c_port = I2C_PORT_TYPEC_2,
+	.i2c_addr_flags = I2C_PORT2_BB_RETIMER_ADDR,
+};
+struct usb_mux_chain usbc2_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = TYPE_C_PORT_2,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+#endif
+#if defined(HAS_TASK_PD_C3)
+struct usb_mux_chain usbc3_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = TYPE_C_PORT_3,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+#endif
+
+/* USB muxes Configuration */
+struct usb_mux_chain usb_muxes[] = {
+	[TYPE_C_PORT_0] = {
+		.mux = &bb_retimer0_usb_mux,
+		.next = &usbc0_tcss_usb_mux,
+	},
+#if defined(HAS_TASK_PD_C1)
+	[TYPE_C_PORT_1] = {
+		.mux = &bb_retimer1_usb_mux,
+		.next = &usbc1_tcss_usb_mux,
+	},
+#endif
+#if defined(HAS_TASK_PD_C2)
+	[TYPE_C_PORT_2] = {
+		.mux = &bb_retimer2_usb_mux,
+		.next = &usbc2_tcss_usb_mux,
+	},
+#endif
+#if defined(HAS_TASK_PD_C3)
+	[TYPE_C_PORT_3] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = TYPE_C_PORT_3,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_TYPEC_3,
+			.i2c_addr_flags = I2C_PORT3_BB_RETIMER_ADDR,
+		},
+		.next = &usbc3_tcss_usb_mux,
+	},
+#endif
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == CONFIG_USB_PD_PORT_MAX_COUNT);
+
+/* USB Mux Configuration for Soc side BB-Retimers for Dual retimer config */
+struct usb_mux_chain soc_side_bb_retimer0_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = TYPE_C_PORT_0,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_TYPEC_0,
+			.i2c_addr_flags = I2C_PORT0_BB_RETIMER_SOC_ADDR,
+		},
+	.next = &usbc0_tcss_usb_mux,
+};
+
+#if defined(HAS_TASK_PD_C1)
+struct usb_mux_chain soc_side_bb_retimer1_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = TYPE_C_PORT_1,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_TYPEC_1,
+			.i2c_addr_flags = I2C_PORT1_BB_RETIMER_SOC_ADDR,
+		},
+	.next = &usbc1_tcss_usb_mux,
+};
+#endif
+
+const struct bb_usb_control bb_controls[] = {
+	[TYPE_C_PORT_0] = {
+		.retimer_rst_gpio = (enum gpio_signal)
+			IOEX_USB_C0_BB_RETIMER_RST,
+		.usb_ls_en_gpio = (enum gpio_signal)
+			IOEX_USB_C0_BB_RETIMER_LS_EN,
+	},
+#if defined(HAS_TASK_PD_C1)
+	[TYPE_C_PORT_1] = {
+		.retimer_rst_gpio = (enum gpio_signal)
+			IOEX_USB_C1_BB_RETIMER_RST,
+		.usb_ls_en_gpio = (enum gpio_signal)
+			IOEX_USB_C1_BB_RETIMER_LS_EN,
+	},
+#endif
+#if defined(HAS_TASK_PD_C2)
+	[TYPE_C_PORT_2] = {
+		.retimer_rst_gpio = (enum gpio_signal)
+			IOEX_USB_C2_BB_RETIMER_RST,
+		.usb_ls_en_gpio = (enum gpio_signal)
+			IOEX_USB_C2_BB_RETIMER_LS_EN,
+	},
+#endif
+#if defined(HAS_TASK_PD_C3)
+	[TYPE_C_PORT_3] = {
+		.retimer_rst_gpio = (enum gpio_signal)
+			IOEX_USB_C3_BB_RETIMER_RST,
+		.usb_ls_en_gpio = (enum gpio_signal)
+			IOEX_USB_C3_BB_RETIMER_LS_EN,
+	},
+#endif
+};
+BUILD_ASSERT(ARRAY_SIZE(bb_controls) == CONFIG_USB_PD_PORT_MAX_COUNT);
+
+/* Cache BB retimer power state */
+static bool cache_bb_enable[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+/* Each TCPC have corresponding IO expander and are available in pair */
+struct ioexpander_config_t ioex_config[] = {
+	[IOEX_C0_PCA9675] = {
+		.i2c_host_port = I2C_PORT_TYPEC_0,
+		.i2c_addr_flags = I2C_ADDR_PCA9675_TCPC_AIC_IOEX,
+		.drv = &pca9675_ioexpander_drv,
+	},
+	[IOEX_C1_PCA9675] = {
+		.i2c_host_port = I2C_PORT_TYPEC_1,
+		.i2c_addr_flags = I2C_ADDR_PCA9675_TCPC_AIC_IOEX,
+		.drv = &pca9675_ioexpander_drv,
+	},
+#if defined(HAS_TASK_PD_C2)
+	[IOEX_C2_PCA9675] = {
+		.i2c_host_port = I2C_PORT_TYPEC_2,
+		.i2c_addr_flags = I2C_ADDR_PCA9675_TCPC_AIC_IOEX,
+		.drv = &pca9675_ioexpander_drv,
+	},
+	[IOEX_C3_PCA9675] = {
+		.i2c_host_port = I2C_PORT_TYPEC_3,
+		.i2c_addr_flags = I2C_ADDR_PCA9675_TCPC_AIC_IOEX,
+		.drv = &pca9675_ioexpander_drv,
+	},
+#endif
+};
+BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT);
+
+/* Charger Chips */
+struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = ISL9241_ADDR_FLAGS,
+		.drv = &isl9241_drv,
+	},
+};
+
+void board_overcurrent_event(int port, int is_overcurrented)
+{
+	/* Port 0 & 1 and 2 & 3 share same line for over current indication */
+#if defined(HAS_TASK_PD_C2)
+	enum ioex_signal oc_signal = port < TYPE_C_PORT_2 ? IOEX_USB_C0_C1_OC :
+							    IOEX_USB_C2_C3_OC;
+#else
+	enum ioex_signal oc_signal = IOEX_USB_C0_C1_OC;
+#endif
+
+	/* Overcurrent indication is active low signal */
+	ioex_set_level(oc_signal, is_overcurrented ? 0 : 1);
+}
+
+__override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
+{
+	/*
+	 * ADL-P-DDR5 RVP SKU has cascaded retimer topology.
+	 * Ports with cascaded retimers share common load switch and reset pin
+	 * hence no need to set the power state again if the 1st retimer's power
+	 * status has already changed.
+	 */
+	if (cache_bb_enable[me->usb_port] == enable)
+		return EC_SUCCESS;
+
+	cache_bb_enable[me->usb_port] = enable;
+
+	/* Handle retimer's power domain.*/
+	if (enable) {
+		ioex_set_level((enum ioex_signal)bb_controls[me->usb_port]
+				       .usb_ls_en_gpio,
+			       1);
+
+		/*
+		 * minimum time from VCC to RESET_N de-assertion is 100us
+		 * For boards that don't provide a load switch control, the
+		 * retimer_init() function ensures power is up before calling
+		 * this function.
+		 */
+		msleep(1);
+		ioex_set_level((enum ioex_signal)bb_controls[me->usb_port]
+				       .retimer_rst_gpio,
+			       1);
+
+		/*
+		 * Allow 1ms time for the retimer to power up lc_domain
+		 * which powers I2C controller within retimer
+		 */
+		msleep(1);
+
+	} else {
+		ioex_set_level((enum ioex_signal)bb_controls[me->usb_port]
+				       .retimer_rst_gpio,
+			       0);
+		msleep(1);
+		ioex_set_level((enum ioex_signal)bb_controls[me->usb_port]
+				       .usb_ls_en_gpio,
+			       0);
+	}
+	return EC_SUCCESS;
+}
+
+static void board_connect_c0_sbu_deferred(void)
+{
+	int ccd_intr_level = gpio_get_level(GPIO_CCD_MODE_ODL);
+
+	if (ccd_intr_level) {
+		/* Default set the SBU lines to AUX mode on TCPC-AIC */
+		ioex_set_level(IOEX_USB_C0_USB_MUX_CNTRL_1, 0);
+		ioex_set_level(IOEX_USB_C0_USB_MUX_CNTRL_0, 0);
+	} else {
+		/* Set the SBU lines to CCD mode on TCPC-AIC */
+		ioex_set_level(IOEX_USB_C0_USB_MUX_CNTRL_1, 1);
+		ioex_set_level(IOEX_USB_C0_USB_MUX_CNTRL_0, 0);
+	}
+}
+DECLARE_DEFERRED(board_connect_c0_sbu_deferred);
+
+void board_connect_c0_sbu(enum gpio_signal s)
+{
+	hook_call_deferred(&board_connect_c0_sbu_deferred_data, 0);
+}
+
+static void enable_h1_irq(void)
+{
+	gpio_enable_interrupt(GPIO_CCD_MODE_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, enable_h1_irq, HOOK_PRIO_LAST);
+
+void set_charger_system_voltage(void)
+{
+	switch (ADL_RVP_BOARD_ID(board_get_version())) {
+	case ADLN_LP5_ERB_SKU_BOARD_ID:
+	case ADLN_LP5_RVP_SKU_BOARD_ID:
+		/*
+		 * As per b:196184163 configure the PPVAR_SYS depend
+		 * on AC or AC+battery
+		 */
+		if (extpower_is_present() && battery_is_present()) {
+			bq25710_set_min_system_voltage(
+				CHARGER_SOLO, battery_get_info()->voltage_min);
+		} else {
+			bq25710_set_min_system_voltage(
+				CHARGER_SOLO, battery_get_info()->voltage_max);
+		}
+		break;
+
+	/* Add additional board SKUs */
+	default:
+		break;
+	}
+}
+DECLARE_HOOK(HOOK_AC_CHANGE, set_charger_system_voltage, HOOK_PRIO_DEFAULT);
+
+static void configure_charger(void)
+{
+	switch (ADL_RVP_BOARD_ID(board_get_version())) {
+	case ADLN_LP5_ERB_SKU_BOARD_ID:
+	case ADLN_LP5_RVP_SKU_BOARD_ID:
+		/* charger chip BQ25720 support */
+		chg_chips[0].i2c_addr_flags = BQ25710_SMBUS_ADDR1_FLAGS;
+		chg_chips[0].drv = &bq25710_drv;
+		set_charger_system_voltage();
+		break;
+
+	/* Add additional board SKUs */
+	default:
+		break;
+	}
+}
+
+static void configure_retimer_usbmux(void)
+{
+	switch (ADL_RVP_BOARD_ID(board_get_version())) {
+	case ADLN_LP5_ERB_SKU_BOARD_ID:
+	case ADLN_LP5_RVP_SKU_BOARD_ID:
+		/* enable TUSB1044RNQR redriver on Port0  */
+		bb_retimer0_usb_mux.i2c_addr_flags = TUSB1064_I2C_ADDR14_FLAGS;
+		bb_retimer0_usb_mux.driver = &tusb1064_usb_mux_driver;
+		bb_retimer0_usb_mux.hpd_update = tusb1044_hpd_update;
+
+#if defined(HAS_TASK_PD_C1)
+		bb_retimer1_usb_mux.driver = NULL;
+		bb_retimer1_usb_mux.hpd_update = NULL;
+#endif
+		break;
+
+	case ADLP_LP5_T4_RVP_SKU_BOARD_ID:
+		/* No retimer on Port-2 */
+#if defined(HAS_TASK_PD_C2)
+		bb_retimer2_usb_mux.driver = NULL;
+#endif
+		break;
+
+	case ADLP_DDR5_RVP_SKU_BOARD_ID:
+		/*
+		 * ADL-P-DDR5 RVP has dual BB-retimers for port0 & port1.
+		 * Change the default usb mux config on runtime to support
+		 * dual retimer topology.
+		 */
+		usb_muxes[TYPE_C_PORT_0].next = &soc_side_bb_retimer0_usb_mux;
+#if defined(HAS_TASK_PD_C1)
+		usb_muxes[TYPE_C_PORT_1].next = &soc_side_bb_retimer1_usb_mux;
+#endif
+		break;
+
+		/* Add additional board SKUs */
+
+	default:
+		break;
+	}
+}
+
+static void configure_battery_type(void)
+{
+	int bat_cell_type;
+
+	switch (ADL_RVP_BOARD_ID(board_get_version())) {
+	case ADLM_LP4_RVP1_SKU_BOARD_ID:
+	case ADLM_LP5_RVP2_SKU_BOARD_ID:
+	case ADLM_LP5_RVP3_SKU_BOARD_ID:
+	case ADLN_LP5_ERB_SKU_BOARD_ID:
+	case ADLN_LP5_RVP_SKU_BOARD_ID:
+		/* configure Battery to 2S based */
+		bat_cell_type = BATTERY_GETAC_SMP_HHP_408_2S;
+		break;
+	default:
+		/* configure Battery to 3S based */
+		bat_cell_type = BATTERY_GETAC_SMP_HHP_408_3S;
+		break;
+	}
+
+	/* Set the fixed battery type */
+	battery_set_fixed_battery_type(bat_cell_type);
+}
+/******************************************************************************/
+/* PWROK signal configuration */
+/*
+ * On ADLRVP, SYS_PWROK_EC is an output controlled by EC and uses ALL_SYS_PWRGD
+ * as input.
+ */
+const struct intel_x86_pwrok_signal pwrok_signal_assert_list[] = {
+	{
+		.gpio = GPIO_SYS_PWROK_EC,
+		.delay_ms = 3,
+	},
+};
+const int pwrok_signal_assert_count = ARRAY_SIZE(pwrok_signal_assert_list);
+
+const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[] = {
+	{
+		.gpio = GPIO_SYS_PWROK_EC,
+	},
+};
+const int pwrok_signal_deassert_count = ARRAY_SIZE(pwrok_signal_assert_list);
+
+/*
+ * Returns board information (board id[7:0] and Fab id[15:8]) on success
+ * -1 on error.
+ */
+__override int board_get_version(void)
+{
+	/* Cache the ADLRVP board ID */
+	static int adlrvp_board_id;
+
+	int port0, port1;
+	int fab_id, board_id, bom_id;
+
+	/* Board ID is already read */
+	if (adlrvp_board_id)
+		return adlrvp_board_id;
+
+	if (ioexpander_read_intelrvp_version(&port0, &port1))
+		return -1;
+	/*
+	 * Port0: bit 0   - BOM ID(2)
+	 *        bit 2:1 - FAB ID(1:0) + 1
+	 * Port1: bit 7:6 - BOM ID(1:0)
+	 *        bit 5:0 - BOARD ID(5:0)
+	 */
+	bom_id = ((port1 & 0xC0) >> 6) | ((port0 & 0x01) << 2);
+	fab_id = ((port0 & 0x06) >> 1) + 1;
+	board_id = port1 & 0x3F;
+
+	CPRINTS("BID:0x%x, FID:0x%x, BOM:0x%x", board_id, fab_id, bom_id);
+
+	adlrvp_board_id = board_id | (fab_id << 8);
+	return adlrvp_board_id;
+}
+
+__override bool board_is_tbt_usb4_port(int port)
+{
+	bool tbt_usb4 = true;
+
+	switch (ADL_RVP_BOARD_ID(board_get_version())) {
+	case ADLN_LP5_ERB_SKU_BOARD_ID:
+	case ADLN_LP5_RVP_SKU_BOARD_ID:
+		/* No retimer on both ports */
+		tbt_usb4 = false;
+		break;
+
+	case ADLP_LP5_T4_RVP_SKU_BOARD_ID:
+		/* No retimer on Port-2 hence no platform level AUX & LSx mux */
+#if defined(HAS_TASK_PD_C2)
+		if (port == TYPE_C_PORT_2)
+			tbt_usb4 = false;
+#endif
+		break;
+
+	/* Add additional board SKUs */
+	default:
+		break;
+	}
+
+	return tbt_usb4;
+}
+
+__override void board_pre_task_i2c_peripheral_init(void)
+{
+	/* Initialized IOEX-0 to access IOEX-GPIOs needed pre-task */
+	ioex_init(IOEX_C0_PCA9675);
+
+	/* Make sure SBU are routed to CCD or AUX based on CCD status at init */
+	board_connect_c0_sbu_deferred();
+
+	/* Configure battery type */
+	configure_battery_type();
+
+	/* Reconfigure board specific charger drivers */
+	configure_charger();
+
+	/* Configure board specific retimer & mux */
+	configure_retimer_usbmux();
+}
+
+/*
+ * ADL RVP has both ITE and FUSB based TCPC chips. By default, the PD
+ * state of a non-attached port remains in PD_DRP_TOGGLE_ON in active
+ * state. Also, FUSB TCPC chip does not support 'dual role auto toggle'
+ * which contradicts the default set S0 state of PD_DRP_TOGGLE_ON,
+ * while ITE  based TCPC can support dual role auto toggle. The
+ * default PD_DRP_TOGGLE_ON state in Active state doesnot allow TCPC
+ * ports to enter Low power mode. To fix the issue, added board specific
+ * code to remove the default DRP state - PD_DRP_TOGGLE_ON in S0. Also,
+ * eventhough 'dual role auto toggle' is not supported by FUSB, the ports
+ * supports both source and sink. Hence, setting the default DRP state
+ * as PD_DRP_FORCE_SOURCE in S0, would be the ideal board based solution to
+ * support for both source and sink devices for this RVP.
+ * Note:For ITE based TCPC, low power mode entry does makes no
+ * difference, as it is controlled by ITE TCPC clk in deep sleepmode.
+ */
+__override enum pd_dual_role_states pd_get_drp_state_in_s0(void)
+{
+	return PD_DRP_FORCE_SOURCE;
+}
diff --git a/baseboard/intelrvp/adlrvp.h b/baseboard/intelrvp/adlrvp.h
new file mode 100644
index 0000000000..2159adf92c
--- /dev/null
+++ b/baseboard/intelrvp/adlrvp.h
@@ -0,0 +1,229 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel ADL-RVP specific configuration */
+
+#ifndef __ADLRVP_BOARD_H
+#define __ADLRVP_BOARD_H
+
+/* Temperature sensor */
+#define CONFIG_TEMP_SENSOR
+
+#include "baseboard.h"
+
+/* RVP Board ids */
+#define CONFIG_BOARD_VERSION_GPIO
+#define ADLM_LP4_RVP1_SKU_BOARD_ID 0x01
+#define ADLM_LP5_RVP2_SKU_BOARD_ID 0x02
+#define ADLM_LP5_RVP3_SKU_BOARD_ID 0x03
+#define ADLN_LP5_ERB_SKU_BOARD_ID 0x06
+#define ADLN_LP5_RVP_SKU_BOARD_ID 0x07
+#define ADLP_DDR5_RVP_SKU_BOARD_ID 0x12
+#define ADLP_LP5_T4_RVP_SKU_BOARD_ID 0x13
+#define ADL_RVP_BOARD_ID(id) ((id)&0x3F)
+
+/* MECC config */
+#define CONFIG_INTEL_RVP_MECC_VERSION_1_0
+
+/* Support early firmware selection */
+#define CONFIG_VBOOT_EFS2
+
+/* Chipset */
+#define CONFIG_CHIPSET_ALDERLAKE
+
+/* ADL has new low-power features that require extra-wide virtual wire
+ * pulses. The EDS specifies 100 microseconds. */
+#undef CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US
+#define CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US 100
+
+/* USB PD config */
+#if defined(HAS_TASK_PD_C3)
+#define CONFIG_USB_PD_PORT_MAX_COUNT 4
+#elif defined(HAS_TASK_PD_C2)
+#define CONFIG_USB_PD_PORT_MAX_COUNT 3
+#elif defined(HAS_TASK_PD_C1)
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#else
+#define CONFIG_USB_PD_PORT_MAX_COUNT 1
+#endif
+#define CONFIG_USB_MUX_VIRTUAL
+#define CONFIG_USB_MUX_TUSB1044
+#define PD_MAX_POWER_MW 100000
+
+#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
+
+/* TCPC AIC config */
+/* Support NXP PCA9675 I/O expander. */
+#define CONFIG_IO_EXPANDER
+#define CONFIG_IO_EXPANDER_PCA9675
+#define I2C_ADDR_PCA9675_TCPC_AIC_IOEX 0x21
+
+/* DC Jack charge ports */
+#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT
+#define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1
+#define DEDICATED_CHARGE_PORT CONFIG_USB_PD_PORT_MAX_COUNT
+
+/* PPC */
+#define CONFIG_USBC_PPC_SN5S330
+#define CONFIG_USB_PD_VBUS_DETECT_PPC
+#define CONFIG_USB_PD_DISCHARGE_PPC
+#define I2C_ADDR_SN5S330_TCPC_AIC_PPC 0x40
+
+/* TCPC */
+#define CONFIG_USB_PD_DISCHARGE
+#define CONFIG_USB_PD_TCPM_FUSB302
+#define I2C_ADDR_FUSB302_TCPC_AIC 0x22
+
+/* Config BB retimer */
+#define CONFIG_USBC_RETIMER_INTEL_BB
+#define CONFIG_USBC_RETIMER_FW_UPDATE
+
+/* Connector side BB retimers */
+#define I2C_PORT0_BB_RETIMER_ADDR 0x56
+#if defined(HAS_TASK_PD_C1)
+#define I2C_PORT1_BB_RETIMER_ADDR 0x57
+#endif
+#if defined(HAS_TASK_PD_C2)
+#define I2C_PORT2_BB_RETIMER_ADDR 0x58
+#endif
+#if defined(HAS_TASK_PD_C3)
+#define I2C_PORT3_BB_RETIMER_ADDR 0x59
+#endif
+
+/* SOC side BB retimers (dual retimer config) */
+#define I2C_PORT0_BB_RETIMER_SOC_ADDR 0x54
+#if defined(HAS_TASK_PD_C1)
+#define I2C_PORT1_BB_RETIMER_SOC_ADDR 0x55
+#endif
+
+/* I2C EEPROM */
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+#define I2C_PORT_EEPROM I2C_PORT_PCA9555_BOARD_ID_GPIO
+
+/* Enable CBI */
+#define CONFIG_CBI_EEPROM
+
+/* Configure mux at runtime */
+#define CONFIG_USB_MUX_RUNTIME_CONFIG
+
+/* Enable VCONN */
+#define CONFIG_USBC_VCONN
+#define CONFIG_USBC_VCONN_SWAP
+
+/* Enabling Thunderbolt-compatible mode */
+#define CONFIG_USB_PD_TBT_COMPAT_MODE
+
+/* Enabling USB4 mode */
+#define CONFIG_USB_PD_USB4
+
+/* Enable low power mode */
+#define CONFIG_USB_PD_TCPC_LOW_POWER
+
+/* Config Fan */
+#define CONFIG_FANS 1
+#define BOARD_FAN_MIN_RPM 3000
+#define BOARD_FAN_MAX_RPM 10000
+
+/* Charger Configs */
+#define CONFIG_CHARGER_RUNTIME_CONFIG
+/* Charger chip on ADL-P, ADL-M */
+#define CONFIG_CHARGER_ISL9241
+/* Charger chip on ADL-N */
+#define CONFIG_CHARGER_BQ25720
+#define CONFIG_CHARGER_BQ25720_VSYS_TH2_CUSTOM
+#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV 70
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10
+
+/* Port 80 */
+#define PORT80_I2C_ADDR MAX695X_I2C_ADDR1_FLAGS
+
+/* Board Id */
+#define I2C_ADDR_PCA9555_BOARD_ID_GPIO 0x22
+
+/*
+ * Frequent watchdog timer resets are seen, with the
+ * increase in number of type-c ports. So increase
+ * the timer value to support more type-c ports.
+ */
+#ifdef VARIANT_INTELRVP_EC_IT8320
+#if defined(HAS_TASK_PD_C2) && defined(HAS_TASK_PD_C3)
+#undef CONFIG_WATCHDOG_PERIOD_MS
+#define CONFIG_WATCHDOG_PERIOD_MS 4000
+#endif
+#endif
+
+/*
+ * Enable support for battery hostcmd, supporting longer strings.
+ * Support for EC_CMD_BATTERY_GET_STATIC version 1.
+ */
+#define CONFIG_BATTERY_V2
+#define CONFIG_BATTERY_COUNT 1
+#define CONFIG_HOSTCMD_BATTERY_V2
+
+/* Config to indicate battery type doesn't auto detect */
+#define CONFIG_BATTERY_TYPE_NO_AUTO_DETECT
+
+/* Enable system boot time logging */
+#define CONFIG_SYSTEM_BOOT_TIME_LOGGING
+
+#ifndef __ASSEMBLER__
+
+enum adlrvp_charge_ports {
+	TYPE_C_PORT_0,
+#if defined(HAS_TASK_PD_C1)
+	TYPE_C_PORT_1,
+#endif
+#if defined(HAS_TASK_PD_C2)
+	TYPE_C_PORT_2,
+#endif
+#if defined(HAS_TASK_PD_C3)
+	TYPE_C_PORT_3,
+#endif
+};
+
+/*
+ * Each Type-C add in card has two I/O expanders hence even if one Type-C port
+ * is enabled other I/O expander is available for usage.
+ */
+enum ioex_port {
+	IOEX_C0_PCA9675,
+	IOEX_C1_PCA9675,
+#if defined(HAS_TASK_PD_C2)
+	IOEX_C2_PCA9675,
+	IOEX_C3_PCA9675,
+#endif
+	IOEX_PORT_COUNT
+};
+#define CONFIG_IO_EXPANDER_PORT_COUNT IOEX_PORT_COUNT
+
+enum battery_type {
+	BATTERY_GETAC_SMP_HHP_408_3S,
+	BATTERY_GETAC_SMP_HHP_408_2S,
+	BATTERY_TYPE_COUNT,
+};
+
+/* I2C access in polling mode before task is initialized */
+#define CONFIG_I2C_BITBANG
+
+enum adlrvp_bitbang_i2c_channel {
+	I2C_BITBANG_CHAN_BRD_ID,
+	I2C_BITBANG_CHAN_IOEX_0,
+	I2C_BITBANG_CHAN_COUNT
+};
+#define I2C_BITBANG_PORT_COUNT I2C_BITBANG_CHAN_COUNT
+
+void espi_reset_pin_asserted_interrupt(enum gpio_signal signal);
+void extpower_interrupt(enum gpio_signal signal);
+void ppc_interrupt(enum gpio_signal signal);
+void tcpc_alert_event(enum gpio_signal signal);
+void board_connect_c0_sbu(enum gpio_signal s);
+int board_get_version(void);
+void battery_detect_interrupt(enum gpio_signal signal);
+void set_charger_system_voltage(void);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __ADLRVP_BOARD_H */
diff --git a/baseboard/intelrvp/adlrvp_battery.c b/baseboard/intelrvp/adlrvp_battery.c
new file mode 100644
index 0000000000..f7107cb1a4
--- /dev/null
+++ b/baseboard/intelrvp/adlrvp_battery.c
@@ -0,0 +1,83 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "battery_smart.h"
+#include "common.h"
+#include "util.h"
+
+#ifdef CONFIG_BATTERY_TYPE_NO_AUTO_DETECT
+/* Battery configuration */
+const struct board_batt_params board_battery_info[] = {
+	/*
+	 * 3S based battery configuration
+	 * Getac Battery (Getac SMP-HHP-408) Information
+	 * Fuel gauge: BQ40Z50-R3
+	 */
+	[BATTERY_GETAC_SMP_HHP_408_3S] = {
+		.fuel_gauge = {
+			.manuf_name = "Getac",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+
+			.fet = {
+				.reg_addr = 0x0,
+				.reg_mask = 0x6000,
+				.disconnect_val = 0x6000,
+			}
+		},
+		.batt_info = {
+			.voltage_max = 13050,        /* mV */
+			.voltage_normal = 11400,
+			.voltage_min = 9000,
+			.precharge_current = 256,   /* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = 0,
+			.discharging_max_c = 60,
+		},
+	},
+	/*
+	 * 2S based battery configuration
+	 * Getac Battery (Getac SMP-HHP-408) Information
+	 * Fuel gauge: BQ40Z50-R3
+	 */
+	[BATTERY_GETAC_SMP_HHP_408_2S] = {
+		.fuel_gauge = {
+			.manuf_name = "Getac",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr = 0x0,
+				.reg_mask = 0x6000,
+				.disconnect_val = 0x6000,
+			}
+		},
+		.batt_info = {
+			.voltage_max = 8800,        /* mV */
+			.voltage_normal = 7700,
+			.voltage_min = 6000,
+			.precharge_current = 256,   /* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = 0,
+			.discharging_max_c = 60,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_GETAC_SMP_HHP_408_3S;
+#endif /* CONFIG_BATTERY_TYPE_NO_AUTO_DETECT */
diff --git a/baseboard/intelrvp/adlrvp_ioex_gpio.inc b/baseboard/intelrvp/adlrvp_ioex_gpio.inc
new file mode 100644
index 0000000000..b62dcf53a3
--- /dev/null
+++ b/baseboard/intelrvp/adlrvp_ioex_gpio.inc
@@ -0,0 +1,32 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+IOEX(USB_C0_BB_RETIMER_RST,	EXPIN(IOEX_C0_PCA9675, 0, PCA9675_IO_P00), GPIO_OUT_LOW)
+IOEX(USB_C0_BB_RETIMER_LS_EN,	EXPIN(IOEX_C0_PCA9675, 0, PCA9675_IO_P01), GPIO_OUT_LOW)
+IOEX(USB_C0_USB_MUX_CNTRL_1,	EXPIN(IOEX_C0_PCA9675, 0, PCA9675_IO_P04), GPIO_OUT_LOW)
+IOEX(USB_C0_USB_MUX_CNTRL_0,	EXPIN(IOEX_C0_PCA9675, 0, PCA9675_IO_P05), GPIO_OUT_LOW)
+
+IOEX(USB_C1_BB_RETIMER_RST,	EXPIN(IOEX_C1_PCA9675, 0, PCA9675_IO_P00), GPIO_OUT_LOW)
+IOEX(USB_C1_BB_RETIMER_LS_EN,	EXPIN(IOEX_C1_PCA9675, 0, PCA9675_IO_P01), GPIO_OUT_LOW)
+IOEX(USB_C1_HPD,		EXPIN(IOEX_C1_PCA9675, 0, PCA9675_IO_P02), GPIO_OUT_LOW)
+IOEX(USB_C0_C1_OC,		EXPIN(IOEX_C1_PCA9675, 0, PCA9675_IO_P10), GPIO_OUT_HIGH)
+
+#if defined(HAS_TASK_PD_C2)
+IOEX(USB_C2_BB_RETIMER_RST,	EXPIN(IOEX_C2_PCA9675, 0, PCA9675_IO_P00), GPIO_OUT_LOW)
+IOEX(USB_C2_BB_RETIMER_LS_EN,	EXPIN(IOEX_C2_PCA9675, 0, PCA9675_IO_P01), GPIO_OUT_LOW)
+IOEX(USB_C2_USB_MUX_CNTRL_1,	EXPIN(IOEX_C2_PCA9675, 0, PCA9675_IO_P04), GPIO_OUT_LOW)
+IOEX(USB_C2_USB_MUX_CNTRL_0,	EXPIN(IOEX_C2_PCA9675, 0, PCA9675_IO_P05), GPIO_OUT_LOW)
+
+IOEX(USB_C3_BB_RETIMER_RST,	EXPIN(IOEX_C3_PCA9675, 0, PCA9675_IO_P00), GPIO_OUT_LOW)
+IOEX(USB_C3_BB_RETIMER_LS_EN,	EXPIN(IOEX_C3_PCA9675, 0, PCA9675_IO_P01), GPIO_OUT_LOW)
+IOEX(USB_C2_C3_OC,		EXPIN(IOEX_C3_PCA9675, 0, PCA9675_IO_P10), GPIO_OUT_HIGH)
+#endif
+
+/* ADL-RVP has custom GPIO implementation for reading board ID */
+UNIMPLEMENTED(BOARD_VERSION1)
+UNIMPLEMENTED(BOARD_VERSION2)
+UNIMPLEMENTED(BOARD_VERSION3)
diff --git a/baseboard/intelrvp/baseboard.c b/baseboard/intelrvp/baseboard.c
index bf1127bb76..41bcdc26c2 100644
--- a/baseboard/intelrvp/baseboard.c
+++ b/baseboard/intelrvp/baseboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,12 +9,13 @@
 #include "charge_state.h"
 #include "espi.h"
 #include "fan.h"
+#include "gpio.h"
 #include "hooks.h"
 #include "pca9555.h"
 #include "peci.h"
 #include "power.h"
 #include "temp_sensor.h"
-#include "thermistor.h"
+#include "temp_sensor/thermistor.h"
 #include "timer.h"
 
 /* Wake-up pins for hibernate */
@@ -25,39 +26,6 @@ const enum gpio_signal hibernate_wake_pins[] = {
 };
 const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SNS_AMBIENT] = {
-		.name = "ADC_TEMP_SNS_AMBIENT",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = ADC_TEMP_SNS_AMBIENT_CHANNEL,
-	},
-	[ADC_TEMP_SNS_DDR] = {
-		.name = "ADC_TEMP_SNS_DDR",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = ADC_TEMP_SNS_DDR_CHANNEL,
-	},
-	[ADC_TEMP_SNS_SKIN] = {
-		.name = "ADC_TEMP_SNS_SKIN",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = ADC_TEMP_SNS_SKIN_CHANNEL,
-	},
-	[ADC_TEMP_SNS_VR] = {
-		.name = "ADC_TEMP_SNS_VR",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = ADC_TEMP_SNS_VR_CHANNEL,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
 #ifdef CONFIG_TEMP_SENSOR
 /* Temperature sensors */
 const struct temp_sensor_t temp_sensors[] = {
@@ -101,6 +69,33 @@ const struct temp_sensor_t temp_sensors[] = {
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+#define THERMAL_A                \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+		.temp_fan_off = C_TO_K(15), \
+		.temp_fan_max = C_TO_K(50), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A;
+
+struct ec_thermal_config thermal_params[] = {
+	[TEMP_SNS_AMBIENT] = THERMAL_A, [TEMP_SNS_BATTERY] = THERMAL_A,
+	[TEMP_SNS_DDR] = THERMAL_A,
+#ifdef CONFIG_PECI
+	[TEMP_SNS_PECI] = THERMAL_A,
+#endif
+	[TEMP_SNS_SKIN] = THERMAL_A,	[TEMP_SNS_VR] = THERMAL_A,
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
 #endif /* CONFIG_TEMP_SENSOR */
 
 #ifdef CONFIG_FANS
@@ -127,33 +122,6 @@ const struct fan_t fans[] = {
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
-
-const static struct ec_thermal_config thermal_a = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(15),
-	.temp_fan_max = C_TO_K(50),
-};
-
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SNS_AMBIENT] = thermal_a,
-	[TEMP_SNS_BATTERY] = thermal_a,
-	[TEMP_SNS_DDR] = thermal_a,
-#ifdef CONFIG_PECI
-	[TEMP_SNS_PECI] = thermal_a,
-#endif
-	[TEMP_SNS_SKIN] = thermal_a,
-	[TEMP_SNS_VR] = thermal_a,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
 #endif /* CONFIG_FANS */
 
 static void board_init(void)
@@ -172,14 +140,23 @@ DECLARE_HOOK(HOOK_INIT, board_interrupts_init, HOOK_PRIO_FIRST);
 
 int ioexpander_read_intelrvp_version(int *port0, int *port1)
 {
-	if (pca9555_read(I2C_PORT_PCA9555_BOARD_ID_GPIO,
-		I2C_ADDR_PCA9555_BOARD_ID_GPIO,
-		PCA9555_CMD_INPUT_PORT_0, port0))
-		return -1;
-
-	return pca9555_read(I2C_PORT_PCA9555_BOARD_ID_GPIO,
-		I2C_ADDR_PCA9555_BOARD_ID_GPIO,
-		PCA9555_CMD_INPUT_PORT_1, port1);
+	int i, rv;
+
+	for (i = 0; i < RVP_VERSION_READ_RETRY_CNT; i++) {
+		rv = pca9555_read(I2C_PORT_PCA9555_BOARD_ID_GPIO,
+				  I2C_ADDR_PCA9555_BOARD_ID_GPIO,
+				  PCA9555_CMD_INPUT_PORT_0, port0);
+
+		if (!rv && !pca9555_read(I2C_PORT_PCA9555_BOARD_ID_GPIO,
+					 I2C_ADDR_PCA9555_BOARD_ID_GPIO,
+					 PCA9555_CMD_INPUT_PORT_1, port1))
+			return 0;
+
+		msleep(1);
+	}
+
+	/* pca9555 read failed */
+	return -1;
 }
 
 __override void intel_x86_sys_reset_delay(void)
@@ -190,4 +167,3 @@ __override void intel_x86_sys_reset_delay(void)
 	 */
 	udelay(60 * MSEC);
 }
-
diff --git a/baseboard/intelrvp/baseboard.h b/baseboard/intelrvp/baseboard.h
index 5b7f969619..e47434c4af 100644
--- a/baseboard/intelrvp/baseboard.h
+++ b/baseboard/intelrvp/baseboard.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,9 +8,23 @@
 #ifndef __CROS_EC_BASEBOARD_H
 #define __CROS_EC_BASEBOARD_H
 
-#ifdef CHIP_FAMILY_IT83XX
-	#include "ite_ec.h"
-#endif /* CHIP_FAMILY_IT83XX */
+#include "compiler.h"
+#include "stdbool.h"
+
+#ifdef VARIANT_INTELRVP_EC_IT8320
+#include "ite_ec.h"
+#elif defined(VARIANT_INTELRVP_EC_MCHP)
+#include "mchp_ec.h"
+#elif defined(VARIANT_INTELRVP_EC_NPCX)
+#include "npcx_ec.h"
+#else
+#error "Define EC chip variant"
+#endif
+
+/*
+ * TODO: b/241322365 - Watchdog error are observed if LTO is enabled
+ * hence disabled it. Enable LTO once the fix is found.
+ */
 
 /*
  * Allow dangerous commands.
@@ -18,7 +32,7 @@
  */
 #define CONFIG_SYSTEM_UNLOCKED
 
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
 #undef CONFIG_HOSTCMD_DEBUG_MODE
 
 /*
@@ -41,10 +55,12 @@
 /* Port80 display */
 #define CONFIG_MAX695X_SEVEN_SEGMENT_DISPLAY
 
+/* RVP ID read retry count */
+#define RVP_VERSION_READ_RETRY_CNT 2
+
 /* Battery */
 #define CONFIG_BATTERY_CUT_OFF
 #define CONFIG_BATTERY_FUEL_GAUGE
-#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_L
 #define CONFIG_BATTERY_REVIVE_DISCONNECT
 #define CONFIG_BATTERY_SMART
 
@@ -52,16 +68,24 @@
 #define CONFIG_CHARGE_MANAGER
 #define CONFIG_CHARGER
 #define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT 512
+#define CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT 512
+#define CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT 512
 #define CONFIG_CHARGER_SENSE_RESISTOR 5
 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
-#undef  CONFIG_EXTPOWER_DEBOUNCE_MS
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
 #define CONFIG_EXTPOWER_DEBOUNCE_MS 200
 #define CONFIG_EXTPOWER_GPIO
 #define CONFIG_TRICKLE_CHARGING
 
+/*
+ * Don't allow the system to boot to S0 when the battery is low and unable to
+ * communicate on locked systems (which haven't PD negotiated)
+ */
+#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT 15000
+#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 15001
+
 /* Keyboard */
-#define CONFIG_KEYBOARD_BOARD_CONFIG
+
 #define CONFIG_KEYBOARD_PROTOCOL_8042
 #define CONFIG_KEYBOARD_COL2_INVERTED
 #define CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2
@@ -71,55 +95,46 @@
 
 /* USB-A config */
 
-/* BC1.2 config */
-#ifdef HAS_TASK_USB_CHG_P0
-	#define CONFIG_CHARGE_RAMP_HW
-#endif
-
 /* Enable USB-PD REV 3.0 */
 #define CONFIG_USB_PD_REV30
 #define CONFIG_USB_PID 0x8086
 
 /* USB PD config */
-#if defined(BOARD_TGLRVPU_ITE_TCPMV1) || defined(BOARD_TGLRVPY_ITE_TCPMV1)
-	#define CONFIG_USB_PD_TCPMV1
-#else
-	#define CONFIG_USB_DRP_ACC_TRYSRC
-	#define CONFIG_USB_PD_DECODE_SOP
-	#define CONFIG_USB_PD_TCPMV2
-	#define CONFIG_USB_PD_TCPM_MUX
-#endif
+#define CONFIG_USB_DRP_ACC_TRYSRC
+#define CONFIG_USB_PD_DECODE_SOP
+#define CONFIG_USB_PD_TCPMV2
+#define CONFIG_USB_PD_TCPM_MUX
 #define CONFIG_USB_PD_ALT_MODE
 #define CONFIG_USB_PD_ALT_MODE_DFP
 #define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT TYPEC_RP_3A0
 #define CONFIG_USB_PD_TCPM_TCPCI
 #define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_PD_VBUS_MEASURE_NOT_PRESENT
 #define CONFIG_USB_POWER_DELIVERY
+/* Treat 2nd reset from H1 as Power-On */
+#define CONFIG_BOARD_RESET_AFTER_POWER_ON
 
 /* USB MUX */
 #ifdef CONFIG_USB_MUX_VIRTUAL
-	#define CONFIG_HOSTCMD_LOCATE_CHIP
-	#define CONFIG_INTEL_VIRTUAL_MUX
+#define CONFIG_HOSTCMD_LOCATE_CHIP
 #endif
 #define CONFIG_USBC_SS_MUX
 
 /* SoC / PCH */
 #define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#define CONFIG_HOST_INTERFACE_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S5
 #define CONFIG_MKBP_EVENT
 #define CONFIG_MKBP_USE_HOST_EVENT
 #define CONFIG_POWER_BUTTON
 #define CONFIG_POWER_BUTTON_X86
 #define CONFIG_POWER_COMMON
 #define CONFIG_POWER_S0IX
+#define CONFIG_POWER_S4_RESIDENCY
 #define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
 
 /* EC */
-#define CONFIG_BOARD_VERSION_CUSTOM
 #define CONFIG_LED_COMMON
 #define CONFIG_LID_SWITCH
 #define CONFIG_VOLUME_BUTTONS
@@ -128,7 +143,6 @@
 /* Tablet mode */
 #define CONFIG_TABLET_MODE
 #define CONFIG_GMR_TABLET_MODE
-#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L
 
 /* Verified boot */
 #define CONFIG_CRC8
@@ -144,17 +158,19 @@
 
 /* Temperature sensor */
 #ifdef CONFIG_TEMP_SENSOR
-	#define CONFIG_STEINHART_HART_3V0_22K6_47K_4050B
-	#define CONFIG_THERMISTOR
-	#define CONFIG_THROTTLE_AP
+#define CONFIG_STEINHART_HART_3V0_22K6_47K_4050B
+#define CONFIG_TEMP_SENSOR_POWER
+#define GPIO_TEMP_SENSOR_POWER GPIO_EN_PP3300_A
+#define CONFIG_THERMISTOR
+#define CONFIG_THROTTLE_AP
 #ifdef CONFIG_PECI
-	#define CONFIG_PECI_COMMON
+#define CONFIG_PECI_COMMON
 #endif /* CONFIG_PECI */
 #endif /* CONFIG_TEMP_SENSOR */
 
 /* I2C ports */
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_CONTROLLER
 
 /* EC exclude modules */
 
@@ -164,13 +180,10 @@
 #include "module_id.h"
 #include "registers.h"
 
-enum tcpc_rp_value;
+FORWARD_DECLARE_ENUM(tcpc_rp_value);
 
 /* PWM channels */
-enum pwm_channel {
-	PWM_CH_FAN,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_FAN, PWM_CH_COUNT };
 
 /* FAN channels */
 enum fan_channel {
@@ -200,21 +213,14 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT,
 };
 
-/* List of supported batteries */
-enum battery_type {
-	BATTERY_SIMPLO_SMP_HHP_408,
-	BATTERY_SIMPLO_SMP_CA_445,
-	BATTERY_TYPE_COUNT,
-};
-
 /* TODO(b:132652892): Verify the below numbers. */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* Define typical operating power */
-#define PD_OPERATING_POWER_MW  15000
-#define PD_MAX_CURRENT_MA      3000
-#define PD_MAX_VOLTAGE_MV      20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_VOLTAGE_MV 20000
+#define PD_MAX_CURRENT_MA ((PD_MAX_POWER_MW / PD_MAX_VOLTAGE_MV) * 1000)
 #define DC_JACK_MAX_VOLTAGE_MV 19000
 
 /* TCPC gpios */
@@ -246,14 +252,23 @@ struct tcpc_gpio_config_t {
 };
 extern const struct tcpc_gpio_config_t tcpc_gpios[];
 
-/* Reset PD MCU */
-void board_reset_pd_mcu(void);
+struct tcpc_aic_gpio_config_t {
+	/* TCPC interrupt */
+	enum gpio_signal tcpc_alert;
+	/* PPC interrupt */
+	enum gpio_signal ppc_alert;
+	/* PPC interrupt handler */
+	void (*ppc_intr_handler)(int port);
+};
+extern const struct tcpc_aic_gpio_config_t tcpc_aic_gpios[];
+
 void board_charging_enable(int port, int enable);
 void board_vbus_enable(int port, int enable);
 void board_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp);
 int ioexpander_read_intelrvp_version(int *port0, int *port1);
 void board_dc_jack_interrupt(enum gpio_signal signal);
 void tcpc_alert_event(enum gpio_signal signal);
+bool is_typec_port(int port);
 
 #endif /* !__ASSEMBLER__ */
 
diff --git a/baseboard/intelrvp/battery.c b/baseboard/intelrvp/battery.c
deleted file mode 100644
index cf4464ce55..0000000000
--- a/baseboard/intelrvp/battery.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "battery_smart.h"
-#include "common.h"
-#include "util.h"
-
-const struct board_batt_params board_battery_info[] = {
-	/*
-	 * Simplo Battery (SMP-HHP-408) Information
-	 * Fuel gauge: BQ40Z50
-	 */
-	[BATTERY_SIMPLO_SMP_HHP_408] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP-HHP-408",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr = SB_BATTERY_STATUS,
-				.reg_mask = STATUS_INITIALIZED,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max = 8700,        /* mV */
-			.voltage_normal = 7600,
-			.voltage_min = 6100,
-			.precharge_current = 204,   /* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = 0,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/*
-	 * Simplo Battery (SMP-CA-445) Information
-	 * Fuel gauge: BQ30Z554
-	 * TODO: SYSCROS-25972
-	 */
-	[BATTERY_SIMPLO_SMP_CA_445] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP-CA-445",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr = SB_BATTERY_STATUS,
-				.reg_mask = STATUS_INITIALIZED,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max = 8700,		/* mV */
-			.voltage_normal = 7600,
-			.voltage_min = 6100,
-			.precharge_current = 150,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -20,
-			.discharging_max_c = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SIMPLO_SMP_HHP_408;
diff --git a/baseboard/intelrvp/bc12.c b/baseboard/intelrvp/bc12.c
deleted file mode 100644
index 9f212fba4e..0000000000
--- a/baseboard/intelrvp/bc12.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel BASEBOARD-RVP BC1.2 specific configuration */
-
-#include "common.h"
-#include "max14637.h"
-
-/* BC1.2 chip Configuration */
-#ifdef CONFIG_BC12_DETECT_MAX14637
-const struct max14637_config_t max14637_config[] = {
-	[TYPE_C_PORT_0] = {
-		.chip_enable_pin = GPIO_USB_C0_BC12_VBUS_ON_ODL,
-		.chg_det_pin = GPIO_USB_C0_BC12_CHG_DET_L,
-		.flags = MAX14637_FLAGS_CHG_DET_ACTIVE_LOW,
-	},
-#ifdef HAS_TASK_PD_C1
-	[TYPE_C_PORT_1] = {
-		.chip_enable_pin = GPIO_USB_C1_BC12_VBUS_ON_ODL,
-		.chg_det_pin = GPIO_USB_C1_BC12_CHG_DET_L,
-		.flags = MAX14637_FLAGS_CHG_DET_ACTIVE_LOW,
-	},
-#endif /* HAS_TASK_PD_C1 */
-};
-BUILD_ASSERT(ARRAY_SIZE(max14637_config) == CONFIG_USB_PD_PORT_MAX_COUNT);
-#endif /* CONFIG_BC12_DETECT_MAX14637 */
diff --git a/baseboard/intelrvp/build.mk b/baseboard/intelrvp/build.mk
index d48d862fd5..b4cacf4cc2 100644
--- a/baseboard/intelrvp/build.mk
+++ b/baseboard/intelrvp/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -9,18 +9,22 @@
 #Intel RVP common files
 baseboard-y=baseboard.o
 baseboard-$(CONFIG_LED_COMMON)+=led.o led_states.o
-baseboard-$(CONFIG_BATTERY_SMART)+=battery.o
-baseboard-$(CONFIG_USB_POWER_DELIVERY)+=chg_usb_pd.o usb_pd_policy.o
 
-#EC specific files
-baseboard-$(CONFIG_USB_PD_TCPM_ITE_ON_CHIP)+=ite_ec.o
-
-#BC1.2 specific files
-baseboard-$(CONFIG_BC12_DETECT_MAX14637)+=bc12.o
+ifneq ($(CONFIG_USB_POWER_DELIVERY),)
+baseboard-$(CONFIG_USB_POWER_DELIVERY)+=chg_usb_pd.o
+baseboard-$(CONFIG_INTEL_RVP_MECC_VERSION_1_0)+=chg_usb_pd_mecc_1_0.o
+baseboard-$(CONFIG_INTEL_RVP_MECC_VERSION_1_0)+=usb_pd_policy_mecc_1_0.o
+endif
 
-#USB MUX specific files
-baseboard-$(CONFIG_USB_MUX_VIRTUAL)+=usb_mux.o
-baseboard-$(CONFIG_USB_MUX_ANX7440)+=usb_mux.o
+#EC specific files
+baseboard-$(VARIANT_INTELRVP_EC_IT8320)+=ite_ec.o
+baseboard-$(VARIANT_INTELRVP_EC_MCHP)+=mchp_ec.o
+baseboard-$(VARIANT_INTELRVP_EC_NPCX)+=npcx_ec.o
 
-#USB Retimer specific files
-baseboard-$(CONFIG_USBC_RETIMER_INTEL_BB)+=retimer.o
+#Common board specific files
+ifneq ($(filter y,$(BOARD_ADLRVPP_ITE) $(BOARD_ADLRVPM_ITE) \
+		$(BOARD_ADLRVPP_MCHP1521) $(BOARD_ADLRVPP_NPCX) \
+		$(BOARD_ADLRVPP_MCHP1727)),)
+baseboard-y+=adlrvp.o
+baseboard-$(CONFIG_BATTERY_SMART)+=adlrvp_battery.o
+endif
diff --git a/baseboard/intelrvp/chg_usb_pd.c b/baseboard/intelrvp/chg_usb_pd.c
index 8620268263..60ad6e5cdb 100644
--- a/baseboard/intelrvp/chg_usb_pd.c
+++ b/baseboard/intelrvp/chg_usb_pd.c
@@ -1,124 +1,50 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-/* Intel-RVP family-specific configuration */
+/* Common USB PD charge configuration */
 
 #include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "console.h"
+#include "charge_state.h"
+#include "gpio.h"
 #include "hooks.h"
-#include "tcpci.h"
-#include "system.h"
+#include "tcpm/tcpci.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#ifdef CONFIG_ZEPHYR
+#include "intelrvp.h"
+#endif /* CONFIG_ZEPHYR */
 
-static inline int is_typec_port(int port)
-{
-	return !(port == DEDICATED_CHARGE_PORT || port == CHARGE_PORT_NONE);
-}
-
-
-int board_vbus_source_enabled(int port)
-{
-	int src_en = 0;
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
-	/* Only Type-C ports can source VBUS */
-	if (is_typec_port(port)) {
-		src_en = gpio_get_level(tcpc_gpios[port].src.pin);
-
-		src_en = tcpc_gpios[port].src.pin_pol ? src_en : !src_en;
-	}
-
-	return src_en;
-}
-
-void board_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp)
+bool is_typec_port(int port)
 {
-	int ilim_en;
-
-	/* Only Type-C ports can source VBUS */
-	if (is_typec_port(port)) {
-		/* Enable SRC ILIM if rp is MAX single source current */
-		ilim_en = (rp == CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT &&
-			board_vbus_source_enabled(port));
-
-		gpio_set_level(tcpc_gpios[port].src_ilim.pin,
-				tcpc_gpios[port].src_ilim.pin_pol ?
-				ilim_en : !ilim_en);
-	}
-}
-
-void board_charging_enable(int port, int enable)
-{
-	gpio_set_level(tcpc_gpios[port].snk.pin,
-		tcpc_gpios[port].snk.pin_pol ? enable : !enable);
-
-}
-
-void board_vbus_enable(int port, int enable)
-{
-	gpio_set_level(tcpc_gpios[port].src.pin,
-		tcpc_gpios[port].src.pin_pol ? enable : !enable);
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	int vbus_intr;
-
-	if (port == DEDICATED_CHARGE_PORT)
-		return 1;
-
-	vbus_intr = gpio_get_level(tcpc_gpios[port].vbus.pin);
-
-	return tcpc_gpios[port].vbus.pin_pol ? vbus_intr : !vbus_intr;
-}
-
-void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-	int i;
-
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		if (tcpc_gpios[i].vbus.pin == signal) {
-			port = i;
-			break;
-		}
-	}
-
-	if (port != -1)
-		schedule_deferred_pd_interrupt(port);
-}
-
-void board_tcpc_init(void)
-{
-	int i;
-
-	/* Only reset TCPC if not sysjump */
-	if (!system_jumped_late())
-		board_reset_pd_mcu();
-
-	/* Enable TCPCx interrupt */
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
-		gpio_enable_interrupt(tcpc_gpios[i].vbus.pin);
+#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
+	return !(port == DEDICATED_CHARGE_PORT || port == CHARGE_PORT_NONE);
+#else
+	return !(port == CHARGE_PORT_NONE);
+#endif /* CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 */
 }
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
 
 static inline int board_dc_jack_present(void)
 {
+#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
 	return gpio_get_level(GPIO_DC_JACK_PRESENT);
+#else
+	return 0;
+#endif
 }
 
+#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
 static void board_dc_jack_handle(void)
 {
 	struct charge_port_info charge_dc_jack;
 
 	/* System is booted from DC Jack */
 	if (board_dc_jack_present()) {
-		charge_dc_jack.current = (PD_MAX_POWER_MW * 1000) /
-					DC_JACK_MAX_VOLTAGE_MV;
+		charge_dc_jack.current =
+			(PD_MAX_POWER_MW * 1000) / DC_JACK_MAX_VOLTAGE_MV;
 		charge_dc_jack.voltage = DC_JACK_MAX_VOLTAGE_MV;
 	} else {
 		charge_dc_jack.current = 0;
@@ -126,12 +52,15 @@ static void board_dc_jack_handle(void)
 	}
 
 	charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED,
-				DEDICATED_CHARGE_PORT, &charge_dc_jack);
+				     DEDICATED_CHARGE_PORT, &charge_dc_jack);
 }
+#endif
 
 void board_dc_jack_interrupt(enum gpio_signal signal)
 {
+#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
 	board_dc_jack_handle();
+#endif
 }
 
 static void board_charge_init(void)
@@ -146,10 +75,12 @@ static void board_charge_init(void)
 	for (port = 0; port < CHARGE_PORT_COUNT; port++) {
 		for (supplier = 0; supplier < CHARGE_SUPPLIER_COUNT; supplier++)
 			charge_manager_update_charge(supplier, port,
-				&charge_init);
+						     &charge_init);
 	}
 
+#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
 	board_dc_jack_handle();
+#endif /* CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 */
 }
 DECLARE_HOOK(HOOK_INIT, board_charge_init, HOOK_PRIO_DEFAULT);
 
@@ -157,8 +88,7 @@ int board_set_active_charge_port(int port)
 {
 	int i;
 	/* charge port is a realy physical port */
-	int is_real_port = (port >= 0 &&
-			port < CHARGE_PORT_COUNT);
+	int is_real_port = (port >= 0 && port < CHARGE_PORT_COUNT);
 	/* check if we are source vbus on that port */
 	int source = board_vbus_source_enabled(port);
 
@@ -167,6 +97,7 @@ int board_set_active_charge_port(int port)
 		return EC_ERROR_INVAL;
 	}
 
+#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
 	/*
 	 * Do not enable Type-C port if the DC Jack is present.
 	 * When the Type-C is active port, hardware circuit will
@@ -176,6 +107,7 @@ int board_set_active_charge_port(int port)
 		CPRINTS("DC Jack present, Skip enable p%d", port);
 		return EC_ERROR_INVAL;
 	}
+#endif /* CONFIG_DEDICATED_CHARGE_PORT_COUNT */
 
 	/* Make sure non-charging ports are disabled */
 	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
@@ -193,10 +125,3 @@ int board_set_active_charge_port(int port)
 
 	return EC_SUCCESS;
 }
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_set_input_current_limit(MAX(charge_ma,
-				CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
diff --git a/baseboard/intelrvp/chg_usb_pd_mecc_1_0.c b/baseboard/intelrvp/chg_usb_pd_mecc_1_0.c
new file mode 100644
index 0000000000..1d18109f6f
--- /dev/null
+++ b/baseboard/intelrvp/chg_usb_pd_mecc_1_0.c
@@ -0,0 +1,114 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel-RVP family-specific configuration */
+
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "console.h"
+#include "driver/ppc/sn5s330.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "system.h"
+#include "tcpm/tcpci.h"
+#include "usbc_ppc.h"
+
+#ifdef CONFIG_ZEPHYR
+#include "intelrvp.h"
+#endif /* CONFIG_ZEPHYR */
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+/* Reset PD MCU */
+void board_reset_pd_mcu(void)
+{
+	/* Add code if TCPC chips need a reset */
+}
+
+static void baseboard_tcpc_init(void)
+{
+	int i;
+
+	/* Only reset TCPC if not sysjump */
+	if (!system_jumped_late())
+		board_reset_pd_mcu();
+
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		/* Enable PPC interrupts. */
+		if (tcpc_aic_gpios[i].ppc_intr_handler)
+			gpio_enable_interrupt(tcpc_aic_gpios[i].ppc_alert);
+
+		/* Enable TCPC interrupts. */
+		if (tcpc_config[i].bus_type != EC_BUS_TYPE_EMBEDDED)
+			gpio_enable_interrupt(tcpc_aic_gpios[i].tcpc_alert);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, baseboard_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
+
+#ifndef CONFIG_ZEPHYR
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		/* No alerts for embdeded TCPC */
+		if (tcpc_config[i].bus_type == EC_BUS_TYPE_EMBEDDED)
+			continue;
+
+		if (signal == tcpc_aic_gpios[i].tcpc_alert) {
+			schedule_deferred_pd_interrupt(i);
+			break;
+		}
+	}
+}
+#endif
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+	int i;
+
+	/* Check which port has the ALERT line set */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		/* No alerts for embdeded TCPC */
+		if (tcpc_config[i].bus_type == EC_BUS_TYPE_EMBEDDED)
+			continue;
+
+		if (!gpio_get_level(tcpc_aic_gpios[i].tcpc_alert))
+			status |= PD_STATUS_TCPC_ALERT_0 << i;
+	}
+
+	return status;
+}
+
+int ppc_get_alert_status(int port)
+{
+	if (!tcpc_aic_gpios[port].ppc_intr_handler)
+		return 0;
+
+	return !gpio_get_level(tcpc_aic_gpios[port].ppc_alert);
+}
+
+/* PPC support routines */
+void ppc_interrupt(enum gpio_signal signal)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		if (tcpc_aic_gpios[i].ppc_intr_handler &&
+		    signal == tcpc_aic_gpios[i].ppc_alert) {
+			tcpc_aic_gpios[i].ppc_intr_handler(i);
+			break;
+		}
+	}
+}
+
+void board_charging_enable(int port, int enable)
+{
+	if (ppc_vbus_sink_enable(port, enable))
+		CPRINTS("C%d: sink path %s failed", port,
+			enable ? "en" : "dis");
+}
diff --git a/baseboard/intelrvp/ite_ec.c b/baseboard/intelrvp/ite_ec.c
index 2a847e5132..76703d4f82 100644
--- a/baseboard/intelrvp/ite_ec.c
+++ b/baseboard/intelrvp/ite_ec.c
@@ -1,10 +1,11 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Intel BASEBOARD-RVP ITE EC specific configuration */
 
+#include "adc_chip.h"
 #include "common.h"
 #include "it83xx_pd.h"
 #include "keyboard_scan.h"
@@ -13,49 +14,8 @@
 #include "timer.h"
 #include "usb_pd_tcpm.h"
 
-/* USB-C TPCP Configuration */
-const struct tcpc_config_t tcpc_config[] = {
-	[TYPE_C_PORT_0] = {
-		.bus_type = EC_BUS_TYPE_EMBEDDED,
-		/* TCPC is embedded within EC so no i2c config needed */
-		.drv = &it83xx_tcpm_drv,
-#ifdef CONFIG_INTEL_VIRTUAL_MUX
-		.usb23 = TYPE_C_PORT_0_USB2_NUM | (TYPE_C_PORT_0_USB3_NUM << 4),
-#endif
-	},
-#ifdef HAS_TASK_PD_C1
-	[TYPE_C_PORT_1] = {
-		.bus_type = EC_BUS_TYPE_EMBEDDED,
-		/* TCPC is embedded within EC so no i2c config needed */
-		.drv = &it83xx_tcpm_drv,
-#ifdef CONFIG_INTEL_VIRTUAL_MUX
-		.usb23 = TYPE_C_PORT_1_USB2_NUM | (TYPE_C_PORT_1_USB3_NUM << 4),
-#endif
-	},
-#endif /* HAS_TASK_PD_C1 */
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == CONFIG_USB_PD_PORT_MAX_COUNT);
-
-/* Reset PD MCU */
-void board_reset_pd_mcu(void)
-{
-	/* Not applicable for ITE TCPC */
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	/*
-	 * Since C0/C1 TCPC are embedded within EC, we don't need the
-	 * PDCMD tasks. The (embedded) TCPC status since chip driver
-	 * code handles its own interrupts and forward the correct
-	 * events to the PD_C0 task. See it83xx/intc.c
-	 */
-
-	return 0;
-}
-
 /* Keyboard scan setting */
-struct keyboard_scan_config keyscan_config = {
+__override struct keyboard_scan_config keyscan_config = {
 	.output_settle_us = 35,
 	.debounce_down_us = 5 * MSEC,
 	.debounce_up_us = 40 * MSEC,
@@ -68,6 +28,39 @@ struct keyboard_scan_config keyscan_config = {
 	},
 };
 
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	[ADC_TEMP_SNS_AMBIENT] = {
+		.name = "ADC_TEMP_SNS_AMBIENT",
+		.factor_mul = ADC_MAX_MVOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+		.channel = ADC_TEMP_SNS_AMBIENT_CHANNEL,
+	},
+	[ADC_TEMP_SNS_DDR] = {
+		.name = "ADC_TEMP_SNS_DDR",
+		.factor_mul = ADC_MAX_MVOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+		.channel = ADC_TEMP_SNS_DDR_CHANNEL,
+	},
+	[ADC_TEMP_SNS_SKIN] = {
+		.name = "ADC_TEMP_SNS_SKIN",
+		.factor_mul = ADC_MAX_MVOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+		.channel = ADC_TEMP_SNS_SKIN_CHANNEL,
+	},
+	[ADC_TEMP_SNS_VR] = {
+		.name = "ADC_TEMP_SNS_VR",
+		.factor_mul = ADC_MAX_MVOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+		.channel = ADC_TEMP_SNS_VR_CHANNEL,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
 /*
  * PWM HW channelx binding tachometer channelx for fan control.
  * Four tachometer input pins but two tachometer modules only,
@@ -137,22 +130,24 @@ const struct pwm_t pwm_channels[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
-#ifdef CONFIG_USBC_VCONN
+#if defined(CONFIG_USBC_VCONN) && defined(CONFIG_USB_PD_TCPM_ITE_ON_CHIP)
 void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
 {
+#ifndef CONFIG_USBC_PPC_VCONN
 	/*
 	 * Setting VCONN low by disabling the power switch before
 	 * enabling the VCONN on respective CC line
 	 */
 	gpio_set_level(tcpc_gpios[port].vconn.cc1_pin,
-			!tcpc_gpios[port].vconn.pin_pol);
+		       !tcpc_gpios[port].vconn.pin_pol);
 	gpio_set_level(tcpc_gpios[port].vconn.cc2_pin,
-			!tcpc_gpios[port].vconn.pin_pol);
+		       !tcpc_gpios[port].vconn.pin_pol);
 
 	if (enabled)
 		gpio_set_level((cc_pin != USBPD_CC_PIN_1) ?
-				tcpc_gpios[port].vconn.cc2_pin :
-				tcpc_gpios[port].vconn.cc1_pin,
-				tcpc_gpios[port].vconn.pin_pol);
+				       tcpc_gpios[port].vconn.cc2_pin :
+				       tcpc_gpios[port].vconn.cc1_pin,
+			       tcpc_gpios[port].vconn.pin_pol);
+#endif
 }
 #endif
diff --git a/baseboard/intelrvp/ite_ec.h b/baseboard/intelrvp/ite_ec.h
index a09923dbb0..7ad147a5f9 100644
--- a/baseboard/intelrvp/ite_ec.h
+++ b/baseboard/intelrvp/ite_ec.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,22 +8,18 @@
 #ifndef __CROS_EC_ITE_EC_H
 #define __CROS_EC_ITE_EC_H
 
-/* USB PD config */
-#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP
-#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 2
-
 /* Optional feature - used by ITE */
 #define CONFIG_IT83XX_FLASH_CLOCK_48MHZ
+#define CONFIG_IT83XX_VCC_1P8V
 
 /* ADC channels */
-#define ADC_TEMP_SNS_AMBIENT_CHANNEL	CHIP_ADC_CH13
-#define ADC_TEMP_SNS_DDR_CHANNEL	CHIP_ADC_CH15
-#define ADC_TEMP_SNS_SKIN_CHANNEL	CHIP_ADC_CH6
-#define ADC_TEMP_SNS_VR_CHANNEL		CHIP_ADC_CH1
+#define ADC_TEMP_SNS_AMBIENT_CHANNEL CHIP_ADC_CH13
+#define ADC_TEMP_SNS_DDR_CHANNEL CHIP_ADC_CH15
+#define ADC_TEMP_SNS_SKIN_CHANNEL CHIP_ADC_CH6
+#define ADC_TEMP_SNS_VR_CHANNEL CHIP_ADC_CH1
 
 #ifdef CONFIG_USBC_VCONN
-	#define CONFIG_USBC_VCONN_SWAP
-	/* delay to turn on/off vconn */
-	#define PD_VCONN_SWAP_DELAY 5000 /* us */
+#define CONFIG_USBC_VCONN_SWAP
+/* delay to turn on/off vconn */
 #endif
 #endif /* __CROS_EC_ITE_EC_H */
diff --git a/baseboard/intelrvp/led.c b/baseboard/intelrvp/led.c
index 8e98f8e10f..10e4e08e63 100644
--- a/baseboard/intelrvp/led.c
+++ b/baseboard/intelrvp/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -14,64 +14,87 @@
 #define LED_ON_LVL 0
 #define LED_OFF_LVL 1
 
-#define GPIO_BAT_LED_RED_L GPIO_BAT_LED_GREEN_L
-#define GPIO_PWR_LED_WHITE_L GPIO_AC_LED_GREEN_L
-
 const int led_charge_lvl_1 = 5;
 
 const int led_charge_lvl_2 = 97;
 
 struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
+	[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED, LED_INDEFINITE } },
+	[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, LED_INDEFINITE } },
+	[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+					   LED_INDEFINITE } },
+	[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+	[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+	[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+	[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+				  { LED_OFF, 1 * LED_ONE_SEC } },
+	[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+				 { EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC } },
 };
 
 const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   1 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 1 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-	EC_LED_ID_BATTERY_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED,
+					     EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 void led_set_color_power(enum ec_led_colors color)
 {
 	if (color == EC_LED_COLOR_WHITE)
+#ifdef CONFIG_ZEPHYR
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_white_l),
+				LED_ON_LVL);
+#else
 		gpio_set_level(GPIO_PWR_LED_WHITE_L, LED_ON_LVL);
+#endif /* CONFIG_ZEPHYR */
 	else
-		/* LED_OFF and unsupported colors */
+	/* LED_OFF and unsupported colors */
+#ifdef CONFIG_ZEPHYR
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_white_l),
+				LED_OFF_LVL);
+#else
 		gpio_set_level(GPIO_PWR_LED_WHITE_L, LED_OFF_LVL);
+#endif /* CONFIG_ZEPHYR */
 }
 
 void led_set_color_battery(enum ec_led_colors color)
 {
 	switch (color) {
 	case EC_LED_COLOR_RED:
+#ifdef CONFIG_ZEPHYR
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_red_l), LED_ON_LVL);
+#else
 		gpio_set_level(GPIO_BAT_LED_RED_L, LED_ON_LVL);
+#endif /* CONFIG_ZEPHYR */
 		break;
 	case EC_LED_COLOR_AMBER:
+#ifdef CONFIG_ZEPHYR
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_red_l), LED_ON_LVL);
+#else
 		gpio_set_level(GPIO_BAT_LED_RED_L, LED_ON_LVL);
+#endif /* CONFIG_ZEPHYR */
 		break;
 	case EC_LED_COLOR_GREEN:
+#ifdef CONFIG_ZEPHYR
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_red_l), LED_OFF_LVL);
+#else
 		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
+#endif /* CONFIG_ZEPHYR */
 		break;
 	default: /* LED_OFF and other unsupported colors */
+#ifdef CONFIG_ZEPHYR
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_red_l), LED_OFF_LVL);
+#else
 		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
+#endif /* CONFIG_ZEPHYR */
 		break;
 	}
 }
diff --git a/baseboard/intelrvp/led_states.c b/baseboard/intelrvp/led_states.c
index 5f8768bdd9..5fdbe0c67e 100644
--- a/baseboard/intelrvp/led_states.c
+++ b/baseboard/intelrvp/led_states.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -15,15 +15,15 @@
 #include "led_common.h"
 #include "led_states.h"
 
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
 
 static enum led_states led_get_state(void)
 {
-	int  charge_lvl;
+	int charge_lvl;
 	enum led_states new_state = LED_NUM_STATES;
 
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
 		/* Get percent charge */
 		charge_lvl = charge_get_percent();
 		/* Determine which charge state to use */
@@ -34,13 +34,13 @@ static enum led_states led_get_state(void)
 		else
 			new_state = STATE_CHARGING_FULL_CHARGE;
 		break;
-	case PWR_STATE_DISCHARGE_FULL:
+	case LED_PWRS_DISCHARGE_FULL:
 		if (extpower_is_present()) {
 			new_state = STATE_CHARGING_FULL_CHARGE;
 			break;
 		}
-		/* Intentional fall-through */
-	case PWR_STATE_DISCHARGE /* and PWR_STATE_DISCHARGE_FULL */:
+		__fallthrough;
+	case LED_PWRS_DISCHARGE /* and LED_PWRS_DISCHARGE_FULL */:
 		if (chipset_in_state(CHIPSET_STATE_ON))
 			new_state = STATE_DISCHARGE_S0;
 		else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
@@ -48,17 +48,17 @@ static enum led_states led_get_state(void)
 		else
 			new_state = STATE_DISCHARGE_S5;
 		break;
-	case PWR_STATE_ERROR:
+	case LED_PWRS_ERROR:
 		new_state = STATE_BATTERY_ERROR;
 		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
+	case LED_PWRS_CHARGE_NEAR_FULL:
 		new_state = STATE_CHARGING_FULL_CHARGE;
 		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (charge_get_flags() & CHARGE_FLAG_FORCE_IDLE)
-			new_state = STATE_FACTORY_TEST;
-		else
-			new_state = STATE_DISCHARGE_S0;
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		new_state = STATE_DISCHARGE_S0;
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		new_state = STATE_FACTORY_TEST;
 		break;
 	default:
 		/* Other states don't alter LED behavior */
@@ -88,14 +88,14 @@ static void led_update_battery(void)
 		ticks = 0;
 
 		period = led_bat_state_table[led_state][LED_PHASE_0].time +
-			led_bat_state_table[led_state][LED_PHASE_1].time;
-
+			 led_bat_state_table[led_state][LED_PHASE_1].time;
 	}
 
 	/* If this state is undefined, turn the LED off */
 	if (period == 0) {
 		CPRINTS("Undefined LED behavior for battery state %d,"
-			"turning off LED", led_state);
+			"turning off LED",
+			led_state);
 		led_set_color_battery(LED_OFF);
 		return;
 	}
@@ -104,8 +104,8 @@ static void led_update_battery(void)
 	 * Determine which phase of the state table to use. The phase is
 	 * determined if it falls within first phase time duration.
 	 */
-	phase = ticks < led_bat_state_table[led_state][LED_PHASE_0].time ?
-									0 : 1;
+	phase = ticks < led_bat_state_table[led_state][LED_PHASE_0].time ? 0 :
+									   1;
 	ticks = (ticks + 1) % period;
 
 	/* Set the color for the given state and phase */
@@ -115,7 +115,7 @@ static void led_update_battery(void)
 static enum pwr_led_states pwr_led_get_state(void)
 {
 	if (extpower_is_present()) {
-		if (charge_get_state() == PWR_STATE_CHARGE_NEAR_FULL)
+		if (led_pwr_get_state() == LED_PWRS_CHARGE_NEAR_FULL)
 			return PWR_LED_STATE_OFF;
 		else
 			return PWR_LED_STATE_ON;
@@ -141,14 +141,14 @@ static void led_update_power(void)
 		ticks = 0;
 
 		period = led_pwr_state_table[led_state][LED_PHASE_0].time +
-			led_pwr_state_table[led_state][LED_PHASE_1].time;
-
+			 led_pwr_state_table[led_state][LED_PHASE_1].time;
 	}
 
 	/* If this state is undefined, turn the LED off */
 	if (period == 0) {
 		CPRINTS("Undefined LED behavior for power state %d,"
-			"turning off LED", led_state);
+			"turning off LED",
+			led_state);
 		led_set_color_power(LED_OFF);
 		return;
 	}
@@ -157,8 +157,8 @@ static void led_update_power(void)
 	 * Determine which phase of the state table to use. The phase is
 	 * determined if it falls within first phase time duration.
 	 */
-	phase = ticks < led_pwr_state_table[led_state][LED_PHASE_0].time ?
-									0 : 1;
+	phase = ticks < led_pwr_state_table[led_state][LED_PHASE_0].time ? 0 :
+									   1;
 	ticks = (ticks + 1) % period;
 
 	/* Set the color for the given state and phase */
diff --git a/baseboard/intelrvp/led_states.h b/baseboard/intelrvp/led_states.h
index 907ff5c8b8..3b584c6efc 100644
--- a/baseboard/intelrvp/led_states.h
+++ b/baseboard/intelrvp/led_states.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,19 +10,15 @@
 
 #include "ec_commands.h"
 
-#define LED_INDEFINITE	UINT8_MAX
-#define LED_ONE_SEC	(1000 / HOOK_TICK_INTERVAL_MS)
-#define LED_OFF         EC_LED_COLOR_COUNT
+#define LED_INDEFINITE UINT8_MAX
+#define LED_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS)
+#define LED_OFF EC_LED_COLOR_COUNT
 
 /*
  * All LED states should have one phase defined,
  * and an additional phase can be defined for blinking
  */
-enum led_phase {
-	LED_PHASE_0,
-	LED_PHASE_1,
-	LED_NUM_PHASES
-};
+enum led_phase { LED_PHASE_0, LED_PHASE_1, LED_NUM_PHASES };
 
 /*
  * STATE_CHARGING_LVL_1 is when 0 <= charge_percentage < led_charge_level_1
@@ -51,10 +47,8 @@ struct led_descriptor {
 	uint8_t time;
 };
 
-
 /* Charging LED state table - defined in board's led.c */
-extern struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES];
+extern struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES];
 
 /* Charging LED state level 1 - defined in board's led.c */
 extern const int led_charge_lvl_1;
@@ -71,8 +65,8 @@ enum pwr_led_states {
 };
 
 /* Power LED state table - defined in board's led.c */
-extern const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES];
+extern const struct led_descriptor led_pwr_state_table[PWR_LED_NUM_STATES]
+						      [LED_NUM_PHASES];
 
 /**
  * Set battery LED color - defined in board's led.c
diff --git a/baseboard/intelrvp/mchp_ec.c b/baseboard/intelrvp/mchp_ec.c
new file mode 100644
index 0000000000..7ede17569b
--- /dev/null
+++ b/baseboard/intelrvp/mchp_ec.c
@@ -0,0 +1,88 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel BASEBOARD-RVP MCHP EC specific configuration */
+
+#include "adc_chip.h"
+#include "common.h"
+#include "keyboard_scan.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "timer.h"
+#include "usb_pd_tcpm.h"
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/*
+	 * F3 key scan cycle completed but scan input is not
+	 * charging to logic high when EC start scan next
+	 * column for "T" key, so we set .output_settle_us
+	 * to 80 us from 50 us.
+	 */
+	.output_settle_us = 80,
+	.debounce_down_us = 9 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
+		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
+	},
+};
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	[ADC_TEMP_SNS_AMBIENT] = {
+		.name = "ADC_TEMP_SNS_AMBIENT",
+		.factor_mul = ADC_MAX_MVOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+		.channel = ADC_TEMP_SNS_AMBIENT_CHANNEL,
+	},
+	[ADC_TEMP_SNS_DDR] = {
+		.name = "ADC_TEMP_SNS_DDR",
+		.factor_mul = ADC_MAX_MVOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+		.channel = ADC_TEMP_SNS_DDR_CHANNEL,
+	},
+	[ADC_TEMP_SNS_SKIN] = {
+		.name = "ADC_TEMP_SNS_SKIN",
+		.factor_mul = ADC_MAX_MVOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+		.channel = ADC_TEMP_SNS_SKIN_CHANNEL,
+	},
+	[ADC_TEMP_SNS_VR] = {
+		.name = "ADC_TEMP_SNS_VR",
+		.factor_mul = ADC_MAX_MVOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+		.channel = ADC_TEMP_SNS_VR_CHANNEL,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/*
+ * TODO - Fan and tach table.
+ * MCHP MEC1322 and MEC170x have fan speed controller(s)
+ * whereas MEC152x only has multiple TACH and PWM modules.
+ * MEC152x fan control will require a firmware layer that uses
+ * specified TACH and PWM modules.
+ */
+
+/* PWM channels */
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_FAN] = {
+#ifdef CHIP_FAMILY_MEC172X
+		.channel = PWM_HW_CH_0,
+#else
+		.channel = PWM_HW_CH_4,
+#endif
+		.flags = PWM_CONFIG_HAS_RPM_MODE,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
diff --git a/baseboard/intelrvp/mchp_ec.h b/baseboard/intelrvp/mchp_ec.h
new file mode 100644
index 0000000000..ec1e47c030
--- /dev/null
+++ b/baseboard/intelrvp/mchp_ec.h
@@ -0,0 +1,26 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel BASEBOARD-RVP MCHP EC specific configuration */
+
+#ifndef __CROS_EC_MCHP_EC_H
+#define __CROS_EC_MCHP_EC_H
+
+/* ADC channels */
+#define ADC_TEMP_SNS_AMBIENT_CHANNEL CHIP_ADC_CH7
+#define ADC_TEMP_SNS_DDR_CHANNEL CHIP_ADC_CH4
+#define ADC_TEMP_SNS_SKIN_CHANNEL CHIP_ADC_CH3
+#define ADC_TEMP_SNS_VR_CHANNEL CHIP_ADC_CH1
+
+/*
+ * ADC maximum voltage is a board level configuration.
+ * MEC152x ADC can use an external 3.0 or 3.3V reference with
+ * maximum values up to the reference voltage.
+ * The ADC maximum voltage depends upon the external reference
+ * voltage connected to MEC152x.
+ */
+#define ADC_MAX_MVOLT 3000
+
+#endif /* __CROS_EC_MCHP_EC_H */
diff --git a/baseboard/intelrvp/npcx_ec.c b/baseboard/intelrvp/npcx_ec.c
new file mode 100644
index 0000000000..a90442e8b1
--- /dev/null
+++ b/baseboard/intelrvp/npcx_ec.c
@@ -0,0 +1,78 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel BASEBOARD-RVP NPCX EC specific configuration */
+
+#include "adc_chip.h"
+#include "fan_chip.h"
+#include "keyboard_scan.h"
+#include "pwm_chip.h"
+#include "time.h"
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	.output_settle_us = 35,
+	.debounce_down_us = 5 * MSEC,
+	.debounce_up_us = 40 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
+		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
+	},
+};
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	[ADC_TEMP_SNS_AMBIENT] = {
+		.name = "ADC_TEMP_SNS_AMBIENT",
+		.factor_mul = ADC_MAX_MVOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+		.input_ch = ADC_TEMP_SNS_AMBIENT_CHANNEL,
+	},
+	[ADC_TEMP_SNS_DDR] = {
+		.name = "ADC_TEMP_SNS_DDR",
+		.factor_mul = ADC_MAX_MVOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+		.input_ch = ADC_TEMP_SNS_DDR_CHANNEL,
+	},
+	[ADC_TEMP_SNS_SKIN] = {
+		.name = "ADC_TEMP_SNS_SKIN",
+		.factor_mul = ADC_MAX_MVOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+		.input_ch = ADC_TEMP_SNS_SKIN_CHANNEL,
+	},
+	[ADC_TEMP_SNS_VR] = {
+		.name = "ADC_TEMP_SNS_VR",
+		.factor_mul = ADC_MAX_MVOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+		.input_ch = ADC_TEMP_SNS_VR_CHANNEL,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* PWM configuration */
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_FAN] = {
+		.channel = PWN_FAN_CHANNEL,
+		.flags = 0,
+		.freq = 30000,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+const struct mft_t mft_channels[] = {
+	[MFT_CH_0] = {
+		.module = NPCX_MFT_MODULE_2,
+		.clk_src = TCKC_LFCLK,
+		.pwm_id = PWM_CH_FAN,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
diff --git a/baseboard/intelrvp/npcx_ec.h b/baseboard/intelrvp/npcx_ec.h
new file mode 100644
index 0000000000..5fe6aa9786
--- /dev/null
+++ b/baseboard/intelrvp/npcx_ec.h
@@ -0,0 +1,38 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel BASEBOARD-RVP NPCX EC specific configuration */
+
+#ifndef __CROS_EC_NPCX_EC_H
+#define __CROS_EC_NPCX_EC_H
+
+#if !defined(__ASSEMBLER__)
+
+enum mft_channel {
+	MFT_CH_0 = 0,
+	/* Number of MFT channels */
+	MFT_CH_COUNT,
+};
+
+#endif /* __ASSEMBLER__ */
+
+/* ADC channels */
+#define ADC_MAX_MVOLT ADC_MAX_VOLT
+#define ADC_TEMP_SNS_AMBIENT_CHANNEL NPCX_ADC_CH3
+#define ADC_TEMP_SNS_DDR_CHANNEL NPCX_ADC_CH4
+#define ADC_TEMP_SNS_SKIN_CHANNEL NPCX_ADC_CH2
+#define ADC_TEMP_SNS_VR_CHANNEL NPCX_ADC_CH1
+
+/* KSO2 is inverted */
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+
+/* Fan */
+#define CONFIG_PWM
+#define PWN_FAN_CHANNEL 3
+
+/* GPIO64/65 are used as UART pins. */
+#define NPCX_UART_MODULE2 1
+
+#endif /* __CROS_EC_NPCX_EC_H */
diff --git a/baseboard/intelrvp/retimer.c b/baseboard/intelrvp/retimer.c
deleted file mode 100644
index c64ad64bcb..0000000000
--- a/baseboard/intelrvp/retimer.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel BASEBOARD-RVP Retimer specific configuration */
-
-#include "bb_retimer.h"
-#include "compile_time_macros.h"
-#include "common.h"
-
-/* USB Retimers configuration */
-#ifdef CONFIG_USBC_RETIMER_INTEL_BB
-const struct bb_usb_control bb_controls[] = {
-	[TYPE_C_PORT_0] = {
-		.usb_ls_en_gpio = GPIO_USB_C0_LS_EN,
-		.retimer_rst_gpio = GPIO_USB_C0_RETIMER_RST,
-	},
-#ifdef HAS_TASK_PD_C1
-	[TYPE_C_PORT_1] = {
-		.usb_ls_en_gpio = GPIO_USB_C1_LS_EN,
-		.retimer_rst_gpio = GPIO_USB_C1_RETIMER_RST,
-	},
-#endif /* HAS_TASK_PD_C1 */
-};
-BUILD_ASSERT(ARRAY_SIZE(bb_controls) == CONFIG_USB_PD_PORT_MAX_COUNT);
-
-#endif /* CONFIG_USBC_RETIMER_INTEL_BB */
diff --git a/baseboard/intelrvp/usb_mux.c b/baseboard/intelrvp/usb_mux.c
deleted file mode 100644
index 644ae1735c..0000000000
--- a/baseboard/intelrvp/usb_mux.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel BASEBOARD-RVP USB MUX specific configuration */
-
-#include "common.h"
-#include "anx7440.h"
-#include "bb_retimer.h"
-#include "timer.h"
-#include "usb_mux.h"
-
-#ifdef CONFIG_USBC_RETIMER_INTEL_BB
-struct usb_mux usbc0_retimer = {
-	.usb_port = TYPE_C_PORT_0,
-	.driver = &bb_usb_retimer,
-	.i2c_port = I2C_PORT0_BB_RETIMER,
-	.i2c_addr_flags = I2C_PORT0_BB_RETIMER_ADDR,
-};
-#ifdef HAS_TASK_PD_C1
-struct usb_mux usbc1_retimer = {
-	.usb_port = TYPE_C_PORT_1,
-	.driver = &bb_usb_retimer,
-	.i2c_port = I2C_PORT1_BB_RETIMER,
-	.i2c_addr_flags = I2C_PORT1_BB_RETIMER_ADDR,
-};
-#endif /* HAS_TASK_PD_C1 */
-#endif
-
-/* USB muxes Configuration */
-#ifdef CONFIG_USB_MUX_VIRTUAL
-const struct usb_mux usb_muxes[] = {
-	[TYPE_C_PORT_0] = {
-		.usb_port = TYPE_C_PORT_0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-#ifdef CONFIG_USBC_RETIMER_INTEL_BB
-		.next_mux = &usbc0_retimer,
-#endif
-	},
-#ifdef HAS_TASK_PD_C1
-	[TYPE_C_PORT_1] = {
-		.usb_port = TYPE_C_PORT_1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-#ifdef CONFIG_USBC_RETIMER_INTEL_BB
-		.next_mux = &usbc1_retimer,
-#endif
-	},
-#endif /* HAS_TASK_PD_C1 */
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == CONFIG_USB_PD_PORT_MAX_COUNT);
-#endif /* CONFIG_USB_MUX_VIRTUAL */
-
-#ifdef CONFIG_USB_MUX_ANX7440
-const struct usb_mux usb_muxes[] = {
-	[TYPE_C_PORT_0] = {
-		.usb_port = TYPE_C_PORT_0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = I2C_ADDR_USB_MUX0_FLAGS,
-		.driver = &anx7440_usb_mux_driver,
-#ifdef CONFIG_USBC_RETIMER_INTEL_BB
-		.next_mux = &usbc0_retimer,
-#endif
-	},
-#ifdef HAS_TASK_PD_C1
-	[TYPE_C_PORT_1] = {
-		.usb_port = TYPE_C_PORT_1,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = I2C_ADDR_USB_MUX1_FLAGS,
-		.driver = &anx7440_usb_mux_driver,
-#ifdef CONFIG_USBC_RETIMER_INTEL_BB
-		.next_mux = &usbc1_retimer,
-#endif
-	},
-#endif /* HAS_TASK_PD_C1 */
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == CONFIG_USB_PD_PORT_MAX_COUNT);
-#endif /* CONFIG_USB_MUX_ANX7440 */
diff --git a/baseboard/intelrvp/usb_pd_policy.c b/baseboard/intelrvp/usb_pd_policy.c
deleted file mode 100644
index d0ca3d6025..0000000000
--- a/baseboard/intelrvp/usb_pd_policy.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "charge_manager.h"
-#include "console.h"
-#include "gpio.h"
-#include "system.h"
-#include "usb_mux.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_set_power_supply_ready(int port)
-{
-	/* Disable charging */
-	board_charging_enable(port, 0);
-
-	/* Provide VBUS */
-	board_vbus_enable(port, 1);
-
-	/* Ensure we advertise the proper available current quota */
-	charge_manager_source_port(port, 1);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS; /* we are ready */
-}
-
-void pd_power_supply_reset(int port)
-{
-	/* Disable VBUS */
-	board_vbus_enable(port, 0);
-
-	/* Give back the current quota we are no longer using */
-	charge_manager_source_port(port, 0);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_check_vconn_swap(int port)
-{
-	/* Only allow vconn swap if PP5000 rail is enabled */
-	return gpio_get_level(GPIO_EN_PP5000);
-}
-
-__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	board_set_vbus_source_current_limit(port, rp);
-}
diff --git a/baseboard/intelrvp/usb_pd_policy_mecc_1_0.c b/baseboard/intelrvp/usb_pd_policy_mecc_1_0.c
new file mode 100644
index 0000000000..303d176405
--- /dev/null
+++ b/baseboard/intelrvp/usb_pd_policy_mecc_1_0.c
@@ -0,0 +1,76 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "console.h"
+#include "gpio.h"
+#include "system.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+
+#ifdef CONFIG_ZEPHYR
+#include "intelrvp.h"
+#endif /* CONFIG_ZEPHYR */
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	/* Disable charging. */
+	rv = ppc_vbus_sink_enable(port, 0);
+	if (rv)
+		return rv;
+
+	pd_set_vbus_discharge(port, 0);
+
+	/* Provide Vbus. */
+	rv = ppc_vbus_source_enable(port, 1);
+	if (rv)
+		return rv;
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+void pd_power_supply_reset(int port)
+{
+	int prev_en;
+
+	prev_en = board_vbus_source_enabled(port);
+
+	/* Disable VBUS. */
+	ppc_vbus_source_enable(port, 0);
+
+	/* Enable discharge if we were previously sourcing 5V */
+	if (prev_en)
+		pd_set_vbus_discharge(port, 1);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_check_vconn_swap(int port)
+{
+	/* Only allow vconn swap if PP3300 rail is enabled */
+	return gpio_get_level(GPIO_EN_PP3300_A);
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	return ppc_is_vbus_present(port);
+}
+
+int board_vbus_source_enabled(int port)
+{
+	if (is_typec_port(port))
+		return ppc_is_sourcing_vbus(port);
+	return 0;
+}
diff --git a/baseboard/ite_evb/baseboard.c b/baseboard/ite_evb/baseboard.c
index 0bd537ef4f..f2077197ff 100644
--- a/baseboard/ite_evb/baseboard.c
+++ b/baseboard/ite_evb/baseboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,6 +25,8 @@
 #include "timer.h"
 #include "uart.h"
 #include "util.h"
+
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 #if defined(CONFIG_FANS) || defined(CONFIG_PWM)
@@ -42,8 +44,10 @@ const struct fan_rpm fan_rpm_0 = {
 };
 
 const struct fan_t fans[] = {
-	{ .conf = &fan_conf_0,
-	  .rpm = &fan_rpm_0, },
+	{
+		.conf = &fan_conf_0,
+		.rpm = &fan_rpm_0,
+	},
 };
 BUILD_ASSERT(ARRAY_SIZE(fans) == CONFIG_FANS);
 
@@ -106,9 +110,8 @@ const struct fan_tach_t fan_tach[] = {
 BUILD_ASSERT(ARRAY_SIZE(fan_tach) == PWM_HW_CH_TOTAL);
 #endif /* defined(CONFIG_FANS) || defined(CONFIG_PWM) */
 
-#if defined(CONFIG_KEYBOARD_BOARD_CONFIG)
 /* Keyboard scan setting */
-struct keyboard_scan_config keyscan_config = {
+__override struct keyboard_scan_config keyscan_config = {
 	.output_settle_us = 35,
 	.debounce_down_us = 5 * MSEC,
 	.debounce_up_us = 40 * MSEC,
@@ -120,16 +123,13 @@ struct keyboard_scan_config keyscan_config = {
 		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
 	},
 };
-#endif
 
 #if defined(CONFIG_SPI_FLASH_PORT)
 /* SPI devices */
 const struct spi_device_t spi_devices[] = {
-	[CONFIG_SPI_FLASH_PORT] = {
-		.port = CONFIG_SPI_FLASH_PORT,
-		.div = 0,
-		.gpio_cs = -1
-	},
+	[CONFIG_SPI_FLASH_PORT] = { .port = CONFIG_SPI_FLASH_PORT,
+				    .div = 0,
+				    .gpio_cs = -1 },
 };
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 #endif
@@ -141,9 +141,8 @@ static void board_init(void)
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
 /* Wake-up pins for hibernate */
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_POWER_BUTTON_L, GPIO_LID_OPEN
-};
+const enum gpio_signal hibernate_wake_pins[] = { GPIO_POWER_BUTTON_L,
+						 GPIO_LID_OPEN };
 const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 
 /*
diff --git a/baseboard/ite_evb/baseboard.h b/baseboard/ite_evb/baseboard.h
index 34c4fee278..5140e22962 100644
--- a/baseboard/ite_evb/baseboard.h
+++ b/baseboard/ite_evb/baseboard.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,10 +13,11 @@
 #define CONFIG_BOARD_VERSION_GPIO
 #define CONFIG_FANS 1
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_CONTROLLER
 #define CONFIG_IT83XX_ENABLE_MOUSE_DEVICE
 #define CONFIG_IT83XX_SMCLK2_ON_GPC7
-#define CONFIG_KEYBOARD_BOARD_CONFIG
+#define CONFIG_IT83XX_VCC_3P3V
+
 #define CONFIG_KEYBOARD_PROTOCOL_8042
 #define CONFIG_LOW_POWER_IDLE
 #define CONFIG_LOW_POWER_S0
@@ -26,15 +27,14 @@
 #define CONFIG_POWER_BUTTON
 #define CONFIG_PWM
 /* Use CS0 of SSPI */
-#define CONFIG_SPI_MASTER
+#define CONFIG_SPI_CONTROLLER
 #define CONFIG_SPI_FLASH_PORT 0
 #define CONFIG_UART_HOST
-#define CONFIG_HOSTCMD_LPC
+#define CONFIG_HOST_INTERFACE_LPC
 
 /* Optional console commands */
 #define CONFIG_CMD_FLASH
 #define CONFIG_CMD_SCRATCHPAD
-#define CONFIG_CMD_STACKOVERFLOW
 
 /* Debug */
 #undef CONFIG_CMD_FORCETIME
diff --git a/baseboard/ite_evb/build.mk b/baseboard/ite_evb/build.mk
index 77352145ee..38a49ff8b6 100644
--- a/baseboard/ite_evb/build.mk
+++ b/baseboard/ite_evb/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -7,4 +7,4 @@
 #
 
 baseboard-y=baseboard.o
-baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
+baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o usb_pd_pdo.o
diff --git a/baseboard/ite_evb/usb_pd_pdo.c b/baseboard/ite_evb/usb_pd_pdo.c
new file mode 100644
index 0000000000..0da735e458
--- /dev/null
+++ b/baseboard/ite_evb/usb_pd_pdo.c
@@ -0,0 +1,24 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "compile_time_macros.h"
+#include "usb_pd.h"
+#include "usb_pd_pdo.h"
+
+#define PDO_FIXED_FLAGS                                                        \
+	(PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP | PDO_FIXED_UNCONSTRAINED | \
+	 PDO_FIXED_COMM_CAP)
+
+const uint32_t pd_src_pdo[] = {
+	PDO_FIXED(5000, 1500, PDO_FIXED_FLAGS),
+};
+const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
+
+const uint32_t pd_snk_pdo[] = {
+	PDO_FIXED(5000, 500, PDO_FIXED_FLAGS),
+	PDO_BATT(4500, 14000, 10000),
+	PDO_VAR(4500, 14000, 3000),
+};
+const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
diff --git a/baseboard/ite_evb/usb_pd_pdo.h b/baseboard/ite_evb/usb_pd_pdo.h
new file mode 100644
index 0000000000..4b19ca32d3
--- /dev/null
+++ b/baseboard/ite_evb/usb_pd_pdo.h
@@ -0,0 +1,20 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_BASEBOARD_ITE_EVB_USB_PD_PDO_H
+#define __CROS_EC_BASEBOARD_ITE_EVB_USB_PD_PDO_H
+
+#include "config.h"
+#include "stdint.h"
+
+/* Threshold voltage of VBUS provided (mV) */
+#define PD_VBUS_PROVIDED_THRESHOLD 3900
+
+extern const uint32_t pd_src_pdo[1];
+extern const int pd_src_pdo_cnt;
+extern const uint32_t pd_snk_pdo[3];
+extern const int pd_snk_pdo_cnt;
+
+#endif /* __CROS_EC_BASEBOARD_ITE_EVB_USB_PD_PDO_H */
diff --git a/baseboard/ite_evb/usb_pd_policy.c b/baseboard/ite_evb/usb_pd_policy.c
index 59f3da13f5..c7d10787bb 100644
--- a/baseboard/ite_evb/usb_pd_policy.c
+++ b/baseboard/ite_evb/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,8 +6,8 @@
 /* Shared USB-C policy for ite_evb baseboard */
 
 #include "adc.h"
-#include "config.h"
 #include "common.h"
+#include "config.h"
 #include "console.h"
 #include "gpio.h"
 #include "hooks.h"
@@ -16,32 +16,12 @@
 #include "system.h"
 #include "task.h"
 #include "timer.h"
-#include "util.h"
 #include "usb_mux.h"
+#include "usb_pd_pdo.h"
+#include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-/* ---------------- Power Data Objects (PDOs) ----------------- */
-#ifdef CONFIG_USB_PD_CUSTOM_PDO
-#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\
-			 PDO_FIXED_UNCONSTRAINED  | PDO_FIXED_COMM_CAP)
-
-/* Threshold voltage of VBUS provided (mV) */
-#define PD_VBUS_PROVIDED_THRESHOLD 3900
-
-const uint32_t pd_src_pdo[] = {
-	PDO_FIXED(5000, 1500, PDO_FIXED_FLAGS),
-};
-const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
-
-const uint32_t pd_snk_pdo[] = {
-	PDO_FIXED(5000, 500, PDO_FIXED_FLAGS),
-	PDO_BATT(4500, 14000, 10000),
-	PDO_VAR(4500, 14000, 3000),
-};
-const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
-#endif
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_is_max_request_allowed(void)
 {
@@ -82,7 +62,6 @@ void pd_power_supply_reset(int port)
 	board_pd_vbus_ctrl(port, 0);
 }
 
-
 __override int pd_check_data_swap(int port, enum pd_data_role data_role)
 {
 	/* Always allow data swap: we can be DFP or UFP for USB */
@@ -127,7 +106,7 @@ __override void svdm_exit_dp_mode(int port)
 }
 
 __override int pd_custom_vdm(int port, int cnt, uint32_t *payload,
-				uint32_t **rpayload)
+			     uint32_t **rpayload)
 {
 	/* Return length 0, means nothing needn't tx */
 	return 0;
diff --git a/baseboard/kalista/baseboard.c b/baseboard/kalista/baseboard.c
index 6592033c83..7972dcdcb7 100644
--- a/baseboard/kalista/baseboard.c
+++ b/baseboard/kalista/baseboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,23 +6,23 @@
 /* Kalista baseboard configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "baseboard.h"
 #include "battery.h"
 #include "bd99992gw.h"
 #include "board_config.h"
 #include "button.h"
+#include "cec.h"
 #include "chipset.h"
 #include "console.h"
 #include "cros_board_info.h"
+#include "driver/cec/bitbang.h"
 #include "driver/pmic_tps650x30.h"
-#include "driver/temp_sensor/tmp432.h"
 #include "driver/tcpm/ps8xxx.h"
 #include "driver/tcpm/tcpci.h"
 #include "driver/tcpm/tcpm.h"
+#include "driver/temp_sensor/tmp432.h"
 #include "espi.h"
 #include "extpower.h"
-#include "espi.h"
 #include "fan.h"
 #include "fan_chip.h"
 #include "gpio.h"
@@ -49,8 +49,8 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static uint8_t board_version;
 static uint32_t oem;
@@ -89,6 +89,7 @@ void vbus0_evt(enum gpio_signal signal)
 	task_wake(TASK_ID_PD_C0);
 }
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /* Hibernate wake configuration */
@@ -100,14 +101,15 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* Vbus sensing (1/10 voltage divider). */
-	[ADC_VBUS] = {"VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
+	[ADC_VBUS] = { "VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT * 10,
+		       ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* TODO: Verify fan control and mft */
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_FAN_PWR_EN,
 };
@@ -124,19 +126,48 @@ const struct fan_t fans[] = {
 BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
 
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN },
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
-const struct i2c_port_t i2c_ports[]  = {
-	{"tcpc", I2C_PORT_TCPC0, 400, GPIO_I2C0_0_SCL, GPIO_I2C0_0_SDA},
-	{"eeprom", I2C_PORT_EEPROM, 400, GPIO_I2C0_1_SCL, GPIO_I2C0_1_SDA},
-	{"backlight", I2C_PORT_BACKLIGHT, 100, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"pmic", I2C_PORT_PMIC, 400, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-	{"thermal", I2C_PORT_THERMAL, 400, GPIO_I2C3_SCL, GPIO_I2C3_SDA},
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "tcpc",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_0_SCL,
+	  .sda = GPIO_I2C0_0_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_1_SCL,
+	  .sda = GPIO_I2C0_1_SDA },
+	{ .name = "backlight",
+	  .port = I2C_PORT_BACKLIGHT,
+	  .kbps = 100,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "pmic",
+	  .port = I2C_PORT_PMIC,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "thermal",
+	  .port = I2C_PORT_THERMAL,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
+/* CEC ports */
+const struct cec_config_t cec_config[] = {
+	[CEC_PORT_0] = {
+		.drv = &bitbang_cec_drv,
+		.offline_policy = NULL,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(cec_config) == CEC_PORT_COUNT);
+
 /* TCPC mux configuration */
 const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	/* Alert is active-low, push-pull */
@@ -157,12 +188,15 @@ static int ps8751_tune_mux(const struct usb_mux *me)
 	return EC_SUCCESS;
 }
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-		.board_init = &ps8751_tune_mux,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+				.board_init = &ps8751_tune_mux,
+			},
 	},
 };
 
@@ -204,14 +238,15 @@ void board_tcpc_init(void)
 	 * HPD pulse to enable video path
 	 */
 	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		usb_mux_hpd_update(port, 0, 0);
+		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
 
 uint16_t tcpc_get_alert_status(void)
 {
 	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL) &&
-			gpio_get_level(GPIO_USB_C0_PD_RST_ODL))
+	    gpio_get_level(GPIO_USB_C0_PD_RST_ODL))
 		return PD_STATUS_TCPC_ALERT_0;
 	return 0;
 }
@@ -224,10 +259,10 @@ uint16_t tcpc_get_alert_status(void)
  *     src/mainboard/google/${board}/acpi/dptf.asl
  */
 const struct temp_sensor_t temp_sensors[] = {
-	{"TMP431_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-			TMP432_IDX_LOCAL},
-	{"TMP431_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-			TMP432_IDX_REMOTE1},
+	{ "TMP431_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
+	  TMP432_IDX_LOCAL },
+	{ "TMP431_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
+	  TMP432_IDX_REMOTE1 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -235,14 +270,18 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
  * Thermal limits for each temp sensor.  All temps are in degrees K.  Must be in
  * same order as enum temp_sensor_id.  To always ignore any temp, use 0.
  */
+static const int temp_fan_off = C_TO_K(30);
+static const int temp_fan_max = C_TO_K(55);
 struct ec_thermal_config thermal_params[] = {
 	/* {Twarn, Thigh, Thalt}, <on>
 	 * {Twarn, Thigh, X    }, <off>
 	 * fan_off, fan_max
 	 */
-	{{0, C_TO_K(80), C_TO_K(81)}, {0, C_TO_K(78), 0},
-		C_TO_K(4), C_TO_K(76)},	/* TMP431_Internal */
-	{{0, 0, 0}, {0, 0, 0}, 0, 0},	/* TMP431_Sensor_1 */
+	{ { 0, C_TO_K(80), C_TO_K(81) },
+	  { 0, C_TO_K(78), 0 },
+	  temp_fan_off,
+	  temp_fan_max }, /* TMP431_Internal */
+	{ { 0, 0, 0 }, { 0, 0, 0 }, 0, 0 }, /* TMP431_Sensor_1 */
 };
 BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
 
@@ -411,34 +450,38 @@ int64_t get_time_dsw_pwrok(void)
 }
 
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED_RED]  = { 3, PWM_CONFIG_DSLEEP, 100 },
+	[PWM_CH_LED_RED] = { 3, PWM_CONFIG_DSLEEP, 100 },
 	[PWM_CH_LED_BLUE] = { 5, PWM_CONFIG_DSLEEP, 100 },
-	[PWM_CH_FAN] = {4, PWM_CONFIG_OPEN_DRAIN, 25000},
+	[PWM_CH_FAN] = { 4, PWM_CONFIG_OPEN_DRAIN, 25000 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
-struct fan_step {
-	int on;
-	int off;
-	int rpm;
-};
-
-/* Note: Do not make the fan on/off point equal to 0 or 100 */
-static const struct fan_step fan_table0[] = {
-	{.on =  0, .off =  5, .rpm = 0},
-	{.on = 30, .off =  5, .rpm = 2180},
-	{.on = 49, .off = 46, .rpm = 2680},
-	{.on = 53, .off = 50, .rpm = 3300},
-	{.on = 58, .off = 54, .rpm = 3760},
-	{.on = 63, .off = 59, .rpm = 4220},
-	{.on = 68, .off = 64, .rpm = 4660},
-	{.on = 75, .off = 70, .rpm = 4900},
+static const struct fan_step_1_1 fan_table0[] = {
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(30),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(37),
+	  .rpm = 2180 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(36),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(41),
+	  .rpm = 2680 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(40),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(43),
+	  .rpm = 3300 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(42),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(45),
+	  .rpm = 3760 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(44),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(47),
+	  .rpm = 4220 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(46),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(49),
+	  .rpm = 4660 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(48),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(55),
+	  .rpm = 4900 },
 };
-/* All fan tables must have the same number of levels */
 #define NUM_FAN_LEVELS ARRAY_SIZE(fan_table0)
 
-static const struct fan_step *fan_table = fan_table0;
-
+static const struct fan_step_1_1 *fan_table = fan_table0;
 
 static void cbi_init(void)
 {
@@ -459,8 +502,8 @@ DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1);
 
 static void setup_bj(void)
 {
-	enum bj_adapter bj = (BJ_ADAPTER_135W_MASK & (1 << sku)) ?
-			BJ_135W_19V : BJ_90W_19V;
+	enum bj_adapter bj = (BJ_ADAPTER_135W_MASK & (1 << sku)) ? BJ_135W_19V :
+								   BJ_90W_19V;
 	gpio_set_level(GPIO_U22_90W, bj == BJ_90W_19V);
 }
 
@@ -474,43 +517,8 @@ static void board_init(void)
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
-int fan_percent_to_rpm(int fan, int pct)
+int fan_percent_to_rpm(int fan, int temp_ratio)
 {
-	static int current_level;
-	static int previous_pct;
-	int i;
-
-	/*
-	 * Compare the pct and previous pct, we have the three paths :
-	 *  1. decreasing path. (check the off point)
-	 *  2. increasing path. (check the on point)
-	 *  3. invariant path. (return the current RPM)
-	 */
-	if (pct < previous_pct) {
-		for (i = current_level; i >= 0; i--) {
-			if (pct <= fan_table[i].off)
-				current_level = i - 1;
-			else
-				break;
-		}
-	} else if (pct > previous_pct) {
-		for (i = current_level + 1; i < NUM_FAN_LEVELS; i++) {
-			if (pct >= fan_table[i].on)
-				current_level = i;
-			else
-				break;
-		}
-	}
-
-	if (current_level < 0)
-		current_level = 0;
-
-	previous_pct = pct;
-
-	if (fan_table[current_level].rpm !=
-		fan_get_rpm_target(FAN_CH(fan)))
-		cprints(CC_THERMAL, "Setting fan RPM to %d",
-			fan_table[current_level].rpm);
-
-	return fan_table[current_level].rpm;
+	return temp_ratio_to_rpm_hysteresis(fan_table, NUM_FAN_LEVELS, fan,
+					    temp_ratio, NULL);
 }
diff --git a/baseboard/kalista/baseboard.h b/baseboard/kalista/baseboard.h
index ede6388b39..fc40207526 100644
--- a/baseboard/kalista/baseboard.h
+++ b/baseboard/kalista/baseboard.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,7 +12,7 @@
  * Allow dangerous commands.
  * TODO: Remove this config before production.
  */
-#undef  CONFIG_SYSTEM_UNLOCKED
+#undef CONFIG_SYSTEM_UNLOCKED
 #define CONFIG_USB_PD_COMM_LOCKED
 
 /* EC */
@@ -21,18 +21,19 @@
 #define CONFIG_BOARD_HAS_RTC_RESET
 #define CONFIG_CRC8
 #define CONFIG_CEC
-#define CONFIG_CROS_BOARD_INFO
+#define CONFIG_CEC_BITBANG
+#define CONFIG_CBI_EEPROM
 #define CONFIG_DEDICATED_RECOVERY_BUTTON
 #define CONFIG_EMULATED_SYSRQ
 #define CONFIG_LED_COMMON
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
+#define CONFIG_MKBP_INPUT_DEVICES
 #define CONFIG_MKBP_USE_HOST_EVENT
 #define CONFIG_DPTF
-#define CONFIG_FLASH_SIZE 0x80000
+#define CONFIG_FLASH_SIZE_BYTES 0x80000
 #define CONFIG_FPU
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
-#undef  CONFIG_LID_SWITCH
+#define CONFIG_I2C_CONTROLLER
+#undef CONFIG_LID_SWITCH
 #define CONFIG_POWER_BUTTON_IGNORE_LID
 #define CONFIG_PWM
 #define CONFIG_LTO
@@ -47,15 +48,13 @@
 #define WIRELESS_GPIO_WLAN_POWER GPIO_PP3300_DX_WLAN
 #define WIRELESS_GPIO_WWAN GPIO_PP3300_DX_LTE
 #define CEC_GPIO_OUT GPIO_CEC_OUT
-#define CEC_GPIO_IN  GPIO_CEC_IN
+#define CEC_GPIO_IN GPIO_CEC_IN
 #define CEC_GPIO_PULL_UP GPIO_CEC_PULL_UP
 #define CONFIG_FANS 1
 #define CONFIG_FAN_RPM_CUSTOM
 #define CONFIG_THROTTLE_AP
 #define CONFIG_CHIPSET_CAN_THROTTLE
 #define CONFIG_PWM
-#define CONFIG_SUPPRESSED_HOST_COMMANDS \
-	EC_CMD_CONSOLE_SNAPSHOT, EC_CMD_CONSOLE_READ, EC_CMD_PD_GET_LOG_ENTRY
 
 /* EC console commands */
 #define CONFIG_CMD_BUTTON
@@ -65,13 +64,14 @@
 #define CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET
 #define CONFIG_CHIPSET_HAS_PRE_INIT_CALLBACK
 #define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#define CONFIG_HOST_INTERFACE_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
+#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD
 
 #define CONFIG_HOSTCMD_PD_CONTROL
 #define CONFIG_EXTPOWER_GPIO
-#undef  CONFIG_EXTPOWER_DEBOUNCE_MS
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
 #define CONFIG_EXTPOWER_DEBOUNCE_MS 1000
 #define CONFIG_POWER_BUTTON
 #define CONFIG_POWER_BUTTON_X86
@@ -106,20 +106,20 @@
 #define USB_PORT_COUNT 4
 
 /* Optional feature to configure npcx chip */
-#define NPCX_UART_MODULE2	1 /* 1:GPIO64/65 as UART */
-#define NPCX_JTAG_MODULE2	0 /* 0:GPIO21/17/16/20 as JTAG */
-#define NPCX_TACH_SEL2		1 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
+#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART */
+#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 as JTAG */
+#define NPCX_TACH_SEL2 1 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
 
 /* I2C ports */
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT0_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT0_1
-#define I2C_PORT_BACKLIGHT	NPCX_I2C_PORT1
-#define I2C_PORT_PMIC		NPCX_I2C_PORT2
-#define I2C_PORT_THERMAL	NPCX_I2C_PORT3
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT0_1
+#define I2C_PORT_BACKLIGHT NPCX_I2C_PORT1
+#define I2C_PORT_PMIC NPCX_I2C_PORT2
+#define I2C_PORT_THERMAL NPCX_I2C_PORT3
 
 /* I2C addresses */
-#define I2C_ADDR_TCPC0_FLAGS	0x0b
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_ADDR_TCPC0_FLAGS 0x0b
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 
 /* Verify and jump to RW image on boot */
 #define CONFIG_VBOOT_EFS
@@ -141,23 +141,22 @@
  * end of RW_A and RW_B, respectively.
  */
 #define CONFIG_RW_B
-#define CONFIG_RW_B_MEM_OFF		CONFIG_RO_MEM_OFF
-#undef  CONFIG_RO_SIZE
-#define CONFIG_RO_SIZE			(CONFIG_FLASH_SIZE / 4)
-#undef  CONFIG_RW_SIZE
-#define CONFIG_RW_SIZE			CONFIG_RO_SIZE
-#define CONFIG_RW_A_STORAGE_OFF		CONFIG_RW_STORAGE_OFF
-#define CONFIG_RW_B_STORAGE_OFF		(CONFIG_RW_A_STORAGE_OFF + \
-					 CONFIG_RW_SIZE)
-#define CONFIG_RW_A_SIGN_STORAGE_OFF	(CONFIG_RW_A_STORAGE_OFF + \
-					 CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE)
-#define CONFIG_RW_B_SIGN_STORAGE_OFF	(CONFIG_RW_B_STORAGE_OFF + \
-					 CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE)
+#define CONFIG_RW_B_MEM_OFF CONFIG_RO_MEM_OFF
+#undef CONFIG_RO_SIZE
+#define CONFIG_RO_SIZE (CONFIG_FLASH_SIZE_BYTES / 4)
+#undef CONFIG_RW_SIZE
+#define CONFIG_RW_SIZE CONFIG_RO_SIZE
+#define CONFIG_RW_A_STORAGE_OFF CONFIG_RW_STORAGE_OFF
+#define CONFIG_RW_B_STORAGE_OFF (CONFIG_RW_A_STORAGE_OFF + CONFIG_RW_SIZE)
+#define CONFIG_RW_A_SIGN_STORAGE_OFF \
+	(CONFIG_RW_A_STORAGE_OFF + CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE)
+#define CONFIG_RW_B_SIGN_STORAGE_OFF \
+	(CONFIG_RW_B_STORAGE_OFF + CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE)
 
 #undef CONFIG_EC_PROTECTED_STORAGE_SIZE
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE	CONFIG_RO_SIZE
+#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE
 #undef CONFIG_EC_WRITABLE_STORAGE_SIZE
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE		CONFIG_RW_SIZE
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE
 
 #define CONFIG_RWSIG
 #define CONFIG_RWSIG_TYPE_RWSIG
@@ -183,15 +182,12 @@ enum charge_port {
 };
 
 enum temp_sensor_id {
-	TEMP_SENSOR_CHARGER,	/* BD99992GW SYSTHERM1 */
-	TEMP_SENSOR_DRAM,	/* BD99992GW SYSTHERM2 */
+	TEMP_SENSOR_CHARGER, /* BD99992GW SYSTHERM1 */
+	TEMP_SENSOR_DRAM, /* BD99992GW SYSTHERM2 */
 	TEMP_SENSOR_COUNT
 };
 
-enum adc_channel {
-	ADC_VBUS,
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_VBUS, ADC_CH_COUNT };
 
 enum pwm_channel {
 	PWM_CH_LED_RED,
@@ -213,6 +209,8 @@ enum mft_channel {
 	MFT_CH_COUNT
 };
 
+enum cec_port { CEC_PORT_0, CEC_PORT_COUNT };
+
 enum OEM_ID {
 	OEM_KARMA = 7,
 	/* Number of OEM IDs */
@@ -224,11 +222,10 @@ enum OEM_ID {
  * delay to turn on the power supply max is ~16ms.
  * delay to turn off the power supply max is about ~180ms.
  */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	250000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* delay to turn on/off vconn */
-#define PD_VCONN_SWAP_DELAY		5000   /* us */
 
 /* Board specific handlers */
 void board_reset_pd_mcu(void);
diff --git a/baseboard/kalista/build.mk b/baseboard/kalista/build.mk
index e64b6a2d71..6bb55b2023 100644
--- a/baseboard/kalista/build.mk
+++ b/baseboard/kalista/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -8,4 +8,4 @@
 
 baseboard-y=baseboard.o
 baseboard-y+=led.o
-baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
\ No newline at end of file
+baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o usb_pd_pdo.o
diff --git a/baseboard/kalista/led.c b/baseboard/kalista/led.c
index e04eecf5e3..c72ce84bb0 100644
--- a/baseboard/kalista/led.c
+++ b/baseboard/kalista/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -15,7 +15,7 @@
 #include "timer.h"
 #include "util.h"
 
-const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 enum led_color {
@@ -76,9 +76,9 @@ static int set_color(enum ec_led_id id, enum led_color color, int duty)
 	}
 }
 
-#define LED_PULSE_US		(2 * SECOND)
+#define LED_PULSE_US (2 * SECOND)
 /* 40 msec for nice and smooth transition. */
-#define LED_PULSE_TICK_US	(40 * MSEC)
+#define LED_PULSE_TICK_US (40 * MSEC)
 
 /* When pulsing is enabled, brightness is incremented by <duty_inc> every
  * <interval> usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented
@@ -181,7 +181,7 @@ void led_critical(void)
 		set_color(EC_LED_ID_POWER_LED, LED_RED, 100);
 }
 
-static int command_led(int argc, char **argv)
+static int command_led(int argc, const char **argv)
 {
 	enum ec_led_id id = EC_LED_ID_POWER_LED;
 
diff --git a/baseboard/kalista/usb_pd_pdo.c b/baseboard/kalista/usb_pd_pdo.c
new file mode 100644
index 0000000000..067b8eb9e7
--- /dev/null
+++ b/baseboard/kalista/usb_pd_pdo.c
@@ -0,0 +1,16 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "compile_time_macros.h"
+#include "usb_pd.h"
+#include "usb_pd_pdo.h"
+
+#define PDO_FIXED_FLAGS \
+	(PDO_FIXED_UNCONSTRAINED | PDO_FIXED_DATA_SWAP | PDO_FIXED_COMM_CAP)
+
+const uint32_t pd_src_pdo[] = {
+	PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS),
+};
+const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
diff --git a/baseboard/kalista/usb_pd_pdo.h b/baseboard/kalista/usb_pd_pdo.h
new file mode 100644
index 0000000000..119658b8a5
--- /dev/null
+++ b/baseboard/kalista/usb_pd_pdo.h
@@ -0,0 +1,15 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_BASEBOARD_KALISTA_USB_PD_PDO_H
+#define __CROS_EC_BASEBOARD_KALISTA_USB_PD_PDO_H
+
+#include "config.h"
+#include "stdint.h"
+
+extern const uint32_t pd_src_pdo[1];
+extern const int pd_src_pdo_cnt;
+
+#endif /* __CROS_EC_BASEBOARD_KALISTA_USB_PD_PDO_H */
diff --git a/baseboard/kalista/usb_pd_policy.c b/baseboard/kalista/usb_pd_policy.c
index 89af4b50fb..b2f4656519 100644
--- a/baseboard/kalista/usb_pd_policy.c
+++ b/baseboard/kalista/usb_pd_policy.c
@@ -1,15 +1,15 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "atomic.h"
-#include "extpower.h"
 #include "charge_manager.h"
 #include "common.h"
 #include "console.h"
 #include "driver/tcpm/anx74xx.h"
 #include "driver/tcpm/ps8xxx.h"
+#include "extpower.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "host_command.h"
@@ -17,22 +17,14 @@
 #include "system.h"
 #include "task.h"
 #include "timer.h"
-#include "util.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
+#include "usb_pd_pdo.h"
 #include "usb_pd_tcpm.h"
+#include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-#define PDO_FIXED_FLAGS (PDO_FIXED_UNCONSTRAINED | \
-			 PDO_FIXED_DATA_SWAP | \
-			 PDO_FIXED_COMM_CAP)
-
-const uint32_t pd_src_pdo[] = {
-	PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS),
-};
-const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int board_vbus_source_enabled(int port)
 {
@@ -66,8 +58,7 @@ int pd_snk_is_vbus_provided(int port)
 	return !gpio_get_level(GPIO_USB_C0_VBUS_WAKE_L);
 }
 
-__override void pd_check_pr_role(int port,
-				 enum pd_power_role pr_role,
+__override void pd_check_pr_role(int port, enum pd_power_role pr_role,
 				 int flags)
 {
 }
diff --git a/baseboard/keeby b/baseboard/keeby
new file mode 120000
index 0000000000..14558486f6
--- /dev/null
+++ b/baseboard/keeby
@@ -0,0 +1 @@
+dedede
\ No newline at end of file
diff --git a/baseboard/kukui/base_detect_kukui.c b/baseboard/kukui/base_detect_kukui.c
index ac7d9f7616..a3ccf4d507 100644
--- a/baseboard/kukui/base_detect_kukui.c
+++ b/baseboard/kukui/base_detect_kukui.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,7 +14,7 @@
 #include "usb_pd.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USB, format, ##args)
 
 /* Krane base detection code */
 
@@ -41,11 +41,11 @@ enum kukui_pogo_device_type {
 struct {
 	int mv_low, mv_high;
 } static const pogo_detect_table[] = {
-	[DEVICE_TYPE_DETACHED] = {2700, 3500}, /* 10K, NC, around 3.3V */
+	[DEVICE_TYPE_DETACHED] = { 2700, 3500 }, /* 10K, NC, around 3.3V */
 #ifdef VARIANT_KUKUI_POGO_DOCK
-	[DEVICE_TYPE_DOCK] = {141, 173},       /* 10K, 0.5K ohm */
+	[DEVICE_TYPE_DOCK] = { 141, 173 }, /* 10K, 0.5K ohm */
 #endif
-	[DEVICE_TYPE_KEYBOARD] = {270, 400},   /* 10K, 1K ohm */
+	[DEVICE_TYPE_KEYBOARD] = { 270, 400 }, /* 10K, 1K ohm */
 };
 BUILD_ASSERT(ARRAY_SIZE(pogo_detect_table) == DEVICE_TYPE_COUNT);
 
@@ -71,7 +71,7 @@ static enum kukui_pogo_device_type get_device_type(int mv)
 
 	for (i = 0; i < DEVICE_TYPE_COUNT; i++) {
 		if (pogo_detect_table[i].mv_low <= mv &&
-				mv <= pogo_detect_table[i].mv_high)
+		    mv <= pogo_detect_table[i].mv_high)
 			return i;
 	}
 
@@ -82,17 +82,17 @@ static void enable_charge(int enable)
 {
 #ifdef VARIANT_KUKUI_POGO_DOCK
 	if (enable) {
-		struct charge_port_info info = {
-			.voltage = 5000, .current = 1500};
+		struct charge_port_info info = { .voltage = 5000,
+						 .current = 1500 };
 		/*
 		 * Set supplier type to PD to have same priority as type c
 		 * port.
 		 */
-		charge_manager_update_charge(
-			CHARGE_SUPPLIER_DEDICATED, CHARGE_PORT_POGO, &info);
+		charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED,
+					     CHARGE_PORT_POGO, &info);
 	} else {
-		charge_manager_update_charge(
-			CHARGE_SUPPLIER_DEDICATED, CHARGE_PORT_POGO, NULL);
+		charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED,
+					     CHARGE_PORT_POGO, NULL);
 	}
 	pd_send_host_event(PD_EVENT_POWER_CHANGE);
 #endif
@@ -112,7 +112,7 @@ static void base_set_device_type(enum kukui_pogo_device_type device_type)
 	case DEVICE_TYPE_ERROR:
 	case DEVICE_TYPE_UNKNOWN:
 		hook_call_deferred(&base_detect_deferred_data,
-				BASE_DETECT_RETRY_US);
+				   BASE_DETECT_RETRY_US);
 		break;
 
 	case DEVICE_TYPE_DETACHED:
@@ -200,9 +200,9 @@ static void pogo_chipset_shutdown(void)
 }
 DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, pogo_chipset_shutdown, HOOK_PRIO_DEFAULT);
 
-void base_force_state(int state)
+void base_force_state(enum ec_set_base_state_cmd state)
 {
-	if (state != 1 && state != 0) {
+	if (state >= EC_SET_BASE_STATE_RESET) {
 		CPRINTS("BD forced reset");
 		pogo_chipset_init();
 		return;
@@ -210,9 +210,11 @@ void base_force_state(int state)
 
 	gpio_disable_interrupt(GPIO_POGO_ADC_INT_L);
 	pogo_type = (state == 1 ? DEVICE_TYPE_KEYBOARD : DEVICE_TYPE_DETACHED);
-	base_set_device_type(state == 1 ? DEVICE_TYPE_KEYBOARD :
-					  DEVICE_TYPE_DETACHED);
-	CPRINTS("BD forced %sconnected", state == 1 ? "" : "dis");
+	base_set_device_type(state == EC_SET_BASE_STATE_ATTACH ?
+				     DEVICE_TYPE_KEYBOARD :
+				     DEVICE_TYPE_DETACHED);
+	CPRINTS("BD forced %sconnected",
+		state == EC_SET_BASE_STATE_ATTACH ? "" : "dis");
 }
 
 #ifdef VARIANT_KUKUI_POGO_DOCK
@@ -225,5 +227,5 @@ static void board_pogo_charge_init(void)
 		charge_manager_update_charge(i, CHARGE_PORT_POGO, NULL);
 }
 DECLARE_HOOK(HOOK_INIT, board_pogo_charge_init,
-	     HOOK_PRIO_CHARGE_MANAGER_INIT + 1);
+	     HOOK_PRIO_INIT_CHARGE_MANAGER + 1);
 #endif
diff --git a/baseboard/kukui/baseboard.c b/baseboard/kukui/baseboard.c
index baf915407a..372e60c1e8 100644
--- a/baseboard/kukui/baseboard.c
+++ b/baseboard/kukui/baseboard.c
@@ -1,18 +1,21 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "charger.h"
+#include "chipset.h"
+#include "dma.h"
 #include "gpio.h"
 #include "hooks.h"
+#include "i2c.h"
+#include "keyboard_scan.h"
 #include "registers.h"
 #include "timer.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 #ifndef CONFIG_CHARGER_RUNTIME_CONFIG
 #if defined(VARIANT_KUKUI_CHARGER_MT6370)
@@ -43,6 +46,7 @@ void board_reset_pd_mcu(void)
 
 void board_config_pre_init(void)
 {
+#ifdef VARIANT_KUKUI_EC_STM32F098
 	STM32_RCC_AHBENR |= STM32_RCC_HB_DMA1;
 	/*
 	 * Remap USART1 and SPI2 DMA:
@@ -50,8 +54,28 @@ void board_config_pre_init(void)
 	 * Ch4: USART1_TX / Ch5: USART1_RX (1000)
 	 * Ch6: SPI2_RX / Ch7: SPI2_TX (0011)
 	 */
-	STM32_DMA_CSELR(STM32_DMAC_CH4) = (8 << 12) | (8 << 16) |
-					  (3 << 20) | (3 << 24);
+	STM32_DMA_CSELR(STM32_DMAC_CH4) = (8 << 12) | (8 << 16) | (3 << 20) |
+					  (3 << 24);
+
+#elif defined(VARIANT_KUKUI_EC_STM32L431)
+#ifdef CONFIG_DMA_CROS
+	dma_init();
+#endif
+	/*
+	 * Remap USART1 and SPI2 DMA:
+	 *
+	 * DMA2_CH=DMA1_CH+8
+	 *
+	 * Ch6 (DMA2): USART1_TX / Ch7: USART1_RX (0010)
+	 * Ch4 (DMA1): SPI2_RX   / Ch5: SPI2_TX (0010)
+	 *
+	 *    (*((volatile unsigned long *)(0x400200A8UL))) = 0x00011000;
+	 *    (*((volatile unsigned long *)(0x400204A8UL))) = 0x00200000;
+	 */
+
+	STM32_DMA_CSELR(STM32_DMAC_CH4) = (1 << 12) | (1 << 16);
+	STM32_DMA_CSELR(STM32_DMAC_CH14) = (2 << 20) | (2 << 24);
+#endif
 }
 
 enum kukui_board_version {
@@ -76,27 +100,50 @@ enum kukui_board_version {
 };
 
 /* map from kukui_board_version to board id voltage in mv */
+#ifdef VARIANT_KUKUI_EC_IT81202
 const int16_t kukui_board_id_map[] = {
-	109,   /* 51.1K , 2.2K(gru 3.3K) ohm */
-	211,   /* 51.1k , 6.8K ohm */
-	319,   /* 51.1K , 11K ohm */
-	427,   /* 56K   , 17.4K ohm */
-	542,   /* 51.1K , 22K ohm */
-	666,   /* 51.1K , 30K ohm */
-	781,   /* 51.1K , 39.2K ohm */
-	900,   /* 56K   , 56K ohm */
-	1023,  /* 47K   , 61.9K ohm */
-	1137,  /* 47K   , 80.6K ohm */
-	1240,  /* 56K   , 124K ohm */
-	1343,  /* 51.1K , 150K ohm */
-	1457,  /* 47K   , 200K ohm */
-	1576,  /* 47K   , 330K ohm */
-	1684,  /* 47K   , 680K ohm */
-	1800,  /* 56K   , NC */
+	136, /* 51.1K , 2.2K(gru 3.3K) ohm */
+	388, /* 51.1k , 6.8K ohm */
+	584, /* 51.1K , 11K ohm */
+	785, /* 56K   , 17.4K ohm */
+	993, /* 51.1K , 22K ohm */
+	1221, /* 51.1K , 30K ohm */
+	1433, /* 51.1K , 39.2K ohm */
+	1650, /* 56K   , 56K ohm */
+	1876, /* 47K   , 61.9K ohm */
+	2084, /* 47K   , 80.6K ohm */
+	2273, /* 56K   , 124K ohm */
+	2461, /* 51.1K , 150K ohm */
+	2672, /* 47K   , 200K ohm */
+	2889, /* 47K   , 330K ohm */
+	3086, /* 47K   , 680K ohm */
+	3300, /* 56K   , NC */
+};
+
+#define THRESHOLD_MV 103 /* Simply assume 3300/16/2 */
+#else
+const int16_t kukui_board_id_map[] = {
+	109, /* 51.1K , 2.2K(gru 3.3K) ohm */
+	211, /* 51.1k , 6.8K ohm */
+	319, /* 51.1K , 11K ohm */
+	427, /* 56K   , 17.4K ohm */
+	542, /* 51.1K , 22K ohm */
+	666, /* 51.1K , 30K ohm */
+	781, /* 51.1K , 39.2K ohm */
+	900, /* 56K   , 56K ohm */
+	1023, /* 47K   , 61.9K ohm */
+	1137, /* 47K   , 80.6K ohm */
+	1240, /* 56K   , 124K ohm */
+	1343, /* 51.1K , 150K ohm */
+	1457, /* 47K   , 200K ohm */
+	1576, /* 47K   , 330K ohm */
+	1684, /* 47K   , 680K ohm */
+	1800, /* 56K   , NC */
 };
-BUILD_ASSERT(ARRAY_SIZE(kukui_board_id_map) == BOARD_VERSION_COUNT);
 
 #define THRESHOLD_MV 56 /* Simply assume 1800/16/2 */
+#endif /* VARIANT_KUKUI_EC_IT81202 */
+BUILD_ASSERT(ARRAY_SIZE(kukui_board_id_map) == BOARD_VERSION_COUNT);
 
 int board_get_version(void)
 {
@@ -109,7 +156,7 @@ int board_get_version(void)
 
 	gpio_set_level(GPIO_EC_BOARD_ID_EN_L, 0);
 	/* Wait to allow cap charge */
-	msleep(10);
+	msleep(20);
 	mv = adc_read_channel(ADC_BOARD_ID);
 
 	if (mv == ADC_READ_ERROR)
@@ -124,27 +171,52 @@ int board_get_version(void)
 		}
 	}
 
+#ifdef VARIANT_KUKUI_EC_STM32F098
 	/*
 	 * For devices without pogo, Disable ADC module after we detect the
 	 * board version, since this is the only thing ADC module needs to do
 	 * for this board.
 	 */
 	if (CONFIG_DEDICATED_CHARGE_PORT_COUNT == 0 &&
-			version != BOARD_VERSION_UNKNOWN)
+	    version != BOARD_VERSION_UNKNOWN)
 		adc_disable();
+#endif
 
 	return version;
 }
 
 static void baseboard_spi_init(void)
 {
+#if defined(VARIANT_KUKUI_EC_STM32F098) || defined(VARIANT_KUKUI_EC_STM32L431)
 	/* Set SPI PA15,PB3/4/5/13/14/15 pins to high speed */
 	STM32_GPIO_OSPEEDR(GPIO_A) |= 0xc0000000;
 	STM32_GPIO_OSPEEDR(GPIO_B) |= 0xfc000fc0;
+#endif
 }
 DECLARE_HOOK(HOOK_INIT, baseboard_spi_init, HOOK_PRIO_INIT_SPI + 1);
 
-int board_allow_i2c_passthru(int port)
+int board_allow_i2c_passthru(const struct i2c_cmd_desc_t *cmd_desc)
 {
-	return (port == I2C_PORT_VIRTUAL_BATTERY);
+	return (cmd_desc->port == I2C_PORT_VIRTUAL_BATTERY);
+}
+
+/* Enable or disable input devices, based on chipset state and tablet mode */
+#ifdef VARIANT_KUKUI_JACUZZI
+__override void lid_angle_peripheral_enable(int enable)
+{
+	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
+
+	if (enable) {
+		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
+	} else {
+		/*
+		 * Ensure that the chipset is off before disabling the
+		 * keyboard. When the chipset is on, the EC keeps the
+		 * keyboard enabled and the AP decides whether to
+		 * ignore input devices or not.
+		 */
+		if (!chipset_in_s0)
+			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
+	}
 }
+#endif
diff --git a/baseboard/kukui/baseboard.h b/baseboard/kukui/baseboard.h
index d4019f1fb1..6cb18b0d4e 100644
--- a/baseboard/kukui/baseboard.h
+++ b/baseboard/kukui/baseboard.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,14 +12,17 @@
  * Variant battery defines, pick one:
  * VARIANT_KUKUI_BATTERY_MAX17055
  * VARIANT_KUKUI_BATTERY_MM8013
+ * VARIANT_KUKUI_BATTERY_BQ27541
  * VARIANT_KUKUI_BATTERY_SMART
  */
 #if defined(VARIANT_KUKUI_BATTERY_MAX17055)
 #define CONFIG_BATTERY_MAX17055
 #define CONFIG_BATTERY_MAX17055_ALERT
-#define BATTERY_MAX17055_RSENSE             5     /* m-ohm */
+#define BATTERY_MAX17055_RSENSE 5 /* m-ohm */
 #elif defined(VARIANT_KUKUI_BATTERY_MM8013)
 #define CONFIG_BATTERY_MM8013
+#elif defined(VARIANT_KUKUI_BATTERY_BQ27541)
+#define CONFIG_BATTERY_BQ27541
 #elif defined(VARIANT_KUKUI_BATTERY_SMART)
 #define CONFIG_BATTERY_SMART
 #define CONFIG_BATTERY_FUEL_GAUGE
@@ -44,9 +47,8 @@
 #define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
 
 /* TCPC MT6370 */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
-#define PD_VCONN_SWAP_DELAY 5000 /* us */
 
 /*
  * The Maximum input voltage is 13.5V, need another 5% tolerance.
@@ -60,11 +62,11 @@
 #define CONFIG_CHARGER_SENSE_RESISTOR 10 /* BOARD_RS2 */
 #define CONFIG_CHARGER_OTG
 #define CONFIG_CHARGE_RAMP_HW
+#define CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT 512
 
 /* TCPC FUSB302 */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  160000  /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 160000 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
-#define PD_VCONN_SWAP_DELAY 5000 /* us */
 
 /* b/2230219: 15V has better charging performance than 20V */
 #define PD_MAX_VOLTAGE_MV 15000
@@ -94,22 +96,44 @@
 /* define this if the board is jacuzzi family */
 #ifdef VARIANT_KUKUI_JACUZZI
 #define CONFIG_HOSTCMD_AP_SET_SKUID
+/*
+ * IT81202 based boards are variant of jacuzzi and I/O expander isn't required
+ * on them.
+ */
+#if defined(VARIANT_KUKUI_EC_STM32F098) || defined(VARIANT_KUKUI_EC_STM32L431)
 #define CONFIG_IO_EXPANDER
 #define CONFIG_IO_EXPANDER_IT8801
 #define CONFIG_IO_EXPANDER_PORT_COUNT 1
-#define CONFIG_KEYBOARD_NOT_RAW
-#define CONFIG_KEYBOARD_BOARD_CONFIG
+#define CONFIG_KEYBOARD_DISCRETE
+
+#endif
+
 #define CONFIG_KEYBOARD_COL2_INVERTED
 
 #define CONFIG_GMR_TABLET_MODE
-#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L
 #define CONFIG_TABLET_MODE
 #define CONFIG_TABLET_MODE_SWITCH
 
 #define PD_OPERATING_POWER_MW 30000
-#define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT TYPEC_RP_3A0
+
+#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK            \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+#else /* !VARIANT_KUKUI_JACUZZI */
+
+#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK                \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |     \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
+
 #endif /* VARIANT_KUKUI_JACUZZI */
 
+#if defined(SECTION_IS_RW) || defined(VARIANT_KUKUI_EC_IT81202)
+#define CONFIG_POWER_SLEEP_FAILURE_DETECTION
+#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
+#endif
+
 /*
  * Define this flag if board controls dp mux via gpio pins USB_C0_DP_OE_L and
  * USB_C0_DP_POLARITY.
@@ -121,23 +145,19 @@
 
 /* Optional modules */
 #define CONFIG_ADC
-#undef  CONFIG_ADC_WATCHDOG
+#undef CONFIG_ADC_WATCHDOG
 #define CONFIG_CHIPSET_MT8183
-#define CONFIG_CMD_ACCELS
+#undef CONFIG_CMD_ACCELS
 #define CONFIG_EMULATED_SYSRQ
-#undef  CONFIG_HIBERNATE
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_CONTROLLER
 #define CONFIG_I2C_VIRTUAL_BATTERY
 #define CONFIG_I2C_PASSTHRU_RESTRICTED
 #define CONFIG_LED_COMMON
 #define CONFIG_LOW_POWER_IDLE
 #define CONFIG_POWER_COMMON
 #define CONFIG_SPI
-#define CONFIG_SPI_MASTER
-#define CONFIG_STM_HWTIMER32
 #define CONFIG_SWITCH
-#define CONFIG_WATCHDOG_HELP
 
 #ifdef SECTION_IS_RO
 #undef CONFIG_SYSTEM_UNLOCKED /* Disabled in RO to save space */
@@ -145,17 +165,6 @@
 #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands for testing */
 #endif
 
-/* free flash space */
-#ifdef SECTION_IS_RO
-#undef CONFIG_USB_PD_DEBUG_LEVEL
-#define CONFIG_USB_PD_DEBUG_LEVEL 0
-#define CONFIG_COMMON_GPIO_SHORTNAMES
-#endif
-
-#undef  CONFIG_UART_CONSOLE
-#define CONFIG_UART_CONSOLE 1
-#define CONFIG_UART_RX_DMA
-
 /* Bootblock */
 #ifdef SECTION_IS_RO
 #define CONFIG_BOOTBLOCK
@@ -165,7 +174,6 @@
 
 /* Optional features */
 #define CONFIG_BOARD_PRE_INIT
-#define CONFIG_BOARD_VERSION_CUSTOM
 #define CONFIG_BUTTON_TRIGGERED_RECOVERY
 #define CONFIG_CHARGER_ILIM_PIN_DISABLED
 #define CONFIG_FORCE_CONSOLE_RESUME
@@ -180,19 +188,15 @@
 /* By default, set hcdebug to off */
 #undef CONFIG_HOSTCMD_DEBUG_MODE
 #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
-#define CONFIG_SUPPRESSED_HOST_COMMANDS \
-	EC_CMD_CONSOLE_SNAPSHOT, EC_CMD_CONSOLE_READ, EC_CMD_MOTION_SENSE_CMD
 
 #define CONFIG_LTO
 #define CONFIG_POWER_BUTTON
 #define CONFIG_POWER_BUTTON_IGNORE_LID
 #define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-#define CONFIG_SOFTWARE_PANIC
 #define CONFIG_VBOOT_HASH
 
 #define CONFIG_CHARGER
-#define CONFIG_CHARGER_INPUT_CURRENT 512
-#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 2
+#define CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT 512
 #define CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT 2
 #define CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW 15000
 #define CONFIG_CHARGER_DISCHARGE_ON_AC
@@ -204,6 +208,7 @@
 #define CONFIG_UART_TX_BUF_SIZE 4096
 
 #define GPIO_LID_OPEN GPIO_HALL_INT_L
+#define GPIO_KB_DISCRETE_INT GPIO_IT8801_SMB_INT
 
 #ifndef VARIANT_KUKUI_NO_SENSORS
 #define CONFIG_ACCEL_FIFO
@@ -219,18 +224,12 @@
 /* USB PD config */
 #define CONFIG_CHARGE_MANAGER
 #define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV1
-/* Exclude PD state names from RO image to save space */
-#ifdef SECTION_IS_RO
-#undef CONFIG_USB_PD_TCPMV1_DEBUG
-#endif
 #define CONFIG_USB_PD_ALT_MODE
 #define CONFIG_USB_PD_ALT_MODE_DFP
 #define CONFIG_USB_PD_DUAL_ROLE
 #define CONFIG_USB_PD_LOGGING
 #define CONFIG_USB_PD_PORT_MAX_COUNT 1
 #define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
 #define CONFIG_USB_PD_5V_EN_CUSTOM
 #define CONFIG_USBC_SS_MUX
 #define CONFIG_USBC_VCONN
@@ -242,55 +241,121 @@
 #define CONFIG_BATTERY_PRESENT_CUSTOM
 #define CONFIG_BATTERY_REVIVE_DISCONNECT
 
-#define PD_MAX_POWER_MW       ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
+#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
 #ifdef BOARD_KODAMA
-#define PD_MAX_CURRENT_MA     2000
+#define PD_MAX_CURRENT_MA 2000
 #else
-#define PD_MAX_CURRENT_MA     3000
+#define PD_MAX_CURRENT_MA 3000
 #endif
 
+/* Optional for testing */
+#undef CONFIG_PECI
+#undef CONFIG_PSTORE
+
+#define CONFIG_TASK_PROFILING
+#define CONFIG_MKBP_USE_GPIO
+
+/*
+ * Variant EC defines. Pick one:
+ * VARIANT_KUKUI_EC_STM32F098
+ * VARIANT_KUKUI_EC_IT81202
+ * VARIANT_KUKUI_EC_STM32L431
+ */
+#if defined(VARIANT_KUKUI_EC_STM32F098) || defined(VARIANT_KUKUI_EC_STM32L431)
 /* Timer selection */
-#define TIM_CLOCK32  2
+#define TIM_CLOCK32 2
 #define TIM_WATCHDOG 7
 
 /* 48 MHz SYSCLK clock frequency */
+#ifdef VARIANT_KUKUI_EC_STM32L431
+#define CPU_CLOCK 80000000
+#else
 #define CPU_CLOCK 48000000
+#endif
 
-/* Optional for testing */
-#undef CONFIG_PECI
-#undef CONFIG_PSTORE
+#undef CONFIG_HIBERNATE
+#define CONFIG_SPI_CONTROLLER
+#define CONFIG_WATCHDOG_HELP
+#undef CONFIG_UART_CONSOLE
+#define CONFIG_UART_CONSOLE 1
+#define CONFIG_UART_RX_DMA
+
+/* This option is limited to TCPMv1 */
+#define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT TYPEC_RP_3A0
+/* STM32F098 based boards use TCPMv1 */
+#define CONFIG_USB_PD_TCPMV1
+#define CONFIG_USB_PD_VBUS_DETECT_TCPC
 
 /* Modules we want to exclude */
+#undef CONFIG_ACCEL_SPOOF_MODE
+#undef CONFIG_CMD_ACCELSPOOF
 #undef CONFIG_CMD_BATTFAKE
 #undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_FLASH_WP
+#undef CONFIG_CMD_FLASHINFO
+#undef CONFIG_CMD_GETTIME
 #undef CONFIG_CMD_HASH
 #undef CONFIG_CMD_MD
+#undef CONFIG_CMD_MEM
 #undef CONFIG_CMD_POWERINDEBUG
+#undef CONFIG_CMD_SHMEM
+#undef CONFIG_CMD_SYSLOCK
 #undef CONFIG_CMD_TIMERINFO
+#undef CONFIG_CONSOLE_CMDHELP
+#undef CONFIG_CONSOLE_HISTORY
 
+/* save space at RO image */
 #ifdef SECTION_IS_RO
+#undef CONFIG_CMD_ADC
 #undef CONFIG_CMD_APTHROTTLE
+#undef CONFIG_CMD_CHARGE_SUPPLIER_INFO
 #undef CONFIG_CMD_CRASH
 #undef CONFIG_CMD_HCDEBUG
 #undef CONFIG_CMD_IDLE_STATS
+#undef CONFIG_CMD_KEYBOARD
+#undef CONFIG_CMD_MFALLOW
 #undef CONFIG_CMD_MMAPINFO
+#undef CONFIG_CMD_PD
+#undef CONFIG_CMD_POWER_AP
 #undef CONFIG_CMD_PWR_AVG
 #undef CONFIG_CMD_REGULATOR
 #undef CONFIG_CMD_RW
-#undef CONFIG_CMD_SHMEM
 #undef CONFIG_CMD_SLEEPMASK
 #undef CONFIG_CMD_SLEEPMASK_SET
-#undef CONFIG_CMD_SYSLOCK
+#undef CONFIG_CMD_SYSINFO
+#undef CONFIG_CMD_TYPEC
+#undef CONFIG_CMD_WAITMS
 #undef CONFIG_HOSTCMD_FLASHPD
 #undef CONFIG_HOSTCMD_RWHASHPD
-#undef CONFIG_CONSOLE_CMDHELP
-#endif
 
-#define CONFIG_TASK_PROFILING
+#undef CONFIG_HOSTCMD_GET_UPTIME_INFO
+#undef CONFIG_CMD_AP_RESET_LOG
+#undef CONFIG_CMD_I2C_SCAN
+#undef CONFIG_CMD_I2C_XFER
 
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_GPIO
+/* free flash space */
+#undef CONFIG_USB_PD_DEBUG_LEVEL
+#define CONFIG_USB_PD_DEBUG_LEVEL 0
+#undef CONFIG_USB_PD_LOGGING
+#define CONFIG_COMMON_GPIO_SHORTNAMES
+#define CONFIG_DEBUG_ASSERT_BRIEF
+/* Exclude PD state names from RO image to save space */
+#undef CONFIG_USB_PD_TCPMV1_DEBUG
+#undef CONFIG_TASK_PROFILING
+#endif /* SECTION_IS_RO */
+
+#elif defined(VARIANT_KUKUI_EC_IT81202)
+#define CONFIG_IT83XX_HARD_RESET_BY_GPG1
+#define CONFIG_IT83XX_VCC_1P8V
+
+/* IT81202 based boards use TCPMv2 */
+#define CONFIG_USB_DRP_ACC_TRYSRC
+#define CONFIG_USB_PD_DECODE_SOP
+#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1
+#define CONFIG_USB_PD_TCPMV2
+#else
+#error "Must define a VARIANT_KUKUI_EC_XXX!"
+#endif
 
 #ifndef __ASSEMBLER__
 #ifdef VARIANT_KUKUI_DP_MUX_GPIO
diff --git a/baseboard/kukui/battery_bq27541.c b/baseboard/kukui/battery_bq27541.c
new file mode 100644
index 0000000000..453d5e984f
--- /dev/null
+++ b/baseboard/kukui/battery_bq27541.c
@@ -0,0 +1,220 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery.h"
+#include "builtin/assert.h"
+#include "charge_state.h"
+#include "charger_mt6370.h"
+#include "console.h"
+#include "driver/tcpm/mt6370.h"
+#include "ec_commands.h"
+#include "util.h"
+
+#define TEMP_OUT_OF_RANGE TEMP_ZONE_COUNT
+
+#define BATT_ID 0
+
+#define BATTERY_CPT_CHARGE_MIN_TEMP 0
+#define BATTERY_CPT_CHARGE_MAX_TEMP 50
+
+#define CHARGER_LIMIT_TIMEOUT_HOURS 48
+#define CHARGER_LIMIT_TIMEOUT_HOURS_TEMP 2
+
+#define BAT_LEVEL_PD_LIMIT 85
+
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+
+enum battery_type { BATTERY_CPT = 0, BATTERY_COUNT };
+
+static const struct battery_info info[] = {
+	[BATTERY_CPT] = {
+		.voltage_max		= 4400,
+		.voltage_normal		= 3850,
+		.voltage_min		= 3000,
+		.precharge_voltage	= 3400,
+		.precharge_current	= 256,
+		.start_charging_min_c	= 0,
+		.start_charging_max_c	= 45,
+		.charging_min_c		= 0,
+		.charging_max_c		= 50,
+		.discharging_min_c	= -20,
+		.discharging_max_c	= 60,
+	},
+};
+
+const struct battery_info *battery_get_info(void)
+{
+	return &info[BATT_ID];
+}
+
+int charger_profile_override(struct charge_state_data *curr)
+{
+	static timestamp_t deadline_48;
+	static timestamp_t deadline_2;
+	int cycle_count = 0, rv, val;
+	unsigned char rcv = 0, rcv_cycle = 0, rcv_soh = 0;
+	/* (FullCharge Capacity / Design Capacity) * 100 = SOH */
+	int full_cap = 0, design_cap = 0, soh = 0;
+	/* battery temp in 0.1 deg C */
+	int bat_temp_c = curr->batt.temperature - 2731;
+	/*
+	 * Keep track of battery temperature range:
+	 *
+	 *        ZONE_0   ZONE_1     ZONE_2
+	 * -----+--------+--------+------------+----- Temperature (C)
+	 *      t0       t1       t2           t3
+	 */
+	enum {
+		TEMP_ZONE_0, /* t0 < bat_temp_c <= t1 */
+		TEMP_ZONE_1, /* t1 < bat_temp_c <= t2 */
+		TEMP_ZONE_2, /* t2 < bat_temp_c <= t3 */
+		TEMP_ZONE_3, /* t3 < bat_temp_c <= t4 */
+		TEMP_ZONE_COUNT
+	} temp_zone;
+
+	static struct {
+		int temp_min; /* 0.1 deg C */
+		int temp_max; /* 0.1 deg C */
+		int desired_current; /* mA */
+		int desired_voltage; /* mV */
+	} temp_zones[BATTERY_COUNT][TEMP_ZONE_COUNT] = {
+		[BATTERY_CPT] = {
+			/* TEMP_ZONE_0 */
+			{BATTERY_CPT_CHARGE_MIN_TEMP * 10, 150, 1408, 4370},
+			/* TEMP_ZONE_1 */
+			{150, 430, 3520, 4370},
+			/* TEMP_ZONE_2 */
+			{430, 450, 2112, 4320},
+			/* TEMP_ZONE_3 */
+			{450, BATTERY_CPT_CHARGE_MAX_TEMP * 10, 1760, 4170},
+		},
+	};
+	BUILD_ASSERT(ARRAY_SIZE(temp_zones[0]) == TEMP_ZONE_COUNT);
+	BUILD_ASSERT(ARRAY_SIZE(temp_zones) == BATTERY_COUNT);
+
+	if ((curr->batt.flags & BATT_FLAG_BAD_TEMPERATURE) ||
+	    (bat_temp_c < temp_zones[BATT_ID][0].temp_min) ||
+	    (bat_temp_c >= temp_zones[BATT_ID][TEMP_ZONE_COUNT - 1].temp_max))
+		temp_zone = TEMP_OUT_OF_RANGE;
+	else {
+		for (temp_zone = 0; temp_zone < TEMP_ZONE_COUNT; temp_zone++) {
+			if (bat_temp_c <
+			    temp_zones[BATT_ID][temp_zone].temp_max)
+				break;
+		}
+	}
+
+	switch (temp_zone) {
+	case TEMP_ZONE_0:
+	case TEMP_ZONE_1:
+	case TEMP_ZONE_2:
+	case TEMP_ZONE_3:
+		curr->requested_current =
+			temp_zones[BATT_ID][temp_zone].desired_current;
+		curr->requested_voltage =
+			temp_zones[BATT_ID][temp_zone].desired_voltage;
+		break;
+	case TEMP_OUT_OF_RANGE:
+		curr->requested_current = curr->requested_voltage = 0;
+		curr->batt.flags &= ~BATT_FLAG_WANT_CHARGE;
+		curr->state = ST_IDLE;
+		break;
+	}
+
+	/* Check cycle count to decrease charging voltage. */
+	rv = battery_cycle_count(&val);
+	if (!rv)
+		cycle_count = val;
+	if (cycle_count > 20 && cycle_count <= 50)
+		rcv_cycle = 50;
+	else if (cycle_count > 50 && cycle_count <= 300)
+		rcv_cycle = 65;
+	else if (cycle_count > 300 && cycle_count <= 600)
+		rcv_cycle = 80;
+	else if (cycle_count > 600 && cycle_count <= 1000)
+		rcv_cycle = 100;
+	else if (cycle_count > 1000)
+		rcv_cycle = 150;
+	/* Check SOH to decrease charging voltage. */
+	if (!battery_full_charge_capacity(&full_cap) &&
+	    !battery_design_capacity(&design_cap))
+		soh = ((full_cap * 100) / design_cap);
+	if (soh > 70 && soh <= 75)
+		rcv_soh = 50;
+	else if (soh > 60 && soh <= 70)
+		rcv_soh = 65;
+	else if (soh > 55 && soh <= 60)
+		rcv_soh = 80;
+	else if (soh > 50 && soh <= 55)
+		rcv_soh = 100;
+	else if (soh <= 50)
+		rcv_soh = 150;
+	rcv = MAX(rcv_cycle, rcv_soh);
+	curr->requested_voltage -= rcv;
+
+	/* Should not keep charging voltage > 4250mV for 48hrs. */
+	if ((curr->state == ST_DISCHARGE) || curr->chg.voltage < 4250) {
+		deadline_48.val = 0;
+		/* Starting count 48hours */
+	} else if (curr->state == ST_CHARGE || curr->state == ST_PRECHARGE) {
+		if (deadline_48.val == 0)
+			deadline_48.val = get_time().val +
+					  CHARGER_LIMIT_TIMEOUT_HOURS * HOUR;
+		/* If charging voltage keep > 4250 for 48hrs,
+		 * set charging voltage = 4250
+		 */
+		else if (timestamp_expired(deadline_48, NULL))
+			curr->requested_voltage = 4250;
+	}
+	/* Should not keeep battery voltage > 4100mV and
+	 * battery temperature > 45C for two hour
+	 */
+	if (curr->state == ST_DISCHARGE || curr->batt.voltage < 4100 ||
+	    bat_temp_c < 450) {
+		deadline_2.val = 0;
+	} else if (curr->state == ST_CHARGE || curr->state == ST_PRECHARGE) {
+		if (deadline_2.val == 0)
+			deadline_2.val =
+				get_time().val +
+				CHARGER_LIMIT_TIMEOUT_HOURS_TEMP * HOUR;
+		else if (timestamp_expired(deadline_2, NULL)) {
+			/* Set discharge and charging voltage = 4100mV */
+			if (curr->batt.voltage >= 4100) {
+				curr->requested_current = 0;
+				curr->requested_voltage = 4100;
+			}
+		}
+	}
+
+#ifdef VARIANT_KUKUI_CHARGER_MT6370
+	mt6370_charger_profile_override(curr);
+#endif /* CONFIG_CHARGER_MT6370 */
+
+	return 0;
+}
+
+enum ec_status charger_profile_override_get_param(uint32_t param,
+						  uint32_t *value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+enum ec_status charger_profile_override_set_param(uint32_t param,
+						  uint32_t value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+int get_battery_manufacturer_name(char *dest, int size)
+{
+	static const char *const name[] = {
+		[BATTERY_CPT] = "AS1XXXD3Ka",
+	};
+	ASSERT(dest);
+	strzcpy(dest, name[BATT_ID], size);
+	return EC_SUCCESS;
+}
diff --git a/baseboard/kukui/battery_max17055.c b/baseboard/kukui/battery_max17055.c
index 972bd13700..5ebb220b0c 100644
--- a/baseboard/kukui/battery_max17055.c
+++ b/baseboard/kukui/battery_max17055.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -6,6 +6,7 @@
  */
 
 #include "battery.h"
+#include "builtin/assert.h"
 #include "charge_state.h"
 #include "charger_mt6370.h"
 #include "console.h"
@@ -15,25 +16,14 @@
 
 #define TEMP_OUT_OF_RANGE TEMP_ZONE_COUNT
 
-#ifdef BOARD_KAKADU
-#define BATT_ID 1
-#else
 #define BATT_ID 0
-#endif
 
 #define BATTERY_SIMPLO_CHARGE_MIN_TEMP 0
 #define BATTERY_SIMPLO_CHARGE_MAX_TEMP 60
 
-#define BATTERY_ATL_CHARGE_MIN_TEMP -20
-#define BATTERY_ATL_CHARGE_MAX_TEMP 60
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-
-enum battery_type {
-	BATTERY_SIMPLO = 0,
-	BATTERY_ATL,
-	BATTERY_COUNT
-};
+enum battery_type { BATTERY_SIMPLO = 0, BATTERY_COUNT };
 
 static const struct battery_info info[] = {
 	[BATTERY_SIMPLO] = {
@@ -48,18 +38,6 @@ static const struct battery_info info[] = {
 		.discharging_min_c	= -20,
 		.discharging_max_c	= 60,
 	},
-	[BATTERY_ATL] = {
-		.voltage_max		= 4370,
-		.voltage_normal		= 3860,
-		.voltage_min		= 3150,
-		.precharge_current	= 256,
-		.start_charging_min_c	= 0,
-		.start_charging_max_c	= 45,
-		.charging_min_c		= 0,
-		.charging_max_c		= 60,
-		.discharging_min_c	= -20,
-		.discharging_max_c	= 60,
-	},
 };
 
 static const struct max17055_batt_profile batt_profile[] = {
@@ -69,12 +47,6 @@ static const struct max17055_batt_profile batt_profile[] = {
 		.ichg_term		= MAX17055_ICHGTERM_REG(235),
 		.v_empty_detect		= MAX17055_VEMPTY_REG(3000, 3600),
 	},
-	[BATTERY_ATL] = {
-		.is_ez_config		= 1,
-		.design_cap		= MAX17055_DESIGNCAP_REG(7270),
-		.ichg_term		= MAX17055_ICHGTERM_REG(500),
-		.v_empty_detect		= MAX17055_VEMPTY_REG(3000, 3600),
-	},
 };
 
 static const struct max17055_alert_profile alert_profile[] = {
@@ -86,14 +58,6 @@ static const struct max17055_alert_profile alert_profile[] = {
 		.s_alert_mxmn = SALRT_DISABLE,
 		.i_alert_mxmn = IALRT_DISABLE,
 	},
-	[BATTERY_ATL] = {
-		.v_alert_mxmn = VALRT_DISABLE,
-		.t_alert_mxmn = MAX17055_TALRTTH_REG(
-			BATTERY_ATL_CHARGE_MAX_TEMP,
-			BATTERY_ATL_CHARGE_MIN_TEMP),
-		.s_alert_mxmn = SALRT_DISABLE,
-		.i_alert_mxmn = IALRT_DISABLE,
-	},
 };
 
 const struct max17055_batt_profile *max17055_get_batt_profile(void)
@@ -120,11 +84,6 @@ enum battery_disconnect_state battery_get_disconnect_state(void)
 
 int charger_profile_override(struct charge_state_data *curr)
 {
-#ifdef BOARD_KAKADU
-	static timestamp_t deadline_48;
-	static timestamp_t deadline_2;
-	int cycle_count = 0, rv, val;
-#endif
 	/* battery temp in 0.1 deg C */
 	int bat_temp_c = curr->batt.temperature - 2731;
 
@@ -160,16 +119,6 @@ int charger_profile_override(struct charge_state_data *curr)
 			/* TEMP_ZONE_3 */
 			{450, BATTERY_SIMPLO_CHARGE_MAX_TEMP * 10, 3350, 4300},
 		},
-		[BATTERY_ATL] = {
-			/* TEMP_ZONE_0 */
-			{BATTERY_ATL_CHARGE_MIN_TEMP * 10, 50, 719, 4370},
-			/* TEMP_ZONE_1 */
-			{50, 100, 2157, 4370},
-			/* TEMP_ZONE_2 */
-			{100, 450, 3595, 4370},
-			/* TEMP_ZONE_3 */
-			{450, BATTERY_ATL_CHARGE_MAX_TEMP * 10, 2516, 4100},
-		},
 	};
 	BUILD_ASSERT(ARRAY_SIZE(temp_zones[BATT_ID]) == TEMP_ZONE_COUNT);
 	BUILD_ASSERT(ARRAY_SIZE(temp_zones) == BATTERY_COUNT);
@@ -181,7 +130,7 @@ int charger_profile_override(struct charge_state_data *curr)
 	else {
 		for (temp_zone = 0; temp_zone < TEMP_ZONE_COUNT; temp_zone++) {
 			if (bat_temp_c <
-				temp_zones[BATT_ID][temp_zone].temp_max)
+			    temp_zones[BATT_ID][temp_zone].temp_max)
 				break;
 		}
 	}
@@ -206,53 +155,6 @@ int charger_profile_override(struct charge_state_data *curr)
 		break;
 	}
 
-#ifdef BOARD_KAKADU
-	/* Check cycle count to decrease charging voltage. */
-	rv = battery_cycle_count(&val);
-	if (!rv)
-		cycle_count = val;
-	if (cycle_count > 300 && cycle_count <= 600)
-		curr->requested_voltage = 4320;
-	else if (cycle_count > 600 && cycle_count <= 1000)
-		curr->requested_voltage = 4300;
-	else if (cycle_count > 1000)
-		curr->requested_voltage = 4250;
-	/* Should not keep charging voltage > 4250mV for 48hrs. */
-	if ((curr->state == ST_DISCHARGE) ||
-		curr->chg.voltage < 4250) {
-		deadline_48.val = 0;
-	/* Starting count 48hours */
-	} else if (curr->state == ST_CHARGE ||
-		curr->state == ST_PRECHARGE) {
-		if (deadline_48.val == 0)
-			deadline_48.val = get_time().val +
-				CHARGER_LIMIT_TIMEOUT_HOURS * HOUR;
-		/* If charging voltage keep > 4250 for 48hrs,
-		set charging voltage = 4250 */
-		else if (timestamp_expired(deadline_48, NULL))
-			curr->requested_voltage = 4250;
-	}
-	/* Should not keeep battery voltage > 4100mV and
-	 battery temperature > 45C for two hour */
-	if (curr->state == ST_DISCHARGE ||
-		curr->batt.voltage < 4100 ||
-		bat_temp_c < 450) {
-		deadline_2.val = 0;
-	} else if (curr->state == ST_CHARGE ||
-		curr->state == ST_PRECHARGE) {
-		if (deadline_2.val == 0)
-			deadline_2.val = get_time().val +
-				CHARGER_LIMIT_TIMEOUT_HOURS_TEMP * HOUR;
-		else if (timestamp_expired(deadline_2, NULL)) {
-			/* Set discharge and charging voltage = 4100mV */
-			if (curr->batt.voltage >= 4100) {
-				curr->requested_current = 0;
-				curr->requested_voltage = 4100;
-			}
-		}
-	}
-#endif
-
 #ifdef VARIANT_KUKUI_CHARGER_MT6370
 	mt6370_charger_profile_override(curr);
 #endif /* CONFIG_CHARGER_MT6370 */
@@ -274,12 +176,10 @@ enum ec_status charger_profile_override_set_param(uint32_t param,
 
 int get_battery_manufacturer_name(char *dest, int size)
 {
-	static const char * const name[] = {
+	static const char *const name[] = {
 		[BATTERY_SIMPLO] = "SIMPLO",
-		[BATTERY_ATL] = "Celxpert",
 	};
 	ASSERT(dest);
 	strzcpy(dest, name[BATT_ID], size);
 	return EC_SUCCESS;
 }
-
diff --git a/baseboard/kukui/battery_mm8013.c b/baseboard/kukui/battery_mm8013.c
index e7f422e561..26507d5915 100644
--- a/baseboard/kukui/battery_mm8013.c
+++ b/baseboard/kukui/battery_mm8013.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -22,12 +22,9 @@
 
 #define BAT_LEVEL_PD_LIMIT 85
 
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
-enum battery_type {
-	BATTERY_SCUD = 0,
-	BATTERY_COUNT
-};
+enum battery_type { BATTERY_SCUD = 0, BATTERY_COUNT };
 
 static const struct battery_info info[] = {
 	[BATTERY_SCUD] = {
@@ -100,7 +97,7 @@ int charger_profile_override(struct charge_state_data *curr)
 	else {
 		for (temp_zone = 0; temp_zone < TEMP_ZONE_COUNT; temp_zone++) {
 			if (bat_temp_c <
-				temp_zones[BATT_ID][temp_zone].temp_max)
+			    temp_zones[BATT_ID][temp_zone].temp_max)
 				break;
 		}
 	}
diff --git a/baseboard/kukui/battery_smart.c b/baseboard/kukui/battery_smart.c
index ba2af17443..b924b2e3a9 100644
--- a/baseboard/kukui/battery_smart.c
+++ b/baseboard/kukui/battery_smart.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -98,39 +98,30 @@ __override void board_battery_compensate_params(struct batt_params *batt)
 
 	/* return cached values for at most CACHE_INVALIDATION_TIME_US */
 	fix_single_param(batt->flags & BATT_FLAG_BAD_STATE_OF_CHARGE,
-			&batt_cache.state_of_charge,
-			&batt->state_of_charge);
+			 &batt_cache.state_of_charge, &batt->state_of_charge);
 	fix_single_param(batt->flags & BATT_FLAG_BAD_VOLTAGE,
-			&batt_cache.voltage,
-			&batt->voltage);
+			 &batt_cache.voltage, &batt->voltage);
 	fix_single_param(batt->flags & BATT_FLAG_BAD_CURRENT,
-			&batt_cache.current,
-			&batt->current);
+			 &batt_cache.current, &batt->current);
 	fix_single_param(batt->flags & BATT_FLAG_BAD_DESIRED_VOLTAGE,
-			&batt_cache.desired_voltage,
-			&batt->desired_voltage);
+			 &batt_cache.desired_voltage, &batt->desired_voltage);
 	fix_single_param(batt->flags & BATT_FLAG_BAD_DESIRED_CURRENT,
-			&batt_cache.desired_current,
-			&batt->desired_current);
+			 &batt_cache.desired_current, &batt->desired_current);
 	fix_single_param(batt->flags & BATT_FLAG_BAD_REMAINING_CAPACITY,
-			&batt_cache.remaining_capacity,
-			&batt->remaining_capacity);
+			 &batt_cache.remaining_capacity,
+			 &batt->remaining_capacity);
 	fix_single_param(batt->flags & BATT_FLAG_BAD_FULL_CAPACITY,
-			&batt_cache.full_capacity,
-			&batt->full_capacity);
-	fix_single_param(batt->flags & BATT_FLAG_BAD_STATUS,
-			&batt_cache.status,
-			&batt->status);
+			 &batt_cache.full_capacity, &batt->full_capacity);
+	fix_single_param(batt->flags & BATT_FLAG_BAD_STATUS, &batt_cache.status,
+			 &batt->status);
 	fix_single_param(batt->flags & BATT_FLAG_BAD_TEMPERATURE,
-			&batt_cache.temperature,
-			&batt->temperature);
+			 &batt_cache.temperature, &batt->temperature);
 	/*
 	 * If battery_compensate_params() didn't calculate display_charge
 	 * for us, also update it with last good value.
 	 */
-	fix_single_param(batt->display_charge == 0,
-			&batt_cache.display_charge,
-			&batt->display_charge);
+	fix_single_param(batt->display_charge == 0, &batt_cache.display_charge,
+			 &batt->display_charge);
 
 	/* remove bad flags after applying cached values */
 	batt->flags &= ~BATT_FLAG_BAD_ANY;
diff --git a/baseboard/kukui/build.mk b/baseboard/kukui/build.mk
index ab62483bc7..f35ed1f4ce 100644
--- a/baseboard/kukui/build.mk
+++ b/baseboard/kukui/build.mk
@@ -1,24 +1,28 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
 # Baseboard specific files build
 #
 
+# Select eMMC CMD0 driver.
+EMMC_CMD0_DRIVER=$(if $(CHIP_IT83XX),emmc_ite.o,emmc.o)
+
 baseboard-y=baseboard.o
 baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
-baseboard-$(CONFIG_BOOTBLOCK)+=emmc.o
+baseboard-$(CONFIG_BOOTBLOCK)+=$(EMMC_CMD0_DRIVER)
 
 baseboard-$(VARIANT_KUKUI_BATTERY_MAX17055)+=battery_max17055.o
 baseboard-$(VARIANT_KUKUI_BATTERY_MM8013)+=battery_mm8013.o
+baseboard-$(VARIANT_KUKUI_BATTERY_BQ27541)+=battery_bq27541.o
 baseboard-$(VARIANT_KUKUI_BATTERY_SMART)+=battery_smart.o
 
 baseboard-$(VARIANT_KUKUI_CHARGER_MT6370)+=charger_mt6370.o
 
 baseboard-$(VARIANT_KUKUI_POGO_KEYBOARD)+=base_detect_kukui.o
 
-$(out)/RO/baseboard/$(BASEBOARD)/emmc.o: $(out)/bootblock_data.h
+$(out)/RO/baseboard/$(BASEBOARD)/$(EMMC_CMD0_DRIVER): $(out)/bootblock_data.h
 
 # bootblock size from 12769.0
 DEFAULT_BOOTBLOCK_SIZE:=21504
diff --git a/baseboard/kukui/charger_mt6370.c b/baseboard/kukui/charger_mt6370.c
index 5e78a100c5..c4300c5552 100644
--- a/baseboard/kukui/charger_mt6370.c
+++ b/baseboard/kukui/charger_mt6370.c
@@ -1,10 +1,10 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "charge_manager.h"
-#include "charge_state_v2.h"
+#include "charge_state.h"
 #include "charger_mt6370.h"
 #include "console.h"
 #include "driver/charger/rt946x.h"
@@ -51,7 +51,7 @@ static void update_plt_resume(void)
 }
 DECLARE_HOOK(HOOK_CHIPSET_RESUME, update_plt_resume, HOOK_PRIO_DEFAULT);
 
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 /* wait time to evaluate charger thermal status */
 static timestamp_t thermal_wait_until;
@@ -77,7 +77,8 @@ int board_cut_off_battery(void)
 static void board_set_charge_limit_throttle(int charge_ma, int charge_mv)
 {
 	charge_set_input_current_limit(
-		MIN(throttled_ma, MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT)),
+		MIN(throttled_ma,
+		    MAX(charge_ma, CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT)),
 		charge_mv);
 }
 
@@ -117,7 +118,7 @@ static void battery_thermal_control(struct charge_state_data *curr)
 		return;
 
 	/* If we fail to read input curr limit, skip for this cycle. */
-	if (charger_get_input_current(CHARGER_SOLO, &input_current))
+	if (charger_get_input_current_limit(CHARGER_SOLO, &input_current))
 		return;
 
 	/*
@@ -155,7 +156,7 @@ static void battery_thermal_control(struct charge_state_data *curr)
 	thermal_wait_until.val = get_time().val + (3 * SECOND);
 }
 
-int command_jc(int argc, char **argv)
+static int command_jc(int argc, const char **argv)
 {
 	static int prev_jc_temp;
 	int jc_temp;
@@ -304,8 +305,8 @@ void mt6370_charger_profile_override(struct charge_state_data *curr)
 				 * and TE function.
 				 */
 				hook_call_deferred(
-						&charge_enable_eoc_and_te_data,
-						(4.5 * SECOND));
+					&charge_enable_eoc_and_te_data,
+					(4.5 * SECOND));
 			}
 		}
 	}
@@ -329,17 +330,16 @@ void mt6370_charger_profile_override(struct charge_state_data *curr)
 
 	/*
 	 * When the charger says it's done charging, even if fuel gauge says
-	 * SOC < BATTERY_LEVEL_NEAR_FULL, we'll overwrite SOC with
-	 * BATTERY_LEVEL_NEAR_FULL. So we can ensure both Chrome OS UI
+	 * SOC < CONFIG_BATT_HOST_FULL_FACTOR, we'll overwrite SOC with
+	 * CONFIG_BATT_HOST_FULL_FACTOR. So we can ensure both Chrome OS UI
 	 * and battery LED indicate full charge.
 	 *
 	 * Enable this hack on on-board gauge only (b/142097561)
 	 */
 	if (IS_ENABLED(CONFIG_BATTERY_MAX17055) && rt946x_is_charge_done()) {
-		curr->batt.state_of_charge = MAX(BATTERY_LEVEL_NEAR_FULL,
+		curr->batt.state_of_charge = MAX(CONFIG_BATT_HOST_FULL_FACTOR,
 						 curr->batt.state_of_charge);
 	}
-
 }
 
 #ifndef CONFIG_BATTERY_SMART
@@ -352,13 +352,12 @@ static void board_charge_termination(void)
 			te = 1;
 	}
 }
-DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE,
-	     board_charge_termination,
+DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, board_charge_termination,
 	     HOOK_PRIO_DEFAULT);
 #endif
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
 {
 	prev_charge_limit = charge_ma;
 	prev_charge_mv = charge_mv;
diff --git a/baseboard/kukui/charger_mt6370.h b/baseboard/kukui/charger_mt6370.h
index 880b00a1a8..1de4e66b0b 100644
--- a/baseboard/kukui/charger_mt6370.h
+++ b/baseboard/kukui/charger_mt6370.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/baseboard/kukui/emmc.c b/baseboard/kukui/emmc.c
index 4735f4aea8..416d44c634 100644
--- a/baseboard/kukui/emmc.c
+++ b/baseboard/kukui/emmc.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -28,6 +28,7 @@
  * case we interrupt the transfer, and the BootROM will try again.
  */
 
+#include "bootblock_data.h"
 #include "chipset.h"
 #include "clock.h"
 #include "console.h"
@@ -41,10 +42,8 @@
 #include "timer.h"
 #include "util.h"
 
-#include "bootblock_data.h"
-
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SPI, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SPI, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SPI, format, ##args)
 
 #if EMMC_SPI_PORT == 1
 #define STM32_SPI_EMMC_REGS STM32_SPI1_REGS
@@ -68,7 +67,7 @@ static timestamp_t boot_deadline;
 
 /* 1024 bytes circular buffer is enough for ~0.6ms @ 13Mhz. */
 #define SPI_RX_BUF_BYTES 1024
-#define SPI_RX_BUF_WORDS (SPI_RX_BUF_BYTES/4)
+#define SPI_RX_BUF_WORDS (SPI_RX_BUF_BYTES / 4)
 static uint32_t in_msg[SPI_RX_BUF_WORDS];
 
 /* Macros to advance in the circular buffer. */
@@ -92,7 +91,7 @@ static const struct dma_option dma_tx_option = {
 static const struct dma_option dma_rx_option = {
 	STM32_DMAC_SPI_EMMC_RX, (void *)&STM32_SPI_EMMC_REGS->dr,
 	STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
-	STM32_DMA_CCR_CIRC
+		STM32_DMA_CCR_CIRC
 };
 
 /* Setup DMA to transfer bootblock. */
@@ -123,7 +122,7 @@ static void bootblock_stop(void)
 	 */
 	start = __hw_clock_source_read();
 	while (STM32_SPI_EMMC_REGS->sr & STM32_SPI_SR_FTLVL &&
-			__hw_clock_source_read() - start < timeout)
+	       __hw_clock_source_read() - start < timeout)
 		;
 
 	/* Then flush SPI FIFO, and make sure DAT line stays idle (high). */
@@ -152,8 +151,8 @@ static enum emmc_cmd emmc_parse_command(int index)
 	/* Number of leading ones. */
 	shift0 = __builtin_clz(~data[0]);
 
-	data[0] = (data[0] << shift0) | (data[1] >> (32-shift0));
-	data[1] = (data[1] << shift0) | (data[2] >> (32-shift0));
+	data[0] = (data[0] << shift0) | (data[1] >> (32 - shift0));
+	data[1] = (data[1] << shift0) | (data[2] >> (32 - shift0));
 
 	if (data[0] == 0x40000000 && data[1] == 0x0095ffff) {
 		/* 400000000095 GO_IDLE_STATE */
@@ -177,7 +176,6 @@ static enum emmc_cmd emmc_parse_command(int index)
 	return EMMC_ERROR;
 }
 
-
 /*
  * Wake the EMMC task when there is a falling edge on the CMD line, so that we
  * can capture the command.
@@ -198,12 +196,21 @@ static void emmc_init_spi(void)
 	/* Enable clocks to SPI module */
 	STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1;
 #elif EMMC_SPI_PORT == 2
+#ifdef CHIP_FAMILY_STM32L4
+	/* Reset SPI */
+	STM32_RCC_APB1RSTR1 |= STM32_RCC_PB1_SPI2;
+	STM32_RCC_APB1RSTR1 &= ~STM32_RCC_PB1_SPI2;
+
+	/* Enable clocks to SPI module */
+	STM32_RCC_APB1ENR1 |= STM32_RCC_PB1_SPI2;
+#else
 	/* Reset SPI */
 	STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2;
 	STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
 
 	/* Enable clocks to SPI module */
 	STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
+#endif
 #else
 #error "Please define EMMC_SPI_PORT in board.h."
 #endif
diff --git a/baseboard/kukui/emmc_ite.c b/baseboard/kukui/emmc_ite.c
new file mode 100644
index 0000000000..6ac0200c1d
--- /dev/null
+++ b/baseboard/kukui/emmc_ite.c
@@ -0,0 +1,204 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "bootblock_data.h"
+#include "chipset.h"
+#include "console.h"
+#include "endian.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "hwtimer.h"
+#include "intc.h"
+#include "system.h"
+#include "task.h"
+#include "timer.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_SPI, format, ##args)
+
+enum emmc_cmd {
+	EMMC_ERROR = -1,
+	EMMC_IDLE = 0,
+	EMMC_PRE_IDLE,
+	EMMC_BOOT,
+};
+
+static void emmc_reset_spi_tx(void)
+{
+	/* Reset TX FIFO and count monitor */
+	IT83XX_SPI_TXFCR = IT83XX_SPI_TXFR | IT83XX_SPI_TXFCMR;
+	/* Send idle state (high/0xff) if master clocks in data. */
+	IT83XX_SPI_FCR = 0;
+}
+
+static void emmc_reset_spi_rx(void)
+{
+	/* End Rx FIFO access */
+	IT83XX_SPI_TXRXFAR = 0;
+	/* Reset RX FIFO and count monitor */
+	IT83XX_SPI_FCR = IT83XX_SPI_RXFR | IT83XX_SPI_RXFCMR;
+}
+
+/*
+ * Set SPI module work as eMMC Alternative Boot Mode.
+ * (CS# pin isn't required, and dropping data until CMD goes low)
+ */
+static void emmc_enable_spi(void)
+{
+	/* Set SPI pin mux to eMMC (GPM2:CLK, GPM3:CMD, GPM6:DATA0) */
+	IT83XX_GCTRL_PIN_MUX0 |= BIT(7);
+	/* Enable eMMC Alternative Boot Mode */
+	IT83XX_SPI_EMMCBMR |= IT83XX_SPI_EMMCABM;
+	/* Reset TX and RX FIFO */
+	emmc_reset_spi_tx();
+	emmc_reset_spi_rx();
+	/* Response idle state (high) */
+	IT83XX_SPI_SPISRDR = 0xff;
+	/* FIFO will be overwritten once it's full */
+	IT83XX_SPI_GCR2 = 0;
+	/* Write to clear pending interrupt bits */
+	IT83XX_SPI_ISR = 0xff;
+	IT83XX_SPI_RX_VLISR = IT83XX_SPI_RVLI;
+	/* Enable RX fifo full interrupt */
+	IT83XX_SPI_IMR = 0xff;
+	IT83XX_SPI_RX_VLISMR |= IT83XX_SPI_RVLIM;
+	IT83XX_SPI_IMR &= ~IT83XX_SPI_RX_FIFO_FULL;
+	/*
+	 * Enable interrupt to detect AP's BOOTBLOCK_EN_L. So EC is able to
+	 * switch SPI module back to communication mode once BOOTBLOCK_EN_L
+	 * goes high (AP Jumped to bootloader).
+	 */
+	gpio_clear_pending_interrupt(GPIO_BOOTBLOCK_EN_L);
+	gpio_enable_interrupt(GPIO_BOOTBLOCK_EN_L);
+
+	disable_sleep(SLEEP_MASK_EMMC);
+	CPRINTS("eMMC emulation enabled");
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, emmc_enable_spi, HOOK_PRIO_FIRST);
+
+static void emmc_init_spi(void)
+{
+	/* Enable alternate function */
+	gpio_config_module(MODULE_SPI_FLASH, 1);
+}
+DECLARE_HOOK(HOOK_INIT, emmc_init_spi, HOOK_PRIO_INIT_SPI + 1);
+
+static void emmc_send_data_over_spi(uint8_t *tx, int tx_size, int rst_tx)
+{
+	int i;
+
+	/* Reset TX FIFO and count monitor */
+	if (rst_tx)
+		IT83XX_SPI_TXFCR = IT83XX_SPI_TXFR | IT83XX_SPI_TXFCMR;
+	/* CPU access TX FIFO1 and FIFO2 */
+	IT83XX_SPI_TXRXFAR = IT83XX_SPI_CPUTFA;
+
+	/* Write response data to TX FIFO */
+	for (i = 0; i < tx_size; i += 4)
+		IT83XX_SPI_CPUWTFDB0 = *(uint32_t *)(tx + i);
+	/*
+	 * After writing data to TX FIFO is finished, this bit will
+	 * be to indicate the SPI peripheral controller.
+	 */
+	IT83XX_SPI_TXFCR = IT83XX_SPI_TXFS;
+	/* End CPU access TX FIFO */
+	IT83XX_SPI_TXRXFAR = 0;
+	/* SPI module access TX FIFO */
+	IT83XX_SPI_FCR = IT83XX_SPI_SPISRTXF;
+}
+
+static void emmc_bootblock_transfer(void)
+{
+	int tx_size, sent = 0, remaining = sizeof(bootblock_raw_data);
+	uint8_t *raw = (uint8_t *)bootblock_raw_data;
+	const uint32_t timeout_us = 200;
+	uint32_t start;
+
+	/*
+	 * HW will transmit the data of FIFO1 or FIFO2 in turn.
+	 * So when a FIFO is empty, we need to fill the FIFO out
+	 * immediately.
+	 */
+	emmc_send_data_over_spi(&raw[sent], 256, 1);
+	sent += 256;
+
+	while (sent < remaining) {
+		/* Wait for FIFO1 or FIFO2 have been transmitted */
+		start = __hw_clock_source_read();
+		while (!(IT83XX_SPI_TXFSR & BIT(0)) &&
+		       (__hw_clock_source_read() - start < timeout_us))
+			;
+		/* Abort an ongoing transfer due to a command is received. */
+		if (IT83XX_SPI_ISR & IT83XX_SPI_RX_FIFO_FULL)
+			break;
+		/* fill out next 128 bytes to FIFO1 or FIFO2 */
+		tx_size = (remaining - sent) < 128 ? (remaining - sent) : 128;
+		emmc_send_data_over_spi(&raw[sent], tx_size, 0);
+		sent += tx_size;
+	}
+}
+
+static enum emmc_cmd emmc_parse_command(int index, uint32_t *cmd0)
+{
+	int32_t shift0;
+	uint32_t data[3];
+
+	data[0] = htobe32(cmd0[index]);
+	data[1] = htobe32(cmd0[index + 1]);
+	data[2] = htobe32(cmd0[index + 2]);
+
+	if ((data[0] & 0xff000000) != 0x40000000) {
+		/* Figure out alignment (cmd starts with 01) */
+		/* Number of leading ones. */
+		shift0 = __builtin_clz(~data[0]);
+
+		data[0] = (data[0] << shift0) | (data[1] >> (32 - shift0));
+		data[1] = (data[1] << shift0) | (data[2] >> (32 - shift0));
+	}
+
+	if (data[0] == 0x40000000 && data[1] == 0x0095ffff) {
+		/* 400000000095 GO_IDLE_STATE */
+		CPRINTS("goIdle");
+		return EMMC_IDLE;
+	}
+
+	if (data[0] == 0x40f0f0f0 && data[1] == 0xf0fdffff) {
+		/* 40f0f0f0f0fd GO_PRE_IDLE_STATE */
+		CPRINTS("goPreIdle");
+		return EMMC_PRE_IDLE;
+	}
+
+	if (data[0] == 0x40ffffff && data[1] == 0xfae5ffff) {
+		/* 40fffffffae5 BOOT_INITIATION */
+		CPRINTS("bootInit");
+		return EMMC_BOOT;
+	}
+
+	CPRINTS("eMMC error");
+	return EMMC_ERROR;
+}
+
+void spi_emmc_cmd0_isr(uint32_t *cmd0_payload)
+{
+	enum emmc_cmd cmd;
+
+	for (int i = 0; i < 8; i++) {
+		if (cmd0_payload[i] == 0xffffffff)
+			continue;
+
+		cmd = emmc_parse_command(i, &cmd0_payload[i]);
+
+		if (cmd == EMMC_IDLE || cmd == EMMC_PRE_IDLE) {
+			/* Abort an ongoing transfer. */
+			emmc_reset_spi_tx();
+			break;
+		}
+
+		if (cmd == EMMC_BOOT) {
+			emmc_bootblock_transfer();
+			break;
+		}
+	}
+}
diff --git a/baseboard/kukui/usb_pd_policy.c b/baseboard/kukui/usb_pd_policy.c
index b2ff65b849..1ca7935762 100644
--- a/baseboard/kukui/usb_pd_policy.c
+++ b/baseboard/kukui/usb_pd_policy.c
@@ -1,13 +1,14 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "charge_manager.h"
-#include "charge_state_v2.h"
+#include "charge_state.h"
 #include "charger.h"
 #include "console.h"
 #include "gpio.h"
+#include "hooks.h"
 #include "system.h"
 #include "timer.h"
 #include "usb_mux.h"
@@ -15,20 +16,45 @@
 #include "usb_pd_policy.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 static int board_get_polarity(int port)
 {
 	/* Krane's aux mux polarity is reversed. Workaround to flip it back. */
 	if (IS_ENABLED(BOARD_KRANE) && board_get_version() == 3)
-		return !pd_get_polarity(port);
+		return !polarity_rm_dts(pd_get_polarity(port));
 
-	return pd_get_polarity(port);
+	return polarity_rm_dts(pd_get_polarity(port));
 }
 
 static uint8_t vbus_en;
 
+#define VBUS_EN_SYSJUMP_TAG 0x5645 /* VE */
+#define VBUS_EN_HOOK_VERSION 1
+
+static void vbus_en_preserve_state(void)
+{
+	system_add_jump_tag(VBUS_EN_SYSJUMP_TAG, VBUS_EN_HOOK_VERSION,
+			    sizeof(vbus_en), &vbus_en);
+}
+DECLARE_HOOK(HOOK_SYSJUMP, vbus_en_preserve_state, HOOK_PRIO_DEFAULT);
+
+static void vbus_en_restore_state(void)
+{
+	const uint8_t *prev_vbus_en;
+	int size, version;
+
+	prev_vbus_en = (const uint8_t *)system_get_jump_tag(VBUS_EN_SYSJUMP_TAG,
+							    &version, &size);
+
+	if (prev_vbus_en && version == VBUS_EN_HOOK_VERSION &&
+	    size == sizeof(*prev_vbus_en)) {
+		memcpy(&vbus_en, prev_vbus_en, sizeof(vbus_en));
+	}
+}
+DECLARE_HOOK(HOOK_INIT, vbus_en_restore_state, HOOK_PRIO_DEFAULT);
+
 int board_vbus_source_enabled(int port)
 {
 	return vbus_en;
@@ -63,7 +89,8 @@ int pd_set_power_supply_ready(int port)
 
 	gpio_set_level(GPIO_EN_USBC_CHARGE_L, 1);
 	gpio_set_level(GPIO_EN_PP5000_USBC, 1);
-	if (IS_ENABLED(CONFIG_CHARGER_OTG) && IS_ENABLED(CONFIG_CHARGER_ISL9238C))
+	if (IS_ENABLED(CONFIG_CHARGER_OTG) &&
+	    IS_ENABLED(CONFIG_CHARGER_ISL9238C))
 		charger_set_current(CHARGER_SOLO, 0);
 
 	/* notify host of power info change */
@@ -104,11 +131,8 @@ void pd_power_supply_reset(int port)
 
 int pd_check_vconn_swap(int port)
 {
-	/*
-	 * VCONN is provided directly by the battery (PPVAR_SYS)
-	 * but use the same rules as power swap.
-	 */
-	return pd_get_dual_role(port) == PD_DRP_TOGGLE_ON ? 1 : 0;
+	/* always allow vconn swap, since PSYS sources VCONN */
+	return 1;
 }
 
 /* ----------------- Vendor Defined Messages ------------------ */
@@ -119,7 +143,7 @@ __overridable int board_has_virtual_mux(void)
 }
 
 static void board_usb_mux_set(int port, mux_state_t mux_mode,
-		 enum usb_switch usb_mode, int polarity)
+			      enum usb_switch usb_mode, int polarity)
 {
 	usb_mux_set(port, mux_mode, usb_mode, polarity);
 
@@ -140,8 +164,9 @@ __override void svdm_safe_dp_mode(int port)
 __override int svdm_enter_dp_mode(int port, uint32_t mode_caps)
 {
 	/* Kukui/Krane doesn't support superspeed lanes. */
-	const uint32_t support_pin_mode = board_has_virtual_mux() ?
-		(MODE_DP_PIN_C | MODE_DP_PIN_E) : MODE_DP_PIN_ALL;
+	const uint32_t support_pin_mode =
+		board_has_virtual_mux() ? (MODE_DP_PIN_C | MODE_DP_PIN_E) :
+					  MODE_DP_PIN_ALL;
 
 	/**
 	 * Only enter mode if device is DFP_D (and PIN_C/E for Kukui/Krane)
@@ -160,7 +185,7 @@ __override int svdm_enter_dp_mode(int port, uint32_t mode_caps)
 
 __override int svdm_dp_config(int port, uint32_t *payload)
 {
-	int opos = pd_alt_mode(port, TCPC_TX_SOP, USB_SID_DISPLAYPORT);
+	int opos = pd_alt_mode(port, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT);
 	int status = dp_status[port];
 	int mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]);
 	int pin_mode;
@@ -182,11 +207,11 @@ __override int svdm_dp_config(int port, uint32_t *payload)
 			port, mf_pref ? USB_PD_MUX_DOCK : USB_PD_MUX_DP_ENABLED,
 			USB_SWITCH_CONNECT, board_get_polarity(port));
 
-	payload[0] = VDO(USB_SID_DISPLAYPORT, 1,
-			 CMD_DP_CONFIG | VDO_OPOS(opos));
-	payload[1] = VDO_DP_CFG(pin_mode,      /* pin mode */
-				1,             /* DPv1.3 signaling */
-				2);            /* UFP connected */
+	payload[0] =
+		VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_CONFIG | VDO_OPOS(opos));
+	payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */
+				1, /* DPv1.3 signaling */
+				2); /* UFP connected */
 	return 2;
 };
 
@@ -204,7 +229,8 @@ __override void svdm_dp_post_config(int port)
 	/* set the minimum time delay (2ms) for the next HPD IRQ */
 	svdm_hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
 
-	usb_mux_hpd_update(port, 1, 0);
+	usb_mux_hpd_update(port,
+			   USB_PD_MUX_HPD_LVL | USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
 
 __override int svdm_dp_attention(int port, uint32_t *payload)
@@ -212,6 +238,7 @@ __override int svdm_dp_attention(int port, uint32_t *payload)
 	int cur_lvl = gpio_get_level(GPIO_USB_C0_HPD_OD);
 	int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]);
 	int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]);
+	mux_state_t mux_state;
 
 	dp_status[port] = payload[1];
 
@@ -222,7 +249,9 @@ __override int svdm_dp_attention(int port, uint32_t *payload)
 		return 1;
 	}
 
-	usb_mux_hpd_update(port, lvl, irq);
+	mux_state = (lvl ? USB_PD_MUX_HPD_LVL : USB_PD_MUX_HPD_LVL_DEASSERTED) |
+		    (irq ? USB_PD_MUX_HPD_IRQ : USB_PD_MUX_HPD_IRQ_DEASSERTED);
+	usb_mux_hpd_update(port, mux_state);
 
 	if (irq & cur_lvl) {
 		uint64_t now = get_time().val;
@@ -240,8 +269,8 @@ __override int svdm_dp_attention(int port, uint32_t *payload)
 #endif
 
 		/* set the minimum time delay (2ms) for the next HPD IRQ */
-		svdm_hpd_deadline[port] = get_time().val +
-			HPD_USTREAM_DEBOUNCE_LVL;
+		svdm_hpd_deadline[port] =
+			get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
 	} else if (irq & !lvl) {
 		CPRINTF("ERR:HPD:IRQ&LOW\n");
 		return 0; /* nak */
@@ -251,8 +280,8 @@ __override int svdm_dp_attention(int port, uint32_t *payload)
 		board_set_dp_mux_control(lvl, board_get_polarity(port));
 #endif
 		/* set the minimum time delay (2ms) for the next HPD IRQ */
-		svdm_hpd_deadline[port] = get_time().val +
-			HPD_USTREAM_DEBOUNCE_LVL;
+		svdm_hpd_deadline[port] =
+			get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
 	}
 
 	/* ack */
@@ -261,11 +290,11 @@ __override int svdm_dp_attention(int port, uint32_t *payload)
 
 __override void svdm_exit_dp_mode(int port)
 {
-	svdm_safe_dp_mode(port);
 	gpio_set_level(GPIO_USB_C0_HPD_OD, 0);
 #ifdef VARIANT_KUKUI_DP_MUX_GPIO
 	board_set_dp_mux_control(0, 0);
 #endif
-	usb_mux_hpd_update(port, 0, 0);
+	usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
+					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
 #endif /* CONFIG_USB_PD_ALT_MODE_DFP */
diff --git a/baseboard/kukui/usb_pd_policy.h b/baseboard/kukui/usb_pd_policy.h
index 78e0213f53..62d6bda062 100644
--- a/baseboard/kukui/usb_pd_policy.h
+++ b/baseboard/kukui/usb_pd_policy.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/baseboard/mtscp-rv32i/baseboard.c b/baseboard/mtscp-rv32i/baseboard.c
new file mode 100644
index 0000000000..e9ec4c6924
--- /dev/null
+++ b/baseboard/mtscp-rv32i/baseboard.c
@@ -0,0 +1,59 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* MT SCP RV32i configuration */
+
+#include "cache.h"
+#include "csr.h"
+#include "hooks.h"
+#include "panic.h"
+#include "registers.h"
+
+#define SCP_SRAM_END (CONFIG_IPC_SHARED_OBJ_ADDR & (~(0x400 - 1)))
+
+struct mpu_entry mpu_entries[NR_MPU_ENTRIES] = {
+	/* SRAM (for most code, data) */
+	{ 0, SCP_SRAM_END, MPU_ATTR_C | MPU_ATTR_W | MPU_ATTR_R },
+	/* SRAM (for IPI shared buffer) */
+	{ SCP_SRAM_END, SCP_FW_END, MPU_ATTR_W | MPU_ATTR_R },
+/* For AP domain */
+#ifdef CHIP_VARIANT_MT8195
+	{ 0x60000000, 0x70000000, MPU_ATTR_W | MPU_ATTR_R | MPU_ATTR_P },
+#else
+	{ 0x60000000, 0x70000000, MPU_ATTR_W | MPU_ATTR_R },
+#endif
+	/* For SCP sys */
+	{ 0x70000000, 0x80000000, MPU_ATTR_W | MPU_ATTR_R },
+#ifdef CHIP_VARIANT_MT8195
+	{ 0x10000000, 0x11400000, MPU_ATTR_C | MPU_ATTR_W | MPU_ATTR_R },
+	{ CONFIG_PANIC_DRAM_BASE,
+	  CONFIG_PANIC_DRAM_BASE + CONFIG_PANIC_DRAM_SIZE,
+	  MPU_ATTR_W | MPU_ATTR_R },
+#else
+	{ 0x10000000, 0x11400000, MPU_ATTR_W | MPU_ATTR_R },
+#endif
+};
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+#ifdef CONFIG_PANIC_CONSOLE_OUTPUT
+static void report_previous_panic(void)
+{
+	struct panic_data *panic = panic_get_data();
+
+	if (panic == NULL && SCP_CORE0_MON_PC_LATCH == 0)
+		return;
+
+	ccprintf("[Previous Panic]\n");
+	if (panic) {
+		panic_data_ccprint(panic);
+	} else {
+		ccprintf("No panic data\n");
+	}
+	ccprintf("Latch PC:%x LR:%x SP:%x\n", SCP_CORE0_MON_PC_LATCH,
+		 SCP_CORE0_MON_LR_LATCH, SCP_CORE0_MON_SP_LATCH);
+}
+DECLARE_HOOK(HOOK_INIT, report_previous_panic, HOOK_PRIO_DEFAULT);
+#endif
diff --git a/baseboard/mtscp-rv32i/baseboard.h b/baseboard/mtscp-rv32i/baseboard.h
new file mode 100644
index 0000000000..49a18c8d9d
--- /dev/null
+++ b/baseboard/mtscp-rv32i/baseboard.h
@@ -0,0 +1,76 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* MT SCP RV32i board configuration */
+
+#ifndef __CROS_EC_BASEBOARD_H
+#define __CROS_EC_BASEBOARD_H
+
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_HOSTCMD) | CC_MASK(CC_IPI)))
+
+#define CONFIG_FLASH_SIZE_BYTES CONFIG_RAM_BASE
+#define CONFIG_LTO
+#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
+#define CONFIG_UART_CONSOLE 0
+
+#ifdef CHIP_VARIANT_MT8195
+#define CONFIG_PANIC_CONSOLE_OUTPUT
+#endif
+
+/* IPI configs */
+#define CONFIG_IPC_SHARED_OBJ_BUF_SIZE 288
+#define CONFIG_IPC_SHARED_OBJ_ADDR \
+	(SCP_FW_END -              \
+	 (CONFIG_IPC_SHARED_OBJ_BUF_SIZE + 2 * 4 /* int32_t */) * 2)
+#define CONFIG_IPI
+#define CONFIG_RPMSG_NAME_SERVICE
+
+#define SCP_IPI_INIT 0
+#define SCP_IPI_VDEC_H264 1
+#define SCP_IPI_VDEC_VP8 2
+#define SCP_IPI_VDEC_VP9 3
+#define SCP_IPI_VENC_H264 4
+#define SCP_IPI_VENC_VP8 5
+#define SCP_IPI_MDP_INIT 6
+#define SCP_IPI_MDP_DEINIT 7
+#define SCP_IPI_MDP_FRAME 8
+#define SCP_IPI_DIP 9
+#define SCP_IPI_ISP_CMD 10
+#define SCP_IPI_ISP_FRAME 11
+#define SCP_IPI_FD_CMD 12
+#define SCP_IPI_HOST_COMMAND 13
+#define SCP_IPI_VDEC_LAT 14
+#define SCP_IPI_VDEC_CORE 15
+#define SCP_IPI_COUNT 16
+
+#define IPI_COUNT SCP_IPI_COUNT
+
+#define SCP_IPI_NS_SERVICE 0xFF
+
+/* Access DRAM through cached access */
+#define CONFIG_DRAM_BASE 0x10000000
+/* Shared memory address in AP physical address space. */
+#define CONFIG_DRAM_BASE_LOAD 0x50000000
+#define CONFIG_DRAM_SIZE 0x01400000 /* 20 MB */
+
+/* Add some space (0x100) before panic for jump data */
+#define CONFIG_PANIC_DRAM_BASE (CONFIG_DRAM_BASE + CONFIG_DRAM_SIZE)
+#define CONFIG_PANIC_DRAM_SIZE 0x00001000 /* 4K */
+
+#define CONFIG_PANIC_BASE_OFFSET 0x100 /* reserved for jump data */
+
+#ifdef CHIP_VARIANT_MT8195
+#define CONFIG_PANIC_DATA_BASE \
+	(CONFIG_PANIC_DRAM_BASE + CONFIG_PANIC_BASE_OFFSET)
+#endif
+
+/* MPU settings */
+#define NR_MPU_ENTRIES 16
+
+#ifndef __ASSEMBLER__
+#include "gpio_signal.h"
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BASEBOARD_H */
diff --git a/baseboard/mtscp-rv32i/build.mk b/baseboard/mtscp-rv32i/build.mk
new file mode 100644
index 0000000000..90b8ded4a1
--- /dev/null
+++ b/baseboard/mtscp-rv32i/build.mk
@@ -0,0 +1,12 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Baseboard specific files build
+#
+baseboard-y+=baseboard.o
+
+baseboard-$(HAS_TASK_VDEC_SERVICE)+=vdec.o
+baseboard-$(HAS_TASK_VENC_SERVICE)+=venc.o
+baseboard-$(HAS_TASK_MDP_SERVICE)+=mdp.o
diff --git a/baseboard/mtscp-rv32i/mdp.c b/baseboard/mtscp-rv32i/mdp.c
new file mode 100644
index 0000000000..4c054dc029
--- /dev/null
+++ b/baseboard/mtscp-rv32i/mdp.c
@@ -0,0 +1,85 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "ipi_chip.h"
+#include "mdp.h"
+#include "queue_policies.h"
+#include "registers.h"
+#include "task.h"
+#include "util.h"
+
+#define CPRINTF(format, args...) cprintf(CC_IPI, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_IPI, format, ##args)
+
+static void event_mdp_written(struct consumer const *consumer, size_t count)
+{
+	task_wake(TASK_ID_MDP_SERVICE);
+}
+static struct consumer const event_mdp_consumer;
+static struct queue const event_mdp_queue = QUEUE_DIRECT(
+	4, struct mdp_msg_service, null_producer, event_mdp_consumer);
+static struct consumer const event_mdp_consumer = {
+	.queue = &event_mdp_queue,
+	.ops = &((struct consumer_ops const){
+		.written = event_mdp_written,
+	}),
+};
+
+/* Stub functions only provided by private overlays. */
+#ifndef HAVE_PRIVATE_MT_SCP
+void mdp_common_init(void)
+{
+}
+void mdp_ipi_task_handler(void *pvParameters)
+{
+}
+#endif
+
+static void mdp_ipi_handler(int id, void *data, unsigned int len)
+{
+	struct mdp_msg_service rsv_msg;
+
+	if (!len) {
+		CPRINTS("len is zero.");
+		return;
+	}
+
+	rsv_msg.id = id;
+	memcpy(rsv_msg.msg, data, MIN(len, sizeof(rsv_msg.msg)));
+
+	/*
+	 * If there is no other IPI handler touch this queue, we don't need to
+	 * interrupt_disable() or task_disable_irq().
+	 */
+	if (!queue_add_unit(&event_mdp_queue, &rsv_msg))
+		CPRINTS("Could not send mdp id: %d to the queue.", id);
+}
+DECLARE_IPI(SCP_IPI_MDP_INIT, mdp_ipi_handler, 0);
+DECLARE_IPI(SCP_IPI_MDP_FRAME, mdp_ipi_handler, 0);
+DECLARE_IPI(SCP_IPI_MDP_DEINIT, mdp_ipi_handler, 0);
+
+void mdp_service_task(void *u)
+{
+	struct mdp_msg_service rsv_msg;
+	size_t size;
+
+	mdp_common_init();
+
+	while (1) {
+		/*
+		 * Queue unit is added in IPI handler, which is in ISR context.
+		 * Disable IRQ to prevent a clobbered queue.
+		 */
+		ipi_disable_irq();
+		size = queue_remove_unit(&event_mdp_queue, &rsv_msg);
+		ipi_enable_irq();
+
+		if (!size)
+			task_wait_event(-1);
+		else
+			mdp_ipi_task_handler(&rsv_msg);
+	}
+}
diff --git a/baseboard/mtscp-rv32i/mdp.h b/baseboard/mtscp-rv32i/mdp.h
new file mode 100644
index 0000000000..48f4937ace
--- /dev/null
+++ b/baseboard/mtscp-rv32i/mdp.h
@@ -0,0 +1,20 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_SCP_MDP_H
+#define __CROS_EC_SCP_MDP_H
+
+struct mdp_msg_service {
+	int id;
+	unsigned char msg[20];
+};
+BUILD_ASSERT(member_size(struct mdp_msg_service, msg) <=
+	     CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
+
+/* Functions provided by private overlay. */
+void mdp_common_init(void);
+void mdp_ipi_task_handler(void *pvParameters);
+
+#endif /* __CROS_EC_SCP_MDP_H */
diff --git a/baseboard/mtscp-rv32i/vdec.c b/baseboard/mtscp-rv32i/vdec.c
new file mode 100644
index 0000000000..7ff98fff10
--- /dev/null
+++ b/baseboard/mtscp-rv32i/vdec.c
@@ -0,0 +1,140 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "hooks.h"
+#include "ipi_chip.h"
+#include "queue.h"
+#include "queue_policies.h"
+#include "registers.h"
+#include "task.h"
+#include "util.h"
+#include "vdec.h"
+
+#define CPRINTF(format, args...) cprintf(CC_IPI, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_IPI, format, ##args)
+
+static void event_vdec_written(struct consumer const *consumer, size_t count)
+{
+	task_wake(TASK_ID_VDEC_SERVICE);
+}
+static struct consumer const event_vdec_consumer;
+static struct queue const event_vdec_queue =
+	QUEUE_DIRECT(8, struct vdec_msg, null_producer, event_vdec_consumer);
+static struct consumer const event_vdec_consumer = {
+	.queue = &event_vdec_queue,
+	.ops = &((struct consumer_ops const){
+		.written = event_vdec_written,
+	}),
+};
+
+static void event_vdec_core_written(struct consumer const *consumer,
+				    size_t count)
+{
+	task_wake(TASK_ID_VDEC_CORE_SERVICE);
+}
+static struct consumer const event_vdec_core_consumer;
+static struct queue const event_vdec_core_queue = QUEUE_DIRECT(
+	8, struct vdec_msg, null_producer, event_vdec_core_consumer);
+static struct consumer const event_vdec_core_consumer = {
+	.queue = &event_vdec_core_queue,
+	.ops = &((struct consumer_ops const){
+		.written = event_vdec_core_written,
+	}),
+};
+
+/* Stub functions only provided by private overlays. */
+#ifndef HAVE_PRIVATE_MT_SCP
+void vdec_msg_handler(void *data)
+{
+}
+void vdec_core_msg_handler(void *data)
+{
+}
+#endif
+
+static void vdec_h264_ipi_handler(int id, void *data, uint32_t len)
+{
+	struct vdec_msg rsv_msg;
+
+	if (!len) {
+		CPRINTS("len is zero.");
+		return;
+	}
+
+	rsv_msg.type = VDEC_LAT;
+	memcpy(rsv_msg.msg, data, MIN(len, sizeof(rsv_msg.msg)));
+
+	/*
+	 * If there is no other IPI handler touch this queue, we don't need to
+	 * interrupt_disable() or task_disable_irq().
+	 */
+	if (!queue_add_unit(&event_vdec_queue, &rsv_msg))
+		CPRINTS("Could not send vdec %d to the queue.", rsv_msg.type);
+}
+DECLARE_IPI(SCP_IPI_VDEC_LAT, vdec_h264_ipi_handler, 0);
+
+static void vdec_h264_ipi_core_handler(int id, void *data, uint32_t len)
+{
+	struct vdec_msg rsv_msg;
+
+	if (!len) {
+		CPRINTS("len is zero.");
+		return;
+	}
+
+	rsv_msg.type = VDEC_CORE;
+	memcpy(rsv_msg.msg, data, MIN(len, sizeof(rsv_msg.msg)));
+
+	/*
+	 * If there is no other IPI handler touch this queue, we don't need to
+	 * interrupt_disable() or task_disable_irq().
+	 */
+	if (!queue_add_unit(&event_vdec_core_queue, &rsv_msg))
+		CPRINTS("Could not send vdec %d to core queue.", rsv_msg.type);
+}
+DECLARE_IPI(SCP_IPI_VDEC_CORE, vdec_h264_ipi_core_handler, 0);
+
+void vdec_service_task(void *u)
+{
+	struct vdec_msg rsv_msg;
+	size_t size;
+
+	while (1) {
+		/*
+		 * Queue unit is added in IPI handler, which is in ISR context.
+		 * Disable IRQ to prevent a clobbered queue.
+		 */
+		ipi_disable_irq();
+		size = queue_remove_unit(&event_vdec_queue, &rsv_msg);
+		ipi_enable_irq();
+
+		if (!size)
+			task_wait_event(-1);
+		else
+			vdec_msg_handler(rsv_msg.msg);
+	}
+}
+
+void vdec_core_service_task(void *u)
+{
+	struct vdec_msg rsv_msg;
+	size_t size;
+
+	while (1) {
+		/*
+		 * Queue unit is added in IPI handler, which is in ISR context.
+		 * Disable IRQ to prevent a clobbered queue.
+		 */
+		ipi_disable_irq();
+		size = queue_remove_unit(&event_vdec_core_queue, &rsv_msg);
+		ipi_enable_irq();
+
+		if (!size)
+			task_wait_event(-1);
+		else
+			vdec_core_msg_handler(rsv_msg.msg);
+	}
+}
diff --git a/baseboard/mtscp-rv32i/vdec.h b/baseboard/mtscp-rv32i/vdec.h
new file mode 100644
index 0000000000..c203c09fae
--- /dev/null
+++ b/baseboard/mtscp-rv32i/vdec.h
@@ -0,0 +1,28 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_SCP_VDEC_H
+#define __CROS_EC_SCP_VDEC_H
+
+#include "compile_time_macros.h"
+
+enum vdec_type {
+	VDEC_LAT,
+	VDEC_CORE,
+	VDEC_MAX,
+};
+
+struct vdec_msg {
+	enum vdec_type type;
+	unsigned char msg[48];
+};
+BUILD_ASSERT(member_size(struct vdec_msg, msg) <=
+	     CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
+
+/* Functions provided by private overlay. */
+void vdec_core_msg_handler(void *msg);
+void vdec_msg_handler(void *msg);
+
+#endif /* __CROS_EC_SCP_VDEC_H */
diff --git a/baseboard/mtscp-rv32i/venc.c b/baseboard/mtscp-rv32i/venc.c
new file mode 100644
index 0000000000..bed2a2dbc6
--- /dev/null
+++ b/baseboard/mtscp-rv32i/venc.c
@@ -0,0 +1,87 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "hooks.h"
+#include "ipi_chip.h"
+#include "queue.h"
+#include "queue_policies.h"
+#include "registers.h"
+#include "task.h"
+#include "util.h"
+#include "venc.h"
+
+#define CPRINTF(format, args...) cprintf(CC_IPI, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_IPI, format, ##args)
+
+static void event_venc_written(struct consumer const *consumer, size_t count)
+{
+	task_wake(TASK_ID_VENC_SERVICE);
+}
+static struct consumer const event_venc_consumer;
+static struct queue const event_venc_queue =
+	QUEUE_DIRECT(8, struct venc_msg, null_producer, event_venc_consumer);
+static struct consumer const event_venc_consumer = {
+	.queue = &event_venc_queue,
+	.ops = &((struct consumer_ops const){
+		.written = event_venc_written,
+	}),
+};
+
+/* Stub functions only provided by private overlays. */
+#ifndef HAVE_PRIVATE_MT_SCP
+void venc_h264_msg_handler(void *data)
+{
+}
+#endif
+
+static void venc_h264_ipi_handler(int id, void *data, uint32_t len)
+{
+	struct venc_msg rsv_msg;
+
+	if (!len) {
+		CPRINTS("len is zero.");
+		return;
+	}
+
+	rsv_msg.type = VENC_H264;
+	memcpy(rsv_msg.msg, data, MIN(len, sizeof(rsv_msg.msg)));
+
+	/*
+	 * If there is no other IPI handler touch this queue, we don't need to
+	 * interrupt_disable() or task_disable_irq().
+	 */
+	if (!queue_add_unit(&event_venc_queue, &rsv_msg))
+		CPRINTS("Could not send venc %d to the queue.", rsv_msg.type);
+}
+DECLARE_IPI(SCP_IPI_VENC_H264, venc_h264_ipi_handler, 0);
+
+void venc_service_task(void *u)
+{
+	struct venc_msg rsv_msg;
+	size_t size;
+
+	typedef void (*venc_msg_handler)(void *msg);
+	static venc_msg_handler mtk_venc_msg_handle[VENC_MAX] = {
+		[VENC_H264] = venc_h264_msg_handler,
+	};
+
+	while (1) {
+		/*
+		 * Queue unit is added in IPI handler, which is in ISR context.
+		 * Disable IRQ to prevent a clobbered queue.
+		 */
+		ipi_disable_irq();
+		size = queue_remove_unit(&event_venc_queue, &rsv_msg);
+		ipi_enable_irq();
+
+		if (!size)
+			task_wait_event(-1);
+		else if (mtk_venc_msg_handle[rsv_msg.type])
+			mtk_venc_msg_handle[rsv_msg.type](rsv_msg.msg);
+		else
+			CPRINTS("venc handler %d not exists.", rsv_msg.type);
+	}
+}
diff --git a/baseboard/mtscp-rv32i/venc.h b/baseboard/mtscp-rv32i/venc.h
new file mode 100644
index 0000000000..c5c7df3883
--- /dev/null
+++ b/baseboard/mtscp-rv32i/venc.h
@@ -0,0 +1,26 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_SCP_VENC_H
+#define __CROS_EC_SCP_VENC_H
+
+#include "compile_time_macros.h"
+
+enum venc_type {
+	VENC_H264,
+	VENC_MAX,
+};
+
+struct venc_msg {
+	enum venc_type type;
+	unsigned char msg[288];
+};
+BUILD_ASSERT(member_size(struct venc_msg, msg) <=
+	     CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
+
+/* Functions provided by private overlay. */
+void venc_h264_msg_handler(void *data);
+
+#endif /* __CROS_EC_SCP_VENC_H */
diff --git a/baseboard/nucleo-f412zg/base-board.c b/baseboard/nucleo-f412zg/base-board.c
index 15e46f006e..53c42e5a26 100644
--- a/baseboard/nucleo-f412zg/base-board.c
+++ b/baseboard/nucleo-f412zg/base-board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/baseboard/nucleo-f412zg/base-board.h b/baseboard/nucleo-f412zg/base-board.h
index 7b69fde7c5..18e88df48c 100644
--- a/baseboard/nucleo-f412zg/base-board.h
+++ b/baseboard/nucleo-f412zg/base-board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -50,28 +50,28 @@
 
 #define CONFIG_FLASH_WRITE_SIZE STM32_FLASH_WRITE_SIZE_3300
 
-#define CONFIG_SHAREDLIB_SIZE   0
+#define CONFIG_SHAREDLIB_SIZE 0
 
-#define CONFIG_RO_MEM_OFF       0
-#define CONFIG_RO_STORAGE_OFF   0
-#define CONFIG_RO_SIZE          (128 * 1024)
+#define CONFIG_RO_MEM_OFF 0
+#define CONFIG_RO_STORAGE_OFF 0
+#define CONFIG_RO_SIZE (128 * 1024)
 
 /* EC rollback protection block */
 #define CONFIG_ROLLBACK_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
 #define CONFIG_ROLLBACK_SIZE (128 * 1024 * 2) /* 2 blocks of 128KB each */
 
-#define CONFIG_RW_MEM_OFF	(CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE)
-#define CONFIG_RW_STORAGE_OFF	0
-#define CONFIG_RW_SIZE		(CONFIG_FLASH_SIZE -			\
-				(CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF))
+#define CONFIG_RW_MEM_OFF (CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE)
+#define CONFIG_RW_STORAGE_OFF 0
+#define CONFIG_RW_SIZE \
+	(CONFIG_FLASH_SIZE_BYTES - (CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF))
 
-#define CONFIG_EC_PROTECTED_STORAGE_OFF         CONFIG_RO_MEM_OFF
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE        CONFIG_RO_SIZE
-#define CONFIG_EC_WRITABLE_STORAGE_OFF          CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE         CONFIG_RW_SIZE
+#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF
+#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE
+#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE
 
-#define CONFIG_WP_STORAGE_OFF           CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE          CONFIG_EC_PROTECTED_STORAGE_SIZE
+#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
+#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
 
 /*
  * We want to prevent flash readout, and use it as indicator of protection
@@ -116,7 +116,7 @@
  */
 #undef CONFIG_ROLLBACK_SECRET_LOCAL_ENTROPY_SIZE
 #ifdef SECTION_IS_RW
-	#undef CONFIG_ROLLBACK_UPDATE
+#undef CONFIG_ROLLBACK_UPDATE
 #endif
 
 /*-------------------------------------------------------------------------*
@@ -124,9 +124,9 @@
  *-------------------------------------------------------------------------*/
 
 #ifdef SECTION_IS_RO
-	/* RO verifies the RW partition signature */
-	#define CONFIG_RSA
-	#define CONFIG_RWSIG
+/* RO verifies the RW partition signature */
+#define CONFIG_RSA
+#define CONFIG_RWSIG
 #endif /* SECTION_IS_RO */
 #define CONFIG_RSA_KEY_SIZE 3072
 #define CONFIG_RSA_EXPONENT_3
@@ -157,44 +157,40 @@
  * Other
  *-------------------------------------------------------------------------*/
 
-#define CONFIG_AES
-#define CONFIG_AES_GCM
-#define CONFIG_DMA
+#define CONFIG_BORINGSSL_CRYPTO
+#define CONFIG_DMA_CROS
 #define CONFIG_FPU
 #define CONFIG_HOST_COMMAND_STATUS
 #define CONFIG_MKBP_EVENT
 #define CONFIG_MKBP_USE_GPIO
-#define CONFIG_PRINTF_LEGACY_LI_FORMAT
+#define CONFIG_PRINTF_LONG_IS_32BITS
 #define CONFIG_RNG
 #define CONFIG_SHA256
 #define CONFIG_SHA256_UNROLLED
-#define CONFIG_STM_HWTIMER32
-#define CONFIG_SUPPRESSED_HOST_COMMANDS \
-	EC_CMD_CONSOLE_SNAPSHOT, EC_CMD_CONSOLE_READ, EC_CMD_PD_GET_LOG_ENTRY
 #define CONFIG_WP_ACTIVE_HIGH
 
 #ifndef TEST_BUILD
-	/* TODO(hesling): Fix the illogical dependency between spi.c
-	 *                and host_command.c
-	 *
-	 * Currently, the chip/stm32/spi.c depends on functions defined in
-	 * common/host_command.c. When unit test builds use their own tasklist
-	 * without the HOSTCMD task, host_command.c is excluded from the build,
-	 * but chip/stm32/spi.c remains (because of CONFIG_SPI).
-	 * This triggers an undefined reference linker error.
-	 * The reproduce case:
-	 * - Allow CONFIG_SPI in TEST_BUILDs
-	 * - make BOARD=nucleo-h743zi tests
-	 */
-	#define CONFIG_SPI
+/* TODO(hesling): Fix the illogical dependency between spi.c
+ *                and host_command.c
+ *
+ * Currently, the chip/stm32/spi.c depends on functions defined in
+ * common/host_command.c. When unit test builds use their own tasklist
+ * without the HOSTCMD task, host_command.c is excluded from the build,
+ * but chip/stm32/spi.c remains (because of CONFIG_SPI).
+ * This triggers an undefined reference linker error.
+ * The reproduce case:
+ * - Allow CONFIG_SPI in TEST_BUILDs
+ * - make BOARD=nucleo-h743zi tests
+ */
+#define CONFIG_SPI
 #endif
 
 #ifndef __ASSEMBLER__
-	/* Timer selection */
-	#define TIM_CLOCK32 2
-	#define TIM_WATCHDOG 16
-	#include "gpio_signal.h"
-	void button_event(enum gpio_signal signal);
+/* Timer selection */
+#define TIM_CLOCK32 2
+#define TIM_WATCHDOG 16
+#include "gpio_signal.h"
+void button_event(enum gpio_signal signal);
 #endif /* !__ASSEMBLER__ */
 
 #endif /* __CROS_EC_BASE_BOARD_H */
diff --git a/baseboard/nucleo-f412zg/base-gpio.inc b/baseboard/nucleo-f412zg/base-gpio.inc
index 4ebd99f91f..d0c48a46e5 100644
--- a/baseboard/nucleo-f412zg/base-gpio.inc
+++ b/baseboard/nucleo-f412zg/base-gpio.inc
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/baseboard/nucleo-f412zg/build.mk b/baseboard/nucleo-f412zg/build.mk
index 1456331fec..d38a618d8c 100644
--- a/baseboard/nucleo-f412zg/build.mk
+++ b/baseboard/nucleo-f412zg/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/baseboard/nucleo-f412zg/openocd-flash.cfg b/baseboard/nucleo-f412zg/openocd-flash.cfg
index 3333d1163a..cbc9fe0218 100644
--- a/baseboard/nucleo-f412zg/openocd-flash.cfg
+++ b/baseboard/nucleo-f412zg/openocd-flash.cfg
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/baseboard/nucleo-f412zg/openocd.cfg b/baseboard/nucleo-f412zg/openocd.cfg
index 589d4400f4..3b286a4ebc 100644
--- a/baseboard/nucleo-f412zg/openocd.cfg
+++ b/baseboard/nucleo-f412zg/openocd.cfg
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/baseboard/nucleo-h743zi/base-board.c b/baseboard/nucleo-h743zi/base-board.c
index 15e46f006e..53c42e5a26 100644
--- a/baseboard/nucleo-h743zi/base-board.c
+++ b/baseboard/nucleo-h743zi/base-board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/baseboard/nucleo-h743zi/base-board.h b/baseboard/nucleo-h743zi/base-board.h
index 0bf91efd83..936b2c6e1c 100644
--- a/baseboard/nucleo-h743zi/base-board.h
+++ b/baseboard/nucleo-h743zi/base-board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -53,24 +53,25 @@
  *
  * We need 2 independently erasable blocks, at a minimum.
  */
-#define CONFIG_ROLLBACK_SIZE   (2 * CONFIG_FLASH_BANK_SIZE)
-#define CONFIG_ROLLBACK_OFF    ((CONFIG_FLASH_SIZE / 2) - CONFIG_ROLLBACK_SIZE)
+#define CONFIG_ROLLBACK_SIZE (2 * CONFIG_FLASH_BANK_SIZE)
+#define CONFIG_ROLLBACK_OFF \
+	((CONFIG_FLASH_SIZE_BYTES / 2) - CONFIG_ROLLBACK_SIZE)
 
-#define CONFIG_RO_MEM_OFF      0
-#define CONFIG_RO_SIZE         CONFIG_ROLLBACK_OFF
-#define CONFIG_RW_MEM_OFF      (CONFIG_FLASH_SIZE / 2)
-#define CONFIG_RW_SIZE         (CONFIG_FLASH_SIZE / 2)
+#define CONFIG_RO_MEM_OFF 0
+#define CONFIG_RO_SIZE CONFIG_ROLLBACK_OFF
+#define CONFIG_RW_MEM_OFF (CONFIG_FLASH_SIZE_BYTES / 2)
+#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE_BYTES / 2)
 
-#define CONFIG_RO_STORAGE_OFF  0
-#define CONFIG_RW_STORAGE_OFF  0
+#define CONFIG_RO_STORAGE_OFF 0
+#define CONFIG_RW_STORAGE_OFF 0
 
-#define CONFIG_EC_PROTECTED_STORAGE_OFF   CONFIG_RO_MEM_OFF
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE  CONFIG_RO_SIZE
-#define CONFIG_EC_WRITABLE_STORAGE_OFF    CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE   CONFIG_RW_SIZE
+#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF
+#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE
+#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE
 
-#define CONFIG_WP_STORAGE_OFF             CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE            CONFIG_EC_PROTECTED_STORAGE_SIZE
+#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
+#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
 
 /* Disabled features */
 
@@ -82,42 +83,38 @@
 
 /* Enabled features */
 
-#define CONFIG_AES
-#define CONFIG_AES_GCM
-#define CONFIG_DMA
+#define CONFIG_BORINGSSL_CRYPTO
+#define CONFIG_DMA_CROS
 #define CONFIG_FORCE_CONSOLE_RESUME
 #define CONFIG_FPU
 #define CONFIG_HOST_COMMAND_STATUS
 #define CONFIG_LOW_POWER_IDLE
 #define CONFIG_MKBP_EVENT
 #define CONFIG_MKBP_USE_GPIO
-#define CONFIG_PRINTF_LEGACY_LI_FORMAT
+#define CONFIG_PRINTF_LONG_IS_32BITS
 #define CONFIG_RNG
 #define CONFIG_RWSIG_TYPE_RWSIG
 #define CONFIG_SHA256
 #define CONFIG_SHA256_UNROLLED
 #undef CONFIG_SHAREDLIB_SIZE
-#define CONFIG_SHAREDLIB_SIZE   0
-#define CONFIG_STM_HWTIMER32
-#define CONFIG_SUPPRESSED_HOST_COMMANDS \
-	EC_CMD_CONSOLE_SNAPSHOT, EC_CMD_CONSOLE_READ, EC_CMD_PD_GET_LOG_ENTRY
+#define CONFIG_SHAREDLIB_SIZE 0
 #define CONFIG_WATCHDOG_HELP
 #define CONFIG_WP_ACTIVE_HIGH
 
 #ifndef TEST_BUILD
-	/* TODO(hesling): Fix the illogical dependency between spi.c
-	 *                and host_command.c
-	 *
-	 * Currently, the chip/stm32/spi.c depends on functions defined in
-	 * common/host_command.c. When unit test builds use their own tasklist
-	 * without the HOSTCMD task, host_command.c is excluded from the build,
-	 * but chip/stm32/spi.c remains (because of CONFIG_SPI).
-	 * This triggers an undefined reference linker error.
-	 * The reproduce case:
-	 * - Allow CONFIG_SPI in TEST_BUILDs
-	 * - make BOARD=nucleo-h743zi tests
-	 */
-#	define CONFIG_SPI
+/* TODO(hesling): Fix the illogical dependency between spi.c
+ *                and host_command.c
+ *
+ * Currently, the chip/stm32/spi.c depends on functions defined in
+ * common/host_command.c. When unit test builds use their own tasklist
+ * without the HOSTCMD task, host_command.c is excluded from the build,
+ * but chip/stm32/spi.c remains (because of CONFIG_SPI).
+ * This triggers an undefined reference linker error.
+ * The reproduce case:
+ * - Allow CONFIG_SPI in TEST_BUILDs
+ * - make BOARD=nucleo-h743zi tests
+ */
+#define CONFIG_SPI
 #endif
 
 /*
@@ -147,10 +144,10 @@
 #define CONFIG_CMD_IDLE_STATS
 
 #ifdef SECTION_IS_RO
-	/* RO verifies the RW partition signature */
-#	define CONFIG_RSA
-#	define CONFIG_RWSIG
-#endif  /* SECTION_IS_RO */
+/* RO verifies the RW partition signature */
+#define CONFIG_RSA
+#define CONFIG_RWSIG
+#endif /* SECTION_IS_RO */
 
 #define CONFIG_RSA_KEY_SIZE 3072
 #define CONFIG_RSA_EXPONENT_3
@@ -161,7 +158,7 @@
  */
 #undef CONFIG_ROLLBACK_SECRET_LOCAL_ENTROPY_SIZE
 #ifdef SECTION_IS_RW
-#	undef CONFIG_ROLLBACK_UPDATE
+#undef CONFIG_ROLLBACK_UPDATE
 #endif
 /*
  * Add rollback protection
@@ -170,11 +167,11 @@
 #define CONFIG_ROLLBACK_MPU_PROTECT
 
 #ifndef __ASSEMBLER__
-	/* Timer selection */
-#	define TIM_CLOCK32 2
-#	define TIM_WATCHDOG 16
-#	include "gpio_signal.h"
-	void button_event(enum gpio_signal signal);
+/* Timer selection */
+#define TIM_CLOCK32 2
+#define TIM_WATCHDOG 16
+#include "gpio_signal.h"
+void button_event(enum gpio_signal signal);
 #endif /* !__ASSEMBLER__ */
 
 #endif /* __CROS_EC_BASE_BOARD_H */
diff --git a/baseboard/nucleo-h743zi/base-ec.tasklist b/baseboard/nucleo-h743zi/base-ec.tasklist
index fae8952113..e8e752aa4e 100644
--- a/baseboard/nucleo-h743zi/base-ec.tasklist
+++ b/baseboard/nucleo-h743zi/base-ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/baseboard/nucleo-h743zi/base-gpio.inc b/baseboard/nucleo-h743zi/base-gpio.inc
index ef224cbaf1..ad7d313328 100644
--- a/baseboard/nucleo-h743zi/base-gpio.inc
+++ b/baseboard/nucleo-h743zi/base-gpio.inc
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/baseboard/nucleo-h743zi/build.mk b/baseboard/nucleo-h743zi/build.mk
index e9f9ae3faa..36c0cfdf50 100644
--- a/baseboard/nucleo-h743zi/build.mk
+++ b/baseboard/nucleo-h743zi/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -11,4 +11,4 @@ CHIP:=stm32
 CHIP_FAMILY:=stm32h7
 CHIP_VARIANT:=stm32h7x3
 
-baseboard-y=base-board.o
\ No newline at end of file
+baseboard-y=base-board.o
diff --git a/baseboard/nucleo-h743zi/openocd-flash.cfg b/baseboard/nucleo-h743zi/openocd-flash.cfg
index 4517266d7b..8ee5dd6707 100644
--- a/baseboard/nucleo-h743zi/openocd-flash.cfg
+++ b/baseboard/nucleo-h743zi/openocd-flash.cfg
@@ -1,4 +1,4 @@
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/baseboard/nucleo-h743zi/openocd.cfg b/baseboard/nucleo-h743zi/openocd.cfg
index 528e8d6cab..9fa8aa89a9 100644
--- a/baseboard/nucleo-h743zi/openocd.cfg
+++ b/baseboard/nucleo-h743zi/openocd.cfg
@@ -1,4 +1,4 @@
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/baseboard/octopus/baseboard.c b/baseboard/octopus/baseboard.c
index 105a3bf71c..164e28b480 100644
--- a/baseboard/octopus/baseboard.c
+++ b/baseboard/octopus/baseboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,12 +27,12 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /******************************************************************************/
 /* Keyboard scan setting */
-struct keyboard_scan_config keyscan_config = {
+__override struct keyboard_scan_config keyscan_config = {
 	/*
 	 * F3 key scan cycle completed but scan input is not
 	 * charging to logic high when EC start scan next
@@ -218,9 +218,9 @@ int board_is_i2c_port_powered(int port)
 enum adc_channel board_get_vbus_adc(int port)
 {
 	if (port == 0)
-		return  ADC_VBUS_C0;
+		return ADC_VBUS_C0;
 	if (port == 1)
-		return  ADC_VBUS_C1;
+		return ADC_VBUS_C1;
 	CPRINTSUSB("Unknown vbus adc port id: %d", port);
 	return ADC_VBUS_C0;
 }
@@ -237,27 +237,27 @@ void baseboard_tcpc_init(void)
 	 * HPD pulse to enable video path
 	 */
 	for (int port = 0; port < board_get_usb_pd_port_count(); ++port)
-		usb_mux_hpd_update(port, 0, 0);
+		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
 /* Called after the cbi_init (via +2) */
 DECLARE_HOOK(HOOK_INIT, baseboard_tcpc_init, HOOK_PRIO_INIT_I2C + 2);
 
 int board_set_active_charge_port(int port)
 {
-	int is_valid_port = (port >= 0 &&
-			    port < board_get_usb_pd_port_count());
+	int is_valid_port = (port >= 0 && port < board_get_usb_pd_port_count());
 	int i;
 
 	if (!is_valid_port && port != CHARGE_PORT_NONE)
 		return EC_ERROR_INVAL;
 
-
 	if (port == CHARGE_PORT_NONE) {
 		CPRINTSUSB("Disabling all charger ports");
 
 		/* Disable all ports. */
-		for (i = 0; (i < ppc_cnt) &&
-		    (i < board_get_usb_pd_port_count()); i++) {
+		for (i = 0;
+		     (i < ppc_cnt) && (i < board_get_usb_pd_port_count());
+		     i++) {
 			/*
 			 * Do not return early if one fails otherwise we can
 			 * get into a boot loop assertion failure.
@@ -281,8 +281,7 @@ int board_set_active_charge_port(int port)
 	 * Turn off the other ports' sink path FETs, before enabling the
 	 * requested charge port.
 	 */
-	for (i = 0; (i < ppc_cnt) &&
-	    (i < board_get_usb_pd_port_count()); i++) {
+	for (i = 0; (i < ppc_cnt) && (i < board_get_usb_pd_port_count()); i++) {
 		if (i == port)
 			continue;
 
@@ -299,21 +298,6 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	/*
-	 * Empirically, the charger seems to draw a little more current that
-	 * it is set to, so we reduce our limit by 5%.
-	 */
-#ifdef VARIANT_OCTOPUS_CHARGER_ISL9238
-	charge_ma = (charge_ma * 95) / 100;
-#endif
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
-}
-
 void board_hibernate(void)
 {
 	int port;
@@ -379,5 +363,5 @@ void board_hibernate(void)
 	 * with any PD contract renegotiation, and tcpm to put TCPC into low
 	 * power mode if required.
 	 */
-	msleep(300);
+	msleep(1500);
 }
diff --git a/baseboard/octopus/baseboard.h b/baseboard/octopus/baseboard.h
index c8e4b24e56..cb09ca8e89 100644
--- a/baseboard/octopus/baseboard.h
+++ b/baseboard/octopus/baseboard.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,15 +12,13 @@
  * EC Config
  */
 
+#define CONFIG_LTO
+
 /*
  * By default, enable all console messages excepted HC, ACPI and event:
  * The sensor stack is generating a lot of activity.
  */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
-#define CONFIG_SUPPRESSED_HOST_COMMANDS \
-	EC_CMD_CONSOLE_SNAPSHOT, EC_CMD_CONSOLE_READ, EC_CMD_USB_PD_DISCOVERY,\
-	EC_CMD_USB_PD_POWER_INFO, EC_CMD_PD_GET_LOG_ENTRY, \
-	EC_CMD_MOTION_SENSE_CMD, EC_CMD_GET_NEXT_EVENT
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
 
 /*
  * Variant EC defines. Pick one:
@@ -28,65 +26,82 @@
  * VARIANT_OCTOPUS_EC_ITE8320
  */
 #if defined(VARIANT_OCTOPUS_EC_NPCX796FB)
-	/* NPCX7 config */
-	#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
-	#define NPCX_TACH_SEL2    0  /* [0:GPIO40/73, 1:GPIO93/A6] as TACH */
-	#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
-
-	/* Internal SPI flash on NPCX7 */
-	/* Flash is 1MB but reserve half for future use. */
-	#define CONFIG_FLASH_SIZE (512 * 1024)
-
-	#define CONFIG_SPI_FLASH_REGS
-	#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
-
-	/* I2C Bus Configuration */
-	#define I2C_PORT_BATTERY	NPCX_I2C_PORT0_0
-	#define I2C_PORT_TCPC0		NPCX_I2C_PORT1_0
-	#define I2C_PORT_TCPC1		NPCX_I2C_PORT2_0
-	#define I2C_PORT_EEPROM		NPCX_I2C_PORT3_0
-	#define I2C_PORT_CHARGER	NPCX_I2C_PORT4_1
-	#define I2C_PORT_SENSOR		NPCX_I2C_PORT7_0
-	#define I2C_ADDR_EEPROM_FLAGS	0x50
-
-	/* Enable PSL hibernate mode. */
-	#define CONFIG_HIBERNATE_PSL
-
-	/* EC variant determines USB-C variant */
-	#define VARIANT_OCTOPUS_USBC_STANDALONE_TCPCS
-
-	/* Allow the EC to enter deep sleep in S0 */
-	#define CONFIG_LOW_POWER_S0
+/* NPCX7 config */
+#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */
+#define NPCX_TACH_SEL2 0 /* [0:GPIO40/73, 1:GPIO93/A6] as TACH */
+#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */
+
+/* Internal SPI flash on NPCX7 */
+/* Flash is 1MB but reserve half for future use. */
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
+
+#define CONFIG_SPI_FLASH_REGS
+#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
+
+/* I2C Bus Configuration */
+#define I2C_PORT_BATTERY NPCX_I2C_PORT0_0
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT1_0
+#define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT3_0
+#define I2C_PORT_CHARGER NPCX_I2C_PORT4_1
+#define I2C_PORT_SENSOR NPCX_I2C_PORT7_0
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+
+/* Enable PSL hibernate mode. */
+#define CONFIG_HIBERNATE_PSL
+
+/* EC variant determines USB-C variant */
+#define VARIANT_OCTOPUS_USBC_STANDALONE_TCPCS
+
+/* Allow the EC to enter deep sleep in S0 */
+#define CONFIG_LOW_POWER_S0
+
+/*
+ * Increase period to prevent false positive hangs (b/255368431).
+ * TODO(b/281584278): Reevaluate period when more data is available.
+ */
+#undef CONFIG_WATCHDOG_PERIOD_MS
+#define CONFIG_WATCHDOG_PERIOD_MS 2100
+
 #elif defined(VARIANT_OCTOPUS_EC_ITE8320)
-	/* I2C Bus Configuration */
-	#define I2C_PORT_BATTERY	IT83XX_I2C_CH_A	/* Shared bus */
-	#define I2C_PORT_CHARGER	IT83XX_I2C_CH_A	/* Shared bus */
-	#define I2C_PORT_SENSOR		IT83XX_I2C_CH_B
-	#define I2C_PORT_USBC0		IT83XX_I2C_CH_C
-	#define I2C_PORT_USBC1		IT83XX_I2C_CH_E
-	#define I2C_PORT_USB_MUX	I2C_PORT_USBC0	/* For MUX driver */
-	#define I2C_PORT_EEPROM		IT83XX_I2C_CH_F
-	#define I2C_ADDR_EEPROM_FLAGS	0x50
-	#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 2
-
-	/* EC variant determines USB-C variant */
-	#define VARIANT_OCTOPUS_USBC_ITE_EC_TCPCS
+/* IT83XX config */
+#define CONFIG_IT83XX_VCC_1P8V
+/* I2C Bus Configuration */
+#define I2C_PORT_BATTERY IT83XX_I2C_CH_A /* Shared bus */
+#define I2C_PORT_CHARGER IT83XX_I2C_CH_A /* Shared bus */
+#define I2C_PORT_SENSOR IT83XX_I2C_CH_B
+#define I2C_PORT_USBC0 IT83XX_I2C_CH_C
+#define I2C_PORT_USBC1 IT83XX_I2C_CH_E
+#define I2C_PORT_USB_MUX I2C_PORT_USBC0 /* For MUX driver */
+#define I2C_PORT_EEPROM IT83XX_I2C_CH_F
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 2
+
+/* EC variant determines USB-C variant */
+#define VARIANT_OCTOPUS_USBC_ITE_EC_TCPCS
+
+/*
+ * Limit maximal ODR to 125Hz, the EC is using ~5ms per sample at
+ * 48MHz core cpu clock.
+ */
+#define CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ 125000
 #else
-	#error Must define a VARIANT_OCTOPUS_EC
+#error Must define a VARIANT_OCTOPUS_EC
 #endif /* VARIANT_OCTOPUS_EC */
 
 /* Common EC defines */
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_CONTROLLER
 #define CONFIG_I2C_BUS_MAY_BE_UNPOWERED
 #define CONFIG_VBOOT_HASH
 #define CONFIG_VSTORE
 #define CONFIG_VSTORE_SLOT_COUNT 1
 #define CONFIG_CRC8
-#define CONFIG_CROS_BOARD_INFO
+#define CONFIG_CBI_EEPROM
 #define CONFIG_BOARD_VERSION_CBI
 #define CONFIG_LOW_POWER_IDLE
 #define CONFIG_DPTF
+#define CONFIG_DO_NOT_INCLUDE_RV32I_PANIC_DATA
 #define CONFIG_BOARD_HAS_RTC_RESET
 #define CONFIG_LED_ONOFF_STATES
 #define CONFIG_CMD_CHARGEN
@@ -110,39 +125,55 @@
  * VARIANT_OCTOPUS_CHARGER_BQ25703
  */
 #if defined(VARIANT_OCTOPUS_CHARGER_ISL9238)
-	#define CONFIG_CHARGER_ISL9238
-	#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20
-	/*
-	 * ISL923x driver sets "Adapter insertion to Switching Debounce"
-	 * CONTROL2 REG 0x3DH <Bit 11> to 1 which is 150 ms
-	 */
-	#undef	CONFIG_EXTPOWER_DEBOUNCE_MS
-	#define	CONFIG_EXTPOWER_DEBOUNCE_MS 200
+#define CONFIG_CHARGER_ISL9238
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20
+/*
+ * ISL923x driver sets "Adapter insertion to Switching Debounce"
+ * CONTROL2 REG 0x3DH <Bit 11> to 1 which is 150 ms
+ */
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
+#define CONFIG_EXTPOWER_DEBOUNCE_MS 200
+/* Charger seems to overdraw by about 5% */
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 5
 #elif defined(VARIANT_OCTOPUS_CHARGER_BQ25703)
-	#define CONFIG_CHARGER_BQ25703
-	#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
-	/*
-	 * From BQ25703: CHRG_OK is HIGH after 50ms deglitch time.
-	 */
-	#undef	CONFIG_EXTPOWER_DEBOUNCE_MS
-	#define	CONFIG_EXTPOWER_DEBOUNCE_MS 50
+#define CONFIG_CHARGER_BQ25703
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+/*
+ * From BQ25703: CHRG_OK is HIGH after 50ms deglitch time.
+ */
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
+#define CONFIG_EXTPOWER_DEBOUNCE_MS 50
+/* Charger seems to overdraw by about 5% */
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 5
+#elif defined(CONFIG_CHARGER_RUNTIME_CONFIG)
+#define CONFIG_CHARGER_ISL9238
+#define CONFIG_CHARGER_BQ25710
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC_ISL9238 20
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10
+
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
+#define CONFIG_EXTPOWER_DEBOUNCE_MS 200
 #else
-	#error Must define a VARIANT_OCTOPUS_CHARGER
+#error Must define a VARIANT_OCTOPUS_CHARGER
 #endif /* VARIANT_OCTOPUS_CHARGER */
 
 /* Common charger defines */
 #define CONFIG_CHARGE_MANAGER
 #define CONFIG_CHARGE_RAMP_HW
 #define CONFIG_CHARGER
-#define CONFIG_CHARGER_INPUT_CURRENT 512 /* Allow low-current USB charging */
-#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 1
+/* Allow low-current USB charging */
+#define CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT 512
+#define CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT 512
 #define CONFIG_CHARGER_SENSE_RESISTOR 10
 #define CONFIG_CHARGER_DISCHARGE_ON_AC
 #define CONFIG_USB_CHARGER
 
 /* Common battery defines */
 #define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY  "LION"
+#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
 #define CONFIG_BATTERY_FUEL_GAUGE
 #define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_L
 #define CONFIG_BATTERY_REVIVE_DISCONNECT
@@ -153,43 +184,45 @@
  * Automatically defined by VARIANT_OCTOPUS_EC_ variant.
  */
 
- /*
-  * Variant USBC defines. Pick one:
-  * VARIANT_OCTOPUS_USBC_STANDALONE_TCPCS
-  * VARIANT_OCTOPUS_USBC_ITE_EC_TCPCS (requires)
-  */
+/*
+ * Variant USBC defines. Pick one:
+ * VARIANT_OCTOPUS_USBC_STANDALONE_TCPCS
+ * VARIANT_OCTOPUS_USBC_ITE_EC_TCPCS (requires)
+ */
 #if defined(VARIANT_OCTOPUS_USBC_STANDALONE_TCPCS)
-	#define CONFIG_USB_PD_TCPC_LOW_POWER
-	#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+#define CONFIG_USB_PD_TCPC_LOW_POWER
+#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
 #if !defined(VARIANT_OCTOPUS_TCPC_0_PS8751)
-	#define CONFIG_USB_PD_TCPM_ANX7447	/* C0 TCPC: ANX7447QN */
+#define CONFIG_USB_PD_TCPM_ANX7447 /* C0 TCPC: ANX7447QN */
 #endif
-	#define CONFIG_USB_PD_TCPM_PS8751	/* C1 TCPC: PS8751 */
-	#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-	#define CONFIG_USBC_PPC_NX20P3483
+#define CONFIG_USB_PD_TCPM_PS8751 /* C1 TCPC: PS8751 */
+#define CONFIG_USB_PD_VBUS_DETECT_TCPC
+#define CONFIG_USBC_PPC_NX20P3483
 #elif defined(VARIANT_OCTOPUS_USBC_ITE_EC_TCPCS)
-	#undef CONFIG_USB_PD_TCPC_LOW_POWER
-	#undef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-	#define CONFIG_USB_PD_VBUS_DETECT_PPC
-	#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP	/* C0 & C1 TCPC: ITE EC */
-	#define CONFIG_USB_MUX_IT5205		/* C0 MUX: IT5205 */
-	#define CONFIG_USB_PD_TCPM_PS8751	/* C1 Mux: PS8751 */
-	#define CONFIG_USBC_PPC_SN5S330		/* C0 & C1 PPC: each SN5S330 */
-	#define CONFIG_USBC_PPC_VCONN
-	#define CONFIG_USBC_PPC_DEDICATED_INT
+#undef CONFIG_USB_PD_TCPC_LOW_POWER
+#undef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+#define CONFIG_USB_PD_VBUS_DETECT_PPC
+#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0 & C1 TCPC: ITE EC */
+#define CONFIG_USB_MUX_IT5205 /* C0 MUX: IT5205 */
+#define CONFIG_USB_PD_TCPM_PS8751 /* C1 Mux: PS8751 */
+#define CONFIG_USB_PD_TCPM_PS8751_CUSTOM_MUX_DRIVER
+#define CONFIG_USBC_PPC_SN5S330 /* C0 & C1 PPC: each SN5S330 */
+#define CONFIG_USBC_PPC_VCONN
+#define CONFIG_USBC_PPC_DEDICATED_INT
 #else
-	#error Must define a VARIANT_OCTOPUS_USBC
+#error Must define a VARIANT_OCTOPUS_USBC
 #endif /* VARIANT_OCTOPUS_USBC */
 
 /* Common USB-C defines */
-#define USB_PD_PORT_TCPC_0	0
-#define USB_PD_PORT_TCPC_1	1
+#define USB_PD_PORT_TCPC_0 0
+#define USB_PD_PORT_TCPC_1 1
 #define CONFIG_USB_PID 0x5046
 
 #define CONFIG_USB_DRP_ACC_TRYSRC
 #define CONFIG_USB_PD_DECODE_SOP
 #define CONFIG_USB_POWER_DELIVERY
 #define CONFIG_USB_PD_TCPMV2
+#define CONFIG_USB_PD_3A_PORTS 0
 #define CONFIG_USB_PD_PORT_MAX_COUNT 2
 #define CONFIG_USB_PD_DUAL_ROLE
 #define CONFIG_USB_PD_LOGGING
@@ -205,19 +238,20 @@
 #define CONFIG_USB_PD_TCPM_MUX
 #define CONFIG_USB_PD_TCPM_TCPCI
 #define CONFIG_BC12_DETECT_MAX14637
+#undef CONFIG_BC12_MAX14637_DELAY_FROM_OFF_TO_ON_MS
+#define CONFIG_BC12_MAX14637_DELAY_FROM_OFF_TO_ON_MS 100
 #define CONFIG_HOSTCMD_PD_CONTROL
 #define CONFIG_CMD_PPC_DUMP
 
 /* TODO(b/76218141): Use correct PD delay values */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000	/* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	250000	/* us */
-#define PD_VCONN_SWAP_DELAY		5000	/* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* TODO(b/76218141): Use correct PD power values */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		45000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 45000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /*******************************************************************************
  * USB-A Configs
@@ -236,10 +270,10 @@
  * SoC / PCH Config
  */
 
- /* Common SoC / PCH defines */
+/* Common SoC / PCH defines */
 #define CONFIG_CHIPSET_GEMINILAKE
 #define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 /* TODO(b/74123961): Enable Virtual Wires after bringup */
 #define CONFIG_POWER_COMMON
 #define CONFIG_POWER_S0IX
@@ -255,11 +289,11 @@
 
 /* Common Keyboard Defines */
 #define CONFIG_CMD_KEYBOARD
-#define CONFIG_KEYBOARD_BOARD_CONFIG
+
 #define CONFIG_KEYBOARD_PROTOCOL_8042
 #define CONFIG_KEYBOARD_COL2_INVERTED
 #define CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2
-#undef  CONFIG_KEYBOARD_VIVALDI
+#undef CONFIG_KEYBOARD_VIVALDI
 
 /*******************************************************************************
  * Sensor Config
@@ -268,11 +302,10 @@
 /* Common Sensor Defines */
 #define CONFIG_TABLET_MODE
 #define CONFIG_GMR_TABLET_MODE
-#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L
 /*
  * Slew rate on the PP1800_SENSOR load switch requires a short delay on startup.
  */
-#undef  CONFIG_MOTION_SENSE_RESUME_DELAY_US
+#undef CONFIG_MOTION_SENSE_RESUME_DELAY_US
 #define CONFIG_MOTION_SENSE_RESUME_DELAY_US (10 * MSEC)
 
 #ifndef VARIANT_OCTOPUS_NO_SENSORS
@@ -280,7 +313,6 @@
  * Interrupt and fifo are only used for base accelerometer
  * and the lid sensor is polled real-time (in forced mode).
  */
-#define CONFIG_ACCEL_INTERRUPTS
 /* Enable sensor fifo, must also define the _SIZE and _THRES */
 #define CONFIG_ACCEL_FIFO
 /* Power of 2 - Too large of a fifo causes too much timestamp jitter */
@@ -289,6 +321,9 @@
 #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
 #endif /* VARIANT_OCTOPUS_NO_SENSORS */
 
+/* System safe mode for improved panic debugging */
+#define CONFIG_SYSTEM_SAFE_MODE
+
 /*
  * Sensor stack in EC/Kernel depends on a hardware interrupt pin from EC->AP, so
  * do not define CONFIG_MKBP_USE_HOST_EVENT since all octopus boards use
@@ -297,6 +332,14 @@
 #define CONFIG_MKBP_EVENT
 #define CONFIG_MKBP_USE_GPIO
 
+/* Free up more flash. */
+#undef CONFIG_CMD_ACCELSPOOF
+#undef CONFIG_CMD_MFALLOW
+#undef CONFIG_CMD_MD
+#undef CONFIG_CMD_MMAPINFO
+#undef CONFIG_CONSOLE_CMDHELP
+#undef CONFIG_CONSOLE_HISTORY
+
 #ifndef __ASSEMBLER__
 
 #include "gpio_signal.h"
diff --git a/baseboard/octopus/build.mk b/baseboard/octopus/build.mk
index bb8a6f8267..696f60d42e 100644
--- a/baseboard/octopus/build.mk
+++ b/baseboard/octopus/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/baseboard/octopus/cbi_ssfc.c b/baseboard/octopus/cbi_ssfc.c
index 1fa45f7338..827d2e045e 100644
--- a/baseboard/octopus/cbi_ssfc.c
+++ b/baseboard/octopus/cbi_ssfc.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -37,3 +37,13 @@ enum ssfc_ppc_p1 get_cbi_ssfc_ppc_p1(void)
 {
 	return ((cached_ssfc & SSFC_PPC_P1_MASK) >> SSFC_PPC_P1_OFFSET);
 }
+
+enum ssfc_charger get_cbi_ssfc_charger(void)
+{
+	return ((cached_ssfc & SSFC_CHARGER_MASK) >> SSFC_CHARGER_OFFSET);
+}
+
+enum ssfc_sensor get_cbi_ssfc_sensor(void)
+{
+	return ((cached_ssfc & SSFC_SENSOR_MASK) >> SSFC_SENSOR_OFFSET);
+}
diff --git a/baseboard/octopus/cbi_ssfc.h b/baseboard/octopus/cbi_ssfc.h
index 07ed4c958d..570c240da1 100644
--- a/baseboard/octopus/cbi_ssfc.h
+++ b/baseboard/octopus/cbi_ssfc.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,8 +18,8 @@ enum ssfc_tcpc_p1 {
 	SSFC_TCPC_P1_PS8751,
 	SSFC_TCPC_P1_PS8755,
 };
-#define SSFC_TCPC_P1_OFFSET		0
-#define SSFC_TCPC_P1_MASK		GENMASK(2, 0)
+#define SSFC_TCPC_P1_OFFSET 0
+#define SSFC_TCPC_P1_MASK GENMASK(2, 0)
 
 /*
  * PPC Port 1 (Bits 3-5)
@@ -29,10 +29,39 @@ enum ssfc_ppc_p1 {
 	SSFC_PPC_P1_NX20P348X,
 	SSFC_PPC_P1_SYV682X,
 };
-#define SSFC_PPC_P1_OFFSET		3
-#define SSFC_PPC_P1_MASK		GENMASK(5, 3)
+#define SSFC_PPC_P1_OFFSET 3
+#define SSFC_PPC_P1_MASK GENMASK(5, 3)
+
+/*
+ * Charger (Bits 8-6)
+ */
+enum ssfc_charger {
+	SSFC_CHARGER_DEFAULT,
+	SSFC_CHARGER_ISL9238,
+	SSFC_CHARGER_BQ25710,
+};
+#define SSFC_CHARGER_OFFSET 6
+#define SSFC_CHARGER_MASK GENMASK(8, 6)
+
+/*
+ * Audio (Bits 11-9)
+ */
+
+/*
+ * Sensor (Bits 14-12)
+ */
+enum ssfc_sensor {
+	SSFC_SENSOR_DEFAULT,
+	SSFC_SENSOR_BMI160,
+	SSFC_SENSOR_ICM426XX,
+	SSFC_SENSOR_BMI260,
+};
+#define SSFC_SENSOR_OFFSET 12
+#define SSFC_SENSOR_MASK GENMASK(14, 12)
 
 enum ssfc_tcpc_p1 get_cbi_ssfc_tcpc_p1(void);
 enum ssfc_ppc_p1 get_cbi_ssfc_ppc_p1(void);
+enum ssfc_charger get_cbi_ssfc_charger(void);
+enum ssfc_sensor get_cbi_ssfc_sensor(void);
 
 #endif /* _OCTOPUS_CBI_SSFC__H_ */
diff --git a/baseboard/octopus/usb_pd_policy.c b/baseboard/octopus/usb_pd_policy.c
index dcd7b41ee1..c8b8b96d3a 100644
--- a/baseboard/octopus/usb_pd_policy.c
+++ b/baseboard/octopus/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,8 +17,8 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
@@ -39,11 +39,6 @@ void pd_power_supply_reset(int port)
 	if (prev_en)
 		pd_set_vbus_discharge(port, 1);
 
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	/* Give back the current quota we are no longer using */
-	charge_manager_source_port(port, 0);
-#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
-
 	/* Notify host of power info change. */
 	pd_send_host_event(PD_EVENT_POWER_CHANGE);
 }
@@ -64,11 +59,6 @@ int pd_set_power_supply_ready(int port)
 	if (rv)
 		return rv;
 
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	/* Ensure we advertise the proper available current quota */
-	charge_manager_source_port(port, 1);
-#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
-
 	/* Notify host of power info change. */
 	pd_send_host_event(PD_EVENT_POWER_CHANGE);
 
diff --git a/baseboard/octopus/variant_ec_ite8320.c b/baseboard/octopus/variant_ec_ite8320.c
index 459ea113b3..e79f4cdb01 100644
--- a/baseboard/octopus/variant_ec_ite8320.c
+++ b/baseboard/octopus/variant_ec_ite8320.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -28,10 +28,30 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 /******************************************************************************/
 /* I2C port map configuration */
 const struct i2c_port_t i2c_ports[] = {
-	{"power",  IT83XX_I2C_CH_A, 100, GPIO_I2C0_SCL, GPIO_I2C0_SDA},
-	{"sensor", IT83XX_I2C_CH_B, 100, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"usbc0",  IT83XX_I2C_CH_C, 400, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-	{"usbc1",  IT83XX_I2C_CH_E, 400, GPIO_I2C4_SCL, GPIO_I2C4_SDA},
-	{"eeprom", IT83XX_I2C_CH_F, 100, GPIO_I2C5_SCL, GPIO_I2C5_SDA},
+	{ .name = "power",
+	  .port = IT83XX_I2C_CH_A,
+	  .kbps = 100,
+	  .scl = GPIO_I2C0_SCL,
+	  .sda = GPIO_I2C0_SDA },
+	{ .name = "sensor",
+	  .port = IT83XX_I2C_CH_B,
+	  .kbps = 100,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "usbc0",
+	  .port = IT83XX_I2C_CH_C,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "usbc1",
+	  .port = IT83XX_I2C_CH_E,
+	  .kbps = 400,
+	  .scl = GPIO_I2C4_SCL,
+	  .sda = GPIO_I2C4_SDA },
+	{ .name = "eeprom",
+	  .port = IT83XX_I2C_CH_F,
+	  .kbps = 100,
+	  .scl = GPIO_I2C5_SCL,
+	  .sda = GPIO_I2C5_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/baseboard/octopus/variant_ec_npcx796fb.c b/baseboard/octopus/variant_ec_npcx796fb.c
index bccb360563..23a4f58bae 100644
--- a/baseboard/octopus/variant_ec_npcx796fb.c
+++ b/baseboard/octopus/variant_ec_npcx796fb.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -31,13 +31,37 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 /******************************************************************************/
 /* I2C port map configuration */
 const struct i2c_port_t i2c_ports[] = {
-	{"battery", I2C_PORT_BATTERY, 100, GPIO_I2C0_SCL, GPIO_I2C0_SDA},
-	{"tcpc0",   I2C_PORT_TCPC0,   400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"tcpc1",   I2C_PORT_TCPC1,   400, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-	{"eeprom",  I2C_PORT_EEPROM,  100, GPIO_I2C3_SCL, GPIO_I2C3_SDA},
-	{"charger", I2C_PORT_CHARGER, 100, GPIO_I2C4_SCL, GPIO_I2C4_SDA},
+	{ .name = "battery",
+	  .port = I2C_PORT_BATTERY,
+	  .kbps = 100,
+	  .scl = GPIO_I2C0_SCL,
+	  .sda = GPIO_I2C0_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "tcpc1",
+	  .port = I2C_PORT_TCPC1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 100,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
+	{ .name = "charger",
+	  .port = I2C_PORT_CHARGER,
+	  .kbps = 100,
+	  .scl = GPIO_I2C4_SCL,
+	  .sda = GPIO_I2C4_SDA },
 #ifndef VARIANT_OCTOPUS_NO_SENSORS
-	{"sensor",  I2C_PORT_SENSOR,  100, GPIO_I2C7_SCL, GPIO_I2C7_SDA},
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 100,
+	  .scl = GPIO_I2C7_SCL,
+	  .sda = GPIO_I2C7_SDA },
 #endif
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
@@ -46,8 +70,9 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 /******************************************************************************/
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = { .channel = 3, .flags = PWM_CONFIG_DSLEEP,
-								.freq = 100 },
+	[PWM_CH_KBLIGHT] = { .channel = 3,
+			     .flags = PWM_CONFIG_DSLEEP,
+			     .freq = 100 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 #endif
diff --git a/baseboard/octopus/variant_usbc_ec_tcpcs.c b/baseboard/octopus/variant_usbc_ec_tcpcs.c
index 2635850bd8..a93dfe3535 100644
--- a/baseboard/octopus/variant_usbc_ec_tcpcs.c
+++ b/baseboard/octopus/variant_usbc_ec_tcpcs.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,20 +10,20 @@
 #include "console.h"
 #include "driver/ppc/sn5s330.h"
 #include "driver/tcpm/it83xx_pd.h"
-#include "driver/usb_mux/it5205.h"
 #include "driver/tcpm/ps8xxx.h"
 #include "driver/tcpm/tcpci.h"
 #include "driver/tcpm/tcpm.h"
+#include "driver/usb_mux/it5205.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "system.h"
-#include "tcpci.h"
+#include "tcpm/tcpci.h"
 #include "usb_mux.h"
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define USB_PD_PORT_ITE_0	0
-#define USB_PD_PORT_ITE_1	1
+#define USB_PD_PORT_ITE_0 0
+#define USB_PD_PORT_ITE_1 1
 
 /******************************************************************************/
 /* USB-C TPCP Configuration */
@@ -49,10 +49,15 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 
 /* TODO(crbug.com/826441): Consolidate this logic with other impls */
 static void board_it83xx_hpd_status(const struct usb_mux *me,
-				    int hpd_lvl, int hpd_irq)
+				    mux_state_t mux_state, bool *ack_required)
 {
-	enum gpio_signal gpio = me->usb_port ?
-		GPIO_USB_C1_HPD_1V8_ODL : GPIO_USB_C0_HPD_1V8_ODL;
+	int hpd_lvl = (mux_state & USB_PD_MUX_HPD_LVL) ? 1 : 0;
+	int hpd_irq = (mux_state & USB_PD_MUX_HPD_IRQ) ? 1 : 0;
+	enum gpio_signal gpio = me->usb_port ? GPIO_USB_C1_HPD_1V8_ODL :
+					       GPIO_USB_C0_HPD_1V8_ODL;
+
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
 
 	/* Invert HPD level since GPIOs are active low. */
 	hpd_lvl = !hpd_lvl;
@@ -66,38 +71,38 @@ static void board_it83xx_hpd_status(const struct usb_mux *me,
 }
 
 /* This configuration might be override by each boards */
-struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_ITE_0] = {
-		.usb_port = USB_PD_PORT_ITE_0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_it83xx_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_ITE_0,
+			.i2c_port = I2C_PORT_USB_MUX,
+			.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+			.driver = &it5205_usb_mux_driver,
+			.hpd_update = &board_it83xx_hpd_status,
+		},
 	},
 	[USB_PD_PORT_ITE_1] = {
-		.usb_port = USB_PD_PORT_ITE_1,
-		/* Use PS8751 as mux only */
-		.i2c_port = I2C_PORT_USBC1,
-		.i2c_addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		.flags = USB_MUX_FLAG_NOT_TCPC,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_ITE_1,
+			/* Use PS8751 as mux only */
+			.i2c_port = I2C_PORT_USBC1,
+			.i2c_addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+			.flags = USB_MUX_FLAG_NOT_TCPC,
+			.driver = &ps8xxx_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 	}
 };
 
 /******************************************************************************/
 /* USB-C PPC Configuration */
 struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_ITE_0] = {
-		.i2c_port = I2C_PORT_USBC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	[USB_PD_PORT_ITE_1] = {
-		.i2c_port = I2C_PORT_USBC1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
+	[USB_PD_PORT_ITE_0] = { .i2c_port = I2C_PORT_USBC0,
+				.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+				.drv = &sn5s330_drv },
+	[USB_PD_PORT_ITE_1] = { .i2c_port = I2C_PORT_USBC1,
+				.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+				.drv = &sn5s330_drv },
 };
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
@@ -152,6 +157,6 @@ void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
 	 * correctly in the PPC driver via the pd state machine.
 	 */
 	if (ppc_set_vconn(port, enabled) != EC_SUCCESS)
-		cprints(CC_USBPD, "C%d: Failed %sabling vconn",
-			port, enabled ? "en" : "dis");
+		cprints(CC_USBPD, "C%d: Failed %sabling vconn", port,
+			enabled ? "en" : "dis");
 }
diff --git a/baseboard/octopus/variant_usbc_standalone_tcpcs.c b/baseboard/octopus/variant_usbc_standalone_tcpcs.c
index e383c486c0..abc325dfa3 100644
--- a/baseboard/octopus/variant_usbc_standalone_tcpcs.c
+++ b/baseboard/octopus/variant_usbc_standalone_tcpcs.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,13 +16,13 @@
 #include "gpio.h"
 #include "hooks.h"
 #include "system.h"
-#include "tcpci.h"
+#include "tcpm/tcpci.h"
 #include "usb_mux.h"
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
 
 /******************************************************************************/
 /* USB-C TPCP Configuration */
@@ -32,7 +32,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = I2C_PORT_TCPC0,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
 		},
 		.drv = &ps8xxx_tcpm_drv,
 #else
@@ -48,7 +48,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = I2C_PORT_TCPC1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
 		},
 		.drv = &ps8xxx_tcpm_drv,
 	},
@@ -66,22 +66,26 @@ static int ps8751_tune_mux(const struct usb_mux *me)
 }
 #endif
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_TCPC_0] = {
-		.usb_port = USB_PD_PORT_TCPC_0,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_0,
 #if defined(VARIANT_OCTOPUS_TCPC_0_PS8751)
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-		.board_init = &ps8751_tune_mux,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			.board_init = &ps8751_tune_mux,
 #else
-		.driver = &anx7447_usb_mux_driver,
-		.hpd_update = &anx7447_tcpc_update_hpd_status,
+			.driver = &anx7447_usb_mux_driver,
+			.hpd_update = &anx7447_tcpc_update_hpd_status,
 #endif
+		},
 	},
 	[USB_PD_PORT_TCPC_1] = {
-		.usb_port = USB_PD_PORT_TCPC_1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 	}
 };
 
diff --git a/baseboard/trogdor/baseboard.c b/baseboard/trogdor/baseboard.c
index ecc8dc59f7..3f3c778ea5 100644
--- a/baseboard/trogdor/baseboard.c
+++ b/baseboard/trogdor/baseboard.c
@@ -1,66 +1,25 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Trogdor baseboard-specific configuration */
 
-#include "charger.h"
-#include "driver/charger/isl923x.h"
 #include "i2c.h"
-#include "power.h"
 
 /* Wake-up pins for hibernate */
-const enum gpio_signal hibernate_wake_pins[] = {
+enum gpio_signal hibernate_wake_pins[] = {
 	GPIO_LID_OPEN,
 	GPIO_AC_PRESENT,
 	GPIO_POWER_BUTTON_L,
 	GPIO_EC_RST_ODL,
 };
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
+int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
+BUILD_ASSERT(ARRAY_SIZE(hibernate_wake_pins) >= 3);
 
-/* Power signal list. Must match order of enum power_signal. */
-const struct power_signal_info power_signal_list[] = {
-	[SC7180_AP_RST_ASSERTED] = {
-		GPIO_AP_RST_L,
-		POWER_SIGNAL_ACTIVE_LOW | POWER_SIGNAL_DISABLE_AT_BOOT,
-		"AP_RST_ASSERTED"},
-	[SC7180_PS_HOLD] = {
-		GPIO_PS_HOLD,
-		POWER_SIGNAL_ACTIVE_HIGH,
-		"PS_HOLD"},
-	[SC7180_PMIC_FAULT_L] = {
-		GPIO_PMIC_FAULT_L,
-		POWER_SIGNAL_ACTIVE_HIGH | POWER_SIGNAL_DISABLE_AT_BOOT,
-		"PMIC_FAULT_L"},
-	[SC7180_POWER_GOOD] = {
-		GPIO_POWER_GOOD,
-		POWER_SIGNAL_ACTIVE_HIGH,
-		"POWER_GOOD"},
-	[SC7180_WARM_RESET] = {
-		GPIO_WARM_RESET_L,
-		POWER_SIGNAL_ACTIVE_HIGH,
-		"WARM_RESET_L"},
-	[SC7180_AP_SUSPEND] = {
-		GPIO_AP_SUSPEND,
-		POWER_SIGNAL_ACTIVE_HIGH,
-		"AP_SUSPEND"},
-	[SC7180_DEPRECATED_AP_RST_REQ] = {
-		GPIO_DEPRECATED_AP_RST_REQ,
-		POWER_SIGNAL_ACTIVE_HIGH,
-		"DEPRECATED_AP_RST_REQ"},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-int board_allow_i2c_passthru(int port)
+int board_allow_i2c_passthru(const struct i2c_cmd_desc_t *cmd_desc)
 {
-	return (port == I2C_PORT_VIRTUAL_BATTERY);
+	return (cmd_desc->port == I2C_PORT_VIRTUAL_BATTERY ||
+		cmd_desc->port == I2C_PORT_TCPC0 ||
+		cmd_desc->port == I2C_PORT_TCPC1);
 }
diff --git a/baseboard/trogdor/baseboard.h b/baseboard/trogdor/baseboard.h
index 20b990b258..37d56a4cec 100644
--- a/baseboard/trogdor/baseboard.h
+++ b/baseboard/trogdor/baseboard.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,17 +8,30 @@
 #ifndef __CROS_EC_BASEBOARD_H
 #define __CROS_EC_BASEBOARD_H
 
+#define CONFIG_LTO
+
+/* Free flash space */
+#undef CONFIG_CONSOLE_CMDHELP
+#undef CONFIG_CONSOLE_HISTORY
+#undef CONFIG_CMD_BATTFAKE
+#undef CONFIG_CMD_I2C_SCAN
+#undef CONFIG_CMD_MFALLOW
+#undef CONFIG_CMD_MD
+#undef CONFIG_CMD_RTC
+#undef CONFIG_CMD_TCPC_DUMP
+#undef CONFIG_CMD_TYPEC
+
 /*
  * By default, enable all console messages excepted event and HC:
  * The sensor stack is generating a lot of activity.
  * They can be enabled through the console command 'chan'.
  */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_HOSTCMD)))
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_HOSTCMD)))
 
 /* NPCX7 config */
-#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
-#define NPCX_TACH_SEL2    0  /* No tach. */
-#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
+#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */
+#define NPCX_TACH_SEL2 0 /* No tach. */
+#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */
 
 /* Internal SPI flash on NPCX7 */
 #define CONFIG_SPI_FLASH_REGS
@@ -26,7 +39,7 @@
 
 /* EC Modules */
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_CONTROLLER
 #define CONFIG_I2C_VIRTUAL_BATTERY
 #define CONFIG_I2C_PASSTHRU_RESTRICTED
 #define CONFIG_LED_COMMON
@@ -41,11 +54,9 @@
 
 #undef CONFIG_PECI
 
-#define CONFIG_HOSTCMD_SPS
+#define CONFIG_HOST_INTERFACE_SHI
 #define CONFIG_HOST_COMMAND_STATUS
 #define CONFIG_HOSTCMD_SECTION_SORTED
-#define CONFIG_MKBP_EVENT
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
 #define CONFIG_KEYBOARD_COL2_INVERTED
 #define CONFIG_MKBP_USE_GPIO
 
@@ -58,6 +69,8 @@
 #define CONFIG_LID_SWITCH
 #define CONFIG_EXTPOWER_GPIO
 
+#define CONFIG_HIBERNATE_WAKE_PINS_DYNAMIC
+
 /*
  * On power-on, H1 releases the EC from reset but then quickly asserts and
  * releases the reset a second time. This means the EC sees 2 resets:
@@ -66,15 +79,23 @@
  */
 #define CONFIG_BOARD_RESET_AFTER_POWER_ON
 
+/* Increase console output buffer since we have the RAM available. */
+#undef CONFIG_UART_TX_BUF_SIZE
+#define CONFIG_UART_TX_BUF_SIZE 4096
+
 /* Battery */
 #define CONFIG_BATTERY_CUT_OFF
 #define CONFIG_BATTERY_PRESENT_GPIO GPIO_BATT_PRES_ODL
 #define CONFIG_BATTERY_SMART
+#define CONFIG_BATTERY_V2
+#define CONFIG_BATTERY_COUNT 1
+#define CONFIG_HOSTCMD_BATTERY_V2
 
 /* Charger */
 #define CONFIG_CHARGER
 #define CONFIG_CHARGE_MANAGER
 #define CONFIG_CHARGER_ISL9238
+#define CONFIG_CHARGER_PROFILE_OVERRIDE
 #define CONFIG_CHARGE_RAMP_HW
 #define CONFIG_USB_CHARGER
 #define CONFIG_CMD_CHARGER_ADC_AMON_BMON
@@ -82,8 +103,8 @@
 #define CONFIG_CHARGER_PSYS_READ
 #define CONFIG_CHARGER_DISCHARGE_ON_AC
 
-#define CONFIG_CHARGER_INPUT_CURRENT 512
-#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 2
+#define CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT 512
+#define CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT 512
 #define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 10000
 #define CONFIG_CHARGER_SENSE_RESISTOR 10
 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 20
@@ -109,7 +130,6 @@
 #define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
 #define CONFIG_USB_PD_TCPC_LOW_POWER
 #define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT TYPEC_RP_3A0
 #define CONFIG_USB_PD_TCPM_MUX
 #define CONFIG_USB_PD_TCPM_TCPCI
 #define CONFIG_CMD_TCPC_DUMP
@@ -117,6 +137,7 @@
 #define CONFIG_USB_PD_VBUS_DETECT_TCPC
 #define CONFIG_USB_PD_5V_EN_CUSTOM
 #define CONFIG_USBC_SS_MUX
+#define CONFIG_USBC_SS_MUX_DFP_ONLY
 #define CONFIG_USBC_VCONN
 #define CONFIG_USBC_VCONN_SWAP
 
@@ -135,14 +156,13 @@
 #define CONFIG_CMD_ACCEL_INFO
 
 /* PD */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY   30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY  250000 /* us */
-#define PD_VCONN_SWAP_DELAY             5000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
-#define PD_OPERATING_POWER_MW   10000
-#define PD_MAX_POWER_MW         ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
-#define PD_MAX_CURRENT_MA       3000
-#define PD_MAX_VOLTAGE_MV       20000
+#define PD_OPERATING_POWER_MW 10000
+#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Chipset */
 #define CONFIG_CHIPSET_SC7180
@@ -152,9 +172,7 @@
 #define CONFIG_POWER_PP5000_CONTROL
 #define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
 #define CONFIG_POWER_SLEEP_FAILURE_DETECTION
-
-/* NPCX Features */
-#define CONFIG_HIBERNATE_PSL
+#define CONFIG_CMD_AP_RESET_LOG
 
 /*
  * Macros for GPIO signals used in common code that don't match the
@@ -162,61 +180,54 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_POWER_BUTTON_L	GPIO_EC_PWR_BTN_ODL
-#define GPIO_VOLUME_DOWN_L	GPIO_EC_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L	GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_LID_OPEN		GPIO_LID_OPEN_EC
-#define GPIO_SHI_CS_L		GPIO_AP_EC_SPI_CS_L
-#define GPIO_ENTERING_RW	GPIO_EC_ENTERING_RW
-#define GPIO_BATT_PRES_ODL	GPIO_EC_BATT_PRES_ODL
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
-#define GPIO_ENABLE_BACKLIGHT	GPIO_EC_BL_DISABLE_L
-#define GPIO_BOARD_VERSION1	GPIO_BRD_ID0
-#define GPIO_BOARD_VERSION2	GPIO_BRD_ID1
-#define GPIO_BOARD_VERSION3	GPIO_BRD_ID2
-#define GPIO_KBD_KSO2		GPIO_EC_KSO_02_INV
+#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_LID_OPEN GPIO_LID_OPEN_EC
+#define GPIO_SHI_CS_L GPIO_AP_EC_SPI_CS_L
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_BATT_PRES_ODL GPIO_EC_BATT_PRES_ODL
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
+#define GPIO_ENABLE_BACKLIGHT GPIO_EC_BL_DISABLE_L
+#define GPIO_BOARD_VERSION1 GPIO_BRD_ID0
+#define GPIO_BOARD_VERSION2 GPIO_BRD_ID1
+#define GPIO_BOARD_VERSION3 GPIO_BRD_ID2
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
 
 /* I2C Ports */
 #define I2C_PORT_BATTERY I2C_PORT_POWER
 #define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
 #define I2C_PORT_CHARGER I2C_PORT_POWER
-#define I2C_PORT_ACCEL   I2C_PORT_SENSOR
-#define I2C_PORT_POWER   NPCX_I2C_PORT0_0
-#define I2C_PORT_TCPC0   NPCX_I2C_PORT1_0
-#define I2C_PORT_TCPC1   NPCX_I2C_PORT2_0
-#define I2C_PORT_WLC     NPCX_I2C_PORT3_0
-#define I2C_PORT_EEPROM  NPCX_I2C_PORT5_0
-#define I2C_PORT_SENSOR  NPCX_I2C_PORT7_0
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
+#define I2C_PORT_POWER NPCX_I2C_PORT0_0
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT1_0
+#define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0
+#define I2C_PORT_WLC NPCX_I2C_PORT3_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT5_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT7_0
+
+/* UART */
+#define CONFIG_CMD_CHARGEN
 
 /* Define the host events which are allowed to wake AP up from S3 */
-#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \
-		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) | \
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) | \
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC) | \
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
+#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK                   \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |        \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |    \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |    \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT) |     \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC) |             \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |     \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_DEVICE))
 
 /* And the MKBP events */
+#ifdef HAS_TASK_KEYSCAN
+#define CONFIG_MKBP_EVENT_WAKEUP_MASK                                    \
+	(BIT(EC_MKBP_EVENT_KEY_MATRIX) | BIT(EC_MKBP_EVENT_HOST_EVENT) | \
+	 BIT(EC_MKBP_EVENT_SENSOR_FIFO))
+#else
 #define CONFIG_MKBP_EVENT_WAKEUP_MASK \
-		(BIT(EC_MKBP_EVENT_KEY_MATRIX) | \
-		 BIT(EC_MKBP_EVENT_HOST_EVENT) | \
-		 BIT(EC_MKBP_EVENT_SENSOR_FIFO))
-
-#ifndef __ASSEMBLER__
-
-enum power_signal {
-	SC7180_AP_RST_ASSERTED = 0,
-	SC7180_PS_HOLD,
-	SC7180_PMIC_FAULT_L,
-	SC7180_POWER_GOOD,
-	SC7180_WARM_RESET,
-	SC7180_AP_SUSPEND,
-	SC7180_DEPRECATED_AP_RST_REQ,
-	/* Number of power signals */
-	POWER_SIGNAL_COUNT
-};
-
-#endif /* !defined(__ASSEMBLER__) */
+	(BIT(EC_MKBP_EVENT_HOST_EVENT) | BIT(EC_MKBP_EVENT_SENSOR_FIFO))
+#endif
 
 #endif /* __CROS_EC_BASEBOARD_H */
diff --git a/baseboard/trogdor/build.mk b/baseboard/trogdor/build.mk
index d882755a64..02ed466d2b 100644
--- a/baseboard/trogdor/build.mk
+++ b/baseboard/trogdor/build.mk
@@ -1,9 +1,12 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
 # Baseboard specific files build
 #
 
-baseboard-y=baseboard.o usb_pd_policy.o
+baseboard-y+=baseboard.o
+baseboard-y+=hibernate.o
+baseboard-y+=power.o
+baseboard-y+=usb_pd_policy.o
diff --git a/baseboard/trogdor/hibernate.c b/baseboard/trogdor/hibernate.c
new file mode 100644
index 0000000000..19af7cfe2e
--- /dev/null
+++ b/baseboard/trogdor/hibernate.c
@@ -0,0 +1,13 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "gpio.h"
+#include "system.h"
+
+void board_hibernate_late(void)
+{
+	/* Set the hibernate GPIO to turn off the rails */
+	gpio_set_level(GPIO_HIBERNATE_L, 0);
+}
diff --git a/baseboard/trogdor/power.c b/baseboard/trogdor/power.c
new file mode 100644
index 0000000000..a8076d0ed5
--- /dev/null
+++ b/baseboard/trogdor/power.c
@@ -0,0 +1,38 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "gpio.h"
+#include "hooks.h"
+#include "power.h"
+#include "task.h"
+
+void board_chipset_pre_init(void)
+{
+	/* Turn on the 3.3V rail */
+	gpio_set_level(GPIO_EN_PP3300_A, 1);
+
+	/* Turn on the 5V rail. */
+#ifdef CONFIG_POWER_PP5000_CONTROL
+	power_5v_enable(task_get_current(), 1);
+#else /* !defined(CONFIG_POWER_PP5000_CONTROL) */
+	gpio_set_level(GPIO_EN_PP5000, 1);
+#endif /* defined(CONFIG_POWER_PP5000_CONTROL) */
+}
+DECLARE_HOOK(HOOK_CHIPSET_PRE_INIT, board_chipset_pre_init, HOOK_PRIO_DEFAULT);
+
+void board_chipset_shutdown_complete(void)
+{
+	/* Turn off the 5V rail. */
+#ifdef CONFIG_POWER_PP5000_CONTROL
+	power_5v_enable(task_get_current(), 0);
+#else /* !defined(CONFIG_POWER_PP5000_CONTROL) */
+	gpio_set_level(GPIO_EN_PP5000, 0);
+#endif /* defined(CONFIG_POWER_PP5000_CONTROL) */
+
+	/* Turn off the 3.3V and 5V rails. */
+	gpio_set_level(GPIO_EN_PP3300_A, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN_COMPLETE, board_chipset_shutdown_complete,
+	     HOOK_PRIO_DEFAULT);
diff --git a/baseboard/trogdor/usb_pd_policy.c b/baseboard/trogdor/usb_pd_policy.c
index f66ea1f276..04a2e78519 100644
--- a/baseboard/trogdor/usb_pd_policy.c
+++ b/baseboard/trogdor/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,8 +12,8 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
@@ -23,10 +23,10 @@ int pd_check_vconn_swap(int port)
 
 static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT];
 #if CONFIG_USB_PD_PORT_MAX_COUNT == 1
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5};
+static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5 };
 #else
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5,
-							TYPEC_RP_1A5};
+static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5,
+							 TYPEC_RP_1A5 };
 #endif
 
 static void board_vbus_update_source_current(int port)
@@ -50,11 +50,6 @@ void pd_power_supply_reset(int port)
 	if (prev_en)
 		pd_set_vbus_discharge(port, 1);
 
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	/* Give back the current quota we are no longer using */
-	charge_manager_source_port(port, 0);
-#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
-
 	/* notify host of power info change */
 	pd_send_host_event(PD_EVENT_POWER_CHANGE);
 }
@@ -70,9 +65,6 @@ int pd_set_power_supply_ready(int port)
 	vbus_en[port] = 1;
 	board_vbus_update_source_current(port);
 
-	/* Ensure we advertise the proper available current quota */
-	charge_manager_source_port(port, 1);
-
 	/* notify host of power info change */
 	pd_send_host_event(PD_EVENT_POWER_CHANGE);
 
@@ -99,14 +91,14 @@ int pd_snk_is_vbus_provided(int port)
 #ifdef CONFIG_USB_PD_ALT_MODE_DFP
 __override int svdm_dp_config(int port, uint32_t *payload)
 {
-	int opos = pd_alt_mode(port, TCPC_TX_SOP, USB_SID_DISPLAYPORT);
+	int opos = pd_alt_mode(port, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT);
 	uint8_t pin_mode = get_dp_pin_mode(port);
 
 	if (!pin_mode)
 		return 0;
 
 	/*
-	 * Defer setting the usb_mux until HPD goes high, svdm_dp_attention().
+	 * Defer setting the DP mux until HPD goes high, svdm_dp_attention().
 	 * The AP only supports one DP phy. An external DP mux switches between
 	 * the two ports. Should switch those muxes when it is really used,
 	 * i.e. HPD high; otherwise, the real use case is preempted, like:
@@ -115,17 +107,45 @@ __override int svdm_dp_config(int port, uint32_t *payload)
 	 *  (3) plug a monitor to the port-1 dongle.
 	 */
 
-	payload[0] = VDO(USB_SID_DISPLAYPORT, 1,
-			 CMD_DP_CONFIG | VDO_OPOS(opos));
-	payload[1] = VDO_DP_CFG(pin_mode,      /* pin mode */
-				1,             /* DPv1.3 signaling */
-				2);            /* UFP connected */
+	payload[0] =
+		VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_CONFIG | VDO_OPOS(opos));
+	payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */
+				1, /* DPv1.3 signaling */
+				2); /* UFP connected */
 	return 2;
 };
 
 __override void svdm_dp_post_config(int port)
 {
+	/*
+	 * Connect the SBU lines in PPC chip such that the AUX termination
+	 * can be passed through.
+	 */
+	if (IS_ENABLED(CONFIG_USBC_PPC_SBU))
+		ppc_set_sbu(port, 1);
+
+	/*
+	 * Connect the USB SS/DP lines in TCPC chip.
+	 *
+	 * When mf_pref not true, still use the dock muxing
+	 * because of the board USB-C topology (limited to 2
+	 * lanes DP).
+	 */
+	usb_mux_set(port, USB_PD_MUX_DOCK, USB_SWITCH_CONNECT,
+		    polarity_rm_dts(pd_get_polarity(port)));
+
 	dp_flags[port] |= DP_FLAGS_DP_ON;
+	if (!(dp_flags[port] & DP_FLAGS_HPD_HI_PENDING))
+		return;
+
+	CPRINTS("C%d: Pending HPD. HPD->1", port);
+	gpio_set_level(GPIO_DP_HOT_PLUG_DET, 1);
+
+	/* set the minimum time delay (2ms) for the next HPD IRQ */
+	svdm_hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
+
+	usb_mux_hpd_update(port,
+			   USB_PD_MUX_HPD_LVL | USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
 
 /**
@@ -138,15 +158,13 @@ __override void svdm_dp_post_config(int port)
  */
 static int is_dp_muxable(int port)
 {
-	int i;
-
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
-		if (i != port) {
-			if (usb_mux_get(i) & USB_PD_MUX_DP_ENABLED)
-				return 0;
-		}
-
-	return 1;
+	/*
+	 * Check the DP port selection mux, positive either:
+	 *  - no port is muxed, OE_L deasserted, HIGH, or
+	 *  - already muxed to the same port.
+	 */
+	return gpio_get_level(GPIO_DP_MUX_OE_L) ||
+	       (gpio_get_level(GPIO_DP_MUX_SEL) == port);
 }
 
 __override int svdm_dp_attention(int port, uint32_t *payload)
@@ -155,9 +173,16 @@ __override int svdm_dp_attention(int port, uint32_t *payload)
 	int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]);
 	int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]);
 	int cur_lvl = gpio_get_level(hpd);
+	mux_state_t mux_state;
 
 	dp_status[port] = payload[1];
 
+	if (!is_dp_muxable(port)) {
+		/* TODO(waihong): Info user? */
+		CPRINTS("p%d: The other port is already muxed.", port);
+		return 0;
+	}
+
 	/*
 	 * Initial implementation to handle HPD. Only the first-plugged port
 	 * works, i.e. sending HPD signal to AP. The second-plugged port
@@ -167,58 +192,39 @@ __override int svdm_dp_attention(int port, uint32_t *payload)
 	 * is then unplugged, switch to the second-plugged port and signal AP?
 	 */
 	if (lvl) {
-		if (is_dp_muxable(port)) {
-			/*
-			 * Enable and switch the DP port selection mux to the
-			 * correct port.
-			 *
-			 * TODO(waihong): Better to move switching DP mux to
-			 * the usb_mux abstraction.
-			 */
-			gpio_set_level(GPIO_DP_MUX_SEL, port == 1);
-			gpio_set_level(GPIO_DP_MUX_OE_L, 0);
-
-			/* Connect the SBU lines in PPC chip. */
-			if (IS_ENABLED(CONFIG_USBC_PPC_SBU))
-				ppc_set_sbu(port, 1);
-
-			/*
-			 * Connect the USB SS/DP lines in TCPC chip.
-			 *
-			 * When mf_pref not true, still use the dock muxing
-			 * because of the board USB-C topology (limited to 2
-			 * lanes DP).
-			 */
-			usb_mux_set(port, USB_PD_MUX_DOCK,
-				    USB_SWITCH_CONNECT, pd_get_polarity(port));
-		} else {
-			/* TODO(waihong): Info user? */
-			CPRINTS("p%d: The other port is already muxed.", port);
-			return 0;  /* Nack */
-		}
+		/*
+		 * Enable and switch the DP port selection mux to the
+		 * correct port.
+		 *
+		 * TODO(waihong): Better to move switching DP mux to
+		 * the usb_mux abstraction.
+		 */
+		gpio_set_level(GPIO_DP_MUX_SEL, port == 1);
+		gpio_set_level(GPIO_DP_MUX_OE_L, 0);
 	} else {
 		/* Disconnect the DP port selection mux. */
 		gpio_set_level(GPIO_DP_MUX_OE_L, 1);
-
-		/* Disconnect the SBU lines in PPC chip. */
-		if (IS_ENABLED(CONFIG_USBC_PPC_SBU))
-			ppc_set_sbu(port, 0);
-
-		/* Disconnect the DP but keep the USB SS lines in TCPC chip. */
-		usb_mux_set(port, USB_PD_MUX_USB_ENABLED,
-			    USB_SWITCH_CONNECT, pd_get_polarity(port));
+		gpio_set_level(GPIO_DP_MUX_SEL, 0);
 	}
 
-	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
-	    (irq || lvl))
+	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && (irq || lvl))
 		/*
 		 * Wake up the AP.  IRQ or level high indicates a DP sink is now
 		 * present.
 		 */
-		pd_notify_dp_alt_mode_entry();
+		pd_notify_dp_alt_mode_entry(port);
+
+	/* Its initial DP status message prior to config */
+	if (!(dp_flags[port] & DP_FLAGS_DP_ON)) {
+		if (lvl)
+			dp_flags[port] |= DP_FLAGS_HPD_HI_PENDING;
+		return 1;
+	}
 
 	/* Configure TCPC for the HPD event, for proper muxing */
-	usb_mux_hpd_update(port, lvl, irq);
+	mux_state = (lvl ? USB_PD_MUX_HPD_LVL : USB_PD_MUX_HPD_LVL_DEASSERTED) |
+		    (irq ? USB_PD_MUX_HPD_IRQ : USB_PD_MUX_HPD_IRQ_DEASSERTED);
+	usb_mux_hpd_update(port, mux_state);
 
 	/* Signal AP for the HPD event, through GPIO to AP */
 	if (irq & cur_lvl) {
@@ -228,36 +234,44 @@ __override int svdm_dp_attention(int port, uint32_t *payload)
 			usleep(svdm_hpd_deadline[port] - now);
 
 		/* Generate IRQ_HPD pulse */
+		CPRINTS("C%d: Recv IRQ. HPD->0", port);
 		gpio_set_level(hpd, 0);
 		usleep(HPD_DSTREAM_DEBOUNCE_IRQ);
 		gpio_set_level(hpd, 1);
+		CPRINTS("C%d: Recv IRQ. HPD->1", port);
 
 		/* Set the minimum time delay (2ms) for the next HPD IRQ */
-		svdm_hpd_deadline[port] = get_time().val +
-			HPD_USTREAM_DEBOUNCE_LVL;
+		svdm_hpd_deadline[port] =
+			get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
 	} else if (irq & !lvl) {
 		CPRINTF("ERR:HPD:IRQ&LOW\n");
-		return 0;  /* Nak */
+		return 0;
 	} else {
+		CPRINTS("C%d: Recv lvl. HPD->%d", port, lvl);
 		gpio_set_level(hpd, lvl);
 		/* Set the minimum time delay (2ms) for the next HPD IRQ */
-		svdm_hpd_deadline[port] = get_time().val +
-			HPD_USTREAM_DEBOUNCE_LVL;
+		svdm_hpd_deadline[port] =
+			get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
 	}
 
-	return 1;  /* Ack */
+	return 1;
 }
 
 __override void svdm_exit_dp_mode(int port)
 {
-	/* Disconnect the DP port selection mux. */
-	gpio_set_level(GPIO_DP_MUX_OE_L, 1);
-
-	/* Below svdm_safe_dp_mode() will disconnect SBU and DP/USB SS lines. */
-	svdm_safe_dp_mode(port);
+	CPRINTS("%s(%d)", __func__, port);
+	dp_flags[port] = 0;
+	dp_status[port] = 0;
+	if (is_dp_muxable(port)) {
+		/* Disconnect the DP port selection mux. */
+		gpio_set_level(GPIO_DP_MUX_OE_L, 1);
+		gpio_set_level(GPIO_DP_MUX_SEL, 0);
 
-	/* Signal AP for the HPD low event */
-	usb_mux_hpd_update(port, 0, 0);
-	gpio_set_level(GPIO_DP_HOT_PLUG_DET, 0);
+		/* Signal AP for the HPD low event */
+		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+		CPRINTS("C%d: DP exit. HPD->0", port);
+		gpio_set_level(GPIO_DP_HOT_PLUG_DET, 0);
+	}
 }
 #endif /* CONFIG_USB_PD_ALT_MODE_DFP */
diff --git a/baseboard/volteer/baseboard.c b/baseboard/volteer/baseboard.c
index f42bcba930..b9f10fd360 100644
--- a/baseboard/volteer/baseboard.c
+++ b/baseboard/volteer/baseboard.c
@@ -1,35 +1,30 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Volteer family-specific configuration */
-#include "adc_chip.h"
+#include "adc.h"
 #include "button.h"
 #include "cbi_ec_fw_config.h"
-#include "charge_manager.h"
 #include "charge_ramp.h"
-#include "charge_state.h"
+#include "charger.h"
 #include "cros_board_info.h"
 #include "driver/charger/isl9241.h"
 #include "driver/tcpm/ps8xxx.h"
 #include "driver/temp_sensor/thermistor.h"
 #include "gpio.h"
-#include "hooks.h"
 #include "i2c.h"
-#include "icelake.h"
 #include "keyboard_scan.h"
 #include "system.h"
 #include "task.h"
 #include "temp_sensor.h"
-#include "usbc_ppc.h"
-#include "util.h"
+#ifdef CONFIG_ZEPHYR
+#include "usbc_config.h"
+#endif
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ## args)
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ##args)
 
 /******************************************************************************/
 /* ADC configuration */
@@ -75,252 +70,24 @@ const enum gpio_signal hibernate_wake_pins[] = {
 };
 const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 
-/******************************************************************************/
-/* Charger Chip Configuration */
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = ISL9241_ADDR_FLAGS,
-		.drv = &isl9241_drv,
-	},
-};
-
-/******************************************************************************/
-/*
- * PWROK signal configuration, see the PWROK Generation Flow Diagram (Figure
- * 235) in the Tiger Lake Platform Design Guide for the list of potential
- * signals.
- *
- * Volteer uses this power sequence:
- *	GPIO_EN_PPVAR_VCCIN - Turns on the VCCIN rail. Also used as a delay to
- *		the VCCST_PWRGD input to the AP so this signal must be delayed
- *		5 ms to meet the tCPU00 timing requirement.
- *	GPIO_EC_PCH_SYS_PWROK - Asserts the SYS_PWROK input to the AP. Delayed
- *		a total of 50 ms after ALL_SYS_PWRGD input is asserted. See
- *		b/144478941 for full discussion.
- *
- * Volteer does not provide direct EC control for the VCCST_PWRGD and PCH_PWROK
- * signals. If your board adds these signals to the EC, copy this array
- * to your board.c file and modify as needed.
- */
-const struct intel_x86_pwrok_signal pwrok_signal_assert_list[] = {
-	{
-		.gpio = GPIO_EN_PPVAR_VCCIN,
-		.delay_ms = 5,
-	},
-	{
-		.gpio = GPIO_EC_PCH_SYS_PWROK,
-		.delay_ms = 50 - 5,
-	},
-};
-const int pwrok_signal_assert_count = ARRAY_SIZE(pwrok_signal_assert_list);
-
-const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[] = {
-	/* No delays needed during S0 exit */
-	{
-		.gpio = GPIO_EC_PCH_SYS_PWROK,
-	},
-	/* Turn off VCCIN last */
-	{
-		.gpio = GPIO_EN_PPVAR_VCCIN,
-	},
-};
-const int pwrok_signal_deassert_count = ARRAY_SIZE(pwrok_signal_deassert_list);
-
 /******************************************************************************/
 /* Temperature sensor configuration */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_1_CHARGER},
-	[TEMP_SENSOR_2_PP3300_REGULATOR] = {.name = "PP3300 Regulator",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_2_PP3300_REGULATOR},
-	[TEMP_SENSOR_3_DDR_SOC] = {.name = "DDR and SOC",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_3_DDR_SOC},
-	[TEMP_SENSOR_4_FAN] = {.name = "Fan",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_4_FAN},
+	[TEMP_SENSOR_1_CHARGER] = { .name = "Charger",
+				    .type = TEMP_SENSOR_TYPE_BOARD,
+				    .read = get_temp_3v3_30k9_47k_4050b,
+				    .idx = ADC_TEMP_SENSOR_1_CHARGER },
+	[TEMP_SENSOR_2_PP3300_REGULATOR] = { .name = "PP3300 Regulator",
+					     .type = TEMP_SENSOR_TYPE_BOARD,
+					     .read = get_temp_3v3_30k9_47k_4050b,
+					     .idx = ADC_TEMP_SENSOR_2_PP3300_REGULATOR },
+	[TEMP_SENSOR_3_DDR_SOC] = { .name = "DDR and SOC",
+				    .type = TEMP_SENSOR_TYPE_BOARD,
+				    .read = get_temp_3v3_30k9_47k_4050b,
+				    .idx = ADC_TEMP_SENSOR_3_DDR_SOC },
+	[TEMP_SENSOR_4_FAN] = { .name = "Fan",
+				.type = TEMP_SENSOR_TYPE_BOARD,
+				.read = get_temp_3v3_30k9_47k_4050b,
+				.idx = ADC_TEMP_SENSOR_4_FAN },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/******************************************************************************/
-void tcpc_alert_event(enum gpio_signal signal)
-{
-	/* TODO: b/140572591 - check correct operation for Volteer */
-
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_TCPC_INT_ODL:
-		port = USBC_PORT_C0;
-		break;
-	case GPIO_USB_C1_TCPC_INT_ODL:
-		port = USBC_PORT_C1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-void bc12_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
-		break;
-
-	case GPIO_USB_C1_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12, 0);
-		break;
-
-	default:
-		break;
-	}
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_valid_port = (port >= 0 &&
-			     port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	int i;
-
-	if (port == CHARGE_PORT_NONE) {
-		CPRINTSUSB("Disabling all charger ports");
-
-		/* Disable all ports. */
-		for (i = 0; i < ppc_cnt; i++) {
-			/*
-			 * Do not return early if one fails otherwise we can
-			 * get into a boot loop assertion failure.
-			 */
-			if (ppc_vbus_sink_enable(i, 0))
-				CPRINTSUSB("Disabling C%d as sink failed.", i);
-		}
-
-		return EC_SUCCESS;
-	} else if (!is_valid_port) {
-		return EC_ERROR_INVAL;
-	}
-
-
-	/* Check if the port is sourcing VBUS. */
-	if (ppc_is_sourcing_vbus(port)) {
-		CPRINTFUSB("Skip enable C%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	CPRINTSUSB("New charge port: C%d", port);
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < ppc_cnt; i++) {
-		if (i == port)
-			continue;
-
-		if (ppc_vbus_sink_enable(i, 0))
-			CPRINTSUSB("C%d: sink path disable failed.", i);
-	}
-
-	/* Enable requested charge port. */
-	if (ppc_vbus_sink_enable(port, 1)) {
-		CPRINTSUSB("C%d: sink path enable failed.", port);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-__overridable void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_set_input_current_limit(MAX(charge_ma,
-					CONFIG_CHARGER_INPUT_CURRENT),
-					charge_mv);
-}
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* Note that the level is inverted because the pin is active low. */
-	switch (port) {
-	case USBC_PORT_C0:
-		gpio_set_level(GPIO_USB_C0_OC_ODL, !is_overcurrented);
-		break;
-	case USBC_PORT_C1:
-		gpio_set_level(GPIO_USB_C1_OC_ODL, !is_overcurrented);
-		break;
-	}
-}
-
-static void baseboard_init(void)
-{
-	/* Enable monitoring of the PROCHOT input to the EC */
-	gpio_enable_interrupt(GPIO_EC_PROCHOT_IN_L);
-}
-DECLARE_HOOK(HOOK_INIT, baseboard_init, HOOK_PRIO_DEFAULT);
-
-static uint8_t board_id;
-
-uint8_t get_board_id(void)
-{
-	return board_id;
-}
-
-__overridable void board_cbi_init(void)
-{
-}
-
-/*
- * Read CBI from i2c eeprom and initialize variables for board variants
- *
- * Example for configuring for a USB3 DB:
- *   ectool cbi set 6 2 4 10
- */
-static void cbi_init(void)
-{
-	uint32_t cbi_val;
-
-	/* Board ID */
-	if (cbi_get_board_version(&cbi_val) != EC_SUCCESS ||
-	    cbi_val > UINT8_MAX)
-		CPRINTS("CBI: Read Board ID failed");
-	else
-		board_id = cbi_val;
-
-	CPRINTS("Board ID: %d", board_id);
-
-	/* FW config */
-	init_fw_config();
-
-	/* Allow the board project to make runtime changes based on CBI data */
-	board_cbi_init();
-}
-DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_FIRST);
-
-/**
- * Return if VBUS is too low
- */
-int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
-{
-	int voltage;
-
-	if (charger_get_vbus_voltage(port, &voltage))
-		voltage = 0;
-
-	/*
-	 * For legacy BC1.2 charging with CONFIG_CHARGE_RAMP_SW, ramp up input
-	 * current until voltage drops to the minimum input voltage of the
-	 * charger, 4.096V.
-	 */
-	return voltage < ISL9241_BC12_MIN_VOLTAGE;
-}
-
diff --git a/baseboard/volteer/baseboard.h b/baseboard/volteer/baseboard.h
index d63c0062d5..d3c82f0651 100644
--- a/baseboard/volteer/baseboard.h
+++ b/baseboard/volteer/baseboard.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,13 +13,13 @@
 /*
  * By default, enable all console messages excepted HC
  */
-#define CC_DEFAULT     (CC_ALL & ~(BIT(CC_HOSTCMD)))
+#define CC_DEFAULT (CC_ALL & ~(BIT(CC_HOSTCMD)))
 
 /* NPCX7 config */
-#define NPCX7_PWM1_SEL    1  /* GPIO C2 is used as PWM1. */
-#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
+#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */
+#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */
 /* Internal SPI flash on NPCX796FC is 512 kB */
-#define CONFIG_FLASH_SIZE (512 * 1024)
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
 #define CONFIG_SPI_FLASH_REGS
 #define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
 
@@ -30,7 +30,7 @@
 #define CONFIG_LTO
 #define CONFIG_BOARD_VERSION_CBI
 #define CONFIG_CRC8
-#define CONFIG_CROS_BOARD_INFO
+#define CONFIG_CBI_EEPROM
 #define CONFIG_DPTF
 #define CONFIG_FPU
 #define CONFIG_HIBERNATE_PSL
@@ -43,8 +43,9 @@
 #define CONFIG_BOARD_RESET_AFTER_POWER_ON
 
 /* Host communication */
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#define CONFIG_HOST_INTERFACE_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S5
 
 /* Chipset config */
 #define CONFIG_CHIPSET_TIGERLAKE
@@ -58,13 +59,14 @@
 #define CONFIG_POWER_BUTTON_X86
 #define CONFIG_POWER_COMMON
 #define CONFIG_POWER_S0IX
+#define CONFIG_POWER_S4_RESIDENCY
 #define CONFIG_POWER_SLEEP_FAILURE_DETECTION
 #define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
 #define CONFIG_BOARD_HAS_RTC_RESET
 
 /* Common Keyboard Defines */
 #define CONFIG_CMD_KEYBOARD
-#define CONFIG_KEYBOARD_BOARD_CONFIG
+
 #define CONFIG_KEYBOARD_COL2_INVERTED
 #define CONFIG_KEYBOARD_KEYPAD
 #define CONFIG_KEYBOARD_PROTOCOL_8042
@@ -77,8 +79,8 @@
 
 #define CONFIG_MKBP_EVENT
 #define CONFIG_MKBP_USE_GPIO
+#define CONFIG_MKBP_INPUT_DEVICES
 #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-#define CONFIG_ACCEL_INTERRUPTS
 
 /* Enable sensor fifo, must also define the _SIZE and _THRES */
 #define CONFIG_ACCEL_FIFO
@@ -92,9 +94,10 @@
 #define CONFIG_CMD_ACCEL_INFO
 
 /* Thermal features */
-#define CONFIG_FANS			FAN_CH_COUNT
+#define CONFIG_FANS FAN_CH_COUNT
 #define CONFIG_TEMP_SENSOR
-#define CONFIG_TEMP_SENSOR_POWER_GPIO	GPIO_EN_PP3300_A
+#define CONFIG_TEMP_SENSOR_POWER
+#define GPIO_TEMP_SENSOR_POWER GPIO_PG_EC_DSW_PWROK
 #define CONFIG_THERMISTOR
 #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
 #define CONFIG_THROTTLE_AP
@@ -104,13 +107,16 @@
 #define CONFIG_CHARGE_MANAGER
 #define CONFIG_CHARGER
 #define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT		512
+#define CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT 512
+#define CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT 512
 
 /*
  * Hardware based charge ramp is broken in the ISL9241 (b/169350714).
  */
 #define CONFIG_CHARGE_RAMP_SW
 #define CONFIG_CHARGER_ISL9241
+/* Setting ISL9241 Register Control1 switching frequency to 724kHz. */
+#define CONFIG_ISL9241_SWITCHING_FREQ ISL9241_CONTROL1_SWITCHING_FREQ_724KHZ
 
 #define CONFIG_USB_CHARGER
 #define CONFIG_BC12_DETECT_PI3USB9201
@@ -119,10 +125,8 @@
  * Don't allow the system to boot to S0 when the battery is low and unable to
  * communicate on locked systems (which haven't PD negotiated)
  */
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT	15000
-#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON			3
-#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC		1
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON		15001
+#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT 15000
+#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 15001
 
 /* Common battery defines */
 #define CONFIG_BATTERY_SMART
@@ -137,7 +141,7 @@
 
 /* EDP back-light control defines */
 #define CONFIG_BACKLIGHT_LID
-#define GPIO_ENABLE_BACKLIGHT   GPIO_EC_EDP_BL_EN
+#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EDP_BL_EN
 
 /* USB Type C and USB PD defines */
 /* Enable the new USB-C PD stack */
@@ -158,19 +162,19 @@
 #define CONFIG_USB_POWER_DELIVERY
 #define CONFIG_USB_PD_ALT_MODE
 #define CONFIG_USB_PD_ALT_MODE_DFP
+#define CONFIG_USB_PD_ALT_MODE_UFP
 #define CONFIG_USB_PD_DISCHARGE_PPC
 #define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT		TYPEC_RP_3A0
 #define CONFIG_USB_PD_TCPC_RUNTIME_CONFIG
 #define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
 #define CONFIG_USB_PD_TCPC_LOW_POWER
 #define CONFIG_USB_PD_TCPM_TCPCI
 #define CONFIG_USB_PD_TCPM_RT1715
-#define CONFIG_USB_PD_TCPM_TUSB422	/* USBC port C0 */
-#define CONFIG_USB_PD_TCPM_PS8815	/* USBC port USB3 DB */
+#define CONFIG_USB_PD_TCPM_TUSB422 /* USBC port C0 */
+#define CONFIG_USB_PD_TCPM_PS8815 /* USBC port USB3 DB */
 #define CONFIG_USB_PD_TCPM_PS8815_FORCE_DID
 #define CONFIG_USB_PD_TCPM_MUX
-#define CONFIG_HOSTCMD_PD_CONTROL		/* Needed for TCPC FW update */
+#define CONFIG_HOSTCMD_PD_CONTROL /* Needed for TCPC FW update */
 #define CONFIG_CMD_USB_PD_PE
 
 /*
@@ -187,14 +191,13 @@
  * with non-PD chargers.  Override the default low-power mode exit delay.
  */
 #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
-#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE	(50*MSEC)
+#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (50 * MSEC)
 
 /* Enable USB3.2 DRD */
 #define CONFIG_USB_PD_USB32_DRD
 
 #define CONFIG_USB_PD_TRY_SRC
 #define CONFIG_USB_PD_VBUS_DETECT_TCPC
-#define CONFIG_USB_PD_VBUS_MEASURE_NOT_PRESENT
 
 #define CONFIG_USB_MUX_RUNTIME_CONFIG
 
@@ -206,7 +209,6 @@
  */
 #define CONFIG_USBC_PPC_DEDICATED_INT
 
-#define CONFIG_INTEL_VIRTUAL_MUX
 #define CONFIG_USBC_SS_MUX
 #define CONFIG_USB_MUX_VIRTUAL
 
@@ -226,15 +228,26 @@
  * http://google3/hardware/standards/usb/
  */
 #define CONFIG_USB_PID 0x503E
+/* Device version of product. */
+#define CONFIG_USB_BCD_DEV 0x0000
 
 /* Retimer */
 #define CONFIG_USBC_RETIMER_INTEL_BB
 #define CONFIG_USBC_RETIMER_INTEL_BB_RUNTIME_CONFIG
+#define CONFIG_USBC_RETIMER_FW_UPDATE
+
+/* Enable volume button command in EC console */
+#define CONFIG_CMD_BUTTON
+
+/* Enable volume button in ectool */
+#define CONFIG_HOSTCMD_BUTTON
 
 #ifndef __ASSEMBLER__
 
-#include "gpio_signal.h"
+#include "baseboard_usbc_config.h"
+#include "cbi.h"
 #include "common.h"
+#include "gpio_signal.h"
 
 enum adc_channel {
 	ADC_TEMP_SENSOR_1_CHARGER,
@@ -264,21 +277,6 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-/* Common definition for the USB PD interrupt handlers. */
-void ppc_interrupt(enum gpio_signal signal);
-void tcpc_alert_event(enum gpio_signal signal);
-void bc12_interrupt(enum gpio_signal signal);
-
-unsigned char get_board_id(void);
-
-/**
- * Configure run-time data structures and operation based on CBI data. This
- * typically includes customization for changes in the BOARD_VERSION and
- * FW_CONFIG fields in CBI. This routine is called from the baseboard after
- * the CBI data has been initialized.
- */
-__override_proto void board_cbi_init(void);
-
 /*
  * Check battery disconnect state.
  * This function will return if battery is initialized or not.
diff --git a/baseboard/volteer/baseboard_usbc_config.h b/baseboard/volteer/baseboard_usbc_config.h
new file mode 100644
index 0000000000..db5e296d46
--- /dev/null
+++ b/baseboard/volteer/baseboard_usbc_config.h
@@ -0,0 +1,18 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* volteer family-specific USB-C configuration */
+
+#ifndef __CROS_EC_BASEBOARD_USBC_CONFIG_H
+#define __CROS_EC_BASEBOARD_USBC_CONFIG_H
+
+#include "gpio_signal.h"
+
+/* Common definition for the USB PD interrupt handlers. */
+void ppc_interrupt(enum gpio_signal signal);
+void tcpc_alert_event(enum gpio_signal signal);
+void bc12_interrupt(enum gpio_signal signal);
+
+#endif /* __CROS_EC_BASEBOARD_USBC_CONFIG_H */
diff --git a/baseboard/volteer/battery_presence.c b/baseboard/volteer/battery_presence.c
index 4953d7a49e..d656b7b626 100644
--- a/baseboard/volteer/battery_presence.c
+++ b/baseboard/volteer/battery_presence.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -6,12 +6,12 @@
  * Each board should implement board_battery_info[] to define the specific
  * battery packs supported.
  */
-#include <stdbool.h>
-
 #include "battery.h"
 #include "battery_smart.h"
 #include "gpio.h"
 
+#include <stdbool.h>
+
 static enum battery_present batt_pres_prev = BP_NOT_SURE;
 
 enum battery_present battery_hw_present(void)
@@ -24,8 +24,9 @@ static bool battery_init(void)
 {
 	int batt_status;
 
-	return battery_status(&batt_status) ? 0 :
-		!!(batt_status & STATUS_INITIALIZED);
+	return battery_status(&batt_status) ?
+		       0 :
+		       !!(batt_status & STATUS_INITIALIZED);
 }
 
 __overridable bool board_battery_is_initialized(void)
diff --git a/baseboard/volteer/build.mk b/baseboard/volteer/build.mk
index 662f3abdee..2b2f4e97b1 100644
--- a/baseboard/volteer/build.mk
+++ b/baseboard/volteer/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -8,5 +8,10 @@
 
 baseboard-y=baseboard.o
 baseboard-y+=battery_presence.o
+baseboard-y+=charger.o
 baseboard-y+=usb_pd_policy.o
+baseboard-y+=cbi.o
 baseboard-y+=cbi_ec_fw_config.o
+baseboard-y+=cbi_ssfc.o
+baseboard-y+=power.o
+baseboard-y+=usbc_config.o
diff --git a/baseboard/volteer/cbi.c b/baseboard/volteer/cbi.c
new file mode 100644
index 0000000000..28606d7eaf
--- /dev/null
+++ b/baseboard/volteer/cbi.c
@@ -0,0 +1,53 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Volteer family-specific functions, shared with Zephyr */
+
+#include "cbi_ec_fw_config.h"
+#include "common.h"
+#include "cros_board_info.h"
+#include "hooks.h"
+#include "system.h"
+
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ##args)
+
+static uint8_t board_id;
+
+uint8_t get_board_id(void)
+{
+	return board_id;
+}
+
+__overridable void board_cbi_init(void)
+{
+}
+
+/*
+ * Read CBI from i2c eeprom and initialize variables for board variants
+ *
+ * Example for configuring for a USB3 DB:
+ *   ectool cbi set 6 2 4 10
+ */
+static void cbi_init(void)
+{
+	uint32_t cbi_val;
+
+	/* Board ID */
+	if (cbi_get_board_version(&cbi_val) != EC_SUCCESS ||
+	    cbi_val > UINT8_MAX)
+		CPRINTS("CBI: Read Board ID failed");
+	else
+		board_id = cbi_val;
+
+	CPRINTS("Board ID: %d", board_id);
+
+	/* FW config */
+	init_fw_config();
+
+	/* Allow the board project to make runtime changes based on CBI data */
+	board_cbi_init();
+}
+DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_FIRST);
diff --git a/baseboard/volteer/cbi.h b/baseboard/volteer/cbi.h
new file mode 100644
index 0000000000..4b4044ea3c
--- /dev/null
+++ b/baseboard/volteer/cbi.h
@@ -0,0 +1,23 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Volteer family-specific CBI functions, shared with Zephyr */
+
+#ifndef __CROS_EC_BASEBOARD_CBI_H
+#define __CROS_EC_BASEBOARD_CBI_H
+
+#include "common.h"
+
+unsigned char get_board_id(void);
+
+/**
+ * Configure run-time data structures and operation based on CBI data. This
+ * typically includes customization for changes in the BOARD_VERSION and
+ * FW_CONFIG fields in CBI. This routine is called from the baseboard after
+ * the CBI data has been initialized.
+ */
+__override_proto void board_cbi_init(void);
+
+#endif /* __CROS_EC_BASEBOARD_CBI_H */
diff --git a/baseboard/volteer/cbi_ec_fw_config.c b/baseboard/volteer/cbi_ec_fw_config.c
index 12b96ff5b4..f925498774 100644
--- a/baseboard/volteer/cbi_ec_fw_config.c
+++ b/baseboard/volteer/cbi_ec_fw_config.c
@@ -1,14 +1,14 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "cbi_ec_fw_config.h"
 #include "common.h"
 #include "console.h"
-#include "cbi_ec_fw_config.h"
 #include "cros_board_info.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 static union volteer_cbi_fw_config fw_config;
 BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
@@ -49,3 +49,7 @@ bool ec_cfg_has_numeric_pad(void)
 	return (fw_config.num_pad == NUMERIC_PAD_ENABLED);
 }
 
+enum ec_cfg_keyboard_layout ec_cfg_keyboard_layout(void)
+{
+	return fw_config.kb_layout;
+}
diff --git a/baseboard/volteer/cbi_ec_fw_config.h b/baseboard/volteer/cbi_ec_fw_config.h
index 5b97f778ec..da91dff27b 100644
--- a/baseboard/volteer/cbi_ec_fw_config.h
+++ b/baseboard/volteer/cbi_ec_fw_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -43,17 +43,20 @@ enum ec_cfg_numeric_pad_type {
 	NUMERIC_PAD_ENABLED = 1
 };
 
+enum ec_cfg_keyboard_layout { KB_LAYOUT_DEFAULT = 0, KB_LAYOUT_1 = 1 };
+
 union volteer_cbi_fw_config {
 	struct {
-		enum ec_cfg_usb_db_type			usb_db : 4;
-		uint32_t				thermal : 4;
-		uint32_t				audio : 3;
-		enum ec_cfg_tabletmode_type		tabletmode : 1;
-		uint32_t				lte_db : 2;
-		enum ec_cfg_keyboard_backlight_type	kb_bl : 1;
-		enum ec_cfg_numeric_pad_type		num_pad : 1;
-		uint32_t				sd_db : 4;
-		uint32_t				reserved_2 : 12;
+		enum ec_cfg_usb_db_type usb_db : 4;
+		uint32_t thermal : 4;
+		uint32_t audio : 3;
+		enum ec_cfg_tabletmode_type tabletmode : 1;
+		uint32_t lte_db : 2;
+		enum ec_cfg_keyboard_backlight_type kb_bl : 1;
+		enum ec_cfg_numeric_pad_type num_pad : 1;
+		uint32_t sd_db : 4;
+		enum ec_cfg_keyboard_layout kb_layout : 2;
+		uint32_t reserved_2 : 10;
 	};
 	uint32_t raw_value;
 };
@@ -108,4 +111,11 @@ bool ec_cfg_has_keyboard_backlight(void);
  */
 bool ec_cfg_has_numeric_pad(void);
 
+/**
+ * Get keyboard type from FW_CONFIG.
+ *
+ * @return the keyboard type.
+ */
+enum ec_cfg_keyboard_layout ec_cfg_keyboard_layout(void);
+
 #endif /* __VOLTEER_CBI_EC_FW_CONFIG_H_ */
diff --git a/baseboard/volteer/cbi_ssfc.c b/baseboard/volteer/cbi_ssfc.c
new file mode 100644
index 0000000000..f68602b558
--- /dev/null
+++ b/baseboard/volteer/cbi_ssfc.c
@@ -0,0 +1,46 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi_ssfc.h"
+#include "common.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "hooks.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+/* Cache SSFC on init since we don't expect it to change in runtime */
+static union volteer_cbi_ssfc cached_ssfc;
+BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
+
+static void cbi_ssfc_init(void)
+{
+	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
+		/* Default to 0 when CBI isn't populated */
+		cached_ssfc.raw_value = 0;
+
+	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
+}
+DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
+
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
+{
+	return cached_ssfc.base_sensor;
+}
+
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
+{
+	return cached_ssfc.lid_sensor;
+}
+
+enum ec_ssfc_lightbar get_cbi_ssfc_lightbar(void)
+{
+	return cached_ssfc.lightbar;
+}
+
+enum ec_ssfc_keyboard get_cbi_ssfc_keyboard(void)
+{
+	return cached_ssfc.keyboard;
+}
diff --git a/baseboard/volteer/cbi_ssfc.h b/baseboard/volteer/cbi_ssfc.h
new file mode 100644
index 0000000000..225ff8670e
--- /dev/null
+++ b/baseboard/volteer/cbi_ssfc.h
@@ -0,0 +1,88 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _VOLTEER_CBI_SSFC__H_
+#define _VOLTEER_CBI_SSFC__H_
+
+#include "stdint.h"
+
+/****************************************************************************
+ * Volteer CBI Second Source Factory Cache
+ */
+
+/*
+ * Base Sensor (Bits 0-2)
+ */
+enum ec_ssfc_base_sensor {
+	SSFC_SENSOR_BASE_DEFAULT = 0,
+	SSFC_SENSOR_BASE_BMI160 = 1,
+	SSFC_SENSOR_BASE_ICM426XX = 2,
+	SSFC_SENSOR_BASE_ICM42607 = 3
+};
+
+/*
+ * Lid Sensor (Bits 3-5)
+ */
+enum ec_ssfc_lid_sensor {
+	SSFC_SENSOR_LID_DEFAULT = 0,
+	SSFC_SENSOR_LID_BMA255 = 1,
+	SSFC_SENSOR_LID_KX022 = 2
+};
+
+/*
+ * Lightbar (Bits 6-7)
+ */
+enum ec_ssfc_lightbar {
+	SSFC_LIGHTBAR_NONE = 0,
+	SSFC_LIGHTBAR_10_LED = 1,
+	SSFC_LIGHTBAR_12_LED = 2
+};
+
+/*
+ * Keyboard Type (Bit 12)
+ */
+enum ec_ssfc_keyboard { SSFC_KEYBOARD_DEFAULT = 0, SSFC_KEYBOARD_GAMING = 1 };
+
+union volteer_cbi_ssfc {
+	struct {
+		enum ec_ssfc_base_sensor base_sensor : 3;
+		enum ec_ssfc_lid_sensor lid_sensor : 3;
+		enum ec_ssfc_lightbar lightbar : 2;
+		uint32_t reserved_2 : 4;
+		enum ec_ssfc_keyboard keyboard : 1;
+		uint32_t reserved_3 : 19;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Get the Base sensor type from SSFC_CONFIG.
+ *
+ * @return the Base sensor board type.
+ */
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
+
+/**
+ * Get the Lid sensor type from SSFC_CONFIG.
+ *
+ * @return the Lid sensor board type.
+ */
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
+
+/**
+ * Get lightbar type from SSFC_CONFIG.
+ *
+ * @return the lightbar type.
+ */
+enum ec_ssfc_lightbar get_cbi_ssfc_lightbar(void);
+
+/**
+ * Get keyboard type from SSFC_CONFIG.
+ *
+ * @return the keyboard type.
+ */
+enum ec_ssfc_keyboard get_cbi_ssfc_keyboard(void);
+
+#endif /* _Volteer_CBI_SSFC__H_ */
diff --git a/baseboard/volteer/charger.c b/baseboard/volteer/charger.c
new file mode 100644
index 0000000000..17f1fe5f7d
--- /dev/null
+++ b/baseboard/volteer/charger.c
@@ -0,0 +1,94 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Volteer family-specific configuration */
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "common.h"
+#include "driver/charger/isl9241_public.h"
+#include "gpio.h"
+#ifdef CONFIG_ZEPHYR
+#include "usbc_config.h"
+#endif
+#include "usbc_ppc.h"
+#include "util.h"
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/* Charger Chip Configuration */
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = ISL9241_ADDR_FLAGS,
+		.drv = &isl9241_drv,
+	},
+};
+
+int board_set_active_charge_port(int port)
+{
+	int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int i;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTSUSB("Disabling all charger ports");
+
+		/* Disable all ports. */
+		for (i = 0; i < ppc_cnt; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (ppc_vbus_sink_enable(i, 0))
+				CPRINTSUSB("Disabling C%d as sink failed.", i);
+		}
+
+		return EC_SUCCESS;
+	} else if (!is_valid_port) {
+		return EC_ERROR_INVAL;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (ppc_is_sourcing_vbus(port)) {
+		CPRINTFUSB("Skip enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTSUSB("New charge port: C%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < ppc_cnt; i++) {
+		if (i == port)
+			continue;
+
+		if (ppc_vbus_sink_enable(i, 0))
+			CPRINTSUSB("C%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTSUSB("C%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+void board_overcurrent_event(int port, int is_overcurrented)
+{
+	/* Note that the level is inverted because the pin is active low. */
+	switch (port) {
+	case USBC_PORT_C0:
+		gpio_set_level(GPIO_USB_C0_OC_ODL, !is_overcurrented);
+		break;
+	case USBC_PORT_C1:
+		gpio_set_level(GPIO_USB_C1_OC_ODL, !is_overcurrented);
+		break;
+	}
+}
diff --git a/baseboard/volteer/power.c b/baseboard/volteer/power.c
new file mode 100644
index 0000000000..882c067b6d
--- /dev/null
+++ b/baseboard/volteer/power.c
@@ -0,0 +1,70 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "gpio.h"
+#include "hooks.h"
+#include "power/icelake.h"
+#include "throttle_ap.h"
+
+/*
+ * PWROK signal configuration, see the PWROK Generation Flow Diagram (Figure
+ * 235) in the Tiger Lake Platform Design Guide for the list of potential
+ * signals.
+ *
+ * Volteer uses this power sequence:
+ *	GPIO_EN_PPVAR_VCCIN - Turns on the VCCIN rail. Also used as a delay to
+ *		the VCCST_PWRGD input to the AP so this signal must be delayed
+ *		5 ms to meet the tCPU00 timing requirement.
+ *	GPIO_EC_PCH_SYS_PWROK - Asserts the SYS_PWROK input to the AP. Delayed
+ *		a total of 50 ms after ALL_SYS_PWRGD input is asserted. See
+ *		b/144478941 for full discussion.
+ *
+ * Volteer does not provide direct EC control for the VCCST_PWRGD and PCH_PWROK
+ * signals. If your board adds these signals to the EC, copy this array
+ * to your board.c file and modify as needed.
+ */
+const struct intel_x86_pwrok_signal pwrok_signal_assert_list[] = {
+	{
+		.gpio = GPIO_EN_PPVAR_VCCIN,
+		.delay_ms = 5,
+	},
+	{
+		.gpio = GPIO_EC_PCH_SYS_PWROK,
+		.delay_ms = 50 - 5,
+	},
+};
+const int pwrok_signal_assert_count = ARRAY_SIZE(pwrok_signal_assert_list);
+
+const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[] = {
+	/* No delays needed during S0 exit */
+	{
+		.gpio = GPIO_EC_PCH_SYS_PWROK,
+	},
+	/* Turn off VCCIN last */
+	{
+		.gpio = GPIO_EN_PPVAR_VCCIN,
+	},
+};
+const int pwrok_signal_deassert_count = ARRAY_SIZE(pwrok_signal_deassert_list);
+
+static const struct prochot_cfg volteer_prochot_cfg = {
+	.gpio_prochot_in = GPIO_EC_PROCHOT_IN_L,
+#ifdef CONFIG_CPU_PROCHOT_GATE_ON_C10
+	.gpio_c10_in = GPIO_CPU_C10_GATE_L,
+	.c10_active_high = false,
+#endif
+};
+
+static void baseboard_init(void)
+{
+	/* Enable monitoring of the PROCHOT input to the EC */
+	throttle_ap_config_prochot(&volteer_prochot_cfg);
+	gpio_enable_interrupt(GPIO_EC_PROCHOT_IN_L);
+
+#ifdef CONFIG_CPU_PROCHOT_GATE_ON_C10
+	gpio_enable_interrupt(GPIO_CPU_C10_GATE_L);
+#endif
+}
+DECLARE_HOOK(HOOK_INIT, baseboard_init, HOOK_PRIO_DEFAULT);
diff --git a/baseboard/volteer/usb_pd_policy.c b/baseboard/volteer/usb_pd_policy.c
index 39bbd918a5..18c24b64ef 100644
--- a/baseboard/volteer/usb_pd_policy.c
+++ b/baseboard/volteer/usb_pd_policy.c
@@ -1,19 +1,21 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 /* Shared USB-C policy for Volteer boards */
 #include "charge_manager.h"
+#include "chipset.h"
 #include "compile_time_macros.h"
 #include "console.h"
 #include "gpio.h"
+#include "system.h"
+#include "usb_common.h"
 #include "usb_mux.h"
-#include "usbc_ppc.h"
 #include "usb_pd.h"
-#include "system.h"
+#include "usbc_ppc.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
@@ -34,11 +36,6 @@ void pd_power_supply_reset(int port)
 	if (prev_en)
 		pd_set_vbus_discharge(port, 1);
 
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	/* Give back the current quota we are no longer using */
-	charge_manager_source_port(port, 0);
-#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
-
 	/* Notify host of power info change. */
 	pd_send_host_event(PD_EVENT_POWER_CHANGE);
 }
@@ -59,23 +56,167 @@ int pd_set_power_supply_ready(int port)
 	if (rv)
 		return rv;
 
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	/* Ensure we advertise the proper available current quota */
-	charge_manager_source_port(port, 1);
-#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
-
 	/* Notify host of power info change. */
 	pd_send_host_event(PD_EVENT_POWER_CHANGE);
 
 	return EC_SUCCESS;
 }
 
+#ifdef CONFIG_USB_PD_VBUS_DETECT_PPC
 int pd_snk_is_vbus_provided(int port)
 {
 	return ppc_is_vbus_present(port);
 }
+#endif /* defined(CONFIG_USB_PD_VBUS_DETECT_PPC) */
 
 int board_vbus_source_enabled(int port)
 {
 	return ppc_is_sourcing_vbus(port);
 }
+
+#ifdef CONFIG_USB_PD_TBT_COMPAT_MODE
+/* ----------------- Vendor Defined Messages ------------------ */
+/* Responses specifically for the enablement of TBT mode in the role of UFP */
+
+#define OPOS_TBT 1
+
+static const union tbt_mode_resp_device vdo_tbt_modes[1] = { {
+	.tbt_alt_mode = 0x0001,
+	.tbt_adapter = TBT_ADAPTER_TBT3,
+	.intel_spec_b0 = 0,
+	.vendor_spec_b0 = 0,
+	.vendor_spec_b1 = 0,
+} };
+
+static const uint32_t vdo_idh = VDO_IDH(1, /* Data caps as USB host     */
+					0, /* Not a USB device   */
+					IDH_PTYPE_PERIPH, 1, /* Supports alt
+								modes */
+					USB_VID_GOOGLE);
+
+static const uint32_t vdo_idh_rev30 =
+	VDO_IDH_REV30(1, /* Data caps as USB host     */
+		      0, /* Not a USB device   */
+		      IDH_PTYPE_PERIPH, 1, /* Supports alt modes */
+		      IDH_PTYPE_DFP_HOST, USB_TYPEC_RECEPTACLE, USB_VID_GOOGLE);
+
+static const uint32_t vdo_product =
+	VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV);
+
+/* TODO(b/168890624): add USB4 to capability once USB4 response implemented */
+static const uint32_t vdo_ufp1 = VDO_UFP1(
+	(VDO_UFP1_CAPABILITY_USB20 | VDO_UFP1_CAPABILITY_USB32),
+	USB_TYPEC_RECEPTACLE, VDO_UFP1_ALT_MODE_TBT3, USB_R30_SS_U40_GEN3);
+
+static const uint32_t vdo_dfp =
+	VDO_DFP((VDO_DFP_HOST_CAPABILITY_USB20 | VDO_DFP_HOST_CAPABILITY_USB32 |
+		 VDO_DFP_HOST_CAPABILITY_USB4),
+		USB_TYPEC_RECEPTACLE, 1 /* Port 1 */);
+
+static int svdm_tbt_compat_response_identity(int port, uint32_t *payload)
+{
+	/* TODO(b/154962766): Get an XID */
+	payload[VDO_I(CSTAT)] = VDO_CSTAT(0);
+	payload[VDO_I(PRODUCT)] = vdo_product;
+
+	if (pd_get_rev(port, TCPCI_MSG_SOP) == PD_REV30) {
+		/* PD Revision 3.0 */
+		payload[VDO_I(IDH)] = vdo_idh_rev30;
+		payload[VDO_I(PTYPE_UFP1_VDO)] = vdo_ufp1;
+		/* TODO(b/156749387): Find power number for USB3/4 */
+		payload[VDO_I(PTYPE_UFP2_VDO)] = 0;
+		payload[VDO_I(PTYPE_DFP_VDO)] = vdo_dfp;
+		return VDO_I(PTYPE_DFP_VDO) + 1;
+	}
+
+	/* PD Revision 2.0 */
+	payload[VDO_I(IDH)] = vdo_idh;
+	return VDO_I(PRODUCT) + 1;
+}
+
+static int svdm_tbt_compat_response_svids(int port, uint32_t *payload)
+{
+	payload[1] = VDO_SVID(USB_VID_INTEL, 0);
+	return 2;
+}
+
+static int svdm_tbt_compat_response_modes(int port, uint32_t *payload)
+{
+	if (PD_VDO_VID(payload[0]) == USB_VID_INTEL) {
+		memcpy(payload + 1, vdo_tbt_modes, sizeof(vdo_tbt_modes));
+		return ARRAY_SIZE(vdo_tbt_modes) + 1;
+	} else {
+		return 0; /* NAK */
+	}
+}
+
+/* Track whether we've been enabled to ACK TBT EnterModes requests */
+static bool tbt_ufp_ack_allowed[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+__override enum ec_status
+board_set_tbt_ufp_reply(int port, enum typec_tbt_ufp_reply reply)
+{
+	/* Note: Host command has already bounds-checked port */
+	if (reply == TYPEC_TBT_UFP_REPLY_ACK)
+		tbt_ufp_ack_allowed[port] = true;
+	else if (reply == TYPEC_TBT_UFP_REPLY_NAK)
+		tbt_ufp_ack_allowed[port] = false;
+	else
+		return EC_RES_INVALID_PARAM;
+
+	return EC_RES_SUCCESS;
+}
+
+static int svdm_tbt_compat_response_enter_mode(int port, uint32_t *payload)
+{
+	mux_state_t mux_state = 0;
+
+	/* Do not enter mode while CPU is off. */
+	if (chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF))
+		return 0; /* NAK */
+
+	/* Do not enter mode while policy disallows it */
+	if (!tbt_ufp_ack_allowed[port])
+		return 0; /* NAK */
+
+	if ((PD_VDO_VID(payload[0]) != USB_VID_INTEL) ||
+	    (PD_VDO_OPOS(payload[0]) != OPOS_TBT))
+		return 0; /* NAK */
+
+	mux_state = usb_mux_get(port);
+	/*
+	 * Ref: USB PD 3.0 Spec figure 6-21 Successful Enter Mode sequence
+	 * UFP (responder) should be in USB mode or safe mode before entering a
+	 * Mode that requires the reconfiguring of any pins.
+	 */
+	if ((mux_state & USB_PD_MUX_USB_ENABLED) ||
+	    (mux_state & USB_PD_MUX_SAFE_MODE)) {
+		pd_ufp_set_enter_mode(port, payload);
+		set_tbt_compat_mode_ready(port);
+
+		/*
+		 * Ref: Above figure 6-21: UFP (responder) should be in the new
+		 * mode before sending the ACK.  However, our mux set sequence
+		 * may exceed tVDMEnterMode, so wait as long as we can
+		 * before sending the reply without violating that timer.
+		 */
+		if (!usb_mux_set_completed(port))
+			usleep(PD_T_VDM_E_MODE / 2);
+
+		CPRINTS("UFP Enter TBT mode");
+		return 1; /* ACK */
+	}
+
+	CPRINTS("UFP failed to enter TBT mode(mux=0x%x)", mux_state);
+	return 0;
+}
+
+const struct svdm_response svdm_rsp = {
+	.identity = &svdm_tbt_compat_response_identity,
+	.svids = &svdm_tbt_compat_response_svids,
+	.modes = &svdm_tbt_compat_response_modes,
+	.enter_mode = &svdm_tbt_compat_response_enter_mode,
+	.amode = NULL,
+	.exit_mode = NULL,
+};
+#endif /* CONFIG_USB_PD_TBT_COMPAT_MODE */
diff --git a/baseboard/volteer/usbc_config.c b/baseboard/volteer/usbc_config.c
new file mode 100644
index 0000000000..d77e275282
--- /dev/null
+++ b/baseboard/volteer/usbc_config.c
@@ -0,0 +1,78 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Volteer family-specific USB-C configuration */
+
+#include "charge_manager.h"
+#include "charge_ramp.h"
+#include "charge_state.h"
+#include "common.h"
+#include "driver/charger/isl9241_public.h"
+#include "gpio.h"
+#include "task.h"
+#include "usb_charge.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#ifdef CONFIG_ZEPHYR
+#include "baseboard_usbc_config.h"
+#include "usbc_config.h"
+#endif
+
+/******************************************************************************/
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	/* TODO: b/140572591 - check correct operation for Volteer */
+
+	int port = -1;
+
+	switch (signal) {
+	case GPIO_USB_C0_TCPC_INT_ODL:
+		port = USBC_PORT_C0;
+		break;
+	case GPIO_USB_C1_TCPC_INT_ODL:
+		port = USBC_PORT_C1;
+		break;
+	default:
+		return;
+	}
+
+	schedule_deferred_pd_interrupt(port);
+}
+
+void bc12_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_BC12_INT_ODL:
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+		break;
+
+	case GPIO_USB_C1_BC12_INT_ODL:
+		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+		break;
+
+	default:
+		break;
+	}
+}
+
+/**
+ * Return if VBUS is too low
+ */
+int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
+{
+	int voltage;
+
+	if (charger_get_vbus_voltage(port, &voltage))
+		voltage = 0;
+
+	/*
+	 * For legacy BC1.2 charging with CONFIG_CHARGE_RAMP_SW, ramp up input
+	 * current until voltage drops to the minimum input voltage of the
+	 * charger, 4.096V.
+	 */
+	return voltage < ISL9241_BC12_MIN_VOLTAGE;
+}
diff --git a/baseboard/zork/baseboard.c b/baseboard/zork/baseboard.c
index 36591bb4f2..e54656f08a 100644
--- a/baseboard/zork/baseboard.c
+++ b/baseboard/zork/baseboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,13 +6,11 @@
 /* Zork family-specific configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "button.h"
 #include "cbi_ec_fw_config.h"
 #include "charge_manager.h"
 #include "charge_ramp.h"
 #include "charge_state.h"
-#include "charge_state_v2.h"
 #include "common.h"
 #include "compile_time_macros.h"
 #include "console.h"
@@ -25,22 +23,23 @@
 #include "extpower.h"
 #include "gpio.h"
 #include "hooks.h"
-#include "ioexpander.h"
 #include "i2c.h"
+#include "ioexpander.h"
 #include "keyboard_scan.h"
 #include "lid_switch.h"
 #include "motion_sense.h"
 #include "power.h"
 #include "power_button.h"
+#include "printf.h"
 #include "pwm.h"
 #include "pwm_chip.h"
 #include "registers.h"
 #include "switch.h"
 #include "system.h"
 #include "task.h"
-#include "tcpci.h"
+#include "tcpm/tcpci.h"
 #include "temp_sensor.h"
-#include "thermistor.h"
+#include "temp_sensor/thermistor.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
 #include "util.h"
@@ -60,15 +59,15 @@ const enum gpio_signal hibernate_wake_pins[] = {
 	GPIO_POWER_BUTTON_L,
 	GPIO_EC_RST_ODL,
 };
-const int hibernate_wake_pins_used =  ARRAY_SIZE(hibernate_wake_pins);
+const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 
 /*
  * In the AOZ1380 PPC, there are no programmable features.  We use
  * the attached NCT3807 to control a GPIO to indicate 1A5 or 3A0
  * current limits.
  */
-__overridable int board_aoz1380_set_vbus_source_current_limit(int port,
-						enum tcpc_rp_value rp)
+__overridable int
+board_aoz1380_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp)
 {
 	int rv;
 
@@ -96,16 +95,8 @@ static void baseboard_chipset_resume(void)
 }
 DECLARE_HOOK(HOOK_CHIPSET_RESUME, baseboard_chipset_resume, HOOK_PRIO_DEFAULT);
 
-__overridable void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
-}
-
 /* Keyboard scan setting */
-struct keyboard_scan_config keyscan_config = {
+__override struct keyboard_scan_config keyscan_config = {
 	/*
 	 * F3 key scan cycle completed but scan input is not
 	 * charging to logic high when EC start scan next
@@ -135,19 +126,19 @@ struct keyboard_scan_config keyscan_config = {
  * Murata page for part NCP15WB473F03RC. Vdd=3.3V, R=30.9Kohm.
  */
 const struct thermistor_data_pair thermistor_data[] = {
-	{ 2761 / THERMISTOR_SCALING_FACTOR, 0},
-	{ 2492 / THERMISTOR_SCALING_FACTOR, 10},
-	{ 2167 / THERMISTOR_SCALING_FACTOR, 20},
-	{ 1812 / THERMISTOR_SCALING_FACTOR, 30},
-	{ 1462 / THERMISTOR_SCALING_FACTOR, 40},
-	{ 1146 / THERMISTOR_SCALING_FACTOR, 50},
-	{ 878 / THERMISTOR_SCALING_FACTOR, 60},
-	{ 665 / THERMISTOR_SCALING_FACTOR, 70},
-	{ 500 / THERMISTOR_SCALING_FACTOR, 80},
-	{ 434 / THERMISTOR_SCALING_FACTOR, 85},
-	{ 376 / THERMISTOR_SCALING_FACTOR, 90},
-	{ 326 / THERMISTOR_SCALING_FACTOR, 95},
-	{ 283 / THERMISTOR_SCALING_FACTOR, 100}
+	{ 2761 / THERMISTOR_SCALING_FACTOR, 0 },
+	{ 2492 / THERMISTOR_SCALING_FACTOR, 10 },
+	{ 2167 / THERMISTOR_SCALING_FACTOR, 20 },
+	{ 1812 / THERMISTOR_SCALING_FACTOR, 30 },
+	{ 1462 / THERMISTOR_SCALING_FACTOR, 40 },
+	{ 1146 / THERMISTOR_SCALING_FACTOR, 50 },
+	{ 878 / THERMISTOR_SCALING_FACTOR, 60 },
+	{ 665 / THERMISTOR_SCALING_FACTOR, 70 },
+	{ 500 / THERMISTOR_SCALING_FACTOR, 80 },
+	{ 434 / THERMISTOR_SCALING_FACTOR, 85 },
+	{ 376 / THERMISTOR_SCALING_FACTOR, 90 },
+	{ 326 / THERMISTOR_SCALING_FACTOR, 95 },
+	{ 283 / THERMISTOR_SCALING_FACTOR, 100 }
 };
 
 const struct thermistor_info thermistor_info = {
@@ -156,8 +147,7 @@ const struct thermistor_info thermistor_info = {
 	.data = thermistor_data,
 };
 
-#ifndef TEST_BUILD
-void lid_angle_peripheral_enable(int enable)
+__override void lid_angle_peripheral_enable(int enable)
 {
 	if (ec_config_has_lid_angle_tablet_mode()) {
 		int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
@@ -177,7 +167,6 @@ void lid_angle_peripheral_enable(int enable)
 		}
 	}
 }
-#endif
 
 static void cbi_init(void)
 {
@@ -236,7 +225,7 @@ void board_hibernate(void)
 		pd_request_source_voltage(port, SAFE_RESET_VBUS_MV);
 
 		/* Give PD task and PPC chip time to get to 5V */
-		msleep(300);
+		msleep(900);
 	}
 }
 
@@ -266,8 +255,10 @@ void board_print_temps(void)
 {
 	int t, i;
 	int rv;
+	char ts_str[PRINTF_TIMESTAMP_BUF_SIZE];
 
-	cprintf(CC_THERMAL, "[%pT ", PRINTF_TIMESTAMP_NOW);
+	snprintf_timestamp_now(ts_str, sizeof(ts_str));
+	cprintf(CC_THERMAL, "[%s ", ts_str);
 	for (i = 0; i < TEMP_SENSOR_COUNT; ++i) {
 		rv = temp_sensor_read(i, &t);
 		if (rv == EC_SUCCESS)
@@ -281,7 +272,7 @@ void board_print_temps(void)
 				   temps_interval * SECOND);
 }
 
-static int command_temps_log(int argc, char **argv)
+static int command_temps_log(int argc, const char **argv)
 {
 	char *e = NULL;
 
@@ -296,8 +287,7 @@ static int command_temps_log(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(tempslog, command_temps_log,
-			"seconds",
+DECLARE_CONSOLE_COMMAND(tempslog, command_temps_log, "seconds",
 			"Print temp sensors periodically");
 
 /*
diff --git a/baseboard/zork/baseboard.h b/baseboard/zork/baseboard.h
index cd3bb4cbb9..c55ca12c76 100644
--- a/baseboard/zork/baseboard.h
+++ b/baseboard/zork/baseboard.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,22 +8,21 @@
 #ifndef __CROS_EC_BASEBOARD_H
 #define __CROS_EC_BASEBOARD_H
 
-#if (defined(VARIANT_ZORK_TREMBYLE) \
-	+ defined(VARIANT_ZORK_DALBOZ)) != 1
+#if (defined(VARIANT_ZORK_TREMBYLE) + defined(VARIANT_ZORK_DALBOZ)) != 1
 #error Must choose VARIANT_ZORK_TREMBYLE or VARIANT_ZORK_DALBOZ
 #endif
 
 /* NPCX7 config */
-#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
-#define NPCX_TACH_SEL2    0  /* No tach. */
-#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
+#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */
+#define NPCX_TACH_SEL2 0 /* No tach. */
+#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */
 
 /* Internal SPI flash on NPCX7 */
-#define CONFIG_FLASH_SIZE (512 * 1024)
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
 #define CONFIG_SPI_FLASH_REGS
 #define CONFIG_SPI_FLASH_W25Q40 /* Internal SPI flash type. */
 
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_HOSTCMD)))
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_HOSTCMD) | CC_MASK(CC_LPC)))
 
 /*
  * Enable 1 slot of secure temporary storage to support
@@ -38,9 +37,9 @@
 #define CONFIG_CMD_AP_RESET_LOG
 #define CONFIG_CPU_PROCHOT_ACTIVE_LOW
 #define CONFIG_HIBERNATE_PSL
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_CONTROLLER
 #define CONFIG_I2C_UPDATE_IF_CHANGED
 #define CONFIG_LOW_POWER_IDLE
 #define CONFIG_LTO
@@ -53,7 +52,7 @@
 #define CONFIG_VOLUME_BUTTONS
 
 /* CBI EEPROM for board version and SKU ID */
-#define CONFIG_CROS_BOARD_INFO
+#define CONFIG_CBI_EEPROM
 #define CONFIG_BOARD_VERSION_CBI
 #define CONFIG_CRC8
 
@@ -61,13 +60,24 @@
 #define CONFIG_BATTERY_FUEL_GAUGE
 #define CONFIG_BATTERY_REVIVE_DISCONNECT
 #define CONFIG_BATTERY_SMART
+/*
+ * Enable support for battery hostcmd, supporting longer strings.
+ *
+ * Vilboz battery options' model names vary in the 8th character, which is
+ * truncated in the memory mapped battery info; differentiating them requires
+ * support for EC_CMD_BATTERY_GET_STATIC version 1.
+ */
+#define CONFIG_BATTERY_V2
+#define CONFIG_BATTERY_COUNT 1
+#define CONFIG_HOSTCMD_BATTERY_V2
 
 #define CONFIG_BC12_DETECT_PI3USB9201
 
 #define CONFIG_CHARGER
 #define CONFIG_CHARGE_MANAGER
 #define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT 512
+#define CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT 512
+#define CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT 512
 #define CONFIG_CHARGER_ISL9241
 #define CONFIG_CHARGER_SENSE_RESISTOR 10
 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 20
@@ -82,20 +92,19 @@
 #define CONFIG_CHIPSET_CAN_THROTTLE
 #define CONFIG_CHIPSET_RESET_HOOK
 
-#undef  CONFIG_EXTPOWER_DEBOUNCE_MS
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
 #define CONFIG_EXTPOWER_DEBOUNCE_MS 200
 #define CONFIG_EXTPOWER_GPIO
 #define CONFIG_POWER_COMMON
-#define CONFIG_POWER_SHUTDOWN_PAUSE_IN_S5
 #define CONFIG_POWER_BUTTON
 #define CONFIG_POWER_BUTTON_X86
 #define CONFIG_POWER_BUTTON_TO_PCH_CUSTOM
+#define CONFIG_THROTTLE_AP
 
 #ifdef VARIANT_ZORK_TREMBYLE
-	#define CONFIG_FANS FAN_CH_COUNT
-	#undef CONFIG_FAN_INIT_SPEED
-	#define CONFIG_FAN_INIT_SPEED 50
-	#define CONFIG_THROTTLE_AP
+#define CONFIG_FANS FAN_CH_COUNT
+#undef CONFIG_FAN_INIT_SPEED
+#define CONFIG_FAN_INIT_SPEED 50
 #endif
 
 #define CONFIG_LED_COMMON
@@ -113,10 +122,9 @@
 #define CONFIG_IO_EXPANDER
 #define CONFIG_IO_EXPANDER_NCT38XX
 
-#define CONFIG_KEYBOARD_BOARD_CONFIG
 #define CONFIG_KEYBOARD_COL2_INVERTED
 #define CONFIG_KEYBOARD_PROTOCOL_8042
-#undef  CONFIG_KEYBOARD_VIVALDI
+#undef CONFIG_KEYBOARD_VIVALDI
 
 /*
  * USB ID
@@ -132,14 +140,14 @@
 #define CONFIG_USB_PD_TCPMV2
 
 #ifndef CONFIG_USB_PD_TCPMV2
-	#define CONFIG_USB_PD_TCPMV1
+#define CONFIG_USB_PD_TCPMV1
 #else
-	#define CONFIG_USB_PD_DECODE_SOP
-	#define CONFIG_USB_DRP_ACC_TRYSRC
+#define CONFIG_USB_PD_DECODE_SOP
+#define CONFIG_USB_DRP_ACC_TRYSRC
 
-	 /* Enable TCPMv2 Fast Role Swap */
-	 /* Turn off until FRSwap is working */
-	#undef CONFIG_USB_PD_FRS_TCPC
+/* Enable TCPMv2 Fast Role Swap */
+/* Turn off until FRSwap is working */
+#undef CONFIG_USB_PD_FRS_TCPC
 #endif
 
 #define CONFIG_HOSTCMD_PD_CONTROL
@@ -156,12 +164,11 @@
  * Use a custom HPD function that supports HPD on IO expander.
  * TODO(b/165622386) remove this when HPD is on EC GPIO.
  */
-#	define CONFIG_USB_PD_DP_HPD_GPIO_CUSTOM
+#define CONFIG_USB_PD_DP_HPD_GPIO_CUSTOM
 #endif
 #define CONFIG_USB_PD_DUAL_ROLE
 #define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
 #define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT TYPEC_RP_3A0
 #define CONFIG_USB_PD_TCPC_LOW_POWER
 #define CONFIG_USB_PD_TCPM_MUX
 #define CONFIG_USB_PD_TCPM_NCT38XX
@@ -179,17 +186,19 @@
 #define CONFIG_USB_MUX_AMD_FP5
 
 #if defined(VARIANT_ZORK_TREMBYLE)
-	#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-	#define CONFIG_USBC_PPC_NX20P3483
-	#define CONFIG_USBC_RETIMER_PS8802
-	#define CONFIG_USBC_RETIMER_PS8818
-	#define CONFIG_IO_EXPANDER_PORT_COUNT USBC_PORT_COUNT
-	#define CONFIG_USB_MUX_RUNTIME_CONFIG
-	/* USB-A config */
-	#define GPIO_USB1_ILIM_SEL IOEX_USB_A0_CHARGE_EN_L
-	#define GPIO_USB2_ILIM_SEL IOEX_USB_A1_CHARGE_EN_DB_L
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#define CONFIG_USBC_PPC_NX20P3483
+#define CONFIG_USBC_RETIMER_PS8802
+#define CONFIG_USBC_RETIMER_PS8818
+#define CONFIG_IO_EXPANDER_PORT_COUNT USBC_PORT_COUNT
+#define CONFIG_USB_MUX_RUNTIME_CONFIG
+/* USB-A config */
+#define GPIO_USB1_ILIM_SEL IOEX_USB_A0_CHARGE_EN_L
+#define GPIO_USB2_ILIM_SEL IOEX_USB_A1_CHARGE_EN_DB_L
+/* PS8818 RX Input Termination - default value */
+#define ZORK_PS8818_RX_INPUT_TERM PS8818_RX_INPUT_TERM_112_OHM
 #elif defined(VARIANT_ZORK_DALBOZ)
-	#define CONFIG_IO_EXPANDER_PORT_COUNT IOEX_PORT_COUNT
+#define CONFIG_IO_EXPANDER_PORT_COUNT IOEX_PORT_COUNT
 #endif
 
 /* USB-A config */
@@ -199,14 +208,13 @@
 #define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_CDP
 #define CONFIG_USB_PORT_POWER_SMART_INVERTED
 
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
 
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		65000
-#define PD_MAX_CURRENT_MA	3250
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 65000
+#define PD_MAX_CURRENT_MA 3250
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Round up 3250 max current to multiple of 128mA for ISL9241 AC prochot. */
 #define ZORK_AC_PROCHOT_CURRENT_MA 3328
@@ -216,8 +224,7 @@
  * CONFIG_CHARGER_LIMIT_* is not set, so there is no additional restriction on
  * Depthcharge to boot OS.
  */
-#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON			4
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON		50000
+#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 50000
 
 /* Increase length of history buffer for port80 messages. */
 #undef CONFIG_PORT80_HISTORY_LEN
@@ -227,33 +234,38 @@
 #undef CONFIG_UART_TX_BUF_SIZE
 #define CONFIG_UART_TX_BUF_SIZE 4096
 
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT0_0
-#define I2C_PORT_USBA0		NPCX_I2C_PORT0_0
-#define I2C_PORT_TCPC1		NPCX_I2C_PORT1_0
-#define I2C_PORT_USBA1		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_AP_MUX	NPCX_I2C_PORT3_0
-#define I2C_PORT_THERMAL_AP	NPCX_I2C_PORT4_1
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT5_0
-#define I2C_PORT_ACCEL		I2C_PORT_SENSOR
-#define I2C_PORT_EEPROM		I2C_PORT_SENSOR
-#define I2C_PORT_AP_AUDIO	NPCX_I2C_PORT6_1
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0
+#define I2C_PORT_USBA0 NPCX_I2C_PORT0_0
+#define I2C_PORT_TCPC1 NPCX_I2C_PORT1_0
+#define I2C_PORT_USBA1 NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_AP_MUX NPCX_I2C_PORT3_0
+#define I2C_PORT_THERMAL_AP NPCX_I2C_PORT4_1
+#define I2C_PORT_SENSOR NPCX_I2C_PORT5_0
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
+#define I2C_PORT_EEPROM I2C_PORT_SENSOR
+#define I2C_PORT_AP_AUDIO NPCX_I2C_PORT6_1
 
 #if defined(VARIANT_ZORK_TREMBYLE)
-	#define CONFIG_CHARGER_RUNTIME_CONFIG
-	#define I2C_PORT_BATTERY	NPCX_I2C_PORT2_0
-	#define I2C_PORT_CHARGER_V0	NPCX_I2C_PORT2_0
-	#define I2C_PORT_CHARGER_V1	NPCX_I2C_PORT4_1
-	#define I2C_PORT_AP_HDMI	NPCX_I2C_PORT7_0
+#define CONFIG_CHARGER_RUNTIME_CONFIG
+#define I2C_PORT_BATTERY NPCX_I2C_PORT2_0
+#define I2C_PORT_CHARGER_V0 NPCX_I2C_PORT2_0
+#define I2C_PORT_CHARGER_V1 NPCX_I2C_PORT4_1
+#define I2C_PORT_AP_HDMI NPCX_I2C_PORT7_0
 #elif defined(VARIANT_ZORK_DALBOZ)
-	#define I2C_PORT_BATTERY_V0	NPCX_I2C_PORT2_0
-	#define I2C_PORT_BATTERY_V1	NPCX_I2C_PORT7_0
-	#define I2C_PORT_CHARGER	NPCX_I2C_PORT2_0
+#define I2C_PORT_BATTERY_V0 NPCX_I2C_PORT2_0
+#define I2C_PORT_BATTERY_V1 NPCX_I2C_PORT7_0
+#define I2C_PORT_CHARGER NPCX_I2C_PORT2_0
 #endif
 
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 
-/* Sensors */
 #define CONFIG_MKBP_EVENT
+/* Host event is required to wake from sleep */
+#define CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT
+/* Required to enable runtime configuration */
+#define CONFIG_MKBP_EVENT_WAKEUP_MASK (BIT(EC_MKBP_EVENT_DP_ALT_MODE_ENTERED))
+
+/* Sensors */
 #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
 
 /* Thermal */
@@ -279,7 +291,6 @@
 #ifndef __ASSEMBLER__
 
 #include "gpio_signal.h"
-#include "math_util.h"
 #include "registers.h"
 
 enum power_signal {
@@ -297,11 +308,7 @@ enum fan_channel {
 };
 
 #ifdef VARIANT_ZORK_TREMBYLE
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 #endif
 
 enum sensor_id {
@@ -311,23 +318,6 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-/*
- * Matrix to rotate accelerators into the standard reference frame.  The default
- * is the identity which is correct for the reference design.  Variations of
- * Zork may need to change it for manufacturability.
- * For the lid:
- *  +x to the right
- *  +y up
- *  +z out of the page
- *
- * The principle axes of the body are aligned with the lid when the lid is in
- * the 180 degree position (open, flat).
- *
- * Boards within the Zork family may need to modify this definition at
- * board_init() time.
- */
-extern mat33_fp_t zork_base_standard_ref;
-
 extern const struct thermistor_info thermistor_info;
 
 /* Sensors without hardware FIFO are in forced mode */
diff --git a/baseboard/zork/build.mk b/baseboard/zork/build.mk
index 740252ac9a..6cf67a1a39 100644
--- a/baseboard/zork/build.mk
+++ b/baseboard/zork/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -8,6 +8,7 @@
 
 baseboard-y=baseboard.o
 baseboard-y+=cbi_ec_fw_config.o
+baseboard-y+=cbi_ssfc.o
 baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
 baseboard-$(VARIANT_ZORK_TREMBYLE)+=variant_trembyle.o
 baseboard-$(VARIANT_ZORK_DALBOZ)+=variant_dalboz.o
diff --git a/baseboard/zork/cbi_ec_fw_config.c b/baseboard/zork/cbi_ec_fw_config.c
index d8101855f7..555aeab9d7 100644
--- a/baseboard/zork/cbi_ec_fw_config.c
+++ b/baseboard/zork/cbi_ec_fw_config.c
@@ -1,10 +1,10 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include "common.h"
 #include "cbi_ec_fw_config.h"
+#include "common.h"
 #include "cros_board_info.h"
 
 /****************************************************************************
@@ -28,8 +28,7 @@ uint32_t get_cbi_fw_config(void)
  */
 enum ec_cfg_usb_db_type ec_config_get_usb_db(void)
 {
-	return ((get_cbi_fw_config() & EC_CFG_USB_DB_MASK)
-			>> EC_CFG_USB_DB_L);
+	return ((get_cbi_fw_config() & EC_CFG_USB_DB_MASK) >> EC_CFG_USB_DB_L);
 }
 
 /*
@@ -37,8 +36,7 @@ enum ec_cfg_usb_db_type ec_config_get_usb_db(void)
  */
 enum ec_cfg_usb_mb_type ec_config_get_usb_mb(void)
 {
-	return ((get_cbi_fw_config() & EC_CFG_USB_MB_MASK)
-			>> EC_CFG_USB_MB_L);
+	return ((get_cbi_fw_config() & EC_CFG_USB_MB_MASK) >> EC_CFG_USB_MB_L);
 }
 
 /*
@@ -46,35 +44,52 @@ enum ec_cfg_usb_mb_type ec_config_get_usb_mb(void)
  */
 enum ec_cfg_lid_accel_sensor_type ec_config_has_lid_accel_sensor(void)
 {
-	return ((get_cbi_fw_config() & EC_CFG_LID_ACCEL_SENSOR_MASK)
-			>> EC_CFG_LID_ACCEL_SENSOR_L);
+	return ((get_cbi_fw_config() & EC_CFG_LID_ACCEL_SENSOR_MASK) >>
+		EC_CFG_LID_ACCEL_SENSOR_L);
 }
 
 /*
  * ec_config_has_base_gyro_sensor() will return ec_cfg_base_gyro_sensor_type
  */
-enum ec_cfg_base_gyro_sensor_type ec_config_has_base_gyro_sensor(void)
+enum ec_ssfc_base_gyro_sensor ec_config_has_base_gyro_sensor(void)
 {
-	return ((get_cbi_fw_config() & EC_CFG_BASE_GYRO_SENSOR_MASK)
-			>> EC_CFG_BASE_GYRO_SENSOR_L);
+	return ((get_cbi_fw_config() & EC_CFG_BASE_GYRO_SENSOR_MASK) >>
+		EC_CFG_BASE_GYRO_SENSOR_L);
 }
 
 /*
  * ec_config_has_pwm_keyboard_backlight() will return 1 is present or 0
  */
-enum ec_cfg_pwm_keyboard_backlight_type ec_config_has_pwm_keyboard_backlight(
-									void)
+enum ec_cfg_pwm_keyboard_backlight_type
+ec_config_has_pwm_keyboard_backlight(void)
 {
-	return ((get_cbi_fw_config() & EC_CFG_PWM_KEYBOARD_BACKLIGHT_MASK)
-			>> EC_CFG_PWM_KEYBOARD_BACKLIGHT_L);
+	return ((get_cbi_fw_config() & EC_CFG_PWM_KEYBOARD_BACKLIGHT_MASK) >>
+		EC_CFG_PWM_KEYBOARD_BACKLIGHT_L);
 }
 
 /*
  * ec_config_has_lid_angle_tablet_mode() will return 1 is present or 0
  */
-enum ec_cfg_lid_angle_tablet_mode_type ec_config_has_lid_angle_tablet_mode(
-									void)
+enum ec_cfg_lid_angle_tablet_mode_type ec_config_has_lid_angle_tablet_mode(void)
+{
+	return ((get_cbi_fw_config() & EC_CFG_LID_ANGLE_TABLET_MODE_MASK) >>
+		EC_CFG_LID_ANGLE_TABLET_MODE_L);
+}
+
+/*
+ * ec_config_lte_present() will return 1 if present else 0.
+ */
+enum ec_cfg_lte_present_type ec_config_lte_present(void)
+{
+	return ((get_cbi_fw_config() & EC_CFG_LTE_PRESENT_MASK) >>
+		EC_CFG_LTE_PRESENT_L);
+}
+
+/*
+ * ec_config_keyboard_layout() will return keyboard layout type.
+ */
+enum ec_cfg_keyboard_layout_type ec_config_keyboard_layout(void)
 {
-	return ((get_cbi_fw_config() & EC_CFG_LID_ANGLE_TABLET_MODE_MASK)
-			>> EC_CFG_LID_ANGLE_TABLET_MODE_L);
+	return ((get_cbi_fw_config() & EC_CFG_KEYBOARD_LAYOUT_MASK) >>
+		EC_CFG_KEYBOARD_LAYOUT_L);
 }
diff --git a/baseboard/zork/cbi_ec_fw_config.h b/baseboard/zork/cbi_ec_fw_config.h
index 9222dd9f45..a73e4504bb 100644
--- a/baseboard/zork/cbi_ec_fw_config.h
+++ b/baseboard/zork/cbi_ec_fw_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,6 +6,8 @@
 #ifndef _ZORK_CBI_EC_FW_CONFIG__H_
 #define _ZORK_CBI_EC_FW_CONFIG__H_
 
+#include "cbi_ssfc.h"
+
 /****************************************************************************
  * CBI Zork EC FW Configuration
  */
@@ -17,11 +19,9 @@
  * get_cbi_ec_cfg_usb_db() will return the DB option number.
  * The option number will be defined in a variant or board level enumeration
  */
-#define EC_CFG_USB_DB_L				0
-#define EC_CFG_USB_DB_H				3
-#define EC_CFG_USB_DB_MASK \
-				GENMASK(EC_CFG_USB_DB_H,\
-					EC_CFG_USB_DB_L)
+#define EC_CFG_USB_DB_L 0
+#define EC_CFG_USB_DB_H 3
+#define EC_CFG_USB_DB_MASK GENMASK(EC_CFG_USB_DB_H, EC_CFG_USB_DB_L)
 
 /*
  * USB Main Board (4 bits)
@@ -29,11 +29,9 @@
  * get_cbi_ec_cfg_usb_mb() will return the MB option number.
  * The option number will be defined in a variant or board level enumeration
  */
-#define EC_CFG_USB_MB_L				4
-#define EC_CFG_USB_MB_H				7
-#define EC_CFG_USB_MB_MASK \
-				GENMASK(EC_CFG_USB_MB_H,\
-					EC_CFG_USB_MB_L)
+#define EC_CFG_USB_MB_L 4
+#define EC_CFG_USB_MB_H 7
+#define EC_CFG_USB_MB_MASK GENMASK(EC_CFG_USB_MB_H, EC_CFG_USB_MB_L)
 
 /*
  * Lid Accelerometer Sensor (3 bits)
@@ -45,27 +43,20 @@ enum ec_cfg_lid_accel_sensor_type {
 	LID_ACCEL_KX022 = 1,
 	LID_ACCEL_LIS2DWL = 2,
 };
-#define EC_CFG_LID_ACCEL_SENSOR_L		8
-#define EC_CFG_LID_ACCEL_SENSOR_H		10
-#define EC_CFG_LID_ACCEL_SENSOR_MASK	\
-				GENMASK(EC_CFG_LID_ACCEL_SENSOR_H,\
-					EC_CFG_LID_ACCEL_SENSOR_L)
+#define EC_CFG_LID_ACCEL_SENSOR_L 8
+#define EC_CFG_LID_ACCEL_SENSOR_H 10
+#define EC_CFG_LID_ACCEL_SENSOR_MASK \
+	GENMASK(EC_CFG_LID_ACCEL_SENSOR_H, EC_CFG_LID_ACCEL_SENSOR_L)
 
 /*
  * Base Gyro Sensor (3 bits)
  *
  * ec_config_has_base_gyro_sensor() will return ec_cfg_base_gyro_sensor_type
  */
-enum ec_cfg_base_gyro_sensor_type {
-	BASE_GYRO_NONE = 0,
-	BASE_GYRO_BMI160 = 1,
-	BASE_GYRO_LSM6DSM = 2,
-};
-#define EC_CFG_BASE_GYRO_SENSOR_L		11
-#define EC_CFG_BASE_GYRO_SENSOR_H		13
-#define EC_CFG_BASE_GYRO_SENSOR_MASK	\
-				GENMASK(EC_CFG_BASE_GYRO_SENSOR_H,\
-					EC_CFG_BASE_GYRO_SENSOR_L)
+#define EC_CFG_BASE_GYRO_SENSOR_L 11
+#define EC_CFG_BASE_GYRO_SENSOR_H 13
+#define EC_CFG_BASE_GYRO_SENSOR_MASK \
+	GENMASK(EC_CFG_BASE_GYRO_SENSOR_H, EC_CFG_BASE_GYRO_SENSOR_L)
 
 /*
  * PWM Keyboard Backlight (1 bit)
@@ -76,11 +67,11 @@ enum ec_cfg_pwm_keyboard_backlight_type {
 	PWM_KEYBOARD_BACKLIGHT_NO = 0,
 	PWM_KEYBOARD_BACKLIGHT_YES = 1,
 };
-#define EC_CFG_PWM_KEYBOARD_BACKLIGHT_L		14
-#define EC_CFG_PWM_KEYBOARD_BACKLIGHT_H		14
-#define EC_CFG_PWM_KEYBOARD_BACKLIGHT_MASK \
-				GENMASK(EC_CFG_PWM_KEYBOARD_BACKLIGHT_H,\
-					EC_CFG_PWM_KEYBOARD_BACKLIGHT_L)
+#define EC_CFG_PWM_KEYBOARD_BACKLIGHT_L 14
+#define EC_CFG_PWM_KEYBOARD_BACKLIGHT_H 14
+#define EC_CFG_PWM_KEYBOARD_BACKLIGHT_MASK       \
+	GENMASK(EC_CFG_PWM_KEYBOARD_BACKLIGHT_H, \
+		EC_CFG_PWM_KEYBOARD_BACKLIGHT_L)
 
 /*
  * Lid Angle Tablet Mode (1 bit)
@@ -91,21 +82,49 @@ enum ec_cfg_lid_angle_tablet_mode_type {
 	LID_ANGLE_TABLET_MODE_NO = 0,
 	LID_ANGLE_TABLET_MODE_YES = 1,
 };
-#define EC_CFG_LID_ANGLE_TABLET_MODE_L		15
-#define EC_CFG_LID_ANGLE_TABLET_MODE_H		15
+#define EC_CFG_LID_ANGLE_TABLET_MODE_L 15
+#define EC_CFG_LID_ANGLE_TABLET_MODE_H 15
 #define EC_CFG_LID_ANGLE_TABLET_MODE_MASK \
-				GENMASK(EC_CFG_LID_ANGLE_TABLET_MODE_H,\
-					EC_CFG_LID_ANGLE_TABLET_MODE_L)
+	GENMASK(EC_CFG_LID_ANGLE_TABLET_MODE_H, EC_CFG_LID_ANGLE_TABLET_MODE_L)
 
+/*
+ * LTE Modem Present (1 bit)
+ *
+ * ec_config_lte_present() will return 1 if present else 0.
+ */
+enum ec_cfg_lte_present_type {
+	LTE_NONE = 0,
+	LTE_PRESENT = 1,
+};
+#define EC_CFG_LTE_PRESENT_L 29
+#define EC_CFG_LTE_PRESENT_H 29
+#define EC_CFG_LTE_PRESENT_MASK \
+	GENMASK(EC_CFG_LTE_PRESENT_H, EC_CFG_LTE_PRESENT_L)
+
+/*
+ * Keyboard Layout (2 bit)
+ *
+ * ec_config_keyboard_layout() will return keyboard layout type.
+ */
+enum ec_cfg_keyboard_layout_type {
+	KB_LAYOUT_DEFAULT = 0,
+	KB_LAYOUT_1 = 1,
+};
+#define EC_CFG_KEYBOARD_LAYOUT_L 30
+#define EC_CFG_KEYBOARD_LAYOUT_H 31
+#define EC_CFG_KEYBOARD_LAYOUT_MASK \
+	GENMASK(EC_CFG_KEYBOARD_LAYOUT_H, EC_CFG_KEYBOARD_LAYOUT_L)
 
 uint32_t get_cbi_fw_config(void);
 enum ec_cfg_usb_db_type ec_config_get_usb_db(void);
 enum ec_cfg_usb_mb_type ec_config_get_usb_mb(void);
 enum ec_cfg_lid_accel_sensor_type ec_config_has_lid_accel_sensor(void);
-enum ec_cfg_base_gyro_sensor_type ec_config_has_base_gyro_sensor(void);
-enum ec_cfg_pwm_keyboard_backlight_type ec_config_has_pwm_keyboard_backlight(
-									void);
-enum ec_cfg_lid_angle_tablet_mode_type ec_config_has_lid_angle_tablet_mode(
-									void);
+enum ec_ssfc_base_gyro_sensor ec_config_has_base_gyro_sensor(void);
+enum ec_cfg_pwm_keyboard_backlight_type
+ec_config_has_pwm_keyboard_backlight(void);
+enum ec_cfg_lid_angle_tablet_mode_type
+ec_config_has_lid_angle_tablet_mode(void);
+enum ec_cfg_lte_present_type ec_config_lte_present(void);
+enum ec_cfg_keyboard_layout_type ec_config_keyboard_layout(void);
 
 #endif /* _ZORK_CBI_EC_FW_CONFIG__H_ */
diff --git a/baseboard/zork/cbi_ssfc.c b/baseboard/zork/cbi_ssfc.c
new file mode 100644
index 0000000000..9cc2fdcef3
--- /dev/null
+++ b/baseboard/zork/cbi_ssfc.c
@@ -0,0 +1,47 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi_ssfc.h"
+#include "common.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "hooks.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+/* Cache SSFC on init since we don't expect it to change in runtime */
+static uint32_t cached_ssfc;
+
+static void cbi_ssfc_init(void)
+{
+	if (cbi_get_ssfc(&cached_ssfc) != EC_SUCCESS)
+		/* Default to 0 when CBI isn't populated */
+		cached_ssfc = 0;
+
+	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc);
+}
+DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
+
+enum ec_ssfc_base_gyro_sensor get_cbi_ssfc_base_sensor(void)
+{
+	return (cached_ssfc & SSFC_BASE_GYRO_MASK) >> SSFC_BASE_GYRO_OFFSET;
+}
+
+enum ec_ssfc_spkr_auto_mode get_cbi_ssfc_spkr_auto_mode(void)
+{
+	return (cached_ssfc & SSFC_SPKR_AUTO_MODE_MASK) >>
+	       SSFC_SPKR_AUTO_MODE_OFFSET;
+}
+
+enum ec_ssfc_edp_phy_alt_tuning get_cbi_ssfc_edp_phy_alt_tuning(void)
+{
+	return (cached_ssfc & SSFC_EDP_PHY_ALT_TUNING_MASK) >>
+	       SSFC_EDP_PHY_ALT_TUNING_OFFSET;
+}
+
+enum ec_ssfc_c1_mux get_cbi_ssfc_c1_mux(void)
+{
+	return (cached_ssfc & SSFC_C1_MUX_MASK) >> SSFC_C1_MUX_OFFSET;
+}
diff --git a/baseboard/zork/cbi_ssfc.h b/baseboard/zork/cbi_ssfc.h
new file mode 100644
index 0000000000..95bf5ba6e4
--- /dev/null
+++ b/baseboard/zork/cbi_ssfc.h
@@ -0,0 +1,80 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _ZORK_CBI_SSFC__H_
+#define _ZORK_CBI_SSFC__H_
+
+#include "stdint.h"
+
+/****************************************************************************
+ * Zork CBI Second Source Factory Cache
+ */
+
+/*
+ * Base Sensor (Bits 0-2)
+ */
+enum ec_ssfc_base_gyro_sensor {
+	SSFC_BASE_GYRO_NONE = 0,
+	SSFC_BASE_GYRO_BMI160 = 1,
+	SSFC_BASE_GYRO_LSM6DSM = 2,
+	SSFC_BASE_GYRO_ICM426XX = 3,
+	SSFC_BASE_GYRO_ICM42607 = 4,
+};
+#define SSFC_BASE_GYRO_OFFSET 0
+#define SSFC_BASE_GYRO_MASK GENMASK(2, 0)
+
+enum ec_ssfc_spkr_auto_mode {
+	SSFC_SPKR_AUTO_MODE_OFF = 0,
+	SSFC_SPKR_AUTO_MODE_ON = 1,
+};
+#define SSFC_SPKR_AUTO_MODE_OFFSET 3
+#define SSFC_SPKR_AUTO_MODE_MASK GENMASK(3, 3)
+
+/*
+ * eDP PHY Alternate Tuning (Bits 4-5)
+ */
+enum ec_ssfc_edp_phy_alt_tuning {
+	SSFC_EDP_PHY_ALT_TUNING_0 = 0,
+	SSFC_EDP_PHY_ALT_TUNING_1 = 1,
+	SSFC_EDP_PHY_ALT_TUNING_2 = 2,
+	SSFC_EDP_PHY_ALT_TUNING_3 = 3,
+};
+#define SSFC_EDP_PHY_ALT_TUNING_OFFSET 4
+#define SSFC_EDP_PHY_ALT_TUNING_MASK GENMASK(5, 4)
+
+/*
+ * TypeC port 1 secondary MUX (Bits 6-7)
+ */
+enum ec_ssfc_c1_mux {
+	SSFC_C1_MUX_NONE = 0,
+	SSFC_C1_MUX_TUSB544 = 1,
+	SSFC_C1_MUX_PS8818 = 2,
+};
+#define SSFC_C1_MUX_OFFSET 6
+#define SSFC_C1_MUX_MASK GENMASK(7, 6)
+
+/**
+ * Get the Base sensor type from SSFC_CONFIG.
+ *
+ * @return the Base sensor board type.
+ */
+enum ec_ssfc_base_gyro_sensor get_cbi_ssfc_base_sensor(void);
+
+/**
+ * Get whether speaker amp auto mode is enabled from SSFC.
+ */
+enum ec_ssfc_spkr_auto_mode get_cbi_ssfc_spkr_auto_mode(void);
+
+/**
+ * Get the eDP PHY alternate tuning from SSFC.
+ */
+enum ec_ssfc_edp_phy_alt_tuning get_cbi_ssfc_edp_phy_alt_tuning(void);
+
+/**
+ * Get the C1 usb mux from SSFC.
+ */
+enum ec_ssfc_c1_mux get_cbi_ssfc_c1_mux(void);
+
+#endif /* _ZORK_CBI_SSFC__H_ */
diff --git a/baseboard/zork/usb_pd_policy.c b/baseboard/zork/usb_pd_policy.c
index 513772213e..aeca706eb2 100644
--- a/baseboard/zork/usb_pd_policy.c
+++ b/baseboard/zork/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,8 +18,8 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
@@ -39,11 +39,6 @@ void pd_power_supply_reset(int port)
 			pd_set_vbus_discharge(port, 1);
 	}
 
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	/* Give back the current quota we are no longer using */
-	charge_manager_source_port(port, 0);
-#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
-
 	/* Notify host of power info change. */
 	pd_send_host_event(PD_EVENT_POWER_CHANGE);
 }
@@ -65,11 +60,6 @@ int pd_set_power_supply_ready(int port)
 	if (rv)
 		return rv;
 
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	/* Ensure we advertise the proper available current quota */
-	charge_manager_source_port(port, 1);
-#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
-
 	/* Notify host of power info change. */
 	pd_send_host_event(PD_EVENT_POWER_CHANGE);
 
@@ -80,83 +70,3 @@ int board_vbus_source_enabled(int port)
 {
 	return ppc_is_sourcing_vbus(port);
 }
-
-/* ----------------- Vendor Defined Messages ------------------ */
-#ifdef CONFIG_USB_PD_ALT_MODE_DFP
-mux_state_t svdm_dp_mux_mode(int port)
-{
-	int mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]);
-	int pin_mode = pd_dfp_dp_get_pin_mode(port, dp_status[port]);
-	/*
-	 * Multi-function operation is only allowed if that pin config is
-	 * supported.
-	 */
-	if ((pin_mode & MODE_DP_PIN_MF_MASK) && mf_pref)
-		return USB_PD_MUX_DOCK;
-	else
-		return USB_PD_MUX_DP_ENABLED;
-}
-
-__override int svdm_dp_config(int port, uint32_t *payload)
-{
-	int opos = pd_alt_mode(port, TCPC_TX_SOP, USB_SID_DISPLAYPORT);
-	int mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]);
-	int pin_mode = pd_dfp_dp_get_pin_mode(port, dp_status[port]);
-	mux_state_t mux_mode = svdm_dp_mux_mode(port);
-
-	if (!pin_mode)
-		return 0;
-
-	CPRINTS("pin_mode: %x, mf: %d, mux: %d", pin_mode, mf_pref, mux_mode);
-
-	/*
-	 * Place the USB Type-C pins that are to be re-configured to DisplayPort
-	 * Configuration into the Safe state. For USB_PD_MUX_DOCK, the
-	 * superspeed signals can remain connected. For USB_PD_MUX_DP_ENABLED,
-	 * disconnect the superspeed signals here, before the pins are
-	 * re-configured to DisplayPort (in svdm_dp_post_config, when we receive
-	 * the config ack).
-	 */
-	if (mux_mode == USB_PD_MUX_DP_ENABLED)
-		usb_mux_set(port, USB_PD_MUX_NONE, USB_SWITCH_CONNECT,
-			    pd_get_polarity(port));
-
-	payload[0] = VDO(USB_SID_DISPLAYPORT, 1,
-			 CMD_DP_CONFIG | VDO_OPOS(opos));
-	payload[1] = VDO_DP_CFG(pin_mode,      /* pin mode */
-				1,             /* DPv1.3 signaling */
-				2);            /* UFP connected */
-	return 2;
-};
-
-__override void svdm_dp_post_config(int port)
-{
-	/* Connect the SBU and USB lines to the connector. */
-	ppc_set_sbu(port, 1);
-	usb_mux_set(port, svdm_dp_mux_mode(port), USB_SWITCH_CONNECT,
-		    pd_get_polarity(port));
-
-	dp_flags[port] |= DP_FLAGS_DP_ON;
-	if (!(dp_flags[port] & DP_FLAGS_HPD_HI_PENDING))
-		return;
-
-	gpio_or_ioex_set_level(PORT_TO_HPD(port), 1);
-
-	/* set the minimum time delay (2ms) for the next HPD IRQ */
-	svdm_hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
-
-	usb_mux_hpd_update(port, 1, 0);
-}
-
-__override void svdm_exit_dp_mode(int port)
-{
-	dp_flags[port] = 0;
-	dp_status[port] = 0;
-
-	usb_mux_set(port, USB_PD_MUX_NONE, USB_SWITCH_CONNECT,
-		    pd_get_polarity(port));
-	gpio_or_ioex_set_level(PORT_TO_HPD(port), 0);
-
-	usb_mux_hpd_update(port, 0, 0);
-}
-#endif /* CONFIG_USB_PD_ALT_MODE_DFP */
diff --git a/baseboard/zork/variant_dalboz.c b/baseboard/zork/variant_dalboz.c
index 6e76034ced..599f29618b 100644
--- a/baseboard/zork/variant_dalboz.c
+++ b/baseboard/zork/variant_dalboz.c
@@ -1,10 +1,9 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "charger.h"
 #include "chipset.h"
 #include "common.h"
@@ -15,7 +14,7 @@
 #include "i2c.h"
 #include "power.h"
 #include "temp_sensor.h"
-#include "thermistor.h"
+#include "temp_sensor/thermistor.h"
 
 const struct power_signal_info power_signal_list[] = {
 	[X86_SLP_S3_N] = {
@@ -57,6 +56,11 @@ int board_get_temp(int idx, int *temp_k)
 		if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
 			return EC_ERROR_NOT_POWERED;
 
+		/* adc power not ready when transition to S5 */
+		if (chipset_in_or_transitioning_to_state(
+			    CHIPSET_STATE_SOFT_OFF))
+			return EC_ERROR_NOT_POWERED;
+
 		channel = ADC_TEMP_SENSOR_SOC;
 		break;
 	default:
@@ -112,6 +116,37 @@ const struct temp_sensor_t temp_sensors[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
+__overridable struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT] = {
+	[TEMP_SENSOR_CHARGER] = {
+		.temp_host = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(90),
+			[EC_TEMP_THRESH_HALT] = C_TO_K(92),
+		},
+		.temp_host_release = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
+		}
+	},
+	[TEMP_SENSOR_SOC] = {
+		.temp_host = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(90),
+			[EC_TEMP_THRESH_HALT] = C_TO_K(92),
+		},
+		.temp_host_release = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
+		}
+	},
+	[TEMP_SENSOR_CPU] = {
+		.temp_host = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(90),
+			[EC_TEMP_THRESH_HALT] = C_TO_K(92),
+		},
+		.temp_host_release = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
+		}
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
+
 const struct i2c_port_t i2c_ports[] = {
 	{
 		.name = "tcpc0",
diff --git a/baseboard/zork/variant_trembyle.c b/baseboard/zork/variant_trembyle.c
index 32151cf0f9..4542ea562c 100644
--- a/baseboard/zork/variant_trembyle.c
+++ b/baseboard/zork/variant_trembyle.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,10 +9,10 @@
 #include "console.h"
 #include "driver/bc12/pi3usb9201.h"
 #include "driver/charger/isl9241.h"
-#include "driver/ppc/aoz1380.h"
+#include "driver/ppc/aoz1380_public.h"
 #include "driver/ppc/nx20p348x.h"
 #include "driver/retimer/ps8802.h"
-#include "driver/retimer/ps8818.h"
+#include "driver/retimer/ps8818_public.h"
 #include "driver/retimer/tusb544.h"
 #include "driver/tcpm/nct38xx.h"
 #include "driver/usb_mux/amd_fp5.h"
@@ -28,8 +28,8 @@
 #include "usb_pd_tcpm.h"
 #include "usbc_ppc.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 const struct i2c_port_t i2c_ports[] = {
 	{
@@ -160,8 +160,7 @@ __overridable void ppc_interrupt(enum gpio_signal signal)
 
 int board_set_active_charge_port(int port)
 {
-	int is_valid_port = (port >= 0 &&
-			     port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	int i;
 
 	if (port == CHARGE_PORT_NONE) {
@@ -182,7 +181,6 @@ int board_set_active_charge_port(int port)
 		return EC_ERROR_INVAL;
 	}
 
-
 	/* Check if the port is sourcing VBUS. */
 	if (ppc_is_sourcing_vbus(port)) {
 		CPRINTFUSB("Skip enable C%d", port);
@@ -264,27 +262,33 @@ const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
 
-static void reset_pd_port(int port, enum gpio_signal reset_gpio_l,
-			  int hold_delay, int finish_delay)
+static void reset_nct38xx_port(int port)
 {
+	enum gpio_signal reset_gpio_l;
+
+	if (port == USBC_PORT_C0)
+		reset_gpio_l = GPIO_USB_C0_TCPC_RST_L;
+	else if (port == USBC_PORT_C1)
+		reset_gpio_l = GPIO_USB_C1_TCPC_RST_L;
+	else
+		/* Invalid port: do nothing */
+		return;
+
 	gpio_set_level(reset_gpio_l, 0);
-	msleep(hold_delay);
+	msleep(NCT38XX_RESET_HOLD_DELAY_MS);
 	gpio_set_level(reset_gpio_l, 1);
-	if (finish_delay)
-		msleep(finish_delay);
+	nct38xx_reset_notify(port);
+	if (NCT3807_RESET_POST_DELAY_MS != 0)
+		msleep(NCT3807_RESET_POST_DELAY_MS);
 }
 
 void board_reset_pd_mcu(void)
 {
 	/* Reset TCPC0 */
-	reset_pd_port(USBC_PORT_C0, GPIO_USB_C0_TCPC_RST_L,
-		      NCT38XX_RESET_HOLD_DELAY_MS,
-		      NCT38XX_RESET_POST_DELAY_MS);
+	reset_nct38xx_port(USBC_PORT_C0);
 
 	/* Reset TCPC1 */
-	reset_pd_port(USBC_PORT_C1, GPIO_USB_C1_TCPC_RST_L,
-		      NCT38XX_RESET_HOLD_DELAY_MS,
-		      NCT38XX_RESET_POST_DELAY_MS);
+	reset_nct38xx_port(USBC_PORT_C1);
 }
 
 uint16_t tcpc_get_alert_status(void)
@@ -326,18 +330,15 @@ void tcpc_alert_event(enum gpio_signal signal)
 	schedule_deferred_pd_interrupt(port);
 }
 
-
 int board_pd_set_frs_enable(int port, int enable)
 {
 	int rv = EC_SUCCESS;
 
 	/* Use the TCPC to enable fast switch when FRS included */
 	if (port == USBC_PORT_C0) {
-		rv = ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN,
-				    !!enable);
+		rv = ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN, !!enable);
 	} else {
-		rv = ioex_set_level(IOEX_USB_C1_TCPC_FASTSW_CTL_EN,
-				    !!enable);
+		rv = ioex_set_level(IOEX_USB_C1_TCPC_FASTSW_CTL_EN, !!enable);
 	}
 
 	return rv;
@@ -347,11 +348,11 @@ void bc12_interrupt(enum gpio_signal signal)
 {
 	switch (signal) {
 	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
 		break;
 
 	case GPIO_USB_C1_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12, 0);
+		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
 		break;
 
 	default:
@@ -366,12 +367,12 @@ void bc12_interrupt(enum gpio_signal signal)
 struct ioexpander_config_t ioex_config[] = {
 	[USBC_PORT_C0] = {
 		.i2c_host_port = I2C_PORT_TCPC0,
-		.i2c_slave_addr = NCT38XX_I2C_ADDR1_1_FLAGS,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
 		.drv = &nct38xx_ioexpander_drv,
 	},
 	[USBC_PORT_C1] = {
 		.i2c_host_port = I2C_PORT_TCPC1,
-		.i2c_slave_addr = NCT38XX_I2C_ADDR1_1_FLAGS,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
 		.drv = &nct38xx_ioexpander_drv,
 	},
 };
@@ -386,8 +387,7 @@ BUILD_ASSERT(CONFIG_IO_EXPANDER_PORT_COUNT == USBC_PORT_COUNT);
  * PS8802 set mux board tuning.
  * Adds in board specific gain and DP lane count configuration
  */
-static int board_ps8802_mux_set(const struct usb_mux *me,
-				mux_state_t mux_state)
+static int board_ps8802_mux_set(const struct usb_mux *me, mux_state_t mux_state)
 {
 	int rv = EC_SUCCESS;
 
@@ -399,11 +399,10 @@ static int board_ps8802_mux_set(const struct usb_mux *me,
 	/* USB specific config */
 	if (mux_state & USB_PD_MUX_USB_ENABLED) {
 		/* Boost the USB gain */
-		rv = ps8802_i2c_field_update16(me,
-					PS8802_REG_PAGE2,
-					PS8802_REG2_USB_SSEQ_LEVEL,
-					PS8802_USBEQ_LEVEL_UP_MASK,
-					PS8802_USBEQ_LEVEL_UP_19DB);
+		rv = ps8802_i2c_field_update16(me, PS8802_REG_PAGE2,
+					       PS8802_REG2_USB_SSEQ_LEVEL,
+					       PS8802_USBEQ_LEVEL_UP_MASK,
+					       PS8802_USBEQ_LEVEL_UP_19DB);
 		if (rv)
 			return rv;
 	}
@@ -411,19 +410,12 @@ static int board_ps8802_mux_set(const struct usb_mux *me,
 	/* DP specific config */
 	if (mux_state & USB_PD_MUX_DP_ENABLED) {
 		/* Boost the DP gain */
-		rv = ps8802_i2c_field_update8(me,
-					PS8802_REG_PAGE2,
-					PS8802_REG2_DPEQ_LEVEL,
-					PS8802_DPEQ_LEVEL_UP_MASK,
-					PS8802_DPEQ_LEVEL_UP_19DB);
+		rv = ps8802_i2c_field_update8(me, PS8802_REG_PAGE2,
+					      PS8802_REG2_DPEQ_LEVEL,
+					      PS8802_DPEQ_LEVEL_UP_MASK,
+					      PS8802_DPEQ_LEVEL_UP_19DB);
 		if (rv)
 			return rv;
-
-		/* Enable IN_HPD on the DB */
-		gpio_or_ioex_set_level(board_usbc1_retimer_inhpd, 1);
-	} else {
-		/* Disable IN_HPD on the DB */
-		gpio_or_ioex_set_level(board_usbc1_retimer_inhpd, 0);
 	}
 
 	return rv;
@@ -433,43 +425,46 @@ static int board_ps8802_mux_set(const struct usb_mux *me,
  * PS8818 set mux board tuning.
  * Adds in board specific gain and DP lane count configuration
  */
-static int board_ps8818_mux_set(const struct usb_mux *me,
-				mux_state_t mux_state)
+static int board_ps8818_mux_set(const struct usb_mux *me, mux_state_t mux_state)
 {
 	int rv = EC_SUCCESS;
 
 	/* USB specific config */
 	if (mux_state & USB_PD_MUX_USB_ENABLED) {
 		/* Boost the USB gain */
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX1EQ_10G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_19DB);
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_APTX1EQ_10G_LEVEL,
+					      PS8818_EQ_LEVEL_UP_MASK,
+					      PS8818_EQ_LEVEL_UP_19DB);
+		if (rv)
+			return rv;
+
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_APTX2EQ_10G_LEVEL,
+					      PS8818_EQ_LEVEL_UP_MASK,
+					      PS8818_EQ_LEVEL_UP_19DB);
 		if (rv)
 			return rv;
 
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX2EQ_10G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_19DB);
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_APTX1EQ_5G_LEVEL,
+					      PS8818_EQ_LEVEL_UP_MASK,
+					      PS8818_EQ_LEVEL_UP_19DB);
 		if (rv)
 			return rv;
 
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX1EQ_5G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_19DB);
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_APTX2EQ_5G_LEVEL,
+					      PS8818_EQ_LEVEL_UP_MASK,
+					      PS8818_EQ_LEVEL_UP_19DB);
 		if (rv)
 			return rv;
 
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX2EQ_5G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_19DB);
+		/* Set the RX input termination */
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_RX_PHY,
+					      PS8818_RX_INPUT_TERM_MASK,
+					      ZORK_PS8818_RX_INPUT_TERM);
 		if (rv)
 			return rv;
 	}
@@ -477,11 +472,10 @@ static int board_ps8818_mux_set(const struct usb_mux *me,
 	/* DP specific config */
 	if (mux_state & USB_PD_MUX_DP_ENABLED) {
 		/* Boost the DP gain */
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_DPEQ_LEVEL,
-					PS8818_DPEQ_LEVEL_UP_MASK,
-					PS8818_DPEQ_LEVEL_UP_19DB);
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_DPEQ_LEVEL,
+					      PS8818_DPEQ_LEVEL_UP_MASK,
+					      PS8818_DPEQ_LEVEL_UP_19DB);
 		if (rv)
 			return rv;
 
@@ -495,7 +489,7 @@ static int board_ps8818_mux_set(const struct usb_mux *me,
 	return rv;
 }
 
-const struct usb_mux usbc1_ps8802 = {
+struct usb_mux usbc1_ps8802 = {
 	.usb_port = USBC_PORT_C1,
 	.i2c_port = I2C_PORT_TCPC1,
 	.i2c_addr_flags = PS8802_I2C_ADDR_FLAGS,
@@ -505,7 +499,7 @@ const struct usb_mux usbc1_ps8802 = {
 const struct usb_mux usbc1_ps8818 = {
 	.usb_port = USBC_PORT_C1,
 	.i2c_port = I2C_PORT_TCPC1,
-	.i2c_addr_flags = PS8818_I2C_ADDR_FLAGS,
+	.i2c_addr_flags = PS8818_I2C_ADDR0_FLAGS,
 	.driver = &ps8818_usb_retimer_driver,
 	.board_set = &board_ps8818_mux_set,
 };
diff --git a/board/adl_ish_lite b/board/adl_ish_lite
new file mode 120000
index 0000000000..e43fd15937
--- /dev/null
+++ b/board/adl_ish_lite
@@ -0,0 +1 @@
+tglrvp_ish
\ No newline at end of file
diff --git a/board/adlrvpm_ite/board.c b/board/adlrvpm_ite/board.c
new file mode 120000
index 0000000000..ea1b98c873
--- /dev/null
+++ b/board/adlrvpm_ite/board.c
@@ -0,0 +1 @@
+../adlrvpp_ite/board.c
\ No newline at end of file
diff --git a/board/adlrvpm_ite/board.h b/board/adlrvpm_ite/board.h
new file mode 100644
index 0000000000..37662a5d52
--- /dev/null
+++ b/board/adlrvpm_ite/board.h
@@ -0,0 +1,102 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel ADL-P-RVP-ITE board-specific configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* ITE EC variant */
+#define VARIANT_INTELRVP_EC_IT8320
+
+#include "adlrvp.h"
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+#define GPIO_AC_PRESENT GPIO_BC_ACOK_EC
+#define GPIO_EC_INT_L GPIO_EC_PCH_MKBP_INT_ODL_EC
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW_EC
+#define GPIO_LID_OPEN GPIO_SMC_LID
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE_EC
+#define GPIO_PCH_WAKE_L GPIO_PCH_WAKE_N
+#define GPIO_PCH_PWRBTN_L GPIO_PM_PWRBTN_N_EC
+#define GPIO_PCH_RSMRST_L GPIO_PM_RSMRST_EC
+#define GPIO_PCH_SLP_S0_L GPIO_PCH_SLP_S0_N
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_R_L
+#define GPIO_PG_EC_DSW_PWROK GPIO_VCCPDSW_3P3_EC
+#define GPIO_POWER_BUTTON_L GPIO_MECH_PWR_BTN_ODL
+#define GPIO_CPU_PROCHOT GPIO_PROCHOT_EC
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL_EC
+#define GPIO_WP_L GPIO_EC_WP_ODL
+#define GPIO_VOLUME_UP_L GPIO_VOLUME_UP
+#define GPIO_VOLUME_DOWN_L GPIO_VOL_DN_EC_R
+#define GPIO_DC_JACK_PRESENT GPIO_STD_ADP_PRSNT
+#define GPIO_ESPI_RESET_L GPIO_ESPI_RST_R
+#define GPIO_UART1_RX GPIO_UART_SERVO_TX_EC_RX
+#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BAT_DET_EC
+#define GPIO_BAT_LED_RED_L GPIO_LED_1_L_EC
+#define GPIO_PWR_LED_WHITE_L GPIO_LED_2_L_EC
+#define GPIO_SLP_SUS_L GPIO_PM_SLP_SUS_EC
+#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_PWRGD_EC
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_ALL_SYS_PWRGD_EC
+#define GPIO_PCH_DSW_PWROK GPIO_DSW_PWROK_EC
+#define GPIO_EN_PP3300_A GPIO_EC_DS3
+#define GPIO_TABLET_MODE_L GPIO_SLATE_MODE_INDICATION
+
+/* I2C ports & Configs */
+#define CONFIG_IT83XX_SMCLK2_ON_GPC7
+
+#define I2C_PORT_CHARGER IT83XX_I2C_CH_B
+
+/* Battery */
+#define I2C_PORT_BATTERY IT83XX_I2C_CH_B
+
+/* Board ID */
+#define I2C_PORT_PCA9555_BOARD_ID_GPIO IT83XX_I2C_CH_B
+
+/* Port 80 */
+#define I2C_PORT_PORT80 IT83XX_I2C_CH_B
+
+/* USB-C I2C */
+#define I2C_PORT_TYPEC_0 IT83XX_I2C_CH_C
+#define I2C_PORT_TYPEC_1 IT83XX_I2C_CH_F
+#if defined(HAS_TASK_PD_C2)
+#define I2C_PORT_TYPEC_2 IT83XX_I2C_CH_E
+#define I2C_PORT_TYPEC_3 IT83XX_I2C_CH_D
+#endif
+
+/* TCPC */
+#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP
+#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1
+
+/* Config Fan */
+#define GPIO_FAN_POWER_EN GPIO_EC_THRM_SEN_PWRGATE_N
+#define GPIO_ALL_SYS_PWRGD GPIO_ALL_SYS_PWRGD_EC
+
+/* Increase EC speed */
+#undef PLL_CLOCK
+#define PLL_CLOCK 96000000
+
+#ifndef __ASSEMBLER__
+
+enum adlrvp_i2c_channel {
+	I2C_CHAN_FLASH,
+	I2C_CHAN_BATT_CHG,
+	I2C_CHAN_TYPEC_0,
+	I2C_CHAN_TYPEC_1,
+#if defined(HAS_TASK_PD_C2)
+	I2C_CHAN_TYPEC_2,
+	I2C_CHAN_TYPEC_3,
+#endif
+	I2C_CHAN_COUNT,
+};
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/adlrvpm_ite/build.mk b/board/adlrvpm_ite/build.mk
new file mode 120000
index 0000000000..ceffb75d7e
--- /dev/null
+++ b/board/adlrvpm_ite/build.mk
@@ -0,0 +1 @@
+../adlrvpp_ite/build.mk
\ No newline at end of file
diff --git a/board/adlrvpm_ite/ec.tasklist b/board/adlrvpm_ite/ec.tasklist
new file mode 100644
index 0000000000..b0afc9e9a7
--- /dev/null
+++ b/board/adlrvpm_ite/ec.tasklist
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Intel ADL-M-RVP-ITE board-specific configuration.
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/adlrvpm_ite/gpio.inc b/board/adlrvpm_ite/gpio.inc
new file mode 120000
index 0000000000..23611687c6
--- /dev/null
+++ b/board/adlrvpm_ite/gpio.inc
@@ -0,0 +1 @@
+../adlrvpp_ite/gpio.inc
\ No newline at end of file
diff --git a/board/adlrvpm_ite/vif_override.xml b/board/adlrvpm_ite/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/adlrvpm_ite/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/adlrvpp_ite/board.c b/board/adlrvpp_ite/board.c
new file mode 100644
index 0000000000..63bbbfd78c
--- /dev/null
+++ b/board/adlrvpp_ite/board.c
@@ -0,0 +1,155 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel ADLRVP-ITE board-specific configuration */
+#include "button.h"
+#include "fan.h"
+#include "fusb302.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "i2c_bitbang.h"
+#include "it83xx_pd.h"
+#include "lid_switch.h"
+#include "pca9675.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "switch.h"
+#include "tablet_mode.h"
+#include "uart.h"
+#include "usb_pd_tbt.h"
+#include "usb_pd_tcpm.h"
+#include "util.h"
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/******************************************************************************/
+/* I2C ports */
+const struct i2c_port_t i2c_ports[] = {
+	[I2C_CHAN_FLASH] = {
+		.name = "ec_flash",
+		.port = IT83XX_I2C_CH_A,
+		.kbps = 100,
+		.scl = GPIO_EC_I2C_PROG_SCL,
+		.sda = GPIO_EC_I2C_PROG_SDA,
+	},
+	[I2C_CHAN_BATT_CHG] = {
+		.name = "batt_chg",
+		.port = IT83XX_I2C_CH_B,
+		.kbps = 100,
+		.scl = GPIO_SMB_BS_CLK,
+		.sda = GPIO_SMB_BS_DATA,
+	},
+	[I2C_CHAN_TYPEC_0] = {
+		.name = "typec_0",
+		.port = IT83XX_I2C_CH_C,
+		.kbps = 400,
+		.scl = GPIO_USBC_TCPC_I2C_CLK_P0,
+		.sda = GPIO_USBC_TCPC_I2C_DATA_P0,
+	},
+	[I2C_CHAN_TYPEC_1] = {
+		.name = "typec_1",
+		.port = IT83XX_I2C_CH_F,
+		.kbps = 400,
+		.scl = GPIO_USBC_TCPC_I2C_CLK_P2,
+		.sda = GPIO_USBC_TCPC_I2C_DATA_P2,
+	},
+#if defined(HAS_TASK_PD_C2)
+	[I2C_CHAN_TYPEC_2] = {
+		.name = "typec_2",
+		.port = IT83XX_I2C_CH_E,
+		.kbps = 400,
+		.scl = GPIO_USBC_TCPC_I2C_CLK_P1,
+		.sda = GPIO_USBC_TCPC_I2C_DATA_P1,
+	},
+	[I2C_CHAN_TYPEC_3] = {
+		.name = "typec_3",
+		.port = IT83XX_I2C_CH_D,
+		.kbps = 400,
+		.scl = GPIO_USBC_TCPC_I2C_CLK_P3,
+		.sda = GPIO_USBC_TCPC_I2C_DATA_P3,
+	},
+#endif
+};
+BUILD_ASSERT(ARRAY_SIZE(i2c_ports) == I2C_CHAN_COUNT);
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+const struct i2c_port_t i2c_bitbang_ports[] = {
+	[I2C_BITBANG_CHAN_BRD_ID] = {
+		.name = "bitbang_brd_id",
+		.port = IT83XX_I2C_CH_B,
+		.kbps = 100,
+		.scl = GPIO_SMB_BS_CLK,
+		.sda = GPIO_SMB_BS_DATA,
+		.drv = &bitbang_drv,
+	},
+	[I2C_BITBANG_CHAN_IOEX_0] = {
+		.name = "bitbang_ioex_0",
+		.port = IT83XX_I2C_CH_C,
+		.kbps = 100,
+		.scl = GPIO_USBC_TCPC_I2C_CLK_P0,
+		.sda = GPIO_USBC_TCPC_I2C_DATA_P0,
+		.drv = &bitbang_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(i2c_bitbang_ports) == I2C_BITBANG_CHAN_COUNT);
+const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
+
+/* USB-C TCPC Configuration */
+const struct tcpc_config_t tcpc_config[] = {
+	[TYPE_C_PORT_0] = {
+		.bus_type = EC_BUS_TYPE_EMBEDDED,
+		/* TCPC is embedded within EC so no i2c config needed */
+		.drv = &it83xx_tcpm_drv,
+	},
+#if defined(HAS_TASK_PD_C1)
+	[TYPE_C_PORT_1] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TYPEC_1,
+			.addr_flags = I2C_ADDR_FUSB302_TCPC_AIC,
+		},
+		.drv = &fusb302_tcpm_drv,
+	},
+#endif
+#if defined(HAS_TASK_PD_C2)
+	[TYPE_C_PORT_2] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TYPEC_2,
+			.addr_flags = I2C_ADDR_FUSB302_TCPC_AIC,
+		},
+		.drv = &fusb302_tcpm_drv,
+	},
+#endif
+#if defined(HAS_TASK_PD_C3)
+	[TYPE_C_PORT_3] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TYPEC_3,
+			.addr_flags = I2C_ADDR_FUSB302_TCPC_AIC,
+		},
+		.drv = &fusb302_tcpm_drv,
+	},
+#endif
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == CONFIG_USB_PD_PORT_MAX_COUNT);
+
+static void enable_irq(void)
+{
+	gpio_enable_interrupt(CONFIG_BATTERY_PRESENT_GPIO);
+}
+DECLARE_HOOK(HOOK_INIT, enable_irq, HOOK_PRIO_LAST);
+
+DECLARE_DEFERRED(set_charger_system_voltage);
+
+void battery_detect_interrupt(enum gpio_signal signal)
+{
+	/* Trigger deferred notification of battery interrupt */
+	hook_call_deferred(&set_charger_system_voltage_data, 0);
+}
diff --git a/board/adlrvpp_ite/board.h b/board/adlrvpp_ite/board.h
new file mode 100644
index 0000000000..37662a5d52
--- /dev/null
+++ b/board/adlrvpp_ite/board.h
@@ -0,0 +1,102 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel ADL-P-RVP-ITE board-specific configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* ITE EC variant */
+#define VARIANT_INTELRVP_EC_IT8320
+
+#include "adlrvp.h"
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+#define GPIO_AC_PRESENT GPIO_BC_ACOK_EC
+#define GPIO_EC_INT_L GPIO_EC_PCH_MKBP_INT_ODL_EC
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW_EC
+#define GPIO_LID_OPEN GPIO_SMC_LID
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE_EC
+#define GPIO_PCH_WAKE_L GPIO_PCH_WAKE_N
+#define GPIO_PCH_PWRBTN_L GPIO_PM_PWRBTN_N_EC
+#define GPIO_PCH_RSMRST_L GPIO_PM_RSMRST_EC
+#define GPIO_PCH_SLP_S0_L GPIO_PCH_SLP_S0_N
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_R_L
+#define GPIO_PG_EC_DSW_PWROK GPIO_VCCPDSW_3P3_EC
+#define GPIO_POWER_BUTTON_L GPIO_MECH_PWR_BTN_ODL
+#define GPIO_CPU_PROCHOT GPIO_PROCHOT_EC
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL_EC
+#define GPIO_WP_L GPIO_EC_WP_ODL
+#define GPIO_VOLUME_UP_L GPIO_VOLUME_UP
+#define GPIO_VOLUME_DOWN_L GPIO_VOL_DN_EC_R
+#define GPIO_DC_JACK_PRESENT GPIO_STD_ADP_PRSNT
+#define GPIO_ESPI_RESET_L GPIO_ESPI_RST_R
+#define GPIO_UART1_RX GPIO_UART_SERVO_TX_EC_RX
+#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BAT_DET_EC
+#define GPIO_BAT_LED_RED_L GPIO_LED_1_L_EC
+#define GPIO_PWR_LED_WHITE_L GPIO_LED_2_L_EC
+#define GPIO_SLP_SUS_L GPIO_PM_SLP_SUS_EC
+#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_PWRGD_EC
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_ALL_SYS_PWRGD_EC
+#define GPIO_PCH_DSW_PWROK GPIO_DSW_PWROK_EC
+#define GPIO_EN_PP3300_A GPIO_EC_DS3
+#define GPIO_TABLET_MODE_L GPIO_SLATE_MODE_INDICATION
+
+/* I2C ports & Configs */
+#define CONFIG_IT83XX_SMCLK2_ON_GPC7
+
+#define I2C_PORT_CHARGER IT83XX_I2C_CH_B
+
+/* Battery */
+#define I2C_PORT_BATTERY IT83XX_I2C_CH_B
+
+/* Board ID */
+#define I2C_PORT_PCA9555_BOARD_ID_GPIO IT83XX_I2C_CH_B
+
+/* Port 80 */
+#define I2C_PORT_PORT80 IT83XX_I2C_CH_B
+
+/* USB-C I2C */
+#define I2C_PORT_TYPEC_0 IT83XX_I2C_CH_C
+#define I2C_PORT_TYPEC_1 IT83XX_I2C_CH_F
+#if defined(HAS_TASK_PD_C2)
+#define I2C_PORT_TYPEC_2 IT83XX_I2C_CH_E
+#define I2C_PORT_TYPEC_3 IT83XX_I2C_CH_D
+#endif
+
+/* TCPC */
+#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP
+#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1
+
+/* Config Fan */
+#define GPIO_FAN_POWER_EN GPIO_EC_THRM_SEN_PWRGATE_N
+#define GPIO_ALL_SYS_PWRGD GPIO_ALL_SYS_PWRGD_EC
+
+/* Increase EC speed */
+#undef PLL_CLOCK
+#define PLL_CLOCK 96000000
+
+#ifndef __ASSEMBLER__
+
+enum adlrvp_i2c_channel {
+	I2C_CHAN_FLASH,
+	I2C_CHAN_BATT_CHG,
+	I2C_CHAN_TYPEC_0,
+	I2C_CHAN_TYPEC_1,
+#if defined(HAS_TASK_PD_C2)
+	I2C_CHAN_TYPEC_2,
+	I2C_CHAN_TYPEC_3,
+#endif
+	I2C_CHAN_COUNT,
+};
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/adlrvpp_ite/build.mk b/board/adlrvpp_ite/build.mk
new file mode 100644
index 0000000000..9da9f60561
--- /dev/null
+++ b/board/adlrvpp_ite/build.mk
@@ -0,0 +1,14 @@
+# -*- makefile -*-
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Intel ADL-P-RVP-ITE board-specific configuration
+#
+
+CHIP:=it83xx
+CHIP_FAMILY:=it8320
+CHIP_VARIANT:=it8320dx
+BASEBOARD:=intelrvp
+
+board-y=board.o
diff --git a/board/adlrvpp_ite/ec.tasklist b/board/adlrvpp_ite/ec.tasklist
new file mode 100644
index 0000000000..8bd63b1730
--- /dev/null
+++ b/board/adlrvpp_ite/ec.tasklist
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Intel ADL-P-RVP-ITE board-specific configuration.
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C2, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C3, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C2, pd_interrupt_handler_task, 2, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C3, pd_interrupt_handler_task, 3, ULTRA_TASK_STACK_SIZE)
diff --git a/board/adlrvpp_ite/gpio.inc b/board/adlrvpp_ite/gpio.inc
new file mode 100644
index 0000000000..22b97a7eff
--- /dev/null
+++ b/board/adlrvpp_ite/gpio.inc
@@ -0,0 +1,207 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel ADL-P-RVP-ITE board-specific configuration */
+
+/*
+ * Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first.
+ */
+
+#include "baseboard/intelrvp/adlrvp_ioex_gpio.inc"
+
+/* Power sequencing interrupts */
+GPIO_INT(ALL_SYS_PWRGD_EC,	PIN(F, 0), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(RSMRST_PWRGD_EC,	PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PCH_SLP_S0_N,		PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCPDSW_3P3_EC,	PIN(I, 3), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCST_PWRGD,		PIN(I, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PM_SLP_SUS_EC, 	PIN(K, 2), GPIO_INT_BOTH, power_signal_interrupt)
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+GPIO_INT(SLP_S3_R_L,		PIN(F, 2), GPIO_INT_BOTH, power_signal_interrupt)
+#endif
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
+GPIO_INT(SLP_S4_R_L,		PIN(F, 3), GPIO_INT_BOTH, power_signal_interrupt)
+#endif
+
+/* Button interrupts */
+GPIO_INT(VOLUME_UP,		PIN(D, 5), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(VOL_DN_EC_R,		PIN(D, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(SMC_LID,		PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP, lid_interrupt)
+GPIO_INT(MECH_PWR_BTN_ODL,	PIN(E, 4), GPIO_INT_BOTH, power_button_interrupt)
+GPIO_INT(EC_WP_ODL,		PIN(I, 4), GPIO_INT_BOTH, switch_interrupt)
+
+/* DC Jack presence coming from +VADP_OUT */
+GPIO_INT(STD_ADP_PRSNT, 	PIN(J, 2), GPIO_INT_BOTH, board_dc_jack_interrupt) /* DC_JACK_PRESENT */
+
+GPIO_INT(BC_ACOK_EC,		PIN(K, 3), GPIO_INT_BOTH, extpower_interrupt) /* AC Present */
+
+GPIO_INT(UART_SERVO_TX_EC_RX,	PIN(B, 0), GPIO_INT_FALLING, uart_deepsleep_interrupt)
+
+/* Battery present */
+GPIO_INT(BAT_DET_EC,	PIN(K, 0), GPIO_INT_BOTH, battery_detect_interrupt)
+
+/* USB-C interrupts */
+/* Using embedded TCPC for Port-0 */
+UNIMPLEMENTED(USBC_TCPC_ALRT_P0)
+GPIO(NC_USBC_TCPC_ALRT_P0,	PIN(I, 7), GPIO_INPUT)
+GPIO_INT(USBC_TCPC_PPC_ALRT_P0, PIN(J, 5), GPIO_INT_FALLING, ppc_interrupt)
+
+/*
+ * b:200265672 External pull-up resistor of port 1 is removed to fix port 3
+ * TCPC interrupt issue. So add internal pull-up for port 1 instead.
+ * This change is only applied to ITE chip.
+ */
+#if defined(HAS_TASK_PD_C1)
+GPIO_INT(USBC_TCPC_ALRT_P1,	PIN(G, 0), GPIO_INT_FALLING | GPIO_PULL_UP, tcpc_alert_event)
+GPIO_INT(USBC_TCPC_PPC_ALRT_P1, PIN(C, 4), GPIO_INT_FALLING, ppc_interrupt)
+#else
+GPIO(USBC_TCPC_ALRT_P1,		PIN(G, 0), GPIO_INPUT)
+GPIO(USBC_TCPC_PPC_ALRT_P1,	PIN(C, 4), GPIO_INPUT)
+#endif
+
+#if defined(HAS_TASK_PD_C2)
+GPIO_INT(USBC_TCPC_ALRT_P2,	PIN(J, 1), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USBC_TCPC_PPC_ALRT_P2, PIN(E, 5), GPIO_INT_FALLING, ppc_interrupt)
+#else
+GPIO(USBC_TCPC_ALRT_P2,		PIN(J, 1), GPIO_INPUT)
+GPIO(USBC_TCPC_PPC_ALRT_P2,	PIN(E, 5), GPIO_INPUT)
+#endif
+
+#if defined(HAS_TASK_PD_C3)
+GPIO_INT(USBC_TCPC_ALRT_P3,	PIN(J, 3), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USBC_TCPC_PPC_ALRT_P3, PIN(E, 6), GPIO_INT_FALLING, ppc_interrupt)
+#else
+GPIO(USBC_TCPC_ALRT_P3,		PIN(J, 3), GPIO_INPUT)
+GPIO(USBC_TCPC_PPC_ALRT_P3,	PIN(E, 6), GPIO_INPUT)
+#endif
+
+#ifndef CONFIG_HOST_INTERFACE_ESPI
+GPIO_INT(ESPI_RST_R,		PIN(D, 2), GPIO_INPUT)
+#endif
+
+#ifdef CONFIG_HOST_INTERFACE_ESPI
+/* enable 1.8v input of EC's espi_reset pin, and then this pin takes effect. */
+GPIO_INT(ESPI_RST_R,		PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt) /* eSPI_reset# */
+#endif
+
+/* Sensor Interrupts */
+GPIO_INT(SLATE_MODE_INDICATION,	PIN(K, 1), GPIO_INT_BOTH | GPIO_SEL_1P8V, gmr_tablet_switch_isr)
+
+/* Power sequencing GPIOs */
+GPIO(SYS_RST_ODL_EC,		PIN(B, 6), GPIO_ODR_HIGH)
+GPIO(PROCHOT_EC,		PIN(C, 0), GPIO_INPUT)
+GPIO(PM_RSMRST_EC,		PIN(C, 6), GPIO_OUT_LOW)
+GPIO(PM_PWRBTN_N_EC,		PIN(D, 0), GPIO_ODR_HIGH)
+GPIO(EC_SPI_OE_N,		PIN(I, 2), GPIO_OUT_LOW)
+
+GPIO(EC_PCH_MKBP_INT_ODL_EC,	PIN(B, 7), GPIO_ODR_HIGH)
+GPIO(EDP_BKLT_EN,		PIN(J, 6), GPIO_OUT_HIGH)
+GPIO(EC_DS3,			PIN(L, 4), GPIO_OUT_LOW)
+UNIMPLEMENTED(EN_PP5000)
+
+/*
+ * PCH_SYS_PWROK is an input, driven by the Silego chip. The common x86
+ * power sequencing expects that PCH_SYS_PWROK is an output and will drive
+ * this signal if GPIO_PCH_SYS_PWROK is configured. Map this pin as no-connect
+ * so that state can be monitored using the console.
+ */
+GPIO(PCH_PWROK_EC_R,	PIN(K, 4), GPIO_INPUT)
+GPIO(SYS_PWROK_EC,	PIN(D, 1), GPIO_OUT_LOW)
+GPIO(DSW_PWROK_EC,	PIN(L, 6), GPIO_OUT_LOW)
+
+/* Host communication GPIOs */
+#ifndef CONFIG_HOST_INTERFACE_ESPI
+GPIO(PLT_RST_L, 	PIN(H, 6), GPIO_INPUT | GPIO_PULL_UP) /* PCH_PLTRST_L */
+#endif
+GPIO(PCH_WAKE_N,	PIN(J, 0), GPIO_ODR_HIGH)
+
+/* LED */
+GPIO(LED_1_L_EC,	PIN(A, 6), GPIO_OUT_HIGH)	/* BAT_LED_GREEN_L LED_2_L */
+GPIO(LED_2_L_EC,	PIN(A, 7), GPIO_OUT_HIGH)	/* AC_LED_GREEN_L LED_1_L */
+
+/* H1 pins */
+GPIO(EC_H1_PACKET_MODE_EC,	PIN(J, 4), GPIO_OUT_LOW)
+GPIO(EC_ENTERING_RW_EC,		PIN(K, 7), GPIO_OUT_LOW)
+
+/* Case Closed Debug Mode */
+GPIO_INT(CCD_MODE_ODL,	PIN(B, 5), GPIO_INT_BOTH, board_connect_c0_sbu)
+
+/* FAN control pins */
+GPIO(EC_THRM_SEN_PWRGATE_N,	PIN(K, 6), GPIO_OUT_LOW)
+
+/*
+ * I2C pins should be configure as inputs until I2C module is
+ * initialized. This will avoid driving the lines unintentionally.
+ */
+GPIO(EC_I2C_PROG_SCL,		PIN(B, 3), GPIO_INPUT)	/* I2C_A_SCL */
+GPIO(EC_I2C_PROG_SDA,		PIN(B, 4), GPIO_INPUT)	/* I2C_A_SDA */
+GPIO(SMB_BS_CLK,		PIN(C, 1), GPIO_INPUT)	/* I2C_B_SCL */
+GPIO(SMB_BS_DATA,		PIN(C, 2), GPIO_INPUT)	/* I2C_B_SDA */
+
+/* P0 IT83XX_I2C_CH_C */
+GPIO(USBC_TCPC_I2C_CLK_P0,	PIN(C, 7), GPIO_INPUT)	/* I2C_C_SCL */
+GPIO(USBC_TCPC_I2C_DATA_P0,	PIN(F, 7), GPIO_INPUT)	/* I2C_C_SDA */
+
+/* P1 IT83XX_I2C_CH_F */
+GPIO(USBC_TCPC_I2C_CLK_P2,	PIN(A, 4), GPIO_INPUT)	/* I2C_F_SCL */
+GPIO(USBC_TCPC_I2C_DATA_P2,	PIN(A, 5), GPIO_INPUT)	/* I2C_F_SDA */
+
+/* P2 IT83XX_I2C_CH_E */
+GPIO(USBC_TCPC_I2C_CLK_P1,	PIN(E, 0), GPIO_INPUT)	/* I2C_E_SCL */
+GPIO(USBC_TCPC_I2C_DATA_P1,	PIN(E, 7), GPIO_INPUT)	/* I2C_E_SDA */
+
+/* P3 IT83XX_I2C_CH_D */
+GPIO(USBC_TCPC_I2C_CLK_P3,	PIN(H, 1), GPIO_INPUT)	/* I2C_D_SCL */
+GPIO(USBC_TCPC_I2C_DATA_P3,	PIN(H, 2), GPIO_INPUT)	/* I2C_D_SDA */
+
+/* Unused 1.8V or 3.3V compatiable pins */
+GPIO(TP_DEVELOPER_MODE_EC,	PIN(B, 2), GPIO_INPUT)
+GPIO(ESPI_CS1_N_R,		PIN(D, 3), GPIO_INPUT)
+GPIO(SUSWARN,			PIN(E, 1), GPIO_INPUT)
+GPIO(CPU_C10_GATE,		PIN(G, 1), GPIO_INPUT)
+GPIO(TP_GPIO_G2,		PIN(G, 2), GPIO_INPUT)
+GPIO(TP_GPIO_G6,		PIN(G, 6), GPIO_INPUT)
+GPIO(BATT_DISABLE_EC,		PIN(H, 0), GPIO_INPUT)
+GPIO(ME_G3_TO_M3_EC,		PIN(H, 5), GPIO_INPUT)
+GPIO(SLP_S0_CS_EC,		PIN(I, 0), GPIO_INPUT)
+GPIO(SMC_SHUTDOWN,		PIN(K, 5), GPIO_INPUT)
+GPIO(CPU_CAT_ERR_MECC,		PIN(L, 1), GPIO_INPUT)
+GPIO(SMC_ONOFF_N,		PIN(L, 3), GPIO_INPUT) /* Power button interrupt without H1 */
+GPIO(STD_ADPT_CNTRL_EC,		PIN(L, 5), GPIO_INPUT)
+GPIO(SMB_PCH_ALRT,		PIN(L, 7), GPIO_INPUT)
+GPIO(ESPI_ALERT0_R,		PIN(M, 6), GPIO_INPUT | GPIO_SEL_1P8V)
+
+/* Unused 3.3V compatiable pins */
+GPIO(TP_GPIO_A0,		PIN(A, 0), GPIO_INPUT)
+GPIO(TP_GPIO_A1,		PIN(A, 1), GPIO_INPUT)
+GPIO(TP_GPIO_A3,		PIN(A, 3), GPIO_INPUT)
+GPIO(TP_GPC3,			PIN(C, 3), GPIO_INPUT)
+GPIO(TP_GPC5,			PIN(C, 5), GPIO_INPUT)
+GPIO(TP_GPIO_E3,		PIN(E, 3), GPIO_INPUT)
+GPIO(TP_GPIO_H3,		PIN(H, 3), GPIO_INPUT)
+GPIO(TP_GPIO_H4,		PIN(H, 4), GPIO_INPUT)
+
+/* Alternate pins for I2C */
+ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C F SCL/SDA A4/A5 */
+ALTERNATE(PIN_MASK(B, BIT(3) | BIT(4)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C A SCL/SDA B3/B4 */
+ALTERNATE(PIN_MASK(C, BIT(1) | BIT(2)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C B SCL/SDA C1/C2 */
+ALTERNATE(PIN_MASK(E, BIT(0) | BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C E SCL/SDA E0/E7 */
+ALTERNATE(PIN_MASK(C, BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)		/* I2C C SCL C7 */
+ALTERNATE(PIN_MASK(F, BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)		/* I2C C SDA F7 */
+ALTERNATE(PIN_MASK(H, BIT(1) | BIT(2)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C D SCL/SDA H1/H2 */
+
+/* Alternate pins for UART */
+ALTERNATE(PIN_MASK(B, BIT(0) | BIT(1)), GPIO_ALT_FUNC_DEFAULT, MODULE_UART, GPIO_FLAG_NONE) 	/* UART1 B0/B1 */
+
+/* Alternate pins for ADC */
+ALTERNATE(PIN_MASK(I, BIT(1) | BIT(6)), GPIO_ALT_FUNC_DEFAULT, MODULE_ADC, GPIO_FLAG_NONE)	/* ADC 1,6 -> I1,I6 */
+ALTERNATE(PIN_MASK(L, BIT(0) | BIT(2)), GPIO_ALT_FUNC_DEFAULT, MODULE_ADC, GPIO_FLAG_NONE)	/* ADC 13,15 -> L0,L2 */
+
+/* Alternate pins for FAN */
+ALTERNATE(PIN_MASK(A, BIT(2)), GPIO_ALT_FUNC_DEFAULT, MODULE_PWM, GPIO_FLAG_NONE)		/* PWM2 A2 */
+ALTERNATE(PIN_MASK(D, BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_PWM, GPIO_FLAG_NONE)		/* TACH1A D7 */
diff --git a/board/adlrvpp_ite/vif_override.xml b/board/adlrvpp_ite/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/adlrvpp_ite/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/adlrvpp_mchp1521/board.c b/board/adlrvpp_mchp1521/board.c
new file mode 100644
index 0000000000..0ec53d1eb5
--- /dev/null
+++ b/board/adlrvpp_mchp1521/board.c
@@ -0,0 +1,111 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel ADLRVP-P-DDR4-MEC1521 board-specific configuration */
+
+#include "button.h"
+#include "fan.h"
+#include "fusb302.h"
+#include "gpio.h"
+#include "i2c.h"
+#include "i2c_bitbang.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "pca9675.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "spi_chip.h"
+#include "switch.h"
+#include "tablet_mode.h"
+#include "timer.h"
+#include "uart.h"
+#include "usb_pd_tbt.h"
+#include "usb_pd_tcpm.h"
+#include "util.h"
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/******************************************************************************/
+/* I2C ports */
+const struct i2c_port_t i2c_ports[] = {
+	/*
+	 * Port-80 Display, Charger, Battery, IO-expander, EEPROM,
+	 * ISH sensor, AUX-rail, power-monitor.
+	 */
+	[I2C_CHAN_BATT_CHG] = {
+		.name = "batt_chg",
+		.port = I2C_PORT_CHARGER,
+		.kbps = 100,
+		.scl = GPIO_SMB_BS_CLK,
+		.sda = GPIO_SMB_BS_DATA,
+	},
+	[I2C_CHAN_TCPC_0] = {
+		.name = "typec_0",
+		.port = I2C_PORT_TYPEC_0,
+		.kbps = 400,
+		.scl = GPIO_TYPEC_EC_SMBUS1_CLK_EC,
+		.sda = GPIO_TYPEC_EC_SMBUS1_DATA_EC,
+	},
+	[I2C_CHAN_TCPC_1] = {
+		.name = "typec_1",
+		.port = I2C_PORT_TYPEC_1,
+		.kbps = 400,
+		.scl = GPIO_TYPEC_EC_SMBUS3_CLK,
+		.sda = GPIO_TYPEC_EC_SMBUS3_DATA,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(i2c_ports) == I2C_CHAN_COUNT);
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+const struct i2c_port_t i2c_bitbang_ports[] = {
+	[I2C_BITBANG_CHAN_BRD_ID] = {
+		.name = "bitbang_brd_id",
+		.port = I2C_PORT_CHARGER,
+		.kbps = 100,
+		.scl = GPIO_SMB_BS_CLK,
+		.sda = GPIO_SMB_BS_DATA,
+		.drv = &bitbang_drv,
+	},
+	[I2C_BITBANG_CHAN_IOEX_0] = {
+		.name = "bitbang_ioex_0",
+		.port = I2C_PORT_TYPEC_0,
+		.kbps = 100,
+		.scl = GPIO_TYPEC_EC_SMBUS1_CLK_EC,
+		.sda = GPIO_TYPEC_EC_SMBUS1_DATA_EC,
+		.drv = &bitbang_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(i2c_bitbang_ports) == I2C_BITBANG_CHAN_COUNT);
+const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
+
+/* USB-C TCPC Configuration */
+const struct tcpc_config_t tcpc_config[] = {
+	[TYPE_C_PORT_0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TYPEC_0,
+			.addr_flags = I2C_ADDR_FUSB302_TCPC_AIC,
+		},
+		.drv = &fusb302_tcpm_drv,
+	},
+	[TYPE_C_PORT_1] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TYPEC_1,
+			.addr_flags = I2C_ADDR_FUSB302_TCPC_AIC,
+		},
+		.drv = &fusb302_tcpm_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == CONFIG_USB_PD_PORT_MAX_COUNT);
+
+/* SPI devices */
+const struct spi_device_t spi_devices[] = {
+	{ QMSPI0_PORT, 4, GPIO_QMSPI_CS0 },
+};
+const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
diff --git a/board/adlrvpp_mchp1521/board.h b/board/adlrvpp_mchp1521/board.h
new file mode 100644
index 0000000000..645bfc0598
--- /dev/null
+++ b/board/adlrvpp_mchp1521/board.h
@@ -0,0 +1,159 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel ADLRVP-P-DDR4-MEC1521 board-specific configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* Microchip EC variant */
+#define VARIANT_INTELRVP_EC_MCHP
+
+/* UART for EC console */
+#undef CONFIG_UART_CONSOLE
+#define CONFIG_UART_CONSOLE 2
+
+#include "adlrvp.h"
+
+#undef CONFIG_CMD_ADC
+#undef CONFIG_CMD_APTHROTTLE
+#undef CONFIG_CMD_BATTFAKE
+#undef CONFIG_CMD_GETTIME
+
+/* Enable LTO */
+#define CONFIG_LTO
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+/* Power sequencing */
+#define GPIO_EC_SPI_OE_N GPIO_EC_PCH_SPI_OE_N
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_ALL_SYS_PWRGD
+#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_PWRGD_EC_N
+#define GPIO_PCH_SLP_S0_L GPIO_PM_SLP_S0_R_N
+#define GPIO_PG_EC_DSW_PWROK GPIO_EC_TRACE_DATA_2
+#define GPIO_VCCST_PWRGD GPIO_EC_TRACE_DATA_3
+#define GPIO_SLP_SUS_L GPIO_PM_SLP_SUS_N
+#define GPIO_SYS_RESET_L GPIO_DG2_PRESENT
+#define GPIO_PCH_RSMRST_L GPIO_PM_RSMRST_R
+#define GPIO_PCH_PWRBTN_L GPIO_PM_PWRBTN_N_R
+#define GPIO_EN_PP3300_A GPIO_EC_DS3_R
+#define GPIO_SYS_PWROK_EC GPIO_SYS_PWROK_EC_R
+#define GPIO_PCH_DSW_PWROK GPIO_EC_TRACE_DATA_1
+
+/* Buttons */
+#define GPIO_LID_OPEN GPIO_SMC_LID
+#define GPIO_VOLUME_UP_L GPIO_VOL_UP_EC
+#define GPIO_VOLUME_DOWN_L GPIO_VOL_DOWN_EC
+#define GPIO_POWER_BUTTON_L GPIO_PWRBTN_EC_IN_N
+
+/* Sensors */
+#define GPIO_TABLET_MODE_L GPIO_EC_SLATEMODE_HALLOUT_SNSR_R
+#define GPIO_CPU_PROCHOT GPIO_PROCHOT_EC_R
+
+/* AC & Battery */
+#define GPIO_DC_JACK_PRESENT GPIO_STD_ADP_PRSNT_EC
+#define GPIO_AC_PRESENT GPIO_BC_ACOK_EC_IN
+#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BATT_ID_R
+
+/* eSPI/Host communication */
+#define GPIO_ESPI_RESET_L GPIO_ESPI_RST_EC_R_N
+#define GPIO_PCH_WAKE_L GPIO_SMC_WAKE_SCI_N
+#define GPIO_EC_INT_L GPIO_EC_TRACE_DATA_0
+
+/* H1 */
+#define GPIO_WP_L GPIO_EC_WAKE_CLK_R
+#define GPIO_PACKET_MODE_EN GPIO_EC_TRACE_CLK
+#define GPIO_ENTERING_RW GPIO_DNX_FORCE_RELOAD_EC_R
+
+/* FAN */
+#define GPIO_FAN_POWER_EN GPIO_FAN_PWR_DISABLE
+
+/* LEDs */
+#define GPIO_BAT_LED_RED_L GPIO_PM_BAT_STATUS_LED2
+#define GPIO_PWR_LED_WHITE_L GPIO_PM_PWRBTN_LED
+
+/* Uart */
+#define GPIO_UART2_RX GPIO_EC_UART_RX
+
+/* Case Closed Debug Mode interrupt */
+#define GPIO_CCD_MODE_ODL GPIO_KBC_NUMLOCK
+
+/* USB-C interrupts */
+#define GPIO_USBC_TCPC_ALRT_P0 GPIO_TYPEC_EC_SMBUS_ALERT_0_R
+#define GPIO_USBC_TCPC_ALRT_P1 GPIO_TYPEC_EC_SMBUS_ALERT_1_R
+#define GPIO_USBC_TCPC_PPC_ALRT_P0 GPIO_KBC_SCANOUT_15
+#define GPIO_USBC_TCPC_PPC_ALRT_P1 GPIO_KBC_CAPSLOCK
+
+/* I2C ports & Configs */
+/* Charger */
+#define I2C_PORT_CHARGER MCHP_I2C_PORT0
+/* Port 80 */
+#define I2C_PORT_PORT80 MCHP_I2C_PORT0
+/* Board ID */
+#define I2C_PORT_PCA9555_BOARD_ID_GPIO MCHP_I2C_PORT0
+/* Battery */
+#define I2C_PORT_BATTERY MCHP_I2C_PORT0
+/* USB-C I2C */
+#define I2C_PORT_TYPEC_0 MCHP_I2C_PORT1
+#define I2C_PORT_TYPEC_1 MCHP_I2C_PORT5
+
+/*
+ * MEC1521H loads firmware using QMSPI controller
+ * CONFIG_SPI_FLASH_PORT is the index into
+ * spi_devices[] in board.c
+ */
+#define CONFIG_SPI_FLASH_PORT 0
+#define CONFIG_SPI_FLASH
+
+/*
+ * ADLRVP uses 32MB SPI flash- W25R256JVEIQ.But, EC binary to be generated
+ * is of size 512KB. This bin is then later appended with 0xFF to become 32MB
+ * binary for flashing purpose.
+ */
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
+#define CONFIG_SPI_FLASH_W25X40 /* TODO: change to W25R256 */
+
+/* ADC channels */
+/*
+ * Undefining below and redefining based on ADL RVP schematics,
+ * as they are already defined with different channels in mchp_ec.h.
+ */
+#undef ADC_TEMP_SNS_AMBIENT_CHANNEL
+#undef ADC_TEMP_SNS_VR_CHANNEL
+#undef ADC_TEMP_SNS_DDR_CHANNEL
+#undef ADC_TEMP_SNS_SKIN_CHANNEL
+
+#define ADC_TEMP_SNS_AMBIENT_CHANNEL CHIP_ADC_CH4
+#define ADC_TEMP_SNS_VR_CHANNEL CHIP_ADC_CH5
+#define ADC_TEMP_SNS_DDR_CHANNEL CHIP_ADC_CH6
+#define ADC_TEMP_SNS_SKIN_CHANNEL CHIP_ADC_CH7
+
+/* To do: Remove once fan register details are added in mchp/fan.c */
+#undef CONFIG_FANS
+
+/* Use internal silicon 32KHz oscillator */
+#undef CONFIG_CLOCK_SRC_EXTERNAL
+
+/* Free up flash space. */
+#undef CONFIG_CONSOLE_CMDHELP
+
+#ifndef __ASSEMBLER__
+
+enum adlrvp_i2c_channel {
+	I2C_CHAN_BATT_CHG,
+	I2C_CHAN_TCPC_0,
+	I2C_CHAN_TCPC_1,
+	I2C_CHAN_COUNT,
+};
+
+/* Map I2C port to controller */
+int board_i2c_p2c(int port);
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/adlrvpp_mchp1521/build.mk b/board/adlrvpp_mchp1521/build.mk
new file mode 100644
index 0000000000..5bc76c4429
--- /dev/null
+++ b/board/adlrvpp_mchp1521/build.mk
@@ -0,0 +1,18 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Intel ADLRVP-P-DDR4-MEC1521 board-specific configuration
+#
+
+# the IC is Microchip MEC1521 with SRAM of 256KB
+# external SPI is 32MB
+# external clock is crystal
+CHIP:=mchp
+CHIP_FAMILY:=mec152x
+CHIP_VARIANT:=mec1521
+CHIP_SPI_SIZE_KB:=512
+BASEBOARD:=intelrvp
+
+board-y=board.o
diff --git a/board/adlrvpp_mchp1521/ec.tasklist b/board/adlrvpp_mchp1521/ec.tasklist
new file mode 100644
index 0000000000..0019755448
--- /dev/null
+++ b/board/adlrvpp_mchp1521/ec.tasklist
@@ -0,0 +1,25 @@
+/*
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Intel ADLRVP-P-DDR4-MEC1521 board-specific configuration.
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, VENTI_TASK_STACK_SIZE)
diff --git a/board/adlrvpp_mchp1521/gpio.inc b/board/adlrvpp_mchp1521/gpio.inc
new file mode 100644
index 0000000000..848253fa17
--- /dev/null
+++ b/board/adlrvpp_mchp1521/gpio.inc
@@ -0,0 +1,314 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel ADLRVP-P-DDR4-MEC1521 board-specific configuration. */
+
+/*
+ * MEC152X data sheets GPIO numbers are OCTAL.
+ */
+
+/*
+ * MEC1521H-SZ MECC board SPI flash is connected to MEC1521H-SZ shared SPI port.
+ * GPIO055/SHD_CS0# pin is used to determine the boot source (eSPI Flash channel
+ * or shared SPI). On RVP, SHD_CS0_N is connected to Flash0 and SHD_CS1_N is
+ * connected to Flash1. Based on RVP design, Flash1 is meant for EC & Flash0
+ * for Coreboot.But, for MEC, it is mandatory to route CS0 to external Flash
+ * for EC to boot load the image. Hence, necessary rework must be taken care to
+ * route CS0 to external Flash1.
+ */
+/* Include common gpios needed for LFW loader and main process FW */
+#include "chip/mchp/lfw/gpio.inc"
+
+#include "baseboard/intelrvp/adlrvp_ioex_gpio.inc"
+
+/* As all signal names used here are supposed to match the schematic,
+ * few pin names may not indicate the real purpose.Refer comments to clarify the pin usage.
+ * Such pins are further renamed in board.h.
+ */
+
+/* Power sequencing interrupts */
+GPIO_INT(ALL_SYS_PWRGD,		PIN(057),	GPIO_INT_BOTH,	power_signal_interrupt)
+GPIO_INT(RSMRST_PWRGD_EC_N,	PIN(012),	GPIO_INT_BOTH,	power_signal_interrupt)
+GPIO_INT(PM_SLP_S0_R_N,		PIN(0243),	GPIO_INT_BOTH,	power_signal_interrupt)
+/* Below meaningless pin names are to match the schematic.*/
+/* PG_EC_DSW_PWROK signal */
+GPIO_INT(EC_TRACE_DATA_2,	PIN(0202),	GPIO_INT_BOTH,	power_signal_interrupt)
+/* VCCST_PWRGD signal */
+GPIO_INT(EC_TRACE_DATA_3,	PIN(0203),	GPIO_INT_BOTH,	power_signal_interrupt)
+GPIO_INT(PM_SLP_SUS_N,		PIN(000),	GPIO_INT_BOTH,	power_signal_interrupt)
+
+/* Button interrupts */
+GPIO_INT(VOL_UP_EC,		PIN(0242),	GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
+GPIO_INT(VOL_DOWN_EC,		PIN(0246),	GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
+GPIO_INT(SMC_LID,		PIN(033),	GPIO_INT_BOTH | GPIO_PULL_UP,	lid_interrupt)
+/* Buffered power button input from
+ * PMIC-SLG7NT4192VTR / PWRBTN_EC_SILEGO_OUTPUT */
+GPIO_INT(PWRBTN_EC_IN_N,	PIN(0163),	GPIO_INT_BOTH,	power_button_interrupt)
+
+/* DC Jack presence coming from +VADP_OUT */
+/* DC_JACK_PRESENT */
+GPIO_INT(STD_ADP_PRSNT_EC,	PIN(052),	GPIO_INT_BOTH,	board_dc_jack_interrupt)
+/* AC Present */
+GPIO_INT(BC_ACOK_EC_IN,		PIN(0172),	GPIO_INT_BOTH,	extpower_interrupt)
+
+/* H1 */
+/* WP_L interrupt pin */
+GPIO_INT(EC_WAKE_CLK_R,		PIN(0241),	GPIO_INT_BOTH,	switch_interrupt)
+
+/* Case Closed Debug Mode */
+/* CCD_MODE_ODL pin */
+GPIO_INT(KBC_NUMLOCK,		PIN(0255),	GPIO_INT_BOTH,	board_connect_c0_sbu)
+
+/* USB-C interrupts */
+/* Below meaningless pin names are to match the schematic */
+/* TCPC & PPC Alerts */
+/* USBC_TCPC_ALRT_P0 */
+GPIO_INT(TYPEC_EC_SMBUS_ALERT_0_R,	PIN(0132),	GPIO_INT_BOTH,	tcpc_alert_event)
+/* USBC_TCPC_ALRT_P1 */
+GPIO_INT(TYPEC_EC_SMBUS_ALERT_1_R,	PIN(0245),	GPIO_INT_BOTH,	tcpc_alert_event)
+/* USBC_TCPC_PPC_ALRT_P0 */
+GPIO_INT(KBC_SCANOUT_15,	PIN(0151),	GPIO_INT_BOTH,	ppc_interrupt)
+/* USBC_TCPC_PPC_ALRT_P1 */
+GPIO_INT(KBC_CAPSLOCK,		PIN(0127),	GPIO_INT_BOTH,	ppc_interrupt)
+
+/* Sensor Interrupts */
+/* GPIO_TABLET_MODE_L */
+GPIO_INT(EC_SLATEMODE_HALLOUT_SNSR_R,	PIN(064),	GPIO_INT_BOTH |
+					GPIO_SEL_1P8V,	gmr_tablet_switch_isr)
+
+/* UART Interrupt */
+GPIO_INT(EC_UART_RX,	PIN(0145),	GPIO_INT_BOTH_DSLEEP | GPIO_PULL_UP,
+						uart_deepsleep_interrupt)
+
+/* Power sequencing GPIOs */
+GPIO(PM_RSMRST_R,	PIN(054),	GPIO_OUT_LOW)
+GPIO(PM_PWRBTN_N_R,	PIN(0101),	GPIO_ODR_HIGH)
+GPIO(EC_PCH_SPI_OE_N,	PIN(024),	GPIO_OUT_LOW)
+GPIO(SYS_PWROK_EC_R,	PIN(043),	GPIO_OUT_LOW)
+/* Below names are meaningless to match schematic */
+/* PCH_DSW_PWROK */
+GPIO(EC_TRACE_DATA_1,	PIN(0201),	GPIO_OUT_LOW)
+/* SYS_RESET_L */
+GPIO(DG2_PRESENT,	PIN(0165),	GPIO_ODR_HIGH)
+/* EN_PP3300_A */
+GPIO(EC_DS3_R,		PIN(0226),	GPIO_OUT_LOW)
+/* PCH_PWROK_EC is an input, as it is driven by the Silego chip on RVP */
+GPIO(EC_PM_PCH_PWROK,	PIN(0106),	GPIO_INPUT)
+UNIMPLEMENTED(EN_PP5000)
+
+/* Host communication GPIOs */
+/* PCH_WAKE_L pin*/
+GPIO(SMC_WAKE_SCI_N,	PIN(0114),	GPIO_ODR_HIGH)
+/* EC_INT_L pin */
+GPIO(EC_TRACE_DATA_0,	PIN(0200),	GPIO_ODR_HIGH)
+#ifndef CONFIG_HOST_INTERFACE_ESPI
+GPIO(ESPI_RST_EC_R_N,	PIN(061),	GPIO_INPUT)
+#endif
+
+/* H1 Pins */
+/* PACKET_MODE_EN */
+GPIO(EC_TRACE_CLK,	PIN(0105),	GPIO_OUT_LOW)
+/* ENTERING_RW */
+GPIO(DNX_FORCE_RELOAD_EC_R,	PIN(0115),	GPIO_OUT_LOW)
+
+/* FAN control pins */
+GPIO(FAN_PWR_DISABLE,	PIN(060),	GPIO_OUT_LOW)
+
+/* EDP */
+GPIO(EC_EDP1_BKLT_EN,	PIN(0157),	GPIO_OUT_HIGH)
+
+/* LEDs */
+GPIO(PM_BAT_STATUS_LED2,	PIN(035),	GPIO_OUT_LOW)
+GPIO(PM_PWRBTN_LED,		PIN(0254),	GPIO_OUT_LOW)
+
+/* Battery present */
+GPIO(BATT_ID_R,		PIN(0162),	GPIO_INPUT)
+
+/* VTR2 STRAP PIN - GPIO0104_UART0_TX
+ * Voltage level strap used to determine,
+ * if shared flash interface must be configured
+ * for 3.3V or 1.8V.
+ * 1 = 3.3V operation
+ * 0 = 1.8V operation
+ */
+GPIO(EC_VTR2_STRAP,	PIN(0104),	GPIO_INPUT)
+
+/* Tap Controller select strap - GPIO0170_UART1_TX
+ * If any of the JTAG TAP controllers are used, GPIO170 must only
+ * be configured as an output to a VTRx powered external function.
+ * GPIO170 may only be configured as an input when
+ * the JTAG TAP controllers are not needed or when an external driver
+ * does not violate the Slave Select Timing.
+ */
+GPIO(EC_JTAG_STRAP,	PIN(0170),	GPIO_ODR_HIGH)
+
+/* I2C pins */
+/* I2C pins should be configure as inputs until I2C module is
+ * initialized. This will avoid driving the lines unintentionally.
+ */
+GPIO(SMB_BS_CLK,		PIN(004),	GPIO_INPUT)
+GPIO(SMB_BS_DATA,		PIN(003),	GPIO_INPUT)
+GPIO(TYPEC_EC_SMBUS1_CLK_EC,	PIN(0131),	GPIO_INPUT)
+GPIO(TYPEC_EC_SMBUS1_DATA_EC,	PIN(0130),	GPIO_INPUT)
+GPIO(TYPEC_EC_SMBUS3_DATA,	PIN(0142),	GPIO_INPUT)
+GPIO(TYPEC_EC_SMBUS3_CLK,	PIN(0141),	GPIO_INPUT)
+
+/* Unused Pins */
+/* These have different meaning on RVP for alternate OS
+ * support.Hence, keep them as input.
+ */
+GPIO(PROCHOT_EC_R,		PIN(0253),	GPIO_INPUT)
+GPIO(BC_PROCHOT_EC_N,		PIN(034),	GPIO_INPUT)
+GPIO(EC_PEG_PLI_N_DG2,		PIN(036),	GPIO_INPUT)
+GPIO(PEG_PIM_DG2,		PIN(0240),	GPIO_INPUT)
+GPIO(KBD_BKLT_CTRL,		PIN(014),	GPIO_INPUT)
+GPIO(STD_ADPT_CNTRL_GPIO_R,	PIN(0171),	GPIO_INPUT)
+GPIO(SAF_G3_DETECT,		PIN(013),	GPIO_INPUT)
+GPIO(EC_GPIO015_PWM7,		PIN(015),	GPIO_INPUT)
+GPIO(EC_GPPC_B14,		PIN(0244),	GPIO_INPUT)
+GPIO(SX_EXIT_HOLDOFF_N,		PIN(0175),	GPIO_INPUT)
+GPIO(MIC_PRIVACY_EC,		PIN(0100),	GPIO_INPUT)
+GPIO(MIC_PRIVACY_SWITCH,	PIN(011),	GPIO_INPUT)
+GPIO(PECI_MUX_CTRL_ER_INT,	PIN(025),	GPIO_INPUT)
+GPIO(PEG_RTD3_COLD_MOD_SW_R,	PIN(0156),	GPIO_INPUT)
+GPIO(H_CATERR_EC_N,		PIN(0153),	GPIO_INPUT)
+GPIO(PM_BATLOW_N,		PIN(0140),	GPIO_INPUT)
+GPIO(HOME_BTN_EC_RVP_AEP_ID,	PIN(023),	GPIO_INPUT)
+GPIO(CPU_C10_GATE_N_R,		PIN(022),	GPIO_INPUT)
+GPIO(VREF_VTT,			PIN(044),	GPIO_INPUT)
+GPIO(HB_NVDC_SEL,		PIN(0161), 	GPIO_INPUT)
+GPIO(EC_VCI_OUT_WAKE_R,		PIN(0250),	GPIO_INPUT)
+GPIO(PM_SLP_S0_CS_N,		PIN(0221),	GPIO_INPUT)
+GPIO(GPPC_E7_EC_SMI_N_R,	PIN(0102),	GPIO_INPUT)
+GPIO(TC_RETIMER_FORCE_PWR_BTP_EC_R,	PIN(0222),	GPIO_INPUT)
+
+/* Alternate functions */
+
+/* Alternate functions GPIO definitions */
+
+/*
+ * MCHP has 6 banks/ports each containing 32 GPIO's.
+ * Each bank/port is connected to a GIRQ.
+ * Port numbering Example:
+ * GPIO_015 = 13 decimal. Port/bank = 13/32 = 0, bit = 13 % 32 = 13
+ * GPIO_0123 = 83 decimal. Port/bank = 83/32 = 2, bit = 83 % 32 = 19
+ * OR port = 0123 >> 5, bit = 0123 & 037(0x1F) = 023 = 19 decimal.
+ */
+
+/*
+ * Configure I2C as alternate function
+ * I2C00_SDA = GPIO_0003(Bank=0, bit=3) Func1
+ * I2C00_SCL = GPIO_0004(Bank=0, bit=4) Func1
+ * I2C01_SDA = GPIO_0130(Bank=2, bit=24) Func1
+ * I2C01_SCL = GPIO_0131(Bank=2, bit=25) Func1
+ * I2C04_SDA = GPIO_0143(Bank=3, bit=3) Func1
+ * I2C04_SCL = GPIO_0144(Bank=3, bit=4) Func1
+ * I2C05_SDA = GPIO_0141(Bank=3, bit=1) Func1
+ * I2C05_SDL = GPIO_0142(Bank=3, bit=2) Func1
+ */
+ALTERNATE(PIN_MASK(0, 0x00000018),	GPIO_ALT_FUNC_1,	MODULE_I2C,
+								GPIO_ODR_HIGH)
+ALTERNATE(PIN_MASK(2, 0x03000000),	GPIO_ALT_FUNC_1,	MODULE_I2C,
+								GPIO_ODR_HIGH)
+ALTERNATE(PIN_MASK(3, 0x0000001E),	GPIO_ALT_FUNC_1,	MODULE_I2C,
+								GPIO_ODR_HIGH)
+
+/* Alternate pins for ADC */
+/*
+ * ADC04 - ADC07
+ * GPIO_0204 Func 1 = ADC04 - AMBIET_THERM_IN0
+ * GPIO_0205 Func 1 = ADC05 - VR_THERM_IN
+ * GPIO_0206 Func 1 = ADC06 - DDR_THERM_IN
+ * GPIO_0207 Func 1 = ADC07 - SKIN_THERM_IN1
+ * Bank 4 bits[4:5:6:7]
+ */
+ALTERNATE(PIN_MASK(4, 0x00000F0),	GPIO_ALT_FUNC_1,	MODULE_ADC,
+								GPIO_ANALOG)
+/*
+ * VREF2_ADC_R
+ * GPIO_067 Func 1 = VREF2_ADC
+ * Bank 1 bit [23]
+ */
+ALTERNATE(PIN_MASK(1, 0x0800000),	GPIO_ALT_FUNC_1,	MODULE_ADC,
+								GPIO_ANALOG)
+
+/* Alternate pins for FAN */
+/*
+ * GPIO_050 Func 1 = TACH0 - CPU_TACHO_FAN
+ * GPIO_053 Func 1 = PWM0 - CPU_PWM_FAN
+ * Bank 1 bits[8:11]
+ */
+ALTERNATE(PIN_MASK(1, 0x0000900),	GPIO_ALT_FUNC_1,	MODULE_PWM,
+								GPIO_FLAG_NONE)
+
+/* KB pins */
+/*
+ * MEC1521H-SZ (144 pin package)
+ * KSO00 = GPIO_0040 Func2 bank 1 bit 0
+ * KSO01 = GPIO_0045 Func1 bank 1 bit 5
+ * KSO02 = GPIO_0046 Func1 bank 1 bit 6
+ * KSO03 = GPIO_0047 Func1 bank 1 bit 7
+ * KSO04 = GPIO_0107 Func2 bank 2 bit 7
+ * KSO05 = GPIO_0112 Func1 bank 2 bit 10
+ * KSO06 = GPIO_0113 Func1 bank 2 bit 11
+ * KSO07 = GPIO_0120 Func1 bank 2 bit 16
+ * KSO08 = GPIO_0121 Func2 bank 2 bit 17
+ * KSO09 = GPIO_0122 Func2 bank 2 bit 18
+ * KSO10 = GPIO_0123 Func2 bank 2 bit 19
+ * KSO11 = GPIO_0124 Func2 bank 2 bit 20
+ * KSO12 = GPIO_0125 Func2 bank 2 bit 21
+ * For 8x16 test keyboard add KSO13 - KSO15
+ * KSO13 = GPIO_0126 Func2 bank 2 bit 22
+ * KSO14 = GPIO_0152 Func1 bank 3 bit 10
+ * KSO15 = GPIO_0151 Func2 bank 3 bit 9
+ *
+ * KSI0 = GPIO_0017 Func1 bank 0 bit 15
+ * KSI1 = GPIO_0020 Func1 bank 0 bit 16
+ * KSI2 = GPIO_0021 Func1 bank 0 bit 17
+ * KSI3 = GPIO_0026 Func1 bank 0 bit 22
+ * KSI4 = GPIO_0027 Func1 bank 0 bit 23
+ * KSI5 = GPIO_0030 Func1 bank 0 bit 24
+ * KSI6 = GPIO_0031 Func1 bank 0 bit 25
+ * KSI7 = GPIO_0032 Func1 bank 0 bit 26
+ */
+/* KSO 0 Bank 1, Func2, bit 0 */
+ALTERNATE(PIN_MASK(1, 0x01),		2,	MODULE_KEYBOARD_SCAN,
+							GPIO_ODR_HIGH)
+
+#ifdef CONFIG_KEYBOARD_COL2_INVERTED
+/* KSO 1-3 Bank 1, Func1, bits 5-7 */
+ALTERNATE(PIN_MASK(1, 0xA0),		1,	MODULE_KEYBOARD_SCAN,
+							GPIO_ODR_HIGH)
+GPIO(KBD_KSO2,		PIN(046),	GPIO_OUT_LOW)
+#else
+/* KSO 1-3 Bank 1, Func1, bits 5-7 */
+ALTERNATE(PIN_MASK(1, 0xE0),		1,	MODULE_KEYBOARD_SCAN,
+							GPIO_ODR_HIGH)
+#endif
+
+/* KSO 4, 8-12 Bank 2, Func2, bits 7, 17-21 */
+ALTERNATE(PIN_MASK(2, 0x003E0080),	2,	MODULE_KEYBOARD_SCAN,
+							GPIO_ODR_HIGH)
+/* KSO 5-7, Bank 2, Func1, bits 10-11, 16 */
+ALTERNATE(PIN_MASK(2, 0x00010C00),	1,	MODULE_KEYBOARD_SCAN,
+							GPIO_ODR_HIGH)
+
+/* KSI 0-7, Bank 0, Func1, bit 15-17, 22-26 */
+ALTERNATE(PIN_MASK(0, 0x07C38000),	1,	MODULE_KEYBOARD_SCAN,
+						(GPIO_INPUT | GPIO_PULL_UP))
+
+/*
+ * ESPI_RST_EC_R_N# - GPIO_0061 Func 1, Bank 1 bit[17]
+ * ESPI_ALERT0_EC_R_N# - GPIO_0063 Func 1, Bank 1 bit[19]
+ * ESPI_CLK_EC_R    - GPIO_0065 Func 1, Bank 1 bit[21]
+ * ESPI_CS0_EC_R_N# - GPIO_0066 Func 1, Bank 1 bit[22]
+ * ESPI_IO0_EC_R    - GPIO_0070 Func 1, Bank 1 bit[24]
+ * ESPI_IO1_EC_R    - GPIO_0071 Func 1, Bank 1 bit[25]
+ * ESPI_IO2_EC_R    - GPIO_0072 Func 1, Bank 1 bit[26]
+ * ESPI_IO3_EC_R    - GPIO_0073 Func 1, Bank 1 bit[27]
+ */
+ALTERNATE(PIN_MASK(1, 0x0F6A0000),	1,	MODULE_LPC,	GPIO_FLAG_NONE)
diff --git a/board/adlrvpp_mchp1521/vif_override.xml b/board/adlrvpp_mchp1521/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/adlrvpp_mchp1521/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/adlrvpp_mchp1727/board.c b/board/adlrvpp_mchp1727/board.c
new file mode 100644
index 0000000000..1d0189d90b
--- /dev/null
+++ b/board/adlrvpp_mchp1727/board.c
@@ -0,0 +1,139 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel ADL-P-RVP-MCHP1727 board-specific configuration */
+#include "button.h"
+#include "fusb302.h"
+#include "i2c_bitbang.h"
+#include "lid_switch.h"
+#include "pca9675.h"
+#include "power.h"
+#include "power_button.h"
+#include "spi.h"
+#include "spi_chip.h"
+#include "switch.h"
+#include "tablet_mode.h"
+#include "uart.h"
+#include "usb_pd_tcpm.h"
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/******************************************************************************/
+/* I2C ports */
+const struct i2c_port_t i2c_ports[] = {
+	[I2C_CHAN_BATT_CHG] = {
+		.name = "batt_chg",
+		.port = I2C_PORT_CHARGER,
+		.kbps = 100,
+		.scl = GPIO_SMB_BS_CLK,
+		.sda = GPIO_SMB_BS_DATA,
+	},
+	[I2C_CHAN_TYPEC_0] = {
+		.name = "typec_0",
+		.port = I2C_PORT_TYPEC_0,
+		.kbps = 400,
+		.scl = GPIO_USBC_TCPC_I2C_CLK_P0,
+		.sda = GPIO_USBC_TCPC_I2C_DATA_P0,
+	},
+	[I2C_CHAN_TYPEC_1] = {
+		.name = "typec_1",
+		.port = I2C_PORT_TYPEC_1,
+		.kbps = 400,
+		.scl = GPIO_USBC_TCPC_I2C_CLK_P2,
+		.sda = GPIO_USBC_TCPC_I2C_DATA_P2,
+	},
+#if defined(HAS_TASK_PD_C2)
+	[I2C_CHAN_TYPEC_2] = {
+		.name = "typec_2",
+		.port = I2C_PORT_TYPEC_2,
+		.kbps = 400,
+		.scl = GPIO_USBC_TCPC_I2C_CLK_P1,
+		.sda = GPIO_USBC_TCPC_I2C_DATA_P1,
+	},
+	[I2C_CHAN_TYPEC_3] = {
+		.name = "typec_3",
+		.port = I2C_PORT_TYPEC_3,
+		.kbps = 400,
+		.scl = GPIO_USBC_TCPC_I2C_CLK_P3,
+		.sda = GPIO_USBC_TCPC_I2C_DATA_P3,
+	},
+#endif
+};
+BUILD_ASSERT(ARRAY_SIZE(i2c_ports) == I2C_CHAN_COUNT);
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+/* I2C access in polling mode before task is initialized */
+#ifdef CONFIG_I2C_BITBANG
+const struct i2c_port_t i2c_bitbang_ports[] = {
+	[I2C_BITBANG_CHAN_BRD_ID] = {
+		.name = "bitbang_brd_id",
+		.port = I2C_PORT_CHARGER,
+		.kbps = 100,
+		.scl = GPIO_SMB_BS_CLK,
+		.sda = GPIO_SMB_BS_DATA,
+		.drv = &bitbang_drv,
+	},
+	[I2C_BITBANG_CHAN_IOEX_0] = {
+		.name = "bitbang_ioex_0",
+		.port = I2C_PORT_TYPEC_0,
+		.kbps = 100,
+		.scl = GPIO_USBC_TCPC_I2C_CLK_P0,
+		.sda = GPIO_USBC_TCPC_I2C_DATA_P0,
+		.drv = &bitbang_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(i2c_bitbang_ports) == I2C_BITBANG_CHAN_COUNT);
+const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
+#endif
+
+/* USB-C TCPC Configuration */
+const struct tcpc_config_t tcpc_config[] = {
+	[TYPE_C_PORT_0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TYPEC_0,
+			.addr_flags = I2C_ADDR_FUSB302_TCPC_AIC,
+		},
+		.drv = &fusb302_tcpm_drv,
+	},
+#if defined(HAS_TASK_PD_C1)
+	[TYPE_C_PORT_1] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TYPEC_1,
+			.addr_flags = I2C_ADDR_FUSB302_TCPC_AIC,
+		},
+		.drv = &fusb302_tcpm_drv,
+	},
+#endif
+#if defined(HAS_TASK_PD_C2)
+	[TYPE_C_PORT_2] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TYPEC_2,
+			.addr_flags = I2C_ADDR_FUSB302_TCPC_AIC,
+		},
+		.drv = &fusb302_tcpm_drv,
+	},
+#endif
+#if defined(HAS_TASK_PD_C3)
+	[TYPE_C_PORT_3] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TYPEC_3,
+			.addr_flags = I2C_ADDR_FUSB302_TCPC_AIC,
+		},
+		.drv = &fusb302_tcpm_drv,
+	},
+#endif
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == CONFIG_USB_PD_PORT_MAX_COUNT);
+
+/* SPI devices */
+const struct spi_device_t spi_devices[] = {
+	{ QMSPI0_PORT, 4, GPIO_QMSPI_CS0 },
+};
+const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
diff --git a/board/adlrvpp_mchp1727/board.h b/board/adlrvpp_mchp1727/board.h
new file mode 100644
index 0000000000..ad4d189b42
--- /dev/null
+++ b/board/adlrvpp_mchp1727/board.h
@@ -0,0 +1,161 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel ADL-P-RVP-MCHP1727 board-specific configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* MCHP EC variant */
+#define VARIANT_INTELRVP_EC_MCHP
+
+/* UART for EC console */
+#undef CONFIG_UART_CONSOLE
+#define CONFIG_UART_CONSOLE 0
+
+#include "adlrvp.h"
+
+/* Heavy I2C communication as POR, increase WDT expired time */
+#undef CONFIG_WATCHDOG_PERIOD_MS
+#define CONFIG_WATCHDOG_PERIOD_MS 5000
+
+/*
+ * External parallel crystal between XTAL1 and XTAL2 pins.
+ *   #define CONFIG_CLOCK_SRC_EXTERNAL
+ *   #define CONFIG_CLOCK_CRYSTAL
+ * External single ended 32KHz 50% duty cycle input clock.
+ *   #define CONFIG_CLOCK_SRC_EXTERNAL
+ *   #undef CONFIG_CLOCK_CRYSTAL
+ * Use internal silicon 32KHz oscillator
+ *   #undef CONFIG_CLOCK_SRC_EXTERNAL
+ *   CONFIG_CLOCK_CRYSTAL is a don't care
+ */
+#undef CONFIG_CLOCK_SRC_EXTERNAL
+
+/* MEC1727 integrated SPI chip 512KB SST25PF040C */
+#define CONFIG_SPI_FLASH_W25X40
+
+/*
+ * Enable extra SPI flash and generic SPI
+ * commands via EC UART
+ */
+#define CONFIG_CMD_SPI_FLASH
+#define CONFIG_CMD_SPI_XFER
+
+/* MEC172x does not apply GP-SPI controllers */
+#undef CONFIG_MCHP_GPSPI
+
+/* ADC channels */
+#undef ADC_TEMP_SNS_AMBIENT_CHANNEL
+#undef ADC_TEMP_SNS_DDR_CHANNEL
+#undef ADC_TEMP_SNS_SKIN_CHANNEL
+#undef ADC_TEMP_SNS_VR_CHANNEL
+#define ADC_TEMP_SNS_AMBIENT_CHANNEL CHIP_ADC_CH3
+#define ADC_TEMP_SNS_DDR_CHANNEL CHIP_ADC_CH5
+#define ADC_TEMP_SNS_SKIN_CHANNEL CHIP_ADC_CH4
+#define ADC_TEMP_SNS_VR_CHANNEL CHIP_ADC_CH0
+
+/*
+ * ADC maximum voltage is a board level configuration.
+ * MEC172x ADC can use an external 3.0 or 3.3V reference with
+ * maximum values up to the reference voltage.
+ * The ADC maximum voltage depends upon the external reference
+ * voltage connected to MEC172x.
+ */
+#undef ADC_MAX_MVOLT
+#define ADC_MAX_MVOLT 3300
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+/* Power sequencing */
+#define GPIO_EC_SPI_OE_N GPIO_EC_SPI_OE_MECC
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_ALL_SYS_PWRGD
+#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_PWRGD
+#define GPIO_PCH_SLP_S0_L GPIO_PCH_SLP_S0_N
+#define GPIO_PG_EC_DSW_PWROK GPIO_VCCPDSW_3P3
+#define GPIO_SLP_SUS_L GPIO_PM_SLP_SUS_EC_N
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_PCH_RSMRST_L GPIO_PM_RSMRST_N
+#define GPIO_PCH_PWRBTN_L GPIO_PM_PWRBTN_N
+#define GPIO_EN_PP3300_A GPIO_EC_DS3
+#define GPIO_SYS_PWROK_EC GPIO_SYS_PWROK
+#define GPIO_PCH_DSW_PWROK GPIO_EC_DSW_PWROK
+
+/* Sensors */
+#define GPIO_TABLET_MODE_L GPIO_SLATE_MODE_INDICATION
+#define GPIO_CPU_PROCHOT GPIO_PROCHOT_EC_N
+
+/* Buttons */
+#define GPIO_LID_OPEN GPIO_SMC_LID
+#define GPIO_VOLUME_UP_L GPIO_VOLUME_UP
+#define GPIO_VOLUME_DOWN_L GPIO_VOL_DN_EC
+#define GPIO_POWER_BUTTON_L GPIO_MECH_PWR_BTN_ODL
+
+/* H1 */
+#define GPIO_WP_L GPIO_EC_FLASH_WP_ODL
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+
+/* AC & Battery */
+#define GPIO_DC_JACK_PRESENT GPIO_STD_ADP_PRSNT
+#define GPIO_AC_PRESENT GPIO_BC_ACOK
+#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BAT_DET
+
+/* eSPI/Host communication */
+#define GPIO_ESPI_RESET_L GPIO_LPC_ESPI_RST_N
+#define GPIO_PCH_WAKE_L GPIO_SMC_WAKE_SCI_N_MECC
+#define GPIO_EC_INT_L GPIO_EC_PCH_MKBP_INT_ODL
+
+/* LED */
+#define GPIO_BAT_LED_RED_L GPIO_LED_1_L
+#define GPIO_PWR_LED_WHITE_L GPIO_LED_2_L
+
+/* FAN */
+#define GPIO_FAN_POWER_EN GPIO_THERM_SEN_MECC
+
+/* Charger */
+#define I2C_PORT_CHARGER MCHP_I2C_PORT0
+
+/* Battery */
+#define I2C_PORT_BATTERY MCHP_I2C_PORT0
+
+/* Board ID */
+#define I2C_PORT_PCA9555_BOARD_ID_GPIO MCHP_I2C_PORT0
+
+/* Port 80 */
+#define I2C_PORT_PORT80 MCHP_I2C_PORT0
+
+/* USB-C I2C */
+#define I2C_PORT_TYPEC_0 MCHP_I2C_PORT6
+/*
+ * Note: I2C for Type-C Port-1 is swapped with Type-C Port-2
+ *       on the RVP to reduce BOM stuffing options.
+ */
+#define I2C_PORT_TYPEC_1 MCHP_I2C_PORT3
+#if defined(HAS_TASK_PD_C2)
+#define I2C_PORT_TYPEC_2 MCHP_I2C_PORT7
+#define I2C_PORT_TYPEC_3 MCHP_I2C_PORT2
+#endif
+
+#ifndef __ASSEMBLER__
+
+enum adlrvp_i2c_channel {
+	I2C_CHAN_BATT_CHG,
+	I2C_CHAN_TYPEC_0,
+	I2C_CHAN_TYPEC_1,
+#if defined(HAS_TASK_PD_C2)
+	I2C_CHAN_TYPEC_2,
+	I2C_CHAN_TYPEC_3,
+#endif
+	I2C_CHAN_COUNT,
+};
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/adlrvpp_mchp1727/build.mk b/board/adlrvpp_mchp1727/build.mk
new file mode 100644
index 0000000000..0527f50d24
--- /dev/null
+++ b/board/adlrvpp_mchp1727/build.mk
@@ -0,0 +1,20 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Intel ADL-P-RVP-MCHP1727 board-specific configuration
+#
+
+# the IC is Microchip MEC172x 416 KB total SRAM
+# MEC1723SZ variant is 144 pin, loads from external SPI flash
+# MEC1727SZ variant is 144 pin, loads from 512KB internal SPI flash
+# external SPI is 512KB
+# clock is Internal ROSC
+CHIP:=mchp
+CHIP_FAMILY:=mec172x
+CHIP_VARIANT:=mec1727sz
+CHIP_SPI_SIZE_KB:=512
+BASEBOARD:=intelrvp
+
+board-y=board.o
diff --git a/board/adlrvpp_mchp1727/ec.tasklist b/board/adlrvpp_mchp1727/ec.tasklist
new file mode 100644
index 0000000000..3ae4784397
--- /dev/null
+++ b/board/adlrvpp_mchp1727/ec.tasklist
@@ -0,0 +1,25 @@
+/*
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Intel ADL-P-RVP-MCHP1727 board-specific configuration.
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/adlrvpp_mchp1727/gpio.inc b/board/adlrvpp_mchp1727/gpio.inc
new file mode 100644
index 0000000000..582da4c46a
--- /dev/null
+++ b/board/adlrvpp_mchp1727/gpio.inc
@@ -0,0 +1,262 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel ADL-P-RVP-MCHP1727 board-specific configuration */
+
+#include "baseboard/intelrvp/adlrvp_ioex_gpio.inc"
+/* include common gpio.inc under chip/mchp/lfw/... */
+#include "chip/mchp/lfw/gpio.inc"
+
+/* Power sequencing interrupts */
+GPIO_INT(ALL_SYS_PWRGD,		PIN(057), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(RSMRST_PWRGD,		PIN(0221), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PCH_SLP_S0_N,		PIN(0243), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCPDSW_3P3,		PIN(0201), GPIO_INT_BOTH, power_signal_interrupt)
+/* TODO: GPIO_INT(VCCST_PWRGD_MECC,	PIN(0207), GPIO_INT_BOTH, power_signal_interrupt) */
+GPIO_INT(PM_SLP_SUS_EC_N, 	PIN(0227), GPIO_INT_BOTH, power_signal_interrupt)
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+GPIO_INT(PM_SLP_S3_N,		PIN(0161), GPIO_INT_BOTH, power_signal_interrupt)
+#else
+GPIO(PM_SLP_S3_N,		PIN(0161), GPIO_INPUT)
+#endif
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
+GPIO_INT(PM_SLP_S4_N,		PIN(0162), GPIO_INT_BOTH, power_signal_interrupt)
+#else
+GPIO(PM_SLP_S4_N,		PIN(0162), GPIO_INPUT)
+#endif
+
+/* Button interrupts */
+GPIO_INT(VOLUME_UP,		PIN(036), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(VOL_DN_EC,		PIN(0254), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(SMC_LID,		PIN(0226), GPIO_INT_BOTH | GPIO_PULL_UP, lid_interrupt)
+GPIO_INT(MECH_PWR_BTN_ODL,	PIN(0115), GPIO_INT_BOTH, power_button_interrupt)
+
+/* DC / AC interrupts, DC Jack presence coming from +VADP_OUT */
+GPIO_INT(STD_ADP_PRSNT, 	PIN(043), GPIO_INT_BOTH, board_dc_jack_interrupt) /* DC_JACK_PRESENT */
+GPIO_INT(BC_ACOK,		PIN(0156), GPIO_INT_BOTH, extpower_interrupt) /* AC Present */
+
+/* Sensor interrupt */
+GPIO_INT(SLATE_MODE_INDICATION,	PIN(0222), GPIO_INT_BOTH, gmr_tablet_switch_isr)
+
+/* Flash WP interrupt */
+GPIO_INT(EC_FLASH_WP_ODL,	PIN(014), GPIO_INT_BOTH, switch_interrupt)
+
+/* Case Closed Debug Mode interrupt */
+GPIO_INT(CCD_MODE_ODL,		PIN(0175), GPIO_INT_BOTH, board_connect_c0_sbu)
+
+/* UART0 RX interrupt, RX input wake event */
+GPIO_INT(UART0_RX, PIN(0105), GPIO_INT_BOTH_DSLEEP | GPIO_PULL_UP, uart_deepsleep_interrupt)
+
+/* USB-C interrupts */
+GPIO_INT(USBC_TCPC_ALRT_P0,	PIN(0143), GPIO_INT_BOTH, tcpc_alert_event)
+GPIO_INT(USBC_TCPC_PPC_ALRT_P0, PIN(0240), GPIO_INT_BOTH, ppc_interrupt)
+
+#if defined(HAS_TASK_PD_C1)
+GPIO_INT(USBC_TCPC_ALRT_P1,	PIN(0241), GPIO_INT_BOTH, tcpc_alert_event)
+GPIO_INT(USBC_TCPC_PPC_ALRT_P1, PIN(0101), GPIO_INT_BOTH, ppc_interrupt)
+#else
+GPIO(USBC_TCPC_ALRT_P1,	PIN(0241), GPIO_INPUT)
+GPIO(USBC_TCPC_PPC_ALRT_P1,	PIN(0101), GPIO_INPUT)
+#endif
+
+#if defined(HAS_TASK_PD_C2)
+/* w/o rework: USBC_TCPC_ALRT_P2 -> VCI_OVRD_IN */
+GPIO_INT(USBC_TCPC_ALRT_P2,	PIN(0130), GPIO_INT_BOTH, tcpc_alert_event)
+GPIO_INT(USBC_TCPC_PPC_ALRT_P2, PIN(0144), GPIO_INT_BOTH, ppc_interrupt)
+#else
+GPIO(USBC_TCPC_ALRT_P2,	PIN(0130), GPIO_INPUT)
+GPIO(USBC_TCPC_PPC_ALRT_P2,	PIN(0144), GPIO_INPUT)
+#endif
+
+#if defined(HAS_TASK_PD_C3)
+GPIO_INT(USBC_TCPC_ALRT_P3,	PIN(0242), GPIO_INT_BOTH, tcpc_alert_event)
+GPIO_INT(USBC_TCPC_PPC_ALRT_P3, PIN(0142), GPIO_INT_BOTH, ppc_interrupt)
+#else
+GPIO(USBC_TCPC_ALRT_P3,	PIN(0242), GPIO_INPUT)
+GPIO(USBC_TCPC_PPC_ALRT_P3,	PIN(0142), GPIO_INPUT)
+#endif
+
+/* Host communication GPIOs */
+GPIO(SMC_WAKE_SCI_N_MECC,	PIN(051), GPIO_ODR_HIGH)
+GPIO(EC_PCH_MKBP_INT_ODL,	PIN(0127), GPIO_ODR_HIGH)
+#ifndef CONFIG_HOST_INTERFACE_ESPI
+GPIO(LPC_ESPI_RST_N,		PIN(061), GPIO_INPUT)
+GPIO(PLT_RST_L, 		PIN(052), GPIO_INPUT) /* PCH_PLTRST_L */
+#endif
+
+/* Prochot GPIO */
+GPIO(PROCHOT_EC_N,		PIN(002), GPIO_INPUT)
+
+/* Power sequencing GPIOs */
+GPIO(SYS_RST_ODL,		PIN(060), GPIO_ODR_HIGH)
+GPIO(PM_RSMRST_N,		PIN(054), GPIO_OUT_LOW)
+GPIO(PM_PWRBTN_N,		PIN(016), GPIO_ODR_HIGH)
+/* w/o rework: EC_SPI_OE_MECC -> BGPO0 */
+GPIO(EC_SPI_OE_MECC,		PIN(042), GPIO_OUT_LOW)
+/* w/o rework: EC_DS3 -> VCI_OUT2 */
+GPIO(EC_DS3,			PIN(025), GPIO_OUT_LOW)
+UNIMPLEMENTED(EN_PP5000)
+
+/* PCH_PWROK_EC is an input, as it's driven by the Silego chip on RVP */
+GPIO(PCH_PWROK_EC,	PIN(0106), GPIO_INPUT)
+GPIO(SYS_PWROK,		PIN(0202), GPIO_OUT_LOW)
+GPIO(EC_DSW_PWROK,	PIN(034), GPIO_OUT_LOW)
+
+/* H1 GPIOs */
+GPIO(EC_H1_PACKET_MODE,		PIN(035), GPIO_OUT_LOW)
+GPIO(EC_ENTERING_RW,		PIN(0102), GPIO_OUT_LOW)
+
+/* Battery present */
+GPIO(BAT_DET,		PIN(0206), GPIO_INPUT)
+
+/* EDP */
+GPIO(EDP_BKLT_EN_MECC,	PIN(022), GPIO_OUT_HIGH)
+
+/* LED */
+GPIO(LED_1_L,		PIN(0157), GPIO_OUT_HIGH)
+GPIO(LED_2_L,		PIN(0153), GPIO_OUT_HIGH)
+
+/* FAN control pins */
+GPIO(THERM_SEN_MECC,	PIN(0141), GPIO_OUT_LOW)
+
+/*
+ * I2C pins should be configure as inputs until I2C module is
+ * initialized. This will avoid driving the lines unintentionally.
+ */
+GPIO(SMB_BS_CLK,		PIN(004), GPIO_INPUT)	/* I2C00_SCL */
+GPIO(SMB_BS_DATA,		PIN(003), GPIO_INPUT)	/* I2C00_SDA */
+GPIO(USBC_TCPC_I2C_CLK_P0,	PIN(0140), GPIO_INPUT)	/* I2C06_SCL */
+GPIO(USBC_TCPC_I2C_DATA_P0,	PIN(0132), GPIO_INPUT)	/* I2C06_SDA */
+GPIO(USBC_TCPC_I2C_CLK_P1,	PIN(013), GPIO_INPUT)	/* I2C07_SCL */
+GPIO(USBC_TCPC_I2C_DATA_P1,	PIN(012), GPIO_INPUT)	/* I2C07_SDA */
+GPIO(USBC_TCPC_I2C_CLK_P2,	PIN(010), GPIO_INPUT)	/* I2C03_SCL */
+GPIO(USBC_TCPC_I2C_DATA_P2,	PIN(007), GPIO_INPUT)	/* I2C03_SDA */
+GPIO(USBC_TCPC_I2C_CLK_P3,	PIN(0155), GPIO_INPUT)	/* I2C02_SCL */
+GPIO(USBC_TCPC_I2C_DATA_P3,	PIN(0154), GPIO_INPUT)	/* I2C02_SDA */
+
+/* Unused pins */
+GPIO(SML1_CLK_MECC,		PIN(0131), GPIO_INPUT)
+GPIO(CPU_CAT_ERR_MECC,		PIN(000), GPIO_INPUT)
+GPIO(ESPI_ALERT0_N,		PIN(063), GPIO_INPUT)
+GPIO(BATT_DISABLE_EC,		PIN(067), GPIO_INPUT)
+/* Unused: GPIO(SLP_S0_CS_N,		PIN(nVCI_IN0), GPIO_INPUT) */
+GPIO(CPU_C10_GATE_MECC,		PIN(023), GPIO_INPUT)
+GPIO(SMC_SDOWN_MECC,		PIN(0255), GPIO_INPUT)
+GPIO(STD_ADPT_CNTRL_GPIO,	PIN(0244), GPIO_INPUT)
+GPIO(SMC_ONOFF_N,		PIN(0114), GPIO_INPUT) /* Power button interrupt without H1 */
+GPIO(SUSWARN,			PIN(024), GPIO_INPUT)
+GPIO(ME_G3_TO_M3_EC,		PIN(033), GPIO_INPUT)
+
+/* Alternate pins for I2C */
+/* I2C pins alternate functions for ports 0, 2-3, 6-7
+ * Configure I2C ports as I2C alternate function.
+ * If board does not use external pull-ups then change GPIO flags
+ * to enable internal pull-ups.
+ * I2C00_SDA = GPIO_0003(Bank=0, bit=3) Func1
+ * I2C00_SCL = GPIO_0004(Bank=0, bit=4) Func1
+ * I2C02_SDA = GPIO_0154(Bank=3, bit=12) Func1
+ * I2C02_SCL = GPIO_0155(Bank=3, bit=13) Func1
+ * I2C03_SDA = GPIO_0007(Bank=0, bit=7) Func1
+ * I2C03_SDL = GPIO_0010(Bank=0, bit=8) Func1
+ * I2C06_SDA = GPIO_0132(Bank=2, bit=26) Func1
+ * I2C06_SCL = GPIO_0140(Bank=3, bit=0) Func1
+ * I2C07_SDA = GPIO_0012(Bank=0, bit=10) Func1
+ * I2C07_SDL = GPIO_0013(Bank=0, bit=11) Func1
+ */
+ALTERNATE(PIN_MASK(0,  0x00000D98), 1, MODULE_I2C, GPIO_ODR_HIGH)
+ALTERNATE(PIN_MASK(2,  0x04000000), 1, MODULE_I2C, GPIO_ODR_HIGH)
+ALTERNATE(PIN_MASK(3,  0x00003001), 1, MODULE_I2C, GPIO_ODR_HIGH)
+
+/* Alternate pins for ADC */
+/* VR_TMP/V_1P05 - GPIO44, SKIN_THERM_IN_EC - GPIO43, AMBIENT_TEMP - GPIO42, DDR_TEMP/EC_5V - GPIO41 */
+/* ADC pins
+ * GPIO200/ADC00 = VR_TMP/V_1P05
+ * GPIO203/ADC03 = AMBIENT_TEMP
+ * GPIO204/ADC04 = SKIN_THERM_IN_EC
+ * GPIO205/ADC05 = DDR_TEMP/EC_5V
+ * ADC00 = GPIO_0200(Bank=4, bit=0) Func1
+ * ADC03 = GPIO_0203(Bank=4, bit=3) Func1
+ * ADC04 = GPIO_0204(Bank=4, bit=4) Func1
+ * ADC05 = GPIO_0205(Bank=4, bit=5) Func1
+ */
+ALTERNATE(PIN_MASK(4,  0x0039), 1, MODULE_ADC, GPIO_ANALOG)
+
+/*
+ * Alternate pins for RPM-FAN control
+ *
+ * GPIO050/GTACH0 = CPU_TACHO_FAN
+ * GPIO053/GPWM0 = CPU_PWM_FAN
+ * GTACH0 = GPIO_050(Bank=1, bit=8) Func2
+ * GPWM0 = GPIO_053(Bank=1, bit=11) Func3
+ */
+ALTERNATE(PIN_MASK(1, 0x0100), 2, MODULE_PWM, GPIO_FLAG_NONE)
+ALTERNATE(PIN_MASK(1, 0x0800), 3, MODULE_PWM, GPIO_FLAG_NONE)
+
+/* Keyboard pins */
+#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
+#define GPIO_KB_OUTPUT (GPIO_ODR_HIGH)
+#define GPIO_KB_OUTPUT_COL2 (GPIO_OUT_LOW)
+/*
+ * MEC172xH-SZ (144 pin package)
+ * KSO00 = GPIO_0040 Func2 bank 1 bit 0
+ * KSO01 = GPIO_0045 Func1 bank 1 bit 5
+ * KSO02 = GPIO_0046 Func1 bank 1 bit 6
+ * KSO03 = GPIO_0047 Func1 bank 1 bit 7
+ * KSO04 = GPIO_0107 Func2 bank 2 bit 7
+ * KSO05 = GPIO_0112 Func1 bank 2 bit 10
+ * KSO06 = GPIO_0113 Func1 bank 2 bit 11
+ * KSO07 = GPIO_0120 Func1 bank 2 bit 16
+ * KSO08 = GPIO_0121 Func2 bank 2 bit 17
+ * KSO09 = GPIO_0122 Func2 bank 2 bit 18
+ * KSO10 = GPIO_0123 Func2 bank 2 bit 19
+ * KSO11 = GPIO_0124 Func2 bank 2 bit 20
+ * KSO12 = GPIO_0125 Func2 bank 2 bit 21
+ * For 8x16 keyboard add KSO13 - KSO15
+ * KSO13 = GPIO_0126 Func2 bank 2 bit 22
+ * KSO14 = GPIO_0152 Func1 bank 3 bit 10
+ * KSO15 = GPIO_0151 Func2 bank 3 bit 9
+ *
+ * KSI0 = GPIO_0017 Func1 bank 0 bit 15
+ * KSI1 = GPIO_0020 Func1 bank 0 bit 16
+ * KSI2 = GPIO_0021 Func1 bank 0 bit 17
+ * KSI3 = GPIO_0026 Func1 bank 0 bit 22
+ * KSI4 = GPIO_0027 Func1 bank 0 bit 23
+ * KSI5 = GPIO_0030 Func1 bank 0 bit 24
+ * KSI6 = GPIO_0031 Func1 bank 0 bit 25
+ * KSI7 = GPIO_0032 Func1 bank 0 bit 26
+ */
+/* KSO 0 Bank 1, Func2, bit 0 */
+ALTERNATE(PIN_MASK(1, 0x01), 2, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
+
+#ifdef CONFIG_KEYBOARD_COL2_INVERTED
+/* KSO 1-3 Bank 1, Func1, bits 5-7 */
+ALTERNATE(PIN_MASK(1, 0xA0), 1, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
+GPIO(KBD_KSO2, PIN(046), GPIO_KB_OUTPUT_COL2)
+#else
+/* KSO 1-3 Bank 1, Func1, bits 5-7 */
+ALTERNATE(PIN_MASK(1, 0xE0), 1, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
+#endif
+
+/* KSO 4, 8-12 Bank 2, Func2, bits 7, 17-21 */
+ALTERNATE(PIN_MASK(2, 0x003E0080), 2, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
+/* KSO 5-7, Bank 2, Func1, bits 10-11, 16 */
+ALTERNATE(PIN_MASK(2, 0x00010C00), 1, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
+
+/* KSI 0-7, Bank 0, Func1, bit 15-17, 22-26 */
+ALTERNATE(PIN_MASK(0, 0x07C38000), 1, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)
+
+/*
+ * ESPI_RESET# - GPIO_0061 Func 1, Bank 1 bit[17]
+ * ESPI_ALERT# - GPIO_0063 Func 1, Bank 1 bit[19]
+ * ESPI_CLK    - GPIO_0065 Func 1, Bank 1 bit[21]
+ * ESPI_CS#    - GPIO_0066 Func 1, Bank 1 bit[22]
+ * ESPI_IO0    - GPIO_0070 Func 1, Bank 1 bit[24]
+ * ESPI_IO1    - GPIO_0071 Func 1, Bank 1 bit[25]
+ * ESPI_IO2    - GPIO_0072 Func 1, Bank 1 bit[26]
+ * ESPI_IO3    - GPIO_0073 Func 1, Bank 1 bit[27]
+ */
+ALTERNATE(PIN_MASK(1, 0x0F6A0000), 1, MODULE_LPC, 0)
diff --git a/board/adlrvpp_mchp1727/vif_override.xml b/board/adlrvpp_mchp1727/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/adlrvpp_mchp1727/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/adlrvpp_npcx/board.c b/board/adlrvpp_npcx/board.c
new file mode 100644
index 0000000000..9736f81807
--- /dev/null
+++ b/board/adlrvpp_npcx/board.c
@@ -0,0 +1,128 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel ADLRVP-NPCX board-specific configuration */
+#include "button.h"
+#include "fusb302.h"
+#include "i2c_bitbang.h"
+#include "lid_switch.h"
+#include "pca9675.h"
+#include "power.h"
+#include "power_button.h"
+#include "switch.h"
+#include "tablet_mode.h"
+#include "uart.h"
+#include "usb_pd_tcpm.h"
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/******************************************************************************/
+/* I2C ports */
+const struct i2c_port_t i2c_ports[] = {
+	[I2C_CHAN_BATT_CHG] = {
+		.name = "batt_chg",
+		.port = I2C_PORT_CHARGER,
+		.kbps = 100,
+		.scl = GPIO_SMB_BS_CLK,
+		.sda = GPIO_SMB_BS_DATA,
+	},
+	[I2C_CHAN_TYPEC_0] = {
+		.name = "typec_0",
+		.port = I2C_PORT_TYPEC_0,
+		.kbps = 400,
+		.scl = GPIO_USBC_TCPC_I2C_CLK_P0,
+		.sda = GPIO_USBC_TCPC_I2C_DATA_P0,
+	},
+	[I2C_CHAN_TYPEC_1] = {
+		.name = "typec_1",
+		.port = I2C_PORT_TYPEC_1,
+		.kbps = 400,
+		.scl = GPIO_USBC_TCPC_I2C_CLK_P2,
+		.sda = GPIO_USBC_TCPC_I2C_DATA_P2,
+	},
+#if defined(HAS_TASK_PD_C2)
+	[I2C_CHAN_TYPEC_2] = {
+		.name = "typec_2",
+		.port = I2C_PORT_TYPEC_2,
+		.kbps = 400,
+		.scl = GPIO_USBC_TCPC_I2C_CLK_P1,
+		.sda = GPIO_USBC_TCPC_I2C_DATA_P1,
+	},
+#endif
+#if defined(HAS_TASK_PD_C3)
+	[I2C_CHAN_TYPEC_3] = {
+		.name = "typec_3",
+		.port = I2C_PORT_TYPEC_3,
+		.kbps = 400,
+		.scl = GPIO_USBC_TCPC_I2C_CLK_P3,
+		.sda = GPIO_USBC_TCPC_I2C_DATA_P3,
+	},
+#endif
+};
+BUILD_ASSERT(ARRAY_SIZE(i2c_ports) == I2C_CHAN_COUNT);
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+const struct i2c_port_t i2c_bitbang_ports[] = {
+	[I2C_BITBANG_CHAN_BRD_ID] = {
+		.name = "bitbang_brd_id",
+		.port = I2C_PORT_CHARGER,
+		.kbps = 100,
+		.scl = GPIO_SMB_BS_CLK,
+		.sda = GPIO_SMB_BS_DATA,
+		.drv = &bitbang_drv,
+	},
+	[I2C_BITBANG_CHAN_IOEX_0] = {
+		.name = "bitbang_ioex_0",
+		.port = I2C_PORT_TYPEC_0,
+		.kbps = 100,
+		.scl = GPIO_USBC_TCPC_I2C_CLK_P0,
+		.sda = GPIO_USBC_TCPC_I2C_DATA_P0,
+		.drv = &bitbang_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(i2c_bitbang_ports) == I2C_BITBANG_CHAN_COUNT);
+const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
+
+/* USB-C TCPC Configuration */
+const struct tcpc_config_t tcpc_config[] = {
+	[TYPE_C_PORT_0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TYPEC_0,
+			.addr_flags = I2C_ADDR_FUSB302_TCPC_AIC,
+		},
+		.drv = &fusb302_tcpm_drv,
+	},
+	[TYPE_C_PORT_1] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TYPEC_1,
+			.addr_flags = I2C_ADDR_FUSB302_TCPC_AIC,
+		},
+		.drv = &fusb302_tcpm_drv,
+	},
+#if defined(HAS_TASK_PD_C2)
+	[TYPE_C_PORT_2] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TYPEC_2,
+			.addr_flags = I2C_ADDR_FUSB302_TCPC_AIC,
+		},
+		.drv = &fusb302_tcpm_drv,
+	},
+#endif
+#if defined(HAS_TASK_PD_C3)
+	[TYPE_C_PORT_3] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TYPEC_3,
+			.addr_flags = I2C_ADDR_FUSB302_TCPC_AIC,
+		},
+		.drv = &fusb302_tcpm_drv,
+	},
+#endif
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == CONFIG_USB_PD_PORT_MAX_COUNT);
diff --git a/board/adlrvpp_npcx/board.h b/board/adlrvpp_npcx/board.h
new file mode 100644
index 0000000000..ff214ddec2
--- /dev/null
+++ b/board/adlrvpp_npcx/board.h
@@ -0,0 +1,112 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel ADL-P-RVP-NPCX board-specific configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* ITE EC variant */
+#define VARIANT_INTELRVP_EC_NPCX
+
+#include "adlrvp.h"
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+/* Power sequencing */
+#define GPIO_EC_SPI_OE_N GPIO_EC_SPI_OE_MECC
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_ALL_SYS_PWRGD
+#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_PWRGD
+#define GPIO_PCH_SLP_S0_L GPIO_PCH_SLP_S0_N
+#define GPIO_PG_EC_DSW_PWROK GPIO_VCCPDSW_3P3
+#define GPIO_SLP_SUS_L GPIO_PM_SLP_SUS_EC_N
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_PCH_RSMRST_L GPIO_PM_RSMRST_N
+#define GPIO_PCH_PWRBTN_L GPIO_PM_PWRBTN_N
+#define GPIO_EN_PP3300_A GPIO_EC_DS3
+#define GPIO_SYS_PWROK_EC GPIO_SYS_PWROK
+#define GPIO_PCH_DSW_PWROK GPIO_EC_DSW_PWROK
+
+/* Sensors */
+#define GPIO_TABLET_MODE_L GPIO_SLATE_MODE_INDICATION
+#define GPIO_CPU_PROCHOT GPIO_PROCHOT_EC_N
+
+/* Buttons */
+#define GPIO_LID_OPEN GPIO_SMC_LID
+#define GPIO_VOLUME_UP_L GPIO_VOLUME_UP
+#define GPIO_VOLUME_DOWN_L GPIO_VOL_DN_EC
+#define GPIO_POWER_BUTTON_L GPIO_MECH_PWR_BTN_ODL
+
+/* H1 */
+#define GPIO_WP_L GPIO_EC_FLASH_WP_ODL
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+
+/* AC & Battery */
+#define GPIO_DC_JACK_PRESENT GPIO_STD_ADP_PRSNT
+#define GPIO_AC_PRESENT GPIO_BC_ACOK
+#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BAT_DET
+
+/* eSPI/Host communication */
+#define GPIO_ESPI_RESET_L GPIO_LPC_ESPI_RST_N
+#define GPIO_PCH_WAKE_L GPIO_SMC_WAKE_SCI_N_MECC
+#define GPIO_EC_INT_L GPIO_EC_PCH_MKBP_INT_ODL
+
+/* LED */
+#define GPIO_BAT_LED_RED_L GPIO_LED_1_L
+#define GPIO_PWR_LED_WHITE_L GPIO_LED_2_L
+
+/* FAN */
+#define GPIO_FAN_POWER_EN GPIO_THERM_SEN_MECC
+
+/* I2C ports & Configs */
+/* Charger */
+#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0
+
+/* Battery */
+#define I2C_PORT_BATTERY NPCX_I2C_PORT7_0
+
+/* Board ID */
+#define I2C_PORT_PCA9555_BOARD_ID_GPIO NPCX_I2C_PORT7_0
+
+/* Port 80 */
+#define I2C_PORT_PORT80 NPCX_I2C_PORT7_0
+
+/* USB-C I2C */
+#define I2C_PORT_TYPEC_0 NPCX_I2C_PORT0_0
+/*
+ * Note: I2C for Type-C Port-1 is swapped with Type-C Port-2
+ *       on the RVP to reduce BOM stuffing options.
+ */
+#define I2C_PORT_TYPEC_1 NPCX_I2C_PORT2_0
+#if defined(HAS_TASK_PD_C2)
+#define I2C_PORT_TYPEC_2 NPCX_I2C_PORT1_0
+#endif
+#if defined(HAS_TASK_PD_C3)
+#define I2C_PORT_TYPEC_3 NPCX_I2C_PORT3_0
+#endif
+
+#ifndef __ASSEMBLER__
+
+enum adlrvp_i2c_channel {
+	I2C_CHAN_BATT_CHG,
+	I2C_CHAN_TYPEC_0,
+	I2C_CHAN_TYPEC_1,
+#if defined(HAS_TASK_PD_C2)
+	I2C_CHAN_TYPEC_2,
+#endif
+#if defined(HAS_TASK_PD_C3)
+	I2C_CHAN_TYPEC_3,
+#endif
+	I2C_CHAN_COUNT,
+};
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/adlrvpp_npcx/build.mk b/board/adlrvpp_npcx/build.mk
new file mode 100644
index 0000000000..db43110a34
--- /dev/null
+++ b/board/adlrvpp_npcx/build.mk
@@ -0,0 +1,14 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Intel ADL-P-RVP-NPCX board-specific configuration
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx9
+CHIP_VARIANT:=npcx9m3f
+BASEBOARD:=intelrvp
+
+board-y=board.o
diff --git a/board/adlrvpp_npcx/ec.tasklist b/board/adlrvpp_npcx/ec.tasklist
new file mode 100644
index 0000000000..df3dc2c67d
--- /dev/null
+++ b/board/adlrvpp_npcx/ec.tasklist
@@ -0,0 +1,29 @@
+/*
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Intel ADL-P-RVP-NPCX board-specific configuration.
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C2, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C3, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C2, pd_interrupt_handler_task, 2, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C3, pd_interrupt_handler_task, 3, ULTRA_TASK_STACK_SIZE)
diff --git a/board/adlrvpp_npcx/gpio.inc b/board/adlrvpp_npcx/gpio.inc
new file mode 100644
index 0000000000..ebc04045bf
--- /dev/null
+++ b/board/adlrvpp_npcx/gpio.inc
@@ -0,0 +1,176 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel ADL-P-RVP-NPCX board-specific configuration */
+
+#include "baseboard/intelrvp/adlrvp_ioex_gpio.inc"
+
+/* Power sequencing interrupts */
+GPIO_INT(ALL_SYS_PWRGD,		PIN(7, 0), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(RSMRST_PWRGD,		PIN(3, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PCH_SLP_S0_N,		PIN(A, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCPDSW_3P3,		PIN(4, 5), GPIO_INT_BOTH, power_signal_interrupt)
+/* TODO: GPIO_INT(VCCST_PWRGD_MECC,	PIN(7, 1), GPIO_INT_BOTH, power_signal_interrupt) */
+GPIO_INT(PM_SLP_SUS_EC_N, 	PIN(8, 6), GPIO_INT_BOTH, power_signal_interrupt)
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+GPIO_INT(PM_SLP_S3_N,		PIN(B, 0), GPIO_INT_BOTH, power_signal_interrupt)
+#else
+GPIO(PM_SLP_S3_N,		PIN(B, 0), GPIO_INPUT)
+#endif
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
+GPIO_INT(PM_SLP_S4_N,		PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
+#else
+GPIO(PM_SLP_S4_N,		PIN(A, 5), GPIO_INPUT)
+#endif
+
+/* Button interrupts */
+GPIO_INT(VOLUME_UP,		PIN(6, 1), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(VOL_DN_EC,		PIN(0, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(SMC_LID,		PIN(0, 1), GPIO_INT_BOTH | GPIO_PULL_UP, lid_interrupt)
+GPIO_INT(MECH_PWR_BTN_ODL,	PIN(0, 0), GPIO_INT_BOTH, power_button_interrupt)
+
+/* DC Jack presence coming from +VADP_OUT */
+GPIO_INT(STD_ADP_PRSNT, 	PIN(0, 2), GPIO_INT_BOTH, board_dc_jack_interrupt) /* DC_JACK_PRESENT */
+
+GPIO_INT(BC_ACOK,		PIN(C, 6), GPIO_INT_BOTH, extpower_interrupt) /* AC Present */
+
+/* USB-C interrupts */
+GPIO_INT(USBC_TCPC_ALRT_P0,	PIN(4, 0), GPIO_INT_BOTH, tcpc_alert_event)
+GPIO_INT(USBC_TCPC_ALRT_P1,	PIN(6, 2), GPIO_INT_BOTH, tcpc_alert_event)
+#if defined(HAS_TASK_PD_C2)
+GPIO_INT(USBC_TCPC_ALRT_P2,	PIN(6, 3), GPIO_INT_BOTH, tcpc_alert_event)
+GPIO_INT(USBC_TCPC_ALRT_P3,	PIN(6, 7), GPIO_INT_BOTH, tcpc_alert_event)
+#else
+GPIO(USBC_TCPC_ALRT_P2,		PIN(6, 3), GPIO_INPUT)
+GPIO(USBC_TCPC_ALRT_P3,		PIN(6, 7), GPIO_INPUT)
+#endif
+
+GPIO_INT(USBC_TCPC_PPC_ALRT_P0, PIN(F, 0), GPIO_INT_BOTH, ppc_interrupt)
+GPIO_INT(USBC_TCPC_PPC_ALRT_P1, PIN(F, 1), GPIO_INT_BOTH, ppc_interrupt)
+#if defined(HAS_TASK_PD_C2)
+GPIO_INT(USBC_TCPC_PPC_ALRT_P2, PIN(F, 2), GPIO_INT_BOTH, ppc_interrupt)
+GPIO_INT(USBC_TCPC_PPC_ALRT_P3, PIN(F, 3), GPIO_INT_BOTH, ppc_interrupt)
+#else
+GPIO(USBC_TCPC_PPC_ALRT_P2,	PIN(F, 2), GPIO_INPUT)
+GPIO(USBC_TCPC_PPC_ALRT_P3,	PIN(F, 3), GPIO_INPUT)
+#endif
+
+/* Host communication GPIOs */
+GPIO(SMC_WAKE_SCI_N_MECC,	PIN(A, 4), GPIO_ODR_HIGH)
+GPIO(EC_PCH_MKBP_INT_ODL,	PIN(F, 5), GPIO_ODR_HIGH)
+#ifndef CONFIG_HOST_INTERFACE_ESPI
+GPIO(LPC_ESPI_RST_N,		PIN(5, 4), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(PLT_RST_L, 		PIN(A, 2), GPIO_INPUT | GPIO_SEL_1P8V) /* PCH_PLTRST_L */
+#endif
+
+/* Sensor Interrupts */
+GPIO_INT(SLATE_MODE_INDICATION,	PIN(E, 5), GPIO_INT_BOTH | GPIO_SEL_1P8V, gmr_tablet_switch_isr)
+GPIO(PROCHOT_EC_N,		PIN(A, 7), GPIO_INPUT)
+
+/* Power sequencing GPIOs */
+GPIO(SYS_RST_ODL,		PIN(C, 5), GPIO_ODR_HIGH)
+/* GPIOD3 (Rework: CPU_TACHO_FAN is swapped with PM_RSMRST_N) */
+GPIO(PM_RSMRST_N,		PIN(D, 3), GPIO_OUT_LOW)
+GPIO(PM_PWRBTN_N,		PIN(9, 7), GPIO_ODR_HIGH)
+GPIO(EC_SPI_OE_MECC,		PIN(6, 0), GPIO_OUT_LOW)
+GPIO(EC_DS3,			PIN(C, 4), GPIO_OUT_LOW)
+UNIMPLEMENTED(EN_PP5000)
+
+/* PCH_PWROK_EC is an input, as it's driven by the Silego chip on RVP */
+GPIO(PCH_PWROK_EC,	PIN(A, 0), GPIO_INPUT)
+GPIO(SYS_PWROK,		PIN(9, 3), GPIO_OUT_LOW)
+GPIO(EC_DSW_PWROK,	PIN(9, 5), GPIO_OUT_LOW)
+
+/* H1 pins */
+GPIO_INT(EC_FLASH_WP_ODL,	PIN(9, 4), GPIO_INT_BOTH, switch_interrupt)
+GPIO(EC_H1_PACKET_MODE,		PIN(E, 2), GPIO_OUT_LOW)
+GPIO(EC_ENTERING_RW,		PIN(D, 4), GPIO_OUT_LOW)
+
+/* Case Closed Debug Mode */
+GPIO_INT(CCD_MODE_ODL,		PIN(F, 4), GPIO_INT_BOTH, board_connect_c0_sbu)
+
+/* Battery present */
+GPIO(BAT_DET,		PIN(7, 6), GPIO_INPUT)
+
+/* EDP */
+GPIO(EDP_BKLT_EN_MECC,	PIN(E, 1), GPIO_OUT_HIGH)
+
+/* LED */
+GPIO(LED_1_L,		PIN(B, 6), GPIO_OUT_HIGH)
+GPIO(LED_2_L,		PIN(B, 7), GPIO_OUT_HIGH)
+
+/* FAN control pins */
+GPIO(THERM_SEN_MECC,	PIN(C, 0), GPIO_OUT_LOW)
+
+/*
+ * I2C pins should be configure as inputs until I2C module is
+ * initialized. This will avoid driving the lines unintentionally.
+ */
+GPIO(SMB_BS_CLK,		PIN(B, 3), GPIO_INPUT)	/* I2C7_SCL0 */
+GPIO(SMB_BS_DATA,		PIN(B, 2), GPIO_INPUT)	/* I2C7_SDA0 */
+GPIO(USBC_TCPC_I2C_CLK_P0,	PIN(B, 5), GPIO_INPUT)	/* I2C0_SCL0 */
+GPIO(USBC_TCPC_I2C_DATA_P0,	PIN(B, 4), GPIO_INPUT)	/* I2C0_SDA0 */
+GPIO(USBC_TCPC_I2C_CLK_P2,	PIN(9, 2), GPIO_INPUT)	/* I2C2_SCL0 */
+GPIO(USBC_TCPC_I2C_DATA_P2,	PIN(9, 1), GPIO_INPUT)	/* I2C2_SDA0 */
+GPIO(USBC_TCPC_I2C_CLK_P1,	PIN(9, 0), GPIO_INPUT)	/* I2C1_SCL0 */
+GPIO(USBC_TCPC_I2C_DATA_P1,	PIN(8, 7), GPIO_INPUT)	/* I2C1_SCL0 */
+GPIO(USBC_TCPC_I2C_CLK_P3,	PIN(D, 1), GPIO_INPUT)	/* I2C3_SCL0 */
+GPIO(USBC_TCPC_I2C_DATA_P3,	PIN(D, 0), GPIO_INPUT)	/* I2C3_SCL0 */
+
+/* Unused pins */
+GPIO(SML1_CLK_MECC,		PIN(3, 3), GPIO_INPUT)
+GPIO(SML1_DATA_MECC,		PIN(3, 6), GPIO_INPUT)
+GPIO(SMB_PCH_CLK,		PIN(C, 2), GPIO_INPUT)
+GPIO(SMB_PCH_DATA,		PIN(C, 1), GPIO_INPUT)
+GPIO(I3C_0_SCL,			PIN(E, 4), GPIO_INPUT)
+GPIO(I3C_0_SDA,			PIN(E, 3), GPIO_INPUT)
+GPIO(CPU_CAT_ERR_MECC,		PIN(3, 4), GPIO_INPUT)
+GPIO(TP29,			PIN(5, 0), GPIO_INPUT)
+GPIO(TP28,			PIN(5, 6), GPIO_INPUT)
+GPIO(ESPI_ALERT0_N,		PIN(5, 7), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(BATT_DISABLE_EC,		PIN(6, 6), GPIO_INPUT)
+GPIO(TP33,			PIN(7, 2), GPIO_INPUT)
+GPIO(TP26,			PIN(7, 3), GPIO_INPUT)
+GPIO(SLP_S0_CS_N,		PIN(7, 4), GPIO_INPUT)
+GPIO(EC_PECI,			PIN(8, 1), GPIO_INPUT)
+GPIO(CPU_C10_GATE_MECC,		PIN(9, 6), GPIO_INPUT)
+GPIO(SMB_PCH_ALRT,		PIN(A, 3), GPIO_INPUT)
+GPIO(SMC_SDOWN_MECC,		PIN(B, 1), GPIO_INPUT)
+GPIO(STD_ADPT_CNTRL_GPIO,	PIN(C, 3), GPIO_INPUT)
+GPIO(SML1_ALERT,		PIN(C, 7), GPIO_INPUT)
+GPIO(SMC_ONOFF_N,		PIN(D, 2), GPIO_INPUT) /* Power button interrupt without H1 */
+GPIO(SUSWARN,			PIN(D, 5), GPIO_INPUT)
+GPIO(TP_GPIOD6_EC,		PIN(D, 6), GPIO_INPUT)
+GPIO(TP_GPIOD7_EC,		PIN(D, 7), GPIO_INPUT)
+GPIO(ME_G3_TO_M3_EC,		PIN(E, 0), GPIO_INPUT)
+
+/* Alternate pins for I2C */
+ALTERNATE(PIN_MASK(8, BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)
+ALTERNATE(PIN_MASK(9, BIT(0) | BIT(1) | BIT(2)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)
+ALTERNATE(PIN_MASK(B, BIT(2) | BIT(3) | BIT(4) | BIT(5)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)
+ALTERNATE(PIN_MASK(D, BIT(0) | BIT(1)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)
+
+/* Alternate pins for UART */
+ALTERNATE(PIN_MASK(6, BIT(4) | BIT(5)), GPIO_ALT_FUNC_DEFAULT, MODULE_UART, GPIO_PULL_UP)
+
+/* Alternate pins for ADC */
+/* VR_TMP/V_1P05 - GPIO44, SKIN_THERM_IN_EC - GPIO43, AMBIENT_TEMP - GPIO42, DDR_TEMP/EC_5V - GPIO41 */
+ALTERNATE(PIN_MASK(4, BIT(1) | BIT(2) | BIT(3) | BIT(4)), GPIO_ALT_FUNC_DEFAULT, MODULE_ADC, GPIO_FLAG_NONE)
+
+/* Alternate pins for FAN */
+ALTERNATE(PIN_MASK(8, BIT(0)), GPIO_ALT_FUNC_DEFAULT, MODULE_PWM, GPIO_FLAG_NONE)	/* CPU_FAN_MECC GPIO80/PWM3_LED3 */
+/* GPIOA6 (Rework: CPU_TACHO_FAN is swapped with PM_RSMRST_N) */
+ALTERNATE(PIN_MASK(A, BIT(6)), GPIO_ALT_FUNC_DEFAULT, MODULE_PWM, GPIO_FLAG_NONE)
+
+/* Keyboard pins */
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_00-01 */
+GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW)
+ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_02-07 */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_00-01 */
+ALTERNATE(PIN_MASK(1, 0xFF), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_02-09 */
+ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_10-13 */
+ALTERNATE(PIN_MASK(8, 0x0C), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_14-15 */
diff --git a/board/adlrvpp_npcx/vif_override.xml b/board/adlrvpp_npcx/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/adlrvpp_npcx/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/agah/battery.c b/board/agah/battery.c
new file mode 100644
index 0000000000..92e2ad4b07
--- /dev/null
+++ b/board/agah/battery.c
@@ -0,0 +1,107 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "cbi.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "gpio.h"
+/*
+ * Battery info for all Agah battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	/* DYNAPACK COSMAX Battery Information */
+	[BATTERY_DYNAPACK_COSMX] = {
+		/* RAJ240045 Fuel Gauge */
+		.fuel_gauge = {
+			.manuf_name = "333-2C-4C-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 0,
+				.reg_addr = 0x43,
+				.reg_mask = 0x0003,
+				.disconnect_val = 0x0,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 17600,
+			.voltage_normal		= 15400, /* mV */
+			.voltage_min		= 12000, /* mV */
+			.precharge_current	= 256,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 45,
+			.charging_min_c		= 0,
+			.charging_max_c		= 50,
+			.discharging_min_c	= -10,
+			.discharging_max_c	= 60,
+		},
+	},
+	/* DYNAPACK HIGHPOWER Battery Information */
+	[BATTERY_DYNAPACK_HIGHPOWER] = {
+		/* RAJ240045 Fuel Gauge */
+		.fuel_gauge = {
+			.manuf_name = "333-2D-4C-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 0,
+				.reg_addr = 0x43,
+				.reg_mask = 0x0003,
+				.disconnect_val = 0x0,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 17600,
+			.voltage_normal		= 15400, /* mV */
+			.voltage_min		= 12000, /* mV */
+			.precharge_current	= 256,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 45,
+			.charging_min_c		= 0,
+			.charging_max_c		= 50,
+			.discharging_min_c	= -10,
+			.discharging_max_c	= 60,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_DYNAPACK_COSMX;
+
+enum battery_present battery_hw_present(void)
+{
+	enum gpio_signal batt_pres;
+
+	batt_pres = GPIO_EC_BATT_PRES_ODL;
+
+	/* The GPIO is low when the battery is physically present */
+	return gpio_get_level(batt_pres) ? BP_NO : BP_YES;
+}
diff --git a/board/agah/board.c b/board/agah/board.c
new file mode 100644
index 0000000000..7884ac1e97
--- /dev/null
+++ b/board/agah/board.c
@@ -0,0 +1,120 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "button.h"
+#include "charge_ramp.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/nvidia_gpu.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "registers.h"
+#include "switch.h"
+#include "system.h"
+#include "throttle_ap.h"
+#include "usbc_config.h"
+#include "util.h"
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* Console output macros */
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+
+static int block_sequence;
+
+struct d_notify_policy d_notify_policies[] = {
+	[D_NOTIFY_1] = AC_ATLEAST_W(100),
+	[D_NOTIFY_2] = AC_ATLEAST_W(65),
+	[D_NOTIFY_3] = AC_DC,
+	[D_NOTIFY_4] = DC_ATMOST_SOC(20),
+	[D_NOTIFY_5] = DC_ATMOST_SOC(5),
+};
+BUILD_ASSERT(ARRAY_SIZE(d_notify_policies) == D_NOTIFY_COUNT);
+
+__override void board_cbi_init(void)
+{
+}
+
+/* Called on AP S3 -> S0 transition */
+static void board_chipset_resume(void)
+{
+	/* Allow keyboard backlight to be enabled */
+	gpio_set_level(GPIO_EC_KB_BL_EN, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S0 -> S3 transition */
+static void board_chipset_suspend(void)
+{
+	/* Turn off the keyboard backlight if it's on. */
+	gpio_set_level(GPIO_EC_KB_BL_EN, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
+
+static void board_init(void)
+{
+	if ((system_get_reset_flags() & EC_RESET_FLAG_AP_OFF) ||
+	    (keyboard_scan_get_boot_keys() & BOOT_KEY_DOWN_ARROW)) {
+		CPRINTS("PG_PP3300_S5_OD block is enabled");
+		block_sequence = 1;
+	}
+	gpio_enable_interrupt(GPIO_PG_PP3300_S5_OD);
+	gpio_enable_interrupt(GPIO_BJ_ADP_PRESENT_ODL);
+
+	nvidia_gpu_init_policy(d_notify_policies);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+/**
+ * Deferred function to handle GPIO PG_PP3300_S5_OD change
+ */
+static void bypass_pp3300_s5_deferred(void)
+{
+	if (block_sequence) {
+		CPRINTS("PG_PP3300_S5_OD is blocked.");
+		return;
+	}
+
+	gpio_set_level(GPIO_PG_PP3300_S5_EC_SEQ_OD,
+		       gpio_get_level(GPIO_PG_PP3300_S5_OD));
+}
+DECLARE_DEFERRED(bypass_pp3300_s5_deferred);
+
+void board_power_interrupt(enum gpio_signal signal)
+{
+	/* Trigger deferred notification of gpio PG_PP3300_S5_OD change */
+	hook_call_deferred(&bypass_pp3300_s5_deferred_data, 0);
+}
+
+static int cc_blockseq(int argc, const char *argv[])
+{
+	if (argc > 1) {
+		if (!parse_bool(argv[1], &block_sequence)) {
+			ccprintf("Invalid argument: %s\n", argv[1]);
+			return EC_ERROR_INVAL;
+		}
+	}
+
+	ccprintf("PG_PP3300_S5_OD block is %s\n",
+		 block_sequence ? "enabled" : "disabled");
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(blockseq, cc_blockseq, "[on/off]", NULL);
+
+void gpu_overt_interrupt(enum gpio_signal signal)
+{
+	nvidia_gpu_over_temp(gpio_get_level(signal));
+}
diff --git a/board/agah/board.h b/board/agah/board.h
new file mode 100644
index 0000000000..802b0f232e
--- /dev/null
+++ b/board/agah/board.h
@@ -0,0 +1,225 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Agah board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "compile_time_macros.h"
+
+/* Baseboard features */
+#include "baseboard.h"
+
+/*
+ * Nvidia GPU
+ */
+#define CONFIG_GPU_NVIDIA
+
+/*
+ * This will happen automatically on NPCX9 ES2 and later. Do not remove
+ * until we can confirm all earlier chips are out of service.
+ */
+#define CONFIG_HIBERNATE_PSL_VCC1_RST_WAKEUP
+
+/*
+ * Agah blocks PG_PP3300_S5_OD instead to control AP power-on.
+ */
+#undef CONFIG_CHIPSET_X86_RSMRST_AFTER_S5
+
+/* Sensors */
+#undef CONFIG_TABLET_MODE
+#undef CONFIG_TABLET_MODE_SWITCH
+#undef CONFIG_GMR_TABLET_MODE
+
+/* Buttons */
+#undef CONFIG_VOLUME_BUTTONS
+
+/* USB Type A Features */
+#define USB_PORT_COUNT 1
+#define CONFIG_USB_PORT_POWER_DUMB
+
+/* USB Type C and USB PD defines */
+#define CONFIG_USB_PD_TCPM_RT1715
+#undef CONFIG_USB_PD_TCPM_NCT38XX
+#define CONFIG_USBC_RETIMER_PS8818
+
+/* I2C speed console command */
+#define CONFIG_CMD_I2C_SPEED
+
+/* I2C control host command */
+#define CONFIG_HOSTCMD_I2C_CONTROL
+
+#define CONFIG_USBC_PPC_SYV682X
+#define CONFIG_USB_PD_FRS_PPC
+#undef CONFIG_SYV682X_HV_ILIM
+#define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_5_50
+
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
+
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 100000
+#define PD_MAX_CURRENT_MA 5000
+#define PD_MAX_VOLTAGE_MV 20000
+
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
+#define CONFIG_EXTPOWER_DEBOUNCE_MS 500
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
+
+/*
+ * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
+ * signal.
+ */
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PCH_DSW_PWROK GPIO_PCH_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
+
+/* System has back-lit keyboard */
+#define CONFIG_PWM_KBLIGHT
+
+/* I2C Bus Configuration */
+
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+
+#define I2C_PORT_USB_C0_TCPC NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C2_TCPC NPCX_I2C_PORT2_0
+
+#define I2C_PORT_USB_C0_PPC NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C2_PPC NPCX_I2C_PORT2_0
+
+#define I2C_PORT_USB_C0_BC12 NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C2_BC12 NPCX_I2C_PORT2_0
+
+#define I2C_PORT_USBA1_RT NPCX_I2C_PORT6_1
+
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+
+/* Thermal features */
+#define CONFIG_THERMISTOR
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_TEMP_SENSOR_POWER
+#define CONFIG_TEMP_SENSOR_FIRST_READ_DELAY_MS 500
+#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
+
+#define CONFIG_FANS FAN_CH_COUNT
+
+/* Charger defines */
+#define CONFIG_CHARGER_BYPASS_MODE
+#define CONFIG_CHARGER_ISL9241
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+/* Round down 7700 max current to multiple of 128mA for ISL9241 AC prochot. */
+#define AGAH_AC_PROCHOT_CURRENT_MA 7680
+
+/* Barrel jack adapter settings */
+#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT
+#define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1
+/* This is the next available port # after USB-C ports. */
+#define DEDICATED_CHARGE_PORT 2
+
+/*
+ * Older boards have a different ADC assignment.
+ */
+
+#define CONFIG_ADC_CHANNELS_RUNTIME_CONFIG
+
+/*
+ * Give power signals higher priority to reduce the chance of damaging the PCH
+ * on urgent power loss.
+ */
+#define NPCX_MIWU0_GROUP_F 1 /* SEQ_EC_DSW_PWROK */
+#define NPCX_MIWU0_GROUP_H 2 /* RSMRST */
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h" /* needed by registers.h */
+#include "registers.h"
+#include "usbc_config.h"
+
+enum adc_channel {
+	ADC_TEMP_SENSOR_1_DDR_SOC,
+	ADC_TEMP_SENSOR_2_GPU,
+	ADC_TEMP_SENSOR_3_CHARGER,
+	ADC_CHARGER_IADP,
+	ADC_ADP_TYP,
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1_DDR_SOC,
+	TEMP_SENSOR_2_GPU,
+	TEMP_SENSOR_3_CHARGER,
+	TEMP_SENSOR_COUNT
+};
+
+enum battery_type {
+	BATTERY_DYNAPACK_COSMX,
+	BATTERY_DYNAPACK_HIGHPOWER,
+	BATTERY_TYPE_COUNT
+};
+
+enum pwm_channel {
+	PWM_CH_KBLIGHT = 0, /* PWM3 */
+	PWM_CH_FAN, /* PWM5 */
+	PWM_CH_FAN2, /* PWM4 */
+	PWM_CH_COUNT
+};
+
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_1, FAN_CH_COUNT };
+
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_1, MFT_CH_COUNT };
+
+enum charge_port {
+	CHARGE_PORT_TYPEC0,
+	CHARGE_PORT_TYPEC1,
+	CHARGE_PORT_BARRELJACK,
+};
+
+/**
+ * Interrupt handler for PG_PP3300_S5_OD changes.
+ *
+ * @param signal	Signal which triggered the interrupt.
+ */
+void board_power_interrupt(enum gpio_signal signal);
+
+/* IRQ for BJ plug/unplug. */
+void bj_present_interrupt(enum gpio_signal signal);
+
+/* IRQ for over temperature. */
+void gpu_overt_interrupt(enum gpio_signal signal);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/agah/build.mk b/board/agah/build.mk
new file mode 100644
index 0000000000..d2f2db68df
--- /dev/null
+++ b/board/agah/build.mk
@@ -0,0 +1,25 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Agah board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx9
+CHIP_VARIANT:=npcx9m3f
+BASEBOARD:=brya
+
+board-y=
+board-y+=battery.o
+board-y+=board.o
+board-y+=charger_isl9241.o
+board-y+=fans.o
+board-y+=fw_config.o
+board-y+=i2c.o
+board-y+=keyboard.o
+board-y+=led.o
+board-y+=pwm.o
+board-y+=sensors.o
+board-y+=usbc_config.o
diff --git a/board/agah/charger_isl9241.c b/board/agah/charger_isl9241.c
new file mode 100644
index 0000000000..892c857ad6
--- /dev/null
+++ b/board/agah/charger_isl9241.c
@@ -0,0 +1,275 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ *
+ * We need to deal with plug / unplug of AC chargers:
+ *
+ *  +---------+    +USB     +---------+
+ *  | BATTERY |------------>| BATTERY |
+ *  |         |<------------|    +USB |
+ *  +---------+    -USB     +---------+
+ *      | ^                     | ^
+ *  +BJ | | -BJ             +BJ | | -BJ
+ *      v |                     v |
+ *  +---------+    +USB     +---------+
+ *  | BATTERY |------------>| BATTERY |
+ *  |     +BJ |<------------| +BJ+USB |
+ *  +---------+    -USB     +---------+
+ *
+ * Depending on available battery charge, power rating of the new charger, and
+ * the system power state, transition/throttling may or may not occur but
+ * switching chargers is handled as follows:
+ *
+ * 1. Detects a new charger or removal of an existing charger.
+ * 2. charge_manager_update_charge is called with new charger's info.
+ * 3. board_set_active_charge_port is called.
+ *    3.1 It triggers hard & soft throttling for AP & GPU.
+ *    3.2 It disable active port then enables the new port.
+ * 4. HOOK_POWER_SUPPLY_CHANGE is called. We disables hard throttling.
+ * 5. charger task wakes up on HOOK_POWER_SUPPLY_CHANGE, enables (or disables)
+ *    bypass mode.
+ */
+
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/charger/isl9241.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "stdbool.h"
+#include "throttle_ap.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+
+/* Charger Chip Configuration */
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = ISL9241_ADDR_FLAGS,
+		.drv = &isl9241_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CHARGER_NUM);
+
+static int board_enable_bj_port(bool enable)
+{
+	if (enable) {
+		if (gpio_get_level(GPIO_BJ_ADP_PRESENT_ODL))
+			return EC_ERROR_INVAL;
+		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 0);
+	} else {
+		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 1);
+	}
+
+	CPRINTS("BJ power is %sabled", enable ? "en" : "dis");
+
+	return EC_SUCCESS;
+}
+
+static void board_throttle_ap_gpu(void)
+{
+	throttle_ap(THROTTLE_ON, THROTTLE_HARD, THROTTLE_SRC_AC);
+	throttle_gpu(THROTTLE_ON, THROTTLE_HARD, THROTTLE_SRC_AC);
+}
+
+/* Disable all VBUS sink ports except <port>. <port> = -1 disables all ports. */
+static int board_disable_other_vbus_sink(int except_port)
+{
+	int i, r, rv = EC_SUCCESS;
+
+	for (i = 0; i < ppc_cnt; i++) {
+		if (i == except_port)
+			continue;
+		/*
+		 * Do not return early if one fails otherwise we can get into a
+		 * boot loop assertion failure.
+		 */
+		r = ppc_vbus_sink_enable(i, 0);
+		if (r)
+			CPRINTS("Failed to disable sink path C%d (%d)", i, r);
+		rv |= r;
+	}
+
+	return rv;
+}
+
+/* Minimum battery SoC required for switching source port. */
+#define MIN_BATT_FOR_SWITCHING_SOURCE_PORT 1
+
+/*
+ * TODO: Recover from incomplete execution:
+ */
+int board_set_active_charge_port(int port)
+{
+	enum charge_supplier active_supplier = charge_manager_get_supplier();
+	int active_port = charge_manager_get_active_charge_port();
+
+	CPRINTS("Switching charger from P%d (supplier=%d) to P%d", active_port,
+		active_supplier, port);
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTS("Disabling all charger ports");
+
+		board_enable_bj_port(false);
+		board_disable_other_vbus_sink(-1);
+
+		return EC_SUCCESS;
+	}
+
+	/* Return on invalid or no-op call. */
+	if (port < 0 || CHARGE_PORT_COUNT <= port) {
+		return EC_ERROR_INVAL;
+	} else if (port == active_port) {
+		return EC_SUCCESS;
+	} else if (board_vbus_source_enabled(port)) {
+		/* Don't charge from a USBC source port */
+		CPRINTS("Don't enable P%d. It's sourcing.", port);
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * If we're in S0, throttle AP and GPU. They'll be unthrottled when
+	 * a port/supply switch completes (via HOOK_POWER_SUPPLY_CHANGE).
+	 *
+	 * If we're running currently on a battery (active_supplier == NONE), we
+	 * don't need to throttle because we're not disabling any port.
+	 */
+	if (chipset_in_state(CHIPSET_STATE_ON) &&
+	    active_supplier != CHARGE_SUPPLIER_NONE)
+		board_throttle_ap_gpu();
+
+	/*
+	 * We're here for the two cases:
+	 * 1. A new charger was connected.
+	 * 2. One charger was disconnected and we're switching to another.
+	 */
+
+	/*
+	 * We need to check the battery if we're switching a source port. If
+	 * we're just starting up or no AC was previously plugged, we shouldn't
+	 * check the battery. Both cases can be caught by supplier == NONE.
+	 */
+	if (active_supplier != CHARGE_SUPPLIER_NONE) {
+		if (charge_get_percent() < MIN_BATT_FOR_SWITCHING_SOURCE_PORT)
+			return EC_ERROR_NOT_POWERED;
+	}
+
+	/* Turn off other ports' sink paths before enabling requested port. */
+	if (is_pd_port(port)) {
+		/*
+		 * BJ port is enabled on start-up. So, we need to turn it off
+		 * even if we were not previously on BJ.
+		 */
+		board_enable_bj_port(false);
+		if (board_disable_other_vbus_sink(port))
+			return EC_ERROR_UNCHANGED;
+
+		/* Enable requested USBC charge port. */
+		if (ppc_vbus_sink_enable(port, 1)) {
+			CPRINTS("Failed to enable sink path for C%d", port);
+			return EC_ERROR_UNKNOWN;
+		}
+	} else if (port == CHARGE_PORT_BARRELJACK) {
+		/*
+		 * We can't proceed unless both ports are successfully
+		 * disconnected as sources.
+		 */
+		if (board_disable_other_vbus_sink(-1))
+			return EC_ERROR_UNKNOWN;
+		board_enable_bj_port(true);
+	}
+
+	CPRINTS("New charger P%d", port);
+
+	return EC_SUCCESS;
+}
+
+static const struct charge_port_info bj_power = {
+	/* 150W (also default) */
+	.voltage = 19500,
+	.current = 7700,
+};
+
+/* Debounce time for BJ plug/unplug */
+#define BJ_DEBOUNCE_MS CONFIG_EXTPOWER_DEBOUNCE_MS
+
+int board_should_charger_bypass(void)
+{
+	return charge_manager_get_active_charge_port() == DEDICATED_CHARGE_PORT;
+}
+
+static void bj_connect(void)
+{
+	static int8_t bj_connected = -1;
+	int connected = !gpio_get_level(GPIO_BJ_ADP_PRESENT_ODL);
+
+	/* Debounce */
+	if (connected == bj_connected)
+		return;
+
+	bj_connected = connected;
+	CPRINTS("BJ %sconnected", connected ? "" : "dis");
+
+	charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED,
+				     DEDICATED_CHARGE_PORT,
+				     connected ? &bj_power : NULL);
+}
+DECLARE_DEFERRED(bj_connect);
+
+/* This handler shouldn't be needed if ACOK from isl9241 is working. */
+void bj_present_interrupt(enum gpio_signal signal)
+{
+	hook_call_deferred(&bj_connect_data, BJ_DEBOUNCE_MS * MSEC);
+}
+
+void ac_change(void)
+{
+	/*
+	 * Serialize. We don't handle USB-C here because we'll get a
+	 * notification from TCPC.
+	 */
+	hook_call_deferred(&bj_connect_data, 0);
+}
+DECLARE_HOOK(HOOK_AC_CHANGE, ac_change, HOOK_PRIO_DEFAULT);
+
+static void power_supply_changed(void)
+{
+	/*
+	 * We've switched to a new charge port (or no port). Hardware throttles
+	 * can be removed now. Software throttles may stay enabled and change
+	 * as the situation changes.
+	 */
+	throttle_ap(THROTTLE_OFF, THROTTLE_HARD, THROTTLE_SRC_AC);
+	/*
+	 * Unthrottling GPU is done through a deferred call scheduled when it
+	 * was throttled.
+	 */
+}
+DECLARE_HOOK(HOOK_POWER_SUPPLY_CHANGE, power_supply_changed, HOOK_PRIO_DEFAULT);
+
+static void bj_state_init(void)
+{
+	/*
+	 * Initialize all charge suppliers to 0. The charge manager waits until
+	 * all ports have reported in before doing anything.
+	 */
+	for (int i = 0; i < CHARGE_PORT_COUNT; i++) {
+		for (int j = 0; j < CHARGE_SUPPLIER_COUNT; j++)
+			charge_manager_update_charge(j, i, NULL);
+	}
+
+	bj_connect();
+
+	isl9241_set_ac_prochot(CHARGER_SOLO, AGAH_AC_PROCHOT_CURRENT_MA);
+}
+DECLARE_HOOK(HOOK_INIT, bj_state_init, HOOK_PRIO_INIT_CHARGE_MANAGER + 1);
diff --git a/board/agah/ec.tasklist b/board/agah/ec.tasklist
new file mode 100644
index 0000000000..ebbfd239f9
--- /dev/null
+++ b/board/agah/ec.tasklist
@@ -0,0 +1,29 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ *
+ * USB_CHG_Px tasks must be contiguous (see USB_CHG_PORT_TO_TASK_ID(x)).
+ * PD_Cx tasks must be contiguous (see PD_PORT_TO_TASK_ID(x))
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, HOOKS_TASK_STACK_SIZE) \
+	TASK_ALWAYS(LED, led_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, BASEBOARD_CHARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, BASEBOARD_CHIPSET_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, CONSOLE_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, BASEBOARD_POWERBTN_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, BASEBOARD_PD_INT_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, BASEBOARD_PD_INT_TASK_STACK_SIZE)
diff --git a/board/agah/fans.c b/board/agah/fans.c
new file mode 100644
index 0000000000..be4d335cfe
--- /dev/null
+++ b/board/agah/fans.c
@@ -0,0 +1,66 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Physical fans. These are logically separate from pwm_channels. */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "fan.h"
+#include "fan_chip.h"
+#include "hooks.h"
+#include "pwm.h"
+
+/* MFT channels. These are logically separate from pwm_channels. */
+const struct mft_t mft_channels[] = {
+	[MFT_CH_0] = {
+		.module = NPCX_MFT_MODULE_1,
+		.clk_src = TCKC_LFCLK,
+		.pwm_id = PWM_CH_FAN,
+	},
+	[MFT_CH_1] = {
+		.module = NPCX_MFT_MODULE_2,
+		.clk_src = TCKC_LFCLK,
+		.pwm_id = PWM_CH_FAN2,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
+
+static const struct fan_conf fan_conf_0 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
+	.pgood_gpio = -1,
+	.enable_gpio = GPIO_EN_PP5000_FAN,
+};
+
+static const struct fan_conf fan_conf_1 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_1, /* Use MFT id to control fan */
+	.pgood_gpio = -1,
+	.enable_gpio = GPIO_EN_PP5000_FAN2,
+};
+
+static const struct fan_rpm fan_rpm_0 = {
+	.rpm_min = 2500,
+	.rpm_start = 2500,
+	.rpm_max = 4300,
+};
+
+static const struct fan_rpm fan_rpm_1 = {
+	.rpm_min = 2500,
+	.rpm_start = 2500,
+	.rpm_max = 4300,
+};
+
+const struct fan_t fans[FAN_CH_COUNT] = {
+	[FAN_CH_0] = {
+		.conf = &fan_conf_0,
+		.rpm = &fan_rpm_0,
+	},
+	[FAN_CH_1] = {
+		.conf = &fan_conf_1,
+		.rpm = &fan_rpm_1,
+	},
+};
diff --git a/board/agah/fw_config.c b/board/agah/fw_config.c
new file mode 100644
index 0000000000..a16cf10d5a
--- /dev/null
+++ b/board/agah/fw_config.c
@@ -0,0 +1,40 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "fw_config.h"
+
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
+
+static union agah_cbi_fw_config fw_config;
+BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
+
+/*
+ * FW_CONFIG defaults for agah if the CBI.FW_CONFIG data is not
+ * initialized.
+ */
+static const union agah_cbi_fw_config fw_config_defaults = {
+	.kb_bl = KEYBOARD_BACKLIGHT_ENABLED,
+};
+
+/****************************************************************************
+ * Agah FW_CONFIG access
+ */
+void board_init_fw_config(void)
+{
+	if (cbi_get_fw_config(&fw_config.raw_value)) {
+		CPRINTS("CBI: Read FW_CONFIG failed, using board defaults");
+		fw_config = fw_config_defaults;
+	}
+}
+
+union agah_cbi_fw_config get_fw_config(void)
+{
+	return fw_config;
+}
diff --git a/board/agah/fw_config.h b/board/agah/fw_config.h
new file mode 100644
index 0000000000..7efdae51ac
--- /dev/null
+++ b/board/agah/fw_config.h
@@ -0,0 +1,38 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __BOARD_AGAH_FW_CONFIG_H_
+#define __BOARD_AGAH_FW_CONFIG_H_
+
+#include <stdint.h>
+
+/****************************************************************************
+ * CBI FW_CONFIG layout for Agah board.
+ *
+ * Source of truth is the project/draco/agah/config.star configuration file.
+ */
+
+enum ec_cfg_keyboard_backlight_type {
+	KEYBOARD_BACKLIGHT_DISABLED = 0,
+	KEYBOARD_BACKLIGHT_ENABLED = 1
+};
+
+union agah_cbi_fw_config {
+	struct {
+		enum ec_cfg_keyboard_backlight_type kb_bl : 1;
+		uint32_t audio : 3;
+		uint32_t reserved_1 : 21;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Read the cached FW_CONFIG.  Guaranteed to have valid values.
+ *
+ * @return the FW_CONFIG for the board.
+ */
+union agah_cbi_fw_config get_fw_config(void);
+
+#endif /* __BOARD_AGAH_FW_CONFIG_H_ */
diff --git a/board/agah/gpio.inc b/board/agah/gpio.inc
new file mode 100644
index 0000000000..bfec03bfe1
--- /dev/null
+++ b/board/agah/gpio.inc
@@ -0,0 +1,135 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define MODULE_KB		MODULE_KEYBOARD_SCAN
+
+/* INTERRUPT GPIOs: */
+GPIO_INT(SEQ_EC_DSW_PWROK,               PIN(C, 7), GPIO_INT_BOTH, intel_x86_pwrok_signal_interrupt)
+GPIO_INT(SEQ_EC_RSMRST_ODL,              PIN(E, 2), GPIO_INT_BOTH, intel_x86_rsmrst_signal_interrupt)
+GPIO_INT(ACOK_OD,                        PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
+GPIO_INT(EC_PROCHOT_IN_L,                PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
+GPIO_INT(EC_WP_ODL,                      PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(GSC_EC_PWR_BTN_ODL,             PIN(0, 1), GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW, power_button_interrupt)
+GPIO_INT(LID_OPEN,                       PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
+GPIO_INT(SEQ_EC_ALL_SYS_PG,              PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,                       PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,                      PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SYS_SLP_S0IX_L,                 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(USB_C0_BC12_INT_ODL,            PIN(C, 6), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C0_TCPC_INT_ODL,            PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C0_PPC_INT_ODL,             PIN(6, 2), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(PG_PP3300_S5_OD,                PIN(B, 4), GPIO_INT_BOTH | GPIO_PULL_UP, board_power_interrupt)
+GPIO_INT(USB_C2_BC12_INT_ODL,            PIN(8, 3), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C2_TCPC_INT_ODL,            PIN(A, 7), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C2_PPC_INT_ODL,             PIN(7, 0), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(BJ_ADP_PRESENT_ODL,             PIN(5, 6), GPIO_INT_BOTH | GPIO_PULL_UP, bj_present_interrupt)
+GPIO_INT(GPU_OVERT_ODL,                  PIN(5, 0), GPIO_INT_BOTH, gpu_overt_interrupt)
+
+/* USED GPIOs: */
+GPIO(CCD_MODE_ODL,                   PIN(E, 5), GPIO_INPUT)
+GPIO(CPU_C10_GATE_L,                 PIN(6, 7), GPIO_INPUT)
+GPIO(EC_BATT_PRES_ODL,               PIN(A, 3), GPIO_INPUT)
+GPIO(EC_ENTERING_RW,                 PIN(0, 3), GPIO_OUT_LOW)
+GPIO(EC_EN_EDP_BL,                   PIN(D, 3), GPIO_OUT_HIGH)
+GPIO(EC_GSC_PACKET_MODE,             PIN(7, 5), GPIO_OUT_LOW)
+GPIO(EC_I2C_BAT_SCL,                 PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_BAT_SDA,                 PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SCL_R,              PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SDA_R,              PIN(B, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C2_SCL,              PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C2_SDA,              PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SCL,              PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SDA,              PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_USBA_RT_SCL,             PIN(E, 4), GPIO_INPUT)
+GPIO(EC_I2C_USBA_RT_SDA,             PIN(E, 3), GPIO_INPUT)
+GPIO(EC_KB_BL_EN,                    PIN(8, 6), GPIO_OUT_LOW)
+GPIO(EC_PCHHOT_ODL,                  PIN(7, 4), GPIO_INPUT)
+GPIO(EC_PCH_INT_ODL,                 PIN(B, 0), GPIO_ODR_HIGH)
+GPIO(EC_PCH_PWR_BTN_ODL,             PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(EC_PCH_RSMRST_L,                PIN(A, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_RTCRST,                  PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_SYS_PWROK,               PIN(3, 7), GPIO_OUT_LOW)
+GPIO(EC_PCH_WAKE_R_ODL,              PIN(C, 0), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_ODL,                 PIN(6, 3), GPIO_ODR_HIGH)
+GPIO(EN_PP5000_FAN,                  PIN(6, 1), GPIO_OUT_LOW)
+GPIO(EN_PP5000_FAN2,                 PIN(F, 5), GPIO_OUT_LOW)
+GPIO(EN_PP5000_USBA_R,               PIN(D, 7), GPIO_OUT_LOW)
+GPIO(EN_S5_RAILS,                    PIN(9, 6), GPIO_OUT_LOW)
+GPIO(IMVP9_VRRDY_OD,                 PIN(4, 3), GPIO_INPUT)
+GPIO(PCH_PWROK,                      PIN(7, 2), GPIO_OUT_LOW)
+GPIO(SYS_RST_ODL,                    PIN(C, 5), GPIO_ODR_HIGH)
+GPIO(EC_USB_PCH_C0_OC_ODL,           PIN(9, 4), GPIO_ODR_HIGH)
+GPIO(EC_USB_PCH_C2_OC_ODL,           PIN(9, 7), GPIO_ODR_HIGH)
+GPIO(USB_C0_FRS_EN,                  PIN(A, 0), GPIO_OUT_LOW)
+GPIO(VCCST_PWRGD_OD,                 PIN(A, 4), GPIO_ODR_LOW)
+GPIO(EN_USB_A_LOW_POWER,             PIN(9, 3), GPIO_OUT_LOW)
+GPIO(PG_PP3300_S5_EC_SEQ_OD,         PIN(B, 5), GPIO_OUT_LOW)
+GPIO(USB_C2_FRS_EN,                  PIN(D, 4), GPIO_OUT_LOW)
+GPIO(NVIDIA_GPU_ACOFF_ODL,           PIN(9, 5), GPIO_ODR_HIGH)
+GPIO(LED_2_L,                        PIN(C, 3), GPIO_OUT_LOW)
+GPIO(LED_1_L,                        PIN(C, 4), GPIO_OUT_LOW)
+
+/*
+ * Barrel-jack adapter enable switch. When starting up on a depleted battery,
+ * we'll be powered by either BJ or USB-C but not both. The EC will detect BJ
+ * or USBC and disable the other ports.
+ */
+GPIO(EN_PPVAR_BJ_ADP_L,              PIN(A, 2), GPIO_OUT_LOW)
+
+/*
+ * The NPCX keyboard driver does not use named GPIOs to access
+ * keyboard scan pins, so we do not list them in *gpio.inc. However, when
+ * KEYBOARD_COL2_INVERTED is defined, this name is required.
+ */
+GPIO(EC_KSO_02_INV,               PIN(1, 7), GPIO_OUT_LOW)
+
+/* UART alternate functions */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)              /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */
+
+/* I2C alternate functions */
+ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)               /* GPIO33/I2C5_SCL0/CTS_L, GPIO36/RTS_L/I2C5_SDA0 */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)               /* GPIO87/I2C1_SDA0 */
+ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)               /* GPIO92/I2C2_SCL0, GPIO91/I2C2_SDA0, GPIO90/I2C1_SCL0 */
+ALTERNATE(PIN_MASK(B, 0x0c), 0, MODULE_I2C, 0)               /* GPIOB3/I2C7_SCL0/DCD_L, GPIOB2/I2C7_SDA0/DSR_L */
+ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)               /* GPIOD1/I2C3_SCL0, GPIOD0/I2C3_SDA0 */
+ALTERNATE(PIN_MASK(E, 0x18), 0, MODULE_I2C, 0)               /* GPIOE4/I2C6_SCL1/I3C_SCL, GPIOE3/I2C6_SDA1/I3C_SDA */
+ALTERNATE(PIN_MASK(F, 0x0c), 0, MODULE_I2C, 0)               /* GPIOF3/I2C4_SCL1, GPIOF2/I2C4_SDA1 */
+
+/* PWM alternate functions */
+ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0)               /* GPIO40/TA1 */
+ALTERNATE(PIN_MASK(7, 0x08), 0, MODULE_PWM, 0)               /* GPIO73/TA2 */
+ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)               /* GPIO80/PWM3 */
+ALTERNATE(PIN_MASK(B, 0xC0), 0, MODULE_PWM, 0)               /* GPIOB7/PWM5, GPIOB6/PWM4 */
+
+/* ADC alternate functions */
+ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0)               /* GPIO34/PS2_DAT2/ADC6 */
+ALTERNATE(PIN_MASK(4, 0x36), 0, MODULE_ADC, 0)               /* GPIO42/ADC3/RI_L, GPIO45/ADC0, GPIO44/ADC1, GPIO41/ADC4 */
+
+/* KB alternate functions */
+ALTERNATE(PIN_MASK(0, 0xf0), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO10&P80_CLK/GPIO07, KSO11&P80_DAT/GPIO06, KSO12/GPIO05, KSO13/GPIO04 */
+ALTERNATE(PIN_MASK(1, 0x7f), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO06/GPO13/GP_SEL_L, KSO07/GPO12/JEN_L, KSO03/GPIO16/JTAG_TDO0_SWO, KSO04/GPIO15/XNOR, KSO05/GPIO14, KSO08/GPIO11/CR_SOUT1, KSO09/GPIO10/CR_SIN1 */
+ALTERNATE(PIN_MASK(2, 0xfc), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI2/GPIO27/TRACEDATA1, KSI3/GPIO26/TRACEDATA0, KSI4/GPIO25/TRACECLK/GP_SCLK, KSI5/GPIO24/GP_MISO, KSI6/GPIO23/S_SBUB, KSI7/GPIO22/S_SBUA */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO00/GPIO21/JTAG_TCK_SWCLK, KSO01/GPIO20/JTAG_TMS_SWIO */
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI0/GPIO31/TRACEDATA3/GP_MOSI, KSI1/GPIO30/TRACEDATA2/GP_CS_L */
+ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO14/GPIO82 */
+
+/* PMU alternate functions */
+ALTERNATE(PIN_MASK(0, 0x01), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN2_L&GPI00/GPIO00 */
+ALTERNATE(PIN_MASK(0, 0x02), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW) /* GPIO01/PSL_IN3_L&GPI01 */
+ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN1_L&GPID2/GPIOD2 */
+
+/* Unused Pins */
+UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
+UNUSED(PIN(3, 2))       /* GPO32/TRIS_L */
+UNUSED(PIN(3, 5))       /* GPO35/CR_SOUT4/TEST_L */
+UNUSED(PIN(0, 2))       /* GPIO02 */
+UNUSED(PIN(6, 6))       /* GPIO66 */
+UNUSED(PIN(5, 7))       /* GPIO57/SER_IRQ/ESPI_ALERT_L */
+UNUSED(PIN(8, 1))       /* GPIO81 */
+UNUSED(PIN(6, 0))       /* GPIO60 */
+UNUSED(PIN(C, 2))       /* GPIOC2 */
+UNUSED(PIN(E, 1))       /* GPIOE1 */
diff --git a/board/agah/i2c.c b/board/agah/i2c.c
new file mode 100644
index 0000000000..5bdf6936c1
--- /dev/null
+++ b/board/agah/i2c.c
@@ -0,0 +1,56 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "hooks.h"
+#include "i2c.h"
+
+#define BOARD_ID_FAST_PLUS_CAPABLE 2
+
+/* I2C port map configuration */
+const struct i2c_port_t i2c_ports[] = {
+	{
+		/* I2C1 */
+		.name = "tcpc0",
+		.port = I2C_PORT_USB_C0_TCPC,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_USB_C0_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_SDA,
+	},
+	{
+		/* I2C2 */
+		.name = "tcpc2",
+		.port = I2C_PORT_USB_C2_TCPC,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_USB_C2_SCL,
+		.sda = GPIO_EC_I2C_USB_C2_SDA,
+	},
+	{
+		/* I2C5 */
+		.name = "battery",
+		.port = I2C_PORT_BATTERY,
+		.kbps = 100,
+		.scl = GPIO_EC_I2C_BAT_SCL,
+		.sda = GPIO_EC_I2C_BAT_SDA,
+	},
+	{
+		/* I2C6 */
+		.name = "usba1",
+		.port = I2C_PORT_USBA1_RT,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_USBA_RT_SCL,
+		.sda = GPIO_EC_I2C_USBA_RT_SDA,
+	},
+	{
+		/* I2C7 */
+		.name = "eeprom",
+		.port = I2C_PORT_EEPROM,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_MISC_SCL_R,
+		.sda = GPIO_EC_I2C_MISC_SDA_R,
+	},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/board/agah/keyboard.c b/board/agah/keyboard.c
new file mode 100644
index 0000000000..cb34543db8
--- /dev/null
+++ b/board/agah/keyboard.c
@@ -0,0 +1,52 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "ec_commands.h"
+#include "keyboard_scan.h"
+#include "timer.h"
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/* Increase from 50 us, because KSO_02 passes through the H1. */
+	.output_settle_us = 80,
+	/* Other values should be the same as the default configuration. */
+	.debounce_down_us = 9 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x1c, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xa4, 0xff, 0xf6, 0x55, 0xfe, 0xff, 0xff, 0xff, /* full set */
+	},
+};
+
+static const struct ec_response_keybd_config keybd = {
+	.num_top_row_keys = 13,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_KBD_BKLIGHT_TOGGLE,	/* T8 */
+		TK_PLAY_PAUSE,		/* T9 */
+		TK_MICMUTE,		/* T10 */
+		TK_VOL_MUTE,		/* T11 */
+		TK_VOL_DOWN,		/* T12 */
+		TK_VOL_UP,		/* T13 */
+	},
+	/* There's no screen lock key on agah */
+	.capabilities = KEYBD_CAP_NUMERIC_KEYPAD,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &keybd;
+}
diff --git a/board/agah/led.c b/board/agah/led.c
new file mode 100644
index 0000000000..f581da6ebc
--- /dev/null
+++ b/board/agah/led.c
@@ -0,0 +1,192 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery LED control for Agah
+ */
+
+#include "battery.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "chipset.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "host_command.h"
+#include "led_common.h"
+#include "task.h"
+
+#include <stdint.h>
+
+#define BAT_LED_ON 0
+#define BAT_LED_OFF 1
+
+#define BATT_LOW_BCT 10
+
+#define LED_TICK_INTERVAL_MS (500 * MSEC)
+#define LED_CYCLE_TIME_MS (2000 * MSEC)
+#define LED_TICKS_PER_CYCLE (LED_CYCLE_TIME_MS / LED_TICK_INTERVAL_MS)
+#define LED_ON_TIME_MS (1000 * MSEC)
+#define LED_ON_TICKS (LED_ON_TIME_MS / LED_TICK_INTERVAL_MS)
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+enum led_color {
+	LED_OFF = 0,
+	LED_AMBER,
+	LED_WHITE,
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
+};
+
+static void led_set_color_battery(enum led_color color)
+{
+	enum gpio_signal amber_led, white_led;
+
+	amber_led = GPIO_LED_1_L;
+	white_led = GPIO_LED_2_L;
+
+	switch (color) {
+	case LED_WHITE:
+		gpio_set_level(white_led, BAT_LED_ON);
+		gpio_set_level(amber_led, BAT_LED_OFF);
+		break;
+	case LED_AMBER:
+		gpio_set_level(white_led, BAT_LED_OFF);
+		gpio_set_level(amber_led, BAT_LED_ON);
+		break;
+	case LED_OFF:
+		gpio_set_level(white_led, BAT_LED_OFF);
+		gpio_set_level(amber_led, BAT_LED_OFF);
+		break;
+	default:
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	switch (led_id) {
+	case EC_LED_ID_BATTERY_LED:
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		break;
+	default:
+		break;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	switch (led_id) {
+	case EC_LED_ID_BATTERY_LED:
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_battery(LED_WHITE);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(LED_AMBER);
+		else
+			led_set_color_battery(LED_OFF);
+		break;
+	default:
+		return EC_ERROR_PARAM1;
+	}
+
+	return EC_SUCCESS;
+}
+
+/*
+ * Set active charge port color to the parameter, turn off all others.
+ * If no port is active (-1), turn off all LEDs.
+ */
+static void set_active_port_color(enum led_color color)
+{
+	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
+		led_set_color_battery(color);
+}
+
+static void led_set_battery(void)
+{
+	static unsigned int battery_ticks;
+	static unsigned int suspend_ticks;
+
+	battery_ticks++;
+
+	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
+	    led_pwr_get_state() != LED_PWRS_CHARGE) {
+		suspend_ticks++;
+
+		led_set_color_battery(
+			(suspend_ticks % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
+				LED_WHITE :
+				LED_OFF);
+
+		return;
+	}
+
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
+		/* Always indicate when charging, even in suspend. */
+		set_active_port_color(LED_AMBER);
+		break;
+	case LED_PWRS_DISCHARGE:
+		/*
+		 * Blinking amber LEDs slowly if battery is lower 10
+		 * percentage.
+		 */
+		if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
+			if (charge_get_percent() < BATT_LOW_BCT)
+				led_set_color_battery(
+					(battery_ticks % LED_TICKS_PER_CYCLE <
+					 LED_ON_TICKS) ?
+						LED_AMBER :
+						LED_OFF);
+			else
+				led_set_color_battery(LED_OFF);
+		}
+
+		break;
+	case LED_PWRS_ERROR:
+		if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
+			led_set_color_battery(
+				(battery_ticks & 0x1) ? LED_AMBER : LED_OFF);
+		}
+
+		break;
+	case LED_PWRS_CHARGE_NEAR_FULL:
+		set_active_port_color(LED_WHITE);
+		break;
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		set_active_port_color(LED_WHITE);
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		set_active_port_color(
+			(battery_ticks % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
+				LED_AMBER :
+				LED_OFF);
+		break;
+	default:
+		/* Other states don't alter LED behavior */
+		break;
+	}
+}
+
+void led_task(void *u)
+{
+	uint32_t start_time;
+	uint32_t task_duration;
+
+	while (1) {
+		start_time = get_time().le.lo;
+
+		led_set_battery();
+
+		/* Compute time for this iteration */
+		task_duration = get_time().le.lo - start_time;
+		/*
+		 * Compute wait time required to for next desired LED tick. If
+		 * the duration exceeds the tick time, then don't sleep.
+		 */
+		if (task_duration < LED_TICK_INTERVAL_MS)
+			usleep(LED_TICK_INTERVAL_MS - task_duration);
+	}
+}
diff --git a/board/agah/pwm.c b/board/agah/pwm.c
new file mode 100644
index 0000000000..e936feabfb
--- /dev/null
+++ b/board/agah/pwm.c
@@ -0,0 +1,47 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "hooks.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_KBLIGHT] = {
+		.channel = 3,
+		.flags = 0,
+		/*
+		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
+		 * flicker. Higher frequencies consume similar average power to
+		 * lower PWM frequencies, but higher frequencies record a much
+		 * lower maximum power.
+		 */
+		.freq = 2400,
+	},
+	[PWM_CH_FAN] = {
+		.channel = 5,
+		.flags = PWM_CONFIG_OPEN_DRAIN,
+		.freq = 25000
+	},
+	[PWM_CH_FAN2] = {
+		.channel = 4,
+		.flags = PWM_CONFIG_OPEN_DRAIN,
+		.freq = 25000
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+static void board_pwm_init(void)
+{
+	/*
+	 * Turn off all the LEDs.
+	 * Turn on the fan at 100%.
+	 */
+
+	pwm_enable(PWM_CH_KBLIGHT, 1);
+	pwm_set_duty(PWM_CH_KBLIGHT, 50);
+}
+DECLARE_HOOK(HOOK_INIT, board_pwm_init, HOOK_PRIO_DEFAULT);
diff --git a/board/agah/sensors.c b/board/agah/sensors.c
new file mode 100644
index 0000000000..591eb9fccd
--- /dev/null
+++ b/board/agah/sensors.c
@@ -0,0 +1,135 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc.h"
+#include "common.h"
+#include "hooks.h"
+#include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
+#include "thermal.h"
+
+/* ADC configuration */
+struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_1_DDR_SOC] = {
+		.name = "TEMP_DDR_SOC",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_2_GPU] = {
+		.name = "TEMP_GPU",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_3_CHARGER] = {
+		.name = "TEMP_CHARGER",
+		.input_ch = NPCX_ADC_CH6,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_CHARGER_IADP] = {
+		.name = "CHARGER_IADP",
+		.input_ch = NPCX_ADC_CH3,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_ADP_TYP] = {
+		.name = "ADP_TYP",
+		.input_ch = NPCX_ADC_CH4,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* Temperature sensor configuration */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1_DDR_SOC] = {
+		.name = "DDR and SOC",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_1_DDR_SOC,
+	},
+	[TEMP_SENSOR_2_GPU] = {
+		.name = "GPU",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_2_GPU,
+	},
+	[TEMP_SENSOR_3_CHARGER] = {
+		.name = "Charger",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_3_CHARGER,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(85), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(90), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(80), \
+		}, \
+		.temp_fan_off = C_TO_K(35), \
+		.temp_fan_max = C_TO_K(60), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
+
+#define THERMAL_GPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(85), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(90), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(80), \
+		}, \
+		.temp_fan_off = C_TO_K(35), \
+		.temp_fan_max = C_TO_K(60), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_gpu = THERMAL_GPU;
+
+/*
+ * Inductor limits - used for both charger and PP3300 regulator
+ *
+ * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
+ *
+ * Charger max recommended temperature 125C, max absolute temperature 150C
+ * PP3300 regulator: operating range -40 C to 125 C
+ *
+ * Inductors: limit of 125c
+ * PCB: limit is 80c
+ */
+#define THERMAL_CHARGER          \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(105), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(120), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(90), \
+		}, \
+		.temp_fan_off = C_TO_K(35), \
+		.temp_fan_max = C_TO_K(65), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_charger =
+	THERMAL_CHARGER;
+
+struct ec_thermal_config thermal_params[] = {
+	[TEMP_SENSOR_1_DDR_SOC] = THERMAL_CPU,
+	[TEMP_SENSOR_2_GPU] = THERMAL_GPU,
+	[TEMP_SENSOR_3_CHARGER] = THERMAL_CHARGER,
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
diff --git a/board/agah/usbc_config.c b/board/agah/usbc_config.c
new file mode 100644
index 0000000000..ac2fb54b86
--- /dev/null
+++ b/board/agah/usbc_config.c
@@ -0,0 +1,332 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi.h"
+#include "charge_ramp.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/bc12/pi3usb9201_public.h"
+#include "driver/ppc/syv682x_public.h"
+#include "driver/retimer/ps8818_public.h"
+#include "driver/tcpm/rt1715.h"
+#include "driver/tcpm/tcpci.h"
+#include "ec_commands.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "system.h"
+#include "task.h"
+#include "task_id.h"
+#include "timer.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+/* USBC TCPC configuration */
+const struct tcpc_config_t tcpc_config[] = {
+	[USBC_PORT_C0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0_TCPC,
+			.addr_flags = RT1715_I2C_ADDR_FLAGS,
+		},
+		.drv = &rt1715_tcpm_drv,
+	},
+	[USBC_PORT_C2] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C2_TCPC,
+			.addr_flags = RT1715_I2C_ADDR_FLAGS,
+		},
+		.drv = &rt1715_tcpm_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
+BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
+
+/******************************************************************************/
+/* USB-A charging control */
+
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_PP5000_USBA_R,
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
+
+/******************************************************************************/
+
+/* USBC PPC configuration */
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_PPC,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.frs_en = GPIO_USB_C0_FRS_EN,
+		.drv = &syv682x_drv,
+	},
+	[USBC_PORT_C2] = {
+		.i2c_port = I2C_PORT_USB_C2_PPC,
+		.i2c_addr_flags = SYV682X_ADDR2_FLAGS,
+		.frs_en = GPIO_USB_C2_FRS_EN,
+		.drv = &syv682x_drv,
+	},
+};
+
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+const static struct ps8818_reg_val equalizer_default_table[] = {
+	{
+		.reg = PS8818_REG1_APTX1EQ_10G_LEVEL,
+		.mask = PS8818_EQ_LEVEL_UP_MASK,
+		.val = PS8818_EQ_LEVEL_UP_19DB,
+	},
+	{
+		.reg = PS8818_REG1_APTX2EQ_10G_LEVEL,
+		.mask = PS8818_EQ_LEVEL_UP_MASK,
+		.val = PS8818_EQ_LEVEL_UP_19DB,
+	},
+	{
+		.reg = PS8818_REG1_APTX1EQ_5G_LEVEL,
+		.mask = PS8818_EQ_LEVEL_UP_MASK,
+		.val = PS8818_EQ_LEVEL_UP_19DB,
+	},
+	{
+		.reg = PS8818_REG1_APTX2EQ_5G_LEVEL,
+		.mask = PS8818_EQ_LEVEL_UP_MASK,
+		.val = PS8818_EQ_LEVEL_UP_19DB,
+	},
+	{
+		.reg = PS8818_REG1_RX_PHY,
+		.mask = PS8818_RX_INPUT_TERM_MASK,
+		.val = PS8818_RX_INPUT_TERM_112_OHM,
+	},
+};
+
+#define NUM_EQ_DEFAULT_ARRAY ARRAY_SIZE(equalizer_default_table)
+
+int board_ps8818_mux_set(const struct usb_mux *me, mux_state_t mux_state)
+{
+	int rv = EC_SUCCESS;
+	int i;
+
+	/* USB specific config */
+	if (mux_state & USB_PD_MUX_USB_ENABLED) {
+		/* Boost the USB gain */
+		for (i = 0; i < NUM_EQ_DEFAULT_ARRAY; i++)
+			rv |= ps8818_i2c_field_update8(
+				me, PS8818_REG_PAGE1,
+				equalizer_default_table[i].reg,
+				equalizer_default_table[i].mask,
+				equalizer_default_table[i].val);
+	}
+
+	/* DP specific config */
+	if (mux_state & USB_PD_MUX_DP_ENABLED) {
+		/* Boost the DP gain */
+		rv |= ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					       PS8818_REG1_DPEQ_LEVEL,
+					       PS8818_DPEQ_LEVEL_UP_MASK,
+					       PS8818_DPEQ_LEVEL_UP_19DB);
+	}
+
+	return rv;
+}
+
+const static struct usb_mux_chain usbc2_ps8818 = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C2,
+			.i2c_port = I2C_PORT_USB_C2_TCPC,
+			.i2c_addr_flags = PS8818_I2C_ADDR0_FLAGS,
+			.driver = &ps8818_usb_retimer_driver,
+			.board_set = &board_ps8818_mux_set,
+		},
+};
+
+/* USBC mux configuration - Alder Lake includes internal mux */
+const struct usb_mux_chain usb_muxes[] = {
+	[USBC_PORT_C0] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+	},
+	[USBC_PORT_C2] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C2,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc2_ps8818,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
+
+/* BC1.2 charger detect configuration */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+	[USBC_PORT_C2] = {
+		.i2c_port = I2C_PORT_USB_C2_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
+
+#ifdef CONFIG_CHARGE_RAMP_SW
+
+#define BC12_MIN_VOLTAGE 4400
+
+/**
+ * Return true if VBUS is too low
+ */
+int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
+{
+	int voltage;
+
+	if (charger_get_vbus_voltage(port, &voltage))
+		voltage = 0;
+
+	if (voltage == 0) {
+		CPRINTS("%s: must be disconnected", __func__);
+		return 1;
+	}
+
+	if (voltage < BC12_MIN_VOLTAGE) {
+		CPRINTS("%s: port %d: vbus %d lower than %d", __func__, port,
+			voltage, BC12_MIN_VOLTAGE);
+		return 1;
+	}
+
+	return 0;
+}
+
+#endif /* CONFIG_CHARGE_RAMP_SW */
+
+void board_reset_pd_mcu(void)
+{
+	/* There's no reset pin on TCPC */
+}
+
+static void board_tcpc_init(void)
+{
+	/* Don't reset TCPCs after initial reset */
+	if (!system_jumped_late())
+		board_reset_pd_mcu();
+
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C2_PPC_INT_ODL);
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C2_TCPC_INT_ODL);
+
+	/* Enable BC1.2 interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C2_BC12_INT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_0;
+
+	if (gpio_get_level(GPIO_USB_C2_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
+
+int ppc_get_alert_status(int port)
+{
+	if (port == USBC_PORT_C0)
+		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
+
+	if (port == USBC_PORT_C2)
+		return gpio_get_level(GPIO_USB_C2_PPC_INT_ODL) == 0;
+
+	return 0;
+}
+
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C2_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C2);
+		break;
+	default:
+		break;
+	}
+}
+
+void bc12_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_BC12_INT_ODL:
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+		break;
+	case GPIO_USB_C2_BC12_INT_ODL:
+		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+		break;
+	default:
+		break;
+	}
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C2_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C2);
+		break;
+	default:
+		break;
+	}
+}
+
+void retimer_interrupt(enum gpio_signal signal)
+{
+}
+
+__override bool board_is_dts_port(int port)
+{
+	return port == USBC_PORT_C0;
+}
+
+__override bool board_is_tbt_usb4_port(int port)
+{
+	return false;
+}
+
+__override enum tbt_compat_cable_speed board_get_max_tbt_speed(int port)
+{
+	if (!board_is_tbt_usb4_port(port))
+		return TBT_SS_RES_0;
+
+	return TBT_SS_TBT_GEN3;
+}
diff --git a/board/agah/usbc_config.h b/board/agah/usbc_config.h
new file mode 100644
index 0000000000..e353263f5f
--- /dev/null
+++ b/board/agah/usbc_config.h
@@ -0,0 +1,21 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Agah board-specific USB-C configuration */
+
+#ifndef __CROS_EC_USBC_CONFIG_H
+#define __CROS_EC_USBC_CONFIG_H
+
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C2, USBC_PORT_COUNT };
+
+struct ps8818_reg_val {
+	uint8_t reg;
+	uint8_t mask;
+	uint16_t val;
+};
+
+#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/agah/vif_override.xml b/board/agah/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/agah/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/akemi/battery.c b/board/akemi/battery.c
index 238716b116..de380ac01c 100644
--- a/board/akemi/battery.c
+++ b/board/akemi/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/akemi/board.c b/board/akemi/board.c
index cc78e77f0c..0665ca1c4e 100644
--- a/board/akemi/board.c
+++ b/board/akemi/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,7 @@
 /* Hatch board-specific configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
+#include "battery_smart.h"
 #include "button.h"
 #include "common.h"
 #include "cros_board_info.h"
@@ -35,17 +35,16 @@
 #include "system.h"
 #include "task.h"
 #include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
 #include "thermal.h"
-#include "thermistor.h"
 #include "uart.h"
 #include "usb_charge.h"
 #include "usb_pd.h"
 #include "usbc_ppc.h"
 #include "util.h"
-#include "battery_smart.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* GPIO to enable/disable the USB Type-A port. */
 const int usb_port_enable[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT] = {
@@ -90,11 +89,11 @@ static void bc12_interrupt(enum gpio_signal signal)
 {
 	switch (signal) {
 	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
 		break;
 
 	case GPIO_USB_C1_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12, 0);
+		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
 		break;
 
 	default:
@@ -102,20 +101,21 @@ static void bc12_interrupt(enum gpio_signal signal)
 	}
 }
 
-#include "gpio_list.h" /* Must come after other header files. */
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
 
 /******************************************************************************/
 /* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
+const struct spi_device_t spi_devices[] = {};
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
 /******************************************************************************/
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT]   = { .channel = 3, .flags = 0, .freq = 10000 },
-	[PWM_CH_FAN] = {.channel = 5, .flags = PWM_CONFIG_OPEN_DRAIN,
-			.freq = 25000},
+	[PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 },
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
@@ -135,22 +135,26 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = I2C_PORT_TCPC1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
 		},
 		.drv = &ps8xxx_tcpm_drv,
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_TCPC_0] = {
-		.usb_port = USB_PD_PORT_TCPC_0,
-		.driver = &anx7447_usb_mux_driver,
-		.hpd_update = &anx7447_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_0,
+			.driver = &anx7447_usb_mux_driver,
+			.hpd_update = &anx7447_tcpc_update_hpd_status,
+		},
 	},
 	[USB_PD_PORT_TCPC_1] = {
-		.usb_port = USB_PD_PORT_TCPC_1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 	}
 };
 
@@ -178,17 +182,13 @@ static struct stprivate_data g_lis2dwl_data;
 static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
 
 /* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, FLOAT_TO_FP(1), 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
 
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+					     { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
@@ -228,8 +228,6 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_base_mutex,
 		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
 				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
 		.port = I2C_PORT_ACCEL,
 		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
 		.rot_standard_ref = &base_standard_ref,
@@ -260,8 +258,6 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_base_mutex,
 		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
 				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
 		.port = I2C_PORT_ACCEL,
 		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
 		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
@@ -272,13 +268,12 @@ struct motion_sensor_t motion_sensors[] = {
 };
 unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
-
 /******************************************************************************/
 /* Physical fans. These are logically separate from pwm_channels. */
 
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
@@ -297,56 +292,60 @@ const struct fan_t fans[FAN_CH_COUNT] = {
 /******************************************************************************/
 /* MFT channels. These are logically separate from pwm_channels. */
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN },
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_2] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_1] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_2] = { "TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Temp1",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Temp2",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "Temp3",
-				 .type = TEMP_SENSOR_TYPE_CPU,
-				 .read = g753_get_val,
-				 .idx = 0},
+	[TEMP_SENSOR_1] = { .name = "Temp1",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Temp2",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "Temp3",
+			    .type = TEMP_SENSOR_TYPE_CPU,
+			    .read = g753_get_val,
+			    .idx = 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
-
 /* Hatch Temperature sensors */
 /*
  * TODO(b/124316213): These setting need to be reviewed and set appropriately
  * for Hatch. They matter when the EC is controlling the fan as opposed to DPTF
  * control.
  */
-const static struct ec_thermal_config thermal_a = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(25),
-	.temp_fan_max = C_TO_K(50),
-};
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_A                \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+		.temp_fan_off = C_TO_K(25), \
+		.temp_fan_max = C_TO_K(50), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A;
 
 struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
 
@@ -391,12 +390,12 @@ __override uint32_t board_override_feature_flags0(uint32_t flags0)
 }
 
 /* Battery functions */
-#define SB_OPTIONALMFG_FUNCTION2        0x26
-#define QUICK_CHARGE_SUPPORT            0x01
-#define QUICK_CHARGE_ENABLE             0x02
+#define SB_OPTIONALMFG_FUNCTION2 0x26
+#define QUICK_CHARGE_SUPPORT 0x01
+#define QUICK_CHARGE_ENABLE 0x02
 
-#define SB_QUICK_CHARGE_ENABLE          1
-#define SB_QUICK_CHARGE_DISABLE         0
+#define SB_QUICK_CHARGE_ENABLE 1
+#define SB_QUICK_CHARGE_DISABLE 0
 
 static void sb_quick_charge_mode(int enable)
 {
@@ -422,7 +421,8 @@ static void board_chipset_startup(void)
 	/* Normal charge current */
 	sb_quick_charge_mode(SB_QUICK_CHARGE_DISABLE);
 }
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_INIT_I2C+1);
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup,
+	     HOOK_PRIO_INIT_I2C + 1);
 
 /* Called on AP S0 -> S5 transition */
 static void board_chipset_shutdown(void)
@@ -437,5 +437,5 @@ bool board_is_convertible(void)
 	const uint8_t sku = get_board_sku();
 
 	return (sku == 255) || (sku == 1) || (sku == 2) || (sku == 3) ||
-		(sku == 4);
+	       (sku == 4);
 }
diff --git a/board/akemi/board.h b/board/akemi/board.h
index 2d4482a8d6..bdc18638f8 100644
--- a/board/akemi/board.h
+++ b/board/akemi/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,9 +15,8 @@
 #define CONFIG_KEYBOARD_PROTOCOL_8042
 #define CONFIG_LED_COMMON
 #define CONFIG_LOW_POWER_IDLE
-#define CONFIG_LED_POWER_LED
 
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 
 #undef CONFIG_UART_TX_BUF_SIZE
 #define CONFIG_UART_TX_BUF_SIZE 4096
@@ -27,7 +26,6 @@
 
 /* Sensors */
 /* LSM6DS3TR-C Base accel/gyro */
-#define CONFIG_ACCEL_INTERRUPTS
 #define CONFIG_ACCELGYRO_LSM6DSM
 #define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
@@ -92,7 +90,7 @@
 #define CONFIG_FANS 1
 #undef CONFIG_FAN_INIT_SPEED
 #define CONFIG_FAN_INIT_SPEED 50
-#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_A_RAILS
+#define CONFIG_TEMP_SENSOR_POWER
 #define CONFIG_THERMISTOR
 #define CONFIG_THROTTLE_AP
 #define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
@@ -104,15 +102,16 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_AC_PRESENT		GPIO_ACOK_OD
-#define GPIO_RSMRST_L_PGOOD	GPIO_PG_EC_RSMRST_L
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
+#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
 
 #ifndef __ASSEMBLER__
 
@@ -120,8 +119,8 @@
 #include "registers.h"
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_1,	/* ADC0 */
-	ADC_TEMP_SENSOR_2,	/* ADC1 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
 	ADC_CH_COUNT
 };
 
@@ -132,11 +131,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_FAN,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_FAN, PWM_CH_COUNT };
 
 enum fan_channel {
 	FAN_CH_0 = 0,
diff --git a/board/akemi/build.mk b/board/akemi/build.mk
index 733912454f..13153c1526 100644
--- a/board/akemi/build.mk
+++ b/board/akemi/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/akemi/ec.tasklist b/board/akemi/ec.tasklist
index 4a1024a091..829be2b7c8 100644
--- a/board/akemi/ec.tasklist
+++ b/board/akemi/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/akemi/gpio.inc b/board/akemi/gpio.inc
index 1ea8cca58a..05466078c7 100644
--- a/board/akemi/gpio.inc
+++ b/board/akemi/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,10 +16,10 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(PG_EC_RSMRST_L,       PIN(E, 2), GPIO_INT_BOTH, intel_x86_rsmrst_signal_interrupt)
diff --git a/board/akemi/led.c b/board/akemi/led.c
index 977acb86ab..b1fa2ddbb6 100644
--- a/board/akemi/led.c
+++ b/board/akemi/led.c
@@ -1,54 +1,57 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Power and battery LED control for Akemi
  */
 
+#include "chipset.h"
 #include "ec_commands.h"
 #include "gpio.h"
 #include "led_common.h"
 #include "led_onoff_states.h"
-#include "chipset.h"
 
 #define LED_ON_LVL 0
 #define LED_OFF_LVL 1
 
-const int led_charge_lvl_1 = 5;
-
-const int led_charge_lvl_2 = 97;
-
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
-
-const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-					{LED_OFF,          0.5 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-	EC_LED_ID_BATTERY_LED
-};
+__override const int led_charge_lvl_1 = 5;
+
+__override const int led_charge_lvl_2 = 97;
+
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
+
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 3 * LED_ONE_SEC },
+					       { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED,
+					     EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-void led_set_color_power(enum ec_led_colors color)
+__override void led_set_color_power(enum ec_led_colors color)
 {
 	if (color == EC_LED_COLOR_WHITE)
 		gpio_set_level(GPIO_LED_3_L, LED_ON_LVL);
@@ -57,8 +60,7 @@ void led_set_color_power(enum ec_led_colors color)
 		gpio_set_level(GPIO_LED_3_L, LED_OFF_LVL);
 }
 
-
-void led_set_color_battery(enum ec_led_colors color)
+__override void led_set_color_battery(enum ec_led_colors color)
 {
 	switch (color) {
 	case EC_LED_COLOR_RED:
@@ -111,4 +113,3 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 
 	return EC_SUCCESS;
 }
-
diff --git a/board/akemi/vif_override.xml b/board/akemi/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/akemi/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/aleena/battery.c b/board/aleena/battery.c
index b3abae7f73..0862ba209f 100644
--- a/board/aleena/battery.c
+++ b/board/aleena/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/aleena/board.c b/board/aleena/board.c
index 102115ef7f..920b339bdf 100644
--- a/board/aleena/board.c
+++ b/board/aleena/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,10 @@
 /* Aleena board-specific configuration */
 
 #include "button.h"
+#include "console.h"
 #include "driver/accelgyro_bmi_common.h"
+#include "driver/accelgyro_icm426xx.h"
+#include "driver/accelgyro_icm_common.h"
 #include "driver/led/lm3630a.h"
 #include "extpower.h"
 #include "hooks.h"
@@ -18,7 +21,9 @@
 #include "pwm_chip.h"
 #include "switch.h"
 #include "tablet_mode.h"
+#include "task.h"
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 const enum gpio_signal hibernate_wake_pins[] = {
@@ -27,16 +32,40 @@ const enum gpio_signal hibernate_wake_pins[] = {
 	GPIO_POWER_BUTTON_L,
 	GPIO_EC_RST_ODL,
 };
-const int hibernate_wake_pins_used =  ARRAY_SIZE(hibernate_wake_pins);
+const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 
 /* I2C port map. */
 const struct i2c_port_t i2c_ports[] = {
-	{"power",   I2C_PORT_POWER,   100, GPIO_I2C0_SCL, GPIO_I2C0_SDA},
-	{"tcpc0",   I2C_PORT_TCPC0,   400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"tcpc1",   I2C_PORT_TCPC1,   400, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-	{"thermal", I2C_PORT_THERMAL_AP, 400, GPIO_I2C3_SCL, GPIO_I2C3_SDA},
-	{"kblight", I2C_PORT_KBLIGHT, 100, GPIO_I2C5_SCL, GPIO_I2C5_SDA},
-	{"sensor",  I2C_PORT_SENSOR,  400, GPIO_I2C7_SCL, GPIO_I2C7_SDA},
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_I2C0_SCL,
+	  .sda = GPIO_I2C0_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "tcpc1",
+	  .port = I2C_PORT_TCPC1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "thermal",
+	  .port = I2C_PORT_THERMAL_AP,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
+	{ .name = "kblight",
+	  .port = I2C_PORT_KBLIGHT,
+	  .kbps = 100,
+	  .scl = GPIO_I2C5_SCL,
+	  .sda = GPIO_I2C5_SDA },
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_I2C7_SCL,
+	  .sda = GPIO_I2C7_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -50,6 +79,113 @@ const struct pwm_t pwm_channels[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
+/* Motion sensors */
+static struct mutex icm426xx_mutex;
+
+static struct icm_drv_data_t g_icm426xx_data;
+
+enum base_accelgyro_type {
+	BASE_GYRO_NONE = 0,
+	BASE_GYRO_BMI160 = 1,
+	BASE_GYRO_ICM426XX = 2,
+};
+
+const mat33_fp_t base_standard_ref_icm426xx = { { 0, FLOAT_TO_FP(-1), 0 },
+						{ FLOAT_TO_FP(1), 0, 0 },
+						{ 0, 0, FLOAT_TO_FP(1) } };
+
+struct motion_sensor_t icm426xx_base_accel = {
+	 .name = "Base Accel",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_ICM426XX,
+	 .type = MOTIONSENSE_TYPE_ACCEL,
+	 .location = MOTIONSENSE_LOC_BASE,
+	 .drv = &icm426xx_drv,
+	 .mutex = &icm426xx_mutex,
+	 .drv_data = &g_icm426xx_data,
+	 .port = I2C_PORT_SENSOR,
+	 .i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	 .default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
+	 .rot_standard_ref = &base_standard_ref_icm426xx,
+	 .min_frequency = ICM426XX_ACCEL_MIN_FREQ,
+	 .max_frequency = ICM426XX_ACCEL_MAX_FREQ,
+	 .config = {
+		 /* EC use accel for angle detection */
+		 [SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100,
+		 },
+		 /* EC use accel for angle detection */
+		 [SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		 },
+	 },
+};
+
+struct motion_sensor_t icm426xx_base_gyro = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &icm426xx_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &base_standard_ref_icm426xx,
+	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
+	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
+};
+
+static enum base_accelgyro_type base_accelgyro_config;
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	switch (base_accelgyro_config) {
+	case BASE_GYRO_ICM426XX:
+		icm426xx_interrupt(signal);
+		break;
+	case BASE_GYRO_BMI160:
+	default:
+		bmi160_interrupt(signal);
+		break;
+	}
+}
+
+static void board_detect_motionsensor(void)
+{
+	int ret;
+	int val;
+
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return;
+	if (base_accelgyro_config != BASE_GYRO_NONE)
+		return;
+
+	if (board_is_convertible()) {
+		/* Check base accelgyro chip */
+		ret = icm_read8(&icm426xx_base_accel, ICM426XX_REG_WHO_AM_I,
+				&val);
+		if (ret)
+			ccprints("Get ICM fail.");
+		if (val == ICM426XX_CHIP_ICM40608) {
+			motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
+			motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
+		}
+		base_accelgyro_config = (val == ICM426XX_CHIP_ICM40608) ?
+						BASE_GYRO_ICM426XX :
+						BASE_GYRO_BMI160;
+		ccprints("Base Accelgyro: %s", (val == ICM426XX_CHIP_ICM40608) ?
+						       "ICM40608" :
+						       "BMI160");
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_detect_motionsensor,
+	     HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_INIT, board_detect_motionsensor, HOOK_PRIO_INIT_ADC + 2);
+
 void board_update_sensor_config_from_sku(void)
 {
 	if (board_is_convertible()) {
@@ -58,10 +194,9 @@ void board_update_sensor_config_from_sku(void)
 	} else {
 		motion_sensor_count = 0;
 		/* Device is clamshell only */
-		tablet_set_mode(0);
+		tablet_set_mode(0, TABLET_TRIGGER_LID);
 		/* Gyro is not present, don't allow line to float */
-		gpio_set_flags(GPIO_6AXIS_INT_L,
-			       GPIO_INPUT | GPIO_PULL_DOWN);
+		gpio_set_flags(GPIO_6AXIS_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
 	}
 }
 
@@ -83,15 +218,14 @@ DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_kblight_init, HOOK_PRIO_DEFAULT);
  * The connector has 30 pins total, and there is no pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-		{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-		{0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3},
-		{-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0},
-		{1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4},
-		{2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0},
-		{-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1},
-		{-1, -1},
+	{ -1, -1 }, { 0, 5 },	{ 1, 1 }, { 1, 0 },   { 0, 6 },	  { 0, 7 },
+	{ -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 },   { -1, -1 }, { 1, 6 },
+	{ 1, 7 },   { 3, 1 },	{ 2, 0 }, { 1, 5 },   { 2, 6 },	  { 2, 7 },
+	{ 2, 1 },   { 2, 4 },	{ 2, 5 }, { 1, 2 },   { 2, 3 },	  { 2, 2 },
+	{ 3, 0 },   { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 },	  { -1, -1 },
+	{ -1, -1 },
 };
 
 const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 #endif
diff --git a/board/aleena/board.h b/board/aleena/board.h
index 76350a76e6..f51b7b3e16 100644
--- a/board/aleena/board.h
+++ b/board/aleena/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,7 @@
  * By default, enable all console messages excepted HC, ACPI and event:
  * The sensor stack is generating a lot of activity.
  */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
 #undef CONFIG_HOSTCMD_DEBUG_MODE
 #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
 
@@ -37,7 +37,9 @@
 #define CONFIG_ACCELGYRO_BMI160
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCEL_INTERRUPTS
+#define CONFIG_ACCELGYRO_ICM426XX /* Base accel second source*/
+#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 #define CONFIG_ACCEL_KX022
 #define CONFIG_CMD_ACCELS
 #define CONFIG_CMD_ACCEL_INFO
@@ -49,17 +51,14 @@
 /*
  * Slew rate on the PP1800_SENSOR load switch requires a short delay on startup.
  */
-#undef  CONFIG_MOTION_SENSE_RESUME_DELAY_US
+#undef CONFIG_MOTION_SENSE_RESUME_DELAY_US
 #define CONFIG_MOTION_SENSE_RESUME_DELAY_US (10 * MSEC)
 
 #define CONFIG_KEYBOARD_FACTORY_TEST
 
 #ifndef __ASSEMBLER__
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_COUNT };
 
 enum battery_type {
 	BATTERY_PANASONIC,
@@ -68,10 +67,7 @@ enum battery_type {
 	BATTERY_TYPE_COUNT,
 };
 
-#ifdef CONFIG_KEYBOARD_FACTORY_TEST
-extern const int keyboard_factory_scan_pins[][2];
-extern const int keyboard_factory_scan_pins_used;
-#endif
+void motion_interrupt(enum gpio_signal signal);
 
 #endif /* !__ASSEMBLER__ */
 
diff --git a/board/aleena/build.mk b/board/aleena/build.mk
index c808e65aed..d24127ddae 100644
--- a/board/aleena/build.mk
+++ b/board/aleena/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/aleena/ec.tasklist b/board/aleena/ec.tasklist
index dc898c4502..9572d61c8f 100644
--- a/board/aleena/ec.tasklist
+++ b/board/aleena/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/aleena/gpio.inc b/board/aleena/gpio.inc
index e5cf59ba53..669c833e56 100644
--- a/board/aleena/gpio.inc
+++ b/board/aleena/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,7 +23,7 @@ GPIO_INT(WP_L,			PIN(A, 1), GPIO_INT_BOTH,			switch_interrupt)
 GPIO_INT(VOLUME_DOWN_L,		PIN(7, 0), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
 GPIO_INT(VOLUME_UP_L,		PIN(7, 5), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
 GPIO_INT(USB_C0_CABLE_DET,	PIN(3, 7), GPIO_INT_RISING,			anx74xx_cable_det_interrupt)
-GPIO_INT(6AXIS_INT_L,		PIN(8, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V,	bmi160_interrupt)
+GPIO_INT(6AXIS_INT_L,		PIN(8, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V,	motion_interrupt)
 
 /* GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an interrupt handler. */
 GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH | GPIO_LOCKED)
diff --git a/board/aleena/led.c b/board/aleena/led.c
index 430400e6ae..359e9814ca 100644
--- a/board/aleena/led.c
+++ b/board/aleena/led.c
@@ -1,23 +1,23 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "common.h"
-#include "led_onoff_states.h"
-#include "led_common.h"
+#include "console.h"
 #include "gpio.h"
 #include "hooks.h"
-#include "console.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
 
-#define CPRINTS(format, args...) cprints(CC_HOOK, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_HOOK, format, ##args)
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
-const int led_charge_lvl_1;
+__override const int led_charge_lvl_1;
 
-const int led_charge_lvl_2 = 100;
+__override const int led_charge_lvl_2 = 100;
 
 /*
  *	board_id	others	5, 6
@@ -28,19 +28,25 @@ static enum gpio_signal led_amber = GPIO_BAT_LED_1_L;
 static enum gpio_signal led_blue = GPIO_BAT_LED_2_L;
 
 /* Note there is only LED for charge / power */
-struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,  2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
 const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
@@ -48,10 +54,9 @@ const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 static void board_led_init(void)
 {
-	int board_id =
-		(gpio_get_level(GPIO_BOARD_VERSION3) << 2) |
-		(gpio_get_level(GPIO_BOARD_VERSION2) << 1) |
-		(gpio_get_level(GPIO_BOARD_VERSION1) << 0);
+	int board_id = (gpio_get_level(GPIO_BOARD_VERSION3) << 2) |
+		       (gpio_get_level(GPIO_BOARD_VERSION2) << 1) |
+		       (gpio_get_level(GPIO_BOARD_VERSION1) << 0);
 
 	CPRINTS("board_id=%d", board_id);
 
@@ -60,11 +65,10 @@ static void board_led_init(void)
 		led_blue = GPIO_BAT_LED_1_L;
 		CPRINTS("LED: switch LED");
 	}
-
 }
 DECLARE_HOOK(HOOK_INIT, board_led_init, HOOK_PRIO_DEFAULT);
 
-void led_set_color_battery(enum ec_led_colors color)
+__override void led_set_color_battery(enum ec_led_colors color)
 {
 	switch (color) {
 	case EC_LED_COLOR_BLUE:
diff --git a/board/aleena/vif_override.xml b/board/aleena/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/aleena/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/ambassador/board.c b/board/ambassador/board.c
new file mode 100644
index 0000000000..dd839574b5
--- /dev/null
+++ b/board/ambassador/board.c
@@ -0,0 +1,987 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Puff board-specific configuration */
+
+#include "adc.h"
+#include "button.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "chipset.h"
+#include "common.h"
+#include "core/cortex-m/cpu.h"
+#include "cros_board_info.h"
+#include "driver/ina3221.h"
+#include "driver/ppc/sn5s330.h"
+#include "driver/tcpm/anx7447.h"
+#include "driver/tcpm/ps8xxx.h"
+#include "driver/tcpm/tcpci.h"
+#include "ec_commands.h"
+#include "extpower.h"
+#include "fan.h"
+#include "fan_chip.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power/cometlake-discrete.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "spi.h"
+#include "switch.h"
+#include "system.h"
+#include "task.h"
+#include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
+#include "thermal.h"
+#include "uart.h"
+#include "usb_charge.h"
+#include "usb_common.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+static void power_monitor(void);
+DECLARE_DEFERRED(power_monitor);
+
+static void ppc_interrupt(enum gpio_signal signal)
+{
+	if (signal == GPIO_USB_C0_TCPPC_INT_ODL)
+		sn5s330_interrupt(0);
+}
+
+int ppc_get_alert_status(int port)
+{
+	return gpio_get_level(GPIO_USB_C0_TCPPC_INT_ODL) == 0;
+}
+
+static void tcpc_alert_event(enum gpio_signal signal)
+{
+	if (signal == GPIO_USB_C0_TCPC_INT_ODL)
+		schedule_deferred_pd_interrupt(0);
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+	int level;
+
+	/*
+	 * Check which port has the ALERT line set and ignore if that TCPC has
+	 * its reset line active.
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL)) {
+		level = !!(tcpc_config[USB_PD_PORT_TCPC_0].flags &
+			   TCPC_FLAGS_RESET_ACTIVE_HIGH);
+		if (gpio_get_level(GPIO_USB_C0_TCPC_RST) != level)
+			status |= PD_STATUS_TCPC_ALERT_0;
+	}
+
+	return status;
+}
+
+/* Called when the charge manager has switched to a new port. */
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
+{
+	/* Blink alert if insufficient power per system_can_boot_ap(). */
+	int insufficient_power =
+		(charge_ma * charge_mv) <
+		(CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON * 1000);
+	led_alert(insufficient_power);
+}
+
+static uint8_t usbc_overcurrent;
+static int32_t base_5v_power;
+
+/*
+ * Power usage for each port as measured or estimated.
+ * Units are milliwatts (5v x ma current)
+ */
+#define PWR_BASE_LOAD (5 * 1335)
+#define PWR_FRONT_HIGH (5 * 1603)
+#define PWR_FRONT_LOW (5 * 963)
+#define PWR_REAR (5 * 1075)
+#define PWR_HDMI (5 * 562)
+#define PWR_C_HIGH (5 * 3740)
+#define PWR_C_LOW (5 * 2090)
+#define PWR_MAX (5 * 10000)
+
+/*
+ * Update the 5V power usage, assuming no throttling,
+ * and invoke the power monitoring.
+ */
+static void update_5v_usage(void)
+{
+	int front_ports = 0;
+	/*
+	 * Recalculate the 5V load, assuming no throttling.
+	 */
+	base_5v_power = PWR_BASE_LOAD;
+	if (!gpio_get_level(GPIO_USB_A0_OC_ODL)) {
+		front_ports++;
+		base_5v_power += PWR_FRONT_LOW;
+	}
+	if (!gpio_get_level(GPIO_USB_A1_OC_ODL)) {
+		front_ports++;
+		base_5v_power += PWR_FRONT_LOW;
+	}
+	/*
+	 * Only 1 front port can run higher power at a time.
+	 */
+	if (front_ports > 0)
+		base_5v_power += PWR_FRONT_HIGH - PWR_FRONT_LOW;
+	if (!gpio_get_level(GPIO_USB_A2_OC_ODL))
+		base_5v_power += PWR_REAR;
+	if (!gpio_get_level(GPIO_USB_A3_OC_ODL))
+		base_5v_power += PWR_REAR;
+	if (ec_config_get_usb4_present() && !gpio_get_level(GPIO_USB_A4_OC_ODL))
+		base_5v_power += PWR_REAR;
+	if (!gpio_get_level(GPIO_HDMI_CONN0_OC_ODL))
+		base_5v_power += PWR_HDMI;
+	if (!gpio_get_level(GPIO_HDMI_CONN1_OC_ODL))
+		base_5v_power += PWR_HDMI;
+	if (usbc_overcurrent)
+		base_5v_power += PWR_C_HIGH;
+	/*
+	 * Invoke the power handler immediately.
+	 */
+	hook_call_deferred(&power_monitor_data, 0);
+}
+DECLARE_DEFERRED(update_5v_usage);
+/*
+ * Start power monitoring after ADCs have been initialised.
+ */
+DECLARE_HOOK(HOOK_INIT, update_5v_usage, HOOK_PRIO_INIT_ADC + 1);
+
+static void port_ocp_interrupt(enum gpio_signal signal)
+{
+	hook_call_deferred(&update_5v_usage_data, 0);
+}
+
+/******************************************************************************/
+/*
+ * Barrel jack power supply handling
+ *
+ * EN_PPVAR_BJ_ADP_L must default active to ensure we can power on when the
+ * barrel jack is connected, and the USB-C port can bring the EC up fine in
+ * dead-battery mode. Both the USB-C and barrel jack switches do reverse
+ * protection, so we're safe to turn one on then the other off- but we should
+ * only do that if the system is off since it might still brown out.
+ */
+
+/*
+ * Barrel-jack power adapter ratings.
+ */
+static const struct {
+	int voltage;
+	int current;
+} bj_power[] = {
+	{ /* 0 - 65W (also default) */
+	  .voltage = 19000,
+	  .current = 3420 },
+	{ /* 1 - 90W */
+	  .voltage = 19000,
+	  .current = 4740 },
+};
+
+#define ADP_DEBOUNCE_MS 1000 /* Debounce time for BJ plug/unplug */
+/* Debounced connection state of the barrel jack */
+static int8_t adp_connected = -1;
+static void adp_connect_deferred(void)
+{
+	struct charge_port_info pi = { 0 };
+	int connected = !gpio_get_level(GPIO_BJ_ADP_PRESENT_L);
+
+	/* Debounce */
+	if (connected == adp_connected)
+		return;
+	if (connected) {
+		unsigned int bj = ec_config_get_bj_power();
+
+		pi.voltage = bj_power[bj].voltage;
+		pi.current = bj_power[bj].current;
+	}
+	charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED,
+				     DEDICATED_CHARGE_PORT, &pi);
+	adp_connected = connected;
+}
+DECLARE_DEFERRED(adp_connect_deferred);
+
+/* IRQ for BJ plug/unplug. It shouldn't be called if BJ is the power source. */
+void adp_connect_interrupt(enum gpio_signal signal)
+{
+	hook_call_deferred(&adp_connect_deferred_data, ADP_DEBOUNCE_MS * MSEC);
+}
+
+static void adp_state_init(void)
+{
+	/*
+	 * Initialize all charge suppliers to 0. The charge manager waits until
+	 * all ports have reported in before doing anything.
+	 */
+	for (int i = 0; i < CHARGE_PORT_COUNT; i++) {
+		for (int j = 0; j < CHARGE_SUPPLIER_COUNT; j++)
+			charge_manager_update_charge(j, i, NULL);
+	}
+
+	/* Report charge state from the barrel jack. */
+	adp_connect_deferred();
+}
+DECLARE_HOOK(HOOK_INIT, adp_state_init, HOOK_PRIO_INIT_CHARGE_MANAGER + 1);
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/******************************************************************************/
+/* SPI devices */
+const struct spi_device_t spi_devices[] = {};
+const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
+
+/******************************************************************************/
+/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
+	[PWM_CH_LED_RED] = { .channel = 0,
+			     .flags = PWM_CONFIG_DSLEEP,
+			     .freq = 2000 },
+	[PWM_CH_LED_WHITE] = { .channel = 2,
+			       .flags = PWM_CONFIG_DSLEEP,
+			       .freq = 2000 },
+};
+
+/******************************************************************************/
+/* USB-C TCPC Configuration */
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	[USB_PD_PORT_TCPC_0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TCPC0,
+			.addr_flags = AN7447_TCPC0_I2C_ADDR_FLAGS,
+		},
+		.drv = &anx7447_tcpm_drv,
+		.flags = TCPC_FLAGS_RESET_ACTIVE_HIGH,
+	},
+};
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	[USB_PD_PORT_TCPC_0] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_0,
+			.driver = &anx7447_usb_mux_driver,
+			.hpd_update = &anx7447_tcpc_update_hpd_status,
+		},
+	},
+};
+
+/******************************************************************************/
+/* I2C port map configuration */
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "ina",
+	  .port = I2C_PORT_INA,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_SCL,
+	  .sda = GPIO_I2C0_SDA },
+	{ .name = "ppc0",
+	  .port = I2C_PORT_PPC0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 400,
+	  .scl = GPIO_I2C5_SCL,
+	  .sda = GPIO_I2C5_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_I2C7_SCL,
+	  .sda = GPIO_I2C7_SDA },
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+const struct adc_t adc_channels[] = {
+	[ADC_SNS_PP3300] = {
+		/*
+		 * 4700/5631 voltage divider: can take the value out of range
+		 * for 32-bit signed integers, so truncate to 470/563 yielding
+		 * <0.1% error and a maximum intermediate value of 1623457792,
+		 * which comfortably fits in int32.
+		 */
+		.name = "SNS_PP3300",
+		.input_ch = NPCX_ADC_CH2,
+		.factor_mul = ADC_MAX_VOLT * 563,
+		.factor_div = (ADC_READ_MAX + 1) * 470,
+	},
+	[ADC_SNS_PP1050] = {
+		.name = "SNS_PP1050",
+		.input_ch = NPCX_ADC_CH7,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+	},
+	[ADC_VBUS] = {  /* 5/39 voltage divider */
+		.name = "VBUS",
+		.input_ch = NPCX_ADC_CH4,
+		.factor_mul = ADC_MAX_VOLT * 39,
+		.factor_div = (ADC_READ_MAX + 1) * 5,
+	},
+	[ADC_PPVAR_IMON] = {  /* 500 mV/A */
+		.name = "PPVAR_IMON",
+		.input_ch = NPCX_ADC_CH9,
+		.factor_mul = ADC_MAX_VOLT * 2, /* Milliamps */
+		.factor_div = ADC_READ_MAX + 1,
+	},
+	[ADC_TEMP_SENSOR_1] = {
+		.name = "TEMP_SENSOR_1",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_CORE] = {
+		.name = "Core",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_1,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/******************************************************************************/
+/* Wake up pins */
+const enum gpio_signal hibernate_wake_pins[] = {};
+const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
+
+/******************************************************************************/
+/* Physical fans. These are logically separate from pwm_channels. */
+const struct fan_conf fan_conf_0 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
+	.pgood_gpio = -1,
+	.enable_gpio = -1,
+};
+
+const struct fan_rpm fan_rpm_0 = {
+	.rpm_min = 2500,
+	.rpm_start = 2500,
+	.rpm_max = 5200,
+};
+
+const struct fan_t fans[] = {
+	[FAN_CH_0] = { .conf = &fan_conf_0, .rpm = &fan_rpm_0, },
+};
+BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
+
+/******************************************************************************/
+/* MFT channels. These are logically separate from pwm_channels. */
+const struct mft_t mft_channels[] = {
+	[MFT_CH_0] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN },
+};
+BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
+
+/******************************************************************************/
+/* Thermal control; drive fan based on temperature sensors. */
+static const int temp_fan_off = C_TO_K(35);
+static const int temp_fan_max = C_TO_K(55);
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_A                \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(78), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(85), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+		.temp_fan_off = temp_fan_off, \
+		.temp_fan_max = temp_fan_max, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A;
+
+static const struct ec_thermal_config thermal_b = {
+		.temp_host = {
+			[EC_TEMP_THRESH_WARN] = 0,
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(78),
+			[EC_TEMP_THRESH_HALT] = C_TO_K(85),
+		},
+		.temp_host_release = {
+			[EC_TEMP_THRESH_WARN] = 0,
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
+			[EC_TEMP_THRESH_HALT] = 0,
+		},
+	};
+
+struct ec_thermal_config thermal_params[] = {
+	[TEMP_SENSOR_CORE] = THERMAL_A,
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
+
+static const struct fan_step_1_1 fan_table0[] = {
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(35),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(41),
+	  .rpm = 2500 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(40),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(44),
+	  .rpm = 2900 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(42),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(46),
+	  .rpm = 3400 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(44),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(48),
+	  .rpm = 3900 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(46),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(50),
+	  .rpm = 4400 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(48),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(52),
+	  .rpm = 4900 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(50),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(55),
+	  .rpm = 5200 },
+};
+#define NUM_FAN_LEVELS ARRAY_SIZE(fan_table0)
+
+static const struct fan_step_1_1 *fan_table = fan_table0;
+
+int fan_percent_to_rpm(int fan, int temp_ratio)
+{
+	return temp_ratio_to_rpm_hysteresis(fan_table, NUM_FAN_LEVELS, fan,
+					    temp_ratio, NULL);
+}
+
+/* Power sensors */
+const struct ina3221_t ina3221[] = {
+	{ I2C_PORT_INA, 0x40, { "PP3300_G", "PP5000_A", "PP3300_WLAN" } },
+	{ I2C_PORT_INA, 0x42, { "PP3300_A", "PP3300_SSD", "PP3300_LAN" } },
+	{ I2C_PORT_INA, 0x43, { NULL, "PP1200_U", "PP2500_DRAM" } }
+};
+const unsigned int ina3221_count = ARRAY_SIZE(ina3221);
+
+static uint16_t board_version;
+static uint32_t sku_id;
+static uint32_t fw_config;
+
+static void cbi_init(void)
+{
+	/*
+	 * Load board info from CBI to control per-device configuration.
+	 *
+	 * If unset it's safe to treat the board as a proto, just C10 gating
+	 * won't be enabled.
+	 */
+	uint32_t val;
+
+	if (cbi_get_board_version(&val) == EC_SUCCESS && val <= UINT16_MAX)
+		board_version = val;
+	if (cbi_get_sku_id(&val) == EC_SUCCESS)
+		sku_id = val;
+	if (cbi_get_fw_config(&val) == EC_SUCCESS)
+		fw_config = val;
+	CPRINTS("Board Version: %d, SKU ID: 0x%08x, F/W config: 0x%08x",
+		board_version, sku_id, fw_config);
+}
+DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1);
+
+static void board_init(void)
+{
+	uint8_t *memmap_batt_flags;
+
+	/* Override some GPIO interrupt priorities.
+	 *
+	 * These interrupts are timing-critical for AP power sequencing, so we
+	 * increase their NVIC priority from the default of 3. This affects
+	 * whole MIWU groups of 8 GPIOs since they share an IRQ.
+	 *
+	 * Latency at the default priority level can be hundreds of
+	 * microseconds while other equal-priority IRQs are serviced, so GPIOs
+	 * requiring faster response must be higher priority.
+	 */
+	/* CPU_C10_GATE_L on GPIO6.7: must be ~instant for ~60us response. */
+	cpu_set_interrupt_priority(NPCX_IRQ_WKINTH_1, 1);
+	/*
+	 * slp_s3_interrupt (GPIOA.5 on WKINTC_0) must respond within 200us
+	 * (tPLT18); less critical than the C10 gate.
+	 */
+	cpu_set_interrupt_priority(NPCX_IRQ_WKINTC_0, 2);
+
+	gpio_enable_interrupt(GPIO_BJ_ADP_PRESENT_L);
+
+	/* Always claim AC is online, because we don't have a battery. */
+	memmap_batt_flags = host_get_memmap(EC_MEMMAP_BATT_FLAG);
+	*memmap_batt_flags |= EC_BATT_FLAG_AC_PRESENT;
+	/*
+	 * For board version < 2, the directly connected recovery
+	 * button is not available.
+	 */
+	if (board_version < 2)
+		button_disable_gpio(BUTTON_RECOVERY);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+static void board_chipset_startup(void)
+{
+	/*
+	 * Workaround to restore VBUS on PPC.
+	 * PP1 is sourced from PP5000_A, and when the CPU shuts down and
+	 * this rail drops, the PPC will internally turn off PP1_EN.
+	 * When the CPU starts again, and the rail is restored, the PPC
+	 * does not turn PP1_EN on again, causing VBUS to stay turned off.
+	 * The workaround is to check whether the PPC is sourcing VBUS, and
+	 * if so, make sure it is enabled.
+	 */
+	if (ppc_is_sourcing_vbus(0))
+		ppc_vbus_source_enable(0, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
+/******************************************************************************/
+/* USB-C PPC Configuration */
+struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	[USB_PD_PORT_TCPC_0] = { .i2c_port = I2C_PORT_PPC0,
+				 .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+				 .drv = &sn5s330_drv },
+};
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/* USB-A port control */
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_PP5000_USB_VBUS,
+};
+
+/* Power Delivery and charging functions */
+static void board_tcpc_init(void)
+{
+	/*
+	 * Reset TCPC if we have had a system reset.
+	 * With EFSv2, it is possible to be in RW without
+	 * having reset the TCPC.
+	 */
+	if (system_get_reset_flags() & EC_RESET_FLAG_POWER_ON)
+		board_reset_pd_mcu();
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_TCPPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
+	/* Enable other overcurrent interrupts */
+	gpio_enable_interrupt(GPIO_HDMI_CONN0_OC_ODL);
+	gpio_enable_interrupt(GPIO_HDMI_CONN1_OC_ODL);
+	gpio_enable_interrupt(GPIO_USB_A0_OC_ODL);
+	gpio_enable_interrupt(GPIO_USB_A1_OC_ODL);
+	gpio_enable_interrupt(GPIO_USB_A2_OC_ODL);
+	gpio_enable_interrupt(GPIO_USB_A3_OC_ODL);
+	if (ec_config_get_usb4_present()) {
+		/*
+		 * By default configured as output low.
+		 */
+		gpio_set_flags(GPIO_USB_A4_OC_ODL, GPIO_INPUT | GPIO_INT_BOTH);
+		gpio_enable_interrupt(GPIO_USB_A4_OC_ODL);
+	} else {
+		/* Ensure no interrupts from pin */
+		gpio_disable_interrupt(GPIO_USB_A4_OC_ODL);
+	}
+}
+/* Make sure this is called after fw_config is initialised */
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 2);
+
+int64_t get_time_dsw_pwrok(void)
+{
+	/* DSW_PWROK is turned on before EC was powered. */
+	return -20 * MSEC;
+}
+
+void board_reset_pd_mcu(void)
+{
+	int level = !!(tcpc_config[USB_PD_PORT_TCPC_0].flags &
+		       TCPC_FLAGS_RESET_ACTIVE_HIGH);
+
+	gpio_set_level(GPIO_USB_C0_TCPC_RST, level);
+	msleep(BOARD_TCPC_C0_RESET_HOLD_DELAY);
+	gpio_set_level(GPIO_USB_C0_TCPC_RST, !level);
+	if (BOARD_TCPC_C0_RESET_POST_DELAY)
+		msleep(BOARD_TCPC_C0_RESET_POST_DELAY);
+}
+
+int board_set_active_charge_port(int port)
+{
+	CPRINTS("Requested charge port change to %d", port);
+
+	/*
+	 * The charge manager may ask us to switch to no charger if we're
+	 * running off USB-C only but upstream doesn't support PD. It requires
+	 * that we accept this switch otherwise it triggers an assert and EC
+	 * reset; it's not possible to boot the AP anyway, but we want to avoid
+	 * resetting the EC so we can continue to do the "low power" LED blink.
+	 */
+	if (port == CHARGE_PORT_NONE)
+		return EC_SUCCESS;
+
+	if (port < 0 || CHARGE_PORT_COUNT <= port)
+		return EC_ERROR_INVAL;
+
+	if (port == charge_manager_get_active_charge_port())
+		return EC_SUCCESS;
+
+	/* Don't charge from a source port */
+	if (board_vbus_source_enabled(port))
+		return EC_ERROR_INVAL;
+
+	if (!chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
+		int bj_active, bj_requested;
+
+		if (charge_manager_get_active_charge_port() != CHARGE_PORT_NONE)
+			/* Change is only permitted while the system is off */
+			return EC_ERROR_INVAL;
+
+		/*
+		 * Current setting is no charge port but the AP is on, so the
+		 * charge manager is out of sync (probably because we're
+		 * reinitializing after sysjump). Reject requests that aren't
+		 * in sync with our outputs.
+		 */
+		bj_active = !gpio_get_level(GPIO_EN_PPVAR_BJ_ADP_L);
+		bj_requested = port == CHARGE_PORT_BARRELJACK;
+		if (bj_active != bj_requested)
+			return EC_ERROR_INVAL;
+	}
+
+	CPRINTS("New charger p%d", port);
+
+	switch (port) {
+	case CHARGE_PORT_TYPEC0:
+		/* TODO(b/143975429) need to touch the PD controller? */
+		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 1);
+		break;
+	case CHARGE_PORT_BARRELJACK:
+		/* Make sure BJ adapter is sourcing power */
+		if (gpio_get_level(GPIO_BJ_ADP_PRESENT_L))
+			return EC_ERROR_INVAL;
+		/* TODO(b/143975429) need to touch the PD controller? */
+		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 0);
+		break;
+	default:
+		return EC_ERROR_INVAL;
+	}
+
+	return EC_SUCCESS;
+}
+
+void board_overcurrent_event(int port, int is_overcurrented)
+{
+	/* Check that port number is valid. */
+	if ((port < 0) || (port >= CONFIG_USB_PD_PORT_MAX_COUNT))
+		return;
+	usbc_overcurrent = is_overcurrented;
+	update_5v_usage();
+}
+
+int extpower_is_present(void)
+{
+	return adp_connected;
+}
+
+int board_is_c10_gate_enabled(void)
+{
+	/*
+	 * Puff proto drives EN_PP5000_HDMI from EN_S0_RAILS so we cannot gate
+	 * core rails while in S0 because HDMI should remain powered.
+	 * EN_PP5000_HDMI is a separate EC output on all other boards.
+	 */
+	return board_version != 0;
+}
+
+void board_enable_s0_rails(int enable)
+{
+	/* This output isn't connected on protos; safe to set anyway. */
+	gpio_set_level(GPIO_EN_PP5000_HDMI, enable);
+}
+
+unsigned int ec_config_get_bj_power(void)
+{
+	unsigned int bj = (fw_config & EC_CFG_BJ_POWER_MASK) >>
+			  EC_CFG_BJ_POWER_L;
+	/* Out of range value defaults to 0 */
+	if (bj >= ARRAY_SIZE(bj_power))
+		bj = 0;
+	return bj;
+}
+
+int ec_config_get_usb4_present(void)
+{
+	return !(fw_config & EC_CFG_NO_USB4_MASK);
+}
+
+unsigned int ec_config_get_thermal_solution(void)
+{
+	return (fw_config & EC_CFG_THERMAL_MASK) >> EC_CFG_THERMAL_L;
+}
+
+static void setup_thermal(void)
+{
+	unsigned int table = ec_config_get_thermal_solution();
+	/* Configure Fan */
+	switch (table) {
+	/* Default and table0 use single fan */
+	case 0:
+	default:
+		thermal_params[TEMP_SENSOR_CORE] = thermal_a;
+		break;
+	/* Table1 is fanless */
+	case 1:
+		fan_set_count(0);
+		thermal_params[TEMP_SENSOR_CORE] = thermal_b;
+		break;
+	}
+}
+/* fan_set_count should be called before  HOOK_INIT/HOOK_PRIO_DEFAULT */
+DECLARE_HOOK(HOOK_INIT, setup_thermal, HOOK_PRIO_DEFAULT - 1);
+
+/*
+ * Power monitoring and management.
+ *
+ * The overall goal is to gracefully manage the power demand so that
+ * the power budgets are met without letting the system fall into
+ * power deficit (perhaps causing a brownout).
+ *
+ * There are 2 power budgets that need to be managed:
+ *  - overall system power as measured on the main power supply rail.
+ *  - 5V power delivered to the USB and HDMI ports.
+ *
+ * The actual system power demand is calculated from the VBUS voltage and
+ * the input current (read from a shunt), averaged over 5 readings.
+ * The power budget limit is from the charge manager.
+ *
+ * The 5V power cannot be read directly. Instead, we rely on overcurrent
+ * inputs from the USB and HDMI ports to indicate that the port is in use
+ * (and drawing maximum power).
+ *
+ * There are 3 throttles that can be applied (in priority order):
+ *
+ *  - Type A BC1.2 front port restriction (3W)
+ *  - Type C PD (throttle to 1.5A if sourcing)
+ *  - Turn on PROCHOT, which immediately throttles the CPU.
+ *
+ *  The first 2 throttles affect both the system power and the 5V rails.
+ *  The third is a last resort to force an immediate CPU throttle to
+ *  reduce the overall power use.
+ *
+ *  The strategy is to determine what the state of the throttles should be,
+ *  and to then turn throttles off or on as needed to match this.
+ *
+ *  This function runs on demand, or every 2 ms when the CPU is up,
+ *  and continually monitors the power usage, applying the
+ *  throttles when necessary.
+ *
+ *  All measurements are in milliwatts.
+ */
+#define THROT_TYPE_A BIT(0)
+#define THROT_TYPE_C BIT(1)
+#define THROT_PROCHOT BIT(2)
+
+/*
+ * Power gain if front USB A ports are limited.
+ */
+#define POWER_GAIN_TYPE_A 3200
+/*
+ * Power gain if Type C port is limited.
+ */
+#define POWER_GAIN_TYPE_C 8800
+/*
+ * Power is averaged over 10 ms, with a reading every 2 ms.
+ */
+#define POWER_DELAY_MS 2
+#define POWER_READINGS (10 / POWER_DELAY_MS)
+
+static void power_monitor(void)
+{
+	static uint32_t current_state;
+	static uint32_t history[POWER_READINGS];
+	static uint8_t index;
+	int32_t delay;
+	uint32_t new_state = 0, diff;
+	int32_t headroom_5v = PWR_MAX - base_5v_power;
+
+	/*
+	 * If CPU is off or suspended, no need to throttle
+	 * or restrict power.
+	 */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF | CHIPSET_STATE_SUSPEND)) {
+		/*
+		 * Slow down monitoring, assume no throttling required.
+		 */
+		delay = 20 * MSEC;
+		/*
+		 * Clear the first entry of the power table so that
+		 * it is re-initilalised when the CPU starts.
+		 */
+		history[0] = 0;
+	} else {
+		int32_t charger_mw;
+
+		delay = POWER_DELAY_MS * MSEC;
+		/*
+		 * Get current charger limit (in mw).
+		 * If not configured yet, skip.
+		 */
+		charger_mw = charge_manager_get_power_limit_uw() / 1000;
+		if (charger_mw != 0) {
+			int32_t gap, total, max, power;
+			int i;
+
+			/*
+			 * Read power usage.
+			 */
+			power = (adc_read_channel(ADC_VBUS) *
+				 adc_read_channel(ADC_PPVAR_IMON)) /
+				1000;
+			/* Init power table */
+			if (history[0] == 0) {
+				for (i = 0; i < POWER_READINGS; i++)
+					history[i] = power;
+			}
+			/*
+			 * Update the power readings and
+			 * calculate the average and max.
+			 */
+			history[index] = power;
+			index = (index + 1) % POWER_READINGS;
+			total = 0;
+			max = history[0];
+			for (i = 0; i < POWER_READINGS; i++) {
+				total += history[i];
+				if (history[i] > max)
+					max = history[i];
+			}
+			/*
+			 * For Type-C power supplies, there is
+			 * less tolerance for exceeding the rating,
+			 * so use the max power that has been measured
+			 * over the measuring period.
+			 * For barrel-jack supplies, the rating can be
+			 * exceeded briefly, so use the average.
+			 */
+			if (charge_manager_get_supplier() == CHARGE_SUPPLIER_PD)
+				power = max;
+			else
+				power = total / POWER_READINGS;
+			/*
+			 * Calculate gap, and if negative, power
+			 * demand is exceeding configured power budget, so
+			 * throttling is required to reduce the demand.
+			 */
+			gap = charger_mw - power;
+			/*
+			 * Limiting type-A power.
+			 */
+			if (gap <= 0) {
+				new_state |= THROT_TYPE_A;
+				headroom_5v += PWR_FRONT_HIGH - PWR_FRONT_LOW;
+				if (!(current_state & THROT_TYPE_A))
+					gap += POWER_GAIN_TYPE_A;
+			}
+			/*
+			 * If the type-C port is sourcing power,
+			 * check whether it should be throttled.
+			 */
+			if (ppc_is_sourcing_vbus(0) && gap <= 0) {
+				new_state |= THROT_TYPE_C;
+				headroom_5v += PWR_C_HIGH - PWR_C_LOW;
+				if (!(current_state & THROT_TYPE_C))
+					gap += POWER_GAIN_TYPE_C;
+			}
+			/*
+			 * As a last resort, turn on PROCHOT to
+			 * throttle the CPU.
+			 */
+			if (gap <= 0)
+				new_state |= THROT_PROCHOT;
+		}
+	}
+	/*
+	 * Check the 5v power usage and if necessary,
+	 * adjust the throttles in priority order.
+	 *
+	 * Either throttle may have already been activated by
+	 * the overall power control.
+	 *
+	 * We rely on the overcurrent detection to inform us
+	 * if the port is in use.
+	 *
+	 *  - If type C not already throttled:
+	 *	* If not overcurrent, prefer to limit type C [1].
+	 *	* If in overcurrentuse:
+	 *		- limit type A first [2]
+	 *		- If necessary, limit type C [3].
+	 *  - If type A not throttled, if necessary limit it [2].
+	 */
+	if (headroom_5v < 0) {
+		/*
+		 * Check whether type C is not throttled,
+		 * and is not overcurrent.
+		 */
+		if (!((new_state & THROT_TYPE_C) || usbc_overcurrent)) {
+			/*
+			 * [1] Type C not in overcurrent, throttle it.
+			 */
+			headroom_5v += PWR_C_HIGH - PWR_C_LOW;
+			new_state |= THROT_TYPE_C;
+		}
+		/*
+		 * [2] If type A not already throttled, and power still
+		 * needed, limit type A.
+		 */
+		if (!(new_state & THROT_TYPE_A) && headroom_5v < 0) {
+			headroom_5v += PWR_FRONT_HIGH - PWR_FRONT_LOW;
+			new_state |= THROT_TYPE_A;
+		}
+		/*
+		 * [3] If still under-budget, limit type C.
+		 * No need to check if it is already throttled or not.
+		 */
+		if (headroom_5v < 0)
+			new_state |= THROT_TYPE_C;
+	}
+	/*
+	 * Turn the throttles on or off if they have changed.
+	 */
+	diff = new_state ^ current_state;
+	current_state = new_state;
+	if (diff & THROT_PROCHOT) {
+		int prochot = (new_state & THROT_PROCHOT) ? 0 : 1;
+
+		gpio_set_level(GPIO_EC_PROCHOT_ODL, prochot);
+	}
+	if (diff & THROT_TYPE_C) {
+		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C) ?
+						TYPEC_RP_1A5 :
+						TYPEC_RP_3A0;
+
+		ppc_set_vbus_source_current_limit(0, rp);
+		tcpm_select_rp_value(0, rp);
+		pd_update_contract(0);
+	}
+	if (diff & THROT_TYPE_A) {
+		int typea_bc = (new_state & THROT_TYPE_A) ? 1 : 0;
+
+		gpio_set_level(GPIO_USB_A_LOW_PWR_OD, typea_bc);
+	}
+	hook_call_deferred(&power_monitor_data, delay);
+}
diff --git a/board/ambassador/board.h b/board/ambassador/board.h
new file mode 100644
index 0000000000..bc6e94a8d5
--- /dev/null
+++ b/board/ambassador/board.h
@@ -0,0 +1,287 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Puff board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#undef CONFIG_UART_TX_BUF_SIZE
+#define CONFIG_UART_TX_BUF_SIZE 4096
+
+/* NPCX7 config */
+#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */
+#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */
+
+/* Internal SPI flash on NPCX796FC is 512 kB */
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
+#define CONFIG_SPI_FLASH_REGS
+#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
+
+/* EC Defines */
+#define CONFIG_ADC
+#define CONFIG_BOARD_HAS_RTC_RESET
+#define CONFIG_BOARD_VERSION_CBI
+#define CONFIG_DEDICATED_RECOVERY_BUTTON
+#define CONFIG_DEDICATED_RECOVERY_BUTTON_2
+#define CONFIG_BUTTONS_RUNTIME_CONFIG
+#define CONFIG_BOARD_RESET_AFTER_POWER_ON
+/* TODO: (b/143496253) re-enable CEC */
+/* #define CONFIG_CEC */
+#define CONFIG_CRC8
+#define CONFIG_CBI_EEPROM
+#define CONFIG_EMULATED_SYSRQ
+#undef CONFIG_KEYBOARD_BOOT_KEYS
+#define CONFIG_MKBP_INPUT_DEVICES
+#define CONFIG_MKBP_USE_HOST_EVENT
+#undef CONFIG_KEYBOARD_RUNTIME_KEYS
+#undef CONFIG_HIBERNATE
+#define CONFIG_HOST_INTERFACE_ESPI
+#define CONFIG_LED_COMMON
+#undef CONFIG_LID_SWITCH
+#define CONFIG_LTO
+#define CONFIG_PWM
+#define CONFIG_VBOOT_EFS2
+#define CONFIG_VBOOT_HASH
+#define CONFIG_VSTORE
+#define CONFIG_VSTORE_SLOT_COUNT 1
+#define CONFIG_SHA256
+
+/* EC Commands */
+#define CONFIG_CMD_BUTTON
+/* Include CLI command needed to support CCD testing. */
+#define CONFIG_CMD_CHARGEN
+#undef CONFIG_CMD_FASTCHARGE
+#undef CONFIG_CMD_KEYBOARD
+#define CONFIG_HOSTCMD_PD_CONTROL
+#undef CONFIG_CMD_PWR_AVG
+#define CONFIG_CMD_PPC_DUMP
+#define CONFIG_CMD_TCPC_DUMP
+#ifdef SECTION_IS_RO
+/* Reduce RO size by removing less-relevant commands. */
+#undef CONFIG_CMD_APTHROTTLE
+#undef CONFIG_CMD_CHARGEN
+#undef CONFIG_CMD_HCDEBUG
+#undef CONFIG_CMD_MMAPINFO
+#endif
+
+#undef CONFIG_CONSOLE_CMDHELP
+
+/* Don't generate host command debug by default */
+#undef CONFIG_HOSTCMD_DEBUG_MODE
+#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
+
+/* Enable AP Reset command for TPM with old firmware version to detect it. */
+#define CONFIG_CMD_AP_RESET_LOG
+#define CONFIG_HOSTCMD_AP_RESET
+
+/* Chipset config */
+#define CONFIG_CHIPSET_COMETLAKE_DISCRETE
+/* check */
+#define CONFIG_CHIPSET_CAN_THROTTLE
+#define CONFIG_CHIPSET_RESET_HOOK
+#define CONFIG_CPU_PROCHOT_ACTIVE_LOW
+
+/* Dedicated barreljack charger port */
+#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT
+#define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1
+#define DEDICATED_CHARGE_PORT 1
+
+#define CONFIG_POWER_BUTTON
+#define CONFIG_POWER_BUTTON_IGNORE_LID
+#define CONFIG_POWER_BUTTON_X86
+/* Check: */
+#define CONFIG_POWER_BUTTON_INIT_IDLE
+#define CONFIG_POWER_COMMON
+#define CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD 30
+#define CONFIG_DELAY_DSW_PWROK_TO_PWRBTN
+#define CONFIG_POWER_PP5000_CONTROL
+#define CONFIG_POWER_S0IX
+#define CONFIG_POWER_SLEEP_FAILURE_DETECTION
+#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
+#define CONFIG_INA3221
+
+/* b/143501304 */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 4000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 2000 /* us */
+#undef CONFIG_USBC_VCONN_SWAP_DELAY_US
+#define CONFIG_USBC_VCONN_SWAP_DELAY_US 8000 /* us */
+
+#define PD_OPERATING_POWER_MW CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
+#define PD_MAX_POWER_MW 100000
+#define PD_MAX_CURRENT_MA 5000
+#define PD_MAX_VOLTAGE_MV 20000
+
+/* Fan and temp. */
+#define CONFIG_FANS 1
+#undef CONFIG_FAN_INIT_SPEED
+#define CONFIG_FAN_INIT_SPEED 0
+#define CONFIG_FAN_RPM_CUSTOM
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_TEMP_SENSOR_POWER
+#define CONFIG_THERMISTOR
+#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
+#define CONFIG_THROTTLE_AP
+
+/* Charger */
+#define CONFIG_CHARGE_MANAGER
+/* Less than this much blocks AP power-on. */
+#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 30000
+#undef CONFIG_CHARGE_MANAGER_SAFE_MODE
+
+/* USB type C */
+#define CONFIG_USB_PD_TCPMV2 /* Use TCPMv2 */
+#define CONFIG_USB_PD_REV30 /* Enable PD 3.0 functionality */
+#define CONFIG_USB_PD_DECODE_SOP
+#undef CONFIG_USB_CHARGER
+#define CONFIG_USB_POWER_DELIVERY
+#define CONFIG_USB_PID 0x5040
+#define CONFIG_USB_PD_ALT_MODE
+#define CONFIG_USB_PD_ALT_MODE_DFP
+#define CONFIG_USB_PD_DISCHARGE_PPC
+#define CONFIG_USB_PD_DUAL_ROLE
+#define CONFIG_USB_PD_LOGGING
+#define CONFIG_USB_PD_PORT_MAX_COUNT 1
+#define CONFIG_USB_PD_VBUS_DETECT_PPC
+#define CONFIG_USBC_PPC_SN5S330
+#define CONFIG_USBC_PPC_DEDICATED_INT
+#define CONFIG_USB_PD_TCPM_MUX
+#define CONFIG_USB_PD_TCPM_TCPCI
+#define CONFIG_USB_PD_TCPM_ANX7447
+#define CONFIG_USB_PD_TRY_SRC
+#define CONFIG_USB_DRP_ACC_TRYSRC
+#define CONFIG_USBC_SS_MUX
+#define CONFIG_USBC_SS_MUX_DFP_ONLY
+#define CONFIG_USBC_VCONN
+#define CONFIG_USBC_VCONN_SWAP
+
+#define USB_PD_PORT_TCPC_0 0
+#define BOARD_TCPC_C0_RESET_HOLD_DELAY ANX74XX_RESET_HOLD_MS
+#define BOARD_TCPC_C0_RESET_POST_DELAY ANX74XX_RESET_HOLD_MS
+
+/* USB Type A Features */
+#define CONFIG_USB_PORT_POWER_DUMB
+/* There are five ports, but power enable is ganged across all of them. */
+#define USB_PORT_COUNT 1
+
+/* I2C Bus Configuration */
+#define CONFIG_I2C
+#define CONFIG_I2C_CONTROLLER
+#define I2C_PORT_INA NPCX_I2C_PORT0_0
+#define I2C_PORT_PPC0 NPCX_I2C_PORT1_0
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT3_0
+#define I2C_PORT_POWER NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+
+#define PP5000_PGOOD_POWER_SIGNAL_MASK POWER_SIGNAL_MASK(PP5000_A_PGOOD)
+
+/* Include math_util for bitmask_uint64 used in pd_timers */
+#define CONFIG_MATH_UTIL
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum charge_port {
+	CHARGE_PORT_TYPEC0,
+	CHARGE_PORT_BARRELJACK,
+};
+
+enum adc_channel {
+	ADC_SNS_PP3300, /* ADC2 */
+	ADC_SNS_PP1050, /* ADC7 */
+	ADC_VBUS, /* ADC4 */
+	ADC_PPVAR_IMON, /* ADC9 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	/* Number of ADC channels */
+	ADC_CH_COUNT
+};
+
+enum pwm_channel {
+	PWM_CH_FAN,
+	PWM_CH_LED_RED,
+	PWM_CH_LED_WHITE,
+	/* Number of PWM channels */
+	PWM_CH_COUNT
+};
+
+enum fan_channel {
+	FAN_CH_0,
+	/* Number of FAN channels */
+	FAN_CH_COUNT
+};
+
+enum mft_channel {
+	MFT_CH_0 = 0,
+	/* Number of MFT channels */
+	MFT_CH_COUNT,
+};
+
+enum temp_sensor_id { TEMP_SENSOR_CORE, TEMP_SENSOR_COUNT };
+
+/* Board specific handlers */
+void board_reset_pd_mcu(void);
+void board_set_tcpc_power_mode(int port, int mode);
+void led_alert(int enable);
+void show_critical_error(void);
+
+/*
+ * firmware config fields
+ */
+/*
+ * Barrel-jack power (4 bits).
+ */
+#define EC_CFG_BJ_POWER_L 0
+#define EC_CFG_BJ_POWER_H 3
+#define EC_CFG_BJ_POWER_MASK GENMASK(EC_CFG_BJ_POWER_H, EC_CFG_BJ_POWER_L)
+/*
+ * USB Connector 4 not present (1 bit).
+ */
+#define EC_CFG_NO_USB4_L 4
+#define EC_CFG_NO_USB4_H 4
+#define EC_CFG_NO_USB4_MASK GENMASK(EC_CFG_NO_USB4_H, EC_CFG_NO_USB4_L)
+/*
+ * Thermal solution config (3 bits).
+ */
+#define EC_CFG_THERMAL_L 5
+#define EC_CFG_THERMAL_H 7
+#define EC_CFG_THERMAL_MASK GENMASK(EC_CFG_THERMAL_H, EC_CFG_THERMAL_L)
+
+unsigned int ec_config_get_bj_power(void);
+int ec_config_get_usb4_present(void);
+unsigned int ec_config_get_thermal_solution(void);
+
+#endif /* !__ASSEMBLER__ */
+
+/* Pin renaming */
+#define GPIO_WP_L GPIO_EC_WP_ODL
+#define GPIO_PP5000_A_PG_OD GPIO_PG_PP5000_A_OD
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
+#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_ODL
+#define GPIO_RECOVERY_L_2 GPIO_H1_EC_RECOVERY_BTN_ODL
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_EN_ROA_RAILS
+#define GPIO_AC_PRESENT GPIO_BJ_ADP_PRESENT_L
+
+/*
+ * There is no RSMRST input, so alias it to the output. This short-circuits
+ * common_intel_x86_handle_rsmrst.
+ */
+#define GPIO_PG_EC_RSMRST_ODL GPIO_PCH_RSMRST_L
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/ambassador/build.mk b/board/ambassador/build.mk
new file mode 100644
index 0000000000..f9096c64ff
--- /dev/null
+++ b/board/ambassador/build.mk
@@ -0,0 +1,15 @@
+# -*- makefile -*-
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx7
+CHIP_VARIANT:=npcx7m6fc
+
+board-y=board.o
+board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
+board-y+=led.o
diff --git a/board/ambassador/ec.tasklist b/board/ambassador/ec.tasklist
new file mode 100644
index 0000000000..42b9542d96
--- /dev/null
+++ b/board/ambassador/ec.tasklist
@@ -0,0 +1,17 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 2048) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE)
diff --git a/board/ambassador/gpio.inc b/board/ambassador/gpio.inc
new file mode 100644
index 0000000000..46b6118ce2
--- /dev/null
+++ b/board/ambassador/gpio.inc
@@ -0,0 +1,169 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Pin names follow the schematic, and are aliased to other names if necessary.
+ * Note: Those with interrupt handlers must be declared first. */
+
+/* Latency on this interrupt is extremely critical, so it comes first to ensure
+ * it gets placed first in gpio_wui_table so gpio_interrupt() needs to do
+ * minimal scanning. */
+GPIO_INT(CPU_C10_GATE_L,       PIN(6, 7), GPIO_INT_BOTH, c10_gate_interrupt)
+
+/* Wake Source interrupts */
+GPIO_INT(EC_WP_ODL,            PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(H1_EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
+
+/* Power sequencing interrupts */
+GPIO_INT(PG_PP5000_A_OD,       PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_PP1800_A_OD,       PIN(3, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_VPRIM_CORE_A_OD,   PIN(2, 3), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_PP1050_A_OD,       PIN(2, 2), GPIO_INT_BOTH, power_signal_interrupt)
+/* EC output, but also interrupt so this can be polled as a power signal */
+GPIO_INT(EC_PCH_RSMRST_L,      PIN(A, 6), GPIO_OUTPUT | GPIO_INT_F_RISING | GPIO_INT_F_FALLING, power_signal_interrupt)
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
+GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
+#endif
+GPIO_INT(PG_PP2500_DRAM_U_OD,  PIN(2, 0), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_PP1200_U_OD,       PIN(2, 1), GPIO_INT_BOTH, power_signal_interrupt)
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, slp_s3_interrupt)
+#endif
+GPIO_INT(PG_PP950_VCCIO_OD,    PIN(1, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(IMVP8_VRRDY_OD,       PIN(1, 6), GPIO_INT_BOTH, power_signal_interrupt)
+
+/* Other interrupts */
+GPIO_INT(USB_C0_TCPPC_INT_ODL, PIN(E, 0), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C0_TCPC_INT_ODL,  PIN(6, 2), GPIO_INT_FALLING, tcpc_alert_event)
+/*
+ * Directly connected recovery button (not available on some boards).
+ */
+GPIO_INT(EC_RECOVERY_BTN_ODL,  PIN(F, 1), GPIO_INT_BOTH, button_interrupt)
+/*
+ * Recovery button input from H1.
+ */
+GPIO_INT(H1_EC_RECOVERY_BTN_ODL, PIN(2, 4), GPIO_INT_BOTH, button_interrupt)
+GPIO_INT(BJ_ADP_PRESENT_L,     PIN(8, 2), GPIO_INT_BOTH | GPIO_PULL_UP, adp_connect_interrupt)
+
+/* Port power control interrupts */
+GPIO_INT(HDMI_CONN0_OC_ODL,    PIN(0, 7), GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(HDMI_CONN1_OC_ODL,    PIN(0, 6), GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(USB_A0_OC_ODL,        PIN(E, 4), GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(USB_A1_OC_ODL,        PIN(A, 2), GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(USB_A2_OC_ODL,        PIN(F, 5), GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(USB_A3_OC_ODL,        PIN(0, 3), GPIO_INT_BOTH, port_ocp_interrupt)
+/* May be reconfigured as input */
+GPIO_INT(USB_A4_OC_ODL,        PIN(B, 0), GPIO_OUT_LOW | GPIO_INT_BOTH, port_ocp_interrupt)
+
+/* PCH/CPU signals */
+GPIO(EC_PCH_PWROK,             PIN(0, 5), GPIO_OUT_LOW)
+GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
+GPIO(EC_PCH_PWR_BTN_ODL,       PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_IN_OD,         PIN(3, 4), GPIO_INPUT)
+GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
+GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
+
+/* Power control outputs */
+GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
+GPIO(EN_PP3300_INA_H1_EC_ODL,  PIN(5, 7), GPIO_ODR_HIGH)
+GPIO(EN_PP1800_A,              PIN(1, 5), GPIO_OUT_LOW)
+GPIO(VCCST_PG_OD,              PIN(1, 4), GPIO_ODR_LOW)
+GPIO(EN_S0_RAILS,              PIN(1, 1), GPIO_OUT_LOW)
+GPIO(EN_ROA_RAILS,             PIN(A, 3), GPIO_OUT_LOW)
+GPIO(EN_PP950_VCCIO,           PIN(1, 0), GPIO_OUT_LOW)
+GPIO(EC_IMVP8_PE,              PIN(A, 7), GPIO_OUT_LOW)
+GPIO(EN_IMVP8_VR,              PIN(F, 4), GPIO_OUT_LOW)
+
+/* Barreljack */
+GPIO(EN_PPVAR_BJ_ADP_L,        PIN(0, 4), GPIO_OUT_LOW)
+
+/* USB type A */
+GPIO(EN_PP5000_USB_VBUS,       PIN(8, 3), GPIO_OUT_LOW)
+GPIO(USB_A_LOW_PWR_OD,         PIN(9, 4), GPIO_ODR_LOW)
+GPIO(USB_A2_STATUS_L,          PIN(6, 1), GPIO_INPUT)
+GPIO(USB_A3_STATUS_L,          PIN(C, 7), GPIO_INPUT)
+
+/* USB type C */
+GPIO(USB_C0_TCPC_RST,          PIN(9, 7), GPIO_OUT_LOW)
+
+/* Misc. */
+GPIO(M2_SSD_PLN,               PIN(A, 0), GPIO_INPUT)
+GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
+GPIO(CCD_MODE_ODL,             PIN(E, 5), GPIO_ODR_HIGH)
+GPIO(EN_PP_MST_OD,             PIN(9, 6), GPIO_ODR_HIGH)
+GPIO(PACKET_MODE_EN,           PIN(7, 5), GPIO_OUT_LOW)
+
+/* HDMI/CEC */
+GPIO(EN_PP5000_HDMI,           PIN(5, 0), GPIO_OUT_LOW)
+GPIO(HDMI_CONN0_CEC_OUT,       PIN(B, 1), GPIO_ODR_HIGH)
+GPIO(HDMI_CONN0_CEC_IN,        PIN(4, 0), GPIO_INPUT)
+GPIO(HDMI_CONN1_CEC_OUT,       PIN(9, 5), GPIO_ODR_HIGH)
+GPIO(HDMI_CONN1_CEC_IN,        PIN(D, 3), GPIO_INPUT)
+
+/* I2C pins - Alternate function below configures I2C module on these pins */
+GPIO(I2C0_SCL,                 PIN(B, 5), GPIO_INPUT)           /* EC_I2C_INA_SCL */
+GPIO(I2C0_SDA,                 PIN(B, 4), GPIO_INPUT)           /* EC_I2C_INA_SDA */
+GPIO(I2C1_SCL,                 PIN(9, 0), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPPC_SCL */
+GPIO(I2C1_SDA,                 PIN(8, 7), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPPC_SDA */
+GPIO(I2C3_SCL,                 PIN(D, 1), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPC_SCL */
+GPIO(I2C3_SDA,                 PIN(D, 0), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPC_SDA */
+GPIO(I2C5_SCL,                 PIN(3, 3), GPIO_INPUT)           /* EC_I2C_IMVP8_SCL */
+GPIO(I2C5_SDA,                 PIN(3, 6), GPIO_INPUT)           /* EC_I2C_IMVP8_SDA */
+GPIO(I2C7_SCL,                 PIN(B, 3), GPIO_INPUT)           /* EC_I2C_EEPROM_SCL */
+GPIO(I2C7_SDA,                 PIN(B, 2), GPIO_INPUT)           /* EC_I2C_EEPROM_SDA */
+
+/* Alternate functions GPIO definitions */
+ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, 0)                  /* I2C0 */
+ALTERNATE(PIN_MASK(9, 0x01), 0, MODULE_I2C, 0)                  /* I2C1 SCL */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)                  /* I2C1 SDA */
+ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)                  /* I2C3 */
+ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)                  /* I2C5 */
+ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, 0)                  /* I2C7 */
+
+/* PWM */
+ALTERNATE(PIN_MASK(C, 0x08), 0, MODULE_PWM, 0)                  /* PWM0 - Red Led */
+ALTERNATE(PIN_MASK(C, 0x10), 0, MODULE_PWM, 0)                  /* PWM2 - White Led */
+ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)                  /* PWM5 - Fan 1 */
+ALTERNATE(PIN_MASK(7, 0x08), 0, MODULE_PWM, 0)                  /* TA2 - Fan Tachometer */
+
+/* ADC */
+ALTERNATE(PIN_MASK(4, 0x2A), 0, MODULE_ADC, 0)                  /* ADC0, ADC2, ADC4 */
+ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0)                  /* ADC7 */
+ALTERNATE(PIN_MASK(F, 0x01), 0, MODULE_ADC, 0)                  /* ADC9 */
+
+/* UART */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)                 /* UART from EC to Servo */
+
+/* Unused pins */
+UNUSED(PIN(1, 3))						/* EC_GP_SEL1_ODL */
+UNUSED(PIN(F, 2))						/* EC_I2C_RFU_SDA */
+UNUSED(PIN(F, 3))						/* EC_I2C_RFU_SCL */
+UNUSED(PIN(C, 0))						/* FAN_PWM_2 */
+UNUSED(PIN(8, 0))						/* LED_BLUE_L */
+UNUSED(PIN(4, 4))						/* ADC1/TEMP_SENSOR_2 */
+UNUSED(PIN(4, 2))						/* ADC3/TEMP_SENSOR_3 */
+UNUSED(PIN(C, 2))						/* A12 NC */
+UNUSED(PIN(9, 2))						/* K8  NC */
+UNUSED(PIN(9, 1))						/* L8  NC */
+UNUSED(PIN(1, 2))						/* C6  NC */
+UNUSED(PIN(6, 6))						/* H4  NC */
+UNUSED(PIN(8, 1))						/* L6  NC */
+UNUSED(PIN(C, 6))						/* B11 NC */
+UNUSED(PIN(E, 2))						/* B8  NC */
+UNUSED(PIN(8, 5))						/* L7  NC */
+UNUSED(PIN(0, 0))						/* D11 NC */
+UNUSED(PIN(3, 2))						/* E5  NC */
+UNUSED(PIN(D, 6))						/* F6  NC */
+UNUSED(PIN(3, 5))						/* F5  NC */
+UNUSED(PIN(5, 6))						/* M2  NC */
+UNUSED(PIN(D, 2))						/* C11 NC */
+UNUSED(PIN(8, 6))						/* J8  NC */
+UNUSED(PIN(9, 3))						/* M11 NC */
+UNUSED(PIN(7, 2))						/* H6  NC */
diff --git a/board/ambassador/led.c b/board/ambassador/led.c
new file mode 100644
index 0000000000..3baf867580
--- /dev/null
+++ b/board/ambassador/led.c
@@ -0,0 +1,267 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power LED control for Puff.
+ * Solid green - active power
+ * Green flashing - suspended
+ * Red flashing - alert
+ * Solid red - critical
+ */
+
+#include "chipset.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "led_common.h"
+#include "pwm.h"
+#include "timer.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
+
+/*
+ * Due to the CSME-Lite processing, upon startup the CPU transitions through
+ * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so
+ * delay turning off the LED during suspend/shutdown.
+ */
+#define LED_CPU_DELAY_MS (2000 * MSEC)
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED };
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+enum led_color {
+	LED_OFF = 0,
+	LED_RED,
+	LED_WHITE,
+	LED_AMBER,
+
+	/* Number of colors, not a color itself */
+	LED_COLOR_COUNT
+};
+
+static int set_color_power(enum led_color color, int duty)
+{
+	int white = 0;
+	int red = 0;
+
+	if (duty < 0 || 100 < duty)
+		return EC_ERROR_UNKNOWN;
+
+	switch (color) {
+	case LED_OFF:
+		break;
+	case LED_WHITE:
+		white = 1;
+		break;
+	case LED_RED:
+		red = 1;
+		break;
+	case LED_AMBER:
+		red = 1;
+		white = 1;
+		break;
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+
+	if (red)
+		pwm_set_duty(PWM_CH_LED_RED, duty);
+	else
+		pwm_set_duty(PWM_CH_LED_RED, 0);
+
+	if (white)
+		pwm_set_duty(PWM_CH_LED_WHITE, duty);
+	else
+		pwm_set_duty(PWM_CH_LED_WHITE, 0);
+
+	return EC_SUCCESS;
+}
+
+static int set_color(enum ec_led_id id, enum led_color color, int duty)
+{
+	switch (id) {
+	case EC_LED_ID_POWER_LED:
+		return set_color_power(color, duty);
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+}
+
+#define LED_PULSE_US (2 * SECOND)
+/* 40 msec for nice and smooth transition. */
+#define LED_PULSE_TICK_US (40 * MSEC)
+
+/* When pulsing is enabled, brightness is incremented by <duty_inc> every
+ * <interval> usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented
+ * likewise in LED_PULSE_US usec.
+ */
+static struct {
+	uint32_t interval;
+	int duty_inc;
+	enum led_color color;
+	int duty;
+} led_pulse;
+
+#define CONFIG_TICK(interval, color) \
+	config_tick((interval), 100 / (LED_PULSE_US / (interval)), (color))
+
+static void config_tick(uint32_t interval, int duty_inc, enum led_color color)
+{
+	led_pulse.interval = interval;
+	led_pulse.duty_inc = duty_inc;
+	led_pulse.color = color;
+	led_pulse.duty = 0;
+}
+
+static void pulse_power_led(enum led_color color)
+{
+	set_color(EC_LED_ID_POWER_LED, color, led_pulse.duty);
+	if (led_pulse.duty + led_pulse.duty_inc > 100)
+		led_pulse.duty_inc = led_pulse.duty_inc * -1;
+	else if (led_pulse.duty + led_pulse.duty_inc < 0)
+		led_pulse.duty_inc = led_pulse.duty_inc * -1;
+	led_pulse.duty += led_pulse.duty_inc;
+}
+
+static void led_tick(void);
+DECLARE_DEFERRED(led_tick);
+static void led_tick(void)
+{
+	uint32_t elapsed;
+	uint32_t next = 0;
+	uint32_t start = get_time().le.lo;
+
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		pulse_power_led(led_pulse.color);
+	elapsed = get_time().le.lo - start;
+	next = led_pulse.interval > elapsed ? led_pulse.interval - elapsed : 0;
+	hook_call_deferred(&led_tick_data, next);
+}
+
+static void led_suspend(void)
+{
+	CONFIG_TICK(LED_PULSE_TICK_US, LED_WHITE);
+	led_tick();
+}
+DECLARE_DEFERRED(led_suspend);
+
+static void led_shutdown(void)
+{
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_OFF, 0);
+}
+DECLARE_DEFERRED(led_shutdown);
+
+static void led_shutdown_hook(void)
+{
+	hook_call_deferred(&led_tick_data, -1);
+	hook_call_deferred(&led_suspend_data, -1);
+	hook_call_deferred(&led_shutdown_data, LED_CPU_DELAY_MS);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, led_shutdown_hook, HOOK_PRIO_DEFAULT);
+
+static void led_suspend_hook(void)
+{
+	hook_call_deferred(&led_shutdown_data, -1);
+	hook_call_deferred(&led_suspend_data, LED_CPU_DELAY_MS);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, led_suspend_hook, HOOK_PRIO_DEFAULT);
+
+static void led_resume(void)
+{
+	/* Assume there is no race condition with led_tick, which also
+	 * runs in hook_task.
+	 */
+	hook_call_deferred(&led_tick_data, -1);
+	/*
+	 * Avoid invoking the suspend/shutdown delayed hooks.
+	 */
+	hook_call_deferred(&led_suspend_data, -1);
+	hook_call_deferred(&led_shutdown_data, -1);
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_WHITE, 100);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, led_resume, HOOK_PRIO_DEFAULT);
+
+static void led_init(void)
+{
+	pwm_enable(PWM_CH_LED_RED, 1);
+	pwm_enable(PWM_CH_LED_WHITE, 1);
+}
+DECLARE_HOOK(HOOK_INIT, led_init, HOOK_PRIO_INIT_PWM + 1);
+
+void led_alert(int enable)
+{
+	if (enable) {
+		/* Overwrite the current signal */
+		config_tick(1 * SECOND, 100, LED_RED);
+		led_tick();
+	} else {
+		/* Restore the previous signal */
+		if (chipset_in_state(CHIPSET_STATE_ON))
+			led_resume();
+		else if (chipset_in_state(CHIPSET_STATE_SUSPEND))
+			led_suspend_hook();
+		else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+			led_shutdown_hook();
+	}
+}
+
+void show_critical_error(void)
+{
+	hook_call_deferred(&led_tick_data, -1);
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_RED, 100);
+}
+
+static int command_led(int argc, const char **argv)
+{
+	enum ec_led_id id = EC_LED_ID_POWER_LED;
+
+	if (argc < 2)
+		return EC_ERROR_PARAM_COUNT;
+
+	if (!strcasecmp(argv[1], "debug")) {
+		led_auto_control(id, !led_auto_control_is_enabled(id));
+		ccprintf("o%s\n", led_auto_control_is_enabled(id) ? "ff" : "n");
+	} else if (!strcasecmp(argv[1], "off")) {
+		set_color(id, LED_OFF, 0);
+	} else if (!strcasecmp(argv[1], "red")) {
+		set_color(id, LED_RED, 100);
+	} else if (!strcasecmp(argv[1], "white")) {
+		set_color(id, LED_WHITE, 100);
+	} else if (!strcasecmp(argv[1], "amber")) {
+		set_color(id, LED_AMBER, 100);
+	} else if (!strcasecmp(argv[1], "alert")) {
+		led_alert(1);
+	} else if (!strcasecmp(argv[1], "crit")) {
+		show_critical_error();
+	} else {
+		return EC_ERROR_PARAM1;
+	}
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(led, command_led,
+			"[debug|red|white|amber|off|alert|crit]",
+			"Turn on/off LED.");
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	brightness_range[EC_LED_COLOR_RED] = 100;
+	brightness_range[EC_LED_COLOR_WHITE] = 100;
+	brightness_range[EC_LED_COLOR_AMBER] = 100;
+}
+
+int led_set_brightness(enum ec_led_id id, const uint8_t *brightness)
+{
+	if (brightness[EC_LED_COLOR_RED])
+		return set_color(id, LED_RED, brightness[EC_LED_COLOR_RED]);
+	else if (brightness[EC_LED_COLOR_WHITE])
+		return set_color(id, LED_WHITE, brightness[EC_LED_COLOR_WHITE]);
+	else if (brightness[EC_LED_COLOR_AMBER])
+		return set_color(id, LED_AMBER, brightness[EC_LED_COLOR_AMBER]);
+	else
+		return set_color(id, LED_OFF, 0);
+}
diff --git a/board/ambassador/usb_pd_policy.c b/board/ambassador/usb_pd_policy.c
new file mode 100644
index 0000000000..fbb4edf23e
--- /dev/null
+++ b/board/ambassador/usb_pd_policy.c
@@ -0,0 +1,83 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Shared USB-C policy for Puff boards */
+
+#include "charge_manager.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "system.h"
+#include "tcpm/tcpci.h"
+#include "tcpm/tcpm.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+int pd_check_vconn_swap(int port)
+{
+	/* Only allow vconn swap if pp5000_A rail is enabled */
+	return gpio_get_level(GPIO_EN_PP5000_A);
+}
+
+void pd_power_supply_reset(int port)
+{
+	int prev_en;
+
+	prev_en = ppc_is_sourcing_vbus(port);
+
+	/* Disable VBUS. */
+	ppc_vbus_source_enable(port, 0);
+
+	/* Enable discharge if we were previously sourcing 5V */
+	if (prev_en)
+		pd_set_vbus_discharge(port, 1);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	/* Disable charging. */
+	rv = ppc_vbus_sink_enable(port, 0);
+	if (rv)
+		return rv;
+
+	pd_set_vbus_discharge(port, 0);
+
+	/* Provide Vbus. */
+	rv = ppc_vbus_source_enable(port, 1);
+	if (rv)
+		return rv;
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+#ifdef CONFIG_USB_PD_VBUS_DETECT_PPC
+int pd_snk_is_vbus_provided(int port)
+{
+	return ppc_is_vbus_present(port);
+}
+#endif
+
+int board_vbus_source_enabled(int port)
+{
+	/* Ignore non-PD ports (the barrel jack). */
+	if (port >= CONFIG_USB_PD_PORT_MAX_COUNT)
+		return 0;
+	return ppc_is_sourcing_vbus(port);
+}
diff --git a/board/ambassador/vif_override.xml b/board/ambassador/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/ambassador/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/ampton/battery.c b/board/ampton/battery.c
index 481216cf61..18bf4e591a 100644
--- a/board/ampton/battery.c
+++ b/board/ampton/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -116,30 +116,35 @@ const struct board_batt_params board_battery_info[] = {
 			.discharging_max_c = 60,
 		},
 	},
+	[BATTERY_C204_SECOND] = {
+		.fuel_gauge = {
+			.manuf_name = "AS3FXXd3KB",
+			.device_name = "C214-43",
+			.ship_mode = {
+				.reg_addr = 0x0,
+				.reg_data = { 0x10, 0x10 },
+			},
+			.fet = {
+				.reg_addr = 0x99,
+				.reg_mask = 0x000C,
+				.disconnect_val = 0x000C,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0004
+			},
+		},
+		.batt_info = {
+			.voltage_max = 13200,
+			.voltage_normal = 11550,
+			.voltage_min = 9000,
+			.precharge_current = 256,
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.discharging_min_c = -20,
+			.discharging_max_c = 60,
+		},
+	},
 };
 BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
 
 const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_C214;
-
-/* Lower our input voltage to 5V in S5/G3 when battery is full. */
-static void reduce_input_voltage_when_full(void)
-{
-	int max_pd_voltage_mv;
-	int port;
-
-	if (charge_get_percent() == 100 &&
-	    chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF))
-		max_pd_voltage_mv = 5000;
-	else
-		max_pd_voltage_mv = PD_MAX_VOLTAGE_MV;
-	if (pd_get_max_voltage() != max_pd_voltage_mv) {
-		for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++)
-			pd_set_external_voltage_limit(port, max_pd_voltage_mv);
-	}
-}
-DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, reduce_input_voltage_when_full,
-	     HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, reduce_input_voltage_when_full,
-	     HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, reduce_input_voltage_when_full,
-	     HOOK_PRIO_DEFAULT);
diff --git a/board/ampton/board.c b/board/ampton/board.c
index 3e5ab18510..ccd82d4e71 100644
--- a/board/ampton/board.c
+++ b/board/ampton/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,6 @@
 /* Ampton/Apel board-specific configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "button.h"
 #include "charge_state.h"
 #include "common.h"
@@ -14,6 +13,8 @@
 #include "driver/accel_bma2x2.h"
 #include "driver/accel_kionix.h"
 #include "driver/accelgyro_bmi_common.h"
+#include "driver/accelgyro_icm42607.h"
+#include "driver/accelgyro_icm_common.h"
 #include "driver/ppc/sn5s330.h"
 #include "driver/sync.h"
 #include "driver/tcpm/it83xx_pd.h"
@@ -33,9 +34,9 @@
 #include "switch.h"
 #include "system.h"
 #include "tablet_mode.h"
-#include "tcpci.h"
+#include "tcpm/tcpci.h"
 #include "temp_sensor.h"
-#include "thermistor.h"
+#include "temp_sensor/thermistor.h"
 #include "uart.h"
 #include "usb_mux.h"
 #include "usbc_ppc.h"
@@ -59,13 +60,14 @@ int ppc_get_alert_status(int port)
 		return gpio_get_level(GPIO_USB_C1_PD_INT_ODL) == 0;
 }
 
-#include "gpio_list.h" /* Must come after other header files. */
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
 
 /******************************************************************************/
 /* USB-C MUX Configuration */
 
-#define USB_PD_PORT_ITE_0      0
-#define USB_PD_PORT_ITE_1      1
+#define USB_PD_PORT_ITE_0 0
+#define USB_PD_PORT_ITE_1 1
 
 static int tune_mux(const struct usb_mux *me);
 
@@ -74,9 +76,9 @@ const struct usb_mux ampton_usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		/* Use PS8751 as mux only */
 		.usb_port = USB_PD_PORT_ITE_0,
 		.i2c_port = I2C_PORT_USBC0,
-		.i2c_addr_flags = PS8751_I2C_ADDR1_FLAGS,
+		.i2c_addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
 		.flags = USB_MUX_FLAG_NOT_TCPC,
-		.driver = &tcpci_tcpm_usb_mux_driver,
+		.driver = &ps8xxx_usb_mux_driver,
 		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
 		.board_init = &tune_mux,
 	},
@@ -84,9 +86,9 @@ const struct usb_mux ampton_usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		/* Use PS8751 as mux only */
 		.usb_port = USB_PD_PORT_ITE_1,
 		.i2c_port = I2C_PORT_USBC1,
-		.i2c_addr_flags = PS8751_I2C_ADDR1_FLAGS,
+		.i2c_addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
 		.flags = USB_MUX_FLAG_NOT_TCPC,
-		.driver = &tcpci_tcpm_usb_mux_driver,
+		.driver = &ps8xxx_usb_mux_driver,
 		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
 		.board_init = &tune_mux,
 	}
@@ -98,9 +100,10 @@ const struct usb_mux ampton_usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 static int tune_mux(const struct usb_mux *me)
 {
 	/* Auto EQ disabled, compensate for channel lost up to 3.6dB */
-	mux_write(me, PS8XXX_REG_MUX_DP_EQ_CONFIGURATION, 0x98);
+	RETURN_ERROR(mux_write(me, PS8XXX_REG_MUX_DP_EQ_CONFIGURATION, 0x98));
 	/* DP output swing adjustment +15% */
-	mux_write(me, PS8XXX_REG_MUX_DP_OUTPUT_CONFIGURATION, 0xc0);
+	RETURN_ERROR(
+		mux_write(me, PS8XXX_REG_MUX_DP_OUTPUT_CONFIGURATION, 0xc0));
 
 	return EC_SUCCESS;
 }
@@ -108,44 +111,44 @@ static int tune_mux(const struct usb_mux *me)
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* Vbus C0 sensing (10x voltage divider). PPVAR_USB_C0_VBUS */
-	[ADC_VBUS_C0] = {.name = "VBUS_C0",
-			 .factor_mul = 10 * ADC_MAX_MVOLT,
-			 .factor_div = ADC_READ_MAX + 1,
-			 .shift = 0,
-			 .channel = CHIP_ADC_CH13},
+	[ADC_VBUS_C0] = { .name = "VBUS_C0",
+			  .factor_mul = 10 * ADC_MAX_MVOLT,
+			  .factor_div = ADC_READ_MAX + 1,
+			  .shift = 0,
+			  .channel = CHIP_ADC_CH13 },
 	/* Vbus C1 sensing (10x voltage divider). SUB_EC_ADC */
-	[ADC_VBUS_C1] = {.name = "VBUS_C1",
-			 .factor_mul = 10 * ADC_MAX_MVOLT,
-			 .factor_div = ADC_READ_MAX + 1,
-			 .shift = 0,
-			 .channel = CHIP_ADC_CH14},
+	[ADC_VBUS_C1] = { .name = "VBUS_C1",
+			  .factor_mul = 10 * ADC_MAX_MVOLT,
+			  .factor_div = ADC_READ_MAX + 1,
+			  .shift = 0,
+			  .channel = CHIP_ADC_CH14 },
 	/* Convert to raw mV for thermistor table lookup */
-	[ADC_TEMP_SENSOR_AMB] = {.name = "TEMP_AMB",
-			 .factor_mul = ADC_MAX_MVOLT,
-			 .factor_div = ADC_READ_MAX + 1,
-			 .shift = 0,
-			 .channel = CHIP_ADC_CH3},
+	[ADC_TEMP_SENSOR_AMB] = { .name = "TEMP_AMB",
+				  .factor_mul = ADC_MAX_MVOLT,
+				  .factor_div = ADC_READ_MAX + 1,
+				  .shift = 0,
+				  .channel = CHIP_ADC_CH3 },
 	/* Convert to raw mV for thermistor table lookup */
-	[ADC_TEMP_SENSOR_CHARGER] = {.name = "TEMP_CHARGER",
-			 .factor_mul = ADC_MAX_MVOLT,
-			 .factor_div = ADC_READ_MAX + 1,
-			 .shift = 0,
-			 .channel = CHIP_ADC_CH5},
+	[ADC_TEMP_SENSOR_CHARGER] = { .name = "TEMP_CHARGER",
+				      .factor_mul = ADC_MAX_MVOLT,
+				      .factor_div = ADC_READ_MAX + 1,
+				      .shift = 0,
+				      .channel = CHIP_ADC_CH5 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
+	[TEMP_SENSOR_BATTERY] = { .name = "Battery",
+				  .type = TEMP_SENSOR_TYPE_BATTERY,
+				  .read = charge_get_battery_temp },
+	[TEMP_SENSOR_AMBIENT] = { .name = "Ambient",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_51k1_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_AMB },
+	[TEMP_SENSOR_CHARGER] = { .name = "Charger",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_13k7_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_CHARGER },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -154,27 +157,29 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
-const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+				      { FLOAT_TO_FP(1), 0, 0 },
+				      { 0, 0, FLOAT_TO_FP(1) } };
 
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+				       { FLOAT_TO_FP(1), 0, 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
 
-const mat33_fp_t gyro_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t gyro_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+				       { FLOAT_TO_FP(1), 0, 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
+
+const mat33_fp_t base_standard_ref_icm42607 = { { 0, FLOAT_TO_FP(1), 0 },
+						{ FLOAT_TO_FP(1), 0, 0 },
+						{ 0, 0, FLOAT_TO_FP(-1) } };
 
+const mat33_fp_t lid_standard_ref_sku57 = { { FLOAT_TO_FP(1), 0, 0 },
+					    { 0, FLOAT_TO_FP(-1), 0 },
+					    { 0, 0, FLOAT_TO_FP(-1) } };
 /* sensor private data */
 static struct kionix_accel_data g_kx022_data;
 static struct bmi_drv_data_t g_bmi160_data;
+static struct icm_drv_data_t g_icm42607_data;
 
 /* BMA253 private data */
 static struct accelgyro_saved_data_t g_bma253_data;
@@ -208,6 +213,49 @@ static const struct motion_sensor_t motion_sensor_bma253 = {
 	},
 };
 
+struct motion_sensor_t motion_sensor_accel_icm42607 = {
+	.name = "Base Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM42607,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm42607_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm42607_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
+	.default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs. */
+	.rot_standard_ref = &base_standard_ref_icm42607,
+	.min_frequency = ICM42607_ACCEL_MIN_FREQ,
+	.max_frequency = ICM42607_ACCEL_MAX_FREQ,
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	},
+};
+
+struct motion_sensor_t motion_sensor_gyro_icm42607 = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM42607,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm42607_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm42607_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &base_standard_ref_icm42607,
+	.min_frequency = ICM42607_GYRO_MIN_FREQ,
+	.max_frequency = ICM42607_GYRO_MAX_FREQ,
+};
+
 /* Drivers */
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
@@ -298,9 +346,9 @@ unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 static int board_is_convertible(void)
 {
 	/* SKU IDs of Ampton & unprovisioned: 1, 2, 3, 4, 255 */
-	return sku_id == 1 || sku_id == 2 || sku_id == 3 || sku_id == 4
-		|| sku_id == 255;
-	}
+	return sku_id == 1 || sku_id == 2 || sku_id == 3 || sku_id == 4 ||
+	       sku_id == 57 || sku_id == 255;
+}
 
 static int board_with_sensor_bma253(void)
 {
@@ -308,6 +356,20 @@ static int board_with_sensor_bma253(void)
 	return sku_id == 3 || sku_id == 4;
 }
 
+static int board_with_sensor_icm42607(void)
+{
+	/* SKU ID 3 and 4 of Ampton with BMA253 */
+	return sku_id == 57;
+}
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	if (board_with_sensor_icm42607())
+		icm42607_interrupt(signal);
+	else
+		bmi160_interrupt(signal);
+}
+
 static void board_update_sensor_config_from_sku(void)
 {
 	if (board_is_convertible()) {
@@ -315,6 +377,15 @@ static void board_update_sensor_config_from_sku(void)
 
 		if (board_with_sensor_bma253())
 			motion_sensors[LID_ACCEL] = motion_sensor_bma253;
+		if (board_with_sensor_icm42607()) {
+			motion_sensors[BASE_ACCEL] =
+				motion_sensor_accel_icm42607;
+			motion_sensors[BASE_GYRO] = motion_sensor_gyro_icm42607;
+			ccprints("Gyro sensor: ICM-42607");
+		}
+		if (sku_id == 57)
+			motion_sensors[LID_ACCEL].rot_standard_ref =
+				&lid_standard_ref_sku57;
 
 		/* Enable Base Accel interrupt */
 		gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
@@ -373,9 +444,8 @@ void board_overcurrent_event(int port, int is_overcurrented)
 	cprints(CC_USBPD, "p%d: overcurrent!", port);
 }
 
-#ifndef TEST_BUILD
 /* This callback disables keyboard when convertibles are fully open */
-void lid_angle_peripheral_enable(int enable)
+__override void lid_angle_peripheral_enable(int enable)
 {
 	/*
 	 * If the lid is in tablet position via other sensors,
@@ -387,4 +457,3 @@ void lid_angle_peripheral_enable(int enable)
 	if (board_is_convertible())
 		keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
 }
-#endif
diff --git a/board/ampton/board.h b/board/ampton/board.h
index 69304cb7c8..4a00f82cd2 100644
--- a/board/ampton/board.h
+++ b/board/ampton/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,8 +13,10 @@
 #define VARIANT_OCTOPUS_CHARGER_ISL9238
 #include "baseboard.h"
 
+#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD
+
 /* I2C bus configuraiton */
-#define I2C_PORT_ACCEL	I2C_PORT_SENSOR
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
 
 /* EC console commands  */
 #define CONFIG_CMD_ACCELS
@@ -26,17 +28,21 @@
 
 #define CONFIG_LED_COMMON
 
+#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV 5000
+
 /* Sensors */
 #define CONFIG_TEMP_SENSOR
 #define CONFIG_THERMISTOR
 #define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
 #define CONFIG_STEINHART_HART_3V3_13K7_47K_4050B
-#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_PP3300
+#define CONFIG_TEMP_SENSOR_POWER
+#define GPIO_TEMP_SENSOR_POWER GPIO_EN_PP3300
 
-#define CONFIG_ACCEL_BMA255	/* Lid accel */
-#define CONFIG_ACCEL_KX022	/* Lid accel */
-#define CONFIG_ACCELGYRO_BMI160	/* Base accel */
-#define CONFIG_SYNC		/* Camera VSYNC */
+#define CONFIG_ACCEL_BMA255 /* Lid accel */
+#define CONFIG_ACCEL_KX022 /* Lid accel */
+#define CONFIG_ACCELGYRO_BMI160 /* Base accel */
+#define CONFIG_ACCELGYRO_ICM42607 /* Base accel */
+#define CONFIG_SYNC /* Camera VSYNC */
 
 #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
 /* Sensors without hardware FIFO are in forced mode */
@@ -49,8 +55,9 @@
 
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_SYNC_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
+#define CONFIG_ACCELGYRO_ICM42607_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+#define CONFIG_SYNC_INT_EVENT TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
 
 /* Keyboard backlight is unimplemented in hardware */
 #undef CONFIG_PWM
@@ -82,22 +89,19 @@ enum temp_sensor_id {
 };
 
 /* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	VSYNC,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, VSYNC, SENSOR_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
 	BATTERY_C214,
 	BATTERY_C204EE,
 	BATTERY_C424,
+	BATTERY_C204_SECOND,
 	BATTERY_TYPE_COUNT,
 };
 
+void motion_interrupt(enum gpio_signal signal);
+
 #endif /* !__ASSEMBLER__ */
 
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/ampton/build.mk b/board/ampton/build.mk
index cc6b73093e..daf4529f19 100644
--- a/board/ampton/build.mk
+++ b/board/ampton/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/ampton/ec.tasklist b/board/ampton/ec.tasklist
index 2703dd0b5c..466dd4c60f 100644
--- a/board/ampton/ec.tasklist
+++ b/board/ampton/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/ampton/gpio.inc b/board/ampton/gpio.inc
index 724d9a98d9..c1d7769668 100644
--- a/board/ampton/gpio.inc
+++ b/board/ampton/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -32,7 +32,7 @@ GPIO_INT(RSMRST_L_PGOOD, PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)	/* PM
 GPIO_INT(ALL_SYS_PGOOD,	 PIN(F, 0), GPIO_INT_BOTH, power_signal_interrupt)	/* PMIC_EC_PWROK_OD */
 GPIO_INT(AC_PRESENT, 	 PIN(A, 7), GPIO_INT_BOTH, extpower_interrupt)		/* ACOK_OD */
 
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 /* enable 1.8v input of EC's espi_reset pin, and then this pin takes effect. */
 GPIO_INT(ESPI_RESET_L, 	 PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt) /* eSPI_reset# */
 #endif
@@ -41,7 +41,7 @@ GPIO_INT(ESPI_RESET_L, 	 PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset
 GPIO_INT(TABLET_MODE_L,		PIN(H, 4), GPIO_INT_BOTH, gmr_tablet_switch_isr)
 GPIO_INT(EC_VOLDN_BTN_ODL,	PIN(D, 6), GPIO_INT_BOTH, button_interrupt)
 GPIO_INT(EC_VOLUP_BTN_ODL,	PIN(D, 5), GPIO_INT_BOTH, button_interrupt)
-GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(J, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, bmi160_interrupt)
+GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(J, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, motion_interrupt)
 GPIO(LID_ACCEL_INT_L,		PIN(J, 3), GPIO_INPUT | GPIO_SEL_1P8V)
 
 GPIO(PCH_PLTRST_L,	 PIN(E, 3), GPIO_INPUT)		/* PLT_RST_L: Platform Reset from SoC */
diff --git a/board/ampton/led.c b/board/ampton/led.c
index 68f9e3eac8..02bafec4e0 100644
--- a/board/ampton/led.c
+++ b/board/ampton/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,34 +10,43 @@
 #include "led_common.h"
 #include "led_onoff_states.h"
 
-#define LED_OFF_LVL	0
-#define LED_ON_LVL	1
+#define LED_OFF_LVL 0
+#define LED_ON_LVL 1
 
-const int led_charge_lvl_1 = 0;
+__override const int led_charge_lvl_1;
 
-const int led_charge_lvl_2 = 94;
+__override const int led_charge_lvl_2 = 94;
 
 /* Ampton: Note there is only LED for charge / power */
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]       = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 BUILD_ASSERT(ARRAY_SIZE(led_bat_state_table) == LED_NUM_STATES);
 
 const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-void led_set_color_battery(enum ec_led_colors color)
+__override void led_set_color_battery(enum ec_led_colors color)
 {
 	switch (color) {
 	case EC_LED_COLOR_WHITE:
@@ -72,4 +81,3 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 
 	return EC_SUCCESS;
 }
-
diff --git a/board/ampton/vif_override.xml b/board/ampton/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/ampton/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/anahera/battery.c b/board/anahera/battery.c
new file mode 100644
index 0000000000..f7b0b6f43f
--- /dev/null
+++ b/board/anahera/battery.c
@@ -0,0 +1,94 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "common.h"
+#include "compile_time_macros.h"
+
+/*
+ * Battery info for all Anahera battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	/* 996QA193H Simplo HIGHPOWER Battery Information */
+	[BATTERY_SIMPLO_HIGHPOWER] = {
+		.fuel_gauge = {
+			.manuf_name = "333-1D-11-A",
+			.ship_mode = {
+				.reg_addr = 0x0,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 13200,		/* mV */
+			.voltage_normal = 11550,	/* mV */
+			.voltage_min = 9000,		/* mV */
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -20,
+			.discharging_max_c = 60,
+		},
+	},
+	/* B00C407792D0001 CosMX Battery Information */
+	[BATTERY_COSMX] = {
+		.fuel_gauge = {
+			.manuf_name = "333-AC-11-A",
+			.ship_mode = {
+				.reg_addr = 0x0,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 13200,		/* mV */
+			.voltage_normal = 11550,	/* mV */
+			.voltage_min = 9000,		/* mV */
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SIMPLO_HIGHPOWER;
diff --git a/board/anahera/board.c b/board/anahera/board.c
new file mode 100644
index 0000000000..f5fc90a9aa
--- /dev/null
+++ b/board/anahera/board.c
@@ -0,0 +1,66 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "button.h"
+#include "charge_ramp.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "lid_switch.h"
+#include "peripheral_charger.h"
+#include "power.h"
+#include "power_button.h"
+#include "registers.h"
+#include "switch.h"
+#include "throttle_ap.h"
+#include "usbc_config.h"
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* Console output macros */
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+
+/******************************************************************************/
+/* USB-A charging control */
+
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_PP5000_USBA_R,
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
+
+/******************************************************************************/
+
+/* Called on AP S3 -> S0 transition */
+static void board_chipset_resume(void)
+{
+	/* Allow keyboard backlight to be enabled */
+	gpio_set_level(GPIO_EC_KB_BL_EN, 1);
+	ioex_set_level(IOEX_USB_A1_PD_R_L, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S0 -> S3 transition */
+static void board_chipset_suspend(void)
+{
+	/* Turn off the keyboard backlight if it's on. */
+	gpio_set_level(GPIO_EC_KB_BL_EN, 0);
+	ioex_set_level(IOEX_USB_A1_PD_R_L, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
+
+enum battery_present battery_hw_present(void)
+{
+	/* The GPIO is low when the battery is physically present */
+	return gpio_get_level(GPIO_EC_BATT_PRES_ODL) ? BP_NO : BP_YES;
+}
diff --git a/board/anahera/board.h b/board/anahera/board.h
new file mode 100644
index 0000000000..517e934f87
--- /dev/null
+++ b/board/anahera/board.h
@@ -0,0 +1,211 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Anahera board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "compile_time_macros.h"
+
+/* Baseboard features */
+#include "baseboard.h"
+
+/*
+ * This will happen automatically on NPCX9 ES2 and later. Do not remove
+ * until we can confirm all earlier chips are out of service.
+ */
+#define CONFIG_HIBERNATE_PSL_VCC1_RST_WAKEUP
+
+/* Sensors */
+#undef CONFIG_TABLET_MODE
+#undef CONFIG_TABLET_MODE_SWITCH
+#undef CONFIG_GMR_TABLET_MODE
+
+/* No side buttons */
+#undef CONFIG_MKBP_INPUT_DEVICES
+#undef CONFIG_VOLUME_BUTTONS
+
+/* USB Type A Features */
+#define USB_PORT_COUNT 1
+#define CONFIG_USB_PORT_POWER_DUMB
+#define CONFIG_USBC_RETIMER_PS8811
+
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 5
+
+/* USB Type C and USB PD defines */
+#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
+
+#define CONFIG_IO_EXPANDER
+#define CONFIG_IO_EXPANDER_NCT38XX
+#define CONFIG_IO_EXPANDER_PORT_COUNT 2
+
+#define CONFIG_USB_PD_FRS_PPC
+
+#define CONFIG_USBC_RETIMER_INTEL_BB
+
+#define CONFIG_USBC_PPC_SYV682X
+#define CONFIG_USBC_PPC_NX20P3483
+
+/* TODO: b/193452481 - measure and check these values on redrix */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
+
+/*
+ * Passive USB-C cables only support up to 60W.
+ */
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
+
+/*
+ * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
+ * signal.
+ */
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
+
+/* System has back-lit keyboard */
+#define CONFIG_PWM_KBLIGHT
+
+/* I2C Bus Configuration */
+#define I2C_PORT_USB_C0_TCPC NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1
+
+#define I2C_PORT_USB_C0_PPC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1
+
+#define I2C_PORT_USB_C0_BC12 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1
+
+#define I2C_PORT_USB_C0_MUX NPCX_I2C_PORT3_0
+#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1
+
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+
+#define I2C_PORT_USB_A0_RETIMER NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_A1_RETIMER NPCX_I2C_PORT6_1
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+
+/*
+ * see b/174768555#comment22
+ */
+#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x56
+#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x58
+
+/* Enabling Thunderbolt-compatible mode */
+#define CONFIG_USB_PD_TBT_COMPAT_MODE
+
+/* Enabling USB4 mode */
+#define CONFIG_USB_PD_USB4
+
+/* Retimer */
+#define CONFIG_USBC_RETIMER_FW_UPDATE
+
+/* Thermal features */
+#define CONFIG_THERMISTOR
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_TEMP_SENSOR_POWER
+#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
+
+/* Fan features */
+#define CONFIG_FANS FAN_CH_COUNT
+#define CONFIG_CUSTOM_FAN_CONTROL
+#define RPM_DEVIATION 1
+
+/* Charger defines */
+#define CONFIG_CHARGER_BQ25720
+#define CONFIG_CHARGER_BQ25720_VSYS_TH2_CUSTOM
+#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV 70
+#define CONFIG_CHARGE_RAMP_HW
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10
+
+/* Keyboard features */
+#define CONFIG_KEYBOARD_FACTORY_TEST
+#define CONFIG_KEYBOARD_VIVALDI
+#define CONFIG_KEYBOARD_REFRESH_ROW3
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h" /* needed by registers.h */
+#include "registers.h"
+#include "usbc_config.h"
+
+enum adc_channel {
+	ADC_TEMP_SENSOR_1_FAN,
+	ADC_TEMP_SENSOR_2_SOC,
+	ADC_TEMP_SENSOR_3_CHARGER,
+	ADC_TEMP_SENSOR_4_REGULATOR,
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1_FAN,
+	TEMP_SENSOR_2_SOC,
+	TEMP_SENSOR_3_CHARGER,
+	TEMP_SENSOR_4_REGULATOR,
+	TEMP_SENSOR_COUNT
+};
+
+enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_C1_NCT38XX, IOEX_PORT_COUNT };
+
+enum battery_type {
+	BATTERY_SIMPLO_HIGHPOWER,
+	BATTERY_COSMX,
+	BATTERY_TYPE_COUNT
+};
+
+enum pwm_channel {
+	PWM_CH_KBLIGHT = 0, /* PWM3 */
+	PWM_CH_FAN, /* PWM5 */
+	PWM_CH_COUNT
+};
+
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT };
+
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT };
+
+#ifdef CONFIG_KEYBOARD_FACTORY_TEST
+extern const int keyboard_factory_scan_pins[][2];
+extern const int keyboard_factory_scan_pins_used;
+#endif
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/anahera/build.mk b/board/anahera/build.mk
new file mode 100644
index 0000000000..dda59fdd82
--- /dev/null
+++ b/board/anahera/build.mk
@@ -0,0 +1,26 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Anahera board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx9
+CHIP_VARIANT:=npcx9m3f
+BASEBOARD:=brya
+
+board-y=
+board-y+=battery.o
+board-y+=board.o
+board-y+=charger.o
+board-y+=fans.o
+board-y+=fw_config.o
+board-y+=i2c.o
+board-y+=keyboard.o
+board-y+=led.o
+board-y+=pwm.o
+board-y+=sensors.o
+board-y+=thermal.o
+board-y+=usbc_config.o
diff --git a/board/anahera/charger.c b/board/anahera/charger.c
new file mode 100644
index 0000000000..827152e115
--- /dev/null
+++ b/board/anahera/charger.c
@@ -0,0 +1,82 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/charger/bq25710.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+#ifndef CONFIG_ZEPHYR
+/* Charger Chip Configuration */
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = BQ25710_SMBUS_ADDR1_FLAGS,
+		.drv = &bq25710_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CHARGER_NUM);
+#endif
+
+int board_set_active_charge_port(int port)
+{
+	int is_valid_port = board_is_usb_pd_port_present(port);
+	int i;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTSUSB("Disabling all charger ports");
+
+		/* Disable all ports. */
+		for (i = 0; i < ppc_cnt; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (ppc_vbus_sink_enable(i, 0))
+				CPRINTSUSB("Disabling C%d as sink failed.", i);
+		}
+
+		return EC_SUCCESS;
+	} else if (!is_valid_port) {
+		return EC_ERROR_INVAL;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (ppc_is_sourcing_vbus(port)) {
+		CPRINTFUSB("Skip enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTSUSB("New charge port: C%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < ppc_cnt; i++) {
+		if (i == port)
+			continue;
+
+		if (ppc_vbus_sink_enable(i, 0))
+			CPRINTSUSB("C%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTSUSB("C%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/board/anahera/ec.tasklist b/board/anahera/ec.tasklist
new file mode 100644
index 0000000000..ebbfd239f9
--- /dev/null
+++ b/board/anahera/ec.tasklist
@@ -0,0 +1,29 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ *
+ * USB_CHG_Px tasks must be contiguous (see USB_CHG_PORT_TO_TASK_ID(x)).
+ * PD_Cx tasks must be contiguous (see PD_PORT_TO_TASK_ID(x))
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, HOOKS_TASK_STACK_SIZE) \
+	TASK_ALWAYS(LED, led_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, BASEBOARD_CHARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, BASEBOARD_CHIPSET_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, CONSOLE_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, BASEBOARD_POWERBTN_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, BASEBOARD_PD_INT_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, BASEBOARD_PD_INT_TASK_STACK_SIZE)
diff --git a/board/anahera/fans.c b/board/anahera/fans.c
new file mode 100644
index 0000000000..f60adb9cb4
--- /dev/null
+++ b/board/anahera/fans.c
@@ -0,0 +1,44 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Physical fans. These are logically separate from pwm_channels. */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "fan.h"
+#include "fan_chip.h"
+#include "hooks.h"
+#include "pwm.h"
+
+/* MFT channels. These are logically separate from pwm_channels. */
+const struct mft_t mft_channels[] = {
+	[MFT_CH_0] = {
+		.module = NPCX_MFT_MODULE_1,
+		.clk_src = TCKC_LFCLK,
+		.pwm_id = PWM_CH_FAN,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
+
+static const struct fan_conf fan_conf_0 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
+	.pgood_gpio = -1,
+	.enable_gpio = GPIO_EN_PP5000_FAN,
+};
+
+static const struct fan_rpm fan_rpm_0 = {
+	.rpm_min = 2800,
+	.rpm_start = 2800,
+	.rpm_max = 5000,
+};
+
+const struct fan_t fans[FAN_CH_COUNT] = {
+	[FAN_CH_0] = {
+		.conf = &fan_conf_0,
+		.rpm = &fan_rpm_0,
+	},
+};
diff --git a/board/anahera/fw_config.c b/board/anahera/fw_config.c
new file mode 100644
index 0000000000..c44343bdb7
--- /dev/null
+++ b/board/anahera/fw_config.c
@@ -0,0 +1,73 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "fw_config.h"
+
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
+
+static union anahera_cbi_fw_config fw_config;
+BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
+
+/*
+ * FW_CONFIG defaults for anahera if the CBI.FW_CONFIG data is not
+ * initialized.
+ */
+static const union anahera_cbi_fw_config fw_config_defaults = {
+	.kb_bl = KEYBOARD_BACKLIGHT_DISABLED,
+};
+
+static uint32_t cbi_sku_id;
+
+/****************************************************************************
+ * Anahera FW_CONFIG access
+ */
+void board_init_fw_config(void)
+{
+	if (cbi_get_fw_config(&fw_config.raw_value)) {
+		CPRINTS("CBI: Read FW_CONFIG failed, using board defaults");
+		fw_config = fw_config_defaults;
+	}
+
+	if (get_board_id() == 0) {
+		/*
+		 * Early boards have a zero'd out FW_CONFIG, so replace
+		 * it with a sensible default value.
+		 */
+		if (fw_config.raw_value == 0) {
+			CPRINTS("CBI: FW_CONFIG is zero, using board defaults");
+			fw_config = fw_config_defaults;
+		}
+	}
+
+	/* Saving sku for later use */
+	if (cbi_get_sku_id(&cbi_sku_id) != EC_SUCCESS)
+		cbi_sku_id = 0;
+}
+
+union anahera_cbi_fw_config get_fw_config(void)
+{
+	return fw_config;
+}
+
+bool ec_cfg_has_eps(void)
+{
+	return (fw_config.eps == EPS_ENABLED);
+}
+
+bool ec_cfg_has_kblight(void)
+{
+	return (fw_config.kb_bl == KEYBOARD_BACKLIGHT_ENABLED);
+}
+
+bool ec_cfg_has_lte(void)
+{
+	/* Also check for mis-configured skus 0xA0108~0xA010B */
+	return (fw_config.lte_db == LTE_PRESENT) ||
+	       ((cbi_sku_id >= 0xA0108) && (cbi_sku_id <= 0xA010B));
+}
diff --git a/board/anahera/fw_config.h b/board/anahera/fw_config.h
new file mode 100644
index 0000000000..32787c1e4f
--- /dev/null
+++ b/board/anahera/fw_config.h
@@ -0,0 +1,74 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __BOARD_ANAHERA_FW_CONFIG_H_
+#define __BOARD_ANAHERA_FW_CONFIG_H_
+
+#include <stdint.h>
+
+/****************************************************************************
+ * CBI FW_CONFIG layout for Anahera board.
+ *
+ * Source of truth is the project/brya/anahera/config.star configuration file.
+ */
+
+enum ec_cfg_keyboard_backlight_type {
+	KEYBOARD_BACKLIGHT_DISABLED = 0,
+	KEYBOARD_BACKLIGHT_ENABLED = 1
+};
+
+enum ec_cfg_eps_type { EPS_DISABLED = 0, EPS_ENABLED = 1 };
+
+enum ec_cfg_ite_type {
+	LTE_NOT_PRESENT = 0,
+	LTE_PRESENT = 1,
+};
+
+union anahera_cbi_fw_config {
+	struct {
+		uint32_t sd_db : 2;
+		enum ec_cfg_keyboard_backlight_type kb_bl : 1;
+		uint32_t audio : 3;
+		enum ec_cfg_ite_type lte_db : 2;
+		uint32_t ufc : 2;
+		enum ec_cfg_eps_type eps : 1;
+		uint32_t boot_device : 2;
+		uint32_t reserved_1 : 19;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Read the cached FW_CONFIG.  Guaranteed to have valid values.
+ *
+ * @return the FW_CONFIG for the board.
+ */
+union anahera_cbi_fw_config get_fw_config(void);
+
+/**
+ * Check if the FW_CONFIG has enabled privacy screen.
+ *
+ * @return true if board supports privacy screen, false if the board
+ * doesn't support it.
+ */
+bool ec_cfg_has_eps(void);
+
+/**
+ * Check if the FW_CONFIG has enabled keyboard backlight.
+ *
+ * @return true if board supports keyboard backlight, false if the board
+ * doesn't support it.
+ */
+bool ec_cfg_has_kblight(void);
+
+/**
+ * Check if the FW_CONFIG has LTE present.
+ *
+ * @return true if board supports LTE, false if the board
+ * doesn't support it.
+ */
+bool ec_cfg_has_lte(void);
+
+#endif /* __BOARD_ANAHERA_FW_CONFIG_H_ */
diff --git a/board/anahera/gpio.inc b/board/anahera/gpio.inc
new file mode 100644
index 0000000000..5cce74abff
--- /dev/null
+++ b/board/anahera/gpio.inc
@@ -0,0 +1,150 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define MODULE_KB		MODULE_KEYBOARD_SCAN
+
+/* INTERRUPT GPIOs: */
+GPIO_INT(ACOK_OD,                        PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
+GPIO_INT(EC_PROCHOT_IN_L,                PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
+GPIO_INT(EC_WP_ODL,                      PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(GSC_EC_PWR_BTN_ODL,             PIN(0, 1), GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW, power_button_interrupt)
+GPIO_INT(LID_OPEN,                       PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
+GPIO_INT(SEQ_EC_ALL_SYS_PG,              PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_DSW_PWROK,               PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_RSMRST_ODL,              PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,                       PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,                      PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SYS_SLP_S0IX_L,                 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(USB_C0_BC12_INT_ODL,            PIN(C, 6), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C0_TCPC_INT_ODL,            PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C0_PPC_INT_ODL,             PIN(6, 2), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C0_RT_INT_ODL,              PIN(B, 1), GPIO_INT_FALLING, retimer_interrupt)
+GPIO_INT(USB_C1_TCPC_INT_ODL,            PIN(A, 2), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C1_BC12_INT_ODL,            PIN(8, 3), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C1_PPC_INT_ODL,             PIN(7, 0), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C1_RT_INT_ODL,              PIN(4, 1), GPIO_INT_FALLING, retimer_interrupt)
+
+/* USED GPIOs: */
+GPIO(CCD_MODE_ODL,                   PIN(E, 5), GPIO_INPUT)
+GPIO(CHARGER_VAP_OTG_EN,             PIN(9, 6), GPIO_OUT_LOW)
+GPIO(CPU_C10_GATE_L,                 PIN(6, 7), GPIO_INPUT)
+GPIO(EC_BATT_PRES_ODL,               PIN(A, 3), GPIO_INPUT)
+GPIO(EC_ENTERING_RW,                 PIN(0, 3), GPIO_OUT_LOW)
+GPIO(EC_EN_EDP_BL,                   PIN(D, 3), GPIO_OUT_HIGH)
+GPIO(EC_GSC_PACKET_MODE,             PIN(7, 5), GPIO_OUT_LOW)
+GPIO(EC_I2C_BAT_SCL,                 PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_BAT_SDA,                 PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SCL_R,              PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SDA_R,              PIN(B, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_PPC_BC_SCL,       PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_PPC_BC_SDA,       PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_RT_SCL,           PIN(D, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_RT_SDA,           PIN(D, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_TCPC_SCL,         PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_TCPC_SDA,         PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_MIX_SCL,          PIN(E, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_MIX_SDA,          PIN(E, 3), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_TCPC_SCL,         PIN(F, 3), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_TCPC_SDA,         PIN(F, 2), GPIO_INPUT)
+GPIO(EC_KB_BL_EN,                    PIN(8, 6), GPIO_OUT_LOW)
+GPIO(EC_PCHHOT_ODL,                  PIN(7, 4), GPIO_INPUT)
+GPIO(EC_PCH_INT_ODL,                 PIN(B, 0), GPIO_ODR_HIGH)
+GPIO(EC_PCH_PWR_BTN_ODL,             PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(EC_PCH_RSMRST_L,                PIN(A, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_RTCRST,                  PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_SYS_PWROK,               PIN(3, 7), GPIO_OUT_LOW)
+GPIO(EC_PCH_WAKE_R_ODL,              PIN(C, 0), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_ODL,                 PIN(6, 3), GPIO_ODR_HIGH)
+GPIO(EN_PP5000_FAN,                  PIN(6, 1), GPIO_OUT_LOW)
+GPIO(EN_PP5000_USBA_R,               PIN(D, 7), GPIO_OUT_LOW)
+GPIO(EN_S5_RAILS,                    PIN(B, 6), GPIO_OUT_LOW)
+GPIO(IMVP9_VRRDY_OD,                 PIN(4, 3), GPIO_INPUT)
+GPIO(PCH_PWROK,                      PIN(7, 2), GPIO_OUT_LOW)
+GPIO(SYS_RST_ODL,                    PIN(C, 5), GPIO_ODR_HIGH)
+GPIO(USB_C0_TCPC_RST_ODL,            PIN(A, 7), GPIO_ODR_LOW)
+GPIO(USB_C1_TCPC_RST_ODL,            PIN(A, 0), GPIO_ODR_LOW)
+GPIO(VCCST_PWRGD_OD,                 PIN(A, 4), GPIO_ODR_LOW)
+
+/* LED */
+GPIO(C0_CHARGE_LED_AMBER_L,          PIN(C, 4), GPIO_OUT_HIGH)	/* Amber C0 port */
+GPIO(C0_CHARGE_LED_WHITE_L,          PIN(C, 3), GPIO_OUT_HIGH)	/* White C0 port */
+GPIO(C1_CHARGE_LED_AMBER_L,          PIN(5, 7), GPIO_OUT_HIGH)	/* Amber C1 port */
+GPIO(C1_CHARGE_LED_WHITE_L,          PIN(9, 4), GPIO_OUT_HIGH)	/* White C1 port */
+
+/* UART alternate functions */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)              /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */
+
+/* I2C alternate functions */
+ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)               /* GPIO33/I2C5_SCL0/CTS_L, GPIO36/RTS_L/I2C5_SDA0 */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)               /* GPIO87/I2C1_SDA0 */
+ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)               /* GPIO92/I2C2_SCL0, GPIO91/I2C2_SDA0, GPIO90/I2C1_SCL0 */
+ALTERNATE(PIN_MASK(B, 0x0c), 0, MODULE_I2C, 0)               /* GPIOB3/I2C7_SCL0/DCD_L, GPIOB2/I2C7_SDA0/DSR_L */
+ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)               /* GPIOD1/I2C3_SCL0, GPIOD0/I2C3_SDA0 */
+ALTERNATE(PIN_MASK(E, 0x18), 0, MODULE_I2C, 0)               /* GPIOE4/I2C6_SCL1/I3C_SCL, GPIOE3/I2C6_SDA1/I3C_SDA */
+ALTERNATE(PIN_MASK(F, 0x0c), 0, MODULE_I2C, 0)               /* GPIOF3/I2C4_SCL1, GPIOF2/I2C4_SDA1 */
+
+/* PWM alternate functions */
+ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0)               /* GPIO40/TA1 */
+ALTERNATE(PIN_MASK(7, 0x08), 0, MODULE_PWM, 0)               /* GPIO73/TA2 */
+ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)               /* GPIO80/PWM3 */
+ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)               /* GPIOB7/PWM5 */
+
+/* ADC alternate functions */
+ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0)               /* GPIO34/PS2_DAT2/ADC6 */
+ALTERNATE(PIN_MASK(4, 0x34), 0, MODULE_ADC, 0)               /* GPIO42/ADC3/RI_L, GPIO45/ADC0, GPIO44/ADC1 */
+ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0)               /* GPIOE1/ADC7 */
+
+/* KB alternate functions */
+ALTERNATE(PIN_MASK(0, 0xf0), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO10&P80_CLK/GPIO07, KSO11&P80_DAT/GPIO06, KSO12/GPIO05, KSO13/GPIO04 */
+ALTERNATE(PIN_MASK(1, 0x7f), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO06/GPO13/GP_SEL_L, KSO07/GPO12/JEN_L, KSO03/GPIO16/JTAG_TDO0_SWO, KSO04/GPIO15/XNOR, KSO05/GPIO14, KSO08/GPIO11/CR_SOUT1, KSO09/GPIO10/CR_SIN1 */
+ALTERNATE(PIN_MASK(2, 0xfc), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI2/GPIO27/TRACEDATA1, KSI3/GPIO26/TRACEDATA0, KSI4/GPIO25/TRACECLK/GP_SCLK, KSI5/GPIO24/GP_MISO, KSI6/GPIO23/S_SBUB, KSI7/GPIO22/S_SBUA */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO00/GPIO21/JTAG_TCK_SWCLK, KSO01/GPIO20/JTAG_TMS_SWIO */
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI0/GPIO31/TRACEDATA3/GP_MOSI, KSI1/GPIO30/TRACEDATA2/GP_CS_L */
+ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO14/GPIO82 */
+
+/* PMU alternate functions */
+ALTERNATE(PIN_MASK(0, 0x01), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN2_L&GPI00/GPIO00 */
+ALTERNATE(PIN_MASK(0, 0x02), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW) /* GPIO01/PSL_IN3_L&GPI01 */
+ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN1_L&GPID2/GPIOD2 */
+
+/* Unused Pins */
+UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
+UNUSED(PIN(3, 2))       /* GPO32/TRIS_L */
+UNUSED(PIN(3, 5))       /* GPO35/CR_SOUT4/TEST_L */
+UNUSED(PIN(6, 6))       /* GPO66/ARM_L_x86 */
+UNUSED(PIN(0, 2))       /* GPIO02/PSL_IN4 */
+UNUSED(PIN(5, 0))       /* GPIO50 */
+UNUSED(PIN(5, 6))       /* GPIO56/CLKRUN_L */
+UNUSED(PIN(6, 0))       /* GPIO60/PWM7 */
+UNUSED(PIN(7, 3))       /* GPIO73/TA2 */
+UNUSED(PIN(8, 1))       /* GPIO81/PECI_DATA */
+UNUSED(PIN(9, 5))       /* GPIO95/SPIP_MISO */
+UNUSED(PIN(B, 4))       /* GPIOB4/I2C0_SDA0 */
+UNUSED(PIN(B, 5))       /* GPIOB5/I2C0_SCL0 */
+UNUSED(PIN(C, 2))       /* GPIOC2/PWM1/I2C6_SCL0 */
+UNUSED(PIN(D, 4))       /* GPIOD4/CR_SIN3 */
+UNUSED(PIN(F, 5))       /* GPIOF5/I2C5_SCL1 */
+UNUSED(PIN(9, 3))       /* GPIO93/TA1/F_DIO2 */
+UNUSED(PIN(9, 7))       /* GPIO97 */
+
+/* Pre-configured PSL balls:  J8  K6 */
+
+/*
+ * The NPCX keyboard driver does not use named GPIOs to access
+ * keyboard scan pins, so we do not list them in *gpio.inc. However, when
+ * KEYBOARD_COL2_INVERTED is defined, this name is required.
+ */
+GPIO(EC_KSO_02_INV,               PIN(1, 7), GPIO_OUT_LOW)
+
+IOEX(USB_C0_OC_ODL,          EXPIN(IOEX_C0_NCT38XX, 0, 4), GPIO_ODR_HIGH)
+IOEX(USB_C0_FRS_EN,          EXPIN(IOEX_C0_NCT38XX, 0, 6), GPIO_OUT_LOW)
+IOEX(USB_C0_RT_RST_ODL,      EXPIN(IOEX_C0_NCT38XX, 0, 7), GPIO_ODR_LOW)
+
+IOEX(USB_C1_OC_ODL,          EXPIN(IOEX_C1_NCT38XX, 0, 4), GPIO_ODR_HIGH)
+IOEX(USB_C1_FRS_EN,          EXPIN(IOEX_C1_NCT38XX, 0, 6), GPIO_OUT_LOW)
+IOEX(USB_C1_RT_RST_ODL,      EXPIN(IOEX_C1_NCT38XX, 0, 7), GPIO_ODR_LOW)
+IOEX(USB_A1_PD_R_L,          EXPIN(IOEX_C1_NCT38XX, 1, 7), GPIO_OUT_LOW)
diff --git a/board/anahera/i2c.c b/board/anahera/i2c.c
new file mode 100644
index 0000000000..e9ccf2d928
--- /dev/null
+++ b/board/anahera/i2c.c
@@ -0,0 +1,69 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "i2c.h"
+
+/* I2C port map configuration */
+const struct i2c_port_t i2c_ports[] = {
+	{
+		/* I2C1 */
+		.name = "tcpc0",
+		.port = I2C_PORT_USB_C0_TCPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_TCPC_SDA,
+	},
+	{
+		/* I2C2 */
+		.name = "ppc0,usba0_retimer",
+		.port = I2C_PORT_USB_C0_PPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_PPC_BC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_PPC_BC_SDA,
+	},
+	{
+		/* I2C3 */
+		.name = "retimer0",
+		.port = I2C_PORT_USB_C0_MUX,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_RT_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_RT_SDA,
+	},
+	{
+		/* I2C4 C1 TCPC */
+		.name = "tcpc1",
+		.port = I2C_PORT_USB_C1_TCPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C1_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C1_TCPC_SDA,
+	},
+	{
+		/* I2C5 */
+		.name = "battery",
+		.port = I2C_PORT_BATTERY,
+		.kbps = 100,
+		.scl = GPIO_EC_I2C_BAT_SCL,
+		.sda = GPIO_EC_I2C_BAT_SDA,
+	},
+	{
+		/* I2C6 */
+		.name = "ppc1,retimer1,usba1_retimer",
+		.port = I2C_PORT_USB_C1_PPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C1_MIX_SCL,
+		.sda = GPIO_EC_I2C_USB_C1_MIX_SDA,
+	},
+	{
+		/* I2C7 */
+		.name = "eeprom",
+		.port = I2C_PORT_EEPROM,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_MISC_SCL_R,
+		.sda = GPIO_EC_I2C_MISC_SDA_R,
+	},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/board/anahera/keyboard.c b/board/anahera/keyboard.c
new file mode 100644
index 0000000000..8588191460
--- /dev/null
+++ b/board/anahera/keyboard.c
@@ -0,0 +1,166 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "ec_commands.h"
+#include "fw_config.h"
+#include "keyboard_scan.h"
+#include "timer.h"
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/* Increase from 50 us, because KSO_02 passes through the H1. */
+	.output_settle_us = 80,
+	/* Other values should be the same as the default configuration. */
+	.debounce_down_us = 9 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x1c, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
+		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
+	},
+};
+
+static const struct ec_response_keybd_config keybd_wo_privacy_w_kblight = {
+	.num_top_row_keys = 13,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_KBD_BKLIGHT_TOGGLE,	/* T8 */
+		TK_PLAY_PAUSE,		/* T9 */
+		TK_MICMUTE,		/* T10 */
+		TK_VOL_MUTE,		/* T11 */
+		TK_VOL_DOWN,		/* T12 */
+		TK_VOL_UP,		/* T13 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+static const struct ec_response_keybd_config
+	keybd_wo_privacy_wo_kblight_old = {
+	.num_top_row_keys = 13,
+	.action_keys = {
+		TK_BACK,			/* T1 */
+		TK_REFRESH,			/* T2 */
+		TK_FULLSCREEN,			/* T3 */
+		TK_OVERVIEW,			/* T4 */
+		TK_SNAPSHOT,			/* T5 */
+		TK_BRIGHTNESS_DOWN,		/* T6 */
+		TK_BRIGHTNESS_UP,		/* T7 */
+		TK_PREV_TRACK,			/* T8 */
+		TK_PLAY_PAUSE,			/* T9 */
+		TK_MICMUTE,			/* T10 */
+		TK_VOL_MUTE,			/* T11 */
+		TK_VOL_DOWN,			/* T12 */
+		TK_VOL_UP,			/* T13 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+static const struct ec_response_keybd_config
+	keybd_wo_privacy_wo_kblight_new = {
+	.num_top_row_keys = 13,
+	.action_keys = {
+		TK_BACK,			/* T1 */
+		TK_REFRESH,			/* T2 */
+		TK_FULLSCREEN,			/* T3 */
+		TK_OVERVIEW,			/* T4 */
+		TK_SNAPSHOT,			/* T5 */
+		TK_BRIGHTNESS_DOWN,		/* T6 */
+		TK_BRIGHTNESS_UP,		/* T7 */
+		TK_PLAY_PAUSE,			/* T8 */
+		TK_MICMUTE,			/* T9 */
+		TK_VOL_MUTE,			/* T10 */
+		TK_VOL_DOWN,			/* T11 */
+		TK_VOL_UP,			/* T12 */
+		TK_MENU,			/* T13 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+static const struct ec_response_keybd_config keybd_w_privacy_w_kblight = {
+	.num_top_row_keys = 13,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_PRIVACY_SCRN_TOGGLE,	/* T8 */
+		TK_KBD_BKLIGHT_TOGGLE,	/* T9 */
+		TK_MICMUTE,		/* T10 */
+		TK_VOL_MUTE,		/* T11 */
+		TK_VOL_DOWN,		/* T12 */
+		TK_VOL_UP,		/* T13 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+static const struct ec_response_keybd_config keybd_w_privacy_wo_kblight = {
+	.num_top_row_keys = 13,
+	.action_keys = {
+		TK_BACK,			/* T1 */
+		TK_REFRESH,			/* T2 */
+		TK_FULLSCREEN,			/* T3 */
+		TK_OVERVIEW,			/* T4 */
+		TK_SNAPSHOT,			/* T5 */
+		TK_BRIGHTNESS_DOWN,		/* T6 */
+		TK_BRIGHTNESS_UP,		/* T7 */
+		TK_PRIVACY_SCRN_TOGGLE,		/* T8 */
+		TK_PLAY_PAUSE,			/* T9 */
+		TK_MICMUTE,			/* T10 */
+		TK_VOL_MUTE,			/* T11 */
+		TK_VOL_DOWN,			/* T12 */
+		TK_VOL_UP,			/* T13 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	if (ec_cfg_has_eps()) {
+		if (ec_cfg_has_kblight())
+			return &keybd_w_privacy_w_kblight;
+		else
+			return &keybd_w_privacy_wo_kblight;
+	} else {
+		if (ec_cfg_has_kblight())
+			return &keybd_wo_privacy_w_kblight;
+		else {
+			if (get_board_id() <= 3)
+				return &keybd_wo_privacy_wo_kblight_old;
+			else
+				return &keybd_wo_privacy_wo_kblight_new;
+		}
+	}
+}
+
+#ifdef CONFIG_KEYBOARD_FACTORY_TEST
+/*
+ * Map keyboard connector pins to EC GPIO pins for factory test.
+ * Pins mapped to {-1, -1} are skipped.
+ * The connector has 24 pins total, and there is no pin 0.
+ */
+const int keyboard_factory_scan_pins[][2] = {
+	{ -1, -1 }, { 0, 5 }, { 1, 1 },	  { 1, 0 },   { 0, 6 },
+	{ 0, 7 },   { 1, 4 }, { 1, 3 },	  { 1, 6 },   { 1, 7 },
+	{ 3, 1 },   { 2, 0 }, { 1, 5 },	  { 2, 6 },   { 2, 7 },
+	{ 2, 1 },   { 2, 4 }, { 2, 5 },	  { 1, 2 },   { 2, 3 },
+	{ 2, 2 },   { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 },
+};
+
+const int keyboard_factory_scan_pins_used =
+	ARRAY_SIZE(keyboard_factory_scan_pins);
+#endif
diff --git a/board/anahera/led.c b/board/anahera/led.c
new file mode 100644
index 0000000000..06e557c81d
--- /dev/null
+++ b/board/anahera/led.c
@@ -0,0 +1,223 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power and battery LED control for Redrix
+ */
+
+#include "battery.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "chipset.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "host_command.h"
+#include "led_common.h"
+#include "task.h"
+
+#include <stdint.h>
+
+#define BAT_LED_ON 0
+#define BAT_LED_OFF 1
+
+#define POWER_LED_ON 0
+#define POWER_LED_OFF 1
+
+#define BATT_LOW_BCT 10
+
+#define LED_TICK_INTERVAL_MS (500 * MSEC)
+#define LED_CYCLE_TIME_MS (2000 * MSEC)
+#define LED_TICKS_PER_CYCLE (LED_CYCLE_TIME_MS / LED_TICK_INTERVAL_MS)
+#define LED_ON_TIME_MS (1000 * MSEC)
+#define LED_ON_TICKS (LED_ON_TIME_MS / LED_TICK_INTERVAL_MS)
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_LEFT_LED,
+					     EC_LED_ID_RIGHT_LED };
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+enum led_color {
+	LED_OFF = 0,
+	LED_AMBER,
+	LED_WHITE,
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
+};
+
+enum led_port { LEFT_PORT = 0, RIGHT_PORT };
+
+static void led_set_color_battery(int port, enum led_color color)
+{
+	enum gpio_signal amber_led, white_led;
+
+	amber_led = (port == RIGHT_PORT ? GPIO_C1_CHARGE_LED_AMBER_L :
+					  GPIO_C0_CHARGE_LED_AMBER_L);
+	white_led = (port == RIGHT_PORT ? GPIO_C1_CHARGE_LED_WHITE_L :
+					  GPIO_C0_CHARGE_LED_WHITE_L);
+
+	switch (color) {
+	case LED_WHITE:
+		gpio_set_level(white_led, BAT_LED_ON);
+		gpio_set_level(amber_led, BAT_LED_OFF);
+		break;
+	case LED_AMBER:
+		gpio_set_level(white_led, BAT_LED_OFF);
+		gpio_set_level(amber_led, BAT_LED_ON);
+		break;
+	case LED_OFF:
+		gpio_set_level(white_led, BAT_LED_OFF);
+		gpio_set_level(amber_led, BAT_LED_OFF);
+		break;
+	default:
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	switch (led_id) {
+	case EC_LED_ID_LEFT_LED:
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		break;
+	case EC_LED_ID_RIGHT_LED:
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		break;
+	default:
+		break;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	switch (led_id) {
+	case EC_LED_ID_LEFT_LED:
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_battery(LEFT_PORT, LED_WHITE);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(LEFT_PORT, LED_AMBER);
+		else
+			led_set_color_battery(LEFT_PORT, LED_OFF);
+		break;
+	case EC_LED_ID_RIGHT_LED:
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_battery(RIGHT_PORT, LED_WHITE);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(RIGHT_PORT, LED_AMBER);
+		else
+			led_set_color_battery(RIGHT_PORT, LED_OFF);
+		break;
+	default:
+		return EC_ERROR_PARAM1;
+	}
+
+	return EC_SUCCESS;
+}
+
+/*
+ * Set active charge port color to the parameter, turn off all others.
+ * If no port is active (-1), turn off all LEDs.
+ */
+static void set_active_port_color(enum led_color color)
+{
+	int port = charge_manager_get_active_charge_port();
+
+	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
+		led_set_color_battery(RIGHT_PORT,
+				      (port == RIGHT_PORT) ? color : LED_OFF);
+	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
+		led_set_color_battery(LEFT_PORT,
+				      (port == LEFT_PORT) ? color : LED_OFF);
+}
+
+static void led_set_battery(void)
+{
+	static unsigned int battery_ticks;
+
+	battery_ticks++;
+
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
+		/* Always indicate when charging, even in suspend. */
+		set_active_port_color(LED_AMBER);
+		break;
+	case LED_PWRS_DISCHARGE:
+		/*
+		 * Blinking amber LEDs slowly if battery is lower 10
+		 * percentage.
+		 */
+		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
+			if (charge_get_percent() < BATT_LOW_BCT)
+				led_set_color_battery(
+					RIGHT_PORT,
+					(battery_ticks % LED_TICKS_PER_CYCLE <
+					 LED_ON_TICKS) ?
+						LED_AMBER :
+						LED_OFF);
+			else
+				led_set_color_battery(RIGHT_PORT, LED_OFF);
+		}
+
+		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) {
+			if (charge_get_percent() < BATT_LOW_BCT)
+				led_set_color_battery(
+					LEFT_PORT,
+					(battery_ticks % LED_TICKS_PER_CYCLE <
+					 LED_ON_TICKS) ?
+						LED_AMBER :
+						LED_OFF);
+			else
+				led_set_color_battery(LEFT_PORT, LED_OFF);
+		}
+		break;
+	case LED_PWRS_ERROR:
+		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
+			led_set_color_battery(
+				RIGHT_PORT,
+				(battery_ticks & 0x1) ? LED_AMBER : LED_OFF);
+		}
+
+		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) {
+			led_set_color_battery(LEFT_PORT, (battery_ticks & 0x1) ?
+								 LED_AMBER :
+								 LED_OFF);
+		}
+		break;
+	case LED_PWRS_CHARGE_NEAR_FULL:
+		set_active_port_color(LED_WHITE);
+		break;
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		set_active_port_color(LED_WHITE);
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		set_active_port_color(
+			(battery_ticks % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
+				LED_AMBER :
+				LED_OFF);
+		break;
+	default:
+		/* Other states don't alter LED behavior */
+		break;
+	}
+}
+
+void led_task(void *u)
+{
+	uint32_t start_time;
+	uint32_t task_duration;
+
+	while (1) {
+		start_time = get_time().le.lo;
+
+		led_set_battery();
+
+		/* Compute time for this iteration */
+		task_duration = get_time().le.lo - start_time;
+		/*
+		 * Compute wait time required to for next desired LED tick. If
+		 * the duration exceeds the tick time, then don't sleep.
+		 */
+		if (task_duration < LED_TICK_INTERVAL_MS)
+			usleep(LED_TICK_INTERVAL_MS - task_duration);
+	}
+}
diff --git a/board/anahera/pwm.c b/board/anahera/pwm.c
new file mode 100644
index 0000000000..1d1747413f
--- /dev/null
+++ b/board/anahera/pwm.c
@@ -0,0 +1,30 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "hooks.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_KBLIGHT] = {
+		.channel = 3,
+		.flags = 0,
+		/*
+		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
+		 * flicker. Higher frequencies consume similar average power to
+		 * lower PWM frequencies, but higher frequencies record a much
+		 * lower maximum power.
+		 */
+		.freq = 2400,
+	},
+	[PWM_CH_FAN] = {
+		.channel = 5,
+		.flags = PWM_CONFIG_OPEN_DRAIN,
+		.freq = 25000
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
diff --git a/board/anahera/sensors.c b/board/anahera/sensors.c
new file mode 100644
index 0000000000..6946e0cd13
--- /dev/null
+++ b/board/anahera/sensors.c
@@ -0,0 +1,140 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc_chip.h"
+#include "common.h"
+#include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
+#include "thermal.h"
+
+/* ADC configuration */
+const struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_1_FAN] = {
+		.name = "TEMP_FAN",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_2_SOC] = {
+		.name = "TEMP_SOC",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_3_CHARGER] = {
+		.name = "TEMP_CHARGER",
+		.input_ch = NPCX_ADC_CH6,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_4_REGULATOR] = {
+		.name = "TEMP_REGULATOR",
+		.input_ch = NPCX_ADC_CH7,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* Temperature sensor configuration */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1_FAN] = { .name = "Fan",
+				.type = TEMP_SENSOR_TYPE_BOARD,
+				.read = get_temp_3v3_30k9_47k_4050b,
+				.idx = ADC_TEMP_SENSOR_1_FAN },
+	[TEMP_SENSOR_2_SOC] = { .name = "SOC",
+				.type = TEMP_SENSOR_TYPE_BOARD,
+				.read = get_temp_3v3_30k9_47k_4050b,
+				.idx = ADC_TEMP_SENSOR_2_SOC },
+	[TEMP_SENSOR_3_CHARGER] = { .name = "Charger",
+				    .type = TEMP_SENSOR_TYPE_BOARD,
+				    .read = get_temp_3v3_30k9_47k_4050b,
+				    .idx = ADC_TEMP_SENSOR_3_CHARGER },
+	[TEMP_SENSOR_4_REGULATOR] = { .name = "Regulator",
+				      .type = TEMP_SENSOR_TYPE_BOARD,
+				      .read = get_temp_3v3_30k9_47k_4050b,
+				      .idx = ADC_TEMP_SENSOR_4_REGULATOR },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_FAN              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(73), \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_fan = THERMAL_FAN;
+
+/*
+ * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
+ * 130 C.  However, sensor is located next to SOC, so we need to use the lower
+ * SOC temperature limit (85 C)
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
+
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CHARGER          \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(80), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(85), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_charger =
+	THERMAL_CHARGER;
+
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_REGULATOR        \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(55), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(60), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(48), \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_regulator =
+	THERMAL_REGULATOR;
+
+/* this should really be "const" */
+struct ec_thermal_config thermal_params[] = {
+	[TEMP_SENSOR_1_FAN] = THERMAL_FAN,
+	[TEMP_SENSOR_2_SOC] = THERMAL_CPU,
+	[TEMP_SENSOR_3_CHARGER] = THERMAL_CHARGER,
+	[TEMP_SENSOR_4_REGULATOR] = THERMAL_REGULATOR,
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
diff --git a/board/anahera/thermal.c b/board/anahera/thermal.c
new file mode 100644
index 0000000000..b5b5a0c1cc
--- /dev/null
+++ b/board/anahera/thermal.c
@@ -0,0 +1,146 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "fan.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "temp_sensor.h"
+#include "thermal.h"
+#include "util.h"
+
+/* Console output macros */
+#define CPUTS(outstr) cputs(CC_THERMAL, outstr)
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
+
+struct fan_step {
+	/*
+	 * Sensor 1~4 trigger point, set -1 if we're not using this
+	 * sensor to determine fan speed.
+	 */
+	int8_t on[TEMP_SENSOR_COUNT];
+
+	/*
+	 * Sensor 1~4 trigger point, set -1 if we're not using this
+	 * sensor to determine fan speed.
+	 */
+	int8_t off[TEMP_SENSOR_COUNT];
+
+	/* Fan 1~2 rpm */
+	uint16_t rpm[FAN_CH_COUNT];
+};
+
+static const struct fan_step fan_table[] = {
+	{
+		/* level 0 */
+		.on = { 53, 51, 0, -1 },
+		.off = { 99, 99, 99, -1 },
+		.rpm = { 0 },
+	},
+	{
+		/* level 1 */
+		.on = { 54, 52, 0, -1 },
+		.off = { 52, 50, 99, -1 },
+		.rpm = { 3000 },
+	},
+	{
+		/* level 2 */
+		.on = { 55, 53, 0, -1 },
+		.off = { 53, 51, 99, -1 },
+		.rpm = { 3400 },
+	},
+	{
+		/* level 3 */
+		.on = { 56, 54, 0, -1 },
+		.off = { 54, 52, 99, -1 },
+		.rpm = { 3800 },
+	},
+	{
+		/* level 4 */
+		.on = { 57, 55, 54, -1 },
+		.off = { 55, 53, 51, -1 },
+		.rpm = { 4100 },
+	},
+	{
+		/* level 5 */
+		.on = { 58, 56, 60, -1 },
+		.off = { 56, 54, 52, -1 },
+		.rpm = { 4400 },
+	},
+	{
+		/* level 6 */
+		.on = { 100, 100, 100, -1 },
+		.off = { 57, 59, 58, -1 },
+		.rpm = { 4900 },
+	},
+};
+
+#define NUM_FAN_LEVELS ARRAY_SIZE(fan_table)
+
+int fan_table_to_rpm(int fan, int *temp)
+{
+	static int current_level;
+	static int prev_tmp[TEMP_SENSOR_COUNT];
+	int i;
+
+	/*
+	 * Compare the current and previous temperature, we have
+	 * the three paths :
+	 *  1. decreasing path. (check the release point)
+	 *  2. increasing path. (check the trigger point)
+	 *  3. invariant path. (return the current RPM)
+	 */
+	if (temp[TEMP_SENSOR_1_FAN] < prev_tmp[TEMP_SENSOR_1_FAN] ||
+	    temp[TEMP_SENSOR_2_SOC] < prev_tmp[TEMP_SENSOR_2_SOC] ||
+	    temp[TEMP_SENSOR_3_CHARGER] < prev_tmp[TEMP_SENSOR_3_CHARGER]) {
+		for (i = current_level; i > 0; i--) {
+			if (temp[TEMP_SENSOR_1_FAN] <
+				    fan_table[i].off[TEMP_SENSOR_1_FAN] &&
+			    temp[TEMP_SENSOR_3_CHARGER] <
+				    fan_table[i].off[TEMP_SENSOR_3_CHARGER] &&
+			    temp[TEMP_SENSOR_2_SOC] <
+				    fan_table[i].off[TEMP_SENSOR_2_SOC])
+				current_level = i - 1;
+			else
+				break;
+		}
+	} else if (temp[TEMP_SENSOR_1_FAN] > prev_tmp[TEMP_SENSOR_1_FAN] ||
+		   temp[TEMP_SENSOR_2_SOC] > prev_tmp[TEMP_SENSOR_2_SOC] ||
+		   temp[TEMP_SENSOR_3_CHARGER] >
+			   prev_tmp[TEMP_SENSOR_3_CHARGER]) {
+		for (i = current_level; i < NUM_FAN_LEVELS; i++) {
+			if ((temp[TEMP_SENSOR_1_FAN] >
+				     fan_table[i].on[TEMP_SENSOR_1_FAN] &&
+			     temp[TEMP_SENSOR_3_CHARGER] >
+				     fan_table[i].on[TEMP_SENSOR_3_CHARGER]) ||
+			    temp[TEMP_SENSOR_2_SOC] >
+				    fan_table[i].on[TEMP_SENSOR_2_SOC])
+				current_level = i + 1;
+			else
+				break;
+		}
+	}
+
+	if (current_level < 0)
+		current_level = 0;
+
+	if (current_level >= NUM_FAN_LEVELS)
+		current_level = NUM_FAN_LEVELS - 1;
+
+	for (i = 0; i < TEMP_SENSOR_COUNT; ++i)
+		prev_tmp[i] = temp[i];
+
+	return fan_table[current_level].rpm[FAN_CH_0];
+}
+
+void board_override_fan_control(int fan, int *tmp)
+{
+	if (chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND)) {
+		fan_set_rpm_mode(FAN_CH(fan), 1);
+		fan_set_rpm_target(FAN_CH(fan), fan_table_to_rpm(fan, tmp));
+	}
+}
diff --git a/board/anahera/usbc_config.c b/board/anahera/usbc_config.c
new file mode 100644
index 0000000000..907f236d70
--- /dev/null
+++ b/board/anahera/usbc_config.c
@@ -0,0 +1,448 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/bc12/pi3usb9201_public.h"
+#include "driver/ppc/syv682x_public.h"
+#include "driver/retimer/bb_retimer_public.h"
+#include "driver/retimer/ps8811.h"
+#include "driver/tcpm/nct38xx.h"
+#include "driver/tcpm/tcpci.h"
+#include "ec_commands.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "ioexpander.h"
+#include "system.h"
+#include "task.h"
+#include "task_id.h"
+#include "timer.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+/* USBC TCPC configuration */
+const struct tcpc_config_t tcpc_config[] = {
+	[USBC_PORT_C0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0_TCPC,
+			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+	},
+	[USBC_PORT_C1] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C1_TCPC,
+			.addr_flags = NCT38XX_I2C_ADDR1_4_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
+BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
+
+/* USBC PPC configuration */
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_PPC,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.frs_en = IOEX_USB_C0_FRS_EN,
+		.drv = &syv682x_drv,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C1_PPC,
+		.i2c_addr_flags = SYV682X_ADDR2_FLAGS,
+		.frs_en = IOEX_USB_C1_FRS_EN,
+		.drv = &syv682x_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
+
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/* USBC mux configuration - Alder Lake includes internal mux */
+static const struct usb_mux_chain usbc0_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+static const struct usb_mux_chain usbc1_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+
+const struct usb_mux_chain usb_muxes[] = {
+	[USBC_PORT_C0] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C0_MUX,
+			.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc0_tcss_usb_mux,
+	},
+	[USBC_PORT_C1] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C1_MUX,
+			.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc1_tcss_usb_mux,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
+
+/* BC1.2 charger detect configuration */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C1_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_1_FLAGS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
+
+/*
+ * USB C0 and C1 uses burnside bridge chips and have their reset
+ * controlled by their respective TCPC chips acting as GPIO expanders.
+ *
+ * ioex_init() is normally called before we take the TCPCs out of
+ * reset, so we need to start in disabled mode, then explicitly
+ * call ioex_init().
+ */
+
+struct ioexpander_config_t ioex_config[] = {
+	[IOEX_C0_NCT38XX] = {
+		.i2c_host_port = I2C_PORT_USB_C0_TCPC,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
+	},
+	[IOEX_C1_NCT38XX] = {
+		.i2c_host_port = I2C_PORT_USB_C1_TCPC,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR1_4_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT);
+
+__override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
+{
+	enum ioex_signal rst_signal;
+
+	if (me->usb_port == USBC_PORT_C0) {
+		rst_signal = IOEX_USB_C0_RT_RST_ODL;
+	} else if (me->usb_port == USBC_PORT_C1) {
+		rst_signal = IOEX_USB_C1_RT_RST_ODL;
+	} else {
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * We do not have a load switch for the burnside bridge chips,
+	 * so we only need to sequence reset.
+	 */
+
+	if (enable) {
+		/*
+		 * Tpw, minimum time from VCC to RESET_N de-assertion is 100us.
+		 * For boards that don't provide a load switch control, the
+		 * retimer_init() function ensures power is up before calling
+		 * this function.
+		 */
+		ioex_set_level(rst_signal, 1);
+		/*
+		 * Allow 1ms time for the retimer to power up lc_domain
+		 * which powers I2C controller within retimer
+		 */
+		msleep(1);
+	} else {
+		ioex_set_level(rst_signal, 0);
+		msleep(1);
+	}
+	return EC_SUCCESS;
+}
+
+void board_reset_pd_mcu(void)
+{
+	gpio_set_level(GPIO_USB_C0_TCPC_RST_ODL, 0);
+	gpio_set_level(GPIO_USB_C1_TCPC_RST_ODL, 0);
+
+	/*
+	 * delay for power-on to reset-off and min. assertion time
+	 */
+	msleep(NCT38XX_RESET_HOLD_DELAY_MS);
+
+	gpio_set_level(GPIO_USB_C0_TCPC_RST_ODL, 1);
+	gpio_set_level(GPIO_USB_C1_TCPC_RST_ODL, 1);
+
+	nct38xx_reset_notify(USBC_PORT_C0);
+	nct38xx_reset_notify(USBC_PORT_C1);
+
+	/* wait for chips to come up */
+	if (NCT3807_RESET_POST_DELAY_MS != 0)
+		msleep(NCT3807_RESET_POST_DELAY_MS);
+}
+
+static void board_tcpc_init(void)
+{
+	int i;
+
+	/* Don't reset TCPCs after initial reset */
+	if (!system_jumped_late())
+		board_reset_pd_mcu();
+
+	/*
+	 * These IO expander pins are implemented using the
+	 * C0/C1 TCPCs, so they must be set up after the TCPCs has
+	 * been taken out of reset.
+	 */
+	for (i = 0; i < CONFIG_IO_EXPANDER_PORT_COUNT; ++i)
+		ioex_init(i);
+
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
+
+	/* Enable BC1.2 interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_0;
+
+	if (gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
+
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C1);
+		break;
+	default:
+		break;
+	}
+}
+
+void bc12_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_BC12_INT_ODL:
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+		break;
+	case GPIO_USB_C1_BC12_INT_ODL:
+		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+		break;
+	default:
+		break;
+	}
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C1);
+		break;
+	default:
+		break;
+	}
+}
+
+void retimer_interrupt(enum gpio_signal signal)
+{
+	/*
+	 * TODO(b/179513527): add USB-C support
+	 */
+}
+
+__override bool board_is_dts_port(int port)
+{
+	return port == USBC_PORT_C0;
+}
+
+const struct usb_mux usba_ps8811[] = {
+	[USBA_PORT_A0] = {
+		.usb_port = USBA_PORT_A0,
+		.i2c_port = I2C_PORT_USB_A0_RETIMER,
+		.i2c_addr_flags = PS8811_I2C_ADDR_FLAGS0,
+	},
+	[USBA_PORT_A1] = {
+		.usb_port = USBA_PORT_A1,
+		.i2c_port = I2C_PORT_USB_A1_RETIMER,
+		.i2c_addr_flags = PS8811_I2C_ADDR_FLAGS0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(usba_ps8811) == USBA_PORT_COUNT);
+
+const static struct ps8811_reg_val equalizer_wwan_table[] = {
+	{
+		/* Set channel A EQ setting */
+		.reg = PS8811_REG1_USB_AEQ_LEVEL,
+		.val = (PS8811_AEQ_I2C_LEVEL_UP_13DB
+			<< PS8811_AEQ_I2C_LEVEL_UP_SHIFT) |
+		       (PS8811_AEQ_PIN_LEVEL_UP_18DB
+			<< PS8811_AEQ_PIN_LEVEL_UP_SHIFT),
+	},
+	{
+		/* Set ADE pin setting */
+		.reg = PS8811_REG1_USB_ADE_CONFIG,
+		.val = (PS8811_ADE_PIN_MID_LEVEL_3DB
+			<< PS8811_ADE_PIN_MID_LEVEL_SHIFT) |
+		       PS8811_AEQ_CONFIG_REG_ENABLE |
+		       PS8811_AEQ_ADAPTIVE_REG_ENABLE,
+	},
+	{
+		/* Set channel B EQ setting */
+		.reg = PS8811_REG1_USB_BEQ_LEVEL,
+		.val = (PS8811_BEQ_I2C_LEVEL_UP_10P5DB
+			<< PS8811_BEQ_I2C_LEVEL_UP_SHIFT) |
+		       (PS8811_BEQ_PIN_LEVEL_UP_18DB
+			<< PS8811_BEQ_PIN_LEVEL_UP_SHIFT),
+	},
+	{
+		/* Set BDE pin setting */
+		.reg = PS8811_REG1_USB_BDE_CONFIG,
+		.val = (PS8811_BDE_PIN_MID_LEVEL_3DB
+			<< PS8811_BDE_PIN_MID_LEVEL_SHIFT) |
+		       PS8811_BEQ_CONFIG_REG_ENABLE,
+	},
+};
+
+#define NUM_EQ_WWAN_ARRAY ARRAY_SIZE(equalizer_wwan_table)
+
+const static struct ps8811_reg_val equalizer_wlan_table[] = {
+	{
+		/* Set 50ohm adjust for B channel */
+		.reg = PS8811_REG1_50OHM_ADJUST_CHAN_B,
+		.val = (PS8811_50OHM_ADJUST_CHAN_B_MINUS_9PCT
+			<< PS8811_50OHM_ADJUST_CHAN_B_SHIFT),
+	},
+};
+
+#define NUM_EQ_WLAN_ARRAY ARRAY_SIZE(equalizer_wlan_table)
+
+static int usba_retimer_init(int port)
+{
+	int rv;
+	int val;
+	int i;
+	const struct usb_mux *me = &usba_ps8811[port];
+
+	rv = ps8811_i2c_read(me, PS8811_REG_PAGE1, PS8811_REG1_USB_BEQ_LEVEL,
+			     &val);
+
+	switch (port) {
+	case USBA_PORT_A0:
+		/* Set channel A output swing */
+		rv = ps8811_i2c_field_update(me, PS8811_REG_PAGE1,
+					     PS8811_REG1_USB_CHAN_A_SWING,
+					     PS8811_CHAN_A_SWING_MASK,
+					     0x2 << PS8811_CHAN_A_SWING_SHIFT);
+		break;
+	case USBA_PORT_A1:
+		if (ec_cfg_has_lte()) {
+			/* Set channel A output swing */
+			rv = ps8811_i2c_field_update(
+				me, PS8811_REG_PAGE1,
+				PS8811_REG1_USB_CHAN_A_SWING,
+				PS8811_CHAN_A_SWING_MASK,
+				0x2 << PS8811_CHAN_A_SWING_SHIFT);
+
+			/* Set channel B output PS level */
+			rv |= ps8811_i2c_field_update(
+				me, PS8811_REG_PAGE1,
+				PS8811_REG1_USB_CHAN_B_DE_PS_LSB,
+				PS8811_CHAN_B_DE_PS_LSB_MASK, 0x06);
+
+			/* Set channel B output DE level */
+			rv |= ps8811_i2c_field_update(
+				me, PS8811_REG_PAGE1,
+				PS8811_REG1_USB_CHAN_B_DE_PS_MSB,
+				PS8811_CHAN_B_DE_PS_MSB_MASK, 0x16);
+
+			for (i = 0; i < NUM_EQ_WWAN_ARRAY; i++)
+				rv |= ps8811_i2c_write(
+					me, PS8811_REG_PAGE1,
+					equalizer_wwan_table[i].reg,
+					equalizer_wwan_table[i].val);
+		} else {
+			/* Set channel A output swing */
+			rv = ps8811_i2c_field_update(
+				me, PS8811_REG_PAGE1,
+				PS8811_REG1_USB_CHAN_A_SWING,
+				PS8811_CHAN_A_SWING_MASK,
+				0x2 << PS8811_CHAN_A_SWING_SHIFT);
+
+			for (i = 0; i < NUM_EQ_WLAN_ARRAY; i++)
+				rv |= ps8811_i2c_write(
+					me, PS8811_REG_PAGE1,
+					equalizer_wlan_table[i].reg,
+					equalizer_wlan_table[i].val);
+		}
+		break;
+	}
+
+	return rv;
+}
+
+void board_chipset_startup(void)
+{
+	int i;
+
+	for (i = 0; i < USBA_PORT_COUNT; ++i)
+		usba_retimer_init(i);
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
diff --git a/board/anahera/usbc_config.h b/board/anahera/usbc_config.h
new file mode 100644
index 0000000000..c476919027
--- /dev/null
+++ b/board/anahera/usbc_config.h
@@ -0,0 +1,24 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Anahera board-specific USB-C configuration */
+
+#ifndef __CROS_EC_USBC_CONFIG_H
+#define __CROS_EC_USBC_CONFIG_H
+
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+
+/* USB-A ports */
+enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT };
+
+/* USB-C ports */
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
+
+struct ps8811_reg_val {
+	uint8_t reg;
+	uint16_t val;
+};
+
+#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/anahera/vif_override.xml b/board/anahera/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/anahera/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/arcada_ish/board.c b/board/arcada_ish/board.c
index 624a376dca..efd0f8a0ca 100644
--- a/board/arcada_ish/board.c
+++ b/board/arcada_ish/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,7 +19,8 @@
 #include "tablet_mode.h"
 #include "task.h"
 
-#include "gpio_list.h" /* has to be included last */
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
 
 /* I2C port map */
 const struct i2c_port_t i2c_ports[] = {
@@ -42,11 +43,9 @@ static struct stprivate_data g_lis2dh_data;
 static struct lis2mdl_private_data lis2mdl_a_data;
 
 /* Matrix to rotate lid sensor into standard reference frame */
-const mat33_fp_t lid_rot_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
+const mat33_fp_t lid_rot_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				 { 0, FLOAT_TO_FP(-1), 0 },
+				 { 0, 0, FLOAT_TO_FP(1) } };
 
 /* Drivers */
 struct motion_sensor_t motion_sensors[] = {
@@ -60,8 +59,6 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_lid_mutex,
 		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_a_data,
 				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_ACCEL_GYRO_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
 		.port = I2C_PORT_SENSOR,
 		.i2c_spi_addr_flags = LSM6DSM_ADDR1_FLAGS,
 		.rot_standard_ref = &lid_rot_ref,
@@ -90,8 +87,6 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_lid_mutex,
 		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_a_data,
 				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_ACCEL_GYRO_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
 		.port = I2C_PORT_SENSOR,
 		.i2c_spi_addr_flags = LSM6DSM_ADDR1_FLAGS,
 		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
@@ -159,8 +154,7 @@ int board_sensor_at_360(void)
 	 * closed at 0 degrees. Ignore the hall sensor when the lid close is
 	 * also active.
 	 */
-	return lid_is_open() &&
-	       !gpio_get_level(GMR_TABLET_MODE_GPIO_L);
+	return lid_is_open() && !gpio_get_level(GPIO_TABLET_MODE_L);
 }
 
 /* Initialize board. */
diff --git a/board/arcada_ish/board.h b/board/arcada_ish/board.h
index ca69c1ba15..129640d60f 100644
--- a/board/arcada_ish/board.h
+++ b/board/arcada_ish/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,24 +16,23 @@
 #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
 
 /* ISH specific*/
-#undef  CONFIG_DEBUG_ASSERT
+#undef CONFIG_DEBUG_ASSERT
 #define CONFIG_CLOCK_CRYSTAL
 /* EC */
-#define CONFIG_FLASH_SIZE 0x80000
+#define CONFIG_FLASH_SIZE_BYTES 0x80000
 #define CONFIG_FPU
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
-
-#define CONFIG_ACCEL_LNG2DM		/* Base sensor: LNG2DM
-					 * (uses LIS2DH driver)
-					 */
-#define CONFIG_ACCELGYRO_LSM6DSM	/* Lid sensor: LSM6DS3
-					 * (uses LSM6DSM driver)
-					 */
-#define CONFIG_MAG_LIS2MDL		/* Lid sensor: LIS2DML */
+#define CONFIG_I2C_CONTROLLER
+
+#define CONFIG_ACCEL_LNG2DM /* Base sensor: LNG2DM  \
+			     * (uses LIS2DH driver) \
+			     */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Lid sensor: LSM6DS3   \
+				  * (uses LSM6DSM driver) \
+				  */
+#define CONFIG_MAG_LIS2MDL /* Lid sensor: LIS2DML */
 #define CONFIG_MAG_CALIBRATE
 
-#define CONFIG_ACCEL_INTERRUPTS
 /* Enable sensor fifo, must also define the _SIZE and _THRES */
 #define CONFIG_ACCEL_FIFO
 /* FIFO size is a power of 2. */
@@ -41,7 +40,7 @@
 /* Depends on how fast the AP boots and typical ODRs. */
 #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
 /* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK  (BIT(BASE_ACCEL) | BIT(LID_MAG))
+#define CONFIG_ACCEL_FORCE_MODE_MASK (BIT(BASE_ACCEL) | BIT(LID_MAG))
 
 #define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
@@ -56,13 +55,12 @@
 #define CONFIG_TABLET_MODE
 #define CONFIG_GMR_TABLET_MODE
 #define CONFIG_GMR_TABLET_MODE_CUSTOM
-#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L
 
 /* DMA paging between SRAM and DRAM */
 #define CONFIG_DMA_PAGING
 
 /* Host command over HECI */
-#define CONFIG_HOSTCMD_HECI
+#define CONFIG_HOST_INTERFACE_HECI
 
 /* I2C ports */
 #define I2C_PORT_SENSOR ISH_I2C0
@@ -82,7 +80,7 @@
 #undef CONFIG_CMD_SHMEM
 #undef CONFIG_EXTPOWER
 #undef CONFIG_KEYBOARD_KSO_BASE
-#undef CONFIG_FLASH
+#undef CONFIG_FLASH_CROS
 #undef CONFIG_FMAP
 #undef CONFIG_SWITCH
 
@@ -101,8 +99,8 @@
 #define CONFIG_ISH_PM_D3
 #define CONFIG_ISH_PM_RESET_PREP
 
-#define CONFIG_ISH_D0I2_MIN_USEC        (15*MSEC)	/* need final tune */
-#define CONFIG_ISH_D0I3_MIN_USEC        (100*MSEC)	/* need final tune */
+#define CONFIG_ISH_D0I2_MIN_USEC (15 * MSEC) /* need final tune */
+#define CONFIG_ISH_D0I3_MIN_USEC (100 * MSEC) /* need final tune */
 
 #ifndef __ASSEMBLER__
 
@@ -114,13 +112,7 @@
  * Note: Since we aren't using LPC memory map to transmit sensor data, the
  * order of this enum does not need to be accel, accel, gyro
  */
-enum sensor_id {
-	LID_ACCEL,
-	LID_GYRO,
-	BASE_ACCEL,
-	LID_MAG,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, LID_GYRO, BASE_ACCEL, LID_MAG, SENSOR_COUNT };
 
 #endif /* !__ASSEMBLER__ */
 
diff --git a/board/arcada_ish/build.mk b/board/arcada_ish/build.mk
index a57c08e6ba..80cf4886eb 100644
--- a/board/arcada_ish/build.mk
+++ b/board/arcada_ish/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/arcada_ish/ec.tasklist b/board/arcada_ish/ec.tasklist
index d72fdf309e..81d3c5dc20 100644
--- a/board/arcada_ish/ec.tasklist
+++ b/board/arcada_ish/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/arcada_ish/gpio.inc b/board/arcada_ish/gpio.inc
index 336f807269..6a577d0efe 100644
--- a/board/arcada_ish/gpio.inc
+++ b/board/arcada_ish/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/asurada/battery.c b/board/asurada/battery.c
index f8fc47034f..ad49477366 100644
--- a/board/asurada/battery.c
+++ b/board/asurada/battery.c
@@ -1,11 +1,17 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "battery.h"
 #include "battery_fuel_gauge.h"
+#include "battery_smart.h"
+#include "charge_manager.h"
+#include "chipset.h"
 #include "gpio.h"
+#include "hooks.h"
+#include "system.h"
+#include "usb_pd.h"
 
 const struct board_batt_params board_battery_info[] = {
 	[BATTERY_C235] = {
diff --git a/board/asurada/board.c b/board/asurada/board.c
index 712a89289e..a9b5e0aab4 100644
--- a/board/asurada/board.c
+++ b/board/asurada/board.c
@@ -1,31 +1,24 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 /* Asurada board configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
-#include "board/asurada/it5205_sbu.h"
 #include "button.h"
 #include "charge_manager.h"
-#include "charge_state_v2.h"
+#include "charge_state.h"
 #include "charger.h"
 #include "chipset.h"
 #include "common.h"
 #include "console.h"
 #include "driver/accel_lis2dw12.h"
 #include "driver/accelgyro_bmi_common.h"
+#include "driver/accelgyro_icm426xx.h"
+#include "driver/accelgyro_icm_common.h"
 #include "driver/als_tcs3400.h"
-#include "driver/bc12/mt6360.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/isl923x.h"
-#include "driver/ppc/syv682x.h"
 #include "driver/tcpm/it83xx_pd.h"
 #include "driver/temp_sensor/thermistor.h"
-#include "driver/usb_mux/it5205.h"
-#include "driver/usb_mux/ps8743.h"
-#include "extpower.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "i2c.h"
@@ -33,7 +26,6 @@
 #include "lid_switch.h"
 #include "motion_sense.h"
 #include "power.h"
-#include "power_button.h"
 #include "pwm.h"
 #include "pwm_chip.h"
 #include "regulator.h"
@@ -44,583 +36,47 @@
 #include "temp_sensor.h"
 #include "timer.h"
 #include "uart.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd_tcpm.h"
-#include "usbc_ppc.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-static void bc12_interrupt(enum gpio_signal signal);
-static void ppc_interrupt(enum gpio_signal signal);
-static void x_ec_interrupt(enum gpio_signal signal);
-
-#include "gpio_list.h"
-
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-/*
- * PWM channels. Must be in the exactly same order as in enum pwm_channel.
- * There total three 16 bits clock prescaler registers for all pwm channels,
- * so use the same frequency and prescaler register setting is required if
- * number of pwm channel greater than three.
- */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED1] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
-		.freq_hz = 324, /* maximum supported frequency */
-		.pcfsr_sel = PWM_PRESCALER_C4
-	},
-	[PWM_CH_LED2] = {
-		.channel = 1,
-		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
-		.freq_hz = 324, /* maximum supported frequency */
-		.pcfsr_sel = PWM_PRESCALER_C4
-	},
-	[PWM_CH_LED3] = {
-		.channel = 2,
-		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
-		.freq_hz = 324, /* maximum supported frequency */
-		.pcfsr_sel = PWM_PRESCALER_C4
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* Wake-up pins for hibernate */
-enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_AC_PRESENT,
-	GPIO_LID_OPEN,
-	GPIO_POWER_BUTTON_L,
-};
-int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-__override void board_hibernate_late(void)
-{
-	/*
-	 * Turn off PP5000_A. Required for devices without Z-state.
-	 * Don't care for devices with Z-state.
-	 */
-	gpio_set_level(GPIO_EN_PP5000_A, 0);
-
-	/*
-	 * GPIO_EN_SLP_Z not implemented in rev0/1,
-	 * fallback to usual hibernate process.
-	 */
-	if (board_get_version() <= 1)
-		return;
-
-	isl9238c_hibernate(CHARGER_SOLO);
-
-	gpio_set_level(GPIO_EN_SLP_Z, 1);
-
-	/* should not reach here */
-	__builtin_unreachable();
-}
-
-/* power signal list.  Must match order of enum power_signal. */
-const struct power_signal_info power_signal_list[] = {
-	{GPIO_PMIC_EC_PWRGD, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
-	{GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L"},
-	{GPIO_AP_EC_WATCHDOG_L,
-	  POWER_SIGNAL_ACTIVE_LOW | POWER_SIGNAL_DISABLE_AT_BOOT,
-	  "AP_WDT_ASSERTED"},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-/* Detect subboard */
-static enum board_sub_board board_get_sub_board(void);
 
 /* Initialize board. */
 static void board_init(void)
 {
-	/* For Rev0 only. Set GPM0~6 1.8V input. */
-	IT83XX_GPIO_GCR30 |= BIT(4);
-
-	gpio_enable_interrupt(GPIO_AC_PRESENT);
-
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-
 	/* Enable motion sensor interrupt */
 	gpio_enable_interrupt(GPIO_BASE_IMU_INT_L);
 	gpio_enable_interrupt(GPIO_LID_ACCEL_INT_L);
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
-static void board_tcpc_init(void)
-{
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
-	/* C1: GPIO_USB_C1_PPC_INT_ODL & HDMI: GPIO_PS185_EC_DP_HPD */
-	gpio_enable_interrupt(GPIO_X_EC_GPIO2);
-
-	/* If this is not a Type-C subboard, disable the task. */
-	if (board_get_sub_board() != SUB_BOARD_TYPEC)
-		task_disable_task(TASK_ID_PD_C1);
-}
-/* Must be done after I2C and subboard */
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
-
-/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
-const struct adc_t adc_channels[] = {
-	/* Convert to mV (3000mV/1024). */
-	{"VBUS", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0, CHIP_ADC_CH0},
-	{"BOARD_ID_0", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH1},
-	{"BOARD_ID_1", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH2},
-	{"CHARGER_AMON_R", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH3},
-	{"CHARGER_PMON", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH6},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* BC12 */
-const struct mt6360_config_t mt6360_config = {
-	.i2c_port = 0,
-	.i2c_addr_flags = MT6360_PMU_SLAVE_ADDR_FLAGS,
-};
-
-const struct pi3usb9201_config_t
-		pi3usb9201_bc12_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	/* [0]: unused */
-	[1] = {
-		.i2c_port = 4,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	}
-};
-
-struct bc12_config bc12_ports[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{ .drv = &mt6360_drv },
-	{ .drv = &pi3usb9201_drv },
-};
-
-static void bc12_interrupt(enum gpio_signal signal)
-{
-	if (signal == GPIO_USB_C0_BC12_INT_ODL)
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
-	else
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12, 0);
-}
-
-static void board_sub_bc12_init(void)
-{
-	if (board_get_sub_board() == SUB_BOARD_TYPEC)
-		gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L);
-	else
-		/* If this is not a Type-C subboard, disable the task. */
-		task_disable_task(TASK_ID_USB_CHG_P1);
-}
-/* Must be done after I2C and subboard */
-DECLARE_HOOK(HOOK_INIT, board_sub_bc12_init, HOOK_PRIO_INIT_I2C + 1);
-
-/*
- * I2C channels (A, B, and C) are using the same timing registers (00h~07h)
- * at default.
- * In order to set frequency independently for each channels,
- * We use timing registers 09h~0Bh, and the supported frequency will be:
- * 50KHz, 100KHz, 400KHz, or 1MHz.
- * I2C channels (D, E and F) can be set different frequency on different ports.
- * The I2C(D/E/F) frequency depend on the frequency of SMBus Module and
- * the individual prescale register.
- * The frequency of SMBus module is 24MHz on default.
- * The allowed range of I2C(D/E/F) frequency is as following setting.
- * SMBus Module Freq = PLL_CLOCK / ((IT83XX_ECPM_SCDCR2 & 0x0F) + 1)
- * (SMBus Module Freq / 510) <=  I2C Freq <= (SMBus Module Freq / 8)
- * Channel D has multi-function and can be used as UART interface.
- * Channel F is reserved for EC debug.
- */
-
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"bat_chg",  IT83XX_I2C_CH_A, 100, GPIO_I2C_A_SCL, GPIO_I2C_A_SDA},
-	{"sensor",   IT83XX_I2C_CH_B, 100, GPIO_I2C_B_SCL, GPIO_I2C_B_SDA},
-	{"usb0",     IT83XX_I2C_CH_C, 100, GPIO_I2C_C_SCL, GPIO_I2C_C_SDA},
-	{"usb1",     IT83XX_I2C_CH_E, 100, GPIO_I2C_E_SCL, GPIO_I2C_E_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-int board_allow_i2c_passthru(int port)
-{
-	return (port == I2C_PORT_VIRTUAL_BATTERY);
-}
-
-/* PPC */
-struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.i2c_port = I2C_PORT_PPC0,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-		.frs_en = GPIO_USB_C0_FRS_EN,
-	},
-	{
-		.i2c_port = I2C_PORT_PPC1,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-		.frs_en = GPIO_USB_C1_FRS_EN,
-	},
-};
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
-	if (signal == GPIO_USB_C0_PPC_INT_ODL)
-		/* C0: PPC interrupt */
-		syv682x_interrupt(0);
-}
-
-int debounced_hpd;
-
-/**
- * Handle PS185 HPD changing state.
- */
-static void ps185_hdmi_hpd_deferred(void)
-{
-	const int new_hpd = gpio_get_level(GPIO_PS185_EC_DP_HPD);
-
-	/* HPD status not changed, probably a glitch, just return. */
-	if (debounced_hpd == new_hpd)
-		return;
-
-	debounced_hpd = new_hpd;
-
-	gpio_set_level(GPIO_EC_DPBRDG_HPD_ODL, !debounced_hpd);
-	CPRINTS(debounced_hpd ? "HDMI plug" : "HDMI unplug");
-}
-DECLARE_DEFERRED(ps185_hdmi_hpd_deferred);
-
-#define PS185_HPD_DEBOUCE 250
-
-static void hdmi_hpd_interrupt(enum gpio_signal signal)
-{
-	hook_call_deferred(&ps185_hdmi_hpd_deferred_data, PS185_HPD_DEBOUCE);
-}
-
-/* HDMI/TYPE-C function shared subboard interrupt */
-static void x_ec_interrupt(enum gpio_signal signal)
-{
-	int sub = board_get_sub_board();
-
-	if (sub == SUB_BOARD_TYPEC)
-		/* C1: PPC interrupt */
-		syv682x_interrupt(1);
-	else if (sub == SUB_BOARD_HDMI)
-		hdmi_hpd_interrupt(signal);
-	else
-		CPRINTS("Undetected subboard interrupt.");
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (port == 0)
-		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
-	if (port == 1 && board_get_sub_board() == SUB_BOARD_TYPEC)
-		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
-
-	return 0;
-}
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* TODO: check correct operation for Asurada */
-}
-
-/* TCPC */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_EMBEDDED,
-		/* TCPC is embedded within EC so no i2c config needed */
-		.drv = &it83xx_tcpm_drv,
-		/* Alert is active-low, push-pull */
-		.flags = 0,
-	},
-	{
-		.bus_type = EC_BUS_TYPE_EMBEDDED,
-		/* TCPC is embedded within EC so no i2c config needed */
-		.drv = &it83xx_tcpm_drv,
-		/* Alert is active-low, push-pull */
-		.flags = 0,
-	},
-};
-
-uint16_t tcpc_get_alert_status(void)
-{
-	/*
-	 * C0 & C1: TCPC is embedded in the EC and processes interrupts in the
-	 * chip code (it83xx/intc.c)
-	 */
-	return 0;
-}
+/* Sensor */
+static struct mutex g_base_mutex;
+static struct mutex g_lid_mutex;
 
-void board_reset_pd_mcu(void)
-{
-	/*
-	 * C0 & C1: TCPC is embedded in the EC and processes interrupts in the
-	 * chip code (it83xx/intc.c)
-	 */
-}
+static struct bmi_drv_data_t g_bmi160_data;
+static struct stprivate_data g_lis2dwl_data;
+static struct icm_drv_data_t g_icm426xx_data;
 
-/* USB-A */
-const int usb_port_enable[] = {
-	GPIO_EN_PP5000_USB_A0_VBUS,
+enum base_accelgyro_type {
+	BASE_GYRO_NONE = 0,
+	BASE_GYRO_BMI160 = 1,
+	BASE_GYRO_ICM426XX = 2,
 };
-BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
-
-/* USB Mux */
-static int board_ps8743_mux_set(const struct usb_mux *me,
-				mux_state_t mux_state)
-{
-	int rv = EC_SUCCESS;
-	int reg = 0;
-
-	rv = ps8743_read(me, PS8743_REG_MODE, &reg);
-	if (rv)
-		return rv;
-
-	/* Disable FLIP pin, enable I2C control. */
-	reg |= PS8743_MODE_FLIP_REG_CONTROL;
-	/* Disable CE_USB pin, enable I2C control. */
-	reg |= PS8743_MODE_USB_REG_CONTROL;
-	/* Disable CE_DP pin, enable I2C control. */
-	reg |= PS8743_MODE_DP_REG_CONTROL;
-
-	/*
-	 * DP specific config
-	 *
-	 * Enable/Disable IN_HPD on the DB.
-	 */
-	gpio_set_level(GPIO_USB_C1_DP_IN_HPD,
-		       mux_state & USB_PD_MUX_DP_ENABLED);
 
-	return ps8743_write(me, PS8743_REG_MODE, reg);
-}
+static enum base_accelgyro_type base_accelgyro_config;
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX0,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-	},
-	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_USB_MUX1,
-		.i2c_addr_flags = PS8743_I2C_ADDR0_FLAG,
-		.driver = &ps8743_usb_mux_driver,
-		.board_set = &board_ps8743_mux_set,
-	},
+#ifdef BOARD_ASURADA_REV0
+/* Matrix to rotate accelerometer into standard reference frame */
+/* for rev 0 */
+static const mat33_fp_t base_standard_ref_rev0 = {
+	{ FLOAT_TO_FP(-1), 0, 0 },
+	{ 0, FLOAT_TO_FP(1), 0 },
+	{ 0, 0, FLOAT_TO_FP(-1) },
 };
 
-int board_set_active_charge_port(int port)
-{
-	int i;
-	int is_valid_port = port == 0 || (port == 1 && board_get_sub_board() ==
-							       SUB_BOARD_TYPEC);
-
-	if (!is_valid_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	if (port == CHARGE_PORT_NONE) {
-		CPRINTS("Disabling all charger ports");
-
-		/* Disable all ports. */
-		for (i = 0; i < ppc_cnt; i++) {
-			/*
-			 * Do not return early if one fails otherwise we can
-			 * get into a boot loop assertion failure.
-			 */
-			if (ppc_vbus_sink_enable(i, 0))
-				CPRINTS("Disabling C%d as sink failed.", i);
-		}
-
-		return EC_SUCCESS;
-	}
-
-	/* Check if the port is sourcing VBUS. */
-	if (ppc_is_sourcing_vbus(port)) {
-		CPRINTF("Skip enable C%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	CPRINTS("New charge port: C%d", port);
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < ppc_cnt; i++) {
-		if (i == port)
-			continue;
-
-		if (ppc_vbus_sink_enable(i, 0))
-			CPRINTS("C%d: sink path disable failed.", i);
-	}
-
-	/* Enable requested charge port. */
-	if (ppc_vbus_sink_enable(port, 1)) {
-		CPRINTS("C%d: sink path enable failed.", port);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_set_input_current_limit(
-		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
-
-void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
-{
-	/*
-	 * We ignore the cc_pin and PPC vconn because polarity and PPC vconn
-	 * should already be set correctly in the PPC driver via the pd
-	 * state machine.
-	 */
-}
-
-/* Called on AP S3 -> S0 transition */
-static void board_chipset_resume(void)
-{
-	gpio_set_level(GPIO_EC_BL_EN_OD, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0 -> S3 transition */
-static void board_chipset_suspend(void)
-{
-	gpio_set_level(GPIO_EC_BL_EN_OD, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-/* Sub-board */
-
-static enum board_sub_board board_get_sub_board(void)
-{
-	static enum board_sub_board sub = SUB_BOARD_NONE;
-
-	if (sub != SUB_BOARD_NONE)
-		return sub;
-
-	/* HDMI board has external pull high. */
-	if (gpio_get_level(GPIO_EC_X_GPIO3)) {
-		sub = SUB_BOARD_HDMI;
-		/* Only has 1 PPC with HDMI subboard */
-		ppc_cnt = 1;
-		/* EC_X_GPIO1 */
-		gpio_set_flags(GPIO_EN_HDMI_PWR, GPIO_OUT_HIGH);
-		/* X_EC_GPIO2 */
-		gpio_set_flags(GPIO_PS185_EC_DP_HPD, GPIO_INT_BOTH);
-		/* EC_X_GPIO3 */
-		gpio_set_flags(GPIO_PS185_PWRDN_ODL, GPIO_ODR_HIGH);
-	} else {
-		sub = SUB_BOARD_TYPEC;
-		/* EC_X_GPIO1 */
-		gpio_set_flags(GPIO_USB_C1_FRS_EN, GPIO_OUT_LOW);
-		/* X_EC_GPIO2 */
-		gpio_set_flags(GPIO_USB_C1_PPC_INT_ODL,
-			       GPIO_INT_BOTH | GPIO_PULL_UP);
-		/* EC_X_GPIO3 */
-		gpio_set_flags(GPIO_USB_C1_DP_IN_HPD, GPIO_OUT_LOW);
-	}
-
-	CPRINTS("Detect %s SUB", sub == SUB_BOARD_HDMI ? "HDMI" : "TYPEC");
-	return sub;
-}
-
-static void sub_board_init(void)
-{
-	board_get_sub_board();
-}
-DECLARE_HOOK(HOOK_INIT, sub_board_init, HOOK_PRIO_INIT_I2C - 1);
-
-__override uint8_t board_get_usb_pd_port_count(void)
-{
-	if (board_get_sub_board() == SUB_BOARD_TYPEC)
-		return CONFIG_USB_PD_PORT_MAX_COUNT;
-	else
-		return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
-}
-
-/* Lid */
-#ifndef TEST_BUILD
-/* This callback disables keyboard when convertibles are fully open */
-void lid_angle_peripheral_enable(int enable)
-{
-	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
-
-	if (enable) {
-		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
-	} else {
-		/*
-		 * Ensure that the chipset is off before disabling the keyboard.
-		 * When the chipset is on, the EC keeps the keyboard enabled and
-		 * the AP decides whether to ignore input devices or not.
-		 */
-		if (!chipset_in_s0)
-			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
-	}
-}
-#endif
-
-/* SD Card */
-int board_regulator_get_info(uint32_t index, char *name,
-			     uint16_t *num_voltages, uint16_t *voltages_mv)
-{
-	enum mt6360_regulator_id id = index;
-
-	return mt6360_regulator_get_info(id, name, num_voltages,
-					 voltages_mv);
-}
-
-int board_regulator_enable(uint32_t index, uint8_t enable)
-{
-	enum mt6360_regulator_id id = index;
-
-	return mt6360_regulator_enable(id, enable);
-}
-
-int board_regulator_is_enabled(uint32_t index, uint8_t *enabled)
-{
-	enum mt6360_regulator_id id = index;
-
-	return mt6360_regulator_is_enabled(id, enabled);
-}
-
-int board_regulator_set_voltage(uint32_t index, uint32_t min_mv,
-				uint32_t max_mv)
-{
-	enum mt6360_regulator_id id = index;
-
-	return mt6360_regulator_set_voltage(id, min_mv, max_mv);
-}
-
-int board_regulator_get_voltage(uint32_t index, uint32_t *voltage_mv)
+static void update_rotation_matrix(void)
 {
-	enum mt6360_regulator_id id = index;
-
-	return mt6360_regulator_get_voltage(id, voltage_mv);
+	motion_sensors[BASE_ACCEL].rot_standard_ref = &base_standard_ref_rev0;
+	motion_sensors[BASE_GYRO].rot_standard_ref = &base_standard_ref_rev0;
 }
-
-/* Sensor */
-static struct mutex g_base_mutex;
-static struct mutex g_lid_mutex;
-
-static struct bmi_drv_data_t g_bmi160_data;
-static struct stprivate_data g_lis2dwl_data;
-
-/* Matrix to rotate accelrator into standard reference frame */
-/* TODO: update the matrix after we have assembled unit */
-static const mat33_fp_t mag_standard_ref = {
-	{0, FLOAT_TO_FP(-1), 0},
-	{FLOAT_TO_FP(-1), 0, 0},
-	{0, 0, FLOAT_TO_FP(-1)},
-};
+DECLARE_HOOK(HOOK_INIT, update_rotation_matrix, HOOK_PRIO_INIT_ADC + 2);
 
 /* TCS3400 private data */
 static struct als_drv_data_t g_tcs3400_data = {
@@ -633,25 +89,6 @@ static struct als_drv_data_t g_tcs3400_data = {
 	},
 };
 
-#ifdef BOARD_ASURADA
-/* Matrix to rotate accelerometer into standard reference frame */
-/* for rev 0 */
-static const mat33_fp_t base_standard_ref_rev0 = {
-	{FLOAT_TO_FP(-1), 0, 0},
-	{0, FLOAT_TO_FP(1), 0},
-	{0, 0, FLOAT_TO_FP(-1)},
-};
-
-static void update_rotation_matrix(void)
-{
-	motion_sensors[BASE_ACCEL].rot_standard_ref =
-		&base_standard_ref_rev0;
-	motion_sensors[BASE_GYRO].rot_standard_ref =
-		&base_standard_ref_rev0;
-}
-DECLARE_HOOK(HOOK_INIT, update_rotation_matrix, HOOK_PRIO_INIT_ADC + 1);
-#endif
-
 static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
 	/*
 	 * TODO: calculate the actual coefficients and scaling factors
@@ -693,6 +130,75 @@ static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
 	.saturation.again = TCS_DEFAULT_AGAIN,
 	.saturation.atime = TCS_DEFAULT_ATIME,
 };
+#endif /* BOARD_ASURADA_REV0 */
+
+#ifdef BOARD_HAYATO
+/* Matrix to rotate accelerometer into standard reference frame */
+/* for Hayato */
+static const mat33_fp_t base_standard_ref = {
+	{ 0, FLOAT_TO_FP(1), 0 },
+	{ FLOAT_TO_FP(-1), 0, 0 },
+	{ 0, 0, FLOAT_TO_FP(1) },
+};
+
+static void update_rotation_matrix(void)
+{
+	if (base_accelgyro_config == BASE_GYRO_ICM426XX)
+		return;
+
+	if (board_get_version() >= 2) {
+		motion_sensors[BASE_ACCEL].rot_standard_ref =
+			&base_standard_ref;
+		motion_sensors[BASE_GYRO].rot_standard_ref = &base_standard_ref;
+	}
+}
+DECLARE_HOOK(HOOK_INIT, update_rotation_matrix, HOOK_PRIO_INIT_ADC + 2);
+
+#endif
+
+struct motion_sensor_t icm426xx_base_accel = {
+	.name = "Base Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs. */
+	.rot_standard_ref = NULL,
+	.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
+	.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	},
+};
+
+struct motion_sensor_t icm426xx_base_gyro = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = NULL,
+	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
+	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
+};
 
 struct motion_sensor_t motion_sensors[] = {
 	/*
@@ -744,22 +250,6 @@ struct motion_sensor_t motion_sensors[] = {
 		.min_frequency = BMI_GYRO_MIN_FREQ,
 		.max_frequency = BMI_GYRO_MAX_FREQ,
 	},
-	[BASE_MAG] = {
-		.name = "Base Mag",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_MAG,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.default_range = BIT(11), /* 16LSB / uT, fixed */
-		.rot_standard_ref = &mag_standard_ref,
-		.min_frequency = BMM150_MAG_MIN_FREQ,
-		.max_frequency = BMM150_MAG_MAX_FREQ(SPECIAL),
-	},
 	[LID_ACCEL] = {
 		.name = "Lid Accel",
 		.active_mask = SENSOR_ACTIVE_S0_S3,
@@ -769,10 +259,8 @@ struct motion_sensor_t motion_sensors[] = {
 		.drv = &lis2dw12_drv,
 		.mutex = &g_lid_mutex,
 		.drv_data = &g_lis2dwl_data,
-		.int_signal = GPIO_LID_ACCEL_INT_L,
 		.port = I2C_PORT_ACCEL,
 		.i2c_spi_addr_flags = LIS2DWL_ADDR1_FLAGS,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
 		.rot_standard_ref = NULL, /* identity matrix */
 		.default_range = 2, /* g */
 		.min_frequency = LIS2DW12_ODR_MIN_VAL,
@@ -788,6 +276,7 @@ struct motion_sensor_t motion_sensors[] = {
 			},
 		},
 	},
+#ifdef BOARD_ASURADA_REV0
 	[CLEAR_ALS] = {
 		.name = "Clear Light",
 		.active_mask = SENSOR_ACTIVE_S0_S3,
@@ -823,5 +312,89 @@ struct motion_sensor_t motion_sensors[] = {
 		.min_frequency = 0,
 		.max_frequency = 0,
 	},
+#endif /* BOARD_ASURADA_REV0 */
 };
 const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	if (base_accelgyro_config == BASE_GYRO_ICM426XX)
+		icm426xx_interrupt(signal);
+	else
+		bmi160_interrupt(signal);
+}
+
+static void board_detect_motionsense(void)
+{
+	int val;
+
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return;
+	if (base_accelgyro_config != BASE_GYRO_NONE)
+		return;
+
+	icm_read8(&icm426xx_base_accel, ICM426XX_REG_WHO_AM_I, &val);
+	if (val == ICM426XX_CHIP_ICM40608) {
+		motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
+		motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
+		base_accelgyro_config = BASE_GYRO_ICM426XX;
+		ccprints("Base Accelgyro: ICM426XX");
+	} else {
+		base_accelgyro_config = BASE_GYRO_BMI160;
+		ccprints("Base Accelgyro: BMI160");
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_detect_motionsense, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_INIT, board_detect_motionsense, HOOK_PRIO_DEFAULT);
+
+/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
+const struct adc_t adc_channels[] = {
+	/* Convert to mV (3000mV/1024). */
+	{ "VBUS_C0", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0, CHIP_ADC_CH0 },
+	{ "BOARD_ID_0", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH1 },
+	{ "BOARD_ID_1", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH2 },
+	/* AMON/BMON gain = 17.97 */
+	{ "CHARGER_AMON_R", ADC_MAX_MVOLT * 1000 / 17.97, ADC_READ_MAX + 1, 0,
+	  CHIP_ADC_CH3 },
+	{ "VBUS_C1", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0, CHIP_ADC_CH5 },
+	{ "CHARGER_PMON", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH6 },
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* PWM */
+
+/*
+ * PWM channels. Must be in the exactly same order as in enum pwm_channel.
+ * There total three 16 bits clock prescaler registers for all pwm channels,
+ * so use the same frequency and prescaler register setting is required if
+ * number of pwm channel greater than three.
+ */
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_LED1] = { .channel = 0,
+			  .flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
+			  .freq_hz = 324, /* maximum supported frequency */
+			  .pcfsr_sel = PWM_PRESCALER_C4 },
+	[PWM_CH_LED2] = { .channel = 1,
+			  .flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
+			  .freq_hz = 324, /* maximum supported frequency */
+			  .pcfsr_sel = PWM_PRESCALER_C4 },
+	[PWM_CH_LED3] = { .channel = 2,
+			  .flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
+			  .freq_hz = 324, /* maximum supported frequency */
+			  .pcfsr_sel = PWM_PRESCALER_C4 },
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+static void board_suspend(void)
+{
+	if (board_get_version() >= 3)
+		gpio_set_level(GPIO_EN_5V_USM, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_suspend, HOOK_PRIO_DEFAULT);
+
+static void board_resume(void)
+{
+	if (board_get_version() >= 3)
+		gpio_set_level(GPIO_EN_5V_USM, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_resume, HOOK_PRIO_DEFAULT);
diff --git a/board/asurada/board.h b/board/asurada/board.h
index 26e74ae78f..619be7cb5d 100644
--- a/board/asurada/board.h
+++ b/board/asurada/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,215 +7,93 @@
 #ifndef __CROS_EC_BOARD_H
 #define __CROS_EC_BOARD_H
 
+#include "baseboard.h"
+
 /* Chipset config */
-#define CONFIG_BOARD_RESET_AFTER_POWER_ON
-#define CONFIG_BRINGUP
-#define CONFIG_CHIPSET_MT8192
-#define CONFIG_CMD_POWERINDEBUG
-#define CONFIG_HIBERNATE_WAKE_PINS_DYNAMIC
-#define CONFIG_POWER_COMMON
 
 /* Optional features */
-#define CONFIG_SYSTEM_UNLOCKED
-#define CONFIG_BOARD_VERSION_CUSTOM
-#define CONFIG_EXTPOWER_GPIO
+#define CONFIG_LTO
+
 /*
  * TODO: Remove this option once the VBAT no longer keeps high when
  * system's power isn't presented.
  */
 #define CONFIG_IT83XX_RESET_PD_CONTRACT_IN_BRAM
-#define CONFIG_LOW_POWER_IDLE
-#define CONFIG_LOW_POWER_S0
-#define CONFIG_POWER_BUTTON
-#define CONFIG_PWM
-#define CONFIG_VBOOT_HASH
-#define CONFIG_VOLUME_BUTTONS
-#define CONFIG_WP_ACTIVE_HIGH
-
-/* Battery */
-#define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_FUEL_GAUGE
-#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL
-#define CONFIG_BATTERY_SMART
 
 /* BC12 */
-#define CONFIG_BC12_DETECT_MT6360
-#define CONFIG_BC12_DETECT_PI3USB9201
-#undef CONFIG_BC12_SINGLE_DRIVER
 /* TODO(b/159583342): remove after rev0 deprecated */
 #define CONFIG_MT6360_BC12_GPIO
-#define CONFIG_USB_CHARGER
-
-/* Charger */
-#define ADC_PSYS ADC_CHARGER_PMON /* ADC name remap */
-#define CONFIG_CHARGER
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT 512
-#define CONFIG_CHARGER_ISL9238C
-#define CONFIG_CHARGER_MAINTAIN_VBAT
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 /* BOARD_RS1 */
-#define CONFIG_CHARGER_SENSE_RESISTOR 10 /* BOARD_RS2 */
-#define CONFIG_CHARGER_OTG
-#define CONFIG_CHARGER_PSYS
-#define CONFIG_CHARGER_PSYS_READ
-#define CONFIG_CHARGE_RAMP_HW
-#define CONFIG_CHARGE_MANAGER
-
-/* Chipset */
-
-/* Keyboard */
-#define CONFIG_CMD_KEYBOARD
-#define CONFIG_KEYBOARD_COL2_INVERTED
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
-#define CONFIG_MKBP_USE_GPIO
-
-/* I2C */
-#define CONFIG_I2C
-#define CONFIG_I2C_MASTER
-#define CONFIG_I2C_PASSTHRU_RESTRICTED
-#define CONFIG_I2C_VIRTUAL_BATTERY
-#define I2C_PORT_CHARGER IT83XX_I2C_CH_A
-#define I2C_PORT_BATTERY IT83XX_I2C_CH_A
-#define I2C_PORT_ACCEL IT83XX_I2C_CH_B
-#define I2C_PORT_PPC0  IT83XX_I2C_CH_C
-#define I2C_PORT_PPC1  IT83XX_I2C_CH_E
-#define I2C_PORT_USB_MUX0 IT83XX_I2C_CH_C
-#define I2C_PORT_USB_MUX1 IT83XX_I2C_CH_E
-#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
-#define CONFIG_SMBUS_PEC
 
 /* LED */
-#define CONFIG_LED_COMMON
+#ifdef BOARD_HAYATO
+#define CONFIG_LED_ONOFF_STATES
+#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
+#endif
 
 /* PD / USB-C / PPC */
-#define CONFIG_CMD_PPC_DUMP
-#define CONFIG_HOSTCMD_PD_CONTROL
-#define CONFIG_USBC_PPC
-#define CONFIG_USBC_PPC_DEDICATED_INT
-#define CONFIG_USBC_PPC_POLARITY
-#define CONFIG_USBC_PPC_SYV682X
-#define CONFIG_USBC_PPC_VCONN
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-#define CONFIG_USB_DRP_ACC_TRYSRC
-#define CONFIG_USB_MUX_IT5205 /* C0 */
-#define CONFIG_USB_MUX_IT5205H_SBU_OVP
-#define CONFIG_USB_MUX_PS8743 /* C1 */
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
 #define CONFIG_USB_PD_DEBUG_LEVEL 3
-#define CONFIG_USB_PD_DECODE_SOP
-#define CONFIG_USB_PD_DISCHARGE
-#define CONFIG_USB_PD_DISCHARGE_PPC
-#define CONFIG_USB_PD_DP_HPD_GPIO
-#define CONFIG_USB_PD_DP_HPD_GPIO_CUSTOM
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_REV30
-#define CONFIG_USB_PD_FRS_PPC
-#define CONFIG_USB_PD_FRS_TCPC
-#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 2
-#define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT TYPEC_RP_3A0
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_TCPMV2
-#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_PD_VBUS_DETECT_PPC
-#define CONFIG_USB_PID 0x5566  /* TODO: update PID */
-#define CONFIG_USB_POWER_DELIVERY
-
 #define PD_MAX_CURRENT_MA 3000
-#define PD_MAX_VOLTAGE_MV 20000
 #define PD_OPERATING_POWER_MW 15000
+#ifdef BOARD_HAYATO
+#define PD_MAX_VOLTAGE_MV 15000
+#define PD_MAX_POWER_MW 45000
+#else
+#define PD_MAX_VOLTAGE_MV 20000
 #define PD_MAX_POWER_MW 60000
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
+#endif
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
-#define PD_VCONN_SWAP_DELAY 5000 /* us */
 
 /* Optional console commands */
 #define CONFIG_CMD_FLASH
 #define CONFIG_CMD_SCRATCHPAD
-#define CONFIG_CMD_STACKOVERFLOW
+
+#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV 9000
 
 /* Sensor */
 #define CONFIG_GMR_TABLET_MODE
 #define CONFIG_TABLET_MODE
 #define CONFIG_TABLET_MODE_SWITCH
-#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L
 
-#define CONFIG_ACCEL_FIFO
-#define CONFIG_ACCEL_FIFO_SIZE 256
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-#define CONFIG_ACCEL_INTERRUPTS
 #define CONFIG_ACCELGYRO_BMI160 /* Base accel */
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCELGYRO_SEC_ADDR_FLAGS BMM150_ADDR0_FLAGS
+#define CONFIG_ACCELGYRO_ICM426XX /* Base accel */
+#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 
 #define CONFIG_ACCEL_LIS2DWL
-#define CONFIG_ACCEL_LIS2DW_AS_BASE
-#define CONFIG_ACCEL_LIS2DW12_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
 
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
 #define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
 #define CONFIG_LID_ANGLE_UPDATE
 
-#define CONFIG_CMD_ACCEL_INFO
-#define CONFIG_CMD_ACCELS
-
-#define CONFIG_MAG_BMI_BMM150
-#define CONFIG_MAG_CALIBRATE
-
+#ifdef BOARD_ASURADA_REV0
+#define CONFIG_ALS
 #define ALS_COUNT 1
 #define CONFIG_ALS_TCS3400
 #define CONFIG_ALS_TCS3400_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS)
 #define CONFIG_ALS_TCS3400_EMULATED_IRQ_EVENT
 
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(CLEAR_ALS)
+#define CONFIG_ACCEL_FORCE_MODE_MASK (BIT(LID_ACCEL) | BIT(CLEAR_ALS))
+#else
+#define CONFIG_ACCEL_LIS2DW12_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
+#endif
 
 /* SPI / Host Command */
 #undef CONFIG_HOSTCMD_DEBUG_MODE
 #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
-#define CONFIG_SPI
-#define CONFIG_SUPPRESSED_HOST_COMMANDS \
-	EC_CMD_CONSOLE_SNAPSHOT, EC_CMD_CONSOLE_READ, EC_CMD_MOTION_SENSE_CMD, \
-	EC_CMD_PD_GET_LOG_ENTRY
-
-/* MKBP */
-#define CONFIG_MKBP_EVENT
-
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
-#define CONFIG_MKBP_USE_GPIO
-
-/* Define the host events which are allowed to wakeup AP in S3. */
-#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK                \
-	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |     \
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) | \
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) /* for DP */)
-
-/* UART */
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
 
 /* USB-A */
-#define CONFIG_USB_PORT_POWER_DUMB
-#define USB_PORT_COUNT 1
-
-/* GPIO name remapping */
-#define GPIO_EN_HDMI_PWR        GPIO_EC_X_GPIO1
-#define GPIO_USB_C1_FRS_EN      GPIO_EC_X_GPIO1
-#define GPIO_USB_C1_PPC_INT_ODL GPIO_X_EC_GPIO2
-#define GPIO_PS185_EC_DP_HPD    GPIO_X_EC_GPIO2
-#define GPIO_USB_C1_DP_IN_HPD   GPIO_EC_X_GPIO3
-#define GPIO_PS185_PWRDN_ODL    GPIO_EC_X_GPIO3
+#define USBA_PORT_COUNT 1
 
-/* Voltage regulator control */
-#define CONFIG_HOSTCMD_REGULATOR
+#ifdef BOARD_HAYATO
+/* Virutal battery optional MFG function */
+#define CONFIG_SMART_BATTERY_OPTIONAL_MFG_FUNC
+#endif
 
 #ifndef __ASSEMBLER__
 
@@ -227,51 +105,38 @@ enum battery_type {
 	BATTERY_TYPE_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_LED1,
-	PWM_CH_LED2,
-	PWM_CH_LED3,
-	PWM_CH_COUNT,
+enum sensor_id {
+	BASE_ACCEL = 0,
+	BASE_GYRO,
+	LID_ACCEL,
+#ifdef BOARD_ASURADA_REV0
+	CLEAR_ALS,
+	RGB_ALS,
+#endif
+	SENSOR_COUNT,
 };
 
 enum adc_channel {
-	ADC_VBUS,                /* ADC 0 */
-	ADC_BOARD_ID_0,          /* ADC 1 */
-	ADC_BOARD_ID_1,          /* ADC 2 */
-	ADC_CHARGER_AMON_R,      /* ADC 3 */
-	ADC_CHARGER_PMON,        /* ADC 6 */
+	ADC_VBUS_C0, /* ADC 0 */
+	ADC_BOARD_ID_0, /* ADC 1 */
+	ADC_BOARD_ID_1, /* ADC 2 */
+	ADC_CHARGER_AMON_R, /* ADC 3 */
+	ADC_VBUS_C1, /* ADC 5 */
+	ADC_CHARGER_PMON, /* ADC 6 */
 
 	/* Number of ADC channels */
 	ADC_CH_COUNT,
 };
 
-enum power_signal {
-	PMIC_PWR_GOOD,
-	AP_IN_S3_L,
-	AP_WDT_ASSERTED,
-	POWER_SIGNAL_COUNT,
-};
-
-enum board_sub_board {
-	SUB_BOARD_NONE = -1,
-	SUB_BOARD_TYPEC,
-	SUB_BOARD_HDMI,
-
-	SUB_BOARD_COUNT,
-};
-
-enum sensor_id {
-	BASE_ACCEL = 0,
-	BASE_GYRO,
-	BASE_MAG,
-	LID_ACCEL,
-	CLEAR_ALS,
-	RGB_ALS,
-	SENSOR_COUNT,
+enum pwm_channel {
+	PWM_CH_LED1,
+	PWM_CH_LED2,
+	PWM_CH_LED3,
+	PWM_CH_COUNT,
 };
 
-void board_reset_pd_mcu(void);
-int board_get_version(void);
+int board_accel_force_mode_mask(void);
+void motion_interrupt(enum gpio_signal signal);
 
 #endif /* !__ASSEMBLER__ */
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/asurada/board_id.c b/board/asurada/board_id.c
deleted file mode 100644
index f57863e03b..0000000000
--- a/board/asurada/board_id.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <adc.h>
-#include <common.h>
-#include <console.h>
-#include <gpio.h>
-#include <timer.h>
-#include <util.h>
-
-/**
- * Conversion based on following table:
- *
- * ID | Rp   | Rd   | Voltage
- *    | kOhm | kOhm | mV
- * ---+------+------+--------
- *  0 | 51.1 |  2.2 | 136.2
- *  1 | 51.1 | 6.81 | 388.1
- *  2 | 51.1 |   11 | 584.5
- *  3 | 57.6 |   18 | 785.7
- *  4 | 51.1 |   22 | 993.2
- *  5 | 51.1 |   30 | 1220.7
- *  6 | 51.1 | 39.2 | 1432.6
- *  7 |   56 |   56 | 1650.0
- *  8 |   47 | 61.9 | 1875.8
- *  9 |   47 | 80.6 | 2084.5
- * 10 |   56 |  124 | 2273.3
- * 11 | 51.1 |  150 | 2461.5
- * 12 |   47 |  200 | 2672.1
- * 13 |   47 |  330 | 2888.6
- * 14 |   47 |  680 | 3086.7
- */
-const static int voltage_map[] = {
-	136,
-	388,
-	584,
-	785,
-	993,
-	1220,
-	1432,
-	1650,
-	1875,
-	2084,
-	2273,
-	2461,
-	2672,
-	2888,
-	3086,
-};
-
-const int threshold_mv = 100;
-
-/**
- * Convert ADC value to board id using the voltage table above.
- *
- * @param ch	ADC channel to read, usually ADC_BOARD_ID_0 or ADC_BOARD_ID_1.
- *
- * @return	a non-negative board id, or negative value if error.
- */
-static int adc_value_to_numeric_id(enum adc_channel ch)
-{
-	int mv;
-
-	gpio_set_level(GPIO_EN_EC_ID_ODL, 0);
-	/* Wait to allow cap charge */
-	msleep(10);
-
-	mv = adc_read_channel(ch);
-	if (mv == ADC_READ_ERROR)
-		mv = adc_read_channel(ch);
-
-	gpio_set_level(GPIO_EN_EC_ID_ODL, 1);
-
-	if (mv == ADC_READ_ERROR)
-		return -EC_ERROR_UNKNOWN;
-
-	for (int i = 0; i < ARRAY_SIZE(voltage_map); i++) {
-		if (IN_RANGE(mv, voltage_map[i] - threshold_mv,
-			     voltage_map[i] + threshold_mv))
-			return i;
-	}
-
-	return -EC_ERROR_UNKNOWN;
-}
-
-int board_get_version(void)
-{
-	static int version = -1;
-
-	if (version >= 0)
-		return version;
-
-	version = adc_value_to_numeric_id(ADC_BOARD_ID_0);
-	if (version < 0) {
-		ccprints("WARNING: failed to read ADC_BOARD_ID_0");
-		ccprints("Assuming board id = 0");
-
-		version = 0;
-	}
-
-	return version;
-}
diff --git a/board/asurada/build.mk b/board/asurada/build.mk
index 33f069093d..72015fba95 100644
--- a/board/asurada/build.mk
+++ b/board/asurada/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -8,6 +8,10 @@
 # the IC is ITE IT8xxx2
 CHIP:=it83xx
 CHIP_FAMILY:=it8xxx2
-CHIP_VARIANT:=it81202ax_1024
+CHIP_VARIANT:=it81202bx_1024
+BASEBOARD:=asurada
 
-board-y=battery.o board.o board_id.o led.o usb_pd_policy.o
+board-$(BOARD_HAYATO)=led_hayato.o
+board-$(BOARD_ASURADA)=led.o
+board-y+=battery.o board.o
+board-y+=usbc_config.o
diff --git a/board/asurada/ec.tasklist b/board/asurada/ec.tasklist
index ff47718bae..c8e234a412 100644
--- a/board/asurada/ec.tasklist
+++ b/board/asurada/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/asurada/gpio.inc b/board/asurada/gpio.inc
index 02458ec518..46700a7749 100644
--- a/board/asurada/gpio.inc
+++ b/board/asurada/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -30,11 +30,15 @@ GPIO_INT(PMIC_EC_PWRGD, PIN(F, 3),
 
 /* Sensor Interrupts */
 GPIO_INT(BASE_IMU_INT_L,     PIN(J, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V,
-         bmi160_interrupt)
+         motion_interrupt)
 GPIO_INT(LID_ACCEL_INT_L,    PIN(J, 3), GPIO_INT_FALLING | GPIO_SEL_1P8V,
          lis2dw12_interrupt)
+#ifdef BOARD_ASURADA_REV0
 GPIO_INT(ALS_RGB_INT_ODL,    PIN(F, 0), GPIO_INT_FALLING,
          tcs3400_interrupt)
+#else
+GPIO(ALS_RGB_INT_ODL,        PIN(F, 0), GPIO_INPUT)
+#endif
 
 /* USB-C interrupts */
 GPIO_INT(USB_C0_PPC_INT_ODL, PIN(D, 1), GPIO_INT_BOTH, ppc_interrupt)
@@ -49,7 +53,9 @@ GPIO_INT(VOLUME_UP_L,        PIN(D, 6), GPIO_INT_BOTH | GPIO_PULL_UP,
          button_interrupt) /* EC_VOLUP_BTN_ODL */
 
 /* Other interrupts */
-#ifdef BOARD_ASURADA
+GPIO_INT(AP_XHCI_INIT_DONE,  PIN(D, 2), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V,
+         usb_a0_interrupt)
+#ifdef BOARD_ASURADA_REV0
 GPIO_INT(AC_PRESENT,         PIN(M, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,
          extpower_interrupt) /* AC_OK / AC_PRESENT in rev0 */
 #else /* HAYATO */
@@ -58,7 +64,7 @@ GPIO_INT(AC_PRESENT,         PIN(E, 5), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,
 #endif
 GPIO_INT(UART1_RX,           PIN(B, 0), GPIO_INT_FALLING,
          uart_deepsleep_interrupt) /* UART_DEBUG_TX_EC_RX */
-GPIO_INT(WP,                 PIN(I, 4), GPIO_INT_BOTH,
+GPIO_INT(WP,                 PIN(I, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V,
          switch_interrupt) /* EC_FLASH_WP_OD */
 GPIO_INT(SPI0_CS,            PIN(M, 5), GPIO_INT_FALLING,
          spi_event)        /* SPI slave Chip Select -- AP_SPI_EC_CS_L */
@@ -73,14 +79,14 @@ GPIO(PG_MT6360_ODL,          PIN(F, 1), GPIO_INPUT)
 GPIO(PG_PP5000_A_ODL,        PIN(A, 6), GPIO_INPUT)
 GPIO(EN_SLP_Z,               PIN(E, 3), GPIO_OUT_LOW)
 GPIO(SYS_RST_ODL,            PIN(B, 6), GPIO_ODR_LOW)
-GPIO(EC_BL_EN_OD,            PIN(B, 5), GPIO_ODR_LOW)
+GPIO(EC_BL_EN_OD,            PIN(B, 5), GPIO_ODR_LOW | GPIO_SEL_1P8V)
 
 /* MKBP event synchronization */
-GPIO(EC_INT_L,               PIN(E, 6), GPIO_ODR_HIGH) /* EC_AP_INT_ODL */
+GPIO(EC_INT_L,               PIN(E, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V) /* EC_AP_INT_ODL */
 
 /* USB and USBC Signals */
 GPIO(DP_AUX_PATH_SEL,        PIN(G, 0), GPIO_OUT_HIGH)
-GPIO(EC_DPBRDG_HPD_ODL,      PIN(J, 0), GPIO_ODR_HIGH)
+GPIO(EC_DPBRDG_HPD_ODL,      PIN(J, 0), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
 GPIO(EN_PP5000_USB_A0_VBUS,  PIN(B, 7), GPIO_OUT_LOW)
 GPIO(USB_C0_FRS_EN,          PIN(H, 3), GPIO_OUT_LOW)
 
@@ -89,13 +95,13 @@ GPIO(EC_BATT_PRES_ODL,       PIN(C, 0), GPIO_INPUT)
 GPIO(BC12_DET_EN,            PIN(J, 5), GPIO_OUT_LOW) /* EN_USB_C0_BC12_DET */
 GPIO(EN_EC_ID_ODL,           PIN(H, 5), GPIO_ODR_LOW)
 GPIO(ENTERING_RW,            PIN(C, 5), GPIO_OUT_LOW) /* EC_ENTERING_RW */
-GPIO(EC_USB_C0_MUX_RESET_L,  PIN(D, 7), GPIO_OUT_HIGH)
+GPIO(EN_5V_USM,              PIN(D, 7), GPIO_OUT_LOW)
 
 /* I2C pins - Alternate function below configures I2C module on these pins */
 GPIO(I2C_A_SCL,              PIN(B, 3), GPIO_INPUT) /* I2C_CHG_BATT_SCL */
 GPIO(I2C_A_SDA,              PIN(B, 4), GPIO_INPUT) /* I2C_CHG_BATT_SDA */
-GPIO(I2C_B_SCL,              PIN(C, 1), GPIO_INPUT) /* I2C_SENSOR_SCL */
-GPIO(I2C_B_SDA,              PIN(C, 2), GPIO_INPUT) /* I2C_SENSOR_SDA */
+GPIO(I2C_B_SCL,              PIN(C, 1), GPIO_INPUT | GPIO_SEL_1P8V) /* I2C_SENSOR_SCL */
+GPIO(I2C_B_SDA,              PIN(C, 2), GPIO_INPUT | GPIO_SEL_1P8V) /* I2C_SENSOR_SDA */
 GPIO(I2C_C_SCL,              PIN(F, 6), GPIO_INPUT) /* I2C_USB_C0_SCL */
 GPIO(I2C_C_SDA,              PIN(F, 7), GPIO_INPUT) /* I2C_USB_C0_SCL */
 GPIO(I2C_E_SCL,              PIN(E, 0), GPIO_INPUT) /* I2C_USB_C1_SCL */
@@ -113,7 +119,7 @@ GPIO(EC_X_GPIO3,             PIN(J, 1), GPIO_INPUT)
 
 /* Alternate functions GPIO definitions */
 ALTERNATE(PIN_MASK(B, 0x18), 1, MODULE_I2C, 0) /* I2C A */
-ALTERNATE(PIN_MASK(C, 0x06), 1, MODULE_I2C, 0) /* I2C B */
+ALTERNATE(PIN_MASK(C, 0x06), 1, MODULE_I2C, GPIO_SEL_1P8V) /* I2C B */
 ALTERNATE(PIN_MASK(F, 0xC0), 1, MODULE_I2C, 0) /* I2C C */
 ALTERNATE(PIN_MASK(E, 0x81), 1, MODULE_I2C, 0) /* I2C E */
 
@@ -124,31 +130,41 @@ ALTERNATE(PIN_MASK(B, 0x03), 1, MODULE_UART, 0) /* EC to Servo */
 ALTERNATE(PIN_MASK(A, 0x07), 1, MODULE_PWM, 0) /* PWM 0~2 */
 
 /* ADC */
-ALTERNATE(PIN_MASK(I, 0x4F), 0, MODULE_ADC, 0) /* ADC 0,1,2,3,6 */
+ALTERNATE(PIN_MASK(I, 0x6F), 0, MODULE_ADC, 0) /* ADC 0,1,2,3,5,6 */
 
 /* SPI */
 ALTERNATE(PIN_MASK(M, 0x33), 0, MODULE_SPI, 0) /* SPI */
 
-/* Power Switch Logic (PSL) inputs */
-GPIO(EC_RST_ODL,             PIN(L, 1), GPIO_INPUT)
-
 /* Unimplemented Pins  */
-UNIMPLEMENTED(PCH_SMI_L)
-UNIMPLEMENTED(PCH_SCI_L)
-UNIMPLEMENTED(PCH_WAKE_L)
-UNIMPLEMENTED(PCH_PLTRST_L)
-
-#define UNIMPLEMENTED_GPIO(name, pin) UNIMPLEMENTED(name)
-
-UNIMPLEMENTED_GPIO(SET_VMC_VOLT_AT_1V8,    PIN(D, 4))
-UNIMPLEMENTED_GPIO(EN_PP3000_VMC_PMU,      PIN(D, 2))
-UNIMPLEMENTED_GPIO(PACKET_MODE_EN,         PIN(A, 3))
+GPIO(SET_VMC_VOLT_AT_1V8,    PIN(D, 4), GPIO_INPUT | GPIO_PULL_DOWN | GPIO_SEL_1P8V)
+GPIO(PACKET_MODE_EN,         PIN(A, 3), GPIO_INPUT | GPIO_PULL_DOWN)
 /* b/160218054: behavior not defined */
-UNIMPLEMENTED_GPIO(USB_A0_FAULT_ODL,       PIN(A, 7))
-UNIMPLEMENTED_GPIO(CHARGER_PROCHOT_ODL,    PIN(C, 3))
-UNIMPLEMENTED_GPIO(PG_MT6315_GPU_ODL,      PIN(H, 6))
-UNIMPLEMENTED_GPIO(EN_PP3000_SD_U,         PIN(G, 1))
+/* *_ODL pin has external pullup so don't pull it down. */
+GPIO(USB_A0_FAULT_ODL,       PIN(A, 7), GPIO_INPUT)
+GPIO(CHARGER_PROCHOT_ODL,    PIN(C, 3), GPIO_INPUT)
+GPIO(PG_MT6315_GPU_ODL,      PIN(H, 6), GPIO_INPUT)
+GPIO(EN_PP3000_SD_U,         PIN(G, 1), GPIO_INPUT | GPIO_PULL_DOWN | GPIO_SEL_1P8V)
 /* reserved for future use */
-UNIMPLEMENTED_GPIO(CCD_MODE_ODL,           PIN(C, 4))
-
-#undef UNIMPLEMENTED_GPIO
+GPIO(CCD_MODE_ODL,           PIN(C, 4), GPIO_INPUT)
+/*
+ * ADC pins don't have internal pull-down capability,
+ * so we set them as output low.
+ */
+GPIO(NC_GPI7,                PIN(I, 7), GPIO_OUT_LOW)
+/* NC pins, enable internal pull-up/down to avoid floating state. */
+#ifdef BOARD_ASURADA_REV0
+GPIO(NC_GPE5,                PIN(E, 5), GPIO_INPUT | GPIO_PULL_UP)
+#else /* HAYATO */
+GPIO(NC_GPM2,                PIN(M, 2), GPIO_INPUT | GPIO_PULL_DOWN)
+#endif
+GPIO(NC_GPM3,                PIN(M, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(NC_GPM6,                PIN(M, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(SPI_CLK_GPG6,           PIN(G, 6), GPIO_INPUT | GPIO_PULL_UP)
+/*
+ * These 4 pins don't have internal pull-down capability,
+ * so we set them as output low.
+ */
+GPIO(NC_GPG3,                PIN(G, 3), GPIO_OUT_LOW)
+GPIO(SPI_MOSI_GPG4,          PIN(G, 4), GPIO_OUT_LOW)
+GPIO(SPI_MISO_GPG5,          PIN(G, 5), GPIO_OUT_LOW)
+GPIO(SPI_CS_GPG7,            PIN(G, 7), GPIO_OUT_LOW)
diff --git a/board/asurada/led.c b/board/asurada/led.c
index 166ece92e9..96093cd8a9 100644
--- a/board/asurada/led.c
+++ b/board/asurada/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -15,18 +15,16 @@
 #include "stdbool.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_PWM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_PWM, format, ##args)
 
 #define LED_OFF EC_LED_COLOR_COUNT
 
 const enum ec_led_id supported_led_ids[] = {
 	/* Main LED */
-	EC_LED_ID_LEFT_LED,
-	EC_LED_ID_RIGHT_LED,
+	EC_LED_ID_LEFT_LED, EC_LED_ID_RIGHT_LED,
 
 	/* Not used, give them some random name for testing */
-	EC_LED_ID_POWER_LED,
-	EC_LED_ID_BATTERY_LED
+	EC_LED_ID_POWER_LED, EC_LED_ID_BATTERY_LED
 };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -85,8 +83,7 @@ static void led_set_color_battery(enum ec_led_colors color, int duty)
 }
 
 static enum ec_error_list set_color(enum ec_led_id led_id,
-				    enum ec_led_colors color,
-				    int duty)
+				    enum ec_led_colors color, int duty)
 {
 	switch (led_id) {
 	case EC_LED_ID_LEFT_LED:
@@ -146,13 +143,13 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 static void update_led(enum ec_led_id led_id, bool is_active_charge_port,
 		       int duty, int tick)
 {
-	enum charge_state power_state = charge_get_state();
+	enum led_pwr_state power_state = led_pwr_get_state();
 
-	if (power_state == PWR_STATE_IDLE) {
+	if (power_state == LED_PWRS_IDLE) {
 		/* Factory mode: blinking white (2sec on + 2sec off) */
 		set_color(led_id, (tick % 8 < 4) ? EC_LED_COLOR_WHITE : LED_OFF,
 			  duty);
-	} else if (power_state == PWR_STATE_ERROR) {
+	} else if (power_state == LED_PWRS_ERROR) {
 		/* Battery error: blinking amber (1sec on + 1sec off) */
 		set_color(led_id, (tick % 4 < 2) ? EC_LED_COLOR_AMBER : LED_OFF,
 			  duty);
@@ -161,7 +158,7 @@ static void update_led(enum ec_led_id led_id, bool is_active_charge_port,
 		 * Active charge port: amber when charging, white if fully
 		 * charged.
 		 */
-		if (power_state == PWR_STATE_CHARGE)
+		if (power_state == LED_PWRS_CHARGE)
 			set_color(led_id, EC_LED_COLOR_AMBER, duty);
 		else
 			set_color(led_id, EC_LED_COLOR_WHITE, duty);
@@ -174,13 +171,11 @@ static void update_led(enum ec_led_id led_id, bool is_active_charge_port,
 		if (chipset_in_state(CHIPSET_STATE_ON))
 			set_color(led_id, EC_LED_COLOR_WHITE, duty);
 		else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-			set_color(
-				led_id,
-				(tick % 8 < 6) ? EC_LED_COLOR_AMBER : LED_OFF,
-				duty);
+			set_color(led_id,
+				  (tick % 8 < 6) ? EC_LED_COLOR_AMBER : LED_OFF,
+				  duty);
 		else
 			set_color(led_id, LED_OFF, 0);
-
 	}
 }
 
diff --git a/board/asurada/led_hayato.c b/board/asurada/led_hayato.c
new file mode 100644
index 0000000000..2243895257
--- /dev/null
+++ b/board/asurada/led_hayato.c
@@ -0,0 +1,129 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "chipset.h"
+#include "driver/bc12/mt6360.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+
+__override const int led_charge_lvl_1 = 5;
+__override const int led_charge_lvl_2 = 95;
+
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
+
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    1 * LED_ONE_SEC },
+						  { LED_OFF,
+						    3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_BATTERY_LED,
+	EC_LED_ID_POWER_LED,
+};
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	mt6360_led_set_brightness(MT6360_LED_RGB2, 50);
+	mt6360_led_set_brightness(MT6360_LED_RGB3, 50);
+
+	switch (color) {
+	case EC_LED_COLOR_AMBER:
+		mt6360_led_enable(MT6360_LED_RGB2, 0);
+		mt6360_led_enable(MT6360_LED_RGB3, 1);
+		break;
+	case EC_LED_COLOR_WHITE:
+		mt6360_led_enable(MT6360_LED_RGB2, 1);
+		mt6360_led_enable(MT6360_LED_RGB3, 0);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		mt6360_led_enable(MT6360_LED_RGB2, 0);
+		mt6360_led_enable(MT6360_LED_RGB3, 0);
+		break;
+	}
+}
+
+__override void led_set_color_power(enum ec_led_colors color)
+{
+	mt6360_led_set_brightness(MT6360_LED_RGB1, 1);
+	mt6360_led_enable(MT6360_LED_RGB1, color == EC_LED_COLOR_WHITE);
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_AMBER] =
+			MT6360_LED_BRIGHTNESS_MAX;
+		brightness_range[EC_LED_COLOR_WHITE] =
+			MT6360_LED_BRIGHTNESS_MAX;
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		brightness_range[EC_LED_COLOR_WHITE] =
+			MT6360_LED_BRIGHTNESS_MAX;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(EC_LED_COLOR_AMBER);
+		else if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_battery(EC_LED_COLOR_WHITE);
+		else
+			led_set_color_battery(LED_OFF);
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_power(EC_LED_COLOR_WHITE);
+		else
+			led_set_color_power(LED_OFF);
+	}
+
+	return EC_SUCCESS;
+}
+
+__override enum led_states board_led_get_state(enum led_states desired_state)
+{
+	if (desired_state == STATE_BATTERY_ERROR) {
+		if (chipset_in_state(CHIPSET_STATE_ON))
+			return desired_state;
+		else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
+			return STATE_DISCHARGE_S3;
+		else
+			return STATE_DISCHARGE_S5;
+	}
+	return desired_state;
+}
diff --git a/board/asurada/usb_pd_policy.c b/board/asurada/usb_pd_policy.c
deleted file mode 100644
index 8cc8b0a922..0000000000
--- a/board/asurada/usb_pd_policy.c
+++ /dev/null
@@ -1,230 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#include "charge_manager.h"
-#include "chipset.h"
-#include "timer.h"
-#include "usb_dp_alt_mode.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usbc_ppc.h"
-
-#ifndef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-#error Asurada reference must define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-#endif
-
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-
-/* The port that the aux channel is on. */
-static enum {
-	AUX_PORT_NONE = -1,
-	AUX_PORT_C0 = 0,
-	AUX_PORT_C1HDMI = 1,
-} aux_port = AUX_PORT_NONE;
-
-int svdm_get_hpd_gpio(int port)
-{
-	/* HPD is low active, inverse the result */
-	return !gpio_get_level(GPIO_EC_DPBRDG_HPD_ODL);
-}
-
-void svdm_set_hpd_gpio(int port, int en)
-{
-	/*
-	 * HPD is low active, inverse the en
-	 * TODO: C0&C1 shares the same HPD, implement FCFS policy.
-	 */
-	gpio_set_level(GPIO_EC_DPBRDG_HPD_ODL, !en);
-}
-
-static void aux_switch_port(int port)
-{
-	if (port != AUX_PORT_NONE)
-		gpio_set_level_verbose(CC_USBPD, GPIO_DP_AUX_PATH_SEL, port);
-	aux_port = port;
-}
-
-static void aux_display_disconnected(int port)
-{
-	/* Gets the other port. C0 -> C1, C1 -> C0. */
-	int other_port = !port;
-
-	/* If the current port is not the aux port, nothing needs to be done. */
-	if (aux_port != port)
-		return;
-
-	/* If the other port is connected to a external display, switch aux. */
-	if (dp_status[other_port] & DP_FLAGS_DP_ON)
-		aux_switch_port(other_port);
-	else
-		aux_switch_port(AUX_PORT_NONE);
-}
-
-__override int svdm_dp_attention(int port, uint32_t *payload)
-{
-	int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]);
-	int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]);
-#ifdef CONFIG_USB_PD_DP_HPD_GPIO
-	int cur_lvl = svdm_get_hpd_gpio(port);
-#endif /* CONFIG_USB_PD_DP_HPD_GPIO */
-
-	dp_status[port] = payload[1];
-
-	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
-	    (irq || lvl))
-		/*
-		 * Wake up the AP.  IRQ or level high indicates a DP sink is now
-		 * present.
-		 */
-		if (IS_ENABLED(CONFIG_MKBP_EVENT))
-			pd_notify_dp_alt_mode_entry();
-
-	/* Its initial DP status message prior to config */
-	if (!(dp_flags[port] & DP_FLAGS_DP_ON)) {
-		if (lvl)
-			dp_flags[port] |= DP_FLAGS_HPD_HI_PENDING;
-		return 1;
-	}
-
-#ifdef CONFIG_USB_PD_DP_HPD_GPIO
-	if (irq && !lvl) {
-		/*
-		 * IRQ can only be generated when the level is high, because
-		 * the IRQ is signaled by a short low pulse from the high level.
-		 */
-		CPRINTF("ERR:HPD:IRQ&LOW\n");
-		return 0; /* nak */
-	}
-
-	if (irq && cur_lvl) {
-		uint64_t now = get_time().val;
-		/* wait for the minimum spacing between IRQ_HPD if needed */
-		if (now < svdm_hpd_deadline[port])
-			usleep(svdm_hpd_deadline[port] - now);
-
-		/* generate IRQ_HPD pulse */
-		svdm_set_hpd_gpio(port, 0);
-		usleep(HPD_DSTREAM_DEBOUNCE_IRQ);
-		svdm_set_hpd_gpio(port, 1);
-	} else {
-		svdm_set_hpd_gpio(port, lvl);
-	}
-
-	/*
-	 * Asurada can only output to 1 display port at a time.
-	 * This implements FCFS policy by changing the aux channel. If a
-	 * display is connected to the either port (says A), and the port A
-	 * will be served until the display is disconnected from port A.
-	 * It won't output to the other display which connects to port B.
-	 */
-	if (lvl && aux_port == AUX_PORT_NONE)
-		/*
-		 * A display is connected, and no display was plugged on either
-		 * port.
-		 */
-		aux_switch_port(port);
-	else if (!lvl)
-		aux_display_disconnected(port);
-
-
-	/* set the minimum time delay (2ms) for the next HPD IRQ */
-	svdm_hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
-#endif /* CONFIG_USB_PD_DP_HPD_GPIO */
-
-	usb_mux_hpd_update(port, lvl, irq);
-
-#ifdef USB_PD_PORT_TCPC_MST
-	if (port == USB_PD_PORT_TCPC_MST)
-		baseboard_mst_enable_control(port, lvl);
-#endif
-
-	/* ack */
-	return 1;
-}
-
-__override void svdm_exit_dp_mode(int port)
-{
-	svdm_safe_dp_mode(port);
-#ifdef CONFIG_USB_PD_DP_HPD_GPIO
-	svdm_set_hpd_gpio(port, 0);
-#endif /* CONFIG_USB_PD_DP_HPD_GPIO */
-	usb_mux_hpd_update(port, 0, 0);
-
-	aux_display_disconnected(port);
-
-#ifdef USB_PD_PORT_TCPC_MST
-	if (port == USB_PD_PORT_TCPC_MST)
-		baseboard_mst_enable_control(port, 0);
-#endif
-#ifdef CONFIG_USB_PD_TCPMV2
-	dp_teardown(port);
-#endif
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return ppc_is_vbus_present(port);
-}
-
-void pd_power_supply_reset(int port)
-{
-	int prev_en;
-
-	prev_en = ppc_is_sourcing_vbus(port);
-
-	/* Disable VBUS. */
-	ppc_vbus_source_enable(port, 0);
-
-	/* Enable discharge if we were previously sourcing 5V */
-	if (prev_en)
-		pd_set_vbus_discharge(port, 1);
-
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	/* Give back the current quota we are no longer using */
-	charge_manager_source_port(port, 0);
-#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_check_vconn_swap(int port)
-{
-	/* TODO: Only allow vconn swap if PP4200_G rail is enabled , s3/s0 on */
-	return 0;
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	int rv;
-
-	/* Disable charging. */
-	rv = ppc_vbus_sink_enable(port, 0);
-	if (rv)
-		return rv;
-
-	pd_set_vbus_discharge(port, 0);
-
-	/* Provide Vbus. */
-	rv = ppc_vbus_source_enable(port, 1);
-	if (rv)
-		return rv;
-
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	/* Ensure we advertise the proper available current quota */
-	charge_manager_source_port(port, 1);
-#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
-
-int board_vbus_source_enabled(int port)
-{
-	return ppc_is_sourcing_vbus(port);
-}
-
diff --git a/board/asurada/usbc_config.c b/board/asurada/usbc_config.c
new file mode 100644
index 0000000000..ba6461b0f8
--- /dev/null
+++ b/board/asurada/usbc_config.c
@@ -0,0 +1,29 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Asurada board-specific USB-C configuration */
+
+#include "driver/ppc/syv682x.h"
+#include "driver/usb_mux/ps8743.h"
+#include "hooks.h"
+
+__override int syv682x_board_is_syv682c(int port)
+{
+	return board_get_version() > 2;
+}
+
+void board_usb_mux_init(void)
+{
+	if (board_get_sub_board() == SUB_BOARD_TYPEC) {
+		ps8743_tune_usb_eq(usb_muxes[1].mux, PS8743_USB_EQ_TX_12_8_DB,
+				   PS8743_USB_EQ_RX_12_8_DB);
+		ps8743_write(usb_muxes[1].mux, PS8743_REG_HS_DET_THRESHOLD,
+			     PS8743_USB_HS_THRESH_NEG_10);
+		ps8743_field_update(usb_muxes[1].mux, PS8743_REG_DCI_CONFIG_2,
+				    PS8743_AUTO_DCI_MODE_MASK,
+				    PS8743_AUTO_DCI_MODE_FORCE_USB);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, board_usb_mux_init, HOOK_PRIO_INIT_I2C + 1);
diff --git a/board/asurada/vif_override.xml b/board/asurada/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/asurada/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/asurada_scp/board.c b/board/asurada_scp/board.c
deleted file mode 100644
index 06b790cd81..0000000000
--- a/board/asurada_scp/board.c
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Asurada SCP configuration */
-
-#include "registers.h"
-
-#include "gpio_list.h"
diff --git a/board/asurada_scp/board.h b/board/asurada_scp/board.h
index 58296e0c23..b70a39d20d 100644
--- a/board/asurada_scp/board.h
+++ b/board/asurada_scp/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,11 +8,7 @@
 #ifndef __CROS_EC_BOARD_H
 #define __CROS_EC_BOARD_H
 
-#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_HOSTCMD) | CC_MASK(CC_IPI)))
-
-#define CONFIG_FLASH_SIZE 0x58000
-#define CONFIG_LTO
-#define CONFIG_UART_CONSOLE 0
+#include "baseboard.h"
 
 /*
  * RW only, no flash
@@ -20,53 +16,18 @@
  * | ROM vectortable, .text, .rodata, .data LMA
  * +-------------------- 0x58000
  * | RAM .bss, .data
- * +-------------------- 0x7BDB0
+ * +-------------------- 0x0ffc00
+ * | Reserved (padding for 1k-alignment)
+ * +-------------------- 0x0ffdb0
  * | IPI shared buffer with AP (288 + 8) * 2
- * +-------------------- 0x7C000
- * | 8KB I-CACHE
- * +-------------------- 0x7E000
- * | 8KB D-CACHE
- * +-------------------- 0x80000
+ * +-------------------- 0x100000
  */
-#define ICACHE_BASE 0x7C000
 #define CONFIG_ROM_BASE 0x0
 #define CONFIG_RAM_BASE 0x58000
 #define CONFIG_ROM_SIZE (CONFIG_RAM_BASE - CONFIG_ROM_BASE)
-#define CONFIG_RAM_SIZE (CONFIG_IPC_SHARED_OBJ_ADDR - CONFIG_RAM_BASE)
-#define CONFIG_CODE_RAM_SIZE CONFIG_RAM_BASE
-#define CONFIG_DATA_RAM_SIZE (ICACHE_BASE - CONFIG_RAM_BASE)
-#define CONFIG_RO_MEM_OFF 0
-
-/* IPI configs */
-#define CONFIG_IPC_SHARED_OBJ_BUF_SIZE 288
-#define CONFIG_IPC_SHARED_OBJ_ADDR                                             \
-	(ICACHE_BASE -                                                         \
-	 (CONFIG_IPC_SHARED_OBJ_BUF_SIZE + 2 * 4 /* int32_t */) * 2)
-#define CONFIG_IPI
-#define CONFIG_RPMSG_NAME_SERVICE
-
-#define SCP_IPI_INIT 0
-#define SCP_IPI_VDEC_H264 1
-#define SCP_IPI_VDEC_VP8 2
-#define SCP_IPI_VDEC_VP9 3
-#define SCP_IPI_VENC_H264 4
-#define SCP_IPI_VENC_VP8 5
-#define SCP_IPI_MDP_INIT 6
-#define SCP_IPI_MDP_DEINIT 7
-#define SCP_IPI_MDP_FRAME 8
-#define SCP_IPI_DIP 9
-#define SCP_IPI_ISP_CMD 10
-#define SCP_IPI_ISP_FRAME 11
-#define SCP_IPI_FD_CMD 12
-#define SCP_IPI_HOST_COMMAND 13
-#define SCP_IPI_COUNT 14
-
-#define IPI_COUNT SCP_IPI_COUNT
-
-#define SCP_IPI_NS_SERVICE 0xFF
+#define CONFIG_RAM_SIZE \
+	((CONFIG_IPC_SHARED_OBJ_ADDR & (~(0x400 - 1))) - CONFIG_RAM_BASE)
 
-#ifndef __ASSEMBLER__
-#include "gpio_signal.h"
-#endif /* !__ASSEMBLER__ */
+#define SCP_FW_END 0x100000
 
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/asurada_scp/build.mk b/board/asurada_scp/build.mk
index 33debd81a6..94efa82a6f 100644
--- a/board/asurada_scp/build.mk
+++ b/board/asurada_scp/build.mk
@@ -1,12 +1,11 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
 # Board specific files build
 #
 
-CHIP:=mt8192_scp
+CHIP:=mt_scp
 CHIP_VARIANT:=mt8192
-
-board-y=board.o
+BASEBOARD:=mtscp-rv32i
diff --git a/board/asurada_scp/ec.tasklist b/board/asurada_scp/ec.tasklist
index a6ea775286..1e43d6d30d 100644
--- a/board/asurada_scp/ec.tasklist
+++ b/board/asurada_scp/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,4 +10,8 @@
 #define CONFIG_TASK_LIST \
 	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
 	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE)
+	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(VDEC_SERVICE, vdec_service_task, NULL, TRENTA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(VDEC_CORE_SERVICE, vdec_core_service_task, NULL, TRENTA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(VENC_SERVICE, venc_service_task, NULL, TRENTA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MDP_SERVICE, mdp_service_task, NULL, TRENTA_TASK_STACK_SIZE)
diff --git a/board/asurada_scp/gpio.inc b/board/asurada_scp/gpio.inc
index 3222a34e08..efc5675875 100644
--- a/board/asurada_scp/gpio.inc
+++ b/board/asurada_scp/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/atlas/battery.c b/board/atlas/battery.c
index fb2fba18be..78b3be16a4 100644
--- a/board/atlas/battery.c
+++ b/board/atlas/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -18,10 +18,10 @@
 #include "i2c.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 /* Shutdown mode parameter to write to manufacturer access register */
-#define SB_SHUTDOWN_DATA	0x0010
+#define SB_SHUTDOWN_DATA 0x0010
 
 enum battery_type {
 	BATTERY_LG,
@@ -52,16 +52,16 @@ static int battery_report_present = 1;
  * limits are given by discharging_min/max_c.
  */
 static const struct battery_info batt_info_lg = {
-	.voltage_max		= TARGET_WITH_MARGIN(8800, 5), /* mV */
-	.voltage_normal		= 7700,
-	.voltage_min		= 6100, /* Add 100mV for charger accuracy */
-	.precharge_current	= 256,	/* mA */
-	.start_charging_min_c	= 0,
-	.start_charging_max_c	= 46,
-	.charging_min_c		= 10,
-	.charging_max_c		= 50,
-	.discharging_min_c	= 0,
-	.discharging_max_c	= 60,
+	.voltage_max = TARGET_WITH_MARGIN(8800, 5), /* mV */
+	.voltage_normal = 7700,
+	.voltage_min = 6100, /* Add 100mV for charger accuracy */
+	.precharge_current = 256, /* mA */
+	.start_charging_min_c = 0,
+	.start_charging_max_c = 46,
+	.charging_min_c = 10,
+	.charging_max_c = 50,
+	.discharging_min_c = 0,
+	.discharging_max_c = 60,
 };
 
 /*
@@ -70,16 +70,16 @@ static const struct battery_info batt_info_lg = {
  * limits are given by discharging_min/max_c.
  */
 static const struct battery_info batt_info_lishen = {
-	.voltage_max		= TARGET_WITH_MARGIN(8800, 5), /* mV */
-	.voltage_normal		= 7700,
-	.voltage_min		= 6100, /* Add 100mV for charger accuracy */
-	.precharge_current	= 256,	/* mA */
-	.start_charging_min_c	= 0,
-	.start_charging_max_c	= 46,
-	.charging_min_c		= 10,
-	.charging_max_c		= 50,
-	.discharging_min_c	= 0,
-	.discharging_max_c	= 60,
+	.voltage_max = TARGET_WITH_MARGIN(8800, 5), /* mV */
+	.voltage_normal = 7700,
+	.voltage_min = 6100, /* Add 100mV for charger accuracy */
+	.precharge_current = 256, /* mA */
+	.start_charging_min_c = 0,
+	.start_charging_max_c = 46,
+	.charging_min_c = 10,
+	.charging_max_c = 50,
+	.discharging_min_c = 0,
+	.discharging_max_c = 60,
 };
 
 static const struct board_batt_params info[] = {
@@ -110,7 +110,7 @@ static int board_get_battery_type(void)
 	if (!battery_manufacturer_name(name, sizeof(name))) {
 		for (i = 0; i < BATTERY_TYPE_COUNT; i++) {
 			if (!strncasecmp(name, info[i].manuf_name,
-					 ARRAY_SIZE(name)-1)) {
+					 ARRAY_SIZE(name) - 1)) {
 				board_battery_type = i;
 				break;
 			}
@@ -139,7 +139,9 @@ DECLARE_HOOK(HOOK_INIT, board_init_battery_type, HOOK_PRIO_INIT_I2C + 1);
 const struct battery_info *battery_get_info(void)
 {
 	return info[board_battery_type == BATTERY_TYPE_COUNT ?
-		    DEFAULT_BATTERY_TYPE : board_battery_type].batt_info;
+			    DEFAULT_BATTERY_TYPE :
+			    board_battery_type]
+		.batt_info;
 }
 
 int board_cut_off_battery(void)
@@ -183,7 +185,7 @@ static int charger_should_discharge_on_ac(struct charge_state_data *curr)
 	 */
 	if (!battery_is_cut_off() &&
 	    !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
-		(curr->batt.status & STATUS_FULLY_CHARGED))
+	    (curr->batt.status & STATUS_FULLY_CHARGED))
 		return 1;
 
 	return 0;
diff --git a/board/atlas/board.c b/board/atlas/board.c
index 0ef9a591da..4ce7f97461 100644
--- a/board/atlas/board.c
+++ b/board/atlas/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,13 +9,13 @@
 #include "bd99992gw.h"
 #include "board_config.h"
 #include "charge_manager.h"
-#include "charger.h"
 #include "charge_state.h"
+#include "charger.h"
 #include "chipset.h"
 #include "console.h"
 #include "driver/als_opt3001.h"
-#include "driver/pmic_bd99992gw.h"
 #include "driver/charger/isl923x.h"
+#include "driver/pmic_bd99992gw.h"
 #include "driver/tcpm/ps8xxx.h"
 #include "driver/tcpm/tcpci.h"
 #include "driver/tcpm/tcpm.h"
@@ -29,10 +29,11 @@
 #include "keyboard_scan.h"
 #include "lid_switch.h"
 #include "motion_sense.h"
-#include "power_button.h"
+#include "panic.h"
 #include "power.h"
-#include "pwm_chip.h"
+#include "power_button.h"
 #include "pwm.h"
+#include "pwm_chip.h"
 #include "spi.h"
 #include "switch.h"
 #include "system.h"
@@ -46,8 +47,8 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
@@ -67,10 +68,11 @@ static void tcpc_alert_event(enum gpio_signal signal)
 	schedule_deferred_pd_interrupt(port);
 }
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /* Keyboard scan. Increase output_settle_us to 80us from default 50us. */
-struct keyboard_scan_config keyscan_config = {
+__override struct keyboard_scan_config keyscan_config = {
 	.output_settle_us = 80,
 	.debounce_down_us = 9 * MSEC,
 	.debounce_up_us = 30 * MSEC,
@@ -85,19 +87,19 @@ struct keyboard_scan_config keyscan_config = {
 
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT]       = { 3, 0, 10000 },
-	[PWM_CH_DB0_LED_BLUE]  = {
-		0, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, 2400 },
-	[PWM_CH_DB0_LED_RED]   = {
-		2, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, 2400 },
-	[PWM_CH_DB0_LED_GREEN] = {
-		6, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, 2400 },
-	[PWM_CH_DB1_LED_BLUE]  = {
-		1, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, 2400 },
-	[PWM_CH_DB1_LED_RED]   = {
-		7, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, 2400 },
-	[PWM_CH_DB1_LED_GREEN] = {
-		5, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, 2400 },
+	[PWM_CH_KBLIGHT] = { 3, 0, 10000 },
+	[PWM_CH_DB0_LED_BLUE] = { 0, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+				  2400 },
+	[PWM_CH_DB0_LED_RED] = { 2, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+				 2400 },
+	[PWM_CH_DB0_LED_GREEN] = { 6, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+				   2400 },
+	[PWM_CH_DB1_LED_BLUE] = { 1, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+				  2400 },
+	[PWM_CH_DB1_LED_RED] = { 7, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+				 2400 },
+	[PWM_CH_DB1_LED_GREEN] = { 5, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+				   2400 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
@@ -114,41 +116,46 @@ const struct adc_t adc_channels[] = {
 	 * Adapter current output or battery charging/discharging current (uV)
 	 * 18x amplification on charger side.
 	 */
-	[ADC_AMON_BMON] = {
-		"AMON_BMON",
-		NPCX_ADC_CH2,
-		ADC_MAX_VOLT*1000/18,
-		ADC_READ_MAX+1,
-		0
-	},
+	[ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH2, ADC_MAX_VOLT * 1000 / 18,
+			    ADC_READ_MAX + 1, 0 },
 	/*
 	 * ISL9238 PSYS output is 1.44 uA/W over 12.4K resistor, to read
 	 * 0.8V @ 45 W, i.e. 56250 uW/mV. Using ADC_MAX_VOLT*56250 and
 	 * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we
 	 * only divide by 2 (enough to avoid precision issues).
 	 */
-	[ADC_PSYS] = {
-		"PSYS",
-		NPCX_ADC_CH3,
-		ADC_MAX_VOLT*56250*2/(ADC_READ_MAX+1),
-		2,
-		0
-	},
+	[ADC_PSYS] = { "PSYS", NPCX_ADC_CH3,
+		       ADC_MAX_VOLT * 56250 * 2 / (ADC_READ_MAX + 1), 2, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* I2C port map */
-const struct i2c_port_t i2c_ports[]  = {
-	{"power",   I2C_PORT_POWER,   100,
-	 GPIO_EC_I2C0_POWER_SCL,      GPIO_EC_I2C0_POWER_SDA},
-	{"tcpc0",   I2C_PORT_TCPC0,   1000,
-	 GPIO_EC_I2C1_USB_C0_SCL,     GPIO_EC_I2C1_USB_C0_SDA},
-	{"tcpc1",   I2C_PORT_TCPC1,   1000,
-	 GPIO_EC_I2C2_USB_C1_SCL,     GPIO_EC_I2C2_USB_C1_SDA},
-	{"sensor",  I2C_PORT_SENSOR,  100,
-	 GPIO_EC_I2C3_SENSOR_3V3_SCL, GPIO_EC_I2C3_SENSOR_3V3_SDA},
-	{"battery", I2C_PORT_BATTERY, 100,
-	 GPIO_EC_I2C4_BATTERY_SCL,    GPIO_EC_I2C4_BATTERY_SDA},
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C0_POWER_SCL,
+	  .sda = GPIO_EC_I2C0_POWER_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C1_USB_C0_SCL,
+	  .sda = GPIO_EC_I2C1_USB_C0_SDA },
+	{ .name = "tcpc1",
+	  .port = I2C_PORT_TCPC1,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C2_USB_C1_SCL,
+	  .sda = GPIO_EC_I2C2_USB_C1_SDA },
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C3_SENSOR_3V3_SCL,
+	  .sda = GPIO_EC_I2C3_SENSOR_3V3_SDA },
+	{ .name = "battery",
+	  .port = I2C_PORT_BATTERY,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C4_BATTERY_SCL,
+	  .sda = GPIO_EC_I2C4_BATTERY_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -187,16 +194,22 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	},
 	{
-		.usb_port = 1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	},
 };
 
@@ -221,9 +234,10 @@ void board_tcpc_init(void)
 	 * HPD pulse to enable video path
 	 */
 	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		usb_mux_hpd_update(port, 0, 0);
+		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
 
 uint16_t tcpc_get_alert_status(void)
 {
@@ -243,16 +257,16 @@ uint16_t tcpc_get_alert_status(void)
 }
 
 const struct temp_sensor_t temp_sensors[] = {
-	{"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0},
+	{ "Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0 },
 	/* BD99992GW temp sensors are only readable in S0 */
-	{"Ambient", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM0},
-	{"Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM1},
-	{"DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM2},
-	{"eMMC", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM3},
+	{ "Ambient", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM0 },
+	{ "Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM1 },
+	{ "DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM2 },
+	{ "eMMC", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM3 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -278,12 +292,12 @@ static void board_report_pmic_fault(const char *str)
 	/* VRFAULT has occurred, print VRFAULT status bits. */
 
 	/* PWRSTAT1 */
-	i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS,
-		  BD99992GW_REG_PWRSTAT1, &pwrstat1);
+	i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, BD99992GW_REG_PWRSTAT1,
+		  &pwrstat1);
 
 	/* PWRSTAT2 */
-	i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS,
-		  BD99992GW_REG_PWRSTAT2, &pwrstat2);
+	i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, BD99992GW_REG_PWRSTAT2,
+		  &pwrstat2);
 
 	CPRINTS("PMIC VRFAULT: %s", str);
 	CPRINTS("PMIC VRFAULT: PWRSTAT1=0x%02x PWRSTAT2=0x%02x", pwrstat1,
@@ -324,8 +338,8 @@ static void board_pmic_disable_slp_s0_vr_decay(void)
 	 * Bits 3:2 (10) - VR set to AUTO on SLP_S0# de-assertion
 	 * Bits 1:0 (10) - VR set to AUTO operating mode
 	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS,
-		   BD99992GW_REG_V18ACNT, 0x2a);
+	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, BD99992GW_REG_V18ACNT,
+		   0x2a);
 
 	/*
 	 * V085ACNT:
@@ -357,8 +371,8 @@ static void board_pmic_enable_slp_s0_vr_decay(void)
 	 * Bits 3:2 (10) - VR set to AUTO on SLP_S0# de-assertion
 	 * Bits 1:0 (10) - VR set to AUTO operating mode
 	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS,
-		   BD99992GW_REG_V18ACNT, 0x6a);
+	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, BD99992GW_REG_V18ACNT,
+		   0x6a);
 
 	/*
 	 * V085ACNT:
@@ -371,8 +385,7 @@ static void board_pmic_enable_slp_s0_vr_decay(void)
 		   BD99992GW_REG_V085ACNT, 0x6a);
 }
 
-__override void power_board_handle_host_sleep_event(
-		enum host_sleep_event state)
+__override void power_board_handle_host_sleep_event(enum host_sleep_event state)
 {
 	if (state == HOST_SLEEP_EVENT_S0IX_SUSPEND)
 		board_pmic_enable_slp_s0_vr_decay();
@@ -491,8 +504,8 @@ int board_set_active_charge_port(int charge_port)
 	int is_real_port = (charge_port >= 0 &&
 			    charge_port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	/* check if we are sourcing VBUS on the port */
-	int is_source = gpio_get_level(charge_port == 0 ?
-			GPIO_USB_C0_5V_EN : GPIO_USB_C1_5V_EN);
+	int is_source = gpio_get_level(charge_port == 0 ? GPIO_USB_C0_5V_EN :
+							  GPIO_USB_C1_5V_EN);
 
 	if (is_real_port && is_source) {
 		CPRINTS("No charging from p%d", charge_port);
@@ -508,48 +521,26 @@ int board_set_active_charge_port(int charge_port)
 	} else {
 		/* Make sure non-charging port is disabled */
 		gpio_set_level(charge_port ? GPIO_EN_USB_C0_CHARGE_L :
-					     GPIO_EN_USB_C1_CHARGE_L, 1);
+					     GPIO_EN_USB_C1_CHARGE_L,
+			       1);
 		/* Enable charging port */
 		gpio_set_level(charge_port ? GPIO_EN_USB_C1_CHARGE_L :
-					     GPIO_EN_USB_C0_CHARGE_L, 0);
+					     GPIO_EN_USB_C0_CHARGE_L,
+			       0);
 	}
 
 	return EC_SUCCESS;
 }
 
-/*
- * Limit the input current to 95% negotiated limit,
- * to account for the charger chip margin.
- */
-
-static int charger_derate(int current)
-{
-	return current * 95 / 100;
-}
-
 static void board_charger_init(void)
 {
-	charger_set_input_current(CHARGER_SOLO, charger_derate
-				  (PD_MAX_CURRENT_MA));
+	charger_set_input_current_limit(
+		CHARGER_SOLO,
+		PD_MAX_CURRENT_MA *
+			(100 - CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT) / 100);
 }
 DECLARE_HOOK(HOOK_INIT, board_charger_init, HOOK_PRIO_DEFAULT);
 
-/**
- * Set the charge limit based upon desired maximum.
- *
- * @param port          Port number.
- * @param supplier      Charge supplier type.
- * @param charge_ma     Desired charge limit (mA).
- * @param charge_mv     Negotiated charge voltage (mV).
- */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_ma = charger_derate(charge_ma);
-	charge_set_input_current_limit(MAX(charge_ma,
-				   CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
-
 static void board_chipset_suspend(void)
 {
 	gpio_set_level(GPIO_KBD_BL_EN, 0);
diff --git a/board/atlas/board.h b/board/atlas/board.h
index 8910d39198..bde6d3e07a 100644
--- a/board/atlas/board.h
+++ b/board/atlas/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,29 +12,27 @@
  * By default, enable all console messages excepted HC, ACPI and event:
  * The sensor stack is generating a lot of activity.
  */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
 #undef CONFIG_HOSTCMD_DEBUG_MODE
 #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
 
 /* EC */
 #define CONFIG_ADC
-#define CONFIG_BOARD_VERSION_CUSTOM
 #define CONFIG_BOARD_FORCE_RESET_PIN
 #define CONFIG_DPTF
 #define CONFIG_FPU
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_CONTROLLER
 #define CONFIG_LID_SWITCH
 #define CONFIG_LOW_POWER_IDLE
 #define CONFIG_LTO
 #define CONFIG_CHIP_PANIC_BACKUP
-#define CONFIG_SOFTWARE_PANIC
 #define CONFIG_PWM
 #define CONFIG_PWM_KBLIGHT
 #define CONFIG_SHA256_UNROLLED
 
 /* Internal SPI flash on NPCX7 */
-#define CONFIG_FLASH_SIZE (512 * 1024) /* It's really 1MB. */
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* It's really 1MB. */
 #define CONFIG_SPI_FLASH_REGS
 #define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
 
@@ -55,10 +53,10 @@
 #define CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET
 #define CONFIG_CHIPSET_RESET_HOOK
 #define CONFIG_CPU_PROCHOT_ACTIVE_LOW
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-#define CONFIG_KEYBOARD_BOARD_CONFIG
+#define CONFIG_HOST_INTERFACE_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
+
 #define CONFIG_KEYBOARD_COL2_INVERTED
 #define CONFIG_KEYBOARD_PROTOCOL_8042
 #define CONFIG_KEYBOARD_REFRESH_ROW3
@@ -66,7 +64,8 @@
 /* Battery */
 #define CONFIG_BATTERY_CUT_OFF
 #define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
-#define CONFIG_BATTERY_LEVEL_NEAR_FULL 95
+#undef CONFIG_BATT_HOST_FULL_FACTOR
+#define CONFIG_BATT_HOST_FULL_FACTOR 95
 #define CONFIG_BATTERY_HW_PRESENT_CUSTOM
 #define CONFIG_BATTERY_PRESENT_CUSTOM
 #define CONFIG_BATTERY_SMART
@@ -79,8 +78,10 @@
 #define CONFIG_CHARGER
 #define CONFIG_CHARGER_ISL9238
 #define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT 512
-#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 2
+#define CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT 512
+#define CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT 512
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 5
 #define CONFIG_CHARGER_PROFILE_OVERRIDE
 #define CONFIG_CHARGER_PSYS
 #define CONFIG_CHARGER_PSYS_READ
@@ -120,7 +121,6 @@
 #define CONFIG_ACCEL_FIFO_SIZE 1024
 /* Depends on how fast the AP boots and typical ODRs. */
 #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-#define CONFIG_ACCEL_INTERRUPTS
 
 /* USB */
 #define CONFIG_USB_PD_ALT_MODE
@@ -150,29 +150,29 @@
 #define CONFIG_USBC_VCONN_SWAP
 
 /* Optional feature to configure npcx chip */
-#define NPCX_UART_MODULE2	1 /* 1:GPIO64/65 as UART */
-#define NPCX_JTAG_MODULE2	0 /* 0:GPIO21/17/16/20 as JTAG */
-#define NPCX_TACH_SEL2		0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
-#define NPCX7_PWM1_SEL		1 /* GPIO C2 is used as PWM1. */
-#define CONFIG_HIBERNATE_PSL	/* Enable PSL pins for wakeup */
+#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART */
+#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 as JTAG */
+#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
+#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */
+#define CONFIG_HIBERNATE_PSL /* Enable PSL pins for wakeup */
 
 /* I2C ports */
-#define I2C_PORT_POWER		NPCX_I2C_PORT0_0	/* pmic/charger */
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT1_0
-#define I2C_PORT_TCPC1		NPCX_I2C_PORT2_0
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT3_0	/* als */
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT4_1
-#define I2C_PORT_GYRO		NPCX_I2C_PORT5_0	/* accel/gyro */
-
-#define I2C_PORT_ACCEL		I2C_PORT_GYRO
-#define I2C_PORT_CHARGER	I2C_PORT_POWER
-#define I2C_PORT_PMIC		I2C_PORT_POWER
-#define I2C_PORT_THERMAL	I2C_PORT_POWER
+#define I2C_PORT_POWER NPCX_I2C_PORT0_0 /* pmic/charger */
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT1_0
+#define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT3_0 /* als */
+#define I2C_PORT_BATTERY NPCX_I2C_PORT4_1
+#define I2C_PORT_GYRO NPCX_I2C_PORT5_0 /* accel/gyro */
+
+#define I2C_PORT_ACCEL I2C_PORT_GYRO
+#define I2C_PORT_CHARGER I2C_PORT_POWER
+#define I2C_PORT_PMIC I2C_PORT_POWER
+#define I2C_PORT_THERMAL I2C_PORT_POWER
 
 /* I2C addresses */
-#define I2C_ADDR_TCPC_FLAGS	0x0B
-#define I2C_ADDR_MP2949_FLAGS	0x20
-#define I2C_ADDR_BD99992_FLAGS	0x30
+#define I2C_ADDR_TCPC_FLAGS 0x0B
+#define I2C_ADDR_MP2949_FLAGS 0x20
+#define I2C_ADDR_BD99992_FLAGS 0x30
 
 #ifndef __ASSEMBLER__
 
@@ -180,11 +180,11 @@
 #include "registers.h"
 
 enum temp_sensor_id {
-	TEMP_SENSOR_BATTERY,	/* BD99956GW TSENSE */
-	TEMP_SENSOR_SYSTHERM0,	/* BD99992GW SYSTHERM0 */
-	TEMP_SENSOR_SYSTHERM1,	/* BD99992GW SYSTHERM1 */
-	TEMP_SENSOR_SYSTHERM2,	/* BD99992GW SYSTHERM2 */
-	TEMP_SENSOR_SYSTHERM3,	/* BD99992GW SYSTHERM3 */
+	TEMP_SENSOR_BATTERY, /* BD99956GW TSENSE */
+	TEMP_SENSOR_SYSTHERM0, /* BD99992GW SYSTHERM0 */
+	TEMP_SENSOR_SYSTHERM1, /* BD99992GW SYSTHERM1 */
+	TEMP_SENSOR_SYSTHERM2, /* BD99992GW SYSTHERM2 */
+	TEMP_SENSOR_SYSTHERM3, /* BD99992GW SYSTHERM3 */
 	TEMP_SENSOR_COUNT
 };
 
@@ -205,29 +205,24 @@ enum sensor_id {
 };
 
 /* LID_ALS needs to be polled */
-#define CONFIG_ACCEL_FORCE_MODE_MASK	BIT(LID_ALS)
+#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ALS)
 
-enum adc_channel {
-	ADC_AMON_BMON,
-	ADC_PSYS,
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_AMON_BMON, ADC_PSYS, ADC_CH_COUNT };
 
 /*
  * delay to turn on the power supply max is ~16ms.
  * delay to turn off the power supply max is about ~180ms.
  */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	250000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* delay to turn on/off vconn */
-#define PD_VCONN_SWAP_DELAY		5000   /* us */
 
 /* Define typical operating power and max power */
-#define PD_OPERATING_POWER_MW		15000
-#define PD_MAX_POWER_MW			60000
-#define PD_MAX_CURRENT_MA		3000
-#define PD_MAX_VOLTAGE_MV		20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Board specific handlers */
 int board_get_version(void);
@@ -240,33 +235,33 @@ void board_reset_pd_mcu(void);
  * vs. names hard-coded in various parts of the EC codebase.
  */
 
-#define GPIO_AC_PRESENT		GPIO_ROP_EC_ACOK
-#define GPIO_BATTERY_PRESENT_L	GPIO_EC_BATT_PRES_L
-#define GPIO_BOARD_VERSION1	GPIO_EC_BRD_ID1
-#define GPIO_BOARD_VERSION2	GPIO_EC_BRD_ID2
-#define GPIO_BOARD_VERSION3	GPIO_EC_BRD_ID3
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_ENTERING_RW	GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2		GPIO_EC_KB_ROW02_INV
-#define GPIO_PCH_ACOK		GPIO_EC_PCH_ACPRESENT
-#define GPIO_PCH_PWRBTN_L	GPIO_EC_PCH_PWR_BTN_L
-#define GPIO_PCH_RSMRST_L	GPIO_RSMRST_L
-#define GPIO_PCH_SLP_SUS_L	GPIO_SLP_SUS_L_PCH
-#define GPIO_PCH_WAKE_L		GPIO_EC_PCH_WAKE_L
-#define GPIO_PMIC_DPWROK	GPIO_ROP_DSW_PWROK_EC
-#define GPIO_PMIC_SLP_SUS_L	GPIO_SLP_SUS_L_PMIC
-#define GPIO_POWER_BUTTON_L	GPIO_MECH_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD	GPIO_ROP_EC_RSMRST_L
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_USB_C0_5V_EN	GPIO_EN_USB_C0_5V_OUT
-#define GPIO_USB_C0_PD_RST_L	GPIO_USB_PD_RST_L
-#define GPIO_USB_C1_5V_EN	GPIO_EN_USB_C1_5V_OUT
-#define GPIO_USB_C1_PD_RST_L	GPIO_USB_PD_RST_L
-#define GPIO_WP_L		GPIO_EC_WP_L
+#define GPIO_AC_PRESENT GPIO_ROP_EC_ACOK
+#define GPIO_BATTERY_PRESENT_L GPIO_EC_BATT_PRES_L
+#define GPIO_BOARD_VERSION1 GPIO_EC_BRD_ID1
+#define GPIO_BOARD_VERSION2 GPIO_EC_BRD_ID2
+#define GPIO_BOARD_VERSION3 GPIO_EC_BRD_ID3
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KB_ROW02_INV
+#define GPIO_PCH_ACOK GPIO_EC_PCH_ACPRESENT
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_L
+#define GPIO_PCH_RSMRST_L GPIO_RSMRST_L
+#define GPIO_PCH_SLP_SUS_L GPIO_SLP_SUS_L_PCH
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_L
+#define GPIO_PMIC_DPWROK GPIO_ROP_DSW_PWROK_EC
+#define GPIO_PMIC_SLP_SUS_L GPIO_SLP_SUS_L_PMIC
+#define GPIO_POWER_BUTTON_L GPIO_MECH_PWR_BTN_ODL
+#define GPIO_PG_EC_RSMRST_ODL GPIO_ROP_EC_RSMRST_L
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_USB_C0_5V_EN GPIO_EN_USB_C0_5V_OUT
+#define GPIO_USB_C0_PD_RST_L GPIO_USB_PD_RST_L
+#define GPIO_USB_C1_5V_EN GPIO_EN_USB_C1_5V_OUT
+#define GPIO_USB_C1_PD_RST_L GPIO_USB_PD_RST_L
+#define GPIO_WP_L GPIO_EC_WP_L
 
 /* ps8751 requires 1ms reset down assertion */
-#define PS8XXX_RST_L_RST_H_DELAY_MS	1
+#define PS8XXX_RST_L_RST_H_DELAY_MS 1
 
-#define ATLAS_REV_FIXED_EC_WP	4
+#define ATLAS_REV_FIXED_EC_WP 4
 
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/atlas/build.mk b/board/atlas/build.mk
index f1619f73cd..b7eeeb0a61 100644
--- a/board/atlas/build.mk
+++ b/board/atlas/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/atlas/ec.tasklist b/board/atlas/ec.tasklist
index 33e3cccb16..b0bf043717 100644
--- a/board/atlas/ec.tasklist
+++ b/board/atlas/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/atlas/gpio.inc b/board/atlas/gpio.inc
index 4ce44cc130..ea76ab8841 100644
--- a/board/atlas/gpio.inc
+++ b/board/atlas/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/atlas/led.c b/board/atlas/led.c
index ec46d9d206..2a297848e3 100644
--- a/board/atlas/led.c
+++ b/board/atlas/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,14 +17,14 @@ const enum ec_led_id supported_led_ids[] = {
 };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-struct pwm_led led_color_map[EC_LED_COLOR_COUNT] = {
-				/* Red, Green, Blue */
-	[EC_LED_COLOR_RED]    = {  70,   0,   0 },
-	[EC_LED_COLOR_GREEN]  = {   0,  35,   0 },
-	[EC_LED_COLOR_BLUE]   = {   0,   0, 100 },
-	[EC_LED_COLOR_YELLOW] = {  55,  15,   0 },
-	[EC_LED_COLOR_WHITE]  = {  62, 100,  31 },
-	[EC_LED_COLOR_AMBER]  = { 100,  31,   0 },
+struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = {
+	/* Red, Green, Blue */
+	[EC_LED_COLOR_RED] = { 70, 0, 0 },
+	[EC_LED_COLOR_GREEN] = { 0, 35, 0 },
+	[EC_LED_COLOR_BLUE] = { 0, 0, 100 },
+	[EC_LED_COLOR_YELLOW] = { 55, 15, 0 },
+	[EC_LED_COLOR_WHITE] = { 62, 100, 31 },
+	[EC_LED_COLOR_AMBER] = { 100, 31, 0 },
 };
 
 /*
diff --git a/board/atlas/usb_pd_policy.c b/board/atlas/usb_pd_policy.c
index cb9a460330..6ade3c0b82 100644
--- a/board/atlas/usb_pd_policy.c
+++ b/board/atlas/usb_pd_policy.c
@@ -1,34 +1,34 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "atomic.h"
-#include "extpower.h"
 #include "charge_manager.h"
 #include "chipset.h"
 #include "common.h"
 #include "console.h"
 #include "driver/tcpm/ps8xxx.h"
+#include "extpower.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "host_command.h"
 #include "registers.h"
 #include "system.h"
 #include "task.h"
-#include "tcpci.h"
+#include "tcpm/tcpci.h"
 #include "timer.h"
-#include "util.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
+#include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT];
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5,
-							TYPEC_RP_1A5};
+static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5,
+							 TYPEC_RP_1A5 };
 
 int board_vbus_source_enabled(int port)
 {
@@ -38,9 +38,9 @@ int board_vbus_source_enabled(int port)
 static void board_vbus_update_source_current(int port)
 {
 	enum gpio_signal gpio_5v_en = port ? GPIO_USB_C1_5V_EN :
-		GPIO_USB_C0_5V_EN;
+					     GPIO_USB_C0_5V_EN;
 	enum gpio_signal gpio_3a_en = port ? GPIO_EN_USB_C1_3A :
-		GPIO_EN_USB_C0_3A;
+					     GPIO_EN_USB_C0_3A;
 
 	/*
 	 * 1.5 vs 3.0 A limit is controlled by a dedicated gpio where
@@ -67,8 +67,8 @@ int pd_snk_is_vbus_provided(int port)
 int pd_set_power_supply_ready(int port)
 {
 	/* Disable charging */
-	gpio_set_level(port ? GPIO_EN_USB_C1_CHARGE_L :
-			      GPIO_EN_USB_C0_CHARGE_L, 1);
+	gpio_set_level(port ? GPIO_EN_USB_C1_CHARGE_L : GPIO_EN_USB_C0_CHARGE_L,
+		       1);
 
 	/* Ensure we advertise the proper available current quota */
 	charge_manager_source_port(port, 1);
@@ -111,15 +111,12 @@ int pd_check_vconn_swap(int port)
 	return gpio_get_level(GPIO_PMIC_SLP_SUS_L);
 }
 
-__override void pd_execute_data_swap(int port,
-				     enum pd_data_role data_role)
+__override void pd_execute_data_swap(int port, enum pd_data_role data_role)
 {
 	/* Only port 0 supports device mode. */
 	if (port != 0)
 		return;
 
-	gpio_set_level(GPIO_USB2_ID,
-		      (data_role == PD_ROLE_UFP) ? 1 : 0);
-	gpio_set_level(GPIO_USB2_VBUSSENSE,
-		      (data_role == PD_ROLE_UFP) ? 1 : 0);
+	gpio_set_level(GPIO_USB2_ID, (data_role == PD_ROLE_UFP) ? 1 : 0);
+	gpio_set_level(GPIO_USB2_VBUSSENSE, (data_role == PD_ROLE_UFP) ? 1 : 0);
 }
diff --git a/board/atlas/vif_override.xml b/board/atlas/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/atlas/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/atlas_ish/board.c b/board/atlas_ish/board.c
deleted file mode 100644
index 066767638c..0000000000
--- a/board/atlas_ish/board.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Atlas ISH board-specific configuration */
-
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "math_util.h"
-#include "task.h"
-#include "uart.h"
-
-#include "gpio_list.h" /* has to be included last */
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-/* I2C port map */
-const struct i2c_port_t i2c_ports[]  = {
-	{"trackpad", I2C_PORT_TP, 1000,
-	GPIO_I2C_PORT_TP_SCL, GPIO_I2C_PORT_TP_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/board/atlas_ish/board.h b/board/atlas_ish/board.h
deleted file mode 100644
index 4e590f033e..0000000000
--- a/board/atlas_ish/board.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Atlas ISH board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/*
- * Allow dangerous commands.
- * TODO: Remove this config before production.
- */
-#define CONFIG_SYSTEM_UNLOCKED
-
-/*
- * By default, enable all console messages except HC, ACPI and event
- * The sensor stack is generating a lot of activity.
- */
-#undef CONFIG_HOSTCMD_DEBUG_MODE
-#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
-
-/* ISH specific*/
-#undef  CONFIG_DEBUG_ASSERT
-#define CONFIG_CLOCK_CRYSTAL
-/* EC */
-#define CONFIG_FLASH_SIZE 0x80000
-#define CONFIG_FPU
-#define CONFIG_I2C
-#define CONFIG_I2C_MASTER
-
-/* HID subsystem */
-#define CONFIG_HID_HECI
-
-/* I2C ports */
-#define I2C_PORT_TP ISH_I2C0
-#define GPIO_I2C_PORT_TP_SCL GPIO_ISH_I2C0_SCL
-#define GPIO_I2C_PORT_TP_SDA GPIO_ISH_I2C0_SDA
-
-/* Undefine unfeatures */
-#undef CONFIG_CMD_HASH
-#undef CONFIG_CMD_I2C_SCAN
-#undef CONFIG_CMD_I2C_XFER
-#undef CONFIG_CMD_KEYBOARD
-#undef CONFIG_CMD_POWER_AP
-#undef CONFIG_CMD_POWERINDEBUG
-#undef CONFIG_CMD_SHMEM
-#undef CONFIG_CMD_TIMERINFO
-#undef CONFIG_EXTPOWER
-#undef CONFIG_KEYBOARD_KSO_BASE
-#undef CONFIG_FLASH
-#undef CONFIG_FMAP
-#undef CONFIG_LID_SWITCH
-#undef CONFIG_SWITCH
-#undef CONFIG_WATCHDOG
-
-/* Modules we want to exclude */
-#undef CONFIG_CMD_ACCELS
-#undef CONFIG_CMD_HASH
-#undef CONFIG_CMD_TEMP_SENSOR
-#undef CONFIG_CMD_TIMERINFO
-#undef CONFIG_ADC
-#undef CONFIG_SHA256
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/atlas_ish/build.mk b/board/atlas_ish/build.mk
deleted file mode 100644
index 9cdcbb2253..0000000000
--- a/board/atlas_ish/build.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-# -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=ish
-CHIP_FAMILY:=ish3
-CHIP_VARIANT:=ish3p0
-
-board-y=board.o
diff --git a/board/atlas_ish/ec.tasklist b/board/atlas_ish/ec.tasklist
deleted file mode 100644
index 15f856131a..0000000000
--- a/board/atlas_ish/ec.tasklist
+++ /dev/null
@@ -1,14 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, HUGE_TASK_STACK_SIZE, 0) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE, 0) \
-	TASK_ALWAYS(HECI_RX, heci_rx_task, NULL, HUGE_TASK_STACK_SIZE, 0) \
-	TASK_ALWAYS(IPC_MNG, ipc_mng_task, NULL, LARGER_TASK_STACK_SIZE, 0)
diff --git a/board/atlas_ish/gpio.inc b/board/atlas_ish/gpio.inc
deleted file mode 100644
index 0ddac6ccbe..0000000000
--- a/board/atlas_ish/gpio.inc
+++ /dev/null
@@ -1,15 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Trackpad interrupt pin */
-/*TODO: touchpad driver is not in gerrit yet, so comment out this for now */
-/*GPIO_INT(TOUCHPAD_INT, PIN(1), GPIO_INT_F_FALLING, touchpad_event)*/
-
-/* Those are used by common code, don't change*/
-UNIMPLEMENTED(ENTERING_RW)
-UNIMPLEMENTED(ISH_I2C0_SDA)
-UNIMPLEMENTED(ISH_I2C0_SCL)
diff --git a/board/aurash/board.c b/board/aurash/board.c
new file mode 100644
index 0000000000..8a0a5218fe
--- /dev/null
+++ b/board/aurash/board.c
@@ -0,0 +1,529 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc.h"
+#include "builtin/assert.h"
+#include "button.h"
+#include "cec.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "chipset.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "driver/cec/bitbang.h"
+#include "driver/tcpm/tcpci.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "power.h"
+#include "power_button.h"
+#include "switch.h"
+#include "throttle_ap.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+/* Console output macros */
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+
+static void power_monitor(void);
+DECLARE_DEFERRED(power_monitor);
+
+/******************************************************************************/
+/* Power on by HDMI/ DP monitor */
+struct monitor_config {
+	enum gpio_signal gpio;
+	uint8_t state;
+};
+
+static struct monitor_config monitors[MONITOR_COUNT] = {
+	[HDMI1_MONITOR] = {
+		.gpio = GPIO_HDMI1_MONITOR_ON,
+		.state = MONITOR_OFF,
+	},
+
+	[HDMI2_MONITOR] = {
+		.gpio = GPIO_HDMI2_MONITOR_ON,
+		.state = MONITOR_OFF,
+	},
+
+	[OPTION_MONITOR] = {
+		.gpio = GPIO_OPTION_MONITOR_ON,
+		.state = MONITOR_OFF,
+	},
+};
+
+/******************************************************************************/
+
+/******************************************************************************/
+/* USB-A charging control */
+
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_PP5000_USBA,
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
+
+/******************************************************************************/
+
+/* CEC ports */
+const struct cec_config_t cec_config[] = {
+	[CEC_PORT_0] = {
+		.drv = &bitbang_cec_drv,
+		.offline_policy = NULL,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(cec_config) == CEC_PORT_COUNT);
+
+int board_set_active_charge_port(int port)
+{
+	CPRINTS("Requested charge port change to %d", port);
+
+	/*
+	 * The charge manager may ask us to switch to no charger if we're
+	 * running off USB-C only but upstream doesn't support PD. It requires
+	 * that we accept this switch otherwise it triggers an assert and EC
+	 * reset; it's not possible to boot the AP anyway, but we want to avoid
+	 * resetting the EC so we can continue to do the "low power" LED blink.
+	 */
+	if (port == CHARGE_PORT_NONE)
+		return EC_SUCCESS;
+
+	if (port < 0 || CHARGE_PORT_COUNT <= port)
+		return EC_ERROR_INVAL;
+
+	if (port == charge_manager_get_active_charge_port())
+		return EC_SUCCESS;
+
+	/* Don't charge from a source port */
+	if (board_vbus_source_enabled(port))
+		return EC_ERROR_INVAL;
+
+	if (!chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
+		int bj_active, bj_requested;
+
+		if (charge_manager_get_active_charge_port() != CHARGE_PORT_NONE)
+			/* Change is only permitted while the system is off */
+			return EC_ERROR_INVAL;
+
+		/*
+		 * Current setting is no charge port but the AP is on, so the
+		 * charge manager is out of sync (probably because we're
+		 * reinitializing after sysjump). Reject requests that aren't
+		 * in sync with our outputs.
+		 */
+		bj_active = !gpio_get_level(GPIO_EN_PPVAR_BJ_ADP_L);
+		bj_requested = port == CHARGE_PORT_BARRELJACK;
+		if (bj_active != bj_requested)
+			return EC_ERROR_INVAL;
+	}
+
+	CPRINTS("New charger p%d", port);
+
+	switch (port) {
+	case CHARGE_PORT_TYPEC0:
+	case CHARGE_PORT_TYPEC1:
+		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 1);
+		break;
+	case CHARGE_PORT_BARRELJACK:
+		/* Make sure BJ adapter is sourcing power */
+		if (gpio_get_level(GPIO_BJ_ADP_PRESENT_ODL))
+			return EC_ERROR_INVAL;
+		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 0);
+		break;
+	default:
+		return EC_ERROR_INVAL;
+	}
+
+	return EC_SUCCESS;
+}
+
+static uint8_t usbc_overcurrent;
+
+/******************************************************************************/
+/*
+ * Barrel jack power supply handling
+ *
+ * EN_PPVAR_BJ_ADP_L must default active to ensure we can power on when the
+ * barrel jack is connected, and the USB-C port can bring the EC up fine in
+ * dead-battery mode. Both the USB-C and barrel jack switches do reverse
+ * protection, so we're safe to turn one on then the other off- but we should
+ * only do that if the system is off since it might still brown out.
+ */
+
+#define ADP_DEBOUNCE_MS 1000 /* Debounce time for BJ plug/unplug */
+/* Debounced connection state of the barrel jack */
+static int8_t adp_connected = -1;
+static void adp_connect_deferred(void)
+{
+	struct charge_port_info pi = { 0 };
+	int connected = !gpio_get_level(GPIO_BJ_ADP_PRESENT_ODL);
+
+	/* Debounce */
+	if (connected == adp_connected)
+		return;
+	if (connected)
+		ec_bj_power(&pi.voltage, &pi.current);
+
+	charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED,
+				     DEDICATED_CHARGE_PORT, &pi);
+	adp_connected = connected;
+}
+DECLARE_DEFERRED(adp_connect_deferred);
+
+/* IRQ for BJ plug/unplug. It shouldn't be called if BJ is the power source. */
+void adp_connect_interrupt(enum gpio_signal signal)
+{
+	hook_call_deferred(&adp_connect_deferred_data, ADP_DEBOUNCE_MS * MSEC);
+}
+
+static void adp_state_init(void)
+{
+	ASSERT(CHARGE_PORT_ENUM_COUNT == CHARGE_PORT_COUNT);
+	/*
+	 * Initialize all charge suppliers to 0. The charge manager waits until
+	 * all ports have reported in before doing anything.
+	 */
+	for (int i = 0; i < CHARGE_PORT_COUNT; i++) {
+		for (int j = 0; j < CHARGE_SUPPLIER_COUNT; j++)
+			charge_manager_update_charge(j, i, NULL);
+	}
+
+	/* Report charge state from the barrel jack. */
+	adp_connect_deferred();
+}
+DECLARE_HOOK(HOOK_INIT, adp_state_init, HOOK_PRIO_INIT_CHARGE_MANAGER + 1);
+
+static void board_init(void)
+{
+	int i;
+
+	gpio_enable_interrupt(GPIO_BJ_ADP_PRESENT_ODL);
+	gpio_enable_interrupt(GPIO_HDMI_CONN_OC_ODL);
+	gpio_enable_interrupt(GPIO_USB_A1_OC_ODL);
+	gpio_enable_interrupt(GPIO_USB_A2_OC_ODL);
+	gpio_enable_interrupt(GPIO_USB_A3_OC_ODL);
+	gpio_enable_interrupt(GPIO_USB_A4_OC_ODL);
+
+	if (ec_cfg_power_on_monitor() == POWER_ON_MONITOR_ENABLE) {
+		/*
+		 * Only enable interrupt when fw_config set it as enable.
+		 */
+		gpio_enable_interrupt(GPIO_HDMI1_MONITOR_ON);
+		gpio_enable_interrupt(GPIO_HDMI2_MONITOR_ON);
+		gpio_enable_interrupt(GPIO_OPTION_MONITOR_ON);
+
+		/*
+		 * Initialize the monitor state to corresponding gpio state.
+		 */
+		for (i = 0; i < MONITOR_COUNT; i++)
+			monitors[i].state = gpio_get_level(monitors[i].gpio);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+void board_overcurrent_event(int port, int is_overcurrented)
+{
+	/* Check that port number is valid. */
+	if ((port < 0) || (port >= CONFIG_USB_PD_PORT_MAX_COUNT))
+		return;
+	usbc_overcurrent = is_overcurrented;
+}
+/*
+ * Power monitoring and management.
+ *
+ * the power budgets are met without letting the system fall into
+ * power deficit (perhaps causing a brownout).
+ *
+ * There are 2 power budgets that need to be managed:
+ * The overall goal is to gracefully manage the power demand so that
+ *  - overall system power as measured on the main power supply rail.
+ *  - 5V power delivered to the USB and HDMI ports.
+ *
+ * The actual system power demand is calculated from the VBUS voltage and
+ * the input current (read from a shunt), averaged over 5 readings.
+ * The power budget limit is from the charge manager.
+ *
+ * The 5V power cannot be read directly. Instead, we rely on overcurrent
+ * inputs from the USB and HDMI ports to indicate that the port is in use
+ * (and drawing maximum power).
+ *
+ * There are 3 throttles that can be applied (in priority order):
+ *
+ *  - Type A BC1.2 front port restriction (3W)
+ *  - Type A BC1.2 rear port restriction (3W)
+ *  - Type C PD (throttle to 1.5A if sourcing)
+ *  - Turn on PROCHOT, which immediately throttles the CPU.
+ *
+ *  The first 3 throttles affect both the system power and the 5V rails.
+ *  The third is a last resort to force an immediate CPU throttle to
+ *  reduce the overall power use.
+ *
+ *  The strategy is to determine what the state of the throttles should be,
+ *  and to then turn throttles off or on as needed to match this.
+ *
+ *  This function runs on demand, or every 2 ms when the CPU is up,
+ *  and continually monitors the power usage, applying the
+ *  throttles when necessary.
+ *
+ *  All measurements are in milliwatts.
+ */
+#define THROT_TYPE_A_FRONT BIT(0)
+#define THROT_TYPE_A_REAR BIT(1)
+#define THROT_TYPE_C0 BIT(2)
+#define THROT_TYPE_C1 BIT(3)
+#define THROT_PROCHOT BIT(5)
+
+/*
+ * Power gain if front USB A ports are limited.
+ */
+#define POWER_GAIN_TYPE_A 3200
+/*
+ * Power gain if Type C port is limited.
+ */
+#define POWER_GAIN_TYPE_C 8800
+/*
+ * Power is averaged over 10 ms, with a reading every 2 ms.
+ */
+#define POWER_DELAY_MS 2
+#define POWER_READINGS (10 / POWER_DELAY_MS)
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+static void power_monitor(void)
+{
+	static uint32_t current_state;
+	static uint32_t history[POWER_READINGS];
+	static uint8_t index;
+	int32_t delay;
+	uint32_t new_state = 0, diff;
+
+	/*
+	 * If CPU is off or suspended, no need to throttle
+	 * or restrict power.
+	 */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF | CHIPSET_STATE_SUSPEND)) {
+		/*
+		 * Slow down monitoring, assume no throttling required.
+		 */
+		delay = 20 * MSEC;
+		/*
+		 * Clear the first entry of the power table so that
+		 * it is re-initilalised when the CPU starts.
+		 */
+		history[0] = 0;
+	} else {
+		int32_t charger_mw;
+
+		delay = POWER_DELAY_MS * MSEC;
+		/*
+		 * Get current charger limit (in mw).
+		 * If not configured yet, skip.
+		 */
+		charger_mw = charge_manager_get_power_limit_uw() / 1000;
+		if (charger_mw != 0) {
+			int32_t gap, total, max, power;
+			int i;
+
+			/*
+			 * Read power usage.
+			 */
+			power = (adc_read_channel(ADC_VBUS) *
+				 adc_read_channel(ADC_PPVAR_IMON)) /
+				1000;
+			/* Init power table */
+			if (history[0] == 0) {
+				for (i = 0; i < POWER_READINGS; i++)
+					history[i] = power;
+			}
+			/*
+			 * Update the power readings and
+			 * calculate the average and max.
+			 */
+			history[index] = power;
+			index = (index + 1) % POWER_READINGS;
+			total = 0;
+			max = history[0];
+			for (i = 0; i < POWER_READINGS; i++) {
+				total += history[i];
+				if (history[i] > max)
+					max = history[i];
+			}
+			/*
+			 * For Type-C power supplies, there is
+			 * less tolerance for exceeding the rating,
+			 * so use the max power that has been measured
+			 * over the measuring period.
+			 * For barrel-jack supplies, the rating can be
+			 * exceeded briefly, so use the average.
+			 */
+			if (charge_manager_get_supplier() == CHARGE_SUPPLIER_PD)
+				power = max;
+			else
+				power = total / POWER_READINGS;
+			/*
+			 * Calculate gap, and if negative, power
+			 * demand is exceeding configured power budget, so
+			 * throttling is required to reduce the demand.
+			 */
+			gap = charger_mw - power;
+			/*
+			 * Limiting type-A power rear ports.
+			 */
+			if (gap <= 0) {
+				new_state |= THROT_TYPE_A_REAR;
+				if (!(current_state & THROT_TYPE_A_REAR))
+					gap += POWER_GAIN_TYPE_A;
+			}
+			/*
+			 * Limiting type-A power front ports.
+			 */
+			if (gap <= 0) {
+				new_state |= THROT_TYPE_A_FRONT;
+				if (!(current_state & THROT_TYPE_A_FRONT))
+					gap += POWER_GAIN_TYPE_A;
+			}
+			/*
+			 * If the type-C port is sourcing power,
+			 * check whether it should be throttled.
+			 */
+			if (ppc_is_sourcing_vbus(0) && gap <= 0) {
+				new_state |= THROT_TYPE_C0;
+				if (!(current_state & THROT_TYPE_C0))
+					gap += POWER_GAIN_TYPE_C;
+			}
+			/*
+			 * If the type-C port is sourcing power,
+			 * check whether it should be throttled.
+			 */
+			if (ppc_is_sourcing_vbus(1) && gap <= 0) {
+				new_state |= THROT_TYPE_C1;
+				if (!(current_state & THROT_TYPE_C1))
+					gap += POWER_GAIN_TYPE_C;
+			}
+			/*
+			 * As a last resort, turn on PROCHOT to
+			 * throttle the CPU.
+			 */
+			if (gap <= 0)
+				new_state |= THROT_PROCHOT;
+		}
+	}
+	/*
+	 * Turn the throttles on or off if they have changed.
+	 */
+	diff = new_state ^ current_state;
+	current_state = new_state;
+	if (diff & THROT_PROCHOT) {
+		int prochot = (new_state & THROT_PROCHOT) ? 0 : 1;
+
+		gpio_set_level(GPIO_EC_PROCHOT_ODL, prochot);
+	}
+	if (diff & THROT_TYPE_C0) {
+		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C0) ?
+						TYPEC_RP_1A5 :
+						TYPEC_RP_3A0;
+
+		ppc_set_vbus_source_current_limit(0, rp);
+		tcpm_select_rp_value(0, rp);
+		pd_update_contract(0);
+	}
+	if (diff & THROT_TYPE_C1) {
+		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C1) ?
+						TYPEC_RP_1A5 :
+						TYPEC_RP_3A0;
+
+		ppc_set_vbus_source_current_limit(1, rp);
+		tcpm_select_rp_value(1, rp);
+		pd_update_contract(1);
+	}
+	if (diff & THROT_TYPE_A_REAR) {
+		int typea_bc = (new_state & THROT_TYPE_A_REAR) ? 1 : 0;
+
+		gpio_set_level(GPIO_USB_A_LOW_PWR1_OD, typea_bc);
+	}
+	if (diff & THROT_TYPE_A_FRONT) {
+		int typea_bc = (new_state & THROT_TYPE_A_FRONT) ? 1 : 0;
+
+		gpio_set_level(GPIO_USB_A_LOW_PWR2_OD, typea_bc);
+	}
+	hook_call_deferred(&power_monitor_data, delay);
+}
+/*
+ * Start power monitoring after ADCs have been initialised.
+ */
+DECLARE_HOOK(HOOK_INIT, power_monitor, HOOK_PRIO_INIT_ADC + 1);
+
+/******************************************************************************/
+/*
+ * System power on and wake up by monitor power button.
+ *
+ * After pressing power button of monitor for power on, monitor will send power
+ * on signal with 3.3V / 200ms to DT. If DT detect that pulse, there are three
+ * DT behavior:
+ *
+ *  - Do nothing in state S0.
+ *  - Wake up from state S0ix.
+ *  - Power on from state S5 and G3.
+ */
+
+/* Debounce time for HDMI power button press */
+#define MONITOR_DEBOUNCE_MS 100
+
+static void monitor_irq_deferred(void);
+DECLARE_DEFERRED(monitor_irq_deferred);
+
+static void monitor_irq_deferred(void)
+{
+	int i;
+
+	for (i = 0; i < MONITOR_COUNT; i++) {
+		if (monitors[i].state && gpio_get_level(monitors[i].gpio)) {
+			/*
+			 * System power on from state S5 and G3.
+			 */
+			if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+				chipset_power_on();
+			/*
+			 * System wake up from state S0ix.
+			 */
+			else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
+				power_button_simulate_press(200);
+		}
+		monitors[i].state = MONITOR_OFF;
+	}
+}
+
+/* Power on by HDMI/ DP monitor. */
+void monitor_interrupt(enum gpio_signal signal)
+{
+	/*
+	 * Power on by HDMI/ DP monitor only works
+	 * when system is not in S0.
+	 */
+	if (chipset_in_state(CHIPSET_STATE_ON))
+		return;
+
+	if (ec_cfg_power_on_monitor() == POWER_ON_MONITOR_ENABLE) {
+		switch (signal) {
+		case GPIO_HDMI1_MONITOR_ON:
+			monitors[HDMI1_MONITOR].state = MONITOR_ON;
+			break;
+		case GPIO_HDMI2_MONITOR_ON:
+			monitors[HDMI2_MONITOR].state = MONITOR_ON;
+			break;
+		case GPIO_OPTION_MONITOR_ON:
+			monitors[OPTION_MONITOR].state = MONITOR_ON;
+			break;
+		default:
+			break;
+		}
+		hook_call_deferred(&monitor_irq_deferred_data,
+				   MONITOR_DEBOUNCE_MS * MSEC);
+	}
+}
diff --git a/board/aurash/board.h b/board/aurash/board.h
new file mode 100644
index 0000000000..80848e70f0
--- /dev/null
+++ b/board/aurash/board.h
@@ -0,0 +1,191 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Aurash board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "compile_time_macros.h"
+
+/* Baseboard features */
+#include "baseboard.h"
+
+#define CONFIG_MP2964
+
+/* Barrel Jack */
+#define DEDICATED_CHARGE_PORT 2
+
+/* HDMI CEC */
+#define CONFIG_CEC
+#define CONFIG_CEC_BITBANG
+#define CEC_GPIO_OUT GPIO_HDMI_CEC_OUT
+#define CEC_GPIO_IN GPIO_HDMI_CEC_IN
+#define CEC_GPIO_PULL_UP GPIO_HDMI_CEC_PULL_UP
+
+/* USB Type A Features */
+#define USB_PORT_COUNT 4
+#define CONFIG_USB_PORT_POWER_DUMB
+
+/* USB Type C and USB PD defines */
+#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
+
+#define CONFIG_IO_EXPANDER
+#define CONFIG_IO_EXPANDER_NCT38XX
+#define CONFIG_IO_EXPANDER_PORT_COUNT 2
+
+#define CONFIG_USB_PD_PPC
+#define CONFIG_USBC_RETIMER_INTEL_BB
+
+#undef CONFIG_CMD_POWERINDEBUG
+
+#define CONFIG_USBC_PPC_SYV682X
+#undef CONFIG_SYV682X_HV_ILIM
+#define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_5_50
+
+/* TODO: b/177608416 - measure and check these values on brya */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
+
+/* The design should support up to 100W. */
+/* TODO(b/197702356): Set the max PD to 60W now and change it
+ * to 100W after we verify it.
+ */
+#define PD_OPERATING_POWER_MW CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
+#define PD_MAX_POWER_MW 100000
+#define PD_MAX_CURRENT_MA 5000
+#define PD_MAX_VOLTAGE_MV 20000
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
+
+/*
+ * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
+ * signal.
+ */
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
+#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_ODL
+#define GPIO_RECOVERY_L_2 GPIO_GSC_EC_RECOVERY_BTN_ODL
+
+/* I2C Bus Configuration */
+
+#define I2C_PORT_USB_C0_C1_TCPC NPCX_I2C_PORT1_0
+
+#define I2C_PORT_USB_C0_C1_PPC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_A0_A1_MIX NPCX_I2C_PORT6_1
+
+#define I2C_PORT_USB_C0_C1_BC12 NPCX_I2C_PORT2_0
+
+#define I2C_PORT_USB_C0_C1_MUX NPCX_I2C_PORT3_0
+
+#define I2C_PORT_QI NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+
+#define I2C_ADDR_MP2964_FLAGS 0x20
+
+#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x56
+#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x57
+
+/* Enabling Thunderbolt-compatible mode */
+#define CONFIG_USB_PD_TBT_COMPAT_MODE
+
+/* Enabling USB4 mode */
+#define CONFIG_USB_PD_USB4
+#define CONFIG_USB_PD_DATA_RESET_MSG
+
+/* Retimer */
+#define CONFIG_USBC_RETIMER_FW_UPDATE
+
+/* Thermal features */
+#define CONFIG_THERMISTOR
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_TEMP_SENSOR_POWER
+#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
+
+/* ADC */
+#define CONFIG_ADC
+
+/* Include math_util for bitmask_uint64 used in pd_timers */
+#define CONFIG_MATH_UTIL
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h" /* needed by registers.h */
+#include "registers.h"
+#include "usbc_config.h"
+
+enum charge_port {
+	CHARGE_PORT_TYPEC0,
+	CHARGE_PORT_TYPEC1,
+	CHARGE_PORT_BARRELJACK,
+	CHARGE_PORT_ENUM_COUNT
+};
+
+enum adc_channel {
+	ADC_TEMP_SENSOR_1_SSD,
+	ADC_TEMP_SENSOR_2_CPU_VR,
+	ADC_TEMP_SENSOR_4_DIMM,
+	ADC_VBUS,
+	ADC_PPVAR_IMON, /* ADC3 */
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1_SSD,
+	TEMP_SENSOR_2_CPU_VR,
+	TEMP_SENSOR_4_DIMM,
+	TEMP_SENSOR_COUNT
+};
+
+enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_C1_NCT38XX, IOEX_PORT_COUNT };
+
+enum pwm_channel {
+	PWM_CH_LED_AMBER, /* PWM0 */
+	PWM_CH_LED_BLUE, /* PWM2 */
+	PWM_CH_COUNT
+};
+
+enum monitor_port {
+	HDMI1_MONITOR,
+	HDMI2_MONITOR,
+	OPTION_MONITOR,
+	MONITOR_COUNT
+};
+
+enum monitor_state { MONITOR_OFF, MONITOR_ON };
+
+enum cec_port { CEC_PORT_0, CEC_PORT_COUNT };
+
+extern void adp_connect_interrupt(enum gpio_signal signal);
+extern void monitor_interrupt(enum gpio_signal signal);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/aurash/build.mk b/board/aurash/build.mk
new file mode 100644
index 0000000000..8f1b8bfc78
--- /dev/null
+++ b/board/aurash/build.mk
@@ -0,0 +1,21 @@
+# -*- makefile -*-
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Aurash board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx9
+CHIP_VARIANT:=npcx9m3f
+BASEBOARD:=brask
+
+board-y=
+board-y+=board.o
+board-y+=fw_config.o
+board-y+=i2c.o
+board-y+=led.o
+board-y+=pwm.o
+board-y+=sensors.o
+board-y+=usbc_config.o
diff --git a/board/aurash/ec.tasklist b/board/aurash/ec.tasklist
new file mode 100644
index 0000000000..a3189950ab
--- /dev/null
+++ b/board/aurash/ec.tasklist
@@ -0,0 +1,25 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ *
+ * USB_CHG_Px tasks must be contiguous (see USB_CHG_PORT_TO_TASK_ID(x)).
+ * PD_Cx tasks must be contiguous (see PD_PORT_TO_TASK_ID(x))
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_shared_alert_task, (BIT(1) | BIT(0)), LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CEC, cec_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/aurash/fw_config.c b/board/aurash/fw_config.c
new file mode 100644
index 0000000000..2c312acea6
--- /dev/null
+++ b/board/aurash/fw_config.c
@@ -0,0 +1,73 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "fw_config.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+static union aurash_cbi_fw_config fw_config;
+BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
+
+/*
+ * FW_CONFIG defaults for aurash if the CBI.FW_CONFIG data is not
+ * initialized.
+ */
+static const union aurash_cbi_fw_config fw_config_defaults = {
+	.bj_power = BJ_90W,
+	.po_mon = POWER_ON_MONITOR_ENABLE,
+};
+
+/*
+ * Barrel-jack power adapter ratings.
+ */
+static const struct {
+	int voltage;
+	int current;
+} bj_power[] = {
+	[BJ_90W] = { /* 0 - 90W (also default) */
+	  .voltage = 19000,
+	  .current = 4740 },
+	[BJ_135W] = { /* 1 - 135W */
+	  .voltage = 19500,
+	  .current = 6920 },
+};
+
+/****************************************************************************
+ * Aurash FW_CONFIG access
+ */
+void board_init_fw_config(void)
+{
+	if (cbi_get_fw_config(&fw_config.raw_value)) {
+		CPRINTS("CBI: Read FW_CONFIG failed, using board defaults");
+		fw_config = fw_config_defaults;
+	}
+}
+
+union aurash_cbi_fw_config get_fw_config(void)
+{
+	return fw_config;
+}
+
+void ec_bj_power(uint32_t *voltage, uint32_t *current)
+{
+	unsigned int bj;
+
+	bj = fw_config.bj_power;
+	/* Out of range value defaults to 0 */
+	if (bj >= ARRAY_SIZE(bj_power))
+		bj = 0;
+	*voltage = bj_power[bj].voltage;
+	*current = bj_power[bj].current;
+}
+
+enum ec_cfg_power_on_monitor ec_cfg_power_on_monitor(void)
+{
+	return fw_config.po_mon;
+}
diff --git a/board/aurash/fw_config.h b/board/aurash/fw_config.h
new file mode 100644
index 0000000000..e498831966
--- /dev/null
+++ b/board/aurash/fw_config.h
@@ -0,0 +1,53 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __BOARD_AURASH_FW_CONFIG_H_
+#define __BOARD_AURASH_FW_CONFIG_H_
+
+#include <stdint.h>
+
+/****************************************************************************
+ * CBI FW_CONFIG layout for Aurash board.
+ *
+ * Source of truth is the project/brask/aurash/config.star configuration file.
+ */
+
+enum ec_cfg_bj_power { BJ_90W = 0, BJ_135W = 1 };
+
+enum ec_cfg_power_on_monitor {
+	POWER_ON_MONITOR_ENABLE = 0,
+	POWER_ON_MONITOR_DISABLE = 1
+};
+
+union aurash_cbi_fw_config {
+	struct {
+		uint32_t bj_power : 2;
+		uint32_t mlb_usb_tbt : 2;
+		uint32_t storage : 2;
+		uint32_t audio : 1;
+		enum ec_cfg_power_on_monitor po_mon : 1;
+		uint32_t reserved_1 : 24;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Read the cached FW_CONFIG.  Guaranteed to have valid values.
+ *
+ * @return the FW_CONFIG for the board.
+ */
+union aurash_cbi_fw_config get_fw_config(void);
+
+/**
+ * Get the barrel-jack power from FW_CONFIG.
+ */
+void ec_bj_power(uint32_t *voltage, uint32_t *current);
+
+/**
+ * Get enable/disable power on by monitor from FW_CONFIG.
+ */
+enum ec_cfg_power_on_monitor ec_cfg_power_on_monitor(void);
+
+#endif /* __BOARD_AURASH_FW_CONFIG_H_ */
diff --git a/board/aurash/gpio.inc b/board/aurash/gpio.inc
new file mode 100644
index 0000000000..702c79df25
--- /dev/null
+++ b/board/aurash/gpio.inc
@@ -0,0 +1,177 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* INTERRUPT GPIOs: */
+GPIO_INT(ACOK_OD,                    PIN(0, 0), GPIO_INT_BOTH, extpower_interrupt)
+GPIO_INT(EC_PROCHOT_IN_L,            PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
+GPIO_INT(EC_WP_ODL,                  PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(GSC_EC_PWR_BTN_ODL,         PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
+GPIO_INT(SEQ_EC_ALL_SYS_PG,          PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_DSW_PWROK,           PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_RSMRST_ODL,          PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,                   PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,                  PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SYS_SLP_S0IX_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(USB_C0_BC12_INT_ODL,        PIN(C, 6), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C0_C1_TCPC_INT_ODL,     PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C0_PPC_INT_ODL,         PIN(6, 2), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C0_RT_INT_ODL,          PIN(B, 1), GPIO_INT_FALLING, retimer_interrupt)
+GPIO_INT(BJ_ADP_PRESENT_ODL,         PIN(8, 2), GPIO_INT_BOTH | GPIO_PULL_UP, adp_connect_interrupt)
+GPIO_INT(EC_RECOVERY_BTN_ODL,        PIN(2, 3), GPIO_INT_BOTH, button_interrupt)
+GPIO_INT(USB_C1_RT_INT_ODL,          PIN(4, 1), GPIO_INT_FALLING, retimer_interrupt)
+GPIO_INT(USB_C1_BC12_INT_ODL,        PIN(8, 3), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C1_PPC_INT_ODL,         PIN(7, 0), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(HDMI1_MONITOR_ON,           PIN(B, 4), GPIO_INT_RISING, monitor_interrupt)
+GPIO_INT(HDMI2_MONITOR_ON,           PIN(B, 5), GPIO_INT_RISING, monitor_interrupt)
+GPIO_INT(OPTION_MONITOR_ON,          PIN(1, 0), GPIO_INT_RISING, monitor_interrupt)
+
+/* CCD */
+GPIO(CCD_MODE_ODL,                   PIN(E, 5), GPIO_INPUT)
+
+/* Security */
+GPIO(EC_ENTERING_RW,                 PIN(0, 3), GPIO_OUT_LOW)
+GPIO(EC_GSC_PACKET_MODE,             PIN(7, 5), GPIO_OUT_LOW)
+
+/* Fan */
+GPIO(EN_PP5000_FAN,                  PIN(6, 1), GPIO_OUT_LOW)
+
+/* ADC, need to check the usage */
+GPIO(ANALOG_PPVAR_PWR_IN_IMON_EC,    PIN(4, 2), GPIO_INPUT)
+
+/* BarrelJack */
+GPIO(EN_PPVAR_BJ_ADP_L,              PIN(0, 7), GPIO_OUT_LOW)
+
+/* Chipset PCH */
+GPIO(EC_PCHHOT_ODL,                  PIN(7, 4), GPIO_INPUT)
+GPIO(EC_PCH_INT_ODL,                 PIN(B, 0), GPIO_ODR_HIGH)
+GPIO(EC_PCH_RSMRST_L,                PIN(A, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_RTCRST,                  PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_SYS_PWROK,               PIN(3, 7), GPIO_OUT_LOW)
+GPIO(EC_PCH_WAKE_ODL,                PIN(C, 0), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_ODL,                 PIN(6, 3), GPIO_ODR_HIGH)
+GPIO(EN_S5_RAILS,                    PIN(B, 6), GPIO_OUT_LOW)
+GPIO(PCH_PWROK,                      PIN(7, 2), GPIO_OUT_LOW)
+GPIO(SYS_RST_ODL,                    PIN(C, 5), GPIO_ODR_HIGH)
+GPIO(VCCST_PWRGD_OD,                 PIN(A, 4), GPIO_ODR_LOW)
+GPIO(IMVP9_VRRDY_OD,                 PIN(6, 0), GPIO_INPUT)
+GPIO(CPU_C10_GATE_L,                 PIN(6, 7), GPIO_INPUT)
+
+/* Button */
+GPIO(EC_PCH_PWR_BTN_ODL,             PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(GSC_EC_RECOVERY_BTN_ODL,        PIN(2, 2), GPIO_INPUT)
+
+/* NFC */
+/* TODO(b/194068530): Enable NFC */
+GPIO(NFC_COIL_ACT_L,                 PIN(D, 4), GPIO_INPUT)
+GPIO(NFC_LOW_POWER_MODE,             PIN(9, 5), GPIO_OUT_HIGH)
+GPIO(NFC_CARD_DET_L,                 PIN(A, 3), GPIO_INPUT)
+GPIO(EN_NFC_BUZZER,                  PIN(0, 5), GPIO_OUT_LOW)
+
+/* Wireless Charger */
+/* TODO(b/191418683): Implement Qi Driver */
+GPIO(EC_QI_PWR,                      PIN(D, 2), GPIO_OUT_HIGH)
+GPIO(EC_I2C_QI_RESET_L,              PIN(9, 3), GPIO_OUT_HIGH)
+GPIO(EC_I2C_QI_INT_ODL,              PIN(9, 6), GPIO_INPUT)
+
+/* HDMI */
+GPIO(HDMI_CONN_OC_ODL,               PIN(2, 4), GPIO_INPUT)
+
+/* HDMI CEC */
+/* TODO(b/197474873): Enable HDMI CEC */
+GPIO(HDMI_CEC_IN,                    PIN(4, 0), GPIO_INPUT)
+GPIO(HDMI_CEC_OUT,                   PIN(D, 3), GPIO_OUT_HIGH | GPIO_OPEN_DRAIN)
+GPIO(HDMI_CEC_PULL_UP,               PIN(C, 2), GPIO_OUT_HIGH)
+
+/* I2C SCL/SDA */
+GPIO(EC_I2C_QI_SCL,                  PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_QI_SDA,                  PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SCL,                PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SDA,                PIN(B, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C1_PPC_BC_SCL,    PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C1_PPC_BC_SDA,    PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C1_RT_SCL,        PIN(D, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C1_RT_SDA,        PIN(D, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C1_TCPC_SCL,      PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C1_TCPC_SDA,      PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_USB_A0_A1_MIX_SCL,       PIN(E, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_A0_A1_MIX_SDA,       PIN(E, 3), GPIO_INPUT)
+
+/* USBA */
+GPIO(EN_PP5000_USBA,                 PIN(D, 7), GPIO_OUT_LOW)
+GPIO(USB_A1_STATUS_L,                PIN(2, 0), GPIO_INPUT)
+GPIO(USB_A2_STATUS_L,                PIN(1, 7), GPIO_INPUT)
+GPIO(USB_A_LOW_PWR1_OD,              PIN(1, 4), GPIO_OUT_LOW)
+GPIO(USB_A_LOW_PWR2_OD,              PIN(1, 1), GPIO_OUT_LOW)
+GPIO(USB_A_OC_SOC_L,                 PIN(8, 0), GPIO_OUT_HIGH)
+GPIO(USB_A1_OC_ODL,                  PIN(3, 0), GPIO_INPUT)
+GPIO(USB_A2_OC_ODL,                  PIN(2, 7), GPIO_INPUT)
+GPIO(USB_A3_OC_ODL,                  PIN(2, 6), GPIO_INPUT)
+GPIO(USB_A4_OC_ODL,                  PIN(0, 6), GPIO_INPUT)
+
+/* USBC */
+GPIO(USB_C0_C1_TCPC_RST_ODL,         PIN(F, 5), GPIO_ODR_LOW)
+
+/* LAN */
+GPIO(LAN_PWR_GOOD,                   PIN(0, 2), GPIO_INPUT)
+
+/* LED */
+GPIO(LED_ORANGE_CONTROL,             PIN(3, 1), GPIO_ODR_LOW)
+GPIO(LED_BLUE_CONTROL,               PIN(2, 5), GPIO_ODR_LOW)
+
+/* Option Board */
+GPIO(HDMI1_MONON_SIO,                PIN(1, 6), GPIO_INPUT)
+GPIO(HDMI2_MONON_SIO,                PIN(1, 5), GPIO_INPUT)
+GPIO(OPTION_MONON_SIO,               PIN(2, 1), GPIO_INPUT)
+
+IOEX(USB_C0_OC_ODL,          EXPIN(IOEX_C0_NCT38XX, 0, 4), GPIO_ODR_HIGH)
+IOEX(USB_C0_FRS_EN,          EXPIN(IOEX_C0_NCT38XX, 0, 6), GPIO_LOW)
+IOEX(USB_C0_RT_RST_ODL,      EXPIN(IOEX_C0_NCT38XX, 0, 7), GPIO_ODR_LOW)
+
+IOEX(USB_C1_OC_ODL,          EXPIN(IOEX_C1_NCT38XX, 0, 4), GPIO_ODR_HIGH)
+IOEX(USB_C1_RT_RST_ODL,      EXPIN(IOEX_C1_NCT38XX, 0, 2), GPIO_ODR_LOW)
+IOEX(USB_C1_FRS_EN,          EXPIN(IOEX_C1_NCT38XX, 0, 6), GPIO_LOW)
+
+/* UART alternate functions */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)              /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */
+
+/* I2C alternate functions */
+ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)               /* GPIO33/I2C5_SCL0/CTS_L, GPIO36/RTS_L/I2C5_SDA0 */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)               /* GPIO87/I2C1_SDA0 */
+ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)               /* GPIO92/I2C2_SCL0, GPIO91/I2C2_SDA0, GPIO90/I2C1_SCL0 */
+ALTERNATE(PIN_MASK(B, 0x0c), 0, MODULE_I2C, 0)               /* GPIOB3/I2C7_SCL0/DCD_L, GPIOB2/I2C7_SDA0/DSR_L */
+ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)               /* GPIOD1/I2C3_SCL0, GPIOD0/I2C3_SDA0 */
+ALTERNATE(PIN_MASK(E, 0x18), 0, MODULE_I2C, 0)               /* GPIOE4/I2C6_SCL1/I3C_SCL, GPIOE3/I2C6_SDA1/I3C_SDA */
+
+/* PWM alternate functions */
+ALTERNATE(PIN_MASK(C, 0x18), 0, MODULE_PWM, 0)               /* GPIOC4/PWM2, GPIOC3/PWM0 */
+
+/* ADC alternate functions */
+ALTERNATE(PIN_MASK(4, 0x38), 0, MODULE_ADC, 0)               /* GPIO45/ADC0, GPIO44/ADC1, GPIO43/ADC2 */
+ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0)               /* GPIOE1/ADC7 */
+
+/* Unused Pins */
+UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
+UNUSED(PIN(3, 2))       /* GPO32/TRIS_L */
+UNUSED(PIN(3, 5))       /* GPO35/CR_SOUT4/TEST_L */
+UNUSED(PIN(6, 6))       /* GPIO66 */
+UNUSED(PIN(8, 1))       /* GPIO81/PECI_DATA */
+UNUSED(PIN(5, 6))       /* GPIO56/CLKRUN# */
+UNUSED(PIN(9, 7))       /* GPIO97 */
+UNUSED(PIN(8, 6))       /* GPIO86/TXD/CR_SOUT2/FLPRG2_L */
+UNUSED(PIN(1, 3))       /* KSO06/GPO13/GP_SEL# */
+UNUSED(PIN(1, 2))       /* KSO07/GPO12/JEN# */
+UNUSED(PIN(0, 4))       /* KSO13/GPIO04 */
+UNUSED(PIN(A, 2))       /* F_SCLK/GPIOA2 */
+UNUSED(PIN(5, 0))       /* GPIO50 */
+UNUSED(PIN(9, 4))       /* GPIO94 */
+UNUSED(PIN(A, 0))       /* F_CS0_L/GPIOA0 */
+UNUSED(PIN(3, 4))       /* GPIO34/PS2_DAT2/ADC6 */
+UNUSED(PIN(F, 3))       /* GPIOF3/I2C4_SCL1 */
+UNUSED(PIN(F, 2))       /* GPIOF2/I2C4_SDA1 */
+UNUSED(PIN(A, 7))       /* GPIOA7/PS2_DAT3/TB2/F_DIO3 */
+UNUSED(PIN(B, 7))       /* GPIOB7/PWM5 */
+UNUSED(PIN(7, 3))       /* GPIO73/TA2 */
diff --git a/board/aurash/i2c.c b/board/aurash/i2c.c
new file mode 100644
index 0000000000..5df3b5b7e7
--- /dev/null
+++ b/board/aurash/i2c.c
@@ -0,0 +1,61 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "i2c.h"
+
+/* I2C port map configuration */
+const struct i2c_port_t i2c_ports[] = {
+	{
+		/* I2C1 */
+		.name = "tcpc0,1",
+		.port = I2C_PORT_USB_C0_C1_TCPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C1_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C1_TCPC_SDA,
+	},
+	{
+		/* I2C2 */
+		.name = "ppc0,1",
+		.port = I2C_PORT_USB_C0_C1_PPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C1_PPC_BC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C1_PPC_BC_SDA,
+	},
+	{
+		/* I2C3 */
+		.name = "retimer0,1",
+		.port = I2C_PORT_USB_C0_C1_MUX,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C1_RT_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C1_RT_SDA,
+	},
+	{
+		/* I2C5 */
+		.name = "wireless_charger",
+		.port = I2C_PORT_QI,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_QI_SCL,
+		.sda = GPIO_EC_I2C_QI_SDA,
+	},
+	{
+		/* I2C6 */
+		.name = "usba_mix0,1",
+		.port = I2C_PORT_USB_A0_A1_MIX,
+		.kbps = 100,
+		.scl = GPIO_EC_I2C_USB_A0_A1_MIX_SCL,
+		.sda = GPIO_EC_I2C_USB_A0_A1_MIX_SDA,
+	},
+	{
+		/* I2C7 */
+		.name = "eeprom",
+		.port = I2C_PORT_EEPROM,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_MISC_SCL,
+		.sda = GPIO_EC_I2C_MISC_SDA,
+	},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/board/aurash/led.c b/board/aurash/led.c
new file mode 100644
index 0000000000..21c4a2dafc
--- /dev/null
+++ b/board/aurash/led.c
@@ -0,0 +1,281 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power LED control for Brask.
+ * Solid green - active power
+ * Green flashing - suspended
+ * Red flashing - alert
+ * Solid red - critical
+ */
+
+#include "chipset.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "led_common.h"
+#include "pwm.h"
+#include "timer.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
+
+/*
+ * Due to the CSME-Lite processing, upon startup the CPU transitions through
+ * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so
+ * delay turning off the LED during suspend/shutdown.
+ */
+#define LED_CPU_DELAY_MS (2000 * MSEC)
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED };
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+enum led_color {
+	LED_OFF = 0,
+	LED_BLUE,
+	LED_AMBER,
+
+	/* Number of colors, not a color itself */
+	LED_COLOR_COUNT
+};
+
+static int set_color_power(enum led_color color, int duty)
+{
+	int amber = 0;
+	int blue = 0;
+
+	if (duty < 0 || 100 < duty)
+		return EC_ERROR_UNKNOWN;
+
+	switch (color) {
+	case LED_OFF:
+		break;
+	case LED_AMBER:
+		amber = 1;
+		break;
+	case LED_BLUE:
+		blue = 1;
+		break;
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+
+	if (blue && duty) {
+		gpio_set_level(GPIO_LED_BLUE_CONTROL, 1);
+		pwm_set_duty(PWM_CH_LED_BLUE, duty);
+	} else {
+		gpio_set_level(GPIO_LED_BLUE_CONTROL, 0);
+		pwm_set_duty(PWM_CH_LED_BLUE, 0);
+	}
+
+	if (amber && duty) {
+		gpio_set_level(GPIO_LED_ORANGE_CONTROL, 1);
+		pwm_set_duty(PWM_CH_LED_AMBER, duty);
+	} else {
+		gpio_set_level(GPIO_LED_ORANGE_CONTROL, 0);
+		pwm_set_duty(PWM_CH_LED_AMBER, 0);
+	}
+
+	return EC_SUCCESS;
+}
+
+static int set_color(enum ec_led_id id, enum led_color color, int duty)
+{
+	switch (id) {
+	case EC_LED_ID_POWER_LED:
+		return set_color_power(color, duty);
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+}
+
+#define LED_PERIOD (4 * SECOND)
+#define LED_DUTY_CYCLE (25)
+#define LED_PULSE_US (LED_PERIOD * LED_DUTY_CYCLE / 100 / 2)
+/* 10 msec for nice and smooth transition. */
+#define LED_PULSE_TICK_US (10 * MSEC)
+
+/*
+ * When pulsing is enabled, brightness is incremented by <duty_inc> every
+ * <interval> usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented
+ * likewise in LED_PULSE_US usec.
+ */
+static struct {
+	uint32_t interval;
+	int duty_inc;
+	enum led_color color;
+	int duty;
+	uint32_t time_off;
+} led_pulse;
+
+/*
+ * LED_PERIOD = time_on + time_off;
+ * time_on = LED_PULSE_US * 2;
+ * time_off = LED_PERIOD - LED_PULSE_US * 2;
+ */
+#define CONFIG_TICK(interval, period, color)                       \
+	config_tick((interval), 100 / (LED_PULSE_US / (interval)), \
+		    LED_PERIOD - LED_PULSE_US * 2, (color))
+
+static void config_tick(uint32_t interval, int duty_inc, int time_off,
+			enum led_color color)
+{
+	led_pulse.interval = interval;
+	led_pulse.duty_inc = duty_inc;
+	led_pulse.color = color;
+	led_pulse.duty = 0;
+	led_pulse.time_off = time_off;
+}
+
+static void pulse_power_led(enum led_color color)
+{
+	set_color(EC_LED_ID_POWER_LED, color, led_pulse.duty);
+	if (led_pulse.duty + led_pulse.duty_inc > 100)
+		led_pulse.duty_inc = led_pulse.duty_inc * -1;
+	else if (led_pulse.duty + led_pulse.duty_inc < 0)
+		led_pulse.duty_inc = led_pulse.duty_inc * -1;
+	led_pulse.duty += led_pulse.duty_inc;
+}
+
+static void led_tick(void);
+DECLARE_DEFERRED(led_tick);
+static void led_tick(void)
+{
+	uint32_t elapsed;
+	uint32_t next = 0;
+	uint32_t start = get_time().le.lo;
+
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		pulse_power_led(led_pulse.color);
+	elapsed = get_time().le.lo - start;
+	next = led_pulse.interval > elapsed ? led_pulse.interval - elapsed : 0;
+	next = (led_pulse.duty - led_pulse.duty_inc) ?
+		       next :
+		       next + led_pulse.time_off;
+	hook_call_deferred(&led_tick_data, next);
+}
+
+static void led_suspend(void)
+{
+	CONFIG_TICK(LED_PULSE_TICK_US, LED_PERIOD, LED_BLUE);
+	led_tick();
+}
+DECLARE_DEFERRED(led_suspend);
+
+static void led_shutdown(void)
+{
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_OFF, 0);
+}
+DECLARE_DEFERRED(led_shutdown);
+
+static void led_shutdown_hook(void)
+{
+	hook_call_deferred(&led_tick_data, -1);
+	hook_call_deferred(&led_suspend_data, -1);
+	hook_call_deferred(&led_shutdown_data, LED_CPU_DELAY_MS);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, led_shutdown_hook, HOOK_PRIO_DEFAULT);
+
+static void led_suspend_hook(void)
+{
+	hook_call_deferred(&led_shutdown_data, -1);
+	hook_call_deferred(&led_suspend_data, LED_CPU_DELAY_MS);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, led_suspend_hook, HOOK_PRIO_DEFAULT);
+
+static void led_resume(void)
+{
+	/*
+	 * Assume there is no race condition with led_tick, which also
+	 * runs in hook_task.
+	 */
+	hook_call_deferred(&led_tick_data, -1);
+	/*
+	 * Avoid invoking the suspend/shutdown delayed hooks.
+	 */
+	hook_call_deferred(&led_suspend_data, -1);
+	hook_call_deferred(&led_shutdown_data, -1);
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_BLUE, 100);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, led_resume, HOOK_PRIO_DEFAULT);
+
+void led_alert(int enable)
+{
+	if (enable) {
+		/* Overwrite the current signal */
+		config_tick(1 * SECOND, 100, 0, LED_AMBER);
+		led_tick();
+	} else {
+		/* Restore the previous signal */
+		if (chipset_in_state(CHIPSET_STATE_ON))
+			led_resume();
+		else if (chipset_in_state(CHIPSET_STATE_SUSPEND))
+			led_suspend_hook();
+		else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+			led_shutdown_hook();
+	}
+}
+
+void show_critical_error(void)
+{
+	hook_call_deferred(&led_tick_data, -1);
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_AMBER, 100);
+}
+
+static int command_led(int argc, const char **argv)
+{
+	enum ec_led_id id = EC_LED_ID_POWER_LED;
+
+	if (argc < 2)
+		return EC_ERROR_PARAM_COUNT;
+
+	if (!strcasecmp(argv[1], "debug")) {
+		led_auto_control(id, !led_auto_control_is_enabled(id));
+		ccprintf("o%s\n", led_auto_control_is_enabled(id) ? "ff" : "n");
+	} else if (!strcasecmp(argv[1], "off")) {
+		set_color(id, LED_OFF, 0);
+	} else if (!strcasecmp(argv[1], "blue")) {
+		set_color(id, LED_BLUE, 100);
+	} else if (!strcasecmp(argv[1], "amber")) {
+		set_color(id, LED_AMBER, 100);
+	} else if (!strcasecmp(argv[1], "alert")) {
+		led_alert(1);
+	} else if (!strcasecmp(argv[1], "crit")) {
+		show_critical_error();
+	} else {
+		return EC_ERROR_PARAM1;
+	}
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(led, command_led, "[debug|blue|amber|off|alert|crit]",
+			"Turn on/off LED.");
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	brightness_range[EC_LED_COLOR_AMBER] = 100;
+	brightness_range[EC_LED_COLOR_BLUE] = 100;
+}
+
+int led_set_brightness(enum ec_led_id id, const uint8_t *brightness)
+{
+	if (brightness[EC_LED_COLOR_BLUE])
+		return set_color(id, LED_BLUE, brightness[EC_LED_COLOR_BLUE]);
+	else if (brightness[EC_LED_COLOR_AMBER])
+		return set_color(id, LED_AMBER, brightness[EC_LED_COLOR_AMBER]);
+	else
+		return set_color(id, LED_OFF, 0);
+}
+
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
+{
+	/* Blink alert if insufficient power per system_can_boot_ap(). */
+	int insufficient_power =
+		(charge_ma * charge_mv) <
+		(CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON * 1000);
+	led_alert(insufficient_power);
+}
diff --git a/board/aurash/pwm.c b/board/aurash/pwm.c
new file mode 100644
index 0000000000..be400d2ea6
--- /dev/null
+++ b/board/aurash/pwm.c
@@ -0,0 +1,29 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "hooks.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_LED_AMBER] = { .channel = 0,
+			       .flags = PWM_CONFIG_ACTIVE_LOW |
+					PWM_CONFIG_DSLEEP,
+			       .freq = 2000 },
+	[PWM_CH_LED_BLUE] = { .channel = 2,
+			      .flags = PWM_CONFIG_ACTIVE_LOW |
+				       PWM_CONFIG_DSLEEP,
+			      .freq = 2000 },
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+static void board_pwm_init(void)
+{
+	pwm_enable(PWM_CH_LED_BLUE, 1);
+	pwm_enable(PWM_CH_LED_AMBER, 1);
+}
+DECLARE_HOOK(HOOK_INIT, board_pwm_init, HOOK_PRIO_DEFAULT);
diff --git a/board/aurash/sensors.c b/board/aurash/sensors.c
new file mode 100644
index 0000000000..517a6ed905
--- /dev/null
+++ b/board/aurash/sensors.c
@@ -0,0 +1,102 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc_chip.h"
+#include "common.h"
+#include "hooks.h"
+#include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
+#include "thermal.h"
+
+/* ADC configuration */
+const struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_1_SSD] = {
+		.name = "TEMP_SSD",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_2_CPU_VR] = {
+		.name = "TEMP_CPU_VR",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_4_DIMM] = {
+		.name = "TEMP_DIMM",
+		.input_ch = NPCX_ADC_CH7,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_VBUS] = {  /* 5/39 voltage divider */
+		.name = "VBUS",
+		.input_ch = NPCX_ADC_CH2,
+		.factor_mul = ADC_MAX_VOLT * 39,
+		.factor_div = (ADC_READ_MAX + 1) * 5,
+	},
+	[ADC_PPVAR_IMON] = {  /* 20/(20+8.66)*50/200 current divider */
+		.name = "PPVAR_IMON",
+		.input_ch = NPCX_ADC_CH3,
+		.factor_mul = ADC_MAX_VOLT * 1433,
+		.factor_div = (ADC_READ_MAX + 1) * 250,
+	},
+
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* Temperature sensor configuration */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1_SSD] = { .name = "SSD",
+				.type = TEMP_SENSOR_TYPE_BOARD,
+				.read = get_temp_3v3_30k9_47k_4050b,
+				.idx = ADC_TEMP_SENSOR_1_SSD },
+	[TEMP_SENSOR_2_CPU_VR] = { .name = "CPU VR",
+				   .type = TEMP_SENSOR_TYPE_BOARD,
+				   .read = get_temp_3v3_30k9_47k_4050b,
+				   .idx = ADC_TEMP_SENSOR_2_CPU_VR },
+	[TEMP_SENSOR_4_DIMM] = { .name = "DIMM",
+				 .type = TEMP_SENSOR_TYPE_BOARD,
+				 .read = get_temp_3v3_30k9_47k_4050b,
+				 .idx = ADC_TEMP_SENSOR_4_DIMM },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+#define THERMAL_SSD                                          \
+	{                                                    \
+		.temp_host = {                               \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(100), \
+		},                                           \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_ssd = THERMAL_SSD;
+
+#define THERMAL_CPU                                          \
+	{                                                    \
+		.temp_host = {                               \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(125), \
+		},                                           \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
+
+#define THERMAL_DIMM                                        \
+	{                                                   \
+		.temp_host = {                              \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(95), \
+		},                                          \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_dimm =
+	THERMAL_DIMM;
+/*
+ * TODO(b/197478860): add the thermal sensor setting
+ */
+/* this should really be "const" */
+struct ec_thermal_config thermal_params[] = {
+	[TEMP_SENSOR_1_SSD] = THERMAL_SSD,
+	[TEMP_SENSOR_2_CPU_VR] = THERMAL_CPU,
+	[TEMP_SENSOR_4_DIMM] = THERMAL_DIMM,
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
diff --git a/board/aurash/usbc_config.c b/board/aurash/usbc_config.c
new file mode 100644
index 0000000000..68a08a2d45
--- /dev/null
+++ b/board/aurash/usbc_config.c
@@ -0,0 +1,345 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/bc12/pi3usb9201_public.h"
+#include "driver/ppc/syv682x_public.h"
+#include "driver/retimer/bb_retimer_public.h"
+#include "driver/tcpm/nct38xx.h"
+#include "driver/tcpm/tcpci.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "ioexpander.h"
+#include "system.h"
+#include "task.h"
+#include "task_id.h"
+#include "timer.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+/* USBC TCPC configuration */
+const struct tcpc_config_t tcpc_config[] = {
+	[USBC_PORT_C0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0_C1_TCPC,
+			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_NO_DEBUG_ACC_CONTROL,
+	},
+	[USBC_PORT_C1] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0_C1_TCPC,
+			.addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
+BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
+
+/* USBC PPC configuration */
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_C1_PPC,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.drv = &syv682x_drv,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C0_C1_PPC,
+		.i2c_addr_flags = SYV682X_ADDR2_FLAGS,
+		.drv = &syv682x_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
+
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/* USBC mux configuration - Alder Lake includes internal mux */
+static const struct usb_mux_chain usbc0_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+
+static const struct usb_mux_chain usbc1_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+
+const struct usb_mux_chain usb_muxes[] = {
+	[USBC_PORT_C0] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C0_C1_MUX,
+			.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc0_tcss_usb_mux,
+	},
+	[USBC_PORT_C1] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C0_C1_MUX,
+			.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc1_tcss_usb_mux,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
+
+/* BC1.2 charger detect configuration */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_C1_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C0_C1_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_1_FLAGS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
+
+/*
+ * USB C0 and C2 uses burnside bridge chips and have their reset
+ * controlled by their respective TCPC chips acting as GPIO expanders.
+ *
+ * ioex_init() is normally called before we take the TCPCs out of
+ * reset, so we need to start in disabled mode, then explicitly
+ * call ioex_init().
+ */
+
+struct ioexpander_config_t ioex_config[] = {
+	[IOEX_C0_NCT38XX] = {
+		.i2c_host_port = I2C_PORT_USB_C0_C1_TCPC,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
+	},
+	[IOEX_C1_NCT38XX] = {
+		.i2c_host_port = I2C_PORT_USB_C0_C1_TCPC,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT);
+
+__override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
+{
+	enum ioex_signal rst_signal;
+
+	if (me->usb_port == USBC_PORT_C0) {
+		rst_signal = IOEX_USB_C0_RT_RST_ODL;
+	} else if (me->usb_port == USBC_PORT_C1) {
+		rst_signal = IOEX_USB_C1_RT_RST_ODL;
+	} else {
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * We do not have a load switch for the burnside bridge chips,
+	 * so we only need to sequence reset.
+	 */
+
+	if (enable) {
+		/*
+		 * Tpw, minimum time from VCC to RESET_N de-assertion is 100us.
+		 * For boards that don't provide a load switch control, the
+		 * retimer_init() function ensures power is up before calling
+		 * this function.
+		 */
+		ioex_set_level(rst_signal, 1);
+		/*
+		 * Allow 1ms time for the retimer to power up lc_domain
+		 * which powers I2C controller within retimer
+		 */
+		msleep(1);
+	} else {
+		ioex_set_level(rst_signal, 0);
+		msleep(1);
+	}
+	return EC_SUCCESS;
+}
+
+__override int bb_retimer_reset(const struct usb_mux *me)
+{
+	/*
+	 * TODO(b/193402306, b/195375738): Remove this once transition to
+	 * QS Silicon is complete
+	 */
+	bb_retimer_power_enable(me, false);
+	msleep(5);
+	bb_retimer_power_enable(me, true);
+	msleep(25);
+
+	return EC_SUCCESS;
+}
+
+void board_reset_pd_mcu(void)
+{
+	enum gpio_signal tcpc_rst;
+
+	tcpc_rst = GPIO_USB_C0_C1_TCPC_RST_ODL;
+
+	/*
+	 * TODO(b/179648104): figure out correct timing
+	 */
+
+	gpio_set_level(tcpc_rst, 0);
+
+	/*
+	 * delay for power-on to reset-off and min. assertion time
+	 */
+
+	msleep(20);
+
+	gpio_set_level(tcpc_rst, 1);
+
+	/* wait for chips to come up */
+
+	msleep(50);
+}
+
+static void enable_ioex(int ioex)
+{
+	ioex_init(ioex);
+}
+
+static void board_tcpc_init(void)
+{
+	/* Don't reset TCPCs after initial reset */
+	if (!system_jumped_late()) {
+		board_reset_pd_mcu();
+
+		/*
+		 * These IO expander pins are implemented using the
+		 * C0/C1 TCPC, so they must be set up after the TCPC has
+		 * been taken out of reset.
+		 */
+		enable_ioex(IOEX_C0_NCT38XX);
+		enable_ioex(IOEX_C1_NCT38XX);
+	}
+
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_C1_TCPC_INT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (gpio_get_level(GPIO_USB_C0_C1_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_0 | PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
+
+int ppc_get_alert_status(int port)
+{
+	if (port == USBC_PORT_C0)
+		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
+	else if (port == USBC_PORT_C1)
+		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
+	return 0;
+}
+
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_C1_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C0);
+		break;
+	default:
+		break;
+	}
+}
+
+void bc12_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_BC12_INT_ODL:
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+		break;
+	case GPIO_USB_C1_BC12_INT_ODL:
+		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+		break;
+	default:
+		break;
+	}
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C1);
+		break;
+	default:
+		break;
+	}
+}
+
+void retimer_interrupt(enum gpio_signal signal)
+{
+	/*
+	 * TODO(b/179513527): add USB-C support
+	 */
+}
+
+__override bool board_is_dts_port(int port)
+{
+	return port == USBC_PORT_C0;
+}
+
+__override bool board_is_tbt_usb4_port(int port)
+{
+	return true;
+}
+
+__override enum tbt_compat_cable_speed board_get_max_tbt_speed(int port)
+{
+	if (!board_is_tbt_usb4_port(port))
+		return TBT_SS_RES_0;
+
+	return TBT_SS_TBT_GEN3;
+}
diff --git a/board/aurash/usbc_config.h b/board/aurash/usbc_config.h
new file mode 100644
index 0000000000..28e43d0e9d
--- /dev/null
+++ b/board/aurash/usbc_config.h
@@ -0,0 +1,15 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Aurash board-specific USB-C configuration */
+
+#ifndef __CROS_EC_USBC_CONFIG_H
+#define __CROS_EC_USBC_CONFIG_H
+
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
+
+#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/aurash/vif_override.xml b/board/aurash/vif_override.xml
new file mode 100644
index 0000000000..9fc397cd40
--- /dev/null
+++ b/board/aurash/vif_override.xml
@@ -0,0 +1,129 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
+
+<?xml version="1.0" encoding="utf-8"?>
+<vif:VIF xmlns="http://usb.org/VendorInfoFile.xsd">
+  <vif:Product_Revision>2</vif:Product_Revision>
+  <vif:TID>0</vif:TID>
+  <vif:Product>
+    <!--Product Level Content:-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;USB4™ Product-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:USB4_Num_Internal_Host_Controllers value="1" />
+    <vif:USB4_Num_PCIe_DN_Bridges value="0" />
+    <!--Bundle: USB4RouterList-->
+    <vif:USB4RouterList>
+      <vif:Usb4Router>
+        <!--USB4 Router 0-->
+        <vif:USB4_Router_ID value="0" />
+        <vif:USB4_Silicon_VID value="32903">8087</vif:USB4_Silicon_VID>
+        <vif:USB4_Num_Lane_Adapters value="4" />
+        <vif:USB4_Num_USB3_DN_Adapters value="1" />
+        <vif:USB4_Num_DP_IN_Adapters value="1" />
+        <vif:USB4_Num_DP_OUT_Adapters value="0" />
+        <vif:USB4_Num_PCIe_DN_Adapters value="4" />
+        <vif:USB4_TBT3_Not_Supported value="0">TBT3 Compatible</vif:USB4_TBT3_Not_Supported>
+        <vif:USB4_PCIe_Wake_Supported value="true" />
+        <vif:USB4_USB3_Wake_Supported value="false" />
+        <vif:USB4_Num_Unused_Adapters value="0" />
+        <vif:USB4_TBT3_VID value="32903">8087</vif:USB4_TBT3_VID>
+        <vif:USB4_PCIe_Switch_Vendor_ID value="32902">8086</vif:USB4_PCIe_Switch_Vendor_ID>
+        <vif:USB4_PCIe_Switch_Device_ID value="17982">463E</vif:USB4_PCIe_Switch_Device_ID>
+      </vif:Usb4Router>
+    </vif:USB4RouterList>
+  </vif:Product>
+  <vif:Component>
+    <!--Component 0: Port 0-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;USB4™ Port-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:USB4_Lane_0_Adapter value="1" />
+    <vif:USB4_Max_Speed value="1">Gen 3 (40Gb)</vif:USB4_Max_Speed>
+    <vif:USB4_DFP_Supported value="true" />
+    <vif:USB4_UFP_Supported value="false" />
+    <vif:USB4_USB3_Tunneling_Supported value="true" />
+    <vif:USB4_DP_Tunneling_Supported value="true" />
+    <vif:USB4_CL1_State_Supported value="true" />
+    <vif:USB4_CL2_State_Supported value="true" />
+    <vif:USB4_Num_Retimers value="1" />
+    <vif:USB4_DP_Bit_Rate value="3">HBR3</vif:USB4_DP_Bit_Rate>
+    <vif:USB4_Num_DP_Lanes value="4">4 Lanes</vif:USB4_Num_DP_Lanes>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;USB Host-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Host_Speed value="2">USB 3.2 Gen 2x1</vif:Host_Speed>
+    <vif:Host_Contains_Captive_Retimer value="true" />
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:Host_Suspend_Supported value="true" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Source-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:USB_Suspend_May_Be_Cleared value="true" />
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="3">3A @ 5V</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <!--Bundle: SrcPdoList-->
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!--Source PDO 1-->
+        <vif:Src_PD_OCP_OC_Debounce value="50">50 msec</vif:Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="360">3600 mA</vif:Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Dual Role-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:FR_Swap_Supported_As_Initial_Sink value="true" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;SOP Discover ID-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Product_Type_UFP_SOP value="3">PSD</vif:Product_Type_UFP_SOP>
+    <vif:Product_Type_DFP_SOP value="2">PDUSB Host</vif:Product_Type_DFP_SOP>
+  </vif:Component>
+  <vif:Component>
+    <!--Component 1: Port 1-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;USB4™ Port-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:USB4_Lane_0_Adapter value="1" />
+    <vif:USB4_Max_Speed value="1">Gen 3 (40Gb)</vif:USB4_Max_Speed>
+    <vif:USB4_DFP_Supported value="true" />
+    <vif:USB4_UFP_Supported value="false" />
+    <vif:USB4_USB3_Tunneling_Supported value="true" />
+    <vif:USB4_DP_Tunneling_Supported value="true" />
+    <vif:USB4_CL1_State_Supported value="true" />
+    <vif:USB4_CL2_State_Supported value="true" />
+    <vif:USB4_Num_Retimers value="1" />
+    <vif:USB4_DP_Bit_Rate value="3">HBR3</vif:USB4_DP_Bit_Rate>
+    <vif:USB4_Num_DP_Lanes value="4">4 Lanes</vif:USB4_Num_DP_Lanes>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;USB Host-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Host_Speed value="2">USB 3.2 Gen 2x1</vif:Host_Speed>
+    <vif:Host_Contains_Captive_Retimer value="true" />
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:Host_Suspend_Supported value="true" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Source-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:USB_Suspend_May_Be_Cleared value="true" />
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="3">3A @ 5V</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <!--Bundle: SrcPdoList-->
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!--Source PDO 1-->
+        <vif:Src_PD_OCP_OC_Debounce value="50">50 msec</vif:Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="360">3600 mA</vif:Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Dual Role-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:FR_Swap_Supported_As_Initial_Sink value="true" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;SOP Discover ID-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Product_Type_UFP_SOP value="3">PSD</vif:Product_Type_UFP_SOP>
+    <vif:Product_Type_DFP_SOP value="2">PDUSB Host</vif:Product_Type_DFP_SOP>
+  </vif:Component>
+</vif:VIF>
diff --git a/board/baklava/board.c b/board/baklava/board.c
new file mode 100644
index 0000000000..7b945a11d9
--- /dev/null
+++ b/board/baklava/board.c
@@ -0,0 +1,356 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Baklava board-specific configuration */
+
+#include "common.h"
+#include "driver/ppc/sn5s330.h"
+#include "driver/tcpm/ps8xxx.h"
+#include "driver/tcpm/stm32gx.h"
+#include "driver/tcpm/tcpci.h"
+#include "driver/usb_mux/ps8822.h"
+#include "ec_version.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "switch.h"
+#include "system.h"
+#include "task.h"
+#include "uart.h"
+#include "usb_descriptor.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_dp_ufp.h"
+#include "usb_pe_sm.h"
+#include "usb_prl_sm.h"
+#include "usb_tc_sm.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+
+#define QUICHE_PD_DEBUG_LVL 1
+
+#ifdef SECTION_IS_RW
+#define CROS_EC_SECTION "RW"
+#else
+#define CROS_EC_SECTION "RO"
+#endif
+
+#ifdef SECTION_IS_RW
+static int pd_dual_role_init[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	PD_DRP_TOGGLE_ON,
+};
+
+static void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_HOST_USBC_PPC_INT_ODL:
+		sn5s330_interrupt(USB_PD_PORT_HOST);
+		break;
+	default:
+		break;
+	}
+}
+
+void hpd_interrupt(enum gpio_signal signal)
+{
+	usb_pd_hpd_edge_event(signal);
+}
+
+static void board_uf_manage_vbus_interrupt(enum gpio_signal signal)
+{
+	baseboard_usb3_check_state();
+}
+
+static void board_pwr_btn_interrupt(enum gpio_signal signal)
+{
+	baseboard_power_button_evt(gpio_get_level(signal));
+}
+
+static void board_usbc_usb3_interrupt(enum gpio_signal signal)
+{
+	baseboard_usbc_usb3_irq();
+}
+#endif /* SECTION_IS_RW */
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/*
+ * Table GPIO signals control both power rails and reset lines to various chips
+ * on the board. The order the signals are changed and the delay between GPIO
+ * signals is driven by USB/MST hub power sequencing requirements.
+ */
+const struct power_seq board_power_seq[] = {
+	{ GPIO_EN_AC_JACK, 1, 20 },
+	{ GPIO_EC_DFU_MUX_CTRL, 0, 0 },
+	{ GPIO_EN_PP5000_A, 1, 31 },
+	{ GPIO_MST_LP_CTL_L, 1, 0 },
+	{ GPIO_EN_PP3300_B, 1, 1 },
+	{ GPIO_EN_PP1100_A, 1, 100 + 30 },
+	{ GPIO_EN_BB, 1, 30 },
+	{ GPIO_EN_PP1050_A, 1, 30 },
+	{ GPIO_EN_PP1200_A, 1, 20 },
+	{ GPIO_EN_PP5000_C, 1, 20 },
+	{ GPIO_EN_PP5000_HSPORT, 1, 31 },
+	{ GPIO_EN_DP_SINK, 1, 80 },
+	{ GPIO_MST_RST_L, 1, 61 },
+	{ GPIO_EC_HUB2_RESET_L, 1, 41 },
+	{ GPIO_EC_HUB3_RESET_L, 1, 33 },
+	{ GPIO_DP_SINK_RESET, 1, 100 },
+	{ GPIO_USBC_UF_RESET_L, 1, 33 },
+	{ GPIO_DEMUX_DP_HDMI_PD_N, 1, 10 },
+	{ GPIO_DEMUX_DP_HDMI_MODE, 1, 5 },
+};
+const size_t board_power_seq_count = ARRAY_SIZE(board_power_seq);
+
+/*
+ * Define the strings used in our USB descriptors.
+ */
+const void *const usb_strings[] = {
+	[USB_STR_DESC] = usb_string_desc,
+	[USB_STR_VENDOR] = USB_STRING_DESC("Acer"),
+	[USB_STR_PRODUCT] = USB_STRING_DESC("D501"),
+	[USB_STR_SERIALNO] = 0,
+	[USB_STR_VERSION] =
+		USB_STRING_DESC(CROS_EC_SECTION ":" CROS_EC_VERSION32),
+	[USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"),
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
+
+#ifndef SECTION_IS_RW
+/* USB-C PPC Configuration */
+struct ppc_config_t ppc_chips[] = {
+	[USB_PD_PORT_HOST] = {
+		.i2c_port = I2C_PORT_I2C1,
+		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	},
+};
+#endif
+
+#ifdef SECTION_IS_RW
+/*
+ * PS8802 set mux board tuning.
+ * Adds in board specific gain and DP lane count configuration
+ */
+static int board_ps8822_mux_set(const struct usb_mux *me, mux_state_t mux_state)
+{
+	int rv = EC_SUCCESS;
+
+	/* DP specific config */
+	if (mux_state & USB_PD_MUX_DP_ENABLED)
+		rv = ps8822_set_dp_rx_eq(me, PS8822_DPEQ_LEVEL_UP_20DB);
+
+	return rv;
+}
+
+/* TCPCs */
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	[USB_PD_PORT_HOST] = {
+		.bus_type = EC_BUS_TYPE_EMBEDDED,
+		.drv = &stm32gx_tcpm_drv,
+	},
+};
+
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	[USB_PD_PORT_HOST] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_HOST,
+			.i2c_port = I2C_PORT_I2C1,
+			.i2c_addr_flags = PS8822_I2C_ADDR3_FLAG,
+			.driver = &ps8822_usb_mux_driver,
+			.board_set = &board_ps8822_mux_set,
+		},
+	},
+};
+
+/* USB-C PPC Configuration */
+struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	[USB_PD_PORT_HOST] = { .i2c_port = I2C_PORT_I2C1,
+			       .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+			       .drv = &sn5s330_drv },
+	[USB_PD_PORT_USB3] = { .i2c_port = I2C_PORT_I2C3,
+			       .i2c_addr_flags = SN5S330_ADDR1_FLAGS,
+			       .drv = &sn5s330_drv },
+};
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+const struct hpd_to_pd_config_t hpd_config = {
+	.port = USB_PD_PORT_HOST,
+	.signal = GPIO_DDI_MST_IN_HPD,
+};
+
+void board_reset_pd_mcu(void)
+{
+	cprints(CC_SYSTEM, "Resetting TCPCs...");
+	cflush();
+
+	gpio_set_level(GPIO_USBC_UF_RESET_L, 0);
+	msleep(PS8805_FW_INIT_DELAY_MS);
+	gpio_set_level(GPIO_USBC_UF_RESET_L, 1);
+	msleep(PS8805_FW_INIT_DELAY_MS);
+}
+
+void board_enable_usbc_interrupts(void)
+{
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_HOST_USBC_PPC_INT_ODL);
+	/* Enable HPD interrupt */
+	gpio_enable_interrupt(GPIO_DDI_MST_IN_HPD);
+	/* Enable VBUS control interrupt for C1 */
+	gpio_enable_interrupt(GPIO_USBC_UF_MUX_VBUS_EN);
+}
+
+void board_disable_usbc_interrupts(void)
+{
+	/* Disable PPC interrupts. */
+	gpio_disable_interrupt(GPIO_HOST_USBC_PPC_INT_ODL);
+	/* Disable HPD interrupt */
+	gpio_disable_interrupt(GPIO_DDI_MST_IN_HPD);
+	/* Disable VBUS control interrupt for C1 */
+	gpio_disable_interrupt(GPIO_USBC_UF_MUX_VBUS_EN);
+}
+
+void board_tcpc_init(void)
+{
+	board_reset_pd_mcu();
+
+	/* Enable board usbc interrupts */
+	board_enable_usbc_interrupts();
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 2);
+
+enum pd_dual_role_states board_tc_get_initial_drp_mode(int port)
+{
+	return pd_dual_role_init[port];
+}
+
+__override uint8_t board_get_usb_pd_port_count(void)
+{
+	/*
+	 * CONFIG_USB_PD_PORT_MAX_COUNT must be defined to account for C0
+	 * and C1, but TCPMv2 only knows about C0, as C1 is a type-c only
+	 * port that is managed directly by the PS8803 TCPC.
+	 */
+	return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
+}
+
+int ppc_get_alert_status(int port)
+{
+	if (port == USB_PD_PORT_HOST)
+		return gpio_get_level(GPIO_HOST_USBC_PPC_INT_ODL) == 0;
+
+	return 0;
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	return 0;
+}
+
+void board_overcurrent_event(int port, int is_overcurrented)
+{
+	/* TODO(b/174825406): check correct operation for honeybuns */
+}
+
+int dock_get_mf_preference(void)
+{
+	return MF_ON;
+}
+
+static void board_usb_tc_connect(void)
+{
+	int port = TASK_ID_TO_PD_PORT(task_get_current());
+
+	/*
+	 * The EC needs to indicate to the MST hub when the host port is
+	 * attached. GPIO_UFP_PLUG_DET is used for this purpose.
+	 */
+	if (port == USB_PD_PORT_HOST)
+		gpio_set_level(GPIO_UFP_PLUG_DET, 0);
+}
+DECLARE_HOOK(HOOK_USB_PD_CONNECT, board_usb_tc_connect, HOOK_PRIO_DEFAULT);
+
+static void board_usb_tc_disconnect(void)
+{
+	int port = TASK_ID_TO_PD_PORT(task_get_current());
+
+	/* Only the host port disconnect is relevant */
+	if (port == USB_PD_PORT_HOST)
+		gpio_set_level(GPIO_UFP_PLUG_DET, 1);
+}
+DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, board_usb_tc_disconnect,
+	     HOOK_PRIO_DEFAULT);
+
+#endif /* SECTION_IS_RW */
+
+static void board_init(void)
+{
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+static void board_debug_gpio_1_pulse(void)
+{
+	gpio_set_level(GPIO_TRIGGER_1, 0);
+}
+DECLARE_DEFERRED(board_debug_gpio_1_pulse);
+
+static void board_debug_gpio_2_pulse(void)
+{
+	gpio_set_level(GPIO_TRIGGER_2, 0);
+}
+DECLARE_DEFERRED(board_debug_gpio_2_pulse);
+
+void board_debug_gpio(enum debug_gpio trigger, int level, int pulse_usec)
+{
+	switch (trigger) {
+	case TRIGGER_1:
+		gpio_set_level(GPIO_TRIGGER_1, level);
+		if (pulse_usec)
+			hook_call_deferred(&board_debug_gpio_1_pulse_data,
+					   pulse_usec);
+		break;
+	case TRIGGER_2:
+		gpio_set_level(GPIO_TRIGGER_2, level);
+		if (pulse_usec)
+			hook_call_deferred(&board_debug_gpio_2_pulse_data,
+					   pulse_usec);
+		break;
+	default:
+		CPRINTS("bad debug gpio selection");
+		break;
+	}
+}
+
+static int command_dplane(int argc, const char **argv)
+{
+	char *e;
+	int lane;
+
+	if (argc < 2)
+		return EC_ERROR_PARAM_COUNT;
+
+	lane = strtoi(argv[1], &e, 10);
+
+	if ((lane != 2) && (lane != 4))
+		return EC_ERROR_PARAM1;
+
+	/* put MST into reset */
+	gpio_set_level(GPIO_MST_RST_L, 0);
+	msleep(1);
+	/* Set lane control to requested level */
+	gpio_set_level(GPIO_MST_HUB_LANE_SWITCH, lane == 2 ? 1 : 0);
+	msleep(1);
+	/* Take MST out of reset */
+	gpio_set_level(GPIO_MST_RST_L, 1);
+
+	ccprintf("MST lane set:  %s, lane_ctrl = %d\n",
+		 lane == 2 ? "2 lane" : "4 lane",
+		 gpio_get_level(GPIO_MST_HUB_LANE_SWITCH));
+
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(dplane, command_dplane, "<2 | 4>", "MST lane control.");
diff --git a/board/baklava/board.h b/board/baklava/board.h
new file mode 100644
index 0000000000..8cbe1cdc76
--- /dev/null
+++ b/board/baklava/board.h
@@ -0,0 +1,98 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Baklava board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* Baseboard features */
+#include "baseboard.h"
+
+/* Optional features */
+/*
+ * For MP release, CONFIG_SYSTEM_UNLOCKED must be undefined, and
+ * CONFIG_FLASH_PSTATE_LOCKED must be defined in order to enable write protect
+ * using option bytes WRP registers.
+ */
+#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
+#undef CONFIG_FLASH_PSTATE_LOCKED
+
+/* USB Type C and USB PD defines */
+#define USB_PD_PORT_HOST 0
+#define USB_PD_PORT_USB3 1
+
+/*
+ * Only the host and display usbc ports are usb-pd capable. There is a 2nd usbc
+ * port, but this is type-c capable only. Only the PPC for this port needs to be
+ * controlled by FW.
+ */
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#define CONFIG_USB_MUX_PS8822
+
+#undef CONFIG_USB_VID
+#define CONFIG_USB_VID 0x502
+#define CONFIG_USB_PID 0x1195
+#define CONFIG_USB_BCD_DEV 0x0001 /* v 0.01 */
+#define CONFIG_USB_PD_IDENTITY_HW_VERS 1
+#define CONFIG_USB_PD_IDENTITY_SW_VERS 1
+
+/* I2C port names */
+#define I2C_PORT_I2C1 0
+#define I2C_PORT_I2C2 1
+#define I2C_PORT_I2C3 2
+
+/* Required symbolic I2C port names */
+#define I2C_PORT_MP4245 I2C_PORT_I2C3
+#define I2C_PORT_EEPROM I2C_PORT_I2C3
+#define MP4245_I2C_ADDR_FLAGS MP4245_I2C_ADDR_0_FLAGS
+
+/* Include math_util for bitmask_uint64 used in pd_timers */
+#define CONFIG_MATH_UTIL
+
+#ifndef __ASSEMBLER__
+
+#include "registers.h"
+
+#define GPIO_DP_HPD GPIO_DDI_MST_IN_HPD
+#define GPIO_USBC_UF_ATTACHED_SRC GPIO_USBC_UF_MUX_VBUS_EN
+#define GPIO_BPWR_DET GPIO_HUB_BPWRDET
+#define GPIO_USB_HUB_OCP_NOTIFY GPIO_USBC_DATA_OCP_NOTIFY
+#define GPIO_UFP_PLUG_DET GPIO_MST_UFP_PLUG_DET
+
+#define BUTTON_PRESSED_LEVEL 1
+#define BUTTON_RELEASED_LEVEL 0
+
+#define GPIO_TRIGGER_1 GPIO_USB3_A5_CDP_EN
+#define GPIO_TRIGGER_2 GPIO_USB3_A6_CDP_EN
+
+enum debug_gpio {
+	TRIGGER_1 = 0,
+	TRIGGER_2,
+};
+
+/*
+ * Function used to control GPIO signals as a timing marker. This is intended to
+ * be used for development/debugging purposes.
+ *
+ * @param trigger GPIO debug signal selection
+ * @param level desired level of the debug gpio signal
+ * @param pulse_usec pulse width if non-zero
+ */
+void board_debug_gpio(enum debug_gpio trigger, int level, int pulse_usec);
+
+/*
+ * Function called in power on case to enable usbc related interrupts
+ */
+void board_enable_usbc_interrupts(void);
+
+/*
+ * Function called in power off case to disable usbc related interrupts
+ */
+void board_disable_usbc_interrupts(void);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/baklava/build.mk b/board/baklava/build.mk
new file mode 100644
index 0000000000..258bafe87d
--- /dev/null
+++ b/board/baklava/build.mk
@@ -0,0 +1,14 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=stm32
+CHIP_FAMILY:=stm32g4
+CHIP_VARIANT:=stm32g473xc
+BASEBOARD:=honeybuns
+
+board-y=board.o
diff --git a/board/baklava/dev_key.pem b/board/baklava/dev_key.pem
new file mode 100644
index 0000000000..4897ceb44e
--- /dev/null
+++ b/board/baklava/dev_key.pem
@@ -0,0 +1,39 @@
+-----BEGIN RSA PRIVATE KEY-----
+MIIG4wIBAAKCAYEAyiT9PsD2wW3mhfuxMtihnLDKC+PY9l6j+j405G5Wd3BBtLLl
+2uEoSD8cFQfnVTeFH7wggVf+SMAP3Y2aTnXIfdTX3N0skAdq/kYNUlQAK0xsa3Z7
+bRZ8puvzu+XNqsSS/tvsdYbNE5WC5sXtt7Wkm3mKn7PAti7oQrKbW1beFD0FgdAq
+JoweIdpkuOwDYtFBcF92LWWGziDcEXlc2v5Xj3qvixMLnhy+Ny1Byr2ApVaYZ56H
+JfjHKxbirNj4IrgmhdzfBIKxDf4mGibG0K1aC1io+SixtRV1cS6JRB0D+GS4QIcq
+y9bCMkBeVQLHhSo1UYZqbB7Qef0blQ2sxsXklo8Q5EIQOd6yiXiTelApOWDn3zTi
+uTkUo+99SPDLw/S3sR3uESxt+OYO2Yt6BWe2JSYBhHWB0Xc0PGItq7DUpm2cEWke
+vS91I/lBfqhOxQOvnEx5NM97/RBQMa3jJ5Jv/72X5oU6OcGmaliBJy3Tv0CSiI06
+qgRgWxMym/XA0ui/AgEDAoIBgQCGw1N/K08rnpmup8t3OxZoddwH7TtO6cKm1CNC
+9Dmk9YEjIe6R63AwKhK4r++OJQNqfWsA5VQwgAqTs7w0ToWpOI/ok3MKr5yphAjh
+jVVyMvLyTvzzZFMZ8qJ9Q95x2GH/PUhOWd4NDldEg/PPzm28+7G/zSskH0WBzGeS
+Oeli01kBNXFvCBQWkZh7SAJB4NZK6k7I7lnewJK2UOiR/uUKUcpct10UEyl6Hivc
+flXDjxBFFFoZUITHZJcd5frB0Bh+EiqJ3CnkSIjD4sTnZs/TP8CKhmYriabfBHdH
+j6ffcr5y8VhqDJK/ISSmWQO1c/rSziJLhx/ZrWvWp1FAbRg+kdh+RmV8hYIdEOq8
+PYOiERihd+eHVhtzsc74+cRGxPbaFJ2rpuJt+xk1Zp7IfGyyPWDmvXFKZgX+vo2s
+vJL6q9pPR57uUHL0xsxDrMH3HFxkl1ta5PsiBGXs+zG0EUzNKGtoRTCi176xUWyo
+NG+eWiL9ddeZVBzWeKfJGfwQ53sCgcEA+JE2E5kjvVCasSqERfDfIkSeOKoqWdZ2
+sAvTHibq6+vMBkRubNA0glHcUrMEBblDg3ds2z1A9YvwjwEUq9UFpVH3qfX9vaTX
+lLYFRZjcA3PkCJvFAt5eIlVXp+vgaEo6OcodLjDiqkYKzbMC13k5uM1wsEEwo2vI
+38vhHQlH1PHVTd8pt2Y7mOpDgxOOJLrvwuew7Lj9QSBRZ0EJxqv+1QA4EQ1cPr1H
+hGqggtL0ChLRV7KBHiLz9ggS5vHTEkFNAoHBANAwaSIfTnpAvkMoGy+iQyw0afC0
+7hnwhHKcAzqenT1Mzo3Yt7/zsZE8ywjKPe9C+ZHZyh+W373tCUQRnjpNOpNiVHzi
+ekFxl8kpLhpbB8LTXuRlQmtZjVQPbyuORPGDCzA05GGBN6mnXju+iQEz2WD8f3oY
+Jz5yYl54eAuMsFl5/0yehqBQjRvky5YRna2eNUKBvz+/BgjpZeb0DtLMffcAvrkQ
+FQbAwNvzvagMOEemjLSp9iXjQSNWJAdc86dMOwKBwQCltiQNEMJ+Nbx2HFguoJTB
+gxQlxsbmjvnKsoy+xJydR91ZgvRIis2sNpLhzK1ZJi0CT53nfitOXUsKALhyjgPD
+i/pxTqkpGI+4eVjZEJKs9+1bEoNXPulsOOUanUBFhtF73BN0IJccLrHed1c6UNEl
+3ksgK3XCR9s/3UC+Bi/jS+OJP3Ek7tJl8YJXYl7DJ0qB78tIe1OAwDZE1gaEcqnj
+VXq2COgp04UC8cBXN01cDIuPzFYUF01OsAyZ9oy21jMCgcEAisrwwWo0UYB+13AS
+H8GCHXhGoHieu/Wtob1XfGm+KN3fCTslKqJ2YNMyBdwpSiymYTvcFQ8/0/NbgrZp
+fDN8YkGNqJb8K6EP23DJZudageI/Qu4sR5EI4rT0x7Qt9ldcys3tllYlG8TpfSmw
+q3fmQKhU/BAaKaGW6aWlXQh1kPv/iGmvFYsIvUMyZAu+c77OLFZ/f9SusJuZRKK0
+jIhT+gB/Jgq4rysrPU0pGrLQL8RdzcakGUIrbOQYBOiib4gnAoHAVrvbmZGxyeeA
+oDE2QlXXmd1higPaQe3u+7vmh6itVpJ71n9wmu9xei7IiTOtGDYjHLXa8Qg0y37/
+FVCUiFxhOz05hpnB1ts70tuIWUJbWttMnhZPTpKa1dzZFB6qrlk2o/ONaSfNzpOZ
+FgKxBURFVzNMTlIh7QOZGoOeRg5BkFG5z21g8egYQ/1cY61BhaxJTz93HGKb0jYn
+QnC0WfVF9amWNGwocKATkwjoSVC7rQRsB2FMbY/WCqgE92lXsU9W
+-----END RSA PRIVATE KEY-----
diff --git a/board/baklava/ec.tasklist b/board/baklava/ec.tasklist
new file mode 100644
index 0000000000..a478fbe2e0
--- /dev/null
+++ b/board/baklava/ec.tasklist
@@ -0,0 +1,16 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS_RO(RWSIG,    rwsig_task,   NULL, 1280) \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS_RW(POWER_BUTTON, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS_RW(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS_RW(UCPD, ucpd_task, 0, LARGER_TASK_STACK_SIZE)
diff --git a/board/baklava/gpio.inc b/board/baklava/gpio.inc
new file mode 100644
index 0000000000..2745ae7caf
--- /dev/null
+++ b/board/baklava/gpio.inc
@@ -0,0 +1,93 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+#ifdef SECTION_IS_RW
+GPIO_INT(HOST_USBC_PPC_INT_ODL,  PIN(D,  9),      GPIO_INT_FALLING | GPIO_PULL_UP, ppc_interrupt)
+GPIO_INT(DDI_MST_IN_HPD,         PIN(C,  14),     GPIO_INT_BOTH, hpd_interrupt)
+GPIO_INT(USBC_UF_MUX_VBUS_EN,    PIN(C,  12),     GPIO_INT_BOTH, board_uf_manage_vbus_interrupt)
+GPIO_INT(PWR_BTN,                PIN(A,  0),      GPIO_INT_BOTH, board_pwr_btn_interrupt)
+GPIO_INT(USBC_UF_PPC_INT_ODL,    PIN(B,  5),      GPIO_INT_FALLING | GPIO_PULL_UP, board_usbc_usb3_interrupt)
+#endif
+
+/* Power sequencing signals */
+GPIO(EN_AC_JACK,                    PIN(A,  1), GPIO_OUT_LOW)
+GPIO(EN_BB,                         PIN(A,  8), GPIO_OUT_LOW)
+GPIO(EN_PP3300_B,                   PIN(B,  2), GPIO_OUT_LOW)
+GPIO(EN_PP5000_A,                   PIN(C,  6), GPIO_OUT_LOW)
+GPIO(EN_PP1200_A,                   PIN(E,  8), GPIO_OUT_LOW)
+GPIO(EN_PP1100_A,                   PIN(C,  7), GPIO_OUT_LOW)
+GPIO(EN_PP1050_A,                   PIN(A,  2), GPIO_OUT_LOW)
+GPIO(EN_PP5000_C,                   PIN(D,  1), GPIO_OUT_LOW)
+GPIO(EN_PP5000_HSPORT,              PIN(D,  0), GPIO_OUT_LOW)
+
+/* MST Hub signals */
+GPIO(MST_LP_CTL_L,                  PIN(D, 10), GPIO_ODR_LOW)
+GPIO(MST_RST_L,                     PIN(E, 14), GPIO_ODR_LOW)
+GPIO(MST_HUB_LANE_SWITCH,           PIN(C, 15), GPIO_OUT_HIGH)
+GPIO(MST_UFP_PLUG_DET,              PIN(B, 12), GPIO_OUT_HIGH)
+
+/* Display Demux signals */
+GPIO(DEMUX_DP_HDMI_MODE,            PIN(E, 15), GPIO_OUT_LOW)
+GPIO(DEMUX_DP_HDMI_PD_N,            PIN(B, 13), GPIO_ODR_LOW)
+
+/* USBC Mux and Demux Signals */
+GPIO(EN_DP_SINK,                    PIN(B, 14), GPIO_OUT_LOW)
+GPIO(DP_SINK_RESET,                 PIN(B, 15), GPIO_OUT_LOW)
+GPIO(USBC_UF_RESET_L,               PIN(D,  2), GPIO_ODR_LOW)
+
+/* USB Hubs signals */
+GPIO(EC_HUB2_RESET_L,               PIN(C,  5), GPIO_ODR_LOW)
+GPIO(EC_HUB3_RESET_L,               PIN(B, 10), GPIO_ODR_LOW)
+GPIO(USBC_DATA_OCP_NOTIFY,          PIN(C,  2), GPIO_OUT_HIGH)
+GPIO(HUB_BPWRDET,                   PIN(C,  1), GPIO_OUT_LOW)
+
+/* USB-A Current limit switches, set default to 1.5A */
+GPIO(GBE_RESET_EC,                  PIN(C,  0), GPIO_OUT_LOW)
+GPIO(EC_DFU_MUX_CTRL,               PIN(C,  3), GPIO_OUT_HIGH)
+GPIO(USB3_A5_CDP_EN,                PIN(B,  9), GPIO_OUT_LOW)
+GPIO(USB3_A6_CDP_EN,                PIN(C, 13), GPIO_OUT_LOW)
+
+
+/* Write protect */
+GPIO(EC_FLASH_WP_ODL,               PIN(A,  3), GPIO_ODR_HIGH)
+GPIO(EC_WP_L,                       PIN(E, 11), GPIO_INT_BOTH)
+
+/* UART Bus */
+GPIO(EC_UART_TX,                    PIN(C, 10), GPIO_INT_BOTH)
+GPIO(EC_UART_RX,                    PIN(C, 11), GPIO_INT_BOTH)
+
+/*
+ * I2C SCL/SDA pins. These will normally be under control of the peripheral from
+ * alt fucntion setting below. But if a port gets wedged, the unwedge code uses
+ * these signals as regular GPIOs.
+ */
+GPIO(EC_I2C1_SCL,                   PIN(A, 15),  GPIO_ODR_HIGH)
+GPIO(EC_I2C1_SDA,                   PIN(B,  7),  GPIO_ODR_HIGH)
+GPIO(EC_I2C3_SCL,                   PIN(C,  8),  GPIO_ODR_HIGH)
+GPIO(EC_I2C3_SDA,                   PIN(C,  9),  GPIO_ODR_HIGH)
+
+/* misc signals */
+GPIO(BOOT0,                         PIN(B,  8),  GPIO_INPUT)
+
+/* Unimplemented signals since we are not an EC */
+UNIMPLEMENTED(ENTERING_RW)
+
+/* USART3_TX/RX GPIOC 10-11*/
+ALTERNATE(PIN_MASK(C, 0x0C00),  7, MODULE_UART,  GPIO_PULL_UP)
+/* I2C Ports
+ *   I2C1: SDA/SCL -> PB7/PA15
+ *   I2C2: SDA/SCL -> PA8/PA9
+ *   I2C3: SDA/SCL -> PC8/PC9
+ */
+ALTERNATE(PIN_MASK(B, 0x0080),  4, MODULE_I2C,   GPIO_OPEN_DRAIN)
+ALTERNATE(PIN_MASK(A, 0X8000),  4, MODULE_I2C,   GPIO_OPEN_DRAIN)
+ALTERNATE(PIN_MASK(C, 0x0300),  8, MODULE_I2C,   GPIO_OPEN_DRAIN)
+/* GPIOA4-7: SPI Signals */
+ALTERNATE(PIN_MASK(A, 0x00F0),  5, MODULE_SPI,   0)
diff --git a/board/banshee/battery.c b/board/banshee/battery.c
new file mode 100644
index 0000000000..35d6a7a935
--- /dev/null
+++ b/board/banshee/battery.c
@@ -0,0 +1,77 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "cbi.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "gpio.h"
+/*
+ * Battery info for all Banshee battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	/* NVT Battery Information */
+	[BATTERY_NVT] = {
+		.fuel_gauge = {
+			.manuf_name = "NVT",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x2000,
+				.disconnect_val = 0x2000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= TARGET_WITH_MARGIN(17600, 5),
+			.voltage_normal		= 15400, /* mV */
+			.voltage_min		= 12000, /* mV */
+			.precharge_current	= 72,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 55,
+			.charging_min_c		= 0,
+			.charging_max_c		= 55,
+			.discharging_min_c	= 0,
+			.discharging_max_c	= 70,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_NVT;
+
+enum battery_present battery_hw_present(void)
+{
+	enum gpio_signal batt_pres;
+
+	batt_pres = GPIO_EC_BATT_PRES_ODL;
+
+	/* The GPIO is low when the battery is physically present */
+	return gpio_get_level(batt_pres) ? BP_NO : BP_YES;
+}
diff --git a/board/banshee/board.c b/board/banshee/board.c
new file mode 100644
index 0000000000..55922d056b
--- /dev/null
+++ b/board/banshee/board.c
@@ -0,0 +1,149 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "button.h"
+#include "charge_ramp.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "driver/als_tcs3400.h"
+#include "driver/charger/isl9241.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "keyboard_customization.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "registers.h"
+#include "switch.h"
+#include "throttle_ap.h"
+#include "usbc_config.h"
+#include "watchdog.h"
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* Console output macros */
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+
+/* Called on AP S3 -> S0 transition */
+static void board_chipset_resume(void)
+{
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S0 -> S3 transition */
+static void board_chipset_suspend(void)
+{
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
+
+void board_set_charger_current_limit_deferred(void)
+{
+	int action;
+	int rv;
+
+	if (extpower_is_present() &&
+	    (battery_get_disconnect_state() != BATTERY_NOT_DISCONNECTED))
+		/* AC only or AC+DC but battery is disconnect */
+		action = MASK_SET;
+	else
+		action = MASK_CLR;
+
+	rv = i2c_update16(chg_chips[CHARGER_SOLO].i2c_port,
+			  chg_chips[CHARGER_SOLO].i2c_addr_flags,
+			  ISL9241_REG_CONTROL3,
+			  ISL9241_CONTROL3_INPUT_CURRENT_LIMIT, action);
+
+	if (rv)
+		CPRINTF("Could not set charger input current limit! Error: %d\n",
+			rv);
+}
+
+DECLARE_DEFERRED(board_set_charger_current_limit_deferred);
+DECLARE_HOOK(HOOK_SECOND, board_set_charger_current_limit_deferred,
+	     HOOK_PRIO_DEFAULT);
+
+void battery_present_interrupt(enum gpio_signal signal)
+{
+	hook_call_deferred(&board_set_charger_current_limit_deferred_data, 0);
+}
+
+static uint32_t board_id;
+static void configure_keyboard(void)
+{
+	uint32_t cbi_val;
+
+	/* Board ID */
+	if (cbi_get_board_version(&cbi_val) != EC_SUCCESS ||
+	    cbi_val > UINT8_MAX)
+		CPRINTS("CBI: Read Board ID failed");
+	else
+		board_id = cbi_val;
+
+	CPRINTS("Read Board ID: %d", board_id);
+
+	if (board_id == 0) {
+		/* keyboard_col2_inverted on board id 0 */
+		gpio_set_flags(GPIO_EC_KSO_04_INV, GPIO_ODR_HIGH);
+		gpio_set_flags(GPIO_EC_KSO_05_INV, GPIO_ODR_HIGH);
+		gpio_set_alternate_function(GPIO_PORT_1, (BIT(4) | BIT(5)),
+					    GPIO_ALT_FUNC_DEFAULT);
+	} else if (board_id == 1) {
+		/* keyboard_col4_inverted on board id 1 */
+		gpio_set_flags(GPIO_EC_KSO_02_INV, GPIO_ODR_HIGH);
+		gpio_set_flags(GPIO_EC_KSO_05_INV, GPIO_ODR_HIGH);
+		gpio_set_alternate_function(GPIO_PORT_1, (BIT(4) | BIT(7)),
+					    GPIO_ALT_FUNC_DEFAULT);
+	} else {
+		/* keyboard_col5_inverted on board id 2 and later */
+		gpio_set_flags(GPIO_EC_KSO_02_INV, GPIO_ODR_HIGH);
+		gpio_set_flags(GPIO_EC_KSO_04_INV, GPIO_ODR_HIGH);
+		gpio_set_alternate_function(GPIO_PORT_1, (BIT(5) | BIT(7)),
+					    GPIO_ALT_FUNC_DEFAULT);
+		key_typ.col_refresh = KEYBOARD_COL_ID2_REFRESH;
+		key_typ.row_refresh = KEYBOARD_ROW_ID2_REFRESH;
+	}
+
+	board_id_keyboard_col_inverted((int)board_id);
+}
+
+void board_init(void)
+{
+	gpio_enable_interrupt(GPIO_EC_BATT_PRES_ODL);
+	hook_call_deferred(&board_set_charger_current_limit_deferred_data, 0);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+__override void board_pre_task_i2c_peripheral_init(void)
+{
+	/* Configure board specific keyboard */
+	configure_keyboard();
+
+	/* Workaround for b:238683420 with board id >= 2 */
+
+#ifdef SECTION_IS_RO
+	if (board_id >= 2) {
+		udelay(500 * MSEC);
+		watchdog_reload();
+		CPRINTS("Add delay to check boot key");
+	}
+#endif
+}
+
+__override uint8_t board_keyboard_row_refresh(void)
+{
+	if (board_id < 2)
+		return KEYBOARD_ROW_ID1_REFRESH;
+	else
+		return KEYBOARD_ROW_ID2_REFRESH;
+}
diff --git a/board/banshee/board.h b/board/banshee/board.h
new file mode 100644
index 0000000000..c456a17e68
--- /dev/null
+++ b/board/banshee/board.h
@@ -0,0 +1,252 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Banshee board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "compile_time_macros.h"
+
+/*
+ * Early banshee boards are not set up for vivaldi
+ */
+#undef CONFIG_KEYBOARD_VIVALDI
+
+/* Baseboard features */
+#include "baseboard.h"
+
+#undef CONFIG_TABLET_MODE
+#undef CONFIG_TABLET_MODE_SWITCH
+#undef CONFIG_GMR_TABLET_MODE
+
+/* No side buttons */
+#undef CONFIG_MKBP_INPUT_DEVICES
+#undef CONFIG_VOLUME_BUTTONS
+
+/*
+ * This will happen automatically on NPCX9 ES2 and later. Do not remove
+ * until we can confirm all earlier chips are out of service.
+ */
+#define CONFIG_HIBERNATE_PSL_VCC1_RST_WAKEUP
+
+#define CONFIG_MP2964
+
+/* KEYBOARD */
+#define CONFIG_KEYBOARD_MULTIPLE
+#define CONFIG_KEYBOARD_CUSTOMIZATION
+#define CONFIG_KEYBOARD_VIVALDI
+
+/* LED */
+#define CONFIG_LED_PWM_COUNT 2
+#define CONFIG_LED_PWM_TASK_DISABLED
+#define CONFIG_CMD_LEDTEST
+
+/* CM32183 ALS */
+#define CONFIG_ALS
+#define ALS_COUNT 1
+#define CONFIG_ALS_CM32183
+
+/* Enable sensor fifo, must also define the _SIZE and _THRES */
+#define CONFIG_ACCEL_FIFO
+/* FIFO size is in power of 2. */
+#define CONFIG_ACCEL_FIFO_SIZE 256
+/* Depends on how fast the AP boots and typical ODRs */
+#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
+
+/* Sensors without hardware FIFO are in forced mode */
+#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(CLEAR_ALS)
+
+/* USB Type C and USB PD defines */
+#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
+
+#define CONFIG_IO_EXPANDER
+#define CONFIG_IO_EXPANDER_NCT38XX
+#define CONFIG_IO_EXPANDER_PORT_COUNT 4
+
+#define CONFIG_USB_PD_FRS_PPC
+
+#define CONFIG_USBC_RETIMER_INTEL_BB
+
+/* I2C speed console command */
+#define CONFIG_CMD_I2C_SPEED
+
+/* I2C control host command */
+#define CONFIG_HOSTCMD_I2C_CONTROL
+
+#define CONFIG_USBC_PPC_SYV682X
+#define CONFIG_USB_PD_PPC
+
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
+
+/*
+ * Passive USB-C cables only support up to 60W.
+ */
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
+
+/*
+ * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
+ * signal.
+ */
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
+
+#define GPIO_ID_1_EC_KB_BL_EN GPIO_EC_BATT_PRES_ODL
+
+/* System has back-lit keyboard */
+#define CONFIG_PWM_KBLIGHT
+
+/* I2C Bus Configuration */
+
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+
+#define I2C_PORT_USB_C0_C1_TCPC NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C2_C3_TCPC NPCX_I2C_PORT4_1
+
+#define I2C_PORT_USB_PPC_BC12 NPCX_I2C_PORT2_0
+
+#define I2C_PORT_USB_C0_C1_MUX NPCX_I2C_PORT3_0
+#define I2C_PORT_USB_C2_C3_MUX NPCX_I2C_PORT6_1
+
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+
+#define I2C_ADDR_MP2964_FLAGS 0x20
+
+#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x56
+#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x57
+#define USBC_PORT_C2_BB_RETIMER_I2C_ADDR 0x58
+#define USBC_PORT_C3_BB_RETIMER_I2C_ADDR 0x59
+
+/* Enabling Thunderbolt-compatible mode */
+#define CONFIG_USB_PD_TBT_COMPAT_MODE
+
+/* Enabling USB4 mode */
+#define CONFIG_USB_PD_USB4
+#define CONFIG_USB_PD_DATA_RESET_MSG
+
+/*
+ * TODO: Disable BBR firmware update temporally,
+ * revert this patch once confirm BBR firmware update is ready
+ * on kernel.
+ */
+/* Retimer */
+#if 0
+#define CONFIG_USBC_RETIMER_FW_UPDATE
+#endif
+
+/* Thermal features */
+#define CONFIG_THERMISTOR
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_TEMP_SENSOR_POWER
+#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
+
+#define CONFIG_FANS FAN_CH_COUNT
+
+/* Charger defines */
+#define CONFIG_CHARGER_ISL9241
+#define CONFIG_CHARGE_RAMP_SW
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20
+
+/*
+ * Older boards have a different ADC assignment.
+ */
+
+#define CONFIG_ADC_CHANNELS_RUNTIME_CONFIG
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h" /* needed by registers.h */
+#include "registers.h"
+#include "usbc_config.h"
+
+/* I2C access in polling mode before task is initialized */
+#define CONFIG_I2C_BITBANG
+
+enum banshee_bitbang_i2c_channel {
+	I2C_BITBANG_CHAN_BRD_ID,
+	I2C_BITBANG_CHAN_COUNT
+};
+#define I2C_BITBANG_PORT_COUNT I2C_BITBANG_CHAN_COUNT
+
+enum adc_channel {
+	ADC_TEMP_SENSOR_1_DDR_SOC,
+	ADC_TEMP_SENSOR_2_AMBIENT,
+	ADC_TEMP_SENSOR_3_CHARGER,
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1_DDR_SOC,
+	TEMP_SENSOR_2_AMBIENT,
+	TEMP_SENSOR_3_CHARGER,
+	TEMP_SENSOR_COUNT
+};
+
+enum sensor_id { CLEAR_ALS = 0, SENSOR_COUNT };
+
+enum ioex_port {
+	IOEX_C0_NCT38XX = 0,
+	IOEX_C1_NCT38XX,
+	IOEX_C2_NCT38XX,
+	IOEX_C3_NCT38XX,
+	IOEX_PORT_COUNT
+};
+
+enum battery_type { BATTERY_NVT, BATTERY_TYPE_COUNT };
+
+enum pwm_channel {
+	PWM_CH_SIDE_LED_R = 0, /* PWM0 (Red charger) */
+	PWM_CH_SIDE_LED_G, /* PWM1 (Green charger) */
+	PWM_CH_SIDE_LED_B, /* PWM2 (Blue charger) */
+	PWM_CH_KBLIGHT, /* PWM3 */
+	PWM_CH_FAN, /* PWM5 */
+	PWM_CH_POWER_LED_W, /* PWM7 (white LED) */
+	PWM_CH_COUNT
+};
+
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT };
+
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT };
+
+void battery_present_interrupt(enum gpio_signal signal);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/banshee/build.mk b/board/banshee/build.mk
new file mode 100644
index 0000000000..78c675a67a
--- /dev/null
+++ b/board/banshee/build.mk
@@ -0,0 +1,26 @@
+# -*- makefile -*-
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Brya board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx9
+CHIP_VARIANT:=npcx9m3f
+BASEBOARD:=brya
+
+board-y=
+board-y+=battery.o
+board-y+=board.o
+board-y+=charger.o
+board-y+=fans.o
+board-y+=fw_config.o
+board-y+=i2c.o
+board-y+=keyboard.o
+board-y+=led.o
+board-y+=pwm.o
+board-y+=sensors.o
+board-y+=usbc_config.o
+board-y+=keyboard_customization.o
diff --git a/board/banshee/charger.c b/board/banshee/charger.c
new file mode 100644
index 0000000000..76e2712181
--- /dev/null
+++ b/board/banshee/charger.c
@@ -0,0 +1,80 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/charger/isl9241.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/* Charger Chip Configuration */
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = ISL9241_ADDR_FLAGS,
+		.drv = &isl9241_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CHARGER_NUM);
+
+int board_set_active_charge_port(int port)
+{
+	int is_valid_port = board_is_usb_pd_port_present(port);
+	int i;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTSUSB("Disabling all charger ports");
+
+		/* Disable all ports. */
+		for (i = 0; i < ppc_cnt; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (ppc_vbus_sink_enable(i, 0))
+				CPRINTSUSB("Disabling C%d as sink failed.", i);
+		}
+
+		return EC_SUCCESS;
+	} else if (!is_valid_port) {
+		return EC_ERROR_INVAL;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (ppc_is_sourcing_vbus(port)) {
+		CPRINTFUSB("Skip enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTSUSB("New charge port: C%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < ppc_cnt; i++) {
+		if (i == port)
+			continue;
+
+		if (ppc_vbus_sink_enable(i, 0))
+			CPRINTSUSB("C%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTSUSB("C%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/board/banshee/ec.tasklist b/board/banshee/ec.tasklist
new file mode 100644
index 0000000000..b193da8f9f
--- /dev/null
+++ b/board/banshee/ec.tasklist
@@ -0,0 +1,34 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ *
+ * USB_CHG_Px tasks must be contiguous (see USB_CHG_PORT_TO_TASK_ID(x)).
+ * PD_Cx tasks must be contiguous (see PD_PORT_TO_TASK_ID(x))
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, HOOKS_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, BASEBOARD_CHG_RAMP_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P2, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P3, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, BASEBOARD_CHARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, BASEBOARD_CHIPSET_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, CONSOLE_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, BASEBOARD_POWERBTN_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C2, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C3, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_shared_alert_task, (BIT(1) | BIT(0)), BASEBOARD_PD_INT_TASK_STACK_SIZE) \
+    TASK_ALWAYS(PD_INT_C1, pd_shared_alert_task, (BIT(3) | BIT(2)), BASEBOARD_PD_INT_TASK_STACK_SIZE)
diff --git a/board/banshee/fans.c b/board/banshee/fans.c
new file mode 100644
index 0000000000..72bf05527f
--- /dev/null
+++ b/board/banshee/fans.c
@@ -0,0 +1,89 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Physical fans. These are logically separate from pwm_channels. */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "fan.h"
+#include "fan_chip.h"
+#include "hooks.h"
+#include "pwm.h"
+
+/* MFT channels. These are logically separate from pwm_channels. */
+const struct mft_t mft_channels[] = {
+	[MFT_CH_0] = {
+		.module = NPCX_MFT_MODULE_1,
+		.clk_src = TCKC_LFCLK,
+		.pwm_id = PWM_CH_FAN,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
+
+static const struct fan_conf fan_conf_0 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
+	.pgood_gpio = -1,
+	.enable_gpio = GPIO_EN_PP5000_FAN,
+};
+
+/*
+ * TOOD(b/181271666): thermistor placement and calibration
+ *
+ * Prototype fan spins at about 4200 RPM at 100% PWM, this
+ * is specific to board ID 2 and might also apears in later
+ * boards as well.
+ */
+static const struct fan_rpm fan_rpm_0 = {
+	.rpm_min = 1800,
+	.rpm_start = 1800,
+	.rpm_max = 6800,
+};
+
+const struct fan_t fans[FAN_CH_COUNT] = {
+	[FAN_CH_0] = {
+		.conf = &fan_conf_0,
+		.rpm = &fan_rpm_0,
+	},
+};
+
+#ifndef CONFIG_FANS
+
+/*
+ * TODO(b/181271666): use static fan speeds until fan and sensors are
+ * tuned. for now, use:
+ *
+ *   AP off:  33%
+ *   AP  on: 100%
+ */
+
+static void fan_slow(void)
+{
+	const int duty_pct = 33;
+
+	ccprints("%s: speed %d%%", __func__, duty_pct);
+
+	pwm_enable(PWM_CH_FAN, 1);
+	pwm_set_duty(PWM_CH_FAN, duty_pct);
+}
+
+static void fan_max(void)
+{
+	const int duty_pct = 100;
+
+	ccprints("%s: speed %d%%", __func__, duty_pct);
+
+	pwm_enable(PWM_CH_FAN, 1);
+	pwm_set_duty(PWM_CH_FAN, duty_pct);
+}
+
+DECLARE_HOOK(HOOK_INIT, fan_slow, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, fan_slow, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, fan_slow, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_RESET, fan_max, HOOK_PRIO_FIRST);
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, fan_max, HOOK_PRIO_DEFAULT);
+
+#endif /* CONFIG_FANS */
diff --git a/board/banshee/fw_config.c b/board/banshee/fw_config.c
new file mode 100644
index 0000000000..dc7fe7ca2a
--- /dev/null
+++ b/board/banshee/fw_config.c
@@ -0,0 +1,53 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "fw_config.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+static union banshee_cbi_fw_config fw_config;
+BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
+
+/*
+ * FW_CONFIG defaults for brya if the CBI.FW_CONFIG data is not
+ * initialized.
+ */
+static const union banshee_cbi_fw_config fw_config_defaults = {
+	.kb_bl = KEYBOARD_BACKLIGHT_ENABLED,
+};
+
+/****************************************************************************
+ * Banshee FW_CONFIG access
+ */
+void board_init_fw_config(void)
+{
+	if (cbi_get_fw_config(&fw_config.raw_value)) {
+		CPRINTS("CBI: Read FW_CONFIG failed, using board defaults");
+		fw_config = fw_config_defaults;
+	}
+
+	if (get_board_id() == 0) {
+		/*
+		 * Early boards have a zero'd out FW_CONFIG, so replace
+		 * it with a sensible default value. If DB_USB_ABSENT2
+		 * was used as an alternate encoding of DB_USB_ABSENT to
+		 * avoid the zero check, then fix it.
+		 */
+		if (fw_config.raw_value == 0) {
+			CPRINTS("CBI: FW_CONFIG is zero, using board defaults");
+			fw_config = fw_config_defaults;
+		}
+	}
+}
+
+union banshee_cbi_fw_config get_fw_config(void)
+{
+	return fw_config;
+}
diff --git a/board/banshee/fw_config.h b/board/banshee/fw_config.h
new file mode 100644
index 0000000000..912aebca7e
--- /dev/null
+++ b/board/banshee/fw_config.h
@@ -0,0 +1,40 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __BOARD_BRYA_FW_CONFIG_H_
+#define __BOARD_BRYA_FW_CONFIG_H_
+
+#include <stdint.h>
+
+/****************************************************************************
+ * CBI FW_CONFIG layout for Banshee board.
+ *
+ * Source of truth is the project/brya/brya/config.star configuration file.
+ */
+
+enum ec_cfg_keyboard_backlight_type {
+	KEYBOARD_BACKLIGHT_DISABLED = 0,
+	KEYBOARD_BACKLIGHT_ENABLED = 1
+};
+
+union banshee_cbi_fw_config {
+	struct {
+		uint32_t sd_db : 2;
+		uint32_t lte_db : 1;
+		enum ec_cfg_keyboard_backlight_type kb_bl : 1;
+		uint32_t audio : 3;
+		uint32_t reserved_1 : 21;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Read the cached FW_CONFIG.  Guaranteed to have valid values.
+ *
+ * @return the FW_CONFIG for the board.
+ */
+union banshee_cbi_fw_config get_fw_config(void);
+
+#endif /* __BOARD_BRYA_FW_CONFIG_H_ */
diff --git a/board/banshee/gpio.inc b/board/banshee/gpio.inc
new file mode 100644
index 0000000000..e33fa5ec06
--- /dev/null
+++ b/board/banshee/gpio.inc
@@ -0,0 +1,177 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define MODULE_KB		MODULE_KEYBOARD_SCAN
+/*
+ * This file was auto-generated.
+ */
+
+/* INTERRUPT GPIOs: */
+GPIO_INT(ACOK_OD,                        PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
+/*TODO(b/208721153): check CM32183 interrupt method */
+GPIO_INT(EC_PROCHOT_IN_L,                PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
+GPIO_INT(EC_WP_ODL,                      PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(GSC_EC_PWR_BTN_ODL,             PIN(0, 1), GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW, power_button_interrupt)
+GPIO_INT(LID_OPEN,                       PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
+GPIO_INT(SEQ_EC_ALL_SYS_PG,              PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_DSW_PWROK,               PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_RSMRST_ODL,              PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,                       PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,                      PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SYS_SLP_S0IX_L,                 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(EC_BATT_PRES_ODL,               PIN(A, 3), GPIO_INT_BOTH, battery_present_interrupt)
+
+GPIO_INT(USB_C0_BC12_INT_ODL,            PIN(C, 6), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C1_BC12_INT_ODL,            PIN(5, 0), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C2_BC12_INT_ODL,            PIN(9, 6), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C3_BC12_INT_ODL,            PIN(9, 5), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C0_PPC_INT_ODL,             PIN(6, 2), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C1_PPC_INT_ODL,             PIN(F, 5), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C2_PPC_INT_ODL,             PIN(7, 0), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C3_PPC_INT_ODL,             PIN(5, 6), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C0_C1_TCPC_INT_ODL,         PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C2_C3_TCPC_INT_ODL,         PIN(A, 2), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C0_RT_INT_ODL,              PIN(B, 1), GPIO_INT_FALLING, retimer_interrupt)
+GPIO_INT(USB_C1_RT_INT_ODL,              PIN(A, 0), GPIO_INT_FALLING, retimer_interrupt)
+GPIO_INT(USB_C2_RT_INT_ODL,              PIN(4, 1), GPIO_INT_FALLING, retimer_interrupt)
+GPIO_INT(USB_C3_RT_INT_ODL,              PIN(8, 1), GPIO_INT_FALLING, retimer_interrupt)
+
+/* USED GPIOs: */
+GPIO(CCD_MODE_ODL,                   PIN(E, 5), GPIO_INPUT)
+GPIO(CHARGER_VAP_OTG_EN,             PIN(7, 3), GPIO_OUT_LOW)
+GPIO(CPU_C10_GATE_L,                 PIN(6, 7), GPIO_INPUT)
+GPIO(EC_ENTERING_RW,                 PIN(0, 3), GPIO_OUT_LOW)
+GPIO(EC_EN_EDP_BL,                   PIN(D, 3), GPIO_OUT_HIGH)
+GPIO(EC_GSC_PACKET_MODE,             PIN(7, 5), GPIO_OUT_LOW)
+GPIO(EC_I2C_BAT_SCL,                 PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_BAT_SDA,                 PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SCL_R,              PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SDA_R,              PIN(B, 2), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,              PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SENSOR_SDA,              PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_USB_PPC_BC_SCL,          PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_PPC_BC_SDA,          PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C1_RT_SCL,        PIN(D, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C1_RT_SDA,        PIN(D, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C1_TCPC_SCL,      PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C1_TCPC_SDA,      PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_USB_C2_C3_RT_SCL,        PIN(E, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C2_C3_RT_SDA,        PIN(E, 3), GPIO_INPUT)
+GPIO(EC_I2C_USB_C2_C3_TCPC_SCL,      PIN(F, 3), GPIO_INPUT)
+GPIO(EC_I2C_USB_C2_C3_TCPC_SDA,      PIN(F, 2), GPIO_INPUT)
+GPIO(EC_PCH_WAKE_D_ODL,              PIN(8, 6), GPIO_ODR_LOW)
+GPIO(EC_PCHHOT_ODL,                  PIN(7, 4), GPIO_INPUT)
+GPIO(EC_PCH_INT_ODL,                 PIN(B, 0), GPIO_ODR_HIGH)
+GPIO(EC_PCH_PWR_BTN_ODL,             PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(EC_PCH_RSMRST_L,                PIN(A, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_RTCRST,                  PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_SYS_PWROK,               PIN(3, 7), GPIO_OUT_LOW)
+GPIO(EC_PROCHOT_ODL,                 PIN(6, 3), GPIO_ODR_HIGH)
+GPIO(EN_PP5000_FAN,                  PIN(6, 1), GPIO_OUT_HIGH)
+GPIO(USBC1_VBUS_ON,                  PIN(D, 7), GPIO_OUT_HIGH)
+GPIO(IMVP9_VRRDY_OD,                 PIN(4, 3), GPIO_INPUT)
+GPIO(PCH_PWROK,                      PIN(7, 2), GPIO_OUT_LOW)
+GPIO(SYS_RST_ODL,                    PIN(C, 5), GPIO_ODR_HIGH)
+GPIO(USB_C0_C1_TCPC_RST_ODL,         PIN(A, 7), GPIO_ODR_LOW)
+GPIO(USB_C2_C3_TCPC_RST_ODL,         PIN(9, 3), GPIO_ODR_LOW)
+GPIO(USBC3_VBUS_ON,                  PIN(9, 4), GPIO_OUT_HIGH)
+GPIO(RIGHT_SIDE,                     PIN(C, 0), GPIO_OUT_LOW)
+GPIO(LEFT_SIDE,                      PIN(B, 6), GPIO_OUT_LOW)
+GPIO(USBC0_VBUS_ON,                  PIN(0, 2), GPIO_OUT_HIGH)
+GPIO(VCCST_PWRGD_OD,                 PIN(A, 4), GPIO_ODR_LOW)
+GPIO(EN_S5_RAILS,                    PIN(E, 1), GPIO_OUT_LOW)
+GPIO(USBC2_VBUS_ON,                  PIN(9, 7), GPIO_OUT_HIGH)
+GPIO(EC_ALS_RGB_INT_R_L,             PIN(D, 4), GPIO_INPUT)
+
+/* UART alternate functions */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)              /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */
+
+/* I2C alternate functions */
+ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)               /* GPIO33/I2C5_SCL0/CTS_L, GPIO36/RTS_L/I2C5_SDA0 */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)               /* GPIO87/I2C1_SDA0 */
+ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)               /* GPIO92/I2C2_SCL0, GPIO91/I2C2_SDA0, GPIO90/I2C1_SCL0 */
+ALTERNATE(PIN_MASK(B, 0x0c), 0, MODULE_I2C, 0)               /* GPIOB3/I2C7_SCL0/DCD_L, GPIOB2/I2C7_SDA0/DSR_L */
+ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, GPIO_SEL_1P8V)   /* GPIOB5/I2C0_SCL0, GPIOB4/I2C0_SDA0 */
+ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)               /* GPIOD1/I2C3_SCL0, GPIOD0/I2C3_SDA0 */
+ALTERNATE(PIN_MASK(E, 0x18), 0, MODULE_I2C, 0)               /* GPIOE4/I2C6_SCL1/I3C_SCL, GPIOE3/I2C6_SDA1/I3C_SDA */
+ALTERNATE(PIN_MASK(F, 0x0c), 0, MODULE_I2C, 0)               /* GPIOF3/I2C4_SCL1, GPIOF2/I2C4_SDA1 */
+
+/* PWM alternate functions */
+ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0)               /* GPIO40/TA1 */
+ALTERNATE(PIN_MASK(6, 0x01), 0, MODULE_PWM, 0)               /* GPIO60/PWM7 */
+ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)               /* GPIO80/PWM3 */
+ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)               /* GPIOB7/PWM5 */
+ALTERNATE(PIN_MASK(C, 0x1c), 0, MODULE_PWM, 0)               /* GPIOC4/PWM2, GPIOC3/PWM0, GPIOC2/PWM1/I2C6_SCL0 */
+
+/* ADC alternate functions */
+ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0)               /* GPIO34/PS2_DAT2/ADC6 */
+ALTERNATE(PIN_MASK(4, 0x34), 0, MODULE_ADC, 0)               /* GPIO42/ADC3/RI_L, GPIO45/ADC0, GPIO44/ADC1 */
+
+/* KB alternate functions */
+ALTERNATE(PIN_MASK(0, 0xf0), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO10&P80_CLK/GPIO07, KSO11&P80_DAT/GPIO06, KSO12/GPIO05, KSO13/GPIO04 */
+ALTERNATE(PIN_MASK(1, 0x4F), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO06/GPO13/GP_SEL_L, KSO07/GPO12/JEN_L, KSO03/GPIO16/JTAG_TDO0_SWO, KSO04/GPIO15/XNOR, KSO05/GPIO14, KSO08/GPIO11/CR_SOUT1, KSO09/GPIO10/CR_SIN1 */
+ALTERNATE(PIN_MASK(2, 0xfc), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI2/GPIO27/TRACEDATA1, KSI3/GPIO26/TRACEDATA0, KSI4/GPIO25/TRACECLK/GP_SCLK, KSI5/GPIO24/GP_MISO, KSI6/GPIO23/S_SBUB, KSI7/GPIO22/S_SBUA */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO00/GPIO21/JTAG_TCK_SWCLK, KSO01/GPIO20/JTAG_TMS_SWIO */
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI0/GPIO31/TRACEDATA3/GP_MOSI, KSI1/GPIO30/TRACEDATA2/GP_CS_L */
+ALTERNATE(PIN_MASK(8, 0x0c), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO14/GPIO82, KSO15/GPIO83 */
+
+/* PMU alternate functions */
+ALTERNATE(PIN_MASK(0, 0x01), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN2_L&GPI00/GPIO00 */
+ALTERNATE(PIN_MASK(0, 0x02), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW) /* GPIO01/PSL_IN3_L&GPI01 */
+ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN1_L&GPID2/GPIOD2 */
+
+/* Unused Pins */
+UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
+UNUSED(PIN(3, 2))       /* GPO32/TRIS_L */
+UNUSED(PIN(3, 5))       /* GPO35/CR_SOUT4/TEST_L */
+UNUSED(PIN(6, 6))       /* GPIO66 */
+UNUSED(PIN(5, 7))       /* GPIO57/SER_IRQ/ESPI_ALERT_L */
+
+/* Pre-configured PSL balls:  J8  K6 */
+
+/*
+ * Generated-gpio.inc is produced using a Brya specific tool that
+ * parses the GPIO definitions derived from the board schematics and
+ * EC pinout descriptions derived form the chip datasheets to generate
+ * the Chrome EC GPIO pinout definitions. Due to the confidential
+ * nature of schematics and datasheets, they are not provided here.
+ *
+ * Variants that do not auto-generate their GPIO definitions should
+ * combine the Brya gpio.inc and generated-gpio.inc into their
+ * gpio.inc and customize as appropriate.
+ */
+
+/*
+ * The NPCX keyboard driver does not use named GPIOs to access
+ * keyboard scan pins, so we do not list them in *gpio.inc. However, when
+ * KEYBOARD_COL2_INVERTED is defined, this name is required.
+ *
+ * GPIO14 needs to be inverted on BOARD ID 2 and later
+ * GPIO15 needs to be inverted on BOARD ID 1
+ * GPIO17 needs to be inverted on BOARD ID 0
+ */
+GPIO(EC_KSO_05_INV,          PIN(1, 4), GPIO_OUT_LOW)
+GPIO(EC_KSO_04_INV,          PIN(1, 5), GPIO_OUT_LOW)
+GPIO(EC_KSO_02_INV,          PIN(1, 7), GPIO_OUT_LOW)
+
+/* IO expander configuration */
+
+IOEX(USB_C0_RT_RST_ODL,      EXPIN(IOEX_C0_NCT38XX, 0, 7), GPIO_ODR_LOW)
+IOEX(USB_C0_OC_ODL,          EXPIN(IOEX_C0_NCT38XX, 0, 4), GPIO_ODR_HIGH)
+IOEX(USB_C0_FRS_EN,          EXPIN(IOEX_C0_NCT38XX, 0, 6), GPIO_OUT_LOW)
+
+IOEX(USB_C1_RT_RST_ODL,      EXPIN(IOEX_C1_NCT38XX, 0, 2), GPIO_ODR_LOW)
+IOEX(USB_C1_OC_ODL,          EXPIN(IOEX_C1_NCT38XX, 0, 3), GPIO_ODR_HIGH)
+IOEX(USB_C1_FRS_EN,          EXPIN(IOEX_C1_NCT38XX, 0, 6), GPIO_OUT_LOW)
+
+IOEX(USB_C2_RT_RST_ODL,      EXPIN(IOEX_C2_NCT38XX, 0, 7), GPIO_ODR_LOW)
+IOEX(USB_C2_OC_ODL,          EXPIN(IOEX_C2_NCT38XX, 0, 4), GPIO_ODR_HIGH)
+IOEX(USB_C2_FRS_EN,          EXPIN(IOEX_C2_NCT38XX, 0, 6), GPIO_OUT_LOW)
+
+IOEX(USB_C3_RT_RST_ODL,      EXPIN(IOEX_C3_NCT38XX, 0, 7), GPIO_ODR_LOW)
+IOEX(USB_C3_OC_ODL,          EXPIN(IOEX_C3_NCT38XX, 0, 4), GPIO_ODR_HIGH)
+IOEX(USB_C3_FRS_EN,          EXPIN(IOEX_C3_NCT38XX, 0, 6), GPIO_OUT_LOW)
diff --git a/board/banshee/i2c.c b/board/banshee/i2c.c
new file mode 100644
index 0000000000..ea3fd38e62
--- /dev/null
+++ b/board/banshee/i2c.c
@@ -0,0 +1,94 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "i2c_bitbang.h"
+
+#define BOARD_ID_FAST_PLUS_CAPABLE 2
+
+/* I2C port map configuration */
+const struct i2c_port_t i2c_ports[] = {
+	{
+		/* I2C0 */
+		.name = "sensor",
+		.port = I2C_PORT_SENSOR,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_SENSOR_SCL,
+		.sda = GPIO_EC_I2C_SENSOR_SDA,
+	},
+	{
+		/* I2C1 */
+		.name = "tcpc0,1",
+		.port = I2C_PORT_USB_C0_C1_TCPC,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_USB_C0_C1_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C1_TCPC_SDA,
+	},
+	{
+		/* I2C2 */
+		.name = "ppc, bc12",
+		.port = I2C_PORT_USB_PPC_BC12,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_USB_PPC_BC_SCL,
+		.sda = GPIO_EC_I2C_USB_PPC_BC_SDA,
+	},
+	{
+		/* I2C3 */
+		.name = "retimer0,1",
+		.port = I2C_PORT_USB_C0_C1_MUX,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_USB_C0_C1_RT_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C1_RT_SDA,
+	},
+	{
+		/* I2C4 */
+		.name = "tcpc2,3",
+		.port = I2C_PORT_USB_C2_C3_TCPC,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_USB_C2_C3_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C2_C3_TCPC_SDA,
+	},
+	{
+		/* I2C5 */
+		.name = "battery",
+		.port = I2C_PORT_BATTERY,
+		.kbps = 100,
+		.scl = GPIO_EC_I2C_BAT_SCL,
+		.sda = GPIO_EC_I2C_BAT_SDA,
+	},
+	{
+		/* I2C6 */
+		.name = "retimer2,3",
+		.port = I2C_PORT_USB_C2_C3_MUX,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_USB_C2_C3_RT_SCL,
+		.sda = GPIO_EC_I2C_USB_C2_C3_RT_SDA,
+	},
+	{
+		/* I2C7 */
+		.name = "eeprom",
+		.port = I2C_PORT_EEPROM,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_MISC_SCL_R,
+		.sda = GPIO_EC_I2C_MISC_SDA_R,
+	},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+const struct i2c_port_t i2c_bitbang_ports[] = {
+	[I2C_BITBANG_CHAN_BRD_ID] = {
+		.name = "bitbang_brd_id",
+		.port = I2C_PORT_EEPROM,
+		.kbps = 100,
+		.scl = GPIO_EC_I2C_MISC_SCL_R,
+		.sda = GPIO_EC_I2C_MISC_SDA_R,
+		.drv = &bitbang_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(i2c_bitbang_ports) == I2C_BITBANG_CHAN_COUNT);
+const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
diff --git a/board/banshee/keyboard.c b/board/banshee/keyboard.c
new file mode 100644
index 0000000000..928f02e025
--- /dev/null
+++ b/board/banshee/keyboard.c
@@ -0,0 +1,100 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "ec_commands.h"
+#include "keyboard_scan.h"
+#include "timer.h"
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/* Increase from 50 us, because KSO_02 passes through the H1. */
+	.output_settle_us = 80,
+	/* Other values should be the same as the default configuration. */
+	.debounce_down_us = 9 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0xff, 0xff, 0xff, 0x03, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0x03, 0xff, 0xff, 0x03, 0xff,
+		0xff, 0xef  /* full set */
+	},
+};
+
+static const struct ec_response_keybd_config banshee_kb_id1 = {
+	.num_top_row_keys = 12,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_FORWARD,		/* T2 */
+		TK_REFRESH,		/* T3 */
+		TK_FULLSCREEN,		/* T4 */
+		TK_OVERVIEW,		/* T5 */
+		TK_SNAPSHOT,		/* T6 */
+		TK_BRIGHTNESS_DOWN,	/* T7 */
+		TK_BRIGHTNESS_UP,	/* T8 */
+		TK_PLAY_PAUSE,		/* T9 */
+		TK_VOL_MUTE,		/* T10 */
+		TK_VOL_DOWN,		/* T11 */
+		TK_VOL_UP,		/* T12 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+static const struct ec_response_keybd_config banshee_kb_id2 = {
+	.num_top_row_keys = 12,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_KBD_BKLIGHT_TOGGLE,	/* T8 */
+		TK_PLAY_PAUSE,		/* T9 */
+		TK_VOL_MUTE,		/* T10 */
+		TK_VOL_DOWN,		/* T11 */
+		TK_VOL_UP,		/* T12 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	if (get_board_id() <= 1)
+		return &banshee_kb_id1;
+	else
+		return &banshee_kb_id2;
+}
+
+/*
+ * Row Column info for Top row keys T1 - T15.
+ * on banshee keyboard Row Column is customization
+ * need define row col to mapping matrix layout.
+ */
+__override const struct key {
+	uint8_t row;
+	uint8_t col;
+} vivaldi_keys[] = {
+	{ .row = 3, .col = 5 }, /* T1 */
+	{ .row = 2, .col = 5 }, /* T2 */
+	{ .row = 6, .col = 4 }, /* T3 */
+	{ .row = 3, .col = 4 }, /* T4 */
+	{ .row = 4, .col = 10 }, /* T5 */
+	{ .row = 3, .col = 10 }, /* T6 */
+	{ .row = 2, .col = 10 }, /* T7 */
+	{ .row = 1, .col = 15 }, /* T8 */
+	{ .row = 3, .col = 11 }, /* T9 */
+	{ .row = 4, .col = 8 }, /* T10 */
+	{ .row = 6, .col = 8 }, /* T11 */
+	{ .row = 3, .col = 13 }, /* T12 */
+	{ .row = 3, .col = 5 }, /* T13 */
+	{ .row = 0, .col = 9 }, /* T14 */
+	{ .row = 0, .col = 11 }, /* T15 */
+};
+BUILD_ASSERT(ARRAY_SIZE(vivaldi_keys) == MAX_TOP_ROW_KEYS);
diff --git a/board/banshee/keyboard_customization.c b/board/banshee/keyboard_customization.c
new file mode 100644
index 0000000000..d561ee6445
--- /dev/null
+++ b/board/banshee/keyboard_customization.c
@@ -0,0 +1,145 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "gpio.h"
+#include "keyboard_8042_sharedlib.h"
+#include "keyboard_config.h"
+#include "keyboard_customization.h"
+#include "keyboard_protocol.h"
+#include "keyboard_raw.h"
+#include "keyboard_scan.h"
+
+enum gpio_signal signal;
+static int colinv;
+
+static uint16_t scancode_set2[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = {
+	{ 0x0021, 0x007B, 0x0079, 0x0072, 0x007A, 0x0071, 0x0069, 0xe04A },
+	{ 0x002f, 0xe070, 0x007D, 0xe01f, 0x006c, 0xe06c, 0xe07d, 0x0077 },
+	{ 0x0015, 0x0070, 0x00ff, 0x000D, 0x000E, 0x0016, 0x0067, 0x001c },
+	{ 0xe011, 0x0011, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 },
+	{ 0xe05a, 0x0029, 0x0024, 0xe01d, 0xe01f, 0x0026, 0xe020, 0xe07a },
+	{ 0x0022, 0x001a, 0xe030, 0xe038, 0x001b, 0x001e, 0x001d, 0x0076 },
+	{ 0x002A, 0x0032, 0x0034, 0x002c, 0x002e, 0x0025, 0x002d, 0x002b },
+	{ 0x003a, 0x0031, 0x0033, 0x0035, 0x0036, 0x003d, 0x003c, 0x003b },
+	{ 0x0049, 0xe072, 0x005d, 0x0044, 0xe023, 0x0046, 0xe021, 0x004b },
+	{ 0x0059, 0x0012, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 },
+	{ 0x0041, 0x007c, 0xe02c, 0xe02d, 0xe024, 0x003e, 0x0043, 0x0042 },
+	{ 0x0013, 0x0064, 0x0075, 0xe054, 0x0051, 0x0061, 0xe06b, 0xe02f },
+	{ 0xe014, 0x0014, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 },
+	{ 0x004a, 0xe075, 0x004e, 0xe032, 0x0045, 0x004d, 0x0054, 0x004c },
+	{ 0x0052, 0x005a, 0xe03c, 0xe069, 0x0055, 0x0066, 0x005b, 0x0023 },
+	{ 0x006a, 0xe035, 0xe074, 0xe054, 0x0000, 0x006b, 0x0073, 0x0074 },
+};
+
+uint16_t get_scancode_set2(uint8_t row, uint8_t col)
+{
+	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS)
+		return scancode_set2[col][row];
+	return 0;
+}
+
+void set_scancode_set2(uint8_t row, uint8_t col, uint16_t val)
+{
+	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS)
+		scancode_set2[col][row] = val;
+}
+
+struct keyboard_type key_typ = {
+	.col_esc = KEYBOARD_COL_ESC,
+	.row_esc = KEYBOARD_ROW_ESC,
+	.col_down = KEYBOARD_COL_DOWN,
+	.row_down = KEYBOARD_ROW_DOWN,
+	.col_left_shift = KEYBOARD_COL_LEFT_SHIFT,
+	.row_left_shift = KEYBOARD_ROW_LEFT_SHIFT,
+	.col_refresh = KEYBOARD_COL_ID1_REFRESH,
+	.row_refresh = KEYBOARD_ROW_ID1_REFRESH,
+	.col_right_alt = KEYBOARD_COL_RIGHT_ALT,
+	.row_right_alt = KEYBOARD_ROW_RIGHT_ALT,
+	.col_left_alt = KEYBOARD_COL_LEFT_ALT,
+	.row_left_alt = KEYBOARD_ROW_LEFT_ALT,
+	.col_key_r = KEYBOARD_COL_KEY_R,
+	.row_key_r = KEYBOARD_ROW_KEY_R,
+	.col_key_h = KEYBOARD_COL_KEY_H,
+	.row_key_h = KEYBOARD_ROW_KEY_H,
+};
+
+void board_id_keyboard_col_inverted(int board_id)
+{
+	if (board_id == 0) {
+		/* keyboard_col2_inverted on board id 0 */
+		signal = GPIO_EC_KSO_02_INV;
+		colinv = 2;
+	} else if (board_id == 1) {
+		/* keyboard_col4_inverted on board id 1 */
+		signal = GPIO_EC_KSO_04_INV;
+		colinv = 4;
+	} else {
+		/* keyboard_col5_inverted on board id 2 and later */
+		signal = GPIO_EC_KSO_05_INV;
+		colinv = 5;
+	}
+}
+
+void board_keyboard_drive_col(int col)
+{
+	/* Drive all lines to high */
+	if (col == KEYBOARD_COLUMN_NONE)
+		gpio_set_level(signal, 0);
+
+	/* Set KBSOUT to zero to detect key-press */
+	else if (col == KEYBOARD_COLUMN_ALL)
+		gpio_set_level(signal, 1);
+
+	/* Drive one line for detection */
+	else {
+		if (col == colinv)
+			gpio_set_level(signal, 1);
+		else
+			gpio_set_level(signal, 0);
+	}
+}
+
+#ifdef CONFIG_KEYBOARD_DEBUG
+static uint8_t keycap_label[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = {
+	{ 'c', KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO },
+	{ KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO },
+	{ 'q', KLLI_UNKNO, KLLI_UNKNO, KLLI_TAB, '`', '1', KLLI_UNKNO, 'a' },
+	{ KLLI_R_ALT, KLLI_L_ALT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO },
+	{ KLLI_UNKNO, KLLI_SPACE, 'e', KLLI_F4, KLLI_SEARC, '3', KLLI_F3,
+	  KLLI_UNKNO },
+	{ 'x', 'z', KLLI_F2, KLLI_F1, 's', '2', 'w', KLLI_ESC },
+	{ 'v', 'b', 'g', 't', '5', '4', 'r', 'f' },
+	{ 'm', 'n', 'h', 'y', '6', '7', 'u', 'j' },
+	{ '.', KLLI_DOWN, '\\', 'o', KLLI_F10, '9', KLLI_UNKNO, 'l' },
+	{ KLLI_R_SHT, KLLI_L_SHT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO },
+	{ ',', KLLI_UNKNO, KLLI_F7, KLLI_F6, KLLI_F5, '8', 'i', 'k' },
+	{ KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_F9, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_LEFT, KLLI_UNKNO },
+	{ KLLI_R_CTR, KLLI_L_CTR, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO },
+	{ '/', KLLI_UP, '-', KLLI_UNKNO, '0', 'p', '[', ';' },
+	{ '\'', KLLI_ENTER, KLLI_UNKNO, KLLI_UNKNO, '=', KLLI_B_SPC, ']', 'd' },
+	{ KLLI_UNKNO, KLLI_F8, KLLI_RIGHT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO },
+};
+
+uint8_t get_keycap_label(uint8_t row, uint8_t col)
+{
+	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS)
+		return keycap_label[col][row];
+	return KLLI_UNKNO;
+}
+
+void set_keycap_label(uint8_t row, uint8_t col, uint8_t val)
+{
+	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS)
+		keycap_label[col][row] = val;
+}
+#endif
diff --git a/board/banshee/keyboard_customization.h b/board/banshee/keyboard_customization.h
new file mode 100644
index 0000000000..1b4994ded0
--- /dev/null
+++ b/board/banshee/keyboard_customization.h
@@ -0,0 +1,77 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Keyboard configuration */
+
+#ifndef __KEYBOARD_CUSTOMIZATION_H
+#define __KEYBOARD_CUSTOMIZATION_H
+
+/*
+ * KEYBOARD_COLS_MAX has the build time column size. It's used to allocate
+ * exact spaces for arrays. Actual keyboard scanning is done using
+ * keyboard_cols, which holds a runtime column size.
+ */
+#define KEYBOARD_COLS_MAX 16
+#define KEYBOARD_ROWS 8
+
+/*
+ * WARNING: Do not directly modify it. You should call keyboard_raw_set_cols,
+ * instead. It checks whether you're eligible or not.
+ */
+extern uint8_t keyboard_cols;
+
+#define KEYBOARD_ROW_TO_MASK(r) (1 << (r))
+
+/* Columns and masks for keys we particularly care about */
+#define KEYBOARD_COL_DOWN 8
+#define KEYBOARD_ROW_DOWN 1
+#define KEYBOARD_MASK_DOWN KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_DOWN)
+#define KEYBOARD_COL_ESC 5
+#define KEYBOARD_ROW_ESC 7
+#define KEYBOARD_MASK_ESC KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_ESC)
+#define KEYBOARD_COL_KEY_H 7
+#define KEYBOARD_ROW_KEY_H 2
+#define KEYBOARD_MASK_KEY_H KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_H)
+#define KEYBOARD_COL_KEY_R 6
+#define KEYBOARD_ROW_KEY_R 6
+#define KEYBOARD_MASK_KEY_R KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_R)
+#define KEYBOARD_COL_LEFT_ALT 3
+#define KEYBOARD_ROW_LEFT_ALT 1
+#define KEYBOARD_MASK_LEFT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_ALT)
+#define KEYBOARD_COL_ID1_REFRESH 4
+#define KEYBOARD_ROW_ID1_REFRESH 6
+#define KEYBOARD_COL_ID2_REFRESH 5
+#define KEYBOARD_ROW_ID2_REFRESH 2
+#define KEYBOARD_MASK_REFRESH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_ID1_REFRESH)
+#define KEYBOARD_COL_RIGHT_ALT 3
+#define KEYBOARD_ROW_RIGHT_ALT 0
+#define KEYBOARD_MASK_RIGHT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_ALT)
+#define KEYBOARD_DEFAULT_COL_VOL_UP 13
+#define KEYBOARD_DEFAULT_ROW_VOL_UP 3
+#define KEYBOARD_COL_LEFT_CTRL 12
+#define KEYBOARD_ROW_LEFT_CTRL 1
+#define KEYBOARD_MASK_LEFT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_CTRL)
+#define KEYBOARD_COL_RIGHT_CTRL 12
+#define KEYBOARD_ROW_RIGHT_CTRL 0
+#define KEYBOARD_MASK_RIGHT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_CTRL)
+#define KEYBOARD_COL_SEARCH 4
+#define KEYBOARD_ROW_SEARCH 4
+#define KEYBOARD_MASK_SEARCH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_SEARCH)
+#define KEYBOARD_COL_KEY_0 13
+#define KEYBOARD_ROW_KEY_0 4
+#define KEYBOARD_MASK_KEY_0 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_0)
+#define KEYBOARD_COL_KEY_1 2
+#define KEYBOARD_ROW_KEY_1 5
+#define KEYBOARD_MASK_KEY_1 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_1)
+#define KEYBOARD_COL_KEY_2 5
+#define KEYBOARD_ROW_KEY_2 5
+#define KEYBOARD_MASK_KEY_2 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_2)
+#define KEYBOARD_COL_LEFT_SHIFT 9
+#define KEYBOARD_ROW_LEFT_SHIFT 1
+#define KEYBOARD_MASK_LEFT_SHIFT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_SHIFT)
+
+void board_id_keyboard_col_inverted(int board_id);
+
+#endif /* __KEYBOARD_CUSTOMIZATION_H */
diff --git a/board/banshee/led.c b/board/banshee/led.c
new file mode 100644
index 0000000000..7333cfcd4f
--- /dev/null
+++ b/board/banshee/led.c
@@ -0,0 +1,364 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Banshee specific PWM LED settings:
+ * there are 2 LEDs on each side of the board,
+ * each one can be controlled separately. The LED colors are white or amber,
+ * and the default behavior is tied to the charging process: both sides are
+ * amber while charging the battery and white when the battery is charged.
+ */
+
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "led_common.h"
+#include "led_pwm.h"
+#include "lid_switch.h"
+#include "pwm.h"
+#include "util.h"
+
+#include <stdint.h>
+
+#define LED_TICKS_PER_CYCLE 10
+#define LED_ON_TICKS 5
+
+#define BREATH_LIGHT_LENGTH 100
+#define BREATH_HOLD_LENGTH 50
+#define BREATH_OFF_LENGTH 200
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_BATTERY_LED,
+	EC_LED_ID_POWER_LED,
+};
+
+enum breath_status {
+	BREATH_LIGHT_UP = 0,
+	BREATH_LIGHT_DOWN,
+	BREATH_HOLD,
+	BREATH_OFF,
+};
+
+enum led_port { RIGHT_PORT = 1, LEFT_PORT };
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = {
+	/* Red, Green, Blue */
+	[EC_LED_COLOR_RED] = { 50, 0, 0 },
+	[EC_LED_COLOR_GREEN] = { 0, 50, 0 },
+	[EC_LED_COLOR_BLUE] = { 0, 0, 8 },
+	[EC_LED_COLOR_YELLOW] = { 40, 50, 0 },
+	[EC_LED_COLOR_WHITE] = { 4, 10, 5 },
+	[EC_LED_COLOR_AMBER] = { 45, 5, 0 },
+};
+
+struct pwm_led_color_map pwr_led_color_map[EC_LED_COLOR_COUNT] = {
+	/* White, Green, Red */
+	[EC_LED_COLOR_WHITE] = { BREATH_LIGHT_LENGTH, 0, 0 },
+};
+
+/*
+ * Three logical LEDs with red、 blue、green channels
+ * and one logical LED with white channels.
+ */
+struct pwm_led pwm_leds[CONFIG_LED_PWM_COUNT] = {
+	[PWM_LED0] = {
+		.ch0 = PWM_CH_SIDE_LED_R,
+		.ch1 = PWM_CH_SIDE_LED_G,
+		.ch2 = PWM_CH_SIDE_LED_B,
+		.enable = &pwm_enable,
+		.set_duty = &pwm_set_duty,
+	},
+	[PWM_LED1] = {
+		.ch0 = PWM_CH_POWER_LED_W,
+		.ch1 = PWM_LED_NO_CHANNEL,
+		.ch2 = PWM_LED_NO_CHANNEL,
+		.enable = &pwm_enable,
+		.set_duty = &pwm_set_duty,
+	},
+};
+
+uint8_t breath_led_light_up;
+uint8_t breath_led_light_down;
+uint8_t breath_led_hold;
+uint8_t breath_led_off;
+
+int breath_pwm_enable;
+int breath_led_status;
+static void breath_led_pwm_deferred(void);
+DECLARE_DEFERRED(breath_led_pwm_deferred);
+
+/*
+ *	Breath LED API
+ *	Max duty (percentage) = BREATH_LIGHT_LENGTH (100%)
+ *	Fade time (second) = 1000ms(In) / 1000ms(Out)
+ *	Duration time (second) = BREATH_HOLD_LENGTH(500ms)
+ *	Interval time (second) = BREATH_OFF_LENGTH(2000ms)
+ */
+
+static void breath_led_pwm_deferred(void)
+{
+	switch (breath_led_status) {
+	case BREATH_LIGHT_UP:
+
+		if (breath_led_light_up <= BREATH_LIGHT_LENGTH)
+			pwm_set_duty(PWM_CH_POWER_LED_W, breath_led_light_up++);
+		else {
+			breath_led_light_up = 0;
+			breath_led_light_down = BREATH_LIGHT_LENGTH;
+			breath_led_status = BREATH_HOLD;
+		}
+
+		break;
+	case BREATH_HOLD:
+
+		if (breath_led_hold <= BREATH_HOLD_LENGTH)
+			breath_led_hold++;
+		else {
+			breath_led_hold = 0;
+			breath_led_status = BREATH_LIGHT_DOWN;
+		}
+
+		break;
+	case BREATH_LIGHT_DOWN:
+
+		if (breath_led_light_down != 0)
+			pwm_set_duty(PWM_CH_POWER_LED_W,
+				     breath_led_light_down--);
+		else {
+			breath_led_light_down = BREATH_LIGHT_LENGTH;
+			breath_led_status = BREATH_OFF;
+		}
+
+		break;
+	case BREATH_OFF:
+
+		if (breath_led_off <= BREATH_OFF_LENGTH)
+			breath_led_off++;
+		else {
+			breath_led_off = 0;
+			breath_led_status = BREATH_LIGHT_UP;
+		}
+
+		break;
+	}
+
+	if (breath_pwm_enable)
+		hook_call_deferred(&breath_led_pwm_deferred_data, 10 * MSEC);
+}
+
+void breath_led_run(uint8_t enable)
+{
+	if (enable && !breath_pwm_enable) {
+		breath_pwm_enable = true;
+		breath_led_status = BREATH_LIGHT_UP;
+		hook_call_deferred(&breath_led_pwm_deferred_data, 10 * MSEC);
+	} else if (!enable && breath_pwm_enable) {
+		breath_pwm_enable = false;
+		breath_led_light_up = 0;
+		breath_led_light_down = 0;
+		breath_led_hold = 0;
+		breath_led_off = 0;
+		breath_led_status = BREATH_OFF;
+		hook_call_deferred(&breath_led_pwm_deferred_data, -1);
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_RED] = 100;
+		brightness_range[EC_LED_COLOR_GREEN] = 100;
+		brightness_range[EC_LED_COLOR_YELLOW] = 100;
+		brightness_range[EC_LED_COLOR_AMBER] = 100;
+		brightness_range[EC_LED_COLOR_BLUE] = 100;
+		brightness_range[EC_LED_COLOR_WHITE] = 100;
+	} else if (led_id == EC_LED_ID_POWER_LED)
+		brightness_range[EC_LED_COLOR_WHITE] = 100;
+}
+
+void set_pwr_led_color(enum pwm_led_id id, int color)
+{
+	struct pwm_led duty = { 0 };
+	const struct pwm_led *led = &pwm_leds[id];
+
+	if ((id >= CONFIG_LED_PWM_COUNT) || (id < 0) ||
+	    (color >= EC_LED_COLOR_COUNT) || (color < -1))
+		return;
+
+	if (color != -1) {
+		duty.ch0 = pwr_led_color_map[color].ch0;
+		duty.ch1 = pwr_led_color_map[color].ch1;
+		duty.ch2 = pwr_led_color_map[color].ch2;
+	}
+
+	if (led->ch0 != (enum pwm_channel)PWM_LED_NO_CHANNEL)
+		led->set_duty(led->ch0, duty.ch0);
+	if (led->ch1 != (enum pwm_channel)PWM_LED_NO_CHANNEL)
+		led->set_duty(led->ch1, duty.ch1);
+	if (led->ch2 != (enum pwm_channel)PWM_LED_NO_CHANNEL)
+		led->set_duty(led->ch2, duty.ch2);
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	enum pwm_led_id pwm_id;
+
+	/* Convert ec_led_id to pwm_led_id. */
+	if (led_id == EC_LED_ID_BATTERY_LED)
+		pwm_id = PWM_LED0;
+	else if (led_id == EC_LED_ID_POWER_LED)
+		pwm_id = PWM_LED1;
+	else
+		return EC_ERROR_UNKNOWN;
+
+	if (led_id == EC_LED_ID_POWER_LED) {
+		if (brightness[EC_LED_COLOR_WHITE])
+			set_pwr_led_color(pwm_id, EC_LED_COLOR_WHITE);
+		else
+			/* Otherwise, the "color" is "off". */
+			set_pwr_led_color(pwm_id, -1);
+	} else {
+		if (brightness[EC_LED_COLOR_RED])
+			set_pwm_led_color(pwm_id, EC_LED_COLOR_RED);
+		else if (brightness[EC_LED_COLOR_GREEN])
+			set_pwm_led_color(pwm_id, EC_LED_COLOR_GREEN);
+		else if (brightness[EC_LED_COLOR_BLUE])
+			set_pwm_led_color(pwm_id, EC_LED_COLOR_BLUE);
+		else if (brightness[EC_LED_COLOR_YELLOW])
+			set_pwm_led_color(pwm_id, EC_LED_COLOR_YELLOW);
+		else if (brightness[EC_LED_COLOR_WHITE])
+			set_pwm_led_color(pwm_id, EC_LED_COLOR_WHITE);
+		else if (brightness[EC_LED_COLOR_AMBER])
+			set_pwm_led_color(pwm_id, EC_LED_COLOR_AMBER);
+		else
+			/* Otherwise, the "color" is "off". */
+			set_pwm_led_color(pwm_id, -1);
+	}
+
+	return EC_SUCCESS;
+}
+
+static int led_get_charge_percent(void)
+{
+	return DIV_ROUND_NEAREST(charge_get_display_charge(), 10);
+}
+
+static void select_active_port_led(int port)
+{
+	if ((led_pwr_get_state() == LED_PWRS_DISCHARGE &&
+	     led_get_charge_percent() < 10) ||
+	    led_pwr_get_state() == LED_PWRS_ERROR) {
+		gpio_set_level(GPIO_LEFT_SIDE, 1);
+		gpio_set_level(GPIO_RIGHT_SIDE, 1);
+	} else if (port == RIGHT_PORT) {
+		gpio_set_level(GPIO_LEFT_SIDE, 0);
+		gpio_set_level(GPIO_RIGHT_SIDE, 1);
+	} else if (port == LEFT_PORT) {
+		gpio_set_level(GPIO_LEFT_SIDE, 1);
+		gpio_set_level(GPIO_RIGHT_SIDE, 0);
+	} else {
+		gpio_set_level(GPIO_LEFT_SIDE, 0);
+		gpio_set_level(GPIO_RIGHT_SIDE, 0);
+	}
+}
+
+static int led_power_enable(void)
+{
+	if (gpio_get_level(GPIO_LEFT_SIDE) || gpio_get_level(GPIO_RIGHT_SIDE))
+		return true;
+
+	return false;
+}
+
+static void set_active_port_color(int color)
+{
+	int usbc_port = charge_manager_get_active_charge_port();
+	int port = 0;
+
+	if ((usbc_port == USBC_PORT_C0) || (usbc_port == USBC_PORT_C1))
+		port = RIGHT_PORT;
+	else if ((usbc_port == USBC_PORT_C2) || (usbc_port == USBC_PORT_C3))
+		port = LEFT_PORT;
+
+	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
+		select_active_port_led(port);
+		set_pwm_led_color(PWM_LED0, led_power_enable() ? color : -1);
+	}
+}
+
+static void led_set_battery(void)
+{
+	static int battery_ticks;
+
+	battery_ticks++;
+
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
+		/* Always indicate when charging, even in suspend. */
+		set_active_port_color(EC_LED_COLOR_AMBER);
+		break;
+	case LED_PWRS_DISCHARGE:
+		if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
+			if (led_get_charge_percent() < 10)
+				set_active_port_color((battery_ticks & 0x2) ?
+							      EC_LED_COLOR_RED :
+							      -1);
+			else
+				set_active_port_color(-1);
+		}
+		break;
+	case LED_PWRS_ERROR:
+		set_active_port_color((battery_ticks & 0x2) ? EC_LED_COLOR_RED :
+							      -1);
+		break;
+	case LED_PWRS_CHARGE_NEAR_FULL:
+		set_active_port_color(EC_LED_COLOR_WHITE);
+		break;
+	case LED_PWRS_IDLE:
+		set_active_port_color(EC_LED_COLOR_AMBER);
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		set_active_port_color(
+			(battery_ticks & 0x4) ? EC_LED_COLOR_AMBER : -1);
+		break;
+	default:
+		break;
+	}
+}
+
+static void led_set_power(void)
+{
+	/* turn off led when lid is close*/
+	if (!lid_is_open()) {
+		set_pwr_led_color(PWM_LED1, -1);
+		return;
+	}
+
+	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
+		breath_led_run(1);
+		return;
+	} else
+		breath_led_run(0);
+
+	if (chipset_in_state(CHIPSET_STATE_ON)) {
+		set_pwr_led_color(PWM_LED1, EC_LED_COLOR_WHITE);
+	} else
+		set_pwr_led_color(PWM_LED1, -1);
+}
+
+/* Called by hook task every TICK */
+static void led_tick(void)
+{
+	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
+		led_set_battery();
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		led_set_power();
+}
+DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
diff --git a/board/banshee/pwm.c b/board/banshee/pwm.c
new file mode 100644
index 0000000000..41e762d6f8
--- /dev/null
+++ b/board/banshee/pwm.c
@@ -0,0 +1,70 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "hooks.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_SIDE_LED_R] = {
+		.channel = 0,
+		.flags = PWM_CONFIG_DSLEEP,
+		.freq = 2000,
+	},
+	[PWM_CH_SIDE_LED_G] = {
+		.channel = 1,
+		.flags = PWM_CONFIG_DSLEEP,
+		.freq = 2000,
+	},
+	[PWM_CH_SIDE_LED_B] = {
+		.channel = 2,
+		.flags = PWM_CONFIG_DSLEEP,
+		.freq = 2000,
+	},
+	[PWM_CH_KBLIGHT] = {
+		.channel = 3,
+		.flags = 0,
+		/*
+		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
+		 * flicker. Higher frequencies consume similar average power to
+		 * lower PWM frequencies, but higher frequencies record a much
+		 * lower maximum power.
+		 */
+		.freq = 2400,
+	},
+	[PWM_CH_FAN] = {
+		.channel = 5,
+		.flags = PWM_CONFIG_OPEN_DRAIN,
+		.freq = 25000
+	},
+	[PWM_CH_POWER_LED_W] = {
+		.channel = 7,
+		.flags = PWM_CONFIG_DSLEEP,
+		.freq = 2000,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+static void board_pwm_init(void)
+{
+	/*
+	 * Turn off all the LEDs.
+	 * Turn on the fan at 100%.
+	 */
+	pwm_enable(PWM_CH_SIDE_LED_R, 1);
+	pwm_set_duty(PWM_CH_SIDE_LED_R, 0);
+	pwm_enable(PWM_CH_SIDE_LED_G, 1);
+	pwm_set_duty(PWM_CH_SIDE_LED_G, 0);
+	pwm_enable(PWM_CH_SIDE_LED_B, 1);
+	pwm_set_duty(PWM_CH_SIDE_LED_B, 0);
+
+	pwm_set_duty(PWM_CH_POWER_LED_W, 0);
+	pwm_enable(PWM_CH_POWER_LED_W, 1);
+
+	pwm_set_duty(PWM_CH_KBLIGHT, 50);
+}
+DECLARE_HOOK(HOOK_INIT, board_pwm_init, HOOK_PRIO_DEFAULT);
diff --git a/board/banshee/sensors.c b/board/banshee/sensors.c
new file mode 100644
index 0000000000..a6bd3d3863
--- /dev/null
+++ b/board/banshee/sensors.c
@@ -0,0 +1,244 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "accelgyro.h"
+#include "adc.h"
+#include "common.h"
+#include "driver/als_cm32183.h"
+#include "hooks.h"
+#include "motion_sense.h"
+#include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
+#include "thermal.h"
+
+/* ADC configuration */
+struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_1_DDR_SOC] = {
+		.name = "TEMP_DDR_SOC",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_2_AMBIENT] = {
+		.name = "TEMP_AMBIENT",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_3_CHARGER] = {
+		.name = "TEMP_CHARGER",
+		.input_ch = NPCX_ADC_CH6,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* CM32183 private data */
+static struct als_drv_data_t g_cm32183_data = {
+	/**
+	 * adjusted_value = raw_value * scale + raw_value * uscale / 10000
+	 * the coeficient we need is 3.2
+	 */
+	.als_cal.scale = 3,
+	.als_cal.uscale = 2000,
+	.als_cal.offset = 0,
+	.als_cal.channel_scale = {
+		/* TODO(b/219424210):  Calibrate ALS CM32183A3OP */
+	},
+};
+
+struct motion_sensor_t motion_sensors[] = {
+	[CLEAR_ALS] = {
+		.name = "Clear Light",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_CM32183,
+		.type = MOTIONSENSE_TYPE_LIGHT,
+		.location = MOTIONSENSE_LOC_CAMERA,
+		.drv = &cm32183_drv,
+		.drv_data = &g_cm32183_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = CM32183_I2C_ADDR,
+		.rot_standard_ref = NULL,
+		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
+		.config = {
+			/* Run ALS sensor in S0 */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 1000,
+			},
+		},
+	},
+};
+const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+/* ALS instances when LPC mapping is needed. Each entry directs to a sensor. */
+const struct motion_sensor_t *motion_als_sensors[] = {
+	&motion_sensors[CLEAR_ALS],
+};
+BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
+
+/*TODO(b/208721153): check CM32183 interrupt method */
+
+/* Temperature sensor configuration */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1_DDR_SOC] = {
+		.name = "DDR and SOC",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_1_DDR_SOC,
+	},
+	[TEMP_SENSOR_2_AMBIENT] = {
+		.name = "Ambient",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_2_AMBIENT,
+	},
+	[TEMP_SENSOR_3_CHARGER] = {
+		.name = "Charger",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_3_CHARGER,
+	},
+
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/*
+ * TODO(b/180681346): update for Alder Lake/brya
+ *
+ * Alder Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
+ * 130 C.  However, sensor is located next to DDR, so we need to use the lower
+ * DDR temperature limit (85 C)
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = C_TO_K(80), \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(90), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(100), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = C_TO_K(75), \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(81), \
+		}, \
+		.temp_fan_off = C_TO_K(50), \
+		.temp_fan_max = C_TO_K(58), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
+
+/*
+ * TODO(b/180681346): update for Alder Lake/brya
+ *
+ * Inductor limits - used for both charger and PP3300 regulator
+ *
+ * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
+ *
+ * Charger max recommended temperature 100C, max absolute temperature 125C
+ * PP3300 regulator: operating range -40 C to 145 C
+ *
+ * Inductors: limit of 125c
+ * PCB: limit is 80c
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_AMBIENT          \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = C_TO_K(85), \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(95), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(105), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = C_TO_K(70), \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(86), \
+		}, \
+		.temp_fan_off = C_TO_K(50), \
+		.temp_fan_max = C_TO_K(58), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_ambient =
+	THERMAL_AMBIENT;
+
+/*
+ * Inductor limits - used for both charger and PP3300 regulator
+ *
+ * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
+ *
+ * Charger max recommended temperature 125C, max absolute temperature 150C
+ * PP3300 regulator: operating range -40 C to 125 C
+ *
+ * Inductors: limit of 125c
+ * PCB: limit is 80c
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CHARGER          \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = C_TO_K(90), \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(100), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(110), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = C_TO_K(85), \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(91), \
+		}, \
+		.temp_fan_off = C_TO_K(50), \
+		.temp_fan_max = C_TO_K(58), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_charger =
+	THERMAL_CHARGER;
+
+/*
+ * TODO(b/180681346): update for brya WWAN module
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_WWAN             \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(130), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(130), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(100), \
+		}, \
+		.temp_fan_off = C_TO_K(35), \
+		.temp_fan_max = C_TO_K(60), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_wwan =
+	THERMAL_WWAN;
+
+struct ec_thermal_config thermal_params[] = {
+	[TEMP_SENSOR_1_DDR_SOC] = THERMAL_CPU,
+	[TEMP_SENSOR_2_AMBIENT] = THERMAL_AMBIENT,
+	[TEMP_SENSOR_3_CHARGER] = THERMAL_CHARGER,
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
+
+static void board_thermals_init(void)
+{
+	if (get_board_id() == 1) {
+		/*
+		 * Board ID 1 only has 3 sensors and the AMBIENT sensor
+		 * ADC pins have been reassigned, so we're down to 2
+		 * sensors that can easily be configured. So, alias the
+		 * AMBIENT sensor ADC channel to the unimplemented ADC
+		 * slots.
+		 */
+		adc_channels[ADC_TEMP_SENSOR_3_CHARGER].input_ch = NPCX_ADC_CH1;
+	}
+}
+
+DECLARE_HOOK(HOOK_INIT, board_thermals_init, HOOK_PRIO_INIT_CHIPSET);
diff --git a/board/banshee/usbc_config.c b/board/banshee/usbc_config.c
new file mode 100644
index 0000000000..7f6dd15d66
--- /dev/null
+++ b/board/banshee/usbc_config.c
@@ -0,0 +1,522 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi.h"
+#include "charge_ramp.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/bc12/pi3usb9201_public.h"
+#include "driver/ppc/nx20p348x.h"
+#include "driver/ppc/syv682x_public.h"
+#include "driver/retimer/bb_retimer_public.h"
+#include "driver/tcpm/nct38xx.h"
+#include "driver/tcpm/ps8xxx_public.h"
+#include "driver/tcpm/tcpci.h"
+#include "ec_commands.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "ioexpander.h"
+#include "system.h"
+#include "task.h"
+#include "task_id.h"
+#include "timer.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+/* USBC TCPC configuration */
+const struct tcpc_config_t tcpc_config[] = {
+	[USBC_PORT_C0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0_C1_TCPC,
+			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+	},
+	[USBC_PORT_C1] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0_C1_TCPC,
+			.addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+	},
+	[USBC_PORT_C2] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C2_C3_TCPC,
+			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+	},
+	[USBC_PORT_C3] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C2_C3_TCPC,
+			.addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
+BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
+/******************************************************************************/
+/* USBC PPC configuration */
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_PPC_BC12,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.frs_en = IOEX_USB_C0_FRS_EN,
+		.drv = &syv682x_drv,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_PPC_BC12,
+		.i2c_addr_flags = SYV682X_ADDR2_FLAGS,
+		.frs_en = IOEX_USB_C1_FRS_EN,
+		.drv = &syv682x_drv,
+	},
+	[USBC_PORT_C2] = {
+		.i2c_port = I2C_PORT_USB_PPC_BC12,
+		.i2c_addr_flags = SYV682X_ADDR1_FLAGS,
+		.frs_en = IOEX_USB_C2_FRS_EN,
+		.drv = &syv682x_drv,
+	},
+	[USBC_PORT_C3] = {
+		.i2c_port = I2C_PORT_USB_PPC_BC12,
+		.i2c_addr_flags = SYV682X_ADDR3_FLAGS,
+		.frs_en = IOEX_USB_C3_FRS_EN,
+		.drv = &syv682x_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
+
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+int is_framework_dp_hdmi_card(int port)
+{
+	uint16_t USB_VID = pd_get_identity_vid(port);
+	uint16_t USB_PID = pd_get_identity_pid(port);
+
+	if (((USB_PID == USB_PID_FRAMEWORK_HDMI_CARD) ||
+	     (USB_PID == USB_PID_FRAMEWORK_DP_CARD)) &&
+	    (USB_VID == USB_VID_FRAMEWORK))
+		return 1;
+
+	return 0;
+}
+
+void board_prefix(const struct usb_mux *me, mux_state_t hpd_state,
+		  bool *ack_required)
+{
+	int port = me->usb_port;
+
+	bb_retimer_hpd_update(me, hpd_state, ack_required);
+
+	if (!is_framework_dp_hdmi_card(port))
+		return;
+
+	if (hpd_state & USB_PD_MUX_HPD_LVL)
+		bb_retimer_set_dp_connection(me, true);
+	else
+		bb_retimer_set_dp_connection(me, false);
+}
+
+int board_virtual_mux_set(const struct usb_mux *me, mux_state_t mux_state)
+{
+	int rv = 0;
+	int port = me->usb_port;
+
+	if (is_framework_dp_hdmi_card(port))
+		rv = bb_retimer_set_dp_connection(me, false);
+
+	return rv;
+}
+
+/* USBC mux configuration - Alder Lake includes internal mux */
+static const struct usb_mux_chain usbc0_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+static const struct usb_mux_chain usbc1_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+static const struct usb_mux_chain usbc2_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C2,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+static const struct usb_mux_chain usbc3_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C3,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+
+const struct usb_mux_chain usb_muxes[] = {
+	[USBC_PORT_C0] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			/*
+			 * When a USB-A card is connected to the
+			 * chromebook, the USB_3_CONNECTION bit will be
+			 * enabled. This increases BBR power
+			 * consumption, so clear the USB3_CONNECTION bit
+			 * in S0ix and re-enable when returning to S0.
+			 */
+			.flags = USB_MUX_FLAG_CAN_IDLE,
+			.driver = &bb_usb_retimer,
+			.hpd_update = board_prefix,
+			.i2c_port = I2C_PORT_USB_C0_C1_MUX,
+			.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
+			.board_set = &board_virtual_mux_set,
+		},
+		.next = &usbc0_tcss_usb_mux,
+	},
+	[USBC_PORT_C1] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.flags = USB_MUX_FLAG_CAN_IDLE,
+			.driver = &bb_usb_retimer,
+			.hpd_update = board_prefix,
+			.i2c_port = I2C_PORT_USB_C0_C1_MUX,
+			.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
+			.board_set = &board_virtual_mux_set,
+		},
+		.next = &usbc1_tcss_usb_mux,
+	},
+	[USBC_PORT_C2] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C2,
+			.flags = USB_MUX_FLAG_CAN_IDLE,
+			.driver = &bb_usb_retimer,
+			.hpd_update = board_prefix,
+			.i2c_port = I2C_PORT_USB_C2_C3_MUX,
+			.i2c_addr_flags = USBC_PORT_C2_BB_RETIMER_I2C_ADDR,
+			.board_set = &board_virtual_mux_set,
+		},
+		.next = &usbc2_tcss_usb_mux,
+	},
+	[USBC_PORT_C3] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C3,
+			.flags = USB_MUX_FLAG_CAN_IDLE,
+			.driver = &bb_usb_retimer,
+			.hpd_update = board_prefix,
+			.i2c_port = I2C_PORT_USB_C2_C3_MUX,
+			.i2c_addr_flags = USBC_PORT_C3_BB_RETIMER_I2C_ADDR,
+			.board_set = &board_virtual_mux_set,
+		},
+		.next = &usbc3_tcss_usb_mux,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
+
+/* BC1.2 charger detect configuration */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_PPC_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_PPC_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_1_FLAGS,
+	},
+	[USBC_PORT_C2] = {
+		.i2c_port = I2C_PORT_USB_PPC_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_2_FLAGS,
+	},
+	[USBC_PORT_C3] = {
+		.i2c_port = I2C_PORT_USB_PPC_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_0_FLAGS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
+
+/*
+ * USB C0 and C2 uses burnside bridge chips and have their reset
+ * controlled by their respective TCPC chips acting as GPIO expanders.
+ *
+ * ioex_init() is normally called before we take the TCPCs out of
+ * reset, so we need to start in disabled mode, then explicitly
+ * call ioex_init().
+ */
+
+struct ioexpander_config_t ioex_config[] = {
+	[IOEX_C0_NCT38XX] = {
+		.i2c_host_port = I2C_PORT_USB_C0_C1_TCPC,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
+	},
+	[IOEX_C1_NCT38XX] = {
+		.i2c_host_port = I2C_PORT_USB_C0_C1_TCPC,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
+	},
+	[IOEX_C2_NCT38XX] = {
+		.i2c_host_port = I2C_PORT_USB_C2_C3_TCPC,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
+	},
+	[IOEX_C3_NCT38XX] = {
+		.i2c_host_port = I2C_PORT_USB_C2_C3_TCPC,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT);
+
+#ifdef CONFIG_CHARGE_RAMP_SW
+
+/*
+ * TODO(b/181508008): tune this threshold
+ */
+
+#define BC12_MIN_VOLTAGE 4400
+
+/**
+ * Return true if VBUS is too low
+ */
+int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
+{
+	int voltage;
+
+	if (charger_get_vbus_voltage(port, &voltage))
+		voltage = 0;
+
+	if (voltage == 0) {
+		CPRINTS("%s: must be disconnected", __func__);
+		return 1;
+	}
+
+	if (voltage < BC12_MIN_VOLTAGE) {
+		CPRINTS("%s: port %d: vbus %d lower than %d", __func__, port,
+			voltage, BC12_MIN_VOLTAGE);
+		return 1;
+	}
+
+	return 0;
+}
+
+#endif /* CONFIG_CHARGE_RAMP_SW */
+
+__override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
+{
+	enum ioex_signal rst_signal;
+
+	if (me->usb_port == USBC_PORT_C0)
+		rst_signal = IOEX_USB_C0_RT_RST_ODL;
+	else if (me->usb_port == USBC_PORT_C1)
+		rst_signal = IOEX_USB_C1_RT_RST_ODL;
+	else if (me->usb_port == USBC_PORT_C2)
+		rst_signal = IOEX_USB_C2_RT_RST_ODL;
+	else if (me->usb_port == USBC_PORT_C3)
+		rst_signal = IOEX_USB_C3_RT_RST_ODL;
+	else
+		return EC_ERROR_INVAL;
+	/*
+	 * We do not have a load switch for the burnside bridge chips,
+	 * so we only need to sequence reset.
+	 */
+
+	if (enable) {
+		/*
+		 * Tpw, minimum time from VCC to RESET_N de-assertion is 100us.
+		 * For boards that don't provide a load switch control, the
+		 * retimer_init() function ensures power is up before calling
+		 * this function.
+		 */
+		ioex_set_level(rst_signal, 1);
+		/*
+		 * Allow 1ms time for the retimer to power up lc_domain
+		 * which powers I2C controller within retimer
+		 */
+		msleep(1);
+	} else {
+		ioex_set_level(rst_signal, 0);
+		msleep(1);
+	}
+	return EC_SUCCESS;
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * TODO(b/179648104): figure out correct timing
+	 */
+	gpio_set_level(GPIO_USB_C0_C1_TCPC_RST_ODL, 0);
+	gpio_set_level(GPIO_USB_C2_C3_TCPC_RST_ODL, 0);
+	/*
+	 * delay for power-on to reset-off and min. assertion time
+	 */
+	msleep(NCT38XX_RESET_HOLD_DELAY_MS);
+	gpio_set_level(GPIO_USB_C0_C1_TCPC_RST_ODL, 1);
+	gpio_set_level(GPIO_USB_C2_C3_TCPC_RST_ODL, 1);
+
+	nct38xx_reset_notify(USBC_PORT_C0);
+	nct38xx_reset_notify(USBC_PORT_C1);
+	nct38xx_reset_notify(USBC_PORT_C2);
+	nct38xx_reset_notify(USBC_PORT_C3);
+
+	/* wait for chips to come up */
+	if (NCT3808_RESET_POST_DELAY_MS != 0)
+		msleep(NCT3808_RESET_POST_DELAY_MS);
+}
+
+static void board_tcpc_init(void)
+{
+	/* Don't reset TCPCs after initial reset */
+	if (!system_jumped_late())
+		board_reset_pd_mcu();
+
+	/*
+	 * These IO expander pins are implemented using the
+	 * C0,C1,C2,C3 TCPC, so they must be set up after the TCPC has
+	 * been taken out of reset.
+	 */
+	ioex_init(IOEX_C0_NCT38XX);
+	ioex_init(IOEX_C1_NCT38XX);
+	ioex_init(IOEX_C2_NCT38XX);
+	ioex_init(IOEX_C3_NCT38XX);
+
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C2_PPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C3_PPC_INT_ODL);
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_C1_TCPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C2_C3_TCPC_INT_ODL);
+
+	/* Enable BC1.2 interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C2_BC12_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C3_BC12_INT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (gpio_get_level(GPIO_USB_C0_C1_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_0 | PD_STATUS_TCPC_ALERT_1;
+
+	if (gpio_get_level(GPIO_USB_C2_C3_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_2 | PD_STATUS_TCPC_ALERT_3;
+
+	return status;
+}
+
+int ppc_get_alert_status(int port)
+{
+	if (port == USBC_PORT_C0)
+		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
+	else if (port == USBC_PORT_C1)
+		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
+	else if (port == USBC_PORT_C2)
+		return gpio_get_level(GPIO_USB_C2_PPC_INT_ODL) == 0;
+	else if (port == USBC_PORT_C3)
+		return gpio_get_level(GPIO_USB_C3_PPC_INT_ODL) == 0;
+	return 0;
+}
+
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_C1_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C2_C3_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C2);
+		break;
+	default:
+		break;
+	}
+}
+
+void bc12_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_BC12_INT_ODL:
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+		break;
+	case GPIO_USB_C1_BC12_INT_ODL:
+		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+		break;
+	case GPIO_USB_C2_BC12_INT_ODL:
+		usb_charger_task_set_event(2, USB_CHG_EVENT_BC12);
+		break;
+	case GPIO_USB_C3_BC12_INT_ODL:
+		usb_charger_task_set_event(3, USB_CHG_EVENT_BC12);
+		break;
+	default:
+		break;
+	}
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C1);
+		break;
+	case GPIO_USB_C2_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C2);
+		break;
+	case GPIO_USB_C3_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C3);
+		break;
+	default:
+		break;
+	}
+}
+
+void retimer_interrupt(enum gpio_signal signal)
+{
+	/*
+	 * TODO(b/179513527): add USB-C support
+	 */
+}
diff --git a/board/banshee/usbc_config.h b/board/banshee/usbc_config.h
new file mode 100644
index 0000000000..5085b28bec
--- /dev/null
+++ b/board/banshee/usbc_config.h
@@ -0,0 +1,21 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Banshee board-specific USB-C configuration */
+
+#ifndef __CROS_EC_USBC_CONFIG_H
+#define __CROS_EC_USBC_CONFIG_H
+
+#define CONFIG_USB_PD_PORT_MAX_COUNT 4
+
+enum usbc_port {
+	USBC_PORT_C0 = 0,
+	USBC_PORT_C1,
+	USBC_PORT_C2,
+	USBC_PORT_C3,
+	USBC_PORT_COUNT
+};
+
+#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/banshee/vif_override.xml b/board/banshee/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/banshee/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/bds/board.c b/board/bds/board.c
deleted file mode 100644
index 95f3ef6cfd..0000000000
--- a/board/bds/board.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Stellaris EKB-LM4F-EAC board-specific configuration */
-
-#include "adc.h"
-#include "adc_chip.h"
-#include "gpio.h"
-#include "i2c.h"
-#include "registers.h"
-#include "util.h"
-
-/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
-const struct adc_t adc_channels[] = {
-	/* EC internal temperature is calculated by
-	 * 273 + (295 - 450 * ADC_VALUE / ADC_READ_MAX) / 2
-	 * = -225 * ADC_VALUE / ADC_READ_MAX + 420.5
-	 */
-	{"ECTemp", LM4_ADC_SEQ0, -225, ADC_READ_MAX, 420,
-	 LM4_AIN_NONE, 0x0e /* TS0 | IE0 | END0 */, 0, 0},
-
-	/* Charger current is mapped from 0~4000mA to 0~1.6V.
-	 * And ADC maps 0~3.3V to ADC_READ_MAX.
-	 *
-	 * Note that on BDS, this is really just the turn pot on the Badger
-	 * board, but that's good enough for debugging the ADC.
-	 */
-	{"BDSPot", LM4_ADC_SEQ1, 33 * 4000, ADC_READ_MAX * 16, 0,
-	 LM4_AIN(0), 0x06 /* IE0 | END0 */, LM4_GPIO_E, (1<<3)},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"lightbar", 5, 400},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-#include "gpio_list.h"
diff --git a/board/bds/board.h b/board/bds/board.h
deleted file mode 100644
index f43ea6ee92..0000000000
--- a/board/bds/board.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Stellaris EKB-LM4F-EAC board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Optional features */
-#define CONFIG_SYSTEM_UNLOCKED  /* Allow dangerous commands */
-#define CONFIG_I2C
-#define CONFIG_I2C_MASTER
-
-/* LM4 modules we don't use on link but still want to keep compiling */
-#define CONFIG_EEPROM
-#define CONFIG_PSTORE
-
-/* Modules we want to exclude */
-#undef CONFIG_LID_SWITCH
-#undef CONFIG_HOSTCMD_LPC
-#undef CONFIG_PECI
-#undef CONFIG_SWITCH
-
-/* Write protect is active high */
-#define CONFIG_WP_ACTIVE_HIGH
-
-#ifndef __ASSEMBLER__
-
-enum adc_channel {
-	ADC_CH_EC_TEMP = 0,  /* EC internal die temperature in degrees K. */
-	ADC_CH_BDS_POT,      /* BDS pot input. */
-	ADC_CH_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_COUNT
-};
-
-/* I2C ports */
-#define I2C_PORT_LIGHTBAR 5  /* Port 5 / PA6:7 on link, but PG6:7 on badger */
-
-/* Second UART port */
-#define CONFIG_UART_HOST 1
-
-#include "gpio_signal.h"
-
-/* EEPROM blocks */
-#define EEPROM_BLOCK_START_PSTORE 16  /* Host persistent storage */
-#define EEPROM_BLOCK_COUNT_PSTORE 16
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/bds/build.mk b/board/bds/build.mk
deleted file mode 100644
index e3e91f0bb2..0000000000
--- a/board/bds/build.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-# -*- makefile -*-
-# Copyright 2012 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-# the IC is TI Stellaris LM4
-CHIP:=lm4
-
-board-y=board.o
diff --git a/board/bds/ec.tasklist b/board/bds/ec.tasklist
deleted file mode 100644
index 7329da7d2d..0000000000
--- a/board/bds/ec.tasklist
+++ /dev/null
@@ -1,12 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(LIGHTBAR, lightbar_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE)
diff --git a/board/bds/gpio.inc b/board/bds/gpio.inc
deleted file mode 100644
index 374894f932..0000000000
--- a/board/bds/gpio.inc
+++ /dev/null
@@ -1,25 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Recovery signal from DOWN button */
-GPIO(RECOVERY_L, PIN(D, 1), GPIO_PULL_UP)
-GPIO(DEBUG_LED,  PIN(A, 7), GPIO_OUT_LOW)
-
-/*
- * Signals which aren't implemented on BDS but we'll emulate anyway, to
- * make it more convenient to debug other code.
- */
-UNIMPLEMENTED(WP)          /* Write protect input */
-UNIMPLEMENTED(ENTERING_RW) /* EC entering RW code */
-
-ALTERNATE(PIN_MASK(A, 0x03), 1, MODULE_UART,     0) /* UART0 */
-ALTERNATE(PIN_MASK(G, 0x40), 3, MODULE_I2C,      0) /* I2C5 SCL */
-ALTERNATE(PIN_MASK(G, 0x80), 3, GPIO_OPEN_DRAIN, 0) /* I2C5 SDA */
-ALTERNATE(PIN_MASK(B, 0x03), 1, MODULE_UART,     0) /* UART1 */
diff --git a/board/beadrix/battery.c b/board/beadrix/battery.c
new file mode 100644
index 0000000000..ba6f295e53
--- /dev/null
+++ b/board/beadrix/battery.c
@@ -0,0 +1,95 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "charge_state.h"
+#include "common.h"
+
+/*
+ * Battery info for all beadrix battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	/* GanFeng SG20 Battery Information */
+	[BATTERY_GANFENG] = {
+		.fuel_gauge = {
+			.manuf_name = "Ganfeng",
+			.device_name = "SG20",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr = 0x43,
+				.reg_mask = 0x0003,
+				.disconnect_val = 0x0000,
+			}
+		},
+		.batt_info = {
+			.voltage_max        = 8700, /* mV */
+			.voltage_normal     = 7600, /* mV */
+			.voltage_min        = 6000, /* mV */
+			.precharge_current  = 256,  /* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 50,
+			.charging_min_c     = 0,
+			.charging_max_c     = 60,
+			.discharging_min_c  = -20,
+			.discharging_max_c  = 60,
+		},
+	},
+	/* Pow-Tech SG20JL1C2S5900-P1P1 Battery Information */
+	[BATTERY_POWTECH_SG20JL1C] = {
+		.fuel_gauge = {
+			.manuf_name = "POW-TECH",
+			.device_name = "SG20",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x54,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0000,
+			}
+		},
+		.batt_info = {
+			.voltage_max        = 8800, /* mV */
+			.voltage_normal     = 7700, /* mV */
+			.voltage_min        = 6000, /* mV */
+			.precharge_current  = 350,  /* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c     = 0,
+			.charging_max_c     = 55,
+			.discharging_min_c  = -20,
+			.discharging_max_c  = 60,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_GANFENG;
diff --git a/board/beadrix/board.c b/board/beadrix/board.c
new file mode 100644
index 0000000000..92da9f5295
--- /dev/null
+++ b/board/beadrix/board.c
@@ -0,0 +1,583 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Waddledee board-specific configuration */
+
+#include "adc_chip.h"
+#include "button.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "driver/bc12/pi3usb9201.h"
+#include "driver/charger/isl923x.h"
+#include "driver/retimer/nb7v904m.h"
+#include "driver/tcpm/anx7447.h"
+#include "driver/tcpm/raa489000.h"
+#include "driver/tcpm/tcpci.h"
+#include "driver/temp_sensor/thermistor.h"
+#include "driver/usb_mux/it5205.h"
+#include "driver/usb_mux/pi3usb3x532.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "intc.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "switch.h"
+#include "system.h"
+#include "task.h"
+#include "temp_sensor.h"
+#include "uart.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+
+#define INT_RECHECK_US 5000
+
+/* C0 interrupt line shared by BC 1.2 and charger */
+static void check_c0_line(void);
+DECLARE_DEFERRED(check_c0_line);
+
+static void notify_c0_chips(void)
+{
+	/*
+	 * The interrupt line is shared between the TCPC and BC 1.2 detection
+	 * chip.  Therefore we'll need to check both ICs.
+	 */
+	schedule_deferred_pd_interrupt(0);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+
+static void check_c0_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		notify_c0_chips();
+		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+	}
+}
+
+static void usb_c0_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c0_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c0_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+}
+
+/* C1 interrupt line shared by BC 1.2, TCPC, and charger */
+static void check_c1_line(void);
+DECLARE_DEFERRED(check_c1_line);
+
+static void notify_c1_chips(void)
+{
+	schedule_deferred_pd_interrupt(1);
+	usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+}
+
+static void check_c1_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips.
+	 */
+	if (!gpio_get_level(GPIO_USB_C1_INT_V1_ODL)) {
+		notify_c1_chips();
+		hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
+	}
+}
+
+static void usb_c1_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c1_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c1_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
+}
+
+static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
+{
+	cprints(CC_USBPD, "C0: CC OVP, SBU OVP, or thermal event");
+	pd_handle_cc_overvoltage(0);
+}
+
+__override void board_pulse_entering_rw(void)
+{
+	/*
+	 * On the ITE variants, the EC_ENTERING_RW signal was connected to a pin
+	 * which is active high by default.  This causes Cr50 to think that the
+	 * EC has jumped to its RW image even though this may not be the case.
+	 * The pin is changed to GPIO_EC_ENTERING_RW2.
+	 */
+	gpio_set_level(GPIO_EC_ENTERING_RW, 1);
+	gpio_set_level(GPIO_EC_ENTERING_RW2, 1);
+	usleep(MSEC);
+	gpio_set_level(GPIO_EC_ENTERING_RW, 0);
+	gpio_set_level(GPIO_EC_ENTERING_RW2, 0);
+}
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	[ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH0 },
+	[ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH2 },
+	[ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH3 },
+	[ADC_SUB_ANALOG] = { .name = "SUB_ANALOG",
+			     .factor_mul = ADC_MAX_MVOLT,
+			     .factor_div = ADC_READ_MAX + 1,
+			     .shift = 0,
+			     .channel = CHIP_ADC_CH13 },
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* BC 1.2 chips */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	{
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+		.flags = PI3USB9201_ALWAYS_POWERED,
+	},
+	{
+		.i2c_port = I2C_PORT_SUB_USB_C1,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+		.flags = PI3USB9201_ALWAYS_POWERED,
+	},
+};
+
+/* Charger chips */
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+	{
+		.i2c_port = I2C_PORT_SUB_USB_C1,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+};
+
+/* TCPCs */
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0,
+			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
+		},
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+		.drv = &raa489000_tcpm_drv,
+	},
+	{	/* Used as TCPC + Charger */
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_SUB_USB_C1,
+			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
+		},
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+		.drv = &raa489000_tcpm_drv,
+	},
+};
+
+static int board_nb7v904m_mux_set(const struct usb_mux *me,
+				  mux_state_t mux_state);
+
+/* USB Retimer */
+const struct usb_mux_chain usbc1_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = 1,
+			.i2c_port = I2C_PORT_SUB_USB_C1,
+			.i2c_addr_flags = NB7V904M_I2C_ADDR0,
+			.driver = &nb7v904m_usb_redriver_drv,
+			.board_set = &board_nb7v904m_mux_set,
+		},
+};
+
+/* USB Muxes */
+struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+			},
+	},
+	{
+		/* Used as MUX only*/
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_SUB_USB_C1,
+				.i2c_addr_flags = AN7447_TCPC0_I2C_ADDR_FLAGS,
+				.flags = USB_MUX_FLAG_NOT_TCPC,
+				.driver = &anx7447_usb_mux_driver,
+			},
+		.next = &usbc1_retimer,
+	},
+};
+
+/* USB Mux */
+static int board_nb7v904m_mux_set(const struct usb_mux *me,
+				  mux_state_t mux_state)
+{
+	int rv = EC_SUCCESS;
+	int flipped = !!(mux_state & USB_PD_MUX_POLARITY_INVERTED);
+
+	if (mux_state & USB_PD_MUX_USB_ENABLED) {
+		/* USB with DP */
+		if (mux_state & USB_PD_MUX_DP_ENABLED) {
+			if (flipped) { /* CC2 */
+				rv |= nb7v904m_tune_usb_set_eq(
+					me, NB7V904M_CH_A_EQ_0_DB,
+					NB7V904M_CH_B_EQ_4_DB,
+					NB7V904M_CH_C_EQ_0_DB,
+					NB7V904M_CH_D_EQ_0_DB);
+				rv |= nb7v904m_tune_usb_flat_gain(
+					me, NB7V904M_CH_A_GAIN_0_DB,
+					NB7V904M_CH_B_GAIN_3P5_DB,
+					NB7V904M_CH_C_GAIN_0_DB,
+					NB7V904M_CH_D_GAIN_0_DB);
+				rv |= nb7v904m_set_loss_profile_match(
+					me, NB7V904M_LOSS_PROFILE_A,
+					NB7V904M_LOSS_PROFILE_A,
+					NB7V904M_LOSS_PROFILE_D,
+					NB7V904M_LOSS_PROFILE_D);
+			} /* CC1 */
+			else {
+				rv |= nb7v904m_tune_usb_set_eq(
+					me, NB7V904M_CH_A_EQ_0_DB,
+					NB7V904M_CH_B_EQ_0_DB,
+					NB7V904M_CH_C_EQ_4_DB,
+					NB7V904M_CH_D_EQ_0_DB);
+				rv |= nb7v904m_tune_usb_flat_gain(
+					me, NB7V904M_CH_A_GAIN_0_DB,
+					NB7V904M_CH_B_GAIN_0_DB,
+					NB7V904M_CH_C_GAIN_3P5_DB,
+					NB7V904M_CH_D_GAIN_0_DB);
+				rv |= nb7v904m_set_loss_profile_match(
+					me, NB7V904M_LOSS_PROFILE_D,
+					NB7V904M_LOSS_PROFILE_D,
+					NB7V904M_LOSS_PROFILE_A,
+					NB7V904M_LOSS_PROFILE_A);
+			}
+		} else {
+			/* USB only */
+			rv |= nb7v904m_tune_usb_set_eq(me,
+						       NB7V904M_CH_A_EQ_0_DB,
+						       NB7V904M_CH_B_EQ_4_DB,
+						       NB7V904M_CH_C_EQ_4_DB,
+						       NB7V904M_CH_D_EQ_0_DB);
+			rv |= nb7v904m_tune_usb_flat_gain(
+				me, NB7V904M_CH_A_GAIN_0_DB,
+				NB7V904M_CH_B_GAIN_3P5_DB,
+				NB7V904M_CH_C_GAIN_3P5_DB,
+				NB7V904M_CH_D_GAIN_0_DB);
+			rv |= nb7v904m_set_loss_profile_match(
+				me, NB7V904M_LOSS_PROFILE_A,
+				NB7V904M_LOSS_PROFILE_A,
+				NB7V904M_LOSS_PROFILE_A,
+				NB7V904M_LOSS_PROFILE_A);
+		}
+
+	} else if (mux_state & USB_PD_MUX_DP_ENABLED) {
+		/* 4 lanes DP */
+		rv |= nb7v904m_tune_usb_set_eq(me, NB7V904M_CH_A_EQ_0_DB,
+					       NB7V904M_CH_B_EQ_0_DB,
+					       NB7V904M_CH_C_EQ_0_DB,
+					       NB7V904M_CH_D_EQ_0_DB);
+		rv |= nb7v904m_tune_usb_flat_gain(me, NB7V904M_CH_A_GAIN_0_DB,
+						  NB7V904M_CH_B_GAIN_0_DB,
+						  NB7V904M_CH_C_GAIN_0_DB,
+						  NB7V904M_CH_D_GAIN_0_DB);
+		rv |= nb7v904m_set_loss_profile_match(
+			me, NB7V904M_LOSS_PROFILE_D, NB7V904M_LOSS_PROFILE_D,
+			NB7V904M_LOSS_PROFILE_D, NB7V904M_LOSS_PROFILE_D);
+	}
+
+	return rv;
+}
+
+void board_init(void)
+{
+	int on;
+
+	/* Enable C0 interrupt and check if it needs processing */
+	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
+
+	/* Enable C1 interrupt and check if it needs processing */
+	gpio_enable_interrupt(GPIO_USB_C1_INT_V1_ODL);
+
+	/*
+	 * If interrupt lines are already low, schedule them to be processed
+	 * after inits are completed.
+	 */
+	check_c0_line();
+	check_c1_line();
+
+	gpio_enable_interrupt(GPIO_USB_C0_CCSBU_OVP_ODL);
+
+	/* Turn on 5V if the system is on, otherwise turn it off. */
+	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
+			      CHIPSET_STATE_SOFT_OFF);
+	board_power_5v_enable(on);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+void board_hibernate(void)
+{
+	/*
+	 * Both charger ICs need to be put into their "low power mode" before
+	 * entering the Z-state.
+	 */
+	if (board_get_charger_chip_count() > 1)
+		raa489000_hibernate(1, true);
+	raa489000_hibernate(0, true);
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * Nothing to do.  TCPC C0 is internal, TCPC C1 reset pin is not
+	 * connected to the EC.
+	 */
+}
+
+__override void board_power_5v_enable(int enable)
+{
+	/*
+	 * Motherboard has a GPIO to turn on the 5V regulator, but the sub-board
+	 * sets it through the charger GPIO.
+	 */
+	gpio_set_level(GPIO_EN_PP5000, !!enable);
+	gpio_set_level(GPIO_EN_USB_A0_VBUS, !!enable);
+
+	if (isl923x_set_comparator_inversion(1, !!enable))
+		CPRINTS("Failed to %sable sub rails!", enable ? "en" : "dis");
+}
+
+int board_is_sourcing_vbus(int port)
+{
+	int regval;
+
+	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
+	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count());
+	int i;
+	int old_port;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	old_port = charge_manager_get_active_charge_port();
+
+	CPRINTS("Old chg p%d", old_port);
+
+	/* Disable all ports. */
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTS("Disabling all charge ports");
+
+		for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+			tcpc_write(i, TCPC_REG_COMMAND,
+				   TCPC_REG_COMMAND_SNK_CTRL_LOW);
+			raa489000_enable_asgate(i, false);
+		}
+
+		return EC_SUCCESS;
+	}
+
+	CPRINTS("New chg p%d", port);
+
+	/* Check if port is sourcing VBUS. */
+	if (board_is_sourcing_vbus(port)) {
+		CPRINTS("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	if (old_port != CHARGE_PORT_NONE && old_port != port) {
+		for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+			if (i == port)
+				continue;
+
+			if (tcpc_write(i, TCPC_REG_COMMAND,
+				       TCPC_REG_COMMAND_SNK_CTRL_LOW))
+				CPRINTS("p%d: sink path disable failed.", i);
+			raa489000_enable_asgate(i, false);
+		}
+
+		/*
+		 * Stop the charger IC from switching while changing ports.
+		 * Otherwise, we can overcurrent the adapter we're switching to.
+		 * (crbug.com/926056)
+		 */
+		charger_discharge_on_ac(1);
+	}
+
+	/* Enable requested charge port. */
+	if (raa489000_enable_asgate(port, true) ||
+	    tcpc_write(port, TCPC_REG_COMMAND,
+		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
+		CPRINTS("p%d: sink path enable failed.", port);
+		charger_discharge_on_ac(0);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	/* Allow the charger IC to begin/continue switching. */
+	charger_discharge_on_ac(0);
+
+	return EC_SUCCESS;
+}
+
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	if (port < 0 || port > CONFIG_USB_PD_PORT_MAX_COUNT)
+		return;
+
+	raa489000_set_output_current(port, rp);
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+	int regval;
+
+	/*
+	 * The interrupt line is shared between the TCPC and BC1.2 detector IC.
+	 * Therefore, go out and actually read the alert registers to report the
+	 * alert status.
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
+			/* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */
+			if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0))
+				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
+
+			if (regval)
+				status |= PD_STATUS_TCPC_ALERT_0;
+		}
+	}
+
+	if (board_get_usb_pd_port_count() > 1 &&
+	    !gpio_get_level(GPIO_USB_C1_INT_V1_ODL)) {
+		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
+			/* TCPCI spec Rev 1.0 says to ignore bits 14:12. */
+			if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0))
+				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
+
+			if (regval)
+				status |= PD_STATUS_TCPC_ALERT_1;
+		}
+	}
+
+	return status;
+}
+
+__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+				       int *ki_div, int *kd, int *kd_div)
+{
+	*kp = 1;
+	*kp_div = 20;
+	*ki = 1;
+	*ki_div = 250;
+	*kd = 0;
+	*kd_div = 1;
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	return pd_check_vbus_level(port, VBUS_PRESENT);
+}
+
+/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
+const struct pwm_t pwm_channels[] = { [PWM_CH_KBLIGHT] = {
+					      .channel = 0,
+					      .flags = PWM_CONFIG_DSLEEP,
+					      .freq_hz = 10000,
+				      } };
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+/* Thermistors */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+static const struct ec_response_keybd_config keybd1 = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	/* No function keys, no numeric keypad and no screenlock key */
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	/*
+	 * Future boards should use fw_config if needed.
+	 */
+
+	return &keybd1;
+}
diff --git a/board/beadrix/board.h b/board/beadrix/board.h
new file mode 100644
index 0000000000..09ef205ee1
--- /dev/null
+++ b/board/beadrix/board.h
@@ -0,0 +1,126 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Waddledee board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* Select Baseboard features */
+#define VARIANT_DEDEDE_EC_IT8320
+#include "baseboard.h"
+
+#undef CONFIG_I2C_DEBUG
+
+/* EC console commands */
+#define CONFIG_CMD_CHARGER_DUMP
+
+/* Battery */
+#define CONFIG_BATTERY_FUEL_GAUGE
+#define CONFIG_BATTERY_LOW_VOLTAGE_PROTECTION
+
+/* BC 1.2 */
+#define CONFIG_BC12_DETECT_PI3USB9201
+
+/* Charger */
+#define CONFIG_CHARGER_RAA489000
+#define PD_MAX_VOLTAGE_MV 20000
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGE_RAMP_HW
+#undef CONFIG_CHARGER_SINGLE_CHIP
+#define CONFIG_OCPC
+#define CONFIG_OCPC_DEF_RBATT_MOHMS               \
+	22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \
+	    */
+
+/*
+ * GPIO for C1 interrupts, for baseboard use
+ *
+ * Note this will only be valid for board revision 1
+ */
+#define GPIO_USB_C1_INT_ODL GPIO_USB_C1_INT_V1_ODL
+
+/* PWM */
+#define CONFIG_PWM
+
+/* TCPC */
+#define CONFIG_USB_PD_TCPM_ANX7447 /* C1: MUX  only*/
+#define CONFIG_USB_PD_TCPM_MUX
+#define CONFIG_USB_PD_TCPM_ANX7447_AUX_PU_PD
+
+/* Thermistors */
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_THERMISTOR
+#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
+
+/* USB */
+#define CONFIG_BC12_DETECT_PI3USB9201
+#define CONFIG_USB_MUX_RUNTIME_CONFIG
+#define CONFIG_USB_MUX_IT5205 /* C0: ITE MUX */
+
+/* USB PD */
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#define CONFIG_USB_PD_TCPM_RAA489000 /* C1: TCPC + Charger */
+#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
+#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
+
+/* USB Mux and Retimer */
+#define CONFIG_USB_MUX_RUNTIME_CONFIG
+#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */
+#define CONFIG_USBC_RETIMER_NB7V904M
+
+/* USB defines specific to external TCPCs */
+#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+#define CONFIG_USB_PD_VBUS_DETECT_TCPC
+#define CONFIG_USB_PD_DISCHARGE_TCPC
+#define CONFIG_USB_PD_TCPC_LOW_POWER
+
+/* Variant references the TCPCs to determine Vbus sourcing */
+#define CONFIG_USB_PD_5V_EN_CUSTOM
+
+#undef PD_POWER_SUPPLY_TURN_ON_DELAY
+#undef PD_POWER_SUPPLY_TURN_OFF_DELAY
+/* 20% margin added for these timings */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 13080 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 16080 /* us */
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum chg_id {
+	CHARGER_PRIMARY,
+	CHARGER_SECONDARY,
+	CHARGER_NUM,
+};
+
+enum pwm_channel {
+	PWM_CH_KBLIGHT,
+	PWM_CH_COUNT,
+};
+
+/* ADC channels */
+enum adc_channel {
+	ADC_VSNS_PP3300_A, /* ADC0 */
+	ADC_TEMP_SENSOR_1, /* ADC2 */
+	ADC_TEMP_SENSOR_2, /* ADC3 */
+	ADC_SUB_ANALOG, /* ADC13 */
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT };
+
+/* List of possible batteries */
+enum battery_type {
+	BATTERY_GANFENG,
+	BATTERY_POWTECH_SG20JL1C,
+	BATTERY_TYPE_COUNT,
+};
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/beadrix/build.mk b/board/beadrix/build.mk
new file mode 100644
index 0000000000..01b890bf29
--- /dev/null
+++ b/board/beadrix/build.mk
@@ -0,0 +1,15 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=it83xx
+CHIP_FAMILY:=it8320
+CHIP_VARIANT:=it8320dx
+BASEBOARD:=dedede
+
+board-y=board.o cbi_ssfc.o led.o usb_pd_policy.o
+board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/beadrix/cbi_ssfc.c b/board/beadrix/cbi_ssfc.c
new file mode 100644
index 0000000000..81f3ee0dad
--- /dev/null
+++ b/board/beadrix/cbi_ssfc.c
@@ -0,0 +1,36 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi_ssfc.h"
+#include "common.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "hooks.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+/* Cache SSFC on init since we don't expect it to change in runtime */
+static union dedede_cbi_ssfc cached_ssfc;
+BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
+
+static void cbi_ssfc_init(void)
+{
+	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
+		/* Default to 0 when CBI isn't populated */
+		cached_ssfc.raw_value = 0;
+
+	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
+}
+DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
+
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
+{
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
+}
+
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
+{
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
+}
diff --git a/board/beadrix/cbi_ssfc.h b/board/beadrix/cbi_ssfc.h
new file mode 100644
index 0000000000..bf8853a43a
--- /dev/null
+++ b/board/beadrix/cbi_ssfc.h
@@ -0,0 +1,59 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _DEDEDE_CBI_SSFC__H_
+#define _DEDEDE_CBI_SSFC__H_
+
+#include "stdint.h"
+
+/****************************************************************************
+ * Dedede CBI Second Source Factory Cache
+ */
+
+/*
+ * Base Sensor (Bits 0-2)
+ */
+enum ec_ssfc_base_sensor {
+	SSFC_SENSOR_BASE_DEFAULT = 0,
+	SSFC_SENSOR_BMI160 = 1,
+	SSFC_SENSOR_ICM426XX = 2,
+	SSFC_SENSOR_LSM6DSM = 3,
+	SSFC_SENSOR_ICM42607 = 4
+};
+
+/*
+ * Lid Sensor (Bits 3-5)
+ */
+enum ec_ssfc_lid_sensor {
+	SSFC_SENSOR_LID_DEFAULT = 0,
+	SSFC_SENSOR_BMA255 = 1,
+	SSFC_SENSOR_KX022 = 2,
+	SSFC_SENSOR_LIS2DWL = 3
+};
+
+union dedede_cbi_ssfc {
+	struct {
+		uint32_t base_sensor : 3;
+		uint32_t lid_sensor : 3;
+		uint32_t reserved_2 : 26;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Get the Base sensor type from SSFC_CONFIG.
+ *
+ * @return the Base sensor board type.
+ */
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
+
+/**
+ * Get the Lid sensor type from SSFC_CONFIG.
+ *
+ * @return the Lid sensor board type.
+ */
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
+
+#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/beadrix/ec.tasklist b/board/beadrix/ec.tasklist
new file mode 100644
index 0000000000..253501100e
--- /dev/null
+++ b/board/beadrix/ec.tasklist
@@ -0,0 +1,24 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, TRENTA_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, TRENTA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TRENTA_TASK_STACK_SIZE)
diff --git a/board/beadrix/gpio.inc b/board/beadrix/gpio.inc
new file mode 100644
index 0000000000..b450c520e8
--- /dev/null
+++ b/board/beadrix/gpio.inc
@@ -0,0 +1,146 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+/* Power State interrupts */
+GPIO_INT(SLP_S4_L,		PIN(I, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,		PIN(H, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(SLP_S0_L,		PIN(E, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,		PIN(G, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID0,	PIN(D, 0), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(RSMRST_PWRGD_L,	PIN(E, 1), GPIO_INT_BOTH | GPIO_PULL_UP, power_signal_interrupt)
+GPIO_INT(CPU_C10_GATE_L,	PIN(G, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_DRAM_OD,		PIN(D, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(PG_PP1050_ST_OD,	PIN(L, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID1,	PIN(K, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_VCCIO_EXT_OD,	PIN(D, 7), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(ESPI_RESET_L, 	 	PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt)
+
+GPIO_INT(H1_EC_PWR_BTN_ODL,	PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
+#ifdef CONFIG_LOW_POWER_IDLE
+/* Used to wake up the EC from Deep Doze mode when writing to console */
+GPIO_INT(UART1_RX,	 	PIN(B, 0), GPIO_INT_BOTH, uart_deepsleep_interrupt)	/* UART_DBG_TX_EC_RX */
+#endif
+
+/* USB-C interrupts */
+GPIO_INT(USB_C0_INT_ODL,	PIN(K, 0), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt) /* BC12 and charger */
+GPIO_INT(USB_C1_INT_V1_ODL,	PIN(E, 6), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c1_interrupt) /* TCPC, charger, BC12  - board version 1 */
+GPIO_INT(USB_C0_CCSBU_OVP_ODL,	PIN(K, 6), GPIO_INT_FALLING | GPIO_PULL_UP, c0_ccsbu_ovp_interrupt) /* Fault protection */
+
+/* Other interrupts */
+GPIO_INT(LID_OPEN,		PIN(F, 3), GPIO_INT_BOTH, lid_interrupt)
+GPIO_INT(VOLDN_BTN_ODL,		PIN(I, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(VOLUP_BTN_ODL,		PIN(I, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(EC_WP_OD,		PIN(A, 6), GPIO_INT_BOTH, switch_interrupt)
+
+/* Power sequence GPIOs */
+GPIO(EC_AP_RTCRST,		PIN(K, 2), GPIO_OUT_LOW)
+GPIO(EC_AP_PWR_BTN_ODL,		PIN(B, 6), GPIO_ODR_HIGH)
+GPIO(EC_AP_DPWROK,		PIN(L, 7), GPIO_OUT_LOW)
+GPIO(EC_AP_RSMRST_L,		PIN(H, 0), GPIO_OUT_LOW)
+GPIO(EC_AP_WAKE_ODL,		PIN(D, 5), GPIO_ODR_HIGH)
+GPIO(SYS_RST_ODL,		PIN(D, 1), GPIO_ODR_HIGH)
+GPIO(EC_AP_SYS_PWROK,		PIN(F, 2), GPIO_OUT_LOW)
+GPIO(PG_PP5000_U_OD,		PIN(E, 3), GPIO_INPUT)
+GPIO(EN_PP3300_A,		PIN(C, 5), GPIO_OUT_LOW)
+GPIO(EC_AP_PCH_PWROK_OD,	PIN(D, 6), GPIO_ODR_LOW)
+GPIO(EN_PP5000_U,		PIN(K, 5), GPIO_OUT_LOW)
+/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
+GPIO(EN_VCCST,			PIN(D, 4), GPIO_INPUT)
+GPIO(EN_VCCIO_EXT,		PIN(B, 2), GPIO_OUT_LOW)
+GPIO(EC_PROCHOT_ODL,		PIN(I, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(EC_AP_VCCST_PWRGD_OD,	PIN(E, 5), GPIO_ODR_LOW)
+GPIO(ALL_SYS_PWRGD,		PIN(B, 7), GPIO_OUT_LOW)
+GPIO(EN_SLP_Z,			PIN(K, 3), GPIO_OUT_LOW)
+
+/* Required for icelake chipset code, but implemented through other means for dedede */
+UNIMPLEMENTED(AC_PRESENT)
+UNIMPLEMENTED(PG_EC_DSW_PWROK)
+UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
+
+/* I2C pins - Alternate function below configures I2C module on these pins */
+GPIO(EC_I2C_EEPROM_SCL,		PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SDA,		PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SCL,	PIN(C, 1), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SDA,	PIN(C, 2), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,		PIN(F, 6), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SENSOR_SDA,		PIN(F, 7), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SUB_USB_C1_SCL,	PIN(E, 0), GPIO_INPUT)
+GPIO(EC_I2C_SUB_USB_C1_SDA,	PIN(E, 7), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SCL,		PIN(A, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SDA,		PIN(A, 5), GPIO_INPUT)
+
+/* USB pins */
+GPIO(EC_AP_USB_C0_HPD,		PIN(L, 4), GPIO_OUT_LOW)
+GPIO(EC_AP_USB_C1_HDMI_HPD,	PIN(K, 7), GPIO_OUT_LOW)
+GPIO(HDMI_SEL_L,		PIN(C, 6), GPIO_OUT_HIGH)
+GPIO(EN_USB_A0_VBUS,		PIN(L, 6), GPIO_OUT_LOW) /* Board rev 1, NC board rev 0 */
+
+/* MKBP event synchronization */
+GPIO(EC_AP_MKBP_INT_L,	PIN(L, 5), GPIO_ODR_HIGH)
+
+/* Misc pins which will run to the I/O board */
+GPIO(EC_SUB_IO_1_1, PIN(L, 3), GPIO_INPUT)
+GPIO(EC_SUB_IO_1_2, PIN(F, 0), GPIO_INPUT)
+GPIO(EC_SUB_IO_2_1, PIN(F, 1), GPIO_INPUT)
+GPIO(EC_SUB_IO_2_2, PIN(L, 2), GPIO_INPUT)
+
+/* Misc */
+GPIO(EN_BL_OD,			PIN(K, 4), GPIO_ODR_LOW)
+GPIO(EC_ENTERING_RW,		PIN(G, 0), GPIO_OUT_LOW)
+GPIO(EC_ENTERING_RW2,		PIN(C, 7), GPIO_OUT_LOW)
+GPIO(CCD_MODE_ODL,		PIN(H, 5), GPIO_ODR_HIGH)
+GPIO(EC_BATTERY_PRES_ODL,	PIN(I, 4), GPIO_INPUT)
+GPIO(IMVP9_PE,			PIN(J, 3), GPIO_OUT_LOW)
+GPIO(ECH1_PACKET_MODE,		PIN(H, 1), GPIO_OUT_LOW)
+
+/* LEDs */
+GPIO(EC_LED_R_ODL,		PIN(A, 1), GPIO_OUT_LOW)
+GPIO(EC_LED_B_ODL,		PIN(A, 3), GPIO_OUT_LOW)
+
+/* NC pins, enable internal pull-down to avoid floating state. */
+GPIO(GPIOA0_NC, PIN(A, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOA2_NC, PIN(A, 2), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOA7_NC, PIN(A, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOB5_NC, PIN(B, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOC3_NC, PIN(C, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOF4_NC, PIN(F, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOF5_NC, PIN(F, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG3_NC, PIN(G, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG4_NC, PIN(G, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG5_NC, PIN(G, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG6_NC, PIN(G, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG7_NC, PIN(G, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOH4_NC,	PIN(H, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOH6_NC,	PIN(H, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ0_NC, PIN(J, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ1_NC, PIN(J, 1), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ4_NC, PIN(J, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ5_NC, PIN(J, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ6_NC, PIN(J, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOM6_NC, PIN(M, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+
+/* Alternate functions GPIO definitions */
+/* UART */
+ALTERNATE(PIN_MASK(B, BIT(0) | BIT(1)), 0, MODULE_UART, 0)		/* UART for debug */
+
+/* I2C */
+ALTERNATE(PIN_MASK(B, BIT(3) | BIT(4)), 0, MODULE_I2C, 0)		/* I2C0 */
+ALTERNATE(PIN_MASK(C, BIT(1) | BIT(2)), 0, MODULE_I2C, 0)		/* I2C1 */
+ALTERNATE(PIN_MASK(F, BIT(6) | BIT(7)), 0, MODULE_I2C, GPIO_SEL_1P8V)	/* I2C2 - 1.8V */
+ALTERNATE(PIN_MASK(E, BIT(0) | BIT(7)), 0, MODULE_I2C, 0)		/* I2C4 */
+ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), 0, MODULE_I2C, 0)		/* I2C5 */
+
+/* ADC */
+ALTERNATE(PIN_MASK(L, BIT(0)), 0, MODULE_ADC, 0)			/* ADC13: EC_SUB_ANALOG */
+ALTERNATE(PIN_MASK(I, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0)	/* ADC0: EC_VSNS_PP3300_A, ADC2: TEMP_SENSOR_1, ADC3: TEMP_SENSOR_2 */
+
+/* PWM */
+ALTERNATE(PIN_MASK(A, BIT(0)), 0, MODULE_PWM, 0) /* KB_BL_PWM */
diff --git a/board/beadrix/led.c b/board/beadrix/led.c
new file mode 100644
index 0000000000..cc78a5e0b3
--- /dev/null
+++ b/board/beadrix/led.c
@@ -0,0 +1,151 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Beadrix specific LED settings. */
+
+#include "battery.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "chipset.h"
+#include "common.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "led_common.h"
+#include "system.h"
+#include "util.h"
+
+#define LED_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS)
+#define BAT_LED_ON 0
+#define BAT_LED_OFF 1
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+enum led_color {
+	LED_OFF = 0,
+	LED_RED,
+	LED_BLUE,
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
+};
+
+static void led_set_color(enum led_color color)
+{
+	gpio_set_level(GPIO_EC_LED_R_ODL,
+		       (color == LED_RED) ? BAT_LED_ON : BAT_LED_OFF);
+	gpio_set_level(GPIO_EC_LED_B_ODL,
+		       (color == LED_BLUE) ? BAT_LED_ON : BAT_LED_OFF);
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	brightness_range[EC_LED_COLOR_RED] = 1;
+	brightness_range[EC_LED_COLOR_BLUE] = 1;
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (brightness[EC_LED_COLOR_BLUE] != 0)
+		led_set_color(LED_BLUE);
+	else if (brightness[EC_LED_COLOR_RED] != 0)
+		led_set_color(LED_RED);
+	else
+		led_set_color(LED_OFF);
+
+	return EC_SUCCESS;
+}
+
+static void board_led_set_battery(void)
+{
+	static int battery_ticks;
+	enum led_color color = LED_OFF;
+	int period = 0;
+
+	battery_ticks++;
+
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
+		/* Always indicate amber on when charging. */
+		color = LED_RED;
+		break;
+	case LED_PWRS_DISCHARGE:
+		if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
+			/* Discharging in S3: Red 1 sec, off 3 sec */
+			period = (1 + 3) * LED_ONE_SEC;
+			battery_ticks = battery_ticks % period;
+			if (battery_ticks < 1 * LED_ONE_SEC)
+				color = LED_RED;
+			else
+				color = LED_OFF;
+		} else if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
+			/* Discharging in S5: off */
+			color = LED_OFF;
+		} else if (chipset_in_state(CHIPSET_STATE_ON)) {
+			/* Discharging in S0: Blue on */
+			color = LED_BLUE;
+		}
+		break;
+	case LED_PWRS_ERROR:
+		/* Battery error: Red 1 sec, off 1 sec */
+		period = (1 + 1) * LED_ONE_SEC;
+		battery_ticks = battery_ticks % period;
+		if (battery_ticks < 1 * LED_ONE_SEC)
+			color = LED_RED;
+		else
+			color = LED_OFF;
+		break;
+	case LED_PWRS_CHARGE_NEAR_FULL:
+		/* Full Charged: Blue on */
+		color = LED_BLUE;
+		break;
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		color = LED_BLUE;
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		/* Factory mode: Blue 2 sec, Red 2 sec */
+		period = (2 + 2) * LED_ONE_SEC;
+		battery_ticks = battery_ticks % period;
+		if (battery_ticks < 2 * LED_ONE_SEC)
+			color = LED_BLUE;
+		else
+			color = LED_RED;
+		break;
+	default:
+		/* Other states don't alter LED behavior */
+		break;
+	}
+
+	led_set_color(color);
+}
+
+/* Called by hook task every TICK */
+static void led_tick(void)
+{
+	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
+		board_led_set_battery();
+}
+DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
+
+void led_control(enum ec_led_id led_id, enum ec_led_state state)
+{
+	enum led_color color;
+
+	if ((led_id != EC_LED_ID_RECOVERY_HW_REINIT_LED) &&
+	    (led_id != EC_LED_ID_SYSRQ_DEBUG_LED))
+		return;
+
+	if (state == LED_STATE_RESET) {
+		led_auto_control(EC_LED_ID_BATTERY_LED, 1);
+		board_led_set_battery();
+		return;
+	}
+
+	color = state ? LED_BLUE : LED_OFF;
+
+	led_auto_control(EC_LED_ID_BATTERY_LED, 0);
+
+	led_set_color(color);
+}
diff --git a/board/beadrix/usb_pd_policy.c b/board/beadrix/usb_pd_policy.c
new file mode 100644
index 0000000000..c22c68d224
--- /dev/null
+++ b/board/beadrix/usb_pd_policy.c
@@ -0,0 +1,66 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery_smart.h"
+#include "charge_manager.h"
+#include "charger.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "driver/charger/isl923x_public.h"
+#include "driver/tcpm/tcpci.h"
+#include "usb_pd.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+int pd_check_vconn_swap(int port)
+{
+	/* Allow VCONN swaps if the AP is on */
+	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
+}
+
+void pd_power_supply_reset(int port)
+{
+	if (port < 0 || port >= board_get_usb_pd_port_count())
+		return;
+
+	/* Disable VBUS */
+	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	if (port >= board_get_usb_pd_port_count())
+		return EC_ERROR_INVAL;
+
+	/* Disable charging. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
+	if (rv)
+		return rv;
+
+	/* Our policy is not to source VBUS when the AP is off. */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	/* Provide Vbus. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
+	if (rv)
+		return rv;
+
+	rv = raa489000_enable_asgate(port, true);
+	if (rv)
+		return rv;
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
diff --git a/board/beadrix/vif_override.xml b/board/beadrix/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/beadrix/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/beetley/battery.c b/board/beetley/battery.c
new file mode 100644
index 0000000000..0402ef33fd
--- /dev/null
+++ b/board/beetley/battery.c
@@ -0,0 +1,192 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "charge_state.h"
+#include "common.h"
+
+/*
+ * Battery info for all beetley battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	/* SMP L20M3PG0 Battery Information */
+	[BATTERY_SMP1] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP",
+			.device_name = "L20M3PG0",
+			.ship_mode = {
+				.reg_addr = 0x34,
+				.reg_data = { 0x0000, 0x1000 },
+			},
+			.fet = {
+				.reg_addr = 0x00,
+				.reg_mask = 0x0018,
+				.disconnect_val = 0x0000,
+				.cfet_mask = 0x0008,
+				.cfet_off_val = 0x0000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13200, /* mV */
+			.voltage_normal		= 11520, /* mV */
+			.voltage_min		= 9000,  /* mV */
+			.precharge_current	= 256,	 /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 60,
+		},
+	},
+
+	/* SMP L20M3PG3 Battery Information */
+	[BATTERY_SMP2] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP",
+			.device_name = "L20M3PG3",
+			.ship_mode = {
+				.reg_addr = 0x34,
+				.reg_data = { 0x0000, 0x1000 },
+			},
+			.fet = {
+				.reg_addr = 0x00,
+				.reg_mask = 0x0018,
+				.disconnect_val = 0x0000,
+				.cfet_mask = 0x0008,
+				.cfet_off_val = 0x0000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13200, /* mV */
+			.voltage_normal		= 11520, /* mV */
+			.voltage_min		= 9000,  /* mV */
+			.precharge_current	= 256,	 /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 60,
+		},
+	},
+
+	/* LGC L20L3PG0 Battery Information */
+	[BATTERY_LGC] = {
+		.fuel_gauge = {
+			.manuf_name = "LGC",
+			.device_name = "L20L3PG0",
+			.ship_mode = {
+				.reg_addr = 0x34,
+				.reg_data = { 0x0000, 0x1000 },
+			},
+			.fet = {
+				.reg_addr = 0x00,
+				.reg_mask = 0x0018,
+				.disconnect_val = 0x0000,
+				.cfet_mask = 0x0008,
+				.cfet_off_val = 0x0000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13200, /* mV */
+			.voltage_normal		= 11520, /* mV */
+			.voltage_min		= 9000,  /* mV */
+			.precharge_current	= 256,	 /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 73,
+		},
+	},
+
+	/* Sunwoda L20D3PG0 Battery Information */
+	[BATTERY_SUNWODA] = {
+		.fuel_gauge = {
+			.manuf_name = "Sunwoda",
+			.device_name = "L20D3PG0",
+			.ship_mode = {
+				.reg_addr = 0x34,
+				.reg_data = { 0x0000, 0x1000 },
+			},
+			.fet = {
+				.reg_addr = 0x00,
+				.reg_mask = 0x0018,
+				.disconnect_val = 0x0000,
+				.cfet_mask = 0x0008,
+				.cfet_off_val = 0x0000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13200, /* mV */
+			.voltage_normal		= 11520, /* mV */
+			.voltage_min		= 9000,  /* mV */
+			.precharge_current	= 205,	 /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 60,
+		},
+	},
+
+	/* Celxert L20C3PG0 Battery Information */
+	[BATTERY_CELXPERT] = {
+		.fuel_gauge = {
+			.manuf_name = "Celxpert",
+			.device_name = "L20C3PG0",
+			.ship_mode = {
+				.reg_addr = 0x34,
+				.reg_data = { 0x0000, 0x1000 },
+			},
+			.fet = {
+				.reg_addr = 0x00,
+				.reg_mask = 0x0018,
+				.disconnect_val = 0x0000,
+				.cfet_mask = 0x0008,
+				.cfet_off_val = 0x0000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13200, /* mV */
+			.voltage_normal		= 11520, /* mV */
+			.voltage_min		= 9000,  /* mV */
+			.precharge_current	= 200,	 /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 60,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SMP1;
diff --git a/board/beetley/board.c b/board/beetley/board.c
new file mode 100644
index 0000000000..7bd12e9bdb
--- /dev/null
+++ b/board/beetley/board.c
@@ -0,0 +1,496 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Beetley board-specific configuration */
+
+#include "adc_chip.h"
+#include "button.h"
+#include "cbi_fw_config.h"
+#include "cbi_ssfc.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "cros_board_info.h"
+#include "driver/accel_lis2dw12.h"
+#include "driver/accelgyro_lsm6dsm.h"
+#include "driver/bc12/pi3usb9201.h"
+#include "driver/charger/isl923x.h"
+#include "driver/tcpm/raa489000.h"
+#include "driver/tcpm/tcpci.h"
+#include "driver/temp_sensor/thermistor.h"
+#include "driver/usb_mux/it5205.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "intc.h"
+#include "keyboard_raw.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "switch.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "tcpm/tcpci.h"
+#include "temp_sensor.h"
+#include "uart.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+
+#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define INT_RECHECK_US 5000
+
+__override struct keyboard_scan_config keyscan_config = {
+	.output_settle_us = 80,
+	.debounce_down_us = 30 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x1c, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
+		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
+	},
+};
+
+/* C0 interrupt line shared by BC 1.2 and charger */
+static void check_c0_line(void);
+DECLARE_DEFERRED(check_c0_line);
+
+static void hdmi_hpd_interrupt(enum gpio_signal s)
+{
+	gpio_set_level(GPIO_USB_C1_DP_HPD, !gpio_get_level(s));
+}
+
+static void notify_c0_chips(void)
+{
+	/*
+	 * The interrupt line is shared between the TCPC and BC 1.2 detection
+	 * chip.  Therefore we'll need to check both ICs.
+	 */
+	schedule_deferred_pd_interrupt(0);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+
+static void check_c0_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		notify_c0_chips();
+		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+	}
+}
+
+static void usb_c0_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c0_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c0_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+}
+
+static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
+{
+	cprints(CC_USBPD, "C0: CC OVP, SBU OVP, or thermal event");
+	pd_handle_cc_overvoltage(0);
+}
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	[ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH0 },
+	[ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH2 },
+	[ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH3 },
+	[ADC_TEMP_SENSOR_3] = { .name = "TEMP_SENSOR3",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH15 },
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* BC 1.2 chips */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	{
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+		.flags = PI3USB9201_ALWAYS_POWERED,
+	},
+};
+
+/* Charger chips */
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+};
+
+/* TCPCs */
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0,
+			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
+		},
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+		.drv = &raa489000_tcpm_drv,
+	},
+};
+
+/* USB Muxes */
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+			},
+	},
+};
+
+static const struct ec_response_keybd_config beetley_keybd = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY | KEYBD_CAP_NUMERIC_KEYPAD,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &beetley_keybd;
+}
+
+/* USB-A charging control */
+const int usb_port_enable[USB_PORT_COUNT] = { GPIO_EN_USB_A0_VBUS };
+
+/* Sensors */
+static struct mutex g_lid_mutex;
+static struct mutex g_base_mutex;
+
+/* Matrices to rotate accelerometers into the standard reference. */
+static const mat33_fp_t base_lsm6dsm_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					     { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
+
+static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
+
+/* Lid accel private data */
+static struct stprivate_data g_lis2dwl_data;
+struct motion_sensor_t motion_sensors[] = {
+	[LID_ACCEL] = {
+		.name = "Lid Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LIS2DWL,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &lis2dw12_drv,
+		.mutex = &g_lid_mutex,
+		.drv_data = &g_lis2dwl_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LIS2DWL_ADDR1_FLAGS,
+		.rot_standard_ref = NULL,		/* identity matrix */
+		.default_range = 2, /* g */
+		.min_frequency = LIS2DW12_ODR_MIN_VAL,
+		.max_frequency = LIS2DW12_ODR_MAX_VAL,
+		.config = {
+			/* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 12500 | ROUND_UP_FLAG,
+			},
+			/* Sensor on for lid angle detection */
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+		},
+	},
+	[BASE_ACCEL] = {
+		.name = "Base Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LSM6DS3,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &lsm6dsm_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
+				MOTIONSENSE_TYPE_ACCEL),
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
+		.rot_standard_ref = &base_lsm6dsm_ref,
+		.default_range = 4,  /* g */
+		.min_frequency = LSM6DSM_ODR_MIN_VAL,
+		.max_frequency = LSM6DSM_ODR_MAX_VAL,
+		.config = {
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 13000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+		},
+	},
+	[BASE_GYRO] = {
+		.name = "Base Gyro",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LSM6DS3,
+		.type = MOTIONSENSE_TYPE_GYRO,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &lsm6dsm_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
+				MOTIONSENSE_TYPE_GYRO),
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
+		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
+		.rot_standard_ref = &base_lsm6dsm_ref,
+		.min_frequency = LSM6DSM_ODR_MIN_VAL,
+		.max_frequency = LSM6DSM_ODR_MAX_VAL,
+	},
+};
+
+const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+void board_init(void)
+{
+	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C0_CCSBU_OVP_ODL);
+
+	gpio_enable_interrupt(GPIO_HDMI_HPD_SUB_ODL);
+
+	/* Set LEDs luminance */
+	pwm_set_duty(PWM_CH_LED_RED, 70);
+	pwm_set_duty(PWM_CH_LED_GREEN, 70);
+	pwm_set_duty(PWM_CH_LED_WHITE, 70);
+
+	/*Enable Base Accel interrupt*/
+	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
+
+	/*
+	 * If interrupt lines are already low, schedule them to be processed
+	 * after inits are completed.
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL))
+		hook_call_deferred(&check_c0_line_data, 0);
+
+	/* Setting scan mask KSO11, KSO12, KSO13 and KSO14 */
+	keyscan_config.actual_key_mask[11] = 0xfe;
+	keyscan_config.actual_key_mask[12] = 0xff;
+	keyscan_config.actual_key_mask[13] = 0xff;
+	keyscan_config.actual_key_mask[14] = 0xff;
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+void board_hibernate(void)
+{
+	/*
+	 * Charger IC need to be put into their "low power mode" before
+	 * entering the Z-state.
+	 *
+	 * b:186717219: In order to solve the power consumption problem of
+	 * hibernate，HW solution is adopted after board id 3 to solve the
+	 * problem that AC cannot wake up hibernate mode.
+	 */
+	raa489000_hibernate(0, true);
+}
+
+__override void board_pulse_entering_rw(void)
+{
+	/*
+	 * On the ITE variants, the EC_ENTERING_RW signal was connected to a pin
+	 * which is active high by default.  This causes Cr50 to think that the
+	 * EC has jumped to its RW image even though this may not be the case.
+	 * The pin is changed to GPIO_EC_ENTERING_RW2.
+	 */
+	gpio_set_level(GPIO_EC_ENTERING_RW, 1);
+	gpio_set_level(GPIO_EC_ENTERING_RW2, 1);
+	usleep(MSEC);
+	gpio_set_level(GPIO_EC_ENTERING_RW, 0);
+	gpio_set_level(GPIO_EC_ENTERING_RW2, 0);
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * Nothing to do.  TCPC C0 is internal, TCPC C1 reset pin is not
+	 * connected to the EC.
+	 */
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+	int regval;
+
+	/*
+	 * The interrupt line is shared between the TCPC and BC1.2 detector IC.
+	 * Therefore, go out and actually read the alert registers to report the
+	 * alert status.
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
+			/* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */
+			if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0))
+				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
+
+			if (regval)
+				status |= PD_STATUS_TCPC_ALERT_0;
+		}
+	}
+
+	return status;
+}
+
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	if (port < 0 || port > board_get_usb_pd_port_count())
+		return;
+
+	raa489000_set_output_current(port, rp);
+}
+
+int board_is_sourcing_vbus(int port)
+{
+	int regval;
+
+	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
+	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
+}
+
+int board_set_active_charge_port(int port)
+{
+	if (port != 0 && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	CPRINTUSB("New chg p%d", port);
+
+	/* Disable all ports. */
+	if (port == CHARGE_PORT_NONE) {
+		tcpc_write(0, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
+		raa489000_enable_asgate(0, false);
+		return EC_SUCCESS;
+	}
+
+	/* Check if port is sourcing VBUS. */
+	if (board_is_sourcing_vbus(port)) {
+		CPRINTUSB("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	/* Enable requested charge port. */
+	if (raa489000_enable_asgate(port, true) ||
+	    tcpc_write(0, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
+		CPRINTUSB("p%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_LED_RED] = {
+		.channel = 1,
+		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
+		.freq_hz = 2400,
+	},
+
+	[PWM_CH_LED_GREEN] = {
+		.channel = 2,
+		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
+		.freq_hz = 2400,
+	},
+
+	[PWM_CH_LED_WHITE] = {
+		.channel = 3,
+		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
+		.freq_hz = 2400,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+/* Thermistors */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1] = { .name = "Charge",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "5V_Inductor",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/* This callback disables keyboard when convertibles are fully open */
+__override void lid_angle_peripheral_enable(int enable)
+{
+	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
+
+	/*
+	 * If the lid is in tablet position via other sensors,
+	 * ignore the lid angle, which might be faulty then
+	 * disable keyboard.
+	 */
+	if (tablet_get_mode())
+		enable = 0;
+
+	if (enable) {
+		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
+	} else {
+		/*
+		 * Ensure that the chipset is off before disabling the keyboard.
+		 * When the chipset is on, the EC keeps the keyboard enabled and
+		 * the AP decides whether to ignore input devices or not.
+		 */
+		if (!chipset_in_s0)
+			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
+	}
+}
diff --git a/board/beetley/board.h b/board/beetley/board.h
new file mode 100644
index 0000000000..f2d43534fa
--- /dev/null
+++ b/board/beetley/board.h
@@ -0,0 +1,154 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Beetley board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* Select Baseboard features */
+#define VARIANT_DEDEDE_EC_IT8320
+#include "baseboard.h"
+
+/* Battery */
+#define CONFIG_BATTERY_FUEL_GAUGE
+#define CONFIG_BATTERY_V2
+#define CONFIG_BATTERY_COUNT 1
+#define CONFIG_HOSYCMD_BATTERY_V2
+
+/* Sysetem unlocked in early development */
+#define CONFIG_SYSTEM_UNLOCKED
+
+/* BC 1.2 */
+#define CONFIG_BC12_DETECT_PI3USB9201
+
+/* Charger */
+#define CONFIG_CHARGE_RAMP_HW
+#define CONFIG_CHARGER_RAA489000
+/*
+ * b/147463641: The charger IC seems to overdraw ~4%, therefore we
+ * reduce our target accordingly.
+ */
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 4
+#define PD_MAX_VOLTAGE_MV 20000
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
+#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
+
+/* DAC for PSYS */
+#define CONFIG_DAC
+
+/* LED */
+#define CONFIG_LED_ONOFF_STATES
+
+/*SENSOR*/
+#define CONFIG_CMD_ACCELS
+#define CONFIG_CMD_ACCEL_INFO
+
+#define CONFIG_ACCEL_LIS2DWL /* Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
+
+/* Lid operates in forced mode, base in FIFO */
+#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
+#define CONFIG_ACCEL_FIFO
+#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */
+#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
+
+#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_UPDATE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+
+#define CONFIG_TABLET_MODE
+#define CONFIG_TABLET_MODE_SWITCH
+#define CONFIG_GMR_TABLET_MODE
+
+/* PWM */
+#define CONFIG_PWM
+
+/* TCPC */
+#define CONFIG_USB_PD_PORT_MAX_COUNT 1
+#define CONFIG_USB_PD_TCPM_RAA489000
+
+/* USB defines specific to external TCPCs */
+#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+#define CONFIG_USB_PD_VBUS_DETECT_TCPC
+#define CONFIG_USB_PD_DISCHARGE_TCPC
+#define CONFIG_USB_PD_TCPC_LOW_POWER
+
+/* EC console commands */
+#define CONFIG_CMD_TCPC_DUMP
+
+/* Variant references the TCPCs to determine Vbus sourcing */
+#define CONFIG_USB_PD_5V_EN_CUSTOM
+
+/* Thermistors */
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_THERMISTOR
+#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
+
+/* USB Mux */
+#define CONFIG_USB_MUX_IT5205
+
+/* KeyBoard */
+#define CONFIG_KEYBOARD_REFRESH_ROW3
+#define CONFIG_KEYBOARD_KEYPAD
+#define CONFIG_KEYBOARD_STRICT_DEBOUNCE
+
+/* USB Type A Features */
+#define USB_PORT_COUNT 1
+#define CONFIG_USB_PORT_POWER_DUMB
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum pwm_channel {
+	PWM_CH_LED_RED,
+	PWM_CH_LED_GREEN,
+	PWM_CH_LED_WHITE,
+	PWM_CH_COUNT,
+};
+
+/* Motion sensors */
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
+
+/* ADC channels */
+enum adc_channel {
+	ADC_VSNS_PP3300_A, /* ADC0 */
+	ADC_TEMP_SENSOR_1, /* ADC2 */
+	ADC_TEMP_SENSOR_2, /* ADC3 */
+	ADC_TEMP_SENSOR_3, /* ADC15 */
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1,
+	TEMP_SENSOR_2,
+	TEMP_SENSOR_3,
+	TEMP_SENSOR_COUNT
+};
+
+/* List of possible batteries */
+enum battery_type {
+	BATTERY_SMP1,
+	BATTERY_SMP2,
+	BATTERY_LGC,
+	BATTERY_SUNWODA,
+	BATTERY_CELXPERT,
+	BATTERY_TYPE_COUNT,
+};
+
+void motion_interrupt(enum gpio_signal signal);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/beetley/build.mk b/board/beetley/build.mk
new file mode 100644
index 0000000000..01b890bf29
--- /dev/null
+++ b/board/beetley/build.mk
@@ -0,0 +1,15 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=it83xx
+CHIP_FAMILY:=it8320
+CHIP_VARIANT:=it8320dx
+BASEBOARD:=dedede
+
+board-y=board.o cbi_ssfc.o led.o usb_pd_policy.o
+board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/beetley/cbi_ssfc.c b/board/beetley/cbi_ssfc.c
new file mode 100644
index 0000000000..81f3ee0dad
--- /dev/null
+++ b/board/beetley/cbi_ssfc.c
@@ -0,0 +1,36 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi_ssfc.h"
+#include "common.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "hooks.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+/* Cache SSFC on init since we don't expect it to change in runtime */
+static union dedede_cbi_ssfc cached_ssfc;
+BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
+
+static void cbi_ssfc_init(void)
+{
+	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
+		/* Default to 0 when CBI isn't populated */
+		cached_ssfc.raw_value = 0;
+
+	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
+}
+DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
+
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
+{
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
+}
+
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
+{
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
+}
diff --git a/board/beetley/cbi_ssfc.h b/board/beetley/cbi_ssfc.h
new file mode 100644
index 0000000000..bf8853a43a
--- /dev/null
+++ b/board/beetley/cbi_ssfc.h
@@ -0,0 +1,59 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _DEDEDE_CBI_SSFC__H_
+#define _DEDEDE_CBI_SSFC__H_
+
+#include "stdint.h"
+
+/****************************************************************************
+ * Dedede CBI Second Source Factory Cache
+ */
+
+/*
+ * Base Sensor (Bits 0-2)
+ */
+enum ec_ssfc_base_sensor {
+	SSFC_SENSOR_BASE_DEFAULT = 0,
+	SSFC_SENSOR_BMI160 = 1,
+	SSFC_SENSOR_ICM426XX = 2,
+	SSFC_SENSOR_LSM6DSM = 3,
+	SSFC_SENSOR_ICM42607 = 4
+};
+
+/*
+ * Lid Sensor (Bits 3-5)
+ */
+enum ec_ssfc_lid_sensor {
+	SSFC_SENSOR_LID_DEFAULT = 0,
+	SSFC_SENSOR_BMA255 = 1,
+	SSFC_SENSOR_KX022 = 2,
+	SSFC_SENSOR_LIS2DWL = 3
+};
+
+union dedede_cbi_ssfc {
+	struct {
+		uint32_t base_sensor : 3;
+		uint32_t lid_sensor : 3;
+		uint32_t reserved_2 : 26;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Get the Base sensor type from SSFC_CONFIG.
+ *
+ * @return the Base sensor board type.
+ */
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
+
+/**
+ * Get the Lid sensor type from SSFC_CONFIG.
+ *
+ * @return the Lid sensor board type.
+ */
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
+
+#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/beetley/ec.tasklist b/board/beetley/ec.tasklist
new file mode 100644
index 0000000000..8ccdfc81b2
--- /dev/null
+++ b/board/beetley/ec.tasklist
@@ -0,0 +1,22 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, TRENTA_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE)
diff --git a/board/beetley/gpio.inc b/board/beetley/gpio.inc
new file mode 100644
index 0000000000..0677e5a2ac
--- /dev/null
+++ b/board/beetley/gpio.inc
@@ -0,0 +1,152 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+/* Power State interrupts */
+GPIO_INT(SLP_S4_L,		PIN(I, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,		PIN(H, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(SLP_S0_L,		PIN(E, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,		PIN(G, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID0,	PIN(D, 0), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(RSMRST_PWRGD_L,	PIN(E, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(CPU_C10_GATE_L,	PIN(G, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_DRAM_OD,		PIN(D, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(PG_PP1050_ST_OD,	PIN(L, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID1,	PIN(K, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_VCCIO_EXT_OD,	PIN(D, 7), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(ESPI_RESET_L, 	 PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt)
+
+GPIO_INT(H1_EC_PWR_BTN_ODL,	PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
+#ifdef CONFIG_LOW_POWER_IDLE
+/* Used to wake up the EC from Deep Doze mode when writing to console */
+GPIO_INT(UART1_RX,	 PIN(B, 0), GPIO_INT_BOTH, uart_deepsleep_interrupt)	/* UART_DBG_TX_EC_RX */
+#endif
+
+/* USB-C interrupts */
+GPIO_INT(USB_C0_INT_ODL,	PIN(K, 0), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt) /* BC12 and charger */
+GPIO_INT(USB_C0_CCSBU_OVP_ODL,	PIN(K, 6), GPIO_INT_FALLING | GPIO_PULL_UP, c0_ccsbu_ovp_interrupt) /* Fault protection */
+
+/* Other interrupts */
+GPIO_INT(LID_OPEN,		PIN(F, 3), GPIO_INT_BOTH, lid_interrupt)
+GPIO_INT(LID_360_L,		PIN(A, 7), GPIO_INT_BOTH, gmr_tablet_switch_isr)
+GPIO_INT(VOLDN_BTN_ODL,		PIN(I, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(VOLUP_BTN_ODL,		PIN(I, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(J, 0), GPIO_INT_FALLING | GPIO_SEL_1P8V, lsm6dsm_interrupt)
+GPIO_INT(EC_WP_OD,		PIN(A, 6), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(HDMI_HPD_SUB_ODL,	PIN(E, 7), GPIO_INT_BOTH, hdmi_hpd_interrupt)
+
+
+/* Power sequence GPIOs */
+GPIO(EC_AP_RTCRST,		PIN(K, 2), GPIO_OUT_LOW)
+GPIO(EC_AP_PWR_BTN_ODL,		PIN(B, 6), GPIO_ODR_HIGH)
+GPIO(EC_AP_DPWROK,		PIN(L, 7), GPIO_OUT_LOW)
+GPIO(EC_AP_RSMRST_L,		PIN(H, 0), GPIO_OUT_LOW)
+GPIO(EC_AP_WAKE_ODL,		PIN(D, 5), GPIO_ODR_HIGH)
+GPIO(SYS_RST_ODL,		PIN(D, 1), GPIO_ODR_HIGH)
+GPIO(EC_AP_SYS_PWROK,		PIN(F, 2), GPIO_OUT_LOW)
+GPIO(PG_PP5000_U_OD,		PIN(E, 3), GPIO_INPUT)
+GPIO(EN_PP3300_A,		PIN(C, 5), GPIO_OUT_LOW)
+GPIO(EC_AP_PCH_PWROK_OD,	PIN(D, 6), GPIO_ODR_LOW)
+GPIO(EN_PP5000_U,		PIN(K, 5), GPIO_OUT_LOW)
+/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
+GPIO(EN_VCCST,			PIN(D, 4), GPIO_INPUT)
+GPIO(EN_VCCIO_EXT,		PIN(B, 2), GPIO_OUT_LOW)
+GPIO(EC_PROCHOT_ODL,		PIN(I, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(EC_AP_VCCST_PWRGD_OD,	PIN(E, 5), GPIO_ODR_LOW)
+GPIO(ALL_SYS_PWRGD,		PIN(B, 7), GPIO_OUT_LOW)
+GPIO(EN_SLP_Z,			PIN(K, 3), GPIO_OUT_LOW)
+
+/* Required for icelake chipset code, but implemented through other means for dedede */
+UNIMPLEMENTED(AC_PRESENT)
+UNIMPLEMENTED(PG_EC_DSW_PWROK)
+UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
+
+/* Used by baseboard z-state enable, but not present on beetley */
+UNIMPLEMENTED(USB_C1_INT_ODL)
+
+/* I2C pins - Alternate function below configures I2C module on these pins */
+GPIO(EC_I2C_EEPROM_SCL,		PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SDA,		PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SCL,	PIN(C, 1), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SDA,	PIN(C, 2), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,		PIN(F, 6), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SENSOR_SDA,		PIN(F, 7), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_USB_C0_SCL,		PIN(A, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SDA,		PIN(A, 5), GPIO_INPUT)
+
+/* USB pins */
+GPIO(EN_USB_A0_VBUS,		PIN(L, 6), GPIO_OUT_LOW)
+GPIO(EN_USB_A1_VBUS,		PIN(E, 6), GPIO_OUT_LOW)
+GPIO(EC_AP_USB_C0_HPD,		PIN(L, 4), GPIO_OUT_LOW)
+GPIO(EC_AP_USB_C1_HDMI_HPD,	PIN(K, 7), GPIO_OUT_LOW)
+GPIO(HDMI_SEL_L,		PIN(C, 6), GPIO_OUT_LOW)
+
+/* MKBP event synchronization */
+GPIO(EC_AP_MKBP_INT_L,	PIN(L, 5), GPIO_ODR_HIGH)
+
+/* Misc pins which will run to the I/O board */
+
+
+/* Misc */
+GPIO(EN_BL_OD,			PIN(K, 4), GPIO_ODR_LOW)
+GPIO(EC_ENTERING_RW,		PIN(G, 0), GPIO_OUT_LOW)
+GPIO(EC_ENTERING_RW2,		PIN(C, 7), GPIO_OUT_LOW)
+GPIO(CCD_MODE_ODL,		PIN(H, 5), GPIO_ODR_HIGH)
+GPIO(EC_BATTERY_PRES_ODL,	PIN(I, 4), GPIO_INPUT)
+GPIO(ECH1_PACKET_MODE,		PIN(H, 1), GPIO_OUT_LOW)
+
+/*TP*/
+GPIO(TP, PIN(C, 3), GPIO_INPUT | GPIO_HIGH)
+
+/* NC pins, enable internal pull-down to avoid floating state. */
+GPIO(GPIOA0_NC, PIN(A, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOB5_NC, PIN(B, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOC4_NC, PIN(C, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOE0_NC, PIN(E, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOF0_NC, PIN(F, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOF1_NC, PIN(F, 1), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOF4_NC, PIN(F, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOF5_NC, PIN(F, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG3_NC, PIN(G, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG4_NC, PIN(G, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG5_NC, PIN(G, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG6_NC, PIN(G, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG7_NC, PIN(G, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOH2_NC, PIN(H, 2), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOH4_NC, PIN(H, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOH6_NC, PIN(H, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ1_NC, PIN(J, 1), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ3_NC, PIN(J, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ4_NC, PIN(J, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ5_NC, PIN(J, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ6_NC, PIN(J, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOL0_NC, PIN(L, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOL3_NC, PIN(L, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOM6_NC, PIN(M, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+
+/* Alternate functions GPIO definitions */
+/* UART */
+ALTERNATE(PIN_MASK(B, BIT(0) | BIT(1)), 0, MODULE_UART, 0)		/* UART for debug */
+
+/* I2C */
+ALTERNATE(PIN_MASK(B, BIT(3) | BIT(4)), 0, MODULE_I2C, 0)		/* I2C0 */
+ALTERNATE(PIN_MASK(C, BIT(1) | BIT(2)), 0, MODULE_I2C, 0)		/* I2C1 */
+ALTERNATE(PIN_MASK(F, BIT(6) | BIT(7)), 0, MODULE_I2C, GPIO_SEL_1P8V)	/* I2C2 - 1.8V SENSOR */
+ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), 0, MODULE_I2C, 0)		/* I2C5 */
+
+/* ADC */
+ALTERNATE(PIN_MASK(L, BIT(2)), 0, MODULE_ADC, 0)		    	/* ADC15: TEMP_SENSOR_3 */
+ALTERNATE(PIN_MASK(I, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0)	/* ADC0: EC_VSNS_PP3300_A, ADC2: TEMP_SENSOR_1, ADC3: TEMP_SENSOR_2 */
+
+/* DAC */
+ALTERNATE(PIN_MASK(J, BIT(2)), 0, MODULE_DAC, 0)			/* DAC2: EC_AP_PSYS */
+
+/* PWM */
+ALTERNATE(PIN_MASK(A, BIT(1) | BIT(2) | BIT(3)), 0, MODULE_PWM, 0) /* RED led, GREEN led, WHITE led */
diff --git a/board/beetley/led.c b/board/beetley/led.c
new file mode 100644
index 0000000000..8a79e41773
--- /dev/null
+++ b/board/beetley/led.c
@@ -0,0 +1,117 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Beetley specific PWM LED settings.
+ */
+
+#include "common.h"
+#include "gpio.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+#include "pwm.h"
+
+#define LED_OFF_LVL 0
+#define LED_ON_LVL 1
+
+__override const int led_charge_lvl_1 = 5;
+
+__override const int led_charge_lvl_2 = 97;
+
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
+
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    1 * LED_ONE_SEC },
+						  { LED_OFF,
+						    3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_RED:
+		pwm_enable(PWM_CH_LED_RED, LED_ON_LVL);
+		pwm_enable(PWM_CH_LED_GREEN, LED_OFF_LVL);
+		break;
+	case EC_LED_COLOR_AMBER:
+		pwm_enable(PWM_CH_LED_RED, LED_ON_LVL);
+		pwm_enable(PWM_CH_LED_GREEN, LED_ON_LVL);
+		break;
+	case EC_LED_COLOR_GREEN:
+		pwm_enable(PWM_CH_LED_RED, LED_OFF_LVL);
+		pwm_enable(PWM_CH_LED_GREEN, LED_ON_LVL);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		pwm_enable(PWM_CH_LED_RED, LED_OFF_LVL);
+		pwm_enable(PWM_CH_LED_GREEN, LED_OFF_LVL);
+		break;
+	}
+}
+
+__override void led_set_color_power(enum ec_led_colors color)
+{
+	if (color == EC_LED_COLOR_WHITE)
+		pwm_enable(PWM_CH_LED_WHITE, LED_ON_LVL);
+	else
+		pwm_enable(PWM_CH_LED_WHITE, LED_OFF_LVL);
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_RED] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		brightness_range[EC_LED_COLOR_GREEN] = 1;
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_POWER_LED) {
+		if (brightness[EC_LED_COLOR_RED] != 0)
+			led_set_color_battery(EC_LED_COLOR_RED);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(EC_LED_COLOR_AMBER);
+		else if (brightness[EC_LED_COLOR_GREEN] != 0)
+			led_set_color_battery(EC_LED_COLOR_GREEN);
+		else
+			led_set_color_battery(LED_OFF);
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_power(EC_LED_COLOR_WHITE);
+		else
+			led_set_color_battery(LED_OFF);
+	} else {
+		return EC_ERROR_INVAL;
+	}
+	return EC_SUCCESS;
+}
diff --git a/board/beetley/usb_pd_policy.c b/board/beetley/usb_pd_policy.c
new file mode 100644
index 0000000000..a7633b73ac
--- /dev/null
+++ b/board/beetley/usb_pd_policy.c
@@ -0,0 +1,71 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery_smart.h"
+#include "charge_manager.h"
+#include "charger.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "driver/charger/isl923x_public.h"
+#include "driver/tcpm/tcpci.h"
+#include "usb_pd.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+int pd_check_vconn_swap(int port)
+{
+	/* Allow VCONN swaps if the AP is on */
+	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
+}
+
+void pd_power_supply_reset(int port)
+{
+	if (port != 0)
+		return;
+
+	/* Disable VBUS */
+	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	if (port != 0)
+		return EC_ERROR_INVAL;
+
+	/* Disable charging. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
+	if (rv)
+		return rv;
+
+	/* Our policy is not to source VBUS when the AP is off. */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	/* Provide Vbus. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
+	if (rv)
+		return rv;
+
+	rv = raa489000_enable_asgate(port, true);
+	if (rv)
+		return rv;
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	return pd_check_vbus_level(port, VBUS_PRESENT);
+}
diff --git a/board/beetley/vif_override.xml b/board/beetley/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/beetley/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/bellis/battery.c b/board/bellis/battery.c
new file mode 100644
index 0000000000..d74876ec27
--- /dev/null
+++ b/board/bellis/battery.c
@@ -0,0 +1,104 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "battery_fuel_gauge.h"
+#include "gpio.h"
+
+const struct board_batt_params board_battery_info[] = {
+	/* LGC L20L3PG2, Gauge IC: RAJ240047A20DNP. */
+	[BATTERY_LGC] = {
+		.fuel_gauge = {
+			.manuf_name = "LGC",
+			.device_name = "L20L3PG2",
+			.ship_mode = {
+				.reg_addr = 0x34,
+				.reg_data = { 0x0000, 0x1000 },
+			},
+			.fet = {
+				.reg_addr = 0x34,
+				.reg_mask = 0x0100,
+				.disconnect_val = 0x0100,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13050,   /* mV */
+			.voltage_normal		= 11400,   /* mV */
+			.voltage_min		= 9000,    /* mV */
+			.precharge_current	= 256,     /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 73,
+		},
+	},
+	/* Sunwoda L20D3PG2, Gauge IC: BQ40Z697A. */
+	[BATTERY_SUNWODA] = {
+		.fuel_gauge = {
+			.manuf_name = "Sunwoda",
+			.device_name = "L20D3PG2",
+			.ship_mode = {
+				.reg_addr = 0x34,
+				.reg_data = { 0x0000, 0x1000 },
+			},
+			.fet = {
+				.reg_addr = 0x34,
+				.reg_mask = 0x0100,
+				.disconnect_val = 0x0100,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13050, /* mV */
+			.voltage_normal		= 11250, /* mV */
+			.voltage_min		= 9000,  /* mV */
+			.precharge_current	= 200,	 /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 60,
+		},
+	},
+
+	/* SIMPLO L20M3PG2, Gauge IC: BQ40Z697A. */
+	[BATTERY_SMP] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP",
+			.device_name = "L20M3PG2",
+			.ship_mode = {
+				.reg_addr = 0x34,
+				.reg_data = { 0x0000, 0x1000 },
+			},
+			.fet = {
+				.reg_addr = 0x34,
+				.reg_mask = 0x0100,
+				.disconnect_val = 0x0100,
+			},
+		},
+		.batt_info = {
+			.voltage_max		= 13050, /* mV */
+			.voltage_normal		= 11250, /* mV */
+			.voltage_min		= 9000,  /* mV */
+			.precharge_current	= 256,   /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 45,
+			.charging_min_c		= 0,
+			.charging_max_c		= 45,
+			.discharging_min_c	= -40,
+			.discharging_max_c	= 73,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_LGC;
+
+enum battery_present battery_hw_present(void)
+{
+	return gpio_get_level(GPIO_EC_BATT_PRES_ODL) ? BP_NO : BP_YES;
+}
diff --git a/board/bellis/board.c b/board/bellis/board.c
new file mode 100644
index 0000000000..9a2054a399
--- /dev/null
+++ b/board/bellis/board.c
@@ -0,0 +1,595 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc.h"
+#include "backlight.h"
+#include "button.h"
+#include "charge_manager.h"
+#include "charge_ramp.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "driver/accel_lis2dw12.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "driver/battery/max17055.h"
+#include "driver/bc12/pi3usb9201.h"
+#include "driver/charger/isl923x.h"
+#include "driver/tcpm/fusb302.h"
+#include "driver/usb_mux/it5205.h"
+#include "ec_commands.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "i2c.h"
+#include "i2c_bitbang.h"
+#include "it8801.h"
+#include "keyboard_backlight.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "panic.h"
+#include "power.h"
+#include "power_button.h"
+#include "registers.h"
+#include "spi.h"
+#include "system.h"
+#include "task.h"
+#include "tcpm/tcpm.h"
+#include "timer.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd_tcpm.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+static void tcpc_alert_event(enum gpio_signal signal)
+{
+	schedule_deferred_pd_interrupt(0 /* port */);
+}
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/******************************************************************************/
+/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
+const struct adc_t adc_channels[] = {
+	[ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(5) },
+	[ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(15) },
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/******************************************************************************/
+/* I2C ports */
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "typec",
+	  .port = 0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "other",
+	  .port = 2,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+const struct i2c_port_t i2c_bitbang_ports[] = {
+	{ .name = "battery",
+	  .port = 3,
+	  .kbps = 100,
+	  .scl = GPIO_I2C4_SCL,
+	  .sda = GPIO_I2C4_SDA,
+	  .drv = &bitbang_drv },
+};
+const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
+
+#define BC12_I2C_ADDR PI3USB9201_I2C_ADDR_3
+
+/* power signal list.  Must match order of enum power_signal. */
+const struct power_signal_info power_signal_list[] = {
+	{ GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" },
+	{ GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" },
+};
+BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/*
+	 * TODO(b/133200075): Tune this once we have the final performance
+	 * out of the driver and the i2c bus.
+	 */
+	.output_settle_us = 35,
+	.debounce_down_us = 5 * MSEC,
+	.debounce_up_us = 40 * MSEC,
+	.scan_period_us = 10 * MSEC,
+	.min_post_scan_delay_us = 10 * MSEC,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
+		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
+	},
+};
+
+struct ioexpander_config_t ioex_config[CONFIG_IO_EXPANDER_PORT_COUNT] = {
+	[0] = {
+		.i2c_host_port = I2C_PORT_KB_DISCRETE,
+		.i2c_addr_flags = IT8801_I2C_ADDR1,
+		.drv = &it8801_ioexpander_drv,
+	},
+};
+
+/******************************************************************************/
+/* SPI devices */
+const struct spi_device_t spi_devices[] = {
+	{ CONFIG_SPI_ACCEL_PORT, 2, GPIO_EC_SENSOR_SPI_NSS },
+};
+const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
+
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	{
+		.i2c_port = I2C_PORT_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+};
+
+/******************************************************************************/
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TCPC0,
+			.addr_flags = FUSB302_I2C_ADDR_FLAGS,
+		},
+		.drv = &fusb302_tcpm_drv,
+	},
+};
+
+static void board_hpd_status(const struct usb_mux *me, mux_state_t mux_state,
+			     bool *ack_required)
+{
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
+	/*
+	 * svdm_dp_attention() did most of the work, we only need to notify
+	 * host here.
+	 */
+	host_set_single_event(EC_HOST_EVENT_USB_MUX);
+}
+
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+				.hpd_update = &board_hpd_status,
+			},
+	},
+};
+
+/* Charger config.  Start i2c address at 1, update during runtime */
+struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = 2,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+};
+
+/* Board version depends on ADCs, so init i2c port after ADC */
+static void charger_config_complete(void)
+{
+	chg_chips[0].i2c_port = board_get_charger_i2c();
+}
+DECLARE_HOOK(HOOK_INIT, charger_config_complete, HOOK_PRIO_INIT_ADC + 1);
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
+		status |= PD_STATUS_TCPC_ALERT_0;
+
+	return status;
+}
+
+static int force_discharge;
+
+int board_set_active_charge_port(int charge_port)
+{
+	CPRINTS("New chg p%d", charge_port);
+
+	/* ignore all request when discharge mode is on */
+	if (force_discharge && charge_port != CHARGE_PORT_NONE)
+		return EC_SUCCESS;
+
+	switch (charge_port) {
+	case CHARGE_PORT_USB_C:
+		/* Don't charge from a source port */
+		if (board_vbus_source_enabled(charge_port))
+			return -1;
+		break;
+	default:
+		/*
+		 * To ensure the fuel gauge (max17055) is always powered
+		 * even when battery is disconnected, keep VBAT rail on but
+		 * set the charging current to minimum.
+		 */
+		charger_set_current(CHARGER_SOLO, 0);
+		break;
+	}
+
+	return EC_SUCCESS;
+}
+
+int board_discharge_on_ac(int enable)
+{
+	int ret, port;
+
+	if (enable) {
+		port = CHARGE_PORT_NONE;
+	} else {
+		/* restore the charge port state */
+		port = charge_manager_get_override();
+		if (port == OVERRIDE_OFF)
+			port = charge_manager_get_active_charge_port();
+	}
+
+	ret = charger_discharge_on_ac(enable);
+	if (ret)
+		return ret;
+
+	force_discharge = enable;
+	return board_set_active_charge_port(port);
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	/* TODO(b:138352732): read IT8801 GPIO EN_USBC_CHARGE_L */
+	return EC_ERROR_UNIMPLEMENTED;
+}
+
+void bc12_interrupt(enum gpio_signal signal)
+{
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+
+#ifndef VARIANT_KUKUI_NO_SENSORS
+static void board_spi_enable(void)
+{
+	/*
+	 * Pin mux spi peripheral away from emmc, since RO might have
+	 * left them there.
+	 */
+	gpio_config_module(MODULE_SPI_FLASH, 0);
+#ifdef CHIP_FAMILY_STM32L4
+	/* Set I/O speed before AF configured */
+	/* EMMC SPI SLAVE: PB13/14/15 */
+	/* SENSORS SPI controller: PB10, PB12, PC2, PC3 */
+	STM32_GPIO_OSPEEDR(GPIO_B) |= 0xFF300000;
+	STM32_GPIO_OSPEEDR(GPIO_C) |= 0x000000F0;
+
+	/* Enable clocks to SPI2 module. */
+	STM32_RCC_APB1ENR1 |= STM32_RCC_PB1_SPI2;
+
+	/* Reset SPI2 to clear state left over from the emmc slave. */
+	STM32_RCC_APB1RSTR1 |= STM32_RCC_PB1_SPI2;
+	STM32_RCC_APB1RSTR1 &= ~STM32_RCC_PB1_SPI2;
+#else
+	/* Enable clocks to SPI2 module. */
+	STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
+
+	/* Reset SPI2 to clear state left over from the emmc slave. */
+	STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2;
+	STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
+#endif
+	/* Reinitialize spi peripheral. */
+	spi_enable(&spi_devices[0], 1);
+
+	/* Pin mux spi peripheral toward the sensor. */
+	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_spi_enable,
+	     MOTION_SENSE_HOOK_PRIO - 1);
+
+static void board_spi_disable(void)
+{
+	/* Set pins to a state calming the sensor down. */
+	gpio_set_flags(GPIO_EC_SENSOR_SPI_CK, GPIO_OUT_LOW);
+	gpio_set_level(GPIO_EC_SENSOR_SPI_CK, 0);
+	gpio_config_module(MODULE_SPI_CONTROLLER, 0);
+
+	/* Disable spi peripheral and clocks. */
+	spi_enable(&spi_devices[0], 0);
+#ifdef CHIP_FAMILY_STM32L4
+	STM32_RCC_APB1ENR1 &= ~STM32_RCC_PB1_SPI2;
+#else
+	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
+#endif
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_spi_disable,
+	     MOTION_SENSE_HOOK_PRIO + 1);
+#endif /* !VARIANT_KUKUI_NO_SENSORS */
+
+static void board_init(void)
+{
+	/* If the reset cause is external, pulse PMIC force reset. */
+	if (system_get_reset_flags() == EC_RESET_FLAG_RESET_PIN) {
+		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 0);
+		msleep(100);
+		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 1);
+	}
+
+	/* Enable TCPC alert interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
+
+#ifndef VARIANT_KUKUI_NO_SENSORS
+	/* Enable interrupts from BMI160 sensor. */
+	gpio_enable_interrupt(GPIO_ACCEL_INT_ODL);
+
+	/* For some reason we have to do this again in case of sysjump */
+	board_spi_enable();
+#endif /* !VARIANT_KUKUI_NO_SENSORS */
+
+	/* Enable interrupt from PMIC. */
+	gpio_enable_interrupt(GPIO_PMIC_EC_RESETB);
+
+	/* Enable BC12 interrupt */
+	gpio_enable_interrupt(GPIO_BC12_EC_INT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+#ifndef VARIANT_KUKUI_NO_SENSORS
+/* Motion sensors */
+/* Mutexes */
+static struct mutex g_lid_mutex;
+static struct mutex g_base_mutex;
+
+/* Rotation matrixes */
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					      { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
+
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, FLOAT_TO_FP(1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
+
+/* sensor private data */
+/* Lid accel private data */
+static struct stprivate_data g_lis2dwl_data;
+/* Base accel private data */
+static struct bmi_drv_data_t g_bmi160_data;
+
+struct motion_sensor_t motion_sensors[] = {
+	[LID_ACCEL] = {
+	 .name = "Lid Accel",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_LIS2DWL,
+	 .type = MOTIONSENSE_TYPE_ACCEL,
+	 .location = MOTIONSENSE_LOC_LID,
+	 .drv = &lis2dw12_drv,
+	 .mutex = &g_lid_mutex,
+	 .drv_data = &g_lis2dwl_data,
+	 .port = I2C_PORT_SENSORS,
+	 .i2c_spi_addr_flags = LIS2DWL_ADDR1_FLAGS,
+	 .rot_standard_ref = &lid_standard_ref,
+	 .default_range = 2, /* g */
+	 .min_frequency = LIS2DW12_ODR_MIN_VAL,
+	 .max_frequency = LIS2DW12_ODR_MAX_VAL,
+	 .config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 12500 | ROUND_UP_FLAG,
+		},
+		/* Sensor on for lid angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	 },
+	},
+	/*
+	 * Note: bmi160: supports accelerometer and gyro sensor
+	 * Requirement: accelerometer sensor must init before gyro sensor
+	 * DO NOT change the order of the following table.
+	 */
+	[BASE_ACCEL] = {
+	 .name = "Accel",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_BMI160,
+	 .type = MOTIONSENSE_TYPE_ACCEL,
+	 .location = MOTIONSENSE_LOC_BASE,
+	 .drv = &bmi160_drv,
+	 .mutex = &g_base_mutex,
+	 .drv_data = &g_bmi160_data,
+	 .port = CONFIG_SPI_ACCEL_PORT,
+	 .i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
+	 .rot_standard_ref = &base_standard_ref,
+	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
+	 .min_frequency = BMI_ACCEL_MIN_FREQ,
+	 .max_frequency = BMI_ACCEL_MAX_FREQ,
+	 .config = {
+		 /* EC use accel for angle detection */
+		 [SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		 },
+		 /* Sensor on for angle detection */
+		 [SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		 },
+	 },
+	},
+	[BASE_GYRO] = {
+	 .name = "Gyro",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_BMI160,
+	 .type = MOTIONSENSE_TYPE_GYRO,
+	 .location = MOTIONSENSE_LOC_BASE,
+	 .drv = &bmi160_drv,
+	 .mutex = &g_base_mutex,
+	 .drv_data = &g_bmi160_data,
+	 .port = CONFIG_SPI_ACCEL_PORT,
+	 .i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
+	 .default_range = 1000, /* dps */
+	 .rot_standard_ref = &base_standard_ref,
+	 .min_frequency = BMI_GYRO_MIN_FREQ,
+	 .max_frequency = BMI_GYRO_MAX_FREQ,
+	},
+};
+const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+const struct it8801_pwm_t it8801_pwm_channels[] = {
+	[IT8801_PWM_CH_KBLIGHT] = { .index = 4 },
+};
+
+void board_kblight_init(void)
+{
+	kblight_register(&kblight_it8801);
+}
+
+bool board_has_kb_backlight(void)
+{
+	/* Default enable keyboard backlight */
+	return true;
+}
+#endif /* !VARIANT_KUKUI_NO_SENSORS */
+
+/* Battery functions */
+#define SB_SMARTCHARGE 0x26
+/* Quick charge enable bit */
+#define SMART_QUICK_CHARGE 0x02
+/* Quick charge support bit */
+#define MODE_QUICK_CHARGE_SUPPORT 0x01
+
+static void sb_quick_charge_mode(int enable)
+{
+	int val, rv;
+
+	rv = sb_read(SB_SMARTCHARGE, &val);
+	if (rv || !(val & MODE_QUICK_CHARGE_SUPPORT))
+		return;
+
+	if (enable)
+		val |= SMART_QUICK_CHARGE;
+	else
+		val &= ~SMART_QUICK_CHARGE;
+
+	sb_write(SB_SMARTCHARGE, val);
+}
+
+/* Called on AP S0iX -> S0 transition */
+static void board_chipset_resume(void)
+{
+#ifndef VARIANT_KUKUI_NO_SENSORS
+	if (board_has_kb_backlight())
+		ioex_set_level(IOEX_KB_BL_EN, 1);
+#endif
+
+	/* Normal charge mode */
+	sb_quick_charge_mode(0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_INIT, board_chipset_resume, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S0 -> S0iX transition */
+static void board_chipset_suspend(void)
+{
+#ifndef VARIANT_KUKUI_NO_SENSORS
+	if (board_has_kb_backlight())
+		ioex_set_level(IOEX_KB_BL_EN, 0);
+#endif
+
+	/* Quick charge mode */
+	sb_quick_charge_mode(1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S5 -> S3 transition */
+static void board_chipset_startup(void)
+{
+	gpio_set_level(GPIO_EN_USBA_5V, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S3 -> S5 transition */
+static void board_chipset_shutdown(void)
+{
+	gpio_set_level(GPIO_EN_USBA_5V, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
+
+int board_get_charger_i2c(void)
+{
+	/* TODO(b:138415463): confirm the bus allocation for future builds */
+	return I2C_PORT_CHARGER;
+}
+
+int board_get_battery_i2c(void)
+{
+	return I2C_PORT_BATTERY;
+}
+
+#ifdef SECTION_IS_RW
+static int it8801_get_target_channel(enum pwm_channel *channel, int type,
+				     int index)
+{
+	switch (type) {
+	case EC_PWM_TYPE_GENERIC:
+		*channel = index;
+		break;
+	default:
+		return -1;
+	}
+
+	return *channel >= 1;
+}
+
+static enum ec_status
+host_command_pwm_set_duty(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_pwm_set_duty *p = args->params;
+	enum pwm_channel channel;
+	uint16_t duty;
+
+	if (it8801_get_target_channel(&channel, p->pwm_type, p->index))
+		return EC_RES_INVALID_PARAM;
+
+	duty = (uint32_t)p->duty * 255 / 65535;
+	it8801_pwm_set_raw_duty(channel, duty);
+	it8801_pwm_enable(channel, p->duty > 0);
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_DUTY, host_command_pwm_set_duty,
+		     EC_VER_MASK(0));
+
+static enum ec_status
+host_command_pwm_get_duty(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_pwm_get_duty *p = args->params;
+	struct ec_response_pwm_get_duty *r = args->response;
+
+	enum pwm_channel channel;
+
+	if (it8801_get_target_channel(&channel, p->pwm_type, p->index))
+		return EC_RES_INVALID_PARAM;
+
+	r->duty = (uint32_t)it8801_pwm_get_raw_duty(channel) * 65535 / 255;
+	args->response_size = sizeof(*r);
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_DUTY, host_command_pwm_get_duty,
+		     EC_VER_MASK(0));
+#endif
diff --git a/board/bellis/board.h b/board/bellis/board.h
new file mode 100644
index 0000000000..7720b5a391
--- /dev/null
+++ b/board/bellis/board.h
@@ -0,0 +1,190 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Configuration for Bellis */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#define VARIANT_KUKUI_JACUZZI
+#define VARIANT_KUKUI_BATTERY_SMART
+#define VARIANT_KUKUI_CHARGER_ISL9238
+#define VARIANT_KUKUI_EC_STM32L431
+
+#ifndef SECTION_IS_RW
+#define VARIANT_KUKUI_NO_SENSORS
+#endif /* SECTION_IS_RW */
+
+#include "baseboard.h"
+
+#undef CONFIG_CHIPSET_POWER_SEQ_VERSION
+#define CONFIG_CHIPSET_POWER_SEQ_VERSION 1
+#undef CONFIG_SYSTEM_UNLOCKED
+
+/* PLL configuration. Freq = STM32_HSE_CLOCK or HSI (16MHz) * n/m/r */
+#undef STM32_PLLM
+#undef STM32_PLLN
+#undef STM32_PLLR
+#define STM32_PLLM 1
+#ifdef STM32_HSE_CLOCK
+#define STM32_PLLN 12
+#else
+#define STM32_PLLN 10
+#endif
+#define STM32_PLLR 2
+
+#define STM32_USE_PLL
+
+#define CONFIG_BATTERY_HW_PRESENT_CUSTOM
+
+#define CONFIG_CHARGER_PSYS
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 5
+
+#define CONFIG_CHARGER_RUNTIME_CONFIG
+
+#define CONFIG_BC12_DETECT_PI3USB9201
+
+#define CONFIG_EXTPOWER_GPIO
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
+#define CONFIG_EXTPOWER_DEBOUNCE_MS 200
+
+#define CONFIG_I2C_BITBANG
+#undef I2C_BITBANG_PORT_COUNT
+#define I2C_BITBANG_PORT_COUNT 1
+#undef CONFIG_I2C_NACK_RETRY_COUNT
+#define CONFIG_I2C_NACK_RETRY_COUNT 10
+#define CONFIG_SMBUS_PEC
+
+#define CONFIG_USB_PD_TCPM_FUSB302
+#define CONFIG_USB_PD_DISCHARGE_GPIO
+#define CONFIG_USB_PD_TCPC_LOW_POWER
+
+#define CONFIG_USB_MUX_IT5205
+
+#define CONFIG_LED_ONOFF_STATES
+#define CONFIG_LED_POWER_LED
+
+#undef CONFIG_WATCHDOG_PERIOD_MS
+#define CONFIG_WATCHDOG_PERIOD_MS 4000
+
+/* Motion Sensors */
+#ifndef VARIANT_KUKUI_NO_SENSORS
+#define CONFIG_ACCEL_LIS2DWL /* Lid accel */
+#define CONFIG_ACCELGYRO_BMI160 /* Base accel */
+#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+#define CONFIG_ALS
+#define CONFIG_CMD_ACCEL_INFO
+
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_UPDATE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+
+#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
+
+#ifdef SECTION_IS_RW
+#define CONFIG_IO_EXPANDER_IT8801_PWM
+#define CONFIG_KEYBOARD_BACKLIGHT
+#endif
+
+#endif /* VARIANT_KUKUI_NO_SENSORS */
+
+/* I2C ports */
+#define I2C_PORT_BC12 0
+#define I2C_PORT_TCPC0 0
+#define I2C_PORT_USB_MUX 0
+#define I2C_PORT_CHARGER 2
+#define I2C_PORT_SENSORS 2
+#define I2C_PORT_KB_DISCRETE 2
+#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
+#define I2C_PORT_BATTERY 3
+#define I2C_PORT_TCPC0 0
+
+#undef I2C_CONTROLLER_COUNT
+#undef I2C_PORT_COUNT
+#define I2C_CONTROLLER_COUNT 3
+#define I2C_PORT_COUNT 3
+
+/* IT8801 I2C address */
+#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1
+
+/* Enable Accel over SPI */
+#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */
+
+#define CONFIG_KEYBOARD_PROTOCOL_MKBP
+#define CONFIG_MKBP_EVENT
+#define CONFIG_MKBP_USE_GPIO
+/* Define the MKBP events which are allowed to wakeup AP in S3. */
+#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK            \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+#undef CONFIG_GMR_TABLET_MODE
+#undef GPIO_TABLET_MODE_L
+#undef CONFIG_TABLET_MODE
+#undef CONFIG_TABLET_MODE_SWITCH
+
+#ifndef __ASSEMBLER__
+
+enum adc_channel {
+	/* Real ADC channels begin here */
+	ADC_BOARD_ID = 0,
+	ADC_EC_SKU_ID,
+	ADC_CH_COUNT
+};
+
+/* power signal definitions */
+enum power_signal {
+	AP_IN_S3_L,
+	PMIC_PWR_GOOD,
+
+	/* Number of signals */
+	POWER_SIGNAL_COUNT,
+};
+
+/* Motion sensors */
+enum sensor_id {
+	LID_ACCEL = 0,
+	BASE_ACCEL,
+	BASE_GYRO,
+	SENSOR_COUNT,
+};
+
+enum charge_port {
+	CHARGE_PORT_USB_C,
+};
+
+enum battery_type {
+	BATTERY_LGC,
+	BATTERY_SUNWODA,
+	BATTERY_SMP,
+	BATTERY_TYPE_COUNT,
+};
+
+enum pwm_channel {
+	IT8801_PWM_CH_KBLIGHT = 0,
+};
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+#ifdef SECTION_IS_RO
+/* Interrupt handler for emmc task */
+void emmc_cmd_interrupt(enum gpio_signal signal);
+#endif
+
+void bc12_interrupt(enum gpio_signal signal);
+void board_reset_pd_mcu(void);
+int board_get_version(void);
+
+/* returns the i2c port number of charger/battery */
+int board_get_charger_i2c(void);
+int board_get_battery_i2c(void);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/bellis/build.mk b/board/bellis/build.mk
new file mode 100644
index 0000000000..604790d66c
--- /dev/null
+++ b/board/bellis/build.mk
@@ -0,0 +1,15 @@
+# -*- makefile -*-
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+#
+# STmicro STM32L431RCI
+CHIP:=stm32
+CHIP_FAMILY:=stm32l4
+CHIP_VARIANT:=stm32l431x
+BASEBOARD:=kukui
+
+board-y=battery.o board.o led.o
diff --git a/board/bellis/ec.tasklist b/board/bellis/ec.tasklist
new file mode 100644
index 0000000000..2d69c1b113
--- /dev/null
+++ b/board/bellis/ec.tasklist
@@ -0,0 +1,20 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, TRENTA_TASK_STACK_SIZE) \
+	TASK_ALWAYS_RW(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 1024) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, 1280) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, 1024) \
+	TASK_ALWAYS_RO(EMMC, emmc_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/bellis/gpio.inc b/board/bellis/gpio.inc
new file mode 100644
index 0000000000..a80ef27c97
--- /dev/null
+++ b/board/bellis/gpio.inc
@@ -0,0 +1,120 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first.
+ */
+
+/* Interrupts */
+GPIO_INT(USB_C0_PD_INT_ODL, PIN(B, 1), GPIO_INT_FALLING | GPIO_PULL_UP,
+         tcpc_alert_event)
+GPIO_INT(POWER_BUTTON_L,    PIN(A, 11),  GPIO_INT_BOTH | GPIO_PULL_UP,
+         power_button_interrupt) /* EC_PWR_BTN_ODL */
+GPIO_INT(AP_IN_SLEEP_L,     PIN(C, 12), GPIO_INT_BOTH | GPIO_PULL_DOWN,
+         power_signal_interrupt)
+GPIO_INT(PMIC_EC_RESETB,    PIN(B, 7),  GPIO_INT_BOTH | GPIO_PULL_DOWN,
+         power_signal_interrupt)
+GPIO_INT(WARM_RESET_REQ,    PIN(A, 3),  GPIO_INT_RISING | GPIO_PULL_DOWN,
+         chipset_reset_request_interrupt)
+GPIO_INT_RW(ACCEL_INT_ODL,  PIN(A, 4),  GPIO_INT_FALLING | GPIO_SEL_1P8V | GPIO_PULL_UP,
+         bmi160_interrupt)
+GPIO_INT_RO(EMMC_CMD,       PIN(B, 15), GPIO_INT_FALLING,
+         emmc_cmd_interrupt)
+GPIO_INT(SPI1_NSS,          PIN(A, 15), GPIO_INT_BOTH | GPIO_PULL_UP,
+         spi_event) /* SPI_AP_EC_CS_L */
+GPIO_INT(LID_OPEN,          PIN(C, 5),  GPIO_INT_BOTH,
+         lid_interrupt)
+GPIO_INT(AC_PRESENT,        PIN(A, 6),  GPIO_INT_BOTH,
+         extpower_interrupt) /* ACOK_OD */
+GPIO_INT(BC12_EC_INT_ODL,   PIN(C, 9),  GPIO_INT_FALLING,
+         bc12_interrupt)
+GPIO_INT(IT8801_SMB_INT,    PIN(A, 8),  GPIO_INT_FALLING | GPIO_PULL_UP,
+         io_expander_it8801_interrupt) /* KB_INT_ODL */
+GPIO_INT(AP_EC_WATCHDOG_L,  PIN(D, 2),  GPIO_INT_FALLING,
+         chipset_watchdog_interrupt)
+
+/* Unimplemented interrupts */
+GPIO(ALS_RGB_INT_ODL,      PIN(C, 10), GPIO_INPUT)
+GPIO(TABLET_MODE_L,        PIN(B, 11), GPIO_INPUT)
+
+/* Reset pins */
+GPIO(AP_SYS_RST_L,         PIN(C, 11), GPIO_OUT_LOW)
+GPIO(PMIC_WATCHDOG_L,      PIN(A, 2),  GPIO_OUT_LOW)
+GPIO(PMIC_EN_ODL,          PIN(H, 0),  GPIO_ODR_HIGH)
+
+/*
+ * I2C pins should be configured as inputs until I2C module is
+ * initialized. This will avoid driving the lines unintentionally.
+ */
+GPIO(I2C1_SCL,             PIN(B, 8),  GPIO_INPUT)
+GPIO(I2C1_SDA,             PIN(B, 9),  GPIO_INPUT)
+GPIO(I2C3_SCL,             PIN(C, 0),  GPIO_INPUT)
+GPIO(I2C3_SDA,             PIN(C, 1),  GPIO_INPUT)
+GPIO(I2C4_SCL,             PIN(A, 5),  GPIO_ODR_HIGH)
+GPIO(I2C4_SDA,             PIN(C, 4),  GPIO_ODR_HIGH)
+
+/* Analog pins */
+GPIO(BOARD_ID,             PIN(A, 0),  GPIO_ANALOG)
+GPIO(EC_SKU_ID,            PIN(B, 0),  GPIO_ANALOG)
+
+/* Other input pins */
+GPIO(WP_L,                 PIN(C, 8),  GPIO_INPUT) /* EC_FLASH_WP_ODL */
+GPIO(BOOT0,                PIN(H, 3),  GPIO_INPUT)
+GPIO(CCD_MODE_ODL,         PIN(A, 1),  GPIO_INPUT)
+
+/* Other output pins */
+GPIO(EC_BATT_PRES_ODL,     PIN(A, 7),  GPIO_INPUT)
+GPIO(EC_BL_EN_OD,          PIN(A, 13), GPIO_ODR_HIGH)
+GPIO(EN_USBA_5V,           PIN(C, 14), GPIO_OUT_LOW)
+GPIO(EC_SENSOR_SPI_MISO,   PIN(C, 2),  GPIO_INPUT)
+GPIO(EC_SENSOR_SPI_MOSI,   PIN(C, 3),  GPIO_OUT_LOW)
+GPIO(EC_SENSOR_SPI_NSS,    PIN(B, 12), GPIO_OUT_HIGH)
+GPIO(EC_SENSOR_SPI_CK,     PIN(B, 10), GPIO_OUT_LOW)
+GPIO(ENTERING_RW,          PIN(C, 6),  GPIO_ODR_HIGH) /* EC_ENTERING_RW_ODL */
+GPIO(EC_INT_L,             PIN(C, 7),  GPIO_ODR_HIGH) /* EC_AP_INT_ODL */
+GPIO(EC_BOARD_ID_EN_L,     PIN(C, 15), GPIO_ODR_HIGH) /* EC_BOARD_ID_EN_ODL */
+GPIO(USB_C0_HPD_OD,        PIN(H, 1),  GPIO_ODR_LOW)
+GPIO(BOOTBLOCK_EN_L,       PIN(A, 12), GPIO_ODR_HIGH)
+GPIO(EN_PP1800_S5_L,       PIN(A, 14), GPIO_OUT_LOW)
+GPIO(USB_C0_DISCHARGE,     PIN(B, 6),  GPIO_OUT_LOW)
+
+IOEX(PWR_LED_WHITE_L,      EXPIN(0, 1, 4), GPIO_OUT_HIGH)
+IOEX(BAT_LED_GREEN_FULL_L, EXPIN(0, 1, 3), GPIO_OUT_HIGH)
+IOEX(BAT_LED_RED_L,        EXPIN(0, 1, 2), GPIO_OUT_HIGH)
+IOEX(KB_BL_EN,             EXPIN(0, 0, 7), GPIO_OUT_LOW)
+
+/*
+ * TODO(b:138352732): On IT88801 expander, To be readded once IT8801 driver and
+ * gpio expander framework has landed.
+ */
+UNIMPLEMENTED(EN_PP5000_USBC)
+UNIMPLEMENTED(PMIC_FORCE_RESET_ODL)
+UNIMPLEMENTED(EN_USBC_CHARGE_L)
+
+/* USART1: PA9/PA10 */
+ALTERNATE(PIN_MASK(A, 0x0600), 7, MODULE_UART,       0)
+/* I2C MASTER: PB8/9 */
+ALTERNATE(PIN_MASK(B, 0x0300), 4, MODULE_I2C,        GPIO_ODR_HIGH )
+/* I2C MASTER: PC0/C1 */
+ALTERNATE(PIN_MASK(C, 0x0003), 4, MODULE_I2C,        GPIO_ODR_HIGH )
+
+
+/* SPI1 */
+/* SPI SLAVE: PB3/4/5 */
+ALTERNATE(PIN_MASK(B, 0x0038), 5, MODULE_SPI,        0)
+/* SPI SLAVE CS: PA15 */
+ALTERNATE(PIN_MASK(A, 0x8000), 5, MODULE_SPI,        0)
+
+/* SPI2 */
+/* Shared between slave for emmc and master for bmi160 */
+/* They're mutually exclusive with gpio_config_module. */
+/* EMMC SPI SLAVE: PB13/14/15 */
+ALTERNATE(PIN_MASK(B, 0xE000), 5, MODULE_SPI_FLASH,  0)
+/* SENSORS SPI MASTER: PB10, PB12, PC2, PC3 */
+ALTERNATE(PIN_MASK(B, 0x0400), 5, MODULE_SPI_CONTROLLER, 0)
+ALTERNATE(PIN_MASK(C, 0x000C), 5, MODULE_SPI_CONTROLLER, 0)
diff --git a/board/bellis/led.c b/board/bellis/led.c
new file mode 100644
index 0000000000..420c491308
--- /dev/null
+++ b/board/bellis/led.c
@@ -0,0 +1,120 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power and battery LED control for Bellis
+ */
+#include "common.h"
+#include "driver/ioexpander/it8801.h"
+#include "ec_commands.h"
+#include "ioexpander.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+
+#define LED_ON_LVL 0
+#define LED_OFF_LVL 1
+
+__override const int led_charge_lvl_1 = 5;
+__override const int led_charge_lvl_2 = 97;
+
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
+
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    1 * LED_ONE_SEC },
+						  { LED_OFF,
+						    3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_GREEN:
+		ioex_set_level(IOEX_BAT_LED_GREEN_FULL_L, LED_ON_LVL);
+		ioex_set_level(IOEX_BAT_LED_RED_L, LED_OFF_LVL);
+		break;
+	case EC_LED_COLOR_AMBER:
+		ioex_set_level(IOEX_BAT_LED_GREEN_FULL_L, LED_ON_LVL);
+		ioex_set_level(IOEX_BAT_LED_RED_L, LED_ON_LVL);
+		break;
+	case EC_LED_COLOR_RED:
+		ioex_set_level(IOEX_BAT_LED_GREEN_FULL_L, LED_OFF_LVL);
+		ioex_set_level(IOEX_BAT_LED_RED_L, LED_ON_LVL);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		ioex_set_level(IOEX_BAT_LED_GREEN_FULL_L, LED_OFF_LVL);
+		ioex_set_level(IOEX_BAT_LED_RED_L, LED_OFF_LVL);
+		break;
+	}
+}
+
+__override void led_set_color_power(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_WHITE:
+		ioex_set_level(IOEX_PWR_LED_WHITE_L, LED_ON_LVL);
+		break;
+	default:
+		ioex_set_level(IOEX_PWR_LED_WHITE_L, LED_OFF_LVL);
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_GREEN] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		brightness_range[EC_LED_COLOR_RED] = 1;
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		if (brightness[EC_LED_COLOR_GREEN] != 0)
+			led_set_color_battery(EC_LED_COLOR_GREEN);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(EC_LED_COLOR_AMBER);
+		else if (brightness[EC_LED_COLOR_RED] != 0)
+			led_set_color_battery(EC_LED_COLOR_RED);
+		else
+			led_set_color_battery(LED_OFF);
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_power(EC_LED_COLOR_WHITE);
+		else
+			led_set_color_power(LED_OFF);
+	} else {
+		return EC_ERROR_INVAL;
+	}
+	return EC_SUCCESS;
+}
diff --git a/board/bellis/vif_override.xml b/board/bellis/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/bellis/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/berknip/battery.c b/board/berknip/battery.c
index 526375c0db..d024e710c3 100644
--- a/board/berknip/battery.c
+++ b/board/berknip/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/berknip/board.c b/board/berknip/board.c
index 9e7be926b7..ee4158e671 100644
--- a/board/berknip/board.c
+++ b/board/berknip/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,14 +6,13 @@
 /* Berknip board configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "button.h"
-#include "charger.h"
 #include "cbi_ec_fw_config.h"
+#include "charger.h"
 #include "cros_board_info.h"
-#include "driver/accelgyro_bmi_common.h"
 #include "driver/accel_kionix.h"
 #include "driver/accel_kx022.h"
+#include "driver/accelgyro_bmi_common.h"
 #include "driver/retimer/pi3hdx1204.h"
 #include "driver/retimer/tusb544.h"
 #include "driver/temp_sensor/sb_tsi.h"
@@ -33,14 +32,17 @@
 #include "system.h"
 #include "task.h"
 #include "temp_sensor.h"
-#include "thermistor.h"
+#include "temp_sensor/thermistor.h"
 #include "usb_charge.h"
 #include "usb_mux.h"
 
+static void hdmi_hpd_interrupt(enum gpio_signal signal);
+
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 const struct pwm_t pwm_channels[] = {
 	[PWM_CH_KBLIGHT] = {
@@ -78,6 +80,11 @@ const struct pi3hdx1204_tuning pi3hdx1204_tuning = {
 	.de_offset = PI3HDX1204_DE_DB_MINUS5,
 };
 
+static int check_hdmi_hpd_status(void)
+{
+	return gpio_get_level(GPIO_DP1_HPD_EC_IN);
+}
+
 /*****************************************************************************
  * Board suspend / resume
  */
@@ -89,9 +96,8 @@ static void board_chipset_resume(void)
 	if (ec_config_has_hdmi_retimer_pi3hdx1204()) {
 		ioex_set_level(IOEX_HDMI_POWER_EN_DB, 1);
 		msleep(PI3HDX1204_POWER_ON_DELAY_MS);
-		pi3hdx1204_enable(I2C_PORT_TCPC1,
-				  PI3HDX1204_I2C_ADDR_FLAGS,
-				  1);
+		pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS,
+				  check_hdmi_hpd_status());
 	}
 }
 DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
@@ -99,9 +105,7 @@ DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
 static void board_chipset_suspend(void)
 {
 	if (ec_config_has_hdmi_retimer_pi3hdx1204()) {
-		pi3hdx1204_enable(I2C_PORT_TCPC1,
-				  PI3HDX1204_I2C_ADDR_FLAGS,
-				  0);
+		pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS, 0);
 		ioex_set_level(IOEX_HDMI_POWER_EN_DB, 0);
 	}
 
@@ -114,8 +118,12 @@ DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
  * chip and it need a board specific driver.
  * Overall, it will use chained mux framework.
  */
-static int pi3usb221_set_mux(const struct usb_mux *me, mux_state_t mux_state)
+static int pi3usb221_set_mux(const struct usb_mux *me, mux_state_t mux_state,
+			     bool *ack_required)
 {
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
 	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
 		ioex_set_level(IOEX_USB_C0_SBU_FLIP, 0);
 	else
@@ -135,14 +143,21 @@ const struct usb_mux_driver usbc0_sbu_mux_driver = {
  * Since PI3USB221 is not a i2c device, .i2c_port and
  * .i2c_addr_flags are not required here.
  */
-const struct usb_mux usbc0_sbu_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &usbc0_sbu_mux_driver,
+const struct usb_mux_chain usbc0_sbu_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &usbc0_sbu_mux_driver,
+		},
 };
 
 /*****************************************************************************
  * USB-C MUX/Retimer dynamic configuration
  */
+
+/* Place holder for second mux in USBC1 chain */
+struct usb_mux_chain usbc1_mux1;
+
 static void setup_mux(void)
 {
 	if (ec_config_has_usbc1_retimer_tusb544()) {
@@ -153,11 +168,9 @@ static void setup_mux(void)
 		 * Replace usb_muxes[USBC_PORT_C1] with the AMD FP5
 		 * table entry.
 		 */
-		memcpy(&usb_muxes[USBC_PORT_C1],
-		       &usbc1_amd_fp5_usb_mux,
-		       sizeof(struct usb_mux));
+		usb_muxes[USBC_PORT_C1].mux = &usbc1_amd_fp5_usb_mux;
 		/* Set the TUSB544 as the secondary MUX */
-		usb_muxes[USBC_PORT_C1].next_mux = &usbc1_tusb544;
+		usbc1_mux1.mux = &usbc1_tusb544;
 	} else if (ec_config_has_usbc1_retimer_ps8743()) {
 		ccprints("C1 PS8743 detected");
 		/*
@@ -166,34 +179,87 @@ static void setup_mux(void)
 		 * Replace usb_muxes[USBC_PORT_C1] with the PS8743
 		 * table entry.
 		 */
-		memcpy(&usb_muxes[USBC_PORT_C1],
-		       &usbc1_ps8743,
-		       sizeof(struct usb_mux));
+		usb_muxes[USBC_PORT_C1].mux = &usbc1_ps8743;
 		/* Set the AMD FP5 as the secondary MUX */
-		usb_muxes[USBC_PORT_C1].next_mux = &usbc1_amd_fp5_usb_mux;
+		usbc1_mux1.mux = &usbc1_amd_fp5_usb_mux;
 		/* Don't have the AMD FP5 flip */
 		usbc1_amd_fp5_usb_mux.flags = USB_MUX_FLAG_SET_WITHOUT_FLIP;
 	}
 }
 
-struct usb_mux usb_muxes[] = {
+struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.i2c_port = I2C_PORT_USB_AP_MUX,
-		.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
-		.driver = &amd_fp5_usb_mux_driver,
-		.next_mux = &usbc0_sbu_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.i2c_port = I2C_PORT_USB_AP_MUX,
+			.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
+			.driver = &amd_fp5_usb_mux_driver,
+		},
+		.next = &usbc0_sbu_mux,
 	},
 	[USBC_PORT_C1] = {
 		/* Filled in dynamically at startup */
+		.next = &usbc1_mux1,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
 
 static int board_tusb544_mux_set(const struct usb_mux *me,
-				mux_state_t mux_state)
+				 mux_state_t mux_state)
 {
+	int rv = EC_SUCCESS;
+
+	if (mux_state & USB_PD_MUX_USB_ENABLED) {
+		rv = tusb544_i2c_field_update8(
+			me, TUSB544_REG_USB3_1_1, TUSB544_EQ_RX_MASK,
+			TUSB544_EQ_RX_DFP_04_UFP_MINUS15);
+		if (rv)
+			return rv;
+
+		rv = tusb544_i2c_field_update8(
+			me, TUSB544_REG_USB3_1_1, TUSB544_EQ_TX_MASK,
+			TUSB544_EQ_TX_DFP_MINUS14_UFP_MINUS33);
+		if (rv)
+			return rv;
+
+		rv = tusb544_i2c_field_update8(
+			me, TUSB544_REG_USB3_1_2, TUSB544_EQ_RX_MASK,
+			TUSB544_EQ_RX_DFP_04_UFP_MINUS15);
+		if (rv)
+			return rv;
+
+		rv = tusb544_i2c_field_update8(
+			me, TUSB544_REG_USB3_1_2, TUSB544_EQ_TX_MASK,
+			TUSB544_EQ_TX_DFP_MINUS14_UFP_MINUS33);
+		if (rv)
+			return rv;
+	}
+
 	if (mux_state & USB_PD_MUX_DP_ENABLED) {
+		rv = tusb544_i2c_field_update8(me, TUSB544_REG_DISPLAYPORT_1,
+					       TUSB544_EQ_RX_MASK,
+					       TUSB544_EQ_RX_DFP_61_UFP_43);
+		if (rv)
+			return rv;
+
+		rv = tusb544_i2c_field_update8(me, TUSB544_REG_DISPLAYPORT_1,
+					       TUSB544_EQ_TX_MASK,
+					       TUSB544_EQ_TX_DFP_61_UFP_43);
+		if (rv)
+			return rv;
+
+		rv = tusb544_i2c_field_update8(me, TUSB544_REG_DISPLAYPORT_2,
+					       TUSB544_EQ_RX_MASK,
+					       TUSB544_EQ_RX_DFP_61_UFP_43);
+		if (rv)
+			return rv;
+
+		rv = tusb544_i2c_field_update8(me, TUSB544_REG_DISPLAYPORT_2,
+					       TUSB544_EQ_TX_MASK,
+					       TUSB544_EQ_TX_DFP_61_UFP_43);
+		if (rv)
+			return rv;
+
 		/* Enable IN_HPD on the DB */
 		gpio_or_ioex_set_level(board_usbc1_retimer_inhpd, 1);
 	} else {
@@ -203,19 +269,6 @@ static int board_tusb544_mux_set(const struct usb_mux *me,
 	return EC_SUCCESS;
 }
 
-static int board_ps8743_mux_set(const struct usb_mux *me,
-				mux_state_t mux_state)
-{
-	if (mux_state & USB_PD_MUX_DP_ENABLED)
-		/* Enable IN_HPD on the DB */
-		gpio_or_ioex_set_level(board_usbc1_retimer_inhpd, 1);
-	else
-		/* Disable IN_HPD on the DB */
-		gpio_or_ioex_set_level(board_usbc1_retimer_inhpd, 0);
-
-	return EC_SUCCESS;
-}
-
 const struct usb_mux usbc1_tusb544 = {
 	.usb_port = USBC_PORT_C1,
 	.i2c_port = I2C_PORT_TCPC1,
@@ -228,7 +281,6 @@ const struct usb_mux usbc1_ps8743 = {
 	.i2c_port = I2C_PORT_TCPC1,
 	.i2c_addr_flags = PS8743_I2C_ADDR1_FLAG,
 	.driver = &ps8743_usb_mux_driver,
-	.board_set = &board_ps8743_mux_set,
 };
 
 /*****************************************************************************
@@ -265,6 +317,10 @@ static void board_remap_gpio(void)
 		 */
 		gpio_set_flags(GPIO_USB_C1_HPD_IN_DB_V1, GPIO_OUT_LOW);
 		board_usbc1_retimer_inhpd = GPIO_USB_C1_HPD_IN_DB_V1;
+
+		if (ec_config_has_hdmi_retimer_pi3hdx1204())
+			gpio_enable_interrupt(GPIO_DP1_HPD_EC_IN);
+
 	} else
 		board_usbc1_retimer_inhpd = IOEX_USB_C1_HPD_IN_DB;
 }
@@ -278,6 +334,25 @@ static void setup_fw_config(void)
 /* Use HOOK_PRIO_INIT_I2C + 2 to be after ioex_init(). */
 DECLARE_HOOK(HOOK_INIT, setup_fw_config, HOOK_PRIO_INIT_I2C + 2);
 
+static void hdmi_hpd_handler(void)
+{
+	/* Pass HPD through DB OPT1 HDMI connector to AP's DP1 */
+	int hpd = check_hdmi_hpd_status();
+
+	gpio_set_level(GPIO_EC_DP1_HPD, hpd);
+	ccprints("HDMI HPD %d", hpd);
+	pi3hdx1204_enable(
+		I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS,
+		chipset_in_or_transitioning_to_state(CHIPSET_STATE_ON) && hpd);
+}
+DECLARE_DEFERRED(hdmi_hpd_handler);
+
+static void hdmi_hpd_interrupt(enum gpio_signal signal)
+{
+	/* Debounce for 2 msec */
+	hook_call_deferred(&hdmi_hpd_handler_data, (2 * MSEC));
+}
+
 /*****************************************************************************
  * Fan
  */
@@ -285,7 +360,7 @@ DECLARE_HOOK(HOOK_INIT, setup_fw_config, HOOK_PRIO_INIT_I2C + 2);
 /* Physical fans. These are logically separate from pwm_channels. */
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = -1,
 };
@@ -318,6 +393,11 @@ int board_get_temp(int idx, int *temp_k)
 		if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
 			return EC_ERROR_NOT_POWERED;
 
+		/* adc power not ready when transition to S5 */
+		if (chipset_in_or_transitioning_to_state(
+			    CHIPSET_STATE_SOFT_OFF))
+			return EC_ERROR_NOT_POWERED;
+
 		channel = ADC_TEMP_SENSOR_SOC;
 		break;
 	case TEMP_SENSOR_5V_REGULATOR:
@@ -325,6 +405,11 @@ int board_get_temp(int idx, int *temp_k)
 		if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
 			return EC_ERROR_NOT_POWERED;
 
+		/* adc power not ready when transition to S5 */
+		if (chipset_in_or_transitioning_to_state(
+			    CHIPSET_STATE_SOFT_OFF))
+			return EC_ERROR_NOT_POWERED;
+
 		channel = ADC_TEMP_SENSOR_5V_REGULATOR;
 		break;
 	default:
@@ -393,53 +478,74 @@ const struct temp_sensor_t temp_sensors[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
-const static struct ec_thermal_config thermal_thermistor_soc = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(73),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(39),
-	.temp_fan_max = C_TO_K(60),
-};
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_THERMISTOR_SOC   \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(62), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(66), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(57), \
+		}, \
+		.temp_fan_off = C_TO_K(39), \
+		.temp_fan_max = C_TO_K(60), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_thermistor_soc =
+	THERMAL_THERMISTOR_SOC;
 
-const static struct ec_thermal_config thermal_thermistor_charger = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(99),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(99),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(98),
-	},
-	.temp_fan_off = C_TO_K(98),
-	.temp_fan_max = C_TO_K(99),
-};
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_THERMISTOR_CHARGER \
+	{                          \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(99), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(99), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(98), \
+		}, \
+		.temp_fan_off = C_TO_K(98), \
+		.temp_fan_max = C_TO_K(99),   \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_thermistor_charger =
+	THERMAL_THERMISTOR_CHARGER;
 
-const static struct ec_thermal_config thermal_thermistor_5v = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(60),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(99),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(50),
-	},
-	.temp_fan_off = C_TO_K(98),
-	.temp_fan_max = C_TO_K(99),
-};
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_THERMISTOR_5V    \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(60), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(99), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(50), \
+		}, \
+		.temp_fan_off = C_TO_K(98), \
+		.temp_fan_max = C_TO_K(99), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_thermistor_5v =
+	THERMAL_THERMISTOR_5V;
 
-const static struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(100),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(105),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(99),
-	},
-	.temp_fan_off = C_TO_K(105),
-	.temp_fan_max = C_TO_K(105),
-};
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(100), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(105), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(99), \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 
 struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
 
@@ -450,13 +556,13 @@ struct fan_step {
 };
 
 static const struct fan_step fan_table0[] = {
-	{.on =  0, .off =  5, .rpm = 0},
-	{.on = 29, .off =  5, .rpm = 3700},
-	{.on = 38, .off = 19, .rpm = 4000},
-	{.on = 48, .off = 33, .rpm = 4500},
-	{.on = 62, .off = 43, .rpm = 4800},
-	{.on = 76, .off = 52, .rpm = 5200},
-	{.on = 100, .off = 67, .rpm = 6200},
+	{ .on = 0, .off = 5, .rpm = 0 },
+	{ .on = 29, .off = 5, .rpm = 3700 },
+	{ .on = 38, .off = 19, .rpm = 4000 },
+	{ .on = 48, .off = 33, .rpm = 4500 },
+	{ .on = 62, .off = 43, .rpm = 4800 },
+	{ .on = 76, .off = 52, .rpm = 5200 },
+	{ .on = 100, .off = 67, .rpm = 6200 },
 };
 /* All fan tables must have the same number of levels */
 #define NUM_FAN_LEVELS ARRAY_SIZE(fan_table0)
@@ -496,8 +602,7 @@ int fan_percent_to_rpm(int fan, int pct)
 
 	previous_pct = pct;
 
-	if (fan_table[current_level].rpm !=
-		fan_get_rpm_target(FAN_CH(fan)))
+	if (fan_table[current_level].rpm != fan_get_rpm_target(FAN_CH(fan)))
 		cprints(CC_THERMAL, "Setting fan RPM to %d",
 			fan_table[current_level].rpm);
 
@@ -520,15 +625,14 @@ DECLARE_HOOK(HOOK_INIT, setup_fans, HOOK_PRIO_DEFAULT);
  * The connector has 24 pins total, and there is no pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-		{0, 5}, {1, 1}, {1, 0}, {0, 6}, {0, 7},
-		{1, 4}, {1, 3}, {1, 6}, {1, 7}, {3, 1},
-		{2, 0}, {1, 5}, {2, 6}, {2, 7}, {2, 1},
-		{2, 4}, {2, 5}, {1, 2}, {2, 3}, {2, 2},
-		{3, 0}, {-1, -1}, {-1, -1}, {-1, -1},
+	{ 0, 5 }, { 1, 1 }, { 1, 0 }, { 0, 6 },	  { 0, 7 },   { 1, 4 },
+	{ 1, 3 }, { 1, 6 }, { 1, 7 }, { 3, 1 },	  { 2, 0 },   { 1, 5 },
+	{ 2, 6 }, { 2, 7 }, { 2, 1 }, { 2, 4 },	  { 2, 5 },   { 1, 2 },
+	{ 2, 3 }, { 2, 2 }, { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 },
 };
 
 const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 #endif
 
 /*****************************************************************************
@@ -573,9 +677,8 @@ enum gpio_signal board_usbc_port_to_hpd_gpio(int port)
 	 *    from USB-PD messages..
 	 */
 	else if (ec_config_has_mst_hub_rtd2141b())
-		return (board_ver >= 3)
-				? GPIO_USB_C1_HPD_IN_DB_V1
-				: GPIO_NO_HPD;
+		return (board_ver >= 3) ? GPIO_USB_C1_HPD_IN_DB_V1 :
+					  GPIO_NO_HPD;
 
 	/* USB-C1 OPT1 DB uses DP2_HPD. */
 	return GPIO_DP2_HPD;
diff --git a/board/berknip/board.h b/board/berknip/board.h
index d6e127ca3c..454432ba0a 100644
--- a/board/berknip/board.h
+++ b/board/berknip/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,10 +10,9 @@
 
 #define VARIANT_ZORK_TREMBYLE
 
-#include <stdbool.h>
 #include "baseboard.h"
 
-#define CONFIG_MKBP_USE_GPIO
+#include <stdbool.h>
 
 #define RPM_DEVIATION 1
 #define CONFIG_FAN_RPM_CUSTOM
@@ -27,31 +26,32 @@
 #define CONFIG_USB_MUX_PS8743
 #define CONFIG_USBC_RETIMER_TUSB544
 #define TUSB544_I2C_ADDR_FLAGS1 0x0F
+#define CONFIG_TUSB544_EQ_BY_REGISTER
 
 #define CONFIG_POWER_SIGNAL_RUNTIME_CONFIG
 
 /* GPIO mapping from board specific name to EC common name. */
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_EC_BATT_PRES_ODL
-#define CONFIG_SCI_GPIO			GPIO_EC_FCH_SCI_ODL
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_AP_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT_L		GPIO_EC_EDP_BL_DISABLE
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_FCH_PWR_BTN_L
-#define GPIO_PCH_RSMRST_L		GPIO_EC_FCH_RSMRST_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S5_L		GPIO_SLP_S5_L
-#define GPIO_PCH_SYS_PWROK		GPIO_EC_FCH_PWROK
-#define GPIO_PCH_WAKE_L			GPIO_EC_FCH_WAKE_L
-#define GPIO_POWER_BUTTON_L		GPIO_EC_PWR_BTN_ODL
-#define GPIO_S5_PGOOD			GPIO_EC_PWROK_OD
-#define GPIO_SYS_RESET_L		GPIO_EC_SYS_RST_L
-#define GPIO_VOLUME_DOWN_L		GPIO_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
+#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL
+#define CONFIG_SCI_GPIO GPIO_EC_FCH_SCI_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_AP_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_EDP_BL_DISABLE
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PCH_PWRBTN_L GPIO_EC_FCH_PWR_BTN_L
+#define GPIO_PCH_RSMRST_L GPIO_EC_FCH_RSMRST_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L
+#define GPIO_PCH_SYS_PWROK GPIO_EC_FCH_PWROK
+#define GPIO_PCH_WAKE_L GPIO_EC_FCH_WAKE_L
+#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL
+#define GPIO_S5_PGOOD GPIO_EC_PWROK_OD
+#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L
+#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
 
 #ifndef __ASSEMBLER__
 
@@ -77,11 +77,7 @@ enum mft_channel {
 	MFT_CH_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_FAN,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_FAN, PWM_CH_COUNT };
 
 enum temp_sensor_id {
 	TEMP_SENSOR_CHARGER = 0,
@@ -91,16 +87,11 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum usba_port {
-	USBA_PORT_A0 = 0,
-	USBA_PORT_A1,
-	USBA_PORT_COUNT
-};
+enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT };
 
 /*****************************************************************************
  * CBI EC FW Configuration
  */
-#include "cbi_ec_fw_config.h"
 
 /**
  * BERKNIP_MB_USBAC
@@ -147,50 +138,41 @@ enum ec_cfg_usb_db_type {
 	BERKNIP_DB_T_OPT3_USBAC_HDMI_MSTHUB = 1,
 };
 
+#include "cbi_ec_fw_config.h"
 
-#define HAS_USBC1_RETIMER_PS8743 \
-			(BIT(BERKNIP_DB_T_OPT3_USBAC_HDMI_MSTHUB))
+#define HAS_USBC1_RETIMER_PS8743 (BIT(BERKNIP_DB_T_OPT3_USBAC_HDMI_MSTHUB))
 
 static inline bool ec_config_has_usbc1_retimer_ps8743(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_USBC1_RETIMER_PS8743);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_USBC1_RETIMER_PS8743);
 }
 
-#define HAS_USBC1_RETIMER_TUSB544 \
-			(BIT(BERKNIP_DB_T_OPT1_USBAC_HMDI))
+#define HAS_USBC1_RETIMER_TUSB544 (BIT(BERKNIP_DB_T_OPT1_USBAC_HMDI))
 
 static inline bool ec_config_has_usbc1_retimer_tusb544(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_USBC1_RETIMER_TUSB544);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_USBC1_RETIMER_TUSB544);
 }
 
-#define HAS_HDMI_RETIMER_PI3HDX1204 \
-			(BIT(BERKNIP_DB_T_OPT1_USBAC_HMDI))
+#define HAS_HDMI_RETIMER_PI3HDX1204 (BIT(BERKNIP_DB_T_OPT1_USBAC_HMDI))
 
 static inline bool ec_config_has_hdmi_retimer_pi3hdx1204(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_HDMI_RETIMER_PI3HDX1204);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_HDMI_RETIMER_PI3HDX1204);
 }
 
-#define HAS_MST_HUB_RTD2141B \
-			(BIT(BERKNIP_DB_T_OPT3_USBAC_HDMI_MSTHUB))
+#define HAS_MST_HUB_RTD2141B (BIT(BERKNIP_DB_T_OPT3_USBAC_HDMI_MSTHUB))
 
 static inline bool ec_config_has_mst_hub_rtd2141b(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_MST_HUB_RTD2141B);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_MST_HUB_RTD2141B);
 }
 
-#define HAS_HDMI_CONN_HPD \
-			(BIT(BERKNIP_DB_T_OPT1_USBAC_HMDI))
+#define HAS_HDMI_CONN_HPD (BIT(BERKNIP_DB_T_OPT1_USBAC_HMDI))
 
 static inline bool ec_config_has_hdmi_conn_hpd(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_HDMI_CONN_HPD);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_HDMI_CONN_HPD);
 }
 
 enum gpio_signal board_usbc_port_to_hpd_gpio(int port);
@@ -200,13 +182,6 @@ extern const struct usb_mux usbc1_tusb544;
 extern const struct usb_mux usbc1_ps8743;
 extern struct usb_mux usbc1_amd_fp5_usb_mux;
 
-void hdmi_hpd_interrupt(enum ioex_signal signal);
-
-#ifdef CONFIG_KEYBOARD_FACTORY_TEST
-extern const int keyboard_factory_scan_pins[][2];
-extern const int keyboard_factory_scan_pins_used;
-#endif
-
 #endif /* !__ASSEMBLER__ */
 
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/berknip/build.mk b/board/berknip/build.mk
index 1c0cbc4f63..45c71f962c 100644
--- a/board/berknip/build.mk
+++ b/board/berknip/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/berknip/ec.tasklist b/board/berknip/ec.tasklist
index 3a08ebc972..779bd4fdd6 100644
--- a/board/berknip/ec.tasklist
+++ b/board/berknip/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/berknip/gpio.inc b/board/berknip/gpio.inc
index e265101d2b..1bba6a3a69 100644
--- a/board/berknip/gpio.inc
+++ b/board/berknip/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -36,6 +36,7 @@ GPIO_INT(ACOK_OD,		PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	extpower_inter
 GPIO_INT(EC_WP_L,		PIN(5, 0), GPIO_INT_BOTH,			switch_interrupt)
 GPIO_INT(VOLDN_BTN_ODL,		PIN(A, 6), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
 GPIO_INT(VOLUP_BTN_ODL,		PIN(9, 5), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
+GPIO_INT(DP1_HPD_EC_IN,		PIN(7, 5), GPIO_INT_BOTH,			hdmi_hpd_interrupt)
 
 /* GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an interrupt handler. */
 GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH)
@@ -60,7 +61,6 @@ GPIO(USB_C0_HPD,		PIN(F, 5), GPIO_OUT_LOW)			/* C0 DP Hotplug Detect */
 GPIO(USB_C0_IN_HPD,		PIN(7, 3), GPIO_OUT_LOW)			/* C0 IN Hotplug Detect */
 GPIO(EC_DP1_HPD,		PIN(F, 4), GPIO_OUT_LOW)			/* C1 DP Hotplug Detect */
 GPIO(DP2_HPD,			PIN(C, 1), GPIO_OUT_LOW)			/* C1 DP Hotplug Detect */
-GPIO(DP1_HPD_EC_IN,		PIN(7, 5), GPIO_INPUT)				/* C1  IN Hotplug Detect */
 GPIO(EC_H1_PACKET_MODE,		PIN(8, 6), GPIO_OUT_LOW)			/* H1 Packet Mode */
 
 UNIMPLEMENTED(NO_HPD)
diff --git a/board/berknip/led.c b/board/berknip/led.c
index 2042186623..431d517572 100644
--- a/board/berknip/led.c
+++ b/board/berknip/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,9 +9,9 @@
 #include "chipset.h"
 #include "ec_commands.h"
 #include "gpio.h"
+#include "hooks.h"
 #include "host_command.h"
 #include "led_common.h"
-#include "hooks.h"
 
 #define BAT_LED_ON 0
 #define BAT_LED_OFF 1
@@ -20,7 +20,9 @@
 #define POWER_LED_OFF 1
 
 #define LED_TICKS_PER_CYCLE 10
+#define LED_TICKS_PER_CYCLE_S3 35
 #define LED_ON_TICKS 5
+#define POWER_LED_ON_S3_TICKS 5
 
 const enum ec_led_id supported_led_ids[] = {
 	EC_LED_ID_LEFT_LED,
@@ -33,22 +35,19 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
-enum led_port {
-	RIGHT_PORT = 0,
-	LEFT_PORT
-};
+enum led_port { RIGHT_PORT = 0, LEFT_PORT };
 
 static void led_set_color_battery(int port, enum led_color color)
 {
 	enum gpio_signal amber_led, white_led;
 
 	amber_led = (port == RIGHT_PORT ? GPIO_LED_CHRG_L :
-				 GPIO_C1_CHARGE_LED_AMBER_DB_L);
+					  GPIO_C1_CHARGE_LED_AMBER_DB_L);
 	white_led = (port == RIGHT_PORT ? GPIO_LED_FULL_L :
-				 GPIO_C1_CHARGE_LED_WHITE_DB_L);
+					  GPIO_C1_CHARGE_LED_WHITE_DB_L);
 
 	switch (color) {
 	case LED_WHITE:
@@ -120,17 +119,16 @@ static void set_active_port_color(enum led_color color)
 
 	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
 		led_set_color_battery(RIGHT_PORT,
-				(port == RIGHT_PORT) ? color : LED_OFF);
+				      (port == RIGHT_PORT) ? color : LED_OFF);
 	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
 		led_set_color_battery(LEFT_PORT,
-				(port == LEFT_PORT) ? color : LED_OFF);
+				      (port == LEFT_PORT) ? color : LED_OFF);
 }
 
 static void led_set_battery(void)
 {
 	static int battery_ticks;
 	static int power_ticks;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
@@ -139,32 +137,39 @@ static void led_set_battery(void)
 	 * design, blinking both two side battery white LEDs to indicate
 	 * system suspend with non-charging state.
 	 */
-	if (chipset_in_state(CHIPSET_STATE_SUSPEND |
-				 CHIPSET_STATE_STANDBY) &&
-		charge_get_state() != PWR_STATE_CHARGE) {
-
+	if (chipset_in_state(CHIPSET_STATE_SUSPEND | CHIPSET_STATE_STANDBY) &&
+	    led_pwr_get_state() != LED_PWRS_CHARGE) {
 		power_ticks++;
 
-		led_set_color_battery(RIGHT_PORT, power_ticks & 0x4 ?
-					  LED_WHITE : LED_OFF);
-		led_set_color_battery(LEFT_PORT, power_ticks & 0x4 ?
-					  LED_WHITE : LED_OFF);
+		led_set_color_battery(RIGHT_PORT,
+				      power_ticks % LED_TICKS_PER_CYCLE_S3 <
+						      POWER_LED_ON_S3_TICKS ?
+					      LED_WHITE :
+					      LED_OFF);
+		led_set_color_battery(LEFT_PORT,
+				      power_ticks % LED_TICKS_PER_CYCLE_S3 <
+						      POWER_LED_ON_S3_TICKS ?
+					      LED_WHITE :
+					      LED_OFF);
 		return;
 	}
 
 	power_ticks = 0;
 
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
 		/* Always indicate when charging, even in suspend. */
 		set_active_port_color(LED_AMBER);
 		break;
-	case PWR_STATE_DISCHARGE:
+	case LED_PWRS_DISCHARGE:
 		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
 			if (charge_get_percent() < 10)
-				led_set_color_battery(RIGHT_PORT,
-					(battery_ticks % LED_TICKS_PER_CYCLE
-					 < LED_ON_TICKS) ? LED_WHITE : LED_OFF);
+				led_set_color_battery(
+					RIGHT_PORT,
+					(battery_ticks % LED_TICKS_PER_CYCLE <
+					 LED_ON_TICKS) ?
+						LED_WHITE :
+						LED_OFF);
 			else
 				led_set_color_battery(RIGHT_PORT, LED_OFF);
 		}
@@ -172,20 +177,21 @@ static void led_set_battery(void)
 		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
 			led_set_color_battery(LEFT_PORT, LED_OFF);
 		break;
-	case PWR_STATE_ERROR:
-		set_active_port_color((battery_ticks & 0x2) ?
-				LED_WHITE : LED_OFF);
+	case LED_PWRS_ERROR:
+		set_active_port_color((battery_ticks & 0x2) ? LED_WHITE :
+							      LED_OFF);
 		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
+	case LED_PWRS_CHARGE_NEAR_FULL:
 		set_active_port_color(LED_WHITE);
 		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			set_active_port_color((battery_ticks %
-				LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-				LED_AMBER : LED_OFF);
-		else
-			set_active_port_color(LED_WHITE);
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		set_active_port_color(LED_WHITE);
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		set_active_port_color(
+			(battery_ticks % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
+				LED_AMBER :
+				LED_OFF);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
diff --git a/board/berknip/vif_override.xml b/board/berknip/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/berknip/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/bland b/board/bland
new file mode 120000
index 0000000000..7f4a914148
--- /dev/null
+++ b/board/bland
@@ -0,0 +1 @@
+hammer
\ No newline at end of file
diff --git a/board/blipper/battery.c b/board/blipper/battery.c
new file mode 100644
index 0000000000..61ad95d4b7
--- /dev/null
+++ b/board/blipper/battery.c
@@ -0,0 +1,192 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "charge_state.h"
+#include "common.h"
+
+/*
+ * Battery info for all blipper battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	/* SMP L20M3PG0 Battery Information */
+	[BATTERY_SMP1] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP",
+			.device_name = "L20M3PG0",
+			.ship_mode = {
+				.reg_addr = 0x34,
+				.reg_data = { 0x0000, 0x1000 },
+			},
+			.fet = {
+				.reg_addr = 0x00,
+				.reg_mask = 0x0018,
+				.disconnect_val = 0x0000,
+				.cfet_mask = 0x0008,
+				.cfet_off_val = 0x0000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13200, /* mV */
+			.voltage_normal		= 11520, /* mV */
+			.voltage_min		= 9000,  /* mV */
+			.precharge_current	= 256,	 /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 60,
+		},
+	},
+
+	/* SMP L20M3PG3 Battery Information */
+	[BATTERY_SMP2] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP",
+			.device_name = "L20M3PG3",
+			.ship_mode = {
+				.reg_addr = 0x34,
+				.reg_data = { 0x0000, 0x1000 },
+			},
+			.fet = {
+				.reg_addr = 0x00,
+				.reg_mask = 0x0018,
+				.disconnect_val = 0x0000,
+				.cfet_mask = 0x0008,
+				.cfet_off_val = 0x0000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13200, /* mV */
+			.voltage_normal		= 11520, /* mV */
+			.voltage_min		= 9000,  /* mV */
+			.precharge_current	= 256,	 /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 60,
+		},
+	},
+
+	/* LGC L20L3PG0 Battery Information */
+	[BATTERY_LGC] = {
+		.fuel_gauge = {
+			.manuf_name = "LGC",
+			.device_name = "L20L3PG0",
+			.ship_mode = {
+				.reg_addr = 0x34,
+				.reg_data = { 0x0000, 0x1000 },
+			},
+			.fet = {
+				.reg_addr = 0x00,
+				.reg_mask = 0x0018,
+				.disconnect_val = 0x0000,
+				.cfet_mask = 0x0008,
+				.cfet_off_val = 0x0000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13200, /* mV */
+			.voltage_normal		= 11520, /* mV */
+			.voltage_min		= 9000,  /* mV */
+			.precharge_current	= 256,	 /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 73,
+		},
+	},
+
+	/* Sunwoda L20D3PG0 Battery Information */
+	[BATTERY_SUNWODA] = {
+		.fuel_gauge = {
+			.manuf_name = "Sunwoda",
+			.device_name = "L20D3PG0",
+			.ship_mode = {
+				.reg_addr = 0x34,
+				.reg_data = { 0x0000, 0x1000 },
+			},
+			.fet = {
+				.reg_addr = 0x00,
+				.reg_mask = 0x0018,
+				.disconnect_val = 0x0000,
+				.cfet_mask = 0x0008,
+				.cfet_off_val = 0x0000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13200, /* mV */
+			.voltage_normal		= 11520, /* mV */
+			.voltage_min		= 9000,  /* mV */
+			.precharge_current	= 205,	 /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 60,
+		},
+	},
+
+	/* Celxert L20C3PG0 Battery Information */
+	[BATTERY_CELXPERT] = {
+		.fuel_gauge = {
+			.manuf_name = "Celxpert",
+			.device_name = "L20C3PG0",
+			.ship_mode = {
+				.reg_addr = 0x34,
+				.reg_data = { 0x0000, 0x1000 },
+			},
+			.fet = {
+				.reg_addr = 0x00,
+				.reg_mask = 0x0018,
+				.disconnect_val = 0x0000,
+				.cfet_mask = 0x0008,
+				.cfet_off_val = 0x0000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13200, /* mV */
+			.voltage_normal		= 11520, /* mV */
+			.voltage_min		= 9000,  /* mV */
+			.precharge_current	= 200,	 /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 60,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SMP1;
diff --git a/board/blipper/board.c b/board/blipper/board.c
new file mode 100644
index 0000000000..15a2d4b520
--- /dev/null
+++ b/board/blipper/board.c
@@ -0,0 +1,648 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Blipper board-specific configuration */
+
+#include "adc_chip.h"
+#include "button.h"
+#include "cbi_fw_config.h"
+#include "cbi_ssfc.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "cros_board_info.h"
+#include "driver/accel_lis2dw12.h"
+#include "driver/accelgyro_bmi260.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "driver/accelgyro_icm42607.h"
+#include "driver/accelgyro_icm_common.h"
+#include "driver/accelgyro_lsm6dsm.h"
+#include "driver/bc12/pi3usb9201.h"
+#include "driver/charger/isl923x.h"
+#include "driver/tcpm/raa489000.h"
+#include "driver/tcpm/tcpci.h"
+#include "driver/temp_sensor/thermistor.h"
+#include "driver/usb_mux/it5205.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "intc.h"
+#include "keyboard_raw.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "switch.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "tcpm/tcpci.h"
+#include "temp_sensor.h"
+#include "uart.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+
+#define CPRINTF(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define INT_RECHECK_US 5000
+
+__override struct keyboard_scan_config keyscan_config = {
+	.output_settle_us = 80,
+	.debounce_down_us = 30 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x1c, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
+		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
+	},
+};
+
+/* C0 interrupt line shared by BC 1.2 and charger */
+static void check_c0_line(void);
+DECLARE_DEFERRED(check_c0_line);
+
+static void hdmi_hpd_interrupt(enum gpio_signal s)
+{
+	gpio_set_level(GPIO_USB_C1_DP_HPD, !gpio_get_level(s));
+}
+
+static void notify_c0_chips(void)
+{
+	/*
+	 * The interrupt line is shared between the TCPC and BC 1.2 detection
+	 * chip.  Therefore we'll need to check both ICs.
+	 */
+	schedule_deferred_pd_interrupt(0);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+
+static void check_c0_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		notify_c0_chips();
+		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+	}
+}
+
+static void usb_c0_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c0_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c0_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+}
+
+static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
+{
+	cprints(CC_USBPD, "C0: CC OVP, SBU OVP, or thermal event");
+	pd_handle_cc_overvoltage(0);
+}
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	[ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH0 },
+	[ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH2 },
+	[ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH3 },
+	[ADC_TEMP_SENSOR_3] = { .name = "TEMP_SENSOR3",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH15 },
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* BC 1.2 chips */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	{
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+		.flags = PI3USB9201_ALWAYS_POWERED,
+	},
+};
+
+/* Charger chips */
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+};
+
+/* TCPCs */
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0,
+			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
+		},
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+		.drv = &raa489000_tcpm_drv,
+	},
+};
+
+/* USB Muxes */
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+			},
+	},
+};
+
+static const struct ec_response_keybd_config blipper_keybd = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY | KEYBD_CAP_NUMERIC_KEYPAD,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &blipper_keybd;
+}
+
+/* USB-A charging control */
+const int usb_port_enable[USB_PORT_COUNT] = { GPIO_EN_USB_A0_VBUS };
+
+static uint32_t board_id;
+
+/* Sensors */
+static struct mutex g_lid_mutex;
+static struct mutex g_base_mutex;
+
+/* Matrices to rotate accelerometers into the standard reference. */
+static const mat33_fp_t lid_lis2dwl_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					    { FLOAT_TO_FP(1), 0, 0 },
+					    { 0, 0, FLOAT_TO_FP(-1) } };
+
+static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
+
+/* Lid accel private data */
+static struct stprivate_data g_lis2dwl_data;
+struct motion_sensor_t motion_sensors[] = {
+	[LID_ACCEL] = {
+		.name = "Lid Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LIS2DWL,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &lis2dw12_drv,
+		.mutex = &g_lid_mutex,
+		.drv_data = &g_lis2dwl_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LIS2DWL_ADDR1_FLAGS,
+		.rot_standard_ref = &lid_lis2dwl_ref,
+		.default_range = 2, /* g */
+		.min_frequency = LIS2DW12_ODR_MIN_VAL,
+		.max_frequency = LIS2DW12_ODR_MAX_VAL,
+		.config = {
+			/* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 12500 | ROUND_UP_FLAG,
+			},
+			/* Sensor on for lid angle detection */
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+		},
+	},
+	[BASE_ACCEL] = {
+		.name = "Base Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LSM6DS3,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &lsm6dsm_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
+				MOTIONSENSE_TYPE_ACCEL),
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
+		.rot_standard_ref = NULL,		/* identity matrix */
+		.default_range = 4,  /* g */
+		.min_frequency = LSM6DSM_ODR_MIN_VAL,
+		.max_frequency = LSM6DSM_ODR_MAX_VAL,
+		.config = {
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 13000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+		},
+	},
+	[BASE_GYRO] = {
+		.name = "Base Gyro",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LSM6DS3,
+		.type = MOTIONSENSE_TYPE_GYRO,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &lsm6dsm_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
+				MOTIONSENSE_TYPE_GYRO),
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
+		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
+		.rot_standard_ref = NULL,               /* identity matrix */
+		.min_frequency = LSM6DSM_ODR_MIN_VAL,
+		.max_frequency = LSM6DSM_ODR_MAX_VAL,
+	},
+};
+
+static struct icm_drv_data_t g_icm42607_data;
+const mat33_fp_t based_ref_icm42607 = { { FLOAT_TO_FP(1), 0, 0 },
+					{ 0, FLOAT_TO_FP(1), 0 },
+					{ 0, 0, FLOAT_TO_FP(1) } };
+struct motion_sensor_t icm42607_base_accel = {
+	 .name = "Base Accel",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_ICM42607,
+	 .type = MOTIONSENSE_TYPE_ACCEL,
+	 .location = MOTIONSENSE_LOC_BASE,
+	 .drv = &icm42607_drv,
+	 .mutex = &g_base_mutex,
+	 .drv_data = &g_icm42607_data,
+	 .port = I2C_PORT_ACCEL,
+	 .i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
+	 .default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
+	 .rot_standard_ref = &based_ref_icm42607,
+	 .min_frequency = ICM42607_ACCEL_MIN_FREQ,
+	 .max_frequency = ICM42607_ACCEL_MAX_FREQ,
+	 .config = {
+		 /* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	 },
+};
+struct motion_sensor_t icm42607_base_gyro = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM42607,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm42607_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm42607_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &based_ref_icm42607,
+	.min_frequency = ICM42607_GYRO_MIN_FREQ,
+	.max_frequency = ICM42607_GYRO_MAX_FREQ,
+};
+
+static struct bmi_drv_data_t g_bmi220_data;
+const mat33_fp_t based_ref_bmi220 = { { 0, FLOAT_TO_FP(1), 0 },
+				      { FLOAT_TO_FP(-1), 0, 0 },
+				      { 0, 0, FLOAT_TO_FP(1) } };
+struct motion_sensor_t bmi220_base_accel = {
+	 .name = "Base Accel",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_BMI220,
+	 .type = MOTIONSENSE_TYPE_ACCEL,
+	 .location = MOTIONSENSE_LOC_BASE,
+	 .drv = &bmi260_drv,
+	 .mutex = &g_base_mutex,
+	 .drv_data = &g_bmi220_data,
+	 .port = I2C_PORT_ACCEL,
+	 .i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
+	 .default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
+	 .rot_standard_ref = &based_ref_bmi220,
+	 .min_frequency = BMI_ACCEL_MIN_FREQ,
+	 .max_frequency = BMI_ACCEL_MAX_FREQ,
+	 .config = {
+		[SENSOR_CONFIG_EC_S0] = {
+				.odr = 13000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+		},
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+	 },
+};
+struct motion_sensor_t bmi220_base_gyro = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_BMI220,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &bmi260_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_bmi220_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &based_ref_bmi220,
+	.min_frequency = BMI_GYRO_MIN_FREQ,
+	.max_frequency = BMI_GYRO_MAX_FREQ,
+};
+
+unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+void board_init(void)
+{
+	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C0_CCSBU_OVP_ODL);
+
+	gpio_enable_interrupt(GPIO_HDMI_HPD_SUB_ODL);
+
+	/* Set LEDs luminance */
+	pwm_set_duty(PWM_CH_LED_RED, 70);
+	pwm_set_duty(PWM_CH_LED_GREEN, 70);
+	pwm_set_duty(PWM_CH_LED_WHITE, 70);
+
+	/* Enable Base Accel interrupt for Beetley */
+	if (get_cbi_fw_config_tablet_mode() == TABLET_MODE_PRESENT)
+		gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
+
+	/*
+	 * If interrupt lines are already low, schedule them to be processed
+	 * after inits are completed.
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL))
+		hook_call_deferred(&check_c0_line_data, 0);
+
+	/* Setting scan mask KSO11, KSO12, KSO13 and KSO14 */
+	keyscan_config.actual_key_mask[11] = 0xfe;
+	keyscan_config.actual_key_mask[12] = 0xff;
+	keyscan_config.actual_key_mask[13] = 0xff;
+	keyscan_config.actual_key_mask[14] = 0xff;
+
+	cbi_get_board_version(&board_id);
+
+	if (get_cbi_fw_config_tablet_mode() == TABLET_MODE_ABSENT) {
+		motion_sensor_count = 0;
+		gmr_tablet_switch_disable();
+		/*
+		 * Base accel is not stuffed, don't allow
+		 * line to float.
+		 */
+		gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L,
+			       GPIO_INPUT | GPIO_PULL_DOWN);
+
+		/* Disable Volume keys for blipper */
+		button_disable_gpio(BUTTON_VOLUME_UP);
+		button_disable_gpio(BUTTON_VOLUME_DOWN);
+		gpio_set_flags(GPIO_VOLDN_BTN_ODL, GPIO_INPUT | GPIO_PULL_DOWN);
+		gpio_set_flags(GPIO_VOLUP_BTN_ODL, GPIO_INPUT | GPIO_PULL_DOWN);
+	} else {
+		if (get_cbi_ssfc_base_sensor() == SSFC_SENSOR_ICM42607) {
+			motion_sensors[BASE_ACCEL] = icm42607_base_accel;
+			motion_sensors[BASE_GYRO] = icm42607_base_gyro;
+			CPRINTF("BASE GYRO is ICM42607");
+		} else if (get_cbi_ssfc_base_sensor() == SSFC_SENSOR_BMI220) {
+			motion_sensors[BASE_ACCEL] = bmi220_base_accel;
+			motion_sensors[BASE_GYRO] = bmi220_base_gyro;
+			CPRINTF("BASE GYRO is BMI220");
+		} else {
+			CPRINTF("BASE GYRO is LSM6DSM");
+		}
+	}
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	switch (get_cbi_ssfc_base_sensor()) {
+	case SSFC_SENSOR_ICM42607:
+		icm42607_interrupt(signal);
+		break;
+	case SSFC_SENSOR_BMI220:
+		bmi260_interrupt(signal);
+		break;
+	case SSFC_SENSOR_LSM6DSM:
+	default:
+		lsm6dsm_interrupt(signal);
+		break;
+	}
+}
+
+void board_hibernate(void)
+{
+	/*
+	 * Charger IC need to be put into their "low power mode" before
+	 * entering the Z-state.
+	 *
+	 * b:186717219: In order to solve the power consumption problem of
+	 * hibernate，HW solution is adopted after board id 3 to solve the
+	 * problem that AC cannot wake up hibernate mode.
+	 */
+	if (board_id > 2)
+		raa489000_hibernate(0, true);
+	else
+		raa489000_hibernate(0, false);
+}
+
+__override void board_pulse_entering_rw(void)
+{
+	/*
+	 * On the ITE variants, the EC_ENTERING_RW signal was connected to a pin
+	 * which is active high by default.  This causes Cr50 to think that the
+	 * EC has jumped to its RW image even though this may not be the case.
+	 * The pin is changed to GPIO_EC_ENTERING_RW2.
+	 */
+	gpio_set_level(GPIO_EC_ENTERING_RW, 1);
+	gpio_set_level(GPIO_EC_ENTERING_RW2, 1);
+	usleep(MSEC);
+	gpio_set_level(GPIO_EC_ENTERING_RW, 0);
+	gpio_set_level(GPIO_EC_ENTERING_RW2, 0);
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * Nothing to do.  TCPC C0 is internal, TCPC C1 reset pin is not
+	 * connected to the EC.
+	 */
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+	int regval;
+
+	/*
+	 * The interrupt line is shared between the TCPC and BC1.2 detector IC.
+	 * Therefore, go out and actually read the alert registers to report the
+	 * alert status.
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
+			/* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */
+			if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0))
+				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
+
+			if (regval)
+				status |= PD_STATUS_TCPC_ALERT_0;
+		}
+	}
+
+	return status;
+}
+
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	if (port < 0 || port > board_get_usb_pd_port_count())
+		return;
+
+	raa489000_set_output_current(port, rp);
+}
+
+int board_is_sourcing_vbus(int port)
+{
+	int regval;
+
+	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
+	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
+}
+
+int board_set_active_charge_port(int port)
+{
+	if (port != 0 && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	CPRINTUSB("New chg p%d", port);
+
+	/* Disable all ports. */
+	if (port == CHARGE_PORT_NONE) {
+		tcpc_write(0, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
+		raa489000_enable_asgate(0, false);
+		return EC_SUCCESS;
+	}
+
+	/* Check if port is sourcing VBUS. */
+	if (board_is_sourcing_vbus(port)) {
+		CPRINTUSB("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	/* Enable requested charge port. */
+	if (raa489000_enable_asgate(port, true) ||
+	    tcpc_write(0, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
+		CPRINTUSB("p%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_LED_RED] = {
+		.channel = 1,
+		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
+		.freq_hz = 2400,
+	},
+
+	[PWM_CH_LED_GREEN] = {
+		.channel = 2,
+		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
+		.freq_hz = 2400,
+	},
+
+	[PWM_CH_LED_WHITE] = {
+		.channel = 3,
+		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
+		.freq_hz = 2400,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+/* Thermistors */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1] = { .name = "Charge",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "5V_Inductor",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/* This callback disables keyboard when convertibles are fully open */
+__override void lid_angle_peripheral_enable(int enable)
+{
+	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
+
+	/*
+	 * If the lid is in tablet position via other sensors,
+	 * ignore the lid angle, which might be faulty then
+	 * disable keyboard.
+	 */
+	if (tablet_get_mode())
+		enable = 0;
+
+	if (enable) {
+		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
+	} else {
+		/*
+		 * Ensure that the chipset is off before disabling the keyboard.
+		 * When the chipset is on, the EC keeps the keyboard enabled and
+		 * the AP decides whether to ignore input devices or not.
+		 */
+		if (!chipset_in_s0)
+			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
+	}
+}
diff --git a/board/blipper/board.h b/board/blipper/board.h
new file mode 100644
index 0000000000..1a911da1df
--- /dev/null
+++ b/board/blipper/board.h
@@ -0,0 +1,167 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Blipper board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* Select Baseboard features */
+#define VARIANT_DEDEDE_EC_IT8320
+#include "baseboard.h"
+
+/* Battery */
+#define CONFIG_BATTERY_FUEL_GAUGE
+#define CONFIG_BATTERY_V2
+#define CONFIG_BATTERY_COUNT 1
+#define CONFIG_HOSTCMD_BATTERY_V2
+
+/* BC 1.2 */
+#define CONFIG_BC12_DETECT_PI3USB9201
+
+/* Charger */
+#define CONFIG_CHARGE_RAMP_HW
+#define CONFIG_CHARGER_RAA489000
+#define PD_MAX_VOLTAGE_MV 20000
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
+#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
+/*
+ * b/147463641: The charger IC seems to overdraw ~4%, therefore we
+ * reduce our target accordingly.
+ */
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 4
+
+/* DAC for PSYS */
+#define CONFIG_DAC
+
+/* LED */
+#define CONFIG_LED_ONOFF_STATES
+
+/*SENSOR*/
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
+#define CONFIG_CMD_ACCELS
+#define CONFIG_CMD_ACCEL_INFO
+#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
+
+#define CONFIG_ACCEL_LIS2DWL /* Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
+#define CONFIG_ACCELGYRO_ICM42607
+#define CONFIG_ACCELGYRO_BMI220
+
+/* Lid operates in forced mode, base in FIFO */
+#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
+#define CONFIG_ACCEL_FIFO
+#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */
+#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
+
+#define CONFIG_I2C_XFER_LARGE_TRANSFER
+
+#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+#define CONFIG_ACCELGYRO_BMI260_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+/* ICM426XX Base accel/gyro */
+#define CONFIG_ACCELGYRO_ICM42607_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_UPDATE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+
+#define CONFIG_TABLET_MODE
+#define CONFIG_TABLET_MODE_SWITCH
+#define CONFIG_GMR_TABLET_MODE
+
+/* PWM */
+#define CONFIG_PWM
+
+/* TCPC */
+#define CONFIG_USB_PD_PORT_MAX_COUNT 1
+#define CONFIG_USB_PD_TCPM_RAA489000
+
+/* USB defines specific to external TCPCs */
+#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+#define CONFIG_USB_PD_VBUS_DETECT_TCPC
+#define CONFIG_USB_PD_DISCHARGE_TCPC
+#define CONFIG_USB_PD_TCPC_LOW_POWER
+
+/* EC console commands */
+#define CONFIG_CMD_TCPC_DUMP
+
+/* Variant references the TCPCs to determine Vbus sourcing */
+#define CONFIG_USB_PD_5V_EN_CUSTOM
+
+/* Thermistors */
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_THERMISTOR
+#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
+
+/* USB Mux */
+#define CONFIG_USB_MUX_IT5205
+
+/* KeyBoard */
+#define CONFIG_KEYBOARD_REFRESH_ROW3
+#define CONFIG_KEYBOARD_KEYPAD
+#define CONFIG_KEYBOARD_STRICT_DEBOUNCE
+
+/* USB Type A Features */
+#define USB_PORT_COUNT 1
+#define CONFIG_USB_PORT_POWER_DUMB
+
+/* Button Config*/
+#define CONFIG_BUTTONS_RUNTIME_CONFIG
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum pwm_channel {
+	PWM_CH_LED_RED,
+	PWM_CH_LED_GREEN,
+	PWM_CH_LED_WHITE,
+	PWM_CH_COUNT,
+};
+
+/* Motion sensors */
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
+
+/* ADC channels */
+enum adc_channel {
+	ADC_VSNS_PP3300_A, /* ADC0 */
+	ADC_TEMP_SENSOR_1, /* ADC2 */
+	ADC_TEMP_SENSOR_2, /* ADC3 */
+	ADC_TEMP_SENSOR_3, /* ADC15 */
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1,
+	TEMP_SENSOR_2,
+	TEMP_SENSOR_3,
+	TEMP_SENSOR_COUNT
+};
+
+/* List of possible batteries */
+enum battery_type {
+	BATTERY_SMP1,
+	BATTERY_SMP2,
+	BATTERY_LGC,
+	BATTERY_SUNWODA,
+	BATTERY_CELXPERT,
+	BATTERY_TYPE_COUNT,
+};
+
+void motion_interrupt(enum gpio_signal signal);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/blipper/build.mk b/board/blipper/build.mk
new file mode 100644
index 0000000000..01b890bf29
--- /dev/null
+++ b/board/blipper/build.mk
@@ -0,0 +1,15 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=it83xx
+CHIP_FAMILY:=it8320
+CHIP_VARIANT:=it8320dx
+BASEBOARD:=dedede
+
+board-y=board.o cbi_ssfc.o led.o usb_pd_policy.o
+board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/blipper/cbi_ssfc.c b/board/blipper/cbi_ssfc.c
new file mode 100644
index 0000000000..81f3ee0dad
--- /dev/null
+++ b/board/blipper/cbi_ssfc.c
@@ -0,0 +1,36 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi_ssfc.h"
+#include "common.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "hooks.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+/* Cache SSFC on init since we don't expect it to change in runtime */
+static union dedede_cbi_ssfc cached_ssfc;
+BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
+
+static void cbi_ssfc_init(void)
+{
+	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
+		/* Default to 0 when CBI isn't populated */
+		cached_ssfc.raw_value = 0;
+
+	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
+}
+DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
+
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
+{
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
+}
+
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
+{
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
+}
diff --git a/board/blipper/cbi_ssfc.h b/board/blipper/cbi_ssfc.h
new file mode 100644
index 0000000000..bc6bc92286
--- /dev/null
+++ b/board/blipper/cbi_ssfc.h
@@ -0,0 +1,60 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _DEDEDE_CBI_SSFC__H_
+#define _DEDEDE_CBI_SSFC__H_
+
+#include "stdint.h"
+
+/****************************************************************************
+ * Dedede CBI Second Source Factory Cache
+ */
+
+/*
+ * Base Sensor (Bits 0-2)
+ */
+enum ec_ssfc_base_sensor {
+	SSFC_SENSOR_BASE_DEFAULT = 0,
+	SSFC_SENSOR_BMI160 = 1,
+	SSFC_SENSOR_ICM426XX = 2,
+	SSFC_SENSOR_LSM6DSM = 3,
+	SSFC_SENSOR_ICM42607 = 4,
+	SSFC_SENSOR_BMI220 = 5
+};
+
+/*
+ * Lid Sensor (Bits 3-5)
+ */
+enum ec_ssfc_lid_sensor {
+	SSFC_SENSOR_LID_DEFAULT = 0,
+	SSFC_SENSOR_BMA255 = 1,
+	SSFC_SENSOR_KX022 = 2,
+	SSFC_SENSOR_LIS2DWL = 3
+};
+
+union dedede_cbi_ssfc {
+	struct {
+		uint32_t base_sensor : 3;
+		uint32_t lid_sensor : 3;
+		uint32_t reserved_2 : 26;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Get the Base sensor type from SSFC_CONFIG.
+ *
+ * @return the Base sensor board type.
+ */
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
+
+/**
+ * Get the Lid sensor type from SSFC_CONFIG.
+ *
+ * @return the Lid sensor board type.
+ */
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
+
+#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/blipper/ec.tasklist b/board/blipper/ec.tasklist
new file mode 100644
index 0000000000..8ccdfc81b2
--- /dev/null
+++ b/board/blipper/ec.tasklist
@@ -0,0 +1,22 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, TRENTA_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE)
diff --git a/board/blipper/gpio.inc b/board/blipper/gpio.inc
new file mode 100644
index 0000000000..215f31a281
--- /dev/null
+++ b/board/blipper/gpio.inc
@@ -0,0 +1,151 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+/* Power State interrupts */
+GPIO_INT(SLP_S4_L,		PIN(I, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,		PIN(H, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(SLP_S0_L,		PIN(E, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,		PIN(G, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID0,	PIN(D, 0), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(RSMRST_PWRGD_L,	PIN(E, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(CPU_C10_GATE_L,	PIN(G, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_DRAM_OD,		PIN(D, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(PG_PP1050_ST_OD,	PIN(L, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID1,	PIN(K, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_VCCIO_EXT_OD,	PIN(D, 7), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(ESPI_RESET_L, 	 PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt)
+
+GPIO_INT(H1_EC_PWR_BTN_ODL,	PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
+#ifdef CONFIG_LOW_POWER_IDLE
+/* Used to wake up the EC from Deep Doze mode when writing to console */
+GPIO_INT(UART1_RX,	 PIN(B, 0), GPIO_INT_BOTH, uart_deepsleep_interrupt)	/* UART_DBG_TX_EC_RX */
+#endif
+
+/* USB-C interrupts */
+GPIO_INT(USB_C0_INT_ODL,	PIN(K, 0), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt) /* BC12 and charger */
+GPIO_INT(USB_C0_CCSBU_OVP_ODL,	PIN(K, 6), GPIO_INT_FALLING | GPIO_PULL_UP, c0_ccsbu_ovp_interrupt) /* Fault protection */
+
+/* Other interrupts */
+GPIO_INT(LID_OPEN,		PIN(F, 3), GPIO_INT_BOTH, lid_interrupt)
+GPIO_INT(LID_360_L,		PIN(A, 7), GPIO_INT_BOTH, gmr_tablet_switch_isr)
+GPIO_INT(VOLDN_BTN_ODL,		PIN(I, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(VOLUP_BTN_ODL,		PIN(I, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(J, 0), GPIO_INT_FALLING | GPIO_SEL_1P8V, motion_interrupt)
+GPIO_INT(EC_WP_OD,		PIN(A, 6), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(HDMI_HPD_SUB_ODL,	PIN(E, 7), GPIO_INT_BOTH, hdmi_hpd_interrupt)
+
+/* Power sequence GPIOs */
+GPIO(EC_AP_RTCRST,		PIN(K, 2), GPIO_OUT_LOW)
+GPIO(EC_AP_PWR_BTN_ODL,		PIN(B, 6), GPIO_ODR_HIGH)
+GPIO(EC_AP_DPWROK,		PIN(L, 7), GPIO_OUT_LOW)
+GPIO(EC_AP_RSMRST_L,		PIN(H, 0), GPIO_OUT_LOW)
+GPIO(EC_AP_WAKE_ODL,		PIN(D, 5), GPIO_ODR_HIGH)
+GPIO(SYS_RST_ODL,		PIN(D, 1), GPIO_ODR_HIGH)
+GPIO(EC_AP_SYS_PWROK,		PIN(F, 2), GPIO_OUT_LOW)
+GPIO(PG_PP5000_U_OD,		PIN(E, 3), GPIO_INPUT)
+GPIO(EN_PP3300_A,		PIN(C, 5), GPIO_OUT_LOW)
+GPIO(EC_AP_PCH_PWROK_OD,	PIN(D, 6), GPIO_ODR_LOW)
+GPIO(EN_PP5000_U,		PIN(K, 5), GPIO_OUT_LOW)
+/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
+GPIO(EN_VCCST,			PIN(D, 4), GPIO_INPUT)
+GPIO(EN_VCCIO_EXT,		PIN(B, 2), GPIO_OUT_LOW)
+GPIO(EC_PROCHOT_ODL,		PIN(I, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(EC_AP_VCCST_PWRGD_OD,	PIN(E, 5), GPIO_ODR_LOW)
+GPIO(ALL_SYS_PWRGD,		PIN(B, 7), GPIO_OUT_LOW)
+GPIO(EN_SLP_Z,			PIN(K, 3), GPIO_OUT_LOW)
+
+/* Required for icelake chipset code, but implemented through other means for dedede */
+UNIMPLEMENTED(AC_PRESENT)
+UNIMPLEMENTED(PG_EC_DSW_PWROK)
+UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
+
+/* Used by baseboard z-state enable, but not present on blipper */
+UNIMPLEMENTED(USB_C1_INT_ODL)
+
+/* I2C pins - Alternate function below configures I2C module on these pins */
+GPIO(EC_I2C_EEPROM_SCL,		PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SDA,		PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SCL,	PIN(C, 1), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SDA,	PIN(C, 2), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,		PIN(F, 6), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SENSOR_SDA,		PIN(F, 7), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_USB_C0_SCL,		PIN(A, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SDA,		PIN(A, 5), GPIO_INPUT)
+
+/* USB pins */
+GPIO(EN_USB_A0_VBUS,		PIN(L, 6), GPIO_OUT_LOW)
+GPIO(EN_USB_A1_VBUS,		PIN(E, 6), GPIO_OUT_LOW)
+GPIO(EC_AP_USB_C0_HPD,		PIN(L, 4), GPIO_OUT_LOW)
+GPIO(EC_AP_USB_C1_HDMI_HPD,	PIN(K, 7), GPIO_OUT_LOW)
+GPIO(HDMI_SEL_L,		PIN(C, 6), GPIO_OUT_LOW)
+
+/* MKBP event synchronization */
+GPIO(EC_AP_MKBP_INT_L,	PIN(L, 5), GPIO_ODR_HIGH)
+
+/* Misc pins which will run to the I/O board */
+
+
+/* Misc */
+GPIO(EN_BL_OD,			PIN(K, 4), GPIO_ODR_LOW)
+GPIO(EC_ENTERING_RW,		PIN(G, 0), GPIO_OUT_LOW)
+GPIO(EC_ENTERING_RW2,		PIN(C, 7), GPIO_OUT_LOW)
+GPIO(CCD_MODE_ODL,		PIN(H, 5), GPIO_ODR_HIGH)
+GPIO(EC_BATTERY_PRES_ODL,	PIN(I, 4), GPIO_INPUT)
+GPIO(ECH1_PACKET_MODE,		PIN(H, 1), GPIO_OUT_LOW)
+
+/*TP*/
+GPIO(TP, PIN(C, 3), GPIO_INPUT | GPIO_HIGH)
+
+/* NC pins, enable internal pull-down to avoid floating state. */
+GPIO(GPIOA0_NC, PIN(A, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOB5_NC, PIN(B, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOC4_NC, PIN(C, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOE0_NC, PIN(E, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOF0_NC, PIN(F, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOF1_NC, PIN(F, 1), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOF4_NC, PIN(F, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOF5_NC, PIN(F, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG3_NC, PIN(G, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG4_NC, PIN(G, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG5_NC, PIN(G, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG6_NC, PIN(G, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG7_NC, PIN(G, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOH2_NC, PIN(H, 2), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOH4_NC, PIN(H, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOH6_NC, PIN(H, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ1_NC, PIN(J, 1), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ3_NC, PIN(J, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ4_NC, PIN(J, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ5_NC, PIN(J, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ6_NC, PIN(J, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOL0_NC, PIN(L, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOL3_NC, PIN(L, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOM6_NC, PIN(M, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+
+/* Alternate functions GPIO definitions */
+/* UART */
+ALTERNATE(PIN_MASK(B, BIT(0) | BIT(1)), 0, MODULE_UART, 0)		/* UART for debug */
+
+/* I2C */
+ALTERNATE(PIN_MASK(B, BIT(3) | BIT(4)), 0, MODULE_I2C, 0)		/* I2C0 */
+ALTERNATE(PIN_MASK(C, BIT(1) | BIT(2)), 0, MODULE_I2C, 0)		/* I2C1 */
+ALTERNATE(PIN_MASK(F, BIT(6) | BIT(7)), 0, MODULE_I2C, GPIO_SEL_1P8V)	/* I2C2 - 1.8V SENSOR */
+ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), 0, MODULE_I2C, 0)		/* I2C5 */
+
+/* ADC */
+ALTERNATE(PIN_MASK(L, BIT(2)), 0, MODULE_ADC, 0)		    	/* ADC15: TEMP_SENSOR_3 */
+ALTERNATE(PIN_MASK(I, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0)	/* ADC0: EC_VSNS_PP3300_A, ADC2: TEMP_SENSOR_1, ADC3: TEMP_SENSOR_2 */
+
+/* DAC */
+ALTERNATE(PIN_MASK(J, BIT(2)), 0, MODULE_DAC, 0)			/* DAC2: EC_AP_PSYS */
+
+/* PWM */
+ALTERNATE(PIN_MASK(A, BIT(1) | BIT(2) | BIT(3)), 0, MODULE_PWM, 0) /* RED led, GREEN led, WHITE led */
diff --git a/board/blipper/led.c b/board/blipper/led.c
new file mode 100644
index 0000000000..afba103db6
--- /dev/null
+++ b/board/blipper/led.c
@@ -0,0 +1,117 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Blipper specific PWM LED settings.
+ */
+
+#include "common.h"
+#include "gpio.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+#include "pwm.h"
+
+#define LED_OFF_LVL 0
+#define LED_ON_LVL 1
+
+__override const int led_charge_lvl_1 = 5;
+
+__override const int led_charge_lvl_2 = 97;
+
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
+
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    1 * LED_ONE_SEC },
+						  { LED_OFF,
+						    3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_RED:
+		pwm_enable(PWM_CH_LED_RED, LED_ON_LVL);
+		pwm_enable(PWM_CH_LED_GREEN, LED_OFF_LVL);
+		break;
+	case EC_LED_COLOR_AMBER:
+		pwm_enable(PWM_CH_LED_RED, LED_ON_LVL);
+		pwm_enable(PWM_CH_LED_GREEN, LED_ON_LVL);
+		break;
+	case EC_LED_COLOR_GREEN:
+		pwm_enable(PWM_CH_LED_RED, LED_OFF_LVL);
+		pwm_enable(PWM_CH_LED_GREEN, LED_ON_LVL);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		pwm_enable(PWM_CH_LED_RED, LED_OFF_LVL);
+		pwm_enable(PWM_CH_LED_GREEN, LED_OFF_LVL);
+		break;
+	}
+}
+
+__override void led_set_color_power(enum ec_led_colors color)
+{
+	if (color == EC_LED_COLOR_WHITE)
+		pwm_enable(PWM_CH_LED_WHITE, LED_ON_LVL);
+	else
+		pwm_enable(PWM_CH_LED_WHITE, LED_OFF_LVL);
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_RED] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		brightness_range[EC_LED_COLOR_GREEN] = 1;
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		if (brightness[EC_LED_COLOR_RED] != 0)
+			led_set_color_battery(EC_LED_COLOR_RED);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(EC_LED_COLOR_AMBER);
+		else if (brightness[EC_LED_COLOR_GREEN] != 0)
+			led_set_color_battery(EC_LED_COLOR_GREEN);
+		else
+			led_set_color_battery(LED_OFF);
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_power(EC_LED_COLOR_WHITE);
+		else
+			led_set_color_power(LED_OFF);
+	} else {
+		return EC_ERROR_INVAL;
+	}
+	return EC_SUCCESS;
+}
diff --git a/board/blipper/usb_pd_policy.c b/board/blipper/usb_pd_policy.c
new file mode 100644
index 0000000000..a7633b73ac
--- /dev/null
+++ b/board/blipper/usb_pd_policy.c
@@ -0,0 +1,71 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery_smart.h"
+#include "charge_manager.h"
+#include "charger.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "driver/charger/isl923x_public.h"
+#include "driver/tcpm/tcpci.h"
+#include "usb_pd.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+int pd_check_vconn_swap(int port)
+{
+	/* Allow VCONN swaps if the AP is on */
+	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
+}
+
+void pd_power_supply_reset(int port)
+{
+	if (port != 0)
+		return;
+
+	/* Disable VBUS */
+	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	if (port != 0)
+		return EC_ERROR_INVAL;
+
+	/* Disable charging. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
+	if (rv)
+		return rv;
+
+	/* Our policy is not to source VBUS when the AP is off. */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	/* Provide Vbus. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
+	if (rv)
+		return rv;
+
+	rv = raa489000_enable_asgate(port, true);
+	if (rv)
+		return rv;
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	return pd_check_vbus_level(port, VBUS_PRESENT);
+}
diff --git a/board/blipper/vif_override.xml b/board/blipper/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/blipper/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/bloog/battery.c b/board/bloog/battery.c
index b8ff4b5823..af3282576a 100644
--- a/board/bloog/battery.c
+++ b/board/bloog/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -33,7 +33,7 @@
  */
 const struct board_batt_params board_battery_info[] = {
 	/* DynaPack Coslight BDAK126150-W0P0703HT attery Information */
-	[BATTERY_DANAPACK_COS] = {
+	[BATTERY_DYNAPACK_COS] = {
 		.fuel_gauge = {
 			.manuf_name = "333-2C-DA-A",
 			.ship_mode = {
@@ -62,7 +62,7 @@ const struct board_batt_params board_battery_info[] = {
 	},
 
 	/* DynaPack ATL DynaPack DAK126150-W0G0703HT Battery Information */
-	[BATTERY_DANAPACK_ATL] = {
+	[BATTERY_DYNAPACK_ATL] = {
 		.fuel_gauge = {
 			.manuf_name = "333-27-DA-A",
 			.ship_mode = {
@@ -91,7 +91,7 @@ const struct board_batt_params board_battery_info[] = {
 	},
 
 	/* DynaPack SDI DAK126150-W020703HT Battery Information */
-	[BATTERY_DANAPACK_SDI] = {
+	[BATTERY_DYNAPACK_SDI] = {
 		.fuel_gauge = {
 			.manuf_name = "333-24-DA-A",
 			.ship_mode = {
@@ -292,7 +292,36 @@ const struct board_batt_params board_battery_info[] = {
 			.discharging_max_c = 60,
 		},
 	},
+
+	/* CosMX B00C4473A9D0002 Battery Information */
+	[BATTERY_COS_2] = {
+		.fuel_gauge = {
+			.manuf_name = "333-AC-DA-A",
+			.ship_mode = {
+				.reg_addr = 0x0,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,		/* mV */
+			.voltage_normal = 7700,		/* mV */
+			.voltage_min = 6000,		/* mV */
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
 };
 BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
 
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_DANAPACK_COS;
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_DYNAPACK_COS;
diff --git a/board/bloog/board.c b/board/bloog/board.c
index 2973b5c6dd..9250dfe299 100644
--- a/board/bloog/board.c
+++ b/board/bloog/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,6 @@
 /* Bloog/Blooguard board-specific configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "battery.h"
 #include "button.h"
 #include "charge_manager.h"
@@ -34,20 +33,20 @@
 #include "switch.h"
 #include "system.h"
 #include "tablet_mode.h"
-#include "tcpci.h"
+#include "tcpm/tcpci.h"
 #include "temp_sensor.h"
-#include "thermistor.h"
+#include "temp_sensor/thermistor.h"
 #include "usb_mux.h"
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
-#define USB_PD_PORT_ANX7447	0
-#define USB_PD_PORT_PS8751	1
+#define USB_PD_PORT_ANX7447 0
+#define USB_PD_PORT_PS8751 1
 
 static uint8_t sku_id;
 
@@ -72,32 +71,32 @@ static void ppc_interrupt(enum gpio_signal signal)
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_AMB] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_AMB] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				  ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_CHARGER] = { "TEMP_CHARGER", NPCX_ADC_CH1,
+				      ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 },
 	/* Vbus C0 sensing (10x voltage divider). PPVAR_USB_C0_VBUS */
-	[ADC_VBUS_C0] = {
-		"VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
+	[ADC_VBUS_C0] = { "VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT * 10,
+			  ADC_READ_MAX + 1, 0 },
 	/* Vbus C1 sensing (10x voltage divider). PPVAR_USB_C1_VBUS */
-	[ADC_VBUS_C1] = {
-		"VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
+	[ADC_VBUS_C1] = { "VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT * 10,
+			  ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp,
-				 .idx = 0},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
+	[TEMP_SENSOR_BATTERY] = { .name = "Battery",
+				  .type = TEMP_SENSOR_TYPE_BATTERY,
+				  .read = charge_get_battery_temp,
+				  .idx = 0 },
+	[TEMP_SENSOR_AMBIENT] = { .name = "Ambient",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_51k1_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_AMB },
+	[TEMP_SENSOR_CHARGER] = { .name = "Charger",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_13k7_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_CHARGER },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -107,23 +106,17 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t lid_a_cover_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0,  FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t lid_a_cover_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				     { 0, FLOAT_TO_FP(1), 0 },
+				     { 0, 0, FLOAT_TO_FP(-1) } };
 
-const mat33_fp_t lid_b_cover_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
+const mat33_fp_t lid_b_cover_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				     { 0, FLOAT_TO_FP(-1), 0 },
+				     { 0, 0, FLOAT_TO_FP(1) } };
 
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				       { 0, FLOAT_TO_FP(-1), 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
 
 /* sensor private data */
 static struct kionix_accel_data kx022_data;
@@ -168,8 +161,6 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_base_mutex,
 		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
 				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
 		.port = I2C_PORT_SENSOR,
 		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
 		.rot_standard_ref = &base_standard_ref,
@@ -200,8 +191,6 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_base_mutex,
 		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
 				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
 		.port = I2C_PORT_SENSOR,
 		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
 		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
@@ -225,10 +214,10 @@ int board_is_convertible(void)
 	 * Bipship: 53, 54, 55, 56
 	 * Unprovisioned: 255
 	 */
-	return sku_id == 33 || sku_id == 34 || sku_id == 35 || sku_id == 36
-		|| sku_id == 49 || sku_id == 50 || sku_id == 51 || sku_id == 52
-		|| sku_id == 53 || sku_id == 54 || sku_id == 55 || sku_id == 56
-		|| sku_id == 255;
+	return sku_id == 33 || sku_id == 34 || sku_id == 35 || sku_id == 36 ||
+	       sku_id == 49 || sku_id == 50 || sku_id == 51 || sku_id == 52 ||
+	       sku_id == 53 || sku_id == 54 || sku_id == 55 || sku_id == 56 ||
+	       sku_id == 255;
 }
 
 static void board_update_sensor_config_from_sku(void)
@@ -239,8 +228,8 @@ static void board_update_sensor_config_from_sku(void)
 		gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
 
 		/* Override sensor marix for Bipship. */
-		if (sku_id == 53 || sku_id == 54 || sku_id == 55
-			|| sku_id == 56)
+		if (sku_id == 53 || sku_id == 54 || sku_id == 55 ||
+		    sku_id == 56)
 			motion_sensors[LID_ACCEL].rot_standard_ref =
 				&lid_b_cover_ref;
 	} else {
@@ -270,19 +259,18 @@ void board_hibernate_late(void)
 
 	const uint32_t hibernate_pins[][2] = {
 		/* Turn off LEDs before going to hibernate */
-		{GPIO_LED_WHITE_C0_L, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_LED_AMBER_C0_L, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_LED_WHITE_C1_L, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_LED_AMBER_C1_L, GPIO_INPUT | GPIO_PULL_UP},
+		{ GPIO_LED_WHITE_C0_L, GPIO_INPUT | GPIO_PULL_UP },
+		{ GPIO_LED_AMBER_C0_L, GPIO_INPUT | GPIO_PULL_UP },
+		{ GPIO_LED_WHITE_C1_L, GPIO_INPUT | GPIO_PULL_UP },
+		{ GPIO_LED_AMBER_C1_L, GPIO_INPUT | GPIO_PULL_UP },
 	};
 
 	for (i = 0; i < ARRAY_SIZE(hibernate_pins); ++i)
 		gpio_set_flags(hibernate_pins[i][0], hibernate_pins[i][1]);
 }
 
-#ifndef TEST_BUILD
 /* This callback disables keyboard when convertibles are fully open */
-void lid_angle_peripheral_enable(int enable)
+__override void lid_angle_peripheral_enable(int enable)
 {
 	/*
 	 * If the lid is in tablet position via other sensors,
@@ -295,7 +283,6 @@ void lid_angle_peripheral_enable(int enable)
 	if (board_is_convertible())
 		keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
 }
-#endif
 
 #ifdef CONFIG_KEYBOARD_FACTORY_TEST
 /*
@@ -304,15 +291,15 @@ void lid_angle_peripheral_enable(int enable)
  * The connector has 24 pins total, and there is no pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-		{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-		{0, 7}, {1, 4}, {1, 3}, {1, 6}, {1, 7},
-		{3, 1}, {2, 0}, {1, 5}, {2, 6}, {2, 7},
-		{2, 1}, {2, 4}, {2, 5}, {1, 2}, {2, 3},
-		{2, 2}, {3, 0}, {-1, -1}, {-1, -1}, {-1, -1},
+	{ -1, -1 }, { 0, 5 }, { 1, 1 },	  { 1, 0 },   { 0, 6 },
+	{ 0, 7 },   { 1, 4 }, { 1, 3 },	  { 1, 6 },   { 1, 7 },
+	{ 3, 1 },   { 2, 0 }, { 1, 5 },	  { 2, 6 },   { 2, 7 },
+	{ 2, 1 },   { 2, 4 }, { 2, 5 },	  { 1, 2 },   { 2, 3 },
+	{ 2, 2 },   { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 },
 };
 
 const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 #endif
 
 void board_overcurrent_event(int port, int is_overcurrented)
@@ -330,9 +317,8 @@ __override uint32_t board_override_feature_flags0(uint32_t flags0)
 	/*
 	 * Remove keyboard backlight feature for devices that don't support it.
 	 */
-	if (sku_id == 33 || sku_id == 36 || sku_id == 51 ||
-		sku_id == 52 || sku_id == 53 || sku_id == 55 ||
-		sku_id == 66 || sku_id == 68)
+	if (sku_id == 33 || sku_id == 36 || sku_id == 51 || sku_id == 52 ||
+	    sku_id == 53 || sku_id == 55 || sku_id == 66 || sku_id == 68)
 		return (flags0 & ~EC_FEATURE_MASK_0(EC_FEATURE_PWM_KEYB));
 	else
 		return flags0;
diff --git a/board/bloog/board.h b/board/bloog/board.h
index c472543589..38e8484df2 100644
--- a/board/bloog/board.h
+++ b/board/bloog/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,6 +13,8 @@
 #define VARIANT_OCTOPUS_CHARGER_ISL9238
 #include "baseboard.h"
 
+#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD
+
 #define CONFIG_VOLUME_BUTTONS
 #define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
 #define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
@@ -25,8 +27,8 @@
 #define CONFIG_LED_COMMON
 
 /* Sensors */
-#define CONFIG_ACCEL_KX022		/* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM	/* Base accel */
+#define CONFIG_ACCEL_KX022 /* Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
 
 /* Sensors without hardware FIFO are in forced mode */
 #define CONFIG_ACCEL_FORCE_MODE_MASK (1 << LID_ACCEL)
@@ -57,10 +59,10 @@
 #include "registers.h"
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_AMB,		/* ADC0 */
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC1 */
-	ADC_VBUS_C0,			/* ADC9 */
-	ADC_VBUS_C1,			/* ADC4 */
+	ADC_TEMP_SENSOR_AMB, /* ADC0 */
+	ADC_TEMP_SENSOR_CHARGER, /* ADC1 */
+	ADC_VBUS_C0, /* ADC9 */
+	ADC_VBUS_C1, /* ADC4 */
 	ADC_CH_COUNT
 };
 
@@ -71,37 +73,25 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_COUNT };
 
 /* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
 enum battery_type {
-	BATTERY_DANAPACK_COS,
-	BATTERY_DANAPACK_ATL,
-	BATTERY_DANAPACK_SDI,
+	BATTERY_DYNAPACK_COS,
+	BATTERY_DYNAPACK_ATL,
+	BATTERY_DYNAPACK_SDI,
 	BATTERY_SAMSUNG_SDI,
 	BATTERY_SIMPLO_COS,
 	BATTERY_SIMPLO_ATL,
 	BATTERY_SIMPLO_HIGHPOWER,
 	BATTERY_LGC,
 	BATTERY_COS,
+	BATTERY_COS_2,
 	BATTERY_TYPE_COUNT,
 };
 
-#ifdef CONFIG_KEYBOARD_FACTORY_TEST
-extern const int keyboard_factory_scan_pins[][2];
-extern const int keyboard_factory_scan_pins_used;
-#endif
-
 int board_is_convertible(void);
 
 #endif /* !__ASSEMBLER__ */
diff --git a/board/bloog/build.mk b/board/bloog/build.mk
index 137e208b53..fee77e38b5 100644
--- a/board/bloog/build.mk
+++ b/board/bloog/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/bloog/ec.tasklist b/board/bloog/ec.tasklist
index 6eac78a042..6c56976091 100644
--- a/board/bloog/ec.tasklist
+++ b/board/bloog/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/bloog/gpio.inc b/board/bloog/gpio.inc
index 3ee2f88eb1..f07b380974 100644
--- a/board/bloog/gpio.inc
+++ b/board/bloog/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/bloog/led.c b/board/bloog/led.c
index ba1a865890..914e286741 100644
--- a/board/bloog/led.c
+++ b/board/bloog/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,9 +11,9 @@
 #include "chipset.h"
 #include "ec_commands.h"
 #include "gpio.h"
+#include "hooks.h"
 #include "host_command.h"
 #include "led_common.h"
-#include "hooks.h"
 
 #define BAT_LED_ON 0
 #define BAT_LED_OFF 1
@@ -24,11 +24,9 @@
 #define LED_TICKS_PER_CYCLE 10
 #define LED_ON_TICKS 5
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_LEFT_LED,
-	EC_LED_ID_RIGHT_LED,
-	EC_LED_ID_POWER_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_LEFT_LED,
+					     EC_LED_ID_RIGHT_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -36,18 +34,18 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static void led_set_color_battery(int port, enum led_color color)
 {
 	gpio_set_level(port ? GPIO_LED_AMBER_C1_L : GPIO_LED_AMBER_C0_L,
-		(color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
+		       (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
 	gpio_set_level(port ? GPIO_LED_WHITE_C1_L : GPIO_LED_WHITE_C0_L,
-		(color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF);
+		       (color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF);
 }
 
-void led_set_color_power(enum ec_led_colors color)
+void led_set_color_power(enum led_color color)
 {
 	switch (color) {
 	case LED_OFF:
@@ -101,7 +99,7 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 		break;
 	case EC_LED_ID_POWER_LED:
 		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(EC_LED_COLOR_WHITE);
+			led_set_color_power(LED_WHITE);
 		else
 			led_set_color_power(LED_OFF);
 		break;
@@ -130,7 +128,6 @@ static void led_set_battery(void)
 {
 	static int battery_ticks;
 	static int power_ticks;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
@@ -141,32 +138,34 @@ static void led_set_battery(void)
 	 */
 	if (!board_is_convertible()) {
 		if (chipset_in_state(CHIPSET_STATE_SUSPEND |
-					 CHIPSET_STATE_STANDBY) &&
-			charge_get_state() != PWR_STATE_CHARGE) {
-
+				     CHIPSET_STATE_STANDBY) &&
+		    led_pwr_get_state() != LED_PWRS_CHARGE) {
 			power_ticks++;
 
-			led_set_color_battery(0, power_ticks & 0x4 ?
-						  LED_WHITE : LED_OFF);
-			led_set_color_battery(1, power_ticks & 0x4 ?
-						  LED_WHITE : LED_OFF);
+			led_set_color_battery(0, power_ticks & 0x4 ? LED_WHITE :
+								     LED_OFF);
+			led_set_color_battery(1, power_ticks & 0x4 ? LED_WHITE :
+								     LED_OFF);
 			return;
 		}
 	}
 
 	power_ticks = 0;
 
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
 		/* Always indicate when charging, even in suspend. */
 		set_active_port_color(LED_AMBER);
 		break;
-	case PWR_STATE_DISCHARGE:
+	case LED_PWRS_DISCHARGE:
 		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
 			if (charge_get_percent() < 10)
-				led_set_color_battery(1, (battery_ticks %
-					LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-					LED_WHITE : LED_OFF);
+				led_set_color_battery(
+					1,
+					(battery_ticks % LED_TICKS_PER_CYCLE <
+					 LED_ON_TICKS) ?
+						LED_WHITE :
+						LED_OFF);
 			else
 				led_set_color_battery(1, LED_OFF);
 		}
@@ -174,20 +173,21 @@ static void led_set_battery(void)
 		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
 			led_set_color_battery(0, LED_OFF);
 		break;
-	case PWR_STATE_ERROR:
-		set_active_port_color((battery_ticks & 0x2) ?
-				LED_WHITE : LED_OFF);
+	case LED_PWRS_ERROR:
+		set_active_port_color((battery_ticks & 0x2) ? LED_WHITE :
+							      LED_OFF);
 		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
+	case LED_PWRS_CHARGE_NEAR_FULL:
 		set_active_port_color(LED_WHITE);
 		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			set_active_port_color((battery_ticks %
-				LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-				LED_AMBER : LED_OFF);
-		else
-			set_active_port_color(LED_WHITE);
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		set_active_port_color(LED_WHITE);
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		set_active_port_color(
+			(battery_ticks % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
+				LED_AMBER :
+				LED_OFF);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
@@ -205,9 +205,10 @@ static void led_set_power(void)
 		led_set_color_power(LED_WHITE);
 	else if (chipset_in_state(CHIPSET_STATE_SUSPEND |
 				  CHIPSET_STATE_STANDBY))
-		led_set_color_power((power_tick %
-			LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-			LED_WHITE : LED_OFF);
+		led_set_color_power(
+			(power_tick % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
+				LED_WHITE :
+				LED_OFF);
 	else
 		led_set_color_power(LED_OFF);
 }
diff --git a/board/bloog/vif_override.xml b/board/bloog/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/bloog/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/bobba/battery.c b/board/bobba/battery.c
index e53e839a68..ab77c44062 100644
--- a/board/bobba/battery.c
+++ b/board/bobba/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -277,6 +277,8 @@ const struct board_batt_params board_battery_info[] = {
 				.reg_addr = 0x43,
 				.reg_mask = 0x0001,
 				.disconnect_val = 0x0,
+				.cfet_mask = 0x0002,
+				.cfet_off_val = 0x0,
 			},
 		},
 		.batt_info = {
diff --git a/board/bobba/board.c b/board/bobba/board.c
index c0902ec9ee..64e713a55e 100644
--- a/board/bobba/board.c
+++ b/board/bobba/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,15 +6,17 @@
 /* Bobba board-specific configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "battery.h"
 #include "button.h"
+#include "cbi_ssfc.h"
 #include "charge_manager.h"
 #include "charge_state.h"
 #include "common.h"
 #include "cros_board_info.h"
 #include "driver/accel_kionix.h"
 #include "driver/accelgyro_bmi_common.h"
+#include "driver/accelgyro_icm426xx.h"
+#include "driver/accelgyro_icm_common.h"
 #include "driver/charger/bd9995x.h"
 #include "driver/ppc/nx20p348x.h"
 #include "driver/ppc/syv682x.h"
@@ -38,19 +40,19 @@
 #include "switch.h"
 #include "system.h"
 #include "tablet_mode.h"
-#include "tcpci.h"
+#include "tcpm/tcpci.h"
 #include "temp_sensor.h"
-#include "thermistor.h"
+#include "temp_sensor/thermistor.h"
 #include "usb_charge.h"
 #include "usb_mux.h"
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define USB_PD_PORT_ANX7447	0
-#define USB_PD_PORT_PS8751	1
+#define USB_PD_PORT_ANX7447 0
+#define USB_PD_PORT_PS8751 1
 
 static uint8_t sku_id;
 
@@ -60,17 +62,16 @@ static uint8_t sku_id;
  * that we don't have pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-		{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-		{0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3},
-		{-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0},
-		{1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4},
-		{2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0},
-		{-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1},
-		{-1, -1},
+	{ -1, -1 }, { 0, 5 },	{ 1, 1 }, { 1, 0 },   { 0, 6 },	  { 0, 7 },
+	{ -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 },   { -1, -1 }, { 1, 6 },
+	{ 1, 7 },   { 3, 1 },	{ 2, 0 }, { 1, 5 },   { 2, 6 },	  { 2, 7 },
+	{ 2, 1 },   { 2, 4 },	{ 2, 5 }, { 1, 2 },   { 2, 3 },	  { 2, 2 },
+	{ 3, 0 },   { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 },	  { -1, -1 },
+	{ -1, -1 },
 };
 
 const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 
 /* Check PPC ID Pin and Board ver to decide which one ppc is used. */
 static bool support_syv_ppc(void)
@@ -113,31 +114,31 @@ static void ppc_interrupt(enum gpio_signal signal)
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_AMB] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_AMB] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				  ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_CHARGER] = { "TEMP_CHARGER", NPCX_ADC_CH1,
+				      ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 },
 	/* Vbus sensing (1/10 voltage divider). */
-	[ADC_VBUS_C0] = {
-		"VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
-	[ADC_VBUS_C1] = {
-		"VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
+	[ADC_VBUS_C0] = { "VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT * 10,
+			  ADC_READ_MAX + 1, 0 },
+	[ADC_VBUS_C1] = { "VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT * 10,
+			  ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp,
-				 .idx = 0},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
+	[TEMP_SENSOR_BATTERY] = { .name = "Battery",
+				  .type = TEMP_SENSOR_TYPE_BATTERY,
+				  .read = charge_get_battery_temp,
+				  .idx = 0 },
+	[TEMP_SENSOR_AMBIENT] = { .name = "Ambient",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_51k1_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_AMB },
+	[TEMP_SENSOR_CHARGER] = { .name = "Charger",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_13k7_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_CHARGER },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -147,11 +148,13 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0,  0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+				       { FLOAT_TO_FP(1), 0, 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
+
+const mat33_fp_t base_icm_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				  { 0, FLOAT_TO_FP(-1), 0 },
+				  { 0, 0, FLOAT_TO_FP(1) } };
 
 /*
  * Sparky360 SKU ID 26 has AR Cam, and move base accel/gryo to AR Cam board.
@@ -166,14 +169,15 @@ const mat33_fp_t base_standard_ref = {
  *                                           |0   0.27564   0.96126|
  */
 const mat33_fp_t base_ar_cam_ref = {
-	{ 0, FLOAT_TO_FP(-0.96126), FLOAT_TO_FP(0.27564)},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(0.27564), FLOAT_TO_FP(0.96126)}
+	{ 0, FLOAT_TO_FP(-0.96126), FLOAT_TO_FP(0.27564) },
+	{ FLOAT_TO_FP(1), 0, 0 },
+	{ 0, FLOAT_TO_FP(0.27564), FLOAT_TO_FP(0.96126) }
 };
 
 /* sensor private data */
 static struct kionix_accel_data g_kx022_data;
 static struct bmi_drv_data_t g_bmi160_data;
+static struct icm_drv_data_t g_icm426xx_data;
 
 /* Drivers */
 struct motion_sensor_t motion_sensors[] = {
@@ -262,15 +266,60 @@ struct motion_sensor_t motion_sensors[] = {
 
 unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
+struct motion_sensor_t icm426xx_base_accel = {
+	 .name = "Base Accel",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_ICM426XX,
+	 .type = MOTIONSENSE_TYPE_ACCEL,
+	 .location = MOTIONSENSE_LOC_BASE,
+	 .drv = &icm426xx_drv,
+	 .mutex = &g_base_mutex,
+	 .drv_data = &g_icm426xx_data,
+	 .port = I2C_PORT_SENSOR,
+	 .i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	 .rot_standard_ref = &base_icm_ref,
+	 .default_range = 4,  /* g */
+	 .min_frequency = ICM426XX_ACCEL_MIN_FREQ,
+	 .max_frequency = ICM426XX_ACCEL_MAX_FREQ,
+	 .config = {
+		 /* EC use accel for angle detection */
+		 [SENSOR_CONFIG_EC_S0] = {
+			.odr = 13000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		 },
+		 /* Sensor on for angle detection */
+		 [SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		 },
+	 },
+};
+
+struct motion_sensor_t icm426xx_base_gyro = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &base_icm_ref,
+	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
+	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
+};
+
 static int board_is_convertible(void)
 {
 	/*
 	 * SKU ID of Bobba360, Sparky360, & unprovisioned: 9, 10, 11, 12,
 	 * 25, 26, 27, 255
 	 */
-	return sku_id == 9 || sku_id == 10 || sku_id == 11 || sku_id == 12
-		|| sku_id == 25 || sku_id == 26 || sku_id == 27
-		|| sku_id == 255;
+	return sku_id == 9 || sku_id == 10 || sku_id == 11 || sku_id == 12 ||
+	       sku_id == 25 || sku_id == 26 || sku_id == 27 || sku_id == 255;
 }
 
 static int board_with_ar_cam(void)
@@ -278,10 +327,17 @@ static int board_with_ar_cam(void)
 	/* SKU ID of Sparky360 with AR Cam: 26 */
 	return sku_id == 26;
 }
-
+static int base_gyro_config;
 static void board_update_sensor_config_from_sku(void)
 {
 	if (board_is_convertible()) {
+		base_gyro_config = get_cbi_ssfc_sensor();
+		if (base_gyro_config == SSFC_SENSOR_ICM426XX) {
+			motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
+			motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
+			ccprints("BASE GYRO is ICM426XX");
+		} else
+			ccprints("BASE GYRO is BMI160");
 		motion_sensor_count = ARRAY_SIZE(motion_sensors);
 		/* Enable Base Accel interrupt */
 		gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
@@ -306,6 +362,19 @@ static void board_update_sensor_config_from_sku(void)
 	}
 }
 
+void motion_interrupt(enum gpio_signal signal)
+{
+	switch (base_gyro_config) {
+	case SSFC_SENSOR_ICM426XX:
+		icm426xx_interrupt(signal);
+		break;
+	case SSFC_SENSOR_BMI160:
+	default:
+		bmi160_interrupt(signal);
+		break;
+	}
+}
+
 static int board_has_keypad(void)
 {
 	return sku_id == 41 || sku_id == 42 || sku_id == 43 || sku_id == 44;
@@ -332,8 +401,9 @@ static void board_usb_charge_mode_init(void)
 	int i;
 
 	/*
-	 * Only overriding the USB_DISALLOW_SUSPEND_CHARGE in RO is enough because
-	 * USB_SYSJUMP_TAG preserves the settings to RW. And we should honor to it.
+	 * Only overriding the USB_DISALLOW_SUSPEND_CHARGE in RO is enough
+	 * because USB_SYSJUMP_TAG preserves the settings to RW. And we should
+	 * honor to it.
 	 */
 	if (system_jumped_late())
 		return;
@@ -350,7 +420,7 @@ static void board_usb_charge_mode_init(void)
 	 */
 	for (i = 0; i < CONFIG_USB_PORT_POWER_SMART_PORT_COUNT; i++)
 		usb_charge_set_mode(i, CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE,
-				USB_DISALLOW_SUSPEND_CHARGE);
+				    USB_DISALLOW_SUSPEND_CHARGE);
 }
 /*
  * usb_charge_init() is hooked in HOOK_PRIO_DEFAULT and set inhibit_charge to
@@ -387,15 +457,15 @@ __override uint32_t board_override_feature_flags0(uint32_t flags0)
 }
 
 static const struct ppc_config_t ppc_syv682x_port0 = {
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
+	.i2c_port = I2C_PORT_TCPC0,
+	.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+	.drv = &syv682x_drv,
 };
 
 static const struct ppc_config_t ppc_syv682x_port1 = {
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
+	.i2c_port = I2C_PORT_TCPC1,
+	.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+	.drv = &syv682x_drv,
 };
 
 static void board_setup_ppc(void)
@@ -403,11 +473,9 @@ static void board_setup_ppc(void)
 	if (!support_syv_ppc())
 		return;
 
-	memcpy(&ppc_chips[USB_PD_PORT_TCPC_0],
-	       &ppc_syv682x_port0,
+	memcpy(&ppc_chips[USB_PD_PORT_TCPC_0], &ppc_syv682x_port0,
 	       sizeof(struct ppc_config_t));
-	memcpy(&ppc_chips[USB_PD_PORT_TCPC_1],
-	       &ppc_syv682x_port1,
+	memcpy(&ppc_chips[USB_PD_PORT_TCPC_1], &ppc_syv682x_port1,
 	       sizeof(struct ppc_config_t));
 
 	gpio_set_flags(GPIO_USB_PD_C0_INT_ODL, GPIO_INT_BOTH);
@@ -415,23 +483,22 @@ static void board_setup_ppc(void)
 }
 DECLARE_HOOK(HOOK_INIT, board_setup_ppc, HOOK_PRIO_INIT_I2C + 2);
 
-void board_hibernate_late(void) {
-
+void board_hibernate_late(void)
+{
 	int i;
 
 	const uint32_t hibernate_pins[][2] = {
 		/* Turn off LEDs before going to hibernate */
-		{GPIO_BAT_LED_BLUE_L, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_BAT_LED_ORANGE_L, GPIO_INPUT | GPIO_PULL_UP},
+		{ GPIO_BAT_LED_BLUE_L, GPIO_INPUT | GPIO_PULL_UP },
+		{ GPIO_BAT_LED_ORANGE_L, GPIO_INPUT | GPIO_PULL_UP },
 	};
 
 	for (i = 0; i < ARRAY_SIZE(hibernate_pins); ++i)
 		gpio_set_flags(hibernate_pins[i][0], hibernate_pins[i][1]);
 }
 
-#ifndef TEST_BUILD
 /* This callback disables keyboard when convertibles are fully open */
-void lid_angle_peripheral_enable(int enable)
+__override void lid_angle_peripheral_enable(int enable)
 {
 	/*
 	 * If the lid is in tablet position via other sensors,
@@ -443,7 +510,6 @@ void lid_angle_peripheral_enable(int enable)
 	if (board_is_convertible())
 		keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
 }
-#endif
 
 void board_overcurrent_event(int port, int is_overcurrented)
 {
@@ -455,7 +521,6 @@ void board_overcurrent_event(int port, int is_overcurrented)
 	gpio_set_level(GPIO_USB_C_OC, !is_overcurrented);
 }
 
-
 int ppc_get_alert_status(int port)
 {
 	if (port == 0)
diff --git a/board/bobba/board.h b/board/bobba/board.h
index a26e047d76..2a1be082e8 100644
--- a/board/bobba/board.h
+++ b/board/bobba/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,12 +13,22 @@
 #define VARIANT_OCTOPUS_CHARGER_ISL9238
 #include "baseboard.h"
 
+#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD
+
 /* I2C bus configuraiton */
-#define I2C_PORT_ACCEL	I2C_PORT_SENSOR
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
 
 /* EC console commands  */
-#define CONFIG_CMD_ACCELS
 #define CONFIG_CMD_ACCEL_INFO
+#undef CONFIG_CMD_ACCELSPOOF
+#undef CONFIG_CMD_MFALLOW
+
+/* Reduce flash space usage */
+#define CONFIG_DEBUG_ASSERT_BRIEF
+#define CONFIG_USB_PD_DEBUG_LEVEL 2
+#undef CONFIG_CMD_ADC
+#undef CONFIG_CMD_BATTFAKE
+#undef CONFIG_CMD_CBI
 
 #define CONFIG_LED_COMMON
 
@@ -30,9 +40,10 @@
 #define CONFIG_USB_PD_RESET_MIN_BATT_SOC 2
 
 /* Sensors */
-#define CONFIG_ACCEL_KX022	/* Lid accel */
-#define CONFIG_ACCELGYRO_BMI160	/* Base accel */
-#define CONFIG_SYNC		/* Camera VSYNC */
+#define CONFIG_ACCEL_KX022 /* Lid accel */
+#define CONFIG_ACCELGYRO_BMI160 /* Base accel main source*/
+#define CONFIG_ACCELGYRO_ICM426XX /* Base accel second source*/
+#define CONFIG_SYNC /* Camera VSYNC */
 
 #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
 /* Sensors without hardware FIFO are in forced mode */
@@ -41,9 +52,10 @@
 /* Motion Sense Task Events */
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 
-#define CONFIG_SYNC_INT_EVENT	\
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
+#define CONFIG_SYNC_INT_EVENT TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
 
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_UPDATE
@@ -71,22 +83,29 @@
 #define CONFIG_USBC_PPC_DEDICATED_INT
 #undef CONFIG_SYV682X_HV_ILIM
 #define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_5_50
+/* SYV682 isn't connected to CC, so TCPC must provide VCONN */
+#define CONFIG_USBC_PPC_SYV682X_NO_CC
+
+/*
+ * SMP battery sleep mode time is 5 second.
+ * Change max sleep time from once/min to once/4sec to prevent
+ * battery entering sleeping mode. See b/226259582.
+ */
+#define CHARGE_MAX_SLEEP_USEC (4 * SECOND)
 
 #ifndef __ASSEMBLER__
 
 /* support factory keyboard test */
 #define CONFIG_KEYBOARD_FACTORY_TEST
-extern const int keyboard_factory_scan_pins[][2];
-extern const int keyboard_factory_scan_pins_used;
 
 #include "gpio_signal.h"
 #include "registers.h"
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_AMB,		/* ADC0 */
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC1 */
-	ADC_VBUS_C0,			/* ADC9 */
-	ADC_VBUS_C1,			/* ADC4 */
+	ADC_TEMP_SENSOR_AMB, /* ADC0 */
+	ADC_TEMP_SENSOR_CHARGER, /* ADC1 */
+	ADC_VBUS_C0, /* ADC9 */
+	ADC_VBUS_C1, /* ADC4 */
 	ADC_CH_COUNT
 };
 
@@ -97,19 +116,10 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_COUNT };
 
 /* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	VSYNC,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, VSYNC, SENSOR_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
@@ -127,6 +137,8 @@ enum battery_type {
 	BATTERY_TYPE_COUNT,
 };
 
+void motion_interrupt(enum gpio_signal signal);
+
 #endif /* !__ASSEMBLER__ */
 
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/bobba/build.mk b/board/bobba/build.mk
index 3d04b75731..998a65a3de 100644
--- a/board/bobba/build.mk
+++ b/board/bobba/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/bobba/ec.tasklist b/board/bobba/ec.tasklist
index d98db145e7..977b8b01be 100644
--- a/board/bobba/ec.tasklist
+++ b/board/bobba/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/bobba/gpio.inc b/board/bobba/gpio.inc
index cc69cc2618..f57ea6bf12 100644
--- a/board/bobba/gpio.inc
+++ b/board/bobba/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -37,7 +37,7 @@ GPIO_INT(TABLET_MODE_L,         PIN(8, 6), GPIO_INT_BOTH, gmr_tablet_switch_isr)
 GPIO_INT(EC_VOLUP_BTN_ODL,	PIN(7, 5), GPIO_INT_BOTH, button_interrupt)
 GPIO_INT(EC_VOLDN_BTN_ODL,	PIN(4, 0), GPIO_INT_BOTH, button_interrupt)
 
-GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, bmi160_interrupt)
+GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, motion_interrupt)
 GPIO_INT(WFCAM_VSYNC,		PIN(0, 3), GPIO_INT_RISING , sync_interrupt)
 
 GPIO(LID_ACCEL_INT_L,		PIN(5, 0), GPIO_INPUT | GPIO_SEL_1P8V)
diff --git a/board/bobba/led.c b/board/bobba/led.c
index 6c5ae18272..54227ed107 100644
--- a/board/bobba/led.c
+++ b/board/bobba/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,32 +10,39 @@
 #include "led_common.h"
 #include "led_onoff_states.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
-const int led_charge_lvl_1 = 0;
+__override const int led_charge_lvl_1;
 
-const int led_charge_lvl_2 = 100;
+__override const int led_charge_lvl_2 = 100;
 
 /* Bobba: Note there is only LED for charge / power */
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,  2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
 const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-void led_set_color_battery(enum ec_led_colors color)
+__override void led_set_color_battery(enum ec_led_colors color)
 {
 	switch (color) {
 	case EC_LED_COLOR_BLUE:
@@ -70,4 +77,3 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 
 	return EC_SUCCESS;
 }
-
diff --git a/board/bobba/vif_override.xml b/board/bobba/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/bobba/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/boldar/battery.c b/board/boldar/battery.c
index 9b356a8efd..2b2a9f4842 100644
--- a/board/boldar/battery.c
+++ b/board/boldar/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -62,6 +62,34 @@ const struct board_batt_params board_battery_info[] = {
 			.discharging_max_c	= 75,
 		},
 	},
+	/* LGC AP18C8K Battery Information */
+	[BATTERY_LGC_AP18C8K] = {
+		.fuel_gauge = {
+			.manuf_name = "LGC KT0030G020",
+			.device_name = "AP18C8K",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.reg_addr = 0x43,
+				.reg_mask = 0x0001,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max		= 13050,
+			.voltage_normal		= 11250,
+			.voltage_min		= 9000,
+			.precharge_current	= 256,
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 75,
+		},
+	},
 };
 BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
 
diff --git a/board/boldar/board.c b/board/boldar/board.c
index 1993b241fb..3972c6746a 100644
--- a/board/boldar/board.c
+++ b/board/boldar/board.c
@@ -1,21 +1,20 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Volteer board-specific configuration */
-#include "bb_retimer.h"
-#include "button.h"
-#include "common.h"
 #include "accelgyro.h"
+#include "button.h"
 #include "cbi_ec_fw_config.h"
+#include "common.h"
 #include "driver/accel_bma2x2.h"
 #include "driver/accelgyro_bmi260.h"
 #include "driver/als_tcs3400.h"
 #include "driver/bc12/pi3usb9201.h"
 #include "driver/ppc/sn5s330.h"
 #include "driver/ppc/syv682x.h"
-#include "driver/retimer/bb_retimer.h"
+#include "driver/retimer/bb_retimer_public.h"
 #include "driver/sync.h"
 #include "driver/tcpm/ps8xxx.h"
 #include "driver/tcpm/rt1715.h"
@@ -35,8 +34,8 @@
 #include "pwm_chip.h"
 #include "switch.h"
 #include "system.h"
-#include "task.h"
 #include "tablet_mode.h"
+#include "task.h"
 #include "throttle_ap.h"
 #include "uart.h"
 #include "usb_mux.h"
@@ -46,12 +45,13 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#include "gpio_list.h" /* Must come after other header files. */
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 /* Keyboard scan setting */
-struct keyboard_scan_config keyscan_config = {
+__override struct keyboard_scan_config keyscan_config = {
 	/* Increase from 50 us, because KSO_02 passes through the H1. */
 	.output_settle_us = 80,
 	/* Other values should be the same as the default configuration. */
@@ -82,68 +82,21 @@ static void board_init(void)
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
-__override enum tbt_compat_cable_speed board_get_max_tbt_speed(int port)
-{
-	enum ec_cfg_usb_db_type usb_db = ec_cfg_usb_db_type();
-
-	if (port == USBC_PORT_C1) {
-		if (usb_db == DB_USB4_GEN2) {
-			/*
-			 * Older boards violate 205mm trace length prior
-			 * to connection to the re-timer and only support up
-			 * to GEN2 speeds.
-			 */
-			return TBT_SS_U32_GEN1_GEN2;
-		} else if (usb_db == DB_USB4_GEN3) {
-			return TBT_SS_TBT_GEN3;
-		}
-	}
-
-	/*
-	 * Thunderbolt-compatible mode not supported
-	 *
-	 * TODO (b/147726366): All the USB-C ports need to support same speed.
-	 * Need to fix once USB-C feature set is known for Volteer.
-	 */
-	return TBT_SS_RES_0;
-}
-
-__override bool board_is_tbt_usb4_port(int port)
-{
-	enum ec_cfg_usb_db_type usb_db = ec_cfg_usb_db_type();
-
-	/*
-	 * Volteer reference design only supports TBT & USB4 on port 1
-	 * if the USB4 DB is present.
-	 *
-	 * TODO (b/147732807): All the USB-C ports need to support same
-	 * features. Need to fix once USB-C feature set is known for Volteer.
-	 */
-	return ((port == USBC_PORT_C1)
-		&& ((usb_db == DB_USB4_GEN2) || (usb_db == DB_USB4_GEN3)));
-}
-
 /******************************************************************************/
 /* Physical fans. These are logically separate from pwm_channels. */
 
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
 
-/*
- * Fan specs from datasheet:
- * Max speed 5900 rpm (+/- 7%), minimum duty cycle 30%.
- * Minimum speed not specified by RPM. Set minimum RPM to max speed (with
- * margin) x 30%.
- *    5900 x 1.07 x 0.30 = 1894, round up to 1900
- */
+/* Default */
 const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 1900,
-	.rpm_start = 1900,
-	.rpm_max = 5900,
+	.rpm_min = 3000,
+	.rpm_start = 3000,
+	.rpm_max = 10000,
 };
 
 const struct fan_t fans[FAN_CH_COUNT] = {
@@ -157,51 +110,50 @@ const struct fan_t fans[FAN_CH_COUNT] = {
 /* EC thermal management configuration */
 
 /*
- * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
- * 130 C.  However, sensor is located next to DDR, so we need to use the lower
- * DDR temperature limit (85 C)
+ * TODO(b/202062363): Remove when clang is fixed.
  */
-const static struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(35),
-	.temp_fan_max = C_TO_K(50),
-};
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+		}, \
+		.temp_fan_off = C_TO_K(15), \
+		.temp_fan_max = C_TO_K(50), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 
 /*
  * Inductor limits - used for both charger and PP3300 regulator
  *
  * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
- *
- * Charger max recommended temperature 100C, max absolute temperature 125C
- * PP3300 regulator: operating range -40 C to 145 C
- *
- * Inductors: limit of 125c
- * PCB: limit is 80c
  */
-const static struct ec_thermal_config thermal_inductor = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(55),
-};
-
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_INDUCTOR         \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+		}, \
+		.temp_fan_off = C_TO_K(15), \
+		.temp_fan_max = C_TO_K(55), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_inductor =
+	THERMAL_INDUCTOR;
 
 struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_CHARGER]			= thermal_inductor,
-	[TEMP_SENSOR_2_PP3300_REGULATOR]	= thermal_inductor,
-	[TEMP_SENSOR_3_DDR_SOC]			= thermal_cpu,
-	[TEMP_SENSOR_4_FAN]			= thermal_cpu,
+	[TEMP_SENSOR_1_CHARGER] = THERMAL_INDUCTOR,
+	[TEMP_SENSOR_2_PP3300_REGULATOR] = THERMAL_INDUCTOR,
+	[TEMP_SENSOR_3_DDR_SOC] = THERMAL_CPU,
+	[TEMP_SENSOR_4_FAN] = THERMAL_CPU,
 };
 BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
 
@@ -319,11 +271,10 @@ static const struct tcpc_config_t tcpc_config_p1_usb3 = {
 	.bus_type = EC_BUS_TYPE_I2C,
 	.i2c_info = {
 		.port = I2C_PORT_USB_C1,
-		.addr_flags = PS8751_I2C_ADDR1_FLAGS,
+		.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
 	},
 	.flags = TCPC_FLAGS_TCPCI_REV2_0 | TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V,
 	.drv = &ps8xxx_tcpm_drv,
-	.usb23 = USBC_PORT_1_USB2_NUM | (USBC_PORT_1_USB3_NUM << 4),
 };
 
 /*
@@ -331,24 +282,33 @@ static const struct tcpc_config_t tcpc_config_p1_usb3 = {
  * virtual_usb_mux_driver so the AP gets notified of mux changes and updates
  * the TCSS configuration on state changes.
  */
-static const struct usb_mux usbc1_usb3_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	.next_mux = NULL,
+static const struct usb_mux_chain usbc1_usb3_db_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
+	.next = NULL,
 };
 
-static const struct usb_mux mux_config_p1_usb3_active = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-	.next_mux = &usbc1_usb3_db_retimer,
+static const struct usb_mux_chain mux_config_p1_usb3_active = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+	.next = &usbc1_usb3_db_retimer,
 };
 
-static const struct usb_mux mux_config_p1_usb3_passive = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+static const struct usb_mux_chain mux_config_p1_usb3_passive = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
 
 /******************************************************************************/
@@ -358,16 +318,13 @@ const int usb_port_enable[USB_PORT_COUNT] = {
 	GPIO_EN_PP5000_USBA,
 };
 
-static enum gpio_signal ps8xxx_rst_odl = GPIO_USB_C1_RT_RST_ODL;
-
 static void ps8815_reset(void)
 {
 	int val;
 
-	gpio_set_level(ps8xxx_rst_odl, 0);
-	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS,
-			   PS8815_PWR_H_RST_H_DELAY_MS));
-	gpio_set_level(ps8xxx_rst_odl, 1);
+	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 0);
+	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS));
+	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 1);
 	msleep(PS8815_FW_INIT_DELAY_MS);
 
 	/*
@@ -377,16 +334,16 @@ static void ps8815_reset(void)
 
 	CPRINTS("%s: patching ps8815 registers", __func__);
 
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
+	if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) ==
+	    EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f was %02x", val);
 
-	if (i2c_write8(I2C_PORT_USB_C1,
-		       PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) == EC_SUCCESS)
+	if (i2c_write8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f,
+		       0x31) == EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f set to 0x31");
 
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
+	if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) ==
+	    EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f now %02x", val);
 }
 
@@ -398,7 +355,9 @@ void board_reset_pd_mcu(void)
 	/* Daughterboard specific reset for port 1 */
 	if (usb_db == DB_USB3_ACTIVE) {
 		ps8815_reset();
-		usb_mux_hpd_update(USBC_PORT_C1, 0, 0);
+		usb_mux_hpd_update(USBC_PORT_C1,
+				   USB_PD_MUX_HPD_LVL_DEASSERTED |
+					   USB_PD_MUX_HPD_IRQ_DEASSERTED);
 	}
 }
 
@@ -458,16 +417,6 @@ __override void board_cbi_init(void)
 {
 	enum ec_cfg_usb_db_type usb_db = ec_cfg_usb_db_type();
 
-	/* Reconfigure Volteer GPIOs based on the board ID */
-	if (get_board_id() == 0) {
-		CPRINTS("Configuring GPIOs for board ID 0");
-		CPRINTS("VOLUME_UP button disabled");
-
-		/* Reassign USB_C1_RT_RST_ODL */
-		bb_controls[USBC_PORT_C1].retimer_rst_gpio =
-			GPIO_USB_C1_RT_RST_ODL_BOARDID_0;
-		ps8xxx_rst_odl = GPIO_USB_C1_RT_RST_ODL_BOARDID_0;
-	}
 	config_port_discrete_tcpc(0);
 	switch (usb_db) {
 	case DB_USB_ABSENT:
@@ -526,6 +475,7 @@ void ppc_interrupt(enum gpio_signal signal)
 		break;
 	case GPIO_USB_C1_PPC_INT_ODL:
 		syv682x_interrupt(USBC_PORT_C1);
+		break;
 	default:
 		break;
 	}
@@ -555,7 +505,6 @@ struct tcpc_config_t tcpc_config[] = {
 			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
 		},
 		.drv = &tusb422_tcpm_drv,
-		.usb23 = USBC_PORT_0_USB2_NUM | (USBC_PORT_0_USB3_NUM << 4),
 	},
 	[USBC_PORT_C1] = {
 		.bus_type = EC_BUS_TYPE_I2C,
@@ -564,7 +513,6 @@ struct tcpc_config_t tcpc_config[] = {
 			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
 		},
 		.drv = &tusb422_tcpm_drv,
-		.usb23 = USBC_PORT_1_USB2_NUM | (USBC_PORT_1_USB3_NUM << 4),
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
@@ -572,30 +520,51 @@ BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
 
 /******************************************************************************/
 /* USBC mux configuration - Tiger Lake includes internal mux */
-struct usb_mux usbc1_usb4_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &bb_usb_retimer,
-	.i2c_port = I2C_PORT_USB_1_MIX,
-	.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
+struct usb_mux_chain usbc0_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+struct usb_mux_chain usbc1_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
-struct usb_mux usb_muxes[] = {
+
+struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_1_MIX,
+			.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc0_tcss_usb_mux,
 	},
 	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc1_usb4_db_retimer,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_1_MIX,
+			.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc1_tcss_usb_mux,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
 
 struct bb_usb_control bb_controls[] = {
 	[USBC_PORT_C0] = {
-		/* USB-C port 0 doesn't have a retimer */
+		.usb_ls_en_gpio = GPIO_USB_C0_LS_EN,
+		.retimer_rst_gpio = GPIO_USB_C0_RT_RST_ODL,
 	},
 	[USBC_PORT_C1] = {
 		.usb_ls_en_gpio = GPIO_USB_C1_LS_EN,
diff --git a/board/boldar/board.h b/board/boldar/board.h
index 64efbf82af..f2a76dab82 100644
--- a/board/boldar/board.h
+++ b/board/boldar/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,28 +11,22 @@
 /* Baseboard features */
 #include "baseboard.h"
 
-#ifdef BOARD_VOLTEER_TCPMV1
-/* Disable TCPMv2 configuration options */
-#undef CONFIG_USB_PD_TCPMV2
-
-/* Enable the required TCPMv1 options */
-#define CONFIG_USB_PD_TCPMV1
+/* Optional features */
 
 /*
- * Because the TPCMv1 stack has considerably smaller flash footprint, disable
- * the CONFIG_CHIP_INIT_ROM_REGION for testing of the init_rom API and the
- * BMI260 driver.
+ * The RAM and flash size combination on the the NPCX797FC does not leave
+ * any unused flash space that can be used to store the .init_rom section.
  */
 #undef CONFIG_CHIP_INIT_ROM_REGION
-#endif
 
-/* Optional features */
 #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
 
 #define CONFIG_VBOOT_EFS2
 
 #define CONFIG_POWER_BUTTON
 
+#define CONFIG_HOST_INTERFACE_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST
+
 #undef CONFIG_UART_TX_BUF_SIZE
 #define CONFIG_UART_TX_BUF_SIZE 4096
 
@@ -47,29 +41,28 @@
 /* Keyboard features */
 
 /* Sensors */
-/* BMA253 accelerometer in base */
-#define CONFIG_ACCEL_BMA255
+/* LIS2DH12 Lid accel */
+#define CONFIG_ACCEL_LIS2DH
 
 /* BMI260 accel/gyro in base */
 #define CONFIG_ACCELGYRO_BMI260
 #define CONFIG_ACCELGYRO_BMI260_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 
-/* TCS3400 ALS */
+/* TCS3400 ALS/RGB */
 #define CONFIG_ALS
-#define ALS_COUNT		1
+#define ALS_COUNT 1
 #define CONFIG_ALS_TCS3400
 #define CONFIG_ALS_TCS3400_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS)
 
 /* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
-	(BIT(LID_ACCEL) | BIT(CLEAR_ALS))
+#define CONFIG_ACCEL_FORCE_MODE_MASK (BIT(LID_ACCEL) | BIT(CLEAR_ALS))
 
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE		BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID		LID_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
 
 /* USB Type C and USB PD defines */
 /*
@@ -79,47 +72,36 @@
  */
 #define CONFIG_USB_PID 0x503E
 
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
-
-/*
- * USB-C port's USB2 & USB3 mapping from schematics
- * USB2 numbering on PCH - 1 to n
- * USB3 numbering on AP - 0 to n (PMC's USB3 numbering for MUX
- * configuration is - 1 to n hence add +1)
- */
-#define USBC_PORT_0_USB2_NUM	9
-#define USBC_PORT_0_USB3_NUM	1
-#define USBC_PORT_1_USB2_NUM	4
-#define USBC_PORT_1_USB3_NUM	2
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
 
 /* TODO: b/144165680 - measure and check these values on Volteer */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
 
 /*
  * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
  * cables only support up to 60W.
  */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Enabling Thunderbolt-compatible mode */
 #define CONFIG_USB_PD_TBT_COMPAT_MODE
 
 /* Enabling USB4 mode */
 #define CONFIG_USB_PD_USB4
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x40
+#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x37
+#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x40
 
 /* USB Type A Features */
-#define USB_PORT_COUNT			1
+#define USB_PORT_COUNT 1
 #define CONFIG_USB_PORT_POWER_DUMB
 
 /* USBC PPC*/
-#define CONFIG_USBC_PPC_SN5S330		/* USBC port C0 */
-#define CONFIG_USBC_PPC_SYV682X		/* USBC port C1 */
+#define CONFIG_USBC_PPC_SN5S330 /* USBC port C0 */
+#define CONFIG_USBC_PPC_SYV682X /* USBC port C1 */
 
 /* BC 1.2 */
 
@@ -128,8 +110,8 @@
 /* Fan features */
 
 /* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 
 /*
  * Macros for GPIO signals used in common code that don't match the
@@ -137,46 +119,43 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_DSW_PWROK		GPIO_EC_PCH_DSW_PWROK
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD		GPIO_PG_EC_RSMRST_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
-#define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE_L
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_LID_OPEN GPIO_EC_LID_OPEN
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
 
 /* I2C Bus Configuration */
 #define CONFIG_I2C
-#define I2C_PORT_ACCEL		I2C_PORT_SENSOR
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_1_MIX	NPCX_I2C_PORT3_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT3_0
+#define I2C_PORT_POWER NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
 
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-#define CONFIG_I2C_MASTER
+#define I2C_PORT_BATTERY I2C_PORT_POWER
+#define I2C_PORT_CHARGER I2C_PORT_EEPROM
 
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+#define CONFIG_I2C_CONTROLLER
 
 #ifndef __ASSEMBLER__
 
@@ -185,6 +164,7 @@
 
 enum battery_type {
 	BATTERY_LGC011,
+	BATTERY_LGC_AP18C8K,
 	BATTERY_TYPE_COUNT,
 };
 
@@ -207,11 +187,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 void board_reset_pd_mcu(void);
 
diff --git a/board/boldar/build.mk b/board/boldar/build.mk
index b78172d3cf..c994631759 100644
--- a/board/boldar/build.mk
+++ b/board/boldar/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -8,7 +8,7 @@
 
 CHIP:=npcx
 CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
+CHIP_VARIANT:=npcx7m7fc
 BASEBOARD:=volteer
 
 board-y=board.o
diff --git a/board/boldar/ec.tasklist b/board/boldar/ec.tasklist
index 292de51cdb..c29125d517 100644
--- a/board/boldar/ec.tasklist
+++ b/board/boldar/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,6 +16,7 @@
 	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
 	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
 	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
 	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
 	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
 	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
diff --git a/board/boldar/gpio.inc b/board/boldar/gpio.inc
index d0055671ca..f06541ebbb 100644
--- a/board/boldar/gpio.inc
+++ b/board/boldar/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,7 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
@@ -84,21 +84,16 @@ GPIO(EC_PCH_INT_ODL,           PIN(B, 0), GPIO_ODR_HIGH)
 /* USB and USBC Signals */
 GPIO(EN_PP5000_USBA,		PIN(C, 6), GPIO_OUT_LOW)	/* Enable USB-A charging - all ports */
 GPIO(USB_A_LOW_PWR_OD,		PIN(6, 6), GPIO_ODR_LOW)	/* Don't limit USB-A charging by default - all ports */
-
-/*
- * USB_C1 moved from GPIO32 to GPIO83 on boards with board ID >=1.
- * GPIO83/EN_PP1800_A is DNS on board ID 0 and GPIO32 is N/C on board ID >=1
- * so it's safe to define GPIOs compatible with both designs.
- * TODO (b/149858568): remove board ID=0 support.
- */
-GPIO(USB_C1_RT_RST_ODL_BOARDID_0,	PIN(3, 2), GPIO_ODR_LOW) /* USB_C1 Reset on boards without board ID */
-GPIO(USB_C1_RT_RST_ODL,			PIN(8, 3), GPIO_ODR_LOW) /* USB_C1 Reset on boards board ID >=1 */
-GPIO(USB_C0_OC_ODL,			PIN(B, 1), GPIO_ODR_HIGH)
-GPIO(USB_C1_OC_ODL,			PIN(5, 0), GPIO_ODR_HIGH)
+GPIO(USB_C0_RT_RST_ODL,		PIN(4, 1), GPIO_ODR_LOW)	/* RST to Burnside bridge */
+GPIO(USB_C1_RT_RST_ODL,		PIN(8, 3), GPIO_ODR_LOW)
+GPIO(USB_C0_OC_ODL,		PIN(B, 1), GPIO_ODR_HIGH)
+GPIO(USB_C1_OC_ODL,		PIN(5, 0), GPIO_ODR_HIGH)
 /* There is currently no need to service this interrupt. */
-GPIO(USB_C1_RT_INT_ODL,			PIN(F, 3), GPIO_INPUT)
+GPIO(USB_C0_RT_INT_ODL,		PIN(F, 2), GPIO_INPUT)
+GPIO(USB_C1_RT_INT_ODL,		PIN(F, 3), GPIO_INPUT)
 
 /* Don't have a load switch for retimer */
+UNIMPLEMENTED(USB_C0_LS_EN)
 UNIMPLEMENTED(USB_C1_LS_EN)
 
 /* Misc Signals */
@@ -113,11 +108,8 @@ GPIO(M2_SSD_PLA,		PIN(7, 0), GPIO_INPUT)		/* SSD power-loss acknowledgment */
 GPIO(CCD_MODE_ODL,		PIN(E, 5), GPIO_INPUT)		/* Case Closed Debug Mode */
 GPIO(EC_SLP_S0IX,		PIN(7, 2), GPIO_INPUT | GPIO_PULL_UP)
 
-/* Unused signals */
-GPIO(UNUSED_GPIO41,		PIN(4, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIOF2,		PIN(F, 2), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIO96,		PIN(9, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIO34,		PIN(3, 4), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(CATERR_L,			PIN(3, 4), GPIO_INPUT)		/* Catastrophic error */
+GPIO(EC_ESPI_ALERT_L,		PIN(5, 7), GPIO_INPUT | GPIO_SEL_1P8V)
 
 /*
  * eDP backlight - both PCH and EC have enable pins that must be high
@@ -126,6 +118,9 @@ GPIO(UNUSED_GPIO34,		PIN(3, 4), GPIO_INPUT | GPIO_PULL_UP)
  */
 GPIO(EC_EDP_BL_EN,             PIN(D, 3), GPIO_OUT_HIGH)
 
+/* Unused signals */
+GPIO(UNUSED_GPIO96,             PIN(9, 6), GPIO_INPUT | GPIO_PULL_UP)
+
 /* I2C pins - Alternate function below configures I2C module on these pins */
 GPIO(EC_I2C0_SENSOR_SCL,       PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
 GPIO(EC_I2C0_SENSOR_SDA,       PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
@@ -182,3 +177,6 @@ ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)  /* GPIO00 =
                                                                        GPIO01 = H1_EC_PWR_BTN_ODL
                                                                        GPIO02 = EC_RST_ODL */
 
+/* Temperature sensors */
+ALTERNATE(PIN_MASK(4, BIT(2) | BIT(4) | BIT(5)), 0, MODULE_ADC, 0) /* TEMP_SENSOR1,2,4 */
+ALTERNATE(PIN_MASK(F, BIT(1)), 0, MODULE_ADC, 0) /* TEMP_SENSOR3 */
diff --git a/board/boldar/led.c b/board/boldar/led.c
index 4486bcb912..d2425d13b6 100644
--- a/board/boldar/led.c
+++ b/board/boldar/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -18,17 +18,17 @@ const enum ec_led_id supported_led_ids[] = {
 };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-struct pwm_led led_color_map[] = {
-				/* Red, Green, Blue */
-	[EC_LED_COLOR_RED] =    {  100,   0,     0 },
-	[EC_LED_COLOR_GREEN] =  {    0, 100,     0 },
-	[EC_LED_COLOR_BLUE] =   {    0,   0,   100 },
+struct pwm_led_color_map led_color_map[] = {
+	/* Red, Green, Blue */
+	[EC_LED_COLOR_RED] = { 100, 0, 0 },
+	[EC_LED_COLOR_GREEN] = { 0, 100, 0 },
+	[EC_LED_COLOR_BLUE] = { 0, 0, 100 },
 	/* The green LED seems to be brighter than the others, so turn down
 	 * green from its natural level for these secondary colors.
 	 */
-	[EC_LED_COLOR_YELLOW] = {  100,  70,     0 },
-	[EC_LED_COLOR_WHITE] =  {  100,  70,   100 },
-	[EC_LED_COLOR_AMBER] =  {  100,  20,     0 },
+	[EC_LED_COLOR_YELLOW] = { 100, 70, 0 },
+	[EC_LED_COLOR_WHITE] = { 100, 70, 100 },
+	[EC_LED_COLOR_AMBER] = { 100, 20, 0 },
 };
 
 struct pwm_led pwm_leds[] = {
diff --git a/board/boldar/sensors.c b/board/boldar/sensors.c
index 9e34812131..90c79a8675 100644
--- a/board/boldar/sensors.c
+++ b/board/boldar/sensors.c
@@ -1,21 +1,22 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Volteer family-specific sensor configuration */
-#include "common.h"
 #include "accelgyro.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi_common.h"
+#include "common.h"
+#include "driver/accel_lis2dh.h"
 #include "driver/accelgyro_bmi260.h"
+#include "driver/accelgyro_bmi_common.h"
 #include "driver/als_tcs3400.h"
 #include "driver/sync.h"
-#include "keyboard_scan.h"
+#include "gpio.h"
 #include "hooks.h"
 #include "i2c.h"
-#include "task.h"
+#include "keyboard_scan.h"
 #include "tablet_mode.h"
+#include "task.h"
 #include "util.h"
 
 /******************************************************************************/
@@ -23,8 +24,8 @@
 static struct mutex g_lid_accel_mutex;
 static struct mutex g_base_mutex;
 
-/* BMA253 private data */
-static struct accelgyro_saved_data_t g_bma253_data;
+/* Lid accel private data */
+static struct stprivate_data g_lis2dh_data;
 
 /* BMI260 private data */
 static struct bmi_drv_data_t g_bmi260_data;
@@ -84,33 +85,29 @@ static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
 };
 
 /* Rotation matrix for the lid accelerometer */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+				       { FLOAT_TO_FP(-1), 0, 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
 		.name = "Lid Accel",
 		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
+		.chip = MOTIONSENSE_CHIP_LIS2DH,
 		.type = MOTIONSENSE_TYPE_ACCEL,
 		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
+		.drv = &lis2dh_drv,
 		.mutex = &g_lid_accel_mutex,
-		.drv_data = &g_bma253_data,
+		.drv_data = &g_lis2dh_data,
 		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
+		.i2c_spi_addr_flags = LIS2DH_ADDR0_FLAGS,
 		.rot_standard_ref = &lid_standard_ref,
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
+		.min_frequency = LIS2DH_ODR_MIN_VAL,
+		.max_frequency = LIS2DH_ODR_MAX_VAL,
 		.default_range = 2, /* g, to support tablet mode */
 		.config = {
 			/* EC use accel for angle detection */
@@ -224,22 +221,3 @@ static void baseboard_sensors_init(void)
 	gpio_enable_interrupt(GPIO_EC_IMU_INT_L);
 }
 DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_DEFAULT);
-
-#ifndef TEST_BUILD
-void lid_angle_peripheral_enable(int enable)
-{
-	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
-
-	if (enable) {
-		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
-	} else {
-		/*
-		 * Ensure that the chipset is off before disabling the keyboard.
-		 * When the chipset is on, the EC keeps the keyboard enabled and
-		 * the AP decides whether to ignore input devices or not.
-		 */
-		if (!chipset_in_s0)
-			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
-	}
-}
-#endif
diff --git a/board/boldar/vif_override.xml b/board/boldar/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/boldar/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/boten/battery.c b/board/boten/battery.c
index 3b6304937d..c4b4f9261d 100644
--- a/board/boten/battery.c
+++ b/board/boten/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -41,9 +41,9 @@ const struct board_batt_params board_battery_info[] = {
 				.reg_data = { 0x0000, 0x1000 },
 			},
 			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
+				.reg_addr = 0x00,
+				.reg_mask = 0x0018,
+				.disconnect_val = 0x0000,
 			}
 		},
 		.batt_info = {
@@ -69,9 +69,9 @@ const struct board_batt_params board_battery_info[] = {
 				.reg_data = { 0x0000, 0x1000 },
 			},
 			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
+				.reg_addr = 0x00,
+				.reg_mask = 0x0018,
+				.disconnect_val = 0x0000,
 			}
 		},
 		.batt_info = {
@@ -97,9 +97,9 @@ const struct board_batt_params board_battery_info[] = {
 				.reg_data = { 0x0000, 0x1000 },
 			},
 			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
+				.reg_addr = 0x00,
+				.reg_mask = 0x0018,
+				.disconnect_val = 0x0000,
 			}
 		},
 		.batt_info = {
diff --git a/board/boten/board.c b/board/boten/board.c
index bf7fdb17bf..c352d12f78 100644
--- a/board/boten/board.c
+++ b/board/boten/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,16 +7,17 @@
 
 #include "adc_chip.h"
 #include "button.h"
+#include "cbi_fw_config.h"
 #include "charge_manager.h"
-#include "charge_state_v2.h"
+#include "charge_state.h"
 #include "charger.h"
 #include "driver/accel_lis2dw12.h"
 #include "driver/accelgyro_lsm6dsm.h"
 #include "driver/bc12/pi3usb9201.h"
 #include "driver/charger/isl923x.h"
-#include "driver/temp_sensor/thermistor.h"
 #include "driver/tcpm/raa489000.h"
 #include "driver/tcpm/tcpci.h"
+#include "driver/temp_sensor/thermistor.h"
 #include "driver/usb_mux/it5205.h"
 #include "gpio.h"
 #include "hooks.h"
@@ -31,7 +32,7 @@
 #include "system.h"
 #include "tablet_mode.h"
 #include "task.h"
-#include "tcpci.h"
+#include "tcpm/tcpci.h"
 #include "temp_sensor.h"
 #include "uart.h"
 #include "usb_charge.h"
@@ -39,21 +40,50 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define INT_RECHECK_US 5000
+
+/* C0 interrupt line shared by BC 1.2 and charger */
+static void check_c0_line(void);
+DECLARE_DEFERRED(check_c0_line);
 
 static void hdmi_hpd_interrupt(enum gpio_signal s)
 {
 	gpio_set_level(GPIO_USB_C1_DP_HPD, !gpio_get_level(s));
 }
 
-static void usb_c0_interrupt(enum gpio_signal s)
+static void notify_c0_chips(void)
 {
 	/*
 	 * The interrupt line is shared between the TCPC and BC 1.2 detection
-	 * chip.
+	 * chip.  Therefore we'll need to check both ICs.
 	 */
 	schedule_deferred_pd_interrupt(0);
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+
+static void check_c0_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		notify_c0_chips();
+		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+	}
+}
+
+static void usb_c0_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c0_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c0_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
 }
 
 static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
@@ -62,39 +92,74 @@ static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
 	pd_handle_cc_overvoltage(0);
 }
 
+/**
+ * Deferred function to handle pen detect change
+ */
+static void pendetect_deferred(void)
+{
+	static int debounced_pen_detect;
+	int pen_detect = !gpio_get_level(GPIO_PEN_DET_ODL);
+
+	if (pen_detect == debounced_pen_detect)
+		return;
+
+	debounced_pen_detect = pen_detect;
+
+	gpio_set_level(GPIO_EN_PP5000_PEN, debounced_pen_detect);
+	gpio_set_level(GPIO_PEN_DET_PCH, !debounced_pen_detect);
+}
+DECLARE_DEFERRED(pendetect_deferred);
+
+void pen_detect_interrupt(enum gpio_signal s)
+{
+	/* Trigger deferred notification of pen detect change */
+	hook_call_deferred(&pendetect_deferred_data, 500 * MSEC);
+}
+
+void board_hibernate(void)
+{
+	/*
+	 * Charger IC need to be put into their "low power mode" before
+	 * entering the Z-state.
+	 */
+	raa489000_hibernate(0, false);
+}
+
+__override void board_pulse_entering_rw(void)
+{
+	/*
+	 * On the ITE variants, the EC_ENTERING_RW signal was connected to a pin
+	 * which is active high by default.  This causes Cr50 to think that the
+	 * EC has jumped to its RW image even though this may not be the case.
+	 * The pin is changed to GPIO_EC_ENTERING_RW2.
+	 */
+	gpio_set_level(GPIO_EC_ENTERING_RW, 1);
+	gpio_set_level(GPIO_EC_ENTERING_RW2, 1);
+	usleep(MSEC);
+	gpio_set_level(GPIO_EC_ENTERING_RW, 0);
+	gpio_set_level(GPIO_EC_ENTERING_RW2, 0);
+}
+
 /* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH0
-	},
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH2
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH3
-	},
-	[ADC_SUB_ANALOG] = {
-		.name = "SUB_ANALOG",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH13
-	},
+	[ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH0 },
+	[ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH2 },
+	[ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH3 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
@@ -130,31 +195,22 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 };
 
 /* USB Muxes */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+			},
 	},
 };
 
-void board_init(void)
-{
-	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C0_CCSBU_OVP_ODL);
-	/* Enable gpio interrupt for base accelgyro sensor */
-	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-	gpio_enable_interrupt(GPIO_HDMI_HPD_SUB_ODL);
-
-	gpio_set_level(GPIO_HDMI_EN_SUB_ODL, 0);
-
-	/* Set LEDs luminance */
-	pwm_set_duty(PWM_CH_LED_RED, 70);
-	pwm_set_duty(PWM_CH_LED_GREEN, 70);
-	pwm_set_duty(PWM_CH_LED_WHITE, 70);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+/* USB-A charging control */
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_USB_A0_VBUS,
+};
 
 void board_reset_pd_mcu(void)
 {
@@ -188,16 +244,12 @@ uint16_t tcpc_get_alert_status(void)
 	return status;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
-			    int charge_mv)
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
 {
-	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
+	if (port < 0 || port > board_get_usb_pd_port_count())
+		return;
 
-	/*
-	 * TODO(b/151955431): Characterize the input current limit in case a
-	 * scaling needs to be applied here
-	 */
-	charge_set_input_current_limit(icl, charge_mv);
+	raa489000_set_output_current(port, rp);
 }
 
 int board_is_sourcing_vbus(int port)
@@ -206,7 +258,6 @@ int board_is_sourcing_vbus(int port)
 
 	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
 	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
-
 }
 
 int board_set_active_charge_port(int port)
@@ -218,9 +269,8 @@ int board_set_active_charge_port(int port)
 
 	/* Disable all ports. */
 	if (port == CHARGE_PORT_NONE) {
-		tcpc_write(0, TCPC_REG_COMMAND,
-				TCPC_REG_COMMAND_SNK_CTRL_LOW);
-
+		tcpc_write(0, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
+		raa489000_enable_asgate(0, false);
 		return EC_SUCCESS;
 	}
 
@@ -231,8 +281,8 @@ int board_set_active_charge_port(int port)
 	}
 
 	/* Enable requested charge port. */
-	if (tcpc_write(0, TCPC_REG_COMMAND,
-		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
+	if (raa489000_enable_asgate(port, true) ||
+	    tcpc_write(0, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
 		CPRINTUSB("p%d: sink path enable failed.", port);
 		return EC_ERROR_UNKNOWN;
 	}
@@ -273,6 +323,15 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
+/* Matrices to rotate accelerometers into the standard reference. */
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
+
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, FLOAT_TO_FP(1), 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
+
 /* Sensor Data */
 static struct stprivate_data g_lis2dwl_data;
 static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
@@ -290,7 +349,7 @@ struct motion_sensor_t motion_sensors[] = {
 		.drv_data = &g_lis2dwl_data,
 		.port = I2C_PORT_SENSOR,
 		.i2c_spi_addr_flags = LIS2DWL_ADDR1_FLAGS,
-		.rot_standard_ref = NULL,
+		.rot_standard_ref = &lid_standard_ref,
 		.default_range = 2, /* g */
 		.min_frequency = LIS2DW12_ODR_MIN_VAL,
 		.max_frequency = LIS2DW12_ODR_MAX_VAL,
@@ -313,11 +372,9 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_base_mutex,
 		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
 				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
 		.port = I2C_PORT_SENSOR,
 		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.rot_standard_ref = NULL,
+		.rot_standard_ref = &base_standard_ref,
 		.default_range = 4,  /* g */
 		.min_frequency = LSM6DSM_ODR_MIN_VAL,
 		.max_frequency = LSM6DSM_ODR_MAX_VAL,
@@ -342,35 +399,83 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_base_mutex,
 		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
 				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
 		.port = I2C_PORT_SENSOR,
 		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
 		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
-		.rot_standard_ref = NULL,
+		.rot_standard_ref = &base_standard_ref,
 		.min_frequency = LSM6DSM_ODR_MIN_VAL,
 		.max_frequency = LSM6DSM_ODR_MAX_VAL,
 	},
 };
 
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+void board_init(void)
+{
+	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C0_CCSBU_OVP_ODL);
+	gpio_enable_interrupt(GPIO_HDMI_HPD_SUB_ODL);
+	if (get_cbi_fw_config_tablet_mode() == TABLET_MODE_PRESENT) {
+		motion_sensor_count = ARRAY_SIZE(motion_sensors);
+		/* Enable gpio interrupt for base accelgyro sensor */
+		gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
+
+		/* Enable gpio interrupt for pen detect */
+		gpio_enable_interrupt(GPIO_PEN_DET_ODL);
+
+		/* Make sure pen detection is triggered or not at sysjump */
+		if (!gpio_get_level(GPIO_PEN_DET_ODL))
+			gpio_set_level(GPIO_EN_PP5000_PEN, 1);
+
+		if (gpio_get_level(GPIO_PEN_DET_ODL))
+			gpio_set_level(GPIO_PEN_DET_PCH, 1);
+	} else {
+		motion_sensor_count = 0;
+		gmr_tablet_switch_disable();
+		/* Base accel is not stuffed, don't allow line to float */
+		gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L,
+			       GPIO_INPUT | GPIO_PULL_DOWN);
+
+		/* only clamshell sku todo */
+		gpio_set_flags(GPIO_PEN_DET_ODL, GPIO_INPUT | GPIO_PULL_DOWN);
+		gpio_set_flags(GPIO_PEN_DET_PCH, GPIO_INPUT | GPIO_PULL_DOWN);
+		gpio_set_flags(GPIO_EN_PP5000_PEN, GPIO_INPUT | GPIO_PULL_DOWN);
+		gpio_set_flags(GPIO_LID_360_L, GPIO_INPUT | GPIO_PULL_DOWN);
+		gpio_set_flags(GPIO_VOLUP_BTN_ODL, GPIO_INPUT | GPIO_PULL_DOWN);
+		gpio_set_flags(GPIO_VOLDN_BTN_ODL, GPIO_INPUT | GPIO_PULL_DOWN);
+		button_disable_gpio(BUTTON_VOLUME_UP);
+		button_disable_gpio(BUTTON_VOLUME_DOWN);
+	}
+
+	/* Set LEDs luminance */
+	pwm_set_duty(PWM_CH_LED_RED, 70);
+	pwm_set_duty(PWM_CH_LED_GREEN, 70);
+	pwm_set_duty(PWM_CH_LED_WHITE, 70);
+
+	/*
+	 * If interrupt lines are already low, schedule them to be processed
+	 * after inits are completed.
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL))
+		hook_call_deferred(&check_c0_line_data, 0);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
 /* Thermistors */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
-#ifndef TEST_BUILD
 /* This callback disables keyboard when convertibles are fully open */
-void lid_angle_peripheral_enable(int enable)
+__override void lid_angle_peripheral_enable(int enable)
 {
 	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
 
@@ -394,4 +499,3 @@ void lid_angle_peripheral_enable(int enable)
 			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
 	}
 }
-#endif
diff --git a/board/boten/board.h b/board/boten/board.h
index f8ce11b817..f429d7c942 100644
--- a/board/boten/board.h
+++ b/board/boten/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,11 +12,11 @@
 #define VARIANT_DEDEDE_EC_IT8320
 #include "baseboard.h"
 
-/* System unlocked in early development */
-#define CONFIG_SYSTEM_UNLOCKED
-
 /* Battery */
 #define CONFIG_BATTERY_FUEL_GAUGE
+#define CONFIG_BATTERY_V2
+#define CONFIG_BATTERY_COUNT 1
+#define CONFIG_HOSTCMD_BATTERY_V2
 
 /* BC 1.2 */
 #define CONFIG_BC12_DETECT_PI3USB9201
@@ -24,27 +24,38 @@
 /* Charger */
 #define CONFIG_CHARGE_RAMP_HW
 #define CONFIG_CHARGER_RAA489000
+#define PD_MAX_VOLTAGE_MV 20000
 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 #define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */
+#define CONFIG_OCPC_DEF_RBATT_MOHMS               \
+	22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \
+	    */
+#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
+#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
+/*
+ * b/147463641: The charger IC seems to overdraw ~4%, therefore we
+ * reduce our target accordingly.
+ */
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 4
 
 /* DAC for PSYS */
 #define CONFIG_DAC
 
 /* LED */
-#define CONFIG_LED_POWER_LED
 #define CONFIG_LED_ONOFF_STATES
 
 /* PWM */
 #define CONFIG_PWM
 
 /* Sensors */
-#define CONFIG_ACCEL_LIS2DWL		/* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM	/* Base accel */
+#define CONFIG_ACCEL_LIS2DWL /* Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
+#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 /* Sensors without hardware FIFO are in forced mode */
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
 
-#define CONFIG_ACCEL_INTERRUPTS
 /* Enable sensor fifo, must also define the _SIZE and _THRES */
 #define CONFIG_ACCEL_FIFO
 /* Power of 2 - Too large of a fifo causes too much timestamp jitter */
@@ -70,6 +81,11 @@
 #define CONFIG_USB_PD_DISCHARGE_TCPC
 #define CONFIG_USB_PD_TCPC_LOW_POWER
 
+/* EC console commands */
+#define CONFIG_CMD_TCPC_DUMP
+#define CONFIG_CMD_ACCELS
+#define CONFIG_CMD_ACCEL_INFO
+
 /* Variant references the TCPCs to determine Vbus sourcing */
 #define CONFIG_USB_PD_5V_EN_CUSTOM
 
@@ -77,11 +93,17 @@
 #define CONFIG_TEMP_SENSOR
 #define CONFIG_THERMISTOR
 #define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_PP3300_A
 
 /* USB Mux */
 #define CONFIG_USB_MUX_IT5205
 
+/* USB Type A Features */
+#define USB_PORT_COUNT 1
+#define CONFIG_USB_PORT_POWER_DUMB
+
+#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
+#define CONFIG_BUTTONS_RUNTIME_CONFIG
+
 #ifndef __ASSEMBLER__
 
 #include "gpio_signal.h"
@@ -96,27 +118,17 @@ enum pwm_channel {
 };
 
 /* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
 /* ADC channels */
 enum adc_channel {
-	ADC_VSNS_PP3300_A,     /* ADC0 */
-	ADC_TEMP_SENSOR_1,     /* ADC2 */
-	ADC_TEMP_SENSOR_2,     /* ADC3 */
-	ADC_SUB_ANALOG,        /* ADC13 */
+	ADC_VSNS_PP3300_A, /* ADC0 */
+	ADC_TEMP_SENSOR_1, /* ADC2 */
+	ADC_TEMP_SENSOR_2, /* ADC3 */
 	ADC_CH_COUNT
 };
 
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_COUNT
-};
+enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
@@ -126,7 +138,7 @@ enum battery_type {
 	BATTERY_TYPE_COUNT,
 };
 
-int board_is_sourcing_vbus(int port);
+void pen_detect_interrupt(enum gpio_signal s);
 
 #endif /* !__ASSEMBLER__ */
 
diff --git a/board/boten/build.mk b/board/boten/build.mk
index 00e4e0bb5d..9b862c7624 100644
--- a/board/boten/build.mk
+++ b/board/boten/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -11,5 +11,5 @@ CHIP_FAMILY:=it8320
 CHIP_VARIANT:=it8320dx
 BASEBOARD:=dedede
 
-board-y=board.o led.o usb_pd_policy.o
+board-y=board.o cbi_ssfc.o led.o usb_pd_policy.o
 board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/boten/cbi_ssfc.c b/board/boten/cbi_ssfc.c
new file mode 100644
index 0000000000..81f3ee0dad
--- /dev/null
+++ b/board/boten/cbi_ssfc.c
@@ -0,0 +1,36 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi_ssfc.h"
+#include "common.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "hooks.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+/* Cache SSFC on init since we don't expect it to change in runtime */
+static union dedede_cbi_ssfc cached_ssfc;
+BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
+
+static void cbi_ssfc_init(void)
+{
+	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
+		/* Default to 0 when CBI isn't populated */
+		cached_ssfc.raw_value = 0;
+
+	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
+}
+DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
+
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
+{
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
+}
+
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
+{
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
+}
diff --git a/board/boten/cbi_ssfc.h b/board/boten/cbi_ssfc.h
new file mode 100644
index 0000000000..bf8853a43a
--- /dev/null
+++ b/board/boten/cbi_ssfc.h
@@ -0,0 +1,59 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _DEDEDE_CBI_SSFC__H_
+#define _DEDEDE_CBI_SSFC__H_
+
+#include "stdint.h"
+
+/****************************************************************************
+ * Dedede CBI Second Source Factory Cache
+ */
+
+/*
+ * Base Sensor (Bits 0-2)
+ */
+enum ec_ssfc_base_sensor {
+	SSFC_SENSOR_BASE_DEFAULT = 0,
+	SSFC_SENSOR_BMI160 = 1,
+	SSFC_SENSOR_ICM426XX = 2,
+	SSFC_SENSOR_LSM6DSM = 3,
+	SSFC_SENSOR_ICM42607 = 4
+};
+
+/*
+ * Lid Sensor (Bits 3-5)
+ */
+enum ec_ssfc_lid_sensor {
+	SSFC_SENSOR_LID_DEFAULT = 0,
+	SSFC_SENSOR_BMA255 = 1,
+	SSFC_SENSOR_KX022 = 2,
+	SSFC_SENSOR_LIS2DWL = 3
+};
+
+union dedede_cbi_ssfc {
+	struct {
+		uint32_t base_sensor : 3;
+		uint32_t lid_sensor : 3;
+		uint32_t reserved_2 : 26;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Get the Base sensor type from SSFC_CONFIG.
+ *
+ * @return the Base sensor board type.
+ */
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
+
+/**
+ * Get the Lid sensor type from SSFC_CONFIG.
+ *
+ * @return the Lid sensor board type.
+ */
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
+
+#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/boten/ec.tasklist b/board/boten/ec.tasklist
index e1fd188d7c..e610e8ad33 100644
--- a/board/boten/ec.tasklist
+++ b/board/boten/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,12 +11,12 @@
 	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
 	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
 	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, TRENTA_TASK_STACK_SIZE) \
 	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
 	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
 	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, ULTRA_TASK_STACK_SIZE) \
 	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
 	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE)
diff --git a/board/boten/gpio.inc b/board/boten/gpio.inc
index d355338bee..4c9890441d 100644
--- a/board/boten/gpio.inc
+++ b/board/boten/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -80,27 +80,26 @@ GPIO(EC_I2C_USB_C0_SCL,		PIN(A, 4), GPIO_INPUT)
 GPIO(EC_I2C_USB_C0_SDA,		PIN(A, 5), GPIO_INPUT)
 
 /* USB pins */
-GPIO(EN_USB_A0_VBUS,		PIN(L, 6), GPIO_OUT_HIGH)
+GPIO(EN_USB_A0_VBUS,		PIN(L, 6), GPIO_OUT_LOW)
 GPIO(EN_USB_A1_VBUS,		PIN(E, 6), GPIO_OUT_LOW)
 GPIO(EC_AP_USB_C0_HPD,		PIN(L, 4), GPIO_OUT_LOW)
 GPIO(EC_AP_USB_C1_HDMI_HPD,	PIN(K, 7), GPIO_OUT_LOW)
 GPIO(HDMI_SEL_L,		PIN(C, 6), GPIO_OUT_LOW)
-GPIO(HDMI_EN_SUB_ODL,		PIN(E, 0), GPIO_OUT_HIGH)
 
 /* MKBP event synchronization */
 GPIO(EC_AP_MKBP_INT_L,	PIN(L, 5), GPIO_ODR_HIGH)
 
 /* Misc pins which will run to the I/O board */
-GPIO(EC_SUB_IO_1_1, PIN(L, 3), GPIO_INPUT)
-GPIO(EC_SUB_IO_1_2, PIN(F, 0), GPIO_INPUT)
 
 /* Misc */
-GPIO(EN_BL_OD,			PIN(K, 4), GPIO_OUT_LOW)
+GPIO(EN_BL_OD,			PIN(K, 4), GPIO_ODR_LOW)
 GPIO(EC_ENTERING_RW,		PIN(G, 0), GPIO_OUT_LOW)
-GPIO(CCD_MODE_ODL,		PIN(H, 5), GPIO_INPUT)
+GPIO(EC_ENTERING_RW2,		PIN(C, 7), GPIO_OUT_LOW)
+GPIO(CCD_MODE_ODL,		PIN(H, 5), GPIO_ODR_HIGH)
 GPIO(EC_BATTERY_PRES_ODL,	PIN(I, 4), GPIO_INPUT)
-GPIO(PEN_DET_ODL,		PIN(J, 1), GPIO_INPUT | GPIO_PULL_UP)
+GPIO_INT(PEN_DET_ODL,		PIN(J, 1), GPIO_INT_BOTH | GPIO_PULL_UP, pen_detect_interrupt)
 GPIO(EN_PP5000_PEN,	    	PIN(B, 5), GPIO_OUT_LOW)
+GPIO(PEN_DET_PCH,	    	PIN(F, 1), GPIO_OUT_LOW)
 GPIO(EN_KB_BL,			PIN(J, 3), GPIO_OUT_LOW) /* Currently unused */
 GPIO(ECH1_PACKET_MODE,		PIN(H, 1), GPIO_OUT_LOW)
 
@@ -108,8 +107,8 @@ GPIO(ECH1_PACKET_MODE,		PIN(H, 1), GPIO_OUT_LOW)
 GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_DOWN)
 GPIO(GPIOC3_NC, PIN(C, 3), GPIO_INPUT | GPIO_PULL_DOWN)
 GPIO(GPIOC4_NC, PIN(C, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOC7_NC, PIN(C, 7), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOF1_NC, PIN(F, 1), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOE0_NC, PIN(E, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOF0_NC, PIN(F, 0), GPIO_INPUT | GPIO_PULL_DOWN)
 GPIO(GPIOF4_NC, PIN(F, 4), GPIO_INPUT | GPIO_PULL_DOWN)
 GPIO(GPIOF5_NC, PIN(F, 5), GPIO_INPUT | GPIO_PULL_DOWN)
 GPIO(GPIOG3_NC, PIN(G, 3), GPIO_INPUT | GPIO_PULL_DOWN)
@@ -122,7 +121,9 @@ GPIO(GPIOH6_NC, PIN(H, 6), GPIO_INPUT | GPIO_PULL_DOWN)
 GPIO(GPIOJ4_NC, PIN(J, 4), GPIO_INPUT | GPIO_PULL_DOWN)
 GPIO(GPIOJ5_NC, PIN(J, 5), GPIO_INPUT | GPIO_PULL_DOWN)
 GPIO(GPIOJ6_NC, PIN(J, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOL0_NC, PIN(L, 0), GPIO_INPUT | GPIO_PULL_DOWN)
 GPIO(GPIOL2_NC, PIN(L, 2), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOL3_NC, PIN(L, 3), GPIO_INPUT | GPIO_PULL_DOWN)
 GPIO(GPIOM6_NC, PIN(M, 6), GPIO_INPUT | GPIO_PULL_DOWN)
 
 /* Alternate functions GPIO definitions */
@@ -136,7 +137,6 @@ ALTERNATE(PIN_MASK(F, BIT(6) | BIT(7)), 0, MODULE_I2C, GPIO_SEL_1P8V)	/* I2C2 -
 ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), 0, MODULE_I2C, 0)		/* I2C5 */
 
 /* ADC */
-ALTERNATE(PIN_MASK(L, BIT(0)), 0, MODULE_ADC, 0)			/* ADC13: EC_SUB_ANALOG */
 ALTERNATE(PIN_MASK(I, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0)	/* ADC0: EC_VSNS_PP3300_A, ADC2: TEMP_SENSOR_1, ADC3: TEMP_SENSOR_2 */
 
 /* DAC */
diff --git a/board/boten/led.c b/board/boten/led.c
index fe0a03e8db..c61ffba6fe 100644
--- a/board/boten/led.c
+++ b/board/boten/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -6,48 +6,55 @@
  */
 
 #include "common.h"
-#include "led_onoff_states.h"
-#include "led_common.h"
 #include "gpio.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
 #include "pwm.h"
 
-#define LED_OFF_LVL	0
-#define LED_ON_LVL	1
+#define LED_OFF_LVL 0
+#define LED_ON_LVL 1
 
-const int led_charge_lvl_1 = 5;
+__override const int led_charge_lvl_1 = 5;
 
-const int led_charge_lvl_2 = 97;
+__override const int led_charge_lvl_2 = 97;
 
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED,   LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,   1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
 
-const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]            = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]    = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-					 {LED_OFF,         0.5 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF,            LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF,            LED_INDEFINITE} },
-};
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 3 * LED_ONE_SEC },
+					       { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    3 * LED_ONE_SEC },
+						  { LED_OFF,
+						    0.5 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-void led_set_color_power(enum ec_led_colors color)
+__override void led_set_color_power(enum ec_led_colors color)
 {
 	if (color == EC_LED_COLOR_WHITE)
 		pwm_enable(PWM_CH_LED_WHITE, LED_ON_LVL);
@@ -55,7 +62,7 @@ void led_set_color_power(enum ec_led_colors color)
 		pwm_enable(PWM_CH_LED_WHITE, LED_OFF_LVL);
 }
 
-void led_set_color_battery(enum ec_led_colors color)
+__override void led_set_color_battery(enum ec_led_colors color)
 {
 	switch (color) {
 	case EC_LED_COLOR_RED:
diff --git a/board/boten/usb_pd_policy.c b/board/boten/usb_pd_policy.c
index 47acd5e67e..74167850ee 100644
--- a/board/boten/usb_pd_policy.c
+++ b/board/boten/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,12 +9,12 @@
 #include "chipset.h"
 #include "common.h"
 #include "console.h"
-#include "driver/charger/sm5803.h"
+#include "driver/charger/isl923x_public.h"
 #include "driver/tcpm/tcpci.h"
 #include "usb_pd.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
@@ -30,11 +30,6 @@ void pd_power_supply_reset(int port)
 	/* Disable VBUS */
 	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
 
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	/* Give back the current quota we are no longer using */
-	charge_manager_source_port(port, 0);
-#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
-
 	/* Notify host of power info change. */
 	pd_send_host_event(PD_EVENT_POWER_CHANGE);
 }
@@ -60,10 +55,9 @@ int pd_set_power_supply_ready(int port)
 	if (rv)
 		return rv;
 
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	/* Ensure we advertise the proper available current quota */
-	charge_manager_source_port(port, 1);
-#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
+	rv = raa489000_enable_asgate(port, true);
+	if (rv)
+		return rv;
 
 	/* Notify host of power info change. */
 	pd_send_host_event(PD_EVENT_POWER_CHANGE);
@@ -73,8 +67,5 @@ int pd_set_power_supply_ready(int port)
 
 int pd_snk_is_vbus_provided(int port)
 {
-	int regval = 0;
-
-	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
-	return regval & TCPC_REG_POWER_STATUS_VBUS_PRES;
+	return pd_check_vbus_level(port, VBUS_PRESENT);
 }
diff --git a/board/boten/vif_override.xml b/board/boten/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/boten/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/boxy/board.c b/board/boxy/board.c
new file mode 100644
index 0000000000..a0f8dd6683
--- /dev/null
+++ b/board/boxy/board.c
@@ -0,0 +1,333 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Boxy board-specific configuration */
+
+#include "adc_chip.h"
+#include "board.h"
+#include "button.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "driver/ppc/syv682x_public.h"
+#include "driver/tcpm/it83xx_pd.h"
+#include "driver/temp_sensor/thermistor.h"
+#include "driver/usb_mux/it5205.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "intc.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "switch.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "tcpm/tcpci.h"
+#include "temp_sensor.h"
+#include "uart.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_ppc.h"
+
+#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	[ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH0 },
+	[ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH2 },
+	[ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH3 },
+	[ADC_VBUS] = { .name = "VBUS", /* 113/1113 voltage divider */
+		       .factor_mul = ADC_MAX_MVOLT * 1113,
+		       .factor_div = (ADC_READ_MAX + 1) * 113,
+		       .shift = 0,
+		       .channel = CHIP_ADC_CH4 },
+	[ADC_TEMP_SENSOR_3] = { .name = "TEMP_SENSOR3",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH13 },
+	[ADC_PPVAR_PWR_IN_IMON] = { .name = "ADC_PPVAR_PWR_IN_IMON",
+				    .factor_mul = ADC_MAX_MVOLT,
+				    .factor_div = ADC_READ_MAX + 1,
+				    .shift = 0,
+				    .channel = CHIP_ADC_CH15 },
+	[ADC_SNS_PPVAR_PWR_IN] = { .name = "ADC_SNS_PPVAR_PWR_IN",
+				   .factor_mul = ADC_MAX_MVOLT,
+				   .factor_div = ADC_READ_MAX + 1,
+				   .shift = 0,
+				   .channel = CHIP_ADC_CH16 },
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* TCPCs */
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_EMBEDDED,
+		.drv = &it83xx_tcpm_drv,
+	},
+};
+
+/* PPCs */
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.drv = &syv682x_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
+
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/* USB Muxes */
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+			},
+	},
+};
+
+/* USB-A ports */
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_USB_A0_VBUS,
+	GPIO_EN_USB_A1_VBUS,
+};
+
+/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_LED_RED] = {
+		.channel = 1,
+		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
+		.freq_hz = 2400,
+	},
+
+	[PWM_CH_LED_GREEN] = {
+		.channel = 2,
+		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
+		.freq_hz = 2400,
+	},
+
+	[PWM_CH_LED_BLUE] = {
+		.channel = 3,
+		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
+		.freq_hz = 2400,
+	}
+
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+/* Thermistors */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "SoC power",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+void board_init(void)
+{
+	/* Enable PPC interrupt */
+	gpio_enable_interrupt(GPIO_USB_C0_FAULT_L);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * Nothing to do.  TCPC C0 is internal.
+	 */
+}
+
+__override void board_power_5v_enable(int enable)
+{
+	/*
+	 * Nothing to do. 5V should always be enabled while in Z1 or above.
+	 */
+}
+
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
+{
+	int insufficient_power =
+		(charge_ma * charge_mv) <
+		(CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON * 1000);
+	/* TODO(b/259467280) blink LED on error */
+	(void)insufficient_power;
+}
+
+int board_vbus_source_enabled(int port)
+{
+	if (port != CHARGE_PORT_TYPEC0)
+		return 0;
+
+	return ppc_is_sourcing_vbus(port);
+}
+
+/* Vconn control for integrated ITE TCPC */
+void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
+{
+	/*
+	 * We ignore the cc_pin and PPC vconn because polarity and PPC vconn
+	 * should already be set correctly in the PPC driver via the pd
+	 * state machine.
+	 */
+}
+
+/******************************************************************************/
+/*
+ * Since boxy has no battery, it must source all of its power from either
+ * USB-C or the barrel jack (preferred). Fizz operates in continuous safe
+ * mode (charge_manager_leave_safe_mode() will never be called), which
+ * modifies port selection as follows:
+ *
+ * - Dual-role / dedicated capability of the port partner is ignored.
+ * - Charge ceiling on PD voltage transition is ignored.
+ * - CHARGE_PORT_NONE will never be selected.
+ */
+
+int board_set_active_charge_port(int port)
+{
+	const int active_port = charge_manager_get_active_charge_port();
+
+	CPRINTUSB("Requested charge port change to %d", port);
+
+	if (port < 0 || CHARGE_PORT_COUNT <= port)
+		return EC_ERROR_INVAL;
+
+	if (port == active_port)
+		return EC_SUCCESS;
+
+	/* Don't sink from a source port */
+	if (board_vbus_source_enabled(port))
+		return EC_ERROR_INVAL;
+
+	if (!chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
+		if (charge_manager_get_active_charge_port() != CHARGE_PORT_NONE)
+			/* Change is only permitted while the system is off */
+			return EC_ERROR_INVAL;
+
+		/*
+		 * Current setting is no charge port but the AP is on, so the
+		 * charge manager is out of sync (probably because we're
+		 * reinitializing after sysjump). Reject requests that aren't
+		 * in sync with our outputs.
+		 */
+
+		/* TODO: add this part after two type-c function is finished. */
+	}
+
+	CPRINTUSB("New charger p%d", port);
+
+	switch (port) {
+	case CHARGE_PORT_TYPEC0:
+		ppc_vbus_sink_enable(USBC_PORT_C0, 1);
+		break;
+	default:
+		return EC_ERROR_INVAL;
+	}
+
+	return EC_SUCCESS;
+}
+
+static void board_charge_manager_init(void)
+{
+	enum charge_port port;
+
+	/*
+	 * Initialize all charge suppliers to 0. The charge manager waits until
+	 * all ports have reported in before doing anything.
+	 */
+	for (int i = 0; i < CHARGE_PORT_COUNT; i++) {
+		for (int j = 0; j < CHARGE_SUPPLIER_COUNT; j++)
+			charge_manager_update_charge(j, i, NULL);
+	}
+
+	port = CHARGE_PORT_TYPEC0;
+	CPRINTUSB("Power source is p%d (USB-C)", port);
+
+	/* Initialize the power source supplier */
+	switch (port) {
+	case CHARGE_PORT_TYPEC0:
+		typec_set_input_current_limit(port, 3000, 5000);
+		break;
+	}
+}
+DECLARE_HOOK(HOOK_INIT, board_charge_manager_init,
+	     HOOK_PRIO_INIT_CHARGE_MANAGER + 1);
+
+__override int extpower_is_present(void)
+{
+	/*
+	 * There's no battery, so running this method implies we have power.
+	 */
+	return 1;
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	if (signal == GPIO_USB_C0_FAULT_L)
+		syv682x_interrupt(USBC_PORT_C0);
+}
+
+/* I2C Ports */
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_EEPROM_SCL,
+	  .sda = GPIO_EC_I2C_EEPROM_SDA },
+
+	{ .name = "usbc0",
+	  .port = I2C_PORT_USB_C0,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C0_SCL,
+	  .sda = GPIO_EC_I2C_USB_C0_SDA },
+
+	{ .name = "hdmi1_edid",
+	  .port = I2C_PORT_HDMI1_EDID,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_HDMI1_EDID_SCL,
+	  .sda = GPIO_EC_I2C_HDMI1_EDID_SDA },
+
+	{ .name = "hdmi1_src_ddc",
+	  .port = I2C_PORT_HDMI1_SRC_DDC,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_HDMI1_SRC_DDC_SCL,
+	  .sda = GPIO_EC_I2C_HDMI1_SRC_DDC_SDA },
+};
+
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
diff --git a/board/boxy/board.h b/board/boxy/board.h
new file mode 100644
index 0000000000..c48d9fe29f
--- /dev/null
+++ b/board/boxy/board.h
@@ -0,0 +1,166 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Boxy board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* Select Baseboard features */
+#define VARIANT_DEDEDE_EC_IT8320
+#include "baseboard.h"
+
+/* System unlocked in early development */
+#define CONFIG_SYSTEM_UNLOCKED
+
+#define CONFIG_CMD_CHARGER_DUMP
+
+/* I2C Bus Configuration */
+#define I2C_PORT_HDMI2_EDID IT83XX_I2C_CH_B
+#undef I2C_PORT_USB_C0
+#define I2C_PORT_USB_C0 IT83XX_I2C_CH_C
+#define I2C_PORT_HDMI2_SRC_DDC IT83XX_I2C_CH_D
+#define I2C_PORT_HDMI1_EDID IT83XX_I2C_CH_E
+#define I2C_PORT_HDMI1_SRC_DDC IT83XX_I2C_CH_F
+
+/* Power */
+#undef CONFIG_CHARGER
+#undef CONFIG_CHARGER_DISCHARGE_ON_AC
+#undef CONFIG_USB_PD_VBUS_MEASURE_CHARGER
+#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 16000
+#define PD_MAX_VOLTAGE_MV 20000
+#undef PD_MAX_CURRENT_MA
+#define PD_MAX_CURRENT_MA 3250
+#undef PD_MAX_POWER_MW
+#define PD_MAX_POWER_MW 65000
+#define CONFIG_USB_PD_VBUS_DETECT_GPIO
+
+/* Override macro for C0 only */
+#define PORT_TO_HPD(port) (GPIO_USB_C0_DP_HPD)
+
+/* Power: Dedicated barreljack charger port */
+#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT
+#define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1
+#define DEDICATED_CHARGE_PORT 1
+
+/* USB Type-C */
+#undef CONFIG_USB_CHARGER
+#undef CONFIG_USB_MUX_PI3USB31532
+
+/* TCPC */
+#define CONFIG_USB_PD_PORT_MAX_COUNT 1
+#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0: ITE EC TCPC */
+#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1
+
+/* PPC */
+#define CONFIG_USB_PD_DISCHARGE_PPC
+#define CONFIG_USB_PD_VBUS_DETECT_PPC
+#define CONFIG_USBC_PPC
+#define CONFIG_USBC_PPC_SYV682X
+
+/* USB Mux and Retimer */
+#define CONFIG_USB_MUX_IT5205 /* C0: ITE Mux */
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */
+
+/* USB Type A Features */
+#define CONFIG_USB_PORT_POWER_DUMB
+#define USB_PORT_COUNT 2 /* Type A ports */
+
+/* No battery */
+#undef CONFIG_BATTERY_CUT_OFF
+#undef CONFIG_BATTERY_PRESENT_GPIO
+#undef CONFIG_BATTERY_REQUESTS_NIL_WHEN_DEAD
+#undef CONFIG_BATTERY_REVIVE_DISCONNECT
+#undef CONFIG_BATTERY_SMART
+
+/* LED */
+#define CONFIG_LED_PWM
+#define CONFIG_LED_PWM_COUNT 1
+
+/* PWM */
+#define CONFIG_PWM
+
+/* Thermistors */
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_THERMISTOR
+#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
+
+/* Buttons */
+#define CONFIG_DEDICATED_RECOVERY_BUTTON
+#define CONFIG_DEDICATED_RECOVERY_BUTTON_2
+#define CONFIG_DEDICATED_RECOVERY_BUTTON_FLAGS BUTTON_FLAG_ACTIVE_HIGH
+#define CONFIG_POWER_BUTTON
+#define CONFIG_POWER_BUTTON_IGNORE_LID
+#define CONFIG_POWER_BUTTON_X86
+#define CONFIG_EMULATED_SYSRQ
+
+/* No Keyboard */
+#undef CONFIG_KEYBOARD_COL2_INVERTED
+#undef CONFIG_KEYBOARD_PROTOCOL_8042
+#undef CONFIG_CMD_KEYBOARD
+#undef CONFIG_KEYBOARD_BOOT_KEYS
+#undef CONFIG_KEYBOARD_RUNTIME_KEYS
+
+/* No backlight */
+#undef CONFIG_BACKLIGHT_LID
+#undef GPIO_ENABLE_BACKLIGHT
+
+/* Unused features - Misc */
+#undef CONFIG_HIBERNATE
+#undef CONFIG_VOLUME_BUTTONS
+#undef CONFIG_LID_SWITCH
+#undef CONFIG_TABLET_MODE
+#undef CONFIG_TABLET_MODE_SWITCH
+#undef CONFIG_GMR_TABLET_MODE
+#undef GPIO_TABLET_MODE_L
+
+/* Unused GPIOs */
+#undef GPIO_USB_C1_DP_HPD
+
+/* Pin renaming */
+#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_OD
+#define GPIO_RECOVERY_L_2 GPIO_H1_EC_RECOVERY_BTN_ODL
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum charge_port {
+	CHARGE_PORT_TYPEC0,
+};
+
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_COUNT };
+
+enum pwm_channel {
+	PWM_CH_LED_RED,
+	PWM_CH_LED_GREEN,
+	PWM_CH_LED_BLUE,
+	PWM_CH_COUNT,
+};
+
+/* ADC channels */
+enum adc_channel {
+	ADC_VSNS_PP3300_A, /* ADC0 */
+	ADC_TEMP_SENSOR_1, /* ADC2 */
+	ADC_TEMP_SENSOR_2, /* ADC3 */
+	ADC_VBUS, /* ADC4 */
+	ADC_TEMP_SENSOR_3, /* ADC13 */
+	ADC_PPVAR_PWR_IN_IMON, /* ADC15 */
+	ADC_SNS_PPVAR_PWR_IN, /* ADC16 */
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1,
+	TEMP_SENSOR_2,
+	TEMP_SENSOR_3,
+	TEMP_SENSOR_COUNT
+};
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/boxy/build.mk b/board/boxy/build.mk
new file mode 100644
index 0000000000..5593502527
--- /dev/null
+++ b/board/boxy/build.mk
@@ -0,0 +1,15 @@
+# -*- makefile -*-
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=it83xx
+CHIP_FAMILY:=it8320
+CHIP_VARIANT:=it8320dx
+BASEBOARD:=dedede
+BOARD:=boxy
+
+board-y=board.o led.o usb_pd_policy.o
diff --git a/board/boxy/ec.tasklist b/board/boxy/ec.tasklist
new file mode 100644
index 0000000000..4aad682d14
--- /dev/null
+++ b/board/boxy/ec.tasklist
@@ -0,0 +1,16 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE)
diff --git a/board/boxy/gpio.inc b/board/boxy/gpio.inc
new file mode 100644
index 0000000000..c21ff3e870
--- /dev/null
+++ b/board/boxy/gpio.inc
@@ -0,0 +1,165 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+/* Power State interrupts */
+GPIO_INT(SLP_S4_L, PIN(I, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L, PIN(H, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(SLP_S0_L, PIN(E, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L, PIN(G, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID0, PIN(D, 0), GPIO_INT_BOTH | GPIO_SEL_1P8V,
+	 power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID1, PIN(K, 1), GPIO_INT_BOTH | GPIO_SEL_1P8V,
+	 power_signal_interrupt)
+GPIO_INT(RSMRST_PWRGD_L, PIN(E, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(CPU_C10_GATE_L, PIN(G, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_DRAM_OD, PIN(D, 3), GPIO_INT_BOTH,
+	 baseboard_all_sys_pgood_interrupt)
+GPIO_INT(PG_PP1050_ST_OD, PIN(L, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(EC_VSNS_PP3300_S5, PIN(I, 0), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_VCCIO_EXT_OD, PIN(D, 7), GPIO_INT_BOTH,
+	 baseboard_all_sys_pgood_interrupt)
+GPIO_INT(ESPI_RESET_L, PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V,
+	 espi_reset_pin_asserted_interrupt)
+
+GPIO_INT(H1_EC_PWR_BTN_ODL, PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP,
+	 power_button_interrupt)
+#ifdef CONFIG_LOW_POWER_IDLE
+/* Used to wake up the EC from Deep Doze mode when writing to console */
+GPIO_INT(UART1_RX, PIN(B, 0), GPIO_INT_BOTH,
+	 uart_deepsleep_interrupt) /* UART_DBG_TX_EC_RX
+				    */
+#endif
+
+/* Other interrupts */
+GPIO_INT(EC_WP_OD, PIN(A, 6), GPIO_INT_BOTH, switch_interrupt)
+/* Directly connected recovery button */
+GPIO_INT(EC_RECOVERY_BTN_OD, PIN(K, 7), GPIO_INT_BOTH, button_interrupt)
+/* Recovery button input from H1 */
+GPIO_INT(H1_EC_RECOVERY_BTN_ODL, PIN(K, 4), GPIO_INT_BOTH, button_interrupt)
+GPIO_INT(USB_C0_FAULT_L, PIN(K, 0), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C1_FAULT_L, PIN(K, 3), GPIO_INT_FALLING, ppc_interrupt)
+
+/* Power sequence GPIOs */
+GPIO(EC_AP_PSYS, PIN(J, 2), GPIO_OUT_LOW)
+GPIO(EC_AP_RTCRST, PIN(K, 2), GPIO_OUT_LOW)
+GPIO(EC_AP_PWR_BTN_ODL, PIN(B, 6), GPIO_ODR_HIGH)
+GPIO(EC_AP_DPWROK, PIN(L, 7), GPIO_OUT_LOW)
+GPIO(EC_AP_RSMRST_L, PIN(H, 0), GPIO_OUT_LOW)
+GPIO(EC_AP_WAKE_ODL, PIN(D, 5), GPIO_ODR_HIGH)
+GPIO(SYS_RST_ODL, PIN(D, 1), GPIO_ODR_HIGH)
+GPIO(EC_AP_SYS_PWROK, PIN(F, 2), GPIO_OUT_LOW)
+GPIO(PG_PP5000_U_OD, PIN(J, 0), GPIO_INPUT)
+GPIO(EN_PP5000_U, PIN(K, 5), GPIO_OUT_HIGH)
+GPIO(PG_PP3300_A, PIN(B, 5), GPIO_INPUT)
+GPIO(EN_PP3300_A, PIN(C, 5), GPIO_OUT_LOW)
+GPIO(EC_AP_PCH_PWROK_OD, PIN(D, 6), GPIO_ODR_LOW)
+/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
+GPIO(EN_VCCST, PIN(D, 4), GPIO_INPUT)
+GPIO(EN_VCCIO_EXT, PIN(B, 2), GPIO_OUT_LOW)
+GPIO(EC_PROCHOT_ODL, PIN(I, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(EC_AP_VCCST_PWRGD_OD, PIN(E, 5), GPIO_ODR_LOW)
+GPIO(ALL_SYS_PWRGD, PIN(B, 7), GPIO_OUT_LOW)
+
+/* Required for icelake chipset code, but implemented through other means for
+ * dedede */
+UNIMPLEMENTED(AC_PRESENT)
+UNIMPLEMENTED(PG_EC_DSW_PWROK)
+UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
+
+/* Required for dedede baseboard but not used in boxy */
+UNIMPLEMENTED(USB_C0_INT_ODL)
+UNIMPLEMENTED(EN_SLP_Z)
+UNIMPLEMENTED(EC_BATTERY_PRES_ODL)
+
+/* I2C pins - Alternate function below configures I2C module on these pins */
+GPIO(EC_I2C_EEPROM_SCL, PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SDA, PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SCL, PIN(F, 6), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SDA, PIN(F, 7), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_SCL, PIN(C, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_SDA, PIN(C, 2), GPIO_INPUT)
+GPIO(EC_I2C_HDMI1_EDID_SCL, PIN(E, 0), GPIO_INPUT)
+GPIO(EC_I2C_HDMI1_EDID_SDA, PIN(E, 7), GPIO_INPUT)
+GPIO(EC_I2C_HDMI1_SRC_DDC_SCL, PIN(A, 4), GPIO_INPUT)
+GPIO(EC_I2C_HDMI1_SRC_DDC_SDA, PIN(A, 5), GPIO_INPUT)
+
+/* USB pins */
+GPIO(EC_AP_USB_C0_HPD, PIN(L, 4), GPIO_OUT_LOW)
+GPIO(EC_AP_USB_C1_HPD, PIN(J, 6), GPIO_OUT_LOW)
+GPIO(EN_USB_A0_VBUS, PIN(L, 6), GPIO_OUT_LOW)
+GPIO(EN_USB_A1_VBUS, PIN(C, 6), GPIO_OUT_LOW)
+GPIO(USB_C0_SBU_MUX_FAULT, PIN(I, 7), GPIO_INPUT)
+
+/* MKBP event synchronization */
+/* TODO(b/257833880) Check whether this pin is needed */
+GPIO(EC_AP_MKBP_INT_L, PIN(L, 5), GPIO_ODR_HIGH)
+
+/* HDMI */
+GPIO(HDMI1_CEC, PIN(F, 0), GPIO_OUT_LOW)
+GPIO(HDMI1_SRC_HPD, PIN(F, 3), GPIO_INPUT)
+GPIO(EC_HDMI1_SRC_HPD_OUT, PIN(K, 6), GPIO_OUT_LOW)
+GPIO(HDMI1_EDID_SEL, PIN(J, 1), GPIO_OUT_LOW)
+GPIO(EDID_BTN_ODL, PIN(C, 3), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(EC_EN_PP5000_HDMI1, PIN(KSO_L, 6), GPIO_OUT_LOW)
+
+/* Misc */
+GPIO(EC_ENTERING_RW, PIN(C, 7), GPIO_OUT_LOW)
+GPIO(CCD_MODE_ODL, PIN(H, 5), GPIO_ODR_HIGH)
+GPIO(ECH1_PACKET_MODE, PIN(C, 0), GPIO_OUT_LOW)
+GPIO(UART0_RX, PIN(B, 1), GPIO_OUT_LOW) /* UART_EC_TX_DBG_RX */
+
+/* NC pins, enable internal pull-down to avoid floating state. */
+GPIO(GPIOG0_NC, PIN(G, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG3_NC, PIN(G, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG4_NC, PIN(G, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG5_NC, PIN(G, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG6_NC, PIN(G, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG7_NC, PIN(G, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOH6_NC, PIN(H, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOI4_NC, PIN(I, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ4_NC, PIN(J, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOM6_NC, PIN(M, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ5_NC, PIN(J, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOE3_NC, PIN(E, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOF1_NC, PIN(F, 1), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOE6_NC, PIN(E, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOC4_NC, PIN(C, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOI6_NC, PIN(I, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOA0_NC, PIN(A, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ3_NC, PIN(J, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOH4_NC, PIN(H, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+
+/* Alternate functions GPIO definitions */
+/* UART */
+ALTERNATE(PIN_MASK(B, BIT(0) | BIT(1)), 0, MODULE_UART, 0) /* UART for debug */
+
+/* I2C */
+ALTERNATE(PIN_MASK(B, BIT(3) | BIT(4)), 0, MODULE_I2C, 0) /* I2C0 - EEPROM */
+ALTERNATE(PIN_MASK(C, BIT(1) | BIT(2)), 0, MODULE_I2C, 0) /* I2C1 - USB_C1*/
+ALTERNATE(PIN_MASK(F, BIT(6) | BIT(7)), 0, MODULE_I2C, 0) /* I2C2 - USB_C0 */
+ALTERNATE(PIN_MASK(E, BIT(0) | BIT(7)), 0, MODULE_I2C, 0) /* I2C4 - HDMI1_EDID
+							   */
+ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), 0, MODULE_I2C, 0) /* I2C5 -
+							     HDMI1_SRC_DDC */
+
+/* ADC */
+/* ADC2: TEMP_SENSOR_1, ADC3: TEMP_SENSOR_2, ADC4: VBUS */
+ALTERNATE(PIN_MASK(I, BIT(2) | BIT(3) | BIT(4)), 0, MODULE_ADC, 0)
+/*
+ * ADC13: TEMP_SENSOR_3
+ * ADC15: ANALOG_PPVAR_PWR_IN_IMON
+ * ADC16: SNS_PPVAR_PWR_IN
+ */
+ALTERNATE(PIN_MASK(L, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0)
+
+/* PWM */
+ALTERNATE(PIN_MASK(A, BIT(1) | BIT(2) | BIT(3)), 0, MODULE_PWM,
+	  0) /* LED_[R,G,B]_ODL
+	      */
\ No newline at end of file
diff --git a/board/boxy/led.c b/board/boxy/led.c
new file mode 100644
index 0000000000..9ed4f3c413
--- /dev/null
+++ b/board/boxy/led.c
@@ -0,0 +1,80 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Boxy specific PWM LED settings. */
+
+#include "common.h"
+#include "ec_commands.h"
+#include "led_pwm.h"
+#include "pwm.h"
+#include "util.h"
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_POWER_LED,
+};
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+/* One physical LED with red, green, and blue. */
+struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = {
+	/* Red, Green, Blue */
+	[EC_LED_COLOR_RED] = { 100, 0, 0 },
+	[EC_LED_COLOR_GREEN] = { 0, 100, 0 },
+	[EC_LED_COLOR_BLUE] = { 0, 0, 100 },
+	[EC_LED_COLOR_YELLOW] = { 50, 50, 0 },
+	[EC_LED_COLOR_WHITE] = { 50, 50, 50 },
+	[EC_LED_COLOR_AMBER] = { 70, 30, 0 },
+};
+
+/* One logical LED with red, green, and blue channels. */
+struct pwm_led pwm_leds[CONFIG_LED_PWM_COUNT] = {
+	{
+		.ch0 = PWM_CH_LED_RED,
+		.ch1 = PWM_CH_LED_GREEN,
+		.ch2 = PWM_CH_LED_BLUE,
+		.enable = &pwm_enable,
+		.set_duty = &pwm_set_duty,
+	},
+};
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	memset(brightness_range, '\0',
+	       sizeof(*brightness_range) * EC_LED_COLOR_COUNT);
+	brightness_range[EC_LED_COLOR_RED] = 100;
+	brightness_range[EC_LED_COLOR_GREEN] = 100;
+	brightness_range[EC_LED_COLOR_BLUE] = 100;
+	brightness_range[EC_LED_COLOR_YELLOW] = 100;
+	brightness_range[EC_LED_COLOR_WHITE] = 100;
+	brightness_range[EC_LED_COLOR_AMBER] = 100;
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	enum pwm_led_id pwm_id;
+
+	/* Convert ec_led_id to pwm_led_id. */
+	if (led_id == EC_LED_ID_POWER_LED)
+		pwm_id = PWM_LED0;
+	else
+		return EC_ERROR_UNKNOWN;
+
+	if (brightness[EC_LED_COLOR_RED])
+		set_pwm_led_color(pwm_id, EC_LED_COLOR_RED);
+	else if (brightness[EC_LED_COLOR_GREEN])
+		set_pwm_led_color(pwm_id, EC_LED_COLOR_GREEN);
+	else if (brightness[EC_LED_COLOR_BLUE])
+		set_pwm_led_color(pwm_id, EC_LED_COLOR_BLUE);
+	else if (brightness[EC_LED_COLOR_YELLOW])
+		set_pwm_led_color(pwm_id, EC_LED_COLOR_YELLOW);
+	else if (brightness[EC_LED_COLOR_WHITE])
+		set_pwm_led_color(pwm_id, EC_LED_COLOR_WHITE);
+	else if (brightness[EC_LED_COLOR_AMBER])
+		set_pwm_led_color(pwm_id, EC_LED_COLOR_AMBER);
+	else
+		/* Otherwise, the "color" is "off". */
+		set_pwm_led_color(pwm_id, -1);
+
+	return EC_SUCCESS;
+}
diff --git a/board/boxy/usb_pd_policy.c b/board/boxy/usb_pd_policy.c
new file mode 100644
index 0000000000..58bc80170f
--- /dev/null
+++ b/board/boxy/usb_pd_policy.c
@@ -0,0 +1,72 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "charger.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "gpio.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+int pd_check_vconn_swap(int port)
+{
+	/* Allow VCONN swaps if the AP is on */
+	return gpio_get_level(GPIO_EN_PP5000_U);
+}
+
+void pd_power_supply_reset(int port)
+{
+	int prev_en;
+
+	if (port < 0 || port >= board_get_usb_pd_port_count())
+		return;
+
+	prev_en = ppc_is_sourcing_vbus(port);
+
+	/* Disable VBUS source */
+	ppc_vbus_source_enable(port, 0);
+
+	/* Enable discharge if we were previously sourcing 5V */
+	if (prev_en)
+		pd_set_vbus_discharge(port, 1);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	/* Disable charging */
+	rv = ppc_vbus_sink_enable(port, 0);
+	if (rv)
+		return rv;
+
+	pd_set_vbus_discharge(port, 0);
+
+	/* Enable VBUS source */
+	rv = ppc_vbus_source_enable(port, 1);
+	if (rv)
+		return rv;
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+__override int pd_snk_is_vbus_provided(int port)
+{
+	if (port != CHARGE_PORT_TYPEC0)
+		return 0;
+
+	return ppc_is_vbus_present(port);
+}
diff --git a/board/boxy/vif_override.xml b/board/boxy/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/boxy/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/brask/board.c b/board/brask/board.c
new file mode 100644
index 0000000000..793c2889f8
--- /dev/null
+++ b/board/brask/board.c
@@ -0,0 +1,611 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "adc.h"
+#include "builtin/assert.h"
+#include "button.h"
+#include "cec.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "driver/cec/bitbang.h"
+#include "driver/tcpm/tcpci.h"
+#include "driver/wpc/cps8100.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "peripheral_charger.h"
+#include "power.h"
+#include "power_button.h"
+#include "switch.h"
+#include "throttle_ap.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+#include <stdbool.h>
+
+/* Console output macros */
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+
+static void power_monitor(void);
+DECLARE_DEFERRED(power_monitor);
+
+/******************************************************************************/
+/* USB-A charging control */
+
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_PP5000_USBA,
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
+
+struct pchg pchgs[] = {
+	[0] = {
+		.cfg = &(const struct pchg_config) {
+			.drv = &cps8100_drv,
+			.i2c_port = I2C_PORT_QI,
+			.irq_pin = GPIO_QI_INT_ODL,
+			.full_percent = 96,
+			.block_size = 128,
+		},
+		.policy = {
+			[PCHG_CHIPSET_STATE_ON] = &pchg_policy_on,
+			[PCHG_CHIPSET_STATE_SUSPEND] = &pchg_policy_suspend,
+		},
+		.events = QUEUE_NULL(PCHG_EVENT_QUEUE_SIZE, enum pchg_event),
+	},
+};
+
+int board_get_pchg_count(void)
+{
+	return ARRAY_SIZE(pchgs);
+}
+
+__override void board_pchg_power_on(int port, bool on)
+{
+	if (port == 0)
+		gpio_set_level(GPIO_EC_QI_PWR, on);
+	else
+		CPRINTS("%s: Invalid port=%d", __func__, port);
+}
+
+/******************************************************************************/
+
+/* CEC ports */
+const struct cec_config_t cec_config[] = {
+	[CEC_PORT_0] = {
+		.drv = &bitbang_cec_drv,
+		.offline_policy = NULL,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(cec_config) == CEC_PORT_COUNT);
+
+int board_set_active_charge_port(int port)
+{
+	CPRINTS("Requested charge port change to %d", port);
+
+	/*
+	 * The charge manager may ask us to switch to no charger if we're
+	 * running off USB-C only but upstream doesn't support PD. It requires
+	 * that we accept this switch otherwise it triggers an assert and EC
+	 * reset; it's not possible to boot the AP anyway, but we want to avoid
+	 * resetting the EC so we can continue to do the "low power" LED blink.
+	 */
+	if (port == CHARGE_PORT_NONE)
+		return EC_SUCCESS;
+
+	if (port < 0 || CHARGE_PORT_COUNT <= port)
+		return EC_ERROR_INVAL;
+
+	if (port == charge_manager_get_active_charge_port())
+		return EC_SUCCESS;
+
+	/* Don't charge from a source port */
+	if (board_vbus_source_enabled(port))
+		return EC_ERROR_INVAL;
+
+	if (!chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
+		int bj_active, bj_requested;
+
+		if (charge_manager_get_active_charge_port() != CHARGE_PORT_NONE)
+			/* Change is only permitted while the system is off */
+			return EC_ERROR_INVAL;
+
+		/*
+		 * Current setting is no charge port but the AP is on, so the
+		 * charge manager is out of sync (probably because we're
+		 * reinitializing after sysjump). Reject requests that aren't
+		 * in sync with our outputs.
+		 */
+		bj_active = !gpio_get_level(GPIO_EN_PPVAR_BJ_ADP_L);
+		bj_requested = port == CHARGE_PORT_BARRELJACK;
+		if (bj_active != bj_requested)
+			return EC_ERROR_INVAL;
+	}
+
+	CPRINTS("New charger p%d", port);
+
+	switch (port) {
+	case CHARGE_PORT_TYPEC0:
+	case CHARGE_PORT_TYPEC1:
+	case CHARGE_PORT_TYPEC2:
+		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 1);
+		break;
+	case CHARGE_PORT_BARRELJACK:
+		/* Make sure BJ adapter is sourcing power */
+		if (gpio_get_level(GPIO_BJ_ADP_PRESENT_ODL))
+			return EC_ERROR_INVAL;
+		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 0);
+		break;
+	default:
+		return EC_ERROR_INVAL;
+	}
+
+	return EC_SUCCESS;
+}
+
+static uint8_t usbc_overcurrent;
+static int32_t base_5v_power_s5;
+static int32_t base_5v_power_z1;
+
+/*
+ * Power usage for each port as measured or estimated.
+ * Units are milliwatts (5v x ma current)
+ */
+
+/* PP5000_S5 loads */
+#define PWR_S5_BASE_LOAD (5 * 1431)
+#define PWR_S5_FRONT_HIGH (5 * 1737)
+#define PWR_S5_FRONT_LOW (5 * 1055)
+#define PWR_S5_REAR_HIGH (5 * 1737)
+#define PWR_S5_REAR_LOW (5 * 1055)
+#define PWR_S5_HDMI (5 * 580)
+#define PWR_S5_MAX (5 * 10000)
+#define FRONT_DELTA (PWR_S5_FRONT_HIGH - PWR_S5_FRONT_LOW)
+#define REAR_DELTA (PWR_S5_REAR_HIGH - PWR_S5_REAR_LOW)
+
+/* PP5000_Z1 loads */
+#define PWR_Z1_BASE_LOAD (5 * 5)
+#define PWR_Z1_C_HIGH (5 * 3600)
+#define PWR_Z1_C_LOW (5 * 2000)
+#define PWR_Z1_MAX (5 * 9000)
+/*
+ * Update the 5V power usage, assuming no throttling,
+ * and invoke the power monitoring.
+ */
+static void update_5v_usage(void)
+{
+	int front_ports = 0;
+	int rear_ports = 0;
+
+	/*
+	 * Recalculate the 5V load, assuming no throttling.
+	 */
+	base_5v_power_s5 = PWR_S5_BASE_LOAD;
+	if (!gpio_get_level(GPIO_USB_A0_OC_ODL)) {
+		front_ports++;
+		base_5v_power_s5 += PWR_S5_FRONT_LOW;
+	}
+	if (!gpio_get_level(GPIO_USB_A1_OC_ODL)) {
+		front_ports++;
+		base_5v_power_s5 += PWR_S5_FRONT_LOW;
+	}
+	/*
+	 * Only 1 front port can run higher power at a time.
+	 */
+	if (front_ports > 0)
+		base_5v_power_s5 += PWR_S5_FRONT_HIGH - PWR_S5_FRONT_LOW;
+
+	if (!gpio_get_level(GPIO_USB_A2_OC_ODL)) {
+		rear_ports++;
+		base_5v_power_s5 += PWR_S5_REAR_LOW;
+	}
+	if (!gpio_get_level(GPIO_USB_A3_OC_ODL)) {
+		rear_ports++;
+		base_5v_power_s5 += PWR_S5_REAR_LOW;
+	}
+	/*
+	 * Only 1 rear port can run higher power at a time.
+	 */
+	if (rear_ports > 0)
+		base_5v_power_s5 += PWR_S5_REAR_HIGH - PWR_S5_REAR_LOW;
+	if (!gpio_get_level(GPIO_HDMI_CONN_OC_ODL))
+		base_5v_power_s5 += PWR_S5_HDMI;
+	base_5v_power_z1 = PWR_Z1_BASE_LOAD;
+	if (usbc_overcurrent)
+		base_5v_power_z1 += PWR_Z1_C_HIGH;
+	/*
+	 * Invoke the power handler immediately.
+	 */
+	hook_call_deferred(&power_monitor_data, 0);
+}
+DECLARE_DEFERRED(update_5v_usage);
+/*
+ * Start power monitoring after ADCs have been initialised.
+ */
+DECLARE_HOOK(HOOK_INIT, update_5v_usage, HOOK_PRIO_INIT_ADC + 1);
+
+static void port_ocp_interrupt(enum gpio_signal signal)
+{
+	hook_call_deferred(&update_5v_usage_data, 0);
+}
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/******************************************************************************/
+/*
+ * Barrel jack power supply handling
+ *
+ * EN_PPVAR_BJ_ADP_L must default active to ensure we can power on when the
+ * barrel jack is connected, and the USB-C port can bring the EC up fine in
+ * dead-battery mode. Both the USB-C and barrel jack switches do reverse
+ * protection, so we're safe to turn one on then the other off- but we should
+ * only do that if the system is off since it might still brown out.
+ */
+
+#define ADP_DEBOUNCE_MS 1000 /* Debounce time for BJ plug/unplug */
+/* Debounced connection state of the barrel jack */
+static int8_t adp_connected = -1;
+static void adp_connect_deferred(void)
+{
+	struct charge_port_info pi = { 0 };
+	int connected = !gpio_get_level(GPIO_BJ_ADP_PRESENT_ODL);
+
+	/* Debounce */
+	if (connected == adp_connected)
+		return;
+	if (connected)
+		ec_bj_power(&pi.voltage, &pi.current);
+	charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED,
+				     DEDICATED_CHARGE_PORT, &pi);
+	adp_connected = connected;
+}
+DECLARE_DEFERRED(adp_connect_deferred);
+
+/* IRQ for BJ plug/unplug. It shouldn't be called if BJ is the power source. */
+void adp_connect_interrupt(enum gpio_signal signal)
+{
+	hook_call_deferred(&adp_connect_deferred_data, ADP_DEBOUNCE_MS * MSEC);
+}
+
+static void adp_state_init(void)
+{
+	ASSERT(CHARGE_PORT_ENUM_COUNT == CHARGE_PORT_COUNT);
+	/*
+	 * Initialize all charge suppliers to 0. The charge manager waits until
+	 * all ports have reported in before doing anything.
+	 */
+	for (int i = 0; i < CHARGE_PORT_COUNT; i++) {
+		for (int j = 0; j < CHARGE_SUPPLIER_COUNT; j++)
+			charge_manager_update_charge(j, i, NULL);
+	}
+
+	/* Report charge state from the barrel jack. */
+	adp_connect_deferred();
+}
+DECLARE_HOOK(HOOK_INIT, adp_state_init, HOOK_PRIO_INIT_CHARGE_MANAGER + 1);
+
+static void board_init(void)
+{
+	gpio_enable_interrupt(GPIO_BJ_ADP_PRESENT_ODL);
+	gpio_enable_interrupt(GPIO_HDMI_CONN_OC_ODL);
+	gpio_enable_interrupt(GPIO_USB_A0_OC_ODL);
+	gpio_enable_interrupt(GPIO_USB_A1_OC_ODL);
+	gpio_enable_interrupt(GPIO_USB_A2_OC_ODL);
+	gpio_enable_interrupt(GPIO_USB_A3_OC_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+void board_overcurrent_event(int port, int is_overcurrented)
+{
+	/* Check that port number is valid. */
+	if ((port < 0) || (port >= CONFIG_USB_PD_PORT_MAX_COUNT))
+		return;
+	usbc_overcurrent = is_overcurrented;
+	update_5v_usage();
+}
+/*
+ * Power monitoring and management.
+ *
+ * the power budgets are met without letting the system fall into
+ * power deficit (perhaps causing a brownout).
+ *
+ * There are 2 power budgets that need to be managed:
+ * The overall goal is to gracefully manage the power demand so that
+ *  - overall system power as measured on the main power supply rail.
+ *  - 5V power delivered to the USB and HDMI ports.
+ *
+ * The actual system power demand is calculated from the VBUS voltage and
+ * the input current (read from a shunt), averaged over 5 readings.
+ * The power budget limit is from the charge manager.
+ *
+ * The 5V power cannot be read directly. Instead, we rely on overcurrent
+ * inputs from the USB and HDMI ports to indicate that the port is in use
+ * (and drawing maximum power).
+ *
+ * There are 3 throttles that can be applied (in priority order):
+ *
+ *  - Type A BC1.2 front port restriction (3W)
+ *  - Type A BC1.2 rear port restriction (3W)
+ *  - Type C PD (throttle to 1.5A if sourcing)
+ *  - Turn on PROCHOT, which immediately throttles the CPU.
+ *
+ *  The first 3 throttles affect both the system power and the 5V rails.
+ *  The third is a last resort to force an immediate CPU throttle to
+ *  reduce the overall power use.
+ *
+ *  The strategy is to determine what the state of the throttles should be,
+ *  and to then turn throttles off or on as needed to match this.
+ *
+ *  This function runs on demand, or every 2 ms when the CPU is up,
+ *  and continually monitors the power usage, applying the
+ *  throttles when necessary.
+ *
+ *  All measurements are in milliwatts.
+ */
+#define THROT_TYPE_A_FRONT BIT(0)
+#define THROT_TYPE_A_REAR BIT(1)
+#define THROT_TYPE_C0 BIT(2)
+#define THROT_TYPE_C1 BIT(3)
+#define THROT_TYPE_C2 BIT(4)
+#define THROT_PROCHOT BIT(5)
+
+/*
+ * Power gain if front USB A ports are limited.
+ */
+#define POWER_GAIN_TYPE_A 3200
+/*
+ * Power gain if Type C port is limited.
+ */
+#define POWER_GAIN_TYPE_C 8800
+/*
+ * Power is averaged over 10 ms, with a reading every 2 ms.
+ */
+#define POWER_DELAY_MS 2
+#define POWER_READINGS (10 / POWER_DELAY_MS)
+
+static void power_monitor(void)
+{
+	static uint32_t current_state;
+	static uint32_t history[POWER_READINGS];
+	static uint8_t index;
+	int32_t delay;
+	uint32_t new_state = 0, diff;
+	int32_t headroom_5v_s5 = PWR_S5_MAX - base_5v_power_s5;
+	int32_t headroom_5v_z1 = PWR_Z1_MAX - base_5v_power_z1;
+
+	/*
+	 * If CPU is off or suspended, no need to throttle
+	 * or restrict power.
+	 */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF | CHIPSET_STATE_SUSPEND)) {
+		/*
+		 * Slow down monitoring, assume no throttling required.
+		 */
+		delay = 20 * MSEC;
+		/*
+		 * Clear the first entry of the power table so that
+		 * it is re-initilalised when the CPU starts.
+		 */
+		history[0] = 0;
+	} else {
+		int32_t charger_mw;
+
+		delay = POWER_DELAY_MS * MSEC;
+		/*
+		 * Get current charger limit (in mw).
+		 * If not configured yet, skip.
+		 */
+		charger_mw = charge_manager_get_power_limit_uw() / 1000;
+		if (charger_mw != 0) {
+			int32_t gap, total, max, power;
+			int i;
+
+			/*
+			 * Read power usage.
+			 */
+			power = (adc_read_channel(ADC_VBUS) *
+				 adc_read_channel(ADC_PPVAR_IMON)) /
+				1000;
+			/* Init power table */
+			if (history[0] == 0) {
+				for (i = 0; i < POWER_READINGS; i++)
+					history[i] = power;
+			}
+			/*
+			 * Update the power readings and
+			 * calculate the average and max.
+			 */
+			history[index] = power;
+			index = (index + 1) % POWER_READINGS;
+			total = 0;
+			max = history[0];
+			for (i = 0; i < POWER_READINGS; i++) {
+				total += history[i];
+				if (history[i] > max)
+					max = history[i];
+			}
+			/*
+			 * For Type-C power supplies, there is
+			 * less tolerance for exceeding the rating,
+			 * so use the max power that has been measured
+			 * over the measuring period.
+			 * For barrel-jack supplies, the rating can be
+			 * exceeded briefly, so use the average.
+			 */
+			if (charge_manager_get_supplier() == CHARGE_SUPPLIER_PD)
+				power = max;
+			else
+				power = total / POWER_READINGS;
+			/*
+			 * Calculate gap, and if negative, power
+			 * demand is exceeding configured power budget, so
+			 * throttling is required to reduce the demand.
+			 */
+			gap = charger_mw - power;
+			/*
+			 * Limiting type-A power rear ports.
+			 */
+			if (gap <= 0) {
+				new_state |= THROT_TYPE_A_REAR;
+				headroom_5v_s5 += REAR_DELTA;
+				if (!(current_state & THROT_TYPE_A_REAR))
+					gap += POWER_GAIN_TYPE_A;
+			}
+			/*
+			 * Limiting type-A power front ports.
+			 */
+			if (gap <= 0) {
+				new_state |= THROT_TYPE_A_FRONT;
+				headroom_5v_s5 += FRONT_DELTA;
+				if (!(current_state & THROT_TYPE_A_REAR))
+					gap += POWER_GAIN_TYPE_A;
+			}
+			/*
+			 * If the type-C port is sourcing power,
+			 * check whether it should be throttled.
+			 */
+			if (ppc_is_sourcing_vbus(0) && gap <= 0) {
+				new_state |= THROT_TYPE_C0;
+				headroom_5v_z1 += PWR_Z1_C_HIGH - PWR_Z1_C_LOW;
+				if (!(current_state & THROT_TYPE_C0))
+					gap += POWER_GAIN_TYPE_C;
+			}
+			/*
+			 * If the type-C port is sourcing power,
+			 * check whether it should be throttled.
+			 */
+			if (ppc_is_sourcing_vbus(1) && gap <= 0) {
+				new_state |= THROT_TYPE_C1;
+				headroom_5v_z1 += PWR_Z1_C_HIGH - PWR_Z1_C_LOW;
+				if (!(current_state & THROT_TYPE_C1))
+					gap += POWER_GAIN_TYPE_C;
+			}
+			/*
+			 * If the type-C port is sourcing power,
+			 * check whether it should be throttled.
+			 */
+			if (ppc_is_sourcing_vbus(2) && gap <= 0) {
+				new_state |= THROT_TYPE_C2;
+				headroom_5v_z1 += PWR_Z1_C_HIGH - PWR_Z1_C_LOW;
+				if (!(current_state & THROT_TYPE_C2))
+					gap += POWER_GAIN_TYPE_C;
+			}
+			/*
+			 * As a last resort, turn on PROCHOT to
+			 * throttle the CPU.
+			 */
+			if (gap <= 0)
+				new_state |= THROT_PROCHOT;
+		}
+	}
+	/*
+	 * Check the 5v power usage and if necessary,
+	 * adjust the throttles in priority order.
+	 *
+	 * Either throttle may have already been activated by
+	 * the overall power control.
+	 *
+	 * We rely on the overcurrent detection to inform us
+	 * if the port is in use.
+	 *
+	 *  - If type C not already throttled:
+	 *	* If not overcurrent, prefer to limit type C [1].
+	 *	* If in overcurrentuse:
+	 *		- limit type A first [2]
+	 *		- If necessary, limit type C [3].
+	 *  - If type A not throttled, if necessary limit it [2].
+	 */
+	if (headroom_5v_z1 < 0) {
+		/*
+		 * Check whether type C is not throttled,
+		 * and is not overcurrent.
+		 */
+		if (!((new_state & THROT_TYPE_C0) || usbc_overcurrent)) {
+			/*
+			 * [1] Type C not in overcurrent, throttle it.
+			 */
+			headroom_5v_z1 += PWR_Z1_C_HIGH - PWR_Z1_C_LOW;
+			new_state |= THROT_TYPE_C0;
+		}
+		/*
+		 * [2] If still under-budget, limit type C.
+		 * No need to check if it is already throttled or not.
+		 */
+		if (headroom_5v_z1 < 0)
+			new_state |= THROT_TYPE_C0;
+	}
+	if (headroom_5v_s5 < 0) {
+		/*
+		 * [1] If type A rear not already throttled, and power still
+		 * needed, limit type A rear.
+		 */
+		if (!(new_state & THROT_TYPE_A_REAR) && headroom_5v_s5 < 0) {
+			headroom_5v_s5 += PWR_S5_REAR_HIGH - PWR_S5_REAR_LOW;
+			new_state |= THROT_TYPE_A_REAR;
+		}
+		/*
+		 * [2] If type A front not already throttled, and power still
+		 * needed, limit type A front.
+		 */
+		if (!(new_state & THROT_TYPE_A_FRONT) && headroom_5v_s5 < 0) {
+			headroom_5v_s5 += PWR_S5_FRONT_HIGH - PWR_S5_FRONT_LOW;
+			new_state |= THROT_TYPE_A_FRONT;
+		}
+	}
+	/*
+	 * Turn the throttles on or off if they have changed.
+	 */
+	diff = new_state ^ current_state;
+	current_state = new_state;
+	if (diff & THROT_PROCHOT) {
+		int prochot = (new_state & THROT_PROCHOT) ? 0 : 1;
+
+		gpio_set_level(GPIO_EC_PROCHOT_ODL, prochot);
+	}
+	if (diff & THROT_TYPE_C0) {
+		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C0) ?
+						TYPEC_RP_1A5 :
+						TYPEC_RP_3A0;
+
+		ppc_set_vbus_source_current_limit(0, rp);
+		tcpm_select_rp_value(0, rp);
+		pd_update_contract(0);
+	}
+	if (diff & THROT_TYPE_C1) {
+		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C1) ?
+						TYPEC_RP_1A5 :
+						TYPEC_RP_3A0;
+
+		ppc_set_vbus_source_current_limit(1, rp);
+		tcpm_select_rp_value(1, rp);
+		pd_update_contract(1);
+	}
+	if (diff & THROT_TYPE_C2) {
+		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C2) ?
+						TYPEC_RP_1A5 :
+						TYPEC_RP_3A0;
+
+		ppc_set_vbus_source_current_limit(2, rp);
+		tcpm_select_rp_value(2, rp);
+		pd_update_contract(2);
+	}
+	if (diff & THROT_TYPE_A_REAR) {
+		int typea_bc = (new_state & THROT_TYPE_A_REAR) ? 1 : 0;
+
+		gpio_set_level(GPIO_USB_A_LOW_PWR0_OD, typea_bc);
+		gpio_set_level(GPIO_USB_A_LOW_PWR1_OD, typea_bc);
+	}
+	if (diff & THROT_TYPE_A_FRONT) {
+		int typea_bc = (new_state & THROT_TYPE_A_FRONT) ? 1 : 0;
+
+		gpio_set_level(GPIO_USB_A_LOW_PWR2_OD, typea_bc);
+		gpio_set_level(GPIO_USB_A_LOW_PWR3_OD, typea_bc);
+	}
+	hook_call_deferred(&power_monitor_data, delay);
+}
diff --git a/board/brask/board.h b/board/brask/board.h
new file mode 100644
index 0000000000..cfd7b8b557
--- /dev/null
+++ b/board/brask/board.h
@@ -0,0 +1,207 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Brask board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "compile_time_macros.h"
+
+/* Baseboard features */
+#include "baseboard.h"
+
+#define CONFIG_MP2964
+
+/* Barrel Jack */
+#define DEDICATED_CHARGE_PORT 3
+
+/* HDMI CEC */
+#define CONFIG_CEC
+#define CONFIG_CEC_BITBANG
+#define CEC_GPIO_OUT GPIO_HDMI_CEC_OUT
+#define CEC_GPIO_IN GPIO_HDMI_CEC_IN
+#define CEC_GPIO_PULL_UP GPIO_HDMI_CEC_PULL_UP
+
+/* USB Type A Features */
+#define USB_PORT_COUNT 4
+#define CONFIG_USB_PORT_POWER_DUMB
+
+/* USB Type C and USB PD defines */
+#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
+
+#define CONFIG_IO_EXPANDER
+#define CONFIG_IO_EXPANDER_NCT38XX
+#define CONFIG_IO_EXPANDER_PORT_COUNT 2
+
+#define CONFIG_USB_PD_PPC
+#define CONFIG_USB_PD_TCPM_RT1715
+#define CONFIG_USBC_RETIMER_INTEL_BB
+
+#define CONFIG_USBC_RETIMER_KB800X
+#define CONFIG_KB800X_CUSTOM_XBAR
+#define CONFIG_USBC_PPC_SYV682X
+#undef CONFIG_SYV682X_HV_ILIM
+#define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_5_50
+
+/* TODO: b/177608416 - measure and check these values on brya */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
+
+/* The design should support up to 100W. */
+/* TODO(b/197702356): Set the max PD to 60W now and change it
+ * to 100W after we verify it.
+ */
+#define PD_OPERATING_POWER_MW CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
+#define PD_MAX_POWER_MW 100000
+#define PD_MAX_CURRENT_MA 5000
+#define PD_MAX_VOLTAGE_MV 20000
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
+
+/*
+ * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
+ * signal.
+ */
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
+#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_OD
+#define GPIO_RECOVERY_L_2 GPIO_GSC_EC_RECOVERY_BTN_OD
+
+/* I2C Bus Configuration */
+
+#define I2C_PORT_DP_REDRIVER NPCX_I2C_PORT0_0
+
+#define I2C_PORT_USB_C0_C2_TCPC NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1
+
+#define I2C_PORT_USB_C0_C2_PPC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1
+
+#define I2C_PORT_USB_C0_C2_BC12 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1
+
+#define I2C_PORT_USB_C0_C2_MUX NPCX_I2C_PORT3_0
+#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1
+
+#define I2C_PORT_QI NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+
+#define I2C_ADDR_MP2964_FLAGS 0x20
+
+#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x58
+#define USBC_PORT_C2_BB_RETIMER_I2C_ADDR 0x59
+
+/* Enabling Thunderbolt-compatible mode */
+#define CONFIG_USB_PD_TBT_COMPAT_MODE
+
+/* Enabling USB4 mode */
+#define CONFIG_USB_PD_USB4
+#define CONFIG_USB_PD_DATA_RESET_MSG
+
+/* Retimer */
+#define CONFIG_USBC_RETIMER_FW_UPDATE
+
+/* Thermal features */
+#define CONFIG_THERMISTOR
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_TEMP_SENSOR_POWER
+#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
+
+/* ADC */
+#define CONFIG_ADC
+
+/*
+ * TODO(b/197478860): Enable the fan control. We need
+ * to check the sensor value and adjust the fan speed.
+ */
+#define CONFIG_FANS FAN_CH_COUNT
+
+/* Include math_util for bitmask_uint64 used in pd_timers */
+#define CONFIG_MATH_UTIL
+
+/* WPC/Qi charger */
+#ifdef SECTION_IS_RW
+#define CONFIG_PERIPHERAL_CHARGER
+#define CONFIG_CPS8100
+#endif
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h" /* needed by registers.h */
+#include "registers.h"
+#include "usbc_config.h"
+
+enum charge_port {
+	CHARGE_PORT_TYPEC0,
+	CHARGE_PORT_TYPEC1,
+	CHARGE_PORT_TYPEC2,
+	CHARGE_PORT_BARRELJACK,
+	CHARGE_PORT_ENUM_COUNT
+};
+
+enum adc_channel {
+	ADC_TEMP_SENSOR_1_CPU,
+	ADC_TEMP_SENSOR_2_CPU_VR,
+	ADC_TEMP_SENSOR_3_WIFI,
+	ADC_TEMP_SENSOR_4_DIMM,
+	ADC_VBUS,
+	ADC_PPVAR_IMON, /* ADC3 */
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1_CPU,
+	TEMP_SENSOR_2_CPU_VR,
+	TEMP_SENSOR_3_WIFI,
+	TEMP_SENSOR_4_DIMM,
+	TEMP_SENSOR_COUNT
+};
+
+enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_C2_NCT38XX, IOEX_PORT_COUNT };
+
+enum pwm_channel {
+	PWM_CH_LED_GREEN, /* PWM0 */
+	PWM_CH_FAN, /* PWM5 */
+	PWM_CH_LED_RED, /* PWM2 */
+	PWM_CH_COUNT
+};
+
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT };
+
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT };
+
+enum cec_port { CEC_PORT_0, CEC_PORT_COUNT };
+
+extern void adp_connect_interrupt(enum gpio_signal signal);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/brask/build.mk b/board/brask/build.mk
new file mode 100644
index 0000000000..f180fcb8ef
--- /dev/null
+++ b/board/brask/build.mk
@@ -0,0 +1,22 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Brask board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx9
+CHIP_VARIANT:=npcx9m3f
+BASEBOARD:=brask
+
+board-y=
+board-y+=board.o
+board-y+=fans.o
+board-y+=fw_config.o
+board-y+=i2c.o
+board-y+=led.o
+board-y+=pwm.o
+board-y+=sensors.o
+board-y+=usbc_config.o
diff --git a/board/brask/ec.tasklist b/board/brask/ec.tasklist
new file mode 100644
index 0000000000..3572543743
--- /dev/null
+++ b/board/brask/ec.tasklist
@@ -0,0 +1,29 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ *
+ * USB_CHG_Px tasks must be contiguous (see USB_CHG_PORT_TO_TASK_ID(x)).
+ * PD_Cx tasks must be contiguous (see PD_PORT_TO_TASK_ID(x))
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS_RW(PCHG, pchg_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P2, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C2, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_shared_alert_task, (BIT(2) | BIT(0)), LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CEC, cec_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/brask/fans.c b/board/brask/fans.c
new file mode 100644
index 0000000000..3f3ad3ccea
--- /dev/null
+++ b/board/brask/fans.c
@@ -0,0 +1,50 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Physical fans. These are logically separate from pwm_channels. */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "fan.h"
+#include "fan_chip.h"
+#include "hooks.h"
+#include "pwm.h"
+
+/* MFT channels. These are logically separate from pwm_channels. */
+const struct mft_t mft_channels[] = {
+	[MFT_CH_0] = {
+		.module = NPCX_MFT_MODULE_2,
+		.clk_src = TCKC_LFCLK,
+		.pwm_id = PWM_CH_FAN,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
+
+static const struct fan_conf fan_conf_0 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
+	.pgood_gpio = -1,
+	.enable_gpio = GPIO_EN_PP5000_FAN,
+};
+
+/*
+ * TOOD(b/197478860): need to update for real fan
+ *
+ * Prototype fan spins at about 7200 RPM at 100% PWM.
+ * Set minimum at around 30% PWM.
+ */
+static const struct fan_rpm fan_rpm_0 = {
+	.rpm_min = 2200,
+	.rpm_start = 2200,
+	.rpm_max = 7200,
+};
+
+const struct fan_t fans[FAN_CH_COUNT] = {
+	[FAN_CH_0] = {
+		.conf = &fan_conf_0,
+		.rpm = &fan_rpm_0,
+	},
+};
diff --git a/board/brask/fw_config.c b/board/brask/fw_config.c
new file mode 100644
index 0000000000..3ee71e6a0f
--- /dev/null
+++ b/board/brask/fw_config.c
@@ -0,0 +1,65 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "fw_config.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+static union brask_cbi_fw_config fw_config;
+BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
+
+/*
+ * FW_CONFIG defaults for brask if the CBI.FW_CONFIG data is not
+ * initialized.
+ */
+static const union brask_cbi_fw_config fw_config_defaults = {
+	.audio = DB_NAU88L25B_I2S,
+	.bj_power = BJ_135W,
+};
+
+/*
+ * Barrel-jack power adapter ratings.
+ */
+static const struct {
+	int voltage;
+	int current;
+} bj_power[] = {
+	[BJ_135W] = { /* 0 - 135W (also default) */
+			.voltage = 19500,
+			.current = 6920
+	},
+	[BJ_230W] = { /* 1 - 230W */
+			.voltage = 19500,
+			.current = 11800
+	}
+};
+
+/****************************************************************************
+ * Brask FW_CONFIG access
+ */
+void board_init_fw_config(void)
+{
+	if (cbi_get_fw_config(&fw_config.raw_value)) {
+		CPRINTS("CBI: Read FW_CONFIG failed, using board defaults");
+		fw_config = fw_config_defaults;
+	}
+}
+
+void ec_bj_power(uint32_t *voltage, uint32_t *current)
+{
+	unsigned int bj;
+
+	bj = fw_config.bj_power;
+	/* Out of range value defaults to 0 */
+	if (bj >= ARRAY_SIZE(bj_power))
+		bj = 0;
+	*voltage = bj_power[bj].voltage;
+	*current = bj_power[bj].current;
+}
diff --git a/board/brask/fw_config.h b/board/brask/fw_config.h
new file mode 100644
index 0000000000..95d81f1e05
--- /dev/null
+++ b/board/brask/fw_config.h
@@ -0,0 +1,41 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __BOARD_BRASK_FW_CONFIG_H_
+#define __BOARD_BRASK_FW_CONFIG_H_
+
+#include <stdint.h>
+
+/****************************************************************************
+ * CBI FW_CONFIG layout for Brask board.
+ *
+ * Source of truth is the project/brask/brask/config.star configuration file.
+ */
+enum ec_cfg_audio_type { DB_AUDIO_UNKNOWN = 0, DB_NAU88L25B_I2S = 1 };
+
+enum ec_cfg_bj_power { BJ_135W = 0, BJ_230W = 1 };
+
+union brask_cbi_fw_config {
+	struct {
+		uint32_t audio : 3;
+		uint32_t bj_power : 2;
+		uint32_t reserved_1 : 27;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Read the cached FW_CONFIG.  Guaranteed to have valid values.
+ *
+ * @return the FW_CONFIG for the board.
+ */
+union brask_cbi_fw_config get_fw_config(void);
+
+/**
+ * Get the barrel-jack power from FW_CONFIG.
+ */
+void ec_bj_power(uint32_t *voltage, uint32_t *current);
+
+#endif /* __BOARD_BRASK_FW_CONFIG_H_ */
diff --git a/board/brask/gpio.inc b/board/brask/gpio.inc
new file mode 100644
index 0000000000..5fa07523f6
--- /dev/null
+++ b/board/brask/gpio.inc
@@ -0,0 +1,187 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* INTERRUPT GPIOs: */
+
+GPIO_INT(ACOK_OD,                    PIN(0, 0), GPIO_INT_BOTH, extpower_interrupt)
+GPIO_INT(EC_PROCHOT_IN_L,            PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
+GPIO_INT(EC_WP_ODL,                  PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(GSC_EC_PWR_BTN_ODL,         PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
+GPIO_INT(SEQ_EC_ALL_SYS_PG,          PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_DSW_PWROK,           PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_RSMRST_ODL,          PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,                   PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,                  PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SYS_SLP_S0IX_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(USB_C0_BC12_INT_ODL,        PIN(C, 6), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C0_C2_TCPC_INT_ODL,     PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C0_PPC_INT_ODL,         PIN(6, 2), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C0_RT_INT_ODL,          PIN(B, 1), GPIO_INT_FALLING, retimer_interrupt)
+GPIO_INT(USB_C1_BC12_INT_ODL,        PIN(5, 0), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C1_PPC_INT_ODL,         PIN(F, 5), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C1_TCPC_INT_ODL,        PIN(A, 2), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C2_BC12_INT_ODL,        PIN(8, 3), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C2_PPC_INT_ODL,         PIN(7, 0), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C2_RT_INT_ODL,          PIN(4, 1), GPIO_INT_FALLING, retimer_interrupt)
+GPIO_INT(BJ_ADP_PRESENT_ODL,         PIN(8, 2), GPIO_INT_BOTH | GPIO_PULL_UP, adp_connect_interrupt)
+GPIO_INT(EC_RECOVERY_BTN_OD,         PIN(2, 3), GPIO_INT_BOTH, button_interrupt)
+GPIO_INT(HDMI_CONN_OC_ODL,           PIN(2, 4), GPIO_INPUT | GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(USB_A0_OC_ODL,              PIN(3, 1), GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(USB_A1_OC_ODL,              PIN(3, 0), GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(USB_A2_OC_ODL,              PIN(2, 7), GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(USB_A3_OC_ODL,              PIN(2, 6), GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH, port_ocp_interrupt)
+#ifdef SECTION_IS_RW
+GPIO_INT(QI_INT_ODL,                 PIN(9, 6), GPIO_INT_FALLING, pchg_irq)
+#else
+UNIMPLEMENTED(QI_INT_ODL)
+#endif
+
+/* CCD */
+GPIO(CCD_MODE_ODL,                   PIN(E, 5), GPIO_INPUT)
+
+/* Security */
+GPIO(EC_ENTERING_RW,                 PIN(0, 3), GPIO_OUT_LOW)
+GPIO(EC_GSC_PACKET_MODE,             PIN(7, 5), GPIO_OUT_LOW)
+
+/* Fan */
+GPIO(EN_PP5000_FAN,                  PIN(6, 1), GPIO_OUT_HIGH)
+
+/* ADC, need to check the usage */
+GPIO(ANALOG_PPVAR_PWR_IN_IMON_EC,    PIN(4, 2), GPIO_INPUT)
+
+/* Display */
+GPIO(DP_CONN_OC_ODL,                 PIN(2, 5), GPIO_INPUT)
+
+
+/* BarrelJack */
+GPIO(EN_PPVAR_BJ_ADP_L,              PIN(0, 7), GPIO_OUT_LOW)
+
+/* Chipset PCH */
+GPIO(EC_PCHHOT_ODL,                  PIN(7, 4), GPIO_INPUT)
+GPIO(EC_PCH_INT_ODL,                 PIN(B, 0), GPIO_ODR_HIGH)
+GPIO(EC_PCH_RSMRST_L,                PIN(A, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_RTCRST,                  PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_SYS_PWROK,               PIN(3, 7), GPIO_OUT_LOW)
+GPIO(EC_PCH_WAKE_ODL,                PIN(C, 0), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_ODL,                 PIN(6, 3), GPIO_ODR_HIGH)
+GPIO(EN_S5_RAILS,                    PIN(B, 6), GPIO_OUT_LOW)
+GPIO(PCH_PWROK,                      PIN(7, 2), GPIO_OUT_LOW)
+GPIO(SYS_RST_ODL,                    PIN(C, 5), GPIO_ODR_HIGH)
+GPIO(VCCST_PWRGD_OD,                 PIN(A, 4), GPIO_ODR_LOW)
+GPIO(IMVP9_VRRDY_OD,                 PIN(6, 0), GPIO_INPUT)
+GPIO(CPU_C10_GATE_L,                 PIN(6, 7), GPIO_INPUT)
+
+/* Button */
+GPIO(EC_PCH_PWR_BTN_ODL,             PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(GSC_EC_RECOVERY_BTN_OD,         PIN(2, 2), GPIO_INPUT)
+
+/* NFC */
+/* TODO(b/194068530): Enable NFC */
+GPIO(NFC_COIL_ACT_L,                 PIN(D, 4), GPIO_INPUT)
+GPIO(NFC_LOW_POWER_MODE,             PIN(9, 5), GPIO_OUT_HIGH)
+GPIO(NFC_CARD_DET_L,                 PIN(A, 3), GPIO_INPUT)
+GPIO(EN_NFC_BUZZER,                  PIN(0, 5), GPIO_OUT_LOW)
+
+/* Wireless Charger */
+GPIO(EC_QI_PWR,                      PIN(D, 2), GPIO_OUT_LOW)
+GPIO(QI_RESET_L,                     PIN(9, 3), GPIO_OUT_HIGH)
+
+/* HDMI CEC */
+/* TODO(b/197474873): Enable HDMI CEC */
+GPIO(HDMI_CEC_IN,                    PIN(4, 0), GPIO_INPUT)
+GPIO(HDMI_CEC_OUT,                   PIN(D, 3), GPIO_OUT_HIGH | GPIO_OPEN_DRAIN)
+GPIO(HDMI_CEC_PULL_UP,               PIN(C, 2), GPIO_OUT_HIGH)
+
+/* I2C SCL/SDA */
+GPIO(EC_I2C_QI_SCL,                  PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_QI_SDA,                  PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SCL_R,              PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SDA_R,              PIN(B, 2), GPIO_INPUT)
+GPIO(EC_I2C_DP_SCL,                  PIN(B, 5), GPIO_INPUT)
+GPIO(EC_I2C_DP_SDA,                  PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_PPC_SCL,       PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_PPC_SDA,       PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_RT_SCL,        PIN(D, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_RT_SDA,        PIN(D, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_TCPC_SCL,      PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_TCPC_SDA,      PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_MIX_SCL,          PIN(E, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_MIX_SDA,          PIN(E, 3), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_TCPC_SCL,         PIN(F, 3), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_TCPC_SDA,         PIN(F, 2), GPIO_INPUT)
+
+/* USBA */
+GPIO(EN_PP5000_USBA,                 PIN(D, 7), GPIO_OUT_LOW)
+GPIO(USB_A0_STATUS_L,                PIN(2, 1), GPIO_INPUT)
+GPIO(USB_A1_STATUS_L,                PIN(2, 0), GPIO_INPUT)
+GPIO(USB_A2_STATUS_L,                PIN(1, 7), GPIO_INPUT)
+GPIO(USB_A3_STATUS_L,                PIN(1, 6), GPIO_INPUT)
+GPIO(USB_A_LOW_PWR0_OD,              PIN(1, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(USB_A_LOW_PWR1_OD,              PIN(1, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(USB_A_LOW_PWR2_OD,              PIN(1, 1), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(USB_A_LOW_PWR3_OD,              PIN(1, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(USB_A_OC_SOC_L,                 PIN(8, 0), GPIO_OUT_HIGH)
+
+/* LED */
+/* TODO(b/197471359): LED implementation */
+GPIO(LED_GREEN_L,                    PIN(C, 3), GPIO_OUT_LOW)
+GPIO(LED_RED_L,                      PIN(C, 4), GPIO_OUT_LOW)
+
+/* USBC */
+GPIO(USB_C0_C2_TCPC_RST_ODL,         PIN(A, 7), GPIO_ODR_LOW)
+GPIO(USB_C1_FRS_EN,                  PIN(9, 4), GPIO_OUT_LOW)
+GPIO(USB_C1_RT_INT_ODL,              PIN(A, 0), GPIO_INPUT)
+GPIO(USB_C1_RT_RST_R_L,              PIN(0, 2), GPIO_OUT_LOW)
+
+/* GPIO02_P2 to PU */
+/* GPIO03_P2 to PU */
+IOEX(USB_C0_OC_ODL,          EXPIN(IOEX_C0_NCT38XX, 0, 4), GPIO_ODR_HIGH)
+IOEX(USB_C0_FRS_EN,          EXPIN(IOEX_C0_NCT38XX, 0, 6), GPIO_LOW)
+IOEX(USB_C0_RT_RST_ODL,      EXPIN(IOEX_C0_NCT38XX, 0, 7), GPIO_ODR_LOW)
+
+IOEX(USB_C2_RT_RST_ODL,      EXPIN(IOEX_C2_NCT38XX, 0, 2), GPIO_ODR_LOW)
+IOEX(USB_C1_OC_ODL,          EXPIN(IOEX_C2_NCT38XX, 0, 3), GPIO_ODR_HIGH)
+IOEX(USB_C2_OC_ODL,          EXPIN(IOEX_C2_NCT38XX, 0, 4), GPIO_ODR_HIGH)
+IOEX(USB_C2_FRS_EN,          EXPIN(IOEX_C2_NCT38XX, 0, 6), GPIO_LOW)
+/* GPIO07_P2 to PU */
+
+/* UART alternate functions */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)              /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */
+
+/* I2C alternate functions */
+ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)               /* GPIO33/I2C5_SCL0/CTS_L, GPIO36/RTS_L/I2C5_SDA0 */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)               /* GPIO87/I2C1_SDA0 */
+ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)               /* GPIO92/I2C2_SCL0, GPIO91/I2C2_SDA0, GPIO90/I2C1_SCL0 */
+ALTERNATE(PIN_MASK(B, 0x0c), 0, MODULE_I2C, 0)               /* GPIOB3/I2C7_SCL0/DCD_L, GPIOB2/I2C7_SDA0/DSR_L */
+ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, 0)               /* GPIOB5/I2C0_SCL0, GPIOB4/I2C0_SDA0 */
+ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)               /* GPIOD1/I2C3_SCL0, GPIOD0/I2C3_SDA0 */
+ALTERNATE(PIN_MASK(E, 0x18), 0, MODULE_I2C, 0)               /* GPIOE4/I2C6_SCL1/I3C_SCL, GPIOE3/I2C6_SDA1/I3C_SDA */
+ALTERNATE(PIN_MASK(F, 0x0c), 0, MODULE_I2C, 0)               /* GPIOF3/I2C4_SCL1, GPIOF2/I2C4_SDA1 */
+
+/* PWM alternate functions */
+ALTERNATE(PIN_MASK(7, 0x08), 0, MODULE_PWM, 0)               /* GPIO73/TA2 */
+ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)               /* GPIOB7/PWM5 */
+ALTERNATE(PIN_MASK(C, 0x18), 0, MODULE_PWM, 0)               /* GPIOC4/PWM2, GPIOC3/PWM0 */
+
+/* ADC alternate functions */
+ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0)               /* GPIO34/PS2_DAT2/ADC6 */
+ALTERNATE(PIN_MASK(4, 0x38), 0, MODULE_ADC, 0)               /* GPIO45/ADC0, GPIO44/ADC1, GPIO43/ADC2 */
+ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0)               /* GPIOE1/ADC7 */
+
+/* Unused Pins */
+UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
+UNUSED(PIN(3, 2))       /* GPO32/TRIS_L */
+UNUSED(PIN(3, 5))       /* GPO35/CR_SOUT4/TEST_L */
+UNUSED(PIN(6, 6))       /* GPIO66 */
+UNUSED(PIN(8, 1))       /* GPIO81/PECI_DATA */
+UNUSED(PIN(5, 6))       /* GPIO56/CLKRUN# */
+UNUSED(PIN(9, 7))       /* GPIO97 */
+UNUSED(PIN(8, 6))       /* GPIO86/TXD/CR_SOUT2 */
+UNUSED(PIN(1, 3))       /* KSO06/GPO13/GP_SEL# */
+UNUSED(PIN(1, 2))       /* KSO07/GPO12/JEN# */
+UNUSED(PIN(0, 6))       /* KSO11/GPIO06/P80_CLK */
+UNUSED(PIN(0, 4))       /* KSO13/GPIO04 */
diff --git a/board/brask/i2c.c b/board/brask/i2c.c
new file mode 100644
index 0000000000..b7666edc60
--- /dev/null
+++ b/board/brask/i2c.c
@@ -0,0 +1,77 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "i2c.h"
+
+/* I2C port map configuration */
+const struct i2c_port_t i2c_ports[] = {
+	{
+		/* I2C0 */
+		.name = "dp_redriver",
+		.port = I2C_PORT_DP_REDRIVER,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_DP_SCL,
+		.sda = GPIO_EC_I2C_DP_SDA,
+	},
+	{
+		/* I2C1 */
+		.name = "tcpc0,2",
+		.port = I2C_PORT_USB_C0_C2_TCPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C2_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C2_TCPC_SDA,
+	},
+	{
+		/* I2C2 */
+		.name = "ppc0,2",
+		.port = I2C_PORT_USB_C0_C2_PPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C2_PPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C2_PPC_SDA,
+	},
+	{
+		/* I2C3 */
+		.name = "retimer0,2",
+		.port = I2C_PORT_USB_C0_C2_MUX,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C2_RT_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C2_RT_SDA,
+	},
+	{
+		/* I2C4 C1 TCPC */
+		.name = "tcpc1",
+		.port = I2C_PORT_USB_C1_TCPC,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_USB_C1_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C1_TCPC_SDA,
+	},
+	{
+		/* I2C5 */
+		.name = "wireless_charger",
+		.port = I2C_PORT_QI,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_QI_SCL,
+		.sda = GPIO_EC_I2C_QI_SDA,
+	},
+	{
+		/* I2C6 */
+		.name = "ppc1",
+		.port = I2C_PORT_USB_C1_PPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C1_MIX_SCL,
+		.sda = GPIO_EC_I2C_USB_C1_MIX_SDA,
+	},
+	{
+		/* I2C7 */
+		.name = "eeprom",
+		.port = I2C_PORT_EEPROM,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_MISC_SCL_R,
+		.sda = GPIO_EC_I2C_MISC_SDA_R,
+	},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/board/brask/led.c b/board/brask/led.c
new file mode 100644
index 0000000000..b86a291625
--- /dev/null
+++ b/board/brask/led.c
@@ -0,0 +1,260 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power LED control for Brask.
+ * Solid green - active power
+ * Green flashing - suspended
+ * Red flashing - alert
+ * Solid red - critical
+ */
+
+#include "chipset.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "led_common.h"
+#include "pwm.h"
+#include "timer.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
+
+/*
+ * Due to the CSME-Lite processing, upon startup the CPU transitions through
+ * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so
+ * delay turning off the LED during suspend/shutdown.
+ */
+#define LED_CPU_DELAY_MS (2000 * MSEC)
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED };
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+enum led_color {
+	LED_OFF = 0,
+	LED_RED,
+	LED_GREEN,
+
+	/* Number of colors, not a color itself */
+	LED_COLOR_COUNT
+};
+
+static int set_color_power(enum led_color color, int duty)
+{
+	int green = 0;
+	int red = 0;
+
+	if (duty < 0 || 100 < duty)
+		return EC_ERROR_UNKNOWN;
+
+	switch (color) {
+	case LED_OFF:
+		break;
+	case LED_GREEN:
+		green = 1;
+		break;
+	case LED_RED:
+		red = 1;
+		break;
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+
+	if (red)
+		pwm_set_duty(PWM_CH_LED_RED, duty);
+	else
+		pwm_set_duty(PWM_CH_LED_RED, 0);
+
+	if (green)
+		pwm_set_duty(PWM_CH_LED_GREEN, duty);
+	else
+		pwm_set_duty(PWM_CH_LED_GREEN, 0);
+
+	return EC_SUCCESS;
+}
+
+static int set_color(enum ec_led_id id, enum led_color color, int duty)
+{
+	switch (id) {
+	case EC_LED_ID_POWER_LED:
+		return set_color_power(color, duty);
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+}
+
+#define LED_PULSE_US (2 * SECOND)
+/* 40 msec for nice and smooth transition. */
+#define LED_PULSE_TICK_US (40 * MSEC)
+
+/*
+ * When pulsing is enabled, brightness is incremented by <duty_inc> every
+ * <interval> usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented
+ * likewise in LED_PULSE_US usec.
+ */
+static struct {
+	uint32_t interval;
+	int duty_inc;
+	enum led_color color;
+	int duty;
+} led_pulse;
+
+#define CONFIG_TICK(interval, color) \
+	config_tick((interval), 100 / (LED_PULSE_US / (interval)), (color))
+
+static void config_tick(uint32_t interval, int duty_inc, enum led_color color)
+{
+	led_pulse.interval = interval;
+	led_pulse.duty_inc = duty_inc;
+	led_pulse.color = color;
+	led_pulse.duty = 0;
+}
+
+static void pulse_power_led(enum led_color color)
+{
+	set_color(EC_LED_ID_POWER_LED, color, led_pulse.duty);
+	if (led_pulse.duty + led_pulse.duty_inc > 100)
+		led_pulse.duty_inc = led_pulse.duty_inc * -1;
+	else if (led_pulse.duty + led_pulse.duty_inc < 0)
+		led_pulse.duty_inc = led_pulse.duty_inc * -1;
+	led_pulse.duty += led_pulse.duty_inc;
+}
+
+static void led_tick(void);
+DECLARE_DEFERRED(led_tick);
+static void led_tick(void)
+{
+	uint32_t elapsed;
+	uint32_t next = 0;
+	uint32_t start = get_time().le.lo;
+
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		pulse_power_led(led_pulse.color);
+	elapsed = get_time().le.lo - start;
+	next = led_pulse.interval > elapsed ? led_pulse.interval - elapsed : 0;
+	hook_call_deferred(&led_tick_data, next);
+}
+
+static void led_suspend(void)
+{
+	CONFIG_TICK(LED_PULSE_TICK_US, LED_GREEN);
+	led_tick();
+}
+DECLARE_DEFERRED(led_suspend);
+
+static void led_shutdown(void)
+{
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_OFF, 0);
+}
+DECLARE_DEFERRED(led_shutdown);
+
+static void led_shutdown_hook(void)
+{
+	hook_call_deferred(&led_tick_data, -1);
+	hook_call_deferred(&led_suspend_data, -1);
+	hook_call_deferred(&led_shutdown_data, LED_CPU_DELAY_MS);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, led_shutdown_hook, HOOK_PRIO_DEFAULT);
+
+static void led_suspend_hook(void)
+{
+	hook_call_deferred(&led_shutdown_data, -1);
+	hook_call_deferred(&led_suspend_data, LED_CPU_DELAY_MS);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, led_suspend_hook, HOOK_PRIO_DEFAULT);
+
+static void led_resume(void)
+{
+	/*
+	 * Assume there is no race condition with led_tick, which also
+	 * runs in hook_task.
+	 */
+	hook_call_deferred(&led_tick_data, -1);
+	/*
+	 * Avoid invoking the suspend/shutdown delayed hooks.
+	 */
+	hook_call_deferred(&led_suspend_data, -1);
+	hook_call_deferred(&led_shutdown_data, -1);
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_GREEN, 100);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, led_resume, HOOK_PRIO_DEFAULT);
+
+void led_alert(int enable)
+{
+	if (enable) {
+		/* Overwrite the current signal */
+		config_tick(1 * SECOND, 100, LED_RED);
+		led_tick();
+	} else {
+		/* Restore the previous signal */
+		if (chipset_in_state(CHIPSET_STATE_ON))
+			led_resume();
+		else if (chipset_in_state(CHIPSET_STATE_SUSPEND))
+			led_suspend_hook();
+		else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+			led_shutdown_hook();
+	}
+}
+
+void show_critical_error(void)
+{
+	hook_call_deferred(&led_tick_data, -1);
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_RED, 100);
+}
+
+static int command_led(int argc, const char **argv)
+{
+	enum ec_led_id id = EC_LED_ID_POWER_LED;
+
+	if (argc < 2)
+		return EC_ERROR_PARAM_COUNT;
+
+	if (!strcasecmp(argv[1], "debug")) {
+		led_auto_control(id, !led_auto_control_is_enabled(id));
+		ccprintf("o%s\n", led_auto_control_is_enabled(id) ? "ff" : "n");
+	} else if (!strcasecmp(argv[1], "off")) {
+		set_color(id, LED_OFF, 0);
+	} else if (!strcasecmp(argv[1], "red")) {
+		set_color(id, LED_RED, 100);
+	} else if (!strcasecmp(argv[1], "green")) {
+		set_color(id, LED_GREEN, 100);
+	} else if (!strcasecmp(argv[1], "alert")) {
+		led_alert(1);
+	} else if (!strcasecmp(argv[1], "crit")) {
+		show_critical_error();
+	} else {
+		return EC_ERROR_PARAM1;
+	}
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(led, command_led, "[debug|red|green|off|alert|crit]",
+			"Turn on/off LED.");
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	brightness_range[EC_LED_COLOR_RED] = 100;
+	brightness_range[EC_LED_COLOR_GREEN] = 100;
+}
+
+int led_set_brightness(enum ec_led_id id, const uint8_t *brightness)
+{
+	if (brightness[EC_LED_COLOR_RED])
+		return set_color(id, LED_RED, brightness[EC_LED_COLOR_RED]);
+	else if (brightness[EC_LED_COLOR_GREEN])
+		return set_color(id, LED_GREEN, brightness[EC_LED_COLOR_GREEN]);
+	else
+		return set_color(id, LED_OFF, 0);
+}
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
+{
+	/* Blink alert if insufficient power per system_can_boot_ap(). */
+	int insufficient_power =
+		(charge_ma * charge_mv) <
+		(CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON * 1000);
+	led_alert(insufficient_power);
+}
diff --git a/board/brask/pwm.c b/board/brask/pwm.c
new file mode 100644
index 0000000000..35fc1f5a98
--- /dev/null
+++ b/board/brask/pwm.c
@@ -0,0 +1,39 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "hooks.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_LED_GREEN] = { .channel = 0,
+			       .flags = PWM_CONFIG_ACTIVE_LOW |
+					PWM_CONFIG_DSLEEP,
+			       .freq = 2000 },
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN | PWM_CONFIG_DSLEEP,
+			 .freq = 1000 },
+	[PWM_CH_LED_RED] = { .channel = 2,
+			     .flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+			     .freq = 2000 },
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+static void board_pwm_init(void)
+{
+	/*
+	 * TODO(b/197478860): Turn on the fan at 100% by default
+	 * We need to find tune the fan speed according to the
+	 * thermal sensor value.
+	 */
+	pwm_enable(PWM_CH_FAN, 1);
+	pwm_set_duty(PWM_CH_FAN, 100);
+
+	pwm_enable(PWM_CH_LED_RED, 1);
+	pwm_enable(PWM_CH_LED_GREEN, 1);
+}
+DECLARE_HOOK(HOOK_INIT, board_pwm_init, HOOK_PRIO_DEFAULT);
diff --git a/board/brask/sensors.c b/board/brask/sensors.c
new file mode 100644
index 0000000000..c6b12a84bf
--- /dev/null
+++ b/board/brask/sensors.c
@@ -0,0 +1,114 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc_chip.h"
+#include "common.h"
+#include "hooks.h"
+#include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
+#include "thermal.h"
+
+/* ADC configuration */
+const struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_1_CPU] = {
+		.name = "TEMP_CPU",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_2_CPU_VR] = {
+		.name = "TEMP_CPU_VR",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_3_WIFI] = {
+		.name = "TEMP_WIFI",
+		.input_ch = NPCX_ADC_CH6,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_4_DIMM] = {
+		.name = "TEMP_DIMM",
+		.input_ch = NPCX_ADC_CH7,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_VBUS] = {  /* 5/39 voltage divider */
+		.name = "VBUS",
+		.input_ch = NPCX_ADC_CH2,
+		.factor_mul = ADC_MAX_VOLT * 39,
+		.factor_div = (ADC_READ_MAX + 1) * 5,
+	},
+	[ADC_PPVAR_IMON] = {  /* 872.3 mV/A */
+		.name = "PPVAR_IMON",
+		.input_ch = NPCX_ADC_CH3,
+		.factor_mul = ADC_MAX_VOLT * 1433,
+		.factor_div = (ADC_READ_MAX + 1) * 1250,
+	},
+
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* Temperature sensor configuration */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1_CPU] = { .name = "CPU",
+				.type = TEMP_SENSOR_TYPE_BOARD,
+				.read = get_temp_3v3_30k9_47k_4050b,
+				.idx = ADC_TEMP_SENSOR_1_CPU },
+	[TEMP_SENSOR_2_CPU_VR] = { .name = "CPU VR",
+				   .type = TEMP_SENSOR_TYPE_BOARD,
+				   .read = get_temp_3v3_30k9_47k_4050b,
+				   .idx = ADC_TEMP_SENSOR_2_CPU_VR },
+	[TEMP_SENSOR_3_WIFI] = { .name = "WIFI",
+				 .type = TEMP_SENSOR_TYPE_BOARD,
+				 .read = get_temp_3v3_30k9_47k_4050b,
+				 .idx = ADC_TEMP_SENSOR_3_WIFI },
+	[TEMP_SENSOR_4_DIMM] = { .name = "DIMM",
+				 .type = TEMP_SENSOR_TYPE_BOARD,
+				 .read = get_temp_3v3_30k9_47k_4050b,
+				 .idx = ADC_TEMP_SENSOR_4_DIMM },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/*
+ * TODO(b/180681346): update for Alder Lake/brya
+ *
+ * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
+ * 130 C.  However, sensor is located next to DDR, so we need to use the lower
+ * DDR temperature limit (85 C)
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+		}, \
+		.temp_fan_off = C_TO_K(35), \
+		.temp_fan_max = C_TO_K(50), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
+
+/*
+ * TODO(b/197478860): add the thermal sensor setting
+ */
+/* this should really be "const" */
+struct ec_thermal_config thermal_params[] = {
+	[TEMP_SENSOR_1_CPU] = THERMAL_CPU,
+	[TEMP_SENSOR_2_CPU_VR] = THERMAL_CPU,
+	[TEMP_SENSOR_3_WIFI] = THERMAL_CPU,
+	[TEMP_SENSOR_4_DIMM] = THERMAL_CPU,
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
diff --git a/board/brask/usbc_config.c b/board/brask/usbc_config.c
new file mode 100644
index 0000000000..b28f6dc28d
--- /dev/null
+++ b/board/brask/usbc_config.c
@@ -0,0 +1,416 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/bc12/pi3usb9201_public.h"
+#include "driver/ppc/syv682x_public.h"
+#include "driver/retimer/bb_retimer_public.h"
+#include "driver/retimer/kb800x.h"
+#include "driver/tcpm/nct38xx.h"
+#include "driver/tcpm/rt1715.h"
+#include "driver/tcpm/tcpci.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "ioexpander.h"
+#include "system.h"
+#include "task.h"
+#include "task_id.h"
+#include "timer.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+/* USBC TCPC configuration */
+const struct tcpc_config_t tcpc_config[] = {
+	[USBC_PORT_C0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0_C2_TCPC,
+			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_NO_DEBUG_ACC_CONTROL,
+	},
+	[USBC_PORT_C1] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C1_TCPC,
+			.addr_flags = RT1715_I2C_ADDR_FLAGS,
+		},
+		.drv = &rt1715_tcpm_drv,
+	},
+	[USBC_PORT_C2] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0_C2_TCPC,
+			.addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
+BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
+
+/* USBC PPC configuration */
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_C2_PPC,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.drv = &syv682x_drv,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C1_PPC,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.drv = &syv682x_drv,
+	},
+	[USBC_PORT_C2] = {
+		.i2c_port = I2C_PORT_USB_C0_C2_PPC,
+		.i2c_addr_flags = SYV682X_ADDR2_FLAGS,
+		.drv = &syv682x_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
+
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/* USBC mux configuration - Alder Lake includes internal mux */
+static const struct usb_mux_chain usbc0_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+static const struct usb_mux_chain usbc1_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+static const struct usb_mux_chain usbc2_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C2,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+
+struct kb800x_control_t kb800x_control[] = {
+	[USBC_PORT_C0] = {
+	},
+	[USBC_PORT_C1] = {
+		.retimer_rst_gpio = GPIO_USB_C1_RT_RST_R_L,
+		.ss_lanes = {
+			[KB800X_A0] = KB800X_TX0, [KB800X_A1] = KB800X_RX0,
+			[KB800X_B0] = KB800X_RX1, [KB800X_B1] = KB800X_TX1,
+			[KB800X_C0] = KB800X_RX0, [KB800X_C1] = KB800X_TX0,
+			[KB800X_D0] = KB800X_TX1, [KB800X_D1] = KB800X_RX1,
+			}
+	},
+	[USBC_PORT_C2] = {
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(kb800x_control) == USBC_PORT_COUNT);
+
+const struct usb_mux_chain usb_muxes[] = {
+	[USBC_PORT_C0] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C0_C2_MUX,
+			.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc0_tcss_usb_mux,
+	},
+	[USBC_PORT_C1] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &kb800x_usb_mux_driver,
+			.i2c_port = I2C_PORT_USB_C1_MUX,
+			.i2c_addr_flags = KB800X_I2C_ADDR0_FLAGS,
+		},
+		.next = &usbc1_tcss_usb_mux,
+	},
+	[USBC_PORT_C2] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C2,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C0_C2_MUX,
+			.i2c_addr_flags = USBC_PORT_C2_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc2_tcss_usb_mux,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
+
+/* BC1.2 charger detect configuration */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_C2_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C1_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+	[USBC_PORT_C2] = {
+		.i2c_port = I2C_PORT_USB_C0_C2_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_1_FLAGS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
+
+/*
+ * USB C0 and C2 uses burnside bridge chips and have their reset
+ * controlled by their respective TCPC chips acting as GPIO expanders.
+ *
+ * ioex_init() is normally called before we take the TCPCs out of
+ * reset, so we need to start in disabled mode, then explicitly
+ * call ioex_init().
+ */
+
+struct ioexpander_config_t ioex_config[] = {
+	[IOEX_C0_NCT38XX] = {
+		.i2c_host_port = I2C_PORT_USB_C0_C2_TCPC,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
+	},
+	[IOEX_C2_NCT38XX] = {
+		.i2c_host_port = I2C_PORT_USB_C0_C2_TCPC,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT);
+
+__override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
+{
+	enum ioex_signal rst_signal;
+
+	if (me->usb_port == USBC_PORT_C0) {
+		rst_signal = IOEX_USB_C0_RT_RST_ODL;
+	} else if (me->usb_port == USBC_PORT_C2) {
+		rst_signal = IOEX_USB_C2_RT_RST_ODL;
+	} else {
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * We do not have a load switch for the burnside bridge chips,
+	 * so we only need to sequence reset.
+	 */
+
+	if (enable) {
+		/*
+		 * Tpw, minimum time from VCC to RESET_N de-assertion is 100us.
+		 * For boards that don't provide a load switch control, the
+		 * retimer_init() function ensures power is up before calling
+		 * this function.
+		 */
+		ioex_set_level(rst_signal, 1);
+		/*
+		 * Allow 1ms time for the retimer to power up lc_domain
+		 * which powers I2C controller within retimer
+		 */
+		msleep(1);
+	} else {
+		ioex_set_level(rst_signal, 0);
+		msleep(1);
+	}
+	return EC_SUCCESS;
+}
+
+__override int bb_retimer_reset(const struct usb_mux *me)
+{
+	/*
+	 * TODO(b/193402306, b/195375738): Remove this once transition to
+	 * QS Silicon is complete
+	 */
+	bb_retimer_power_enable(me, false);
+	msleep(5);
+	bb_retimer_power_enable(me, true);
+	msleep(25);
+
+	return EC_SUCCESS;
+}
+
+void board_reset_pd_mcu(void)
+{
+	enum gpio_signal tcpc_rst;
+
+	tcpc_rst = GPIO_USB_C0_C2_TCPC_RST_ODL;
+
+	/*
+	 * TODO(b/179648104): figure out correct timing
+	 */
+
+	gpio_set_level(tcpc_rst, 0);
+	gpio_set_level(GPIO_USB_C1_RT_RST_R_L, 0);
+
+	/*
+	 * delay for power-on to reset-off and min. assertion time
+	 */
+
+	msleep(20);
+
+	gpio_set_level(tcpc_rst, 1);
+	gpio_set_level(GPIO_USB_C1_RT_RST_R_L, 1);
+
+	/* wait for chips to come up */
+
+	msleep(50);
+}
+
+static void enable_ioex(int ioex)
+{
+	ioex_init(ioex);
+}
+
+static void board_tcpc_init(void)
+{
+	/* Don't reset TCPCs after initial reset */
+	if (!system_jumped_late()) {
+		board_reset_pd_mcu();
+
+		/*
+		 * These IO expander pins are implemented using the
+		 * C0/C2 TCPC, so they must be set up after the TCPC has
+		 * been taken out of reset.
+		 */
+		enable_ioex(IOEX_C0_NCT38XX);
+		enable_ioex(IOEX_C2_NCT38XX);
+	}
+
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C2_PPC_INT_ODL);
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_C2_TCPC_INT_ODL);
+
+	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (gpio_get_level(GPIO_USB_C0_C2_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_0 | PD_STATUS_TCPC_ALERT_2;
+
+	if (gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
+
+int ppc_get_alert_status(int port)
+{
+	if (port == USBC_PORT_C0)
+		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
+	else if (port == USBC_PORT_C1)
+		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
+	else if (port == USBC_PORT_C2)
+		return gpio_get_level(GPIO_USB_C2_PPC_INT_ODL) == 0;
+	return 0;
+}
+
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_C2_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C1);
+		break;
+	default:
+		break;
+	}
+}
+
+void bc12_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_BC12_INT_ODL:
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+		break;
+	case GPIO_USB_C1_BC12_INT_ODL:
+		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+		break;
+	case GPIO_USB_C2_BC12_INT_ODL:
+		usb_charger_task_set_event(2, USB_CHG_EVENT_BC12);
+		break;
+	default:
+		break;
+	}
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C1);
+		break;
+	case GPIO_USB_C2_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C2);
+		break;
+	default:
+		break;
+	}
+}
+
+void retimer_interrupt(enum gpio_signal signal)
+{
+	/*
+	 * TODO(b/179513527): add USB-C support
+	 */
+}
+
+__override bool board_is_dts_port(int port)
+{
+	return port == USBC_PORT_C0;
+}
+
+__override bool board_is_tbt_usb4_port(int port)
+{
+	return true;
+}
+
+__override enum tbt_compat_cable_speed board_get_max_tbt_speed(int port)
+{
+	if (!board_is_tbt_usb4_port(port))
+		return TBT_SS_RES_0;
+
+	return TBT_SS_TBT_GEN3;
+}
diff --git a/board/brask/usbc_config.h b/board/brask/usbc_config.h
new file mode 100644
index 0000000000..0d4f62651a
--- /dev/null
+++ b/board/brask/usbc_config.h
@@ -0,0 +1,20 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Brya board-specific USB-C configuration */
+
+#ifndef __CROS_EC_USBC_CONFIG_H
+#define __CROS_EC_USBC_CONFIG_H
+
+#define CONFIG_USB_PD_PORT_MAX_COUNT 3
+
+enum usbc_port {
+	USBC_PORT_C0 = 0,
+	USBC_PORT_C1,
+	USBC_PORT_C2,
+	USBC_PORT_COUNT
+};
+
+#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/brask/vif_override.xml b/board/brask/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/brask/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/brya/battery.c b/board/brya/battery.c
new file mode 100644
index 0000000000..71b46082d8
--- /dev/null
+++ b/board/brya/battery.c
@@ -0,0 +1,109 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "cbi.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "gpio.h"
+/*
+ * Battery info for all Brya battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	/* POW-TECH GQA05 Battery Information */
+	[BATTERY_POWER_TECH] = {
+		/* BQ40Z50 Fuel Gauge */
+		.fuel_gauge = {
+			.manuf_name = "POW-TECH",
+			.device_name = "BATGQA05L22",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x00,
+				.reg_mask = 0x2000,		/* XDSG */
+				.disconnect_val = 0x2000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= TARGET_WITH_MARGIN(13050, 5),
+			.voltage_normal		= 11400, /* mV */
+			.voltage_min		= 9000, /* mV */
+			.precharge_current	= 280,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 45,
+			.charging_min_c		= 0,
+			.charging_max_c		= 45,
+			.discharging_min_c	= -10,
+			.discharging_max_c	= 60,
+		},
+	},
+	/* LGC L17L3PB0 Battery Information */
+	/*
+	 * Battery info provided by ODM on b/143477210, comment #11
+	 */
+	[BATTERY_LGC011] = {
+		.fuel_gauge = {
+			.manuf_name = "LGC",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr = 0x0,
+				.reg_mask = 0x6000,
+				.disconnect_val = 0x6000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= TARGET_WITH_MARGIN(13200, 5),
+			.voltage_normal		= 11550, /* mV */
+			.voltage_min		= 9000, /* mV */
+			.precharge_current	= 256,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 45,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= 0,
+			.discharging_max_c	= 75,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_POWER_TECH;
+
+enum battery_present battery_hw_present(void)
+{
+	enum gpio_signal batt_pres;
+
+	batt_pres = GPIO_EC_BATT_PRES_ODL;
+
+	/* The GPIO is low when the battery is physically present */
+	return gpio_get_level(batt_pres) ? BP_NO : BP_YES;
+}
diff --git a/board/brya/board.c b/board/brya/board.c
new file mode 100644
index 0000000000..66c25e0641
--- /dev/null
+++ b/board/brya/board.c
@@ -0,0 +1,58 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "button.h"
+#include "cbi.h"
+#include "charge_ramp.h"
+#include "charger.h"
+#include "common.h"
+#include "console.h"
+#include "driver/accel_lis2dw12.h"
+#include "driver/accelgyro_lsm6dso.h"
+#include "driver/als_tcs3400.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "registers.h"
+#include "switch.h"
+#include "tablet_mode.h"
+#include "throttle_ap.h"
+#include "usbc_config.h"
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* Console output macros */
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+
+__override void board_cbi_init(void)
+{
+	config_usb_db_type();
+}
+
+/* Called on AP S3 -> S0 transition */
+static void board_chipset_resume(void)
+{
+	/* Allow keyboard backlight to be enabled */
+
+	if (IS_ENABLED(CONFIG_PWM_KBLIGHT))
+		gpio_set_level(GPIO_EC_KB_BL_EN_L, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S0 -> S3 transition */
+static void board_chipset_suspend(void)
+{
+	/* Turn off the keyboard backlight if it's on. */
+
+	if (IS_ENABLED(CONFIG_PWM_KBLIGHT))
+		gpio_set_level(GPIO_EC_KB_BL_EN_L, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
diff --git a/board/brya/board.h b/board/brya/board.h
new file mode 100644
index 0000000000..8b0aceb93b
--- /dev/null
+++ b/board/brya/board.h
@@ -0,0 +1,267 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Brya board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "compile_time_macros.h"
+
+/*
+ * Early brya boards are not set up for vivaldi
+ */
+#undef CONFIG_KEYBOARD_VIVALDI
+
+/* Baseboard features */
+#include "baseboard.h"
+
+/*
+ * This will happen automatically on NPCX9 ES2 and later. Do not remove
+ * until we can confirm all earlier chips are out of service.
+ */
+#define CONFIG_HIBERNATE_PSL_VCC1_RST_WAKEUP
+
+#define CONFIG_MP2964
+
+/* LED */
+#define CONFIG_LED_PWM
+#define CONFIG_LED_PWM_COUNT 2
+#undef CONFIG_LED_PWM_NEAR_FULL_COLOR
+#undef CONFIG_LED_PWM_SOC_ON_COLOR
+#undef CONFIG_LED_PWM_SOC_SUSPEND_COLOR
+#undef CONFIG_LED_PWM_LOW_BATT_COLOR
+#define CONFIG_LED_PWM_NEAR_FULL_COLOR EC_LED_COLOR_WHITE
+#define CONFIG_LED_PWM_SOC_ON_COLOR EC_LED_COLOR_WHITE
+#define CONFIG_LED_PWM_SOC_SUSPEND_COLOR EC_LED_COLOR_WHITE
+#define CONFIG_LED_PWM_LOW_BATT_COLOR EC_LED_COLOR_AMBER
+
+/* Sensors */
+#define CONFIG_ACCELGYRO_LSM6DSO /* Base accel */
+#define CONFIG_ACCEL_LSM6DSO_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+/* TCS3400 ALS */
+#define CONFIG_ALS
+#define ALS_COUNT 1
+#define CONFIG_ALS_TCS3400
+#define CONFIG_ALS_TCS3400_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS)
+
+/* Enable sensor fifo, must also define the _SIZE and _THRES */
+#define CONFIG_ACCEL_FIFO
+/* FIFO size is in power of 2. */
+#define CONFIG_ACCEL_FIFO_SIZE 256
+/* Depends on how fast the AP boots and typical ODRs */
+#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
+
+/* Sensors without hardware interrupt are in forced mode */
+#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(CLEAR_ALS)
+
+/* Lid accel */
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_UPDATE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+#define CONFIG_ACCEL_LIS2DWL
+#define CONFIG_ACCEL_LIS2DW12_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
+
+/* Sensor console commands */
+#define CONFIG_CMD_ACCELS
+#define CONFIG_CMD_ACCEL_INFO
+
+/* USB Type A Features */
+#define USB_PORT_COUNT 1
+#define CONFIG_USB_PORT_POWER_DUMB
+
+/* USB Type C and USB PD defines */
+#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
+
+#define CONFIG_IO_EXPANDER
+#define CONFIG_IO_EXPANDER_NCT38XX
+#define CONFIG_IO_EXPANDER_PORT_COUNT 2
+
+#define CONFIG_USB_PD_FRS_PPC
+
+#define CONFIG_USB_PD_TCPM_PS8815
+#define CONFIG_USB_PD_TCPM_PS8815_FORCE_DID
+#define CONFIG_USBC_RETIMER_INTEL_BB
+
+/* I2C speed console command */
+#define CONFIG_CMD_I2C_SPEED
+
+/* I2C control host command */
+#define CONFIG_HOSTCMD_I2C_CONTROL
+
+#define CONFIG_USBC_PPC_SYV682X
+#define CONFIG_USBC_PPC_NX20P3483
+
+/* TODO: b/177608416 - measure and check these values on brya */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
+
+/*
+ * Passive USB-C cables only support up to 60W.
+ */
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
+
+/*
+ * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
+ * signal.
+ */
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
+
+/* System has back-lit keyboard */
+#define CONFIG_PWM_KBLIGHT
+
+/* I2C Bus Configuration */
+
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+
+#define I2C_PORT_USB_C0_C2_TCPC NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1
+
+#define I2C_PORT_USB_C0_C2_PPC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1
+
+#define I2C_PORT_USB_C0_C2_BC12 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1
+
+#define I2C_PORT_USB_C0_C2_MUX NPCX_I2C_PORT3_0
+#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1
+
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+
+#define I2C_ADDR_MP2964_FLAGS 0x20
+
+/*
+ * see b/174768555#comment22
+ */
+#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x56
+#define USBC_PORT_C2_BB_RETIMER_I2C_ADDR 0x57
+
+/* Enabling Thunderbolt-compatible mode */
+#define CONFIG_USB_PD_TBT_COMPAT_MODE
+
+/* Enabling USB4 mode */
+#define CONFIG_USB_PD_USB4
+#define CONFIG_USB_PD_DATA_RESET_MSG
+
+/* Retimer */
+#define CONFIG_USBC_RETIMER_FW_UPDATE
+
+/* Thermal features */
+#define CONFIG_THERMISTOR
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_TEMP_SENSOR_POWER
+#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
+
+#define CONFIG_FANS FAN_CH_COUNT
+
+/* Charger defines */
+#define CONFIG_CHARGER_BQ25720
+#define CONFIG_CHARGER_BQ25720_VSYS_TH2_CUSTOM
+#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV 70
+#define CONFIG_CHARGE_RAMP_SW
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10
+#define CONFIG_CHARGER_BQ25710_PSYS_SENSING
+
+/*
+ * Older boards have a different ADC assignment.
+ */
+
+#define CONFIG_ADC_CHANNELS_RUNTIME_CONFIG
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h" /* needed by registers.h */
+#include "registers.h"
+#include "usbc_config.h"
+
+enum adc_channel {
+	ADC_TEMP_SENSOR_1_DDR_SOC,
+	ADC_TEMP_SENSOR_2_AMBIENT,
+	ADC_TEMP_SENSOR_3_CHARGER,
+	ADC_TEMP_SENSOR_4_WWAN,
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1_DDR_SOC,
+	TEMP_SENSOR_2_AMBIENT,
+	TEMP_SENSOR_3_CHARGER,
+	TEMP_SENSOR_4_WWAN,
+	TEMP_SENSOR_COUNT
+};
+
+enum sensor_id {
+	LID_ACCEL = 0,
+	BASE_ACCEL,
+	BASE_GYRO,
+	CLEAR_ALS,
+	RGB_ALS,
+	SENSOR_COUNT
+};
+
+enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_C2_NCT38XX, IOEX_PORT_COUNT };
+
+enum battery_type { BATTERY_POWER_TECH, BATTERY_LGC011, BATTERY_TYPE_COUNT };
+
+enum pwm_channel {
+	PWM_CH_LED2 = 0, /* PWM0 (white charger) */
+	PWM_CH_LED3, /* PWM1 (orange on DB) */
+	PWM_CH_LED1, /* PWM2 (orange charger) */
+	PWM_CH_KBLIGHT, /* PWM3 */
+	PWM_CH_FAN, /* PWM5 */
+	PWM_CH_LED4, /* PWM7 (white on DB) */
+	PWM_CH_COUNT
+};
+
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT };
+
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT };
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/brya/build.mk b/board/brya/build.mk
new file mode 100644
index 0000000000..bc3e3cd31e
--- /dev/null
+++ b/board/brya/build.mk
@@ -0,0 +1,25 @@
+# -*- makefile -*-
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Brya board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx9
+CHIP_VARIANT:=npcx9m3f
+BASEBOARD:=brya
+
+board-y=
+board-y+=battery.o
+board-y+=board.o
+board-y+=charger.o
+board-y+=fans.o
+board-y+=fw_config.o
+board-y+=i2c.o
+board-y+=keyboard.o
+board-y+=led.o
+board-y+=pwm.o
+board-y+=sensors.o
+board-y+=usbc_config.o
diff --git a/board/brya/charger.c b/board/brya/charger.c
new file mode 100644
index 0000000000..827152e115
--- /dev/null
+++ b/board/brya/charger.c
@@ -0,0 +1,82 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/charger/bq25710.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+#ifndef CONFIG_ZEPHYR
+/* Charger Chip Configuration */
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = BQ25710_SMBUS_ADDR1_FLAGS,
+		.drv = &bq25710_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CHARGER_NUM);
+#endif
+
+int board_set_active_charge_port(int port)
+{
+	int is_valid_port = board_is_usb_pd_port_present(port);
+	int i;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTSUSB("Disabling all charger ports");
+
+		/* Disable all ports. */
+		for (i = 0; i < ppc_cnt; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (ppc_vbus_sink_enable(i, 0))
+				CPRINTSUSB("Disabling C%d as sink failed.", i);
+		}
+
+		return EC_SUCCESS;
+	} else if (!is_valid_port) {
+		return EC_ERROR_INVAL;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (ppc_is_sourcing_vbus(port)) {
+		CPRINTFUSB("Skip enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTSUSB("New charge port: C%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < ppc_cnt; i++) {
+		if (i == port)
+			continue;
+
+		if (ppc_vbus_sink_enable(i, 0))
+			CPRINTSUSB("C%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTSUSB("C%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/board/brya/ec.tasklist b/board/brya/ec.tasklist
new file mode 100644
index 0000000000..3b94575196
--- /dev/null
+++ b/board/brya/ec.tasklist
@@ -0,0 +1,32 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ *
+ * USB_CHG_Px tasks must be contiguous (see USB_CHG_PORT_TO_TASK_ID(x)).
+ * PD_Cx tasks must be contiguous (see PD_PORT_TO_TASK_ID(x))
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, HOOKS_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, BASEBOARD_CHG_RAMP_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P2, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, BASEBOARD_CHARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, BASEBOARD_CHIPSET_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, CONSOLE_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, BASEBOARD_POWERBTN_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C2, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_shared_alert_task, (BIT(2) | BIT(0)), BASEBOARD_PD_INT_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, BASEBOARD_PD_INT_TASK_STACK_SIZE)
diff --git a/board/brya/fans.c b/board/brya/fans.c
new file mode 100644
index 0000000000..ff8f27c69e
--- /dev/null
+++ b/board/brya/fans.c
@@ -0,0 +1,89 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Physical fans. These are logically separate from pwm_channels. */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "fan.h"
+#include "fan_chip.h"
+#include "hooks.h"
+#include "pwm.h"
+
+/* MFT channels. These are logically separate from pwm_channels. */
+const struct mft_t mft_channels[] = {
+	[MFT_CH_0] = {
+		.module = NPCX_MFT_MODULE_1,
+		.clk_src = TCKC_LFCLK,
+		.pwm_id = PWM_CH_FAN,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
+
+static const struct fan_conf fan_conf_0 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
+	.pgood_gpio = -1,
+	.enable_gpio = GPIO_EN_PP5000_FAN,
+};
+
+/*
+ * TOOD(b/181271666): thermistor placement and calibration
+ *
+ * Prototype fan spins at about 4200 RPM at 100% PWM, this
+ * is specific to board ID 2 and might also apears in later
+ * boards as well.
+ */
+static const struct fan_rpm fan_rpm_0 = {
+	.rpm_min = 2200,
+	.rpm_start = 2200,
+	.rpm_max = 4200,
+};
+
+const struct fan_t fans[FAN_CH_COUNT] = {
+	[FAN_CH_0] = {
+		.conf = &fan_conf_0,
+		.rpm = &fan_rpm_0,
+	},
+};
+
+#ifndef CONFIG_FANS
+
+/*
+ * TODO(b/181271666): use static fan speeds until fan and sensors are
+ * tuned. for now, use:
+ *
+ *   AP off:  33%
+ *   AP  on: 100%
+ */
+
+static void fan_slow(void)
+{
+	const int duty_pct = 33;
+
+	ccprints("%s: speed %d%%", __func__, duty_pct);
+
+	pwm_enable(PWM_CH_FAN, 1);
+	pwm_set_duty(PWM_CH_FAN, duty_pct);
+}
+
+static void fan_max(void)
+{
+	const int duty_pct = 100;
+
+	ccprints("%s: speed %d%%", __func__, duty_pct);
+
+	pwm_enable(PWM_CH_FAN, 1);
+	pwm_set_duty(PWM_CH_FAN, duty_pct);
+}
+
+DECLARE_HOOK(HOOK_INIT, fan_slow, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, fan_slow, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, fan_slow, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_RESET, fan_max, HOOK_PRIO_FIRST);
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, fan_max, HOOK_PRIO_DEFAULT);
+
+#endif /* CONFIG_FANS */
diff --git a/board/brya/fw_config.c b/board/brya/fw_config.c
new file mode 100644
index 0000000000..3a4c91acf1
--- /dev/null
+++ b/board/brya/fw_config.c
@@ -0,0 +1,46 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "fw_config.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+static union brya_cbi_fw_config fw_config;
+BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
+
+/*
+ * FW_CONFIG defaults for brya if the CBI.FW_CONFIG data is not
+ * initialized.
+ */
+static const union brya_cbi_fw_config fw_config_defaults = {
+	.usb_db = DB_USB3_PS8815,
+	.kb_bl = KEYBOARD_BACKLIGHT_ENABLED,
+};
+
+/****************************************************************************
+ * Brya FW_CONFIG access
+ */
+void board_init_fw_config(void)
+{
+	if (cbi_get_fw_config(&fw_config.raw_value)) {
+		CPRINTS("CBI: Read FW_CONFIG failed, using board defaults");
+		fw_config = fw_config_defaults;
+	}
+}
+
+union brya_cbi_fw_config get_fw_config(void)
+{
+	return fw_config;
+}
+
+enum ec_cfg_usb_db_type ec_cfg_usb_db_type(void)
+{
+	return fw_config.usb_db;
+}
diff --git a/board/brya/fw_config.h b/board/brya/fw_config.h
new file mode 100644
index 0000000000..fea6c9a8da
--- /dev/null
+++ b/board/brya/fw_config.h
@@ -0,0 +1,54 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __BOARD_BRYA_FW_CONFIG_H_
+#define __BOARD_BRYA_FW_CONFIG_H_
+
+#include <stdint.h>
+
+/****************************************************************************
+ * CBI FW_CONFIG layout for Brya board.
+ *
+ * Source of truth is the project/brya/brya/config.star configuration file.
+ */
+
+enum ec_cfg_usb_db_type {
+	DB_USB_ABSENT = 0,
+	DB_USB3_PS8815 = 1,
+	DB_USB_ABSENT2 = 15
+};
+
+enum ec_cfg_keyboard_backlight_type {
+	KEYBOARD_BACKLIGHT_DISABLED = 0,
+	KEYBOARD_BACKLIGHT_ENABLED = 1
+};
+
+union brya_cbi_fw_config {
+	struct {
+		enum ec_cfg_usb_db_type usb_db : 4;
+		uint32_t sd_db : 2;
+		uint32_t lte_db : 1;
+		enum ec_cfg_keyboard_backlight_type kb_bl : 1;
+		uint32_t audio : 3;
+		uint32_t reserved_1 : 21;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Read the cached FW_CONFIG.  Guaranteed to have valid values.
+ *
+ * @return the FW_CONFIG for the board.
+ */
+union brya_cbi_fw_config get_fw_config(void);
+
+/**
+ * Get the USB daughter board type from FW_CONFIG.
+ *
+ * @return the USB daughter board type.
+ */
+enum ec_cfg_usb_db_type ec_cfg_usb_db_type(void);
+
+#endif /* __BOARD_BRYA_FW_CONFIG_H_ */
diff --git a/board/brya/generated-gpio.inc b/board/brya/generated-gpio.inc
new file mode 100644
index 0000000000..f4772188a5
--- /dev/null
+++ b/board/brya/generated-gpio.inc
@@ -0,0 +1,125 @@
+/*
+ * This file was auto-generated.
+ */
+
+/* INTERRUPT GPIOs: */
+GPIO_INT(ACOK_OD,                        PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
+GPIO_INT(EC_ACCEL_INT_R_L,               PIN(8, 1), GPIO_SEL_1P8V | GPIO_INT_FALLING, lis2dw12_interrupt)
+GPIO_INT(EC_ALS_RGB_INT_R_L,             PIN(D, 4), GPIO_INT_FALLING, tcs3400_interrupt)
+GPIO_INT(EC_IMU_INT_R_L,                 PIN(5, 6), GPIO_SEL_1P8V | GPIO_INT_FALLING, lsm6dso_interrupt)
+GPIO_INT(EC_PROCHOT_IN_L,                PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
+GPIO_INT(EC_VOLDN_BTN_ODL,               PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(EC_VOLUP_BTN_ODL,               PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(EC_WP_ODL,                      PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(GSC_EC_PWR_BTN_ODL,             PIN(0, 1), GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW, power_button_interrupt)
+GPIO_INT(LID_OPEN,                       PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
+GPIO_INT(SEQ_EC_ALL_SYS_PG,              PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_DSW_PWROK,               PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_RSMRST_ODL,              PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,                       PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,                      PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SYS_SLP_S0IX_L,                 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(TABLET_MODE_L,                  PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
+GPIO_INT(USB_C0_BC12_INT_ODL,            PIN(C, 6), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C0_C2_TCPC_INT_ODL,         PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C0_PPC_INT_ODL,             PIN(6, 2), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C0_RT_INT_ODL,              PIN(B, 1), GPIO_INT_FALLING, retimer_interrupt)
+GPIO_INT(USB_C1_BC12_INT_ODL,            PIN(5, 0), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C1_PPC_INT_ODL,             PIN(F, 5), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C1_TCPC_INT_ODL,            PIN(A, 2), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C2_BC12_INT_ODL,            PIN(8, 3), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C2_PPC_INT_ODL,             PIN(7, 0), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C2_RT_INT_ODL,              PIN(4, 1), GPIO_INT_FALLING, retimer_interrupt)
+
+/* USED GPIOs: */
+GPIO(CCD_MODE_ODL,                   PIN(E, 5), GPIO_INPUT)
+GPIO(CHARGER_VAP_OTG_EN,             PIN(7, 3), GPIO_OUT_LOW)
+GPIO(CPU_C10_GATE_L,                 PIN(6, 7), GPIO_INPUT)
+GPIO(EC_BATT_PRES_ODL,               PIN(A, 3), GPIO_INPUT)
+GPIO(EC_ENTERING_RW,                 PIN(0, 3), GPIO_OUT_LOW)
+GPIO(EC_EN_EDP_BL,                   PIN(D, 3), GPIO_OUT_HIGH)
+GPIO(EC_GSC_PACKET_MODE,             PIN(7, 5), GPIO_OUT_LOW)
+GPIO(EC_I2C_BAT_SCL,                 PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_BAT_SDA,                 PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SCL_R,              PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SDA_R,              PIN(B, 2), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,              PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SENSOR_SDA,              PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_USB_C0_C2_PPC_BC_SCL,    PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_PPC_BC_SDA,    PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_RT_SCL,        PIN(D, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_RT_SDA,        PIN(D, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_TCPC_SCL,      PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_TCPC_SDA,      PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_MIX_SCL,          PIN(E, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_MIX_SDA,          PIN(E, 3), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_TCPC_SCL,         PIN(F, 3), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_TCPC_SDA,         PIN(F, 2), GPIO_INPUT)
+GPIO(EC_KB_BL_EN_L,                  PIN(8, 6), GPIO_OUT_HIGH)
+GPIO(EC_PCHHOT_ODL,                  PIN(7, 4), GPIO_INPUT)
+GPIO(EC_PCH_INT_ODL,                 PIN(B, 0), GPIO_ODR_HIGH)
+GPIO(EC_PCH_PWR_BTN_ODL,             PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(EC_PCH_RSMRST_L,                PIN(A, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_RTCRST,                  PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_SYS_PWROK,               PIN(3, 7), GPIO_OUT_LOW)
+GPIO(EC_PCH_WAKE_R_ODL,              PIN(C, 0), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_ODL,                 PIN(6, 3), GPIO_ODR_HIGH)
+GPIO(EN_PP5000_FAN,                  PIN(6, 1), GPIO_OUT_HIGH)
+GPIO(EN_PP5000_USBA_R,               PIN(D, 7), GPIO_OUT_LOW)
+GPIO(EN_S5_RAILS,                    PIN(B, 6), GPIO_OUT_LOW)
+GPIO(IMVP9_VRRDY_OD,                 PIN(4, 3), GPIO_INPUT)
+GPIO(PCH_PWROK,                      PIN(7, 2), GPIO_OUT_LOW)
+GPIO(SYS_RST_ODL,                    PIN(C, 5), GPIO_ODR_HIGH)
+GPIO(USB_C0_C2_TCPC_RST_ODL,         PIN(A, 7), GPIO_ODR_LOW)
+GPIO(USB_C1_FRS_EN,                  PIN(9, 4), GPIO_OUT_LOW)
+GPIO(USB_C1_RST_ODL,                 PIN(9, 6), GPIO_ODR_LOW)
+GPIO(USB_C1_RT_INT_ODL,              PIN(A, 0), GPIO_INPUT)
+GPIO(USB_C1_RT_RST_R_ODL,            PIN(0, 2), GPIO_ODR_LOW)
+GPIO(VCCST_PWRGD_OD,                 PIN(A, 4), GPIO_ODR_LOW)
+
+/* UART alternate functions */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)              /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */
+
+/* I2C alternate functions */
+ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)               /* GPIO33/I2C5_SCL0/CTS_L, GPIO36/RTS_L/I2C5_SDA0 */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)               /* GPIO87/I2C1_SDA0 */
+ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)               /* GPIO92/I2C2_SCL0, GPIO91/I2C2_SDA0, GPIO90/I2C1_SCL0 */
+ALTERNATE(PIN_MASK(B, 0x0c), 0, MODULE_I2C, 0)               /* GPIOB3/I2C7_SCL0/DCD_L, GPIOB2/I2C7_SDA0/DSR_L */
+ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, GPIO_SEL_1P8V)   /* GPIOB5/I2C0_SCL0, GPIOB4/I2C0_SDA0 */
+ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)               /* GPIOD1/I2C3_SCL0, GPIOD0/I2C3_SDA0 */
+ALTERNATE(PIN_MASK(E, 0x18), 0, MODULE_I2C, 0)               /* GPIOE4/I2C6_SCL1/I3C_SCL, GPIOE3/I2C6_SDA1/I3C_SDA */
+ALTERNATE(PIN_MASK(F, 0x0c), 0, MODULE_I2C, 0)               /* GPIOF3/I2C4_SCL1, GPIOF2/I2C4_SDA1 */
+
+/* PWM alternate functions */
+ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0)               /* GPIO40/TA1 */
+ALTERNATE(PIN_MASK(6, 0x01), 0, MODULE_PWM, 0)               /* GPIO60/PWM7 */
+ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)               /* GPIO80/PWM3 */
+ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)               /* GPIOB7/PWM5 */
+ALTERNATE(PIN_MASK(C, 0x1c), 0, MODULE_PWM, 0)               /* GPIOC4/PWM2, GPIOC3/PWM0, GPIOC2/PWM1/I2C6_SCL0 */
+
+/* ADC alternate functions */
+ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0)               /* GPIO34/PS2_DAT2/ADC6 */
+ALTERNATE(PIN_MASK(4, 0x34), 0, MODULE_ADC, 0)               /* GPIO42/ADC3/RI_L, GPIO45/ADC0, GPIO44/ADC1 */
+ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0)               /* GPIOE1/ADC7 */
+
+/* KB alternate functions */
+ALTERNATE(PIN_MASK(0, 0xf0), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO10&P80_CLK/GPIO07, KSO11&P80_DAT/GPIO06, KSO12/GPIO05, KSO13/GPIO04 */
+ALTERNATE(PIN_MASK(1, 0x7f), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO06/GPO13/GP_SEL_L, KSO07/GPO12/JEN_L, KSO03/GPIO16/JTAG_TDO0_SWO, KSO04/GPIO15/XNOR, KSO05/GPIO14, KSO08/GPIO11/CR_SOUT1, KSO09/GPIO10/CR_SIN1 */
+ALTERNATE(PIN_MASK(2, 0xfc), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI2/GPIO27/TRACEDATA1, KSI3/GPIO26/TRACEDATA0, KSI4/GPIO25/TRACECLK/GP_SCLK, KSI5/GPIO24/GP_MISO, KSI6/GPIO23/S_SBUB, KSI7/GPIO22/S_SBUA */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO00/GPIO21/JTAG_TCK_SWCLK, KSO01/GPIO20/JTAG_TMS_SWIO */
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI0/GPIO31/TRACEDATA3/GP_MOSI, KSI1/GPIO30/TRACEDATA2/GP_CS_L */
+ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO14/GPIO82 */
+
+/* PMU alternate functions */
+ALTERNATE(PIN_MASK(0, 0x01), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN2_L&GPI00/GPIO00 */
+ALTERNATE(PIN_MASK(0, 0x02), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW) /* GPIO01/PSL_IN3_L&GPI01 */
+ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN1_L&GPID2/GPIOD2 */
+
+/* Unused Pins */
+UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
+UNUSED(PIN(3, 2))       /* GPO32/TRIS_L */
+UNUSED(PIN(3, 5))       /* GPO35/CR_SOUT4/TEST_L */
+UNUSED(PIN(6, 6))       /* GPIO66 */
+UNUSED(PIN(5, 7))       /* GPIO57/SER_IRQ/ESPI_ALERT_L */
+
+/* Pre-configured PSL balls:  J8  K6 */
diff --git a/board/brya/gpio.inc b/board/brya/gpio.inc
new file mode 100644
index 0000000000..d68dfc4dd0
--- /dev/null
+++ b/board/brya/gpio.inc
@@ -0,0 +1,43 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define MODULE_KB		MODULE_KEYBOARD_SCAN
+
+/*
+ * Generated-gpio.inc is produced using a Brya specific tool that
+ * parses the GPIO definitions derived from the board schematics and
+ * EC pinout descriptions derived form the chip datasheets to generate
+ * the Chrome EC GPIO pinout definitions. Due to the confidential
+ * nature of schematics and datasheets, they are not provided here.
+ *
+ * Variants that do not auto-generate their GPIO definitions should
+ * combine the Brya gpio.inc and generated-gpio.inc into their
+ * gpio.inc and customize as appropriate.
+ */
+
+#include "generated-gpio.inc"
+
+/*
+ * The NPCX keyboard driver does not use named GPIOs to access
+ * keyboard scan pins, so we do not list them in *gpio.inc. However, when
+ * KEYBOARD_COL2_INVERTED is defined, this name is required.
+ */
+GPIO(EC_KSO_02_INV,               PIN(1, 7), GPIO_OUT_LOW)
+
+/* IO expander configuration */
+
+/* GPIO02_P2 to PU */
+/* GPIO03_P2 to PU */
+IOEX(USB_C0_OC_ODL,          EXPIN(IOEX_C0_NCT38XX, 0, 4), GPIO_ODR_HIGH)
+IOEX(USB_C0_FRS_EN,          EXPIN(IOEX_C0_NCT38XX, 0, 6), GPIO_OUT_LOW)
+IOEX(USB_C0_RT_RST_ODL,      EXPIN(IOEX_C0_NCT38XX, 0, 7), GPIO_ODR_LOW)
+
+IOEX(USB_C2_RT_RST_ODL,      EXPIN(IOEX_C2_NCT38XX, 0, 2), GPIO_ODR_LOW)
+IOEX(USB_C1_OC_ODL,          EXPIN(IOEX_C2_NCT38XX, 0, 3), GPIO_ODR_HIGH)
+IOEX(USB_C2_OC_ODL,          EXPIN(IOEX_C2_NCT38XX, 0, 4), GPIO_ODR_HIGH)
+IOEX(USB_C2_FRS_EN,          EXPIN(IOEX_C2_NCT38XX, 0, 6), GPIO_OUT_LOW)
+/* GPIO07_P2 to PU */
diff --git a/board/brya/i2c.c b/board/brya/i2c.c
new file mode 100644
index 0000000000..feed4023d7
--- /dev/null
+++ b/board/brya/i2c.c
@@ -0,0 +1,81 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "hooks.h"
+#include "i2c.h"
+
+/* I2C port map configuration */
+const struct i2c_port_t i2c_ports[] = {
+	{
+		/* I2C0 */
+		.name = "sensor",
+		.port = I2C_PORT_SENSOR,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_SENSOR_SCL,
+		.sda = GPIO_EC_I2C_SENSOR_SDA,
+	},
+	{
+		/* I2C1 */
+		.name = "tcpc0,2",
+		.port = I2C_PORT_USB_C0_C2_TCPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C2_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C2_TCPC_SDA,
+	},
+	{
+		/* I2C2 */
+		.name = "ppc0,2",
+		.port = I2C_PORT_USB_C0_C2_PPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C2_PPC_BC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C2_PPC_BC_SDA,
+	},
+	{
+		/* I2C3 */
+		.name = "retimer0,2",
+		.port = I2C_PORT_USB_C0_C2_MUX,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C2_RT_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C2_RT_SDA,
+	},
+	{
+		/* I2C4 C1 TCPC */
+		.name = "tcpc1",
+		.port = I2C_PORT_USB_C1_TCPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C1_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C1_TCPC_SDA,
+		.flags = I2C_PORT_FLAG_DYNAMIC_SPEED,
+	},
+	{
+		/* I2C5 */
+		.name = "battery",
+		.port = I2C_PORT_BATTERY,
+		.kbps = 100,
+		.scl = GPIO_EC_I2C_BAT_SCL,
+		.sda = GPIO_EC_I2C_BAT_SDA,
+	},
+	{
+		/* I2C6 */
+		.name = "ppc1",
+		.port = I2C_PORT_USB_C1_PPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C1_MIX_SCL,
+		.sda = GPIO_EC_I2C_USB_C1_MIX_SDA,
+		.flags = I2C_PORT_FLAG_DYNAMIC_SPEED,
+	},
+	{
+		/* I2C7 */
+		.name = "eeprom",
+		.port = I2C_PORT_EEPROM,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_MISC_SCL_R,
+		.sda = GPIO_EC_I2C_MISC_SDA_R,
+	},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/board/brya/keyboard.c b/board/brya/keyboard.c
new file mode 100644
index 0000000000..156d4b49dd
--- /dev/null
+++ b/board/brya/keyboard.c
@@ -0,0 +1,24 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "keyboard_scan.h"
+#include "timer.h"
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/* Increase from 50 us, because KSO_02 passes through the H1. */
+	.output_settle_us = 80,
+	/* Other values should be the same as the default configuration. */
+	.debounce_down_us = 9 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
+		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
+	},
+};
diff --git a/board/brya/led.c b/board/brya/led.c
new file mode 100644
index 0000000000..80814523e7
--- /dev/null
+++ b/board/brya/led.c
@@ -0,0 +1,90 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Brya specific PWM LED settings: there are 2 LEDs on each side of the board,
+ * each one can be controlled separately. The LED colors are white or amber,
+ * and the default behavior is tied to the charging process: both sides are
+ * amber while charging the battery and white when the battery is charged.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "ec_commands.h"
+#include "led_pwm.h"
+#include "pwm.h"
+#include "util.h"
+
+#include <stdint.h>
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_LEFT_LED,
+	EC_LED_ID_RIGHT_LED,
+};
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+/*
+ * We only have a white and an amber LED, so setting any other color results in
+ * both LEDs being off. Cap at 50% to save power.
+ */
+struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = {
+	/* Amber, White */
+	[EC_LED_COLOR_RED] = { 0, 0 },	  [EC_LED_COLOR_GREEN] = { 0, 0 },
+	[EC_LED_COLOR_BLUE] = { 0, 0 },	  [EC_LED_COLOR_YELLOW] = { 0, 0 },
+	[EC_LED_COLOR_WHITE] = { 0, 50 }, [EC_LED_COLOR_AMBER] = { 50, 0 },
+};
+
+/* Two logical LEDs with amber and white channels. */
+struct pwm_led pwm_leds[CONFIG_LED_PWM_COUNT] = {
+	{
+		.ch0 = PWM_CH_LED1,
+		.ch1 = PWM_CH_LED2,
+		.ch2 = PWM_LED_NO_CHANNEL,
+		.enable = &pwm_enable,
+		.set_duty = &pwm_set_duty,
+	},
+	{
+		.ch0 = PWM_CH_LED3,
+		.ch1 = PWM_CH_LED4,
+		.ch2 = PWM_LED_NO_CHANNEL,
+		.enable = &pwm_enable,
+		.set_duty = &pwm_set_duty,
+	},
+};
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	memset(brightness_range, '\0',
+	       sizeof(*brightness_range) * EC_LED_COLOR_COUNT);
+	brightness_range[EC_LED_COLOR_AMBER] = 100;
+	brightness_range[EC_LED_COLOR_WHITE] = 100;
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	enum pwm_led_id pwm_id;
+
+	/* Convert ec_led_id to pwm_led_id. */
+	switch (led_id) {
+	case EC_LED_ID_LEFT_LED:
+		pwm_id = PWM_LED0;
+		break;
+	case EC_LED_ID_RIGHT_LED:
+		pwm_id = PWM_LED1;
+		break;
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+
+	if (brightness[EC_LED_COLOR_WHITE])
+		set_pwm_led_color(pwm_id, EC_LED_COLOR_WHITE);
+	else if (brightness[EC_LED_COLOR_AMBER])
+		set_pwm_led_color(pwm_id, EC_LED_COLOR_AMBER);
+	else
+		/* Otherwise, the "color" is "off". */
+		set_pwm_led_color(pwm_id, -1);
+
+	return EC_SUCCESS;
+}
diff --git a/board/brya/pwm.c b/board/brya/pwm.c
new file mode 100644
index 0000000000..dad5d5c444
--- /dev/null
+++ b/board/brya/pwm.c
@@ -0,0 +1,70 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "hooks.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_LED2] = {
+		.channel = 0,
+		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+		.freq = 4800,
+	},
+	[PWM_CH_LED3] = {
+		.channel = 1,
+		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+		.freq = 4800,
+	},
+	[PWM_CH_LED1] = {
+		.channel = 2,
+		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+		.freq = 4800,
+	},
+	[PWM_CH_KBLIGHT] = {
+		.channel = 3,
+		.flags = 0,
+		/*
+		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
+		 * flicker. Higher frequencies consume similar average power to
+		 * lower PWM frequencies, but higher frequencies record a much
+		 * lower maximum power.
+		 */
+		.freq = 12000,
+	},
+	[PWM_CH_FAN] = {
+		.channel = 5,
+		.flags = PWM_CONFIG_OPEN_DRAIN,
+		.freq = 25000,
+	},
+	[PWM_CH_LED4] = {
+		.channel = 7,
+		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+		.freq = 4800,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+static void board_pwm_init(void)
+{
+	/*
+	 * Turn off all the LEDs.
+	 * Turn on the fan at 100%.
+	 */
+	pwm_enable(PWM_CH_LED1, 1);
+	pwm_set_duty(PWM_CH_LED1, 0);
+	pwm_enable(PWM_CH_LED2, 1);
+	pwm_set_duty(PWM_CH_LED2, 0);
+	pwm_enable(PWM_CH_LED3, 1);
+	pwm_set_duty(PWM_CH_LED3, 0);
+	pwm_enable(PWM_CH_LED4, 1);
+	pwm_set_duty(PWM_CH_LED4, 0);
+
+	pwm_enable(PWM_CH_KBLIGHT, 1);
+	pwm_set_duty(PWM_CH_KBLIGHT, 50);
+}
+DECLARE_HOOK(HOOK_INIT, board_pwm_init, HOOK_PRIO_DEFAULT);
diff --git a/board/brya/sensors.c b/board/brya/sensors.c
new file mode 100644
index 0000000000..5868ba12ef
--- /dev/null
+++ b/board/brya/sensors.c
@@ -0,0 +1,392 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "accelgyro.h"
+#include "adc.h"
+#include "common.h"
+#include "driver/accel_lis2dw12.h"
+#include "driver/accelgyro_lsm6dso.h"
+#include "driver/als_tcs3400_public.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "motion_sense.h"
+#include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
+#include "thermal.h"
+
+/* ADC configuration */
+struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_1_DDR_SOC] = {
+		.name = "TEMP_DDR_SOC",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_2_AMBIENT] = {
+		.name = "TEMP_AMBIENT",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_3_CHARGER] = {
+		.name = "TEMP_CHARGER",
+		.input_ch = NPCX_ADC_CH6,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_4_WWAN] = {
+		.name = "TEMP_WWAN",
+		.input_ch = NPCX_ADC_CH7,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+K_MUTEX_DEFINE(g_lid_accel_mutex);
+K_MUTEX_DEFINE(g_base_accel_mutex);
+static struct stprivate_data g_lis2dw12_data;
+static struct lsm6dso_data lsm6dso_data;
+
+/* TODO(b/184779333): calibrate the orientation matrix on later board stage */
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					     { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
+
+/* TODO(b/184779743): verify orientation matrix */
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, FLOAT_TO_FP(-1), 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
+
+/* TCS3400 private data */
+static struct als_drv_data_t g_tcs3400_data = {
+	.als_cal.scale = 1,
+	.als_cal.uscale = 0,
+	.als_cal.offset = 0,
+	.als_cal.channel_scale = {
+		.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kc from VPD */
+		.cover_scale = ALS_CHANNEL_SCALE(1.0),     /* CT */
+	},
+};
+
+/*
+ * TODO: b/184702900 need to calibrate ALS/RGB sensor. At default settings,
+ * shining phone flashlight on sensor pegs all readings at 0xFFFF.
+ */
+static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
+	.calibration.rgb_cal[X] = {
+		.offset = 0,
+		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
+		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
+		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
+		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(1.0),
+		.scale = {
+			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kr */
+			.cover_scale = ALS_CHANNEL_SCALE(1.0)
+		}
+	},
+	.calibration.rgb_cal[Y] = {
+		.offset = 0,
+		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
+		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
+		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
+		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(1.0),
+		.scale = {
+			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kg */
+			.cover_scale = ALS_CHANNEL_SCALE(1.0)
+		},
+	},
+	.calibration.rgb_cal[Z] = {
+		.offset = 0,
+		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
+		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
+		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
+		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(1.0),
+		.scale = {
+			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kb */
+			.cover_scale = ALS_CHANNEL_SCALE(1.0)
+		}
+	},
+	.calibration.irt = INT_TO_FP(1),
+	.saturation.again = TCS_DEFAULT_AGAIN,
+	.saturation.atime = TCS_DEFAULT_ATIME,
+};
+
+struct motion_sensor_t motion_sensors[] = {
+	[LID_ACCEL] = {
+		.name = "Lid Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LIS2DW12,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &lis2dw12_drv,
+		.mutex = &g_lid_accel_mutex,
+		.drv_data = &g_lis2dw12_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LIS2DW12_ADDR0,
+		.rot_standard_ref = &lid_standard_ref, /* identity matrix */
+		.default_range = 2, /* g */
+		.min_frequency = LIS2DW12_ODR_MIN_VAL,
+		.max_frequency = LIS2DW12_ODR_MAX_VAL,
+		.config = {
+			/* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+			/* Sensor on for lid angle detection */
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+		},
+	},
+
+	[BASE_ACCEL] = {
+		.name = "Base Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LSM6DSO,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &lsm6dso_drv,
+		.mutex = &g_base_accel_mutex,
+		.drv_data = LSM6DSO_ST_DATA(lsm6dso_data,
+				MOTIONSENSE_TYPE_ACCEL),
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LSM6DSO_ADDR0_FLAGS,
+		.rot_standard_ref = &base_standard_ref,
+		.default_range = 4,  /* g */
+		.min_frequency = LSM6DSO_ODR_MIN_VAL,
+		.max_frequency = LSM6DSO_ODR_MAX_VAL,
+		.config = {
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 13000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+		},
+	},
+
+	[BASE_GYRO] = {
+		.name = "Base Gyro",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LSM6DSO,
+		.type = MOTIONSENSE_TYPE_GYRO,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &lsm6dso_drv,
+		.mutex = &g_base_accel_mutex,
+		.drv_data = LSM6DSO_ST_DATA(lsm6dso_data,
+				MOTIONSENSE_TYPE_GYRO),
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LSM6DSO_ADDR0_FLAGS,
+		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = LSM6DSO_ODR_MIN_VAL,
+		.max_frequency = LSM6DSO_ODR_MAX_VAL,
+	},
+
+	[CLEAR_ALS] = {
+		.name = "Clear Light",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_TCS3400,
+		.type = MOTIONSENSE_TYPE_LIGHT,
+		.location = MOTIONSENSE_LOC_CAMERA,
+		.drv = &tcs3400_drv,
+		.drv_data = &g_tcs3400_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = TCS3400_I2C_ADDR_FLAGS,
+		.rot_standard_ref = NULL,
+		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
+		.min_frequency = TCS3400_LIGHT_MIN_FREQ,
+		.max_frequency = TCS3400_LIGHT_MAX_FREQ,
+		.config = {
+			/* Run ALS sensor in S0 */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 1000,
+			},
+		},
+	},
+
+	[RGB_ALS] = {
+		/*
+		 * RGB channels read by CLEAR_ALS and so the i2c port and
+		 * address do not need to be defined for RGB_ALS.
+		 */
+		.name = "RGB Light",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_TCS3400,
+		.type = MOTIONSENSE_TYPE_LIGHT_RGB,
+		.location = MOTIONSENSE_LOC_CAMERA,
+		.drv = &tcs3400_rgb_drv,
+		.drv_data = &g_tcs3400_rgb_data,
+		.rot_standard_ref = NULL,
+		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
+	},
+};
+const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+/* ALS instances when LPC mapping is needed. Each entry directs to a sensor. */
+const struct motion_sensor_t *motion_als_sensors[] = {
+	&motion_sensors[CLEAR_ALS],
+};
+BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
+
+static void baseboard_sensors_init(void)
+{
+	/* Enable gpio interrupt for lid accel sensor */
+	gpio_enable_interrupt(GPIO_EC_ACCEL_INT_R_L);
+	/* Enable interrupt for the TCS3400 color light sensor */
+	gpio_enable_interrupt(GPIO_EC_ALS_RGB_INT_R_L);
+	/* Enable gpio interrupt for base accelgyro sensor */
+	gpio_enable_interrupt(GPIO_EC_IMU_INT_R_L);
+}
+DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_INIT_I2C + 1);
+
+/* Temperature sensor configuration */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1_DDR_SOC] = {
+		.name = "DDR and SOC",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_1_DDR_SOC,
+	},
+	[TEMP_SENSOR_2_AMBIENT] = {
+		.name = "Ambient",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_2_AMBIENT,
+	},
+	[TEMP_SENSOR_3_CHARGER] = {
+		.name = "Charger",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_3_CHARGER,
+	},
+	[TEMP_SENSOR_4_WWAN] = {
+		.name = "WWAN",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_4_WWAN,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/*
+ * TODO(b/180681346): update for Alder Lake/brya
+ *
+ * Alder Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
+ * 130 C.  However, sensor is located next to DDR, so we need to use the lower
+ * DDR temperature limit (85 C)
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(85), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(90), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(80), \
+		}, \
+		.temp_fan_off = C_TO_K(35), \
+		.temp_fan_max = C_TO_K(60), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
+
+/*
+ * TODO(b/180681346): update for Alder Lake/brya
+ *
+ * Inductor limits - used for both charger and PP3300 regulator
+ *
+ * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
+ *
+ * Charger max recommended temperature 100C, max absolute temperature 125C
+ * PP3300 regulator: operating range -40 C to 145 C
+ *
+ * Inductors: limit of 125c
+ * PCB: limit is 80c
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_AMBIENT          \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(85), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(90), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(80), \
+		}, \
+		.temp_fan_off = C_TO_K(35), \
+		.temp_fan_max = C_TO_K(60), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_ambient =
+	THERMAL_AMBIENT;
+
+/*
+ * Inductor limits - used for both charger and PP3300 regulator
+ *
+ * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
+ *
+ * Charger max recommended temperature 125C, max absolute temperature 150C
+ * PP3300 regulator: operating range -40 C to 125 C
+ *
+ * Inductors: limit of 125c
+ * PCB: limit is 80c
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CHARGER          \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(105), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(120), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(90), \
+		}, \
+		.temp_fan_off = C_TO_K(35), \
+		.temp_fan_max = C_TO_K(65), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_charger =
+	THERMAL_CHARGER;
+
+/*
+ * TODO(b/180681346): update for brya WWAN module
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_WWAN             \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(130), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(130), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(100), \
+		}, \
+		.temp_fan_off = C_TO_K(35), \
+		.temp_fan_max = C_TO_K(60), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_wwan =
+	THERMAL_WWAN;
+
+struct ec_thermal_config thermal_params[] = {
+	[TEMP_SENSOR_1_DDR_SOC] = THERMAL_CPU,
+	[TEMP_SENSOR_2_AMBIENT] = THERMAL_AMBIENT,
+	[TEMP_SENSOR_3_CHARGER] = THERMAL_CHARGER,
+	[TEMP_SENSOR_4_WWAN] = THERMAL_WWAN,
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
diff --git a/board/brya/usbc_config.c b/board/brya/usbc_config.c
new file mode 100644
index 0000000000..fbec72f20b
--- /dev/null
+++ b/board/brya/usbc_config.c
@@ -0,0 +1,524 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi.h"
+#include "charge_ramp.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/bc12/pi3usb9201_public.h"
+#include "driver/ppc/nx20p348x.h"
+#include "driver/ppc/syv682x_public.h"
+#include "driver/retimer/bb_retimer_public.h"
+#include "driver/tcpm/nct38xx.h"
+#include "driver/tcpm/ps8xxx_public.h"
+#include "driver/tcpm/tcpci.h"
+#include "ec_commands.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "ioexpander.h"
+#include "system.h"
+#include "task.h"
+#include "task_id.h"
+#include "timer.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+#ifdef CONFIG_ZEPHYR
+enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_C2_NCT38XX, IOEX_PORT_COUNT };
+#endif /* CONFIG_ZEPHYR */
+
+#ifndef CONFIG_ZEPHYR
+/* USBC TCPC configuration */
+const struct tcpc_config_t tcpc_config[] = {
+	[USBC_PORT_C0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0_C2_TCPC,
+			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_NO_DEBUG_ACC_CONTROL,
+	},
+	[USBC_PORT_C1] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C1_TCPC,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
+			 TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V |
+			 TCPC_FLAGS_CONTROL_VCONN |
+			 TCPC_FLAGS_CONTROL_FRS,
+	},
+	[USBC_PORT_C2] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0_C2_TCPC,
+			.addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
+BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
+#endif /* !CONFIG_ZEPHYR */
+
+/******************************************************************************/
+/* USB-A charging control */
+
+#ifndef CONFIG_ZEPHYR
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_PP5000_USBA_R,
+};
+#endif
+BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
+
+/******************************************************************************/
+
+#ifndef CONFIG_ZEPHYR
+/* USBC PPC configuration */
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_C2_PPC,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.frs_en = IOEX_USB_C0_FRS_EN,
+		.drv = &syv682x_drv,
+	},
+	[USBC_PORT_C1] = {
+		/* Compatible with Silicon Mitus SM5360A */
+		.i2c_port = I2C_PORT_USB_C1_PPC,
+		.i2c_addr_flags = NX20P3483_ADDR2_FLAGS,
+		.drv = &nx20p348x_drv,
+	},
+	[USBC_PORT_C2] = {
+		.i2c_port = I2C_PORT_USB_C0_C2_PPC,
+		.i2c_addr_flags = SYV682X_ADDR2_FLAGS,
+		.frs_en = IOEX_USB_C2_FRS_EN,
+		.drv = &syv682x_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
+
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/* USBC mux configuration - Alder Lake includes internal mux */
+static const struct usb_mux_chain usbc0_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+static const struct usb_mux_chain usbc2_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C2,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+
+/*
+ * USB3 DB mux configuration - the top level mux still needs to be set
+ * to the virtual_usb_mux_driver so the AP gets notified of mux changes
+ * and updates the TCSS configuration on state changes.
+ */
+static const struct usb_mux_chain usbc1_usb3_db_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
+};
+
+const struct usb_mux_chain usb_muxes[] = {
+	[USBC_PORT_C0] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.flags = USB_MUX_FLAG_CAN_IDLE,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C0_C2_MUX,
+			.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc0_tcss_usb_mux,
+	},
+	[USBC_PORT_C1] = {
+		.mux = &(const struct usb_mux) {
+			/* PS8815 DB */
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc1_usb3_db_retimer,
+	},
+	[USBC_PORT_C2] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C2,
+			.flags = USB_MUX_FLAG_CAN_IDLE,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C0_C2_MUX,
+			.i2c_addr_flags = USBC_PORT_C2_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc2_tcss_usb_mux,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
+
+/* BC1.2 charger detect configuration */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_C2_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C1_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+	[USBC_PORT_C2] = {
+		.i2c_port = I2C_PORT_USB_C0_C2_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_1_FLAGS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
+
+/*
+ * USB C0 and C2 uses burnside bridge chips and have their reset
+ * controlled by their respective TCPC chips acting as GPIO expanders.
+ *
+ * ioex_init() is normally called before we take the TCPCs out of
+ * reset, so we need to start in disabled mode, then explicitly
+ * call ioex_init().
+ */
+
+struct ioexpander_config_t ioex_config[] = {
+	[IOEX_C0_NCT38XX] = {
+		.i2c_host_port = I2C_PORT_USB_C0_C2_TCPC,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
+	},
+	[IOEX_C2_NCT38XX] = {
+		.i2c_host_port = I2C_PORT_USB_C0_C2_TCPC,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT);
+#endif /* !CONFIG_ZEPHYR */
+
+#ifdef CONFIG_CHARGE_RAMP_SW
+
+/*
+ * TODO(b/181508008): tune this threshold
+ */
+
+#define BC12_MIN_VOLTAGE 4400
+
+/**
+ * Return true if VBUS is too low
+ */
+int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
+{
+	int voltage;
+
+	if (charger_get_vbus_voltage(port, &voltage))
+		voltage = 0;
+
+	if (voltage == 0) {
+		CPRINTS("%s: must be disconnected", __func__);
+		return 1;
+	}
+
+	if (voltage < BC12_MIN_VOLTAGE) {
+		CPRINTS("%s: port %d: vbus %d lower than %d", __func__, port,
+			voltage, BC12_MIN_VOLTAGE);
+		return 1;
+	}
+
+	return 0;
+}
+
+#endif /* CONFIG_CHARGE_RAMP_SW */
+
+void config_usb_db_type(void)
+{
+	enum ec_cfg_usb_db_type db_type = ec_cfg_usb_db_type();
+
+	/*
+	 * TODO(b/180434685): implement multiple DB types
+	 */
+
+	CPRINTS("Configured USB DB type number is %d", db_type);
+}
+
+__override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
+{
+	enum ioex_signal rst_signal;
+
+	if (me->usb_port == USBC_PORT_C0) {
+/* TODO: explore how to handle board id in zephyr*/
+#ifndef CONFIG_ZEPHYR
+		rst_signal = IOEX_USB_C0_RT_RST_ODL;
+#else
+		/* On Zephyr use bb_controls generated from DTS */
+		rst_signal = bb_controls[me->usb_port].retimer_rst_gpio;
+#endif /* !CONFIG_ZEPHYR */
+	} else if (me->usb_port == USBC_PORT_C2) {
+/* TODO: explore how to handle board id in zephyr*/
+#ifndef CONFIG_ZEPHYR
+		rst_signal = IOEX_USB_C2_RT_RST_ODL;
+#else
+		/* On Zephyr use bb_controls generated from DTS */
+		rst_signal = bb_controls[me->usb_port].retimer_rst_gpio;
+#endif /* !CONFIG_ZEPHYR */
+	} else {
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * We do not have a load switch for the burnside bridge chips,
+	 * so we only need to sequence reset.
+	 */
+
+	if (enable) {
+		/*
+		 * Tpw, minimum time from VCC to RESET_N de-assertion is 100us.
+		 * For boards that don't provide a load switch control, the
+		 * retimer_init() function ensures power is up before calling
+		 * this function.
+		 */
+		ioex_set_level(rst_signal, 1);
+		/*
+		 * Allow 1ms time for the retimer to power up lc_domain
+		 * which powers I2C controller within retimer
+		 */
+		msleep(1);
+	} else {
+		ioex_set_level(rst_signal, 0);
+		msleep(1);
+	}
+	return EC_SUCCESS;
+}
+
+void board_reset_pd_mcu(void)
+{
+	enum gpio_signal tcpc_rst;
+
+#ifndef CONFIG_ZEPHYR
+	tcpc_rst = GPIO_USB_C0_C2_TCPC_RST_ODL;
+#else
+	tcpc_rst = GPIO_UNIMPLEMENTED;
+#endif /* !CONFIG_ZEPHYR */
+
+	/*
+	 * TODO(b/179648104): figure out correct timing
+	 */
+
+	gpio_set_level(tcpc_rst, 0);
+	if (ec_cfg_usb_db_type() != DB_USB_ABSENT) {
+		gpio_set_level(GPIO_USB_C1_RST_ODL, 0);
+		gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 0);
+	}
+
+	/*
+	 * delay for power-on to reset-off and min. assertion time
+	 */
+
+	msleep(20);
+
+	gpio_set_level(tcpc_rst, 1);
+	if (ec_cfg_usb_db_type() != DB_USB_ABSENT) {
+		gpio_set_level(GPIO_USB_C1_RST_ODL, 1);
+		gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 1);
+	}
+
+	/* wait for chips to come up */
+
+	msleep(50);
+}
+
+static void board_tcpc_init(void)
+{
+	/* Don't reset TCPCs after initial reset */
+	if (!system_jumped_late())
+		board_reset_pd_mcu();
+
+		/*
+		 * These IO expander pins are implemented using the
+		 * C0/C2 TCPC, so they must be set up after the TCPC has
+		 * been taken out of reset.
+		 */
+#ifndef CONFIG_ZEPHYR
+	ioex_init(IOEX_C0_NCT38XX);
+	ioex_init(IOEX_C2_NCT38XX);
+#else
+	gpio_reset_port(DEVICE_DT_GET(DT_NODELABEL(ioex_port1)));
+	gpio_reset_port(DEVICE_DT_GET(DT_NODELABEL(ioex_port2)));
+#endif
+
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C2_PPC_INT_ODL);
+
+#ifndef CONFIG_ZEPHYR
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_C2_TCPC_INT_ODL);
+
+	/* Enable BC1.2 interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C2_BC12_INT_ODL);
+#endif /* !CONFIG_ZEPHYR */
+
+	if (ec_cfg_usb_db_type() != DB_USB_ABSENT) {
+		gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
+#ifndef CONFIG_ZEPHYR
+		gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
+		gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
+#else
+	} else {
+		tcpc_config[1].irq_gpio.port = NULL;
+#endif /* !CONFIG_ZEPHYR */
+	}
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
+
+#ifndef CONFIG_ZEPHYR
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (gpio_get_level(GPIO_USB_C0_C2_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_0 | PD_STATUS_TCPC_ALERT_2;
+
+	if ((ec_cfg_usb_db_type() != DB_USB_ABSENT) &&
+	    gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
+#endif
+
+int ppc_get_alert_status(int port)
+{
+	if (port == USBC_PORT_C0)
+		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
+	else if ((port == USBC_PORT_C1) &&
+		 (ec_cfg_usb_db_type() != DB_USB_ABSENT))
+		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
+	else if (port == USBC_PORT_C2)
+		return gpio_get_level(GPIO_USB_C2_PPC_INT_ODL) == 0;
+	return 0;
+}
+
+#ifndef CONFIG_ZEPHYR
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_C2_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_TCPC_INT_ODL:
+		if (ec_cfg_usb_db_type() == DB_USB_ABSENT)
+			break;
+		schedule_deferred_pd_interrupt(USBC_PORT_C1);
+		break;
+	default:
+		break;
+	}
+}
+#endif
+
+void bc12_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_BC12_INT_ODL:
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+		break;
+	case GPIO_USB_C1_BC12_INT_ODL:
+		if (ec_cfg_usb_db_type() == DB_USB_ABSENT)
+			break;
+		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+		break;
+	case GPIO_USB_C2_BC12_INT_ODL:
+		usb_charger_task_set_event(2, USB_CHG_EVENT_BC12);
+		break;
+	default:
+		break;
+	}
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_PPC_INT_ODL:
+		switch (ec_cfg_usb_db_type()) {
+		case DB_USB_ABSENT:
+		case DB_USB_ABSENT2:
+			break;
+		case DB_USB3_PS8815:
+			nx20p348x_interrupt(USBC_PORT_C1);
+			break;
+		}
+		break;
+	case GPIO_USB_C2_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C2);
+		break;
+	default:
+		break;
+	}
+}
+
+void retimer_interrupt(enum gpio_signal signal)
+{
+	/*
+	 * TODO(b/179513527): add USB-C support
+	 */
+}
+
+__override bool board_is_dts_port(int port)
+{
+	return port == USBC_PORT_C0;
+}
+
+__override bool board_is_tbt_usb4_port(int port)
+{
+	if (port == USBC_PORT_C0 || port == USBC_PORT_C2)
+		return true;
+
+	return false;
+}
+
+__override enum tbt_compat_cable_speed board_get_max_tbt_speed(int port)
+{
+	if (!board_is_tbt_usb4_port(port))
+		return TBT_SS_RES_0;
+
+	return TBT_SS_TBT_GEN3;
+}
diff --git a/board/brya/usbc_config.h b/board/brya/usbc_config.h
new file mode 100644
index 0000000000..bff89438d4
--- /dev/null
+++ b/board/brya/usbc_config.h
@@ -0,0 +1,24 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Brya board-specific USB-C configuration */
+
+#ifndef __CROS_EC_USBC_CONFIG_H
+#define __CROS_EC_USBC_CONFIG_H
+
+#ifndef CONFIG_ZEPHYR
+#define CONFIG_USB_PD_PORT_MAX_COUNT 3
+#endif
+
+enum usbc_port {
+	USBC_PORT_C0 = 0,
+	USBC_PORT_C1,
+	USBC_PORT_C2,
+	USBC_PORT_COUNT
+};
+
+void config_usb_db_type(void);
+
+#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/brya/vif_override.xml b/board/brya/vif_override.xml
new file mode 100644
index 0000000000..6ade5d2f92
--- /dev/null
+++ b/board/brya/vif_override.xml
@@ -0,0 +1,148 @@
+<?xml version="1.0" encoding="utf-8"?>
+<vif:VIF xmlns="http://usb.org/VendorInfoFile.xsd">
+  <vif:Product_Revision>2</vif:Product_Revision>
+  <vif:TID>0</vif:TID>
+  <vif:Product>
+    <vif:USB4_Num_Internal_Host_Controllers value="1" />
+    <vif:USB4_Num_PCIe_DN_Bridges value="0" />
+    <vif:USB4RouterList>
+      <vif:Usb4Router>
+        <!--USB4 Router 0-->
+        <vif:USB4_Router_ID value="0" />
+        <vif:USB4_Silicon_VID value="32903">8087</vif:USB4_Silicon_VID>
+        <vif:USB4_Num_Lane_Adapters value="4" />
+        <vif:USB4_Num_USB3_DN_Adapters value="1" />
+        <vif:USB4_Num_DP_IN_Adapters value="1" />
+        <vif:USB4_Num_DP_OUT_Adapters value="0" />
+        <vif:USB4_Num_PCIe_DN_Adapters value="4" />
+        <vif:USB4_TBT3_Not_Supported value="0">TBT3 Compatible</vif:USB4_TBT3_Not_Supported>
+        <vif:USB4_PCIe_Wake_Supported value="true" />
+        <vif:USB4_USB3_Wake_Supported value="false" />
+        <vif:USB4_Num_Unused_Adapters value="0" />
+        <vif:USB4_TBT3_VID value="32903">8087</vif:USB4_TBT3_VID>
+        <vif:USB4_PCIe_Switch_Vendor_ID value="32902">8086</vif:USB4_PCIe_Switch_Vendor_ID>
+        <vif:USB4_PCIe_Switch_Device_ID value="39451">9A1B</vif:USB4_PCIe_Switch_Device_ID>
+      </vif:Usb4Router>
+    </vif:USB4RouterList>
+  </vif:Product>
+
+  <vif:Component>
+    <vif:USB4_Max_Speed value="1">Gen 3 (40Gb)</vif:USB4_Max_Speed>
+
+    <!--;USB Host-->
+
+    <vif:Host_Speed value="4">USB 3.2 Gen 2x2</vif:Host_Speed>
+    <vif:Host_Contains_Captive_Retimer value="true" />
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:Host_Suspend_Supported value="true" />
+
+    <!--;PD Source-->
+    <!-- will we ever clear USB_Suspend_Supported? -->
+    <vif:USB_Suspend_May_Be_Cleared value="true" />
+
+    <!-- remove FR_Swap_* when we enable CONFIG_USB_PD_FRS -->
+    <!--;Dual Role-->
+    <vif:FR_Swap_Supported_As_Initial_Sink value="true" />
+    <!--;PD Source-->
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="3">3A @ 5V</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!--Source PDO 1-->
+        <vif:Src_PD_OCP_OC_Debounce value="50">50 msec</vif:Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="360">3600 mA</vif:Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+
+    <!-- SOP Discover ID -->
+    <vif:Product_Type_UFP_SOP value="2">PDUSB Peripheral</vif:Product_Type_UFP_SOP>
+    <vif:Product_Type_DFP_SOP value="2">PDUSB Host</vif:Product_Type_DFP_SOP>
+
+    <!-- USB4 Port -->
+    <vif:USB4_Lane_0_Adapter value="1" />
+    <vif:USB4_UFP_Supported value="false" />
+    <vif:USB4_DFP_Supported value="true" />
+    <vif:USB4_USB3_Tunneling_Supported value="true" />
+    <vif:USB4_DP_Tunneling_Supported value="true" />
+    <vif:USB4_CL1_State_Supported value="true" />
+    <vif:USB4_CL2_State_Supported value="true" />
+    <vif:USB4_Num_Retimers value="1" />
+    <vif:USB4_DP_Bit_Rate value="3">HBR3</vif:USB4_DP_Bit_Rate>
+    <vif:USB4_Num_DP_Lanes value="4">4 Lanes</vif:USB4_Num_DP_Lanes>
+
+  </vif:Component>
+
+  <vif:Component>
+    <vif:USB4_Supported value="false" />
+
+    <!--;USB Host-->
+    <vif:Host_Speed value="2">USB 3.2 Gen 2x1</vif:Host_Speed>
+    <vif:Host_Contains_Captive_Retimer value="true" />
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:Host_Suspend_Supported value="true" />
+
+    <!--;PD Source-->
+    <!-- will we ever clear USB_Suspend_Supported? -->
+    <vif:USB_Suspend_May_Be_Cleared value="true" />
+
+    <!-- remove FR_Swap_* when we enable CONFIG_USB_PD_FRS -->
+    <!--;Dual Role-->
+    <vif:FR_Swap_Supported_As_Initial_Sink value="true" />
+    <!--;PD Source-->
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="3">3A @ 5V</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!--Source PDO 1-->
+        <vif:Src_PD_OCP_OC_Debounce value="50">50 msec</vif:Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="360">3600 mA</vif:Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+
+    <!-- SOP Discover ID -->
+    <vif:Product_Type_UFP_SOP value="3">PSD</vif:Product_Type_UFP_SOP>
+    <vif:Product_Type_DFP_SOP value="2">PDUSB Host</vif:Product_Type_DFP_SOP>
+
+  </vif:Component>
+
+  <vif:Component>
+    <vif:USB4_Max_Speed value="1">Gen 3 (40Gb)</vif:USB4_Max_Speed>
+    <!--;USB Host-->
+    <vif:Host_Speed value="4">USB 3.2 Gen 2x2</vif:Host_Speed>
+    <vif:Host_Contains_Captive_Retimer value="true" />
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:Host_Suspend_Supported value="true" />
+
+    <!--;PD Source-->
+    <!-- will we ever clear USB_Suspend_Supported? -->
+    <vif:USB_Suspend_May_Be_Cleared value="true" />
+
+    <!-- remove FR_Swap_* when we enable CONFIG_USB_PD_FRS -->
+    <!--;Dual Role-->
+    <vif:FR_Swap_Supported_As_Initial_Sink value="true" />
+    <!--;PD Source-->
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="3">3A @ 5V</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!--Source PDO 1-->
+        <vif:Src_PD_OCP_OC_Debounce value="50">50 msec</vif:Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="360">3600 mA</vif:Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+
+    <!-- SOP Discover ID -->
+    <vif:Product_Type_UFP_SOP value="2">PDUSB Peripheral</vif:Product_Type_UFP_SOP>
+    <vif:Product_Type_DFP_SOP value="2">PDUSB Host</vif:Product_Type_DFP_SOP>
+
+    <!-- USB4 Port -->
+    <vif:USB4_Lane_0_Adapter value="1" />
+    <vif:USB4_UFP_Supported value="false" />
+    <vif:USB4_DFP_Supported value="true" />
+    <vif:USB4_USB3_Tunneling_Supported value="true" />
+    <vif:USB4_DP_Tunneling_Supported value="true" />
+    <vif:USB4_CL1_State_Supported value="true" />
+    <vif:USB4_CL2_State_Supported value="true" />
+    <vif:USB4_Num_Retimers value="1" />
+    <vif:USB4_DP_Bit_Rate value="3">HBR3</vif:USB4_DP_Bit_Rate>
+    <vif:USB4_Num_DP_Lanes value="4">4 Lanes</vif:USB4_Num_DP_Lanes>
+
+  </vif:Component>
+</vif:VIF>
diff --git a/board/bugzzy/battery.c b/board/bugzzy/battery.c
new file mode 100644
index 0000000000..2df4848d05
--- /dev/null
+++ b/board/bugzzy/battery.c
@@ -0,0 +1,134 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "charge_state.h"
+#include "common.h"
+#include "hooks.h"
+#include "usb_pd.h"
+#include "util.h"
+
+/*
+ * Battery info for all bugzzy battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ *
+ * Battery FET Status in Manufacture Access : bit15 & bit14
+ *  b'00 - dfet : on / cfet : on
+ *  b'01 - dfet : on / cfet : off
+ *  b'10 - dfet : off / cfet : off
+ *  b'11 - dfet : off / cfet : on
+ *  The value b'10 is disconnect_val, so we can use b'01 for cfet_off_val
+ */
+
+/* charging current is limited to 0.45C */
+#define CHARGING_CURRENT_45C 2601
+
+const struct board_batt_params board_battery_info[] = {
+	/* SDI Battery Information */
+	[BATTERY_SDI] = {
+		.fuel_gauge = {
+			.manuf_name = "SDI",
+			.device_name = "4404D57",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 0,
+				.reg_addr = 0x00,
+				.reg_mask = 0xc000,
+				.disconnect_val = 0x8000,
+				.cfet_mask = 0xc000,
+				.cfet_off_val = 0x4000,
+			}
+		},
+		.batt_info = {
+			.voltage_max            = 8700,
+			.voltage_normal         = 7700, /* mV */
+			.voltage_min            = 6000, /* mV */
+			.precharge_current      = 200,  /* mA */
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 45,
+			.charging_min_c         = 0,
+			.charging_max_c         = 55,
+			.discharging_min_c      = -20,
+			.discharging_max_c      = 70,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SDI;
+
+int charger_profile_override(struct charge_state_data *curr)
+{
+	if ((chipset_in_state(CHIPSET_STATE_ON)) &&
+	    (curr->requested_current > CHARGING_CURRENT_45C))
+		curr->requested_current = CHARGING_CURRENT_45C;
+
+	return 0;
+}
+
+/* Customs options controllable by host command. */
+#define PARAM_FASTCHARGE (CS_PARAM_CUSTOM_PROFILE_MIN + 0)
+
+enum ec_status charger_profile_override_get_param(uint32_t param,
+						  uint32_t *value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+enum ec_status charger_profile_override_set_param(uint32_t param,
+						  uint32_t value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+/* Lower our input voltage to 5V in S0iX when battery is full. */
+#define PD_VOLTAGE_WHEN_FULL 5000
+static void reduce_input_voltage_when_full(void)
+{
+	static int saved_input_voltage = -1;
+	int max_pd_voltage_mv = pd_get_max_voltage();
+	int port;
+
+	if (charge_get_percent() == 100 &&
+	    chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
+		if (max_pd_voltage_mv != PD_VOLTAGE_WHEN_FULL) {
+			saved_input_voltage = max_pd_voltage_mv;
+			max_pd_voltage_mv = PD_VOLTAGE_WHEN_FULL;
+		}
+	} else if (saved_input_voltage != -1) {
+		if (max_pd_voltage_mv == PD_VOLTAGE_WHEN_FULL)
+			max_pd_voltage_mv = saved_input_voltage;
+		saved_input_voltage = -1;
+	}
+
+	if (pd_get_max_voltage() != max_pd_voltage_mv) {
+		for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++)
+			pd_set_external_voltage_limit(port, max_pd_voltage_mv);
+	}
+}
+DECLARE_HOOK(HOOK_SECOND, reduce_input_voltage_when_full, HOOK_PRIO_DEFAULT);
diff --git a/board/bugzzy/board.c b/board/bugzzy/board.c
new file mode 100644
index 0000000000..5102db15be
--- /dev/null
+++ b/board/bugzzy/board.c
@@ -0,0 +1,906 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Waddledoo board-specific configuration */
+
+#include "adc_chip.h"
+#include "button.h"
+#include "cbi_fw_config.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "chipset.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "cros_board_info.h"
+#include "driver/accel_lis2ds.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "driver/accelgyro_lsm6dsm.h"
+#include "driver/bc12/pi3usb9201.h"
+#include "driver/charger/isl923x.h"
+#include "driver/tcpm/raa489000.h"
+#include "driver/tcpm/tcpci.h"
+#include "driver/temp_sensor/thermistor.h"
+#include "driver/usb_mux/ps8743.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "keyboard_8042.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "motion_sense.h"
+#include "power.h"
+#include "power_button.h"
+#include "stdbool.h"
+#include "switch.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "temp_sensor.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+#define INT_RECHECK_US 5000
+
+/* C0 interrupt line shared by BC 1.2 and charger */
+static void check_c0_line(void);
+DECLARE_DEFERRED(check_c0_line);
+
+static void notify_c0_chips(void)
+{
+	/*
+	 * The interrupt line is shared between the TCPC and BC 1.2 detection
+	 * chip.  Therefore we'll need to check both ICs.
+	 */
+	schedule_deferred_pd_interrupt(0);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+
+static void check_c0_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		notify_c0_chips();
+		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+	}
+}
+
+static void usb_c0_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c0_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c0_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+}
+
+/* C1 interrupt line shared by BC 1.2, TCPC, and charger */
+static void check_c1_line(void);
+DECLARE_DEFERRED(check_c1_line);
+
+static void notify_c1_chips(void)
+{
+	schedule_deferred_pd_interrupt(1);
+	usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+}
+
+static void check_c1_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips.
+	 */
+	if (!gpio_get_level(GPIO_SUB_C1_INT_EN_RAILS_ODL)) {
+		notify_c1_chips();
+		hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
+	}
+}
+
+static void sub_usb_c1_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c1_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c1_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
+}
+
+static void sub_hdmi_hpd_interrupt(enum gpio_signal s)
+{
+	int hdmi_hpd_odl = gpio_get_level(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL);
+
+	gpio_set_level(GPIO_EC_AP_USB_C1_HDMI_HPD, !hdmi_hpd_odl);
+}
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_1] = {
+		.name = "TEMP_SENSOR1",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_2] = {
+		.name = "TEMP_SENSOR2",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_3] = {
+		.name = "TEMP_SENSOR3",
+		.input_ch = NPCX_ADC_CH5,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_4] = {
+		.name = "TEMP_SENSOR4",
+		.input_ch = NPCX_ADC_CH6,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_SUB_ANALOG] = {
+		.name = "SUB_ANALOG",
+		.input_ch = NPCX_ADC_CH2,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_VSNS_PP3300_A] = {
+		.name = "PP3300_A_PGOOD",
+		.input_ch = NPCX_ADC_CH9,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* Thermistors */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Charger",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "Skin1",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
+	[TEMP_SENSOR_4] = { .name = "Skin2",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_4 },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+static int board_id = -1;
+
+void board_init(void)
+{
+	int on;
+
+	/* Enable C0 interrupt and check if it needs processing */
+	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
+	check_c0_line();
+
+	if (get_cbi_fw_config_db() == DB_1A_HDMI) {
+		/* Disable i2c on HDMI pins */
+		gpio_config_pin(MODULE_I2C, GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL,
+				0);
+		gpio_config_pin(MODULE_I2C, GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL,
+				0);
+
+		/* Set HDMI and sub-rail enables to output */
+		gpio_set_flags(GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL,
+			       chipset_in_state(CHIPSET_STATE_ON) ?
+				       GPIO_ODR_LOW :
+				       GPIO_ODR_HIGH);
+		gpio_set_flags(GPIO_SUB_C1_INT_EN_RAILS_ODL, GPIO_ODR_HIGH);
+
+		/* Select HDMI option */
+		gpio_set_level(GPIO_HDMI_SEL_L, 0);
+
+		/* Enable interrupt for passing through HPD */
+		gpio_enable_interrupt(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL);
+	} else {
+		/* Set SDA as an input */
+		gpio_set_flags(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL, GPIO_INPUT);
+
+		/* Enable C1 interrupt and check if it needs processing */
+		gpio_enable_interrupt(GPIO_SUB_C1_INT_EN_RAILS_ODL);
+		check_c1_line();
+	}
+	/* Enable gpio interrupt for base accelgyro sensor */
+	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
+
+	/* Turn on 5V if the system is on, otherwise turn it off. */
+	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
+			      CHIPSET_STATE_SOFT_OFF);
+	board_power_5v_enable(on);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+/* Enable HDMI any time the SoC is on */
+static void hdmi_enable(void)
+{
+	if (get_cbi_fw_config_db() == DB_1A_HDMI)
+		gpio_set_level(GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, hdmi_enable, HOOK_PRIO_DEFAULT);
+
+static void hdmi_disable(void)
+{
+	if (get_cbi_fw_config_db() == DB_1A_HDMI)
+		gpio_set_level(GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, hdmi_disable, HOOK_PRIO_DEFAULT);
+
+void board_hibernate(void)
+{
+	/*
+	 * Both charger ICs need to be put into their "low power mode" before
+	 * entering the Z-state.
+	 */
+	if (board_get_charger_chip_count() > 1)
+		raa489000_hibernate(1, true);
+	raa489000_hibernate(0, false);
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * TODO(b:147316511): Here we could issue a digital reset to the IC,
+	 * unsure if we actually want to do that or not yet.
+	 */
+}
+
+static void set_5v_gpio(int level)
+{
+	gpio_set_level(GPIO_EN_PP5000, level);
+}
+
+__override void board_power_5v_enable(int enable)
+{
+	/*
+	 * Port 0 simply has a GPIO to turn on the 5V regulator, however, 5V is
+	 * generated locally on the sub board and we need to set the comparator
+	 * polarity on the sub board charger IC, or send enable signal to HDMI
+	 * DB.
+	 */
+	set_5v_gpio(!!enable);
+
+	if (get_cbi_fw_config_db() == DB_1A_HDMI) {
+		gpio_set_level(GPIO_SUB_C1_INT_EN_RAILS_ODL, !enable);
+	} else {
+		if (isl923x_set_comparator_inversion(1, !!enable))
+			CPRINTS("Failed to %sable sub rails!",
+				enable ? "en" : "dis");
+	}
+}
+
+__override uint8_t board_get_usb_pd_port_count(void)
+{
+	if (get_cbi_fw_config_db() == DB_1A_HDMI)
+		return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
+	else
+		return CONFIG_USB_PD_PORT_MAX_COUNT;
+}
+
+__override uint8_t board_get_charger_chip_count(void)
+{
+	if (get_cbi_fw_config_db() == DB_1A_HDMI)
+		return CHARGER_NUM - 1;
+	else
+		return CHARGER_NUM;
+}
+
+int board_is_sourcing_vbus(int port)
+{
+	int regval;
+
+	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
+	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count());
+	int i;
+	int old_port;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	old_port = charge_manager_get_active_charge_port();
+
+	CPRINTS("New chg p%d", port);
+
+	/* Disable all ports. */
+	if (port == CHARGE_PORT_NONE) {
+		for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+			tcpc_write(i, TCPC_REG_COMMAND,
+				   TCPC_REG_COMMAND_SNK_CTRL_LOW);
+			raa489000_enable_asgate(i, false);
+		}
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if port is sourcing VBUS. */
+	if (board_is_sourcing_vbus(port)) {
+		CPRINTS("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+		if (i == port)
+			continue;
+
+		if (tcpc_write(i, TCPC_REG_COMMAND,
+			       TCPC_REG_COMMAND_SNK_CTRL_LOW))
+			CPRINTS("p%d: sink path disable failed.", i);
+		raa489000_enable_asgate(i, false);
+	}
+
+	/*
+	 * Stop the charger IC from switching while changing ports.  Otherwise,
+	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
+	 */
+	if (old_port != CHARGE_PORT_NONE)
+		charger_discharge_on_ac(1);
+
+	/* Enable requested charge port. */
+	if (raa489000_enable_asgate(port, true) ||
+	    tcpc_write(port, TCPC_REG_COMMAND,
+		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
+		CPRINTS("p%d: sink path enable failed.", port);
+		charger_discharge_on_ac(0);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	/* Allow the charger IC to begin/continue switching. */
+	charger_discharge_on_ac(0);
+
+	return EC_SUCCESS;
+}
+
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	if (port < 0 || port > board_get_usb_pd_port_count())
+		return;
+
+	raa489000_set_output_current(port, rp);
+}
+
+/* Sensors */
+static struct mutex g_lid_mutex;
+static struct mutex g_base_mutex;
+
+static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
+
+/* Matrices to rotate accelerometers into the standard reference. */
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					     { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
+
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+					      { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
+
+static const mat33_fp_t base_standard_ref_lsm = { { FLOAT_TO_FP(1), 0, 0 },
+						  { 0, FLOAT_TO_FP(-1), 0 },
+						  { 0, 0, FLOAT_TO_FP(-1) } };
+
+struct motion_sensor_t ldm6dsm_base_accel = {
+	.name = "Base Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_LSM6DSM,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &lsm6dsm_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
+			MOTIONSENSE_TYPE_ACCEL),
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
+	.rot_standard_ref = &base_standard_ref_lsm,
+	.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
+	.min_frequency = LSM6DSM_ODR_MIN_VAL,
+	.max_frequency = LSM6DSM_ODR_MAX_VAL,
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 13000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+		/* Sensor on for angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+	},
+};
+struct motion_sensor_t ldm6dsm_base_gyro = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_LSM6DSM,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &lsm6dsm_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data, MOTIONSENSE_TYPE_GYRO),
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
+	.default_range = 1000 | ROUND_UP_FLAG, /* dps */
+	.rot_standard_ref = &base_standard_ref_lsm,
+	.min_frequency = LSM6DSM_ODR_MIN_VAL,
+	.max_frequency = LSM6DSM_ODR_MAX_VAL,
+
+};
+
+static struct stprivate_data g_lis2ds_data;
+static struct bmi_drv_data_t g_bmi160_data;
+
+struct motion_sensor_t motion_sensors[] = {
+	[LID_ACCEL] = {
+		.name = "Lid Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LIS2DS,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &lis2ds_drv,
+		.mutex = &g_lid_mutex,
+		.drv_data = &g_lis2ds_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LIS2DS_ADDR1_FLAGS,
+		.rot_standard_ref = &lid_standard_ref,
+		.min_frequency = LIS2DS_ODR_MIN_VAL,
+		.max_frequency = LIS2DS_ODR_MAX_VAL,
+		.default_range = 2, /* g, to support lid angle calculation. */
+		.config = {
+			/* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 12500 | ROUND_UP_FLAG,
+			},
+			/* Sensor on in S3 */
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 12500 | ROUND_UP_FLAG,
+			},
+		},
+	},
+	[BASE_ACCEL] = {
+		.name = "Base Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMI160,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &bmi160_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = &g_bmi160_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+		.rot_standard_ref = &base_standard_ref,
+		.default_range = 4,
+		.min_frequency = BMI_ACCEL_MIN_FREQ,
+		.max_frequency = BMI_ACCEL_MAX_FREQ,
+		.config = {
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 13000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+		},
+	},
+	[BASE_GYRO] = {
+		.name = "Base Gyro",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMI160,
+		.type = MOTIONSENSE_TYPE_GYRO,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &bmi160_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = &g_bmi160_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+		.default_range = 1000, /* dps */
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = BMI_GYRO_MIN_FREQ,
+		.max_frequency = BMI_GYRO_MAX_FREQ,
+	},
+};
+
+const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+enum base_accelgyro_type {
+	BASE_GYRO_NONE = 0,
+	BASE_GYRO_BMI160 = 1,
+	BASE_GYRO_LSM6DSM = 2,
+};
+
+static enum base_accelgyro_type base_accelgyro_config;
+static void board_set_motionsensor(void)
+{
+	if (board_id == -1) {
+		uint32_t val;
+
+		if (cbi_get_board_version(&val) == EC_SUCCESS)
+			board_id = val;
+	}
+
+	base_accelgyro_config = BASE_GYRO_BMI160;
+	if (board_id > 6) {
+		motion_sensors[BASE_ACCEL] = ldm6dsm_base_accel;
+		motion_sensors[BASE_GYRO] = ldm6dsm_base_gyro;
+		base_accelgyro_config = BASE_GYRO_LSM6DSM;
+	}
+}
+DECLARE_HOOK(HOOK_INIT, board_set_motionsensor, HOOK_PRIO_INIT_I2C + 2);
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	if (base_accelgyro_config == BASE_GYRO_BMI160)
+		bmi160_interrupt(signal);
+	else
+		lsm6dsm_interrupt(signal);
+}
+
+__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+				       int *ki_div, int *kd, int *kd_div)
+{
+	*kp = 1;
+	*kp_div = 20;
+	*ki = 1;
+	*ki_div = 250;
+	*kd = 0;
+	*kd_div = 1;
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	return pd_check_vbus_level(port, VBUS_PRESENT);
+}
+
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+
+	{
+		.i2c_port = I2C_PORT_SUB_USB_C1,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+};
+
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	{
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+		.flags = PI3USB9201_ALWAYS_POWERED,
+	},
+
+	{
+		.i2c_port = I2C_PORT_SUB_USB_C1,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+		.flags = PI3USB9201_ALWAYS_POWERED,
+	},
+};
+
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0,
+			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
+		},
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+		.drv = &raa489000_tcpm_drv,
+	},
+
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_SUB_USB_C1,
+			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
+		},
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+		.drv = &raa489000_tcpm_drv,
+	},
+};
+
+static int ps8743_tune_mux_c0(const struct usb_mux *me);
+static int ps8743_tune_mux_c1(const struct usb_mux *me);
+
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = PS8743_I2C_ADDR0_FLAG,
+				.driver = &ps8743_usb_mux_driver,
+				.board_init = &ps8743_tune_mux_c0,
+			},
+	},
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_SUB_USB_C1,
+				.i2c_addr_flags = PS8743_I2C_ADDR0_FLAG,
+				.driver = &ps8743_usb_mux_driver,
+				.board_init = &ps8743_tune_mux_c1,
+			},
+	}
+};
+/* USB Mux C0 : board_init of PS8743 */
+static int ps8743_tune_mux_c0(const struct usb_mux *me)
+{
+	ps8743_tune_usb_eq(me, PS8743_USB_EQ_TX_3_6_DB,
+			   PS8743_USB_EQ_RX_16_0_DB);
+
+	return EC_SUCCESS;
+}
+/* USB Mux C1 : board_init of PS8743 */
+static int ps8743_tune_mux_c1(const struct usb_mux *me)
+{
+	ps8743_tune_usb_eq(me, PS8743_USB_EQ_TX_3_6_DB,
+			   PS8743_USB_EQ_RX_16_0_DB);
+
+	ps8743_write(me, PS8743_REG_USB_SWING, PS8743_LFPS_SWG_TD);
+	ps8743_write(me, PS8743_REG_DP_SETTING, PS8743_DP_SWG_ADJ_P15P);
+
+	return EC_SUCCESS;
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+	int regval;
+
+	/*
+	 * The interrupt line is shared between the TCPC and BC1.2 detector IC.
+	 * Therefore, go out and actually read the alert registers to report the
+	 * alert status.
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
+			/* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */
+			if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0))
+				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
+
+			if (regval)
+				status |= PD_STATUS_TCPC_ALERT_0;
+		}
+	}
+
+	if (board_get_usb_pd_port_count() > 1 &&
+	    !gpio_get_level(GPIO_SUB_C1_INT_EN_RAILS_ODL)) {
+		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
+			/* TCPCI spec Rev 1.0 says to ignore bits 14:12. */
+			if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0))
+				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
+
+			if (regval)
+				status |= PD_STATUS_TCPC_ALERT_1;
+		}
+	}
+
+	return status;
+}
+static const struct ec_response_keybd_config keybd1 = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_FORWARD,		/* T2 */
+		TK_REFRESH,		/* T3 */
+		TK_FULLSCREEN,		/* T4 */
+		TK_OVERVIEW,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	/* No function keys, no numeric keypad, has screenlock key */
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	/*
+	 * Future boards should use fw_config if needed.
+	 */
+
+	return &keybd1;
+}
+
+#ifndef TEST_BUILD
+/* This callback disables keyboard when convertibles are fully open */
+void lid_angle_peripheral_enable(int enable)
+{
+	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
+
+	/*
+	 * If the lid is in tablet position via other sensors,
+	 * ignore the lid angle, which might be faulty then
+	 * disable keyboard.
+	 */
+	if (tablet_get_mode())
+		enable = 0;
+
+	if (enable) {
+		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
+	} else {
+		/*
+		 * Ensure that the chipset is off before disabling the keyboard.
+		 * When the chipset is on, the EC keeps the keyboard enabled and
+		 * the AP decides whether to ignore input devices or not.
+		 */
+		if (!chipset_in_s0)
+			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
+	}
+}
+#endif
+/**
+ * Enable panel power detection
+ */
+static void panel_power_detect_init(void)
+{
+	gpio_enable_interrupt(GPIO_EN_PP1800_PANEL_S0);
+}
+DECLARE_HOOK(HOOK_INIT, panel_power_detect_init, HOOK_PRIO_DEFAULT);
+
+/**
+ * Handle VPN / VSN for mipi display.
+ */
+static void panel_power_change_deferred(void)
+{
+	int signal = gpio_get_level(GPIO_EN_PP1800_PANEL_S0);
+
+	if (board_id == -1) {
+		uint32_t val;
+
+		if (cbi_get_board_version(&val) == EC_SUCCESS)
+			board_id = val;
+	}
+	if (board_id < 4) {
+		gpio_set_level(GPIO_EN_LCD_ENP, signal);
+		msleep(1);
+		gpio_set_level(GPIO_EN_LCD_ENN, signal);
+	} else if (signal != 0) {
+		i2c_write8(I2C_PORT_LCD, I2C_ADDR_ISL98607_FLAGS,
+			   ISL98607_REG_VBST_OUT, ISL98607_VBST_OUT_5P65);
+		i2c_write8(I2C_PORT_LCD, I2C_ADDR_ISL98607_FLAGS,
+			   ISL98607_REG_VN_OUT, ISL98607_VN_OUT_5P5);
+		i2c_write8(I2C_PORT_LCD, I2C_ADDR_ISL98607_FLAGS,
+			   ISL98607_REG_VP_OUT, ISL98607_VP_OUT_5P5);
+	}
+	gpio_set_level(GPIO_TSP_TA, signal & extpower_is_present());
+}
+DECLARE_DEFERRED(panel_power_change_deferred);
+
+void panel_power_change_interrupt(enum gpio_signal signal)
+{
+	/* Reset lid debounce time */
+	hook_call_deferred(&panel_power_change_deferred_data, 1 * MSEC);
+}
+
+/*
+ * Detect LCD reset & control LCD DCDC power
+ */
+static void lcd_reset_detect_init(void)
+{
+	if (board_id == -1) {
+		uint32_t val;
+
+		if (cbi_get_board_version(&val) == EC_SUCCESS)
+			board_id = val;
+	}
+
+	if (board_id < 4)
+		return;
+	gpio_enable_interrupt(GPIO_DDI0_DDC_SCL);
+}
+DECLARE_HOOK(HOOK_INIT, lcd_reset_detect_init, HOOK_PRIO_DEFAULT);
+/*
+ * Handle VSP / VSN for mipi display when lcd turns off
+ */
+static void lcd_reset_change_deferred(void)
+{
+	int signal = gpio_get_level(GPIO_DDI0_DDC_SCL);
+
+	if (signal != 0)
+		return;
+
+	signal = gpio_get_level(GPIO_EN_PP1800_PANEL_S0);
+
+	if (signal == 0)
+		return;
+
+	i2c_write8(I2C_PORT_LCD, I2C_ADDR_ISL98607_FLAGS, ISL98607_REG_ENABLE,
+		   ISL97607_VP_VN_VBST_DIS);
+}
+DECLARE_DEFERRED(lcd_reset_change_deferred);
+void lcd_reset_change_interrupt(enum gpio_signal signal)
+{
+	hook_call_deferred(&lcd_reset_change_deferred_data, 45 * MSEC);
+}
+
+/**
+ * Handle TSP_TA according to AC status
+ */
+static void handle_tsp_ta(void)
+{
+	int signal = gpio_get_level(GPIO_EN_PP1800_PANEL_S0);
+
+	gpio_set_level(GPIO_TSP_TA, signal & extpower_is_present());
+}
+DECLARE_HOOK(HOOK_AC_CHANGE, handle_tsp_ta, HOOK_PRIO_DEFAULT);
+
+/******************************************************************************/
+/* USB-A charging control */
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_USB_A0_VBUS,
+};
+
+/*
+ * Change LED Driver Current
+ * LED driver current must be written when EN_BL_OD goes from Low to High.
+ */
+static int backup_enable_backlight = -1;
+void backlit_gpio_tick(void)
+{
+	int signal = gpio_get_level(GPIO_ENABLE_BACKLIGHT);
+
+	if (backup_enable_backlight == signal)
+		return;
+
+	backup_enable_backlight = signal;
+	if (board_id == -1) {
+		uint32_t val;
+
+		if (cbi_get_board_version(&val) == EC_SUCCESS)
+			board_id = val;
+	}
+
+	if (board_id >= 4 && signal == 1)
+		i2c_write16(I2C_PORT_LCD, I2C_ADDR_MP3372_FLAGS,
+			    MP3372_REG_ISET_CHEN, MP3372_ISET_15P3_CHEN_ALL);
+}
+DECLARE_HOOK(HOOK_TICK, backlit_gpio_tick, HOOK_PRIO_DEFAULT);
diff --git a/board/bugzzy/board.h b/board/bugzzy/board.h
new file mode 100644
index 0000000000..b62928b5e1
--- /dev/null
+++ b/board/bugzzy/board.h
@@ -0,0 +1,244 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Waddledoo board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#define VARIANT_DEDEDE_EC_NPCX796FC
+#include "baseboard.h"
+
+#undef CONFIG_I2C_DEBUG
+/*
+ * The RAM and flash size combination on the the NPCX797FC does not leave
+ * any unused flash space that can be used to store the .init_rom section.
+ */
+#undef CONFIG_CHIP_INIT_ROM_REGION
+
+/* Save some flash space */
+#define CONFIG_DEBUG_ASSERT_BRIEF
+#undef CONFIG_CMD_ACCELSPOOF
+#undef CONFIG_CMD_BATTFAKE
+
+/* EC console commands */
+#define CONFIG_CMD_TCPC_DUMP
+#define CONFIG_CMD_CHARGER_DUMP
+
+/* Battery */
+#define CONFIG_BATTERY_FUEL_GAUGE
+
+/* Charger */
+#define CONFIG_CHARGER_RAA489000
+#define PD_MAX_VOLTAGE_MV 20000
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_OCPC_DEF_RBATT_MOHMS               \
+	22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \
+	    */
+#define CONFIG_OCPC
+#define CONFIG_CHARGE_RAMP_HW
+#undef CONFIG_CHARGER_SINGLE_CHIP
+#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
+#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
+/*
+ * b/147463641: The charger IC seems to overdraw ~4%, therefore we
+ * reduce our target accordingly.
+ */
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 4
+#define CONFIG_BATTERY_CHECK_CHARGE_TEMP_LIMITS
+#define CONFIG_CHARGER_PROFILE_OVERRIDE
+
+/*
+ * GPIO for C1 interrupts, for baseboard use
+ *
+ * Note this line might already have its pull up disabled for HDMI DBs, but
+ * it should be fine to set again before z-state.
+ */
+#define GPIO_USB_C1_INT_ODL GPIO_SUB_C1_INT_EN_RAILS_ODL
+
+/* Keyboard */
+
+/* LED */
+#define CONFIG_LED_COMMON
+#define CONFIG_LED_ONOFF_STATES
+#define GPIO_BAT_LED_RED_L GPIO_LED_R_ODL
+#define GPIO_BAT_LED_GREEN_L GPIO_LED_G_ODL
+#define GPIO_PWR_LED_BLUE_L GPIO_LED_B_ODL
+
+/* PWM */
+#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */
+
+/* Thermistors */
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_THERMISTOR
+#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
+
+/* USB */
+#define CONFIG_BC12_DETECT_PI3USB9201
+#define CONFIG_USB_MUX_PS8743
+
+/* USB PD */
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#define CONFIG_USB_PD_TCPM_RAA489000
+#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
+#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
+#define CONFIG_USB_PD_COMM_LOCKED
+
+/* USB defines specific to external TCPCs */
+#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+#define CONFIG_USB_PD_VBUS_DETECT_TCPC
+#define CONFIG_USB_PD_DISCHARGE_TCPC
+#define CONFIG_USB_PD_TCPC_LOW_POWER
+
+/* USB Type A Features */
+#define USB_PORT_COUNT 1
+#define CONFIG_USB_PORT_POWER_DUMB
+
+/* Variant references the TCPCs to determine Vbus sourcing */
+#define CONFIG_USB_PD_5V_EN_CUSTOM
+
+#undef PD_POWER_SUPPLY_TURN_ON_DELAY
+#undef PD_POWER_SUPPLY_TURN_OFF_DELAY
+#undef CONFIG_USBC_VCONN_SWAP_DELAY_US
+/* 20% margin added for these timings */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 13080 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 16080 /* us */
+#undef CONFIG_USBC_VCONN_SWAP_DELAY_US
+#define CONFIG_USBC_VCONN_SWAP_DELAY_US 787 /* us */
+
+/* I2C configuration */
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
+#define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0
+#define I2C_PORT_LCD NPCX_I2C_PORT3_0
+/* TODO(b:147440290): Need to handle multiple charger ICs */
+#define I2C_PORT_CHARGER I2C_PORT_USB_C0
+
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */
+#define I2C_ADDR_ISL98607_FLAGS 0x29
+#define I2C_ADDR_MP3372_FLAGS 0x28
+
+/* ISL98607 registers and value */
+/* Enable VP / VN / VBST */
+#define ISL98607_REG_ENABLE 0x05
+#define ISL98607_VP_VN_VBST_EN 0x07
+#define ISL97607_VP_VN_VBST_DIS 0x00
+
+/* VBST Voltage Adjustment */
+#define ISL98607_REG_VBST_OUT 0x06
+#define ISL98607_VBST_OUT_5P65 0x0a
+
+/* VN Voltage Adjustment */
+#define ISL98607_REG_VN_OUT 0x08
+#define ISL98607_VN_OUT_5P5 0x0a
+
+/* VP Voltage Adjustment */
+#define ISL98607_REG_VP_OUT 0x09
+#define ISL98607_VP_OUT_5P5 0x0a
+
+/* MP3372 registers and value */
+/* ISET & CHEN */
+#define MP3372_REG_ISET_CHEN 0x00
+#define MP3372_ISET_21P8_CHEN_ALL 0x70ff
+#define MP3372_ISET_19P4_CHEN_ALL 0x63ff
+#define MP3372_ISET_18P0_CHEN_ALL 0x5cff
+#define MP3372_ISET_15P8_CHEN_ALL 0x50ff
+#define MP3372_ISET_15P3_CHEN_ALL 0x4eff
+/*
+ * I2C pin names for baseboard
+ *
+ * Note: these lines will be set as i2c on start-up, but this should be
+ * okay since they're ODL.
+ */
+#define GPIO_EC_I2C_SUB_USB_C1_SCL GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL
+#define GPIO_EC_I2C_SUB_USB_C1_SDA GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL
+
+/* Sensors */
+#define CONFIG_CMD_ACCELS
+#define CONFIG_CMD_ACCEL_INFO
+
+#define CONFIG_ACCELGYRO_BMI160 /* Base accel */
+
+/* Lid operates in forced mode, base in interrupt mode */
+#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
+#define CONFIG_ACCEL_FIFO
+#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */
+#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
+
+#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
+#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_UPDATE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+
+#define CONFIG_TABLET_MODE
+#define CONFIG_TABLET_MODE_SWITCH
+
+/* On-body detection */
+#define CONFIG_BODY_DETECTION
+#define CONFIG_BODY_DETECTION_SENSOR BASE_ACCEL
+#define CONFIG_BODY_DETECTION_VAR_NOISE_FACTOR 150 /* % */
+#define CONFIG_GESTURE_DETECTION
+#define CONFIG_GESTURE_DETECTION_MASK BIT(CONFIG_BODY_DETECTION_SENSOR)
+#define CONFIG_GESTURE_HOST_DETECTION
+
+/* LIS2DS Lid accel */
+#define CONFIG_ACCEL_LIS2DS
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum chg_id {
+	CHARGER_PRIMARY,
+	CHARGER_SECONDARY,
+	CHARGER_NUM,
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1,
+	TEMP_SENSOR_2,
+	TEMP_SENSOR_3,
+	TEMP_SENSOR_4,
+	TEMP_SENSOR_COUNT
+};
+
+enum adc_channel {
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
+	ADC_TEMP_SENSOR_3, /* ADC5 */
+	ADC_TEMP_SENSOR_4, /* ADC6 */
+	ADC_SUB_ANALOG, /* ADC2 */
+	ADC_VSNS_PP3300_A, /* ADC9 */
+	ADC_CH_COUNT
+};
+
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
+
+/* List of possible batteries */
+enum battery_type {
+	BATTERY_SDI,
+	BATTERY_TYPE_COUNT,
+};
+
+void panel_power_change_interrupt(enum gpio_signal signal);
+void lcd_reset_change_interrupt(enum gpio_signal signal);
+void motion_interrupt(enum gpio_signal signal);
+#endif /* !__ASSEMBLER__ */
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/bugzzy/build.mk b/board/bugzzy/build.mk
new file mode 100644
index 0000000000..5b37e085ef
--- /dev/null
+++ b/board/bugzzy/build.mk
@@ -0,0 +1,14 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx7
+CHIP_VARIANT:=npcx7m7fc
+BASEBOARD:=dedede
+
+board-y=board.o battery.o cbi_ssfc.o led.o usb_pd_policy.o
diff --git a/board/bugzzy/cbi_ssfc.c b/board/bugzzy/cbi_ssfc.c
new file mode 100644
index 0000000000..81f3ee0dad
--- /dev/null
+++ b/board/bugzzy/cbi_ssfc.c
@@ -0,0 +1,36 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi_ssfc.h"
+#include "common.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "hooks.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+/* Cache SSFC on init since we don't expect it to change in runtime */
+static union dedede_cbi_ssfc cached_ssfc;
+BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
+
+static void cbi_ssfc_init(void)
+{
+	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
+		/* Default to 0 when CBI isn't populated */
+		cached_ssfc.raw_value = 0;
+
+	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
+}
+DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
+
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
+{
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
+}
+
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
+{
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
+}
diff --git a/board/bugzzy/cbi_ssfc.h b/board/bugzzy/cbi_ssfc.h
new file mode 100644
index 0000000000..bf8853a43a
--- /dev/null
+++ b/board/bugzzy/cbi_ssfc.h
@@ -0,0 +1,59 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _DEDEDE_CBI_SSFC__H_
+#define _DEDEDE_CBI_SSFC__H_
+
+#include "stdint.h"
+
+/****************************************************************************
+ * Dedede CBI Second Source Factory Cache
+ */
+
+/*
+ * Base Sensor (Bits 0-2)
+ */
+enum ec_ssfc_base_sensor {
+	SSFC_SENSOR_BASE_DEFAULT = 0,
+	SSFC_SENSOR_BMI160 = 1,
+	SSFC_SENSOR_ICM426XX = 2,
+	SSFC_SENSOR_LSM6DSM = 3,
+	SSFC_SENSOR_ICM42607 = 4
+};
+
+/*
+ * Lid Sensor (Bits 3-5)
+ */
+enum ec_ssfc_lid_sensor {
+	SSFC_SENSOR_LID_DEFAULT = 0,
+	SSFC_SENSOR_BMA255 = 1,
+	SSFC_SENSOR_KX022 = 2,
+	SSFC_SENSOR_LIS2DWL = 3
+};
+
+union dedede_cbi_ssfc {
+	struct {
+		uint32_t base_sensor : 3;
+		uint32_t lid_sensor : 3;
+		uint32_t reserved_2 : 26;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Get the Base sensor type from SSFC_CONFIG.
+ *
+ * @return the Base sensor board type.
+ */
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
+
+/**
+ * Get the Lid sensor type from SSFC_CONFIG.
+ *
+ * @return the Lid sensor board type.
+ */
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
+
+#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/bugzzy/ec.tasklist b/board/bugzzy/ec.tasklist
new file mode 100644
index 0000000000..29666dd959
--- /dev/null
+++ b/board/bugzzy/ec.tasklist
@@ -0,0 +1,25 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/bugzzy/gpio.inc b/board/bugzzy/gpio.inc
new file mode 100644
index 0000000000..8e0fa56768
--- /dev/null
+++ b/board/bugzzy/gpio.inc
@@ -0,0 +1,140 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first.
+ */
+
+/* Power Interrupts */
+GPIO_INT(SLP_S0_L,		 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,		 PIN(A, 5), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(SLP_S4_L,		 PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,		 PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(RSMRST_PWRGD_L,	 PIN(C, 6), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID1,	 PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(CPU_C10_GATE_L,	 PIN(6, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID0,	 PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, power_signal_interrupt)
+GPIO_INT(PG_VCCIO_EXT_OD,	 PIN(B, 0), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(PG_PP5000_U_OD,	 PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_DRAM_OD,		 PIN(E, 4), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(PG_PP1050_ST_OD,	 PIN(4, 2), GPIO_INT_BOTH, power_signal_interrupt)
+
+/* USB-C interrupts */
+GPIO_INT(USB_C0_INT_ODL,	 		PIN(6, 2), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt)
+GPIO_INT(SUB_C1_INT_EN_RAILS_ODL,		PIN(F, 5), GPIO_INT_FALLING | GPIO_PULL_UP, sub_usb_c1_interrupt) /* C1 interrupt OR 5V power en */
+GPIO_INT(EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL,	PIN(9, 1), GPIO_INT_BOTH, sub_hdmi_hpd_interrupt) /* C1 I2C SDA OR HDMI_HPD */
+
+/* Button interrupts */
+GPIO_INT(H1_EC_PWR_BTN_ODL,	 PIN(0, 1), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
+GPIO_INT(VOLDN_BTN_ODL,          PIN(4, 0), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(VOLUP_BTN_ODL,          PIN(7, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+
+/* Other interrupts */
+GPIO_INT(LID_OPEN,		 PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)
+GPIO_INT(EC_WP_OD,		 PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(BASE_SIXAXIS_INT_L,	 PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, motion_interrupt)
+GPIO_INT(EN_PP1800_PANEL_S0,     PIN(4, 1), GPIO_INT_BOTH, panel_power_change_interrupt)
+GPIO_INT(DDI0_DDC_SCL,		 PIN(6, 0), GPIO_INT_FALLING, lcd_reset_change_interrupt)
+
+/* I2C Ports */
+GPIO(EC_I2C_EEPROM_SCL,			PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SDA,			PIN(B, 2), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SCL,		PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SDA,		PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,			PIN(B, 5), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SDA,			PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SCL,			PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SDA,			PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_SUB_C1_SCL_HDMI_EN_ODL,	PIN(9, 2), GPIO_INPUT) /* C1 I2C SCL OR HDMI en */
+GPIO(EC_I2C_LCD_SCL,			PIN(D, 1), GPIO_INPUT)
+GPIO(EC_I2C_LCD_SDA,			PIN(D, 0), GPIO_INPUT)
+
+/* Misc Enables */
+GPIO(LID_360_L,		 PIN(9, 5), GPIO_INPUT)
+GPIO(EN_VCCIO_EXT,   PIN(6, 1), GPIO_OUT_LOW)
+/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
+GPIO(EN_VCCST,		PIN(A, 7), GPIO_INPUT)
+GPIO(EN_PP3300_A,	PIN(0, 3), GPIO_OUT_LOW)
+GPIO(EN_PP5000_U,	PIN(A, 4), GPIO_OUT_LOW)
+GPIO(EN_SLP_Z,		PIN(8, 3), GPIO_OUT_LOW)
+GPIO(EN_BL_OD,		PIN(D, 3), GPIO_ODR_LOW)
+GPIO(IMVP9_PE,		PIN(E, 0), GPIO_OUT_LOW)
+GPIO(ECH1_PACKET_MODE,	PIN(7, 5), GPIO_OUT_LOW)
+GPIO(LED_R_ODL,		PIN(C, 4), GPIO_OUT_HIGH)
+GPIO(LED_G_ODL,		PIN(C, 3), GPIO_OUT_HIGH)
+GPIO(LED_B_ODL,		PIN(C, 2), GPIO_OUT_HIGH)
+GPIO(EN_LCD_ENN,	PIN(9, 7), GPIO_OUT_LOW)
+GPIO(EN_LCD_ENP,	PIN(8, 6), GPIO_OUT_LOW)
+GPIO(TSP_TA,		PIN(A, 2), GPIO_OUT_LOW)
+
+/* Power Sequencing */
+GPIO(EC_AP_PSYS,	     PIN(B, 7), GPIO_OUT_LOW)
+GPIO(EC_AP_RSMRST_L,         PIN(A, 6), GPIO_OUT_LOW)
+GPIO(EC_AP_PWR_BTN_ODL,      PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(EC_AP_RTCRST,           PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_AP_WAKE_ODL,         PIN(7, 4), GPIO_ODR_HIGH)
+GPIO(EC_AP_DPWROK,	     PIN(A, 3), GPIO_OUT_LOW)
+GPIO(EC_AP_PCH_PWROK_OD,     PIN(9, 4), GPIO_ODR_LOW)
+GPIO(EC_AP_VCCST_PWRGD_OD,   PIN(B, 1), GPIO_ODR_LOW)
+GPIO(EC_AP_SYS_PWROK,	     PIN(0, 2), GPIO_OUT_LOW)
+GPIO(EC_AP_MKBP_INT_L,	     PIN(7, 0), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_ODL,	     PIN(F, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(EC_ENTERING_RW,	     PIN(E, 3), GPIO_OUT_LOW)
+GPIO(ALL_SYS_PWRGD,	     PIN(A, 0), GPIO_OUT_LOW)
+GPIO(SYS_RST_ODL,	     PIN(C, 5), GPIO_ODR_HIGH)
+GPIO(CCD_MODE_ODL,	     PIN(E, 5), GPIO_ODR_HIGH)
+
+GPIO(EC_AP_USB_C1_HDMI_HPD,  PIN(9, 6), GPIO_OUT_LOW)
+GPIO(EC_AP_USB_C0_HPD,	     PIN(9, 3), GPIO_OUT_LOW)
+GPIO(HDMI_SEL_L,	     PIN(7, 2), GPIO_OUT_HIGH)
+GPIO(EC_BATTERY_PRES_ODL,    PIN(E, 1), GPIO_INPUT)
+GPIO(EN_USB_A0_VBUS,	     PIN(6, 3), GPIO_OUT_LOW)
+
+/*
+ * Waddledoo doesn't have these physical pins coming to the EC but uses other
+ * logic.
+ */
+UNIMPLEMENTED(AC_PRESENT)
+UNIMPLEMENTED(PG_EC_DSW_PWROK)
+UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
+
+/* Alternate Functions */
+/* ADC */
+ALTERNATE(PIN_MASK(F, BIT(0)), 0, MODULE_ADC, 0) /* ADC9 */
+ALTERNATE(PIN_MASK(4, 0x38), 0, MODULE_ADC, 0)   /* ADC0-2 */
+ALTERNATE(PIN_MASK(3, 0x90), 0, MODULE_ADC, 0)	/* ADC5-6 */
+
+/* Keyboard */
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI0, KSI1 */
+ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI2-7 */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO0, KSO1 */
+ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO3-9 */
+ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO10-13 */
+ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO14 */
+GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW)	/* KSO2 inverted */
+
+/* UART */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)  /* UART1 */
+
+/* I2C */
+ALTERNATE(PIN_MASK(B, 0x3C), 0, MODULE_I2C, 0)   /* I2C7,I2C0 */
+ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)   /* I2C5 */
+ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)   /* I2C2, I2C1 SCL */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)   /* I2C1 SDA */
+ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)   /* I2C3 */
+
+/* NC pins, enable internal pull-up to avoid floating state. */
+GPIO(GPIO00_NC, PIN(0, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIO32_NC, PIN(3, 2), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIO35_NC, PIN(3, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIO50_NC, PIN(5, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIO57_NC, PIN(5, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIO80_NC, PIN(8, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIO81_NC, PIN(8, 1), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOD6_NC, PIN(D, 6), GPIO_INPUT | GPIO_PULL_DOWN)
diff --git a/board/bugzzy/led.c b/board/bugzzy/led.c
new file mode 100644
index 0000000000..cad2d5ed0b
--- /dev/null
+++ b/board/bugzzy/led.c
@@ -0,0 +1,156 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power and battery LED control for bugzzy
+ */
+
+#include "chipset.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
+
+__override const int led_charge_lvl_1 = 1;
+
+__override const int led_charge_lvl_2 = 100;
+
+/* bugzzy : There are 3 leds for AC, Battery and Power */
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     1 * LED_ONE_SEC },
+					   { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_GREEN,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED,
+					    0.5 * LED_ONE_SEC },
+					  { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					 { LED_OFF, 1 * LED_ONE_SEC } },
+	};
+
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_BLUE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_power(enum ec_led_colors color)
+{
+	static enum ec_led_colors prev_color = EC_LED_COLOR_COUNT;
+
+	/* Don't set led if led_auto_control is disabled. */
+	if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) ||
+	    !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
+		return;
+	}
+
+	/*
+	 * Sometimes system wakes and sleeps automatically.
+	 * Add LED debounce time to prevent blinking led by this.
+	 */
+	if (prev_color != color) {
+		prev_color = color;
+		return;
+	}
+
+	if (color == EC_LED_COLOR_BLUE) {
+		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_ON_LVL);
+	} else {
+		/* LED_OFF and unsupported colors */
+		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_OFF_LVL);
+	}
+}
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	static enum ec_led_colors prev_color = EC_LED_COLOR_COUNT;
+
+	/* Don't set led if led_auto_control is disabled. */
+	if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) ||
+	    !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
+		return;
+	}
+
+	/*
+	 * Sometimes system wakes and sleeps automatically.
+	 * Add LED debounce time to prevent blinking led by this.
+	 */
+	if (prev_color != color) {
+		prev_color = color;
+		return;
+	}
+	/*
+	 * Battery leds must be turn off when blue led is on
+	 * because bugzzy has 3-in-1 led.
+	 */
+	if (!gpio_get_level(GPIO_PWR_LED_BLUE_L)) {
+		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); /*red*/
+		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); /*green*/
+		return;
+	}
+
+	switch (color) {
+	case EC_LED_COLOR_GREEN:
+		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); /*red*/
+		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_ON_LVL); /*green*/
+		break;
+	case EC_LED_COLOR_RED:
+		gpio_set_level(GPIO_BAT_LED_RED_L, LED_ON_LVL); /*red*/
+		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); /*green*/
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); /*red*/
+		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); /*green*/
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_GREEN] = 1;
+		brightness_range[EC_LED_COLOR_RED] = 1;
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		brightness_range[EC_LED_COLOR_BLUE] = 1;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_BAT_LED_GREEN_L,
+			       !brightness[EC_LED_COLOR_GREEN]);
+		gpio_set_level(GPIO_BAT_LED_RED_L,
+			       !brightness[EC_LED_COLOR_RED]);
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		gpio_set_level(GPIO_PWR_LED_BLUE_L,
+			       !brightness[EC_LED_COLOR_BLUE]);
+		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/board/bugzzy/usb_pd_policy.c b/board/bugzzy/usb_pd_policy.c
new file mode 100644
index 0000000000..83c09bb99e
--- /dev/null
+++ b/board/bugzzy/usb_pd_policy.c
@@ -0,0 +1,61 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "driver/charger/isl923x_public.h"
+#include "driver/tcpm/tcpci.h"
+#include "usb_pd.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+int pd_check_vconn_swap(int port)
+{
+	/* Allow VCONN swaps if the AP is on. */
+	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
+}
+
+void pd_power_supply_reset(int port)
+{
+	/* Disable VBUS */
+	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	if (port >= board_get_usb_pd_port_count())
+		return EC_ERROR_INVAL;
+
+	/* Disable charging. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
+	if (rv)
+		return rv;
+
+	/* Our policy is not to source VBUS when the AP is off. */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	/* Provide Vbus. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
+	if (rv)
+		return rv;
+
+	rv = raa489000_enable_asgate(port, true);
+	if (rv)
+		return rv;
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
diff --git a/board/bugzzy/vif_override.xml b/board/bugzzy/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/bugzzy/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/burnet/battery.c b/board/burnet/battery.c
index 6373040d45..d76634d6ce 100644
--- a/board/burnet/battery.c
+++ b/board/burnet/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,7 +9,7 @@
 
 const struct board_batt_params board_battery_info[] = {
 	/* Dynapack ATL Battery Information */
-	[BATTERY_DANAPACK_ATL] = {
+	[BATTERY_DYNAPACK_ATL] = {
 		.fuel_gauge = {
 			.manuf_name = "333-27-DA-A",
 			.ship_mode = {
@@ -34,10 +34,11 @@ const struct board_batt_params board_battery_info[] = {
 			.charging_max_c = 45,
 			.discharging_min_c = -10,
 			.discharging_max_c = 60,
+			.vendor_param_start = 0x70,
 		},
 	},
 	/* Dynapack CosMX Battery Information */
-	[BATTERY_DANAPACK_COS] = {
+	[BATTERY_DYNAPACK_COS] = {
 		.fuel_gauge = {
 			.manuf_name = "333-2C-DA-A",
 			.ship_mode = {
@@ -62,6 +63,7 @@ const struct board_batt_params board_battery_info[] = {
 			.charging_max_c = 45,
 			.discharging_min_c = -10,
 			.discharging_max_c = 60,
+			.vendor_param_start = 0x70,
 		},
 	},
 	/* Simplo CosMX Battery Information */
@@ -90,6 +92,7 @@ const struct board_batt_params board_battery_info[] = {
 			.charging_max_c = 45,
 			.discharging_min_c = -10,
 			.discharging_max_c = 60,
+			.vendor_param_start = 0x70,
 		},
 	},
 	/* Simplo HIGHPOWER Battery Information */
@@ -118,6 +121,7 @@ const struct board_batt_params board_battery_info[] = {
 			.charging_max_c = 45,
 			.discharging_min_c = -10,
 			.discharging_max_c = 60,
+			.vendor_param_start = 0x70,
 		},
 	},
 	/* Samsung SDI Battery Information */
@@ -146,6 +150,7 @@ const struct board_batt_params board_battery_info[] = {
 			.charging_max_c = 45,
 			.discharging_min_c = -10,
 			.discharging_max_c = 60,
+			.vendor_param_start = 0x70,
 		},
 	},
 	/* CosMX Battery Information */
@@ -174,12 +179,100 @@ const struct board_batt_params board_battery_info[] = {
 			.charging_max_c = 45,
 			.discharging_min_c = -10,
 			.discharging_max_c = 60,
+			.vendor_param_start = 0x70,
+		},
+	},
+	/* DynaPack CosMX DAK125720-W0P0701HT Battery Information */
+	[BATTERY_DYNAPACK_COS_44WH] = {
+		.fuel_gauge = {
+			.manuf_name = "333-2C-DB-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,		/* mV */
+			.voltage_normal = 7700,		/* mV */
+			.voltage_min = 6000,		/* mV */
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+			.vendor_param_start = 0x70,
+		},
+	},
+	/* DynaPack ATL DAK125720-W0G0701HT Battery Information */
+	[BATTERY_DYNAPACK_ATL_44WH] = {
+		.fuel_gauge = {
+			.manuf_name = "333-27-DB-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,		/* mV */
+			.voltage_normal = 7700,		/* mV */
+			.voltage_min = 6000,		/* mV */
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+			.vendor_param_start = 0x70,
+		},
+	},
+	/* Simplo HIGHPOWER 996Q4242H Battery Information */
+	[BATTERY_SIMPLO_HIGHPOWER_44WH] = {
+		.fuel_gauge = {
+			.manuf_name = "333-1D-DB-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,		/* mV */
+			.voltage_normal = 7700,		/* mV */
+			.voltage_min = 6000,		/* mV */
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+			.vendor_param_start = 0x70,
 		},
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
 
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_DANAPACK_ATL;
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_DYNAPACK_ATL;
 
 enum battery_present battery_hw_present(void)
 {
diff --git a/board/burnet/board.c b/board/burnet/board.c
index 18929f50d2..95fa8e2d85 100644
--- a/board/burnet/board.c
+++ b/board/burnet/board.c
@@ -1,10 +1,9 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "backlight.h"
 #include "button.h"
 #include "charge_manager.h"
@@ -15,7 +14,10 @@
 #include "common.h"
 #include "console.h"
 #include "driver/accel_bma2x2.h"
+#include "driver/accel_kionix.h"
 #include "driver/accelgyro_bmi_common.h"
+#include "driver/accelgyro_icm42607.h"
+#include "driver/accelgyro_icm_common.h"
 #include "driver/battery/max17055.h"
 #include "driver/bc12/pi3usb9201.h"
 #include "driver/charger/isl923x.h"
@@ -32,6 +34,7 @@
 #include "it8801.h"
 #include "keyboard_scan.h"
 #include "lid_switch.h"
+#include "panic.h"
 #include "power.h"
 #include "power_button.h"
 #include "registers.h"
@@ -39,41 +42,55 @@
 #include "system.h"
 #include "tablet_mode.h"
 #include "task.h"
-#include "tcpm.h"
+#include "tcpm/tcpm.h"
 #include "timer.h"
 #include "usb_charge.h"
 #include "usb_mux.h"
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
 	schedule_deferred_pd_interrupt(0 /* port */);
 }
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /******************************************************************************/
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] =  {"BOARD_ID",  3300, 4096, 0, STM32_AIN(10)},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)},
+	[ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(10) },
+	[ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /******************************************************************************/
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{"typec", 0, 400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"other", 1, 100, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
+	{ .name = "typec",
+	  .port = 0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "other",
+	  .port = 1,
+	  .kbps = 100,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
 const struct i2c_port_t i2c_bitbang_ports[] = {
-	{"battery", 2, 100, GPIO_I2C3_SCL, GPIO_I2C3_SDA, .drv = &bitbang_drv},
+	{ .name = "battery",
+	  .port = 2,
+	  .kbps = 100,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA,
+	  .drv = &bitbang_drv },
 };
 const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
 
@@ -81,13 +98,13 @@ const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
 
 /* power signal list.  Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
+	{ GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" },
+	{ GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" },
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
 /* Keyboard scan setting */
-struct keyboard_scan_config keyscan_config = {
+__override struct keyboard_scan_config keyscan_config = {
 	/*
 	 * TODO(b/133200075): Tune this once we have the final performance
 	 * out of the driver and the i2c bus.
@@ -106,8 +123,8 @@ struct keyboard_scan_config keyscan_config = {
 
 struct ioexpander_config_t ioex_config[CONFIG_IO_EXPANDER_PORT_COUNT] = {
 	[0] = {
-		.i2c_host_port = I2C_PORT_IO_EXPANDER_IT8801,
-		.i2c_slave_addr = IT8801_I2C_ADDR,
+		.i2c_host_port = I2C_PORT_KB_DISCRETE,
+		.i2c_addr_flags = IT8801_I2C_ADDR1,
 		.drv = &it8801_ioexpander_drv,
 	},
 };
@@ -132,15 +149,18 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = I2C_PORT_TCPC0,
-			.addr_flags = FUSB302_I2C_SLAVE_ADDR_FLAGS,
+			.addr_flags = FUSB302_I2C_ADDR_FLAGS,
 		},
 		.drv = &fusb302_tcpm_drv,
 	},
 };
 
-static void board_hpd_status(const struct usb_mux *me,
-			     int hpd_lvl, int hpd_irq)
+static void board_hpd_status(const struct usb_mux *me, mux_state_t mux_state,
+			     bool *ack_required)
 {
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
 	/*
 	 * svdm_dp_attention() did most of the work, we only need to notify
 	 * host here.
@@ -148,13 +168,16 @@ static void board_hpd_status(const struct usb_mux *me,
 	host_set_single_event(EC_HOST_EVENT_USB_MUX);
 }
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+				.hpd_update = &board_hpd_status,
+			},
 	},
 };
 
@@ -184,7 +207,7 @@ int board_set_active_charge_port(int charge_port)
 		if (board_vbus_source_enabled(charge_port))
 			return -1;
 		break;
-	case CHARGE_PORT_NONE:
+	default:
 		/*
 		 * To ensure the fuel gauge (max17055) is always powered
 		 * even when battery is disconnected, keep VBAT rail on but
@@ -192,22 +215,11 @@ int board_set_active_charge_port(int charge_port)
 		 */
 		charger_set_current(CHARGER_SOLO, 0);
 		break;
-	default:
-		panic("Invalid charge port\n");
-		break;
 	}
 
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-			       CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
-
 int board_discharge_on_ac(int enable)
 {
 	int ret, port;
@@ -237,7 +249,7 @@ int pd_snk_is_vbus_provided(int port)
 
 void bc12_interrupt(enum gpio_signal signal)
 {
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
 }
 
 /*
@@ -270,13 +282,12 @@ static void board_spi_enable(void)
 	STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
 
 	/* Reinitialize spi peripheral. */
-	spi_enable(CONFIG_SPI_ACCEL_PORT, 1);
+	spi_enable(&spi_devices[0], 1);
 
 	/* Pin mux spi peripheral toward the sensor. */
-	gpio_config_module(MODULE_SPI_MASTER, 1);
+	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
 }
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP,
-	     board_spi_enable,
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_spi_enable,
 	     MOTION_SENSE_HOOK_PRIO - 1);
 
 static void board_spi_disable(void)
@@ -284,14 +295,15 @@ static void board_spi_disable(void)
 	/* Set pins to a state calming the sensor down. */
 	gpio_set_flags(GPIO_EC_SENSOR_SPI_CK, GPIO_OUT_LOW);
 	gpio_set_level(GPIO_EC_SENSOR_SPI_CK, 0);
-	gpio_config_module(MODULE_SPI_MASTER, 0);
+	gpio_set_flags(GPIO_EC_SENSOR_SPI_NSS, GPIO_OUT_LOW);
+	gpio_set_level(GPIO_EC_SENSOR_SPI_NSS, 0);
+	gpio_config_module(MODULE_SPI_CONTROLLER, 0);
 
 	/* Disable spi peripheral and clocks. */
-	spi_enable(CONFIG_SPI_ACCEL_PORT, 0);
+	spi_enable(&spi_devices[0], 0);
 	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
 }
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN,
-	     board_spi_disable,
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_spi_disable,
 	     MOTION_SENSE_HOOK_PRIO + 1);
 #endif /* !VARIANT_KUKUI_NO_SENSORS */
 
@@ -302,21 +314,90 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Rotation matrixes */
-static const mat33_fp_t lid_standard_ref = {
-	{FLOAT_TO_FP(1), 0, 0},
-	{0, FLOAT_TO_FP(-1), 0},
-	{0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
-static const mat33_fp_t base_standard_ref = {
-	{FLOAT_TO_FP(-1), 0, 0},
-	{0, FLOAT_TO_FP(1), 0},
-	{0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t base_bmi160_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					    { 0, FLOAT_TO_FP(1), 0 },
+					    { 0, 0, FLOAT_TO_FP(-1) } };
+
+static const mat33_fp_t base_icm42607_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+					      { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
 
 /* sensor private data */
 static struct accelgyro_saved_data_t g_bma253_data;
+static struct kionix_accel_data g_kx022_data;
 static struct bmi_drv_data_t g_bmi160_data;
+static struct icm_drv_data_t g_icm42607_data;
+
+struct motion_sensor_t lid_accel_kx022 = {
+	.name = "Lid Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_KX022,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_LID,
+	.drv = &kionix_accel_drv,
+	.mutex = &g_lid_mutex,
+	.drv_data = &g_kx022_data,
+	.port = I2C_PORT_SENSORS,
+	.i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
+	.rot_standard_ref = &lid_standard_ref,
+	.default_range = 2,
+	.config = {
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	},
+};
+
+struct motion_sensor_t base_accel_icm42607 = {
+	.name = "Base Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM42607,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm42607_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm42607_data,
+	.port = CONFIG_SPI_ACCEL_PORT,
+	.i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
+	.default_range = 4,
+	.rot_standard_ref = &base_icm42607_ref,
+	.min_frequency = ICM42607_ACCEL_MIN_FREQ,
+	.max_frequency = ICM42607_ACCEL_MAX_FREQ,
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	},
+};
+
+struct motion_sensor_t base_gyro_icm42607 = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM42607,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm42607_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm42607_data,
+	.port = CONFIG_SPI_ACCEL_PORT,
+	.i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &base_icm42607_ref,
+	.min_frequency = ICM42607_GYRO_MIN_FREQ,
+	.max_frequency = ICM42607_GYRO_MAX_FREQ,
+};
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
@@ -358,9 +439,10 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_base_mutex,
 		.drv_data = &g_bmi160_data,
 		.port = CONFIG_SPI_ACCEL_PORT,
-		.i2c_spi_addr_flags = SLAVE_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
-		.rot_standard_ref = &base_standard_ref,
-		.default_range = 2,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
+		.i2c_spi_addr_flags =
+				ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
+		.rot_standard_ref = &base_bmi160_ref,
+		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
 		.min_frequency = BMI_ACCEL_MIN_FREQ,
 		.max_frequency = BMI_ACCEL_MAX_FREQ,
 		.config = {
@@ -386,15 +468,52 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_base_mutex,
 		.drv_data = &g_bmi160_data,
 		.port = CONFIG_SPI_ACCEL_PORT,
-		.i2c_spi_addr_flags = SLAVE_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
+		.i2c_spi_addr_flags =
+				ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
 		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_standard_ref,
+		.rot_standard_ref = &base_bmi160_ref,
 		.min_frequency = BMI_GYRO_MIN_FREQ,
 		.max_frequency = BMI_GYRO_MAX_FREQ,
 	},
 };
 unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
+void sensor_interrupt(enum gpio_signal signal)
+{
+	switch (motion_sensors[BASE_ACCEL].chip) {
+	case MOTIONSENSE_CHIP_ICM42607:
+		icm42607_interrupt(signal);
+		break;
+	case MOTIONSENSE_CHIP_BMI160:
+	default:
+		bmi160_interrupt(signal);
+		break;
+	}
+}
+
+static void board_update_config(void)
+{
+	int val;
+	enum ec_error_list rv;
+
+	/* Ping for ack */
+	rv = i2c_read8(I2C_PORT_SENSORS, KX022_ADDR1_FLAGS, KX022_WHOAMI, &val);
+
+	if (rv == EC_SUCCESS)
+		motion_sensors[LID_ACCEL] = lid_accel_kx022;
+
+	/* Read icm-42607 chip content */
+	rv = icm_read8(&base_accel_icm42607, ICM42607_REG_WHO_AM_I, &val);
+
+	if (rv == EC_SUCCESS && val == ICM42607_CHIP_ICM42607P) {
+		motion_sensors[BASE_ACCEL] = base_accel_icm42607;
+		motion_sensors[BASE_GYRO] = base_gyro_icm42607;
+	}
+
+	CPRINTS("Lid Accel Chip: %d", motion_sensors[LID_ACCEL].chip);
+	CPRINTS("Base Accel Chip: %d", motion_sensors[BASE_ACCEL].chip);
+}
+
 #endif /* !VARIANT_KUKUI_NO_SENSORS */
 
 static void board_init(void)
@@ -414,13 +533,18 @@ static void board_init(void)
 		motion_sensor_count = ARRAY_SIZE(motion_sensors);
 		/* Enable interrupts from BMI160 sensor. */
 		gpio_enable_interrupt(GPIO_ACCEL_INT_ODL);
-		/* For some reason we have to do this again in case of sysjump */
+		/* For some reason we have to do this again in case of sysjump
+		 */
 		board_spi_enable();
+		board_update_config();
 	} else {
 		motion_sensor_count = 0;
+		/* Device is clamshell only */
+		tablet_set_mode(0, TABLET_TRIGGER_LID);
+		/* Turn off GMR interrupt */
+		gmr_tablet_switch_disable();
 		/* Base accel is not stuffed, don't allow line to float */
-		gpio_set_flags(GPIO_ACCEL_INT_ODL,
-			       GPIO_INPUT | GPIO_PULL_DOWN);
+		gpio_set_flags(GPIO_ACCEL_INT_ODL, GPIO_INPUT | GPIO_PULL_DOWN);
 		board_spi_disable();
 	}
 #endif /* !VARIANT_KUKUI_NO_SENSORS */
@@ -446,25 +570,3 @@ static void board_chipset_shutdown(void)
 	gpio_set_level(GPIO_EN_USBA_5V, 0);
 }
 DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
-
-int battery_get_vendor_param(uint32_t param, uint32_t *value)
-{
-	int rv;
-	uint8_t data[16] = {};
-
-	/* only allow reading 0x70~0x7F, 16 byte data */
-	if (param < 0x70 || param >= 0x80)
-		return EC_ERROR_ACCESS_DENIED;
-
-	rv = sb_read_string(0x70, data, sizeof(data));
-	if (rv)
-		return rv;
-
-	*value = data[param - 0x70];
-	return EC_SUCCESS;
-}
-
-int battery_set_vendor_param(uint32_t param, uint32_t value)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
diff --git a/board/burnet/board.h b/board/burnet/board.h
index 898beb058b..6d6870da2b 100644
--- a/board/burnet/board.h
+++ b/board/burnet/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,9 +8,13 @@
 #ifndef __CROS_EC_BOARD_H
 #define __CROS_EC_BOARD_H
 
+/* Free up flash space. */
+#undef CONFIG_CMD_KEYBOARD
+
 #define VARIANT_KUKUI_JACUZZI
 #define VARIANT_KUKUI_BATTERY_SMART
 #define VARIANT_KUKUI_CHARGER_ISL9238
+#define VARIANT_KUKUI_EC_STM32F098
 
 #ifndef SECTION_IS_RW
 #define VARIANT_KUKUI_NO_SENSORS
@@ -23,8 +27,12 @@
 
 #define CONFIG_BATTERY_HW_PRESENT_CUSTOM
 #define CONFIG_BATTERY_VENDOR_PARAM
+#define CONFIG_BATTERY_V2
+#define CONFIG_BATTERY_COUNT 1
 
 #define CONFIG_CHARGER_PSYS
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 5
 
 #define CONFIG_BC12_DETECT_PI3USB9201
 
@@ -44,18 +52,26 @@
 
 #define CONFIG_USB_MUX_IT5205
 
+/* Disable verbose output in EC pd */
+#define CONFIG_CMD_PD_SRCCAPS_REDUCED_SIZE
+
 /* Motion Sensors */
 #ifndef VARIANT_KUKUI_NO_SENSORS
-#define CONFIG_ACCEL_BMA255		/* Lid accel */
-#define CONFIG_ACCELGYRO_BMI160		/* Base accel */
-#define CONFIG_ACCEL_INTERRUPTS
+#define CONFIG_ACCEL_BMA255 /* Lid accel */
+#define CONFIG_ACCEL_KX022
+#define CONFIG_ACCELGYRO_BMI160 /* Base accel */
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+/* ICM42607 Base accel/gyro */
+#define CONFIG_ACCELGYRO_ICM42607
+#define CONFIG_ACCELGYRO_ICM42607_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 #define CONFIG_ALS
 #define CONFIG_CMD_ACCEL_INFO
 #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
 
 #define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_UPDATE
 #define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
 #define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
 
@@ -64,25 +80,24 @@
 #endif /* VARIANT_KUKUI_NO_SENSORS */
 
 /* I2C ports */
-#define I2C_PORT_BC12               0
-#define I2C_PORT_TCPC0              0
-#define I2C_PORT_USB_MUX            0
-#define I2C_PORT_BATTERY            2
-#define I2C_PORT_CHARGER            1
-#define I2C_PORT_SENSORS            1
-#define I2C_PORT_IO_EXPANDER_IT8801 1
-#define I2C_PORT_VIRTUAL_BATTERY    I2C_PORT_BATTERY
+#define I2C_PORT_BC12 0
+#define I2C_PORT_TCPC0 0
+#define I2C_PORT_USB_MUX 0
+#define I2C_PORT_BATTERY 2
+#define I2C_PORT_CHARGER 1
+#define I2C_PORT_SENSORS 1
+#define I2C_PORT_KB_DISCRETE 1
+#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
+
+/* IT8801 I2C address */
+#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1
 
 /* Enable Accel over SPI */
-#define CONFIG_SPI_ACCEL_PORT    0  /* The first SPI master port (SPI2) */
+#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */
 
 #define CONFIG_KEYBOARD_PROTOCOL_MKBP
 #define CONFIG_MKBP_EVENT
 #define CONFIG_MKBP_USE_GPIO
-/* Define the MKBP events which are allowed to wakeup AP in S3. */
-#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \
-		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
 
 #ifndef __ASSEMBLER__
 
@@ -115,12 +130,15 @@ enum charge_port {
 };
 
 enum battery_type {
-	BATTERY_DANAPACK_ATL,
-	BATTERY_DANAPACK_COS,
+	BATTERY_DYNAPACK_ATL,
+	BATTERY_DYNAPACK_COS,
 	BATTERY_SIMPLO_COS,
 	BATTERY_SIMPLO_HIGHPOWER,
 	BATTERY_SAMSUNG_SDI,
 	BATTERY_COS,
+	BATTERY_DYNAPACK_COS_44WH,
+	BATTERY_DYNAPACK_ATL_44WH,
+	BATTERY_SIMPLO_HIGHPOWER_44WH,
 	BATTERY_TYPE_COUNT,
 };
 
@@ -135,13 +153,15 @@ void emmc_cmd_interrupt(enum gpio_signal signal);
 void bc12_interrupt(enum gpio_signal signal);
 void board_reset_pd_mcu(void);
 int board_get_version(void);
-int board_is_sourcing_vbus(int port);
 
 /* returns the i2c port number of charger */
 int board_get_charger_i2c(void);
 
 int board_is_convertible(void);
 
+/* Motion sensor interrupt */
+void sensor_interrupt(enum gpio_signal signal);
+
 #endif /* !__ASSEMBLER__ */
 
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/burnet/build.mk b/board/burnet/build.mk
index a6e1c010d7..f583684804 100644
--- a/board/burnet/build.mk
+++ b/board/burnet/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/burnet/ec.tasklist b/board/burnet/ec.tasklist
index c1330b86f8..fb131b8eb4 100644
--- a/board/burnet/ec.tasklist
+++ b/board/burnet/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/burnet/gpio.inc b/board/burnet/gpio.inc
index a08ef74c3c..9bb0aa73db 100644
--- a/board/burnet/gpio.inc
+++ b/board/burnet/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,7 +22,7 @@ GPIO_INT(PMIC_EC_RESETB,    PIN(B, 7),  GPIO_INT_BOTH | GPIO_PULL_DOWN,
 GPIO_INT(WARM_RESET_REQ,    PIN(A, 3),  GPIO_INT_RISING | GPIO_PULL_DOWN,
          chipset_reset_request_interrupt)
 GPIO_INT_RW(ACCEL_INT_ODL,  PIN(A, 4), GPIO_INT_FALLING | GPIO_SEL_1P8V | GPIO_PULL_UP,
-         bmi160_interrupt)
+         sensor_interrupt)
 GPIO_INT_RO(EMMC_CMD,       PIN(B, 15), GPIO_INT_FALLING,
          emmc_cmd_interrupt)
 GPIO_INT(SPI1_NSS,          PIN(A, 15), GPIO_INT_BOTH | GPIO_PULL_UP,
@@ -116,5 +116,5 @@ ALTERNATE(PIN_MASK(A, 0x8000), 0, MODULE_SPI,        0)
 /* EMMC SPI SLAVE: PB13/14/15 */
 ALTERNATE(PIN_MASK(B, 0xE000), 0, MODULE_SPI_FLASH,  0)
 /* SENSORS SPI MASTER: PB10, PB12, PC2, PC3 */
-ALTERNATE(PIN_MASK(B, 0x0400), 5, MODULE_SPI_MASTER, 0)
-ALTERNATE(PIN_MASK(C, 0x000C), 1, MODULE_SPI_MASTER, 0)
+ALTERNATE(PIN_MASK(B, 0x0400), 5, MODULE_SPI_CONTROLLER, 0)
+ALTERNATE(PIN_MASK(C, 0x000C), 1, MODULE_SPI_CONTROLLER, 0)
diff --git a/board/burnet/led.c b/board/burnet/led.c
index 1f2b75325c..97e30f24be 100644
--- a/board/burnet/led.c
+++ b/board/burnet/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -17,10 +17,8 @@
 #define POWER_LED_ON 0
 #define POWER_LED_OFF 1
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -28,7 +26,7 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static int led_set_color_battery(enum led_color color)
@@ -52,7 +50,7 @@ static int led_set_color_battery(enum led_color color)
 	return EC_SUCCESS;
 }
 
-static int led_set_color_power(enum ec_led_colors color)
+static int led_set_color_power(enum led_color color)
 {
 	switch (color) {
 	case LED_OFF:
@@ -111,8 +109,7 @@ static void led_set_power(void)
 	if (chipset_in_state(CHIPSET_STATE_ON))
 		led_set_color_power(LED_WHITE);
 	else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-		led_set_color_power(
-			(power_tick & 0x2) ? LED_WHITE : LED_OFF);
+		led_set_color_power((power_tick & 0x2) ? LED_WHITE : LED_OFF);
 	else
 		led_set_color_power(LED_OFF);
 }
@@ -121,7 +118,6 @@ static void led_set_battery(void)
 {
 	static int battery_ticks;
 	static int power_ticks;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
@@ -132,27 +128,27 @@ static void led_set_battery(void)
 	 */
 	if (!board_is_convertible()) {
 		if (chipset_in_state(CHIPSET_STATE_SUSPEND |
-					 CHIPSET_STATE_STANDBY) &&
-			charge_get_state() != PWR_STATE_CHARGE) {
-			led_set_color_battery(power_ticks++ & 0x2 ?
-						  LED_WHITE : LED_OFF);
+				     CHIPSET_STATE_STANDBY) &&
+		    led_pwr_get_state() != LED_PWRS_CHARGE) {
+			led_set_color_battery(power_ticks++ & 0x2 ? LED_WHITE :
+								    LED_OFF);
 			return;
 		}
 	}
 
 	power_ticks = 0;
 
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
 		led_set_color_battery(LED_AMBER);
 		break;
-	case PWR_STATE_DISCHARGE_FULL:
+	case LED_PWRS_DISCHARGE_FULL:
 		if (extpower_is_present()) {
 			led_set_color_battery(LED_WHITE);
 			break;
 		}
-		/* Intentional fall-through */
-	case PWR_STATE_DISCHARGE:
+		__fallthrough;
+	case LED_PWRS_DISCHARGE:
 		/*
 		 * Blink white light (1 sec on, 1 sec off)
 		 * when battery capacity is less than 10%
@@ -163,19 +159,19 @@ static void led_set_battery(void)
 		else
 			led_set_color_battery(LED_OFF);
 		break;
-	case PWR_STATE_ERROR:
-		led_set_color_battery(
-			(battery_ticks % 0x2) ? LED_WHITE : LED_OFF);
+	case LED_PWRS_ERROR:
+		led_set_color_battery((battery_ticks % 0x2) ? LED_WHITE :
+							      LED_OFF);
 		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
+	case LED_PWRS_CHARGE_NEAR_FULL:
 		led_set_color_battery(LED_WHITE);
 		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			led_set_color_battery(
-				(battery_ticks & 0x2) ? LED_AMBER : LED_OFF);
-		else
-			led_set_color_battery(LED_WHITE);
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		led_set_color_battery(LED_WHITE);
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		led_set_color_battery((battery_ticks & 0x2) ? LED_AMBER :
+							      LED_OFF);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
diff --git a/board/burnet/vif_override.xml b/board/burnet/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/burnet/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/c2d2/OWNERS b/board/c2d2/OWNERS
new file mode 100644
index 0000000000..e4d6123372
--- /dev/null
+++ b/board/c2d2/OWNERS
@@ -0,0 +1,3 @@
+bnemec@google.com
+jettrink@chromium.org
+matthewb@chromium.org
diff --git a/board/c2d2/board.c b/board/c2d2/board.c
index 7e8af674c1..d8cf0f0e0a 100644
--- a/board/c2d2/board.c
+++ b/board/c2d2/board.c
@@ -1,10 +1,9 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 /* C2D2 debug device board configuration */
 
-#include "adc_chip.h"
 #include "adc.h"
 #include "common.h"
 #include "console.h"
@@ -20,19 +19,20 @@
 #include "task.h"
 #include "timer.h"
 #include "update_fw.h"
+#include "usart-stm32f0.h"
 #include "usart_rx_dma.h"
 #include "usart_tx_dma.h"
-#include "usart-stm32f0.h"
+#include "usb-stream.h"
 #include "usb_hw.h"
 #include "usb_i2c.h"
 #include "usb_spi.h"
-#include "usb-stream.h"
 #include "util.h"
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
 /* Forward declarations */
 static void update_vrefs_and_shifters(void);
@@ -42,19 +42,19 @@ static bool is_ec_i2c_enabled(void);
 /* Global state tracking current pin configuration and operations */
 static struct mutex vref_bus_state_mutex;
 static int vref_monitor_disable;
-#define VREF_MON_DIS_H1_RST_HELD	BIT(0)
-#define VREF_MON_DIS_EC_PWR_HELD	BIT(1)
-#define VREF_MON_DIS_SPI_MODE		BIT(2)
+#define VREF_MON_DIS_H1_RST_HELD BIT(0)
+#define VREF_MON_DIS_EC_PWR_HELD BIT(1)
+#define VREF_MON_DIS_SPI_MODE BIT(2)
 
 /*
  * Tracks if bus pins are locked by a function like UART holding, I2C,
  * or SPI.
  */
 enum bus_lock {
-	BUS_UNLOCKED,	/* Normal UART; pins available for other functions */
-	BUS_UART_HELD,	/* UART locked to pins while holding RX low */
-	BUS_SPI,	/* SPI locked to pins */
-	BUS_I2C,	/* I2C bus locked to pins */
+	BUS_UNLOCKED, /* Normal UART; pins available for other functions */
+	BUS_UART_HELD, /* UART locked to pins while holding RX low */
+	BUS_SPI, /* SPI locked to pins */
+	BUS_I2C, /* I2C bus locked to pins */
 };
 /* A0/A1 (H1 UART or SPI) */
 enum bus_lock h1_pins;
@@ -78,7 +78,7 @@ static const char *lock_to_string(const enum bus_lock val)
 	return names[val];
 }
 
-static int command_bus_status(int argc, char **argv)
+static int command_bus_status(int argc, const char **argv)
 {
 	if (argc > 1)
 		return EC_ERROR_PARAM_COUNT;
@@ -89,11 +89,9 @@ static int command_bus_status(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(bus_status, command_bus_status,
-			"",
+DECLARE_CONSOLE_COMMAND(bus_status, command_bus_status, "",
 			"Gets the bus state for swappable pins");
 
-
 /******************************************************************************
  ** Chip-specific board configuration
  */
@@ -115,12 +113,11 @@ void board_config_pre_init(void)
 	 *  i2c : no dma
 	 *  tim16/17: no dma
 	 */
-	STM32_SYSCFG_CFGR1 |= BIT(24);	/* Remap SPI2_RX to channel 6 */
-	STM32_SYSCFG_CFGR1 |= BIT(26);  /* Remap USART3 RX/TX DMA */
-	STM32_SYSCFG_CFGR1 |= BIT(10);  /* Remap USART1 RX/TX DMA */
+	STM32_SYSCFG_CFGR1 |= BIT(24); /* Remap SPI2_RX to channel 6 */
+	STM32_SYSCFG_CFGR1 |= BIT(26); /* Remap USART3 RX/TX DMA */
+	STM32_SYSCFG_CFGR1 |= BIT(10); /* Remap USART1 RX/TX DMA */
 }
 
-
 /******************************************************************************
  ** ADC channels
  */
@@ -148,17 +145,18 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
  * Define the strings used in our USB descriptors.
  */
 const void *const usb_strings[] = {
-	[USB_STR_DESC]			= usb_string_desc,
-	[USB_STR_VENDOR]		= USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]		= USB_STRING_DESC("C2D2"),
-	[USB_STR_SERIALNO]		= 0,
-	[USB_STR_VERSION]		= USB_STRING_DESC(CROS_EC_VERSION32),
-	[USB_STR_USART4_STREAM_NAME]	= USB_STRING_DESC("CR50"),
-	[USB_STR_UPDATE_NAME]		= USB_STRING_DESC("Firmware update"),
-	[USB_STR_CONSOLE_NAME]		= USB_STRING_DESC("C2D2 Shell"),
-	[USB_STR_I2C_NAME]		= USB_STRING_DESC("I2C"),
-	[USB_STR_USART3_STREAM_NAME]	= USB_STRING_DESC("CPU"),
-	[USB_STR_USART1_STREAM_NAME]	= USB_STRING_DESC("EC"),
+	[USB_STR_DESC] = usb_string_desc,
+	[USB_STR_VENDOR] = USB_STRING_DESC("Google LLC"),
+	[USB_STR_PRODUCT] = USB_STRING_DESC("C2D2"),
+	[USB_STR_SERIALNO] = 0,
+	[USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32),
+	[USB_STR_USART4_STREAM_NAME] = USB_STRING_DESC("CR50"),
+	[USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"),
+	[USB_STR_CONSOLE_NAME] = USB_STRING_DESC("C2D2 Shell"),
+	[USB_STR_SPI_NAME] = USB_STRING_DESC("SPI"),
+	[USB_STR_I2C_NAME] = USB_STRING_DESC("I2C"),
+	[USB_STR_USART3_STREAM_NAME] = USB_STRING_DESC("CPU"),
+	[USB_STR_USART1_STREAM_NAME] = USB_STRING_DESC("EC"),
 };
 
 BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
@@ -174,7 +172,7 @@ const struct i2c_port_t i2c_ports[] = {
 		.port = I2C_PORT_EC,
 		.kbps = 100,
 		.scl = GPIO_UART_DBG_TX_EC_RX_SCL,
-		.sda =  GPIO_UART_EC_TX_DBG_RX_SDA,
+		.sda = GPIO_UART_EC_TX_DBG_RX_SDA,
 		.flags = I2C_PORT_FLAG_DYNAMIC_SPEED,
 	},
 	{
@@ -182,7 +180,7 @@ const struct i2c_port_t i2c_ports[] = {
 		.port = I2C_PORT_AUX,
 		.kbps = 100,
 		.scl = GPIO_UART_DBG_TX_AP_RX_INA_SCL,
-		.sda =  GPIO_UART_AP_TX_DBG_RX_INA_SDA,
+		.sda = GPIO_UART_AP_TX_DBG_RX_INA_SDA,
 		.flags = I2C_PORT_FLAG_DYNAMIC_SPEED,
 	},
 };
@@ -203,14 +201,19 @@ const struct ite_dfu_config_t ite_dfu_config = {
  * let the i2c transactions fail instead of using the USB endpoint disable
  * status.
  */
-int usb_i2c_board_is_enabled(void) { return 1; }
+int usb_i2c_board_is_enabled(void)
+{
+	return 1;
+}
 
 /******************************************************************************
  * Forward UARTs as a USB serial interface.
  */
 
-#define USB_STREAM_RX_SIZE	32
-#define USB_STREAM_TX_SIZE	64
+#define USB_STREAM_RX_SIZE 32
+#define USB_STREAM_TX_SIZE 64
+#define USART_TO_USB_SIZE 1024
+#define USB_TO_USART_SIZE 64
 
 /******************************************************************************
  * Forward USART1 (EC) as a simple USB serial interface.
@@ -219,33 +222,22 @@ int usb_i2c_board_is_enabled(void) { return 1; }
 static struct usart_config const usart1;
 struct usb_stream_config const usart1_usb;
 
-static struct queue const usart1_to_usb = QUEUE_DIRECT(128, uint8_t,
-	usart1.producer, usart1_usb.consumer);
-static struct queue const usb_to_usart1 = QUEUE_DIRECT(64, uint8_t,
-	usart1_usb.producer, usart1.consumer);
+static struct queue const usart1_to_usb = QUEUE_DIRECT(
+	USART_TO_USB_SIZE, uint8_t, usart1.producer, usart1_usb.consumer);
+static struct queue const usb_to_usart1 = QUEUE_DIRECT(
+	USB_TO_USART_SIZE, uint8_t, usart1_usb.producer, usart1.consumer);
 
 static struct usart_rx_dma const usart1_rx_dma =
 	USART_RX_DMA(STM32_DMAC_CH5, 32);
 
 static struct usart_config const usart1 =
-	USART_CONFIG(usart1_hw,
-		usart1_rx_dma.usart_rx,
-		usart_tx_interrupt,
-		115200,
-		0,
-		usart1_to_usb,
-		usb_to_usart1);
-
-USB_STREAM_CONFIG_USART_IFACE(usart1_usb,
-	USB_IFACE_USART1_STREAM,
-	USB_STR_USART1_STREAM_NAME,
-	USB_EP_USART1_STREAM,
-	USB_STREAM_RX_SIZE,
-	USB_STREAM_TX_SIZE,
-	usb_to_usart1,
-	usart1_to_usb,
-	usart1)
+	USART_CONFIG(usart1_hw, usart1_rx_dma.usart_rx, usart_tx_interrupt,
+		     115200, 0, usart1_to_usb, usb_to_usart1);
 
+USB_STREAM_CONFIG_USART_IFACE(usart1_usb, USB_IFACE_USART1_STREAM,
+			      USB_STR_USART1_STREAM_NAME, USB_EP_USART1_STREAM,
+			      USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE,
+			      usb_to_usart1, usart1_to_usb, usart1)
 
 /******************************************************************************
  * Forward USART3 (CPU) as a simple USB serial interface.
@@ -254,33 +246,22 @@ USB_STREAM_CONFIG_USART_IFACE(usart1_usb,
 static struct usart_config const usart3;
 struct usb_stream_config const usart3_usb;
 
-static struct queue const usart3_to_usb = QUEUE_DIRECT(1024, uint8_t,
-	usart3.producer, usart3_usb.consumer);
-static struct queue const usb_to_usart3 = QUEUE_DIRECT(64, uint8_t,
-	usart3_usb.producer, usart3.consumer);
+static struct queue const usart3_to_usb = QUEUE_DIRECT(
+	USART_TO_USB_SIZE, uint8_t, usart3.producer, usart3_usb.consumer);
+static struct queue const usb_to_usart3 = QUEUE_DIRECT(
+	USB_TO_USART_SIZE, uint8_t, usart3_usb.producer, usart3.consumer);
 
 static struct usart_rx_dma const usart3_rx_dma =
 	USART_RX_DMA(STM32_DMAC_CH3, 32);
 
 static struct usart_config const usart3 =
-	USART_CONFIG(usart3_hw,
-		usart3_rx_dma.usart_rx,
-		usart_tx_interrupt,
-		115200,
-		0,
-		usart3_to_usb,
-		usb_to_usart3);
-
-USB_STREAM_CONFIG_USART_IFACE(usart3_usb,
-	USB_IFACE_USART3_STREAM,
-	USB_STR_USART3_STREAM_NAME,
-	USB_EP_USART3_STREAM,
-	USB_STREAM_RX_SIZE,
-	USB_STREAM_TX_SIZE,
-	usb_to_usart3,
-	usart3_to_usb,
-	usart3)
+	USART_CONFIG(usart3_hw, usart3_rx_dma.usart_rx, usart_tx_interrupt,
+		     115200, 0, usart3_to_usb, usb_to_usart3);
 
+USB_STREAM_CONFIG_USART_IFACE(usart3_usb, USB_IFACE_USART3_STREAM,
+			      USB_STR_USART3_STREAM_NAME, USB_EP_USART3_STREAM,
+			      USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE,
+			      usb_to_usart3, usart3_to_usb, usart3)
 
 /******************************************************************************
  * Forward USART4 (cr50) as a simple USB serial interface.
@@ -291,29 +272,19 @@ USB_STREAM_CONFIG_USART_IFACE(usart3_usb,
 static struct usart_config const usart4;
 struct usb_stream_config const usart4_usb;
 
-static struct queue const usart4_to_usb = QUEUE_DIRECT(1024, uint8_t,
-	usart4.producer, usart4_usb.consumer);
-static struct queue const usb_to_usart4 = QUEUE_DIRECT(64, uint8_t,
-	usart4_usb.producer, usart4.consumer);
+static struct queue const usart4_to_usb = QUEUE_DIRECT(
+	USART_TO_USB_SIZE, uint8_t, usart4.producer, usart4_usb.consumer);
+static struct queue const usb_to_usart4 = QUEUE_DIRECT(
+	USB_TO_USART_SIZE, uint8_t, usart4_usb.producer, usart4.consumer);
 
 static struct usart_config const usart4 =
-	USART_CONFIG(usart4_hw,
-		usart_rx_interrupt,
-		usart_tx_interrupt,
-		115200,
-		0,
-		usart4_to_usb,
-		usb_to_usart4);
-
-USB_STREAM_CONFIG_USART_IFACE(usart4_usb,
-	USB_IFACE_USART4_STREAM,
-	USB_STR_USART4_STREAM_NAME,
-	USB_EP_USART4_STREAM,
-	USB_STREAM_RX_SIZE,
-	USB_STREAM_TX_SIZE,
-	usb_to_usart4,
-	usart4_to_usb,
-	usart4)
+	USART_CONFIG(usart4_hw, usart_rx_interrupt, usart_tx_interrupt, 115200,
+		     0, usart4_to_usb, usb_to_usart4);
+
+USB_STREAM_CONFIG_USART_IFACE(usart4_usb, USB_IFACE_USART4_STREAM,
+			      USB_STR_USART4_STREAM_NAME, USB_EP_USART4_STREAM,
+			      USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE,
+			      usb_to_usart4, usart4_to_usb, usart4)
 
 /******************************************************************************
  * Set up SPI over USB
@@ -322,11 +293,11 @@ USB_STREAM_CONFIG_USART_IFACE(usart4_usb,
 
 /* SPI devices */
 const struct spi_device_t spi_devices[] = {
-	{ CONFIG_SPI_FLASH_PORT, 1, GPIO_SPI_CSN},
+	{ CONFIG_SPI_FLASH_PORT, 1, GPIO_SPI_CSN, USB_SPI_ENABLED },
 };
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
-void usb_spi_board_enable(struct usb_spi_config const *config)
+void usb_spi_board_enable(void)
 {
 	/* Configure SPI GPIOs */
 	gpio_config_module(MODULE_SPI_FLASH, 1);
@@ -341,12 +312,12 @@ void usb_spi_board_enable(struct usb_spi_config const *config)
 	STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2;
 	STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
 
-	spi_enable(CONFIG_SPI_FLASH_PORT, 1);
+	spi_enable(&spi_devices[0], 1);
 }
 
-void usb_spi_board_disable(struct usb_spi_config const *config)
+void usb_spi_board_disable(void)
 {
-	spi_enable(CONFIG_SPI_FLASH_PORT, 0);
+	spi_enable(&spi_devices[0], 0);
 
 	/* Disable clocks to SPI2 module */
 	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
@@ -358,13 +329,10 @@ void usb_spi_board_disable(struct usb_spi_config const *config)
 	STM32_GPIO_OSPEEDR(GPIO_B) &= ~0xff000000;
 }
 
-USB_SPI_CONFIG(usb_spi, USB_IFACE_SPI, USB_EP_SPI,
-	       USB_SPI_CONFIG_FLAGS_IGNORE_HOST_SIDE_ENABLE);
-
 /******************************************************************************
  * Check parity setting on usarts.
  */
-static int command_uart_parity(int argc, char **argv)
+static int command_uart_parity(int argc, const char **argv)
 {
 	int parity = 0, newparity;
 	struct usart_config const *usart;
@@ -398,14 +366,13 @@ static int command_uart_parity(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(parity, command_uart_parity,
-			"usart[2|3|4] [0|1|2]",
+DECLARE_CONSOLE_COMMAND(parity, command_uart_parity, "usart[2|3|4] [0|1|2]",
 			"Set parity on uart");
 
 /******************************************************************************
  * Set baud rate setting on usarts.
  */
-static int command_uart_baud(int argc, char **argv)
+static int command_uart_baud(int argc, const char **argv)
 {
 	int baud = 0;
 	struct usart_config const *usart;
@@ -431,14 +398,13 @@ static int command_uart_baud(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(baud, command_uart_baud,
-			"usart[2|3|4] rate",
+DECLARE_CONSOLE_COMMAND(baud, command_uart_baud, "usart[2|3|4] rate",
 			"Set baud rate on uart");
 
 /******************************************************************************
  * Hold the usart pins low while disabling it, or return it to normal.
  */
-static int command_hold_usart_low(int argc, char **argv)
+static int command_hold_usart_low(int argc, const char **argv)
 {
 	enum bus_lock *bus;
 	enum gpio_signal rx;
@@ -501,7 +467,7 @@ static int command_hold_usart_low(int argc, char **argv)
 
 	/* Print status for get and set case. */
 	ccprintf("USART status: %s\n",
-			*bus == BUS_UART_HELD ? "held low" : "normal");
+		 *bus == BUS_UART_HELD ? "held low" : "normal");
 
 	return EC_SUCCESS;
 
@@ -513,7 +479,6 @@ DECLARE_CONSOLE_COMMAND(hold_usart_low, command_hold_usart_low,
 			"usart[1|3|4] [0|1]?",
 			"Get/set the hold-low state for usart port");
 
-
 /******************************************************************************
  * Console commands SPI programming
  */
@@ -523,7 +488,7 @@ enum vref {
 	PP3300 = 3300,
 };
 
-static int command_enable_spi(int argc, char **argv)
+static int command_enable_spi(int argc, const char **argv)
 {
 	static enum vref current_spi_vref_state;
 
@@ -563,7 +528,7 @@ static int command_enable_spi(int argc, char **argv)
 			gpio_set_level(GPIO_EN_CLK_CSN_EC_UART, 0);
 
 			/* Disable SPI. Sets SPI pins to inputs. */
-			usb_spi_enable(&usb_spi, 0);
+			usb_spi_enable(0);
 
 			/* Set default state for chip select */
 			gpio_set_flags(GPIO_SPI_CSN, GPIO_INPUT);
@@ -616,7 +581,7 @@ static int command_enable_spi(int argc, char **argv)
 			gpio_set_flags(GPIO_SPI_CSN, GPIO_OUT_HIGH);
 
 			/* Enable SPI. Sets SPI pins to SPI alternate mode. */
-			usb_spi_enable(&usb_spi, 1);
+			usb_spi_enable(1);
 
 			/* Set requested Vref voltage */
 			gpio_set_level(GPIO_SEL_SPIVREF_H1VREF_3V3,
@@ -650,8 +615,7 @@ static int command_enable_spi(int argc, char **argv)
 	mutex_unlock(&vref_bus_state_mutex);
 	return EC_ERROR_BUSY;
 }
-DECLARE_CONSOLE_COMMAND(enable_spi, command_enable_spi,
-			"[0|1800|3300]?",
+DECLARE_CONSOLE_COMMAND(enable_spi, command_enable_spi, "[0|1800|3300]?",
 			"Get/set the SPI Vref");
 
 /******************************************************************************
@@ -686,7 +650,7 @@ static inline int to_kbps(enum i2c_freq freq)
 	}
 }
 
-static int command_enable_i2c(int argc, char **argv)
+static int command_enable_i2c(int argc, const char **argv)
 {
 	int i2c_index;
 	enum bus_lock *bus;
@@ -770,7 +734,7 @@ DECLARE_CONSOLE_COMMAND(enable_i2c, command_enable_i2c,
  * Console commands for asserting H1 reset and EC Power button
  */
 
-static int command_vref_alternate(int argc, char **argv,
+static int command_vref_alternate(int argc, const char **argv,
 				  const enum gpio_signal vref_signal,
 				  const enum gpio_signal en_signal,
 				  const int state_flag,
@@ -819,7 +783,6 @@ static int command_vref_alternate(int argc, char **argv,
 	ccprintf("%s held: %s\n", print_name,
 		 vref_monitor_disable & state_flag ? "yes" : "no");
 
-
 	return EC_SUCCESS;
 
 busy_error_unlock:
@@ -827,29 +790,47 @@ static int command_vref_alternate(int argc, char **argv,
 	return EC_ERROR_BUSY;
 }
 
-static int command_pwr_button(int argc, char **argv)
+static int command_pwr_button(int argc, const char **argv)
 {
 	return command_vref_alternate(argc, argv,
 				      GPIO_SPIVREF_HOLDN_ECVREF_H1_PWRBTN_ODL,
 				      GPIO_EN_SPIVREF_HOLDN_ECVREF_H1_PWRBTN,
 				      VREF_MON_DIS_EC_PWR_HELD, "Power button");
 }
-DECLARE_CONSOLE_COMMAND(pwr_button, command_pwr_button,
-			"[0|1]?",
+DECLARE_CONSOLE_COMMAND(pwr_button, command_pwr_button, "[0|1]?",
 			"Get/set the power button state");
 
-static int command_h1_reset(int argc, char **argv)
+static int command_h1_reset(int argc, const char **argv)
 {
+	if ((argc == 2) && !strncasecmp("pulse", argv[1], strlen(argv[1]))) {
+		int rv;
+		int c = 2;
+		const char *cmd_on[] = { "", "1", "" };
+		const char *cmd_off[] = { "", "0", "" };
+
+		rv = command_vref_alternate(c, cmd_on,
+					    GPIO_SPIVREF_RSVD_H1VREF_H1_RST_ODL,
+					    GPIO_EN_SPIVREF_RSVD_H1VREF_H1_RST,
+					    VREF_MON_DIS_H1_RST_HELD,
+					    "H1 reset");
+		if (rv == EC_SUCCESS) {
+			msleep(100);
+			rv = command_vref_alternate(
+				c, cmd_off, GPIO_SPIVREF_RSVD_H1VREF_H1_RST_ODL,
+				GPIO_EN_SPIVREF_RSVD_H1VREF_H1_RST,
+				VREF_MON_DIS_H1_RST_HELD, "H1 reset");
+		}
+		return rv;
+	}
+
 	return command_vref_alternate(argc, argv,
 				      GPIO_SPIVREF_RSVD_H1VREF_H1_RST_ODL,
 				      GPIO_EN_SPIVREF_RSVD_H1VREF_H1_RST,
 				      VREF_MON_DIS_H1_RST_HELD, "H1 reset");
 }
-DECLARE_CONSOLE_COMMAND(h1_reset, command_h1_reset,
-			"[0|1]?",
+DECLARE_CONSOLE_COMMAND(h1_reset, command_h1_reset, "[0|1|pulse]?",
 			"Get/set the h1 reset state");
 
-
 /******************************************************************************
  * Vref detection logic
  */
@@ -858,14 +839,13 @@ DECLARE_CONSOLE_COMMAND(h1_reset, command_h1_reset,
 static enum vref h1_vref;
 static enum vref ec_vref;
 
-static int command_h1_vref_present(int argc, char **argv)
+static int command_h1_vref_present(int argc, const char **argv)
 {
 	ccprintf("H1 Vref: %s\n", h1_vref ? "on" : "off");
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(h1_vref, command_h1_vref_present,
-			"",
+DECLARE_CONSOLE_COMMAND(h1_vref, command_h1_vref_present, "",
 			"Get if the h1 vref is present");
 
 /* Voltage thresholds for rail detection */
@@ -1011,11 +991,9 @@ static void update_vrefs_and_shifters(void)
 void set_up_comparator(void)
 {
 	/* Overwrite any previous values. This is the only comparator usage */
-	STM32_COMP_CSR = STM32_COMP_CMP2HYST_HI |
-			 STM32_COMP_CMP2OUTSEL_NONE |
+	STM32_COMP_CSR = STM32_COMP_CMP2HYST_HI | STM32_COMP_CMP2OUTSEL_NONE |
 			 STM32_COMP_CMP2INSEL_INM5 | /* Watch DAC_OUT2 (PA5) */
-			 STM32_COMP_CMP2MODE_LSPEED |
-			 STM32_COMP_CMP2EN;
+			 STM32_COMP_CMP2MODE_LSPEED | STM32_COMP_CMP2EN;
 
 	/* Set Falling and Rising interrupts for COMP2 */
 	STM32_EXTI_FTSR |= EXTI_COMP2_EVENT;
@@ -1091,6 +1069,6 @@ static void board_jump(void)
 	usart_shutdown(&usart4);
 
 	/* Ensure SPI2 is disabled as well */
-	usb_spi_enable(&usb_spi, 0);
+	usb_spi_enable(0);
 }
 DECLARE_HOOK(HOOK_SYSJUMP, board_jump, HOOK_PRIO_DEFAULT);
diff --git a/board/c2d2/board.h b/board/c2d2/board.h
index 2aa129ef25..dc9b8321a2 100644
--- a/board/c2d2/board.h
+++ b/board/c2d2/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,9 +21,9 @@
 
 /* Enable USART */
 #define CONFIG_STREAM_USART
-#define CONFIG_STREAM_USART1	/* EC USART */
-#define CONFIG_STREAM_USART3	/* AP USART - not connected by default */
-#define CONFIG_STREAM_USART4	/* H1 USART */
+#define CONFIG_STREAM_USART1 /* EC USART */
+#define CONFIG_STREAM_USART3 /* AP USART - not connected by default */
+#define CONFIG_STREAM_USART4 /* H1 USART */
 #define CONFIG_STREAM_USB
 #define CONFIG_CMD_USART_INFO
 
@@ -34,7 +34,6 @@
 #undef CONFIG_UART_RX_DMA
 
 /* Optional features */
-#define CONFIG_STM_HWTIMER32
 #define CONFIG_HW_CRC
 
 /* USB Configuration */
@@ -45,50 +44,50 @@
 #define DEFAULT_SERIALNO "Uninitialized"
 #define CONFIG_USB_UPDATE
 
-
 /* USB interface indexes (use define rather than enum to expand them)
  *
  * Note these values are used in servo_interface.py for the 'interface' value
  */
-#define USB_IFACE_USART4_STREAM	0	/* H1 */
-#define USB_IFACE_UPDATE	1
-#define USB_IFACE_SPI		2
-#define USB_IFACE_CONSOLE	3
-#define USB_IFACE_I2C		4
-#define USB_IFACE_USART3_STREAM	5	/* AP (not connected by default) */
-#define USB_IFACE_USART1_STREAM	6	/* EC */
-#define USB_IFACE_COUNT		7
+#define USB_IFACE_USART4_STREAM 0 /* H1 */
+#define USB_IFACE_UPDATE 1
+#define USB_IFACE_SPI 2
+#define USB_IFACE_CONSOLE 3
+#define USB_IFACE_I2C 4
+#define USB_IFACE_USART3_STREAM 5 /* AP (not connected by default) */
+#define USB_IFACE_USART1_STREAM 6 /* EC */
+#define USB_IFACE_COUNT 7
 
 /* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL		0
-#define USB_EP_USART4_STREAM	1
-#define USB_EP_UPDATE		2
-#define USB_EP_SPI		3
-#define USB_EP_CONSOLE		4
-#define USB_EP_I2C		5
-#define USB_EP_USART3_STREAM	6
-#define USB_EP_USART1_STREAM	7
-#define USB_EP_COUNT		8
+#define USB_EP_CONTROL 0
+#define USB_EP_USART4_STREAM 1
+#define USB_EP_UPDATE 2
+#define USB_EP_SPI 3
+#define USB_EP_CONSOLE 4
+#define USB_EP_I2C 5
+#define USB_EP_USART3_STREAM 6
+#define USB_EP_USART1_STREAM 7
+#define USB_EP_COUNT 8
 
 /* Enable control of SPI over USB */
 #define CONFIG_USB_SPI
-#define CONFIG_SPI_MASTER
-#define CONFIG_SPI_FLASH_PORT 0  /* SPI2 is 0th in stm's SPI_REGS var */
+#define CONFIG_USB_SPI_IGNORE_HOST_SIDE_ENABLE
+#define CONFIG_SPI_CONTROLLER
+#define CONFIG_SPI_FLASH_PORT 0 /* SPI2 is 0th in stm's SPI_REGS var */
 
 /* Enable control of I2C over USB */
 #define CONFIG_USB_I2C
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_CONTROLLER
 #define I2C_PORT_EC 0
 #define I2C_PORT_AUX 1
 
 /* See i2c_ite_flash_support.c for more information about these values */
 #define CONFIG_ITE_FLASH_SUPPORT
-#define CONFIG_I2C_XFER_LARGE_READ
+#define CONFIG_I2C_XFER_LARGE_TRANSFER
 #undef CONFIG_USB_I2C_MAX_WRITE_COUNT
 #undef CONFIG_USB_I2C_MAX_READ_COUNT
-#define CONFIG_USB_I2C_MAX_WRITE_COUNT ((1<<9) - 4)
-#define CONFIG_USB_I2C_MAX_READ_COUNT ((1<<9) - 6)
+#define CONFIG_USB_I2C_MAX_WRITE_COUNT ((1 << 9) - 4)
+#define CONFIG_USB_I2C_MAX_READ_COUNT ((1 << 9) - 6)
 
 /*
  * Set all ADC samples to take 239.5 clock cycles. This allows us to measure
@@ -114,7 +113,7 @@
 
 /* Timer selection */
 #define TIM_CLOCK32 2
-#define TIM_ADC     3
+#define TIM_ADC 3
 
 #include "gpio_signal.h"
 
@@ -128,6 +127,7 @@ enum usb_strings {
 	USB_STR_USART4_STREAM_NAME,
 	USB_STR_UPDATE_NAME,
 	USB_STR_CONSOLE_NAME,
+	USB_STR_SPI_NAME,
 	USB_STR_I2C_NAME,
 	USB_STR_USART3_STREAM_NAME,
 	USB_STR_USART1_STREAM_NAME,
diff --git a/board/c2d2/build.mk b/board/c2d2/build.mk
index 559b6b8e95..d5940c3885 100644
--- a/board/c2d2/build.mk
+++ b/board/c2d2/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/c2d2/ec.tasklist b/board/c2d2/ec.tasklist
index c1fb169118..c45a1e89a7 100644
--- a/board/c2d2/ec.tasklist
+++ b/board/c2d2/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/c2d2/gpio.inc b/board/c2d2/gpio.inc
index 485a603453..b100250f20 100644
--- a/board/c2d2/gpio.inc
+++ b/board/c2d2/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/cappy2/battery.c b/board/cappy2/battery.c
new file mode 100644
index 0000000000..19be1825eb
--- /dev/null
+++ b/board/cappy2/battery.c
@@ -0,0 +1,177 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+#include "battery.h"
+#include "battery_fuel_gauge.h"
+#include "battery_smart.h"
+#include "charge_state.h"
+#include "common.h"
+#include "util.h"
+
+#define CHARGING_VOLTAGE_MV_SAFE 8400
+#define CHARGING_CURRENT_MA_SAFE 1500
+
+/*
+ * Battery info for lalala battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	/* SDI Battery Information */
+	[BATTERY_SDI] = {
+		.fuel_gauge = {
+			.manuf_name = "SDI",
+			.device_name = "4402D51",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 0,
+				.reg_addr = 0x00,
+				.reg_mask = 0xc000,
+				.disconnect_val = 0x8000,
+				.cfet_mask = 0xc000,
+				.cfet_off_val = 0x2000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 8800,
+			.voltage_normal		= 7700, /* mV */
+			.voltage_min		= 6000, /* mV */
+			.precharge_current	= 200,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 70,
+		},
+	}
+};
+
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SDI;
+
+int charger_profile_override(struct charge_state_data *curr)
+{
+	int current;
+	int voltage;
+	/* battery temp in 0.1 deg C */
+	int bat_temp_c;
+	const struct battery_info *batt_info;
+
+	/*
+	 * Keep track of battery temperature range:
+	 *
+	 *     ZONE_0  ZONE_1   ZONE_2  ZONE_3
+	 * ---+------+--------+--------+------+--- Temperature (C)
+	 *    0      5        12       45     50
+	 */
+	enum {
+		TEMP_ZONE_0, /* 0 <= bat_temp_c <= 5 */
+		TEMP_ZONE_1, /* 5 < bat_temp_c <= 12 */
+		TEMP_ZONE_2, /* 12 < bat_temp_c <= 45 */
+		TEMP_ZONE_3, /* 45 < bat_temp_c <= 50 */
+		TEMP_ZONE_COUNT,
+		TEMP_OUT_OF_RANGE = TEMP_ZONE_COUNT
+	} temp_zone;
+
+	/*
+	 * Precharge must be executed when communication is failed on
+	 * dead battery.
+	 */
+	if (!(curr->batt.flags & BATT_FLAG_RESPONSIVE))
+		return 0;
+
+	current = curr->requested_current;
+	voltage = curr->requested_voltage;
+	bat_temp_c = curr->batt.temperature - 2731;
+	batt_info = battery_get_info();
+
+	/*
+	 * If the temperature reading is bad, assume the temperature
+	 * is out of allowable range.
+	 */
+	if ((curr->batt.flags & BATT_FLAG_BAD_TEMPERATURE) ||
+	    (bat_temp_c < 0) || (bat_temp_c > 500))
+		temp_zone = TEMP_OUT_OF_RANGE;
+	else if (bat_temp_c <= 50)
+		temp_zone = TEMP_ZONE_0;
+	else if (bat_temp_c <= 120)
+		temp_zone = TEMP_ZONE_1;
+	else if (bat_temp_c <= 450)
+		temp_zone = TEMP_ZONE_2;
+	else
+		temp_zone = TEMP_ZONE_3;
+
+	switch (temp_zone) {
+	case TEMP_ZONE_0:
+		voltage = CHARGING_VOLTAGE_MV_SAFE;
+		current = CHARGING_CURRENT_MA_SAFE;
+		break;
+
+	case TEMP_ZONE_1:
+		voltage += 100;
+		current = CHARGING_CURRENT_MA_SAFE;
+		break;
+
+	case TEMP_ZONE_2:
+		voltage += 100;
+		break;
+
+	case TEMP_ZONE_3:
+		voltage = CHARGING_VOLTAGE_MV_SAFE;
+		break;
+
+	case TEMP_OUT_OF_RANGE:
+		/* Don't charge if outside of allowable temperature range */
+		current = 0;
+		voltage = 0;
+		curr->batt.flags &= ~BATT_FLAG_WANT_CHARGE;
+		if (curr->state != ST_DISCHARGE)
+			curr->state = ST_IDLE;
+		break;
+	}
+
+	if (voltage > batt_info->voltage_max)
+		voltage = batt_info->voltage_max;
+
+	curr->requested_voltage = voltage;
+	curr->requested_current = MIN(curr->requested_current, current);
+
+	return 0;
+}
+
+enum ec_status charger_profile_override_get_param(uint32_t param,
+						  uint32_t *value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+enum ec_status charger_profile_override_set_param(uint32_t param,
+						  uint32_t value)
+{
+	return EC_RES_INVALID_PARAM;
+}
diff --git a/board/cappy2/board.c b/board/cappy2/board.c
new file mode 100644
index 0000000000..9525e9c1f2
--- /dev/null
+++ b/board/cappy2/board.c
@@ -0,0 +1,348 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* cappy2 board-specific configuration */
+
+#include "adc_chip.h"
+#include "button.h"
+#include "cbi_fw_config.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "driver/bc12/pi3usb9201.h"
+#include "driver/charger/isl923x.h"
+#include "driver/tcpm/raa489000.h"
+#include "driver/temp_sensor/thermistor.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "keyboard_raw.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "math_util.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "switch.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "tcpm/tcpci.h"
+#include "temp_sensor.h"
+#include "uart.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_mux/ps8743_public.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+#define INT_RECHECK_US 5000
+
+/* C0 interrupt line shared by BC 1.2 and charger */
+static void check_c0_line(void);
+DECLARE_DEFERRED(check_c0_line);
+
+static void notify_c0_chips(void)
+{
+	/*
+	 * The interrupt line is shared between the TCPC and BC 1.2 detection
+	 * chip.  Therefore we'll need to check both ICs.
+	 */
+	schedule_deferred_pd_interrupt(0);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+
+static void check_c0_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		notify_c0_chips();
+		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+	}
+}
+
+static void usb_c0_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c0_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c0_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+}
+
+static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
+{
+	cprints(CC_USBPD, "C0: CC OVP, SBU OVP, or thermal event");
+	pd_handle_cc_overvoltage(0);
+}
+
+/* Keyboard scan setting */
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_1] = {
+		.name = "TEMP_SENSOR1",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_2] = {
+		.name = "TEMP_SENSOR2",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_SUB_ANALOG] = {
+		.name = "SUB_ANALOG",
+		.input_ch = NPCX_ADC_CH2,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_3] = {
+		.name = "TEMP_SENSOR3",
+		.input_ch = NPCX_ADC_CH6,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_VSNS_PP3300_A] = {
+		.name = "PP3300_A_PGOOD",
+		.input_ch = NPCX_ADC_CH9,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+void board_hibernate(void)
+{
+	/*
+	 * Both charger ICs need to be put into their "low power mode" before
+	 * entering the Z-state.
+	 */
+	raa489000_hibernate(0, true);
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * TODO(b:147316511): Here we could issue a digital reset to the IC,
+	 * unsure if we actually want to do that or not yet.
+	 */
+}
+
+__override void board_power_5v_enable(int enable)
+{
+	/*
+	 * Port 0 simply has a GPIO to turn on the 5V regulator, however, 5V is
+	 * generated locally on the sub board and we need to set the comparator
+	 * polarity on the sub board charger IC.
+	 */
+	gpio_set_level(GPIO_EN_PP5000, !!enable);
+	gpio_set_level(GPIO_EN_USB_A0_VBUS, !!enable);
+}
+
+int board_is_sourcing_vbus(int port)
+{
+	int regval;
+
+	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
+	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int i;
+	int old_port;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	old_port = charge_manager_get_active_charge_port();
+
+	CPRINTS("New chg p%d", port);
+
+	/* Disable all ports. */
+	if (port == CHARGE_PORT_NONE) {
+		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
+			tcpc_write(i, TCPC_REG_COMMAND,
+				   TCPC_REG_COMMAND_SNK_CTRL_LOW);
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if port is sourcing VBUS. */
+	if (board_is_sourcing_vbus(port)) {
+		CPRINTS("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		if (i == port)
+			continue;
+
+		if (tcpc_write(i, TCPC_REG_COMMAND,
+			       TCPC_REG_COMMAND_SNK_CTRL_LOW))
+			CPRINTS("p%d: sink path disable failed.", i);
+	}
+
+	/*
+	 * Stop the charger IC from switching while changing ports.  Otherwise,
+	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
+	 */
+	if (old_port != CHARGE_PORT_NONE)
+		charger_discharge_on_ac(1);
+
+	/* Enable requested charge port. */
+	if (tcpc_write(port, TCPC_REG_COMMAND,
+		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
+		CPRINTS("p%d: sink path enable failed.", port);
+		charger_discharge_on_ac(0);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	/* Allow the charger IC to begin/continue switching. */
+	charger_discharge_on_ac(0);
+
+	return EC_SUCCESS;
+}
+
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	if (port < 0 || port > board_get_usb_pd_port_count())
+		return;
+
+	raa489000_set_output_current(port, rp);
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	return pd_check_vbus_level(port, VBUS_PRESENT);
+}
+
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+};
+
+/* BC 1.2 chip*/
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	{
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+		.flags = PI3USB9201_ALWAYS_POWERED,
+	},
+};
+
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0,
+			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
+		},
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+		.drv = &raa489000_tcpm_drv,
+	},
+};
+
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = PS8743_I2C_ADDR0_FLAG,
+				.driver = &ps8743_usb_mux_driver,
+			},
+	},
+};
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+	int regval;
+
+	/*
+	 * The interrupt line is shared between the TCPC and BC1.2 detector IC.
+	 * Therefore, go out and actually read the alert registers to report the
+	 * alert status.
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
+			if (regval)
+				status |= PD_STATUS_TCPC_ALERT_0;
+		}
+	}
+
+	return status;
+}
+
+void board_init(void)
+{
+	int on;
+
+	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
+
+	/*
+	 * If interrupt lines are already low, schedule them to be processed
+	 * after inits are completed.
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL))
+		hook_call_deferred(&check_c0_line_data, 0);
+
+	gpio_enable_interrupt(GPIO_USB_C0_CCSBU_OVP_ODL);
+
+	/* Turn on 5V if the system is on, otherwise turn it off. */
+	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
+			      CHIPSET_STATE_SOFT_OFF);
+	board_power_5v_enable(on);
+
+	/* modify AC DC prochot value */
+	isl923x_set_ac_prochot(CHARGER_SOLO, 4096);
+	isl923x_set_dc_prochot(CHARGER_SOLO, 6000);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+/* Thermistors */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "Cpu",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
diff --git a/board/cappy2/board.h b/board/cappy2/board.h
new file mode 100644
index 0000000000..d9b027eed9
--- /dev/null
+++ b/board/cappy2/board.h
@@ -0,0 +1,126 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* cappy2 board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#define VARIANT_KEEBY_EC_NPCX797FC
+#include "baseboard.h"
+
+#undef GPIO_VOLUME_UP_L
+#undef GPIO_VOLUME_DOWN_L
+#undef CONFIG_VOLUME_BUTTONS
+
+/* System unlocked in early development */
+#define CONFIG_SYSTEM_UNLOCKED
+
+/*
+ * The RAM and flash size combination on the the NPCX797FC does not leave
+ * any unused flash space that can be used to store the .init_rom section.
+ */
+#undef CONFIG_CHIP_INIT_ROM_REGION
+
+/* Battery */
+#define CONFIG_BATTERY_FUEL_GAUGE
+#define CONFIG_BATTERY_V2
+#define CONFIG_BATTERY_COUNT 1
+#define CONFIG_HOSTCMD_BATTERY_V2
+
+/* Charger */
+#define CONFIG_CHARGER_RAA489000
+#define PD_MAX_VOLTAGE_MV 20000
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SINGLE_CHIP
+#define CONFIG_CHARGER_PROFILE_OVERRIDE
+#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
+#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
+/*
+ * b/147463641: The charger IC seems to overdraw ~4%, therefore we
+ * reduce our target accordingly.
+ */
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 4
+
+/* Keyboard */
+#undef CONFIG_PWM_KBLIGHT
+
+/* LED defines */
+#define CONFIG_LED_COMMON
+#define CONFIG_LED_ONOFF_STATES
+#define GPIO_BAT_LED_RED_L GPIO_LED_R_ODL
+#define GPIO_BAT_LED_GREEN_L GPIO_LED_G_ODL
+#define GPIO_PWR_LED_BLUE_L GPIO_LED_B_ODL
+
+/* PWM */
+#define NPCX7_PWM1_SEL 0 /* GPIO C2 is used as PWM1. */
+
+/******************************************************************************/
+
+/* USB PD */
+#define CONFIG_USB_PD_PORT_MAX_COUNT 1
+#define CONFIG_USB_PD_TCPM_RAA489000
+
+/* USB defines specific to external TCPCs */
+#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+#define CONFIG_USB_PD_VBUS_DETECT_TCPC
+#define CONFIG_USB_PD_DISCHARGE_TCPC
+#define CONFIG_USB_PD_TCPC_LOW_POWER
+
+/* Variant references the TCPCs to determine Vbus sourcing */
+#define CONFIG_USB_PD_5V_EN_CUSTOM
+
+/* BC1.2 */
+#define CONFIG_BC12_DETECT_PI3USB9201
+
+/* MUX */
+#define CONFIG_USB_MUX_PS8743
+
+/* Thermistors */
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_THERMISTOR
+#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
+#define CONFIG_TEMP_SENSOR_POWER
+#define GPIO_TEMP_SENSOR_POWER GPIO_EN_PP3300_A
+
+/* I2C configuration */
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum adc_channel {
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
+	ADC_SUB_ANALOG, /* ADC2 */
+	ADC_TEMP_SENSOR_3, /* ADC6 */
+	ADC_VSNS_PP3300_A, /* ADC9 */
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1,
+	TEMP_SENSOR_2,
+	TEMP_SENSOR_3,
+	TEMP_SENSOR_COUNT
+};
+
+enum battery_type {
+	BATTERY_SDI,
+	BATTERY_TYPE_COUNT,
+};
+
+#endif /* !__ASSEMBLER__ */
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/cappy2/build.mk b/board/cappy2/build.mk
new file mode 100644
index 0000000000..eb422dae93
--- /dev/null
+++ b/board/cappy2/build.mk
@@ -0,0 +1,14 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx7
+CHIP_VARIANT:=npcx7m7fc
+BASEBOARD:=keeby
+
+board-y=board.o battery.o cbi_ssfc.o led.o usb_pd_policy.o
diff --git a/board/cappy2/cbi_ssfc.c b/board/cappy2/cbi_ssfc.c
new file mode 100644
index 0000000000..81f3ee0dad
--- /dev/null
+++ b/board/cappy2/cbi_ssfc.c
@@ -0,0 +1,36 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi_ssfc.h"
+#include "common.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "hooks.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+/* Cache SSFC on init since we don't expect it to change in runtime */
+static union dedede_cbi_ssfc cached_ssfc;
+BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
+
+static void cbi_ssfc_init(void)
+{
+	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
+		/* Default to 0 when CBI isn't populated */
+		cached_ssfc.raw_value = 0;
+
+	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
+}
+DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
+
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
+{
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
+}
+
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
+{
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
+}
diff --git a/board/cappy2/cbi_ssfc.h b/board/cappy2/cbi_ssfc.h
new file mode 100644
index 0000000000..bf8853a43a
--- /dev/null
+++ b/board/cappy2/cbi_ssfc.h
@@ -0,0 +1,59 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _DEDEDE_CBI_SSFC__H_
+#define _DEDEDE_CBI_SSFC__H_
+
+#include "stdint.h"
+
+/****************************************************************************
+ * Dedede CBI Second Source Factory Cache
+ */
+
+/*
+ * Base Sensor (Bits 0-2)
+ */
+enum ec_ssfc_base_sensor {
+	SSFC_SENSOR_BASE_DEFAULT = 0,
+	SSFC_SENSOR_BMI160 = 1,
+	SSFC_SENSOR_ICM426XX = 2,
+	SSFC_SENSOR_LSM6DSM = 3,
+	SSFC_SENSOR_ICM42607 = 4
+};
+
+/*
+ * Lid Sensor (Bits 3-5)
+ */
+enum ec_ssfc_lid_sensor {
+	SSFC_SENSOR_LID_DEFAULT = 0,
+	SSFC_SENSOR_BMA255 = 1,
+	SSFC_SENSOR_KX022 = 2,
+	SSFC_SENSOR_LIS2DWL = 3
+};
+
+union dedede_cbi_ssfc {
+	struct {
+		uint32_t base_sensor : 3;
+		uint32_t lid_sensor : 3;
+		uint32_t reserved_2 : 26;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Get the Base sensor type from SSFC_CONFIG.
+ *
+ * @return the Base sensor board type.
+ */
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
+
+/**
+ * Get the Lid sensor type from SSFC_CONFIG.
+ *
+ * @return the Lid sensor board type.
+ */
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
+
+#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/cappy2/ec.tasklist b/board/cappy2/ec.tasklist
new file mode 100644
index 0000000000..386e8625b3
--- /dev/null
+++ b/board/cappy2/ec.tasklist
@@ -0,0 +1,21 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE)
diff --git a/board/cappy2/gpio.inc b/board/cappy2/gpio.inc
new file mode 100644
index 0000000000..1a32f31e06
--- /dev/null
+++ b/board/cappy2/gpio.inc
@@ -0,0 +1,148 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first.
+ */
+
+/* Power Interrupts */
+GPIO_INT(SLP_S0_L,		 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,		 PIN(A, 5), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(SLP_S4_L,		 PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,		 PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(RSMRST_PWRGD_L,	 PIN(C, 6), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID1,	 PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(CPU_C10_GATE_L,	 PIN(6, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID0,	 PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, power_signal_interrupt)
+GPIO_INT(PG_VCCIO_EXT_OD,	 PIN(B, 0), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(PG_PP5000_U_OD,	 PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_DRAM_OD,		 PIN(E, 4), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(PG_PP1050_ST_OD,	 PIN(4, 2), GPIO_INT_BOTH, power_signal_interrupt)
+
+/* USB-C interrupts */
+GPIO_INT(USB_C0_INT_ODL,	PIN(6, 2), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt)
+GPIO_INT(USB_C0_CCSBU_OVP_ODL,	PIN(A, 2), GPIO_INT_FALLING | GPIO_PULL_UP, c0_ccsbu_ovp_interrupt)
+
+/* Button interrupts */
+GPIO_INT(EC_PWR_BTN_ODL,	 PIN(0, 1), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
+
+/* Other interrupts */
+GPIO_INT(LID_OPEN,		 PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)
+GPIO_INT(EC_WP_OD,		 PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+
+/* I2C Ports */
+GPIO(EC_I2C_EEPROM_SCL,		PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SDA,		PIN(B, 2), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SCL,      	PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SDA,      	PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SCL,	      	PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SDA,	      	PIN(8, 7), GPIO_INPUT)
+
+/* Extra Sub-board I/O pins */
+GPIO(LTE_EN, 			PIN(6, 0), GPIO_OUT_LOW)
+
+/* Misc Enables */
+GPIO(EN_VCCIO_EXT,   		PIN(6, 1), GPIO_OUT_LOW)
+/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
+GPIO(EN_VCCST,			PIN(A, 7), GPIO_INPUT)
+GPIO(EN_PP3300_A,		PIN(0, 3), GPIO_OUT_LOW)
+GPIO(EN_PP5000_U,		PIN(A, 4), GPIO_OUT_LOW)
+GPIO(EN_SLP_Z,			PIN(8, 3), GPIO_OUT_LOW)
+GPIO(EN_BL_OD,			PIN(D, 3), GPIO_ODR_LOW)
+GPIO(EC_CBI_WP,			PIN(E, 5), GPIO_OUT_LOW)
+
+/* LED */
+GPIO(LED_B_ODL,                  PIN(C, 2), GPIO_OUT_HIGH)        /* PWM_CH_LED2_BLUE */
+GPIO(LED_G_ODL,                  PIN(C, 3), GPIO_OUT_HIGH)        /* PWM_CH_LED1_GREEN */
+GPIO(LED_R_ODL,                  PIN(C, 4), GPIO_OUT_HIGH)        /* PWM_CH_LED2_ORANGE */
+
+/* Power Sequencing */
+GPIO(EC_AP_PSYS,	     	PIN(B, 7), GPIO_OUT_LOW)
+GPIO(EC_AP_RSMRST_L,         	PIN(A, 6), GPIO_OUT_LOW)
+GPIO(EC_AP_PWR_BTN_ODL,      	PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(EC_AP_RTCRST,           	PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_AP_WAKE_ODL,         	PIN(7, 4), GPIO_ODR_HIGH)
+GPIO(EC_AP_DPWROK,	     	PIN(A, 3), GPIO_OUT_LOW)
+GPIO(EC_AP_PCH_PWROK_OD,     	PIN(9, 4), GPIO_ODR_LOW)
+GPIO(EC_AP_VCCST_PWRGD_OD,   	PIN(B, 1), GPIO_ODR_LOW)
+GPIO(EC_AP_SYS_PWROK,	     	PIN(0, 2), GPIO_OUT_LOW)
+GPIO(EC_AP_MKBP_INT_L,	     	PIN(7, 0), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_ODL,	     	PIN(F, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(EC_ENTERING_RW,	     	PIN(E, 3), GPIO_OUT_LOW)
+GPIO(ALL_SYS_PWRGD,	     	PIN(A, 0), GPIO_OUT_LOW)
+GPIO(SYS_RST_ODL,	     	PIN(C, 5), GPIO_ODR_HIGH)
+
+/* USB pins */
+GPIO(EC_AP_USB_C1_HDMI_HPD,  	PIN(9, 6), GPIO_OUT_LOW)
+GPIO(EC_AP_USB_C0_HPD,	     	PIN(9, 3), GPIO_OUT_LOW)
+GPIO(HDMI_SEL_L,	     	PIN(7, 2), GPIO_OUT_HIGH)
+GPIO(EC_BATTERY_PRES_ODL,    	PIN(E, 1), GPIO_INPUT)
+GPIO(EN_USB_A0_VBUS,	 	PIN(4, 1), GPIO_OUT_LOW)		/* Enable A1 5V Charging */
+/*
+ * cappy2 doesn't have these physical pins coming to the EC but uses other
+ * logic.
+ */
+UNIMPLEMENTED(AC_PRESENT)
+UNIMPLEMENTED(PG_EC_DSW_PWROK)
+UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
+UNIMPLEMENTED(VOLDN_BTN_ODL)
+UNIMPLEMENTED(VOLUP_BTN_ODL)
+
+/* Alternate Functions */
+/* ADC */
+ALTERNATE(PIN_MASK(F, BIT(0)), 0, MODULE_ADC, 0)		/* ADC9 */
+ALTERNATE(PIN_MASK(3, BIT(4)), 0, MODULE_ADC, 0)		/* ADC6 */
+ALTERNATE(PIN_MASK(4, BIT(3)|BIT(4)|BIT(5)), 0, MODULE_ADC, 0)	/* ADC0-2 */
+
+/* Keyboard */
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI0, KSI1 */
+ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI2-7 */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO0, KSO1 */
+ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO3-9 */
+ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO10-13 */
+ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO14 */
+GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW)	/* KSO2 inverted */
+
+/* UART */
+ALTERNATE(PIN_MASK(6, BIT(4)|BIT(5)), 0, MODULE_UART, 0)  /* UART1 */
+
+/* I2C */
+ALTERNATE(PIN_MASK(B, BIT(2)|BIT(3)), 0, MODULE_I2C, 0)	/* I2C7 */
+ALTERNATE(PIN_MASK(3, BIT(3)|BIT(6)), 0, MODULE_I2C, 0)	/* I2C5 */
+ALTERNATE(PIN_MASK(9, BIT(0)), 0, MODULE_I2C, 0)	/* I2C1 SCL */
+ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)	/* I2C1 SDA */
+
+/* NC pins, enable internal pull-up to avoid floating state. */
+GPIO(GPIO00_NC, PIN(0, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO32_NC, PIN(3, 2), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO35_NC, PIN(3, 5), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO37_NC, PIN(3, 7), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO50_NC,	PIN(5, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO56_NC,	PIN(5, 6), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO57_NC, PIN(5, 7), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO63_NC,	PIN(6, 3), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO73_NC, PIN(7, 3), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO75_NC, PIN(7, 5), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO80_NC, PIN(8, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO81_NC, PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO86_NC, PIN(8, 6), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO91_NC,	PIN(9, 1), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO92_NC,	PIN(9, 2), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO95_NC,	PIN(9, 5), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO97_NC,	PIN(9, 7), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOB4_NC,	PIN(B, 4), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOB5_NC,	PIN(B, 5), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOD0_NC, PIN(D, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOD1_NC, PIN(D, 1), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOD6_NC, PIN(D, 6), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOE0_NC, PIN(E, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO40_NC, PIN(4, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOF2_NC,	PIN(F, 2), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOF3_NC,	PIN(F, 3), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOF5_NC,	PIN(F, 5), GPIO_INPUT | GPIO_PULL_UP)
diff --git a/board/cappy2/led.c b/board/cappy2/led.c
new file mode 100644
index 0000000000..dba215ab51
--- /dev/null
+++ b/board/cappy2/led.c
@@ -0,0 +1,134 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power and battery LED control for lalala
+ */
+
+#include "chipset.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+
+#define LED_ON_LVL 0
+#define LED_OFF_LVL 1
+
+__override const int led_charge_lvl_1 = 1;
+
+__override const int led_charge_lvl_2 = 100;
+
+/* cappy2 : There are 3 leds for AC, Battery and Power */
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     1 * LED_ONE_SEC },
+					   { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED,
+					    0.5 * LED_ONE_SEC },
+					  { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					 { LED_OFF, 1 * LED_ONE_SEC } },
+	};
+
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_BLUE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_power(enum ec_led_colors color)
+{
+	/* Don't set led if led_auto_control is disabled. */
+	if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) ||
+	    !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
+		return;
+	}
+
+	if (color == EC_LED_COLOR_BLUE) {
+		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_ON_LVL);
+	} else {
+		/* LED_OFF and unsupported colors */
+		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_OFF_LVL);
+	}
+}
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	/* Don't set led if led_auto_control is disabled. */
+	if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) ||
+	    !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
+		return;
+	}
+
+	/* Battery leds must be turn off when blue led is on
+	 * because the led is 3-in-1 led.
+	 */
+	if (!gpio_get_level(GPIO_PWR_LED_BLUE_L)) {
+		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); /*red*/
+		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); /*green*/
+		return;
+	}
+
+	switch (color) {
+	case EC_LED_COLOR_GREEN:
+		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); /*red*/
+		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_ON_LVL); /*green*/
+		break;
+	case EC_LED_COLOR_RED:
+		gpio_set_level(GPIO_BAT_LED_RED_L, LED_ON_LVL); /*red*/
+		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); /*green*/
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); /*red*/
+		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); /*green*/
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_GREEN] = 1;
+		brightness_range[EC_LED_COLOR_RED] = 1;
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		brightness_range[EC_LED_COLOR_BLUE] = 1;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_BAT_LED_GREEN_L,
+			       !brightness[EC_LED_COLOR_GREEN]);
+		gpio_set_level(GPIO_BAT_LED_RED_L,
+			       !brightness[EC_LED_COLOR_RED]);
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		gpio_set_level(GPIO_PWR_LED_BLUE_L,
+			       !brightness[EC_LED_COLOR_BLUE]);
+		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/board/cappy2/usb_pd_policy.c b/board/cappy2/usb_pd_policy.c
new file mode 100644
index 0000000000..3410726e87
--- /dev/null
+++ b/board/cappy2/usb_pd_policy.c
@@ -0,0 +1,56 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "driver/tcpm/tcpci.h"
+#include "usb_pd.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+int pd_check_vconn_swap(int port)
+{
+	/* Allow VCONN swaps if the AP is on. */
+	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
+}
+
+void pd_power_supply_reset(int port)
+{
+	/* Disable VBUS */
+	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	if (port >= CONFIG_USB_PD_PORT_MAX_COUNT)
+		return EC_ERROR_INVAL;
+
+	/* Disable charging. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
+	if (rv)
+		return rv;
+
+	/* Our policy is not to source VBUS when the AP is off. */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	/* Provide Vbus. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
+	if (rv)
+		return rv;
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
diff --git a/board/cappy2/vif_override.xml b/board/cappy2/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/cappy2/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/careena/battery.c b/board/careena/battery.c
index 695bbaa63a..ae8b2f905a 100644
--- a/board/careena/battery.c
+++ b/board/careena/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -33,7 +33,7 @@
  */
 const struct board_batt_params board_battery_info[] = {
 	/* DynaPack Coslight Battery Information */
-	[BATTERY_DANAPACK_COS] = {
+	[BATTERY_DYNAPACK_COS] = {
 		.fuel_gauge = {
 			.manuf_name = "333-2C-DA-A",
 			.ship_mode = {
@@ -63,7 +63,7 @@ const struct board_batt_params board_battery_info[] = {
 	},
 
 	/* DynaPack ATL Battery Information */
-	[BATTERY_DANAPACK_ATL] = {
+	[BATTERY_DYNAPACK_ATL] = {
 		.fuel_gauge = {
 			.manuf_name = "333-27-DA-A",
 			.ship_mode = {
@@ -93,7 +93,7 @@ const struct board_batt_params board_battery_info[] = {
 	},
 
 	/* DynaPack SDI Battery Information */
-	[BATTERY_DANAPACK_SDI] = {
+	[BATTERY_DYNAPACK_SDI] = {
 		.fuel_gauge = {
 			.manuf_name = "333-24-DA-A",
 			.ship_mode = {
@@ -241,7 +241,37 @@ const struct board_batt_params board_battery_info[] = {
 			.discharging_max_c = 60,
 		},
 	},
+
+	/* CosMX B00C4473A9D0002 Battery Information */
+	[BATTERY_COS] = {
+		.fuel_gauge = {
+			.manuf_name = "333-AC-DA-A",
+			.ship_mode = {
+				.reg_addr = 0x0,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+			},
+			.imbalance_mv = &battery_default_imbalance_mv,
+		},
+		.batt_info = {
+			.voltage_max = 8800,		/* mV */
+			.voltage_normal = 7700,		/* mV */
+			.voltage_min = 6000,		/* mV */
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
 };
 BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
 
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_DANAPACK_COS;
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_DYNAPACK_COS;
diff --git a/board/careena/board.c b/board/careena/board.c
index 082a47ab50..01c92dfe1a 100644
--- a/board/careena/board.c
+++ b/board/careena/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,6 +8,7 @@
 #include "button.h"
 #include "driver/tcpm/ps8xxx.h"
 #include "extpower.h"
+#include "hooks.h"
 #include "i2c.h"
 #include "lid_switch.h"
 #include "power.h"
@@ -15,7 +16,9 @@
 #include "pwm.h"
 #include "pwm_chip.h"
 #include "switch.h"
+#include "thermal.h"
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 const enum gpio_signal hibernate_wake_pins[] = {
@@ -24,15 +27,35 @@ const enum gpio_signal hibernate_wake_pins[] = {
 	GPIO_POWER_BUTTON_L,
 	GPIO_EC_RST_ODL,
 };
-const int hibernate_wake_pins_used =  ARRAY_SIZE(hibernate_wake_pins);
+const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 
 /* I2C port map. */
 const struct i2c_port_t i2c_ports[] = {
-	{"power",   I2C_PORT_POWER,   100, GPIO_I2C0_SCL, GPIO_I2C0_SDA},
-	{"tcpc0",   I2C_PORT_TCPC0,   400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"tcpc1",   I2C_PORT_TCPC1,   400, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-	{"thermal", I2C_PORT_THERMAL_AP, 400, GPIO_I2C3_SCL, GPIO_I2C3_SDA},
-	{"sensor",  I2C_PORT_SENSOR,  400, GPIO_I2C7_SCL, GPIO_I2C7_SDA},
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_I2C0_SCL,
+	  .sda = GPIO_I2C0_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "tcpc1",
+	  .port = I2C_PORT_TCPC1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "thermal",
+	  .port = I2C_PORT_THERMAL_AP,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_I2C7_SCL,
+	  .sda = GPIO_I2C7_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -46,6 +69,35 @@ const struct pwm_t pwm_channels[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
+struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT] = {
+	[TEMP_SENSOR_SOC] = {
+		.temp_host = {
+			[EC_TEMP_THRESH_WARN] = 0,
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(74),
+			[EC_TEMP_THRESH_HALT] = C_TO_K(79),
+		},
+		.temp_host_release = {
+			[EC_TEMP_THRESH_WARN] = 0,
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(71),
+			[EC_TEMP_THRESH_HALT] = 0,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
+
+static void board_init(void)
+{
+	/*
+	 * Ensure PROCHOT is deasserted after sysjump.
+	 * The GPIO was an input in old RO images. On sysjump to new RW, the
+	 * direction is changed to output but the level is not set, which
+	 * results in the output driving low, which asserts PROCHOT incorrectly.
+	 * (crbug.com/1226694)
+	 */
+	gpio_set_level(GPIO_CPU_PROCHOT, 1);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
 #ifdef CONFIG_KEYBOARD_FACTORY_TEST
 /*
  * We have total 24 pins for keyboard connecter, {-1, -1} mean
@@ -53,15 +105,15 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
  * that we don't have pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-		{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-		{0, 7}, {1, 4}, {1, 3}, {1, 6}, {-1, -1},
-		{3, 1}, {2, 0}, {1, 5}, {2, 6}, {-1, -1},
-		{2, 1}, {2, 4}, {2, 5}, {1, 2}, {2, 3},
-		{2, 2}, {3, 0}, {-1, -1}, {-1, -1}, {-1, -1},
+	{ -1, -1 }, { 0, 5 }, { 1, 1 },	  { 1, 0 },   { 0, 6 },
+	{ 0, 7 },   { 1, 4 }, { 1, 3 },	  { 1, 6 },   { -1, -1 },
+	{ 3, 1 },   { 2, 0 }, { 1, 5 },	  { 2, 6 },   { -1, -1 },
+	{ 2, 1 },   { 2, 4 }, { 2, 5 },	  { 1, 2 },   { 2, 3 },
+	{ 2, 2 },   { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 },
 };
 
 const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 
 static int board_is_support_ps8755_tcpc(void)
 {
diff --git a/board/careena/board.h b/board/careena/board.h
index ed17d38646..86b88b64f0 100644
--- a/board/careena/board.h
+++ b/board/careena/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,7 +17,7 @@
  * By default, enable all console messages excepted HC, ACPI and event:
  * The sensor stack is generating a lot of activity.
  */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
 #undef CONFIG_HOSTCMD_DEBUG_MODE
 #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
 
@@ -27,6 +27,11 @@
 #define CONFIG_CMD_LEDTEST
 #define CONFIG_KEYBOARD_FACTORY_TEST
 
+/* Thermal */
+#define CONFIG_CHIPSET_CAN_THROTTLE
+#define CONFIG_CPU_PROCHOT_ACTIVE_LOW
+#define CONFIG_THROTTLE_AP
+
 #define CONFIG_BATTERY_MEASURE_IMBALANCE
 #define CONFIG_BATTERY_BQ4050
 
@@ -36,27 +41,20 @@
 
 #ifndef __ASSEMBLER__
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_COUNT };
 
 enum battery_type {
-	BATTERY_DANAPACK_COS,
-	BATTERY_DANAPACK_ATL,
-	BATTERY_DANAPACK_SDI,
+	BATTERY_DYNAPACK_COS,
+	BATTERY_DYNAPACK_ATL,
+	BATTERY_DYNAPACK_SDI,
 	BATTERY_SAMSUNG_SDI,
 	BATTERY_SIMPLO_COS,
 	BATTERY_SIMPLO_ATL,
 	BATTERY_SIMPLO_HIGHPOWER,
+	BATTERY_COS,
 	BATTERY_TYPE_COUNT,
 };
 
-#ifdef CONFIG_KEYBOARD_FACTORY_TEST
-extern const int keyboard_factory_scan_pins[][2];
-extern const int keyboard_factory_scan_pins_used;
-#endif
-
 #endif /* !__ASSEMBLER__ */
 
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/careena/build.mk b/board/careena/build.mk
index c808e65aed..d24127ddae 100644
--- a/board/careena/build.mk
+++ b/board/careena/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/careena/ec.tasklist b/board/careena/ec.tasklist
index b562761311..24300fe7da 100644
--- a/board/careena/ec.tasklist
+++ b/board/careena/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/careena/gpio.inc b/board/careena/gpio.inc
index eeccf9f50d..477b17234e 100644
--- a/board/careena/gpio.inc
+++ b/board/careena/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -38,7 +38,7 @@ GPIO(CCD_MODE_ODL,		PIN(E, 3), GPIO_INPUT)				/* Case Closed Debug Mode */
 GPIO(ENTERING_RW,		PIN(E, 1), GPIO_OUT_LOW)			/* EC Entering RW */
 GPIO(EC_BATT_PRES_L,		PIN(E, 5), GPIO_INPUT | GPIO_PULL_UP)		/* Battery Present */
 GPIO(PCH_SYS_PWROK,		PIN(D, 6), GPIO_OUT_LOW)			/* Power OK to SOC */
-GPIO(CPU_PROCHOT,		PIN(3, 4), GPIO_INPUT | GPIO_SEL_1P8V)		/* PROCHOT to SOC */
+GPIO(CPU_PROCHOT,		PIN(3, 4), GPIO_ODR_HIGH | GPIO_SEL_1P8V)	/* PROCHOT to SOC */
 GPIO(APU_ALERT_L,		PIN(A, 2), GPIO_INPUT)				/* Alert to SOC */
 GPIO(3AXIS_INT_L,		PIN(5, 0), GPIO_INPUT | GPIO_SEL_1P8V)		/* 3 Axis Accel */
 GPIO(TCPC_ID,			PIN(E, 0), GPIO_INPUT | GPIO_PULL_DOWN)		/* TCPC ID pin */
diff --git a/board/careena/led.c b/board/careena/led.c
index 4188290b4f..dd5cffc385 100644
--- a/board/careena/led.c
+++ b/board/careena/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -14,13 +14,13 @@
 #include "hooks.h"
 #include "host_command.h"
 #include "led_common.h"
-#include "util.h"
 #include "system.h"
+#include "util.h"
 
 #define BAT_LED_ON 0
 #define BAT_LED_OFF 1
 
-const enum ec_led_id supported_led_ids[] = {EC_LED_ID_BATTERY_LED};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -28,7 +28,7 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static int led_set_color_battery(enum led_color color)
@@ -88,32 +88,30 @@ static void led_set_battery(void)
 {
 	static int battery_ticks;
 	static int power_ticks;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
 	/* override battery led for system suspend */
-	if (chipset_in_state(CHIPSET_STATE_SUSPEND |
-			     CHIPSET_STATE_STANDBY) &&
-	    charge_get_state() != PWR_STATE_CHARGE) {
-		led_set_color_battery(power_ticks++ & 0x4 ?
-				      LED_WHITE : LED_OFF);
+	if (chipset_in_state(CHIPSET_STATE_SUSPEND | CHIPSET_STATE_STANDBY) &&
+	    led_pwr_get_state() != LED_PWRS_CHARGE) {
+		led_set_color_battery(power_ticks++ & 0x4 ? LED_WHITE :
+							    LED_OFF);
 		return;
 	}
 
 	power_ticks = 0;
 
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
 		led_set_color_battery(LED_AMBER);
 		break;
-	case PWR_STATE_DISCHARGE_FULL:
+	case LED_PWRS_DISCHARGE_FULL:
 		if (extpower_is_present()) {
 			led_set_color_battery(LED_WHITE);
 			break;
 		}
-		/* Intentional fall-through */
-	case PWR_STATE_DISCHARGE:
+		__fallthrough;
+	case LED_PWRS_DISCHARGE:
 		/*
 		 * Blink white light (1 sec on, 1 sec off)
 		 * when battery capacity is less than 10%
@@ -124,19 +122,19 @@ static void led_set_battery(void)
 		else
 			led_set_color_battery(LED_OFF);
 		break;
-	case PWR_STATE_ERROR:
-		led_set_color_battery(
-			(battery_ticks & 0x2) ? LED_WHITE : LED_OFF);
+	case LED_PWRS_ERROR:
+		led_set_color_battery((battery_ticks & 0x2) ? LED_WHITE :
+							      LED_OFF);
 		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
+	case LED_PWRS_CHARGE_NEAR_FULL:
 		led_set_color_battery(LED_WHITE);
 		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			led_set_color_battery(
-				(battery_ticks & 0x4) ? LED_AMBER : LED_OFF);
-		else
-			led_set_color_battery(LED_WHITE);
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		led_set_color_battery(LED_WHITE);
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		led_set_color_battery((battery_ticks & 0x4) ? LED_AMBER :
+							      LED_OFF);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
diff --git a/board/careena/vif_override.xml b/board/careena/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/careena/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/casta/battery.c b/board/casta/battery.c
index 0ced18e734..846165ff13 100644
--- a/board/casta/battery.c
+++ b/board/casta/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -12,9 +12,10 @@
 #include "common.h"
 #include "util.h"
 
-#define CHARGING_VOLTAGE_MV_SAFE        8400
-#define CHARGING_CURRENT_MA_SAFE        1500
-
+#define CHARGING_VOLTAGE_MV_SAFE 8400
+#define CHARGING_CURRENT_MA_SAFE 1500
+#define CHARGING_VOLTAGE_MV_ADJUST 8600
+#define CHARGING_CURRENT_MA_ADJUST 3200
 /*
  * Battery info for all casta battery types. Note that the fields
  * start_charging_min/max and charging_min/max are not used for the charger.
@@ -54,7 +55,7 @@ const struct board_batt_params board_battery_info[] = {
 			}
 		},
 		.batt_info = {
-			.voltage_max            = 8650,
+			.voltage_max            = 8600,
 			.voltage_normal         = 7700, /* mV */
 			.voltage_min            = 6000, /* mV */
 			.precharge_current      = 200,  /* mA */
@@ -95,15 +96,19 @@ int charger_profile_override(struct charge_state_data *curr)
 		TEMP_OUT_OF_RANGE = TEMP_ZONE_COUNT
 	} temp_zone;
 
-        /*
-         * Precharge must be executed when communication is failed on
+	/*
+	 * Precharge must be executed when communication is failed on
 	 * dead battery.
-         */
-        if(!(curr->batt.flags & BATT_FLAG_RESPONSIVE))
-                return 0;
+	 */
+	if (!(curr->batt.flags & BATT_FLAG_RESPONSIVE))
+		return 0;
 
 	current = curr->requested_current;
+	if (current > CHARGING_CURRENT_MA_ADJUST)
+		current = CHARGING_CURRENT_MA_ADJUST;
 	voltage = curr->requested_voltage;
+	if (voltage > CHARGING_VOLTAGE_MV_ADJUST)
+		voltage = CHARGING_VOLTAGE_MV_ADJUST;
 	bat_temp_c = curr->batt.temperature - 2731;
 	batt_info = battery_get_info();
 
@@ -146,7 +151,7 @@ int charger_profile_override(struct charge_state_data *curr)
 		break;
 	}
 
-	if(voltage > batt_info->voltage_max)
+	if (voltage > batt_info->voltage_max)
 		voltage = batt_info->voltage_max;
 
 	curr->requested_voltage = MIN(curr->requested_voltage, voltage);
diff --git a/board/casta/board.c b/board/casta/board.c
index e1d7630e3f..5529c3a36d 100644
--- a/board/casta/board.c
+++ b/board/casta/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,13 +6,15 @@
 /* Casta board-specific configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "battery.h"
+#include "cbi_ssfc.h"
 #include "charge_manager.h"
 #include "charge_state.h"
 #include "common.h"
 #include "cros_board_info.h"
 #include "driver/charger/bd9995x.h"
+#include "driver/charger/bq25710.h"
+#include "driver/charger/isl923x.h"
 #include "driver/ppc/nx20p348x.h"
 #include "driver/tcpm/anx7447.h"
 #include "driver/tcpm/ps8xxx.h"
@@ -28,17 +30,17 @@
 #include "power_button.h"
 #include "switch.h"
 #include "system.h"
-#include "tcpci.h"
+#include "tcpm/tcpci.h"
 #include "temp_sensor.h"
-#include "thermistor.h"
+#include "temp_sensor/thermistor.h"
 #include "usb_mux.h"
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 static uint8_t sku_id;
 
@@ -58,46 +60,55 @@ static void ppc_interrupt(enum gpio_signal signal)
 	}
 }
 
-/* Must come after other header files and GPIO interrupts*/
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_AMB] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_AMB] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				  ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_CHARGER] = { "TEMP_CHARGER", NPCX_ADC_CH1,
+				      ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* TODO(b/119872005): Casta: confirm thermistor parts */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp,
-				 .idx = 0},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
+	[TEMP_SENSOR_BATTERY] = { .name = "Battery",
+				  .type = TEMP_SENSOR_TYPE_BATTERY,
+				  .read = charge_get_battery_temp,
+				  .idx = 0 },
+	[TEMP_SENSOR_AMBIENT] = { .name = "Ambient",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_51k1_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_AMB },
+	[TEMP_SENSOR_CHARGER] = { .name = "Charger",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_13k7_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_CHARGER },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
+/* Charger config.  Start i2c address at isl9238, update during runtime */
+struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+};
+const unsigned int chg_cnt = ARRAY_SIZE(chg_chips);
+
 /*
  * I2C callbacks to ensure bus free time for battery I2C transactions is at
  * least 5ms.
  */
-#define BATTERY_FREE_MIN_DELTA_US               (5 * MSEC)
+#define BATTERY_FREE_MIN_DELTA_US (5 * MSEC)
 static timestamp_t battery_last_i2c_time;
 
-static int is_battery_i2c(const int port, const uint16_t slave_addr_flags)
+static int is_battery_i2c(const int port, const uint16_t addr_flags)
 {
-	return (port == I2C_PORT_BATTERY)
-		&& (slave_addr_flags == BATTERY_ADDR_FLAGS);
+	return (port == I2C_PORT_BATTERY) && (addr_flags == BATTERY_ADDR_FLAGS);
 }
 
 static int is_battery_port(int port)
@@ -105,11 +116,11 @@ static int is_battery_port(int port)
 	return (port == I2C_PORT_BATTERY);
 }
 
-void i2c_start_xfer_notify(const int port, const uint16_t slave_addr_flags)
+void i2c_start_xfer_notify(const int port, const uint16_t addr_flags)
 {
 	unsigned int time_delta_us;
 
-	if (!is_battery_i2c(port, slave_addr_flags))
+	if (!is_battery_i2c(port, addr_flags))
 		return;
 
 	time_delta_us = time_since32(battery_last_i2c_time);
@@ -119,7 +130,7 @@ void i2c_start_xfer_notify(const int port, const uint16_t slave_addr_flags)
 	usleep(BATTERY_FREE_MIN_DELTA_US - time_delta_us);
 }
 
-void i2c_end_xfer_notify(const int port, const uint16_t slave_addr_flags)
+void i2c_end_xfer_notify(const int port, const uint16_t addr_flags)
 {
 	/*
 	 * The bus free time needs to be maintained from last transaction
@@ -141,18 +152,30 @@ static void cbi_init(void)
 	sku_id = val;
 	CPRINTS("SKU: %d", sku_id);
 }
-DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1);
+DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C);
 
-/* TODO: Casta: remove this routine after rev0 is not supported */
 static void board_init(void)
 {
-	uint32_t val;
-	if (cbi_get_board_version(&val) == EC_SUCCESS && val > 0)
+	if (get_cbi_ssfc_charger() != SSFC_CHARGER_BQ25710)
+		return;
+
+	chg_chips[0].drv = &bq25710_drv;
+	chg_chips[0].i2c_addr_flags = BQ25710_SMBUS_ADDR1_FLAGS;
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_INIT_I2C);
+
+static void set_input_limit_on_ac_removal(void)
+{
+	if (extpower_is_present())
+		return;
+
+	if (get_cbi_ssfc_charger() != SSFC_CHARGER_BQ25710)
 		return;
 
-	gpio_set_flags(GPIO_USB_C0_MUX_INT_ODL, GPIO_INT_FALLING | GPIO_PULL_UP);
+	charger_set_input_current_limit(0,
+					CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT);
 }
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_AC_CHANGE, set_input_limit_on_ac_removal, HOOK_PRIO_DEFAULT);
 
 void board_overcurrent_event(int port, int is_overcurrented)
 {
diff --git a/board/casta/board.h b/board/casta/board.h
index 7f934dc4c6..3e7fe066cc 100644
--- a/board/casta/board.h
+++ b/board/casta/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,17 +10,22 @@
 
 /* Select Baseboard features */
 #define VARIANT_OCTOPUS_EC_NPCX796FB
-#define VARIANT_OCTOPUS_CHARGER_ISL9238
 #define VARIANT_OCTOPUS_TCPC_0_PS8751
 #define VARIANT_OCTOPUS_NO_SENSORS
+#define CONFIG_CHARGER_RUNTIME_CONFIG
 #include "baseboard.h"
 
+#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD
+
 #define CONFIG_LED_COMMON
-#define CONFIG_LED_POWER_LED
 
 /* USB PD */
 #undef CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT
-#define CONFIG_USB_PD_VBUS_MEASURE_NOT_PRESENT
+/*
+ * This board configures two chargers, one of which can measure VBUS and one of
+ * which cannot. Leave the default config, which defines
+ * CONFIG_USB_PD_VBUS_MEASURE_CHARGER.
+ */
 
 #define CONFIG_TEMP_SENSOR
 #define CONFIG_THERMISTOR
@@ -30,7 +35,6 @@
  * communicate on locked systems (which haven't PD negotiated).
  */
 #define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT 15000
-#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC 1
 
 #define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 15001
 
@@ -50,24 +54,28 @@
 
 /* All casta systems are clamshells */
 #undef CONFIG_TABLET_MODE
-#undef CONFIG_TABLET_SWITCH
 
 /* TODO(b/119872005): Casta: confirm thermistor parts */
 #define CONFIG_STEINHART_HART_3V3_13K7_47K_4050B
 #define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
 
 /* Battery W/A */
+#define CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA 6144
 #define CONFIG_CHARGER_PROFILE_OVERRIDE
 #define CONFIG_I2C_XFER_BOARD_CALLBACK
 
+/* The board needs 100ms for VBUS_C[0|1]_BC12 to drop to lower VvbusUVLO */
+#undef CONFIG_BC12_MAX14637_DELAY_FROM_OFF_TO_ON_MS
+#define CONFIG_BC12_MAX14637_DELAY_FROM_OFF_TO_ON_MS 100
+
 #ifndef __ASSEMBLER__
 
 #include "gpio_signal.h"
 #include "registers.h"
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_AMB,		/* ADC0 */
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC1 */
+	ADC_TEMP_SENSOR_AMB, /* ADC0 */
+	ADC_TEMP_SENSOR_CHARGER, /* ADC1 */
 	ADC_CH_COUNT
 };
 
diff --git a/board/casta/build.mk b/board/casta/build.mk
index 3d04b75731..998a65a3de 100644
--- a/board/casta/build.mk
+++ b/board/casta/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/casta/ec.tasklist b/board/casta/ec.tasklist
index ac41d643dc..5a1dc02a25 100644
--- a/board/casta/ec.tasklist
+++ b/board/casta/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/casta/gpio.inc b/board/casta/gpio.inc
index e37926b72e..724efd36ce 100644
--- a/board/casta/gpio.inc
+++ b/board/casta/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/casta/led.c b/board/casta/led.c
index 2f1a8a6b35..7dfdc39151 100644
--- a/board/casta/led.c
+++ b/board/casta/led.c
@@ -1,8 +1,8 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
- * Power and battery LED control for Casta 
+ * Power and battery LED control for Casta
  */
 
 #include "chipset.h"
@@ -12,56 +12,59 @@
 #include "led_common.h"
 #include "led_onoff_states.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
-const int led_charge_lvl_1 = 1;
+__override const int led_charge_lvl_1 = 1;
 
-const int led_charge_lvl_2 = 100;
+__override const int led_charge_lvl_2 = 100;
 
 /* Casta : There are 3 leds for AC, Battery and Power */
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC},
-       					{LED_OFF, 1 * LED_ONE_SEC} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED, 0.5 * LED_ONE_SEC},
-					{LED_OFF, 0.5 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC},
-					{LED_OFF, 1 * LED_ONE_SEC} },
-};
-
-const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     1 * LED_ONE_SEC },
+					   { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_GREEN,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED,
+					    0.5 * LED_ONE_SEC },
+					  { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					 { LED_OFF, 1 * LED_ONE_SEC } },
+	};
+
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_BLUE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-void led_set_color_power(enum ec_led_colors color)
+__override void led_set_color_power(enum ec_led_colors color)
 {
 	/* Don't set led if led_auto_control is disabled. */
 	if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) ||
-                !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
+	    !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
 		return;
-        }
+	}
 
-	if (color == EC_LED_COLOR_BLUE)
-	{
-                gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
-                gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
+	if (color == EC_LED_COLOR_BLUE) {
+		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
 		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_ON_LVL);
 	} else {
 		/* LED_OFF and unsupported colors */
@@ -69,21 +72,20 @@ void led_set_color_power(enum ec_led_colors color)
 	}
 }
 
-void led_set_color_battery(enum ec_led_colors color)
+__override void led_set_color_battery(enum ec_led_colors color)
 {
 	/* Don't set led if led_auto_control is disabled. */
 	if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) ||
-                !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
+	    !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
 		return;
-        }
+	}
 
 	/* Battery leds must be turn off when blue led is on
 	 * because casta has 3-in-1 led.
 	 */
-	if(!gpio_get_level(GPIO_PWR_LED_BLUE_L))
-	{
+	if (!gpio_get_level(GPIO_PWR_LED_BLUE_L)) {
 		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); /*red*/
-                gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); /*green*/
+		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); /*green*/
 		return;
 	}
 
@@ -117,14 +119,16 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 {
 	if (led_id == EC_LED_ID_BATTERY_LED) {
 		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, !brightness[EC_LED_COLOR_GREEN]);
-		gpio_set_level(GPIO_BAT_LED_RED_L, !brightness[EC_LED_COLOR_RED]);
+		gpio_set_level(GPIO_BAT_LED_GREEN_L,
+			       !brightness[EC_LED_COLOR_GREEN]);
+		gpio_set_level(GPIO_BAT_LED_RED_L,
+			       !brightness[EC_LED_COLOR_RED]);
 	} else if (led_id == EC_LED_ID_POWER_LED) {
-		gpio_set_level(GPIO_PWR_LED_BLUE_L, !brightness[EC_LED_COLOR_BLUE]);
+		gpio_set_level(GPIO_PWR_LED_BLUE_L,
+			       !brightness[EC_LED_COLOR_BLUE]);
 		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
 		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
 	}
 
 	return EC_SUCCESS;
 }
-
diff --git a/board/casta/vif_override.xml b/board/casta/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/casta/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/cerise/battery.c b/board/cerise/battery.c
index 50d2bf397c..9edab52867 100644
--- a/board/cerise/battery.c
+++ b/board/cerise/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/cerise/board.c b/board/cerise/board.c
index 0a04842e35..5ac4835abb 100644
--- a/board/cerise/board.c
+++ b/board/cerise/board.c
@@ -1,10 +1,9 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "backlight.h"
 #include "button.h"
 #include "charge_manager.h"
@@ -31,6 +30,7 @@
 #include "it8801.h"
 #include "keyboard_scan.h"
 #include "lid_switch.h"
+#include "panic.h"
 #include "power.h"
 #include "power_button.h"
 #include "pwm.h"
@@ -40,41 +40,55 @@
 #include "system.h"
 #include "tablet_mode.h"
 #include "task.h"
-#include "tcpm.h"
+#include "tcpm/tcpm.h"
 #include "timer.h"
 #include "usb_charge.h"
 #include "usb_mux.h"
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
 	schedule_deferred_pd_interrupt(0 /* port */);
 }
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /******************************************************************************/
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] =  {"BOARD_ID",  3300, 4096, 0, STM32_AIN(10)},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)},
+	[ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(10) },
+	[ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /******************************************************************************/
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{"typec", 0, 400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"other", 1, 100, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
+	{ .name = "typec",
+	  .port = 0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "other",
+	  .port = 1,
+	  .kbps = 100,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
 const struct i2c_port_t i2c_bitbang_ports[] = {
-	{"battery", 2, 100, GPIO_I2C3_SCL, GPIO_I2C3_SDA, .drv = &bitbang_drv},
+	{ .name = "battery",
+	  .port = 2,
+	  .kbps = 100,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA,
+	  .drv = &bitbang_drv },
 };
 const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
 
@@ -82,13 +96,13 @@ const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
 
 /* power signal list.  Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
+	{ GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" },
+	{ GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" },
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
 /* Keyboard scan setting */
-struct keyboard_scan_config keyscan_config = {
+__override struct keyboard_scan_config keyscan_config = {
 	/*
 	 * TODO(b/133200075): Tune this once we have the final performance
 	 * out of the driver and the i2c bus.
@@ -107,8 +121,8 @@ struct keyboard_scan_config keyscan_config = {
 
 struct ioexpander_config_t ioex_config[CONFIG_IO_EXPANDER_PORT_COUNT] = {
 	[0] = {
-		.i2c_host_port = I2C_PORT_IO_EXPANDER_IT8801,
-		.i2c_slave_addr = IT8801_I2C_ADDR,
+		.i2c_host_port = I2C_PORT_KB_DISCRETE,
+		.i2c_addr_flags = IT8801_I2C_ADDR1,
 		.drv = &it8801_ioexpander_drv,
 	},
 };
@@ -133,15 +147,18 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = I2C_PORT_TCPC0,
-			.addr_flags = FUSB302_I2C_SLAVE_ADDR_FLAGS,
+			.addr_flags = FUSB302_I2C_ADDR_FLAGS,
 		},
 		.drv = &fusb302_tcpm_drv,
 	},
 };
 
-static void board_hpd_status(const struct usb_mux *me,
-			     int hpd_lvl, int hpd_irq)
+static void board_hpd_status(const struct usb_mux *me, mux_state_t mux_state,
+			     bool *ack_required)
 {
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
 	/*
 	 * svdm_dp_attention() did most of the work, we only need to notify
 	 * host here.
@@ -149,13 +166,16 @@ static void board_hpd_status(const struct usb_mux *me,
 	host_set_single_event(EC_HOST_EVENT_USB_MUX);
 }
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+				.hpd_update = &board_hpd_status,
+			},
 	},
 };
 
@@ -201,7 +221,7 @@ int board_set_active_charge_port(int charge_port)
 		if (board_vbus_source_enabled(charge_port))
 			return -1;
 		break;
-	case CHARGE_PORT_NONE:
+	default:
 		/*
 		 * To ensure the fuel gauge (max17055) is always powered
 		 * even when battery is disconnected, keep VBAT rail on but
@@ -209,22 +229,11 @@ int board_set_active_charge_port(int charge_port)
 		 */
 		charger_set_current(CHARGER_SOLO, 0);
 		break;
-	default:
-		panic("Invalid charge port\n");
-		break;
 	}
 
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-			       CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
-
 int board_discharge_on_ac(int enable)
 {
 	int ret, port;
@@ -254,7 +263,7 @@ int pd_snk_is_vbus_provided(int port)
 
 void bc12_interrupt(enum gpio_signal signal)
 {
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
 }
 
 #ifndef VARIANT_KUKUI_NO_SENSORS
@@ -274,13 +283,12 @@ static void board_spi_enable(void)
 	STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
 
 	/* Reinitialize spi peripheral. */
-	spi_enable(CONFIG_SPI_ACCEL_PORT, 1);
+	spi_enable(&spi_devices[0], 1);
 
 	/* Pin mux spi peripheral toward the sensor. */
-	gpio_config_module(MODULE_SPI_MASTER, 1);
+	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
 }
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP,
-	     board_spi_enable,
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_spi_enable,
 	     MOTION_SENSE_HOOK_PRIO - 1);
 
 static void board_spi_disable(void)
@@ -288,14 +296,13 @@ static void board_spi_disable(void)
 	/* Set pins to a state calming the sensor down. */
 	gpio_set_flags(GPIO_EC_SENSOR_SPI_CK, GPIO_OUT_LOW);
 	gpio_set_level(GPIO_EC_SENSOR_SPI_CK, 0);
-	gpio_config_module(MODULE_SPI_MASTER, 0);
+	gpio_config_module(MODULE_SPI_CONTROLLER, 0);
 
 	/* Disable spi peripheral and clocks. */
-	spi_enable(CONFIG_SPI_ACCEL_PORT, 0);
+	spi_enable(&spi_devices[0], 0);
 	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
 }
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN,
-	     board_spi_disable,
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_spi_disable,
 	     MOTION_SENSE_HOOK_PRIO + 1);
 #endif /* !VARIANT_KUKUI_NO_SENSORS */
 
@@ -324,6 +331,9 @@ static void board_init(void)
 
 	/* Enable BC12 interrupt */
 	gpio_enable_interrupt(GPIO_BC12_EC_INT_ODL);
+
+	/* Enable USM mode */
+	ioex_set_level(IOEX_5V_DC_DC_MODE_CTRL, 1);
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
@@ -334,17 +344,13 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Rotation matrixes */
-static const mat33_fp_t base_standard_ref = {
-	{FLOAT_TO_FP(1), 0, 0},
-	{0, FLOAT_TO_FP(-1), 0},
-	{0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+					      { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
 
-static const mat33_fp_t lid_standard_ref = {
-	{FLOAT_TO_FP(1), 0, 0},
-	{0, FLOAT_TO_FP(1), 0},
-	{0, 0, FLOAT_TO_FP(1) }
-};
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					     { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
 /* sensor private data */
 /* Lid accel private data */
@@ -394,9 +400,10 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_base_mutex,
 		.drv_data = &g_bmi160_data,
 		.port = CONFIG_SPI_ACCEL_PORT,
-		.i2c_spi_addr_flags = SLAVE_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
+		.i2c_spi_addr_flags =
+				ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
 		.rot_standard_ref = &base_standard_ref,
-		.default_range = 2,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
+		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
 		.min_frequency = BMI_ACCEL_MIN_FREQ,
 		.max_frequency = BMI_ACCEL_MAX_FREQ,
 		.config = {
@@ -422,7 +429,8 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_base_mutex,
 		.drv_data = &g_bmi160_data,
 		.port = CONFIG_SPI_ACCEL_PORT,
-		.i2c_spi_addr_flags = SLAVE_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
+		.i2c_spi_addr_flags =
+				ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
 		.default_range = 1000, /* dps */
 		.rot_standard_ref = &base_standard_ref,
 		.min_frequency = BMI_GYRO_MIN_FREQ,
@@ -447,21 +455,24 @@ static void board_chipset_shutdown(void)
 }
 DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
 
-int board_get_charger_i2c(void)
+/* Called on AP S3 -> S0 transition, 5V DC-DC ctrl  */
+static void board_chipset_resume(void)
 {
-	/* TODO(b:138415463): confirm the bus allocation for future builds */
-	return board_get_version() == 1 ? 2 : 1;
+	/* Enable USM mode */
+	ioex_set_level(IOEX_5V_DC_DC_MODE_CTRL, 1);
 }
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
 
-/* Enable or disable input devices, based on chipset state and tablet mode */
-#ifndef TEST_BUILD
-void lid_angle_peripheral_enable(int enable)
+/* Called on AP S0 -> S3 transition */
+static void board_chipset_suspend(void)
 {
-	/* If the lid is in 360 position, ignore the lid angle,
-	 * which might be faulty. Disable keyboard.
-	 */
-	if (tablet_get_mode() || chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		enable = 0;
-	keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
+	/* Enable Normal mode */
+	ioex_set_level(IOEX_5V_DC_DC_MODE_CTRL, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
+
+int board_get_charger_i2c(void)
+{
+	/* TODO(b:138415463): confirm the bus allocation for future builds */
+	return board_get_version() == 1 ? 2 : 1;
 }
-#endif
diff --git a/board/cerise/board.h b/board/cerise/board.h
index 1ee3d931eb..cce105ae27 100644
--- a/board/cerise/board.h
+++ b/board/cerise/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,6 +11,7 @@
 #define VARIANT_KUKUI_JACUZZI
 #define VARIANT_KUKUI_BATTERY_SMART
 #define VARIANT_KUKUI_CHARGER_ISL9238
+#define VARIANT_KUKUI_EC_STM32F098
 
 #ifndef SECTION_IS_RW
 #define VARIANT_KUKUI_NO_SENSORS
@@ -18,6 +19,9 @@
 
 #include "baseboard.h"
 
+/* Disable deferred (async) flash protect*/
+#undef CONFIG_FLASH_PROTECT_DEFERRED
+
 #undef CONFIG_CHIPSET_POWER_SEQ_VERSION
 #define CONFIG_CHIPSET_POWER_SEQ_VERSION 1
 
@@ -27,6 +31,8 @@
 #define CONFIG_BATTERY_HW_PRESENT_CUSTOM
 
 #define CONFIG_CHARGER_PSYS
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 5
 
 #define CONFIG_CHARGER_RUNTIME_CONFIG
 
@@ -50,14 +56,13 @@
 #define CONFIG_USB_MUX_IT5205
 
 #define CONFIG_LED_ONOFF_STATES
-#define CONFIG_LED_POWER_LED
+#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
 #define CONFIG_LED_COMMON
 
 /* Motion Sensors */
 #ifndef VARIANT_KUKUI_NO_SENSORS
-#define CONFIG_ACCEL_LIS2DWL    /* Lid accel */
+#define CONFIG_ACCEL_LIS2DWL /* Lid accel */
 #define CONFIG_ACCELGYRO_BMI160 /* Base accel */
-#define CONFIG_ACCEL_INTERRUPTS
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 #define CONFIG_CMD_ACCEL_INFO
@@ -72,25 +77,24 @@
 #endif /* VARIANT_KUKUI_NO_SENSORS */
 
 /* I2C ports */
-#define I2C_PORT_BC12               0
-#define I2C_PORT_TCPC0              0
-#define I2C_PORT_USB_MUX            0
-#define I2C_PORT_BATTERY            2
-#define I2C_PORT_CHARGER            board_get_charger_i2c()
-#define I2C_PORT_SENSORS            1
-#define I2C_PORT_IO_EXPANDER_IT8801 1
-#define I2C_PORT_VIRTUAL_BATTERY    I2C_PORT_BATTERY
+#define I2C_PORT_BC12 0
+#define I2C_PORT_TCPC0 0
+#define I2C_PORT_USB_MUX 0
+#define I2C_PORT_BATTERY 2
+#define I2C_PORT_CHARGER board_get_charger_i2c()
+#define I2C_PORT_SENSORS 1
+#define I2C_PORT_KB_DISCRETE 1
+#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
+
+/* IT8801 I2C address */
+#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1
 
 /* Enable Accel over SPI */
-#define CONFIG_SPI_ACCEL_PORT    0  /* The first SPI master port (SPI2) */
+#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */
 
 #define CONFIG_KEYBOARD_PROTOCOL_MKBP
 #define CONFIG_MKBP_EVENT
 #define CONFIG_MKBP_USE_GPIO
-/* Define the MKBP events which are allowed to wakeup AP in S3. */
-#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \
-		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
 
 #ifndef __ASSEMBLER__
 
@@ -127,6 +131,13 @@ enum battery_type {
 	BATTERY_TYPE_COUNT,
 };
 
+enum BOARD_SKU_ID {
+	BOARD_SKU_ID_UNKNOWN = -1,
+	BOARD_SKU_ID_REV0 = 0,
+	BOARD_SKU_ID_REV1 = 1,
+	BOARD_SKU_ID_COUNT,
+};
+
 #include "gpio_signal.h"
 #include "registers.h"
 
@@ -138,7 +149,6 @@ void emmc_cmd_interrupt(enum gpio_signal signal);
 void bc12_interrupt(enum gpio_signal signal);
 void board_reset_pd_mcu(void);
 int board_get_version(void);
-int board_is_sourcing_vbus(int port);
 
 /* returns the i2c port number of charger */
 int board_get_charger_i2c(void);
diff --git a/board/cerise/build.mk b/board/cerise/build.mk
index a6e1c010d7..f583684804 100644
--- a/board/cerise/build.mk
+++ b/board/cerise/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/cerise/ec.tasklist b/board/cerise/ec.tasklist
index 36be2e96a4..e77603a8e2 100644
--- a/board/cerise/ec.tasklist
+++ b/board/cerise/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/cerise/gpio.inc b/board/cerise/gpio.inc
index 51972ec367..6edf1f1eab 100644
--- a/board/cerise/gpio.inc
+++ b/board/cerise/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -87,6 +87,8 @@ GPIO(USB_C0_DISCHARGE,     PIN(B, 6),  GPIO_OUT_LOW)
 IOEX(PWR_LED_WHITE_L,      EXPIN(0, 1, 4), GPIO_OUT_HIGH)
 IOEX(BAT_LED_WHITE_L,      EXPIN(0, 1, 3), GPIO_OUT_HIGH)
 IOEX(BAT_LED_AMBER_L,      EXPIN(0, 1, 2), GPIO_OUT_HIGH)
+IOEX(5V_DC_DC_MODE_CTRL,   EXPIN(0, 0, 7), GPIO_OUT_LOW)
+
 /*
  * TODO(b:138352732): On IT88801 expander, To be readded once IT8801 driver and
  * gpio expander framework has landed.
@@ -111,5 +113,5 @@ ALTERNATE(PIN_MASK(A, 0x8000), 0, MODULE_SPI,        0)
 /* EMMC SPI SLAVE: PB13/14/15 */
 ALTERNATE(PIN_MASK(B, 0xE000), 0, MODULE_SPI_FLASH,  0)
 /* SENSORS SPI MASTER: PB10, PB12, PC2, PC3 */
-ALTERNATE(PIN_MASK(B, 0x0400), 5, MODULE_SPI_MASTER, 0)
-ALTERNATE(PIN_MASK(C, 0x000C), 1, MODULE_SPI_MASTER, 0)
+ALTERNATE(PIN_MASK(B, 0x0400), 5, MODULE_SPI_CONTROLLER, 0)
+ALTERNATE(PIN_MASK(C, 0x000C), 1, MODULE_SPI_CONTROLLER, 0)
diff --git a/board/cerise/led.c b/board/cerise/led.c
index ff5f9f2373..622ab9feb6 100644
--- a/board/cerise/led.c
+++ b/board/cerise/led.c
@@ -1,50 +1,53 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Power and battery LED control for Damu
  */
 #include "common.h"
-#include "ioexpander.h"
 #include "driver/ioexpander/it8801.h"
 #include "ec_commands.h"
+#include "hooks.h"
+#include "ioexpander.h"
 #include "led_common.h"
 #include "led_onoff_states.h"
 
 #define LED_ON_LVL 0
 #define LED_OFF_LVL 1
 
-const int led_charge_lvl_1 = 5;
-const int led_charge_lvl_2 = 95;
+__override const int led_charge_lvl_1 = 5;
+__override const int led_charge_lvl_2 = 95;
 
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_WHITE,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
-const struct led_descriptor led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-	EC_LED_ID_BATTERY_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-void led_set_color_battery(enum ec_led_colors color)
+__override void led_set_color_battery(enum ec_led_colors color)
 {
 	switch (color) {
 	case EC_LED_COLOR_WHITE:
@@ -62,25 +65,11 @@ void led_set_color_battery(enum ec_led_colors color)
 	}
 }
 
-void led_set_color_power(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_WHITE:
-		ioex_set_level(IOEX_PWR_LED_WHITE_L, LED_ON_LVL);
-		break;
-	default:
-		ioex_set_level(IOEX_PWR_LED_WHITE_L, LED_OFF_LVL);
-		break;
-	}
-}
-
 void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
 {
 	if (led_id == EC_LED_ID_BATTERY_LED) {
 		brightness_range[EC_LED_COLOR_AMBER] = 1;
 		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
 	}
 }
 
@@ -93,11 +82,6 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 			led_set_color_battery(EC_LED_COLOR_WHITE);
 		else
 			led_set_color_battery(LED_OFF);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_power(LED_OFF);
 	} else {
 		return EC_ERROR_INVAL;
 	}
diff --git a/board/cerise/vif_override.xml b/board/cerise/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/cerise/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/cherry/battery.c b/board/cherry/battery.c
new file mode 100644
index 0000000000..4f3a12e43d
--- /dev/null
+++ b/board/cherry/battery.c
@@ -0,0 +1,126 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "battery_fuel_gauge.h"
+#include "battery_smart.h"
+
+const struct board_batt_params board_battery_info[] = {
+	/* Panasonic AP16L5J Battery Information */
+	[BATTERY_PANASONIC_AC16L5J] = {
+		.fuel_gauge = {
+			.manuf_name = "PANASONIC",
+			.device_name = "AP16L5J",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.reg_addr = 0x0,
+				.reg_mask = 0x4000,
+				.disconnect_val = 0x0,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 8800,
+			.voltage_normal		= 7700,
+			.voltage_min		= 6000,
+			.precharge_current	= 256,
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 75,
+		},
+	},
+	[BATTERY_PANASONIC_AC16L5J_KT00205009] = {
+		.fuel_gauge = {
+			.manuf_name = "PANASONIC KT00205009",
+			.device_name = "AP16L5J",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.reg_addr = 0x0,
+				.reg_mask = 0x4000,
+				.disconnect_val = 0x0,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 8800,
+			.voltage_normal		= 7700,
+			.voltage_min		= 6000,
+			.precharge_current	= 256,
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 75,
+		},
+	},
+	/* AP16L8J */
+	[BATTERY_AP16L8J] = {
+		.fuel_gauge = {
+			.manuf_name = "LGC KT0020G010",
+			.device_name = "AP16L8J",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0002,
+				.disconnect_val = 0x0,
+			}
+		},
+		.batt_info = {
+			.voltage_max            = 8700,
+			.voltage_normal         = 7500, /* mV */
+			.voltage_min            = 6000, /* mV */
+			.precharge_current      = 256,  /* mA */
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 50,
+			.charging_min_c         = 0,
+			.charging_max_c         = 60,
+			.discharging_min_c      = -20,
+			.discharging_max_c      = 75,
+		},
+	},
+	/* LGC AP18C8K Battery Information */
+	[BATTERY_LGC_AP18C8K] = {
+		.fuel_gauge = {
+			.manuf_name = "LGC KT0030G020",
+			.device_name = "AP18C8K",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.reg_addr = 0x43,
+				.reg_mask = 0x0001,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max		= 13050,
+			.voltage_normal		= 11250,
+			.voltage_min		= 9000,
+			.precharge_current	= 256,
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 75,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_PANASONIC_AC16L5J;
diff --git a/board/cherry/board.c b/board/cherry/board.c
new file mode 100644
index 0000000000..8d3faaf621
--- /dev/null
+++ b/board/cherry/board.c
@@ -0,0 +1,294 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* Cherry board configuration */
+
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "common.h"
+#include "console.h"
+#include "driver/accel_bma422.h"
+#include "driver/accel_kionix.h"
+#include "driver/accel_kx022.h"
+#include "driver/accelgyro_icm42607.h"
+#include "driver/accelgyro_icm_common.h"
+#include "driver/retimer/ps8802.h"
+#include "driver/usb_mux/anx3443.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "motion_sense.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "system.h"
+#include "usb_mux.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/* Sensor */
+static struct mutex g_base_mutex;
+static struct mutex g_lid_mutex;
+
+static struct icm_drv_data_t g_icm42607_data;
+static struct kionix_accel_data g_kx022_data;
+static struct accelgyro_saved_data_t g_bma422_data;
+
+/* Matrix to rotate accelrator into standard reference frame */
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					      { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
+
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
+
+struct motion_sensor_t motion_sensors[] = {
+	/*
+	 * Note: bmi160: supports accelerometer and gyro sensor
+	 * Requirement: accelerometer sensor must init before gyro sensor
+	 * DO NOT change the order of the following table.
+	 */
+	[BASE_ACCEL] = {
+		.name = "Base Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_ICM42607,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &icm42607_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = &g_icm42607_data,
+		.port = I2C_PORT_ACCEL,
+		.i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
+		.default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = ICM42607_ACCEL_MIN_FREQ,
+		.max_frequency = ICM42607_ACCEL_MAX_FREQ,
+		.config = {
+			/* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+			/* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+		},
+	},
+	[BASE_GYRO] = {
+		.name = "Base Gyro",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_ICM42607,
+		.type = MOTIONSENSE_TYPE_GYRO,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &icm42607_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = &g_icm42607_data,
+		.port = I2C_PORT_ACCEL,
+		.i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
+		.default_range = 1000, /* dps */
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = ICM42607_GYRO_MIN_FREQ,
+		.max_frequency = ICM42607_GYRO_MAX_FREQ,
+	},
+	[LID_ACCEL] = {
+		.name = "Lid Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_KX022,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &kionix_accel_drv,
+		.mutex = &g_lid_mutex,
+		.drv_data = &g_kx022_data,
+		.port = I2C_PORT_ACCEL,
+		.i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
+		.rot_standard_ref = &lid_standard_ref,
+		.default_range = 2, /* g, enough for laptop. */
+		.min_frequency = KX022_ACCEL_MIN_FREQ,
+		.max_frequency = KX022_ACCEL_MAX_FREQ,
+		.config = {
+			 /* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100,
+			},
+			/* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+		},
+	},
+};
+const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+struct motion_sensor_t bma422_lid_accel = {
+	.name = "Lid Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_BMA422,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_LID,
+	.drv = &bma4_accel_drv,
+	.mutex = &g_lid_mutex,
+	.drv_data = &g_bma422_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = BMA4_I2C_ADDR_PRIMARY,
+	.rot_standard_ref = &lid_standard_ref,
+	.min_frequency = BMA4_ACCEL_MIN_FREQ,
+	.max_frequency = BMA4_ACCEL_MAX_FREQ,
+	.default_range = 2, /* g, enough for laptop. */
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 12500 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+		/* Sensor on in S3 */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 12500 | ROUND_UP_FLAG,
+			.ec_rate = 0,
+		},
+	},
+};
+
+static void board_update_motion_sensor_config(void)
+{
+	if (system_get_board_version() >= 2) {
+		motion_sensors[LID_ACCEL] = bma422_lid_accel;
+		ccprints("LID ACCEL is BMA422");
+	} else {
+		ccprints("LID ACCEL is KX022");
+	}
+}
+
+/* PWM */
+
+/*
+ * PWM channels. Must be in the exactly same order as in enum pwm_channel.
+ * There total three 16 bits clock prescaler registers for all pwm channels,
+ * so use the same frequency and prescaler register setting is required if
+ * number of pwm channel greater than three.
+ */
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_LED1] = {
+		.channel = 0,
+		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
+		.freq_hz = 324, /* maximum supported frequency */
+		.pcfsr_sel = PWM_PRESCALER_C4,
+	},
+	[PWM_CH_LED2] = {
+		.channel = 1,
+		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
+		.freq_hz = 324, /* maximum supported frequency */
+		.pcfsr_sel = PWM_PRESCALER_C4,
+	},
+	[PWM_CH_LED3] = {
+		.channel = 2,
+		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
+		.freq_hz = 324, /* maximum supported frequency */
+		.pcfsr_sel = PWM_PRESCALER_C4,
+	},
+	[PWM_CH_KBLIGHT] = {
+		.channel = 3,
+		.freq_hz = 10000,
+		.pcfsr_sel = PWM_PRESCALER_C6,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+/* USB Mux */
+
+static int board_ps8762_mux_set(const struct usb_mux *me, mux_state_t mux_state)
+{
+	/* Make sure the PS8802 is awake */
+	RETURN_ERROR(ps8802_i2c_wake(me));
+
+	/* USB specific config */
+	if (mux_state & USB_PD_MUX_USB_ENABLED) {
+		/* Boost the USB gain */
+		RETURN_ERROR(ps8802_i2c_field_update16(
+			me, PS8802_REG_PAGE2, PS8802_REG2_USB_SSEQ_LEVEL,
+			PS8802_USBEQ_LEVEL_UP_MASK,
+			PS8802_USBEQ_LEVEL_UP_12DB));
+	}
+
+	/* DP specific config */
+	if (mux_state & USB_PD_MUX_DP_ENABLED) {
+		/* Boost the DP gain */
+		RETURN_ERROR(ps8802_i2c_field_update8(
+			me, PS8802_REG_PAGE2, PS8802_REG2_DPEQ_LEVEL,
+			PS8802_DPEQ_LEVEL_UP_MASK, PS8802_DPEQ_LEVEL_UP_12DB));
+	}
+
+	return EC_SUCCESS;
+}
+
+static int board_ps8762_mux_init(const struct usb_mux *me)
+{
+	return ps8802_i2c_field_update8(me, PS8802_REG_PAGE1, PS8802_REG_DCIRX,
+					PS8802_AUTO_DCI_MODE_DISABLE |
+						PS8802_FORCE_DCI_MODE,
+					PS8802_AUTO_DCI_MODE_DISABLE);
+}
+
+static int board_anx3443_mux_set(const struct usb_mux *me,
+				 mux_state_t mux_state)
+{
+	gpio_set_level(GPIO_USB_C1_DP_IN_HPD,
+		       mux_state & USB_PD_MUX_DP_ENABLED);
+	return EC_SUCCESS;
+}
+
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX0,
+				.i2c_addr_flags = PS8802_I2C_ADDR_FLAGS,
+				.driver = &ps8802_usb_mux_driver,
+				.board_init = &board_ps8762_mux_init,
+				.board_set = &board_ps8762_mux_set,
+			},
+	},
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_USB_MUX1,
+				.i2c_addr_flags = ANX3443_I2C_ADDR0_FLAGS,
+				.driver = &anx3443_usb_mux_driver,
+				.board_set = &board_anx3443_mux_set,
+			},
+	},
+};
+
+/* Initialize board. */
+static void board_init(void)
+{
+	/* Enable motion sensor interrupt */
+	gpio_enable_interrupt(GPIO_BASE_IMU_INT_L);
+	gpio_enable_interrupt(GPIO_LID_ACCEL_INT_L);
+
+	/* Disable PWM_CH_LED2(Green) for unuse */
+	pwm_enable(PWM_CH_LED2, 0);
+
+	board_update_motion_sensor_config();
+
+	if (board_get_version() >= 2) {
+		gpio_set_flags(GPIO_I2C_H_SCL, GPIO_INPUT | GPIO_PULL_DOWN);
+		gpio_set_flags(GPIO_I2C_H_SDA, GPIO_INPUT | GPIO_PULL_DOWN);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+static void board_do_chipset_resume(void)
+{
+	gpio_set_level(GPIO_EN_KB_BL, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_do_chipset_resume, HOOK_PRIO_DEFAULT);
+
+static void board_do_chipset_suspend(void)
+{
+	gpio_set_level(GPIO_EN_KB_BL, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_do_chipset_suspend, HOOK_PRIO_DEFAULT);
diff --git a/board/cherry/board.h b/board/cherry/board.h
new file mode 100644
index 0000000000..e15239dd64
--- /dev/null
+++ b/board/cherry/board.h
@@ -0,0 +1,107 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* Cherry board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "baseboard.h"
+
+/* Optional features */
+#define CONFIG_LTO
+#define CONFIG_PRESERVE_LOGS
+
+/*
+ * TODO: Remove this option once the VBAT no longer keeps high when
+ * system's power isn't presented.
+ */
+#define CONFIG_IT83XX_RESET_PD_CONTRACT_IN_BRAM
+
+/* BC12 */
+
+/* LED */
+#define CONFIG_LED_ONOFF_STATES
+#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
+
+/* PD / USB-C / PPC */
+#undef CONFIG_USB_PD_DEBUG_LEVEL /* default to 1, configurable in ec console \
+				  */
+
+/* Optional console commands */
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_SCRATCHPAD
+
+#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV 9000
+
+/* Keyboard */
+#define CONFIG_KEYBOARD_REFRESH_ROW3
+
+/* Sensor */
+#define CONFIG_GMR_TABLET_MODE
+#define CONFIG_TABLET_MODE
+#define CONFIG_TABLET_MODE_SWITCH
+
+/* ICM426XX Base accel/gyro */
+#define CONFIG_ACCELGYRO_ICM42607
+#define CONFIG_ACCELGYRO_ICM42607_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+/* KX022 Lid accel */
+#define CONFIG_ACCEL_KX022
+
+/* BMA422 Lid accel */
+#define CONFIG_ACCEL_BMA4XX
+
+#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
+
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+#define CONFIG_LID_ANGLE_UPDATE
+
+/* SPI / Host Command */
+#undef CONFIG_HOSTCMD_DEBUG_MODE
+#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
+
+/* USB-A */
+#define USBA_PORT_COUNT 1
+
+/* Temperature */
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_THERMISTOR
+#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum battery_type {
+	BATTERY_PANASONIC_AC16L5J,
+	BATTERY_PANASONIC_AC16L5J_KT00205009,
+	BATTERY_AP16L8J,
+	BATTERY_LGC_AP18C8K,
+	BATTERY_TYPE_COUNT,
+};
+
+enum sensor_id {
+	BASE_ACCEL = 0,
+	BASE_GYRO,
+	LID_ACCEL,
+	SENSOR_COUNT,
+};
+
+enum pwm_channel {
+	PWM_CH_LED1,
+	PWM_CH_LED2,
+	PWM_CH_LED3,
+	PWM_CH_KBLIGHT,
+	PWM_CH_COUNT,
+};
+
+int board_accel_force_mode_mask(void);
+
+#endif /* !__ASSEMBLER__ */
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/cherry/build.mk b/board/cherry/build.mk
new file mode 100644
index 0000000000..998e4d2750
--- /dev/null
+++ b/board/cherry/build.mk
@@ -0,0 +1,14 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+
+# the IC is ITE IT8xxx2
+CHIP:=it83xx
+CHIP_FAMILY:=it8xxx2
+CHIP_VARIANT:=it81202bx_1024
+BASEBOARD:=cherry
+
+board-y+=led.o battery.o board.o
diff --git a/board/cherry/ec.tasklist b/board/cherry/ec.tasklist
new file mode 100644
index 0000000000..5ce0fab583
--- /dev/null
+++ b/board/cherry/ec.tasklist
@@ -0,0 +1,23 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 1024) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(DPS, dps_task, NULL, 1280) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, 1280) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, 1280) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, 1024) \
+
diff --git a/board/cherry/gpio.inc b/board/cherry/gpio.inc
new file mode 100644
index 0000000000..b953b16b27
--- /dev/null
+++ b/board/cherry/gpio.inc
@@ -0,0 +1,164 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+/* Wake Source interrupts */
+GPIO_INT(POWER_BUTTON_L,     PIN(E, 4), GPIO_INT_BOTH | GPIO_PULL_UP |
+	 GPIO_HIB_WAKE_HIGH, power_button_interrupt) /* GSC_EC_PWR_BTN_ODL */
+GPIO_INT(LID_OPEN,           PIN(E, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,
+         lid_interrupt)
+GPIO_INT(TABLET_MODE_L,      PIN(J, 7), GPIO_INT_BOTH,
+         gmr_tablet_switch_isr)
+
+/* Chipset interrupts */
+GPIO_INT(AP_EC_WARM_RST_REQ, PIN(D, 3), GPIO_INT_RISING | GPIO_SEL_1P8V,
+         chipset_reset_request_interrupt)
+
+/* Power sequencing interrupts */
+GPIO_INT(AP_EC_WATCHDOG_L, PIN(C, 7), GPIO_INT_BOTH | GPIO_SEL_1P8V,
+         chipset_watchdog_interrupt)
+GPIO_INT(AP_IN_SLEEP_L, PIN(F, 2),
+         GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V, power_signal_interrupt)
+GPIO_INT(PMIC_EC_PWRGD, PIN(F, 3),
+         GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V, power_signal_interrupt)
+
+/* Sensor Interrupts */
+GPIO_INT(BASE_IMU_INT_L,     PIN(M, 3), GPIO_INT_FALLING | GPIO_SEL_1P8V,
+         icm42607_interrupt)
+/* USB-C interrupts */
+GPIO_INT(USB_C0_PPC_INT_ODL, PIN(D, 1), GPIO_INT_BOTH, ppc_interrupt)
+#ifdef BOARD_CHERRY
+GPIO_INT(USB_C0_BC12_INT_ODL,PIN(J, 4), GPIO_INT_FALLING, bc12_interrupt)
+#else /* TOMATO */
+GPIO_INT(USB_C0_BC12_INT_ODL,PIN(I, 5), GPIO_INT_FALLING, bc12_interrupt)
+#endif
+GPIO_INT(USB_C1_INT_ODL,     PIN(B, 2), GPIO_INT_FALLING, rt1718s_tcpc_interrupt)
+/* TODO: not used in other devices? */
+GPIO(LID_ACCEL_INT_L,        PIN(M, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V)
+
+/* Volume button interrupts */
+GPIO_INT(VOLUME_DOWN_L,      PIN(D, 5), GPIO_INT_BOTH | GPIO_PULL_UP,
+         button_interrupt) /* EC_VOLDN_BTN_ODL */
+GPIO_INT(VOLUME_UP_L,        PIN(D, 6), GPIO_INT_BOTH | GPIO_PULL_UP,
+         button_interrupt) /* EC_VOLUP_BTN_ODL */
+
+/* Other interrupts */
+GPIO_INT(AC_PRESENT,         PIN(E, 5), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,
+         extpower_interrupt) /* AC_OK / AC_PRESENT in rev1+ */
+GPIO_INT(UART1_RX,           PIN(B, 0), GPIO_INT_FALLING,
+         uart_deepsleep_interrupt) /* UART_DEBUG_TX_EC_RX */
+GPIO_INT(WP,                 PIN(I, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V,
+         switch_interrupt) /* EC_FLASH_WP_OD */
+GPIO_INT(SPI0_CS,            PIN(M, 5), GPIO_INT_FALLING,
+         spi_event)        /* SPI slave Chip Select -- AP_SPI_EC_CS_L */
+#ifndef BOARD_CHERRY
+GPIO_INT(AP_XHCI_INIT_DONE,  PIN(J, 5), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V,
+         xhci_init_done_interrupt)
+#endif
+
+/* Power Sequencing Signals */
+GPIO(EC_PMIC_EN_ODL,         PIN(D, 0), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(EC_PMIC_WATCHDOG_L,     PIN(H, 0), GPIO_ODR_LOW | GPIO_SEL_1P8V)
+GPIO(EN_PP5000_A,            PIN(C, 6), GPIO_OUT_HIGH)
+GPIO(PG_MT6315_PROC_B_ODL,   PIN(E, 1), GPIO_INPUT)
+GPIO(PG_MT6360_ODL,          PIN(F, 1), GPIO_INPUT)
+GPIO(EN_SLP_Z,               PIN(E, 3), GPIO_OUT_LOW)
+GPIO(SYS_RST_ODL,            PIN(B, 6), GPIO_ODR_LOW)
+GPIO(EC_BL_EN_OD,            PIN(B, 5), GPIO_ODR_LOW | GPIO_SEL_1P8V)
+
+/* MKBP event synchronization */
+GPIO(EC_INT_L,               PIN(E, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V) /* EC_AP_INT_ODL */
+
+/* USB and USBC Signals */
+GPIO(DP_PATH_SEL,            PIN(G, 0), GPIO_OUT_HIGH)
+GPIO(DP_DEMUX_EN,            PIN(G, 1), GPIO_OUT_LOW)
+GPIO(EC_AP_DP_HPD_ODL,       PIN(J, 0), GPIO_ODR_HIGH)
+GPIO(EN_PP5000_USB_A0_VBUS_X,PIN(B, 7), GPIO_OUT_LOW)
+GPIO(USB_C0_DP_IN_HPD,       PIN(H, 4), GPIO_OUT_LOW)
+GPIO(USB_C1_DP_IN_HPD,       PIN(J, 1), GPIO_OUT_LOW)
+GPIO(USB_C0_FRS_EN,          PIN(F, 0), GPIO_OUT_LOW)
+
+/* Misc Signals */
+GPIO(EN_KB_BL,               PIN(A, 6), GPIO_OUT_LOW)
+GPIO(EC_BATT_PRES_ODL,       PIN(C, 0), GPIO_INPUT)
+GPIO(EN_EC_ID_ODL,           PIN(H, 5), GPIO_ODR_LOW)
+GPIO(ENTERING_RW,            PIN(C, 5), GPIO_OUT_LOW) /* EC_ENTERING_RW */
+GPIO(EN_5V_USM,              PIN(G, 3), GPIO_OUT_LOW)
+GPIO(USB_A0_FAULT_ODL,       PIN(J, 6), GPIO_INPUT)
+GPIO(PACKET_MODE_EN,         PIN(D, 4), GPIO_OUT_LOW) /* EC_GSC_PACKET_MODE */
+
+/* I2C pins - Alternate function below configures I2C module on these pins */
+GPIO(I2C_A_SCL,              PIN(B, 3), GPIO_INPUT) /* I2C_CHG_BATT_SCL */
+GPIO(I2C_A_SDA,              PIN(B, 4), GPIO_INPUT) /* I2C_CHG_BATT_SDA */
+GPIO(I2C_B_SCL,              PIN(C, 1), GPIO_INPUT | GPIO_SEL_1P8V) /* I2C_SENSOR_SCL */
+GPIO(I2C_B_SDA,              PIN(C, 2), GPIO_INPUT | GPIO_SEL_1P8V) /* I2C_SENSOR_SDA */
+GPIO(I2C_C_SCL,              PIN(F, 6), GPIO_INPUT) /* I2C_USB_C0_SCL */
+GPIO(I2C_C_SDA,              PIN(F, 7), GPIO_INPUT) /* I2C_USB_C0_SDA */
+GPIO(I2C_E_SCL,              PIN(E, 0), GPIO_INPUT) /* I2C_USB_C1_SCL */
+GPIO(I2C_E_SDA,              PIN(E, 7), GPIO_INPUT) /* I2C_USB_C1_SDA */
+GPIO(I2C_F_SCL,              PIN(A, 4), GPIO_INPUT) /* Rev 2+ I2C_PROG_SCL */
+GPIO(I2C_F_SDA,              PIN(A, 5), GPIO_INPUT) /* Rev 2+ I2C_PROG_SDA */
+GPIO(I2C_H_SCL,              PIN(H, 1), GPIO_INPUT) /* Rev 0,1 I2C_PROG_SCL */
+GPIO(I2C_H_SDA,              PIN(H, 2), GPIO_INPUT) /* Rev 0,1 I2C_PROG_SDA */
+
+/* Alternate functions GPIO definitions */
+ALTERNATE(PIN_MASK(B, 0x18), 1, MODULE_I2C, 0) /* I2C A */
+ALTERNATE(PIN_MASK(C, 0x06), 1, MODULE_I2C, GPIO_SEL_1P8V) /* I2C B */
+ALTERNATE(PIN_MASK(F, 0xC0), 1, MODULE_I2C, 0) /* I2C C */
+ALTERNATE(PIN_MASK(E, 0x81), 1, MODULE_I2C, 0) /* I2C E */
+
+/* UART */
+ALTERNATE(PIN_MASK(B, 0x03), 1, MODULE_UART, 0) /* EC to Servo */
+
+/* PWM */
+ALTERNATE(PIN_MASK(A, 0b1111), 1, MODULE_PWM, 0) /* PWM 0,1,2,3 */
+
+/* ADC */
+ALTERNATE(PIN_MASK(I, 0b11001001), 0, MODULE_ADC, 0) /* ADC 0,3,6,7 */
+
+/* SPI */
+ALTERNATE(PIN_MASK(M, 0x33), 0, MODULE_SPI, 0) /* SPI */
+
+/* Unimplemented Pins  */
+GPIO(PG_PP5000_S5_OD,        PIN(D, 2), GPIO_INPUT)
+/* *_ODL pin has external pullup so don't pull it down. */
+GPIO(PG_MT6315_GPU_ODL,      PIN(H, 6), GPIO_INPUT)
+/* reserved for future use */
+GPIO(CCD_MODE_ODL,           PIN(C, 4), GPIO_INPUT)
+/*
+ * ADC pins don't have internal pull-down capability,
+ * so we set them as output low.
+ */
+#ifdef BOARD_CHERRY
+GPIO(NC_GPI5,                PIN(I, 5), GPIO_OUT_LOW)
+#else
+GPIO(NC_GPJ4,                PIN(J, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+#endif
+/* NC pins, enable internal pull-up/down to avoid floating state. */
+GPIO(NC_GPA1,                PIN(A, 1), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(PWM7,                   PIN(A, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(EC_NVME_PLN_ODL,        PIN(D, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(SPI_CLK_GPG6,           PIN(G, 6), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(PG_NVME_OD,             PIN(H, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(EN_PP2500_NVME_X,       PIN(J, 2), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(EN_PP1200_NVME_X,       PIN(J, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(NC_GPM6,                PIN(M, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+/*
+ * These pins don't have internal pull-down capability,
+ * so we set them as output low.
+ */
+GPIO(SPI_MOSI_GPG4,          PIN(G, 4), GPIO_OUT_LOW)
+GPIO(SPI_MISO_GPG5,          PIN(G, 5), GPIO_OUT_LOW)
+GPIO(SPI_CS_GPG7,            PIN(G, 7), GPIO_OUT_LOW)
+GPIO(EC_ID0,                 PIN(I, 1), GPIO_OUT_LOW)
+GPIO(EC_ID1,                 PIN(I, 2), GPIO_OUT_LOW)
+
+/* Other unused pins */
+GPIO(NVME_EC_PLA_S3_ODL,     PIN(I, 7), GPIO_INPUT)
+
diff --git a/board/cherry/led.c b/board/cherry/led.c
new file mode 100644
index 0000000000..0607301d4c
--- /dev/null
+++ b/board/cherry/led.c
@@ -0,0 +1,96 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "chipset.h"
+#include "common.h"
+#include "gpio.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+#include "pwm.h"
+
+#define LED_OFF_LVL 0
+#define LED_ON_LVL 1
+
+__override const int led_charge_lvl_1 = 5;
+__override const int led_charge_lvl_2 = 95;
+
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_S5] = { { EC_LED_COLOR_BLUE,
+					       LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_BATTERY_LED,
+};
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_AMBER:
+		pwm_enable(PWM_CH_LED1, LED_ON_LVL);
+		pwm_enable(PWM_CH_LED3, LED_OFF_LVL);
+		break;
+	case EC_LED_COLOR_BLUE:
+		pwm_enable(PWM_CH_LED1, LED_OFF_LVL);
+		pwm_enable(PWM_CH_LED3, LED_ON_LVL);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		pwm_enable(PWM_CH_LED1, LED_OFF_LVL);
+		pwm_enable(PWM_CH_LED3, LED_OFF_LVL);
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	brightness_range[EC_LED_COLOR_AMBER] = 1;
+	brightness_range[EC_LED_COLOR_BLUE] = 1;
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (brightness[EC_LED_COLOR_AMBER] != 0)
+		led_set_color_battery(EC_LED_COLOR_AMBER);
+	else if (brightness[EC_LED_COLOR_BLUE] != 0)
+		led_set_color_battery(EC_LED_COLOR_BLUE);
+	else
+		led_set_color_battery(LED_OFF);
+	return EC_SUCCESS;
+}
+
+__override enum led_states board_led_get_state(enum led_states desired_state)
+{
+	if (desired_state == STATE_BATTERY_ERROR) {
+		if (chipset_in_state(CHIPSET_STATE_ON))
+			return desired_state;
+		else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
+			return STATE_DISCHARGE_S3;
+		else
+			return STATE_DISCHARGE_S5;
+	}
+	return desired_state;
+}
diff --git a/board/cherry/vif_override.xml b/board/cherry/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/cherry/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/cherry_scp/board.h b/board/cherry_scp/board.h
new file mode 100644
index 0000000000..28c9d8cc5e
--- /dev/null
+++ b/board/cherry_scp/board.h
@@ -0,0 +1,33 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Cherry SCP configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "baseboard.h"
+
+/*
+ * RW only, no flash
+ * +-------------------- 0x0
+ * | ROM vectortable, .text, .rodata, .data LMA
+ * +-------------------- 0x6f000
+ * | RAM .bss, .data
+ * +-------------------- 0xbfc00
+ * | Reserved (padding for 1k-alignment)
+ * +-------------------- 0xbfdb0
+ * | IPI shared buffer with AP (288 + 8) * 2
+ * +-------------------- 0xc0000
+ */
+#define CONFIG_ROM_BASE 0x0
+#define CONFIG_RAM_BASE 0x6f000
+#define CONFIG_ROM_SIZE (CONFIG_RAM_BASE - CONFIG_ROM_BASE)
+#define CONFIG_RAM_SIZE \
+	((CONFIG_IPC_SHARED_OBJ_ADDR & (~(0x400 - 1))) - CONFIG_RAM_BASE)
+
+#define SCP_FW_END 0xc0000
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/cherry_scp/build.mk b/board/cherry_scp/build.mk
new file mode 100644
index 0000000000..498bee2848
--- /dev/null
+++ b/board/cherry_scp/build.mk
@@ -0,0 +1,11 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=mt_scp
+CHIP_VARIANT:=mt8195
+BASEBOARD:=mtscp-rv32i
diff --git a/board/cherry_scp/ec.tasklist b/board/cherry_scp/ec.tasklist
new file mode 100644
index 0000000000..353e5ee686
--- /dev/null
+++ b/board/cherry_scp/ec.tasklist
@@ -0,0 +1,18 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(VDEC_SERVICE, vdec_service_task, NULL, 4096) \
+	TASK_ALWAYS(VDEC_CORE_SERVICE, vdec_core_service_task, NULL, 4096) \
+	TASK_ALWAYS(VENC_SERVICE, venc_service_task, NULL, TRENTA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MDP_SERVICE, mdp_service_task, NULL, 4096) \
+	TASK_ALWAYS(SR, sr_task, NULL, TASK_STACK_SIZE)
diff --git a/board/cherry_scp/gpio.inc b/board/cherry_scp/gpio.inc
new file mode 100644
index 0000000000..8301fb437f
--- /dev/null
+++ b/board/cherry_scp/gpio.inc
@@ -0,0 +1,10 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Unimplemented signals which we need to emulate for now */
+UNIMPLEMENTED(ENTERING_RW)
+UNIMPLEMENTED(WP_L)
diff --git a/board/cheza/base_detect.c b/board/cheza/base_detect.c
deleted file mode 100644
index 3999ad022f..0000000000
--- a/board/cheza/base_detect.c
+++ /dev/null
@@ -1,216 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Lux base without battery detection code */
-
-#include "adc.h"
-#include "adc_chip.h"
-#include "board.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-
-/* Base detection and debouncing */
-#define BASE_DETECT_DEBOUNCE_US (20 * MSEC)
-
-/*
- * If the base status is unclear (i.e. not within expected ranges, read
- * the ADC value again every 500ms.
- */
-#define BASE_DETECT_RETRY_US (500 * MSEC)
-
-/*
- * When base is disconnected, and gets connected:
- * Lid has 1M pull-up, base has 200K pull-down, so the ADC
- * value should be around 200/(200+1000)*3300 = 550.
- *
- * Idle value should be ~3300: lid has 1M pull-up, and nothing else (i.e. ADC
- * maxing out at 2813).
- */
-#define BASE_DISCONNECTED_CONNECT_MIN_MV 450
-#define BASE_DISCONNECTED_CONNECT_MAX_MV 650
-
-#define BASE_DISCONNECTED_MIN_MV 2800
-#define BASE_DISCONNECTED_MAX_MV (ADC_MAX_VOLT+1)
-
-/*
- * When base is connected, then gets disconnected:
- * Lid has 1M pull-up, lid has 10.0K pull-down, so the ADC
- * value should be around 10.0/(10.0+1000)*3300 = 33.
- *
- * Idle level when connected should be:
- * Lid has 10K pull-down, base has 5.1K pull-up, so the ADC value should be
- * around 10.0/(10.0+5.1)*3300 = 2185 (actual value is 2153 as there is still
- * a 1M pull-up on lid, and 200K pull-down on base).
- */
-#define BASE_CONNECTED_DISCONNECT_MIN_MV 20
-#define BASE_CONNECTED_DISCONNECT_MAX_MV 45
-
-#define BASE_CONNECTED_MIN_MV 2050
-#define BASE_CONNECTED_MAX_MV 2300
-
-static uint64_t base_detect_debounce_time;
-
-static void base_detect_deferred(void);
-DECLARE_DEFERRED(base_detect_deferred);
-
-enum base_status {
-	BASE_UNKNOWN = 0,
-	BASE_DISCONNECTED = 1,
-	BASE_CONNECTED = 2,
-};
-
-static enum base_status current_base_status;
-
-/*
- * This function is called whenever there is a change in the base detect
- * status. Actions taken include:
- * 1. Enable/disable pull-down on half-duplex UART line
- * 2. Enable/disable power to base.
- * 3. Indicate mode change to host.
- * 4. Indicate tablet mode to host. Current assumption is that if base is
- * disconnected then the system is in tablet mode, else if the base is
- * connected, then the system is not in tablet mode.
- */
-static void base_detect_change(enum base_status status)
-{
-	int connected = (status == BASE_CONNECTED);
-
-	if (current_base_status == status)
-		return;
-
-	current_base_status = status;
-
-	/* Enable pull-down if connected. */
-	gpio_set_level(GPIO_EN_CC_LID_BASE_PULLDN, !connected);
-
-	/* We don't enable dual-battery support. Set the base power directly. */
-	gpio_set_level(GPIO_EN_PPVAR_VAR_BASE, connected);
-
-	tablet_set_mode(!connected);
-}
-
-static void print_base_detect_value(const char *str, int v)
-{
-	CPRINTS("Base %s. ADC: %d", str, v);
-}
-
-static void base_detect_deferred(void)
-{
-	uint64_t time_now = get_time().val;
-	int v;
-
-	if (base_detect_debounce_time > time_now) {
-		hook_call_deferred(&base_detect_deferred_data,
-				   base_detect_debounce_time - time_now);
-		return;
-	}
-
-	v = adc_read_channel(ADC_BASE_DET);
-	if (v == ADC_READ_ERROR)
-		goto retry;
-
-	if (current_base_status == BASE_CONNECTED) {
-		if (v >= BASE_CONNECTED_DISCONNECT_MIN_MV &&
-		    v <= BASE_CONNECTED_DISCONNECT_MAX_MV) {
-			print_base_detect_value("disconnected", v);
-			base_detect_change(BASE_DISCONNECTED);
-			return;
-		} else if (v >= BASE_CONNECTED_MIN_MV &&
-			   v <= BASE_CONNECTED_MAX_MV) {
-			/* Still connected. */
-			return;
-		}
-	} else { /* Disconnected or unknown. */
-		if (v >= BASE_DISCONNECTED_CONNECT_MIN_MV &&
-		    v <= BASE_DISCONNECTED_CONNECT_MAX_MV) {
-			print_base_detect_value("connected", v);
-			base_detect_change(BASE_CONNECTED);
-			return;
-		} else if (v >= BASE_DISCONNECTED_MIN_MV &&
-			   v <= BASE_DISCONNECTED_MAX_MV) {
-			if (current_base_status == BASE_UNKNOWN) {
-				print_base_detect_value("disconnected", v);
-				base_detect_change(BASE_DISCONNECTED);
-			}
-			/* Still disconnected. */
-			return;
-		}
-	}
-
-retry:
-	print_base_detect_value("status unclear", v);
-	/* Unclear base status, schedule again in a while. */
-	hook_call_deferred(&base_detect_deferred_data,
-				   BASE_DETECT_RETRY_US);
-}
-
-void base_detect_interrupt(enum gpio_signal signal)
-{
-	uint64_t time_now = get_time().val;
-
-	if (base_detect_debounce_time <= time_now)
-		hook_call_deferred(&base_detect_deferred_data,
-				   BASE_DETECT_DEBOUNCE_US);
-
-	base_detect_debounce_time = time_now + BASE_DETECT_DEBOUNCE_US;
-}
-
-static void base_detect_enable(void)
-{
-	/* Enable base detection interrupt. */
-	base_detect_debounce_time = get_time().val;
-	hook_call_deferred(&base_detect_deferred_data, 0);
-	gpio_enable_interrupt(GPIO_CC_LID_BASE_ADC);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, base_detect_enable, HOOK_PRIO_DEFAULT);
-
-static void base_detect_disable(void)
-{
-	/* Disable base detection interrupt and disable power to base. */
-	gpio_disable_interrupt(GPIO_CC_LID_BASE_ADC);
-	base_detect_change(BASE_DISCONNECTED);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, base_detect_disable, HOOK_PRIO_DEFAULT);
-
-static void base_init(void)
-{
-	/*
-	 * Make sure base power and pull-down are off. This will reset the base
-	 * if it is already connected.
-	 */
-	gpio_set_level(GPIO_EN_PPVAR_VAR_BASE, 0);
-	gpio_set_level(GPIO_EN_CC_LID_BASE_PULLDN, 1);
-}
-DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT+1);
-
-void base_force_state(int state)
-{
-	if (state == 1) {
-		gpio_disable_interrupt(GPIO_CC_LID_BASE_ADC);
-		base_detect_change(BASE_CONNECTED);
-		CPRINTS("BD forced connected");
-	} else if (state == 0) {
-		gpio_disable_interrupt(GPIO_CC_LID_BASE_ADC);
-		base_detect_change(BASE_DISCONNECTED);
-		CPRINTS("BD forced disconnected");
-	} else {
-		hook_call_deferred(&base_detect_deferred_data, 0);
-		gpio_enable_interrupt(GPIO_CC_LID_BASE_ADC);
-		CPRINTS("BD forced reset");
-	}
-}
diff --git a/board/cheza/battery.c b/board/cheza/battery.c
deleted file mode 100644
index ab98864a9a..0000000000
--- a/board/cheza/battery.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery.h"
-#include "battery_smart.h"
-
-/* Shutdown mode parameter to write to manufacturer access register */
-#define SB_SHIP_MODE_REG	SB_MANUFACTURER_ACCESS
-#define SB_SHUTDOWN_DATA	0x0010
-
-/* Battery info */
-static const struct battery_info info = {
-	.voltage_max = 8800,
-	.voltage_normal = 7700,
-	.voltage_min = 6000,
-	.precharge_current = 256, /* mA */
-	.start_charging_min_c = 0,
-	.start_charging_max_c = 45,
-	.charging_min_c = 0,
-	.charging_max_c = 45,
-	.discharging_min_c = -10,
-	.discharging_max_c = 60,
-};
-
-const struct battery_info *battery_get_info(void)
-{
-	return &info;
-}
-
-int board_cut_off_battery(void)
-{
-	int rv;
-
-	/* Ship mode command must be sent twice to take effect */
-	rv = sb_write(SB_SHIP_MODE_REG, SB_SHUTDOWN_DATA);
-
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	return sb_write(SB_SHIP_MODE_REG, SB_SHUTDOWN_DATA);
-}
diff --git a/board/cheza/board.c b/board/cheza/board.c
deleted file mode 100644
index d8901bc845..0000000000
--- a/board/cheza/board.c
+++ /dev/null
@@ -1,706 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Cheza board-specific configuration */
-
-#include "adc_chip.h"
-#include "als.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "extpower.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/als_opt3001.h"
-#include "driver/charger/isl923x.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/tcpm/anx74xx.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "lid_switch.h"
-#include "pi3usb9281.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "system.h"
-#include "shi_chip.h"
-#include "switch.h"
-#include "task.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#define USB_PD_PORT_ANX3429	0
-#define USB_PD_PORT_PS8751	1
-
-/* Forward declaration */
-static void tcpc_alert_event(enum gpio_signal signal);
-static void vbus0_evt(enum gpio_signal signal);
-static void vbus1_evt(enum gpio_signal signal);
-static void usb0_evt(enum gpio_signal signal);
-static void usb1_evt(enum gpio_signal signal);
-static void ppc_interrupt(enum gpio_signal signal);
-static void anx74xx_cable_det_interrupt(enum gpio_signal signal);
-static void usb1_oc_evt(enum gpio_signal signal);
-
-#include "gpio_list.h"
-
-/* GPIO Interrupt Handlers */
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_PD_INT_ODL:
-		port = 0;
-		break;
-	case GPIO_USB_C1_PD_INT_ODL:
-		port = 1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-static void vbus0_evt(enum gpio_signal signal)
-{
-	/* VBUS present GPIO is inverted */
-	usb_charger_vbus_change(0, !gpio_get_level(GPIO_USB_C0_VBUS_DET_L));
-	task_wake(TASK_ID_PD_C0);
-}
-
-static void vbus1_evt(enum gpio_signal signal)
-{
-	/* VBUS present GPIO is inverted */
-	usb_charger_vbus_change(1, !gpio_get_level(GPIO_USB_C1_VBUS_DET_L));
-	task_wake(TASK_ID_PD_C1);
-}
-
-static void usb0_evt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
-}
-
-static void usb1_evt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12, 0);
-}
-
-static void anx74xx_cable_det_handler(void)
-{
-	int cable_det = gpio_get_level(GPIO_USB_C0_CABLE_DET);
-	int reset_n = gpio_get_level(GPIO_USB_C0_PD_RST_R_L);
-
-	/*
-	 * A cable_det low->high transition was detected. If following the
-	 * debounce time, cable_det is high, and reset_n is low, then ANX3429 is
-	 * currently in standby mode and needs to be woken up. Set the
-	 * TCPC_RESET event which will bring the ANX3429 out of standby
-	 * mode. Setting this event is gated on reset_n being low because the
-	 * ANX3429 will always set cable_det when transitioning to normal mode
-	 * and if in normal mode, then there is no need to trigger a tcpc reset.
-	 */
-	if (cable_det && !reset_n)
-		task_set_event(TASK_ID_PD_C0, PD_EVENT_TCPC_RESET, 0);
-}
-DECLARE_DEFERRED(anx74xx_cable_det_handler);
-
-static void anx74xx_cable_det_interrupt(enum gpio_signal signal)
-{
-	/* debounce for 2 msec */
-	hook_call_deferred(&anx74xx_cable_det_handler_data, (2 * MSEC));
-}
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
-	/* Only port-0 uses PPC chip */
-	sn5s330_interrupt(0);
-}
-
-static void usb1_oc_evt_deferred(void)
-{
-	/* Only port-1 has overcurrent GPIO interrupt */
-	board_overcurrent_event(1, 1);
-}
-DECLARE_DEFERRED(usb1_oc_evt_deferred);
-
-static void usb1_oc_evt(enum gpio_signal signal)
-{
-	/* Switch the context to handle the event */
-	hook_call_deferred(&usb1_oc_evt_deferred_data, 0);
-}
-
-/* Wake-up pins for hibernate */
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_LID_OPEN,
-	GPIO_AC_PRESENT,
-	GPIO_POWER_BUTTON_L,
-	GPIO_EC_RST_ODL,
-};
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	/* Base detection */
-	[ADC_BASE_DET] = {
-		"BASE_DET",
-		NPCX_ADC_CH0,
-		ADC_MAX_VOLT,
-		ADC_READ_MAX + 1,
-		0
-	},
-	/* Measure VBUS through a 1/10 voltage divider */
-	[ADC_VBUS] = {
-		"VBUS",
-		NPCX_ADC_CH1,
-		ADC_MAX_VOLT * 10,
-		ADC_READ_MAX + 1,
-		0
-	},
-	/*
-	 * Adapter current output or battery charging/discharging current (uV)
-	 * 18x amplification on charger side.
-	 */
-	[ADC_AMON_BMON] = {
-		"AMON_BMON",
-		NPCX_ADC_CH2,
-		ADC_MAX_VOLT * 1000 / 18,
-		ADC_READ_MAX + 1,
-		0
-	},
-	/*
-	 * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read
-	 * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and
-	 * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we
-	 * only divide by 2 (enough to avoid precision issues).
-	 */
-	[ADC_PSYS] = {
-		"PSYS",
-		NPCX_ADC_CH3,
-		ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1),
-		2,
-		0
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct pwm_t pwm_channels[] = {
-	/* TODO(waihong): Assign a proper frequency. */
-	[PWM_CH_DISPLIGHT] = { 5, 0, 4800 },
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-
-/* Power signal list. Must match order of enum power_signal. */
-const struct power_signal_info power_signal_list[] = {
-	[SDM845_AP_RST_ASSERTED] = {
-		GPIO_AP_RST_L,
-		POWER_SIGNAL_ACTIVE_LOW | POWER_SIGNAL_DISABLE_AT_BOOT,
-		"AP_RST_ASSERTED"},
-	[SDM845_PS_HOLD] = {
-		GPIO_PS_HOLD,
-		POWER_SIGNAL_ACTIVE_HIGH,
-		"PS_HOLD"},
-	[SDM845_PMIC_FAULT_L] = {
-		GPIO_PMIC_FAULT_L,
-		POWER_SIGNAL_ACTIVE_HIGH | POWER_SIGNAL_DISABLE_AT_BOOT,
-		"PMIC_FAULT_L"},
-	[SDM845_POWER_GOOD] = {
-		GPIO_POWER_GOOD,
-		POWER_SIGNAL_ACTIVE_HIGH,
-		"POWER_GOOD"},
-	[SDM845_WARM_RESET] = {
-		GPIO_WARM_RESET_L,
-		POWER_SIGNAL_ACTIVE_HIGH,
-		"WARM_RESET_L"},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-/* I2C port map */
-const struct i2c_port_t i2c_ports[] = {
-	{"power",   I2C_PORT_POWER,  100, GPIO_I2C0_SCL,  GPIO_I2C0_SDA},
-	/* TODO(b/78189419): ANX7428 operates at 400kHz initially. */
-	{"tcpc0",   I2C_PORT_TCPC0,  400, GPIO_I2C1_SCL,  GPIO_I2C1_SDA},
-	{"tcpc1",   I2C_PORT_TCPC1, 1000, GPIO_I2C2_SCL,  GPIO_I2C2_SDA},
-	{"eeprom",  I2C_PORT_EEPROM, 400, GPIO_I2C5_SCL,  GPIO_I2C5_SDA},
-	{"sensor",  I2C_PORT_SENSOR, 400, GPIO_I2C7_SCL,  GPIO_I2C7_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* Power Path Controller */
-struct ppc_config_t ppc_chips[] = {
-	{
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	/*
-	 * Port 1 uses two power switches instead:
-	 *   NX5P3290: to source VBUS
-	 *   NX20P5090: to sink VBUS (charge battery)
-	 * which are controlled directly by EC GPIOs.
-	 */
-};
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/* TCPC mux configuration */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	/* Alert is active-low, open-drain */
-	[USB_PD_PORT_ANX3429] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = 0x28,
-		},
-		.drv = &anx74xx_tcpm_drv,
-		.flags = TCPC_FLAGS_ALERT_OD,
-	},
-	[USB_PD_PORT_PS8751] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC1,
-			.addr_flags = 0x0B,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-/*
- * Port-0 USB mux driver.
- *
- * The USB mux is handled by TCPC chip and the HPD is handled by AP.
- * Redirect to anx74xx_tcpm_usb_mux_driver but override the get() function
- * to check the HPD_IRQ mask from virtual_usb_mux_driver.
- */
-static int port0_usb_mux_init(const struct usb_mux *me)
-{
-	return anx74xx_tcpm_usb_mux_driver.init(me);
-}
-
-static int port0_usb_mux_set(const struct usb_mux *me, mux_state_t mux_state)
-{
-	return anx74xx_tcpm_usb_mux_driver.set(me, mux_state);
-}
-
-static int port0_usb_mux_get(const struct usb_mux *me, mux_state_t *mux_state)
-{
-	int rv;
-	mux_state_t virtual_mux_state;
-
-	rv = anx74xx_tcpm_usb_mux_driver.get(me, mux_state);
-	rv |= virtual_usb_mux_driver.get(me, &virtual_mux_state);
-
-	if (virtual_mux_state & USB_PD_MUX_HPD_IRQ)
-		*mux_state |= USB_PD_MUX_HPD_IRQ;
-	return rv;
-}
-
-const struct usb_mux_driver port0_usb_mux_driver = {
-	.init = port0_usb_mux_init,
-	.set = port0_usb_mux_set,
-	.get = port0_usb_mux_get,
-};
-
-/*
- * Port-1 USB mux driver.
- *
- * The USB mux is handled by TCPC chip and the HPD is handled by AP.
- * Redirect to tcpci_tcpm_usb_mux_driver but override the get() function
- * to check the HPD_IRQ mask from virtual_usb_mux_driver.
- */
-static int port1_usb_mux_init(const struct usb_mux *me)
-{
-	return tcpci_tcpm_usb_mux_driver.init(me);
-}
-
-static int port1_usb_mux_set(const struct usb_mux *me, mux_state_t mux_state)
-{
-	return tcpci_tcpm_usb_mux_driver.set(me, mux_state);
-}
-
-static int port1_usb_mux_get(const struct usb_mux *me, mux_state_t *mux_state)
-{
-	int rv;
-	mux_state_t virtual_mux_state;
-
-	rv = tcpci_tcpm_usb_mux_driver.get(me, mux_state);
-	rv |= virtual_usb_mux_driver.get(me, &virtual_mux_state);
-
-	if (virtual_mux_state & USB_PD_MUX_HPD_IRQ)
-		*mux_state |= USB_PD_MUX_HPD_IRQ;
-	return rv;
-}
-
-static int port1_usb_mux_enter_low_power(const struct usb_mux *me)
-{
-	return tcpci_tcpm_usb_mux_driver.enter_low_power_mode(me);
-}
-
-const struct usb_mux_driver port1_usb_mux_driver = {
-	.init = &port1_usb_mux_init,
-	.set = &port1_usb_mux_set,
-	.get = &port1_usb_mux_get,
-	.enter_low_power_mode = &port1_usb_mux_enter_low_power,
-};
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.driver = &port0_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-	},
-	{
-		.usb_port = 1,
-		.driver = &port1_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-	}
-};
-
-/* BC1.2 */
-struct pi3usb9281_config pi3usb9281_chips[] = {
-	{
-		.i2c_port = I2C_PORT_POWER,
-	},
-	{
-		.i2c_port = I2C_PORT_EEPROM,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9281_chips) ==
-	     CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT);
-
-/* Initialize board. */
-static void board_init(void)
-{
-	/* Enable BC1.2 VBUS detection */
-	gpio_enable_interrupt(GPIO_USB_C0_VBUS_DET_L);
-	gpio_enable_interrupt(GPIO_USB_C1_VBUS_DET_L);
-
-	/* Enable BC1.2 interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_L);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L);
-
-	/* Enable interrupt for BMI160 sensor */
-	gpio_enable_interrupt(GPIO_ACCEL_GYRO_INT_L);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-void board_tcpc_init(void)
-{
-	/* Only reset TCPC if not sysjump */
-	if (!system_jumped_late()) {
-		/* TODO(crosbug.com/p/61098): How long do we need to wait? */
-		board_reset_pd_mcu();
-	}
-
-	/* Enable PPC interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_SWCTL_INT_ODL);
-
-	/* Enable TCPC interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL);
-
-	/* Enable CABLE_DET interrupt for ANX3429 wake from standby */
-	gpio_enable_interrupt(GPIO_USB_C0_CABLE_DET);
-
-	/*
-	 * Initialize HPD to low; after sysjump SOC needs to see
-	 * HPD pulse to enable video path
-	 */
-	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		usb_mux_hpd_update(port, 0, 0);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
-
-/* Called on AP S0 -> S3 transition */
-static void board_chipset_suspend(void)
-{
-	/*
-	 * Turn off display backlight in S3. AP has its own control. The EC's
-	 * and the AP's will be AND'ed together in hardware.
-	 */
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S0 transition */
-static void board_chipset_resume(void)
-{
-	/* Turn on display backlight in S0. */
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S5 -> S3 transition */
-static void board_chipset_startup(void)
-{
-	gpio_set_flags(GPIO_USB_C1_OC_ODL, GPIO_INT_FALLING | GPIO_PULL_UP);
-	gpio_enable_interrupt(GPIO_USB_C1_OC_ODL);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S5 transition */
-static void board_chipset_shutdown(void)
-{
-	/* 5V is off in S5. Disable pull-up to prevent current leak. */
-	gpio_disable_interrupt(GPIO_USB_C1_OC_ODL);
-	gpio_set_flags(GPIO_USB_C1_OC_ODL, GPIO_INT_FALLING);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
-
-/**
- * Power on (or off) a single TCPC.
- * minimum on/off delays are included.
- *
- * @param port  Port number of TCPC.
- * @param mode  0: power off, 1: power on.
- */
-void board_set_tcpc_power_mode(int port, int mode)
-{
-	if (port != USB_PD_PORT_ANX3429)
-		return;
-
-	if (mode) {
-		gpio_set_level(GPIO_EN_USB_C0_TCPC_PWR, 1);
-		msleep(ANX74XX_PWR_H_RST_H_DELAY_MS);
-		gpio_set_level(GPIO_USB_C0_PD_RST_R_L, 1);
-	} else {
-		gpio_set_level(GPIO_USB_C0_PD_RST_R_L, 0);
-		msleep(ANX74XX_RST_L_PWR_L_DELAY_MS);
-		gpio_set_level(GPIO_EN_USB_C0_TCPC_PWR, 0);
-		msleep(ANX74XX_PWR_L_PWR_H_DELAY_MS);
-	}
-}
-
-void board_reset_pd_mcu(void)
-{
-	/* Assert reset */
-	gpio_set_level(GPIO_USB_C0_PD_RST_R_L, 0);
-	gpio_set_level(GPIO_USB_C1_PD_RST_ODL, 0);
-
-	msleep(MAX(1, ANX74XX_RST_L_PWR_L_DELAY_MS));
-	gpio_set_level(GPIO_USB_C1_PD_RST_ODL, 1);
-	/* Disable TCPC0 (anx3429) power */
-	gpio_set_level(GPIO_EN_USB_C0_TCPC_PWR, 0);
-
-	msleep(ANX74XX_PWR_L_PWR_H_DELAY_MS);
-	board_set_tcpc_power_mode(USB_PD_PORT_ANX3429, 1);
-}
-
-int board_vbus_sink_enable(int port, int enable)
-{
-	if (port == USB_PD_PORT_ANX3429) {
-		/* Port 0 is controlled by a PPC SN5S330 */
-		return ppc_vbus_sink_enable(port, enable);
-	} else if (port == USB_PD_PORT_PS8751) {
-		/* Port 1 is controlled by a power switch NX20P5090 */
-		gpio_set_level(GPIO_EN_USB_C1_CHARGE_EC_L, !enable);
-		return EC_SUCCESS;
-	}
-	return EC_ERROR_INVAL;
-}
-
-int board_is_sourcing_vbus(int port)
-{
-	if (port == USB_PD_PORT_ANX3429) {
-		/* Port 0 is controlled by a PPC SN5S330 */
-		return ppc_is_sourcing_vbus(port);
-	} else if (port == USB_PD_PORT_PS8751) {
-		/* Port 1 is controlled by a power switch NX5P3290 */
-		return gpio_get_level(GPIO_EN_USB_C1_5V_OUT);
-	}
-	return EC_ERROR_INVAL;
-}
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* TODO(b/120231371): Notify AP */
-	CPRINTS("p%d: overcurrent!", port);
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	int i;
-	int rv;
-
-	if (!is_real_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	CPRINTS("New chg p%d", port);
-
-	if (port == CHARGE_PORT_NONE) {
-		/* Disable all ports. */
-		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-			rv = board_vbus_sink_enable(i, 0);
-			if (rv) {
-				CPRINTS("Disabling p%d sink path failed.", i);
-				return rv;
-			}
-		}
-
-		return EC_SUCCESS;
-	}
-
-	/* Check if the port is sourcing VBUS. */
-	if (board_is_sourcing_vbus(port)) {
-		CPRINTF("Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		if (i == port)
-			continue;
-
-		if (board_vbus_sink_enable(i, 0))
-			CPRINTS("p%d: sink path disable failed.", i);
-	}
-
-	/* Enable requested charge port. */
-	if (board_vbus_sink_enable(port, 1)) {
-		CPRINTS("p%d: sink path enable failed.", port);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	/*
-	 * Ignore lower charge ceiling on PD transition if our battery is
-	 * critical, as we may brownout.
-	 */
-	if (supplier == CHARGE_SUPPLIER_PD &&
-	    charge_ma < 1500 &&
-	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
-		CPRINTS("Using max ilim %d", max_ma);
-		charge_ma = max_ma;
-	}
-
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
-		if (gpio_get_level(GPIO_USB_C0_PD_RST_R_L))
-			status |= PD_STATUS_TCPC_ALERT_0;
-	if (!gpio_get_level(GPIO_USB_C1_PD_INT_ODL))
-		if (gpio_get_level(GPIO_USB_C1_PD_RST_ODL))
-			status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
-/* Mutexes */
-static struct mutex g_lid_mutex;
-
-static struct bmi_drv_data_t g_bmi160_data;
-static struct opt3001_drv_data_t g_opt3001_data = {
-	.scale = 1,
-	.uscale = 0,
-	.offset = 0,
-};
-
-/* Matrix to rotate accelerometer into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0,  0},
-	{ 0,  FLOAT_TO_FP(-1),  0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	/*
-	 * Note: bmi160: supports accelerometer and gyro sensor
-	 * Requirement: accelerometer sensor must init before gyro sensor
-	 * DO NOT change the order of the following table.
-	 */
-	[LID_ACCEL] = {
-	 .name = "Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3_S5,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .rot_standard_ref = &base_standard_ref,
-	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	 .min_frequency = BMI_ACCEL_MIN_FREQ,
-	 .max_frequency = BMI_ACCEL_MAX_FREQ,
-	 .config = {
-		 [SENSOR_CONFIG_EC_S0] = {
-			 .odr = 10000 | ROUND_UP_FLAG,
-		 },
-	 },
-	},
-	[LID_GYRO] = {
-	 .name = "Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3_S5,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &base_standard_ref,
-	 .min_frequency = BMI_GYRO_MIN_FREQ,
-	 .max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-	[LID_ALS] = {
-	 .name = "Light",
-	 .active_mask = SENSOR_ACTIVE_S0,
-	 .chip = MOTIONSENSE_CHIP_OPT3001,
-	 .type = MOTIONSENSE_TYPE_LIGHT,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &opt3001_drv,
-	 .drv_data = &g_opt3001_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = OPT3001_I2C_ADDR_FLAGS,
-	 .rot_standard_ref = NULL,
-	 .default_range = 0x10000, /* scale = 1; uscale = 0 */
-	 .min_frequency = OPT3001_LIGHT_MIN_FREQ,
-	 .max_frequency = OPT3001_LIGHT_MAX_FREQ,
-	 .config = {
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 1000,
-		},
-	 },
-	},
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
diff --git a/board/cheza/board.h b/board/cheza/board.h
deleted file mode 100644
index 23a6b9f81a..0000000000
--- a/board/cheza/board.h
+++ /dev/null
@@ -1,229 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Cheza board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* TODO(waihong): Remove the following bringup features */
-#define CONFIG_BRINGUP
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands. */
-#define CONFIG_USB_PD_DEBUG_LEVEL 3
-#define CONFIG_CMD_AP_RESET_LOG
-#define CONFIG_HOSTCMD_AP_RESET
-
-/*
- * By default, enable all console messages excepted event and HC:
- * The sensor stack is generating a lot of activity.
- * They can be enabled through the console command 'chan'.
- */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_HOSTCMD)))
-
-/* NPCX7 config */
-#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
-#define NPCX_TACH_SEL2    0  /* No tach. */
-#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
-
-/* Internal SPI flash on NPCX7 */
-#define CONFIG_FLASH_SIZE (1024 * 1024)  /* 1MB internal spi flash */
-#define CONFIG_SPI_FLASH_REGS
-#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
-#define CONFIG_HOSTCMD_FLASH_SPI_INFO
-
-/* EC Modules */
-#define CONFIG_I2C
-#define CONFIG_I2C_MASTER
-#define CONFIG_LED_COMMON
-#define CONFIG_LOW_POWER_IDLE
-#define CONFIG_ADC
-#define CONFIG_BACKLIGHT_LID
-#define CONFIG_FPU
-#define CONFIG_PWM
-#define CONFIG_PWM_DISPLIGHT
-
-#define CONFIG_VBOOT_HASH
-
-#define CONFIG_DETACHABLE_BASE
-
-#undef CONFIG_PECI
-
-#define CONFIG_HOSTCMD_SPS
-#define CONFIG_HOST_COMMAND_STATUS
-#define CONFIG_HOSTCMD_SECTION_SORTED /* Host commands are sorted. */
-#define CONFIG_MKBP_EVENT
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
-#define CONFIG_MKBP_USE_GPIO
-
-#define CONFIG_BOARD_VERSION_GPIO
-#define CONFIG_POWER_BUTTON
-#define CONFIG_VOLUME_BUTTONS
-#define CONFIG_BUTTON_TRIGGERED_RECOVERY
-#define CONFIG_EMULATED_SYSRQ
-#define CONFIG_CMD_BUTTON
-#define CONFIG_SWITCH
-#define CONFIG_LID_SWITCH
-#define CONFIG_EXTPOWER_GPIO
-
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-
-/* Battery */
-#define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BATT_PRES_ODL
-#define CONFIG_BATTERY_SMART
-
-/* Charger */
-#define CONFIG_CHARGER
-#define CONFIG_CHARGE_MANAGER
-#define CONFIG_CHARGER_ISL9238
-#define CONFIG_CHARGE_RAMP_HW
-#define CONFIG_USB_CHARGER
-#define CONFIG_CMD_CHARGER_ADC_AMON_BMON
-#define CONFIG_CHARGER_PSYS
-#define CONFIG_CHARGER_PSYS_READ
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-
-#define CONFIG_CHARGER_INPUT_CURRENT 512
-#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 2
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 7500
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20
-
-/* BC 1.2 Charger */
-#define CONFIG_BC12_DETECT_PI3USB9281
-#define CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT 2
-
-/* USB */
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV1
-#define CONFIG_HOSTCMD_PD_CONTROL
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_DISCHARGE_PPC
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT TYPEC_RP_3A0
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-#define CONFIG_USB_PD_TCPM_ANX3429
-#define CONFIG_USB_PD_TCPM_PS8751
-#define CONFIG_USB_PD_TCPM_MUX
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_PD_VBUS_DETECT_CHARGER
-#define CONFIG_USB_PD_5V_EN_CUSTOM
-#define CONFIG_USB_MUX_VIRTUAL
-#define CONFIG_USBC_PPC_SN5S330
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-
-/* RTC */
-#define CONFIG_CMD_RTC
-#define CONFIG_HOSTCMD_RTC
-
-/* Sensors */
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
-/* Enable sensor fifo, must also define the _SIZE and _THRES */
-#define CONFIG_ACCEL_FIFO
-/* FIFO size is a power of 2. */
-#define CONFIG_ACCEL_FIFO_SIZE 256
-/* Depends on how fast the AP boots and typical ODRs. */
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-#define CONFIG_ALS
-#define CONFIG_ALS_OPT3001
-#define ALS_COUNT 1
-#define OPT3001_I2C_ADDR_FLAGS OPT3001_I2C_ADDR1_FLAGS
-
-/* PD */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY   30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY  250000 /* us */
-#define PD_VCONN_SWAP_DELAY             5000 /* us */
-
-#define PD_OPERATING_POWER_MW   15000
-#define PD_MAX_POWER_MW         ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
-#define PD_MAX_CURRENT_MA       3000
-#define PD_MAX_VOLTAGE_MV       20000
-
-/* Chipset */
-#define CONFIG_CHIPSET_SDM845
-#define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_POWER_COMMON
-#define CONFIG_POWER_PP5000_CONTROL
-
-/* NPCX Features */
-#define CONFIG_HIBERNATE_PSL
-
-/* I2C Ports */
-#define I2C_PORT_BATTERY I2C_PORT_POWER
-#define I2C_PORT_CHARGER I2C_PORT_POWER
-#define I2C_PORT_ACCEL   I2C_PORT_SENSOR
-#define I2C_PORT_POWER   NPCX_I2C_PORT0_0
-#define I2C_PORT_TCPC0   NPCX_I2C_PORT1_0
-#define I2C_PORT_TCPC1   NPCX_I2C_PORT2_0
-#define I2C_PORT_EEPROM  NPCX_I2C_PORT5_0
-#define I2C_PORT_SENSOR  NPCX_I2C_PORT7_0
-
-/* GPIO alias */
-#define GPIO_PMIC_RESIN_L GPIO_PM845_RESIN_L
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum power_signal {
-	SDM845_AP_RST_ASSERTED = 0,
-	SDM845_PS_HOLD,
-	SDM845_PMIC_FAULT_L,
-	SDM845_POWER_GOOD,
-	SDM845_WARM_RESET,
-	/* Number of power signals */
-	POWER_SIGNAL_COUNT
-};
-
-enum adc_channel {
-	ADC_BASE_DET,
-	ADC_VBUS,
-	ADC_AMON_BMON,
-	ADC_PSYS,
-	ADC_CH_COUNT
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL = 0,
-	LID_GYRO,
-	LID_ALS,
-	SENSOR_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_DISPLIGHT,
-	PWM_CH_COUNT
-};
-
-/* Custom function to indicate if sourcing VBUS */
-int board_is_sourcing_vbus(int port);
-/* Enable VBUS sink for a given port */
-int board_vbus_sink_enable(int port, int enable);
-/* Reset all TCPCs. */
-void board_reset_pd_mcu(void);
-/* Base detection interrupt handler */
-void base_detect_interrupt(enum gpio_signal signal);
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ALS)
-
-#endif /* !defined(__ASSEMBLER__) */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/cheza/build.mk b/board/cheza/build.mk
deleted file mode 100644
index 2e8e53ec88..0000000000
--- a/board/cheza/build.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-# -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m7wb
-
-board-y=battery.o board.o led.o usb_pd_policy.o base_detect.o
diff --git a/board/cheza/ec.tasklist b/board/cheza/ec.tasklist
deleted file mode 100644
index ef70197bac..0000000000
--- a/board/cheza/ec.tasklist
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/cheza/gpio.inc b/board/cheza/gpio.inc
deleted file mode 100644
index bc9d12ad79..0000000000
--- a/board/cheza/gpio.inc
+++ /dev/null
@@ -1,169 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_PD_INT_ODL,    PIN(A, 0), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-0 TCPC */
-GPIO_INT(USB_C1_PD_INT_ODL,    PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-1 TCPC */
-GPIO_INT(USB_C0_SWCTL_INT_ODL, PIN(0, 3), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-0 PPC */
-GPIO_INT(USB_C0_BC12_INT_L,    PIN(6, 1), GPIO_INT_FALLING, usb0_evt)  /* Interrupt from port-0 BC1.2 */
-GPIO_INT(USB_C1_BC12_INT_L,    PIN(8, 2), GPIO_INT_FALLING, usb1_evt)  /* Interrupt from port-1 BC1.2 */
-GPIO_INT(USB_C0_VBUS_DET_L,    PIN(6, 2), GPIO_INT_BOTH | GPIO_PULL_UP, vbus0_evt)  /* BC1.2 VBUS detection on port-0 */
-GPIO_INT(USB_C1_VBUS_DET_L,    PIN(8, 3), GPIO_INT_BOTH | GPIO_PULL_UP, vbus1_evt)  /* BC1.2 VBUS detection on port-1 */
-GPIO_INT(USB_C0_CABLE_DET,     PIN(3, 7), GPIO_INT_RISING, anx74xx_cable_det_interrupt)  /* Cable detection from port-0 TCPC */
-GPIO_INT(USB_C1_OC_ODL,        PIN(7, 2), GPIO_INT_FALLING, usb1_oc_evt)  /* Port-1 power switch over-current */
-GPIO_INT(ACCEL_GYRO_INT_L,     PIN(D, 3), GPIO_INT_FALLING | GPIO_SEL_1P8V, bmi160_interrupt)  /* Accelerometer/gyro interrupt */
-
-/* System interrupts */
-GPIO_INT(AC_PRESENT,        PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt) /* ACOK_OD */
-GPIO_INT(POWER_BUTTON_L,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)  /* EC_PWR_BTN_ODL */
-GPIO_INT(VOLUME_DOWN_L,     PIN(7, 0), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* EC_VOLDN_BTN_ODL */
-GPIO_INT(VOLUME_UP_L,       PIN(F, 2), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* EC_VOLUP_BTN_ODL */
-GPIO_INT(WP_L,              PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)  /* EC_WP_ODL */
-GPIO_INT(LID_OPEN,          PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)  /* LID_OPEN_EC */
-GPIO_INT(AP_RST_REQ,        PIN(C, 2), GPIO_INT_RISING | GPIO_PULL_DOWN | GPIO_SEL_1P8V, chipset_reset_request_interrupt)  /* Reset request from AP */
-GPIO_INT(AP_RST_L,          PIN(C, 1), GPIO_INT_BOTH | GPIO_SEL_1P8V, power_signal_interrupt)
-GPIO_INT(PS_HOLD,           PIN(D, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V, power_signal_interrupt)  /* Indicate when AP triggers reset/shutdown */
-GPIO_INT(PMIC_FAULT_L,      PIN(7, 6), GPIO_INT_BOTH | GPIO_SEL_1P8V, power_signal_interrupt)  /* Any PMIC fault? */
-/*
- * When switch-cap is off, the POWER_GOOD signal is floating. Need a pull-down
- * to make it low. Overload the interrupt function chipset_warm_reset_interrupt
- * for not only signalling power_signal_interrupt but also handling the logic
- * of WARM_RESET_L which is pulled-up by the same rail of POWER_GOOD.
- */
-GPIO_INT(POWER_GOOD,        PIN(5, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, chipset_warm_reset_interrupt)  /* SRC_PP1800_S4A from PMIC */
-GPIO_INT(WARM_RESET_L,      PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_warm_reset_interrupt)  /* AP warm reset */
-GPIO_INT(SHI_CS_L,          PIN(5, 3), GPIO_INT_FALLING | GPIO_PULL_DOWN, shi_cs_event)  /* AP_EC_SPI_CS_L */
-GPIO_INT(CC_LID_BASE_ADC,   PIN(4, 5), GPIO_INT_BOTH, base_detect_interrupt)  /* Base detection */
-
-/*
- * EC_RST_ODL acts as a wake source from PSL hibernate mode. However, it does
- * not need to be an interrupt for normal EC operations. Thus, configure it as
- * GPIO_INT_BOTH with wake on low-to-high edge using GPIO_HIB_WAKE_HIGH so that
- * PSL common code can configure PSL_IN correctly.
- *
- * Use the rising edge to wake EC up. If we chose the falling edge, it would
- * still wake EC up, but EC is in an intermediate state until the signal goes
- * back to high.
- */
-GPIO(EC_RST_ODL,            PIN(0, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH)  /* Wake source: EC reset */
-GPIO(ENTERING_RW,           PIN(E, 1), GPIO_OUT_LOW)   /* EC_ENTERING_RW: Indicate when EC is entering RW code */
-GPIO(CCD_MODE_ODL,          PIN(E, 3), GPIO_INPUT)     /* Case Closed Debug Mode */
-GPIO(BATT_PRES_ODL,         PIN(E, 5), GPIO_INPUT)     /* EC_BATT_PRES_ODL: Battery Present */
-GPIO(PROCHOT_L,             PIN(3, 4), GPIO_INPUT)
-
-/* PMIC/AP 1.8V */
-GPIO(PM845_RESIN_L,         PIN(3, 2), GPIO_ODR_HIGH | GPIO_SEL_1P8V)  /* PMIC reset trigger */
-GPIO(PMIC_KPD_PWR_ODL,      PIN(D, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V)  /* PMIC power button */
-GPIO(EC_INT_L,              PIN(A, 2), GPIO_ODR_HIGH)  /* Interrupt line between AP and EC */
-GPIO(AP_SUSPEND_L,          PIN(5, 7), GPIO_INPUT)     /* Suspend signal from AP */
-
-/* Power enables */
-GPIO(SWITCHCAP_ON_L,        PIN(D, 5), GPIO_OUT_LOW)   /* Enable switch cap. XXX: It's active-high */
-GPIO(VBOB_EN,               PIN(9, 5), GPIO_OUT_LOW)   /* Enable VBOB */
-GPIO(EN_PP3300_A,           PIN(A, 6), GPIO_OUT_LOW)   /* Enable PP3300 */
-GPIO(EN_PP5000,             PIN(6, 7), GPIO_OUT_LOW)   /* EN_PP5000_A: Enable PP5000 */
-GPIO(ENABLE_BACKLIGHT,      PIN(B, 6), GPIO_OUT_LOW)   /* EC_BL_DISABLE_L: Backlight disable signal from EC */
-
-/* Sensors */
-GPIO(ALS_INT_L,             PIN(5, 0), GPIO_INPUT)     /* ALS sensor interrupt */
-GPIO(P_SENSOR_INT_L,        PIN(F, 3), GPIO_INPUT | GPIO_SEL_1P8V) /* P-sensor interrupt */
-GPIO(RCAM_VSYNC,            PIN(4, 0), GPIO_INPUT | GPIO_SEL_1P8V) /* VSYNC from rear camera */
-
-/* Base */
-GPIO(EN_PPVAR_VAR_BASE,     PIN(0, 4), GPIO_OUT_LOW)   /* Power to the base */
-GPIO(EN_CC_LID_BASE_PH,     PIN(D, 1), GPIO_ODR_HIGH)
-GPIO(EN_CC_LID_BASE_PULLDN, PIN(D, 0), GPIO_ODR_HIGH)
-GPIO(REVERSE_DOCK_EC,       PIN(C, 6), GPIO_INPUT)     /* Indicate if the dock is reversed */
-GPIO(CC_LID_RX_BASE_TX,     PIN(7, 5), GPIO_INPUT)
-GPIO(CC_LID_RX_BASE_RX,     PIN(8, 6), GPIO_INPUT)
-
-/* LEDs */
-GPIO(CHG_LED_Y_C0,          PIN(C, 3), GPIO_OUT_LOW)   /* EC_CHG_LED_Y_C0 */
-GPIO(CHG_LED_W_C0,          PIN(C, 4), GPIO_OUT_LOW)   /* EC_CHG_LED_W_C0 */
-GPIO(CHG_LED_Y_C1,          PIN(6, 0), GPIO_OUT_LOW)   /* EC_CHG_LED_Y_C1 */
-GPIO(CHG_LED_W_C1,          PIN(C, 0), GPIO_OUT_LOW)   /* EC_CHG_LED_W_C1 */
-
-/*
- * USB HS muxes
- *
- *               C0_MUX:D ----- C0_BC12 ---- C0_PORT
- * AP --+------- C0_MUX:D1
- *      |   +--- C0_MUX:D2
- *      |   |
- *      |   |
- *      |   |    C1_MUX:D ----- C1_BC12 ---- C1_PORT
- *      |   | +- C1_MUX:D1
- *      +------- C1_MUX:D2
- *          | |
- * AP --- USB_HUB
- */
-/* Switch both port-0 and port-1 to the hub, which matches the SS path. */
-GPIO(USB_C0_HS_MUX_OE_L,    PIN(A, 4), GPIO_OUT_LOW)
-GPIO(USB_C0_HS_MUX_SEL,     PIN(A, 3), GPIO_OUT_HIGH)  /* L:D1(AP), H:D2(hub) */
-GPIO(USB_C1_HS_MUX_OE_L,    PIN(7, 3), GPIO_OUT_LOW)
-GPIO(USB_C1_HS_MUX_SEL,     PIN(7, 4), GPIO_OUT_LOW)   /* L:D1(hub), H:D2(AP) */
-
-/* USB-C port-0 controls */
-GPIO(USB_C0_PD_RST_R_L,     PIN(F, 1), GPIO_OUT_HIGH)  /* Port-0 TCPC chip reset */
-GPIO(EN_USB_C0_TCPC_PWR,    PIN(C, 5), GPIO_OUT_LOW)   /* Port-0 TCPC power enable */
-
-/* USB-C port-1 controls */
-GPIO(USB_C1_PD_RST_ODL,     PIN(E, 4), GPIO_ODR_HIGH)  /* Port-1 TCPC chip reset */
-GPIO(EN_USB_C1_5V_OUT,      PIN(6, 3), GPIO_OUT_LOW)   /* Port-1 power switch 5V output */
-GPIO(EN_USB_C1_3A,          PIN(5, 6), GPIO_OUT_LOW)   /* Port-1 power switch 3A current */
-GPIO(EN_USB_C1_CHARGE_EC_L, PIN(B, 1), GPIO_OUT_LOW)   /* Port-1 enable charging */
-GPIO(USBC_MUX_CONF1,        PIN(5, 1), GPIO_OUT_HIGH)  /* Port-1 enable DP switch */
-
-/* USB-C port-1 interrupts */
-GPIO(USB_C1_DP_HPD,         PIN(9, 6), GPIO_INPUT)     /* DP HPD from port-1 TCPC */
-
-/* I2C */
-GPIO(I2C0_SCL,              PIN(B, 5), GPIO_INPUT)     /* EC_I2C_POWER_SCL */
-GPIO(I2C0_SDA,              PIN(B, 4), GPIO_INPUT)     /* EC_I2C_POWER_SDA */
-GPIO(I2C1_SCL,              PIN(9, 0), GPIO_INPUT)     /* EC_I2C_USB_C0_PD_SCL */
-GPIO(I2C1_SDA,              PIN(8, 7), GPIO_INPUT)     /* EC_I2C_USB_C0_PD_SDA */
-GPIO(I2C2_SCL,              PIN(9, 2), GPIO_INPUT)     /* EC_I2C_USB_C1_PD_SCL */
-GPIO(I2C2_SDA,              PIN(9, 1), GPIO_INPUT)     /* EC_I2C_USB_C1_PD_SDA */
-GPIO(I2C5_SCL,              PIN(3, 3), GPIO_INPUT)     /* EC_I2C_EEPROM_SCL */
-GPIO(I2C5_SDA,              PIN(3, 6), GPIO_INPUT)     /* EC_I2C_EEPROM_SDA */
-GPIO(I2C7_SCL,              PIN(B, 3), GPIO_INPUT |
-                                       GPIO_SEL_1P8V)  /* EC_I2C_SENSOR_SCL */
-GPIO(I2C7_SDA,              PIN(B, 2), GPIO_INPUT |
-                                       GPIO_SEL_1P8V)  /* EC_I2C_SENSOR_SDA */
-
-/* Board/SKU IDs */
-GPIO(BOARD_VERSION1,        PIN(C, 7), GPIO_INPUT)     /* BRD_ID1 */
-GPIO(BOARD_VERSION2,        PIN(9, 3), GPIO_INPUT)     /* BRD_ID2 */
-GPIO(BOARD_VERSION3,        PIN(8, 0), GPIO_INPUT)     /* BRD_ID3 */
-GPIO(SKU_ID1,               PIN(F, 0), GPIO_INPUT)
-GPIO(SKU_ID2,               PIN(4, 1), GPIO_INPUT)
-
-/* Switchcap */
-/*
- * GPIO0 is configured as PVC_PG. When the chip in power down mode, it outputs
- * high-Z. Set pull-down to avoid floating.
- */
-GPIO(DA9313_GPIO0,          PIN(E, 2), GPIO_INPUT | GPIO_PULL_DOWN) /* Switchcap GPIO0 */
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)            /* UART (GPIO64/65) */
-ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0)             /* I2C0 (GPIOB4/B5) */
-ALTERNATE(PIN_MASK(9, 0x07), 1, MODULE_I2C, 0)             /* I2C1 SDA (GPIO90), I2C2 (GPIO91/92) */
-ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, 0)             /* I2C1 SCL (GPIO87) */
-ALTERNATE(PIN_MASK(3, 0x48), 1, MODULE_I2C, 0)             /* I2C5 (GPIO33/36) */
-ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, GPIO_SEL_1P8V) /* I2C7 (GPIOB2/B3) - 1.8V */
-ALTERNATE(PIN_MASK(4, 0x1C), 0, MODULE_ADC, 0)             /* ADC1 (GPIO44), ADC2 (GPIO43), ADC3 (GPIO42) */
-ALTERNATE(PIN_MASK(4, 0xC0), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SDO (GPIO47), SHI_SDI (GPIO46) */
-ALTERNATE(PIN_MASK(5, 0x28), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SCLK (GPIO55), SHI_CS# (GPIO53) */
-ALTERNATE(PIN_MASK(B, 0x80), 1, MODULE_PWM, 0)             /* PWM5 (GPIOB7) */
-ALTERNATE(PIN_MASK(D, 0x04), 1, MODULE_PMU, 0)             /* PSL_IN1 (GPIOD2) - LID_OPEN_EC */
-ALTERNATE(PIN_MASK(0, 0x01), 1, MODULE_PMU, 0)             /* PSL_IN2 (GPIO00) - ACOK_OD */
-ALTERNATE(PIN_MASK(0, 0x02), 1, MODULE_PMU, 0)             /* PSL_IN3 (GPIO01) - EC_PWR_BTN_ODL */
-ALTERNATE(PIN_MASK(0, 0x04), 1, MODULE_PMU, 0)             /* PSL_IN4 (GPIO02) - EC_RST_ODL */
diff --git a/board/cheza/led.c b/board/cheza/led.c
deleted file mode 100644
index 21ca78cb5c..0000000000
--- a/board/cheza/led.c
+++ /dev/null
@@ -1,163 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control.
- */
-
-#include "battery.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "led_common.h"
-#include "system.h"
-#include "util.h"
-
-#define BAT_LED_ON 1
-#define BAT_LED_OFF 0
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_RIGHT_LED,
-	EC_LED_ID_LEFT_LED,
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_AMBER,
-	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
-};
-
-static void side_led_set_color(int port, enum led_color color)
-{
-	gpio_set_level(port ? GPIO_CHG_LED_Y_C1 : GPIO_CHG_LED_Y_C0,
-		(color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
-	gpio_set_level(port ? GPIO_CHG_LED_W_C1 : GPIO_CHG_LED_W_C0,
-		(color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF);
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_AMBER] = 1;
-	brightness_range[EC_LED_COLOR_WHITE] = 1;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	int port;
-
-	switch (led_id) {
-	case EC_LED_ID_RIGHT_LED:
-		port = 0;
-		break;
-	case EC_LED_ID_LEFT_LED:
-		port = 1;
-		break;
-	default:
-		return EC_ERROR_PARAM1;
-	}
-
-	if (brightness[EC_LED_COLOR_WHITE] != 0)
-		side_led_set_color(port, LED_WHITE);
-	else if (brightness[EC_LED_COLOR_AMBER] != 0)
-		side_led_set_color(port, LED_AMBER);
-	else
-		side_led_set_color(port, LED_OFF);
-
-	return EC_SUCCESS;
-}
-
-/*
- * Set active charge port color to the parameter, turn off all others.
- * If no port is active (-1), turn off all LEDs.
- */
-static void set_active_port_color(enum led_color color)
-{
-	int port = charge_manager_get_active_charge_port();
-
-	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
-		side_led_set_color(0, (port == 0) ? color : LED_OFF);
-	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
-		side_led_set_color(1, (port == 1) ? color : LED_OFF);
-}
-
-static void board_led_set_battery(void)
-{
-	static int battery_ticks;
-	uint32_t chflags = charge_get_flags();
-
-	battery_ticks++;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		/* Always indicate when charging, even in suspend. */
-		set_active_port_color(LED_AMBER);
-		break;
-	case PWR_STATE_DISCHARGE:
-		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
-			if (charge_get_percent() <= 10)
-				side_led_set_color(0,
-				   (battery_ticks & 0x4) ? LED_WHITE : LED_OFF);
-			else
-				side_led_set_color(0, LED_OFF);
-		}
-
-		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
-			side_led_set_color(1, LED_OFF);
-		break;
-	case PWR_STATE_ERROR:
-		set_active_port_color((battery_ticks & 0x2) ?
-				LED_WHITE : LED_OFF);
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		set_active_port_color(LED_WHITE);
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			set_active_port_color((battery_ticks & 0x4) ?
-					LED_AMBER : LED_OFF);
-		else
-			set_active_port_color(LED_WHITE);
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-}
-
-/* Called by hook task every TICK */
-static void led_tick(void)
-{
-	board_led_set_battery();
-}
-DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
-
-void led_control(enum ec_led_id led_id, enum ec_led_state state)
-{
-	enum led_color color;
-
-	if ((led_id != EC_LED_ID_RECOVERY_HW_REINIT_LED) &&
-	    (led_id != EC_LED_ID_SYSRQ_DEBUG_LED))
-		return;
-
-	if (state == LED_STATE_RESET) {
-		led_auto_control(EC_LED_ID_LEFT_LED, 1);
-		led_auto_control(EC_LED_ID_RIGHT_LED, 1);
-		board_led_set_battery();
-		return;
-	}
-
-	color = state ? LED_WHITE : LED_OFF;
-
-	led_auto_control(EC_LED_ID_LEFT_LED, 0);
-	led_auto_control(EC_LED_ID_RIGHT_LED, 0);
-
-	side_led_set_color(0, color);
-	side_led_set_color(1, color);
-}
diff --git a/board/cheza/usb_pd_policy.c b/board/cheza/usb_pd_policy.c
deleted file mode 100644
index 694899ab79..0000000000
--- a/board/cheza/usb_pd_policy.c
+++ /dev/null
@@ -1,203 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "charge_manager.h"
-#include "console.h"
-#include "gpio.h"
-#include "pi3usb9281.h"
-#include "system.h"
-#include "usb_mux.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-int pd_check_vconn_swap(int port)
-{
-	/* TODO(waihong): Check any case we do not allow. */
-	return 1;
-}
-
-__override void pd_execute_data_swap(int port,
-				     enum pd_data_role data_role)
-{
-	int enable = (data_role == PD_ROLE_UFP);
-	int type;
-
-	/*
-	 * Exclude the PD charger, in which the "USB Communications Capable"
-	 * bit is unset in the Fixed Supply PDO.
-	 */
-	if (pd_capable(port))
-		enable = enable && pd_get_partner_usb_comm_capable(port);
-
-	/*
-	 * The hub behind the BC1.2 chip may advertise a BC1.2 type. So
-	 * disconnect the switch when getting the charger type to ensure
-	 * the detected type is from external.
-	 */
-	usb_charger_set_switches(port, USB_SWITCH_DISCONNECT);
-	type = pi3usb9281_get_device_type(port);
-	usb_charger_set_switches(port, USB_SWITCH_RESTORE);
-
-	/* Exclude the BC1.2 charger, which is not detected as CDP or SDP. */
-	enable = enable && (type & (PI3USB9281_TYPE_CDP | PI3USB9281_TYPE_SDP));
-
-	/* Only mux one port to AP. If already muxed, return. */
-	if (enable && (!gpio_get_level(GPIO_USB_C0_HS_MUX_SEL) ||
-		       gpio_get_level(GPIO_USB_C1_HS_MUX_SEL)))
-		return;
-
-	/* Port-0 and port-1 have different polarities. */
-	if (port == 0)
-		gpio_set_level(GPIO_USB_C0_HS_MUX_SEL, enable ? 0 : 1);
-	else if (port == 1)
-		gpio_set_level(GPIO_USB_C1_HS_MUX_SEL, enable ? 1 : 0);
-}
-
-static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT];
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5,
-							TYPEC_RP_1A5};
-
-static void board_vbus_update_source_current(int port)
-{
-	if (port == 0) {
-		/*
-		 * Port 0 is controlled by a USB-C PPC SN5S330.
-		 */
-		ppc_set_vbus_source_current_limit(port, vbus_rp[port]);
-		ppc_vbus_source_enable(port, vbus_en[port]);
-	} else if (port == 1) {
-		/*
-		 * Port 1 is controlled by a USB-C current-limited power
-		 * switch, NX5P3290.   Change the GPIO driving the load switch.
-		 *
-		 * 1.5 vs 3.0 A limit is controlled by a dedicated gpio.
-		 * If the GPIO is asserted, it shorts a n-MOSFET to put a
-		 * 16.5k resistance (2x 33k in parallel) on the NX5P3290 load
-		 * switch ILIM pin, setting a minimum OCP current of 3100 mA.
-		 * If the GPIO is deasserted, the n-MOSFET is open that makes
-		 * a single 33k resistor on ILIM, setting a minimum OCP
-		 * current of 1505 mA.
-		 */
-		gpio_set_level(GPIO_EN_USB_C1_3A,
-			       vbus_rp[port] == TYPEC_RP_3A0 ? 1 : 0);
-		gpio_set_level(GPIO_EN_USB_C1_5V_OUT, vbus_en[port]);
-	}
-}
-
-void pd_power_supply_reset(int port)
-{
-	int prev_en;
-
-	prev_en = vbus_en[port];
-
-	/* Disable VBUS */
-	vbus_en[port] = 0;
-	board_vbus_update_source_current(port);
-
-	/* Enable discharge if we were previously sourcing 5V */
-	if (prev_en)
-		pd_set_vbus_discharge(port, 1);
-
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	/* Give back the current quota we are no longer using */
-	charge_manager_source_port(port, 0);
-#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	/* Disable charging */
-	board_vbus_sink_enable(port, 0);
-
-	pd_set_vbus_discharge(port, 0);
-
-	/* Provide VBUS */
-	vbus_en[port] = 1;
-	board_vbus_update_source_current(port);
-
-	/* Ensure we advertise the proper available current quota */
-	charge_manager_source_port(port, 1);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS; /* we are ready */
-}
-
-int board_vbus_source_enabled(int port)
-{
-	return vbus_en[port];
-}
-
-__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	vbus_rp[port] = rp;
-	board_vbus_update_source_current(port);
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return !gpio_get_level(port ? GPIO_USB_C1_VBUS_DET_L :
-				      GPIO_USB_C0_VBUS_DET_L);
-}
-
-/* ----------------- Vendor Defined Messages ------------------ */
-/**
- * Is the port fine to be muxed its DisplayPort lines?
- *
- * Only one port can be muxed to DisplayPort at a time.
- *
- * @param port	Port number of TCPC.
- * @return	1 is fine; 0 is bad as other port is already muxed;
- */
-static int is_dp_muxable(int port)
-{
-	int i;
-
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
-		if (i != port) {
-			if (usb_mux_get(i) & USB_PD_MUX_DP_ENABLED)
-				return 0;
-		}
-
-	return 1;
-}
-
-extern uint32_t dp_status[CONFIG_USB_PD_PORT_MAX_COUNT];
-__override int svdm_dp_attention(int port, uint32_t *payload)
-{
-	int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]);
-	int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]);
-	int mf_pref = PD_VDO_DPSTS_MF_PREF(payload[1]);
-
-	dp_status[port] = payload[1];
-
-	usb_mux_hpd_update(port, lvl, irq);
-
-	if (lvl && is_dp_muxable(port)) {
-		/*
-		 * The GPIO USBC_MUX_CONF1 enables the mux of the DP redriver
-		 * for the port 1.
-		 */
-		gpio_set_level(GPIO_USBC_MUX_CONF1, port == 1);
-
-		usb_mux_set(port, mf_pref ?
-			    USB_PD_MUX_DOCK : USB_PD_MUX_DP_ENABLED,
-			    USB_SWITCH_CONNECT, pd_get_polarity(port));
-	} else {
-		usb_mux_set(port, mf_pref ?
-			    USB_PD_MUX_USB_ENABLED : USB_PD_MUX_NONE,
-			    USB_SWITCH_CONNECT, pd_get_polarity(port));
-	}
-
-	/* ack */
-	return 1;
-}
diff --git a/board/chocodile_vpdmcu/board.c b/board/chocodile_vpdmcu/board.c
index ea4d129502..098d7bb61b 100644
--- a/board/chocodile_vpdmcu/board.c
+++ b/board/chocodile_vpdmcu/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,6 @@
 /* chocodile board configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "common.h"
 #include "gpio.h"
 #include "hooks.h"
@@ -21,7 +20,7 @@
 #include "util.h"
 #include "vpd_api.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
 
 void board_config_pre_init(void)
 {
@@ -29,6 +28,7 @@ void board_config_pre_init(void)
 	STM32_RCC_APB2ENR |= 1 << 0;
 }
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /* Initialize board. */
@@ -41,26 +41,26 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* USB PD CC lines sensing. Converted to mV (3300mV/4096). */
-	[ADC_VCONN_VSENSE] =  {
-	"VCONN_VSENSE",  3000, 4096, 0, STM32_AIN(ADC_VCONN_VSENSE)},
-	[ADC_CC_VPDMCU] =     {
-	"CC_VPDMCU",     3000, 4096, 0, STM32_AIN(ADC_CC_VPDMCU)},
-	[ADC_CC_RP3A0_RD_L] = {
-	"CC_RP3A0_RD_L", 3000, 4096, 0, STM32_AIN(ADC_CC_RP3A0_RD_L)},
-	[ADC_RDCONNECT_REF] = {
-	"RDCONNECT_REF", 3000, 4096, 0, STM32_AIN(ADC_RDCONNECT_REF)},
-	[ADC_CC1_RP3A0_RD_L] = {
-	"CC1_RP1A5_ODH", 3000, 4096, 0, STM32_AIN(ADC_CC1_RP3A0_RD_L)},
-	[ADC_CC2_RP3A0_RD_L] = {
-	"CC2_RP1A5_ODH", 3000, 4096, 0, STM32_AIN(ADC_CC2_RP3A0_RD_L)},
-	[ADC_HOST_VBUS_VSENSE] = {
-	"HOST_VBUS_VSENSE", 3000, 4096, 0, STM32_AIN(ADC_HOST_VBUS_VSENSE)},
-	[ADC_CHARGE_VBUS_VSENSE] = {
-	"CHARGE_VBUS_VSENSE", 3000, 4096, 0, STM32_AIN(ADC_CHARGE_VBUS_VSENSE)},
-	[ADC_CC1_RPUSB_ODH] = {
-	"CC1_RPUSB_ODH", 3000, 4096, 0, STM32_AIN(ADC_CC1_RPUSB_ODH)},
-	[ADC_CC2_RPUSB_ODH] = {
-	"CC2_RPUSB_ODH", 3000, 4096, 0, STM32_AIN(ADC_CC2_RPUSB_ODH)},
+	[ADC_VCONN_VSENSE] = { "VCONN_VSENSE", 3000, 4096, 0,
+			       STM32_AIN(ADC_VCONN_VSENSE) },
+	[ADC_CC_VPDMCU] = { "CC_VPDMCU", 3000, 4096, 0,
+			    STM32_AIN(ADC_CC_VPDMCU) },
+	[ADC_CC_RP3A0_RD_L] = { "CC_RP3A0_RD_L", 3000, 4096, 0,
+				STM32_AIN(ADC_CC_RP3A0_RD_L) },
+	[ADC_RDCONNECT_REF] = { "RDCONNECT_REF", 3000, 4096, 0,
+				STM32_AIN(ADC_RDCONNECT_REF) },
+	[ADC_CC1_RP3A0_RD_L] = { "CC1_RP1A5_ODH", 3000, 4096, 0,
+				 STM32_AIN(ADC_CC1_RP3A0_RD_L) },
+	[ADC_CC2_RP3A0_RD_L] = { "CC2_RP1A5_ODH", 3000, 4096, 0,
+				 STM32_AIN(ADC_CC2_RP3A0_RD_L) },
+	[ADC_HOST_VBUS_VSENSE] = { "HOST_VBUS_VSENSE", 3000, 4096, 0,
+				   STM32_AIN(ADC_HOST_VBUS_VSENSE) },
+	[ADC_CHARGE_VBUS_VSENSE] = { "CHARGE_VBUS_VSENSE", 3000, 4096, 0,
+				     STM32_AIN(ADC_CHARGE_VBUS_VSENSE) },
+	[ADC_CC1_RPUSB_ODH] = { "CC1_RPUSB_ODH", 3000, 4096, 0,
+				STM32_AIN(ADC_CC1_RPUSB_ODH) },
+	[ADC_CC2_RPUSB_ODH] = { "CC2_RPUSB_ODH", 3000, 4096, 0,
+				STM32_AIN(ADC_CC2_RPUSB_ODH) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
diff --git a/board/chocodile_vpdmcu/board.h b/board/chocodile_vpdmcu/board.h
index 09adee47b5..0e0ff70ab8 100644
--- a/board/chocodile_vpdmcu/board.h
+++ b/board/chocodile_vpdmcu/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,14 +27,14 @@
 #define CONFIG_RO_SIZE 0
 /* Fake full size if we had a RO partition */
 #undef CONFIG_RW_SIZE
-#define CONFIG_RW_SIZE CONFIG_FLASH_SIZE
+#define CONFIG_RW_SIZE CONFIG_FLASH_SIZE_BYTES
 #endif /* HAS_TASK_CONSOLE */
 
 /* 48 MHz SYSCLK clock frequency */
 #define CPU_CLOCK 48000000
 
 /* the UART console is on USART1 (PA9/PA10) */
-#undef  CONFIG_UART_CONSOLE
+#undef CONFIG_UART_CONSOLE
 #define CONFIG_UART_CONSOLE 1
 
 /* Optional features */
@@ -43,23 +43,22 @@
 #undef CONFIG_CMD_PD
 #undef CONFIG_USBC_VCONN
 #define CONFIG_ADC
-#undef  CONFIG_ADC_WATCHDOG
+#undef CONFIG_ADC_WATCHDOG
 #define CONFIG_ADC_SAMPLE_TIME STM32_ADC_SMPR_41_5_CY
 #define CONFIG_BOARD_PRE_INIT
 #define CONFIG_COMMON_GPIO_SHORTNAMES
-#undef  CONFIG_DEBUG_ASSERT
+#undef CONFIG_DEBUG_ASSERT
 #define CONFIG_FORCE_CONSOLE_RESUME
 #define CONFIG_HIBERNATE
-#undef  CONFIG_HOSTCMD_EVENTS
+#undef CONFIG_HOSTCMD_EVENTS
 #define CONFIG_HW_CRC
-#undef  CONFIG_LID_SWITCH
+#undef CONFIG_LID_SWITCH
 #define CONFIG_LOW_POWER_IDLE
 #define CONFIG_LTO
-#define CONFIG_STM_HWTIMER32
-#undef  CONFIG_TASK_PROFILING
-#undef  CONFIG_UART_TX_BUF_SIZE
-#undef  CONFIG_UART_TX_DMA
-#undef  CONFIG_UART_RX_DMA
+#undef CONFIG_TASK_PROFILING
+#undef CONFIG_UART_TX_BUF_SIZE
+#undef CONFIG_UART_TX_DMA
+#undef CONFIG_UART_RX_DMA
 #define CONFIG_UART_TX_BUF_SIZE 128
 #define CONFIG_USB_PD_PORT_MAX_COUNT 1
 #define CONFIG_USB_PD_TCPC
@@ -72,9 +71,10 @@
 #define CONFIG_USB_PD_DECODE_SOP
 #define CONFIG_USB_PD_DUAL_ROLE
 #define CONFIG_USB_PD_INTERNAL_COMP
+#undef CONFIG_USB_DPM_SM
 #define CONFIG_VBOOT_HASH
 #define CONFIG_WATCHDOG
-#undef  CONFIG_WATCHDOG_HELP
+#undef CONFIG_WATCHDOG_HELP
 
 #define CONFIG_USB_PID 0x5036
 #define VPD_HW_VERSION 0x0001
@@ -83,16 +83,19 @@
 /* USB bcdDevice */
 #define USB_BCD_DEVICE 0
 
+/* Charge Through Current */
+#define VPD_CT_CURRENT VPD_CT_CURRENT_3A
+
 /* Vbus impedance in milliohms */
 #define VPD_VBUS_IMPEDANCE 65
 
 /* GND impedance in milliohms */
 #define VPD_GND_IMPEDANCE 33
 
-#define PD_OPERATING_POWER_MW           15000
-#define PD_MAX_POWER_MW                 45000
-#define PD_MAX_CURRENT_MA               3000
-#define PD_MAX_VOLTAGE_MV               20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 45000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 /*
  * TODO(crosbug.com/p/50519): Remove CONFIG_SYSTEM_UNLOCKED prior to building
  * MP FW.
@@ -100,26 +103,29 @@
 #define CONFIG_SYSTEM_UNLOCKED
 
 #ifdef HAS_TASK_CONSOLE
-#undef  CONFIG_CONSOLE_HISTORY
+#undef CONFIG_CONSOLE_HISTORY
 #define CONFIG_CONSOLE_HISTORY 2
 
 #else
-#undef  CONFIG_CONSOLE_CMDHELP
+#undef CONFIG_CONSOLE_CMDHELP
 #define CONFIG_DEBUG_PRINTF
 #define UARTN CONFIG_UART_CONSOLE
 #define UARTN_BASE STM32_USART_BASE(CONFIG_UART_CONSOLE)
 #endif /* HAS_TASK_CONSOLE */
 
 /* Use PSTATE embedded in the RO image, not in its own erase block */
-#undef  CONFIG_FLASH_PSTATE_BANK
-#undef  CONFIG_FW_PSTATE_SIZE
+#undef CONFIG_FLASH_PSTATE_BANK
+#undef CONFIG_FW_PSTATE_SIZE
 #define CONFIG_FW_PSTATE_SIZE 0
 
+/* Include math_util for bitmask_uint64 used in pd_timers */
+#define CONFIG_MATH_UTIL
+
 #ifndef __ASSEMBLER__
 
 /* Timer selection */
 #define TIM_CLOCK32 2
-#define TIM_ADC     3
+#define TIM_ADC 3
 
 #include "gpio_signal.h"
 
@@ -140,8 +146,8 @@ enum adc_channel {
 };
 
 /* 1.5A Rp */
-#define PD_SRC_VNC            PD_SRC_1_5_VNC_MV
-#define PD_SRC_RD_THRESHOLD   PD_SRC_1_5_RD_THRESH_MV
+#define PD_SRC_VNC PD_SRC_1_5_VNC_MV
+#define PD_SRC_RD_THRESHOLD PD_SRC_1_5_RD_THRESH_MV
 
 #endif /* !__ASSEMBLER__ */
 
diff --git a/board/chocodile_vpdmcu/build.mk b/board/chocodile_vpdmcu/build.mk
index d4e5f58962..21c257bd7e 100644
--- a/board/chocodile_vpdmcu/build.mk
+++ b/board/chocodile_vpdmcu/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/chocodile_vpdmcu/chocodile.html b/board/chocodile_vpdmcu/chocodile.html
index b38edf94ec..6aec670f2a 100644
--- a/board/chocodile_vpdmcu/chocodile.html
+++ b/board/chocodile_vpdmcu/chocodile.html
@@ -866,7 +866,7 @@ <h1>chocodile/page1: TABLE OF CONTENTS</h1>
 <text stroke="none" x="4750" y="-25" font-size="40" text-anchor="middle">10</text>
 <text stroke="none" x="250" y="-25" font-size="40" text-anchor="middle">1</text>
 <text stroke="none" x="38" y="-250" font-size="40" text-anchor="middle">A</text>
-<text stroke="none" x="99" y="-97" font-size="24">FOLLOWING NOTICE SHALL APPLY: &nbsp;COPYRIGHT C 2009 GOOGLE, INC. &nbsp;ALL RIGHTS RESERVED.</text>
+<text stroke="none" x="99" y="-97" font-size="24">FOLLOWING NOTICE SHALL APPLY: &nbsp;COPYRIGHT 2009 GOOGLE LLC</text>
 <text stroke="none" x="38" y="-3750" font-size="40" text-anchor="middle">H</text>
 <text stroke="none" x="5750" y="-25" font-size="40" text-anchor="middle">12</text>
 <text stroke="none" x="92" y="-200" font-size="24">THESE MATERIALS (INCLUDING ALL TEXT, SOFTWARE,CODE, DISPLAYS, ARTWORK, AND IMAGES) CONTAIN TRADE SECRETS AND CONFIDENTIAL INFORMATION WHICH ARE PROPRIETARY TO GOOGLE, INC. &nbsp;ANY USE, REPRODUCTION, DISTRIBUTION,</text>
diff --git a/board/chocodile_vpdmcu/ec.tasklist b/board/chocodile_vpdmcu/ec.tasklist
index 6753502b92..ecbd3b052c 100644
--- a/board/chocodile_vpdmcu/ec.tasklist
+++ b/board/chocodile_vpdmcu/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/chocodile_vpdmcu/gpio.inc b/board/chocodile_vpdmcu/gpio.inc
index a34c617ef1..060054f719 100644
--- a/board/chocodile_vpdmcu/gpio.inc
+++ b/board/chocodile_vpdmcu/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/chocodile_vpdmcu/usb_pd_config.h b/board/chocodile_vpdmcu/usb_pd_config.h
index a6c1adbc61..7fe608eb2a 100644
--- a/board/chocodile_vpdmcu/usb_pd_config.h
+++ b/board/chocodile_vpdmcu/usb_pd_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -55,7 +55,7 @@ static inline void spi_enable_clock(int port)
 
 #define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
 #define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
-#define TIM_CCR_CS  1
+#define TIM_CCR_CS 1
 
 /* EXTI line 21 is connected to the CMP1 output */
 #define EXTI_COMP1_MASK (1 << 21)
@@ -95,13 +95,15 @@ static inline void pd_tx_spi_reset(int port)
 static inline void pd_tx_enable(int port, int polarity)
 {
 	/* USB_CC_TX_DATA: PB4 is SPI1 MISO */
-	STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B)
-			& ~(3 << (2*4))) /* PB4 disable ADC */
-			|  (2 << (2*4)); /* Set as SPI1_MISO */
+	STM32_GPIO_MODER(GPIO_B) =
+		(STM32_GPIO_MODER(GPIO_B) & ~(3 << (2 * 4))) /* PB4 disable ADC
+							      */
+		| (2 << (2 * 4)); /* Set as SPI1_MISO */
 	/* MCU ADC PA1 pin output low */
-	STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
-			& ~(3 << (2*1))) /* PA1 disable ADC */
-			|  (1 << (2*1)); /* Set as GPO */
+	STM32_GPIO_MODER(GPIO_A) =
+		(STM32_GPIO_MODER(GPIO_A) & ~(3 << (2 * 1))) /* PA1 disable ADC
+							      */
+		| (1 << (2 * 1)); /* Set as GPO */
 	gpio_set_level(GPIO_CC_VPDMCU, 0);
 }
 
@@ -109,11 +111,10 @@ static inline void pd_tx_enable(int port, int polarity)
 static inline void pd_tx_disable(int port, int polarity)
 {
 	/* Set CC_TX_DATA to Hi-Z, PB4 is SPI1 MISO */
-	STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B)
-			& ~(3 << (2*4)));
+	STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B) & ~(3 << (2 * 4)));
 	/* set ADC PA1 pin to ADC function (Hi-Z) */
-	STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
-			|  (3 << (2*1))); /* PA1 as ADC */
+	STM32_GPIO_MODER(GPIO_A) =
+		(STM32_GPIO_MODER(GPIO_A) | (3 << (2 * 1))); /* PA1 as ADC */
 }
 
 /* we know the plug polarity, do the right configuration */
@@ -123,8 +124,8 @@ static inline void pd_select_polarity(int port, int polarity)
 	 * use the right comparator : CC1 -> PA1 (COMP1 INP)
 	 * use VrefInt / 2 as INM (about 600mV)
 	 */
-	STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK)
-		| STM32_COMP_CMP1EN | STM32_COMP_CMP1INSEL_VREF12;
+	STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK) |
+			 STM32_COMP_CMP1EN | STM32_COMP_CMP1INSEL_VREF12;
 }
 
 /* Initialize pins used for TX and put them in Hi-Z */
@@ -160,4 +161,3 @@ static inline int pd_adc_read(int port, int cc)
 }
 
 #endif /* __CROS_EC_USB_PD_CONFIG_H */
-
diff --git a/board/chocodile_vpdmcu/vif_override.xml b/board/chocodile_vpdmcu/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/chocodile_vpdmcu/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/chocodile_vpdmcu/vpd_api.c b/board/chocodile_vpdmcu/vpd_api.c
index 857ca46d1c..53cc0fa733 100644
--- a/board/chocodile_vpdmcu/vpd_api.c
+++ b/board/chocodile_vpdmcu/vpd_api.c
@@ -1,13 +1,13 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "adc.h"
+#include "driver/tcpm/tcpm.h"
 #include "gpio.h"
 #include "registers.h"
 #include "vpd_api.h"
-#include "driver/tcpm/tcpm.h"
 
 /*
  * Polarity based on 'DFP Perspective' (see table 4-10 USB Type-C Cable and
@@ -35,7 +35,7 @@
 #endif
 
 #undef CC_RA
-#define CC_RA(cc, sel)  (cc < pd_src_rd_threshold[sel])
+#define CC_RA(cc, sel) (cc < pd_src_rd_threshold[sel])
 #undef CC_RD
 #define CC_RD(cc, sel) ((cc >= pd_src_rd_threshold[sel]) && (cc < PD_SRC_VNC))
 
@@ -47,16 +47,16 @@
 #define VBUS_DETECT_THRESHOLD 2500 /* mV */
 #define VCONN_DETECT_THRESHOLD 2500 /* mV */
 
-#define SCALE(vmeas, sfactor) (((vmeas) * 1000) / (sfactor))
+#define SCALE(vmeas, sfactor) (((vmeas)*1000) / (sfactor))
 
 /*
  * Type C power source charge current limits are identified by their cc
  * voltage (set by selecting the proper Rd resistor). Any voltage below
  * TYPE_C_SRC_500_THRESHOLD will not be identified as a type C charger.
  */
-#define TYPE_C_SRC_DEFAULT_THRESHOLD    200  /* mV */
-#define TYPE_C_SRC_1500_THRESHOLD       660  /* mV */
-#define TYPE_C_SRC_3000_THRESHOLD       1230 /* mV */
+#define TYPE_C_SRC_DEFAULT_THRESHOLD 200 /* mV */
+#define TYPE_C_SRC_1500_THRESHOLD 660 /* mV */
+#define TYPE_C_SRC_3000_THRESHOLD 1230 /* mV */
 
 /* Charge-Through pull up/down enabled */
 static int ct_cc_pull;
@@ -86,7 +86,7 @@ static int vpd_cc_voltage_to_status(int cc_volt, int cc_pull)
 			return TYPEC_CC_VOLT_RA;
 		else
 			return TYPEC_CC_VOLT_OPEN;
-	/* If we have a pull-down, then we are sink, check for Rp. */
+		/* If we have a pull-down, then we are sink, check for Rp. */
 	} else if (cc_pull == TYPEC_CC_RD || cc_pull == TYPEC_CC_RA_RD) {
 		if (cc_volt >= TYPE_C_SRC_3000_THRESHOLD)
 			return TYPEC_CC_VOLT_RP_3_0;
@@ -200,13 +200,13 @@ void vpd_host_set_pull(int pull, int rp_value)
 		break;
 	case TYPEC_CC_RA_RD:
 		vpd_cc_rpusb_odh(GPO_HZ);
-		vpd_config_cc_rp3a0_rd_l(PIN_GPO, 0);
+		vpd_config_cc_rp3a0_rd_l(PIN_CMP, 0);
 
 		/*
 		 * RA is connected to VCONN
 		 * RD is connected to CC
 		 */
-		vpd_cc_db_en_od(GPO_HZ);
+		vpd_cc_db_en_od(GPO_HIGH);
 		break;
 	case TYPEC_CC_OPEN:
 		vpd_cc_rpusb_odh(GPO_HZ);
@@ -218,8 +218,8 @@ void vpd_host_set_pull(int pull, int rp_value)
 
 void vpd_host_get_cc(int *cc)
 {
-	*cc = vpd_cc_voltage_to_status(
-		adc_read_channel(ADC_CC_VPDMCU), host_cc_pull);
+	*cc = vpd_cc_voltage_to_status(adc_read_channel(ADC_CC_VPDMCU),
+				       host_cc_pull);
 }
 
 void vpd_rx_enable(int en)
@@ -237,17 +237,23 @@ void vpd_config_cc_rp3a0_rd_l(enum vpd_pin cfg, int en)
 		gpio_set_level(GPIO_CC_RP3A0_RD_L, en ? 1 : 0);
 
 		/* Disable Analog mode and Enable GPO */
-		STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
-				& ~(3 << (2*2))) /* PA2 disable ADC */
-				|  (1 << (2*2)); /* Set as GPO */
+		STM32_GPIO_MODER(GPIO_A) =
+			(STM32_GPIO_MODER(GPIO_A) & ~(3 << (2 * 2))) /* PA2
+									disable
+									ADC */
+			| (1 << (2 * 2)); /* Set as GPO */
 	} else {
 		/* Set PA2 pin to ANALOG function */
-		STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
-				|  (3 << (2*2))); /* PA2 in ANALOG mode */
+		STM32_GPIO_MODER(GPIO_A) =
+			(STM32_GPIO_MODER(GPIO_A) | (3 << (2 * 2))); /* PA2 in
+									ANALOG
+									mode */
 
 		/* Set PA3 pin to ANALOG function */
-		STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
-				|  (3 << (2*3))); /* PA3 in ANALOG mode */
+		STM32_GPIO_MODER(GPIO_A) =
+			(STM32_GPIO_MODER(GPIO_A) | (3 << (2 * 3))); /* PA3 in
+									ANALOG
+									mode */
 
 		/* Disable Window Mode. Select PA3 */
 		STM32_COMP_CSR &= ~STM32_COMP_WNDWEN;
@@ -276,9 +282,11 @@ void vpd_config_cc1_rp3a0_rd_l(enum vpd_pin cfg, int en)
 		gpio_set_level(GPIO_CC1_RP3A0_RD_L, en ? 1 : 0);
 
 		/* Disable Analog mode and Enable GPO */
-		STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
-				& ~(3 << (2*4))) /* PA4 disable ADC */
-				|  (1 << (2*4)); /* Set as GPO */
+		STM32_GPIO_MODER(GPIO_A) =
+			(STM32_GPIO_MODER(GPIO_A) & ~(3 << (2 * 4))) /* PA4
+									disable
+									ADC */
+			| (1 << (2 * 4)); /* Set as GPO */
 	}
 
 	if (cfg == PIN_ADC || cfg == PIN_CMP) {
@@ -286,13 +294,17 @@ void vpd_config_cc1_rp3a0_rd_l(enum vpd_pin cfg, int en)
 		STM32_COMP_CSR &= ~STM32_COMP_CMP2EN;
 
 		/* Set PA4 pin to Analog mode */
-		STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
-				|  (3 << (2*4))); /* PA4 in ANALOG mode */
+		STM32_GPIO_MODER(GPIO_A) =
+			(STM32_GPIO_MODER(GPIO_A) | (3 << (2 * 4))); /* PA4 in
+									ANALOG
+									mode */
 
 		if (cfg == PIN_CMP) {
 			/* Set PA3 pin to ANALOG function */
-			STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
-				|  (3 << (2*3))); /* PA3 in ANALOG mode */
+			STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) |
+						    (3 << (2 * 3))); /* PA3 in
+									ANALOG
+									mode */
 
 			/* Disable Window Mode. Select PA3*/
 			STM32_COMP_CSR &= ~STM32_COMP_WNDWEN;
@@ -319,9 +331,11 @@ void vpd_config_cc2_rp3a0_rd_l(enum vpd_pin cfg, int en)
 		gpio_set_level(GPIO_CC2_RP3A0_RD_L, en ? 1 : 0);
 
 		/* Disable Analog mode and Enable GPO */
-		STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
-				& ~(3 << (2*5))) /* PA5 disable ADC */
-				|  (1 << (2*5)); /* Set as GPO */
+		STM32_GPIO_MODER(GPIO_A) =
+			(STM32_GPIO_MODER(GPIO_A) & ~(3 << (2 * 5))) /* PA5
+									disable
+									ADC */
+			| (1 << (2 * 5)); /* Set as GPO */
 	}
 
 	if (cfg == PIN_ADC || cfg == PIN_CMP) {
@@ -329,13 +343,17 @@ void vpd_config_cc2_rp3a0_rd_l(enum vpd_pin cfg, int en)
 		STM32_COMP_CSR &= ~STM32_COMP_CMP2EN;
 
 		/* Set PA5 pin to ANALOG function */
-		STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
-				|  (3 << (2*5))); /* PA5 in ANALOG mode */
+		STM32_GPIO_MODER(GPIO_A) =
+			(STM32_GPIO_MODER(GPIO_A) | (3 << (2 * 5))); /* PA5 in
+									ANALOG
+									mode */
 
 		if (cfg == PIN_CMP) {
 			/* Set PA3 pin to ANALOG function */
-			STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
-				|  (3 << (2*3))); /* PA3 in ANALOG mode */
+			STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) |
+						    (3 << (2 * 3))); /* PA3 in
+									ANALOG
+									mode */
 
 			/* Disable Window Mode. */
 			STM32_COMP_CSR &= ~STM32_COMP_WNDWEN;
@@ -362,13 +380,17 @@ void vpd_config_cc1_rpusb_odh(enum vpd_pin cfg, int en)
 		gpio_set_level(GPIO_CC1_RPUSB_ODH, en ? 1 : 0);
 
 		/* Disable Analog mode and Enable GPO */
-		STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B)
-				& ~(3 << (2*0))) /* PB0 disable ADC */
-				|  (1 << (2*0)); /* Set as GPO */
+		STM32_GPIO_MODER(GPIO_B) =
+			(STM32_GPIO_MODER(GPIO_B) & ~(3 << (2 * 0))) /* PB0
+									disable
+									ADC */
+			| (1 << (2 * 0)); /* Set as GPO */
 	} else {
 		/* Enable Analog mode */
-		STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B)
-				|  (3 << (2*0))); /* PB0 in ANALOG mode */
+		STM32_GPIO_MODER(GPIO_B) =
+			(STM32_GPIO_MODER(GPIO_B) | (3 << (2 * 0))); /* PB0 in
+									ANALOG
+									mode */
 	}
 }
 
@@ -382,13 +404,17 @@ void vpd_config_cc2_rpusb_odh(enum vpd_pin cfg, int en)
 		gpio_set_level(GPIO_CC2_RPUSB_ODH, en ? 1 : 0);
 
 		/* Disable Analog mode and Enable GPO */
-		STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B)
-				& ~(3 << (2*1))) /* PB1 disable ADC */
-				|  (1 << (2*1)); /* Set as GPO */
+		STM32_GPIO_MODER(GPIO_B) =
+			(STM32_GPIO_MODER(GPIO_B) & ~(3 << (2 * 1))) /* PB1
+									disable
+									ADC */
+			| (1 << (2 * 1)); /* Set as GPO */
 	} else {
 		/* Enable Analog mode */
-		STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B)
-				|  (3 << (2*1))); /* PB1 in ANALOG mode */
+		STM32_GPIO_MODER(GPIO_B) =
+			(STM32_GPIO_MODER(GPIO_B) | (3 << (2 * 1))); /* PB1 in
+									ANALOG
+									mode */
 	}
 }
 
@@ -405,7 +431,7 @@ inline int vpd_read_host_vbus(void)
 inline int vpd_read_ct_vbus(void)
 {
 	return SCALE(adc_read_channel(ADC_CHARGE_VBUS_VSENSE),
-							VBUS_SCALE_FACTOR);
+		     VBUS_SCALE_FACTOR);
 }
 
 inline int vpd_read_vconn(void)
diff --git a/board/chocodile_vpdmcu/vpd_api.h b/board/chocodile_vpdmcu/vpd_api.h
index df50f92006..5d2fd24afb 100644
--- a/board/chocodile_vpdmcu/vpd_api.h
+++ b/board/chocodile_vpdmcu/vpd_api.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,34 +12,18 @@
 #include "gpio.h"
 #include "usb_pd.h"
 
-enum vpd_pin {
-	PIN_ADC,
-	PIN_CMP,
-	PIN_GPO
-};
+enum vpd_pin { PIN_ADC, PIN_CMP, PIN_GPO };
 
-enum vpd_gpo {
-	GPO_HZ,
-	GPO_HIGH,
-	GPO_LOW
-};
+enum vpd_gpo { GPO_HZ, GPO_HIGH, GPO_LOW };
 
 enum vpd_pwr {
 	PWR_VCONN,
 	PWR_VBUS,
 };
 
-enum vpd_cc {
-	CT_OPEN,
-	CT_CC1,
-	CT_CC2
-};
+enum vpd_cc { CT_OPEN, CT_CC1, CT_CC2 };
 
-enum vpd_billboard {
-	BB_NONE,
-	BB_SRC,
-	BB_SNK
-};
+enum vpd_billboard { BB_NONE, BB_SRC, BB_SNK };
 
 /**
  * Set Charge-Through Rp or Rd on CC lines
diff --git a/board/chronicler/battery.c b/board/chronicler/battery.c
new file mode 100644
index 0000000000..1d885607b7
--- /dev/null
+++ b/board/chronicler/battery.c
@@ -0,0 +1,66 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "common.h"
+#include "util.h"
+
+/*
+ * Battery info for all Chronicler battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	/* NVT CP813907-01 Battery Information */
+	[BATTERY_NVT_CP813907] = {
+		.fuel_gauge = {
+			.manuf_name = "NVT",
+			.device_name = "CP813907-01",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x10, 0x10 },
+			},
+			.fet = {
+				.reg_addr = 0x00,
+				.reg_mask = 0x2000,
+				.disconnect_val = 0x2000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13200, /* mV */
+			.voltage_normal		= 11550, /* mV */
+			.voltage_min		= 9000,  /* mV */
+			.precharge_current	= 128,	 /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 45,
+			.charging_min_c		= 0,
+			.charging_max_c		= 55,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 60,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_NVT_CP813907;
diff --git a/board/chronicler/board.c b/board/chronicler/board.c
new file mode 100644
index 0000000000..ca6ae5c392
--- /dev/null
+++ b/board/chronicler/board.c
@@ -0,0 +1,455 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Chronicler board-specific configuration */
+#include "accelgyro.h"
+#include "battery.h"
+#include "battery_smart.h"
+#include "button.h"
+#include "cbi_ec_fw_config.h"
+#include "charge_state.h"
+#include "common.h"
+#include "driver/sync.h"
+#include "driver/tcpm/ps8xxx.h"
+#include "extpower.h"
+#include "fan.h"
+#include "fan_chip.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "keyboard_8042.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "switch.h"
+#include "system.h"
+#include "task.h"
+#include "throttle_ap.h"
+#include "uart.h"
+#include "usb_pd.h"
+#include "usb_pd_tbt.h"
+#include "usb_pd_tcpm.h"
+#include "util.h"
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
+
+/******************************************************************************/
+/* Physical fans. These are logically separate from pwm_channels. */
+
+const struct fan_conf fan_conf_0 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
+	.pgood_gpio = -1,
+	.enable_gpio = GPIO_EN_PP5000_FAN,
+};
+
+const struct fan_rpm fan_rpm_0 = {
+	.rpm_min = 3000,
+	.rpm_start = 5000,
+	.rpm_max = 5100,
+};
+
+const struct fan_t fans[FAN_CH_COUNT] = {
+	[FAN_CH_0] = {
+		.conf = &fan_conf_0,
+		.rpm = &fan_rpm_0,
+	},
+};
+
+/******************************************************************************/
+/* EC thermal management configuration */
+
+/*
+ * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
+ * 130 C.  However, sensor is located next to DDR, so we need to use the lower
+ * DDR temperature limit (80 C)
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CONFIG_WITHOUT_FAN \
+	{                          \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(77), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+		},   \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_config_without_fan =
+	THERMAL_CONFIG_WITHOUT_FAN;
+
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CONFIG_WITH_FAN  \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(77), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+		}, \
+		/* For real temperature fan_table (0 ~ 99C) */ \
+		.temp_fan_off = C_TO_K(0), \
+		.temp_fan_max = C_TO_K(99), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_config_with_fan =
+	THERMAL_CONFIG_WITH_FAN;
+
+struct ec_thermal_config thermal_params[] = {
+	[TEMP_SENSOR_1_CHARGER] = THERMAL_CONFIG_WITH_FAN,
+	[TEMP_SENSOR_2_PP3300_REGULATOR] = THERMAL_CONFIG_WITHOUT_FAN,
+	[TEMP_SENSOR_3_DDR_SOC] = THERMAL_CONFIG_WITHOUT_FAN,
+	[TEMP_SENSOR_4_FAN] = THERMAL_CONFIG_WITHOUT_FAN,
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
+
+struct fan_step {
+	int on;
+	int off;
+	int rpm;
+};
+
+/* Fan control table */
+static const struct fan_step fan_table0[] = {
+	{ .on = 30, .off = 0, .rpm = 3150 }, /* Fan level 0 */
+	{ .on = 47, .off = 43, .rpm = 3500 }, /* Fan level 1 */
+	{ .on = 50, .off = 47, .rpm = 3750 }, /* Fan level 2 */
+	{ .on = 53, .off = 50, .rpm = 4200 }, /* Fan level 3 */
+	{ .on = 56, .off = 53, .rpm = 4500 }, /* Fan level 4 */
+	{ .on = 59, .off = 56, .rpm = 5000 }, /* Fan level 5 */
+};
+
+/* All fan tables must have the same number of levels */
+#define NUM_FAN_LEVELS ARRAY_SIZE(fan_table0)
+
+static const struct fan_step *fan_table = fan_table0;
+
+#define FAN_AVERAGE_TIME_SEC 5
+
+int fan_percent_to_rpm(int fan, int pct)
+{
+	static int current_level;
+	static int previous_level = NUM_FAN_LEVELS;
+	static int cnt, avg_pct, previous_pct;
+	int i;
+
+	/* Average several times to smooth fan rotating speed. */
+	avg_pct += pct;
+
+	if (++cnt != FAN_AVERAGE_TIME_SEC)
+		return fan_table[previous_level].rpm;
+
+	avg_pct = (int)avg_pct / FAN_AVERAGE_TIME_SEC;
+
+	/*
+	 * Compare the pct and previous pct, we have the three paths :
+	 *  1. decreasing path. (check the off point)
+	 *  2. increasing path. (check the on point)
+	 *  3. invariant path. (return the current RPM)
+	 */
+	if (avg_pct < previous_pct) {
+		for (i = current_level; i >= 0; i--) {
+			if (avg_pct <= fan_table[i].off)
+				current_level = i - 1;
+			else
+				break;
+		}
+	} else if (avg_pct > previous_pct) {
+		for (i = current_level + 1; i < NUM_FAN_LEVELS; i++) {
+			if (avg_pct >= fan_table[i].on)
+				current_level = i;
+			else
+				break;
+		}
+	}
+
+	if (current_level < 0)
+		current_level = 0;
+
+	if (current_level != previous_level)
+		cprints(CC_THERMAL, "Setting fan RPM to %d",
+			fan_table[current_level].rpm);
+
+	previous_pct = avg_pct;
+	previous_level = current_level;
+
+	cnt = 0;
+	avg_pct = 0;
+
+	return fan_table[current_level].rpm;
+}
+
+/******************************************************************************/
+/* MFT channels. These are logically separate from pwm_channels. */
+const struct mft_t mft_channels[] = {
+	[MFT_CH_0] = {
+		.module = NPCX_MFT_MODULE_1,
+		.clk_src = TCKC_LFCLK,
+		.pwm_id = PWM_CH_FAN,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
+
+/******************************************************************************/
+/* I2C port map configuration */
+const struct i2c_port_t i2c_ports[] = {
+	{
+		.name = "usb_c0",
+		.port = I2C_PORT_USB_C0,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C1_USB_C0_SCL,
+		.sda = GPIO_EC_I2C1_USB_C0_SDA,
+	},
+	{
+		.name = "usb_c1",
+		.port = I2C_PORT_USB_C1,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C2_USB_C1_SCL,
+		.sda = GPIO_EC_I2C2_USB_C1_SDA,
+	},
+	{
+		.name = "usb_1_mix",
+		.port = I2C_PORT_USB_1_MIX,
+		.kbps = 100,
+		.scl = GPIO_EC_I2C3_USB_1_MIX_SCL,
+		.sda = GPIO_EC_I2C3_USB_1_MIX_SDA,
+	},
+	{
+		.name = "power",
+		.port = I2C_PORT_POWER,
+		.kbps = 100,
+		.scl = GPIO_EC_I2C5_BATTERY_SCL,
+		.sda = GPIO_EC_I2C5_BATTERY_SDA,
+	},
+	{
+		.name = "eeprom",
+		.port = I2C_PORT_EEPROM,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C7_EEPROM_PWR_SCL_R,
+		.sda = GPIO_EC_I2C7_EEPROM_PWR_SDA_R,
+	},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+/******************************************************************************/
+/* PWM configuration */
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_FAN] = {
+		.channel = 5,
+		.flags = PWM_CONFIG_OPEN_DRAIN,
+		.freq = 25000
+	},
+	[PWM_CH_KBLIGHT] = {
+		.channel = 3,
+		.flags = 0,
+		/*
+		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
+		 * flicker. Higher frequencies consume similar average power to
+		 * lower PWM frequencies, but higher frequencies record a much
+		 * lower maximum power.
+		 */
+		.freq = 2400,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+/******************************************************************************/
+/* keyboard config */
+static const struct ec_response_keybd_config main_kb = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		/*
+		 *  Chronicler keyboard swaps T2 and T3 in the keyboard
+		 *  matrix,So swap the actions key lookup to match.
+		 *  The physical keyboard still orders the top row as
+		 *  Back, Refresh, Fullscreen, etc.
+		 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_REFRESH,		/* T2 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &main_kb;
+}
+
+/******************************************************************************/
+/* keyboard factory test */
+#ifdef CONFIG_KEYBOARD_FACTORY_TEST
+/*
+ * Map keyboard connector pins to EC GPIO pins for factory test.
+ * Pins mapped to {-1, -1} are skipped.
+ * The connector has 24 pins total, and there is no pin 0.
+ */
+
+const int keyboard_factory_scan_pins[][2] = {
+	{ -1, -1 }, { 0, 5 }, { 1, 1 },	  { 1, 0 },   { 0, 6 },
+	{ 0, 7 },   { 1, 4 }, { 1, 3 },	  { 1, 6 },   { 1, 7 },
+	{ 3, 1 },   { 2, 0 }, { 1, 5 },	  { 2, 6 },   { 2, 7 },
+	{ 2, 1 },   { 2, 4 }, { 2, 5 },	  { 1, 2 },   { 2, 3 },
+	{ 2, 2 },   { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 },
+};
+
+const int keyboard_factory_scan_pins_used =
+	ARRAY_SIZE(keyboard_factory_scan_pins);
+#endif
+
+/******************************************************************************/
+/* drop battery charging voltage depending on battery run time */
+
+#ifdef BATTERY_RUNTIME_TEST
+static int manual_run_time = -1;
+#endif
+
+struct drop_step {
+	int run_time; /* battery run time (day) */
+	int drop_volt; /* drop voltage (mV) */
+};
+
+/* voltage drop table */
+static const struct drop_step voltage_drop_table[] = {
+	{ .run_time = 90, .drop_volt = 13200 }, /* drop level 0 */
+	{ .run_time = 198, .drop_volt = 13125 }, /* drop level 1 */
+	{ .run_time = 305, .drop_volt = 13050 }, /* drop level 2 */
+	{ .run_time = 412, .drop_volt = 12975 }, /* drop level 3 */
+	{ .run_time = 519, .drop_volt = 12900 }, /* drop level 4 */
+	{ .run_time = 626, .drop_volt = 12825 }, /* drop level 5 */
+	{ .run_time = __INT_MAX__, .drop_volt = 12750 }, /* drop level 6 */
+};
+
+#define NUM_DROP_LEVELS ARRAY_SIZE(voltage_drop_table)
+
+static int get_battery_run_time_day(uint32_t *battery_run_time)
+{
+	int rv;
+	uint32_t run_time;
+	uint8_t data[6];
+
+	/* get battery run time */
+	rv = sb_read_mfgacc(PARAM_FIRMWARE_RUNTIME, SB_ALT_MANUFACTURER_ACCESS,
+			    data, sizeof(data));
+
+	if (rv)
+		return EC_ERROR_UNKNOWN;
+	/*
+	 * The response is 6 bytes; the runtime in seconds is the last 4 bytes.
+	 */
+	run_time = *(int32_t *)(&data[2]);
+
+#ifdef BATTERY_RUNTIME_TEST
+	cprints(CC_CHARGER, "run_time : 0x%08x (%d day)", run_time,
+		(run_time / 86400));
+
+	/* manual battery run time fot test */
+	if (manual_run_time != -1)
+		run_time = manual_run_time;
+#endif
+	/* second to day */
+	*battery_run_time = run_time / 86400;
+
+	return EC_SUCCESS;
+}
+
+/* charger profile override */
+int charger_profile_override(struct charge_state_data *curr)
+{
+	int i;
+	uint32_t batt_run_time = 0;
+
+	/* Should not do anything if battery not present */
+	if (battery_hw_present() != BP_YES)
+		return 0;
+
+	if (get_battery_run_time_day(&batt_run_time))
+		return EC_ERROR_UNKNOWN;
+
+	for (i = 0; i < NUM_DROP_LEVELS; i++) {
+		if (batt_run_time <= voltage_drop_table[i].run_time)
+			break;
+	}
+
+	curr->requested_voltage =
+		MIN(curr->requested_voltage, voltage_drop_table[i].drop_volt);
+#ifdef BATTERY_RUNTIME_TEST
+	cprints(CC_CHARGER,
+		"Charger: run time(day): %d, drop level: %d, CV: %d",
+		batt_run_time, i, curr->requested_voltage);
+#endif
+	return 0;
+}
+
+enum ec_status charger_profile_override_get_param(uint32_t param,
+						  uint32_t *value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+enum ec_status charger_profile_override_set_param(uint32_t param,
+						  uint32_t value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+static void battery_runtime_init(void)
+{
+	uint32_t batt_run_time = 0;
+
+	/* Should not do anything if battery not present */
+	if (battery_hw_present() != BP_YES)
+		return;
+
+	if (get_battery_run_time_day(&batt_run_time))
+		return;
+
+	cprints(CC_CHARGER, "battery run time(day): %d", batt_run_time);
+}
+DECLARE_HOOK(HOOK_INIT, battery_runtime_init, HOOK_PRIO_LAST);
+
+#ifdef BATTERY_RUNTIME_TEST
+/* test command */
+static int command_manual_run_time(int argc, const char **argv)
+{
+	char *e = NULL;
+
+	if (argc < 2) {
+		manual_run_time = -1;
+		cprints(CC_CHARGER, "manual run time reset");
+		return EC_SUCCESS;
+	}
+
+	if (argc != 2)
+		return EC_ERROR_PARAM_COUNT;
+
+	manual_run_time = strtoi(argv[1], &e, 0);
+	if (*e)
+		return EC_ERROR_PARAM1;
+
+	cprints(CC_CHARGER, "manual run time set to %d sec (%d day)",
+		manual_run_time, (manual_run_time / 86400));
+
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(rt, command_manual_run_time, "<battery_run_time_sec>",
+			"Set manual run time for test");
+#endif
diff --git a/board/chronicler/board.h b/board/chronicler/board.h
new file mode 100644
index 0000000000..d017b896be
--- /dev/null
+++ b/board/chronicler/board.h
@@ -0,0 +1,151 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Chronicler board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* Baseboard features */
+#include "baseboard.h"
+
+/*
+ * The RAM and flash size combination on the NPCX797FC dose not leave
+ * any unused flash space that can be used to store the .init_rom section.
+ */
+#undef CONFIG_CHIP_INIT_ROM_REGION
+
+/* Optional features */
+
+#define CONFIG_VBOOT_EFS2
+
+#define CONFIG_POWER_BUTTON
+
+#undef CONFIG_UART_TX_BUF_SIZE
+#define CONFIG_UART_TX_BUF_SIZE 4096
+
+/* Chipset features */
+#define CONFIG_POWER_PP5000_CONTROL
+#define CONFIG_CPU_PROCHOT_GATE_ON_C10
+
+/* Sensors */
+#undef CONFIG_TABLET_MODE
+#undef CONFIG_GMR_TABLET_MODE
+#undef CONFIG_ACCEL_FIFO
+#undef CONFIG_ACCEL_FIFO_SIZE
+
+/* USB Type C and USB PD defines */
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+
+/* TODO: b/144165680 - measure and check these values on Volteer */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+/*
+ * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
+ * cables only support up to 60W.
+ */
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
+
+/* USB Type A Features */
+#define USB_PORT_COUNT 1
+#define CONFIG_USB_PORT_POWER_DUMB
+
+/* USBC PPC*/
+#define CONFIG_USBC_PPC_SN5S330 /* USBC port C0 */
+#define CONFIG_USBC_PPC_SYV682X /* USBC port C1 */
+#define CONFIG_USB_PD_FRS_PPC
+#undef CONFIG_USB_PD_TCPC_RUNTIME_CONFIG
+#undef CONFIG_USB_PD_TCPM_TUSB422
+#undef CONFIG_USB_MUX_RUNTIME_CONFIG
+
+/* BC 1.2 */
+
+/* Volume Button feature */
+#undef CONFIG_VOLUME_BUTTONS
+
+/* Fan features */
+#define CONFIG_FAN_RPM_CUSTOM
+
+/* charger defines */
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+#define CONFIG_CHARGER_PROFILE_OVERRIDE
+
+/* Retimer */
+#undef CONFIG_USBC_RETIMER_INTEL_BB
+#undef CONFIG_USBC_RETIMER_INTEL_BB_RUNTIME_CONFIG
+
+/* Keyboard feature */
+#define CONFIG_KEYBOARD_FACTORY_TEST
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_LID_OPEN GPIO_EC_LID_OPEN
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL
+
+/* I2C Bus Configuration */
+#define CONFIG_I2C
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT3_0
+#define I2C_PORT_POWER NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+
+#define I2C_PORT_BATTERY I2C_PORT_POWER
+#define I2C_PORT_CHARGER I2C_PORT_EEPROM
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+#define CONFIG_I2C_CONTROLLER
+
+#define CONFIG_DEBUG_ASSERT_BRIEF
+
+/* Disable volume button command in EC console */
+#undef CONFIG_CMD_BUTTON
+
+/* Disable volume button in ectool */
+#undef CONFIG_HOSTCMD_BUTTON
+
+/* battery runtime test */
+#undef BATTERY_RUNTIME_TEST
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+#include "usbc_config.h"
+
+enum battery_type { BATTERY_NVT_CP813907, BATTERY_TYPE_COUNT };
+
+enum pwm_channel { PWM_CH_FAN, PWM_CH_KBLIGHT, PWM_CH_COUNT };
+
+void board_reset_pd_mcu(void);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/chronicler/build.mk b/board/chronicler/build.mk
new file mode 100644
index 0000000000..f317b88795
--- /dev/null
+++ b/board/chronicler/build.mk
@@ -0,0 +1,19 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx7
+CHIP_VARIANT:=npcx7m7fc
+BASEBOARD:=volteer
+
+board-y=board.o
+board-y+=battery.o
+board-y+=cbi.o
+board-y+=led.o
+board-y+=keyboard.o
+board-y+=usbc_config.o
diff --git a/board/chronicler/cbi.c b/board/chronicler/cbi.c
new file mode 100644
index 0000000000..a9c458b88d
--- /dev/null
+++ b/board/chronicler/cbi.c
@@ -0,0 +1,26 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Features common to ECOS and Zephyr */
+#include "cbi.h"
+#include "cbi_ec_fw_config.h"
+#include "common.h"
+#include "keyboard_raw.h"
+#include "usbc_config.h"
+
+/******************************************************************************/
+/*
+ * FW_CONFIG defaults for Chronicler if the CBI data is not initialized.
+ */
+union volteer_cbi_fw_config fw_config_defaults = {
+	.usb_db = DB_USB3_ACTIVE,
+};
+
+__override void board_cbi_init(void)
+{
+	if ((!IS_ENABLED(TEST_BUILD) && !ec_cfg_has_numeric_pad()) ||
+	    get_board_id() <= 2)
+		keyboard_raw_set_cols(KEYBOARD_COLS_NO_KEYPAD);
+}
diff --git a/board/chronicler/ec.tasklist b/board/chronicler/ec.tasklist
new file mode 100644
index 0000000000..644c36cd37
--- /dev/null
+++ b/board/chronicler/ec.tasklist
@@ -0,0 +1,26 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/chronicler/gpio.inc b/board/chronicler/gpio.inc
new file mode 100644
index 0000000000..b0a9ad6981
--- /dev/null
+++ b/board/chronicler/gpio.inc
@@ -0,0 +1,178 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+/* Wake Source interrupts */
+GPIO_INT(EC_LID_OPEN,          PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
+GPIO_INT(EC_WP_L,              PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(H1_EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
+GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
+
+/* Power sequencing interrupts */
+GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
+#endif
+GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_EC_RSMRST_ODL,     PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_EC_DSW_PWROK,      PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
+
+/* USB-C interrupts */
+GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(E, 0), GPIO_INT_BOTH, tcpc_alert_event)
+GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(A, 2), GPIO_INT_BOTH, tcpc_alert_event)
+
+GPIO_INT(USB_C0_PPC_INT_ODL,	PIN(6, 2), GPIO_INT_BOTH, ppc_interrupt)
+GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(F, 5), GPIO_INT_BOTH, ppc_interrupt)
+
+GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(E, 4), GPIO_INT_BOTH, bc12_interrupt)
+GPIO_INT(USB_C1_MIX_INT_ODL,	PIN(0, 3), GPIO_INT_BOTH, bc12_interrupt)
+
+/* HDMI interrupts */
+
+/* Power Sequencing Signals */
+GPIO(EN_PP3300_A,              PIN(A, 3), GPIO_OUT_LOW)
+GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
+GPIO(EN_PPVAR_VCCIN,           PIN(4, 3), GPIO_OUT_LOW) /* Enables VCCIN IMPV9 */
+GPIO(EC_PCH_DSW_PWROK,         PIN(C, 0), GPIO_OUT_LOW)
+
+/* Other wake sources */
+/*
+ * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an
+ * interrupt handler because it is automatically handled by the PSL.
+ *
+ * We need to lock the setting so this gpio can't be reconfigured to overdrive
+ * the real reset signal. (This is the PSL input pin not the real reset pin).
+ */
+GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH |
+					   GPIO_HIB_WAKE_HIGH |
+					   GPIO_LOCKED)
+
+/* AP/PCH Signals */
+GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
+GPIO(EC_PCH_RSMRST_ODL,        PIN(A, 6), GPIO_ODR_LOW) /* TODO - b/140950085 - implement TGL sequencing requirement */
+GPIO(EC_PCH_PWR_BTN_ODL,       PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
+GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
+GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
+GPIO_INT(EC_PROCHOT_IN_L,      PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
+GPIO_INT(CPU_C10_GATE_L,       PIN(6, 7), GPIO_INT_RISING, throttle_ap_c10_input_interrupt)
+GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
+
+GPIO(EC_PCH_INT_ODL,           PIN(B, 0), GPIO_ODR_HIGH)
+
+/* USB and USBC Signals */
+GPIO(EN_PP5000_USBA,		PIN(C, 6), GPIO_OUT_LOW)	/* Enable USB-A charging - all ports */
+GPIO(USB_A_LOW_PWR_OD,		PIN(6, 6), GPIO_ODR_LOW)	/* Don't limit USB-A charging by default - all ports */
+GPIO(USB_C1_RT_RST_ODL,		PIN(8, 3), GPIO_ODR_LOW)
+GPIO(USB_C0_OC_ODL,		PIN(B, 1), GPIO_ODR_HIGH)
+GPIO(USB_C1_OC_ODL,		PIN(5, 0), GPIO_ODR_HIGH)
+/* There is currently no need to service this interrupt. */
+GPIO(USB_C1_RT_INT_ODL,		PIN(F, 3), GPIO_INPUT)
+GPIO(USB_C1_FRS_EN, 		PIN(9, 4), GPIO_OUT_LOW)
+
+/* Don't have a load switch for retimer */
+UNIMPLEMENTED(USB_C1_LS_EN)
+
+/* Misc Signals */
+GPIO(EC_H1_PACKET_MODE,		PIN(7, 5), GPIO_OUT_LOW)	/* H1 Packet Mode */
+/*
+ * Despite their names, M2_SSD_PLN and M2_SSD_PLA are active-low, and M2_SSD_PLN
+ * is open-drain.
+ * TODO(b/138954381): Change these names when they change on the schematic.
+ */
+GPIO(M2_SSD_PLN,		PIN(A, 0), GPIO_ODR_HIGH)	/* SSD power-loss notification */
+GPIO(M2_SSD_PLA,		PIN(7, 0), GPIO_INPUT)		/* SSD power-loss acknowledgment */
+GPIO(CCD_MODE_ODL,		PIN(E, 5), GPIO_INPUT)		/* Case Closed Debug Mode */
+GPIO(EC_SLP_S0IX,		PIN(7, 2), GPIO_INPUT | GPIO_PULL_UP)
+
+/* LED */
+GPIO(C0_CHARGE_LED_AMBER_L,	PIN(C, 3), GPIO_OUT_HIGH)	/* Amber C0 port */
+GPIO(C0_CHARGE_LED_WHITE_L,	PIN(C, 4), GPIO_OUT_HIGH)	/* White C0 port */
+GPIO(C1_CHARGE_LED_AMBER_L,	PIN(6, 0), GPIO_OUT_HIGH)	/* Amber C1 port */
+GPIO(C1_CHARGE_LED_WHITE_L,	PIN(C, 2), GPIO_OUT_HIGH)	/* White C1 port */
+
+/* Unused signals */
+GPIO(CHARGER_INT_L,		PIN(7, 3), GPIO_INPUT)		/* Interrupt not used from ISL9241, on board pull-up */
+GPIO(EC_GP_SEL0_ODL,		PIN(B, 6), GPIO_OUT_LOW) 	/* Cannot be configured as input, drive output low, don't rely on the default setting of PxDOUT register */
+GPIO(EN_PP5000_USB_AG,		PIN(A, 7), GPIO_INPUT | GPIO_PULL_UP) /* Unconnected power sequencing signal */
+GPIO(UNUSED_GPIO41,		PIN(4, 1), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIOF2,		PIN(F, 2), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIO96,		PIN(9, 6), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIO34,		PIN(3, 4), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIO56,		PIN(5, 6), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIOD4,		PIN(D, 4), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIO95,		PIN(9, 5), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIO81,		PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIO93,		PIN(9, 3), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIO97,		PIN(9, 7), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIOB5,		PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)	/* Unused I2C port, Set input only */
+GPIO(UNUSED_GPIOB4,		PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)	/* Unused I2C port, Set input only */
+/* Only connected to test points */
+GPIO(EC_KB_BL_EN,		PIN(8, 6), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(EC_ESPI_ALERT_L,		PIN(5, 7), GPIO_INPUT | GPIO_PULL_UP)
+
+/*
+ * eDP backlight - both PCH and EC have enable pins that must be high
+ * for the backlight to turn on. Default state is high, and can be turned
+ * off during sleep states.
+ */
+GPIO(EC_EDP_BL_EN,             PIN(D, 3), GPIO_OUT_HIGH)
+
+/* I2C pins - Alternate function below configures I2C module on these pins */
+GPIO(EC_I2C1_USB_C0_SCL,       PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C1_USB_C0_SDA,       PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C2_USB_C1_SCL,       PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C2_USB_C1_SDA,       PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C3_USB_1_MIX_SCL,    PIN(D, 1), GPIO_INPUT)
+GPIO(EC_I2C3_USB_1_MIX_SDA,    PIN(D, 0), GPIO_INPUT)
+GPIO(EC_I2C5_BATTERY_SCL,      PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C5_BATTERY_SDA,      PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C7_EEPROM_PWR_SCL_R, PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C7_EEPROM_PWR_SDA_R, PIN(B, 2), GPIO_INPUT)
+
+/* Battery signals */
+GPIO(EC_BATT_PRES_ODL, 		PIN(E, 1), GPIO_INPUT)
+
+/* Alternate functions GPIO definitions */
+ALTERNATE(PIN_MASK(9, BIT(0) | BIT(2) | BIT(1)), 0, MODULE_I2C, 0)                   /* I2C1 SCL / I2C2 */
+ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)                                     /* I2C1 SDA */
+ALTERNATE(PIN_MASK(D, BIT(1) | BIT(0)), 0, MODULE_I2C, 0)                            /* I2C3 */
+ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)                            /* I2C5 */
+ALTERNATE(PIN_MASK(B, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)                            /* I2C7 */
+
+/* Fan signals */
+GPIO(EN_PP5000_FAN,            PIN(6, 1), GPIO_OUT_LOW)
+ALTERNATE(PIN_MASK(B, BIT(7)), 0, MODULE_PWM, 0)	/* FAN_PWM */
+ALTERNATE(PIN_MASK(4, BIT(0)), 0, MODULE_PWM, 0)	/* FAN_SPEED_TACH */
+
+/* Keyboard pins */
+#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_00-01 */
+ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_02-07 */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_00-01 */
+GPIO(EC_KSO_02_INV, PIN(1, 7),                        GPIO_OUT_LOW)  /* KSO_02 */
+ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_03-09 */
+ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_10-13 */
+ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_14 */
+ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)                     /* EC_KB_BL_PWM */
+
+/* UART */
+ALTERNATE(PIN_MASK(6, BIT(5) | BIT(4)), 0, MODULE_UART, 0)                           /* UART from EC to Servo */
+
+/* Power Switch Logic (PSL) inputs */
+ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)                    /* GPIOD2 = EC_LID_OPEN */
+ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)  /* GPIO00 = ACOK_OD,
+                                                                       GPIO01 = H1_EC_PWR_BTN_ODL
+                                                                       GPIO02 = EC_RST_ODL */
+
+/* Temperature sensors */
+ALTERNATE(PIN_MASK(4, BIT(2) | BIT(4) | BIT(5)), 0, MODULE_ADC, 0) /* TEMP_SENSOR1,2,4 */
+ALTERNATE(PIN_MASK(F, BIT(1)), 0, MODULE_ADC, 0) /* TEMP_SENSOR3 */
diff --git a/board/chronicler/keyboard.c b/board/chronicler/keyboard.c
new file mode 100644
index 0000000000..9e04d77ca3
--- /dev/null
+++ b/board/chronicler/keyboard.c
@@ -0,0 +1,26 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Keyboard config common to ECOS and zephyr */
+
+#include "keyboard_raw.h"
+#include "keyboard_scan.h"
+#include "timer.h"
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/* Increase from 50 us, because KSO_02 passes through the H1. */
+	.output_settle_us = 80,
+	/* Other values should be the same as the default configuration. */
+	.debounce_down_us = 9 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
+		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
+	},
+};
diff --git a/board/chronicler/led.c b/board/chronicler/led.c
new file mode 100644
index 0000000000..81e2656543
--- /dev/null
+++ b/board/chronicler/led.c
@@ -0,0 +1,203 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power and battery LED control for Chronicler
+ */
+
+#include "battery.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "chipset.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "led_common.h"
+
+#define BAT_LED_ON 0
+#define BAT_LED_OFF 1
+
+#define POWER_LED_ON 0
+#define POWER_LED_OFF 1
+
+#define LED_CYCLE_TIME_MS (2 * 1000)
+#define LED_TICKS_PER_CYCLE (LED_CYCLE_TIME_MS / HOOK_TICK_INTERVAL_MS)
+#define LED_ON_TIME_MS (1 * 1000)
+#define LED_ON_TICKS (LED_ON_TIME_MS / HOOK_TICK_INTERVAL_MS)
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_LEFT_LED,
+	EC_LED_ID_RIGHT_LED,
+};
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+enum led_color {
+	LED_OFF = 0,
+	LED_AMBER,
+	LED_WHITE,
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
+};
+
+enum led_port { RIGHT_PORT = 0, LEFT_PORT };
+
+static void led_set_color_battery(enum led_port port, enum led_color color)
+{
+	enum gpio_signal amber_led, white_led;
+
+	amber_led = (port == RIGHT_PORT ? GPIO_C0_CHARGE_LED_AMBER_L :
+					  GPIO_C1_CHARGE_LED_AMBER_L);
+	white_led = (port == RIGHT_PORT ? GPIO_C0_CHARGE_LED_WHITE_L :
+					  GPIO_C1_CHARGE_LED_WHITE_L);
+
+	switch (color) {
+	case LED_WHITE:
+		gpio_set_level(white_led, BAT_LED_ON);
+		gpio_set_level(amber_led, BAT_LED_OFF);
+		break;
+	case LED_AMBER:
+		gpio_set_level(white_led, BAT_LED_OFF);
+		gpio_set_level(amber_led, BAT_LED_ON);
+		break;
+	case LED_OFF:
+		gpio_set_level(white_led, BAT_LED_OFF);
+		gpio_set_level(amber_led, BAT_LED_OFF);
+		break;
+	default:
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	switch (led_id) {
+	case EC_LED_ID_LEFT_LED:
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		break;
+	case EC_LED_ID_RIGHT_LED:
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		break;
+	default:
+		break;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	switch (led_id) {
+	case EC_LED_ID_LEFT_LED:
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_battery(LEFT_PORT, LED_WHITE);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(LEFT_PORT, LED_AMBER);
+		else
+			led_set_color_battery(LEFT_PORT, LED_OFF);
+		break;
+	case EC_LED_ID_RIGHT_LED:
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_battery(RIGHT_PORT, LED_WHITE);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(RIGHT_PORT, LED_AMBER);
+		else
+			led_set_color_battery(RIGHT_PORT, LED_OFF);
+		break;
+	default:
+		return EC_ERROR_PARAM1;
+	}
+
+	return EC_SUCCESS;
+}
+
+/*
+ * Set active charge port color to the parameter, turn off all others.
+ * If no port is active (-1), turn off all LEDs.
+ */
+static void set_active_port_color(enum led_color color)
+{
+	int port = charge_manager_get_active_charge_port();
+
+	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
+		led_set_color_battery(RIGHT_PORT,
+				      (port == RIGHT_PORT) ? color : LED_OFF);
+	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
+		led_set_color_battery(LEFT_PORT,
+				      (port == LEFT_PORT) ? color : LED_OFF);
+}
+
+static void led_set_battery(void)
+{
+	static int battery_ticks;
+	static int suspend_ticks;
+
+	battery_ticks++;
+
+	/*
+	 * Override battery LEDs for Chronicler, Chronicler doesn't
+	 * have power LED, blinking both two side battery white
+	 * LEDs to indicate system suspend without charging state.
+	 */
+	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
+	    led_pwr_get_state() != LED_PWRS_CHARGE) {
+		suspend_ticks++;
+
+		led_set_color_battery(
+			RIGHT_PORT, suspend_ticks & 0x4 ? LED_WHITE : LED_OFF);
+		led_set_color_battery(
+			LEFT_PORT, suspend_ticks & 0x4 ? LED_WHITE : LED_OFF);
+		return;
+	}
+
+	suspend_ticks = 0;
+
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
+		/* Always indicate when charging, even in suspend. */
+		set_active_port_color(LED_AMBER);
+		break;
+	case LED_PWRS_DISCHARGE:
+		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
+			if (charge_get_percent() < 10)
+				led_set_color_battery(
+					RIGHT_PORT,
+					(battery_ticks % LED_TICKS_PER_CYCLE <
+					 LED_ON_TICKS) ?
+						LED_WHITE :
+						LED_OFF);
+			else
+				led_set_color_battery(RIGHT_PORT, LED_OFF);
+		}
+
+		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
+			led_set_color_battery(LEFT_PORT, LED_OFF);
+		break;
+	case LED_PWRS_ERROR:
+		set_active_port_color((battery_ticks & 0x2) ? LED_WHITE :
+							      LED_OFF);
+		break;
+	case LED_PWRS_CHARGE_NEAR_FULL:
+		set_active_port_color(LED_WHITE);
+		break;
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		set_active_port_color(LED_WHITE);
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		set_active_port_color(
+			(battery_ticks % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
+				LED_AMBER :
+				LED_OFF);
+		break;
+	default:
+		/* Other states don't alter LED behavior */
+		break;
+	}
+}
+
+/* Called by hook task every TICK */
+static void led_tick(void)
+{
+	led_set_battery();
+}
+DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
diff --git a/board/chronicler/usbc_config.c b/board/chronicler/usbc_config.c
new file mode 100644
index 0000000000..55ef253c5b
--- /dev/null
+++ b/board/chronicler/usbc_config.c
@@ -0,0 +1,279 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Volteer family-specific USB-C configuration */
+#include "cbi_ec_fw_config.h"
+#include "common.h"
+#include "driver/bc12/pi3usb9201_public.h"
+#include "driver/ppc/sn5s330_public.h"
+#include "driver/ppc/syv682x_public.h"
+#include "driver/retimer/bb_retimer_public.h"
+#include "driver/retimer/ps8811.h"
+#include "driver/tcpm/ps8xxx_public.h"
+#include "driver/tcpm/rt1715_public.h"
+#include "driver/tcpm/tcpci.h"
+#include "driver/tcpm/tusb422_public.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "system.h"
+#include "timer.h"
+#include "usb_mux.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
+
+/*
+ * USB3 DB mux configuration - the top level mux still needs to be set to the
+ * virtual_usb_mux_driver so the AP gets notified of mux changes and updates
+ * the TCSS configuration on state changes.
+ */
+static const struct usb_mux_chain usbc1_usb3_db_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
+	.next = NULL,
+};
+
+/******************************************************************************/
+/* USBC PPC configuration */
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+		.drv = &sn5s330_drv,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C1,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.frs_en = GPIO_USB_C1_FRS_EN,
+		.drv = &syv682x_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/******************************************************************************/
+/* PPC support routines */
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		sn5s330_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C1);
+		break;
+	default:
+		break;
+	}
+}
+
+/******************************************************************************/
+/* USBC TCPC configuration */
+const struct tcpc_config_t tcpc_config[] = {
+	[USBC_PORT_C0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0,
+			.addr_flags = RT1715_I2C_ADDR_FLAGS,
+		},
+		.drv = &rt1715_tcpm_drv,
+	},
+	[USBC_PORT_C1] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C1,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V,
+		.drv = &ps8xxx_tcpm_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
+BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
+
+/******************************************************************************/
+/* USB-A charging control */
+
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_PP5000_USBA,
+};
+
+/******************************************************************************/
+/* USBC mux configuration - Tiger Lake includes internal mux */
+const struct usb_mux_chain usb_muxes[] = {
+	[USBC_PORT_C0] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+	},
+	[USBC_PORT_C1] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc1_usb3_db_retimer,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
+
+static void ps8815_reset(void)
+{
+	int val;
+
+	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 0);
+	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS));
+	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 1);
+	msleep(PS8815_FW_INIT_DELAY_MS);
+
+	/*
+	 * b/144397088
+	 * ps8815 firmware 0x01 needs special configuration
+	 */
+
+	CPRINTS("%s: patching ps8815 registers", __func__);
+
+	if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) ==
+	    EC_SUCCESS)
+		CPRINTS("ps8815: reg 0x0f was %02x", val);
+
+	if (i2c_write8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f,
+		       0x31) == EC_SUCCESS)
+		CPRINTS("ps8815: reg 0x0f set to 0x31");
+
+	if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) ==
+	    EC_SUCCESS)
+		CPRINTS("ps8815: reg 0x0f now %02x", val);
+}
+
+/*
+ * Adjust USB3 settings to improve signal integrity.
+ * See b/194985848.
+ */
+__override void board_ps8xxx_tcpc_init(int port)
+{
+	int rv;
+
+	CPRINTS("%s", __func__);
+
+	/* TX1 EQ 19db / TX2 EQ 19db */
+	rv = tcpc_addr_write(port, PS8XXX_I2C_ADDR1_P1_FLAGS, 0x20, 0x77);
+	/* RX1 EQ 12db / RX2 EQ 13db */
+	rv |= tcpc_addr_write(port, PS8XXX_I2C_ADDR1_P1_FLAGS, 0x22, 0x32);
+	/* Swing level for upstream port output */
+	rv |= tcpc_addr_write(port, PS8XXX_I2C_ADDR1_P1_FLAGS, 0xc4, 0x03);
+
+	if (rv)
+		CPRINTS("%s fail!", __func__);
+}
+
+/* Called on AP S5 -> S0 transition */
+void board_ps8811_init(void)
+{
+	int rv;
+	const int port = I2C_PORT_USB_1_MIX;
+	const int addr = PS8811_I2C_ADDR_FLAGS0 + PS8811_REG_PAGE1;
+
+	CPRINTS("%s", __func__);
+
+	/* AEQ 12db */
+	rv = i2c_write8(port, addr, 0x01, 0x26);
+	/* ADE 2.1db */
+	rv |= i2c_write8(port, addr, 0x02, 0x60);
+	/* BEQ 10.5db */
+	rv |= i2c_write8(port, addr, 0x05, 0x16);
+	/* BDE 2.1db */
+	rv |= i2c_write8(port, addr, 0x06, 0x63);
+	/* Channel A swing level */
+	rv |= i2c_write8(port, addr, 0x66, 0x20);
+	/* Channel B swing level */
+	rv |= i2c_write8(port, addr, 0xa4, 0x03);
+	/* PS level foe B channel */
+	rv |= i2c_write8(port, addr, 0xa5, 0x83);
+	/* DE level foe B channel */
+	rv |= i2c_write8(port, addr, 0xa6, 0x14);
+
+	if (rv)
+		CPRINTS("%s fail!", __func__);
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_ps8811_init, HOOK_PRIO_LAST);
+
+void board_reset_pd_mcu(void)
+{
+	/* No reset available for TCPC on port 0 */
+	/* Daughterboard specific reset for port 1 */
+	ps8815_reset();
+	usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+}
+
+static void board_tcpc_init(void)
+{
+	/* Don't reset TCPCs after initial reset */
+	if (!system_jumped_late())
+		board_reset_pd_mcu();
+
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
+
+	/* Enable BC1.2 interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
+
+/******************************************************************************/
+/* BC1.2 charger detect configuration */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C1,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
+
+/******************************************************************************/
+/* TCPC support routines */
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	/*
+	 * Check which port has the ALERT line set
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL))
+		status |= PD_STATUS_TCPC_ALERT_0;
+	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL))
+		status |= PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
+
+/******************************************************************************/
+
+int ppc_get_alert_status(int port)
+{
+	if (port == USBC_PORT_C0)
+		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
+	else
+		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
+}
diff --git a/board/chronicler/usbc_config.h b/board/chronicler/usbc_config.h
new file mode 100644
index 0000000000..7428d0c436
--- /dev/null
+++ b/board/chronicler/usbc_config.h
@@ -0,0 +1,16 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* volteer board-specific USB-C configuration */
+
+#ifndef __CROS_EC_USBC_CONFIG_H
+#define __CROS_EC_USBC_CONFIG_H
+
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
+
+/* Configure the USB3 daughterboard type */
+void config_usb3_db_type(void);
+
+#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/chronicler/vif_override.xml b/board/chronicler/vif_override.xml
new file mode 100644
index 0000000000..29dd5642e3
--- /dev/null
+++ b/board/chronicler/vif_override.xml
@@ -0,0 +1,114 @@
+<?xml version="1.0" encoding="utf-8"?>
+<vif:VIF xmlns="http://usb.org/VendorInfoFile.xsd">
+  <vif:Model_Part_Number>Volteer RT1715</Model_Part_Number>
+  <vif:Product_Revision>0</Product_Revision>
+  <vif:TID>0</TID>
+  <vif:Product>
+    <!-- Information about TGL USB4 provided by Intel. See b/172963736 -->
+    <vif:USB4_Num_Internal_Host_Controllers value="1" />
+    <vif:USB4_Num_PCIe_DN_Bridges value="0" />
+    <vif:USB4RouterList>
+      <vif:Usb4Router>
+        <vif:USB4_Router_ID value="1" />
+        <vif:USB4_Silicon_VID value="32903">8087</USB4_Silicon_VID>
+        <vif:USB4_Num_Lane_Adapters value="4" />
+        <vif:USB4_Num_USB3_DN_Adapters value="1" />
+        <vif:USB4_Num_DP_IN_Adapters value="1" />
+        <vif:USB4_Num_DP_OUT_Adapters value="0" />
+        <vif:USB4_Num_PCIe_DN_Adapters value="4" />
+        <vif:USB4_TBT3_Not_Supported value="0">TBT3 Compatible</USB4_TBT3_Not_Supported>
+        <vif:USB4_PCIe_Wake_Supported value="true" />
+        <vif:USB4_USB3_Wake_Supported value="false" />
+        <vif:USB4_Num_Unused_Adapters value="0" />
+        <vif:USB4_TBT3_VID value="32903">8087</USB4_TBT3_VID>
+        <vif:USB4_PCIe_Switch_Vendor_ID value="32902">8086</USB4_PCIe_Switch_Vendor_ID>
+        <vif:USB4_PCIe_Switch_Device_ID value="39451">9A1B</USB4_PCIe_Switch_Device_ID>
+      </vif:Usb4Router>
+      <vif:Usb4Router>
+        <vif:USB4_Router_ID value="0" />
+        <vif:USB4_Silicon_VID value="32903">8087</USB4_Silicon_VID>
+        <vif:USB4_Num_Lane_Adapters value="2" />
+        <vif:USB4_Num_USB3_DN_Adapters value="1" />
+        <vif:USB4_Num_DP_IN_Adapters value="0" />
+        <vif:USB4_Num_DP_OUT_Adapters value="0" />
+        <vif:USB4_Num_PCIe_DN_Adapters value="0" />
+        <vif:USB4_TBT3_Not_Supported value="1">Not TBT3-Compatible</USB4_TBT3_Not_Supported>
+        <vif:USB4_PCIe_Wake_Supported value="false" />
+        <vif:USB4_USB3_Wake_Supported value="false" />
+        <vif:USB4_Num_Unused_Adapters value="0" />
+      </vif:Usb4Router>
+    </vif:USB4RouterList>
+  </vif:Product>
+  <vif:Component>
+    <!-- Port 0 is USB3-only. -->
+    <vif:USB4_Supported value="false">NO</USB4_Supported>
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!-- Add in missing fields for SrcPdo0, derived from SYV682B datasheet. -->
+        <vif:Src_PD_OCP_OC_Debounce value="50">50 msec</Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="360">3600 mA</Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+    <vif:DFP_VDO_Port_Number value="0" />
+    <vif:Modal_Operation_Supported_SOP value="false" />
+  </vif:Component>
+  <vif:Component>
+    <vif:USB4_Max_Speed value="1">Gen 3 (40Gb)</USB4_Max_Speed>
+    <vif:USB4_DFP_Supported value="true" />
+    <vif:USB4_UFP_Supported value="false" />
+    <vif:USB4_USB3_Tunneling_Supported value="true" />
+    <vif:USB4_DP_Tunneling_Supported value="true" />
+    <vif:USB4_PCIe_Tunneling_Supported value="true" />
+    <vif:USB4_TBT3_Compatibility_Supported value="true" />
+    <vif:USB4_CL1_State_Supported value="true" />
+    <vif:USB4_CL2_State_Supported value="true" />
+    <vif:USB4_Num_Retimers value="1" />
+    <vif:USB4_DP_Bit_Rate value="3">HBR3</USB4_DP_Bit_Rate>
+    <vif:USB4_Num_DP_Lanes value="4">4 Lanes</USB4_Num_DP_Lanes>
+    <vif:USB4_Lane_0_Adapter value="1" />
+    <vif:Host_Supports_USB_Data value="true" />
+    <vif:Host_Speed value="2">USB 3.2 Gen 2x1</Host_Speed>
+    <vif:Host_Contains_Captive_Retimer value="true" />
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:Host_Suspend_Supported value="true" />
+    <vif:Is_DFP_On_Hub value="false" />
+    <vif:USB_Suspend_May_Be_Cleared value="true" />
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="3">3A @ 5V</FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <vif:FR_Swap_Supported_As_Initial_Sink value="true" />
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!-- Add in missing fields for SrcPdo0, derived from SYV682B datasheet. -->
+        <vif:Src_PD_OCP_OC_Debounce value="50">50 msec</Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="360">3600 mA</Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+    <vif:Data_Capable_As_USB_Host_SOP value="true" />
+    <vif:Data_Capable_As_USB_Device_SOP value="false" />
+    <!-- TODO(b/173028252): Figure out the appropriate Discover Identity ACK for
+         Volteer and update the EC and VIF accordingly. -->
+    <vif:Product_Type_UFP_SOP value="3">PSD</Product_Type_UFP_SOP>
+    <vif:Product_Type_DFP_SOP value="4">Alternate Mode Controller (AMC)</Product_Type_DFP_SOP>
+    <vif:DFP_VDO_Port_Number value="1" />
+    <vif:Modal_Operation_Supported_SOP value="true" />
+    <vif:USB_VID_SOP value="6353">18D1</USB_VID_SOP>
+    <vif:bcdDevice_SOP value="0">0000</bcdDevice_SOP>
+    <vif:SVID_Fixed_SOP value="true" />
+    <vif:Num_SVIDs_Min_SOP value="1" />
+    <vif:Num_SVIDs_Max_SOP value="1" />
+    <vif:SOPSVIDList>
+      <vif:SOPSVID>
+        <vif:SVID_SOP value="32903">8087</SVID_SOP>
+        <vif:SVID_Modes_Fixed_SOP value="true" />
+        <vif:SVID_Num_Modes_Min_SOP value="1" />
+        <vif:SVID_Num_Modes_Max_SOP value="1" />
+        <vif:SOPSVIDModeList>
+          <vif:SOPSVIDMode>
+            <vif:SVID_Mode_Enter_SOP value="true" />
+            <vif:SVID_Mode_Recog_Value_SOP value="0">00000000</SVID_Mode_Recog_Value_SOP>
+          </vif:SOPSVIDMode>
+        </vif:SOPSVIDModeList>
+      </vif:SOPSVID>
+    </vif:SOPSVIDList>
+  </vif:Component>
+</vif:VIF>
diff --git a/board/coachz/base_detect.c b/board/coachz/base_detect.c
index ae485dc5ee..fbae1698de 100644
--- a/board/coachz/base_detect.c
+++ b/board/coachz/base_detect.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,7 @@
 /* Coachz base detection code */
 
 #include "adc.h"
-#include "adc_chip.h"
+#include "base_state.h"
 #include "board.h"
 #include "chipset.h"
 #include "common.h"
@@ -19,11 +19,12 @@
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
 /* Base detection and debouncing */
-#define BASE_DETECT_DEBOUNCE_US (20 * MSEC)
+#define BASE_DETECT_EN_DEBOUNCE_US (350 * MSEC)
+#define BASE_DETECT_DIS_DEBOUNCE_US (20 * MSEC)
 
 /*
  * If the base status is unclear (i.e. not within expected ranges, read
@@ -80,9 +81,9 @@ static void base_detect_change(enum base_status status)
 	if (current_base_status == status)
 		return;
 
-	CPRINTS("Base %sconnected", connected ? "" : "not ");
 	gpio_set_level(GPIO_EN_BASE, connected);
-	tablet_set_mode(!connected);
+	tablet_set_mode(!connected, TABLET_TRIGGER_BASE);
+	base_set_state(connected);
 	current_base_status = status;
 }
 
@@ -92,8 +93,8 @@ static uint32_t pulse_width;
 
 static void print_base_detect_value(int v, int tmp_pulse_width)
 {
-	CPRINTS("%s = %d (pulse %d)", adc_channels[ADC_BASE_DET].name,
-			v, tmp_pulse_width);
+	CPRINTS("%s = %d (pulse %d)", adc_channels[ADC_BASE_DET].name, v,
+		tmp_pulse_width);
 }
 
 static void base_detect_deferred(void)
@@ -142,6 +143,12 @@ static inline int detect_pin_connected(enum gpio_signal det_pin)
 void base_detect_interrupt(enum gpio_signal signal)
 {
 	uint64_t time_now = get_time().val;
+	int debounce_us;
+
+	if (detect_pin_connected(signal))
+		debounce_us = BASE_DETECT_EN_DEBOUNCE_US;
+	else
+		debounce_us = BASE_DETECT_DIS_DEBOUNCE_US;
 
 	if (base_detect_debounce_time <= time_now) {
 		/*
@@ -158,8 +165,7 @@ void base_detect_interrupt(enum gpio_signal signal)
 		}
 		pulse_width = 0;
 
-		hook_call_deferred(&base_detect_deferred_data,
-				   BASE_DETECT_DEBOUNCE_US);
+		hook_call_deferred(&base_detect_deferred_data, debounce_us);
 	} else {
 		if (current_base_status == BASE_CONNECTED &&
 		    detect_pin_connected(signal) && !pulse_width &&
@@ -172,7 +178,7 @@ void base_detect_interrupt(enum gpio_signal signal)
 		}
 	}
 
-	base_detect_debounce_time = time_now + BASE_DETECT_DEBOUNCE_US;
+	base_detect_debounce_time = time_now + debounce_us;
 }
 
 static void base_enable(void)
@@ -186,9 +192,13 @@ DECLARE_HOOK(HOOK_CHIPSET_STARTUP, base_enable, HOOK_PRIO_DEFAULT);
 
 static void base_disable(void)
 {
-	/* Disable base detection interrupt and disable power to base. */
+	/*
+	 * Disable base detection interrupt and disable power to base.
+	 * Set the state UNKNOWN so the next startup will initialize a
+	 * correct state and notify AP.
+	 */
 	gpio_disable_interrupt(GPIO_BASE_DET_L);
-	base_detect_change(BASE_DISCONNECTED);
+	base_detect_change(BASE_UNKNOWN);
 }
 DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, base_disable, HOOK_PRIO_DEFAULT);
 
@@ -201,15 +211,15 @@ static void base_init(void)
 	if (system_jumped_late() && chipset_in_state(CHIPSET_STATE_ON))
 		base_enable();
 }
-DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT+1);
+DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT + 1);
 
-void base_force_state(int state)
+void base_force_state(enum ec_set_base_state_cmd state)
 {
-	if (state == 1) {
+	if (state == EC_SET_BASE_STATE_ATTACH) {
 		gpio_disable_interrupt(GPIO_BASE_DET_L);
 		base_detect_change(BASE_CONNECTED);
 		CPRINTS("BD forced connected");
-	} else if (state == 0) {
+	} else if (state == EC_SET_BASE_STATE_DETACH) {
 		gpio_disable_interrupt(GPIO_BASE_DET_L);
 		base_detect_change(BASE_DISCONNECTED);
 		CPRINTS("BD forced disconnected");
diff --git a/board/coachz/battery.c b/board/coachz/battery.c
index a97395ca73..a89b26f49a 100644
--- a/board/coachz/battery.c
+++ b/board/coachz/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -33,6 +33,66 @@
  */
 
 const struct board_batt_params board_battery_info[] = {
+	/* COSMX GH02047XL 333-1C-DA-A */
+	[BATTERY_GH02047XL_1C] = {
+		.fuel_gauge = {
+			.manuf_name = "333-1C-DA-A",
+			.device_name = "GH02047XL",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0002,
+				.disconnect_val = 0x0,
+			}
+		},
+		.batt_info = {
+			.voltage_max            = 8800, /* mV */
+			.voltage_normal         = 7700, /* mV */
+			.voltage_min            = 6000, /* mV */
+			.precharge_current      = 256,  /* mA */
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 45,
+			.charging_min_c         = 0,
+			.charging_max_c         = 45,
+			.discharging_min_c      = -10,
+			.discharging_max_c      = 60,
+			.vendor_param_start     = 0x70,
+		},
+	},
+	/* COSMX GH02047XL */
+	[BATTERY_GH02047XL] = {
+		.fuel_gauge = {
+			.manuf_name = "333-AC-DA-A",
+			.device_name = "GH02047XL",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0002,
+				.disconnect_val = 0x0,
+			}
+		},
+		.batt_info = {
+			.voltage_max            = 8800, /* mV */
+			.voltage_normal         = 7700, /* mV */
+			.voltage_min            = 6000, /* mV */
+			.precharge_current      = 256,  /* mA */
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 45,
+			.charging_min_c         = 0,
+			.charging_max_c         = 45,
+			.discharging_min_c      = -10,
+			.discharging_max_c      = 60,
+			.vendor_param_start     = 0x70,
+		},
+	},
 	/* COSMX DS02032XL */
 	[BATTERY_DS02032XL] = {
 		.fuel_gauge = {
@@ -60,6 +120,37 @@ const struct board_batt_params board_battery_info[] = {
 			.charging_max_c         = 45,
 			.discharging_min_c      = -10,
 			.discharging_max_c      = 60,
+			.vendor_param_start     = 0x70,
+		},
+	},
+	/* SMP DS02032XL */
+	[BATTERY_DS02032XL_1C] = {
+		.fuel_gauge = {
+			.manuf_name = "333-1C-13-A",
+			.device_name = "DS02032XL",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0002,
+				.disconnect_val = 0x0,
+			}
+		},
+		.batt_info = {
+			.voltage_max            = 8800, /* mV */
+			.voltage_normal         = 7700, /* mV */
+			.voltage_min            = 6000, /* mV */
+			.precharge_current      = 256,  /* mA */
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 45,
+			.charging_min_c         = 0,
+			.charging_max_c         = 45,
+			.discharging_min_c      = -10,
+			.discharging_max_c      = 60,
+			.vendor_param_start     = 0x70,
 		},
 	},
 };
diff --git a/board/coachz/board.c b/board/coachz/board.c
index 3e9b46655b..d1ab5fb647 100644
--- a/board/coachz/board.c
+++ b/board/coachz/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,30 +9,37 @@
 #include "button.h"
 #include "charge_manager.h"
 #include "charge_state.h"
-#include "extpower.h"
+#include "common.h"
 #include "driver/accel_bma2x2.h"
+#include "driver/accelgyro_bmi260.h"
 #include "driver/accelgyro_bmi_common.h"
 #include "driver/ppc/sn5s330.h"
 #include "driver/tcpm/ps8xxx.h"
 #include "driver/tcpm/tcpci.h"
+#include "extpower.h"
 #include "gpio.h"
 #include "hooks.h"
-#include "keyboard_scan.h"
 #include "lid_switch.h"
+#include "mkbp_input_devices.h"
+#include "peripheral_charger.h"
 #include "pi3usb9201.h"
 #include "power.h"
+#include "power/qcom.h"
 #include "power_button.h"
 #include "pwm.h"
 #include "pwm_chip.h"
-#include "system.h"
+#include "queue.h"
 #include "shi_chip.h"
 #include "switch.h"
+#include "system.h"
 #include "tablet_mode.h"
 #include "task.h"
 #include "usbc_ppc.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+#define KS_DEBOUNCE_US (30 * MSEC) /* Debounce time for kickstand switch */
 
 /* Forward declaration */
 static void tcpc_alert_event(enum gpio_signal signal);
@@ -40,9 +47,45 @@ static void usb0_evt(enum gpio_signal signal);
 static void usb1_evt(enum gpio_signal signal);
 static void ppc_interrupt(enum gpio_signal signal);
 static void board_connect_c0_sbu(enum gpio_signal s);
+static void ks_interrupt(enum gpio_signal s);
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
+/*
+ * Workaround for b/193223400. This disables the IRQ from CTN730. Fixing this
+ * here (using a rather awkward way) separates the fix from the common code.
+ */
+#ifdef SECTION_IS_RW
+#define GPIO_PCHG_P0 GPIO_WLC_IRQ_CONN
+#else
+#define GPIO_PCHG_P0 ARRAY_SIZE(gpio_irq_handlers)
+#endif
+
+extern struct pchg_drv ctn730_drv;
+
+struct pchg pchgs[] = {
+	[0] = {
+		.cfg = &(const struct pchg_config) {
+			.drv = &ctn730_drv,
+			.i2c_port = I2C_PORT_WLC,
+			.irq_pin = GPIO_PCHG_P0,
+			.full_percent = 96,
+			.block_size = 128,
+		},
+		.policy = {
+			[PCHG_CHIPSET_STATE_ON] = &pchg_policy_on,
+			[PCHG_CHIPSET_STATE_SUSPEND] = &pchg_policy_suspend,
+		},
+		.events = QUEUE_NULL(PCHG_EVENT_QUEUE_SIZE, enum pchg_event),
+	},
+};
+
+int board_get_pchg_count(void)
+{
+	return ARRAY_SIZE(pchgs);
+}
+
 /* GPIO Interrupt Handlers */
 static void tcpc_alert_event(enum gpio_signal signal)
 {
@@ -64,12 +107,12 @@ static void tcpc_alert_event(enum gpio_signal signal)
 
 static void usb0_evt(enum gpio_signal signal)
 {
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
 }
 
 static void usb1_evt(enum gpio_signal signal)
 {
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12, 0);
+	usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
 }
 
 static void ppc_interrupt(enum gpio_signal signal)
@@ -101,20 +144,91 @@ static void board_connect_c0_sbu(enum gpio_signal s)
 	hook_call_deferred(&board_connect_c0_sbu_deferred_data, 0);
 }
 
+static int debounced_ks_attached;
+static int debounced_ks_open;
+
+/**
+ * Kickstand switch initialization
+ */
+static void ks_init(void)
+{
+	debounced_ks_attached = !gpio_get_level(GPIO_KS_ATTACHED_L);
+	debounced_ks_open = gpio_get_level(GPIO_KS_OPEN);
+
+	/* Enable interrupts, now that we've initialized */
+	gpio_enable_interrupt(GPIO_KS_ATTACHED_L);
+	gpio_enable_interrupt(GPIO_KS_OPEN);
+}
+DECLARE_HOOK(HOOK_INIT, ks_init, HOOK_PRIO_INIT_SWITCH);
+
+/**
+ * Handle debounced kickstand switch changing state.
+ */
+static void ks_change_deferred(void)
+{
+	const int ks_attached = !gpio_get_level(GPIO_KS_ATTACHED_L);
+	const int ks_open = gpio_get_level(GPIO_KS_OPEN);
+	int proximity_detected;
+
+	/* If the switches haven't changed, nothing to do */
+	if (ks_attached == debounced_ks_attached &&
+	    ks_open == debounced_ks_open)
+		return;
+
+	/*
+	 * A heuristic method to use the kickstand position to approach
+	 * the human body proximity.
+	 */
+	proximity_detected = !(ks_attached && ks_open);
+	CPRINTS("ks %s %s -> proximity %s",
+		ks_attached ? "attached" : "detached",
+		ks_open ? "open" : "close", proximity_detected ? "on" : "off");
+
+	debounced_ks_attached = ks_attached;
+	debounced_ks_open = ks_open;
+
+	body_detect_change_state(proximity_detected, false);
+}
+DECLARE_DEFERRED(ks_change_deferred);
+
+static void ks_interrupt(enum gpio_signal s)
+{
+	/* Reset kickstand debounce time */
+	hook_call_deferred(&ks_change_deferred_data, KS_DEBOUNCE_US);
+}
+
 /* I2C port map */
 const struct i2c_port_t i2c_ports[] = {
-	{"power",   I2C_PORT_POWER,  100, GPIO_EC_I2C_POWER_SCL,
-					  GPIO_EC_I2C_POWER_SDA},
-	{"tcpc0",   I2C_PORT_TCPC0, 1000, GPIO_EC_I2C_USB_C0_PD_SCL,
-					  GPIO_EC_I2C_USB_C0_PD_SDA},
-	{"tcpc1",   I2C_PORT_TCPC1, 1000, GPIO_EC_I2C_USB_C1_PD_SCL,
-					  GPIO_EC_I2C_USB_C1_PD_SDA},
-	{"wlc",     I2C_PORT_WLC,   1000, GPIO_EC_I2C_WLC_SCL,
-					  GPIO_EC_I2C_WLC_SDA},
-	{"eeprom",  I2C_PORT_EEPROM, 400, GPIO_EC_I2C_EEPROM_SCL,
-					  GPIO_EC_I2C_EEPROM_SDA},
-	{"sensor",  I2C_PORT_SENSOR, 400, GPIO_EC_I2C_SENSOR_SCL,
-					  GPIO_EC_I2C_SENSOR_SDA},
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_POWER_SCL,
+	  .sda = GPIO_EC_I2C_POWER_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C0_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C0_PD_SDA },
+	{ .name = "tcpc1",
+	  .port = I2C_PORT_TCPC1,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C1_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C1_PD_SDA },
+	{ .name = "wlc",
+	  .port = I2C_PORT_WLC,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_WLC_SCL,
+	  .sda = GPIO_EC_I2C_WLC_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_EEPROM_SCL,
+	  .sda = GPIO_EC_I2C_EEPROM_SDA },
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_SENSOR_SCL,
+	  .sda = GPIO_EC_I2C_SENSOR_SDA },
 };
 
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
@@ -122,45 +236,25 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* Measure VBUS through a 1/10 voltage divider */
-	[ADC_VBUS] = {
-		"VBUS",
-		NPCX_ADC_CH1,
-		ADC_MAX_VOLT * 10,
-		ADC_READ_MAX + 1,
-		0
-	},
+	[ADC_VBUS] = { "VBUS", NPCX_ADC_CH1, ADC_MAX_VOLT * 10,
+		       ADC_READ_MAX + 1, 0 },
 	/*
 	 * Adapter current output or battery charging/discharging current (uV)
 	 * 18x amplification on charger side.
 	 */
-	[ADC_AMON_BMON] = {
-		"AMON_BMON",
-		NPCX_ADC_CH2,
-		ADC_MAX_VOLT * 1000 / 18,
-		ADC_READ_MAX + 1,
-		0
-	},
+	[ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH2, ADC_MAX_VOLT * 1000 / 18,
+			    ADC_READ_MAX + 1, 0 },
 	/*
 	 * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read
 	 * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and
 	 * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we
 	 * only divide by 2 (enough to avoid precision issues).
 	 */
-	[ADC_PSYS] = {
-		"PSYS",
-		NPCX_ADC_CH3,
-		ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1),
-		2,
-		0
-	},
+	[ADC_PSYS] = { "PSYS", NPCX_ADC_CH3,
+		       ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), 2, 0 },
 	/* Base detection */
-	[ADC_BASE_DET] = {
-		"BASE_DET",
-		NPCX_ADC_CH5,
-		ADC_MAX_VOLT,
-		ADC_READ_MAX + 1,
-		0
-	},
+	[ADC_BASE_DET] = { "BASE_DET", NPCX_ADC_CH5, ADC_MAX_VOLT,
+			   ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
@@ -172,16 +266,12 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
 /* Power Path Controller */
 struct ppc_config_t ppc_chips[] = {
-	{
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	{
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
+	{ .i2c_port = I2C_PORT_TCPC0,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
+	{ .i2c_port = I2C_PORT_TCPC1,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
 };
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
@@ -191,7 +281,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = I2C_PORT_TCPC0,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
 		},
 		.drv = &ps8xxx_tcpm_drv,
 	},
@@ -199,7 +289,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = I2C_PORT_TCPC1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
 		},
 		.drv = &ps8xxx_tcpm_drv,
 	},
@@ -212,16 +302,22 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
  * to AP. But the TCPC chip is also needed to know the HPD status; otherwise,
  * the mux misbehaves.
  */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	},
 	{
-		.usb_port = 1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	}
 };
 
@@ -241,13 +337,14 @@ const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
 static struct mutex g_lid_mutex;
 
 static struct bmi_drv_data_t g_bmi160_data;
+static struct bmi_drv_data_t g_bmi260_data;
+
+bool is_bmi260_present;
 
 /* Matrix to rotate accelerometer into standard reference frame */
-const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0,  0},
-	{ 0,  FLOAT_TO_FP(-1),  0},
-	{ 0,  0, FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+				      { FLOAT_TO_FP(1), 0, 0 },
+				      { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	/*
@@ -257,10 +354,10 @@ struct motion_sensor_t motion_sensors[] = {
 	 */
 	[LID_ACCEL] = {
 	 .name = "Lid Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3_S5,
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
 	 .chip = MOTIONSENSE_CHIP_BMI160,
 	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_BASE,
+	 .location = MOTIONSENSE_LOC_LID,
 	 .drv = &bmi160_drv,
 	 .mutex = &g_lid_mutex,
 	 .drv_data = &g_bmi160_data,
@@ -278,10 +375,10 @@ struct motion_sensor_t motion_sensors[] = {
 	},
 	[LID_GYRO] = {
 	 .name = "Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3_S5,
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
 	 .chip = MOTIONSENSE_CHIP_BMI160,
 	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
+	 .location = MOTIONSENSE_LOC_LID,
 	 .drv = &bmi160_drv,
 	 .mutex = &g_lid_mutex,
 	 .drv_data = &g_bmi160_data,
@@ -293,14 +390,102 @@ struct motion_sensor_t motion_sensors[] = {
 	 .max_frequency = BMI_GYRO_MAX_FREQ,
 	},
 };
+
+struct motion_sensor_t motion_sensors_260[] = {
+	/*
+	 * Note: bmi260: supports accelerometer and gyro sensor
+	 * Requirement: accelerometer sensor must init before gyro sensor
+	 * DO NOT change the order of the following table.
+	 */
+	[LID_ACCEL] = {
+	 .name = "Lid Accel",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_BMI260,
+	 .type = MOTIONSENSE_TYPE_ACCEL,
+	 .location = MOTIONSENSE_LOC_LID,
+	 .drv = &bmi260_drv,
+	 .mutex = &g_lid_mutex,
+	 .drv_data = &g_bmi260_data,
+	 .port = I2C_PORT_SENSOR,
+	 .i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
+	 .rot_standard_ref = &lid_standard_ref,
+	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
+	 .min_frequency = BMI_ACCEL_MIN_FREQ,
+	 .max_frequency = BMI_ACCEL_MAX_FREQ,
+	 .config = {
+		 [SENSOR_CONFIG_EC_S0] = {
+			 .odr = 10000 | ROUND_UP_FLAG,
+		 },
+	 },
+	},
+	[LID_GYRO] = {
+	 .name = "Gyro",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_BMI260,
+	 .type = MOTIONSENSE_TYPE_GYRO,
+	 .location = MOTIONSENSE_LOC_LID,
+	 .drv = &bmi260_drv,
+	 .mutex = &g_lid_mutex,
+	 .drv_data = &g_bmi260_data,
+	 .port = I2C_PORT_SENSOR,
+	 .i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
+	 .default_range = 1000, /* dps */
+	 .rot_standard_ref = &lid_standard_ref,
+	 .min_frequency = BMI_GYRO_MIN_FREQ,
+	 .max_frequency = BMI_GYRO_MAX_FREQ,
+	},
+};
+
 const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
+static void board_detect_motionsensor(void)
+{
+	int val = -1;
+
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return;
+
+	/* Check base accelgyro chip */
+	bmi_read8(motion_sensors[LID_ACCEL].port,
+		  motion_sensors[LID_ACCEL].i2c_spi_addr_flags, BMI260_CHIP_ID,
+		  &val);
+	if (val == BMI260_CHIP_ID_MAJOR) {
+		motion_sensors[LID_ACCEL] = motion_sensors_260[LID_ACCEL];
+		motion_sensors[LID_GYRO] = motion_sensors_260[LID_GYRO];
+		is_bmi260_present = 1;
+	} else {
+		is_bmi260_present = 0;
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_detect_motionsensor,
+	     HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_INIT, board_detect_motionsensor, HOOK_PRIO_DEFAULT + 1);
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	if (is_bmi260_present) {
+		bmi260_interrupt(signal);
+	} else {
+		bmi160_interrupt(signal);
+	}
+}
+
 /* Initialize board. */
 static void board_init(void)
 {
+	/*
+	 * The rev-1 hardware doesn't have the external pull-up fix for the bug
+	 * b/177611071. It requires rework to stuff the resistor. For people who
+	 * has difficulty to do the rework, this is a workaround, which makes
+	 * the GPIO push-pull, instead of open-drain.
+	 */
+	if (system_get_board_version() == 1)
+		gpio_set_flags(GPIO_HIBERNATE_L, GPIO_OUTPUT);
+
 	/* Enable BC1.2 interrupts */
 	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_L);
 	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L);
+	gpio_enable_interrupt(GPIO_ACCEL_GYRO_INT_L);
 
 	/*
 	 * The H1 SBU line for CCD are behind PPC chip. The PPC internal FETs
@@ -314,6 +499,15 @@ static void board_init(void)
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
+__overridable uint16_t board_get_ps8xxx_product_id(int port)
+{
+	/* Coachz board rev 2+ changes TCPC from 8805 to 8755*/
+	if (system_get_board_version() < 2)
+		return PS8805_PRODUCT_ID;
+
+	return PS8755_PRODUCT_ID;
+}
+
 void board_tcpc_init(void)
 {
 	/* Only reset TCPC if not sysjump */
@@ -324,6 +518,7 @@ void board_tcpc_init(void)
 
 	/* Enable PPC interrupts */
 	gpio_enable_interrupt(GPIO_USB_C0_SWCTL_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_SWCTL_INT_ODL);
 
 	/* Enable TCPC interrupts */
 	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
@@ -334,9 +529,36 @@ void board_tcpc_init(void)
 	 * HPD pulse to enable video path
 	 */
 	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		usb_mux_hpd_update(port, 0, 0);
+		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
+
+void board_hibernate(void)
+{
+	int i;
+
+	/*
+	 * Sensors are unpowered in hibernate. Apply PD to the
+	 * interrupt lines such that they don't float.
+	 */
+	gpio_set_flags(GPIO_ACCEL_GYRO_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
+
+	/*
+	 * Board rev 1+ has the hardware fix. Don't need the following
+	 * workaround.
+	 */
+	if (system_get_board_version() >= 1)
+		return;
+
+	/*
+	 * Enable the PPC power sink path before EC enters hibernate;
+	 * otherwise, ACOK won't go High and can't wake EC up. Check the
+	 * bug b/170324206 for details.
+	 */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
+		ppc_vbus_sink_enable(i, 1);
 }
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
 
 /* Called on AP S0 -> S3 transition */
 static void board_chipset_suspend(void)
@@ -416,8 +638,7 @@ void board_overcurrent_event(int port, int is_overcurrented)
 
 int board_set_active_charge_port(int port)
 {
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	int i;
 
 	if (!is_real_port && port != CHARGE_PORT_NONE)
@@ -445,7 +666,6 @@ int board_set_active_charge_port(int port)
 		return EC_ERROR_INVAL;
 	}
 
-
 	CPRINTS("New charge port: p%d", port);
 
 	/*
@@ -469,23 +689,20 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
 {
 	/*
 	 * Ignore lower charge ceiling on PD transition if our battery is
 	 * critical, as we may brownout.
 	 */
-	if (supplier == CHARGE_SUPPLIER_PD &&
-	    charge_ma < 1500 &&
+	if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 &&
 	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
 		CPRINTS("Using max ilim %d", max_ma);
 		charge_ma = max_ma;
 	}
 
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
+	charge_set_input_current_limit(charge_ma, charge_mv);
 }
 
 uint16_t tcpc_get_alert_status(void)
@@ -501,4 +718,3 @@ uint16_t tcpc_get_alert_status(void)
 
 	return status;
 }
-
diff --git a/board/coachz/board.h b/board/coachz/board.h
index b85d057604..e0786075df 100644
--- a/board/coachz/board.h
+++ b/board/coachz/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,45 +10,80 @@
 
 #include "baseboard.h"
 
-/* TODO(waihong): Remove the following bringup features */
-#define CONFIG_BRINGUP
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands. */
-#define CONFIG_USB_PD_DEBUG_LEVEL 3
-#define CONFIG_CMD_AP_RESET_LOG
-#define CONFIG_CMD_GPIO_EXTENDED
-#define CONFIG_CMD_POWERINDEBUG
-#define CONFIG_I2C_DEBUG
+/* On-body detection */
+#define CONFIG_BODY_DETECTION
+#define CONFIG_BODY_DETECTION_SENSOR LID_ACCEL
+#define CONFIG_BODY_DETECTION_VAR_NOISE_FACTOR 150 /* % */
+#define CONFIG_GESTURE_DETECTION
+#define CONFIG_GESTURE_DETECTION_MASK BIT(CONFIG_BODY_DETECTION_SENSOR)
+#define CONFIG_GESTURE_HOST_DETECTION
+
+#define CONFIG_BUTTON_TRIGGERED_RECOVERY
 
 /* Internal SPI flash on NPCX7 */
-#define CONFIG_FLASH_SIZE (512 * 1024)  /* 512KB internal spi flash */
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */
+
+/* Save some flash space */
+#define CONFIG_LTO
+#define CONFIG_USB_PD_DEBUG_LEVEL 2
+#undef CONFIG_CMD_FLASHINFO
+#undef CONFIG_CMD_MMAPINFO
+#undef CONFIG_CMD_ACCELSPOOF
+#undef CONFIG_CMD_ACCEL_FIFO
+#undef CONFIG_CMD_ACCEL_INFO
+#undef CONFIG_CMD_TASK_RESET
+#undef CONFIG_CONSOLE_CMDHELP
 
 /* Battery */
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY  "LION"
+#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
 #define CONFIG_BATTERY_REVIVE_DISCONNECT
 #define CONFIG_BATTERY_FUEL_GAUGE
+#define CONFIG_BATTERY_VENDOR_PARAM
+
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 5
 
 /* BC 1.2 Charger */
 #define CONFIG_BC12_DETECT_PI3USB9201
 
 /* USB */
+#define CONFIG_USB_PD_TCPM_MULTI_PS8XXX
+#define CONFIG_USB_PD_TCPM_PS8755
 #define CONFIG_USB_PD_TCPM_PS8805
 #define CONFIG_USBC_PPC_SN5S330
 #define CONFIG_USB_PD_PORT_MAX_COUNT 2
 
 /* BMI160 Lid accel/gyro */
 #define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCEL_INTERRUPTS
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
 #define OPT3001_I2C_ADDR_FLAGS OPT3001_I2C_ADDR1_FLAGS
+#define CONFIG_ACCELGYRO_BMI260
+#define CONFIG_ACCELGYRO_BMI260_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
 
 #define CONFIG_TABLET_MODE
 #define CONFIG_TABLET_MODE_SWITCH
+#define CONFIG_GMR_TABLET_MODE
+#define CONFIG_FRONT_PROXIMITY_SWITCH
+
+#define CONFIG_MKBP_INPUT_DEVICES
+
+#define CONFIG_DETACHABLE_BASE
+#define CONFIG_BASE_ATTACHED_SWITCH
 
 /* GPIO alias */
 #define GPIO_AC_PRESENT GPIO_CHG_ACOK_OD
 #define GPIO_WP_L GPIO_EC_FLASH_WP_ODL
 #define GPIO_PMIC_RESIN_L GPIO_PM845_RESIN_L
+#define GPIO_TABLET_MODE_L GPIO_LID_360_L
+#define GPIO_KS_ATTACHED_L GPIO_LID_INT_N_HALL1
+#define GPIO_KS_OPEN GPIO_LID_INT_N_HALL2
+
+/* WLC pins */
+#define CONFIG_PERIPHERAL_CHARGER
+#define CONFIG_DEVICE_EVENT
+#define CONFIG_CTN730
 
 #ifndef __ASSEMBLER__
 
@@ -70,30 +105,24 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_DISPLIGHT = 0,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_DISPLIGHT = 0, PWM_CH_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
+	BATTERY_GH02047XL_1C,
+	BATTERY_GH02047XL,
 	BATTERY_DS02032XL,
+	BATTERY_DS02032XL_1C,
 	BATTERY_TYPE_COUNT,
 };
 
-/* Swithcap functions */
-void board_set_switchcap_power(int enable);
-int board_is_switchcap_enabled(void);
-int board_is_switchcap_power_good(void);
-/* Custom function to indicate if sourcing VBUS */
-int board_is_sourcing_vbus(int port);
-/* Enable VBUS sink for a given port */
-int board_vbus_sink_enable(int port, int enable);
 /* Reset all TCPCs. */
 void board_reset_pd_mcu(void);
 void board_set_tcpc_power_mode(int port, int mode);
 /* Base detection */
 void base_detect_interrupt(enum gpio_signal signal);
+/* motion sensor interrupt */
+void motion_interrupt(enum gpio_signal signal);
 
 #endif /* !defined(__ASSEMBLER__) */
 
diff --git a/board/coachz/build.mk b/board/coachz/build.mk
index 5b6ecb0398..01678fc8bb 100644
--- a/board/coachz/build.mk
+++ b/board/coachz/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -11,4 +11,4 @@ CHIP_FAMILY:=npcx7
 CHIP_VARIANT:=npcx7m6fc
 BASEBOARD:=trogdor
 
-board-y=battery.o board.o led.o base_detect.o
+board-y=battery.o board.o led.o base_detect.o usbc_config.o
diff --git a/board/coachz/ec.tasklist b/board/coachz/ec.tasklist
index 49e7fb11c6..ecb6672d32 100644
--- a/board/coachz/ec.tasklist
+++ b/board/coachz/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,6 +9,7 @@
 
 #define CONFIG_TASK_LIST \
 	TASK_ALWAYS(HOOKS, hook_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PCHG, pchg_task, NULL, LARGER_TASK_STACK_SIZE) \
 	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, LARGER_TASK_STACK_SIZE) \
 	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, NULL, LARGER_TASK_STACK_SIZE) \
 	TASK_NOTEST(CHIPSET, chipset_task, NULL, ULTRA_TASK_STACK_SIZE) \
diff --git a/board/coachz/gpio.inc b/board/coachz/gpio.inc
index d60d49fd77..1bb8e9135b 100644
--- a/board/coachz/gpio.inc
+++ b/board/coachz/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,22 +13,25 @@ GPIO_INT(USB_C0_PD_INT_ODL,    PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)  /
 GPIO_INT(USB_C1_PD_INT_ODL,    PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-1 TCPC */
 GPIO_INT(USB_C0_SWCTL_INT_ODL, PIN(0, 3), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-0 PPC */
 GPIO_INT(USB_C1_SWCTL_INT_ODL, PIN(4, 0), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-1 PPC */
-GPIO_INT(USB_C0_BC12_INT_L,    PIN(6, 1), GPIO_INT_FALLING, usb0_evt)  /* Interrupt from port-0 BC1.2 */
-GPIO_INT(USB_C1_BC12_INT_L,    PIN(8, 2), GPIO_INT_FALLING, usb1_evt)  /* Interrupt from port-1 BC1.2 */
+GPIO_INT(USB_C0_BC12_INT_L,    PIN(6, 1), GPIO_INT_FALLING | GPIO_PULL_UP, usb0_evt)  /* Interrupt from port-0 BC1.2 */
+GPIO_INT(USB_C1_BC12_INT_L,    PIN(8, 2), GPIO_INT_FALLING | GPIO_PULL_UP, usb1_evt)  /* Interrupt from port-1 BC1.2 */
 
 /* System interrupts */
-GPIO_INT(CHG_ACOK_OD,       PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)  /* AC OK? */
+GPIO_INT(CHG_ACOK_OD,       PIN(0, 0), GPIO_INT_BOTH, extpower_interrupt)  /* ACOK */
 GPIO_INT(CCD_MODE_ODL,      PIN(E, 3), GPIO_INT_FALLING, board_connect_c0_sbu)  /* Case Closed Debug Mode */
 GPIO_INT(EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)  /* Power button */
 GPIO_INT(EC_VOLDN_BTN_ODL,  PIN(7, 0), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Up button */
 GPIO_INT(EC_VOLUP_BTN_ODL,  PIN(F, 2), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Down button */
 GPIO_INT(EC_FLASH_WP_ODL,   PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)  /* Write protection */
-GPIO_INT(LID_OPEN_EC,       PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)  /* Lid open? */
+GPIO_INT(LID_OPEN_EC,       PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)  /* Lid open */
 GPIO_INT(AP_RST_L,          PIN(C, 1), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_ap_rst_interrupt)  /* PMIC to signal AP reset */
-GPIO_INT(PS_HOLD,           PIN(A, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V, power_signal_interrupt)  /* Indicate when AP triggers reset/shutdown */
-GPIO_INT(PMIC_FAULT_L,      PIN(A, 3), GPIO_INT_BOTH | GPIO_SEL_1P8V, power_signal_interrupt)  /* Any PMIC fault? */
-GPIO_INT(AP_SUSPEND,        PIN(5, 7), GPIO_INT_BOTH | GPIO_SEL_1P8V, power_signal_interrupt)  /* Suspend signal from PMIC */
+GPIO_INT(PS_HOLD,           PIN(A, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, power_signal_interrupt)  /* Indicate when AP triggers reset/shutdown */
+GPIO_INT(AP_SUSPEND,        PIN(5, 7), GPIO_INT_BOTH, power_signal_interrupt)  /* Suspend signal from PMIC */
 GPIO_INT(DEPRECATED_AP_RST_REQ, PIN(C, 2), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V, power_signal_interrupt) /* Deprecated AP initiated reset indicator */
+
+/* WLC interrupt. GPIO_PULL_DOWN ensures no IRQ when WLC chip is off. */
+GPIO_INT(WLC_IRQ_CONN, PIN(7, 4), GPIO_INT_RISING | GPIO_PULL_DOWN, pchg_irq)
+
 /*
  * When switch-cap is off, the POWER_GOOD signal is floating. Need a pull-down
  * to make it low. Overload the interrupt function chipset_warm_reset_interrupt
@@ -42,49 +45,37 @@ GPIO_INT(AP_EC_SPI_CS_L,    PIN(5, 3), GPIO_INT_FALLING | GPIO_PULL_DOWN, shi_cs
 GPIO_INT(BASE_DET_L,        PIN(3, 7), GPIO_INT_BOTH, base_detect_interrupt)  /* Detachable base attached? */
 
 /* Sensor interrupts */
-GPIO_INT(ACCEL_GYRO_INT_L,  PIN(A, 0), GPIO_INT_FALLING | GPIO_SEL_1P8V, bmi160_interrupt)  /* Accelerometer/gyro interrupt */
+GPIO_INT(LID_360_L,         PIN(7, 3), GPIO_INT_BOTH, gmr_tablet_switch_isr)
+GPIO_INT(LID_INT_N_HALL1,   PIN(D, 7), GPIO_INT_BOTH, ks_interrupt)  /* Kickstand attached (0) or detached (1) */
+GPIO_INT(LID_INT_N_HALL2,   PIN(6, 0), GPIO_INT_BOTH, ks_interrupt)  /* Kickstand close (0) or open (1) */
+GPIO_INT(ACCEL_GYRO_INT_L,  PIN(A, 0), GPIO_INT_FALLING, motion_interrupt)  /* Accelerometer/gyro interrupt */
 
 /*
- * EC_RST_ODL acts as a wake source from PSL hibernate mode. However, it does
- * not need to be an interrupt for normal EC operations. Thus, configure it as
- * GPIO_INT_BOTH with wake on low-to-high edge using GPIO_HIB_WAKE_HIGH so that
- * PSL common code can configure PSL_IN correctly.
- *
- * Use the rising edge to wake EC up. If we chose the falling edge, it would
- * still wake EC up, but EC is in an intermediate state until the signal goes
- * back to high.
+ * EC_RST_ODL acts as a wake source from hibernate mode. However, it does not
+ * need to be an interrupt for normal EC operations. Simply set it an INPUT.
  */
-GPIO(EC_RST_ODL,            PIN(0, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH)  /* Wake source: EC reset */
+GPIO(EC_RST_ODL,            PIN(0, 2), GPIO_INPUT)     /* EC reset */
 GPIO(EC_ENTERING_RW,        PIN(E, 1), GPIO_OUT_LOW)   /* Indicate when EC is entering RW code */
 GPIO(EC_BATT_PRES_ODL,      PIN(E, 5), GPIO_INPUT)     /* Battery Present */
 
 /* PMIC/AP 1.8V */
-GPIO(PM845_RESIN_L,         PIN(3, 2), GPIO_ODR_HIGH | GPIO_SEL_1P8V)  /* PMIC reset trigger */
-GPIO(PMIC_KPD_PWR_ODL,      PIN(D, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V)  /* PMIC power button */
+GPIO(PM845_RESIN_L,         PIN(3, 2), GPIO_ODR_HIGH)  /* PMIC reset trigger */
+GPIO(PMIC_KPD_PWR_ODL,      PIN(D, 6), GPIO_ODR_HIGH)  /* PMIC power button */
 GPIO(EC_INT_L,              PIN(A, 2), GPIO_ODR_HIGH)  /* Interrupt line between AP and EC */
 GPIO(QSIP_ON,               PIN(5, 0), GPIO_OUT_LOW)   /* Not used, for non-switchcap testing */
 
 /* Power enables */
+GPIO(HIBERNATE_L,           PIN(5, 2), GPIO_ODR_HIGH)  /* EC hibernate */
 GPIO(SWITCHCAP_ON,          PIN(D, 5), GPIO_OUT_LOW)   /* Enable switch cap; will be configured in the board init */
-/* TODO(waihong): Remove it. The VBOB switch is for backup. */
-GPIO(VBOB_EN,               PIN(D, 3), GPIO_OUT_LOW)   /* Enable VBOB */
 GPIO(EN_PP3300_A,           PIN(A, 6), GPIO_OUT_LOW)   /* Enable PP3300 */
 GPIO(EN_PP5000_A,           PIN(6, 7), GPIO_OUT_LOW)   /* Enable PP5000 */
 GPIO(EC_BL_DISABLE_L,       PIN(B, 6), GPIO_OUT_LOW)   /* Backlight disable signal from EC */
 
-/* Sensors */
-GPIO(REVERSE_DOCK_EC,       PIN(C, 6), GPIO_INPUT)
-/* TODO(b/168714440): Implement the hall sensor interrupts */
-GPIO(LID_INT_N_HALL1,       PIN(7, 3), GPIO_INPUT)
-GPIO(LID_INT_N_HALL2,       PIN(6, 0), GPIO_INPUT)
-GPIO(LID_INT_N_HALL3,       PIN(D, 7), GPIO_INPUT)
 /* TODO(waihong): Should remove it from hardware */
 GPIO(CAM_LED,               PIN(3, 0), GPIO_INPUT)
 
-/* Stylus */
-/* TODO(b/168652326): Implement the WLC controls */
-GPIO(WLC_IRQ_CONN,          PIN(7, 4), GPIO_INPUT)
-GPIO(WLC_NRST_CONN,         PIN(C, 5), GPIO_INPUT)
+/* Reset line for WLC. External pull-up is expected. */
+GPIO(WLC_NRST_CONN,         PIN(C, 5), GPIO_ODR_HIGH)
 
 /* Base detection */
 GPIO(EN_BASE,               PIN(0, 4), GPIO_OUT_LOW)   /* Enable power to detachable base */
@@ -92,18 +83,23 @@ GPIO(EN_BASE,               PIN(0, 4), GPIO_OUT_LOW)   /* Enable power to detach
 /* USB-C */
 GPIO(USB_C0_PD_RST_L,       PIN(F, 1), GPIO_ODR_HIGH)  /* Port-0 TCPC chip reset, actaully Open-Drain */
 GPIO(USB_C1_PD_RST_L,       PIN(E, 4), GPIO_ODR_HIGH)  /* Port-1 TCPC chip reset, actually Open-Drain */
-GPIO(DP_MUX_OE_L,           PIN(9, 6), GPIO_OUT_HIGH)  /* DP mux enable */
-GPIO(DP_MUX_SEL,            PIN(4, 5), GPIO_OUT_HIGH)  /* DP mux selection: L:C0, H:C1 */
+GPIO(DP_MUX_OE_L,           PIN(9, 6), GPIO_ODR_HIGH)  /* DP mux enable, actually Open-Drain */
+GPIO(DP_MUX_SEL,            PIN(4, 5), GPIO_OUT_LOW)   /* DP mux selection: L:C0, H:C1 */
 GPIO(DP_HOT_PLUG_DET,       PIN(9, 5), GPIO_OUT_LOW)   /* DP HPD to AP */
 
-/* USB-A */
-GPIO(EN_USB_A_5V,           PIN(8, 6), GPIO_INPUT)     /* NC, backup only */
-GPIO(USB_A_CDP_ILIM_EN,     PIN(7, 5), GPIO_INPUT)     /* NC, backup only */
-
 /* LEDs */
 GPIO(EC_CHG_LED_Y_C0,       PIN(C, 3), GPIO_OUT_LOW)
 GPIO(EC_CHG_LED_W_C0,       PIN(C, 4), GPIO_OUT_LOW)
 
+/*
+ * SPI host interface - enable PDs by default. These will be made functional
+ * by the SHI driver when the AP powers up, and restored back to GPIO when
+ * the AP powers down.
+ */
+GPIO(AP_EC_SPI_MOSI,        PIN(4, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(AP_EC_SPI_MISO,        PIN(4, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(AP_EC_SPI_CLK,         PIN(5, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+
 /* PWM */
 GPIO(EDP_BKLTCTL,           PIN(B, 7), GPIO_INPUT)     /* PWM5 */
 
@@ -141,6 +137,54 @@ GPIO(SKU_ID2,               PIN(D, 4), GPIO_INPUT)
  */
 GPIO(DA9313_GPIO0,          PIN(E, 2), GPIO_INPUT | GPIO_PULL_DOWN) /* Switchcap GPIO0 */
 
+/* Special straps */
+GPIO(ARM_X86,               PIN(6, 6), GPIO_OUT_LOW)  /* NC, low for power saving */
+
+/* Unused GPIOs, NC. Apply PU for power saving */
+UNUSED(PIN(5, 1))
+UNUSED(PIN(F, 3))
+UNUSED(PIN(3, 1))
+UNUSED(PIN(2, 7))
+UNUSED(PIN(2, 6))
+UNUSED(PIN(2, 5))
+UNUSED(PIN(2, 4))
+UNUSED(PIN(2, 3))
+UNUSED(PIN(2, 2))
+UNUSED(PIN(2, 1))
+UNUSED(PIN(2, 0))
+UNUSED(PIN(1, 7))
+UNUSED(PIN(1, 6))
+UNUSED(PIN(1, 5))
+UNUSED(PIN(1, 4))
+UNUSED(PIN(1, 3))
+UNUSED(PIN(1, 2))
+UNUSED(PIN(1, 1))
+UNUSED(PIN(1, 0))
+UNUSED(PIN(0, 7))
+UNUSED(PIN(0, 6))
+UNUSED(PIN(0, 5))
+UNUSED(PIN(9, 4))
+UNUSED(PIN(9, 7))
+UNUSED(PIN(A, 7))
+UNUSED(PIN(B, 0))
+UNUSED(PIN(A, 5))
+UNUSED(PIN(3, 5))
+UNUSED(PIN(7, 2))
+UNUSED(PIN(8, 1))
+UNUSED(PIN(7, 6))
+UNUSED(PIN(3, 4))
+UNUSED(PIN(C, 6))
+UNUSED(PIN(C, 0))
+UNUSED(PIN(A, 3))
+UNUSED(PIN(6, 2))
+UNUSED(PIN(8, 3))
+UNUSED(PIN(B, 1))
+UNUSED(PIN(5, 6))
+UNUSED(PIN(8, 0))
+UNUSED(PIN(D, 3))
+UNUSED(PIN(7, 5))
+UNUSED(PIN(8, 6))
+
 /* Alternate functions GPIO definitions */
 ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)            /* UART (GPIO64/65) */
 ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0)             /* I2C0 (GPIOB4/B5) */
@@ -149,12 +193,7 @@ ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, 0)             /* I2C1 SCL (GPIO87)
 ALTERNATE(PIN_MASK(3, 0x48), 1, MODULE_I2C, 0)             /* I2C5 (GPIO33/36) */
 ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, GPIO_SEL_1P8V) /* I2C7 (GPIOB2/B3) - 1.8V */
 ALTERNATE(PIN_MASK(D, 0x03), 1, MODULE_I2C, 0)             /* I2C3 (GPIOD0/D1) */
-ALTERNATE(PIN_MASK(3, 0x80), 0, MODULE_ADC, 0)             /* ADC5 (GPIO37) */
 ALTERNATE(PIN_MASK(4, 0x1C), 0, MODULE_ADC, 0)             /* ADC1 (GPIO44), ADC2 (GPIO43), ADC3 (GPIO42) */
 ALTERNATE(PIN_MASK(4, 0xC0), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SDO (GPIO47), SHI_SDI (GPIO46) */
 ALTERNATE(PIN_MASK(5, 0x28), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SCLK (GPIO55), SHI_CS# (GPIO53) */
 ALTERNATE(PIN_MASK(B, 0x80), 1, MODULE_PWM, 0)             /* PWM5 (GPIOB7) - EDP_BKLTCTL */
-ALTERNATE(PIN_MASK(D, 0x04), 1, MODULE_PMU, 0)             /* PSL_IN1 (GPIOD2) - LID_OPEN_EC */
-ALTERNATE(PIN_MASK(0, 0x01), 1, MODULE_PMU, 0)             /* PSL_IN2 (GPIO00) - ACOK_OD */
-ALTERNATE(PIN_MASK(0, 0x02), 1, MODULE_PMU, 0)             /* PSL_IN3 (GPIO01) - EC_PWR_BTN_ODL */
-ALTERNATE(PIN_MASK(0, 0x04), 1, MODULE_PMU, 0)             /* PSL_IN4 (GPIO02) - EC_RST_ODL */
diff --git a/board/coachz/led.c b/board/coachz/led.c
index 8575d8cdaf..06840da74c 100644
--- a/board/coachz/led.c
+++ b/board/coachz/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,6 +10,7 @@
 #include "charge_state.h"
 #include "chipset.h"
 #include "ec_commands.h"
+#include "extpower.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "host_command.h"
@@ -18,6 +19,8 @@
 #include "util.h"
 
 #define LED_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS)
+/* Battery LED blinks every per 400ms */
+#define LED_HALF_ONE_SEC (500 / HOOK_TICK_INTERVAL_MS)
 
 #define BAT_LED_ON 1
 #define BAT_LED_OFF 0
@@ -32,15 +35,15 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_BLUE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static void led_set_color(enum led_color color)
 {
 	gpio_set_level(GPIO_EC_CHG_LED_Y_C0,
-		(color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
+		       (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
 	gpio_set_level(GPIO_EC_CHG_LED_W_C0,
-		(color == LED_BLUE) ? BAT_LED_ON : BAT_LED_OFF);
+		       (color == LED_BLUE) ? BAT_LED_ON : BAT_LED_OFF);
 }
 
 void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
@@ -66,56 +69,83 @@ static void board_led_set_battery(void)
 	static int battery_ticks;
 	int color = LED_OFF;
 	int period = 0;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
 		/* Always indicate amber on when charging. */
 		color = LED_AMBER;
 		break;
-	case PWR_STATE_DISCHARGE:
+	case LED_PWRS_DISCHARGE:
 		if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
-			/* Discharging in S3: Amber 1 sec, off 3 sec */
-			period = (1 + 3) * LED_ONE_SEC;
+			/* Discharging in S3: White 1 sec, off 1 sec */
+			period = (1 + 1) * LED_ONE_SEC;
 			battery_ticks = battery_ticks % period;
-			if (battery_ticks < 1 * LED_ONE_SEC)
-				color = LED_AMBER;
-			else
+			if (battery_ticks < 1 * LED_ONE_SEC) {
+				if (charge_get_percent() < 10) {
+					/* Blink amber light (1 sec on, 1 sec
+					 * off) */
+					color = LED_AMBER;
+				} else {
+					/* Blink white light (1 sec on, 1 sec
+					 * off) */
+					color = LED_BLUE;
+				}
+			} else {
 				color = LED_OFF;
-		} else if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
-			/* Discharging in S5: off */
-			color = LED_OFF;
-		} else if (chipset_in_state(CHIPSET_STATE_ON)) {
-			/* Discharging in S0: Blue on */
-			color = LED_BLUE;
+			}
+		} else {
+			/* Discharging in S5 and S0: off */
+			/* Blink amber light (1 sec on, 1 sec off) */
+			if (charge_get_percent() < 10) {
+				period = (1 + 1) * LED_ONE_SEC;
+				battery_ticks = battery_ticks % period;
+				if (battery_ticks < 1 * LED_ONE_SEC)
+					color = LED_AMBER;
+				else
+					color = LED_OFF;
+			} else {
+				/* G3 or S5 or S0: off */
+				color = LED_OFF;
+			}
 		}
 		break;
-	case PWR_STATE_ERROR:
-		/* Battery error: Amber 1 sec, off 1 sec */
-		period = (1 + 1) * LED_ONE_SEC;
+	case LED_PWRS_ERROR:
+		/* Battery error: Amber on 0.5 sec, off 0.5 sec */
+		period = (1 + 1) * LED_HALF_ONE_SEC;
 		battery_ticks = battery_ticks % period;
-		if (battery_ticks < 1 * LED_ONE_SEC)
+		if (battery_ticks < 1 * LED_HALF_ONE_SEC)
 			color = LED_AMBER;
 		else
 			color = LED_OFF;
 		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
+	case LED_PWRS_CHARGE_NEAR_FULL:
 		/* Full Charged: Blue on */
-		color = LED_BLUE;
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE) {
-			/* Factory mode: Blue 2 sec, Amber 2 sec */
-			period = (2 + 2) * LED_ONE_SEC;
+		/* S3: Blink white light (1 sec on, 1 sec off) */
+		if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
+			period = (1 + 1) * LED_ONE_SEC;
 			battery_ticks = battery_ticks % period;
-			if (battery_ticks < 2 * LED_ONE_SEC)
+			if (battery_ticks < 1 * LED_ONE_SEC)
 				color = LED_BLUE;
 			else
-				color = LED_AMBER;
-		} else
+				color = LED_OFF;
+		} else {
+			/* Full charged: White on */
 			color = LED_BLUE;
+		}
+		break;
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		color = LED_BLUE;
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		/* Factory mode: Blue 2 sec, Amber 2 sec */
+		period = (2 + 2) * LED_ONE_SEC;
+		battery_ticks = battery_ticks % period;
+		if (battery_ticks < 2 * LED_ONE_SEC)
+			color = LED_BLUE;
+		else
+			color = LED_AMBER;
 		break;
 	default:
 		/* Other states don't alter LED behavior */
diff --git a/board/coachz/usbc_config.c b/board/coachz/usbc_config.c
new file mode 100644
index 0000000000..704d21722a
--- /dev/null
+++ b/board/coachz/usbc_config.c
@@ -0,0 +1,61 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Trogdor family-specific USB-C configuration */
+
+#include "charge_state.h"
+#include "charger.h"
+#include "charger/isl923x_public.h"
+#include "gpio.h"
+#include "usb_pd.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+};
+
+int charger_profile_override(struct charge_state_data *curr)
+{
+	int usb_mv;
+	int port;
+
+	if (curr->state != ST_CHARGE)
+		return 0;
+
+	/* Lower the max requested voltage to 5V when battery is full. */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
+	    !(curr->batt.flags & BATT_FLAG_BAD_STATUS) &&
+	    !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
+	    (curr->batt.status & STATUS_FULLY_CHARGED))
+		usb_mv = 5000;
+	else
+		usb_mv = PD_MAX_VOLTAGE_MV;
+
+	if (pd_get_max_voltage() != usb_mv) {
+		CPRINTS("VBUS limited to %dmV", usb_mv);
+		for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++)
+			pd_set_external_voltage_limit(port, usb_mv);
+	}
+
+	return 0;
+}
+
+enum ec_status charger_profile_override_get_param(uint32_t param,
+						  uint32_t *value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+enum ec_status charger_profile_override_set_param(uint32_t param,
+						  uint32_t value)
+{
+	return EC_RES_INVALID_PARAM;
+}
diff --git a/board/coachz/vif_override.xml b/board/coachz/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/coachz/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/coffeecake/board.c b/board/coffeecake/board.c
index e00c9e7b4b..441f95d21b 100644
--- a/board/coffeecake/board.c
+++ b/board/coffeecake/board.c
@@ -1,11 +1,10 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 /* Coffeecake dock configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "charger/sy21612.h"
 #include "clock.h"
 #include "common.h"
@@ -17,10 +16,10 @@
 #include "mcdp28x0.h"
 #include "registers.h"
 #include "task.h"
+#include "timer.h"
 #include "usb_bb.h"
 #include "usb_descriptor.h"
 #include "usb_pd.h"
-#include "timer.h"
 #include "util.h"
 
 static volatile uint64_t hpd_prev_ts;
@@ -28,11 +27,16 @@ static volatile int hpd_prev_level;
 
 void hpd_event(enum gpio_signal signal);
 void vbus_event(enum gpio_signal signal);
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{"charger", I2C_PORT_SY21612, 400, GPIO_I2C0_SCL, GPIO_I2C0_SDA},
+	{ .name = "charger",
+	  .port = I2C_PORT_SY21612,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_SCL,
+	  .sda = GPIO_I2C0_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -148,7 +152,7 @@ void board_config_pre_init(void)
 	/* Set 5Vsafe Vdac */
 	board_set_usb_output_voltage(5000);
 	/* Remap USART DMA to match the USART driver */
-	STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10);/* Remap USART1 RX/TX DMA */
+	STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10); /* Remap USART1 RX/TX DMA */
 }
 
 #ifdef CONFIG_SPI_FLASH
@@ -192,10 +196,9 @@ static void factory_validation_deferred(void)
 
 	/* test mcdp via serial to validate function */
 	if (!mcdp_get_info(&info) && (MCDP_FAMILY(info.family) == 0x0010) &&
-	(MCDP_CHIPID(info.chipid) == 0x2850)) {
+	    (MCDP_CHIPID(info.chipid) == 0x2850)) {
 		pd_log_event(PD_EVENT_VIDEO_CODEC,
-			     PD_LOG_PORT_SIZE(0, sizeof(info)),
-			     0, &info);
+			     PD_LOG_PORT_SIZE(0, sizeof(info)), 0, &info);
 	}
 
 	mcdp_disable();
@@ -210,7 +213,8 @@ static void board_post_init(void)
 	 * DUT powered - DRP SINK
 	 */
 	pd_set_dual_role(0, gpio_get_level(GPIO_AC_PRESENT_L) ?
-			 PD_DRP_FORCE_SINK : PD_DRP_FORCE_SOURCE);
+				    PD_DRP_FORCE_SINK :
+				    PD_DRP_FORCE_SOURCE);
 }
 DECLARE_DEFERRED(board_post_init);
 
@@ -228,10 +232,11 @@ static void board_init(void)
 	gpio_enable_interrupt(GPIO_CHARGER_INT);
 	gpio_enable_interrupt(GPIO_USB_C_VBUS_DET_L);
 	/* Set PD_DISCHARGE initial state */
-	gpio_set_level(GPIO_PD_DISCHARGE, gpio_get_level(GPIO_USB_C_VBUS_DET_L));
+	gpio_set_level(GPIO_PD_DISCHARGE,
+		       gpio_get_level(GPIO_USB_C_VBUS_DET_L));
 
 	/* Delay needed to allow HDMI MCU to boot. */
-	hook_call_deferred(&factory_validation_deferred_data, 200*MSEC);
+	hook_call_deferred(&factory_validation_deferred_data, 200 * MSEC);
 	/* Initialize buck-boost converter */
 	hook_call_deferred(&board_post_init_data, 0);
 }
@@ -241,16 +246,16 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* USB PD CC lines sensing. Converted to mV (3300mV/4096). */
-	[ADC_CH_CC1_PD]    = {"USB_C_CC1_PD", 3300, 4096, 0, STM32_AIN(1)},
-	[ADC_VBUS_MON]     = {"VBUS_MON", 13200, 4096, 0, STM32_AIN(2)},
-	[ADC_DAC_REF_TP28] = {"DAC_REF_TP28", 3300, 4096, 0, STM32_AIN(4)},
-	[ADC_DAC_VOLT]     = {"DAC_VOLT", 3300, 4096, 0, STM32_AIN(5)},
+	[ADC_CH_CC1_PD] = { "USB_C_CC1_PD", 3300, 4096, 0, STM32_AIN(1) },
+	[ADC_VBUS_MON] = { "VBUS_MON", 13200, 4096, 0, STM32_AIN(2) },
+	[ADC_DAC_REF_TP28] = { "DAC_REF_TP28", 3300, 4096, 0, STM32_AIN(4) },
+	[ADC_DAC_VOLT] = { "DAC_VOLT", 3300, 4096, 0, STM32_AIN(5) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
-const void * const usb_strings[] = {
+const void *const usb_strings[] = {
 	[USB_STR_DESC] = usb_string_desc,
-	[USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."),
+	[USB_STR_VENDOR] = USB_STRING_DESC("Google LLC"),
 	[USB_STR_PRODUCT] = USB_STRING_DESC("Hoho"),
 	[USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32),
 	[USB_STR_BB_URL] = USB_STRING_DESC(USB_GOOGLE_TYPEC_URL),
diff --git a/board/coffeecake/board.h b/board/coffeecake/board.h
index f69ebe2f29..9c7a2643d0 100644
--- a/board/coffeecake/board.h
+++ b/board/coffeecake/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,6 +8,9 @@
 #ifndef __CROS_EC_BOARD_H
 #define __CROS_EC_BOARD_H
 
+/* Free up flash space */
+#define CONFIG_LTO
+
 /* 48 MHz SYSCLK clock frequency */
 #define CPU_CLOCK 48000000
 
@@ -15,7 +18,6 @@
 #define CONFIG_UART_CONSOLE 1
 
 /* Optional features */
-#define CONFIG_STM_HWTIMER32
 #define CONFIG_ADC
 #define CONFIG_BOARD_PRE_INIT
 #define CONFIG_CMD_CHARGER
@@ -24,15 +26,14 @@
 #define CONFIG_CHARGER_SY21612
 #define CONFIG_HW_CRC
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_CONTROLLER
 #define CONFIG_RSA
 #define CONFIG_RWSIG
 #define CONFIG_RWSIG_TYPE_USBPD1
 #define CONFIG_SHA256
-/* TODO(tbroch) Re-enable once STM spi master can be inhibited at boot so it
+/* TODO(tbroch) Re-enable once STM spi controller can be inhibited at boot so it
    doesn't interfere with HDMI loading its f/w */
 #undef CONFIG_SPI_FLASH
-#define CONFIG_SPI_MASTER_PORT 2
 #define CONFIG_SPI_CS_GPIO GPIO_PD_MCDP_SPI_CS_L
 #define CONFIG_USB
 #define CONFIG_USB_BOS
@@ -48,7 +49,7 @@
 #define CONFIG_USB_PD_IDENTITY_HW_VERS 1
 #define CONFIG_USB_PD_IDENTITY_SW_VERS 1
 #define CONFIG_USB_PD_LOGGING
-#undef  CONFIG_EVENT_LOG_SIZE
+#undef CONFIG_EVENT_LOG_SIZE
 #define CONFIG_EVENT_LOG_SIZE 256
 #define CONFIG_USB_PD_CUSTOM_PDO
 #define CONFIG_USB_PD_PORT_MAX_COUNT 1
@@ -78,7 +79,7 @@
 
 /* Timer selection */
 #define TIM_CLOCK32 2
-#define TIM_ADC     3
+#define TIM_ADC 3
 
 #include "gpio_signal.h"
 
@@ -104,21 +105,21 @@ enum usb_strings {
 };
 
 /* 3.0A Rp */
-#define PD_SRC_VNC            PD_SRC_3_0_VNC_MV
-#define PD_SRC_RD_THRESHOLD   PD_SRC_3_0_RD_THRESH_MV
+#define PD_SRC_VNC PD_SRC_3_0_VNC_MV
+#define PD_SRC_RD_THRESHOLD PD_SRC_3_0_RD_THRESH_MV
 
 /* delay necessary for the voltage transition on the power supply */
 /* TODO (code.google.com/p/chrome-os-partner/issues/detail?id=37078)
  * Need to measure these and adjust for honeybuns.
  */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  50000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 50000 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 50000 /* us */
 
 /* Define typical operating power and max power */
 #define PD_OPERATING_POWER_MW 1000
-#define PD_MAX_POWER_MW       22500
-#define PD_MAX_CURRENT_MA     2500
-#define PD_MAX_VOLTAGE_MV     9000
+#define PD_MAX_POWER_MW 22500
+#define PD_MAX_CURRENT_MA 2500
+#define PD_MAX_VOLTAGE_MV 9000
 
 /* Board interfaces */
 void board_set_usb_output_voltage(int mv);
@@ -129,11 +130,11 @@ void board_set_usb_output_voltage(int mv);
 #define USB_DEV_CLASS USB_CLASS_BILLBOARD
 
 /* USB interface indexes (use define rather than enum to expand them) */
-#define USB_IFACE_COUNT     0
+#define USB_IFACE_COUNT 0
 
 /* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL   0
-#define USB_EP_COUNT     1
+#define USB_EP_CONTROL 0
+#define USB_EP_COUNT 1
 
 /* I2C ports */
 #define I2C_PORT_SY21612 0
diff --git a/board/coffeecake/build.mk b/board/coffeecake/build.mk
index fb5a6fccdb..26ddbbd925 100644
--- a/board/coffeecake/build.mk
+++ b/board/coffeecake/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -14,4 +14,4 @@ CHIP_VARIANT:=stm32f07x
 test-list-y=
 
 board-y=board.o
-board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
+board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o usb_pd_pdo.o
diff --git a/board/coffeecake/ec.tasklist b/board/coffeecake/ec.tasklist
index d6686d72e9..e02c0620f8 100644
--- a/board/coffeecake/ec.tasklist
+++ b/board/coffeecake/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/coffeecake/gpio.inc b/board/coffeecake/gpio.inc
index bab62a6bea..9d0a02ea40 100644
--- a/board/coffeecake/gpio.inc
+++ b/board/coffeecake/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/coffeecake/usb_pd_config.h b/board/coffeecake/usb_pd_config.h
index e2c1dbb2db..728d96bafe 100644
--- a/board/coffeecake/usb_pd_config.h
+++ b/board/coffeecake/usb_pd_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -49,7 +49,7 @@ static inline void spi_enable_clock(int port)
 
 #define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
 #define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
-#define TIM_CCR_CS  1
+#define TIM_CCR_CS 1
 #define EXTI_COMP_MASK(p) BIT(21)
 #define IRQ_COMP STM32_IRQ_COMP
 /* triggers packet detection on comparator falling edge */
@@ -100,8 +100,8 @@ static inline void pd_select_polarity(int port, int polarity)
 	 * use the right comparator : CC1 -> PA1 (COMP1 INP)
 	 * use VrefInt / 2 as INM (about 600mV)
 	 */
-	STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK)
-		| STM32_COMP_CMP1EN | STM32_COMP_CMP1INSEL_VREF12;
+	STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK) |
+			 STM32_COMP_CMP1EN | STM32_COMP_CMP1INSEL_VREF12;
 }
 
 /* Initialize pins used for TX and put them in Hi-Z */
@@ -136,7 +136,7 @@ static inline int pd_adc_read(int port, int cc)
 	 * Check HOST_HIGH Rp setting.
 	 * Return 3300mV on host mode.
 	 */
-	if ((STM32_GPIO_MODER(GPIO_B) & (3 << (2*5))) == (1 << (2*5)))
+	if ((STM32_GPIO_MODER(GPIO_B) & (3 << (2 * 5))) == (1 << (2 * 5)))
 		return 3300;
 	else
 		return 0;
diff --git a/board/coffeecake/usb_pd_pdo.c b/board/coffeecake/usb_pd_pdo.c
new file mode 100644
index 0000000000..c0d2298706
--- /dev/null
+++ b/board/coffeecake/usb_pd_pdo.c
@@ -0,0 +1,27 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "compile_time_macros.h"
+#include "usb_pd.h"
+#include "usb_pd_pdo.h"
+
+#define PDO_FIXED_FLAGS_EXT                                               \
+	(PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP | PDO_FIXED_COMM_CAP | \
+	 PDO_FIXED_UNCONSTRAINED)
+
+#define PDO_FIXED_FLAGS \
+	(PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP | PDO_FIXED_COMM_CAP)
+
+const uint32_t pd_src_pdo[] = {
+	[PDO_IDX_5V] = PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS_EXT),
+	[PDO_IDX_9V] = PDO_FIXED(9000, 2500, PDO_FIXED_FLAGS),
+};
+const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
+BUILD_ASSERT(ARRAY_SIZE(pd_src_pdo) == PDO_IDX_COUNT);
+
+const uint32_t pd_snk_pdo[] = {
+	PDO_FIXED(5000, 1500, PDO_FIXED_FLAGS),
+};
+const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
diff --git a/board/coffeecake/usb_pd_pdo.h b/board/coffeecake/usb_pd_pdo.h
new file mode 100644
index 0000000000..2ec925955d
--- /dev/null
+++ b/board/coffeecake/usb_pd_pdo.h
@@ -0,0 +1,25 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_BOARD_COFFEECAKE_USB_PD_PDO_H
+#define __CROS_EC_BOARD_COFFEECAKE_USB_PD_PDO_H
+
+#include "stdint.h"
+
+/* Voltage indexes for the PDOs */
+enum volt_idx {
+	PDO_IDX_5V = 0,
+	PDO_IDX_9V = 1,
+	/* TODO: add PPS support */
+	PDO_IDX_COUNT
+};
+
+extern const uint32_t pd_src_pdo[2];
+extern const int pd_src_pdo_cnt;
+
+extern const uint32_t pd_snk_pdo[1];
+extern const int pd_snk_pdo_cnt;
+
+#endif /* __CROS_EC_BOARD_COFFEECAKE_USB_PD_PDO_H */
diff --git a/board/coffeecake/usb_pd_policy.c b/board/coffeecake/usb_pd_policy.c
index 6da20a5b37..525d1057e2 100644
--- a/board/coffeecake/usb_pd_policy.c
+++ b/board/coffeecake/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,6 +8,7 @@
 #include "charger/sy21612.h"
 #include "common.h"
 #include "console.h"
+#include "cros_version.h"
 #include "ec_commands.h"
 #include "gpio.h"
 #include "hooks.h"
@@ -17,39 +18,12 @@
 #include "usb_api.h"
 #include "usb_bb.h"
 #include "usb_pd.h"
+#include "usb_pd_pdo.h"
+#include "usb_pd_tcpm.h"
 #include "util.h"
-#include "version.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-#define PDO_FIXED_FLAGS_EXT (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\
-			     PDO_FIXED_COMM_CAP | PDO_FIXED_UNCONSTRAINED)
-
-#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\
-			 PDO_FIXED_COMM_CAP)
-
-
-/* Voltage indexes for the PDOs */
-enum volt_idx {
-	PDO_IDX_5V  = 0,
-	PDO_IDX_9V  = 1,
-	/* TODO: add PPS support */
-	PDO_IDX_COUNT
-};
-
-/* PDOs */
-const uint32_t pd_src_pdo[] = {
-	[PDO_IDX_5V]  = PDO_FIXED(5000,  3000, PDO_FIXED_FLAGS_EXT),
-	[PDO_IDX_9V]  = PDO_FIXED(9000,  2500, PDO_FIXED_FLAGS),
-};
-const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
-BUILD_ASSERT(ARRAY_SIZE(pd_src_pdo) == PDO_IDX_COUNT);
-
-const uint32_t pd_snk_pdo[] = {
-	PDO_FIXED(5000, 1500, PDO_FIXED_FLAGS),
-};
-const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 /* Holds valid object position (opos) for entered mode */
 static int alt_mode[PD_AMODE_COUNT];
@@ -123,31 +97,24 @@ int pd_check_power_swap(int port)
 	return 0;
 }
 
-int pd_check_data_swap(int port,
-		       enum pd_data_role data_role)
+int pd_check_data_swap(int port, enum pd_data_role data_role)
 {
 	/* We can swap to UFP */
 	return data_role == PD_ROLE_DFP;
 }
 
-void pd_execute_data_swap(int port,
-			  enum pd_data_role data_role)
+void pd_execute_data_swap(int port, enum pd_data_role data_role)
 {
 	/* TODO: turn on pp5000, pp3300 */
 }
 
-void pd_check_pr_role(int port,
-		      enum pd_power_role pr_role,
-		      int flags)
+void pd_check_pr_role(int port, enum pd_power_role pr_role, int flags)
 {
 	if (pr_role == PD_ROLE_SINK && !gpio_get_level(GPIO_AC_PRESENT_L))
 		pd_request_power_swap(port);
-
 }
 
-void pd_check_dr_role(int port,
-		      enum pd_data_role dr_role,
-		      int flags)
+void pd_check_dr_role(int port, enum pd_data_role dr_role, int flags)
 {
 	if ((flags & PD_FLAGS_PARTNER_DR_DATA) && dr_role == PD_ROLE_DFP)
 		pd_request_data_swap(port);
@@ -162,8 +129,8 @@ const uint32_t vdo_idh = VDO_IDH(0, /* data caps as USB host */
 const uint32_t vdo_product = VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV);
 
 const uint32_t vdo_ama = VDO_AMA(CONFIG_USB_PD_IDENTITY_HW_VERS,
-				 CONFIG_USB_PD_IDENTITY_SW_VERS,
-				 0, 0, 0, 0, /* SS[TR][12] */
+				 CONFIG_USB_PD_IDENTITY_SW_VERS, 0, 0, 0,
+				 0, /* SS[TR][12] */
 				 0, /* Vconn power */
 				 0, /* Vconn power required */
 				 1, /* Vbus power required */
@@ -189,18 +156,16 @@ static int svdm_response_svids(int port, uint32_t *payload)
 #define OPOS_DP 1
 #define OPOS_GFU 1
 
-const uint32_t vdo_dp_modes[1] =  {
-	VDO_MODE_DP(0,		   /* UFP pin cfg supported : none */
+const uint32_t vdo_dp_modes[1] = {
+	VDO_MODE_DP(0, /* UFP pin cfg supported : none */
 		    MODE_DP_PIN_C, /* DFP pin cfg supported */
-		    1,		   /* no usb2.0	signalling in AMode */
-		    CABLE_PLUG,	   /* its a plug */
-		    MODE_DP_V13,   /* DPv1.3 Support, no Gen2 */
-		    MODE_DP_SNK)   /* Its a sink only */
+		    1, /* no usb2.0	signalling in AMode */
+		    CABLE_PLUG, /* its a plug */
+		    MODE_DP_V13, /* DPv1.3 Support, no Gen2 */
+		    MODE_DP_SNK) /* Its a sink only */
 };
 
-const uint32_t vdo_goog_modes[1] =  {
-	VDO_MODE_GOOGLE(MODE_GOOGLE_FU)
-};
+const uint32_t vdo_goog_modes[1] = { VDO_MODE_GOOGLE(MODE_GOOGLE_FU) };
 
 static int svdm_response_modes(int port, uint32_t *payload)
 {
@@ -222,13 +187,15 @@ static int dp_status(int port, uint32_t *payload)
 	if (opos != OPOS_DP)
 		return 0; /* nak */
 
-	payload[1] = VDO_DP_STATUS(0,                /* IRQ_HPD */
-				   (hpd == 1),       /* HPD_HI|LOW */
-				   0,		     /* request exit DP */
-				   0,		     /* request exit USB */
-				   0,		     /* MF pref */
+	payload[1] = VDO_DP_STATUS(0, /* IRQ_HPD */
+				   (hpd == 1), /* HPD_HI|LOW */
+				   0, /* request exit DP */
+				   0, /* request exit USB */
+				   0, /* MF pref */
 				   gpio_get_level(GPIO_PD_SBU_ENABLE),
-				   0,		     /* power low */
+				   0, /* power
+					 low
+				       */
 				   0x2);
 	return 2;
 }
@@ -266,9 +233,9 @@ static int svdm_enter_mode(int port, uint32_t *payload)
 	return rv;
 }
 
-int pd_alt_mode(int port, enum tcpm_transmit_type type, uint16_t svid)
+int pd_alt_mode(int port, enum tcpci_msg_type type, uint16_t svid)
 {
-	if (type != TCPC_TX_SOP)
+	if (type != TCPCI_MSG_SOP)
 		return 0;
 
 	if (svid == USB_SID_DISPLAYPORT)
@@ -307,8 +274,7 @@ const struct svdm_response svdm_rsp = {
 	.exit_mode = &svdm_exit_mode,
 };
 
-int pd_custom_vdm(int port, int cnt, uint32_t *payload,
-		  uint32_t **rpayload)
+int pd_custom_vdm(int port, int cnt, uint32_t *payload, uint32_t **rpayload)
 {
 	int rsize;
 
diff --git a/board/coffeecake/vif_override.xml b/board/coffeecake/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/coffeecake/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/collis/battery.c b/board/collis/battery.c
new file mode 100644
index 0000000000..21c7b80901
--- /dev/null
+++ b/board/collis/battery.c
@@ -0,0 +1,66 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "common.h"
+#include "util.h"
+
+/*
+ * Battery info for all Volteer battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	[BATTERY_C490] = {
+		.fuel_gauge = {
+			.manuf_name = "AS3GWQd3jB",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x10, 0x10 },
+			},
+			.fet = {
+				.reg_addr = 0x99,
+				.reg_mask = 0x000c,
+				.disconnect_val = 0x000c,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0004,
+			}
+		},
+		.batt_info = {
+			.voltage_max            = 13200, /* mV */
+			.voltage_normal         = 11550, /* mV */
+			.voltage_min            = 9000, /* mV */
+			.precharge_current      = 256,  /* mA */
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 45,
+			.charging_min_c         = 0,
+			.charging_max_c         = 60,
+			.discharging_min_c      = -20,
+			.discharging_max_c      = 60,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_C490;
diff --git a/board/collis/board.c b/board/collis/board.c
new file mode 100644
index 0000000000..43b8f8f6d3
--- /dev/null
+++ b/board/collis/board.c
@@ -0,0 +1,458 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Volteer board-specific configuration */
+#include "accelgyro.h"
+#include "button.h"
+#include "cbi_ec_fw_config.h"
+#include "common.h"
+#include "driver/accel_bma2x2.h"
+#include "driver/accelgyro_bmi160.h"
+#include "driver/bc12/pi3usb9201.h"
+#include "driver/ppc/syv682x.h"
+#include "driver/sync.h"
+#include "driver/tcpm/ps8xxx.h"
+#include "driver/tcpm/tcpci.h"
+#include "extpower.h"
+#include "fan.h"
+#include "fan_chip.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "switch.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "throttle_ap.h"
+#include "uart.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tbt.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/* Increase from 50 us, because KSO_02 passes through the H1. */
+	.output_settle_us = 80,
+	/* Other values should be the same as the default configuration. */
+	.debounce_down_us = 9 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x1c, 0xfe, 0xff, 0xff, 0xff, 0xf5, 0xff,
+		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
+	},
+};
+
+static const struct ec_response_keybd_config copano_kb = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &copano_kb;
+}
+
+/******************************************************************************/
+/*
+ * FW_CONFIG defaults for Terrador if the CBI data is not initialized.
+ */
+union volteer_cbi_fw_config fw_config_defaults = {
+	.usb_db = DB_USB3_ACTIVE,
+};
+
+static void board_init(void)
+{
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+/******************************************************************************/
+/* I2C port map configuration */
+const struct i2c_port_t i2c_ports[] = {
+	{
+		.name = "sensor",
+		.port = I2C_PORT_SENSOR,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C0_SENSOR_SCL,
+		.sda = GPIO_EC_I2C0_SENSOR_SDA,
+	},
+	{
+		.name = "usb_c0",
+		.port = I2C_PORT_USB_C0,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C1_USB_C0_SCL,
+		.sda = GPIO_EC_I2C1_USB_C0_SDA,
+	},
+	{
+		.name = "usb_c1",
+		.port = I2C_PORT_USB_C1,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C2_USB_C1_SCL,
+		.sda = GPIO_EC_I2C2_USB_C1_SDA,
+	},
+	{
+		.name = "usb_0_mix",
+		.port = I2C_PORT_USB_0_MIX,
+		.kbps = 100,
+		.scl = GPIO_EC_I2C3_USB_0_MIX_SCL,
+		.sda = GPIO_EC_I2C3_USB_0_MIX_SDA,
+	},
+	{
+		.name = "usb_1_mix",
+		.port = I2C_PORT_USB_1_MIX,
+		.kbps = 100,
+		.scl = GPIO_EC_I2C4_USB_1_MIX_SCL,
+		.sda = GPIO_EC_I2C4_USB_1_MIX_SDA,
+	},
+	{
+		.name = "power",
+		.port = I2C_PORT_POWER,
+		.kbps = 100,
+		.scl = GPIO_EC_I2C5_POWER_SCL,
+		.sda = GPIO_EC_I2C5_POWER_SDA,
+	},
+	{
+		.name = "eeprom",
+		.port = I2C_PORT_EEPROM,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C7_EEPROM_SCL,
+		.sda = GPIO_EC_I2C7_EEPROM_SDA,
+	},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+/******************************************************************************/
+/* PWM configuration */
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_KBLIGHT] = {
+		.channel = 3,
+		.flags = 0,
+		/*
+		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
+		 * flicker. Higher frequencies consume similar average power to
+		 * lower PWM frequencies, but higher frequencies record a much
+		 * lower maximum power.
+		 */
+		.freq = 10000,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+/******************************************************************************/
+/* EC thermal management configuration */
+
+/*
+ * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
+ * 130 C.  However, sensor is located next to DDR, so we need to use the lower
+ * DDR temperature limit (85 C)
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+		}, \
+		.temp_fan_off = C_TO_K(35), \
+		.temp_fan_max = C_TO_K(50), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
+
+/*
+ * Inductor limits - used for both charger and PP3300 regulator
+ *
+ * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
+ *
+ * Charger max recommended temperature 100C, max absolute temperature 125C
+ * PP3300 regulator: operating range -40 C to 145 C
+ *
+ * Inductors: limit of 125c
+ * PCB: limit is 80c
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_INDUCTOR         \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+		}, \
+		.temp_fan_off = C_TO_K(40), \
+		.temp_fan_max = C_TO_K(55), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_inductor =
+	THERMAL_INDUCTOR;
+
+struct ec_thermal_config thermal_params[] = {
+	[TEMP_SENSOR_1_CHARGER] = THERMAL_INDUCTOR,
+	[TEMP_SENSOR_2_PP3300_REGULATOR] = THERMAL_INDUCTOR,
+	[TEMP_SENSOR_3_DDR_SOC] = THERMAL_CPU,
+	[TEMP_SENSOR_4_FAN] = THERMAL_CPU,
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
+
+/******************************************************************************/
+
+static void kb_backlight_enable(void)
+{
+	gpio_set_level(GPIO_EC_KB_BL_EN, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, kb_backlight_enable, HOOK_PRIO_DEFAULT);
+
+static void kb_backlight_disable(void)
+{
+	gpio_set_level(GPIO_EC_KB_BL_EN, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, kb_backlight_disable, HOOK_PRIO_DEFAULT);
+
+/*****************************************************************************/
+/* USBC PPC configuration */
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.drv = &syv682x_drv,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C1,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.drv = &syv682x_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/******************************************************************************/
+/* PPC support routines */
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C1);
+		break;
+	default:
+		break;
+	}
+}
+
+/******************************************************************************/
+/* BC1.2 charger detect configuration */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C1,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
+
+/******************************************************************************/
+/* USBC TCPC configuration */
+const struct tcpc_config_t tcpc_config[] = {
+	[USBC_PORT_C0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V,
+		.drv = &ps8xxx_tcpm_drv,
+	},
+	[USBC_PORT_C1] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C1,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V,
+		.drv = &ps8xxx_tcpm_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
+BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
+
+/******************************************************************************/
+/* USBC mux configuration - Tiger Lake includes internal mux */
+static const struct usb_mux_chain usbc0_usb3_mb_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
+	.next = NULL,
+};
+
+static const struct usb_mux_chain usbc1_usb3_db_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
+	.next = NULL,
+};
+
+const struct usb_mux_chain usb_muxes[] = {
+	[USBC_PORT_C0] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc0_usb3_mb_retimer,
+	},
+	[USBC_PORT_C1] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc1_usb3_db_retimer,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
+
+static void board_tcpc_init(void)
+{
+	/* Don't reset TCPCs after initial reset */
+	if (!system_jumped_late())
+		board_reset_pd_mcu();
+
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
+
+	/* Enable BC1.2 interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
+
+/******************************************************************************/
+/* TCPC support routines */
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	/*
+	 * Check which port has the ALERT line set
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL))
+		status |= PD_STATUS_TCPC_ALERT_0;
+	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL))
+		status |= PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
+
+int ppc_get_alert_status(int port)
+{
+	if (port == USBC_PORT_C0)
+		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
+	else
+		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
+}
+
+/******************************************************************************/
+/* USB-A charging control */
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_PP5000_USBA,
+};
+
+static void ps8815_reset(int port)
+{
+	int val;
+	int i2c_port;
+	enum gpio_signal ps8xxx_rst_odl;
+
+	if (port == USBC_PORT_C0) {
+		ps8xxx_rst_odl = GPIO_USB_C0_RT_RST_ODL;
+		i2c_port = I2C_PORT_USB_C0;
+	} else if (port == USBC_PORT_C1) {
+		ps8xxx_rst_odl = GPIO_USB_C1_RT_RST_ODL;
+		i2c_port = I2C_PORT_USB_C1;
+	} else {
+		return;
+	}
+
+	gpio_set_level(ps8xxx_rst_odl, 0);
+	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS));
+	gpio_set_level(ps8xxx_rst_odl, 1);
+	msleep(PS8815_FW_INIT_DELAY_MS);
+
+	CPRINTS("[C%d] %s: patching ps8815 registers", port, __func__);
+
+	if (i2c_read8(i2c_port, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) ==
+	    EC_SUCCESS)
+		CPRINTS("ps8815: reg 0x0f was %02x", val);
+
+	if (i2c_write8(i2c_port, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) ==
+	    EC_SUCCESS)
+		CPRINTS("ps8815: reg 0x0f set to 0x31");
+
+	if (i2c_read8(i2c_port, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) ==
+	    EC_SUCCESS)
+		CPRINTS("ps8815: reg 0x0f now %02x", val);
+}
+
+void board_reset_pd_mcu(void)
+{
+	ps8815_reset(USBC_PORT_C0);
+	usb_mux_hpd_update(USBC_PORT_C0, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+	ps8815_reset(USBC_PORT_C1);
+	usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+}
diff --git a/board/collis/board.h b/board/collis/board.h
new file mode 100644
index 0000000000..d9e903c6b3
--- /dev/null
+++ b/board/collis/board.h
@@ -0,0 +1,177 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Volteer board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* Baseboard features */
+#include "baseboard.h"
+
+/*
+ * The RAM and flash size combination on the NPCX797FC dose not leave
+ * any unused flash space that can be used to store the .init_rom section.
+ */
+#undef CONFIG_CHIP_INIT_ROM_REGION
+
+#define CONFIG_VBOOT_EFS2
+
+#define CONFIG_POWER_BUTTON
+
+#undef CONFIG_UART_TX_BUF_SIZE
+#define CONFIG_UART_TX_BUF_SIZE 4096
+
+/* Chipset features */
+#define CONFIG_POWER_PP5000_CONTROL
+
+#undef NPCX_PWM1_SEL
+#define NPCX_PWM1_SEL 0 /* GPIO C2 is not used as PWM1 */
+
+/* LED defines */
+#define CONFIG_LED_ONOFF_STATES
+#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
+
+/* Keyboard features */
+#define CONFIG_KEYBOARD_VIVALDI
+#define CONFIG_KEYBOARD_REFRESH_ROW3
+
+/* Sensors */
+/* BMA253 accelerometer in base */
+#define CONFIG_ACCEL_BMA255
+#define CONFIG_ACCEL_KX022
+
+/* BMI160 accel/gyro in base */
+#define CONFIG_ACCELGYRO_BMI160
+#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+#define CONFIG_ACCELGYRO_ICM426XX
+#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+/* Sensors without hardware FIFO are in forced mode */
+#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
+
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_UPDATE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+
+/* USB Type C and USB PD defines */
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+
+/*
+ * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
+ * cables only support up to 60W, the limitation of 45W is for the Collis
+ * board.
+ */
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 45000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
+
+#undef CONFIG_USBC_RETIMER_INTEL_BB
+#undef CONFIG_USBC_RETIMER_INTEL_BB_RUNTIME_CONFIG
+
+/* USB Type A Features */
+#define USB_PORT_COUNT 1
+#define CONFIG_USB_PORT_POWER_DUMB
+
+/* USBC PPC*/
+#define CONFIG_USBC_PPC_SYV682X /* USBC port C0/C1 */
+
+#undef CONFIG_USB_MUX_RUNTIME_CONFIG
+#undef CONFIG_USB_PD_TCPC_RUNTIME_CONFIG
+#undef CONFIG_USB_PD_TCPM_RT1715
+#undef CONFIG_USB_PD_TCPM_TUSB422
+
+/* BC 1.2 */
+
+/* Volume Button feature */
+
+/* Fan features */
+#undef CONFIG_FANS
+
+/* charger defines */
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_LID_OPEN GPIO_EC_LID_OPEN
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK
+#define GPIO_PG_EC_DSW_PWROK GPIO_DSW_PWROK
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
+
+/* I2C Bus Configuration */
+#define CONFIG_I2C
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_0_MIX NPCX_I2C_PORT3_0
+#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT4_1
+#define I2C_PORT_POWER NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+
+#define I2C_PORT_BATTERY I2C_PORT_POWER
+#define I2C_PORT_CHARGER I2C_PORT_EEPROM
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+#define CONFIG_I2C_CONTROLLER
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum battery_type {
+	BATTERY_C490,
+	BATTERY_TYPE_COUNT,
+};
+
+enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_COUNT };
+
+enum sensor_id {
+	LID_ACCEL = 0,
+	BASE_ACCEL,
+	BASE_GYRO,
+	SENSOR_COUNT,
+};
+
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
+
+void board_reset_pd_mcu(void);
+void motion_interrupt(enum gpio_signal signal);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/collis/build.mk b/board/collis/build.mk
new file mode 100644
index 0000000000..18397fdec3
--- /dev/null
+++ b/board/collis/build.mk
@@ -0,0 +1,17 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx7
+CHIP_VARIANT:=npcx7m7fc
+BASEBOARD:=volteer
+
+board-y=board.o
+board-y+=battery.o
+board-y+=led.o
+board-y+=sensors.o
diff --git a/board/collis/ec.tasklist b/board/collis/ec.tasklist
new file mode 100644
index 0000000000..07a91894ed
--- /dev/null
+++ b/board/collis/ec.tasklist
@@ -0,0 +1,27 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/collis/gpio.inc b/board/collis/gpio.inc
new file mode 100644
index 0000000000..51c5f6b144
--- /dev/null
+++ b/board/collis/gpio.inc
@@ -0,0 +1,176 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+/* Wake Source interrupts */
+GPIO_INT(EC_LID_OPEN,          PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
+GPIO_INT(EC_WP_L,              PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(H1_EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
+GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
+
+/* Power sequencing interrupts */
+GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
+#endif
+GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_EC_RSMRST_ODL,     PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(DSW_PWROK,            PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4),  GPIO_INT_BOTH, power_signal_interrupt)
+
+/* Sensor Interrupts */
+GPIO_INT(EC_IMU_INT_L,         PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, motion_interrupt)
+GPIO_INT(TABLET_MODE_L,        PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
+
+/* USB-C interrupts */
+GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(E, 0), GPIO_INT_BOTH, tcpc_alert_event)
+GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(A, 2), GPIO_INT_BOTH, tcpc_alert_event)
+
+GPIO_INT(USB_C0_PPC_INT_ODL,	PIN(6, 2), GPIO_INT_BOTH, ppc_interrupt)
+GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(F, 5), GPIO_INT_BOTH, ppc_interrupt)
+
+GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(E, 4), GPIO_INT_BOTH, bc12_interrupt)
+GPIO_INT(USB_C1_MIX_INT_ODL,	PIN(0, 3), GPIO_INT_BOTH, bc12_interrupt)
+
+/* HDMI interrupts */
+
+/* Volume button interrupts */
+GPIO_INT(EC_VOLDN_BTN_ODL,		PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(EC_VOLUP_BTN_ODL,		PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+
+/* Power Sequencing Signals */
+GPIO(EN_PP3300_A,              PIN(A, 3), GPIO_OUT_LOW)
+GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
+GPIO(EN_PPVAR_VCCIN,           PIN(4, 3), GPIO_OUT_LOW) /* Enables VCCIN IMPV9 */
+GPIO(EC_PCH_DSW_PWROK,         PIN(C, 0), GPIO_OUT_LOW)
+
+/* Other wake sources */
+/*
+ * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an
+ * interrupt handler because it is automatically handled by the PSL.
+ *
+ * We need to lock the setting so this gpio can't be reconfigured to overdrive
+ * the real reset signal. (This is the PSL input pin not the real reset pin).
+ */
+GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH |
+					   GPIO_HIB_WAKE_HIGH |
+					   GPIO_LOCKED)
+
+/* AP/PCH Signals */
+GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
+GPIO(EC_PCH_RSMRST_ODL,        PIN(A, 6), GPIO_ODR_LOW) /* TODO - b/140950085 - implement TGL sequencing requirement */
+GPIO(EC_PCH_PWR_BTN_ODL,       PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
+GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
+GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
+GPIO_INT(EC_PROCHOT_IN_L,      PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
+GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
+
+GPIO(EC_PCH_INT_ODL,           PIN(B, 0), GPIO_ODR_HIGH)
+
+/* USB and USBC Signals */
+GPIO(EN_PP5000_USBA,		PIN(C, 6), GPIO_OUT_LOW)	/* Enable USB-A charging - all ports */
+GPIO(USB_A_LOW_PWR_OD,		PIN(6, 6), GPIO_ODR_LOW)	/* Don't limit USB-A charging by default - all ports */
+
+/*
+ * USB_C1 moved from GPIO32 to GPIO83 on boards with board ID >=1.
+ * GPIO83/EN_PP1800_A is DNS on board ID 0 and GPIO32 is N/C on board ID >=1
+ * so it's safe to define GPIOs compatible with both designs.
+ * TODO (b/149858568): remove board ID=0 support.
+ */
+GPIO(USB_C0_RT_RST_ODL,			PIN(6, 1), GPIO_ODR_LOW) /* USB_C0 Reset */
+GPIO(USB_C1_RT_RST_ODL,			PIN(8, 3), GPIO_ODR_LOW) /* USB_C1 Reset */
+GPIO(USB_C0_OC_ODL,			PIN(B, 1), GPIO_ODR_HIGH)
+GPIO(USB_C1_OC_ODL,			PIN(5, 0), GPIO_ODR_HIGH)
+/* There is currently no need to service this interrupt. */
+GPIO(USB_C0_RT_INT_ODL,			PIN(B, 7), GPIO_INPUT)
+GPIO(USB_C1_RT_INT_ODL,			PIN(4, 0), GPIO_INPUT)
+GPIO(USB_C0_FRS_EN,			PIN(6, 0), GPIO_OUT_LOW)
+GPIO(USB_C1_FRS_EN,			PIN(9, 4), GPIO_OUT_LOW)
+
+/* Don't have a load switch for retimer */
+UNIMPLEMENTED(USB_C0_LS_EN)
+UNIMPLEMENTED(USB_C1_LS_EN)
+
+/* Misc Signals */
+GPIO(EC_H1_PACKET_MODE,		PIN(7, 5), GPIO_OUT_LOW)	/* H1 Packet Mode */
+GPIO(EC_KB_BL_EN,		PIN(8, 6), GPIO_OUT_LOW)	/* Keyboard backlight enable*/
+GPIO(CCD_MODE_ODL,		PIN(E, 5), GPIO_INPUT)		/* Case Closed Debug Mode */
+GPIO(M2_SSD_PLA,		PIN(7, 0), GPIO_INPUT)		/* SSD power-loss acknowledgment */
+GPIO(M2_SSD_PLN,		PIN(A, 0), GPIO_ODR_HIGH)	/* SSD power-loss notification */
+
+
+/* LED */
+GPIO(LED_2_L,			PIN(C, 3), GPIO_OUT_HIGH)	/* Battery Full LED / Power LED: White */
+GPIO(LED_1_L,			PIN(C, 4), GPIO_OUT_HIGH)	/* Battery Charging LED: Amber */
+
+/*
+ * eDP backlight - both PCH and EC have enable pins that must be high
+ * for the backlight to turn on. Default state is high, and can be turned
+ * off during sleep states.
+ */
+GPIO(EC_EDP_BL_EN,             PIN(D, 3), GPIO_OUT_HIGH)
+
+/* I2C pins - Alternate function below configures I2C module on these pins */
+GPIO(EC_I2C0_SENSOR_SCL,       PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C0_SENSOR_SDA,       PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C1_USB_C0_SCL,       PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C1_USB_C0_SDA,       PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C2_USB_C1_SCL,       PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C2_USB_C1_SDA,       PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C3_USB_0_MIX_SCL,    PIN(D, 1), GPIO_INPUT)
+GPIO(EC_I2C3_USB_0_MIX_SDA,    PIN(D, 0), GPIO_INPUT)
+GPIO(EC_I2C4_USB_1_MIX_SCL,    PIN(F, 3), GPIO_INPUT)
+GPIO(EC_I2C4_USB_1_MIX_SDA,    PIN(F, 2), GPIO_INPUT)
+GPIO(EC_I2C5_POWER_SCL,        PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C5_POWER_SDA,        PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C7_EEPROM_SCL,       PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C7_EEPROM_SDA,       PIN(B, 2), GPIO_INPUT)
+
+/* Battery signals */
+GPIO(EC_BATT_PRES_ODL, 		PIN(E, 1), GPIO_INPUT)
+
+/* Alternate functions GPIO definitions */
+ALTERNATE(PIN_MASK(B, BIT(5) | BIT(4)), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V)) /* I2C0 */
+ALTERNATE(PIN_MASK(9, BIT(0) | BIT(2) | BIT(1)), 0, MODULE_I2C, 0)                   /* I2C1 SCL / I2C2 */
+ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)                                     /* I2C1 SDA */
+ALTERNATE(PIN_MASK(D, BIT(1) | BIT(0)), 0, MODULE_I2C, 0)                            /* I2C3 */
+ALTERNATE(PIN_MASK(F, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)                            /* I2C4 */
+ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)                            /* I2C5 */
+ALTERNATE(PIN_MASK(B, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)                            /* I2C7 */
+
+/* Keyboard pins */
+#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_00-01 */
+ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_02-07 */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_00-01 */
+GPIO(EC_KSO_02_INV, PIN(1, 7),                        GPIO_OUT_LOW)  /* KSO_02 */
+ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_03-09 */
+ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_10-13 */
+ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_14 */
+ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)                     /* EC_KB_BL_PWM */
+
+/* UART */
+ALTERNATE(PIN_MASK(6, BIT(5) | BIT(4)), 0, MODULE_UART, 0)                           /* UART from EC to Servo */
+
+/* Power Switch Logic (PSL) inputs */
+ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)                    /* GPIOD2 = EC_LID_OPEN */
+ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)  /* GPIO00 = ACOK_OD,
+                                                                       GPIO01 = H1_EC_PWR_BTN_ODL
+                                                                       GPIO02 = EC_RST_ODL */
+
+/* Temperature sensors */
+ALTERNATE(PIN_MASK(4, BIT(2) | BIT(4) | BIT(5)), 0, MODULE_ADC, 0) /* TEMP_SENSOR1,2,4 */
+ALTERNATE(PIN_MASK(F, BIT(1)), 0, MODULE_ADC, 0) /* TEMP_SENSOR3 */
+
+/* Unused signals */
+GPIO(UNUSED_GPIOD4,		PIN(D, 4), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIOC2,		PIN(C, 2), GPIO_INPUT | GPIO_PULL_UP)
+
diff --git a/board/collis/led.c b/board/collis/led.c
new file mode 100644
index 0000000000..9220b7a95c
--- /dev/null
+++ b/board/collis/led.c
@@ -0,0 +1,101 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "chipset.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
+
+__override const int led_charge_lvl_1;
+__override const int led_charge_lvl_2 = 95;
+
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_WHITE,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_BATTERY_LED,
+};
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_WHITE:
+		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_2_L, LED_ON_LVL);
+		break;
+	case EC_LED_COLOR_AMBER:
+		gpio_set_level(GPIO_LED_1_L, LED_ON_LVL);
+		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_battery(EC_LED_COLOR_WHITE);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(EC_LED_COLOR_AMBER);
+		else
+			led_set_color_battery(LED_OFF);
+	}
+
+	return EC_SUCCESS;
+}
+
+__override enum led_states board_led_get_state(enum led_states desired_state)
+{
+	if (desired_state == STATE_BATTERY_ERROR) {
+		if (chipset_in_state(CHIPSET_STATE_ON))
+			return desired_state;
+		else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
+			return STATE_DISCHARGE_S3;
+		else
+			return STATE_DISCHARGE_S5;
+	}
+	return desired_state;
+}
diff --git a/board/collis/sensors.c b/board/collis/sensors.c
new file mode 100644
index 0000000000..dac94535b3
--- /dev/null
+++ b/board/collis/sensors.c
@@ -0,0 +1,226 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Volteer family-specific sensor configuration */
+#include "accelgyro.h"
+#include "cbi_ec_fw_config.h"
+#include "cbi_ssfc.h"
+#include "common.h"
+#include "driver/accel_bma2x2.h"
+#include "driver/accel_kionix.h"
+#include "driver/accelgyro_bmi160.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "driver/accelgyro_icm426xx.h"
+#include "driver/accelgyro_icm_common.h"
+#include "driver/sync.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "keyboard_scan.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "util.h"
+
+/******************************************************************************/
+/* Sensors */
+static struct mutex g_lid_accel_mutex;
+static struct mutex g_base_mutex;
+
+/* sensor private data */
+static struct accelgyro_saved_data_t g_bma253_data;
+static struct kionix_accel_data g_kx022_data;
+
+static struct bmi_drv_data_t g_bmi160_data;
+static struct icm_drv_data_t g_icm426xx_data;
+
+/* Rotation matrix for the lid accelerometer */
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(1), 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
+
+const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+				       { 0, FLOAT_TO_FP(-1), 0 },
+				       { 0, 0, FLOAT_TO_FP(-1) } };
+
+const mat33_fp_t base_standard_ref_icm = {
+	{ 0, FLOAT_TO_FP(1), 0 },
+	{ FLOAT_TO_FP(1), 0, 0 },
+	{ 0, 0, FLOAT_TO_FP(-1) },
+};
+
+struct motion_sensor_t icm426xx_base_accel = {
+	.name = "Base Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.rot_standard_ref = &base_standard_ref_icm,
+	.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
+	.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
+	.default_range = 4, /* g */
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+		/* Sensor on in S3 */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	},
+};
+
+struct motion_sensor_t icm426xx_base_gyro = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &base_standard_ref_icm,
+	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
+	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
+};
+
+struct motion_sensor_t kx022_lid_accel = {
+	.name = "Lid Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_KX022,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_LID,
+	.drv = &kionix_accel_drv,
+	.mutex = &g_lid_accel_mutex,
+	.drv_data = &g_kx022_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
+	.rot_standard_ref = &lid_standard_ref,
+	.min_frequency = KX022_ACCEL_MIN_FREQ,
+	.max_frequency = KX022_ACCEL_MAX_FREQ,
+	.default_range = 2, /* g, to support tablet mode */
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	},
+};
+
+struct motion_sensor_t motion_sensors[] = {
+	[LID_ACCEL] = {
+		.name = "Lid Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMA255,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &bma2x2_accel_drv,
+		.mutex = &g_lid_accel_mutex,
+		.drv_data = &g_bma253_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
+		.rot_standard_ref = &lid_standard_ref,
+		.min_frequency = BMA255_ACCEL_MIN_FREQ,
+		.max_frequency = BMA255_ACCEL_MAX_FREQ,
+		.default_range = 2, /* g, to support tablet mode */
+		.config = {
+			/* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+			/* Sensor on in S3 */
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+		},
+	},
+	[BASE_ACCEL] = {
+		.name = "Base Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMI160,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &bmi160_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = &g_bmi160_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = BMI_ACCEL_MIN_FREQ,
+		.max_frequency = BMI_ACCEL_MAX_FREQ,
+		.default_range = 4, /* g */
+		.config = {
+			/* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+			/* Sensor on in S3 */
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+		},
+	},
+
+	[BASE_GYRO] = {
+		.name = "Base Gyro",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMI160,
+		.type = MOTIONSENSE_TYPE_GYRO,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &bmi160_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = &g_bmi160_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+		.default_range = 1000, /* dps */
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = BMI_GYRO_MIN_FREQ,
+		.max_frequency = BMI_GYRO_MAX_FREQ,
+	},
+};
+unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	if (get_cbi_ssfc_base_sensor() == SSFC_SENSOR_BASE_ICM426XX)
+		icm426xx_interrupt(signal);
+	else
+		bmi160_interrupt(signal);
+}
+
+static void baseboard_sensors_init(void)
+{
+	if (get_cbi_ssfc_lid_sensor() == SSFC_SENSOR_LID_KX022) {
+		motion_sensors[LID_ACCEL] = kx022_lid_accel;
+		ccprints("LID_ACCEL is KX022");
+	} else
+		ccprints("LID_ACCEL is BMA253");
+
+	if (get_cbi_ssfc_base_sensor() == SSFC_SENSOR_BASE_ICM426XX) {
+		motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
+		motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
+		ccprints("BASE ACCEL is ICM426XX");
+	} else
+		ccprints("BASE ACCEL IS BMI160");
+
+	/* Enable interrupt for the accel/gyro sensor */
+	gpio_enable_interrupt(GPIO_EC_IMU_INT_L);
+}
+DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_DEFAULT);
diff --git a/board/collis/vif_override.xml b/board/collis/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/collis/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/constitution/board.c b/board/constitution/board.c
new file mode 100644
index 0000000000..3bb1142496
--- /dev/null
+++ b/board/constitution/board.c
@@ -0,0 +1,544 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "adc.h"
+#include "builtin/assert.h"
+#include "button.h"
+#include "cec.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "driver/cec/bitbang.h"
+#include "driver/tcpm/tcpci.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "peripheral_charger.h"
+#include "power.h"
+#include "power_button.h"
+#include "pse_ltc4291.h"
+#include "switch.h"
+#include "throttle_ap.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+#include <stdbool.h>
+
+/* Console output macros */
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+
+static void power_monitor(void);
+DECLARE_DEFERRED(power_monitor);
+
+/*
+ * The LTC4291 is a power over ethernet (PoE) power sourcing equipment (PSE)
+ * controller.
+ *
+ * Port 1: 100W
+ * Port 2-4: 15W
+ */
+const int pse_port_hpmd[4] = {
+	LTC4291_HPMD_MAX,
+	LTC4291_HPMD_MIN,
+	LTC4291_HPMD_MIN,
+	LTC4291_HPMD_MIN,
+};
+
+/******************************************************************************/
+/* USB-A charging control */
+
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_PP5000_USBA,
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
+
+/******************************************************************************/
+
+/* CEC ports */
+const struct cec_config_t cec_config[] = {
+	[CEC_PORT_0] = {
+		.drv = &bitbang_cec_drv,
+		.offline_policy = NULL,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(cec_config) == CEC_PORT_COUNT);
+
+int board_set_active_charge_port(int port)
+{
+	CPRINTS("Requested charge port change to %d", port);
+
+	/*
+	 * The charge manager may ask us to switch to no charger if we're
+	 * running off USB-C only but upstream doesn't support PD. It requires
+	 * that we accept this switch otherwise it triggers an assert and EC
+	 * reset; it's not possible to boot the AP anyway, but we want to avoid
+	 * resetting the EC so we can continue to do the "low power" LED blink.
+	 */
+	if (port == CHARGE_PORT_NONE)
+		return EC_SUCCESS;
+
+	if (port < 0 || CHARGE_PORT_COUNT <= port)
+		return EC_ERROR_INVAL;
+
+	if (port == charge_manager_get_active_charge_port())
+		return EC_SUCCESS;
+
+	/* Don't charge from a source port */
+	if (board_vbus_source_enabled(port))
+		return EC_ERROR_INVAL;
+
+	if (!chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
+		int bj_active, bj_requested;
+
+		if (charge_manager_get_active_charge_port() != CHARGE_PORT_NONE)
+			/* Change is only permitted while the system is off */
+			return EC_ERROR_INVAL;
+
+		/*
+		 * Current setting is no charge port but the AP is on, so the
+		 * charge manager is out of sync (probably because we're
+		 * reinitializing after sysjump). Reject requests that aren't
+		 * in sync with our outputs.
+		 */
+		bj_active = !gpio_get_level(GPIO_EN_PPVAR_BJ_ADP_L);
+		bj_requested = port == CHARGE_PORT_BARRELJACK;
+		if (bj_active != bj_requested)
+			return EC_ERROR_INVAL;
+	}
+
+	CPRINTS("New charger p%d", port);
+
+	switch (port) {
+	case CHARGE_PORT_TYPEC0:
+	case CHARGE_PORT_TYPEC1:
+	case CHARGE_PORT_TYPEC2:
+		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 1);
+		break;
+	case CHARGE_PORT_BARRELJACK:
+		/* Make sure BJ adapter is sourcing power */
+		if (gpio_get_level(GPIO_BJ_ADP_PRESENT_ODL))
+			return EC_ERROR_INVAL;
+		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 0);
+		break;
+	default:
+		return EC_ERROR_INVAL;
+	}
+
+	return EC_SUCCESS;
+}
+
+static uint8_t usbc_overcurrent;
+static int32_t base_5v_power_s5;
+static int32_t base_5v_power_z1;
+
+/*
+ * Power usage for each port as measured or estimated.
+ * Units are milliwatts (5v x ma current)
+ */
+
+/* PP5000_S5 loads */
+#define PWR_S5_BASE_LOAD (5 * 1431)
+#define PWR_S5_REAR_HIGH (5 * 1737)
+#define PWR_S5_REAR_LOW (5 * 1055)
+#define PWR_S5_HDMI (5 * 580)
+#define PWR_S5_MAX (5 * 10000)
+#define REAR_DELTA (PWR_S5_REAR_HIGH - PWR_S5_REAR_LOW)
+
+/* PP5000_Z1 loads */
+#define PWR_Z1_BASE_LOAD (5 * 5)
+#define PWR_Z1_C_HIGH (5 * 3600)
+#define PWR_Z1_C_LOW (5 * 2000)
+#define PWR_Z1_MAX (5 * 9000)
+/*
+ * Update the 5V power usage, assuming no throttling,
+ * and invoke the power monitoring.
+ */
+static void update_5v_usage(void)
+{
+	int rear_ports = 0;
+
+	/*
+	 * Recalculate the 5V load, assuming no throttling.
+	 */
+	base_5v_power_s5 = PWR_S5_BASE_LOAD;
+	if (!gpio_get_level(GPIO_USB_A0_OC_ODL)) {
+		rear_ports++;
+		base_5v_power_s5 += PWR_S5_REAR_LOW;
+	}
+	if (!gpio_get_level(GPIO_USB_A1_OC_ODL)) {
+		rear_ports++;
+		base_5v_power_s5 += PWR_S5_REAR_LOW;
+	}
+	/*
+	 * Only 1 rear port can run higher power at a time.
+	 */
+	if (rear_ports > 0)
+		base_5v_power_s5 += PWR_S5_REAR_HIGH - PWR_S5_REAR_LOW;
+	if (!gpio_get_level(GPIO_HDMI_CONN_OC_ODL))
+		base_5v_power_s5 += PWR_S5_HDMI;
+	base_5v_power_z1 = PWR_Z1_BASE_LOAD;
+	if (usbc_overcurrent)
+		base_5v_power_z1 += PWR_Z1_C_HIGH;
+	/*
+	 * Invoke the power handler immediately.
+	 */
+	hook_call_deferred(&power_monitor_data, 0);
+}
+DECLARE_DEFERRED(update_5v_usage);
+/*
+ * Start power monitoring after ADCs have been initialised.
+ */
+DECLARE_HOOK(HOOK_INIT, update_5v_usage, HOOK_PRIO_INIT_ADC + 1);
+
+static void port_ocp_interrupt(enum gpio_signal signal)
+{
+	hook_call_deferred(&update_5v_usage_data, 0);
+}
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/******************************************************************************/
+/*
+ * Barrel jack power supply handling
+ *
+ * EN_PPVAR_BJ_ADP_L must default active to ensure we can power on when the
+ * barrel jack is connected, and the USB-C port can bring the EC up fine in
+ * dead-battery mode. Both the USB-C and barrel jack switches do reverse
+ * protection, so we're safe to turn one on then the other off- but we should
+ * only do that if the system is off since it might still brown out.
+ */
+
+#define ADP_DEBOUNCE_MS 1000 /* Debounce time for BJ plug/unplug */
+/* Debounced connection state of the barrel jack */
+static int8_t adp_connected = -1;
+static void adp_connect_deferred(void)
+{
+	struct charge_port_info pi = { 0 };
+	int connected = !gpio_get_level(GPIO_BJ_ADP_PRESENT_ODL);
+
+	/* Debounce */
+	if (connected == adp_connected)
+		return;
+	if (connected)
+		ec_bj_power(&pi.voltage, &pi.current);
+	charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED,
+				     DEDICATED_CHARGE_PORT, &pi);
+	adp_connected = connected;
+}
+DECLARE_DEFERRED(adp_connect_deferred);
+
+/* IRQ for BJ plug/unplug. It shouldn't be called if BJ is the power source. */
+void adp_connect_interrupt(enum gpio_signal signal)
+{
+	hook_call_deferred(&adp_connect_deferred_data, ADP_DEBOUNCE_MS * MSEC);
+}
+
+static void adp_state_init(void)
+{
+	ASSERT(CHARGE_PORT_ENUM_COUNT == CHARGE_PORT_COUNT);
+	/*
+	 * Initialize all charge suppliers to 0. The charge manager waits until
+	 * all ports have reported in before doing anything.
+	 */
+	for (int i = 0; i < CHARGE_PORT_COUNT; i++) {
+		for (int j = 0; j < CHARGE_SUPPLIER_COUNT; j++)
+			charge_manager_update_charge(j, i, NULL);
+	}
+
+	/* Report charge state from the barrel jack. */
+	adp_connect_deferred();
+}
+DECLARE_HOOK(HOOK_INIT, adp_state_init, HOOK_PRIO_INIT_CHARGE_MANAGER + 1);
+
+static void board_init(void)
+{
+	gpio_enable_interrupt(GPIO_BJ_ADP_PRESENT_ODL);
+	gpio_enable_interrupt(GPIO_HDMI_CONN_OC_ODL);
+	gpio_enable_interrupt(GPIO_USB_A0_OC_ODL);
+	gpio_enable_interrupt(GPIO_USB_A1_OC_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+void board_overcurrent_event(int port, int is_overcurrented)
+{
+	/* Check that port number is valid. */
+	if ((port < 0) || (port >= CONFIG_USB_PD_PORT_MAX_COUNT))
+		return;
+	usbc_overcurrent = is_overcurrented;
+	update_5v_usage();
+}
+/*
+ * Power monitoring and management.
+ *
+ * the power budgets are met without letting the system fall into
+ * power deficit (perhaps causing a brownout).
+ *
+ * There are 2 power budgets that need to be managed:
+ * The overall goal is to gracefully manage the power demand so that
+ *  - overall system power as measured on the main power supply rail.
+ *  - 5V power delivered to the USB and HDMI ports.
+ *
+ * The actual system power demand is calculated from the VBUS voltage and
+ * the input current (read from a shunt), averaged over 5 readings.
+ * The power budget limit is from the charge manager.
+ *
+ * The 5V power cannot be read directly. Instead, we rely on overcurrent
+ * inputs from the USB and HDMI ports to indicate that the port is in use
+ * (and drawing maximum power).
+ *
+ * There are 3 throttles that can be applied (in priority order):
+ *
+ *  - Type A BC1.2 rear port restriction (3W)
+ *  - Type C PD (throttle to 1.5A if sourcing)
+ *  - Turn on PROCHOT, which immediately throttles the CPU.
+ *
+ *  The first 3 throttles affect both the system power and the 5V rails.
+ *  The third is a last resort to force an immediate CPU throttle to
+ *  reduce the overall power use.
+ *
+ *  The strategy is to determine what the state of the throttles should be,
+ *  and to then turn throttles off or on as needed to match this.
+ *
+ *  This function runs on demand, or every 2 ms when the CPU is up,
+ *  and continually monitors the power usage, applying the
+ *  throttles when necessary.
+ *
+ *  All measurements are in milliwatts.
+ */
+#define THROT_TYPE_A_REAR BIT(0)
+#define THROT_TYPE_C0 BIT(1)
+#define THROT_TYPE_C1 BIT(2)
+#define THROT_TYPE_C2 BIT(3)
+#define THROT_PROCHOT BIT(4)
+
+/*
+ * Power gain if Type C port is limited.
+ */
+#define POWER_GAIN_TYPE_C 8800
+/*
+ * Power is averaged over 10 ms, with a reading every 2 ms.
+ */
+#define POWER_DELAY_MS 2
+#define POWER_READINGS (10 / POWER_DELAY_MS)
+
+static void power_monitor(void)
+{
+	static uint32_t current_state;
+	static uint32_t history[POWER_READINGS];
+	static uint8_t index;
+	int32_t delay;
+	uint32_t new_state = 0, diff;
+	int32_t headroom_5v_s5 = PWR_S5_MAX - base_5v_power_s5;
+	int32_t headroom_5v_z1 = PWR_Z1_MAX - base_5v_power_z1;
+
+	/*
+	 * If CPU is off or suspended, no need to throttle
+	 * or restrict power.
+	 */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF | CHIPSET_STATE_SUSPEND)) {
+		/*
+		 * Slow down monitoring, assume no throttling required.
+		 */
+		delay = 20 * MSEC;
+		/*
+		 * Clear the first entry of the power table so that
+		 * it is re-initilalised when the CPU starts.
+		 */
+		history[0] = 0;
+	} else {
+		int32_t charger_mw;
+
+		delay = POWER_DELAY_MS * MSEC;
+		/*
+		 * Get current charger limit (in mw).
+		 * If not configured yet, skip.
+		 */
+		charger_mw = charge_manager_get_power_limit_uw() / 1000;
+		if (charger_mw != 0) {
+			int32_t gap, total, max, power;
+			int i;
+
+			/*
+			 * Read power usage.
+			 */
+			power = (adc_read_channel(ADC_VBUS) *
+				 adc_read_channel(ADC_PPVAR_IMON)) /
+				1000;
+			/* Init power table */
+			if (history[0] == 0) {
+				for (i = 0; i < POWER_READINGS; i++)
+					history[i] = power;
+			}
+			/*
+			 * Update the power readings and
+			 * calculate the average and max.
+			 */
+			history[index] = power;
+			index = (index + 1) % POWER_READINGS;
+			total = 0;
+			max = history[0];
+			for (i = 0; i < POWER_READINGS; i++) {
+				total += history[i];
+				if (history[i] > max)
+					max = history[i];
+			}
+			/*
+			 * For Type-C power supplies, there is
+			 * less tolerance for exceeding the rating,
+			 * so use the max power that has been measured
+			 * over the measuring period.
+			 * For barrel-jack supplies, the rating can be
+			 * exceeded briefly, so use the average.
+			 */
+			if (charge_manager_get_supplier() == CHARGE_SUPPLIER_PD)
+				power = max;
+			else
+				power = total / POWER_READINGS;
+			/*
+			 * Calculate gap, and if negative, power
+			 * demand is exceeding configured power budget, so
+			 * throttling is required to reduce the demand.
+			 */
+			gap = charger_mw - power;
+			/*
+			 * Limiting type-A power rear ports.
+			 */
+			if (gap <= 0) {
+				new_state |= THROT_TYPE_A_REAR;
+				headroom_5v_s5 += REAR_DELTA;
+			}
+			/*
+			 * If the type-C port is sourcing power,
+			 * check whether it should be throttled.
+			 */
+			if (ppc_is_sourcing_vbus(0) && gap <= 0) {
+				new_state |= THROT_TYPE_C0;
+				headroom_5v_z1 += PWR_Z1_C_HIGH - PWR_Z1_C_LOW;
+				if (!(current_state & THROT_TYPE_C0))
+					gap += POWER_GAIN_TYPE_C;
+			}
+			/*
+			 * If the type-C port is sourcing power,
+			 * check whether it should be throttled.
+			 */
+			if (ppc_is_sourcing_vbus(1) && gap <= 0) {
+				new_state |= THROT_TYPE_C1;
+				headroom_5v_z1 += PWR_Z1_C_HIGH - PWR_Z1_C_LOW;
+				if (!(current_state & THROT_TYPE_C1))
+					gap += POWER_GAIN_TYPE_C;
+			}
+			/*
+			 * If the type-C port is sourcing power,
+			 * check whether it should be throttled.
+			 */
+			if (ppc_is_sourcing_vbus(2) && gap <= 0) {
+				new_state |= THROT_TYPE_C2;
+				headroom_5v_z1 += PWR_Z1_C_HIGH - PWR_Z1_C_LOW;
+				if (!(current_state & THROT_TYPE_C2))
+					gap += POWER_GAIN_TYPE_C;
+			}
+			/*
+			 * As a last resort, turn on PROCHOT to
+			 * throttle the CPU.
+			 */
+			if (gap <= 0)
+				new_state |= THROT_PROCHOT;
+		}
+	}
+	/*
+	 * Check the 5v power usage and if necessary,
+	 * adjust the throttles in priority order.
+	 *
+	 * Either throttle may have already been activated by
+	 * the overall power control.
+	 *
+	 * We rely on the overcurrent detection to inform us
+	 * if the port is in use.
+	 *
+	 *  - If type C not already throttled:
+	 *	* If not overcurrent, prefer to limit type C [1].
+	 *	* If in overcurrentuse:
+	 *		- limit type A first [2]
+	 *		- If necessary, limit type C [3].
+	 *  - If type A not throttled, if necessary limit it [2].
+	 */
+	if (headroom_5v_z1 < 0) {
+		/*
+		 * Check whether type C is not throttled,
+		 * and is not overcurrent.
+		 */
+		if (!((new_state & THROT_TYPE_C0) || usbc_overcurrent)) {
+			/*
+			 * [1] Type C not in overcurrent, throttle it.
+			 */
+			headroom_5v_z1 += PWR_Z1_C_HIGH - PWR_Z1_C_LOW;
+			new_state |= THROT_TYPE_C0;
+		}
+		/*
+		 * [2] If still under-budget, limit type C.
+		 * No need to check if it is already throttled or not.
+		 */
+		if (headroom_5v_z1 < 0)
+			new_state |= THROT_TYPE_C0;
+	}
+	if (headroom_5v_s5 < 0) {
+		/*
+		 * If type A rear not already throttled, and power still
+		 * needed, limit type A rear.
+		 */
+		if (!(new_state & THROT_TYPE_A_REAR) && headroom_5v_s5 < 0) {
+			headroom_5v_s5 += PWR_S5_REAR_HIGH - PWR_S5_REAR_LOW;
+			new_state |= THROT_TYPE_A_REAR;
+		}
+	}
+	/*
+	 * Turn the throttles on or off if they have changed.
+	 */
+	diff = new_state ^ current_state;
+	current_state = new_state;
+	if (diff & THROT_PROCHOT) {
+		int prochot = (new_state & THROT_PROCHOT) ? 0 : 1;
+
+		gpio_set_level(GPIO_EC_PROCHOT_ODL, prochot);
+	}
+	if (diff & THROT_TYPE_C0) {
+		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C0) ?
+						TYPEC_RP_1A5 :
+						TYPEC_RP_3A0;
+
+		ppc_set_vbus_source_current_limit(0, rp);
+		tcpm_select_rp_value(0, rp);
+		pd_update_contract(0);
+	}
+	if (diff & THROT_TYPE_C1) {
+		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C1) ?
+						TYPEC_RP_1A5 :
+						TYPEC_RP_3A0;
+
+		ppc_set_vbus_source_current_limit(1, rp);
+		tcpm_select_rp_value(1, rp);
+		pd_update_contract(1);
+	}
+	if (diff & THROT_TYPE_C2) {
+		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C2) ?
+						TYPEC_RP_1A5 :
+						TYPEC_RP_3A0;
+
+		ppc_set_vbus_source_current_limit(2, rp);
+		tcpm_select_rp_value(2, rp);
+		pd_update_contract(2);
+	}
+	if (diff & THROT_TYPE_A_REAR) {
+		int typea_bc = (new_state & THROT_TYPE_A_REAR) ? 1 : 0;
+
+		gpio_set_level(GPIO_USB_A_LOW_PWR0_OD, typea_bc);
+		gpio_set_level(GPIO_USB_A_LOW_PWR1_OD, typea_bc);
+	}
+	hook_call_deferred(&power_monitor_data, delay);
+}
diff --git a/board/constitution/board.h b/board/constitution/board.h
new file mode 100644
index 0000000000..a8287f8579
--- /dev/null
+++ b/board/constitution/board.h
@@ -0,0 +1,199 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Brask board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "compile_time_macros.h"
+
+/* Baseboard features */
+#include "baseboard.h"
+
+#define CONFIG_MP2964
+
+/* Barrel Jack */
+#define DEDICATED_CHARGE_PORT 3
+
+/* HDMI CEC */
+#define CONFIG_CEC
+#define CONFIG_CEC_BITBANG
+#define CEC_GPIO_OUT GPIO_HDMIB_CEC_OUT
+#define CEC_GPIO_IN GPIO_HDMIB_CEC_IN
+#define CEC_GPIO_PULL_UP GPIO_HDMIB_CEC_PULL_UP
+
+/* USB Type A Features */
+#define USB_PORT_COUNT 2
+#define CONFIG_USB_PORT_POWER_DUMB
+
+/* USB Type C and USB PD defines */
+#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
+
+#define CONFIG_IO_EXPANDER
+#define CONFIG_IO_EXPANDER_NCT38XX
+#define CONFIG_IO_EXPANDER_PORT_COUNT 2
+
+#define CONFIG_USB_PD_PPC
+#define CONFIG_USB_PD_TCPM_RT1715
+#define CONFIG_USBC_RETIMER_INTEL_BB
+
+#define CONFIG_USBC_PPC_SYV682X
+#undef CONFIG_SYV682X_HV_ILIM
+#define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_5_50
+
+/* TODO: b/177608416 - measure and check these values on brya */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
+
+/* The design should support up to 100W. */
+/* TODO(b/197702356): Set the max PD to 60W now and change it
+ * to 100W after we verify it.
+ */
+#define PD_OPERATING_POWER_MW CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
+#define PD_MAX_POWER_MW 100000
+#define PD_MAX_CURRENT_MA 5000
+#define PD_MAX_VOLTAGE_MV 20000
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
+
+/*
+ * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
+ * signal.
+ */
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
+#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_OD
+#define GPIO_RECOVERY_L_2 GPIO_GSC_EC_RECOVERY_BTN_OD
+
+/* I2C Bus Configuration */
+#define I2C_PORT_USB_C0_C2_TCPC NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT0_0
+
+#define I2C_PORT_USB_C0_C2_PPC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT4_1
+
+#define I2C_PORT_USB_C0_C2_BC12 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT4_1
+
+#define I2C_PORT_USB_C0_C2_MUX NPCX_I2C_PORT3_0
+
+#define I2C_PORT_PSE NPCX_I2C_PORT5_0
+#define I2C_PORT_ADB NPCX_I2C_PORT6_1
+
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+
+#define I2C_ADDR_MP2964_FLAGS 0x20
+
+#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x59
+
+/* Enabling Thunderbolt-compatible mode */
+#define CONFIG_USB_PD_TBT_COMPAT_MODE
+
+/* Enabling USB4 mode */
+#define CONFIG_USB_PD_USB4
+#define CONFIG_USB_PD_DATA_RESET_MSG
+
+/* Retimer */
+#define CONFIG_USBC_RETIMER_FW_UPDATE
+
+/* Thermal features */
+#define CONFIG_THERMISTOR
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_TEMP_SENSOR_POWER
+#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
+
+/* ADC */
+#define CONFIG_ADC
+
+/* PSE */
+#define CONFIG_PSE_LTC4291
+
+/*
+ * TODO(b/197478860): Enable the fan control. We need
+ * to check the sensor value and adjust the fan speed.
+ */
+#define CONFIG_FANS FAN_CH_COUNT
+
+/* Include math_util for bitmask_uint64 used in pd_timers */
+#define CONFIG_MATH_UTIL
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h" /* needed by registers.h */
+#include "registers.h"
+#include "usbc_config.h"
+
+enum charge_port {
+	CHARGE_PORT_TYPEC0,
+	CHARGE_PORT_TYPEC1,
+	CHARGE_PORT_TYPEC2,
+	CHARGE_PORT_BARRELJACK,
+	CHARGE_PORT_ENUM_COUNT
+};
+
+enum adc_channel {
+	ADC_TEMP_SENSOR_1_CPU,
+	ADC_TEMP_SENSOR_2_CPU_VR,
+	ADC_TEMP_SENSOR_3_WIFI,
+	ADC_TEMP_SENSOR_4_DIMM,
+	ADC_VBUS,
+	ADC_PPVAR_IMON, /* ADC3 */
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1_CPU,
+	TEMP_SENSOR_2_CPU_VR,
+	TEMP_SENSOR_3_WIFI,
+	TEMP_SENSOR_4_DIMM,
+	TEMP_SENSOR_COUNT
+};
+
+enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_C2_NCT38XX, IOEX_PORT_COUNT };
+
+enum pwm_channel {
+	PWM_CH_LED_WHITE, /* PWM0 */
+	PWM_CH_FAN, /* PWM5 */
+	PWM_CH_LED_RED, /* PWM2 */
+	PWM_CH_COUNT
+};
+
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT };
+
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT };
+
+enum cec_port { CEC_PORT_0, CEC_PORT_COUNT };
+
+extern void adp_connect_interrupt(enum gpio_signal signal);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/constitution/build.mk b/board/constitution/build.mk
new file mode 100644
index 0000000000..2301983a1f
--- /dev/null
+++ b/board/constitution/build.mk
@@ -0,0 +1,22 @@
+# -*- makefile -*-
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Brask board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx9
+CHIP_VARIANT:=npcx9m3f
+BASEBOARD:=brask
+
+board-y=
+board-y+=board.o
+board-y+=fans.o
+board-y+=fw_config.o
+board-y+=i2c.o
+board-y+=led.o
+board-y+=pwm.o
+board-y+=sensors.o
+board-y+=usbc_config.o
diff --git a/board/constitution/ec.tasklist b/board/constitution/ec.tasklist
new file mode 100644
index 0000000000..2d063fe252
--- /dev/null
+++ b/board/constitution/ec.tasklist
@@ -0,0 +1,28 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ *
+ * USB_CHG_Px tasks must be contiguous (see USB_CHG_PORT_TO_TASK_ID(x)).
+ * PD_Cx tasks must be contiguous (see PD_PORT_TO_TASK_ID(x))
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P2, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C2, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_shared_alert_task, (BIT(2) | BIT(0)), LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CEC, cec_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/constitution/fans.c b/board/constitution/fans.c
new file mode 100644
index 0000000000..ecc93bd330
--- /dev/null
+++ b/board/constitution/fans.c
@@ -0,0 +1,50 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Physical fans. These are logically separate from pwm_channels. */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "fan.h"
+#include "fan_chip.h"
+#include "hooks.h"
+#include "pwm.h"
+
+/* MFT channels. These are logically separate from pwm_channels. */
+const struct mft_t mft_channels[] = {
+	[MFT_CH_0] = {
+		.module = NPCX_MFT_MODULE_2,
+		.clk_src = TCKC_LFCLK,
+		.pwm_id = PWM_CH_FAN,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
+
+static const struct fan_conf fan_conf_0 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
+	.pgood_gpio = -1,
+	.enable_gpio = GPIO_EN_PP5000_FAN,
+};
+
+/*
+ * TOOD(b/197478860): need to update for real fan
+ *
+ * Prototype fan spins at about 7200 RPM at 100% PWM.
+ * Set minimum at around 30% PWM.
+ */
+static const struct fan_rpm fan_rpm_0 = {
+	.rpm_min = 2200,
+	.rpm_start = 2200,
+	.rpm_max = 7200,
+};
+
+const struct fan_t fans[FAN_CH_COUNT] = {
+	[FAN_CH_0] = {
+		.conf = &fan_conf_0,
+		.rpm = &fan_rpm_0,
+	},
+};
diff --git a/board/constitution/fw_config.c b/board/constitution/fw_config.c
new file mode 100644
index 0000000000..957a5c8c50
--- /dev/null
+++ b/board/constitution/fw_config.c
@@ -0,0 +1,65 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "fw_config.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+static union brask_cbi_fw_config fw_config;
+BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
+
+/*
+ * FW_CONFIG defaults for brask if the CBI.FW_CONFIG data is not
+ * initialized.
+ */
+static const union brask_cbi_fw_config fw_config_defaults = {
+	.audio = DB_NAU88L25B_I2S,
+	.bj_power = BJ_135W,
+};
+
+/*
+ * Barrel-jack power adapter ratings.
+ */
+static const struct {
+	int voltage;
+	int current;
+} bj_power[] = {
+	[BJ_135W] = { /* 0 - 135W (also default) */
+			.voltage = 19500,
+			.current = 6920
+	},
+	[BJ_230W] = { /* 1 - 230W */
+			.voltage = 19500,
+			.current = 11800
+	}
+};
+
+/****************************************************************************
+ * Brask FW_CONFIG access
+ */
+void board_init_fw_config(void)
+{
+	if (cbi_get_fw_config(&fw_config.raw_value)) {
+		CPRINTS("CBI: Read FW_CONFIG failed, using board defaults");
+		fw_config = fw_config_defaults;
+	}
+}
+
+void ec_bj_power(uint32_t *voltage, uint32_t *current)
+{
+	unsigned int bj;
+
+	bj = fw_config.bj_power;
+	/* Out of range value defaults to 0 */
+	if (bj >= ARRAY_SIZE(bj_power))
+		bj = 0;
+	*voltage = bj_power[bj].voltage;
+	*current = bj_power[bj].current;
+}
diff --git a/board/constitution/fw_config.h b/board/constitution/fw_config.h
new file mode 100644
index 0000000000..c2afd4c603
--- /dev/null
+++ b/board/constitution/fw_config.h
@@ -0,0 +1,41 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __BOARD_BRASK_FW_CONFIG_H_
+#define __BOARD_BRASK_FW_CONFIG_H_
+
+#include <stdint.h>
+
+/****************************************************************************
+ * CBI FW_CONFIG layout for Brask board.
+ *
+ * Source of truth is the project/brask/brask/config.star configuration file.
+ */
+enum ec_cfg_audio_type { DB_AUDIO_UNKNOWN = 0, DB_NAU88L25B_I2S = 1 };
+
+enum ec_cfg_bj_power { BJ_135W = 0, BJ_230W = 1 };
+
+union brask_cbi_fw_config {
+	struct {
+		uint32_t audio : 3;
+		uint32_t bj_power : 2;
+		uint32_t reserved_1 : 27;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Read the cached FW_CONFIG.  Guaranteed to have valid values.
+ *
+ * @return the FW_CONFIG for the board.
+ */
+union brask_cbi_fw_config get_fw_config(void);
+
+/**
+ * Get the barrel-jack power from FW_CONFIG.
+ */
+void ec_bj_power(uint32_t *voltage, uint32_t *current);
+
+#endif /* __BOARD_BRASK_FW_CONFIG_H_ */
diff --git a/board/constitution/gpio.inc b/board/constitution/gpio.inc
new file mode 100644
index 0000000000..fb2915a3a7
--- /dev/null
+++ b/board/constitution/gpio.inc
@@ -0,0 +1,182 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* INTERRUPT GPIOs: */
+
+GPIO_INT(ACOK_OD,                    PIN(0, 0), GPIO_INT_BOTH, extpower_interrupt)
+GPIO_INT(EC_PROCHOT_IN_L,            PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
+GPIO_INT(EC_WP_ODL,                  PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(GSC_EC_PWR_BTN_ODL,         PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
+GPIO_INT(SEQ_EC_ALL_SYS_PG,          PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_DSW_PWROK,           PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_RSMRST_ODL,          PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,                   PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,                  PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SYS_SLP_S0IX_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(USB_C0_BC12_INT_ODL,        PIN(C, 6), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C0_C2_TCPC_INT_ODL,     PIN(A, 0), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C0_PPC_INT_ODL,         PIN(6, 2), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C0_RT_INT_ODL,          PIN(B, 1), GPIO_INT_FALLING, retimer_interrupt)
+GPIO_INT(USB_C1_BC12_INT_ODL,        PIN(A, 2), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C1_PPC_INT_ODL,         PIN(F, 5), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C1_TCPC_INT_ODL,        PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C2_BC12_INT_ODL,        PIN(8, 3), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C2_PPC_INT_ODL,         PIN(7, 0), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(BJ_ADP_PRESENT_ODL,         PIN(8, 2), GPIO_INT_BOTH | GPIO_PULL_UP, adp_connect_interrupt)
+GPIO_INT(EC_RECOVERY_BTN_OD,         PIN(2, 3), GPIO_INT_BOTH, button_interrupt)
+GPIO_INT(HDMI_CONN_OC_ODL,           PIN(5, 0), GPIO_INPUT | GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(USB_A0_OC_ODL,              PIN(3, 1), GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(USB_A1_OC_ODL,              PIN(3, 0), GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH, port_ocp_interrupt)
+
+/* PSE controller */
+GPIO(EC_PSE_PWM_INT,                 PIN(9, 6), GPIO_INPUT)
+GPIO(EC_RST_LTC4291,                 PIN(9, 7), GPIO_OUT_HIGH)
+
+/* TPU */
+GPIO(PP3300_TPU_EN,                  PIN(2, 6), GPIO_OUT_HIGH)
+
+/* Wake EC */
+GPIO(WLAN_PCIE_WAKE_EC,              PIN(4, 1), GPIO_INPUT)
+GPIO(LAN_WAKE_EC,                    PIN(9, 3), GPIO_INPUT)
+
+/* ADB Scaler signals */
+GPIO(ADB_WAKEUP_EC,                  PIN(2, 5), GPIO_INPUT)
+
+/* CCD */
+GPIO(CCD_MODE_ODL,                   PIN(E, 5), GPIO_INPUT)
+
+/* Security */
+GPIO(EC_ENTERING_RW,                 PIN(0, 3), GPIO_OUT_LOW)
+GPIO(EC_GSC_PACKET_MODE,             PIN(7, 5), GPIO_OUT_LOW)
+
+/* Fan */
+GPIO(EN_PP5000_FAN,                  PIN(6, 1), GPIO_OUT_HIGH)
+
+/* ADC, need to check the usage */
+GPIO(ANALOG_PPVAR_PWR_IN_IMON_EC,    PIN(4, 2), GPIO_INPUT)
+
+/* BarrelJack */
+GPIO(EN_PPVAR_BJ_ADP_L,              PIN(0, 4), GPIO_OUT_LOW)
+
+/* Chipset PCH */
+GPIO(EC_PCHHOT_ODL,                  PIN(7, 4), GPIO_INPUT)
+GPIO(EC_PCH_INT_ODL,                 PIN(B, 0), GPIO_ODR_HIGH)
+GPIO(EC_PCH_RSMRST_L,                PIN(A, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_RTCRST,                  PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_SYS_PWROK,               PIN(3, 7), GPIO_OUT_LOW)
+GPIO(EC_PCH_WAKE_ODL,                PIN(C, 0), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_ODL,                 PIN(6, 3), GPIO_ODR_HIGH)
+GPIO(EN_S5_RAILS,                    PIN(B, 6), GPIO_OUT_LOW)
+GPIO(PCH_PWROK,                      PIN(7, 2), GPIO_OUT_LOW)
+GPIO(SYS_RST_ODL,                    PIN(C, 5), GPIO_ODR_HIGH)
+GPIO(VCCST_PWRGD_OD,                 PIN(A, 4), GPIO_ODR_LOW)
+GPIO(IMVP9_VRRDY_OD,                 PIN(6, 0), GPIO_INPUT)
+GPIO(CPU_C10_GATE_L,                 PIN(6, 7), GPIO_INPUT)
+
+/* Button */
+GPIO(EC_PCH_PWR_BTN_ODL,             PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(GSC_EC_RECOVERY_BTN_OD,         PIN(2, 2), GPIO_INPUT)
+
+/* HDMI CEC */
+/* TODO(b/197474873): Enable HDMI CEC */
+GPIO(HDMIA_CEC_IN,                   PIN(D, 3), GPIO_INPUT)
+GPIO(HDMIA_CEC_OUT,                  PIN(1, 0), GPIO_OUT_HIGH | GPIO_OPEN_DRAIN)
+GPIO(HDMIA_CEC_PULL_UP,              PIN(1, 1), GPIO_OUT_HIGH)
+GPIO(HDMIB_CEC_IN,                   PIN(4, 0), GPIO_INPUT)
+GPIO(HDMIB_CEC_OUT,                  PIN(2, 7), GPIO_OUT_HIGH | GPIO_OPEN_DRAIN)
+GPIO(HDMIB_CEC_PULL_UP,              PIN(C, 2), GPIO_OUT_HIGH)
+
+/* I2C SCL/SDA */
+GPIO(EC_I2C_LTC_SCL,                 PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_LTC_SDA,                 PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SCL_R,              PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SDA_R,              PIN(B, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_TCPC_SCL,         PIN(B, 5), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_TCPC_SDA,         PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_PPC_SCL,       PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_PPC_SDA,       PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_RT_SCL,        PIN(D, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_RT_SDA,        PIN(D, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_TCPC_SCL,      PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_TCPC_SDA,      PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_ADB_SCL,                 PIN(E, 4), GPIO_INPUT)
+GPIO(EC_I2C_ADB_SDA,                 PIN(E, 3), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_PPC_SCL,          PIN(F, 3), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_PPC_SDA,          PIN(F, 2), GPIO_INPUT)
+
+/* USBA */
+GPIO(EN_PP5000_USBA,                 PIN(D, 7), GPIO_OUT_LOW)
+GPIO(USB_A0_STATUS_L,                PIN(2, 1), GPIO_INPUT)
+GPIO(USB_A1_STATUS_L,                PIN(2, 0), GPIO_INPUT)
+GPIO(USB_A_LOW_PWR0_OD,              PIN(1, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(USB_A_LOW_PWR1_OD,              PIN(1, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(USB_A_OC_SOC_L,                 PIN(8, 0), GPIO_OUT_HIGH)
+
+/* LED */
+/* TODO(b/197471359): LED implementation */
+GPIO(LED_WHITE_L,                    PIN(C, 3), GPIO_OUT_LOW)
+GPIO(LED_RED_L,                      PIN(C, 4), GPIO_OUT_LOW)
+
+/* USBC */
+GPIO(USB_C0_C2_TCPC_RST_ODL,         PIN(A, 7), GPIO_ODR_LOW)
+GPIO(USB_C1_FRS_EN,                  PIN(9, 4), GPIO_OUT_LOW)
+
+/* GPIO02_P2 to PU */
+/* GPIO03_P2 to PU */
+IOEX(USB_C0_OC_ODL,          EXPIN(IOEX_C0_NCT38XX, 0, 4), GPIO_ODR_HIGH)
+IOEX(USB_C0_FRS_EN,          EXPIN(IOEX_C0_NCT38XX, 0, 6), GPIO_LOW)
+IOEX(USB_C0_RT_RST_ODL,      EXPIN(IOEX_C0_NCT38XX, 0, 7), GPIO_ODR_LOW)
+
+IOEX(USB_C2_RT_RST_ODL,      EXPIN(IOEX_C2_NCT38XX, 0, 2), GPIO_ODR_LOW)
+IOEX(USB_C1_OC_ODL,          EXPIN(IOEX_C2_NCT38XX, 0, 3), GPIO_ODR_HIGH)
+IOEX(USB_C2_OC_ODL,          EXPIN(IOEX_C2_NCT38XX, 0, 4), GPIO_ODR_HIGH)
+IOEX(USB_C2_FRS_EN,          EXPIN(IOEX_C2_NCT38XX, 0, 6), GPIO_LOW)
+/* GPIO07_P2 to PU */
+
+/* UART alternate functions */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)              /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */
+
+/* I2C alternate functions */
+ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)               /* GPIO33/I2C5_SCL0/CTS_L, GPIO36/RTS_L/I2C5_SDA0 */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)               /* GPIO87/I2C1_SDA0 */
+ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)               /* GPIO92/I2C2_SCL0, GPIO91/I2C2_SDA0, GPIO90/I2C1_SCL0 */
+ALTERNATE(PIN_MASK(B, 0x0c), 0, MODULE_I2C, 0)               /* GPIOB3/I2C7_SCL0/DCD_L, GPIOB2/I2C7_SDA0/DSR_L */
+ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, 0)               /* GPIOB5/I2C0_SCL0, GPIOB4/I2C0_SDA0 */
+ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)               /* GPIOD1/I2C3_SCL0, GPIOD0/I2C3_SDA0 */
+ALTERNATE(PIN_MASK(E, 0x18), 0, MODULE_I2C, 0)               /* GPIOE4/I2C6_SCL1/I3C_SCL, GPIOE3/I2C6_SDA1/I3C_SDA */
+ALTERNATE(PIN_MASK(F, 0x0c), 0, MODULE_I2C, 0)               /* GPIOF3/I2C4_SCL1, GPIOF2/I2C4_SDA1 */
+
+/* PWM alternate functions */
+ALTERNATE(PIN_MASK(7, 0x08), 0, MODULE_PWM, 0)               /* GPIO73/TA2 */
+ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)               /* GPIOB7/PWM5 */
+ALTERNATE(PIN_MASK(C, 0x18), 0, MODULE_PWM, 0)               /* GPIOC4/PWM2, GPIOC3/PWM0 */
+
+/* ADC alternate functions */
+ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0)               /* GPIO34/PS2_DAT2/ADC6 */
+ALTERNATE(PIN_MASK(4, 0x38), 0, MODULE_ADC, 0)               /* GPIO45/ADC0, GPIO44/ADC1, GPIO43/ADC2 */
+ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0)               /* GPIOE1/ADC7 */
+
+/* Unused Pins */
+UNUSED(PIN(D, 4))       /* GPIOD4/CRSIN3 */
+UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
+UNUSED(PIN(3, 2))       /* GPO32/TRIS_L */
+UNUSED(PIN(3, 5))       /* GPO35/CR_SOUT4/TEST_L */
+UNUSED(PIN(6, 6))       /* GPIO66 */
+UNUSED(PIN(8, 1))       /* GPIO81/PECI_DATA */
+UNUSED(PIN(5, 6))       /* GPIO56/CLKRUN# */
+UNUSED(PIN(8, 6))       /* GPIO86/TXD/CR_SOUT2 */
+UNUSED(PIN(1, 7))       /* KSO2/GPIO17/JTAG_TDI */
+UNUSED(PIN(1, 6))       /* KSO03/GPIO16/JTAG_TDO_SWO */
+UNUSED(PIN(1, 3))       /* KSO06/GPO13/GP_SEL# */
+UNUSED(PIN(1, 2))       /* KSO07/GPO12/JEN# */
+UNUSED(PIN(0, 7))       /* KSO10/GPIO07/P80_CLK */
+UNUSED(PIN(0, 6))       /* KSO11/GPIO06/P80_DAT */
+UNUSED(PIN(0, 5))       /* KSO12/GPIO05 */
+UNUSED(PIN(A, 3))       /* SPIP_MOSI/GPIOA3 */
+UNUSED(PIN(9, 5))       /* SPIP_MISO/GPIO95 */
+UNUSED(PIN(D, 2))       /* PSL_IN1/GPIOD2 */
+UNUSED(PIN(0, 2))       /* GPIO02/PSL_IN4 */
\ No newline at end of file
diff --git a/board/constitution/i2c.c b/board/constitution/i2c.c
new file mode 100644
index 0000000000..f9ff3524a1
--- /dev/null
+++ b/board/constitution/i2c.c
@@ -0,0 +1,77 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "i2c.h"
+
+/* I2C port map configuration */
+const struct i2c_port_t i2c_ports[] = {
+	{
+		/* I2C0 C1 TCPC */
+		.name = "tcpc1",
+		.port = I2C_PORT_USB_C1_TCPC,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_USB_C1_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C1_TCPC_SDA,
+	},
+	{
+		/* I2C1 */
+		.name = "tcpc0,2",
+		.port = I2C_PORT_USB_C0_C2_TCPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C2_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C2_TCPC_SDA,
+	},
+	{
+		/* I2C2 */
+		.name = "ppc0,2",
+		.port = I2C_PORT_USB_C0_C2_PPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C2_PPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C2_PPC_SDA,
+	},
+	{
+		/* I2C3 */
+		.name = "retimer0,2",
+		.port = I2C_PORT_USB_C0_C2_MUX,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C2_RT_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C2_RT_SDA,
+	},
+	{
+		/* I2C4 */
+		.name = "ppc1",
+		.port = I2C_PORT_USB_C1_PPC,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_USB_C1_PPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C1_PPC_SDA,
+	},
+	{
+		/* I2C5 */
+		.name = "pse",
+		.port = I2C_PORT_PSE,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_LTC_SCL,
+		.sda = GPIO_EC_I2C_LTC_SDA,
+	},
+	{
+		/* I2C6 */
+		.name = "ADB",
+		.port = I2C_PORT_ADB,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_ADB_SCL,
+		.sda = GPIO_EC_I2C_ADB_SDA,
+	},
+	{
+		/* I2C7 */
+		.name = "eeprom",
+		.port = I2C_PORT_EEPROM,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_MISC_SCL_R,
+		.sda = GPIO_EC_I2C_MISC_SDA_R,
+	},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/board/constitution/led.c b/board/constitution/led.c
new file mode 100644
index 0000000000..2d8c167a13
--- /dev/null
+++ b/board/constitution/led.c
@@ -0,0 +1,260 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power LED control for Brask.
+ * Solid white - active power
+ * White flashing - suspended
+ * Red flashing - alert
+ * Solid red - critical
+ */
+
+#include "chipset.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "led_common.h"
+#include "pwm.h"
+#include "timer.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
+
+/*
+ * Due to the CSME-Lite processing, upon startup the CPU transitions through
+ * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so
+ * delay turning off the LED during suspend/shutdown.
+ */
+#define LED_CPU_DELAY_MS (2000 * MSEC)
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED };
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+enum led_color {
+	LED_OFF = 0,
+	LED_RED,
+	LED_WHITE,
+
+	/* Number of colors, not a color itself */
+	LED_COLOR_COUNT
+};
+
+static int set_color_power(enum led_color color, int duty)
+{
+	int white = 0;
+	int red = 0;
+
+	if (duty < 0 || 100 < duty)
+		return EC_ERROR_UNKNOWN;
+
+	switch (color) {
+	case LED_OFF:
+		break;
+	case LED_WHITE:
+		white = 1;
+		break;
+	case LED_RED:
+		red = 1;
+		break;
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+
+	if (red)
+		pwm_set_duty(PWM_CH_LED_RED, duty);
+	else
+		pwm_set_duty(PWM_CH_LED_RED, 0);
+
+	if (white)
+		pwm_set_duty(PWM_CH_LED_WHITE, duty);
+	else
+		pwm_set_duty(PWM_CH_LED_WHITE, 0);
+
+	return EC_SUCCESS;
+}
+
+static int set_color(enum ec_led_id id, enum led_color color, int duty)
+{
+	switch (id) {
+	case EC_LED_ID_POWER_LED:
+		return set_color_power(color, duty);
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+}
+
+#define LED_PULSE_US (2 * SECOND)
+/* 40 msec for nice and smooth transition. */
+#define LED_PULSE_TICK_US (40 * MSEC)
+
+/*
+ * When pulsing is enabled, brightness is incremented by <duty_inc> every
+ * <interval> usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented
+ * likewise in LED_PULSE_US usec.
+ */
+static struct {
+	uint32_t interval;
+	int duty_inc;
+	enum led_color color;
+	int duty;
+} led_pulse;
+
+#define CONFIG_TICK(interval, color) \
+	config_tick((interval), 100 / (LED_PULSE_US / (interval)), (color))
+
+static void config_tick(uint32_t interval, int duty_inc, enum led_color color)
+{
+	led_pulse.interval = interval;
+	led_pulse.duty_inc = duty_inc;
+	led_pulse.color = color;
+	led_pulse.duty = 0;
+}
+
+static void pulse_power_led(enum led_color color)
+{
+	set_color(EC_LED_ID_POWER_LED, color, led_pulse.duty);
+	if (led_pulse.duty + led_pulse.duty_inc > 100)
+		led_pulse.duty_inc = led_pulse.duty_inc * -1;
+	else if (led_pulse.duty + led_pulse.duty_inc < 0)
+		led_pulse.duty_inc = led_pulse.duty_inc * -1;
+	led_pulse.duty += led_pulse.duty_inc;
+}
+
+static void led_tick(void);
+DECLARE_DEFERRED(led_tick);
+static void led_tick(void)
+{
+	uint32_t elapsed;
+	uint32_t next = 0;
+	uint32_t start = get_time().le.lo;
+
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		pulse_power_led(led_pulse.color);
+	elapsed = get_time().le.lo - start;
+	next = led_pulse.interval > elapsed ? led_pulse.interval - elapsed : 0;
+	hook_call_deferred(&led_tick_data, next);
+}
+
+static void led_suspend(void)
+{
+	CONFIG_TICK(LED_PULSE_TICK_US, LED_WHITE);
+	led_tick();
+}
+DECLARE_DEFERRED(led_suspend);
+
+static void led_shutdown(void)
+{
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_OFF, 0);
+}
+DECLARE_DEFERRED(led_shutdown);
+
+static void led_shutdown_hook(void)
+{
+	hook_call_deferred(&led_tick_data, -1);
+	hook_call_deferred(&led_suspend_data, -1);
+	hook_call_deferred(&led_shutdown_data, LED_CPU_DELAY_MS);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, led_shutdown_hook, HOOK_PRIO_DEFAULT);
+
+static void led_suspend_hook(void)
+{
+	hook_call_deferred(&led_shutdown_data, -1);
+	hook_call_deferred(&led_suspend_data, LED_CPU_DELAY_MS);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, led_suspend_hook, HOOK_PRIO_DEFAULT);
+
+static void led_resume(void)
+{
+	/*
+	 * Assume there is no race condition with led_tick, which also
+	 * runs in hook_task.
+	 */
+	hook_call_deferred(&led_tick_data, -1);
+	/*
+	 * Avoid invoking the suspend/shutdown delayed hooks.
+	 */
+	hook_call_deferred(&led_suspend_data, -1);
+	hook_call_deferred(&led_shutdown_data, -1);
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_WHITE, 100);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, led_resume, HOOK_PRIO_DEFAULT);
+
+void led_alert(int enable)
+{
+	if (enable) {
+		/* Overwrite the current signal */
+		config_tick(1 * SECOND, 100, LED_RED);
+		led_tick();
+	} else {
+		/* Restore the previous signal */
+		if (chipset_in_state(CHIPSET_STATE_ON))
+			led_resume();
+		else if (chipset_in_state(CHIPSET_STATE_SUSPEND))
+			led_suspend_hook();
+		else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+			led_shutdown_hook();
+	}
+}
+
+void show_critical_error(void)
+{
+	hook_call_deferred(&led_tick_data, -1);
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_RED, 100);
+}
+
+static int command_led(int argc, const char **argv)
+{
+	enum ec_led_id id = EC_LED_ID_POWER_LED;
+
+	if (argc < 2)
+		return EC_ERROR_PARAM_COUNT;
+
+	if (!strcasecmp(argv[1], "debug")) {
+		led_auto_control(id, !led_auto_control_is_enabled(id));
+		ccprintf("o%s\n", led_auto_control_is_enabled(id) ? "ff" : "n");
+	} else if (!strcasecmp(argv[1], "off")) {
+		set_color(id, LED_OFF, 0);
+	} else if (!strcasecmp(argv[1], "red")) {
+		set_color(id, LED_RED, 100);
+	} else if (!strcasecmp(argv[1], "white")) {
+		set_color(id, LED_WHITE, 100);
+	} else if (!strcasecmp(argv[1], "alert")) {
+		led_alert(1);
+	} else if (!strcasecmp(argv[1], "crit")) {
+		show_critical_error();
+	} else {
+		return EC_ERROR_PARAM1;
+	}
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(led, command_led, "[debug|red|white|off|alert|crit]",
+			"Turn on/off LED.");
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	brightness_range[EC_LED_COLOR_RED] = 100;
+	brightness_range[EC_LED_COLOR_WHITE] = 100;
+}
+
+int led_set_brightness(enum ec_led_id id, const uint8_t *brightness)
+{
+	if (brightness[EC_LED_COLOR_RED])
+		return set_color(id, LED_RED, brightness[EC_LED_COLOR_RED]);
+	else if (brightness[EC_LED_COLOR_WHITE])
+		return set_color(id, LED_WHITE, brightness[EC_LED_COLOR_WHITE]);
+	else
+		return set_color(id, LED_OFF, 0);
+}
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
+{
+	/* Blink alert if insufficient power per system_can_boot_ap(). */
+	int insufficient_power =
+		(charge_ma * charge_mv) <
+		(CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON * 1000);
+	led_alert(insufficient_power);
+}
diff --git a/board/constitution/pwm.c b/board/constitution/pwm.c
new file mode 100644
index 0000000000..6558587bf9
--- /dev/null
+++ b/board/constitution/pwm.c
@@ -0,0 +1,38 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "hooks.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_LED_WHITE] = { .channel = 0,
+			       .flags = PWM_CONFIG_DSLEEP,
+			       .freq = 2000 },
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
+	[PWM_CH_LED_RED] = { .channel = 2,
+			     .flags = PWM_CONFIG_DSLEEP,
+			     .freq = 2000 },
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+static void board_pwm_init(void)
+{
+	/*
+	 * TODO(b/197478860): Turn on the fan at 100% by default
+	 * We need to find tune the fan speed according to the
+	 * thermal sensor value.
+	 */
+	pwm_enable(PWM_CH_FAN, 1);
+	pwm_set_duty(PWM_CH_FAN, 100);
+
+	pwm_enable(PWM_CH_LED_RED, 1);
+	pwm_enable(PWM_CH_LED_WHITE, 1);
+}
+DECLARE_HOOK(HOOK_INIT, board_pwm_init, HOOK_PRIO_DEFAULT);
diff --git a/board/constitution/sensors.c b/board/constitution/sensors.c
new file mode 100644
index 0000000000..211faace1c
--- /dev/null
+++ b/board/constitution/sensors.c
@@ -0,0 +1,114 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc_chip.h"
+#include "common.h"
+#include "hooks.h"
+#include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
+#include "thermal.h"
+
+/* ADC configuration */
+const struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_1_CPU] = {
+		.name = "TEMP_CPU",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_2_CPU_VR] = {
+		.name = "TEMP_CPU_VR",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_3_WIFI] = {
+		.name = "TEMP_WIFI",
+		.input_ch = NPCX_ADC_CH6,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_4_DIMM] = {
+		.name = "TEMP_DIMM",
+		.input_ch = NPCX_ADC_CH7,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_VBUS] = {  /* 5/39 voltage divider */
+		.name = "VBUS",
+		.input_ch = NPCX_ADC_CH2,
+		.factor_mul = ADC_MAX_VOLT * 39,
+		.factor_div = (ADC_READ_MAX + 1) * 5,
+	},
+	[ADC_PPVAR_IMON] = {  /* 872.3 mV/A */
+		.name = "PPVAR_IMON",
+		.input_ch = NPCX_ADC_CH3,
+		.factor_mul = ADC_MAX_VOLT * 1433,
+		.factor_div = (ADC_READ_MAX + 1) * 1250,
+	},
+
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* Temperature sensor configuration */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1_CPU] = { .name = "CPU",
+				.type = TEMP_SENSOR_TYPE_BOARD,
+				.read = get_temp_3v3_30k9_47k_4050b,
+				.idx = ADC_TEMP_SENSOR_1_CPU },
+	[TEMP_SENSOR_2_CPU_VR] = { .name = "CPU VR",
+				   .type = TEMP_SENSOR_TYPE_BOARD,
+				   .read = get_temp_3v3_30k9_47k_4050b,
+				   .idx = ADC_TEMP_SENSOR_2_CPU_VR },
+	[TEMP_SENSOR_3_WIFI] = { .name = "WIFI",
+				 .type = TEMP_SENSOR_TYPE_BOARD,
+				 .read = get_temp_3v3_30k9_47k_4050b,
+				 .idx = ADC_TEMP_SENSOR_3_WIFI },
+	[TEMP_SENSOR_4_DIMM] = { .name = "DIMM",
+				 .type = TEMP_SENSOR_TYPE_BOARD,
+				 .read = get_temp_3v3_30k9_47k_4050b,
+				 .idx = ADC_TEMP_SENSOR_4_DIMM },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/*
+ * TODO(b/180681346): update for Alder Lake/brya
+ *
+ * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
+ * 130 C.  However, sensor is located next to DDR, so we need to use the lower
+ * DDR temperature limit (85 C)
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+		}, \
+		.temp_fan_off = C_TO_K(35), \
+		.temp_fan_max = C_TO_K(50), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
+
+/*
+ * TODO(b/197478860): add the thermal sensor setting
+ */
+/* this should really be "const" */
+struct ec_thermal_config thermal_params[] = {
+	[TEMP_SENSOR_1_CPU] = THERMAL_CPU,
+	[TEMP_SENSOR_2_CPU_VR] = THERMAL_CPU,
+	[TEMP_SENSOR_3_WIFI] = THERMAL_CPU,
+	[TEMP_SENSOR_4_DIMM] = THERMAL_CPU,
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
diff --git a/board/constitution/usbc_config.c b/board/constitution/usbc_config.c
new file mode 100644
index 0000000000..cc96a898b1
--- /dev/null
+++ b/board/constitution/usbc_config.c
@@ -0,0 +1,375 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/bc12/pi3usb9201_public.h"
+#include "driver/ppc/syv682x_public.h"
+#include "driver/retimer/bb_retimer_public.h"
+#include "driver/tcpm/nct38xx.h"
+#include "driver/tcpm/rt1715.h"
+#include "driver/tcpm/tcpci.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "ioexpander.h"
+#include "system.h"
+#include "task.h"
+#include "task_id.h"
+#include "timer.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+/* USBC TCPC configuration */
+const struct tcpc_config_t tcpc_config[] = {
+	[USBC_PORT_C0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0_C2_TCPC,
+			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_NO_DEBUG_ACC_CONTROL,
+	},
+	[USBC_PORT_C1] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C1_TCPC,
+			.addr_flags = RT1715_I2C_ADDR_FLAGS,
+		},
+		.drv = &rt1715_tcpm_drv,
+	},
+	[USBC_PORT_C2] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0_C2_TCPC,
+			.addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
+BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
+
+/* USBC PPC configuration */
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_C2_PPC,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.drv = &syv682x_drv,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C1_PPC,
+		.i2c_addr_flags = SYV682X_ADDR1_FLAGS,
+		.drv = &syv682x_drv,
+	},
+	[USBC_PORT_C2] = {
+		.i2c_port = I2C_PORT_USB_C0_C2_PPC,
+		.i2c_addr_flags = SYV682X_ADDR2_FLAGS,
+		.drv = &syv682x_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
+
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/* USBC mux configuration - Alder Lake includes internal mux */
+static const struct usb_mux_chain usbc0_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+
+const struct usb_mux_chain usb_muxes[] = {
+	[USBC_PORT_C0] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C0_C2_MUX,
+			.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc0_tcss_usb_mux,
+	},
+	[USBC_PORT_C1] = {
+		.mux = &(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+	},
+	[USBC_PORT_C2] = {
+		.mux = &(const struct usb_mux){
+			.usb_port = USBC_PORT_C2,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
+
+/* BC1.2 charger detect configuration */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_C2_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C1_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_2_FLAGS,
+	},
+	[USBC_PORT_C2] = {
+		.i2c_port = I2C_PORT_USB_C0_C2_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_1_FLAGS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
+
+/*
+ * USB C0 and C2 uses burnside bridge chips and have their reset
+ * controlled by their respective TCPC chips acting as GPIO expanders.
+ *
+ * ioex_init() is normally called before we take the TCPCs out of
+ * reset, so we need to start in disabled mode, then explicitly
+ * call ioex_init().
+ */
+
+struct ioexpander_config_t ioex_config[] = {
+	[IOEX_C0_NCT38XX] = {
+		.i2c_host_port = I2C_PORT_USB_C0_C2_TCPC,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
+	},
+	[IOEX_C2_NCT38XX] = {
+		.i2c_host_port = I2C_PORT_USB_C0_C2_TCPC,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT);
+
+__override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
+{
+	enum ioex_signal rst_signal;
+
+	if (me->usb_port == USBC_PORT_C0) {
+		rst_signal = IOEX_USB_C0_RT_RST_ODL;
+	} else if (me->usb_port == USBC_PORT_C2) {
+		rst_signal = IOEX_USB_C2_RT_RST_ODL;
+	} else {
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * We do not have a load switch for the burnside bridge chips,
+	 * so we only need to sequence reset.
+	 */
+
+	if (enable) {
+		/*
+		 * Tpw, minimum time from VCC to RESET_N de-assertion is 100us.
+		 * For boards that don't provide a load switch control, the
+		 * retimer_init() function ensures power is up before calling
+		 * this function.
+		 */
+		ioex_set_level(rst_signal, 1);
+		/*
+		 * Allow 1ms time for the retimer to power up lc_domain
+		 * which powers I2C controller within retimer
+		 */
+		msleep(1);
+	} else {
+		ioex_set_level(rst_signal, 0);
+		msleep(1);
+	}
+	return EC_SUCCESS;
+}
+
+__override int bb_retimer_reset(const struct usb_mux *me)
+{
+	/*
+	 * TODO(b/193402306, b/195375738): Remove this once transition to
+	 * QS Silicon is complete
+	 */
+	bb_retimer_power_enable(me, false);
+	msleep(5);
+	bb_retimer_power_enable(me, true);
+	msleep(25);
+
+	return EC_SUCCESS;
+}
+
+void board_reset_pd_mcu(void)
+{
+	enum gpio_signal tcpc_rst;
+
+	tcpc_rst = GPIO_USB_C0_C2_TCPC_RST_ODL;
+
+	/*
+	 * TODO(b/179648104): figure out correct timing
+	 */
+
+	gpio_set_level(tcpc_rst, 0);
+
+	/*
+	 * delay for power-on to reset-off and min. assertion time
+	 */
+
+	msleep(20);
+
+	gpio_set_level(tcpc_rst, 1);
+
+	/* wait for chips to come up */
+
+	msleep(50);
+}
+
+static void enable_ioex(int ioex)
+{
+	ioex_init(ioex);
+}
+
+static void board_tcpc_init(void)
+{
+	/* Don't reset TCPCs after initial reset */
+	if (!system_jumped_late()) {
+		board_reset_pd_mcu();
+
+		/*
+		 * These IO expander pins are implemented using the
+		 * C0/C2 TCPC, so they must be set up after the TCPC has
+		 * been taken out of reset.
+		 */
+		enable_ioex(IOEX_C0_NCT38XX);
+		enable_ioex(IOEX_C2_NCT38XX);
+	}
+
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C2_PPC_INT_ODL);
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_C2_TCPC_INT_ODL);
+
+	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (gpio_get_level(GPIO_USB_C0_C2_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_0 | PD_STATUS_TCPC_ALERT_2;
+
+	if (gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
+
+int ppc_get_alert_status(int port)
+{
+	if (port == USBC_PORT_C0)
+		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
+	else if (port == USBC_PORT_C1)
+		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
+	else if (port == USBC_PORT_C2)
+		return gpio_get_level(GPIO_USB_C2_PPC_INT_ODL) == 0;
+	return 0;
+}
+
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_C2_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C1);
+		break;
+	default:
+		break;
+	}
+}
+
+void bc12_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_BC12_INT_ODL:
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+		break;
+	case GPIO_USB_C1_BC12_INT_ODL:
+		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+		break;
+	case GPIO_USB_C2_BC12_INT_ODL:
+		usb_charger_task_set_event(2, USB_CHG_EVENT_BC12);
+		break;
+	default:
+		break;
+	}
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C1);
+		break;
+	case GPIO_USB_C2_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C2);
+		break;
+	default:
+		break;
+	}
+}
+
+void retimer_interrupt(enum gpio_signal signal)
+{
+	/*
+	 * TODO(b/179513527): add USB-C support
+	 */
+}
+
+__override bool board_is_dts_port(int port)
+{
+	return port == USBC_PORT_C0;
+}
+
+__override bool board_is_tbt_usb4_port(int port)
+{
+	return true;
+}
+
+__override enum tbt_compat_cable_speed board_get_max_tbt_speed(int port)
+{
+	if (!board_is_tbt_usb4_port(port))
+		return TBT_SS_RES_0;
+
+	return TBT_SS_TBT_GEN3;
+}
diff --git a/board/constitution/usbc_config.h b/board/constitution/usbc_config.h
new file mode 100644
index 0000000000..778ca51a0d
--- /dev/null
+++ b/board/constitution/usbc_config.h
@@ -0,0 +1,20 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Brya board-specific USB-C configuration */
+
+#ifndef __CROS_EC_USBC_CONFIG_H
+#define __CROS_EC_USBC_CONFIG_H
+
+#define CONFIG_USB_PD_PORT_MAX_COUNT 3
+
+enum usbc_port {
+	USBC_PORT_C0 = 0,
+	USBC_PORT_C1,
+	USBC_PORT_C2,
+	USBC_PORT_COUNT
+};
+
+#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/constitution/vif_override.xml b/board/constitution/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/constitution/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/copano/battery.c b/board/copano/battery.c
new file mode 100644
index 0000000000..85f3d67448
--- /dev/null
+++ b/board/copano/battery.c
@@ -0,0 +1,66 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "common.h"
+#include "util.h"
+
+/*
+ * Battery info for all Volteer battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	[BATTERY_C433] = {
+		.fuel_gauge = {
+			.manuf_name = "AS1GVPc3KB",
+			.device_name = "C433-41",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x10, 0x10 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x44,
+				.reg_mask = 0x6000,
+				.disconnect_val = 0x6000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13200,
+			.voltage_normal		= 11550, /* mV */
+			.voltage_min		= 9000, /* mV */
+			.precharge_current	= 256,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 45,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 60,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_C433;
diff --git a/board/copano/board.c b/board/copano/board.c
new file mode 100644
index 0000000000..7608b8cee7
--- /dev/null
+++ b/board/copano/board.c
@@ -0,0 +1,448 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Volteer board-specific configuration */
+#include "accelgyro.h"
+#include "button.h"
+#include "cbi_ec_fw_config.h"
+#include "common.h"
+#include "driver/accel_bma2x2.h"
+#include "driver/accelgyro_bmi160.h"
+#include "driver/bc12/pi3usb9201.h"
+#include "driver/ppc/syv682x.h"
+#include "driver/retimer/bb_retimer_public.h"
+#include "driver/sync.h"
+#include "driver/tcpm/rt1715.h"
+#include "driver/tcpm/tcpci.h"
+#include "extpower.h"
+#include "fan.h"
+#include "fan_chip.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "switch.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "throttle_ap.h"
+#include "uart.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tbt.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/* Increase from 50 us, because KSO_02 passes through the H1. */
+	.output_settle_us = 80,
+	/* Other values should be the same as the default configuration. */
+	.debounce_down_us = 9 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x1c, 0xfe, 0xff, 0xff, 0xff, 0xf5, 0xff,
+		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
+	},
+};
+
+static const struct ec_response_keybd_config copano_kb = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &copano_kb;
+}
+
+/******************************************************************************/
+/*
+ * FW_CONFIG defaults for Terrador if the CBI data is not initialized.
+ */
+union volteer_cbi_fw_config fw_config_defaults = {
+	.usb_db = DB_USB3_PASSIVE,
+};
+
+static void board_init(void)
+{
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+/******************************************************************************/
+/* I2C port map configuration */
+const struct i2c_port_t i2c_ports[] = {
+	{
+		.name = "sensor",
+		.port = I2C_PORT_SENSOR,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C0_SENSOR_SCL,
+		.sda = GPIO_EC_I2C0_SENSOR_SDA,
+	},
+	{
+		.name = "usb_c0",
+		.port = I2C_PORT_USB_C0,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C1_USB_C0_SCL,
+		.sda = GPIO_EC_I2C1_USB_C0_SDA,
+	},
+	{
+		.name = "usb_c1",
+		.port = I2C_PORT_USB_C1,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C2_USB_C1_SCL,
+		.sda = GPIO_EC_I2C2_USB_C1_SDA,
+	},
+	{
+		.name = "usb_0_mix",
+		.port = I2C_PORT_USB_0_MIX,
+		.kbps = 100,
+		.scl = GPIO_EC_I2C3_USB_0_MIX_SCL,
+		.sda = GPIO_EC_I2C3_USB_0_MIX_SDA,
+	},
+	{
+		.name = "usb_1_mix",
+		.port = I2C_PORT_USB_1_MIX,
+		.kbps = 100,
+		.scl = GPIO_EC_I2C4_USB_1_MIX_SCL,
+		.sda = GPIO_EC_I2C4_USB_1_MIX_SDA,
+	},
+	{
+		.name = "power",
+		.port = I2C_PORT_POWER,
+		.kbps = 100,
+		.scl = GPIO_EC_I2C5_POWER_SCL,
+		.sda = GPIO_EC_I2C5_POWER_SDA,
+	},
+	{
+		.name = "eeprom",
+		.port = I2C_PORT_EEPROM,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C7_EEPROM_SCL,
+		.sda = GPIO_EC_I2C7_EEPROM_SDA,
+	},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+/******************************************************************************/
+/* PWM configuration */
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_KBLIGHT] = {
+		.channel = 3,
+		.flags = 0,
+		/*
+		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
+		 * flicker. Higher frequencies consume similar average power to
+		 * lower PWM frequencies, but higher frequencies record a much
+		 * lower maximum power.
+		 */
+		.freq = 10000,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+/******************************************************************************/
+/* EC thermal management configuration */
+
+/*
+ * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
+ * 130 C.  However, sensor is located next to DDR, so we need to use the lower
+ * DDR temperature limit (85 C)
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+		}, \
+		.temp_fan_off = C_TO_K(35), \
+		.temp_fan_max = C_TO_K(50), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
+
+/*
+ * Inductor limits - used for both charger and PP3300 regulator
+ *
+ * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
+ *
+ * Charger max recommended temperature 100C, max absolute temperature 125C
+ * PP3300 regulator: operating range -40 C to 145 C
+ *
+ * Inductors: limit of 125c
+ * PCB: limit is 80c
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_INDUCTOR         \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+		}, \
+		.temp_fan_off = C_TO_K(40), \
+		.temp_fan_max = C_TO_K(55), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_inductor =
+	THERMAL_INDUCTOR;
+
+struct ec_thermal_config thermal_params[] = {
+	[TEMP_SENSOR_1_CHARGER] = THERMAL_INDUCTOR,
+	[TEMP_SENSOR_2_PP3300_REGULATOR] = THERMAL_INDUCTOR,
+	[TEMP_SENSOR_3_DDR_SOC] = THERMAL_CPU,
+	[TEMP_SENSOR_4_FAN] = THERMAL_CPU,
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
+
+/******************************************************************************/
+
+static void kb_backlight_enable(void)
+{
+	gpio_set_level(GPIO_EC_KB_BL_EN, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, kb_backlight_enable, HOOK_PRIO_DEFAULT);
+
+static void kb_backlight_disable(void)
+{
+	gpio_set_level(GPIO_EC_KB_BL_EN, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, kb_backlight_disable, HOOK_PRIO_DEFAULT);
+
+void board_reset_pd_mcu(void)
+{
+	/* TODO(b/159025015): Terrador: check USB PD reset operation */
+}
+
+/* USBC mux configuration - Tiger Lake includes internal mux */
+struct usb_mux_chain usbc0_usb4_mb_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_0_MIX,
+			.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
+		},
+};
+/*****************************************************************************
+ * USB-C MUX/Retimer dynamic configuration.
+ */
+static void setup_mux(void)
+{
+	CPRINTS("C0 supports bb-retimer");
+	/* USB-C port 0 have a retimer */
+	usb_muxes[USBC_PORT_C0].next = &usbc0_usb4_mb_retimer;
+}
+
+__override void board_cbi_init(void)
+{
+	/*
+	 * TODO(b/159025015): Terrador: check FW_CONFIG fields for USB DB type
+	 */
+	setup_mux();
+	/* Reassign USB_C0_RT_RST_ODL */
+	bb_controls[USBC_PORT_C0].usb_ls_en_gpio = GPIO_USB_C0_LS_EN;
+	bb_controls[USBC_PORT_C0].retimer_rst_gpio = GPIO_USB_C0_RT_RST_ODL;
+}
+
+/******************************************************************************/
+/* USBC PPC configuration */
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.frs_en = GPIO_USB_C0_FRS_EN,
+		.drv = &syv682x_drv,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C1,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.frs_en = GPIO_USB_C1_FRS_EN,
+		.drv = &syv682x_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/******************************************************************************/
+/* PPC support routines */
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C1);
+		break;
+	default:
+		break;
+	}
+}
+
+/******************************************************************************/
+/* BC1.2 charger detect configuration */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C1,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
+
+/******************************************************************************/
+/* USBC TCPC configuration */
+const struct tcpc_config_t tcpc_config[] = {
+	[USBC_PORT_C0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0,
+			.addr_flags = RT1715_I2C_ADDR_FLAGS,
+		},
+		.drv = &rt1715_tcpm_drv,
+	},
+	[USBC_PORT_C1] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C1,
+			.addr_flags = RT1715_I2C_ADDR_FLAGS,
+		},
+		.drv = &rt1715_tcpm_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
+BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
+
+/******************************************************************************/
+/* USBC mux configuration - Tiger Lake includes internal mux */
+struct usb_mux_chain usbc1_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+struct usb_mux_chain usb_muxes[] = {
+	[USBC_PORT_C0] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+	},
+	[USBC_PORT_C1] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_1_MIX,
+			.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc1_tcss_usb_mux,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
+
+struct bb_usb_control bb_controls[] = {
+	[USBC_PORT_C0] = {
+		/* USB-C port 0 doesn't have a retimer */
+	},
+	[USBC_PORT_C1] = {
+		.usb_ls_en_gpio = GPIO_USB_C1_LS_EN,
+		.retimer_rst_gpio = GPIO_USB_C1_RT_RST_ODL,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(bb_controls) == USBC_PORT_COUNT);
+
+static void board_tcpc_init(void)
+{
+	/* Don't reset TCPCs after initial reset */
+	if (!system_jumped_late())
+		board_reset_pd_mcu();
+
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
+
+	/* Enable BC1.2 interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
+
+/******************************************************************************/
+/* TCPC support routines */
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	/*
+	 * Check which port has the ALERT line set
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL))
+		status |= PD_STATUS_TCPC_ALERT_0;
+	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL))
+		status |= PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
+
+int ppc_get_alert_status(int port)
+{
+	if (port == USBC_PORT_C0)
+		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
+	else
+		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
+}
+
+/******************************************************************************/
+/* USB-A charging control */
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_PP5000_USBA,
+};
diff --git a/board/copano/board.h b/board/copano/board.h
new file mode 100644
index 0000000000..6efd3e88ee
--- /dev/null
+++ b/board/copano/board.h
@@ -0,0 +1,182 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Volteer board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* Baseboard features */
+#include "baseboard.h"
+
+/*
+ * The RAM and flash size combination on the NPCX797FC dose not leave
+ * any unused flash space that can be used to store the .init_rom section.
+ */
+#undef CONFIG_CHIP_INIT_ROM_REGION
+
+#define CONFIG_VBOOT_EFS2
+
+#define CONFIG_POWER_BUTTON
+
+#undef CONFIG_UART_TX_BUF_SIZE
+#define CONFIG_UART_TX_BUF_SIZE 4096
+
+/* Chipset features */
+#define CONFIG_POWER_PP5000_CONTROL
+
+#undef NPCX_PWM1_SEL
+#define NPCX_PWM1_SEL 0 /* GPIO C2 is not used as PWM1 */
+
+/* LED defines */
+#define CONFIG_LED_ONOFF_STATES
+#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
+
+/* Keyboard features */
+#define CONFIG_KEYBOARD_VIVALDI
+#define CONFIG_KEYBOARD_REFRESH_ROW3
+
+/* Sensors */
+/* BMA253 accelerometer in base */
+#define CONFIG_ACCEL_BMA255
+#define CONFIG_ACCEL_KX022
+
+/* BMI160 accel/gyro in base */
+#define CONFIG_ACCELGYRO_BMI160
+#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+#define CONFIG_ACCELGYRO_ICM426XX
+#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+/* Sensors without hardware FIFO are in forced mode */
+#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
+
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_UPDATE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+
+/* USB Type C and USB PD defines */
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+
+/*
+ * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
+ * cables only support up to 60W.
+ */
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 45000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 15000
+
+#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
+
+/* Enabling Thunderbolt-compatible mode */
+#define CONFIG_USB_PD_TBT_COMPAT_MODE
+
+/* Enabling USB4 mode */
+#define CONFIG_USB_PD_USB4
+#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x40
+#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x40
+
+/* USB Type A Features */
+#define USB_PORT_COUNT 1
+#define CONFIG_USB_PORT_POWER_DUMB
+
+/* USBC PPC*/
+#define CONFIG_USBC_PPC_SYV682X /* USBC port C0/C1 */
+#define CONFIG_USB_PD_FRS_PPC
+
+#undef CONFIG_USB_PD_TCPC_RUNTIME_CONFIG
+#undef CONFIG_USB_PD_TCPM_TUSB422
+
+/* BC 1.2 */
+
+/* Volume Button feature */
+
+/* Fan features */
+#undef CONFIG_FANS
+
+/* charger defines */
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_LID_OPEN GPIO_EC_LID_OPEN
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK
+#define GPIO_PG_EC_DSW_PWROK GPIO_DSW_PWROK
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
+
+/* I2C Bus Configuration */
+#define CONFIG_I2C
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_0_MIX NPCX_I2C_PORT3_0
+#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT4_1
+#define I2C_PORT_POWER NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+
+#define I2C_PORT_BATTERY I2C_PORT_POWER
+#define I2C_PORT_CHARGER I2C_PORT_EEPROM
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+#define CONFIG_I2C_CONTROLLER
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum battery_type {
+	BATTERY_C433,
+	BATTERY_TYPE_COUNT,
+};
+
+enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_COUNT };
+
+enum sensor_id {
+	LID_ACCEL = 0,
+	BASE_ACCEL,
+	BASE_GYRO,
+	SENSOR_COUNT,
+};
+
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
+
+void board_reset_pd_mcu(void);
+void motion_interrupt(enum gpio_signal signal);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/copano/build.mk b/board/copano/build.mk
new file mode 100644
index 0000000000..c994631759
--- /dev/null
+++ b/board/copano/build.mk
@@ -0,0 +1,17 @@
+# -*- makefile -*-
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx7
+CHIP_VARIANT:=npcx7m7fc
+BASEBOARD:=volteer
+
+board-y=board.o
+board-y+=battery.o
+board-y+=led.o
+board-y+=sensors.o
diff --git a/board/copano/ec.tasklist b/board/copano/ec.tasklist
new file mode 100644
index 0000000000..c29125d517
--- /dev/null
+++ b/board/copano/ec.tasklist
@@ -0,0 +1,27 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/copano/gpio.inc b/board/copano/gpio.inc
new file mode 100644
index 0000000000..c6271c20f4
--- /dev/null
+++ b/board/copano/gpio.inc
@@ -0,0 +1,176 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+/* Wake Source interrupts */
+GPIO_INT(EC_LID_OPEN,          PIN(9, 5), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
+GPIO_INT(EC_WP_L,              PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(H1_EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
+GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
+
+/* Power sequencing interrupts */
+GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
+#endif
+GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_EC_RSMRST_ODL,     PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(DSW_PWROK,            PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4),  GPIO_INT_BOTH, power_signal_interrupt)
+
+/* Sensor Interrupts */
+GPIO_INT(EC_IMU_INT_L,         PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, motion_interrupt)
+GPIO_INT(TABLET_MODE_L,        PIN(D, 2), GPIO_INT_BOTH, gmr_tablet_switch_isr)
+
+/* USB-C interrupts */
+GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(E, 0), GPIO_INT_BOTH, tcpc_alert_event)
+GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(A, 2), GPIO_INT_BOTH, tcpc_alert_event)
+
+GPIO_INT(USB_C0_PPC_INT_ODL,	PIN(6, 2), GPIO_INT_BOTH, ppc_interrupt)
+GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(F, 5), GPIO_INT_BOTH, ppc_interrupt)
+
+GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(E, 4), GPIO_INT_BOTH, bc12_interrupt)
+GPIO_INT(USB_C1_MIX_INT_ODL,	PIN(0, 3), GPIO_INT_BOTH, bc12_interrupt)
+
+/* HDMI interrupts */
+
+/* Volume button interrupts */
+GPIO_INT(EC_VOLDN_BTN_ODL,		PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(EC_VOLUP_BTN_ODL,		PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+
+/* Power Sequencing Signals */
+GPIO(EN_PP3300_A,              PIN(A, 3), GPIO_OUT_LOW)
+GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
+GPIO(EN_PPVAR_VCCIN,           PIN(4, 3), GPIO_OUT_LOW) /* Enables VCCIN IMPV9 */
+GPIO(EC_PCH_DSW_PWROK,         PIN(C, 0), GPIO_OUT_LOW)
+
+/* Other wake sources */
+/*
+ * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an
+ * interrupt handler because it is automatically handled by the PSL.
+ *
+ * We need to lock the setting so this gpio can't be reconfigured to overdrive
+ * the real reset signal. (This is the PSL input pin not the real reset pin).
+ */
+GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH |
+					   GPIO_HIB_WAKE_HIGH |
+					   GPIO_LOCKED)
+
+/* AP/PCH Signals */
+GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
+GPIO(EC_PCH_RSMRST_ODL,        PIN(A, 6), GPIO_ODR_LOW) /* TODO - b/140950085 - implement TGL sequencing requirement */
+GPIO(EC_PCH_PWR_BTN_ODL,       PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
+GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
+GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
+GPIO_INT(EC_PROCHOT_IN_L,      PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
+GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
+
+GPIO(EC_PCH_INT_ODL,           PIN(B, 0), GPIO_ODR_HIGH)
+
+/* USB and USBC Signals */
+GPIO(EN_PP5000_USBA,		PIN(C, 6), GPIO_OUT_LOW)	/* Enable USB-A charging - all ports */
+GPIO(USB_A_LOW_PWR_OD,		PIN(6, 6), GPIO_ODR_LOW)	/* Don't limit USB-A charging by default - all ports */
+
+/*
+ * USB_C1 moved from GPIO32 to GPIO83 on boards with board ID >=1.
+ * GPIO83/EN_PP1800_A is DNS on board ID 0 and GPIO32 is N/C on board ID >=1
+ * so it's safe to define GPIOs compatible with both designs.
+ * TODO (b/149858568): remove board ID=0 support.
+ */
+GPIO(USB_C0_RT_RST_ODL,			PIN(6, 1), GPIO_ODR_LOW) /* USB_C0 Reset */
+GPIO(USB_C1_RT_RST_ODL,			PIN(8, 3), GPIO_ODR_LOW) /* USB_C1 Reset */
+GPIO(USB_C0_OC_ODL,			PIN(B, 1), GPIO_ODR_HIGH)
+GPIO(USB_C1_OC_ODL,			PIN(5, 0), GPIO_ODR_HIGH)
+/* There is currently no need to service this interrupt. */
+GPIO(USB_C0_RT_INT_ODL,			PIN(B, 7), GPIO_INPUT)
+GPIO(USB_C1_RT_INT_ODL,			PIN(4, 0), GPIO_INPUT)
+GPIO(USB_C0_FRS_EN,			PIN(6, 0), GPIO_OUT_LOW)
+GPIO(USB_C1_FRS_EN,			PIN(9, 4), GPIO_OUT_LOW)
+
+/* Don't have a load switch for retimer */
+UNIMPLEMENTED(USB_C0_LS_EN)
+UNIMPLEMENTED(USB_C1_LS_EN)
+
+/* Misc Signals */
+GPIO(EC_H1_PACKET_MODE,		PIN(7, 5), GPIO_OUT_LOW)	/* H1 Packet Mode */
+GPIO(EC_KB_BL_EN,		PIN(8, 6), GPIO_OUT_LOW)	/* Keyboard backlight enable*/
+GPIO(CCD_MODE_ODL,		PIN(E, 5), GPIO_INPUT)		/* Case Closed Debug Mode */
+GPIO(M2_SSD_PLA,		PIN(7, 0), GPIO_INPUT)		/* SSD power-loss acknowledgment */
+GPIO(M2_SSD_PLN,		PIN(A, 0), GPIO_ODR_HIGH)	/* SSD power-loss notification */
+
+
+/* LED */
+GPIO(LED_2_L,			PIN(C, 3), GPIO_OUT_HIGH)	/* Battery Full LED / Power LED: White */
+GPIO(LED_1_L,			PIN(C, 4), GPIO_OUT_HIGH)	/* Battery Charging LED: Amber */
+
+/*
+ * eDP backlight - both PCH and EC have enable pins that must be high
+ * for the backlight to turn on. Default state is high, and can be turned
+ * off during sleep states.
+ */
+GPIO(EC_EDP_BL_EN,             PIN(D, 3), GPIO_OUT_HIGH)
+
+/* I2C pins - Alternate function below configures I2C module on these pins */
+GPIO(EC_I2C0_SENSOR_SCL,       PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C0_SENSOR_SDA,       PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C1_USB_C0_SCL,       PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C1_USB_C0_SDA,       PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C2_USB_C1_SCL,       PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C2_USB_C1_SDA,       PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C3_USB_0_MIX_SCL,    PIN(D, 1), GPIO_INPUT)
+GPIO(EC_I2C3_USB_0_MIX_SDA,    PIN(D, 0), GPIO_INPUT)
+GPIO(EC_I2C4_USB_1_MIX_SCL,    PIN(F, 3), GPIO_INPUT)
+GPIO(EC_I2C4_USB_1_MIX_SDA,    PIN(F, 2), GPIO_INPUT)
+GPIO(EC_I2C5_POWER_SCL,        PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C5_POWER_SDA,        PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C7_EEPROM_SCL,       PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C7_EEPROM_SDA,       PIN(B, 2), GPIO_INPUT)
+
+/* Battery signals */
+GPIO(EC_BATT_PRES_ODL, 		PIN(E, 1), GPIO_INPUT)
+
+/* Alternate functions GPIO definitions */
+ALTERNATE(PIN_MASK(B, BIT(5) | BIT(4)), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V)) /* I2C0 */
+ALTERNATE(PIN_MASK(9, BIT(0) | BIT(2) | BIT(1)), 0, MODULE_I2C, 0)                   /* I2C1 SCL / I2C2 */
+ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)                                     /* I2C1 SDA */
+ALTERNATE(PIN_MASK(D, BIT(1) | BIT(0)), 0, MODULE_I2C, 0)                            /* I2C3 */
+ALTERNATE(PIN_MASK(F, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)                            /* I2C4 */
+ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)                            /* I2C5 */
+ALTERNATE(PIN_MASK(B, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)                            /* I2C7 */
+
+/* Keyboard pins */
+#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_00-01 */
+ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_02-07 */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_00-01 */
+GPIO(EC_KSO_02_INV, PIN(1, 7),                        GPIO_OUT_LOW)  /* KSO_02 */
+ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_03-09 */
+ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_10-13 */
+ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_14 */
+ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)                     /* EC_KB_BL_PWM */
+
+/* UART */
+ALTERNATE(PIN_MASK(6, BIT(5) | BIT(4)), 0, MODULE_UART, 0)                           /* UART from EC to Servo */
+
+/* Power Switch Logic (PSL) inputs */
+ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)                    /* GPIOD2 = EC_LID_OPEN */
+ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)  /* GPIO00 = ACOK_OD,
+                                                                       GPIO01 = H1_EC_PWR_BTN_ODL
+                                                                       GPIO02 = EC_RST_ODL */
+
+/* Temperature sensors */
+ALTERNATE(PIN_MASK(4, BIT(2) | BIT(4) | BIT(5)), 0, MODULE_ADC, 0) /* TEMP_SENSOR1,2,4 */
+ALTERNATE(PIN_MASK(F, BIT(1)), 0, MODULE_ADC, 0) /* TEMP_SENSOR3 */
+
+/* Unused signals */
+GPIO(UNUSED_GPIOD4,		PIN(D, 4), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIOC2,		PIN(C, 2), GPIO_INPUT | GPIO_PULL_UP)
+
diff --git a/board/copano/led.c b/board/copano/led.c
new file mode 100644
index 0000000000..15daf7b2b9
--- /dev/null
+++ b/board/copano/led.c
@@ -0,0 +1,101 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "chipset.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
+
+__override const int led_charge_lvl_1;
+__override const int led_charge_lvl_2 = 95;
+
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_WHITE,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_BATTERY_LED,
+};
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_WHITE:
+		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_2_L, LED_ON_LVL);
+		break;
+	case EC_LED_COLOR_AMBER:
+		gpio_set_level(GPIO_LED_1_L, LED_ON_LVL);
+		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_battery(EC_LED_COLOR_WHITE);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(EC_LED_COLOR_AMBER);
+		else
+			led_set_color_battery(LED_OFF);
+	}
+
+	return EC_SUCCESS;
+}
+
+__override enum led_states board_led_get_state(enum led_states desired_state)
+{
+	if (desired_state == STATE_BATTERY_ERROR) {
+		if (chipset_in_state(CHIPSET_STATE_ON))
+			return desired_state;
+		else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
+			return STATE_DISCHARGE_S3;
+		else
+			return STATE_DISCHARGE_S5;
+	}
+	return desired_state;
+}
diff --git a/board/copano/sensors.c b/board/copano/sensors.c
new file mode 100644
index 0000000000..5a37f7ab8b
--- /dev/null
+++ b/board/copano/sensors.c
@@ -0,0 +1,226 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Volteer family-specific sensor configuration */
+#include "accelgyro.h"
+#include "cbi_ec_fw_config.h"
+#include "cbi_ssfc.h"
+#include "common.h"
+#include "driver/accel_bma2x2.h"
+#include "driver/accel_kionix.h"
+#include "driver/accelgyro_bmi160.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "driver/accelgyro_icm426xx.h"
+#include "driver/accelgyro_icm_common.h"
+#include "driver/sync.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "keyboard_scan.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "util.h"
+
+/******************************************************************************/
+/* Sensors */
+static struct mutex g_lid_accel_mutex;
+static struct mutex g_base_mutex;
+
+/* sensor private data */
+static struct accelgyro_saved_data_t g_bma253_data;
+static struct kionix_accel_data g_kx022_data;
+
+static struct bmi_drv_data_t g_bmi160_data;
+static struct icm_drv_data_t g_icm426xx_data;
+
+/* Rotation matrix for the lid accelerometer */
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, FLOAT_TO_FP(1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
+
+const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+				       { 0, FLOAT_TO_FP(-1), 0 },
+				       { 0, 0, FLOAT_TO_FP(-1) } };
+
+const mat33_fp_t base_standard_ref_icm = {
+	{ 0, FLOAT_TO_FP(1), 0 },
+	{ FLOAT_TO_FP(1), 0, 0 },
+	{ 0, 0, FLOAT_TO_FP(-1) },
+};
+
+struct motion_sensor_t icm426xx_base_accel = {
+	.name = "Base Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.rot_standard_ref = &base_standard_ref_icm,
+	.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
+	.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
+	.default_range = 4, /* g */
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+		/* Sensor on in S3 */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	},
+};
+
+struct motion_sensor_t icm426xx_base_gyro = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &base_standard_ref_icm,
+	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
+	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
+};
+
+struct motion_sensor_t kx022_lid_accel = {
+	.name = "Lid Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_KX022,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_LID,
+	.drv = &kionix_accel_drv,
+	.mutex = &g_lid_accel_mutex,
+	.drv_data = &g_kx022_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
+	.rot_standard_ref = &lid_standard_ref,
+	.min_frequency = KX022_ACCEL_MIN_FREQ,
+	.max_frequency = KX022_ACCEL_MAX_FREQ,
+	.default_range = 2, /* g, to support tablet mode */
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	},
+};
+
+struct motion_sensor_t motion_sensors[] = {
+	[LID_ACCEL] = {
+		.name = "Lid Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMA255,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &bma2x2_accel_drv,
+		.mutex = &g_lid_accel_mutex,
+		.drv_data = &g_bma253_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
+		.rot_standard_ref = &lid_standard_ref,
+		.min_frequency = BMA255_ACCEL_MIN_FREQ,
+		.max_frequency = BMA255_ACCEL_MAX_FREQ,
+		.default_range = 2, /* g, to support tablet mode */
+		.config = {
+			/* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+			/* Sensor on in S3 */
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+		},
+	},
+	[BASE_ACCEL] = {
+		.name = "Base Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMI160,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &bmi160_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = &g_bmi160_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = BMI_ACCEL_MIN_FREQ,
+		.max_frequency = BMI_ACCEL_MAX_FREQ,
+		.default_range = 4, /* g */
+		.config = {
+			/* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+			/* Sensor on in S3 */
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+		},
+	},
+
+	[BASE_GYRO] = {
+		.name = "Base Gyro",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMI160,
+		.type = MOTIONSENSE_TYPE_GYRO,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &bmi160_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = &g_bmi160_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+		.default_range = 1000, /* dps */
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = BMI_GYRO_MIN_FREQ,
+		.max_frequency = BMI_GYRO_MAX_FREQ,
+	},
+};
+unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	if (get_cbi_ssfc_base_sensor() == SSFC_SENSOR_BASE_ICM426XX)
+		icm426xx_interrupt(signal);
+	else
+		bmi160_interrupt(signal);
+}
+
+static void baseboard_sensors_init(void)
+{
+	if (get_cbi_ssfc_lid_sensor() == SSFC_SENSOR_LID_KX022) {
+		motion_sensors[LID_ACCEL] = kx022_lid_accel;
+		ccprints("LID_ACCEL is KX022");
+	} else
+		ccprints("LID_ACCEL is BMA253");
+
+	if (get_cbi_ssfc_base_sensor() == SSFC_SENSOR_BASE_ICM426XX) {
+		motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
+		motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
+		ccprints("BASE ACCEL is ICM426XX");
+	} else
+		ccprints("BASE ACCEL IS BMI160");
+
+	/* Enable interrupt for the accel/gyro sensor */
+	gpio_enable_interrupt(GPIO_EC_IMU_INT_L);
+}
+DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_DEFAULT);
diff --git a/board/copano/vif_override.xml b/board/copano/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/copano/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/coral/battery.c b/board/coral/battery.c
index ebc8071c0d..3b105c90ca 100644
--- a/board/coral/battery.c
+++ b/board/coral/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,7 +19,7 @@
 #include "i2c.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 /* Number of writes needed to invoke battery cutoff command */
 #define SHIP_MODE_WRITES 2
@@ -412,7 +412,8 @@ BUILD_ASSERT(ARRAY_SIZE(info) == BATTERY_TYPE_COUNT);
 static inline const struct board_batt_params *board_get_batt_params(void)
 {
 	return &info[board_battery_type == BATTERY_TYPE_COUNT ?
-			DEFAULT_BATTERY_TYPE : board_battery_type];
+			     DEFAULT_BATTERY_TYPE :
+			     board_battery_type];
 }
 
 /* Get type of the battery connected on the board */
@@ -424,14 +425,16 @@ static int board_get_battery_type(void)
 	if (!battery_manufacturer_name(manu_name, sizeof(manu_name))) {
 		for (i = 0; i < BATTERY_TYPE_COUNT; i++) {
 			if (!strcasecmp(manu_name,
-				info[i].fuel_gauge.manuf_name)) {
+					info[i].fuel_gauge.manuf_name)) {
 				if (info[i].fuel_gauge.device_name == NULL) {
 					board_battery_type = i;
 					break;
-				} else if (!battery_device_name(device_name,
-					sizeof(device_name))) {
+				} else if (!battery_device_name(
+						   device_name,
+						   sizeof(device_name))) {
 					if (!strcasecmp(device_name,
-					info[i].fuel_gauge.device_name)) {
+							info[i].fuel_gauge
+								.device_name)) {
 						board_battery_type = i;
 						break;
 					}
@@ -496,7 +499,7 @@ static int charger_should_discharge_on_ac(struct charge_state_data *curr)
 
 	/* Do not discharge on AC if the battery is still waking up */
 	if (!(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
-		!(curr->batt.status & STATUS_FULLY_CHARGED))
+	    !(curr->batt.status & STATUS_FULLY_CHARGED))
 		return 0;
 
 	/*
@@ -513,8 +516,8 @@ static int charger_should_discharge_on_ac(struct charge_state_data *curr)
 	 * and suspend USB charging and DC/DC converter.
 	 */
 	if (!battery_is_cut_off() &&
-		!(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
-		(curr->batt.status & STATUS_FULLY_CHARGED))
+	    !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
+	    (curr->batt.status & STATUS_FULLY_CHARGED))
 		return 1;
 
 	/*
@@ -548,13 +551,13 @@ enum battery_present battery_hw_present(void)
 	return gpio_get_level(GPIO_EC_BATT_PRES_L) ? BP_NO : BP_YES;
 }
 
-
 static int battery_init(void)
 {
 	int batt_status;
 
-	return battery_status(&batt_status) ? 0 :
-		!!(batt_status & STATUS_INITIALIZED);
+	return battery_status(&batt_status) ?
+		       0 :
+		       !!(batt_status & STATUS_INITIALIZED);
 }
 
 /* Allow booting now that the battery has woke up */
@@ -595,12 +598,13 @@ static int battery_check_disconnect(void)
 	/* Read the status of charge/discharge FETs */
 	if (info[board_battery_type].fuel_gauge.fet.mfgacc_support == 1) {
 		rv = sb_read_mfgacc(PARAM_OPERATION_STATUS,
-				SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data));
+				    SB_ALT_MANUFACTURER_ACCESS, data,
+				    sizeof(data));
 		/* Get the lowest 16bits of the OperationStatus() data */
 		reg = data[2] | data[3] << 8;
 	} else
 		rv = sb_read(info[board_battery_type].fuel_gauge.fet.reg_addr,
-					&reg);
+			     &reg);
 
 	if (rv)
 		return BATTERY_DISCONNECT_ERROR;
@@ -650,7 +654,7 @@ enum battery_present battery_is_present(void)
 		 * error due to a failed sb_read.
 		 */
 		battery_report_present_timer_started = 0;
-	}  else if (batt_pres == BP_YES && batt_pres_prev == BP_NO &&
+	} else if (batt_pres == BP_YES && batt_pres_prev == BP_NO &&
 		   !battery_report_present_timer_started) {
 		/*
 		 * Wait 1/2 second before reporting present if it was
@@ -674,11 +678,10 @@ int board_battery_initialized(void)
 	return battery_hw_present() == batt_pres_prev;
 }
 
-
 /* Customs options controllable by host command. */
 #define PARAM_FASTCHARGE (CS_PARAM_CUSTOM_PROFILE_MIN + 0)
-#define PARAM_LEARN_MODE	0x10001
-#define PARAM_DISCONNECT_STATE	0x10002
+#define PARAM_LEARN_MODE 0x10001
+#define PARAM_DISCONNECT_STATE 0x10002
 
 enum ec_status charger_profile_override_get_param(uint32_t param,
 						  uint32_t *value)
@@ -686,10 +689,10 @@ enum ec_status charger_profile_override_get_param(uint32_t param,
 	switch (param) {
 	case PARAM_LEARN_MODE:
 		*value = disch_on_ac;
-		return EC_SUCCESS;
+		return EC_RES_SUCCESS;
 	case PARAM_DISCONNECT_STATE:
 		*value = battery_check_disconnect();
-		return EC_SUCCESS;
+		return EC_RES_SUCCESS;
 	default:
 		return EC_RES_INVALID_PARAM;
 	}
diff --git a/board/coral/board.c b/board/coral/board.c
index 829b057d77..2e42bbc0e0 100644
--- a/board/coral/board.c
+++ b/board/coral/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,6 @@
 /* Coral board-specific configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "button.h"
 #include "charge_manager.h"
 #include "charge_ramp.h"
@@ -14,10 +13,10 @@
 #include "charger.h"
 #include "chipset.h"
 #include "console.h"
-#include "driver/als_opt3001.h"
 #include "driver/accel_kionix.h"
 #include "driver/accel_kx022.h"
 #include "driver/accelgyro_bmi_common.h"
+#include "driver/als_opt3001.h"
 #include "driver/charger/bd9995x.h"
 #include "driver/tcpm/anx74xx.h"
 #include "driver/tcpm/ps8xxx.h"
@@ -32,8 +31,9 @@
 #include "lid_angle.h"
 #include "lid_switch.h"
 #include "math_util.h"
-#include "motion_sense.h"
 #include "motion_lid.h"
+#include "motion_sense.h"
+#include "panic.h"
 #include "power.h"
 #include "power_button.h"
 #include "pwm.h"
@@ -45,7 +45,7 @@
 #include "tablet_mode.h"
 #include "task.h"
 #include "temp_sensor.h"
-#include "thermistor.h"
+#include "temp_sensor/thermistor.h"
 #include "timer.h"
 #include "uart.h"
 #include "usb_charge.h"
@@ -54,15 +54,15 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define IN_ALL_SYS_PG	POWER_SIGNAL_MASK(X86_ALL_SYS_PG)
-#define IN_PGOOD_PP3300	POWER_SIGNAL_MASK(X86_PGOOD_PP3300)
-#define IN_PGOOD_PP5000	POWER_SIGNAL_MASK(X86_PGOOD_PP5000)
+#define IN_ALL_SYS_PG POWER_SIGNAL_MASK(X86_ALL_SYS_PG)
+#define IN_PGOOD_PP3300 POWER_SIGNAL_MASK(X86_PGOOD_PP3300)
+#define IN_PGOOD_PP5000 POWER_SIGNAL_MASK(X86_PGOOD_PP5000)
 
-#define USB_PD_PORT_ANX74XX	0
-#define USB_PD_PORT_PS8751	1
+#define USB_PD_PORT_ANX74XX 0
+#define USB_PD_PORT_PS8751 1
 
 static int sku_id;
 
@@ -100,7 +100,7 @@ static void anx74xx_cable_det_handler(void)
 	 * and if in normal mode, then there is no need to trigger a tcpc reset.
 	 */
 	if (cable_det && !reset_n)
-		task_set_event(TASK_ID_PD_C0, PD_EVENT_TCPC_RESET, 0);
+		task_set_event(TASK_ID_PD_C0, PD_EVENT_TCPC_RESET);
 }
 DECLARE_DEFERRED(anx74xx_cable_det_handler);
 
@@ -119,52 +119,62 @@ void anx74xx_cable_det_interrupt(enum gpio_signal signal)
 static void enable_input_devices(void);
 DECLARE_DEFERRED(enable_input_devices);
 
-#define LID_DEBOUNCE_US    (30 * MSEC)  /* Debounce time for lid switch */
 void tablet_mode_interrupt(enum gpio_signal signal)
 {
 	hook_call_deferred(&enable_input_devices_data, LID_DEBOUNCE_US);
 }
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* Vfs = Vref = 2.816V, 10-bit unsigned reading */
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0
-	},
-	[ADC_TEMP_SENSOR_AMB] = {
-		"AMBIENT", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0
-	},
-	[ADC_BOARD_ID] = {
-		"BRD_ID", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0
-	},
-	[ADC_BOARD_SKU_1] = {
-		"BRD_SKU_1", NPCX_ADC_CH3, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0
-	},
-	[ADC_BOARD_SKU_0] = {
-		"BRD_SKU_0", NPCX_ADC_CH4, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0
-	},
+	[ADC_TEMP_SENSOR_CHARGER] = { "CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				      ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_AMB] = { "AMBIENT", NPCX_ADC_CH1, ADC_MAX_VOLT,
+				  ADC_READ_MAX + 1, 0 },
+	[ADC_BOARD_ID] = { "BRD_ID", NPCX_ADC_CH2, ADC_MAX_VOLT,
+			   ADC_READ_MAX + 1, 0 },
+	[ADC_BOARD_SKU_1] = { "BRD_SKU_1", NPCX_ADC_CH3, ADC_MAX_VOLT,
+			      ADC_READ_MAX + 1, 0 },
+	[ADC_BOARD_SKU_0] = { "BRD_SKU_0", NPCX_ADC_CH4, ADC_MAX_VOLT,
+			      ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] =   { 4, PWM_CONFIG_DSLEEP, 100 },
+	[PWM_CH_KBLIGHT] = { 4, PWM_CONFIG_DSLEEP, 100 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
-const struct i2c_port_t i2c_ports[]  = {
-	{"tcpc0",     NPCX_I2C_PORT0_0, 400,
-		GPIO_EC_I2C_USB_C0_PD_SCL, GPIO_EC_I2C_USB_C0_PD_SDA},
-	{"tcpc1",     NPCX_I2C_PORT0_1, 400,
-		GPIO_EC_I2C_USB_C1_PD_SCL, GPIO_EC_I2C_USB_C1_PD_SDA},
-	{"accelgyro", I2C_PORT_GYRO,   400,
-		GPIO_EC_I2C_GYRO_SCL,      GPIO_EC_I2C_GYRO_SDA},
-	{"sensors",   NPCX_I2C_PORT2,   400,
-		GPIO_EC_I2C_SENSOR_SCL,    GPIO_EC_I2C_SENSOR_SDA},
-	{"batt",      NPCX_I2C_PORT3,   100,
-		GPIO_EC_I2C_POWER_SCL,     GPIO_EC_I2C_POWER_SDA},
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "tcpc0",
+	  .port = NPCX_I2C_PORT0_0,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_USB_C0_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C0_PD_SDA },
+	{ .name = "tcpc1",
+	  .port = NPCX_I2C_PORT0_1,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_USB_C1_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C1_PD_SDA },
+	{ .name = "accelgyro",
+	  .port = I2C_PORT_GYRO,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_GYRO_SCL,
+	  .sda = GPIO_EC_I2C_GYRO_SDA },
+	{ .name = "sensors",
+	  .port = NPCX_I2C_PORT2,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_SENSOR_SCL,
+	  .sda = GPIO_EC_I2C_SENSOR_SDA },
+	{ .name = "batt",
+	  .port = NPCX_I2C_PORT3,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_POWER_SCL,
+	  .sda = GPIO_EC_I2C_POWER_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -183,7 +193,7 @@ struct i2c_stress_test i2c_stress_tests[] = {
 #ifdef CONFIG_CMD_I2C_STRESS_TEST_TCPC
 	{
 		.port = NPCX_I2C_PORT0_1,
-		.addr_flags = PS8751_I2C_ADDR1_FLAGS,
+		.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
 		.i2c_test = &ps8xxx_i2c_stress_test_dev,
 	},
 #endif
@@ -234,7 +244,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = NPCX_I2C_PORT0_1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
 		},
 		.drv = &ps8xxx_tcpm_drv,
 	},
@@ -280,17 +290,21 @@ static int ps8751_tune_mux(const struct usb_mux *me)
 	return EC_SUCCESS;
 }
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_ANX74XX] = {
-		.usb_port = USB_PD_PORT_ANX74XX,
-		.driver = &anx74xx_tcpm_usb_mux_driver,
-		.hpd_update = &anx74xx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_ANX74XX,
+			.driver = &anx74xx_tcpm_usb_mux_driver,
+			.hpd_update = &anx74xx_tcpc_update_hpd_status,
+		},
 	},
 	[USB_PD_PORT_PS8751] = {
-		.usb_port = USB_PD_PORT_PS8751,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-		.board_init = &ps8751_tune_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_PS8751,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			.board_init = &ps8751_tune_mux,
+		},
 	}
 };
 
@@ -396,27 +410,28 @@ static void board_tcpc_init(void)
 	gpio_enable_interrupt(GPIO_USB_C0_CABLE_DET);
 #endif
 	/*
-	* Initialize HPD to low; after sysjump SOC needs to see
-	* HPD pulse to enable video path
-	*/
+	 * Initialize HPD to low; after sysjump SOC needs to see
+	 * HPD pulse to enable video path
+	 */
 	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		usb_mux_hpd_update(port, 0, 0);
+		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
 DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_DEFAULT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp,
-				 .idx = 0},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
+	[TEMP_SENSOR_BATTERY] = { .name = "Battery",
+				  .type = TEMP_SENSOR_TYPE_BATTERY,
+				  .read = charge_get_battery_temp,
+				  .idx = 0 },
+	[TEMP_SENSOR_AMBIENT] = { .name = "Ambient",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_51k1_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_AMB },
+	[TEMP_SENSOR_CHARGER] = { .name = "Charger",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_13k7_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_CHARGER },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -456,7 +471,7 @@ static void board_set_tablet_mode(void)
 	if (SKU_IS_CONVERTIBLE(sku_id))
 		tablet_mode = !gpio_get_level(GPIO_TABLET_MODE_L);
 
-	tablet_set_mode(tablet_mode);
+	tablet_set_mode(tablet_mode, TABLET_TRIGGER_LID);
 }
 
 /* Initialize board. */
@@ -540,8 +555,8 @@ int board_set_active_charge_port(int charge_port)
  * @param charge_ma     Desired charge limit (mA).
  * @param charge_mv     Negotiated charge voltage (mV).
  */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
 {
 	/* Enable charging trigger by BC1.2 detection */
 	int bc12_enable = (supplier == CHARGE_SUPPLIER_BC12_CDP ||
@@ -552,9 +567,7 @@ void board_set_charge_limit(int port, int supplier, int charge_ma,
 	if (bd9995x_bc12_enable_charging(port, bc12_enable))
 		return;
 
-	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-				   CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+	charge_set_input_current_limit(charge_ma, charge_mv);
 }
 
 /**
@@ -585,8 +598,7 @@ static void enable_input_devices(void)
 }
 
 /* Enable or disable input devices, based on chipset state and tablet mode */
-#ifndef TEST_BUILD
-void lid_angle_peripheral_enable(int enable)
+__override void lid_angle_peripheral_enable(int enable)
 {
 	/* If the lid is in 360 position, ignore the lid angle,
 	 * which might be faulty. Disable keyboard.
@@ -595,7 +607,6 @@ void lid_angle_peripheral_enable(int enable)
 		enable = 0;
 	keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
 }
-#endif
 
 /* Called on AP S5 -> S3 transition */
 static void board_chipset_startup(void)
@@ -666,17 +677,17 @@ void board_hibernate_late(void)
 	int i;
 	const uint32_t hibernate_pins[][2] = {
 		/* Turn off LEDs in hibernate */
-		{GPIO_BAT_LED_BLUE, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_BAT_LED_AMBER, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_LID_OPEN, GPIO_INT_RISING | GPIO_PULL_DOWN},
+		{ GPIO_BAT_LED_BLUE, GPIO_INPUT | GPIO_PULL_UP },
+		{ GPIO_BAT_LED_AMBER, GPIO_INPUT | GPIO_PULL_UP },
+		{ GPIO_LID_OPEN, GPIO_INT_RISING | GPIO_PULL_DOWN },
 
 		/*
 		 * BD99956 handles charge input automatically. We'll disable
 		 * charge output in hibernate. Charger will assert ACOK_OD
 		 * when VBUS or VCC are plugged in.
 		 */
-		{GPIO_USB_C0_5V_EN,       GPIO_INPUT  | GPIO_PULL_DOWN},
-		{GPIO_USB_C1_5V_EN,       GPIO_INPUT  | GPIO_PULL_DOWN},
+		{ GPIO_USB_C0_5V_EN, GPIO_INPUT | GPIO_PULL_DOWN },
+		{ GPIO_USB_C1_5V_EN, GPIO_INPUT | GPIO_PULL_DOWN },
 	};
 
 	/* Change GPIOs' state in hibernate for better power consumption */
@@ -703,17 +714,13 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0,  0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+				       { FLOAT_TO_FP(1), 0, 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
 
-const mat33_fp_t mag_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0,  FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t mag_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				      { 0, FLOAT_TO_FP(1), 0 },
+				      { 0, 0, FLOAT_TO_FP(-1) } };
 
 /* sensor private data */
 static struct kionix_accel_data g_kx022_data;
@@ -823,8 +830,8 @@ static void board_set_motion_sensor_count(uint8_t sku_id)
 	 * sensor. If a new SKU id is used that is not in the table, then the
 	 * number of motion sensors will remain as ARRAY_SIZE(motion_sensors).
 	 */
-	motion_sensor_count = SKU_IS_CONVERTIBLE(sku_id) ?
-		ARRAY_SIZE(motion_sensors) : 0;
+	motion_sensor_count =
+		SKU_IS_CONVERTIBLE(sku_id) ? ARRAY_SIZE(motion_sensors) : 0;
 
 	CPRINTS("Motion Sensor Count = %d", motion_sensor_count);
 }
@@ -835,11 +842,11 @@ struct {
 } const coral_board_versions[] = {
 	/* Vin = 3.3V, Ideal voltage, R2 values listed below */
 	/* R1 = 51.1 kOhm */
-	{ BOARD_VERSION_1, 200 },  /* 124 mV, 2.0 Kohm */
-	{ BOARD_VERSION_2, 366 },  /* 278 mV, 4.7 Kohm */
-	{ BOARD_VERSION_3, 550 },  /* 456 mV, 8.2  Kohm */
-	{ BOARD_VERSION_4, 752 },  /* 644 mV, 12.4 Kohm */
-	{ BOARD_VERSION_5, 927},   /* 860 mV, 18.0 Kohm */
+	{ BOARD_VERSION_1, 200 }, /* 124 mV, 2.0 Kohm */
+	{ BOARD_VERSION_2, 366 }, /* 278 mV, 4.7 Kohm */
+	{ BOARD_VERSION_3, 550 }, /* 456 mV, 8.2  Kohm */
+	{ BOARD_VERSION_4, 752 }, /* 644 mV, 12.4 Kohm */
+	{ BOARD_VERSION_5, 927 }, /* 860 mV, 18.0 Kohm */
 	{ BOARD_VERSION_6, 1073 }, /* 993 mV, 22.0 Kohm */
 	{ BOARD_VERSION_7, 1235 }, /* 1152 mV, 27.4 Kohm */
 	{ BOARD_VERSION_8, 1386 }, /* 1318 mV, 34.0 Kohm */
@@ -892,7 +899,7 @@ int board_get_version(void)
 	return version;
 }
 
-static void board_get_sku_id(void)
+static void sku_id_init(void)
 {
 	int sku_id_lower;
 	int sku_id_higher;
@@ -911,12 +918,12 @@ static void board_get_sku_id(void)
 			CPRINTS("Disable tablet mode interrupt");
 			gpio_disable_interrupt(GPIO_TABLET_MODE_L);
 			/* Enfore device in laptop mode */
-			tablet_set_mode(0);
+			tablet_set_mode(0, TABLET_TRIGGER_LID);
 		}
 	}
 }
 /* This can't run until after the ADC module has been initialized */
-DECLARE_HOOK(HOOK_INIT, board_get_sku_id, HOOK_PRIO_INIT_ADC + 1);
+DECLARE_HOOK(HOOK_INIT, sku_id_init, HOOK_PRIO_INIT_ADC + 1);
 
 static void print_form_factor_list(int low, int high)
 {
@@ -926,15 +933,15 @@ static void print_form_factor_list(int low, int high)
 	if (high > 255)
 		high = 255;
 	for (id = low; id <= high; id++) {
-		ccprintf("SKU ID %03d: %s\n", id, SKU_IS_CONVERTIBLE(id) ?
-			 "Convertible" : "Clamshell");
+		ccprintf("SKU ID %03d: %s\n", id,
+			 SKU_IS_CONVERTIBLE(id) ? "Convertible" : "Clamshell");
 		/* Don't print too many lines at once */
 		if (!(++count % 5))
 			msleep(20);
 	}
 }
 
-static int command_sku(int argc, char **argv)
+static int command_sku(int argc, const char **argv)
 {
 	enum adc_channel chan;
 
@@ -977,20 +984,19 @@ static int command_sku(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(sku, command_sku,
-			"<board|line0|line1|form [low high]>",
+DECLARE_CONSOLE_COMMAND(sku, command_sku, "<board|line0|line1|form [low high]>",
 			"Get board id, sku, form factor");
 
-uint32_t system_get_sku_id(void)
+__override uint32_t board_get_sku_id(void)
 {
 	if (sku_id == BOARD_VERSION_UNKNOWN)
-		board_get_sku_id();
+		sku_id_init();
 
 	return (uint32_t)sku_id;
 }
 
 /* Keyboard scan setting */
-struct keyboard_scan_config keyscan_config = {
+__override struct keyboard_scan_config keyscan_config = {
 	/*
 	 * F3 key scan cycle completed but scan input is not
 	 * charging to logic high when EC start scan next
diff --git a/board/coral/board.h b/board/coral/board.h
index 85ddd8e5c2..f5cc6bb706 100644
--- a/board/coral/board.h
+++ b/board/coral/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,24 +12,27 @@
  * By default, enable all console messages except Events:
  * The sensor stack is generating a lot of activity.
  */
-#define CC_DEFAULT     (CC_ALL & ~CC_MASK(CC_EVENTS))
+#define CC_DEFAULT (CC_ALL & ~CC_MASK(CC_EVENTS))
 #undef CONFIG_HOSTCMD_DEBUG_MODE
 #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
 
+#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD
 
 /* EC console commands  */
 #define CONFIG_CMD_ACCELS
 #define CONFIG_CMD_ACCEL_INFO
 #define CONFIG_CMD_BATT_MFG_ACCESS
 #define CONFIG_CMD_CHARGER_ADC_AMON_BMON
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 5
 #define BD9995X_IOUT_GAIN_SELECT \
-		BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V
+	BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V
 
 #define CONFIG_CHARGER_PSYS_READ
 #define BD9995X_PSYS_GAIN_SELECT \
-		BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_02UAW
+	BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_02UAW
 
 #define CONFIG_CMD_I2C_STRESS_TEST
 #define CONFIG_CMD_I2C_STRESS_TEST_ACCEL
@@ -43,10 +46,11 @@
 #define CONFIG_PORT80_HISTORY_LEN 256
 
 /* Battery */
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY  "LION"
+#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
 #define CONFIG_BATTERY_CUT_OFF
 #define CONFIG_BATTERY_HW_PRESENT_CUSTOM
-#define CONFIG_BATTERY_LEVEL_NEAR_FULL 94
+#undef CONFIG_BATT_HOST_FULL_FACTOR
+#define CONFIG_BATT_HOST_FULL_FACTOR 94
 #define CONFIG_BATTERY_PRESENT_CUSTOM
 #define CONFIG_BATTERY_SMART
 
@@ -58,8 +62,10 @@
 #define CONFIG_CHARGER_BD9995X
 #define CONFIG_CHARGER_BD9995X_CHGEN
 #define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT 512
+#define CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT 512
+#define CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT 512
 #define CONFIG_CHARGER_MAINTAIN_VBAT
+#undef CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON
 #define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 1
 #define CONFIG_USB_CHARGER
 #define CONFIG_CHARGER_PROFILE_OVERRIDE
@@ -88,7 +94,7 @@
 #define CONFIG_USB_PD_PORT_MAX_COUNT 2
 #define CONFIG_USB_PD_VBUS_DETECT_CHARGER
 #define CONFIG_USB_PD_TCPC_LOW_POWER
-#define CONFIG_USB_PD_TCPM_MUX  /* for both PS8751 and ANX3429 */
+#define CONFIG_USB_PD_TCPM_MUX /* for both PS8751 and ANX3429 */
 #define CONFIG_USB_PD_TCPM_ANX3429
 #define CONFIG_USB_PD_TCPM_PS8751
 #define CONFIG_USB_PD_TCPM_TCPCI
@@ -103,7 +109,7 @@
 #define CONFIG_USBC_VCONN_SWAP
 
 /* SoC / PCH */
-#define CONFIG_HOSTCMD_LPC
+#define CONFIG_HOST_INTERFACE_LPC
 #define CONFIG_CHIPSET_APOLLOLAKE
 #define CONFIG_CHIPSET_RESET_HOOK
 #define CONFIG_POWER_BUTTON
@@ -114,17 +120,16 @@
 
 /* EC */
 #define CONFIG_ADC
-#define CONFIG_BOARD_VERSION_CUSTOM
 #define CONFIG_EXTPOWER_GPIO
-#undef   CONFIG_EXTPOWER_DEBOUNCE_MS
-#define  CONFIG_EXTPOWER_DEBOUNCE_MS 1000
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
+#define CONFIG_EXTPOWER_DEBOUNCE_MS 1000
 #define CONFIG_FPU
 /* Region sizes are not a power of 2 so we can't use MPU */
-#undef  CONFIG_MPU
+#undef CONFIG_MPU
 #define CONFIG_HOSTCMD_FLASH_SPI_INFO
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
-#define CONFIG_KEYBOARD_BOARD_CONFIG
+#define CONFIG_I2C_CONTROLLER
+
 #define CONFIG_KEYBOARD_PROTOCOL_8042
 #define CONFIG_KEYBOARD_COL2_INVERTED
 #define CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2
@@ -149,7 +154,7 @@
 #define CONFIG_WIRELESS
 #define CONFIG_WIRELESS_SUSPEND EC_WIRELESS_SWITCH_WLAN_POWER
 #define CONFIG_WLAN_POWER_ACTIVE_LOW
-#define  WIRELESS_GPIO_WLAN_POWER GPIO_WIRELESS_GPIO_WLAN_POWER
+#define WIRELESS_GPIO_WLAN_POWER GPIO_WIRELESS_GPIO_WLAN_POWER
 #define CONFIG_PWR_STATE_DISCHARGE_FULL
 
 /*
@@ -165,9 +170,9 @@
 #undef CONFIG_MOTION_SENSE_SUSPEND_DELAY_US
 #define CONFIG_MOTION_SENSE_SUSPEND_DELAY_US (MSEC * 60)
 
-#define CONFIG_FLASH_SIZE 524288
+#define CONFIG_FLASH_SIZE_BYTES 524288
 #define CONFIG_SPI_FLASH_REGS
-#define CONFIG_SPI_FLASH_W25Q40	/* FIXME: Should be GD25LQ40? */
+#define CONFIG_SPI_FLASH_W25Q40 /* FIXME: Should be GD25LQ40? */
 
 /*
  * Enable 1 slot of secure temporary storage to support
@@ -177,25 +182,24 @@
 #define CONFIG_VSTORE_SLOT_COUNT 1
 
 /* Optional feature - used by nuvoton */
-#define NPCX_UART_MODULE2    1 /* 0:GPIO10/11 1:GPIO64/65 as UART */
-#define NPCX_JTAG_MODULE2    0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/
+#define NPCX_UART_MODULE2 1 /* 0:GPIO10/11 1:GPIO64/65 as UART */
+#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/
 /* FIXME(dhendrix): these pins are just normal GPIOs on Coral. Do we need
  * to change some other setting to put them in GPIO mode? */
-#define NPCX_TACH_SEL2       0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
+#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
 
 /* I2C ports */
-#define I2C_PORT_GYRO			NPCX_I2C_PORT1
-#define I2C_PORT_LID_ACCEL		NPCX_I2C_PORT2
-#define I2C_PORT_BATTERY		NPCX_I2C_PORT3
-#define I2C_PORT_CHARGER		NPCX_I2C_PORT3
+#define I2C_PORT_GYRO NPCX_I2C_PORT1
+#define I2C_PORT_LID_ACCEL NPCX_I2C_PORT2
+#define I2C_PORT_BATTERY NPCX_I2C_PORT3
+#define I2C_PORT_CHARGER NPCX_I2C_PORT3
 /* Accelerometer and Gyroscope are the same device. */
-#define I2C_PORT_ACCEL			I2C_PORT_GYRO
+#define I2C_PORT_ACCEL I2C_PORT_GYRO
 
 /* Sensors */
 #define CONFIG_MKBP_EVENT
 #define CONFIG_MKBP_USE_HOST_EVENT
 #define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCEL_INTERRUPTS
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 #define CONFIG_MAG_CALIBRATE
@@ -213,7 +217,6 @@
 /* Depends on how fast the AP boots and typical ODRs */
 #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
 
-
 #ifndef __ASSEMBLER__
 
 #include "gpio_signal.h"
@@ -221,11 +224,11 @@
 
 /* ADC signal */
 enum adc_channel {
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC0 */
-	ADC_TEMP_SENSOR_AMB,		/* ADC1 */
-	ADC_BOARD_ID,			/* ADC2 */
-	ADC_BOARD_SKU_1,		/* ADC3 */
-	ADC_BOARD_SKU_0,		/* ADC4 */
+	ADC_TEMP_SENSOR_CHARGER, /* ADC0 */
+	ADC_TEMP_SENSOR_AMB, /* ADC1 */
+	ADC_BOARD_ID, /* ADC2 */
+	ADC_BOARD_SKU_1, /* ADC3 */
+	ADC_BOARD_SKU_0, /* ADC4 */
 	ADC_CH_COUNT
 };
 
@@ -283,17 +286,16 @@ enum coral_board_version {
  * delay to turn on the power supply max is ~16ms.
  * delay to turn off the power supply max is about ~180ms.
  */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* delay to turn on/off vconn */
-#define PD_VCONN_SWAP_DELAY 5000 /* us */
 
 /* Define typical operating power and max power */
 #define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       45000
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_VOLTAGE_MV     20000
+#define PD_MAX_POWER_MW 45000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Reset PD MCU */
 void board_reset_pd_mcu(void);
diff --git a/board/coral/build.mk b/board/coral/build.mk
index 728d027803..470e439b13 100644
--- a/board/coral/build.mk
+++ b/board/coral/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/coral/ec.tasklist b/board/coral/ec.tasklist
index eeebc0cc59..bc8668a1db 100644
--- a/board/coral/ec.tasklist
+++ b/board/coral/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/coral/gpio.inc b/board/coral/gpio.inc
index 43a130a140..7f09fe0735 100644
--- a/board/coral/gpio.inc
+++ b/board/coral/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -62,7 +62,7 @@ GPIO(EC_I2C_POWER_SCL,		PIN(D, 1), GPIO_INPUT)
  * Pin 57 (SER_IRQ) defaults to LPC mode, but we also have EC_PCH_KB_INT_ODL
  * (Pin B0) in case it doesn't work (Set CONFIG_KEYBOARD_IRQ_GPIO in this case).
  *
- * See also the NO_LPC_ESPI bit in DEVALT1 and the CONFIG_HOSTCMD_SPS option.
+ * See also the NO_LPC_ESPI bit in DEVALT1 and the CONFIG_HOST_INTERFACE_SHI option.
  */
 
 GPIO(PCH_SMI_L,			PIN(A, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V)	/* EC_SMI_ODL */
@@ -161,7 +161,7 @@ ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0)	/* GPIOB5-B4 for EC_I2C_USB_C0_PD
 ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, 0)	/* GPOPB3-B2 for EC_I2C_USB_C1_PD_SDA/SCL */
 ALTERNATE(PIN_MASK(D, 0x03), 1, MODULE_I2C, 0)	/* GPIOD1-D0 for EC_I2C_POWER_SDA/SCL */
 
-ALTERNATE(PIN(B, 6), 3, MODULE_PWM, 0)		/* PWM KB Backlight */
+ALTERNATE(PIN_MASK(B, BIT(6)), 3, MODULE_PWM, 0) /* PWM KB Backlight */
 
 /* FIXME: Make UART RX an interrupt? */
 ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)	/* UART from EC to Servo */
diff --git a/board/coral/led.c b/board/coral/led.c
index 2a1e39946c..09d944b979 100644
--- a/board/coral/led.c
+++ b/board/coral/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -28,8 +28,7 @@
 #define LED_POWER_ON_TICKS (LED_POWER_BLINK_ON_MSEC / HOOK_TICK_INTERVAL_MS)
 #define LED_POWER_OFF_TICKS (LED_POWER_BLINK_OFF_MSEC / HOOK_TICK_INTERVAL_MS)
 
-const enum ec_led_id supported_led_ids[] = {
-			EC_LED_ID_BATTERY_LED};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -37,18 +36,14 @@ const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 #define GPIO_LED_COLOR_2 GPIO_BAT_LED_BLUE
 #define GPIO_LED_COLOR_3 GPIO_POW_LED
 
-enum led_phase {
-	LED_PHASE_0,
-	LED_PHASE_1,
-	LED_NUM_PHASES
-};
+enum led_phase { LED_PHASE_0, LED_PHASE_1, LED_NUM_PHASES };
 
 enum led_color {
 	LED_OFF,
 	LED_COLOR_1,
 	LED_COLOR_2,
 	LED_COLOR_BOTH,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 enum led_states {
@@ -85,37 +80,37 @@ struct led_info {
 
 /* COLOR_1 = Amber, COLOR_2 = Blue */
 static const struct led_descriptor led_default_state_table[][LED_NUM_PHASES] = {
-	{ {LED_COLOR_1, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} },
-	{ {LED_COLOR_2, LED_INDEFINITE}, {LED_COLOR_1, LED_INDEFINITE} },
-	{ {LED_COLOR_2, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} },
-	{ {LED_COLOR_2, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} },
-	{ {LED_COLOR_1, 1 * LED_ONE_SEC }, {LED_OFF, 3 * LED_ONE_SEC} },
-	{ {LED_OFF, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} },
-	{ {LED_COLOR_1, 1 * LED_ONE_SEC}, {LED_OFF, 1 * LED_ONE_SEC} },
-	{ {LED_COLOR_1, 2 * LED_ONE_SEC}, {LED_COLOR_2, 2 * LED_ONE_SEC} },
+	{ { LED_COLOR_1, LED_INDEFINITE }, { LED_OFF, LED_INDEFINITE } },
+	{ { LED_COLOR_2, LED_INDEFINITE }, { LED_COLOR_1, LED_INDEFINITE } },
+	{ { LED_COLOR_2, LED_INDEFINITE }, { LED_OFF, LED_INDEFINITE } },
+	{ { LED_COLOR_2, LED_INDEFINITE }, { LED_OFF, LED_INDEFINITE } },
+	{ { LED_COLOR_1, 1 * LED_ONE_SEC }, { LED_OFF, 3 * LED_ONE_SEC } },
+	{ { LED_OFF, LED_INDEFINITE }, { LED_OFF, LED_INDEFINITE } },
+	{ { LED_COLOR_1, 1 * LED_ONE_SEC }, { LED_OFF, 1 * LED_ONE_SEC } },
+	{ { LED_COLOR_1, 2 * LED_ONE_SEC }, { LED_COLOR_2, 2 * LED_ONE_SEC } },
 };
 
 /* COLOR_1 = Green, COLOR_2 = Red */
 static const struct led_descriptor led_robo_state_table[][LED_NUM_PHASES] = {
-	{ {LED_COLOR_2, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} },
-	{ {LED_COLOR_BOTH, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} },
-	{ {LED_COLOR_1, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} },
-	{ {LED_OFF, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} },
-	{ {LED_OFF, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} },
-	{ {LED_OFF, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} },
-	{ {LED_COLOR_2, 1 * LED_ONE_SEC}, {LED_OFF, 1 * LED_ONE_SEC} },
-	{ {LED_COLOR_2, 2 * LED_ONE_SEC}, {LED_COLOR_1, 2 * LED_ONE_SEC} },
+	{ { LED_COLOR_2, LED_INDEFINITE }, { LED_OFF, LED_INDEFINITE } },
+	{ { LED_COLOR_BOTH, LED_INDEFINITE }, { LED_OFF, LED_INDEFINITE } },
+	{ { LED_COLOR_1, LED_INDEFINITE }, { LED_OFF, LED_INDEFINITE } },
+	{ { LED_OFF, LED_INDEFINITE }, { LED_OFF, LED_INDEFINITE } },
+	{ { LED_OFF, LED_INDEFINITE }, { LED_OFF, LED_INDEFINITE } },
+	{ { LED_OFF, LED_INDEFINITE }, { LED_OFF, LED_INDEFINITE } },
+	{ { LED_COLOR_2, 1 * LED_ONE_SEC }, { LED_OFF, 1 * LED_ONE_SEC } },
+	{ { LED_COLOR_2, 2 * LED_ONE_SEC }, { LED_COLOR_1, 2 * LED_ONE_SEC } },
 };
 
 static const struct led_descriptor led_nasher_state_table[][LED_NUM_PHASES] = {
-	{ {LED_COLOR_1, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} },
-	{ {LED_COLOR_2, LED_INDEFINITE}, {LED_COLOR_1, LED_INDEFINITE} },
-	{ {LED_COLOR_2, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} },
-	{ {LED_COLOR_2, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} },
-	{ {LED_COLOR_2, 1 * LED_ONE_SEC}, {LED_OFF, 1 * LED_ONE_SEC} },
-	{ {LED_OFF, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} },
-	{ {LED_COLOR_1, 1 * LED_ONE_SEC}, {LED_OFF, 1 * LED_ONE_SEC} },
-	{ {LED_COLOR_1, 2 * LED_ONE_SEC}, {LED_COLOR_2, 2 * LED_ONE_SEC} },
+	{ { LED_COLOR_1, LED_INDEFINITE }, { LED_OFF, LED_INDEFINITE } },
+	{ { LED_COLOR_2, LED_INDEFINITE }, { LED_COLOR_1, LED_INDEFINITE } },
+	{ { LED_COLOR_2, LED_INDEFINITE }, { LED_OFF, LED_INDEFINITE } },
+	{ { LED_COLOR_2, LED_INDEFINITE }, { LED_OFF, LED_INDEFINITE } },
+	{ { LED_COLOR_2, 1 * LED_ONE_SEC }, { LED_OFF, 1 * LED_ONE_SEC } },
+	{ { LED_OFF, LED_INDEFINITE }, { LED_OFF, LED_INDEFINITE } },
+	{ { LED_COLOR_1, 1 * LED_ONE_SEC }, { LED_OFF, 1 * LED_ONE_SEC } },
+	{ { LED_COLOR_1, 2 * LED_ONE_SEC }, { LED_COLOR_2, 2 * LED_ONE_SEC } },
 };
 
 static struct led_info led;
@@ -176,24 +171,25 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 
 static enum led_states led_get_state(void)
 {
-	int  charge_lvl;
+	int charge_lvl;
 	enum led_states new_state = LED_NUM_STATES;
 
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
 		/* Get percent charge */
 		charge_lvl = charge_get_percent();
 		/* Determine which charge state to use */
 		new_state = charge_lvl <= led.charge_lvl_1 ?
-			STATE_CHARGING_LVL_1 : STATE_CHARGING_LVL_2;
+				    STATE_CHARGING_LVL_1 :
+				    STATE_CHARGING_LVL_2;
 		break;
-	case PWR_STATE_DISCHARGE_FULL:
+	case LED_PWRS_DISCHARGE_FULL:
 		if (extpower_is_present()) {
 			new_state = STATE_CHARGING_LVL_3;
 			break;
 		}
-		/* Intentional fall-through */
-	case PWR_STATE_DISCHARGE /* and PWR_STATE_DISCHARGE_FULL */:
+		__fallthrough;
+	case LED_PWRS_DISCHARGE /* and LED_PWRS_DISCHARGE_FULL */:
 		if (chipset_in_state(CHIPSET_STATE_ON))
 			new_state = STATE_DISCHARGE_S0;
 		else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
@@ -201,17 +197,17 @@ static enum led_states led_get_state(void)
 		else
 			new_state = STATE_DISCHARGE_S5;
 		break;
-	case PWR_STATE_ERROR:
+	case LED_PWRS_ERROR:
 		new_state = STATE_BATTERY_ERROR;
 		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
+	case LED_PWRS_CHARGE_NEAR_FULL:
 		new_state = STATE_CHARGING_LVL_3;
 		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (charge_get_flags() & CHARGE_FLAG_FORCE_IDLE)
-			new_state = STATE_FACTORY_TEST;
-		else
-			new_state = STATE_DISCHARGE_S0;
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		new_state = STATE_DISCHARGE_S0;
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		new_state = STATE_FACTORY_TEST;
 		break;
 	default:
 		/* Other states don't alter LED behavior */
@@ -248,11 +244,13 @@ static void led_update_battery(void)
 		int period;
 
 		period = led.state_table[led.state][LED_PHASE_0].time +
-			led.state_table[led.state][LED_PHASE_1].time;
+			 led.state_table[led.state][LED_PHASE_1].time;
 		if (period)
-			phase = ticks % period <
-				led.state_table[led.state][LED_PHASE_0].time ?
-				0 : 1;
+			phase = ticks % period < led.state_table[led.state]
+								[LED_PHASE_0]
+									.time ?
+					0 :
+					1;
 	}
 
 	/* Set the color for the given state and phase */
@@ -278,8 +276,8 @@ static void led_robo_update_power(void)
 		 * power LED is off for 600 msec, on for 3 seconds.
 		 */
 		period = LED_POWER_ON_TICKS + LED_POWER_OFF_TICKS;
-		level = ticks % period < LED_POWER_OFF_TICKS ?
-			LED_OFF_LVL : LED_ON_LVL;
+		level = ticks % period < LED_POWER_OFF_TICKS ? LED_OFF_LVL :
+							       LED_ON_LVL;
 		ticks++;
 	} else {
 		level = LED_OFF_LVL;
diff --git a/board/coral/sku.h b/board/coral/sku.h
index 4588932377..c12777a2f7 100644
--- a/board/coral/sku.h
+++ b/board/coral/sku.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,7 +8,7 @@
 #ifndef __CROS_EC_SKU_H
 #define __CROS_EC_SKU_H
 
-#define SKU_CONVERTIBLE(id) (1 << ((id) & 0x7))
+#define SKU_CONVERTIBLE(id) (1 << ((id)&0x7))
 
 /*
  * There are 256 possible SKUs for Coral. This table is used to map a given SKU
@@ -22,7 +22,7 @@ static const uint8_t form_factor[32] = {
 	SKU_CONVERTIBLE(4) | SKU_CONVERTIBLE(5),
 	/* SKU 8 - 15 */
 	SKU_CONVERTIBLE(8) | SKU_CONVERTIBLE(9) | SKU_CONVERTIBLE(10) |
-	SKU_CONVERTIBLE(11),
+		SKU_CONVERTIBLE(11),
 	/* SKU 16 - 23 */
 	0x00,
 	/* SKU 24 - 31 */
@@ -61,7 +61,7 @@ static const uint8_t form_factor[32] = {
 	0x00,
 	/* SKU 160 - 167 */
 	SKU_CONVERTIBLE(163) | SKU_CONVERTIBLE(164) | SKU_CONVERTIBLE(165) |
-	SKU_CONVERTIBLE(166),
+		SKU_CONVERTIBLE(166),
 	/* SKU 168 - 175 */
 	0x00,
 	/* SKU 176 - 183 */
@@ -86,6 +86,6 @@ static const uint8_t form_factor[32] = {
 	0x00,
 };
 
-#define SKU_IS_CONVERTIBLE(id) ((form_factor[(id) >> 3] >> ((id) & 0x7)) & 1)
+#define SKU_IS_CONVERTIBLE(id) ((form_factor[(id) >> 3] >> ((id)&0x7)) & 1)
 
 #endif /* __CROS_EC_SKU_H */
diff --git a/board/coral/usb_pd_policy.c b/board/coral/usb_pd_policy.c
index e071f6ae2a..ad6ac613e8 100644
--- a/board/coral/usb_pd_policy.c
+++ b/board/coral/usb_pd_policy.c
@@ -1,16 +1,16 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "atomic.h"
-#include "extpower.h"
 #include "charge_manager.h"
 #include "common.h"
 #include "console.h"
 #include "driver/charger/bd9995x.h"
 #include "driver/tcpm/anx74xx.h"
 #include "driver/tcpm/ps8xxx.h"
+#include "extpower.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "host_command.h"
@@ -18,17 +18,17 @@
 #include "system.h"
 #include "task.h"
 #include "timer.h"
-#include "util.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
+#include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT];
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5,
-							TYPEC_RP_1A5};
+static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5,
+							 TYPEC_RP_1A5 };
 
 int board_vbus_source_enabled(int port)
 {
@@ -39,7 +39,8 @@ static void board_vbus_update_source_current(int port)
 {
 	enum gpio_signal gpio = port ? GPIO_USB_C1_5V_EN : GPIO_USB_C0_5V_EN;
 	int flags = (vbus_rp[port] == TYPEC_RP_1A5 && vbus_en[port]) ?
-		(GPIO_INPUT | GPIO_PULL_UP) : (GPIO_OUTPUT | GPIO_PULL_UP);
+			    (GPIO_INPUT | GPIO_PULL_UP) :
+			    (GPIO_OUTPUT | GPIO_PULL_UP);
 
 	/*
 	 * Driving USB_Cx_5V_EN high, actually put a 16.5k resistance
diff --git a/board/coral/vif_override.xml b/board/coral/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/coral/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/corori/battery.c b/board/corori/battery.c
new file mode 100644
index 0000000000..f4e126d42e
--- /dev/null
+++ b/board/corori/battery.c
@@ -0,0 +1,71 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+#include "battery.h"
+#include "battery_fuel_gauge.h"
+#include "common.h"
+#include "gpio.h"
+#include "util.h"
+
+/*
+ * Battery info for lalala battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+		/* C21N2018 Battery Information
+		 * TODO(b:196506846):Need to be verified on the Proto
+		 */
+	 [BATTERY_C21N2018] = {
+		.fuel_gauge = {
+			.manuf_name = "AS3GXXD3KA",
+			.device_name = "C110160",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr = 0x0,
+				.reg_mask = 0x2000,
+				.disconnect_val = 0x2000,
+				.cfet_mask = 0x4000,
+				.cfet_off_val = 0x4000,
+			},
+		},
+		.batt_info = {
+			.voltage_max            = 8800,
+			.voltage_normal         = 7890,
+			.voltage_min            = 6000,
+			.precharge_current      = 256,
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 45,
+			.charging_min_c         = 0,
+			.charging_max_c         = 60,
+			.discharging_min_c      = -20,
+			.discharging_max_c      = 60,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_C21N2018;
diff --git a/board/corori/board.c b/board/corori/board.c
new file mode 100644
index 0000000000..0717b73750
--- /dev/null
+++ b/board/corori/board.c
@@ -0,0 +1,466 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Lalala board-specific configuration */
+
+#include "adc_chip.h"
+#include "button.h"
+#include "cbi_fw_config.h"
+#include "cbi_ssfc.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "chipset.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "driver/bc12/pi3usb9201.h"
+#include "driver/charger/isl923x.h"
+#include "driver/tcpm/raa489000.h"
+#include "driver/tcpm/tcpci.h"
+#include "driver/temp_sensor/thermistor.h"
+#include "driver/usb_mux/pi3usb3x532.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "keyboard_8042.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "stdbool.h"
+#include "switch.h"
+#include "system.h"
+#include "task.h"
+#include "temp_sensor.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+#define INT_RECHECK_US 5000
+
+#define ADC_VOL_UP_MASK BIT(0)
+#define ADC_VOL_DOWN_MASK BIT(1)
+
+/******************************************************************************/
+/* USB-A Configuration */
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_USB_A0_VBUS,
+};
+
+static const struct ec_response_keybd_config corori_keybd = {
+	/* Default Chromeos keyboard config */
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_FORWARD,		/* T2 */
+		TK_REFRESH,		/* T3 */
+		TK_FULLSCREEN,		/* T4 */
+		TK_OVERVIEW,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	/* No function keys, no numeric keypad, no screenlock key */
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &corori_keybd;
+}
+
+/* C0 interrupt line shared by BC 1.2 and charger */
+static void check_c0_line(void);
+DECLARE_DEFERRED(check_c0_line);
+
+static void notify_c0_chips(void)
+{
+	/*
+	 * The interrupt line is shared between the TCPC and BC 1.2 detection
+	 * chip.  Therefore we'll need to check both ICs.
+	 */
+	schedule_deferred_pd_interrupt(0);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+
+static void check_c0_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		notify_c0_chips();
+		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+	}
+}
+
+static void usb_c0_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c0_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c0_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+}
+
+static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
+{
+	cprints(CC_USBPD, "C0: CC OVP, SBU OVP, or thermal event");
+	pd_handle_cc_overvoltage(0);
+}
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_1] = {
+		.name = "TEMP_SENSOR1",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_2] = {
+		.name = "TEMP_SENSOR2",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_VSNS_PP3300_A] = {
+		.name = "PP3300_A_PGOOD",
+		.input_ch = NPCX_ADC_CH9,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* Thermistors */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Charger",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_A                \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(85), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A;
+
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_B                \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(73), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(85), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_b = THERMAL_B;
+
+struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
+
+static void setup_thermal(void)
+{
+	thermal_params[TEMP_SENSOR_1] = thermal_a;
+	thermal_params[TEMP_SENSOR_2] = thermal_b;
+}
+
+void board_hibernate(void)
+{
+	/*
+	 * Both charger ICs need to be put into their "low power mode" before
+	 * entering the Z-state.
+	 */
+	raa489000_hibernate(1, true);
+	raa489000_hibernate(0, true);
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * TODO(b:147316511): Here we could issue a digital reset to the IC,
+	 * unsure if we actually want to do that or not yet.
+	 */
+}
+
+static void set_5v_gpio(int level)
+{
+	gpio_set_level(GPIO_EN_PP5000, level);
+	gpio_set_level(GPIO_EN_USB_A0_VBUS, level);
+}
+
+__override void board_power_5v_enable(int enable)
+{
+	/*
+	 * Port 0 simply has a GPIO to turn on the 5V regulator, however, 5V is
+	 * generated locally on the sub board and we need to set the comparator
+	 * polarity on the sub board charger IC.
+	 */
+	set_5v_gpio(!!enable);
+}
+
+int board_is_sourcing_vbus(int port)
+{
+	int regval;
+
+	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
+	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int i;
+	int old_port;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	old_port = charge_manager_get_active_charge_port();
+
+	CPRINTS("New chg p%d", port);
+
+	/* Disable all ports. */
+	if (port == CHARGE_PORT_NONE) {
+		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
+			tcpc_write(i, TCPC_REG_COMMAND,
+				   TCPC_REG_COMMAND_SNK_CTRL_LOW);
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if port is sourcing VBUS. */
+	if (board_is_sourcing_vbus(port)) {
+		CPRINTS("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		if (i == port)
+			continue;
+
+		if (tcpc_write(i, TCPC_REG_COMMAND,
+			       TCPC_REG_COMMAND_SNK_CTRL_LOW))
+			CPRINTS("p%d: sink path disable failed.", i);
+	}
+
+	/*
+	 * Stop the charger IC from switching while changing ports.  Otherwise,
+	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
+	 */
+	if (old_port != CHARGE_PORT_NONE)
+		charger_discharge_on_ac(1);
+
+	/* Enable requested charge port. */
+	if (tcpc_write(port, TCPC_REG_COMMAND,
+		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
+		CPRINTS("p%d: sink path enable failed.", port);
+		charger_discharge_on_ac(0);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	/* Allow the charger IC to begin/continue switching. */
+	charger_discharge_on_ac(0);
+
+	return EC_SUCCESS;
+}
+
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	if (port < 0 || port > board_get_usb_pd_port_count())
+		return;
+
+	raa489000_set_output_current(port, rp);
+}
+
+void board_init(void)
+{
+	int on;
+
+	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
+	check_c0_line();
+
+	/* Turn on 5V if the system is on, otherwise turn it off. */
+	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
+			      CHIPSET_STATE_SOFT_OFF);
+	board_power_5v_enable(on);
+
+	/* Initialize THERMAL */
+	setup_thermal();
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+				       int *ki_div, int *kd, int *kd_div)
+{
+	*kp = 1;
+	*kp_div = 20;
+	*ki = 1;
+	*ki_div = 250;
+	*kd = 0;
+	*kd_div = 1;
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	return pd_check_vbus_level(port, VBUS_PRESENT);
+}
+
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+};
+const unsigned int chg_cnt = ARRAY_SIZE(chg_chips);
+
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	{
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+		.flags = PI3USB9201_ALWAYS_POWERED,
+	},
+};
+
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0,
+			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
+		},
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+		.drv = &raa489000_tcpm_drv,
+	},
+};
+
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
+				.driver = &pi3usb3x532_usb_mux_driver,
+			},
+	},
+};
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+	int regval;
+
+	/*
+	 * The interrupt line is shared between the TCPC and BC1.2 detector IC.
+	 * Therefore, go out and actually read the alert registers to report the
+	 * alert status.
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
+			/* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */
+			if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0))
+				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
+
+			if (regval)
+				status |= PD_STATUS_TCPC_ALERT_0;
+		}
+	}
+
+	return status;
+}
+
+static void board_extpower(void)
+{
+	int extpower_present;
+
+	if (pd_is_connected(0))
+		extpower_present = extpower_is_present();
+	else
+		extpower_present = 0;
+
+	gpio_set_level(GPIO_EC_ACOK_OTG, extpower_present);
+}
+DECLARE_HOOK(HOOK_AC_CHANGE, board_extpower, HOOK_PRIO_DEFAULT);
+
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_EEPROM_SCL,
+	  .sda = GPIO_EC_I2C_EEPROM_SDA },
+
+	{ .name = "battery",
+	  .port = I2C_PORT_BATTERY,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_BATTERY_SCL,
+	  .sda = GPIO_EC_I2C_BATTERY_SDA },
+
+#ifdef HAS_TASK_MOTIONSENSE
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_SENSOR_SCL,
+	  .sda = GPIO_EC_I2C_SENSOR_SDA },
+#endif
+
+	{ .name = "usbc0",
+	  .port = I2C_PORT_USB_C0,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C0_SCL,
+	  .sda = GPIO_EC_I2C_USB_C0_SDA },
+#if CONFIG_USB_PD_PORT_MAX_COUNT > 1
+	{ .name = "sub_usbc1",
+	  .port = I2C_PORT_SUB_USB_C1,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_SUB_USB_C1_SCL,
+	  .sda = GPIO_EC_I2C_SUB_USB_C1_SDA },
+#endif
+};
diff --git a/board/corori/board.h b/board/corori/board.h
new file mode 100644
index 0000000000..5db8be64cc
--- /dev/null
+++ b/board/corori/board.h
@@ -0,0 +1,114 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Lalala board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#define VARIANT_KEEBY_EC_NPCX797FC
+#include "baseboard.h"
+
+/*
+ * The RAM and flash size combination on the the NPCX797FC does not leave
+ * any unused flash space that can be used to store the .init_rom section.
+ */
+#undef CONFIG_CHIP_INIT_ROM_REGION
+
+/* Battery */
+#define CONFIG_BATTERY_FUEL_GAUGE
+
+/* Charger */
+#define CONFIG_CHARGER_RAA489000
+#define PD_MAX_VOLTAGE_MV 20000
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#undef CONFIG_CMD_CHARGER_DUMP
+#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
+#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
+/*
+ * b/147463641: The charger IC seems to overdraw ~4%, therefore we
+ * reduce our target accordingly.
+ */
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 4
+
+/* LED defines */
+#define CONFIG_LED_COMMON
+#undef CONFIG_BATT_HOST_FULL_FACTOR
+#define CONFIG_BATT_HOST_FULL_FACTOR 94
+#define GPIO_BAT_LED_AMBER GPIO_LED_Y_ODL
+#define GPIO_PWR_LED_WHITE GPIO_LED_W_ODL
+
+/* PWM */
+#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */
+
+/* Temp sensor */
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_THERMISTOR
+#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
+
+/* USB */
+#define CONFIG_BC12_DETECT_PI3USB9201
+
+/* Common USB-A defines */
+#define USB_PORT_COUNT 1
+
+/******************************************************************************/
+
+/* USB PD */
+#define CONFIG_USB_PD_PORT_MAX_COUNT 1
+#define CONFIG_USB_PD_TCPM_RAA489000
+
+/* USB defines specific to external TCPCs */
+#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+#define CONFIG_USB_PD_VBUS_DETECT_TCPC
+#define CONFIG_USB_PD_DISCHARGE_TCPC
+#define CONFIG_USB_PD_TCPC_LOW_POWER
+
+/* Variant references the TCPCs to determine Vbus sourcing */
+#define CONFIG_USB_PD_5V_EN_CUSTOM
+
+/* I2C configuration */
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
+#define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0
+/* TODO(b:147440290): Need to handle multiple charger ICs */
+#define I2C_PORT_CHARGER I2C_PORT_USB_C0
+
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */
+
+/* Volume Button feature */
+#define CONFIG_VOLUME_BUTTONS
+#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum adc_channel {
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
+	ADC_VSNS_PP3300_A, /* ADC9 */
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT };
+
+enum battery_type {
+	BATTERY_C21N2018,
+	BATTERY_TYPE_COUNT,
+};
+
+int board_is_sourcing_vbus(int port);
+#endif /* !__ASSEMBLER__ */
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/corori/build.mk b/board/corori/build.mk
new file mode 100644
index 0000000000..eb422dae93
--- /dev/null
+++ b/board/corori/build.mk
@@ -0,0 +1,14 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx7
+CHIP_VARIANT:=npcx7m7fc
+BASEBOARD:=keeby
+
+board-y=board.o battery.o cbi_ssfc.o led.o usb_pd_policy.o
diff --git a/board/corori/cbi_ssfc.c b/board/corori/cbi_ssfc.c
new file mode 100644
index 0000000000..81f3ee0dad
--- /dev/null
+++ b/board/corori/cbi_ssfc.c
@@ -0,0 +1,36 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi_ssfc.h"
+#include "common.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "hooks.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+/* Cache SSFC on init since we don't expect it to change in runtime */
+static union dedede_cbi_ssfc cached_ssfc;
+BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
+
+static void cbi_ssfc_init(void)
+{
+	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
+		/* Default to 0 when CBI isn't populated */
+		cached_ssfc.raw_value = 0;
+
+	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
+}
+DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
+
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
+{
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
+}
+
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
+{
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
+}
diff --git a/board/corori/cbi_ssfc.h b/board/corori/cbi_ssfc.h
new file mode 100644
index 0000000000..bf8853a43a
--- /dev/null
+++ b/board/corori/cbi_ssfc.h
@@ -0,0 +1,59 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _DEDEDE_CBI_SSFC__H_
+#define _DEDEDE_CBI_SSFC__H_
+
+#include "stdint.h"
+
+/****************************************************************************
+ * Dedede CBI Second Source Factory Cache
+ */
+
+/*
+ * Base Sensor (Bits 0-2)
+ */
+enum ec_ssfc_base_sensor {
+	SSFC_SENSOR_BASE_DEFAULT = 0,
+	SSFC_SENSOR_BMI160 = 1,
+	SSFC_SENSOR_ICM426XX = 2,
+	SSFC_SENSOR_LSM6DSM = 3,
+	SSFC_SENSOR_ICM42607 = 4
+};
+
+/*
+ * Lid Sensor (Bits 3-5)
+ */
+enum ec_ssfc_lid_sensor {
+	SSFC_SENSOR_LID_DEFAULT = 0,
+	SSFC_SENSOR_BMA255 = 1,
+	SSFC_SENSOR_KX022 = 2,
+	SSFC_SENSOR_LIS2DWL = 3
+};
+
+union dedede_cbi_ssfc {
+	struct {
+		uint32_t base_sensor : 3;
+		uint32_t lid_sensor : 3;
+		uint32_t reserved_2 : 26;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Get the Base sensor type from SSFC_CONFIG.
+ *
+ * @return the Base sensor board type.
+ */
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
+
+/**
+ * Get the Lid sensor type from SSFC_CONFIG.
+ *
+ * @return the Lid sensor board type.
+ */
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
+
+#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/corori/ec.tasklist b/board/corori/ec.tasklist
new file mode 100644
index 0000000000..386e8625b3
--- /dev/null
+++ b/board/corori/ec.tasklist
@@ -0,0 +1,21 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE)
diff --git a/board/corori/gpio.inc b/board/corori/gpio.inc
new file mode 100644
index 0000000000..038c70243f
--- /dev/null
+++ b/board/corori/gpio.inc
@@ -0,0 +1,141 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first.
+ */
+
+/* Power Interrupts */
+GPIO_INT(SLP_S0_L,		 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,		 PIN(A, 5), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(SLP_S4_L,		 PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,		 PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(RSMRST_PWRGD_L,	 PIN(C, 6), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID1,	 PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(CPU_C10_GATE_L,	 PIN(6, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID0,	 PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, power_signal_interrupt)
+GPIO_INT(PG_VCCIO_EXT_OD,	 PIN(B, 0), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(PG_PP5000_U_OD,	 PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_DRAM_OD,		 PIN(E, 4), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(PG_PP1050_ST_OD,	 PIN(4, 2), GPIO_INT_BOTH, power_signal_interrupt)
+
+/* USB-C interrupts */
+GPIO_INT(USB_C0_INT_ODL,	 PIN(6, 2), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt)
+GPIO_INT(USB_C0_CCSBU_OVP_ODL,	PIN(A, 2), GPIO_INT_FALLING | GPIO_PULL_UP, c0_ccsbu_ovp_interrupt) /* Fault protection */
+
+/* Button interrupts */
+GPIO_INT(EC_PWR_BTN_ODL,	 PIN(0, 1), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
+GPIO_INT(VOLDN_BTN_ODL,		 PIN(4, 0), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(VOLUP_BTN_ODL,		 PIN(7, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+
+/* Other interrupts */
+GPIO_INT(LID_OPEN,		 PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)
+GPIO_INT(EC_WP_OD,		 PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+
+/* I2C Ports */
+GPIO(EC_I2C_EEPROM_SCL,	      PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SDA,	      PIN(B, 2), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SCL,      PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SDA,      PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,	      PIN(B, 5), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SDA,	      PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SCL,	      PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SDA,	      PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_SUB_USB_C1_SCL,   PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_SUB_USB_C1_SDA,   PIN(9, 1), GPIO_INPUT)
+
+/* Extra Sub-board I/O pins */
+
+/* Misc Enables */
+GPIO(EN_VCCIO_EXT,   PIN(6, 1), GPIO_OUT_LOW)
+/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
+GPIO(EN_VCCST,		PIN(A, 7), GPIO_INPUT)
+GPIO(EN_PP3300_PEN,	PIN(6, 3), GPIO_OUT_LOW)
+GPIO(EN_PP3300_A,	PIN(0, 3), GPIO_OUT_LOW)
+GPIO(EN_PP5000_U,	PIN(A, 4), GPIO_OUT_LOW)
+GPIO(EN_SLP_Z,		PIN(8, 3), GPIO_OUT_LOW)
+GPIO(EN_BL_OD,		PIN(D, 3), GPIO_ODR_LOW)
+GPIO(EC_CBI_WP,		PIN(E, 5), GPIO_OUT_LOW)
+
+/* LED */
+GPIO(LED_W_ODL,                  PIN(C, 3), GPIO_OUT_HIGH)        /* POWER LED */
+GPIO(LED_Y_ODL,                  PIN(C, 4), GPIO_OUT_HIGH)        /* BATTERY LED */
+
+/* Power Sequencing */
+GPIO(EC_AP_PSYS,	     PIN(B, 7), GPIO_OUT_LOW)
+GPIO(EC_AP_RSMRST_L,         PIN(A, 6), GPIO_OUT_LOW)
+GPIO(EC_AP_PWR_BTN_ODL,      PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(EC_AP_RTCRST,           PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_AP_WAKE_ODL,         PIN(7, 4), GPIO_ODR_HIGH)
+GPIO(EC_AP_DPWROK,	     PIN(A, 3), GPIO_OUT_LOW)
+GPIO(EC_AP_PCH_PWROK_OD,     PIN(9, 4), GPIO_ODR_LOW)
+GPIO(EC_AP_VCCST_PWRGD_OD,   PIN(B, 1), GPIO_ODR_LOW)
+GPIO(EC_AP_SYS_PWROK,	     PIN(0, 2), GPIO_OUT_LOW)
+GPIO(EC_AP_MKBP_INT_L,	     PIN(7, 0), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_ODL,	     PIN(F, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(EC_ENTERING_RW,	     PIN(E, 3), GPIO_OUT_LOW)
+GPIO(ALL_SYS_PWRGD,	     PIN(A, 0), GPIO_OUT_LOW)
+GPIO(SYS_RST_ODL,	     PIN(C, 5), GPIO_ODR_HIGH)
+
+/* USB pins */
+GPIO(EC_AP_USB_C1_HDMI_HPD,  PIN(9, 6), GPIO_OUT_LOW)
+GPIO(EC_AP_USB_C0_HPD,	     PIN(9, 3), GPIO_OUT_LOW)
+GPIO(HDMI_SEL_L,	     PIN(7, 2), GPIO_OUT_HIGH)
+GPIO(EC_BATTERY_PRES_ODL,    PIN(E, 1), GPIO_INPUT)
+GPIO(EN_USB_A0_VBUS,	 PIN(4, 1), GPIO_OUT_LOW)		/* Enable A0 5V Charging */
+
+GPIO(EC_ACOK_OTG, PIN(C, 0), GPIO_OUT_LOW)  /* OTG-OVP protect enable */
+/*
+ * Lalala doesn't have these physical pins coming to the EC but uses other
+ * logic.
+ */
+UNIMPLEMENTED(AC_PRESENT)
+UNIMPLEMENTED(PG_EC_DSW_PWROK)
+UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
+
+/* Alternate Functions */
+/* ADC */
+ALTERNATE(PIN_MASK(F, BIT(0)), 0, MODULE_ADC, 0) /* ADC9 */
+ALTERNATE(PIN_MASK(4, 0x30), 0, MODULE_ADC, 0)   /* ADC0-1 */
+
+/* Keyboard */
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI0, KSI1 */
+ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI2-7 */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO0, KSO1 */
+ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO3-9 */
+ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO10-13 */
+ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO14 */
+GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW)	/* KSO2 inverted */
+
+/* UART */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)  /* UART1 */
+
+/* I2C */
+ALTERNATE(PIN_MASK(B, 0x3C), 0, MODULE_I2C, 0)   /* I2C7,I2C0 */
+ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)   /* I2C5 */
+ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)   /* I2C2, I2C1 SCL */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)   /* I2C1 SDA */
+
+/* NC pins, enable internal pull-up to avoid floating state. */
+GPIO(GPIO32_NC, PIN(3, 2), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO34_NC, PIN(3, 4), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO35_NC, PIN(3, 5), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO43_NC, PIN(4, 3), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO57_NC, PIN(5, 7), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO60_NC, PIN(6, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO75_NC, PIN(7, 5), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO81_NC, PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO86_NC, PIN(8, 6), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOD0_NC, PIN(D, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOD1_NC, PIN(D, 1), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOD6_NC, PIN(D, 6), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOE0_NC, PIN(E, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO37_NC, PIN(3, 7), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOF2_NC, PIN(F, 2), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOF3_NC, PIN(F, 3), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO50_NC, PIN(5, 0), GPIO_INPUT | GPIO_PULL_UP)
diff --git a/board/corori/led.c b/board/corori/led.c
new file mode 100644
index 0000000000..6ae0e5f4c9
--- /dev/null
+++ b/board/corori/led.c
@@ -0,0 +1,225 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power and battery LED control for lalala
+ */
+
+#include "battery.h"
+#include "charge_state.h"
+#include "chipset.h"
+#include "ec_commands.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "led_common.h"
+#include "system.h"
+#include "util.h"
+
+#define LED_ON_LVL 0
+#define LED_OFF_LVL 1
+#define LED_INDEFINITE UINT8_MAX
+#define LED_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS)
+#define LED_OFF EC_LED_COLOR_COUNT
+
+struct led_descriptor {
+	enum ec_led_colors color;
+	uint8_t time;
+};
+
+enum led_phase { LED_PHASE_0, LED_PHASE_1, LED_NUM_PHASES };
+
+enum led_states {
+	STATE_CHARGING,
+	STATE_CHARGING_FULL_CHARGE,
+	STATE_DISCHARGE_S0,
+	STATE_DISCHARGE_S0_BAT_LOW,
+	STATE_BATTERY_S0_ERROR,
+	STATE_BATTERY_S3_BLINK,
+	STATE_BATTERY_S5_OFF,
+	STATE_FACTORY_TEST,
+	LED_NUM_STATES
+};
+
+static const struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING] = { { EC_LED_COLOR_AMBER, LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_BATTERY_S0_ERROR] = { { EC_LED_COLOR_AMBER,
+					       1 * LED_ONE_SEC },
+					     { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_BATTERY_S3_BLINK] = { { EC_LED_COLOR_WHITE,
+					       1 * LED_ONE_SEC },
+					     { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_BATTERY_S5_OFF] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+static int led_get_charge_percent(void)
+{
+	return DIV_ROUND_NEAREST(charge_get_display_charge(), 10);
+}
+
+void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_AMBER:
+		gpio_set_level(GPIO_BAT_LED_AMBER, LED_ON_LVL);
+		gpio_set_level(GPIO_PWR_LED_WHITE, LED_OFF_LVL);
+		break;
+	case EC_LED_COLOR_WHITE:
+		gpio_set_level(GPIO_BAT_LED_AMBER, LED_OFF_LVL);
+		gpio_set_level(GPIO_PWR_LED_WHITE, LED_ON_LVL);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		gpio_set_level(GPIO_BAT_LED_AMBER, LED_OFF_LVL);
+		gpio_set_level(GPIO_PWR_LED_WHITE, LED_OFF_LVL);
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_battery(EC_LED_COLOR_WHITE);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(EC_LED_COLOR_AMBER);
+		else
+			led_set_color_battery(LED_OFF);
+	}
+	return EC_SUCCESS;
+}
+
+/* Custom led on off states control */
+static enum led_states led_get_state(void)
+{
+	enum led_states new_state = LED_NUM_STATES;
+
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
+		new_state = STATE_CHARGING;
+		break;
+	case LED_PWRS_DISCHARGE_FULL:
+		if (extpower_is_present()) {
+			new_state = STATE_CHARGING_FULL_CHARGE;
+			break;
+		}
+		__fallthrough;
+	case LED_PWRS_DISCHARGE /* and LED_PWRS_DISCHARGE_FULL */:
+		if (chipset_in_state(CHIPSET_STATE_ON))
+			new_state = (led_get_charge_percent() < 10) ?
+					    STATE_DISCHARGE_S0_BAT_LOW :
+					    STATE_DISCHARGE_S0;
+		else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
+			new_state = STATE_BATTERY_S3_BLINK;
+		else
+			new_state = STATE_BATTERY_S5_OFF;
+		break;
+	case LED_PWRS_ERROR:
+		if (chipset_in_state(CHIPSET_STATE_ON))
+			new_state = STATE_BATTERY_S0_ERROR;
+		else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
+			new_state = STATE_BATTERY_S3_BLINK;
+		else
+			new_state = STATE_BATTERY_S5_OFF;
+		break;
+	case LED_PWRS_CHARGE_NEAR_FULL:
+		new_state = STATE_CHARGING_FULL_CHARGE;
+		break;
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		new_state = STATE_DISCHARGE_S0;
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		new_state = STATE_FACTORY_TEST;
+		break;
+	default:
+		/* Other states don't alter LED behavior */
+		break;
+	}
+
+	return new_state;
+}
+
+static void led_update_battery(void)
+{
+	static uint8_t ticks, period;
+	static int led_state = LED_NUM_STATES;
+	int phase;
+	enum led_states desired_state = led_get_state();
+
+	/*
+	 * We always need to check the current state since the value could
+	 * have been manually overwritten. If we're in a new valid state,
+	 * update our ticks and period info. If our new state isn't defined,
+	 * continue using the previous one.
+	 */
+	if (desired_state != led_state && desired_state < LED_NUM_STATES) {
+		/* State is changing */
+		led_state = desired_state;
+		/* Reset ticks and period when state changes */
+		ticks = 0;
+
+		period = led_bat_state_table[led_state][LED_PHASE_0].time +
+			 led_bat_state_table[led_state][LED_PHASE_1].time;
+	}
+
+	/* If this state is undefined, turn the LED off */
+	if (period == 0) {
+		led_set_color_battery(LED_OFF);
+		return;
+	}
+
+	/*
+	 * Determine which phase of the state table to use. The phase is
+	 * determined if it falls within first phase time duration.
+	 */
+	phase = ticks < led_bat_state_table[led_state][LED_PHASE_0].time ? 0 :
+									   1;
+	ticks = (ticks + 1) % period;
+
+	/* Set the color for the given state and phase */
+	led_set_color_battery(led_bat_state_table[led_state][phase].color);
+}
+
+static void led_init(void)
+{
+	/* If battery LED is enabled, set it to "off" to start with */
+	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
+		led_set_color_battery(LED_OFF);
+}
+DECLARE_HOOK(HOOK_INIT, led_init, HOOK_PRIO_DEFAULT);
+
+/* Called by hook task every hook tick (200 msec) */
+static void led_update(void)
+{
+	/*
+	 * If battery LED is enabled, set its state based on our power and
+	 * charge
+	 */
+	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
+		led_update_battery();
+}
+DECLARE_HOOK(HOOK_TICK, led_update, HOOK_PRIO_DEFAULT);
diff --git a/board/corori/usb_pd_policy.c b/board/corori/usb_pd_policy.c
new file mode 100644
index 0000000000..3410726e87
--- /dev/null
+++ b/board/corori/usb_pd_policy.c
@@ -0,0 +1,56 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "driver/tcpm/tcpci.h"
+#include "usb_pd.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+int pd_check_vconn_swap(int port)
+{
+	/* Allow VCONN swaps if the AP is on. */
+	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
+}
+
+void pd_power_supply_reset(int port)
+{
+	/* Disable VBUS */
+	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	if (port >= CONFIG_USB_PD_PORT_MAX_COUNT)
+		return EC_ERROR_INVAL;
+
+	/* Disable charging. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
+	if (rv)
+		return rv;
+
+	/* Our policy is not to source VBUS when the AP is off. */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	/* Provide Vbus. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
+	if (rv)
+		return rv;
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
diff --git a/board/corori/vif_override.xml b/board/corori/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/corori/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/corori2/battery.c b/board/corori2/battery.c
new file mode 100644
index 0000000000..a59663c751
--- /dev/null
+++ b/board/corori2/battery.c
@@ -0,0 +1,100 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery.h"
+#include "battery_fuel_gauge.h"
+#include "charge_state.h"
+#include "common.h"
+#include "util.h"
+
+/*
+ * Battery info for all waddledoo battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	/* C21N2018 Battery Information*/
+	 [BATTERY_C21N2018] = {
+		.fuel_gauge = {
+			.manuf_name = "AS3GXXD3KA",
+			.device_name = "C110160",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr = 0x0,
+				.reg_mask = 0x2000,
+				.disconnect_val = 0x2000,
+				.cfet_mask = 0x4000,
+				.cfet_off_val = 0x4000,
+			},
+		},
+		.batt_info = {
+			.voltage_max            = 8800,
+			.voltage_normal         = 7890,
+			.voltage_min            = 6000,
+			.precharge_current      = 256,
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 45,
+			.charging_min_c         = 0,
+			.charging_max_c         = 60,
+			.discharging_min_c      = -20,
+			.discharging_max_c      = 60,
+		},
+	},
+	/* C21N2018 second Battery Information*/
+	[BATTERY_C21N2018_2ND] = {
+		.fuel_gauge = {
+			.manuf_name = "AS3FXXD3KA",
+			.device_name = "C110160",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr = 0x0,
+				.reg_mask = 0x2000,
+				.disconnect_val = 0x2000,
+				.cfet_mask = 0x4000,
+				.cfet_off_val = 0x4000,
+			},
+		},
+		.batt_info = {
+			.voltage_max            = 8800,
+			.voltage_normal         = 7890,
+			.voltage_min            = 6000,
+			.precharge_current      = 256,
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 45,
+			.charging_min_c         = 0,
+			.charging_max_c         = 60,
+			.discharging_min_c      = -20,
+			.discharging_max_c      = 60,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_C21N2018;
diff --git a/board/corori2/board.c b/board/corori2/board.c
new file mode 100644
index 0000000000..909099c6f8
--- /dev/null
+++ b/board/corori2/board.c
@@ -0,0 +1,732 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Waddledoo board-specific configuration */
+
+#include "adc_chip.h"
+#include "button.h"
+#include "cbi_fw_config.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "chipset.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "driver/accel_bma2x2.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "driver/bc12/pi3usb9201.h"
+#include "driver/charger/isl923x.h"
+#include "driver/retimer/nb7v904m.h"
+#include "driver/tcpm/raa489000.h"
+#include "driver/tcpm/tcpci.h"
+#include "driver/temp_sensor/thermistor.h"
+#include "driver/usb_mux/pi3usb3x532.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "motion_sense.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "stdbool.h"
+#include "switch.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "temp_sensor.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+#define INT_RECHECK_US 5000
+
+/* C0 interrupt line shared by BC 1.2 and charger */
+static void check_c0_line(void);
+DECLARE_DEFERRED(check_c0_line);
+
+static void notify_c0_chips(void)
+{
+	/*
+	 * The interrupt line is shared between the TCPC and BC 1.2 detection
+	 * chip.  Therefore we'll need to check both ICs.
+	 */
+	schedule_deferred_pd_interrupt(0);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+
+static void check_c0_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		notify_c0_chips();
+		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+	}
+}
+
+static void usb_c0_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c0_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c0_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+}
+
+/* C1 interrupt line shared by BC 1.2, TCPC, and charger */
+static void check_c1_line(void);
+DECLARE_DEFERRED(check_c1_line);
+
+static void notify_c1_chips(void)
+{
+	schedule_deferred_pd_interrupt(1);
+	usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+}
+
+static void check_c1_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips.
+	 */
+	if (!gpio_get_level(GPIO_SUB_C1_INT_EN_RAILS_ODL)) {
+		notify_c1_chips();
+		hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
+	}
+}
+
+static void sub_usb_c1_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c1_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c1_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
+}
+
+static void sub_hdmi_hpd_interrupt(enum gpio_signal s)
+{
+	int hdmi_hpd_odl = gpio_get_level(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL);
+
+	gpio_set_level(GPIO_EC_AP_USB_C1_HDMI_HPD, !hdmi_hpd_odl);
+}
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_1] = {
+		.name = "TEMP_SENSOR1",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_2] = {
+		.name = "TEMP_SENSOR2",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_SUB_ANALOG] = {
+		.name = "SUB_ANALOG",
+		.input_ch = NPCX_ADC_CH2,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_VSNS_PP3300_A] = {
+		.name = "PP3300_A_PGOOD",
+		.input_ch = NPCX_ADC_CH9,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* Thermistors */
+const struct temp_sensor_t temp_sensors[] = {
+	[ADC_TEMP_SENSOR_1] = { .name = "Memory",
+				.type = TEMP_SENSOR_TYPE_BOARD,
+				.read = get_temp_3v3_51k1_47k_4050b,
+				.idx = ADC_TEMP_SENSOR_1 },
+	[ADC_TEMP_SENSOR_2] = { .name = "Charger",
+				.type = TEMP_SENSOR_TYPE_BOARD,
+				.read = get_temp_3v3_51k1_47k_4050b,
+				.idx = ADC_TEMP_SENSOR_2 },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_MEMORY           \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(85), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(95), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_memory =
+	THERMAL_MEMORY;
+
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CHARGER          \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(80), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(85), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(55), \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_charger =
+	THERMAL_CHARGER;
+
+struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
+
+static void setup_thermal(void)
+{
+	thermal_params[ADC_TEMP_SENSOR_1] = thermal_memory;
+	thermal_params[ADC_TEMP_SENSOR_2] = thermal_charger;
+}
+
+void board_init(void)
+{
+	int on;
+
+	/* Enable C0 interrupt and check if it needs processing */
+	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
+	check_c0_line();
+
+	if (get_cbi_fw_config_db() == DB_1A_HDMI) {
+		/* Disable i2c on HDMI pins */
+		gpio_config_pin(MODULE_I2C, GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL,
+				0);
+		gpio_config_pin(MODULE_I2C, GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL,
+				0);
+
+		/* Set HDMI and sub-rail enables to output */
+		gpio_set_flags(GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL,
+			       chipset_in_state(CHIPSET_STATE_ON) ?
+				       GPIO_ODR_LOW :
+				       GPIO_ODR_HIGH);
+		gpio_set_flags(GPIO_SUB_C1_INT_EN_RAILS_ODL, GPIO_ODR_HIGH);
+
+		/* Select HDMI option */
+		gpio_set_level(GPIO_HDMI_SEL_L, 0);
+
+		/* Enable interrupt for passing through HPD */
+		gpio_enable_interrupt(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL);
+	} else {
+		/* Set SDA as an input */
+		gpio_set_flags(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL, GPIO_INPUT);
+
+		/* Enable C1 interrupt and check if it needs processing */
+		gpio_enable_interrupt(GPIO_SUB_C1_INT_EN_RAILS_ODL);
+		check_c1_line();
+	}
+	/* Enable gpio interrupt for base accelgyro sensor */
+	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
+
+	/* Turn on 5V if the system is on, otherwise turn it off. */
+	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
+			      CHIPSET_STATE_SOFT_OFF);
+	board_power_5v_enable(on);
+
+	/* Initialize THERMAL */
+	setup_thermal();
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+/* Enable HDMI any time the SoC is on */
+static void hdmi_enable(void)
+{
+	if (get_cbi_fw_config_db() == DB_1A_HDMI)
+		gpio_set_level(GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, hdmi_enable, HOOK_PRIO_DEFAULT);
+
+static void hdmi_disable(void)
+{
+	if (get_cbi_fw_config_db() == DB_1A_HDMI)
+		gpio_set_level(GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, hdmi_disable, HOOK_PRIO_DEFAULT);
+
+void board_hibernate(void)
+{
+	/*
+	 * Both charger ICs need to be put into their "low power mode" before
+	 * entering the Z-state.
+	 */
+	if (board_get_charger_chip_count() > 1)
+		raa489000_hibernate(1, true);
+	raa489000_hibernate(0, true);
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * TODO(b:147316511): Here we could issue a digital reset to the IC,
+	 * unsure if we actually want to do that or not yet.
+	 */
+}
+
+#ifdef BOARD_WADDLEDOO
+static void reconfigure_5v_gpio(void)
+{
+	/*
+	 * b/147257497: On early waddledoo boards, GPIO_EN_PP5000 was swapped
+	 * with GPIO_VOLUP_BTN_ODL. Therefore, we'll actually need to set that
+	 * GPIO instead for those boards.  Note that this breaks the volume up
+	 * button functionality.
+	 */
+	if (system_get_board_version() < 0) {
+		CPRINTS("old board - remapping 5V en");
+		gpio_set_flags(GPIO_VOLUP_BTN_ODL, GPIO_OUT_LOW);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, reconfigure_5v_gpio, HOOK_PRIO_INIT_I2C + 1);
+#endif /* BOARD_WADDLEDOO */
+
+static void set_5v_gpio(int level)
+{
+	int version;
+	enum gpio_signal gpio = GPIO_EN_PP5000;
+
+	/*
+	 * b/147257497: On early waddledoo boards, GPIO_EN_PP5000 was swapped
+	 * with GPIO_VOLUP_BTN_ODL. Therefore, we'll actually need to set that
+	 * GPIO instead for those boards.  Note that this breaks the volume up
+	 * button functionality.
+	 */
+	if (IS_ENABLED(BOARD_WADDLEDOO)) {
+		version = system_get_board_version();
+
+		/*
+		 * If the CBI EEPROM wasn't formatted, assume it's a very early
+		 * board.
+		 */
+		gpio = version < 0 ? GPIO_VOLUP_BTN_ODL : GPIO_EN_PP5000;
+	}
+
+	gpio_set_level(gpio, level);
+}
+
+__override void board_power_5v_enable(int enable)
+{
+	/*
+	 * Port 0 simply has a GPIO to turn on the 5V regulator, however, 5V is
+	 * generated locally on the sub board and we need to set the comparator
+	 * polarity on the sub board charger IC, or send enable signal to HDMI
+	 * DB.
+	 */
+	set_5v_gpio(!!enable);
+
+	if (get_cbi_fw_config_db() == DB_1A_HDMI) {
+		gpio_set_level(GPIO_SUB_C1_INT_EN_RAILS_ODL, !enable);
+	} else {
+		if (isl923x_set_comparator_inversion(1, !!enable))
+			CPRINTS("Failed to %sable sub rails!",
+				enable ? "en" : "dis");
+	}
+}
+
+__override uint8_t board_get_usb_pd_port_count(void)
+{
+	if (get_cbi_fw_config_db() == DB_1A_HDMI)
+		return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
+	else
+		return CONFIG_USB_PD_PORT_MAX_COUNT;
+}
+
+__override uint8_t board_get_charger_chip_count(void)
+{
+	if (get_cbi_fw_config_db() == DB_1A_HDMI)
+		return CHARGER_NUM - 1;
+	else
+		return CHARGER_NUM;
+}
+
+int board_is_sourcing_vbus(int port)
+{
+	int regval;
+
+	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
+	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count());
+	int i;
+	int old_port;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	old_port = charge_manager_get_active_charge_port();
+
+	CPRINTS("New chg p%d", port);
+
+	/* Disable all ports. */
+	if (port == CHARGE_PORT_NONE) {
+		for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+			tcpc_write(i, TCPC_REG_COMMAND,
+				   TCPC_REG_COMMAND_SNK_CTRL_LOW);
+			raa489000_enable_asgate(i, false);
+		}
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if port is sourcing VBUS. */
+	if (board_is_sourcing_vbus(port)) {
+		CPRINTS("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+		if (i == port)
+			continue;
+
+		if (tcpc_write(i, TCPC_REG_COMMAND,
+			       TCPC_REG_COMMAND_SNK_CTRL_LOW))
+			CPRINTS("p%d: sink path disable failed.", i);
+		raa489000_enable_asgate(i, false);
+	}
+
+	/*
+	 * Stop the charger IC from switching while changing ports.  Otherwise,
+	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
+	 */
+	if (old_port != CHARGE_PORT_NONE)
+		charger_discharge_on_ac(1);
+
+	/* Enable requested charge port. */
+	if (raa489000_enable_asgate(port, true) ||
+	    tcpc_write(port, TCPC_REG_COMMAND,
+		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
+		CPRINTS("p%d: sink path enable failed.", port);
+		charger_discharge_on_ac(0);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	/* Allow the charger IC to begin/continue switching. */
+	charger_discharge_on_ac(0);
+
+	return EC_SUCCESS;
+}
+
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	if (port < 0 || port > board_get_usb_pd_port_count())
+		return;
+
+	raa489000_set_output_current(port, rp);
+}
+
+/* Sensors */
+static struct mutex g_lid_mutex;
+static struct mutex g_base_mutex;
+
+/* Matrices to rotate accelerometers into the standard reference. */
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					     { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
+
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					      { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
+
+static struct accelgyro_saved_data_t g_bma253_data;
+static struct bmi_drv_data_t g_bmi160_data;
+
+struct motion_sensor_t motion_sensors[] = {
+	[LID_ACCEL] = {
+		.name = "Lid Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMA255,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &bma2x2_accel_drv,
+		.mutex = &g_lid_mutex,
+		.drv_data = &g_bma253_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
+		.rot_standard_ref = &lid_standard_ref,
+		.default_range = 2,
+		.min_frequency = BMA255_ACCEL_MIN_FREQ,
+		.max_frequency = BMA255_ACCEL_MAX_FREQ,
+		.config = {
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+		},
+	},
+	[BASE_ACCEL] = {
+		.name = "Base Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMI160,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &bmi160_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = &g_bmi160_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+		.rot_standard_ref = &base_standard_ref,
+		.default_range = 4,
+		.min_frequency = BMI_ACCEL_MIN_FREQ,
+		.max_frequency = BMI_ACCEL_MAX_FREQ,
+		.config = {
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 13000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+		},
+	},
+	[BASE_GYRO] = {
+		.name = "Base Gyro",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMI160,
+		.type = MOTIONSENSE_TYPE_GYRO,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &bmi160_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = &g_bmi160_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+		.default_range = 1000, /* dps */
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = BMI_GYRO_MIN_FREQ,
+		.max_frequency = BMI_GYRO_MAX_FREQ,
+	},
+};
+
+const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+				       int *ki_div, int *kd, int *kd_div)
+{
+	*kp = 1;
+	*kp_div = 20;
+	*ki = 1;
+	*ki_div = 250;
+	*kd = 0;
+	*kd_div = 1;
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	return pd_check_vbus_level(port, VBUS_PRESENT);
+}
+
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+
+	{
+		.i2c_port = I2C_PORT_SUB_USB_C1,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+};
+
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	{
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+		.flags = PI3USB9201_ALWAYS_POWERED,
+	},
+
+	{
+		.i2c_port = I2C_PORT_SUB_USB_C1,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+		.flags = PI3USB9201_ALWAYS_POWERED,
+	},
+};
+
+/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_KBLIGHT] = {
+		.channel = 3,
+		.flags = PWM_CONFIG_DSLEEP,
+		.freq = 10000,
+	},
+
+	[PWM_CH_LED1_AMBER] = {
+		.channel = 2,
+		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
+		.freq = 2400,
+	},
+
+	[PWM_CH_LED2_WHITE] = {
+		.channel = 0,
+		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
+		.freq = 2400,
+	}
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0,
+			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
+		},
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+		.drv = &raa489000_tcpm_drv,
+	},
+
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_SUB_USB_C1,
+			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
+		},
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+		.drv = &raa489000_tcpm_drv,
+	},
+};
+
+const struct usb_mux_chain usbc1_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = 1,
+			.i2c_port = I2C_PORT_SUB_USB_C1,
+			.i2c_addr_flags = NB7V904M_I2C_ADDR0,
+			.driver = &nb7v904m_usb_redriver_drv,
+		},
+};
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
+				.driver = &pi3usb3x532_usb_mux_driver,
+			},
+	},
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_SUB_USB_C1,
+				.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
+				.driver = &pi3usb3x532_usb_mux_driver,
+			},
+		.next = &usbc1_retimer,
+	}
+};
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+	int regval;
+
+	/*
+	 * The interrupt line is shared between the TCPC and BC1.2 detector IC.
+	 * Therefore, go out and actually read the alert registers to report the
+	 * alert status.
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
+			/* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */
+			if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0))
+				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
+
+			if (regval)
+				status |= PD_STATUS_TCPC_ALERT_0;
+		}
+	}
+
+	if (board_get_usb_pd_port_count() > 1 &&
+	    !gpio_get_level(GPIO_SUB_C1_INT_EN_RAILS_ODL)) {
+		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
+			/* TCPCI spec Rev 1.0 says to ignore bits 14:12. */
+			if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0))
+				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
+
+			if (regval)
+				status |= PD_STATUS_TCPC_ALERT_1;
+		}
+	}
+
+	return status;
+}
+
+/* This callback disables keyboard when convertibles are fully open */
+__override void lid_angle_peripheral_enable(int enable)
+{
+	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
+
+	/*
+	 * If the lid is in tablet position via other sensors,
+	 * ignore the lid angle, which might be faulty then
+	 * disable keyboard.
+	 */
+	if (tablet_get_mode())
+		enable = 0;
+
+	if (enable) {
+		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
+	} else {
+		/*
+		 * Ensure that the chipset is off before disabling the keyboard.
+		 * When the chipset is on, the EC keeps the keyboard enabled and
+		 * the AP decides whether to ignore input devices or not.
+		 */
+		if (!chipset_in_s0)
+			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
+	}
+}
diff --git a/board/corori2/board.h b/board/corori2/board.h
new file mode 100644
index 0000000000..5d4d810dd1
--- /dev/null
+++ b/board/corori2/board.h
@@ -0,0 +1,203 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Waddledoo board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#define VARIANT_DEDEDE_EC_NPCX796FC
+#include "baseboard.h"
+
+/*
+ * Keep the system unlocked in early development.
+ * TODO(b/151264302): Make sure to remove this before production!
+ */
+#define CONFIG_SYSTEM_UNLOCKED
+
+/* Save some flash space */
+#define CONFIG_CHIP_INIT_ROM_REGION
+#undef CONFIG_CONSOLE_CMDHELP
+#undef CONFIG_CONSOLE_HISTORY
+#define CONFIG_DEBUG_ASSERT_BRIEF
+#define CONFIG_USB_PD_DEBUG_LEVEL 0
+
+/* EC console commands */
+#define CONFIG_CMD_CHARGER_DUMP
+
+/* Remove default commands to free flash space */
+#undef CONFIG_CMD_ACCELSPOOF
+#undef CONFIG_CMD_BATTFAKE
+#undef CONFIG_CMD_GETTIME
+#undef CONFIG_CMD_I2C_SCAN
+#undef CONFIG_CMD_I2C_XFER
+#undef CONFIG_CMD_MEM
+
+/* Battery */
+#define CONFIG_BATTERY_FUEL_GAUGE
+
+/* Charger */
+#define CONFIG_CHARGER_RAA489000
+#define PD_MAX_VOLTAGE_MV 20000
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_OCPC_DEF_RBATT_MOHMS               \
+	22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \
+	    */
+#define CONFIG_OCPC
+#undef CONFIG_CHARGER_SINGLE_CHIP
+#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
+#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
+/*
+ * b/147463641: The charger IC seems to overdraw ~4%, therefore we
+ * reduce our target accordingly.
+ */
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 4
+
+/*
+ * GPIO for C1 interrupts, for baseboard use
+ *
+ * Note this line might already have its pull up disabled for HDMI DBs, but
+ * it should be fine to set again before z-state.
+ */
+#define GPIO_USB_C1_INT_ODL GPIO_SUB_C1_INT_EN_RAILS_ODL
+
+/* Keyboard */
+#define CONFIG_PWM_KBLIGHT
+
+/* LED */
+#define CONFIG_LED_PWM
+#define CONFIG_LED_PWM_COUNT 1
+#undef CONFIG_LED_PWM_NEAR_FULL_COLOR
+#undef CONFIG_LED_PWM_SOC_ON_COLOR
+#undef CONFIG_LED_PWM_SOC_SUSPEND_COLOR
+#undef CONFIG_LED_PWM_LOW_BATT_COLOR
+#define CONFIG_LED_PWM_NEAR_FULL_COLOR EC_LED_COLOR_WHITE
+#define CONFIG_LED_PWM_SOC_ON_COLOR EC_LED_COLOR_WHITE
+#define CONFIG_LED_PWM_SOC_SUSPEND_COLOR EC_LED_COLOR_WHITE
+#define CONFIG_LED_PWM_LOW_BATT_COLOR EC_LED_COLOR_AMBER
+
+/* PWM */
+#define CONFIG_PWM
+#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */
+
+/* Temp sensor */
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_THERMISTOR
+#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
+#define CONFIG_THROTTLE_AP
+#define CONFIG_CHIPSET_CAN_THROTTLE
+
+/* USB */
+#define CONFIG_BC12_DETECT_PI3USB9201
+#define CONFIG_USBC_RETIMER_NB7V904M
+
+/* USB PD */
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#define CONFIG_USB_PD_TCPM_RAA489000
+
+/* USB defines specific to external TCPCs */
+#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+#define CONFIG_USB_PD_VBUS_DETECT_TCPC
+#define CONFIG_USB_PD_DISCHARGE_TCPC
+#define CONFIG_USB_PD_TCPC_LOW_POWER
+
+/* Variant references the TCPCs to determine Vbus sourcing */
+#define CONFIG_USB_PD_5V_EN_CUSTOM
+
+#undef PD_POWER_SUPPLY_TURN_ON_DELAY
+#undef PD_POWER_SUPPLY_TURN_OFF_DELAY
+#undef CONFIG_USBC_VCONN_SWAP_DELAY_US
+/* 20% margin added for these timings */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 13080 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 16080 /* us */
+#undef CONFIG_USBC_VCONN_SWAP_DELAY_US
+#define CONFIG_USBC_VCONN_SWAP_DELAY_US 787 /* us */
+
+/* I2C configuration */
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
+#define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0
+/* TODO(b:147440290): Need to handle multiple charger ICs */
+#define I2C_PORT_CHARGER I2C_PORT_USB_C0
+
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */
+
+/*
+ * I2C pin names for baseboard
+ *
+ * Note: these lines will be set as i2c on start-up, but this should be
+ * okay since they're ODL.
+ */
+#define GPIO_EC_I2C_SUB_USB_C1_SCL GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL
+#define GPIO_EC_I2C_SUB_USB_C1_SDA GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL
+
+/* Sensors */
+#define CONFIG_ACCEL_BMA255 /* Lid accel */
+#define CONFIG_ACCELGYRO_BMI160 /* Base accel */
+
+/* Lid operates in forced mode, base in FIFO */
+#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
+#define CONFIG_ACCEL_FIFO
+#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */
+#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
+
+#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_UPDATE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+
+#define CONFIG_TABLET_MODE
+#define CONFIG_TABLET_MODE_SWITCH
+#define CONFIG_GMR_TABLET_MODE
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum chg_id {
+	CHARGER_PRIMARY,
+	CHARGER_SECONDARY,
+	CHARGER_NUM,
+};
+
+enum adc_channel {
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
+	ADC_SUB_ANALOG, /* ADC2 */
+	ADC_VSNS_PP3300_A, /* ADC9 */
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT };
+
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
+
+enum pwm_channel {
+	PWM_CH_KBLIGHT,
+	PWM_CH_LED1_AMBER,
+	PWM_CH_LED2_WHITE,
+	PWM_CH_COUNT,
+};
+
+/* List of possible batteries */
+enum battery_type {
+	BATTERY_C21N2018,
+	BATTERY_C21N2018_2ND,
+	BATTERY_TYPE_COUNT,
+};
+
+#endif /* !__ASSEMBLER__ */
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/corori2/build.mk b/board/corori2/build.mk
new file mode 100644
index 0000000000..1512a49379
--- /dev/null
+++ b/board/corori2/build.mk
@@ -0,0 +1,14 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx7
+CHIP_VARIANT:=npcx7m6fc
+BASEBOARD:=dedede
+
+board-y=board.o battery.o cbi_ssfc.o led.o usb_pd_policy.o
diff --git a/board/corori2/cbi_ssfc.c b/board/corori2/cbi_ssfc.c
new file mode 100644
index 0000000000..81f3ee0dad
--- /dev/null
+++ b/board/corori2/cbi_ssfc.c
@@ -0,0 +1,36 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi_ssfc.h"
+#include "common.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "hooks.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+/* Cache SSFC on init since we don't expect it to change in runtime */
+static union dedede_cbi_ssfc cached_ssfc;
+BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
+
+static void cbi_ssfc_init(void)
+{
+	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
+		/* Default to 0 when CBI isn't populated */
+		cached_ssfc.raw_value = 0;
+
+	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
+}
+DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
+
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
+{
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
+}
+
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
+{
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
+}
diff --git a/board/corori2/cbi_ssfc.h b/board/corori2/cbi_ssfc.h
new file mode 100644
index 0000000000..bf8853a43a
--- /dev/null
+++ b/board/corori2/cbi_ssfc.h
@@ -0,0 +1,59 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _DEDEDE_CBI_SSFC__H_
+#define _DEDEDE_CBI_SSFC__H_
+
+#include "stdint.h"
+
+/****************************************************************************
+ * Dedede CBI Second Source Factory Cache
+ */
+
+/*
+ * Base Sensor (Bits 0-2)
+ */
+enum ec_ssfc_base_sensor {
+	SSFC_SENSOR_BASE_DEFAULT = 0,
+	SSFC_SENSOR_BMI160 = 1,
+	SSFC_SENSOR_ICM426XX = 2,
+	SSFC_SENSOR_LSM6DSM = 3,
+	SSFC_SENSOR_ICM42607 = 4
+};
+
+/*
+ * Lid Sensor (Bits 3-5)
+ */
+enum ec_ssfc_lid_sensor {
+	SSFC_SENSOR_LID_DEFAULT = 0,
+	SSFC_SENSOR_BMA255 = 1,
+	SSFC_SENSOR_KX022 = 2,
+	SSFC_SENSOR_LIS2DWL = 3
+};
+
+union dedede_cbi_ssfc {
+	struct {
+		uint32_t base_sensor : 3;
+		uint32_t lid_sensor : 3;
+		uint32_t reserved_2 : 26;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Get the Base sensor type from SSFC_CONFIG.
+ *
+ * @return the Base sensor board type.
+ */
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
+
+/**
+ * Get the Lid sensor type from SSFC_CONFIG.
+ *
+ * @return the Lid sensor board type.
+ */
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
+
+#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/corori2/ec.tasklist b/board/corori2/ec.tasklist
new file mode 100644
index 0000000000..29666dd959
--- /dev/null
+++ b/board/corori2/ec.tasklist
@@ -0,0 +1,25 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/corori2/gpio.inc b/board/corori2/gpio.inc
new file mode 100644
index 0000000000..63b16a1bc3
--- /dev/null
+++ b/board/corori2/gpio.inc
@@ -0,0 +1,139 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first.
+ */
+
+/* Power Interrupts */
+GPIO_INT(SLP_S0_L,		 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,		 PIN(A, 5), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(SLP_S4_L,		 PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,		 PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(RSMRST_PWRGD_L,	 PIN(C, 6), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID1,	 PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(CPU_C10_GATE_L,	 PIN(6, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID0,	 PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, power_signal_interrupt)
+GPIO_INT(PG_VCCIO_EXT_OD,	 PIN(B, 0), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(PG_PP5000_U_OD,	 PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_DRAM_OD,		 PIN(E, 4), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(PG_PP1050_ST_OD,	 PIN(4, 2), GPIO_INT_BOTH, power_signal_interrupt)
+
+/* USB-C interrupts */
+GPIO_INT(USB_C0_INT_ODL,	 		PIN(6, 2), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt)
+GPIO_INT(SUB_C1_INT_EN_RAILS_ODL,		PIN(F, 5), GPIO_INT_FALLING | GPIO_PULL_UP, sub_usb_c1_interrupt) /* C1 interrupt OR 5V power en */
+GPIO_INT(EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL,	PIN(9, 1), GPIO_INT_BOTH, sub_hdmi_hpd_interrupt) /* C1 I2C SDA OR HDMI_HPD */
+
+/* Button interrupts */
+GPIO_INT(H1_EC_PWR_BTN_ODL,	 PIN(0, 1), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
+GPIO_INT(VOLDN_BTN_ODL,		 PIN(4, 0), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(VOLUP_BTN_ODL,		 PIN(7, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+
+/* Other interrupts */
+GPIO_INT(LID_OPEN,		 PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)
+GPIO_INT(EC_WP_OD,		 PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(BASE_SIXAXIS_INT_L,	 PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, bmi160_interrupt)
+GPIO_INT(LID_360_L,		 PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
+
+/* I2C Ports */
+GPIO(EC_I2C_EEPROM_SCL,			PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SDA,			PIN(B, 2), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SCL,		PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SDA,		PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,			PIN(B, 5), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SDA,			PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SCL,			PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SDA,			PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_SUB_C1_SCL_HDMI_EN_ODL,	PIN(9, 2), GPIO_INPUT) /* C1 I2C SCL OR HDMI en */
+
+/* Extra Sub-board I/O pins */
+GPIO(EC_SUB_IO_1,  PIN(3, 7), GPIO_OUT_LOW)
+GPIO(EC_SUB_IO_2,  PIN(3, 4), GPIO_OUT_LOW)
+
+/* Misc Enables */
+GPIO(EN_VCCIO_EXT,   PIN(6, 1), GPIO_OUT_LOW)
+/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
+GPIO(EN_VCCST,		PIN(A, 7), GPIO_INPUT)
+GPIO(EN_PP3300_PEN,	PIN(6, 3), GPIO_OUT_LOW)
+GPIO(EN_PP3300_A,	PIN(0, 3), GPIO_OUT_LOW)
+GPIO(EN_PP5000_U,	PIN(A, 4), GPIO_OUT_LOW)
+GPIO(EN_SLP_Z,		PIN(8, 3), GPIO_OUT_LOW)
+GPIO(EN_KB_BL,		PIN(6, 0), GPIO_OUT_LOW)
+GPIO(EN_BL_OD,		PIN(D, 3), GPIO_ODR_LOW)
+GPIO(IMVP9_PE,		PIN(E, 0), GPIO_OUT_LOW)
+GPIO(ECH1_PACKET_MODE,	PIN(7, 5), GPIO_OUT_LOW)
+
+/* Power Sequencing */
+GPIO(EC_AP_PSYS,	     PIN(B, 7), GPIO_OUT_LOW)
+GPIO(EC_AP_RSMRST_L,         PIN(A, 6), GPIO_OUT_LOW)
+GPIO(EC_AP_PWR_BTN_ODL,      PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(EC_AP_RTCRST,           PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_AP_WAKE_ODL,         PIN(7, 4), GPIO_ODR_HIGH)
+GPIO(EC_AP_DPWROK,	     PIN(A, 3), GPIO_OUT_LOW)
+GPIO(EC_AP_PCH_PWROK_OD,     PIN(9, 4), GPIO_ODR_LOW)
+GPIO(EC_AP_VCCST_PWRGD_OD,   PIN(B, 1), GPIO_ODR_LOW)
+GPIO(EC_AP_SYS_PWROK,	     PIN(0, 2), GPIO_OUT_LOW)
+GPIO(EC_AP_MKBP_INT_L,	     PIN(7, 0), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_ODL,	     PIN(F, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(EC_ENTERING_RW,	     PIN(E, 3), GPIO_OUT_LOW)
+GPIO(ALL_SYS_PWRGD,	     PIN(A, 0), GPIO_OUT_LOW)
+GPIO(SYS_RST_ODL,	     PIN(C, 5), GPIO_ODR_HIGH)
+GPIO(CCD_MODE_ODL,	     PIN(E, 5), GPIO_ODR_HIGH)
+
+GPIO(USB_C0_RST_ODL,	     PIN(9, 7), GPIO_OUT_HIGH) /* currently unused */
+GPIO(EC_AP_USB_C1_HDMI_HPD,  PIN(9, 6), GPIO_OUT_LOW)
+GPIO(EC_AP_USB_C0_HPD,	     PIN(9, 3), GPIO_OUT_LOW)
+GPIO(HDMI_SEL_L,	     PIN(7, 2), GPIO_OUT_HIGH)
+GPIO(EC_BATTERY_PRES_ODL,    PIN(E, 1), GPIO_INPUT)
+
+/*
+ * Waddledoo doesn't have these physical pins coming to the EC but uses other
+ * logic.
+ */
+UNIMPLEMENTED(AC_PRESENT)
+UNIMPLEMENTED(PG_EC_DSW_PWROK)
+UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
+
+/* Alternate Functions */
+/* ADC */
+ALTERNATE(PIN_MASK(F, BIT(0)), 0, MODULE_ADC, 0) /* ADC9 */
+ALTERNATE(PIN_MASK(4, 0x38), 0, MODULE_ADC, 0)   /* ADC0-2 */
+
+/* Keyboard */
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI0, KSI1 */
+ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI2-7 */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO0, KSO1 */
+ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO3-9 */
+ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO10-13 */
+ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO14 */
+GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW)	/* KSO2 inverted */
+
+/* PWM */
+ALTERNATE(PIN_MASK(C, 0x1C), 0, MODULE_PWM, 0)   /* PWM0-2 */
+ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0) /* PWM3 */
+
+/* UART */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)  /* UART1 */
+
+/* I2C */
+ALTERNATE(PIN_MASK(B, 0x3C), 0, MODULE_I2C, 0)   /* I2C7,I2C0 */
+ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)   /* I2C5 */
+ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)   /* I2C2, I2C1 SCL */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)   /* I2C1 SDA */
+
+/* NC pins, enable internal pull-up to avoid floating state. */
+GPIO(GPIO32_NC, PIN(3, 2), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO35_NC, PIN(3, 5), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO41_NC, PIN(4, 1), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO57_NC, PIN(5, 7), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO81_NC, PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO86_NC, PIN(8, 6), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOD0_NC, PIN(D, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOD1_NC, PIN(D, 1), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOD6_NC, PIN(D, 6), GPIO_INPUT | GPIO_PULL_UP)
diff --git a/board/corori2/led.c b/board/corori2/led.c
new file mode 100644
index 0000000000..71a8159a07
--- /dev/null
+++ b/board/corori2/led.c
@@ -0,0 +1,67 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Waddledoo specific PWM LED settings. */
+
+#include "common.h"
+#include "ec_commands.h"
+#include "led_pwm.h"
+#include "pwm.h"
+#include "util.h"
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_POWER_LED,
+};
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+/*
+ * We only have a white and an amber LED, so setting any other colour results in
+ * both LEDs being off.
+ */
+struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = {
+	/* Amber, White */
+	[EC_LED_COLOR_RED] = { 0, 0 },	   [EC_LED_COLOR_GREEN] = { 0, 0 },
+	[EC_LED_COLOR_BLUE] = { 0, 0 },	   [EC_LED_COLOR_YELLOW] = { 0, 0 },
+	[EC_LED_COLOR_WHITE] = { 0, 100 }, [EC_LED_COLOR_AMBER] = { 100, 0 },
+};
+
+/* One logical LED with amber and white channels. */
+struct pwm_led pwm_leds[CONFIG_LED_PWM_COUNT] = {
+	{
+		.ch0 = PWM_CH_LED1_AMBER,
+		.ch1 = PWM_CH_LED2_WHITE,
+		.ch2 = PWM_LED_NO_CHANNEL,
+		.enable = &pwm_enable,
+		.set_duty = &pwm_set_duty,
+	},
+};
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	memset(brightness_range, '\0',
+	       sizeof(*brightness_range) * EC_LED_COLOR_COUNT);
+	brightness_range[EC_LED_COLOR_AMBER] = 100;
+	brightness_range[EC_LED_COLOR_WHITE] = 100;
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	enum pwm_led_id pwm_id;
+
+	/* Convert ec_led_id to pwm_led_id. */
+	if (led_id == EC_LED_ID_POWER_LED)
+		pwm_id = PWM_LED0;
+	else
+		return EC_ERROR_UNKNOWN;
+
+	if (brightness[EC_LED_COLOR_WHITE])
+		set_pwm_led_color(pwm_id, EC_LED_COLOR_WHITE);
+	else if (brightness[EC_LED_COLOR_AMBER])
+		set_pwm_led_color(pwm_id, EC_LED_COLOR_AMBER);
+	else
+		/* Otherwise, the "color" is "off". */
+		set_pwm_led_color(pwm_id, -1);
+
+	return EC_SUCCESS;
+}
diff --git a/board/corori2/usb_pd_policy.c b/board/corori2/usb_pd_policy.c
new file mode 100644
index 0000000000..83c09bb99e
--- /dev/null
+++ b/board/corori2/usb_pd_policy.c
@@ -0,0 +1,61 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "driver/charger/isl923x_public.h"
+#include "driver/tcpm/tcpci.h"
+#include "usb_pd.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+int pd_check_vconn_swap(int port)
+{
+	/* Allow VCONN swaps if the AP is on. */
+	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
+}
+
+void pd_power_supply_reset(int port)
+{
+	/* Disable VBUS */
+	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	if (port >= board_get_usb_pd_port_count())
+		return EC_ERROR_INVAL;
+
+	/* Disable charging. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
+	if (rv)
+		return rv;
+
+	/* Our policy is not to source VBUS when the AP is off. */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	/* Provide Vbus. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
+	if (rv)
+		return rv;
+
+	rv = raa489000_enable_asgate(port, true);
+	if (rv)
+		return rv;
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
diff --git a/board/corori2/vif_override.xml b/board/corori2/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/corori2/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/flapjack_scp b/board/corsola_scp
similarity index 100%
rename from board/flapjack_scp
rename to board/corsola_scp
diff --git a/board/cozmo b/board/cozmo
new file mode 120000
index 0000000000..9ed6f26875
--- /dev/null
+++ b/board/cozmo
@@ -0,0 +1 @@
+icarus
\ No newline at end of file
diff --git a/board/cret/battery.c b/board/cret/battery.c
new file mode 100644
index 0000000000..27bfed5355
--- /dev/null
+++ b/board/cret/battery.c
@@ -0,0 +1,658 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "battery_smart.h"
+#include "charge_state.h"
+#include "common.h"
+#include "util.h"
+
+/*
+ * Battery info for all waddledoo battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	/* BYD Battery Information */
+	[BATTERY_BYD_1VX1H] = {
+		.fuel_gauge = {
+			.manuf_name = "BYD",
+			.device_name = "DELL 1VX1H",
+			.ship_mode = {
+				.wb_support = 1,
+				.reg_addr = 0x44,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr       = 0x0,
+				.reg_mask       = 0x8000,
+				.disconnect_val = 0x8000,
+				.cfet_mask = 0x4000,
+				.cfet_off_val = 0x4000,
+			}
+		},
+		.batt_info = {
+			.voltage_max          = 13200,    /* mV */
+			.voltage_normal       = 11400,
+			.voltage_min          = 9000,
+			.precharge_current    = 256,       /* mA */
+			.start_charging_min_c = -3,
+			.start_charging_max_c = 50,
+			.charging_min_c       = -3,
+			.charging_max_c       = 60,
+			.discharging_min_c    = -5,
+			.discharging_max_c    = 70,
+		},
+	},
+
+	/* BYD Battery Information */
+	[BATTERY_BYD_YT39X] = {
+		.fuel_gauge = {
+			.manuf_name = "BYD",
+			.device_name = "DELL YT39X",
+			.ship_mode = {
+				.wb_support = 1,
+				.reg_addr = 0x44,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr       = 0x0,
+				.reg_mask       = 0x8000,
+				.disconnect_val = 0x8000,
+				.cfet_mask = 0x4000,
+				.cfet_off_val = 0x4000,
+			}
+		},
+		.batt_info = {
+			.voltage_max          = 13200,    /* mV */
+			.voltage_normal       = 11400,
+			.voltage_min          = 9000,
+			.precharge_current    = 256,       /* mA */
+			.start_charging_min_c = -3,
+			.start_charging_max_c = 50,
+			.charging_min_c       = -3,
+			.charging_max_c       = 60,
+			.discharging_min_c    = -5,
+			.discharging_max_c    = 70,
+		},
+	},
+
+	/* BYD Battery Information */
+	[BATTERY_BYD_X0Y5M] = {
+		.fuel_gauge = {
+			.manuf_name = "BYD",
+			.device_name = "DELL X0Y5M",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr       = 0x043,
+				.reg_mask       = 0x0001,
+				.disconnect_val = 0x0000,
+				.cfet_mask = 0x0002,
+				.cfet_off_val = 0x0000,
+			}
+		},
+		.batt_info = {
+			.voltage_max          = 13200,    /* mV */
+			.voltage_normal       = 11400,
+			.voltage_min          = 9000,
+			.precharge_current    = 256,       /* mA */
+			.start_charging_min_c = -3,
+			.start_charging_max_c = 50,
+			.charging_min_c       = -3,
+			.charging_max_c       = 60,
+			.discharging_min_c    = -5,
+			.discharging_max_c    = 70,
+		},
+	},
+
+	/* LGC Battery Information */
+	[BATTERY_LGC_FDRHM] = {
+		.fuel_gauge = {
+			.manuf_name = "LGC-LGC3.65",
+			.device_name = "DELL FDRHM",
+			.ship_mode = {
+				.wb_support = 1,
+				.reg_addr = 0x44,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr       = 0x0,
+				.reg_mask       = 0x8000,
+				.disconnect_val = 0x8000,
+				.cfet_mask = 0x4000,
+				.cfet_off_val = 0x4000,
+			}
+		},
+		.batt_info = {
+			.voltage_max          = 13200,    /* mV */
+			.voltage_normal       = 11460,
+			.voltage_min          = 9000,
+			.precharge_current    = 256,       /* mA */
+			.start_charging_min_c = -3,
+			.start_charging_max_c = 50,
+			.charging_min_c       = -3,
+			.charging_max_c       = 60,
+			.discharging_min_c    = -5,
+			.discharging_max_c    = 70,
+		},
+	},
+
+	/* LGC Battery Information */
+	[BATTERY_LGC_8GHCX] = {
+		.fuel_gauge = {
+			.manuf_name = "LGC-LGC3.65",
+			.device_name = "DELL 8GHCX",
+			.ship_mode = {
+				.wb_support = 1,
+				.reg_addr = 0x44,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr       = 0x0,
+				.reg_mask       = 0x8000,
+				.disconnect_val = 0x8000,
+				.cfet_mask = 0x4000,
+				.cfet_off_val = 0x4000,
+			}
+		},
+		.batt_info = {
+			.voltage_max          = 13200,    /* mV */
+			.voltage_normal       = 11460,
+			.voltage_min          = 9000,
+			.precharge_current    = 256,       /* mA */
+			.start_charging_min_c = -3,
+			.start_charging_max_c = 50,
+			.charging_min_c       = -3,
+			.charging_max_c       = 60,
+			.discharging_min_c    = -5,
+			.discharging_max_c    = 70,
+		},
+	},
+
+
+	/* SWD-ATL Battery Information */
+	[BATTERY_SWD_ATL_WJPC4] = {
+		.fuel_gauge = {
+			.manuf_name = "SWD-ATL3.618",
+			.device_name = "DELL WJPC4",
+			.ship_mode = {
+				.wb_support = 1,
+				.reg_addr = 0x44,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr       = 0x0,
+				.reg_mask       = 0x8000,
+				.disconnect_val = 0x8000,
+				.cfet_mask = 0x4000,
+				.cfet_off_val = 0x4000,
+			}
+		},
+		.batt_info = {
+			.voltage_max          = 13200,    /* mV */
+			.voltage_normal       = 11400,
+			.voltage_min          = 9000,
+			.precharge_current    = 256,       /* mA */
+			.start_charging_min_c = -3,
+			.start_charging_max_c = 50,
+			.charging_min_c       = -3,
+			.charging_max_c       = 60,
+			.discharging_min_c    = -5,
+			.discharging_max_c    = 70,
+		},
+	},
+
+	/* SWD-ATL Battery Information */
+	[BATTERY_SWD_ATL_CTGKT] = {
+		.fuel_gauge = {
+			.manuf_name = "SWD-ATL3.618",
+			.device_name = "DELL CTGKT",
+			.ship_mode = {
+				.wb_support = 1,
+				.reg_addr = 0x44,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr       = 0x0,
+				.reg_mask       = 0x8000,
+				.disconnect_val = 0x8000,
+				.cfet_mask = 0x4000,
+				.cfet_off_val = 0x4000,
+			}
+		},
+		.batt_info = {
+			.voltage_max          = 13200,    /* mV */
+			.voltage_normal       = 11400,
+			.voltage_min          = 9000,
+			.precharge_current    = 256,       /* mA */
+			.start_charging_min_c = -3,
+			.start_charging_max_c = 50,
+			.charging_min_c       = -3,
+			.charging_max_c       = 60,
+			.discharging_min_c    = -5,
+			.discharging_max_c    = 70,
+		},
+	},
+
+	/* SWD-COS Battery Information */
+	[BATTERY_SWD_COS_WJPC4] = {
+		.fuel_gauge = {
+			.manuf_name = "SWD-COS3.634",
+			.device_name = "DELL WJPC4",
+			.ship_mode = {
+				.wb_support = 1,
+				.reg_addr = 0x44,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr       = 0x0,
+				.reg_mask       = 0x8000,
+				.disconnect_val = 0x8000,
+				.cfet_mask = 0x4000,
+				.cfet_off_val = 0x4000,
+			}
+		},
+		.batt_info = {
+			.voltage_max          = 13200,    /* mV */
+			.voltage_normal       = 11400,
+			.voltage_min          = 9000,
+			.precharge_current    = 256,       /* mA */
+			.start_charging_min_c = -3,
+			.start_charging_max_c = 50,
+			.charging_min_c       = -3,
+			.charging_max_c       = 60,
+			.discharging_min_c    = -5,
+			.discharging_max_c    = 70,
+		},
+	},
+
+	/* SWD-COS Battery Information */
+	[BATTERY_SWD_COS_CTGKT] = {
+		.fuel_gauge = {
+			.manuf_name = "SWD-COS3.634",
+			.device_name = "DELL CTGKT",
+			.ship_mode = {
+				.wb_support = 1,
+				.reg_addr = 0x44,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr       = 0x0,
+				.reg_mask       = 0x8000,
+				.disconnect_val = 0x8000,
+				.cfet_mask = 0x4000,
+				.cfet_off_val = 0x4000,
+			}
+		},
+		.batt_info = {
+			.voltage_max          = 13200,    /* mV */
+			.voltage_normal       = 11400,
+			.voltage_min          = 9000,
+			.precharge_current    = 256,       /* mA */
+			.start_charging_min_c = -3,
+			.start_charging_max_c = 50,
+			.charging_min_c       = -3,
+			.charging_max_c       = 60,
+			.discharging_min_c    = -5,
+			.discharging_max_c    = 70,
+		},
+	},
+
+	/* SMP-ATL Battery Information */
+	[BATTERY_SMP_ATL_VM732] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP-ATL-3.61",
+			.device_name = "DELL VM732",
+			.ship_mode = {
+				.wb_support = 1,
+				.reg_addr = 0x44,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr       = 0x0,
+				.reg_mask       = 0x8000,
+				.disconnect_val = 0x8000,
+				.cfet_mask = 0x4000,
+				.cfet_off_val = 0x4000,
+			}
+		},
+		.batt_info = {
+			.voltage_max          = 13200,    /* mV */
+			.voltage_normal       = 11400,
+			.voltage_min          = 9000,
+			.precharge_current    = 256,       /* mA */
+			.start_charging_min_c = -3,
+			.start_charging_max_c = 50,
+			.charging_min_c       = -3,
+			.charging_max_c       = 60,
+			.discharging_min_c    = -5,
+			.discharging_max_c    = 70,
+		},
+	},
+
+	/* SMP-ATL Battery Information */
+	[BATTERY_SMP_ATL_26JGK] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP-ATL-3.61",
+			.device_name = "DELL 26JGK",
+			.ship_mode = {
+				.wb_support = 1,
+				.reg_addr = 0x44,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr       = 0x0,
+				.reg_mask       = 0x8000,
+				.disconnect_val = 0x8000,
+				.cfet_mask = 0x4000,
+				.cfet_off_val = 0x4000,
+			}
+		},
+		.batt_info = {
+			.voltage_max          = 13200,    /* mV */
+			.voltage_normal       = 11400,
+			.voltage_min          = 9000,
+			.precharge_current    = 256,       /* mA */
+			.start_charging_min_c = -3,
+			.start_charging_max_c = 50,
+			.charging_min_c       = -3,
+			.charging_max_c       = 60,
+			.discharging_min_c    = -5,
+			.discharging_max_c    = 70,
+		},
+	},
+
+	/* SMP-ATL Battery Information */
+	[BATTERY_SMP_ATL_RF9H3] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP-ATL-3.61",
+			.device_name = "DELL RF9H3",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr       = 0x43,
+				.reg_mask       = 0x0001,
+				.disconnect_val = 0x0000,
+				.cfet_mask = 0x0002,
+				.cfet_off_val = 0x0000,
+			}
+		},
+		.batt_info = {
+			.voltage_max          = 13200,    /* mV */
+			.voltage_normal       = 11400,
+			.voltage_min          = 9000,
+			.precharge_current    = 256,       /* mA */
+			.start_charging_min_c = -3,
+			.start_charging_max_c = 50,
+			.charging_min_c       = -3,
+			.charging_max_c       = 60,
+			.discharging_min_c    = -5,
+			.discharging_max_c    = 70,
+		},
+	},
+
+	/* SMP-COS Battery Information */
+	[BATTERY_SMP_COS_VM732] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP-COS3.63",
+			.device_name = "DELL VM732",
+			.ship_mode = {
+				.wb_support = 1,
+				.reg_addr = 0x44,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr       = 0x0,
+				.reg_mask       = 0x8000,
+				.disconnect_val = 0x8000,
+				.cfet_mask = 0x4000,
+				.cfet_off_val = 0x4000,
+			}
+		},
+		.batt_info = {
+			.voltage_max          = 13200,    /* mV */
+			.voltage_normal       = 11400,
+			.voltage_min          = 9000,
+			.precharge_current    = 256,       /* mA */
+			.start_charging_min_c = -3,
+			.start_charging_max_c = 50,
+			.charging_min_c       = -3,
+			.charging_max_c       = 60,
+			.discharging_min_c    = -5,
+			.discharging_max_c    = 70,
+		},
+	},
+
+	/* SMP-COS Battery Information */
+	[BATTERY_SMP_COS_26JGK] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP-COS3.63",
+			.device_name = "DELL 26JGK",
+			.ship_mode = {
+				.wb_support = 1,
+				.reg_addr = 0x44,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr       = 0x0,
+				.reg_mask       = 0x8000,
+				.disconnect_val = 0x8000,
+				.cfet_mask = 0x4000,
+				.cfet_off_val = 0x4000,
+			}
+		},
+		.batt_info = {
+			.voltage_max          = 13200,    /* mV */
+			.voltage_normal       = 11400,
+			.voltage_min          = 9000,
+			.precharge_current    = 256,       /* mA */
+			.start_charging_min_c = -3,
+			.start_charging_max_c = 50,
+			.charging_min_c       = -3,
+			.charging_max_c       = 60,
+			.discharging_min_c    = -5,
+			.discharging_max_c    = 70,
+		},
+	},
+	/* SMP-COS Battery Information */
+	[BATTERY_SMP_COS_RF9H3] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP-COS3.63",
+			.device_name = "DELL RF9H3",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr       = 0x43,
+				.reg_mask       = 0x0001,
+				.disconnect_val = 0x0000,
+				.cfet_mask = 0x0002,
+				.cfet_off_val = 0x0000,
+			}
+		},
+		.batt_info = {
+			.voltage_max          = 13200,    /* mV */
+			.voltage_normal       = 11400,
+			.voltage_min          = 9000,
+			.precharge_current    = 256,       /* mA */
+			.start_charging_min_c = -3,
+			.start_charging_max_c = 50,
+			.charging_min_c       = -3,
+			.charging_max_c       = 60,
+			.discharging_min_c    = -5,
+			.discharging_max_c    = 70,
+		},
+	},
+
+	/* BYD 16DPHYMD Battery Information */
+	[BATTERY_BYD16] = {
+		.fuel_gauge = {
+			.manuf_name = "BYD-BYD3.685",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr = 0x043,
+				.reg_mask = 0x0001,
+				.disconnect_val = 0x000,
+				.cfet_mask = 0x0002,
+				.cfet_off_val = 0x0000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13200, /* mV */
+			.voltage_normal		= 11400, /* mV */
+			.voltage_min		= 9000, /* mV */
+			.precharge_current	= 256,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= 0,
+			.discharging_max_c	= 70,
+		},
+	},
+
+	/* LGC Battery Information */
+	[BATTERY_LGC3] = {
+		.fuel_gauge = {
+			.manuf_name = "LGC-LGC3.553",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr       = 0x0,
+				.reg_mask       = 0x8000,
+				.disconnect_val = 0x8000,
+				.cfet_mask = 0x4000,
+				.cfet_off_val = 0x4000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13200, /* mV */
+			.voltage_normal		= 11400, /* mV */
+			.voltage_min		= 9000, /* mV */
+			.precharge_current	= 256,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 70,
+		},
+	},
+
+	/* SIMPLO Battery Information */
+	[BATTERY_SIMPLO] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP-SDI3.72",
+			.ship_mode = {
+				.reg_addr = 0x0,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr = 0x043,
+				.reg_mask = 0x0001,
+				.disconnect_val = 0x000,
+				.cfet_mask = 0x0002,
+				.cfet_off_val = 0x0000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13200, /* mV */
+			.voltage_normal		= 11400, /* mV */
+			.voltage_min		= 9000, /* mV */
+			.precharge_current	= 256,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 70,
+		},
+	},
+
+	/* SIMPLO-LISHEN 7T0D3YMD Battery Information */
+	[BATTERY_SIMPLO_LS] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP-LS3.66",
+			.ship_mode = {
+				.reg_addr = 0x0,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr = 0x043,
+				.reg_mask = 0x0001,
+				.disconnect_val = 0x000,
+				.cfet_mask = 0x0002,
+				.cfet_off_val = 0x0000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13200, /* mV */
+			.voltage_normal		= 11400, /* mV */
+			.voltage_min		= 9000, /* mV */
+			.precharge_current	= 256,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= 0,
+			.discharging_max_c	= 70,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_BYD_1VX1H;
+
+int charger_profile_override(struct charge_state_data *curr)
+{
+	if (chipset_in_state(CHIPSET_STATE_ON)) {
+		curr->requested_current =
+			MIN(curr->requested_current, CHARGING_CURRENT_1100MA);
+	}
+
+	return 0;
+}
+
+enum ec_status charger_profile_override_get_param(uint32_t param,
+						  uint32_t *value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+enum ec_status charger_profile_override_set_param(uint32_t param,
+						  uint32_t value)
+{
+	return EC_RES_INVALID_PARAM;
+}
diff --git a/board/cret/board.c b/board/cret/board.c
new file mode 100644
index 0000000000..59edd8145a
--- /dev/null
+++ b/board/cret/board.c
@@ -0,0 +1,585 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Waddledoo board-specific configuration */
+
+#include "adc_chip.h"
+#include "button.h"
+#include "cbi_fw_config.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "chipset.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "driver/accel_lis2dh.h"
+#include "driver/accelgyro_lsm6dso.h"
+#include "driver/bc12/pi3usb9201.h"
+#include "driver/charger/isl923x.h"
+#include "driver/tcpm/raa489000.h"
+#include "driver/tcpm/tcpci.h"
+#include "driver/temp_sensor/thermistor.h"
+#include "driver/usb_mux/pi3usb3x532.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "keyboard_8042.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "motion_sense.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "stdbool.h"
+#include "switch.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "temp_sensor.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+#define INT_RECHECK_US 5000
+
+static void fw_config_tablet_mode(void);
+/* C0 interrupt line shared by BC 1.2 and charger */
+static void check_c0_line(void);
+DECLARE_DEFERRED(check_c0_line);
+
+static void notify_c0_chips(void)
+{
+	/*
+	 * The interrupt line is shared between the TCPC and BC 1.2 detection
+	 * chip.  Therefore we'll need to check both ICs.
+	 */
+	schedule_deferred_pd_interrupt(0);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+
+static void check_c0_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		notify_c0_chips();
+		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+	}
+}
+
+static void usb_c0_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c0_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c0_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+}
+
+static void sub_hdmi_hpd_interrupt(enum gpio_signal s)
+{
+	int hdmi_hpd_odl = gpio_get_level(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL);
+
+	gpio_set_level(GPIO_EC_AP_USB_C1_HDMI_HPD, !hdmi_hpd_odl);
+}
+
+static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
+{
+	cprints(CC_USBPD, "C0: CC OVP, SBU OVP, or thermal event");
+	pd_handle_cc_overvoltage(0);
+}
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_1] = {
+		.name = "TEMP_SENSOR1",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_2] = {
+		.name = "TEMP_SENSOR2",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_VSNS_PP3300_A] = {
+		.name = "PP3300_A_PGOOD",
+		.input_ch = NPCX_ADC_CH9,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+void board_init(void)
+{
+	int on;
+
+	/* Enable C0 interrupt and check if it needs processing */
+	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
+	check_c0_line();
+
+	/* Enable interrupt for passing through HPD */
+	gpio_enable_interrupt(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL);
+
+	fw_config_tablet_mode();
+
+	/* Turn on 5V if the system is on, otherwise turn it off. */
+	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
+			      CHIPSET_STATE_SOFT_OFF);
+	board_power_5v_enable(on);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+/* Enable HDMI any time the SoC is on */
+static void hdmi_enable(void)
+{
+	if (get_cbi_fw_config_hdmi() == HDMI_PRESENT) {
+		gpio_set_level(GPIO_EC_HDMI_EN_ODL, 0);
+		gpio_set_level(GPIO_HDMI_PP3300_EN, 1);
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, hdmi_enable, HOOK_PRIO_DEFAULT);
+
+static void hdmi_disable(void)
+{
+	if (get_cbi_fw_config_hdmi() == HDMI_PRESENT) {
+		gpio_set_level(GPIO_EC_HDMI_EN_ODL, 1);
+		gpio_set_level(GPIO_HDMI_PP3300_EN, 0);
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, hdmi_disable, HOOK_PRIO_DEFAULT);
+
+void board_hibernate(void)
+{
+	/*
+	 * Both charger ICs need to be put into their "low power mode" before
+	 * entering the Z-state.
+	 */
+	if (board_get_charger_chip_count() > 1)
+		raa489000_hibernate(1, true);
+	raa489000_hibernate(0, true);
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * TODO(b:147316511): Here we could issue a digital reset to the IC,
+	 * unsure if we actually want to do that or not yet.
+	 */
+}
+
+#ifdef BOARD_WADDLEDOO
+static void reconfigure_5v_gpio(void)
+{
+	/*
+	 * b/147257497: On early waddledoo boards, GPIO_EN_PP5000 was swapped
+	 * with GPIO_VOLUP_BTN_ODL. Therefore, we'll actually need to set that
+	 * GPIO instead for those boards.  Note that this breaks the volume up
+	 * button functionality.
+	 */
+	if (system_get_board_version() < 0) {
+		CPRINTS("old board - remapping 5V en");
+		gpio_set_flags(GPIO_VOLUP_BTN_ODL, GPIO_OUT_LOW);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, reconfigure_5v_gpio, HOOK_PRIO_INIT_I2C + 1);
+#endif /* BOARD_WADDLEDOO */
+
+static void set_5v_gpio(int level)
+{
+	gpio_set_level(GPIO_EN_PP5000, level);
+	gpio_set_level(GPIO_EN_USB_A0_VBUS, level);
+}
+
+__override void board_power_5v_enable(int enable)
+{
+	/*
+	 * Port 0 simply has a GPIO to turn on the 5V regulator, however, 5V is
+	 * generated locally on the sub board and we need to set the comparator
+	 * polarity on the sub board charger IC, or send enable signal to HDMI
+	 * DB.
+	 */
+	set_5v_gpio(!!enable);
+}
+
+__override uint8_t board_get_usb_pd_port_count(void)
+{
+	return CONFIG_USB_PD_PORT_MAX_COUNT;
+}
+
+__override uint8_t board_get_charger_chip_count(void)
+{
+	return CHARGER_NUM;
+}
+
+int board_is_sourcing_vbus(int port)
+{
+	int regval;
+
+	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
+	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count());
+	int i;
+	int old_port;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	old_port = charge_manager_get_active_charge_port();
+
+	CPRINTS("New chg p%d", port);
+
+	/* Disable all ports. */
+	if (port == CHARGE_PORT_NONE) {
+		for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+			tcpc_write(i, TCPC_REG_COMMAND,
+				   TCPC_REG_COMMAND_SNK_CTRL_LOW);
+			raa489000_enable_asgate(i, false);
+		}
+		return EC_SUCCESS;
+	}
+
+	/* Check if port is sourcing VBUS. */
+	if (board_is_sourcing_vbus(port)) {
+		CPRINTS("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+		if (i == port)
+			continue;
+
+		if (tcpc_write(i, TCPC_REG_COMMAND,
+			       TCPC_REG_COMMAND_SNK_CTRL_LOW))
+			CPRINTS("p%d: sink path disable failed.", i);
+		raa489000_enable_asgate(i, false);
+	}
+
+	/*
+	 * Stop the charger IC from switching while changing ports.  Otherwise,
+	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
+	 */
+	if (old_port != CHARGE_PORT_NONE)
+		charger_discharge_on_ac(1);
+
+	/* Enable requested charge port. */
+	if (raa489000_enable_asgate(port, true) ||
+	    tcpc_write(port, TCPC_REG_COMMAND,
+		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
+		CPRINTS("p%d: sink path enable failed.", port);
+		charger_discharge_on_ac(0);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	/* Allow the charger IC to begin/continue switching. */
+	charger_discharge_on_ac(0);
+
+	return EC_SUCCESS;
+}
+
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	if (port < 0 || port > board_get_usb_pd_port_count())
+		return;
+
+	raa489000_set_output_current(port, rp);
+}
+
+/* Sensors */
+static struct mutex g_lid_mutex;
+static struct mutex g_base_mutex;
+
+/* Matrices to rotate accelerometers into the standard reference. */
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					     { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
+
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					      { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
+
+static struct stprivate_data g_lis2dh_data;
+static struct lsm6dso_data lsm6dso_data;
+
+struct motion_sensor_t motion_sensors[] = {
+	[LID_ACCEL] = {
+		.name = "Lid Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LIS2DE,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &lis2dh_drv,
+		.mutex = &g_lid_mutex,
+		.drv_data = &g_lis2dh_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LIS2DH_ADDR1_FLAGS,
+		.rot_standard_ref = &lid_standard_ref,
+		.default_range = 2,
+		.min_frequency = LIS2DH_ODR_MIN_VAL,
+		.max_frequency = LIS2DH_ODR_MAX_VAL,
+		.config = {
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+		},
+	},
+	[BASE_ACCEL] = {
+		.name = "Base Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LSM6DSO,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &lsm6dso_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = LSM6DSO_ST_DATA(lsm6dso_data,
+				MOTIONSENSE_TYPE_ACCEL),
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LSM6DSO_ADDR0_FLAGS,
+		.rot_standard_ref = &base_standard_ref,
+		.default_range = 4,
+		.min_frequency = LSM6DSO_ODR_MIN_VAL,
+		.max_frequency = LSM6DSO_ODR_MAX_VAL,
+		.config = {
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 13000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+		},
+	},
+	[BASE_GYRO] = {
+		.name = "Base Gyro",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LSM6DSO,
+		.type = MOTIONSENSE_TYPE_GYRO,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &lsm6dso_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = LSM6DSO_ST_DATA(lsm6dso_data,
+				MOTIONSENSE_TYPE_GYRO),
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LSM6DSO_ADDR0_FLAGS,
+		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = LSM6DSO_ODR_MIN_VAL,
+		.max_frequency = LSM6DSO_ODR_MAX_VAL,
+	},
+};
+
+unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+/* Thermistors */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Charger",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+				       int *ki_div, int *kd, int *kd_div)
+{
+	*kp = 1;
+	*kp_div = 20;
+	*ki = 1;
+	*ki_div = 250;
+	*kd = 0;
+	*kd_div = 1;
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	return pd_check_vbus_level(port, VBUS_PRESENT);
+}
+
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+};
+
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	{
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+		.flags = PI3USB9201_ALWAYS_POWERED,
+	},
+};
+
+/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_KBLIGHT] = {
+		.channel = 3,
+		.flags = PWM_CONFIG_DSLEEP,
+		.freq = 10000,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0,
+			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
+		},
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+		.drv = &raa489000_tcpm_drv,
+	},
+};
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
+				.driver = &pi3usb3x532_usb_mux_driver,
+			},
+	},
+};
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+	int regval;
+
+	/*
+	 * The interrupt line is shared between the TCPC and BC1.2 detector IC.
+	 * Therefore, go out and actually read the alert registers to report the
+	 * alert status.
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
+			/* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */
+			if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0))
+				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
+
+			if (regval)
+				status |= PD_STATUS_TCPC_ALERT_0;
+		}
+	}
+
+	return status;
+}
+
+/* This callback disables keyboard when convertibles are fully open */
+__override void lid_angle_peripheral_enable(int enable)
+{
+	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
+
+	/*
+	 * If the lid is in tablet position via other sensors,
+	 * ignore the lid angle, which might be faulty then
+	 * disable keyboard.
+	 */
+	if (tablet_get_mode())
+		enable = 0;
+
+	if (enable) {
+		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
+	} else {
+		/*
+		 * Ensure that the chipset is off before disabling the keyboard.
+		 * When the chipset is on, the EC keeps the keyboard enabled and
+		 * the AP decides whether to ignore input devices or not.
+		 */
+		if (!chipset_in_s0)
+			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
+	}
+}
+
+/* Keyboard scan setting */
+static const struct ec_response_keybd_config cret_keybd = {
+	/* Default Chromeos keyboard config */
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_FORWARD,		/* T2 */
+		TK_REFRESH,		/* T3 */
+		TK_FULLSCREEN,		/* T4 */
+		TK_OVERVIEW,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	/* No function keys, no numeric keypad, has screenlock key */
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &cret_keybd;
+}
+
+static void fw_config_tablet_mode(void)
+{
+	if (get_cbi_fw_config_tablet_mode() == TABLET_MODE_PRESENT) {
+		motion_sensor_count = ARRAY_SIZE(motion_sensors);
+		/* Enable Base Accel interrupt */
+		gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
+	} else {
+		motion_sensor_count = 0;
+		gmr_tablet_switch_disable();
+		/* Base accel is not stuffed, don't allow line to float */
+		gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L,
+			       GPIO_INPUT | GPIO_PULL_DOWN);
+	}
+}
+
+static void board_extpower(void)
+{
+	int extpower_present;
+
+	if (pd_is_connected(0))
+		extpower_present = extpower_is_present();
+	else
+		extpower_present = 0;
+
+	gpio_set_level(GPIO_EC_ACOK_OTG, extpower_present);
+}
+DECLARE_HOOK(HOOK_AC_CHANGE, board_extpower, HOOK_PRIO_DEFAULT);
diff --git a/board/cret/board.h b/board/cret/board.h
new file mode 100644
index 0000000000..9dc2edb265
--- /dev/null
+++ b/board/cret/board.h
@@ -0,0 +1,180 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Waddledoo board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#define VARIANT_DEDEDE_EC_NPCX796FC
+#include "baseboard.h"
+
+/* Save some flash space */
+#define CONFIG_CHIP_INIT_ROM_REGION
+#define CONFIG_DEBUG_ASSERT_BRIEF
+
+/* EC console commands */
+#define CONFIG_CMD_TCPC_DUMP
+#define CONFIG_CMD_CHARGER_DUMP
+#undef CONFIG_CMD_POWERINDEBUG
+#undef CONFIG_I2C_DEBUG
+
+/* Battery */
+#define CONFIG_BATTERY_FUEL_GAUGE
+#define CONFIG_BATTERY_V2
+#define CONFIG_BATTERY_COUNT 1
+#define CONFIG_HOSTCMD_BATTERY_V2
+
+/* Charger */
+#define CONFIG_CHARGER_RAA489000
+#define PD_MAX_VOLTAGE_MV 20000
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
+#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
+/*
+ * b/147463641: The charger IC seems to overdraw ~4%, therefore we
+ * reduce our target accordingly.
+ */
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 4
+#define CONFIG_CHARGER_PROFILE_OVERRIDE
+#define CHARGING_CURRENT_1100MA 1100
+
+/*
+ * GPIO for C1 interrupts, for baseboard use
+ *
+ * Note this line might already have its pull up disabled for HDMI DBs, but
+ * it should be fine to set again before z-state.
+ */
+#define GPIO_EC_HDMI_EN_ODL GPIO_EC_I2C_SBU_USB_C1_SCL
+#define GPIO_HDMI_PP3300_EN GPIO_SUB_USB_C1_INT_ODL
+
+/* PWM */
+#define CONFIG_PWM
+#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */
+
+/* USB */
+#define CONFIG_BC12_DETECT_PI3USB9201
+
+/* LED */
+#define CONFIG_LED_COMMON
+#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
+#define CONFIG_LED_ONOFF_STATES
+
+/* USB PD */
+#define CONFIG_USB_PD_PORT_MAX_COUNT 1
+#define CONFIG_USB_PD_TCPM_RAA489000
+
+/* USB defines specific to external TCPCs */
+#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+#define CONFIG_USB_PD_VBUS_DETECT_TCPC
+#define CONFIG_USB_PD_DISCHARGE_TCPC
+#define CONFIG_USB_PD_TCPC_LOW_POWER
+
+/* Variant references the TCPCs to determine Vbus sourcing */
+#define CONFIG_USB_PD_5V_EN_CUSTOM
+
+#undef PD_POWER_SUPPLY_TURN_ON_DELAY
+#undef PD_POWER_SUPPLY_TURN_OFF_DELAY
+#undef CONFIG_USBC_VCONN_SWAP_DELAY_US
+/* 20% margin added for these timings */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 13080 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 16080 /* us */
+#undef CONFIG_USBC_VCONN_SWAP_DELAY_US
+#define CONFIG_USBC_VCONN_SWAP_DELAY_US 787 /* us */
+
+/* I2C configuration */
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
+#define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0
+/* TODO(b:147440290): Need to handle multiple charger ICs */
+#define I2C_PORT_CHARGER I2C_PORT_USB_C0
+
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */
+
+/* Sensors */
+#define CONFIG_CMD_ACCELS
+#define CONFIG_CMD_ACCEL_INFO
+
+#define CONFIG_ACCEL_LIS2DE /* Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSO /* Base accel */
+#define CONFIG_ACCEL_LSM6DSO_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+/* Lid operates in forced mode, base in FIFO */
+#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
+#define CONFIG_ACCEL_FIFO
+#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */
+#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
+
+#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
+
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_UPDATE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+
+#define CONFIG_TABLET_MODE
+#define CONFIG_TABLET_MODE_SWITCH
+#define CONFIG_GMR_TABLET_MODE
+
+/* Thermistors */
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_THERMISTOR
+#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum adc_channel {
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
+	ADC_VSNS_PP3300_A, /* ADC9 */
+	ADC_CH_COUNT
+};
+
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
+
+enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT };
+
+enum pwm_channel {
+	PWM_CH_KBLIGHT,
+	PWM_CH_COUNT,
+};
+
+/* List of possible batteries */
+enum battery_type {
+	BATTERY_BYD_1VX1H,
+	BATTERY_BYD_YT39X,
+	BATTERY_BYD_X0Y5M,
+	BATTERY_LGC_FDRHM,
+	BATTERY_LGC_8GHCX,
+	BATTERY_SWD_ATL_WJPC4,
+	BATTERY_SWD_ATL_CTGKT,
+	BATTERY_SWD_COS_WJPC4,
+	BATTERY_SWD_COS_CTGKT,
+	BATTERY_SMP_ATL_VM732,
+	BATTERY_SMP_ATL_26JGK,
+	BATTERY_SMP_ATL_RF9H3,
+	BATTERY_SMP_COS_VM732,
+	BATTERY_SMP_COS_26JGK,
+	BATTERY_SMP_COS_RF9H3,
+	BATTERY_BYD16,
+	BATTERY_LGC3,
+	BATTERY_SIMPLO,
+	BATTERY_SIMPLO_LS,
+	BATTERY_TYPE_COUNT,
+};
+
+#endif /* !__ASSEMBLER__ */
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/cret/build.mk b/board/cret/build.mk
new file mode 100644
index 0000000000..1512a49379
--- /dev/null
+++ b/board/cret/build.mk
@@ -0,0 +1,14 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx7
+CHIP_VARIANT:=npcx7m6fc
+BASEBOARD:=dedede
+
+board-y=board.o battery.o cbi_ssfc.o led.o usb_pd_policy.o
diff --git a/board/cret/cbi_ssfc.c b/board/cret/cbi_ssfc.c
new file mode 100644
index 0000000000..81f3ee0dad
--- /dev/null
+++ b/board/cret/cbi_ssfc.c
@@ -0,0 +1,36 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi_ssfc.h"
+#include "common.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "hooks.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+/* Cache SSFC on init since we don't expect it to change in runtime */
+static union dedede_cbi_ssfc cached_ssfc;
+BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
+
+static void cbi_ssfc_init(void)
+{
+	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
+		/* Default to 0 when CBI isn't populated */
+		cached_ssfc.raw_value = 0;
+
+	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
+}
+DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
+
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
+{
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
+}
+
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
+{
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
+}
diff --git a/board/cret/cbi_ssfc.h b/board/cret/cbi_ssfc.h
new file mode 100644
index 0000000000..bef606bc72
--- /dev/null
+++ b/board/cret/cbi_ssfc.h
@@ -0,0 +1,64 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _DEDEDE_CBI_SSFC__H_
+#define _DEDEDE_CBI_SSFC__H_
+
+#include "stdint.h"
+
+/****************************************************************************
+ * Dedede CBI Second Source Factory Cache
+ */
+
+/*
+ * Base Sensor (Bits 0-2)
+ */
+enum ec_ssfc_base_sensor {
+	SSFC_SENSOR_BASE_DEFAULT = 0,
+	SSFC_SENSOR_BMI160 = 1,
+	SSFC_SENSOR_ICM426XX = 2,
+	SSFC_SENSOR_LSM6DSM = 3,
+	SSFC_SENSOR_ICM42607 = 4
+};
+
+/*
+ * Lid Sensor (Bits 3-5)
+ */
+enum ec_ssfc_lid_sensor {
+	SSFC_SENSOR_LID_DEFAULT = 0,
+	SSFC_SENSOR_BMA255 = 1,
+	SSFC_SENSOR_KX022 = 2,
+	SSFC_SENSOR_LIS2DWL = 3
+};
+
+/*
+ * Bits 9-11
+ * Cret board uses SSFC bits 9-11 in coreboot for audio codec.
+ */
+
+union dedede_cbi_ssfc {
+	struct {
+		uint32_t base_sensor : 3;
+		uint32_t lid_sensor : 3;
+		uint32_t reserved_2 : 26;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Get the Base sensor type from SSFC_CONFIG.
+ *
+ * @return the Base sensor board type.
+ */
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
+
+/**
+ * Get the Lid sensor type from SSFC_CONFIG.
+ *
+ * @return the Lid sensor board type.
+ */
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
+
+#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/cret/ec.tasklist b/board/cret/ec.tasklist
new file mode 100644
index 0000000000..a98ca6fd86
--- /dev/null
+++ b/board/cret/ec.tasklist
@@ -0,0 +1,22 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE)
diff --git a/board/cret/gpio.inc b/board/cret/gpio.inc
new file mode 100644
index 0000000000..5f39fedc80
--- /dev/null
+++ b/board/cret/gpio.inc
@@ -0,0 +1,148 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first.
+ */
+
+/* Power Interrupts */
+GPIO_INT(SLP_S0_L,		 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,		 PIN(A, 5), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(SLP_S4_L,		 PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,		 PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(RSMRST_PWRGD_L,	 PIN(C, 6), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID1,	 PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(CPU_C10_GATE_L,	 PIN(6, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID0,	 PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, power_signal_interrupt)
+GPIO_INT(PG_VCCIO_EXT_OD,	 PIN(B, 0), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(PG_PP5000_U_OD,	 PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_DRAM_OD,		 PIN(E, 4), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(PG_PP1050_ST_OD,	 PIN(4, 2), GPIO_INT_BOTH, power_signal_interrupt)
+
+/* USB-C interrupts */
+GPIO_INT(USB_C0_INT_ODL,	 		PIN(6, 2), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt)
+GPIO_INT(EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL,	PIN(9, 1), GPIO_INT_BOTH, sub_hdmi_hpd_interrupt) /* C1 I2C SDA OR HDMI_HPD */
+GPIO_INT(USB_C0_CCSBU_OVP_ODL,	PIN(A, 2), GPIO_INT_FALLING | GPIO_PULL_UP, c0_ccsbu_ovp_interrupt) /* Fault protection */
+
+/* Button interrupts */
+GPIO_INT(H1_EC_PWR_BTN_ODL,	 PIN(0, 1), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
+GPIO_INT(VOLDN_BTN_ODL,		 PIN(4, 0), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(VOLUP_BTN_ODL,		 PIN(7, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+
+/* Other interrupts */
+GPIO_INT(LID_OPEN,		 PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)
+GPIO_INT(EC_WP_OD,		 PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(LID_360_L,		 PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
+GPIO_INT(BASE_SIXAXIS_INT_L,	 PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, lsm6dso_interrupt)
+GPIO(LID_ACCEL_INT_L,		PIN(5, 0), GPIO_INPUT | GPIO_SEL_1P8V)
+
+/* I2C Ports */
+GPIO(EC_I2C_EEPROM_SCL,			PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SDA,			PIN(B, 2), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SCL,		PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SDA,		PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,			PIN(B, 5), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SDA,			PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SCL,			PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SDA,			PIN(8, 7), GPIO_INPUT)
+
+/* Misc Enables */
+GPIO(EN_VCCIO_EXT,   PIN(6, 1), GPIO_OUT_LOW)
+/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
+GPIO(EN_VCCST,		PIN(A, 7), GPIO_INPUT)
+GPIO(EN_PP3300_A,	PIN(0, 3), GPIO_OUT_LOW)
+GPIO(EN_PP5000_U,	PIN(A, 4), GPIO_OUT_LOW)
+GPIO(EN_SLP_Z,		PIN(8, 3), GPIO_OUT_LOW)
+GPIO(EN_BL_OD,		PIN(D, 3), GPIO_ODR_LOW)
+GPIO(IMVP9_PE,		PIN(E, 0), GPIO_OUT_LOW)
+GPIO(ECH1_PACKET_MODE,	PIN(7, 5), GPIO_OUT_LOW)
+GPIO(SUB_USB_C1_INT_ODL,    PIN(F, 5), GPIO_OUT_LOW) /* 5V power en */
+GPIO(EC_I2C_SBU_USB_C1_SCL,	PIN(9, 2), GPIO_ODR_LOW) /* HDMI en */
+
+/* Power Sequencing */
+GPIO(EC_AP_PSYS,	     PIN(B, 7), GPIO_OUT_LOW)
+GPIO(EC_AP_RSMRST_L,         PIN(A, 6), GPIO_OUT_LOW)
+GPIO(EC_AP_PWR_BTN_ODL,      PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(EC_AP_RTCRST,           PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_AP_WAKE_ODL,         PIN(7, 4), GPIO_ODR_HIGH)
+GPIO(EC_AP_DPWROK,	     PIN(A, 3), GPIO_OUT_LOW)
+GPIO(EC_AP_PCH_PWROK_OD,     PIN(9, 4), GPIO_ODR_LOW)
+GPIO(EC_AP_VCCST_PWRGD_OD,   PIN(B, 1), GPIO_ODR_LOW)
+GPIO(EC_AP_SYS_PWROK,	     PIN(0, 2), GPIO_OUT_LOW)
+GPIO(EC_AP_MKBP_INT_L,	     PIN(7, 0), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_ODL,	     PIN(F, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(EC_ENTERING_RW,	     PIN(E, 3), GPIO_OUT_LOW)
+GPIO(ALL_SYS_PWRGD,	     PIN(A, 0), GPIO_OUT_LOW)
+GPIO(SYS_RST_ODL,	     PIN(C, 5), GPIO_ODR_HIGH)
+GPIO(CCD_MODE_ODL,	     PIN(E, 5), GPIO_ODR_HIGH)
+
+GPIO(USB_C0_RST_ODL,	     PIN(9, 7), GPIO_OUT_HIGH) /* currently unused */
+GPIO(EC_AP_USB_C1_HDMI_HPD,  PIN(9, 6), GPIO_OUT_LOW)
+GPIO(EC_AP_USB_C0_HPD,	     PIN(9, 3), GPIO_OUT_LOW)
+GPIO(EC_BATTERY_PRES_ODL,    PIN(E, 1), GPIO_INPUT)
+
+/* USB pins */
+GPIO(USB_A0_CHARGE_EN_L,	PIN(6, 3), GPIO_OUT_HIGH)  /* Reverse: Enable A0 1.5A Charging */
+GPIO(EN_USB_A0_VBUS,         PIN(4, 1), GPIO_OUT_LOW)  /* Enable A0 5V Charging */
+
+/*LEDs*/
+GPIO(LED_1_PWR_WHITE_L,	 PIN(C, 3), GPIO_OUT_HIGH)
+GPIO(LED_2_CHG_AMBER_L,	 PIN(C, 4), GPIO_OUT_HIGH)
+
+/*
+ * Waddledoo doesn't have these physical pins coming to the EC but uses other
+ * logic.
+ */
+UNIMPLEMENTED(AC_PRESENT)
+UNIMPLEMENTED(PG_EC_DSW_PWROK)
+UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
+
+/* Alternate Functions */
+/* ADC */
+ALTERNATE(PIN_MASK(F, BIT(0)), 0, MODULE_ADC, 0) /* ADC9 */
+ALTERNATE(PIN_MASK(4, 0x30), 0, MODULE_ADC, 0)   /* ADC0-1 */
+
+/* Keyboard */
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI0, KSI1 */
+ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI2-7 */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO0, KSO1 */
+ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO3-9 */
+ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO10-13 */
+ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO14 */
+GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW)	/* KSO2 inverted */
+
+/* PWM */
+ALTERNATE(PIN_MASK(C, 0x04), 0, MODULE_PWM, 0)   /* PWM1 */
+
+/* UART */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)  /* UART1 */
+
+/* I2C */
+ALTERNATE(PIN_MASK(B, 0x3C), 0, MODULE_I2C, 0)   /* I2C7,I2C0 */
+ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)   /* I2C5 */
+ALTERNATE(PIN_MASK(9, 0x01), 0, MODULE_I2C, 0)   /* I2C2, I2C1 SCL */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)   /* I2C1 SDA */
+
+GPIO(EC_ACOK_OTG, PIN(C, 0), GPIO_OUT_LOW)  /* OTG-OVP protect enable */
+
+/* NC pins, enable internal pull-up to avoid floating state. */
+GPIO(GPIO32_NC, PIN(3, 2), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO35_NC, PIN(3, 5), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO57_NC, PIN(5, 7), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO81_NC, PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOD0_NC, PIN(D, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOD1_NC, PIN(D, 1), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOD6_NC, PIN(D, 6), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOF2_NC, PIN(F, 2), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOF3_NC, PIN(F, 3), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO37_NC, PIN(3, 7), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO34_NC, PIN(3, 4), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO43_NC, PIN(4, 3), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO60_NC, PIN(6, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO72_NC, PIN(7, 2), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO86_NC, PIN(8, 6), GPIO_INPUT | GPIO_PULL_UP)
diff --git a/board/cret/led.c b/board/cret/led.c
new file mode 100644
index 0000000000..8a7a343fb3
--- /dev/null
+++ b/board/cret/led.c
@@ -0,0 +1,86 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+#include "gpio.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
+
+__override const int led_charge_lvl_1 = 10;
+
+__override const int led_charge_lvl_2 = 100;
+
+/* Cret: Note there is only LED for charge / power */
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     1 * LED_ONE_SEC },
+					   { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_WHITE,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
+BUILD_ASSERT(ARRAY_SIZE(led_bat_state_table) == LED_NUM_STATES);
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_WHITE:
+		gpio_set_level(GPIO_LED_1_PWR_WHITE_L, LED_ON_LVL);
+		gpio_set_level(GPIO_LED_2_CHG_AMBER_L, LED_OFF_LVL);
+		break;
+	case EC_LED_COLOR_AMBER:
+		gpio_set_level(GPIO_LED_1_PWR_WHITE_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_2_CHG_AMBER_L, LED_ON_LVL);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		gpio_set_level(GPIO_LED_1_PWR_WHITE_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_2_CHG_AMBER_L, LED_OFF_LVL);
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	brightness_range[EC_LED_COLOR_WHITE] = 1;
+	brightness_range[EC_LED_COLOR_AMBER] = 1;
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (brightness[EC_LED_COLOR_WHITE] != 0)
+		led_set_color_battery(EC_LED_COLOR_WHITE);
+	else if (brightness[EC_LED_COLOR_AMBER] != 0)
+		led_set_color_battery(EC_LED_COLOR_AMBER);
+	else
+		led_set_color_battery(LED_OFF);
+
+	return EC_SUCCESS;
+}
diff --git a/board/cret/usb_pd_policy.c b/board/cret/usb_pd_policy.c
new file mode 100644
index 0000000000..83c09bb99e
--- /dev/null
+++ b/board/cret/usb_pd_policy.c
@@ -0,0 +1,61 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "driver/charger/isl923x_public.h"
+#include "driver/tcpm/tcpci.h"
+#include "usb_pd.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+int pd_check_vconn_swap(int port)
+{
+	/* Allow VCONN swaps if the AP is on. */
+	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
+}
+
+void pd_power_supply_reset(int port)
+{
+	/* Disable VBUS */
+	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	if (port >= board_get_usb_pd_port_count())
+		return EC_ERROR_INVAL;
+
+	/* Disable charging. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
+	if (rv)
+		return rv;
+
+	/* Our policy is not to source VBUS when the AP is off. */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	/* Provide Vbus. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
+	if (rv)
+		return rv;
+
+	rv = raa489000_enable_asgate(port, true);
+	if (rv)
+		return rv;
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
diff --git a/board/cret/vif_override.xml b/board/cret/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/cret/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/crota/battery.c b/board/crota/battery.c
new file mode 100644
index 0000000000..4738b5910f
--- /dev/null
+++ b/board/crota/battery.c
@@ -0,0 +1,431 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "cbi.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "gpio.h"
+/*
+ * Battery info for all Brya battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	/* ATL GB-S40-496570-010H Battery Information */
+	[BATTERY_ATL] = {
+		.fuel_gauge = {
+			.manuf_name = "ATL-ATL3.66",
+			.device_name = "DELL CFD72",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 0,
+				.reg_addr = 0x00,
+				.reg_mask = 0x2000,
+				.disconnect_val = 0x2000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 17600,  /* mV */
+			.voltage_normal		= 15000,  /* mV */
+			.voltage_min		= 12000,  /* mV */
+			.precharge_current	= 256,	  /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 60,
+			.charging_min_c		= 0,
+			.charging_max_c		= 50,
+			.discharging_min_c	= 0,
+			.discharging_max_c	= 60,
+		},
+	},
+	/* BYD 13076993-009 Battery Information */
+	[BATTERY_BYD_GSL4] = {
+		.fuel_gauge = {
+			.manuf_name = "BYD",
+			.device_name = "DELL WV3K8",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 0,
+				.reg_addr = 0x00,
+				.reg_mask = 0x2000,
+				.disconnect_val = 0x2000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 17400,  /* mV */
+			.voltage_normal		= 15000,  /* mV */
+			.voltage_min		= 12000,  /* mV */
+			.precharge_current	= 256,	  /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 60,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= 0,
+			.discharging_max_c	= 70,
+		},
+	},
+	/* CosMX B00C496570D0002 Battery Information */
+	[BATTERY_COM] = {
+		.fuel_gauge = {
+			.manuf_name = "COM",
+			.device_name = "DELL MVK11",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 0,
+				.reg_addr = 0x00,
+				.reg_mask = 0x2000,
+				.disconnect_val = 0x2000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 17600,  /* mV */
+			.voltage_normal		= 15000,  /* mV */
+			.voltage_min		= 12000,  /* mV */
+			.precharge_current	= 256,	  /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 50,
+			.discharging_min_c	= -17,
+			.discharging_max_c	= 70,
+		},
+	},
+	/* LGES MPPDELWM4C1N Battery Information */
+	[BATTERY_LGC] = {
+		.fuel_gauge = {
+			.manuf_name = "LGC-LGC3.600",
+			.device_name = "DELL XPHX8",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 0,
+				.reg_addr = 0x00,
+				.reg_mask = 0x2000,
+				.disconnect_val = 0x2000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 17600,  /* mV */
+			.voltage_normal		= 15000,  /* mV */
+			.voltage_min		= 12000,  /* mV */
+			.precharge_current	= 256,	  /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 50,
+			.discharging_min_c	= 0,
+			.discharging_max_c	= 70,
+		},
+	},
+	/* SMP 999QA455H Battery Information */
+	[BATTERY_SMP_ATL3] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP-ATL3.66",
+			.device_name = "DELL XDY9K",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 0,
+				.reg_addr = 0x00,
+				.reg_mask = 0x2000,
+				.disconnect_val = 0x2000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 17600,  /* mV */
+			.voltage_normal		= 15000,  /* mV */
+			.voltage_min		= 12000,  /* mV */
+			.precharge_current	= 256,	  /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 50,
+			.discharging_min_c	= -14,
+			.discharging_max_c	= 70,
+		},
+	},
+	/* SMP 999QA454H Battery Information */
+	[BATTERY_SMP_COS3] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP-COS3.66",
+			.device_name = "DELL XDY9K",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 0,
+				.reg_addr = 0x00,
+				.reg_mask = 0x2000,
+				.disconnect_val = 0x2000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 17600,  /* mV */
+			.voltage_normal		= 15000,  /* mV */
+			.voltage_min		= 12000,  /* mV */
+			.precharge_current	= 256,	  /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 50,
+			.discharging_min_c	= -14,
+			.discharging_max_c	= 70,
+		},
+	},
+	/* SWD 1002000008482 Battery Information */
+	[BATTERY_SWD_ATL3] = {
+		.fuel_gauge = {
+			.manuf_name = "SWD-ATL3.660",
+			.device_name = "DELL VKYJX",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 0,
+				.reg_addr = 0x00,
+				.reg_mask = 0x2000,
+				.disconnect_val = 0x2000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 17600,  /* mV */
+			.voltage_normal		= 15000,  /* mV */
+			.voltage_min		= 12000,  /* mV */
+			.precharge_current	= 256,	  /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 50,
+			.discharging_min_c	= 0,
+			.discharging_max_c	= 70,
+		},
+	},
+	/* SWD 1002000008492 Battery Information */
+	[BATTERY_SWD_COS3] = {
+		.fuel_gauge = {
+			.manuf_name = "SWD-COS3.661",
+			.device_name = "DELL VKYJX",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 0,
+				.reg_addr = 0x00,
+				.reg_mask = 0x2000,
+				.disconnect_val = 0x2000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 17600,  /* mV */
+			.voltage_normal		= 15000,  /* mV */
+			.voltage_min		= 12000,  /* mV */
+			.precharge_current	= 256,	  /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 50,
+			.discharging_min_c	= 0,
+			.discharging_max_c	= 70,
+		},
+	},
+	/* SMP 999QA485H Battery Information */
+	[BATTERY_SMP_ATL4] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP-ATL4.24",
+			.device_name = "DELL N9XX1",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 0,
+				.reg_addr = 0x00,
+				.reg_mask = 0x2000,
+				.disconnect_val = 0x2000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 17800,  /* mV */
+			.voltage_normal		= 15200,  /* mV */
+			.voltage_min		= 12000,  /* mV */
+			.precharge_current	= 256,	  /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 50,
+			.discharging_min_c	= -14,
+			.discharging_max_c	= 70,
+		},
+	},
+	/* SMP 999QA486H Battery Information */
+	[BATTERY_SMP_COS4] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP-COS4.26",
+			.device_name = "DELL N9XX1",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 0,
+				.reg_addr = 0x00,
+				.reg_mask = 0x2000,
+				.disconnect_val = 0x2000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 17800,  /* mV */
+			.voltage_normal		= 15200,  /* mV */
+			.voltage_min		= 12000,  /* mV */
+			.precharge_current	= 256,	  /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 50,
+			.discharging_min_c	= -14,
+			.discharging_max_c	= 70,
+		},
+	},
+	/* BYD 13148981-00 Battery Information */
+	[BATTERY_BYD_CSL4] = {
+		.fuel_gauge = {
+			.manuf_name = "BYD",
+			.device_name = "DELL JGCCT",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 0,
+				.reg_addr = 0x00,
+				.reg_mask = 0x2000,
+				.disconnect_val = 0x2000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 17400,  /* mV */
+			.voltage_normal		= 15000,  /* mV */
+			.voltage_min		= 12000,  /* mV */
+			.precharge_current	= 256,	  /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 60,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= 0,
+			.discharging_max_c	= 70,
+		},
+	},
+	/* Sunwoda 1002000009262 Battery Information */
+	[BATTERY_SWD_ATL4] = {
+		.fuel_gauge = {
+			.manuf_name = "SWD-ATL4.242",
+			.device_name = "DELL 3RR09",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 0,
+				.reg_addr = 0x00,
+				.reg_mask = 0x2000,
+				.disconnect_val = 0x2000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 17800,  /* mV */
+			.voltage_normal		= 15200,  /* mV */
+			.voltage_min		= 12000,  /* mV */
+			.precharge_current	= 256,	  /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 50,
+			.discharging_min_c	= 0,
+			.discharging_max_c	= 70,
+		},
+	},
+	/* Sunwoda 1002000009272 Battery Information */
+	[BATTERY_SWD_COS4] = {
+		.fuel_gauge = {
+			.manuf_name = "SWD-COS4.264",
+			.device_name = "DELL 3RR09",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 0,
+				.reg_addr = 0x00,
+				.reg_mask = 0x2000,
+				.disconnect_val = 0x2000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 17800,  /* mV */
+			.voltage_normal		= 15200,  /* mV */
+			.voltage_min		= 12000,  /* mV */
+			.precharge_current	= 256,	  /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 50,
+			.discharging_min_c	= 0,
+			.discharging_max_c	= 70,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_ATL;
+
+enum battery_present battery_hw_present(void)
+{
+	enum gpio_signal batt_pres;
+
+	batt_pres = GPIO_EC_BATT_PRES_ODL;
+
+	/*
+	 * The GPIO is low when the battery is physically present.
+	 * But if battery cell voltage < 2.5V, it will not able to
+	 * pull down EC_BATT_PRES_ODL. So we need to set pre-charge
+	 * current even EC_BATT_PRES_ODL is high.
+	 */
+	return gpio_get_level(batt_pres) ? BP_NOT_SURE : BP_YES;
+}
diff --git a/board/crota/board.c b/board/crota/board.c
new file mode 100644
index 0000000000..2e6f851ad5
--- /dev/null
+++ b/board/crota/board.c
@@ -0,0 +1,69 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "button.h"
+#include "charge_ramp.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/accel_lis2dw12.h"
+#include "driver/accelgyro_bmi260.h"
+#include "driver/accelgyro_lsm6dso.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "registers.h"
+#include "switch.h"
+#include "tablet_mode.h"
+#include "throttle_ap.h"
+#include "usbc_config.h"
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* Console output macros */
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+
+/* Called on AP S3 -> S0 transition */
+static void board_chipset_resume(void)
+{
+	/* Allow keyboard backlight to be enabled */
+
+	gpio_set_level(GPIO_EC_KB_BL_EN_L, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S0 -> S3 transition */
+static void board_chipset_suspend(void)
+{
+	/* Turn off the keyboard backlight if it's on. */
+
+	gpio_set_level(GPIO_EC_KB_BL_EN_L, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
+
+bool board_is_convertible(void)
+{
+	/*
+	 * convertible = 0
+	 * clamshell = 1
+	 */
+	return !get_fw_config().form_factor;
+}
+
+int board_sensor_at_360(void)
+{
+	if (board_is_convertible())
+		return !gpio_get_level(GPIO_TABLET_MODE_L);
+
+	return 0;
+}
diff --git a/board/crota/board.h b/board/crota/board.h
new file mode 100644
index 0000000000..d652a93ad0
--- /dev/null
+++ b/board/crota/board.h
@@ -0,0 +1,295 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Crota board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "compile_time_macros.h"
+
+/* Baseboard features */
+#include "baseboard.h"
+
+/*
+ * This will happen automatically on NPCX9 ES2 and later. Do not remove
+ * until we can confirm all earlier chips are out of service.
+ */
+#define CONFIG_HIBERNATE_PSL_VCC1_RST_WAKEUP
+
+#define CONFIG_MP2964
+
+/* Sensors */
+#define CONFIG_ACCELGYRO_BMI260 /* Base accel/gyro */
+#define CONFIG_ACCELGYRO_BMI260_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+#define CONFIG_ACCELGYRO_LSM6DSO /* Base accel/gyro */
+#define CONFIG_ACCEL_LSM6DSO_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+/* Enable sensor fifo, must also define the _SIZE and _THRES */
+#define CONFIG_ACCEL_FIFO
+/* FIFO size is in power of 2. */
+#define CONFIG_ACCEL_FIFO_SIZE 256
+/* Depends on how fast the AP boots and typical ODRs */
+#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
+
+/* Lid accel */
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_UPDATE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+#define CONFIG_ACCEL_LIS2DWL
+#define CONFIG_ACCEL_LIS2DW12_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
+
+#define CONFIG_BODY_DETECTION
+#define CONFIG_BODY_DETECTION_SENSOR BASE_ACCEL
+#define CONFIG_BODY_DETECTION_VAR_NOISE_FACTOR 150 /* % */
+#define CONFIG_GESTURE_DETECTION
+#define CONFIG_GESTURE_DETECTION_MASK BIT(CONFIG_BODY_DETECTION_SENSOR)
+#define CONFIG_GESTURE_HOST_DETECTION
+
+#define CONFIG_GMR_TABLET_MODE_CUSTOM
+/* Sensor console commands */
+#define CONFIG_CMD_ACCELS
+#define CONFIG_CMD_ACCEL_INFO
+
+/* USB Type A Features */
+#define USB_PORT_COUNT 1
+#define CONFIG_USB_PORT_POWER_DUMB
+
+/* USB Type C and USB PD defines */
+#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
+
+#define CONFIG_IO_EXPANDER
+#define CONFIG_IO_EXPANDER_NCT38XX
+#define CONFIG_IO_EXPANDER_PORT_COUNT 2
+
+#define CONFIG_USBC_RETIMER_INTEL_BB
+
+/* I2C speed console command */
+#define CONFIG_CMD_I2C_SPEED
+
+/* I2C control host command */
+#define CONFIG_HOSTCMD_I2C_CONTROL
+
+#define CONFIG_USBC_PPC_SYV682X
+
+#define CONFIG_USB_PD_FRS_PPC
+
+/* TODO: b/177608416 - measure and check these values on brya */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
+
+/*
+ * Passive USB-C cables only support up to 60W.
+ */
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
+
+#undef CONFIG_CMD_POWERINDEBUG
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
+
+/*
+ * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
+ * signal.
+ */
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
+
+#define GPIO_ID_1_EC_KB_BL_EN GPIO_EC_BATT_PRES_ODL
+
+/* System has back-lit keyboard */
+#define CONFIG_PWM_KBLIGHT
+
+/* Keyboard features */
+#define CONFIG_KEYBOARD_REFRESH_ROW3
+
+/* I2C Bus Configuration */
+
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+
+#define I2C_PORT_USB_C0_C1_TCPC NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1
+
+#define I2C_PORT_USB_C0_C1_PPC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1
+
+#define I2C_PORT_USB_C0_C1_BC12 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1
+
+#define I2C_PORT_USB_C0_C1_MUX NPCX_I2C_PORT3_0
+#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1
+
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0
+
+/* define this to avoid error on CONFIG_ACCELGYRO_BMI_COMM_I2C */
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+
+#define I2C_ADDR_MP2964_FLAGS 0x20
+/*
+ * see b/174768555#comment22
+ */
+#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x58
+#define USBC_PORT_C1_SOC_BB_RETIMER_I2C_ADDR 0x54
+/* Type-C connector facing Burnside Bridge retimer */
+#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x56
+
+/* Enabling Thunderbolt-compatible mode */
+#define CONFIG_USB_PD_TBT_COMPAT_MODE
+
+/* Enabling USB4 mode */
+#define CONFIG_USB_PD_USB4
+#define CONFIG_USB_PD_DATA_RESET_MSG
+
+/* Retimer */
+#define CONFIG_USBC_RETIMER_FW_UPDATE
+
+/* Thermal features */
+#define CONFIG_THERMISTOR
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_TEMP_SENSOR_POWER
+#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
+
+/* LED defines */
+#define CONFIG_LED_ONOFF_STATES
+#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
+
+/* Fan features */
+#define CONFIG_CUSTOM_FAN_CONTROL
+#define CONFIG_FANS FAN_CH_COUNT
+#define CONFIG_FAN_DYNAMIC
+#define RPM_DEVIATION 1
+
+/* Charger defines */
+#define CONFIG_CHARGER_BQ25720
+#define CONFIG_CHARGER_BQ25720_VSYS_TH2_CUSTOM
+#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV 70
+#define CONFIG_CHARGE_RAMP_SW
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10
+#define CONFIG_CHARGER_BQ25710_PSYS_SENSING
+#define CONFIG_CHARGER_BQ25710_PP_ACOK
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h" /* needed by registers.h */
+#include "registers.h"
+#include "usbc_config.h"
+
+enum adc_channel {
+	ADC_TEMP_SENSOR_1_SOC,
+	ADC_TEMP_SENSOR_2_DDR,
+	ADC_TEMP_SENSOR_3_CHARGER,
+	ADC_TEMP_SENSOR_4_AMBIENT,
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1_SOC,
+	TEMP_SENSOR_2_DDR,
+	TEMP_SENSOR_3_CHARGER,
+	TEMP_SENSOR_4_AMBIENT,
+	TEMP_SENSOR_COUNT
+};
+
+enum sensor_id { LID_ACCEL = 0, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
+
+enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_C1_NCT38XX, IOEX_PORT_COUNT };
+
+enum battery_type {
+	BATTERY_ATL,
+	BATTERY_BYD_GSL4,
+	BATTERY_COM,
+	BATTERY_LGC,
+	BATTERY_SMP_ATL3,
+	BATTERY_SMP_COS3,
+	BATTERY_SWD_ATL3,
+	BATTERY_SWD_COS3,
+	BATTERY_SMP_ATL4,
+	BATTERY_SMP_COS4,
+	BATTERY_BYD_CSL4,
+	BATTERY_SWD_ATL4,
+	BATTERY_SWD_COS4,
+	BATTERY_TYPE_COUNT
+};
+
+enum pwm_channel {
+	PWM_CH_LED2 = 0, /* PWM0 (white charger) */
+	PWM_CH_LED1, /* PWM2 (orange charger) */
+	PWM_CH_KBLIGHT, /* PWM3 */
+	PWM_CH_FAN, /* PWM5 */
+	PWM_CH_COUNT
+};
+
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT };
+
+enum fan_rpm_table {
+	RPM_TABLE_CPU,
+	RPM_TABLE_CPU_TABLET,
+	RPM_TABLE_DDR,
+	RPM_TABLE_CHARGER,
+	RPM_TABLE_AMBIENT,
+	FAN_RPM_TABLE_COUNT
+};
+
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT };
+
+struct thermal_policy_config {
+	uint8_t fan_off_slop1;
+	uint8_t fan_max_slop1;
+	uint8_t fan_off_slop2;
+	uint8_t fan_max_slop2;
+	uint8_t fan_slop_threshold;
+	uint8_t ddr_fan_turn_on;
+	uint8_t ddr_fan_turn_off;
+	uint8_t rpm_table_cpu;
+};
+
+enum thermal_cfg_table { LAPTOP_MODE, TABLET_MODE, THERMAL_CFG_TABLE_COUNT };
+
+void motion_interrupt(enum gpio_signal signal);
+
+bool board_is_convertible(void);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/crota/build.mk b/board/crota/build.mk
new file mode 100644
index 0000000000..8b85854cf0
--- /dev/null
+++ b/board/crota/build.mk
@@ -0,0 +1,25 @@
+# -*- makefile -*-
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Brya board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx9
+CHIP_VARIANT:=npcx9m3f
+BASEBOARD:=brya
+
+board-y=
+board-y+=battery.o
+board-y+=board.o
+board-y+=charger.o
+board-y+=fans.o
+board-y+=fw_config.o
+board-y+=i2c.o
+board-y+=keyboard.o
+board-y+=led.o
+board-y+=pwm.o
+board-y+=sensors.o
+board-y+=usbc_config.o
diff --git a/board/crota/charger.c b/board/crota/charger.c
new file mode 100644
index 0000000000..7b3edd270d
--- /dev/null
+++ b/board/crota/charger.c
@@ -0,0 +1,80 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/charger/bq25710.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/* Charger Chip Configuration */
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = BQ25710_SMBUS_ADDR1_FLAGS,
+		.drv = &bq25710_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CHARGER_NUM);
+
+int board_set_active_charge_port(int port)
+{
+	int is_valid_port = board_is_usb_pd_port_present(port);
+	int i;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTSUSB("Disabling all charger ports");
+
+		/* Disable all ports. */
+		for (i = 0; i < ppc_cnt; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (ppc_vbus_sink_enable(i, 0))
+				CPRINTSUSB("Disabling C%d as sink failed.", i);
+		}
+
+		return EC_SUCCESS;
+	} else if (!is_valid_port) {
+		return EC_ERROR_INVAL;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (ppc_is_sourcing_vbus(port)) {
+		CPRINTFUSB("Skip enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTSUSB("New charge port: C%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < ppc_cnt; i++) {
+		if (i == port)
+			continue;
+
+		if (ppc_vbus_sink_enable(i, 0))
+			CPRINTSUSB("C%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTSUSB("C%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/board/crota/ec.tasklist b/board/crota/ec.tasklist
new file mode 100644
index 0000000000..17eeb4ae7c
--- /dev/null
+++ b/board/crota/ec.tasklist
@@ -0,0 +1,29 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ *
+ * USB_CHG_Px tasks must be contiguous (see USB_CHG_PORT_TO_TASK_ID(x)).
+ * PD_Cx tasks must be contiguous (see PD_PORT_TO_TASK_ID(x))
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, HOOKS_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, BASEBOARD_CHG_RAMP_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, BASEBOARD_CHARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, BASEBOARD_CHIPSET_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, CONSOLE_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, BASEBOARD_POWERBTN_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_shared_alert_task, (BIT(1) | BIT(0)), BASEBOARD_PD_INT_TASK_STACK_SIZE)
diff --git a/board/crota/fans.c b/board/crota/fans.c
new file mode 100644
index 0000000000..874f04317f
--- /dev/null
+++ b/board/crota/fans.c
@@ -0,0 +1,207 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Physical fans. These are logically separate from pwm_channels. */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "fan.h"
+#include "fan_chip.h"
+#include "hooks.h"
+#include "pwm.h"
+#include "tablet_mode.h"
+#include "thermal.h"
+#include "timer.h"
+#include "util.h"
+
+#define RECORD_TIME (2 * MINUTE)
+
+/* MFT channels. These are logically separate from pwm_channels. */
+const struct mft_t mft_channels[] = {
+	[MFT_CH_0] = {
+		.module = NPCX_MFT_MODULE_1,
+		.clk_src = TCKC_LFCLK,
+		.pwm_id = PWM_CH_FAN,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
+
+static const struct fan_conf fan_conf_0 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
+	.pgood_gpio = -1,
+	.enable_gpio = GPIO_EN_PP5000_FAN,
+};
+
+static const struct fan_rpm rpm_table[FAN_RPM_TABLE_COUNT] = {
+	[RPM_TABLE_CPU] = {
+		.rpm_min = 0,
+		.rpm_start = 0,
+		.rpm_max = 4000,
+	},
+
+	[RPM_TABLE_CPU_TABLET] = {
+		.rpm_min = 0,
+		.rpm_start = 0,
+		.rpm_max = 4000,
+	},
+
+	[RPM_TABLE_DDR] = {
+		.rpm_min = 4000,
+		.rpm_start = 4000,
+		.rpm_max = 4200,
+	},
+
+	[RPM_TABLE_CHARGER] = {
+		.rpm_min = 4000,
+		.rpm_start = 4000,
+		.rpm_max = 4200,
+	},
+
+	[RPM_TABLE_AMBIENT] = {
+		.rpm_min = 4000,
+		.rpm_start = 4000,
+		.rpm_max = 4200,
+	},
+};
+
+struct fan_t fans[FAN_CH_COUNT] = {
+	[FAN_CH_0] = {
+		.conf = &fan_conf_0,
+		.rpm = &rpm_table[RPM_TABLE_CPU],
+	},
+};
+
+static const struct thermal_policy_config
+	thermal_cfg[THERMAL_CFG_TABLE_COUNT] = {
+	[LAPTOP_MODE] = {
+		.fan_off_slop1 = 24,
+		.fan_max_slop1 = 51,
+		.fan_off_slop2 = 29,
+		.fan_max_slop2 = 48,
+		.fan_slop_threshold = 45,
+		.ddr_fan_turn_off = 38,
+		.ddr_fan_turn_on = 44,
+		.rpm_table_cpu = RPM_TABLE_CPU,
+	},
+
+	[TABLET_MODE] = {
+		.fan_off_slop1 = 25,
+		.fan_max_slop1 = 52,
+		.fan_off_slop2 = 30,
+		.fan_max_slop2 = 49,
+		.fan_slop_threshold = 45,
+		.ddr_fan_turn_off = 38,
+		.ddr_fan_turn_on = 44,
+		.rpm_table_cpu = RPM_TABLE_CPU_TABLET,
+	},
+};
+
+static void fan_get_rpm(int fan)
+{
+	static timestamp_t deadline;
+
+	/* Record actual RPM every 2 minutes. */
+	if (timestamp_expired(deadline, NULL)) {
+		ccprints("fan actual rpm: %d", fan_get_rpm_actual(FAN_CH(fan)));
+		deadline.val = get_time().val + RECORD_TIME;
+	}
+}
+
+static void fan_set_percent(int fan, int pct)
+{
+	int new_rpm;
+
+	new_rpm = fan_percent_to_rpm(fan, pct);
+	fan_set_rpm_target(FAN_CH(fan), new_rpm);
+	fan_get_rpm(fan);
+}
+
+void board_override_fan_control(int fan, int *tmp)
+{
+	/*
+	 * Crota's fan speed is control by four sensors.
+	 *
+	 * Sensor charger control the speed when system's temperature
+	 * is too high.
+	 * Other sensors control normal loading's speed.
+	 *
+	 * When sensor charger is triggered, the fan speed is only
+	 * control by sensor charger, avoid heat damage to system.
+	 * When other sensors is triggered, the fan is control
+	 * by other sensors.
+	 *
+	 * Sensor SOC has two slopes for fan speed.
+	 * Sensor DDR also become a fan on/off switch.
+	 */
+	const struct thermal_policy_config *t;
+	static int pct;
+	int i;
+	int fan_pct[TEMP_SENSOR_COUNT];
+	int fan_off;
+	int fan_max;
+
+	/* Decide is tablet mode or laptop mode. */
+	if (tablet_get_mode())
+		t = &thermal_cfg[TABLET_MODE];
+	else
+		t = &thermal_cfg[LAPTOP_MODE];
+
+	/* Decide sensor SOC temperature using which slope. */
+	if (tmp[TEMP_SENSOR_1_SOC] <= t->fan_slop_threshold) {
+		fan_off = t->fan_off_slop1;
+		fan_max = t->fan_max_slop1;
+	} else {
+		fan_off = t->fan_off_slop2;
+		fan_max = t->fan_max_slop2;
+	}
+	thermal_params[TEMP_SENSOR_1_SOC].temp_fan_off = C_TO_K(fan_off);
+	thermal_params[TEMP_SENSOR_1_SOC].temp_fan_max = C_TO_K(fan_max);
+
+	for (i = 0; i < TEMP_SENSOR_COUNT; i++) {
+		fan_pct[i] = thermal_fan_percent(thermal_params[i].temp_fan_off,
+						 thermal_params[i].temp_fan_max,
+						 C_TO_K(tmp[i]));
+	}
+
+	/*
+	 * In Balance mode:
+	 * Sensor DDR turn on when temperature > 44,
+	 * turn off when temperature < 38
+	 *
+	 * In Tablet mode:
+	 * Sensor DDR turn on when temperature > 44,
+	 * turn off when temperature < 38
+	 *
+	 * When temperature from high dropping to 38 ~ 44,
+	 * if pct is not 0, keep sensor trigger and choose table.
+	 */
+	if (((tmp[TEMP_SENSOR_2_DDR]) <= t->ddr_fan_turn_on && pct == 0) ||
+	    ((tmp[TEMP_SENSOR_2_DDR]) < t->ddr_fan_turn_off))
+		pct = 0;
+	else {
+		/*
+		 * Decide which sensor was triggered and choose table.
+		 * Priority: charger > soc > ddr > ambient
+		 */
+		if (fan_pct[TEMP_SENSOR_3_CHARGER]) {
+			fans[fan].rpm = &rpm_table[RPM_TABLE_CHARGER];
+			pct = fan_pct[TEMP_SENSOR_3_CHARGER];
+		} else if (fan_pct[TEMP_SENSOR_1_SOC]) {
+			fans[fan].rpm = &rpm_table[t->rpm_table_cpu];
+			pct = fan_pct[TEMP_SENSOR_1_SOC];
+		} else if (fan_pct[TEMP_SENSOR_2_DDR]) {
+			fans[fan].rpm = &rpm_table[RPM_TABLE_DDR];
+			pct = fan_pct[TEMP_SENSOR_2_DDR];
+		} else {
+			fans[fan].rpm = &rpm_table[RPM_TABLE_AMBIENT];
+			pct = fan_pct[TEMP_SENSOR_4_AMBIENT];
+		}
+	}
+
+	/* Transfer percent to rpm. */
+	fan_set_percent(fan, pct);
+}
diff --git a/board/crota/fw_config.c b/board/crota/fw_config.c
new file mode 100644
index 0000000000..c5ee4708c2
--- /dev/null
+++ b/board/crota/fw_config.c
@@ -0,0 +1,53 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "fw_config.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+static union brya_cbi_fw_config fw_config;
+BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
+
+/*
+ * FW_CONFIG defaults for brya if the CBI.FW_CONFIG data is not
+ * initialized.
+ */
+static const union brya_cbi_fw_config fw_config_defaults = {
+	.kb_bl = KEYBOARD_BACKLIGHT_ENABLED,
+};
+
+/****************************************************************************
+ * Brya FW_CONFIG access
+ */
+void board_init_fw_config(void)
+{
+	if (cbi_get_fw_config(&fw_config.raw_value)) {
+		CPRINTS("CBI: Read FW_CONFIG failed, using board defaults");
+		fw_config = fw_config_defaults;
+	}
+
+	if (get_board_id() == 0) {
+		/*
+		 * Early boards have a zero'd out FW_CONFIG, so replace
+		 * it with a sensible default value. If DB_USB_ABSENT2
+		 * was used as an alternate encoding of DB_USB_ABSENT to
+		 * avoid the zero check, then fix it.
+		 */
+		if (fw_config.raw_value == 0) {
+			CPRINTS("CBI: FW_CONFIG is zero, using board defaults");
+			fw_config = fw_config_defaults;
+		}
+	}
+}
+
+union brya_cbi_fw_config get_fw_config(void)
+{
+	return fw_config;
+}
diff --git a/board/crota/fw_config.h b/board/crota/fw_config.h
new file mode 100644
index 0000000000..f2317c7cd7
--- /dev/null
+++ b/board/crota/fw_config.h
@@ -0,0 +1,42 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __BOARD_BRYA_FW_CONFIG_H_
+#define __BOARD_BRYA_FW_CONFIG_H_
+
+#include <stdint.h>
+
+/****************************************************************************
+ * CBI FW_CONFIG layout for Brya board.
+ *
+ * Source of truth is the project/brya/brya/config.star configuration file.
+ */
+
+enum ec_cfg_keyboard_backlight_type {
+	KEYBOARD_BACKLIGHT_DISABLED = 0,
+	KEYBOARD_BACKLIGHT_ENABLED = 1
+};
+
+union brya_cbi_fw_config {
+	struct {
+		uint32_t mb_db : 2;
+		enum ec_cfg_keyboard_backlight_type kb_bl : 1;
+		uint32_t audio : 3;
+		uint32_t db_lte : 2;
+		uint32_t wifi_sar_id : 1;
+		uint32_t form_factor : 1;
+		uint32_t reserved_1 : 22;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Read the cached FW_CONFIG.  Guaranteed to have valid values.
+ *
+ * @return the FW_CONFIG for the board.
+ */
+union brya_cbi_fw_config get_fw_config(void);
+
+#endif /* __BOARD_BRYA_FW_CONFIG_H_ */
diff --git a/board/crota/gpio.inc b/board/crota/gpio.inc
new file mode 100644
index 0000000000..0a3471b5c0
--- /dev/null
+++ b/board/crota/gpio.inc
@@ -0,0 +1,145 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define MODULE_KB		MODULE_KEYBOARD_SCAN
+
+/* INTERRUPT GPIOs: */
+GPIO_INT(ACOK_OD,                        PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
+GPIO_INT(EC_ACCEL_INT_R_L,               PIN(8, 1), GPIO_SEL_1P8V | GPIO_INT_FALLING, lis2dw12_interrupt)
+GPIO_INT(EC_IMU_INT_R_L,                 PIN(5, 6), GPIO_SEL_1P8V | GPIO_INT_FALLING, motion_interrupt)
+GPIO_INT(EC_PROCHOT_IN_L,                PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
+GPIO_INT(EC_VOLDN_BTN_ODL,               PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(EC_VOLUP_BTN_ODL,               PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(EC_WP_ODL,                      PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(GSC_EC_PWR_BTN_ODL,             PIN(0, 1), GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW, power_button_interrupt)
+GPIO_INT(LID_OPEN,                       PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
+GPIO_INT(SEQ_EC_ALL_SYS_PG,              PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_DSW_PWROK,               PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_RSMRST_ODL,              PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,                       PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,                      PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SYS_SLP_S0IX_L,                 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(TABLET_MODE_L,                  PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
+GPIO_INT(USB_C0_BC12_INT_ODL,            PIN(C, 6), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C0_C1_TCPC_INT_ODL,         PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C0_PPC_INT_ODL,             PIN(6, 2), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C0_RT_INT_ODL,              PIN(B, 1), GPIO_INT_FALLING, retimer_interrupt)
+GPIO_INT(USB_C1_BC12_INT_ODL,            PIN(8, 3), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C1_PPC_INT_ODL,             PIN(7, 0), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C1_RT_INT_ODL,              PIN(4, 1), GPIO_INT_FALLING, retimer_interrupt)
+
+/* USED GPIOs: */
+GPIO(CCD_MODE_ODL,                   PIN(E, 5), GPIO_INPUT)
+GPIO(CHARGER_VAP_OTG_EN,             PIN(7, 3), GPIO_OUT_LOW)
+GPIO(CPU_C10_GATE_L,                 PIN(6, 7), GPIO_INPUT)
+GPIO(EC_BATT_PRES_ODL,               PIN(A, 3), GPIO_INPUT)
+GPIO(EC_ENTERING_RW,                 PIN(0, 3), GPIO_OUT_LOW)
+GPIO(EC_EN_EDP_BL,                   PIN(D, 3), GPIO_OUT_HIGH)
+GPIO(EC_GSC_PACKET_MODE,             PIN(7, 5), GPIO_OUT_LOW)
+GPIO(EC_I2C_BAT_SCL,                 PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_BAT_SDA,                 PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SCL_R,              PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SDA_R,              PIN(B, 2), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,              PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SENSOR_SDA,              PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_USB_C0_C1_PPC_BC_SCL,    PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C1_PPC_BC_SDA,    PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C1_RT_SCL,        PIN(D, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C1_RT_SDA,        PIN(D, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C1_TCPC_SCL,      PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C1_TCPC_SDA,      PIN(8, 7), GPIO_INPUT)
+GPIO(EC_KB_BL_EN_L,                  PIN(8, 6), GPIO_OUT_HIGH)
+GPIO(EC_PCHHOT_ODL,                  PIN(7, 4), GPIO_INPUT)
+GPIO(EC_PCH_INT_ODL,                 PIN(B, 0), GPIO_ODR_HIGH)
+GPIO(EC_PCH_PWR_BTN_ODL,             PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(EC_PCH_RSMRST_L,                PIN(A, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_RTCRST,                  PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_SYS_PWROK,               PIN(3, 7), GPIO_OUT_LOW)
+GPIO(EC_PCH_WAKE_R_ODL,              PIN(C, 0), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_ODL,                 PIN(6, 3), GPIO_ODR_HIGH)
+GPIO(EN_PP5000_FAN,                  PIN(6, 1), GPIO_OUT_HIGH)
+GPIO(EN_PP5000_USBA_R,               PIN(D, 7), GPIO_OUT_LOW)
+GPIO(EN_S5_RAILS,                    PIN(B, 6), GPIO_OUT_LOW)
+GPIO(IMVP9_VRRDY_OD,                 PIN(4, 3), GPIO_INPUT)
+GPIO(PCH_PWROK,                      PIN(7, 2), GPIO_OUT_LOW)
+GPIO(SYS_RST_ODL,                    PIN(C, 5), GPIO_ODR_HIGH)
+GPIO(USB_C0_C1_TCPC_RST_ODL,         PIN(A, 7), GPIO_ODR_LOW)
+GPIO(VCCST_PWRGD_OD,                 PIN(A, 4), GPIO_ODR_LOW)
+GPIO(EC_SENSOR_STRAP,                PIN(5, 7), GPIO_INPUT)
+
+/* UART alternate functions */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)              /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */
+
+/* I2C alternate functions */
+ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)               /* GPIO33/I2C5_SCL0/CTS_L, GPIO36/RTS_L/I2C5_SDA0 */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)               /* GPIO87/I2C1_SDA0 */
+ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)               /* GPIO92/I2C2_SCL0, GPIO91/I2C2_SDA0, GPIO90/I2C1_SCL0 */
+ALTERNATE(PIN_MASK(B, 0x0c), 0, MODULE_I2C, 0)               /* GPIOB3/I2C7_SCL0/DCD_L, GPIOB2/I2C7_SDA0/DSR_L */
+ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, GPIO_SEL_1P8V)   /* GPIOB5/I2C0_SCL0, GPIOB4/I2C0_SDA0 */
+ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)               /* GPIOD1/I2C3_SCL0, GPIOD0/I2C3_SDA0 */
+
+/* PWM alternate functions */
+ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0)               /* GPIO40/TA1 */
+ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)               /* GPIO80/PWM3 */
+ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)               /* GPIOB7/PWM5 */
+ALTERNATE(PIN_MASK(C, 0x18), 0, MODULE_PWM, 0)               /* GPIOC4/PWM2, GPIOC3/PWM0 */
+
+/* ADC alternate functions */
+ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0)               /* GPIO34/PS2_DAT2/ADC6 */
+ALTERNATE(PIN_MASK(4, 0x34), 0, MODULE_ADC, 0)               /* GPIO42/ADC3/RI_L, GPIO45/ADC0, GPIO44/ADC1 */
+ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0)               /* GPIOE1/ADC7 */
+
+/* KB alternate functions */
+ALTERNATE(PIN_MASK(0, 0xf0), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO10&P80_CLK/GPIO07, KSO11&P80_DAT/GPIO06, KSO12/GPIO05, KSO13/GPIO04 */
+ALTERNATE(PIN_MASK(1, 0x7f), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO06/GPO13/GP_SEL_L, KSO07/GPO12/JEN_L, KSO03/GPIO16/JTAG_TDO0_SWO, KSO04/GPIO15/XNOR, KSO05/GPIO14, KSO08/GPIO11/CR_SOUT1, KSO09/GPIO10/CR_SIN1 */
+ALTERNATE(PIN_MASK(2, 0xfc), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI2/GPIO27/TRACEDATA1, KSI3/GPIO26/TRACEDATA0, KSI4/GPIO25/TRACECLK/GP_SCLK, KSI5/GPIO24/GP_MISO, KSI6/GPIO23/S_SBUB, KSI7/GPIO22/S_SBUA */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO00/GPIO21/JTAG_TCK_SWCLK, KSO01/GPIO20/JTAG_TMS_SWIO */
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI0/GPIO31/TRACEDATA3/GP_MOSI, KSI1/GPIO30/TRACEDATA2/GP_CS_L */
+ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO14/GPIO82 */
+
+/* PMU alternate functions */
+ALTERNATE(PIN_MASK(0, 0x01), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN2_L&GPI00/GPIO00 */
+ALTERNATE(PIN_MASK(0, 0x02), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW) /* GPIO01/PSL_IN3_L&GPI01 */
+ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN1_L&GPID2/GPIOD2 */
+
+/* Unused Pins */
+UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
+UNUSED(PIN(3, 2))       /* GPO32/TRIS_L */
+UNUSED(PIN(3, 5))       /* GPO35/CR_SOUT4/TEST_L */
+UNUSED(PIN(6, 6))       /* GPIO66 */
+UNUSED(PIN(D, 4))       /* GPIOD4/CR_SIN3 */
+UNUSED(PIN(5, 0))       /* GPIO50 */
+UNUSED(PIN(F, 5))       /* GPIOF5/I2C5_SCL1 */
+UNUSED(PIN(A, 2))       /* F_SCLK/GPIOA2 */
+UNUSED(PIN(E, 4))       /* GPIOE4/I2C6_SCL1/I3C_SCL */
+UNUSED(PIN(E, 3))       /* GPIOE3/I2C6_SDA1/I3C_SDA */
+UNUSED(PIN(F, 3))       /* GPIOF3/I2C4_SCL1 */
+UNUSED(PIN(F, 2))       /* GPIOF2/I2C4_SDA1 */
+UNUSED(PIN(9, 4))       /* GPIO94 */
+UNUSED(PIN(9, 6))       /* F_DIO1/GPIO96 */
+UNUSED(PIN(A, 0))       /* F_CS0#/GPIOA0 */
+UNUSED(PIN(0, 2))       /* GPIO02/PSL_IN4#&GPI02 */
+UNUSED(PIN(6, 0))       /* GPIO60/PWM7 */
+UNUSED(PIN(C, 2))       /* GPIOC2/PWM1/I2C6_SCL0 */
+
+/* Pre-configured PSL balls:  J8  K6 */
+
+
+/*
+ * The NPCX keyboard driver does not use named GPIOs to access
+ * keyboard scan pins, so we do not list them in *gpio.inc. However, when
+ * KEYBOARD_COL2_INVERTED is defined, this name is required.
+ */
+GPIO(EC_KSO_02_INV,               PIN(1, 7), GPIO_OUT_LOW)
+
+IOEX(USB_C0_OC_ODL,          EXPIN(IOEX_C0_NCT38XX, 0, 4), GPIO_ODR_HIGH)
+IOEX(USB_C0_FRS_EN,          EXPIN(IOEX_C0_NCT38XX, 0, 6), GPIO_OUT_LOW)
+IOEX(USB_C0_RT_RST_ODL,      EXPIN(IOEX_C0_NCT38XX, 0, 7), GPIO_ODR_LOW)
+
+IOEX(USB_C1_RT_RST_ODL,      EXPIN(IOEX_C1_NCT38XX, 0, 2), GPIO_ODR_LOW)
+IOEX(USB_C1_OC_ODL,          EXPIN(IOEX_C1_NCT38XX, 0, 4), GPIO_ODR_HIGH)
+IOEX(USB_C1_FRS_EN,          EXPIN(IOEX_C1_NCT38XX, 0, 6), GPIO_OUT_LOW)
diff --git a/board/crota/i2c.c b/board/crota/i2c.c
new file mode 100644
index 0000000000..681e600bf2
--- /dev/null
+++ b/board/crota/i2c.c
@@ -0,0 +1,65 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "hooks.h"
+#include "i2c.h"
+
+#define BOARD_ID_FAST_PLUS_CAPABLE 2
+
+/* I2C port map configuration */
+const struct i2c_port_t i2c_ports[] = {
+	{
+		/* I2C0 */
+		.name = "sensor",
+		.port = I2C_PORT_SENSOR,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_SENSOR_SCL,
+		.sda = GPIO_EC_I2C_SENSOR_SDA,
+	},
+	{
+		/* I2C1 */
+		.name = "tcpc0,2",
+		.port = I2C_PORT_USB_C0_C1_TCPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C1_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C1_TCPC_SDA,
+	},
+	{
+		/* I2C2 */
+		.name = "ppc0,2",
+		.port = I2C_PORT_USB_C0_C1_PPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C1_PPC_BC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C1_PPC_BC_SDA,
+	},
+	{
+		/* I2C3 */
+		.name = "retimer0,2",
+		.port = I2C_PORT_USB_C0_C1_MUX,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C1_RT_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C1_RT_SDA,
+	},
+	{
+		/* I2C5 */
+		.name = "battery",
+		.port = I2C_PORT_BATTERY,
+		.kbps = 100,
+		.scl = GPIO_EC_I2C_BAT_SCL,
+		.sda = GPIO_EC_I2C_BAT_SDA,
+	},
+	{
+		/* I2C7 */
+		.name = "eeprom",
+		.port = I2C_PORT_EEPROM,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_MISC_SCL_R,
+		.sda = GPIO_EC_I2C_MISC_SDA_R,
+	},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/board/crota/keyboard.c b/board/crota/keyboard.c
new file mode 100644
index 0000000000..8911d48b81
--- /dev/null
+++ b/board/crota/keyboard.c
@@ -0,0 +1,48 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "ec_commands.h"
+#include "keyboard_scan.h"
+#include "timer.h"
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/* Increase from 50 us, because KSO_02 passes through the H1. */
+	.output_settle_us = 80,
+	/* Other values should be the same as the default configuration. */
+	.debounce_down_us = 9 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
+		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
+	},
+};
+
+static const struct ec_response_keybd_config crota_kb = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		    /* T1 */
+		TK_REFRESH,		    /* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		    /* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &crota_kb;
+}
diff --git a/board/crota/led.c b/board/crota/led.c
new file mode 100644
index 0000000000..ee8b7ad8ea
--- /dev/null
+++ b/board/crota/led.c
@@ -0,0 +1,106 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Crota specific PWM LED settings. */
+
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+#include "pwm.h"
+#include "util.h"
+
+#include <stdint.h>
+
+#define BAT_LED_ON_LVL 100
+#define BAT_LED_OFF_LVL 0
+
+__override const int led_charge_lvl_1 = 5;
+__override const int led_charge_lvl_2 = 96;
+
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_WHITE,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_WHITE,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 1 * LED_ONE_SEC } },
+	};
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_BATTERY_LED,
+};
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	/* There are two battery leds, LED1/LED2 are on MB side.
+	 * All leds are OFF by default.
+	 */
+	int led1_duty, led2_duty;
+
+	led1_duty = led2_duty = BAT_LED_OFF_LVL;
+
+	switch (color) {
+	case EC_LED_COLOR_AMBER:
+		led1_duty = BAT_LED_ON_LVL;
+		break;
+	case EC_LED_COLOR_WHITE:
+		led2_duty = BAT_LED_ON_LVL;
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		break;
+	}
+
+	pwm_set_duty(PWM_CH_LED1, led1_duty);
+	pwm_set_duty(PWM_CH_LED2, led2_duty);
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	brightness_range[EC_LED_COLOR_AMBER] = 1;
+	brightness_range[EC_LED_COLOR_WHITE] = 1;
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	led_auto_control(led_id, 0);
+	if (brightness[EC_LED_COLOR_AMBER] != 0)
+		led_set_color_battery(EC_LED_COLOR_AMBER);
+	else if (brightness[EC_LED_COLOR_WHITE] != 0)
+		led_set_color_battery(EC_LED_COLOR_WHITE);
+	else
+		led_set_color_battery(LED_OFF);
+
+	return EC_SUCCESS;
+}
+
+__override enum led_states board_led_get_state(enum led_states desired_state)
+{
+	/* Make sure when battery is pre-charging, the LED will blinking.
+	 * Otherwise it will wait 30 seconds then blinking.
+	 */
+	if (led_pwr_get_state() == LED_PWRS_IDLE) {
+		if (charge_get_flags() & CHARGE_FLAG_EXTERNAL_POWER)
+			desired_state = STATE_BATTERY_ERROR;
+	}
+	return desired_state;
+}
diff --git a/board/crota/pwm.c b/board/crota/pwm.c
new file mode 100644
index 0000000000..26da4e4f7d
--- /dev/null
+++ b/board/crota/pwm.c
@@ -0,0 +1,57 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "chipset.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "hooks.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_LED2] = {
+		.channel = 0,
+		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+		.freq = 4800,
+	},
+	[PWM_CH_LED1] = {
+		.channel = 2,
+		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+		.freq = 4800,
+	},
+	[PWM_CH_KBLIGHT] = {
+		.channel = 3,
+		.flags = 0,
+		/*
+		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
+		 * flicker. Higher frequencies consume similar average power to
+		 * lower PWM frequencies, but higher frequencies record a much
+		 * lower maximum power.
+		 */
+		.freq = 2400,
+	},
+	[PWM_CH_FAN] = {
+		.channel = 5,
+		.flags = PWM_CONFIG_OPEN_DRAIN,
+		.freq = 25000
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+static void board_pwm_init(void)
+{
+	/*
+	 * Turn off all the LEDs.
+	 * Turn on the fan at 100%.
+	 */
+	pwm_enable(PWM_CH_LED1, 1);
+	pwm_set_duty(PWM_CH_LED1, 0);
+	pwm_enable(PWM_CH_LED2, 1);
+	pwm_set_duty(PWM_CH_LED2, 0);
+
+	pwm_enable(PWM_CH_KBLIGHT, 1);
+	pwm_set_duty(PWM_CH_KBLIGHT, 50);
+}
+DECLARE_HOOK(HOOK_INIT, board_pwm_init, HOOK_PRIO_DEFAULT);
diff --git a/board/crota/sensors.c b/board/crota/sensors.c
new file mode 100644
index 0000000000..9121976a40
--- /dev/null
+++ b/board/crota/sensors.c
@@ -0,0 +1,339 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "accelgyro.h"
+#include "adc.h"
+#include "common.h"
+#include "console.h"
+#include "driver/accel_lis2dw12.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "driver/accelgyro_lsm6dso.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "motion_sense.h"
+#include "tablet_mode.h"
+#include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
+#include "thermal.h"
+
+/* ADC configuration */
+const struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_1_SOC] = {
+		.name = "TEMP_SOC",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_2_DDR] = {
+		.name = "TEMP_DDR",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_3_CHARGER] = {
+		.name = "TEMP_CHARGER",
+		.input_ch = NPCX_ADC_CH6,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_4_AMBIENT] = {
+		.name = "TEMP_AMBIENT",
+		.input_ch = NPCX_ADC_CH7,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+K_MUTEX_DEFINE(g_lid_accel_mutex);
+K_MUTEX_DEFINE(g_base_accel_mutex);
+static struct stprivate_data g_lis2dw12_data;
+static struct lsm6dso_data lsm6dso_data;
+static struct bmi_drv_data_t g_bmi260_data;
+
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
+
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, FLOAT_TO_FP(1), 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
+
+static const mat33_fp_t base_standard_ref_id_1 = { { 0, FLOAT_TO_FP(1), 0 },
+						   { FLOAT_TO_FP(1), 0, 0 },
+						   { 0, 0, FLOAT_TO_FP(-1) } };
+
+struct motion_sensor_t motion_sensors[] = {
+	[LID_ACCEL] = {
+		.name = "Lid Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LIS2DW12,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &lis2dw12_drv,
+		.mutex = &g_lid_accel_mutex,
+		.drv_data = &g_lis2dw12_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LIS2DW12_ADDR0,
+		.rot_standard_ref = &lid_standard_ref, /* identity matrix */
+		.default_range = 2, /* g */
+		.min_frequency = LIS2DW12_ODR_MIN_VAL,
+		.max_frequency = LIS2DW12_ODR_MAX_VAL,
+		.config = {
+			/* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+			/* Sensor on for lid angle detection */
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+		},
+	},
+
+	[BASE_ACCEL] = {
+		.name = "Base Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LSM6DSO,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &lsm6dso_drv,
+		.mutex = &g_base_accel_mutex,
+		.drv_data = LSM6DSO_ST_DATA(lsm6dso_data,
+				MOTIONSENSE_TYPE_ACCEL),
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LSM6DSO_ADDR0_FLAGS,
+		.rot_standard_ref = &base_standard_ref,
+		.default_range = 4,  /* g */
+		.min_frequency = LSM6DSO_ODR_MIN_VAL,
+		.max_frequency = LSM6DSO_ODR_MAX_VAL,
+		.config = {
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 13000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+		},
+	},
+
+	[BASE_GYRO] = {
+		.name = "Base Gyro",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LSM6DSO,
+		.type = MOTIONSENSE_TYPE_GYRO,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &lsm6dso_drv,
+		.mutex = &g_base_accel_mutex,
+		.drv_data = LSM6DSO_ST_DATA(lsm6dso_data,
+				MOTIONSENSE_TYPE_GYRO),
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LSM6DSO_ADDR0_FLAGS,
+		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = LSM6DSO_ODR_MIN_VAL,
+		.max_frequency = LSM6DSO_ODR_MAX_VAL,
+	},
+};
+const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+struct motion_sensor_t bmi260_base_accel = {
+	.name = "Base Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_BMI260,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &bmi260_drv,
+	.mutex = &g_base_accel_mutex,
+	.drv_data = &g_bmi260_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
+	.rot_standard_ref = &base_standard_ref_id_1,
+	.min_frequency = BMI_ACCEL_MIN_FREQ,
+	.max_frequency = BMI_ACCEL_MAX_FREQ,
+	.default_range = 4, /* g */
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+		/* Sensor on in S3 */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+	},
+};
+struct motion_sensor_t bmi260_base_gyro = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_BMI260,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &bmi260_drv,
+	.mutex = &g_base_accel_mutex,
+	.drv_data = &g_bmi260_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &base_standard_ref_id_1,
+	.min_frequency = BMI_GYRO_MIN_FREQ,
+	.max_frequency = BMI_GYRO_MAX_FREQ,
+};
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	if (get_board_id() > 1) {
+		if (gpio_get_level(GPIO_EC_SENSOR_STRAP) == 0)
+			bmi260_interrupt(signal);
+		else
+			lsm6dso_interrupt(signal);
+	} else
+		lsm6dso_interrupt(signal);
+}
+
+static void board_update_motion_sensor_config(void)
+{
+	if (get_board_id() > 1 && gpio_get_level(GPIO_EC_SENSOR_STRAP) == 0) {
+		motion_sensors[BASE_ACCEL] = bmi260_base_accel;
+		motion_sensors[BASE_GYRO] = bmi260_base_gyro;
+		ccprints("BASE IMU is BMI260");
+	} else {
+		ccprints("BASE IMU is LSM6DSO");
+	}
+
+	if (!board_is_convertible()) {
+		tablet_set_mode(0, TABLET_TRIGGER_LID);
+		gmr_tablet_switch_disable();
+		/* Make sure tablet mode detection is not trigger by mistake. */
+		gpio_set_flags(GPIO_TABLET_MODE_L, GPIO_INPUT | GPIO_PULL_UP);
+		/*
+		 * Make sure we don't even try to initialize the lid accel, it
+		 * is not present.
+		 */
+		motion_sensors[LID_ACCEL].active_mask = 0;
+		gpio_set_flags(GPIO_EC_ACCEL_INT_R_L,
+			       GPIO_INPUT | GPIO_PULL_UP);
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_update_motion_sensor_config,
+	     HOOK_PRIO_INIT_I2C + 1);
+
+__override int sensor_board_is_lid_angle_available(void)
+{
+	return board_is_convertible();
+}
+
+static void baseboard_sensors_init(void)
+{
+	/* Enable gpio interrupt for lid accel sensor */
+	gpio_enable_interrupt(GPIO_EC_ACCEL_INT_R_L);
+	/* Enable gpio interrupt for base accelgyro sensor */
+	gpio_enable_interrupt(GPIO_EC_IMU_INT_R_L);
+}
+DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_INIT_I2C + 1);
+
+/* Temperature sensor configuration */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1_SOC] = {
+		.name = "SOC",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_1_SOC,
+	},
+	[TEMP_SENSOR_2_DDR] = {
+		.name = "DDR",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_2_DDR,
+	},
+	[TEMP_SENSOR_3_CHARGER] = {
+		.name = "Charger",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_3_CHARGER,
+	},
+	[TEMP_SENSOR_4_AMBIENT] = {
+		.name = "Ambient",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_4_AMBIENT,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(77), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(77), \
+		}, \
+		.temp_fan_off = C_TO_K(24), \
+		.temp_fan_max = C_TO_K(51), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
+
+#define THERMAL_DDR              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(78), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
+		}, \
+		.temp_fan_off = C_TO_K(56), \
+		.temp_fan_max = C_TO_K(59), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_ddr = THERMAL_DDR;
+
+#define THERMAL_CHARGER          \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(86), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(89), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(86), \
+		}, \
+		.temp_fan_off = C_TO_K(67), \
+		.temp_fan_max = C_TO_K(70), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_charger =
+	THERMAL_CHARGER;
+
+#define THERMAL_AMBIENT          \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(57), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(60), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(57), \
+		}, \
+		.temp_fan_off = C_TO_K(38), \
+		.temp_fan_max = C_TO_K(45), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_ambient =
+	THERMAL_AMBIENT;
+
+struct ec_thermal_config thermal_params[] = {
+	[TEMP_SENSOR_1_SOC] = THERMAL_CPU,
+	[TEMP_SENSOR_2_DDR] = THERMAL_DDR,
+	[TEMP_SENSOR_3_CHARGER] = THERMAL_CHARGER,
+	[TEMP_SENSOR_4_AMBIENT] = THERMAL_AMBIENT,
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
diff --git a/board/crota/usbc_config.c b/board/crota/usbc_config.c
new file mode 100644
index 0000000000..f8e3c0704a
--- /dev/null
+++ b/board/crota/usbc_config.c
@@ -0,0 +1,397 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi.h"
+#include "charge_ramp.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/bc12/pi3usb9201_public.h"
+#include "driver/ppc/nx20p348x.h"
+#include "driver/ppc/syv682x_public.h"
+#include "driver/retimer/bb_retimer_public.h"
+#include "driver/tcpm/nct38xx.h"
+#include "driver/tcpm/ps8xxx_public.h"
+#include "driver/tcpm/tcpci.h"
+#include "ec_commands.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "ioexpander.h"
+#include "system.h"
+#include "task.h"
+#include "task_id.h"
+#include "timer.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+#ifdef CONFIG_ZEPHYR
+enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_C1_NCT38XX, IOEX_PORT_COUNT };
+#endif /* CONFIG_ZEPHYR */
+
+/* USBC TCPC configuration */
+const struct tcpc_config_t tcpc_config[] = {
+	[USBC_PORT_C0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0_C1_TCPC,
+			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_NO_DEBUG_ACC_CONTROL,
+	},
+	[USBC_PORT_C1] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0_C1_TCPC,
+			.addr_flags = NCT38XX_I2C_ADDR1_4_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
+BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
+
+/******************************************************************************/
+/* USB-A charging control */
+
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_PP5000_USBA_R,
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
+
+/******************************************************************************/
+
+/* USBC PPC configuration */
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_C1_PPC,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.frs_en = IOEX_USB_C0_FRS_EN,
+		.drv = &syv682x_drv,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C0_C1_PPC,
+		.i2c_addr_flags = SYV682X_ADDR2_FLAGS,
+		.frs_en = IOEX_USB_C1_FRS_EN,
+		.drv = &syv682x_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
+
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/* USBC mux configuration - Alder Lake includes internal mux */
+static const struct usb_mux_chain usbc0_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+static const struct usb_mux_chain usbc1_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+struct usb_mux_chain soc_side_bb_retimer_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C0_C1_MUX,
+			.i2c_addr_flags = USBC_PORT_C1_SOC_BB_RETIMER_I2C_ADDR,
+		},
+	.next = &usbc1_tcss_usb_mux,
+};
+const struct usb_mux_chain usb_muxes[] = {
+	[USBC_PORT_C0] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C0_C1_MUX,
+			.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc0_tcss_usb_mux,
+	},
+	[USBC_PORT_C1] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C0_C1_MUX,
+			.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &soc_side_bb_retimer_usb_mux,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
+
+#ifndef CONFIG_ZEPHYR
+/* BC1.2 charger detect configuration */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_C1_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C0_C1_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_1_FLAGS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
+
+/*
+ * USB C0 and C1 uses burnside bridge chips and have their reset
+ * controlled by their respective TCPC chips acting as GPIO expanders.
+ *
+ * ioex_init() is normally called before we take the TCPCs out of
+ * reset, so we need to start in disabled mode, then explicitly
+ * call ioex_init().
+ */
+
+struct ioexpander_config_t ioex_config[] = {
+	[IOEX_C0_NCT38XX] = {
+		.i2c_host_port = I2C_PORT_USB_C0_C1_TCPC,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
+	},
+	[IOEX_C1_NCT38XX] = {
+		.i2c_host_port = I2C_PORT_USB_C0_C1_TCPC,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR1_4_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT);
+#endif /* !CONFIG_ZEPHYR */
+
+#ifdef CONFIG_CHARGE_RAMP_SW
+
+/*
+ * TODO(b/181508008): tune this threshold
+ */
+
+#define BC12_MIN_VOLTAGE 4400
+
+/**
+ * Return true if VBUS is too low
+ */
+int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
+{
+	int voltage;
+
+	if (charger_get_vbus_voltage(port, &voltage))
+		voltage = 0;
+
+	if (voltage == 0) {
+		CPRINTS("%s: must be disconnected", __func__);
+		return 1;
+	}
+
+	if (voltage < BC12_MIN_VOLTAGE) {
+		CPRINTS("%s: port %d: vbus %d lower than %d", __func__, port,
+			voltage, BC12_MIN_VOLTAGE);
+		return 1;
+	}
+
+	return 0;
+}
+
+#endif /* CONFIG_CHARGE_RAMP_SW */
+
+__override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
+{
+	enum ioex_signal rst_signal;
+
+	if (me->usb_port == USBC_PORT_C0) {
+		rst_signal = IOEX_USB_C0_RT_RST_ODL;
+	} else if (me->usb_port == USBC_PORT_C1) {
+		rst_signal = IOEX_USB_C1_RT_RST_ODL;
+	} else {
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * We do not have a load switch for the burnside bridge chips,
+	 * so we only need to sequence reset.
+	 */
+
+	if (enable) {
+		/*
+		 * Tpw, minimum time from VCC to RESET_N de-assertion is 100us.
+		 * For boards that don't provide a load switch control, the
+		 * retimer_init() function ensures power is up before calling
+		 * this function.
+		 */
+		ioex_set_level(rst_signal, 1);
+		/*
+		 * Allow 1ms time for the retimer to power up lc_domain
+		 * which powers I2C controller within retimer
+		 */
+		msleep(1);
+	} else {
+		ioex_set_level(rst_signal, 0);
+		msleep(1);
+	}
+	return EC_SUCCESS;
+}
+
+void board_reset_pd_mcu(void)
+{
+	enum gpio_signal tcpc_rst;
+
+	tcpc_rst = GPIO_USB_C0_C1_TCPC_RST_ODL;
+
+	gpio_set_level(tcpc_rst, 0);
+
+	/*
+	 * delay for power-on to reset-off and min. assertion time
+	 */
+
+	msleep(20);
+
+	gpio_set_level(tcpc_rst, 1);
+
+	/* wait for chips to come up */
+
+	msleep(50);
+}
+
+static void board_tcpc_init(void)
+{
+	/* Don't reset TCPCs after initial reset */
+	if (!system_jumped_late())
+		board_reset_pd_mcu();
+
+	/*
+	 * These IO expander pins are implemented using the
+	 * C0/C1 TCPC, so they must be set up after the TCPC has
+	 * been taken out of reset.
+	 */
+	ioex_init(IOEX_C0_NCT38XX);
+	ioex_init(IOEX_C1_NCT38XX);
+
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_C1_TCPC_INT_ODL);
+
+#ifndef CONFIG_ZEPHYR
+	/* Enable BC1.2 interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
+#endif /* !CONFIG_ZEPHYR */
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (gpio_get_level(GPIO_USB_C0_C1_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_0 | PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
+
+int ppc_get_alert_status(int port)
+{
+	if (port == USBC_PORT_C0)
+		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
+	else if (port == USBC_PORT_C1)
+		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
+	return 0;
+}
+
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_C1_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C0);
+		break;
+	default:
+		break;
+	}
+}
+
+void bc12_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_BC12_INT_ODL:
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+		break;
+	case GPIO_USB_C1_BC12_INT_ODL:
+		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+		break;
+	default:
+		break;
+	}
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C1);
+		break;
+	default:
+		break;
+	}
+}
+
+void retimer_interrupt(enum gpio_signal signal)
+{
+	/*
+	 * TODO(b/179513527): add USB-C support
+	 */
+}
+
+__override bool board_is_dts_port(int port)
+{
+	return port == USBC_PORT_C0;
+}
+
+__override bool board_is_tbt_usb4_port(int port)
+{
+	if (port == USBC_PORT_C0 || port == USBC_PORT_C1)
+		return true;
+
+	return false;
+}
+
+__override enum tbt_compat_cable_speed board_get_max_tbt_speed(int port)
+{
+	if (!board_is_tbt_usb4_port(port))
+		return TBT_SS_RES_0;
+
+	return TBT_SS_TBT_GEN3;
+}
diff --git a/board/crota/usbc_config.h b/board/crota/usbc_config.h
new file mode 100644
index 0000000000..1fa7ad4c7a
--- /dev/null
+++ b/board/crota/usbc_config.h
@@ -0,0 +1,17 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Brya board-specific USB-C configuration */
+
+#ifndef __CROS_EC_USBC_CONFIG_H
+#define __CROS_EC_USBC_CONFIG_H
+
+#ifndef CONFIG_ZEPHYR
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#endif
+
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
+
+#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/crota/vif_override.xml b/board/crota/vif_override.xml
new file mode 100644
index 0000000000..db6c426f50
--- /dev/null
+++ b/board/crota/vif_override.xml
@@ -0,0 +1,225 @@
+
+<?xml version="1.0" encoding="utf-8"?>
+<vif:VIF xmlns="http://usb.org/VendorInfoFile.xsd">
+  <vif:Product_Revision>2</vif:Product_Revision>
+  <vif:TID>0</vif:TID>
+  <vif:Product>
+    <vif:USB4_Num_Internal_Host_Controllers value="1" />
+    <vif:USB4_Num_PCIe_DN_Bridges value="0" />
+    <vif:USB4RouterList>
+      <vif:Usb4Router>
+        <!--USB4 Router 0-->
+        <vif:USB4_Router_ID value="0" />
+        <vif:USB4_Num_Lane_Adapters value="4" />
+        <vif:USB4_Num_USB3_DN_Adapters value="1" />
+        <vif:USB4_Num_DP_IN_Adapters value="1" />
+        <vif:USB4_Num_DP_OUT_Adapters value="0" />
+        <vif:USB4_Num_PCIe_DN_Adapters value="4" />
+        <vif:USB4_Num_Unused_Adapters value="0" />
+        <vif:USB4_TBT3_Not_Supported value="0">TBT3 Compatible</vif:USB4_TBT3_Not_Supported>
+        <vif:USB4_PCIe_Wake_Supported value="true" />
+        <vif:USB4_USB3_Wake_Supported value="false" />
+        <vif:USB4_Silicon_VID value="32903">8087</vif:USB4_Silicon_VID>
+        <vif:USB4_PCIe_Switch_Vendor_ID value="32902">8086</vif:USB4_PCIe_Switch_Vendor_ID>
+        <vif:USB4_PCIe_Switch_Device_ID value="17982">463E</vif:USB4_PCIe_Switch_Device_ID>
+        <vif:USB4_TBT3_VID value="32903">8087</vif:USB4_TBT3_VID>
+      </vif:Usb4Router>
+      <vif:Usb4Router>
+        <!--USB4 Router 0-->
+        <vif:USB4_Router_ID value="1" />
+        <vif:USB4_Num_Lane_Adapters value="4" />
+        <vif:USB4_Num_USB3_DN_Adapters value="1" />
+        <vif:USB4_Num_DP_IN_Adapters value="0" />
+        <vif:USB4_Num_DP_OUT_Adapters value="0" />
+        <vif:USB4_Num_PCIe_DN_Adapters value="4" />
+        <vif:USB4_Num_Unused_Adapters value="0" />
+        <vif:USB4_TBT3_Not_Supported value="1">Not TBT3-Compatible</vif:USB4_TBT3_Not_Supported>
+        <vif:USB4_PCIe_Wake_Supported value="true" />
+        <vif:USB4_USB3_Wake_Supported value="false" />
+        <vif:USB4_Silicon_VID value="32903">8087</vif:USB4_Silicon_VID>
+        <vif:USB4_PCIe_Switch_Vendor_ID value="32902">8086</vif:USB4_PCIe_Switch_Vendor_ID>
+        <vif:USB4_PCIe_Switch_Device_ID value="17982">463E</vif:USB4_PCIe_Switch_Device_ID>
+        <vif:USB4_TBT3_VID value="32903">8087</vif:USB4_TBT3_VID>
+      </vif:Usb4Router>
+    </vif:USB4RouterList>
+  </vif:Product>
+  <vif:Component>
+    <!--Component 0: Port 0-->
+    <!--;PD Capabilities-->
+    <vif:DR_Swap_To_DFP_Supported value="true" />
+    <!--;USB Type-C®-->
+    <vif:Type_C_Can_Act_As_Device value="true" />
+    <vif:Type_C_Is_Alt_Mode_Adapter value="true" />
+  
+    <!-- USB4 Port -->
+    <vif:USB4_Lane_0_Adapter value="1" />
+    <vif:USB4_Max_Speed value="1">Gen 3 (40Gb)</vif:USB4_Max_Speed>
+    <vif:USB4_DFP_Supported value="true" />
+    <vif:USB4_UFP_Supported value="false" />
+    <vif:USB4_Num_Retimers value="1" />
+    <vif:USB4_CL1_State_Supported value="true" />
+    <vif:USB4_CL2_State_Supported value="true" />
+    <vif:USB4_USB3_Tunneling_Supported value="true" />
+    <vif:USB4_DP_Tunneling_Supported value="true" />
+    <vif:USB4_DP_Bit_Rate value="3">HBR3</vif:USB4_DP_Bit_Rate>
+    <vif:USB4_Num_DP_Lanes value="4">4 Lanes</vif:USB4_Num_DP_Lanes>
+    <!-- Product Power -->
+    <vif:Product_Total_Source_Power_mW value="22500">22500 mW</vif:Product_Total_Source_Power_mW>
+    <vif:Port_Source_Power_Type value="1">Shared</vif:Port_Source_Power_Type>
+    <vif:Port_Source_Power_Gang>Google</vif:Port_Source_Power_Gang>
+    <vif:Port_Source_Power_Gang_Max_Power value="22500">22500 mW</vif:Port_Source_Power_Gang_Max_Power>
+    <!-- USB Host -->
+    <vif:Host_Speed value="2">USB 3.2 Gen 2x1</vif:Host_Speed>
+    <vif:Host_Contains_Captive_Retimer value="true" />
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:Host_Suspend_Supported value="true" />
+    <!-- USB Device -->
+    <vif:Device_Supports_USB_Data value="true" />
+    <vif:Device_Speed value="2">USB 3.2 Gen 2x1</vif:Device_Speed>
+    <vif:Device_Contains_Captive_Retimer value="true" />
+    <vif:Device_Truncates_DP_For_tDHPResponse value="false" />
+    <!-- PD Source -->
+    <vif:Master_Port value="true"/>
+      <!-- will we ever clear USB_Suspend_Supported? -->
+    <vif:USB_Suspend_May_Be_Cleared value="true" />
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="3">3A @ 5V</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!--Source PDO 1-->
+        <vif:Src_PDO_Supply_Type value="0">Fixed</vif:Src_PDO_Supply_Type>
+        <vif:Src_PDO_Peak_Current value="0">100% IOC</vif:Src_PDO_Peak_Current>
+        <vif:Src_PDO_Voltage value="100">5000 mV</vif:Src_PDO_Voltage>
+        <vif:Src_PDO_Max_Current value="300">3000 mA</vif:Src_PDO_Max_Current>
+        <vif:Src_PD_OCP_OC_Debounce value="50">50 msec</vif:Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="360">3600 mA</vif:Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+    <!-- Dual Role -->
+      <!-- remove FR_Swap_* when we enable CONFIG_USB_PD_FRS -->
+    <vif:FR_Swap_Supported_As_Initial_Sink value="true" />
+    <!-- SOP Discover ID -->
+    <vif:Data_Capable_As_USB_Device_SOP value="true" />
+    <vif:Product_Type_UFP_SOP value="2">PDUSB Peripheral</vif:Product_Type_UFP_SOP>
+    <vif:Product_Type_DFP_SOP value="2">PDUSB Host</vif:Product_Type_DFP_SOP>
+    <vif:Modal_Operation_Supported_SOP value="true" />
+    <vif:USB_VID_SOP value="6353">18D1</USB_VID_SOP>
+    <!-- SOP Modes -->
+    <vif:SVID_Fixed_SOP value="true" />
+    <vif:Num_SVIDs_Min_SOP value="1" />
+    <vif:Num_SVIDs_Max_SOP value="1" />
+    <!-- Bundle: SOPSVIDList -->
+    <vif:SOPSVIDList>
+      <vif:SOPSVID>
+        <!-- SOP SVID 1 -->
+        <vif:SVID_SOP value="32903">8087</vif:SVID_SOP>
+        <vif:SVID_Modes_Fixed_SOP value="true" />
+        <vif:SVID_Num_Modes_Min_SOP value="1" />
+        <vif:SVID_Num_Modes_Max_SOP value="1" />
+        <!-- Bundle: SOPSVIDModeList -->
+        <vif:SOPSVIDModeList>
+          <vif:SOPSVIDMode>
+            <!-- SOP SVID Mode 1 -->
+            <vif:SVID_Mode_Enter_SOP value="true" />
+            <vif:SVID_Mode_Recog_Value_SOP value="1">00000001</vif:SVID_Mode_Recog_Value_SOP>
+          </vif:SOPSVIDMode>
+        </vif:SOPSVIDModeList>
+      </vif:SOPSVID>
+    </vif:SOPSVIDList>
+    <!-- AMA -->
+    <vif:AMA_HW_Vers value="0">0</vif:AMA_HW_Vers>
+    <vif:AMA_FW_Vers value="0">0</vif:AMA_FW_Vers>
+    <vif:AMA_VCONN_Reqd value="false" />
+    <vif:AMA_VBUS_Reqd value="true" />
+    <vif:AMA_Superspeed_Support value="2">USB 3.2 Gen 2</vif:AMA_Superspeed_Support>
+  </vif:Component>
+  <vif:Component>
+    <!-- Component 1: Port 1 -->
+    <!--;PD Capabilities-->
+    <vif:DR_Swap_To_DFP_Supported value="true" />
+    <!-- USB Type-C®-->
+    <vif:Type_C_Can_Act_As_Device value="true" />
+    <vif:Type_C_Is_Alt_Mode_Adapter value="true" />
+    <!-- USB4 Port -->
+    <vif:USB4_Lane_0_Adapter value="1" />
+    <vif:USB4_Max_Speed value="1">Gen 3 (40Gb)</vif:USB4_Max_Speed>
+    <vif:USB4_DFP_Supported value="true" />
+    <vif:USB4_UFP_Supported value="false" />
+    <vif:USB4_Num_Retimers value="1" />
+    <vif:USB4_CL1_State_Supported value="true" />
+    <vif:USB4_CL2_State_Supported value="true" />
+    <vif:USB4_USB3_Tunneling_Supported value="true" />
+    <vif:USB4_DP_Tunneling_Supported value="true" />
+    <vif:USB4_DP_Bit_Rate value="3">HBR3</vif:USB4_DP_Bit_Rate>
+    <vif:USB4_Num_DP_Lanes value="4">4 Lanes</vif:USB4_Num_DP_Lanes>
+    <!-- Product Power -->
+    <vif:Product_Total_Source_Power_mW value="22500">22500 mW</vif:Product_Total_Source_Power_mW>
+    <vif:Port_Source_Power_Type value="1">Shared</vif:Port_Source_Power_Type>
+    <vif:Port_Source_Power_Gang>Google</vif:Port_Source_Power_Gang>
+    <vif:Port_Source_Power_Gang_Max_Power value="22500">22500 mW</vif:Port_Source_Power_Gang_Max_Power>
+    <!-- USB Host-->
+    <vif:Host_Speed value="2">USB 3.2 Gen 2x1</vif:Host_Speed>
+    <vif:Host_Contains_Captive_Retimer value="true" />
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:Host_Suspend_Supported value="true" />
+    
+    <!-- USB Device -->
+    <vif:Device_Supports_USB_Data value="true" />
+    <vif:Device_Speed value="2">USB 3.2 Gen 2x1</vif:Device_Speed>
+    <vif:Device_Contains_Captive_Retimer value="true" />
+    <vif:Device_Truncates_DP_For_tDHPResponse value="false" />
+    <!-- PD Source-->
+    <vif:Master_Port value="true"/>
+      <!-- will we ever clear USB_Suspend_Supported? -->
+    <vif:USB_Suspend_May_Be_Cleared value="true" />
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="3">3A @ 5V</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!--Source PDO 1-->
+        <vif:Src_PDO_Supply_Type value="0">Fixed</vif:Src_PDO_Supply_Type>
+        <vif:Src_PDO_Peak_Current value="0">100% IOC</vif:Src_PDO_Peak_Current>
+        <vif:Src_PDO_Voltage value="100">5000 mV</vif:Src_PDO_Voltage>
+        <vif:Src_PDO_Max_Current value="300">3000 mA</vif:Src_PDO_Max_Current>
+        <vif:Src_PD_OCP_OC_Debounce value="50">50 msec</vif:Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="360">3600 mA</vif:Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+    <!-- Dual Role-->
+      <!-- remove FR_Swap_* when we enable CONFIG_USB_PD_FRS -->
+    <vif:FR_Swap_Supported_As_Initial_Sink value="true" />
+    <!-- SOP Discover ID -->
+    <!-- SOP Discover ID -->
+    <vif:Data_Capable_As_USB_Device_SOP value="true" />
+    <vif:Product_Type_UFP_SOP value="2">PDUSB Peripheral</vif:Product_Type_UFP_SOP>
+    <vif:Product_Type_DFP_SOP value="2">PDUSB Host</vif:Product_Type_DFP_SOP>
+    <vif:Modal_Operation_Supported_SOP value="true" />
+    <vif:USB_VID_SOP value="6353">18D1</USB_VID_SOP>
+    <!-- SOP Modes -->
+    <vif:SVID_Fixed_SOP value="true" />
+    <vif:Num_SVIDs_Min_SOP value="1" />
+    <vif:Num_SVIDs_Max_SOP value="1" />
+    <!-- Bundle: SOPSVIDList -->
+    <vif:SOPSVIDList>
+      <vif:SOPSVID>
+        <!-- SOP SVID 1 -->
+        <vif:SVID_SOP value="32903">8087</vif:SVID_SOP>
+        <vif:SVID_Modes_Fixed_SOP value="true" />
+        <vif:SVID_Num_Modes_Min_SOP value="1" />
+        <vif:SVID_Num_Modes_Max_SOP value="1" />
+        <!-- Bundle: SOPSVIDModeList -->
+        <vif:SOPSVIDModeList>
+          <vif:SOPSVIDMode>
+            <!-- SOP SVID Mode 1 -->
+            <vif:SVID_Mode_Enter_SOP value="true" />
+            <vif:SVID_Mode_Recog_Value_SOP value="1">00000001</vif:SVID_Mode_Recog_Value_SOP>
+          </vif:SOPSVIDMode>
+        </vif:SOPSVIDModeList>
+      </vif:SOPSVID>
+    </vif:SOPSVIDList>
+    <!-- AMA -->
+    <vif:AMA_HW_Vers value="0">0</vif:AMA_HW_Vers>
+    <vif:AMA_FW_Vers value="0">0</vif:AMA_FW_Vers>
+    <vif:AMA_VCONN_Reqd value="false" />
+    <vif:AMA_VBUS_Reqd value="true" />
+    <vif:AMA_Superspeed_Support value="2">USB 3.2 Gen 2</vif:AMA_Superspeed_Support>
+  </vif:Component>
+</vif:VIF>
diff --git a/board/dalboz/battery.c b/board/dalboz/battery.c
index 5a90a767c8..e5adf3c4b3 100644
--- a/board/dalboz/battery.c
+++ b/board/dalboz/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/dalboz/board.c b/board/dalboz/board.c
index f0a0e23c2b..20b8a0b9a8 100644
--- a/board/dalboz/board.c
+++ b/board/dalboz/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,7 +10,7 @@
 #include "driver/accelgyro_lsm6dsm.h"
 #include "driver/bc12/pi3usb9201.h"
 #include "driver/ioexpander/pcal6408.h"
-#include "driver/ppc/aoz1380.h"
+#include "driver/ppc/aoz1380_public.h"
 #include "driver/ppc/nx20p348x.h"
 #include "driver/retimer/pi3hdx1204.h"
 #include "driver/tcpm/nct38xx.h"
@@ -36,8 +36,8 @@
 #include "usb_pd_tcpm.h"
 #include "usbc_ppc.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* This I2C moved. Temporarily detect and support the V0 HW. */
 int I2C_PORT_BATTERY = I2C_PORT_BATTERY_V1;
@@ -73,10 +73,9 @@ void hdmi_hpd_interrupt(enum gpio_signal signal)
 	hook_call_deferred(&hdmi_hpd_handler_data, (2 * MSEC));
 }
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
-#ifdef HAS_TASK_MOTIONSENSE
-
 /* Motion sensors */
 static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
@@ -86,11 +85,9 @@ static struct stprivate_data g_lis2dwl_data;
 static struct lsm6dsm_data g_lsm6dsm_data = LSM6DSM_DATA;
 
 /* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, FLOAT_TO_FP(-1), 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
 
 /* TODO(gcc >= 5.0) Remove the casts to const pointer at rot_standard_ref */
 struct motion_sensor_t motion_sensors[] = {
@@ -131,11 +128,9 @@ struct motion_sensor_t motion_sensors[] = {
 	 .mutex = &g_base_mutex,
 	 .drv_data = LSM6DSM_ST_DATA(g_lsm6dsm_data,
 			MOTIONSENSE_TYPE_ACCEL),
-	 .int_signal = GPIO_6AXIS_INT_L,
-	 .flags = MOTIONSENSE_FLAG_INT_SIGNAL,
 	 .port = I2C_PORT_SENSOR,
 	 .i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-	 .default_range = 4, /* g, enough for laptop */
+	 .default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
 	 .rot_standard_ref = &base_standard_ref,
 	 .min_frequency = LSM6DSM_ODR_MIN_VAL,
 	 .max_frequency = LSM6DSM_ODR_MAX_VAL,
@@ -163,8 +158,6 @@ struct motion_sensor_t motion_sensors[] = {
 	 .mutex = &g_base_mutex,
 	 .drv_data = LSM6DSM_ST_DATA(g_lsm6dsm_data,
 			MOTIONSENSE_TYPE_GYRO),
-	.int_signal = GPIO_6AXIS_INT_L,
-	.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
 	 .port = I2C_PORT_SENSOR,
 	 .i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
 	 .default_range = 1000 | ROUND_UP_FLAG, /* dps */
@@ -176,11 +169,9 @@ struct motion_sensor_t motion_sensors[] = {
 
 unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
-#endif /* HAS_TASK_MOTIONSENSE */
-
 /* These IO expander GPIOs vary with DB option. */
-enum gpio_signal IOEX_USB_A1_RETIMER_EN = IOEX_USB_A1_RETIMER_EN_OPT1;
-enum gpio_signal IOEX_USB_A1_CHARGE_EN_DB_L = IOEX_USB_A1_CHARGE_EN_DB_L_OPT1;
+enum ioex_signal IOEX_USB_A1_RETIMER_EN = IOEX_USB_A1_RETIMER_EN_OPT1;
+enum ioex_signal IOEX_USB_A1_CHARGE_EN_DB_L = IOEX_USB_A1_CHARGE_EN_DB_L_OPT1;
 
 static void pcal6408_handler(void)
 {
@@ -196,7 +187,7 @@ void pcal6408_interrupt(enum gpio_signal signal)
 const struct pi3hdx1204_tuning pi3hdx1204_tuning = {
 	.eq_ch0_ch1_offset = PI3HDX1204_EQ_DB710,
 	.eq_ch2_ch3_offset = PI3HDX1204_EQ_DB710,
-	.vod_offset = PI3HDX1204_VOD_115_ALL_CHANNELS,
+	.vod_offset = PI3HDX1204_VOD_130_ALL_CHANNELS,
 	.de_offset = PI3HDX1204_DE_DB_MINUS5,
 };
 
@@ -211,9 +202,7 @@ static void board_chipset_resume(void)
 	if (ec_config_has_hdmi_retimer_pi3hdx1204()) {
 		ioex_set_level(IOEX_EN_PWR_HDMI_DB, 1);
 		msleep(PI3HDX1204_POWER_ON_DELAY_MS);
-		pi3hdx1204_enable(I2C_PORT_TCPC1,
-				  PI3HDX1204_I2C_ADDR_FLAGS,
-				  1);
+		pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS, 1);
 	}
 }
 DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
@@ -223,16 +212,13 @@ static void board_chipset_suspend(void)
 	ioex_set_level(IOEX_USB_A1_RETIMER_EN, 0);
 
 	if (ec_config_has_hdmi_retimer_pi3hdx1204()) {
-		pi3hdx1204_enable(I2C_PORT_TCPC1,
-				  PI3HDX1204_I2C_ADDR_FLAGS,
-				  0);
+		pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS, 0);
 		ioex_set_level(IOEX_EN_PWR_HDMI_DB, 0);
 	}
 }
 DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
 
-static int board_ps8743_mux_set(const struct usb_mux *me,
-				mux_state_t mux_state)
+static int board_ps8743_mux_set(const struct usb_mux *me, mux_state_t mux_state)
 {
 	if (mux_state & USB_PD_MUX_DP_ENABLED)
 		/* Enable IN_HPD on the DB */
@@ -244,7 +230,6 @@ static int board_ps8743_mux_set(const struct usb_mux *me,
 	return EC_SUCCESS;
 }
 
-
 /*****************************************************************************
  * USB-C
  */
@@ -254,8 +239,12 @@ static int board_ps8743_mux_set(const struct usb_mux *me,
  * chip and it need a board specific driver.
  * Overall, it will use chained mux framework.
  */
-static int fsusb42umx_set_mux(const struct usb_mux *me, mux_state_t mux_state)
+static int fsusb42umx_set_mux(const struct usb_mux *me, mux_state_t mux_state,
+			      bool *ack_required)
 {
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
 	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
 		ioex_set_level(IOEX_USB_C0_SBU_FLIP, 1);
 	else
@@ -278,33 +267,45 @@ const struct usb_mux_driver usbc0_sbu_mux_driver = {
  * Since FSUSB42UMX is not a i2c device, .i2c_port and
  * .i2c_addr_flags are not required here.
  */
-const struct usb_mux usbc0_sbu_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &usbc0_sbu_mux_driver,
+const struct usb_mux_chain usbc0_sbu_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &usbc0_sbu_mux_driver,
+		},
 };
 
-struct usb_mux usbc1_amd_fp5_usb_mux = {
+struct usb_mux usbc1_ps8xxx_mux = {
 	.usb_port = USBC_PORT_C1,
-	.i2c_port = I2C_PORT_USB_AP_MUX,
-	.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
-	.driver = &amd_fp5_usb_mux_driver,
-	.flags = USB_MUX_FLAG_SET_WITHOUT_FLIP,
+	.i2c_port = I2C_PORT_TCPC1,
+	.i2c_addr_flags = PS8743_I2C_ADDR1_FLAG,
+	.driver = &ps8743_usb_mux_driver,
+};
+
+struct usb_mux_chain usbc1_amd_fp5_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.i2c_port = I2C_PORT_USB_AP_MUX,
+			.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
+			.driver = &amd_fp5_usb_mux_driver,
+			.flags = USB_MUX_FLAG_SET_WITHOUT_FLIP,
+		},
 };
 
-struct usb_mux usb_muxes[] = {
+struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.i2c_port = I2C_PORT_USB_AP_MUX,
-		.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
-		.driver = &amd_fp5_usb_mux_driver,
-		.next_mux = &usbc0_sbu_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.i2c_port = I2C_PORT_USB_AP_MUX,
+			.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
+			.driver = &amd_fp5_usb_mux_driver,
+		},
+		.next = &usbc0_sbu_mux,
 	},
 	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = PS8743_I2C_ADDR1_FLAG,
-		.driver = &ps8743_usb_mux_driver,
-		.next_mux = &usbc1_amd_fp5_usb_mux,
+		.mux = &usbc1_ps8xxx_mux,
+		.next = &usbc1_amd_fp5_usb_mux,
 	}
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
@@ -347,8 +348,7 @@ void ppc_interrupt(enum gpio_signal signal)
 
 int board_set_active_charge_port(int port)
 {
-	int is_valid_port = (port >= 0 &&
-			     port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	int i;
 
 	if (port == CHARGE_PORT_NONE) {
@@ -369,7 +369,6 @@ int board_set_active_charge_port(int port)
 		return EC_ERROR_INVAL;
 	}
 
-
 	/* Check if the port is sourcing VBUS. */
 	if (ppc_is_sourcing_vbus(port)) {
 		CPRINTFUSB("Skip enable C%d", port);
@@ -451,27 +450,33 @@ const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
 
-static void reset_pd_port(int port, enum gpio_signal reset_gpio_l,
-			  int hold_delay, int finish_delay)
+static void reset_nct38xx_port(int port)
 {
+	enum gpio_signal reset_gpio_l;
+
+	if (port == USBC_PORT_C0)
+		reset_gpio_l = GPIO_USB_C0_TCPC_RST_L;
+	else if (port == USBC_PORT_C1)
+		reset_gpio_l = GPIO_USB_C1_TCPC_RST_L;
+	else
+		/* Invalid port: do nothing */
+		return;
+
 	gpio_set_level(reset_gpio_l, 0);
-	msleep(hold_delay);
+	msleep(NCT38XX_RESET_HOLD_DELAY_MS);
 	gpio_set_level(reset_gpio_l, 1);
-	if (finish_delay)
-		msleep(finish_delay);
+	nct38xx_reset_notify(port);
+	if (NCT3807_RESET_POST_DELAY_MS != 0)
+		msleep(NCT3807_RESET_POST_DELAY_MS);
 }
 
 void board_reset_pd_mcu(void)
 {
 	/* Reset TCPC0 */
-	reset_pd_port(USBC_PORT_C0, GPIO_USB_C0_TCPC_RST_L,
-		      NCT38XX_RESET_HOLD_DELAY_MS,
-		      NCT38XX_RESET_POST_DELAY_MS);
+	reset_nct38xx_port(USBC_PORT_C0);
 
 	/* Reset TCPC1 */
-	reset_pd_port(USBC_PORT_C1, GPIO_USB_C1_TCPC_RST_L,
-		      NCT38XX_RESET_HOLD_DELAY_MS,
-		      NCT38XX_RESET_POST_DELAY_MS);
+	reset_nct38xx_port(USBC_PORT_C1);
 }
 
 uint16_t tcpc_get_alert_status(void)
@@ -517,11 +522,11 @@ void bc12_interrupt(enum gpio_signal signal)
 {
 	switch (signal) {
 	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
 		break;
 
 	case GPIO_USB_C1_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12, 0);
+		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
 		break;
 
 	default:
@@ -535,11 +540,9 @@ int board_pd_set_frs_enable(int port, int enable)
 
 	/* Use the TCPC to enable fast switch when FRS included */
 	if (port == USBC_PORT_C0) {
-		rv = ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN,
-				    !!enable);
+		rv = ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN, !!enable);
 	} else {
-		rv = ioex_set_level(IOEX_USB_C1_TCPC_FASTSW_CTL_EN,
-				    !!enable);
+		rv = ioex_set_level(IOEX_USB_C1_TCPC_FASTSW_CTL_EN, !!enable);
 	}
 
 	return rv;
@@ -549,17 +552,17 @@ static void setup_fw_config(void)
 {
 	uint32_t board_version = 0;
 
-	if (cbi_get_board_version(&board_version) == EC_SUCCESS
-	    && board_version >= 2) {
+	if (cbi_get_board_version(&board_version) == EC_SUCCESS &&
+	    board_version >= 2) {
 		ccprints("PS8743 USB MUX");
-		usb_muxes[USBC_PORT_C1].i2c_addr_flags = PS8743_I2C_ADDR1_FLAG;
-		usb_muxes[USBC_PORT_C1].driver = &ps8743_usb_mux_driver;
-		usb_muxes[USBC_PORT_C1].board_set = &board_ps8743_mux_set;
+		usbc1_ps8xxx_mux.i2c_addr_flags = PS8743_I2C_ADDR1_FLAG;
+		usbc1_ps8xxx_mux.driver = &ps8743_usb_mux_driver;
+		usbc1_ps8xxx_mux.board_set = &board_ps8743_mux_set;
 	} else {
 		ccprints("PS8740 USB MUX");
-		usb_muxes[USBC_PORT_C1].i2c_addr_flags = PS8740_I2C_ADDR0_FLAG;
-		usb_muxes[USBC_PORT_C1].driver = &ps8740_usb_mux_driver;
-		usb_muxes[USBC_PORT_C1].board_set = NULL;
+		usbc1_ps8xxx_mux.i2c_addr_flags = PS8740_I2C_ADDR0_FLAG;
+		usbc1_ps8xxx_mux.driver = &ps8740_usb_mux_driver;
+		usbc1_ps8xxx_mux.board_set = NULL;
 	}
 
 	if (ec_config_get_usb_db() == DALBOZ_DB_D_OPT2_USBA_HDMI) {
@@ -604,7 +607,7 @@ static void setup_fw_config(void)
 	} else {
 		motion_sensor_count = 0;
 		/* Device is clamshell only */
-		tablet_set_mode(0);
+		tablet_set_mode(0, TABLET_TRIGGER_LID);
 		/* Gyro is not present, don't allow line to float */
 		gpio_set_flags(GPIO_6AXIS_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
 	}
@@ -626,20 +629,20 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 struct ioexpander_config_t ioex_config[] = {
 	[IOEX_C0_NCT3807] = {
 		.i2c_host_port = I2C_PORT_TCPC0,
-		.i2c_slave_addr = NCT38XX_I2C_ADDR1_1_FLAGS,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
 		.drv = &nct38xx_ioexpander_drv,
 	},
 	[IOEX_C1_NCT3807] = {
 		.i2c_host_port = I2C_PORT_TCPC1,
-		.i2c_slave_addr = NCT38XX_I2C_ADDR1_1_FLAGS,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
 		.drv = &nct38xx_ioexpander_drv,
-		.flags = IOEX_FLAGS_DISABLED,
+		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
 	},
 	[IOEX_HDMI_PCAL6408] = {
 		.i2c_host_port = I2C_PORT_TCPC1,
-		.i2c_slave_addr = PCAL6408_I2C_ADDR0,
+		.i2c_addr_flags = PCAL6408_I2C_ADDR0,
 		.drv = &pcal6408_ioexpander_drv,
-		.flags = IOEX_FLAGS_DISABLED,
+		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT);
diff --git a/board/dalboz/board.h b/board/dalboz/board.h
index 9fa8ac6094..0d77b7be06 100644
--- a/board/dalboz/board.h
+++ b/board/dalboz/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,11 +10,11 @@
 
 #define VARIANT_ZORK_DALBOZ
 
-#include <stdbool.h>
 #include "baseboard.h"
 
+#include <stdbool.h>
+
 #define CONFIG_IO_EXPANDER_PCAL6408
-#define CONFIG_MKBP_USE_GPIO
 
 #define CONFIG_USBC_PPC_NX20P3483
 #define CONFIG_USB_MUX_PS8740
@@ -28,15 +28,11 @@
 #define GPIO_USB1_ILIM_SEL IOEX_USB_A0_CHARGE_EN_L
 #define GPIO_USB2_ILIM_SEL IOEX_USB_A1_CHARGE_EN_DB_L
 
-/* Power  LEDs */
-#define CONFIG_LED_POWER_LED
-
 /* Motion sensing drivers */
 #define CONFIG_ACCELGYRO_LSM6DSM
 #define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 #define CONFIG_ACCEL_LIS2DWL
-#define CONFIG_ACCEL_INTERRUPTS
 #define CONFIG_CMD_ACCELS
 #define CONFIG_CMD_ACCEL_INFO
 #define CONFIG_TABLET_MODE
@@ -45,42 +41,36 @@
 #define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
 #define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
 
-
-
 /* GPIO mapping from board specific name to EC common name. */
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_EC_BATT_PRES_ODL
-#define CONFIG_SCI_GPIO			GPIO_EC_FCH_SCI_ODL
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_AP_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT_L		GPIO_EC_EDP_BL_DISABLE
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_FCH_PWR_BTN_L
-#define GPIO_PCH_RSMRST_L		GPIO_EC_FCH_RSMRST_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S5_L		GPIO_SLP_S5_L
-#define GPIO_PCH_SYS_PWROK		GPIO_EC_FCH_PWROK
-#define GPIO_PCH_WAKE_L			GPIO_EC_FCH_WAKE_L
-#define GPIO_POWER_BUTTON_L		GPIO_EC_PWR_BTN_ODL
-#define GPIO_S0_PGOOD			GPIO_S0_PWROK_OD
-#define GPIO_S5_PGOOD			GPIO_EC_PWROK_OD
-#define GPIO_SYS_RESET_L		GPIO_EC_SYS_RST_L
-#define GPIO_VOLUME_DOWN_L		GPIO_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
+#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL
+#define CONFIG_SCI_GPIO GPIO_EC_FCH_SCI_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_AP_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_EDP_BL_DISABLE
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PCH_PWRBTN_L GPIO_EC_FCH_PWR_BTN_L
+#define GPIO_PCH_RSMRST_L GPIO_EC_FCH_RSMRST_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L
+#define GPIO_PCH_SYS_PWROK GPIO_EC_FCH_PWROK
+#define GPIO_PCH_WAKE_L GPIO_EC_FCH_WAKE_L
+#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL
+#define GPIO_S0_PGOOD GPIO_S0_PWROK_OD
+#define GPIO_S5_PGOOD GPIO_EC_PWROK_OD
+#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L
+#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
 
 #ifndef __ASSEMBLER__
 
 /* This I2C moved. Temporarily detect and support the V0 HW. */
 extern int I2C_PORT_BATTERY;
 
-enum adc_channel {
-	ADC_TEMP_SENSOR_CHARGER,
-	ADC_TEMP_SENSOR_SOC,
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_TEMP_SENSOR_CHARGER, ADC_TEMP_SENSOR_SOC, ADC_CH_COUNT };
 
 enum battery_type {
 	BATTERY_SMP,
@@ -89,10 +79,7 @@ enum battery_type {
 	BATTERY_TYPE_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_COUNT };
 
 enum ioex_port {
 	IOEX_C0_NCT3807 = 0,
@@ -101,9 +88,7 @@ enum ioex_port {
 	IOEX_PORT_COUNT
 };
 
-#define PORT_TO_HPD(port) ((port == 0) \
-	? GPIO_USB3_C0_DP2_HPD \
-	: GPIO_DP1_HPD)
+#define PORT_TO_HPD(port) ((port == 0) ? GPIO_USB3_C0_DP2_HPD : GPIO_DP1_HPD)
 
 enum temp_sensor_id {
 	TEMP_SENSOR_CHARGER = 0,
@@ -112,22 +97,13 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum usba_port {
-	USBA_PORT_A0 = 0,
-	USBA_PORT_A1,
-	USBA_PORT_COUNT
-};
+enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT };
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 /*****************************************************************************
  * CBI EC FW Configuration
  */
-#include "cbi_ec_fw_config.h"
 
 /**
  * DALBOZ_MB_USBAC
@@ -170,36 +146,32 @@ enum ec_cfg_usb_db_type {
 	DALBOZ_DB_D_OPT2_USBA_HDMI = 1,
 };
 
-#define HAS_USBC1 \
-			(BIT(DALBOZ_DB_D_OPT1_USBAC))
+#include "cbi_ec_fw_config.h"
+
+#define HAS_USBC1 (BIT(DALBOZ_DB_D_OPT1_USBAC))
 
 static inline bool ec_config_has_usbc1(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_USBC1);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_USBC1);
 }
 
-#define HAS_USBC1_RETIMER_PS8740 \
-			(BIT(DALBOZ_DB_D_OPT1_USBAC))
+#define HAS_USBC1_RETIMER_PS8740 (BIT(DALBOZ_DB_D_OPT1_USBAC))
 
 static inline bool ec_config_has_usbc1_retimer_ps8740(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_USBC1_RETIMER_PS8740);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_USBC1_RETIMER_PS8740);
 }
 
-#define HAS_HDMI_RETIMER_PI3HDX1204 \
-			(BIT(DALBOZ_DB_D_OPT2_USBA_HDMI))
+#define HAS_HDMI_RETIMER_PI3HDX1204 (BIT(DALBOZ_DB_D_OPT2_USBA_HDMI))
 
 static inline bool ec_config_has_hdmi_retimer_pi3hdx1204(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_HDMI_RETIMER_PI3HDX1204);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_HDMI_RETIMER_PI3HDX1204);
 }
 
 /* These IO expander GPIOs vary with DB option. */
-extern enum gpio_signal IOEX_USB_A1_RETIMER_EN;
-extern enum gpio_signal IOEX_USB_A1_CHARGE_EN_DB_L;
+extern enum ioex_signal IOEX_USB_A1_RETIMER_EN;
+extern enum ioex_signal IOEX_USB_A1_CHARGE_EN_DB_L;
 
 void board_reset_pd_mcu(void);
 
diff --git a/board/dalboz/build.mk b/board/dalboz/build.mk
index 4ca0cbd96f..cd58c2b91b 100644
--- a/board/dalboz/build.mk
+++ b/board/dalboz/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/dalboz/ec.tasklist b/board/dalboz/ec.tasklist
index 41b83cf4f3..4bb60ed55d 100644
--- a/board/dalboz/ec.tasklist
+++ b/board/dalboz/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/dalboz/gpio.inc b/board/dalboz/gpio.inc
index 74fe019b47..386898f013 100644
--- a/board/dalboz/gpio.inc
+++ b/board/dalboz/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/dalboz/led.c b/board/dalboz/led.c
index 6ef9c26e8c..d9614539e5 100644
--- a/board/dalboz/led.c
+++ b/board/dalboz/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,47 +8,55 @@
 #include "led_common.h"
 #include "led_onoff_states.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
-const int led_charge_lvl_1;
-const int led_charge_lvl_2 = 100;
+__override const int led_charge_lvl_1;
+__override const int led_charge_lvl_2 = 100;
 
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]       = {{EC_LED_COLOR_GREEN,  2 * LED_ONE_SEC},
-					{EC_LED_COLOR_RED, 2 * LED_ONE_SEC} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_GREEN,  2 * LED_ONE_SEC},
-					{EC_LED_COLOR_RED, 2 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-};
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_GREEN,
+					     2 * LED_ONE_SEC },
+					   { EC_LED_COLOR_RED,
+					     2 * LED_ONE_SEC } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_GREEN,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_GREEN,
+					    2 * LED_ONE_SEC },
+					  { EC_LED_COLOR_RED,
+					    2 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_GREEN,
+					   LED_INDEFINITE } },
+	};
 
 BUILD_ASSERT(ARRAY_SIZE(led_bat_state_table) == LED_NUM_STATES);
 
-const struct led_descriptor
-			led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-				{LED_OFF,          0.5 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 3 * LED_ONE_SEC },
+					       { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
 BUILD_ASSERT(ARRAY_SIZE(led_pwr_state_table) == PWR_LED_NUM_STATES);
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-void led_set_color_power(enum ec_led_colors color)
+__override void led_set_color_power(enum ec_led_colors color)
 {
 	if (color == EC_LED_COLOR_WHITE)
 		gpio_set_level(GPIO_LED3_PWM, LED_ON_LVL);
@@ -57,7 +65,7 @@ void led_set_color_power(enum ec_led_colors color)
 		gpio_set_level(GPIO_LED3_PWM, LED_OFF_LVL);
 }
 
-void led_set_color_battery(enum ec_led_colors color)
+__override void led_set_color_battery(enum ec_led_colors color)
 {
 	switch (color) {
 	case EC_LED_COLOR_GREEN:
diff --git a/board/dalboz/vif_override.xml b/board/dalboz/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/dalboz/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/damu/battery.c b/board/damu/battery.c
index c85240a108..2c3b259a23 100644
--- a/board/damu/battery.c
+++ b/board/damu/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/damu/board.c b/board/damu/board.c
index 280e834c85..3704b019cc 100644
--- a/board/damu/board.c
+++ b/board/damu/board.c
@@ -1,10 +1,9 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "backlight.h"
 #include "button.h"
 #include "charge_manager.h"
@@ -31,6 +30,7 @@
 #include "it8801.h"
 #include "keyboard_scan.h"
 #include "lid_switch.h"
+#include "panic.h"
 #include "power.h"
 #include "power_button.h"
 #include "pwm.h"
@@ -40,41 +40,55 @@
 #include "system.h"
 #include "tablet_mode.h"
 #include "task.h"
-#include "tcpm.h"
+#include "tcpm/tcpm.h"
 #include "timer.h"
 #include "usb_charge.h"
 #include "usb_mux.h"
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
 	schedule_deferred_pd_interrupt(0 /* port */);
 }
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /******************************************************************************/
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] =  {"BOARD_ID",  3300, 4096, 0, STM32_AIN(10)},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)},
+	[ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(10) },
+	[ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /******************************************************************************/
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{"typec", 0, 400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"other", 1, 100, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
+	{ .name = "typec",
+	  .port = 0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "other",
+	  .port = 1,
+	  .kbps = 100,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
 const struct i2c_port_t i2c_bitbang_ports[] = {
-	{"battery", 2, 100, GPIO_I2C3_SCL, GPIO_I2C3_SDA, .drv = &bitbang_drv},
+	{ .name = "battery",
+	  .port = 2,
+	  .kbps = 100,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA,
+	  .drv = &bitbang_drv },
 };
 const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
 
@@ -82,13 +96,13 @@ const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
 
 /* power signal list.  Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
+	{ GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" },
+	{ GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" },
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
 /* Keyboard scan setting */
-struct keyboard_scan_config keyscan_config = {
+__override struct keyboard_scan_config keyscan_config = {
 	/*
 	 * TODO(b/133200075): Tune this once we have the final performance
 	 * out of the driver and the i2c bus.
@@ -107,8 +121,8 @@ struct keyboard_scan_config keyscan_config = {
 
 struct ioexpander_config_t ioex_config[CONFIG_IO_EXPANDER_PORT_COUNT] = {
 	[0] = {
-		.i2c_host_port = I2C_PORT_IO_EXPANDER_IT8801,
-		.i2c_slave_addr = IT8801_I2C_ADDR,
+		.i2c_host_port = I2C_PORT_KB_DISCRETE,
+		.i2c_addr_flags = IT8801_I2C_ADDR1,
 		.drv = &it8801_ioexpander_drv,
 	},
 };
@@ -133,15 +147,18 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = I2C_PORT_TCPC0,
-			.addr_flags = FUSB302_I2C_SLAVE_ADDR_FLAGS,
+			.addr_flags = FUSB302_I2C_ADDR_FLAGS,
 		},
 		.drv = &fusb302_tcpm_drv,
 	},
 };
 
-static void board_hpd_status(const struct usb_mux *me,
-			     int hpd_lvl, int hpd_irq)
+static void board_hpd_status(const struct usb_mux *me, mux_state_t mux_state,
+			     bool *ack_required)
 {
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
 	/*
 	 * svdm_dp_attention() did most of the work, we only need to notify
 	 * host here.
@@ -149,13 +166,16 @@ static void board_hpd_status(const struct usb_mux *me,
 	host_set_single_event(EC_HOST_EVENT_USB_MUX);
 }
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+				.hpd_update = &board_hpd_status,
+			},
 	},
 };
 
@@ -201,7 +221,7 @@ int board_set_active_charge_port(int charge_port)
 		if (board_vbus_source_enabled(charge_port))
 			return -1;
 		break;
-	case CHARGE_PORT_NONE:
+	default:
 		/*
 		 * To ensure the fuel gauge (max17055) is always powered
 		 * even when battery is disconnected, keep VBAT rail on but
@@ -209,22 +229,11 @@ int board_set_active_charge_port(int charge_port)
 		 */
 		charger_set_current(CHARGER_SOLO, 0);
 		break;
-	default:
-		panic("Invalid charge port\n");
-		break;
 	}
 
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-			       CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
-
 int board_discharge_on_ac(int enable)
 {
 	int ret, port;
@@ -254,7 +263,7 @@ int pd_snk_is_vbus_provided(int port)
 
 void bc12_interrupt(enum gpio_signal signal)
 {
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
 }
 
 #ifndef VARIANT_KUKUI_NO_SENSORS
@@ -274,13 +283,12 @@ static void board_spi_enable(void)
 	STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
 
 	/* Reinitialize spi peripheral. */
-	spi_enable(CONFIG_SPI_ACCEL_PORT, 1);
+	spi_enable(&spi_devices[0], 1);
 
 	/* Pin mux spi peripheral toward the sensor. */
-	gpio_config_module(MODULE_SPI_MASTER, 1);
+	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
 }
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP,
-	     board_spi_enable,
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_spi_enable,
 	     MOTION_SENSE_HOOK_PRIO - 1);
 
 static void board_spi_disable(void)
@@ -288,14 +296,13 @@ static void board_spi_disable(void)
 	/* Set pins to a state calming the sensor down. */
 	gpio_set_flags(GPIO_EC_SENSOR_SPI_CK, GPIO_OUT_LOW);
 	gpio_set_level(GPIO_EC_SENSOR_SPI_CK, 0);
-	gpio_config_module(MODULE_SPI_MASTER, 0);
+	gpio_config_module(MODULE_SPI_CONTROLLER, 0);
 
 	/* Disable spi peripheral and clocks. */
-	spi_enable(CONFIG_SPI_ACCEL_PORT, 0);
+	spi_enable(&spi_devices[0], 0);
 	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
 }
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN,
-	     board_spi_disable,
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_spi_disable,
 	     MOTION_SENSE_HOOK_PRIO + 1);
 #endif /* !VARIANT_KUKUI_NO_SENSORS */
 
@@ -334,17 +341,13 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Rotation matrixes */
-static const mat33_fp_t base_standard_ref = {
-	{FLOAT_TO_FP(1), 0, 0},
-	{0, FLOAT_TO_FP(-1), 0},
-	{0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, FLOAT_TO_FP(-1), 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
 
-static const mat33_fp_t lid_standard_ref = {
-	{FLOAT_TO_FP(1), 0, 0},
-	{0, FLOAT_TO_FP(1), 0},
-	{0, 0, FLOAT_TO_FP(1) }
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(1), 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
 
 /* sensor private data */
 /* Lid accel private data */
@@ -394,9 +397,10 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_base_mutex,
 		.drv_data = &g_bmi160_data,
 		.port = CONFIG_SPI_ACCEL_PORT,
-		.i2c_spi_addr_flags = SLAVE_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
+		.i2c_spi_addr_flags =
+				ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
 		.rot_standard_ref = &base_standard_ref,
-		.default_range = 2,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
+		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
 		.min_frequency = BMI_ACCEL_MIN_FREQ,
 		.max_frequency = BMI_ACCEL_MAX_FREQ,
 		.config = {
@@ -422,7 +426,8 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_base_mutex,
 		.drv_data = &g_bmi160_data,
 		.port = CONFIG_SPI_ACCEL_PORT,
-		.i2c_spi_addr_flags = SLAVE_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
+		.i2c_spi_addr_flags =
+				ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
 		.default_range = 1000, /* dps */
 		.rot_standard_ref = &base_standard_ref,
 		.min_frequency = BMI_GYRO_MIN_FREQ,
@@ -452,16 +457,3 @@ int board_get_charger_i2c(void)
 	/* TODO(b:138415463): confirm the bus allocation for future builds */
 	return board_get_version() == 1 ? 2 : 1;
 }
-
-/* Enable or disable input devices, based on chipset state and tablet mode */
-#ifndef TEST_BUILD
-void lid_angle_peripheral_enable(int enable)
-{
-	/* If the lid is in 360 position, ignore the lid angle,
-	 * which might be faulty. Disable keyboard.
-	 */
-	if (tablet_get_mode() || chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		enable = 0;
-	keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
-}
-#endif
diff --git a/board/damu/board.h b/board/damu/board.h
index e5de9c205c..64aa8404ec 100644
--- a/board/damu/board.h
+++ b/board/damu/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,9 +8,13 @@
 #ifndef __CROS_EC_BOARD_H
 #define __CROS_EC_BOARD_H
 
+/* Save some flash space */
+#undef CONFIG_CHARGE_DEBUG
+
 #define VARIANT_KUKUI_JACUZZI
 #define VARIANT_KUKUI_BATTERY_SMART
 #define VARIANT_KUKUI_CHARGER_ISL9238
+#define VARIANT_KUKUI_EC_STM32F098
 
 #ifndef SECTION_IS_RW
 #define VARIANT_KUKUI_NO_SENSORS
@@ -18,6 +22,9 @@
 
 #include "baseboard.h"
 
+/* Disable deferred (async) flash protect*/
+#undef CONFIG_FLASH_PROTECT_DEFERRED
+
 #undef CONFIG_CHIPSET_POWER_SEQ_VERSION
 #define CONFIG_CHIPSET_POWER_SEQ_VERSION 1
 
@@ -27,6 +34,8 @@
 #define CONFIG_BATTERY_HW_PRESENT_CUSTOM
 
 #define CONFIG_CHARGER_PSYS
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 5
 
 #define CONFIG_CHARGER_RUNTIME_CONFIG
 
@@ -50,14 +59,12 @@
 #define CONFIG_USB_MUX_IT5205
 
 #define CONFIG_LED_ONOFF_STATES
-#define CONFIG_LED_POWER_LED
 #define CONFIG_LED_COMMON
 
 /* Motion Sensors */
 #ifndef VARIANT_KUKUI_NO_SENSORS
-#define CONFIG_ACCEL_LIS2DWL   	/* Lid accel */
+#define CONFIG_ACCEL_LIS2DWL /* Lid accel */
 #define CONFIG_ACCELGYRO_BMI160 /* Base accel */
-#define CONFIG_ACCEL_INTERRUPTS
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 #define CONFIG_CMD_ACCEL_INFO
@@ -72,25 +79,27 @@
 #endif /* VARIANT_KUKUI_NO_SENSORS */
 
 /* I2C ports */
-#define I2C_PORT_BC12               0
-#define I2C_PORT_TCPC0              0
-#define I2C_PORT_USB_MUX            0
-#define I2C_PORT_BATTERY            2
-#define I2C_PORT_CHARGER            board_get_charger_i2c()
-#define I2C_PORT_SENSORS            1
-#define I2C_PORT_IO_EXPANDER_IT8801 1
-#define I2C_PORT_VIRTUAL_BATTERY    I2C_PORT_BATTERY
+#define I2C_PORT_BC12 0
+#define I2C_PORT_TCPC0 0
+#define I2C_PORT_USB_MUX 0
+#define I2C_PORT_BATTERY 2
+#define I2C_PORT_CHARGER board_get_charger_i2c()
+#define I2C_PORT_SENSORS 1
+#define I2C_PORT_KB_DISCRETE 1
+#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
+
+/* IT8801 I2C address */
+#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1
 
 /* Enable Accel over SPI */
-#define CONFIG_SPI_ACCEL_PORT    0  /* The first SPI master port (SPI2) */
+#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */
 
 #define CONFIG_KEYBOARD_PROTOCOL_MKBP
 #define CONFIG_MKBP_EVENT
 #define CONFIG_MKBP_USE_GPIO
-/* Define the MKBP events which are allowed to wakeup AP in S3. */
-#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \
-		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+/* Virutal battery optional MFG function */
+#define CONFIG_SMART_BATTERY_OPTIONAL_MFG_FUNC
 
 #ifndef __ASSEMBLER__
 
@@ -138,7 +147,6 @@ void emmc_cmd_interrupt(enum gpio_signal signal);
 void bc12_interrupt(enum gpio_signal signal);
 void board_reset_pd_mcu(void);
 int board_get_version(void);
-int board_is_sourcing_vbus(int port);
 
 /* returns the i2c port number of charger */
 int board_get_charger_i2c(void);
diff --git a/board/damu/build.mk b/board/damu/build.mk
index 0b3565fd84..6a7e557a0e 100644
--- a/board/damu/build.mk
+++ b/board/damu/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/damu/ec.tasklist b/board/damu/ec.tasklist
index 19d2f34687..30e9967a0a 100644
--- a/board/damu/ec.tasklist
+++ b/board/damu/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/damu/gpio.inc b/board/damu/gpio.inc
index ba565b4772..9db5b49238 100644
--- a/board/damu/gpio.inc
+++ b/board/damu/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -111,5 +111,5 @@ ALTERNATE(PIN_MASK(A, 0x8000), 0, MODULE_SPI,        0)
 /* EMMC SPI SLAVE: PB13/14/15 */
 ALTERNATE(PIN_MASK(B, 0xE000), 0, MODULE_SPI_FLASH,  0)
 /* SENSORS SPI MASTER: PB10, PB12, PC2, PC3 */
-ALTERNATE(PIN_MASK(B, 0x0400), 5, MODULE_SPI_MASTER, 0)
-ALTERNATE(PIN_MASK(C, 0x000C), 1, MODULE_SPI_MASTER, 0)
+ALTERNATE(PIN_MASK(B, 0x0400), 5, MODULE_SPI_CONTROLLER, 0)
+ALTERNATE(PIN_MASK(C, 0x000C), 1, MODULE_SPI_CONTROLLER, 0)
diff --git a/board/damu/led.c b/board/damu/led.c
index a6f27f2200..7fcda9afda 100644
--- a/board/damu/led.c
+++ b/board/damu/led.c
@@ -1,50 +1,60 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Power and battery LED control for Damu
  */
 #include "common.h"
-#include "ioexpander.h"
 #include "driver/ioexpander/it8801.h"
 #include "ec_commands.h"
+#include "ioexpander.h"
 #include "led_common.h"
 #include "led_onoff_states.h"
 
 #define LED_ON_LVL 0
 #define LED_OFF_LVL 1
 
-const int led_charge_lvl_1 = 5;
-const int led_charge_lvl_2 = 95;
+__override const int led_charge_lvl_1 = 5;
+__override const int led_charge_lvl_2 = 95;
 
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
-const struct led_descriptor led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    1 * LED_ONE_SEC },
+						  { LED_OFF,
+						    3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-	EC_LED_ID_BATTERY_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED,
+					     EC_LED_ID_BATTERY_LED };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-void led_set_color_battery(enum ec_led_colors color)
+__override void led_set_color_battery(enum ec_led_colors color)
 {
 	switch (color) {
 	case EC_LED_COLOR_WHITE:
@@ -62,7 +72,7 @@ void led_set_color_battery(enum ec_led_colors color)
 	}
 }
 
-void led_set_color_power(enum ec_led_colors color)
+__override void led_set_color_power(enum ec_led_colors color)
 {
 	switch (color) {
 	case EC_LED_COLOR_WHITE:
@@ -76,24 +86,24 @@ void led_set_color_power(enum ec_led_colors color)
 
 void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
 {
-	if(led_id == EC_LED_ID_BATTERY_LED) {
+	if (led_id == EC_LED_ID_BATTERY_LED) {
 		brightness_range[EC_LED_COLOR_AMBER] = 1;
 		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	} else if(led_id == EC_LED_ID_POWER_LED) {
+	} else if (led_id == EC_LED_ID_POWER_LED) {
 		brightness_range[EC_LED_COLOR_WHITE] = 1;
 	}
 }
 
 int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 {
-	if(led_id == EC_LED_ID_BATTERY_LED) {
-		if(brightness[EC_LED_COLOR_AMBER] != 0)
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		if (brightness[EC_LED_COLOR_AMBER] != 0)
 			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if(brightness[EC_LED_COLOR_WHITE] != 0)
+		else if (brightness[EC_LED_COLOR_WHITE] != 0)
 			led_set_color_battery(EC_LED_COLOR_WHITE);
 		else
 			led_set_color_battery(LED_OFF);
-	} else if(led_id == EC_LED_ID_POWER_LED) {
+	} else if (led_id == EC_LED_ID_POWER_LED) {
 		if (brightness[EC_LED_COLOR_WHITE] != 0)
 			led_set_color_power(EC_LED_COLOR_WHITE);
 		else
diff --git a/board/damu/vif_override.xml b/board/damu/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/damu/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/delbin/battery.c b/board/delbin/battery.c
index e907a3574f..6d6ae2afad 100644
--- a/board/delbin/battery.c
+++ b/board/delbin/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/delbin/board.c b/board/delbin/board.c
index b7a26b683b..0e416e6e2e 100644
--- a/board/delbin/board.c
+++ b/board/delbin/board.c
@@ -1,19 +1,19 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Volteer board-specific configuration */
-#include "bb_retimer.h"
-#include "button.h"
-#include "common.h"
 #include "accelgyro.h"
+#include "button.h"
 #include "cbi_ec_fw_config.h"
+#include "cbi_ssfc.h"
+#include "common.h"
 #include "driver/accel_bma2x2.h"
 #include "driver/accelgyro_bmi260.h"
 #include "driver/bc12/pi3usb9201.h"
 #include "driver/ppc/syv682x.h"
-#include "driver/retimer/bb_retimer.h"
+#include "driver/retimer/ps8811.h"
 #include "driver/tcpm/ps8xxx.h"
 #include "driver/tcpm/tcpci.h"
 #include "driver/tcpm/tusb422.h"
@@ -22,6 +22,7 @@
 #include "fan_chip.h"
 #include "gpio.h"
 #include "hooks.h"
+#include "keyboard_customization.h"
 #include "keyboard_scan.h"
 #include "lid_switch.h"
 #include "power.h"
@@ -30,23 +31,23 @@
 #include "pwm_chip.h"
 #include "switch.h"
 #include "system.h"
-#include "task.h"
 #include "tablet_mode.h"
+#include "task.h"
 #include "throttle_ap.h"
 #include "uart.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
-#include "usb_pd_tbt.h"
 #include "usb_pd_tcpm.h"
 #include "usbc_ppc.h"
 #include "util.h"
 
-#include "gpio_list.h" /* Must come after other header files. */
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 /* Keyboard scan setting */
-struct keyboard_scan_config keyscan_config = {
+__override struct keyboard_scan_config keyscan_config = {
 	/* Increase from 50 us, because KSO_02 passes through the H1. */
 	.output_settle_us = 80,
 	/* Other values should be the same as the default configuration. */
@@ -62,6 +63,28 @@ struct keyboard_scan_config keyscan_config = {
 	},
 };
 
+__override struct key {
+	uint8_t row;
+	uint8_t col;
+} vivaldi_keys[] = {
+	{ .row = 0, .col = 2 }, /* T1 */
+	{ .row = 3, .col = 2 }, /* T2 */
+	{ .row = 2, .col = 2 }, /* T3 */
+	{ .row = 1, .col = 2 }, /* T4 */
+	{ .row = 3, .col = 4 }, /* T5 */
+	{ .row = 2, .col = 4 }, /* T6 */
+	{ .row = 1, .col = 4 }, /* T7 */
+	{ .row = 2, .col = 9 }, /* T8 */
+	{ .row = 1, .col = 9 }, /* T9 */
+	{ .row = 0, .col = 4 }, /* T10 */
+	{ .row = 0, .col = 1 }, /* T11 */
+	{ .row = 1, .col = 5 }, /* T12 */
+	{ .row = 3, .col = 5 }, /* T13 */
+	{ .row = 0, .col = 9 }, /* T14 */
+	{ .row = 0, .col = 11 }, /* T15 */
+};
+BUILD_ASSERT(ARRAY_SIZE(vivaldi_keys) == MAX_TOP_ROW_KEYS);
+
 /******************************************************************************/
 /*
  * FW_CONFIG defaults for Delbin if the CBI data is not initialized.
@@ -72,56 +95,35 @@ union volteer_cbi_fw_config fw_config_defaults = {
 
 static void board_init(void)
 {
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-__override enum tbt_compat_cable_speed board_get_max_tbt_speed(int port)
-{
-	enum ec_cfg_usb_db_type usb_db = ec_cfg_usb_db_type();
-
-	if (port == USBC_PORT_C1) {
-		if (usb_db == DB_USB4_GEN2) {
-			/*
-			 * Older boards violate 205mm trace length prior
-			 * to connection to the re-timer and only support up
-			 * to GEN2 speeds.
-			 */
-			return TBT_SS_U32_GEN1_GEN2;
-		} else if (usb_db == DB_USB4_GEN3) {
-			return TBT_SS_TBT_GEN3;
-		}
+	key_choose();
+
+	if (get_cbi_ssfc_keyboard() == SSFC_KEYBOARD_GAMING) {
+		keyscan_config.actual_key_mask[1] = 0xfa;
+		keyscan_config.actual_key_mask[4] = 0xfe;
+		keyscan_config.actual_key_mask[7] = 0x86;
+		keyscan_config.actual_key_mask[9] = 0xff;
+		keyscan_config.actual_key_mask[11] = 0xff;
+
+		vivaldi_keys[0].row = 4;
+		vivaldi_keys[0].col = 2;
+		vivaldi_keys[4].row = 4;
+		vivaldi_keys[4].col = 4;
+		vivaldi_keys[5].row = 3;
+		vivaldi_keys[5].col = 4;
+		vivaldi_keys[6].row = 2;
+		vivaldi_keys[6].col = 4;
+		vivaldi_keys[9].row = 1;
+		vivaldi_keys[9].col = 4;
 	}
-
-	/*
-	 * Thunderbolt-compatible mode not supported
-	 *
-	 * TODO (b/147726366): All the USB-C ports need to support same speed.
-	 * Need to fix once USB-C feature set is known for Volteer.
-	 */
-	return TBT_SS_RES_0;
-}
-
-__override bool board_is_tbt_usb4_port(int port)
-{
-	enum ec_cfg_usb_db_type usb_db = ec_cfg_usb_db_type();
-
-	/*
-	 * Volteer reference design only supports TBT & USB4 on port 1
-	 * if the USB4 DB is present.
-	 *
-	 * TODO (b/147732807): All the USB-C ports need to support same
-	 * features. Need to fix once USB-C feature set is known for Volteer.
-	 */
-	return ((port == USBC_PORT_C1)
-		&& ((usb_db == DB_USB4_GEN2) || (usb_db == DB_USB4_GEN3)));
 }
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_PRE_DEFAULT);
 
 /******************************************************************************/
 /* Physical fans. These are logically separate from pwm_channels. */
 
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
@@ -154,17 +156,22 @@ const struct fan_t fans[FAN_CH_COUNT] = {
  * 130 C.  However, sensor is located next to DDR, so we need to use the lower
  * DDR temperature limit (85 C)
  */
-const static struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(35),
-	.temp_fan_max = C_TO_K(50),
-};
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+		}, \
+		.temp_fan_off = C_TO_K(35), \
+		.temp_fan_max = C_TO_K(65), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 
 /*
  * Inductor limits - used for both charger and PP3300 regulator
@@ -177,24 +184,29 @@ const static struct ec_thermal_config thermal_cpu = {
  * Inductors: limit of 125c
  * PCB: limit is 80c
  */
-const static struct ec_thermal_config thermal_inductor = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(55),
-};
-
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_INDUCTOR         \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+		}, \
+		.temp_fan_off = C_TO_K(40), \
+		.temp_fan_max = C_TO_K(65), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_inductor =
+	THERMAL_INDUCTOR;
 
 struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_CHARGER]			= thermal_inductor,
-	[TEMP_SENSOR_2_PP3300_REGULATOR]	= thermal_inductor,
-	[TEMP_SENSOR_3_DDR_SOC]			= thermal_cpu,
-	[TEMP_SENSOR_4_FAN]			= thermal_cpu,
+	[TEMP_SENSOR_1_CHARGER] = THERMAL_INDUCTOR,
+	[TEMP_SENSOR_2_PP3300_REGULATOR] = THERMAL_INDUCTOR,
+	[TEMP_SENSOR_3_DDR_SOC] = THERMAL_CPU,
+	[TEMP_SENSOR_4_FAN] = THERMAL_CPU,
 };
 BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
 
@@ -279,61 +291,6 @@ const struct pwm_t pwm_channels[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
-static const struct tcpc_config_t tcpc_config_p0_usb3 = {
-	.bus_type = EC_BUS_TYPE_I2C,
-	.i2c_info = {
-		.port = I2C_PORT_USB_C0,
-		.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-	},
-	.flags = TCPC_FLAGS_TCPCI_REV2_0 | TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V,
-	.drv = &ps8xxx_tcpm_drv,
-	.usb23 = USBC_PORT_0_USB2_NUM | (USBC_PORT_0_USB3_NUM << 4),
-};
-
-static const struct tcpc_config_t tcpc_config_p1_usb3 = {
-	.bus_type = EC_BUS_TYPE_I2C,
-	.i2c_info = {
-		.port = I2C_PORT_USB_C1,
-		.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-	},
-	.flags = TCPC_FLAGS_TCPCI_REV2_0 | TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V,
-	.drv = &ps8xxx_tcpm_drv,
-	.usb23 = USBC_PORT_1_USB2_NUM | (USBC_PORT_1_USB3_NUM << 4),
-};
-
-static const struct usb_mux usbc0_usb3_mb_retimer = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	.next_mux = NULL,
-};
-
-static const struct usb_mux mux_config_p0_usb3 = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-	.next_mux = &usbc0_usb3_mb_retimer,
-};
-
-static const struct usb_mux usbc1_usb3_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	.next_mux = NULL,
-};
-
-static const struct usb_mux mux_config_p1_usb3 = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-	.next_mux = &usbc1_usb3_db_retimer,
-};
-
-static const struct bb_usb_control bb_p0_control = {
-	.usb_ls_en_gpio = GPIO_USB_C0_LS_EN,
-	.retimer_rst_gpio = GPIO_USB_C0_RT_RST_ODL,
-};
-
 /******************************************************************************/
 /* USB-A charging control */
 
@@ -358,44 +315,33 @@ static void ps8815_reset(int port)
 	}
 
 	gpio_set_level(ps8xxx_rst_odl, 0);
-	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS,
-			   PS8815_PWR_H_RST_H_DELAY_MS));
+	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS));
 	gpio_set_level(ps8xxx_rst_odl, 1);
 	msleep(PS8815_FW_INIT_DELAY_MS);
 
 	CPRINTS("[C%d] %s: patching ps8815 registers", port, __func__);
 
-	if (i2c_read8(i2c_port,
-		      PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
+	if (i2c_read8(i2c_port, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) ==
+	    EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f was %02x", val);
 
-	if (i2c_write8(i2c_port,
-		      PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) == EC_SUCCESS)
+	if (i2c_write8(i2c_port, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) ==
+	    EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f set to 0x31");
 
-	if (i2c_read8(i2c_port,
-		      PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
+	if (i2c_read8(i2c_port, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) ==
+	    EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f now %02x", val);
 }
 
 void board_reset_pd_mcu(void)
 {
 	ps8815_reset(USBC_PORT_C0);
-	usb_mux_hpd_update(USBC_PORT_C0, 0, 0);
+	usb_mux_hpd_update(USBC_PORT_C0, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 	ps8815_reset(USBC_PORT_C1);
-	usb_mux_hpd_update(USBC_PORT_C1, 0, 0);
-}
-
-__override void board_cbi_init(void)
-{
-	/* Config MB USB3 */
-	tcpc_config[USBC_PORT_C0] = tcpc_config_p0_usb3;
-	usb_muxes[USBC_PORT_C0] = mux_config_p0_usb3;
-	bb_controls[USBC_PORT_C0] = bb_p0_control;
-
-	/* Config DB USB3 */
-	tcpc_config[USBC_PORT_C1] = tcpc_config_p1_usb3;
-	usb_muxes[USBC_PORT_C1] = mux_config_p1_usb3;
+	usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
 
 /******************************************************************************/
@@ -425,6 +371,7 @@ void ppc_interrupt(enum gpio_signal signal)
 		break;
 	case GPIO_USB_C1_PPC_INT_ODL:
 		syv682x_interrupt(USBC_PORT_C1);
+		break;
 	default:
 		break;
 	}
@@ -447,12 +394,40 @@ static const struct ec_response_keybd_config delbin_kb = {
 	.capabilities = KEYBD_CAP_SCRNLOCK_KEY | KEYBD_CAP_NUMERIC_KEYPAD,
 };
 
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	return &delbin_kb;
 }
 
+static void ps8811_init(void)
+{
+	int rv;
+
+	/* Set Channel A output swing to Level1 */
+	rv = i2c_write8(I2C_PORT_USB_1_MIX,
+			PS8811_I2C_ADDR_FLAGS0 + PS8811_REG_PAGE1, 0x66, 0x10);
+	/* Set 50 ohm termination adjuct for B channel: -9%*/
+	rv |= i2c_write8(I2C_PORT_USB_1_MIX,
+			 PS8811_I2C_ADDR_FLAGS0 + PS8811_REG_PAGE1, 0x73, 0x04);
+	/* Set Channel B output swing to Level3 */
+	rv |= i2c_write8(I2C_PORT_USB_1_MIX,
+			 PS8811_I2C_ADDR_FLAGS0 + PS8811_REG_PAGE1, 0xA4, 0x03);
+	/* Set PS level for B channel */
+	rv |= i2c_write8(I2C_PORT_USB_1_MIX,
+			 PS8811_I2C_ADDR_FLAGS0 + PS8811_REG_PAGE1, 0xA5, 0x84);
+	/* Set DE level for B channel */
+	rv |= i2c_write8(I2C_PORT_USB_1_MIX,
+			 PS8811_I2C_ADDR_FLAGS0 + PS8811_REG_PAGE1, 0xA6, 0x16);
+}
+
+/* Called on AP S5 -> S0ix transition */
+static void board_chipset_startup(void)
+{
+	ps8811_init();
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
+
 /* Called on AP S0ix -> S0 transition */
 static void board_chipset_resume(void)
 {
@@ -483,24 +458,26 @@ BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
 
 /******************************************************************************/
 /* USBC TCPC configuration */
-struct tcpc_config_t tcpc_config[] = {
+const struct tcpc_config_t tcpc_config[] = {
 	[USBC_PORT_C0] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = I2C_PORT_USB_C0,
-			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
 		},
-		.drv = &tusb422_tcpm_drv,
-		.usb23 = USBC_PORT_0_USB2_NUM | (USBC_PORT_0_USB3_NUM << 4),
+		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V,
+		.drv = &ps8xxx_tcpm_drv,
 	},
 	[USBC_PORT_C1] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = I2C_PORT_USB_C1,
-			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
 		},
-		.drv = &tusb422_tcpm_drv,
-		.usb23 = USBC_PORT_1_USB2_NUM | (USBC_PORT_1_USB3_NUM << 4),
+		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V,
+		.drv = &ps8xxx_tcpm_drv,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
@@ -508,37 +485,45 @@ BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
 
 /******************************************************************************/
 /* USBC mux configuration - Tiger Lake includes internal mux */
-struct usb_mux usbc1_usb4_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &bb_usb_retimer,
-	.i2c_port = I2C_PORT_USB_1_MIX,
-	.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
+static const struct usb_mux_chain usbc0_usb3_mb_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
+	.next = NULL,
 };
-struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc1_usb4_db_retimer,
-	},
+
+static const struct usb_mux_chain usbc1_usb3_db_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
+	.next = NULL,
 };
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
 
-struct bb_usb_control bb_controls[] = {
+const struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		/* USB-C port 0 doesn't have a retimer */
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc0_usb3_mb_retimer,
 	},
 	[USBC_PORT_C1] = {
-		.usb_ls_en_gpio = GPIO_USB_C1_LS_EN,
-		.retimer_rst_gpio = GPIO_USB_C1_RT_RST_ODL,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc1_usb3_db_retimer,
 	},
 };
-BUILD_ASSERT(ARRAY_SIZE(bb_controls) == USBC_PORT_COUNT);
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
 
 static void board_tcpc_init(void)
 {
diff --git a/board/delbin/board.h b/board/delbin/board.h
index 7b94edf039..50759b74d2 100644
--- a/board/delbin/board.h
+++ b/board/delbin/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,11 +11,17 @@
 /* Baseboard features */
 #include "baseboard.h"
 
+/*
+ * The RAM and flash size combination on the NPCX797FC dose not leave
+ * any unused flash space that can be used to store the .init_rom section.
+ */
+#undef CONFIG_CHIP_INIT_ROM_REGION
+
 #undef NPCX_PWM1_SEL
-#define NPCX_PWM1_SEL 0	/* GPIO C2 is not used as PWM1. */
+#define NPCX_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */
 
 /* Optional features */
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
+#undef CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
 
 #define CONFIG_VBOOT_EFS2
 
@@ -28,72 +34,61 @@
 #define CONFIG_POWER_PP5000_CONTROL
 
 /* LED defines */
-#define CONFIG_LED_POWER_LED
 #define CONFIG_LED_ONOFF_STATES
 
 /* Keyboard features */
 #define CONFIG_KEYBOARD_VIVALDI
 #define CONFIG_KEYBOARD_REFRESH_ROW3
+#define CONFIG_KEYBOARD_CUSTOMIZATION
+#define CONFIG_KEYBOARD_MULTIPLE
 
 /* Sensors */
 /* BMA253 accelerometer in base */
 #define CONFIG_ACCEL_BMA255
+#define CONFIG_ACCEL_KX022
 
 /* BMI260 accel/gyro in base */
 #define CONFIG_ACCELGYRO_BMI260
 #define CONFIG_ACCELGYRO_BMI260_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+#define CONFIG_ACCELGYRO_ICM426XX
+#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 
 /* Sensors without hardware FIFO are in forced mode */
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
 
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE		BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID		LID_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
 
 /* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
-
-/*
- * USB-C port's USB2 & USB3 mapping from schematics
- * USB2 numbering on PCH - 1 to n
- * USB3 numbering on AP - 0 to n (PMC's USB3 numbering for MUX
- * configuration is - 1 to n hence add +1)
- */
-#define USBC_PORT_0_USB2_NUM	9
-#define USBC_PORT_0_USB3_NUM	1
-#define USBC_PORT_1_USB2_NUM	4
-#define USBC_PORT_1_USB3_NUM	2
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
 
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
 
 /*
  * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
- * cables only support up to 60W.
+ * cables only support up to 60W, the limitation of 45W is for the delbin
+ * board.
  */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 45000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
-/* Enabling Thunderbolt-compatible mode */
-#define CONFIG_USB_PD_TBT_COMPAT_MODE
-
-/* Enabling USB4 mode */
-#define CONFIG_USB_PD_USB4
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x40
+#undef CONFIG_USB_PD_TCPC_RUNTIME_CONFIG
+#undef CONFIG_USB_MUX_RUNTIME_CONFIG
 
 /* USB Type A Features */
-#define USB_PORT_COUNT			1
+#define USB_PORT_COUNT 1
 #define CONFIG_USB_PORT_POWER_DUMB
 
 /* USBC PPC*/
 #define CONFIG_USBC_PPC_SYV682X
 
-
 /* BC 1.2 */
 
 /* Volume Button feature */
@@ -101,8 +96,12 @@
 /* Fan features */
 
 /* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+
+/* Retimer */
+#undef CONFIG_USBC_RETIMER_INTEL_BB
+#undef CONFIG_USBC_RETIMER_INTEL_BB_RUNTIME_CONFIG
 
 /*
  * Macros for GPIO signals used in common code that don't match the
@@ -110,46 +109,43 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_UART2_EC_RX
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PG_EC_DSW_PWROK		GPIO_DSW_PWROK
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD		GPIO_PG_EC_RSMRST_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
-#define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE_L
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_LID_OPEN GPIO_EC_LID_OPEN
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_UART2_EC_RX
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PG_EC_DSW_PWROK GPIO_DSW_PWROK
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
 
 /* I2C Bus Configuration */
 #define CONFIG_I2C
-#define I2C_PORT_ACCEL		I2C_PORT_SENSOR
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_1_MIX	NPCX_I2C_PORT3_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT3_0
+#define I2C_PORT_POWER NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
 
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-#define CONFIG_I2C_MASTER
+#define I2C_PORT_BATTERY I2C_PORT_POWER
+#define I2C_PORT_CHARGER I2C_PORT_EEPROM
 
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+#define CONFIG_I2C_CONTROLLER
 
 #ifndef __ASSEMBLER__
 
@@ -161,11 +157,7 @@ enum battery_type {
 	BATTERY_TYPE_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_FAN = 0,
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_FAN = 0, PWM_CH_KBLIGHT, PWM_CH_COUNT };
 
 enum sensor_id {
 	LID_ACCEL = 0,
@@ -174,13 +166,10 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 void board_reset_pd_mcu(void);
+void motion_interrupt(enum gpio_signal signal);
 
 #endif /* !__ASSEMBLER__ */
 
diff --git a/board/delbin/build.mk b/board/delbin/build.mk
index b78172d3cf..26007095af 100644
--- a/board/delbin/build.mk
+++ b/board/delbin/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -8,10 +8,12 @@
 
 CHIP:=npcx
 CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
+
+CHIP_VARIANT:=npcx7m7fc
 BASEBOARD:=volteer
 
 board-y=board.o
 board-y+=battery.o
 board-y+=led.o
 board-y+=sensors.o
+board-$(CONFIG_KEYBOARD_CUSTOMIZATION)+=keyboard_customization.o
diff --git a/board/delbin/ec.tasklist b/board/delbin/ec.tasklist
index 292de51cdb..c29125d517 100644
--- a/board/delbin/ec.tasklist
+++ b/board/delbin/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,6 +16,7 @@
 	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
 	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
 	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
 	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
 	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
 	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
diff --git a/board/delbin/gpio.inc b/board/delbin/gpio.inc
index 3ac9d81092..f229e50dcc 100644
--- a/board/delbin/gpio.inc
+++ b/board/delbin/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,7 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
@@ -25,7 +25,7 @@ GPIO_INT(DSW_PWROK,            PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
 GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4),  GPIO_INT_BOTH, power_signal_interrupt)
 
 /* Sensor Interrupts */
-GPIO_INT(EC_IMU_INT_L,         PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, bmi260_interrupt)
+GPIO_INT(EC_IMU_INT_L,         PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, motion_interrupt)
 GPIO_INT(TABLET_MODE_L,        PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
 /*
  * Lid g-sensor interrupt unused on Delbin, configure as regular input for
@@ -173,3 +173,6 @@ ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)  /* GPIO00 =
                                                                        GPIO01 = H1_EC_PWR_BTN_ODL
                                                                        GPIO02 = EC_RST_ODL */
 
+/* Temperature sensors */
+ALTERNATE(PIN_MASK(4, BIT(2) | BIT(4) | BIT(5)), 0, MODULE_ADC, 0) /* TEMP_SENSOR1,2,4 */
+ALTERNATE(PIN_MASK(F, BIT(1)), 0, MODULE_ADC, 0) /* TEMP_SENSOR3 */
diff --git a/board/delbin/keyboard_customization.c b/board/delbin/keyboard_customization.c
new file mode 100644
index 0000000000..3ee81cb093
--- /dev/null
+++ b/board/delbin/keyboard_customization.c
@@ -0,0 +1,169 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi_ssfc.h"
+#include "common.h"
+#include "gpio.h"
+#include "keyboard_8042_sharedlib.h"
+#include "keyboard_config.h"
+#include "keyboard_customization.h"
+#include "keyboard_protocol.h"
+#include "keyboard_raw.h"
+#include "keyboard_scan.h"
+
+static uint16_t (*scancode_set2)[KEYBOARD_ROWS];
+
+static uint16_t KB2scancode_set2[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = {
+	{ 0x0000, 0x0000, 0x0014, 0xe01f, 0xe014, 0x0000, 0x0000, 0x0000 },
+	{ 0x0000, 0x0076, 0x0000, 0x000e, 0x001c, 0x003a, 0x000d, 0x0016 },
+	{ 0x006c, 0x000c, 0x0004, 0x0006, 0x0005, 0xe071, 0x0026, 0x002a },
+	{ 0x0032, 0x0034, 0x002c, 0x002e, 0x002b, 0x0029, 0x0025, 0x002d },
+	{ 0xe01f, 0x0009, 0x0083, 0x000b, 0x0003, 0x0041, 0x001e, 0x001d },
+	{ 0x0051, 0x0000, 0x005b, 0x0000, 0x0042, 0x0022, 0x003e, 0x0043 },
+	{ 0x0031, 0x0033, 0x0035, 0x0036, 0x003b, 0x001b, 0x003d, 0x003c },
+	{ 0x0000, 0x0012, 0x0061, 0x0000, 0x0000, 0x0000, 0x0000, 0x0059 },
+	{ 0x0055, 0x0052, 0x0054, 0x004e, 0x004c, 0x0024, 0x0044, 0x004d },
+	{ 0x0045, 0x0001, 0x000a, 0x002f, 0x004b, 0x0049, 0x0046, 0x001a },
+	{ 0xe011, 0x0000, 0x006a, 0x0000, 0x005d, 0x0000, 0x0011, 0x0000 },
+	{ 0xe07a, 0x005d, 0xe075, 0x006b, 0x005a, 0xe072, 0x004a, 0x0066 },
+	{ 0xe06b, 0xe074, 0xe069, 0x0067, 0xe06c, 0x0064, 0x0015, 0xe07d },
+	{ 0x0073, 0x007c, 0x007b, 0x0074, 0x0071, 0xe04a, 0x0070, 0x0021 },
+	{ 0x0023, 0xe05a, 0x0075, 0x0079, 0x007a, 0x0072, 0x007D, 0x0069 },
+};
+
+/* The standard Chrome OS keyboard matrix table in scan code set 2. */
+static uint16_t KB1scancode_set2[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = {
+	{ 0x0000, 0x0000, 0x0014, 0xe01f, 0xe014, 0xe007, 0x0000, 0x0000 },
+	{ 0xe01f, 0x0076, 0x000d, 0x000e, 0x001c, 0x001a, 0x0016, 0x0015 },
+	{ 0x0005, 0x000c, 0x0004, 0x0006, 0x0023, 0x0021, 0x0026, 0x0024 },
+	{ 0x0032, 0x0034, 0x002c, 0x002e, 0x002b, 0x002a, 0x0025, 0x002d },
+	{ 0x0009, 0x0083, 0x000b, 0x0003, 0x001b, 0x0022, 0x001e, 0x001d },
+	{ 0x0051, 0x0000, 0x005b, 0x0000, 0x0042, 0x0041, 0x003e, 0x0043 },
+	{ 0x0031, 0x0033, 0x0035, 0x0036, 0x003b, 0x003a, 0x003d, 0x003c },
+	{ 0x0000, 0x0000, 0x0061, 0x0000, 0x0000, 0x0012, 0x0000, 0x0059 },
+	{ 0x0055, 0x0052, 0x0054, 0x004e, 0x004c, 0x004a, 0x0045, 0x004d },
+	{ 0x0000, 0x0001, 0x000a, 0x002f, 0x004b, 0x0049, 0x0046, 0x0044 },
+	{ 0xe011, 0x0000, 0x006a, 0x0000, 0x005d, 0x0000, 0x0011, 0x0000 },
+#ifndef CONFIG_KEYBOARD_KEYPAD
+	{ 0x0000, 0x0066, 0x0000, 0x005d, 0x005a, 0x0029, 0xe072, 0xe075 },
+	{ 0x0000, 0x0064, 0x0000, 0x0067, 0x0000, 0x0000, 0xe074, 0xe06b },
+#else
+	{ 0x0000, 0x0066, 0xe071, 0x005d, 0x005a, 0x0029, 0xe072, 0xe075 },
+	{ 0xe06c, 0x0064, 0xe07d, 0x0067, 0xe069, 0xe07a, 0xe074, 0xe06b },
+	{ 0xe04a, 0x007c, 0x007b, 0x0074, 0x0071, 0x0073, 0x006b, 0x0070 },
+	{ 0x006c, 0x0075, 0x007d, 0x0079, 0x007a, 0x0072, 0x0069, 0xe05a },
+#endif
+};
+
+uint16_t get_scancode_set2(uint8_t row, uint8_t col)
+{
+	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS) {
+		return *(*(scancode_set2 + col) + row);
+	}
+	return 0;
+}
+
+void set_scancode_set2(uint8_t row, uint8_t col, uint16_t val)
+{
+	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS) {
+		*(*(scancode_set2 + col) + row) = val;
+	}
+}
+
+void board_keyboard_drive_col(int col)
+{
+	/* Drive all lines to high */
+	if (col == KEYBOARD_COLUMN_NONE)
+		gpio_set_level(GPIO_KBD_KSO2, 0);
+
+	/* Set KBSOUT to zero to detect key-press */
+	else if (col == KEYBOARD_COLUMN_ALL)
+		gpio_set_level(GPIO_KBD_KSO2, 1);
+
+	/* Drive one line for detection */
+	else {
+		if (col == 2)
+			gpio_set_level(GPIO_KBD_KSO2, 1);
+		else
+			gpio_set_level(GPIO_KBD_KSO2, 0);
+	}
+}
+
+struct keyboard_type key_typ = {
+	.col_esc = KEYBOARD_COL_ESC,
+	.row_esc = KEYBOARD_ROW_ESC,
+	.col_down = KEYBOARD_COL_DOWN,
+	.row_down = KEYBOARD_ROW_DOWN,
+	.col_left_shift = KEYBOARD_COL_LEFT_SHIFT,
+	.row_left_shift = KEYBOARD_ROW_LEFT_SHIFT,
+	.col_refresh = KEYBOARD_COL_REFRESH,
+	.row_refresh = KEYBOARD_ROW_REFRESH,
+	.col_right_alt = KEYBOARD_COL_RIGHT_ALT,
+	.row_right_alt = KEYBOARD_ROW_RIGHT_ALT,
+	.col_left_alt = KEYBOARD_COL_LEFT_ALT,
+	.row_left_alt = KEYBOARD_ROW_LEFT_ALT,
+	.col_key_r = KEYBOARD_COL_KEY_R,
+	.row_key_r = KEYBOARD_ROW_KEY_R,
+	.col_key_h = KEYBOARD_COL_KEY_H,
+	.row_key_h = KEYBOARD_ROW_KEY_H,
+};
+
+int keyboard_choose(void)
+{
+	if (get_cbi_ssfc_keyboard() == SSFC_KEYBOARD_GAMING)
+		return 1;
+
+	return 0;
+}
+
+void key_choose(void)
+{
+	if (keyboard_choose() == 1) {
+		key_typ.col_esc = KEYBOARD2_COL_ESC;
+		key_typ.row_esc = KEYBOARD2_ROW_ESC;
+		key_typ.col_down = KEYBOARD2_COL_DOWN;
+		key_typ.row_down = KEYBOARD2_ROW_DOWN;
+		key_typ.col_left_shift = KEYBOARD2_COL_LEFT_SHIFT;
+		key_typ.row_left_shift = KEYBOARD2_ROW_LEFT_SHIFT;
+		key_typ.col_refresh = KEYBOARD2_COL_REFRESH;
+		key_typ.row_refresh = KEYBOARD2_ROW_REFRESH;
+		key_typ.col_right_alt = KEYBOARD2_COL_RIGHT_ALT;
+		key_typ.row_right_alt = KEYBOARD2_ROW_RIGHT_ALT;
+		key_typ.col_left_alt = KEYBOARD2_COL_LEFT_ALT;
+		key_typ.row_left_alt = KEYBOARD2_ROW_LEFT_ALT;
+		key_typ.col_key_r = KEYBOARD2_COL_KEY_R;
+		key_typ.row_key_r = KEYBOARD2_ROW_KEY_R;
+		key_typ.col_key_h = KEYBOARD2_COL_KEY_H;
+		key_typ.row_key_h = KEYBOARD2_ROW_KEY_H;
+
+		boot_key_list[0].col = KEYBOARD2_COL_ESC;
+		boot_key_list[0].row = KEYBOARD2_ROW_ESC;
+		boot_key_list[1].col = KEYBOARD2_COL_DOWN;
+		boot_key_list[1].row = KEYBOARD2_ROW_DOWN;
+		boot_key_list[2].col = KEYBOARD2_COL_LEFT_SHIFT;
+		boot_key_list[2].row = KEYBOARD2_ROW_LEFT_SHIFT;
+
+		scancode_set2 = KB2scancode_set2;
+	} else {
+		key_typ.col_esc = KEYBOARD_COL_ESC;
+		key_typ.row_esc = KEYBOARD_ROW_ESC;
+		key_typ.col_down = KEYBOARD_COL_DOWN;
+		key_typ.row_down = KEYBOARD_ROW_DOWN;
+		key_typ.col_left_shift = KEYBOARD_COL_LEFT_SHIFT;
+		key_typ.row_left_shift = KEYBOARD_ROW_LEFT_SHIFT;
+		key_typ.col_refresh = KEYBOARD_COL_REFRESH;
+		key_typ.row_refresh = KEYBOARD_ROW_REFRESH;
+		key_typ.col_right_alt = KEYBOARD_COL_RIGHT_ALT;
+		key_typ.row_right_alt = KEYBOARD_ROW_RIGHT_ALT;
+		key_typ.col_left_alt = KEYBOARD_COL_LEFT_ALT;
+		key_typ.row_left_alt = KEYBOARD_ROW_LEFT_ALT;
+		key_typ.col_key_r = KEYBOARD_COL_KEY_R;
+		key_typ.row_key_r = KEYBOARD_ROW_KEY_R;
+		key_typ.col_key_h = KEYBOARD_COL_KEY_H;
+		key_typ.row_key_h = KEYBOARD_ROW_KEY_H;
+
+		scancode_set2 = KB1scancode_set2;
+	}
+}
diff --git a/board/delbin/keyboard_customization.h b/board/delbin/keyboard_customization.h
new file mode 100644
index 0000000000..bfe5c3b584
--- /dev/null
+++ b/board/delbin/keyboard_customization.h
@@ -0,0 +1,130 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Keyboard configuration */
+
+#ifndef __KEYBOARD_CUSTOMIZATION_H
+#define __KEYBOARD_CUSTOMIZATION_H
+
+/*
+ * KEYBOARD_COLS_MAX has the build time column size. It's used to allocate
+ * exact spaces for arrays. Actual keyboard scanning is done using
+ * keyboard_cols, which holds a runtime column size.
+ */
+#define KEYBOARD_COLS_MAX 16
+#define KEYBOARD_ROWS 8
+
+/*
+ * WARNING: Do not directly modify it. You should call keyboard_raw_set_cols,
+ * instead. It checks whether you're eligible or not.
+ */
+extern uint8_t keyboard_cols;
+
+#define KEYBOARD_ROW_TO_MASK(r) (1 << (r))
+
+#define KEYBOARD_COL_DOWN 11
+#define KEYBOARD_ROW_DOWN 6
+#define KEYBOARD_MASK_DOWN KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_DOWN)
+#define KEYBOARD_COL_ESC 1
+#define KEYBOARD_ROW_ESC 1
+#define KEYBOARD_MASK_ESC KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_ESC)
+#define KEYBOARD_COL_KEY_H 6
+#define KEYBOARD_ROW_KEY_H 1
+#define KEYBOARD_MASK_KEY_H KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_H)
+#define KEYBOARD_COL_KEY_R 3
+#define KEYBOARD_ROW_KEY_R 7
+#define KEYBOARD_MASK_KEY_R KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_R)
+#define KEYBOARD_COL_LEFT_ALT 10
+#define KEYBOARD_ROW_LEFT_ALT 6
+#define KEYBOARD_MASK_LEFT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_ALT)
+#define KEYBOARD_COL_REFRESH 2
+#ifdef CONFIG_KEYBOARD_REFRESH_ROW3
+#define KEYBOARD_ROW_REFRESH 3
+#else
+#define KEYBOARD_ROW_REFRESH 2
+#endif
+#define KEYBOARD_MASK_REFRESH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_REFRESH)
+#define KEYBOARD_COL_RIGHT_ALT 10
+#define KEYBOARD_ROW_RIGHT_ALT 0
+#define KEYBOARD_MASK_RIGHT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_ALT)
+#define KEYBOARD_DEFAULT_COL_VOL_UP 4
+#define KEYBOARD_DEFAULT_ROW_VOL_UP 0
+#define KEYBOARD_COL_LEFT_CTRL 0
+#define KEYBOARD_ROW_LEFT_CTRL 2
+#define KEYBOARD_MASK_LEFT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_CTRL)
+#define KEYBOARD_COL_RIGHT_CTRL 0
+#define KEYBOARD_ROW_RIGHT_CTRL 4
+#define KEYBOARD_MASK_RIGHT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_CTRL)
+#define KEYBOARD_COL_SEARCH 1
+#define KEYBOARD_ROW_SEARCH 0
+#define KEYBOARD_MASK_SEARCH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_SEARCH)
+#define KEYBOARD_COL_KEY_0 8
+#define KEYBOARD_ROW_KEY_0 6
+#define KEYBOARD_MASK_KEY_0 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_0)
+#define KEYBOARD_COL_KEY_1 1
+#define KEYBOARD_ROW_KEY_1 6
+#define KEYBOARD_MASK_KEY_1 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_1)
+#define KEYBOARD_COL_KEY_2 4
+#define KEYBOARD_ROW_KEY_2 6
+#define KEYBOARD_MASK_KEY_2 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_2)
+#define KEYBOARD_COL_LEFT_SHIFT 7
+#define KEYBOARD_ROW_LEFT_SHIFT 5
+#define KEYBOARD_MASK_LEFT_SHIFT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_SHIFT)
+#ifdef CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2
+#define KEYBOARD_MASK_PWRBTN KEYBOARD_ROW_TO_MASK(2)
+#elif defined(CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI3)
+#define KEYBOARD_MASK_PWRBTN KEYBOARD_ROW_TO_MASK(3)
+#endif
+
+/* Columns and masks for keys we particularly care about */
+#define KEYBOARD2_COL_DOWN 11
+#define KEYBOARD2_ROW_DOWN 5
+#define KEYBOARD2_MASK_DOWN KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_DOWN)
+#define KEYBOARD2_COL_ESC 1
+#define KEYBOARD2_ROW_ESC 1
+#define KEYBOARD2_MASK_ESC KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_ESC)
+#define KEYBOARD2_COL_KEY_H 6
+#define KEYBOARD2_ROW_KEY_H 1
+#define KEYBOARD2_MASK_KEY_H KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_KEY_H)
+#define KEYBOARD2_COL_KEY_R 3
+#define KEYBOARD2_ROW_KEY_R 7
+#define KEYBOARD2_MASK_KEY_R KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_KEY_R)
+#define KEYBOARD2_COL_LEFT_ALT 10
+#define KEYBOARD2_ROW_LEFT_ALT 6
+#define KEYBOARD2_MASK_LEFT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_LEFT_ALT)
+#define KEYBOARD2_COL_REFRESH 2
+#define KEYBOARD2_ROW_REFRESH 3
+#define KEYBOARD2_MASK_REFRESH KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_REFRESH)
+#define KEYBOARD2_COL_RIGHT_ALT 10
+#define KEYBOARD2_ROW_RIGHT_ALT 0
+#define KEYBOARD2_MASK_RIGHT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_RIGHT_ALT)
+#define KEYBOARD2_DEFAULT_COL_VOL_UP 4
+#define KEYBOARD2_DEFAULT_ROW_VOL_UP 1
+#define KEYBOARD2_COL_LEFT_CTRL 0
+#define KEYBOARD2_ROW_LEFT_CTRL 2
+#define KEYBOARD2_MASK_LEFT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_LEFT_CTRL)
+#define KEYBOARD2_COL_RIGHT_CTRL 0
+#define KEYBOARD2_ROW_RIGHT_CTRL 4
+#define KEYBOARD2_MASK_RIGHT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_RIGHT_CTRL)
+#define KEYBOARD2_COL_SEARCH 4
+#define KEYBOARD2_ROW_SEARCH 0
+#define KEYBOARD2_MASK_SEARCH KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_SEARCH)
+#define KEYBOARD2_COL_KEY_0 9
+#define KEYBOARD2_ROW_KEY_0 0
+#define KEYBOARD2_MASK_KEY_0 KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_KEY_0)
+#define KEYBOARD2_COL_KEY_1 1
+#define KEYBOARD2_ROW_KEY_1 7
+#define KEYBOARD2_MASK_KEY_1 KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_KEY_1)
+#define KEYBOARD2_COL_KEY_2 4
+#define KEYBOARD2_ROW_KEY_2 6
+#define KEYBOARD2_MASK_KEY_2 KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_KEY_2)
+#define KEYBOARD2_COL_LEFT_SHIFT 7
+#define KEYBOARD2_ROW_LEFT_SHIFT 1
+#define KEYBOARD2_MASK_LEFT_SHIFT KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_LEFT_SHIFT)
+
+int keyboard_choose(void);
+void key_choose(void);
+
+#endif /* __KEYBOARD_CUSTOMIZATION_H */
diff --git a/board/delbin/led.c b/board/delbin/led.c
index fb61d35574..299071818b 100644
--- a/board/delbin/led.c
+++ b/board/delbin/led.c
@@ -1,44 +1,53 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "chipset.h"
 #include "ec_commands.h"
 #include "gpio.h"
 #include "led_common.h"
 #include "led_onoff_states.h"
-#include "chipset.h"
 
 #define LED_ON_LVL 0
 #define LED_OFF_LVL 1
 
-const int led_charge_lvl_1 = 5;
-
-const int led_charge_lvl_2 = 95;
+__override const int led_charge_lvl_1 = 5;
 
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+__override const int led_charge_lvl_2 = 95;
 
-const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	     3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	     3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    1 * LED_ONE_SEC },
+						  { LED_OFF,
+						    3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
 const enum ec_led_id supported_led_ids[] = {
 	EC_LED_ID_BATTERY_LED,
@@ -47,7 +56,7 @@ const enum ec_led_id supported_led_ids[] = {
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-void led_set_color_battery(enum ec_led_colors color)
+__override void led_set_color_battery(enum ec_led_colors color)
 {
 	switch (color) {
 	case EC_LED_COLOR_AMBER:
@@ -65,7 +74,7 @@ void led_set_color_battery(enum ec_led_colors color)
 	}
 }
 
-void led_set_color_power(enum ec_led_colors color)
+__override void led_set_color_power(enum ec_led_colors color)
 {
 	if (color == EC_LED_COLOR_WHITE)
 		gpio_set_level(GPIO_LED_3_L, LED_ON_LVL);
@@ -102,4 +111,3 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 
 	return EC_SUCCESS;
 }
-
diff --git a/board/delbin/sensors.c b/board/delbin/sensors.c
index d5413769d5..e8d2034015 100644
--- a/board/delbin/sensors.c
+++ b/board/delbin/sensors.c
@@ -1,19 +1,25 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Volteer family-specific sensor configuration */
-#include "common.h"
 #include "accelgyro.h"
+#include "cbi_ec_fw_config.h"
+#include "cbi_ssfc.h"
+#include "common.h"
 #include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi_common.h"
+#include "driver/accel_kionix.h"
 #include "driver/accelgyro_bmi260.h"
-#include "keyboard_scan.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "driver/accelgyro_icm426xx.h"
+#include "driver/accelgyro_icm_common.h"
+#include "gpio.h"
 #include "hooks.h"
 #include "i2c.h"
-#include "task.h"
+#include "keyboard_scan.h"
 #include "tablet_mode.h"
+#include "task.h"
 #include "util.h"
 
 /******************************************************************************/
@@ -21,23 +27,97 @@
 static struct mutex g_lid_accel_mutex;
 static struct mutex g_base_mutex;
 
-/* BMA253 private data */
+/* sensor private data */
 static struct accelgyro_saved_data_t g_bma253_data;
-
-/* BMI260 private data */
+static struct kionix_accel_data g_kx022_data;
 static struct bmi_drv_data_t g_bmi260_data;
+static struct icm_drv_data_t g_icm426xx_data;
 
 /* Rotation matrix for the lid accelerometer */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
+
+const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+				       { 0, FLOAT_TO_FP(1), 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
+
+const mat33_fp_t base_standard_ref_icm = {
+	{ 0, FLOAT_TO_FP(-1), 0 },
+	{ FLOAT_TO_FP(1), 0, 0 },
+	{ 0, 0, FLOAT_TO_FP(1) },
 };
 
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
+struct motion_sensor_t icm426xx_base_accel = {
+	.name = "Base Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.rot_standard_ref = &base_standard_ref_icm,
+	.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
+	.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
+	.default_range = 4, /* g */
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+		/* Sensor on in S3 */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	},
+};
+
+struct motion_sensor_t icm426xx_base_gyro = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &base_standard_ref_icm,
+	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
+	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
+};
+
+struct motion_sensor_t kx022_lid_accel = {
+	.name = "Lid Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_KX022,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_LID,
+	.drv = &kionix_accel_drv,
+	.mutex = &g_lid_accel_mutex,
+	.drv_data = &g_kx022_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
+	.rot_standard_ref = &lid_standard_ref,
+	.min_frequency = KX022_ACCEL_MIN_FREQ,
+	.max_frequency = KX022_ACCEL_MAX_FREQ,
+	.default_range = 2, /* g, to support tablet mode */
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	},
 };
 
 struct motion_sensor_t motion_sensors[] = {
@@ -115,30 +195,30 @@ struct motion_sensor_t motion_sensors[] = {
 };
 unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
-static void baseboard_sensors_init(void)
+void motion_interrupt(enum gpio_signal signal)
 {
-	/* Note - BMA253 interrupt unused by EC */
-
-	/* Enable interrupt for the BMI260 accel/gyro sensor */
-	gpio_enable_interrupt(GPIO_EC_IMU_INT_L);
+	if (get_cbi_ssfc_base_sensor() == SSFC_SENSOR_BASE_ICM426XX)
+		icm426xx_interrupt(signal);
+	else
+		bmi260_interrupt(signal);
 }
-DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_DEFAULT);
 
-#ifndef TEST_BUILD
-void lid_angle_peripheral_enable(int enable)
+static void baseboard_sensors_init(void)
 {
-	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
+	if (get_cbi_ssfc_lid_sensor() == SSFC_SENSOR_LID_KX022) {
+		motion_sensors[LID_ACCEL] = kx022_lid_accel;
+		ccprints("LID_ACCEL is KX022");
+	} else
+		ccprints("LID_ACCEL is BMA253");
 
-	if (enable) {
-		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
-	} else {
-		/*
-		 * Ensure that the chipset is off before disabling the keyboard.
-		 * When the chipset is on, the EC keeps the keyboard enabled and
-		 * the AP decides whether to ignore input devices or not.
-		 */
-		if (!chipset_in_s0)
-			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
-	}
+	if (get_cbi_ssfc_base_sensor() == SSFC_SENSOR_BASE_ICM426XX) {
+		motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
+		motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
+		ccprints("BASE ACCEL is ICM426XX");
+	} else
+		ccprints("BASE ACCEL IS BMI260");
+
+	/* Enable interrupt for the accel/gyro sensor */
+	gpio_enable_interrupt(GPIO_EC_IMU_INT_L);
 }
-#endif
+DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_DEFAULT);
diff --git a/board/delbin/vif_override.xml b/board/delbin/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/delbin/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/dewatt/battery.c b/board/dewatt/battery.c
new file mode 100644
index 0000000000..9b3e15cfcf
--- /dev/null
+++ b/board/dewatt/battery.c
@@ -0,0 +1,63 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+
+/*
+ * Battery info for all Guybrush battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	/* AP19B8M */
+	[BATTERY_AP19B8M] = {
+		.fuel_gauge = {
+			.manuf_name = "LGC KT0030G024",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.reg_addr = 0x43,
+				.reg_mask = 0x0001,
+				.disconnect_val = 0x0,
+			}
+		},
+		.batt_info = {
+			.voltage_max          = 13350,
+			.voltage_normal       = 11610,
+			.voltage_min          = 9000,
+			.precharge_current    = 256,
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 50,
+			.charging_min_c       = 0,
+			.charging_max_c       = 60,
+			.discharging_min_c    = -20,
+			.discharging_max_c    = 75,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_AP19B8M;
diff --git a/board/dewatt/board.c b/board/dewatt/board.c
new file mode 100644
index 0000000000..14b646144f
--- /dev/null
+++ b/board/dewatt/board.c
@@ -0,0 +1,451 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Guybrush board-specific configuration */
+
+#include "adc.h"
+#include "base_fw_config.h"
+#include "battery.h"
+#include "board_fw_config.h"
+#include "builtin/assert.h"
+#include "button.h"
+#include "charger.h"
+#include "common.h"
+#include "cros_board_info.h"
+#include "driver/accel_bma422.h"
+#include "driver/accelgyro_bmi260.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "driver/retimer/ps8811.h"
+#include "driver/retimer/ps8818_public.h"
+#include "driver/temp_sensor/pct2075.h"
+#include "driver/temp_sensor/sb_tsi.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "keyboard_8042.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "switch.h"
+#include "tablet_mode.h"
+#include "temp_sensor.h"
+#include "temp_sensor/pct2075.h"
+#include "temp_sensor/thermistor.h"
+#include "thermal.h"
+#include "usb_mux.h"
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* Motion sensor mutex */
+static struct mutex g_lid_mutex;
+static struct mutex g_base_mutex;
+
+/* Motion sensor private data */
+static struct bmi_drv_data_t g_bmi_data;
+static struct accelgyro_saved_data_t g_bma422_data;
+
+/* Matrix to rotate accelrator into standard reference frame */
+const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				       { 0, FLOAT_TO_FP(1), 0 },
+				       { 0, 0, FLOAT_TO_FP(-1) } };
+
+const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				      { 0, FLOAT_TO_FP(-1), 0 },
+				      { 0, 0, FLOAT_TO_FP(1) } };
+
+/*
+ * We have total 30 pins for keyboard connecter {-1, -1} mean
+ * the N/A pin that don't consider it and reserve index 0 area
+ * that we don't have pin 0.
+ */
+const int keyboard_factory_scan_pins[][2] = {
+	{ -1, -1 }, { 0, 5 },	{ 1, 1 }, { 1, 0 },   { 0, 6 },	  { 0, 7 },
+	{ -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 },   { -1, -1 }, { 1, 6 },
+	{ 1, 7 },   { 3, 1 },	{ 2, 0 }, { 1, 5 },   { 2, 6 },	  { 2, 7 },
+	{ 2, 1 },   { 2, 4 },	{ 2, 5 }, { 1, 2 },   { 2, 3 },	  { 2, 2 },
+	{ 3, 0 },   { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 },	  { -1, -1 },
+	{ -1, -1 },
+};
+const int keyboard_factory_scan_pins_used =
+	ARRAY_SIZE(keyboard_factory_scan_pins);
+
+struct motion_sensor_t motion_sensors[] = {
+	[BASE_ACCEL] = {
+		.name = "Base Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMI260,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &bmi260_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = &g_bmi_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = BMI_ACCEL_MIN_FREQ,
+		.max_frequency = BMI_ACCEL_MAX_FREQ,
+		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
+		.config = {
+			/* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+			/* Sensor on in S3 */
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 0,
+			},
+		},
+	},
+	[LID_ACCEL] = {
+		.name = "Lid Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMA422,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &bma4_accel_drv,
+		.mutex = &g_lid_mutex,
+		.drv_data = &g_bma422_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMA4_I2C_ADDR_PRIMARY,
+		.rot_standard_ref = &lid_standard_ref,
+		.min_frequency = BMA4_ACCEL_MIN_FREQ,
+		.max_frequency = BMA4_ACCEL_MAX_FREQ,
+		.default_range = 2, /* g, enough for laptop. */
+		.config = {
+			/* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 12500 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+			/* Sensor on in S3 */
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 12500 | ROUND_UP_FLAG,
+				.ec_rate = 0,
+			},
+		},
+	},
+	[BASE_GYRO] = {
+		.name = "Base Gyro",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMI260,
+		.type = MOTIONSENSE_TYPE_GYRO,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &bmi260_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = &g_bmi_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
+		.default_range = 1000, /* dps */
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = BMI_GYRO_MIN_FREQ,
+		.max_frequency = BMI_GYRO_MAX_FREQ,
+	},
+};
+unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+__override enum ec_error_list
+board_a1_ps8811_retimer_init(const struct usb_mux *me)
+{
+	/* Set channel A output swing */
+	RETURN_ERROR(ps8811_i2c_field_update(
+		me, PS8811_REG_PAGE1, PS8811_REG1_USB_CHAN_A_SWING,
+		PS8811_CHAN_A_SWING_MASK, 0x2 << PS8811_CHAN_A_SWING_SHIFT));
+
+	/* Set channel B output swing */
+	RETURN_ERROR(ps8811_i2c_field_update(
+		me, PS8811_REG_PAGE1, PS8811_REG1_USB_CHAN_B_SWING,
+		PS8811_CHAN_B_SWING_MASK, 0x2 << PS8811_CHAN_B_SWING_SHIFT));
+
+	/* Set channel B de-emphasis to -6dB and pre-shoot to 1.5 dB */
+	RETURN_ERROR(ps8811_i2c_field_update(
+		me, PS8811_REG_PAGE1, PS8811_REG1_USB_CHAN_B_DE_PS_LSB,
+		PS8811_CHAN_B_DE_PS_LSB_MASK, PS8811_CHAN_B_DE_6_PS_1_5_LSB));
+
+	RETURN_ERROR(ps8811_i2c_field_update(
+		me, PS8811_REG_PAGE1, PS8811_REG1_USB_CHAN_B_DE_PS_MSB,
+		PS8811_CHAN_B_DE_PS_MSB_MASK, PS8811_CHAN_B_DE_6_PS_1_5_MSB));
+
+	return EC_SUCCESS;
+}
+
+__override int board_c1_ps8818_mux_set(const struct usb_mux *me,
+				       mux_state_t mux_state)
+{
+	int rv = EC_SUCCESS;
+
+	/* USB specific config */
+	if (mux_state & USB_PD_MUX_USB_ENABLED) {
+		/* Boost the USB gain */
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_APTX1EQ_10G_LEVEL,
+					      PS8818_EQ_LEVEL_UP_MASK,
+					      PS8818_EQ_LEVEL_UP_19DB);
+		if (rv)
+			return rv;
+
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_APTX2EQ_10G_LEVEL,
+					      PS8818_EQ_LEVEL_UP_MASK,
+					      PS8818_EQ_LEVEL_UP_19DB);
+		if (rv)
+			return rv;
+
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_APTX1EQ_5G_LEVEL,
+					      PS8818_EQ_LEVEL_UP_MASK,
+					      PS8818_EQ_LEVEL_UP_19DB);
+		if (rv)
+			return rv;
+
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_APTX2EQ_5G_LEVEL,
+					      PS8818_EQ_LEVEL_UP_MASK,
+					      PS8818_EQ_LEVEL_UP_19DB);
+		if (rv)
+			return rv;
+
+		/* Set the RX input termination */
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_RX_PHY,
+					      PS8818_RX_INPUT_TERM_MASK,
+					      PS8818_RX_INPUT_TERM_112_OHM);
+		if (rv)
+			return rv;
+	}
+
+	/* DP specific config */
+	if (mux_state & USB_PD_MUX_DP_ENABLED) {
+		/* Boost the DP gain */
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_DPEQ_LEVEL,
+					      PS8818_DPEQ_LEVEL_UP_MASK,
+					      PS8818_DPEQ_LEVEL_UP_19DB);
+		if (rv)
+			return rv;
+
+		/* Enable HPD on the DB */
+		ioex_set_level(IOEX_USB_C1_IN_HPD, 1);
+	} else {
+		/* Disable HPD on the DB */
+		ioex_set_level(IOEX_USB_C1_IN_HPD, 0);
+	}
+
+	return rv;
+}
+
+/*
+ * ANX7491(A1) and ANX7451(C1) are on the same i2c bus. Both default
+ * to 0x29 for the USB i2c address. This moves ANX7451(C1) USB i2c
+ * address to 0x2A. ANX7491(A1) will stay at the default 0x29.
+ */
+uint16_t board_anx7451_get_usb_i2c_addr(const struct usb_mux *me)
+{
+	ASSERT(me->usb_port == USBC_PORT_C1);
+	return 0x2a;
+}
+
+/*
+ * Base Gyro Sensor dynamic configuration
+ */
+static int base_gyro_config;
+
+static void board_update_motion_sensor_config(void)
+{
+	if (board_is_convertible()) {
+		base_gyro_config = BASE_GYRO_BMI260;
+		ccprints("BASE GYRO is BMI260");
+
+		motion_sensor_count = ARRAY_SIZE(motion_sensors);
+		/* Enable Base Accel and Gyro interrupt */
+		gpio_enable_interrupt(GPIO_6AXIS_INT_L);
+	} else {
+		motion_sensor_count = 0;
+		gmr_tablet_switch_disable();
+		/* Base accel is not stuffed, don't allow line to float */
+		gpio_set_flags(GPIO_6AXIS_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
+	}
+}
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	switch (base_gyro_config) {
+	case BASE_GYRO_BMI260:
+	default:
+		bmi260_interrupt(signal);
+		break;
+	}
+}
+
+static void board_init(void)
+{
+	board_update_motion_sensor_config();
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+static void board_chipset_startup(void)
+{
+	if (get_board_version() > 1)
+		pct2075_init();
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
+
+int board_get_soc_temp_k(int idx, int *temp_k)
+{
+	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	return pct2075_get_val_k(idx, temp_k);
+}
+
+int board_get_soc_temp_mk(int *temp_mk)
+{
+	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	return pct2075_get_val_mk(PCT2075_SOC, temp_mk);
+}
+
+int board_get_ambient_temp_mk(int *temp_mk)
+{
+	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	return pct2075_get_val_mk(PCT2075_AMB, temp_mk);
+}
+
+/* ADC Channels */
+const struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_SOC] = {
+		.name = "SOC",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_CHARGER] = {
+		.name = "CHARGER",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_MEMORY] = {
+		.name = "MEMORY",
+		.input_ch = NPCX_ADC_CH2,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_CORE_IMON1] = {
+		.name = "CORE_I",
+		.input_ch = NPCX_ADC_CH3,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_SOC_IMON2] = {
+		.name = "SOC_I",
+		.input_ch = NPCX_ADC_CH4,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* Temp Sensors */
+static int board_get_memory_temp(int, int *);
+
+const struct pct2075_sensor_t pct2075_sensors[] = {
+	{ I2C_PORT_SENSOR, PCT2075_I2C_ADDR_FLAGS0 },
+	{ I2C_PORT_SENSOR, PCT2075_I2C_ADDR_FLAGS7 },
+};
+BUILD_ASSERT(ARRAY_SIZE(pct2075_sensors) == PCT2075_COUNT);
+
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_SOC] = {
+		.name = "SOC",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = board_get_soc_temp_k,
+		.idx = PCT2075_SOC,
+	},
+	[TEMP_SENSOR_CHARGER] = {
+		.name = "Charger",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_CHARGER,
+	},
+	[TEMP_SENSOR_MEMORY] = {
+		.name = "Memory",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = board_get_memory_temp,
+		.idx = ADC_TEMP_SENSOR_MEMORY,
+	},
+	[TEMP_SENSOR_CPU] = {
+		.name = "CPU",
+		.type = TEMP_SENSOR_TYPE_CPU,
+		.read = sb_tsi_get_val,
+		.idx = 0,
+	},
+	[TEMP_SENSOR_AMBIENT] = {
+		.name = "Ambient",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = pct2075_get_val_k,
+		.idx = PCT2075_AMB,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+static int board_get_memory_temp(int idx, int *temp_k)
+{
+	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
+		return EC_ERROR_NOT_POWERED;
+	return get_temp_3v3_30k9_47k_4050b(idx, temp_k);
+}
+
+/* keyboard config */
+static const struct ec_response_keybd_config main_kb = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &main_kb;
+}
+
+void board_set_current_limit(void)
+{
+	const int no_battery_current_limit_override_ma = 6000;
+	/*
+	 * When there is no battery, override charger current limit to
+	 * prevent brownout during boot.
+	 */
+	if (battery_is_present() == BP_NO) {
+		ccprints("No Battery Found - Override Current Limit to %dmA",
+			 no_battery_current_limit_override_ma);
+		charger_set_input_current_limit(
+			CHARGER_SOLO, no_battery_current_limit_override_ma);
+	}
+}
+DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, board_set_current_limit,
+	     HOOK_PRIO_INIT_EXTPOWER);
diff --git a/board/dewatt/board.h b/board/dewatt/board.h
new file mode 100644
index 0000000000..58990c97d3
--- /dev/null
+++ b/board/dewatt/board.h
@@ -0,0 +1,110 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Guybrush board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* Baseboard features */
+#include "baseboard.h"
+
+/* Motion sensing drivers */
+
+/* Keyboard features */
+#define CONFIG_KEYBOARD_FACTORY_TEST
+#define CONFIG_KEYBOARD_REFRESH_ROW3
+
+/* Tablet Mode Switch */
+#define CONFIG_TABLET_MODE_SWITCH
+
+/* Sensors */
+#define CONFIG_ACCELGYRO_BMI260
+#define CONFIG_ACCELGYRO_BMI260_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+#define CONFIG_ACCEL_BMA4XX
+
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
+
+/* EC console commands */
+#define CONFIG_CMD_ACCELS
+#define CONFIG_CMD_ACCEL_INFO
+#define CONFIG_CMD_BUTTON
+
+/* USB Type C and USB PD defines */
+#define CONFIG_USB_MUX_ANX7451
+#define CONFIG_USBC_RETIMER_ANX7451
+
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_CURRENT_MA 3250
+#define PD_MAX_VOLTAGE_MV 20000
+/* Max Power = 65 W */
+#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
+
+/* USB Type A Features */
+
+/* BC 1.2 */
+
+/* Volume Button feature */
+
+/* Fan features */
+#define CONFIG_FAN_RPM_CUSTOM
+
+/* LED features */
+#define CONFIG_LED_COMMON
+#define CONFIG_LED_ONOFF_STATES
+
+/* Thermal Config */
+#define CONFIG_TEMP_SENSOR_PCT2075
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+/* Motion sensor interrupt */
+void motion_interrupt(enum gpio_signal signal);
+
+/* Battery Types */
+enum battery_type {
+	BATTERY_AP19B8M,
+	BATTERY_TYPE_COUNT,
+};
+
+enum base_accelgyro_type {
+	BASE_GYRO_NONE = 0,
+	BASE_GYRO_BMI260 = 1,
+};
+
+/* ADC Channels */
+enum adc_channel {
+	ADC_TEMP_SENSOR_SOC = 0,
+	ADC_TEMP_SENSOR_CHARGER,
+	ADC_TEMP_SENSOR_MEMORY,
+	ADC_CORE_IMON1,
+	ADC_SOC_IMON2,
+	ADC_CH_COUNT
+};
+
+/* Temp Sensors */
+enum temp_sensor_id {
+	TEMP_SENSOR_SOC = 0,
+	TEMP_SENSOR_CHARGER,
+	TEMP_SENSOR_MEMORY,
+	TEMP_SENSOR_CPU,
+	TEMP_SENSOR_AMBIENT,
+	TEMP_SENSOR_COUNT
+};
+
+/* PCT2075 sensors */
+enum pct2075_sensor {
+	PCT2075_SOC,
+	PCT2075_AMB,
+	PCT2075_COUNT,
+};
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/dewatt/board_fw_config.c b/board/dewatt/board_fw_config.c
new file mode 100644
index 0000000000..7128a153ca
--- /dev/null
+++ b/board/dewatt/board_fw_config.c
@@ -0,0 +1,29 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "base_fw_config.h"
+#include "board_fw_config.h"
+
+bool board_is_convertible(void)
+{
+	return 1;
+}
+
+bool board_has_kblight(void)
+{
+	return (get_fw_config_field(FW_CONFIG_KBLIGHT_OFFSET,
+				    FW_CONFIG_KBLIGHT_WIDTH) ==
+		FW_CONFIG_KBLIGHT_YES);
+}
+
+enum board_usb_c1_mux board_get_usb_c1_mux(void)
+{
+	return USB_C1_MUX_PS8818;
+};
+
+enum board_usb_a1_retimer board_get_usb_a1_retimer(void)
+{
+	return USB_A1_RETIMER_UNKNOWN;
+};
diff --git a/board/dewatt/board_fw_config.h b/board/dewatt/board_fw_config.h
new file mode 100644
index 0000000000..4477aca6fd
--- /dev/null
+++ b/board/dewatt/board_fw_config.h
@@ -0,0 +1,37 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _GUYBRUSH_BOARD_FW_CONFIG__H_
+#define _GUYBRUSH_BOARD_FW_CONFIG__H_
+
+/****************************************************************************
+ * Guybrush CBI FW Configuration
+ */
+
+/*
+ * USB Daughter Board (2 bits)
+ */
+#define FW_CONFIG_USB_DB_OFFSET 0
+#define FW_CONFIG_USB_DB_WIDTH 2
+#define FW_CONFIG_USB_DB_A1_PS8811_C1_PS8818 0
+#define FW_CONFIG_USB_DB_A1_ANX7491_C1_ANX7451 1
+
+/*
+ * Form Factor (1 bits)
+ */
+#define FW_CONFIG_FORM_FACTOR_OFFSET 2
+#define FW_CONFIG_FORM_FACTOR_WIDTH 1
+#define FW_CONFIG_FORM_FACTOR_CLAMSHELL 0
+#define FW_CONFIG_FORM_FACTOR_CONVERTIBLE 1
+
+/*
+ * Keyboard Backlight (1 bit)
+ */
+#define FW_CONFIG_KBLIGHT_OFFSET 3
+#define FW_CONFIG_KBLIGHT_WIDTH 1
+#define FW_CONFIG_KBLIGHT_NO 0
+#define FW_CONFIG_KBLIGHT_YES 1
+
+#endif /* _GUYBRUSH_CBI_FW_CONFIG__H_ */
diff --git a/board/dewatt/build.mk b/board/dewatt/build.mk
new file mode 100644
index 0000000000..8a1ce35e1e
--- /dev/null
+++ b/board/dewatt/build.mk
@@ -0,0 +1,12 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+BASEBOARD:=guybrush
+
+board-y=board.o
+board-y+=board_fw_config.o led.o battery.o thermal.o
diff --git a/board/dewatt/ec.tasklist b/board/dewatt/ec.tasklist
new file mode 100644
index 0000000000..14ecddebc9
--- /dev/null
+++ b/board/dewatt/ec.tasklist
@@ -0,0 +1,26 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, VENTI_TASK_STACK_SIZE)
diff --git a/board/dewatt/gpio.inc b/board/dewatt/gpio.inc
new file mode 100644
index 0000000000..9798239af5
--- /dev/null
+++ b/board/dewatt/gpio.inc
@@ -0,0 +1,28 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the board GPIOs that we care about. */
+
+#include "base_gpio.inc"
+
+GPIO_INT(6AXIS_INT_L,		PIN(A, 0), GPIO_INT_FALLING | GPIO_PULL_UP, motion_interrupt)		/* 6 Axis IMU */
+GPIO_INT(TABLET_MODE,		PIN(C, 1), GPIO_INT_BOTH, gmr_tablet_switch_isr)			/* 360 Tablet Mode */
+
+/* LED Signals */
+ALTERNATE(/*EC_PWM_LED_CHRG_L*/	PIN_MASK(C, BIT(4)), 0, 			MODULE_PWM, 0)		/* Charging LED */
+ALTERNATE(/*EC_PWM_LED_FULL_L*/	PIN_MASK(8, BIT(0)), 0, 			MODULE_PWM, 0)		/* Full LED */
+
+/* Test Points */
+GPIO(EC_GPIO56,			PIN(5, 6), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(EC_PS2_CLK,		PIN(6, 7), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(EC_PS2_DAT,		PIN(7, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(EC_PS2_RST,		PIN(6, 2), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(EC_GPIOB0,			PIN(B, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(EC_GPIO81,			PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(EC_FLPRG2,			PIN(8, 6), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(EC_PSL_GPO,		PIN(D, 7), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(EC_PWM7,			PIN(6, 0), GPIO_INPUT | GPIO_PULL_UP)
\ No newline at end of file
diff --git a/board/dewatt/led.c b/board/dewatt/led.c
new file mode 100644
index 0000000000..05bc7d88fc
--- /dev/null
+++ b/board/dewatt/led.c
@@ -0,0 +1,124 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Guybrush specific PWM LED settings.
+ */
+
+#include "common.h"
+#include "cros_board_info.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+#include "pwm.h"
+
+/* Note PWM LEDs are active low */
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
+
+#define CPRINTS(format, args...) cprints(CC_PWM, format, ##args)
+
+__override const int led_charge_lvl_1 = 5;
+
+__override const int led_charge_lvl_2 = 97;
+
+static enum pwm_channel pwm_ch_led_blue;
+static enum pwm_channel pwm_ch_led_amber;
+
+static void led_pwm_ch_init(void)
+{
+	int val;
+
+	pwm_ch_led_blue = PWM_CH_LED_FULL;
+	pwm_ch_led_amber = PWM_CH_LED_CHRG;
+
+	/*
+	 * Ver1: GPIOC4(PWM2) -> Blue LED
+	 *       GPIO80(PWM3) -> Amber LED
+	 */
+	if (cbi_get_board_version(&val) == EC_SUCCESS && val <= 1) {
+		pwm_ch_led_blue = PWM_CH_LED_CHRG;
+		pwm_ch_led_amber = PWM_CH_LED_FULL;
+	}
+}
+DECLARE_HOOK(HOOK_INIT, led_pwm_ch_init, HOOK_PRIO_INIT_PWM - 1);
+
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_S5] = { { EC_LED_COLOR_BLUE,
+					       LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_BLUE,
+					   2 * LED_ONE_SEC } },
+	};
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_BATTERY_LED,
+};
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_AMBER:
+		pwm_enable(pwm_ch_led_amber, LED_ON_LVL);
+		pwm_enable(pwm_ch_led_blue, LED_OFF_LVL);
+		break;
+	case EC_LED_COLOR_BLUE:
+		pwm_enable(pwm_ch_led_amber, LED_OFF_LVL);
+		pwm_enable(pwm_ch_led_blue, LED_ON_LVL);
+		break;
+	case LED_OFF:
+		pwm_enable(pwm_ch_led_amber, LED_OFF_LVL);
+		pwm_enable(pwm_ch_led_blue, LED_OFF_LVL);
+		break;
+	default: /* Unsupported colors */
+		CPRINTS("Unsupported LED color: %d", color);
+		pwm_enable(pwm_ch_led_amber, LED_OFF_LVL);
+		pwm_enable(pwm_ch_led_blue, LED_OFF_LVL);
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		brightness_range[EC_LED_COLOR_BLUE] = 1;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		if (brightness[EC_LED_COLOR_BLUE] != 0)
+			led_set_color_battery(EC_LED_COLOR_BLUE);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(EC_LED_COLOR_AMBER);
+		else
+			led_set_color_battery(LED_OFF);
+	} else {
+		CPRINTS("Unsupported LED set: %d", led_id);
+		return EC_ERROR_INVAL;
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/board/dewatt/thermal.c b/board/dewatt/thermal.c
new file mode 100644
index 0000000000..bd63fda984
--- /dev/null
+++ b/board/dewatt/thermal.c
@@ -0,0 +1,144 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Guybrush board-specific configuration */
+
+#include "console.h"
+#include "fan.h"
+#include "thermal.h"
+#include "util.h"
+
+/* Console output macros */
+#define CPUTS(outstr) cputs(CC_THERMAL, outstr)
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
+
+const struct fan_conf fan_conf_0 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
+	.pgood_gpio = GPIO_S0_PGOOD,
+	.enable_gpio = -1,
+};
+const struct fan_rpm fan_rpm_0 = {
+	.rpm_min = 3000,
+	.rpm_start = 3000,
+	.rpm_max = 6000,
+};
+const struct fan_t fans[] = {
+	[FAN_CH_0] = {
+		.conf = &fan_conf_0,
+		.rpm = &fan_rpm_0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
+
+struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT] = {
+	[TEMP_SENSOR_SOC] = {
+		.temp_host = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
+			[EC_TEMP_THRESH_HALT] = C_TO_K(85),
+		},
+		.temp_host_release = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
+		},
+		.temp_fan_off = C_TO_K(27),
+		.temp_fan_max = C_TO_K(80),
+	},
+	[TEMP_SENSOR_CHARGER] = {
+		.temp_host = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
+			[EC_TEMP_THRESH_HALT] = C_TO_K(85),
+		},
+		.temp_host_release = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
+		},
+		.temp_fan_off = 0,
+		.temp_fan_max = 0,
+	},
+	[TEMP_SENSOR_MEMORY] = {
+		.temp_host = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
+			[EC_TEMP_THRESH_HALT] = C_TO_K(85),
+		},
+		.temp_host_release = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
+		},
+		.temp_fan_off = 0,
+		.temp_fan_max = 0,
+	},
+	[TEMP_SENSOR_CPU] = {
+		.temp_host = {
+			[EC_TEMP_THRESH_WARN] = C_TO_K(100),
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(105),
+			[EC_TEMP_THRESH_HALT] = C_TO_K(108),
+		},
+		.temp_host_release = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(85),
+		},
+		.temp_fan_off = 0,
+		.temp_fan_max = 0,
+	},
+	/*
+	 * Note: Leave ambient entries at 0, both as it does not represent a
+	 * hotspot and as not all boards have this sensor
+	 */
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
+
+struct fan_step {
+	int on;
+	int off;
+	int rpm;
+};
+
+static const struct fan_step fan_table[] = {
+	{ .on = 0, .off = 1, .rpm = 0 },
+	{ .on = 6, .off = 2, .rpm = 3000 },
+	{ .on = 28, .off = 15, .rpm = 3300 },
+	{ .on = 34, .off = 26, .rpm = 3700 },
+	{ .on = 39, .off = 32, .rpm = 4000 },
+	{ .on = 45, .off = 38, .rpm = 4300 },
+	{ .on = 51, .off = 43, .rpm = 4700 },
+	{ .on = 74, .off = 62, .rpm = 5400 },
+};
+#define NUM_FAN_LEVELS ARRAY_SIZE(fan_table)
+
+int fan_percent_to_rpm(int fan, int pct)
+{
+	static int current_level;
+	static int previous_pct;
+	int i;
+
+	/*
+	 * Compare the pct and previous pct, we have the three paths :
+	 *  1. decreasing path. (check the off point)
+	 *  2. increasing path. (check the on point)
+	 *  3. invariant path. (return the current RPM)
+	 */
+	if (pct < previous_pct) {
+		for (i = current_level; i >= 0; i--) {
+			if (pct <= fan_table[i].off)
+				current_level = i - 1;
+			else
+				break;
+		}
+	} else if (pct > previous_pct) {
+		for (i = current_level + 1; i < NUM_FAN_LEVELS; i++) {
+			if (pct >= fan_table[i].on)
+				current_level = i;
+			else
+				break;
+		}
+	}
+
+	if (current_level < 0)
+		current_level = 0;
+
+	previous_pct = pct;
+
+	if (fan_table[current_level].rpm != fan_get_rpm_target(FAN_CH(fan)))
+		CPRINTS("Setting fan RPM to %d", fan_table[current_level].rpm);
+
+	return fan_table[current_level].rpm;
+}
diff --git a/board/dewatt/vif_override.xml b/board/dewatt/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/dewatt/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/dibbi/board.c b/board/dibbi/board.c
new file mode 100644
index 0000000000..063211c0c4
--- /dev/null
+++ b/board/dibbi/board.c
@@ -0,0 +1,426 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Dibbi board-specific configuration */
+
+#include "adc_chip.h"
+#include "board.h"
+#include "button.h"
+#include "cec.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "driver/cec/bitbang.h"
+#include "driver/ppc/syv682x_public.h"
+#include "driver/tcpm/it83xx_pd.h"
+#include "driver/temp_sensor/thermistor.h"
+#include "driver/usb_mux/it5205.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "intc.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "switch.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "tcpm/tcpci.h"
+#include "temp_sensor.h"
+#include "uart.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_ppc.h"
+
+#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	[ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH0 },
+	[ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH2 },
+	[ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH3 },
+	[ADC_VBUS] = { .name = "VBUS", /* 113/1113 voltage divider */
+		       .factor_mul = ADC_MAX_MVOLT * 1113,
+		       .factor_div = (ADC_READ_MAX + 1) * 113,
+		       .shift = 0,
+		       .channel = CHIP_ADC_CH4 },
+	[ADC_TEMP_SENSOR_3] = { .name = "TEMP_SENSOR3",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH13 },
+	[ADC_PPVAR_PWR_IN_IMON] = { .name = "ADC_PPVAR_PWR_IN_IMON",
+				    .factor_mul = ADC_MAX_MVOLT,
+				    .factor_div = ADC_READ_MAX + 1,
+				    .shift = 0,
+				    .channel = CHIP_ADC_CH15 },
+	[ADC_SNS_PPVAR_PWR_IN] = { .name = "ADC_SNS_PPVAR_PWR_IN",
+				   .factor_mul = ADC_MAX_MVOLT,
+				   .factor_div = ADC_READ_MAX + 1,
+				   .shift = 0,
+				   .channel = CHIP_ADC_CH16 },
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* TCPCs */
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_EMBEDDED,
+		.drv = &it83xx_tcpm_drv,
+	},
+};
+
+/* PPCs */
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.frs_en = GPIO_EC_USB_C0_FRS_EN,
+		.drv = &syv682x_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
+
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/* USB Muxes */
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+			},
+	},
+};
+
+/* USB-A ports */
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_USB_A0_VBUS,
+	GPIO_EN_USB_A1_VBUS,
+	GPIO_EN_USB_A2_VBUS,
+	GPIO_EN_USB_A3_VBUS,
+};
+
+/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_LED_RED] = {
+		.channel = 1,
+		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
+		.freq_hz = 2400,
+	},
+
+	[PWM_CH_LED_GREEN] = {
+		.channel = 2,
+		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
+		.freq_hz = 2400,
+	},
+
+	[PWM_CH_LED_BLUE] = {
+		.channel = 3,
+		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
+		.freq_hz = 2400,
+	}
+
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+/* Thermistors */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "SoC power",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/* CEC ports */
+const struct cec_config_t cec_config[] = {
+	[CEC_PORT_0] = {
+		.drv = &bitbang_cec_drv,
+		.offline_policy = NULL,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(cec_config) == CEC_PORT_COUNT);
+
+void board_init(void)
+{
+	gpio_enable_interrupt(GPIO_BJ_ADP_PRESENT);
+
+	/* Enable PPC interrupt */
+	gpio_enable_interrupt(GPIO_USB_C0_FAULT_L);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * Nothing to do.  TCPC C0 is internal.
+	 */
+}
+
+__override void board_power_5v_enable(int enable)
+{
+	/*
+	 * Nothing to do. 5V should always be enabled while in Z1 or above.
+	 */
+}
+
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
+{
+	int insufficient_power =
+		(charge_ma * charge_mv) <
+		(CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON * 1000);
+	/* TODO(b/259467280) blink LED on error */
+	(void)insufficient_power;
+}
+
+int board_vbus_source_enabled(int port)
+{
+	if (port != CHARGE_PORT_TYPEC0)
+		return 0;
+
+	return ppc_is_sourcing_vbus(port);
+}
+
+/* Vconn control for integrated ITE TCPC */
+void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
+{
+	/*
+	 * We ignore the cc_pin and PPC vconn because polarity and PPC vconn
+	 * should already be set correctly in the PPC driver via the pd
+	 * state machine.
+	 */
+}
+
+/******************************************************************************/
+/*
+ * Since dibbi has no battery, it must source all of its power from either
+ * USB-C or the barrel jack (preferred). Fizz operates in continuous safe
+ * mode (charge_manager_leave_safe_mode() will never be called), which
+ * modifies port selection as follows:
+ *
+ * - Dual-role / dedicated capability of the port partner is ignored.
+ * - Charge ceiling on PD voltage transition is ignored.
+ * - CHARGE_PORT_NONE will never be selected.
+ */
+
+/* List of BJ adapters */
+enum bj_adapter {
+	BJ_NONE,
+	BJ_65W_19V,
+};
+
+/* Barrel-jack power adapter ratings. */
+static const struct charge_port_info bj_adapters[] = {
+	[BJ_NONE] = { .current = 0, .voltage = 0 },
+	[BJ_65W_19V] = { .current = 3420, .voltage = 19000 },
+};
+#define BJ_ADP_RATING_DEFAULT BJ_65W_19V /* BJ power ratings default */
+#define ADP_DEBOUNCE_MS 1000 /* Debounce time for BJ plug/unplug */
+
+/* Debounced connection state of the barrel jack */
+static int8_t bj_adp_connected = -1;
+static void adp_connect_deferred(void)
+{
+	const struct charge_port_info *pi;
+	int connected = gpio_get_level(GPIO_BJ_ADP_PRESENT);
+
+	/* Debounce */
+	if (connected == bj_adp_connected)
+		return;
+
+	if (connected) {
+		pi = &bj_adapters[BJ_ADP_RATING_DEFAULT];
+	} else {
+		/* No barrel-jack, zero out this power supply */
+		pi = &bj_adapters[BJ_NONE];
+	}
+	/* This will result in a call to board_set_active_charge_port */
+	charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED,
+				     DEDICATED_CHARGE_PORT, pi);
+	bj_adp_connected = connected;
+}
+DECLARE_DEFERRED(adp_connect_deferred);
+
+/* IRQ for BJ plug/unplug. It shouldn't be called if BJ is the power source. */
+void adp_connect_interrupt(enum gpio_signal signal)
+{
+	hook_call_deferred(&adp_connect_deferred_data, ADP_DEBOUNCE_MS * MSEC);
+}
+
+int board_set_active_charge_port(int port)
+{
+	const int active_port = charge_manager_get_active_charge_port();
+
+	CPRINTUSB("Requested charge port change to %d", port);
+
+	if (port < 0 || CHARGE_PORT_COUNT <= port)
+		return EC_ERROR_INVAL;
+
+	if (port == active_port)
+		return EC_SUCCESS;
+
+	/* Don't sink from a source port */
+	if (board_vbus_source_enabled(port))
+		return EC_ERROR_INVAL;
+
+	if (!chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
+		int bj_requested;
+
+		if (charge_manager_get_active_charge_port() != CHARGE_PORT_NONE)
+			/* Change is only permitted while the system is off */
+			return EC_ERROR_INVAL;
+
+		/*
+		 * Current setting is no charge port but the AP is on, so the
+		 * charge manager is out of sync (probably because we're
+		 * reinitializing after sysjump). Reject requests that aren't
+		 * in sync with our outputs.
+		 */
+		bj_requested = port == CHARGE_PORT_BARRELJACK;
+		if (bj_adp_connected != bj_requested)
+			return EC_ERROR_INVAL;
+	}
+
+	CPRINTUSB("New charger p%d", port);
+
+	switch (port) {
+	case CHARGE_PORT_TYPEC0:
+		ppc_vbus_sink_enable(USBC_PORT_C0, 1);
+		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_OD, 0);
+		break;
+	case CHARGE_PORT_BARRELJACK:
+		/* Make sure BJ adapter is sourcing power */
+		if (!gpio_get_level(GPIO_BJ_ADP_PRESENT))
+			return EC_ERROR_INVAL;
+		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_OD, 1);
+		ppc_vbus_sink_enable(USBC_PORT_C0, 1);
+		break;
+	default:
+		return EC_ERROR_INVAL;
+	}
+
+	return EC_SUCCESS;
+}
+
+static void board_charge_manager_init(void)
+{
+	enum charge_port port;
+
+	/*
+	 * Initialize all charge suppliers to 0. The charge manager waits until
+	 * all ports have reported in before doing anything.
+	 */
+	for (int i = 0; i < CHARGE_PORT_COUNT; i++) {
+		for (int j = 0; j < CHARGE_SUPPLIER_COUNT; j++)
+			charge_manager_update_charge(j, i, NULL);
+	}
+
+	port = gpio_get_level(GPIO_BJ_ADP_PRESENT) ? CHARGE_PORT_BARRELJACK :
+						     CHARGE_PORT_TYPEC0;
+	CPRINTUSB("Power source is p%d (%s)", port,
+		  port == CHARGE_PORT_TYPEC0 ? "USB-C" : "BJ");
+
+	/* Initialize the power source supplier */
+	switch (port) {
+	case CHARGE_PORT_TYPEC0:
+		typec_set_input_current_limit(port, 3000, 5000);
+		break;
+	case CHARGE_PORT_BARRELJACK:
+		charge_manager_update_charge(
+			CHARGE_SUPPLIER_DEDICATED, DEDICATED_CHARGE_PORT,
+			&bj_adapters[BJ_ADP_RATING_DEFAULT]);
+		break;
+	}
+
+	/* Report charge state from the barrel jack. */
+	adp_connect_deferred();
+}
+DECLARE_HOOK(HOOK_INIT, board_charge_manager_init,
+	     HOOK_PRIO_INIT_CHARGE_MANAGER + 1);
+
+__override int extpower_is_present(void)
+{
+	/*
+	 * There's no battery, so running this method implies we have power.
+	 */
+	return 1;
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	if (signal == GPIO_USB_C0_FAULT_L)
+		syv682x_interrupt(USBC_PORT_C0);
+}
+
+/* I2C Ports */
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_EEPROM_SCL,
+	  .sda = GPIO_EC_I2C_EEPROM_SDA },
+
+	{ .name = "hdmi2_edid",
+	  .port = I2C_PORT_HDMI2_EDID,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_HDMI2_EDID_SCL,
+	  .sda = GPIO_EC_I2C_HDMI2_EDID_SDA },
+
+	{ .name = "usbc0",
+	  .port = I2C_PORT_USB_C0,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C0_SCL,
+	  .sda = GPIO_EC_I2C_USB_C0_SDA },
+
+	{ .name = "hdmi2_src_ddc",
+	  .port = I2C_PORT_HDMI2_SRC_DDC,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_HDMI2_SRC_DDC_SCL,
+	  .sda = GPIO_EC_I2C_HDMI2_SRC_DDC_SDA },
+
+	{ .name = "hdmi1_edid",
+	  .port = I2C_PORT_HDMI1_EDID,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_HDMI1_EDID_SCL,
+	  .sda = GPIO_EC_I2C_HDMI1_EDID_SDA },
+
+	{ .name = "hdmi1_src_ddc",
+	  .port = I2C_PORT_HDMI1_SRC_DDC,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_HDMI1_SRC_DDC_SCL,
+	  .sda = GPIO_EC_I2C_HDMI1_SRC_DDC_SDA },
+};
+
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
diff --git a/board/dibbi/board.h b/board/dibbi/board.h
new file mode 100644
index 0000000000..0958f754fc
--- /dev/null
+++ b/board/dibbi/board.h
@@ -0,0 +1,176 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Dibbi board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* Select Baseboard features */
+#define VARIANT_DEDEDE_EC_IT8320
+#include "baseboard.h"
+
+/* System unlocked in early development */
+#define CONFIG_SYSTEM_UNLOCKED
+
+#define CONFIG_CMD_CHARGER_DUMP
+
+/* I2C Bus Configuration */
+#define I2C_PORT_HDMI2_EDID IT83XX_I2C_CH_B
+#undef I2C_PORT_USB_C0
+#define I2C_PORT_USB_C0 IT83XX_I2C_CH_C
+#define I2C_PORT_HDMI2_SRC_DDC IT83XX_I2C_CH_D
+#define I2C_PORT_HDMI1_EDID IT83XX_I2C_CH_E
+#define I2C_PORT_HDMI1_SRC_DDC IT83XX_I2C_CH_F
+
+/* Power */
+#undef CONFIG_CHARGER
+#undef CONFIG_CHARGER_DISCHARGE_ON_AC
+#undef CONFIG_USB_PD_VBUS_MEASURE_CHARGER
+#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 16000
+#define PD_MAX_VOLTAGE_MV 20000
+#undef PD_MAX_CURRENT_MA
+#define PD_MAX_CURRENT_MA 3250
+#undef PD_MAX_POWER_MW
+#define PD_MAX_POWER_MW 65000
+#define CONFIG_USB_PD_VBUS_DETECT_GPIO
+
+/* Override macro for C0 only */
+#define PORT_TO_HPD(port) (GPIO_USB_C0_DP_HPD)
+
+/* Power: Dedicated barreljack charger port */
+#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT
+#define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1
+#define DEDICATED_CHARGE_PORT 1
+
+/* USB Type-C */
+#undef CONFIG_USB_CHARGER
+#undef CONFIG_USB_MUX_PI3USB31532
+
+/* TCPC */
+#define CONFIG_USB_PD_PORT_MAX_COUNT 1
+#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0: ITE EC TCPC */
+#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1
+
+/* PPC */
+#define CONFIG_USB_PD_DISCHARGE_PPC
+#define CONFIG_USB_PD_VBUS_DETECT_PPC
+#define CONFIG_USBC_PPC
+#define CONFIG_USBC_PPC_SYV682X
+
+/* USB Mux and Retimer */
+#define CONFIG_USB_MUX_IT5205 /* C0: ITE Mux */
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */
+
+/* USB Type A Features */
+#define CONFIG_USB_PORT_POWER_DUMB
+#define USB_PORT_COUNT 4 /* Type A ports */
+
+/* No battery */
+#undef CONFIG_BATTERY_CUT_OFF
+#undef CONFIG_BATTERY_PRESENT_GPIO
+#undef CONFIG_BATTERY_REQUESTS_NIL_WHEN_DEAD
+#undef CONFIG_BATTERY_REVIVE_DISCONNECT
+#undef CONFIG_BATTERY_SMART
+
+/* LED */
+#define CONFIG_LED_PWM
+#define CONFIG_LED_PWM_COUNT 1
+
+/* PWM */
+#define CONFIG_PWM
+
+/* Thermistors */
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_THERMISTOR
+#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
+
+/* Buttons */
+#define CONFIG_DEDICATED_RECOVERY_BUTTON
+#define CONFIG_DEDICATED_RECOVERY_BUTTON_2
+#define CONFIG_DEDICATED_RECOVERY_BUTTON_FLAGS BUTTON_FLAG_ACTIVE_HIGH
+#define CONFIG_POWER_BUTTON
+#define CONFIG_POWER_BUTTON_IGNORE_LID
+#define CONFIG_POWER_BUTTON_X86
+#define CONFIG_EMULATED_SYSRQ
+
+/* CEC */
+#define CONFIG_CEC
+#define CONFIG_CEC_BITBANG
+#define CEC_GPIO_OUT GPIO_HDMI2_CEC
+#define CEC_GPIO_IN GPIO_HDMI2_CEC_IN
+#undef CEC_GPIO_PULL_UP /* Pull-up to PP3300_Z1 */
+
+/* No Keyboard */
+#undef CONFIG_KEYBOARD_COL2_INVERTED
+#undef CONFIG_KEYBOARD_PROTOCOL_8042
+#undef CONFIG_CMD_KEYBOARD
+#undef CONFIG_KEYBOARD_BOOT_KEYS
+#undef CONFIG_KEYBOARD_RUNTIME_KEYS
+
+/* No backlight */
+#undef CONFIG_BACKLIGHT_LID
+#undef GPIO_ENABLE_BACKLIGHT
+
+/* Unused features - Misc */
+#undef CONFIG_HIBERNATE
+#undef CONFIG_VOLUME_BUTTONS
+#undef CONFIG_LID_SWITCH
+#undef CONFIG_TABLET_MODE
+#undef CONFIG_TABLET_MODE_SWITCH
+#undef CONFIG_GMR_TABLET_MODE
+#undef GPIO_TABLET_MODE_L
+
+/* Unused GPIOs */
+#undef GPIO_USB_C1_DP_HPD
+
+/* Pin renaming */
+#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_OD
+#define GPIO_RECOVERY_L_2 GPIO_H1_EC_RECOVERY_BTN_ODL
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum charge_port {
+	CHARGE_PORT_TYPEC0,
+	CHARGE_PORT_BARRELJACK,
+};
+
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_COUNT };
+
+enum pwm_channel {
+	PWM_CH_LED_RED,
+	PWM_CH_LED_GREEN,
+	PWM_CH_LED_BLUE,
+	PWM_CH_COUNT,
+};
+
+/* ADC channels */
+enum adc_channel {
+	ADC_VSNS_PP3300_A, /* ADC0 */
+	ADC_TEMP_SENSOR_1, /* ADC2 */
+	ADC_TEMP_SENSOR_2, /* ADC3 */
+	ADC_VBUS, /* ADC4 */
+	ADC_TEMP_SENSOR_3, /* ADC13 */
+	ADC_PPVAR_PWR_IN_IMON, /* ADC15 */
+	ADC_SNS_PPVAR_PWR_IN, /* ADC16 */
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1,
+	TEMP_SENSOR_2,
+	TEMP_SENSOR_3,
+	TEMP_SENSOR_COUNT
+};
+
+enum cec_port { CEC_PORT_0, CEC_PORT_COUNT };
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/dibbi/build.mk b/board/dibbi/build.mk
new file mode 100644
index 0000000000..8336360a6a
--- /dev/null
+++ b/board/dibbi/build.mk
@@ -0,0 +1,15 @@
+# -*- makefile -*-
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=it83xx
+CHIP_FAMILY:=it8320
+CHIP_VARIANT:=it8320dx
+BASEBOARD:=dedede
+BOARD:=dibbi
+
+board-y=board.o led.o usb_pd_policy.o
diff --git a/board/dibbi/ec.tasklist b/board/dibbi/ec.tasklist
new file mode 100644
index 0000000000..f3afa44da1
--- /dev/null
+++ b/board/dibbi/ec.tasklist
@@ -0,0 +1,17 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CEC, cec_task, NULL, TASK_STACK_SIZE)
diff --git a/board/dibbi/gpio.inc b/board/dibbi/gpio.inc
new file mode 100644
index 0000000000..ccd83d3266
--- /dev/null
+++ b/board/dibbi/gpio.inc
@@ -0,0 +1,162 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+/* Power State interrupts */
+GPIO_INT(SLP_S4_L,		PIN(I, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,		PIN(H, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(SLP_S0_L,		PIN(E, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,		PIN(G, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID0,	PIN(D, 0), GPIO_INT_BOTH | GPIO_SEL_1P8V, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID1,	PIN(K, 1), GPIO_INT_BOTH | GPIO_SEL_1P8V, power_signal_interrupt)
+GPIO_INT(RSMRST_PWRGD_L,	PIN(E, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(CPU_C10_GATE_L,	PIN(G, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_DRAM_OD,		PIN(D, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(PG_PP1050_ST_OD,	PIN(L, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(EC_VSNS_PP3300_S5,	PIN(I, 0), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_VCCIO_EXT_OD,	PIN(D, 7), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(ESPI_RESET_L,		PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt)
+
+GPIO_INT(H1_EC_PWR_BTN_ODL,	PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
+#ifdef CONFIG_LOW_POWER_IDLE
+/* Used to wake up the EC from Deep Doze mode when writing to console */
+GPIO_INT(UART1_RX,		PIN(B, 0), GPIO_INT_BOTH, uart_deepsleep_interrupt)	/* UART_DBG_TX_EC_RX */
+#endif
+
+/* Other interrupts */
+GPIO_INT(EC_WP_OD,		PIN(A, 6), GPIO_INT_BOTH, switch_interrupt)
+/* Directly connected recovery button */
+GPIO_INT(EC_RECOVERY_BTN_OD,	PIN(K, 7), GPIO_INT_BOTH, button_interrupt)
+/* Recovery button input from H1 */
+GPIO_INT(H1_EC_RECOVERY_BTN_ODL,PIN(K, 4), GPIO_INT_BOTH, button_interrupt)
+GPIO_INT(BJ_ADP_PRESENT,	PIN(A, 7), GPIO_INT_BOTH, adp_connect_interrupt)
+GPIO_INT(USB_C0_FAULT_L,	PIN(K, 0), GPIO_INT_FALLING, ppc_interrupt)
+/* CEC interrupt */
+GPIO_INT(HDMI2_CEC_IN,		PIN(J, 3), GPIO_INT_BOTH, cec_gpio_interrupt)
+
+/* Power sequence GPIOs */
+GPIO(EC_AP_PSYS,		PIN(J, 2), GPIO_OUT_LOW)
+GPIO(EC_AP_RTCRST,		PIN(K, 2), GPIO_OUT_LOW)
+GPIO(EC_AP_PWR_BTN_ODL,		PIN(B, 6), GPIO_ODR_HIGH)
+GPIO(EC_AP_DPWROK,		PIN(L, 7), GPIO_OUT_LOW)
+GPIO(EC_AP_RSMRST_L,		PIN(H, 0), GPIO_OUT_LOW)
+GPIO(EC_AP_WAKE_ODL,		PIN(D, 5), GPIO_ODR_HIGH)
+GPIO(SYS_RST_ODL,		PIN(D, 1), GPIO_ODR_HIGH)
+GPIO(EC_AP_SYS_PWROK,		PIN(F, 2), GPIO_OUT_LOW)
+GPIO(PG_PP5000_U_OD,		PIN(J, 0), GPIO_INPUT)
+GPIO(EN_PP5000_U,		PIN(K, 5), GPIO_OUT_HIGH)
+GPIO(PG_PP3300_A,		PIN(B, 5), GPIO_INPUT)
+GPIO(EN_PP3300_A,		PIN(C, 5), GPIO_OUT_LOW)
+GPIO(EC_AP_PCH_PWROK_OD,	PIN(D, 6), GPIO_ODR_LOW)
+/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
+GPIO(EN_VCCST,			PIN(D, 4), GPIO_INPUT)
+GPIO(EN_VCCIO_EXT,		PIN(B, 2), GPIO_OUT_LOW)
+GPIO(EC_PROCHOT_ODL,		PIN(I, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(EC_AP_VCCST_PWRGD_OD,	PIN(E, 5), GPIO_ODR_LOW)
+GPIO(ALL_SYS_PWRGD,		PIN(B, 7), GPIO_OUT_LOW)
+GPIO(EN_PPVAR_BJ_ADP_OD,	PIN(E, 3), GPIO_ODR_HIGH)
+GPIO(ACK_PPVAR_BJ_ADP_ODL,	PIN(A, 0), GPIO_INPUT)
+
+/* Required for icelake chipset code, but implemented through other means for dedede */
+UNIMPLEMENTED(AC_PRESENT)
+UNIMPLEMENTED(PG_EC_DSW_PWROK)
+UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
+
+/* Required for dedede baseboard but not used in dibbi */
+UNIMPLEMENTED(USB_C0_INT_ODL)
+UNIMPLEMENTED(EN_SLP_Z)
+UNIMPLEMENTED(EC_BATTERY_PRES_ODL)
+
+/* I2C pins - Alternate function below configures I2C module on these pins */
+GPIO(EC_I2C_EEPROM_SCL,		PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SDA,		PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SCL,		PIN(F, 6), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SDA,		PIN(F, 7), GPIO_INPUT)
+GPIO(EC_I2C_HDMI1_EDID_SCL,	PIN(E, 0), GPIO_INPUT)
+GPIO(EC_I2C_HDMI1_EDID_SDA,	PIN(E, 7), GPIO_INPUT)
+GPIO(EC_I2C_HDMI2_EDID_SCL,	PIN(C, 1), GPIO_INPUT)
+GPIO(EC_I2C_HDMI2_EDID_SDA,	PIN(C, 2), GPIO_INPUT)
+GPIO(EC_I2C_HDMI1_SRC_DDC_SCL,	PIN(A, 4), GPIO_INPUT)
+GPIO(EC_I2C_HDMI1_SRC_DDC_SDA,	PIN(A, 5), GPIO_INPUT)
+GPIO(EC_I2C_HDMI2_SRC_DDC_SCL,	PIN(H, 1), GPIO_INPUT)
+GPIO(EC_I2C_HDMI2_SRC_DDC_SDA,	PIN(H, 2), GPIO_INPUT)
+
+/* USB pins */
+GPIO(EC_AP_USB_C0_HPD,		PIN(L, 4), GPIO_OUT_LOW)
+GPIO(EN_USB_A0_VBUS,		PIN(L, 6), GPIO_OUT_LOW)
+GPIO(EN_USB_A1_VBUS,		PIN(C, 6), GPIO_OUT_LOW)
+GPIO(EN_USB_A2_VBUS,		PIN(C, 4), GPIO_OUT_LOW)
+GPIO(EN_USB_A3_VBUS,		PIN(J, 5), GPIO_OUT_LOW)
+GPIO(EC_USB_C0_FRS_EN,		PIN(K, 6), GPIO_OUT_LOW)
+GPIO(USB_C0_SBU_MUX_FAULT,	PIN(I, 7), GPIO_INPUT)
+
+/* MKBP event synchronization */
+/* TODO(b/257833880) Check whether this pin is needed */
+GPIO(EC_AP_MKBP_INT_L,		PIN(L, 5), GPIO_ODR_HIGH)
+
+/* HDMI */
+GPIO(HDMI1_CEC,			PIN(F, 0), GPIO_OUT_LOW)
+GPIO(HDMI2_CEC,			PIN(F, 1), GPIO_ODR_HIGH)
+GPIO(HDMI1_SRC_HPD,		PIN(F, 3), GPIO_INPUT)
+GPIO(HDMI2_SRC_HPD,		PIN(KSO_L, 3), GPIO_INPUT)
+GPIO(EC_HDMI1_SRC_HPD_OUT,	PIN(I, 6), GPIO_OUT_LOW)
+GPIO(EC_HDMI2_SRC_HPD_OUT,	PIN(KSO_L, 4), GPIO_OUT_LOW)
+GPIO(HDMI1_EDID_SEL,		PIN(J, 1), GPIO_OUT_LOW)
+GPIO(HDMI2_EDID_SEL,		PIN(KSO_L, 5), GPIO_OUT_LOW)
+GPIO(EDID_BTN_ODL,		PIN(C, 3), GPIO_INPUT)
+GPIO(EC_EN_PP5000_HDMI1,	PIN(KSO_L, 6), GPIO_OUT_LOW)
+GPIO(EC_EN_PP5000_HDMI2,	PIN(KSO_L, 7), GPIO_OUT_LOW)
+
+/* Misc */
+GPIO(EC_ENTERING_RW,		PIN(C, 7), GPIO_OUT_LOW)
+GPIO(CCD_MODE_ODL,		PIN(H, 5), GPIO_ODR_HIGH)
+GPIO(ECH1_PACKET_MODE,		PIN(C, 0), GPIO_OUT_LOW)
+GPIO(EN_RS232_X,		PIN(E, 6), GPIO_OUT_LOW)
+GPIO(UART0_RX,	 		PIN(B, 1), GPIO_OUT_LOW)	/* UART_EC_TX_DBG_RX */
+
+
+/* NC pins, enable internal pull-down to avoid floating state. */
+GPIO(GPIOG0_NC, PIN(G, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG3_NC, PIN(G, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG4_NC, PIN(G, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG5_NC, PIN(G, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG6_NC, PIN(G, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG7_NC, PIN(G, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOH4_NC, PIN(H, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOH6_NC, PIN(H, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOI4_NC, PIN(I, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ4_NC, PIN(J, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ6_NC, PIN(J, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOK3_NC, PIN(K, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOM6_NC, PIN(M, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+
+/* Alternate functions GPIO definitions */
+/* UART */
+ALTERNATE(PIN_MASK(B, BIT(0) | BIT(1)), 0, MODULE_UART, 0)		/* UART for debug */
+
+/* I2C */
+ALTERNATE(PIN_MASK(B, BIT(3) | BIT(4)), 0, MODULE_I2C, 0)		/* I2C0 - EEPROM */
+ALTERNATE(PIN_MASK(C, BIT(1) | BIT(2)), 0, MODULE_I2C, 0)		/* I2C1 - HDMI2_EDID */
+ALTERNATE(PIN_MASK(F, BIT(6) | BIT(7)), 0, MODULE_I2C, 0)		/* I2C2 - USB_C0 */
+ALTERNATE(PIN_MASK(E, BIT(0) | BIT(7)), 0, MODULE_I2C, 0)		/* I2C4 - HDMI1_EDID */
+ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), 0, MODULE_I2C, 0)		/* I2C5 - HDMI1_SRC_DDC */
+ALTERNATE(PIN_MASK(H, BIT(1) | BIT(2)), 0, MODULE_I2C, 0)		/* I2C3 - HDMI2_SRC_DDC */
+
+/* ADC */
+/* ADC2: TEMP_SENSOR_1, ADC3: TEMP_SENSOR_2, ADC4: VBUS */
+ALTERNATE(PIN_MASK(I, BIT(2) | BIT(3) | BIT(4)), 0, MODULE_ADC, 0)
+/*
+ * ADC13: TEMP_SENSOR_3
+ * ADC15: ANALOG_PPVAR_PWR_IN_IMON
+ * ADC16: SNS_PPVAR_PWR_IN
+ */
+ALTERNATE(PIN_MASK(L, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0)
+
+/* PWM */
+ALTERNATE(PIN_MASK(A, BIT(1) | BIT(2) | BIT(3)), 0, MODULE_PWM, 0) /* LED_[R,G,B]_ODL */
diff --git a/board/dibbi/led.c b/board/dibbi/led.c
new file mode 100644
index 0000000000..fb423877c6
--- /dev/null
+++ b/board/dibbi/led.c
@@ -0,0 +1,80 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Dibbi specific PWM LED settings. */
+
+#include "common.h"
+#include "ec_commands.h"
+#include "led_pwm.h"
+#include "pwm.h"
+#include "util.h"
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_POWER_LED,
+};
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+/* One physical LED with red, green, and blue. */
+struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = {
+	/* Red, Green, Blue */
+	[EC_LED_COLOR_RED] = { 100, 0, 0 },
+	[EC_LED_COLOR_GREEN] = { 0, 100, 0 },
+	[EC_LED_COLOR_BLUE] = { 0, 0, 100 },
+	[EC_LED_COLOR_YELLOW] = { 50, 50, 0 },
+	[EC_LED_COLOR_WHITE] = { 50, 50, 50 },
+	[EC_LED_COLOR_AMBER] = { 70, 30, 0 },
+};
+
+/* One logical LED with red, green, and blue channels. */
+struct pwm_led pwm_leds[CONFIG_LED_PWM_COUNT] = {
+	{
+		.ch0 = PWM_CH_LED_RED,
+		.ch1 = PWM_CH_LED_GREEN,
+		.ch2 = PWM_CH_LED_BLUE,
+		.enable = &pwm_enable,
+		.set_duty = &pwm_set_duty,
+	},
+};
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	memset(brightness_range, '\0',
+	       sizeof(*brightness_range) * EC_LED_COLOR_COUNT);
+	brightness_range[EC_LED_COLOR_RED] = 100;
+	brightness_range[EC_LED_COLOR_GREEN] = 100;
+	brightness_range[EC_LED_COLOR_BLUE] = 100;
+	brightness_range[EC_LED_COLOR_YELLOW] = 100;
+	brightness_range[EC_LED_COLOR_WHITE] = 100;
+	brightness_range[EC_LED_COLOR_AMBER] = 100;
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	enum pwm_led_id pwm_id;
+
+	/* Convert ec_led_id to pwm_led_id. */
+	if (led_id == EC_LED_ID_POWER_LED)
+		pwm_id = PWM_LED0;
+	else
+		return EC_ERROR_UNKNOWN;
+
+	if (brightness[EC_LED_COLOR_RED])
+		set_pwm_led_color(pwm_id, EC_LED_COLOR_RED);
+	else if (brightness[EC_LED_COLOR_GREEN])
+		set_pwm_led_color(pwm_id, EC_LED_COLOR_GREEN);
+	else if (brightness[EC_LED_COLOR_BLUE])
+		set_pwm_led_color(pwm_id, EC_LED_COLOR_BLUE);
+	else if (brightness[EC_LED_COLOR_YELLOW])
+		set_pwm_led_color(pwm_id, EC_LED_COLOR_YELLOW);
+	else if (brightness[EC_LED_COLOR_WHITE])
+		set_pwm_led_color(pwm_id, EC_LED_COLOR_WHITE);
+	else if (brightness[EC_LED_COLOR_AMBER])
+		set_pwm_led_color(pwm_id, EC_LED_COLOR_AMBER);
+	else
+		/* Otherwise, the "color" is "off". */
+		set_pwm_led_color(pwm_id, -1);
+
+	return EC_SUCCESS;
+}
diff --git a/board/dibbi/usb_pd_policy.c b/board/dibbi/usb_pd_policy.c
new file mode 100644
index 0000000000..b28e1ae7d4
--- /dev/null
+++ b/board/dibbi/usb_pd_policy.c
@@ -0,0 +1,72 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "charger.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "gpio.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+int pd_check_vconn_swap(int port)
+{
+	/* Allow VCONN swaps if the AP is on */
+	return gpio_get_level(GPIO_EN_PP5000_U);
+}
+
+void pd_power_supply_reset(int port)
+{
+	int prev_en;
+
+	if (port < 0 || port >= board_get_usb_pd_port_count())
+		return;
+
+	prev_en = ppc_is_sourcing_vbus(port);
+
+	/* Disable VBUS source */
+	ppc_vbus_source_enable(port, 0);
+
+	/* Enable discharge if we were previously sourcing 5V */
+	if (prev_en)
+		pd_set_vbus_discharge(port, 1);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	/* Disable charging */
+	rv = ppc_vbus_sink_enable(port, 0);
+	if (rv)
+		return rv;
+
+	pd_set_vbus_discharge(port, 0);
+
+	/* Enable VBUS source */
+	rv = ppc_vbus_source_enable(port, 1);
+	if (rv)
+		return rv;
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+__override int pd_snk_is_vbus_provided(int port)
+{
+	if (port != CHARGE_PORT_TYPEC0)
+		return 0;
+
+	return ppc_is_vbus_present(port);
+}
diff --git a/board/dibbi/vif_override.xml b/board/dibbi/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/dibbi/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/dingdong/board.c b/board/dingdong/board.c
index 0ca41dec45..bc9bb3803a 100644
--- a/board/dingdong/board.c
+++ b/board/dingdong/board.c
@@ -1,27 +1,27 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 /* Dingdong dongle configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "common.h"
 #include "ec_version.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "registers.h"
+#include "task.h"
+#include "timer.h"
 #include "usb_bb.h"
 #include "usb_descriptor.h"
 #include "usb_pd.h"
-#include "task.h"
-#include "timer.h"
 #include "util.h"
 
 static volatile uint64_t hpd_prev_ts;
 static volatile int hpd_prev_level;
 
 void hpd_event(enum gpio_signal signal);
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /**
@@ -97,7 +97,7 @@ void board_config_pre_init(void)
 	/* enable SYSCFG clock */
 	STM32_RCC_APB2ENR |= BIT(0);
 	/* Remap USART DMA to match the USART driver */
-	STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10);/* Remap USART1 RX/TX DMA */
+	STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10); /* Remap USART1 RX/TX DMA */
 }
 
 /* Initialize board. */
@@ -116,12 +116,12 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* USB PD CC lines sensing. Converted to mV (3300mV/4096). */
-	[ADC_CH_CC1_PD] = {"USB_C_CC1_PD", 3300, 4096, 0, STM32_AIN(1)},
+	[ADC_CH_CC1_PD] = { "USB_C_CC1_PD", 3300, 4096, 0, STM32_AIN(1) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-const void * const usb_strings[] = {
+const void *const usb_strings[] = {
 	[USB_STR_DESC] = usb_string_desc,
-	[USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."),
+	[USB_STR_VENDOR] = USB_STRING_DESC("Google LLC"),
 	[USB_STR_PRODUCT] = USB_STRING_DESC("Dingdong"),
 	[USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32),
 	[USB_STR_BB_URL] = USB_STRING_DESC(USB_GOOGLE_TYPEC_URL),
diff --git a/board/dingdong/board.h b/board/dingdong/board.h
index 64947960ba..52c3b740e4 100644
--- a/board/dingdong/board.h
+++ b/board/dingdong/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,7 +15,6 @@
 #define CONFIG_UART_CONSOLE 1
 
 /* Optional features */
-#define CONFIG_STM_HWTIMER32
 #define CONFIG_ADC
 #define CONFIG_BOARD_PRE_INIT
 #define CONFIG_HW_CRC
@@ -39,7 +38,7 @@
 #define CONFIG_USB_PD_IDENTITY_SW_VERS 1
 #define CONFIG_USB_PD_VBUS_DETECT_NONE
 #define CONFIG_USB_PD_LOGGING
-#undef  CONFIG_EVENT_LOG_SIZE
+#undef CONFIG_EVENT_LOG_SIZE
 #define CONFIG_EVENT_LOG_SIZE 256
 #define CONFIG_USB_PD_PORT_MAX_COUNT 1
 #define CONFIG_USB_PD_TCPC
@@ -63,7 +62,7 @@
 
 /* Timer selection */
 #define TIM_CLOCK32 2
-#define TIM_ADC     3
+#define TIM_ADC 3
 
 #include "gpio_signal.h"
 
@@ -86,14 +85,14 @@ enum usb_strings {
 };
 
 /* we are never a source : don't care about power supply */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  0 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 0 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 0 /* us */
 
 /* Define typical operating power and max power */
 #define PD_OPERATING_POWER_MW 1000
-#define PD_MAX_POWER_MW       1500
-#define PD_MAX_CURRENT_MA     300
-#define PD_MAX_VOLTAGE_MV     5000
+#define PD_MAX_POWER_MW 1500
+#define PD_MAX_CURRENT_MA 300
+#define PD_MAX_VOLTAGE_MV 5000
 
 #endif /* !__ASSEMBLER__ */
 
@@ -101,10 +100,10 @@ enum usb_strings {
 #define USB_DEV_CLASS USB_CLASS_BILLBOARD
 
 /* USB interface indexes (use define rather than enum to expand them) */
-#define USB_IFACE_COUNT     0
+#define USB_IFACE_COUNT 0
 
 /* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL   0
-#define USB_EP_COUNT     1
+#define USB_EP_CONTROL 0
+#define USB_EP_COUNT 1
 
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/dingdong/build.mk b/board/dingdong/build.mk
index 18799c3b9f..b6fbbe7a9e 100644
--- a/board/dingdong/build.mk
+++ b/board/dingdong/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
+# Copyright 2014 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -11,4 +11,4 @@ CHIP_FAMILY:=stm32f0
 CHIP_VARIANT:=stm32f07x
 
 board-y=board.o
-board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
+board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o usb_pd_pdo.o
diff --git a/board/dingdong/ec.tasklist b/board/dingdong/ec.tasklist
index 41fc047d6a..5a82344122 100644
--- a/board/dingdong/ec.tasklist
+++ b/board/dingdong/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/dingdong/gpio.inc b/board/dingdong/gpio.inc
index ec1e9a7fa9..d8ea0dfc8f 100644
--- a/board/dingdong/gpio.inc
+++ b/board/dingdong/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
+ * Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/dingdong/usb_pd_config.h b/board/dingdong/usb_pd_config.h
index 2f01c275a8..5a7dfd12a6 100644
--- a/board/dingdong/usb_pd_config.h
+++ b/board/dingdong/usb_pd_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -49,7 +49,7 @@ static inline void spi_enable_clock(int port)
 
 #define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
 #define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
-#define TIM_CCR_CS  1
+#define TIM_CCR_CS 1
 #define EXTI_COMP_MASK(p) BIT(21)
 #define IRQ_COMP STM32_IRQ_COMP
 /* triggers packet detection on comparator falling edge */
@@ -88,9 +88,8 @@ static inline void pd_tx_enable(int port, int polarity)
 static inline void pd_tx_disable(int port, int polarity)
 {
 	/* output low on SPI TX (PB4) to disable the FET */
-	STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B)
-				   & ~(3 << (2*4)))
-				   |  (1 << (2*4));
+	STM32_GPIO_MODER(GPIO_B) =
+		(STM32_GPIO_MODER(GPIO_B) & ~(3 << (2 * 4))) | (1 << (2 * 4));
 	/* put the low level reference in Hi-Z */
 	gpio_set_level(GPIO_PD_CC1_TX_EN, 0);
 }
@@ -101,8 +100,8 @@ static inline void pd_select_polarity(int port, int polarity)
 	 * use the right comparator : CC1 -> PA1 (COMP1 INP)
 	 * use VrefInt / 2 as INM (about 600mV)
 	 */
-	STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK)
-		| STM32_COMP_CMP1EN | STM32_COMP_CMP1INSEL_VREF12;
+	STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK) |
+			 STM32_COMP_CMP1EN | STM32_COMP_CMP1INSEL_VREF12;
 }
 
 /* Initialize pins used for TX and put them in Hi-Z */
@@ -111,7 +110,9 @@ static inline void pd_tx_init(void)
 	gpio_config_module(MODULE_USB_PD, 1);
 }
 
-static inline void pd_set_host_mode(int port, int enable) {}
+static inline void pd_set_host_mode(int port, int enable)
+{
+}
 
 static inline void pd_config_init(int port, uint8_t power_role)
 {
diff --git a/board/dingdong/usb_pd_pdo.c b/board/dingdong/usb_pd_pdo.c
new file mode 100644
index 0000000000..7b4ed3e2d8
--- /dev/null
+++ b/board/dingdong/usb_pd_pdo.c
@@ -0,0 +1,20 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "compile_time_macros.h"
+#include "usb_pd.h"
+#include "usb_pd_pdo.h"
+
+#define PDO_FIXED_FLAGS PDO_FIXED_COMM_CAP
+
+/* Source PDOs */
+const uint32_t pd_src_pdo[] = {};
+const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
+
+/* Fake PDOs : we just want our pre-defined voltages */
+const uint32_t pd_snk_pdo[] = {
+	PDO_FIXED(5000, 500, PDO_FIXED_FLAGS),
+};
+const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
diff --git a/board/dingdong/usb_pd_pdo.h b/board/dingdong/usb_pd_pdo.h
new file mode 100644
index 0000000000..e1b628c3a8
--- /dev/null
+++ b/board/dingdong/usb_pd_pdo.h
@@ -0,0 +1,17 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_BOARD_DINGDONG_USB_PD_PDO_H
+#define __CROS_EC_BOARD_DINGDONG_USB_PD_PDO_H
+
+#include "stdint.h"
+
+extern const uint32_t pd_src_pdo[0];
+extern const int pd_src_pdo_cnt;
+
+extern const uint32_t pd_snk_pdo[1];
+extern const int pd_snk_pdo_cnt;
+
+#endif /* __CROS_EC_BOARD_DINGDONG_USB_PD_PDO_H */
diff --git a/board/dingdong/usb_pd_policy.c b/board/dingdong/usb_pd_policy.c
index f17802c82a..c7e3f0e4a9 100644
--- a/board/dingdong/usb_pd_policy.c
+++ b/board/dingdong/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,32 +7,21 @@
 #include "board.h"
 #include "common.h"
 #include "console.h"
+#include "cros_version.h"
 #include "ec_commands.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "registers.h"
 #include "task.h"
 #include "timer.h"
-#include "util.h"
-#include "usb_bb.h"
 #include "usb_api.h"
+#include "usb_bb.h"
 #include "usb_pd.h"
-#include "version.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-#define PDO_FIXED_FLAGS PDO_FIXED_COMM_CAP
-
-/* Source PDOs */
-const uint32_t pd_src_pdo[] = {};
-const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
+#include "usb_pd_tcpm.h"
+#include "util.h"
 
-/* Fake PDOs : we just want our pre-defined voltages */
-const uint32_t pd_snk_pdo[] = {
-		PDO_FIXED(5000,   500, PDO_FIXED_FLAGS),
-};
-const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 /* Holds valid object position (opos) for entered mode */
 static int alt_mode[PD_AMODE_COUNT];
@@ -80,28 +69,22 @@ int pd_check_power_swap(int port)
 	return 0;
 }
 
-int pd_check_data_swap(int port,
-		       enum pd_data_role data_role)
+int pd_check_data_swap(int port, enum pd_data_role data_role)
 {
 	/* Always refuse data swap */
 	return 0;
 }
 
-void pd_execute_data_swap(int port,
-			  enum pd_data_role data_role)
+void pd_execute_data_swap(int port, enum pd_data_role data_role)
 {
 	/* Do nothing */
 }
 
-void pd_check_pr_role(int port,
-		      enum pd_power_role pr_role,
-		      int flags)
+void pd_check_pr_role(int port, enum pd_power_role pr_role, int flags)
 {
 }
 
-void pd_check_dr_role(int port,
-		      enum pd_data_role dr_role,
-		      int flags)
+void pd_check_dr_role(int port, enum pd_data_role dr_role, int flags)
 {
 }
 /* ----------------- Vendor Defined Messages ------------------ */
@@ -114,8 +97,8 @@ const uint32_t vdo_idh = VDO_IDH(0, /* data caps as USB host */
 const uint32_t vdo_product = VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV);
 
 const uint32_t vdo_ama = VDO_AMA(CONFIG_USB_PD_IDENTITY_HW_VERS,
-				 CONFIG_USB_PD_IDENTITY_SW_VERS,
-				 0, 0, 0, 0, /* SS[TR][12] */
+				 CONFIG_USB_PD_IDENTITY_SW_VERS, 0, 0, 0,
+				 0, /* SS[TR][12] */
 				 0, /* Vconn power */
 				 0, /* Vconn power required */
 				 1, /* Vbus power required */
@@ -141,18 +124,16 @@ static int svdm_response_svids(int port, uint32_t *payload)
 #define OPOS_DP 1
 #define OPOS_GFU 1
 
-const uint32_t vdo_dp_modes[1] =  {
-	VDO_MODE_DP(0,             /* UFP pin cfg supported : none */
+const uint32_t vdo_dp_modes[1] = {
+	VDO_MODE_DP(0, /* UFP pin cfg supported : none */
 		    MODE_DP_PIN_E, /* DFP pin cfg supported */
-		    1,		   /* no usb2.0 signalling in AMode */
-		    CABLE_PLUG,    /* its a plug */
-		    MODE_DP_V13,   /* DPv1.3 Support, no Gen2 */
-		    MODE_DP_SNK)   /* Its a sink only */
+		    1, /* no usb2.0 signalling in AMode */
+		    CABLE_PLUG, /* its a plug */
+		    MODE_DP_V13, /* DPv1.3 Support, no Gen2 */
+		    MODE_DP_SNK) /* Its a sink only */
 };
 
-const uint32_t vdo_goog_modes[1] =  {
-	VDO_MODE_GOOGLE(MODE_GOOGLE_FU)
-};
+const uint32_t vdo_goog_modes[1] = { VDO_MODE_GOOGLE(MODE_GOOGLE_FU) };
 
 static int svdm_response_modes(int port, uint32_t *payload)
 {
@@ -174,13 +155,15 @@ static int dp_status(int port, uint32_t *payload)
 	if (opos != OPOS_DP)
 		return 0; /* nak */
 
-	payload[1] = VDO_DP_STATUS(0,                /* IRQ_HPD */
-				   (hpd == 1),       /* HPD_HI|LOW */
-				   0,		     /* request exit DP */
-				   0,		     /* request exit USB */
-				   0,		     /* MF pref */
+	payload[1] = VDO_DP_STATUS(0, /* IRQ_HPD */
+				   (hpd == 1), /* HPD_HI|LOW */
+				   0, /* request exit DP */
+				   0, /* request exit USB */
+				   0, /* MF pref */
 				   gpio_get_level(GPIO_PD_SBU_ENABLE),
-				   0,		     /* power low */
+				   0, /* power
+					 low
+				       */
 				   0x2);
 	return 2;
 }
@@ -219,9 +202,9 @@ static int svdm_enter_mode(int port, uint32_t *payload)
 	return rv;
 }
 
-int pd_alt_mode(int port, enum tcpm_transmit_type type, uint16_t svid)
+int pd_alt_mode(int port, enum tcpci_msg_type type, uint16_t svid)
 {
-	if (type != TCPC_TX_SOP)
+	if (type != TCPCI_MSG_SOP)
 		return 0;
 
 	if (svid == USB_SID_DISPLAYPORT)
@@ -260,8 +243,7 @@ const struct svdm_response svdm_rsp = {
 	.exit_mode = &svdm_exit_mode,
 };
 
-int pd_custom_vdm(int port, int cnt, uint32_t *payload,
-		  uint32_t **rpayload)
+int pd_custom_vdm(int port, int cnt, uint32_t *payload, uint32_t **rpayload)
 {
 	int rsize;
 
diff --git a/board/dingdong/vif_override.xml b/board/dingdong/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/dingdong/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/dirinboz/battery.c b/board/dirinboz/battery.c
index f53143aa65..d02d424ba4 100644
--- a/board/dirinboz/battery.c
+++ b/board/dirinboz/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -120,7 +120,7 @@ const struct board_batt_params board_battery_info[] = {
 	},
 
 	/* DynaPack ATL Battery Information */
-	[BATTERY_DANAPACK_ATL] = {
+	[BATTERY_DYNAPACK_ATL] = {
 		.fuel_gauge = {
 			.manuf_name = "333-27-DA-A",
 			.ship_mode = {
@@ -149,7 +149,7 @@ const struct board_batt_params board_battery_info[] = {
 	},
 
 	/* DynaPack Coslight Battery Information */
-	[BATTERY_DANAPACK_COS] = {
+	[BATTERY_DYNAPACK_COS] = {
 		.fuel_gauge = {
 			.manuf_name = "333-2C-DA-A",
 			.ship_mode = {
diff --git a/board/dirinboz/board.c b/board/dirinboz/board.c
index 7517ee2130..efdcac76ef 100644
--- a/board/dirinboz/board.c
+++ b/board/dirinboz/board.c
@@ -1,15 +1,14 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "battery_smart.h"
 #include "button.h"
+#include "charge_state.h"
 #include "cros_board_info.h"
-#include "driver/accel_lis2dw12.h"
-#include "driver/accelgyro_lsm6dsm.h"
 #include "driver/bc12/pi3usb9201.h"
-#include "driver/ppc/aoz1380.h"
+#include "driver/ppc/aoz1380_public.h"
 #include "driver/ppc/nx20p348x.h"
 #include "driver/tcpm/nct38xx.h"
 #include "driver/usb_mux/amd_fp5.h"
@@ -20,6 +19,7 @@
 #include "gpio.h"
 #include "hooks.h"
 #include "ioexpander.h"
+#include "keyboard_8042_sharedlib.h"
 #include "lid_switch.h"
 #include "power.h"
 #include "power_button.h"
@@ -29,121 +29,21 @@
 #include "system.h"
 #include "tablet_mode.h"
 #include "task.h"
+#include "temp_sensor.h"
+#include "thermal.h"
 #include "usb_charge.h"
 #include "usb_pd_tcpm.h"
 #include "usbc_ppc.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* This I2C moved. Temporarily detect and support the V0 HW. */
 int I2C_PORT_BATTERY = I2C_PORT_BATTERY_V1;
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
-#ifdef HAS_TASK_MOTIONSENSE
-
-/* Motion sensors */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* sensor private data */
-static struct stprivate_data g_lis2dwl_data;
-static struct lsm6dsm_data g_lsm6dsm_data = LSM6DSM_DATA;
-
-/* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-/* TODO(gcc >= 5.0) Remove the casts to const pointer at rot_standard_ref */
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-	 .name = "Lid Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_LIS2DWL,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &lis2dw12_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_lis2dwl_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = LIS2DWL_ADDR1_FLAGS,
-	 .rot_standard_ref = NULL,
-	 .default_range = 2, /* g, enough for laptop. */
-	 .min_frequency = LIS2DW12_ODR_MIN_VAL,
-	 .max_frequency = LIS2DW12_ODR_MAX_VAL,
-	 .config = {
-		 /* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 12500 | ROUND_UP_FLAG,
-		},
-		 /* Sensor on for lid angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	},
-	},
-
-	[BASE_ACCEL] = {
-	 .name = "Base Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_LSM6DSM,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &lsm6dsm_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = LSM6DSM_ST_DATA(g_lsm6dsm_data,
-			MOTIONSENSE_TYPE_ACCEL),
-	 .int_signal = GPIO_6AXIS_INT_L,
-	 .flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-	 .default_range = 4, /* g, enough for laptop */
-	 .rot_standard_ref = &base_standard_ref,
-	 .min_frequency = LSM6DSM_ODR_MIN_VAL,
-	 .max_frequency = LSM6DSM_ODR_MAX_VAL,
-	 .config = {
-		 /* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 13000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-		/* Sensor on for angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-	 },
-	},
-
-	[BASE_GYRO] = {
-	 .name = "Base Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_LSM6DSM,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &lsm6dsm_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = LSM6DSM_ST_DATA(g_lsm6dsm_data,
-			MOTIONSENSE_TYPE_GYRO),
-	.int_signal = GPIO_6AXIS_INT_L,
-	.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-	 .default_range = 1000 | ROUND_UP_FLAG, /* dps */
-	 .rot_standard_ref = &base_standard_ref,
-	 .min_frequency = LSM6DSM_ODR_MIN_VAL,
-	 .max_frequency = LSM6DSM_ODR_MAX_VAL,
-	},
-};
-
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-#endif /* HAS_TASK_MOTIONSENSE */
-
 /*****************************************************************************
  * Retimers
  */
@@ -171,8 +71,12 @@ DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, retimers_off, HOOK_PRIO_DEFAULT);
  * chip and it need a board specific driver.
  * Overall, it will use chained mux framework.
  */
-static int pi3usb221_set_mux(const struct usb_mux *me, mux_state_t mux_state)
+static int pi3usb221_set_mux(const struct usb_mux *me, mux_state_t mux_state,
+			     bool *ack_required)
 {
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
 	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
 		ioex_set_level(IOEX_USB_C0_SBU_FLIP, 1);
 	else
@@ -195,33 +99,43 @@ const struct usb_mux_driver usbc0_sbu_mux_driver = {
  * Since PI3USB221 is not a i2c device, .i2c_port and
  * .i2c_addr_flags are not required here.
  */
-const struct usb_mux usbc0_sbu_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &usbc0_sbu_mux_driver,
+const struct usb_mux_chain usbc0_sbu_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &usbc0_sbu_mux_driver,
+		},
 };
 
-struct usb_mux usbc1_amd_fp5_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.i2c_port = I2C_PORT_USB_AP_MUX,
-	.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
-	.driver = &amd_fp5_usb_mux_driver,
-	.flags = USB_MUX_FLAG_SET_WITHOUT_FLIP,
+struct usb_mux_chain usbc1_amd_fp5_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.i2c_port = I2C_PORT_USB_AP_MUX,
+			.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
+			.driver = &amd_fp5_usb_mux_driver,
+			.flags = USB_MUX_FLAG_SET_WITHOUT_FLIP,
+		},
 };
 
-struct usb_mux usb_muxes[] = {
+struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.i2c_port = I2C_PORT_USB_AP_MUX,
-		.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
-		.driver = &amd_fp5_usb_mux_driver,
-		.next_mux = &usbc0_sbu_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.i2c_port = I2C_PORT_USB_AP_MUX,
+			.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
+			.driver = &amd_fp5_usb_mux_driver,
+		},
+		.next = &usbc0_sbu_mux,
 	},
 	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = PS8743_I2C_ADDR1_FLAG,
-		.driver = &ps8743_usb_mux_driver,
-		.next_mux = &usbc1_amd_fp5_usb_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.i2c_port = I2C_PORT_TCPC1,
+			.i2c_addr_flags = PS8743_I2C_ADDR1_FLAG,
+			.driver = &ps8743_usb_mux_driver,
+		},
+		.next = &usbc1_amd_fp5_usb_mux,
 	}
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
@@ -264,8 +178,7 @@ void ppc_interrupt(enum gpio_signal signal)
 
 int board_set_active_charge_port(int port)
 {
-	int is_valid_port = (port >= 0 &&
-			     port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	int i;
 
 	if (port == CHARGE_PORT_NONE) {
@@ -286,7 +199,6 @@ int board_set_active_charge_port(int port)
 		return EC_ERROR_INVAL;
 	}
 
-
 	/* Check if the port is sourcing VBUS. */
 	if (ppc_is_sourcing_vbus(port)) {
 		CPRINTFUSB("Skip enable C%d", port);
@@ -368,27 +280,33 @@ const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
 
-static void reset_pd_port(int port, enum gpio_signal reset_gpio_l,
-			  int hold_delay, int finish_delay)
+static void reset_nct38xx_port(int port)
 {
+	enum gpio_signal reset_gpio_l;
+
+	if (port == USBC_PORT_C0)
+		reset_gpio_l = GPIO_USB_C0_TCPC_RST_L;
+	else if (port == USBC_PORT_C1)
+		reset_gpio_l = GPIO_USB_C1_TCPC_RST_L;
+	else
+		/* Invalid port: do nothing */
+		return;
+
 	gpio_set_level(reset_gpio_l, 0);
-	msleep(hold_delay);
+	msleep(NCT38XX_RESET_HOLD_DELAY_MS);
 	gpio_set_level(reset_gpio_l, 1);
-	if (finish_delay)
-		msleep(finish_delay);
+	nct38xx_reset_notify(port);
+	if (NCT3807_RESET_POST_DELAY_MS != 0)
+		msleep(NCT3807_RESET_POST_DELAY_MS);
 }
 
 void board_reset_pd_mcu(void)
 {
 	/* Reset TCPC0 */
-	reset_pd_port(USBC_PORT_C0, GPIO_USB_C0_TCPC_RST_L,
-		      NCT38XX_RESET_HOLD_DELAY_MS,
-		      NCT38XX_RESET_POST_DELAY_MS);
+	reset_nct38xx_port(USBC_PORT_C0);
 
 	/* Reset TCPC1 */
-	reset_pd_port(USBC_PORT_C1, GPIO_USB_C1_TCPC_RST_L,
-		      NCT38XX_RESET_HOLD_DELAY_MS,
-		      NCT38XX_RESET_POST_DELAY_MS);
+	reset_nct38xx_port(USBC_PORT_C1);
 }
 
 uint16_t tcpc_get_alert_status(void)
@@ -434,11 +352,11 @@ void bc12_interrupt(enum gpio_signal signal)
 {
 	switch (signal) {
 	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
 		break;
 
 	case GPIO_USB_C1_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12, 0);
+		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
 		break;
 
 	default:
@@ -452,11 +370,9 @@ int board_pd_set_frs_enable(int port, int enable)
 
 	/* Use the TCPC to enable fast switch when FRS included */
 	if (port == USBC_PORT_C0) {
-		rv = ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN,
-				    !!enable);
+		rv = ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN, !!enable);
 	} else {
-		rv = ioex_set_level(IOEX_USB_C1_TCPC_FASTSW_CTL_EN,
-				    !!enable);
+		rv = ioex_set_level(IOEX_USB_C1_TCPC_FASTSW_CTL_EN, !!enable);
 	}
 
 	return rv;
@@ -480,16 +396,12 @@ static void setup_fw_config(void)
 	ioex_enable_interrupt(IOEX_USB_C0_SBU_FAULT_ODL);
 	ioex_enable_interrupt(IOEX_USB_C1_SBU_FAULT_DB_ODL);
 
-	if (ec_config_has_lid_angle_tablet_mode()) {
-		/* Enable Gyro interrupts */
-		gpio_enable_interrupt(GPIO_6AXIS_INT_L);
-	} else {
-		motion_sensor_count = 0;
-		/* Device is clamshell only */
-		tablet_set_mode(0);
-		/* Gyro is not present, don't allow line to float */
-		gpio_set_flags(GPIO_6AXIS_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
-	}
+	/*
+	 * If keyboard is US2(KB_LAYOUT_1), we need translate right ctrl
+	 * to backslash(\|) key.
+	 */
+	if (ec_config_keyboard_layout() == KB_LAYOUT_1)
+		set_scancode_set2(4, 0, get_scancode_set2(2, 7));
 }
 DECLARE_HOOK(HOOK_INIT, setup_fw_config, HOOK_PRIO_INIT_I2C + 2);
 
@@ -505,12 +417,12 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 struct ioexpander_config_t ioex_config[] = {
 	[IOEX_C0_NCT3807] = {
 		.i2c_host_port = I2C_PORT_TCPC0,
-		.i2c_slave_addr = NCT38XX_I2C_ADDR1_1_FLAGS,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
 		.drv = &nct38xx_ioexpander_drv,
 	},
 	[IOEX_C1_NCT3807] = {
 		.i2c_host_port = I2C_PORT_TCPC1,
-		.i2c_slave_addr = NCT38XX_I2C_ADDR1_1_FLAGS,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
 		.drv = &nct38xx_ioexpander_drv,
 	},
 };
@@ -520,3 +432,117 @@ int usb_port_enable[USBA_PORT_COUNT] = {
 	IOEX_EN_USB_A0_5V,
 	IOEX_EN_USB_A1_5V_DB,
 };
+
+#ifdef CONFIG_KEYBOARD_FACTORY_TEST
+/*
+ * Map keyboard connector pins to EC GPIO pins for factory test.
+ * Pins mapped to {-1, -1} are skipped.
+ * The connector has 24 pins total, and there is no pin 0.
+ */
+const int keyboard_factory_scan_pins[][2] = {
+	{ 0, 5 }, { 1, 1 }, { 1, 0 }, { 0, 6 },	  { 0, 7 },   { 1, 4 },
+	{ 1, 3 }, { 1, 6 }, { 1, 7 }, { 3, 1 },	  { 2, 0 },   { 1, 5 },
+	{ 2, 6 }, { 2, 7 }, { 2, 1 }, { 2, 4 },	  { 2, 5 },   { 1, 2 },
+	{ 2, 3 }, { 2, 2 }, { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 },
+};
+const int keyboard_factory_scan_pins_used =
+	ARRAY_SIZE(keyboard_factory_scan_pins);
+#endif
+
+#define CHARGING_CURRENT_500mA 500
+
+int charger_profile_override(struct charge_state_data *curr)
+{
+	static int thermal_sensor_temp;
+	static int prev_thermal_sensor_temp;
+	static int limit_charge;
+	static int limit_usbc_power;
+	static int limit_usbc_power_backup;
+	enum tcpc_rp_value rp;
+
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return 0;
+
+	temp_sensor_read(TEMP_SENSOR_CHARGER, &thermal_sensor_temp);
+
+	if (thermal_sensor_temp > prev_thermal_sensor_temp) {
+		if (thermal_sensor_temp > C_TO_K(63))
+			limit_usbc_power = 1;
+
+		if (thermal_sensor_temp > C_TO_K(58)) {
+			if (curr->state == ST_CHARGE)
+				limit_charge = 1;
+		}
+	} else if (thermal_sensor_temp < prev_thermal_sensor_temp) {
+		if (thermal_sensor_temp < C_TO_K(62))
+			limit_usbc_power = 0;
+
+		if (thermal_sensor_temp < C_TO_K(57)) {
+			if (curr->state == ST_CHARGE)
+				limit_charge = 0;
+		}
+	}
+
+	if (limit_charge)
+		curr->requested_current = CHARGING_CURRENT_500mA;
+	else
+		curr->requested_current = curr->batt.desired_current;
+
+	if (limit_usbc_power != limit_usbc_power_backup) {
+		if (limit_usbc_power == 1)
+			rp = TYPEC_RP_1A5;
+		else
+			rp = TYPEC_RP_3A0;
+
+		ppc_set_vbus_source_current_limit(0, rp);
+		tcpm_select_rp_value(0, rp);
+		pd_update_contract(0);
+		limit_usbc_power_backup = limit_usbc_power;
+	}
+
+	prev_thermal_sensor_temp = thermal_sensor_temp;
+
+	return 0;
+}
+
+enum ec_status charger_profile_override_get_param(uint32_t param,
+						  uint32_t *value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+enum ec_status charger_profile_override_set_param(uint32_t param,
+						  uint32_t value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+__override struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT] = {
+	[TEMP_SENSOR_CHARGER] = {
+		.temp_host = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(63),
+			[EC_TEMP_THRESH_HALT] = C_TO_K(92),
+		},
+		.temp_host_release = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(62),
+		}
+	},
+	[TEMP_SENSOR_SOC] = {
+		.temp_host = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
+			[EC_TEMP_THRESH_HALT] = C_TO_K(85),
+		},
+		.temp_host_release = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(77),
+		}
+	},
+	[TEMP_SENSOR_CPU] = {
+		.temp_host = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(85),
+			[EC_TEMP_THRESH_HALT] = C_TO_K(90),
+		},
+		.temp_host_release = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(83),
+		}
+	},
+};
diff --git a/board/dirinboz/board.h b/board/dirinboz/board.h
index 2538918873..8c77d0665e 100644
--- a/board/dirinboz/board.h
+++ b/board/dirinboz/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,20 +10,24 @@
 
 #define VARIANT_ZORK_DALBOZ
 
-#include <stdbool.h>
 #include "baseboard.h"
 
-#define CONFIG_IO_EXPANDER_PCAL6408
-#define CONFIG_MKBP_USE_GPIO
+#include <stdbool.h>
 
 #define CONFIG_USBC_PPC_NX20P3483
-#define CONFIG_USB_MUX_PS8740
 #define CONFIG_USB_MUX_PS8743
 #define CONFIG_USB_MUX_RUNTIME_CONFIG
 
 #define CONFIG_USB_PD_PORT_MAX_COUNT 2
 #define CONFIG_USB_PORT_ENABLE_DYNAMIC
 
+#undef CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
+#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 40000
+
+#define CONFIG_CHARGER_PROFILE_OVERRIDE
+
+#define CONFIG_KEYBOARD_FACTORY_TEST
+
 /* USB-A config */
 #define GPIO_USB1_ILIM_SEL IOEX_USB_A0_CHARGE_EN_L
 #define GPIO_USB2_ILIM_SEL IOEX_USB_A1_CHARGE_EN_DB_L
@@ -31,81 +35,52 @@
 /* LED */
 #undef CONFIG_LED_ONOFF_STATES
 
-/* Motion sensing drivers */
-#define CONFIG_ACCELGYRO_LSM6DSM
-#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCEL_LIS2DWL
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-#define CONFIG_TABLET_MODE
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-
-
 /* GPIO mapping from board specific name to EC common name. */
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_EC_BATT_PRES_ODL
-#define CONFIG_SCI_GPIO			GPIO_EC_FCH_SCI_ODL
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_AP_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT_L		GPIO_EC_EDP_BL_DISABLE
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_FCH_PWR_BTN_L
-#define GPIO_PCH_RSMRST_L		GPIO_EC_FCH_RSMRST_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S5_L		GPIO_SLP_S5_L
-#define GPIO_PCH_SYS_PWROK		GPIO_EC_FCH_PWROK
-#define GPIO_PCH_WAKE_L			GPIO_EC_FCH_WAKE_L
-#define GPIO_POWER_BUTTON_L		GPIO_EC_PWR_BTN_ODL
-#define GPIO_S0_PGOOD			GPIO_S0_PWROK_OD
-#define GPIO_S5_PGOOD			GPIO_EC_PWROK_OD
-#define GPIO_SYS_RESET_L		GPIO_EC_SYS_RST_L
-#define GPIO_VOLUME_DOWN_L		GPIO_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
+#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL
+#define CONFIG_SCI_GPIO GPIO_EC_FCH_SCI_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_AP_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_EDP_BL_DISABLE
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PCH_PWRBTN_L GPIO_EC_FCH_PWR_BTN_L
+#define GPIO_PCH_RSMRST_L GPIO_EC_FCH_RSMRST_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L
+#define GPIO_PCH_SYS_PWROK GPIO_EC_FCH_PWROK
+#define GPIO_PCH_WAKE_L GPIO_EC_FCH_WAKE_L
+#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL
+#define GPIO_S0_PGOOD GPIO_S0_PWROK_OD
+#define GPIO_S5_PGOOD GPIO_EC_PWROK_OD
+#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L
+#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
 
 #ifndef __ASSEMBLER__
 
 /* This I2C moved. Temporarily detect and support the V0 HW. */
 extern int I2C_PORT_BATTERY;
 
-enum adc_channel {
-	ADC_TEMP_SENSOR_CHARGER,
-	ADC_TEMP_SENSOR_SOC,
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_TEMP_SENSOR_CHARGER, ADC_TEMP_SENSOR_SOC, ADC_CH_COUNT };
 
 enum battery_type {
 	BATTERY_SIMPLO_COS,
 	BATTERY_SIMPLO_HIGHPOWER,
 	BATTERY_SAMSUNG_SDI,
-	BATTERY_DANAPACK_ATL,
-	BATTERY_DANAPACK_COS,
+	BATTERY_DYNAPACK_ATL,
+	BATTERY_DYNAPACK_COS,
 	BATTERY_COSMX,
 	BATTERY_TYPE_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_COUNT };
 
-enum ioex_port {
-	IOEX_C0_NCT3807 = 0,
-	IOEX_C1_NCT3807,
-	IOEX_PORT_COUNT
-};
+enum ioex_port { IOEX_C0_NCT3807 = 0, IOEX_C1_NCT3807, IOEX_PORT_COUNT };
 
-#define PORT_TO_HPD(port) ((port == 0) \
-	? GPIO_USB3_C0_DP2_HPD \
-	: GPIO_DP1_HPD)
+#define PORT_TO_HPD(port) ((port == 0) ? GPIO_USB3_C0_DP2_HPD : GPIO_DP1_HPD)
 
 enum temp_sensor_id {
 	TEMP_SENSOR_CHARGER = 0,
@@ -114,22 +89,13 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum usba_port {
-	USBA_PORT_A0 = 0,
-	USBA_PORT_A1,
-	USBA_PORT_COUNT
-};
+enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT };
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 /*****************************************************************************
  * CBI EC FW Configuration
  */
-#include "cbi_ec_fw_config.h"
 
 /**
  * DALBOZ_MB_USBAC
@@ -162,6 +128,8 @@ enum ec_cfg_usb_db_type {
 	DIRINBOZ_DB_OPT1_USBC = 0,
 };
 
+#include "cbi_ec_fw_config.h"
+
 static inline bool ec_config_has_hdmi_retimer_pi3hdx1204(void)
 {
 	return 0;
diff --git a/board/dirinboz/build.mk b/board/dirinboz/build.mk
index 1c0cbc4f63..45c71f962c 100644
--- a/board/dirinboz/build.mk
+++ b/board/dirinboz/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/dirinboz/ec.tasklist b/board/dirinboz/ec.tasklist
index d9c1606eb2..779bd4fdd6 100644
--- a/board/dirinboz/ec.tasklist
+++ b/board/dirinboz/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,7 +13,6 @@
 	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
 	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, TASK_STACK_SIZE) \
 	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
 	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
 	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
 	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
diff --git a/board/dirinboz/gpio.inc b/board/dirinboz/gpio.inc
index 042ae7fe4f..ab1b83c55f 100644
--- a/board/dirinboz/gpio.inc
+++ b/board/dirinboz/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,12 +24,10 @@ GPIO_INT(ACOK_OD,		PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	extpower_inter
 GPIO_INT(EC_WP_L,		PIN(5, 0), GPIO_INT_BOTH,			switch_interrupt)
 GPIO_INT(VOLDN_BTN_ODL,		PIN(A, 6), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
 GPIO_INT(VOLUP_BTN_ODL,		PIN(9, 5), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-GPIO_INT(6AXIS_INT_L,		PIN(A, 0), GPIO_INT_FALLING | GPIO_PULL_UP,	lsm6dsm_interrupt)
 
 /* GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an interrupt handler. */
 GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH)
 
-GPIO(3AXIS_INT_L,		PIN(9, 6), GPIO_INPUT | GPIO_PULL_DOWN)		/* 3 Axis Accel */
 GPIO(CCD_MODE_ODL,		PIN(C, 6), GPIO_INPUT)				/* Case Closed Debug Mode */
 GPIO(PROCHOT_ODL,		PIN(D, 5), GPIO_ODR_HIGH)			/* PROCHOT to SOC */
 GPIO(EC_BATT_PRES_ODL,		PIN(4, 1), GPIO_INPUT)				/* Battery Present */
diff --git a/board/dirinboz/led.c b/board/dirinboz/led.c
index 624277d209..ff9bcd986b 100644
--- a/board/dirinboz/led.c
+++ b/board/dirinboz/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,17 +7,12 @@
 #include "charge_manager.h"
 #include "charge_state.h"
 #include "chipset.h"
+#include "cros_board_info.h"
 #include "ec_commands.h"
 #include "gpio.h"
+#include "hooks.h"
 #include "host_command.h"
 #include "led_common.h"
-#include "hooks.h"
-
-#define BAT_LED_ON 0
-#define BAT_LED_OFF 1
-
-#define POWER_LED_ON 0
-#define POWER_LED_OFF 1
 
 #define LED_TICKS_PER_CYCLE 10
 #define LED_ON_TICKS 5
@@ -33,35 +28,43 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
-enum led_port {
-	LEFT_PORT = 0,
-	RIGHT_PORT
-};
+enum led_port { LEFT_PORT = 0, RIGHT_PORT };
 
 static void led_set_color_battery(int port, enum led_color color)
 {
-	enum gpio_signal amber_led, white_led;
+	int amber_led, white_led;
+	uint32_t board_ver = 0;
+	int led_batt_on_lvl, led_batt_off_lvl;
 
+	cbi_get_board_version(&board_ver);
 	amber_led = (port == LEFT_PORT ? GPIO_LED_CHRG_L :
-				 IOEX_C1_CHARGER_LED_AMBER_DB);
+					 IOEX_C1_CHARGER_LED_AMBER_DB);
 	white_led = (port == LEFT_PORT ? GPIO_LED_FULL_L :
-				 IOEX_C1_CHARGER_LED_WHITE_DB);
+					 IOEX_C1_CHARGER_LED_WHITE_DB);
+
+	if ((board_ver >= 3) && (port == RIGHT_PORT)) {
+		led_batt_on_lvl = 1;
+		led_batt_off_lvl = 0;
+	} else {
+		led_batt_on_lvl = 0;
+		led_batt_off_lvl = 1;
+	}
 
 	switch (color) {
 	case LED_WHITE:
-		gpio_or_ioex_set_level(white_led, BAT_LED_ON);
-		gpio_or_ioex_set_level(amber_led, BAT_LED_OFF);
+		gpio_or_ioex_set_level(white_led, led_batt_on_lvl);
+		gpio_or_ioex_set_level(amber_led, led_batt_off_lvl);
 		break;
 	case LED_AMBER:
-		gpio_or_ioex_set_level(white_led, BAT_LED_OFF);
-		gpio_or_ioex_set_level(amber_led, BAT_LED_ON);
+		gpio_or_ioex_set_level(white_led, led_batt_off_lvl);
+		gpio_or_ioex_set_level(amber_led, led_batt_on_lvl);
 		break;
 	case LED_OFF:
-		gpio_or_ioex_set_level(white_led, BAT_LED_OFF);
-		gpio_or_ioex_set_level(amber_led, BAT_LED_OFF);
+		gpio_or_ioex_set_level(white_led, led_batt_off_lvl);
+		gpio_or_ioex_set_level(amber_led, led_batt_off_lvl);
 		break;
 	default:
 		break;
@@ -120,17 +123,16 @@ static void set_active_port_color(enum led_color color)
 
 	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
 		led_set_color_battery(RIGHT_PORT,
-				(port == RIGHT_PORT) ? color : LED_OFF);
+				      (port == RIGHT_PORT) ? color : LED_OFF);
 	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
 		led_set_color_battery(LEFT_PORT,
-				(port == LEFT_PORT) ? color : LED_OFF);
+				      (port == LEFT_PORT) ? color : LED_OFF);
 }
 
 static void led_set_battery(void)
 {
 	static int battery_ticks;
 	static int power_ticks;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
@@ -139,32 +141,33 @@ static void led_set_battery(void)
 	 * design, blinking both two side battery white LEDs to indicate
 	 * system suspend with non-charging state.
 	 */
-	if (chipset_in_state(CHIPSET_STATE_SUSPEND |
-				 CHIPSET_STATE_STANDBY) &&
-		charge_get_state() != PWR_STATE_CHARGE) {
-
+	if (chipset_in_state(CHIPSET_STATE_SUSPEND | CHIPSET_STATE_STANDBY) &&
+	    led_pwr_get_state() != LED_PWRS_CHARGE) {
 		power_ticks++;
 
-		led_set_color_battery(RIGHT_PORT, power_ticks & 0x4 ?
-					  LED_WHITE : LED_OFF);
-		led_set_color_battery(LEFT_PORT, power_ticks & 0x4 ?
-					  LED_WHITE : LED_OFF);
+		led_set_color_battery(RIGHT_PORT,
+				      power_ticks & 0x4 ? LED_WHITE : LED_OFF);
+		led_set_color_battery(LEFT_PORT,
+				      power_ticks & 0x4 ? LED_WHITE : LED_OFF);
 		return;
 	}
 
 	power_ticks = 0;
 
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
 		/* Always indicate when charging, even in suspend. */
 		set_active_port_color(LED_AMBER);
 		break;
-	case PWR_STATE_DISCHARGE:
+	case LED_PWRS_DISCHARGE:
 		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
 			if (charge_get_percent() < 10)
-				led_set_color_battery(RIGHT_PORT,
-					(battery_ticks % LED_TICKS_PER_CYCLE
-					 < LED_ON_TICKS) ? LED_WHITE : LED_OFF);
+				led_set_color_battery(
+					RIGHT_PORT,
+					(battery_ticks % LED_TICKS_PER_CYCLE <
+					 LED_ON_TICKS) ?
+						LED_WHITE :
+						LED_OFF);
 			else
 				led_set_color_battery(RIGHT_PORT, LED_OFF);
 		}
@@ -172,20 +175,21 @@ static void led_set_battery(void)
 		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
 			led_set_color_battery(LEFT_PORT, LED_OFF);
 		break;
-	case PWR_STATE_ERROR:
-		set_active_port_color((battery_ticks & 0x2) ?
-				LED_WHITE : LED_OFF);
+	case LED_PWRS_ERROR:
+		set_active_port_color((battery_ticks & 0x2) ? LED_WHITE :
+							      LED_OFF);
 		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
+	case LED_PWRS_CHARGE_NEAR_FULL:
 		set_active_port_color(LED_WHITE);
 		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			set_active_port_color((battery_ticks %
-				LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-				LED_AMBER : LED_OFF);
-		else
-			set_active_port_color(LED_WHITE);
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		set_active_port_color(LED_WHITE);
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		set_active_port_color(
+			(battery_ticks % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
+				LED_AMBER :
+				LED_OFF);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
diff --git a/board/dirinboz/vif_override.xml b/board/dirinboz/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/dirinboz/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/discovery-stm32f072/board.c b/board/discovery-stm32f072/board.c
index b1b9346cd3..1ba70c99d9 100644
--- a/board/discovery-stm32f072/board.c
+++ b/board/discovery-stm32f072/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,11 +13,11 @@
 #include "spi.h"
 #include "task.h"
 #include "usart-stm32f0.h"
-#include "usart_tx_dma.h"
 #include "usart_rx_dma.h"
+#include "usart_tx_dma.h"
+#include "usb-stream.h"
 #include "usb_gpio.h"
 #include "usb_spi.h"
-#include "usb-stream.h"
 #include "util.h"
 
 /******************************************************************************
@@ -25,34 +25,26 @@
  */
 void button_event(enum gpio_signal signal);
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 static enum gpio_signal const usb_gpio_list[] = {
-	GPIO_USER_BUTTON,
-	GPIO_LED_U,
-	GPIO_LED_D,
-	GPIO_LED_L,
-	GPIO_LED_R,
+	GPIO_USER_BUTTON, GPIO_LED_U, GPIO_LED_D, GPIO_LED_L, GPIO_LED_R,
 };
 
 /*
  * This instantiates struct usb_gpio_config const usb_gpio, plus several other
  * variables, all named something beginning with usb_gpio_
  */
-USB_GPIO_CONFIG(usb_gpio,
-		usb_gpio_list,
-		USB_IFACE_GPIO,
-		USB_EP_GPIO);
+USB_GPIO_CONFIG(usb_gpio, usb_gpio_list, USB_IFACE_GPIO, USB_EP_GPIO);
 
 /******************************************************************************
  * Setup USART1 as a loopback device, it just echo's back anything sent to it.
  */
 static struct usart_config const loopback_usart;
 
-static struct queue const loopback_queue =
-	QUEUE_DIRECT(64, uint8_t,
-		     loopback_usart.producer,
-		     loopback_usart.consumer);
+static struct queue const loopback_queue = QUEUE_DIRECT(
+	64, uint8_t, loopback_usart.producer, loopback_usart.consumer);
 
 static struct usart_rx_dma const loopback_rx_dma =
 	USART_RX_DMA(STM32_DMAC_CH3, 8);
@@ -60,14 +52,9 @@ static struct usart_rx_dma const loopback_rx_dma =
 static struct usart_tx_dma const loopback_tx_dma =
 	USART_TX_DMA(STM32_DMAC_CH2, 16);
 
-static struct usart_config const loopback_usart =
-	USART_CONFIG(usart1_hw,
-		     loopback_rx_dma.usart_rx,
-		     loopback_tx_dma.usart_tx,
-		     115200,
-		     0,
-		     loopback_queue,
-		     loopback_queue);
+static struct usart_config const loopback_usart = USART_CONFIG(
+	usart1_hw, loopback_rx_dma.usart_rx, loopback_tx_dma.usart_tx, 115200,
+	0, loopback_queue, loopback_queue);
 
 /******************************************************************************
  * Forward USART4 as a simple USB serial interface.
@@ -75,36 +62,24 @@ static struct usart_config const loopback_usart =
 static struct usart_config const forward_usart;
 struct usb_stream_config const forward_usb;
 
-static struct queue const usart_to_usb = QUEUE_DIRECT(64, uint8_t,
-						      forward_usart.producer,
-						      forward_usb.consumer);
-static struct queue const usb_to_usart = QUEUE_DIRECT(64, uint8_t,
-						      forward_usb.producer,
-						      forward_usart.consumer);
+static struct queue const usart_to_usb =
+	QUEUE_DIRECT(64, uint8_t, forward_usart.producer, forward_usb.consumer);
+static struct queue const usb_to_usart =
+	QUEUE_DIRECT(64, uint8_t, forward_usb.producer, forward_usart.consumer);
 
 static struct usart_tx_dma const forward_tx_dma =
 	USART_TX_DMA(STM32_DMAC_CH7, 16);
 
 static struct usart_config const forward_usart =
-	USART_CONFIG(usart4_hw,
-		     usart_rx_interrupt,
-		     forward_tx_dma.usart_tx,
-		     115200,
-		     0,
-		     usart_to_usb,
-		     usb_to_usart);
-
-#define USB_STREAM_RX_SIZE	16
-#define USB_STREAM_TX_SIZE	16
-
-USB_STREAM_CONFIG(forward_usb,
-		  USB_IFACE_STREAM,
-		  USB_STR_STREAM_NAME,
-		  USB_EP_STREAM,
-		  USB_STREAM_RX_SIZE,
-		  USB_STREAM_TX_SIZE,
-		  usb_to_usart,
-		  usart_to_usb)
+	USART_CONFIG(usart4_hw, usart_rx_interrupt, forward_tx_dma.usart_tx,
+		     115200, 0, usart_to_usb, usb_to_usart);
+
+#define USB_STREAM_RX_SIZE 16
+#define USB_STREAM_TX_SIZE 16
+
+USB_STREAM_CONFIG(forward_usb, USB_IFACE_STREAM, USB_STR_STREAM_NAME,
+		  USB_EP_STREAM, USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE,
+		  usb_to_usart, usart_to_usb)
 
 /******************************************************************************
  * Handle button presses by cycling the LEDs on the board.  Also run a tick
@@ -135,17 +110,17 @@ DECLARE_HOOK(HOOK_TICK, usb_gpio_tick, HOOK_PRIO_DEFAULT);
  * Define the strings used in our USB descriptors.
  */
 const void *const usb_strings[] = {
-	[USB_STR_DESC]         = usb_string_desc,
-	[USB_STR_VENDOR]       = USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]      = USB_STRING_DESC("discovery-stm32f072"),
-	[USB_STR_VERSION]      = USB_STRING_DESC(CROS_EC_VERSION32),
-	[USB_STR_STREAM_NAME]  = USB_STRING_DESC("Forward"),
+	[USB_STR_DESC] = usb_string_desc,
+	[USB_STR_VENDOR] = USB_STRING_DESC("Google LLC"),
+	[USB_STR_PRODUCT] = USB_STRING_DESC("discovery-stm32f072"),
+	[USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32),
+	[USB_STR_STREAM_NAME] = USB_STRING_DESC("Forward"),
 	[USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Shell"),
+	[USB_STR_SPI_NAME] = USB_STRING_DESC("SPI"),
 };
 
 BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
 
-
 /******************************************************************************
  * Support SPI bridging over USB, this requires usb_spi_board_enable and
  * usb_spi_board_disable to be defined to enable and disable the SPI bridge.
@@ -153,11 +128,11 @@ BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
 
 /* SPI devices */
 const struct spi_device_t spi_devices[] = {
-	{ CONFIG_SPI_FLASH_PORT, 0, GPIO_SPI_CS},
+	{ CONFIG_SPI_FLASH_PORT, 0, GPIO_SPI_CS, USB_SPI_ENABLED },
 };
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
-void usb_spi_board_enable(struct usb_spi_config const *config)
+void usb_spi_board_enable(void)
 {
 	/* Remap SPI2 to DMA channels 6 and 7 */
 	STM32_SYSCFG_CFGR1 |= BIT(24);
@@ -175,12 +150,12 @@ void usb_spi_board_enable(struct usb_spi_config const *config)
 	STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2;
 	STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
 
-	spi_enable(CONFIG_SPI_FLASH_PORT, 1);
+	spi_enable(&spi_devices[0], 1);
 }
 
-void usb_spi_board_disable(struct usb_spi_config const *config)
+void usb_spi_board_disable(void)
 {
-	spi_enable(CONFIG_SPI_FLASH_PORT, 0);
+	spi_enable(&spi_devices[0], 0);
 
 	/* Disable clocks to SPI2 module */
 	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
@@ -189,8 +164,6 @@ void usb_spi_board_disable(struct usb_spi_config const *config)
 	gpio_config_module(MODULE_SPI_FLASH, 0);
 }
 
-USB_SPI_CONFIG(usb_spi, USB_IFACE_SPI, USB_EP_SPI, 0);
-
 /******************************************************************************
  * Initialize board.
  */
@@ -204,6 +177,6 @@ static void board_init(void)
 	usart_init(&loopback_usart);
 	usart_init(&forward_usart);
 
-	usb_spi_enable(&usb_spi, 1);
+	usb_spi_enable(1);
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/discovery-stm32f072/board.h b/board/discovery-stm32f072/board.h
index ba5894db56..b112f14f9f 100644
--- a/board/discovery-stm32f072/board.h
+++ b/board/discovery-stm32f072/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,7 +23,6 @@
 #define CONFIG_UART_CONSOLE 2
 
 /* Optional features */
-#define CONFIG_STM_HWTIMER32
 #define CONFIG_HW_CRC
 
 /* USB Configuration */
@@ -32,27 +31,26 @@
 #define CONFIG_USB_CONSOLE
 
 /* USB interface indexes (use define rather than enum to expand them) */
-#define USB_IFACE_STREAM  0
-#define USB_IFACE_GPIO    1
-#define USB_IFACE_SPI     2
+#define USB_IFACE_STREAM 0
+#define USB_IFACE_GPIO 1
+#define USB_IFACE_SPI 2
 #define USB_IFACE_CONSOLE 3
-#define USB_IFACE_COUNT   4
+#define USB_IFACE_COUNT 4
 
 /* USB endpoint indexes (use define rather than enum to expand them) */
 #define USB_EP_CONTROL 0
-#define USB_EP_STREAM  1
-#define USB_EP_GPIO    2
-#define USB_EP_SPI     3
+#define USB_EP_STREAM 1
+#define USB_EP_GPIO 2
+#define USB_EP_SPI 3
 #define USB_EP_CONSOLE 4
-#define USB_EP_COUNT   5
+#define USB_EP_COUNT 5
 
 /* Enable control of GPIOs over USB */
 #define CONFIG_USB_GPIO
 
 /* Enable control of SPI over USB */
-#define CONFIG_SPI_MASTER
-#define CONFIG_SPI_FLASH_PORT    0  /* First SPI master port */
-
+#define CONFIG_SPI_CONTROLLER
+#define CONFIG_SPI_FLASH_PORT 0 /* First SPI controller port */
 
 #define CONFIG_USB_SPI
 
@@ -80,6 +78,7 @@ enum usb_strings {
 	USB_STR_VERSION,
 	USB_STR_STREAM_NAME,
 	USB_STR_CONSOLE_NAME,
+	USB_STR_SPI_NAME,
 
 	USB_STR_COUNT
 };
diff --git a/board/discovery-stm32f072/build.mk b/board/discovery-stm32f072/build.mk
index c1892335ed..3e87efe412 100644
--- a/board/discovery-stm32f072/build.mk
+++ b/board/discovery-stm32f072/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
+# Copyright 2014 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -11,3 +11,6 @@ CHIP_FAMILY:=stm32f0
 CHIP_VARIANT:=stm32f07x
 
 board-y=board.o
+
+test-list-y=\
+	panic \
diff --git a/board/discovery-stm32f072/ec.tasklist b/board/discovery-stm32f072/ec.tasklist
index cc4c2ad42d..2bd7e2f5ce 100644
--- a/board/discovery-stm32f072/ec.tasklist
+++ b/board/discovery-stm32f072/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/discovery-stm32f072/gpio.inc b/board/discovery-stm32f072/gpio.inc
index 65bdd0179b..25b5f1b0e0 100644
--- a/board/discovery-stm32f072/gpio.inc
+++ b/board/discovery-stm32f072/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
+ * Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/discovery-stm32f072/openocd-flash.cfg b/board/discovery-stm32f072/openocd-flash.cfg
index ec32416934..05a697acf8 100644
--- a/board/discovery-stm32f072/openocd-flash.cfg
+++ b/board/discovery-stm32f072/openocd-flash.cfg
@@ -1,4 +1,4 @@
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
+# Copyright 2014 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/board/discovery/board.c b/board/discovery/board.c
index 0d4cde2e7c..7892f1a5e0 100644
--- a/board/discovery/board.c
+++ b/board/discovery/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,6 +17,7 @@
 
 void button_event(enum gpio_signal signal);
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 void button_event(enum gpio_signal signal)
@@ -39,10 +40,8 @@ DECLARE_HOOK(HOOK_TICK, usb_gpio_tick, HOOK_PRIO_DEFAULT);
  */
 static struct usart_config const loopback_usart;
 
-static struct queue const loopback_queue =
-	QUEUE_DIRECT(64, uint8_t,
-		     loopback_usart.producer,
-		     loopback_usart.consumer);
+static struct queue const loopback_queue = QUEUE_DIRECT(
+	64, uint8_t, loopback_usart.producer, loopback_usart.consumer);
 
 static struct usart_rx_dma const loopback_rx_dma =
 	USART_RX_DMA(STM32_DMAC_CH6, 32);
@@ -50,14 +49,9 @@ static struct usart_rx_dma const loopback_rx_dma =
 static struct usart_tx_dma const loopback_tx_dma =
 	USART_TX_DMA(STM32_DMAC_CH7, 16);
 
-static struct usart_config const loopback_usart =
-	USART_CONFIG(usart2_hw,
-		     loopback_rx_dma.usart_rx,
-		     loopback_tx_dma.usart_tx,
-		     115200,
-		     0,
-		     loopback_queue,
-		     loopback_queue);
+static struct usart_config const loopback_usart = USART_CONFIG(
+	usart2_hw, loopback_rx_dma.usart_rx, loopback_tx_dma.usart_tx, 115200,
+	0, loopback_queue, loopback_queue);
 
 /******************************************************************************
  * Initialize board.
diff --git a/board/discovery/board.h b/board/discovery/board.h
index ddd2461a56..a722408e81 100644
--- a/board/discovery/board.h
+++ b/board/discovery/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,9 +25,14 @@
 
 #ifndef __ASSEMBLER__
 
-/* Timer selection */
-#define TIM_CLOCK_MSB 3
-#define TIM_CLOCK_LSB 4
+/* Timer selection
+ *
+ * "discovery" is an STM32L152RC, which is a "Category 3" product that
+ * has the 32-bit timer TIM5. See Section 17 "General-purpose Timers" and
+ * "Table 3. STM32L15xxx product categories":
+ * https://www.st.com/resource/en/reference_manual/cd00240193-stm32l100xx-stm32l151xx-stm32l152xx-and-stm32l162xx-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf
+ */
+#define TIM_CLOCK32 5
 
 #include "gpio_signal.h"
 
diff --git a/board/discovery/build.mk b/board/discovery/build.mk
index 42f9f9a0fc..e07d8af33d 100644
--- a/board/discovery/build.mk
+++ b/board/discovery/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
+# Copyright 2013 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/discovery/ec.tasklist b/board/discovery/ec.tasklist
index 3822ab3779..e58390c01d 100644
--- a/board/discovery/ec.tasklist
+++ b/board/discovery/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/discovery/gpio.inc b/board/discovery/gpio.inc
index 821f38ca46..da2742ff7a 100644
--- a/board/discovery/gpio.inc
+++ b/board/discovery/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
+ * Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/discovery/openocd-flash.cfg b/board/discovery/openocd-flash.cfg
index 6426ad5473..f87c191576 100644
--- a/board/discovery/openocd-flash.cfg
+++ b/board/discovery/openocd-flash.cfg
@@ -1,4 +1,4 @@
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/board/dojo/battery.c b/board/dojo/battery.c
new file mode 100644
index 0000000000..a766ea3e59
--- /dev/null
+++ b/board/dojo/battery.c
@@ -0,0 +1,262 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "battery_fuel_gauge.h"
+#include "battery_smart.h"
+#include "charge_state.h"
+#include "console.h"
+#include "gpio.h"
+#include "temp_sensor.h"
+#include "util.h"
+
+const struct board_batt_params board_battery_info[] = {
+	/* DynaPack CosMX Battery Information */
+	[BATTERY_DYNAPACK_COS] = {
+		.fuel_gauge = {
+			.manuf_name = "333-2C-DA-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,	/* mV */
+			.voltage_normal = 7700,
+			.voltage_min = 6000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+			.vendor_param_start = 0x70,
+		},
+	},
+
+	/* DynaPack ATL Battery Information */
+	[BATTERY_DYNAPACK_ATL] = {
+		.fuel_gauge = {
+			.manuf_name = "333-27-DA-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,	/* mV */
+			.voltage_normal = 7700,
+			.voltage_min = 6000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+			.vendor_param_start = 0x70,
+		},
+	},
+
+	/* Simplo CosMX Battery Information */
+	[BATTERY_SIMPLO_COS] = {
+		.fuel_gauge = {
+			.manuf_name = "333-1C-DA-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,	/* mV */
+			.voltage_normal = 7700,
+			.voltage_min = 6000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+			.vendor_param_start = 0x70,
+		},
+	},
+
+	/* Simplo HIGHPOWER Battery Information */
+	[BATTERY_SIMPLO_HIGHPOWER] = {
+		.fuel_gauge = {
+			.manuf_name = "333-1D-DA-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,	/* mV */
+			.voltage_normal = 7700,
+			.voltage_min = 6000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+			.vendor_param_start = 0x70,
+		},
+	},
+
+	/* CosMX B00C4473A9D0002 Battery Information */
+	[BATTERY_COS] = {
+		.fuel_gauge = {
+			.manuf_name = "333-AC-DA-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,	/* mV */
+			.voltage_normal = 7700,
+			.voltage_min = 6000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+			.vendor_param_start = 0x70,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_DYNAPACK_COS;
+
+int charger_profile_override(struct charge_state_data *curr)
+{
+	int chg_temp;
+	int prev_chg_lvl;
+	static int chg_lvl;
+
+	if (chipset_in_state(CHIPSET_STATE_ON)) {
+		temp_sensor_read(TEMP_SENSOR_CHARGER, &chg_temp);
+		chg_temp = K_TO_C(chg_temp);
+
+		prev_chg_lvl = chg_lvl;
+		if (chg_temp <= temp_chg_table[chg_lvl].lo_thre && chg_lvl > 0)
+			chg_lvl--;
+		else if (chg_temp >= temp_chg_table[chg_lvl].hi_thre &&
+			 chg_lvl < CHG_LEVEL_COUNT - 1)
+			chg_lvl++;
+
+		curr->requested_current = MIN(curr->requested_current,
+					      temp_chg_table[chg_lvl].chg_curr);
+
+		if (chg_lvl != prev_chg_lvl)
+			ccprints("Override chg curr to %dmA by chg LEVEL_%d",
+				 curr->requested_current, chg_lvl);
+	}
+
+	return 0;
+}
+
+enum ec_status charger_profile_override_get_param(uint32_t param,
+						  uint32_t *value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+enum ec_status charger_profile_override_set_param(uint32_t param,
+						  uint32_t value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+enum battery_present batt_pres_prev = BP_NOT_SURE;
+
+/*
+ * Physical detection of battery.
+ */
+static enum battery_present battery_check_present_status(void)
+{
+	enum battery_present batt_pres = BP_NOT_SURE;
+
+	/* Get the physical hardware status */
+	batt_pres = battery_hw_present();
+
+	/*
+	 * If the battery is not physically connected, then no need to perform
+	 * any more checks.
+	 */
+	if (batt_pres == BP_NO)
+		return batt_pres;
+
+	/*
+	 * If the battery is present now and was present last time we checked,
+	 * return early.
+	 */
+	if (batt_pres == batt_pres_prev)
+		return batt_pres;
+
+	/*
+	 * Check battery disconnect status. If we are unable to read battery
+	 * disconnect status, then return BP_NOT_SURE. Battery could be in ship
+	 * mode and might require pre-charge current to wake it up. BP_NO is not
+	 * returned here because charger state machine will not provide
+	 * pre-charge current assuming that battery is not present.
+	 */
+	if (battery_get_disconnect_state() == BATTERY_DISCONNECT_ERROR)
+		return BP_NOT_SURE;
+
+	/* Ensure the battery is not in cutoff state */
+	if (battery_is_cut_off() != BATTERY_CUTOFF_STATE_NORMAL)
+		return BP_NO;
+
+	return batt_pres;
+}
+
+enum battery_present battery_is_present(void)
+{
+	batt_pres_prev = battery_check_present_status();
+	return batt_pres_prev;
+}
+
+enum battery_present battery_hw_present(void)
+{
+	return gpio_get_level(GPIO_EC_BATT_PRES_ODL) ? BP_NO : BP_YES;
+}
diff --git a/board/dojo/board.c b/board/dojo/board.c
new file mode 100644
index 0000000000..28788d4641
--- /dev/null
+++ b/board/dojo/board.c
@@ -0,0 +1,531 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* Dojo board configuration */
+
+#include "cbi_fw_config.h"
+#include "cbi_ssfc.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "common.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "driver/accel_kionix.h"
+#include "driver/accel_kx022.h"
+#include "driver/accelgyro_bmi260_public.h"
+#include "driver/accelgyro_bmi_common_public.h"
+#include "driver/accelgyro_icm42607.h"
+#include "driver/accelgyro_icm426xx.h"
+#include "driver/accelgyro_icm_common.h"
+#include "driver/retimer/ps8802.h"
+#include "driver/usb_mux/anx3443.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "keyboard_scan.h"
+#include "motion_sense.h"
+#include "power.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "system.h"
+#include "usb_mux.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+uint32_t board_version;
+enum ec_ssfc_base_sensor base_sensor;
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/* Increase from 50 us, because KSO_02 passes through the H1. */
+	.output_settle_us = 80,
+	.debounce_down_us = 9 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x1c, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
+	},
+};
+
+/* Support keyboard factory test */
+#ifdef CONFIG_KEYBOARD_FACTORY_TEST
+/*
+ * Map keyboard connector pins to EC GPIO pins for factory test.
+ * Pins mapped to {-1, -1} are skipped.
+ * The connector has 30 pins total, and there is no pin 0.
+ */
+const int keyboard_factory_scan_pins[][2] = {
+	{ -1, -1 },	   { GPIO_KSO_H, 4 }, { GPIO_KSO_H, 0 },
+	{ GPIO_KSO_H, 1 }, { GPIO_KSO_H, 3 }, { GPIO_KSO_H, 2 },
+	{ -1, -1 },	   { -1, -1 },	      { GPIO_KSO_L, 5 },
+	{ GPIO_KSO_L, 6 }, { -1, -1 },	      { GPIO_KSO_L, 3 },
+	{ GPIO_KSO_L, 2 }, { GPIO_KSI, 0 },   { GPIO_KSO_L, 1 },
+	{ GPIO_KSO_L, 4 }, { GPIO_KSI, 3 },   { GPIO_KSI, 2 },
+	{ GPIO_KSO_L, 0 }, { GPIO_KSI, 5 },   { GPIO_KSI, 4 },
+	{ GPIO_KSO_L, 7 }, { GPIO_KSI, 6 },   { GPIO_KSI, 7 },
+	{ GPIO_KSI, 1 },   { -1, -1 },	      { GPIO_KSO_H, 5 },
+	{ -1, -1 },	   { GPIO_KSO_H, 6 }, { -1, -1 },
+	{ -1, -1 },
+};
+
+const int keyboard_factory_scan_pins_used =
+	ARRAY_SIZE(keyboard_factory_scan_pins);
+#endif
+
+/* Vol-up key matrix at T13 */
+const struct vol_up_key vol_up_key_matrix_T13 = {
+	.row = 3,
+	.col = 5,
+};
+
+/* Vol-up key matrix at T12 */
+const struct vol_up_key vol_up_key_matrix_T12 = {
+	.row = 1,
+	.col = 5,
+};
+
+/* Vol-up key update */
+static void board_update_vol_up_key(void)
+{
+	if (board_version >= 2) {
+		if (get_cbi_fw_config_kblayout() == KB_BL_TOGGLE_KEY_PRESENT) {
+			/*
+			 * Set vol up key to T13 for KB_BL_TOGGLE_KEY_PRESENT
+			 * and board_version >= 2
+			 */
+			set_vol_up_key(vol_up_key_matrix_T13.row,
+				       vol_up_key_matrix_T13.col);
+		} else {
+			/*
+			 * Set vol up key to T12 for KB_BL_TOGGLE_KEY_ABSENT
+			 * and board_version >= 2
+			 */
+			set_vol_up_key(vol_up_key_matrix_T12.row,
+				       vol_up_key_matrix_T12.col);
+		}
+	} else {
+		/* Set vol up key to T13 for board_version < 2 */
+		set_vol_up_key(vol_up_key_matrix_T13.row,
+			       vol_up_key_matrix_T13.col);
+	}
+}
+
+/* Temperature charging table */
+const struct temp_chg_struct temp_chg_table[] = {
+	[LEVEL_0] = {
+		.lo_thre = 0,
+		.hi_thre = 68,
+		.chg_curr = 3000,
+	},
+	[LEVEL_1] = {
+		.lo_thre = 63,
+		.hi_thre = 74,
+		.chg_curr = 1500,
+	},
+	[LEVEL_2] = {
+		.lo_thre = 69,
+		.hi_thre = 100,
+		.chg_curr = 500,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_chg_table) == CHG_LEVEL_COUNT);
+
+/* Sensor */
+static struct mutex g_base_mutex;
+static struct mutex g_lid_mutex;
+
+static struct icm_drv_data_t g_icm426xx_data;
+static struct icm_drv_data_t g_icm42607_data;
+static struct bmi_drv_data_t g_bmi260_data;
+static struct kionix_accel_data g_kx022_data;
+
+/* Matrix to rotate accelrator into standard reference frame */
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+					      { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
+
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
+
+static const mat33_fp_t icm42607_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+						  { 0, FLOAT_TO_FP(-1), 0 },
+						  { 0, 0, FLOAT_TO_FP(1) } };
+
+static const mat33_fp_t icm426xx_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+						  { 0, FLOAT_TO_FP(-1), 0 },
+						  { 0, 0, FLOAT_TO_FP(1) } };
+
+struct motion_sensor_t motion_sensors[] = {
+	/*
+	 * Note: bmi160: supports accelerometer and gyro sensor
+	 * Requirement: accelerometer sensor must init before gyro sensor
+	 * DO NOT change the order of the following table.
+	 */
+	[BASE_ACCEL] = {
+		.name = "Base Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMI260,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &bmi260_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = &g_bmi260_data,
+		.port = I2C_PORT_ACCEL,
+		.i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = BMI_ACCEL_MIN_FREQ,
+		.max_frequency = BMI_ACCEL_MAX_FREQ,
+		.default_range = 4, /* g */
+		.config = {
+			/* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+			/* Sensor on in S3 */
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+		},
+	},
+	[BASE_GYRO] = {
+		.name = "Base Gyro",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMI260,
+		.type = MOTIONSENSE_TYPE_GYRO,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &bmi260_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = &g_bmi260_data,
+		.port = I2C_PORT_ACCEL,
+		.i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
+		.default_range = 1000, /* dps */
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = BMI_GYRO_MIN_FREQ,
+		.max_frequency = BMI_GYRO_MAX_FREQ,
+	},
+	[LID_ACCEL] = {
+		.name = "Lid Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_KX022,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &kionix_accel_drv,
+		.mutex = &g_lid_mutex,
+		.drv_data = &g_kx022_data,
+		.port = I2C_PORT_ACCEL,
+		.i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
+		.rot_standard_ref = &lid_standard_ref,
+		.default_range = 2, /* g, enough for laptop. */
+		.min_frequency = KX022_ACCEL_MIN_FREQ,
+		.max_frequency = KX022_ACCEL_MAX_FREQ,
+		.config = {
+			 /* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100,
+			},
+			/* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+		},
+	},
+};
+const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+struct motion_sensor_t icm42607_base_accel = {
+	.name = "Base Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM42607,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm42607_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm42607_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
+	.default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
+	.rot_standard_ref = &icm42607_standard_ref,
+	.min_frequency = ICM42607_ACCEL_MIN_FREQ,
+	.max_frequency = ICM42607_ACCEL_MAX_FREQ,
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	},
+};
+
+struct motion_sensor_t icm42607_base_gyro = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM42607,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm42607_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm42607_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &icm42607_standard_ref,
+	.min_frequency = ICM42607_GYRO_MIN_FREQ,
+	.max_frequency = ICM42607_GYRO_MAX_FREQ,
+};
+
+struct motion_sensor_t icm426xx_base_accel = {
+	.name = "Base Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs. */
+	.rot_standard_ref = &icm426xx_standard_ref,
+	.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
+	.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	},
+};
+
+struct motion_sensor_t icm426xx_base_gyro = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &icm426xx_standard_ref,
+	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
+	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
+};
+
+static void board_update_motion_sensor_config(void)
+{
+	if (board_version <= 1 || base_sensor == SSFC_SENSOR_ICM426XX) {
+		motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
+		motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
+		ccprints("BASE Accelgyro is ICM426XX");
+	} else if (base_sensor == SSFC_SENSOR_ICM42607) {
+		motion_sensors[BASE_ACCEL] = icm42607_base_accel;
+		motion_sensors[BASE_GYRO] = icm42607_base_gyro;
+		ccprints("BASE Accelgyro is ICM42607");
+	} else {
+		ccprints("BASE Accelgyro is BMI260");
+	}
+}
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	if (board_version <= 1 || base_sensor == SSFC_SENSOR_ICM426XX)
+		icm426xx_interrupt(signal);
+	else if (base_sensor == SSFC_SENSOR_ICM42607)
+		icm42607_interrupt(signal);
+	else
+		bmi260_interrupt(signal);
+}
+
+/* PWM */
+
+/*
+ * PWM channels. Must be in the exactly same order as in enum pwm_channel.
+ * There total three 16 bits clock prescaler registers for all pwm channels,
+ * so use the same frequency and prescaler register setting is required if
+ * number of pwm channel greater than three.
+ */
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_LED_C1_WHITE] = {
+		.channel = 0,
+		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
+		.freq_hz = 324, /* maximum supported frequency */
+		.pcfsr_sel = PWM_PRESCALER_C4,
+	},
+	[PWM_CH_LED_C1_AMBER] = {
+		.channel = 1,
+		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
+		.freq_hz = 324, /* maximum supported frequency */
+		.pcfsr_sel = PWM_PRESCALER_C4,
+	},
+	[PWM_CH_LED_PWR] = {
+		.channel = 2,
+		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
+		.freq_hz = 324, /* maximum supported frequency */
+		.pcfsr_sel = PWM_PRESCALER_C4,
+	},
+	[PWM_CH_KBLIGHT] = {
+		.channel = 3,
+		.freq_hz = 2400,
+		.pcfsr_sel = PWM_PRESCALER_C6,
+	},
+	[PWM_CH_LED_C0_WHITE] = {
+		.channel = 6,
+		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
+		.freq_hz = 324, /* maximum supported frequency */
+		.pcfsr_sel = PWM_PRESCALER_C4,
+	},
+	[PWM_CH_LED_C0_AMBER] = {
+		.channel = 7,
+		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
+		.freq_hz = 324, /* maximum supported frequency */
+		.pcfsr_sel = PWM_PRESCALER_C4,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+/* USB Mux */
+
+static int board_ps8762_mux_set(const struct usb_mux *me, mux_state_t mux_state)
+{
+	/* Make sure the PS8802 is awake */
+	RETURN_ERROR(ps8802_i2c_wake(me));
+
+	/* USB specific config */
+	if (mux_state & USB_PD_MUX_USB_ENABLED) {
+		/* Boost the USB gain */
+		RETURN_ERROR(ps8802_i2c_field_update16(
+			me, PS8802_REG_PAGE2, PS8802_REG2_USB_SSEQ_LEVEL,
+			PS8802_USBEQ_LEVEL_UP_MASK,
+			PS8802_USBEQ_LEVEL_UP_12DB));
+	}
+
+	/* DP specific config */
+	if (mux_state & USB_PD_MUX_DP_ENABLED) {
+		/* Boost the DP gain */
+		RETURN_ERROR(ps8802_i2c_field_update8(
+			me, PS8802_REG_PAGE2, PS8802_REG2_DPEQ_LEVEL,
+			PS8802_DPEQ_LEVEL_UP_MASK, PS8802_DPEQ_LEVEL_UP_9DB));
+	}
+
+	return EC_SUCCESS;
+}
+
+static int board_ps8762_mux_init(const struct usb_mux *me)
+{
+	return ps8802_i2c_field_update8(me, PS8802_REG_PAGE1, PS8802_REG_DCIRX,
+					PS8802_AUTO_DCI_MODE_DISABLE |
+						PS8802_FORCE_DCI_MODE,
+					PS8802_AUTO_DCI_MODE_DISABLE);
+}
+
+static int board_anx3443_mux_set(const struct usb_mux *me,
+				 mux_state_t mux_state)
+{
+	gpio_set_level(GPIO_USB_C1_DP_IN_HPD,
+		       mux_state & USB_PD_MUX_DP_ENABLED);
+	return EC_SUCCESS;
+}
+
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX0,
+				.i2c_addr_flags = PS8802_I2C_ADDR_FLAGS,
+				.driver = &ps8802_usb_mux_driver,
+				.board_init = &board_ps8762_mux_init,
+				.board_set = &board_ps8762_mux_set,
+			},
+	},
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_USB_MUX1,
+				.i2c_addr_flags = ANX3443_I2C_ADDR0_FLAGS,
+				.driver = &anx3443_usb_mux_driver,
+				.board_set = &board_anx3443_mux_set,
+			},
+	},
+};
+
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
+{
+	/* Limit input current lower than 2944 mA for safety */
+	charge_ma = MIN(charge_ma, 2944);
+
+	charge_set_input_current_limit(charge_ma, charge_mv);
+}
+
+/* NVME */
+static void nvme_enable(int enable)
+{
+	gpio_set_level(GPIO_EN_PP3300_SSD, enable);
+}
+
+void suspend_resume_power_signal_interrupt(enum gpio_signal signal)
+{
+	/* AP resume */
+	if (gpio_get_level(signal) == GPIO_SIGNAL_RESUME)
+		nvme_enable(1);
+	/* AP suspend */
+	else
+		nvme_enable(0);
+
+	power_signal_interrupt(signal);
+}
+
+/* Initialize board. */
+static void board_init(void)
+{
+	/* Enable motion sensor interrupt */
+	gpio_enable_interrupt(GPIO_BASE_IMU_INT_L);
+	gpio_enable_interrupt(GPIO_LID_ACCEL_INT_L);
+
+	/* Store board version for use of something */
+	cbi_get_board_version(&board_version);
+
+	/* Store base sensor to recognize which base sensor we are using */
+	base_sensor = get_cbi_ssfc_base_sensor();
+
+	/* Make sure that nvme can be enabled/disabled when board init */
+	if (gpio_get_level(GPIO_AP_IN_SLEEP_L) == GPIO_SIGNAL_RESUME)
+		nvme_enable(1);
+	else
+		nvme_enable(0);
+
+	board_update_motion_sensor_config();
+	board_update_vol_up_key();
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+static void board_do_chipset_resume(void)
+{
+	gpio_set_level(GPIO_EN_KB_BL, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_do_chipset_resume, HOOK_PRIO_DEFAULT);
+
+static void board_do_chipset_suspend(void)
+{
+	gpio_set_level(GPIO_EN_KB_BL, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_do_chipset_suspend, HOOK_PRIO_DEFAULT);
diff --git a/board/dojo/board.h b/board/dojo/board.h
new file mode 100644
index 0000000000..43ecd32d7c
--- /dev/null
+++ b/board/dojo/board.h
@@ -0,0 +1,167 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* Dojo board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "baseboard.h"
+
+/* Optional features */
+#define CONFIG_LTO
+#define CONFIG_PRESERVE_LOGS
+
+/* Watchdog period in ms */
+#undef CONFIG_WATCHDOG_PERIOD_MS
+#define CONFIG_WATCHDOG_PERIOD_MS 2500
+
+/*
+ * TODO: Remove this option once the VBAT no longer keeps high when
+ * system's power isn't presented.
+ */
+#define CONFIG_IT83XX_RESET_PD_CONTRACT_IN_BRAM
+
+/* Battery */
+#undef CONFIG_BATTERY_PRESENT_GPIO
+#define CONFIG_BATTERY_V2
+#define CONFIG_BATTERY_COUNT 1
+#define CONFIG_HOSTCMD_BATTERY_V2
+#define CONFIG_BATTERY_PRESENT_CUSTOM
+#define CONFIG_BATTERY_REVIVE_DISCONNECT
+#define CONFIG_BATTERY_VENDOR_PARAM
+
+/* BC12 */
+
+/* Charger */
+#define CONFIG_CHARGER_PROFILE_OVERRIDE
+
+/* Chipset */
+#define CONFIG_CHIPSET_RESUME_INIT_HOOK
+
+/* PD / USB-C / PPC */
+#undef CONFIG_USB_PD_DEBUG_LEVEL /* default to 1, configurable in ec console \
+				  */
+
+/* Optional console commands */
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_SCRATCHPAD
+
+#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV 9000
+
+/* Keyboard */
+#define CONFIG_KEYBOARD_REFRESH_ROW3
+#define CONFIG_KEYBOARD_FACTORY_TEST
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+
+/* Sensor */
+#define CONFIG_GMR_TABLET_MODE
+#define CONFIG_TABLET_MODE
+#define CONFIG_TABLET_MODE_SWITCH
+#define CONFIG_I2C_XFER_LARGE_TRANSFER
+
+/* ICM426XX Base accel/gyro */
+#define CONFIG_ACCELGYRO_ICM426XX
+#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+/* ICM42607 Base accel/gyro*/
+#define CONFIG_ACCELGYRO_ICM42607
+#define CONFIG_ACCELGYRO_ICM42607_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+/* BMI260 accel/gyro in base */
+#define CONFIG_ACCELGYRO_BMI260
+#define CONFIG_ACCELGYRO_BMI260_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+/* KX022 Lid accel */
+#define CONFIG_ACCEL_KX022
+
+#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
+
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+#define CONFIG_LID_ANGLE_UPDATE
+
+/* SPI / Host Command */
+#undef CONFIG_HOSTCMD_DEBUG_MODE
+#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
+
+/* USB-A */
+#define USBA_PORT_COUNT 1
+
+/* Temperature */
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_THERMISTOR
+#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum battery_type {
+	BATTERY_DYNAPACK_COS,
+	BATTERY_DYNAPACK_ATL,
+	BATTERY_SIMPLO_COS,
+	BATTERY_SIMPLO_HIGHPOWER,
+	BATTERY_COS,
+	BATTERY_TYPE_COUNT,
+};
+
+enum sensor_id {
+	BASE_ACCEL = 0,
+	BASE_GYRO,
+	LID_ACCEL,
+	SENSOR_COUNT,
+};
+
+enum pwm_channel {
+	PWM_CH_LED_C1_WHITE,
+	PWM_CH_LED_C1_AMBER,
+	PWM_CH_LED_PWR,
+	PWM_CH_KBLIGHT,
+	PWM_CH_LED_C0_WHITE,
+	PWM_CH_LED_C0_AMBER,
+	PWM_CH_COUNT,
+};
+
+/* Temperature charging level */
+enum temp_chg_lvl {
+	LEVEL_0 = 0,
+	LEVEL_1,
+	LEVEL_2,
+	CHG_LEVEL_COUNT,
+};
+
+/* Temperature charging struct */
+struct temp_chg_struct {
+	int lo_thre;
+	int hi_thre;
+	int chg_curr;
+};
+
+/* Forward declaration of temperature charging table */
+extern const struct temp_chg_struct temp_chg_table[];
+
+/* Vol-up key matrix struct */
+struct vol_up_key {
+	uint8_t row;
+	uint8_t col;
+};
+
+/* AP in sleep power signal */
+enum ap_in_sleep_l_signal {
+	GPIO_SIGNAL_SUSPEND = 0,
+	GPIO_SIGNAL_RESUME,
+};
+void suspend_resume_power_signal_interrupt(enum gpio_signal signal);
+
+int board_accel_force_mode_mask(void);
+void motion_interrupt(enum gpio_signal signal);
+
+#endif /* !__ASSEMBLER__ */
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/dojo/build.mk b/board/dojo/build.mk
new file mode 100644
index 0000000000..740cd30a9d
--- /dev/null
+++ b/board/dojo/build.mk
@@ -0,0 +1,14 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+
+# the IC is ITE IT8xxx2
+CHIP:=it83xx
+CHIP_FAMILY:=it8xxx2
+CHIP_VARIANT:=it81202bx_1024
+BASEBOARD:=cherry
+
+board-y+=led.o battery.o board.o cbi_fw_config.o cbi_ssfc.o
diff --git a/board/dojo/cbi_fw_config.c b/board/dojo/cbi_fw_config.c
new file mode 100644
index 0000000000..96e6d9b266
--- /dev/null
+++ b/board/dojo/cbi_fw_config.c
@@ -0,0 +1,41 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi_fw_config.h"
+#include "common.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "hooks.h"
+
+/****************************************************************************
+ * Dojo CBI FW Configuration
+ */
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+/* Cache FW_CONFIG on init since we don't expect it to change in runtime */
+static uint32_t cached_fw_config;
+
+static void cbi_fw_config_init(void)
+{
+	if (cbi_get_fw_config(&cached_fw_config) != EC_SUCCESS)
+		/* Default to 0 when CBI isn't populated */
+		cached_fw_config = 0;
+
+	CPRINTS("FW_CONFIG: 0x%04X", cached_fw_config);
+}
+DECLARE_HOOK(HOOK_INIT, cbi_fw_config_init, HOOK_PRIO_FIRST);
+
+enum fw_config_kblight_type get_cbi_fw_config_kblight(void)
+{
+	return ((cached_fw_config & FW_CONFIG_KB_BL_MASK) >>
+		FW_CONFIG_KB_BL_OFFSET);
+}
+
+enum fw_config_kblayout_type get_cbi_fw_config_kblayout(void)
+{
+	return ((cached_fw_config & FW_CONFIG_KB_LAYOUT_MASK) >>
+		FW_CONFIG_KB_LAYOUT_OFFSET);
+}
diff --git a/board/dojo/cbi_fw_config.h b/board/dojo/cbi_fw_config.h
new file mode 100644
index 0000000000..6ca0e5b9a8
--- /dev/null
+++ b/board/dojo/cbi_fw_config.h
@@ -0,0 +1,36 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _DOJO_CBI_FW_CONFIG__H_
+#define _DOJO_CBI_FW_CONFIG__H_
+
+/****************************************************************************
+ * Dojo CBI FW Configuration
+ */
+
+/*
+ * Keyboard backlight (bit 0)
+ */
+enum fw_config_kblight_type {
+	KB_BL_ABSENT = 0,
+	KB_BL_PRESENT = 1,
+};
+#define FW_CONFIG_KB_BL_OFFSET 0
+#define FW_CONFIG_KB_BL_MASK GENMASK(0, 0)
+
+/*
+ * Keyboard layout (bit 4-5)
+ */
+enum fw_config_kblayout_type {
+	KB_BL_TOGGLE_KEY_ABSENT = 0, /* Vol-up key on T12 */
+	KB_BL_TOGGLE_KEY_PRESENT = 1, /* Vol-up key on T13 */
+};
+#define FW_CONFIG_KB_LAYOUT_OFFSET 4
+#define FW_CONFIG_KB_LAYOUT_MASK GENMASK(5, 4)
+
+enum fw_config_kblight_type get_cbi_fw_config_kblight(void);
+enum fw_config_kblayout_type get_cbi_fw_config_kblayout(void);
+
+#endif /* _DOJO_CBI_FW_CONFIG__H_ */
diff --git a/board/dojo/cbi_ssfc.c b/board/dojo/cbi_ssfc.c
new file mode 100644
index 0000000000..3b7ed483f5
--- /dev/null
+++ b/board/dojo/cbi_ssfc.c
@@ -0,0 +1,36 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi_ssfc.h"
+#include "common.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "hooks.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+/* Cache SSFC on init since we don't expect it to change in runtime */
+static union dojo_cbi_ssfc cached_ssfc;
+BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
+
+static void cbi_ssfc_init(void)
+{
+	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
+		/* Default to 0 when CBI isn't populated */
+		cached_ssfc.raw_value = 0;
+
+	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
+}
+DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
+
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
+{
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
+}
+
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
+{
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
+}
diff --git a/board/dojo/cbi_ssfc.h b/board/dojo/cbi_ssfc.h
new file mode 100644
index 0000000000..da37dbaca1
--- /dev/null
+++ b/board/dojo/cbi_ssfc.h
@@ -0,0 +1,57 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _DOJO_CBI_SSFC__H_
+#define _DOJO_CBI_SSFC__H_
+
+#include "stdint.h"
+
+/****************************************************************************
+ * Dojo CBI Second Source Factory Cache
+ */
+
+/*
+ * Base Sensor (Bits 0-2)
+ */
+enum ec_ssfc_base_sensor {
+	SSFC_SENSOR_BASE_DEFAULT = 0,
+	SSFC_SENSOR_ICM42607 = 1,
+	SSFC_SENSOR_ICM426XX = 2,
+	SSFC_SENSOR_BMI260 = 3,
+};
+
+/*
+ * Lid Sensor (Bits 3-5)
+ */
+enum ec_ssfc_lid_sensor {
+	SSFC_SENSOR_LID_DEFAULT = 0,
+	SSFC_SENSOR_BMA422 = 1,
+	SSFC_SENSOR_KX022 = 2,
+};
+
+union dojo_cbi_ssfc {
+	struct {
+		uint32_t base_sensor : 3;
+		uint32_t lid_sensor : 3;
+		uint32_t reserved_2 : 26;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Get the Base sensor type from SSFC_CONFIG.
+ *
+ * @return the Base sensor board type.
+ */
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
+
+/**
+ * Get the Lid sensor type from SSFC_CONFIG.
+ *
+ * @return the Lid sensor board type.
+ */
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
+
+#endif /* _DOJO_CBI_SSFC__H_ */
diff --git a/board/dojo/ec.tasklist b/board/dojo/ec.tasklist
new file mode 100644
index 0000000000..5ce0fab583
--- /dev/null
+++ b/board/dojo/ec.tasklist
@@ -0,0 +1,23 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 1024) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(DPS, dps_task, NULL, 1280) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, 1280) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, 1280) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, 1024) \
+
diff --git a/board/dojo/gpio.inc b/board/dojo/gpio.inc
new file mode 100644
index 0000000000..35a0fa0eae
--- /dev/null
+++ b/board/dojo/gpio.inc
@@ -0,0 +1,156 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+/* Wake Source interrupts */
+GPIO_INT(POWER_BUTTON_L,     PIN(E, 4), GPIO_INT_BOTH | GPIO_PULL_UP |
+	 GPIO_HIB_WAKE_HIGH, power_button_interrupt) /* GSC_EC_PWR_BTN_ODL */
+GPIO_INT(LID_OPEN,           PIN(E, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,
+         lid_interrupt)
+GPIO_INT(TABLET_MODE_L,      PIN(J, 7), GPIO_INT_BOTH,
+         gmr_tablet_switch_isr)
+
+/* Chipset interrupts */
+GPIO_INT(AP_EC_WARM_RST_REQ, PIN(D, 3), GPIO_INT_RISING | GPIO_SEL_1P8V,
+         chipset_reset_request_interrupt)
+
+/* Power sequencing interrupts */
+GPIO_INT(AP_EC_WATCHDOG_L, PIN(C, 7), GPIO_INT_BOTH | GPIO_SEL_1P8V,
+         chipset_watchdog_interrupt)
+GPIO_INT(AP_IN_SLEEP_L, PIN(F, 2),
+         GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V,
+         suspend_resume_power_signal_interrupt)
+GPIO_INT(PMIC_EC_PWRGD, PIN(F, 3),
+         GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V, power_signal_interrupt)
+
+/* Sensor Interrupts */
+GPIO_INT(BASE_IMU_INT_L,     PIN(M, 3), GPIO_INT_FALLING | GPIO_SEL_1P8V,
+         motion_interrupt)
+/* USB-C interrupts */
+GPIO_INT(USB_C0_PPC_INT_ODL, PIN(D, 1), GPIO_INT_BOTH, ppc_interrupt)
+GPIO_INT(USB_C0_BC12_INT_ODL,PIN(I, 5), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C1_INT_ODL,     PIN(B, 2), GPIO_INT_FALLING, rt1718s_tcpc_interrupt)
+/* TODO: not used in other devices? */
+GPIO(LID_ACCEL_INT_L,        PIN(M, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V)
+
+/* Volume button interrupts */
+GPIO_INT(VOLUME_DOWN_L,      PIN(D, 5), GPIO_INT_BOTH | GPIO_PULL_UP,
+         button_interrupt) /* EC_VOLDN_BTN_ODL */
+GPIO_INT(VOLUME_UP_L,        PIN(D, 6), GPIO_INT_BOTH | GPIO_PULL_UP,
+         button_interrupt) /* EC_VOLUP_BTN_ODL */
+
+/* Other interrupts */
+GPIO_INT(AC_PRESENT,         PIN(E, 5), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,
+         extpower_interrupt) /* AC_OK / AC_PRESENT in rev1+ */
+GPIO_INT(UART1_RX,           PIN(B, 0), GPIO_INT_FALLING,
+         uart_deepsleep_interrupt) /* UART_DEBUG_TX_EC_RX */
+GPIO_INT(WP,                 PIN(I, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V,
+         switch_interrupt) /* EC_FLASH_WP_OD */
+GPIO_INT(SPI0_CS,            PIN(M, 5), GPIO_INT_FALLING,
+         spi_event)        /* SPI slave Chip Select -- AP_SPI_EC_CS_L */
+GPIO_INT(AP_XHCI_INIT_DONE,  PIN(J, 5), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V,
+         xhci_init_done_interrupt)
+
+/* Power Sequencing Signals */
+GPIO(EC_PMIC_EN_ODL,         PIN(D, 0), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(EC_PMIC_WATCHDOG_L,     PIN(H, 0), GPIO_ODR_LOW | GPIO_SEL_1P8V)
+GPIO(EN_PP5000_A,            PIN(C, 6), GPIO_OUT_HIGH)
+GPIO(PG_MT6315_PROC_B_ODL,   PIN(E, 1), GPIO_INPUT)
+GPIO(PG_MT6360_ODL,          PIN(F, 1), GPIO_INPUT)
+GPIO(EN_SLP_Z,               PIN(E, 3), GPIO_OUT_LOW)
+GPIO(SYS_RST_ODL,            PIN(B, 6), GPIO_ODR_LOW)
+GPIO(EC_BL_EN_OD,            PIN(B, 5), GPIO_ODR_LOW | GPIO_SEL_1P8V)
+GPIO(EN_PP3300_SSD,          PIN(H, 1), GPIO_ODR_LOW) /* NVME power sequence control */
+
+/* MKBP event synchronization */
+GPIO(EC_INT_L,               PIN(E, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V) /* EC_AP_INT_ODL */
+
+/* USB and USBC Signals */
+GPIO(DP_PATH_SEL,            PIN(G, 0), GPIO_OUT_HIGH)
+GPIO(DP_DEMUX_EN,            PIN(G, 1), GPIO_OUT_LOW)
+GPIO(EC_AP_DP_HPD_ODL,       PIN(J, 0), GPIO_ODR_HIGH)
+GPIO(EN_PP5000_USB_A0_VBUS_X,PIN(B, 7), GPIO_OUT_LOW)
+GPIO(USB_C0_DP_IN_HPD,       PIN(H, 4), GPIO_OUT_LOW)
+GPIO(USB_C1_DP_IN_HPD,       PIN(J, 1), GPIO_OUT_LOW)
+GPIO(USB_C0_FRS_EN,          PIN(F, 0), GPIO_OUT_LOW)
+
+/* Misc Signals */
+GPIO(EN_KB_BL,               PIN(J, 2), GPIO_OUT_LOW)
+GPIO(EC_BATT_PRES_ODL,       PIN(C, 0), GPIO_INPUT)
+GPIO(EN_EC_ID_ODL,           PIN(H, 5), GPIO_ODR_LOW)
+GPIO(ENTERING_RW,            PIN(C, 5), GPIO_OUT_LOW) /* EC_ENTERING_RW */
+GPIO(EN_5V_USM,              PIN(G, 3), GPIO_OUT_LOW)
+GPIO(USB_A0_FAULT_ODL,       PIN(J, 6), GPIO_INPUT)
+GPIO(PACKET_MODE_EN,         PIN(D, 4), GPIO_OUT_LOW) /* EC_GSC_PACKET_MODE */
+
+/* I2C pins - Alternate function below configures I2C module on these pins */
+GPIO(I2C_A_SCL,              PIN(B, 3), GPIO_INPUT) /* I2C_CHG_BATT_SCL */
+GPIO(I2C_A_SDA,              PIN(B, 4), GPIO_INPUT) /* I2C_CHG_BATT_SDA */
+GPIO(I2C_B_SCL,              PIN(C, 1), GPIO_INPUT | GPIO_SEL_1P8V) /* I2C_SENSOR_SCL */
+GPIO(I2C_B_SDA,              PIN(C, 2), GPIO_INPUT | GPIO_SEL_1P8V) /* I2C_SENSOR_SDA */
+GPIO(I2C_C_SCL,              PIN(F, 6), GPIO_INPUT) /* I2C_USB_C0_SCL */
+GPIO(I2C_C_SDA,              PIN(F, 7), GPIO_INPUT) /* I2C_USB_C0_SDA */
+GPIO(I2C_E_SCL,              PIN(E, 0), GPIO_INPUT) /* I2C_USB_C1_SCL */
+GPIO(I2C_E_SDA,              PIN(E, 7), GPIO_INPUT) /* I2C_USB_C1_SDA */
+GPIO(I2C_F_SCL,              PIN(A, 4), GPIO_INPUT) /* Rev 2+ I2C_PROG_SCL */
+GPIO(I2C_F_SDA,              PIN(A, 5), GPIO_INPUT) /* Rev 2+ I2C_PROG_SDA */
+
+/* Alternate functions GPIO definitions */
+ALTERNATE(PIN_MASK(B, 0x18), 1, MODULE_I2C, 0) /* I2C A */
+ALTERNATE(PIN_MASK(C, 0x06), 1, MODULE_I2C, GPIO_SEL_1P8V) /* I2C B */
+ALTERNATE(PIN_MASK(F, 0xC0), 1, MODULE_I2C, 0) /* I2C C */
+ALTERNATE(PIN_MASK(E, 0x81), 1, MODULE_I2C, 0) /* I2C E */
+
+/* UART */
+ALTERNATE(PIN_MASK(B, 0x03), 1, MODULE_UART, 0) /* EC to Servo */
+
+/* PWM */
+ALTERNATE(PIN_MASK(A, 0b11001111), 1, MODULE_PWM, 0) /* PWM 0,1,2,3,6,7 */
+
+/* ADC */
+ALTERNATE(PIN_MASK(I, 0b11001001), 0, MODULE_ADC, 0) /* ADC 0,3,6,7 */
+
+/* SPI */
+ALTERNATE(PIN_MASK(M, 0x33), 0, MODULE_SPI, 0) /* SPI */
+
+/* KEYBOARD */
+ALTERNATE(PIN_MASK(KSI,   0xFF), 0, MODULE_KEYBOARD_SCAN, 0)		/* KSI0-7 */
+ALTERNATE(PIN_MASK(KSO_H, 0xFF), 0, MODULE_KEYBOARD_SCAN, 0)		/* KSO8-15 */
+ALTERNATE(PIN_MASK(KSO_L, 0xFB), 0, MODULE_KEYBOARD_SCAN, 0)		/* KSO0-1, 3-7 */
+GPIO(EC_KSO_02_INV, PIN(KSO_L, 2), GPIO_OUT_HIGH) /* KSO2 inverted */
+
+/* Unimplemented Pins  */
+GPIO(PG_PP5000_S5_OD,        PIN(D, 2), GPIO_INPUT)
+/* *_ODL pin has external pullup so don't pull it down. */
+GPIO(PG_MT6315_GPU_ODL,      PIN(H, 6), GPIO_INPUT)
+/* reserved for future use */
+GPIO(CCD_MODE_ODL,           PIN(C, 4), GPIO_INPUT)
+
+/* NC pins, enable internal pull-up/down to avoid floating state. */
+GPIO(NC_GPA1,                PIN(A, 1), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(EC_NVME_PLN_ODL,        PIN(D, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(SPI_CLK_GPG6,           PIN(G, 6), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(NC_GPH2,                PIN(H, 2), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(PG_NVME_OD,             PIN(H, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(EN_PP1200_NVME_X,       PIN(J, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(NC_GPJ4,                PIN(J, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(NC_GPM6,                PIN(M, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+/*
+ * These pins don't have internal pull-down capability,
+ * so we set them as output low.
+ */
+GPIO(SPI_MOSI_GPG4,          PIN(G, 4), GPIO_OUT_LOW)
+GPIO(SPI_MISO_GPG5,          PIN(G, 5), GPIO_OUT_LOW)
+GPIO(SPI_CS_GPG7,            PIN(G, 7), GPIO_OUT_LOW)
+GPIO(EC_ID0,                 PIN(I, 1), GPIO_OUT_LOW)
+GPIO(EC_ID1,                 PIN(I, 2), GPIO_OUT_LOW)
+
+/* Other unused pins */
+GPIO(NVME_EC_PLA_S3_ODL,     PIN(I, 7), GPIO_INPUT)
+
diff --git a/board/dojo/led.c b/board/dojo/led.c
new file mode 100644
index 0000000000..e041ea6a79
--- /dev/null
+++ b/board/dojo/led.c
@@ -0,0 +1,227 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "chipset.h"
+#include "ec_commands.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "led_common.h"
+#include "pwm.h"
+#include "system.h"
+#include "util.h"
+
+/* Times of tick per 1 second */
+#define TIMES_TICK_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS)
+/* Times of tick per half second */
+#define TIMES_TICK_HALF_SEC (500 / HOOK_TICK_INTERVAL_MS)
+
+#define BAT_LED_ON 1
+#define BAT_LED_OFF 0
+
+#define PWR_LED_ON 1
+#define PWR_LED_OFF 0
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_RIGHT_LED,
+	EC_LED_ID_LEFT_LED,
+	EC_LED_ID_POWER_LED,
+};
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+enum led_color {
+	LED_OFF = 0,
+	LED_AMBER,
+	LED_WHITE,
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
+};
+
+enum led_port {
+	RIGHT_PORT = 0,
+	LEFT_PORT,
+};
+
+static void battery_led_set_color(enum led_port port, enum led_color color)
+{
+	pwm_enable(port ? PWM_CH_LED_C1_AMBER : PWM_CH_LED_C0_AMBER,
+		   (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
+	pwm_enable(port ? PWM_CH_LED_C1_WHITE : PWM_CH_LED_C0_WHITE,
+		   (color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF);
+}
+
+static void power_led_set_color(enum led_color color)
+{
+	pwm_enable(PWM_CH_LED_PWR,
+		   (color == LED_WHITE) ? PWR_LED_ON : PWR_LED_OFF);
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	switch (led_id) {
+	case EC_LED_ID_RIGHT_LED:
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		break;
+	case EC_LED_ID_LEFT_LED:
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		break;
+	case EC_LED_ID_POWER_LED:
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		break;
+	default:
+		break;
+	}
+}
+
+static int led_set_color(enum ec_led_id led_id, enum led_color color)
+{
+	switch (led_id) {
+	case EC_LED_ID_RIGHT_LED:
+		battery_led_set_color(RIGHT_PORT, color);
+		break;
+	case EC_LED_ID_LEFT_LED:
+		battery_led_set_color(LEFT_PORT, color);
+		break;
+	case EC_LED_ID_POWER_LED:
+		power_led_set_color(color);
+		break;
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (brightness[EC_LED_COLOR_WHITE] != 0)
+		led_set_color(led_id, LED_WHITE);
+	else if (brightness[EC_LED_COLOR_AMBER] != 0)
+		led_set_color(led_id, LED_AMBER);
+	else
+		led_set_color(led_id, LED_OFF);
+
+	return EC_SUCCESS;
+}
+
+/*
+ * Set active charge port color to the parameter, turn off all others.
+ * If no port is active (-1), turn off all LEDs.
+ */
+static void set_active_port_color(enum led_color color)
+{
+	int port = charge_manager_get_active_charge_port();
+
+	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
+		battery_led_set_color(RIGHT_PORT,
+				      (port == RIGHT_PORT) ? color : LED_OFF);
+	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
+		battery_led_set_color(LEFT_PORT,
+				      (port == LEFT_PORT) ? color : LED_OFF);
+}
+
+static void board_led_set_battery(void)
+{
+	static int battery_ticks;
+	int battery_led_blink_cycle;
+
+	battery_ticks++;
+
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
+		/* Always indicate when charging, even in suspend. */
+		set_active_port_color(LED_AMBER);
+		break;
+	case LED_PWRS_DISCHARGE:
+		if (charge_get_percent() <= 10) {
+			battery_led_blink_cycle =
+				battery_ticks % (2 * TIMES_TICK_ONE_SEC);
+			if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
+				battery_led_set_color(RIGHT_PORT,
+						      (battery_led_blink_cycle <
+						       TIMES_TICK_ONE_SEC) ?
+							      LED_AMBER :
+							      LED_OFF);
+			if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
+				battery_led_set_color(LEFT_PORT,
+						      (battery_led_blink_cycle <
+						       TIMES_TICK_ONE_SEC) ?
+							      LED_AMBER :
+							      LED_OFF);
+		} else {
+			if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
+				battery_led_set_color(RIGHT_PORT, LED_OFF);
+			if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
+				battery_led_set_color(LEFT_PORT, LED_OFF);
+		}
+		break;
+	case LED_PWRS_ERROR:
+		battery_led_blink_cycle = battery_ticks % TIMES_TICK_ONE_SEC;
+		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
+			battery_led_set_color(RIGHT_PORT,
+					      (battery_led_blink_cycle <
+					       TIMES_TICK_HALF_SEC) ?
+						      LED_AMBER :
+						      LED_OFF);
+		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
+			battery_led_set_color(LEFT_PORT,
+					      (battery_led_blink_cycle <
+					       TIMES_TICK_HALF_SEC) ?
+						      LED_AMBER :
+						      LED_OFF);
+		break;
+	case LED_PWRS_CHARGE_NEAR_FULL:
+		set_active_port_color(LED_WHITE);
+		break;
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		set_active_port_color(LED_WHITE);
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		battery_led_blink_cycle =
+			battery_ticks % (2 * TIMES_TICK_ONE_SEC);
+		set_active_port_color(
+			(battery_led_blink_cycle < TIMES_TICK_ONE_SEC) ?
+				LED_AMBER :
+				LED_OFF);
+		break;
+	default:
+		/* Other states don't alter LED behavior */
+		break;
+	}
+}
+
+static void board_led_set_power(void)
+{
+	static int power_ticks;
+	int power_led_blink_cycle;
+
+	power_ticks++;
+
+	if (chipset_in_state(CHIPSET_STATE_ON)) {
+		power_led_set_color(LED_WHITE);
+	} else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
+		power_led_blink_cycle = power_ticks % (2 * TIMES_TICK_ONE_SEC);
+		power_led_set_color(power_led_blink_cycle < TIMES_TICK_ONE_SEC ?
+					    LED_WHITE :
+					    LED_OFF);
+	} else {
+		power_led_set_color(LED_OFF);
+	}
+}
+
+/* Called by hook task every TICK */
+static void led_tick(void)
+{
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		board_led_set_power();
+
+	board_led_set_battery();
+}
+DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
diff --git a/board/dojo/vif_override.xml b/board/dojo/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/dojo/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/don b/board/don
new file mode 120000
index 0000000000..7ca3c85ad3
--- /dev/null
+++ b/board/don
@@ -0,0 +1 @@
+hammer/
\ No newline at end of file
diff --git a/board/dood/battery.c b/board/dood/battery.c
index e719ea3151..8564eb0926 100644
--- a/board/dood/battery.c
+++ b/board/dood/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -277,6 +277,8 @@ const struct board_batt_params board_battery_info[] = {
 				.reg_addr = 0x43,
 				.reg_mask = 0x0001,
 				.disconnect_val = 0x0,
+				.cfet_mask = 0x0002,
+				.cfet_off_val = 0x0,
 			},
 		},
 		.batt_info = {
diff --git a/board/dood/board.c b/board/dood/board.c
index eb87efe87e..9d395d3bfe 100644
--- a/board/dood/board.c
+++ b/board/dood/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,6 @@
 /* dood board-specific configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "battery.h"
 #include "button.h"
 #include "charge_manager.h"
@@ -38,19 +37,19 @@
 #include "switch.h"
 #include "system.h"
 #include "tablet_mode.h"
-#include "tcpci.h"
+#include "tcpm/tcpci.h"
 #include "temp_sensor.h"
-#include "thermistor.h"
+#include "temp_sensor/thermistor.h"
 #include "usb_charge.h"
 #include "usb_mux.h"
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define USB_PD_PORT_ANX7447	0
-#define USB_PD_PORT_PS8751	1
+#define USB_PD_PORT_ANX7447 0
+#define USB_PD_PORT_PS8751 1
 
 static uint8_t sku_id;
 
@@ -60,17 +59,16 @@ static uint8_t sku_id;
  * that we don't have pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-		{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-		{0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3},
-		{-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0},
-		{1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4},
-		{2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0},
-		{-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1},
-		{-1, -1},
+	{ -1, -1 }, { 0, 5 },	{ 1, 1 }, { 1, 0 },   { 0, 6 },	  { 0, 7 },
+	{ -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 },   { -1, -1 }, { 1, 6 },
+	{ 1, 7 },   { 3, 1 },	{ 2, 0 }, { 1, 5 },   { 2, 6 },	  { 2, 7 },
+	{ 2, 1 },   { 2, 4 },	{ 2, 5 }, { 1, 2 },   { 2, 3 },	  { 2, 2 },
+	{ 3, 0 },   { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 },	  { -1, -1 },
+	{ -1, -1 },
 };
 
 const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 
 /* Check PPC ID and board version to decide which one ppc is used. */
 static bool support_syv_ppc(void)
@@ -88,7 +86,6 @@ static bool support_syv_ppc(void)
 
 static void ppc_interrupt(enum gpio_signal signal)
 {
-
 	switch (signal) {
 	case GPIO_USB_PD_C0_INT_ODL:
 		if (support_syv_ppc())
@@ -114,31 +111,31 @@ static void ppc_interrupt(enum gpio_signal signal)
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_AMB] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_AMB] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				  ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_CHARGER] = { "TEMP_CHARGER", NPCX_ADC_CH1,
+				      ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 },
 	/* Vbus sensing (1/10 voltage divider). */
-	[ADC_VBUS_C0] = {
-		"VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
-	[ADC_VBUS_C1] = {
-		"VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
+	[ADC_VBUS_C0] = { "VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT * 10,
+			  ADC_READ_MAX + 1, 0 },
+	[ADC_VBUS_C1] = { "VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT * 10,
+			  ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp,
-				 .idx = 0},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
+	[TEMP_SENSOR_BATTERY] = { .name = "Battery",
+				  .type = TEMP_SENSOR_TYPE_BATTERY,
+				  .read = charge_get_battery_temp,
+				  .idx = 0 },
+	[TEMP_SENSOR_AMBIENT] = { .name = "Ambient",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_51k1_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_AMB },
+	[TEMP_SENSOR_CHARGER] = { .name = "Charger",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_13k7_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_CHARGER },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -148,11 +145,9 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0,  0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+				       { FLOAT_TO_FP(1), 0, 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
 
 /* sensor private data */
 static struct kionix_accel_data g_kx022_data;
@@ -275,17 +270,16 @@ void board_hibernate_late(void)
 
 	const uint32_t hibernate_pins[][2] = {
 		/* Turn off LEDs before going to hibernate */
-		{GPIO_BAT_LED_WHITE_L, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_BAT_LED_AMBER_L, GPIO_INPUT | GPIO_PULL_UP},
+		{ GPIO_BAT_LED_WHITE_L, GPIO_INPUT | GPIO_PULL_UP },
+		{ GPIO_BAT_LED_AMBER_L, GPIO_INPUT | GPIO_PULL_UP },
 	};
 
 	for (i = 0; i < ARRAY_SIZE(hibernate_pins); ++i)
 		gpio_set_flags(hibernate_pins[i][0], hibernate_pins[i][1]);
 }
 
-#ifndef TEST_BUILD
 /* This callback disables keyboard when convertibles are fully open */
-void lid_angle_peripheral_enable(int enable)
+__override void lid_angle_peripheral_enable(int enable)
 {
 	/*
 	 * If the lid is in tablet position via other sensors,
@@ -297,7 +291,6 @@ void lid_angle_peripheral_enable(int enable)
 	if (board_is_convertible())
 		keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
 }
-#endif
 
 void board_overcurrent_event(int port, int is_overcurrented)
 {
@@ -310,15 +303,15 @@ void board_overcurrent_event(int port, int is_overcurrented)
 }
 
 const struct ppc_config_t ppc_syv682x_port0 = {
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
+	.i2c_port = I2C_PORT_TCPC0,
+	.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+	.drv = &syv682x_drv,
 };
 
 const struct ppc_config_t ppc_syv682x_port1 = {
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
+	.i2c_port = I2C_PORT_TCPC1,
+	.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+	.drv = &syv682x_drv,
 };
 
 static void board_setup_ppc(void)
@@ -326,12 +319,10 @@ static void board_setup_ppc(void)
 	if (!support_syv_ppc())
 		return;
 
-	memcpy(&ppc_chips[USB_PD_PORT_TCPC_0],
-		&ppc_syv682x_port0,
-		sizeof(struct ppc_config_t));
-	memcpy(&ppc_chips[USB_PD_PORT_TCPC_1],
-		&ppc_syv682x_port1,
-		sizeof(struct ppc_config_t));
+	memcpy(&ppc_chips[USB_PD_PORT_TCPC_0], &ppc_syv682x_port0,
+	       sizeof(struct ppc_config_t));
+	memcpy(&ppc_chips[USB_PD_PORT_TCPC_1], &ppc_syv682x_port1,
+	       sizeof(struct ppc_config_t));
 
 	gpio_set_flags(GPIO_USB_PD_C0_INT_ODL, GPIO_INT_BOTH);
 	gpio_set_flags(GPIO_USB_PD_C1_INT_ODL, GPIO_INT_BOTH);
diff --git a/board/dood/board.h b/board/dood/board.h
index 47e5b460da..8c9f225a59 100644
--- a/board/dood/board.h
+++ b/board/dood/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,18 +13,16 @@
 #define VARIANT_OCTOPUS_CHARGER_ISL9238
 #include "baseboard.h"
 
-/* I2C bus configuraiton */
-#define I2C_PORT_ACCEL	I2C_PORT_SENSOR
+#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD
 
-/* EC console commands  */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
+/* I2C bus configuraiton */
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
 
 #define CONFIG_LED_COMMON
 
 /* Sensors */
-#define CONFIG_ACCEL_KX022	/* Lid accel */
-#define CONFIG_ACCELGYRO_BMI160	/* Base accel */
+#define CONFIG_ACCEL_KX022 /* Lid accel */
+#define CONFIG_ACCELGYRO_BMI160 /* Base accel */
 
 #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
 /* Sensors without hardware FIFO are in forced mode */
@@ -34,8 +32,7 @@
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 
-#define CONFIG_SYNC_INT_EVENT	\
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
+#define CONFIG_SYNC_INT_EVENT TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
 
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_UPDATE
@@ -56,23 +53,25 @@
 #define CONFIG_USBC_PPC_DEDICATED_INT
 #undef CONFIG_SYV682X_HV_ILIM
 #define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_5_50
+/* SYV682 isn't connected to CC, so TCPC must provide VCONN */
+#define CONFIG_USBC_PPC_SYV682X_NO_CC
 
+/* prevent pd reset when battery soc under 2% */
+#define CONFIG_USB_PD_RESET_MIN_BATT_SOC 2
 
 #ifndef __ASSEMBLER__
 
 /* support factory keyboard test */
 #define CONFIG_KEYBOARD_FACTORY_TEST
-extern const int keyboard_factory_scan_pins[][2];
-extern const int keyboard_factory_scan_pins_used;
 
 #include "gpio_signal.h"
 #include "registers.h"
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_AMB,		/* ADC0 */
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC1 */
-	ADC_VBUS_C0,			/* ADC9 */
-	ADC_VBUS_C1,			/* ADC4 */
+	ADC_TEMP_SENSOR_AMB, /* ADC0 */
+	ADC_TEMP_SENSOR_CHARGER, /* ADC1 */
+	ADC_VBUS_C0, /* ADC9 */
+	ADC_VBUS_C1, /* ADC4 */
 	ADC_CH_COUNT
 };
 
@@ -84,12 +83,7 @@ enum temp_sensor_id {
 };
 
 /* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
diff --git a/board/dood/build.mk b/board/dood/build.mk
index 3d04b75731..998a65a3de 100644
--- a/board/dood/build.mk
+++ b/board/dood/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/dood/ec.tasklist b/board/dood/ec.tasklist
index d98db145e7..977b8b01be 100644
--- a/board/dood/ec.tasklist
+++ b/board/dood/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/dood/gpio.inc b/board/dood/gpio.inc
index 961acf8ee0..b10c377ddf 100644
--- a/board/dood/gpio.inc
+++ b/board/dood/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/dood/led.c b/board/dood/led.c
index c31b2d5316..248dae037f 100644
--- a/board/dood/led.c
+++ b/board/dood/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,32 +10,40 @@
 #include "led_common.h"
 #include "led_onoff_states.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
-const int led_charge_lvl_1;
+__override const int led_charge_lvl_1;
 
-const int led_charge_lvl_2 = 100;
+__override const int led_charge_lvl_2 = 100;
 
 /* Dood: Note there is only LED for charge / power */
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_WHITE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE,  2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
 const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-void led_set_color_battery(enum ec_led_colors color)
+__override void led_set_color_battery(enum ec_led_colors color)
 {
 	switch (color) {
 	case EC_LED_COLOR_WHITE:
@@ -70,4 +78,3 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 
 	return EC_SUCCESS;
 }
-
diff --git a/board/dood/vif_override.xml b/board/dood/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/dood/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/dooly/board.c b/board/dooly/board.c
index 8c1c295a66..306fc86ae3 100644
--- a/board/dooly/board.c
+++ b/board/dooly/board.c
@@ -1,20 +1,23 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Dooly board-specific configuration */
 
+#include "accelgyro.h"
 #include "adc.h"
-#include "adc_chip.h"
 #include "button.h"
 #include "charge_manager.h"
-#include "charge_state_v2.h"
+#include "charge_state.h"
 #include "chipset.h"
 #include "common.h"
 #include "core/cortex-m/cpu.h"
 #include "cros_board_info.h"
+#include "driver/accel_bma2x2.h"
+#include "driver/als_tcs3400.h"
 #include "driver/ina3221.h"
+#include "driver/led/mp3385.h"
 #include "driver/led/oz554.h"
 #include "driver/ppc/sn5s330.h"
 #include "driver/tcpm/anx7447.h"
@@ -38,8 +41,8 @@
 #include "system.h"
 #include "task.h"
 #include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
 #include "thermal.h"
-#include "thermistor.h"
 #include "uart.h"
 #include "usb_charge.h"
 #include "usb_common.h"
@@ -47,12 +50,208 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/* Sensors */
+static struct mutex g_accel_mutex;
+static struct accelgyro_saved_data_t g_bma253_data;
+
+/* TCS3400 private data */
+static struct als_drv_data_t g_tcs3400_data = {
+	.als_cal.scale = 1,
+	.als_cal.uscale = 0,
+	.als_cal.offset = 0,
+	.als_cal.channel_scale = {
+		.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kc */
+		.cover_scale = ALS_CHANNEL_SCALE(1.0),     /* CT */
+	},
+};
+static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
+	/*
+	 * TODO: calculate the actual coefficients and scaling factors
+	 */
+	.calibration.rgb_cal[X] = {
+		.offset = 0,
+		.scale = {
+			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kr */
+			.cover_scale = ALS_CHANNEL_SCALE(1.0)
+		},
+		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
+		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
+		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
+		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
+	},
+	.calibration.rgb_cal[Y] = {
+		.offset = 0,
+		.scale = {
+			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kg */
+			.cover_scale = ALS_CHANNEL_SCALE(1.0)
+		},
+		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
+		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
+		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
+		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0.1),
+	},
+	.calibration.rgb_cal[Z] = {
+		.offset = 0,
+		.scale = {
+			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kb */
+			.cover_scale = ALS_CHANNEL_SCALE(1.0)
+		},
+		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
+		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
+		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
+		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
+	},
+	.calibration.irt = INT_TO_FP(1),
+	.saturation.again = TCS_DEFAULT_AGAIN,
+	.saturation.atime = TCS_DEFAULT_ATIME,
+};
+
+const mat33_fp_t screen_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					 { FLOAT_TO_FP(1), 0, 0 },
+					 { 0, 0, FLOAT_TO_FP(-1) } };
+
+struct motion_sensor_t motion_sensors[] = {
+	[SCREEN_ACCEL] = {
+		.name = "Screen Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMA255,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &bma2x2_accel_drv,
+		.mutex = &g_accel_mutex,
+		.drv_data = &g_bma253_data,
+		.port = I2C_PORT_SENSORS,
+		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR2_FLAGS,
+		.rot_standard_ref = &screen_standard_ref,
+		.default_range = 2,
+		.min_frequency = BMA255_ACCEL_MIN_FREQ,
+		.max_frequency = BMA255_ACCEL_MAX_FREQ,
+		.config = {
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+		},
+	},
+	[CLEAR_ALS] = {
+		.name = "Clear Light",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_TCS3400,
+		.type = MOTIONSENSE_TYPE_LIGHT,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &tcs3400_drv,
+		.drv_data = &g_tcs3400_data,
+		.port = I2C_PORT_SENSORS,
+		.i2c_spi_addr_flags = TCS3400_I2C_ADDR_FLAGS,
+		.rot_standard_ref = NULL,
+		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
+		.min_frequency = TCS3400_LIGHT_MIN_FREQ,
+		.max_frequency = TCS3400_LIGHT_MAX_FREQ,
+		.config = {
+			/* Run ALS sensor in S0 */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 1000,
+			},
+		},
+	},
+	[RGB_ALS] = {
+		.name = "RGB Light",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_TCS3400,
+		.type = MOTIONSENSE_TYPE_LIGHT_RGB,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &tcs3400_rgb_drv,
+		.drv_data = &g_tcs3400_rgb_data,
+		.rot_standard_ref = NULL,
+		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
+	},
+};
+const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+/* ALS instances when LPC mapping is needed. Each entry directs to a sensor. */
+const struct motion_sensor_t *motion_als_sensors[] = {
+	&motion_sensors[CLEAR_ALS],
+};
+BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
 
 static void power_monitor(void);
 DECLARE_DEFERRED(power_monitor);
 
+/* On ECs without an FPU, the fp_t type is backed by a 32-bit fixed precision
+ * representation that can only store values in the range [-32K, +32K]. Some
+ * intermediary values produced in tcs3400_translate_to_xyz() do not fit in
+ * that range, so we define and use a 64-bit fixed representation instead.
+ */
+typedef int64_t fp64_t;
+#define INT_TO_FP64(x) ((int64_t)(x) << 32)
+#define FP64_TO_INT(x) ((x) >> 32)
+#define FLOAT_TO_FP64(x) ((int64_t)((x) * (float)(1LL << 32)))
+
+__override void tcs3400_translate_to_xyz(struct motion_sensor_t *s,
+					 int32_t *crgb_data, int32_t *xyz_data)
+{
+	struct tcs_saturation_t *sat_p =
+		&(TCS3400_RGB_DRV_DATA(s + 1)->saturation);
+
+	int32_t cur_gain = (1 << (2 * sat_p->again));
+	int32_t integration_time_us =
+		tcs3400_get_integration_time(sat_p->atime);
+
+	fp64_t c_coeff, r_coeff, g_coeff, b_coeff;
+	fp64_t result;
+
+	/* Use different coefficients based on n_interval = (G+B)/C */
+	fp64_t gb_sum = INT_TO_FP64(crgb_data[2]) + INT_TO_FP64(crgb_data[3]);
+	fp64_t n_interval = gb_sum / MAX(crgb_data[0], 1);
+
+	if (n_interval < FLOAT_TO_FP64(0.692)) {
+		const float scale = 799.797;
+
+		c_coeff = FLOAT_TO_FP64(0.009 * scale);
+		r_coeff = FLOAT_TO_FP64(0.056 * scale);
+		g_coeff = FLOAT_TO_FP64(2.735 * scale);
+		b_coeff = FLOAT_TO_FP64(-1.903 * scale);
+	} else if (n_interval < FLOAT_TO_FP64(1.012)) {
+		const float scale = 801.347;
+
+		c_coeff = FLOAT_TO_FP64(0.202 * scale);
+		r_coeff = FLOAT_TO_FP64(-1.1 * scale);
+		g_coeff = FLOAT_TO_FP64(8.692 * scale);
+		b_coeff = FLOAT_TO_FP64(-7.068 * scale);
+	} else {
+		const float scale = 795.574;
+
+		c_coeff = FLOAT_TO_FP64(-0.661 * scale);
+		r_coeff = FLOAT_TO_FP64(1.334 * scale);
+		g_coeff = FLOAT_TO_FP64(1.095 * scale);
+		b_coeff = FLOAT_TO_FP64(-1.821 * scale);
+	}
+
+	/* Multiply each channel by the coefficient and compute the sum.
+	 * Note: int * fp64_t = fp64_t and fp64_t + fp64_t = fp64_t.
+	 */
+	result = crgb_data[0] * c_coeff + crgb_data[1] * r_coeff +
+		 crgb_data[2] * g_coeff + crgb_data[3] * b_coeff;
+
+	/* Adjust for exposure time and sensor gain.
+	 * Note: fp64_t / int = fp64_t.
+	 */
+	result /= MAX(integration_time_us * cur_gain / 1000, 1);
+
+	/* Some C/R/G/B coefficients are negative, so the result could also be
+	 * negative and must be clamped at zero.
+	 *
+	 * The value of xyz_data[1] is stored in a 16 bit integer later on, so
+	 * it must be clamped at INT16_MAX.
+	 */
+	xyz_data[1] = MIN(MAX(FP64_TO_INT(result), 0), INT16_MAX);
+}
+
 static void ppc_interrupt(enum gpio_signal signal)
 {
 	switch (signal) {
@@ -124,8 +323,8 @@ uint16_t tcpc_get_alert_status(void)
 }
 
 /* Called when the charge manager has switched to a new port. */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
 {
 	/* Blink alert if insufficient power per system_can_boot_ap(). */
 	int insufficient_power =
@@ -142,12 +341,12 @@ static int32_t base_5v_power;
  * Power usage for each port as measured or estimated.
  * Units are milliwatts (5v x ma current)
  */
-#define PWR_BASE_LOAD	(5*1335)
-#define PWR_FRONT_HIGH	(5*1603)
-#define PWR_FRONT_LOW	(5*963)
-#define PWR_C_HIGH	(5*3740)
-#define PWR_C_LOW	(5*2090)
-#define PWR_MAX		(5*10000)
+#define PWR_BASE_LOAD (5 * 1335)
+#define PWR_FRONT_HIGH (5 * 1603)
+#define PWR_FRONT_LOW (5 * 963)
+#define PWR_C_HIGH (5 * 3740)
+#define PWR_C_LOW (5 * 2090)
+#define PWR_MAX (5 * 10000)
 
 /*
  * Update the 5V power usage, assuming no throttling,
@@ -212,16 +411,14 @@ static const struct {
 	int current;
 } bj_power[] = {
 	{ /* 0 - 65W (also default) */
-	.voltage = 19000,
-	.current = 3420
-	},
+	  .voltage = 19500,
+	  .current = 3200 },
 	{ /* 1 - 90W */
-	.voltage = 19000,
-	.current = 4740
-	},
+	  .voltage = 19500,
+	  .current = 4600 },
 };
 
-#define ADP_DEBOUNCE_MS		1000  /* Debounce time for BJ plug/unplug */
+#define ADP_DEBOUNCE_MS 1000 /* Debounce time for BJ plug/unplug */
 /* Debounced connection state of the barrel jack */
 static int8_t adp_connected = -1;
 static void adp_connect_deferred(void)
@@ -264,27 +461,29 @@ static void adp_state_init(void)
 	/* Report charge state from the barrel jack. */
 	adp_connect_deferred();
 }
-DECLARE_HOOK(HOOK_INIT, adp_state_init, HOOK_PRIO_CHARGE_MANAGER_INIT + 1);
+DECLARE_HOOK(HOOK_INIT, adp_state_init, HOOK_PRIO_INIT_CHARGE_MANAGER + 1);
 
-
-#include "gpio_list.h" /* Must come after other header files. */
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
 
 /******************************************************************************/
 /* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
+const struct spi_device_t spi_devices[] = {};
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
 /******************************************************************************/
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN]        = { .channel = 5,
-				.flags = PWM_CONFIG_OPEN_DRAIN,
-				.freq = 25000},
-	[PWM_CH_LED_WHITE]  = { .channel = 0,
-				.flags = PWM_CONFIG_ACTIVE_LOW |
-					 PWM_CONFIG_DSLEEP,
-				.freq = 2000 },
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
+	[PWM_CH_LED_RED] = { .channel = 0,
+			     .flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+			     .freq = 2000 },
+	[PWM_CH_LED_WHITE] = { .channel = 2,
+			       .flags = PWM_CONFIG_ACTIVE_LOW |
+					PWM_CONFIG_DSLEEP,
+			       .freq = 2000 },
 };
 
 /******************************************************************************/
@@ -309,29 +508,61 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.flags = TCPC_FLAGS_RESET_ACTIVE_HIGH,
 	},
 };
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_TCPC_0] = {
-		.usb_port = USB_PD_PORT_TCPC_0,
-		.driver = &anx7447_usb_mux_driver,
-		.hpd_update = &anx7447_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_0,
+			.driver = &anx7447_usb_mux_driver,
+			.hpd_update = &anx7447_tcpc_update_hpd_status,
+		},
 	},
 	[USB_PD_PORT_TCPC_1] = {
-		.usb_port = USB_PD_PORT_TCPC_1,
-		.driver = &anx7447_usb_mux_driver,
-		.hpd_update = &anx7447_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_1,
+			.driver = &anx7447_usb_mux_driver,
+			.hpd_update = &anx7447_tcpc_update_hpd_status,
+		},
 	},
 };
 
 /******************************************************************************/
 /* I2C port map configuration */
 const struct i2c_port_t i2c_ports[] = {
-	{"ina",     I2C_PORT_INA,     400, GPIO_I2C0_SCL, GPIO_I2C0_SDA},
-	{"ppc0",    I2C_PORT_PPC0,    400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"ppc1",    I2C_PORT_PPC1,    400, GPIO_I2C2_SCL, GPIO_I2C1_SDA},
-	{"tcpc0",   I2C_PORT_TCPC0,   400, GPIO_I2C3_SCL, GPIO_I2C3_SDA},
-	{"tcpc1",   I2C_PORT_TCPC1,   400, GPIO_I2C4_SCL, GPIO_I2C3_SDA},
-	{"power",   I2C_PORT_POWER,   400, GPIO_I2C5_SCL, GPIO_I2C5_SDA},
-	{"eeprom",  I2C_PORT_EEPROM,  400, GPIO_I2C7_SCL, GPIO_I2C7_SDA},
+	{ .name = "ina",
+	  .port = I2C_PORT_INA,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_SCL,
+	  .sda = GPIO_I2C0_SDA },
+	{ .name = "ppc0",
+	  .port = I2C_PORT_PPC0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "ppc1",
+	  .port = I2C_PORT_PPC1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
+	{ .name = "tcpc1",
+	  .port = I2C_PORT_TCPC1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C4_SCL,
+	  .sda = GPIO_I2C4_SDA },
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 400,
+	  .scl = GPIO_I2C5_SCL,
+	  .sda = GPIO_I2C5_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_I2C7_SCL,
+	  .sda = GPIO_I2C7_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -372,12 +603,6 @@ const struct adc_t adc_channels[] = {
 		.factor_mul = ADC_MAX_VOLT,
 		.factor_div = ADC_READ_MAX + 1,
 	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR_2",
-		.input_ch = NPCX_ADC_CH1,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-	},
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
@@ -388,26 +613,19 @@ const struct temp_sensor_t temp_sensors[] = {
 		.read = get_temp_3v3_30k9_47k_4050b,
 		.idx = ADC_TEMP_SENSOR_1,
 	},
-	[TEMP_SENSOR_2] = {
-		.name = "PP5000",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_2,
-	},
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
 /******************************************************************************/
 /* Wake up pins */
-const enum gpio_signal hibernate_wake_pins[] = {
-};
+const enum gpio_signal hibernate_wake_pins[] = {};
 const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 
 /******************************************************************************/
 /* Physical fans. These are logically separate from pwm_channels. */
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = -1,
 };
@@ -426,30 +644,34 @@ BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
 /******************************************************************************/
 /* MFT channels. These are logically separate from pwm_channels. */
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN },
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 /******************************************************************************/
 /* Thermal control; drive fan based on temperature sensors. */
-const static struct ec_thermal_config thermal_a = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(68),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(78),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(58),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(41),
-	.temp_fan_max = C_TO_K(72),
-};
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_A                \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(78), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+		.temp_fan_off = C_TO_K(41), \
+		.temp_fan_max = C_TO_K(72), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A;
 
 struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1] = thermal_a,
-	[TEMP_SENSOR_2] = thermal_a,
+	[TEMP_SENSOR_1] = THERMAL_A,
 };
 BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
 
@@ -464,6 +686,7 @@ const unsigned int ina3221_count = ARRAY_SIZE(ina3221);
 static uint16_t board_version;
 static uint32_t sku_id;
 static uint32_t fw_config;
+static uint32_t ssfc;
 
 static void cbi_init(void)
 {
@@ -481,8 +704,11 @@ static void cbi_init(void)
 		sku_id = val;
 	if (cbi_get_fw_config(&val) == EC_SUCCESS)
 		fw_config = val;
-	CPRINTS("Board Version: %d, SKU ID: 0x%08x, F/W config: 0x%08x",
-		board_version, sku_id, fw_config);
+	if (cbi_get_ssfc(&val) == EC_SUCCESS)
+		ssfc = val;
+	CPRINTS("Board Version: %d, SKU ID: 0x%08x, "
+		"F/W config: 0x%08x, SSFC: 0x%08x ",
+		board_version, sku_id, fw_config, ssfc);
 }
 DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1);
 
@@ -510,10 +736,21 @@ static void board_init(void)
 
 	gpio_enable_interrupt(GPIO_BJ_ADP_PRESENT_L);
 
+	/* Enable interrupt for the TCS3400 color light sensor */
+	gpio_enable_interrupt(GPIO_ALS_GSENSOR_INT_ODL);
+
 	/* Always claim AC is online, because we don't have a battery. */
 	memmap_batt_flags = host_get_memmap(EC_MEMMAP_BATT_FLAG);
 	*memmap_batt_flags |= EC_BATT_FLAG_AC_PRESENT;
 
+	/* Initial backlight ic setting by ssfc */
+	if (ec_ssfc_get_led_ic() == SSFC_LED_MP3385)
+		mp3385_board_init();
+	else
+		oz554_board_init();
+	gpio_enable_interrupt(GPIO_PANEL_BACKLIGHT_EN);
+	/* set low to disable EC_PCH_RTCRST */
+	gpio_set_level(GPIO_EC_PCH_RTCRST, 0);
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
@@ -532,22 +769,27 @@ static void board_chipset_startup(void)
 		ppc_vbus_source_enable(USB_PD_PORT_TCPC_0, 1);
 	if (ppc_is_sourcing_vbus(USB_PD_PORT_TCPC_1))
 		ppc_vbus_source_enable(USB_PD_PORT_TCPC_1, 1);
+
+	/* set high to enable EDID ROM WP */
+	gpio_set_level(GPIO_EC_EDID_WP_DISABLE_L, 1);
 }
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup,
-	     HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
+
+static void board_chipset_shutdown(void)
+{
+	/* set low to prevent power leakage */
+	gpio_set_level(GPIO_EC_EDID_WP_DISABLE_L, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
 /******************************************************************************/
 /* USB-C PPC Configuration */
 struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.i2c_port = I2C_PORT_PPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	[USB_PD_PORT_TCPC_1] = {
-		.i2c_port = I2C_PORT_PPC1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
+	[USB_PD_PORT_TCPC_0] = { .i2c_port = I2C_PORT_PPC0,
+				 .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+				 .drv = &sn5s330_drv },
+	[USB_PD_PORT_TCPC_1] = { .i2c_port = I2C_PORT_PPC1,
+				 .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+				 .drv = &sn5s330_drv },
 };
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
@@ -574,7 +816,6 @@ static void board_tcpc_init(void)
 	/* Enable other overcurrent interrupts */
 	gpio_enable_interrupt(GPIO_USB_A0_OC_ODL);
 	gpio_enable_interrupt(GPIO_USB_A1_OC_ODL);
-
 }
 /* Make sure this is called after fw_config is initialised */
 DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 2);
@@ -688,7 +929,7 @@ int extpower_is_present(void)
 
 int board_is_c10_gate_enabled(void)
 {
-	return 1;
+	return 0;
 }
 
 void board_enable_s0_rails(int enable)
@@ -697,8 +938,8 @@ void board_enable_s0_rails(int enable)
 
 unsigned int ec_config_get_bj_power(void)
 {
-	unsigned int bj =
-		(fw_config & EC_CFG_BJ_POWER_MASK) >> EC_CFG_BJ_POWER_L;
+	unsigned int bj = (fw_config & EC_CFG_BJ_POWER_MASK) >>
+			  EC_CFG_BJ_POWER_L;
 	/* Out of range value defaults to 0 */
 	if (bj >= ARRAY_SIZE(bj_power))
 		bj = 0;
@@ -710,6 +951,11 @@ unsigned int ec_config_get_thermal_solution(void)
 	return (fw_config & EC_CFG_THERMAL_MASK) >> EC_CFG_THERMAL_L;
 }
 
+unsigned int ec_ssfc_get_led_ic(void)
+{
+	return (ssfc & EC_SSFC_LED_MASK) >> EC_SSFC_LED_L;
+}
+
 /*
  * Power monitoring and management.
  *
@@ -748,29 +994,35 @@ unsigned int ec_config_get_thermal_solution(void)
  *
  *  All measurements are in milliwatts.
  */
-#define THROT_TYPE_A		BIT(0)
-#define THROT_TYPE_C		BIT(1)
-#define THROT_PROCHOT		BIT(2)
+#define THROT_TYPE_A BIT(0)
+#define THROT_TYPE_C BIT(1)
+#define THROT_PROCHOT BIT(2)
 
 /*
  * Power gain if front USB A ports are limited.
  */
-#define POWER_GAIN_TYPE_A	3200
+#define POWER_GAIN_TYPE_A 3200
 /*
  * Power gain if Type C port is limited.
  */
-#define POWER_GAIN_TYPE_C	8800
+#define POWER_GAIN_TYPE_C 8800
 /*
  * Power is averaged over 10 ms, with a reading every 2 ms.
  */
-#define POWER_DELAY_MS		2
-#define POWER_READINGS		(10/POWER_DELAY_MS)
+#define POWER_DELAY_MS 2
+#define POWER_READINGS (10 / POWER_DELAY_MS)
+
+/* PROCHOT_DEFER_OFF is to extend CPU prochot long enough
+ * to pass safety requirement 30 * 2ms = 60 ms
+ */
+#define PROCHOT_DEFER_OFF 30
 
 static void power_monitor(void)
 {
 	static uint32_t current_state;
 	static uint32_t history[POWER_READINGS];
 	static uint8_t index;
+	static uint8_t prochot_linger;
 	int32_t delay;
 	uint32_t new_state = 0, diff;
 	int32_t headroom_5v = PWR_MAX - base_5v_power;
@@ -779,8 +1031,7 @@ static void power_monitor(void)
 	 * If CPU is off or suspended, no need to throttle
 	 * or restrict power.
 	 */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF |
-			     CHIPSET_STATE_SUSPEND)) {
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF | CHIPSET_STATE_SUSPEND)) {
 		/*
 		 * Slow down monitoring, assume no throttling required.
 		 */
@@ -808,7 +1059,7 @@ static void power_monitor(void)
 			 */
 			power = (adc_read_channel(ADC_VBUS) *
 				 adc_read_channel(ADC_PPVAR_IMON)) /
-				 1000;
+				1000;
 			/* Init power table */
 			if (history[0] == 0) {
 				for (i = 0; i < POWER_READINGS; i++)
@@ -835,8 +1086,7 @@ static void power_monitor(void)
 			 * For barrel-jack supplies, the rating can be
 			 * exceeded briefly, so use the average.
 			 */
-			if (charge_manager_get_supplier() ==
-			    CHARGE_SUPPLIER_PD)
+			if (charge_manager_get_supplier() == CHARGE_SUPPLIER_PD)
 				power = max;
 			else
 				power = total / POWER_READINGS;
@@ -871,8 +1121,16 @@ static void power_monitor(void)
 			 * As a last resort, turn on PROCHOT to
 			 * throttle the CPU.
 			 */
-			if (gap <= 0)
+			if (gap <= 0) {
+				prochot_linger = 0;
+				new_state |= THROT_PROCHOT;
+			} else if (prochot_linger < PROCHOT_DEFER_OFF) {
+				/*
+				 * Do not turn off PROCHOT immediately.
+				 */
+				prochot_linger++;
 				new_state |= THROT_PROCHOT;
+			}
 		}
 	}
 	/*
@@ -897,8 +1155,8 @@ static void power_monitor(void)
 		 * Check whether type C is not throttled,
 		 * and is not overcurrent.
 		 */
-		if (!((new_state & THROT_TYPE_C) ||
-		       usbc_0_overcurrent || usbc_1_overcurrent)) {
+		if (!((new_state & THROT_TYPE_C) || usbc_0_overcurrent ||
+		      usbc_1_overcurrent)) {
 			/*
 			 * [1] Type C not in overcurrent, throttle it.
 			 */
@@ -931,12 +1189,17 @@ static void power_monitor(void)
 		gpio_set_level(GPIO_EC_PROCHOT_ODL, prochot);
 	}
 	if (diff & THROT_TYPE_C) {
-		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C)
-			? TYPEC_RP_1A5 : TYPEC_RP_3A0;
+		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C) ?
+						TYPEC_RP_1A5 :
+						TYPEC_RP_3A0;
 
 		ppc_set_vbus_source_current_limit(0, rp);
 		tcpm_select_rp_value(0, rp);
 		pd_update_contract(0);
+
+		ppc_set_vbus_source_current_limit(1, rp);
+		tcpm_select_rp_value(1, rp);
+		pd_update_contract(1);
 	}
 	if (diff & THROT_TYPE_A) {
 		int typea_bc = (new_state & THROT_TYPE_A) ? 1 : 0;
@@ -946,7 +1209,7 @@ static void power_monitor(void)
 	hook_call_deferred(&power_monitor_data, delay);
 }
 
-__override void oz554_board_init(void)
+void oz554_board_init(void)
 {
 	int pin_status = 0;
 
@@ -957,17 +1220,58 @@ __override void oz554_board_init(void)
 	case 0x00:
 		CPRINTS("PANEL_HAN01.10A");
 		oz554_set_config(0, 0xF3);
+		oz554_set_config(2, 0x4C);
+		oz554_set_config(5, 0xB7);
+		break;
+	case 0x02:
+		CPRINTS("PANEL_WF9_SSA2");
+		oz554_set_config(0, 0xF3);
 		oz554_set_config(2, 0x55);
 		oz554_set_config(5, 0x87);
 		break;
+	default:
+		CPRINTS("PANEL UNKNOWN");
+		break;
+	}
+}
+
+void mp3385_board_init(void)
+{
+	int pin_status = 0;
+
+	pin_status |= gpio_get_level(GPIO_PANEL_ID0) << 0;
+	pin_status |= gpio_get_level(GPIO_PANEL_ID1) << 1;
+
+	switch (pin_status) {
+	case 0x00:
+		CPRINTS("PANEL_HAN01.10A");
+		mp3385_set_config(0, 0xF1);
+		mp3385_set_config(2, 0x4C);
+		mp3385_set_config(5, 0xB7);
+		break;
 	case 0x02:
 		CPRINTS("PANEL_WF9_SSA2");
-		oz554_set_config(0, 0xF3);
-		oz554_set_config(2, 0x4C);
-		oz554_set_config(5, 0xB7);
+		mp3385_set_config(0, 0xF1);
+		mp3385_set_config(2, 0x55);
+		mp3385_set_config(5, 0x87);
 		break;
 	default:
 		CPRINTS("PANEL UNKNOWN");
 		break;
 	}
 }
+
+void board_backlight_enable_interrupt(enum gpio_signal signal)
+{
+	switch (ec_ssfc_get_led_ic()) {
+	case SSFC_LED_OZ554:
+		oz554_interrupt(signal);
+		break;
+	case SSFC_LED_MP3385:
+		mp3385_interrupt(signal);
+		break;
+	default:
+		oz554_interrupt(signal);
+		break;
+	}
+}
diff --git a/board/dooly/board.h b/board/dooly/board.h
index 3ea5583766..cb9d12f4ff 100644
--- a/board/dooly/board.h
+++ b/board/dooly/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,15 +11,52 @@
 #undef CONFIG_UART_TX_BUF_SIZE
 #define CONFIG_UART_TX_BUF_SIZE 4096
 
+/*
+ * By default, enable all console messages except HC, ACPI and event:
+ * The sensor stack is generating a lot of activity.
+ */
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
+#undef CONFIG_HOSTCMD_DEBUG_MODE
+#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
+
 /* NPCX7 config */
-#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
-#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
+#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */
+#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */
 
 /* Internal SPI flash on NPCX796FC is 512 kB */
-#define CONFIG_FLASH_SIZE (512 * 1024)
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
 #define CONFIG_SPI_FLASH_REGS
 #define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
 
+/* Sensor */
+/*
+ * Reduce maximal sensor speed: lid accelerometer is not interrupt driven,
+ * so EC does not timestamp sensor events as accurately as interrupt
+ * driven ones.
+ */
+#define CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ 125000
+#define CONFIG_CMD_ACCEL_INFO
+/* Enable sensor fifo, must also define the _SIZE and _THRES */
+#define CONFIG_ACCEL_FIFO
+/* FIFO size is in power of 2. */
+#define CONFIG_ACCEL_FIFO_SIZE 256
+/* Depends on how fast the AP boots and typical ODRs */
+#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
+
+/* BMA253 accelerometer */
+#define CONFIG_ACCEL_BMA255
+#define CONFIG_CMD_ACCELS
+
+/* TCS3400 ALS */
+#define CONFIG_ALS
+#define ALS_COUNT 1
+#define CONFIG_ALS_TCS3400
+#define CONFIG_ALS_TCS3400_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS)
+
+/* Sensors without hardware FIFO are in forced mode */
+#define CONFIG_ACCEL_FORCE_MODE_MASK (BIT(SCREEN_ACCEL) | BIT(CLEAR_ALS))
+
 /* EC Defines */
 #define CONFIG_ADC
 #define CONFIG_BOARD_HAS_RTC_RESET
@@ -27,16 +64,16 @@
 #define CONFIG_DEDICATED_RECOVERY_BUTTON
 #define CONFIG_BOARD_RESET_AFTER_POWER_ON
 #define CONFIG_CRC8
-#define CONFIG_CROS_BOARD_INFO
+#define CONFIG_CBI_EEPROM
 #define CONFIG_EMULATED_SYSRQ
 #undef CONFIG_KEYBOARD_BOOT_KEYS
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
+#define CONFIG_MKBP_INPUT_DEVICES
 #define CONFIG_MKBP_USE_HOST_EVENT
 #undef CONFIG_KEYBOARD_RUNTIME_KEYS
 #undef CONFIG_HIBERNATE
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 #define CONFIG_LED_COMMON
-#undef  CONFIG_LID_SWITCH
+#undef CONFIG_LID_SWITCH
 #define CONFIG_LTO
 #define CONFIG_PWM
 #define CONFIG_VBOOT_EFS2
@@ -45,9 +82,6 @@
 #define CONFIG_VSTORE_SLOT_COUNT 1
 #define CONFIG_SHA256
 
-#define CONFIG_SUPPRESSED_HOST_COMMANDS \
-	EC_CMD_CONSOLE_SNAPSHOT, EC_CMD_CONSOLE_READ, EC_CMD_PD_GET_LOG_ENTRY
-
 /* EC Commands */
 #define CONFIG_CMD_BUTTON
 /* Include CLI command needed to support CCD testing. */
@@ -84,7 +118,7 @@
 #define CONFIG_CPU_PROCHOT_ACTIVE_LOW
 
 /* Dedicated barreljack charger port */
-#undef  CONFIG_DEDICATED_CHARGE_PORT_COUNT
+#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT
 #define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1
 #define DEDICATED_CHARGE_PORT 2
 
@@ -105,21 +139,22 @@
 #define CONFIG_INA3221
 
 /* b/143501304 */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	4000	/* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	2000	/* us */
-#define PD_VCONN_SWAP_DELAY		8000	/* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 4000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 2000 /* us */
+#undef CONFIG_USBC_VCONN_SWAP_DELAY_US
+#define CONFIG_USBC_VCONN_SWAP_DELAY_US 8000 /* us */
 
-#define PD_OPERATING_POWER_MW	CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
-#define PD_MAX_POWER_MW		100000
-#define PD_MAX_CURRENT_MA	5000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
+#define PD_MAX_POWER_MW 100000
+#define PD_MAX_CURRENT_MA 5000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Fan and temp. */
 #define CONFIG_FANS 1
 #undef CONFIG_FAN_INIT_SPEED
 #define CONFIG_FAN_INIT_SPEED 0
 #define CONFIG_TEMP_SENSOR
-#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_ROA_RAILS
+#define CONFIG_TEMP_SENSOR_POWER
 #define CONFIG_THERMISTOR
 #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
 #define CONFIG_THROTTLE_AP
@@ -136,13 +171,12 @@
 #define CONFIG_USB_PD_DECODE_SOP
 #undef CONFIG_USB_CHARGER
 #define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PID		0x5040
+#define CONFIG_USB_PID 0x5040
 #define CONFIG_USB_PD_ALT_MODE
 #define CONFIG_USB_PD_ALT_MODE_DFP
 #define CONFIG_USB_PD_DISCHARGE_PPC
 #define CONFIG_USB_PD_DUAL_ROLE
 #define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT TYPEC_RP_3A0
 #define CONFIG_USB_PD_PORT_MAX_COUNT 2
 #define CONFIG_USB_PD_VBUS_DETECT_PPC
 #define CONFIG_USBC_PPC_SN5S330
@@ -157,10 +191,10 @@
 #define CONFIG_USBC_VCONN
 #define CONFIG_USBC_VCONN_SWAP
 
-#define USB_PD_PORT_TCPC_0	0
+#define USB_PD_PORT_TCPC_0 0
 #define BOARD_TCPC_C0_RESET_HOLD_DELAY ANX74XX_RESET_HOLD_MS
 #define BOARD_TCPC_C0_RESET_POST_DELAY ANX74XX_RESET_HOLD_MS
-#define USB_PD_PORT_TCPC_1	1
+#define USB_PD_PORT_TCPC_1 1
 #define BOARD_TCPC_C1_RESET_HOLD_DELAY ANX74XX_RESET_HOLD_MS
 #define BOARD_TCPC_C1_RESET_POST_DELAY ANX74XX_RESET_HOLD_MS
 
@@ -171,21 +205,23 @@
 
 /* I2C Bus Configuration */
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
-#define I2C_PORT_INA		NPCX_I2C_PORT0_0
-#define I2C_PORT_PPC0		NPCX_I2C_PORT1_0
-#define I2C_PORT_PPC1		NPCX_I2C_PORT2_0
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT3_0
-#define I2C_PORT_TCPC1		NPCX_I2C_PORT4_1
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-#define I2C_PORT_BACKLIGHT	NPCX_I2C_PORT7_0
+#define CONFIG_I2C_CONTROLLER
+#define I2C_PORT_INA NPCX_I2C_PORT0_0
+#define I2C_PORT_SENSORS NPCX_I2C_PORT0_0
+#define I2C_PORT_PPC0 NPCX_I2C_PORT1_0
+#define I2C_PORT_PPC1 NPCX_I2C_PORT2_0
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT3_0
+#define I2C_PORT_TCPC1 NPCX_I2C_PORT4_1
+#define I2C_PORT_POWER NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+#define I2C_PORT_BACKLIGHT NPCX_I2C_PORT7_0
 
 /*
  * LED backlight controller
  */
 #define CONFIG_LED_DRIVER_OZ554
+#define CONFIG_LED_DRIVER_MP3385
 
 #define PP5000_PGOOD_POWER_SIGNAL_MASK POWER_SIGNAL_MASK(PP5000_A_PGOOD)
 
@@ -201,18 +237,18 @@ enum charge_port {
 };
 
 enum adc_channel {
-	ADC_SNS_PP3300,     /* ADC2 */
-	ADC_SNS_PP1050,     /* ADC7 */
-	ADC_VBUS,           /* ADC4 */
-	ADC_PPVAR_IMON,     /* ADC9 */
-	ADC_TEMP_SENSOR_1,  /* ADC0 */
-	ADC_TEMP_SENSOR_2,  /* ADC1 */
+	ADC_SNS_PP3300, /* ADC2 */
+	ADC_SNS_PP1050, /* ADC7 */
+	ADC_VBUS, /* ADC4 */
+	ADC_PPVAR_IMON, /* ADC9 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
 	/* Number of ADC channels */
 	ADC_CH_COUNT
 };
 
 enum pwm_channel {
 	PWM_CH_FAN,
+	PWM_CH_LED_RED,
 	PWM_CH_LED_WHITE,
 	/* Number of PWM channels */
 	PWM_CH_COUNT
@@ -230,12 +266,20 @@ enum mft_channel {
 	MFT_CH_COUNT,
 };
 
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_COUNT
+enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_COUNT };
+
+enum sensor_id {
+	SCREEN_ACCEL = 0,
+	CLEAR_ALS,
+	RGB_ALS,
+	SENSOR_COUNT,
 };
 
+enum ssfc_led_id {
+	SSFC_LED_OZ554 = 0,
+	SSFC_LED_MP3385,
+	SSFC_LED_COUNT,
+};
 
 /* Board specific handlers */
 void board_reset_pd_mcu(void);
@@ -249,52 +293,66 @@ void show_critical_error(void);
 /*
  * Barrel-jack power (4 bits).
  */
-#define EC_CFG_BJ_POWER_L		0
-#define EC_CFG_BJ_POWER_H		3
+#define EC_CFG_BJ_POWER_L 0
+#define EC_CFG_BJ_POWER_H 3
 #define EC_CFG_BJ_POWER_MASK GENMASK(EC_CFG_BJ_POWER_H, EC_CFG_BJ_POWER_L)
 /*
  * USB Connector 4 not present (1 bit) (not used).
  */
-#define EC_CFG_NO_USB4_L		4
-#define EC_CFG_NO_USB4_H		4
+#define EC_CFG_NO_USB4_L 4
+#define EC_CFG_NO_USB4_H 4
 #define EC_CFG_NO_USB4_MASK GENMASK(EC_CFG_NO_USB4_H, EC_CFG_NO_USB4_L)
 /*
  * Thermal solution config (3 bits).
  */
-#define EC_CFG_THERMAL_L		5
-#define EC_CFG_THERMAL_H		7
+#define EC_CFG_THERMAL_L 5
+#define EC_CFG_THERMAL_H 7
 #define EC_CFG_THERMAL_MASK GENMASK(EC_CFG_THERMAL_H, EC_CFG_THERMAL_L)
 
+/*
+ * Second Source Factory Cache (SSFC) CBI field
+ */
+/*
+ * Led driver IC (2 bits).
+ */
+#define EC_SSFC_LED_L 0
+#define EC_SSFC_LED_H 1
+#define EC_SSFC_LED_MASK GENMASK(EC_SSFC_LED_H, EC_SSFC_LED_L)
+
 unsigned int ec_config_get_bj_power(void);
 unsigned int ec_config_get_thermal_solution(void);
+unsigned int ec_ssfc_get_led_ic(void);
+
+void board_backlight_enable_interrupt(enum gpio_signal signal);
 
 #endif /* !__ASSEMBLER__ */
 
 /* Pin renaming */
-#define GPIO_WP_L               GPIO_EC_WP_ODL
-#define GPIO_PP5000_A_PG_OD     GPIO_PG_PP5000_A_OD
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
-#define GPIO_RECOVERY_L         GPIO_EC_RECOVERY_BTN_ODL
-#define GPIO_POWER_BUTTON_L	GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_VOLUME_UP_L	GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L	GPIO_EC_VOLDN_BTN_ODL
-#define GPIO_PCH_WAKE_L		GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L	GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_ENTERING_RW	GPIO_EC_ENTERING_RW
-#define GPIO_SYS_RESET_L	GPIO_SYS_RST_ODL
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_PCH_RTCRST		GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_AC_PRESENT		GPIO_BJ_ADP_PRESENT_L
+#define GPIO_WP_L GPIO_EC_WP_ODL
+#define GPIO_PP5000_A_PG_OD GPIO_PG_PP5000_A_OD
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
+#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_ODL
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_EN_ROA_RAILS
+#define GPIO_AC_PRESENT GPIO_BJ_ADP_PRESENT_L
 
 /*
  * There is no RSMRST input, so alias it to the output. This short-circuits
  * common_intel_x86_handle_rsmrst.
  */
-#define GPIO_RSMRST_L_PGOOD	GPIO_PCH_RSMRST_L
+#define GPIO_PG_EC_RSMRST_ODL GPIO_PCH_RSMRST_L
 
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/dooly/build.mk b/board/dooly/build.mk
index 0f55c45f77..f9096c64ff 100644
--- a/board/dooly/build.mk
+++ b/board/dooly/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/dooly/ec.tasklist b/board/dooly/ec.tasklist
index 5d42008105..cf509f86a2 100644
--- a/board/dooly/ec.tasklist
+++ b/board/dooly/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,6 +9,7 @@
 
 #define CONFIG_TASK_LIST \
 	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
 	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
 	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 2048) \
 	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
diff --git a/board/dooly/gpio.inc b/board/dooly/gpio.inc
index aed8bedd82..d92dedd145 100644
--- a/board/dooly/gpio.inc
+++ b/board/dooly/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,12 +25,12 @@ GPIO_INT(PG_VPRIM_CORE_A_OD,   PIN(2, 3), GPIO_INT_BOTH, power_signal_interrupt)
 GPIO_INT(PG_PP1050_A_OD,       PIN(2, 2), GPIO_INT_BOTH, power_signal_interrupt)
 /* EC output, but also interrupt so this can be polled as a power signal */
 GPIO_INT(EC_PCH_RSMRST_L,      PIN(A, 6), GPIO_OUTPUT | GPIO_INT_F_RISING | GPIO_INT_F_FALLING, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(PG_PP2500_DRAM_U_OD,  PIN(2, 0), GPIO_INT_BOTH, power_signal_interrupt)
 GPIO_INT(PG_PP1200_U_OD,       PIN(2, 1), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, slp_s3_interrupt)
 #endif
 GPIO_INT(PG_PP950_VCCIO_OD,    PIN(1, 7), GPIO_INT_BOTH, power_signal_interrupt)
@@ -42,7 +42,11 @@ GPIO_INT(USB_C0_TCPPC_INT_ODL, PIN(E, 0), GPIO_INT_FALLING, ppc_interrupt)
 GPIO_INT(USB_C0_TCPC_INT_ODL,  PIN(6, 2), GPIO_INT_FALLING, tcpc_alert_event)
 GPIO_INT(USB_C1_TCPPC_INT_ODL, PIN(A, 2), GPIO_INT_FALLING, ppc_interrupt)
 GPIO_INT(USB_C1_TCPC_INT_ODL,  PIN(E, 4), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(PANEL_BACKLIGHT_EN,	PIN(B, 1), GPIO_INT_RISING, backlight_enable_interrupt)
+GPIO_INT(PANEL_BACKLIGHT_EN,	PIN(B, 1), GPIO_INT_RISING, board_backlight_enable_interrupt)
+
+/* Sensor Interrupts */
+GPIO_INT(ALS_GSENSOR_INT_ODL, PIN(9, 6), GPIO_INT_FALLING, tcs3400_interrupt)
+
 /*
  * Directly connected recovery button.
  */
@@ -58,14 +62,14 @@ GPIO_INT(USB_A0_OC_ODL,        PIN(F, 5), GPIO_INT_BOTH, port_ocp_interrupt)
 GPIO_INT(USB_A1_OC_ODL,        PIN(0, 3), GPIO_INT_BOTH, port_ocp_interrupt)
 
 /* Volume button interrupts */
-GPIO_INT(EC_VOLDN_BTN_ODL,     PIN(C, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(EC_VOLDN_BTN_ODL,     PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
 GPIO_INT(EC_VOLUP_BTN_ODL,     PIN(8, 0), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
 
 /* PCH/CPU signals */
 GPIO(EC_PCH_PWROK,             PIN(0, 5), GPIO_OUT_LOW)
 GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
 GPIO(EC_PCH_PWR_BTN_ODL,       PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_ODR_HIGH)
+GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_OUT_LOW)
 GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
 GPIO(EC_PROCHOT_IN_OD,         PIN(3, 4), GPIO_INPUT)
 GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
@@ -130,6 +134,7 @@ ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)                  /* I2C5 */
 ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, 0)                  /* I2C7 */
 
 /* PWM */
+ALTERNATE(PIN_MASK(C, 0x08), 0, MODULE_PWM, 0)                  /* PWM0 - Red Led */
 ALTERNATE(PIN_MASK(C, 0x10), 0, MODULE_PWM, 0)                  /* PWM2 - White Led */
 ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)                  /* PWM5 - Fan 1 */
 ALTERNATE(PIN_MASK(7, 0x08), 0, MODULE_PWM, 0)                  /* TA2 - Fan Tachometer */
@@ -146,12 +151,18 @@ ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)                 /* UART from EC
 GPIO(PANEL_ID0,			PIN(0, 2), GPIO_INPUT)
 GPIO(PANEL_ID1,			PIN(C, 6), GPIO_INPUT)
 
+/*
+ * EDID write protect control
+ * EDID ROM powered by EN_ROA_RAILS, init low to prevent power leakage
+ * high to enable EDID ROM WP
+ * low to disable EDID ROM WP
+ */
+GPIO(EC_EDID_WP_DISABLE_L,	PIN(D, 3), GPIO_OUT_LOW)
+
 /* Unused pins */
-UNUSED(PIN(D, 3))						/* E9  TP55 */
 UNUSED(PIN(9, 5))						/* H10 TP54 */
 UNUSED(PIN(4, 0))						/* E4  TP56 */
 UNUSED(PIN(5, 0))						/* G4 NC */
-UNUSED(PIN(9, 6))						/* M12 TP998 */
 UNUSED(PIN(0, 7))						/* E8  TP991 */
 UNUSED(PIN(0, 6))						/* B10 TP992 */
 UNUSED(PIN(D, 6))						/* F6 */
diff --git a/board/dooly/led.c b/board/dooly/led.c
index eeb52b2844..224db77dc0 100644
--- a/board/dooly/led.c
+++ b/board/dooly/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,42 +19,62 @@
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
 
 /*
  * Due to the CSME-Lite processing, upon startup the CPU transitions through
  * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so
  * delay turning off the LED during suspend/shutdown.
  */
-#define LED_CPU_DELAY_MS	(2000 * MSEC)
+#define LED_CPU_DELAY_MS (2000 * MSEC)
 
-const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 enum led_color {
 	LED_OFF = 0,
+	LED_RED,
 	LED_WHITE,
-
+	LED_AMBER,
 	/* Number of colors, not a color itself */
 	LED_COLOR_COUNT
 };
 
 static int set_color_power(enum led_color color, int duty)
 {
+	int white = 0;
+	int red = 0;
+
 	if (duty < 0 || 100 < duty)
 		return EC_ERROR_UNKNOWN;
 
 	switch (color) {
 	case LED_OFF:
-		pwm_set_duty(PWM_CH_LED_WHITE, 0);
 		break;
 	case LED_WHITE:
-		pwm_set_duty(PWM_CH_LED_WHITE, duty);
+		white = 1;
+		break;
+	case LED_RED:
+		red = 1;
+		break;
+	case LED_AMBER:
+		white = 1;
+		red = 1;
 		break;
 	default:
 		return EC_ERROR_UNKNOWN;
 	}
 
+	if (red)
+		pwm_set_duty(PWM_CH_LED_RED, duty);
+	else
+		pwm_set_duty(PWM_CH_LED_RED, 0);
+
+	if (white)
+		pwm_set_duty(PWM_CH_LED_WHITE, duty);
+	else
+		pwm_set_duty(PWM_CH_LED_WHITE, 0);
+
 	return EC_SUCCESS;
 }
 
@@ -68,9 +88,9 @@ static int set_color(enum ec_led_id id, enum led_color color, int duty)
 	}
 }
 
-#define LED_PULSE_US		(2 * SECOND)
+#define LED_PULSE_US (2 * SECOND)
 /* 40 msec for nice and smooth transition. */
-#define LED_PULSE_TICK_US	(40 * MSEC)
+#define LED_PULSE_TICK_US (40 * MSEC)
 
 /* When pulsing is enabled, brightness is incremented by <duty_inc> every
  * <interval> usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented
@@ -165,6 +185,7 @@ DECLARE_HOOK(HOOK_CHIPSET_RESUME, led_resume, HOOK_PRIO_DEFAULT);
 static void led_init(void)
 {
 	pwm_enable(PWM_CH_LED_WHITE, 1);
+	pwm_enable(PWM_CH_LED_RED, 1);
 }
 DECLARE_HOOK(HOOK_INIT, led_init, HOOK_PRIO_INIT_PWM + 1);
 
@@ -172,7 +193,7 @@ void led_alert(int enable)
 {
 	if (enable) {
 		/* Overwrite the current signal */
-		config_tick(1 * SECOND, 100, LED_WHITE);
+		config_tick(1 * SECOND, 100, LED_RED);
 		led_tick();
 	} else {
 		/* Restore the previous signal */
@@ -189,10 +210,10 @@ void show_critical_error(void)
 {
 	hook_call_deferred(&led_tick_data, -1);
 	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		set_color(EC_LED_ID_POWER_LED, LED_WHITE, 100);
+		set_color(EC_LED_ID_POWER_LED, LED_RED, 100);
 }
 
-static int command_led(int argc, char **argv)
+static int command_led(int argc, const char **argv)
 {
 	enum ec_led_id id = EC_LED_ID_POWER_LED;
 
@@ -204,8 +225,12 @@ static int command_led(int argc, char **argv)
 		ccprintf("o%s\n", led_auto_control_is_enabled(id) ? "ff" : "n");
 	} else if (!strcasecmp(argv[1], "off")) {
 		set_color(id, LED_OFF, 0);
+	} else if (!strcasecmp(argv[1], "red")) {
+		set_color(id, LED_RED, 100);
 	} else if (!strcasecmp(argv[1], "white")) {
 		set_color(id, LED_WHITE, 100);
+	} else if (!strcasecmp(argv[1], "amber")) {
+		set_color(id, LED_AMBER, 100);
 	} else if (!strcasecmp(argv[1], "alert")) {
 		led_alert(1);
 	} else if (!strcasecmp(argv[1], "crit")) {
@@ -216,18 +241,24 @@ static int command_led(int argc, char **argv)
 	return EC_SUCCESS;
 }
 DECLARE_CONSOLE_COMMAND(led, command_led,
-			"[debug|red|green|amber|off|alert|crit]",
+			"[debug|red|white|amber|off|alert|crit]",
 			"Turn on/off LED.");
 
 void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
 {
 	brightness_range[EC_LED_COLOR_WHITE] = 100;
+	brightness_range[EC_LED_COLOR_RED] = 100;
+	brightness_range[EC_LED_COLOR_AMBER] = 100;
 }
 
 int led_set_brightness(enum ec_led_id id, const uint8_t *brightness)
 {
 	if (brightness[EC_LED_COLOR_WHITE])
 		return set_color(id, LED_WHITE, brightness[EC_LED_COLOR_WHITE]);
+	else if (brightness[EC_LED_COLOR_RED])
+		return set_color(id, LED_RED, brightness[EC_LED_COLOR_RED]);
+	else if (brightness[EC_LED_COLOR_AMBER])
+		return set_color(id, LED_AMBER, brightness[EC_LED_COLOR_AMBER]);
 	else
 		return set_color(id, LED_OFF, 0);
 }
diff --git a/board/dooly/usb_pd_policy.c b/board/dooly/usb_pd_policy.c
index 021b18cae7..71396e8797 100644
--- a/board/dooly/usb_pd_policy.c
+++ b/board/dooly/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,16 +12,15 @@
 #include "ec_commands.h"
 #include "gpio.h"
 #include "system.h"
-#include "tcpci.h"
-#include "tcpm.h"
+#include "tcpm/tcpci.h"
+#include "tcpm/tcpm.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
@@ -42,11 +41,6 @@ void pd_power_supply_reset(int port)
 	if (prev_en)
 		pd_set_vbus_discharge(port, 1);
 
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	/* Give back the current quota we are no longer using */
-	charge_manager_source_port(port, 0);
-#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
-
 	/* Notify host of power info change. */
 	pd_send_host_event(PD_EVENT_POWER_CHANGE);
 }
@@ -67,11 +61,6 @@ int pd_set_power_supply_ready(int port)
 	if (rv)
 		return rv;
 
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	/* Ensure we advertise the proper available current quota */
-	charge_manager_source_port(port, 1);
-#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
-
 	/* Notify host of power info change. */
 	pd_send_host_event(PD_EVENT_POWER_CHANGE);
 
diff --git a/board/dooly/vif_override.xml b/board/dooly/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/dooly/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/dragonegg/battery.c b/board/dragonegg/battery.c
deleted file mode 100644
index ae583a0d40..0000000000
--- a/board/dragonegg/battery.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all DragonEgg battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* Panasonic AP1505L Battery Information */
-	[BATTERY_0RD] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP-COS5940",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8800,
-			.voltage_normal		= 7700, /* mV */
-			.voltage_min		= 6000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 60,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_0RD;
diff --git a/board/dragonegg/board.c b/board/dragonegg/board.c
deleted file mode 100644
index 18b4c7c6dc..0000000000
--- a/board/dragonegg/board.c
+++ /dev/null
@@ -1,165 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* DragonEgg board-specific configuration */
-#include "adc.h"
-#include "adc_chip.h"
-#include "button.h"
-#include "common.h"
-#include "charger.h"
-#include "console.h"
-#include "driver/ppc/nx20p348x.h"
-#include "driver/ppc/sn5s330.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "intc.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "spi.h"
-#include "switch.h"
-#include "system.h"
-#include "uart.h"
-#include "usb_pd.h"
-#include "util.h"
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
-
-	switch (signal) {
-	case GPIO_USB_C0_TCPPC_INT_L:
-		sn5s330_interrupt(0);
-		break;
-
-	case GPIO_USB_C2_TCPPC_INT_ODL:
-		nx20p348x_interrupt(2);
-		break;
-
-	default:
-		break;
-	}
-}
-
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	/*
-	 * Since C0/C1 TCPC are embedded within EC, we don't need the PDCMD
-	 * tasks.The (embedded) TCPC status since chip driver code will
-	 * handles its own interrupts and forward the correct events to
-	 * the PD_C0/1 task. See it83xx/intc.c
-	 */
-	switch (signal) {
-	case GPIO_USB_C2_TCPC_INT_ODL:
-		port = 2;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/******************************************************************************/
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	/* Vbus C0 sensing (7.3x voltage divider). PPVAR_USB_C0_VBUS */
-	[ADC_VBUS_C0] = {.name = "VBUS_C0",
-			 .factor_mul = (ADC_MAX_MVOLT * 73) / 10,
-			 .factor_div = ADC_READ_MAX + 1,
-			 .shift = 0,
-			 .channel = CHIP_ADC_CH1},
-	/* Vbus C1 sensing (7.3x voltage divider). PPVAR_USB_C1_VBUS */
-	[ADC_VBUS_C1] = {.name = "VBUS_C1",
-			 .factor_mul = (ADC_MAX_MVOLT * 73) / 10,
-			 .factor_div = ADC_READ_MAX + 1,
-			 .shift = 0,
-			 .channel = CHIP_ADC_CH0},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/******************************************************************************/
-/* SPI devices */
-/* TODO(b/110880394): Fill out correctly (SPI FLASH) */
-const struct spi_device_t spi_devices[] = {
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-/******************************************************************************/
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT]   = { .channel = 0, .flags = 0, .freq_hz = 100 },
-	[PWM_CH_LED_RED]   = { .channel = 2, .flags = PWM_CONFIG_DSLEEP |
-			       PWM_CONFIG_ACTIVE_LOW, .freq_hz = 100 },
-	[PWM_CH_LED_GREEN] = { .channel = 1, .flags = PWM_CONFIG_DSLEEP |
-			       PWM_CONFIG_ACTIVE_LOW, .freq_hz = 100 },
-	[PWM_CH_LED_BLUE]  = { .channel = 3, .flags = PWM_CONFIG_DSLEEP |
-			       PWM_CONFIG_ACTIVE_LOW, .freq_hz = 100 },
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* GPIO to enable/disable the USB Type-A port. */
-const int usb_port_enable[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT] = {
-	GPIO_EN_USB_A_5V,
-};
-
-void board_overcurrent_event(int port)
-{
-	if (port == 0) {
-		/* TODO(b/111281797): When does this get set high again? */
-		gpio_set_level(GPIO_USB_OC_ODL, 0);
-		cprints(CC_USBPD, "p%d: overcurrent!", port);
-	}
-}
-
-static void board_disable_learn_mode(void)
-{
-	/* Disable learn mode after checking to make sure AC is still present */
-	if (extpower_is_present())
-		charger_discharge_on_ac(0);
-}
-DECLARE_DEFERRED(board_disable_learn_mode);
-
-static void board_extpower(void)
-{
-	/*
-	 * For the bq25710 charger, we need the switching converter to remain
-	 * disabled until ~130 msec from when VBUS present to allow the
-	 * converter to be biased properly. Otherwise, there will be a reverse
-	 * buck/boost until the converter is biased. The recommendation is to
-	 * exit learn mode 200 msec after external charger is connected.
-	 *
-	 * TODO(b/112372451): When there are updated versions of the bq25710,
-	 * this set of changes can be removed.
-	 */
-	if (extpower_is_present()) {
-		hook_call_deferred(&board_disable_learn_mode_data, 200 * MSEC);
-	} else {
-		/* Enable charger learn mode */
-		charger_discharge_on_ac(1);
-		/* Cancel any pending call to disable learn mode */
-		hook_call_deferred(&board_disable_learn_mode_data, -1);
-	}
-}
-DECLARE_HOOK(HOOK_AC_CHANGE, board_extpower, HOOK_PRIO_DEFAULT);
-
-/* Initialize board. */
-static void board_init(void)
-{
-	/*
-	 * On EC reboot, need to always set battery learn mode to the correct
-	 * state based on presence of AC.
-	 */
-	board_extpower();
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/dragonegg/board.h b/board/dragonegg/board.h
deleted file mode 100644
index daf6f4c255..0000000000
--- a/board/dragonegg/board.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* DragonEgg board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Baseboard features */
-#include "baseboard.h"
-
-/* Optional features */
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
-#define CONFIG_LOW_POWER_IDLE
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* EC */
-#define CONFIG_BOARD_VERSION_GPIO
-
-/* Keyboard features */
-#define CONFIG_PWM_KBLIGHT
-#define CONFIG_VOLUME_BUTTONS
-
-/* USB and USBC features */
-#define CONFIG_USB_PORT_POWER_SMART
-#undef CONFIG_USB_PORT_POWER_SMART_PORT_COUNT
-#define CONFIG_USB_PORT_POWER_SMART_PORT_COUNT 1
-#define CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY
-#define GPIO_USB1_ILIM_SEL GPIO_EN_USB_A_HIGH_POWER
-
-/* LEDs */
-#define CONFIG_LED_COMMON
-#define CONFIG_LED_PWM_COUNT 1
-#undef CONFIG_LED_PWM_SOC_ON_COLOR
-#define CONFIG_LED_PWM_SOC_ON_COLOR EC_LED_COLOR_BLUE
-#undef CONFIG_LED_PWM_SOC_SUSPEND_COLOR
-#define CONFIG_LED_PWM_SOC_SUSPEND_COLOR EC_LED_COLOR_WHITE
-#define CONFIG_CMD_LEDTEST
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_AC_PRESENT		GPIO_ACOK_OD
-#define GPIO_RSMRST_L_PGOOD	GPIO_PG_EC_RSMRST_ODL
-#define GPIO_PCH_DSW_PWROK	GPIO_EC_PCH_DSW_PWROK
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum adc_channel {
-	ADC_VBUS_C0,
-	ADC_VBUS_C1,
-	ADC_CH_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_LED_RED,
-	PWM_CH_LED_GREEN,
-	PWM_CH_LED_BLUE,
-	PWM_CH_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_0RD,
-	BATTERY_TYPE_COUNT,
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/dragonegg/build.mk b/board/dragonegg/build.mk
deleted file mode 100644
index 6da7e2db93..0000000000
--- a/board/dragonegg/build.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-# -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=it83xx
-CHIP_FAMILY:=it8320
-CHIP_VARIANT:=it8320dx
-BASEBOARD:=dragonegg
-
-board-y=board.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
-board-$(CONFIG_LED_COMMON)+=led.o
diff --git a/board/dragonegg/ec.tasklist b/board/dragonegg/ec.tasklist
deleted file mode 100644
index 7f2b65261f..0000000000
--- a/board/dragonegg/ec.tasklist
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P2, usb_charger_task, 2, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C2, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C2, pd_interrupt_handler_task, 2, TASK_STACK_SIZE)
diff --git a/board/dragonegg/gpio.inc b/board/dragonegg/gpio.inc
deleted file mode 100644
index ac46ccbd6f..0000000000
--- a/board/dragonegg/gpio.inc
+++ /dev/null
@@ -1,131 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(LID_OPEN,        PIN(F, 3), GPIO_INT_BOTH, lid_interrupt)
-GPIO_INT(WP_L,            PIN(F, 1), GPIO_INT_BOTH, switch_interrupt)        /* EC_WP_ODL */
-GPIO_INT(POWER_BUTTON_L,  PIN(E, 2), GPIO_INT_BOTH, power_button_interrupt)  /* MECH_PWR_BTN_ODL */
-GPIO_INT(ACOK_OD,         PIN(E, 3), GPIO_INT_BOTH, extpower_interrupt)
-#ifdef CONFIG_LOW_POWER_IDLE
-/* Used to wake up the EC from Deep Doze mode when writing to console */
-GPIO_INT(UART1_RX,        PIN(B, 0), GPIO_INT_BOTH, uart_deepsleep_interrupt) /* UART_SERVO_TX_EC_RX */
-#endif
-
-/* Power sequencing interrupts */
-GPIO_INT(SLP_S0_L,        PIN(E, 4), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_L,        PIN(I, 4), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-GPIO_INT(SLP_S4_L,        PIN(I, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-GPIO_INT(SLP_SUS_L,       PIN(G, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_RSMRST_ODL,PIN(E, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_DSW_PWROK, PIN(D, 6), GPIO_INT_BOTH, power_signal_interrupt)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_TCPPC_INT_L,   PIN(B, 2), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C2_TCPPC_INT_ODL, PIN(L, 1), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C2_TCPC_INT_ODL,  PIN(K, 6), GPIO_INT_FALLING, tcpc_alert_event)
-
-/* Misc. interrupts */
-GPIO_INT(VOLUME_DOWN_L,    PIN(I, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(VOLUME_UP_L,      PIN(I, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-/* TODO (b:110947310) Uncomment this when sensor task is added to image */
-/* GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(J, 0), GPIO_INT_FALLING | GPIO_SEL_1P8V, lsm6dsm_interrupt) */
-
-#ifdef CONFIG_HOSTCMD_ESPI
-/* enable 1.8v input of EC's espi_reset pin, and then this pin takes effect. */
-GPIO_INT(ESPI_RESET_L,    PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt) /* eSPI_reset# */
-#endif
-
-GPIO(SYS_RESET_L,         PIN(D, 1), GPIO_ODR_HIGH)  /* SYS_RST_ODL */
-GPIO(PCH_WAKE_L,          PIN(D, 5), GPIO_ODR_HIGH)  /* EC_PCH_WAKE_ODL */
-GPIO(PCH_PWRBTN_L,        PIN(B, 6), GPIO_ODR_HIGH)  /* EC_PCH_PWR_BTN_ODL */
-
-/* Power Sequencing Signals */
-/*
- * Both PP5000 and PP3300_TCPC should be powered up whenever the EC is not in
- * hibernate mode. They are enabled by default here and disabled in the
- * board_hibernate() callback when the EC goes into hibernate mode.
- */
-GPIO(EN_PP5000,           PIN(K, 5), GPIO_OUT_HIGH)
-GPIO(EN_PP3300_TCPC,      PIN(E, 6), GPIO_OUT_HIGH)
-GPIO(EN_PP3300_A,         PIN(C, 5), GPIO_OUT_LOW)
-GPIO(EC_PCH_DSW_PWROK,    PIN(L, 7), GPIO_OUT_LOW)
-GPIO(EC_PCH_RSMRST_L,     PIN(H, 0), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,      PIN(D, 0), GPIO_ODR_HIGH)
-GPIO(PP5000_PG_OD,        PIN(F, 0), GPIO_INPUT)
-
-/* SYS_PWROK generation is done by the Dialog power good IC */
-UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
-
-/* USB and USBC Signals */
-GPIO(USB_OC_ODL,          PIN(J, 6), GPIO_ODR_HIGH)
-GPIO(EN_USB_A_5V,         PIN(G, 6), GPIO_OUT_LOW)
-GPIO(EN_USB_A_HIGH_POWER, PIN(D, 4), GPIO_OUT_LOW)
-
-/* BC 1.2 Detection Signals */
-GPIO(USB_C0_BC12_CHG_MAX,     PIN(D, 3), GPIO_INPUT)     /* C0 BC 1.2 CDP signal */
-GPIO(USB_C1_BC12_CHG_MAX,     PIN(B, 7), GPIO_INPUT)     /* C1 BC 1.2 CDP signal */
-GPIO(USB_C2_BC12_CHG_MAX,     PIN(K, 0), GPIO_INPUT)     /* C2 BC 1.2 CDP signal */
-GPIO(USB_C0_BC12_VBUS_ON_ODL, PIN(C, 0), GPIO_ODR_HIGH)  /* C0 BC 1.2 enable signal */
-GPIO(USB_C1_BC12_VBUS_ON_ODL, PIN(E, 5), GPIO_ODR_HIGH)  /* C1 BC 1.2 enable signal */
-GPIO(USB_C2_BC12_VBUS_ON_ODL, PIN(K, 1), GPIO_ODR_HIGH)  /* C2 BC 1.2 enable signal */
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(I2C0_SCL,            PIN(B, 3), GPIO_INPUT)     /* EC_PROG_SCL */
-GPIO(I2C0_SDA,            PIN(B, 4), GPIO_INPUT)     /* EC_PROG_SDA */
-GPIO(I2C1_SCL,            PIN(C, 1), GPIO_INPUT)     /* EC_I2C_SENSOR_KB_BL_SCL */
-GPIO(I2C1_SDA,            PIN(C, 2), GPIO_INPUT)     /* EC_I2C_SENSOR_KB_BL_SDA */
-GPIO(I2C2_SCL,            PIN(F, 6), GPIO_INPUT)     /* EC_I2C_USB_C1C2_SCL */
-GPIO(I2C2_SDA,            PIN(F, 7), GPIO_INPUT)     /* EC_I2C_USB_C1C2_SDA */
-GPIO(I2C4_SCL,            PIN(E, 0), GPIO_INPUT)     /* EC_I2C_USB_C0_SCL */
-GPIO(I2C4_SDA,            PIN(E, 7), GPIO_INPUT)     /* EC_I2C_USB_C0_SDA */
-GPIO(I2C5_SCL,            PIN(A, 4), GPIO_INPUT)     /* EC_I2C_POWER_SCL */
-GPIO(I2C5_SDA,            PIN(A, 5), GPIO_INPUT)     /* EC_I2C_POWER_SDA */
-
-GPIO(CCD_MODE_ODL,        PIN(H, 5), GPIO_INPUT)     /* H1 Case Closed Debug */
-GPIO(CHG_VAP_OTG_EN,      PIN(C, 3), GPIO_OUT_LOW)   /* Charger VAP/OTG Mode_*/
-GPIO(EC_BATT_PRES_ODL,    PIN(H, 3), GPIO_INPUT)
-GPIO(ENTERING_RW,         PIN(G, 0), GPIO_OUT_LOW)   /* EC_ENTERING_RW */
-GPIO(EDP_BKTLEN_OD,       PIN(K, 4), GPIO_ODR_LOW)   /* Backlight Disable */
-GPIO(KB_BL_EN,            PIN(J, 3), GPIO_OUT_LOW)
-/* TODO (b:110947310) Convert this to interrupt when senor support is added */
-GPIO(LID_ACCEL_INT_L,     PIN(J, 1), GPIO_INPUT | GPIO_SEL_1P8V)
-
-/* Board ID */
-GPIO(BOARD_VERSION1,      PIN(H, 4), GPIO_INPUT)     /* Board ID bit0 */
-GPIO(BOARD_VERSION2,      PIN(K, 3), GPIO_INPUT)     /* Board ID bit1 */
-GPIO(BOARD_VERSION3,      PIN(H, 6), GPIO_INPUT)     /* Board ID bit2 */
-
-/* Fan Control Pins (connected to TP only, set as inputs) */
-GPIO(EC_FAN_TACH1,        PIN(J, 2), GPIO_INPUT)
-GPIO(EC_FAN_TACH2,        PIN(D, 7), GPIO_INPUT)
-GPIO(FAN_PWM1,            PIN(A, 6), GPIO_INPUT)
-GPIO(FAN_PWM2,            PIN(A, 7), GPIO_INPUT)
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, 0x03), 0, MODULE_UART, 0)            /* UART from EC to Servo */
-ALTERNATE(PIN_MASK(B, 0x18), 0, MODULE_I2C, 0)             /* I2C0 */
-ALTERNATE(PIN_MASK(C, 0x06), 0, MODULE_I2C, 0)             /* I2C1 */
-ALTERNATE(PIN_MASK(F, 0xC0), 0, MODULE_I2C, 0)             /* I2C2 */
-ALTERNATE(PIN_MASK(E, 0x81), 0, MODULE_I2C, 0)             /* I2C4 */
-ALTERNATE(PIN_MASK(A, 0x30), 0, MODULE_I2C, 0)             /* I2C5 */
-/* Charger_IADP -> ADC15, CHARGER_PSYS -> ADC16 */
-ALTERNATE(PIN_MASK(L, 0x0C), 0, MODULE_ADC, 0)
-/* Temp sensors 1 -> ADC2, 2 -> ADC3, 3 -> ADC13 */
-ALTERNATE(PIN_MASK(I, 0x0C), 0, MODULE_ADC, 0)
-ALTERNATE(PIN_MASK(L, 0x01), 0, MODULE_ADC, 0)
-/* Keyboard Backlight Control */
-ALTERNATE(PIN_MASK(A, 0x01), 0, MODULE_PWM, 0)
-/* 3 Color LED Control */
-ALTERNATE(PIN_MASK(A, 0x0E), 0, MODULE_PWM, 0)
-ALTERNATE(PIN_MASK(I, 0x03), 0, MODULE_ADC, 0)		/* ADC1 & ADC0: ADC_USB_C0_VBUS & ADC_USB_C1_VBUS */
diff --git a/board/dragonegg/led.c b/board/dragonegg/led.c
deleted file mode 100644
index 45e944619d..0000000000
--- a/board/dragonegg/led.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for DragonEgg
- */
-
-#include "common.h"
-#include "ec_commands.h"
-#include "led_pwm.h"
-#include "pwm.h"
-#include "util.h"
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-struct pwm_led led_color_map[EC_LED_COLOR_COUNT] = {
-				/* Red, Green, Blue */
-	[EC_LED_COLOR_RED]    = {  80,   0,   0 },
-	[EC_LED_COLOR_GREEN]  = {   0,  65,   0 },
-	[EC_LED_COLOR_BLUE]   = {   0,   0, 100 },
-	[EC_LED_COLOR_YELLOW] = {  80,  80,   0 },
-	[EC_LED_COLOR_WHITE]  = {  80,  65, 100 },
-	[EC_LED_COLOR_AMBER]  = {  65,  20,   0 },
-};
-
-/*
- * One tri-color LEDs with red, green, and blue channels.
- *
- */
-struct pwm_led pwm_leds[CONFIG_LED_PWM_COUNT] = {
-	[PWM_LED0] = {
-		/* left port LEDs */
-		.ch0 = PWM_CH_LED_RED,
-		.ch1 = PWM_CH_LED_GREEN,
-		.ch2 = PWM_CH_LED_BLUE,
-		.enable = &pwm_enable,
-		.set_duty = &pwm_set_duty,
-	},
-};
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_RED] = 100;
-	brightness_range[EC_LED_COLOR_GREEN] = 100;
-	brightness_range[EC_LED_COLOR_YELLOW] = 100;
-	brightness_range[EC_LED_COLOR_AMBER] = 100;
-	brightness_range[EC_LED_COLOR_BLUE] = 100;
-	brightness_range[EC_LED_COLOR_WHITE] = 100;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	enum pwm_led_id pwm_id;
-
-	/* Convert ec_led_id to pwm_led_id. */
-	if (led_id == EC_LED_ID_POWER_LED)
-		pwm_id = PWM_LED0;
-	else
-		return EC_ERROR_UNKNOWN;
-
-	if (brightness[EC_LED_COLOR_RED])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_RED);
-	else if (brightness[EC_LED_COLOR_GREEN])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_GREEN);
-	else if (brightness[EC_LED_COLOR_BLUE])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_BLUE);
-	else if (brightness[EC_LED_COLOR_YELLOW])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_YELLOW);
-	else if (brightness[EC_LED_COLOR_WHITE])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_WHITE);
-	else if (brightness[EC_LED_COLOR_AMBER])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_AMBER);
-	else
-		/* Otherwise, the "color" is "off". */
-		set_pwm_led_color(pwm_id, -1);
-
-	return EC_SUCCESS;
-}
diff --git a/board/drallion_ish/board.c b/board/drallion_ish/board.c
index c9a683e36d..8cfee8c19d 100644
--- a/board/drallion_ish/board.c
+++ b/board/drallion_ish/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,7 +19,8 @@
 #include "tablet_mode.h"
 #include "task.h"
 
-#include "gpio_list.h" /* has to be included last */
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
 
 /* I2C port map */
 const struct i2c_port_t i2c_ports[] = {
@@ -43,11 +44,9 @@ static struct stprivate_data g_lis2dh_data;
 static struct lis2mdl_private_data lis2mdl_a_data;
 
 /* Matrix to rotate base sensor into standard reference frame */
-const mat33_fp_t base_rot_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_rot_ref = { { 0, FLOAT_TO_FP(1), 0 },
+				  { FLOAT_TO_FP(-1), 0, 0 },
+				  { 0, 0, FLOAT_TO_FP(1) } };
 
 /* Drivers */
 struct motion_sensor_t motion_sensors[] = {
@@ -61,8 +60,6 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_lid_mutex,
 		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_a_data,
 				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_ACCEL_GYRO_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
 		.port = I2C_PORT_SENSOR,
 		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
 		.rot_standard_ref = NULL,
@@ -91,8 +88,6 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_lid_mutex,
 		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_a_data,
 				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_ACCEL_GYRO_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
 		.port = I2C_PORT_SENSOR,
 		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
 		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
diff --git a/board/drallion_ish/board.h b/board/drallion_ish/board.h
index fbe4477a39..d87acc48c3 100644
--- a/board/drallion_ish/board.h
+++ b/board/drallion_ish/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,10 +19,10 @@
 #undef CONFIG_DEBUG_ASSERT
 #define CONFIG_CLOCK_CRYSTAL
 /* EC */
-#define CONFIG_FLASH_SIZE 0x80000
+#define CONFIG_FLASH_SIZE_BYTES 0x80000
 #define CONFIG_FPU
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_CONTROLLER
 
 /* Base sensor: LNG2DM (uses LIS2DH driver) */
 #define CONFIG_ACCEL_LNG2DM
@@ -32,7 +32,6 @@
 #define CONFIG_MAG_LIS2MDL
 #define CONFIG_MAG_CALIBRATE
 
-#define CONFIG_ACCEL_INTERRUPTS
 /* Enable sensor fifo, must also define the _SIZE and _THRES */
 #define CONFIG_ACCEL_FIFO
 /* FIFO size is a power of 2. */
@@ -54,13 +53,12 @@
 
 #define CONFIG_TABLET_MODE
 #define CONFIG_GMR_TABLET_MODE
-#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L
 
 /* DMA paging between SRAM and DRAM */
 #define CONFIG_DMA_PAGING
 
 /* Host command over HECI */
-#define CONFIG_HOSTCMD_HECI
+#define CONFIG_HOST_INTERFACE_HECI
 
 /* I2C ports */
 #define I2C_PORT_SENSOR ISH_I2C0
@@ -74,7 +72,7 @@
 /* Undefined features */
 #undef CONFIG_EXTPOWER
 #undef CONFIG_KEYBOARD_KSO_BASE
-#undef CONFIG_FLASH
+#undef CONFIG_FLASH_CROS
 #undef CONFIG_FMAP
 #undef CONFIG_SWITCH
 
@@ -96,8 +94,8 @@
 #define CONFIG_ISH_PM_D3
 #define CONFIG_ISH_PM_RESET_PREP
 
-#define CONFIG_ISH_D0I2_MIN_USEC        (15*MSEC)
-#define CONFIG_ISH_D0I3_MIN_USEC        (100*MSEC)
+#define CONFIG_ISH_D0I2_MIN_USEC (15 * MSEC)
+#define CONFIG_ISH_D0I3_MIN_USEC (100 * MSEC)
 
 #ifndef __ASSEMBLER__
 
@@ -109,13 +107,7 @@
  * Note: Since we aren't using LPC memory map to transmit sensor data, the
  * order of this enum does not need to be accel, accel, gyro
  */
-enum sensor_id {
-	LID_ACCEL,
-	LID_GYRO,
-	BASE_ACCEL,
-	LID_MAG,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, LID_GYRO, BASE_ACCEL, LID_MAG, SENSOR_COUNT };
 
 #endif /* !__ASSEMBLER__ */
 
diff --git a/board/drallion_ish/build.mk b/board/drallion_ish/build.mk
index 51bd96d339..50d4bf1042 100644
--- a/board/drallion_ish/build.mk
+++ b/board/drallion_ish/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/drallion_ish/ec.tasklist b/board/drallion_ish/ec.tasklist
index a4db486e9a..de7d256324 100644
--- a/board/drallion_ish/ec.tasklist
+++ b/board/drallion_ish/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/drallion_ish/gpio.inc b/board/drallion_ish/gpio.inc
index 93e6752e2b..b1c585b329 100644
--- a/board/drallion_ish/gpio.inc
+++ b/board/drallion_ish/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/dratini/battery.c b/board/dratini/battery.c
index dafd0c9425..5cb57e4ba5 100644
--- a/board/dratini/battery.c
+++ b/board/dratini/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -96,27 +96,3 @@ const struct board_batt_params board_battery_info[] = {
 BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
 
 const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SIMPLO_COS;
-
-/* Lower our input voltage to 5V in S5/G3 when battery is full. */
-static void reduce_input_voltage_when_full(void)
-{
-	int max_pd_voltage_mv;
-	int port;
-
-	if (charge_get_percent() == 100 &&
-	    chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF))
-		max_pd_voltage_mv = 5000;
-	else
-		max_pd_voltage_mv = PD_MAX_VOLTAGE_MV;
-
-	if (pd_get_max_voltage() != max_pd_voltage_mv) {
-		for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++)
-			pd_set_external_voltage_limit(port, max_pd_voltage_mv);
-	}
-}
-DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, reduce_input_voltage_when_full,
-	     HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, reduce_input_voltage_when_full,
-	     HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, reduce_input_voltage_when_full,
-	     HOOK_PRIO_DEFAULT);
diff --git a/board/dratini/board.c b/board/dratini/board.c
index b10c299af1..f109379767 100644
--- a/board/dratini/board.c
+++ b/board/dratini/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,6 @@
 /* Hatch board-specific configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "button.h"
 #include "common.h"
 #include "cros_board_info.h"
@@ -36,16 +35,16 @@
 #include "tablet_mode.h"
 #include "task.h"
 #include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
 #include "thermal.h"
-#include "thermistor.h"
 #include "uart.h"
 #include "usb_charge.h"
 #include "usb_pd.h"
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void check_reboot_deferred(void);
 DECLARE_DEFERRED(check_reboot_deferred);
@@ -113,11 +112,11 @@ static void bc12_interrupt(enum gpio_signal signal)
 {
 	switch (signal) {
 	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
 		break;
 
 	case GPIO_USB_C1_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12, 0);
+		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
 		break;
 
 	default:
@@ -125,20 +124,21 @@ static void bc12_interrupt(enum gpio_signal signal)
 	}
 }
 
-#include "gpio_list.h" /* Must come after other header files. */
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
 
 /******************************************************************************/
 /* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
+const struct spi_device_t spi_devices[] = {};
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
 /******************************************************************************/
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT]   = { .channel = 3, .flags = 0, .freq = 100 },
-	[PWM_CH_FAN] = {.channel = 5, .flags = PWM_CONFIG_OPEN_DRAIN,
-			.freq = 25000},
+	[PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 100 },
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
@@ -158,22 +158,48 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = I2C_PORT_TCPC1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
 		},
 		.drv = &ps8xxx_tcpm_drv,
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+/* Set aux switch to 0xc when CCD enabled on port C0 */
+static int board_anx7447_mux_set_c0(const struct usb_mux *me,
+				    mux_state_t mux_state)
+{
+	int port = me->usb_port;
+	int rv = EC_SUCCESS;
+
+	if (port != USB_PD_PORT_TCPC_0)
+		return rv;
+
+	if (gpio_get_level(GPIO_CCD_MODE_ODL))
+		return rv;
+
+	CPRINTS("C%d: set AUX_SW_SEL=0x%x", port, 0xc);
+	rv = tcpc_write(port, ANX7447_REG_TCPC_AUX_SWITCH, 0xc);
+	if (rv)
+		CPRINTS("C%d: Setting AUX_SW_SEL failed", port);
+
+	return rv;
+}
+
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_TCPC_0] = {
-		.usb_port = USB_PD_PORT_TCPC_0,
-		.driver = &anx7447_usb_mux_driver,
-		.hpd_update = &anx7447_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_0,
+			.driver = &anx7447_usb_mux_driver,
+			.board_set = &board_anx7447_mux_set_c0,
+			.hpd_update = &anx7447_tcpc_update_hpd_status,
+		},
 	},
 	[USB_PD_PORT_TCPC_1] = {
-		.usb_port = USB_PD_PORT_TCPC_1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 	}
 };
 
@@ -202,17 +228,13 @@ static struct bmi_drv_data_t g_bmi160_data;
 static struct accelgyro_saved_data_t g_bma255_data;
 
 /* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, FLOAT_TO_FP(-1), 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
 
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
@@ -292,7 +314,7 @@ unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
@@ -311,68 +333,77 @@ const struct fan_t fans[FAN_CH_COUNT] = {
 /******************************************************************************/
 /* MFT channels. These are logically separate from pwm_channels. */
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN },
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		"TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_2] = {
-		"TEMP_5V_REG", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_3] = {
-		"TEMP_CPU", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_1] = { "TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_2] = { "TEMP_5V_REG", NPCX_ADC_CH1, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_3] = { "TEMP_CPU", NPCX_ADC_CH2, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "5V Reg",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "CPU",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_3},
+	[TEMP_SENSOR_1] = { .name = "Charger",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "5V Reg",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "CPU",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
-
 /* Dratini Temperature sensors */
-const static struct ec_thermal_config thermal_a = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(73),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(70),
-};
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_A                \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(73), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+		.temp_fan_off = C_TO_K(40), \
+		.temp_fan_max = C_TO_K(70), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A;
 
-const static struct ec_thermal_config thermal_b = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(68),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(70),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(55),
-};
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_B                \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(68), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(70), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+		.temp_fan_off = C_TO_K(40), \
+		.temp_fan_max = C_TO_K(55), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_b = THERMAL_B;
 
 struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
 
@@ -395,8 +426,8 @@ bool board_is_convertible(void)
 	 * Dratini is not.
 	 * Unprovisioned SKU 255.
 	 */
-	return sku_id == 21 || sku_id == 22 || sku_id == 23 ||
-		sku_id == 24 || sku_id == 255;
+	return sku_id == 21 || sku_id == 22 || sku_id == 23 || sku_id == 24 ||
+	       sku_id == 255;
 }
 
 static void board_update_sensor_config_from_sku(void)
@@ -452,7 +483,7 @@ bool board_has_kb_backlight(void)
 	 * Unprovisioned: 255
 	 */
 	return sku_id == 2 || sku_id == 3 || sku_id == 5 || sku_id == 8 ||
-		sku_id == 22 || sku_id == 24 || sku_id == 255;
+	       sku_id == 22 || sku_id == 24 || sku_id == 255;
 }
 
 __override uint32_t board_override_feature_flags0(uint32_t flags0)
@@ -470,15 +501,15 @@ __override uint32_t board_override_feature_flags0(uint32_t flags0)
  * The connector has 24 pins total, and there is no pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-		{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-		{0, 7}, {1, 4}, {1, 3}, {1, 6}, {1, 7},
-		{3, 1}, {2, 0}, {1, 5}, {2, 6}, {2, 7},
-		{2, 1}, {2, 4}, {2, 5}, {1, 2}, {2, 3},
-		{2, 2}, {3, 0}, {-1, -1}, {-1, -1}, {-1, -1},
+	{ -1, -1 }, { 0, 5 }, { 1, 1 },	  { 1, 0 },   { 0, 6 },
+	{ 0, 7 },   { 1, 4 }, { 1, 3 },	  { 1, 6 },   { 1, 7 },
+	{ 3, 1 },   { 2, 0 }, { 1, 5 },	  { 2, 6 },   { 2, 7 },
+	{ 2, 1 },   { 2, 4 }, { 2, 5 },	  { 1, 2 },   { 2, 3 },
+	{ 2, 2 },   { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 },
 };
 
 const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 #endif
 
 /* Disable HDMI power while AP is suspended / off */
@@ -507,7 +538,7 @@ __override void board_chipset_forced_shutdown(void)
 	hook_call_deferred(&check_reboot_deferred_data, -1);
 }
 DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_forced_shutdown,
-	HOOK_PRIO_DEFAULT);
+	     HOOK_PRIO_DEFAULT);
 
 static void check_reboot_deferred(void)
 {
diff --git a/board/dratini/board.h b/board/dratini/board.h
index bc45b2ca47..8cdbf0947f 100644
--- a/board/dratini/board.h
+++ b/board/dratini/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,7 +17,7 @@
 #define CONFIG_LED_COMMON
 #define CONFIG_LOW_POWER_IDLE
 
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 
 #undef CONFIG_UART_TX_BUF_SIZE
 #define CONFIG_UART_TX_BUF_SIZE 2048
@@ -30,12 +30,13 @@
  * Dratini's battery takes several seconds to come back out of its disconnect
  * state (~4 seconds, but give it 6 for margin).
  */
-#undef  CONFIG_POWER_BUTTON_INIT_TIMEOUT
+#undef CONFIG_POWER_BUTTON_INIT_TIMEOUT
 #define CONFIG_POWER_BUTTON_INIT_TIMEOUT 6
 
+#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV 5000
+
 /* Sensors */
 /* BMI160 Base accel/gyro */
-#define CONFIG_ACCEL_INTERRUPTS
 #define CONFIG_ACCELGYRO_BMI160
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
@@ -49,7 +50,6 @@
 #define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
 #define CONFIG_LID_ANGLE_UPDATE
 #define CONFIG_GMR_TABLET_MODE
-#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L
 
 /* USB Type C and USB PD defines */
 #define CONFIG_USB_PD_COMM_LOCKED
@@ -93,7 +93,7 @@
 #define CONFIG_FANS 1
 #undef CONFIG_FAN_INIT_SPEED
 #define CONFIG_FAN_INIT_SPEED 10
-#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_A_RAILS
+#define CONFIG_TEMP_SENSOR_POWER
 #define CONFIG_THERMISTOR
 #define CONFIG_THROTTLE_AP
 #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
@@ -112,15 +112,16 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_AC_PRESENT		GPIO_ACOK_OD
-#define GPIO_RSMRST_L_PGOOD	GPIO_PG_EC_RSMRST_L
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L
+#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
 
 #ifndef __ASSEMBLER__
 
@@ -128,9 +129,9 @@
 #include "registers.h"
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_1,	/* ADC0 */
-	ADC_TEMP_SENSOR_2,	/* ADC1 */
-	ADC_TEMP_SENSOR_3,	/* ADC2 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
+	ADC_TEMP_SENSOR_3, /* ADC2 */
 	ADC_CH_COUNT
 };
 
@@ -141,11 +142,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_FAN,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_FAN, PWM_CH_COUNT };
 
 enum fan_channel {
 	FAN_CH_0 = 0,
@@ -173,11 +170,6 @@ enum battery_type {
 	BATTERY_TYPE_COUNT,
 };
 
-#ifdef CONFIG_KEYBOARD_FACTORY_TEST
-extern const int keyboard_factory_scan_pins[][2];
-extern const int keyboard_factory_scan_pins_used;
-#endif
-
 bool board_is_convertible(void);
 
 #endif /* !__ASSEMBLER__ */
diff --git a/board/dratini/build.mk b/board/dratini/build.mk
index 733912454f..13153c1526 100644
--- a/board/dratini/build.mk
+++ b/board/dratini/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/dratini/ec.tasklist b/board/dratini/ec.tasklist
index 4a1024a091..829be2b7c8 100644
--- a/board/dratini/ec.tasklist
+++ b/board/dratini/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/dratini/gpio.inc b/board/dratini/gpio.inc
index 1d83a9813a..bf1a8a431c 100644
--- a/board/dratini/gpio.inc
+++ b/board/dratini/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,10 +17,10 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(PG_EC_RSMRST_L,       PIN(E, 2), GPIO_INT_BOTH, intel_x86_rsmrst_signal_interrupt)
@@ -79,6 +79,9 @@ GPIO(USB_C1_TCPC_RST_ODL,      PIN(3, 2), GPIO_ODR_HIGH)
 GPIO(EN_USB_A_5V,              PIN(3, 5), GPIO_OUT_LOW)
 GPIO(EN_USB_A_LOW_PWR_OD,      PIN(9, 4), GPIO_OUT_LOW)
 
+/* CCD mode line*/
+GPIO(CCD_MODE_ODL,             PIN(E, 5), GPIO_INPUT)
+
 /* Misc Signals */
 GPIO(EC_BATT_PRES_ODL,         PIN(E, 1), GPIO_INPUT)
 GPIO(LED_AMBER_C0_L,           PIN(C, 4), GPIO_OUT_HIGH)        /* Amber C0 port */
diff --git a/board/dratini/led.c b/board/dratini/led.c
index 5cc256b2c5..64d5ed3e4d 100644
--- a/board/dratini/led.c
+++ b/board/dratini/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,9 +11,9 @@
 #include "chipset.h"
 #include "ec_commands.h"
 #include "gpio.h"
+#include "hooks.h"
 #include "host_command.h"
 #include "led_common.h"
-#include "hooks.h"
 
 #define BAT_LED_ON 0
 #define BAT_LED_OFF 1
@@ -24,11 +24,9 @@
 #define LED_TICKS_PER_CYCLE 10
 #define LED_ON_TICKS 5
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_LEFT_LED,
-	EC_LED_ID_RIGHT_LED,
-	EC_LED_ID_POWER_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_LEFT_LED,
+					     EC_LED_ID_RIGHT_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -36,7 +34,7 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static void led_set_color_battery(int port, enum led_color color)
@@ -64,7 +62,7 @@ static void led_set_color_battery(int port, enum led_color color)
 	}
 }
 
-void led_set_color_power(enum ec_led_colors color)
+void led_set_color_power(enum led_color color)
 {
 	switch (color) {
 	case LED_OFF:
@@ -147,7 +145,6 @@ static void led_set_battery(void)
 {
 	static int battery_ticks;
 	static int power_ticks;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
@@ -158,32 +155,34 @@ static void led_set_battery(void)
 	 */
 	if (!board_is_convertible()) {
 		if (chipset_in_state(CHIPSET_STATE_SUSPEND |
-					 CHIPSET_STATE_STANDBY) &&
-			charge_get_state() != PWR_STATE_CHARGE) {
-
+				     CHIPSET_STATE_STANDBY) &&
+		    led_pwr_get_state() != LED_PWRS_CHARGE) {
 			power_ticks++;
 
-			led_set_color_battery(0, power_ticks & 0x4 ?
-						  LED_WHITE : LED_OFF);
-			led_set_color_battery(1, power_ticks & 0x4 ?
-						  LED_WHITE : LED_OFF);
+			led_set_color_battery(0, power_ticks & 0x4 ? LED_WHITE :
+								     LED_OFF);
+			led_set_color_battery(1, power_ticks & 0x4 ? LED_WHITE :
+								     LED_OFF);
 			return;
 		}
 	}
 
 	power_ticks = 0;
 
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
 		/* Always indicate when charging, even in suspend. */
 		set_active_port_color(LED_AMBER);
 		break;
-	case PWR_STATE_DISCHARGE:
+	case LED_PWRS_DISCHARGE:
 		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
 			if (charge_get_percent() < 10)
-				led_set_color_battery(0, (battery_ticks %
-					LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-					LED_WHITE : LED_OFF);
+				led_set_color_battery(
+					0,
+					(battery_ticks % LED_TICKS_PER_CYCLE <
+					 LED_ON_TICKS) ?
+						LED_WHITE :
+						LED_OFF);
 			else
 				led_set_color_battery(0, LED_OFF);
 		}
@@ -191,20 +190,21 @@ static void led_set_battery(void)
 		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
 			led_set_color_battery(1, LED_OFF);
 		break;
-	case PWR_STATE_ERROR:
-		set_active_port_color((battery_ticks & 0x2) ?
-				LED_WHITE : LED_OFF);
+	case LED_PWRS_ERROR:
+		set_active_port_color((battery_ticks & 0x2) ? LED_WHITE :
+							      LED_OFF);
 		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
+	case LED_PWRS_CHARGE_NEAR_FULL:
 		set_active_port_color(LED_WHITE);
 		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			set_active_port_color((battery_ticks %
-				LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-				LED_AMBER : LED_OFF);
-		else
-			set_active_port_color(LED_WHITE);
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		set_active_port_color(LED_WHITE);
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		set_active_port_color(
+			(battery_ticks % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
+				LED_AMBER :
+				LED_OFF);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
@@ -222,9 +222,10 @@ static void led_set_power(void)
 		led_set_color_power(LED_WHITE);
 	else if (chipset_in_state(CHIPSET_STATE_SUSPEND |
 				  CHIPSET_STATE_STANDBY))
-		led_set_color_power((power_tick %
-			LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-			LED_WHITE : LED_OFF);
+		led_set_color_power(
+			(power_tick % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
+				LED_WHITE :
+				LED_OFF);
 	else
 		led_set_color_power(LED_OFF);
 }
diff --git a/board/dratini/vif_override.xml b/board/dratini/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/dratini/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/drawcia/battery.c b/board/drawcia/battery.c
index 3052f93dcc..acc50ca048 100644
--- a/board/drawcia/battery.c
+++ b/board/drawcia/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -33,7 +33,7 @@
  */
 const struct board_batt_params board_battery_info[] = {
 	/* DynaPack CosMX Battery Information */
-	[BATTERY_DANAPACK_COS] = {
+	[BATTERY_DYNAPACK_COS] = {
 		.fuel_gauge = {
 			.manuf_name = "333-2C-DA-A",
 			.ship_mode = {
@@ -45,6 +45,8 @@ const struct board_batt_params board_battery_info[] = {
 				.reg_addr = 0x0,
 				.reg_mask = 0x0006,
 				.disconnect_val = 0x0,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0,
 			},
 		},
 		.batt_info = {
@@ -62,7 +64,7 @@ const struct board_batt_params board_battery_info[] = {
 	},
 
 	/* DynaPack ATL Battery Information */
-	[BATTERY_DANAPACK_ATL] = {
+	[BATTERY_DYNAPACK_ATL] = {
 		.fuel_gauge = {
 			.manuf_name = "333-27-DA-A",
 			.ship_mode = {
@@ -74,6 +76,8 @@ const struct board_batt_params board_battery_info[] = {
 				.reg_addr = 0x0,
 				.reg_mask = 0x0006,
 				.disconnect_val = 0x0,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0,
 			},
 		},
 		.batt_info = {
@@ -91,7 +95,7 @@ const struct board_batt_params board_battery_info[] = {
 	},
 
 	/* DynaPack HIGHPOWER Battery Information */
-	[BATTERY_DANAPACK_HIGHPOWER] = {
+	[BATTERY_DYNAPACK_HIGHPOWER] = {
 		.fuel_gauge = {
 			.manuf_name = "333-2D-0D-A",
 			.ship_mode = {
@@ -103,6 +107,8 @@ const struct board_batt_params board_battery_info[] = {
 				.reg_addr = 0x0,
 				.reg_mask = 0x0006,
 				.disconnect_val = 0x0,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0,
 			},
 		},
 		.batt_info = {
@@ -120,7 +126,7 @@ const struct board_batt_params board_battery_info[] = {
 	},
 
 	/* DynaPack BYD Battery Information */
-	[BATTERY_DANAPACK_BYD] = {
+	[BATTERY_DYNAPACK_BYD] = {
 		.fuel_gauge = {
 			.manuf_name = "333-2E-0D-A",
 			.ship_mode = {
@@ -132,6 +138,8 @@ const struct board_batt_params board_battery_info[] = {
 				.reg_addr = 0x0,
 				.reg_mask = 0x0006,
 				.disconnect_val = 0x0,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0,
 			},
 		},
 		.batt_info = {
@@ -161,6 +169,8 @@ const struct board_batt_params board_battery_info[] = {
 				.reg_addr = 0x0,
 				.reg_mask = 0x0006,
 				.disconnect_val = 0x0,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0,
 			},
 		},
 		.batt_info = {
@@ -190,6 +200,8 @@ const struct board_batt_params board_battery_info[] = {
 				.reg_addr = 0x0,
 				.reg_mask = 0x0006,
 				.disconnect_val = 0x0,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0,
 			},
 		},
 		.batt_info = {
@@ -219,6 +231,8 @@ const struct board_batt_params board_battery_info[] = {
 				.reg_addr = 0x0,
 				.reg_mask = 0x0006,
 				.disconnect_val = 0x0,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0,
 			},
 		},
 		.batt_info = {
@@ -248,6 +262,8 @@ const struct board_batt_params board_battery_info[] = {
 				.reg_addr = 0x0,
 				.reg_mask = 0x0006,
 				.disconnect_val = 0x0,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0,
 			},
 		},
 		.batt_info = {
@@ -263,7 +279,71 @@ const struct board_batt_params board_battery_info[] = {
 			.discharging_max_c = 60,
 		},
 	},
+
+	/* CosMX B00C4473A9D0002 Battery Information */
+	[BATTERY_COS_2] = {
+		.fuel_gauge = {
+			.manuf_name = "333-AC-DA-A",
+			.ship_mode = {
+				.reg_addr = 0x0,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,		/* mV */
+			.voltage_normal = 7700,		/* mV */
+			.voltage_min = 6000,		/* mV */
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
+
+	/* ATL GB-S20-4473A9-01H&020H Battery Information
+	 * Gauge IC : RAJ240045
+	 */
+	[BATTERY_ATL] = {
+		.fuel_gauge = {
+			.manuf_name = "313-B7-0D-A",
+			.ship_mode = {
+				.reg_addr = 0x0,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 0,
+				.reg_addr = 0x43,
+				.reg_mask = 0x0003,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0002,
+				.cfet_off_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,		/* mV */
+			.voltage_normal = 7700,		/* mV */
+			.voltage_min = 6000,		/* mV */
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
 };
 BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
 
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_DANAPACK_COS;
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_DYNAPACK_COS;
diff --git a/board/drawcia/board.c b/board/drawcia/board.c
index fe9bb0e940..78459b6ef5 100644
--- a/board/drawcia/board.c
+++ b/board/drawcia/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,17 +8,19 @@
 #include "adc_chip.h"
 #include "button.h"
 #include "cbi_fw_config.h"
+#include "cbi_ssfc.h"
 #include "charge_manager.h"
-#include "charge_state_v2.h"
+#include "charge_state.h"
 #include "charger.h"
 #include "cros_board_info.h"
 #include "driver/accel_bma2x2.h"
+#include "driver/accel_bma422.h"
 #include "driver/accelgyro_lsm6dsm.h"
 #include "driver/bc12/pi3usb9201.h"
 #include "driver/charger/sm5803.h"
-#include "driver/temp_sensor/thermistor.h"
 #include "driver/tcpm/it83xx_pd.h"
 #include "driver/tcpm/ps8xxx.h"
+#include "driver/temp_sensor/thermistor.h"
 #include "driver/usb_mux/it5205.h"
 #include "gpio.h"
 #include "hooks.h"
@@ -33,7 +35,7 @@
 #include "system.h"
 #include "tablet_mode.h"
 #include "task.h"
-#include "tcpci.h"
+#include "tcpm/tcpci.h"
 #include "temp_sensor.h"
 #include "uart.h"
 #include "usb_charge.h"
@@ -41,7 +43,7 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
 
 #define INT_RECHECK_US 5000
 
@@ -52,13 +54,28 @@ const int usb_port_enable[USB_PORT_COUNT] = {
 	GPIO_EN_USB_A_5V,
 };
 
+__override void board_process_pd_alert(int port)
+{
+	/*
+	 * PD_INT task will process this alert, and that task is only needed on
+	 * C1.
+	 */
+	if (port != 1)
+		return;
+
+	if (gpio_get_level(GPIO_USB_C1_INT_ODL))
+		return;
+
+	sm5803_handle_interrupt(port);
+}
+
 /* C0 interrupt line shared by BC 1.2 and charger */
 static void check_c0_line(void);
 DECLARE_DEFERRED(check_c0_line);
 
 static void notify_c0_chips(void)
 {
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
 	sm5803_interrupt(0);
 }
 
@@ -93,8 +110,7 @@ DECLARE_DEFERRED(check_c1_line);
 static void notify_c1_chips(void)
 {
 	schedule_deferred_pd_interrupt(1);
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12, 0);
-	sm5803_interrupt(1);
+	usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
 }
 
 static void check_c1_line(void)
@@ -121,13 +137,30 @@ static void usb_c1_interrupt(enum gpio_signal s)
 	hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
 }
 
+static void board_enable_hdmi_hpd(int enable)
+{
+	enum fw_config_db db = get_cbi_fw_config_db();
+	int hdmi_hpd = gpio_get_level(GPIO_VOLUP_BTN_ODL_HDMI_HPD);
+
+	if (db == DB_1A_HDMI || db == DB_LTE_HDMI || db == DB_1A_HDMI_LTE) {
+		/* Check if we can report HDMI_HPD signal to CPU  */
+		if (enable)
+			gpio_set_level(GPIO_EC_AP_USB_C1_HDMI_HPD, hdmi_hpd);
+		else
+			gpio_set_level(GPIO_EC_AP_USB_C1_HDMI_HPD, 0);
+	}
+}
+
 static void button_sub_hdmi_hpd_interrupt(enum gpio_signal s)
 {
+	enum fw_config_db db = get_cbi_fw_config_db();
 	int hdmi_hpd = gpio_get_level(GPIO_VOLUP_BTN_ODL_HDMI_HPD);
 
-	if (get_cbi_fw_config_db() == DB_1A_HDMI)
-		gpio_set_level(GPIO_EC_AP_USB_C1_HDMI_HPD, hdmi_hpd);
-	else
+	if (db == DB_1A_HDMI || db == DB_LTE_HDMI || db == DB_1A_HDMI_LTE) {
+		/* Do not report HDMI_HPD signal to CPU when system off. */
+		if (!chipset_in_state(CHIPSET_STATE_ANY_OFF))
+			gpio_set_level(GPIO_EC_AP_USB_C1_HDMI_HPD, hdmi_hpd);
+	} else
 		button_interrupt(s);
 }
 
@@ -149,48 +182,36 @@ static void pen_detect_interrupt(enum gpio_signal s)
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH0
-	},
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH2
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH3
-	},
-	[ADC_SUB_ANALOG] = {
-		.name = "SUB_ANALOG",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH13
-	},
-	[ADC_TEMP_SENSOR_3] = {
-		.name = "TEMP_SENSOR3",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH15
-	},
-	[ADC_TEMP_SENSOR_4] = {
-		.name = "TEMP_SENSOR4",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH16
-	},
+	[ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH0 },
+	[ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH2 },
+	[ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH3 },
+	[ADC_SUB_ANALOG] = { .name = "SUB_ANALOG",
+			     .factor_mul = ADC_MAX_MVOLT,
+			     .factor_div = ADC_READ_MAX + 1,
+			     .shift = 0,
+			     .channel = CHIP_ADC_CH13 },
+	[ADC_TEMP_SENSOR_3] = { .name = "TEMP_SENSOR3",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH15 },
+	[ADC_TEMP_SENSOR_4] = { .name = "TEMP_SENSOR4",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH16 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
@@ -232,26 +253,32 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = I2C_PORT_SUB_USB_C1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
 		},
 		.drv = &ps8xxx_tcpm_drv,
 	},
 };
 
 /* USB Muxes */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+			},
 	},
 	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_SUB_USB_C1,
+				.i2c_addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	},
 };
 
@@ -261,20 +288,17 @@ static struct mutex g_base_mutex;
 
 /* Sensor Data */
 static struct accelgyro_saved_data_t g_bma253_data;
+static struct accelgyro_saved_data_t g_bma422_data;
 static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
 
 /* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, FLOAT_TO_FP(-1), 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
 
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
 /* Drivers */
 struct motion_sensor_t motion_sensors[] = {
@@ -312,8 +336,6 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_base_mutex,
 		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
 				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
 		.port = I2C_PORT_SENSOR,
 		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
 		.rot_standard_ref = &base_standard_ref,
@@ -341,12 +363,10 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_base_mutex,
 		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
 				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
 		.port = I2C_PORT_SENSOR,
 		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
 		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
-		.rot_standard_ref = NULL,
+		.rot_standard_ref = &base_standard_ref,
 		.min_frequency = LSM6DSM_ODR_MIN_VAL,
 		.max_frequency = LSM6DSM_ODR_MAX_VAL,
 	},
@@ -354,11 +374,47 @@ struct motion_sensor_t motion_sensors[] = {
 
 unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
+struct motion_sensor_t bma422_lid_accel = {
+	.name = "Lid Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_BMA422,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_LID,
+	.drv = &bma4_accel_drv,
+	.mutex = &g_lid_mutex,
+	.drv_data = &g_bma422_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = BMA4_I2C_ADDR_PRIMARY,
+	.rot_standard_ref = &lid_standard_ref,
+	.default_range = 2,
+	.min_frequency = BMA4_ACCEL_MIN_FREQ,
+	.max_frequency = BMA4_ACCEL_MAX_FREQ,
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 12500 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+		/* Sensor on in S3 */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 12500 | ROUND_UP_FLAG,
+			.ec_rate = 0,
+		},
+	},
+};
+
+static void board_update_motion_sensor_config(void)
+{
+	if (get_cbi_ssfc_lid_sensor() == SSFC_SENSOR_BMA422)
+		motion_sensors[LID_ACCEL] = bma422_lid_accel;
+}
+
 void board_init(void)
 {
 	int on;
+	enum fw_config_db db = get_cbi_fw_config_db();
 
-	if (get_cbi_fw_config_db() == DB_1A_HDMI) {
+	if (db == DB_1A_HDMI || db == DB_LTE_HDMI || db == DB_1A_HDMI_LTE) {
 		/* Select HDMI option */
 		gpio_set_level(GPIO_HDMI_SEL_L, 0);
 	} else {
@@ -387,6 +443,8 @@ void board_init(void)
 		motion_sensor_count = ARRAY_SIZE(motion_sensors);
 		/* Enable Base Accel interrupt */
 		gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
+
+		board_update_motion_sensor_config();
 	} else {
 		motion_sensor_count = 0;
 		gmr_tablet_switch_disable();
@@ -397,6 +455,13 @@ void board_init(void)
 
 	gpio_enable_interrupt(GPIO_PEN_DET_ODL);
 
+	/* Make sure pen detection is triggered or not at sysjump */
+	if (!gpio_get_level(GPIO_PEN_DET_ODL))
+		gpio_set_level(GPIO_EN_PP5000_PEN, 1);
+
+	/* Make sure HDMI_HPD signal can be reported to CPU at sysjump */
+	board_enable_hdmi_hpd(1);
+
 	/* Charger on the MB will be outputting PROCHOT_ODL and OD CHG_DET */
 	sm5803_configure_gpio0(CHARGER_PRIMARY, GPIO0_MODE_PROCHOT, 1);
 	sm5803_configure_chg_det_od(CHARGER_PRIMARY, 1);
@@ -407,7 +472,8 @@ void board_init(void)
 	}
 
 	/* Turn on 5V if the system is on, otherwise turn it off */
-	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND);
+	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
+			      CHIPSET_STATE_SOFT_OFF);
 	board_power_5v_enable(on);
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
@@ -417,6 +483,9 @@ static void board_resume(void)
 	sm5803_disable_low_power_mode(CHARGER_PRIMARY);
 	if (board_get_charger_chip_count() > 1)
 		sm5803_disable_low_power_mode(CHARGER_SECONDARY);
+
+	/* Enable reporting HDMI_HPD to CPU when system resume */
+	board_enable_hdmi_hpd(1);
 }
 DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_resume, HOOK_PRIO_DEFAULT);
 
@@ -428,6 +497,13 @@ static void board_suspend(void)
 }
 DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_suspend, HOOK_PRIO_DEFAULT);
 
+static void board_shutdown(void)
+{
+	/* Disable reporting HDMI_HPD to CPU at shutdown */
+	board_enable_hdmi_hpd(0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_shutdown, HOOK_PRIO_DEFAULT);
+
 void board_hibernate(void)
 {
 	/*
@@ -445,6 +521,21 @@ __override void board_ocpc_init(struct ocpc_data *ocpc)
 	ocpc->chg_flags[CHARGER_SECONDARY] |= OCPC_NO_ISYS_MEAS_CAP;
 }
 
+__override void board_pulse_entering_rw(void)
+{
+	/*
+	 * On the ITE variants, the EC_ENTERING_RW signal was connected to a pin
+	 * which is active high by default.  This causes Cr50 to think that the
+	 * EC has jumped to its RW image even though this may not be the case.
+	 * The pin is changed to GPIO_EC_ENTERING_RW2.
+	 */
+	gpio_set_level(GPIO_EC_ENTERING_RW, 1);
+	gpio_set_level(GPIO_EC_ENTERING_RW2, 1);
+	usleep(MSEC);
+	gpio_set_level(GPIO_EC_ENTERING_RW, 0);
+	gpio_set_level(GPIO_EC_ENTERING_RW2, 0);
+}
+
 void board_reset_pd_mcu(void)
 {
 	/*
@@ -463,25 +554,39 @@ __override void board_power_5v_enable(int enable)
 
 	if (board_get_charger_chip_count() > 1) {
 		if (sm5803_set_gpio0_level(1, !!enable))
-			CPRINTUSB("Failed to %sable sub rails!", enable ?
-								  "en" : "dis");
+			CPRINTUSB("Failed to %sable sub rails!",
+				  enable ? "en" : "dis");
 	}
 }
 
 __override uint8_t board_get_usb_pd_port_count(void)
 {
-	if (get_cbi_fw_config_db() == DB_1A_HDMI)
+	enum fw_config_db db = get_cbi_fw_config_db();
+
+	if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI ||
+	    db == DB_1A_HDMI_LTE)
 		return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
-	else
+	else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A ||
+		 db == DB_1C_1A_LTE)
 		return CONFIG_USB_PD_PORT_MAX_COUNT;
+
+	ccprints("Unhandled DB configuration: %d", db);
+	return 0;
 }
 
 __override uint8_t board_get_charger_chip_count(void)
 {
-	if (get_cbi_fw_config_db() == DB_1A_HDMI)
+	enum fw_config_db db = get_cbi_fw_config_db();
+
+	if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI ||
+	    db == DB_1A_HDMI_LTE)
 		return CHARGER_NUM - 1;
-	else
+	else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A ||
+		 db == DB_1C_1A_LTE)
 		return CHARGER_NUM;
+
+	ccprints("Unhandled DB configuration: %d", db);
+	return 0;
 }
 
 uint16_t tcpc_get_alert_status(void)
@@ -505,19 +610,17 @@ uint16_t tcpc_get_alert_status(void)
 	return status;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
-			    int charge_mv)
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
 {
-	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
-
 	/* Limit C1 on board version 0 to 2.0 A */
 	if ((board_version == 0) && (port == 1))
-		icl = MIN(icl, 2000);
+		charge_ma = MIN(charge_ma, 2000);
 	/*
 	 * TODO(b/151955431): Characterize the input current limit in case a
 	 * scaling needs to be applied here
 	 */
-	charge_set_input_current_limit(icl, charge_mv);
+	charge_set_input_current_limit(charge_ma, charge_mv);
 }
 
 int board_set_active_charge_port(int port)
@@ -581,40 +684,53 @@ __override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
 	charger_set_otg_current_voltage(port, current, 5000);
 }
 
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq_hz = 10000,
+__override uint16_t board_get_ps8xxx_product_id(int port)
+{
+	/* Drawcia variant doesn't have ps8xxx product in the port 0 */
+	if (port == 0)
+		return 0;
+
+	switch (get_cbi_ssfc_tcpc_p1()) {
+	case SSFC_TCPC_P1_PS8805:
+		return PS8805_PRODUCT_ID;
+	case SSFC_TCPC_P1_DEFAULT:
+	case SSFC_TCPC_P1_PS8705:
+	default:
+		return PS8705_PRODUCT_ID;
 	}
-};
+}
+
+/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
+const struct pwm_t pwm_channels[] = { [PWM_CH_KBLIGHT] = {
+					      .channel = 0,
+					      .flags = PWM_CONFIG_DSLEEP,
+					      .freq_hz = 10000,
+				      } };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
 /* Thermistors */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "Charger",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_3},
-	[TEMP_SENSOR_4] = {.name = "5V regular",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_4},
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "Charger",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
+	[TEMP_SENSOR_4] = { .name = "5V regular",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_4 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
-#ifndef TEST_BUILD
 /* This callback disables keyboard when convertibles are fully open */
-void lid_angle_peripheral_enable(int enable)
+__override void lid_angle_peripheral_enable(int enable)
 {
 	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
 
@@ -638,18 +754,38 @@ void lid_angle_peripheral_enable(int enable)
 			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
 	}
 }
-#endif
 
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
+__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+				       int *ki_div, int *kd, int *kd_div)
 {
 	*kp = 3;
-	*kp_div = 14;
+	*kp_div = 20;
 
 	*ki = 3;
-	*ki_div = 500;
+	*ki_div = 125;
 
 	*kd = 4;
 	*kd_div = 40;
 }
+
+#ifdef CONFIG_KEYBOARD_FACTORY_TEST
+/*
+ * Map keyboard connector pins to EC GPIO pins for factory test.
+ * Pins mapped to {-1, -1} are skipped.
+ * The connector has 24 pins total, and there is no pin 0.
+ */
+const int keyboard_factory_scan_pins[][2] = {
+	{ -1, -1 },	   { GPIO_KSO_H, 4 }, { GPIO_KSO_H, 0 },
+	{ GPIO_KSO_H, 1 }, { GPIO_KSO_H, 3 }, { GPIO_KSO_H, 2 },
+	{ GPIO_KSO_L, 5 }, { GPIO_KSO_L, 6 }, { GPIO_KSO_L, 3 },
+	{ GPIO_KSO_L, 2 }, { GPIO_KSI, 0 },   { GPIO_KSO_L, 1 },
+	{ GPIO_KSO_L, 4 }, { GPIO_KSI, 3 },   { GPIO_KSI, 2 },
+	{ GPIO_KSO_L, 0 }, { GPIO_KSI, 5 },   { GPIO_KSI, 4 },
+	{ GPIO_KSO_L, 7 }, { GPIO_KSI, 6 },   { GPIO_KSI, 7 },
+	{ GPIO_KSI, 1 },   { -1, -1 },	      { -1, -1 },
+	{ -1, -1 },
+};
+
+const int keyboard_factory_scan_pins_used =
+	ARRAY_SIZE(keyboard_factory_scan_pins);
+#endif
diff --git a/board/drawcia/board.h b/board/drawcia/board.h
index fb9a5db542..e696ecf7cd 100644
--- a/board/drawcia/board.h
+++ b/board/drawcia/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,9 +15,6 @@
 #undef GPIO_VOLUME_UP_L
 #define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL_HDMI_HPD
 
-/* System unlocked in early development */
-#define CONFIG_SYSTEM_UNLOCKED
-
 /* Battery */
 #define CONFIG_BATTERY_FUEL_GAUGE
 
@@ -25,24 +22,31 @@
 #define CONFIG_BC12_DETECT_PI3USB9201
 
 /* Charger */
-#define CONFIG_CHARGER_SM5803		/* C0 and C1: Charger */
+#define CONFIG_CHARGE_RAMP_HW
+#define CONFIG_CHARGER_SM5803 /* C0 and C1: Charger */
+#define PD_MAX_VOLTAGE_MV 15000
 #define CONFIG_USB_PD_VBUS_DETECT_CHARGER
 #define CONFIG_USB_PD_5V_CHARGER_CTRL
 #define CONFIG_CHARGER_OTG
-#undef  CONFIG_CHARGER_SINGLE_CHIP
+#undef CONFIG_CHARGER_SINGLE_CHIP
 #define CONFIG_OCPC
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr */
+#define CONFIG_OCPC_DEF_RBATT_MOHMS               \
+	21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr \
+	    */
 
 /* PWM */
 #define CONFIG_PWM
 
 /* Sensors */
-#define CONFIG_ACCEL_BMA255		/* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM	/* Base accel */
+#define CONFIG_ACCEL_BMA255 /* Lid accel */
+#define CONFIG_ACCEL_BMA4XX /* 2nd source Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
 /* Sensors without hardware FIFO are in forced mode */
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
 
-#define CONFIG_ACCEL_INTERRUPTS
+#define CONFIG_CMD_ACCELS
+#define CONFIG_CMD_ACCEL_INFO
+
 /* Enable sensor fifo, must also define the _SIZE and _THRES */
 #define CONFIG_ACCEL_FIFO
 /* Power of 2 - Too large of a fifo causes too much timestamp jitter */
@@ -64,12 +68,16 @@
 #define CONFIG_GMR_TABLET_MODE
 
 /* Keyboard */
+#define CONFIG_KEYBOARD_FACTORY_TEST
 #define CONFIG_PWM_KBLIGHT
 
 /* TCPC */
 #define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP	/* C0: ITE EC TCPC */
-#define CONFIG_USB_PD_TCPM_PS8705	/* C1: PS8705 TCPC*/
+#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0: ITE EC TCPC */
+#define CONFIG_USB_PD_TCPM_MULTI_PS8XXX
+#define CONFIG_USB_PD_TCPM_PS8705 /* C1: PS8705 TCPC */
+#define CONFIG_USB_PD_TCPM_PS8805 /* C1: second source PS8805 TCPC */
+#define CONFIG_USB_PD_TCPM_PS8805_FORCE_DID
 #define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1
 #define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
 #define CONFIG_USB_PD_TCPC_LOW_POWER
@@ -78,11 +86,10 @@
 #define CONFIG_TEMP_SENSOR
 #define CONFIG_THERMISTOR
 #define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_PP3300_A
 
 /* USB Mux and Retimer */
-#define CONFIG_USB_MUX_IT5205			/* C1: ITE Mux */
-#define I2C_PORT_USB_MUX I2C_PORT_USB_C0	/* Required for ITE Mux */
+#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */
 
 /* USB Type A Features */
 #define USB_PORT_COUNT 1
@@ -105,21 +112,16 @@ enum pwm_channel {
 };
 
 /* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
 /* ADC channels */
 enum adc_channel {
-	ADC_VSNS_PP3300_A,     /* ADC0 */
-	ADC_TEMP_SENSOR_1,     /* ADC2 */
-	ADC_TEMP_SENSOR_2,     /* ADC3 */
-	ADC_SUB_ANALOG,        /* ADC13 */
-	ADC_TEMP_SENSOR_3,     /* ADC15 */
-	ADC_TEMP_SENSOR_4,     /* ADC16 */
+	ADC_VSNS_PP3300_A, /* ADC0 */
+	ADC_TEMP_SENSOR_1, /* ADC2 */
+	ADC_TEMP_SENSOR_2, /* ADC3 */
+	ADC_SUB_ANALOG, /* ADC13 */
+	ADC_TEMP_SENSOR_3, /* ADC15 */
+	ADC_TEMP_SENSOR_4, /* ADC16 */
 	ADC_CH_COUNT
 };
 
@@ -133,19 +135,19 @@ enum temp_sensor_id {
 
 /* List of possible batteries */
 enum battery_type {
-	BATTERY_DANAPACK_COS,
-	BATTERY_DANAPACK_ATL,
-	BATTERY_DANAPACK_HIGHPOWER,
-	BATTERY_DANAPACK_BYD,
+	BATTERY_DYNAPACK_COS,
+	BATTERY_DYNAPACK_ATL,
+	BATTERY_DYNAPACK_HIGHPOWER,
+	BATTERY_DYNAPACK_BYD,
 	BATTERY_SAMSUNG_SDI,
 	BATTERY_SIMPLO_COS,
 	BATTERY_SIMPLO_HIGHPOWER,
 	BATTERY_COS,
+	BATTERY_COS_2,
+	BATTERY_ATL,
 	BATTERY_TYPE_COUNT,
 };
 
-int board_is_sourcing_vbus(int port);
-
 #endif /* !__ASSEMBLER__ */
 
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/drawcia/build.mk b/board/drawcia/build.mk
index 00e4e0bb5d..9b862c7624 100644
--- a/board/drawcia/build.mk
+++ b/board/drawcia/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -11,5 +11,5 @@ CHIP_FAMILY:=it8320
 CHIP_VARIANT:=it8320dx
 BASEBOARD:=dedede
 
-board-y=board.o led.o usb_pd_policy.o
+board-y=board.o cbi_ssfc.o led.o usb_pd_policy.o
 board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/drawcia/cbi_ssfc.c b/board/drawcia/cbi_ssfc.c
new file mode 100644
index 0000000000..324ceffb63
--- /dev/null
+++ b/board/drawcia/cbi_ssfc.c
@@ -0,0 +1,41 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi_ssfc.h"
+#include "common.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "hooks.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+/* Cache SSFC on init since we don't expect it to change in runtime */
+static union dedede_cbi_ssfc cached_ssfc;
+BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
+
+static void cbi_ssfc_init(void)
+{
+	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
+		/* Default to 0 when CBI isn't populated */
+		cached_ssfc.raw_value = 0;
+
+	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
+}
+DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
+
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
+{
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
+}
+
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
+{
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
+}
+
+enum ec_ssfc_tcpc_p1 get_cbi_ssfc_tcpc_p1(void)
+{
+	return (enum ec_ssfc_tcpc_p1)cached_ssfc.tcpc_type;
+}
diff --git a/board/drawcia/cbi_ssfc.h b/board/drawcia/cbi_ssfc.h
new file mode 100644
index 0000000000..407efaf3f5
--- /dev/null
+++ b/board/drawcia/cbi_ssfc.h
@@ -0,0 +1,85 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _DEDEDE_CBI_SSFC__H_
+#define _DEDEDE_CBI_SSFC__H_
+
+#include "stdint.h"
+
+/****************************************************************************
+ * Dedede CBI Second Source Factory Cache
+ */
+
+/*
+ * Base Sensor (Bits 0-2)
+ */
+enum ec_ssfc_base_sensor {
+	SSFC_SENSOR_BASE_DEFAULT = 0,
+	SSFC_SENSOR_BMI160 = 1,
+	SSFC_SENSOR_ICM426XX = 2,
+	SSFC_SENSOR_LSM6DSM = 3,
+	SSFC_SENSOR_ICM42607 = 4
+};
+
+/*
+ * Lid Sensor (Bits 3-5)
+ */
+enum ec_ssfc_lid_sensor {
+	SSFC_SENSOR_LID_DEFAULT = 0,
+	SSFC_SENSOR_BMA255 = 1,
+	SSFC_SENSOR_BMA422 = 2,
+};
+
+/*
+ * TCPC Port 1 (Bits 6-7)
+ */
+enum ec_ssfc_tcpc_p1 {
+	SSFC_TCPC_P1_DEFAULT,
+	SSFC_TCPC_P1_PS8705,
+	SSFC_TCPC_P1_PS8805,
+};
+
+/*
+ * Audio Codec Source(Bit 8-10)
+ */
+enum ec_ssfc_audio_codec_source {
+	SSFC_AUDIO_CODEC_DEFAULT = 0,
+	SSFC_AUDIO_CODEC_VD = 1,
+	SSFC_ADUIO_CODEC_VS = 2,
+};
+
+union dedede_cbi_ssfc {
+	struct {
+		uint32_t base_sensor : 3;
+		uint32_t lid_sensor : 3;
+		uint32_t tcpc_type : 2;
+		uint32_t audio_codec_source : 3;
+		uint32_t reserved_2 : 21;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Get the Base sensor type from SSFC_CONFIG.
+ *
+ * @return the Base sensor board type.
+ */
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
+
+/**
+ * Get the Lid sensor type from SSFC_CONFIG.
+ *
+ * @return the Lid sensor board type.
+ */
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
+
+/**
+ * Get the TCPC port 1 type from SSFC_CONFIG.
+ *
+ * @return the TCPC type.
+ */
+enum ec_ssfc_tcpc_p1 get_cbi_ssfc_tcpc_p1(void);
+
+#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/drawcia/ec.tasklist b/board/drawcia/ec.tasklist
index 75181a4531..c3c360febb 100644
--- a/board/drawcia/ec.tasklist
+++ b/board/drawcia/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,13 +12,13 @@
 	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
 	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
 	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, TRENTA_TASK_STACK_SIZE) \
 	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
 	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
 	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, ULTRA_TASK_STACK_SIZE) \
         TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
         TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
         TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/drawcia/gpio.inc b/board/drawcia/gpio.inc
index cfc6b5e867..0c4599911a 100644
--- a/board/drawcia/gpio.inc
+++ b/board/drawcia/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -36,8 +36,8 @@ GPIO_INT(USB_C0_CCSBU_OVP_ODL,	PIN(K, 6), GPIO_INT_FALLING | GPIO_PULL_UP, c0_cc
 /* Other interrupts */
 GPIO_INT(LID_OPEN,		PIN(F, 3), GPIO_INT_BOTH, lid_interrupt)
 GPIO_INT(LID_360_L,		PIN(A, 7), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-GPIO_INT(VOLDN_BTN_ODL,		PIN(I, 6), GPIO_INT_BOTH, button_interrupt)
-GPIO_INT(VOLUP_BTN_ODL_HDMI_HPD,	PIN(I, 7), GPIO_INT_BOTH, button_sub_hdmi_hpd_interrupt)
+GPIO_INT(VOLDN_BTN_ODL,		PIN(I, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(VOLUP_BTN_ODL_HDMI_HPD,	PIN(I, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_sub_hdmi_hpd_interrupt)
 GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(J, 0), GPIO_INT_FALLING | GPIO_SEL_1P8V, lsm6dsm_interrupt)
 GPIO_INT(EC_WP_OD,		PIN(A, 6), GPIO_INT_BOTH, switch_interrupt)
 GPIO_INT(PEN_DET_ODL,		PIN(J, 1), GPIO_INT_BOTH | GPIO_PULL_UP, pen_detect_interrupt)
@@ -98,7 +98,8 @@ GPIO(EC_SUB_IO_2_1, PIN(F, 1), GPIO_INPUT)
 /* Misc */
 GPIO(EN_BL_OD,			PIN(K, 4), GPIO_ODR_LOW)
 GPIO(EC_ENTERING_RW,		PIN(G, 0), GPIO_OUT_LOW)
-GPIO(CCD_MODE_ODL,		PIN(H, 5), GPIO_INPUT)
+GPIO(EC_ENTERING_RW2,		PIN(C, 7), GPIO_OUT_LOW)
+GPIO(CCD_MODE_ODL,		PIN(H, 5), GPIO_ODR_HIGH)
 GPIO(EC_BATTERY_PRES_ODL,	PIN(I, 4), GPIO_INPUT)
 GPIO(EN_KB_BL,			PIN(J, 3), GPIO_OUT_LOW) /* Currently unused */
 GPIO(ECH1_PACKET_MODE,		PIN(H, 1), GPIO_OUT_LOW)
@@ -123,6 +124,12 @@ GPIO(BAT_LED_WHITE_L,	 PIN(A, 2), GPIO_OUT_HIGH)
 GPIO(PWR_LED_WHITE_L,	 PIN(A, 3), GPIO_OUT_HIGH)
 
 /* Alternate functions GPIO definitions */
+/* Keyboard */
+ALTERNATE(PIN_MASK(KSI,   0xFF), 0, MODULE_KEYBOARD_SCAN, 0)		/* KSI0-7 */
+ALTERNATE(PIN_MASK(KSO_H, 0xFF), 0, MODULE_KEYBOARD_SCAN, 0)		/* KSO8-15 */
+ALTERNATE(PIN_MASK(KSO_L, 0xFB), 0, MODULE_KEYBOARD_SCAN, 0)		/* KSO0-1, 3-7 */
+GPIO(EC_KSO_02_INV, PIN(KSO_L, 2), GPIO_OUT_HIGH)			/* KSO2 inverted */
+
 /* UART */
 ALTERNATE(PIN_MASK(B, BIT(0) | BIT(1)), 0, MODULE_UART, 0)		/* UART for debug */
 
diff --git a/board/drawcia/led.c b/board/drawcia/led.c
index 68242180fa..bc4db1d983 100644
--- a/board/drawcia/led.c
+++ b/board/drawcia/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,6 +8,7 @@
 #include "cbi_fw_config.h"
 #include "charge_state.h"
 #include "extpower.h"
+#include "gpio.h"
 #include "hooks.h"
 #include "led_common.h"
 
@@ -17,10 +18,8 @@
 #define POWER_LED_ON 0
 #define POWER_LED_OFF 1
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -28,7 +27,7 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static int led_set_color_battery(enum led_color color)
@@ -52,7 +51,7 @@ static int led_set_color_battery(enum led_color color)
 	return EC_SUCCESS;
 }
 
-static int led_set_color_power(enum ec_led_colors color)
+static int led_set_color_power(enum led_color color)
 {
 	switch (color) {
 	case LED_OFF:
@@ -115,7 +114,6 @@ static void led_set_battery(void)
 {
 	static int battery_ticks;
 	static int power_ticks;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
@@ -126,26 +124,26 @@ static void led_set_battery(void)
 	 */
 	if (get_cbi_fw_config_tablet_mode() == TABLET_MODE_ABSENT) {
 		if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
-			charge_get_state() != PWR_STATE_CHARGE) {
-			led_set_color_battery(power_ticks++ & 0x2 ?
-						  LED_WHITE : LED_OFF);
+		    led_pwr_get_state() != LED_PWRS_CHARGE) {
+			led_set_color_battery(power_ticks++ & 0x2 ? LED_WHITE :
+								    LED_OFF);
 			return;
 		}
 	}
 
 	power_ticks = 0;
 
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
 		led_set_color_battery(LED_AMBER);
 		break;
-	case PWR_STATE_DISCHARGE_FULL:
+	case LED_PWRS_DISCHARGE_FULL:
 		if (extpower_is_present()) {
 			led_set_color_battery(LED_WHITE);
 			break;
 		}
-		/* Intentional fall-through */
-	case PWR_STATE_DISCHARGE:
+		__fallthrough;
+	case LED_PWRS_DISCHARGE:
 		/*
 		 * Blink white light (1 sec on, 1 sec off)
 		 * when battery capacity is less than 10%
@@ -156,19 +154,19 @@ static void led_set_battery(void)
 		else
 			led_set_color_battery(LED_OFF);
 		break;
-	case PWR_STATE_ERROR:
-		led_set_color_battery(
-			(battery_ticks % 0x2) ? LED_WHITE : LED_OFF);
+	case LED_PWRS_ERROR:
+		led_set_color_battery((battery_ticks % 0x2) ? LED_WHITE :
+							      LED_OFF);
 		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
+	case LED_PWRS_CHARGE_NEAR_FULL:
 		led_set_color_battery(LED_WHITE);
 		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			led_set_color_battery(
-				(battery_ticks & 0x2) ? LED_AMBER : LED_OFF);
-		else
-			led_set_color_battery(LED_WHITE);
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		led_set_color_battery(LED_WHITE);
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		led_set_color_battery((battery_ticks & 0x2) ? LED_AMBER :
+							      LED_OFF);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
@@ -185,8 +183,7 @@ static void led_set_power(void)
 	if (chipset_in_state(CHIPSET_STATE_ON))
 		led_set_color_power(LED_WHITE);
 	else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-		led_set_color_power(
-			(power_tick & 0x2) ? LED_WHITE : LED_OFF);
+		led_set_color_power((power_tick & 0x2) ? LED_WHITE : LED_OFF);
 	else
 		led_set_color_power(LED_OFF);
 }
diff --git a/board/drawcia/usb_pd_policy.c b/board/drawcia/usb_pd_policy.c
index 9d53f20047..2433b25431 100644
--- a/board/drawcia/usb_pd_policy.c
+++ b/board/drawcia/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,8 +13,8 @@
 #include "driver/tcpm/tcpci.h"
 #include "usb_pd.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
@@ -38,11 +38,6 @@ void pd_power_supply_reset(int port)
 	if (prev_en)
 		sm5803_set_vbus_disch(port, 1);
 
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	/* Give back the current quota we are no longer using */
-	charge_manager_source_port(port, 0);
-#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
-
 	/* Notify host of power info change. */
 	pd_send_host_event(PD_EVENT_POWER_CHANGE);
 }
@@ -62,11 +57,6 @@ int pd_set_power_supply_ready(int port)
 	/* Provide Vbus */
 	charger_enable_otg_power(port, 1);
 
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	/* Ensure we advertise the proper available current quota */
-	charge_manager_source_port(port, 1);
-#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
-
 	/* Notify host of power info change. */
 	pd_send_host_event(PD_EVENT_POWER_CHANGE);
 
@@ -75,18 +65,7 @@ int pd_set_power_supply_ready(int port)
 
 __override bool pd_check_vbus_level(int port, enum vbus_level level)
 {
-	int vbus_voltage;
-
-	/* If we're unable to speak to the charger, best to guess false */
-	if (charger_get_vbus_voltage(port, &vbus_voltage))
-		return false;
-
-	if (level == VBUS_SAFE0V)
-		return vbus_voltage < PD_V_SAFE0V_MAX;
-	else if (level == VBUS_PRESENT)
-		return vbus_voltage > PD_V_SAFE5V_MIN;
-	else
-		return vbus_voltage < PD_V_SINK_DISCONNECT_MAX;
+	return sm5803_check_vbus_level(port, level);
 }
 
 int pd_snk_is_vbus_provided(int port)
diff --git a/board/drawcia/vif_override.xml b/board/drawcia/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/drawcia/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/drawcia_riscv/battery.c b/board/drawcia_riscv/battery.c
new file mode 100644
index 0000000000..074bc78d58
--- /dev/null
+++ b/board/drawcia_riscv/battery.c
@@ -0,0 +1,349 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "charge_state.h"
+#include "common.h"
+
+/*
+ * Battery info for all drawcia battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	/* DynaPack CosMX Battery Information */
+	[BATTERY_DYNAPACK_COS] = {
+		.fuel_gauge = {
+			.manuf_name = "333-2C-DA-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,	/* mV */
+			.voltage_normal = 7700,
+			.voltage_min = 6000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
+
+	/* DynaPack ATL Battery Information */
+	[BATTERY_DYNAPACK_ATL] = {
+		.fuel_gauge = {
+			.manuf_name = "333-27-DA-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,	/* mV */
+			.voltage_normal = 7700,
+			.voltage_min = 6000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
+
+	/* DynaPack HIGHPOWER Battery Information */
+	[BATTERY_DYNAPACK_HIGHPOWER] = {
+		.fuel_gauge = {
+			.manuf_name = "333-2D-0D-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,	/* mV */
+			.voltage_normal = 7700,
+			.voltage_min = 6000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
+
+	/* DynaPack BYD Battery Information */
+	[BATTERY_DYNAPACK_BYD] = {
+		.fuel_gauge = {
+			.manuf_name = "333-2E-0D-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,	/* mV */
+			.voltage_normal = 7700,
+			.voltage_min = 6000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
+
+	/* Samsung SDI Battery Information */
+	[BATTERY_SAMSUNG_SDI] = {
+		.fuel_gauge = {
+			.manuf_name = "333-54-DA-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,	/* mV */
+			.voltage_normal = 7700,
+			.voltage_min = 6000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
+
+	/* Simplo CosMX Battery Information */
+	[BATTERY_SIMPLO_COS] = {
+		.fuel_gauge = {
+			.manuf_name = "333-1C-DA-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,	/* mV */
+			.voltage_normal = 7700,
+			.voltage_min = 6000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
+
+	/* Simplo HIGHPOWER Battery Information */
+	[BATTERY_SIMPLO_HIGHPOWER] = {
+		.fuel_gauge = {
+			.manuf_name = "333-1D-DA-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,	/* mV */
+			.voltage_normal = 7700,
+			.voltage_min = 6000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
+
+	/* CosMX Battery Information */
+	[BATTERY_COS] = {
+		.fuel_gauge = {
+			.manuf_name = "333-AC-0D-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,	/* mV */
+			.voltage_normal = 7700,
+			.voltage_min = 6000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
+
+	/* CosMX B00C4473A9D0002 Battery Information */
+	[BATTERY_COS_2] = {
+		.fuel_gauge = {
+			.manuf_name = "333-AC-DA-A",
+			.ship_mode = {
+				.reg_addr = 0x0,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,		/* mV */
+			.voltage_normal = 7700,		/* mV */
+			.voltage_min = 6000,		/* mV */
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
+
+	/* ATL GB-S20-4473A9-01H&020H Battery Information
+	 * Gauge IC : RAJ240045
+	 */
+	[BATTERY_ATL] = {
+		.fuel_gauge = {
+			.manuf_name = "313-B7-0D-A",
+			.ship_mode = {
+				.reg_addr = 0x0,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 0,
+				.reg_addr = 0x43,
+				.reg_mask = 0x0003,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0002,
+				.cfet_off_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,		/* mV */
+			.voltage_normal = 7700,		/* mV */
+			.voltage_min = 6000,		/* mV */
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_DYNAPACK_COS;
diff --git a/board/drawcia_riscv/board.c b/board/drawcia_riscv/board.c
new file mode 100644
index 0000000000..d8d0189635
--- /dev/null
+++ b/board/drawcia_riscv/board.c
@@ -0,0 +1,707 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Drawcia board-specific configuration */
+
+#include "adc_chip.h"
+#include "button.h"
+#include "cbi_fw_config.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "cros_board_info.h"
+#include "driver/accel_bma2x2.h"
+#include "driver/accelgyro_lsm6dsm.h"
+#include "driver/bc12/pi3usb9201.h"
+#include "driver/charger/sm5803.h"
+#include "driver/tcpm/it83xx_pd.h"
+#include "driver/tcpm/ps8xxx.h"
+#include "driver/temp_sensor/thermistor.h"
+#include "driver/usb_mux/it5205.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "intc.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "switch.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "tcpm/it8xxx2_pd_public.h"
+#include "tcpm/tcpci.h"
+#include "temp_sensor.h"
+#include "uart.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+
+#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+
+#define INT_RECHECK_US 5000
+
+uint32_t board_version;
+
+/* GPIO to enable/disable the USB Type-A port. */
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_USB_A_5V,
+};
+
+__override void board_process_pd_alert(int port)
+{
+	/*
+	 * PD_INT task will process this alert, and that task is only needed on
+	 * C1.
+	 */
+	if (port != 1)
+		return;
+
+	if (gpio_get_level(GPIO_USB_C1_INT_ODL))
+		return;
+
+	sm5803_handle_interrupt(port);
+}
+
+/* C0 interrupt line shared by BC 1.2 and charger */
+static void check_c0_line(void);
+DECLARE_DEFERRED(check_c0_line);
+
+static void notify_c0_chips(void)
+{
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+	sm5803_interrupt(0);
+}
+
+static void check_c0_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		notify_c0_chips();
+		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+	}
+}
+
+static void usb_c0_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c0_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c0_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+}
+
+/* C1 interrupt line shared by BC 1.2, TCPC, and charger */
+static void check_c1_line(void);
+DECLARE_DEFERRED(check_c1_line);
+
+static void notify_c1_chips(void)
+{
+	schedule_deferred_pd_interrupt(1);
+	usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+}
+
+static void check_c1_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips.
+	 */
+	if (!gpio_get_level(GPIO_USB_C1_INT_ODL)) {
+		notify_c1_chips();
+		hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
+	}
+}
+
+static void usb_c1_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c1_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c1_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
+}
+
+static void button_sub_hdmi_hpd_interrupt(enum gpio_signal s)
+{
+	enum fw_config_db db = get_cbi_fw_config_db();
+	int hdmi_hpd = gpio_get_level(GPIO_VOLUP_BTN_ODL_HDMI_HPD);
+
+	if (db == DB_1A_HDMI || db == DB_LTE_HDMI || db == DB_1A_HDMI_LTE)
+		gpio_set_level(GPIO_EC_AP_USB_C1_HDMI_HPD, hdmi_hpd);
+	else
+		button_interrupt(s);
+}
+
+static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
+{
+	cprints(CC_USBPD, "C0: CC OVP, SBU OVP, or thermal event");
+	pd_handle_cc_overvoltage(0);
+}
+
+static void pen_detect_interrupt(enum gpio_signal s)
+{
+	int pen_detect = !gpio_get_level(GPIO_PEN_DET_ODL);
+
+	gpio_set_level(GPIO_EN_PP5000_PEN, pen_detect);
+}
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	[ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH0 },
+	[ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH2 },
+	[ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH3 },
+	[ADC_SUB_ANALOG] = { .name = "SUB_ANALOG",
+			     .factor_mul = ADC_MAX_MVOLT,
+			     .factor_div = ADC_READ_MAX + 1,
+			     .shift = 0,
+			     .channel = CHIP_ADC_CH13 },
+	[ADC_TEMP_SENSOR_3] = { .name = "TEMP_SENSOR3",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH15 },
+	[ADC_TEMP_SENSOR_4] = { .name = "TEMP_SENSOR4",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH16 },
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* BC 1.2 chips */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	{
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+		.flags = PI3USB9201_ALWAYS_POWERED,
+	},
+	{
+		.i2c_port = I2C_PORT_SUB_USB_C1,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+		.flags = PI3USB9201_ALWAYS_POWERED,
+	},
+};
+
+/* Charger chips */
+const struct charger_config_t chg_chips[] = {
+	[CHARGER_PRIMARY] = {
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = SM5803_ADDR_CHARGER_FLAGS,
+		.drv = &sm5803_drv,
+	},
+	[CHARGER_SECONDARY] = {
+		.i2c_port = I2C_PORT_SUB_USB_C1,
+		.i2c_addr_flags = SM5803_ADDR_CHARGER_FLAGS,
+		.drv = &sm5803_drv,
+	},
+};
+
+/* TCPCs */
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_EMBEDDED,
+		.drv = &it8xxx2_tcpm_drv,
+	},
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_SUB_USB_C1,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+	},
+};
+
+/* USB Muxes */
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+			},
+	},
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_SUB_USB_C1,
+				.i2c_addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
+	},
+};
+
+/* Sensor Mutexes */
+static struct mutex g_lid_mutex;
+static struct mutex g_base_mutex;
+
+/* Sensor Data */
+static struct accelgyro_saved_data_t g_bma253_data;
+static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
+
+/* Matrix to rotate accelrator into standard reference frame */
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, FLOAT_TO_FP(-1), 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
+
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
+
+/* Drivers */
+struct motion_sensor_t motion_sensors[] = {
+	[LID_ACCEL] = {
+		.name = "Lid Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMA255,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &bma2x2_accel_drv,
+		.mutex = &g_lid_mutex,
+		.drv_data = &g_bma253_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
+		.rot_standard_ref = &lid_standard_ref,
+		.default_range = 2,
+		.min_frequency = BMA255_ACCEL_MIN_FREQ,
+		.max_frequency = BMA255_ACCEL_MAX_FREQ,
+		.config = {
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+		},
+	},
+	[BASE_ACCEL] = {
+		.name = "Base Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LSM6DSM,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &lsm6dsm_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
+				MOTIONSENSE_TYPE_ACCEL),
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
+		.rot_standard_ref = &base_standard_ref,
+		.default_range = 4,  /* g */
+		.min_frequency = LSM6DSM_ODR_MIN_VAL,
+		.max_frequency = LSM6DSM_ODR_MAX_VAL,
+		.config = {
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 13000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+		},
+	},
+	[BASE_GYRO] = {
+		.name = "Base Gyro",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LSM6DSM,
+		.type = MOTIONSENSE_TYPE_GYRO,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &lsm6dsm_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
+				MOTIONSENSE_TYPE_GYRO),
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
+		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = LSM6DSM_ODR_MIN_VAL,
+		.max_frequency = LSM6DSM_ODR_MAX_VAL,
+	},
+};
+
+unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+void board_init(void)
+{
+	int on;
+	enum fw_config_db db = get_cbi_fw_config_db();
+
+	if (db == DB_1A_HDMI || db == DB_LTE_HDMI || db == DB_1A_HDMI_LTE) {
+		/* Select HDMI option */
+		gpio_set_level(GPIO_HDMI_SEL_L, 0);
+	} else {
+		/* Select AUX option */
+		gpio_set_level(GPIO_HDMI_SEL_L, 1);
+	}
+
+	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_INT_ODL);
+
+	/* Store board version for use in determining charge limits */
+	cbi_get_board_version(&board_version);
+
+	/*
+	 * If interrupt lines are already low, schedule them to be processed
+	 * after inits are completed.
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL))
+		hook_call_deferred(&check_c0_line_data, 0);
+	if (!gpio_get_level(GPIO_USB_C1_INT_ODL))
+		hook_call_deferred(&check_c1_line_data, 0);
+
+	gpio_enable_interrupt(GPIO_USB_C0_CCSBU_OVP_ODL);
+
+	if (get_cbi_fw_config_tablet_mode() == TABLET_MODE_PRESENT) {
+		motion_sensor_count = ARRAY_SIZE(motion_sensors);
+		/* Enable Base Accel interrupt */
+		gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
+	} else {
+		motion_sensor_count = 0;
+		gmr_tablet_switch_disable();
+		/* Base accel is not stuffed, don't allow line to float */
+		gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L,
+			       GPIO_INPUT | GPIO_PULL_DOWN);
+	}
+
+	gpio_enable_interrupt(GPIO_PEN_DET_ODL);
+
+	/* Make sure pen detection is triggered or not at sysjump */
+	if (!gpio_get_level(GPIO_PEN_DET_ODL))
+		gpio_set_level(GPIO_EN_PP5000_PEN, 1);
+
+	/* Charger on the MB will be outputting PROCHOT_ODL and OD CHG_DET */
+	sm5803_configure_gpio0(CHARGER_PRIMARY, GPIO0_MODE_PROCHOT, 1);
+	sm5803_configure_chg_det_od(CHARGER_PRIMARY, 1);
+
+	if (board_get_charger_chip_count() > 1) {
+		/* Charger on the sub-board will be a push-pull GPIO */
+		sm5803_configure_gpio0(CHARGER_SECONDARY, GPIO0_MODE_OUTPUT, 0);
+	}
+
+	/* Turn on 5V if the system is on, otherwise turn it off */
+	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
+			      CHIPSET_STATE_SOFT_OFF);
+	board_power_5v_enable(on);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+static void board_resume(void)
+{
+	sm5803_disable_low_power_mode(CHARGER_PRIMARY);
+	if (board_get_charger_chip_count() > 1)
+		sm5803_disable_low_power_mode(CHARGER_SECONDARY);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_resume, HOOK_PRIO_DEFAULT);
+
+static void board_suspend(void)
+{
+	sm5803_enable_low_power_mode(CHARGER_PRIMARY);
+	if (board_get_charger_chip_count() > 1)
+		sm5803_enable_low_power_mode(CHARGER_SECONDARY);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_suspend, HOOK_PRIO_DEFAULT);
+
+void board_hibernate(void)
+{
+	/*
+	 * Put all charger ICs present into low power mode before entering
+	 * z-state.
+	 */
+	sm5803_hibernate(CHARGER_PRIMARY);
+	if (board_get_charger_chip_count() > 1)
+		sm5803_hibernate(CHARGER_SECONDARY);
+}
+
+__override void board_ocpc_init(struct ocpc_data *ocpc)
+{
+	/* There's no provision to measure Isys */
+	ocpc->chg_flags[CHARGER_SECONDARY] |= OCPC_NO_ISYS_MEAS_CAP;
+}
+
+__override void board_pulse_entering_rw(void)
+{
+	/*
+	 * On the ITE variants, the EC_ENTERING_RW signal was connected to a pin
+	 * which is active high by default.  This causes Cr50 to think that the
+	 * EC has jumped to its RW image even though this may not be the case.
+	 * The pin is changed to GPIO_EC_ENTERING_RW2.
+	 */
+	gpio_set_level(GPIO_EC_ENTERING_RW, 1);
+	gpio_set_level(GPIO_EC_ENTERING_RW2, 1);
+	usleep(MSEC);
+	gpio_set_level(GPIO_EC_ENTERING_RW, 0);
+	gpio_set_level(GPIO_EC_ENTERING_RW2, 0);
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * Nothing to do.  TCPC C0 is internal, TCPC C1 reset pin is not
+	 * connected to the EC.
+	 */
+}
+
+__override void board_power_5v_enable(int enable)
+{
+	/*
+	 * Motherboard has a GPIO to turn on the 5V regulator, but the sub-board
+	 * sets it through the charger GPIO.
+	 */
+	gpio_set_level(GPIO_EN_PP5000, !!enable);
+
+	if (board_get_charger_chip_count() > 1) {
+		if (sm5803_set_gpio0_level(1, !!enable))
+			CPRINTUSB("Failed to %sable sub rails!",
+				  enable ? "en" : "dis");
+	}
+}
+
+__override uint8_t board_get_usb_pd_port_count(void)
+{
+	enum fw_config_db db = get_cbi_fw_config_db();
+
+	if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI ||
+	    db == DB_1A_HDMI_LTE)
+		return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
+	else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A ||
+		 db == DB_1C_1A_LTE)
+		return CONFIG_USB_PD_PORT_MAX_COUNT;
+
+	ccprints("Unhandled DB configuration: %d", db);
+	return 0;
+}
+
+__override uint8_t board_get_charger_chip_count(void)
+{
+	enum fw_config_db db = get_cbi_fw_config_db();
+
+	if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI ||
+	    db == DB_1A_HDMI_LTE)
+		return CHARGER_NUM - 1;
+	else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A ||
+		 db == DB_1C_1A_LTE)
+		return CHARGER_NUM;
+
+	ccprints("Unhandled DB configuration: %d", db);
+	return 0;
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	/*
+	 * TCPC 0 is embedded in the EC and processes interrupts in the chip
+	 * code (it83xx/intc.c)
+	 */
+
+	uint16_t status = 0;
+	int regval;
+
+	/* Check whether TCPC 1 pulled the shared interrupt line */
+	if (!gpio_get_level(GPIO_USB_C1_INT_ODL)) {
+		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
+			if (regval)
+				status = PD_STATUS_TCPC_ALERT_1;
+		}
+	}
+
+	return status;
+}
+
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
+{
+	/* Limit C1 on board version 0 to 2.0 A */
+	if ((board_version == 0) && (port == 1))
+		charge_ma = MIN(charge_ma, 2000);
+	/*
+	 * TODO(b/151955431): Characterize the input current limit in case a
+	 * scaling needs to be applied here
+	 */
+	charge_set_input_current_limit(charge_ma, charge_mv);
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_valid_port = (port >= 0 && port < board_get_usb_pd_port_count());
+
+	if (!is_valid_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTUSB("Disabling all charge ports");
+
+		sm5803_vbus_sink_enable(CHARGER_PRIMARY, 0);
+
+		if (board_get_charger_chip_count() > 1)
+			sm5803_vbus_sink_enable(CHARGER_SECONDARY, 0);
+
+		return EC_SUCCESS;
+	}
+
+	CPRINTUSB("New chg p%d", port);
+
+	/*
+	 * Ensure other port is turned off, then enable new charge port
+	 */
+	if (port == 0) {
+		if (board_get_charger_chip_count() > 1)
+			sm5803_vbus_sink_enable(CHARGER_SECONDARY, 0);
+		sm5803_vbus_sink_enable(CHARGER_PRIMARY, 1);
+
+	} else {
+		sm5803_vbus_sink_enable(CHARGER_PRIMARY, 0);
+		sm5803_vbus_sink_enable(CHARGER_SECONDARY, 1);
+	}
+
+	return EC_SUCCESS;
+}
+
+/* Vconn control for integrated ITE TCPC */
+void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
+{
+	/* Vconn control is only for port 0 */
+	if (port)
+		return;
+
+	if (cc_pin == USBPD_CC_PIN_1)
+		gpio_set_level(GPIO_EN_USB_C0_CC1_VCONN, !!enabled);
+	else
+		gpio_set_level(GPIO_EN_USB_C0_CC2_VCONN, !!enabled);
+}
+
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	int current;
+
+	if (port < 0 || port > board_get_usb_pd_port_count())
+		return;
+
+	current = (rp == TYPEC_RP_3A0) ? 3000 : 1500;
+
+	charger_set_otg_current_voltage(port, current, 5000);
+}
+
+/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
+const struct pwm_t pwm_channels[] = { [PWM_CH_KBLIGHT] = {
+					      .channel = 0,
+					      .flags = PWM_CONFIG_DSLEEP,
+					      .freq_hz = 10000,
+				      } };
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+/* Thermistors */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "Charger",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
+	[TEMP_SENSOR_4] = { .name = "5V regular",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_4 },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/* This callback disables keyboard when convertibles are fully open */
+__override void lid_angle_peripheral_enable(int enable)
+{
+	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
+
+	/*
+	 * If the lid is in tablet position via other sensors,
+	 * ignore the lid angle, which might be faulty then
+	 * disable keyboard.
+	 */
+	if (tablet_get_mode())
+		enable = 0;
+
+	if (enable) {
+		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
+	} else {
+		/*
+		 * Ensure that the chipset is off before disabling the keyboard.
+		 * When the chipset is on, the EC keeps the keyboard enabled and
+		 * the AP decides whether to ignore input devices or not.
+		 */
+		if (!chipset_in_s0)
+			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
+	}
+}
+
+__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+				       int *ki_div, int *kd, int *kd_div)
+{
+	*kp = 3;
+	*kp_div = 20;
+
+	*ki = 3;
+	*ki_div = 125;
+
+	*kd = 4;
+	*kd_div = 40;
+}
+
+#ifdef CONFIG_KEYBOARD_FACTORY_TEST
+/*
+ * Map keyboard connector pins to EC GPIO pins for factory test.
+ * Pins mapped to {-1, -1} are skipped.
+ * The connector has 24 pins total, and there is no pin 0.
+ */
+const int keyboard_factory_scan_pins[][2] = {
+	{ -1, -1 },	   { GPIO_KSO_H, 4 }, { GPIO_KSO_H, 0 },
+	{ GPIO_KSO_H, 1 }, { GPIO_KSO_H, 3 }, { GPIO_KSO_H, 2 },
+	{ GPIO_KSO_L, 5 }, { GPIO_KSO_L, 6 }, { GPIO_KSO_L, 3 },
+	{ GPIO_KSO_L, 2 }, { GPIO_KSI, 0 },   { GPIO_KSO_L, 1 },
+	{ GPIO_KSO_L, 4 }, { GPIO_KSI, 3 },   { GPIO_KSI, 2 },
+	{ GPIO_KSO_L, 0 }, { GPIO_KSI, 5 },   { GPIO_KSI, 4 },
+	{ GPIO_KSO_L, 7 }, { GPIO_KSI, 6 },   { GPIO_KSI, 7 },
+	{ GPIO_KSI, 1 },   { -1, -1 },	      { -1, -1 },
+	{ -1, -1 },
+};
+
+const int keyboard_factory_scan_pins_used =
+	ARRAY_SIZE(keyboard_factory_scan_pins);
+#endif
diff --git a/board/drawcia_riscv/board.h b/board/drawcia_riscv/board.h
new file mode 100644
index 0000000000..2867412cf8
--- /dev/null
+++ b/board/drawcia_riscv/board.h
@@ -0,0 +1,166 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Drawcia board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* Select Baseboard features */
+
+/*
+ * We can use this define since it will work for IT81302 as well, since
+ * it is mostly used for TCPM config.
+ */
+#define VARIANT_DEDEDE_EC_IT8320
+#include "baseboard.h"
+
+#define CONFIG_LTO
+
+/*
+ * The workaround can be enabled on a chip variant with 1MB flash.
+ * (There is relocation truncated to fit error when building this board)
+ */
+#define CONFIG_RISCV_EXTENSION_M
+#undef CONFIG_IT8XXX2_MUL_WORKAROUND
+
+#undef GPIO_VOLUME_UP_L
+#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL_HDMI_HPD
+
+/* Battery */
+#define CONFIG_BATTERY_FUEL_GAUGE
+
+/* BC 1.2 */
+#define CONFIG_BC12_DETECT_PI3USB9201
+
+/* Charger */
+#define CONFIG_CHARGE_RAMP_HW
+#define CONFIG_CHARGER_SM5803 /* C0 and C1: Charger */
+#define PD_MAX_VOLTAGE_MV 15000
+#define CONFIG_USB_PD_VBUS_DETECT_CHARGER
+#define CONFIG_USB_PD_5V_CHARGER_CTRL
+#define CONFIG_CHARGER_OTG
+#undef CONFIG_CHARGER_SINGLE_CHIP
+#define CONFIG_OCPC
+#define CONFIG_OCPC_DEF_RBATT_MOHMS               \
+	21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr \
+	    */
+
+/* PWM */
+#define CONFIG_PWM
+
+/* Sensors */
+#define CONFIG_ACCEL_BMA255 /* Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
+/* Sensors without hardware FIFO are in forced mode */
+#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
+
+#define CONFIG_CMD_ACCELS
+#define CONFIG_CMD_ACCEL_INFO
+
+/* Enable sensor fifo, must also define the _SIZE and _THRES */
+#define CONFIG_ACCEL_FIFO
+/* Power of 2 - Too large of a fifo causes too much timestamp jitter */
+#define CONFIG_ACCEL_FIFO_SIZE 256
+#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
+
+#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
+
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_UPDATE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+
+#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+#define CONFIG_TABLET_MODE
+#define CONFIG_TABLET_MODE_SWITCH
+#define CONFIG_GMR_TABLET_MODE
+
+/* Keyboard */
+#define CONFIG_KEYBOARD_FACTORY_TEST
+#define CONFIG_PWM_KBLIGHT
+
+/* TCPC */
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0: ITE EC TCPC */
+#define CONFIG_USB_PD_TCPM_PS8705 /* C1: PS8705 TCPC*/
+#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1
+#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+#define CONFIG_USB_PD_TCPC_LOW_POWER
+
+/* Thermistors */
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_THERMISTOR
+#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
+
+/* USB Mux and Retimer */
+#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */
+
+/* USB Type A Features */
+#define USB_PORT_COUNT 1
+#define CONFIG_USB_PORT_POWER_DUMB
+
+/* Reduce flash image footprint */
+#undef CONFIG_CMD_ACCELS
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum chg_id {
+	CHARGER_PRIMARY,
+	CHARGER_SECONDARY,
+	CHARGER_NUM,
+};
+
+enum pwm_channel {
+	PWM_CH_KBLIGHT,
+	PWM_CH_COUNT,
+};
+
+/* Motion sensors */
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
+
+/* ADC channels */
+enum adc_channel {
+	ADC_VSNS_PP3300_A, /* ADC0 */
+	ADC_TEMP_SENSOR_1, /* ADC2 */
+	ADC_TEMP_SENSOR_2, /* ADC3 */
+	ADC_SUB_ANALOG, /* ADC13 */
+	ADC_TEMP_SENSOR_3, /* ADC15 */
+	ADC_TEMP_SENSOR_4, /* ADC16 */
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1,
+	TEMP_SENSOR_2,
+	TEMP_SENSOR_3,
+	TEMP_SENSOR_4,
+	TEMP_SENSOR_COUNT
+};
+
+/* List of possible batteries */
+enum battery_type {
+	BATTERY_DYNAPACK_COS,
+	BATTERY_DYNAPACK_ATL,
+	BATTERY_DYNAPACK_HIGHPOWER,
+	BATTERY_DYNAPACK_BYD,
+	BATTERY_SAMSUNG_SDI,
+	BATTERY_SIMPLO_COS,
+	BATTERY_SIMPLO_HIGHPOWER,
+	BATTERY_COS,
+	BATTERY_COS_2,
+	BATTERY_ATL,
+	BATTERY_TYPE_COUNT,
+};
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/drawcia_riscv/build.mk b/board/drawcia_riscv/build.mk
new file mode 100644
index 0000000000..b63b7a58b9
--- /dev/null
+++ b/board/drawcia_riscv/build.mk
@@ -0,0 +1,17 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+# Reworked drawcia with it8320 replaced with RISC-V it82302
+#
+
+CHIP:=it83xx
+CHIP_FAMILY:=it8xxx2
+CHIP_VARIANT:=it81302bx_512
+BASEBOARD:=dedede
+
+board-y=board.o cbi_ssfc.o led.o usb_pd_policy.o
+board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/drawcia_riscv/cbi_ssfc.c b/board/drawcia_riscv/cbi_ssfc.c
new file mode 100644
index 0000000000..81f3ee0dad
--- /dev/null
+++ b/board/drawcia_riscv/cbi_ssfc.c
@@ -0,0 +1,36 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi_ssfc.h"
+#include "common.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "hooks.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+/* Cache SSFC on init since we don't expect it to change in runtime */
+static union dedede_cbi_ssfc cached_ssfc;
+BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
+
+static void cbi_ssfc_init(void)
+{
+	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
+		/* Default to 0 when CBI isn't populated */
+		cached_ssfc.raw_value = 0;
+
+	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
+}
+DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
+
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
+{
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
+}
+
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
+{
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
+}
diff --git a/board/drawcia_riscv/cbi_ssfc.h b/board/drawcia_riscv/cbi_ssfc.h
new file mode 100644
index 0000000000..bf8853a43a
--- /dev/null
+++ b/board/drawcia_riscv/cbi_ssfc.h
@@ -0,0 +1,59 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _DEDEDE_CBI_SSFC__H_
+#define _DEDEDE_CBI_SSFC__H_
+
+#include "stdint.h"
+
+/****************************************************************************
+ * Dedede CBI Second Source Factory Cache
+ */
+
+/*
+ * Base Sensor (Bits 0-2)
+ */
+enum ec_ssfc_base_sensor {
+	SSFC_SENSOR_BASE_DEFAULT = 0,
+	SSFC_SENSOR_BMI160 = 1,
+	SSFC_SENSOR_ICM426XX = 2,
+	SSFC_SENSOR_LSM6DSM = 3,
+	SSFC_SENSOR_ICM42607 = 4
+};
+
+/*
+ * Lid Sensor (Bits 3-5)
+ */
+enum ec_ssfc_lid_sensor {
+	SSFC_SENSOR_LID_DEFAULT = 0,
+	SSFC_SENSOR_BMA255 = 1,
+	SSFC_SENSOR_KX022 = 2,
+	SSFC_SENSOR_LIS2DWL = 3
+};
+
+union dedede_cbi_ssfc {
+	struct {
+		uint32_t base_sensor : 3;
+		uint32_t lid_sensor : 3;
+		uint32_t reserved_2 : 26;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Get the Base sensor type from SSFC_CONFIG.
+ *
+ * @return the Base sensor board type.
+ */
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
+
+/**
+ * Get the Lid sensor type from SSFC_CONFIG.
+ *
+ * @return the Lid sensor board type.
+ */
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
+
+#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/drawcia_riscv/ec.tasklist b/board/drawcia_riscv/ec.tasklist
new file mode 100644
index 0000000000..c13df44543
--- /dev/null
+++ b/board/drawcia_riscv/ec.tasklist
@@ -0,0 +1,24 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, TRENTA_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, ULTRA_TASK_STACK_SIZE) \
+        TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+        TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+        TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/drawcia_riscv/gpio.inc b/board/drawcia_riscv/gpio.inc
new file mode 100644
index 0000000000..ad20442673
--- /dev/null
+++ b/board/drawcia_riscv/gpio.inc
@@ -0,0 +1,148 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+/* Power State interrupts */
+GPIO_INT(SLP_S4_L,		PIN(I, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,		PIN(H, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(SLP_S0_L,		PIN(E, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,		PIN(G, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID0,	PIN(D, 0), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(RSMRST_PWRGD_L,	PIN(E, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(CPU_C10_GATE_L,	PIN(G, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_DRAM_OD,		PIN(D, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(PG_PP1050_ST_OD,	PIN(L, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID1,	PIN(K, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_VCCIO_EXT_OD,	PIN(D, 7), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(ESPI_RESET_L, 	 PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt)
+
+GPIO_INT(H1_EC_PWR_BTN_ODL,	PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
+#ifdef CONFIG_LOW_POWER_IDLE
+/* Used to wake up the EC from Deep Doze mode when writing to console */
+GPIO_INT(UART1_RX,	 PIN(B, 0), GPIO_INT_BOTH, uart_deepsleep_interrupt)	/* UART_DBG_TX_EC_RX */
+#endif
+
+/* USB-C interrupts */
+GPIO_INT(USB_C0_INT_ODL,	PIN(K, 0), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt) /* BC12 and charger */
+GPIO_INT(USB_C1_INT_ODL,	PIN(E, 6), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c1_interrupt) /* TCPC, charger, BC12 */
+GPIO_INT(USB_C0_CCSBU_OVP_ODL,	PIN(K, 6), GPIO_INT_FALLING | GPIO_PULL_UP, c0_ccsbu_ovp_interrupt) /* Fault protection */
+
+/* Other interrupts */
+GPIO_INT(LID_OPEN,		PIN(F, 3), GPIO_INT_BOTH, lid_interrupt)
+GPIO_INT(LID_360_L,		PIN(A, 7), GPIO_INT_BOTH, gmr_tablet_switch_isr)
+GPIO_INT(VOLDN_BTN_ODL,		PIN(I, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(VOLUP_BTN_ODL_HDMI_HPD,	PIN(I, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_sub_hdmi_hpd_interrupt)
+GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(J, 0), GPIO_INT_FALLING | GPIO_SEL_1P8V, lsm6dsm_interrupt)
+GPIO_INT(EC_WP_OD,		PIN(A, 6), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(PEN_DET_ODL,		PIN(J, 1), GPIO_INT_BOTH | GPIO_PULL_UP, pen_detect_interrupt)
+
+/* Power sequence GPIOs */
+GPIO(EC_AP_RTCRST,		PIN(K, 2), GPIO_OUT_LOW)
+GPIO(EC_AP_PWR_BTN_ODL,		PIN(B, 6), GPIO_ODR_HIGH)
+GPIO(EC_AP_DPWROK,		PIN(L, 7), GPIO_OUT_LOW)
+GPIO(EC_AP_RSMRST_L,		PIN(H, 0), GPIO_OUT_LOW)
+GPIO(EC_AP_WAKE_ODL,		PIN(D, 5), GPIO_ODR_HIGH)
+GPIO(SYS_RST_ODL,		PIN(D, 1), GPIO_ODR_HIGH)
+GPIO(EC_AP_SYS_PWROK,		PIN(F, 2), GPIO_OUT_LOW)
+GPIO(PG_PP5000_U_OD,		PIN(E, 3), GPIO_INPUT)
+GPIO(EN_PP3300_A,		PIN(C, 5), GPIO_OUT_LOW)
+GPIO(EC_AP_PCH_PWROK_OD,	PIN(D, 6), GPIO_ODR_LOW)
+GPIO(EN_PP5000_U,		PIN(K, 5), GPIO_OUT_LOW)
+/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
+GPIO(EN_VCCST,			PIN(D, 4), GPIO_INPUT)
+GPIO(EN_VCCIO_EXT,		PIN(B, 2), GPIO_OUT_LOW)
+GPIO(EC_PROCHOT_ODL,		PIN(I, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(EC_AP_VCCST_PWRGD_OD,	PIN(E, 5), GPIO_ODR_LOW)
+GPIO(ALL_SYS_PWRGD,		PIN(B, 7), GPIO_OUT_LOW)
+GPIO(EN_SLP_Z,			PIN(K, 3), GPIO_OUT_LOW)
+
+/* Required for icelake chipset code, but implemented through other means for dedede */
+UNIMPLEMENTED(AC_PRESENT)
+UNIMPLEMENTED(PG_EC_DSW_PWROK)
+UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
+
+/* I2C pins - Alternate function below configures I2C module on these pins */
+GPIO(EC_I2C_EEPROM_SCL,		PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SDA,		PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SCL,	PIN(C, 1), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SDA,	PIN(C, 2), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,		PIN(F, 6), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SENSOR_SDA,		PIN(F, 7), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SUB_USB_C1_SCL,	PIN(E, 0), GPIO_INPUT)
+GPIO(EC_I2C_SUB_USB_C1_SDA,	PIN(E, 7), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SCL,		PIN(A, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SDA,		PIN(A, 5), GPIO_INPUT)
+
+/* USB pins */
+GPIO(EN_USB_A_5V,			PIN(L, 6), GPIO_OUT_LOW)
+GPIO(EN_USB_C0_CC1_VCONN,	PIN(H, 4), GPIO_OUT_LOW)
+GPIO(EN_USB_C0_CC2_VCONN,	PIN(H, 6), GPIO_OUT_LOW)
+GPIO(EC_AP_USB_C0_HPD,		PIN(L, 4), GPIO_OUT_LOW)
+GPIO(EC_AP_USB_C1_HDMI_HPD,	PIN(K, 7), GPIO_OUT_LOW)
+GPIO(USB_C0_FRS,		PIN(C, 4), GPIO_OUT_LOW)
+GPIO(HDMI_SEL_L,		PIN(C, 6), GPIO_OUT_HIGH)
+
+/* MKBP event synchronization */
+GPIO(EC_AP_MKBP_INT_L,	PIN(L, 5), GPIO_ODR_HIGH)
+
+/* Misc pins which will run to the I/O board */
+GPIO(EC_SUB_IO_1_2, PIN(F, 0), GPIO_INPUT)
+GPIO(EC_SUB_IO_2_1, PIN(F, 1), GPIO_INPUT)
+
+/* Misc */
+GPIO(EN_BL_OD,			PIN(K, 4), GPIO_ODR_LOW)
+GPIO(EC_ENTERING_RW,		PIN(G, 0), GPIO_OUT_LOW)
+GPIO(EC_ENTERING_RW2,		PIN(C, 7), GPIO_OUT_LOW)
+GPIO(CCD_MODE_ODL,		PIN(H, 5), GPIO_ODR_HIGH)
+GPIO(EC_BATTERY_PRES_ODL,	PIN(I, 4), GPIO_INPUT)
+GPIO(EN_KB_BL,			PIN(J, 3), GPIO_OUT_LOW) /* Currently unused */
+GPIO(ECH1_PACKET_MODE,		PIN(H, 1), GPIO_OUT_LOW)
+GPIO(EN_PP5000_PEN,		PIN(B, 5), GPIO_OUT_LOW)
+
+/* NC pins, enable internal pull-down to avoid floating state. */
+GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOC3_NC, PIN(C, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG3_NC, PIN(G, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG4_NC, PIN(G, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG5_NC, PIN(G, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG6_NC, PIN(G, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG7_NC, PIN(G, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ4_NC, PIN(J, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ5_NC, PIN(J, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ6_NC, PIN(J, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOM6_NC, PIN(M, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+
+/* LED */
+GPIO(BAT_LED_AMBER_L,	 PIN(A, 1), GPIO_OUT_HIGH)
+GPIO(BAT_LED_WHITE_L,	 PIN(A, 2), GPIO_OUT_HIGH)
+GPIO(PWR_LED_WHITE_L,	 PIN(A, 3), GPIO_OUT_HIGH)
+
+/* Alternate functions GPIO definitions */
+/* Keyboard */
+ALTERNATE(PIN_MASK(KSI,   0xFF), 0, MODULE_KEYBOARD_SCAN, 0)		/* KSI0-7 */
+ALTERNATE(PIN_MASK(KSO_H, 0xFF), 0, MODULE_KEYBOARD_SCAN, 0)		/* KSO8-15 */
+ALTERNATE(PIN_MASK(KSO_L, 0xFB), 0, MODULE_KEYBOARD_SCAN, 0)		/* KSO0-1, 3-7 */
+GPIO(EC_KSO_02_INV, PIN(KSO_L, 2), GPIO_OUT_HIGH)			/* KSO2 inverted */
+
+/* UART */
+ALTERNATE(PIN_MASK(B, BIT(0) | BIT(1)), 0, MODULE_UART, 0)		/* UART for debug */
+
+/* I2C */
+ALTERNATE(PIN_MASK(B, BIT(3) | BIT(4)), 0, MODULE_I2C, 0)		/* I2C0 */
+ALTERNATE(PIN_MASK(C, BIT(1) | BIT(2)), 0, MODULE_I2C, 0)		/* I2C1 */
+ALTERNATE(PIN_MASK(F, BIT(6) | BIT(7)), 0, MODULE_I2C, GPIO_SEL_1P8V)	/* I2C2 - 1.8V */
+ALTERNATE(PIN_MASK(E, BIT(0) | BIT(7)), 0, MODULE_I2C, 0)		/* I2C4 */
+ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), 0, MODULE_I2C, 0)		/* I2C5 */
+
+/* ADC */
+ALTERNATE(PIN_MASK(L, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0)	/* ADC13: EC_SUB_ANALOG, ADC15: TEMP_SENSOR_3, ADC16: TEMP_SENSOR_4 */
+ALTERNATE(PIN_MASK(I, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0)	/* ADC0: EC_VSNS_PP3300_A, ADC2: TEMP_SENSOR_1, ADC3: TEMP_SENSOR_2 */
+
+/* PWM */
+ALTERNATE(PIN_MASK(A, BIT(0)), 0, MODULE_PWM, 0) 			/* KB_BL_PWM */
diff --git a/board/drawcia_riscv/led.c b/board/drawcia_riscv/led.c
new file mode 100644
index 0000000000..926f83d1f6
--- /dev/null
+++ b/board/drawcia_riscv/led.c
@@ -0,0 +1,200 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Drawcia specific LED settings. */
+
+#include "cbi_fw_config.h"
+#include "charge_state.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "led_common.h"
+
+#define BAT_LED_ON 0
+#define BAT_LED_OFF 1
+
+#define POWER_LED_ON 0
+#define POWER_LED_OFF 1
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+enum led_color {
+	LED_OFF = 0,
+	LED_AMBER,
+	LED_WHITE,
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
+};
+
+static int led_set_color_battery(enum led_color color)
+{
+	switch (color) {
+	case LED_OFF:
+		gpio_set_level(GPIO_BAT_LED_WHITE_L, BAT_LED_OFF);
+		gpio_set_level(GPIO_BAT_LED_AMBER_L, BAT_LED_OFF);
+		break;
+	case LED_WHITE:
+		gpio_set_level(GPIO_BAT_LED_WHITE_L, BAT_LED_ON);
+		gpio_set_level(GPIO_BAT_LED_AMBER_L, BAT_LED_OFF);
+		break;
+	case LED_AMBER:
+		gpio_set_level(GPIO_BAT_LED_WHITE_L, BAT_LED_OFF);
+		gpio_set_level(GPIO_BAT_LED_AMBER_L, BAT_LED_ON);
+		break;
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+	return EC_SUCCESS;
+}
+
+static int led_set_color_power(enum led_color color)
+{
+	switch (color) {
+	case LED_OFF:
+		gpio_set_level(GPIO_PWR_LED_WHITE_L, POWER_LED_OFF);
+		break;
+	case LED_WHITE:
+		gpio_set_level(GPIO_PWR_LED_WHITE_L, POWER_LED_ON);
+		break;
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+	return EC_SUCCESS;
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	switch (led_id) {
+	case EC_LED_ID_BATTERY_LED:
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		break;
+	case EC_LED_ID_POWER_LED:
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		break;
+	default:
+		break;
+	}
+}
+
+static int led_set_color(enum ec_led_id led_id, enum led_color color)
+{
+	int rv;
+
+	switch (led_id) {
+	case EC_LED_ID_BATTERY_LED:
+		rv = led_set_color_battery(color);
+		break;
+	case EC_LED_ID_POWER_LED:
+		rv = led_set_color_power(color);
+		break;
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+	return rv;
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (brightness[EC_LED_COLOR_WHITE] != 0)
+		led_set_color(led_id, LED_WHITE);
+	else if (brightness[EC_LED_COLOR_AMBER] != 0)
+		led_set_color(led_id, LED_AMBER);
+	else
+		led_set_color(led_id, LED_OFF);
+
+	return EC_SUCCESS;
+}
+
+static void led_set_battery(void)
+{
+	static int battery_ticks;
+	static int power_ticks;
+
+	battery_ticks++;
+
+	/*
+	 * Override battery LED for Drawlet/Drawman, Drawlet/Drawman
+	 * don't have power LED, blinking battery white LED to indicate
+	 * system suspend without charging.
+	 */
+	if (get_cbi_fw_config_tablet_mode() == TABLET_MODE_ABSENT) {
+		if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
+		    led_pwr_get_state() != LED_PWRS_CHARGE) {
+			led_set_color_battery(power_ticks++ & 0x2 ? LED_WHITE :
+								    LED_OFF);
+			return;
+		}
+	}
+
+	power_ticks = 0;
+
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
+		led_set_color_battery(LED_AMBER);
+		break;
+	case LED_PWRS_DISCHARGE_FULL:
+		if (extpower_is_present()) {
+			led_set_color_battery(LED_WHITE);
+			break;
+		}
+		__fallthrough;
+	case LED_PWRS_DISCHARGE:
+		/*
+		 * Blink white light (1 sec on, 1 sec off)
+		 * when battery capacity is less than 10%
+		 */
+		if (charge_get_percent() < 10)
+			led_set_color_battery(
+				(battery_ticks & 0x2) ? LED_WHITE : LED_OFF);
+		else
+			led_set_color_battery(LED_OFF);
+		break;
+	case LED_PWRS_ERROR:
+		led_set_color_battery((battery_ticks % 0x2) ? LED_WHITE :
+							      LED_OFF);
+		break;
+	case LED_PWRS_CHARGE_NEAR_FULL:
+		led_set_color_battery(LED_WHITE);
+		break;
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		led_set_color_battery(LED_WHITE);
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		led_set_color_battery((battery_ticks & 0x2) ? LED_AMBER :
+							      LED_OFF);
+		break;
+	default:
+		/* Other states don't alter LED behavior */
+		break;
+	}
+}
+
+static void led_set_power(void)
+{
+	static int power_tick;
+
+	power_tick++;
+
+	if (chipset_in_state(CHIPSET_STATE_ON))
+		led_set_color_power(LED_WHITE);
+	else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
+		led_set_color_power((power_tick & 0x2) ? LED_WHITE : LED_OFF);
+	else
+		led_set_color_power(LED_OFF);
+}
+
+/* Called by hook task every TICK */
+static void led_tick(void)
+{
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		led_set_power();
+
+	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
+		led_set_battery();
+}
+DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
diff --git a/board/drawcia_riscv/usb_pd_policy.c b/board/drawcia_riscv/usb_pd_policy.c
new file mode 100644
index 0000000000..8a2c07c575
--- /dev/null
+++ b/board/drawcia_riscv/usb_pd_policy.c
@@ -0,0 +1,74 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery_smart.h"
+#include "charge_manager.h"
+#include "charger.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "driver/charger/sm5803.h"
+#include "driver/tcpm/tcpci.h"
+#include "usb_pd.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+int pd_check_vconn_swap(int port)
+{
+	/* Allow VCONN swaps if the AP is on */
+	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
+}
+
+void pd_power_supply_reset(int port)
+{
+	int prev_en;
+
+	if (port < 0 || port >= board_get_usb_pd_port_count())
+		return;
+
+	prev_en = charger_is_sourcing_otg_power(port);
+
+	/* Disable Vbus */
+	charger_enable_otg_power(port, 0);
+
+	/* Discharge Vbus if previously enabled */
+	if (prev_en)
+		sm5803_set_vbus_disch(port, 1);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	enum ec_error_list rv;
+
+	/* Disable sinking */
+	rv = sm5803_vbus_sink_enable(port, 0);
+	if (rv)
+		return rv;
+
+	/* Disable Vbus discharge */
+	sm5803_set_vbus_disch(port, 0);
+
+	/* Provide Vbus */
+	charger_enable_otg_power(port, 1);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+__override bool pd_check_vbus_level(int port, enum vbus_level level)
+{
+	return sm5803_check_vbus_level(port, level);
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	return sm5803_is_vbus_present(port);
+}
diff --git a/board/drawcia_riscv/vif_override.xml b/board/drawcia_riscv/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/drawcia_riscv/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/driblee/battery.c b/board/driblee/battery.c
new file mode 100644
index 0000000000..d73bc104ac
--- /dev/null
+++ b/board/driblee/battery.c
@@ -0,0 +1,658 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "battery_smart.h"
+#include "charge_state.h"
+#include "common.h"
+#include "util.h"
+
+/*
+ * Battery info for lalala battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	/* BYD Battery Information */
+	[BATTERY_BYD_1VX1H] = {
+		.fuel_gauge = {
+			.manuf_name = "BYD",
+			.device_name = "DELL 1VX1H",
+			.ship_mode = {
+				.wb_support = 1,
+				.reg_addr = 0x44,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr       = 0x0,
+				.reg_mask       = 0x8000,
+				.disconnect_val = 0x8000,
+				.cfet_mask = 0x4000,
+				.cfet_off_val = 0x4000,
+			}
+		},
+		.batt_info = {
+			.voltage_max          = 13200,    /* mV */
+			.voltage_normal       = 11400,
+			.voltage_min          = 9000,
+			.precharge_current    = 256,       /* mA */
+			.start_charging_min_c = -3,
+			.start_charging_max_c = 50,
+			.charging_min_c       = -3,
+			.charging_max_c       = 60,
+			.discharging_min_c    = -5,
+			.discharging_max_c    = 70,
+		},
+	},
+
+	/* BYD Battery Information */
+	[BATTERY_BYD_YT39X] = {
+		.fuel_gauge = {
+			.manuf_name = "BYD",
+			.device_name = "DELL YT39X",
+			.ship_mode = {
+				.wb_support = 1,
+				.reg_addr = 0x44,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr       = 0x0,
+				.reg_mask       = 0x8000,
+				.disconnect_val = 0x8000,
+				.cfet_mask = 0x4000,
+				.cfet_off_val = 0x4000,
+			}
+		},
+		.batt_info = {
+			.voltage_max          = 13200,    /* mV */
+			.voltage_normal       = 11400,
+			.voltage_min          = 9000,
+			.precharge_current    = 256,       /* mA */
+			.start_charging_min_c = -3,
+			.start_charging_max_c = 50,
+			.charging_min_c       = -3,
+			.charging_max_c       = 60,
+			.discharging_min_c    = -5,
+			.discharging_max_c    = 70,
+		},
+	},
+
+	/* BYD Battery Information */
+	[BATTERY_BYD_X0Y5M] = {
+		.fuel_gauge = {
+			.manuf_name = "BYD",
+			.device_name = "DELL X0Y5M",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr       = 0x043,
+				.reg_mask       = 0x0001,
+				.disconnect_val = 0x0000,
+				.cfet_mask = 0x0002,
+				.cfet_off_val = 0x0000,
+			}
+		},
+		.batt_info = {
+			.voltage_max          = 13200,    /* mV */
+			.voltage_normal       = 11400,
+			.voltage_min          = 9000,
+			.precharge_current    = 256,       /* mA */
+			.start_charging_min_c = -3,
+			.start_charging_max_c = 50,
+			.charging_min_c       = -3,
+			.charging_max_c       = 60,
+			.discharging_min_c    = -5,
+			.discharging_max_c    = 70,
+		},
+	},
+
+	/* LGC Battery Information */
+	[BATTERY_LGC_FDRHM] = {
+		.fuel_gauge = {
+			.manuf_name = "LGC-LGC3.65",
+			.device_name = "DELL FDRHM",
+			.ship_mode = {
+				.wb_support = 1,
+				.reg_addr = 0x44,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr       = 0x0,
+				.reg_mask       = 0x8000,
+				.disconnect_val = 0x8000,
+				.cfet_mask = 0x4000,
+				.cfet_off_val = 0x4000,
+			}
+		},
+		.batt_info = {
+			.voltage_max          = 13200,    /* mV */
+			.voltage_normal       = 11460,
+			.voltage_min          = 9000,
+			.precharge_current    = 256,       /* mA */
+			.start_charging_min_c = -3,
+			.start_charging_max_c = 50,
+			.charging_min_c       = -3,
+			.charging_max_c       = 60,
+			.discharging_min_c    = -5,
+			.discharging_max_c    = 70,
+		},
+	},
+
+	/* LGC Battery Information */
+	[BATTERY_LGC_8GHCX] = {
+		.fuel_gauge = {
+			.manuf_name = "LGC-LGC3.65",
+			.device_name = "DELL 8GHCX",
+			.ship_mode = {
+				.wb_support = 1,
+				.reg_addr = 0x44,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr       = 0x0,
+				.reg_mask       = 0x8000,
+				.disconnect_val = 0x8000,
+				.cfet_mask = 0x4000,
+				.cfet_off_val = 0x4000,
+			}
+		},
+		.batt_info = {
+			.voltage_max          = 13200,    /* mV */
+			.voltage_normal       = 11460,
+			.voltage_min          = 9000,
+			.precharge_current    = 256,       /* mA */
+			.start_charging_min_c = -3,
+			.start_charging_max_c = 50,
+			.charging_min_c       = -3,
+			.charging_max_c       = 60,
+			.discharging_min_c    = -5,
+			.discharging_max_c    = 70,
+		},
+	},
+
+
+	/* SWD-ATL Battery Information */
+	[BATTERY_SWD_ATL_WJPC4] = {
+		.fuel_gauge = {
+			.manuf_name = "SWD-ATL3.618",
+			.device_name = "DELL WJPC4",
+			.ship_mode = {
+				.wb_support = 1,
+				.reg_addr = 0x44,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr       = 0x0,
+				.reg_mask       = 0x8000,
+				.disconnect_val = 0x8000,
+				.cfet_mask = 0x4000,
+				.cfet_off_val = 0x4000,
+			}
+		},
+		.batt_info = {
+			.voltage_max          = 13200,    /* mV */
+			.voltage_normal       = 11400,
+			.voltage_min          = 9000,
+			.precharge_current    = 256,       /* mA */
+			.start_charging_min_c = -3,
+			.start_charging_max_c = 50,
+			.charging_min_c       = -3,
+			.charging_max_c       = 60,
+			.discharging_min_c    = -5,
+			.discharging_max_c    = 70,
+		},
+	},
+
+	/* SWD-ATL Battery Information */
+	[BATTERY_SWD_ATL_CTGKT] = {
+		.fuel_gauge = {
+			.manuf_name = "SWD-ATL3.618",
+			.device_name = "DELL CTGKT",
+			.ship_mode = {
+				.wb_support = 1,
+				.reg_addr = 0x44,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr       = 0x0,
+				.reg_mask       = 0x8000,
+				.disconnect_val = 0x8000,
+				.cfet_mask = 0x4000,
+				.cfet_off_val = 0x4000,
+			}
+		},
+		.batt_info = {
+			.voltage_max          = 13200,    /* mV */
+			.voltage_normal       = 11400,
+			.voltage_min          = 9000,
+			.precharge_current    = 256,       /* mA */
+			.start_charging_min_c = -3,
+			.start_charging_max_c = 50,
+			.charging_min_c       = -3,
+			.charging_max_c       = 60,
+			.discharging_min_c    = -5,
+			.discharging_max_c    = 70,
+		},
+	},
+
+	/* SWD-COS Battery Information */
+	[BATTERY_SWD_COS_WJPC4] = {
+		.fuel_gauge = {
+			.manuf_name = "SWD-COS3.634",
+			.device_name = "DELL WJPC4",
+			.ship_mode = {
+				.wb_support = 1,
+				.reg_addr = 0x44,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr       = 0x0,
+				.reg_mask       = 0x8000,
+				.disconnect_val = 0x8000,
+				.cfet_mask = 0x4000,
+				.cfet_off_val = 0x4000,
+			}
+		},
+		.batt_info = {
+			.voltage_max          = 13200,    /* mV */
+			.voltage_normal       = 11400,
+			.voltage_min          = 9000,
+			.precharge_current    = 256,       /* mA */
+			.start_charging_min_c = -3,
+			.start_charging_max_c = 50,
+			.charging_min_c       = -3,
+			.charging_max_c       = 60,
+			.discharging_min_c    = -5,
+			.discharging_max_c    = 70,
+		},
+	},
+
+	/* SWD-COS Battery Information */
+	[BATTERY_SWD_COS_CTGKT] = {
+		.fuel_gauge = {
+			.manuf_name = "SWD-COS3.634",
+			.device_name = "DELL CTGKT",
+			.ship_mode = {
+				.wb_support = 1,
+				.reg_addr = 0x44,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr       = 0x0,
+				.reg_mask       = 0x8000,
+				.disconnect_val = 0x8000,
+				.cfet_mask = 0x4000,
+				.cfet_off_val = 0x4000,
+			}
+		},
+		.batt_info = {
+			.voltage_max          = 13200,    /* mV */
+			.voltage_normal       = 11400,
+			.voltage_min          = 9000,
+			.precharge_current    = 256,       /* mA */
+			.start_charging_min_c = -3,
+			.start_charging_max_c = 50,
+			.charging_min_c       = -3,
+			.charging_max_c       = 60,
+			.discharging_min_c    = -5,
+			.discharging_max_c    = 70,
+		},
+	},
+
+	/* SMP-ATL Battery Information */
+	[BATTERY_SMP_ATL_VM732] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP-ATL-3.61",
+			.device_name = "DELL VM732",
+			.ship_mode = {
+				.wb_support = 1,
+				.reg_addr = 0x44,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr       = 0x0,
+				.reg_mask       = 0x8000,
+				.disconnect_val = 0x8000,
+				.cfet_mask = 0x4000,
+				.cfet_off_val = 0x4000,
+			}
+		},
+		.batt_info = {
+			.voltage_max          = 13200,    /* mV */
+			.voltage_normal       = 11400,
+			.voltage_min          = 9000,
+			.precharge_current    = 256,       /* mA */
+			.start_charging_min_c = -3,
+			.start_charging_max_c = 50,
+			.charging_min_c       = -3,
+			.charging_max_c       = 60,
+			.discharging_min_c    = -5,
+			.discharging_max_c    = 70,
+		},
+	},
+
+	/* SMP-ATL Battery Information */
+	[BATTERY_SMP_ATL_26JGK] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP-ATL-3.61",
+			.device_name = "DELL 26JGK",
+			.ship_mode = {
+				.wb_support = 1,
+				.reg_addr = 0x44,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr       = 0x0,
+				.reg_mask       = 0x8000,
+				.disconnect_val = 0x8000,
+				.cfet_mask = 0x4000,
+				.cfet_off_val = 0x4000,
+			}
+		},
+		.batt_info = {
+			.voltage_max          = 13200,    /* mV */
+			.voltage_normal       = 11400,
+			.voltage_min          = 9000,
+			.precharge_current    = 256,       /* mA */
+			.start_charging_min_c = -3,
+			.start_charging_max_c = 50,
+			.charging_min_c       = -3,
+			.charging_max_c       = 60,
+			.discharging_min_c    = -5,
+			.discharging_max_c    = 70,
+		},
+	},
+
+	/* SMP-ATL Battery Information */
+	[BATTERY_SMP_ATL_RF9H3] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP-ATL-3.61",
+			.device_name = "DELL RF9H3",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr       = 0x43,
+				.reg_mask       = 0x0001,
+				.disconnect_val = 0x0000,
+				.cfet_mask = 0x0002,
+				.cfet_off_val = 0x0000,
+			}
+		},
+		.batt_info = {
+			.voltage_max          = 13200,    /* mV */
+			.voltage_normal       = 11400,
+			.voltage_min          = 9000,
+			.precharge_current    = 256,       /* mA */
+			.start_charging_min_c = -3,
+			.start_charging_max_c = 50,
+			.charging_min_c       = -3,
+			.charging_max_c       = 60,
+			.discharging_min_c    = -5,
+			.discharging_max_c    = 70,
+		},
+	},
+
+	/* SMP-COS Battery Information */
+	[BATTERY_SMP_COS_VM732] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP-COS3.63",
+			.device_name = "DELL VM732",
+			.ship_mode = {
+				.wb_support = 1,
+				.reg_addr = 0x44,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr       = 0x0,
+				.reg_mask       = 0x8000,
+				.disconnect_val = 0x8000,
+				.cfet_mask = 0x4000,
+				.cfet_off_val = 0x4000,
+			}
+		},
+		.batt_info = {
+			.voltage_max          = 13200,    /* mV */
+			.voltage_normal       = 11400,
+			.voltage_min          = 9000,
+			.precharge_current    = 256,       /* mA */
+			.start_charging_min_c = -3,
+			.start_charging_max_c = 50,
+			.charging_min_c       = -3,
+			.charging_max_c       = 60,
+			.discharging_min_c    = -5,
+			.discharging_max_c    = 70,
+		},
+	},
+
+	/* SMP-COS Battery Information */
+	[BATTERY_SMP_COS_26JGK] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP-COS3.63",
+			.device_name = "DELL 26JGK",
+			.ship_mode = {
+				.wb_support = 1,
+				.reg_addr = 0x44,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr       = 0x0,
+				.reg_mask       = 0x8000,
+				.disconnect_val = 0x8000,
+				.cfet_mask = 0x4000,
+				.cfet_off_val = 0x4000,
+			}
+		},
+		.batt_info = {
+			.voltage_max          = 13200,    /* mV */
+			.voltage_normal       = 11400,
+			.voltage_min          = 9000,
+			.precharge_current    = 256,       /* mA */
+			.start_charging_min_c = -3,
+			.start_charging_max_c = 50,
+			.charging_min_c       = -3,
+			.charging_max_c       = 60,
+			.discharging_min_c    = -5,
+			.discharging_max_c    = 70,
+		},
+	},
+	/* SMP-COS Battery Information */
+	[BATTERY_SMP_COS_RF9H3] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP-COS3.63",
+			.device_name = "DELL RF9H3",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr       = 0x43,
+				.reg_mask       = 0x0001,
+				.disconnect_val = 0x0000,
+				.cfet_mask = 0x0002,
+				.cfet_off_val = 0x0000,
+			}
+		},
+		.batt_info = {
+			.voltage_max          = 13200,    /* mV */
+			.voltage_normal       = 11400,
+			.voltage_min          = 9000,
+			.precharge_current    = 256,       /* mA */
+			.start_charging_min_c = -3,
+			.start_charging_max_c = 50,
+			.charging_min_c       = -3,
+			.charging_max_c       = 60,
+			.discharging_min_c    = -5,
+			.discharging_max_c    = 70,
+		},
+	},
+
+	/* BYD 16DPHYMD Battery Information */
+	[BATTERY_BYD16] = {
+		.fuel_gauge = {
+			.manuf_name = "BYD-BYD3.685",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr = 0x043,
+				.reg_mask = 0x0001,
+				.disconnect_val = 0x000,
+				.cfet_mask = 0x0002,
+				.cfet_off_val = 0x0000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13200, /* mV */
+			.voltage_normal		= 11400, /* mV */
+			.voltage_min		= 9000, /* mV */
+			.precharge_current	= 256,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= 0,
+			.discharging_max_c	= 70,
+		},
+	},
+
+	/* LGC Battery Information */
+	[BATTERY_LGC3] = {
+		.fuel_gauge = {
+			.manuf_name = "LGC-LGC3.553",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr       = 0x0,
+				.reg_mask       = 0x8000,
+				.disconnect_val = 0x8000,
+				.cfet_mask = 0x4000,
+				.cfet_off_val = 0x4000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13200, /* mV */
+			.voltage_normal		= 11400, /* mV */
+			.voltage_min		= 9000, /* mV */
+			.precharge_current	= 256,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 70,
+		},
+	},
+
+	/* SIMPLO Battery Information */
+	[BATTERY_SIMPLO] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP-SDI3.72",
+			.ship_mode = {
+				.reg_addr = 0x0,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr = 0x043,
+				.reg_mask = 0x0001,
+				.disconnect_val = 0x000,
+				.cfet_mask = 0x0002,
+				.cfet_off_val = 0x0000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13200, /* mV */
+			.voltage_normal		= 11400, /* mV */
+			.voltage_min		= 9000, /* mV */
+			.precharge_current	= 256,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 70,
+		},
+	},
+
+	/* SIMPLO-LISHEN 7T0D3YMD Battery Information */
+	[BATTERY_SIMPLO_LS] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP-LS3.66",
+			.ship_mode = {
+				.reg_addr = 0x0,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr = 0x043,
+				.reg_mask = 0x0001,
+				.disconnect_val = 0x000,
+				.cfet_mask = 0x0002,
+				.cfet_off_val = 0x0000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13200, /* mV */
+			.voltage_normal		= 11400, /* mV */
+			.voltage_min		= 9000, /* mV */
+			.precharge_current	= 256,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= 0,
+			.discharging_max_c	= 70,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_BYD_1VX1H;
+
+int charger_profile_override(struct charge_state_data *curr)
+{
+	if (chipset_in_state(CHIPSET_STATE_ON)) {
+		curr->requested_current =
+			MIN(curr->requested_current, CHARGING_CURRENT_1100MA);
+	}
+
+	return 0;
+}
+
+enum ec_status charger_profile_override_get_param(uint32_t param,
+						  uint32_t *value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+enum ec_status charger_profile_override_set_param(uint32_t param,
+						  uint32_t value)
+{
+	return EC_RES_INVALID_PARAM;
+}
diff --git a/board/driblee/board.c b/board/driblee/board.c
new file mode 100644
index 0000000000..739be95ce3
--- /dev/null
+++ b/board/driblee/board.c
@@ -0,0 +1,493 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Lalala board-specific configuration */
+
+#include "adc_chip.h"
+#include "button.h"
+#include "cbi_fw_config.h"
+#include "cbi_ssfc.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "chipset.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "driver/bc12/pi3usb9201.h"
+#include "driver/charger/isl923x.h"
+#include "driver/retimer/ps8802.h"
+#include "driver/tcpm/raa489000.h"
+#include "driver/tcpm/tcpci.h"
+#include "driver/temp_sensor/thermistor.h"
+#include "driver/usb_mux/pi3usb3x532.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "keyboard_8042.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "stdbool.h"
+#include "switch.h"
+#include "system.h"
+#include "task.h"
+#include "temp_sensor.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+#define INT_RECHECK_US 5000
+
+#define ADC_VOL_UP_MASK BIT(0)
+#define ADC_VOL_DOWN_MASK BIT(1)
+
+static uint8_t new_adc_key_state;
+
+/******************************************************************************/
+/* USB-A Configuration */
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_USB_A0_VBUS,
+};
+
+/* Keyboard scan setting */
+static const struct ec_response_keybd_config driblee_keybd = {
+	/* Default Chromeos keyboard config */
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_FORWARD,		/* T2 */
+		TK_REFRESH,		/* T3 */
+		TK_FULLSCREEN,		/* T4 */
+		TK_OVERVIEW,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	/* No function keys, no numeric keypad, has screenlock key */
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &driblee_keybd;
+}
+
+/* C0 interrupt line shared by BC 1.2 and charger */
+static void check_c0_line(void);
+DECLARE_DEFERRED(check_c0_line);
+
+static void notify_c0_chips(void)
+{
+	/*
+	 * The interrupt line is shared between the TCPC and BC 1.2 detection
+	 * chip.  Therefore we'll need to check both ICs.
+	 */
+	schedule_deferred_pd_interrupt(0);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+
+static void check_c0_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		notify_c0_chips();
+		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+	}
+}
+
+static void usb_c0_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c0_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c0_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+}
+
+static void sub_hdmi_hpd_interrupt(enum gpio_signal s)
+{
+	int hdmi_hpd_odl = gpio_get_level(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL);
+
+	gpio_set_level(GPIO_EC_AP_USB_C1_HDMI_HPD, !hdmi_hpd_odl);
+}
+
+static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
+{
+	cprints(CC_USBPD, "C0: CC OVP, SBU OVP, or thermal event");
+	pd_handle_cc_overvoltage(0);
+}
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_1] = {
+		.name = "TEMP_SENSOR1",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_2] = {
+		.name = "TEMP_SENSOR2",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_VSNS_PP3300_A] = {
+		.name = "PP3300_A_PGOOD",
+		.input_ch = NPCX_ADC_CH9,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* Thermistors */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Charger",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_A                \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(85), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A;
+
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_B                \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(73), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(85), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_b = THERMAL_B;
+
+struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
+
+static void setup_thermal(void)
+{
+	thermal_params[TEMP_SENSOR_1] = thermal_a;
+	thermal_params[TEMP_SENSOR_2] = thermal_b;
+}
+
+void board_hibernate(void)
+{
+	/*
+	 * Both charger ICs need to be put into their "low power mode" before
+	 * entering the Z-state.
+	 */
+	if (board_get_charger_chip_count() > 1)
+		raa489000_hibernate(1, true);
+	raa489000_hibernate(0, true);
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * TODO(b:147316511): Here we could issue a digital reset to the IC,
+	 * unsure if we actually want to do that or not yet.
+	 */
+}
+
+static void set_5v_gpio(int level)
+{
+	gpio_set_level(GPIO_EN_PP5000, level);
+	gpio_set_level(GPIO_EN_USB_A0_VBUS, level);
+}
+
+__override void board_power_5v_enable(int enable)
+{
+	/*
+	 * Port 0 simply has a GPIO to turn on the 5V regulator, however, 5V is
+	 * generated locally on the sub board and we need to set the comparator
+	 * polarity on the sub board charger IC.
+	 */
+	set_5v_gpio(!!enable);
+}
+
+__override uint8_t board_get_usb_pd_port_count(void)
+{
+	return CONFIG_USB_PD_PORT_MAX_COUNT;
+}
+
+__override uint8_t board_get_charger_chip_count(void)
+{
+	return CHARGER_NUM;
+}
+
+int board_is_sourcing_vbus(int port)
+{
+	int regval;
+
+	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
+	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count());
+	int i;
+	int old_port;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	old_port = charge_manager_get_active_charge_port();
+
+	CPRINTS("New chg p%d", port);
+
+	/* Disable all ports. */
+	if (port == CHARGE_PORT_NONE) {
+		for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+			tcpc_write(i, TCPC_REG_COMMAND,
+				   TCPC_REG_COMMAND_SNK_CTRL_LOW);
+			raa489000_enable_asgate(i, false);
+		}
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if port is sourcing VBUS. */
+	if (board_is_sourcing_vbus(port)) {
+		CPRINTS("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+		if (i == port)
+			continue;
+
+		if (tcpc_write(i, TCPC_REG_COMMAND,
+			       TCPC_REG_COMMAND_SNK_CTRL_LOW))
+			CPRINTS("p%d: sink path disable failed.", i);
+		raa489000_enable_asgate(i, false);
+	}
+
+	/*
+	 * Stop the charger IC from switching while changing ports.  Otherwise,
+	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
+	 */
+	if (old_port != CHARGE_PORT_NONE)
+		charger_discharge_on_ac(1);
+
+	/* Enable requested charge port. */
+	if (raa489000_enable_asgate(port, true) ||
+	    tcpc_write(port, TCPC_REG_COMMAND,
+		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
+		CPRINTS("p%d: sink path enable failed.", port);
+		charger_discharge_on_ac(0);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	/* Allow the charger IC to begin/continue switching. */
+	charger_discharge_on_ac(0);
+
+	return EC_SUCCESS;
+}
+
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	if (port < 0 || port > board_get_usb_pd_port_count())
+		return;
+
+	raa489000_set_output_current(port, rp);
+}
+
+void board_init(void)
+{
+	int on;
+
+	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
+	check_c0_line();
+
+	/* Turn on 5V if the system is on, otherwise turn it off. */
+	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
+			      CHIPSET_STATE_SOFT_OFF);
+	board_power_5v_enable(on);
+
+	/* Initialize THERMAL */
+	setup_thermal();
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+/* Enable HDMI any time the SoC is on */
+static void hdmi_enable(void)
+{
+	if (get_cbi_fw_config_hdmi() == HDMI_PRESENT) {
+		gpio_set_level(GPIO_EC_HDMI_EN_ODL, 0);
+		gpio_set_level(GPIO_HDMI_PP3300_EN, 1);
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, hdmi_enable, HOOK_PRIO_DEFAULT);
+
+static void hdmi_disable(void)
+{
+	if (get_cbi_fw_config_hdmi() == HDMI_PRESENT) {
+		gpio_set_level(GPIO_EC_HDMI_EN_ODL, 1);
+		gpio_set_level(GPIO_HDMI_PP3300_EN, 0);
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, hdmi_disable, HOOK_PRIO_DEFAULT);
+
+__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+				       int *ki_div, int *kd, int *kd_div)
+{
+	*kp = 1;
+	*kp_div = 20;
+	*ki = 1;
+	*ki_div = 250;
+	*kd = 0;
+	*kd_div = 1;
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	return pd_check_vbus_level(port, VBUS_PRESENT);
+}
+
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+};
+const unsigned int chg_cnt = ARRAY_SIZE(chg_chips);
+
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	{
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+		.flags = PI3USB9201_ALWAYS_POWERED,
+	},
+};
+
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0,
+			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
+		},
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+		.drv = &raa489000_tcpm_drv,
+	},
+};
+
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
+				.driver = &pi3usb3x532_usb_mux_driver,
+			},
+	},
+};
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+	int regval;
+
+	/*
+	 * The interrupt line is shared between the TCPC and BC1.2 detector IC.
+	 * Therefore, go out and actually read the alert registers to report the
+	 * alert status.
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
+			/* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */
+			if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0))
+				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
+
+			if (regval)
+				status |= PD_STATUS_TCPC_ALERT_0;
+		}
+	}
+
+	return status;
+}
+
+int adc_to_physical_value(enum gpio_signal gpio)
+{
+	if (gpio == GPIO_VOLUME_UP_L)
+		return !!(new_adc_key_state & ADC_VOL_UP_MASK);
+	else if (gpio == GPIO_VOLUME_DOWN_L)
+		return !!(new_adc_key_state & ADC_VOL_DOWN_MASK);
+
+	CPRINTS("Not a volume up or down key");
+	return 0;
+}
+
+int button_is_adc_detected(enum gpio_signal gpio)
+{
+	return (gpio == GPIO_VOLUME_DOWN_L) || (gpio == GPIO_VOLUME_UP_L);
+}
+
+static void board_extpower(void)
+{
+	int extpower_present;
+
+	if (pd_is_connected(0))
+		extpower_present = extpower_is_present();
+	else
+		extpower_present = 0;
+
+	gpio_set_level(GPIO_EC_ACOK_OTG, extpower_present);
+}
+DECLARE_HOOK(HOOK_AC_CHANGE, board_extpower, HOOK_PRIO_DEFAULT);
diff --git a/board/driblee/board.h b/board/driblee/board.h
new file mode 100644
index 0000000000..e2d51723c0
--- /dev/null
+++ b/board/driblee/board.h
@@ -0,0 +1,155 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Lalala board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#define VARIANT_KEEBY_EC_NPCX797FC
+#include "baseboard.h"
+
+/*
+ * The RAM and flash size combination on the the NPCX797FC does not leave
+ * any unused flash space that can be used to store the .init_rom section.
+ */
+#undef CONFIG_CHIP_INIT_ROM_REGION
+
+/* Battery */
+#define CONFIG_BATTERY_FUEL_GAUGE
+#define CONFIG_BATTERY_V2
+#define CONFIG_BATTERY_COUNT 1
+#define CONFIG_HOSTCMD_BATTERY_V2
+
+/* Charger */
+#define CONFIG_CHARGER_RAA489000
+#define PD_MAX_VOLTAGE_MV 20000
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#undef CONFIG_CMD_CHARGER_DUMP
+#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
+#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
+/*
+ * b/147463641: The charger IC seems to overdraw ~4%, therefore we
+ * reduce our target accordingly.
+ */
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 4
+#define CONFIG_MATH_UTIL
+#define CONFIG_CHARGER_PROFILE_OVERRIDE
+#define CHARGING_CURRENT_1100MA 1100
+
+/*
+ * GPIO for C1 interrupts, for baseboard use
+ *
+ * Note this line might already have its pull up disabled for HDMI DBs, but
+ * it should be fine to set again before z-state.
+ */
+#define GPIO_EC_HDMI_EN_ODL GPIO_EC_I2C_SBU_USB_C1_SCL
+#define GPIO_HDMI_PP3300_EN GPIO_SUB_USB_C1_INT_ODL
+
+/* LED defines */
+#define CONFIG_LED_ONOFF_STATES
+#define CONFIG_LED_COMMON
+#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
+
+/* PWM */
+#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */
+
+/* Temp sensor */
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_THERMISTOR
+#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
+
+/* USB */
+#define CONFIG_BC12_DETECT_PI3USB9201
+#define CONFIG_USBC_RETIMER_PS8802
+
+/* Common USB-A defines */
+#define USB_PORT_COUNT 1
+#define CONFIG_USB_PORT_POWER_SMART
+#undef CONFIG_USB_PORT_POWER_SMART_PORT_COUNT
+#define CONFIG_USB_PORT_POWER_SMART_PORT_COUNT 1
+#define CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY
+#define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_CDP
+#define CONFIG_USB_PORT_POWER_SMART_INVERTED
+#define GPIO_USB1_ILIM_SEL GPIO_USB_A0_CHARGE_EN_L
+
+/******************************************************************************/
+
+/* USB PD */
+#define CONFIG_USB_PD_PORT_MAX_COUNT 1
+#define CONFIG_USB_PD_TCPM_RAA489000
+
+/* USB defines specific to external TCPCs */
+#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+#define CONFIG_USB_PD_VBUS_DETECT_TCPC
+#define CONFIG_USB_PD_DISCHARGE_TCPC
+#define CONFIG_USB_PD_TCPC_LOW_POWER
+
+/* Variant references the TCPCs to determine Vbus sourcing */
+#define CONFIG_USB_PD_5V_EN_CUSTOM
+
+/* I2C configuration */
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
+#define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0
+/* TODO(b:147440290): Need to handle multiple charger ICs */
+#define I2C_PORT_CHARGER I2C_PORT_USB_C0
+
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */
+
+/* Volume Button feature */
+#define CONFIG_ADC_BUTTONS
+#define CONFIG_VOLUME_BUTTONS
+#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum adc_channel {
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
+	ADC_VSNS_PP3300_A, /* ADC9 */
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT };
+
+/* List of possible batteries */
+enum battery_type {
+	BATTERY_BYD_1VX1H,
+	BATTERY_BYD_YT39X,
+	BATTERY_BYD_X0Y5M,
+	BATTERY_LGC_FDRHM,
+	BATTERY_LGC_8GHCX,
+	BATTERY_SWD_ATL_WJPC4,
+	BATTERY_SWD_ATL_CTGKT,
+	BATTERY_SWD_COS_WJPC4,
+	BATTERY_SWD_COS_CTGKT,
+	BATTERY_SMP_ATL_VM732,
+	BATTERY_SMP_ATL_26JGK,
+	BATTERY_SMP_ATL_RF9H3,
+	BATTERY_SMP_COS_VM732,
+	BATTERY_SMP_COS_26JGK,
+	BATTERY_SMP_COS_RF9H3,
+	BATTERY_BYD16,
+	BATTERY_LGC3,
+	BATTERY_SIMPLO,
+	BATTERY_SIMPLO_LS,
+	BATTERY_TYPE_COUNT,
+};
+
+int board_is_sourcing_vbus(int port);
+#endif /* !__ASSEMBLER__ */
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/driblee/build.mk b/board/driblee/build.mk
new file mode 100644
index 0000000000..eb422dae93
--- /dev/null
+++ b/board/driblee/build.mk
@@ -0,0 +1,14 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx7
+CHIP_VARIANT:=npcx7m7fc
+BASEBOARD:=keeby
+
+board-y=board.o battery.o cbi_ssfc.o led.o usb_pd_policy.o
diff --git a/board/driblee/cbi_ssfc.c b/board/driblee/cbi_ssfc.c
new file mode 100644
index 0000000000..81f3ee0dad
--- /dev/null
+++ b/board/driblee/cbi_ssfc.c
@@ -0,0 +1,36 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi_ssfc.h"
+#include "common.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "hooks.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+/* Cache SSFC on init since we don't expect it to change in runtime */
+static union dedede_cbi_ssfc cached_ssfc;
+BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
+
+static void cbi_ssfc_init(void)
+{
+	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
+		/* Default to 0 when CBI isn't populated */
+		cached_ssfc.raw_value = 0;
+
+	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
+}
+DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
+
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
+{
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
+}
+
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
+{
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
+}
diff --git a/board/driblee/cbi_ssfc.h b/board/driblee/cbi_ssfc.h
new file mode 100644
index 0000000000..bf8853a43a
--- /dev/null
+++ b/board/driblee/cbi_ssfc.h
@@ -0,0 +1,59 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _DEDEDE_CBI_SSFC__H_
+#define _DEDEDE_CBI_SSFC__H_
+
+#include "stdint.h"
+
+/****************************************************************************
+ * Dedede CBI Second Source Factory Cache
+ */
+
+/*
+ * Base Sensor (Bits 0-2)
+ */
+enum ec_ssfc_base_sensor {
+	SSFC_SENSOR_BASE_DEFAULT = 0,
+	SSFC_SENSOR_BMI160 = 1,
+	SSFC_SENSOR_ICM426XX = 2,
+	SSFC_SENSOR_LSM6DSM = 3,
+	SSFC_SENSOR_ICM42607 = 4
+};
+
+/*
+ * Lid Sensor (Bits 3-5)
+ */
+enum ec_ssfc_lid_sensor {
+	SSFC_SENSOR_LID_DEFAULT = 0,
+	SSFC_SENSOR_BMA255 = 1,
+	SSFC_SENSOR_KX022 = 2,
+	SSFC_SENSOR_LIS2DWL = 3
+};
+
+union dedede_cbi_ssfc {
+	struct {
+		uint32_t base_sensor : 3;
+		uint32_t lid_sensor : 3;
+		uint32_t reserved_2 : 26;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Get the Base sensor type from SSFC_CONFIG.
+ *
+ * @return the Base sensor board type.
+ */
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
+
+/**
+ * Get the Lid sensor type from SSFC_CONFIG.
+ *
+ * @return the Lid sensor board type.
+ */
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
+
+#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/driblee/ec.tasklist b/board/driblee/ec.tasklist
new file mode 100644
index 0000000000..386e8625b3
--- /dev/null
+++ b/board/driblee/ec.tasklist
@@ -0,0 +1,21 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE)
diff --git a/board/driblee/gpio.inc b/board/driblee/gpio.inc
new file mode 100644
index 0000000000..acd6a33852
--- /dev/null
+++ b/board/driblee/gpio.inc
@@ -0,0 +1,141 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first.
+ */
+
+/* Power Interrupts */
+GPIO_INT(SLP_S0_L,		 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,		 PIN(A, 5), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(SLP_S4_L,		 PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,		 PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(RSMRST_PWRGD_L,	 PIN(C, 6), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID1,	 PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(CPU_C10_GATE_L,	 PIN(6, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID0,	 PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, power_signal_interrupt)
+GPIO_INT(PG_VCCIO_EXT_OD,	 PIN(B, 0), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(PG_PP5000_U_OD,	 PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_DRAM_OD,		 PIN(E, 4), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(PG_PP1050_ST_OD,	 PIN(4, 2), GPIO_INT_BOTH, power_signal_interrupt)
+
+/* USB-C interrupts */
+GPIO_INT(USB_C0_INT_ODL,	 PIN(6, 2), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt)
+GPIO_INT(EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL,	PIN(9, 1), GPIO_INT_BOTH, sub_hdmi_hpd_interrupt) /* HDMI_HPD */
+GPIO_INT(USB_C0_CCSBU_OVP_ODL,	PIN(A, 2), GPIO_INT_FALLING | GPIO_PULL_UP, c0_ccsbu_ovp_interrupt) /* Fault protection */
+
+/* Button interrupts */
+GPIO_INT(EC_PWR_BTN_ODL,	 PIN(0, 1), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
+
+/* Other interrupts */
+GPIO_INT(LID_OPEN,		 PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)
+GPIO_INT(EC_WP_OD,		 PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+
+/* I2C Ports */
+GPIO(EC_I2C_EEPROM_SCL,	      PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SDA,	      PIN(B, 2), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SCL,      PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SDA,      PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,	      PIN(B, 5), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SDA,	      PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SCL,	      PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SDA,	      PIN(8, 7), GPIO_INPUT)
+
+/* Misc Enables */
+GPIO(EN_VCCIO_EXT,   PIN(6, 1), GPIO_OUT_LOW)
+/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
+GPIO(EN_VCCST,		PIN(A, 7), GPIO_INPUT)
+GPIO(EN_PP3300_A,	PIN(0, 3), GPIO_OUT_LOW)
+GPIO(EN_PP5000_U,	PIN(A, 4), GPIO_OUT_LOW)
+GPIO(EN_SLP_Z,		PIN(8, 3), GPIO_OUT_LOW)
+GPIO(EN_BL_OD,		PIN(D, 3), GPIO_ODR_LOW)
+GPIO(EC_CBI_WP,		PIN(E, 5), GPIO_OUT_LOW)
+GPIO(SUB_USB_C1_INT_ODL,    PIN(F, 5), GPIO_OUT_LOW) /* 5V power en */
+GPIO(EC_I2C_SBU_USB_C1_SCL,	PIN(9, 2), GPIO_ODR_LOW) /* HDMI en */
+
+/* LED */
+GPIO(LED_1_PWR_WHITE_L,	 PIN(C, 3), GPIO_OUT_HIGH)
+GPIO(LED_2_CHG_AMBER_L,	 PIN(C, 4), GPIO_OUT_HIGH)
+
+/* Power Sequencing */
+GPIO(EC_AP_PSYS,	     PIN(B, 7), GPIO_OUT_LOW)
+GPIO(EC_AP_RSMRST_L,         PIN(A, 6), GPIO_OUT_LOW)
+GPIO(EC_AP_PWR_BTN_ODL,      PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(EC_AP_RTCRST,           PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_AP_WAKE_ODL,         PIN(7, 4), GPIO_ODR_HIGH)
+GPIO(EC_AP_DPWROK,	     PIN(A, 3), GPIO_OUT_LOW)
+GPIO(EC_AP_PCH_PWROK_OD,     PIN(9, 4), GPIO_ODR_LOW)
+GPIO(EC_AP_VCCST_PWRGD_OD,   PIN(B, 1), GPIO_ODR_LOW)
+GPIO(EC_AP_SYS_PWROK,	     PIN(0, 2), GPIO_OUT_LOW)
+GPIO(EC_AP_MKBP_INT_L,	     PIN(7, 0), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_ODL,	     PIN(F, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(EC_ENTERING_RW,	     PIN(E, 3), GPIO_OUT_LOW)
+GPIO(ALL_SYS_PWRGD,	     PIN(A, 0), GPIO_OUT_LOW)
+GPIO(SYS_RST_ODL,	     PIN(C, 5), GPIO_ODR_HIGH)
+
+/* USB pins */
+GPIO(EC_AP_USB_C1_HDMI_HPD,  PIN(9, 6), GPIO_OUT_LOW)
+GPIO(EC_AP_USB_C0_HPD,	     PIN(9, 3), GPIO_OUT_LOW)
+GPIO(EC_BATTERY_PRES_ODL,    PIN(E, 1), GPIO_INPUT)
+GPIO(EN_USB_A0_VBUS,	 PIN(4, 1), GPIO_OUT_LOW)		/* Enable A0 5V Charging */
+GPIO(USB_A0_CHARGE_EN_L,	PIN(6, 3), GPIO_OUT_HIGH)  /* Reverse: Enable A0 1.5A Charging */
+/*
+ * Lalala doesn't have these physical pins coming to the EC but uses other
+ * logic.
+ */
+UNIMPLEMENTED(AC_PRESENT)
+UNIMPLEMENTED(PG_EC_DSW_PWROK)
+UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
+UNIMPLEMENTED(VOLDN_BTN_ODL)
+UNIMPLEMENTED(VOLUP_BTN_ODL)
+
+/* Alternate Functions */
+/* ADC */
+ALTERNATE(PIN_MASK(F, BIT(0)), 0, MODULE_ADC, 0) /* ADC9 */
+ALTERNATE(PIN_MASK(4, 0x30), 0, MODULE_ADC, 0)   /* ADC0-1 */
+
+/* Keyboard */
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI0, KSI1 */
+ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI2-7 */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO0, KSO1 */
+ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO3-9 */
+ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO10-13 */
+ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO14 */
+GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW)	/* KSO2 inverted */
+
+/* UART */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)  /* UART1 */
+
+/* I2C */
+ALTERNATE(PIN_MASK(B, 0x3C), 0, MODULE_I2C, 0)   /* I2C7,I2C0 */
+ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)   /* I2C5 */
+ALTERNATE(PIN_MASK(9, 0x01), 0, MODULE_I2C, 0)   /* I2C2, I2C1 SCL */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)   /* I2C1 SDA */
+
+GPIO(EC_ACOK_OTG, PIN(C, 0), GPIO_OUT_LOW)  /* OTG-OVP protect enable */
+
+/* NC pins, enable internal pull-up to avoid floating state. */
+GPIO(GPIO32_NC, PIN(3, 2), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO35_NC, PIN(3, 5), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO43_NC, PIN(4, 3), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO57_NC, PIN(5, 7), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO81_NC, PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO86_NC, PIN(8, 6), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOD0_NC, PIN(D, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOD1_NC, PIN(D, 1), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOD6_NC, PIN(D, 6), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOE0_NC, PIN(E, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO40_NC, PIN(4, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO50_NC, PIN(5, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO34_NC, PIN(3, 4), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO37_NC, PIN(3, 7), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOF2_NC, PIN(F, 2), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOF3_NC, PIN(F, 3), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO72_NC, PIN(7, 2), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO73_NC, PIN(7, 3), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO75_NC, PIN(7, 5), GPIO_INPUT | GPIO_PULL_UP)
diff --git a/board/driblee/led.c b/board/driblee/led.c
new file mode 100644
index 0000000000..4eecb2c590
--- /dev/null
+++ b/board/driblee/led.c
@@ -0,0 +1,88 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power and battery LED control for lalala
+ */
+
+#include "chipset.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+
+#define LED_ON_LVL 0
+#define LED_OFF_LVL 1
+
+__override const int led_charge_lvl_1 = 10;
+
+__override const int led_charge_lvl_2 = 100;
+
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     1 * LED_ONE_SEC },
+					   { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_WHITE,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
+BUILD_ASSERT(ARRAY_SIZE(led_bat_state_table) == LED_NUM_STATES);
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_WHITE:
+		gpio_set_level(GPIO_LED_1_PWR_WHITE_L, LED_ON_LVL);
+		gpio_set_level(GPIO_LED_2_CHG_AMBER_L, LED_OFF_LVL);
+		break;
+	case EC_LED_COLOR_AMBER:
+		gpio_set_level(GPIO_LED_1_PWR_WHITE_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_2_CHG_AMBER_L, LED_ON_LVL);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		gpio_set_level(GPIO_LED_1_PWR_WHITE_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_2_CHG_AMBER_L, LED_OFF_LVL);
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	brightness_range[EC_LED_COLOR_WHITE] = 1;
+	brightness_range[EC_LED_COLOR_AMBER] = 1;
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (brightness[EC_LED_COLOR_WHITE] != 0)
+		led_set_color_battery(EC_LED_COLOR_WHITE);
+	else if (brightness[EC_LED_COLOR_AMBER] != 0)
+		led_set_color_battery(EC_LED_COLOR_AMBER);
+	else
+		led_set_color_battery(LED_OFF);
+
+	return EC_SUCCESS;
+}
diff --git a/board/driblee/usb_pd_policy.c b/board/driblee/usb_pd_policy.c
new file mode 100644
index 0000000000..f8a1ee83a2
--- /dev/null
+++ b/board/driblee/usb_pd_policy.c
@@ -0,0 +1,61 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "driver/charger/isl923x_public.h"
+#include "driver/tcpm/tcpci.h"
+#include "usb_pd.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+int pd_check_vconn_swap(int port)
+{
+	/* Allow VCONN swaps if the AP is on. */
+	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
+}
+
+void pd_power_supply_reset(int port)
+{
+	/* Disable VBUS */
+	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	if (port >= CONFIG_USB_PD_PORT_MAX_COUNT)
+		return EC_ERROR_INVAL;
+
+	/* Disable charging. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
+	if (rv)
+		return rv;
+
+	/* Our policy is not to source VBUS when the AP is off. */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	/* Provide Vbus. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
+	if (rv)
+		return rv;
+
+	rv = raa489000_enable_asgate(port, true);
+	if (rv)
+		return rv;
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
diff --git a/board/driblee/vif_override.xml b/board/driblee/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/driblee/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/drobit/battery.c b/board/drobit/battery.c
new file mode 100644
index 0000000000..0db543a12f
--- /dev/null
+++ b/board/drobit/battery.c
@@ -0,0 +1,65 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "common.h"
+#include "util.h"
+
+/*
+ * Battery info for all Volteer battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	/* C490-42 Battery Information */
+	[BATTERY_C490] = {
+		.fuel_gauge = {
+			.manuf_name = "AS3GWQd3jB",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x10, 0x10 },
+			},
+			.fet = {
+				.reg_addr = 0x99,
+				.reg_mask = 0x000c,
+				.disconnect_val = 0x000c,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13200, /* mV */
+			.voltage_normal		= 11550, /* mV */
+			.voltage_min		= 9000, /* mV */
+			.precharge_current	= 256,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 45,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 60,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_C490;
diff --git a/board/drobit/board.c b/board/drobit/board.c
new file mode 100644
index 0000000000..ab4e98c887
--- /dev/null
+++ b/board/drobit/board.c
@@ -0,0 +1,478 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Volteer board-specific configuration */
+#include "accelgyro.h"
+#include "button.h"
+#include "cbi_ec_fw_config.h"
+#include "charge_state.h"
+#include "common.h"
+#include "driver/bc12/pi3usb9201.h"
+#include "driver/ppc/syv682x.h"
+#include "driver/retimer/bb_retimer_public.h"
+#include "driver/sync.h"
+#include "driver/tcpm/rt1715.h"
+#include "driver/tcpm/tcpci.h"
+#include "extpower.h"
+#include "fan.h"
+#include "fan_chip.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "keyboard_raw.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "switch.h"
+#include "system.h"
+#include "task.h"
+#include "throttle_ap.h"
+#include "uart.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tbt.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/* Increase from 50 us, because KSO_02 passes through the H1. */
+	.output_settle_us = 80,
+	/* Other values should be the same as the default configuration. */
+	.debounce_down_us = 9 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x1c, 0xfe, 0xff, 0xff, 0xff, 0xf5, 0xff,
+		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
+	},
+};
+
+static const struct ec_response_keybd_config drobit_kb = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &drobit_kb;
+}
+
+/******************************************************************************/
+/*
+ * FW_CONFIG defaults for Volteer if the CBI data is not initialized.
+ */
+union volteer_cbi_fw_config fw_config_defaults = {
+	.usb_db = DB_USB4_GEN3,
+};
+
+/******************************************************************************/
+/* Physical fans. These are logically separate from pwm_channels. */
+
+const struct fan_conf fan_conf_0 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
+	.pgood_gpio = -1,
+	.enable_gpio = GPIO_EN_PP5000_FAN,
+};
+
+/*
+ * Fan specs from datasheet:
+ * Max speed 5900 rpm (+/- 7%), minimum duty cycle 30%.
+ * Minimum speed not specified by RPM. Set minimum RPM to max speed (with
+ * margin) x 30%.
+ *    5900 x 1.07 x 0.30 = 1894, round up to 1900
+ */
+const struct fan_rpm fan_rpm_0 = {
+	.rpm_min = 1900,
+	.rpm_start = 1900,
+	.rpm_max = 5900,
+};
+
+const struct fan_t fans[FAN_CH_COUNT] = {
+	[FAN_CH_0] = {
+		.conf = &fan_conf_0,
+		.rpm = &fan_rpm_0,
+	},
+};
+
+/******************************************************************************/
+/* EC thermal management configuration */
+
+/*
+ * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
+ * 130 C.  However, sensor is located next to DDR, so we need to use the lower
+ * DDR temperature limit (85 C)
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(72), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+		}, \
+		.temp_fan_off = C_TO_K(35), \
+		.temp_fan_max = C_TO_K(75), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
+
+/*
+ * Inductor limits - used for both charger and PP3300 regulator
+ *
+ * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
+ *
+ * Charger max recommended temperature 100C, max absolute temperature 125C
+ * PP3300 regulator: operating range -40 C to 145 C
+ *
+ * Inductors: limit of 125c
+ * PCB: limit is 80c
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_INDUCTOR         \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(72), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+		}, \
+		.temp_fan_off = C_TO_K(40), \
+		.temp_fan_max = C_TO_K(75), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_inductor =
+	THERMAL_INDUCTOR;
+
+struct ec_thermal_config thermal_params[] = {
+	[TEMP_SENSOR_1_CHARGER] = THERMAL_INDUCTOR,
+	[TEMP_SENSOR_2_PP3300_REGULATOR] = THERMAL_INDUCTOR,
+	[TEMP_SENSOR_3_DDR_SOC] = THERMAL_CPU,
+	[TEMP_SENSOR_4_FAN] = THERMAL_CPU,
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
+
+/******************************************************************************/
+/* MFT channels. These are logically separate from pwm_channels. */
+const struct mft_t mft_channels[] = {
+	[MFT_CH_0] = {
+		.module = NPCX_MFT_MODULE_1,
+		.clk_src = TCKC_LFCLK,
+		.pwm_id = PWM_CH_FAN,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
+
+/******************************************************************************/
+/* I2C port map configuration */
+const struct i2c_port_t i2c_ports[] = {
+	{
+		.name = "usb_c1_mix",
+		.port = I2C_PORT_USB_C1_MIX,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C0_USB_C1_MIX_SCL,
+		.sda = GPIO_EC_I2C0_USB_C1_MIX_SDA,
+	},
+	{
+		.name = "usb_c0",
+		.port = I2C_PORT_USB_C0,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C1_USB_C0_SCL,
+		.sda = GPIO_EC_I2C1_USB_C0_SDA,
+	},
+	{
+		.name = "usb_c1",
+		.port = I2C_PORT_USB_C1,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C2_USB_C1_SCL,
+		.sda = GPIO_EC_I2C2_USB_C1_SDA,
+	},
+	{
+		.name = "usb_1_mix",
+		.port = I2C_PORT_USB_1_MIX,
+		.kbps = 100,
+		.scl = GPIO_EC_I2C3_USB_1_MIX_SCL,
+		.sda = GPIO_EC_I2C3_USB_1_MIX_SDA,
+	},
+	{
+		.name = "power",
+		.port = I2C_PORT_POWER,
+		.kbps = 100,
+		.scl = GPIO_EC_I2C5_BATTERY_SCL,
+		.sda = GPIO_EC_I2C5_BATTERY_SDA,
+	},
+	{
+		.name = "eeprom",
+		.port = I2C_PORT_EEPROM,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C7_EEPROM_PWR_SCL_R,
+		.sda = GPIO_EC_I2C7_EEPROM_PWR_SDA_R,
+	},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+/******************************************************************************/
+/* PWM configuration */
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_FAN] = {
+		.channel = 5,
+		.flags = PWM_CONFIG_OPEN_DRAIN,
+		.freq = 25000
+	},
+	[PWM_CH_KBLIGHT] = {
+		.channel = 3,
+		.flags = 0,
+		/*
+		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
+		 * flicker. Higher frequencies consume similar average power to
+		 * lower PWM frequencies, but higher frequencies record a much
+		 * lower maximum power.
+		 */
+		.freq = 10000,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+/******************************************************************************/
+/* USB-A charging control */
+
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_PP5000_USBA,
+};
+
+void board_reset_pd_mcu(void)
+{
+}
+
+/******************************************************************************/
+/* USBC PPC configuration */
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.frs_en = GPIO_USB_C0_FRS_EN,
+		.drv = &syv682x_drv,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C1,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.frs_en = GPIO_USB_C1_FRS_EN,
+		.drv = &syv682x_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/******************************************************************************/
+/* PPC support routines */
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C1);
+		break;
+	default:
+		break;
+	}
+}
+
+/* Disable FRS on boards with the SYV682A. FRS only works on the SYV682B. */
+void setup_board_ppc(void)
+{
+	uint8_t board_id = get_board_id();
+
+	if (board_id < 2) {
+		ppc_chips[USBC_PORT_C0].frs_en = 0;
+		ppc_chips[USBC_PORT_C1].frs_en = 0;
+	}
+}
+
+__override void board_cbi_init(void)
+{
+	setup_board_ppc();
+}
+
+/******************************************************************************/
+/* BC1.2 charger detect configuration */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C1,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
+
+/******************************************************************************/
+/* USBC TCPC configuration */
+struct tcpc_config_t tcpc_config[] = {
+	[USBC_PORT_C0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0,
+			.addr_flags = RT1715_I2C_ADDR_FLAGS,
+		},
+		.drv = &rt1715_tcpm_drv,
+	},
+	[USBC_PORT_C1] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C1,
+			.addr_flags = RT1715_I2C_ADDR_FLAGS,
+		},
+		.drv = &rt1715_tcpm_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
+BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
+
+/******************************************************************************/
+/* USBC mux configuration - Tiger Lake includes internal mux */
+struct usb_mux_chain usbc0_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+struct usb_mux_chain usbc1_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+
+struct usb_mux_chain usb_muxes[] = {
+	[USBC_PORT_C0] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_1_MIX,
+			.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc0_tcss_usb_mux,
+	},
+	[USBC_PORT_C1] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_1_MIX,
+			.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc1_tcss_usb_mux,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
+
+struct bb_usb_control bb_controls[] = {
+	[USBC_PORT_C0] = {
+		.usb_ls_en_gpio = GPIO_USB_C0_LS_EN,
+		.retimer_rst_gpio = GPIO_USB_C0_RT_RST_ODL,
+	},
+	[USBC_PORT_C1] = {
+		.usb_ls_en_gpio = GPIO_USB_C1_LS_EN,
+		.retimer_rst_gpio = GPIO_USB_C1_RT_RST_ODL,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(bb_controls) == USBC_PORT_COUNT);
+
+static void board_tcpc_init(void)
+{
+	/* Don't reset TCPCs after initial reset */
+	if (!system_jumped_late())
+		board_reset_pd_mcu();
+
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
+
+	/* Enable BC1.2 interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
+
+/******************************************************************************/
+/* TCPC support routines */
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	/*
+	 * Check which port has the ALERT line set
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL))
+		status |= PD_STATUS_TCPC_ALERT_0;
+	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL))
+		status |= PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
+
+int ppc_get_alert_status(int port)
+{
+	if (port == USBC_PORT_C0)
+		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
+	else
+		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
+}
+
+/* Called on AP S0ix -> S0 tranition */
+static void board_chipset_resume(void)
+{
+	gpio_set_level(GPIO_EC_KB_BL_EN, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S0 -> S0ix transition */
+static void board_chipset_suspend(void)
+{
+	gpio_set_level(GPIO_EC_KB_BL_EN, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
diff --git a/board/drobit/board.h b/board/drobit/board.h
new file mode 100644
index 0000000000..c8e51962fa
--- /dev/null
+++ b/board/drobit/board.h
@@ -0,0 +1,161 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Volteer board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* Baseboard features */
+#include "baseboard.h"
+
+/*
+ * The RAM and flash size combination on the NPCX797FC dose not leave
+ * any unused flash space that can be used to store the .init_rom section.
+ */
+#undef CONFIG_CHIP_INIT_ROM_REGION
+
+#define CONFIG_VBOOT_EFS2
+
+#define CONFIG_POWER_BUTTON
+
+#undef CONFIG_UART_TX_BUF_SIZE
+#define CONFIG_UART_TX_BUF_SIZE 4096
+
+/* Chipset features */
+#define CONFIG_POWER_PP5000_CONTROL
+
+/* LED defines */
+#define CONFIG_LED_ONOFF_STATES
+#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
+
+/* Keyboard features */
+#define CONFIG_KEYBOARD_VIVALDI
+#define CONFIG_KEYBOARD_REFRESH_ROW3
+
+/* Sensors */
+#undef CONFIG_TABLET_MODE
+#undef CONFIG_GMR_TABLET_MODE
+#undef CONFIG_ACCEL_FIFO
+#undef CONFIG_ACCEL_FIFO_SIZE
+
+/* USB Type C and USB PD defines */
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+
+/* TODO: b/144165680 - measure and check these values on Volteer */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+
+/*
+ * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
+ * cables only support up to 60W.
+ */
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
+
+#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
+#ifdef BOARD_DROBIT_ECMODEENTRY
+#undef CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
+#endif
+
+/* Enabling Thunderbolt-compatible mode */
+#define CONFIG_USB_PD_TBT_COMPAT_MODE
+
+/* Enabling USB4 mode */
+#define CONFIG_USB_PD_USB4
+
+#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x40
+#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x41
+
+/* USB Type A Features */
+#define USB_PORT_COUNT 1
+#define CONFIG_USB_PORT_POWER_DUMB
+
+/* USBC PPC*/
+#define CONFIG_USBC_PPC_SYV682X
+#define CONFIG_USB_PD_FRS_PPC
+
+/* BC 1.2 */
+
+/* Volume Button feature */
+#undef CONFIG_VOLUME_BUTTONS
+
+/* Fan features */
+
+/* charger defines */
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 2
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_LID_OPEN GPIO_EC_LID_OPEN
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL
+
+/* I2C Bus Configuration */
+#define CONFIG_I2C
+#define I2C_PORT_USB_C1_MIX NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT3_0
+#define I2C_PORT_POWER NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+
+#define I2C_PORT_BATTERY I2C_PORT_POWER
+#define I2C_PORT_CHARGER I2C_PORT_EEPROM
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+#define CONFIG_I2C_CONTROLLER
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum battery_type {
+	BATTERY_C490,
+	BATTERY_TYPE_COUNT,
+};
+
+enum pwm_channel { PWM_CH_FAN = 0, PWM_CH_KBLIGHT, PWM_CH_COUNT };
+
+enum sensor_id {
+	LID_ACCEL = 0,
+	BASE_ACCEL,
+	BASE_GYRO,
+	SENSOR_COUNT,
+};
+
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
+
+void board_reset_pd_mcu(void);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/drobit/build.mk b/board/drobit/build.mk
new file mode 100644
index 0000000000..d590255d2a
--- /dev/null
+++ b/board/drobit/build.mk
@@ -0,0 +1,16 @@
+# -*- makefile -*-
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx7
+CHIP_VARIANT:=npcx7m7fc
+BASEBOARD:=volteer
+
+board-y=board.o
+board-y+=battery.o
+board-y+=led.o
diff --git a/board/drobit/ec.tasklist b/board/drobit/ec.tasklist
new file mode 100644
index 0000000000..a1b5d30d93
--- /dev/null
+++ b/board/drobit/ec.tasklist
@@ -0,0 +1,26 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/drobit/gpio.inc b/board/drobit/gpio.inc
new file mode 100644
index 0000000000..2057cfd27a
--- /dev/null
+++ b/board/drobit/gpio.inc
@@ -0,0 +1,184 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+/* Wake Source interrupts */
+GPIO_INT(EC_LID_OPEN,          PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
+GPIO_INT(EC_WP_L,              PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(H1_EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
+GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
+
+/* Power sequencing interrupts */
+GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
+#endif
+GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_EC_RSMRST_ODL,     PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_EC_DSW_PWROK,      PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
+
+/* Sensor Interrupts */
+
+/*
+ * Lid g-sensor interrupt unused on Volteer, configure as regular input for
+ * power saving.
+ */
+
+/* USB-C interrupts */
+GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(E, 0), GPIO_INT_BOTH, tcpc_alert_event)
+GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(A, 2), GPIO_INT_BOTH, tcpc_alert_event)
+
+GPIO_INT(USB_C0_PPC_INT_ODL,	PIN(6, 2), GPIO_INT_BOTH, ppc_interrupt)
+GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(F, 5), GPIO_INT_BOTH, ppc_interrupt)
+
+GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(E, 4), GPIO_INT_BOTH, bc12_interrupt)
+GPIO_INT(USB_C1_MIX_INT_ODL,	PIN(0, 3), GPIO_INT_BOTH, bc12_interrupt)
+
+/* HDMI interrupts */
+
+/* Volume button interrupts */
+
+/* Power Sequencing Signals */
+GPIO(EN_PP3300_A,              PIN(A, 3), GPIO_OUT_LOW)
+GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
+GPIO(EN_PPVAR_VCCIN,           PIN(4, 3), GPIO_OUT_LOW) /* Enables VCCIN IMPV9 */
+GPIO(EC_PCH_DSW_PWROK,         PIN(C, 0), GPIO_OUT_LOW)
+
+/* Other wake sources */
+/*
+ * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an
+ * interrupt handler because it is automatically handled by the PSL.
+ *
+ * We need to lock the setting so this gpio can't be reconfigured to overdrive
+ * the real reset signal. (This is the PSL input pin not the real reset pin).
+ */
+GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH |
+					   GPIO_HIB_WAKE_HIGH |
+					   GPIO_LOCKED)
+
+/* AP/PCH Signals */
+GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
+GPIO(EC_PCH_RSMRST_ODL,        PIN(A, 6), GPIO_ODR_LOW) /* TODO - b/140950085 - implement TGL sequencing requirement */
+GPIO(EC_PCH_PWR_BTN_ODL,       PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
+GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
+GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
+GPIO_INT(EC_PROCHOT_IN_L,      PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
+GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
+
+GPIO(EC_PCH_INT_ODL,           PIN(B, 0), GPIO_ODR_HIGH)
+
+/* USB and USBC Signals */
+GPIO(EN_PP5000_USBA,		PIN(C, 6), GPIO_OUT_LOW)	/* Enable USB-A charging - all ports */
+GPIO(USB_A_LOW_PWR_OD,		PIN(6, 6), GPIO_ODR_LOW)	/* Don't limit USB-A charging by default - all ports */
+GPIO(USB_C0_RT_RST_ODL,		PIN(D, 4), GPIO_ODR_LOW)
+GPIO(USB_C1_RT_RST_ODL,		PIN(8, 3), GPIO_ODR_LOW)
+GPIO(USB_C0_OC_ODL,		PIN(B, 1), GPIO_ODR_HIGH)
+GPIO(USB_C1_OC_ODL,		PIN(5, 0), GPIO_ODR_HIGH)
+GPIO(USB_C0_FRS_EN,		PIN(6, 0), GPIO_OUT_LOW)
+GPIO(USB_C1_FRS_EN,		PIN(9, 4), GPIO_OUT_LOW)
+/* There is currently no need to service this interrupt. */
+GPIO(USB_C0_RT_INT_ODL,		PIN(F, 2), GPIO_INPUT)
+GPIO(USB_C1_RT_INT_ODL,		PIN(F, 3), GPIO_INPUT)
+
+/* Don't have a load switch for retimer */
+UNIMPLEMENTED(USB_C0_LS_EN)
+UNIMPLEMENTED(USB_C1_LS_EN)
+
+/* Misc Signals */
+GPIO(EC_H1_PACKET_MODE,		PIN(7, 5), GPIO_OUT_LOW)	/* H1 Packet Mode */
+/*
+ * Despite their names, M2_SSD_PLN and M2_SSD_PLA are active-low, and M2_SSD_PLN
+ * is open-drain.
+ * TODO(b/138954381): Change these names when they change on the schematic.
+ */
+GPIO(M2_SSD_PLN,		PIN(A, 0), GPIO_ODR_HIGH)	/* SSD power-loss notification */
+GPIO(M2_SSD_PLA,		PIN(7, 0), GPIO_INPUT)		/* SSD power-loss acknowledgment */
+GPIO(CCD_MODE_ODL,		PIN(E, 5), GPIO_INPUT)		/* Case Closed Debug Mode */
+GPIO(EC_SLP_S0IX,		PIN(7, 2), GPIO_INPUT | GPIO_PULL_UP)
+
+GPIO(LED_2_L,			PIN(C, 3), GPIO_OUT_HIGH)
+GPIO(LED_3_L,			PIN(C, 2), GPIO_OUT_HIGH)
+
+/* Unused signals */
+GPIO(UNUSED_GPIO41,		PIN(4, 1), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIO96,		PIN(9, 6), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIO34,		PIN(3, 4), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIO56,		PIN(5, 6), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIO81,		PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIO95,		PIN(9, 5), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIOC4,		PIN(C, 4), GPIO_INPUT | GPIO_PULL_UP)
+
+/* Only connected to test points */
+GPIO(EC_KB_BL_EN,		PIN(8, 6), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(EC_ESPI_ALERT_L,		PIN(5, 7), GPIO_INPUT | GPIO_PULL_UP)
+
+/*
+ * eDP backlight - both PCH and EC have enable pins that must be high
+ * for the backlight to turn on. Default state is high, and can be turned
+ * off during sleep states.
+ */
+GPIO(EC_EDP_BL_EN,             PIN(D, 3), GPIO_OUT_HIGH)
+
+/* I2C pins - Alternate function below configures I2C module on these pins */
+GPIO(EC_I2C0_USB_C1_MIX_SCL,   PIN(B, 5), GPIO_INPUT)		/* Reserved for USB4 retimer port 1 */
+GPIO(EC_I2C0_USB_C1_MIX_SDA,   PIN(B, 4), GPIO_INPUT)		/* Reserved for USB4 retimer port 1 */
+GPIO(EC_I2C1_USB_C0_SCL,       PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C1_USB_C0_SDA,       PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C2_USB_C1_SCL,       PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C2_USB_C1_SDA,       PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C3_USB_1_MIX_SCL,    PIN(D, 1), GPIO_INPUT)
+GPIO(EC_I2C3_USB_1_MIX_SDA,    PIN(D, 0), GPIO_INPUT)
+GPIO(EC_I2C5_BATTERY_SCL,      PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C5_BATTERY_SDA,      PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C7_EEPROM_PWR_SCL_R, PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C7_EEPROM_PWR_SDA_R, PIN(B, 2), GPIO_INPUT)
+
+/* Battery signals */
+GPIO(EC_BATT_PRES_ODL, 		PIN(E, 1), GPIO_INPUT)
+
+/* Alternate functions GPIO definitions */
+ALTERNATE(PIN_MASK(B, BIT(5) | BIT(4)), 0, MODULE_I2C, 0) /* I2C0 */
+ALTERNATE(PIN_MASK(9, BIT(0) | BIT(2) | BIT(1)), 0, MODULE_I2C, 0)                   /* I2C1 SCL / I2C2 */
+ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)                                     /* I2C1 SDA */
+ALTERNATE(PIN_MASK(D, BIT(1) | BIT(0)), 0, MODULE_I2C, 0)                            /* I2C3 */
+ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)                            /* I2C5 */
+ALTERNATE(PIN_MASK(B, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)                            /* I2C7 */
+
+/* Fan signals */
+GPIO(EN_PP5000_FAN,            PIN(6, 1), GPIO_OUT_LOW)
+ALTERNATE(PIN_MASK(B, BIT(7)), 0, MODULE_PWM, 0)	/* FAN_PWM */
+ALTERNATE(PIN_MASK(4, BIT(0)), 0, MODULE_PWM, 0)	/* FAN_SPEED_TACH */
+
+/* Keyboard pins */
+#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_00-01 */
+ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_02-07 */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_00-01 */
+GPIO(EC_KSO_02_INV, PIN(1, 7),                        GPIO_OUT_LOW)  /* KSO_02 */
+ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_03-09 */
+ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_10-13 */
+ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_14 */
+ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)                     /* EC_KB_BL_PWM */
+
+/* UART */
+ALTERNATE(PIN_MASK(6, BIT(5) | BIT(4)), 0, MODULE_UART, 0)                           /* UART from EC to Servo */
+
+/* Power Switch Logic (PSL) inputs */
+ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)                    /* GPIOD2 = EC_LID_OPEN */
+ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)  /* GPIO00 = ACOK_OD,
+                                                                       GPIO01 = H1_EC_PWR_BTN_ODL
+                                                                       GPIO02 = EC_RST_ODL */
+
+/* Temperature sensors */
+ALTERNATE(PIN_MASK(4, BIT(2) | BIT(4) | BIT(5)), 0, MODULE_ADC, 0) /* TEMP_SENSOR1,2,4 */
+ALTERNATE(PIN_MASK(F, BIT(1)), 0, MODULE_ADC, 0) /* TEMP_SENSOR3 */
+
diff --git a/board/drobit/led.c b/board/drobit/led.c
new file mode 100644
index 0000000000..bb712a8fe0
--- /dev/null
+++ b/board/drobit/led.c
@@ -0,0 +1,101 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "chipset.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
+
+__override const int led_charge_lvl_1;
+__override const int led_charge_lvl_2 = 95;
+
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_WHITE,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_BATTERY_LED,
+};
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_WHITE:
+		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_3_L, LED_ON_LVL);
+		break;
+	case EC_LED_COLOR_AMBER:
+		gpio_set_level(GPIO_LED_2_L, LED_ON_LVL);
+		gpio_set_level(GPIO_LED_3_L, LED_OFF_LVL);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_3_L, LED_OFF_LVL);
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_battery(EC_LED_COLOR_WHITE);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(EC_LED_COLOR_AMBER);
+		else
+			led_set_color_battery(LED_OFF);
+	}
+
+	return EC_SUCCESS;
+}
+
+__override enum led_states board_led_get_state(enum led_states desired_state)
+{
+	if (desired_state == STATE_BATTERY_ERROR) {
+		if (chipset_in_state(CHIPSET_STATE_ON))
+			return desired_state;
+		else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
+			return STATE_DISCHARGE_S3;
+		else
+			return STATE_DISCHARGE_S5;
+	}
+	return desired_state;
+}
diff --git a/board/drobit/vif_override.xml b/board/drobit/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/drobit/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/drobit_ecmodeentry b/board/drobit_ecmodeentry
new file mode 120000
index 0000000000..c3ab5c1706
--- /dev/null
+++ b/board/drobit_ecmodeentry
@@ -0,0 +1 @@
+drobit
\ No newline at end of file
diff --git a/board/duck b/board/duck
new file mode 120000
index 0000000000..7f4a914148
--- /dev/null
+++ b/board/duck
@@ -0,0 +1 @@
+hammer
\ No newline at end of file
diff --git a/board/eel b/board/eel
new file mode 120000
index 0000000000..7f4a914148
--- /dev/null
+++ b/board/eel
@@ -0,0 +1 @@
+hammer
\ No newline at end of file
diff --git a/board/eldrid/battery.c b/board/eldrid/battery.c
index 3c9f2b0c21..6f9e6df5af 100644
--- a/board/eldrid/battery.c
+++ b/board/eldrid/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -100,7 +100,9 @@ __override bool board_battery_is_initialized(void)
 	bool batt_initialization_state;
 	int batt_status;
 
-	batt_initialization_state = (battery_status(&batt_status) ? false :
-		!!(batt_status & STATUS_INITIALIZED));
+	batt_initialization_state =
+		(battery_status(&batt_status) ?
+			 false :
+			 !!(batt_status & STATUS_INITIALIZED));
 	return batt_initialization_state;
 }
diff --git a/board/eldrid/board.c b/board/eldrid/board.c
index c665e9c9c1..c5a0bb437e 100644
--- a/board/eldrid/board.c
+++ b/board/eldrid/board.c
@@ -1,14 +1,14 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Volteer board-specific configuration */
-#include "button.h"
-#include "common.h"
 #include "accelgyro.h"
+#include "button.h"
 #include "cbi_ec_fw_config.h"
-#include "charge_state_v2.h"
+#include "charge_state.h"
+#include "common.h"
 #include "driver/accel_bma2x2.h"
 #include "driver/accelgyro_bmi160.h"
 #include "driver/bc12/pi3usb9201.h"
@@ -16,6 +16,7 @@
 #include "driver/ppc/syv682x.h"
 #include "driver/sync.h"
 #include "driver/tcpm/ps8xxx.h"
+#include "driver/tcpm/rt1715.h"
 #include "driver/tcpm/tcpci.h"
 #include "driver/tcpm/tusb422.h"
 #include "extpower.h"
@@ -23,17 +24,19 @@
 #include "fan_chip.h"
 #include "gpio.h"
 #include "hooks.h"
+#include "isl9241.h"
+#include "keyboard_8042_sharedlib.h"
 #include "keyboard_raw.h"
-#include "lid_switch.h"
 #include "keyboard_scan.h"
+#include "lid_switch.h"
 #include "power.h"
 #include "power_button.h"
 #include "pwm.h"
 #include "pwm_chip.h"
 #include "switch.h"
 #include "system.h"
-#include "task.h"
 #include "tablet_mode.h"
+#include "task.h"
 #include "throttle_ap.h"
 #include "uart.h"
 #include "usb_mux.h"
@@ -43,12 +46,13 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#include "gpio_list.h" /* Must come after other header files. */
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 /* Keyboard scan setting */
-struct keyboard_scan_config keyscan_config = {
+__override struct keyboard_scan_config keyscan_config = {
 	/* Increase from 50 us, because KSO_02 passes through the H1. */
 	.output_settle_us = 80,
 	/* Other values should be the same as the default configuration. */
@@ -71,10 +75,58 @@ union volteer_cbi_fw_config fw_config_defaults = {
 	.usb_db = DB_USB3_ACTIVE,
 };
 
+static void board_charger_config(void)
+{
+	/*
+	 * b/166728543, we configured charger setting to throttle CPU
+	 * when the system loading is at battery current limit.
+	 */
+	int reg;
+
+	/*
+	 * Set DCProchot# to 5120mA
+	 */
+	isl9241_set_dc_prochot(CHARGER_SOLO, 5120);
+
+	/*
+	 * Set Control1 bit<3> = 1, PSYS = 1
+	 */
+	if (i2c_read16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+		       ISL9241_REG_CONTROL1, &reg) == EC_SUCCESS) {
+		reg |= ISL9241_CONTROL1_PSYS;
+		if (i2c_write16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+				ISL9241_REG_CONTROL1, reg))
+			CPRINTS("Failed to set isl9241");
+	}
+
+	/*
+	 * Set Control2 bit<10:9> = 00, PROCHOT# Debounce = 7us
+	 */
+	if (i2c_read16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+		       ISL9241_REG_CONTROL2, &reg) == EC_SUCCESS) {
+		reg &= ~ISL9241_CONTROL2_PROCHOT_DEBOUNCE_MASK;
+		if (i2c_write16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+				ISL9241_REG_CONTROL2, reg))
+			CPRINTS("Failed to set isl9241");
+	}
+
+	/*
+	 * Set Control4 bit<11> = 1, PSYS Rsense Ratio = 1:1
+	 */
+	if (i2c_read16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+		       ISL9241_REG_CONTROL4, &reg) == EC_SUCCESS) {
+		reg |= ISL9241_CONTROL4_PSYS_RSENSE_RATIO;
+		if (i2c_write16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+				ISL9241_REG_CONTROL4, reg))
+			CPRINTS("Failed to set isl9241");
+	}
+}
+
 static void board_init(void)
 {
 	pwm_enable(PWM_CH_LED4_SIDESEL, 1);
 	pwm_set_duty(PWM_CH_LED4_SIDESEL, 100);
+	board_charger_config();
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
@@ -115,23 +167,23 @@ __override bool board_is_tbt_usb4_port(int port)
 	 * TODO (b/147732807): All the USB-C ports need to support same
 	 * features. Need to fix once USB-C feature set is known for Volteer.
 	 */
-	return ((port == USBC_PORT_C1)
-		&& ((usb_db == DB_USB4_GEN2) || (usb_db == DB_USB4_GEN3)));
+	return ((port == USBC_PORT_C1) &&
+		((usb_db == DB_USB4_GEN2) || (usb_db == DB_USB4_GEN3)));
 }
 
 __override void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+				       int max_ma, int charge_mv)
 {
 	/*
-	 * Follow OEM request to limit the input current to
-	 * 90% negotiated limit when S0.
+	 * b/166728543
+	 * Set different AC_PROCHOT value when using different wattage ADT.
 	 */
-	if (chipset_in_state(CHIPSET_STATE_ON))
-		charge_ma = charge_ma * 90 / 100;
+	if (max_ma * charge_mv == PD_MAX_POWER_MW * 1000)
+		isl9241_set_ac_prochot(0, 3840);
+	else
+		isl9241_set_ac_prochot(0, 3328);
 
-	charge_set_input_current_limit(MAX(charge_ma,
-					CONFIG_CHARGER_INPUT_CURRENT),
-					charge_mv);
+	charge_set_input_current_limit(charge_ma, charge_mv);
 }
 
 /******************************************************************************/
@@ -139,7 +191,7 @@ __override void board_set_charge_limit(int port, int supplier, int charge_ma,
 
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
@@ -256,11 +308,10 @@ static const struct tcpc_config_t tcpc_config_p1_usb3 = {
 	.bus_type = EC_BUS_TYPE_I2C,
 	.i2c_info = {
 		.port = I2C_PORT_USB_C1,
-		.addr_flags = PS8751_I2C_ADDR1_FLAGS,
+		.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
 	},
 	.flags = TCPC_FLAGS_TCPCI_REV2_0 | TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V,
 	.drv = &ps8xxx_tcpm_drv,
-	.usb23 = USBC_PORT_1_USB2_NUM | (USBC_PORT_1_USB3_NUM << 4),
 };
 
 /*
@@ -268,24 +319,33 @@ static const struct tcpc_config_t tcpc_config_p1_usb3 = {
  * virtual_usb_mux_driver so the AP gets notified of mux changes and updates
  * the TCSS configuration on state changes.
  */
-static const struct usb_mux usbc1_usb3_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	.next_mux = NULL,
+static const struct usb_mux_chain usbc1_usb3_db_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
+	.next = NULL,
 };
 
-static const struct usb_mux mux_config_p1_usb3_active = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-	.next_mux = &usbc1_usb3_db_retimer,
+static const struct usb_mux_chain mux_config_p1_usb3_active = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+	.next = &usbc1_usb3_db_retimer,
 };
 
-static const struct usb_mux mux_config_p1_usb3_passive = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+static const struct usb_mux_chain mux_config_p1_usb3_passive = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
 
 /******************************************************************************/
@@ -302,8 +362,7 @@ static void ps8815_reset(void)
 	int val;
 
 	gpio_set_level(ps8xxx_rst_odl, 0);
-	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS,
-			   PS8815_PWR_H_RST_H_DELAY_MS));
+	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS));
 	gpio_set_level(ps8xxx_rst_odl, 1);
 	msleep(PS8815_FW_INIT_DELAY_MS);
 
@@ -314,16 +373,16 @@ static void ps8815_reset(void)
 
 	CPRINTS("%s: patching ps8815 registers", __func__);
 
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
+	if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) ==
+	    EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f was %02x", val);
 
-	if (i2c_write8(I2C_PORT_USB_C1,
-		       PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) == EC_SUCCESS)
+	if (i2c_write8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f,
+		       0x31) == EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f set to 0x31");
 
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
+	if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) ==
+	    EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f now %02x", val);
 }
 
@@ -335,7 +394,9 @@ void board_reset_pd_mcu(void)
 	/* Daughterboard specific reset for port 1 */
 	if (usb_db == DB_USB3_ACTIVE) {
 		ps8815_reset();
-		usb_mux_hpd_update(USBC_PORT_C1, 0, 0);
+		usb_mux_hpd_update(USBC_PORT_C1,
+				   USB_PD_MUX_HPD_LVL_DEASSERTED |
+					   USB_PD_MUX_HPD_IRQ_DEASSERTED);
 	}
 }
 
@@ -365,11 +426,29 @@ static void config_db_usb3_passive(void)
 	usb_muxes[USBC_PORT_C1] = mux_config_p1_usb3_passive;
 }
 
+static void config_port_discrete_tcpc(int port)
+{
+	/*
+	 * Support 2 Pin-to-Pin compatible parts: TUSB422 and RT1715, for
+	 * simplicity allow either and decide which we are using.
+	 * Default to TUSB422, and switch to RT1715 after BOARD_ID >=1.
+	 */
+	if (get_board_id() >= 1) {
+		CPRINTS("C%d: RT1715", port);
+		tcpc_config[port].i2c_info.addr_flags = RT1715_I2C_ADDR_FLAGS;
+		tcpc_config[port].drv = &rt1715_tcpm_drv;
+		return;
+	}
+	CPRINTS("C%d: Default to TUSB422", port);
+}
+
 static const char *db_type_prefix = "USB DB type: ";
 __override void board_cbi_init(void)
 {
 	enum ec_cfg_usb_db_type usb_db = ec_cfg_usb_db_type();
 
+	config_port_discrete_tcpc(0);
+
 	switch (usb_db) {
 	case DB_USB_ABSENT:
 		CPRINTS("%sNone", db_type_prefix);
@@ -395,6 +474,13 @@ __override void board_cbi_init(void)
 	if ((!IS_ENABLED(TEST_BUILD) && !ec_cfg_has_numeric_pad()) ||
 	    get_board_id() < 1)
 		keyboard_raw_set_cols(KEYBOARD_COLS_NO_KEYPAD);
+
+	/*
+	 * If keyboard is US2(KB_LAYOUT_1), we need translate right ctrl
+	 * to backslash(\|) key.
+	 */
+	if (ec_cfg_keyboard_layout() == KB_LAYOUT_1)
+		set_scancode_set2(4, 0, get_scancode_set2(2, 7));
 }
 
 /******************************************************************************/
@@ -424,6 +510,7 @@ void ppc_interrupt(enum gpio_signal signal)
 		break;
 	case GPIO_USB_C1_PPC_INT_ODL:
 		syv682x_interrupt(USBC_PORT_C1);
+		break;
 	default:
 		break;
 	}
@@ -453,7 +540,6 @@ struct tcpc_config_t tcpc_config[] = {
 			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
 		},
 		.drv = &tusb422_tcpm_drv,
-		.usb23 = USBC_PORT_0_USB2_NUM | (USBC_PORT_0_USB3_NUM << 4),
 	},
 	[USBC_PORT_C1] = {
 		.bus_type = EC_BUS_TYPE_I2C,
@@ -462,7 +548,6 @@ struct tcpc_config_t tcpc_config[] = {
 			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
 		},
 		.drv = &tusb422_tcpm_drv,
-		.usb23 = USBC_PORT_1_USB2_NUM | (USBC_PORT_1_USB3_NUM << 4),
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
@@ -470,16 +555,20 @@ BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
 
 /******************************************************************************/
 /* USBC mux configuration - Tiger Lake includes internal mux */
-struct usb_mux usb_muxes[] = {
+struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 	},
 	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
diff --git a/board/eldrid/board.h b/board/eldrid/board.h
index b7b0b62d95..84c04217d8 100644
--- a/board/eldrid/board.h
+++ b/board/eldrid/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,16 +11,13 @@
 /* Baseboard features */
 #include "baseboard.h"
 
-#ifdef BOARD_VOLTEER_TCPMV1
-/* Disable TCPMv2 configuration options */
-#undef CONFIG_USB_PD_TCPMV2
-
-/* Enable the required TCPMv1 options */
-#define CONFIG_USB_PD_TCPMV1
-#endif
-
 /* Optional features */
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
+#undef CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
+/*
+ * The RAM and flash size combination on the the NPCX797FC does not leave
+ * any unused flash space that can be used to store the .init_rom section.
+ */
+#undef CONFIG_CHIP_INIT_ROM_REGION
 
 #define CONFIG_VBOOT_EFS2
 
@@ -33,11 +30,18 @@
 #define CONFIG_POWER_PP5000_CONTROL
 
 /* LED defines */
-#define CONFIG_LED_POWER_LED
 #define CONFIG_LED_ONOFF_STATES
+#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
 
 /* Keyboard features */
 
+/*
+ * Disable VOL up/down when tablet mode.
+ * TODO(b/170966461): Re-enable Vivaldi keyboard once
+ * 8042 and MKBP drivers can coexist.
+ */
+#undef CONFIG_KEYBOARD_VIVALDI
+
 /* Sensors */
 /* BMA253 accelerometer in base */
 #define CONFIG_ACCEL_BMA255
@@ -48,52 +52,36 @@
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 
 /* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
-	(BIT(LID_ACCEL))
+#define CONFIG_ACCEL_FORCE_MODE_MASK (BIT(LID_ACCEL))
 
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE		BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID		LID_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
 
 /* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
-
-/*
- * USB-C port's USB2 & USB3 mapping from schematics
- * USB2 numbering on PCH - 1 to n
- * USB3 numbering on AP - 0 to n (PMC's USB3 numbering for MUX
- * configuration is - 1 to n hence add +1)
- */
-#define USBC_PORT_0_USB2_NUM	9
-#define USBC_PORT_0_USB3_NUM	1
-#define USBC_PORT_1_USB2_NUM	4
-#define USBC_PORT_1_USB3_NUM	2
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
 
 /* TODO: b/144165680 - measure and check these values on Volteer */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
 
 /*
  * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
  * cables only support up to 60W.
  */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
-
-/* Disabled PD extended message support to save flash space. */
-#undef CONFIG_USB_PD_EXTENDED_MESSAGES
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* USB Type A Features */
-#define USB_PORT_COUNT			1
+#define USB_PORT_COUNT 1
 #define CONFIG_USB_PORT_POWER_DUMB
 
 /* USBC PPC*/
-#define CONFIG_USBC_PPC_SN5S330		/* USBC port C0 */
-#define CONFIG_USBC_PPC_SYV682X		/* USBC port C1 */
+#define CONFIG_USBC_PPC_SN5S330 /* USBC port C0 */
+#define CONFIG_USBC_PPC_SYV682X /* USBC port C1 */
 
 /* BC 1.2 */
 
@@ -103,8 +91,11 @@
 #define CONFIG_CUSTOM_FAN_CONTROL
 
 /* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+/* OEM requested 10% derating */
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 10
 
 /* Retimer */
 #undef CONFIG_USBC_RETIMER_INTEL_BB
@@ -116,45 +107,42 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_DSW_PWROK		GPIO_EC_PCH_DSW_PWROK
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD		GPIO_PG_EC_RSMRST_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
-#define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE_L
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_LID_OPEN GPIO_EC_LID_OPEN
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
 
 /* I2C Bus Configuration */
 #define CONFIG_I2C
-#define I2C_PORT_ACCEL		I2C_PORT_SENSOR
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0
+#define I2C_PORT_POWER NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
 
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-#define CONFIG_I2C_MASTER
+#define I2C_PORT_BATTERY I2C_PORT_POWER
+#define I2C_PORT_CHARGER I2C_PORT_EEPROM
 
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+#define CONFIG_I2C_CONTROLLER
 
 #ifndef __ASSEMBLER__
 
@@ -181,11 +169,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 void board_reset_pd_mcu(void);
 
diff --git a/board/eldrid/build.mk b/board/eldrid/build.mk
index 8a5f8f68cd..91041efa43 100644
--- a/board/eldrid/build.mk
+++ b/board/eldrid/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -8,7 +8,8 @@
 
 CHIP:=npcx
 CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
+
+CHIP_VARIANT:=npcx7m7fc
 BASEBOARD:=volteer
 
 board-y=board.o
diff --git a/board/eldrid/ec.tasklist b/board/eldrid/ec.tasklist
index 292de51cdb..c29125d517 100644
--- a/board/eldrid/ec.tasklist
+++ b/board/eldrid/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,6 +16,7 @@
 	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
 	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
 	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
 	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
 	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
 	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
diff --git a/board/eldrid/gpio.inc b/board/eldrid/gpio.inc
index 67be3988c0..08d754b366 100644
--- a/board/eldrid/gpio.inc
+++ b/board/eldrid/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,7 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
@@ -177,3 +177,6 @@ ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)  /* GPIO00 =
                                                                        GPIO01 = H1_EC_PWR_BTN_ODL
                                                                        GPIO02 = EC_RST_ODL */
 
+/* Temperature sensors */
+ALTERNATE(PIN_MASK(4, BIT(2) | BIT(4) | BIT(5)), 0, MODULE_ADC, 0) /* TEMP_SENSOR1,2,4 */
+ALTERNATE(PIN_MASK(F, BIT(1)), 0, MODULE_ADC, 0) /* TEMP_SENSOR3 */
diff --git a/board/eldrid/led.c b/board/eldrid/led.c
index eecbf9b345..797b6d4bda 100644
--- a/board/eldrid/led.c
+++ b/board/eldrid/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,41 +19,47 @@
 /* LED_SIDESEL_4_L=1, MB BAT LED open
  * LED_SIDESEL_4_L=0, DB BAT LED open
  */
-#define LED_SISESEL_MB_PORT 0
-#define LED_SISESEL_DB_PORT 1
-
-const int led_charge_lvl_1 = 5;
-
-const int led_charge_lvl_2 = 95;
-
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {
-		{EC_LED_COLOR_WHITE, 0.4 * LED_ONE_SEC},
-		{LED_OFF,            0.4 * LED_ONE_SEC}
-	},
-	[STATE_FACTORY_TEST]         = {
-		{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-		{LED_OFF,            1 * LED_ONE_SEC}
-	},
-};
-
-const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           =  {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   =  {{EC_LED_COLOR_WHITE,  1 * LED_ONE_SEC},
-		{LED_OFF,	           1 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE,  1 * LED_ONE_SEC},
-		{LED_OFF,	           1 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {
-		{LED_OFF,             LED_INDEFINITE} },
-};
-
+#define LED_SIDESEL_MB_PORT 0
+#define LED_SIDESEL_DB_PORT 1
+
+__override const int led_charge_lvl_1 = 5;
+
+__override const int led_charge_lvl_2 = 95;
+
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_WHITE,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_WHITE,
+					    0.4 * LED_ONE_SEC },
+					  { LED_OFF, 0.4 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 1 * LED_ONE_SEC } },
+	};
+
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 1 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    1 * LED_ONE_SEC },
+						  { LED_OFF,
+						    6 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
 const enum ec_led_id supported_led_ids[] = {
 	EC_LED_ID_BATTERY_LED,
@@ -62,15 +68,31 @@ const enum ec_led_id supported_led_ids[] = {
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-void led_set_color_battery(enum ec_led_colors color)
+__override void led_set_color_battery(enum ec_led_colors color)
 {
 	int port;
-
-	port = charge_manager_get_active_charge_port();
-
-	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
-		pwm_set_duty(PWM_CH_LED4_SIDESEL,
-			(port == LED_SISESEL_MB_PORT ? 0 : 100));
+	int side_select_duty;
+
+	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
+		port = charge_manager_get_active_charge_port();
+		switch (port) {
+		case LED_SIDESEL_MB_PORT:
+			side_select_duty = 0;
+			break;
+		case LED_SIDESEL_DB_PORT:
+			side_select_duty = 100;
+			break;
+		default:
+			/*
+			 * We need to turn off led here since curr.ac won't
+			 * update immediately but led will update every 200ms.
+			 */
+			side_select_duty = 50;
+			color = LED_OFF;
+		}
+
+		pwm_set_duty(PWM_CH_LED4_SIDESEL, side_select_duty);
+	}
 
 	switch (color) {
 	case EC_LED_COLOR_AMBER:
@@ -88,7 +110,7 @@ void led_set_color_battery(enum ec_led_colors color)
 	}
 }
 
-void led_set_color_power(enum ec_led_colors color)
+__override void led_set_color_power(enum ec_led_colors color)
 {
 	if (color == EC_LED_COLOR_WHITE)
 		gpio_set_level(GPIO_POWER_LED_GATE, PWR_LED_ON_LVL);
@@ -110,6 +132,7 @@ void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
 int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 {
 	if (led_id == EC_LED_ID_BATTERY_LED) {
+		led_auto_control(led_id, 0);
 		if (brightness[EC_LED_COLOR_AMBER] != 0)
 			led_set_color_battery(EC_LED_COLOR_AMBER);
 		else if (brightness[EC_LED_COLOR_WHITE] != 0)
@@ -125,4 +148,3 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 
 	return EC_SUCCESS;
 }
-
diff --git a/board/eldrid/sensors.c b/board/eldrid/sensors.c
index 9a760897bf..9f8996d052 100644
--- a/board/eldrid/sensors.c
+++ b/board/eldrid/sensors.c
@@ -1,20 +1,21 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Volteer family-specific sensor configuration */
-#include "common.h"
 #include "accelgyro.h"
+#include "common.h"
 #include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi_common.h"
 #include "driver/accelgyro_bmi160.h"
+#include "driver/accelgyro_bmi_common.h"
 #include "driver/sync.h"
-#include "keyboard_scan.h"
+#include "gpio.h"
 #include "hooks.h"
 #include "i2c.h"
-#include "task.h"
+#include "keyboard_scan.h"
 #include "tablet_mode.h"
+#include "task.h"
 #include "util.h"
 
 /******************************************************************************/
@@ -29,17 +30,13 @@ static struct accelgyro_saved_data_t g_bma253_data;
 static struct bmi_drv_data_t g_bmi160_data;
 
 /* Rotation matrix for the lid accelerometer */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					     { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+				       { 0, FLOAT_TO_FP(1), 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
@@ -124,22 +121,3 @@ static void board_sensors_init(void)
 	gpio_enable_interrupt(GPIO_EC_IMU_INT_L);
 }
 DECLARE_HOOK(HOOK_INIT, board_sensors_init, HOOK_PRIO_DEFAULT);
-
-#ifndef TEST_BUILD
-void lid_angle_peripheral_enable(int enable)
-{
-	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
-
-	if (enable) {
-		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
-	} else {
-		/*
-		 * Ensure that the chipset is off before disabling the keyboard.
-		 * When the chipset is on, the EC keeps the keyboard enabled and
-		 * the AP decides whether to ignore input devices or not.
-		 */
-		if (!chipset_in_s0)
-			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
-	}
-}
-#endif
diff --git a/board/eldrid/thermal.c b/board/eldrid/thermal.c
index 2f4210c36c..5ce7b362fc 100644
--- a/board/eldrid/thermal.c
+++ b/board/eldrid/thermal.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,8 +15,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_THERMAL, outstr)
-#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args)
-
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
 
 /******************************************************************************/
 /* EC thermal management configuration */
@@ -27,17 +26,20 @@
  * TODO(b/170143672): Have different sensor placement. The temperature need to
  * be changed.
  */
-const static struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(35),
-	.temp_fan_max = C_TO_K(50),
-};
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 
 /*
  * Inductor limits - used for both charger and PP3300 regulator
@@ -50,23 +52,27 @@ const static struct ec_thermal_config thermal_cpu = {
  * Inductors: limit of 125c
  * PCB: limit is 80c
  */
-const static struct ec_thermal_config thermal_inductor = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(55),
-};
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_INDUCTOR         \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_inductor =
+	THERMAL_INDUCTOR;
 
 struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_CHARGER]			= thermal_inductor,
-	[TEMP_SENSOR_2_PP3300_REGULATOR]	= thermal_inductor,
-	[TEMP_SENSOR_3_DDR_SOC]			= thermal_cpu,
-	[TEMP_SENSOR_4_FAN]			= thermal_cpu,
+	[TEMP_SENSOR_1_CHARGER] = THERMAL_INDUCTOR,
+	[TEMP_SENSOR_2_PP3300_REGULATOR] = THERMAL_INDUCTOR,
+	[TEMP_SENSOR_3_DDR_SOC] = THERMAL_CPU,
+	[TEMP_SENSOR_4_FAN] = THERMAL_CPU,
 };
 BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
 
@@ -95,51 +101,39 @@ struct fan_step {
 static const struct fan_step fan_table[] = {
 	{
 		/* level 0 */
-		.on = {-1, -1, 36, -1},
-		.off = {-1, -1, 0, -1},
-		.rpm = {0},
+		.on = { -1, -1, 44, -1 },
+		.off = { -1, -1, 0, -1 },
+		.rpm = { 0 },
 	},
 	{
 		/* level 1 */
-		.on = {-1, -1, 38, -1},
-		.off = {-1, -1, 36, -1},
-		.rpm = {2000},
+		.on = { -1, -1, 46, -1 },
+		.off = { -1, -1, 44, -1 },
+		.rpm = { 3200 },
 	},
 	{
 		/* level 2 */
-		.on = {-1, -1, 41, -1},
-		.off = {-1, -1, 39, -1},
-		.rpm = {2600},
+		.on = { -1, -1, 50, -1 },
+		.off = { -1, -1, 45, -1 },
+		.rpm = { 3600 },
 	},
 	{
 		/* level 3 */
-		.on = {-1, -1, 44, -1},
-		.off = {-1, -1, 42, -1},
-		.rpm = {3000},
+		.on = { -1, -1, 54, -1 },
+		.off = { -1, -1, 49, -1 },
+		.rpm = { 4100 },
 	},
 	{
 		/* level 4 */
-		.on = {-1, -1, 46, -1},
-		.off = {-1, -1, 44, -1},
-		.rpm = {3300},
+		.on = { -1, -1, 58, -1 },
+		.off = { -1, -1, 53, -1 },
+		.rpm = { 4900 },
 	},
 	{
 		/* level 5 */
-		.on = {-1, -1, 49, -1},
-		.off = {-1, -1, 47, -1},
-		.rpm = {3600},
-	},
-	{
-		/* level 6 */
-		.on = {-1, -1, 51, -1},
-		.off = {-1, -1, 49, -1},
-		.rpm = {4200},
-	},
-	{
-		/* level 7 */
-		.on = {-1, -1, 55, -1},
-		.off = {-1, -1, 52, -1},
-		.rpm = {4700},
+		.on = { -1, -1, 60, -1 },
+		.off = { -1, -1, 57, -1 },
+		.rpm = { 5200 },
 	},
 };
 
@@ -147,6 +141,9 @@ int fan_table_to_rpm(int fan, int *temp)
 {
 	/* current fan level */
 	static int current_level;
+	/* previous fan level */
+	static int prev_current_level;
+
 	/* previous sensor temperature */
 	static int prev_temp[TEMP_SENSOR_COUNT];
 	const int num_fan_levels = ARRAY_SIZE(fan_table);
@@ -161,22 +158,20 @@ int fan_table_to_rpm(int fan, int *temp)
 	 *  3. invariant path. (return the current RPM)
 	 */
 
-	CPRINTS("temp: %d, prev_temp: %d", temp[TEMP_SENSOR_3_DDR_SOC],
-		prev_temp[TEMP_SENSOR_3_DDR_SOC]);
 	if (temp[TEMP_SENSOR_3_DDR_SOC] < prev_temp[TEMP_SENSOR_3_DDR_SOC]) {
 		for (i = current_level; i > 0; i--) {
 			if (temp[TEMP_SENSOR_3_DDR_SOC] <
-				fan_table[i].off[TEMP_SENSOR_3_DDR_SOC])
+			    fan_table[i].off[TEMP_SENSOR_3_DDR_SOC])
 				current_level = i - 1;
 			else
 				break;
 		}
 	} else if (temp[TEMP_SENSOR_3_DDR_SOC] >
-		prev_temp[TEMP_SENSOR_3_DDR_SOC]) {
+		   prev_temp[TEMP_SENSOR_3_DDR_SOC]) {
 		for (i = current_level; i < num_fan_levels; i++) {
 			if (temp[TEMP_SENSOR_3_DDR_SOC] >
-				fan_table[i].on[TEMP_SENSOR_3_DDR_SOC])
-				current_level = i + 1;
+			    fan_table[i].on[TEMP_SENSOR_3_DDR_SOC])
+				current_level = i;
 			else
 				break;
 		}
@@ -185,10 +180,16 @@ int fan_table_to_rpm(int fan, int *temp)
 	if (current_level < 0)
 		current_level = 0;
 
+	if (current_level != prev_current_level) {
+		CPRINTS("temp: %d, prev_temp: %d", temp[TEMP_SENSOR_3_DDR_SOC],
+			prev_temp[TEMP_SENSOR_3_DDR_SOC]);
+		CPRINTS("current_level: %d", current_level);
+	}
+
 	for (i = 0; i < TEMP_SENSOR_COUNT; ++i)
 		prev_temp[i] = temp[i];
 
-	CPRINTS("current_level: %d", current_level);
+	prev_current_level = current_level;
 
 	switch (fan) {
 	case FAN_CH_0:
@@ -205,8 +206,7 @@ void board_override_fan_control(int fan, int *temp)
 {
 	if (chipset_in_state(CHIPSET_STATE_ON)) {
 		fan_set_rpm_mode(FAN_CH(fan), 1);
-		fan_set_rpm_target(FAN_CH(fan),
-			fan_table_to_rpm(fan, temp));
+		fan_set_rpm_target(FAN_CH(fan), fan_table_to_rpm(fan, temp));
 	} else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
 		/* Stop fan when enter S0ix */
 		fan_set_rpm_mode(FAN_CH(fan), 1);
diff --git a/board/eldrid/vif_override.xml b/board/eldrid/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/eldrid/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/elemi/battery.c b/board/elemi/battery.c
index 9b356a8efd..f24c4c6847 100644
--- a/board/elemi/battery.c
+++ b/board/elemi/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,7 +10,7 @@
 #include "util.h"
 
 /*
- * Battery info for all Volteer battery types. Note that the fields
+ * Battery info for all Elemi battery types. Note that the fields
  * start_charging_min/max and charging_min/max are not used for the charger.
  * The effective temperature limits are given by discharging_min/max_c.
  *
@@ -32,37 +32,63 @@
  * address, mask, and disconnect value need to be provided.
  */
 const struct board_batt_params board_battery_info[] = {
-	/* LGC\011 L17L3PB0 Battery Information */
-	/*
-	 * Battery info provided by ODM on b/143477210, comment #11
-	 */
-	[BATTERY_LGC011] = {
+	/* SMP 996QA193H Battery Information */
+	[BATTERY_SIMPLO_HIGHPOWER] = {
 		.fuel_gauge = {
-			.manuf_name = "LGC",
+			.manuf_name = "333-1D-11-A",
 			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x10, 0x10 },
+				.reg_addr = 0x0,
+				.reg_data = { 0x0010, 0x0010 },
 			},
 			.fet = {
+				.mfgacc_support = 1,
 				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			}
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 13200,		/* mV */
+			.voltage_normal = 11550,	/* mV */
+			.voltage_min = 9000,		/* mV */
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -20,
+			.discharging_max_c = 60,
+		},
+	},
+	/* Cosmx CA407792G Battery Information */
+	[BATTERY_COSMX] = {
+		.fuel_gauge = {
+			.manuf_name = "333-AC-11-A",
+			.ship_mode = {
+				.reg_addr = 0x0,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+			},
 		},
 		.batt_info = {
-			.voltage_max		= TARGET_WITH_MARGIN(13200, 5),
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 75,
+			.voltage_max = 13200,		/* mV */
+			.voltage_normal = 11550,	/* mV */
+			.voltage_min = 9000,		/* mV */
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
 		},
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
 
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_LGC011;
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SIMPLO_HIGHPOWER;
diff --git a/board/elemi/board.c b/board/elemi/board.c
index 1993b241fb..944e585ea4 100644
--- a/board/elemi/board.c
+++ b/board/elemi/board.c
@@ -1,21 +1,16 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-/* Volteer board-specific configuration */
-#include "bb_retimer.h"
-#include "button.h"
-#include "common.h"
+/* Elemi board-specific configuration */
 #include "accelgyro.h"
+#include "button.h"
 #include "cbi_ec_fw_config.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi260.h"
-#include "driver/als_tcs3400.h"
+#include "common.h"
 #include "driver/bc12/pi3usb9201.h"
 #include "driver/ppc/sn5s330.h"
 #include "driver/ppc/syv682x.h"
-#include "driver/retimer/bb_retimer.h"
 #include "driver/sync.h"
 #include "driver/tcpm/ps8xxx.h"
 #include "driver/tcpm/rt1715.h"
@@ -36,7 +31,6 @@
 #include "switch.h"
 #include "system.h"
 #include "task.h"
-#include "tablet_mode.h"
 #include "throttle_ap.h"
 #include "uart.h"
 #include "usb_mux.h"
@@ -46,12 +40,13 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#include "gpio_list.h" /* Must come after other header files. */
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 /* Keyboard scan setting */
-struct keyboard_scan_config keyscan_config = {
+__override struct keyboard_scan_config keyscan_config = {
 	/* Increase from 50 us, because KSO_02 passes through the H1. */
 	.output_settle_us = 80,
 	/* Other values should be the same as the default configuration. */
@@ -68,82 +63,25 @@ struct keyboard_scan_config keyscan_config = {
 
 /******************************************************************************/
 /*
- * FW_CONFIG defaults for Volteer if the CBI data is not initialized.
+ * FW_CONFIG defaults for Elemi if the CBI data is not initialized.
  */
 union volteer_cbi_fw_config fw_config_defaults = {
-	.usb_db = DB_USB4_GEN2,
+	.usb_db = DB_USB3_ACTIVE,
 };
 
-static void board_init(void)
-{
-	/* Illuminate motherboard and daughter board LEDs equally to start. */
-	pwm_enable(PWM_CH_LED4_SIDESEL, 1);
-	pwm_set_duty(PWM_CH_LED4_SIDESEL, 50);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-__override enum tbt_compat_cable_speed board_get_max_tbt_speed(int port)
-{
-	enum ec_cfg_usb_db_type usb_db = ec_cfg_usb_db_type();
-
-	if (port == USBC_PORT_C1) {
-		if (usb_db == DB_USB4_GEN2) {
-			/*
-			 * Older boards violate 205mm trace length prior
-			 * to connection to the re-timer and only support up
-			 * to GEN2 speeds.
-			 */
-			return TBT_SS_U32_GEN1_GEN2;
-		} else if (usb_db == DB_USB4_GEN3) {
-			return TBT_SS_TBT_GEN3;
-		}
-	}
-
-	/*
-	 * Thunderbolt-compatible mode not supported
-	 *
-	 * TODO (b/147726366): All the USB-C ports need to support same speed.
-	 * Need to fix once USB-C feature set is known for Volteer.
-	 */
-	return TBT_SS_RES_0;
-}
-
-__override bool board_is_tbt_usb4_port(int port)
-{
-	enum ec_cfg_usb_db_type usb_db = ec_cfg_usb_db_type();
-
-	/*
-	 * Volteer reference design only supports TBT & USB4 on port 1
-	 * if the USB4 DB is present.
-	 *
-	 * TODO (b/147732807): All the USB-C ports need to support same
-	 * features. Need to fix once USB-C feature set is known for Volteer.
-	 */
-	return ((port == USBC_PORT_C1)
-		&& ((usb_db == DB_USB4_GEN2) || (usb_db == DB_USB4_GEN3)));
-}
-
-/******************************************************************************/
 /* Physical fans. These are logically separate from pwm_channels. */
 
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
 
-/*
- * Fan specs from datasheet:
- * Max speed 5900 rpm (+/- 7%), minimum duty cycle 30%.
- * Minimum speed not specified by RPM. Set minimum RPM to max speed (with
- * margin) x 30%.
- *    5900 x 1.07 x 0.30 = 1894, round up to 1900
- */
 const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 1900,
-	.rpm_start = 1900,
-	.rpm_max = 5900,
+	.rpm_min = 2500,
+	.rpm_start = 2500,
+	.rpm_max = 6500,
 };
 
 const struct fan_t fans[FAN_CH_COUNT] = {
@@ -161,47 +99,64 @@ const struct fan_t fans[FAN_CH_COUNT] = {
  * 130 C.  However, sensor is located next to DDR, so we need to use the lower
  * DDR temperature limit (85 C)
  */
-const static struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(35),
-	.temp_fan_max = C_TO_K(50),
-};
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(68), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(70), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(58), \
+		}, \
+		.temp_fan_off = C_TO_K(40), \
+		.temp_fan_max = C_TO_K(60), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 
 /*
- * Inductor limits - used for both charger and PP3300 regulator
- *
- * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
- *
- * Charger max recommended temperature 100C, max absolute temperature 125C
- * PP3300 regulator: operating range -40 C to 145 C
- *
- * Inductors: limit of 125c
- * PCB: limit is 80c
+ * TODO(b/202062363): Remove when clang is fixed.
  */
-const static struct ec_thermal_config thermal_inductor = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(55),
-};
+#define THERMAL_CHARGER          \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(78), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(68), \
+		}, \
+		.temp_fan_off = C_TO_K(40), \
+		.temp_fan_max = C_TO_K(70), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_charger =
+	THERMAL_CHARGER;
 
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_REGULATOR        \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(68), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(70), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(58), \
+		}, \
+		.temp_fan_off = C_TO_K(40), \
+		.temp_fan_max = C_TO_K(55), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_regulator =
+	THERMAL_REGULATOR;
 
 struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_CHARGER]			= thermal_inductor,
-	[TEMP_SENSOR_2_PP3300_REGULATOR]	= thermal_inductor,
-	[TEMP_SENSOR_3_DDR_SOC]			= thermal_cpu,
-	[TEMP_SENSOR_4_FAN]			= thermal_cpu,
+	[TEMP_SENSOR_1_CHARGER] = THERMAL_CHARGER,
+	[TEMP_SENSOR_2_PP3300_REGULATOR] = THERMAL_REGULATOR,
+	[TEMP_SENSOR_3_DDR_SOC] = THERMAL_CPU,
+	[TEMP_SENSOR_4_FAN] = THERMAL_CPU,
 };
 BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
 
@@ -219,13 +174,6 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 /******************************************************************************/
 /* I2C port map configuration */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C0_SENSOR_SCL,
-		.sda = GPIO_EC_I2C0_SENSOR_SDA,
-	},
 	{
 		.name = "usb_c0",
 		.port = I2C_PORT_USB_C0,
@@ -267,31 +215,6 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 /******************************************************************************/
 /* PWM configuration */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED1_BLUE] = {
-		.channel = 2,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 4800,
-	},
-	[PWM_CH_LED2_GREEN] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 4800,
-	},
-	[PWM_CH_LED3_RED] = {
-		.channel = 1,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 4800,
-	},
-	[PWM_CH_LED4_SIDESEL] = {
-		.channel = 7,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		/*
-		 * If using the side select to run both LEDs at the same time,
-		 * the frequency should be 1/2 of the color channel PWM
-		 * frequency to drive each LED equally.
-		 */
-		.freq = 2400,
-	},
 	[PWM_CH_FAN] = {
 		.channel = 5,
 		.flags = PWM_CONFIG_OPEN_DRAIN,
@@ -311,44 +234,39 @@ const struct pwm_t pwm_channels[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
-/******************************************************************************/
-/* Volteer specific USB daughter-board configuration */
+static void kb_backlight_enable(void)
+{
+	gpio_set_level(GPIO_EC_KB_BL_EN, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, kb_backlight_enable, HOOK_PRIO_DEFAULT);
 
-/* USBC TCPC configuration for USB3 daughter board */
-static const struct tcpc_config_t tcpc_config_p1_usb3 = {
-	.bus_type = EC_BUS_TYPE_I2C,
-	.i2c_info = {
-		.port = I2C_PORT_USB_C1,
-		.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-	},
-	.flags = TCPC_FLAGS_TCPCI_REV2_0 | TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V,
-	.drv = &ps8xxx_tcpm_drv,
-	.usb23 = USBC_PORT_1_USB2_NUM | (USBC_PORT_1_USB3_NUM << 4),
-};
+static void kb_backlight_disable(void)
+{
+	gpio_set_level(GPIO_EC_KB_BL_EN, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, kb_backlight_disable, HOOK_PRIO_DEFAULT);
+
+__override void board_ps8xxx_tcpc_init(int port)
+{
+	/* b/189587527: Set Displayport EQ loss up to 10dB */
+	tcpc_addr_write(
+		port, PS8XXX_I2C_ADDR1_P1_FLAGS, PS8815_REG_DP_EQ_SETTING,
+		PS8815_DPEQ_LOSS_UP_10DB << PS8815_REG_DP_EQ_COMP_SHIFT);
+}
 
 /*
  * USB3 DB mux configuration - the top level mux still needs to be set to the
  * virtual_usb_mux_driver so the AP gets notified of mux changes and updates
  * the TCSS configuration on state changes.
  */
-static const struct usb_mux usbc1_usb3_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	.next_mux = NULL,
-};
-
-static const struct usb_mux mux_config_p1_usb3_active = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-	.next_mux = &usbc1_usb3_db_retimer,
-};
-
-static const struct usb_mux mux_config_p1_usb3_passive = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+static const struct usb_mux_chain usbc1_usb3_db_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
+	.next = NULL,
 };
 
 /******************************************************************************/
@@ -358,16 +276,13 @@ const int usb_port_enable[USB_PORT_COUNT] = {
 	GPIO_EN_PP5000_USBA,
 };
 
-static enum gpio_signal ps8xxx_rst_odl = GPIO_USB_C1_RT_RST_ODL;
-
 static void ps8815_reset(void)
 {
 	int val;
 
-	gpio_set_level(ps8xxx_rst_odl, 0);
-	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS,
-			   PS8815_PWR_H_RST_H_DELAY_MS));
-	gpio_set_level(ps8xxx_rst_odl, 1);
+	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 0);
+	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS));
+	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 1);
 	msleep(PS8815_FW_INIT_DELAY_MS);
 
 	/*
@@ -377,123 +292,30 @@ static void ps8815_reset(void)
 
 	CPRINTS("%s: patching ps8815 registers", __func__);
 
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
+	if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) ==
+	    EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f was %02x", val);
 
-	if (i2c_write8(I2C_PORT_USB_C1,
-		       PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) == EC_SUCCESS)
+	if (i2c_write8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f,
+		       0x31) == EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f set to 0x31");
 
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
+	if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) ==
+	    EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f now %02x", val);
 }
 
 void board_reset_pd_mcu(void)
 {
-	enum ec_cfg_usb_db_type usb_db = ec_cfg_usb_db_type();
-
 	/* No reset available for TCPC on port 0 */
 	/* Daughterboard specific reset for port 1 */
-	if (usb_db == DB_USB3_ACTIVE) {
-		ps8815_reset();
-		usb_mux_hpd_update(USBC_PORT_C1, 0, 0);
-	}
-}
-
-/*
- * Set up support for the USB3 daughterboard:
- *   Parade PS8815 TCPC (integrated retimer)
- *   Diodes PI3USB9201 BC 1.2 chip (same as USB4 board)
- *   Silergy SYV682A PPC (same as USB4 board)
- *   Virtual mux with stacked retimer
- */
-static void config_db_usb3_active(void)
-{
-	tcpc_config[USBC_PORT_C1] = tcpc_config_p1_usb3;
-	usb_muxes[USBC_PORT_C1] = mux_config_p1_usb3_active;
-}
-
-/*
- * Set up support for the passive USB3 daughterboard:
- *   TUSB422 TCPC (already the default)
- *   PI3USB9201 BC 1.2 chip (already the default)
- *   Silergy SYV682A PPC (already the default)
- *   Virtual mux without stacked retimer
- */
-
-static void config_db_usb3_passive(void)
-{
-	usb_muxes[USBC_PORT_C1] = mux_config_p1_usb3_passive;
-}
-
-static void config_port_discrete_tcpc(int port)
-{
-	/*
-	 * Support 2 Pin-to-Pin compatible parts: TUSB422 and RT1715, for
-	 * simplicity allow either and decide at runtime which we are using.
-	 * Default to TUSB422, and switch to RT1715 if it is on the I2C bus and
-	 * the VID matches.
-	 */
-
-	int regval;
-
-	if (i2c_read16(port ? I2C_PORT_USB_C1 : I2C_PORT_USB_C0,
-		       RT1715_I2C_ADDR_FLAGS, TCPC_REG_VENDOR_ID,
-		       &regval) == EC_SUCCESS) {
-		if (regval == RT1715_VENDOR_ID) {
-			CPRINTS("C%d: RT1715 detected", port);
-			tcpc_config[port].i2c_info.addr_flags =
-				RT1715_I2C_ADDR_FLAGS;
-			tcpc_config[port].drv = &rt1715_tcpm_drv;
-			return;
-		}
-	}
-	CPRINTS("C%d: Default to TUSB422", port);
+	ps8815_reset();
+	usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
 
-static const char *db_type_prefix = "USB DB type: ";
 __override void board_cbi_init(void)
 {
-	enum ec_cfg_usb_db_type usb_db = ec_cfg_usb_db_type();
-
-	/* Reconfigure Volteer GPIOs based on the board ID */
-	if (get_board_id() == 0) {
-		CPRINTS("Configuring GPIOs for board ID 0");
-		CPRINTS("VOLUME_UP button disabled");
-
-		/* Reassign USB_C1_RT_RST_ODL */
-		bb_controls[USBC_PORT_C1].retimer_rst_gpio =
-			GPIO_USB_C1_RT_RST_ODL_BOARDID_0;
-		ps8xxx_rst_odl = GPIO_USB_C1_RT_RST_ODL_BOARDID_0;
-	}
-	config_port_discrete_tcpc(0);
-	switch (usb_db) {
-	case DB_USB_ABSENT:
-		CPRINTS("%sNone", db_type_prefix);
-		break;
-	case DB_USB4_GEN2:
-		config_port_discrete_tcpc(1);
-		CPRINTS("%sUSB4 Gen1/2", db_type_prefix);
-		break;
-	case DB_USB4_GEN3:
-		config_port_discrete_tcpc(1);
-		CPRINTS("%sUSB4 Gen3", db_type_prefix);
-		break;
-	case DB_USB3_ACTIVE:
-		config_db_usb3_active();
-		CPRINTS("%sUSB3 Active", db_type_prefix);
-		break;
-	case DB_USB3_PASSIVE:
-		config_db_usb3_passive();
-		config_port_discrete_tcpc(1);
-		CPRINTS("%sUSB3 Passive", db_type_prefix);
-		break;
-	default:
-		CPRINTS("%sID %d not supported", db_type_prefix, usb_db);
-	}
-
 	if ((!IS_ENABLED(TEST_BUILD) && !ec_cfg_has_numeric_pad()) ||
 	    get_board_id() <= 2)
 		keyboard_raw_set_cols(KEYBOARD_COLS_NO_KEYPAD);
@@ -526,6 +348,7 @@ void ppc_interrupt(enum gpio_signal signal)
 		break;
 	case GPIO_USB_C1_PPC_INT_ODL:
 		syv682x_interrupt(USBC_PORT_C1);
+		break;
 	default:
 		break;
 	}
@@ -547,24 +370,24 @@ BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
 
 /******************************************************************************/
 /* USBC TCPC configuration */
-struct tcpc_config_t tcpc_config[] = {
+const struct tcpc_config_t tcpc_config[] = {
 	[USBC_PORT_C0] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = I2C_PORT_USB_C0,
-			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
+			.addr_flags = RT1715_I2C_ADDR_FLAGS,
 		},
-		.drv = &tusb422_tcpm_drv,
-		.usb23 = USBC_PORT_0_USB2_NUM | (USBC_PORT_0_USB3_NUM << 4),
+		.drv = &rt1715_tcpm_drv,
 	},
 	[USBC_PORT_C1] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = I2C_PORT_USB_C1,
-			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
 		},
-		.drv = &tusb422_tcpm_drv,
-		.usb23 = USBC_PORT_1_USB2_NUM | (USBC_PORT_1_USB3_NUM << 4),
+		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V,
+		.drv = &ps8xxx_tcpm_drv,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
@@ -572,38 +395,25 @@ BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
 
 /******************************************************************************/
 /* USBC mux configuration - Tiger Lake includes internal mux */
-struct usb_mux usbc1_usb4_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &bb_usb_retimer,
-	.i2c_port = I2C_PORT_USB_1_MIX,
-	.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
-};
-struct usb_mux usb_muxes[] = {
+const struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 	},
 	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc1_usb4_db_retimer,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc1_usb3_db_retimer,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
 
-struct bb_usb_control bb_controls[] = {
-	[USBC_PORT_C0] = {
-		/* USB-C port 0 doesn't have a retimer */
-	},
-	[USBC_PORT_C1] = {
-		.usb_ls_en_gpio = GPIO_USB_C1_LS_EN,
-		.retimer_rst_gpio = GPIO_USB_C1_RT_RST_ODL,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(bb_controls) == USBC_PORT_COUNT);
-
 static void board_tcpc_init(void)
 {
 	/* Don't reset TCPCs after initial reset */
@@ -648,3 +458,21 @@ int ppc_get_alert_status(int port)
 	else
 		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
 }
+
+#ifdef CONFIG_KEYBOARD_FACTORY_TEST
+/*
+ * Map keyboard connector pins to EC GPIO pins for factory test.
+ * Pins mapped to {-1, -1} are skipped.
+ * The connector has 24 pins total, and there is no pin 0.
+ */
+const int keyboard_factory_scan_pins[][2] = {
+	{ -1, -1 }, { 0, 5 }, { 1, 1 },	  { 1, 0 },   { 0, 6 },
+	{ 0, 7 },   { 1, 4 }, { 1, 3 },	  { 1, 6 },   { 1, 7 },
+	{ 3, 1 },   { 2, 0 }, { 1, 5 },	  { 2, 6 },   { 2, 7 },
+	{ 2, 1 },   { 2, 4 }, { 2, 5 },	  { 1, 2 },   { 2, 3 },
+	{ 2, 2 },   { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 },
+};
+
+const int keyboard_factory_scan_pins_used =
+	ARRAY_SIZE(keyboard_factory_scan_pins);
+#endif
diff --git a/board/elemi/board.h b/board/elemi/board.h
index 0efc83180c..aa6756d0ce 100644
--- a/board/elemi/board.h
+++ b/board/elemi/board.h
@@ -1,9 +1,9 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-/* Volteer board configuration */
+/* Elemi board configuration */
 
 #ifndef __CROS_EC_BOARD_H
 #define __CROS_EC_BOARD_H
@@ -11,24 +11,13 @@
 /* Baseboard features */
 #include "baseboard.h"
 
-#ifdef BOARD_VOLTEER_TCPMV1
-/* Disable TCPMv2 configuration options */
-#undef CONFIG_USB_PD_TCPMV2
-
-/* Enable the required TCPMv1 options */
-#define CONFIG_USB_PD_TCPMV1
-
 /*
- * Because the TPCMv1 stack has considerably smaller flash footprint, disable
- * the CONFIG_CHIP_INIT_ROM_REGION for testing of the init_rom API and the
- * BMI260 driver.
+ * The RAM and flash size combination on the NPCX797FC dose not leave
+ * any unused flash space that can be used to store the .init_rom section.
  */
 #undef CONFIG_CHIP_INIT_ROM_REGION
-#endif
 
 /* Optional features */
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
-
 #define CONFIG_VBOOT_EFS2
 
 #define CONFIG_POWER_BUTTON
@@ -39,90 +28,61 @@
 /* Chipset features */
 #define CONFIG_POWER_PP5000_CONTROL
 
-/* LED defines */
-#define CONFIG_LED_PWM
-/* Although there are 2 LEDs, they are both controlled by the same lines. */
-#define CONFIG_LED_PWM_COUNT 1
-
 /* Keyboard features */
 
 /* Sensors */
-/* BMA253 accelerometer in base */
-#define CONFIG_ACCEL_BMA255
-
-/* BMI260 accel/gyro in base */
-#define CONFIG_ACCELGYRO_BMI260
-#define CONFIG_ACCELGYRO_BMI260_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-/* TCS3400 ALS */
-#define CONFIG_ALS
-#define ALS_COUNT		1
-#define CONFIG_ALS_TCS3400
-#define CONFIG_ALS_TCS3400_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS)
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
-	(BIT(LID_ACCEL) | BIT(CLEAR_ALS))
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE		BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID		LID_ACCEL
+#undef CONFIG_TABLET_MODE
+#undef CONFIG_GMR_TABLET_MODE
+#undef CONFIG_ACCEL_FIFO
+#undef CONFIG_ACCEL_FIFO_SIZE
 
 /* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
-
-/*
- * USB-C port's USB2 & USB3 mapping from schematics
- * USB2 numbering on PCH - 1 to n
- * USB3 numbering on AP - 0 to n (PMC's USB3 numbering for MUX
- * configuration is - 1 to n hence add +1)
- */
-#define USBC_PORT_0_USB2_NUM	9
-#define USBC_PORT_0_USB3_NUM	1
-#define USBC_PORT_1_USB2_NUM	4
-#define USBC_PORT_1_USB3_NUM	2
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
 
 /* TODO: b/144165680 - measure and check these values on Volteer */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+/* Experimentally determined. See b/186079130. */
+#undef CONFIG_USBC_VCONN_SWAP_DELAY_US
+#define CONFIG_USBC_VCONN_SWAP_DELAY_US 10000 /* us */
 
 /*
  * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
  * cables only support up to 60W.
  */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
-
-/* Enabling Thunderbolt-compatible mode */
-#define CONFIG_USB_PD_TBT_COMPAT_MODE
-
-/* Enabling USB4 mode */
-#define CONFIG_USB_PD_USB4
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x40
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* USB Type A Features */
-#define USB_PORT_COUNT			1
+#define USB_PORT_COUNT 1
 #define CONFIG_USB_PORT_POWER_DUMB
 
 /* USBC PPC*/
-#define CONFIG_USBC_PPC_SN5S330		/* USBC port C0 */
-#define CONFIG_USBC_PPC_SYV682X		/* USBC port C1 */
+#define CONFIG_USBC_PPC_SN5S330 /* USBC port C0 */
+#define CONFIG_USBC_PPC_SYV682X /* USBC port C1 */
+#undef CONFIG_USB_PD_TCPC_RUNTIME_CONFIG
+#undef CONFIG_USB_PD_TCPM_TUSB422
+#undef CONFIG_USB_MUX_RUNTIME_CONFIG
 
 /* BC 1.2 */
 
 /* Volume Button feature */
+#undef CONFIG_VOLUME_BUTTONS
 
 /* Fan features */
 
 /* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+
+/* Retimer */
+#undef CONFIG_USBC_RETIMER_INTEL_BB
+#undef CONFIG_USBC_RETIMER_INTEL_BB_RUNTIME_CONFIG
+
+/* Keyboard feature */
+#define CONFIG_KEYBOARD_FACTORY_TEST
 
 /*
  * Macros for GPIO signals used in common code that don't match the
@@ -130,46 +90,39 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_DSW_PWROK		GPIO_EC_PCH_DSW_PWROK
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD		GPIO_PG_EC_RSMRST_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
-#define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE_L
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_LID_OPEN GPIO_EC_LID_OPEN
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL
 
 /* I2C Bus Configuration */
 #define CONFIG_I2C
-#define I2C_PORT_ACCEL		I2C_PORT_SENSOR
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_1_MIX	NPCX_I2C_PORT3_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT3_0
+#define I2C_PORT_POWER NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
 
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-#define CONFIG_I2C_MASTER
+#define I2C_PORT_BATTERY I2C_PORT_POWER
+#define I2C_PORT_CHARGER I2C_PORT_EEPROM
 
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+#define CONFIG_I2C_CONTROLLER
 
 #ifndef __ASSEMBLER__
 
@@ -177,34 +130,14 @@
 #include "registers.h"
 
 enum battery_type {
-	BATTERY_LGC011,
+	BATTERY_SIMPLO_HIGHPOWER,
+	BATTERY_COSMX,
 	BATTERY_TYPE_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_LED1_BLUE = 0,
-	PWM_CH_LED2_GREEN,
-	PWM_CH_LED3_RED,
-	PWM_CH_LED4_SIDESEL,
-	PWM_CH_FAN,
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	CLEAR_ALS,
-	RGB_ALS,
-	SENSOR_COUNT,
-};
+enum pwm_channel { PWM_CH_FAN, PWM_CH_KBLIGHT, PWM_CH_COUNT };
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 void board_reset_pd_mcu(void);
 
diff --git a/board/elemi/build.mk b/board/elemi/build.mk
index b78172d3cf..d590255d2a 100644
--- a/board/elemi/build.mk
+++ b/board/elemi/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -8,10 +8,9 @@
 
 CHIP:=npcx
 CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
+CHIP_VARIANT:=npcx7m7fc
 BASEBOARD:=volteer
 
 board-y=board.o
 board-y+=battery.o
 board-y+=led.o
-board-y+=sensors.o
diff --git a/board/elemi/ec.tasklist b/board/elemi/ec.tasklist
index 292de51cdb..a1b5d30d93 100644
--- a/board/elemi/ec.tasklist
+++ b/board/elemi/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,9 +13,9 @@
 	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
 	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
 	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
 	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
 	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
 	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
 	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
 	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
diff --git a/board/elemi/gpio.inc b/board/elemi/gpio.inc
index d0055671ca..3dbf9b35c7 100644
--- a/board/elemi/gpio.inc
+++ b/board/elemi/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,7 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
@@ -24,16 +24,6 @@ GPIO_INT(PG_EC_RSMRST_ODL,     PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
 GPIO_INT(PG_EC_DSW_PWROK,      PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
 GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
 
-/* Sensor Interrupts */
-GPIO_INT(EC_IMU_INT_L,         PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, bmi260_interrupt)
-GPIO_INT(EC_ALS_RGB_INT_L,     PIN(D, 4), GPIO_INT_FALLING, tcs3400_interrupt)
-GPIO_INT(TABLET_MODE_L,        PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-/*
- * Lid g-sensor interrupt unused on Volteer, configure as regular input for
- * power saving.
- */
-GPIO(EC_ACCEL_INT,		PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
-
 /* USB-C interrupts */
 GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(E, 0), GPIO_INT_BOTH, tcpc_alert_event)
 GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(A, 2), GPIO_INT_BOTH, tcpc_alert_event)
@@ -46,10 +36,6 @@ GPIO_INT(USB_C1_MIX_INT_ODL,	PIN(0, 3), GPIO_INT_BOTH, bc12_interrupt)
 
 /* HDMI interrupts */
 
-/* Volume button interrupts */
-GPIO_INT(EC_VOLDN_BTN_ODL,		PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL,		PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-
 /* Power Sequencing Signals */
 GPIO(EN_PP3300_A,              PIN(A, 3), GPIO_OUT_LOW)
 GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
@@ -84,15 +70,7 @@ GPIO(EC_PCH_INT_ODL,           PIN(B, 0), GPIO_ODR_HIGH)
 /* USB and USBC Signals */
 GPIO(EN_PP5000_USBA,		PIN(C, 6), GPIO_OUT_LOW)	/* Enable USB-A charging - all ports */
 GPIO(USB_A_LOW_PWR_OD,		PIN(6, 6), GPIO_ODR_LOW)	/* Don't limit USB-A charging by default - all ports */
-
-/*
- * USB_C1 moved from GPIO32 to GPIO83 on boards with board ID >=1.
- * GPIO83/EN_PP1800_A is DNS on board ID 0 and GPIO32 is N/C on board ID >=1
- * so it's safe to define GPIOs compatible with both designs.
- * TODO (b/149858568): remove board ID=0 support.
- */
-GPIO(USB_C1_RT_RST_ODL_BOARDID_0,	PIN(3, 2), GPIO_ODR_LOW) /* USB_C1 Reset on boards without board ID */
-GPIO(USB_C1_RT_RST_ODL,			PIN(8, 3), GPIO_ODR_LOW) /* USB_C1 Reset on boards board ID >=1 */
+GPIO(USB_C1_RT_RST_ODL,		PIN(8, 3), GPIO_ODR_LOW) /* USB_C1 Reset */
 GPIO(USB_C0_OC_ODL,			PIN(B, 1), GPIO_ODR_HIGH)
 GPIO(USB_C1_OC_ODL,			PIN(5, 0), GPIO_ODR_HIGH)
 /* There is currently no need to service this interrupt. */
@@ -103,6 +81,7 @@ UNIMPLEMENTED(USB_C1_LS_EN)
 
 /* Misc Signals */
 GPIO(EC_H1_PACKET_MODE,		PIN(7, 5), GPIO_OUT_LOW)	/* H1 Packet Mode */
+GPIO(EC_KB_BL_EN,		PIN(8, 6), GPIO_OUT_LOW)	/* Keyboard backlight enable */
 /*
  * Despite their names, M2_SSD_PLN and M2_SSD_PLA are active-low, and M2_SSD_PLN
  * is open-drain.
@@ -112,12 +91,24 @@ GPIO(M2_SSD_PLN,		PIN(A, 0), GPIO_ODR_HIGH)	/* SSD power-loss notification */
 GPIO(M2_SSD_PLA,		PIN(7, 0), GPIO_INPUT)		/* SSD power-loss acknowledgment */
 GPIO(CCD_MODE_ODL,		PIN(E, 5), GPIO_INPUT)		/* Case Closed Debug Mode */
 GPIO(EC_SLP_S0IX,		PIN(7, 2), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(C0_CHARGE_LED_AMBER_L,	PIN(C, 3), GPIO_OUT_HIGH)	/* Amber C0 port */
+GPIO(C0_CHARGE_LED_WHITE_L,	PIN(C, 4), GPIO_OUT_HIGH)	/* White C0 port */
+GPIO(C1_CHARGE_LED_AMBER_L,	PIN(6, 0), GPIO_OUT_HIGH)	/* Amber C1 port */
+GPIO(C1_CHARGE_LED_WHITE_L,	PIN(C, 2), GPIO_OUT_HIGH)	/* White C1 port */
 
 /* Unused signals */
 GPIO(UNUSED_GPIO41,		PIN(4, 1), GPIO_INPUT | GPIO_PULL_UP)
 GPIO(UNUSED_GPIOF2,		PIN(F, 2), GPIO_INPUT | GPIO_PULL_UP)
 GPIO(UNUSED_GPIO96,		PIN(9, 6), GPIO_INPUT | GPIO_PULL_UP)
 GPIO(UNUSED_GPIO34,		PIN(3, 4), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIO56,		PIN(5, 6), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIOD4,		PIN(D, 4), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIO95,		PIN(9, 5), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIO81,		PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIO93,		PIN(9, 3), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIO97,		PIN(9, 7), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIOB5,		PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)	/* Unused I2C port, Set input only */
+GPIO(UNUSED_GPIOB4,		PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)	/* Unused I2C port, Set input only */
 
 /*
  * eDP backlight - both PCH and EC have enable pins that must be high
@@ -127,8 +118,6 @@ GPIO(UNUSED_GPIO34,		PIN(3, 4), GPIO_INPUT | GPIO_PULL_UP)
 GPIO(EC_EDP_BL_EN,             PIN(D, 3), GPIO_OUT_HIGH)
 
 /* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(EC_I2C0_SENSOR_SCL,       PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C0_SENSOR_SDA,       PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
 GPIO(EC_I2C1_USB_C0_SCL,       PIN(9, 0), GPIO_INPUT)
 GPIO(EC_I2C1_USB_C0_SDA,       PIN(8, 7), GPIO_INPUT)
 GPIO(EC_I2C2_USB_C1_SCL,       PIN(9, 2), GPIO_INPUT)
@@ -144,19 +133,12 @@ GPIO(EC_I2C7_EEPROM_PWR_SDA_R, PIN(B, 2), GPIO_INPUT)
 GPIO(EC_BATT_PRES_ODL, 		PIN(E, 1), GPIO_INPUT)
 
 /* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, BIT(5) | BIT(4)), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V)) /* I2C0 */
 ALTERNATE(PIN_MASK(9, BIT(0) | BIT(2) | BIT(1)), 0, MODULE_I2C, 0)                   /* I2C1 SCL / I2C2 */
 ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)                                     /* I2C1 SDA */
 ALTERNATE(PIN_MASK(D, BIT(1) | BIT(0)), 0, MODULE_I2C, 0)                            /* I2C3 */
 ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)                            /* I2C5 */
 ALTERNATE(PIN_MASK(B, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)                            /* I2C7 */
 
-/* This selects between an LED module on the motherboard and one on the daughter
- * board, to be controlled by LED_{1,2,3}_L. PWM allows driving both modules at
- * the same time. */
-ALTERNATE(PIN_MASK(6, BIT(0)), 0, MODULE_PWM, 0)                                     /* LED_SIDESEL_4_L */
-ALTERNATE(PIN_MASK(C, BIT(2) | BIT(3) | BIT(4)), 0, MODULE_PWM, 0)                   /* LED_{3,2,1}_L */
-
 /* Fan signals */
 GPIO(EN_PP5000_FAN,            PIN(6, 1), GPIO_OUT_LOW)
 ALTERNATE(PIN_MASK(B, BIT(7)), 0, MODULE_PWM, 0)	/* FAN_PWM */
@@ -182,3 +164,6 @@ ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)  /* GPIO00 =
                                                                        GPIO01 = H1_EC_PWR_BTN_ODL
                                                                        GPIO02 = EC_RST_ODL */
 
+/* Temperature sensors */
+ALTERNATE(PIN_MASK(4, BIT(2) | BIT(4) | BIT(5)), 0, MODULE_ADC, 0) /* TEMP_SENSOR1,2,4 */
+ALTERNATE(PIN_MASK(F, BIT(1)), 0, MODULE_ADC, 0) /* TEMP_SENSOR3 */
diff --git a/board/elemi/led.c b/board/elemi/led.c
index 4486bcb912..f8ac543350 100644
--- a/board/elemi/led.c
+++ b/board/elemi/led.c
@@ -1,104 +1,203 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
- * Power and battery LED control for Volteer
+ * Power and battery LED control for Elemi
  */
 
+#include "battery.h"
 #include "charge_manager.h"
-#include "common.h"
+#include "charge_state.h"
+#include "chipset.h"
 #include "ec_commands.h"
+#include "gpio.h"
 #include "hooks.h"
+#include "host_command.h"
 #include "led_common.h"
-#include "led_pwm.h"
-#include "pwm.h"
+
+#define BAT_LED_ON 0
+#define BAT_LED_OFF 1
+
+#define POWER_LED_ON 0
+#define POWER_LED_OFF 1
+
+#define LED_CYCLE_TIME_MS (2 * 1000)
+#define LED_TICKS_PER_CYCLE (LED_CYCLE_TIME_MS / HOOK_TICK_INTERVAL_MS)
+#define LED_ON_TIME_MS (1 * 1000)
+#define LED_ON_TICKS (LED_ON_TIME_MS / HOOK_TICK_INTERVAL_MS)
 
 const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
+	EC_LED_ID_LEFT_LED,
+	EC_LED_ID_RIGHT_LED,
 };
+
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-struct pwm_led led_color_map[] = {
-				/* Red, Green, Blue */
-	[EC_LED_COLOR_RED] =    {  100,   0,     0 },
-	[EC_LED_COLOR_GREEN] =  {    0, 100,     0 },
-	[EC_LED_COLOR_BLUE] =   {    0,   0,   100 },
-	/* The green LED seems to be brighter than the others, so turn down
-	 * green from its natural level for these secondary colors.
-	 */
-	[EC_LED_COLOR_YELLOW] = {  100,  70,     0 },
-	[EC_LED_COLOR_WHITE] =  {  100,  70,   100 },
-	[EC_LED_COLOR_AMBER] =  {  100,  20,     0 },
+enum led_color {
+	LED_OFF = 0,
+	LED_AMBER,
+	LED_WHITE,
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
-struct pwm_led pwm_leds[] = {
-	/* 2 RGB diffusers controlled by 1 set of 3 channels. */
-	[PWM_LED0] = {
-		.ch0 = PWM_CH_LED3_RED,
-		.ch1 = PWM_CH_LED2_GREEN,
-		.ch2 = PWM_CH_LED1_BLUE,
-		.enable = &pwm_enable,
-		.set_duty = &pwm_set_duty,
-	},
-};
+enum led_port { RIGHT_PORT = 0, LEFT_PORT };
+
+static void led_set_color_battery(int port, enum led_color color)
+{
+	enum gpio_signal amber_led, white_led;
+
+	amber_led = (port == RIGHT_PORT ? GPIO_C0_CHARGE_LED_AMBER_L :
+					  GPIO_C1_CHARGE_LED_AMBER_L);
+	white_led = (port == RIGHT_PORT ? GPIO_C0_CHARGE_LED_WHITE_L :
+					  GPIO_C1_CHARGE_LED_WHITE_L);
+
+	switch (color) {
+	case LED_WHITE:
+		gpio_set_level(white_led, BAT_LED_ON);
+		gpio_set_level(amber_led, BAT_LED_OFF);
+		break;
+	case LED_AMBER:
+		gpio_set_level(white_led, BAT_LED_OFF);
+		gpio_set_level(amber_led, BAT_LED_ON);
+		break;
+	case LED_OFF:
+		gpio_set_level(white_led, BAT_LED_OFF);
+		gpio_set_level(amber_led, BAT_LED_OFF);
+		break;
+	default:
+		break;
+	}
+}
 
 void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
 {
-	brightness_range[EC_LED_COLOR_RED] = 255;
-	brightness_range[EC_LED_COLOR_GREEN] = 255;
-	brightness_range[EC_LED_COLOR_BLUE] = 255;
+	switch (led_id) {
+	case EC_LED_ID_LEFT_LED:
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		break;
+	case EC_LED_ID_RIGHT_LED:
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		break;
+	default:
+		break;
+	}
 }
 
 int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 {
-	enum pwm_led_id pwm_id;
-
-	/* Convert ec_led_id to pwm_led_id. */
-	if (led_id == EC_LED_ID_POWER_LED)
-		pwm_id = PWM_LED0;
-	else
-		return EC_ERROR_UNKNOWN;
-
-	if (brightness[EC_LED_COLOR_RED])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_RED);
-	else if (brightness[EC_LED_COLOR_GREEN])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_GREEN);
-	else if (brightness[EC_LED_COLOR_BLUE])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_BLUE);
-	else if (brightness[EC_LED_COLOR_YELLOW])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_YELLOW);
-	else if (brightness[EC_LED_COLOR_WHITE])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_WHITE);
-	else if (brightness[EC_LED_COLOR_AMBER])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_AMBER);
-	else
-		/* Otherwise, the "color" is "off". */
-		set_pwm_led_color(pwm_id, -1);
+	switch (led_id) {
+	case EC_LED_ID_LEFT_LED:
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_battery(LEFT_PORT, LED_WHITE);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(LEFT_PORT, LED_AMBER);
+		else
+			led_set_color_battery(LEFT_PORT, LED_OFF);
+		break;
+	case EC_LED_ID_RIGHT_LED:
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_battery(RIGHT_PORT, LED_WHITE);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(RIGHT_PORT, LED_AMBER);
+		else
+			led_set_color_battery(RIGHT_PORT, LED_OFF);
+		break;
+	default:
+		return EC_ERROR_PARAM1;
+	}
 
 	return EC_SUCCESS;
 }
 
-/* Illuminates the LED on the side of the active charging port. If not charging,
- * illuminates both LEDs.
+/*
+ * Set active charge port color to the parameter, turn off all others.
+ * If no port is active (-1), turn off all LEDs.
  */
-static void led_set_charge_port_tick(void)
+static void set_active_port_color(enum led_color color)
 {
-	int port;
-	int side_select_duty;
+	int port = charge_manager_get_active_charge_port();
+
+	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
+		led_set_color_battery(RIGHT_PORT,
+				      (port == RIGHT_PORT) ? color : LED_OFF);
+	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
+		led_set_color_battery(LEFT_PORT,
+				      (port == LEFT_PORT) ? color : LED_OFF);
+}
+
+static void led_set_battery(void)
+{
+	static int battery_ticks;
+	static int suspend_ticks;
+
+	battery_ticks++;
+
+	/*
+	 * Override battery LEDs for Elemi, Elemi doesn't have power LED,
+	 * blinking both two side battery white LEDs to indicate
+	 * system suspend without charging state.
+	 */
+	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
+	    led_pwr_get_state() != LED_PWRS_CHARGE) {
+		suspend_ticks++;
 
-	port = charge_manager_get_active_charge_port();
-	switch (port) {
-	case 0:
-		side_select_duty = 100;
+		led_set_color_battery(
+			RIGHT_PORT, suspend_ticks & 0x4 ? LED_WHITE : LED_OFF);
+		led_set_color_battery(
+			LEFT_PORT, suspend_ticks & 0x4 ? LED_WHITE : LED_OFF);
+		return;
+	}
+
+	suspend_ticks = 0;
+
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
+		/* Always indicate when charging, even in suspend. */
+		set_active_port_color(LED_AMBER);
+		break;
+	case LED_PWRS_DISCHARGE:
+		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
+			if (charge_get_percent() < 10)
+				led_set_color_battery(
+					RIGHT_PORT,
+					(battery_ticks % LED_TICKS_PER_CYCLE <
+					 LED_ON_TICKS) ?
+						LED_WHITE :
+						LED_OFF);
+			else
+				led_set_color_battery(RIGHT_PORT, LED_OFF);
+		}
+
+		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
+			led_set_color_battery(LEFT_PORT, LED_OFF);
+		break;
+	case LED_PWRS_ERROR:
+		set_active_port_color((battery_ticks & 0x2) ? LED_WHITE :
+							      LED_OFF);
 		break;
-	case 1:
-		side_select_duty = 0;
+	case LED_PWRS_CHARGE_NEAR_FULL:
+		set_active_port_color(LED_WHITE);
+		break;
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		set_active_port_color(LED_WHITE);
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		set_active_port_color(
+			(battery_ticks % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
+				LED_AMBER :
+				LED_OFF);
 		break;
 	default:
-		side_select_duty = 50;
+		/* Other states don't alter LED behavior */
+		break;
 	}
+}
 
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		pwm_set_duty(PWM_CH_LED4_SIDESEL, side_select_duty);
+/* Called by hook task every TICK */
+static void led_tick(void)
+{
+	led_set_battery();
 }
-DECLARE_HOOK(HOOK_TICK, led_set_charge_port_tick, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
diff --git a/board/elemi/sensors.c b/board/elemi/sensors.c
deleted file mode 100644
index 9e34812131..0000000000
--- a/board/elemi/sensors.c
+++ /dev/null
@@ -1,245 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer family-specific sensor configuration */
-#include "common.h"
-#include "accelgyro.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_bmi260.h"
-#include "driver/als_tcs3400.h"
-#include "driver/sync.h"
-#include "keyboard_scan.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "task.h"
-#include "tablet_mode.h"
-#include "util.h"
-
-/******************************************************************************/
-/* Sensors */
-static struct mutex g_lid_accel_mutex;
-static struct mutex g_base_mutex;
-
-/* BMA253 private data */
-static struct accelgyro_saved_data_t g_bma253_data;
-
-/* BMI260 private data */
-static struct bmi_drv_data_t g_bmi260_data;
-
-/* TCS3400 private data */
-static struct als_drv_data_t g_tcs3400_data = {
-	.als_cal.scale = 1,
-	.als_cal.uscale = 0,
-	.als_cal.offset = 0,
-	.als_cal.channel_scale = {
-		.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kc from VPD */
-		.cover_scale = ALS_CHANNEL_SCALE(1.0),     /* CT */
-	},
-};
-
-/*
- * TODO: b/146166425 need to calibrate ALS/RGB sensor. At default settings,
- * shining phone flashlight on sensor pegs all readings at 0xFFFF.
- */
-static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
-	.calibration.rgb_cal[X] = {
-		.offset = 0,
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kr */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		}
-	},
-	.calibration.rgb_cal[Y] = {
-		.offset = 0,
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kg */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		},
-	},
-	.calibration.rgb_cal[Z] = {
-		.offset = 0,
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kb */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		}
-	},
-	.calibration.irt = INT_TO_FP(1),
-	.saturation.again = TCS_DEFAULT_AGAIN,
-	.saturation.atime = TCS_DEFAULT_ATIME,
-};
-
-/* Rotation matrix for the lid accelerometer */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_lid_accel_mutex,
-		.drv_data = &g_bma253_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.default_range = 2, /* g, to support tablet mode */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI260,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi260_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi260_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.default_range = 4, /* g */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI260,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi260_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi260_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-	[CLEAR_ALS] = {
-		.name = "Clear Light",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_TCS3400,
-		.type = MOTIONSENSE_TYPE_LIGHT,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &tcs3400_drv,
-		.drv_data = &g_tcs3400_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = TCS3400_I2C_ADDR_FLAGS,
-		.rot_standard_ref = NULL,
-		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
-		.min_frequency = TCS3400_LIGHT_MIN_FREQ,
-		.max_frequency = TCS3400_LIGHT_MAX_FREQ,
-		.config = {
-			/* Run ALS sensor in S0 */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 1000,
-			},
-		},
-	},
-
-	[RGB_ALS] = {
-		/*
-		 * RGB channels read by CLEAR_ALS and so the i2c port and
-		 * address do not need to be defined for RGB_ALS.
-		 */
-		.name = "RGB Light",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_TCS3400,
-		.type = MOTIONSENSE_TYPE_LIGHT_RGB,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &tcs3400_rgb_drv,
-		.drv_data = &g_tcs3400_rgb_data,
-		.rot_standard_ref = NULL,
-		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
-	},
-};
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/* ALS instances when LPC mapping is needed. Each entry directs to a sensor. */
-const struct motion_sensor_t *motion_als_sensors[] = {
-	&motion_sensors[CLEAR_ALS],
-};
-BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
-
-static void baseboard_sensors_init(void)
-{
-	/* Note - BMA253 interrupt unused by EC */
-
-	/* Enable interrupt for the TCS3400 color light sensor */
-	gpio_enable_interrupt(GPIO_EC_ALS_RGB_INT_L);
-	/* Enable interrupt for the BMI260 accel/gyro sensor */
-	gpio_enable_interrupt(GPIO_EC_IMU_INT_L);
-}
-DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_DEFAULT);
-
-#ifndef TEST_BUILD
-void lid_angle_peripheral_enable(int enable)
-{
-	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
-
-	if (enable) {
-		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
-	} else {
-		/*
-		 * Ensure that the chipset is off before disabling the keyboard.
-		 * When the chipset is on, the EC keeps the keyboard enabled and
-		 * the AP decides whether to ignore input devices or not.
-		 */
-		if (!chipset_in_s0)
-			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
-	}
-}
-#endif
diff --git a/board/elemi/vif_override.xml b/board/elemi/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/elemi/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/elm/battery.c b/board/elm/battery.c
index de9685a89d..9ef59414a2 100644
--- a/board/elm/battery.c
+++ b/board/elm/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,8 +10,8 @@
 #include "util.h"
 
 /* Shutdown mode parameter to write to manufacturer access register */
-#define SB_SHIP_MODE_REG	0x3a
-#define SB_SHUTDOWN_DATA	0xC574
+#define SB_SHIP_MODE_REG 0x3a
+#define SB_SHUTDOWN_DATA 0xC574
 
 static const struct battery_info info = {
 	.voltage_max = 13200,
diff --git a/board/elm/board.c b/board/elm/board.c
index a893a57416..15362ee635 100644
--- a/board/elm/board.c
+++ b/board/elm/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,6 @@
 /* Oak board configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "atomic.h"
 #include "battery.h"
 #include "charge_manager.h"
@@ -50,8 +49,8 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* Dispaly port hardware can connect to port 0, 1 or neither. */
 #define PD_PORT_NONE -1
@@ -67,15 +66,16 @@ DECLARE_DEFERRED(deferred_reset_pd_mcu);
 void usb_evt(enum gpio_signal signal)
 {
 	if (!gpio_get_level(GPIO_BC12_WAKE_L))
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
 }
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /* power signal list.  Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
-	{GPIO_SOC_POWER_GOOD, POWER_SIGNAL_ACTIVE_HIGH, "POWER_GOOD"},
-	{GPIO_SUSPEND_L, POWER_SIGNAL_ACTIVE_LOW, "SUSPEND#_ASSERTED"},
+	{ GPIO_SOC_POWER_GOOD, POWER_SIGNAL_ACTIVE_HIGH, "POWER_GOOD" },
+	{ GPIO_SUSPEND_L, POWER_SIGNAL_ACTIVE_LOW, "SUSPEND#_ASSERTED" },
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
@@ -85,18 +85,18 @@ const struct adc_t adc_channels[] = {
 	 * PSYS_MONITOR(PA2): ADC_IN2, 1.44 uA/W on 6.05k Ohm
 	 * output in mW
 	 */
-	[ADC_PSYS] = {"PSYS", 379415, 4096, 0, STM32_AIN(2)},
+	[ADC_PSYS] = { "PSYS", 379415, 4096, 0, STM32_AIN(2) },
 	/* AMON_BMON(PC0): ADC_IN10, output in uV */
-	[ADC_AMON_BMON] = {"AMON_BMON", 183333, 4096, 0, STM32_AIN(10)},
+	[ADC_AMON_BMON] = { "AMON_BMON", 183333, 4096, 0, STM32_AIN(10) },
 	/* VDC_BOOSTIN_SENSE(PC1): ADC_IN11, output in mV */
-	[ADC_VBUS] = {"VBUS", 33000, 4096, 0, STM32_AIN(11)},
+	[ADC_VBUS] = { "VBUS", 33000, 4096, 0, STM32_AIN(11) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 int anx7688_passthru_allowed(const struct i2c_port_t *port,
 			     const uint16_t addr_flags)
 {
-	uint16_t addr = I2C_GET_ADDR(addr_flags);
+	uint16_t addr = I2C_STRIP_FLAGS(addr_flags);
 
 	/* Allow access to 0x2c (TCPC) */
 	if (addr == 0x2c)
@@ -108,11 +108,18 @@ int anx7688_passthru_allowed(const struct i2c_port_t *port,
 }
 
 /* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"battery", I2C_PORT_BATTERY, 100,  GPIO_I2C0_SCL, GPIO_I2C0_SDA},
-	{"pd",      I2C_PORT_PD_MCU,  1000, GPIO_I2C1_SCL, GPIO_I2C1_SDA,
-		anx7688_passthru_allowed}
-};
+const struct i2c_port_t i2c_ports[] = { { .name = "battery",
+					  .port = I2C_PORT_BATTERY,
+					  .kbps = 100,
+					  .scl = GPIO_I2C0_SCL,
+					  .sda = GPIO_I2C0_SDA },
+					{ .name = "pd",
+					  .port = I2C_PORT_PD_MCU,
+					  .kbps = 1000,
+					  .scl = GPIO_I2C1_SCL,
+					  .sda = GPIO_I2C1_SDA,
+					  .passthru_allowed =
+						  anx7688_passthru_allowed } };
 
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -151,22 +158,24 @@ BUILD_ASSERT(ARRAY_SIZE(pi3usb9281_chips) ==
  */
 const struct temp_sensor_t temp_sensors[] = {
 #ifdef CONFIG_TEMP_SENSOR_TMP432
-	{"TMP432_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-		TMP432_IDX_LOCAL},
-	{"TMP432_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-		TMP432_IDX_REMOTE1},
-	{"TMP432_Sensor_2", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-		TMP432_IDX_REMOTE2},
+	{ "TMP432_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
+	  TMP432_IDX_LOCAL },
+	{ "TMP432_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
+	  TMP432_IDX_REMOTE1 },
+	{ "TMP432_Sensor_2", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
+	  TMP432_IDX_REMOTE2 },
 #endif
-	{"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp,
-		0},
+	{ "Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.driver    = &anx7688_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &anx7688_usb_mux_driver,
+			},
 	},
 };
 
@@ -196,7 +205,7 @@ void deferred_reset_pd_mcu(void)
 		 * and wait for 1ms.
 		 */
 		gpio_set_level(GPIO_USB_C0_PWR_EN_L, 1);
-		hook_call_deferred(&deferred_reset_pd_mcu_data, 1*MSEC);
+		hook_call_deferred(&deferred_reset_pd_mcu_data, 1 * MSEC);
 		break;
 	case 1:
 		/*
@@ -204,9 +213,9 @@ void deferred_reset_pd_mcu(void)
 		 * pull PD reset pin and wait for another 1ms
 		 */
 		gpio_set_level(GPIO_USB_C0_RST, 1);
-		hook_call_deferred(&deferred_reset_pd_mcu_data, 1*MSEC);
+		hook_call_deferred(&deferred_reset_pd_mcu_data, 1 * MSEC);
 		/* on PD reset, trigger PD task to reset state */
-		task_set_event(TASK_ID_PD_C0, PD_EVENT_TCPC_RESET, 0);
+		task_set_event(TASK_ID_PD_C0, PD_EVENT_TCPC_RESET);
 		break;
 	case 3:
 		/*
@@ -214,7 +223,7 @@ void deferred_reset_pd_mcu(void)
 		 * enable power and wait for 10ms then pull RESET_N
 		 */
 		gpio_set_level(GPIO_USB_C0_PWR_EN_L, 0);
-		hook_call_deferred(&deferred_reset_pd_mcu_data, 10*MSEC);
+		hook_call_deferred(&deferred_reset_pd_mcu_data, 10 * MSEC);
 		break;
 	case 2:
 		/*
@@ -233,7 +242,7 @@ static void board_power_on_pd_mcu(void)
 		return;
 
 	gpio_set_level(GPIO_USB_C0_EXTPWR_EN, 1);
-	hook_call_deferred(&deferred_reset_pd_mcu_data, 1*MSEC);
+	hook_call_deferred(&deferred_reset_pd_mcu_data, 1 * MSEC);
 }
 
 void board_reset_pd_mcu(void)
@@ -242,17 +251,15 @@ void board_reset_pd_mcu(void)
 	anx7688_enable_cable_detection(0);
 
 	/* wait for 10ms, then start port controller's reset sequence */
-	hook_call_deferred(&deferred_reset_pd_mcu_data, 10*MSEC);
+	hook_call_deferred(&deferred_reset_pd_mcu_data, 10 * MSEC);
 }
 
-int command_pd_reset(int argc, char **argv)
+static int command_pd_reset(int argc, const char **argv)
 {
 	board_reset_pd_mcu();
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(resetpd, command_pd_reset,
-			"",
-			"Reset PD IC");
+DECLARE_CONSOLE_COMMAND(resetpd, command_pd_reset, "", "Reset PD IC");
 
 /**
  * There is a level shift for AC_OK & LID_OPEN signal between AP & EC,
@@ -331,13 +338,10 @@ int board_set_active_charge_port(int charge_port)
  * @param charge_ma     Desired charge limit (mA).
  * @param charge_mv     Negotiated charge voltage (mV).
  */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
 {
-	/* Limit input current 95% ratio on elm board for safety */
-	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-				   CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+	charge_set_input_current_limit(charge_ma, charge_mv);
 	pd_send_host_event(PD_EVENT_POWER_CHANGE);
 }
 
@@ -388,7 +392,7 @@ static void board_chipset_pre_init(void)
 	board_extpower_buffer_to_soc();
 
 	/* Enable SPI for KX022 */
-	gpio_config_module(MODULE_SPI_MASTER, 1);
+	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
 
 	/* Set all four SPI pins to high speed */
 	/* pins D0/D1/D3/D4 */
@@ -403,7 +407,7 @@ static void board_chipset_pre_init(void)
 	STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2;
 	STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
 
-	spi_enable(CONFIG_SPI_ACCEL_PORT, 1);
+	spi_enable(&spi_devices[0], 1);
 }
 DECLARE_HOOK(HOOK_CHIPSET_PRE_INIT, board_chipset_pre_init, HOOK_PRIO_DEFAULT);
 
@@ -413,12 +417,12 @@ static void board_chipset_shutdown(void)
 	/* Disable level shift to SoC when shutting down */
 	gpio_set_level(GPIO_LEVEL_SHIFT_EN_L, 1);
 
-	spi_enable(CONFIG_SPI_ACCEL_PORT, 0);
+	spi_enable(&spi_devices[0], 0);
 
 	/* Disable clocks to SPI2 module */
 	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
 
-	gpio_config_module(MODULE_SPI_MASTER, 0);
+	gpio_config_module(MODULE_SPI_CONTROLLER, 0);
 
 	/*
 	 * Calling gpio_config_module sets disabled alternate function pins to
@@ -448,23 +452,18 @@ static void board_chipset_suspend(void)
 }
 DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
 
-#ifdef HAS_TASK_MOTIONSENSE
 /* Motion sensors */
 /* Mutexes */
 static struct mutex g_kx022_mutex[2];
 
 /* Matrix to rotate accelerometer into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0,  0},
-	{ 0,  FLOAT_TO_FP(1),  0},
-	{ 0,  0, FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				       { 0, FLOAT_TO_FP(1), 0 },
+				       { 0, 0, FLOAT_TO_FP(-1) } };
 
-const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1),  0,  0},
-	{ 0, FLOAT_TO_FP(-1),  0},
-	{ 0,  0, FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+				      { 0, FLOAT_TO_FP(-1), 0 },
+				      { 0, 0, FLOAT_TO_FP(-1) } };
 
 /* KX022 private data */
 struct kionix_accel_data g_kx022_data[2];
@@ -479,7 +478,7 @@ struct motion_sensor_t motion_sensors[] = {
 		.drv = &kionix_accel_drv,
 		.mutex = &g_kx022_mutex[0],
 		.drv_data = &g_kx022_data[0],
-		.i2c_spi_addr_flags = SLAVE_MK_SPI_ADDR_FLAGS(0),
+		.i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(0),
 		.rot_standard_ref = &base_standard_ref,
 		.default_range = 2, /* g, enough for lid angle calculation. */
 		.min_frequency = KX022_ACCEL_MIN_FREQ,
@@ -502,7 +501,7 @@ struct motion_sensor_t motion_sensors[] = {
 		.drv = &kionix_accel_drv,
 		.mutex = &g_kx022_mutex[1],
 		.drv_data = &g_kx022_data[1],
-		.i2c_spi_addr_flags = SLAVE_MK_SPI_ADDR_FLAGS(1),
+		.i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(1),
 		.rot_standard_ref = &lid_standard_ref,
 		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
 		.min_frequency = KX022_ACCEL_MIN_FREQ,
@@ -519,17 +518,15 @@ struct motion_sensor_t motion_sensors[] = {
 
 const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
-void lid_angle_peripheral_enable(int enable)
+__override void lid_angle_peripheral_enable(int enable)
 {
 	keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
 
 	/* enable/disable touchpad */
 	gpio_set_level(GPIO_EN_TP_INT_L, !enable);
 }
-#endif /* defined(HAS_TASK_MOTIONSENSE) */
 
 uint16_t tcpc_get_alert_status(void)
 {
 	return gpio_get_level(GPIO_PD_MCU_INT) ? PD_STATUS_TCPC_ALERT_0 : 0;
 }
-
diff --git a/board/elm/board.h b/board/elm/board.h
index a248f6b757..42c8e06c35 100644
--- a/board/elm/board.h
+++ b/board/elm/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,17 +14,20 @@
  */
 #define CONFIG_SYSTEM_UNLOCKED
 
+/* Free up flash space */
+#undef CONFIG_USB_PD_TCPMV1_DEBUG
+#define CONFIG_LTO
+
 /* Accelero meter and gyro sensor */
 #define CONFIG_ACCEL_KX022
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
+#undef CONfFIG_CMD_ACCELSPOOF
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
 #define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
 #define CONFIG_LID_ANGLE_UPDATE
 
 #define CONFIG_ADC
-#undef  CONFIG_ADC_WATCHDOG
+#undef CONFIG_ADC_WATCHDOG
 
 /* AC adaptor, charger, battery */
 #define CONFIG_BATTERY_CUT_OFF
@@ -34,13 +37,16 @@
 #define CONFIG_BATTERY_SMART
 #define CONFIG_CHARGE_MANAGER
 #define CONFIG_CHARGER
-#define CONFIG_CHARGER_INPUT_CURRENT 512
+#define CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT 512
+#define CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT 512
 #define CONFIG_CHARGE_RAMP_HW
 #define CONFIG_CHARGER_ISL9237
 #define CONFIG_CHARGER_MAX_INPUT_CURRENT 3000
 #define CONFIG_CHARGER_SENSE_RESISTOR 10
 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 20
 #define CONFIG_CHARGER_DISCHARGE_ON_AC
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 5
 #define CONFIG_CHIPSET_MT817X
 #define CONFIG_CMD_TYPEC
 #define CONFIG_EXTPOWER_GPIO
@@ -57,7 +63,7 @@
 /* Other configs */
 #define CONFIG_HOST_COMMAND_STATUS
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_CONTROLLER
 #define CONFIG_KEYBOARD_COL2_INVERTED
 #define CONFIG_KEYBOARD_PROTOCOL_MKBP
 #define CONFIG_LED_COMMON
@@ -69,13 +75,12 @@
 #define CONFIG_POWER_COMMON
 #define CONFIG_USB_CHARGER
 #define CONFIG_SPI
-#define CONFIG_SPI_MASTER
-#define CONFIG_STM_HWTIMER32
+#define CONFIG_SPI_CONTROLLER
 #define CONFIG_VBOOT_HASH
-#undef  CONFIG_WATCHDOG_HELP
+#undef CONFIG_WATCHDOG_HELP
 #define CONFIG_SWITCH
 #define CONFIG_BOARD_VERSION_GPIO
-#undef  CONFIG_UART_CONSOLE
+#undef CONFIG_UART_CONSOLE
 #define CONFIG_UART_CONSOLE 1
 #define CONFIG_TEMP_SENSOR
 #define CONFIG_DPTF
@@ -99,7 +104,7 @@
 #define CONFIG_USB_PD_TCPM_TCPCI
 #define CONFIG_USB_PD_TRY_SRC
 #define CONFIG_USB_PD_VBUS_DETECT_TCPC
-#undef  CONFIG_TCPC_I2C_BASE_ADDR_FLAGS
+#undef CONFIG_TCPC_I2C_BASE_ADDR_FLAGS
 #define CONFIG_TCPC_I2C_BASE_ADDR_FLAGS 0x2C
 #define CONFIG_USB_PD_ANX7688
 
@@ -120,6 +125,8 @@
 #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
 #define CONFIG_CMD_I2C_PROTECT
 #define CONFIG_HOSTCMD_PD_CONTROL
+/* Disable verbose output in EC pd */
+#define CONFIG_CMD_PD_SRCCAPS_REDUCED_SIZE
 
 /*
  * Flash layout:
@@ -139,11 +146,11 @@
 #undef CONFIG_EC_WRITABLE_STORAGE_OFF
 #undef CONFIG_EC_WRITABLE_STORAGE_SIZE
 #undef CONFIG_WP_STORAGE_SIZE
-#define CONFIG_RW_MEM_OFF                (128 * 1024)
-#define CONFIG_RW_SIZE                   (128 * 1024)
-#define CONFIG_EC_WRITABLE_STORAGE_OFF   (128 * 1024)
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE  (128 * 1024)
-#define CONFIG_WP_STORAGE_SIZE           (128 * 1024)
+#define CONFIG_RW_MEM_OFF (128 * 1024)
+#define CONFIG_RW_SIZE (128 * 1024)
+#define CONFIG_EC_WRITABLE_STORAGE_OFF (128 * 1024)
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE (128 * 1024)
+#define CONFIG_WP_STORAGE_SIZE (128 * 1024)
 
 /* Drivers */
 #ifndef __ASSEMBLER__
@@ -155,30 +162,30 @@
 #define KB_OUT_PORT_LIST GPIO_A, GPIO_B, GPIO_C, GPIO_D
 
 /* 2 I2C master ports, connect to battery, charger, pd and USB switches */
-#define I2C_PORT_MASTER  0
-#define I2C_PORT_ACCEL   0
+#define I2C_PORT_MASTER 0
+#define I2C_PORT_ACCEL 0
 #define I2C_PORT_BATTERY 0
 #define I2C_PORT_CHARGER 0
 #define I2C_PORT_PERICOM 0
 #define I2C_PORT_THERMAL 0
-#define I2C_PORT_PD_MCU  1
+#define I2C_PORT_PD_MCU 1
 #define I2C_PORT_USB_MUX 1
-#define I2C_PORT_TCPC    1
+#define I2C_PORT_TCPC 1
 
 /* Enable Accel over SPI */
-#define CONFIG_SPI_ACCEL_PORT    0  /* First SPI master port (SPI2) */
+#define CONFIG_SPI_ACCEL_PORT 0 /* First SPI controller port (SPI2) */
 
 /* Timer selection */
 #define TIM_CLOCK32 2
 #define TIM_WATCHDOG 4
 
 /* Define the host events which are allowed to wakeup AP in S3. */
-#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \
-		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_FASTBOOT))
+#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK                     \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |          \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |      \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |       \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_FASTBOOT))
 
 #include "gpio_signal.h"
 
@@ -196,9 +203,9 @@ enum pwm_channel {
 };
 
 enum adc_channel {
-	ADC_PSYS = 0,  /* PC1: STM32_AIN(2) */
+	ADC_PSYS = 0, /* PC1: STM32_AIN(2) */
 	ADC_AMON_BMON, /* PC0: STM32_AIN(10) */
-	ADC_VBUS,      /* PA2: STM32_AIN(11) */
+	ADC_VBUS, /* PA2: STM32_AIN(11) */
 	ADC_CH_COUNT
 };
 
@@ -226,17 +233,16 @@ enum sensor_id {
  * delay to turn on the power supply max is ~16ms.
  * delay to turn off the power supply max is about ~180ms.
  */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* delay to turn on/off vconn */
-#define PD_VCONN_SWAP_DELAY 5000 /* us */
 
 /* Define typical operating power and max power */
 #define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       45000
-#define PD_MAX_CURRENT_MA     CONFIG_CHARGER_MAX_INPUT_CURRENT
-#define PD_MAX_VOLTAGE_MV     20000
+#define PD_MAX_POWER_MW 45000
+#define PD_MAX_CURRENT_MA CONFIG_CHARGER_MAX_INPUT_CURRENT
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* The lower the input voltage, the higher the power efficiency. */
 #define PD_PREFER_LOW_VOLTAGE
@@ -246,6 +252,6 @@ void board_reset_pd_mcu(void);
 /* Set AP reset pin according to parameter */
 void board_set_ap_reset(int asserted);
 
-#endif  /* !__ASSEMBLER__ */
+#endif /* !__ASSEMBLER__ */
 
-#endif  /* __CROS_EC_BOARD_H */
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/elm/build.mk b/board/elm/build.mk
index 172a88e843..4d6ba76cae 100644
--- a/board/elm/build.mk
+++ b/board/elm/build.mk
@@ -1,5 +1,5 @@
 #-*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/elm/ec.tasklist b/board/elm/ec.tasklist
index 3ea68bf9f8..be745f7487 100644
--- a/board/elm/ec.tasklist
+++ b/board/elm/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/elm/gpio.inc b/board/elm/gpio.inc
index 246c97edcd..ef77ad732e 100644
--- a/board/elm/gpio.inc
+++ b/board/elm/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -110,4 +110,4 @@ ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART, GPIO_PULL_UP) /* USART1: PA9/PA10
 ALTERNATE(PIN_MASK(B, 0x00c0), 1, MODULE_I2C,        0) /* I2C MASTER:PB6/7 */
 ALTERNATE(PIN_MASK(B, 0x6000), 5, MODULE_I2C,        0) /* I2C MASTER:PB13/14 */
 ALTERNATE(PIN_MASK(A, 0x00f0), 0, MODULE_SPI,        0) /* SPI SLAVE:PA4/5/6/7 */
-ALTERNATE(PIN_MASK(D, 0x001A), 1, MODULE_SPI_MASTER, 0) /* SPI MASTER:PD1/3/4 */
+ALTERNATE(PIN_MASK(D, 0x001A), 1, MODULE_SPI_CONTROLLER, 0) /* SPI MASTER:PD1/3/4 */
diff --git a/board/elm/led.c b/board/elm/led.c
index d73cc05c1b..f420419456 100644
--- a/board/elm/led.c
+++ b/board/elm/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -12,17 +12,15 @@
 #include "hooks.h"
 #include "host_command.h"
 #include "led_common.h"
-#include "util.h"
 #include "system.h"
+#include "util.h"
 
 #define CRITICAL_LOW_BATTERY_PERMILLAGE 71
 #define LOW_BATTERY_PERMILLAGE 137
 #define FULL_BATTERY_PERMILLAGE 937
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -31,7 +29,7 @@ enum led_color {
 	BAT_LED_ORANGE,
 	PWR_LED_BLUE,
 	PWR_LED_ORANGE,
-	LED_COLOR_COUNT		/* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static int bat_led_set(enum led_color color, int on)
@@ -93,7 +91,7 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 	}
 }
 
-static unsigned blink_second;
+static unsigned int blink_second;
 
 static void elm_led_set_power(void)
 {
@@ -111,8 +109,7 @@ static void elm_led_set_power(void)
 		bat_led_set(PWR_LED_ORANGE, 0);
 	} else if (chipset_in_state(CHIPSET_STATE_SUSPEND)) {
 		bat_led_set(PWR_LED_BLUE, 0);
-		bat_led_set(PWR_LED_ORANGE,
-			    (blink_second & 3) ? 0 : 1);
+		bat_led_set(PWR_LED_ORANGE, (blink_second & 3) ? 0 : 1);
 	}
 }
 
@@ -135,11 +132,12 @@ static void elm_led_set_battery(void)
 	/* Make the percentage approximate to UI shown */
 	remaining_capacity = *(int *)host_get_memmap(EC_MEMMAP_BATT_CAP);
 	full_charge_capacity = *(int *)host_get_memmap(EC_MEMMAP_BATT_LFCC);
-	permillage = !full_charge_capacity ? 0 :
-		(1000 * remaining_capacity) / full_charge_capacity;
+	permillage = !full_charge_capacity ?
+			     0 :
+			     (1000 * remaining_capacity) / full_charge_capacity;
 
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
 		if (permillage < FULL_BATTERY_PERMILLAGE) {
 			bat_led_set(BAT_LED_BLUE, 0);
 			bat_led_set(BAT_LED_ORANGE, 1);
@@ -148,28 +146,26 @@ static void elm_led_set_battery(void)
 			bat_led_set(BAT_LED_ORANGE, 0);
 		}
 		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
+	case LED_PWRS_CHARGE_NEAR_FULL:
 		bat_led_set(BAT_LED_BLUE, 1);
 		bat_led_set(BAT_LED_ORANGE, 0);
 		break;
-	case PWR_STATE_DISCHARGE:
+	case LED_PWRS_DISCHARGE:
 		bat_led_set(BAT_LED_BLUE, 0);
 		if (!chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
 		    permillage <= CRITICAL_LOW_BATTERY_PERMILLAGE)
-			bat_led_set(BAT_LED_ORANGE,
-				    (blink_second & 1) ? 0 : 1);
+			bat_led_set(BAT_LED_ORANGE, (blink_second & 1) ? 0 : 1);
 		else if (!chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
 			 permillage <= LOW_BATTERY_PERMILLAGE)
-			bat_led_set(BAT_LED_ORANGE,
-				    (blink_second & 3) ? 0 : 1);
+			bat_led_set(BAT_LED_ORANGE, (blink_second & 3) ? 0 : 1);
 		else
 			bat_led_set(BAT_LED_ORANGE, 0);
 		break;
-	case PWR_STATE_ERROR:
+	case LED_PWRS_ERROR:
 		bat_led_set(BAT_LED_BLUE, 0);
 		bat_led_set(BAT_LED_ORANGE, (blink_second & 1) ? 0 : 1);
 		break;
-	case PWR_STATE_IDLE: /* Ext. power connected in IDLE. */
+	case LED_PWRS_IDLE: /* Ext. power connected in IDLE. */
 		if (charge_flags & CHARGE_FLAG_FORCE_IDLE) {
 			bat_led_set(BAT_LED_BLUE, (blink_second & 2) ? 0 : 1);
 			bat_led_set(BAT_LED_ORANGE, (blink_second & 2) ? 1 : 0);
diff --git a/board/elm/usb_pd_policy.c b/board/elm/usb_pd_policy.c
index 5cfc60650e..0369d8a15c 100644
--- a/board/elm/usb_pd_policy.c
+++ b/board/elm/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,12 +17,12 @@
 #include "system.h"
 #include "task.h"
 #include "timer.h"
-#include "util.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
+#include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_set_power_supply_ready(int port)
 {
@@ -87,7 +87,6 @@ __override int svdm_dp_attention(int port, uint32_t *payload)
 
 __override void svdm_exit_dp_mode(int port)
 {
-	svdm_safe_dp_mode(port);
 	anx7688_hpd_disable(port);
 }
 #endif /* CONFIG_USB_PD_ALT_MODE_DFP */
diff --git a/board/elm/vif_override.xml b/board/elm/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/elm/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/endeavour/board.c b/board/endeavour/board.c
index b3d44ec777..10ab236f0f 100644
--- a/board/endeavour/board.c
+++ b/board/endeavour/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,6 @@
 /* Endeavour board configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "battery.h"
 #include "bd99992gw.h"
 #include "board_config.h"
@@ -39,13 +38,14 @@
 #include "uart.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static uint8_t board_version;
 static uint32_t oem;
 static uint32_t sku;
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /* Hibernate wake configuration */
@@ -57,14 +57,15 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* Vbus sensing (1/10 voltage divider). */
-	[ADC_VBUS] = {"VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
+	[ADC_VBUS] = { "VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT * 10,
+		       ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* TODO: Verify fan control and mft */
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_FAN_PWR_EN,
 };
@@ -81,15 +82,31 @@ const struct fan_t fans[] = {
 BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
 
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN },
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
-const struct i2c_port_t i2c_ports[]  = {
-	{"pse", I2C_PORT_PSE, 400, GPIO_I2C0_0_SCL, GPIO_I2C0_0_SDA},
-	{"eeprom", I2C_PORT_EEPROM, 400, GPIO_I2C0_1_SCL, GPIO_I2C0_1_SDA},
-	{"pmic", I2C_PORT_PMIC, 400, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-	{"thermal", I2C_PORT_THERMAL, 400, GPIO_I2C3_SCL, GPIO_I2C3_SDA},
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "pse",
+	  .port = I2C_PORT_PSE,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_0_SCL,
+	  .sda = GPIO_I2C0_0_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_1_SCL,
+	  .sda = GPIO_I2C0_1_SDA },
+	{ .name = "pmic",
+	  .port = I2C_PORT_PMIC,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "thermal",
+	  .port = I2C_PORT_THERMAL,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -108,10 +125,10 @@ const int usb_port_enable[USB_PORT_COUNT] = {
  *     src/mainboard/google/${board}/acpi/dptf.asl
  */
 const struct temp_sensor_t temp_sensors[] = {
-	{"TMP431_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-			TMP432_IDX_LOCAL},
-	{"TMP431_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-			TMP432_IDX_REMOTE1},
+	{ "TMP431_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
+	  TMP432_IDX_LOCAL },
+	{ "TMP431_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
+	  TMP432_IDX_REMOTE1 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -119,14 +136,18 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
  * Thermal limits for each temp sensor.  All temps are in degrees K.  Must be in
  * same order as enum temp_sensor_id.  To always ignore any temp, use 0.
  */
+static const int temp_fan_off = C_TO_K(35);
+static const int temp_fan_max = C_TO_K(55);
 struct ec_thermal_config thermal_params[] = {
 	/* {Twarn, Thigh, Thalt}, <on>
 	 * {Twarn, Thigh, X    }, <off>
 	 * fan_off, fan_max
 	 */
-	{{0, C_TO_K(81), C_TO_K(82)}, {0, C_TO_K(77), 0},
-		C_TO_K(43), C_TO_K(76)},	/* TMP431_Internal */
-	{{0, 0, 0}, {0, 0, 0}, 0, 0},	/* TMP431_Sensor_1 */
+	{ { 0, C_TO_K(81), C_TO_K(82) },
+	  { 0, C_TO_K(77), 0 },
+	  temp_fan_off,
+	  temp_fan_max }, /* TMP431_Internal */
+	{ { 0, 0, 0 }, { 0, 0, 0 }, 0, 0 }, /* TMP431_Sensor_1 */
 };
 BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
 
@@ -295,34 +316,38 @@ int64_t get_time_dsw_pwrok(void)
 }
 
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED_RED]  = { 3, PWM_CONFIG_DSLEEP, 100 },
+	[PWM_CH_LED_RED] = { 3, PWM_CONFIG_DSLEEP, 100 },
 	[PWM_CH_LED_WHITE] = { 5, PWM_CONFIG_DSLEEP, 100 },
-	[PWM_CH_FAN] = {4, PWM_CONFIG_OPEN_DRAIN, 25000},
+	[PWM_CH_FAN] = { 4, PWM_CONFIG_OPEN_DRAIN, 25000 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
-struct fan_step {
-	int on;
-	int off;
-	int rpm;
+static const struct fan_step_1_1 fan_table0[] = {
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(35),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(41),
+	  .rpm = 2500 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(40),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(44),
+	  .rpm = 2900 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(42),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(46),
+	  .rpm = 3400 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(44),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(48),
+	  .rpm = 3900 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(46),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(50),
+	  .rpm = 4400 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(48),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(52),
+	  .rpm = 4900 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(50),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(55),
+	  .rpm = 5400 },
 };
-
-/* Note: Do not make the fan on/off point equal to 0 or 100 */
-static const struct fan_step fan_table0[] = {
-	{.on =  0, .off =  3, .rpm = 0},
-	{.on = 15, .off =  3, .rpm = 2500},
-	{.on = 36, .off = 18, .rpm = 3200},
-	{.on = 52, .off = 39, .rpm = 3500},
-	{.on = 61, .off = 55, .rpm = 3900},
-	{.on = 70, .off = 64, .rpm = 4500},
-	{.on = 82, .off = 73, .rpm = 5100},
-	{.on = 97, .off = 85, .rpm = 5400},
-};
-/* All fan tables must have the same number of levels */
 #define NUM_FAN_LEVELS ARRAY_SIZE(fan_table0)
 
-static const struct fan_step *fan_table = fan_table0;
-
+static const struct fan_step_1_1 *fan_table = fan_table0;
 
 static void cbi_init(void)
 {
@@ -347,43 +372,8 @@ static void board_init(void)
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
-int fan_percent_to_rpm(int fan, int pct)
+int fan_percent_to_rpm(int fan, int temp_ratio)
 {
-	static int current_level;
-	static int previous_pct;
-	int i;
-
-	/*
-	 * Compare the pct and previous pct, we have the three paths :
-	 *  1. decreasing path. (check the off point)
-	 *  2. increasing path. (check the on point)
-	 *  3. invariant path. (return the current RPM)
-	 */
-	if (pct < previous_pct) {
-		for (i = current_level; i >= 0; i--) {
-			if (pct <= fan_table[i].off)
-				current_level = i - 1;
-			else
-				break;
-		}
-	} else if (pct > previous_pct) {
-		for (i = current_level + 1; i < NUM_FAN_LEVELS; i++) {
-			if (pct >= fan_table[i].on)
-				current_level = i;
-			else
-				break;
-		}
-	}
-
-	if (current_level < 0)
-		current_level = 0;
-
-	previous_pct = pct;
-
-	if (fan_table[current_level].rpm !=
-		fan_get_rpm_target(FAN_CH(fan)))
-		cprints(CC_THERMAL, "Setting fan RPM to %d",
-			fan_table[current_level].rpm);
-
-	return fan_table[current_level].rpm;
+	return temp_ratio_to_rpm_hysteresis(fan_table, NUM_FAN_LEVELS, fan,
+					    temp_ratio, NULL);
 }
diff --git a/board/endeavour/board.h b/board/endeavour/board.h
index 29ca1316f9..9c0836b0e3 100644
--- a/board/endeavour/board.h
+++ b/board/endeavour/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,7 +12,7 @@
  * Allow dangerous commands.
  * TODO: Remove this config before production.
  */
-#undef  CONFIG_SYSTEM_UNLOCKED
+#undef CONFIG_SYSTEM_UNLOCKED
 #define CONFIG_USB_PD_COMM_LOCKED
 
 /* EC */
@@ -20,18 +20,18 @@
 #define CONFIG_BOARD_VERSION_CBI
 #define CONFIG_BOARD_HAS_RTC_RESET
 #define CONFIG_CRC8
-#define CONFIG_CROS_BOARD_INFO
+#define CONFIG_CBI_EEPROM
 #define CONFIG_DEDICATED_RECOVERY_BUTTON
 #define CONFIG_EMULATED_SYSRQ
 #define CONFIG_LED_COMMON
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
+#define CONFIG_MKBP_INPUT_DEVICES
 #define CONFIG_MKBP_USE_HOST_EVENT
 #define CONFIG_DPTF
-#define CONFIG_FLASH_SIZE 0x80000
+#define CONFIG_FLASH_SIZE_BYTES 0x80000
 #define CONFIG_FPU
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
-#undef  CONFIG_LID_SWITCH
+#define CONFIG_I2C_CONTROLLER
+#undef CONFIG_LID_SWITCH
 #define CONFIG_POWER_BUTTON_IGNORE_LID
 #define CONFIG_PWM
 #define CONFIG_LTO
@@ -49,8 +49,6 @@
 #define CONFIG_THROTTLE_AP
 #define CONFIG_CHIPSET_CAN_THROTTLE
 #define CONFIG_PWM
-#define CONFIG_SUPPRESSED_HOST_COMMANDS \
-	EC_CMD_CONSOLE_SNAPSHOT, EC_CMD_CONSOLE_READ, EC_CMD_PD_GET_LOG_ENTRY
 
 /* EC console commands */
 #define CONFIG_CMD_BUTTON
@@ -60,12 +58,13 @@
 #define CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET
 #define CONFIG_CHIPSET_HAS_PRE_INIT_CALLBACK
 #define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#define CONFIG_HOST_INTERFACE_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
+#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD
 
 #define CONFIG_EXTPOWER_GPIO
-#undef  CONFIG_EXTPOWER_DEBOUNCE_MS
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
 #define CONFIG_EXTPOWER_DEBOUNCE_MS 1000
 #define CONFIG_POWER_BUTTON
 #define CONFIG_POWER_BUTTON_X86
@@ -83,18 +82,18 @@
 #define USB_PORT_COUNT 4
 
 /* Optional feature to configure npcx chip */
-#define NPCX_UART_MODULE2	1 /* 1:GPIO64/65 as UART */
-#define NPCX_JTAG_MODULE2	0 /* 0:GPIO21/17/16/20 as JTAG */
-#define NPCX_TACH_SEL2		1 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
+#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART */
+#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 as JTAG */
+#define NPCX_TACH_SEL2 1 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
 
 /* I2C ports */
-#define I2C_PORT_PSE		NPCX_I2C_PORT0_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT0_1
-#define I2C_PORT_PMIC		NPCX_I2C_PORT2
-#define I2C_PORT_THERMAL	NPCX_I2C_PORT3
+#define I2C_PORT_PSE NPCX_I2C_PORT0_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT0_1
+#define I2C_PORT_PMIC NPCX_I2C_PORT2
+#define I2C_PORT_THERMAL NPCX_I2C_PORT3
 
 /* I2C addresses */
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 
 #define CONFIG_VBOOT_HASH
 #define CONFIG_VSTORE
@@ -110,15 +109,12 @@ enum charge_port {
 };
 
 enum temp_sensor_id {
-	TEMP_SENSOR_CHARGER,	/* BD99992GW SYSTHERM1 */
-	TEMP_SENSOR_DRAM,	/* BD99992GW SYSTHERM2 */
+	TEMP_SENSOR_CHARGER, /* BD99992GW SYSTHERM1 */
+	TEMP_SENSOR_DRAM, /* BD99992GW SYSTHERM2 */
 	TEMP_SENSOR_COUNT
 };
 
-enum adc_channel {
-	ADC_VBUS,
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_VBUS, ADC_CH_COUNT };
 
 enum pwm_channel {
 	PWM_CH_LED_RED,
diff --git a/board/endeavour/build.mk b/board/endeavour/build.mk
index 20f3f4d02c..2b19f6b43d 100644
--- a/board/endeavour/build.mk
+++ b/board/endeavour/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/endeavour/ec.tasklist b/board/endeavour/ec.tasklist
index ef58c6267a..9a4435f43e 100644
--- a/board/endeavour/ec.tasklist
+++ b/board/endeavour/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/endeavour/gpio.inc b/board/endeavour/gpio.inc
index 85904aab0c..e67f88347a 100644
--- a/board/endeavour/gpio.inc
+++ b/board/endeavour/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/endeavour/led.c b/board/endeavour/led.c
index b75de503e5..91bd6a3410 100644
--- a/board/endeavour/led.c
+++ b/board/endeavour/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -15,7 +15,7 @@
 #include "timer.h"
 #include "util.h"
 
-const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 enum led_color {
@@ -71,9 +71,9 @@ static int set_color(enum ec_led_id id, enum led_color color, int duty)
 	}
 }
 
-#define LED_PULSE_US		(2 * SECOND)
+#define LED_PULSE_US (2 * SECOND)
 /* 40 msec for nice and smooth transition. */
-#define LED_PULSE_TICK_US	(40 * MSEC)
+#define LED_PULSE_TICK_US (40 * MSEC)
 
 /* When pulsing is enabled, brightness is incremented by <duty_inc> every
  * <interval> usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented
@@ -167,7 +167,7 @@ void show_critical_error(void)
 		set_color(EC_LED_ID_POWER_LED, LED_RED, 100);
 }
 
-static int command_led(int argc, char **argv)
+static int command_led(int argc, const char **argv)
 {
 	enum ec_led_id id = EC_LED_ID_POWER_LED;
 
@@ -190,8 +190,7 @@ static int command_led(int argc, char **argv)
 	}
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(led, command_led,
-			"[debug|red|white|off|crit]",
+DECLARE_CONSOLE_COMMAND(led, command_led, "[debug|red|white|off|crit]",
 			"Turn on/off LED.");
 
 void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
diff --git a/board/endeavour/pse.c b/board/endeavour/pse.c
index cce1a104b1..bda7e1994d 100644
--- a/board/endeavour/pse.c
+++ b/board/endeavour/pse.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,44 +18,44 @@
 #include "timer.h"
 #include "util.h"
 
-#define LTC4291_I2C_ADDR	0x2C
-
-#define LTC4291_REG_SUPEVN_COR	0x0B
-#define LTC4291_REG_STATPWR	0x10
-#define LTC4291_REG_STATPIN	0x11
-#define LTC4291_REG_OPMD	0x12
-#define LTC4291_REG_DISENA	0x13
-#define LTC4291_REG_DETENA	0x14
-#define LTC4291_REG_DETPB	0x18
-#define LTC4291_REG_PWRPB	0x19
-#define LTC4291_REG_RSTPB	0x1A
-#define LTC4291_REG_ID		0x1B
-#define LTC4291_REG_DEVID	0x43
-#define LTC4291_REG_HPMD1	0x46
-#define LTC4291_REG_HPMD2	0x4B
-#define LTC4291_REG_HPMD3	0x50
-#define LTC4291_REG_HPMD4	0x55
-#define LTC4291_REG_LPWRPB	0x6E
-
-#define LTC4291_FLD_STATPIN_AUTO	BIT(0)
-#define LTC4291_FLD_RSTPB_RSTALL	BIT(4)
-
-#define LTC4291_STATPWR_ON_PORT(port)	(0x01 << (port))
-#define LTC4291_DETENA_EN_PORT(port)	(0x11 << (port))
-#define LTC4291_DETPB_EN_PORT(port)	(0x11 << (port))
-#define LTC4291_PWRPB_OFF_PORT(port)	(0x10 << (port))
-
-#define LTC4291_OPMD_AUTO	0xFF
-#define LTC4291_DISENA_ALL	0x0F
-#define LTC4291_DETENA_ALL	0xFF
-#define LTC4291_ID		0x64
-#define LTC4291_DEVID		0x38
-#define LTC4291_HPMD_MIN	0x00
-#define LTC4291_HPMD_MAX	0xA8
-
-#define LTC4291_PORT_MAX	4
-
-#define LTC4291_RESET_DELAY_US	(20 * MSEC)
+#define LTC4291_I2C_ADDR 0x2C
+
+#define LTC4291_REG_SUPEVN_COR 0x0B
+#define LTC4291_REG_STATPWR 0x10
+#define LTC4291_REG_STATPIN 0x11
+#define LTC4291_REG_OPMD 0x12
+#define LTC4291_REG_DISENA 0x13
+#define LTC4291_REG_DETENA 0x14
+#define LTC4291_REG_DETPB 0x18
+#define LTC4291_REG_PWRPB 0x19
+#define LTC4291_REG_RSTPB 0x1A
+#define LTC4291_REG_ID 0x1B
+#define LTC4291_REG_DEVID 0x43
+#define LTC4291_REG_HPMD1 0x46
+#define LTC4291_REG_HPMD2 0x4B
+#define LTC4291_REG_HPMD3 0x50
+#define LTC4291_REG_HPMD4 0x55
+#define LTC4291_REG_LPWRPB 0x6E
+
+#define LTC4291_FLD_STATPIN_AUTO BIT(0)
+#define LTC4291_FLD_RSTPB_RSTALL BIT(4)
+
+#define LTC4291_STATPWR_ON_PORT(port) (0x01 << (port))
+#define LTC4291_DETENA_EN_PORT(port) (0x11 << (port))
+#define LTC4291_DETPB_EN_PORT(port) (0x11 << (port))
+#define LTC4291_PWRPB_OFF_PORT(port) (0x10 << (port))
+
+#define LTC4291_OPMD_AUTO 0xFF
+#define LTC4291_DISENA_ALL 0x0F
+#define LTC4291_DETENA_ALL 0xFF
+#define LTC4291_ID 0x64
+#define LTC4291_DEVID 0x38
+#define LTC4291_HPMD_MIN 0x00
+#define LTC4291_HPMD_MAX 0xA8
+
+#define LTC4291_PORT_MAX 4
+
+#define LTC4291_RESET_DELAY_US (20 * MSEC)
 
 #define I2C_PSE_READ(reg, data) \
 	i2c_read8(I2C_PORT_PSE, LTC4291_I2C_ADDR, LTC4291_REG_##reg, (data))
@@ -63,7 +63,7 @@
 #define I2C_PSE_WRITE(reg, data) \
 	i2c_write8(I2C_PORT_PSE, LTC4291_I2C_ADDR, LTC4291_REG_##reg, (data))
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 static int pse_write_hpmd(int port, int val)
 {
@@ -170,7 +170,10 @@ static void pse_init(void)
 }
 DECLARE_HOOK(HOOK_CHIPSET_RESUME, pse_init, HOOK_PRIO_DEFAULT);
 
-static int command_pse(int argc, char **argv)
+/* Also reset the PSE on a reboot to toggle the power. */
+DECLARE_HOOK(HOOK_CHIPSET_RESET, pse_init, HOOK_PRIO_DEFAULT);
+
+static int command_pse(int argc, const char **argv)
 {
 	int port;
 
@@ -202,8 +205,7 @@ static int command_pse(int argc, char **argv)
 	else
 		return EC_ERROR_PARAM2;
 }
-DECLARE_CONSOLE_COMMAND(pse, command_pse,
-			"<port# 0-3> <off | on | min | max>",
+DECLARE_CONSOLE_COMMAND(pse, command_pse, "<port# 0-3> <off | on | min | max>",
 			"Set PSE port power");
 
 static int ec_command_pse_status(int port, uint8_t *status)
diff --git a/board/eve/battery.c b/board/eve/battery.c
index b5fb949ffe..d1ce1fd74a 100644
--- a/board/eve/battery.c
+++ b/board/eve/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -18,10 +18,10 @@
 #include "i2c.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 /* Shutdown mode parameter to write to manufacturer access register */
-#define SB_SHUTDOWN_DATA	0x0010
+#define SB_SHUTDOWN_DATA 0x0010
 
 /* Vendor CTO command parameter */
 #define SB_VENDOR_PARAM_CTO_DISABLE 0
@@ -81,16 +81,16 @@ static int otd_recovery_temp_reg = -1;
  * limits are given by discharging_min/max_c.
  */
 static const struct battery_info batt_info_lg = {
-	.voltage_max		= TARGET_WITH_MARGIN(8800, 5), /* mV */
-	.voltage_normal		= 7700,
-	.voltage_min		= 6100, /* Add 100mV for charger accuracy */
-	.precharge_current	= 256,	/* mA */
-	.start_charging_min_c	= 0,
-	.start_charging_max_c	= 46,
-	.charging_min_c		= 10,
-	.charging_max_c		= 50,
-	.discharging_min_c	= 0,
-	.discharging_max_c	= 60,
+	.voltage_max = TARGET_WITH_MARGIN(8800, 5), /* mV */
+	.voltage_normal = 7700,
+	.voltage_min = 6100, /* Add 100mV for charger accuracy */
+	.precharge_current = 256, /* mA */
+	.start_charging_min_c = 0,
+	.start_charging_max_c = 46,
+	.charging_min_c = 10,
+	.charging_max_c = 50,
+	.discharging_min_c = 0,
+	.discharging_max_c = 60,
 };
 
 /*
@@ -99,16 +99,16 @@ static const struct battery_info batt_info_lg = {
  * limits are given by discharging_min/max_c.
  */
 static const struct battery_info batt_info_lishen = {
-	.voltage_max		= TARGET_WITH_MARGIN(8800, 5), /* mV */
-	.voltage_normal		= 7700,
-	.voltage_min		= 6100, /* Add 100mV for charger accuracy */
-	.precharge_current	= 256,	/* mA */
-	.start_charging_min_c	= 0,
-	.start_charging_max_c	= 46,
-	.charging_min_c		= 10,
-	.charging_max_c		= 50,
-	.discharging_min_c	= 0,
-	.discharging_max_c	= 60,
+	.voltage_max = TARGET_WITH_MARGIN(8800, 5), /* mV */
+	.voltage_normal = 7700,
+	.voltage_min = 6100, /* Add 100mV for charger accuracy */
+	.precharge_current = 256, /* mA */
+	.start_charging_min_c = 0,
+	.start_charging_max_c = 46,
+	.charging_min_c = 10,
+	.charging_max_c = 50,
+	.discharging_min_c = 0,
+	.discharging_max_c = 60,
 };
 
 static const struct board_batt_params info[] = {
@@ -139,7 +139,7 @@ static int board_get_battery_type(void)
 	if (!battery_manufacturer_name(name, sizeof(name))) {
 		for (i = 0; i < BATTERY_TYPE_COUNT; i++) {
 			if (!strncasecmp(name, info[i].manuf_name,
-					 ARRAY_SIZE(name)-1)) {
+					 ARRAY_SIZE(name) - 1)) {
 				board_battery_type = i;
 				break;
 			}
@@ -168,7 +168,9 @@ DECLARE_HOOK(HOOK_INIT, board_init_battery_type, HOOK_PRIO_INIT_I2C + 1);
 const struct battery_info *battery_get_info(void)
 {
 	return info[board_battery_type == BATTERY_TYPE_COUNT ?
-		    DEFAULT_BATTERY_TYPE : board_battery_type].batt_info;
+			    DEFAULT_BATTERY_TYPE :
+			    board_battery_type]
+		.batt_info;
 }
 
 int board_cut_off_battery(void)
@@ -192,7 +194,7 @@ static int charger_should_discharge_on_ac(struct charge_state_data *curr)
 
 	/* Do not discharge on AC if the battery is still waking up */
 	if (!(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
-		!(curr->batt.status & STATUS_FULLY_CHARGED))
+	    !(curr->batt.status & STATUS_FULLY_CHARGED))
 		return 0;
 
 	/*
@@ -209,8 +211,8 @@ static int charger_should_discharge_on_ac(struct charge_state_data *curr)
 	 * and suspend USB charging and DC/DC converter.
 	 */
 	if (!battery_is_cut_off() &&
-		!(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
-		(curr->batt.status & STATUS_FULLY_CHARGED))
+	    !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
+	    (curr->batt.status & STATUS_FULLY_CHARGED))
 		return 1;
 
 	/*
@@ -275,8 +277,9 @@ static int battery_init(void)
 {
 	int batt_status;
 
-	return battery_status(&batt_status) ? 0 :
-		!!(batt_status & STATUS_INITIALIZED);
+	return battery_status(&batt_status) ?
+		       0 :
+		       !!(batt_status & STATUS_INITIALIZED);
 }
 
 /* Allow booting now that the battery has woke up */
@@ -305,8 +308,8 @@ static int battery_check_disconnect(void)
 	uint8_t data[6];
 
 	/* Check if battery discharging is disabled. */
-	rv = sb_read_mfgacc(PARAM_OPERATION_STATUS,
-			    SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data));
+	rv = sb_read_mfgacc(PARAM_OPERATION_STATUS, SB_ALT_MANUFACTURER_ACCESS,
+			    data, sizeof(data));
 	if (rv)
 		return BATTERY_DISCONNECT_ERROR;
 
@@ -384,14 +387,13 @@ static int board_battery_sb_write(uint8_t access, int cmd)
 	buf[1] = cmd & 0xff;
 	buf[2] = (cmd >> 8) & 0xff;
 
-	rv = i2c_xfer(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS,
-		      buf, 1 + sizeof(uint16_t), NULL, 0);
+	rv = i2c_xfer(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS, buf,
+		      1 + sizeof(uint16_t), NULL, 0);
 
 	return rv;
 }
 
-int board_battery_read_mfgacc(int offset, int access,
-				      uint8_t *buf, int len)
+int board_battery_read_mfgacc(int offset, int access, uint8_t *buf, int len)
 {
 	int rv;
 	uint8_t block_len, reg;
@@ -408,7 +410,7 @@ int board_battery_read_mfgacc(int offset, int access,
 
 	reg = access;
 	rv = i2c_xfer_unlocked(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS, &reg, 1,
-	    &block_len, 1, I2C_XFER_START);
+			       &block_len, 1, I2C_XFER_START);
 	if (rv) {
 		i2c_lock(I2C_PORT_BATTERY, 0);
 		return rv;
@@ -419,7 +421,7 @@ int board_battery_read_mfgacc(int offset, int access,
 		block_len = len;
 
 	rv = i2c_xfer_unlocked(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS, NULL, 0,
-	    buf, block_len, I2C_XFER_STOP);
+			       buf, block_len, I2C_XFER_STOP);
 	i2c_lock(I2C_PORT_BATTERY, 0);
 
 	return rv;
@@ -432,7 +434,8 @@ static int board_battery_unseal(uint32_t param)
 
 	/* Get Operation Status */
 	rv = board_battery_read_mfgacc(PARAM_OPERATION_STATUS,
-			    SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data));
+				       SB_ALT_MANUFACTURER_ACCESS, data,
+				       sizeof(data));
 
 	if (rv)
 		return EC_ERROR_UNKNOWN;
@@ -457,7 +460,8 @@ static int board_battery_unseal(uint32_t param)
 
 		/* Verify that battery is unsealed */
 		rv = board_battery_read_mfgacc(PARAM_OPERATION_STATUS,
-			    SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data));
+					       SB_ALT_MANUFACTURER_ACCESS, data,
+					       sizeof(data));
 		if (rv || ((data[3] & 0x3) != 0x2))
 			return EC_ERROR_UNKNOWN;
 	}
@@ -474,7 +478,7 @@ static int board_battery_seal(void)
 	int rv;
 
 	i2c_lock(I2C_PORT_BATTERY, 1);
-	rv = board_battery_sb_write(SB_MANUFACTURER_ACCESS,  0x0030);
+	rv = board_battery_sb_write(SB_MANUFACTURER_ACCESS, 0x0030);
 	i2c_lock(I2C_PORT_BATTERY, 0);
 
 	if (rv != EC_SUCCESS)
@@ -507,8 +511,7 @@ static int board_battery_write_flash(int addr, uint32_t data, int len)
 	len += 4;
 
 	i2c_lock(I2C_PORT_BATTERY, 1);
-	rv = i2c_xfer(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS, buf,
-		      len, NULL, 0);
+	rv = i2c_xfer(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS, buf, len, NULL, 0);
 	i2c_lock(I2C_PORT_BATTERY, 0);
 
 	return rv;
@@ -522,13 +525,13 @@ static int board_battery_read_flash(int block, int len, uint8_t *buf)
 
 	if (len > 4)
 		len = 4;
-	rv = board_battery_read_mfgacc(block,
-			    SB_ALT_MANUFACTURER_ACCESS, data, len + 2);
+	rv = board_battery_read_mfgacc(block, SB_ALT_MANUFACTURER_ACCESS, data,
+				       len + 2);
 	if (rv)
 		return EC_RES_ERROR;
 
 	for (i = 0; i < len; i++)
-		buf[i] = data[i+2];
+		buf[i] = data[i + 2];
 
 	return EC_SUCCESS;
 }
@@ -594,7 +597,7 @@ static int board_battery_fix_otd_recovery_temp(uint32_t value)
 					      (uint8_t *)&otd_recovery_temp))
 			otd_recovery_temp_reg = otd_recovery_temp;
 	} else {
-			otd_recovery_temp_reg = otd_recovery_temp;
+		otd_recovery_temp_reg = otd_recovery_temp;
 	}
 
 	if (board_battery_seal()) {
@@ -607,7 +610,7 @@ static int board_battery_fix_otd_recovery_temp(uint32_t value)
 	return EC_SUCCESS;
 }
 
-int battery_get_vendor_param(uint32_t param, uint32_t *value)
+__override int battery_get_vendor_param(uint32_t param, uint32_t *value)
 {
 	/*
 	 * These registers can't be read directly because the flash area
@@ -638,7 +641,7 @@ int battery_get_vendor_param(uint32_t param, uint32_t *value)
 	return EC_RES_ERROR;
 }
 
-int battery_set_vendor_param(uint32_t param, uint32_t value)
+__override int battery_set_vendor_param(uint32_t param, uint32_t value)
 {
 	switch (param) {
 	case SB_VENDOR_PARAM_CTO_DISABLE:
diff --git a/board/eve/board.c b/board/eve/board.c
index 095b19ef3a..3193451ad1 100644
--- a/board/eve/board.c
+++ b/board/eve/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,15 +6,15 @@
 /* Eve board-specific configuration */
 
 #include "acpi.h"
-#include "adc_chip.h"
 #include "bd99992gw.h"
 #include "board_config.h"
 #include "button.h"
 #include "charge_manager.h"
-#include "charge_state.h"
 #include "charge_ramp.h"
+#include "charge_state.h"
 #include "charger.h"
 #include "chipset.h"
+#include "compiler.h"
 #include "console.h"
 #include "device_event.h"
 #include "driver/accel_kionix.h"
@@ -26,19 +26,21 @@
 #include "driver/tcpm/tcpci.h"
 #include "driver/tcpm/tcpm.h"
 #include "driver/temp_sensor/bd99992gw.h"
+#include "espi.h"
 #include "extpower.h"
 #include "gesture.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "host_command.h"
 #include "i2c.h"
-#include "keyboard_scan.h"
 #include "keyboard_8042_sharedlib.h"
+#include "keyboard_scan.h"
 #include "lid_angle.h"
 #include "lid_switch.h"
 #include "math_util.h"
 #include "motion_lid.h"
 #include "motion_sense.h"
+#include "panic.h"
 #include "power.h"
 #include "power_button.h"
 #include "pwm.h"
@@ -56,10 +58,9 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 #include "util.h"
-#include "espi.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
@@ -86,7 +87,6 @@ static void tcpc_alert_event(enum gpio_signal signal)
 static void enable_input_devices(void);
 DECLARE_DEFERRED(enable_input_devices);
 
-#define LID_DEBOUNCE_US	(30 * MSEC)
 void tablet_mode_interrupt(enum gpio_signal signal)
 {
 	hook_call_deferred(&enable_input_devices_data, LID_DEBOUNCE_US);
@@ -120,7 +120,7 @@ static void anx74xx_c0_cable_det_handler(void)
 	 * and if in normal mode, then there is no need to trigger a tcpc reset.
 	 */
 	if (cable_det && !reset_n)
-		task_set_event(TASK_ID_PD_C0, PD_EVENT_TCPC_RESET, 0);
+		task_set_event(TASK_ID_PD_C0, PD_EVENT_TCPC_RESET);
 }
 DECLARE_DEFERRED(anx74xx_c0_cable_det_handler);
 
@@ -139,7 +139,7 @@ static void anx74xx_c1_cable_det_handler(void)
 	 * and if in normal mode, then there is no need to trigger a tcpc reset.
 	 */
 	if (cable_det && !reset_n)
-		task_set_event(TASK_ID_PD_C1, PD_EVENT_TCPC_RESET, 0);
+		task_set_event(TASK_ID_PD_C1, PD_EVENT_TCPC_RESET);
 }
 DECLARE_DEFERRED(anx74xx_c1_cable_det_handler);
 
@@ -155,10 +155,11 @@ void anx74xx_cable_det_interrupt(enum gpio_signal signal)
 }
 #endif
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /* Keyboard scan. Increase output_settle_us to 80us from default 50us. */
-struct keyboard_scan_config keyscan_config = {
+__override struct keyboard_scan_config keyscan_config = {
 	.output_settle_us = 80,
 	.debounce_down_us = 9 * MSEC,
 	.debounce_up_us = 30 * MSEC,
@@ -173,13 +174,13 @@ struct keyboard_scan_config keyscan_config = {
 
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT]     = { 5, 0, 10000 },
-	[PWM_CH_LED_L_RED]   = { 2, PWM_CONFIG_DSLEEP, 100 },
+	[PWM_CH_KBLIGHT] = { 5, 0, 10000 },
+	[PWM_CH_LED_L_RED] = { 2, PWM_CONFIG_DSLEEP, 100 },
 	[PWM_CH_LED_L_GREEN] = { 3, PWM_CONFIG_DSLEEP, 100 },
-	[PWM_CH_LED_L_BLUE]  = { 4, PWM_CONFIG_DSLEEP, 100 },
-	[PWM_CH_LED_R_RED]   = { 1, PWM_CONFIG_DSLEEP, 100 },
+	[PWM_CH_LED_L_BLUE] = { 4, PWM_CONFIG_DSLEEP, 100 },
+	[PWM_CH_LED_R_RED] = { 1, PWM_CONFIG_DSLEEP, 100 },
 	[PWM_CH_LED_R_GREEN] = { 0, PWM_CONFIG_DSLEEP, 100 },
-	[PWM_CH_LED_R_BLUE]  = { 6, PWM_CONFIG_DSLEEP, 100 },
+	[PWM_CH_LED_R_BLUE] = { 6, PWM_CONFIG_DSLEEP, 100 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
@@ -192,12 +193,32 @@ const enum gpio_signal hibernate_wake_pins[] = {
 const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 
 /* I2C port map */
-const struct i2c_port_t i2c_ports[]  = {
-	{"tcpc0",     I2C_PORT_TCPC0,    400, GPIO_I2C0_0_SCL, GPIO_I2C0_0_SDA},
-	{"tcpc1",     I2C_PORT_TCPC1,    400, GPIO_I2C0_1_SCL, GPIO_I2C0_1_SDA},
-	{"accelgyro", I2C_PORT_GYRO,     400, GPIO_I2C1_SCL,   GPIO_I2C1_SDA},
-	{"sensors",   I2C_PORT_LID_ACCEL, 400, GPIO_I2C2_SCL,  GPIO_I2C2_SDA},
-	{"batt",      I2C_PORT_BATTERY,  100, GPIO_I2C3_SCL,   GPIO_I2C3_SDA},
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_0_SCL,
+	  .sda = GPIO_I2C0_0_SDA },
+	{ .name = "tcpc1",
+	  .port = I2C_PORT_TCPC1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_1_SCL,
+	  .sda = GPIO_I2C0_1_SDA },
+	{ .name = "accelgyro",
+	  .port = I2C_PORT_GYRO,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "sensors",
+	  .port = I2C_PORT_LID_ACCEL,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "batt",
+	  .port = I2C_PORT_BATTERY,
+	  .kbps = 100,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -221,16 +242,22 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.driver = &anx74xx_tcpm_usb_mux_driver,
-		.hpd_update = &anx74xx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &anx74xx_tcpm_usb_mux_driver,
+				.hpd_update = &anx74xx_tcpc_update_hpd_status,
+			},
 	},
 	{
-		.usb_port = 1,
-		.driver = &anx74xx_tcpm_usb_mux_driver,
-		.hpd_update = &anx74xx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.driver = &anx74xx_tcpm_usb_mux_driver,
+				.hpd_update = &anx74xx_tcpc_update_hpd_status,
+			},
 	},
 };
 
@@ -331,7 +358,8 @@ void board_tcpc_init(void)
 	 * HPD pulse to enable video path
 	 */
 	for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		usb_mux_hpd_update(port, 0, 0);
+		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
 
 uint16_t tcpc_get_alert_status(void)
@@ -352,18 +380,18 @@ uint16_t tcpc_get_alert_status(void)
 }
 
 const struct temp_sensor_t temp_sensors[] = {
-	{"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0},
+	{ "Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0 },
 
 	/* These BD99992GW temp sensors are only readable in S0 */
-	{"Ambient", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM0},
-	{"Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM1},
-	{"DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM2},
-	{"eMMC", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM3},
-	{"Gyro", TEMP_SENSOR_TYPE_BOARD, bmi160_get_sensor_temp, BASE_GYRO},
+	{ "Ambient", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM0 },
+	{ "Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM1 },
+	{ "DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM2 },
+	{ "eMMC", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM3 },
+	{ "Gyro", TEMP_SENSOR_TYPE_BOARD, bmi160_get_sensor_temp, BASE_GYRO },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -379,8 +407,8 @@ static void board_report_pmic_fault(const char *str)
 	uint32_t info;
 
 	/* RESETIRQ1 -- Bit 4: VRFAULT */
-	if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x8, &vrfault)
-	    != EC_SUCCESS)
+	if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x8, &vrfault) !=
+	    EC_SUCCESS)
 		return;
 
 	if (!(vrfault & BIT(4)))
@@ -459,7 +487,7 @@ static void board_set_tablet_mode(void)
 {
 	int flipped_360_mode = !gpio_get_level(GPIO_TABLET_MODE_L);
 
-	tablet_set_mode(flipped_360_mode);
+	tablet_set_mode(flipped_360_mode, TABLET_TRIGGER_LID);
 
 	/* Update DPTF profile based on mode */
 	if (flipped_360_mode)
@@ -607,8 +635,8 @@ int board_set_active_charge_port(int charge_port)
  * @param charge_ma     Desired charge limit (mA).
  * @param charge_mv     Negotiated charge voltage (mV).
  */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
 {
 	/* Enable charging trigger by BC1.2 detection */
 	int bc12_enable = (supplier == CHARGE_SUPPLIER_BC12_CDP ||
@@ -619,9 +647,7 @@ void board_set_charge_limit(int port, int supplier, int charge_ma,
 	if (bd9995x_bc12_enable_charging(port, bc12_enable))
 		return;
 
-	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-				   CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+	charge_set_input_current_limit(charge_ma, charge_mv);
 }
 
 /**
@@ -683,15 +709,14 @@ static void enable_input_devices(void)
 }
 
 /* Enable or disable input devices, based on chipset state and tablet mode */
-#ifndef TEST_BUILD
-void lid_angle_peripheral_enable(int enable)
+__override void lid_angle_peripheral_enable(int enable)
 {
 	/*
 	 * If suspended and the lid is in 360 position, ignore the lid angle,
 	 * which might be faulty. Disable keyboard and trackpad wake.
 	 */
 	if (chipset_in_state(CHIPSET_STATE_ANY_OFF) ||
-	   (tablet_get_mode() && chipset_in_state(CHIPSET_STATE_SUSPEND)))
+	    (tablet_get_mode() && chipset_in_state(CHIPSET_STATE_SUSPEND)))
 		enable = 0;
 	keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
 
@@ -700,7 +725,6 @@ void lid_angle_peripheral_enable(int enable)
 		enable = 0;
 	trackpad_wake_enable(enable);
 }
-#endif
 
 /* Called on AP S5 -> S3 transition */
 static void board_chipset_startup(void)
@@ -824,35 +848,30 @@ static struct mutex g_lid_mutex;
 static struct kionix_accel_data g_kxcj9_data;
 static struct bmi_drv_data_t g_bmi160_data;
 
-static struct si114x_drv_data_t g_si114x_data = {
-	.state = SI114X_NOT_READY,
-	.covered = 0,
-	.type_data = {
-		/* Proximity - unused */
-		{
-		},
-		/* light */
-		{
-			.base_data_reg = SI114X_REG_ALSVIS_DATA0,
-			.irq_flags = SI114X_ALS_INT_FLAG,
-			.scale = 1,
-			.offset = -256,
-		}
-	}
-};
+static struct si114x_drv_data_t
+	g_si114x_data = { .state = SI114X_NOT_READY,
+			  .covered = 0,
+			  .type_data = {
+				  /* Proximity - unused */
+				  {},
+				  /* light */
+				  {
+					  .base_data_reg = SI114X_ALS_VIS_DATA0,
+					  .irq_flags =
+						  SI114X_IRQ_ENABLE_ALS_IE_INT0 |
+						  SI114X_IRQ_ENABLE_ALS_IE_INT1,
+					  .scale = 1,
+					  .offset = -256,
+				  } } };
 
 /* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t mag_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0,  FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t mag_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				      { 0, FLOAT_TO_FP(1), 0 },
+				      { 0, 0, FLOAT_TO_FP(-1) } };
 
-const mat33_fp_t lid_standard_ref = {
-	{FLOAT_TO_FP(-1),  0,  0},
-	{ 0,  FLOAT_TO_FP(-1), 0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				      { 0, FLOAT_TO_FP(-1), 0 },
+				      { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
@@ -947,7 +966,10 @@ struct motion_sensor_t motion_sensors[] = {
 	 .default_range = BIT(11), /* 16LSB / uT, fixed */
 	 .rot_standard_ref = &mag_standard_ref,
 	 .min_frequency = BMM150_MAG_MIN_FREQ,
+/* TODO(b/253292373): Remove when clang is fixed. */
+DISABLE_CLANG_WARNING("-Wshift-count-negative")
 	 .max_frequency = BMM150_MAG_MAX_FREQ(SPECIAL),
+ENABLE_CLANG_WARNING("-Wshift-count-negative")
 	},
 
 	[LID_LIGHT] = {
diff --git a/board/eve/board.h b/board/eve/board.h
index 1e0431d5cc..f72fd9b523 100644
--- a/board/eve/board.h
+++ b/board/eve/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,34 +12,32 @@
  * By default, enable all console messages excepted HC, ACPI and event:
  * The sensor stack is generating a lot of activity.
  */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
 #undef CONFIG_HOSTCMD_DEBUG_MODE
 #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
 
 /* EC */
 #define CONFIG_ADC
 #define CONFIG_BACKLIGHT_LID
-#define CONFIG_BOARD_VERSION_CUSTOM
 #define CONFIG_BOARD_FORCE_RESET_PIN
 #define CONFIG_DEVICE_EVENT
 #define CONFIG_DPTF
 #define CONFIG_DPTF_MULTI_PROFILE
-#define CONFIG_FLASH_SIZE 0x80000
+#define CONFIG_FLASH_SIZE_BYTES 0x80000
 #define CONFIG_FPU
 /* 7 day delay before hibernate */
-#undef  CONFIG_HIBERNATE_DELAY_SEC
+#undef CONFIG_HIBERNATE_DELAY_SEC
 #define CONFIG_HIBERNATE_DELAY_SEC (3600 * 24 * 7)
 /* 1 day delay before hibernate if battery is less than 10% */
 #define CONFIG_HIBERNATE_BATT_PCT 10
 #define CONFIG_HIBERNATE_BATT_SEC (3600 * 24)
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_CONTROLLER
 #define CONFIG_LED_COMMON
 #define CONFIG_LID_SWITCH
 #define CONFIG_LOW_POWER_IDLE
 #define CONFIG_LTO
 #define CONFIG_CHIP_PANIC_BACKUP
-#define CONFIG_SOFTWARE_PANIC
 #define CONFIG_PWM
 #define CONFIG_PWM_KBLIGHT
 #define CONFIG_SHA256_UNROLLED
@@ -56,7 +54,7 @@
 #define WIRELESS_GPIO_WLAN GPIO_WLAN_OFF_L
 #define WIRELESS_GPIO_WLAN_POWER GPIO_PP3300_DX_WLAN
 #undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 512
+#define CONFIG_UART_TX_BUF_SIZE 256
 
 /* EC console commands */
 #define CONFIG_CMD_ACCELS
@@ -65,16 +63,21 @@
 #define CONFIG_CMD_CHARGER_ADC_AMON_BMON
 #define CONFIG_HOSTCMD_PD_CONTROL
 
+/* EC console history configuration */
+#undef CONFIG_CONSOLE_HISTORY
+#define CONFIG_CONSOLE_HISTORY 1
+
 /* SOC */
 #define CONFIG_CHIPSET_SKYLAKE
 #define CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET
 #define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-#define CONFIG_KEYBOARD_BOARD_CONFIG
+#define CONFIG_HOST_INTERFACE_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
+#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD
+
 #define CONFIG_KEYBOARD_COL2_INVERTED
-#undef  CONFIG_KEYBOARD_VIVALDI
+#undef CONFIG_KEYBOARD_VIVALDI
 #define CONFIG_KEYBOARD_PROTOCOL_8042
 #define CONFIG_KEYBOARD_REFRESH_ROW3
 #define CONFIG_TABLET_MODE
@@ -83,7 +86,8 @@
 #define CONFIG_BATTERY_CRITICAL_SHUTDOWN_CUT_OFF
 #define CONFIG_BATTERY_CUT_OFF
 #define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
-#define CONFIG_BATTERY_LEVEL_NEAR_FULL 94
+#undef CONFIG_BATT_HOST_FULL_FACTOR
+#define CONFIG_BATT_HOST_FULL_FACTOR 94
 #define CONFIG_BATTERY_PRESENT_CUSTOM
 #define CONFIG_BATTERY_HW_PRESENT_CUSTOM
 #define CONFIG_BATTERY_SMART
@@ -97,20 +101,22 @@
 #define CONFIG_CHARGER_BD9995X
 #define CONFIG_CHARGER_BD9995X_CHGEN
 #define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT 512
+#define CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT 512
+#define CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT 512
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 5
 #define CONFIG_CHARGER_MAINTAIN_VBAT
-#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 2
 #define CONFIG_CHARGER_PROFILE_OVERRIDE
 #define CONFIG_CHARGER_PSYS_READ
 #define CONFIG_CHARGER_SENSE_RESISTOR 10
 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 #define BD9995X_IOUT_GAIN_SELECT \
-		BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V
+	BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V
 #define BD9995X_PSYS_GAIN_SELECT \
-		BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_02UAW
+	BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_02UAW
 #define CONFIG_EXTPOWER_GPIO
-#undef   CONFIG_EXTPOWER_DEBOUNCE_MS
-#define  CONFIG_EXTPOWER_DEBOUNCE_MS 1000
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
+#define CONFIG_EXTPOWER_DEBOUNCE_MS 1000
 #define CONFIG_POWER_BUTTON
 #define CONFIG_POWER_BUTTON_X86
 #define CONFIG_POWER_COMMON
@@ -132,11 +138,10 @@
 #define CONFIG_THERMISTOR_NCP15WB
 #define CONFIG_ACCELGYRO_BMI160
 #define CONFIG_MAG_BMI_BMM150
-#define CONFIG_ACCEL_INTERRUPTS
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 #define CONFIG_ACCELGYRO_SEC_ADDR_FLAGS BMM150_ADDR0_FLAGS
-#define CONFIG_ACCELGYRO_BMI160_INT2_OUTPUT  /* Unused */
+#define CONFIG_ACCELGYRO_BMI160_INT2_OUTPUT /* Unused */
 #define CONFIG_MAG_CALIBRATE
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_INVALID_CHECK
@@ -148,31 +153,34 @@
 /* Enable sensor fifo, must also define the _SIZE and _THRES */
 #define CONFIG_ACCEL_FIFO
 /* FIFO size is in power of 2. */
-#define CONFIG_ACCEL_FIFO_SIZE 512
+#define CONFIG_ACCEL_FIFO_SIZE 256
 /* Depends on how fast the AP boots and typical ODRs */
 #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
 
 /* Enable double tap detection */
 #define CONFIG_GESTURE_DETECTION
 #define CONFIG_GESTURE_HOST_DETECTION
-#define CONFIG_GESTURE_SENSOR_DOUBLE_TAP 1
+#define CONFIG_GESTURE_SENSOR_DOUBLE_TAP
 #define CONFIG_GESTURE_SAMPLING_INTERVAL_MS 5
 #define CONFIG_GESTURE_TAP_THRES_MG 100
 #define CONFIG_GESTURE_TAP_MAX_INTERSTICE_T 500
-#define CONFIG_GESTURE_DETECTION_MASK \
-	 BIT(CONFIG_GESTURE_SENSOR_DOUBLE_TAP)
+#define CONFIG_GESTURE_DETECTION_MASK BIT(CONFIG_GESTURE_TAP_SENSOR)
+#define CONFIG_GESTURE_TAP_SENSOR 1
 
 /* USB */
+#define CONFIG_USB_PID 0x504B
+
 #define CONFIG_USB_CHARGER
+#define CONFIG_USB_DRP_ACC_TRYSRC
 #define CONFIG_USB_PD_ALT_MODE
 #define CONFIG_USB_PD_ALT_MODE_DFP
 #define CONFIG_USB_PD_COMM_LOCKED
+#define CONFIG_USB_PD_DECODE_SOP
 #define CONFIG_USB_PD_DISCHARGE_TCPC
 #define CONFIG_USB_PD_DUAL_ROLE
 #define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
 #define CONFIG_BD9995X_DELAY_INPUT_PORT_SELECT
 #define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT TYPEC_RP_3A0
 #define CONFIG_USB_PD_PORT_MAX_COUNT 2
 #define CONFIG_USB_PD_VBUS_DETECT_CHARGER
 #define CONFIG_USB_PD_TCPC_BOARD_INIT
@@ -184,32 +192,32 @@
 #undef CONFIG_USB_PD_TRY_SRC_MIN_BATT_SOC
 #define CONFIG_USB_PD_TRY_SRC_MIN_BATT_SOC 2
 #define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV1
+#define CONFIG_USB_PD_TCPMV2
 #define CONFIG_USBC_SS_MUX
 #define CONFIG_USBC_VCONN
 #define CONFIG_USBC_VCONN_SWAP
 
 /* Optional feature to configure npcx chip */
-#define NPCX_UART_MODULE2	1 /* 1:GPIO64/65 as UART */
-#define NPCX_JTAG_MODULE2	0 /* 0:GPIO21/17/16/20 as JTAG */
-#define NPCX_TACH_SEL2		0 /* 0:GPIO40/73 as TACH */
+#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART */
+#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 as JTAG */
+#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 as TACH */
 
 /* I2C ports */
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT0_0
-#define I2C_PORT_TCPC1		NPCX_I2C_PORT0_1
-#define I2C_PORT_GYRO		NPCX_I2C_PORT1
-#define I2C_PORT_ACCEL		I2C_PORT_GYRO
-#define I2C_PORT_LID_ACCEL	NPCX_I2C_PORT2
-#define I2C_PORT_ALS		NPCX_I2C_PORT2
-#define I2C_PORT_PMIC		NPCX_I2C_PORT3
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT3
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT3
-#define I2C_PORT_THERMAL	I2C_PORT_PMIC
-#define I2C_PORT_MP2949		NPCX_I2C_PORT3
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0
+#define I2C_PORT_TCPC1 NPCX_I2C_PORT0_1
+#define I2C_PORT_GYRO NPCX_I2C_PORT1
+#define I2C_PORT_ACCEL I2C_PORT_GYRO
+#define I2C_PORT_LID_ACCEL NPCX_I2C_PORT2
+#define I2C_PORT_ALS NPCX_I2C_PORT2
+#define I2C_PORT_PMIC NPCX_I2C_PORT3
+#define I2C_PORT_BATTERY NPCX_I2C_PORT3
+#define I2C_PORT_CHARGER NPCX_I2C_PORT3
+#define I2C_PORT_THERMAL I2C_PORT_PMIC
+#define I2C_PORT_MP2949 NPCX_I2C_PORT3
 
 /* I2C addresses */
-#define I2C_ADDR_BD99992_FLAGS	0x30
-#define I2C_ADDR_MP2949_FLAGS	0x20
+#define I2C_ADDR_BD99992_FLAGS 0x30
+#define I2C_ADDR_MP2949_FLAGS 0x20
 
 #ifndef __ASSEMBLER__
 
@@ -229,11 +237,11 @@ enum board_version_list {
 };
 
 enum temp_sensor_id {
-	TEMP_SENSOR_BATTERY,	/* BD99956GW TSENSE */
-	TEMP_SENSOR_AMBIENT,	/* BD99992GW SYSTHERM0 */
-	TEMP_SENSOR_CHARGER,	/* BD99992GW SYSTHERM1 */
-	TEMP_SENSOR_DRAM,	/* BD99992GW SYSTHERM2 */
-	TEMP_SENSOR_EMMC,	/* BD99992GW SYSTHERM3 */
+	TEMP_SENSOR_BATTERY, /* BD99956GW TSENSE */
+	TEMP_SENSOR_AMBIENT, /* BD99992GW SYSTHERM0 */
+	TEMP_SENSOR_CHARGER, /* BD99992GW SYSTHERM1 */
+	TEMP_SENSOR_DRAM, /* BD99992GW SYSTHERM2 */
+	TEMP_SENSOR_EMMC, /* BD99992GW SYSTHERM3 */
 	TEMP_SENSOR_GYRO,
 	TEMP_SENSOR_COUNT
 };
@@ -277,25 +285,22 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum adc_channel {
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_CH_COUNT };
 
 /*
  * delay to turn on the power supply max is ~16ms.
  * delay to turn off the power supply max is about ~180ms.
  */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	250000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* delay to turn on/off vconn */
-#define PD_VCONN_SWAP_DELAY		5000   /* us */
 
 /* Define typical operating power and max power */
-#define PD_OPERATING_POWER_MW		15000
-#define PD_MAX_POWER_MW			45000
-#define PD_MAX_CURRENT_MA		3000
-#define PD_MAX_VOLTAGE_MV		20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 45000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Board specific handlers */
 int board_get_version(void);
diff --git a/board/eve/build.mk b/board/eve/build.mk
index f47b5d9caf..0913dd9370 100644
--- a/board/eve/build.mk
+++ b/board/eve/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/eve/ec.tasklist b/board/eve/ec.tasklist
index 99de365243..75e5f918c5 100644
--- a/board/eve/ec.tasklist
+++ b/board/eve/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/eve/gpio.inc b/board/eve/gpio.inc
index f9b0c3cfc4..6bf357f0c3 100644
--- a/board/eve/gpio.inc
+++ b/board/eve/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/eve/led.c b/board/eve/led.c
index 91a7b24a2b..df3f632cf1 100644
--- a/board/eve/led.c
+++ b/board/eve/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -13,14 +13,14 @@
 #include "gpio.h"
 #include "hooks.h"
 #include "led_common.h"
-#include "pwm.h"
 #include "math_util.h"
+#include "pwm.h"
 #include "registers.h"
 #include "task.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_PWM, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_PWM, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_PWM, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_PWM, format, ##args)
 
 #define LED_TICK_TIME (500 * MSEC)
 #define LED_TICKS_PER_BEAT 1
@@ -37,7 +37,9 @@
  * (120, .5, .33). For the transitions of interest only S and I are changed and
  * they are changed linearly in HSI space.
  */
-static const uint8_t trans_steps[] = {0, 4, 9, 16, 24, 33, 44, 56, 69, 84, 100};
+static const uint8_t trans_steps[] = {
+	0, 4, 9, 16, 24, 33, 44, 56, 69, 84, 100
+};
 
 /* List of LED colors used */
 enum led_color {
@@ -65,11 +67,7 @@ enum led_pattern {
 	LED_NUM_PATTERNS,
 };
 
-enum led_side {
-	LED_LEFT = 0,
-	LED_RIGHT,
-	LED_BOTH
-};
+enum led_side { LED_LEFT = 0, LED_RIGHT, LED_BOTH };
 
 struct led_info {
 	/* LED pattern manage variables */
@@ -101,8 +99,8 @@ static int double_tap;
 static int led_charge_side;
 static struct led_info led[LED_BOTH];
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_LEFT_LED, EC_LED_ID_RIGHT_LED};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_LEFT_LED,
+					     EC_LED_ID_RIGHT_LED };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 /*
@@ -110,16 +108,18 @@ const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
  * particular pattern never changes from the first phase.
  */
 static const struct led_phase pattern[LED_NUM_PATTERNS] = {
-	{ {LED_OFF, LED_OFF}, {0, 0}, DOUBLE_TAP_TICK_LEN },
-	{ {LED_GREEN, LED_GREEN}, {0, 0}, DOUBLE_TAP_TICK_LEN },
-	{ {LED_WHITE, LED_GREEN}, {2, 4}, DOUBLE_TAP_TICK_LEN },
-	{ {LED_WHITE, LED_WHITE}, {0, 0}, DOUBLE_TAP_TICK_LEN },
-	{ {LED_WHITE, LED_RED}, {2, 4}, DOUBLE_TAP_TICK_LEN },
-	{ {LED_RED, LED_RED}, {0, 0},  DOUBLE_TAP_TICK_LEN},
-	{ {LED_RED, LED_RED_HALF}, {4, 4}, DOUBLE_TAP_TICK_LEN * 2 +
-	  DOUBLE_TAP_TICK_LEN / 2},
-	{ {LED_RED, LED_OFF}, {1, 5}, DOUBLE_TAP_TICK_LEN * 3 +
-	  DOUBLE_TAP_TICK_LEN / 2},
+	{ { LED_OFF, LED_OFF }, { 0, 0 }, DOUBLE_TAP_TICK_LEN },
+	{ { LED_GREEN, LED_GREEN }, { 0, 0 }, DOUBLE_TAP_TICK_LEN },
+	{ { LED_WHITE, LED_GREEN }, { 2, 4 }, DOUBLE_TAP_TICK_LEN },
+	{ { LED_WHITE, LED_WHITE }, { 0, 0 }, DOUBLE_TAP_TICK_LEN },
+	{ { LED_WHITE, LED_RED }, { 2, 4 }, DOUBLE_TAP_TICK_LEN },
+	{ { LED_RED, LED_RED }, { 0, 0 }, DOUBLE_TAP_TICK_LEN },
+	{ { LED_RED, LED_RED_HALF },
+	  { 4, 4 },
+	  DOUBLE_TAP_TICK_LEN * 2 + DOUBLE_TAP_TICK_LEN / 2 },
+	{ { LED_RED, LED_OFF },
+	  { 1, 5 },
+	  DOUBLE_TAP_TICK_LEN * 3 + DOUBLE_TAP_TICK_LEN / 2 },
 };
 
 /*
@@ -129,12 +129,9 @@ static const struct led_phase pattern[LED_NUM_PATTERNS] = {
 #define PWM_CHAN_PER_LED 3
 static const uint8_t color_brightness[LED_COLOR_COUNT][PWM_CHAN_PER_LED] = {
 	/* {Red, Green, Blue}, */
-	[LED_OFF]   = {0, 0, 0},
-	[LED_RED]   = {80,  0, 0},
-	[LED_GREEN] = {0, 80, 0},
-	[LED_BLUE] = {0, 0, 80},
-	[LED_WHITE]  = {100, 100, 100},
-	[LED_RED_HALF]  = {40, 0, 0},
+	[LED_OFF] = { 0, 0, 0 },	 [LED_RED] = { 80, 0, 0 },
+	[LED_GREEN] = { 0, 80, 0 },	 [LED_BLUE] = { 0, 0, 80 },
+	[LED_WHITE] = { 100, 100, 100 }, [LED_RED_HALF] = { 40, 0, 0 },
 };
 
 /*
@@ -153,13 +150,13 @@ struct range_map {
 #error "LED: PULSE_RED battery level <= BLINK_RED level"
 #endif
 static const struct range_map pattern_tbl[] = {
-	{CONFIG_USB_PD_TRY_SRC_MIN_BATT_SOC - 1, BLINK_RED},
-	{5, PULSE_RED},
-	{15, SOLID_RED},
-	{25, WHITE_RED},
-	{75, SOLID_WHITE},
-	{95, WHITE_GREEN},
-	{100, SOLID_GREEN},
+	{ CONFIG_USB_PD_TRY_SRC_MIN_BATT_SOC - 1, BLINK_RED },
+	{ 5, PULSE_RED },
+	{ 15, SOLID_RED },
+	{ 25, WHITE_RED },
+	{ 75, SOLID_WHITE },
+	{ 95, WHITE_GREEN },
+	{ 100, SOLID_GREEN },
 };
 
 enum led_state_change {
@@ -323,18 +320,17 @@ static void led_setup_color_change(int old_idx, int new_idx, enum led_side side)
 		 */
 		total_change = ABS(led[side].rgb_current[rgb_index] -
 				   led[side].rgb_target[rgb_index]);
-		delta_per_step = (total_change << LED_FRAC_BITS)
-			/ (ARRAY_SIZE(trans_steps) - 1);
+		delta_per_step = (total_change << LED_FRAC_BITS) /
+				 (ARRAY_SIZE(trans_steps) - 1);
 		step_value = 0;
 		for (i = 0; i < ARRAY_SIZE(trans_steps); i++) {
-			led[side].trans[i] = start_lvl +
-				((step_value +
-				  (1 << (LED_FRAC_BITS - 1)))
-				 >> LED_FRAC_BITS);
+			led[side].trans[i] =
+				start_lvl +
+				((step_value + (1 << (LED_FRAC_BITS - 1))) >>
+				 LED_FRAC_BITS);
 			step_value += delta_per_step;
 		}
 	}
-
 }
 
 static void led_adjust_color_step(int side)
@@ -397,12 +393,10 @@ static void led_change_color(void)
 	/* Will loop here until the color change is complete. */
 	while (led[LED_LEFT].state != LED_STATE_DONE ||
 	       led[LED_RIGHT].state != LED_STATE_DONE) {
-
 		for (i = 0; i < LED_BOTH; i++) {
 			if (led[i].state != LED_STATE_DONE)
 				/* Move one step in the transition table */
 				led_adjust_color_step(i);
-
 		}
 		msleep(LED_STEP_MSEC);
 	}
@@ -427,14 +421,19 @@ static void led_manage_patterns(enum led_pattern *pattern_desired, int tap)
 			 */
 			if (i == led_charge_side || !led[i].tap_tick_count) {
 				led[i].ticks = 0;
-				led[i].tap_tick_count = tap ?
-					pattern[pattern_desired[i]].tap_len : 0;
+				led[i].tap_tick_count =
+					tap ? pattern[pattern_desired[i]]
+							.tap_len :
+					      0;
 				led[i].pattern_sel = pattern_desired[i];
 			}
 		}
 		/* Determine pattern phase and color for current phase */
 		phase = led[i].ticks < LED_TICKS_PER_BEAT *
-			pattern[led[i].pattern_sel].len[0] ? 0 : 1;
+						pattern[led[i].pattern_sel]
+							.len[0] ?
+				0 :
+				1;
 		color = pattern[led[i].pattern_sel].color[phase];
 		/* If color is changing, then setup the transition. */
 		if (led[i].color != color) {
@@ -458,9 +457,10 @@ static void led_manage_patterns(enum led_pattern *pattern_desired, int tap)
 		 * count.
 		 */
 		if (pattern[led[i].pattern_sel].len[0])
-			if (++led[i].ticks == LED_TICKS_PER_BEAT *
-			    (pattern[led[i].pattern_sel].len[0] +
-			     pattern[led[i].pattern_sel].len[1]))
+			if (++led[i].ticks ==
+			    LED_TICKS_PER_BEAT *
+				    (pattern[led[i].pattern_sel].len[0] +
+				     pattern[led[i].pattern_sel].len[1]))
 				led[i].ticks = 0;
 
 		/* If double tap display is active, decrement its counter */
@@ -486,7 +486,7 @@ static enum led_pattern led_get_double_tap_pattern(int percent_chg)
 
 static void led_select_pattern(enum led_pattern *pattern_desired, int tap)
 {
-	enum charge_state chg_state = charge_get_state();
+	enum led_pwr_state chg_state = led_pwr_get_state();
 	int side;
 	int percent_chg;
 	enum led_pattern new_pattern;
@@ -534,11 +534,11 @@ static void led_select_pattern(enum led_pattern *pattern_desired, int tap)
 		 * External charger is connected. First determine pattern for
 		 * charging side LED.
 		 */
-		if (chg_state == PWR_STATE_CHARGE_NEAR_FULL ||
-		    ((chg_state == PWR_STATE_DISCHARGE_FULL)
-		     && extpower_is_present())) {
+		if (chg_state == LED_PWRS_CHARGE_NEAR_FULL ||
+		    ((chg_state == LED_PWRS_DISCHARGE_FULL) &&
+		     extpower_is_present())) {
 			new_pattern = SOLID_GREEN;
-		} else if (chg_state == PWR_STATE_CHARGE) {
+		} else if (chg_state == LED_PWRS_CHARGE) {
 			new_pattern = SOLID_WHITE;
 		} else {
 			new_pattern = OFF;
@@ -586,7 +586,6 @@ static void led_init(void)
 		led[i].tap_tick_count = 0;
 		led[i].state = LED_STATE_DONE;
 	}
-
 }
 
 void led_task(void *u)
@@ -633,7 +632,7 @@ void led_task(void *u)
 
 /******************************************************************/
 /* Console commands */
-static int command_led(int argc, char **argv)
+static int command_led(int argc, const char **argv)
 {
 	int side = LED_BOTH;
 	char *e;
diff --git a/board/eve/usb_pd_policy.c b/board/eve/usb_pd_policy.c
index 4d10047d85..969876756e 100644
--- a/board/eve/usb_pd_policy.c
+++ b/board/eve/usb_pd_policy.c
@@ -1,16 +1,16 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "atomic.h"
-#include "extpower.h"
 #include "charge_manager.h"
 #include "common.h"
 #include "console.h"
 #include "driver/charger/bd9995x.h"
 #include "driver/tcpm/anx74xx.h"
 #include "driver/tcpm/ps8xxx.h"
+#include "extpower.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "host_command.h"
@@ -18,17 +18,17 @@
 #include "system.h"
 #include "task.h"
 #include "timer.h"
-#include "util.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
+#include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT];
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5,
-							TYPEC_RP_1A5};
+static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5,
+							 TYPEC_RP_1A5 };
 
 int board_vbus_source_enabled(int port)
 {
@@ -38,9 +38,9 @@ int board_vbus_source_enabled(int port)
 static void board_vbus_update_source_current(int port)
 {
 	enum gpio_signal gpio_5v_en = port ? GPIO_USB_C1_5V_EN :
-		GPIO_USB_C0_5V_EN;
+					     GPIO_USB_C0_5V_EN;
 	enum gpio_signal gpio_3a_en = port ? GPIO_EN_USB_C1_3A :
-		GPIO_EN_USB_C0_3A;
+					     GPIO_EN_USB_C0_3A;
 	int flags;
 
 	if (system_get_board_version() >= BOARD_VERSION_P1B) {
@@ -50,8 +50,8 @@ static void board_vbus_update_source_current(int port)
 		 * is controlled by GPIO_USB_C0/1_5V_EN. Both of these signals
 		 * can remain outputs.
 		 */
-		gpio_set_level(gpio_3a_en, vbus_rp[port] == TYPEC_RP_3A0 ?
-			       1 : 0);
+		gpio_set_level(gpio_3a_en,
+			       vbus_rp[port] == TYPEC_RP_3A0 ? 1 : 0);
 		gpio_set_level(gpio_5v_en, vbus_en[port]);
 	} else {
 		/*
@@ -65,8 +65,8 @@ static void board_vbus_update_source_current(int port)
 		 * 1505 mA.
 		 */
 		flags = (vbus_rp[port] == TYPEC_RP_1A5 && vbus_en[port]) ?
-			(GPIO_INPUT | GPIO_PULL_UP) :
-			(GPIO_OUTPUT | GPIO_PULL_UP);
+				(GPIO_INPUT | GPIO_PULL_UP) :
+				(GPIO_OUTPUT | GPIO_PULL_UP);
 		gpio_set_level(gpio_5v_en, vbus_en[port]);
 		gpio_set_flags(gpio_5v_en, flags);
 	}
@@ -85,9 +85,6 @@ int pd_set_power_supply_ready(int port)
 	/* Ensure we're not charging from this port */
 	bd9995x_select_input_port(port, 0);
 
-	/* Ensure we advertise the proper available current quota */
-	charge_manager_source_port(port, 1);
-
 	pd_set_vbus_discharge(port, 0);
 	/* Provide VBUS */
 	vbus_en[port] = 1;
@@ -113,9 +110,6 @@ void pd_power_supply_reset(int port)
 	if (prev_en)
 		pd_set_vbus_discharge(port, 1);
 
-	/* Give back the current quota we are no longer using */
-	charge_manager_source_port(port, 0);
-
 	/* notify host of power info change */
 	pd_send_host_event(PD_EVENT_POWER_CHANGE);
 }
@@ -126,15 +120,13 @@ int pd_check_vconn_swap(int port)
 	return gpio_get_level(GPIO_PMIC_SLP_SUS_L);
 }
 
-void pd_execute_data_swap(int port,
-			  enum pd_data_role data_role)
+void pd_execute_data_swap(int port, enum pd_data_role data_role)
 {
 	/* Only port 0 supports device mode. */
 	if (port != 0)
 		return;
 
-	gpio_set_level(GPIO_USB2_OTG_ID,
-		      (data_role == PD_ROLE_UFP) ? 1 : 0);
+	gpio_set_level(GPIO_USB2_OTG_ID, (data_role == PD_ROLE_UFP) ? 1 : 0);
 	gpio_set_level(GPIO_USB2_OTG_VBUSSENSE,
-		      (data_role == PD_ROLE_UFP) ? 1 : 0);
+		       (data_role == PD_ROLE_UFP) ? 1 : 0);
 }
diff --git a/board/eve/vif_override.xml b/board/eve/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/eve/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/ezkinil/battery.c b/board/ezkinil/battery.c
index 8c5ec9e1d7..1260b428ae 100644
--- a/board/ezkinil/battery.c
+++ b/board/ezkinil/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/ezkinil/board.c b/board/ezkinil/board.c
index 17134dd522..d2124188ce 100644
--- a/board/ezkinil/board.c
+++ b/board/ezkinil/board.c
@@ -1,17 +1,20 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "button.h"
-#include "charge_state_v2.h"
+#include "cbi_ssfc.h"
+#include "charge_state.h"
 #include "cros_board_info.h"
-#include "driver/accelgyro_bmi_common.h"
 #include "driver/accel_kionix.h"
 #include "driver/accel_kx022.h"
-#include "driver/ppc/aoz1380.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "driver/accelgyro_icm42607.h"
+#include "driver/accelgyro_icm426xx.h"
+#include "driver/accelgyro_icm_common.h"
+#include "driver/ppc/aoz1380_public.h"
 #include "driver/ppc/nx20p348x.h"
 #include "driver/retimer/pi3hdx1204.h"
 #include "driver/retimer/tusb544.h"
@@ -31,18 +34,34 @@
 #include "switch.h"
 #include "system.h"
 #include "task.h"
-#include "thermistor.h"
 #include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
 #include "usb_charge.h"
 #include "usb_mux.h"
 #include "usbc_ppc.h"
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
-#ifdef HAS_TASK_MOTIONSENSE
-
 static int board_ver;
 
+/*
+ * We have total 30 pins for keyboard connecter {-1, -1} mean
+ * the N/A pin that don't consider it and reserve index 0 area
+ * that we don't have pin 0.
+ */
+const int keyboard_factory_scan_pins[][2] = {
+	{ -1, -1 }, { 0, 5 },	{ 1, 1 }, { 1, 0 },   { 0, 6 },	  { 0, 7 },
+	{ -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 },   { -1, -1 }, { 1, 6 },
+	{ 1, 7 },   { 3, 1 },	{ 2, 0 }, { 1, 5 },   { 2, 6 },	  { 2, 7 },
+	{ 2, 1 },   { 2, 4 },	{ 2, 5 }, { 1, 2 },   { 2, 3 },	  { 2, 2 },
+	{ 3, 0 },   { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 },	  { -1, -1 },
+	{ -1, -1 },
+};
+
+const int keyboard_factory_scan_pins_used =
+	ARRAY_SIZE(keyboard_factory_scan_pins);
+
 /* Motion sensors */
 static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
@@ -50,18 +69,18 @@ static struct mutex g_base_mutex;
 /* sensor private data */
 static struct kionix_accel_data g_kx022_data;
 static struct bmi_drv_data_t g_bmi160_data;
+static struct icm_drv_data_t g_icm426xx_data;
 
 /* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(-1), 0,  0},
-	{ 0, 0,  FLOAT_TO_FP(-1)}
-};
-const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0,  0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+				       { FLOAT_TO_FP(-1), 0, 0 },
+				       { 0, 0, FLOAT_TO_FP(-1) } };
+const mat33_fp_t base_standard_ref_1 = { { FLOAT_TO_FP(1), 0, 0 },
+					 { 0, FLOAT_TO_FP(-1), 0 },
+					 { 0, 0, FLOAT_TO_FP(-1) } };
+const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				      { 0, FLOAT_TO_FP(-1), 0 },
+				      { 0, 0, FLOAT_TO_FP(1) } };
 
 /* TODO(gcc >= 5.0) Remove the casts to const pointer at rot_standard_ref */
 struct motion_sensor_t motion_sensors[] = {
@@ -104,7 +123,7 @@ struct motion_sensor_t motion_sensors[] = {
 	 .drv_data = &g_bmi160_data,
 	 .port = I2C_PORT_SENSOR,
 	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 2, /* g, enough for laptop */
+	 .default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
 	 .rot_standard_ref = &base_standard_ref,
 	 .min_frequency = BMI_ACCEL_MIN_FREQ,
 	 .max_frequency = BMI_ACCEL_MAX_FREQ,
@@ -141,7 +160,95 @@ struct motion_sensor_t motion_sensors[] = {
 
 unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
-#endif /* HAS_TASK_MOTIONSENSE */
+struct motion_sensor_t icm426xx_base_accel = {
+	.name = "Base Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
+	.rot_standard_ref = &base_standard_ref_1,
+	.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
+	.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100,
+		},
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	},
+};
+
+struct motion_sensor_t icm426xx_base_gyro = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &base_standard_ref_1,
+	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
+	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
+};
+
+struct motion_sensor_t icm42607_base_accel = {
+	.name = "Base Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM42607,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm42607_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
+	.default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
+	.rot_standard_ref = &base_standard_ref_1,
+	.min_frequency = ICM42607_ACCEL_MIN_FREQ,
+	.max_frequency = ICM42607_ACCEL_MAX_FREQ,
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100,
+		},
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	},
+};
+
+struct motion_sensor_t icm42607_base_gyro = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM42607,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm42607_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &base_standard_ref_1,
+	.min_frequency = ICM42607_GYRO_MIN_FREQ,
+	.max_frequency = ICM42607_GYRO_MAX_FREQ,
+};
 
 const struct power_signal_info power_signal_list[] = {
 	[X86_SLP_S3_N] = {
@@ -199,7 +306,7 @@ const int usb_port_enable[USBA_PORT_COUNT] = {
 const struct pi3hdx1204_tuning pi3hdx1204_tuning = {
 	.eq_ch0_ch1_offset = PI3HDX1204_EQ_DB710,
 	.eq_ch2_ch3_offset = PI3HDX1204_EQ_DB710,
-	.vod_offset = PI3HDX1204_VOD_115_ALL_CHANNELS,
+	.vod_offset = PI3HDX1204_VOD_130_ALL_CHANNELS,
 	.de_offset = PI3HDX1204_DE_DB_MINUS5,
 };
 
@@ -208,8 +315,12 @@ const struct pi3hdx1204_tuning pi3hdx1204_tuning = {
  * chip and it need a board specific driver.
  * Overall, it will use chained mux framework.
  */
-static int fsusb42umx_set_mux(const struct usb_mux *me, mux_state_t mux_state)
+static int fsusb42umx_set_mux(const struct usb_mux *me, mux_state_t mux_state,
+			      bool *ack_required)
 {
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
 	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
 		ioex_set_level(IOEX_USB_C0_SBU_FLIP, 1);
 	else
@@ -229,18 +340,80 @@ const struct usb_mux_driver usbc0_sbu_mux_driver = {
  * Since FSUSB42UMX is not a i2c device, .i2c_port and
  * .i2c_addr_flags are not required here.
  */
-const struct usb_mux usbc0_sbu_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &usbc0_sbu_mux_driver,
+const struct usb_mux_chain usbc0_sbu_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &usbc0_sbu_mux_driver,
+		},
 };
 
+/*****************************************************************************
+ * Base Gyro Sensor dynamic configuration
+ */
+
+static enum ec_ssfc_base_gyro_sensor base_gyro_config = SSFC_BASE_GYRO_NONE;
+
+static void setup_base_gyro_config(void)
+{
+	base_gyro_config = ec_config_has_base_gyro_sensor();
+
+	if (base_gyro_config == SSFC_BASE_GYRO_ICM426XX) {
+		motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
+		motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
+		ccprints("BASE GYRO is ICM426XX");
+	} else if (base_gyro_config == SSFC_BASE_GYRO_ICM42607) {
+		motion_sensors[BASE_ACCEL] = icm42607_base_accel;
+		motion_sensors[BASE_GYRO] = icm42607_base_gyro;
+		ccprints("BASE GYRO is ICM42607");
+	} else if (base_gyro_config == SSFC_BASE_GYRO_BMI160)
+		ccprints("BASE GYRO is BMI160");
+}
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	switch (base_gyro_config) {
+	case SSFC_BASE_GYRO_ICM426XX:
+		icm426xx_interrupt(signal);
+		break;
+	case SSFC_BASE_GYRO_ICM42607:
+		icm42607_interrupt(signal);
+		break;
+	case SSFC_BASE_GYRO_BMI160:
+	default:
+		bmi160_interrupt(signal);
+		break;
+	}
+}
+
 /*****************************************************************************
  * USB-C MUX/Retimer dynamic configuration
  */
 
+/* Place holder for second mux in USBC1 chain */
+struct usb_mux_chain usbc1_mux1;
+
+int board_usbc1_retimer_inhpd = IOEX_USB_C1_HPD_IN_DB;
+
 static void setup_mux(void)
 {
-	if (ec_config_has_usbc1_retimer_tusb544()) {
+	enum ec_ssfc_c1_mux mux = get_cbi_ssfc_c1_mux();
+
+	if (mux == SSFC_C1_MUX_NONE && ec_config_has_usbc1_retimer_tusb544())
+		mux = SSFC_C1_MUX_TUSB544;
+
+	if (mux == SSFC_C1_MUX_PS8818) {
+		ccprints("C1 PS8818 detected");
+		/*
+		 * Main MUX is FP5, secondary MUX is PS8818
+		 *
+		 * Replace usb_muxes[USBC_PORT_C1] with the AMD FP5
+		 * table entry.
+		 */
+		usb_muxes[USBC_PORT_C1].mux = &usbc1_amd_fp5_usb_mux;
+		/* Set the PS8818 as the secondary MUX */
+		usbc1_mux1.mux = &usbc1_ps8818;
+	} else if (mux == SSFC_C1_MUX_TUSB544) {
 		ccprints("C1 TUSB544 detected");
 		/*
 		 * Main MUX is FP5, secondary MUX is TUSB544
@@ -248,11 +421,9 @@ static void setup_mux(void)
 		 * Replace usb_muxes[USBC_PORT_C1] with the AMD FP5
 		 * table entry.
 		 */
-		memcpy(&usb_muxes[USBC_PORT_C1],
-		       &usbc1_amd_fp5_usb_mux,
-		       sizeof(struct usb_mux));
+		usb_muxes[USBC_PORT_C1].mux = &usbc1_amd_fp5_usb_mux;
 		/* Set the TUSB544 as the secondary MUX */
-		usb_muxes[USBC_PORT_C1].next_mux = &usbc1_tusb544;
+		usbc1_mux1.mux = &usbc1_tusb544;
 	} else if (ec_config_has_usbc1_retimer_ps8743()) {
 		ccprints("C1 PS8743 detected");
 		/*
@@ -261,32 +432,33 @@ static void setup_mux(void)
 		 * Replace usb_muxes[USBC_PORT_C1] with the PS8743
 		 * table entry.
 		 */
-		memcpy(&usb_muxes[USBC_PORT_C1],
-		       &usbc1_ps8743,
-		       sizeof(struct usb_mux));
+		usb_muxes[USBC_PORT_C1].mux = &usbc1_ps8743;
 		/* Set the AMD FP5 as the secondary MUX */
-		usb_muxes[USBC_PORT_C1].next_mux = &usbc1_amd_fp5_usb_mux;
+		usbc1_mux1.mux = &usbc1_amd_fp5_usb_mux;
 		/* Don't have the AMD FP5 flip */
 		usbc1_amd_fp5_usb_mux.flags = USB_MUX_FLAG_SET_WITHOUT_FLIP;
 	}
 }
 
-struct usb_mux usb_muxes[] = {
+struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.i2c_port = I2C_PORT_USB_AP_MUX,
-		.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
-		.driver = &amd_fp5_usb_mux_driver,
-		.next_mux = &usbc0_sbu_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.i2c_port = I2C_PORT_USB_AP_MUX,
+			.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
+			.driver = &amd_fp5_usb_mux_driver,
+		},
+		.next = &usbc0_sbu_mux,
 	},
 	[USBC_PORT_C1] = {
 		/* Filled in dynamically at startup */
+		.next = &usbc1_mux1,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
 
 static int board_tusb544_mux_set(const struct usb_mux *me,
-				mux_state_t mux_state)
+				 mux_state_t mux_state)
 {
 	if (mux_state & USB_PD_MUX_DP_ENABLED) {
 		/* Enable IN_HPD on the DB */
@@ -298,8 +470,7 @@ static int board_tusb544_mux_set(const struct usb_mux *me,
 	return EC_SUCCESS;
 }
 
-static int board_ps8743_mux_set(const struct usb_mux *me,
-				mux_state_t mux_state)
+static int board_ps8743_mux_set(const struct usb_mux *me, mux_state_t mux_state)
 {
 	if (mux_state & USB_PD_MUX_DP_ENABLED)
 		/* Enable IN_HPD on the DB */
@@ -367,15 +538,15 @@ __override void ppc_interrupt(enum gpio_signal signal)
 	}
 }
 
-__override int board_aoz1380_set_vbus_source_current_limit(int port,
-						enum tcpc_rp_value rp)
+__override int
+board_aoz1380_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp)
 {
 	int rv;
 
 	/* Use the TCPC to set the current limit */
-	rv = ioex_set_level(port ? IOEX_USB_C1_PPC_ILIM_3A_EN
-				: IOEX_USB_C0_PPC_ILIM_3A_EN,
-				(rp == TYPEC_RP_3A0) ? 1 : 0);
+	rv = ioex_set_level(port ? IOEX_USB_C1_PPC_ILIM_3A_EN :
+				   IOEX_USB_C0_PPC_ILIM_3A_EN,
+			    (rp == TYPEC_RP_3A0) ? 1 : 0);
 
 	return rv;
 }
@@ -420,6 +591,8 @@ static void setup_fw_config(void)
 		else
 			gpio_enable_interrupt(GPIO_DP1_HPD_EC_IN);
 	}
+
+	setup_base_gyro_config();
 }
 /* Use HOOK_PRIO_INIT_I2C + 2 to be after ioex_init(). */
 DECLARE_HOOK(HOOK_INIT, setup_fw_config, HOOK_PRIO_INIT_I2C + 2);
@@ -443,10 +616,9 @@ static void hdmi_hpd_handler(void)
 
 	gpio_set_level(GPIO_DP1_HPD, hpd);
 	ccprints("HDMI HPD %d", hpd);
-	pi3hdx1204_enable(I2C_PORT_TCPC1,
-			  PI3HDX1204_I2C_ADDR_FLAGS,
-			  chipset_in_or_transitioning_to_state(CHIPSET_STATE_ON)
-			  && hpd);
+	pi3hdx1204_enable(
+		I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS,
+		chipset_in_or_transitioning_to_state(CHIPSET_STATE_ON) && hpd);
 }
 DECLARE_DEFERRED(hdmi_hpd_handler);
 
@@ -474,8 +646,7 @@ static void board_chipset_resume(void)
 	if (ec_config_has_hdmi_retimer_pi3hdx1204()) {
 		ioex_set_level(IOEX_HDMI_POWER_EN_DB, 1);
 		msleep(PI3HDX1204_POWER_ON_DELAY_MS);
-		pi3hdx1204_enable(I2C_PORT_TCPC1,
-				  PI3HDX1204_I2C_ADDR_FLAGS,
+		pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS,
 				  check_hdmi_hpd_status());
 	}
 }
@@ -486,9 +657,7 @@ static void board_chipset_suspend(void)
 	ioex_set_level(IOEX_USB_A1_RETIMER_EN, 0);
 
 	if (ec_config_has_hdmi_retimer_pi3hdx1204()) {
-		pi3hdx1204_enable(I2C_PORT_TCPC1,
-				  PI3HDX1204_I2C_ADDR_FLAGS,
-				  0);
+		pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS, 0);
 		ioex_set_level(IOEX_HDMI_POWER_EN_DB, 0);
 	}
 
@@ -503,13 +672,13 @@ DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
 /* Physical fans. These are logically separate from pwm_channels. */
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = -1,
 };
 const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 2800,
-	.rpm_start = 2800,
+	.rpm_min = 3200,
+	.rpm_start = 3200,
 	.rpm_max = 6000,
 };
 const struct fan_t fans[] = {
@@ -591,41 +760,40 @@ const struct temp_sensor_t temp_sensors[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
-const static struct ec_thermal_config thermal_thermistor = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(85),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(95),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-	},
-	.temp_fan_off = 0,
-	.temp_fan_max = 0,
-};
-
-const static struct ec_thermal_config thermal_soc = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = 0,
-	.temp_fan_max = 0,
-};
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_THERMISTOR       \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(85), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(95), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
+		}, \
+		.temp_fan_off = 0, \
+		.temp_fan_max = 0, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_thermistor =
+	THERMAL_THERMISTOR;
 
-const static struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(85),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(95),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
-	},
-	.temp_fan_off = C_TO_K(37),
-	.temp_fan_max = C_TO_K(90),
-};
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_SOC              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+		}, \
+		.temp_fan_off = C_TO_K(32), \
+		.temp_fan_max = C_TO_K(75), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_soc = THERMAL_SOC;
 
 struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
 
@@ -637,14 +805,14 @@ struct fan_step {
 
 /* Note: Do not make the fan on/off point equal to 0 or 100 */
 static const struct fan_step fan_table0[] = {
-	{.on =  0, .off =  2, .rpm = 0},
-	{.on = 15, .off =  2, .rpm = 2800},
-	{.on = 23, .off = 13, .rpm = 3200},
-	{.on = 30, .off = 21, .rpm = 3400},
-	{.on = 38, .off = 28, .rpm = 3700},
-	{.on = 45, .off = 36, .rpm = 4200},
-	{.on = 55, .off = 43, .rpm = 4500},
-	{.on = 66, .off = 53, .rpm = 5300},
+	{ .on = 0, .off = 1, .rpm = 0 },
+	{ .on = 9, .off = 1, .rpm = 3200 },
+	{ .on = 21, .off = 7, .rpm = 3500 },
+	{ .on = 28, .off = 16, .rpm = 3900 },
+	{ .on = 37, .off = 26, .rpm = 4200 },
+	{ .on = 47, .off = 35, .rpm = 4600 },
+	{ .on = 56, .off = 44, .rpm = 5100 },
+	{ .on = 72, .off = 60, .rpm = 5500 },
 };
 /* All fan tables must have the same number of levels */
 #define NUM_FAN_LEVELS ARRAY_SIZE(fan_table0)
@@ -655,7 +823,6 @@ static void setup_fans(void)
 {
 	thermal_params[TEMP_SENSOR_CHARGER] = thermal_thermistor;
 	thermal_params[TEMP_SENSOR_SOC] = thermal_soc;
-	thermal_params[TEMP_SENSOR_CPU] = thermal_cpu;
 }
 DECLARE_HOOK(HOOK_INIT, setup_fans, HOOK_PRIO_DEFAULT);
 
@@ -691,8 +858,7 @@ int fan_percent_to_rpm(int fan, int pct)
 
 	previous_pct = pct;
 
-	if (fan_table[current_level].rpm !=
-		fan_get_rpm_target(FAN_CH(fan))) {
+	if (fan_table[current_level].rpm != fan_get_rpm_target(FAN_CH(fan))) {
 		cprints(CC_THERMAL, "Setting fan RPM to %d",
 			fan_table[current_level].rpm);
 		board_print_temps();
@@ -700,17 +866,3 @@ int fan_percent_to_rpm(int fan, int pct)
 
 	return fan_table[current_level].rpm;
 }
-
-__override void board_set_charge_limit(int port, int supplier, int charge_ma,
-			int max_ma, int charge_mv)
-{
-	/*
-	 * Limit the input current to 95% negotiated limit,
-	 * to account for the charger chip margin.
-	 */
-	charge_ma = charge_ma * 95 / 100;
-
-	charge_set_input_current_limit(MAX(charge_ma,
-				CONFIG_CHARGER_INPUT_CURRENT),
-				charge_mv);
-}
diff --git a/board/ezkinil/board.h b/board/ezkinil/board.h
index 17a924e99d..66c01a4efb 100644
--- a/board/ezkinil/board.h
+++ b/board/ezkinil/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,17 +8,28 @@
 
 #define VARIANT_ZORK_TREMBYLE
 
-#include <stdbool.h>
 #include "baseboard.h"
 
-#define CONFIG_MKBP_USE_GPIO
+#include <stdbool.h>
+
 #define CONFIG_FAN_RPM_CUSTOM
 
+#define CONFIG_KEYBOARD_FACTORY_TEST
+
+/* charger margin */
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 5
+
 /* Motion sensing drivers */
+#define CONFIG_ACCELGYRO_ICM426XX
+#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+#define CONFIG_ACCELGYRO_ICM42607
+#define CONFIG_ACCELGYRO_ICM42607_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 #define CONFIG_ACCELGYRO_BMI160
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCEL_INTERRUPTS
 #define CONFIG_ACCEL_KX022
 #define CONFIG_CMD_ACCELS
 #define CONFIG_CMD_ACCEL_INFO
@@ -34,38 +45,34 @@
 #define TUSB544_I2C_ADDR_FLAGS1 0x0F
 
 /* GPIO mapping from board specific name to EC common name. */
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_EC_BATT_PRES_ODL
-#define CONFIG_SCI_GPIO			GPIO_EC_FCH_SCI_ODL
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_AP_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT_L		GPIO_EC_EDP_BL_DISABLE
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_FCH_PWR_BTN_L
-#define GPIO_PCH_RSMRST_L		GPIO_EC_FCH_RSMRST_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S5_L		GPIO_SLP_S5_L
-#define GPIO_PCH_SYS_PWROK		GPIO_EC_FCH_PWROK
-#define GPIO_PCH_WAKE_L			GPIO_EC_FCH_WAKE_L
-#define GPIO_POWER_BUTTON_L		GPIO_EC_PWR_BTN_ODL
-#define GPIO_S0_PGOOD			GPIO_S0_PWROK_OD
-#define GPIO_S5_PGOOD			GPIO_EC_PWROK_OD
-#define GPIO_SYS_RESET_L		GPIO_EC_SYS_RST_L
-#define GPIO_VOLUME_DOWN_L		GPIO_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GPIO_DP1_HPD			GPIO_EC_DP1_HPD
-#define IOEX_HDMI_CONN_HPD_3V3_DB	IOEX_USB_C1_PPC_ILIM_3A_EN
+#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL
+#define CONFIG_SCI_GPIO GPIO_EC_FCH_SCI_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_AP_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_EDP_BL_DISABLE
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PCH_PWRBTN_L GPIO_EC_FCH_PWR_BTN_L
+#define GPIO_PCH_RSMRST_L GPIO_EC_FCH_RSMRST_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L
+#define GPIO_PCH_SYS_PWROK GPIO_EC_FCH_PWROK
+#define GPIO_PCH_WAKE_L GPIO_EC_FCH_WAKE_L
+#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL
+#define GPIO_S0_PGOOD GPIO_S0_PWROK_OD
+#define GPIO_S5_PGOOD GPIO_EC_PWROK_OD
+#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L
+#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
+#define GPIO_DP1_HPD GPIO_EC_DP1_HPD
+#define IOEX_HDMI_CONN_HPD_3V3_DB IOEX_USB_C1_PPC_ILIM_3A_EN
 
 #ifndef __ASSEMBLER__
 
-enum adc_channel {
-	ADC_TEMP_SENSOR_CHARGER,
-	ADC_TEMP_SENSOR_SOC,
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_TEMP_SENSOR_CHARGER, ADC_TEMP_SENSOR_SOC, ADC_CH_COUNT };
 
 enum battery_type {
 	BATTERY_AP19B8M,
@@ -79,11 +86,7 @@ enum mft_channel {
 	MFT_CH_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_FAN,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_FAN, PWM_CH_COUNT };
 
 enum temp_sensor_id {
 	TEMP_SENSOR_CHARGER = 0,
@@ -92,16 +95,11 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum usba_port {
-	USBA_PORT_A0 = 0,
-	USBA_PORT_A1,
-	USBA_PORT_COUNT
-};
+enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT };
 
 /*****************************************************************************
  * CBI EC FW Configuration
  */
-#include "cbi_ec_fw_config.h"
 
 /**
  * EZKINIL_MB_USBAC
@@ -146,63 +144,55 @@ enum ec_cfg_usb_db_type {
 	EZKINIL_DB_T_OPT2_USBAC = 1,
 };
 
+#include "cbi_ec_fw_config.h"
 
-#define HAS_USBA1_RETIMER_TUSB522 \
-			(BIT(EZKINIL_DB_T_OPT2_USBAC))
+#define HAS_USBA1_RETIMER_TUSB522 (BIT(EZKINIL_DB_T_OPT2_USBAC))
 
 static inline bool ec_config_has_usba1_retimer_tusb522(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_USBA1_RETIMER_TUSB522);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_USBA1_RETIMER_TUSB522);
 }
 
-#define HAS_USBC1_RETIMER_PS8743 \
-			(BIT(EZKINIL_DB_T_OPT2_USBAC))
+#define HAS_USBC1_RETIMER_PS8743 (BIT(EZKINIL_DB_T_OPT2_USBAC))
 
 static inline bool ec_config_has_usbc1_retimer_ps8743(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_USBC1_RETIMER_PS8743);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_USBC1_RETIMER_PS8743);
 }
 
-#define HAS_USBC1_RETIMER_TUSB544 \
-			(BIT(EZKINIL_DB_T_OPT1_USBC_HDMI))
+#define HAS_USBC1_RETIMER_TUSB544 (BIT(EZKINIL_DB_T_OPT1_USBC_HDMI))
 
 static inline bool ec_config_has_usbc1_retimer_tusb544(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_USBC1_RETIMER_TUSB544);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_USBC1_RETIMER_TUSB544);
 }
 
-#define HAS_HDMI_RETIMER_PI3HDX1204 \
-			(BIT(EZKINIL_DB_T_OPT1_USBC_HDMI))
+#define HAS_HDMI_RETIMER_PI3HDX1204 (BIT(EZKINIL_DB_T_OPT1_USBC_HDMI))
 
 static inline bool ec_config_has_hdmi_retimer_pi3hdx1204(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_HDMI_RETIMER_PI3HDX1204);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_HDMI_RETIMER_PI3HDX1204);
 }
 
-#define HAS_HDMI_CONN_HPD \
-			(BIT(EZKINIL_DB_T_OPT1_USBC_HDMI))
+#define HAS_HDMI_CONN_HPD (BIT(EZKINIL_DB_T_OPT1_USBC_HDMI))
 
 static inline bool ec_config_has_hdmi_conn_hpd(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_HDMI_CONN_HPD);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_HDMI_CONN_HPD);
 }
 
 /* TODO: Fill in with GPIO values */
-#define PORT_TO_HPD(port) ((port == 0) \
-	? GPIO_USB_C0_HPD \
-	: (ec_config_has_usbc1_retimer_ps8743()) \
-		? GPIO_DP1_HPD \
-		: GPIO_DP2_HPD)
+#define PORT_TO_HPD(port)                                           \
+	((port == 0)				? GPIO_USB_C0_HPD : \
+	 (ec_config_has_usbc1_retimer_ps8743()) ? GPIO_DP1_HPD :    \
+						  GPIO_DP2_HPD)
 
 extern const struct usb_mux usbc1_tusb544;
+extern const struct usb_mux usbc1_ps8818;
 extern const struct usb_mux usbc1_ps8743;
 extern struct usb_mux usbc1_amd_fp5_usb_mux;
 
+void motion_interrupt(enum gpio_signal signal);
 void hdmi_hpd_interrupt(enum gpio_signal signal);
 void hdmi_hpd_interrupt_v2(enum ioex_signal signal);
 
diff --git a/board/ezkinil/build.mk b/board/ezkinil/build.mk
index 1c0cbc4f63..45c71f962c 100644
--- a/board/ezkinil/build.mk
+++ b/board/ezkinil/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/ezkinil/ec.tasklist b/board/ezkinil/ec.tasklist
index d9c1606eb2..abc796f74f 100644
--- a/board/ezkinil/ec.tasklist
+++ b/board/ezkinil/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/ezkinil/gpio.inc b/board/ezkinil/gpio.inc
index 9a3b022db4..4ea6712424 100644
--- a/board/ezkinil/gpio.inc
+++ b/board/ezkinil/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,7 +24,7 @@ GPIO_INT(ACOK_OD,		PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	extpower_inter
 GPIO_INT(EC_WP_L,		PIN(5, 0), GPIO_INT_BOTH,			switch_interrupt)
 GPIO_INT(VOLDN_BTN_ODL,		PIN(A, 6), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
 GPIO_INT(VOLUP_BTN_ODL,		PIN(9, 5), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-GPIO_INT(6AXIS_INT_L,		PIN(A, 0), GPIO_INT_FALLING | GPIO_PULL_UP,	bmi160_interrupt)
+GPIO_INT(6AXIS_INT_L,		PIN(A, 0), GPIO_INT_FALLING | GPIO_PULL_UP,	motion_interrupt)
 GPIO_INT(DP1_HPD_EC_IN,		PIN(7, 5), GPIO_INT_BOTH,			hdmi_hpd_interrupt)
 
 /* GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an interrupt handler. */
diff --git a/board/ezkinil/led.c b/board/ezkinil/led.c
index a4eb63b13f..328b47a9e4 100644
--- a/board/ezkinil/led.c
+++ b/board/ezkinil/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,32 +8,41 @@
 #include "led_common.h"
 #include "led_onoff_states.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
-const int led_charge_lvl_1;
-const int led_charge_lvl_2 = 100;
+__override const int led_charge_lvl_1;
+__override const int led_charge_lvl_2 = 100;
 
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]       = {{EC_LED_COLOR_BLUE,  2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{LED_OFF,	     1 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-};
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_BLUE,
+					     2 * LED_ONE_SEC },
+					   { EC_LED_COLOR_AMBER,
+					     2 * LED_ONE_SEC } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { LED_OFF, 1 * LED_ONE_SEC },
+					  { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+	};
 BUILD_ASSERT(ARRAY_SIZE(led_bat_state_table) == LED_NUM_STATES);
 
 const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-void led_set_color_battery(enum ec_led_colors color)
+__override void led_set_color_battery(enum ec_led_colors color)
 {
 	switch (color) {
 	case EC_LED_COLOR_BLUE:
diff --git a/board/ezkinil/vif_override.xml b/board/ezkinil/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/ezkinil/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/felwinter/battery.c b/board/felwinter/battery.c
new file mode 100644
index 0000000000..257d7e8255
--- /dev/null
+++ b/board/felwinter/battery.c
@@ -0,0 +1,66 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "common.h"
+#include "compile_time_macros.h"
+
+/*
+ * Battery info for all Brya battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	[BATTERY_C536] = {
+		/* BQ40Z50 Fuel Gauge */
+		.fuel_gauge = {
+			.manuf_name = "AS3GXAE3jB",
+			.device_name = "C536-49",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr = 0x00,
+				.reg_mask = 0x2000,		/* XDSG */
+				.disconnect_val = 0x2000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13200,
+			.voltage_normal		= 11800, /* mV */
+			.voltage_min		= 9000, /* mV */
+			.precharge_current	= 256,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 45,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 60,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_C536;
diff --git a/board/felwinter/board.c b/board/felwinter/board.c
new file mode 100644
index 0000000000..630a8c331a
--- /dev/null
+++ b/board/felwinter/board.c
@@ -0,0 +1,169 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "button.h"
+#include "charge_ramp.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/accel_lis2dw12.h"
+#include "driver/accelgyro_lsm6dso.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "registers.h"
+#include "switch.h"
+#include "tablet_mode.h"
+#include "throttle_ap.h"
+#include "usbc_config.h"
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* Console output macros */
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+
+/******************************************************************************/
+/* USB-A charging control */
+
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_PP5000_USBA_R,
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
+
+/******************************************************************************/
+
+__override void board_cbi_init(void)
+{
+	config_usb_db_type();
+}
+
+/* Called on AP S3 -> S0 transition */
+static void board_chipset_resume(void)
+{
+	/* Allow keyboard backlight to be enabled */
+	gpio_set_level(GPIO_EC_KB_BL_EN_L, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S0 -> S3 transition */
+static void board_chipset_suspend(void)
+{
+	/* Turn off the keyboard backlight if it's on. */
+	gpio_set_level(GPIO_EC_KB_BL_EN_L, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S5 -> S3 transition */
+static void board_chipset_startup(void)
+{
+	pen_config();
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
+
+#ifdef CONFIG_CHARGE_RAMP_SW
+
+/*
+ * TODO(b/181508008): tune this threshold
+ */
+
+#define BC12_MIN_VOLTAGE 4400
+
+/**
+ * Return true if VBUS is too low
+ */
+int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
+{
+	int voltage;
+
+	if (charger_get_vbus_voltage(port, &voltage))
+		voltage = 0;
+
+	if (voltage == 0) {
+		CPRINTS("%s: must be disconnected", __func__);
+		return 1;
+	}
+
+	if (voltage < BC12_MIN_VOLTAGE) {
+		CPRINTS("%s: port %d: vbus %d lower than %d", __func__, port,
+			voltage, BC12_MIN_VOLTAGE);
+		return 1;
+	}
+
+	return 0;
+}
+
+#endif /* CONFIG_CHARGE_RAMP_SW */
+
+enum battery_present battery_hw_present(void)
+{
+	enum gpio_signal batt_pres;
+	batt_pres = GPIO_EC_BATT_PRES_ODL;
+
+	/* The GPIO is low when the battery is physically present */
+	return gpio_get_level(batt_pres) ? BP_NO : BP_YES;
+}
+
+static void board_init(void)
+{
+	if (ec_cfg_usb_db_type() == DB_USB4_NCT3807)
+		db_update_usb4_config_from_config();
+
+	if (ec_cfg_usb_mb_type() == MB_USB4_TBT)
+		mb_update_usb4_tbt_config_from_config();
+
+	if (ec_cfg_stylus() == STYLUS_PRSENT)
+		gpio_enable_interrupt(GPIO_PEN_DET_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+/**
+ * Deferred function to handle pen detect change
+ */
+static void pendetect_deferred(void)
+{
+	static int debounced_pen_detect;
+	int pen_detect = !gpio_get_level(GPIO_PEN_DET_ODL);
+
+	if (pen_detect == debounced_pen_detect)
+		return;
+
+	debounced_pen_detect = pen_detect;
+
+	if (!chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		gpio_set_level(GPIO_EN_PP5000_PEN, debounced_pen_detect);
+}
+DECLARE_DEFERRED(pendetect_deferred);
+DECLARE_HOOK(HOOK_INIT, pendetect_deferred, HOOK_PRIO_DEFAULT);
+
+void pen_detect_interrupt(enum gpio_signal s)
+{
+	/* Trigger deferred notification of pen detect change */
+	hook_call_deferred(&pendetect_deferred_data, 500 * MSEC);
+}
+
+void pen_config(void)
+{
+	if (ec_cfg_stylus() == STYLUS_PRSENT) {
+		/* Make sure pen detection is triggered or not at resume */
+		if (!gpio_get_level(GPIO_PEN_DET_ODL))
+			gpio_set_level(GPIO_EN_PP5000_PEN, 1);
+		else
+			gpio_set_level(GPIO_EN_PP5000_PEN, 0);
+	}
+}
+
+static void board_chipset_shutdown(void)
+{
+	gpio_set_level(GPIO_EN_PP5000_PEN, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
diff --git a/board/felwinter/board.h b/board/felwinter/board.h
new file mode 100644
index 0000000000..5327e8fec2
--- /dev/null
+++ b/board/felwinter/board.h
@@ -0,0 +1,229 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Brya board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "compile_time_macros.h"
+
+/* Baseboard features */
+#include "baseboard.h"
+
+/*
+ * This will happen automatically on NPCX9 ES2 and later. Do not remove
+ * until we can confirm all earlier chips are out of service.
+ */
+#define CONFIG_HIBERNATE_PSL_VCC1_RST_WAKEUP
+
+#define CONFIG_MP2964
+
+/* LED */
+#define CONFIG_LED_ONOFF_STATES
+#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
+#define GPIO_PWR_LED_WHITE_L GPIO_LED_1_L
+#define GPIO_BAT_LED_AMBER_L GPIO_LED_3_L
+#define GPIO_BAT_LED_WHITE_L GPIO_LED_4_L
+
+/* Sensors */
+#define CONFIG_ACCELGYRO_LSM6DSO /* Base accel */
+#define CONFIG_ACCEL_LSM6DSO_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+/* Enable sensor fifo, must also define the _SIZE and _THRES */
+#define CONFIG_ACCEL_FIFO
+/* FIFO size is in power of 2. */
+#define CONFIG_ACCEL_FIFO_SIZE 256
+/* Depends on how fast the AP boots and typical ODRs */
+#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
+
+/* Lid accel */
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_UPDATE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+#define CONFIG_ACCEL_LIS2DWL
+#define CONFIG_ACCEL_LIS2DW12_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
+
+/* Sensor console commands */
+#define CONFIG_CMD_ACCELS
+#define CONFIG_CMD_ACCEL_INFO
+
+/* USB Type A Features */
+#define USB_PORT_COUNT 1
+#define CONFIG_USB_PORT_POWER_DUMB
+
+/* USB Type C and USB PD defines */
+#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
+
+#define CONFIG_IO_EXPANDER
+#define CONFIG_IO_EXPANDER_NCT38XX
+#define CONFIG_IO_EXPANDER_PORT_COUNT 2
+
+#define CONFIG_USB_PD_TCPM_PS8815
+#define CONFIG_USBC_RETIMER_INTEL_BB
+
+/* I2C control host command */
+#define CONFIG_HOSTCMD_I2C_CONTROL
+
+/* Disable console commands to help save space */
+#undef CONFIG_CMD_POWERINDEBUG
+
+#define CONFIG_USBC_PPC_SYV682X
+#define CONFIG_USBC_PPC_NX20P3483
+
+/* TODO: b/177608416 - measure and check these values on brya */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
+
+/*
+ * Passive USB-C cables only support up to 60W.
+ */
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 65000
+#define PD_MAX_CURRENT_MA 3250
+#define PD_MAX_VOLTAGE_MV 20000
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
+
+/*
+ * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
+ * signal.
+ */
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
+
+/* System has back-lit keyboard */
+#define CONFIG_PWM_KBLIGHT
+
+/* I2C Bus Configuration */
+
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+
+#define I2C_PORT_USB_C2_TCPC NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1
+
+#define I2C_PORT_USB_C2_PPC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1
+
+#define I2C_PORT_USB_C2_BC12 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1
+
+#define I2C_PORT_USB_C2_MUX NPCX_I2C_PORT3_0
+#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1
+
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+
+#define I2C_ADDR_MP2964_FLAGS 0x20
+
+/*
+ *
+ */
+#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x56
+#define USBC_PORT_C2_BB_RETIMER_I2C_ADDR 0x58
+
+/* Enabling Thunderbolt-compatible mode */
+#define CONFIG_USB_PD_TBT_COMPAT_MODE
+
+/* Enabling USB4 mode */
+#define CONFIG_USB_PD_USB4
+
+/* Retimer */
+#define CONFIG_USBC_RETIMER_FW_UPDATE
+
+/* Thermal features */
+#define CONFIG_THERMISTOR
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_TEMP_SENSOR_POWER
+#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
+
+#define CONFIG_FANS FAN_CH_COUNT
+
+/* Charger defines */
+#define CONFIG_CHARGER_ISL9241
+#define CONFIG_CHARGE_RAMP_SW
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 10
+
+#define CONFIG_KEYBOARD_REFRESH_ROW3
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h" /* needed by registers.h */
+#include "registers.h"
+#include "usbc_config.h"
+
+enum adc_channel {
+	ADC_TEMP_SENSOR_1_DDR_SOC,
+	ADC_TEMP_SENSOR_2_FAN,
+	ADC_TEMP_SENSOR_3_CHARGER,
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1_DDR_SOC,
+	TEMP_SENSOR_2_FAN,
+	TEMP_SENSOR_3_CHARGER,
+	TEMP_SENSOR_COUNT
+};
+
+enum sensor_id { LID_ACCEL = 0, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
+
+enum ioex_port { IOEX_C2_NCT38XX = 0, IOEX_C1_NCT38XX, IOEX_PORT_COUNT };
+
+enum battery_type { BATTERY_C536, BATTERY_TYPE_COUNT };
+
+enum pwm_channel {
+	PWM_CH_KBLIGHT = 0, /* PWM3 */
+	PWM_CH_FAN, /* PWM5 */
+	PWM_CH_COUNT
+};
+
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT };
+
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT };
+
+void pen_detect_interrupt(enum gpio_signal s);
+
+void pen_config(void);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/felwinter/build.mk b/board/felwinter/build.mk
new file mode 100644
index 0000000000..848c76f457
--- /dev/null
+++ b/board/felwinter/build.mk
@@ -0,0 +1,25 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Brya board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx9
+CHIP_VARIANT:=npcx9m3f
+BASEBOARD:=brya
+
+board-y=
+board-y+=battery.o
+board-y+=board.o
+board-y+=charger_isl9241.o
+board-y+=fans.o
+board-y+=fw_config.o
+board-y+=i2c.o
+board-y+=keyboard.o
+board-y+=led.o
+board-y+=pwm.o
+board-y+=sensors.o
+board-y+=usbc_config.o
diff --git a/board/felwinter/charger_isl9241.c b/board/felwinter/charger_isl9241.c
new file mode 100644
index 0000000000..b86d92965b
--- /dev/null
+++ b/board/felwinter/charger_isl9241.c
@@ -0,0 +1,80 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/charger/isl9241.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/* Charger Chip Configuration */
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = ISL9241_ADDR_FLAGS,
+		.drv = &isl9241_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CHARGER_NUM);
+
+int board_set_active_charge_port(int port)
+{
+	int is_valid_port = board_is_usb_pd_port_present(port);
+	int i;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTSUSB("Disabling all charger ports");
+
+		/* Disable all ports. */
+		for (i = 0; i < ppc_cnt; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (ppc_vbus_sink_enable(i, 0))
+				CPRINTSUSB("Disabling C%d as sink failed.", i);
+		}
+
+		return EC_SUCCESS;
+	} else if (!is_valid_port) {
+		return EC_ERROR_INVAL;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (ppc_is_sourcing_vbus(port)) {
+		CPRINTFUSB("Skip enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTSUSB("New charge port: C%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < ppc_cnt; i++) {
+		if (i == port)
+			continue;
+
+		if (ppc_vbus_sink_enable(i, 0))
+			CPRINTSUSB("C%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTSUSB("C%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/board/felwinter/ec.tasklist b/board/felwinter/ec.tasklist
new file mode 100644
index 0000000000..29fd0bf4cb
--- /dev/null
+++ b/board/felwinter/ec.tasklist
@@ -0,0 +1,30 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ *
+ * USB_CHG_Px tasks must be contiguous (see USB_CHG_PORT_TO_TASK_ID(x)).
+ * PD_Cx tasks must be contiguous (see PD_PORT_TO_TASK_ID(x))
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, HOOKS_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, BASEBOARD_CHG_RAMP_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, BASEBOARD_CHARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, BASEBOARD_CHIPSET_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, CONSOLE_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, BASEBOARD_POWERBTN_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, BASEBOARD_PD_INT_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, BASEBOARD_PD_INT_TASK_STACK_SIZE)
diff --git a/board/felwinter/fans.c b/board/felwinter/fans.c
new file mode 100644
index 0000000000..891e8288a9
--- /dev/null
+++ b/board/felwinter/fans.c
@@ -0,0 +1,82 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Physical fans. These are logically separate from pwm_channels. */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "fan.h"
+#include "fan_chip.h"
+#include "hooks.h"
+#include "pwm.h"
+
+/* MFT channels. These are logically separate from pwm_channels. */
+const struct mft_t mft_channels[] = {
+	[MFT_CH_0] = {
+		.module = NPCX_MFT_MODULE_1,
+		.clk_src = TCKC_LFCLK,
+		.pwm_id = PWM_CH_FAN,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
+
+static const struct fan_conf fan_conf_0 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
+	.pgood_gpio = -1,
+	.enable_gpio = GPIO_EN_PP5000_FAN,
+};
+
+static const struct fan_rpm fan_rpm_0 = {
+	.rpm_min = 1100,
+	.rpm_start = 2000,
+	.rpm_max = 5000,
+};
+
+const struct fan_t fans[FAN_CH_COUNT] = {
+	[FAN_CH_0] = {
+		.conf = &fan_conf_0,
+		.rpm = &fan_rpm_0,
+	},
+};
+
+#ifndef CONFIG_FANS
+
+/*
+ * TODO(b/181271666): use static fan speeds until fan and sensors are
+ * tuned. for now, use:
+ *
+ *   AP off:  33%
+ *   AP  on: 100%
+ */
+
+static void fan_slow(void)
+{
+	const int duty_pct = 33;
+
+	ccprints("%s: speed %d%%", __func__, duty_pct);
+
+	pwm_enable(PWM_CH_FAN, 1);
+	pwm_set_duty(PWM_CH_FAN, duty_pct);
+}
+
+static void fan_max(void)
+{
+	const int duty_pct = 100;
+
+	ccprints("%s: speed %d%%", __func__, duty_pct);
+
+	pwm_enable(PWM_CH_FAN, 1);
+	pwm_set_duty(PWM_CH_FAN, duty_pct);
+}
+
+DECLARE_HOOK(HOOK_INIT, fan_slow, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, fan_slow, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, fan_slow, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_RESET, fan_max, HOOK_PRIO_FIRST);
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, fan_max, HOOK_PRIO_DEFAULT);
+
+#endif /* CONFIG_FANS */
diff --git a/board/felwinter/fw_config.c b/board/felwinter/fw_config.c
new file mode 100644
index 0000000000..0a4905bc9d
--- /dev/null
+++ b/board/felwinter/fw_config.c
@@ -0,0 +1,55 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "fw_config.h"
+
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
+
+static union brya_cbi_fw_config fw_config;
+BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
+
+/*
+ * FW_CONFIG defaults for brya if the CBI.FW_CONFIG data is not
+ * initialized.
+ */
+static const union brya_cbi_fw_config fw_config_defaults = {
+	.usb_db = DB_USB3_PS8815,
+	.kb_bl = KEYBOARD_BACKLIGHT_ENABLED,
+};
+
+/****************************************************************************
+ * Brya FW_CONFIG access
+ */
+void board_init_fw_config(void)
+{
+	if (cbi_get_fw_config(&fw_config.raw_value)) {
+		CPRINTS("CBI: Read FW_CONFIG failed, using board defaults");
+		fw_config = fw_config_defaults;
+	}
+}
+
+union brya_cbi_fw_config get_fw_config(void)
+{
+	return fw_config;
+}
+
+enum ec_cfg_usb_db_type ec_cfg_usb_db_type(void)
+{
+	return fw_config.usb_db;
+}
+
+enum ec_cfg_usb_mb_type ec_cfg_usb_mb_type(void)
+{
+	return fw_config.usb_mb;
+}
+
+enum ec_cfg_stylus_type ec_cfg_stylus(void)
+{
+	return fw_config.stylus;
+}
diff --git a/board/felwinter/fw_config.h b/board/felwinter/fw_config.h
new file mode 100644
index 0000000000..2a8a175efd
--- /dev/null
+++ b/board/felwinter/fw_config.h
@@ -0,0 +1,71 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __BOARD_BRYA_FW_CONFIG_H_
+#define __BOARD_BRYA_FW_CONFIG_H_
+
+#include <stdint.h>
+
+/****************************************************************************
+ * CBI FW_CONFIG layout for felwinter board.
+ *
+ * Source of truth is the project/brya/felwinter/config.star configuration file.
+ */
+
+enum ec_cfg_usb_db_type { DB_USB3_PS8815 = 1, DB_USB4_NCT3807 = 2 };
+
+enum ec_cfg_keyboard_backlight_type {
+	KEYBOARD_BACKLIGHT_DISABLED = 0,
+	KEYBOARD_BACKLIGHT_ENABLED = 1
+};
+
+enum ec_cfg_usb_mb_type { MB_USB4_TBT = 0, MB_USB3_NON_TBT = 1 };
+
+enum ec_cfg_stylus_type { STYLUS_ABSENT = 0, STYLUS_PRSENT = 1 };
+
+union brya_cbi_fw_config {
+	struct {
+		enum ec_cfg_usb_db_type usb_db : 3;
+		uint32_t wifi : 2;
+		enum ec_cfg_stylus_type stylus : 1;
+		enum ec_cfg_keyboard_backlight_type kb_bl : 1;
+		uint32_t audio : 3;
+		uint32_t thermal : 2;
+		uint32_t table_mode : 1;
+		enum ec_cfg_usb_mb_type usb_mb : 3;
+		uint32_t reserved_1 : 16;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Read the cached FW_CONFIG.  Guaranteed to have valid values.
+ *
+ * @return the FW_CONFIG for the board.
+ */
+union brya_cbi_fw_config get_fw_config(void);
+
+/**
+ * Get the USB daughter board type from FW_CONFIG.
+ *
+ * @return the USB daughter board type.
+ */
+enum ec_cfg_usb_db_type ec_cfg_usb_db_type(void);
+
+/**
+ * Get the USB main board type from FW_CONFIG.
+ *
+ * @return the USB main board type.
+ */
+enum ec_cfg_usb_mb_type ec_cfg_usb_mb_type(void);
+
+#endif /* __BOARD_BRYA_FW_CONFIG_H_ */
+
+/**
+ * Get the stylus type from FW_CONFIG.
+ *
+ * @return the stylus type.
+ */
+enum ec_cfg_stylus_type ec_cfg_stylus(void);
diff --git a/board/felwinter/gpio.inc b/board/felwinter/gpio.inc
new file mode 100644
index 0000000000..df992a18eb
--- /dev/null
+++ b/board/felwinter/gpio.inc
@@ -0,0 +1,154 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define MODULE_KB		MODULE_KEYBOARD_SCAN
+
+/* INTERRUPT GPIOs: */
+GPIO_INT(ACOK_OD,                        PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
+GPIO_INT(EC_ACCEL_INT_R_L,               PIN(8, 1), GPIO_SEL_1P8V | GPIO_INT_FALLING, lis2dw12_interrupt)
+GPIO_INT(EC_IMU_INT_R_L,                 PIN(5, 6), GPIO_SEL_1P8V | GPIO_INT_FALLING, lsm6dso_interrupt)
+GPIO_INT(EC_PROCHOT_IN_L,                PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
+GPIO_INT(EC_VOLDN_BTN_ODL,               PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(EC_VOLUP_BTN_ODL,               PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(EC_WP_ODL,                      PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(GSC_EC_PWR_BTN_ODL,             PIN(0, 1), GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW, power_button_interrupt)
+GPIO_INT(LID_OPEN,                       PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
+GPIO_INT(SEQ_EC_ALL_SYS_PG,              PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_DSW_PWROK,               PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_RSMRST_ODL,              PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,                       PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,                      PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SYS_SLP_S0IX_L,                 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(TABLET_MODE_L,                  PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
+GPIO_INT(USB_C2_TCPC_INT_ODL,            PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C1_BC12_INT_ODL,            PIN(5, 0), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C1_PPC_INT_ODL,             PIN(F, 5), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C1_TCPC_INT_ODL,            PIN(A, 2), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C2_BC12_INT_ODL,            PIN(8, 3), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C2_PPC_INT_ODL,             PIN(7, 0), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C2_RT_INT_ODL,              PIN(4, 1), GPIO_INT_FALLING, retimer_interrupt)
+GPIO_INT(PEN_DET_ODL,                    PIN(D, 4), GPIO_INT_BOTH, pen_detect_interrupt)
+
+/* USED GPIOs: */
+GPIO(CCD_MODE_ODL,                   PIN(E, 5), GPIO_INPUT)
+GPIO(CHARGER_VAP_OTG_EN,             PIN(7, 3), GPIO_OUT_LOW)
+GPIO(CPU_C10_GATE_L,                 PIN(6, 7), GPIO_INPUT)
+GPIO(EC_BATT_PRES_ODL,               PIN(A, 3), GPIO_INPUT)
+GPIO(EC_ENTERING_RW,                 PIN(0, 3), GPIO_OUT_LOW)
+GPIO(EC_EN_EDP_BL,                   PIN(D, 3), GPIO_OUT_HIGH)
+GPIO(EC_GSC_PACKET_MODE,             PIN(7, 5), GPIO_OUT_LOW)
+GPIO(EC_I2C_BAT_SCL,                 PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_BAT_SDA,                 PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SCL_R,              PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SDA_R,              PIN(B, 2), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,              PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SENSOR_SDA,              PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_USB_C0_C2_PPC_BC_SCL,    PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_PPC_BC_SDA,    PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_RT_SCL,        PIN(D, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_RT_SDA,        PIN(D, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_TCPC_SCL,      PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_TCPC_SDA,      PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_MIX_SCL,          PIN(E, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_MIX_SDA,          PIN(E, 3), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_TCPC_SCL,         PIN(F, 3), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_TCPC_SDA,         PIN(F, 2), GPIO_INPUT)
+GPIO(EC_KB_BL_EN_L,                  PIN(8, 6), GPIO_OUT_HIGH)
+GPIO(EC_PCHHOT_ODL,                  PIN(7, 4), GPIO_INPUT)
+GPIO(EC_PCH_INT_ODL,                 PIN(B, 0), GPIO_ODR_HIGH)
+GPIO(EC_PCH_PWR_BTN_ODL,             PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(EC_PCH_RSMRST_L,                PIN(A, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_RTCRST,                  PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_SYS_PWROK,               PIN(3, 7), GPIO_OUT_LOW)
+GPIO(EC_PCH_WAKE_R_ODL,              PIN(C, 0), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_ODL,                 PIN(6, 3), GPIO_ODR_HIGH)
+GPIO(EN_PP5000_FAN,                  PIN(6, 1), GPIO_OUT_HIGH)
+GPIO(EN_PP5000_USBA_R,               PIN(D, 7), GPIO_OUT_LOW)
+GPIO(EN_PP5000_PEN,                  PIN(E, 1), GPIO_OUT_LOW)
+GPIO(EN_S5_RAILS,                    PIN(B, 6), GPIO_OUT_LOW)
+GPIO(IMVP9_VRRDY_OD,                 PIN(4, 3), GPIO_INPUT)
+GPIO(PCH_PWROK,                      PIN(7, 2), GPIO_OUT_LOW)
+GPIO(SYS_RST_ODL,                    PIN(C, 5), GPIO_ODR_HIGH)
+GPIO(USB_C0_C2_TCPC_RST_ODL,         PIN(A, 7), GPIO_ODR_LOW)
+GPIO(USB_C1_FRS_EN,                  PIN(9, 4), GPIO_OUT_LOW)
+GPIO(USB_C1_RST_ODL,                 PIN(9, 6), GPIO_ODR_LOW)
+GPIO(USB_C1_RT_INT_ODL,              PIN(A, 0), GPIO_INPUT)
+GPIO(USB_C1_RT_RST_R_ODL,            PIN(0, 2), GPIO_ODR_LOW)
+GPIO(VCCST_PWRGD_OD,                 PIN(A, 4), GPIO_ODR_LOW)
+
+/* LED */
+GPIO(LED_4_L,                        PIN(6, 0), GPIO_OUT_HIGH) /* battery led white */
+GPIO(LED_3_L,                        PIN(C, 2), GPIO_OUT_HIGH) /* battery led amber */
+GPIO(LED_1_L,                        PIN(C, 4), GPIO_OUT_HIGH) /* power led white */
+
+/* UART alternate functions */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)              /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */
+
+/* I2C alternate functions */
+ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)               /* GPIO33/I2C5_SCL0/CTS_L, GPIO36/RTS_L/I2C5_SDA0 */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)               /* GPIO87/I2C1_SDA0 */
+ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)               /* GPIO92/I2C2_SCL0, GPIO91/I2C2_SDA0, GPIO90/I2C1_SCL0 */
+ALTERNATE(PIN_MASK(B, 0x0c), 0, MODULE_I2C, 0)               /* GPIOB3/I2C7_SCL0/DCD_L, GPIOB2/I2C7_SDA0/DSR_L */
+ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, GPIO_SEL_1P8V)   /* GPIOB5/I2C0_SCL0, GPIOB4/I2C0_SDA0 */
+ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)               /* GPIOD1/I2C3_SCL0, GPIOD0/I2C3_SDA0 */
+ALTERNATE(PIN_MASK(E, 0x18), 0, MODULE_I2C, 0)               /* GPIOE4/I2C6_SCL1/I3C_SCL, GPIOE3/I2C6_SDA1/I3C_SDA */
+ALTERNATE(PIN_MASK(F, 0x0c), 0, MODULE_I2C, 0)               /* GPIOF3/I2C4_SCL1, GPIOF2/I2C4_SDA1 */
+
+/* PWM alternate functions */
+ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0)               /* GPIO40/TA1 */
+ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)               /* GPIO80/PWM3 */
+ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)               /* GPIOB7/PWM5 */
+
+/* ADC alternate functions */
+ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0)               /* GPIO34/PS2_DAT2/ADC6 */
+ALTERNATE(PIN_MASK(4, 0x34), 0, MODULE_ADC, 0)               /* GPIO42/ADC3/RI_L, GPIO45/ADC0, GPIO44/ADC1 */
+
+/* KB alternate functions */
+ALTERNATE(PIN_MASK(0, 0xf0), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO10&P80_CLK/GPIO07, KSO11&P80_DAT/GPIO06, KSO12/GPIO05, KSO13/GPIO04 */
+ALTERNATE(PIN_MASK(1, 0x7f), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO06/GPO13/GP_SEL_L, KSO07/GPO12/JEN_L, KSO03/GPIO16/JTAG_TDO0_SWO, KSO04/GPIO15/XNOR, KSO05/GPIO14, KSO08/GPIO11/CR_SOUT1, KSO09/GPIO10/CR_SIN1 */
+ALTERNATE(PIN_MASK(2, 0xfc), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI2/GPIO27/TRACEDATA1, KSI3/GPIO26/TRACEDATA0, KSI4/GPIO25/TRACECLK/GP_SCLK, KSI5/GPIO24/GP_MISO, KSI6/GPIO23/S_SBUB, KSI7/GPIO22/S_SBUA */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO00/GPIO21/JTAG_TCK_SWCLK, KSO01/GPIO20/JTAG_TMS_SWIO */
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI0/GPIO31/TRACEDATA3/GP_MOSI, KSI1/GPIO30/TRACEDATA2/GP_CS_L */
+ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO14/GPIO82 */
+
+/* PMU alternate functions */
+ALTERNATE(PIN_MASK(0, 0x01), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN2_L&GPI00/GPIO00 */
+ALTERNATE(PIN_MASK(0, 0x02), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW) /* GPIO01/PSL_IN3_L&GPI01 */
+ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN1_L&GPID2/GPIOD2 */
+
+/* Unused Pins */
+UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
+UNUSED(PIN(3, 2))       /* GPO32/TRIS_L */
+UNUSED(PIN(3, 5))       /* GPO35/CR_SOUT4/TEST_L */
+UNUSED(PIN(6, 6))       /* GPIO66 */
+UNUSED(PIN(C, 3))       /* GPIOC3 */
+UNUSED(PIN(C, 6))       /* GPIOC6 */
+UNUSED(PIN(6, 2))       /* GPIO62 */
+UNUSED(PIN(B, 1))       /* GPIOB1 */
+UNUSED(PIN(5, 7))       /* GPIO57/SER_IRQ/ESPI_ALERT_L */
+
+/* Pre-configured PSL balls:  J8  K6 */
+
+
+/*
+ * The NPCX keyboard driver does not use named GPIOs to access
+ * keyboard scan pins, so we do not list them in *gpio.inc. However, when
+ * KEYBOARD_COL2_INVERTED is defined, this name is required.
+ */
+GPIO(EC_KSO_02_INV,               PIN(1, 7), GPIO_OUT_LOW)
+
+/* GPIO02_P2 to PU */
+/* GPIO03_P2 to PU */
+
+IOEX(USB_C1_RT_RST_ODL,      EXPIN(IOEX_C1_NCT38XX, 0, 2), GPIO_ODR_LOW)
+IOEX(USB_C1_OC_ODL,          EXPIN(IOEX_C1_NCT38XX, 0, 4), GPIO_ODR_HIGH)
+IOEX(USB_C1_FRS_EN,          EXPIN(IOEX_C1_NCT38XX, 0, 6), GPIO_LOW)
+
+IOEX(USB_C2_RT_RST_ODL,      EXPIN(IOEX_C2_NCT38XX, 0, 7), GPIO_ODR_LOW)
+IOEX(USB_C2_OC_ODL,          EXPIN(IOEX_C2_NCT38XX, 0, 4), GPIO_ODR_HIGH)
+IOEX(USB_C2_FRS_EN,          EXPIN(IOEX_C2_NCT38XX, 0, 6), GPIO_LOW)
+/* GPIO07_P2 to PU */
diff --git a/board/felwinter/i2c.c b/board/felwinter/i2c.c
new file mode 100644
index 0000000000..81f461a5ba
--- /dev/null
+++ b/board/felwinter/i2c.c
@@ -0,0 +1,78 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "i2c.h"
+
+/* I2C port map configuration */
+const struct i2c_port_t i2c_ports[] = {
+	{
+		/* I2C0 */
+		.name = "sensor",
+		.port = I2C_PORT_SENSOR,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_SENSOR_SCL,
+		.sda = GPIO_EC_I2C_SENSOR_SDA,
+	},
+	{
+		/* I2C1 */
+		.name = "tcpc2",
+		.port = I2C_PORT_USB_C2_TCPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C2_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C2_TCPC_SDA,
+	},
+	{
+		/* I2C2 */
+		.name = "ppc2",
+		.port = I2C_PORT_USB_C2_PPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C2_PPC_BC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C2_PPC_BC_SDA,
+	},
+	{
+		/* I2C3 */
+		.name = "retimer2",
+		.port = I2C_PORT_USB_C2_MUX,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C2_RT_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C2_RT_SDA,
+	},
+	{
+		/* I2C4 C1 TCPC */
+		.name = "tcpc1",
+		.port = I2C_PORT_USB_C1_TCPC,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_USB_C1_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C1_TCPC_SDA,
+		.flags = I2C_PORT_FLAG_DYNAMIC_SPEED,
+	},
+	{
+		/* I2C5 */
+		.name = "battery",
+		.port = I2C_PORT_BATTERY,
+		.kbps = 100,
+		.scl = GPIO_EC_I2C_BAT_SCL,
+		.sda = GPIO_EC_I2C_BAT_SDA,
+	},
+	{
+		/* I2C6 */
+		.name = "ppc1",
+		.port = I2C_PORT_USB_C1_PPC,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_USB_C1_MIX_SCL,
+		.sda = GPIO_EC_I2C_USB_C1_MIX_SDA,
+	},
+	{
+		/* I2C7 */
+		.name = "eeprom",
+		.port = I2C_PORT_EEPROM,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_MISC_SCL_R,
+		.sda = GPIO_EC_I2C_MISC_SDA_R,
+	},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/board/felwinter/keyboard.c b/board/felwinter/keyboard.c
new file mode 100644
index 0000000000..cee23af8c3
--- /dev/null
+++ b/board/felwinter/keyboard.c
@@ -0,0 +1,48 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "ec_commands.h"
+#include "keyboard_scan.h"
+#include "timer.h"
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/* Increase from 50 us, because KSO_02 passes through the H1. */
+	.output_settle_us = 80,
+	/* Other values should be the same as the default configuration. */
+	.debounce_down_us = 9 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x1c, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
+		0xa4, 0xff, 0xfe, 0x55, 0xfe, 0xff, 0xff, 0xff,  /* full set */
+	},
+};
+
+static const struct ec_response_keybd_config felwinter_kb = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY | KEYBD_CAP_NUMERIC_KEYPAD,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &felwinter_kb;
+}
diff --git a/board/felwinter/led.c b/board/felwinter/led.c
new file mode 100644
index 0000000000..2770e7fae8
--- /dev/null
+++ b/board/felwinter/led.c
@@ -0,0 +1,126 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power and battery LED control for felwinter
+ */
+
+#include "chipset.h"
+#include "gpio.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+#include "system.h"
+
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
+
+__override const int led_charge_lvl_1;
+__override const int led_charge_lvl_2 = 95;
+
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+	};
+
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    1 * LED_ONE_SEC },
+						  { LED_OFF,
+						    3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_BATTERY_LED,
+	EC_LED_ID_POWER_LED,
+};
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_power(enum ec_led_colors color)
+{
+	if (color == EC_LED_COLOR_WHITE)
+		gpio_set_level(GPIO_PWR_LED_WHITE_L, LED_ON_LVL);
+	else
+		/* LED_OFF and unsupported colors */
+		gpio_set_level(GPIO_PWR_LED_WHITE_L, LED_OFF_LVL);
+}
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_WHITE:
+		gpio_set_level(GPIO_BAT_LED_WHITE_L, LED_ON_LVL);
+		gpio_set_level(GPIO_BAT_LED_AMBER_L, LED_OFF_LVL);
+		break;
+	case EC_LED_COLOR_AMBER:
+		gpio_set_level(GPIO_BAT_LED_WHITE_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_BAT_LED_AMBER_L, LED_ON_LVL);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		gpio_set_level(GPIO_BAT_LED_WHITE_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_BAT_LED_AMBER_L, LED_OFF_LVL);
+		break;
+	}
+}
+
+__override enum led_states board_led_get_state(enum led_states desired_state)
+{
+	if (desired_state == STATE_BATTERY_ERROR) {
+		if (chipset_in_state(CHIPSET_STATE_ON))
+			return desired_state;
+		else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
+			return STATE_DISCHARGE_S3;
+		else
+			return STATE_DISCHARGE_S5;
+	}
+	return desired_state;
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_battery(EC_LED_COLOR_WHITE);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(EC_LED_COLOR_AMBER);
+		else
+			led_set_color_battery(LED_OFF);
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_power(EC_LED_COLOR_WHITE);
+		else
+			led_set_color_power(LED_OFF);
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/board/felwinter/pwm.c b/board/felwinter/pwm.c
new file mode 100644
index 0000000000..5023f429cc
--- /dev/null
+++ b/board/felwinter/pwm.c
@@ -0,0 +1,37 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "hooks.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_KBLIGHT] = {
+		.channel = 3,
+		.flags = 0,
+		/*
+		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
+		 * flicker. Higher frequencies consume similar average power to
+		 * lower PWM frequencies, but higher frequencies record a much
+		 * lower maximum power.
+		 */
+		.freq = 2400,
+	},
+	[PWM_CH_FAN] = {
+		.channel = 5,
+		.flags = PWM_CONFIG_OPEN_DRAIN,
+		.freq = 25000,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+static void board_pwm_init(void)
+{
+	pwm_enable(PWM_CH_KBLIGHT, 1);
+	pwm_set_duty(PWM_CH_KBLIGHT, 0);
+}
+DECLARE_HOOK(HOOK_INIT, board_pwm_init, HOOK_PRIO_DEFAULT);
diff --git a/board/felwinter/sensors.c b/board/felwinter/sensors.c
new file mode 100644
index 0000000000..4016b12514
--- /dev/null
+++ b/board/felwinter/sensors.c
@@ -0,0 +1,235 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "accelgyro.h"
+#include "adc_chip.h"
+#include "common.h"
+#include "driver/accel_lis2dw12.h"
+#include "driver/accelgyro_lsm6dso.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "motion_sense.h"
+#include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
+#include "thermal.h"
+
+/* ADC configuration */
+const struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_1_DDR_SOC] = {
+		.name = "TEMP_DDR_SOC",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_2_FAN] = {
+		.name = "TEMP_FAN",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_3_CHARGER] = {
+		.name = "TEMP_CHARGER",
+		.input_ch = NPCX_ADC_CH6,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+K_MUTEX_DEFINE(g_lid_accel_mutex);
+K_MUTEX_DEFINE(g_base_accel_mutex);
+static struct stprivate_data g_lis2dw12_data;
+static struct lsm6dso_data lsm6dso_data;
+
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(1), 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
+
+/* TODO(b/184779743): verify orientation matrix */
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, FLOAT_TO_FP(-1), 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
+
+struct motion_sensor_t motion_sensors[] = {
+	[LID_ACCEL] = {
+		.name = "Lid Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LIS2DW12,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &lis2dw12_drv,
+		.mutex = &g_lid_accel_mutex,
+		.drv_data = &g_lis2dw12_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LIS2DW12_ADDR0,
+		.rot_standard_ref = &lid_standard_ref, /* identity matrix */
+		.default_range = 2, /* g */
+		.min_frequency = LIS2DW12_ODR_MIN_VAL,
+		.max_frequency = LIS2DW12_ODR_MAX_VAL,
+		.config = {
+			/* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 12500 | ROUND_UP_FLAG,
+			},
+			/* Sensor on for lid angle detection */
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+		},
+	},
+
+	[BASE_ACCEL] = {
+		.name = "Base Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LSM6DSO,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &lsm6dso_drv,
+		.mutex = &g_base_accel_mutex,
+		.drv_data = LSM6DSO_ST_DATA(lsm6dso_data,
+				MOTIONSENSE_TYPE_ACCEL),
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LSM6DSO_ADDR0_FLAGS,
+		.rot_standard_ref = &base_standard_ref,
+		.default_range = 4,  /* g */
+		.min_frequency = LSM6DSO_ODR_MIN_VAL,
+		.max_frequency = LSM6DSO_ODR_MAX_VAL,
+		.config = {
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 13000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+		},
+	},
+
+	[BASE_GYRO] = {
+		.name = "Base Gyro",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LSM6DSO,
+		.type = MOTIONSENSE_TYPE_GYRO,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &lsm6dso_drv,
+		.mutex = &g_base_accel_mutex,
+		.drv_data = LSM6DSO_ST_DATA(lsm6dso_data,
+				MOTIONSENSE_TYPE_GYRO),
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LSM6DSO_ADDR0_FLAGS,
+		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = LSM6DSO_ODR_MIN_VAL,
+		.max_frequency = LSM6DSO_ODR_MAX_VAL,
+	},
+};
+const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+static void baseboard_sensors_init(void)
+{
+	/* Enable gpio interrupt for lid accel sensor */
+	gpio_enable_interrupt(GPIO_EC_ACCEL_INT_R_L);
+	/* Enable gpio interrupt for base accelgyro sensor */
+	gpio_enable_interrupt(GPIO_EC_IMU_INT_R_L);
+}
+DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_INIT_I2C + 1);
+
+/* Temperature sensor configuration */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1_DDR_SOC] = { .name = "DDR and SOC",
+				    .type = TEMP_SENSOR_TYPE_BOARD,
+				    .read = get_temp_3v3_30k9_47k_4050b,
+				    .idx = ADC_TEMP_SENSOR_1_DDR_SOC },
+	[TEMP_SENSOR_2_FAN] = { .name = "FAN",
+				.type = TEMP_SENSOR_TYPE_BOARD,
+				.read = get_temp_3v3_30k9_47k_4050b,
+				.idx = ADC_TEMP_SENSOR_2_FAN },
+	[TEMP_SENSOR_3_CHARGER] = { .name = "Charger",
+				    .type = TEMP_SENSOR_TYPE_BOARD,
+				    .read = get_temp_3v3_30k9_47k_4050b,
+				    .idx = ADC_TEMP_SENSOR_3_CHARGER },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/*
+ * TODO(b/180681346): update for Alder Lake/brya
+ *
+ * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
+ * 130 C.  However, sensor is located next to DDR, so we need to use the lower
+ * DDR temperature limit (85 C)
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(60), \
+		}, \
+		.temp_fan_off = C_TO_K(30), \
+		.temp_fan_max = C_TO_K(73), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
+
+/*
+ * TODO(b/180681346): update for Alder Lake/brya
+ *
+ * Inductor limits - used for both charger and PP3300 regulator
+ *
+ * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
+ *
+ * Charger max recommended temperature 100C, max absolute temperature 125C
+ * PP3300 regulator: operating range -40 C to 145 C
+ *
+ * Inductors: limit of 125c
+ * PCB: limit is 80c
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_FAN              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(60), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(70), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(50), \
+		}, \
+		.temp_fan_off = C_TO_K(30), \
+		.temp_fan_max = C_TO_K(63), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_fan = THERMAL_FAN;
+
+#define THERMAL_CHARGER          \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(60), \
+		}, \
+		.temp_fan_off = C_TO_K(30), \
+		.temp_fan_max = C_TO_K(73), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_charger =
+	THERMAL_CHARGER;
+
+/* this should really be "const" */
+struct ec_thermal_config thermal_params[] = {
+	[TEMP_SENSOR_1_DDR_SOC] = THERMAL_CPU,
+	[TEMP_SENSOR_2_FAN] = THERMAL_FAN,
+	[TEMP_SENSOR_3_CHARGER] = THERMAL_CHARGER,
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
diff --git a/board/felwinter/usbc_config.c b/board/felwinter/usbc_config.c
new file mode 100644
index 0000000000..1c93f822c6
--- /dev/null
+++ b/board/felwinter/usbc_config.c
@@ -0,0 +1,438 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/bc12/pi3usb9201_public.h"
+#include "driver/ppc/nx20p348x.h"
+#include "driver/ppc/syv682x_public.h"
+#include "driver/retimer/bb_retimer_public.h"
+#include "driver/tcpm/nct38xx.h"
+#include "driver/tcpm/ps8xxx_public.h"
+#include "driver/tcpm/tcpci.h"
+#include "ec_commands.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "ioexpander.h"
+#include "system.h"
+#include "task.h"
+#include "task_id.h"
+#include "timer.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+/* USBC TCPC configuration */
+struct tcpc_config_t tcpc_config[] = {
+	[USBC_PORT_C2] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C2_TCPC,
+			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_NO_DEBUG_ACC_CONTROL,
+	},
+	[USBC_PORT_C1] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C1_TCPC,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
+			 TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V |
+			 TCPC_FLAGS_CONTROL_VCONN,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
+BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
+
+struct tcpc_config_t tcpc_config_c1 = {
+	.bus_type = EC_BUS_TYPE_I2C,
+	.i2c_info = {
+		.port = I2C_PORT_USB_C1_TCPC,
+		.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+	},
+	.drv = &nct38xx_tcpm_drv,
+	.flags = TCPC_FLAGS_TCPCI_REV2_0 |
+		TCPC_FLAGS_NO_DEBUG_ACC_CONTROL,
+};
+
+/* USBC PPC configuration */
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C2] = {
+		.i2c_port = I2C_PORT_USB_C2_PPC,
+		.i2c_addr_flags = SYV682X_ADDR2_FLAGS,
+		.drv = &syv682x_drv,
+	},
+	[USBC_PORT_C1] = {
+		/* Compatible with Silicon Mitus SM536A0 */
+		.i2c_port = I2C_PORT_USB_C1_PPC,
+		.i2c_addr_flags = NX20P3483_ADDR2_FLAGS,
+		.drv = &nx20p348x_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
+
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+struct ppc_config_t ppc_chips_c1 = {
+	.i2c_port = I2C_PORT_USB_C1_PPC,
+	.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+	.drv = &syv682x_drv,
+};
+
+/* USBC mux configuration - Alder Lake includes internal mux */
+static const struct usb_mux_chain usbc2_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C2,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+
+static const struct usb_mux_chain usbc1_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+
+/*
+ * USB3 DB mux configuration - the top level mux still needs to be set
+ * to the virtual_usb_mux_driver so the AP gets notified of mux changes
+ * and updates the TCSS configuration on state changes.
+ */
+static const struct usb_mux_chain usbc1_usb3_db_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
+};
+
+struct usb_mux_chain usb_muxes[] = {
+	[USBC_PORT_C2] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C2,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+	},
+	[USBC_PORT_C1] = {
+		.mux = &(const struct usb_mux) {
+			/* PS8815 DB */
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc1_usb3_db_retimer,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
+
+static const struct usb_mux_chain usb_muxes_c1 = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C1_MUX,
+			.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
+		},
+	.next = &usbc1_tcss_usb_mux,
+};
+
+static const struct usb_mux_chain usb_muxes_c2 = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C2,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C2_MUX,
+			.i2c_addr_flags = USBC_PORT_C2_BB_RETIMER_I2C_ADDR,
+		},
+	.next = &usbc2_tcss_usb_mux,
+};
+
+/* BC1.2 charger detect configuration */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	[USBC_PORT_C2] = {
+		.i2c_port = I2C_PORT_USB_C2_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_1_FLAGS,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C1_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
+
+/*
+ * USB C0 and C2 uses burnside bridge chips and have their reset
+ * controlled by their respective TCPC chips acting as GPIO expanders.
+ *
+ * ioex_init() is normally called before we take the TCPCs out of
+ * reset, so we need to start in disabled mode, then explicitly
+ * call ioex_init().
+ */
+
+struct ioexpander_config_t ioex_config[] = {
+	[IOEX_C1_NCT38XX] = {
+		.i2c_host_port = I2C_PORT_USB_C1_TCPC,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
+	},
+	[IOEX_C2_NCT38XX] = {
+		.i2c_host_port = I2C_PORT_USB_C2_TCPC,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT);
+
+void config_usb_db_type(void)
+{
+	enum ec_cfg_usb_db_type db_type = ec_cfg_usb_db_type();
+
+	/*
+	 * TODO(b/180434685): implement multiple DB types
+	 */
+
+	CPRINTS("Configured USB DB type number is %d", db_type);
+}
+
+__override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
+{
+	int rst_signal;
+
+	if (me->usb_port == USBC_PORT_C1)
+		rst_signal = IOEX_USB_C1_RT_RST_ODL;
+	else if (me->usb_port == USBC_PORT_C2)
+		rst_signal = IOEX_USB_C2_RT_RST_ODL;
+	else
+		return EC_ERROR_INVAL;
+
+	/*
+	 * We do not have a load switch for the burnside bridge chips,
+	 * so we only need to sequence reset.
+	 */
+
+	if (enable) {
+		/*
+		 * Tpw, minimum time from VCC to RESET_N de-assertion is 100us.
+		 * For boards that don't provide a load switch control, the
+		 * retimer_init() function ensures power is up before calling
+		 * this function.
+		 */
+		gpio_or_ioex_set_level(rst_signal, 1);
+		/*
+		 * Allow 1ms time for the retimer to power up lc_domain
+		 * which powers I2C controller within retimer
+		 */
+		msleep(1);
+	} else {
+		gpio_or_ioex_set_level(rst_signal, 0);
+		msleep(1);
+	}
+	return EC_SUCCESS;
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * TODO(b/179648104): figure out correct timing
+	 */
+
+	gpio_set_level(GPIO_USB_C0_C2_TCPC_RST_ODL, 0);
+	gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 0);
+
+	if (ec_cfg_usb_db_type() == DB_USB4_NCT3807)
+		gpio_set_level(GPIO_USB_C1_RST_ODL, 0);
+
+	/*
+	 * delay for power-on to reset-off and min. assertion time
+	 */
+
+	msleep(20);
+
+	gpio_set_level(GPIO_USB_C0_C2_TCPC_RST_ODL, 1);
+	gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 1);
+
+	if (ec_cfg_usb_db_type() == DB_USB4_NCT3807)
+		gpio_set_level(GPIO_USB_C1_RST_ODL, 1);
+
+	/* wait for chips to come up */
+
+	msleep(50);
+}
+
+static void enable_ioex(int ioex)
+{
+	ioex_init(ioex);
+}
+
+static void board_tcpc_init(void)
+{
+	/* Don't reset TCPCs after initial reset */
+	if (!system_jumped_late()) {
+		board_reset_pd_mcu();
+
+		/*
+		 * These IO expander pins are implemented using the
+		 * C0/C2 TCPC, so they must be set up after the TCPC has
+		 * been taken out of reset.
+		 */
+		if (ec_cfg_usb_db_type() == DB_USB4_NCT3807)
+			enable_ioex(IOEX_C1_NCT38XX);
+		enable_ioex(IOEX_C2_NCT38XX);
+	}
+
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C2_PPC_INT_ODL);
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C2_TCPC_INT_ODL);
+
+	/* Enable BC1.2 interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C2_BC12_INT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (gpio_get_level(GPIO_USB_C2_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_0;
+
+	if (gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
+
+int ppc_get_alert_status(int port)
+{
+	if (port == USBC_PORT_C2)
+		return gpio_get_level(GPIO_USB_C2_PPC_INT_ODL) == 0;
+	else if (port == USBC_PORT_C1)
+		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
+	return 0;
+}
+
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C2_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C2);
+		break;
+	case GPIO_USB_C1_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C1);
+		break;
+	default:
+		break;
+	}
+}
+
+void bc12_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C2_BC12_INT_ODL:
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+		break;
+	case GPIO_USB_C1_BC12_INT_ODL:
+		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+		break;
+	default:
+		break;
+	}
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C1_PPC_INT_ODL:
+		switch (ec_cfg_usb_db_type()) {
+		case DB_USB3_PS8815:
+			nx20p348x_interrupt(USBC_PORT_C1);
+			break;
+		case DB_USB4_NCT3807:
+			syv682x_interrupt(USBC_PORT_C1);
+			break;
+		}
+		break;
+	case GPIO_USB_C2_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C2);
+		break;
+	default:
+		break;
+	}
+}
+
+void retimer_interrupt(enum gpio_signal signal)
+{
+	/*
+	 * TODO(b/179513527): add USB-C support
+	 */
+}
+
+__override bool board_is_dts_port(int port)
+{
+	return port == USBC_PORT_C2;
+}
+
+__override bool board_is_tbt_usb4_port(int port)
+{
+	if (((port == USBC_PORT_C2) && (ec_cfg_usb_mb_type() == MB_USB4_TBT)) ||
+	    ((port == USBC_PORT_C1) &&
+	     (ec_cfg_usb_db_type() == DB_USB4_NCT3807)))
+		return true;
+
+	return false;
+}
+
+__override enum tbt_compat_cable_speed board_get_max_tbt_speed(int port)
+{
+	if (!board_is_tbt_usb4_port(port))
+		return TBT_SS_RES_0;
+
+	return TBT_SS_TBT_GEN3;
+}
+
+void db_update_usb4_config_from_config(void)
+{
+	tcpc_config[USBC_PORT_C1] = tcpc_config_c1;
+	ppc_chips[USBC_PORT_C1] = ppc_chips_c1;
+	usb_muxes[USBC_PORT_C1] = usb_muxes_c1;
+}
+
+void mb_update_usb4_tbt_config_from_config(void)
+{
+	usb_muxes[USBC_PORT_C2] = usb_muxes_c2;
+}
diff --git a/board/felwinter/usbc_config.h b/board/felwinter/usbc_config.h
new file mode 100644
index 0000000000..cab32351f5
--- /dev/null
+++ b/board/felwinter/usbc_config.h
@@ -0,0 +1,21 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Brya board-specific USB-C configuration */
+
+#ifndef __CROS_EC_USBC_CONFIG_H
+#define __CROS_EC_USBC_CONFIG_H
+
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#define CONFIG_USB_PD_TCPC_RUNTIME_CONFIG
+#define CONFIG_USB_MUX_RUNTIME_CONFIG
+
+enum usbc_port { USBC_PORT_C2 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
+
+void config_usb_db_type(void);
+void db_update_usb4_config_from_config(void);
+void mb_update_usb4_tbt_config_from_config(void);
+
+#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/felwinter/vif_override.xml b/board/felwinter/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/felwinter/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/fennel/battery.c b/board/fennel/battery.c
index cfd17a136f..882ff0c5a2 100644
--- a/board/fennel/battery.c
+++ b/board/fennel/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/fennel/board.c b/board/fennel/board.c
index 799255712d..f650911ba0 100644
--- a/board/fennel/board.c
+++ b/board/fennel/board.c
@@ -1,10 +1,9 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "backlight.h"
 #include "button.h"
 #include "charge_manager.h"
@@ -16,6 +15,8 @@
 #include "console.h"
 #include "driver/accel_lis2dw12.h"
 #include "driver/accelgyro_bmi_common.h"
+#include "driver/accelgyro_icm42607.h"
+#include "driver/accelgyro_icm_common.h"
 #include "driver/battery/max17055.h"
 #include "driver/bc12/pi3usb9201.h"
 #include "driver/charger/isl923x.h"
@@ -29,9 +30,10 @@
 #include "i2c.h"
 #include "i2c_bitbang.h"
 #include "it8801.h"
-#include "keyboard_scan.h"
 #include "keyboard_backlight.h"
+#include "keyboard_scan.h"
 #include "lid_switch.h"
+#include "panic.h"
 #include "power.h"
 #include "power_button.h"
 #include "registers.h"
@@ -39,41 +41,55 @@
 #include "system.h"
 #include "tablet_mode.h"
 #include "task.h"
-#include "tcpm.h"
+#include "tcpm/tcpm.h"
 #include "timer.h"
 #include "usb_charge.h"
 #include "usb_mux.h"
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
 	schedule_deferred_pd_interrupt(0 /* port */);
 }
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /******************************************************************************/
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] =  {"BOARD_ID",  3300, 4096, 0, STM32_AIN(10)},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)},
+	[ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(10) },
+	[ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /******************************************************************************/
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{"typec", 0, 400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"other", 1, 400, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
+	{ .name = "typec",
+	  .port = 0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "other",
+	  .port = 1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
 const struct i2c_port_t i2c_bitbang_ports[] = {
-	{"battery", 2, 100, GPIO_I2C3_SCL, GPIO_I2C3_SDA, .drv = &bitbang_drv},
+	{ .name = "battery",
+	  .port = 2,
+	  .kbps = 100,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA,
+	  .drv = &bitbang_drv },
 };
 const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
 
@@ -81,13 +97,13 @@ const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
 
 /* power signal list.  Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
+	{ GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" },
+	{ GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" },
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
 /* Keyboard scan setting */
-struct keyboard_scan_config keyscan_config = {
+__override struct keyboard_scan_config keyscan_config = {
 	/*
 	 * TODO(b/133200075): Tune this once we have the final performance
 	 * out of the driver and the i2c bus.
@@ -106,8 +122,8 @@ struct keyboard_scan_config keyscan_config = {
 
 struct ioexpander_config_t ioex_config[CONFIG_IO_EXPANDER_PORT_COUNT] = {
 	[0] = {
-		.i2c_host_port = I2C_PORT_IO_EXPANDER_IT8801,
-		.i2c_slave_addr = IT8801_I2C_ADDR,
+		.i2c_host_port = I2C_PORT_KB_DISCRETE,
+		.i2c_addr_flags = IT8801_I2C_ADDR1,
 		.drv = &it8801_ioexpander_drv,
 	},
 };
@@ -132,15 +148,18 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = I2C_PORT_TCPC0,
-			.addr_flags = FUSB302_I2C_SLAVE_ADDR_FLAGS,
+			.addr_flags = FUSB302_I2C_ADDR_FLAGS,
 		},
 		.drv = &fusb302_tcpm_drv,
 	},
 };
 
-static void board_hpd_status(const struct usb_mux *me,
-			     int hpd_lvl, int hpd_irq)
+static void board_hpd_status(const struct usb_mux *me, mux_state_t mux_state,
+			     bool *ack_required)
 {
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
 	/*
 	 * svdm_dp_attention() did most of the work, we only need to notify
 	 * host here.
@@ -148,13 +167,16 @@ static void board_hpd_status(const struct usb_mux *me,
 	host_set_single_event(EC_HOST_EVENT_USB_MUX);
 }
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+				.hpd_update = &board_hpd_status,
+			},
 	},
 };
 
@@ -200,7 +222,7 @@ int board_set_active_charge_port(int charge_port)
 		if (board_vbus_source_enabled(charge_port))
 			return -1;
 		break;
-	case CHARGE_PORT_NONE:
+	default:
 		/*
 		 * To ensure the fuel gauge (max17055) is always powered
 		 * even when battery is disconnected, keep VBAT rail on but
@@ -208,22 +230,11 @@ int board_set_active_charge_port(int charge_port)
 		 */
 		charger_set_current(CHARGER_SOLO, 0);
 		break;
-	default:
-		panic("Invalid charge port\n");
-		break;
 	}
 
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-			       CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
-
 int board_discharge_on_ac(int enable)
 {
 	int ret, port;
@@ -253,7 +264,7 @@ int pd_snk_is_vbus_provided(int port)
 
 void bc12_interrupt(enum gpio_signal signal)
 {
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
 }
 
 #ifndef VARIANT_KUKUI_NO_SENSORS
@@ -273,13 +284,12 @@ static void board_spi_enable(void)
 	STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
 
 	/* Reinitialize spi peripheral. */
-	spi_enable(CONFIG_SPI_ACCEL_PORT, 1);
+	spi_enable(&spi_devices[0], 1);
 
 	/* Pin mux spi peripheral toward the sensor. */
-	gpio_config_module(MODULE_SPI_MASTER, 1);
+	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
 }
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP,
-	     board_spi_enable,
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_spi_enable,
 	     MOTION_SENSE_HOOK_PRIO - 1);
 
 static void board_spi_disable(void)
@@ -287,14 +297,16 @@ static void board_spi_disable(void)
 	/* Set pins to a state calming the sensor down. */
 	gpio_set_flags(GPIO_EC_SENSOR_SPI_CK, GPIO_OUT_LOW);
 	gpio_set_level(GPIO_EC_SENSOR_SPI_CK, 0);
-	gpio_config_module(MODULE_SPI_MASTER, 0);
+	/* Pull SPI_NSS pin to low to prevent a leakage. */
+	gpio_set_flags(GPIO_EC_SENSOR_SPI_NSS, GPIO_OUT_LOW);
+	gpio_set_level(GPIO_EC_SENSOR_SPI_NSS, 0);
+	gpio_config_module(MODULE_SPI_CONTROLLER, 0);
 
 	/* Disable spi peripheral and clocks. */
-	spi_enable(CONFIG_SPI_ACCEL_PORT, 0);
+	spi_enable(&spi_devices[0], 0);
 	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
 }
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN,
-	     board_spi_disable,
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_spi_disable,
 	     MOTION_SENSE_HOOK_PRIO + 1);
 #endif /* !VARIANT_KUKUI_NO_SENSORS */
 
@@ -333,23 +345,74 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Rotation matrixes */
-static const mat33_fp_t base_standard_ref = {
-	{0, FLOAT_TO_FP(1), 0},
-	{FLOAT_TO_FP(-1), 0, 0},
-	{0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					      { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
 
-static const mat33_fp_t lid_standard_ref = {
-	{FLOAT_TO_FP(-1), 0, 0},
-	{0, FLOAT_TO_FP(1), 0},
-	{0, 0, FLOAT_TO_FP(-1) }
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, FLOAT_TO_FP(1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
 /* sensor private data */
 /* Lid accel private data */
 static struct stprivate_data g_lis2dwl_data;
 /* Base accel private data */
 static struct bmi_drv_data_t g_bmi160_data;
+static struct icm_drv_data_t g_icm42607_data;
+
+enum base_accelgyro_type {
+	BASE_GYRO_NONE = 0,
+	BASE_GYRO_BMI160 = 1,
+	BASE_GYRO_ICM426XX = 2,
+};
+
+static enum base_accelgyro_type base_accelgyro_config;
+
+struct motion_sensor_t icm42607_base_accel = {
+	 .name = "Accel",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_ICM42607,
+	 .type = MOTIONSENSE_TYPE_ACCEL,
+	 .location = MOTIONSENSE_LOC_BASE,
+	 .drv = &icm42607_drv,
+	 .mutex = &g_base_mutex,
+	 .drv_data = &g_icm42607_data,
+	 .port = CONFIG_SPI_ACCEL_PORT,
+	 .i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
+	 .default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
+	 .rot_standard_ref = NULL,
+	 .min_frequency = ICM42607_ACCEL_MIN_FREQ,
+	 .max_frequency = ICM42607_ACCEL_MAX_FREQ,
+	 .config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+		/* Sensor on for angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+	 },
+};
+
+struct motion_sensor_t icm42607_base_gyro = {
+	.name = "Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM42607,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm42607_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm42607_data,
+	.port = CONFIG_SPI_ACCEL_PORT,
+	.i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = NULL,
+	.min_frequency = ICM42607_GYRO_MIN_FREQ,
+	.max_frequency = ICM42607_GYRO_MAX_FREQ,
+};
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
@@ -393,9 +456,9 @@ struct motion_sensor_t motion_sensors[] = {
 	 .mutex = &g_base_mutex,
 	 .drv_data = &g_bmi160_data,
 	 .port = CONFIG_SPI_ACCEL_PORT,
-	 .i2c_spi_addr_flags = SLAVE_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
+	 .i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
 	 .rot_standard_ref = &base_standard_ref,
-	 .default_range = 2,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
+	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
 	 .min_frequency = BMI_ACCEL_MIN_FREQ,
 	 .max_frequency = BMI_ACCEL_MAX_FREQ,
 	 .config = {
@@ -421,7 +484,7 @@ struct motion_sensor_t motion_sensors[] = {
 	 .mutex = &g_base_mutex,
 	 .drv_data = &g_bmi160_data,
 	 .port = CONFIG_SPI_ACCEL_PORT,
-	 .i2c_spi_addr_flags = SLAVE_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
+	 .i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
 	 .default_range = 1000, /* dps */
 	 .rot_standard_ref = &base_standard_ref,
 	 .min_frequency = BMI_GYRO_MIN_FREQ,
@@ -430,8 +493,54 @@ struct motion_sensor_t motion_sensors[] = {
 };
 const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
+static void board_detect_motionsensor(void)
+{
+	int ret;
+	int val;
+
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return;
+	if (base_accelgyro_config != BASE_GYRO_NONE)
+		return;
+	/* Check base accelgyro chip */
+	ret = icm_read8(&icm42607_base_accel, ICM42607_REG_WHO_AM_I, &val);
+	if (ret)
+		ccprints("Get ICM fail.");
+	if (val == ICM42607_CHIP_ICM42607P) {
+		motion_sensors[BASE_ACCEL] = icm42607_base_accel;
+		motion_sensors[BASE_GYRO] = icm42607_base_gyro;
+	}
+	base_accelgyro_config = (val == ICM42607_CHIP_ICM42607P) ?
+					BASE_GYRO_ICM426XX :
+					BASE_GYRO_BMI160;
+	ccprints("BASE Accelgyro: %s",
+		 (val == ICM42607_CHIP_ICM42607P) ? "ICM42607" : "BMI160");
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_detect_motionsensor,
+	     HOOK_PRIO_DEFAULT);
+/*
+ * board_spi_enable() will be called in the board_init() when sysjump to rw
+ * the board_init() is DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT)
+ * the board_detect_motionsensor() reads data via sensor SPI
+ * so the priority of board_detect_motionsensor should be HOOK_PRIO_DEFAULT+1
+ */
+DECLARE_HOOK(HOOK_INIT, board_detect_motionsensor, HOOK_PRIO_DEFAULT + 1);
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	switch (base_accelgyro_config) {
+	case BASE_GYRO_ICM426XX:
+		icm42607_interrupt(signal);
+		break;
+	case BASE_GYRO_BMI160:
+	default:
+		bmi160_interrupt(signal);
+		break;
+	}
+}
+
 const struct it8801_pwm_t it8801_pwm_channels[] = {
-	[IT8801_PWM_CH_KBLIGHT] = {.index = 4},
+	[IT8801_PWM_CH_KBLIGHT] = { .index = 4 },
 };
 
 void board_kblight_init(void)
@@ -444,12 +553,41 @@ bool board_has_kb_backlight(void)
 	/* Default enable keyboard backlight */
 	return true;
 }
+#endif /* !VARIANT_KUKUI_NO_SENSORS */
+
+/* Battery functions */
+#define SB_SMARTCHARGE 0x26
+/* Quick charge enable bit */
+#define SMART_QUICK_CHARGE 0x02
+/* Quick charge support bit */
+#define MODE_QUICK_CHARGE_SUPPORT 0x01
+
+static void sb_quick_charge_mode(int enable)
+{
+	int val, rv;
+
+	rv = sb_read(SB_SMARTCHARGE, &val);
+	if (rv || !(val & MODE_QUICK_CHARGE_SUPPORT))
+		return;
+
+	if (enable)
+		val |= SMART_QUICK_CHARGE;
+	else
+		val &= ~SMART_QUICK_CHARGE;
+
+	sb_write(SB_SMARTCHARGE, val);
+}
 
 /* Called on AP S0iX -> S0 transition */
 static void board_chipset_resume(void)
 {
+#ifndef VARIANT_KUKUI_NO_SENSORS
 	if (board_has_kb_backlight())
 		ioex_set_level(IOEX_KB_BL_EN, 1);
+#endif
+
+	/* Normal charge mode */
+	sb_quick_charge_mode(0);
 }
 DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
 DECLARE_HOOK(HOOK_INIT, board_chipset_resume, HOOK_PRIO_DEFAULT);
@@ -457,13 +595,16 @@ DECLARE_HOOK(HOOK_INIT, board_chipset_resume, HOOK_PRIO_DEFAULT);
 /* Called on AP S0 -> S0iX transition */
 static void board_chipset_suspend(void)
 {
+#ifndef VARIANT_KUKUI_NO_SENSORS
 	if (board_has_kb_backlight())
 		ioex_set_level(IOEX_KB_BL_EN, 0);
+#endif
+
+	/* Quick charge mode */
+	sb_quick_charge_mode(1);
 }
 DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
 
-#endif /* !VARIANT_KUKUI_NO_SENSORS */
-
 /* Called on AP S5 -> S3 transition */
 static void board_chipset_startup(void)
 {
@@ -490,8 +631,8 @@ int board_get_battery_i2c(void)
 }
 
 #ifdef SECTION_IS_RW
-static int it8801_get_target_channel(enum pwm_channel *channel,
-				     int type, int index)
+static int it8801_get_target_channel(enum pwm_channel *channel, int type,
+				     int index)
 {
 	switch (type) {
 	case EC_PWM_TYPE_GENERIC:
@@ -514,14 +655,13 @@ host_command_pwm_set_duty(struct host_cmd_handler_args *args)
 	if (it8801_get_target_channel(&channel, p->pwm_type, p->index))
 		return EC_RES_INVALID_PARAM;
 
-	duty = (uint32_t) p->duty * 255 / 65535;
+	duty = (uint32_t)p->duty * 255 / 65535;
 	it8801_pwm_set_raw_duty(channel, duty);
 	it8801_pwm_enable(channel, p->duty > 0);
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_DUTY,
-		     host_command_pwm_set_duty,
+DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_DUTY, host_command_pwm_set_duty,
 		     EC_VER_MASK(0));
 
 static enum ec_status
@@ -535,12 +675,11 @@ host_command_pwm_get_duty(struct host_cmd_handler_args *args)
 	if (it8801_get_target_channel(&channel, p->pwm_type, p->index))
 		return EC_RES_INVALID_PARAM;
 
-	r->duty = (uint32_t) it8801_pwm_get_raw_duty(channel) * 65535 / 255;
+	r->duty = (uint32_t)it8801_pwm_get_raw_duty(channel) * 65535 / 255;
 	args->response_size = sizeof(*r);
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_DUTY,
-		     host_command_pwm_get_duty,
+DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_DUTY, host_command_pwm_get_duty,
 		     EC_VER_MASK(0));
 #endif
diff --git a/board/fennel/board.h b/board/fennel/board.h
index aaf863206a..e00c37c4e9 100644
--- a/board/fennel/board.h
+++ b/board/fennel/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,7 +11,8 @@
 #define VARIANT_KUKUI_JACUZZI
 #define VARIANT_KUKUI_BATTERY_SMART
 #define VARIANT_KUKUI_CHARGER_ISL9238
-
+#define VARIANT_KUKUI_EC_STM32F098
+#undef CONFIG_CMD_MFALLOW
 #ifndef SECTION_IS_RW
 #define VARIANT_KUKUI_NO_SENSORS
 #endif /* SECTION_IS_RW */
@@ -25,6 +26,8 @@
 #define CONFIG_BATTERY_HW_PRESENT_CUSTOM
 
 #define CONFIG_CHARGER_PSYS
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 5
 
 #define CONFIG_CHARGER_RUNTIME_CONFIG
 
@@ -48,24 +51,24 @@
 #define CONFIG_USB_MUX_IT5205
 
 #define CONFIG_LED_ONOFF_STATES
-#define CONFIG_LED_POWER_LED
 
 /* Motion Sensors */
 #ifndef VARIANT_KUKUI_NO_SENSORS
-#define CONFIG_ACCEL_LIS2DWL    /* Lid accel */
+#define CONFIG_ACCEL_LIS2DWL /* Lid accel */
 #define CONFIG_ACCELGYRO_BMI160 /* Base accel */
-#define CONFIG_ACCEL_INTERRUPTS
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+#define CONFIG_ACCELGYRO_ICM42607 /* Base accel second source*/
+#define CONFIG_ACCELGYRO_ICM42607_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
 #define CONFIG_ALS
 #define CONFIG_CMD_ACCEL_INFO
 
 #define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_UPDATE
 #define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
 #define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
 
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
 #ifdef SECTION_IS_RW
 #define CONFIG_IO_EXPANDER_IT8801_PWM
 #define CONFIG_KEYBOARD_BACKLIGHT
@@ -74,25 +77,24 @@
 #endif /* VARIANT_KUKUI_NO_SENSORS */
 
 /* I2C ports */
-#define I2C_PORT_BC12               0
-#define I2C_PORT_TCPC0              0
-#define I2C_PORT_USB_MUX            0
-#define I2C_PORT_CHARGER            board_get_charger_i2c()
-#define I2C_PORT_SENSORS            1
-#define I2C_PORT_IO_EXPANDER_IT8801 1
-#define I2C_PORT_VIRTUAL_BATTERY    I2C_PORT_BATTERY
-#define I2C_PORT_BATTERY            2
+#define I2C_PORT_BC12 0
+#define I2C_PORT_TCPC0 0
+#define I2C_PORT_USB_MUX 0
+#define I2C_PORT_CHARGER board_get_charger_i2c()
+#define I2C_PORT_SENSORS 1
+#define I2C_PORT_KB_DISCRETE 1
+#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
+#define I2C_PORT_BATTERY 2
+
+/* IT8801 I2C address */
+#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1
 
 /* Enable Accel over SPI */
-#define CONFIG_SPI_ACCEL_PORT    0  /* The first SPI master port (SPI2) */
+#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */
 
 #define CONFIG_KEYBOARD_PROTOCOL_MKBP
 #define CONFIG_MKBP_EVENT
 #define CONFIG_MKBP_USE_GPIO
-/* Define the MKBP events which are allowed to wakeup AP in S3. */
-#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \
-		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
 
 #ifndef __ASSEMBLER__
 
@@ -146,7 +148,7 @@ void emmc_cmd_interrupt(enum gpio_signal signal);
 void bc12_interrupt(enum gpio_signal signal);
 void board_reset_pd_mcu(void);
 int board_get_version(void);
-int board_is_sourcing_vbus(int port);
+void motion_interrupt(enum gpio_signal signal);
 
 /* returns the i2c port number of charger/battery */
 int board_get_charger_i2c(void);
diff --git a/board/fennel/build.mk b/board/fennel/build.mk
index a6e1c010d7..f583684804 100644
--- a/board/fennel/build.mk
+++ b/board/fennel/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/fennel/ec.tasklist b/board/fennel/ec.tasklist
index c1330b86f8..fb131b8eb4 100644
--- a/board/fennel/ec.tasklist
+++ b/board/fennel/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/fennel/gpio.inc b/board/fennel/gpio.inc
index 3dccd94506..5ebecfac53 100644
--- a/board/fennel/gpio.inc
+++ b/board/fennel/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,7 +22,7 @@ GPIO_INT(PMIC_EC_RESETB,    PIN(B, 7),  GPIO_INT_BOTH | GPIO_PULL_DOWN,
 GPIO_INT(WARM_RESET_REQ,    PIN(A, 3),  GPIO_INT_RISING | GPIO_PULL_DOWN,
          chipset_reset_request_interrupt)
 GPIO_INT_RW(ACCEL_INT_ODL,  PIN(A, 4), GPIO_INT_FALLING | GPIO_SEL_1P8V | GPIO_PULL_UP,
-         bmi160_interrupt)
+         motion_interrupt)
 GPIO_INT_RO(EMMC_CMD,       PIN(B, 15), GPIO_INT_FALLING,
          emmc_cmd_interrupt)
 GPIO_INT(SPI1_NSS,          PIN(A, 15), GPIO_INT_BOTH | GPIO_PULL_UP,
@@ -117,5 +117,5 @@ ALTERNATE(PIN_MASK(A, 0x8000), 0, MODULE_SPI,        0)
 /* EMMC SPI SLAVE: PB13/14/15 */
 ALTERNATE(PIN_MASK(B, 0xE000), 0, MODULE_SPI_FLASH,  0)
 /* SENSORS SPI MASTER: PB10, PB12, PC2, PC3 */
-ALTERNATE(PIN_MASK(B, 0x0400), 5, MODULE_SPI_MASTER, 0)
-ALTERNATE(PIN_MASK(C, 0x000C), 1, MODULE_SPI_MASTER, 0)
+ALTERNATE(PIN_MASK(B, 0x0400), 5, MODULE_SPI_CONTROLLER, 0)
+ALTERNATE(PIN_MASK(C, 0x000C), 1, MODULE_SPI_CONTROLLER, 0)
diff --git a/board/fennel/led.c b/board/fennel/led.c
index 69b9fcfe97..60fadc3eb0 100644
--- a/board/fennel/led.c
+++ b/board/fennel/led.c
@@ -1,51 +1,58 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Power and battery LED control for Fennel
  */
 #include "common.h"
-#include "ioexpander.h"
 #include "driver/ioexpander/it8801.h"
 #include "ec_commands.h"
+#include "ioexpander.h"
 #include "led_common.h"
 #include "led_onoff_states.h"
 
 #define LED_ON_LVL 0
 #define LED_OFF_LVL 1
 
-const int led_charge_lvl_1 = 5;
-const int led_charge_lvl_2 = 97;
+__override const int led_charge_lvl_1 = 5;
+__override const int led_charge_lvl_2 = 97;
 
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED,    LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER,  LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
 
-const struct led_descriptor led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    1 * LED_ONE_SEC },
+						  { LED_OFF,
+						    3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-void led_set_color_battery(enum ec_led_colors color)
+__override void led_set_color_battery(enum ec_led_colors color)
 {
 	switch (color) {
 	case EC_LED_COLOR_GREEN:
@@ -67,7 +74,7 @@ void led_set_color_battery(enum ec_led_colors color)
 	}
 }
 
-void led_set_color_power(enum ec_led_colors color)
+__override void led_set_color_power(enum ec_led_colors color)
 {
 	switch (color) {
 	case EC_LED_COLOR_WHITE:
diff --git a/board/fennel/vif_override.xml b/board/fennel/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/fennel/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/fizz/board.c b/board/fizz/board.c
index b3627afa7b..5eaa09efec 100644
--- a/board/fizz/board.c
+++ b/board/fizz/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,26 +6,26 @@
 /* Fizz board-specific configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "als.h"
 #include "battery.h"
 #include "bd99992gw.h"
 #include "board_config.h"
 #include "button.h"
+#include "cec.h"
 #include "charge_manager.h"
 #include "charge_state.h"
 #include "charger.h"
 #include "chipset.h"
 #include "console.h"
 #include "cros_board_info.h"
+#include "driver/cec/bitbang.h"
 #include "driver/pmic_tps650x30.h"
-#include "driver/temp_sensor/tmp432.h"
 #include "driver/tcpm/ps8xxx.h"
 #include "driver/tcpm/tcpci.h"
 #include "driver/tcpm/tcpm.h"
+#include "driver/temp_sensor/tmp432.h"
 #include "espi.h"
 #include "extpower.h"
-#include "espi.h"
 #include "fan.h"
 #include "fan_chip.h"
 #include "gpio.h"
@@ -51,8 +51,8 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static uint16_t board_version;
 static uint8_t oem;
@@ -63,7 +63,7 @@ static void tcpc_alert_event(enum gpio_signal signal)
 	schedule_deferred_pd_interrupt(0 /* port */);
 }
 
-#define ADP_DEBOUNCE_MS		1000  /* Debounce time for BJ plug/unplug */
+#define ADP_DEBOUNCE_MS 1000 /* Debounce time for BJ plug/unplug */
 /*
  * ADP_IN pin state. It's initialized to 1 (=unplugged) because the IRQ won't
  * be triggered if BJ is the power source.
@@ -115,6 +115,7 @@ void vbus0_evt(enum gpio_signal signal)
 	task_wake(TASK_ID_PD_C0);
 }
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /* Hibernate wake configuration */
@@ -126,7 +127,8 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* Vbus sensing (1/10 voltage divider). */
-	[ADC_VBUS] = {"VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
+	[ADC_VBUS] = { "VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT * 10,
+		       ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
@@ -134,7 +136,7 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 /* Physical fans. These are logically separate from pwm_channels. */
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_FAN_PWR_EN,
 };
@@ -159,20 +161,49 @@ BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
 /******************************************************************************/
 /* MFT channels. These are logically separate from pwm_channels. */
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN },
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 /* I2C port map */
-const struct i2c_port_t i2c_ports[]  = {
-	{"tcpc", NPCX_I2C_PORT0_0, 400, GPIO_I2C0_0_SCL, GPIO_I2C0_0_SDA},
-	{"eeprom", NPCX_I2C_PORT0_1, 400, GPIO_I2C0_1_SCL, GPIO_I2C0_1_SDA},
-	{"charger", NPCX_I2C_PORT1, 100, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"pmic", NPCX_I2C_PORT2, 400, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-	{"thermal", NPCX_I2C_PORT3, 400, GPIO_I2C3_SCL, GPIO_I2C3_SDA},
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "tcpc",
+	  .port = NPCX_I2C_PORT0_0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_0_SCL,
+	  .sda = GPIO_I2C0_0_SDA },
+	{ .name = "eeprom",
+	  .port = NPCX_I2C_PORT0_1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_1_SCL,
+	  .sda = GPIO_I2C0_1_SDA },
+	{ .name = "charger",
+	  .port = NPCX_I2C_PORT1,
+	  .kbps = 100,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "pmic",
+	  .port = NPCX_I2C_PORT2,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "thermal",
+	  .port = NPCX_I2C_PORT3,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
+/* CEC ports */
+const struct cec_config_t cec_config[] = {
+	[CEC_PORT_0] = {
+		.drv = &bitbang_cec_drv,
+		.offline_policy = NULL,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(cec_config) == CEC_PORT_COUNT);
+
 /* TCPC mux configuration */
 const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
@@ -192,21 +223,19 @@ static int ps8751_tune_mux(const struct usb_mux *me)
 	return EC_SUCCESS;
 }
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-		.board_init = &ps8751_tune_mux,
-	}
-};
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = 0,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			.board_init = &ps8751_tune_mux,
+		},
+} };
 
 const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_USB1_ENABLE,
-	GPIO_USB2_ENABLE,
-	GPIO_USB3_ENABLE,
-	GPIO_USB4_ENABLE,
-	GPIO_USB5_ENABLE,
+	GPIO_USB1_ENABLE, GPIO_USB2_ENABLE, GPIO_USB3_ENABLE,
+	GPIO_USB4_ENABLE, GPIO_USB5_ENABLE,
 };
 
 void board_reset_pd_mcu(void)
@@ -240,9 +269,10 @@ void board_tcpc_init(void)
 	 * HPD pulse to enable video path
 	 */
 	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		usb_mux_hpd_update(port, 0, 0);
+		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
 
 uint16_t tcpc_get_alert_status(void)
 {
@@ -264,10 +294,10 @@ uint16_t tcpc_get_alert_status(void)
  *     src/mainboard/google/${board}/acpi/dptf.asl
  */
 const struct temp_sensor_t temp_sensors[] = {
-	{"TMP431_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-			TMP432_IDX_LOCAL},
-	{"TMP431_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-			TMP432_IDX_REMOTE1},
+	{ "TMP431_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
+	  TMP432_IDX_LOCAL },
+	{ "TMP431_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
+	  TMP432_IDX_REMOTE1 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -275,14 +305,18 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
  * Thermal limits for each temp sensor.  All temps are in degrees K.  Must be in
  * same order as enum temp_sensor_id.  To always ignore any temp, use 0.
  */
+static const int temp_fan_off = C_TO_K(25);
+static const int temp_fan_max = C_TO_K(50);
 struct ec_thermal_config thermal_params[] = {
 	/* {Twarn, Thigh, Thalt}, <on>
 	 * {Twarn, Thigh, X    }, <off>
 	 * fan_off, fan_max
 	 */
-	{{0, C_TO_K(80), C_TO_K(81)}, {0, C_TO_K(78), 0},
-		C_TO_K(4), C_TO_K(76)},	/* TMP431_Internal */
-	{{0, 0, 0}, {0, 0, 0}, 0, 0},	/* TMP431_Sensor_1 */
+	{ { 0, C_TO_K(80), C_TO_K(81) },
+	  { 0, C_TO_K(78), 0 },
+	  temp_fan_off,
+	  temp_fan_max }, /* TMP431_Internal */
+	{ { 0, 0, 0 }, { 0, 0, 0 }, 0, 0 }, /* TMP431_Sensor_1 */
 };
 BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
 
@@ -491,8 +525,8 @@ static void set_charge_limit(int charge_ma)
 	}
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
 {
 	int p87w = 0, p65w = 0, p60w = 0;
 
@@ -503,11 +537,11 @@ void board_set_charge_limit(int port, int supplier, int charge_ma,
 	 * is called.
 	 */
 	led_alert(charge_ma * charge_mv <
-			CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON * 1000);
+		  CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON * 1000);
 
 	/*
 	 * In terms of timing, this should always work because
-	 * HOOK_PRIO_CHARGE_MANAGER_INIT is notified after HOOK_PRIO_INIT_I2C.
+	 * HOOK_PRIO_INIT_CHARGE_MANAGER is notified after HOOK_PRIO_INIT_I2C.
 	 * If CBI isn't initialized or contains invalid data, we assume it's
 	 * a new board.
 	 */
@@ -550,11 +584,11 @@ void board_set_charge_limit(int port, int supplier, int charge_ma,
 		} else {
 			/*
 			 * TODO:http://crosbug.com/p/65013352.
-	 		 * The current monitoring system doesn't support lower
-	 		 * current. These currents are most likely not enough to
-	 		 * power the system. However, if they're needed, EC can
-	 		 * monitor PMON_PSYS and trigger H_PROCHOT by itself.
-	 		 */
+			 * The current monitoring system doesn't support lower
+			 * current. These currents are most likely not enough to
+			 * power the system. However, if they're needed, EC can
+			 * monitor PMON_PSYS and trigger H_PROCHOT by itself.
+			 */
 			p60w = 1;
 			CPRINTS("Current %dmA not supported", charge_ma);
 		}
@@ -572,60 +606,105 @@ int64_t get_time_dsw_pwrok(void)
 }
 
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED_RED]   = { 3, PWM_CONFIG_DSLEEP, 100 },
+	[PWM_CH_LED_RED] = { 3, PWM_CONFIG_DSLEEP, 100 },
 	[PWM_CH_LED_GREEN] = { 5, PWM_CONFIG_DSLEEP, 100 },
-	[PWM_CH_FAN] = {4, PWM_CONFIG_OPEN_DRAIN, 25000},
+	[PWM_CH_FAN] = { 4, PWM_CONFIG_OPEN_DRAIN, 25000 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
-struct fan_step {
-	int on;
-	int off;
-	int rpm;
+static const struct fan_step_1_1 *fan_table;
+
+static const struct fan_step_1_1 fan_table0[] = {
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(25),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(34),
+	  .rpm = 2800 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(39),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(40),
+	  .rpm = 3200 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(40),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(42),
+	  .rpm = 3400 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(42),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(44),
+	  .rpm = 4200 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(44),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(46),
+	  .rpm = 4800 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(45),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(47),
+	  .rpm = 5200 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(47),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(50),
+	  .rpm = 5600 },
 };
-
-static const struct fan_step *fan_table;
-
-/* Note: Do not make the fan on/off point equal to 0 or 100 */
-static const struct fan_step fan_table0[] = {
-	{.on =  0, .off =  1, .rpm = 0},
-	{.on = 36, .off =  1, .rpm = 2800},
-	{.on = 58, .off = 58, .rpm = 3200},
-	{.on = 66, .off = 61, .rpm = 3400},
-	{.on = 75, .off = 69, .rpm = 4200},
-	{.on = 81, .off = 76, .rpm = 4800},
-	{.on = 88, .off = 83, .rpm = 5200},
-	{.on = 98, .off = 91, .rpm = 5600},
+static const struct fan_step_1_1 fan_table1[] = {
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(25),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(34),
+	  .rpm = 2800 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(39),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(40),
+	  .rpm = 3200 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(40),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(42),
+	  .rpm = 3400 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(42),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(44),
+	  .rpm = 4200 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(44),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(46),
+	  .rpm = 4800 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(45),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(47),
+	  .rpm = 5200 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(47),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(50),
+	  .rpm = 5600 },
 };
-static const struct fan_step fan_table1[] = {
-	{.on =  0, .off =  1, .rpm = 0},
-	{.on = 36, .off =  1, .rpm = 2800},
-	{.on = 62, .off = 58, .rpm = 3200},
-	{.on = 68, .off = 63, .rpm = 3400},
-	{.on = 75, .off = 69, .rpm = 4200},
-	{.on = 81, .off = 76, .rpm = 4800},
-	{.on = 88, .off = 83, .rpm = 5200},
-	{.on = 98, .off = 91, .rpm = 5600},
+static const struct fan_step_1_1 fan_table2[] = {
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(25),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(34),
+	  .rpm = 2200 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(39),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(41),
+	  .rpm = 2900 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(41),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(43),
+	  .rpm = 3000 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(42),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(44),
+	  .rpm = 3300 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(44),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(46),
+	  .rpm = 3600 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(45),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(47),
+	  .rpm = 3900 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(47),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(50),
+	  .rpm = 5000 },
 };
-static const struct fan_step fan_table2[] = {
-	{.on =  0, .off =  1, .rpm = 0},
-	{.on = 36, .off =  1, .rpm = 2200},
-	{.on = 63, .off = 56, .rpm = 2900},
-	{.on = 69, .off = 65, .rpm = 3000},
-	{.on = 75, .off = 70, .rpm = 3300},
-	{.on = 80, .off = 76, .rpm = 3600},
-	{.on = 87, .off = 81, .rpm = 3900},
-	{.on = 98, .off = 91, .rpm = 5000},
-};
-static const struct fan_step fan_table3[] = {
-	{.on =  0, .off =  1, .rpm = 0},
-	{.on = 36, .off = 22, .rpm = 2500},
-	{.on = 54, .off = 49, .rpm = 3200},
-	{.on = 61, .off = 56, .rpm = 3500},
-	{.on = 68, .off = 63, .rpm = 3900},
-	{.on = 75, .off = 69, .rpm = 4500},
-	{.on = 82, .off = 76, .rpm = 5100},
-	{.on = 92, .off = 85, .rpm = 5400},
+static const struct fan_step_1_1 fan_table3[] = {
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(30),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(34),
+	  .rpm = 2500 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(37),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(39),
+	  .rpm = 3200 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(39),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(40),
+	  .rpm = 3500 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(40),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(42),
+	  .rpm = 3900 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(42),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(44),
+	  .rpm = 4500 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(44),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(46),
+	  .rpm = 5100 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(46),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(48),
+	  .rpm = 5400 },
 };
 /* All fan tables must have the same number of levels */
 #define NUM_FAN_LEVELS ARRAY_SIZE(fan_table0)
@@ -718,8 +797,8 @@ static void setup_bj(void)
 
 	switch (oem) {
 	case OEM_KENCH:
-		bj = (BJ_ADAPTER_90W_MASK & BIT(sku)) ?
-			BJ_90W_19P5V : BJ_65W_19P5V;
+		bj = (BJ_ADAPTER_90W_MASK & BIT(sku)) ? BJ_90W_19P5V :
+							BJ_65W_19P5V;
 		break;
 	case OEM_TEEMO:
 	case OEM_BLEEMO:
@@ -728,15 +807,14 @@ static void setup_bj(void)
 	case OEM_WUKONG_A:
 	case OEM_WUKONG_M:
 	case OEM_EXCELSIOR:
-		bj = (BJ_ADAPTER_90W_MASK & BIT(sku)) ?
-			BJ_90W_19V : BJ_65W_19V;
+		bj = (BJ_ADAPTER_90W_MASK & BIT(sku)) ? BJ_90W_19V : BJ_65W_19V;
 		break;
 	case OEM_JAX:
 		bj = BJ_65W_19V;
 		break;
 	default:
-		bj = (BJ_ADAPTER_90W_MASK & BIT(sku)) ?
-			BJ_90W_19P5V : BJ_65W_19P5V;
+		bj = (BJ_ADAPTER_90W_MASK & BIT(sku)) ? BJ_90W_19P5V :
+							BJ_65W_19P5V;
 		break;
 	}
 
@@ -765,8 +843,8 @@ static void board_charge_manager_init(void)
 			charge_manager_update_charge(j, i, NULL);
 	}
 
-	port = gpio_get_level(GPIO_ADP_IN_L) ?
-			CHARGE_PORT_TYPEC0 : CHARGE_PORT_BARRELJACK;
+	port = gpio_get_level(GPIO_ADP_IN_L) ? CHARGE_PORT_TYPEC0 :
+					       CHARGE_PORT_BARRELJACK;
 	CPRINTS("Power source is p%d (%s)", port,
 		port == CHARGE_PORT_TYPEC0 ? "USB-C" : "BJ");
 
@@ -781,7 +859,7 @@ static void board_charge_manager_init(void)
 	}
 }
 DECLARE_HOOK(HOOK_INIT, board_charge_manager_init,
-	     HOOK_PRIO_CHARGE_MANAGER_INIT + 1);
+	     HOOK_PRIO_INIT_CHARGE_MANAGER + 1);
 
 static void board_init(void)
 {
@@ -792,43 +870,8 @@ static void board_init(void)
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
-int fan_percent_to_rpm(int fan, int pct)
+int fan_percent_to_rpm(int fan, int temp_ratio)
 {
-	static int current_level;
-	static int previous_pct;
-	int i;
-
-	/*
-	 * Compare the pct and previous pct, we have the three paths :
-	 *  1. decreasing path. (check the off point)
-	 *  2. increasing path. (check the on point)
-	 *  3. invariant path. (return the current RPM)
-	 */
-	if (pct < previous_pct) {
-		for (i = current_level; i >= 0; i--) {
-			if (pct <= fan_table[i].off)
-				current_level = i - 1;
-			else
-				break;
-		}
-	} else if (pct > previous_pct) {
-		for (i = current_level + 1; i < NUM_FAN_LEVELS; i++) {
-			if (pct >= fan_table[i].on)
-				current_level = i;
-			else
-				break;
-		}
-	}
-
-	if (current_level < 0)
-		current_level = 0;
-
-	previous_pct = pct;
-
-	if (fan_table[current_level].rpm !=
-		fan_get_rpm_target(FAN_CH(fan)))
-		cprints(CC_THERMAL, "Setting fan RPM to %d",
-			fan_table[current_level].rpm);
-
-	return fan_table[current_level].rpm;
+	return temp_ratio_to_rpm_hysteresis(fan_table, NUM_FAN_LEVELS, fan,
+					    temp_ratio, NULL);
 }
diff --git a/board/fizz/board.h b/board/fizz/board.h
index 209fe29dfe..b10c7d8407 100644
--- a/board/fizz/board.h
+++ b/board/fizz/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,7 +12,7 @@
  * Allow dangerous commands.
  * TODO: Remove this config before production.
  */
-#undef  CONFIG_SYSTEM_UNLOCKED
+#undef CONFIG_SYSTEM_UNLOCKED
 #define CONFIG_USB_PD_COMM_LOCKED
 
 /* EC */
@@ -21,18 +21,19 @@
 #define CONFIG_BOARD_HAS_RTC_RESET
 #define CONFIG_CRC8
 #define CONFIG_CEC
-#define CONFIG_CROS_BOARD_INFO
+#define CONFIG_CEC_BITBANG
+#define CONFIG_CBI_EEPROM
 #define CONFIG_DEDICATED_RECOVERY_BUTTON
 #define CONFIG_EMULATED_SYSRQ
 #define CONFIG_LED_COMMON
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
+#define CONFIG_MKBP_INPUT_DEVICES
 #define CONFIG_MKBP_USE_HOST_EVENT
 #define CONFIG_DPTF
-#define CONFIG_FLASH_SIZE 0x80000
+#define CONFIG_FLASH_SIZE_BYTES 0x80000
 #define CONFIG_FPU
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
-#undef  CONFIG_LID_SWITCH
+#define CONFIG_I2C_CONTROLLER
+#undef CONFIG_LID_SWITCH
 #define CONFIG_POWER_BUTTON_IGNORE_LID
 #define CONFIG_PWM
 #define CONFIG_LTO
@@ -47,7 +48,7 @@
 #define WIRELESS_GPIO_WLAN_POWER GPIO_PP3300_DX_WLAN
 #define WIRELESS_GPIO_WWAN GPIO_PP3300_DX_LTE
 #define CEC_GPIO_OUT GPIO_CEC_OUT
-#define CEC_GPIO_IN  GPIO_CEC_IN
+#define CEC_GPIO_IN GPIO_CEC_IN
 #define CEC_GPIO_PULL_UP GPIO_CEC_PULL_UP
 #define CONFIG_FANS 1
 #undef CONFIG_FAN_INIT_SPEED
@@ -57,20 +58,23 @@
 #define CONFIG_THROTTLE_AP
 #define CONFIG_CHIPSET_CAN_THROTTLE
 #define CONFIG_PWM
-#define CONFIG_SUPPRESSED_HOST_COMMANDS \
-	EC_CMD_CONSOLE_SNAPSHOT, EC_CMD_CONSOLE_READ, EC_CMD_PD_GET_LOG_ENTRY
 
 /* EC console commands */
 #define CONFIG_CMD_BUTTON
+#undef CONFIG_CMD_ADC
+
+/* Reduce flash space usage */
+#undef CONFIG_CONSOLE_CMDHELP
 
 /* SOC */
 #define CONFIG_CHIPSET_SKYLAKE
 #define CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET
 #define CONFIG_CHIPSET_HAS_PRE_INIT_CALLBACK
 #define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#define CONFIG_HOST_INTERFACE_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
+#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD
 
 /* Charger */
 #define CONFIG_CHARGE_MANAGER
@@ -79,7 +83,7 @@
 
 #define CONFIG_HOSTCMD_PD_CONTROL
 #define CONFIG_EXTPOWER_GPIO
-#undef  CONFIG_EXTPOWER_DEBOUNCE_MS
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
 #define CONFIG_EXTPOWER_DEBOUNCE_MS 1000
 #define CONFIG_POWER_BUTTON
 #define CONFIG_POWER_BUTTON_X86
@@ -93,7 +97,7 @@
 #define CONFIG_TEMP_SENSOR_TMP432
 
 /* USB */
-#undef  CONFIG_USB_CHARGER		/* dnojiri: verify */
+#undef CONFIG_USB_CHARGER /* dnojiri: verify */
 #define CONFIG_USB_PD_ALT_MODE
 #define CONFIG_USB_PD_ALT_MODE_DFP
 #define CONFIG_USB_PD_CUSTOM_PDO
@@ -116,7 +120,7 @@
 #define CONFIG_USBC_VCONN_SWAP
 
 /* Charge ports */
-#undef  CONFIG_DEDICATED_CHARGE_PORT_COUNT
+#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT
 #define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1
 #define DEDICATED_CHARGE_PORT 1
 
@@ -125,21 +129,21 @@
 #define USB_PORT_COUNT 5
 
 /* Optional feature to configure npcx chip */
-#define NPCX_UART_MODULE2	1 /* 1:GPIO64/65 as UART */
-#define NPCX_JTAG_MODULE2	0 /* 0:GPIO21/17/16/20 as JTAG */
-#define NPCX_TACH_SEL2		1 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
+#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART */
+#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 as JTAG */
+#define NPCX_TACH_SEL2 1 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
 
 /* I2C ports */
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT0_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT0_1
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT1
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT1
-#define I2C_PORT_PMIC		NPCX_I2C_PORT2
-#define I2C_PORT_THERMAL	NPCX_I2C_PORT3
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT0_1
+#define I2C_PORT_BATTERY NPCX_I2C_PORT1
+#define I2C_PORT_CHARGER NPCX_I2C_PORT1
+#define I2C_PORT_PMIC NPCX_I2C_PORT2
+#define I2C_PORT_THERMAL NPCX_I2C_PORT3
 
 /* I2C addresses */
-#define I2C_ADDR_TCPC0_FLAGS		0x0b
-#define I2C_ADDR_EEPROM_FLAGS		0x50
+#define I2C_ADDR_TCPC0_FLAGS 0x0b
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 
 /* Verify and jump to RW image on boot */
 #define CONFIG_VBOOT_EFS
@@ -156,18 +160,17 @@
  * end of RW_A and RW_B, respectively.
  */
 #define CONFIG_RW_B
-#define CONFIG_RW_B_MEM_OFF		CONFIG_RO_MEM_OFF
-#undef  CONFIG_RO_SIZE
-#define CONFIG_RO_SIZE			(CONFIG_FLASH_SIZE / 4)
-#undef  CONFIG_RW_SIZE
-#define CONFIG_RW_SIZE			CONFIG_RO_SIZE
-#define CONFIG_RW_A_STORAGE_OFF		CONFIG_RW_STORAGE_OFF
-#define CONFIG_RW_B_STORAGE_OFF		(CONFIG_RW_A_STORAGE_OFF + \
-					 CONFIG_RW_SIZE)
-#define CONFIG_RW_A_SIGN_STORAGE_OFF	(CONFIG_RW_A_STORAGE_OFF + \
-					 CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE)
-#define CONFIG_RW_B_SIGN_STORAGE_OFF	(CONFIG_RW_B_STORAGE_OFF + \
-					 CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE)
+#define CONFIG_RW_B_MEM_OFF CONFIG_RO_MEM_OFF
+#undef CONFIG_RO_SIZE
+#define CONFIG_RO_SIZE (CONFIG_FLASH_SIZE_BYTES / 4)
+#undef CONFIG_RW_SIZE
+#define CONFIG_RW_SIZE CONFIG_RO_SIZE
+#define CONFIG_RW_A_STORAGE_OFF CONFIG_RW_STORAGE_OFF
+#define CONFIG_RW_B_STORAGE_OFF (CONFIG_RW_A_STORAGE_OFF + CONFIG_RW_SIZE)
+#define CONFIG_RW_A_SIGN_STORAGE_OFF \
+	(CONFIG_RW_A_STORAGE_OFF + CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE)
+#define CONFIG_RW_B_SIGN_STORAGE_OFF \
+	(CONFIG_RW_B_STORAGE_OFF + CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE)
 
 #define CONFIG_RWSIG
 #define CONFIG_RWSIG_TYPE_RWSIG
@@ -193,15 +196,12 @@ enum charge_port {
 };
 
 enum temp_sensor_id {
-	TEMP_SENSOR_CHARGER,	/* BD99992GW SYSTHERM1 */
-	TEMP_SENSOR_DRAM,	/* BD99992GW SYSTHERM2 */
+	TEMP_SENSOR_CHARGER, /* BD99992GW SYSTHERM1 */
+	TEMP_SENSOR_DRAM, /* BD99992GW SYSTHERM2 */
 	TEMP_SENSOR_COUNT
 };
 
-enum adc_channel {
-	ADC_VBUS,
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_VBUS, ADC_CH_COUNT };
 
 enum pwm_channel {
 	PWM_CH_LED_RED,
@@ -223,6 +223,8 @@ enum mft_channel {
 	MFT_CH_COUNT
 };
 
+enum cec_port { CEC_PORT_0, CEC_PORT_COUNT };
+
 enum OEM_ID {
 	OEM_KENCH = 0,
 	OEM_TEEMO = 1,
@@ -242,18 +244,17 @@ enum OEM_ID {
  * delay to turn on the power supply max is ~16ms.
  * delay to turn off the power supply max is about ~180ms.
  */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	250000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* delay to turn on/off vconn */
-#define PD_VCONN_SWAP_DELAY		5000   /* us */
 
 /* Define typical operating power. Since Fizz doesn't have a battery to charge,
  * we're not interested in any power lower than the AP power-on threshold. */
-#define PD_OPERATING_POWER_MW	CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
-#define PD_MAX_POWER_MW		100000
-#define PD_MAX_CURRENT_MA	5000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
+#define PD_MAX_POWER_MW 100000
+#define PD_MAX_CURRENT_MA 5000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Board specific handlers */
 void board_reset_pd_mcu(void);
diff --git a/board/fizz/build.mk b/board/fizz/build.mk
index 74094ac834..b07b1b4cf3 100644
--- a/board/fizz/build.mk
+++ b/board/fizz/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -10,5 +10,5 @@ CHIP:=npcx
 CHIP_VARIANT:=npcx5m6g
 
 board-y=board.o
-board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
+board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o usb_pd_pdo.o
 board-y+=led.o
diff --git a/board/fizz/ec.tasklist b/board/fizz/ec.tasklist
index 75a09a43df..6212516e6a 100644
--- a/board/fizz/ec.tasklist
+++ b/board/fizz/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/fizz/gpio.inc b/board/fizz/gpio.inc
index 7da0bfce71..2eee02bfd3 100644
--- a/board/fizz/gpio.inc
+++ b/board/fizz/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,10 +13,10 @@ GPIO_INT(AC_PRESENT,		PIN(C, 1), GPIO_INT_BOTH,			extpower_interrupt)
 GPIO_INT(POWER_BUTTON_L,	PIN(0, 4), GPIO_INT_BOTH | GPIO_PULL_UP,	power_button_interrupt)	/* MECH_PWR_BTN_ODL */
 
 GPIO_INT(PCH_SLP_S0_L,		PIN(7, 5), GPIO_INT_BOTH,			power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(PCH_SLP_S3_L,		PIN(7, 3), GPIO_INT_BOTH,			power_signal_interrupt)
 #endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 GPIO_INT(PCH_SLP_S4_L,		PIN(8, 6), GPIO_INT_BOTH,			power_signal_interrupt)
 #endif
 GPIO_INT(PCH_SLP_SUS_L,		PIN(6, 2), GPIO_INT_BOTH,			power_signal_interrupt)
diff --git a/board/fizz/led.c b/board/fizz/led.c
index 9b6942d241..acd0eb5918 100644
--- a/board/fizz/led.c
+++ b/board/fizz/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -15,7 +15,7 @@
 #include "timer.h"
 #include "util.h"
 
-const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 enum led_color {
@@ -76,9 +76,9 @@ static int set_color(enum ec_led_id id, enum led_color color, int duty)
 	}
 }
 
-#define LED_PULSE_US		(2 * SECOND)
+#define LED_PULSE_US (2 * SECOND)
 /* 40 msec for nice and smooth transition. */
-#define LED_PULSE_TICK_US	(40 * MSEC)
+#define LED_PULSE_TICK_US (40 * MSEC)
 
 /* When pulsing is enabled, brightness is incremented by <duty_inc> every
  * <interval> usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented
@@ -181,7 +181,7 @@ void led_critical(void)
 		set_color(EC_LED_ID_POWER_LED, LED_RED, 100);
 }
 
-static int command_led(int argc, char **argv)
+static int command_led(int argc, const char **argv)
 {
 	enum ec_led_id id = EC_LED_ID_POWER_LED;
 
diff --git a/board/fizz/usb_pd_pdo.c b/board/fizz/usb_pd_pdo.c
new file mode 100644
index 0000000000..edcc43f15a
--- /dev/null
+++ b/board/fizz/usb_pd_pdo.c
@@ -0,0 +1,23 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "compile_time_macros.h"
+#include "usb_pd.h"
+#include "usb_pd_pdo.h"
+
+#define PDO_FIXED_FLAGS \
+	(PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP | PDO_FIXED_COMM_CAP)
+
+const uint32_t pd_src_pdo[] = {
+	PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS),
+};
+const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
+
+const uint32_t pd_snk_pdo[] = {
+	PDO_FIXED(5000, 500, PDO_FIXED_FLAGS),
+	PDO_BATT(4750, 21000, 50000),
+	PDO_VAR(4750, 21000, 3000),
+};
+const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
diff --git a/board/fizz/usb_pd_pdo.h b/board/fizz/usb_pd_pdo.h
new file mode 100644
index 0000000000..97ee437a3f
--- /dev/null
+++ b/board/fizz/usb_pd_pdo.h
@@ -0,0 +1,17 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_BOARD_FIZZ_USB_PD_PDO_H
+#define __CROS_EC_BOARD_FIZZ_USB_PD_PDO_H
+
+#include "stdint.h"
+
+extern const uint32_t pd_src_pdo[1];
+extern const int pd_src_pdo_cnt;
+
+extern const uint32_t pd_snk_pdo[3];
+extern const int pd_snk_pdo_cnt;
+
+#endif /* __CROS_EC_BOARD_FIZZ_USB_PD_PDO_H */
diff --git a/board/fizz/usb_pd_policy.c b/board/fizz/usb_pd_policy.c
index 5de57f3c9b..1d96c40a04 100644
--- a/board/fizz/usb_pd_policy.c
+++ b/board/fizz/usb_pd_policy.c
@@ -1,15 +1,15 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "atomic.h"
-#include "extpower.h"
 #include "charge_manager.h"
 #include "common.h"
 #include "console.h"
 #include "driver/tcpm/anx74xx.h"
 #include "driver/tcpm/ps8xxx.h"
+#include "extpower.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "host_command.h"
@@ -17,28 +17,14 @@
 #include "system.h"
 #include "task.h"
 #include "timer.h"
-#include "util.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
+#include "usb_pd_pdo.h"
 #include "usb_pd_tcpm.h"
+#include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\
-			 PDO_FIXED_COMM_CAP)
-
-const uint32_t pd_src_pdo[] = {
-	PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS),
-};
-const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
-
-const uint32_t pd_snk_pdo[] = {
-	PDO_FIXED(5000, 500, PDO_FIXED_FLAGS),
-	PDO_BATT(4750, 21000, 50000),
-	PDO_VAR(4750, 21000, 3000),
-};
-const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int board_vbus_source_enabled(int port)
 {
@@ -75,19 +61,6 @@ int pd_snk_is_vbus_provided(int port)
 	return !gpio_get_level(GPIO_USB_C0_VBUS_WAKE_L);
 }
 
-__override int pd_check_power_swap(int port)
-{
-	/* If type-c port is supplying power, we never swap PR (to source) */
-	if (port == charge_manager_get_active_charge_port())
-		return 0;
-	/*
-	 * Allow power swap as long as we are acting as a dual role device,
-	 * otherwise assume our role is fixed (not in S0 or console command
-	 * to fix our role).
-	 */
-	return pd_get_dual_role(port) == PD_DRP_TOGGLE_ON ? 1 : 0;
-}
-
 int pd_check_vconn_swap(int port)
 {
 	/* in G3, do not allow vconn swap since pp5000_A rail is off */
diff --git a/board/fizz/vif_override.xml b/board/fizz/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/fizz/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/flapjack/battery.c b/board/flapjack/battery.c
deleted file mode 100644
index 981edea013..0000000000
--- a/board/flapjack/battery.c
+++ /dev/null
@@ -1,468 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery.h"
-#include "battery_smart.h"
-#include "charge_state.h"
-#include "console.h"
-#include "driver/battery/max17055.h"
-#include "driver/charger/rt946x.h"
-#include "driver/tcpm/mt6370.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "usb_pd.h"
-#include "util.h"
-#include "board.h"
-#include "adc.h"
-#include "adc_chip.h"
-#include "math_util.h"
-#include "p9221.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#define BAT_LEVEL_PD_LIMIT 85
-
-#define BATTERY_ATL_CHARGE_MIN_TEMP 0
-#define BATTERY_ATL_CHARGE_MAX_TEMP 60
-
-#define BATTERY_SUNWODA_CHARGE_MIN_TEMP 0
-#define BATTERY_SUNWODA_CHARGE_MAX_TEMP 60
-
-static const uint16_t full_model_ocv_table[][MAX17055_OCV_TABLE_SIZE] = {
-	[BATTERY_C18_ATL] = {
-		0x8fc0, 0xb6c0, 0xb910, 0xbb30, 0xbcb0, 0xbdd0, 0xbef0, 0xc050,
-		0xc1a0, 0xc460, 0xc750, 0xca40, 0xcd10, 0xd070, 0xd560, 0xda20,
-		0x0060, 0x0f20, 0x0f40, 0x16c0, 0x17f0, 0x15c0, 0x1050, 0x10e0,
-		0x09f0, 0x0850, 0x0730, 0x07a0, 0x0730, 0x0700, 0x0710, 0x0710,
-		0x0800, 0x0800, 0x0800, 0x0800, 0x0800, 0x0800, 0x0800, 0x0800,
-		0x0800, 0x0800, 0x0800, 0x0800, 0x0800, 0x0800, 0x0800, 0x0800,
-	},
-	[BATTERY_C19_ATL] = {
-		0xa260, 0xb5d0, 0xb840, 0xb940, 0xbbb0, 0xbcb0, 0xbdb0, 0xbf80,
-		0xc0a0, 0xc1e0, 0xc520, 0xc840, 0xcdb0, 0xd150, 0xd590, 0xd9e0,
-		0x0030, 0x0cd0, 0x1100, 0x0f30, 0x19e0, 0x19f0, 0x14f0, 0x1160,
-		0x0dc0, 0x0980, 0x0850, 0x0780, 0x0730, 0x0700, 0x0710, 0x0710,
-		0x0800, 0x0800, 0x0800, 0x0800, 0x0800, 0x0800, 0x0800, 0x0800,
-		0x0800, 0x0800, 0x0800, 0x0800, 0x0800, 0x0800, 0x0800, 0x0800,
-	},
-	[BATTERY_C18_SUNWODA] = {
-		0x9d70, 0xaf80, 0xb6b0, 0xb830, 0xb990, 0xbc00, 0xbcd0, 0xbea0,
-		0xc080, 0xc2e0, 0xc5f0, 0xc890, 0xcb90, 0xcf10, 0xd270, 0xd9e0,
-		0x0060, 0x0240, 0x0b20, 0x1210, 0x0f20, 0x2200, 0x1650, 0x14f0,
-		0x0980, 0x09c0, 0x07b0, 0x07f0, 0x06f0, 0x07e0, 0x05c0, 0x05c0,
-		0x0400, 0x0400, 0x0400, 0x0400, 0x0400, 0x0400, 0x0400, 0x0400,
-		0x0400, 0x0400, 0x0400, 0x0400, 0x0400, 0x0400, 0x0400, 0x0400,
-	},
-	[BATTERY_C19_SUNWODA] = {
-		0x8590, 0xb1d0, 0xb810, 0xbae0, 0xbc30, 0xbd70, 0xbeb0, 0xbfa0,
-		0xc0f0, 0xc330, 0xc640, 0xc890, 0xcb50, 0xce20, 0xd370, 0xd950,
-		0x0020, 0x0520, 0x0d80, 0x1860, 0x1910, 0x2040, 0x0be0, 0x0dd0,
-		0x0cb0, 0x07b0, 0x08f0, 0x07c0, 0x0790, 0x06e0, 0x0620, 0x0620,
-		0x0400, 0x0400, 0x0400, 0x0400, 0x0400, 0x0400, 0x0400, 0x0400,
-		0x0400, 0x0400, 0x0400, 0x0400, 0x0400, 0x0400, 0x0400, 0x0400,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(full_model_ocv_table) == BATTERY_COUNT);
-
-/*
- * TODO: Only precharge_current is different. We should consolidate these
- * and apply 294 or 327 at run-time.when we need more rom space later.
- */
-static const struct battery_info info[] = {
-	[BATTERY_C18_ATL] = {
-		.voltage_max		= 4400,
-		.voltage_normal		= 3850,
-		.voltage_min		= 3000,
-		.precharge_current	= 294,
-		.start_charging_min_c	= 0,
-		.start_charging_max_c	= 45,
-		.charging_min_c		= 0,
-		.charging_max_c		= 60,
-		.discharging_min_c	= -20,
-		.discharging_max_c	= 60,
-	},
-	[BATTERY_C19_ATL] = {
-		.voltage_max		= 4400,
-		.voltage_normal		= 3850,
-		.voltage_min		= 3000,
-		.precharge_current	= 327,
-		.start_charging_min_c	= 0,
-		.start_charging_max_c	= 45,
-		.charging_min_c		= 0,
-		.charging_max_c		= 60,
-		.discharging_min_c	= -20,
-		.discharging_max_c	= 60,
-	},
-	[BATTERY_C18_SUNWODA] = {
-		.voltage_max		= 4400,
-		.voltage_normal		= 3850,
-		.voltage_min		= 3000,
-		.precharge_current	= 294,
-		.start_charging_min_c	= 0,
-		.start_charging_max_c	= 45,
-		.charging_min_c		= 0,
-		.charging_max_c		= 60,
-		.discharging_min_c	= -20,
-		.discharging_max_c	= 60,
-	},
-	[BATTERY_C19_SUNWODA] = {
-		.voltage_max		= 4400,
-		.voltage_normal		= 3850,
-		.voltage_min		= 3000,
-		.precharge_current	= 327,
-		.start_charging_min_c	= 0,
-		.start_charging_max_c	= 45,
-		.charging_min_c		= 0,
-		.charging_max_c		= 60,
-		.discharging_min_c	= -20,
-		.discharging_max_c	= 60,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(info) == BATTERY_COUNT);
-
-static const struct max17055_batt_profile batt_profile[] = {
-	[BATTERY_C18_ATL] = {
-		.is_ez_config		= 0,
-		.design_cap		= 0x2e78, /* 5948mAh */
-		.ichg_term		= 0x03c0, /* 150 mA */
-		/* Empty voltage = 3400mV, Recovery voltage = 4000mV */
-		.v_empty_detect		= 0xaa64,
-		.learn_cfg		= 0x4402,
-		.dpacc			= 0x0c7d,
-		.rcomp0			= 0x0011,
-		.tempco			= 0x0209,
-		.qr_table00		= 0x5a00,
-		.qr_table10		= 0x2980,
-		.qr_table20		= 0x1100,
-		.qr_table30		= 0x1000,
-		.ocv_table		= full_model_ocv_table[BATTERY_C18_ATL],
-	},
-	[BATTERY_C19_ATL] = {
-		.is_ez_config		= 0,
-		.design_cap		= 0x3407, /* 6659mAh */
-		.ichg_term		= 0x03c0, /* 150 mA */
-		/* Empty voltage = 3400mV, Recovery voltage = 4000mV */
-		.v_empty_detect		= 0xaa64,
-		.learn_cfg		= 0x4402,
-		.dpacc			= 0x0c7e,
-		.rcomp0			= 0x000f,
-		.tempco			= 0x000b,
-		.qr_table00		= 0x5800,
-		.qr_table10		= 0x2680,
-		.qr_table20		= 0x0d00,
-		.qr_table30		= 0x0b00,
-		.ocv_table		= full_model_ocv_table[BATTERY_C19_ATL],
-	},
-	[BATTERY_C18_SUNWODA] = {
-		.is_ez_config		= 0,
-		.design_cap		= 0x2fcc, /* 6118mAh */
-		.ichg_term		= 0x03c0, /* 150 mA */
-		/* Empty voltage = 3400mV, Recovery voltage = 4000mV */
-		.v_empty_detect		= 0xaa64,
-		.learn_cfg		= 0x4402,
-		.dpacc			= 0x0c7c,
-		.rcomp0			= 0x0024,
-		.tempco			= 0x0c1f,
-		.qr_table00		= 0x9f00,
-		.qr_table10		= 0x4480,
-		.qr_table20		= 0x1600,
-		.qr_table30		= 0x1400,
-		.ocv_table	= full_model_ocv_table[BATTERY_C18_SUNWODA],
-	},
-	[BATTERY_C19_SUNWODA] = {
-		.is_ez_config		= 0,
-		.design_cap		= 0x34b1, /* 6744mAh */
-		.ichg_term		= 0x03c0, /* 150 mA */
-		/* Empty voltage = 3400mV, Recovery voltage = 4000mV */
-		.v_empty_detect		= 0xaa64,
-		.learn_cfg		= 0x4402,
-		.dpacc			= 0x0c80,
-		.rcomp0			= 0x001f,
-		.tempco			= 0x051f,
-		.qr_table00		= 0x9100,
-		.qr_table10		= 0x3d00,
-		.qr_table20		= 0x1200,
-		.qr_table30		= 0x1002,
-		.ocv_table	= full_model_ocv_table[BATTERY_C19_SUNWODA],
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(batt_profile) == BATTERY_COUNT);
-
-static const struct max17055_alert_profile alert_profile[] = {
-	[BATTERY_C18_ATL] = {
-		.v_alert_mxmn = VALRT_DISABLE,
-		.t_alert_mxmn = MAX17055_TALRTTH_REG(
-			BATTERY_ATL_CHARGE_MAX_TEMP,
-			BATTERY_ATL_CHARGE_MIN_TEMP),
-		.s_alert_mxmn = SALRT_DISABLE,
-		.i_alert_mxmn = IALRT_DISABLE,
-	},
-	[BATTERY_C19_ATL] = {
-		.v_alert_mxmn = VALRT_DISABLE,
-		.t_alert_mxmn = MAX17055_TALRTTH_REG(
-			BATTERY_ATL_CHARGE_MAX_TEMP,
-			BATTERY_ATL_CHARGE_MIN_TEMP),
-		.s_alert_mxmn = SALRT_DISABLE,
-		.i_alert_mxmn = IALRT_DISABLE,
-	},
-	[BATTERY_C18_SUNWODA] = {
-		.v_alert_mxmn = VALRT_DISABLE,
-		.t_alert_mxmn = MAX17055_TALRTTH_REG(
-			BATTERY_SUNWODA_CHARGE_MIN_TEMP,
-			BATTERY_SUNWODA_CHARGE_MAX_TEMP),
-		.s_alert_mxmn = SALRT_DISABLE,
-		.i_alert_mxmn = IALRT_DISABLE,
-	},
-	[BATTERY_C19_SUNWODA] = {
-		.v_alert_mxmn = VALRT_DISABLE,
-		.t_alert_mxmn = MAX17055_TALRTTH_REG(
-			BATTERY_SUNWODA_CHARGE_MIN_TEMP,
-			BATTERY_SUNWODA_CHARGE_MAX_TEMP),
-		.s_alert_mxmn = SALRT_DISABLE,
-		.i_alert_mxmn = IALRT_DISABLE,
-	},
-
-};
-BUILD_ASSERT(ARRAY_SIZE(alert_profile) == BATTERY_COUNT);
-
-enum temp_zone {
-	TEMP_ZONE_0, /* t0 <= bat_temp_c < t1  */
-	TEMP_ZONE_1, /* t1 <= bat_temp_c < t2 */
-	TEMP_ZONE_2, /* t2 <= bat_temp_c < t3 */
-	TEMP_ZONE_3, /* t3 <= bat_temp_c < t4 */
-	TEMP_ZONE_COUNT,
-	TEMP_OUT_OF_RANGE = TEMP_ZONE_COUNT,
-};
-
-/*
- * TODO: Many value in temp_zones are pretty similar, we should consolidate
- * these and modify the value when we need more rom space later.
- */
-static const struct {
-	int temp_min; /* 0.1 deg C */
-	int temp_max; /* 0.1 deg C */
-	int desired_current; /* mA */
-	int desired_voltage; /* mV */
-} temp_zones[BATTERY_COUNT][TEMP_ZONE_COUNT] = {
-	[BATTERY_C18_ATL] = {
-		{BATTERY_ATL_CHARGE_MIN_TEMP * 10, 100, 1170, 4400},
-		{100, 200, 1755, 4400},
-		{200, 450, 2925, 4400},
-		{450, BATTERY_ATL_CHARGE_MAX_TEMP * 10, 2925, 4100},
-	},
-	[BATTERY_C19_ATL] = {
-		{BATTERY_ATL_CHARGE_MIN_TEMP * 10, 100, 1300, 4400},
-		{100, 200, 1950, 4400},
-		{200, 450, 3250, 4400},
-		{450, BATTERY_ATL_CHARGE_MAX_TEMP * 10, 3250, 4100},
-	},
-	[BATTERY_C18_SUNWODA] = {
-		{BATTERY_SUNWODA_CHARGE_MIN_TEMP * 10, 100, 1170, 4400},
-		{100, 200, 1755, 4400},
-		{200, 450, 2925, 4400},
-		{450, BATTERY_SUNWODA_CHARGE_MAX_TEMP * 10, 2925, 4100},
-	},
-	[BATTERY_C19_SUNWODA] = {
-		{BATTERY_SUNWODA_CHARGE_MIN_TEMP * 10, 100, 1300, 4400},
-		{100, 200, 1950, 4400},
-		{200, 450, 3250, 4400},
-		{450, BATTERY_SUNWODA_CHARGE_MAX_TEMP * 10, 3250, 4100},
-	},
-};
-
-/* BOARD_VERSION < 5: Pull-up = 1800 mV. */
-static const struct mv_to_id batteries0[] = {
-	{ BATTERY_C18_ATL,	900 },   /* 100K ohm */
-	{ BATTERY_C19_ATL,	576 },   /*  47K ohm */
-	{ BATTERY_C18_SUNWODA,	1484 },   /* 470K ohm */
-	{ BATTERY_C19_SUNWODA,	1200 },   /* 200K ohm */
-};
-BUILD_ASSERT(ARRAY_SIZE(batteries0) < BATTERY_COUNT);
-
-/* BOARD_VERSION >= 5: Pull-up = 3300 mV. */
-static const struct mv_to_id batteries1[] = {
-	{ BATTERY_C18_ATL,	1650 },   /* 100K ohm */
-	{ BATTERY_C19_ATL,	1055 },   /*  47K ohm */
-	{ BATTERY_C18_SUNWODA,	2721 },   /* 470K ohm */
-	{ BATTERY_C19_SUNWODA,	2200 },   /* 200K ohm */
-};
-BUILD_ASSERT(ARRAY_SIZE(batteries1) < BATTERY_COUNT);
-
-static enum battery_type batt_type = BATTERY_UNKNOWN;
-
-static void board_get_battery_type(void)
-{
-	const struct mv_to_id *table = batteries0;
-	int size = ARRAY_SIZE(batteries0);
-	int id;
-
-	if (board_version >= 5) {
-		table = batteries1;
-		size = ARRAY_SIZE(batteries1);
-	}
-	id = board_read_id(ADC_BATT_ID, table, size);
-	if (id != ADC_READ_ERROR)
-		batt_type = id;
-	CPRINTS("Battery Type: %d", batt_type);
-}
-/* It has to run after BOARD_VERSION is read */
-DECLARE_HOOK(HOOK_INIT, board_get_battery_type, HOOK_PRIO_INIT_I2C + 2);
-
-const struct battery_info *battery_get_info(void)
-{
-	return &info[batt_type];
-}
-
-const struct max17055_batt_profile *max17055_get_batt_profile(void)
-{
-	return &batt_profile[batt_type];
-}
-
-const struct max17055_alert_profile *max17055_get_alert_profile(void)
-{
-	return &alert_profile[batt_type];
-}
-
-int get_battery_manufacturer_name(char *dest, int size)
-{
-	static const char * const name[] = {
-		[BATTERY_UNKNOWN] = "UNKNOWN",
-		[BATTERY_C18_ATL] = "C18_ATL",
-		[BATTERY_C19_ATL] = "C19_ATL",
-		[BATTERY_C18_SUNWODA] = "C18_SWD",
-		[BATTERY_C19_SUNWODA] = "C19_SWD",
-	};
-	ASSERT(dest);
-	strzcpy(dest, name[batt_type], size);
-	return EC_SUCCESS;
-}
-
-int board_cut_off_battery(void)
-{
-	/* The cut-off procedure is recommended by Richtek. b/116682788 */
-	rt946x_por_reset();
-	mt6370_vconn_discharge(0);
-	rt946x_cutoff_battery();
-
-	return EC_SUCCESS;
-}
-
-enum battery_disconnect_state battery_get_disconnect_state(void)
-{
-	if (battery_is_present() == BP_YES)
-		return BATTERY_NOT_DISCONNECTED;
-	return BATTERY_DISCONNECTED;
-}
-
-int charger_profile_override(struct charge_state_data *curr)
-{
-	/* battery temp in 0.1 deg C */
-	int temp = curr->batt.temperature - 2731;
-	enum temp_zone zone;
-	int usb_mv, wpc_mv;
-	static int previous_usb_mv;
-	int val;
-
-	if (curr->state != ST_CHARGE)
-		return 0;
-
-	/* Limit input (=VBUS) to 5V when soc > 85% and charge current < 1A. */
-	if (!(curr->batt.flags & BATT_FLAG_BAD_CURRENT) &&
-			charge_get_percent() > BAT_LEVEL_PD_LIMIT &&
-			curr->batt.current < 1000 &&
-			curr->batt.current > 0) {
-		usb_mv = 5500;
-		wpc_mv = 5500;
-	} else {
-		usb_mv = PD_MAX_VOLTAGE_MV;
-		wpc_mv = P9221_DC_IVL_EPP_MV;
-	}
-
-	if (usb_mv != previous_usb_mv)
-		CPRINTS("VBUS limited to %dmV", usb_mv);
-	previous_usb_mv = usb_mv;
-
-	/* Pull down USB VBUS */
-	if (pd_get_max_voltage() != usb_mv)
-		pd_set_external_voltage_limit(0, usb_mv);
-
-	/*
-	 * Pull down WPC VBUS. Need to use raw i2c APIs because RO
-	 * doesn't have p9221 driver. If WPC is off, this is a no-op.
-	 */
-	if (i2c_read_offset16(I2C_PORT_WPC, P9221_R7_ADDR_FLAGS,
-			      P9221R7_VOUT_SET_REG, &val, 1) == EC_SUCCESS
-			&& val * 100 != wpc_mv)
-		i2c_write_offset16(I2C_PORT_WPC, P9221_R7_ADDR_FLAGS,
-			      P9221R7_VOUT_SET_REG, wpc_mv / 100, 1);
-
-	if ((curr->batt.flags & BATT_FLAG_BAD_TEMPERATURE) ||
-	    (temp < temp_zones[batt_type][TEMP_ZONE_0].temp_min)) {
-		zone = TEMP_OUT_OF_RANGE;
-	} else {
-		for (zone = TEMP_ZONE_0; zone < TEMP_ZONE_COUNT; zone++) {
-			if (temp < temp_zones[batt_type][zone].temp_max)
-				break;
-		}
-	}
-
-	if (zone == TEMP_OUT_OF_RANGE || zone >= TEMP_ZONE_COUNT) {
-		curr->requested_current = curr->requested_voltage = 0;
-		curr->batt.flags &= ~BATT_FLAG_WANT_CHARGE;
-		curr->state = ST_IDLE;
-	} else {
-		curr->requested_current =
-			temp_zones[batt_type][zone].desired_current;
-		curr->requested_voltage =
-			temp_zones[batt_type][zone].desired_voltage;
-	}
-
-	/*
-	 * When the charger says it's done charging, even if fuel gauge says
-	 * SOC < BATTERY_LEVEL_NEAR_FULL, we'll overwrite SOC with
-	 * BATTERY_LEVEL_NEAR_FULL. So we can ensure both Chrome OS UI
-	 * and battery LED indicate full charge.
-	 */
-	if (rt946x_is_charge_done()) {
-		curr->batt.state_of_charge = MAX(BATTERY_LEVEL_NEAR_FULL,
-						 curr->batt.state_of_charge);
-	}
-
-	return 0;
-}
-
-static void board_charge_termination(void)
-{
-	static uint8_t te;
-	/* Enable charge termination when we are sure battery is present. */
-	if (!te && battery_is_present() == BP_YES) {
-		if (!rt946x_enable_charge_termination(1))
-			te = 1;
-	}
-}
-DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE,
-	     board_charge_termination,
-	     HOOK_PRIO_DEFAULT);
-
-/* Customs options controllable by host command. */
-#define PARAM_FASTCHARGE (CS_PARAM_CUSTOM_PROFILE_MIN + 0)
-
-enum ec_status charger_profile_override_get_param(uint32_t param,
-						  uint32_t *value)
-{
-	return EC_RES_INVALID_PARAM;
-}
-
-enum ec_status charger_profile_override_set_param(uint32_t param,
-						  uint32_t value)
-{
-	return EC_RES_INVALID_PARAM;
-}
diff --git a/board/flapjack/board.c b/board/flapjack/board.c
deleted file mode 100644
index 065df1edf9..0000000000
--- a/board/flapjack/board.c
+++ /dev/null
@@ -1,639 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "adc_chip.h"
-#include "backlight.h"
-#include "board.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/als_tcs3400.h"
-#include "driver/battery/max17055.h"
-#include "driver/charger/rt946x.h"
-#include "driver/sync.h"
-#include "driver/tcpm/mt6370.h"
-#include "driver/temp_sensor/tmp432.h"
-#include "driver/wpc/p9221.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "power.h"
-#include "power_button.h"
-#include "lid_switch.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "spi.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "tcpm.h"
-#include "temp_sensor.h"
-#include "temp_sensor_chip.h"
-#include "thermal.h"
-#include "timer.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-/* LCM_ID is embedded in SKU_ID bit[19-16] */
-#define SKU_ID_TO_LCM_ID(x)	(((x) >> PANEL_ID_BIT_POSITION) & 0xf)
-#define LCM_ID_TO_SKU_ID(x)	(((x) & 0xf) << PANEL_ID_BIT_POSITION)
-
-/* BOARD_VERSION < 5: Pull-up = 1800 mV. */
-static const struct mv_to_id panels0[] = {
-	{ PANEL_BOE_TV101WUM_NG0,	74 },	/* 2.2 kohm */
-	{ PANEL_BOE_TV080WUM_NG0,	212 },	/* 6.8 kohm */
-	{ PANEL_STA_10P,		1191 },	/* 100 kohm */
-	{ PANEL_STA_08P,		1028 },	/* 68 kohm */
-};
-BUILD_ASSERT(ARRAY_SIZE(panels0) < PANEL_COUNT);
-
-/* BOARD_VERSION >= 5: Pull-up = 3300 mV. */
-static const struct mv_to_id panels1[] = {
-	{ PANEL_BOE_TV101WUM_NG0,	136 },	/* 2.2 kohm */
-	{ PANEL_BOE_TV080WUM_NG0,	387 },	/* 6.8 kohm */
-	{ PANEL_STA_10P,		2184 },	/* 100 kohm */
-	{ PANEL_STA_08P,		1884 },	/* 68 kohm */
-};
-BUILD_ASSERT(ARRAY_SIZE(panels1) < PANEL_COUNT);
-
-BUILD_ASSERT(PANEL_COUNT <= PANEL_UNINITIALIZED);
-
-uint8_t board_version;
-uint8_t oem;
-uint32_t sku = LCM_ID_TO_SKU_ID(PANEL_UNINITIALIZED);
-
-static const struct rt946x_init_setting battery_init_setting = {
-	.eoc_current = 150,
-	.mivr = 4000,
-	.ircmp_vclamp = 32,
-	.ircmp_res = 25,
-	.boost_voltage = 5050,
-	.boost_current = 1500,
-};
-
-int board_read_id(enum adc_channel ch, const struct mv_to_id *table, int size)
-{
-	int mv = adc_read_channel(ch);
-	int i;
-
-	if (mv == ADC_READ_ERROR)
-		mv = adc_read_channel(ch);
-
-	for (i = 0; i < size; i++) {
-		if (ABS(mv - table[i].median_mv) < ADC_MARGIN_MV)
-			return table[i].id;
-	}
-
-	return ADC_READ_ERROR;
-}
-
-const struct rt946x_init_setting *board_rt946x_init_setting(void)
-{
-	return &battery_init_setting;
-}
-
-static void board_setup_panel(void)
-{
-	uint8_t channel;
-	uint8_t dim;
-	int rv = 0;
-
-	if (board_version >= 3) {
-		switch (SKU_ID_TO_LCM_ID(sku)) {
-		case PANEL_BOE_TV080WUM_NG0:
-		case PANEL_STA_08P:
-			channel = 0xfa;
-			dim = 0xc8;
-			break;
-		case PANEL_BOE_TV101WUM_NG0:
-		case PANEL_STA_10P:
-			channel = 0xfe;
-			dim = 0xc4;
-			break;
-		default:
-			return;
-		}
-	} else {
-		/* TODO: to be removed once the boards are deprecated. */
-		channel = sku & SKU_ID_PANEL_SIZE_MASK ? 0xfe : 0xfa;
-		dim = sku & SKU_ID_PANEL_SIZE_MASK ? 0xc4 : 0xc8;
-	}
-
-	rv |= i2c_write8(I2C_PORT_CHARGER, RT946X_ADDR_FLAGS,
-			 MT6370_BACKLIGHT_BLEN, channel);
-	rv |= i2c_write8(I2C_PORT_CHARGER, RT946X_ADDR_FLAGS,
-			 MT6370_BACKLIGHT_BLDIM, dim);
-	rv |= i2c_write8(I2C_PORT_CHARGER, RT946X_ADDR_FLAGS,
-			 MT6370_BACKLIGHT_BLPWM, 0xac);
-	if (rv)
-		CPRINTS("Board setup panel failed");
-}
-
-static enum panel_id board_get_panel_id(void)
-{
-	enum panel_id id;
-
-	if (board_version < 3) {
-		id = PANEL_DEFAULT; /* No LCM_ID. */
-	} else {
-		const struct mv_to_id *table = panels0;
-		int size = ARRAY_SIZE(panels0);
-		if (board_version >= 5) {
-			table = panels1;
-			size = ARRAY_SIZE(panels1);
-		}
-		id  = board_read_id(ADC_LCM_ID, table, size);
-		if (id < PANEL_DEFAULT || PANEL_COUNT <= id)
-			id = PANEL_DEFAULT;
-	}
-	CPRINTS("LCM ID: %d", id);
-	return id;
-}
-
-#define CBI_SKU_ID_SIZE 4
-
-int cbi_board_override(enum cbi_data_tag tag, uint8_t *buf, uint8_t *size)
-{
-	switch (tag) {
-	case CBI_TAG_SKU_ID:
-		if (*size != CBI_SKU_ID_SIZE)
-			/* For old boards (board_version < 3) */
-			return EC_SUCCESS;
-		if (SKU_ID_TO_LCM_ID(sku) == PANEL_UNINITIALIZED)
-			/* Haven't read LCM_ID */
-			return EC_ERROR_BUSY;
-		buf[PANEL_ID_BIT_POSITION / 8] = SKU_ID_TO_LCM_ID(sku);
-		break;
-	default:
-		break;
-	}
-	return EC_SUCCESS;
-}
-
-static void cbi_init(void)
-{
-	uint32_t val;
-
-	if (cbi_get_board_version(&val) == EC_SUCCESS && val <= UINT8_MAX)
-		board_version = val;
-	CPRINTS("Board Version: 0x%02x", board_version);
-
-	if (cbi_get_oem_id(&val) == EC_SUCCESS && val <= PROJECT_COUNT)
-		oem = val;
-	CPRINTS("OEM: %d", oem);
-
-	sku = LCM_ID_TO_SKU_ID(board_get_panel_id());
-
-	if (cbi_get_sku_id(&val) == EC_SUCCESS)
-		sku = val;
-
-	CPRINTS("SKU: 0x%08x", sku);
-}
-DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1);
-
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	schedule_deferred_pd_interrupt(0 /* port */);
-}
-
-static void gauge_interrupt(enum gpio_signal signal)
-{
-	task_wake(TASK_ID_CHARGER);
-}
-
-#include "gpio_list.h"
-
-/******************************************************************************/
-/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
-const struct adc_t adc_channels[] = {
-	[ADC_LCM_ID] = {"LCM_ID", 3300, 4096, 0, STM32_AIN(10)},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)},
-	[ADC_BATT_ID] = {"BATT_ID", 3300, 4096, 0, STM32_AIN(7)},
-	[ADC_USBC_THERM] = {"USBC_THERM", 3300, 4096, 0, STM32_AIN(14),
-		STM32_ADC_SMPR_239_5_CY},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/******************************************************************************/
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"charger",   I2C_PORT_CHARGER,   400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"tcpc0",     I2C_PORT_TCPC0,     400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"als",       I2C_PORT_ALS,       400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"battery",   I2C_PORT_BATTERY,   400, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-	{"accelgyro", I2C_PORT_ACCEL,     400, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-	{"eeprom",    I2C_PORT_EEPROM,    400, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/******************************************************************************/
-/* Charger Chips */
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = RT946X_ADDR_FLAGS,
-		.drv = &rt946x_drv,
-	},
-};
-
-/* power signal list.  Must match order of enum power_signal. */
-const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-#ifdef CONFIG_TEMP_SENSOR_TMP432
-/* Temperature sensors data; must be in same order as enum temp_sensor_id. */
-const struct temp_sensor_t temp_sensors[] = {
-	{"TMP432_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-		TMP432_IDX_LOCAL, 4},
-	{"TMP432_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-		TMP432_IDX_REMOTE1, 4},
-	{"TMP432_Sensor_2", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-		TMP432_IDX_REMOTE2, 4},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/*
- * Thermal limits for each temp sensor. All temps are in degrees K. Must be in
- * same order as enum temp_sensor_id. To always ignore any temp, use 0.
- */
-struct ec_thermal_config thermal_params[] = {
-	{{0, 0, 0}, 0, 0}, /* TMP432_Internal */
-	{{0, 0, 0}, 0, 0}, /* TMP432_Sensor_1 */
-	{{0, 0, 0}, 0, 0}, /* TMP432_Sensor_2 */
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-#endif
-
-/******************************************************************************/
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-/******************************************************************************/
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = MT6370_TCPC_I2C_ADDR_FLAGS,
-		},
-		.drv = &mt6370_tcpm_drv},
-};
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-	},
-};
-
-void board_reset_pd_mcu(void)
-{
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_0;
-
-	return status;
-}
-
-int board_set_active_charge_port(int charge_port)
-{
-	CPRINTS("New chg p%d", charge_port);
-
-	switch (charge_port) {
-	case 0:
-		/* Don't charge from a source port except wireless charging*/
-#ifdef CONFIG_WIRELESS_CHARGER_P9221_R7
-		if (board_vbus_source_enabled(charge_port)
-			&& !wpc_chip_is_online())
-#else
-		if (board_vbus_source_enabled(charge_port))
-#endif
-			return -1;
-		break;
-	case CHARGE_PORT_NONE:
-		/*
-		 * To ensure the fuel gauge (max17055) is always powered
-		 * even when battery is disconnected, keep VBAT rail on but
-		 * set the charging current to minimum.
-		 */
-		charger_set_current(CHARGER_SOLO, 0);
-		break;
-	default:
-		panic("Invalid charge port\n");
-		break;
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_set_input_current_limit(MAX(charge_ma,
-			       CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
-
-int extpower_is_present(void)
-{
-	return tcpm_check_vbus_level(0, VBUS_PRESENT);
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	if (port)
-		panic("Invalid charge port\n");
-
-	return rt946x_is_vbus_ready();
-}
-
-/*
- * Threshold to detect USB-C board. If the USB-C board isn't connected,
- * USBC_THERM is floating thus the ADC pin should read about the pull-up
- * voltage. If it's connected, the voltage is capped by the resistor (429k)
- * place in parallel to the thermistor. 3.3V x 429k/(39k + 429k) = 3.025V
- */
-#define USBC_THERM_THRESHOLD 3025
-
-static void board_init(void)
-{
-#ifdef SECTION_IS_RO
-	/* If USB-C board isn't connected, the device is being assembled.
-	 * We cut off the battery until the assembly is done for better yield.
-	 * Timing is ok because STM32F0 initializes ADC on demand. */
-	if (board_version > 0x02) {
-		int mv = adc_read_channel(ADC_USBC_THERM);
-		if (mv == ADC_READ_ERROR)
-			mv = adc_read_channel(ADC_USBC_THERM);
-		CPRINTS("USBC_THERM=%d", mv);
-		if (mv > USBC_THERM_THRESHOLD) {
-			cflush();
-			board_cut_off_battery();
-		}
-	}
-#endif
-	/* Set SPI1 PB13/14/15 pins to high speed */
-	STM32_GPIO_OSPEEDR(GPIO_B) |= 0xfc000000;
-
-	/* Enable TCPC alert interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-
-	/* Enable charger interrupts */
-	gpio_enable_interrupt(GPIO_CHARGER_INT_ODL);
-
-#ifdef SECTION_IS_RW
-#ifdef CONFIG_WIRELESS_CHARGER_P9221_R7
-	/* Enable Wireless charger interrupts */
-	gpio_enable_interrupt(GPIO_P9221_INT_ODL);
-#endif
-	/* Enable interrupts from BMI160 sensor. */
-	gpio_enable_interrupt(GPIO_ACCEL_INT_ODL);
-
-	/* Enable interrupt for the TCS3400 color light sensor */
-	if (board_version >= 4)
-		gpio_enable_interrupt(GPIO_TCS3400_INT_ODL);
-
-	/* Enable interrupt for the camera vsync. */
-	gpio_enable_interrupt(GPIO_SYNC_INT);
-#endif /* SECTION_IS_RW */
-
-	/* Enable interrupt from PMIC. */
-	gpio_enable_interrupt(GPIO_PMIC_EC_RESETB);
-
-	/* Enable gauge interrupt from max17055 */
-	gpio_enable_interrupt(GPIO_GAUGE_INT_ODL);
-	board_setup_panel();
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-#ifdef SECTION_IS_RW
-static void usb_pd_connect(void)
-{
-	/* VBUS from p9221 is already zero as it's disabled by NCP3902 */
-	p9221_notify_vbus_change(0);
-	rt946x_toggle_bc12_detection();
-}
-DECLARE_HOOK(HOOK_USB_PD_CONNECT, usb_pd_connect, HOOK_PRIO_DEFAULT);
-#endif
-
-void board_config_pre_init(void)
-{
-	STM32_RCC_AHBENR |= STM32_RCC_HB_DMA1;
-	/*
-	 * Remap USART1 and SPI2 DMA:
-	 *
-	 * Ch4: USART1_TX / Ch5: USART1_RX (1000)
-	 * Ch6: SPI2_RX / Ch7: SPI2_TX (0011)
-	 */
-	STM32_DMA_CSELR(STM32_DMAC_CH4) = (8 << 12) | (8 << 16) |
-					  (3 << 20) | (3 << 24);
-}
-
-/* Motion sensors */
-/* Mutexes */
-#ifdef SECTION_IS_RW
-static struct mutex g_lid_mutex;
-
-static struct bmi_drv_data_t g_bmi160_data;
-
-static struct als_drv_data_t g_tcs3400_data = {
-	.als_cal.scale = 1,
-	.als_cal.uscale = 0,
-	.als_cal.offset = 0,
-	.als_cal.channel_scale = {
-		.k_channel_scale = ALS_CHANNEL_SCALE(1.0),   /* kc from VPD */
-		.cover_scale = ALS_CHANNEL_SCALE(0.9),       /* CT */
-	},
-};
-
-static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
-	.calibration.rgb_cal[X] = {
-		.offset = 15, /* 15.65956688 */
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(-0.04592318),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0.06756278),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(-0.05885579),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0.12021096),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kr */
-			.cover_scale = ALS_CHANNEL_SCALE(0.6)
-		}
-	},
-	.calibration.rgb_cal[Y] = {
-		.offset = 8, /* 8.75943638 */
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(-0.07786953),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0.18940035),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(-0.0524428),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0.09092403),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kg */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		}
-	},
-	.calibration.rgb_cal[Z] = {
-		.offset = -21, /* -21.92665481 */
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(-0.18981975),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0.5351057),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(-0.01858507),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(-0.01793189),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0),   /* kb */
-			.cover_scale = ALS_CHANNEL_SCALE(1.5)
-		}
-	},
-	.calibration.irt = INT_TO_FP(1),
-	.saturation.again = TCS_DEFAULT_AGAIN,
-	.saturation.atime = TCS_DEFAULT_ATIME,
-};
-
-/* Matrix to rotate accelerometer into standard reference frame */
-const mat33_fp_t lid_standard_ref = {
-	{ 0,  FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(-1), 0,  0},
-	{ 0,  0, FLOAT_TO_FP(-1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	/*
-	 * Note: bmi160: supports accelerometer and gyro sensor
-	 * Requirement: accelerometer sensor must init before gyro sensor
-	 * DO NOT change the order of the following table.
-	 */
-	[LID_ACCEL] = {
-	 .name = "Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_ACCEL,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .rot_standard_ref = &lid_standard_ref,
-	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	 .min_frequency = BMI_ACCEL_MIN_FREQ,
-	 .max_frequency = BMI_ACCEL_MAX_FREQ,
-	 .config = {
-		 /* Enable accel in S0 */
-		 [SENSOR_CONFIG_EC_S0] = {
-			 .odr = 10000 | ROUND_UP_FLAG,
-			 .ec_rate = 100 * MSEC,
-		 },
-	 },
-	},
-	[LID_GYRO] = {
-	 .name = "Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_ACCEL,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &lid_standard_ref,
-	 .min_frequency = BMI_GYRO_MIN_FREQ,
-	 .max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-	[CLEAR_ALS] = {
-	 .name = "Clear Light",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_TCS3400,
-	 .type = MOTIONSENSE_TYPE_LIGHT,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &tcs3400_drv,
-	 .drv_data = &g_tcs3400_data,
-	 .port = I2C_PORT_ALS,
-	 .i2c_spi_addr_flags = TCS3400_I2C_ADDR_FLAGS,
-	 .rot_standard_ref = NULL,
-	 .default_range = 0x10000, /* scale = 1x, uscale = 0 */
-	 .min_frequency = TCS3400_LIGHT_MIN_FREQ,
-	 .max_frequency = TCS3400_LIGHT_MAX_FREQ,
-	 .config = {
-		 /* Run ALS sensor in S0 */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 1000,
-		},
-	 },
-	},
-	[RGB_ALS] = {
-	.name = "RGB Light",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_TCS3400,
-	 .type = MOTIONSENSE_TYPE_LIGHT_RGB,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &tcs3400_rgb_drv,
-	 .drv_data = &g_tcs3400_rgb_data,
-	 /*.port=I2C_PORT_ALS,*/ /* Unused. RGB channels read by CLEAR_ALS. */
-	 .rot_standard_ref = NULL,
-	 .default_range = 0x10000, /* scale = 1x, uscale = 0 */
-	 .min_frequency = 0, /* 0 indicates we should not use sensor directly */
-	 .max_frequency = 0, /* 0 indicates we should not use sensor directly */
-	},
-	[VSYNC] = {
-	 .name = "Camera vsync",
-	 .active_mask = SENSOR_ACTIVE_S0,
-	 .chip = MOTIONSENSE_CHIP_GPIO,
-	 .type = MOTIONSENSE_TYPE_SYNC,
-	 .location = MOTIONSENSE_LOC_CAMERA,
-	 .drv = &sync_drv,
-	 .default_range = 0,
-	 .min_frequency = 0,
-	 .max_frequency = 1,
-	},
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-const struct motion_sensor_t *motion_als_sensors[] = {
-	&motion_sensors[CLEAR_ALS],
-};
-BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
-#endif /* SECTION_IS_RW */
-
-int board_allow_i2c_passthru(int port)
-{
-	return (port == I2C_PORT_VIRTUAL_BATTERY);
-}
-
-int board_get_fod(uint8_t **fod)
-{
-	*fod = NULL;
-	return 0;
-}
-
-int board_get_epp_fod(uint8_t **fod)
-{
-	*fod = NULL;
-	return 0;
-}
-
diff --git a/board/flapjack/board.h b/board/flapjack/board.h
deleted file mode 100644
index 370bd1727f..0000000000
--- a/board/flapjack/board.h
+++ /dev/null
@@ -1,345 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Configuration for Kukui */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Optional modules */
-#define CONFIG_ADC
-#undef  CONFIG_ADC_WATCHDOG
-#define CONFIG_BOARD_VERSION_CBI
-#define CONFIG_CHIPSET_MT8183
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CRC8
-#define CONFIG_CROS_BOARD_INFO
-#define CONFIG_EMULATED_SYSRQ
-#undef  CONFIG_HIBERNATE
-#define CONFIG_I2C
-#define CONFIG_I2C_MASTER
-#define CONFIG_I2C_VIRTUAL_BATTERY
-#define CONFIG_I2C_PASSTHRU_RESTRICTED
-#define CONFIG_LED_COMMON
-#define CONFIG_LOW_POWER_IDLE
-#define CONFIG_POWER_COMMON
-#define CONFIG_SPI
-#define CONFIG_SPI_MASTER
-#define CONFIG_STM_HWTIMER32
-#define CONFIG_SWITCH
-#define CONFIG_WATCHDOG_HELP
-
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands for testing */
-
-#undef  CONFIG_UART_CONSOLE
-#define CONFIG_UART_CONSOLE 1
-#define CONFIG_UART_RX_DMA
-
-/* Bootblock */
-#ifdef SECTION_IS_RO
-#define CONFIG_BOOTBLOCK
-
-#define EMMC_SPI_PORT 2
-#endif
-
-/* Optional features */
-#define CONFIG_BOARD_PRE_INIT
-#define CONFIG_BUTTON_TRIGGERED_RECOVERY
-#define CONFIG_CHARGER_ILIM_PIN_DISABLED
-#define CONFIG_FORCE_CONSOLE_RESUME
-#define CONFIG_HOST_COMMAND_STATUS
-#define CONFIG_CMD_AP_RESET_LOG
-
-/* Required for FAFT */
-#define CONFIG_CMD_BUTTON
-
-/* By default, set hcdebug to off */
-#undef CONFIG_HOSTCMD_DEBUG_MODE
-#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
-#define CONFIG_LTO
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_IGNORE_LID
-#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-#define CONFIG_SOFTWARE_PANIC
-#define CONFIG_VBOOT_HASH
-#define CONFIG_VOLUME_BUTTONS
-
-#define CONFIG_CHARGER
-#define CONFIG_CHARGER_MT6370
-#define CONFIG_CHARGER_INPUT_CURRENT 512
-#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 2
-#define CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT 2
-#define CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW 15000
-#define CONFIG_CHARGER_PROFILE_OVERRIDE
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_OTG
-#define CONFIG_USB_CHARGER
-#define CONFIG_USB_MUX_VIRTUAL
-
-/* Increase tx buffer size, as we'd like to stream EC log to AP. */
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* Motion Sensors */
-#ifdef SECTION_IS_RW
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
-
-#define CONFIG_ALS
-#define ALS_COUNT 1
-
-/* TSC3400 ALS */
-#define CONFIG_ALS_TCS3400
-#define CONFIG_ALS_TCS3400_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS)
-#define CONFIG_TCS_USE_LUX_TABLE
-
-
-/* ALS needs to be polled */
-#define CONFIG_ACCEL_FORCE_MODE_MASK    BIT(CLEAR_ALS)
-
-/* Camera VSYNC */
-#define CONFIG_SYNC
-#define CONFIG_SYNC_COMMAND
-#define CONFIG_SYNC_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
-#endif /* SECTION_IS_RW */
-
-/* To be able to indicate the device is in tablet mode. */
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-
-/*
- * Only include the sensor fifo in the RW section (since the motion task is only
- * included there).
- */
-#ifdef SECTION_IS_RW
-/* Enable sensor fifo, must also define the _SIZE and _THRES */
-#define CONFIG_ACCEL_FIFO
-/* FIFO size is in power of 2. */
-#define CONFIG_ACCEL_FIFO_SIZE 256
-/* Depends on how fast the AP boots and typical ODRs. */
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-#endif /* SECTION_IS_RW */
-
-/* Wireless Power Charger Config */
-#ifdef SECTION_IS_RW
-#define CONFIG_WIRELESS_CHARGER_P9221_R7
-#endif
-
-
-/* USB PD config */
-#define CONFIG_CHARGE_MANAGER
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV1
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_DISCHARGE_TCPC
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-#define CONFIG_USB_PD_TCPM_MT6370
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-#define CONFIG_USB_PD_5V_CHARGER_CTRL
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-#define CONFIG_USB_PD_COMM_LOCKED
-#define CONFIG_USB_PD_DP_HPD_GPIO
-#define CONFIG_USBC_DISABLE_CHARGE_FROM_RP_DEF
-#ifdef SECTION_IS_RO
-#define CONFIG_USB_PD_DEBUG_LEVEL 0
-#endif
-
-#define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_PRESENT_CUSTOM
-#define CONFIG_BATTERY_REVIVE_DISCONNECT
-#define CONFIG_BATTERY_MAX17055
-#define CONFIG_BATTERY_MAX17055_ALERT
-#define CONFIG_BATTERY_MAX17055_FULL_MODEL
-
-/* Battery parameters for max17055 ModelGauge m5 algorithm. */
-#define BATTERY_MAX17055_RSENSE             10    /* m-ohm */
-#define BATTERY_DESIRED_CHARGING_CURRENT    2000  /* mA */
-
-#define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_VOLTAGE_MV     9000
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_POWER_MW       18000
-
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY 50000  /* us */
-#define PD_VCONN_SWAP_DELAY 5000 /* us */
-
-/* Timer selection */
-#define TIM_CLOCK32  2
-#define TIM_WATCHDOG 7
-
-/* 48 MHz SYSCLK clock frequency */
-#define CPU_CLOCK 48000000
-
-/* Optional for testing */
-#undef  CONFIG_PECI
-#undef  CONFIG_PSTORE
-
-/* Modules we want to exclude */
-#undef CONFIG_CMD_ACCELSPOOF
-#undef CONFIG_CMD_APTHROTTLE
-#undef CONFIG_CMD_BATTFAKE
-#undef CONFIG_CMD_DEVICE_EVENT
-#undef CONFIG_CMD_FASTCHARGE
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_GETTIME
-#undef CONFIG_CMD_HASH
-#undef CONFIG_CMD_HCDEBUG
-#undef CONFIG_CMD_MD
-#undef CONFIG_CMD_MEM
-#undef CONFIG_CMD_POWERINDEBUG
-#undef CONFIG_CMD_TIMERINFO
-
-#ifdef SECTION_IS_RO
-#undef CONFIG_CMD_ADC
-#undef CONFIG_CMD_APTHROTTLE
-#undef CONFIG_CMD_CBI
-#undef CONFIG_CMD_I2C_SCAN
-#undef CONFIG_CMD_I2C_XFER
-#undef CONFIG_CMD_IDLE_STATS
-#undef CONFIG_CMD_INA
-#undef CONFIG_CMD_MMAPINFO
-#undef CONFIG_CMD_PD
-#undef CONFIG_CMD_PWR_AVG
-#undef CONFIG_CMD_REGULATOR
-#undef CONFIG_CMD_RW
-#undef CONFIG_CMD_SHMEM
-/* TODO: Consider put these back when FSI is (about to be) done. */
-#undef CONFIG_CMD_SLEEPMASK
-#undef CONFIG_CMD_SLEEPMASK_SET
-#undef CONFIG_CMD_SYSLOCK
-#endif
-
-#define CONFIG_TASK_PROFILING
-
-/* I2C ports */
-#define I2C_PORT_CHARGER  0
-#define I2C_PORT_TCPC0    0
-#define I2C_PORT_WPC      0
-#define I2C_PORT_BATTERY  1
-#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
-#define I2C_PORT_ACCEL    1
-#define I2C_PORT_ALS      1
-#define I2C_PORT_EEPROM		1
-
-/* I2C addresses */
-#define I2C_ADDR_EEPROM_FLAGS		0x50
-
-/* Route sbs host requests to virtual battery driver */
-#define VIRTUAL_BATTERY_ADDR_FLAGS	0x0B
-
-/* Enable Accel over SPI */
-#define CONFIG_SPI_ACCEL_PORT    0  /* The first SPI master port (SPI2) */
-
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_GPIO
-/* Define the host events which are allowed to wakeup AP in S3. */
-#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \
-		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC))
-
-/* Define panel size mask according to skuid */
-#define SKU_ID_PANEL_SIZE_MASK  BIT(1)
-
-#ifndef __ASSEMBLER__
-
-enum oem_id {
-	PROJECT_FLAPJACK = 0,
-	PROJECT_COUNT,
-};
-
-enum adc_channel {
-	/* Real ADC channels begin here */
-	ADC_LCM_ID = 0,
-	ADC_EC_SKU_ID,
-	ADC_BATT_ID,
-	ADC_USBC_THERM,
-	ADC_CH_COUNT
-};
-
-/* Panel ID bit position inside sku_id */
-#define PANEL_ID_BIT_POSITION  16
-
-/* Refer to coreboot/src/mainboard/google/kukui/display.h */
-enum panel_id {
-	PANEL_DEFAULT = 0,
-	PANEL_BOE_TV101WUM_NG0,
-	PANEL_BOE_TV080WUM_NG0,
-	PANEL_STA_10P,
-	PANEL_STA_08P,
-	PANEL_COUNT,
-	PANEL_UNINITIALIZED = 0xf,
-};
-
-/* power signal definitions */
-enum power_signal {
-	AP_IN_S3_L,
-	PMIC_PWR_GOOD,
-
-	/* Number of signals */
-	POWER_SIGNAL_COUNT,
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL = 0,
-	LID_GYRO,
-	CLEAR_ALS,
-	RGB_ALS,
-	VSYNC,
-	SENSOR_COUNT,
-};
-
-/* Batteries */
-enum battery_type {
-	BATTERY_UNKNOWN = 0,
-	BATTERY_C18_ATL,
-	BATTERY_C19_ATL,
-	BATTERY_C18_SUNWODA,
-	BATTERY_C19_SUNWODA,
-	BATTERY_COUNT,
-};
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-#ifdef SECTION_IS_RO
-/* Interrupt handler for emmc task */
-void emmc_cmd_interrupt(enum gpio_signal signal);
-#endif
-
-void board_reset_pd_mcu(void);
-
-#define ADC_MARGIN_MV 56 /* Simply assume 1800/16/2 */
-
-struct mv_to_id {
-	int id;
-	int median_mv;
-};
-
-int board_read_id(enum adc_channel, const struct mv_to_id *table, int size);
-
-extern uint8_t board_version;
-extern uint8_t oem;
-extern uint32_t sku;
-
-#define PORT_TO_HPD(port) GPIO_USB_C0_HPD_OD
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/flapjack/build.mk b/board/flapjack/build.mk
deleted file mode 100644
index a368c187bf..0000000000
--- a/board/flapjack/build.mk
+++ /dev/null
@@ -1,21 +0,0 @@
-# -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-#
-# STmicro STM32F098VC
-CHIP:=stm32
-CHIP_FAMILY:=stm32f0
-CHIP_VARIANT:=stm32f09x
-
-board-y=battery.o board.o usb_pd_policy.o led.o
-board-$(CONFIG_BOOTBLOCK)+=emmc.o
-board-$(BOARD_KRANE)+=base_detect_krane.o
-
-$(out)/RO/board/$(BOARD)/emmc.o: $(out)/bootblock_data.h
-
-# 21504 bytes plus some extra buffer
-DEFAULT_BOOTBLOCK_SIZE:=23000
diff --git a/board/flapjack/ec.tasklist b/board/flapjack/ec.tasklist
deleted file mode 100644
index 33e3538139..0000000000
--- a/board/flapjack/ec.tasklist
+++ /dev/null
@@ -1,21 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG, usb_charger_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS_RW(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS_RO(EMMC, emmc_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS_RW(WPC,wireless_power_charger_task,NULL,LARGER_TASK_STACK_SIZE)
-
diff --git a/board/flapjack/emmc.c b/board/flapjack/emmc.c
deleted file mode 120000
index a97e912173..0000000000
--- a/board/flapjack/emmc.c
+++ /dev/null
@@ -1 +0,0 @@
-../../baseboard/kukui/emmc.c
\ No newline at end of file
diff --git a/board/flapjack/gpio.inc b/board/flapjack/gpio.inc
deleted file mode 100644
index f349ceb972..0000000000
--- a/board/flapjack/gpio.inc
+++ /dev/null
@@ -1,107 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first.
- */
-
-/* Interrupts */
-GPIO_INT(USB_C0_PD_INT_ODL, PIN(B, 1), GPIO_INT_FALLING | GPIO_PULL_UP,
-         tcpc_alert_event)
-GPIO_INT(VOLUME_UP_L,       PIN(B, 10), GPIO_INT_BOTH | GPIO_PULL_UP,
-         button_interrupt) /* EC_VOLUP_BTN_ODL */
-GPIO_INT(VOLUME_DOWN_L,     PIN(B, 11), GPIO_INT_BOTH | GPIO_PULL_UP,
-         button_interrupt) /* EC_VOLDN_BTN_ODL */
-GPIO_INT(POWER_BUTTON_L,    PIN(A, 0),  GPIO_INT_BOTH | GPIO_PULL_UP,
-         power_button_interrupt) /* EC_PWR_BTN_ODL */
-
-GPIO_INT(AP_IN_SLEEP_L,     PIN(C, 12), GPIO_INT_BOTH | GPIO_PULL_DOWN,
-         power_signal_interrupt)
-GPIO_INT(PMIC_EC_RESETB,    PIN(B, 7),  GPIO_INT_BOTH | GPIO_PULL_DOWN,
-         power_signal_interrupt)
-GPIO_INT(WARM_RESET_REQ,    PIN(A, 3),  GPIO_INT_RISING | GPIO_PULL_DOWN,
-         chipset_reset_request_interrupt)
-GPIO_INT(AP_EC_WATCHDOG_L,  PIN(C, 2),  GPIO_INT_FALLING,
-         chipset_watchdog_interrupt)
-
-GPIO_INT_RW(ACCEL_INT_ODL,  PIN(A, 4), GPIO_INT_FALLING | GPIO_SEL_1P8V | \
-	 GPIO_PULL_UP, bmi160_interrupt)
-
-GPIO_INT_RW(TCS3400_INT_ODL,  PIN(A, 14), GPIO_INT_FALLING,
-         tcs3400_interrupt)
-GPIO_INT(CHARGER_INT_ODL,   PIN(C, 13), GPIO_INT_FALLING | GPIO_PULL_UP,
-         rt946x_interrupt)
-GPIO_INT_RO(EMMC_CMD,       PIN(B, 15), GPIO_INT_FALLING,
-         emmc_cmd_interrupt)
-GPIO_INT(SPI1_NSS,          PIN(A, 15), GPIO_INT_BOTH | GPIO_PULL_UP,
-         spi_event)
-GPIO_INT_RW(SYNC_INT,       PIN(A, 8),  GPIO_INT_RISING | GPIO_PULL_DOWN,
-         sync_interrupt)
-GPIO_INT(LID_OPEN,        PIN(C, 5),  GPIO_INT_BOTH,
-         lid_interrupt) /* HALL_INT_L */
-GPIO_INT(GAUGE_INT_ODL,     PIN(C, 9),  GPIO_INT_FALLING | GPIO_PULL_UP,
-         gauge_interrupt)
-GPIO_INT_RW(P9221_INT_ODL,  PIN(A, 6), GPIO_INT_FALLING,
-        p9221_interrupt)
-
-/* Voltage rails control pins */
-
-/* Reset pins */
-GPIO(AP_SYS_RST_L,         PIN(C, 11), GPIO_OUT_LOW)
-GPIO(PMIC_WATCHDOG_L,      PIN(C, 3),  GPIO_OUT_LOW)
-GPIO(PMIC_EN_ODL,          PIN(C, 10), GPIO_ODR_HIGH)
-GPIO(PMIC_FORCE_RESET_ODL, PIN(A, 2),  GPIO_ODR_HIGH)
-GPIO(MT6370_RST_L,         PIN(F, 0),  GPIO_OUT_LOW)
-
-/*
- * I2C pins should be configured as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-GPIO(I2C1_SCL,             PIN(B, 8),  GPIO_INPUT)
-GPIO(I2C1_SDA,             PIN(B, 9),  GPIO_INPUT)
-GPIO(I2C2_SCL,             PIN(A, 11), GPIO_INPUT)
-GPIO(I2C2_SDA,             PIN(A, 12), GPIO_INPUT)
-
-/* Analog pins */
-GPIO(BATT_ID,              PIN(A, 7),  GPIO_ANALOG)
-GPIO(LCM_ID,               PIN(C, 0),  GPIO_ANALOG)
-GPIO(EC_SKU_ID,            PIN(B, 0),  GPIO_ANALOG)
-GPIO(USBC_THERM,           PIN(C, 4),  GPIO_ANALOG)
-
-/* Other input pins */
-GPIO(WP_L,                 PIN(C, 8),  GPIO_INPUT) /* EC_FLASH_WP_ODL */
-GPIO(BOOT0,                PIN(F, 11), GPIO_INPUT)
-GPIO(CCD_MODE_ODL,         PIN(A, 1),  GPIO_INPUT)
-
-/* Other output pins */
-GPIO(ENTERING_RW,          PIN(C, 6),  GPIO_ODR_HIGH) /* EC_ENTERING_RW_ODL */
-GPIO(EC_INT_L,             PIN(B, 12), GPIO_ODR_HIGH) /* EC_AP_INT_ODL */
-GPIO(USB_C0_DP_POLARITY,   PIN(C, 14), GPIO_OUT_LOW)
-GPIO(USB_C0_HPD_OD,        PIN(F, 1),  GPIO_ODR_LOW)
-GPIO(BOOTBLOCK_EN_L,       PIN(C, 1),  GPIO_ODR_HIGH)
-GPIO(USB_C0_DP_OE_L,       PIN(A, 5),  GPIO_OUT_HIGH)
-GPIO(EC_SWDIO,             PIN(A, 13), GPIO_ODR_HIGH)
-GPIO(EN_PP5000_USBC,       PIN(D, 2),  GPIO_OUT_LOW)
-GPIO(BPP_EPP_SEL,          PIN(B, 6),  GPIO_OUT_LOW)
-GPIO(NCP3902_EN_L,         PIN(C, 7),  GPIO_OUT_LOW)
-
-
-/* USART1: PA9/PA10 */
-ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART,       0)
-/* I2C MASTER: PB8/9 */
-ALTERNATE(PIN_MASK(B, 0x0300), 1, MODULE_I2C,        GPIO_ODR_HIGH )
-/* I2C MASTER: PA11/12 */
-ALTERNATE(PIN_MASK(A, 0x1800), 5, MODULE_I2C,        GPIO_ODR_HIGH )
-/* SPI SLAVE: PB3/4/5 */
-ALTERNATE(PIN_MASK(B, 0x0038), 0, MODULE_SPI,        0)
-#ifdef SECTION_IS_RO
-/* SPI SLAVE: PB13/14/15 */
-ALTERNATE(PIN_MASK(B, 0xE000), 0, MODULE_SPI_FLASH,        0)
-#endif
-/* SPI SLAVE CS: PA15 */
-ALTERNATE(PIN_MASK(A, 0x8000), 0, MODULE_SPI,        0)
diff --git a/board/flapjack/led.c b/board/flapjack/led.c
deleted file mode 100644
index 165d549eb7..0000000000
--- a/board/flapjack/led.c
+++ /dev/null
@@ -1,182 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery LED control for Flapjack board.
- */
-
-#include "battery.h"
-#include "charge_state.h"
-#include "console.h"
-#include "driver/charger/rt946x.h"
-#include "hooks.h"
-#include "led_common.h"
-#include "util.h"
-
-/* Define this to enable led command and debug LED */
-#undef DEBUG_LED
-
-const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-#define LED_OFF		MT6370_LED_ID_OFF
-#define LED_RED		MT6370_LED_ID1
-#define LED_GRN		MT6370_LED_ID2
-#define LED_BLU		MT6370_LED_ID3
-
-#define LED_MASK_OFF	0
-#define LED_MASK_RED	MT6370_MASK_RGB_ISNK1DIM_EN
-#define LED_MASK_GRN	MT6370_MASK_RGB_ISNK2DIM_EN
-#define LED_MASK_BLU	MT6370_MASK_RGB_ISNK3DIM_EN
-
-static enum charge_state chstate;
-
-static void led_set_battery(void)
-{
-	static enum charge_state prev = PWR_STATE_UNCHANGE;
-	static int battery_second;
-	int red = 0, grn = 0, blu = 0;
-
-	battery_second++;
-#ifndef DEBUG_LED
-	chstate = charge_get_state();
-#endif
-	if (chstate == prev)
-		return;
-	prev = chstate;
-
-	/*
-	 * Full      White
-	 * Charging  Amber
-	 * Error     Red
-	 */
-	switch (chstate) {
-	case PWR_STATE_CHARGE:
-		/* RGB(current, duty) = (4mA,10/32) (4mA,1/32) (0mA,) */
-		red = 1;
-		grn = 1;
-		mt6370_led_set_pwm_dim_duty(LED_RED, 9);
-		mt6370_led_set_pwm_dim_duty(LED_GRN, 0);
-		break;
-	case PWR_STATE_DISCHARGE:
-		/* RGB(current, duty) = (0mA,) (0mA,) (0mA,) */
-		break;
-	case PWR_STATE_ERROR:
-		/* RGB(current, duty) = (4mA,8/32) (0mA,) (0mA,) */
-		red = 1;
-		mt6370_led_set_pwm_dim_duty(LED_RED, 7);
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		/* RGB(current, duty) = (8mA,2/32) (8mA,1/32) (4mA,1/32) */
-		red = 2;
-		grn = 2;
-		blu = 1;
-		mt6370_led_set_pwm_dim_duty(LED_RED, 1);
-		mt6370_led_set_pwm_dim_duty(LED_GRN, 0);
-		mt6370_led_set_pwm_dim_duty(LED_BLU, 0);
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		return;
-	}
-
-	mt6370_led_set_brightness(LED_RED, red);
-	mt6370_led_set_brightness(LED_GRN, grn);
-	mt6370_led_set_brightness(LED_BLU, blu);
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	/* Current is fixed at 4mA. Brightness is controlled by duty only. */
-	const uint8_t max = MT6370_LED_PWM_DIMDUTY_MAX;
-	if (led_id != EC_LED_ID_BATTERY_LED)
-		return;
-	brightness_range[EC_LED_COLOR_GREEN] = max;
-	brightness_range[EC_LED_COLOR_RED] = max;
-	brightness_range[EC_LED_COLOR_BLUE] = max;
-}
-
-static void set_current_and_pwm_duty(uint8_t brightness,
-				     enum mt6370_led_index color)
-{
-	if (brightness) {
-		/* Current is fixed at 4mA. Brightness is controlled by duty. */
-		mt6370_led_set_brightness(color, 1);
-		mt6370_led_set_pwm_dim_duty(color, brightness);
-	} else {
-		/* off */
-		mt6370_led_set_brightness(color, 0);
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id != EC_LED_ID_BATTERY_LED)
-		return EC_ERROR_INVAL;
-	set_current_and_pwm_duty(brightness[EC_LED_COLOR_RED], LED_RED);
-	set_current_and_pwm_duty(brightness[EC_LED_COLOR_GREEN], LED_GRN);
-	set_current_and_pwm_duty(brightness[EC_LED_COLOR_BLUE], LED_BLU);
-	return EC_SUCCESS;
-}
-
-static void flapjack_led_init(void)
-{
-	const enum mt6370_led_dim_mode dim = MT6370_LED_DIM_MODE_PWM;
-	const enum mt6370_led_pwm_freq freq = MT6370_LED_PWM_FREQ1000;
-	mt6370_led_set_color(LED_MASK_RED | LED_MASK_GRN | LED_MASK_BLU);
-	mt6370_led_set_dim_mode(LED_RED, dim);
-	mt6370_led_set_dim_mode(LED_GRN, dim);
-	mt6370_led_set_dim_mode(LED_BLU, dim);
-	mt6370_led_set_pwm_frequency(LED_RED, freq);
-	mt6370_led_set_pwm_frequency(LED_GRN, freq);
-	mt6370_led_set_pwm_frequency(LED_BLU, freq);
-}
-DECLARE_HOOK(HOOK_INIT, flapjack_led_init, HOOK_PRIO_DEFAULT);
-
-/* Called by hook task every 1 sec */
-static void led_second(void)
-{
-	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
-		led_set_battery();
-}
-DECLARE_HOOK(HOOK_SECOND, led_second, HOOK_PRIO_DEFAULT);
-
-#ifdef DEBUG_LED
-static int command_led(int argc, char **argv)
-{
-	int val;
-	char *e;
-
-	mt6370_led_set_color(LED_MASK_RED|LED_MASK_GRN|LED_MASK_BLU);
-
-	if (argc == 2) {
-		val = strtoi(argv[1], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM1;
-		chstate = val;
-		return EC_SUCCESS;
-	}
-
-	if (argc < 4)
-		return EC_ERROR_PARAM_COUNT;
-
-	val = strtoi(argv[1], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM1;
-	mt6370_led_set_brightness(LED_RED, val);
-
-	val = strtoi(argv[2], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM2;
-	mt6370_led_set_brightness(LED_GRN, val);
-
-	val = strtoi(argv[3], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM3;
-	mt6370_led_set_brightness(LED_BLU, val);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(led, command_led, "<chg_state> or <R> <G> <B>", NULL);
-#endif
diff --git a/board/flapjack/usb_pd_policy.c b/board/flapjack/usb_pd_policy.c
deleted file mode 100644
index 20de95dc3b..0000000000
--- a/board/flapjack/usb_pd_policy.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "atomic.h"
-#include "charger.h"
-#include "charge_manager.h"
-#include "common.h"
-#include "console.h"
-#include "driver/charger/rt946x.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-static uint8_t vbus_en;
-
-int board_vbus_source_enabled(int port)
-{
-	return vbus_en;
-}
-
-int pd_check_vconn_swap(int port)
-{
-	/*
-	 * VCONN is provided directly by the battery (PPVAR_SYS)
-	 * but use the same rules as power swap.
-	 */
-	return pd_get_dual_role(port) == PD_DRP_TOGGLE_ON ? 1 : 0;
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	/* Disable NCP3902 to avoid charging from VBUS */
-	gpio_set_level(GPIO_NCP3902_EN_L, 1);
-
-	/* Provide VBUS */
-	vbus_en = 1;
-	gpio_set_level(GPIO_EN_PP5000_USBC, 1);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS; /* we are ready */
-}
-
-void pd_power_supply_reset(int port)
-{
-	int prev_en;
-
-	prev_en = vbus_en;
-	/* Disable VBUS */
-	vbus_en = 0;
-
-	if (prev_en) {
-		gpio_set_level(GPIO_EN_PP5000_USBC, 0);
-		msleep(250);
-		gpio_set_level(GPIO_NCP3902_EN_L, 0);
-	}
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-/* ----------------- Vendor Defined Messages ------------------ */
-#ifdef CONFIG_USB_PD_ALT_MODE_DFP
-__override void svdm_dp_post_config(int port)
-{
-	dp_flags[port] |= DP_FLAGS_DP_ON;
-	if (!(dp_flags[port] & DP_FLAGS_HPD_HI_PENDING))
-		return;
-
-	gpio_set_level(GPIO_USB_C0_HPD_OD, 1);
-	gpio_set_level(GPIO_USB_C0_DP_OE_L, 0);
-	gpio_set_level(GPIO_USB_C0_DP_POLARITY, pd_get_polarity(port));
-
-	/* set the minimum time delay (2ms) for the next HPD IRQ */
-	svdm_hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
-	usb_mux_hpd_update(port, 1, 0);
-}
-
-__override int svdm_dp_attention(int port, uint32_t *payload)
-{
-	int cur_lvl = gpio_get_level(GPIO_USB_C0_HPD_OD);
-	int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]);
-	int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]);
-
-	dp_status[port] = payload[1];
-
-	/* Its initial DP status message prior to config */
-	if (!(dp_flags[port] & DP_FLAGS_DP_ON)) {
-		if (lvl)
-			dp_flags[port] |= DP_FLAGS_HPD_HI_PENDING;
-		return 1;
-	}
-
-	usb_mux_set(port, lvl ? USB_PD_MUX_DP_ENABLED : USB_PD_MUX_NONE,
-		    USB_SWITCH_CONNECT, pd_get_polarity(port));
-
-	usb_mux_hpd_update(port, lvl, irq);
-
-	if (irq & cur_lvl) {
-		uint64_t now = get_time().val;
-		/* wait for the minimum spacing between IRQ_HPD if needed */
-		if (now < svdm_hpd_deadline[port])
-			usleep(svdm_hpd_deadline[port] - now);
-
-		/* generate IRQ_HPD pulse */
-		gpio_set_level(GPIO_USB_C0_HPD_OD, 0);
-		usleep(HPD_DSTREAM_DEBOUNCE_IRQ);
-		gpio_set_level(GPIO_USB_C0_HPD_OD, 1);
-
-		gpio_set_level(GPIO_USB_C0_DP_OE_L, 0);
-		gpio_set_level(GPIO_USB_C0_DP_POLARITY, pd_get_polarity(port));
-
-		/* set the minimum time delay (2ms) for the next HPD IRQ */
-		svdm_hpd_deadline[port] = get_time().val +
-			HPD_USTREAM_DEBOUNCE_LVL;
-	} else if (irq & !cur_lvl) {
-		CPRINTF("ERR:HPD:IRQ&LOW\n");
-		return 0; /* nak */
-	} else {
-		gpio_set_level(GPIO_USB_C0_HPD_OD, lvl);
-		gpio_set_level(GPIO_USB_C0_DP_OE_L, !lvl);
-		gpio_set_level(GPIO_USB_C0_DP_POLARITY, pd_get_polarity(port));
-		/* set the minimum time delay (2ms) for the next HPD IRQ */
-		svdm_hpd_deadline[port] = get_time().val +
-			HPD_USTREAM_DEBOUNCE_LVL;
-	}
-
-	/* ack */
-	return 1;
-}
-
-__override void svdm_exit_dp_mode(int port)
-{
-	svdm_safe_dp_mode(port);
-	gpio_set_level(GPIO_USB_C0_HPD_OD, 0);
-	gpio_set_level(GPIO_USB_C0_DP_OE_L, 1);
-	usb_mux_hpd_update(port, 0, 0);
-}
-#endif /* CONFIG_USB_PD_ALT_MODE_DFP */
diff --git a/board/fleex/battery.c b/board/fleex/battery.c
index 57a5246052..e5efb19920 100644
--- a/board/fleex/battery.c
+++ b/board/fleex/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/fleex/board.c b/board/fleex/board.c
index c487da68f2..c8cecbadd4 100644
--- a/board/fleex/board.c
+++ b/board/fleex/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,6 @@
 /* Fleex board-specific configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "battery.h"
 #include "button.h"
 #include "charge_manager.h"
@@ -18,6 +17,7 @@
 #include "driver/accelgyro_lsm6dsm.h"
 #include "driver/charger/isl923x.h"
 #include "driver/ppc/nx20p348x.h"
+#include "driver/ppc/syv682x.h"
 #include "driver/tcpm/anx7447.h"
 #include "driver/tcpm/ps8xxx.h"
 #include "driver/tcpm/tcpci.h"
@@ -33,32 +33,71 @@
 #include "power_button.h"
 #include "switch.h"
 #include "system.h"
-#include "task.h"
 #include "tablet_mode.h"
-#include "tcpci.h"
+#include "task.h"
+#include "tcpm/tcpci.h"
 #include "temp_sensor.h"
-#include "thermistor.h"
+#include "temp_sensor/thermistor.h"
 #include "usb_mux.h"
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define USB_PD_PORT_ANX7447	0
-#define USB_PD_PORT_PS8751	1
+#define USB_PD_PORT_ANX7447 0
+#define USB_PD_PORT_PS8751 1
 
 static uint8_t sku_id;
+static int is_support_syv_ppc;
+
+const struct ppc_config_t ppc_syv682x_port0 = {
+	.i2c_port = I2C_PORT_TCPC0,
+	.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+	.drv = &syv682x_drv,
+};
+
+const struct ppc_config_t ppc_syv682x_port1 = {
+	.i2c_port = I2C_PORT_TCPC1,
+	.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+	.drv = &syv682x_drv,
+};
+
+/* Check PPC_ID pin status to decide which one ppc is used. */
+static int board_is_syv_ppc(void)
+{
+	return gpio_get_level(GPIO_PPC_ID);
+}
+
+static void board_update_ppc_config_from_board(void)
+{
+	if (!is_support_syv_ppc)
+		return;
+
+	memcpy(&ppc_chips[USB_PD_PORT_TCPC_0], &ppc_syv682x_port0,
+	       sizeof(struct ppc_config_t));
+	memcpy(&ppc_chips[USB_PD_PORT_TCPC_1], &ppc_syv682x_port1,
+	       sizeof(struct ppc_config_t));
+
+	gpio_set_flags(GPIO_USB_PD_C0_INT_ODL, GPIO_INT_BOTH);
+	gpio_set_flags(GPIO_USB_PD_C1_INT_ODL, GPIO_INT_BOTH);
+}
 
 static void ppc_interrupt(enum gpio_signal signal)
 {
 	switch (signal) {
 	case GPIO_USB_PD_C0_INT_ODL:
-		nx20p348x_interrupt(0);
+		if (is_support_syv_ppc)
+			syv682x_interrupt(0);
+		else
+			nx20p348x_interrupt(0);
 		break;
 
 	case GPIO_USB_PD_C1_INT_ODL:
-		nx20p348x_interrupt(1);
+		if (is_support_syv_ppc)
+			syv682x_interrupt(1);
+		else
+			nx20p348x_interrupt(1);
 		break;
 
 	default:
@@ -71,28 +110,30 @@ static void ppc_interrupt(enum gpio_signal signal)
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_AMB] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_VBUS_C0] = {"VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
-	[ADC_VBUS_C1] = {"VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_AMB] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				  ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_CHARGER] = { "TEMP_CHARGER", NPCX_ADC_CH1,
+				      ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 },
+	[ADC_VBUS_C0] = { "VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT * 10,
+			  ADC_READ_MAX + 1, 0 },
+	[ADC_VBUS_C1] = { "VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT * 10,
+			  ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp,
-				 .idx = 0},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
+	[TEMP_SENSOR_BATTERY] = { .name = "Battery",
+				  .type = TEMP_SENSOR_TYPE_BATTERY,
+				  .read = charge_get_battery_temp,
+				  .idx = 0 },
+	[TEMP_SENSOR_AMBIENT] = { .name = "Ambient",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_51k1_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_AMB },
+	[TEMP_SENSOR_CHARGER] = { .name = "Charger",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_13k7_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_CHARGER },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -102,17 +143,13 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrix to rotate accelerometer into standard reference frame */
-const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1),  0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
+const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+				      { FLOAT_TO_FP(-1), 0, 0 },
+				      { 0, 0, FLOAT_TO_FP(1) } };
 
- const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0,  0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
- };
+const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				       { 0, FLOAT_TO_FP(-1), 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
 
 /* sensor private data */
 static struct stprivate_data g_lis2dh_data;
@@ -158,8 +195,6 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_base_mutex,
 		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
 				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
 		.port = I2C_PORT_SENSOR,
 		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
 		.rot_standard_ref = &base_standard_ref,
@@ -190,8 +225,6 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_base_mutex,
 		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
 				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
 		.port = I2C_PORT_SENSOR,
 		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
 		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
@@ -205,8 +238,8 @@ unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
 static int board_is_convertible(void)
 {
-	return sku_id == 0x21 || sku_id == 0x22 || sku_id == 0x23
-		|| sku_id == 0xff;
+	return sku_id == 0x21 || sku_id == 0x22 || sku_id == 0x23 ||
+	       sku_id == 0xff;
 }
 
 static void board_update_sensor_config_from_sku(void)
@@ -236,9 +269,8 @@ static void cbi_init(void)
 }
 DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1);
 
-#ifndef TEST_BUILD
 /* This callback disables keyboard when convertibles are fully open */
-void lid_angle_peripheral_enable(int enable)
+__override void lid_angle_peripheral_enable(int enable)
 {
 	/*
 	 * If the lid is in tablet position via other sensors,
@@ -250,7 +282,6 @@ void lid_angle_peripheral_enable(int enable)
 	if (board_is_convertible())
 		keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
 }
-#endif
 
 void board_overcurrent_event(int port, int is_overcurrented)
 {
@@ -265,9 +296,10 @@ void board_overcurrent_event(int port, int is_overcurrented)
 static void charger_set_buck_boost_mode(void)
 {
 	int reg;
-	/* Reduce Buck-boost mode switching frequency to improve power efficiency. */
+	/* Reduce Buck-boost mode switching frequency to improve power
+	 * efficiency. */
 	if (i2c_read16(I2C_PORT_CHARGER, I2C_ADDR_CHARGER_FLAGS,
-			ISL9238_REG_CONTROL3, &reg) == EC_SUCCESS) {
+		       ISL9238_REG_CONTROL3, &reg) == EC_SUCCESS) {
 		reg |= ISL9238_C3_BB_SWITCHING_PERIOD;
 		if (i2c_write16(I2C_PORT_CHARGER, I2C_ADDR_CHARGER_FLAGS,
 				ISL9238_REG_CONTROL3, reg))
@@ -278,5 +310,17 @@ static void charger_set_buck_boost_mode(void)
 static void board_init(void)
 {
 	charger_set_buck_boost_mode();
+
+	is_support_syv_ppc = board_is_syv_ppc();
+
+	board_update_ppc_config_from_board();
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+int ppc_get_alert_status(int port)
+{
+	if (port == 0)
+		return gpio_get_level(GPIO_USB_PD_C0_INT_ODL) == 0;
+
+	return gpio_get_level(GPIO_USB_PD_C1_INT_ODL) == 0;
+}
diff --git a/board/fleex/board.h b/board/fleex/board.h
index fe48f4e232..3095fad271 100644
--- a/board/fleex/board.h
+++ b/board/fleex/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,6 +13,8 @@
 #define VARIANT_OCTOPUS_CHARGER_ISL9238
 #include "baseboard.h"
 
+#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD
+
 /* EC console commands  */
 #define CONFIG_CMD_ACCELS
 #define CONFIG_CMD_ACCEL_INFO
@@ -31,8 +33,8 @@
 #define CONFIG_USB_PD_RESET_MIN_BATT_SOC 2
 
 /* Sensors */
-#define CONFIG_ACCEL_LIS2DE		/* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM	/* Base accel */
+#define CONFIG_ACCEL_LIS2DE /* Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
 /* Sensors without hardware FIFO are in forced mode */
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
 #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
@@ -65,16 +67,23 @@
 
 #define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+/* Additional PPC second source */
+#define CONFIG_USBC_PPC_SYV682X
+#define CONFIG_USBC_PPC_DEDICATED_INT
+/* SYV682 isn't connected to CC, so TCPC must provide VCONN */
+#define CONFIG_USBC_PPC_SYV682X_NO_CC
+
 #ifndef __ASSEMBLER__
 
 #include "gpio_signal.h"
 #include "registers.h"
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_AMB,		/* ADC0 */
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC1 */
-	ADC_VBUS_C0,			/* ADC9 */
-	ADC_VBUS_C1,			/* ADC4 */
+	ADC_TEMP_SENSOR_AMB, /* ADC0 */
+	ADC_TEMP_SENSOR_CHARGER, /* ADC1 */
+	ADC_VBUS_C0, /* ADC9 */
+	ADC_VBUS_C1, /* ADC4 */
 	ADC_CH_COUNT
 };
 
@@ -85,18 +94,10 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_COUNT };
 
 /* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
diff --git a/board/fleex/build.mk b/board/fleex/build.mk
index 7e806f4667..0eab0adc21 100644
--- a/board/fleex/build.mk
+++ b/board/fleex/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/fleex/ec.tasklist b/board/fleex/ec.tasklist
index d98db145e7..977b8b01be 100644
--- a/board/fleex/ec.tasklist
+++ b/board/fleex/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/fleex/gpio.inc b/board/fleex/gpio.inc
index 726f2da951..0b74f8fa76 100644
--- a/board/fleex/gpio.inc
+++ b/board/fleex/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -152,11 +152,12 @@ GPIO(EC_GPIO03, 	 PIN(0, 3), GPIO_INPUT)		/* TP only */
 /* MKBP event synchronization */
 GPIO(EC_INT_L,		 PIN(9, 4), GPIO_ODR_HIGH)	/* EC_AP_INT_ODL */
 
+GPIO(PPC_ID,		PIN(9, 7), GPIO_INPUT | GPIO_PULL_DOWN)	/* PPC ID Pin */
+
 /* Unused Pins */
 GPIO(CHARGER_PMON,	PIN(4, 2), GPIO_INPUT)
 GPIO(CHARGER_IADP,	PIN(4, 3), GPIO_INPUT)
 GPIO(EC_GPIO57,		PIN(5, 7), GPIO_INPUT | GPIO_PULL_UP)	/* TP Only */
-GPIO(EC_GPIO97,		PIN(9, 7), GPIO_INPUT | GPIO_PULL_UP)	/* TP Only */
 GPIO(EC_I2S_SFRM,	PIN(A, 5), GPIO_INPUT | GPIO_SEL_1P8V)
 GPIO(EC_I2S_SCLK,	PIN(A, 7), GPIO_INPUT | GPIO_SEL_1P8V)
 GPIO(EC_I2S_TX_PCH_RX,	PIN(B, 0), GPIO_INPUT | GPIO_SEL_1P8V)
diff --git a/board/fleex/led.c b/board/fleex/led.c
index d502c16797..4ba3c18457 100644
--- a/board/fleex/led.c
+++ b/board/fleex/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,38 +10,48 @@
 #include "led_common.h"
 #include "led_onoff_states.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
-const int led_charge_lvl_1 = 10;
+__override const int led_charge_lvl_1 = 10;
 
-const int led_charge_lvl_2 = 100;
+__override const int led_charge_lvl_2 = 100;
 
 /* Fleex: Note there is only LED for charge / power */
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_S5]     = {{LED_OFF,	     LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     1 * LED_ONE_SEC },
+					   { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_WHITE,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 BUILD_ASSERT(ARRAY_SIZE(led_bat_state_table) == LED_NUM_STATES);
 
 const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-void led_set_color_battery(enum ec_led_colors color)
+__override void led_set_color_battery(enum ec_led_colors color)
 {
 	switch (color) {
 	case EC_LED_COLOR_WHITE:
@@ -76,4 +86,3 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 
 	return EC_SUCCESS;
 }
-
diff --git a/board/fleex/usb_pd_policy.c b/board/fleex/usb_pd_policy.c
index 82922f9a4d..bfcf4484e4 100644
--- a/board/fleex/usb_pd_policy.c
+++ b/board/fleex/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/fleex/vif_override.xml b/board/fleex/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/fleex/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/fluffy/board.c b/board/fluffy/board.c
index 264ffc4478..b16170148e 100644
--- a/board/fluffy/board.c
+++ b/board/fluffy/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,34 +6,34 @@
 /* Fluffy configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "common.h"
 #include "console.h"
 #include "ec_version.h"
 #include "hooks.h"
 #include "i2c.h"
-#include "usb_descriptor.h"
 #include "registers.h"
 #include "timer.h"
+#include "usb_descriptor.h"
 #include "usb_pd.h"
 #include "util.h"
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
 /******************************************************************************
  * Define the strings used in our USB descriptors.
  */
 
 const void *const usb_strings[] = {
-	[USB_STR_DESC]         = usb_string_desc,
-	[USB_STR_VENDOR]       = USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]      = USB_STRING_DESC("Fluffy"),
+	[USB_STR_DESC] = usb_string_desc,
+	[USB_STR_VENDOR] = USB_STRING_DESC("Google LLC"),
+	[USB_STR_PRODUCT] = USB_STRING_DESC("Fluffy"),
 	/* This gets filled in at runtime. */
-	[USB_STR_SERIALNO]     = USB_STRING_DESC(""),
-	[USB_STR_VERSION]      = USB_STRING_DESC(CROS_EC_VERSION32),
+	[USB_STR_SERIALNO] = USB_STRING_DESC(""),
+	[USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32),
 	[USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Fluffy Shell"),
 };
 
@@ -78,7 +78,7 @@ static void print_port_status(void)
 	CPRINTS("USB MUX: %s", gpio_get_level(GPIO_EN_USB_MUX2) ? "ON" : "OFF");
 }
 
-static int command_cc_flip(int argc, char *argv[])
+static int command_cc_flip(int argc, const char *argv[])
 {
 	int enable;
 
@@ -107,20 +107,19 @@ static int command_cc_flip(int argc, char *argv[])
 	print_port_status();
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(ccflip, command_cc_flip,
-			"<enable/disable>",
+DECLARE_CONSOLE_COMMAND(ccflip, command_cc_flip, "<enable/disable>",
 			"enable or disable flipping CC orientation");
 /*
  * Support tca6416 I2C ioexpander.
  */
-#define GPIOX_I2C_ADDR_FLAGS	0x20
-#define GPIOX_IN_PORT_A		0x0
-#define GPIOX_IN_PORT_B		0x1
-#define GPIOX_OUT_PORT_A	0x2
-#define GPIOX_OUT_PORT_B	0x3
-#define GPIOX_DIR_PORT_A	0x6
-#define GPIOX_DIR_PORT_B	0x7
-#define I2C_PORT_MASTER		1
+#define GPIOX_I2C_ADDR_FLAGS 0x20
+#define GPIOX_IN_PORT_A 0x0
+#define GPIOX_IN_PORT_B 0x1
+#define GPIOX_OUT_PORT_A 0x2
+#define GPIOX_OUT_PORT_B 0x3
+#define GPIOX_DIR_PORT_A 0x6
+#define GPIOX_DIR_PORT_B 0x7
+#define I2C_PORT_MASTER 1
 
 static void i2c_expander_init(void)
 {
@@ -129,12 +128,12 @@ static void i2c_expander_init(void)
 	/*
 	 * Setup P00, P02, P04, P10, and P12 on the I/O expander as an output.
 	 */
-	i2c_write8(I2C_PORT_MASTER, GPIOX_I2C_ADDR_FLAGS,
-		   GPIOX_DIR_PORT_A, 0xea);
-	i2c_write8(I2C_PORT_MASTER, GPIOX_I2C_ADDR_FLAGS,
-		   GPIOX_DIR_PORT_B, 0xfa);
+	i2c_write8(I2C_PORT_MASTER, GPIOX_I2C_ADDR_FLAGS, GPIOX_DIR_PORT_A,
+		   0xea);
+	i2c_write8(I2C_PORT_MASTER, GPIOX_I2C_ADDR_FLAGS, GPIOX_DIR_PORT_B,
+		   0xfa);
 }
-DECLARE_HOOK(HOOK_INIT, i2c_expander_init, HOOK_PRIO_INIT_I2C+1);
+DECLARE_HOOK(HOOK_INIT, i2c_expander_init, HOOK_PRIO_INIT_I2C + 1);
 
 /* Write to a GPIO register on the tca6416 I2C ioexpander. */
 static void write_ioexpander(int bank, int gpio, int reg, int val)
@@ -142,15 +141,13 @@ static void write_ioexpander(int bank, int gpio, int reg, int val)
 	int tmp;
 
 	/* Read output port register */
-	i2c_read8(I2C_PORT_MASTER, GPIOX_I2C_ADDR_FLAGS,
-		  reg + bank, &tmp);
+	i2c_read8(I2C_PORT_MASTER, GPIOX_I2C_ADDR_FLAGS, reg + bank, &tmp);
 	if (val)
 		tmp |= BIT(gpio);
 	else
 		tmp &= ~BIT(gpio);
 	/* Write back modified output port register */
-	i2c_write8(I2C_PORT_MASTER, GPIOX_I2C_ADDR_FLAGS,
-		   reg + bank, tmp);
+	i2c_write8(I2C_PORT_MASTER, GPIOX_I2C_ADDR_FLAGS, reg + bank, tmp);
 }
 
 enum led_ch {
@@ -228,7 +225,6 @@ static void board_init(void)
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
-
 enum usb_mux {
 	USB_MUX0 = 0,
 	USB_MUX1,
@@ -262,7 +258,7 @@ static void set_mux(enum usb_mux mux, uint8_t val)
 		break;
 
 	default:
-		break;
+		return;
 	}
 
 	val &= 0x7;
@@ -273,7 +269,7 @@ static void set_mux(enum usb_mux mux, uint8_t val)
 }
 
 /* This function assumes only 1 port works at a time. */
-static int command_portctl(int argc, char **argv)
+static int command_portctl(int argc, const char **argv)
 {
 	int port;
 	int enable;
@@ -294,7 +290,7 @@ static int command_portctl(int argc, char **argv)
 
 	gpio_set_level(enabled_port, 0);
 	if (enabled_port != GPIO_EN_C0 + port)
-		CPRINTS("Port %d: disabled", enabled_port-GPIO_EN_C0);
+		CPRINTS("Port %d: disabled", enabled_port - GPIO_EN_C0);
 
 	/* Allow time for an "unplug" to allow VBUS and CC to fall. */
 	usleep(1 * SECOND);
@@ -310,17 +306,17 @@ static int command_portctl(int argc, char **argv)
 		gpio_set_level(enabled_port, 1);
 
 		if (port < 8) {
-			set_mux(USB_MUX0, 7-port);
+			set_mux(USB_MUX0, 7 - port);
 			set_mux(USB_MUX2, 3);
 		} else if (port < 16) {
 			if (port < 14)
-				set_mux(USB_MUX1, 5-(port-8));
+				set_mux(USB_MUX1, 5 - (port - 8));
 			else
-				set_mux(USB_MUX1, 7-(port-14));
+				set_mux(USB_MUX1, 7 - (port - 14));
 
 			set_mux(USB_MUX2, 1);
 		} else {
-			set_mux(USB_MUX2, 7-(port-16));
+			set_mux(USB_MUX2, 7 - (port - 16));
 		}
 
 		gpio_set_level(GPIO_EN_USB_MUX2, 1);
@@ -338,11 +334,11 @@ DECLARE_CONSOLE_COMMAND(portctl, command_portctl,
 			"<port# 0-19> <enable/disable>",
 			"enable or disable a port");
 
-static int command_status(int argc, char **argv)
+static int command_status(int argc, const char **argv)
 {
 	int vbus_mv = adc_read_channel(ADC_PPVAR_VBUS_DUT);
 
-	CPRINTS("PPVAR_VBUS_DUT: %dmV (raw: %d)", vbus_mv*7692/1000,
+	CPRINTS("PPVAR_VBUS_DUT: %dmV (raw: %d)", vbus_mv * 7692 / 1000,
 		vbus_mv);
 	print_port_status();
 
@@ -389,7 +385,8 @@ void show_output_voltage_on_leds(void)
 			set_led(i, i < max_on_exclusive);
 
 		act = (vbus_mv * 76667) / 10000;
-		if ((vbus_mv > prev_vbus_mv+2) || (vbus_mv < prev_vbus_mv-2)) {
+		if ((vbus_mv > prev_vbus_mv + 2) ||
+		    (vbus_mv < prev_vbus_mv - 2)) {
 			CPRINTS("PPVAR_VBUS_DUT: %d mV (raw: %d)", act,
 				vbus_mv);
 			prev_vbus_mv = vbus_mv;
@@ -401,6 +398,5 @@ void show_output_voltage_on_leds(void)
 	 * a hook with a HOOK_TICK period is to allow the LED sweep sequence
 	 * when the board boots up.
 	 */
-	hook_call_deferred(&show_output_voltage_on_leds_data,
-			   500 * MSEC);
+	hook_call_deferred(&show_output_voltage_on_leds_data, 500 * MSEC);
 }
diff --git a/board/fluffy/board.h b/board/fluffy/board.h
index 41c01bd8fa..604e67d9b8 100644
--- a/board/fluffy/board.h
+++ b/board/fluffy/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -29,26 +29,25 @@
 #define DEFAULT_SERIALNO "Uninitialized"
 
 /* USB interface indexes (use define rather than enum to expand them) */
-#define USB_IFACE_CONSOLE	0
-#define USB_IFACE_COUNT		1
+#define USB_IFACE_CONSOLE 0
+#define USB_IFACE_COUNT 1
 
 /* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL		0
-#define USB_EP_CONSOLE		1
-#define USB_EP_COUNT		2
+#define USB_EP_CONTROL 0
+#define USB_EP_CONSOLE 1
+#define USB_EP_COUNT 2
 
 /* Optional features */
-#define CONFIG_STM_HWTIMER32
 
 #define CONFIG_ADC
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_CONTROLLER
 
 #ifndef __ASSEMBLER__
 
 /* Timer selection */
 #define TIM_CLOCK32 2
-#define TIM_ADC     3
+#define TIM_ADC 3
 
 #include "gpio_signal.h"
 
diff --git a/board/fluffy/build.mk b/board/fluffy/build.mk
index b6761a4692..82aa7522d0 100644
--- a/board/fluffy/build.mk
+++ b/board/fluffy/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -10,9 +10,4 @@ CHIP:=stm32
 CHIP_FAMILY:=stm32f0
 CHIP_VARIANT:=stm32f07x
 
-# Use coreboot-sdk
-$(call set-option,CROSS_COMPILE_arm,\
-	$(CROSS_COMPILE_coreboot_sdk_arm),\
-	/opt/coreboot-sdk/bin/arm-eabi-)
-
 board-y=board.o
diff --git a/board/fluffy/ec.tasklist b/board/fluffy/ec.tasklist
index c732944a23..9c45739414 100644
--- a/board/fluffy/ec.tasklist
+++ b/board/fluffy/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/fluffy/gpio.inc b/board/fluffy/gpio.inc
index 4c802554f9..532422ae5b 100644
--- a/board/fluffy/gpio.inc
+++ b/board/fluffy/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/foob/battery.c b/board/foob/battery.c
index 01a6654920..fe5692eec2 100644
--- a/board/foob/battery.c
+++ b/board/foob/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/foob/board.c b/board/foob/board.c
index 87a5c656de..65fafddd45 100644
--- a/board/foob/board.c
+++ b/board/foob/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,7 @@
 /* Phaser board-specific configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
+#include "battery_smart.h"
 #include "button.h"
 #include "charge_state.h"
 #include "common.h"
@@ -24,19 +24,18 @@
 #include "power.h"
 #include "power_button.h"
 #include "switch.h"
-#include "task.h"
 #include "tablet_mode.h"
-#include "tcpci.h"
+#include "task.h"
+#include "tcpm/tcpci.h"
 #include "temp_sensor.h"
-#include "thermistor.h"
+#include "temp_sensor/thermistor.h"
 #include "util.h"
-#include "battery_smart.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define USB_PD_PORT_ANX7447	0
-#define USB_PD_PORT_PS8751	1
+#define USB_PD_PORT_ANX7447 0
+#define USB_PD_PORT_PS8751 1
 
 static uint8_t sku_id;
 
@@ -61,31 +60,31 @@ static void ppc_interrupt(enum gpio_signal signal)
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_AMB] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_AMB] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				  ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_CHARGER] = { "TEMP_CHARGER", NPCX_ADC_CH1,
+				      ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 },
 	/* Vbus sensing (1/10 voltage divider). */
-	[ADC_VBUS_C0] = {
-		"VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
-	[ADC_VBUS_C1] = {
-		"VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
+	[ADC_VBUS_C0] = { "VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT * 10,
+			  ADC_READ_MAX + 1, 0 },
+	[ADC_VBUS_C1] = { "VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT * 10,
+			  ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp,
-				 .idx = 0},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
+	[TEMP_SENSOR_BATTERY] = { .name = "Battery",
+				  .type = TEMP_SENSOR_TYPE_BATTERY,
+				  .read = charge_get_battery_temp,
+				  .idx = 0 },
+	[TEMP_SENSOR_AMBIENT] = { .name = "Ambient",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_51k1_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_AMB },
+	[TEMP_SENSOR_CHARGER] = { .name = "Charger",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_13k7_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_CHARGER },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -95,11 +94,9 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrix to rotate lid and base sensor into standard reference frame */
-const mat33_fp_t standard_rot_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
+const mat33_fp_t standard_rot_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				      { 0, FLOAT_TO_FP(-1), 0 },
+				      { 0, 0, FLOAT_TO_FP(1) } };
 
 /* sensor private data */
 static struct stprivate_data g_lis2dh_data;
@@ -145,8 +142,6 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_base_mutex,
 		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
 				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
 		.port = I2C_PORT_SENSOR,
 		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
 		.rot_standard_ref = &standard_rot_ref,
@@ -177,8 +172,6 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_base_mutex,
 		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
 				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
 		.port = I2C_PORT_SENSOR,
 		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
 		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
@@ -222,9 +215,8 @@ static void cbi_init(void)
 }
 DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1);
 
-#ifndef TEST_BUILD
 /* This callback disables keyboard when convertibles are fully open */
-void lid_angle_peripheral_enable(int enable)
+__override void lid_angle_peripheral_enable(int enable)
 {
 	/*
 	 * If the lid is in tablet position via other sensors,
@@ -237,7 +229,6 @@ void lid_angle_peripheral_enable(int enable)
 	if (board_is_convertible())
 		keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
 }
-#endif
 
 int board_is_lid_angle_tablet_mode(void)
 {
@@ -245,11 +236,11 @@ int board_is_lid_angle_tablet_mode(void)
 }
 
 /* Battery functions */
-#define SB_OPTIONALMFG_FUNCTION2		0x3e
+#define SB_OPTIONALMFG_FUNCTION2 0x3e
 /* Optional mfg function2 */
-#define SMART_QUICK_CHARGE			(1<<12)
+#define SMART_QUICK_CHARGE (1 << 12)
 /* Quick charge support */
-#define MODE_QUICK_CHARGE_SUPPORT		(1<<4)
+#define MODE_QUICK_CHARGE_SUPPORT (1 << 4)
 
 static void sb_quick_charge_mode(int enable)
 {
diff --git a/board/foob/board.h b/board/foob/board.h
index 9e1c4d093c..f6d0f20607 100644
--- a/board/foob/board.h
+++ b/board/foob/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,12 +13,13 @@
 #define VARIANT_OCTOPUS_CHARGER_ISL9238
 #include "baseboard.h"
 
+#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD
+
 #define CONFIG_VOLUME_BUTTONS
 #define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
 #define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
 
 #define CONFIG_LED_COMMON
-#define CONFIG_LED_POWER_LED
 #define CONFIG_TEMP_SENSOR
 #define CONFIG_THERMISTOR
 #define CONFIG_STEINHART_HART_3V3_13K7_47K_4050B
@@ -29,8 +30,8 @@
 #define CONFIG_CMD_ACCEL_INFO
 
 /* Sensors */
-#define CONFIG_ACCEL_LIS2DE             /* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM        /* Base accel */
+#define CONFIG_ACCEL_LIS2DE /* Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
 /* Sensors without hardware FIFO are in forced mode */
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
 
@@ -49,10 +50,10 @@
 #include "registers.h"
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_AMB,		/* ADC0 */
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC1 */
-	ADC_VBUS_C0,			/* ADC9 */
-	ADC_VBUS_C1,			/* ADC4 */
+	ADC_TEMP_SENSOR_AMB, /* ADC0 */
+	ADC_TEMP_SENSOR_CHARGER, /* ADC1 */
+	ADC_VBUS_C0, /* ADC9 */
+	ADC_VBUS_C1, /* ADC4 */
 	ADC_CH_COUNT,
 };
 
@@ -63,18 +64,10 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_COUNT };
 
 /* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
diff --git a/board/foob/build.mk b/board/foob/build.mk
index 137e208b53..fee77e38b5 100644
--- a/board/foob/build.mk
+++ b/board/foob/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/foob/ec.tasklist b/board/foob/ec.tasklist
index 6eac78a042..6c56976091 100644
--- a/board/foob/ec.tasklist
+++ b/board/foob/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/foob/gpio.inc b/board/foob/gpio.inc
index ad6773a211..3a553f6e91 100644
--- a/board/foob/gpio.inc
+++ b/board/foob/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/foob/led.c b/board/foob/led.c
index 0b582e9ca6..a7271f95d3 100644
--- a/board/foob/led.c
+++ b/board/foob/led.c
@@ -1,53 +1,57 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Power and battery LED control for Phaser
  */
 
+#include "chipset.h"
 #include "ec_commands.h"
 #include "gpio.h"
 #include "led_common.h"
 #include "led_onoff_states.h"
-#include "chipset.h"
 
 #define LED_ON_LVL 0
 #define LED_OFF_LVL 1
 
-const int led_charge_lvl_1 = 5;
+__override const int led_charge_lvl_1 = 5;
 
-const int led_charge_lvl_2 = 97;
+__override const int led_charge_lvl_2 = 97;
 
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
 
-const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-					{LED_OFF,	   0.5 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 3 * LED_ONE_SEC },
+					       { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-	EC_LED_ID_BATTERY_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED,
+					     EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-void led_set_color_power(enum ec_led_colors color)
+__override void led_set_color_power(enum ec_led_colors color)
 {
 	if (color == EC_LED_COLOR_WHITE)
 		gpio_set_level(GPIO_PWR_LED_WHITE_L, LED_ON_LVL);
@@ -56,7 +60,7 @@ void led_set_color_power(enum ec_led_colors color)
 		gpio_set_level(GPIO_PWR_LED_WHITE_L, LED_OFF_LVL);
 }
 
-void led_set_color_battery(enum ec_led_colors color)
+__override void led_set_color_battery(enum ec_led_colors color)
 {
 	switch (color) {
 	case EC_LED_COLOR_RED:
@@ -109,4 +113,3 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 
 	return EC_SUCCESS;
 }
-
diff --git a/board/foob/vif_override.xml b/board/foob/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/foob/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/fusb307bgevb/board.c b/board/fusb307bgevb/board.c
index 35dececafb..2b9f4dac2f 100644
--- a/board/fusb307bgevb/board.c
+++ b/board/fusb307bgevb/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,15 +17,15 @@
 #include "task.h"
 #include "timer.h"
 #include "usart-stm32f0.h"
-#include "usart_tx_dma.h"
 #include "usart_rx_dma.h"
-#include "usb_gpio.h"
+#include "usart_tx_dma.h"
 #include "usb-stream.h"
 #include "usb_common.h"
+#include "usb_gpio.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
@@ -40,12 +40,13 @@ static int count;
 
 static void button_enter_event_deferred(void)
 {
-	uint32_t ma, mv;
+	uint32_t ma, mv, unused;
 
 	CPRINTS("Button enter event");
 
 	if (count >= 0 && count < pd_get_src_cap_cnt(0)) {
-		pd_extract_pdo_power(pd_get_src_caps(0)[count], &ma, &mv);
+		pd_extract_pdo_power(pd_get_src_caps(0)[count], &ma, &mv,
+				     &unused);
 		pd_request_source_voltage(0, mv);
 	} else {
 		CPRINTS("ERROR: button counter weird value.");
@@ -62,7 +63,7 @@ void button_enter_event(enum gpio_signal signal)
 static void button_refresh_event_deferred(void)
 {
 	int i;
-	uint32_t ma, mv;
+	uint32_t ma, mv, unused;
 	char c[20];
 
 	CPRINTS("Button refresh event");
@@ -71,10 +72,13 @@ static void button_refresh_event_deferred(void)
 	/* Display supply voltage on first page. */
 	lcd_clear();
 	for (i = 0; i < MIN(pd_get_src_cap_cnt(0), 4); i++) {
-		pd_extract_pdo_power(pd_get_src_caps(0)[i], &ma, &mv);
-		snprintf(c, ARRAY_SIZE(c), "[%d] %dmV %dmA", i, mv, ma);
-		lcd_set_cursor(0, i);
-		lcd_print_string(c);
+		int rv;
+		pd_extract_pdo_power(pd_get_src_caps(0)[i], &ma, &mv, &unused);
+		rv = snprintf(c, ARRAY_SIZE(c), "[%d] %dmV %dmA", i, mv, ma);
+		if (rv > 0) {
+			lcd_set_cursor(0, i);
+			lcd_print_string(c);
+		}
 	}
 
 	/* Display selector */
@@ -91,7 +95,7 @@ void button_refresh_event(enum gpio_signal signal)
 static void button_down_event_deferred(void)
 {
 	int i;
-	uint32_t ma, mv;
+	uint32_t ma, mv, unused;
 	char c[20];
 
 	CPRINTS("Button down event");
@@ -106,19 +110,29 @@ static void button_down_event_deferred(void)
 	if (count == 0) {
 		lcd_clear();
 		for (i = 0; i < MIN(pd_get_src_cap_cnt(0), 4); i++) {
-			pd_extract_pdo_power(pd_get_src_caps(0)[i], &ma, &mv);
-			snprintf(c, ARRAY_SIZE(c), "[%d] %dmV %dmA", i, mv, ma);
-			lcd_set_cursor(0, i);
-			lcd_print_string(c);
+			int rv;
+			pd_extract_pdo_power(pd_get_src_caps(0)[i], &ma, &mv,
+					     &unused);
+			rv = snprintf(c, ARRAY_SIZE(c), "[%d] %dmV %dmA", i, mv,
+				      ma);
+			if (rv > 0) {
+				lcd_set_cursor(0, i);
+				lcd_print_string(c);
+			}
 		}
 	}
 	if (count == 4) {
 		lcd_clear();
 		for (i = 4; i < pd_get_src_cap_cnt(0); i++) {
-			pd_extract_pdo_power(pd_get_src_caps(0)[i], &ma, &mv);
-			snprintf(c, ARRAY_SIZE(c), "[%d] %dmV %dmA", i, mv, ma);
-			lcd_set_cursor(0, i - 4);
-			lcd_print_string(c);
+			int rv;
+			pd_extract_pdo_power(pd_get_src_caps(0)[i], &ma, &mv,
+					     &unused);
+			rv = snprintf(c, ARRAY_SIZE(c), "[%d] %dmV %dmA", i, mv,
+				      ma);
+			if (rv > 0) {
+				lcd_set_cursor(0, i - 4);
+				lcd_print_string(c);
+			}
 		}
 	}
 
@@ -141,6 +155,7 @@ void button_down_event(enum gpio_signal signal)
 /******************************************************************************
  * Build GPIO tables and expose a subset of the GPIOs over USB.
  */
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 static enum gpio_signal const usb_gpio_list[] = {
@@ -153,20 +168,15 @@ static enum gpio_signal const usb_gpio_list[] = {
  * This instantiates struct usb_gpio_config const usb_gpio, plus several other
  * variables, all named something beginning with usb_gpio_
  */
-USB_GPIO_CONFIG(usb_gpio,
-		usb_gpio_list,
-		USB_IFACE_GPIO,
-		USB_EP_GPIO);
+USB_GPIO_CONFIG(usb_gpio, usb_gpio_list, USB_IFACE_GPIO, USB_EP_GPIO);
 
 /******************************************************************************
  * Setup USART1 as a loopback device, it just echo's back anything sent to it.
  */
 static struct usart_config const loopback_usart;
 
-static struct queue const loopback_queue =
-	QUEUE_DIRECT(64, uint8_t,
-		     loopback_usart.producer,
-		     loopback_usart.consumer);
+static struct queue const loopback_queue = QUEUE_DIRECT(
+	64, uint8_t, loopback_usart.producer, loopback_usart.consumer);
 
 static struct usart_rx_dma const loopback_rx_dma =
 	USART_RX_DMA(STM32_DMAC_CH3, 8);
@@ -174,14 +184,9 @@ static struct usart_rx_dma const loopback_rx_dma =
 static struct usart_tx_dma const loopback_tx_dma =
 	USART_TX_DMA(STM32_DMAC_CH2, 16);
 
-static struct usart_config const loopback_usart =
-	USART_CONFIG(usart1_hw,
-		     loopback_rx_dma.usart_rx,
-		     loopback_tx_dma.usart_tx,
-		     115200,
-		     0,
-		     loopback_queue,
-		     loopback_queue);
+static struct usart_config const loopback_usart = USART_CONFIG(
+	usart1_hw, loopback_rx_dma.usart_rx, loopback_tx_dma.usart_tx, 115200,
+	0, loopback_queue, loopback_queue);
 
 /******************************************************************************
  * Forward USART4 as a simple USB serial interface.
@@ -189,46 +194,34 @@ static struct usart_config const loopback_usart =
 static struct usart_config const forward_usart;
 struct usb_stream_config const forward_usb;
 
-static struct queue const usart_to_usb = QUEUE_DIRECT(64, uint8_t,
-						      forward_usart.producer,
-						      forward_usb.consumer);
-static struct queue const usb_to_usart = QUEUE_DIRECT(64, uint8_t,
-						      forward_usb.producer,
-						      forward_usart.consumer);
+static struct queue const usart_to_usb =
+	QUEUE_DIRECT(64, uint8_t, forward_usart.producer, forward_usb.consumer);
+static struct queue const usb_to_usart =
+	QUEUE_DIRECT(64, uint8_t, forward_usb.producer, forward_usart.consumer);
 
 static struct usart_tx_dma const forward_tx_dma =
 	USART_TX_DMA(STM32_DMAC_CH7, 16);
 
 static struct usart_config const forward_usart =
-	USART_CONFIG(usart4_hw,
-		     usart_rx_interrupt,
-		     forward_tx_dma.usart_tx,
-		     115200,
-		     0,
-		     usart_to_usb,
-		     usb_to_usart);
-
-#define USB_STREAM_RX_SIZE	16
-#define USB_STREAM_TX_SIZE	16
-
-USB_STREAM_CONFIG(forward_usb,
-		  USB_IFACE_STREAM,
-		  USB_STR_STREAM_NAME,
-		  USB_EP_STREAM,
-		  USB_STREAM_RX_SIZE,
-		  USB_STREAM_TX_SIZE,
-		  usb_to_usart,
-		  usart_to_usb)
+	USART_CONFIG(usart4_hw, usart_rx_interrupt, forward_tx_dma.usart_tx,
+		     115200, 0, usart_to_usb, usb_to_usart);
+
+#define USB_STREAM_RX_SIZE 16
+#define USB_STREAM_TX_SIZE 16
+
+USB_STREAM_CONFIG(forward_usb, USB_IFACE_STREAM, USB_STR_STREAM_NAME,
+		  USB_EP_STREAM, USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE,
+		  usb_to_usart, usart_to_usb)
 
 /******************************************************************************
  * Define the strings used in our USB descriptors.
  */
 const void *const usb_strings[] = {
-	[USB_STR_DESC]         = usb_string_desc,
-	[USB_STR_VENDOR]       = USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]      = USB_STRING_DESC("fusb307bgevb"),
-	[USB_STR_VERSION]      = USB_STRING_DESC(CROS_EC_VERSION32),
-	[USB_STR_STREAM_NAME]  = USB_STRING_DESC("Forward"),
+	[USB_STR_DESC] = usb_string_desc,
+	[USB_STR_VENDOR] = USB_STRING_DESC("Google LLC"),
+	[USB_STR_PRODUCT] = USB_STRING_DESC("fusb307bgevb"),
+	[USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32),
+	[USB_STR_STREAM_NAME] = USB_STRING_DESC("Forward"),
 	[USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Shell"),
 };
 
@@ -237,9 +230,11 @@ BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
 /******************************************************************************
  * I2C interface.
  */
-const struct i2c_port_t i2c_ports[] = {
-	{"tcpc", I2C_PORT_TCPC, 400 /* kHz */, GPIO_I2C2_SCL, GPIO_I2C2_SDA}
-};
+const struct i2c_port_t i2c_ports[] = { { .name = "tcpc",
+					  .port = I2C_PORT_TCPC,
+					  .kbps = 400 /* kHz */,
+					  .scl = GPIO_I2C2_SCL,
+					  .sda = GPIO_I2C2_SDA } };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
 /******************************************************************************
@@ -250,13 +245,12 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = I2C_PORT_TCPC,
-			.addr_flags = FUSB307_I2C_SLAVE_ADDR_FLAGS,
+			.addr_flags = FUSB307_I2C_ADDR_FLAGS,
 		},
 		.drv = &fusb307_tcpm_drv,
 	},
 };
 
-
 uint16_t tcpc_get_alert_status(void)
 {
 	uint16_t status = 0;
@@ -320,6 +314,5 @@ static void board_init(void)
 	queue_init(&usb_to_usart);
 	usart_init(&loopback_usart);
 	usart_init(&forward_usart);
-
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/fusb307bgevb/board.h b/board/fusb307bgevb/board.h
index 2497dc7c69..8d2fdfcfed 100644
--- a/board/fusb307bgevb/board.h
+++ b/board/fusb307bgevb/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,6 +8,7 @@
 #ifndef __CROS_EC_BOARD_H
 #define __CROS_EC_BOARD_H
 
+#define CONFIG_LTO
 
 /* 48 MHz SYSCLK clock frequency */
 #define CPU_CLOCK 48000000
@@ -28,10 +29,9 @@
 #define CONFIG_UART_CONSOLE 2
 
 /* Optional features */
-#define CONFIG_STM_HWTIMER32
 #define CONFIG_HW_CRC
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_CONTROLLER
 
 /* USB Configuration */
 #define CONFIG_USB
@@ -52,16 +52,15 @@
 #define CONFIG_USB_PD_TCPM_FUSB307
 
 /* delay to turn on/off vconn */
-#define PD_VCONN_SWAP_DELAY 5000 /* us */
 /* Define operating power and max power */
 #define PD_OPERATING_POWER_MW 15000
 #define PD_MAX_VOLTAGE_MV 20000
 #define PD_MAX_CURRENT_MA 3000
-#define PD_MAX_POWER_MW       ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
+#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
 
 /* Degine board specific type-C power constants */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY 160000  /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 160000 /* us */
 
 /* I2C master port connected to the TCPC */
 #define I2C_PORT_TCPC 1
@@ -70,23 +69,24 @@
 #define LCD_SLAVE_ADDR 0x27
 
 /* USB interface indexes (use define rather than enum to expand them) */
-#define USB_IFACE_STREAM  0
-#define USB_IFACE_GPIO    1
-#define USB_IFACE_SPI     2
+#define USB_IFACE_STREAM 0
+#define USB_IFACE_GPIO 1
+#define USB_IFACE_SPI 2
 #define USB_IFACE_CONSOLE 3
-#define USB_IFACE_COUNT   4
+#define USB_IFACE_COUNT 4
 
 /* USB endpoint indexes (use define rather than enum to expand them) */
 #define USB_EP_CONTROL 0
-#define USB_EP_STREAM  1
-#define USB_EP_GPIO    2
-#define USB_EP_SPI     3
+#define USB_EP_STREAM 1
+#define USB_EP_GPIO 2
+#define USB_EP_SPI 3
 #define USB_EP_CONSOLE 4
-#define USB_EP_COUNT   5
+#define USB_EP_COUNT 5
 
 /* Enable control of GPIOs over USB */
 #define CONFIG_USB_GPIO
 
+#undef CONFIG_CMD_GETTIME
 #undef CONFIG_WATCHDOG_HELP
 #undef CONFIG_LID_SWITCH
 
diff --git a/board/fusb307bgevb/build.mk b/board/fusb307bgevb/build.mk
index 1372562107..923b144165 100644
--- a/board/fusb307bgevb/build.mk
+++ b/board/fusb307bgevb/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/fusb307bgevb/ec.tasklist b/board/fusb307bgevb/ec.tasklist
index e25b8f7a68..bca2d075be 100644
--- a/board/fusb307bgevb/ec.tasklist
+++ b/board/fusb307bgevb/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/fusb307bgevb/gpio.inc b/board/fusb307bgevb/gpio.inc
index 16a845576d..ba3b84fb08 100644
--- a/board/fusb307bgevb/gpio.inc
+++ b/board/fusb307bgevb/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/fusb307bgevb/lcd.c b/board/fusb307bgevb/lcd.c
index 892888329e..f907de7462 100644
--- a/board/fusb307bgevb/lcd.c
+++ b/board/fusb307bgevb/lcd.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -26,17 +26,17 @@ static struct lcd_state_info state = {
 /* write either command or data */
 static void expander_write(uint8_t data)
 {
-	i2c_write8(I2C_PORT_TCPC, LCD_SLAVE_ADDR, 0x00, data |
-		state.backlightval);
+	i2c_write8(I2C_PORT_TCPC, LCD_SLAVE_ADDR, 0x00,
+		   data | state.backlightval);
 }
 
 static void pulse_enable(uint8_t data)
 {
-	expander_write(data | LCD_EN);/* En high */
-	usleep(1);	/* enable pulse must be >450ns */
+	expander_write(data | LCD_EN); /* En high */
+	usleep(1); /* enable pulse must be >450ns */
 
-	expander_write(data & ~LCD_EN);/* En low */
-	usleep(50);	/* commands need > 37us to settle */
+	expander_write(data & ~LCD_EN); /* En low */
+	usleep(50); /* commands need > 37us to settle */
 }
 
 static void write_4bits(uint8_t value)
@@ -63,8 +63,8 @@ static void command(uint8_t value)
 /********** high level commands, for the user! */
 void lcd_clear(void)
 {
-	command(LCD_CLEAR_DISPLAY);/* clear display, set cursor to zero */
-	usleep(2000);	/* this command takes a long time! */
+	command(LCD_CLEAR_DISPLAY); /* clear display, set cursor to zero */
+	usleep(2000); /* this command takes a long time! */
 }
 
 void lcd_set_cursor(uint8_t col, uint8_t row)
diff --git a/board/fusb307bgevb/lcd.h b/board/fusb307bgevb/lcd.h
index 21b0ee9ce9..9ed773d92f 100644
--- a/board/fusb307bgevb/lcd.h
+++ b/board/fusb307bgevb/lcd.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,50 +11,50 @@
 #include "common.h"
 
 /* commands */
-#define LCD_CLEAR_DISPLAY	BIT(0)
-#define LCD_RETURN_HOME		BIT(1)
-#define LCD_ENTRYMODE_SET	BIT(2)
-#define LCD_DISPLAY_CONTROL	BIT(3)
-#define LCD_CURSOR_SHIFT	BIT(4)
-#define LCD_FUNCTION_SET	BIT(5)
-#define LCD_SET_CGRAMADDR	BIT(6)
-#define LCD_SET_DDRAMADDR	BIT(7)
+#define LCD_CLEAR_DISPLAY BIT(0)
+#define LCD_RETURN_HOME BIT(1)
+#define LCD_ENTRYMODE_SET BIT(2)
+#define LCD_DISPLAY_CONTROL BIT(3)
+#define LCD_CURSOR_SHIFT BIT(4)
+#define LCD_FUNCTION_SET BIT(5)
+#define LCD_SET_CGRAMADDR BIT(6)
+#define LCD_SET_DDRAMADDR BIT(7)
 
 /* flags for display entry mode */
-#define LCD_ENTRY_RIGHT			0x00
-#define LCD_ENTRY_LEFT			BIT(1)
-#define LCD_ENTRY_SHIFT_INCREMENT	BIT(0)
-#define LCD_ENTRY_SHIFT_DECREMENT	0x00
+#define LCD_ENTRY_RIGHT 0x00
+#define LCD_ENTRY_LEFT BIT(1)
+#define LCD_ENTRY_SHIFT_INCREMENT BIT(0)
+#define LCD_ENTRY_SHIFT_DECREMENT 0x00
 
 /* flags for display on/off control */
-#define LCD_DISPLAY_ON	BIT(2)
-#define LCD_DISPLAY_OFF	0x00
-#define LCD_CURSOR_ON	BIT(1)
-#define LCD_CURSOR_OFF	0x00
-#define LCD_BLINK_ON	BIT(0)
-#define LCD_BLINK_OFF	0x00
+#define LCD_DISPLAY_ON BIT(2)
+#define LCD_DISPLAY_OFF 0x00
+#define LCD_CURSOR_ON BIT(1)
+#define LCD_CURSOR_OFF 0x00
+#define LCD_BLINK_ON BIT(0)
+#define LCD_BLINK_OFF 0x00
 
 /* flags for display/cursor shift */
-#define LCD_DISPLAY_MOVE	BIT(3)
-#define LCD_CURSOR_MOVE		0x00
-#define LCD_MOVE_RIGHT		BIT(2)
-#define LCD_MOVE_LEFT		0x00
+#define LCD_DISPLAY_MOVE BIT(3)
+#define LCD_CURSOR_MOVE 0x00
+#define LCD_MOVE_RIGHT BIT(2)
+#define LCD_MOVE_LEFT 0x00
 
 /* flags for function set */
-#define LCD_8BITMODE	BIT(4)
-#define LCD_4BITMODE	0x00
-#define LCD_2LINE	BIT(3)
-#define LCD_1LINE	0x00
-#define LCD_5X10DOTS	BIT(2)
-#define LCD_5X8DOTS	0x00
+#define LCD_8BITMODE BIT(4)
+#define LCD_4BITMODE 0x00
+#define LCD_2LINE BIT(3)
+#define LCD_1LINE 0x00
+#define LCD_5X10DOTS BIT(2)
+#define LCD_5X8DOTS 0x00
 
 /* flags for backlight control */
-#define LCD_BACKLIGHT		BIT(3)
-#define LCD_NO_BACKLIGHT	0x00
+#define LCD_BACKLIGHT BIT(3)
+#define LCD_NO_BACKLIGHT 0x00
 
-#define LCD_EN	BIT(2) /* Enable bit */
-#define LCD_RW	BIT(1) /* Read/Write bit */
-#define LCD_RS	BIT(0) /* Register select bit */
+#define LCD_EN BIT(2) /* Enable bit */
+#define LCD_RW BIT(1) /* Read/Write bit */
+#define LCD_RS BIT(0) /* Register select bit */
 
 void lcd_init(uint8_t cols, uint8_t rows, uint8_t dotsize);
 void lcd_set_cursor(uint8_t col, uint8_t row);
diff --git a/board/fusb307bgevb/vif_override.xml b/board/fusb307bgevb/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/fusb307bgevb/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/gaelin/board.c b/board/gaelin/board.c
new file mode 100644
index 0000000000..32ab3e3fdc
--- /dev/null
+++ b/board/gaelin/board.c
@@ -0,0 +1,616 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "adc.h"
+#include "assert.h"
+#include "button.h"
+#include "cec.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "driver/cec/bitbang.h"
+#include "driver/retimer/ps8811.h"
+#include "driver/tcpm/tcpci.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "power.h"
+#include "power_button.h"
+#include "switch.h"
+#include "throttle_ap.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+/* Console output macros */
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+
+static void power_monitor(void);
+DECLARE_DEFERRED(power_monitor);
+
+/******************************************************************************/
+/* USB-A charging control */
+
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_PP5000_USBA,
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
+
+/******************************************************************************/
+/* USB-A retimer control */
+
+const struct usb_mux usba_ps8811[] = {
+	[USBA_PORT_A0] = {
+		.usb_port = USBA_PORT_A0,
+		.i2c_port = I2C_PORT_USB_A0_A1_MIX,
+		.i2c_addr_flags = PS8811_I2C_ADDR_FLAGS0,
+	},
+	[USBA_PORT_A1] = {
+		.usb_port = USBA_PORT_A1,
+		.i2c_port = I2C_PORT_USB_A0_A1_MIX,
+		.i2c_addr_flags = PS8811_I2C_ADDR_FLAGS2,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(usba_ps8811) == USBA_PORT_COUNT);
+
+static int usba_retimer_init(int port)
+{
+	int rv, val;
+	const struct usb_mux *me = &usba_ps8811[port];
+
+	rv = ps8811_i2c_read(me, PS8811_REG_PAGE1, PS8811_REG1_USB_BEQ_LEVEL,
+			     &val);
+
+	if (rv) {
+		CPRINTS("A%d: PS8811 retimer not detected!", port);
+	} else {
+		CPRINTS("A%d: PS8811 retimer detected", port);
+	}
+
+	if (port == USBA_PORT_A1) {
+		/* Set channel B output swing */
+		/* offset 0xA4, Data 0x04 */
+		rv |= ps8811_i2c_field_update(me, PS8811_REG_PAGE1,
+					      PS8811_REG1_USB_CHAN_B_SWING,
+					      PS8811_CHAN_B_SWING_MASK, 0x4);
+
+		/* Set channel B output DE level */
+		/* offset 0xA6, Data 0x12 */
+		rv |= ps8811_i2c_field_update(me, PS8811_REG_PAGE1,
+					      PS8811_REG1_USB_CHAN_B_DE_PS_MSB,
+					      PS8811_CHAN_B_DE_PS_MSB_MASK,
+					      0x12);
+	}
+
+	return rv;
+}
+
+void board_chipset_startup(void)
+{
+	int i;
+
+	for (i = 0; i < USBA_PORT_COUNT; i++)
+		usba_retimer_init(i);
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
+
+/******************************************************************************/
+
+/* CEC ports */
+const struct cec_config_t cec_config[] = {
+	[CEC_PORT_0] = {
+		.drv = &bitbang_cec_drv,
+		.offline_policy = NULL,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(cec_config) == CEC_PORT_COUNT);
+
+int board_set_active_charge_port(int port)
+{
+	CPRINTS("Requested charge port change to %d", port);
+
+	/*
+	 * The charge manager may ask us to switch to no charger if we're
+	 * running off USB-C only but upstream doesn't support PD. It requires
+	 * that we accept this switch otherwise it triggers an assert and EC
+	 * reset; it's not possible to boot the AP anyway, but we want to avoid
+	 * resetting the EC so we can continue to do the "low power" LED blink.
+	 */
+	if (port == CHARGE_PORT_NONE)
+		return EC_SUCCESS;
+
+	if (port < 0 || CHARGE_PORT_COUNT <= port)
+		return EC_ERROR_INVAL;
+
+	if (port == charge_manager_get_active_charge_port())
+		return EC_SUCCESS;
+
+	/* Don't charge from a source port */
+	if (board_vbus_source_enabled(port))
+		return EC_ERROR_INVAL;
+
+	if (!chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
+		int bj_active, bj_requested;
+
+		if (charge_manager_get_active_charge_port() != CHARGE_PORT_NONE)
+			/* Change is only permitted while the system is off */
+			return EC_ERROR_INVAL;
+
+		/*
+		 * Current setting is no charge port but the AP is on, so the
+		 * charge manager is out of sync (probably because we're
+		 * reinitializing after sysjump). Reject requests that aren't
+		 * in sync with our outputs.
+		 */
+		bj_active = !gpio_get_level(GPIO_EN_PPVAR_BJ_ADP_L);
+		bj_requested = port == CHARGE_PORT_BARRELJACK;
+		if (bj_active != bj_requested)
+			return EC_ERROR_INVAL;
+	}
+
+	CPRINTS("New charger p%d", port);
+
+	switch (port) {
+	case CHARGE_PORT_TYPEC0:
+	case CHARGE_PORT_TYPEC1:
+		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 1);
+		break;
+	case CHARGE_PORT_BARRELJACK:
+		/* Make sure BJ adapter is sourcing power */
+		if (gpio_get_level(GPIO_BJ_ADP_PRESENT_ODL))
+			return EC_ERROR_INVAL;
+		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 0);
+		break;
+	default:
+		return EC_ERROR_INVAL;
+	}
+
+	return EC_SUCCESS;
+}
+
+static uint8_t usbc_overcurrent;
+static int32_t base_5v_power_s5;
+static int32_t base_5v_power_z1;
+
+/*
+ * Power usage for each port as measured or estimated.
+ * Units are milliwatts (5v x ma current)
+ */
+
+/* PP5000_S5 loads */
+#define PWR_S5_BASE_LOAD (5 * 1431)
+#define PWR_S5_FRONT_HIGH (5 * 1737)
+#define PWR_S5_FRONT_LOW (5 * 1055)
+#define PWR_S5_REAR_HIGH (5 * 1737)
+#define PWR_S5_REAR_LOW (5 * 1055)
+#define PWR_S5_HDMI (5 * 580)
+#define PWR_S5_MAX (5 * 10000)
+#define FRONT_DELTA (PWR_S5_FRONT_HIGH - PWR_S5_FRONT_LOW)
+#define REAR_DELTA (PWR_S5_REAR_HIGH - PWR_S5_REAR_LOW)
+
+/* PP5000_Z1 loads */
+#define PWR_Z1_BASE_LOAD (5 * 5)
+#define PWR_Z1_C_HIGH (5 * 3600)
+#define PWR_Z1_C_LOW (5 * 2000)
+#define PWR_Z1_MAX (5 * 9000)
+/*
+ * Update the 5V power usage, assuming no throttling,
+ * and invoke the power monitoring.
+ */
+static void update_5v_usage(void)
+{
+	int front_ports = 0;
+	int rear_ports = 0;
+
+	/*
+	 * Recalculate the 5V load, assuming no throttling.
+	 */
+	base_5v_power_s5 = PWR_S5_BASE_LOAD;
+	if (!gpio_get_level(GPIO_USB_A0_OC_ODL)) {
+		front_ports++;
+		base_5v_power_s5 += PWR_S5_FRONT_LOW;
+	}
+	if (!gpio_get_level(GPIO_USB_A1_OC_ODL)) {
+		front_ports++;
+		base_5v_power_s5 += PWR_S5_FRONT_LOW;
+	}
+	/*
+	 * Only 1 front port can run higher power at a time.
+	 */
+	if (front_ports > 0)
+		base_5v_power_s5 += PWR_S5_FRONT_HIGH - PWR_S5_FRONT_LOW;
+
+	if (!gpio_get_level(GPIO_USB_A2_OC_ODL)) {
+		rear_ports++;
+		base_5v_power_s5 += PWR_S5_REAR_LOW;
+	}
+	if (!gpio_get_level(GPIO_USB_A3_OC_ODL)) {
+		rear_ports++;
+		base_5v_power_s5 += PWR_S5_REAR_LOW;
+	}
+	/*
+	 * Only 1 rear port can run higher power at a time.
+	 */
+	if (rear_ports > 0)
+		base_5v_power_s5 += PWR_S5_REAR_HIGH - PWR_S5_REAR_LOW;
+	if (!gpio_get_level(GPIO_HDMI_CONN_OC_ODL))
+		base_5v_power_s5 += PWR_S5_HDMI;
+	base_5v_power_z1 = PWR_Z1_BASE_LOAD;
+	if (usbc_overcurrent)
+		base_5v_power_z1 += PWR_Z1_C_HIGH;
+	/*
+	 * Invoke the power handler immediately.
+	 */
+	hook_call_deferred(&power_monitor_data, 0);
+}
+DECLARE_DEFERRED(update_5v_usage);
+/*
+ * Start power monitoring after ADCs have been initialised.
+ */
+DECLARE_HOOK(HOOK_INIT, update_5v_usage, HOOK_PRIO_INIT_ADC + 1);
+
+static void port_ocp_interrupt(enum gpio_signal signal)
+{
+	hook_call_deferred(&update_5v_usage_data, 0);
+}
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/******************************************************************************/
+/*
+ * Barrel jack power supply handling
+ *
+ * EN_PPVAR_BJ_ADP_L must default active to ensure we can power on when the
+ * barrel jack is connected, and the USB-C port can bring the EC up fine in
+ * dead-battery mode. Both the USB-C and barrel jack switches do reverse
+ * protection, so we're safe to turn one on then the other off- but we should
+ * only do that if the system is off since it might still brown out.
+ */
+
+#define ADP_DEBOUNCE_MS 1000 /* Debounce time for BJ plug/unplug */
+/* Debounced connection state of the barrel jack */
+static int8_t adp_connected = -1;
+static void adp_connect_deferred(void)
+{
+	struct charge_port_info pi = { 0 };
+	int connected = !gpio_get_level(GPIO_BJ_ADP_PRESENT_ODL);
+
+	/* Debounce */
+	if (connected == adp_connected)
+		return;
+	if (connected)
+		ec_bj_power(&pi.voltage, &pi.current);
+	charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED,
+				     DEDICATED_CHARGE_PORT, &pi);
+	adp_connected = connected;
+}
+DECLARE_DEFERRED(adp_connect_deferred);
+
+/* IRQ for BJ plug/unplug. It shouldn't be called if BJ is the power source. */
+void adp_connect_interrupt(enum gpio_signal signal)
+{
+	hook_call_deferred(&adp_connect_deferred_data, ADP_DEBOUNCE_MS * MSEC);
+}
+
+static void adp_state_init(void)
+{
+	ASSERT(CHARGE_PORT_ENUM_COUNT == CHARGE_PORT_COUNT);
+	/*
+	 * Initialize all charge suppliers to 0. The charge manager waits until
+	 * all ports have reported in before doing anything.
+	 */
+	for (int i = 0; i < CHARGE_PORT_COUNT; i++) {
+		for (int j = 0; j < CHARGE_SUPPLIER_COUNT; j++)
+			charge_manager_update_charge(j, i, NULL);
+	}
+
+	/* Report charge state from the barrel jack. */
+	adp_connect_deferred();
+}
+DECLARE_HOOK(HOOK_INIT, adp_state_init, HOOK_PRIO_INIT_CHARGE_MANAGER + 1);
+
+static void board_init(void)
+{
+	gpio_enable_interrupt(GPIO_BJ_ADP_PRESENT_ODL);
+	gpio_enable_interrupt(GPIO_HDMI_CONN_OC_ODL);
+	gpio_enable_interrupt(GPIO_USB_A0_OC_ODL);
+	gpio_enable_interrupt(GPIO_USB_A1_OC_ODL);
+	gpio_enable_interrupt(GPIO_USB_A2_OC_ODL);
+	gpio_enable_interrupt(GPIO_USB_A3_OC_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+void board_overcurrent_event(int port, int is_overcurrented)
+{
+	/* Check that port number is valid. */
+	if ((port < 0) || (port >= CONFIG_USB_PD_PORT_MAX_COUNT))
+		return;
+	usbc_overcurrent = is_overcurrented;
+	update_5v_usage();
+}
+
+/*
+ * Power monitoring and management.
+ *
+ * the power budgets are met without letting the system fall into
+ * power deficit (perhaps causing a brownout).
+ *
+ * There are 2 power budgets that need to be managed:
+ * The overall goal is to gracefully manage the power demand so that
+ *  - overall system power as measured on the main power supply rail.
+ *  - 5V power delivered to the USB and HDMI ports.
+ *
+ * The actual system power demand is calculated from the VBUS voltage and
+ * the input current (read from a shunt), averaged over 5 readings.
+ * The power budget limit is from the charge manager.
+ *
+ * The 5V power cannot be read directly. Instead, we rely on overcurrent
+ * inputs from the USB and HDMI ports to indicate that the port is in use
+ * (and drawing maximum power).
+ *
+ * There are 3 throttles that can be applied (in priority order):
+ *
+ *  - Type A BC1.2 front port restriction (3W)
+ *  - Type A BC1.2 rear port restriction (3W)
+ *  - Type C PD (throttle to 1.5A if sourcing)
+ *  - Turn on PROCHOT, which immediately throttles the CPU.
+ *
+ *  The first 3 throttles affect both the system power and the 5V rails.
+ *  The third is a last resort to force an immediate CPU throttle to
+ *  reduce the overall power use.
+ *
+ *  The strategy is to determine what the state of the throttles should be,
+ *  and to then turn throttles off or on as needed to match this.
+ *
+ *  This function runs on demand, or every 2 ms when the CPU is up,
+ *  and continually monitors the power usage, applying the
+ *  throttles when necessary.
+ *
+ *  All measurements are in milliwatts.
+ */
+#define THROT_TYPE_A_FRONT BIT(0)
+#define THROT_TYPE_A_REAR BIT(1)
+#define THROT_TYPE_C0 BIT(2)
+#define THROT_TYPE_C1 BIT(3)
+#define THROT_PROCHOT BIT(5)
+
+/*
+ * Power gain if front USB A ports are limited.
+ */
+#define POWER_GAIN_TYPE_A 3200
+/*
+ * Power gain if Type C port is limited.
+ */
+#define POWER_GAIN_TYPE_C 8800
+/*
+ * Power is averaged over 10 ms, with a reading every 2 ms.
+ */
+#define POWER_DELAY_MS 2
+#define POWER_READINGS (10 / POWER_DELAY_MS)
+
+static void power_monitor(void)
+{
+	static uint32_t current_state;
+	static uint32_t history[POWER_READINGS];
+	static uint8_t index;
+	int32_t delay;
+	uint32_t new_state = 0, diff;
+	int32_t headroom_5v_s5 = PWR_S5_MAX - base_5v_power_s5;
+	int32_t headroom_5v_z1 = PWR_Z1_MAX - base_5v_power_z1;
+
+	/*
+	 * If CPU is off or suspended, no need to throttle
+	 * or restrict power.
+	 */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF | CHIPSET_STATE_SUSPEND)) {
+		/*
+		 * Slow down monitoring, assume no throttling required.
+		 */
+		delay = 20 * MSEC;
+		/*
+		 * Clear the first entry of the power table so that
+		 * it is re-initilalised when the CPU starts.
+		 */
+		history[0] = 0;
+	} else {
+		int32_t charger_mw;
+
+		delay = POWER_DELAY_MS * MSEC;
+		/*
+		 * Get current charger limit (in mw).
+		 * If not configured yet, skip.
+		 */
+		charger_mw = charge_manager_get_power_limit_uw() / 1000;
+		if (charger_mw != 0) {
+			int32_t gap, total, max, power;
+			int i;
+
+			/*
+			 * Read power usage.
+			 */
+			power = (adc_read_channel(ADC_VBUS) *
+				 adc_read_channel(ADC_PPVAR_IMON)) /
+				1000;
+			/* Init power table */
+			if (history[0] == 0) {
+				for (i = 0; i < POWER_READINGS; i++)
+					history[i] = power;
+			}
+			/*
+			 * Update the power readings and
+			 * calculate the average and max.
+			 */
+			history[index] = power;
+			index = (index + 1) % POWER_READINGS;
+			total = 0;
+			max = history[0];
+			for (i = 0; i < POWER_READINGS; i++) {
+				total += history[i];
+				if (history[i] > max)
+					max = history[i];
+			}
+			/*
+			 * For Type-C power supplies, there is
+			 * less tolerance for exceeding the rating,
+			 * so use the max power that has been measured
+			 * over the measuring period.
+			 * For barrel-jack supplies, the rating can be
+			 * exceeded briefly, so use the average.
+			 */
+			if (charge_manager_get_supplier() == CHARGE_SUPPLIER_PD)
+				power = max;
+			else
+				power = total / POWER_READINGS;
+			/*
+			 * Calculate gap, and if negative, power
+			 * demand is exceeding configured power budget, so
+			 * throttling is required to reduce the demand.
+			 */
+			gap = charger_mw - power;
+			/*
+			 * Limiting type-A power rear ports.
+			 */
+			if (gap <= 0) {
+				new_state |= THROT_TYPE_A_REAR;
+				headroom_5v_s5 += REAR_DELTA;
+				if (!(current_state & THROT_TYPE_A_REAR))
+					gap += POWER_GAIN_TYPE_A;
+			}
+			/*
+			 * Limiting type-A power front ports.
+			 */
+			if (gap <= 0) {
+				new_state |= THROT_TYPE_A_FRONT;
+				headroom_5v_s5 += FRONT_DELTA;
+				if (!(current_state & THROT_TYPE_A_REAR))
+					gap += POWER_GAIN_TYPE_A;
+			}
+			/*
+			 * If the type-C port is sourcing power,
+			 * check whether it should be throttled.
+			 */
+			if (ppc_is_sourcing_vbus(0) && gap <= 0) {
+				new_state |= THROT_TYPE_C0;
+				headroom_5v_z1 += PWR_Z1_C_HIGH - PWR_Z1_C_LOW;
+				if (!(current_state & THROT_TYPE_C0))
+					gap += POWER_GAIN_TYPE_C;
+			}
+			/*
+			 * If the type-C port is sourcing power,
+			 * check whether it should be throttled.
+			 */
+			if (ppc_is_sourcing_vbus(1) && gap <= 0) {
+				new_state |= THROT_TYPE_C1;
+				headroom_5v_z1 += PWR_Z1_C_HIGH - PWR_Z1_C_LOW;
+				if (!(current_state & THROT_TYPE_C1))
+					gap += POWER_GAIN_TYPE_C;
+			}
+			/*
+			 * As a last resort, turn on PROCHOT to
+			 * throttle the CPU.
+			 */
+			if (gap <= 0)
+				new_state |= THROT_PROCHOT;
+		}
+	}
+	/*
+	 * Check the 5v power usage and if necessary,
+	 * adjust the throttles in priority order.
+	 *
+	 * Either throttle may have already been activated by
+	 * the overall power control.
+	 *
+	 * We rely on the overcurrent detection to inform us
+	 * if the port is in use.
+	 *
+	 *  - If type C not already throttled:
+	 *	* If not overcurrent, prefer to limit type C [1].
+	 *	* If in overcurrentuse:
+	 *		- limit type A first [2]
+	 *		- If necessary, limit type C [3].
+	 *  - If type A not throttled, if necessary limit it [2].
+	 */
+	if (headroom_5v_z1 < 0) {
+		/*
+		 * Check whether type C is not throttled,
+		 * and is not overcurrent.
+		 */
+		if (!((new_state & THROT_TYPE_C0) || usbc_overcurrent)) {
+			/*
+			 * [1] Type C not in overcurrent, throttle it.
+			 */
+			headroom_5v_z1 += PWR_Z1_C_HIGH - PWR_Z1_C_LOW;
+			new_state |= THROT_TYPE_C0;
+		}
+		/*
+		 * [2] If still under-budget, limit type C.
+		 * No need to check if it is already throttled or not.
+		 */
+		if (headroom_5v_z1 < 0)
+			new_state |= THROT_TYPE_C0;
+	}
+	if (headroom_5v_s5 < 0) {
+		/*
+		 * [1] If type A rear not already throttled, and power still
+		 * needed, limit type A rear.
+		 */
+		if (!(new_state & THROT_TYPE_A_REAR) && headroom_5v_s5 < 0) {
+			headroom_5v_s5 += PWR_S5_REAR_HIGH - PWR_S5_REAR_LOW;
+			new_state |= THROT_TYPE_A_REAR;
+		}
+		/*
+		 * [2] If type A front not already throttled, and power still
+		 * needed, limit type A front.
+		 */
+		if (!(new_state & THROT_TYPE_A_FRONT) && headroom_5v_s5 < 0) {
+			headroom_5v_s5 += PWR_S5_FRONT_HIGH - PWR_S5_FRONT_LOW;
+			new_state |= THROT_TYPE_A_FRONT;
+		}
+	}
+	/*
+	 * Turn the throttles on or off if they have changed.
+	 */
+	diff = new_state ^ current_state;
+	current_state = new_state;
+	if (diff & THROT_PROCHOT) {
+		int prochot = (new_state & THROT_PROCHOT) ? 0 : 1;
+
+		gpio_set_level(GPIO_EC_PROCHOT_ODL, prochot);
+	}
+	if (diff & THROT_TYPE_C0) {
+		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C0) ?
+						TYPEC_RP_1A5 :
+						TYPEC_RP_3A0;
+
+		ppc_set_vbus_source_current_limit(0, rp);
+		tcpm_select_rp_value(0, rp);
+		pd_update_contract(0);
+	}
+	if (diff & THROT_TYPE_C1) {
+		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C1) ?
+						TYPEC_RP_1A5 :
+						TYPEC_RP_3A0;
+
+		ppc_set_vbus_source_current_limit(1, rp);
+		tcpm_select_rp_value(1, rp);
+		pd_update_contract(1);
+	}
+	if (diff & THROT_TYPE_A_REAR) {
+		int typea_bc = (new_state & THROT_TYPE_A_REAR) ? 1 : 0;
+
+		gpio_set_level(GPIO_USB_A_LOW_PWR0_OD, typea_bc);
+		gpio_set_level(GPIO_USB_A_LOW_PWR1_OD, typea_bc);
+	}
+	if (diff & THROT_TYPE_A_FRONT) {
+		int typea_bc = (new_state & THROT_TYPE_A_FRONT) ? 1 : 0;
+
+		gpio_set_level(GPIO_USB_A_LOW_PWR2_OD, typea_bc);
+		gpio_set_level(GPIO_USB_A_LOW_PWR3_OD, typea_bc);
+	}
+	hook_call_deferred(&power_monitor_data, delay);
+}
diff --git a/board/gaelin/board.h b/board/gaelin/board.h
new file mode 100644
index 0000000000..a469deafb3
--- /dev/null
+++ b/board/gaelin/board.h
@@ -0,0 +1,176 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Brask board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "compile_time_macros.h"
+
+/* Baseboard features */
+#include "baseboard.h"
+
+#define CONFIG_MP2964
+
+/* Barrel Jack */
+#define DEDICATED_CHARGE_PORT 2
+
+/* HDMI CEC */
+#define CONFIG_CEC
+#define CONFIG_CEC_BITBANG
+#define CEC_GPIO_OUT GPIO_HDMI_CEC_OUT
+#define CEC_GPIO_IN GPIO_HDMI_CEC_IN
+#define CEC_GPIO_PULL_UP GPIO_HDMI_CEC_PULL_UP
+
+/* USB Type A Features */
+#define USB_PORT_COUNT 4
+#define CONFIG_USB_PORT_POWER_DUMB
+#define CONFIG_USBC_RETIMER_PS8811
+
+/* USB Type C and USB PD defines */
+#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
+
+#define CONFIG_USB_PD_PPC
+#define CONFIG_USB_PD_TCPM_PS8815
+#define CONFIG_USBC_PPC_NX20P3483 /* Compatible with Silicon Mitus SM5360A */
+
+/* TODO: b/177608416 - measure and check these values on brya */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
+
+/* The design should support up to 100W. */
+/* TODO(b/197702356): Set the max PD to 60W now and change it
+ * to 100W after we verify it.
+ */
+#define PD_OPERATING_POWER_MW CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
+#define PD_MAX_POWER_MW 100000
+#define PD_MAX_CURRENT_MA 5000
+#define PD_MAX_VOLTAGE_MV 20000
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
+
+/*
+ * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
+ * signal.
+ */
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
+#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_OD
+#define GPIO_RECOVERY_L_2 GPIO_GSC_EC_RECOVERY_BTN_OD
+
+/* I2C Bus Configuration */
+#define I2C_PORT_SCALER NPCX_I2C_PORT5_0
+
+#define I2C_PORT_USB_C0_TCPC NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1
+
+#define I2C_PORT_USB_C0_PPC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT3_0
+
+#define I2C_PORT_USB_C0_BC12 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT3_0
+
+#define I2C_PORT_USB_A0_A1_MIX NPCX_I2C_PORT6_1
+
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+
+#define I2C_ADDR_MP2964_FLAGS 0x20
+
+#define I2C_ADDR_SCALER_FLAGS 0x58
+
+/* Thermal features */
+#define CONFIG_THERMISTOR
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_TEMP_SENSOR_POWER
+#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
+
+/* ADC */
+#define CONFIG_ADC
+
+/* Fan */
+#define CONFIG_FANS FAN_CH_COUNT
+#define RPM_DEVIATION 1
+#define CONFIG_CUSTOM_FAN_CONTROL
+
+/* Include math_util for bitmask_uint64 used in pd_timers */
+#define CONFIG_MATH_UTIL
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h" /* needed by registers.h */
+#include "registers.h"
+#include "usbc_config.h"
+
+enum charge_port {
+	CHARGE_PORT_TYPEC0,
+	CHARGE_PORT_TYPEC1,
+	CHARGE_PORT_BARRELJACK,
+	CHARGE_PORT_ENUM_COUNT
+};
+
+enum adc_channel {
+	ADC_TEMP_SENSOR_1_CPU,
+	ADC_TEMP_SENSOR_2_CPU_VR,
+	ADC_TEMP_SENSOR_3_WIFI,
+	ADC_TEMP_SENSOR_4_DIMM,
+	ADC_VBUS,
+	ADC_PPVAR_IMON, /* ADC3 */
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1_CPU,
+	TEMP_SENSOR_2_CPU_VR,
+	TEMP_SENSOR_3_WIFI,
+	TEMP_SENSOR_4_DIMM,
+	TEMP_SENSOR_COUNT
+};
+
+enum pwm_channel {
+	PWM_CH_LED_GREEN, /* PWM0 */
+	PWM_CH_FAN, /* PWM5 */
+	PWM_CH_LED_RED, /* PWM2 */
+	PWM_CH_COUNT
+};
+
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT };
+
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT };
+
+enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT };
+
+enum cec_port { CEC_PORT_0, CEC_PORT_COUNT };
+
+extern void adp_connect_interrupt(enum gpio_signal signal);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/gaelin/build.mk b/board/gaelin/build.mk
new file mode 100644
index 0000000000..6961fb3f60
--- /dev/null
+++ b/board/gaelin/build.mk
@@ -0,0 +1,23 @@
+# -*- makefile -*-
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Brask board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx9
+CHIP_VARIANT:=npcx9m3f
+BASEBOARD:=brask
+
+board-y=
+board-y+=board.o
+board-y+=fans.o
+board-y+=fw_config.o
+board-y+=i2c.o
+board-y+=led.o
+board-y+=pwm.o
+board-y+=sensors.o
+board-y+=thermal.o
+board-y+=usbc_config.o
diff --git a/board/gaelin/ec.tasklist b/board/gaelin/ec.tasklist
new file mode 100644
index 0000000000..4a40f332e8
--- /dev/null
+++ b/board/gaelin/ec.tasklist
@@ -0,0 +1,26 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ *
+ * USB_CHG_Px tasks must be contiguous (see USB_CHG_PORT_TO_TASK_ID(x)).
+ * PD_Cx tasks must be contiguous (see PD_PORT_TO_TASK_ID(x))
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CEC, cec_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/gaelin/fans.c b/board/gaelin/fans.c
new file mode 100644
index 0000000000..c92ae84872
--- /dev/null
+++ b/board/gaelin/fans.c
@@ -0,0 +1,44 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Physical fans. These are logically separate from pwm_channels. */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "fan.h"
+#include "fan_chip.h"
+#include "hooks.h"
+#include "pwm.h"
+
+/* MFT channels. These are logically separate from pwm_channels. */
+const struct mft_t mft_channels[] = {
+	[MFT_CH_0] = {
+		.module = NPCX_MFT_MODULE_2,
+		.clk_src = TCKC_LFCLK,
+		.pwm_id = PWM_CH_FAN,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
+
+static const struct fan_conf fan_conf_0 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
+	.pgood_gpio = -1,
+	.enable_gpio = GPIO_EN_PP5000_FAN,
+};
+
+static const struct fan_rpm fan_rpm_0 = {
+	.rpm_min = 2350,
+	.rpm_start = 2350,
+	.rpm_max = 4100,
+};
+
+const struct fan_t fans[FAN_CH_COUNT] = {
+	[FAN_CH_0] = {
+		.conf = &fan_conf_0,
+		.rpm = &fan_rpm_0,
+	},
+};
diff --git a/board/gaelin/fw_config.c b/board/gaelin/fw_config.c
new file mode 100644
index 0000000000..3ee71e6a0f
--- /dev/null
+++ b/board/gaelin/fw_config.c
@@ -0,0 +1,65 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "fw_config.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+static union brask_cbi_fw_config fw_config;
+BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
+
+/*
+ * FW_CONFIG defaults for brask if the CBI.FW_CONFIG data is not
+ * initialized.
+ */
+static const union brask_cbi_fw_config fw_config_defaults = {
+	.audio = DB_NAU88L25B_I2S,
+	.bj_power = BJ_135W,
+};
+
+/*
+ * Barrel-jack power adapter ratings.
+ */
+static const struct {
+	int voltage;
+	int current;
+} bj_power[] = {
+	[BJ_135W] = { /* 0 - 135W (also default) */
+			.voltage = 19500,
+			.current = 6920
+	},
+	[BJ_230W] = { /* 1 - 230W */
+			.voltage = 19500,
+			.current = 11800
+	}
+};
+
+/****************************************************************************
+ * Brask FW_CONFIG access
+ */
+void board_init_fw_config(void)
+{
+	if (cbi_get_fw_config(&fw_config.raw_value)) {
+		CPRINTS("CBI: Read FW_CONFIG failed, using board defaults");
+		fw_config = fw_config_defaults;
+	}
+}
+
+void ec_bj_power(uint32_t *voltage, uint32_t *current)
+{
+	unsigned int bj;
+
+	bj = fw_config.bj_power;
+	/* Out of range value defaults to 0 */
+	if (bj >= ARRAY_SIZE(bj_power))
+		bj = 0;
+	*voltage = bj_power[bj].voltage;
+	*current = bj_power[bj].current;
+}
diff --git a/board/gaelin/fw_config.h b/board/gaelin/fw_config.h
new file mode 100644
index 0000000000..95d81f1e05
--- /dev/null
+++ b/board/gaelin/fw_config.h
@@ -0,0 +1,41 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __BOARD_BRASK_FW_CONFIG_H_
+#define __BOARD_BRASK_FW_CONFIG_H_
+
+#include <stdint.h>
+
+/****************************************************************************
+ * CBI FW_CONFIG layout for Brask board.
+ *
+ * Source of truth is the project/brask/brask/config.star configuration file.
+ */
+enum ec_cfg_audio_type { DB_AUDIO_UNKNOWN = 0, DB_NAU88L25B_I2S = 1 };
+
+enum ec_cfg_bj_power { BJ_135W = 0, BJ_230W = 1 };
+
+union brask_cbi_fw_config {
+	struct {
+		uint32_t audio : 3;
+		uint32_t bj_power : 2;
+		uint32_t reserved_1 : 27;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Read the cached FW_CONFIG.  Guaranteed to have valid values.
+ *
+ * @return the FW_CONFIG for the board.
+ */
+union brask_cbi_fw_config get_fw_config(void);
+
+/**
+ * Get the barrel-jack power from FW_CONFIG.
+ */
+void ec_bj_power(uint32_t *voltage, uint32_t *current);
+
+#endif /* __BOARD_BRASK_FW_CONFIG_H_ */
diff --git a/board/gaelin/gpio.inc b/board/gaelin/gpio.inc
new file mode 100644
index 0000000000..3e84f2e692
--- /dev/null
+++ b/board/gaelin/gpio.inc
@@ -0,0 +1,176 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* INTERRUPT GPIOs: */
+
+GPIO_INT(ACOK_OD,                    PIN(0, 0), GPIO_INT_BOTH, extpower_interrupt)
+GPIO_INT(EC_PROCHOT_IN_L,            PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
+GPIO_INT(EC_WP_ODL,                  PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(GSC_EC_PWR_BTN_ODL,         PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
+GPIO_INT(SEQ_EC_ALL_SYS_PG,          PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_DSW_PWROK,           PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_RSMRST_ODL,          PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,                   PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,                  PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SYS_SLP_S0IX_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(USB_C0_BC12_INT_ODL,        PIN(C, 6), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C0_TCPC_INT_ODL,        PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C0_PPC_INT_ODL,         PIN(6, 2), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C1_BC12_INT_ODL,        PIN(5, 0), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C1_PPC_INT_ODL,         PIN(F, 5), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C1_TCPC_INT_ODL,        PIN(A, 2), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(BJ_ADP_PRESENT_ODL,         PIN(8, 2), GPIO_INT_BOTH | GPIO_PULL_UP, adp_connect_interrupt)
+GPIO_INT(EC_RECOVERY_BTN_OD,         PIN(2, 3), GPIO_INT_BOTH, button_interrupt)
+GPIO_INT(HDMI_CONN_OC_ODL,           PIN(2, 4), GPIO_INPUT | GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(USB_A0_OC_ODL,              PIN(3, 1), GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(USB_A1_OC_ODL,              PIN(3, 0), GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(USB_A2_OC_ODL,              PIN(2, 7), GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(USB_A3_OC_ODL,              PIN(2, 6), GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH, port_ocp_interrupt)
+
+/* CCD */
+GPIO(CCD_MODE_ODL,                   PIN(E, 5), GPIO_INPUT)
+
+/* Security */
+GPIO(EC_ENTERING_RW,                 PIN(0, 3), GPIO_OUT_LOW)
+GPIO(EC_GSC_PACKET_MODE,             PIN(7, 5), GPIO_OUT_LOW)
+
+/* Fan */
+GPIO(EN_PP5000_FAN,                  PIN(6, 1), GPIO_OUT_HIGH)
+
+/* ADC, need to check the usage */
+GPIO(ANALOG_PPVAR_PWR_IN_IMON_EC,    PIN(4, 2), GPIO_INPUT)
+
+/* Display */
+GPIO(EC_OVERRIDE_SCLR_EN,            PIN(D, 4), GPIO_OUT_HIGH)
+
+/* TODO(b/260063632): the gpio pin control is wip, setting to level high
+                      to enable the backlight by default */
+GPIO(EC_12VSC_EN,                    PIN(D, 2), GPIO_OUT_HIGH)
+
+GPIO(OSD_STS,                        PIN(4, 1), GPIO_INPUT)
+GPIO(DISP_MODE,                      PIN(A, 0), GPIO_INPUT)
+GPIO(PANEL_PWR_STS,                  PIN(9, 5), GPIO_INPUT)
+GPIO(EN_SCLR_RAILS,                  PIN(0, 4), GPIO_INPUT)
+GPIO(HDMI_5V_IN,                     PIN(9, 3), GPIO_INPUT)
+GPIO(HDMI0_CABLE_DET,                PIN(9, 6), GPIO_INPUT)
+GPIO(WP_EC,                          PIN(C, 3), GPIO_INPUT)
+GPIO(OSD_INT,                        PIN(0, 5), GPIO_INPUT)
+
+/* Audio */
+/* TODO(b/260063632): the gpio pin control is wip, setting to level high
+                      to enable the speaker by default */
+GPIO(EC_AMP_SD,                      PIN(5, 6), GPIO_OUT_HIGH)
+
+/* BarrelJack */
+GPIO(EN_PPVAR_BJ_ADP_L,              PIN(0, 7), GPIO_OUT_LOW)
+
+/* Chipset PCH */
+GPIO(EC_PCHHOT_ODL,                  PIN(7, 4), GPIO_INPUT)
+GPIO(EC_PCH_INT_ODL,                 PIN(B, 0), GPIO_ODR_HIGH)
+GPIO(EC_PCH_RSMRST_L,                PIN(A, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_RTCRST,                  PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_SYS_PWROK,               PIN(3, 7), GPIO_OUT_LOW)
+GPIO(EC_PCH_WAKE_ODL,                PIN(C, 0), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_ODL,                 PIN(6, 3), GPIO_ODR_HIGH)
+GPIO(EN_S5_RAILS,                    PIN(B, 6), GPIO_OUT_LOW)
+GPIO(PCH_PWROK,                      PIN(7, 2), GPIO_OUT_LOW)
+GPIO(SYS_RST_ODL,                    PIN(C, 5), GPIO_ODR_HIGH)
+GPIO(VCCST_PWRGD_OD,                 PIN(A, 4), GPIO_ODR_LOW)
+GPIO(IMVP9_VRRDY_OD,                 PIN(6, 0), GPIO_INPUT)
+GPIO(CPU_C10_GATE_L,                 PIN(6, 7), GPIO_INPUT)
+
+/* Button */
+GPIO(EC_PCH_PWR_BTN_ODL,             PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(GSC_EC_RECOVERY_BTN_OD,         PIN(2, 2), GPIO_INPUT)
+
+/* HDMI CEC */
+/* TODO(b/197474873): Enable HDMI CEC */
+GPIO(HDMI_CEC_IN,                    PIN(4, 0), GPIO_INPUT)
+GPIO(HDMI_CEC_OUT,                   PIN(D, 3), GPIO_OUT_HIGH | GPIO_OPEN_DRAIN)
+GPIO(HDMI_CEC_PULL_UP,               PIN(C, 2), GPIO_OUT_HIGH)
+
+/* I2C SCL/SDA */
+GPIO(SMSCALER_CLK,                   PIN(3, 3), GPIO_INPUT)
+GPIO(SMSCALER_DATA,                  PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SCL_R,              PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SDA_R,              PIN(B, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_PPC_BC_SCL,       PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_PPC_BC_SDA,       PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_PPC_BC_SCL,       PIN(D, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_PPC_BC_SDA,       PIN(D, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_TCPC_SCL,         PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_TCPC_SDA,         PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_TCPC_SCL,         PIN(F, 3), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_TCPC_SDA,         PIN(F, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_A0_A1_MIX_SCL,       PIN(E, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_A0_A1_MIX_SDA,       PIN(E, 3), GPIO_INPUT)
+
+/* USBA */
+GPIO(EN_PP5000_USBA,                 PIN(D, 7), GPIO_OUT_LOW)
+GPIO(USB_A0_STATUS_L,                PIN(2, 1), GPIO_INPUT)
+GPIO(USB_A1_STATUS_L,                PIN(2, 0), GPIO_INPUT)
+GPIO(USB_A2_STATUS_L,                PIN(1, 7), GPIO_INPUT)
+GPIO(USB_A3_STATUS_L,                PIN(1, 6), GPIO_INPUT)
+GPIO(USB_A_LOW_PWR0_OD,              PIN(1, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(USB_A_LOW_PWR1_OD,              PIN(1, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(USB_A_LOW_PWR2_OD,              PIN(1, 1), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(USB_A_LOW_PWR3_OD,              PIN(1, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(USB_A_OC_SOC_L,                 PIN(8, 0), GPIO_OUT_HIGH)
+
+/* LED */
+/* TODO(b/197471359): LED implementation */
+GPIO(LED_RED_L,                      PIN(C, 4), GPIO_OUT_LOW)
+
+/* USBC */
+GPIO(USB_C0_FRS_EN,                  PIN(9, 7), GPIO_OUT_LOW)
+GPIO(USB_C0_RT_RST_L,                PIN(A, 7), GPIO_OUT_HIGH)
+GPIO(USB_C1_FRS_EN,                  PIN(9, 4), GPIO_OUT_LOW)
+GPIO(USB_C1_RT_RST_L,                PIN(0, 2), GPIO_OUT_HIGH)
+
+/* GPIO02_P2 to PU */
+/* GPIO03_P2 to PU */
+/* GPIO07_P2 to PU */
+
+/* UART alternate functions */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)              /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */
+
+/* I2C alternate functions */
+ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)               /* GPIO36/RTS_L/I2C5_SDA0, GPIO33/I2C5_SCL0/CTS_L */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)               /* GPIO87/I2C1_SDA0 */
+ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)               /* GPIO92/I2C2_SCL0, GPIO91/I2C2_SDA0, GPIO90/I2C1_SCL0 */
+ALTERNATE(PIN_MASK(B, 0x0c), 0, MODULE_I2C, 0)               /* GPIOB3/I2C7_SCL0/DCD_L, GPIOB2/I2C7_SDA0/DSR_L */
+ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)               /* GPIOD1/I2C3_SCL0, GPIOD0/I2C3_SDA0 */
+ALTERNATE(PIN_MASK(E, 0x18), 0, MODULE_I2C, 0)               /* GPIOE4/I2C6_SCL1/I3C_SCL, GPIOE3/I2C6_SDA1/I3C_SDA */
+ALTERNATE(PIN_MASK(F, 0x0c), 0, MODULE_I2C, 0)               /* GPIOF3/I2C4_SCL1, GPIOF2/I2C4_SDA1 */
+
+/* PWM alternate functions */
+ALTERNATE(PIN_MASK(7, 0x08), 0, MODULE_PWM, 0)               /* GPIO73/TA2 */
+ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)               /* GPIOB7/PWM5 */
+ALTERNATE(PIN_MASK(C, 0x18), 0, MODULE_PWM, 0)               /* GPIOC4/PWM2, GPIOC3/PWM0 */
+
+/* ADC alternate functions */
+ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0)               /* GPIO34/PS2_DAT2/ADC6 */
+ALTERNATE(PIN_MASK(4, 0x38), 0, MODULE_ADC, 0)               /* GPIO45/ADC0, GPIO44/ADC1, GPIO43/ADC2 */
+ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0)               /* GPIOE1/ADC7 */
+
+/* Unused Pins */
+UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
+UNUSED(PIN(3, 2))       /* GPO32/TRIS_L */
+UNUSED(PIN(3, 5))       /* GPO35/CR_SOUT4/TEST_L */
+UNUSED(PIN(6, 6))       /* GPIO66 */
+UNUSED(PIN(8, 1))       /* GPIO81/PECI_DATA */
+UNUSED(PIN(8, 6))       /* GPIO86/TXD/CR_SOUT2 */
+UNUSED(PIN(1, 3))       /* KSO06/GPO13/GP_SEL# */
+UNUSED(PIN(1, 2))       /* KSO07/GPO12/JEN# */
+UNUSED(PIN(0, 6))       /* KSO11/GPIO06/P80_CLK */
+UNUSED(PIN(B, 4))       /* GPIOB4/I2C0_SDA0 */
+UNUSED(PIN(2, 5))       /* KSI4/GPIO25/TRACECLK/GP_SCLK */
+UNUSED(PIN(B, 5))       /* GPIOB5/I2C0_SCL0 */
+UNUSED(PIN(8, 3))       /* KSO15/GPIO83 */
+UNUSED(PIN(B, 1))       /* KSO17/GPIOB1/CR_SIN4 */
+UNUSED(PIN(7, 0))       /* GPIO70/PS2_DAT0 */
+UNUSED(PIN(A, 3))       /* SPIP_MOSI/GPIOA3 */
diff --git a/board/gaelin/i2c.c b/board/gaelin/i2c.c
new file mode 100644
index 0000000000..ce285d16b4
--- /dev/null
+++ b/board/gaelin/i2c.c
@@ -0,0 +1,69 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "i2c.h"
+
+/* I2C port map configuration */
+const struct i2c_port_t i2c_ports[] = {
+	{
+		/* I2C1 */
+		.name = "tcpc0",
+		.port = I2C_PORT_USB_C0_TCPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_TCPC_SDA,
+	},
+	{
+		/* I2C2 */
+		.name = "ppc0",
+		.port = I2C_PORT_USB_C0_PPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_PPC_BC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_PPC_BC_SDA,
+	},
+	{
+		/* I2C3 */
+		.name = "ppc1",
+		.port = I2C_PORT_USB_C1_PPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C1_PPC_BC_SCL,
+		.sda = GPIO_EC_I2C_USB_C1_PPC_BC_SDA,
+	},
+	{
+		/* I2C4 */
+		.name = "tcpc1",
+		.port = I2C_PORT_USB_C1_TCPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C1_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C1_TCPC_SDA,
+	},
+	{
+		/* I2C5 */
+		.name = "scaler",
+		.port = I2C_PORT_SCALER,
+		.kbps = 400,
+		.scl = GPIO_SMSCALER_CLK,
+		.sda = GPIO_SMSCALER_DATA,
+	},
+	{
+		/* I2C6 */
+		.name = "usba0_retimer,usba1_retimer",
+		.port = I2C_PORT_USB_A0_A1_MIX,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_A0_A1_MIX_SCL,
+		.sda = GPIO_EC_I2C_USB_A0_A1_MIX_SDA,
+	},
+	{
+		/* I2C7 */
+		.name = "eeprom",
+		.port = I2C_PORT_EEPROM,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_MISC_SCL_R,
+		.sda = GPIO_EC_I2C_MISC_SDA_R,
+	},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/board/gaelin/led.c b/board/gaelin/led.c
new file mode 100644
index 0000000000..a4b9a0d094
--- /dev/null
+++ b/board/gaelin/led.c
@@ -0,0 +1,260 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power LED control for Brask.
+ * Solid green - active power
+ * Green flashing - suspended
+ * Red flashing - alert
+ * Solid red - critical
+ */
+
+#include "chipset.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "led_common.h"
+#include "pwm.h"
+#include "timer.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
+
+/*
+ * Due to the CSME-Lite processing, upon startup the CPU transitions through
+ * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so
+ * delay turning off the LED during suspend/shutdown.
+ */
+#define LED_CPU_DELAY_MS (2000 * MSEC)
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED };
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+enum led_color {
+	LED_OFF = 0,
+	LED_RED,
+	LED_GREEN,
+
+	/* Number of colors, not a color itself */
+	LED_COLOR_COUNT
+};
+
+static int set_color_power(enum led_color color, int duty)
+{
+	int green = 0;
+	int red = 0;
+
+	if (duty < 0 || 100 < duty)
+		return EC_ERROR_UNKNOWN;
+
+	switch (color) {
+	case LED_OFF:
+		break;
+	case LED_GREEN:
+		green = 1;
+		break;
+	case LED_RED:
+		red = 1;
+		break;
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+
+	if (red)
+		pwm_set_duty(PWM_CH_LED_RED, duty);
+	else
+		pwm_set_duty(PWM_CH_LED_RED, 0);
+
+	if (green)
+		pwm_set_duty(PWM_CH_LED_GREEN, duty);
+	else
+		pwm_set_duty(PWM_CH_LED_GREEN, 0);
+
+	return EC_SUCCESS;
+}
+
+static int set_color(enum ec_led_id id, enum led_color color, int duty)
+{
+	switch (id) {
+	case EC_LED_ID_POWER_LED:
+		return set_color_power(color, duty);
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+}
+
+#define LED_PULSE_US (2 * SECOND)
+/* 40 msec for nice and smooth transition. */
+#define LED_PULSE_TICK_US (40 * MSEC)
+
+/*
+ * When pulsing is enabled, brightness is incremented by <duty_inc> every
+ * <interval> usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented
+ * likewise in LED_PULSE_US usec.
+ */
+static struct {
+	uint32_t interval;
+	int duty_inc;
+	enum led_color color;
+	int duty;
+} led_pulse;
+
+#define CONFIG_TICK(interval, color) \
+	config_tick((interval), 100 / (LED_PULSE_US / (interval)), (color))
+
+static void config_tick(uint32_t interval, int duty_inc, enum led_color color)
+{
+	led_pulse.interval = interval;
+	led_pulse.duty_inc = duty_inc;
+	led_pulse.color = color;
+	led_pulse.duty = 0;
+}
+
+static void pulse_power_led(enum led_color color)
+{
+	set_color(EC_LED_ID_POWER_LED, color, led_pulse.duty);
+	if (led_pulse.duty + led_pulse.duty_inc > 100)
+		led_pulse.duty_inc = led_pulse.duty_inc * -1;
+	else if (led_pulse.duty + led_pulse.duty_inc < 0)
+		led_pulse.duty_inc = led_pulse.duty_inc * -1;
+	led_pulse.duty += led_pulse.duty_inc;
+}
+
+static void led_tick(void);
+DECLARE_DEFERRED(led_tick);
+static void led_tick(void)
+{
+	uint32_t elapsed;
+	uint32_t next = 0;
+	uint32_t start = get_time().le.lo;
+
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		pulse_power_led(led_pulse.color);
+	elapsed = get_time().le.lo - start;
+	next = led_pulse.interval > elapsed ? led_pulse.interval - elapsed : 0;
+	hook_call_deferred(&led_tick_data, next);
+}
+
+static void led_suspend(void)
+{
+	CONFIG_TICK(LED_PULSE_TICK_US, LED_GREEN);
+	led_tick();
+}
+DECLARE_DEFERRED(led_suspend);
+
+static void led_shutdown(void)
+{
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_OFF, 0);
+}
+DECLARE_DEFERRED(led_shutdown);
+
+static void led_shutdown_hook(void)
+{
+	hook_call_deferred(&led_tick_data, -1);
+	hook_call_deferred(&led_suspend_data, -1);
+	hook_call_deferred(&led_shutdown_data, LED_CPU_DELAY_MS);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, led_shutdown_hook, HOOK_PRIO_DEFAULT);
+
+static void led_suspend_hook(void)
+{
+	hook_call_deferred(&led_shutdown_data, -1);
+	hook_call_deferred(&led_suspend_data, LED_CPU_DELAY_MS);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, led_suspend_hook, HOOK_PRIO_DEFAULT);
+
+static void led_resume(void)
+{
+	/*
+	 * Assume there is no race condition with led_tick, which also
+	 * runs in hook_task.
+	 */
+	hook_call_deferred(&led_tick_data, -1);
+	/*
+	 * Avoid invoking the suspend/shutdown delayed hooks.
+	 */
+	hook_call_deferred(&led_suspend_data, -1);
+	hook_call_deferred(&led_shutdown_data, -1);
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_GREEN, 100);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, led_resume, HOOK_PRIO_DEFAULT);
+
+void led_alert(int enable)
+{
+	if (enable) {
+		/* Overwrite the current signal */
+		config_tick(1 * SECOND, 100, LED_RED);
+		led_tick();
+	} else {
+		/* Restore the previous signal */
+		if (chipset_in_state(CHIPSET_STATE_ON))
+			led_resume();
+		else if (chipset_in_state(CHIPSET_STATE_SUSPEND))
+			led_suspend_hook();
+		else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+			led_shutdown_hook();
+	}
+}
+
+void show_critical_error(void)
+{
+	hook_call_deferred(&led_tick_data, -1);
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_RED, 100);
+}
+
+static int command_led(int argc, const char **argv)
+{
+	enum ec_led_id id = EC_LED_ID_POWER_LED;
+
+	if (argc < 2)
+		return EC_ERROR_PARAM_COUNT;
+
+	if (!strcasecmp(argv[1], "debug")) {
+		led_auto_control(id, !led_auto_control_is_enabled(id));
+		ccprintf("o%s\n", led_auto_control_is_enabled(id) ? "ff" : "n");
+	} else if (!strcasecmp(argv[1], "off")) {
+		set_color(id, LED_OFF, 0);
+	} else if (!strcasecmp(argv[1], "red")) {
+		set_color(id, LED_RED, 100);
+	} else if (!strcasecmp(argv[1], "green")) {
+		set_color(id, LED_GREEN, 100);
+	} else if (!strcasecmp(argv[1], "alert")) {
+		led_alert(1);
+	} else if (!strcasecmp(argv[1], "crit")) {
+		show_critical_error();
+	} else {
+		return EC_ERROR_PARAM1;
+	}
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(led, command_led, "[debug|red|green|off|alert|crit]",
+			"Turn on/off LED.");
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	brightness_range[EC_LED_COLOR_RED] = 100;
+	brightness_range[EC_LED_COLOR_GREEN] = 100;
+}
+
+int led_set_brightness(enum ec_led_id id, const uint8_t *brightness)
+{
+	if (brightness[EC_LED_COLOR_RED])
+		return set_color(id, LED_RED, brightness[EC_LED_COLOR_RED]);
+	else if (brightness[EC_LED_COLOR_GREEN])
+		return set_color(id, LED_GREEN, brightness[EC_LED_COLOR_GREEN]);
+	else
+		return set_color(id, LED_OFF, 0);
+}
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
+{
+	/* Blink alert if insufficient power per system_can_boot_ap(). */
+	int insufficient_power =
+		(charge_ma * charge_mv) <
+		(CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON * 1000);
+	led_alert(insufficient_power);
+}
diff --git a/board/gaelin/pwm.c b/board/gaelin/pwm.c
new file mode 100644
index 0000000000..bf90ad5f63
--- /dev/null
+++ b/board/gaelin/pwm.c
@@ -0,0 +1,39 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "hooks.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_LED_GREEN] = { .channel = 0,
+			       .flags = PWM_CONFIG_ACTIVE_LOW |
+					PWM_CONFIG_DSLEEP,
+			       .freq = 2000 },
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
+	[PWM_CH_LED_RED] = { .channel = 2,
+			     .flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+			     .freq = 2000 },
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+static void board_pwm_init(void)
+{
+	/*
+	 * TODO(b/197478860): Turn on the fan at 100% by default
+	 * We need to find tune the fan speed according to the
+	 * thermal sensor value.
+	 */
+	pwm_enable(PWM_CH_FAN, 1);
+	pwm_set_duty(PWM_CH_FAN, 100);
+
+	pwm_enable(PWM_CH_LED_RED, 1);
+	pwm_enable(PWM_CH_LED_GREEN, 1);
+}
+DECLARE_HOOK(HOOK_INIT, board_pwm_init, HOOK_PRIO_DEFAULT);
diff --git a/board/gaelin/sensors.c b/board/gaelin/sensors.c
new file mode 100644
index 0000000000..13948f60d8
--- /dev/null
+++ b/board/gaelin/sensors.c
@@ -0,0 +1,114 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc_chip.h"
+#include "common.h"
+#include "hooks.h"
+#include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
+#include "thermal.h"
+
+/* ADC configuration */
+const struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_1_CPU] = {
+		.name = "TEMP_CPU",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_2_CPU_VR] = {
+		.name = "TEMP_CPU_VR",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_3_WIFI] = {
+		.name = "TEMP_WIFI",
+		.input_ch = NPCX_ADC_CH6,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_4_DIMM] = {
+		.name = "TEMP_DIMM",
+		.input_ch = NPCX_ADC_CH7,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_VBUS] = {  /* 5/39 voltage divider */
+		.name = "VBUS",
+		.input_ch = NPCX_ADC_CH2,
+		.factor_mul = ADC_MAX_VOLT * 39,
+		.factor_div = (ADC_READ_MAX + 1) * 5,
+	},
+	[ADC_PPVAR_IMON] = {  /* 872.3 mV/A */
+		.name = "PPVAR_IMON",
+		.input_ch = NPCX_ADC_CH3,
+		.factor_mul = ADC_MAX_VOLT * 1433,
+		.factor_div = (ADC_READ_MAX + 1) * 1250,
+	},
+
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* Temperature sensor configuration */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1_CPU] = { .name = "CPU",
+				.type = TEMP_SENSOR_TYPE_BOARD,
+				.read = get_temp_3v3_30k9_47k_4050b,
+				.idx = ADC_TEMP_SENSOR_1_CPU },
+	[TEMP_SENSOR_2_CPU_VR] = { .name = "CPU VR",
+				   .type = TEMP_SENSOR_TYPE_BOARD,
+				   .read = get_temp_3v3_30k9_47k_4050b,
+				   .idx = ADC_TEMP_SENSOR_2_CPU_VR },
+	[TEMP_SENSOR_3_WIFI] = { .name = "WIFI",
+				 .type = TEMP_SENSOR_TYPE_BOARD,
+				 .read = get_temp_3v3_30k9_47k_4050b,
+				 .idx = ADC_TEMP_SENSOR_3_WIFI },
+	[TEMP_SENSOR_4_DIMM] = { .name = "DIMM",
+				 .type = TEMP_SENSOR_TYPE_BOARD,
+				 .read = get_temp_3v3_30k9_47k_4050b,
+				 .idx = ADC_TEMP_SENSOR_4_DIMM },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/*
+ * TODO(b/180681346): update for Alder Lake/brya
+ *
+ * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
+ * 130 C.  However, sensor is located next to DDR, so we need to use the lower
+ * DDR temperature limit (85 C)
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+		}, \
+		.temp_fan_off = C_TO_K(35), \
+		.temp_fan_max = C_TO_K(50), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
+
+/*
+ * TODO(b/197478860): add the thermal sensor setting
+ */
+/* this should really be "const" */
+struct ec_thermal_config thermal_params[] = {
+	[TEMP_SENSOR_1_CPU] = THERMAL_CPU,
+	[TEMP_SENSOR_2_CPU_VR] = THERMAL_CPU,
+	[TEMP_SENSOR_3_WIFI] = THERMAL_CPU,
+	[TEMP_SENSOR_4_DIMM] = THERMAL_CPU,
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
diff --git a/board/gaelin/thermal.c b/board/gaelin/thermal.c
new file mode 100644
index 0000000000..e15e0043e1
--- /dev/null
+++ b/board/gaelin/thermal.c
@@ -0,0 +1,140 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "fan.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "temp_sensor.h"
+#include "thermal.h"
+#include "util.h"
+
+/* Console output macros */
+#define CPUTS(outstr) cputs(CC_THERMAL, outstr)
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
+
+struct fan_step {
+	/*
+	 * Sensor 1~4 trigger point, set -1 if we're not using this
+	 * sensor to determine fan speed.
+	 */
+	int8_t on[TEMP_SENSOR_COUNT];
+	/*
+	 * Sensor 1~4 trigger point, set -1 if we're not using this
+	 * sensor to determine fan speed.
+	 */
+	int8_t off[TEMP_SENSOR_COUNT];
+	/* Fan rpm */
+	int16_t rpm[FAN_CH_COUNT];
+};
+
+static const struct fan_step fan_table[] = {
+	{
+		/* level 0 */
+		.on = { 65, -1, -1, -1 },
+		.off = { 0, -1, -1, -1 },
+		.rpm = { 2350 },
+	},
+	{
+		/* level 1 */
+		.on = { 80, -1, -1, -1 },
+		.off = { 60, -1, -1, -1 },
+		.rpm = { 2350 },
+	},
+	{
+		/* level 2 */
+		.on = { 87, -1, -1, -1 },
+		.off = { 75, -1, -1, -1 },
+		.rpm = { 3250 },
+	},
+	{
+		/* level 3 */
+		.on = { 91, -1, -1, -1 },
+		.off = { 82, -1, -1, -1 },
+		.rpm = { 3750 },
+	},
+	{
+		/* level 4 */
+		.on = { 100, -1, -1, -1 },
+		.off = { 86, -1, -1, -1 },
+		.rpm = { 4100 },
+	},
+};
+const int num_fan_levels = ARRAY_SIZE(fan_table);
+
+int fan_table_to_rpm(int fan, int *temp, enum temp_sensor_id temp_sensor)
+{
+	/* current fan level */
+	static int current_level;
+	/* previous fan level */
+	static int prev_current_level;
+	/* previous sensor temperature */
+	static int prev_temp[TEMP_SENSOR_COUNT];
+	int i;
+	int new_rpm = 0;
+
+	/*
+	 * Compare the current and previous temperature, we have
+	 * the three paths:
+	 *   1. decreasing path. (check the release point)
+	 *   2. increasing path. (check the trigger point)
+	 *   3. invariant path. (return the current RPM)
+	 */
+	if (temp[temp_sensor] < prev_temp[temp_sensor]) {
+		for (i = current_level; i > 0; i--) {
+			if (temp[temp_sensor] < fan_table[i].off[temp_sensor])
+				current_level = i - 1;
+			else
+				break;
+		}
+	} else if (temp[temp_sensor] > prev_temp[temp_sensor]) {
+		for (i = current_level; i < num_fan_levels; i++) {
+			if (temp[temp_sensor] > fan_table[i].on[temp_sensor])
+				current_level = i + 1;
+			else
+				break;
+		}
+	}
+
+	if (current_level < 0)
+		current_level = 0;
+	if (current_level >= num_fan_levels)
+		current_level = num_fan_levels - 1;
+
+	if (current_level != prev_current_level) {
+		CPRINTS("temp: %d, prev_temp: %d", temp[temp_sensor],
+			prev_temp[temp_sensor]);
+		CPRINTS("current_level: %d", current_level);
+	}
+
+	prev_temp[temp_sensor] = temp[temp_sensor];
+	prev_current_level = current_level;
+
+	switch (fan) {
+	case FAN_CH_0:
+		new_rpm = fan_table[current_level].rpm[FAN_CH_0];
+		break;
+	default:
+		break;
+	}
+
+	return new_rpm;
+}
+
+void board_override_fan_control(int fan, int *temp)
+{
+	if (chipset_in_state(CHIPSET_STATE_ON)) {
+		fan_set_rpm_mode(FAN_CH(fan), 1);
+		fan_set_rpm_target(FAN_CH(fan),
+				   fan_table_to_rpm(FAN_CH(fan), temp,
+						    TEMP_SENSOR_1_CPU));
+	} else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
+		/* Stop fan when enter S0ix */
+		fan_set_rpm_mode(FAN_CH(fan), 1);
+		fan_set_rpm_target(FAN_CH(fan), 0);
+	}
+}
diff --git a/board/gaelin/usbc_config.c b/board/gaelin/usbc_config.c
new file mode 100644
index 0000000000..90b9f73d87
--- /dev/null
+++ b/board/gaelin/usbc_config.c
@@ -0,0 +1,275 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/bc12/pi3usb9201_public.h"
+#include "driver/ppc/nx20p348x.h"
+#include "driver/tcpm/ps8xxx_public.h"
+#include "driver/tcpm/tcpci.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "system.h"
+#include "task.h"
+#include "task_id.h"
+#include "timer.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+/* USBC TCPC configuration */
+const struct tcpc_config_t tcpc_config[] = {
+	[USBC_PORT_C0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0_TCPC,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
+			 TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V,
+	},
+	[USBC_PORT_C1] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C1_TCPC,
+			.addr_flags = PS8XXX_I2C_ADDR2_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
+			 TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
+BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
+
+/* USBC PPC configuration */
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C0] = {
+		/* Compatible with Silicon Mitus SM5360A */
+		.i2c_port = I2C_PORT_USB_C0_PPC,
+		.i2c_addr_flags = NX20P3483_ADDR2_FLAGS,
+		.drv = &nx20p348x_drv,
+	},
+	[USBC_PORT_C1] = {
+		/* Compatible with Silicon Mitus SM5360A */
+		.i2c_port = I2C_PORT_USB_C1_PPC,
+		.i2c_addr_flags = NX20P3483_ADDR3_FLAGS,
+		.drv = &nx20p348x_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
+
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/* USBC mux configuration - Alder Lake includes internal mux */
+static const struct usb_mux_chain usbc0_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
+};
+static const struct usb_mux_chain usbc1_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
+};
+
+const struct usb_mux_chain usb_muxes[] = {
+	[USBC_PORT_C0] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc0_tcss_usb_mux,
+	},
+	[USBC_PORT_C1] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc1_tcss_usb_mux,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
+
+/* BC1.2 charger detect configuration */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C1_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_2_FLAGS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
+
+static void ps8815_reset(int port)
+{
+	int val;
+	int i2c_port;
+	uint16_t i2c_addr_flags;
+	enum gpio_signal ps8xxx_rst_odl;
+
+	if (port == USBC_PORT_C0) {
+		ps8xxx_rst_odl = GPIO_USB_C0_RT_RST_L;
+		i2c_port = I2C_PORT_USB_C0_TCPC;
+		i2c_addr_flags = PS8XXX_I2C_ADDR1_FLAGS;
+	} else if (port == USBC_PORT_C1) {
+		ps8xxx_rst_odl = GPIO_USB_C1_RT_RST_L;
+		i2c_port = I2C_PORT_USB_C1_TCPC;
+		i2c_addr_flags = PS8XXX_I2C_ADDR2_FLAGS;
+	} else {
+		return;
+	}
+
+	gpio_set_level(ps8xxx_rst_odl, 0);
+	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS));
+	gpio_set_level(ps8xxx_rst_odl, 1);
+	msleep(PS8815_FW_INIT_DELAY_MS);
+
+	CPRINTS("[C%d] %s: patching ps8815 registers", port, __func__);
+
+	if (i2c_read8(i2c_port, i2c_addr_flags, 0x0f, &val) == EC_SUCCESS)
+		CPRINTS("ps8815: reg 0x0f was %02x", val);
+	else {
+		CPRINTS("delay 10ms to make sure ps8815 is waken from idle");
+		msleep(10);
+	}
+
+	if (i2c_write8(i2c_port, i2c_addr_flags, 0x0f, 0x31) == EC_SUCCESS)
+		CPRINTS("ps8815: reg 0x0f set to 0x31");
+
+	if (i2c_read8(i2c_port, i2c_addr_flags, 0x0f, &val) == EC_SUCCESS)
+		CPRINTS("ps8815: reg 0x0f now %02x", val);
+}
+
+void board_reset_pd_mcu(void)
+{
+	ps8815_reset(USBC_PORT_C0);
+	usb_mux_hpd_update(USBC_PORT_C0, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+	ps8815_reset(USBC_PORT_C1);
+	usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+}
+
+static void board_tcpc_init(void)
+{
+	/* Don't reset TCPCs after initial reset */
+	if (!system_jumped_late()) {
+		board_reset_pd_mcu();
+	}
+
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
+
+	/* Enable BC1.2 interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_0;
+
+	if (gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
+
+int ppc_get_alert_status(int port)
+{
+	if (port == USBC_PORT_C0)
+		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
+	else if (port == USBC_PORT_C1)
+		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
+	return 0;
+}
+
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C1);
+		break;
+	default:
+		break;
+	}
+}
+
+void bc12_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_BC12_INT_ODL:
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+		break;
+	case GPIO_USB_C1_BC12_INT_ODL:
+		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+		break;
+	default:
+		break;
+	}
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		nx20p348x_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_PPC_INT_ODL:
+		nx20p348x_interrupt(USBC_PORT_C1);
+		break;
+	default:
+		break;
+	}
+}
+
+void retimer_interrupt(enum gpio_signal signal)
+{
+	/*
+	 * TODO(b/179513527): add USB-C support
+	 */
+}
+
+__override bool board_is_dts_port(int port)
+{
+	return port == USBC_PORT_C0;
+}
diff --git a/board/gaelin/usbc_config.h b/board/gaelin/usbc_config.h
new file mode 100644
index 0000000000..219ad9a745
--- /dev/null
+++ b/board/gaelin/usbc_config.h
@@ -0,0 +1,15 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Brya board-specific USB-C configuration */
+
+#ifndef __CROS_EC_USBC_CONFIG_H
+#define __CROS_EC_USBC_CONFIG_H
+
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
+
+#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/gaelin/vif_override.xml b/board/gaelin/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/gaelin/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/galtic/battery.c b/board/galtic/battery.c
new file mode 100644
index 0000000000..10fc273303
--- /dev/null
+++ b/board/galtic/battery.c
@@ -0,0 +1,131 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "charge_state.h"
+#include "common.h"
+
+/*
+ * Battery info for all waddledee battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	[BATTERY_C140254] = {
+		.fuel_gauge = {
+			.manuf_name = "AS3GXXE3KA",
+			.device_name = "C140254",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr = 0x99,
+				.reg_mask = 0x000C,
+				.disconnect_val = 0x000C,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 8900, /* mV */
+			.voltage_normal		= 7970, /* mV */
+			.voltage_min		= 6000, /* mV */
+			.precharge_current	= 256,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 45,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 60,
+		},
+	},
+	[BATTERY_C340184] = {
+		.fuel_gauge = {
+			.manuf_name = "AS3GXXH3KD",
+			.device_name = "C340184",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr = 0x99,
+				.reg_mask = 0x000C,
+				.disconnect_val = 0x000C,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0004,
+			}
+		},
+		.batt_info = {
+			.voltage_max            = 8900, /* mV */
+			.voltage_normal         = 7960, /* mV */
+			.voltage_min            = 6000, /* mV */
+			.precharge_current      = 256,  /* mA */
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 45,
+			.charging_min_c         = 0,
+			.charging_max_c         = 60,
+			.discharging_min_c      = -20,
+			.discharging_max_c      = 60,
+		},
+	},
+	[BATTERY_C140243] = {
+		.fuel_gauge = {
+			.manuf_name = "AS3GXXD3KB",
+			.device_name = "C140243",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr = 0x99,
+				.reg_mask = 0x000C,
+				.disconnect_val = 0x000C,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0004,
+			}
+		},
+		.batt_info = {
+			.voltage_max            = 13200, /* mV */
+			.voltage_normal         = 11880, /* mV */
+			.voltage_min            = 9000, /* mV */
+			.precharge_current      = 256,  /* mA */
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 45,
+			.charging_min_c         = 0,
+			.charging_max_c         = 60,
+			.discharging_min_c      = -20,
+			.discharging_max_c      = 60,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_C140254;
+
+__override int board_get_default_battery_type(void)
+{
+	if (board_get_battery_cell_type() == BATTERY_CELL_TYPE_3S)
+		return BATTERY_C140243;
+	else
+		return DEFAULT_BATTERY_TYPE;
+}
diff --git a/board/galtic/board.c b/board/galtic/board.c
new file mode 100644
index 0000000000..a05c9f470d
--- /dev/null
+++ b/board/galtic/board.c
@@ -0,0 +1,937 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Waddledee board-specific configuration */
+
+#include "adc_chip.h"
+#include "button.h"
+#include "cbi_fw_config.h"
+#include "cbi_ssfc.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "driver/accel_bma2x2.h"
+#include "driver/accel_kionix.h"
+#include "driver/accelgyro_bmi160.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "driver/accelgyro_icm426xx.h"
+#include "driver/accelgyro_icm_common.h"
+#include "driver/bc12/pi3usb9201.h"
+#include "driver/charger/isl923x.h"
+#include "driver/retimer/tusb544.h"
+#include "driver/tcpm/raa489000.h"
+#include "driver/temp_sensor/thermistor.h"
+#include "driver/usb_mux/it5205.h"
+#include "driver/usb_mux/ps8743_public.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "intc.h"
+#include "keyboard_raw.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "switch.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "tcpm/tcpci.h"
+#include "temp_sensor.h"
+#include "uart.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+
+#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+
+#define INT_RECHECK_US 5000
+
+/* C0 interrupt line shared by BC 1.2 and charger */
+static void check_c0_line(void);
+DECLARE_DEFERRED(check_c0_line);
+
+static void notify_c0_chips(void)
+{
+	schedule_deferred_pd_interrupt(0);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+
+static void check_c0_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		notify_c0_chips();
+		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+	}
+}
+
+static void usb_c0_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c0_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c0_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+}
+
+/* C1 interrupt line shared by BC 1.2, TCPC, and charger */
+static void check_c1_line(void);
+DECLARE_DEFERRED(check_c1_line);
+
+static void notify_c1_chips(void)
+{
+	schedule_deferred_pd_interrupt(1);
+	usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+}
+
+static void check_c1_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips.
+	 */
+	if (!gpio_get_level(GPIO_USB_C1_INT_ODL)) {
+		notify_c1_chips();
+		hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
+	}
+}
+
+static void usb_c1_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c1_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c1_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
+}
+
+static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
+{
+	cprints(CC_USBPD, "C0: CC OVP, SBU OVP, or thermal event");
+	pd_handle_cc_overvoltage(0);
+}
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	[ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH0 },
+	[ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH2 },
+	[ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH3 },
+	[ADC_TEMP_SENSOR_3] = { .name = "TEMP_SENSOR3",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH15 },
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* BC 1.2 chips */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	{
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+		.flags = PI3USB9201_ALWAYS_POWERED,
+	},
+	{
+		.i2c_port = I2C_PORT_SUB_USB_C1,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+		.flags = PI3USB9201_ALWAYS_POWERED,
+	},
+};
+
+int pd_snk_is_vbus_provided(int port)
+{
+	return pd_check_vbus_level(port, VBUS_PRESENT);
+}
+
+/* Charger chips */
+const struct charger_config_t chg_chips[] = {
+	[CHARGER_PRIMARY] = {
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+	[CHARGER_SECONDARY] = {
+		.i2c_port = I2C_PORT_SUB_USB_C1,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+};
+
+/* TCPCs */
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0,
+			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
+		},
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+		.drv = &raa489000_tcpm_drv,
+	},
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_SUB_USB_C1,
+			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
+		},
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+		.drv = &raa489000_tcpm_drv,
+	},
+};
+
+/* USB Retimer */
+enum tusb544_conf { USB_DP = 0, USB_DP_INV, USB, USB_INV, DP, DP_INV };
+
+static int board_tusb544_set(const struct usb_mux *me, mux_state_t mux_state)
+{
+	int rv = EC_SUCCESS;
+	enum tusb544_conf usb_mode = 0;
+	/* USB */
+	if (mux_state & USB_PD_MUX_USB_ENABLED) {
+		/* USB with DP */
+		if (mux_state & USB_PD_MUX_DP_ENABLED) {
+			usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ?
+					   USB_DP_INV :
+					   USB_DP;
+		}
+		/* USB without DP */
+		else {
+			usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ?
+					   USB_INV :
+					   USB;
+		}
+	}
+	/* DP without USB */
+	else if (mux_state & USB_PD_MUX_DP_ENABLED) {
+		usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ? DP_INV :
+									DP;
+	}
+	/* Nothing enabled */
+	else
+		return EC_SUCCESS;
+	/* Write the retimer config byte */
+	if (usb_mode == USB_INV) {
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_GENERAL4, 0x15);
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_DISPLAYPORT_1, 0x33);
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_DISPLAYPORT_2, 0x33);
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_USB3_1_1, 0x22);
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_USB3_1_2, 0x22);
+	} else if (usb_mode == USB) {
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_GENERAL4, 0x11);
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_DISPLAYPORT_1, 0x33);
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_DISPLAYPORT_2, 0x33);
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_USB3_1_1, 0x22);
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_USB3_1_2, 0x22);
+	} else if (usb_mode == USB_DP_INV) {
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_GENERAL4, 0x1F);
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_DISPLAYPORT_1, 0x33);
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_DISPLAYPORT_2, 0x99);
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_USB3_1_1, 0x22);
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_USB3_1_2, 0x22);
+	} else if (usb_mode == USB_DP) {
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_GENERAL4, 0x1B);
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_DISPLAYPORT_1, 0x99);
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_DISPLAYPORT_2, 0x33);
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_USB3_1_1, 0x22);
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_USB3_1_2, 0x22);
+	} else if (usb_mode == DP_INV) {
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_GENERAL4, 0x1E);
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_DISPLAYPORT_1, 0x99);
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_DISPLAYPORT_2, 0x99);
+	} else if (usb_mode == DP) {
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_GENERAL4, 0x1A);
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_DISPLAYPORT_1, 0x99);
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_DISPLAYPORT_2, 0x99);
+	}
+
+	return rv;
+}
+
+static int board_ps8743_mux_set(const struct usb_mux *me, mux_state_t mux_state)
+{
+	return ps8743_write(me, PS8743_REG_USB_EQ_RX, PS8743_USB_EQ_RX_16_7_DB);
+}
+
+const struct usb_mux usbc1_retimer = {
+	.usb_port = 1,
+	.i2c_port = I2C_PORT_SUB_USB_C1,
+	.i2c_addr_flags = TUSB544_I2C_ADDR_FLAGS0,
+	.driver = &tusb544_drv,
+	.board_set = &board_tusb544_set,
+};
+
+const struct usb_mux usbc1_virtual_mux_ps8743 = {
+	.usb_port = 1,
+	.driver = &virtual_usb_mux_driver,
+	.hpd_update = &virtual_hpd_update,
+};
+
+struct usb_mux usbc1_mux0_data = {
+	.usb_port = 1,
+	.i2c_port = I2C_PORT_SUB_USB_C1,
+	.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+	.driver = &it5205_usb_mux_driver,
+};
+
+struct usb_mux_chain usbc1_mux1 = {
+	.mux = &usbc1_retimer,
+};
+
+/* USB Muxes */
+struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+			},
+	},
+	{
+		.mux = &usbc1_mux0_data,
+		.next = &usbc1_mux1,
+	},
+};
+
+static const struct ec_response_keybd_config galith_kb = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY | KEYBD_CAP_NUMERIC_KEYPAD,
+};
+
+static const struct ec_response_keybd_config galtic_kb = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_FORWARD,		/* T2 */
+		TK_REFRESH,		/* T3 */
+		TK_FULLSCREEN,		/* T4 */
+		TK_OVERVIEW,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	if (get_cbi_fw_config_numeric_pad() == NUMERIC_PAD_PRESENT)
+		return &galith_kb;
+	else
+		return &galtic_kb;
+}
+
+void board_init(void)
+{
+	int on;
+
+	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_INT_ODL);
+
+	/*
+	 * If interrupt lines are already low, schedule them to be processed
+	 * after inits are completed.
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL))
+		hook_call_deferred(&check_c0_line_data, 0);
+	if (!gpio_get_level(GPIO_USB_C1_INT_ODL))
+		hook_call_deferred(&check_c1_line_data, 0);
+
+	gpio_enable_interrupt(GPIO_USB_C0_CCSBU_OVP_ODL);
+	/* Enable Base Accel interrupt */
+	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
+
+	/* Turn on 5V if the system is on, otherwise turn it off */
+	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
+			      CHIPSET_STATE_SOFT_OFF);
+	board_power_5v_enable(on);
+
+	if (get_cbi_fw_config_numeric_pad() == NUMERIC_PAD_ABSENT) {
+		/* Disable scanning KSO13 and 14 if keypad isn't present. */
+		keyboard_raw_set_cols(KEYBOARD_COLS_NO_KEYPAD);
+	} else {
+		/* Setting scan mask KSO11, KSO12, KSO13 and KSO14 */
+		keyscan_config.actual_key_mask[11] = 0xfe;
+		keyscan_config.actual_key_mask[12] = 0xff;
+		keyscan_config.actual_key_mask[13] = 0xff;
+		keyscan_config.actual_key_mask[14] = 0xff;
+	}
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+void setup_mux_config(void)
+{
+	if (get_cbi_ssfc_mux_redriver() == SSFC_MUX_PS8743) {
+		usbc1_mux0_data.i2c_addr_flags = PS8743_I2C_ADDR1_FLAG;
+		usbc1_mux0_data.driver = &ps8743_usb_mux_driver;
+		usbc1_mux1.mux = &usbc1_virtual_mux_ps8743;
+		usbc1_mux0_data.board_set = &board_ps8743_mux_set;
+	}
+}
+DECLARE_HOOK(HOOK_INIT, setup_mux_config, HOOK_PRIO_INIT_I2C + 2);
+
+void board_hibernate(void)
+{
+	/*
+	 * Put all charger ICs present into low power mode before entering
+	 * z-state.
+	 */
+	raa489000_hibernate(CHARGER_PRIMARY, true);
+	if (board_get_charger_chip_count() > 1)
+		raa489000_hibernate(CHARGER_SECONDARY, true);
+}
+
+__override void board_ocpc_init(struct ocpc_data *ocpc)
+{
+	/* There's no provision to measure Isys */
+	ocpc->chg_flags[CHARGER_SECONDARY] |= OCPC_NO_ISYS_MEAS_CAP;
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * Nothing to do.  TCPC C0 is internal, TCPC C1 reset pin is not
+	 * connected to the EC.
+	 */
+}
+
+__override void board_power_5v_enable(int enable)
+{
+	/*
+	 * Motherboard has a GPIO to turn on the 5V regulator, but the sub-board
+	 * sets it through the charger GPIO.
+	 */
+	gpio_set_level(GPIO_EN_PP5000, !!enable);
+	gpio_set_level(GPIO_EN_USB_A0_VBUS, !!enable);
+	if (isl923x_set_comparator_inversion(1, !!enable))
+		CPRINTS("Failed to %sable sub rails!", enable ? "en" : "dis");
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+	int regval;
+
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
+			if (regval)
+				status = PD_STATUS_TCPC_ALERT_0;
+		}
+	}
+
+	/* Check whether TCPC 1 pulled the shared interrupt line */
+	if (!gpio_get_level(GPIO_USB_C1_INT_ODL)) {
+		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
+			if (regval)
+				status = PD_STATUS_TCPC_ALERT_1;
+		}
+	}
+
+	return status;
+}
+
+int board_is_sourcing_vbus(int port)
+{
+	int regval;
+
+	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
+	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count());
+	int i;
+	int old_port;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	old_port = charge_manager_get_active_charge_port();
+
+	CPRINTS("New chg p%d", port);
+
+	/* Disable all ports. */
+	if (port == CHARGE_PORT_NONE) {
+		for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+			tcpc_write(i, TCPC_REG_COMMAND,
+				   TCPC_REG_COMMAND_SNK_CTRL_LOW);
+			raa489000_enable_asgate(i, false);
+		}
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if port is sourcing VBUS. */
+	if (board_is_sourcing_vbus(port)) {
+		CPRINTS("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * Turn off the other ports sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+		if (port == i)
+			continue;
+
+		if (tcpc_write(i, TCPC_REG_COMMAND,
+			       TCPC_REG_COMMAND_SNK_CTRL_LOW))
+			CPRINTS("p%d: sink path disable failed.", i);
+		raa489000_enable_asgate(i, false);
+	}
+
+	/*
+	 * Stop the charger IC from switching while changing ports.  Otherwise,
+	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
+	 */
+	if ((old_port != CHARGE_PORT_NONE) && (old_port != port))
+		charger_discharge_on_ac(1);
+
+	/* Enable requested charge port. */
+	if (raa489000_enable_asgate(port, true) ||
+	    tcpc_write(port, TCPC_REG_COMMAND,
+		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
+		CPRINTS("p%d: sink path enable failed.", port);
+		charger_discharge_on_ac(0);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	/* Allow the charger IC to begin/continue switching. */
+	charger_discharge_on_ac(0);
+
+	return EC_SUCCESS;
+}
+
+__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+				       int *ki_div, int *kd, int *kd_div)
+{
+	*kp = 1;
+	*kp_div = 20;
+	*ki = 1;
+	*ki_div = 250;
+	*kd = 0;
+	*kd_div = 1;
+}
+
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	if (port < 0 || port > board_get_usb_pd_port_count())
+		return;
+
+	raa489000_set_output_current(port, rp);
+}
+
+/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_KBLIGHT] = {
+		.channel = 0,
+		.flags = PWM_CONFIG_DSLEEP,
+		.freq_hz = 10000,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+/* Sensor Mutexes */
+static struct mutex g_lid_mutex;
+static struct mutex g_base_mutex;
+
+/* Sensor Data */
+static struct accelgyro_saved_data_t g_bma253_data;
+static struct kionix_accel_data g_kx022_data;
+static struct bmi_drv_data_t g_bmi160_data;
+static struct icm_drv_data_t g_icm426xx_data;
+
+const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+				      { 0, FLOAT_TO_FP(-1), 0 },
+				      { 0, 0, FLOAT_TO_FP(-1) } };
+
+const mat33_fp_t base_standard_ref_icm = { { FLOAT_TO_FP(1), 0, 0 },
+					   { 0, FLOAT_TO_FP(-1), 0 },
+					   { 0, 0, FLOAT_TO_FP(-1) } };
+
+const mat33_fp_t base_standard_ref_bmi = { { 0, FLOAT_TO_FP(-1), 0 },
+					   { FLOAT_TO_FP(-1), 0, 0 },
+					   { 0, 0, FLOAT_TO_FP(-1) } };
+
+struct motion_sensor_t bma253_lid_accel = {
+	.name = "Lid Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_BMA255,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_LID,
+	.drv = &bma2x2_accel_drv,
+	.mutex = &g_lid_mutex,
+	.drv_data = &g_bma253_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
+	.rot_standard_ref = &lid_standard_ref,
+	.default_range = 2, /* g */
+	/* We only use 2g because its resolution is only 8-bits */
+	.min_frequency = BMA255_ACCEL_MIN_FREQ,
+	.max_frequency = BMA255_ACCEL_MAX_FREQ,
+	.config = {
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	},
+};
+
+struct motion_sensor_t bmi160_base_accel = {
+	.name = "Base Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_BMI160,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &bmi160_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_bmi160_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+	.rot_standard_ref = &base_standard_ref_bmi,
+	.default_range = 4,  /* g */
+	.min_frequency = BMI_ACCEL_MIN_FREQ,
+	.max_frequency = BMI_ACCEL_MAX_FREQ,
+	.config = {
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 13000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+	},
+};
+
+struct motion_sensor_t bmi160_base_gyro = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_BMI160,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &bmi160_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_bmi160_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &base_standard_ref_bmi,
+	.min_frequency = BMI_GYRO_MIN_FREQ,
+	.max_frequency = BMI_GYRO_MAX_FREQ,
+};
+
+/* Drivers */
+struct motion_sensor_t motion_sensors[] = {
+	[LID_ACCEL] = {
+		.name = "Lid Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_KX022,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &kionix_accel_drv,
+		.mutex = &g_lid_mutex,
+		.drv_data = &g_kx022_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = KX022_ADDR0_FLAGS,
+		.rot_standard_ref = &lid_standard_ref,
+		.default_range = 2, /* g */
+		/* We only use 2g because its resolution is only 8-bits */
+		.min_frequency = KX022_ACCEL_MIN_FREQ,
+		.max_frequency = KX022_ACCEL_MAX_FREQ,
+		.config = {
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+		},
+	},
+	[BASE_ACCEL] = {
+		.name = "Base Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_ICM426XX,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &icm426xx_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = &g_icm426xx_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+		.rot_standard_ref = &base_standard_ref_icm,
+		.default_range = 4,  /* g */
+		.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
+		.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
+		.config = {
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+		},
+	},
+	[BASE_GYRO] = {
+		.name = "Base Gyro",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_ICM426XX,
+		.type = MOTIONSENSE_TYPE_GYRO,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &icm426xx_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = &g_icm426xx_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+		.default_range = 1000, /* dps */
+		.rot_standard_ref = &base_standard_ref_icm,
+		.min_frequency = ICM426XX_GYRO_MIN_FREQ,
+		.max_frequency = ICM426XX_GYRO_MAX_FREQ,
+	},
+};
+
+const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	if (get_cbi_ssfc_base_sensor() == SSFC_SENSOR_BMI160)
+		bmi160_interrupt(signal);
+	else
+		icm426xx_interrupt(signal);
+}
+
+static void board_sensors_init(void)
+{
+	if (get_cbi_ssfc_lid_sensor() == SSFC_SENSOR_BMA255) {
+		motion_sensors[LID_ACCEL] = bma253_lid_accel;
+		ccprints("LID_ACCEL is BMA253");
+	} else
+		ccprints("LID_ACCEL is KX022");
+
+	if (get_cbi_ssfc_base_sensor() == SSFC_SENSOR_BMI160) {
+		motion_sensors[BASE_ACCEL] = bmi160_base_accel;
+		motion_sensors[BASE_GYRO] = bmi160_base_gyro;
+		ccprints("BASE_ACCEL is BMI160");
+	} else
+		ccprints("BASE_ACCEL is ICM426XX");
+}
+DECLARE_HOOK(HOOK_INIT, board_sensors_init, HOOK_PRIO_DEFAULT);
+
+/* Thermistors */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1] = { .name = "Charger",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Vcore",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CHARGER          \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(85), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(98), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_charger =
+	THERMAL_CHARGER;
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_VCORE            \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(50), \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_vcore =
+	THERMAL_VCORE;
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_AMBIENT          \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(50), \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_ambient =
+	THERMAL_AMBIENT;
+
+struct ec_thermal_config thermal_params[] = {
+	[TEMP_SENSOR_1] = THERMAL_CHARGER,
+	[TEMP_SENSOR_2] = THERMAL_VCORE,
+	[TEMP_SENSOR_3] = THERMAL_AMBIENT,
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
+
+/* This callback disables keyboard when convertibles are fully open */
+__override void lid_angle_peripheral_enable(int enable)
+{
+	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
+
+	/*
+	 * If the lid is in tablet position via other sensors,
+	 * ignore the lid angle, which might be faulty then
+	 * disable keyboard.
+	 */
+	if (tablet_get_mode())
+		enable = 0;
+
+	if (enable) {
+		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
+	} else {
+		/*
+		 * Ensure that the chipset is off before disabling the keyboard.
+		 * When the chipset is on, the EC keeps the keyboard enabled and
+		 * the AP decides whether to ignore input devices or not.
+		 */
+		if (!chipset_in_s0)
+			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
+	}
+}
+
+__override void board_pulse_entering_rw(void)
+{
+	/*
+	 * On the ITE variants, the EC_ENTERING_RW signal was connected to a pin
+	 * which is active high by default. This cause Cr50 to think that the
+	 * EC has jumped to its RW image even though this may not be the case.
+	 * The pin is changed to GPIO_EC_ENTERING_RW2.
+	 */
+	gpio_set_level(GPIO_EC_ENTERING_RW, 1);
+	gpio_set_level(GPIO_EC_ENTERING_RW2, 1);
+	usleep(MSEC);
+	gpio_set_level(GPIO_EC_ENTERING_RW, 0);
+	gpio_set_level(GPIO_EC_ENTERING_RW2, 0);
+}
+
+enum battery_cell_type battery_cell;
+
+static void get_battery_cell(void)
+{
+	int val;
+
+	if (i2c_read16(I2C_PORT_USB_C0, ISL923X_ADDR_FLAGS, ISL9238_REG_INFO2,
+		       &val) == EC_SUCCESS) {
+		/* PROG resistor read out. Number of battery cells [4:0] */
+		val = val & 0x001f;
+	}
+
+	if (val == 0 || val >= 0x18)
+		battery_cell = BATTERY_CELL_TYPE_1S;
+	else if (val >= 0x01 && val <= 0x08)
+		battery_cell = BATTERY_CELL_TYPE_2S;
+	else if (val >= 0x09 && val <= 0x10)
+		battery_cell = BATTERY_CELL_TYPE_3S;
+	else
+		battery_cell = BATTERY_CELL_TYPE_4S;
+
+	CPRINTS("Get battery cells: %d", battery_cell);
+}
+DECLARE_HOOK(HOOK_INIT, get_battery_cell, HOOK_PRIO_INIT_I2C + 1);
+
+enum battery_cell_type board_get_battery_cell_type(void)
+{
+	return battery_cell;
+}
diff --git a/board/galtic/board.h b/board/galtic/board.h
new file mode 100644
index 0000000000..cfed23b359
--- /dev/null
+++ b/board/galtic/board.h
@@ -0,0 +1,160 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Waddledee board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* Select Baseboard features */
+#define VARIANT_DEDEDE_EC_IT8320
+#include "baseboard.h"
+
+#define CONFIG_CMD_TCPC_DUMP
+#define CONFIG_CMD_CHARGER_DUMP
+
+/* Battery */
+#define CONFIG_BATTERY_FUEL_GAUGE
+
+/* BC 1.2 */
+#define CONFIG_BC12_DETECT_PI3USB9201
+
+/* Charger */
+#define CONFIG_CHARGER_RAA489000 /* C0 and C1: Charger */
+#define PD_MAX_VOLTAGE_MV 20000
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#undef CONFIG_CHARGER_SINGLE_CHIP
+#define CONFIG_OCPC
+#define CONFIG_OCPC_DEF_RBATT_MOHMS               \
+	22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \
+	    */
+#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
+#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
+
+#define GPIO_USB_C1_INT_ODL GPIO_SUB_USB_C1_INT_ODL
+
+/* LED */
+#define CONFIG_LED_ONOFF_STATES
+#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
+
+/* PWM */
+#define CONFIG_PWM
+
+/* Sensors */
+#define CONFIG_ACCEL_BMA255 /* Lid accel */
+#define CONFIG_ACCEL_KX022 /* Lid accel */
+#define CONFIG_ACCELGYRO_BMI160 /* Base accel */
+#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+#define CONFIG_ACCELGYRO_BMI_COMM_I2C
+#define CONFIG_ACCELGYRO_ICM426XX /* Base accel */
+#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+#define CONFIG_ACCELGYRO_ICM_COMM_I2C
+
+/* Sensors without hardware FIFO are in forced mode */
+#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
+
+/* Enable sensor fifo, must also define the _SIZE and _THRES */
+#define CONFIG_ACCEL_FIFO
+/* Power of 2 - Too large of a fifo causes too much timestamp jitter */
+#define CONFIG_ACCEL_FIFO_SIZE 256
+#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
+
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_UPDATE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+
+#define CONFIG_TABLET_MODE
+#define CONFIG_TABLET_MODE_SWITCH
+#define CONFIG_GMR_TABLET_MODE
+
+/* TCPC */
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#define CONFIG_USB_PD_TCPM_RAA489000
+#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+#define CONFIG_USB_PD_VBUS_DETECT_TCPC
+#define CONFIG_USB_PD_DISCHARGE_TCPC
+#define CONFIG_USB_PD_TCPC_LOW_POWER
+#define CONFIG_USB_PD_5V_EN_CUSTOM
+
+/* Thermistors */
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_THERMISTOR
+#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
+#define CONFIG_THROTTLE_AP
+
+/* USB Mux and Retimer */
+#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */
+#define CONFIG_USB_MUX_PS8743 /* C1: PS8743 Mux */
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */
+
+#define CONFIG_USBC_RETIMER_TUSB544 /* C1 Redriver: TUSB544 */
+#define CONFIG_USB_MUX_RUNTIME_CONFIG
+#define CONFIG_USB_MUX_VIRTUAL
+
+/* Keyboard */
+#define CONFIG_KEYBOARD_VIVALDI
+#define CONFIG_KEYBOARD_REFRESH_ROW3
+#define CONFIG_KEYBOARD_KEYPAD
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum chg_id {
+	CHARGER_PRIMARY,
+	CHARGER_SECONDARY,
+	CHARGER_NUM,
+};
+
+enum pwm_channel {
+	PWM_CH_KBLIGHT,
+	PWM_CH_COUNT,
+};
+
+/* Motion sensors */
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
+
+/* ADC channels */
+enum adc_channel {
+	ADC_VSNS_PP3300_A, /* ADC0 */
+	ADC_TEMP_SENSOR_1, /* ADC2 */
+	ADC_TEMP_SENSOR_2, /* ADC3 */
+	ADC_TEMP_SENSOR_3, /* ADC15 */
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1,
+	TEMP_SENSOR_2,
+	TEMP_SENSOR_3,
+	TEMP_SENSOR_COUNT
+};
+
+/* List of possible batteries */
+enum battery_type {
+	BATTERY_C140254,
+	BATTERY_C340184,
+	BATTERY_C140243,
+	BATTERY_TYPE_COUNT,
+};
+
+enum battery_cell_type {
+	BATTERY_CELL_TYPE_1S = 1,
+	BATTERY_CELL_TYPE_2S = 2,
+	BATTERY_CELL_TYPE_3S = 3,
+	BATTERY_CELL_TYPE_4S = 4,
+};
+
+void motion_interrupt(enum gpio_signal signal);
+enum battery_cell_type board_get_battery_cell_type(void);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/galtic/build.mk b/board/galtic/build.mk
new file mode 100644
index 0000000000..9b862c7624
--- /dev/null
+++ b/board/galtic/build.mk
@@ -0,0 +1,15 @@
+# -*- makefile -*-
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=it83xx
+CHIP_FAMILY:=it8320
+CHIP_VARIANT:=it8320dx
+BASEBOARD:=dedede
+
+board-y=board.o cbi_ssfc.o led.o usb_pd_policy.o
+board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/galtic/cbi_ssfc.c b/board/galtic/cbi_ssfc.c
new file mode 100644
index 0000000000..7a7ed9f7cf
--- /dev/null
+++ b/board/galtic/cbi_ssfc.c
@@ -0,0 +1,41 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi_ssfc.h"
+#include "common.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "hooks.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+/* Cache SSFC on init since we don't expect it to change in runtime */
+static union dedede_cbi_ssfc cached_ssfc;
+BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
+
+static void cbi_ssfc_init(void)
+{
+	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
+		/* Default to 0 when CBI isn't populated */
+		cached_ssfc.raw_value = 0;
+
+	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
+}
+DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
+
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
+{
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
+}
+
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
+{
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
+}
+
+enum ec_ssfc_mux_redriver get_cbi_ssfc_mux_redriver(void)
+{
+	return (enum ec_ssfc_mux_redriver)cached_ssfc.mux_redriver;
+}
diff --git a/board/galtic/cbi_ssfc.h b/board/galtic/cbi_ssfc.h
new file mode 100644
index 0000000000..84f321977e
--- /dev/null
+++ b/board/galtic/cbi_ssfc.h
@@ -0,0 +1,75 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _DEDEDE_CBI_SSFC__H_
+#define _DEDEDE_CBI_SSFC__H_
+
+#include "stdint.h"
+
+/****************************************************************************
+ * Dedede CBI Second Source Factory Cache
+ */
+
+/*
+ * Base Sensor (Bits 0-2)
+ */
+enum ec_ssfc_base_sensor {
+	SSFC_SENSOR_BASE_DEFAULT = 0,
+	SSFC_SENSOR_BMI160 = 1,
+	SSFC_SENSOR_ICM426XX = 2,
+	SSFC_SENSOR_LSM6DSM = 3,
+	SSFC_SENSOR_ICM42607 = 4
+};
+
+/*
+ * Lid Sensor (Bits 3-5)
+ */
+enum ec_ssfc_lid_sensor {
+	SSFC_SENSOR_LID_DEFAULT = 0,
+	SSFC_SENSOR_BMA255 = 1,
+	SSFC_SENSOR_KX022 = 2,
+	SSFC_SENSOR_LIS2DWL = 3
+};
+
+/*
+ * Mux Redriver (Bit 6)
+ */
+enum ec_ssfc_mux_redriver {
+	SSFC_MUX_DEFAULT = 0, /* IT5205 + TUSB544 */
+	SSFC_MUX_PS8743 = 1,
+};
+
+union dedede_cbi_ssfc {
+	struct {
+		uint32_t base_sensor : 3;
+		uint32_t lid_sensor : 3;
+		uint32_t mux_redriver : 1;
+		uint32_t reserved_2 : 25;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Get the Base sensor type from SSFC_CONFIG.
+ *
+ * @return the Base sensor board type.
+ */
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
+
+/**
+ * Get the Lid sensor type from SSFC_CONFIG.
+ *
+ * @return the Lid sensor board type.
+ */
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
+
+/**
+ * Get the MUX and redriver type from SSFC_CONFIG.
+ *
+ * @return the MUX and redriver type.
+ */
+enum ec_ssfc_mux_redriver get_cbi_ssfc_mux_redriver(void);
+
+#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/galtic/ec.tasklist b/board/galtic/ec.tasklist
new file mode 100644
index 0000000000..bc2fea6148
--- /dev/null
+++ b/board/galtic/ec.tasklist
@@ -0,0 +1,25 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, TRENTA_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, ULTRA_TASK_STACK_SIZE) \
+        TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+        TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE) \
+        TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/galtic/gpio.inc b/board/galtic/gpio.inc
new file mode 100644
index 0000000000..721a193f36
--- /dev/null
+++ b/board/galtic/gpio.inc
@@ -0,0 +1,145 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+/* Power State interrupts */
+GPIO_INT(SLP_S4_L,		PIN(I, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,		PIN(H, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(SLP_S0_L,		PIN(E, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,		PIN(G, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID0,	PIN(D, 0), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(RSMRST_PWRGD_L,	PIN(E, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(CPU_C10_GATE_L,	PIN(G, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_DRAM_OD,		PIN(D, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(PG_PP1050_ST_OD,	PIN(L, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID1,	PIN(K, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_VCCIO_EXT_OD,	PIN(D, 7), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(ESPI_RESET_L, 	 PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt)
+
+GPIO_INT(H1_EC_PWR_BTN_ODL,	PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
+#ifdef CONFIG_LOW_POWER_IDLE
+/* Used to wake up the EC from Deep Doze mode when writing to console */
+GPIO_INT(UART1_RX,	 PIN(B, 0), GPIO_INT_BOTH, uart_deepsleep_interrupt)	/* UART_DBG_TX_EC_RX */
+#endif
+
+/* USB-C interrupts */
+GPIO_INT(USB_C0_INT_ODL,	PIN(K, 0), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt) /* BC12 and charger */
+GPIO_INT(SUB_USB_C1_INT_ODL,	PIN(E, 6), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c1_interrupt)
+GPIO_INT(USB_C0_CCSBU_OVP_ODL,	PIN(K, 6), GPIO_INT_FALLING | GPIO_PULL_UP, c0_ccsbu_ovp_interrupt) /* Fault protection */
+
+/* Other interrupts */
+GPIO_INT(LID_OPEN,		PIN(F, 3), GPIO_INT_BOTH, lid_interrupt)
+GPIO_INT(LID_360_L,		PIN(A, 7), GPIO_INT_BOTH, gmr_tablet_switch_isr)
+GPIO_INT(VOLDN_BTN_ODL,		PIN(I, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(VOLUP_BTN_ODL,		PIN(I, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(J, 0), GPIO_INT_FALLING | GPIO_SEL_1P8V, motion_interrupt)
+GPIO_INT(EC_WP_OD,		PIN(A, 6), GPIO_INT_BOTH, switch_interrupt)
+
+/* Power sequence GPIOs */
+GPIO(EC_AP_RTCRST,		PIN(K, 2), GPIO_OUT_LOW)
+GPIO(EC_AP_PWR_BTN_ODL,		PIN(B, 6), GPIO_ODR_HIGH)
+GPIO(EC_AP_DPWROK,		PIN(L, 7), GPIO_OUT_LOW)
+GPIO(EC_AP_RSMRST_L,		PIN(H, 0), GPIO_OUT_LOW)
+GPIO(EC_AP_WAKE_ODL,		PIN(D, 5), GPIO_ODR_HIGH)
+GPIO(SYS_RST_ODL,		PIN(D, 1), GPIO_ODR_HIGH)
+GPIO(EC_AP_SYS_PWROK,		PIN(F, 2), GPIO_OUT_LOW)
+GPIO(PG_PP5000_U_OD,		PIN(E, 3), GPIO_INPUT)
+GPIO(EN_PP3300_A,		PIN(C, 5), GPIO_OUT_LOW)
+GPIO(EC_AP_PCH_PWROK_OD,	PIN(D, 6), GPIO_ODR_LOW)
+GPIO(EN_PP5000_U,		PIN(K, 5), GPIO_OUT_LOW)
+/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
+GPIO(EN_VCCST,			PIN(D, 4), GPIO_INPUT)
+GPIO(EN_VCCIO_EXT,		PIN(B, 2), GPIO_OUT_LOW)
+GPIO(EC_PROCHOT_ODL,		PIN(I, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(EC_AP_VCCST_PWRGD_OD,	PIN(E, 5), GPIO_ODR_LOW)
+GPIO(ALL_SYS_PWRGD,		PIN(B, 7), GPIO_OUT_LOW)
+GPIO(EN_SLP_Z,			PIN(K, 3), GPIO_OUT_LOW)
+
+/* Required for icelake chipset code, but implemented through other means for dedede */
+UNIMPLEMENTED(AC_PRESENT)
+UNIMPLEMENTED(PG_EC_DSW_PWROK)
+UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
+
+/* I2C pins - Alternate function below configures I2C module on these pins */
+GPIO(EC_I2C_EEPROM_SCL,		PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SDA,		PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SCL,	PIN(C, 1), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SDA,	PIN(C, 2), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,		PIN(F, 6), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SENSOR_SDA,		PIN(F, 7), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SUB_USB_C1_SCL,	PIN(E, 0), GPIO_INPUT)
+GPIO(EC_I2C_SUB_USB_C1_SDA,	PIN(E, 7), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SCL,		PIN(A, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SDA,		PIN(A, 5), GPIO_INPUT)
+
+/* USB pins */
+GPIO(EC_AP_USB_C0_HPD,		PIN(L, 4), GPIO_OUT_LOW)
+GPIO(EC_AP_USB_C1_HDMI_HPD,	PIN(K, 7), GPIO_OUT_LOW)
+GPIO(EN_USB_A0_VBUS,		PIN(L, 6), GPIO_OUT_LOW) /* Board rev 1, NC board rev 0 */
+
+/* MKBP event synchronization */
+GPIO(EC_AP_MKBP_INT_L,	PIN(L, 5), GPIO_ODR_HIGH)
+
+/* Misc pins which will run to the I/O board */
+
+/* Misc */
+GPIO(EN_BL_OD,			PIN(K, 4), GPIO_ODR_LOW)
+GPIO(EC_ENTERING_RW,		PIN(G, 0), GPIO_OUT_LOW)
+GPIO(EC_ENTERING_RW2,		PIN(C, 7), GPIO_OUT_LOW)
+GPIO(CCD_MODE_ODL,		PIN(H, 5), GPIO_ODR_HIGH)
+GPIO(EC_BATTERY_PRES_ODL,	PIN(I, 4), GPIO_INPUT)
+GPIO(ECH1_PACKET_MODE,		PIN(H, 1), GPIO_OUT_LOW)
+
+/* LED */
+GPIO(LED_R_ODL,                 PIN(A, 1), GPIO_OUT_HIGH)
+GPIO(LED_G_ODL,                 PIN(A, 2), GPIO_OUT_HIGH)
+
+/* NC pins, enable internal pull-down to avoid floating state. */
+GPIO(GPIOA0_NC, PIN(A, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOA3_NC, PIN(A, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOB5_NC, PIN(B, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOC3_NC, PIN(C, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOC4_NC, PIN(C, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOC6_NC, PIN(C, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOF0_NC, PIN(F, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOF1_NC, PIN(F, 1), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOF4_NC, PIN(F, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOF5_NC, PIN(F, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG3_NC, PIN(G, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG4_NC, PIN(G, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG5_NC, PIN(G, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG6_NC, PIN(G, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG7_NC, PIN(G, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOH4_NC, PIN(H, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOH6_NC, PIN(H, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ1_NC, PIN(J, 1), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ3_NC, PIN(J, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ4_NC, PIN(J, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ5_NC, PIN(J, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ6_NC, PIN(J, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOL0_NC, PIN(L, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOL3_NC, PIN(L, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOM6_NC, PIN(M, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+
+/* Alternate functions GPIO definitions */
+/* UART */
+ALTERNATE(PIN_MASK(B, BIT(0) | BIT(1)), 0, MODULE_UART, 0)		/* UART for debug */
+
+/* I2C */
+ALTERNATE(PIN_MASK(B, BIT(3) | BIT(4)), 0, MODULE_I2C, 0)		/* I2C0 */
+ALTERNATE(PIN_MASK(C, BIT(1) | BIT(2)), 0, MODULE_I2C, 0)		/* I2C1 */
+ALTERNATE(PIN_MASK(F, BIT(6) | BIT(7)), 0, MODULE_I2C, GPIO_SEL_1P8V)	/* I2C2 - 1.8V */
+ALTERNATE(PIN_MASK(E, BIT(0) | BIT(7)), 0, MODULE_I2C, 0)		/* I2C4 */
+ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), 0, MODULE_I2C, 0)		/* I2C5 */
+
+/* ADC */
+ALTERNATE(PIN_MASK(L, BIT(2)), 0, MODULE_ADC, 0)		/* ADC15: TEMP_SENSOR_3 */
+ALTERNATE(PIN_MASK(I, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0)	/* ADC0: EC_VSNS_PP3300_A, ADC2: TEMP_SENSOR_1, ADC3: TEMP_SENSOR_2 */
+
diff --git a/board/galtic/led.c b/board/galtic/led.c
new file mode 100644
index 0000000000..1438ccd91a
--- /dev/null
+++ b/board/galtic/led.c
@@ -0,0 +1,106 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "chipset.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
+
+__override const int led_charge_lvl_1;
+__override const int led_charge_lvl_2 = 95;
+
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { LED_OFF, 2 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_BATTERY_LED,
+};
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_WHITE:
+		gpio_set_level(GPIO_LED_R_ODL, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_G_ODL, LED_ON_LVL);
+		break;
+	case EC_LED_COLOR_AMBER:
+		gpio_set_level(GPIO_LED_R_ODL, LED_ON_LVL);
+		gpio_set_level(GPIO_LED_G_ODL, LED_OFF_LVL);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		gpio_set_level(GPIO_LED_R_ODL, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_G_ODL, LED_OFF_LVL);
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_battery(EC_LED_COLOR_WHITE);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(EC_LED_COLOR_AMBER);
+		else
+			led_set_color_battery(LED_OFF);
+	}
+	return EC_SUCCESS;
+}
+
+__override enum led_states board_led_get_state(enum led_states desired_state)
+{
+	/* Battery error LED behavior as below:
+	 * S0: Blinking Amber LED, 1s on/ 1s off
+	 * S3/S5: following S3/S5 behavior
+	 * Add function to let battery error LED follow S3/S5 behavior in S3/S5.
+	 */
+
+	if (desired_state == STATE_BATTERY_ERROR) {
+		if (chipset_in_state(CHIPSET_STATE_ON))
+			return desired_state;
+		else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
+			return STATE_DISCHARGE_S3;
+		else
+			return STATE_DISCHARGE_S5;
+	}
+	return desired_state;
+}
diff --git a/board/galtic/usb_pd_policy.c b/board/galtic/usb_pd_policy.c
new file mode 100644
index 0000000000..23166f7fca
--- /dev/null
+++ b/board/galtic/usb_pd_policy.c
@@ -0,0 +1,61 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "driver/charger/isl923x_public.h"
+#include "driver/tcpm/tcpci.h"
+#include "usb_pd.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+int pd_check_vconn_swap(int port)
+{
+	/* Allow VCONN swaps if the AP is on. */
+	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
+}
+
+void pd_power_supply_reset(int port)
+{
+	/* Disable VBUS */
+	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	if (port >= board_get_usb_pd_port_count())
+		return EC_ERROR_INVAL;
+
+	/* Disable charging. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
+	if (rv)
+		return rv;
+
+	/* Our policy is not to source VBUS when the AP is off. */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	/* Provide Vbus. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
+	if (rv)
+		return rv;
+
+	rv = raa489000_enable_asgate(port, true);
+	if (rv)
+		return rv;
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
diff --git a/board/galtic/vif_override.xml b/board/galtic/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/galtic/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/garg/battery.c b/board/garg/battery.c
index 119023877e..5706344191 100644
--- a/board/garg/battery.c
+++ b/board/garg/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -89,6 +89,63 @@ const struct board_batt_params board_battery_info[] = {
 			.discharging_max_c = 60,
 		},
 	},
+
+	/* Simplo CA475778G 916QA141H battery information */
+	[BATTERY_SIMPLO_CA475778G] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP-CA475778G",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0002,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 13050,		/* mV */
+			.voltage_normal = 11430,
+			.voltage_min = 9000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -20,
+			.discharging_max_c = 60,
+		},
+	},
+	/* Simplo CA475778G_R 916QA152H battery information, BMU RAJ240045 */
+	[BATTERY_SIMPLO_CA475778G_R] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP-CA475778G_R",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 0,
+				.reg_addr = 0x43,
+				.reg_mask = 0x0001,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 13050,		/* mV */
+			.voltage_normal = 11430,
+			.voltage_min = 9000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -20,
+			.discharging_max_c = 60,
+		},
+	},
 };
 BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
 
diff --git a/board/garg/board.c b/board/garg/board.c
index 44cc3b3759..60365a6312 100644
--- a/board/garg/board.c
+++ b/board/garg/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,15 +6,19 @@
 /* Garg board-specific configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "battery.h"
 #include "button.h"
+#include "cbi_ssfc.h"
 #include "charge_manager.h"
 #include "charge_state.h"
 #include "common.h"
 #include "cros_board_info.h"
 #include "driver/accel_kionix.h"
+#include "driver/accelgyro_bmi160.h"
+#include "driver/accelgyro_bmi260.h"
 #include "driver/accelgyro_bmi_common.h"
+#include "driver/accelgyro_icm426xx.h"
+#include "driver/accelgyro_icm_common.h"
 #include "driver/charger/bd9995x.h"
 #include "driver/ppc/nx20p348x.h"
 #include "driver/tcpm/anx7447.h"
@@ -33,18 +37,18 @@
 #include "switch.h"
 #include "system.h"
 #include "tablet_mode.h"
-#include "tcpci.h"
+#include "tcpm/tcpci.h"
 #include "temp_sensor.h"
-#include "thermistor.h"
+#include "temp_sensor/thermistor.h"
 #include "usb_mux.h"
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define USB_PD_PORT_ANX7447	0
-#define USB_PD_PORT_PS8751	1
+#define USB_PD_PORT_ANX7447 0
+#define USB_PD_PORT_PS8751 1
 
 static uint8_t sku_id;
 
@@ -54,17 +58,16 @@ static uint8_t sku_id;
  * that we don't have pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-		{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-		{0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3},
-		{-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0},
-		{1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4},
-		{2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0},
-		{-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1},
-		{-1, -1},
+	{ -1, -1 }, { 0, 5 },	{ 1, 1 }, { 1, 0 },   { 0, 6 },	  { 0, 7 },
+	{ -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 },   { -1, -1 }, { 1, 6 },
+	{ 1, 7 },   { 3, 1 },	{ 2, 0 }, { 1, 5 },   { 2, 6 },	  { 2, 7 },
+	{ 2, 1 },   { 2, 4 },	{ 2, 5 }, { 1, 2 },   { 2, 3 },	  { 2, 2 },
+	{ 3, 0 },   { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 },	  { -1, -1 },
+	{ -1, -1 },
 };
 
 const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 
 static void ppc_interrupt(enum gpio_signal signal)
 {
@@ -87,31 +90,31 @@ static void ppc_interrupt(enum gpio_signal signal)
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_AMB] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_AMB] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				  ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_CHARGER] = { "TEMP_CHARGER", NPCX_ADC_CH1,
+				      ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 },
 	/* Vbus sensing (1/10 voltage divider). */
-	[ADC_VBUS_C0] = {
-		"VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
-	[ADC_VBUS_C1] = {
-		"VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
+	[ADC_VBUS_C0] = { "VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT * 10,
+			  ADC_READ_MAX + 1, 0 },
+	[ADC_VBUS_C1] = { "VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT * 10,
+			  ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp,
-				 .idx = 0},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
+	[TEMP_SENSOR_BATTERY] = { .name = "Battery",
+				  .type = TEMP_SENSOR_TYPE_BATTERY,
+				  .read = charge_get_battery_temp,
+				  .idx = 0 },
+	[TEMP_SENSOR_AMBIENT] = { .name = "Ambient",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_51k1_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_AMB },
+	[TEMP_SENSOR_CHARGER] = { .name = "Charger",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_13k7_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_CHARGER },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -121,15 +124,23 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0,  0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+				       { FLOAT_TO_FP(1), 0, 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
+
+const mat33_fp_t base_icm_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				  { 0, FLOAT_TO_FP(-1), 0 },
+				  { 0, 0, FLOAT_TO_FP(1) } };
+
+static const mat33_fp_t base_bmi260_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+					    { FLOAT_TO_FP(1), 0, 0 },
+					    { 0, 0, FLOAT_TO_FP(1) } };
 
 /* sensor private data */
 static struct kionix_accel_data g_kx022_data;
 static struct bmi_drv_data_t g_bmi160_data;
+static struct bmi_drv_data_t g_bmi260_data;
+static struct icm_drv_data_t g_icm426xx_data;
 
 /* Drivers */
 struct motion_sensor_t motion_sensors[] = {
@@ -207,18 +218,120 @@ struct motion_sensor_t motion_sensors[] = {
 
 unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
+struct motion_sensor_t icm426xx_base_accel = {
+	 .name = "Base Accel",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_ICM426XX,
+	 .type = MOTIONSENSE_TYPE_ACCEL,
+	 .location = MOTIONSENSE_LOC_BASE,
+	 .drv = &icm426xx_drv,
+	 .mutex = &g_base_mutex,
+	 .drv_data = &g_icm426xx_data,
+	 .port = I2C_PORT_SENSOR,
+	 .i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	 .rot_standard_ref = &base_icm_ref,
+	 .default_range = 4,  /* g */
+	 .min_frequency = ICM426XX_ACCEL_MIN_FREQ,
+	 .max_frequency = ICM426XX_ACCEL_MAX_FREQ,
+	 .config = {
+		 /* EC use accel for angle detection */
+		 [SENSOR_CONFIG_EC_S0] = {
+			.odr = 13000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		 },
+		 /* Sensor on for angle detection */
+		 [SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		 },
+	 },
+};
+
+struct motion_sensor_t icm426xx_base_gyro = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &base_icm_ref,
+	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
+	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
+};
+
+struct motion_sensor_t bmi260_base_accel = {
+	.name = "Base Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_BMI260,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &bmi260_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_bmi260_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
+	.rot_standard_ref = &base_bmi260_ref,
+	.min_frequency = BMI_ACCEL_MIN_FREQ,
+	.max_frequency = BMI_ACCEL_MAX_FREQ,
+	.default_range = 4, /* g */
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+		/* Sensor on in S3 */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+	},
+};
+
+struct motion_sensor_t bmi260_base_gyro = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_BMI260,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &bmi260_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_bmi260_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &base_bmi260_ref,
+	.min_frequency = BMI_GYRO_MIN_FREQ,
+	.max_frequency = BMI_GYRO_MAX_FREQ,
+};
+
 static int board_is_convertible(void)
 {
 	/*
-	 * Garg360: 37, 38
+	 * Garg360: 37, 38, 39
 	 * Unprovisioned: 255
 	 */
-	return sku_id == 37 || sku_id == 38 || sku_id == 255;
+	return sku_id == 37 || sku_id == 38 || sku_id == 39 || sku_id == 255;
 }
 
 static void board_update_sensor_config_from_sku(void)
 {
 	if (board_is_convertible()) {
+		if (get_cbi_ssfc_sensor() == SSFC_SENSOR_ICM426XX) {
+			motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
+			motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
+			ccprints("BASE GYRO is ICM426XX");
+		} else if (get_cbi_ssfc_sensor() == SSFC_SENSOR_BMI260) {
+			motion_sensors[BASE_ACCEL] = bmi260_base_accel;
+			motion_sensors[BASE_GYRO] = bmi260_base_gyro;
+			ccprints("BASE GYRO is BMI260");
+		} else
+			ccprints("BASE GYRO is BMI160");
 		motion_sensor_count = ARRAY_SIZE(motion_sensors);
 		/* Enable Base Accel interrupt */
 		gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
@@ -231,6 +344,22 @@ static void board_update_sensor_config_from_sku(void)
 	}
 }
 
+void sensor_interrupt(enum gpio_signal signal)
+{
+	switch (motion_sensors[BASE_ACCEL].chip) {
+	case MOTIONSENSE_CHIP_ICM426XX:
+		icm426xx_interrupt(signal);
+		break;
+	case MOTIONSENSE_CHIP_BMI260:
+		bmi260_interrupt(signal);
+		break;
+	case MOTIONSENSE_CHIP_BMI160:
+	default:
+		bmi160_interrupt(signal);
+		break;
+	}
+}
+
 /* Read CBI from i2c eeprom and initialize variables for board variants */
 static void cbi_init(void)
 {
@@ -245,34 +374,22 @@ static void cbi_init(void)
 }
 DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1);
 
-__override uint32_t board_override_feature_flags0(uint32_t flags0)
-{
-	/*
-	 * Remove keyboard backlight feature for devices that don't support it.
-	 */
-	if (sku_id == 255)
-		return flags0;
-	else
-		return (flags0 & ~EC_FEATURE_MASK_0(EC_FEATURE_PWM_KEYB));
-}
-
 void board_hibernate_late(void)
 {
 	int i;
 
 	const uint32_t hibernate_pins[][2] = {
 		/* Turn off LEDs before going to hibernate */
-		{GPIO_BAT_LED_BLUE_L, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_BAT_LED_ORANGE_L, GPIO_INPUT | GPIO_PULL_UP},
+		{ GPIO_BAT_LED_BLUE_L, GPIO_INPUT | GPIO_PULL_UP },
+		{ GPIO_BAT_LED_ORANGE_L, GPIO_INPUT | GPIO_PULL_UP },
 	};
 
 	for (i = 0; i < ARRAY_SIZE(hibernate_pins); ++i)
 		gpio_set_flags(hibernate_pins[i][0], hibernate_pins[i][1]);
 }
 
-#ifndef TEST_BUILD
 /* This callback disables keyboard when convertibles are fully open */
-void lid_angle_peripheral_enable(int enable)
+__override void lid_angle_peripheral_enable(int enable)
 {
 	/*
 	 * If the lid is in tablet position via other sensors,
@@ -284,7 +401,6 @@ void lid_angle_peripheral_enable(int enable)
 	if (board_is_convertible())
 		keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
 }
-#endif
 
 void board_overcurrent_event(int port, int is_overcurrented)
 {
diff --git a/board/garg/board.h b/board/garg/board.h
index 79871f0af6..90ddb1b217 100644
--- a/board/garg/board.h
+++ b/board/garg/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,24 +8,30 @@
 #ifndef __CROS_EC_BOARD_H
 #define __CROS_EC_BOARD_H
 
+/* Free up flash space */
+#define CONFIG_LTO
+#undef CONFIG_CMD_ACCELSPOOF
+#undef CONFIG_CMD_BATTFAKE
+#undef CONFIG_CMD_MEM
+
 /* Select Baseboard features */
 #define VARIANT_OCTOPUS_EC_NPCX796FB
 #define VARIANT_OCTOPUS_CHARGER_ISL9238
 #include "baseboard.h"
 
-/* I2C bus configuraiton */
-#define I2C_PORT_ACCEL	I2C_PORT_SENSOR
+#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD
 
-/* EC console commands  */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
+/* I2C bus configuraiton */
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
 
 #define CONFIG_LED_COMMON
 
 /* Sensors */
-#define CONFIG_ACCEL_KX022	/* Lid accel */
-#define CONFIG_ACCELGYRO_BMI160	/* Base accel */
-#define CONFIG_SYNC		/* Camera VSYNC */
+#define CONFIG_ACCEL_KX022 /* Lid accel */
+#define CONFIG_ACCELGYRO_BMI160 /* Base accel */
+#define CONFIG_ACCELGYRO_BMI260 /* 3rd Base accel */
+#define CONFIG_ACCELGYRO_ICM426XX /* 2nd Base accel */
+#define CONFIG_SYNC /* Camera VSYNC */
 
 #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
 /* Sensors without hardware FIFO are in forced mode */
@@ -34,9 +40,12 @@
 /* Motion Sense Task Events */
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+#define CONFIG_ACCELGYRO_BMI260_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 
-#define CONFIG_SYNC_INT_EVENT	\
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
+#define CONFIG_SYNC_INT_EVENT TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
 
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_UPDATE
@@ -52,25 +61,29 @@
 #define CONFIG_STEINHART_HART_3V3_13K7_47K_4050B
 #define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
 
-/* Keyboard backliht */
-#define CONFIG_PWM
-#define CONFIG_PWM_KBLIGHT
+/* Free up more flash. */
+#undef CONFIG_CMD_GETTIME
+#undef CONFIG_CMD_HCDEBUG
+#undef CONFIG_CMD_I2C_SCAN
+#undef CONFIG_CMD_I2C_XFER
+#undef CONFIG_CONSOLE_VERBOSE
+#undef CONFIG_CONSOLE_CMDHELP
+#undef CONFIG_CONSOLE_HISTORY
+#define CONFIG_USB_PD_DEBUG_LEVEL 0
 
 #ifndef __ASSEMBLER__
 
 /* support factory keyboard test */
 #define CONFIG_KEYBOARD_FACTORY_TEST
-extern const int keyboard_factory_scan_pins[][2];
-extern const int keyboard_factory_scan_pins_used;
 
 #include "gpio_signal.h"
 #include "registers.h"
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_AMB,		/* ADC0 */
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC1 */
-	ADC_VBUS_C0,			/* ADC9 */
-	ADC_VBUS_C1,			/* ADC4 */
+	ADC_TEMP_SENSOR_AMB, /* ADC0 */
+	ADC_TEMP_SENSOR_CHARGER, /* ADC1 */
+	ADC_VBUS_C0, /* ADC9 */
+	ADC_VBUS_C1, /* ADC4 */
 	ADC_CH_COUNT
 };
 
@@ -81,27 +94,20 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
-
 /* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	VSYNC,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, VSYNC, SENSOR_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
 	BATTERY_SIMPLO_SDI,
 	BATTERY_SIMPLO_BYD,
+	BATTERY_SIMPLO_CA475778G,
+	BATTERY_SIMPLO_CA475778G_R,
 	BATTERY_TYPE_COUNT,
 };
 
+void sensor_interrupt(enum gpio_signal signal);
+
 #endif /* !__ASSEMBLER__ */
 
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/garg/build.mk b/board/garg/build.mk
index 137e208b53..fee77e38b5 100644
--- a/board/garg/build.mk
+++ b/board/garg/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/garg/ec.tasklist b/board/garg/ec.tasklist
index 6eac78a042..6c56976091 100644
--- a/board/garg/ec.tasklist
+++ b/board/garg/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/garg/gpio.inc b/board/garg/gpio.inc
index 2c485e4e2c..57feead408 100644
--- a/board/garg/gpio.inc
+++ b/board/garg/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -37,7 +37,7 @@ GPIO_INT(TABLET_MODE_L,         PIN(8, 6), GPIO_INT_BOTH, gmr_tablet_switch_isr)
 GPIO_INT(EC_VOLUP_BTN_ODL,	PIN(7, 5), GPIO_INT_BOTH, button_interrupt)
 GPIO_INT(EC_VOLDN_BTN_ODL,	PIN(4, 0), GPIO_INT_BOTH, button_interrupt)
 
-GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, bmi160_interrupt)
+GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, sensor_interrupt)
 
 GPIO(LID_ACCEL_INT_L,		PIN(5, 0), GPIO_INPUT | GPIO_SEL_1P8V)
 
@@ -136,9 +136,6 @@ GPIO(BAT_LED_ORANGE_L,	 PIN(C, 3), GPIO_OUT_HIGH)	/* LED_1_L */
 GPIO(BAT_LED_BLUE_L,	 PIN(C, 4), GPIO_OUT_HIGH)	/* LED_2_L */
 GPIO(LED_3_L,		 PIN(D, 7), GPIO_OUT_HIGH)
 
-/* Keyboard Backlight */
-GPIO(KB_BL_PWR_EN,	PIN(6, 2), GPIO_OUT_LOW)
-
 /* MKBP event synchronization */
 GPIO(EC_INT_L,		PIN(9, 4), GPIO_ODR_HIGH)
 
@@ -158,6 +155,8 @@ GPIO(EC_I2S_SFRM,	PIN(A, 5), GPIO_INPUT | GPIO_SEL_1P8V)
 GPIO(EC_I2S_SCLK,	PIN(A, 7), GPIO_INPUT | GPIO_SEL_1P8V)
 GPIO(EC_I2S_TX_PCH_RX,	PIN(B, 0), GPIO_INPUT | GPIO_SEL_1P8V)
 GPIO(WFCAM_VSYNC,	PIN(0, 3), GPIO_INPUT)
+GPIO(KB_BL_PWR_EN,	PIN(6, 2), GPIO_INPUT)
+GPIO(EC_GPIO80,		PIN(8, 0), GPIO_INPUT)
 
 /* Keyboard pins */
 ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)	/* KSI_00-01 */
@@ -181,7 +180,6 @@ ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V)) /* 1.8
 ALTERNATE(PIN_MASK(4, 0x30), 0, MODULE_ADC, 0)		/* ADC0-1 */
 ALTERNATE(PIN_MASK(4, 0x02), 0, MODULE_ADC, 0)		/* ADC4 */
 ALTERNATE(PIN_MASK(F, 0x01), 0, MODULE_ADC, 0)		/* ADC9 */
-ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)		/* PWM3: KB_BL_PWM */
 
 /* Power Switch Logic (PSL) inputs */
 ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, 0)		/* GPIOD2 = LID_OPEN */
diff --git a/board/garg/led.c b/board/garg/led.c
index f533ed32b6..eff8c1307b 100644
--- a/board/garg/led.c
+++ b/board/garg/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,32 +10,39 @@
 #include "led_common.h"
 #include "led_onoff_states.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
-const int led_charge_lvl_1;
+__override const int led_charge_lvl_1;
 
-const int led_charge_lvl_2 = 100;
+__override const int led_charge_lvl_2 = 100;
 
 /* Garg: Note there is only LED for charge / power */
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,  2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
 const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-void led_set_color_battery(enum ec_led_colors color)
+__override void led_set_color_battery(enum ec_led_colors color)
 {
 	switch (color) {
 	case EC_LED_COLOR_BLUE:
@@ -70,4 +77,3 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 
 	return EC_SUCCESS;
 }
-
diff --git a/board/garg/vif_override.xml b/board/garg/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/garg/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/gelarshie/base_detect.c b/board/gelarshie/base_detect.c
new file mode 100644
index 0000000000..9c1a47d2e4
--- /dev/null
+++ b/board/gelarshie/base_detect.c
@@ -0,0 +1,230 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Gelarshie base detection code */
+
+#include "adc.h"
+#include "base_state.h"
+#include "board.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "timer.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+
+/* Base detection and debouncing */
+#define BASE_DETECT_EN_DEBOUNCE_US (350 * MSEC)
+#define BASE_DETECT_DIS_DEBOUNCE_US (20 * MSEC)
+
+/*
+ * If the base status is unclear (i.e. not within expected ranges, read
+ * the ADC value again every 500ms.
+ */
+#define BASE_DETECT_RETRY_US (500 * MSEC)
+
+/*
+ * Lid has 604K pull-up, base has 30.1K pull-down, so the
+ * ADC value should be around 30.1/(604+30.1)*3300 = 156
+ *
+ * We add a significant margin on the maximum value, due to noise on the line,
+ * especially when PWM is active. See b/64193554 for details.
+ */
+#define BASE_DETECT_MIN_MV 120
+#define BASE_DETECT_MAX_MV 300
+
+/* Minimum ADC value to indicate base is disconnected for sure */
+#define BASE_DETECT_DISCONNECT_MIN_MV 1500
+
+/*
+ * Base EC pulses detection pin for 500 us to signal out of band USB wake (that
+ * can be used to wake system from deep S3).
+ */
+#define BASE_DETECT_PULSE_MIN_US 400
+#define BASE_DETECT_PULSE_MAX_US 650
+
+static uint64_t base_detect_debounce_time;
+
+static void base_detect_deferred(void);
+DECLARE_DEFERRED(base_detect_deferred);
+
+enum base_status {
+	BASE_UNKNOWN = 0,
+	BASE_DISCONNECTED = 1,
+	BASE_CONNECTED = 2,
+};
+
+static enum base_status current_base_status;
+
+/*
+ * This function is called whenever there is a change in the base detect
+ * status. Actions taken include:
+ * 1. Change in power to base
+ * 2. Indicate mode change to host.
+ * 3. Indicate tablet mode to host. Current assumption is that if base is
+ * disconnected then the system is in tablet mode, else if the base is
+ * connected, then the system is not in tablet mode.
+ */
+static void base_detect_change(enum base_status status)
+{
+	int connected = (status == BASE_CONNECTED);
+
+	if (current_base_status == status)
+		return;
+
+	gpio_set_level(GPIO_EN_BASE, connected);
+	tablet_set_mode(!connected, TABLET_TRIGGER_BASE);
+	base_set_state(connected);
+	current_base_status = status;
+}
+
+/* Measure detection pin pulse duration (used to wake AP from deep S3). */
+static uint64_t pulse_start;
+static uint32_t pulse_width;
+
+static void print_base_detect_value(int v, int tmp_pulse_width)
+{
+	CPRINTS("%s = %d (pulse %d)", adc_channels[ADC_BASE_DET].name, v,
+		tmp_pulse_width);
+}
+
+static void base_detect_deferred(void)
+{
+	uint64_t time_now = get_time().val;
+	int v;
+	uint32_t tmp_pulse_width = pulse_width;
+
+	if (base_detect_debounce_time > time_now) {
+		hook_call_deferred(&base_detect_deferred_data,
+				   base_detect_debounce_time - time_now);
+		return;
+	}
+
+	v = adc_read_channel(ADC_BASE_DET);
+	if (v == ADC_READ_ERROR)
+		return;
+
+	print_base_detect_value(v, tmp_pulse_width);
+
+	if (v >= BASE_DETECT_MIN_MV && v <= BASE_DETECT_MAX_MV) {
+		if (current_base_status != BASE_CONNECTED) {
+			base_detect_change(BASE_CONNECTED);
+		} else if (tmp_pulse_width >= BASE_DETECT_PULSE_MIN_US &&
+			   tmp_pulse_width <= BASE_DETECT_PULSE_MAX_US) {
+			CPRINTS("Sending event to AP");
+			host_set_single_event(EC_HOST_EVENT_KEY_PRESSED);
+		}
+		return;
+	}
+
+	if (v >= BASE_DETECT_DISCONNECT_MIN_MV) {
+		base_detect_change(BASE_DISCONNECTED);
+		return;
+	}
+
+	/* Unclear base status, schedule again in a while. */
+	hook_call_deferred(&base_detect_deferred_data, BASE_DETECT_RETRY_US);
+}
+
+static inline int detect_pin_connected(enum gpio_signal det_pin)
+{
+	return gpio_get_level(det_pin) == 0;
+}
+
+void base_detect_interrupt(enum gpio_signal signal)
+{
+	uint64_t time_now = get_time().val;
+	int debounce_us;
+
+	if (detect_pin_connected(signal))
+		debounce_us = BASE_DETECT_EN_DEBOUNCE_US;
+	else
+		debounce_us = BASE_DETECT_DIS_DEBOUNCE_US;
+
+	if (base_detect_debounce_time <= time_now) {
+		/*
+		 * Detect and measure detection pin pulse, when base is
+		 * connected. Only a single pulse is measured over a debounce
+		 * period. If no pulse, or multiple pulses are detected,
+		 * pulse_width is set to 0.
+		 */
+		if (current_base_status == BASE_CONNECTED &&
+		    !detect_pin_connected(signal)) {
+			pulse_start = time_now;
+		} else {
+			pulse_start = 0;
+		}
+		pulse_width = 0;
+
+		hook_call_deferred(&base_detect_deferred_data, debounce_us);
+	} else {
+		if (current_base_status == BASE_CONNECTED &&
+		    detect_pin_connected(signal) && !pulse_width &&
+		    pulse_start) {
+			/* First pulse within period. */
+			pulse_width = time_now - pulse_start;
+		} else {
+			pulse_start = 0;
+			pulse_width = 0;
+		}
+	}
+
+	base_detect_debounce_time = time_now + debounce_us;
+}
+
+static void base_enable(void)
+{
+	/* Enable base detection interrupt. */
+	base_detect_debounce_time = get_time().val;
+	hook_call_deferred(&base_detect_deferred_data, 0);
+	gpio_enable_interrupt(GPIO_BASE_DET_L);
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, base_enable, HOOK_PRIO_DEFAULT);
+
+static void base_disable(void)
+{
+	/*
+	 * Disable base detection interrupt and disable power to base.
+	 * Set the state UNKNOWN so the next startup will initialize a
+	 * correct state and notify AP.
+	 */
+	gpio_disable_interrupt(GPIO_BASE_DET_L);
+	base_detect_change(BASE_UNKNOWN);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, base_disable, HOOK_PRIO_DEFAULT);
+
+static void base_init(void)
+{
+	/*
+	 * If we jumped to this image and chipset is already in S0, enable
+	 * base.
+	 */
+	if (system_jumped_late() && chipset_in_state(CHIPSET_STATE_ON))
+		base_enable();
+}
+DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT + 1);
+
+void base_force_state(enum ec_set_base_state_cmd state)
+{
+	if (state == EC_SET_BASE_STATE_ATTACH) {
+		gpio_disable_interrupt(GPIO_BASE_DET_L);
+		base_detect_change(BASE_CONNECTED);
+		CPRINTS("BD forced connected");
+	} else if (state == EC_SET_BASE_STATE_DETACH) {
+		gpio_disable_interrupt(GPIO_BASE_DET_L);
+		base_detect_change(BASE_DISCONNECTED);
+		CPRINTS("BD forced disconnected");
+	} else {
+		base_enable();
+		CPRINTS("BD forced reset");
+	}
+}
diff --git a/board/gelarshie/battery.c b/board/gelarshie/battery.c
new file mode 100644
index 0000000000..da96b773f8
--- /dev/null
+++ b/board/gelarshie/battery.c
@@ -0,0 +1,159 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "common.h"
+#include "util.h"
+
+/*
+ * Battery info for all gelarshie battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+
+const struct board_batt_params board_battery_info[] = {
+	/* COSMX GH02047XL 333-1C-DA-A */
+	[BATTERY_GH02047XL_1C] = {
+		.fuel_gauge = {
+			.manuf_name = "333-1C-DA-A",
+			.device_name = "GH02047XL",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0002,
+				.disconnect_val = 0x0,
+			}
+		},
+		.batt_info = {
+			.voltage_max            = 8800, /* mV */
+			.voltage_normal         = 7700, /* mV */
+			.voltage_min            = 6000, /* mV */
+			.precharge_current      = 256,  /* mA */
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 45,
+			.charging_min_c         = 0,
+			.charging_max_c         = 45,
+			.discharging_min_c      = -10,
+			.discharging_max_c      = 60,
+			.vendor_param_start     = 0x70,
+		},
+	},
+	/* COSMX GH02047XL */
+	[BATTERY_GH02047XL] = {
+		.fuel_gauge = {
+			.manuf_name = "333-AC-DA-A",
+			.device_name = "GH02047XL",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0002,
+				.disconnect_val = 0x0,
+			}
+		},
+		.batt_info = {
+			.voltage_max            = 8800, /* mV */
+			.voltage_normal         = 7700, /* mV */
+			.voltage_min            = 6000, /* mV */
+			.precharge_current      = 256,  /* mA */
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 45,
+			.charging_min_c         = 0,
+			.charging_max_c         = 45,
+			.discharging_min_c      = -10,
+			.discharging_max_c      = 60,
+			.vendor_param_start     = 0x70,
+		},
+	},
+	/* COSMX DS02032XL */
+	[BATTERY_DS02032XL] = {
+		.fuel_gauge = {
+			.manuf_name = "333-AC-13-A",
+			.device_name = "DS02032XL",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0002,
+				.disconnect_val = 0x0,
+			}
+		},
+		.batt_info = {
+			.voltage_max            = 8800, /* mV */
+			.voltage_normal         = 7700, /* mV */
+			.voltage_min            = 6000, /* mV */
+			.precharge_current      = 256,  /* mA */
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 45,
+			.charging_min_c         = 0,
+			.charging_max_c         = 45,
+			.discharging_min_c      = -10,
+			.discharging_max_c      = 60,
+			.vendor_param_start     = 0x70,
+		},
+	},
+	/* SMP DS02032XL */
+	[BATTERY_DS02032XL_1C] = {
+		.fuel_gauge = {
+			.manuf_name = "333-1C-13-A",
+			.device_name = "DS02032XL",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0002,
+				.disconnect_val = 0x0,
+			}
+		},
+		.batt_info = {
+			.voltage_max            = 8800, /* mV */
+			.voltage_normal         = 7700, /* mV */
+			.voltage_min            = 6000, /* mV */
+			.precharge_current      = 256,  /* mA */
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 45,
+			.charging_min_c         = 0,
+			.charging_max_c         = 45,
+			.discharging_min_c      = -10,
+			.discharging_max_c      = 60,
+			.vendor_param_start     = 0x70,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_DS02032XL;
diff --git a/board/gelarshie/board.c b/board/gelarshie/board.c
new file mode 100644
index 0000000000..2899fa9566
--- /dev/null
+++ b/board/gelarshie/board.c
@@ -0,0 +1,715 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Gelarshie board-specific configuration */
+
+#include "adc_chip.h"
+#include "button.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "common.h"
+#include "driver/accel_bma2x2.h"
+#include "driver/accelgyro_bmi260.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "driver/ln9310.h"
+#include "driver/ppc/sn5s330.h"
+#include "driver/tcpm/ps8xxx.h"
+#include "driver/tcpm/tcpci.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "lid_switch.h"
+#include "mkbp_input_devices.h"
+#include "peripheral_charger.h"
+#include "pi3usb9201.h"
+#include "power.h"
+#include "power/qcom.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "queue.h"
+#include "shi_chip.h"
+#include "switch.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "usbc_ppc.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+#define KS_DEBOUNCE_US (30 * MSEC) /* Debounce time for kickstand switch */
+
+/* Forward declaration */
+static void tcpc_alert_event(enum gpio_signal signal);
+static void usb0_evt(enum gpio_signal signal);
+static void usb1_evt(enum gpio_signal signal);
+static void ppc_interrupt(enum gpio_signal signal);
+static void board_connect_c0_sbu(enum gpio_signal s);
+static void ks_interrupt(enum gpio_signal s);
+static void switchcap_interrupt(enum gpio_signal signal);
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* GPIO Interrupt Handlers */
+static void tcpc_alert_event(enum gpio_signal signal)
+{
+	int port = -1;
+
+	switch (signal) {
+	case GPIO_USB_C0_PD_INT_ODL:
+		port = 0;
+		break;
+	case GPIO_USB_C1_PD_INT_ODL:
+		port = 1;
+		break;
+	default:
+		return;
+	}
+
+	schedule_deferred_pd_interrupt(port);
+}
+
+static void usb0_evt(enum gpio_signal signal)
+{
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+
+static void usb1_evt(enum gpio_signal signal)
+{
+	usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+}
+
+static void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_SWCTL_INT_ODL:
+		sn5s330_interrupt(0);
+		break;
+	case GPIO_USB_C1_SWCTL_INT_ODL:
+		sn5s330_interrupt(1);
+		break;
+	default:
+		break;
+	}
+}
+
+static void board_connect_c0_sbu_deferred(void)
+{
+	/*
+	 * If CCD_MODE_ODL asserts, it means there's a debug accessory connected
+	 * and we should enable the SBU FETs.
+	 */
+	ppc_set_sbu(0, 1);
+}
+DECLARE_DEFERRED(board_connect_c0_sbu_deferred);
+
+static void board_connect_c0_sbu(enum gpio_signal s)
+{
+	hook_call_deferred(&board_connect_c0_sbu_deferred_data, 0);
+}
+
+static int debounced_ks_attached;
+static int debounced_ks_open;
+
+/**
+ * Kickstand switch initialization
+ */
+static void ks_init(void)
+{
+	debounced_ks_attached = !gpio_get_level(GPIO_KS_ATTACHED_L);
+	debounced_ks_open = gpio_get_level(GPIO_KS_OPEN);
+
+	/* Enable interrupts, now that we've initialized */
+	gpio_enable_interrupt(GPIO_KS_ATTACHED_L);
+	gpio_enable_interrupt(GPIO_KS_OPEN);
+}
+DECLARE_HOOK(HOOK_INIT, ks_init, HOOK_PRIO_INIT_SWITCH);
+
+/**
+ * Handle debounced kickstand switch changing state.
+ */
+static void ks_change_deferred(void)
+{
+	const int ks_attached = !gpio_get_level(GPIO_KS_ATTACHED_L);
+	const int ks_open = gpio_get_level(GPIO_KS_OPEN);
+	int proximity_detected;
+
+	/* If the switches haven't changed, nothing to do */
+	if (ks_attached == debounced_ks_attached &&
+	    ks_open == debounced_ks_open)
+		return;
+
+	/*
+	 * A heuristic method to use the kickstand position to approach
+	 * the human body proximity.
+	 */
+	proximity_detected = !(ks_attached && ks_open);
+	CPRINTS("ks %s %s -> proximity %s",
+		ks_attached ? "attached" : "detached",
+		ks_open ? "open" : "close", proximity_detected ? "on" : "off");
+
+	debounced_ks_attached = ks_attached;
+	debounced_ks_open = ks_open;
+
+	body_detect_change_state(proximity_detected, false);
+}
+DECLARE_DEFERRED(ks_change_deferred);
+
+static void ks_interrupt(enum gpio_signal s)
+{
+	/* Reset kickstand debounce time */
+	hook_call_deferred(&ks_change_deferred_data, KS_DEBOUNCE_US);
+}
+
+static void switchcap_interrupt(enum gpio_signal signal)
+{
+	ln9310_interrupt(signal);
+}
+
+/* I2C port map */
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_POWER_SCL,
+	  .sda = GPIO_EC_I2C_POWER_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C0_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C0_PD_SDA },
+	{ .name = "tcpc1",
+	  .port = I2C_PORT_TCPC1,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C1_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C1_PD_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_EEPROM_SCL,
+	  .sda = GPIO_EC_I2C_EEPROM_SDA },
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_SENSOR_SCL,
+	  .sda = GPIO_EC_I2C_SENSOR_SDA },
+};
+
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	/* Measure VBUS through a 1/10 voltage divider */
+	[ADC_VBUS] = { "VBUS", NPCX_ADC_CH1, ADC_MAX_VOLT * 10,
+		       ADC_READ_MAX + 1, 0 },
+	/*
+	 * Adapter current output or battery charging/discharging current (uV)
+	 * 18x amplification on charger side.
+	 */
+	[ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH2, ADC_MAX_VOLT * 1000 / 18,
+			    ADC_READ_MAX + 1, 0 },
+	/*
+	 * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read
+	 * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and
+	 * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we
+	 * only divide by 2 (enough to avoid precision issues).
+	 */
+	[ADC_PSYS] = { "PSYS", NPCX_ADC_CH3,
+		       ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), 2, 0 },
+	/* Base detection */
+	[ADC_BASE_DET] = { "BASE_DET", NPCX_ADC_CH5, ADC_MAX_VOLT,
+			   ADC_READ_MAX + 1, 0 },
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+const struct pwm_t pwm_channels[] = {
+	/* TODO(waihong): Assign a proper frequency. */
+	[PWM_CH_DISPLIGHT] = { .channel = 5, .flags = 0, .freq = 4800 },
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+/* LN9310 switchcap */
+const struct ln9310_config_t ln9310_config = {
+	.i2c_port = I2C_PORT_POWER,
+	.i2c_addr_flags = LN9310_I2C_ADDR_0_FLAGS,
+};
+
+/* Power Path Controller */
+struct ppc_config_t ppc_chips[] = {
+	{ .i2c_port = I2C_PORT_TCPC0,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
+	{ .i2c_port = I2C_PORT_TCPC1,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
+};
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/* TCPC mux configuration */
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TCPC0,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+	},
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TCPC1,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+	},
+};
+
+/*
+ * Port-0/1 USB mux driver.
+ *
+ * The USB mux is handled by TCPC chip and the HPD update is through a GPIO
+ * to AP. But the TCPC chip is also needed to know the HPD status; otherwise,
+ * the mux misbehaves.
+ */
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
+	},
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
+	}
+};
+
+/* BC1.2 */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	{
+		.i2c_port = I2C_PORT_TCPC0,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+	{
+		.i2c_port = I2C_PORT_TCPC1,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+};
+
+/* Mutexes */
+static struct mutex g_lid_mutex;
+
+static struct bmi_drv_data_t g_bmi160_data;
+static struct bmi_drv_data_t g_bmi260_data;
+
+bool is_bmi260_present;
+
+/* Matrix to rotate accelerometer into standard reference frame */
+const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+				      { FLOAT_TO_FP(1), 0, 0 },
+				      { 0, 0, FLOAT_TO_FP(1) } };
+
+struct motion_sensor_t motion_sensors[] = {
+	/*
+	 * Note: bmi160: supports accelerometer and gyro sensor
+	 * Requirement: accelerometer sensor must init before gyro sensor
+	 * DO NOT change the order of the following table.
+	 */
+	[LID_ACCEL] = {
+	 .name = "Lid Accel",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_BMI160,
+	 .type = MOTIONSENSE_TYPE_ACCEL,
+	 .location = MOTIONSENSE_LOC_LID,
+	 .drv = &bmi160_drv,
+	 .mutex = &g_lid_mutex,
+	 .drv_data = &g_bmi160_data,
+	 .port = I2C_PORT_SENSOR,
+	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+	 .rot_standard_ref = &lid_standard_ref,
+	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
+	 .min_frequency = BMI_ACCEL_MIN_FREQ,
+	 .max_frequency = BMI_ACCEL_MAX_FREQ,
+	 .config = {
+		 [SENSOR_CONFIG_EC_S0] = {
+			 .odr = 10000 | ROUND_UP_FLAG,
+		 },
+	 },
+	},
+	[LID_GYRO] = {
+	 .name = "Gyro",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_BMI160,
+	 .type = MOTIONSENSE_TYPE_GYRO,
+	 .location = MOTIONSENSE_LOC_LID,
+	 .drv = &bmi160_drv,
+	 .mutex = &g_lid_mutex,
+	 .drv_data = &g_bmi160_data,
+	 .port = I2C_PORT_SENSOR,
+	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+	 .default_range = 1000, /* dps */
+	 .rot_standard_ref = &lid_standard_ref,
+	 .min_frequency = BMI_GYRO_MIN_FREQ,
+	 .max_frequency = BMI_GYRO_MAX_FREQ,
+	},
+};
+
+struct motion_sensor_t motion_sensors_260[] = {
+	/*
+	 * Note: bmi260: supports accelerometer and gyro sensor
+	 * Requirement: accelerometer sensor must init before gyro sensor
+	 * DO NOT change the order of the following table.
+	 */
+	[LID_ACCEL] = {
+	 .name = "Lid Accel",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_BMI260,
+	 .type = MOTIONSENSE_TYPE_ACCEL,
+	 .location = MOTIONSENSE_LOC_LID,
+	 .drv = &bmi260_drv,
+	 .mutex = &g_lid_mutex,
+	 .drv_data = &g_bmi260_data,
+	 .port = I2C_PORT_SENSOR,
+	 .i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
+	 .rot_standard_ref = &lid_standard_ref,
+	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
+	 .min_frequency = BMI_ACCEL_MIN_FREQ,
+	 .max_frequency = BMI_ACCEL_MAX_FREQ,
+	 .config = {
+		 [SENSOR_CONFIG_EC_S0] = {
+			 .odr = 10000 | ROUND_UP_FLAG,
+		 },
+	 },
+	},
+	[LID_GYRO] = {
+	 .name = "Gyro",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_BMI260,
+	 .type = MOTIONSENSE_TYPE_GYRO,
+	 .location = MOTIONSENSE_LOC_LID,
+	 .drv = &bmi260_drv,
+	 .mutex = &g_lid_mutex,
+	 .drv_data = &g_bmi260_data,
+	 .port = I2C_PORT_SENSOR,
+	 .i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
+	 .default_range = 1000, /* dps */
+	 .rot_standard_ref = &lid_standard_ref,
+	 .min_frequency = BMI_GYRO_MIN_FREQ,
+	 .max_frequency = BMI_GYRO_MAX_FREQ,
+	},
+};
+
+const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+static void board_detect_motionsensor(void)
+{
+	int val = -1;
+
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return;
+
+	/* Check base accelgyro chip */
+	bmi_read8(motion_sensors[LID_ACCEL].port,
+		  motion_sensors[LID_ACCEL].i2c_spi_addr_flags, BMI260_CHIP_ID,
+		  &val);
+	if (val == BMI260_CHIP_ID_MAJOR) {
+		motion_sensors[LID_ACCEL] = motion_sensors_260[LID_ACCEL];
+		motion_sensors[LID_GYRO] = motion_sensors_260[LID_GYRO];
+		is_bmi260_present = 1;
+	} else {
+		is_bmi260_present = 0;
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_detect_motionsensor,
+	     HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_INIT, board_detect_motionsensor, HOOK_PRIO_DEFAULT + 1);
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	if (is_bmi260_present) {
+		bmi260_interrupt(signal);
+	} else {
+		bmi160_interrupt(signal);
+	}
+}
+
+enum battery_cell_type board_get_battery_cell_type(void)
+{
+	return BATTERY_CELL_TYPE_2S;
+}
+
+static void board_switchcap_init(void)
+{
+	CPRINTS("Use switchcap: LN9310");
+
+	/* Configure and enable interrupt for LN9310 */
+	gpio_set_flags(GPIO_SWITCHCAP_PG_INT_L, GPIO_INT_FALLING);
+	gpio_enable_interrupt(GPIO_SWITCHCAP_PG_INT_L);
+
+	/* Only configure the switchcap if not sysjump */
+	if (!system_jumped_late()) {
+		ln9310_init();
+	}
+}
+/* Initialize board. */
+static void board_init(void)
+{
+	/*
+	 * The rev-1 hardware doesn't have the external pull-up fix for the bug
+	 * b/177611071. It requires rework to stuff the resistor. For people who
+	 * has difficulty to do the rework, this is a workaround, which makes
+	 * the GPIO push-pull, instead of open-drain.
+	 */
+	if (system_get_board_version() == 1)
+		gpio_set_flags(GPIO_HIBERNATE_L, GPIO_OUTPUT);
+
+	/* Enable BC1.2 interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_L);
+	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L);
+	gpio_enable_interrupt(GPIO_ACCEL_GYRO_INT_L);
+
+	/*
+	 * The H1 SBU line for CCD are behind PPC chip. The PPC internal FETs
+	 * for SBU may be disconnected after DP alt mode is off. Should enable
+	 * the CCD_MODE_ODL interrupt to make sure the SBU FETs are connected.
+	 */
+	gpio_enable_interrupt(GPIO_CCD_MODE_ODL);
+
+	/* Set the backlight duty cycle to 0. AP will override it later. */
+	pwm_set_duty(PWM_CH_DISPLIGHT, 0);
+
+	board_switchcap_init();
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+__overridable uint16_t board_get_ps8xxx_product_id(int port)
+{
+	/* Coachz board rev 2+ changes TCPC from 8805 to 8755*/
+	if (system_get_board_version() < 2)
+		return PS8805_PRODUCT_ID;
+
+	return PS8755_PRODUCT_ID;
+}
+
+void board_tcpc_init(void)
+{
+	/* Only reset TCPC if not sysjump */
+	if (!system_jumped_late()) {
+		/* TODO(crosbug.com/p/61098): How long do we need to wait? */
+		board_reset_pd_mcu();
+	}
+
+	/* Enable PPC interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_SWCTL_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_SWCTL_INT_ODL);
+
+	/* Enable TCPC interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL);
+
+	/*
+	 * Initialize HPD to low; after sysjump SOC needs to see
+	 * HPD pulse to enable video path
+	 */
+	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
+		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
+
+void board_hibernate(void)
+{
+	int i;
+
+	/*
+	 * Sensors are unpowered in hibernate. Apply PD to the
+	 * interrupt lines such that they don't float.
+	 */
+	gpio_set_flags(GPIO_ACCEL_GYRO_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
+
+	/*
+	 * Board rev 1+ has the hardware fix. Don't need the following
+	 * workaround.
+	 */
+	if (system_get_board_version() >= 1)
+		return;
+
+	/*
+	 * Enable the PPC power sink path before EC enters hibernate;
+	 * otherwise, ACOK won't go High and can't wake EC up. Check the
+	 * bug b/170324206 for details.
+	 */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
+		ppc_vbus_sink_enable(i, 1);
+}
+
+/* Called on AP S0 -> S3 transition */
+static void board_chipset_suspend(void)
+{
+	/*
+	 * Turn off display backlight in S3. AP has its own control. The EC's
+	 * and the AP's will be AND'ed together in hardware.
+	 */
+	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 0);
+	pwm_enable(PWM_CH_DISPLIGHT, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S3 -> S0 transition */
+static void board_chipset_resume(void)
+{
+	/* Turn on display and keyboard backlight in S0. */
+	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 1);
+	if (pwm_get_duty(PWM_CH_DISPLIGHT))
+		pwm_enable(PWM_CH_DISPLIGHT, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
+
+void board_set_switchcap_power(int enable)
+{
+	gpio_set_level(GPIO_SWITCHCAP_ON_L, !enable);
+	ln9310_software_enable(enable);
+}
+
+int board_is_switchcap_enabled(void)
+{
+	return !gpio_get_level(GPIO_SWITCHCAP_ON_L);
+}
+
+int board_is_switchcap_power_good(void)
+{
+	return ln9310_power_good();
+}
+
+void board_reset_pd_mcu(void)
+{
+	cprints(CC_USB, "Resetting TCPCs...");
+	cflush();
+
+	gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
+	gpio_set_level(GPIO_USB_C1_PD_RST_L, 0);
+	msleep(PS8XXX_RESET_DELAY_MS);
+	gpio_set_level(GPIO_USB_C0_PD_RST_L, 1);
+	gpio_set_level(GPIO_USB_C1_PD_RST_L, 1);
+}
+
+void board_set_tcpc_power_mode(int port, int mode)
+{
+	/* Ignore the "mode" to turn the chip on.  We can only do a reset. */
+	if (mode)
+		return;
+
+	board_reset_pd_mcu();
+}
+
+int board_vbus_sink_enable(int port, int enable)
+{
+	/* Both ports are controlled by PPC SN5S330 */
+	return ppc_vbus_sink_enable(port, enable);
+}
+
+int board_is_sourcing_vbus(int port)
+{
+	/* Both ports are controlled by PPC SN5S330 */
+	return ppc_is_sourcing_vbus(port);
+}
+
+void board_overcurrent_event(int port, int is_overcurrented)
+{
+	/* TODO(b/120231371): Notify AP */
+	CPRINTS("p%d: overcurrent!", port);
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int i;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTS("Disabling all charging port");
+
+		/* Disable all ports. */
+		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (board_vbus_sink_enable(i, 0))
+				CPRINTS("Disabling p%d sink path failed.", i);
+		}
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (board_is_sourcing_vbus(port)) {
+		CPRINTS("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTS("New charge port: p%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		if (i == port)
+			continue;
+
+		if (board_vbus_sink_enable(i, 0))
+			CPRINTS("p%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (board_vbus_sink_enable(port, 1)) {
+		CPRINTS("p%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
+{
+	/*
+	 * Ignore lower charge ceiling on PD transition if our battery is
+	 * critical, as we may brownout.
+	 */
+	if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 &&
+	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
+		CPRINTS("Using max ilim %d", max_ma);
+		charge_ma = max_ma;
+	}
+
+	charge_set_input_current_limit(charge_ma, charge_mv);
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
+		if (gpio_get_level(GPIO_USB_C0_PD_RST_L))
+			status |= PD_STATUS_TCPC_ALERT_0;
+	if (!gpio_get_level(GPIO_USB_C1_PD_INT_ODL))
+		if (gpio_get_level(GPIO_USB_C1_PD_RST_L))
+			status |= PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
diff --git a/board/gelarshie/board.h b/board/gelarshie/board.h
new file mode 100644
index 0000000000..65016ceb75
--- /dev/null
+++ b/board/gelarshie/board.h
@@ -0,0 +1,132 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Gelarshie board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "baseboard.h"
+
+/* On-body detection */
+#define CONFIG_BODY_DETECTION
+#define CONFIG_BODY_DETECTION_SENSOR LID_ACCEL
+#define CONFIG_BODY_DETECTION_VAR_NOISE_FACTOR 150 /* % */
+#define CONFIG_GESTURE_DETECTION
+#define CONFIG_GESTURE_DETECTION_MASK BIT(CONFIG_BODY_DETECTION_SENSOR)
+#define CONFIG_GESTURE_HOST_DETECTION
+
+#define CONFIG_BUTTON_TRIGGERED_RECOVERY
+
+/* Internal SPI flash on NPCX7 */
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */
+
+/* Switchcap */
+#define CONFIG_LN9310
+
+/* Save some flash space */
+#define CONFIG_LTO
+#define CONFIG_USB_PD_DEBUG_LEVEL 2
+#undef CONFIG_CMD_FLASHINFO
+#undef CONFIG_CMD_MMAPINFO
+#undef CONFIG_CMD_ACCELSPOOF
+#undef CONFIG_CMD_ACCEL_FIFO
+#undef CONFIG_CMD_ACCEL_INFO
+#undef CONFIG_CMD_TASK_RESET
+#undef CONFIG_CONSOLE_CMDHELP
+
+/* Battery */
+#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
+#define CONFIG_BATTERY_REVIVE_DISCONNECT
+#define CONFIG_BATTERY_FUEL_GAUGE
+#define CONFIG_BATTERY_VENDOR_PARAM
+
+/* charger margin */
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 5
+
+/* Enable PD3.0 */
+#define CONFIG_USB_PD_REV30
+/* BC 1.2 Charger */
+#define CONFIG_BC12_DETECT_PI3USB9201
+
+/* USB */
+#define CONFIG_USB_PD_TCPM_MULTI_PS8XXX
+#define CONFIG_USB_PD_TCPM_PS8755
+#define CONFIG_USB_PD_TCPM_PS8805
+#define CONFIG_USB_PD_TCPM_PS8805_FORCE_DID
+#define CONFIG_USBC_PPC_SN5S330
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+
+/* BMI160 Lid accel/gyro */
+#define CONFIG_ACCELGYRO_BMI160
+#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
+#define OPT3001_I2C_ADDR_FLAGS OPT3001_I2C_ADDR1_FLAGS
+#define CONFIG_ACCELGYRO_BMI260
+#define CONFIG_ACCELGYRO_BMI260_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
+
+#define CONFIG_TABLET_MODE
+#define CONFIG_TABLET_MODE_SWITCH
+#define CONFIG_GMR_TABLET_MODE
+#define CONFIG_FRONT_PROXIMITY_SWITCH
+
+#define CONFIG_MKBP_INPUT_DEVICES
+
+#define CONFIG_DETACHABLE_BASE
+#define CONFIG_BASE_ATTACHED_SWITCH
+
+/* GPIO alias */
+#define GPIO_AC_PRESENT GPIO_CHG_ACOK_OD
+#define GPIO_WP_L GPIO_EC_FLASH_WP_ODL
+#define GPIO_PMIC_RESIN_L GPIO_PM845_RESIN_L
+#define GPIO_TABLET_MODE_L GPIO_LID_360_L
+#define GPIO_KS_ATTACHED_L GPIO_LID_INT_N_HALL1
+#define GPIO_KS_OPEN GPIO_LID_INT_N_HALL2
+#define GPIO_SWITCHCAP_PG_INT_L GPIO_LN9310_INT
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum adc_channel {
+	ADC_VBUS,
+	ADC_AMON_BMON,
+	ADC_PSYS,
+	ADC_BASE_DET,
+	ADC_CH_COUNT
+};
+
+/* Motion sensors */
+enum sensor_id {
+	LID_ACCEL = 0,
+	LID_GYRO,
+	SENSOR_COUNT,
+};
+
+enum pwm_channel { PWM_CH_DISPLIGHT = 0, PWM_CH_COUNT };
+
+/* List of possible batteries */
+enum battery_type {
+	BATTERY_GH02047XL_1C,
+	BATTERY_GH02047XL,
+	BATTERY_DS02032XL,
+	BATTERY_DS02032XL_1C,
+	BATTERY_TYPE_COUNT,
+};
+
+/* Reset all TCPCs. */
+void board_reset_pd_mcu(void);
+void board_set_tcpc_power_mode(int port, int mode);
+/* Base detection */
+void base_detect_interrupt(enum gpio_signal signal);
+/* motion sensor interrupt */
+void motion_interrupt(enum gpio_signal signal);
+
+#endif /* !defined(__ASSEMBLER__) */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/gelarshie/build.mk b/board/gelarshie/build.mk
new file mode 100644
index 0000000000..5b0f734fda
--- /dev/null
+++ b/board/gelarshie/build.mk
@@ -0,0 +1,14 @@
+# -*- makefile -*-
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx7
+CHIP_VARIANT:=npcx7m6fc
+BASEBOARD:=trogdor
+
+board-y=battery.o board.o led.o base_detect.o usbc_config.o
diff --git a/board/gelarshie/ec.tasklist b/board/gelarshie/ec.tasklist
new file mode 100644
index 0000000000..7d193fecf3
--- /dev/null
+++ b/board/gelarshie/ec.tasklist
@@ -0,0 +1,22 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/gelarshie/gpio.inc b/board/gelarshie/gpio.inc
new file mode 100644
index 0000000000..189a9657a6
--- /dev/null
+++ b/board/gelarshie/gpio.inc
@@ -0,0 +1,192 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+/* USB-C interrupts */
+GPIO_INT(USB_C0_PD_INT_ODL,    PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-0 TCPC */
+GPIO_INT(USB_C1_PD_INT_ODL,    PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-1 TCPC */
+GPIO_INT(USB_C0_SWCTL_INT_ODL, PIN(0, 3), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-0 PPC */
+GPIO_INT(USB_C1_SWCTL_INT_ODL, PIN(4, 0), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-1 PPC */
+GPIO_INT(USB_C0_BC12_INT_L,    PIN(6, 1), GPIO_INT_FALLING | GPIO_PULL_UP, usb0_evt)  /* Interrupt from port-0 BC1.2 */
+GPIO_INT(USB_C1_BC12_INT_L,    PIN(8, 2), GPIO_INT_FALLING | GPIO_PULL_UP, usb1_evt)  /* Interrupt from port-1 BC1.2 */
+
+/* System interrupts */
+GPIO_INT(CHG_ACOK_OD,       PIN(0, 0), GPIO_INT_BOTH, extpower_interrupt)  /* ACOK */
+GPIO_INT(CCD_MODE_ODL,      PIN(E, 3), GPIO_INT_FALLING, board_connect_c0_sbu)  /* Case Closed Debug Mode */
+GPIO_INT(EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)  /* Power button */
+GPIO_INT(EC_VOLDN_BTN_ODL,  PIN(7, 0), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Down button */
+GPIO_INT(EC_VOLUP_BTN_ODL,  PIN(F, 2), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Up button */
+GPIO_INT(EC_FLASH_WP_ODL,   PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)  /* Write protection */
+GPIO_INT(LID_OPEN_EC,       PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)  /* Lid open */
+GPIO_INT(AP_RST_L,          PIN(C, 1), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_ap_rst_interrupt)  /* PMIC to signal AP reset */
+GPIO_INT(PS_HOLD,           PIN(A, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, power_signal_interrupt)  /* Indicate when AP triggers reset/shutdown */
+GPIO_INT(AP_SUSPEND,        PIN(5, 7), GPIO_INT_BOTH, power_signal_interrupt)  /* Suspend signal from PMIC */
+GPIO_INT(DEPRECATED_AP_RST_REQ, PIN(C, 2), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V, power_signal_interrupt) /* Deprecated AP initiated reset indicator */
+
+/*
+ * When switch-cap is off, the POWER_GOOD signal is floating. Need a pull-down
+ * to make it low. Overload the interrupt function chipset_warm_reset_interrupt
+ * for not only signalling power_signal_interrupt but also handling the logic
+ * of WARM_RESET_L which is pulled-up by the same rail of POWER_GOOD.
+ */
+GPIO_INT(POWER_GOOD,        PIN(5, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, chipset_power_good_interrupt)  /* SRC_PP1800_S10A from PMIC */
+GPIO_INT(WARM_RESET_L,      PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_warm_reset_interrupt)  /* AP warm reset */
+GPIO_INT(AP_EC_SPI_CS_L,    PIN(5, 3), GPIO_INT_FALLING | GPIO_PULL_DOWN, shi_cs_event)  /* EC SPI Chip Select */
+
+GPIO_INT(BASE_DET_L,        PIN(3, 7), GPIO_INT_BOTH, base_detect_interrupt)  /* Detachable base attached? */
+
+/* Sensor interrupts */
+GPIO_INT(LID_360_L,         PIN(7, 3), GPIO_INT_BOTH, gmr_tablet_switch_isr)
+GPIO_INT(LID_INT_N_HALL1,   PIN(D, 7), GPIO_INT_BOTH, ks_interrupt)  /* Kickstand attached (0) or detached (1) */
+GPIO_INT(LID_INT_N_HALL2,   PIN(6, 0), GPIO_INT_BOTH, ks_interrupt)  /* Kickstand close (0) or open (1) */
+GPIO_INT(ACCEL_GYRO_INT_L,  PIN(A, 0), GPIO_INT_FALLING, motion_interrupt)  /* Accelerometer/gyro interrupt */
+
+/* Switchcap, for LN9310, it is the interrupt line of LN9310. */
+GPIO_INT(LN9310_INT,      PIN(E, 2), GPIO_INT_FALLING, switchcap_interrupt)
+
+/*
+ * EC_RST_ODL acts as a wake source from hibernate mode. However, it does not
+ * need to be an interrupt for normal EC operations. Simply set it an INPUT.
+ */
+GPIO(EC_RST_ODL,            PIN(0, 2), GPIO_INPUT)     /* EC reset */
+GPIO(EC_ENTERING_RW,        PIN(E, 1), GPIO_OUT_LOW)   /* Indicate when EC is entering RW code */
+GPIO(EC_BATT_PRES_ODL,      PIN(E, 5), GPIO_INPUT)     /* Battery Present */
+
+/* PMIC/AP 1.8V */
+GPIO(PM845_RESIN_L,         PIN(3, 2), GPIO_ODR_HIGH)  /* PMIC reset trigger */
+GPIO(PMIC_KPD_PWR_ODL,      PIN(D, 6), GPIO_ODR_HIGH)  /* PMIC power button */
+GPIO(EC_INT_L,              PIN(A, 2), GPIO_ODR_HIGH)  /* Interrupt line between AP and EC */
+GPIO(QSIP_ON,               PIN(5, 0), GPIO_OUT_LOW)   /* Not used, for non-switchcap testing */
+
+/* Power enables */
+GPIO(HIBERNATE_L,           PIN(5, 2), GPIO_ODR_HIGH)  /* EC hibernate */
+GPIO(SWITCHCAP_ON_L,        PIN(D, 5), GPIO_ODR_HIGH)  /* Enable switch cap */
+GPIO(EN_PP3300_A,           PIN(A, 6), GPIO_OUT_LOW)   /* Enable PP3300 */
+GPIO(EN_PP5000_A,           PIN(6, 7), GPIO_OUT_LOW)   /* Enable PP5000 */
+GPIO(EC_BL_DISABLE_L,       PIN(B, 6), GPIO_OUT_LOW)   /* Backlight disable signal from EC */
+
+/* TODO(waihong): Should remove it from hardware */
+GPIO(CAM_LED,               PIN(3, 0), GPIO_INPUT)
+
+/* Base detection */
+GPIO(EN_BASE,               PIN(0, 4), GPIO_OUT_LOW)   /* Enable power to detachable base */
+
+/* USB-C */
+GPIO(USB_C0_PD_RST_L,       PIN(F, 1), GPIO_ODR_HIGH)  /* Port-0 TCPC chip reset, actaully Open-Drain */
+GPIO(USB_C1_PD_RST_L,       PIN(E, 4), GPIO_ODR_HIGH)  /* Port-1 TCPC chip reset, actually Open-Drain */
+GPIO(DP_MUX_OE_L,           PIN(9, 6), GPIO_ODR_HIGH)  /* DP mux enable, actually Open-Drain */
+GPIO(DP_MUX_SEL,            PIN(4, 5), GPIO_OUT_LOW)   /* DP mux selection: L:C0, H:C1 */
+GPIO(DP_HOT_PLUG_DET,       PIN(9, 5), GPIO_OUT_LOW)   /* DP HPD to AP */
+
+/* LEDs */
+GPIO(EC_CHG_LED_Y_C0,       PIN(C, 3), GPIO_OUT_LOW)
+GPIO(EC_CHG_LED_W_C0,       PIN(C, 4), GPIO_OUT_LOW)
+
+/*
+ * SPI host interface - enable PDs by default. These will be made functional
+ * by the SHI driver when the AP powers up, and restored back to GPIO when
+ * the AP powers down.
+ */
+GPIO(AP_EC_SPI_MOSI,        PIN(4, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(AP_EC_SPI_MISO,        PIN(4, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(AP_EC_SPI_CLK,         PIN(5, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+
+/* PWM */
+GPIO(EDP_BKLTCTL,           PIN(B, 7), GPIO_INPUT)     /* PWM5 */
+
+/* ADC */
+GPIO(PPVAR_BOOSTIN_SENSE,   PIN(4, 4), GPIO_INPUT)     /* ADC1 */
+GPIO(CHARGER_IADP,          PIN(4, 3), GPIO_INPUT)     /* ADC2 */
+GPIO(CHARGER_PMON,          PIN(4, 2), GPIO_INPUT)     /* ADC3 */
+
+/* I2C */
+GPIO(EC_I2C_POWER_SCL,      PIN(B, 5), GPIO_INPUT)
+GPIO(EC_I2C_POWER_SDA,      PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_PD_SCL,  PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_PD_SDA,  PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_PD_SCL,  PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_PD_SDA,  PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SCL,     PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SDA,     PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,     PIN(B, 3), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SENSOR_SDA,     PIN(B, 2), GPIO_INPUT | GPIO_SEL_1P8V)
+
+/* Board/SKU IDs */
+GPIO(BRD_ID0,               PIN(C, 7), GPIO_INPUT)
+GPIO(BRD_ID1,               PIN(9, 3), GPIO_INPUT)
+GPIO(BRD_ID2,               PIN(6, 3), GPIO_INPUT)
+GPIO(SKU_ID0,               PIN(F, 0), GPIO_INPUT)
+GPIO(SKU_ID1,               PIN(4, 1), GPIO_INPUT)
+GPIO(SKU_ID2,               PIN(D, 4), GPIO_INPUT)
+
+/* Special straps */
+GPIO(ARM_X86,               PIN(6, 6), GPIO_OUT_LOW)  /* NC, low for power saving */
+
+/* Unused GPIOs, NC. Apply PU for power saving */
+UNUSED(PIN(5, 1))
+UNUSED(PIN(F, 3))
+UNUSED(PIN(3, 1))
+UNUSED(PIN(2, 7))
+UNUSED(PIN(2, 6))
+UNUSED(PIN(2, 5))
+UNUSED(PIN(2, 4))
+UNUSED(PIN(2, 3))
+UNUSED(PIN(2, 2))
+UNUSED(PIN(2, 1))
+UNUSED(PIN(2, 0))
+UNUSED(PIN(1, 7))
+UNUSED(PIN(1, 6))
+UNUSED(PIN(1, 5))
+UNUSED(PIN(1, 4))
+UNUSED(PIN(1, 3))
+UNUSED(PIN(1, 2))
+UNUSED(PIN(1, 1))
+UNUSED(PIN(1, 0))
+UNUSED(PIN(0, 7))
+UNUSED(PIN(0, 6))
+UNUSED(PIN(0, 5))
+UNUSED(PIN(9, 4))
+UNUSED(PIN(9, 7))
+UNUSED(PIN(A, 7))
+UNUSED(PIN(B, 0))
+UNUSED(PIN(A, 5))
+UNUSED(PIN(3, 5))
+UNUSED(PIN(7, 2))
+UNUSED(PIN(8, 1))
+UNUSED(PIN(7, 6))
+UNUSED(PIN(3, 4))
+UNUSED(PIN(C, 5))
+UNUSED(PIN(C, 6))
+UNUSED(PIN(C, 0))
+UNUSED(PIN(A, 3))
+UNUSED(PIN(6, 2))
+UNUSED(PIN(8, 3))
+UNUSED(PIN(B, 1))
+UNUSED(PIN(5, 6))
+UNUSED(PIN(8, 0))
+UNUSED(PIN(D, 0))
+UNUSED(PIN(D, 1))
+UNUSED(PIN(D, 3))
+UNUSED(PIN(7, 5))
+UNUSED(PIN(8, 6))
+UNUSED(PIN(7, 4))
+UNUSED(PIN(8, 5))
+
+/* Alternate functions GPIO definitions */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)            /* UART (GPIO64/65) */
+ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0)             /* I2C0 (GPIOB4/B5) */
+ALTERNATE(PIN_MASK(9, 0x07), 1, MODULE_I2C, 0)             /* I2C1 SDA (GPIO90), I2C2 (GPIO91/92) */
+ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, 0)             /* I2C1 SCL (GPIO87) */
+ALTERNATE(PIN_MASK(3, 0x48), 1, MODULE_I2C, 0)             /* I2C5 (GPIO33/36) */
+ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, GPIO_SEL_1P8V) /* I2C7 (GPIOB2/B3) - 1.8V */
+ALTERNATE(PIN_MASK(D, 0x03), 1, MODULE_I2C, 0)             /* I2C3 (GPIOD0/D1) */
+ALTERNATE(PIN_MASK(4, 0x1C), 0, MODULE_ADC, 0)             /* ADC1 (GPIO44), ADC2 (GPIO43), ADC3 (GPIO42) */
+ALTERNATE(PIN_MASK(4, 0xC0), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SDO (GPIO47), SHI_SDI (GPIO46) */
+ALTERNATE(PIN_MASK(5, 0x28), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SCLK (GPIO55), SHI_CS# (GPIO53) */
+ALTERNATE(PIN_MASK(B, 0x80), 1, MODULE_PWM, 0)             /* PWM5 (GPIOB7) - EDP_BKLTCTL */
diff --git a/board/gelarshie/led.c b/board/gelarshie/led.c
new file mode 100644
index 0000000000..33dac6bb12
--- /dev/null
+++ b/board/gelarshie/led.c
@@ -0,0 +1,185 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power and battery LED control.
+ */
+
+#include "battery.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "chipset.h"
+#include "ec_commands.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "led_common.h"
+#include "system.h"
+#include "util.h"
+
+#define LED_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS)
+/* Battery LED blinks every per 400ms */
+#define LED_HALF_ONE_SEC (500 / HOOK_TICK_INTERVAL_MS)
+
+#define BAT_LED_ON 1
+#define BAT_LED_OFF 0
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_BATTERY_LED,
+};
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+enum led_color {
+	LED_OFF = 0,
+	LED_AMBER,
+	LED_BLUE,
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
+};
+
+static void led_set_color(enum led_color color)
+{
+	gpio_set_level(GPIO_EC_CHG_LED_Y_C0,
+		       (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
+	gpio_set_level(GPIO_EC_CHG_LED_W_C0,
+		       (color == LED_BLUE) ? BAT_LED_ON : BAT_LED_OFF);
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	brightness_range[EC_LED_COLOR_AMBER] = 1;
+	brightness_range[EC_LED_COLOR_BLUE] = 1;
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (brightness[EC_LED_COLOR_BLUE] != 0)
+		led_set_color(LED_BLUE);
+	else if (brightness[EC_LED_COLOR_AMBER] != 0)
+		led_set_color(LED_AMBER);
+	else
+		led_set_color(LED_OFF);
+
+	return EC_SUCCESS;
+}
+
+static void board_led_set_battery(void)
+{
+	static int battery_ticks;
+	int color = LED_OFF;
+	int period = 0;
+
+	battery_ticks++;
+
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
+		/* Always indicate amber on when charging. */
+		color = LED_AMBER;
+		break;
+	case LED_PWRS_DISCHARGE:
+		if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
+			/* Discharging in S3: White 1 sec, off 1 sec */
+			period = (1 + 1) * LED_ONE_SEC;
+			battery_ticks = battery_ticks % period;
+			if (battery_ticks < 1 * LED_ONE_SEC) {
+				if (charge_get_percent() < 10) {
+					/* Blink amber light (1 sec on, 1 sec
+					 * off) */
+					color = LED_AMBER;
+				} else {
+					/* Blink white light (1 sec on, 1 sec
+					 * off) */
+					color = LED_BLUE;
+				}
+			} else {
+				color = LED_OFF;
+			}
+		} else {
+			/* Discharging in S5 and S0: off */
+			/* Blink amber light (1 sec on, 1 sec off) */
+			if (charge_get_percent() < 10) {
+				period = (1 + 1) * LED_ONE_SEC;
+				battery_ticks = battery_ticks % period;
+				if (battery_ticks < 1 * LED_ONE_SEC)
+					color = LED_AMBER;
+				else
+					color = LED_OFF;
+			} else {
+				/* G3 or S5 or S0: off */
+				color = LED_OFF;
+			}
+		}
+		break;
+	case LED_PWRS_ERROR:
+		/* Battery error: Amber on 0.5 sec, off 0.5 sec */
+		period = (1 + 1) * LED_HALF_ONE_SEC;
+		battery_ticks = battery_ticks % period;
+		if (battery_ticks < 1 * LED_HALF_ONE_SEC)
+			color = LED_AMBER;
+		else
+			color = LED_OFF;
+		break;
+	case LED_PWRS_CHARGE_NEAR_FULL:
+		/* Full Charged: Blue on */
+		/* S3: Blink white light (1 sec on, 1 sec off) */
+		if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
+			period = (1 + 1) * LED_ONE_SEC;
+			battery_ticks = battery_ticks % period;
+			if (battery_ticks < 1 * LED_ONE_SEC)
+				color = LED_BLUE;
+			else
+				color = LED_OFF;
+		} else {
+			/* Full charged: White on */
+			color = LED_BLUE;
+		}
+		break;
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		color = LED_BLUE;
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		/* Factory mode: Blue 2 sec, Amber 2 sec */
+		period = (2 + 2) * LED_ONE_SEC;
+		battery_ticks = battery_ticks % period;
+		if (battery_ticks < 2 * LED_ONE_SEC)
+			color = LED_BLUE;
+		else
+			color = LED_AMBER;
+		break;
+	default:
+		/* Other states don't alter LED behavior */
+		break;
+	}
+
+	led_set_color(color);
+}
+
+/* Called by hook task every TICK */
+static void led_tick(void)
+{
+	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
+		board_led_set_battery();
+}
+DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
+
+void led_control(enum ec_led_id led_id, enum ec_led_state state)
+{
+	enum led_color color;
+
+	if ((led_id != EC_LED_ID_RECOVERY_HW_REINIT_LED) &&
+	    (led_id != EC_LED_ID_SYSRQ_DEBUG_LED))
+		return;
+
+	if (state == LED_STATE_RESET) {
+		led_auto_control(EC_LED_ID_BATTERY_LED, 1);
+		board_led_set_battery();
+		return;
+	}
+
+	color = state ? LED_BLUE : LED_OFF;
+
+	led_auto_control(EC_LED_ID_BATTERY_LED, 0);
+
+	led_set_color(color);
+}
diff --git a/board/gelarshie/usbc_config.c b/board/gelarshie/usbc_config.c
new file mode 100644
index 0000000000..70c0229793
--- /dev/null
+++ b/board/gelarshie/usbc_config.c
@@ -0,0 +1,61 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Trogdor family-specific USB-C configuration */
+
+#include "charge_state.h"
+#include "charger.h"
+#include "charger/isl923x_public.h"
+#include "gpio.h"
+#include "usb_pd.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+};
+
+int charger_profile_override(struct charge_state_data *curr)
+{
+	int usb_mv;
+	int port;
+
+	if (curr->state != ST_CHARGE)
+		return 0;
+
+	/* Lower the max requested voltage to 5V when battery is full. */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
+	    !(curr->batt.flags & BATT_FLAG_BAD_STATUS) &&
+	    !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
+	    (curr->batt.status & STATUS_FULLY_CHARGED))
+		usb_mv = 5000;
+	else
+		usb_mv = PD_MAX_VOLTAGE_MV;
+
+	if (pd_get_max_voltage() != usb_mv) {
+		CPRINTS("VBUS limited to %dmV", usb_mv);
+		for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++)
+			pd_set_external_voltage_limit(port, usb_mv);
+	}
+
+	return 0;
+}
+
+enum ec_status charger_profile_override_get_param(uint32_t param,
+						  uint32_t *value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+enum ec_status charger_profile_override_set_param(uint32_t param,
+						  uint32_t value)
+{
+	return EC_RES_INVALID_PARAM;
+}
diff --git a/board/gelarshie/vif_override.xml b/board/gelarshie/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/gelarshie/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/gelatin b/board/gelatin
new file mode 120000
index 0000000000..7f4a914148
--- /dev/null
+++ b/board/gelatin
@@ -0,0 +1 @@
+hammer
\ No newline at end of file
diff --git a/board/genesis/board.c b/board/genesis/board.c
new file mode 100644
index 0000000000..3bea8beb63
--- /dev/null
+++ b/board/genesis/board.c
@@ -0,0 +1,535 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Puff board-specific configuration */
+
+#include "adc.h"
+#include "button.h"
+#include "chipset.h"
+#include "common.h"
+#include "core/cortex-m/cpu.h"
+#include "cros_board_info.h"
+#include "driver/ina3221.h"
+#include "ec_commands.h"
+#include "extpower.h"
+#include "fan.h"
+#include "fan_chip.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power/cometlake-discrete.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "spi.h"
+#include "switch.h"
+#include "system.h"
+#include "task.h"
+#include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
+#include "thermal.h"
+#include "uart.h"
+#include "usb_common.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+
+static void power_monitor(void);
+DECLARE_DEFERRED(power_monitor);
+
+static uint8_t usbc_overcurrent;
+static int32_t base_5v_power;
+
+/*
+ * Power usage for each port as measured or estimated.
+ * Units are milliwatts (5v x ma current)
+ */
+#define PWR_BASE_LOAD (5 * 1335)
+#define PWR_FRONT_HIGH (5 * 1500)
+#define PWR_FRONT_LOW (5 * 900)
+#define PWR_REAR (5 * 1500)
+#define PWR_HDMI (5 * 562)
+#define PWR_C_HIGH (5 * 3740)
+#define PWR_C_LOW (5 * 2090)
+#define PWR_MAX (5 * 10000)
+
+/*
+ * Update the 5V power usage, assuming no throttling,
+ * and invoke the power monitoring.
+ */
+static void update_5v_usage(void)
+{
+	int front_ports = 0;
+	/*
+	 * Recalculate the 5V load, assuming no throttling.
+	 */
+	base_5v_power = PWR_BASE_LOAD;
+	if (!gpio_get_level(GPIO_USB_A2_OC_ODL)) {
+		front_ports++;
+		base_5v_power += PWR_FRONT_LOW;
+	}
+	if (!gpio_get_level(GPIO_USB_A3_OC_ODL)) {
+		front_ports++;
+		base_5v_power += PWR_FRONT_LOW;
+	}
+	/*
+	 * Only 1 front port can run higher power at a time.
+	 */
+	if (front_ports > 0)
+		base_5v_power += PWR_FRONT_HIGH - PWR_FRONT_LOW;
+	if (!gpio_get_level(GPIO_USB_A1_OC_ODL))
+		base_5v_power += PWR_REAR;
+	if (!gpio_get_level(GPIO_HDMI_CONN0_OC_ODL))
+		base_5v_power += PWR_HDMI;
+	if (!gpio_get_level(GPIO_HDMI_CONN1_OC_ODL))
+		base_5v_power += PWR_HDMI;
+	if (usbc_overcurrent)
+		base_5v_power += PWR_C_HIGH;
+	/*
+	 * Invoke the power handler immediately.
+	 */
+	hook_call_deferred(&power_monitor_data, 0);
+}
+DECLARE_DEFERRED(update_5v_usage);
+/*
+ * Start power monitoring after ADCs have been initialised.
+ */
+DECLARE_HOOK(HOOK_INIT, update_5v_usage, HOOK_PRIO_INIT_ADC + 1);
+
+static void port_ocp_interrupt(enum gpio_signal signal)
+{
+	hook_call_deferred(&update_5v_usage_data, 0);
+}
+
+/******************************************************************************/
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/******************************************************************************/
+/* SPI devices */
+const struct spi_device_t spi_devices[] = {};
+const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
+
+/******************************************************************************/
+/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
+	[PWM_CH_LED_RED] = { .channel = 0,
+			     .flags = PWM_CONFIG_DSLEEP,
+			     .freq = 2000 },
+	[PWM_CH_LED_WHITE] = { .channel = 2,
+			       .flags = PWM_CONFIG_DSLEEP,
+			       .freq = 2000 },
+};
+
+/******************************************************************************/
+/* I2C port map configuration */
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "ina",
+	  .port = I2C_PORT_INA,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_SCL,
+	  .sda = GPIO_I2C0_SDA },
+	{ .name = "ppc0",
+	  .port = I2C_PORT_PPC0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
+	{ .name = "pse",
+	  .port = I2C_PORT_PSE,
+	  .kbps = 400,
+	  .scl = GPIO_I2C4_SCL,
+	  .sda = GPIO_I2C4_SDA },
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 400,
+	  .scl = GPIO_I2C5_SCL,
+	  .sda = GPIO_I2C5_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_I2C7_SCL,
+	  .sda = GPIO_I2C7_SDA },
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+const struct adc_t adc_channels[] = {
+	[ADC_SNS_PP3300] = {
+		/*
+		 * 4700/5631 voltage divider: can take the value out of range
+		 * for 32-bit signed integers, so truncate to 470/563 yielding
+		 * <0.1% error and a maximum intermediate value of 1623457792,
+		 * which comfortably fits in int32.
+		 */
+		.name = "SNS_PP3300",
+		.input_ch = NPCX_ADC_CH2,
+		.factor_mul = ADC_MAX_VOLT * 563,
+		.factor_div = (ADC_READ_MAX + 1) * 470,
+	},
+	[ADC_SNS_PP1050] = {
+		.name = "SNS_PP1050",
+		.input_ch = NPCX_ADC_CH7,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+	},
+	[ADC_VBUS] = {  /* 5/39 voltage divider */
+		.name = "VBUS",
+		.input_ch = NPCX_ADC_CH4,
+		.factor_mul = ADC_MAX_VOLT * 39,
+		.factor_div = (ADC_READ_MAX + 1) * 5,
+	},
+	[ADC_PPVAR_IMON] = {  /* 500 mV/A */
+		.name = "PPVAR_IMON",
+		.input_ch = NPCX_ADC_CH9,
+		.factor_mul = ADC_MAX_VOLT * 2, /* Milliamps */
+		.factor_div = ADC_READ_MAX + 1,
+	},
+	[ADC_TEMP_SENSOR_1] = {
+		.name = "TEMP_SENSOR_1",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_CORE] = {
+		.name = "Core",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_1,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/******************************************************************************/
+/* Wake up pins */
+const enum gpio_signal hibernate_wake_pins[] = {};
+const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
+
+/******************************************************************************/
+/* Physical fans. These are logically separate from pwm_channels. */
+const struct fan_conf fan_conf_0 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
+	.pgood_gpio = -1,
+	.enable_gpio = -1,
+};
+
+const struct fan_rpm fan_rpm_0 = {
+	.rpm_min = 2500,
+	.rpm_start = 2500,
+	.rpm_max = 5200,
+};
+
+const struct fan_t fans[] = {
+	[FAN_CH_0] = { .conf = &fan_conf_0, .rpm = &fan_rpm_0, },
+};
+BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
+
+/******************************************************************************/
+/* MFT channels. These are logically separate from pwm_channels. */
+const struct mft_t mft_channels[] = {
+	[MFT_CH_0] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN },
+};
+BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
+
+/******************************************************************************/
+/* Thermal control; drive fan based on temperature sensors. */
+static const int temp_fan_off = C_TO_K(35);
+static const int temp_fan_max = C_TO_K(55);
+struct ec_thermal_config thermal_params[] = {
+	[TEMP_SENSOR_CORE] = {
+		.temp_host = {
+			[EC_TEMP_THRESH_WARN] = 0,
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(78),
+			[EC_TEMP_THRESH_HALT] = C_TO_K(85),
+		},
+		.temp_host_release = {
+			[EC_TEMP_THRESH_WARN] = 0,
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
+			[EC_TEMP_THRESH_HALT] = 0,
+		},
+		.temp_fan_off = temp_fan_off,
+		.temp_fan_max = temp_fan_max,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
+
+static const struct fan_step_1_1 fan_table0[] = {
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(35),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(41),
+	  .rpm = 2500 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(40),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(44),
+	  .rpm = 2900 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(42),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(46),
+	  .rpm = 3400 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(44),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(48),
+	  .rpm = 3900 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(46),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(50),
+	  .rpm = 4400 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(48),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(52),
+	  .rpm = 4900 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(50),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(55),
+	  .rpm = 5200 },
+};
+#define NUM_FAN_LEVELS ARRAY_SIZE(fan_table0)
+
+static const struct fan_step_1_1 *fan_table = fan_table0;
+
+int fan_percent_to_rpm(int fan, int temp_ratio)
+{
+	return temp_ratio_to_rpm_hysteresis(fan_table, NUM_FAN_LEVELS, fan,
+					    temp_ratio, NULL);
+}
+
+/* Power sensors */
+const struct ina3221_t ina3221[] = {
+	{ I2C_PORT_INA, 0x40, { "PP3300_G", "PP5000_A", "PP3300_WLAN" } },
+	{ I2C_PORT_INA, 0x42, { "PP3300_A", "PP3300_SSD", "PP3300_LAN" } },
+	{ I2C_PORT_INA, 0x43, { NULL, "PP1200_U", "PP2500_DRAM" } }
+};
+const unsigned int ina3221_count = ARRAY_SIZE(ina3221);
+
+static uint16_t board_version;
+static uint32_t sku_id;
+static uint32_t fw_config;
+
+static void cbi_init(void)
+{
+	/*
+	 * Load board info from CBI to control per-device configuration.
+	 *
+	 * If unset it's safe to treat the board as a proto, just C10 gating
+	 * won't be enabled.
+	 */
+	uint32_t val;
+
+	if (cbi_get_board_version(&val) == EC_SUCCESS && val <= UINT16_MAX)
+		board_version = val;
+	if (cbi_get_sku_id(&val) == EC_SUCCESS)
+		sku_id = val;
+	if (cbi_get_fw_config(&val) == EC_SUCCESS)
+		fw_config = val;
+	CPRINTS("Board Version: %d, SKU ID: 0x%08x, F/W config: 0x%08x",
+		board_version, sku_id, fw_config);
+}
+DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1);
+
+static void board_init(void)
+{
+	uint8_t *memmap_batt_flags;
+
+	/* Override some GPIO interrupt priorities.
+	 *
+	 * These interrupts are timing-critical for AP power sequencing, so we
+	 * increase their NVIC priority from the default of 3. This affects
+	 * whole MIWU groups of 8 GPIOs since they share an IRQ.
+	 *
+	 * Latency at the default priority level can be hundreds of
+	 * microseconds while other equal-priority IRQs are serviced, so GPIOs
+	 * requiring faster response must be higher priority.
+	 */
+	/* CPU_C10_GATE_L on GPIO6.7: must be ~instant for ~60us response. */
+	cpu_set_interrupt_priority(NPCX_IRQ_WKINTH_1, 1);
+	/*
+	 * slp_s3_interrupt (GPIOA.5 on WKINTC_0) must respond within 200us
+	 * (tPLT18); less critical than the C10 gate.
+	 */
+	cpu_set_interrupt_priority(NPCX_IRQ_WKINTC_0, 2);
+
+	/* Always claim AC is online, because we don't have a battery. */
+	memmap_batt_flags = host_get_memmap(EC_MEMMAP_BATT_FLAG);
+	*memmap_batt_flags |= EC_BATT_FLAG_AC_PRESENT;
+	/*
+	 * For board version < 2, the directly connected recovery
+	 * button is not available.
+	 */
+	if (board_version < 2)
+		button_disable_gpio(BUTTON_RECOVERY);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+/******************************************************************************/
+/* USB-A port control */
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_PP5000_USB_VBUS,
+};
+
+int64_t get_time_dsw_pwrok(void)
+{
+	/* DSW_PWROK is turned on before EC was powered. */
+	return -20 * MSEC;
+}
+
+int extpower_is_present(void)
+{
+	/* genesis: If the EC is running, then there is external power */
+	return 1;
+}
+
+int board_is_c10_gate_enabled(void)
+{
+	return 0;
+}
+
+void board_enable_s0_rails(int enable)
+{
+}
+
+/*
+ * Power monitoring and management.
+ *
+ * The overall goal is to gracefully manage the power demand so that
+ * the power budgets are met without letting the system fall into
+ * power deficit (perhaps causing a brownout).
+ *
+ * There are 2 power budgets that need to be managed:
+ *  - overall system power as measured on the main power supply rail.
+ *  - 5V power delivered to the USB and HDMI ports.
+ *
+ * The actual system power demand is calculated from the VBUS voltage and
+ * the input current (read from a shunt), averaged over 5 readings.
+ * The power budget limit is from the charge manager.
+ *
+ * The 5V power cannot be read directly. Instead, we rely on overcurrent
+ * inputs from the USB and HDMI ports to indicate that the port is in use
+ * (and drawing maximum power).
+ *
+ * There are 3 throttles that can be applied (in priority order):
+ *
+ *  - Type A BC1.2 front port restriction (3W)
+ *  - Type C PD (throttle to 1.5A if sourcing)
+ *  - Turn on PROCHOT, which immediately throttles the CPU.
+ *
+ *  The first 2 throttles affect both the system power and the 5V rails.
+ *  The third is a last resort to force an immediate CPU throttle to
+ *  reduce the overall power use.
+ *
+ *  The strategy is to determine what the state of the throttles should be,
+ *  and to then turn throttles off or on as needed to match this.
+ *
+ *  This function runs on demand, or every 2 ms when the CPU is up,
+ *  and continually monitors the power usage, applying the
+ *  throttles when necessary.
+ *
+ *  All measurements are in milliwatts.
+ */
+#define THROT_TYPE_A BIT(0)
+#define THROT_TYPE_C BIT(1)
+#define THROT_PROCHOT BIT(2)
+
+/*
+ * Power gain if front USB A ports are limited.
+ */
+#define POWER_GAIN_TYPE_A 3200
+/*
+ * Power gain if Type C port is limited.
+ */
+#define POWER_GAIN_TYPE_C 8800
+/*
+ * Power is averaged over 10 ms, with a reading every 2 ms.
+ */
+#define POWER_DELAY_MS 2
+#define POWER_READINGS (10 / POWER_DELAY_MS)
+
+static void power_monitor(void)
+{
+	static uint32_t current_state;
+	int32_t delay;
+	uint32_t new_state = 0, diff;
+	int32_t headroom_5v = PWR_MAX - base_5v_power;
+
+	/*
+	 * If CPU is off or suspended, no need to throttle
+	 * or restrict power.
+	 */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF | CHIPSET_STATE_SUSPEND)) {
+		/*
+		 * Slow down monitoring, assume no throttling required.
+		 */
+		delay = 20 * MSEC;
+	} else {
+		delay = POWER_DELAY_MS * MSEC;
+	}
+	/*
+	 * Check the 5v power usage and if necessary,
+	 * adjust the throttles in priority order.
+	 *
+	 * Either throttle may have already been activated by
+	 * the overall power control.
+	 *
+	 * We rely on the overcurrent detection to inform us
+	 * if the port is in use.
+	 *
+	 *  - If type C not already throttled:
+	 *	* If not overcurrent, prefer to limit type C [1].
+	 *	* If in overcurrentuse:
+	 *		- limit type A first [2]
+	 *		- If necessary, limit type C [3].
+	 *  - If type A not throttled, if necessary limit it [2].
+	 */
+	if (headroom_5v < 0) {
+		/*
+		 * Check whether type C is not throttled,
+		 * and is not overcurrent.
+		 */
+		if (!((new_state & THROT_TYPE_C) || usbc_overcurrent)) {
+			/*
+			 * [1] Type C not in overcurrent, throttle it.
+			 */
+			headroom_5v += PWR_C_HIGH - PWR_C_LOW;
+			new_state |= THROT_TYPE_C;
+		}
+		/*
+		 * [2] If type A not already throttled, and power still
+		 * needed, limit type A.
+		 */
+		if (!(new_state & THROT_TYPE_A) && headroom_5v < 0) {
+			headroom_5v += PWR_FRONT_HIGH - PWR_FRONT_LOW;
+			new_state |= THROT_TYPE_A;
+		}
+		/*
+		 * [3] If still under-budget, limit type C.
+		 * No need to check if it is already throttled or not.
+		 */
+		if (headroom_5v < 0)
+			new_state |= THROT_TYPE_C;
+	}
+	/*
+	 * Turn the throttles on or off if they have changed.
+	 */
+	diff = new_state ^ current_state;
+	current_state = new_state;
+	if (diff & THROT_PROCHOT) {
+		int prochot = (new_state & THROT_PROCHOT) ? 0 : 1;
+
+		gpio_set_level(GPIO_EC_PROCHOT_ODL, prochot);
+	}
+	if (diff & THROT_TYPE_A) {
+		int typea_bc = (new_state & THROT_TYPE_A) ? 1 : 0;
+
+		gpio_set_level(GPIO_USB_A3_LOW_PWR_OD, typea_bc);
+	}
+	hook_call_deferred(&power_monitor_data, delay);
+}
diff --git a/board/genesis/board.h b/board/genesis/board.h
new file mode 100644
index 0000000000..603fdb0d02
--- /dev/null
+++ b/board/genesis/board.h
@@ -0,0 +1,226 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Puff board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#undef CONFIG_UART_TX_BUF_SIZE
+#define CONFIG_UART_TX_BUF_SIZE 4096
+
+/* NPCX7 config */
+#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */
+#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */
+
+/* Internal SPI flash on NPCX796FC is 512 kB */
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
+#define CONFIG_SPI_FLASH_REGS
+#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
+
+/* EC Defines */
+#define CONFIG_ADC
+#define CONFIG_BOARD_HAS_RTC_RESET
+#define CONFIG_BOARD_VERSION_CBI
+#define CONFIG_DEDICATED_RECOVERY_BUTTON
+#define CONFIG_DEDICATED_RECOVERY_BUTTON_2
+#define CONFIG_BUTTONS_RUNTIME_CONFIG
+#define CONFIG_BOARD_RESET_AFTER_POWER_ON
+/* TODO: (b/143496253) re-enable CEC */
+/* #define CONFIG_CEC */
+#define CONFIG_CRC8
+#define CONFIG_CBI_EEPROM
+#define CONFIG_EMULATED_SYSRQ
+#undef CONFIG_KEYBOARD_BOOT_KEYS
+#define CONFIG_MKBP_INPUT_DEVICES
+#define CONFIG_MKBP_USE_HOST_EVENT
+#undef CONFIG_KEYBOARD_RUNTIME_KEYS
+#undef CONFIG_HIBERNATE
+#define CONFIG_HOST_INTERFACE_ESPI
+#define CONFIG_LED_COMMON
+#undef CONFIG_LID_SWITCH
+#define CONFIG_LTO
+#define CONFIG_PWM
+#define CONFIG_VBOOT_EFS2
+#define CONFIG_VBOOT_HASH
+#define CONFIG_VSTORE
+#define CONFIG_VSTORE_SLOT_COUNT 1
+#define CONFIG_SHA256
+
+/* EC Commands */
+#define CONFIG_CMD_BUTTON
+/* Include CLI command needed to support CCD testing. */
+#define CONFIG_CMD_CHARGEN
+#undef CONFIG_CMD_FASTCHARGE
+#undef CONFIG_CMD_KEYBOARD
+#define CONFIG_HOSTCMD_PD_CONTROL
+#undef CONFIG_CMD_PWR_AVG
+#define CONFIG_CMD_PPC_DUMP
+#define CONFIG_CMD_TCPC_DUMP
+#ifdef SECTION_IS_RO
+/* Reduce RO size by removing less-relevant commands. */
+#undef CONFIG_CMD_APTHROTTLE
+#undef CONFIG_CMD_CHARGEN
+#undef CONFIG_CMD_HCDEBUG
+#undef CONFIG_CMD_MMAPINFO
+#endif
+
+#undef CONFIG_CONSOLE_CMDHELP
+
+/* Don't generate host command debug by default */
+#undef CONFIG_HOSTCMD_DEBUG_MODE
+#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
+
+/* Enable AP Reset command for TPM with old firmware version to detect it. */
+#define CONFIG_CMD_AP_RESET_LOG
+#define CONFIG_HOSTCMD_AP_RESET
+
+/* Chipset config */
+#define CONFIG_CHIPSET_COMETLAKE_DISCRETE
+/* check */
+#define CONFIG_CHIPSET_CAN_THROTTLE
+#define CONFIG_CHIPSET_RESET_HOOK
+#define CONFIG_CPU_PROCHOT_ACTIVE_LOW
+
+#define CONFIG_POWER_BUTTON
+#define CONFIG_POWER_BUTTON_IGNORE_LID
+#define CONFIG_POWER_BUTTON_X86
+/* Check: */
+#define CONFIG_POWER_BUTTON_INIT_IDLE
+#define CONFIG_POWER_COMMON
+#define CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD 30
+#define CONFIG_DELAY_DSW_PWROK_TO_PWRBTN
+#define CONFIG_POWER_PP5000_CONTROL
+#define CONFIG_POWER_S0IX
+#define CONFIG_POWER_SLEEP_FAILURE_DETECTION
+#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
+#define CONFIG_INA3221
+
+/* Fan and temp. */
+#define CONFIG_FANS 1
+#undef CONFIG_FAN_INIT_SPEED
+#define CONFIG_FAN_INIT_SPEED 0
+#define CONFIG_FAN_RPM_CUSTOM
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_TEMP_SENSOR_POWER
+#define CONFIG_THERMISTOR
+#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
+#define CONFIG_THROTTLE_AP
+
+#define CONFIG_USB_PD_PORT_MAX_COUNT 0
+
+/* USB Type A Features */
+#define CONFIG_USB_PORT_POWER_DUMB
+/* There are five ports, but power enable is ganged across all of them. */
+#define USB_PORT_COUNT 1
+
+/* I2C Bus Configuration */
+#define CONFIG_I2C
+#define CONFIG_I2C_CONTROLLER
+#define I2C_PORT_INA NPCX_I2C_PORT0_0
+#define I2C_PORT_PPC0 NPCX_I2C_PORT1_0
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT3_0
+#define I2C_PORT_PSE NPCX_I2C_PORT4_1
+#define I2C_PORT_POWER NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+
+#define PP5000_PGOOD_POWER_SIGNAL_MASK POWER_SIGNAL_MASK(PP5000_A_PGOOD)
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum adc_channel {
+	ADC_SNS_PP3300, /* ADC2 */
+	ADC_SNS_PP1050, /* ADC7 */
+	ADC_VBUS, /* ADC4 */
+	ADC_PPVAR_IMON, /* ADC9 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	/* Number of ADC channels */
+	ADC_CH_COUNT
+};
+
+enum pwm_channel {
+	PWM_CH_FAN,
+	PWM_CH_LED_RED,
+	PWM_CH_LED_WHITE,
+	/* Number of PWM channels */
+	PWM_CH_COUNT
+};
+
+enum fan_channel {
+	FAN_CH_0,
+	/* Number of FAN channels */
+	FAN_CH_COUNT
+};
+
+enum mft_channel {
+	MFT_CH_0 = 0,
+	/* Number of MFT channels */
+	MFT_CH_COUNT,
+};
+
+enum temp_sensor_id { TEMP_SENSOR_CORE, TEMP_SENSOR_COUNT };
+
+/* Board specific handlers */
+void led_alert(int enable);
+void show_critical_error(void);
+
+/*
+ * firmware config fields
+ */
+/*
+ * Barrel-jack power (4 bits).
+ */
+#define EC_CFG_BJ_POWER_L 0
+#define EC_CFG_BJ_POWER_H 3
+#define EC_CFG_BJ_POWER_MASK GENMASK(EC_CFG_BJ_POWER_H, EC_CFG_BJ_POWER_L)
+/*
+ * USB Connector 4 not present (1 bit).
+ */
+#define EC_CFG_NO_USB4_L 4
+#define EC_CFG_NO_USB4_H 4
+#define EC_CFG_NO_USB4_MASK GENMASK(EC_CFG_NO_USB4_H, EC_CFG_NO_USB4_L)
+/*
+ * Thermal solution config (3 bits).
+ */
+#define EC_CFG_THERMAL_L 5
+#define EC_CFG_THERMAL_H 7
+#define EC_CFG_THERMAL_MASK GENMASK(EC_CFG_THERMAL_H, EC_CFG_THERMAL_L)
+
+unsigned int ec_config_get_thermal_solution(void);
+
+#endif /* !__ASSEMBLER__ */
+
+/* Pin renaming */
+#define GPIO_WP_L GPIO_EC_WP_ODL
+#define GPIO_PP5000_A_PG_OD GPIO_PG_PP5000_A_OD
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
+#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_ODL
+#define GPIO_RECOVERY_L_2 GPIO_H1_EC_RECOVERY_BTN_ODL
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_EN_ROA_RAILS
+#define GPIO_AC_PRESENT GPIO_BJ_ADP_PRESENT_L
+
+/*
+ * There is no RSMRST input, so alias it to the output. This short-circuits
+ * common_intel_x86_handle_rsmrst.
+ */
+#define GPIO_PG_EC_RSMRST_ODL GPIO_PCH_RSMRST_L
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/genesis/build.mk b/board/genesis/build.mk
new file mode 100644
index 0000000000..50d3763d2b
--- /dev/null
+++ b/board/genesis/build.mk
@@ -0,0 +1,15 @@
+# -*- makefile -*-
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx7
+CHIP_VARIANT:=npcx7m6fc
+
+board-y=board.o
+board-y+=led.o
+board-y+=pse.o
diff --git a/board/genesis/ec.tasklist b/board/genesis/ec.tasklist
new file mode 100644
index 0000000000..c43d643410
--- /dev/null
+++ b/board/genesis/ec.tasklist
@@ -0,0 +1,15 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 2048) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/genesis/gpio.inc b/board/genesis/gpio.inc
new file mode 100644
index 0000000000..7d2c33c5a9
--- /dev/null
+++ b/board/genesis/gpio.inc
@@ -0,0 +1,170 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Pin names follow the schematic, and are aliased to other names if necessary.
+ * Note: Those with interrupt handlers must be declared first. */
+
+/* Latency on this interrupt is extremely critical, so it comes first to ensure
+ * it gets placed first in gpio_wui_table so gpio_interrupt() needs to do
+ * minimal scanning. */
+GPIO_INT(CPU_C10_GATE_L,       PIN(6, 7), GPIO_INT_BOTH, c10_gate_interrupt)
+
+/* Wake Source interrupts */
+GPIO_INT(EC_WP_ODL,            PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(H1_EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
+
+/* Power sequencing interrupts */
+GPIO_INT(PG_PP5000_A_OD,       PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_PP1800_A_OD,       PIN(3, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_VPRIM_CORE_A_OD,   PIN(2, 3), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_PP1050_A_OD,       PIN(2, 2), GPIO_INT_BOTH, power_signal_interrupt)
+/* EC output, but also interrupt so this can be polled as a power signal */
+GPIO_INT(EC_PCH_RSMRST_L,      PIN(A, 6), GPIO_OUTPUT | GPIO_INT_F_RISING | GPIO_INT_F_FALLING, power_signal_interrupt)
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
+GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
+#endif
+GPIO_INT(PG_PP2500_DRAM_U_OD,  PIN(2, 0), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_PP1200_U_OD,       PIN(2, 1), GPIO_INT_BOTH, power_signal_interrupt)
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, slp_s3_interrupt)
+#endif
+GPIO_INT(PG_PP950_VCCIO_OD,    PIN(1, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(IMVP8_VRRDY_OD,       PIN(1, 6), GPIO_INT_BOTH, power_signal_interrupt)
+
+/*
+ * Directly connected recovery button (not available on some boards).
+ */
+GPIO_INT(EC_RECOVERY_BTN_ODL,  PIN(F, 1), GPIO_INT_BOTH, button_interrupt)
+/*
+ * Recovery button input from H1.
+ */
+GPIO_INT(H1_EC_RECOVERY_BTN_ODL, PIN(2, 4), GPIO_INT_BOTH, button_interrupt)
+GPIO(BJ_ADP_PRESENT_L,     PIN(8, 2), GPIO_INT_BOTH | GPIO_PULL_UP)
+
+/* Port power control interrupts */
+GPIO_INT(HDMI_CONN0_OC_ODL,    PIN(0, 7), GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(HDMI_CONN1_OC_ODL,    PIN(0, 6), GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(USB_A1_OC_ODL,        PIN(A, 2), GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(USB_A2_OC_ODL,        PIN(F, 5), GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(USB_A3_OC_ODL,        PIN(0, 3), GPIO_INT_BOTH, port_ocp_interrupt)
+
+/* PCH/CPU signals */
+GPIO(EC_PCH_PWROK,             PIN(0, 5), GPIO_OUT_LOW)
+GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
+GPIO(EC_PCH_PWR_BTN_ODL,       PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_IN_OD,         PIN(3, 4), GPIO_INPUT)
+GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
+GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
+
+/* Power control outputs */
+GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
+GPIO(EN_PP3300_INA_H1_EC_ODL,  PIN(5, 7), GPIO_ODR_HIGH)
+GPIO(EN_PP1800_A,              PIN(1, 5), GPIO_OUT_LOW)
+GPIO(VCCST_PG_OD,              PIN(1, 4), GPIO_ODR_LOW)
+GPIO(EN_S0_RAILS,              PIN(1, 1), GPIO_OUT_LOW)
+GPIO(EN_ROA_RAILS,             PIN(A, 3), GPIO_OUT_LOW)
+GPIO(EN_PP950_VCCIO,           PIN(1, 0), GPIO_OUT_LOW)
+GPIO(EC_IMVP8_PE,              PIN(A, 7), GPIO_OUT_LOW)
+GPIO(EN_IMVP8_VR,              PIN(F, 4), GPIO_OUT_LOW)
+
+/* Barreljack */
+GPIO(EN_PPVAR_BJ_ADP_L,        PIN(0, 4), GPIO_OUT_LOW)
+
+/* USB type A */
+GPIO(EN_PP5000_USB_VBUS,       PIN(8, 3), GPIO_OUT_LOW)
+GPIO(USB_A_LOW_PWR_OD,         PIN(9, 4), GPIO_ODR_LOW)
+GPIO(USB_A3_LOW_PWR_OD,        PIN(5, 0), GPIO_ODR_LOW)
+GPIO(USB_A1_STATUS_L,          PIN(6, 1), GPIO_INPUT)
+GPIO(USB_A2_STATUS_L,          PIN(C, 7), GPIO_INPUT)
+GPIO(USB_A3_STATUS_L,          PIN(D, 2), GPIO_INPUT)
+
+/* USB type C */
+GPIO(USB_C0_TCPC_RST,          PIN(9, 7), GPIO_OUT_LOW)
+GPIO(USB_C0_POL_L,             PIN(0, 0), GPIO_INPUT | GPIO_SEL_1P8V) /* USB-C Polarity */
+
+/* TPU */
+GPIO(PP3300_TPU_EN,            PIN(E, 4), GPIO_OUT_HIGH)
+
+/* PSE controller */
+GPIO(EC_PSE_PWM_INT,           PIN(B, 0), GPIO_INPUT)		/* PSE controller interrupt */
+GPIO(EC_RST_LTC4291_L,         PIN(9, 6), GPIO_OUT_HIGH)	/* PSE controller reset */
+
+/* Misc. */
+GPIO(M2_SSD_PLN,               PIN(A, 0), GPIO_INPUT)
+GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
+GPIO(CCD_MODE_ODL,             PIN(E, 5), GPIO_ODR_HIGH)
+GPIO(PACKET_MODE_EN,           PIN(7, 5), GPIO_OUT_LOW)
+
+/* HDMI/CEC */
+GPIO(HDMI_CONN0_CEC_OUT,       PIN(B, 1), GPIO_ODR_HIGH)
+GPIO(HDMI_CONN0_CEC_IN,        PIN(4, 0), GPIO_INPUT)
+GPIO(HDMI_CONN1_CEC_OUT,       PIN(9, 5), GPIO_ODR_HIGH)
+GPIO(HDMI_CONN1_CEC_IN,        PIN(D, 3), GPIO_INPUT)
+
+/* I2C pins - Alternate function below configures I2C module on these pins */
+GPIO(I2C0_SCL,                 PIN(B, 5), GPIO_INPUT)           /* EC_I2C_INA_SCL */
+GPIO(I2C0_SDA,                 PIN(B, 4), GPIO_INPUT)           /* EC_I2C_INA_SDA */
+GPIO(I2C1_SCL,                 PIN(9, 0), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPPC_SCL */
+GPIO(I2C1_SDA,                 PIN(8, 7), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPPC_SDA */
+GPIO(I2C3_SCL,                 PIN(D, 1), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPC_SCL */
+GPIO(I2C3_SDA,                 PIN(D, 0), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPC_SDA */
+GPIO(I2C4_SCL,                 PIN(F, 3), GPIO_INPUT)           /* EC_I2C_LTC_SCL */
+GPIO(I2C4_SDA,                 PIN(F, 2), GPIO_INPUT)           /* EC_I2C_LTC_SDA */
+GPIO(I2C5_SCL,                 PIN(3, 3), GPIO_INPUT)           /* EC_I2C_IMVP8_SCL */
+GPIO(I2C5_SDA,                 PIN(3, 6), GPIO_INPUT)           /* EC_I2C_IMVP8_SDA */
+GPIO(I2C7_SCL,                 PIN(B, 3), GPIO_INPUT)           /* EC_I2C_EEPROM_SCL */
+GPIO(I2C7_SDA,                 PIN(B, 2), GPIO_INPUT)           /* EC_I2C_EEPROM_SDA */
+
+/* Alternate functions GPIO definitions */
+ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, 0)                  /* I2C0 */
+ALTERNATE(PIN_MASK(9, 0x01), 0, MODULE_I2C, 0)                  /* I2C1 SCL */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)                  /* I2C1 SDA */
+ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)                  /* I2C3 */
+ALTERNATE(PIN_MASK(F, 0x0C), 0, MODULE_I2C, 0)                  /* I2C4 */
+ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)                  /* I2C5 */
+ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, 0)                  /* I2C7 */
+
+/* PWM */
+ALTERNATE(PIN_MASK(C, 0x08), 0, MODULE_PWM, 0)                  /* PWM0 - Red Led */
+ALTERNATE(PIN_MASK(C, 0x10), 0, MODULE_PWM, 0)                  /* PWM2 - White Led */
+ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)                  /* PWM5 - Fan 1 */
+ALTERNATE(PIN_MASK(7, 0x08), 0, MODULE_PWM, 0)                  /* TA2 - Fan Tachometer */
+
+/* ADC */
+ALTERNATE(PIN_MASK(4, 0x2A), 0, MODULE_ADC, 0)                  /* ADC0, ADC2, ADC4 */
+ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0)                  /* ADC7 */
+ALTERNATE(PIN_MASK(F, 0x01), 0, MODULE_ADC, 0)                  /* ADC9 */
+
+/* UART */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)                 /* UART from EC to Servo */
+
+/* Unused pins */
+UNUSED(PIN(1, 3))						/* EC_GP_SEL1_ODL */
+UNUSED(PIN(C, 0))						/* FAN_PWM_2 */
+UNUSED(PIN(8, 0))						/* LED_BLUE_L */
+UNUSED(PIN(4, 4))						/* ADC1/TEMP_SENSOR_2 */
+UNUSED(PIN(4, 2))						/* ADC3/TEMP_SENSOR_3 */
+UNUSED(PIN(C, 2))						/* A12 NC */
+UNUSED(PIN(9, 2))						/* K8  NC */
+UNUSED(PIN(9, 1))						/* L8  NC */
+UNUSED(PIN(1, 2))						/* C6  NC */
+UNUSED(PIN(6, 6))						/* H4  NC */
+UNUSED(PIN(8, 1))						/* L6  NC */
+UNUSED(PIN(C, 6))						/* B11 NC */
+UNUSED(PIN(E, 2))						/* B8  NC */
+UNUSED(PIN(8, 5))						/* L7  NC */
+UNUSED(PIN(3, 2))						/* E5  NC */
+UNUSED(PIN(D, 6))						/* F6  NC */
+UNUSED(PIN(3, 5))						/* F5  NC */
+UNUSED(PIN(5, 6))						/* M2  NC */
+UNUSED(PIN(8, 6))						/* J8  NC */
+UNUSED(PIN(9, 3))						/* M11 NC */
+UNUSED(PIN(7, 2))						/* H6  NC */
diff --git a/board/genesis/led.c b/board/genesis/led.c
new file mode 100644
index 0000000000..9258b6eb6d
--- /dev/null
+++ b/board/genesis/led.c
@@ -0,0 +1,274 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power LED control for Puff.
+ * Solid green - active power
+ * Green flashing - suspended
+ * Red flashing - alert
+ * Solid red - critical
+ */
+
+#include "chipset.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "led_common.h"
+#include "pwm.h"
+#include "timer.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
+
+/*
+ * Due to the CSME-Lite processing, upon startup the CPU transitions through
+ * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so
+ * delay turning off the LED during suspend/shutdown.
+ */
+#define LED_CPU_DELAY_MS (2000 * MSEC)
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED };
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+enum led_color {
+	LED_OFF = 0,
+	LED_RED,
+	LED_WHITE,
+	LED_AMBER,
+
+	/* Number of colors, not a color itself */
+	LED_COLOR_COUNT
+};
+
+static int set_color_power(enum led_color color, int duty)
+{
+	int white = 0;
+	int red = 0;
+
+	if (duty < 0 || 100 < duty)
+		return EC_ERROR_UNKNOWN;
+
+	switch (color) {
+	case LED_OFF:
+		break;
+	case LED_WHITE:
+		white = 1;
+		break;
+	case LED_RED:
+		red = 1;
+		break;
+	case LED_AMBER:
+		red = 1;
+		white = 1;
+		break;
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+
+	if (red)
+		pwm_set_duty(PWM_CH_LED_RED, duty);
+	else
+		pwm_set_duty(PWM_CH_LED_RED, 0);
+
+	if (white)
+		pwm_set_duty(PWM_CH_LED_WHITE, duty);
+	else
+		pwm_set_duty(PWM_CH_LED_WHITE, 0);
+
+	return EC_SUCCESS;
+}
+
+static int set_color(enum ec_led_id id, enum led_color color, int duty)
+{
+	switch (id) {
+	case EC_LED_ID_POWER_LED:
+		return set_color_power(color, duty);
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+}
+
+#define LED_PULSE_US (2 * SECOND)
+/* 40 msec for nice and smooth transition. */
+#define LED_PULSE_TICK_US (40 * MSEC)
+
+/* When pulsing is enabled, brightness is incremented by <duty_inc> every
+ * <interval> usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented
+ * likewise in LED_PULSE_US usec.
+ */
+static struct {
+	uint32_t interval;
+	int duty_inc;
+	enum led_color color;
+	int duty;
+} led_pulse;
+
+#define CONFIG_TICK(interval, color) \
+	config_tick((interval), 100 / (LED_PULSE_US / (interval)), (color))
+
+static void config_tick(uint32_t interval, int duty_inc, enum led_color color)
+{
+	led_pulse.interval = interval;
+	led_pulse.duty_inc = duty_inc;
+	led_pulse.color = color;
+	led_pulse.duty = 0;
+}
+
+static void pulse_power_led(enum led_color color)
+{
+	set_color(EC_LED_ID_POWER_LED, color, led_pulse.duty);
+	if (led_pulse.duty + led_pulse.duty_inc > 100)
+		led_pulse.duty_inc = led_pulse.duty_inc * -1;
+	else if (led_pulse.duty + led_pulse.duty_inc < 0)
+		led_pulse.duty_inc = led_pulse.duty_inc * -1;
+	led_pulse.duty += led_pulse.duty_inc;
+}
+
+static void led_tick(void);
+DECLARE_DEFERRED(led_tick);
+static void led_tick(void)
+{
+	uint32_t elapsed;
+	uint32_t next = 0;
+	uint32_t start = get_time().le.lo;
+
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		pulse_power_led(led_pulse.color);
+	elapsed = get_time().le.lo - start;
+	next = led_pulse.interval > elapsed ? led_pulse.interval - elapsed : 0;
+	hook_call_deferred(&led_tick_data, next);
+}
+
+static void led_suspend(void)
+{
+	CONFIG_TICK(LED_PULSE_TICK_US, LED_WHITE);
+	led_tick();
+}
+DECLARE_DEFERRED(led_suspend);
+
+static void led_shutdown(void)
+{
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_OFF, 0);
+}
+DECLARE_DEFERRED(led_shutdown);
+
+static void led_shutdown_hook(void)
+{
+	hook_call_deferred(&led_tick_data, -1);
+	hook_call_deferred(&led_suspend_data, -1);
+	hook_call_deferred(&led_shutdown_data, LED_CPU_DELAY_MS);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, led_shutdown_hook, HOOK_PRIO_DEFAULT);
+
+static void led_suspend_hook(void)
+{
+	hook_call_deferred(&led_shutdown_data, -1);
+	hook_call_deferred(&led_suspend_data, LED_CPU_DELAY_MS);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, led_suspend_hook, HOOK_PRIO_DEFAULT);
+
+static void led_resume(void)
+{
+	/* Assume there is no race condition with led_tick, which also
+	 * runs in hook_task.
+	 */
+	hook_call_deferred(&led_tick_data, -1);
+	/*
+	 * Avoid invoking the suspend/shutdown delayed hooks.
+	 */
+	hook_call_deferred(&led_suspend_data, -1);
+	hook_call_deferred(&led_shutdown_data, -1);
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_WHITE, 100);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, led_resume, HOOK_PRIO_DEFAULT);
+
+static void led_init(void)
+{
+	pwm_enable(PWM_CH_LED_RED, 1);
+	pwm_enable(PWM_CH_LED_WHITE, 1);
+
+	if (chipset_in_state(CHIPSET_STATE_ON))
+		led_resume();
+	else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
+		led_suspend();
+	else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		led_shutdown();
+}
+DECLARE_HOOK(HOOK_INIT, led_init, HOOK_PRIO_INIT_PWM + 1);
+
+void led_alert(int enable)
+{
+	if (enable) {
+		/* Overwrite the current signal */
+		config_tick(1 * SECOND, 100, LED_RED);
+		led_tick();
+	} else {
+		/* Restore the previous signal */
+		if (chipset_in_state(CHIPSET_STATE_ON))
+			led_resume();
+		else if (chipset_in_state(CHIPSET_STATE_SUSPEND))
+			led_suspend_hook();
+		else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+			led_shutdown_hook();
+	}
+}
+
+void show_critical_error(void)
+{
+	hook_call_deferred(&led_tick_data, -1);
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_RED, 100);
+}
+
+static int command_led(int argc, const char **argv)
+{
+	enum ec_led_id id = EC_LED_ID_POWER_LED;
+
+	if (argc < 2)
+		return EC_ERROR_PARAM_COUNT;
+
+	if (!strcasecmp(argv[1], "debug")) {
+		led_auto_control(id, !led_auto_control_is_enabled(id));
+		ccprintf("o%s\n", led_auto_control_is_enabled(id) ? "ff" : "n");
+	} else if (!strcasecmp(argv[1], "off")) {
+		set_color(id, LED_OFF, 0);
+	} else if (!strcasecmp(argv[1], "red")) {
+		set_color(id, LED_RED, 100);
+	} else if (!strcasecmp(argv[1], "white")) {
+		set_color(id, LED_WHITE, 100);
+	} else if (!strcasecmp(argv[1], "amber")) {
+		set_color(id, LED_AMBER, 100);
+	} else if (!strcasecmp(argv[1], "alert")) {
+		led_alert(1);
+	} else if (!strcasecmp(argv[1], "crit")) {
+		show_critical_error();
+	} else {
+		return EC_ERROR_PARAM1;
+	}
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(led, command_led,
+			"[debug|red|white|amber|off|alert|crit]",
+			"Turn on/off LED.");
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	brightness_range[EC_LED_COLOR_RED] = 100;
+	brightness_range[EC_LED_COLOR_WHITE] = 100;
+	brightness_range[EC_LED_COLOR_AMBER] = 100;
+}
+
+int led_set_brightness(enum ec_led_id id, const uint8_t *brightness)
+{
+	if (brightness[EC_LED_COLOR_RED])
+		return set_color(id, LED_RED, brightness[EC_LED_COLOR_RED]);
+	else if (brightness[EC_LED_COLOR_WHITE])
+		return set_color(id, LED_WHITE, brightness[EC_LED_COLOR_WHITE]);
+	else if (brightness[EC_LED_COLOR_AMBER])
+		return set_color(id, LED_AMBER, brightness[EC_LED_COLOR_AMBER]);
+	else
+		return set_color(id, LED_OFF, 0);
+}
diff --git a/board/genesis/pse.c b/board/genesis/pse.c
new file mode 100644
index 0000000000..bda7e1994d
--- /dev/null
+++ b/board/genesis/pse.c
@@ -0,0 +1,265 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * The LTC4291 is a power over ethernet (PoE) power sourcing equipment (PSE)
+ * controller.
+ */
+
+#include "common.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "i2c.h"
+#include "string.h"
+#include "timer.h"
+#include "util.h"
+
+#define LTC4291_I2C_ADDR 0x2C
+
+#define LTC4291_REG_SUPEVN_COR 0x0B
+#define LTC4291_REG_STATPWR 0x10
+#define LTC4291_REG_STATPIN 0x11
+#define LTC4291_REG_OPMD 0x12
+#define LTC4291_REG_DISENA 0x13
+#define LTC4291_REG_DETENA 0x14
+#define LTC4291_REG_DETPB 0x18
+#define LTC4291_REG_PWRPB 0x19
+#define LTC4291_REG_RSTPB 0x1A
+#define LTC4291_REG_ID 0x1B
+#define LTC4291_REG_DEVID 0x43
+#define LTC4291_REG_HPMD1 0x46
+#define LTC4291_REG_HPMD2 0x4B
+#define LTC4291_REG_HPMD3 0x50
+#define LTC4291_REG_HPMD4 0x55
+#define LTC4291_REG_LPWRPB 0x6E
+
+#define LTC4291_FLD_STATPIN_AUTO BIT(0)
+#define LTC4291_FLD_RSTPB_RSTALL BIT(4)
+
+#define LTC4291_STATPWR_ON_PORT(port) (0x01 << (port))
+#define LTC4291_DETENA_EN_PORT(port) (0x11 << (port))
+#define LTC4291_DETPB_EN_PORT(port) (0x11 << (port))
+#define LTC4291_PWRPB_OFF_PORT(port) (0x10 << (port))
+
+#define LTC4291_OPMD_AUTO 0xFF
+#define LTC4291_DISENA_ALL 0x0F
+#define LTC4291_DETENA_ALL 0xFF
+#define LTC4291_ID 0x64
+#define LTC4291_DEVID 0x38
+#define LTC4291_HPMD_MIN 0x00
+#define LTC4291_HPMD_MAX 0xA8
+
+#define LTC4291_PORT_MAX 4
+
+#define LTC4291_RESET_DELAY_US (20 * MSEC)
+
+#define I2C_PSE_READ(reg, data) \
+	i2c_read8(I2C_PORT_PSE, LTC4291_I2C_ADDR, LTC4291_REG_##reg, (data))
+
+#define I2C_PSE_WRITE(reg, data) \
+	i2c_write8(I2C_PORT_PSE, LTC4291_I2C_ADDR, LTC4291_REG_##reg, (data))
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+static int pse_write_hpmd(int port, int val)
+{
+	switch (port) {
+	case 0:
+		return I2C_PSE_WRITE(HPMD1, val);
+	case 1:
+		return I2C_PSE_WRITE(HPMD2, val);
+	case 2:
+		return I2C_PSE_WRITE(HPMD3, val);
+	case 3:
+		return I2C_PSE_WRITE(HPMD4, val);
+	default:
+		return EC_ERROR_INVAL;
+	}
+}
+
+/*
+ * Port 1: 100W
+ * Port 2-4: 15W
+ */
+static int pse_port_hpmd[4] = {
+	LTC4291_HPMD_MAX,
+	LTC4291_HPMD_MIN,
+	LTC4291_HPMD_MIN,
+	LTC4291_HPMD_MIN,
+};
+
+static int pse_port_enable(int port)
+{
+	/* Enable detection and classification */
+	return I2C_PSE_WRITE(DETPB, LTC4291_DETPB_EN_PORT(port));
+}
+
+static int pse_port_disable(int port)
+{
+	/* Request power off (this also disables detection/classification) */
+	return I2C_PSE_WRITE(PWRPB, LTC4291_PWRPB_OFF_PORT(port));
+}
+
+static int pse_init_worker(void)
+{
+	timestamp_t deadline;
+	int err, id, devid, statpin, port;
+
+	/* Ignore errors -- may already be resetting */
+	I2C_PSE_WRITE(RSTPB, LTC4291_FLD_RSTPB_RSTALL);
+
+	deadline.val = get_time().val + LTC4291_RESET_DELAY_US;
+	while ((err = I2C_PSE_READ(ID, &id)) != 0) {
+		if (timestamp_expired(deadline, NULL))
+			return err;
+	}
+
+	err = I2C_PSE_READ(DEVID, &devid);
+	if (err != 0)
+		return err;
+
+	if (id != LTC4291_ID || devid != LTC4291_DEVID)
+		return EC_ERROR_INVAL;
+
+	err = I2C_PSE_READ(STATPIN, &statpin);
+	if (err != 0)
+		return err;
+
+	/*
+	 * We don't want to supply power until we've had a chance to set the
+	 * limits.
+	 */
+	if (statpin & LTC4291_FLD_STATPIN_AUTO)
+		CPRINTS("WARN: PSE reset in AUTO mode");
+
+	err = I2C_PSE_WRITE(OPMD, LTC4291_OPMD_AUTO);
+	if (err != 0)
+		return err;
+
+	/* Set maximum power each port is allowed to allocate. */
+	for (port = 0; port < LTC4291_PORT_MAX; port++) {
+		err = pse_write_hpmd(port, pse_port_hpmd[port]);
+		if (err != 0)
+			return err;
+	}
+
+	err = I2C_PSE_WRITE(DISENA, LTC4291_DISENA_ALL);
+	if (err != 0)
+		return err;
+
+	err = I2C_PSE_WRITE(DETENA, LTC4291_DETENA_ALL);
+	if (err != 0)
+		return err;
+
+	return 0;
+}
+
+static void pse_init(void)
+{
+	int err;
+
+	err = pse_init_worker();
+	if (err != 0)
+		CPRINTS("PSE init failed: %d", err);
+	else
+		CPRINTS("PSE init done");
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, pse_init, HOOK_PRIO_DEFAULT);
+
+/* Also reset the PSE on a reboot to toggle the power. */
+DECLARE_HOOK(HOOK_CHIPSET_RESET, pse_init, HOOK_PRIO_DEFAULT);
+
+static int command_pse(int argc, const char **argv)
+{
+	int port;
+
+	/*
+	 *  TODO(b/156399232): endeavour: PSE controller reset by PLTRST
+	 *
+	 *  Initialization does not reliably work after reset because the device
+	 *  is held in reset by the AP. Running this command after boot finishes
+	 *  always succeeds. Remove once the reset signal changes.
+	 */
+	if (!strncmp(argv[1], "init", 4))
+		return pse_init_worker();
+
+	if (argc != 3)
+		return EC_ERROR_PARAM_COUNT;
+
+	port = atoi(argv[1]);
+	if (port < 0 || port >= LTC4291_PORT_MAX)
+		return EC_ERROR_PARAM1;
+
+	if (!strncmp(argv[2], "off", 3))
+		return pse_port_disable(port);
+	else if (!strncmp(argv[2], "on", 2))
+		return pse_port_enable(port);
+	else if (!strncmp(argv[2], "min", 3))
+		return pse_write_hpmd(port, LTC4291_HPMD_MIN);
+	else if (!strncmp(argv[2], "max", 3))
+		return pse_write_hpmd(port, LTC4291_HPMD_MAX);
+	else
+		return EC_ERROR_PARAM2;
+}
+DECLARE_CONSOLE_COMMAND(pse, command_pse, "<port# 0-3> <off | on | min | max>",
+			"Set PSE port power");
+
+static int ec_command_pse_status(int port, uint8_t *status)
+{
+	int detena, statpwr;
+	int err;
+
+	err = I2C_PSE_READ(DETENA, &detena);
+	if (err != 0)
+		return err;
+
+	err = I2C_PSE_READ(STATPWR, &statpwr);
+	if (err != 0)
+		return err;
+
+	if ((detena & LTC4291_DETENA_EN_PORT(port)) == 0)
+		*status = EC_PSE_STATUS_DISABLED;
+	else if ((statpwr & LTC4291_STATPWR_ON_PORT(port)) == 0)
+		*status = EC_PSE_STATUS_ENABLED;
+	else
+		*status = EC_PSE_STATUS_POWERED;
+
+	return 0;
+}
+
+static enum ec_status ec_command_pse(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_pse *p = args->params;
+	int err = 0;
+
+	if (p->port >= LTC4291_PORT_MAX)
+		return EC_RES_INVALID_PARAM;
+
+	switch (p->cmd) {
+	case EC_PSE_STATUS: {
+		struct ec_response_pse_status *r = args->response;
+
+		args->response_size = sizeof(*r);
+		err = ec_command_pse_status(p->port, &r->status);
+		break;
+	}
+	case EC_PSE_ENABLE:
+		err = pse_port_enable(p->port);
+		break;
+	case EC_PSE_DISABLE:
+		err = pse_port_disable(p->port);
+		break;
+	default:
+		return EC_RES_INVALID_PARAM;
+	}
+
+	if (err)
+		return EC_RES_ERROR;
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_PSE, ec_command_pse, EC_VER_MASK(0));
diff --git a/board/gimble/battery.c b/board/gimble/battery.c
new file mode 100644
index 0000000000..89b0ddf1e2
--- /dev/null
+++ b/board/gimble/battery.c
@@ -0,0 +1,94 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "common.h"
+#include "compile_time_macros.h"
+
+/*
+ * Battery info for all Brya battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	/* SMP 996QA193H Battery Information */
+	[BATTERY_SIMPLO_HIGHPOWER] = {
+		.fuel_gauge = {
+			.manuf_name = "333-1D-11-A",
+			.ship_mode = {
+				.reg_addr = 0x0,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 13200,		/* mV */
+			.voltage_normal = 11550,	/* mV */
+			.voltage_min = 9000,		/* mV */
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -20,
+			.discharging_max_c = 60,
+		},
+	},
+	/* Cosmx CA407792G Battery Information */
+	[BATTERY_COSMX] = {
+		.fuel_gauge = {
+			.manuf_name = "333-AC-11-A",
+			.ship_mode = {
+				.reg_addr = 0x0,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 13200,		/* mV */
+			.voltage_normal = 11550,	/* mV */
+			.voltage_min = 9000,		/* mV */
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SIMPLO_HIGHPOWER;
diff --git a/board/gimble/board.c b/board/gimble/board.c
new file mode 100644
index 0000000000..0a04dc5714
--- /dev/null
+++ b/board/gimble/board.c
@@ -0,0 +1,187 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "button.h"
+#include "charge_ramp.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/accel_bma2x2_public.h"
+#include "driver/accel_bma422.h"
+#include "driver/accelgyro_bmi160.h"
+#include "driver/accelgyro_lsm6dsm.h"
+#include "driver/charger/bq25710.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "keyboard_8042_sharedlib.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "ps8xxx.h"
+#include "registers.h"
+#include "switch.h"
+#include "tablet_mode.h"
+#include "throttle_ap.h"
+#include "usbc_config.h"
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* Console output macros */
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+
+/******************************************************************************/
+/* USB-A charging control */
+
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_PP5000_USBA_R,
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
+
+/******************************************************************************/
+
+__override void board_cbi_init(void)
+{
+	config_usb_db_type();
+
+	/*
+	 * If keyboard is US2(KB_LAYOUT_1), we need translate right ctrl
+	 * to backslash(\|) key.
+	 */
+	if (ec_cfg_keyboard_layout() == KB_LAYOUT_1)
+		set_scancode_set2(4, 0, get_scancode_set2(2, 7));
+}
+
+/* Called on AP S3 -> S0 transition */
+static void board_chipset_resume(void)
+{
+	/* Allow keyboard backlight to be enabled */
+
+	/* TODO(b/190783131)
+	 * Need to implement specific keyboard backlight control method.
+	 */
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S0 -> S3 transition */
+static void board_chipset_suspend(void)
+{
+	/* Turn off the keyboard backlight if it's on. */
+
+	/* TODO(b/190783131)
+	 * Need to implement specific keyboard backlight control method.
+	 */
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
+
+#ifdef CONFIG_CHARGE_RAMP_SW
+
+/*
+ * TODO(b/181508008): tune this threshold
+ */
+
+#define BC12_MIN_VOLTAGE 4400
+
+/**
+ * Return true if VBUS is too low
+ */
+int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
+{
+	int voltage;
+
+	if (charger_get_vbus_voltage(port, &voltage))
+		voltage = 0;
+
+	if (voltage == 0) {
+		CPRINTS("%s: must be disconnected", __func__);
+		return 1;
+	}
+
+	if (voltage < BC12_MIN_VOLTAGE) {
+		CPRINTS("%s: port %d: vbus %d lower than %d", __func__, port,
+			voltage, BC12_MIN_VOLTAGE);
+		return 1;
+	}
+
+	return 0;
+}
+
+#endif /* CONFIG_CHARGE_RAMP_SW */
+
+enum battery_present battery_hw_present(void)
+{
+	enum gpio_signal batt_pres;
+
+	batt_pres = GPIO_EC_BATT_PRES_ODL;
+
+	/* The GPIO is low when the battery is physically present */
+	return gpio_get_level(batt_pres) ? BP_NO : BP_YES;
+}
+
+static void board_init(void)
+{
+	/* The PPVAR_SYS must same as battery voltage(3 cells * 4.4V) */
+	if (extpower_is_present() && battery_hw_present()) {
+		bq25710_set_min_system_voltage(CHARGER_SOLO, 9200);
+	} else {
+		bq25710_set_min_system_voltage(CHARGER_SOLO, 13200);
+	}
+}
+DECLARE_HOOK(HOOK_SECOND, board_init, HOOK_PRIO_DEFAULT);
+
+__overridable void board_ps8xxx_tcpc_init(int port)
+{
+	int val;
+
+	if (i2c_read8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_P1_FLAGS,
+		      PS8815_REG_APTX_EQ_AT_10G, &val))
+		CPRINTS("ps8815: fail to read reg 0x%02x",
+			PS8815_REG_APTX_EQ_AT_10G);
+
+	/* APTX2 EQ 23dB, APTX1 EQ 23dB */
+	if (i2c_write8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_P1_FLAGS,
+		       PS8815_REG_APTX_EQ_AT_10G, 0x99))
+		CPRINTS("ps8815: fail to write reg 0x%02x",
+			PS8815_REG_APTX_EQ_AT_10G);
+
+	if (i2c_read8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_P1_FLAGS,
+		      PS8815_REG_RX_EQ_AT_10G, &val))
+		CPRINTS("ps8815: fail to read reg 0x%02x",
+			PS8815_REG_RX_EQ_AT_10G);
+
+	/* RX2 EQ 18dB, RX1 EQ 16dB */
+	if (i2c_write8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_P1_FLAGS,
+		       PS8815_REG_RX_EQ_AT_10G, 0x64))
+		CPRINTS("ps8815: fail to write reg 0x%02x",
+			PS8815_REG_RX_EQ_AT_10G);
+
+	if (i2c_read8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_P1_FLAGS,
+		      PS8815_REG_APTX_EQ_AT_5G, &val))
+		CPRINTS("ps8815: fail to read reg 0x%02x",
+			PS8815_REG_APTX_EQ_AT_5G);
+
+	/* APTX2 EQ 16dB, APTX1 EQ 16dB */
+	if (i2c_write8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_P1_FLAGS,
+		       PS8815_REG_APTX_EQ_AT_5G, 0x44))
+		CPRINTS("ps8815: fail to write reg 0x%02x",
+			PS8815_REG_APTX_EQ_AT_5G);
+
+	if (i2c_read8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_P1_FLAGS,
+		      PS8815_REG_RX_EQ_AT_5G, &val))
+		CPRINTS("ps8815: fail to read reg 0x%02x",
+			PS8815_REG_RX_EQ_AT_5G);
+
+	/* RX2 EQ 16dB, RX1 EQ 16dB */
+	if (i2c_write8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_P1_FLAGS,
+		       PS8815_REG_RX_EQ_AT_5G, 0x44))
+		CPRINTS("ps8815: fail to write reg 0x%02x",
+			PS8815_REG_RX_EQ_AT_5G);
+}
diff --git a/board/gimble/board.h b/board/gimble/board.h
new file mode 100644
index 0000000000..3fd3adcafa
--- /dev/null
+++ b/board/gimble/board.h
@@ -0,0 +1,266 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Brya board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "compile_time_macros.h"
+
+/* Baseboard features */
+#include "baseboard.h"
+
+/*
+ * This will happen automatically on NPCX9 ES2 and later. Do not remove
+ * until we can confirm all earlier chips are out of service.
+ */
+#define CONFIG_HIBERNATE_PSL_VCC1_RST_WAKEUP
+
+#define CONFIG_MP2964
+
+/* Sensors */
+/* BMA253 accelerometer in lid */
+#define CONFIG_ACCEL_BMA255
+
+#define CONFIG_ACCELGYRO_BMI160 /* Base accel/gyro */
+#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+/* BMA422 accelerometer in lid */
+#define CONFIG_ACCEL_BMA4XX
+
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel/gyro */
+#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+/* Sensors without hardware FIFO are in forced mode */
+#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
+
+/* Lid accel */
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_UPDATE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+
+/* Enable sensor fifo, must also define the _SIZE and _THRES */
+#define CONFIG_ACCEL_FIFO
+/* FIFO size is in power of 2. */
+#define CONFIG_ACCEL_FIFO_SIZE 256
+/* Depends on how fast the AP boots and typical ODRs */
+#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
+
+/* Sensor console commands */
+#define CONFIG_CMD_ACCELS
+#define CONFIG_CMD_ACCEL_INFO
+
+/* USB Type A Features */
+#define USB_PORT_COUNT 1
+#define CONFIG_USB_PORT_POWER_DUMB
+
+/* USB Type C and USB PD defines */
+#define CONFIG_IO_EXPANDER
+#define CONFIG_IO_EXPANDER_NCT38XX
+#define CONFIG_IO_EXPANDER_PORT_COUNT 1
+
+#define CONFIG_USB_PD_TCPM_PS8815
+#define CONFIG_USB_PD_TCPM_PS8815_FORCE_DID
+#undef CONFIG_USBC_RETIMER_INTEL_BB
+
+#define CONFIG_USBC_PPC_SYV682X
+#undef CONFIG_SYV682X_HV_ILIM
+#define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_5_50
+#define CONFIG_USBC_PPC_NX20P3483
+
+#define CONFIG_USB_PD_FRS
+#define CONFIG_USB_PD_FRS_PPC
+
+/* measure and check these values on gimble */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
+
+/* I2C speed console command */
+#define CONFIG_CMD_I2C_SPEED
+
+/* I2C control host command */
+#define CONFIG_HOSTCMD_I2C_CONTROL
+
+/*
+ * Passive USB-C cables only support up to 60W.
+ */
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
+
+/*
+ * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
+ * signal.
+ */
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
+
+/* System has back-lit keyboard */
+#define CONFIG_PWM_KBLIGHT
+
+/* Keyboard features */
+#define CONFIG_KEYBOARD_VIVALDI
+#define CONFIG_KEYBOARD_REFRESH_ROW3
+
+/* I2C Bus Configuration */
+
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+
+#define I2C_PORT_USB_C0_TCPC NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1
+
+#define I2C_PORT_USB_C0_PPC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT4_1
+
+#define I2C_PORT_USB_C0_BC12 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT4_1
+
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0
+
+/* define this to aviod error on CONFIG_ACCELGYRO_BMI_COMM_I2C */
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+
+#define I2C_ADDR_MP2964_FLAGS 0x20
+
+/* Disabling Thunderbolt-compatible mode */
+#undef CONFIG_USB_PD_TBT_COMPAT_MODE
+
+/* Enabling USB4 mode */
+#undef CONFIG_USB_PD_USB4
+
+/* Retimer */
+#undef CONFIG_USBC_RETIMER_FW_UPDATE
+
+/* Thermal features */
+#define CONFIG_FANS FAN_CH_COUNT
+#define CONFIG_THERMISTOR
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_TEMP_SENSOR_POWER
+#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
+
+/* LED defines */
+#define CONFIG_LED_ONOFF_STATES
+#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
+
+/*
+ * TODO(b/181271666): no fan control loop until sensors are tuned
+ */
+/* Fan features */
+#define CONFIG_CUSTOM_FAN_CONTROL
+
+/* Charger defines */
+#define CONFIG_CHARGER_BQ25720
+#define CONFIG_CHARGER_BQ25720_VSYS_TH2_CUSTOM
+#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV 70
+#define CONFIG_CHARGE_RAMP_SW
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10
+#define CONFIG_CHARGER_BQ25710_PSYS_SENSING
+/* OEM requested 10% derating */
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 10
+
+/* PROCHOT defines */
+#define BATT_MAX_CONTINUE_DISCHARGE_WATT 45
+
+/* Prochot assertion/deassertion ratios*/
+#define PROCHOT_ADAPTER_WATT_RATIO 97
+#define PROCHOT_ASSERTION_BATTERY_RATIO 95
+#define PROCHOT_DEASSERTION_BATTERY_RATIO 85
+#define PROCHOT_ASSERTION_PD_RATIO 104
+#define PROCHOT_DEASSERTION_PD_RATIO 94
+#define PROCHOT_DEASSERTION_PD_BATTERY_RATIO 95
+#define PROCHOT_ASSERTION_ADAPTER_RATIO 102
+#define PROCHOT_DEASSERTION_ADAPTER_RATIO 100
+#define PROCHOT_DEASSERTION_ADAPTER_BATT_RATIO 90
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h" /* needed by registers.h */
+#include "registers.h"
+#include "usbc_config.h"
+
+enum adc_channel {
+	ADC_TEMP_SENSOR_1_DDR_SOC,
+	ADC_TEMP_SENSOR_2_FAN,
+	ADC_TEMP_SENSOR_3_CHARGER,
+	ADC_IADPT,
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1_DDR_SOC,
+	TEMP_SENSOR_2_FAN,
+	TEMP_SENSOR_3_CHARGER,
+	TEMP_SENSOR_COUNT
+};
+
+enum sensor_id { LID_ACCEL = 0, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
+
+enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_PORT_COUNT };
+
+enum battery_type {
+	BATTERY_SIMPLO_HIGHPOWER,
+	BATTERY_COSMX,
+	BATTERY_TYPE_COUNT
+};
+
+enum pwm_channel {
+	PWM_CH_LED2 = 0, /* PWM0 (white charger) */
+	PWM_CH_LED3, /* PWM1 (orange on DB) */
+	PWM_CH_LED1, /* PWM2 (orange charger) */
+	PWM_CH_KBLIGHT, /* PWM3 */
+	PWM_CH_FAN, /* PWM5 */
+	PWM_CH_LED4, /* PWM7 (white on DB) */
+	PWM_CH_COUNT
+};
+
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT };
+
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT };
+
+void motion_interrupt(enum gpio_signal signal);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/gimble/build.mk b/board/gimble/build.mk
new file mode 100644
index 0000000000..cad0da2a4e
--- /dev/null
+++ b/board/gimble/build.mk
@@ -0,0 +1,26 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Brya board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx9
+CHIP_VARIANT:=npcx9m3f
+BASEBOARD:=brya
+
+board-y=
+board-y+=battery.o
+board-y+=board.o
+board-y+=charger.o
+board-y+=fans.o
+board-y+=fw_config.o
+board-y+=i2c.o
+board-y+=keyboard.o
+board-y+=led.o
+board-y+=pwm.o
+board-y+=sensors.o
+board-y+=thermal.o
+board-y+=usbc_config.o
diff --git a/board/gimble/charger.c b/board/gimble/charger.c
new file mode 100644
index 0000000000..827152e115
--- /dev/null
+++ b/board/gimble/charger.c
@@ -0,0 +1,82 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/charger/bq25710.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+#ifndef CONFIG_ZEPHYR
+/* Charger Chip Configuration */
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = BQ25710_SMBUS_ADDR1_FLAGS,
+		.drv = &bq25710_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CHARGER_NUM);
+#endif
+
+int board_set_active_charge_port(int port)
+{
+	int is_valid_port = board_is_usb_pd_port_present(port);
+	int i;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTSUSB("Disabling all charger ports");
+
+		/* Disable all ports. */
+		for (i = 0; i < ppc_cnt; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (ppc_vbus_sink_enable(i, 0))
+				CPRINTSUSB("Disabling C%d as sink failed.", i);
+		}
+
+		return EC_SUCCESS;
+	} else if (!is_valid_port) {
+		return EC_ERROR_INVAL;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (ppc_is_sourcing_vbus(port)) {
+		CPRINTFUSB("Skip enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTSUSB("New charge port: C%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < ppc_cnt; i++) {
+		if (i == port)
+			continue;
+
+		if (ppc_vbus_sink_enable(i, 0))
+			CPRINTSUSB("C%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTSUSB("C%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/board/gimble/ec.tasklist b/board/gimble/ec.tasklist
new file mode 100644
index 0000000000..27ab9a6e63
--- /dev/null
+++ b/board/gimble/ec.tasklist
@@ -0,0 +1,31 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ *
+ * USB_CHG_Px tasks must be contiguous (see USB_CHG_PORT_TO_TASK_ID(x)).
+ * PD_Cx tasks must be contiguous (see PD_PORT_TO_TASK_ID(x))
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, HOOKS_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, BASEBOARD_CHG_RAMP_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, BASEBOARD_CHARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, BASEBOARD_CHIPSET_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, CONSOLE_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, BASEBOARD_POWERBTN_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, BASEBOARD_PD_INT_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, BASEBOARD_PD_INT_TASK_STACK_SIZE) \
+	TASK_NOTEST(PROCHOT, prochot_task, NULL, VENTI_TASK_STACK_SIZE)
diff --git a/board/gimble/fans.c b/board/gimble/fans.c
new file mode 100644
index 0000000000..69d7542f37
--- /dev/null
+++ b/board/gimble/fans.c
@@ -0,0 +1,88 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Physical fans. These are logically separate from pwm_channels. */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "fan.h"
+#include "fan_chip.h"
+#include "hooks.h"
+#include "pwm.h"
+
+/* MFT channels. These are logically separate from pwm_channels. */
+const struct mft_t mft_channels[] = {
+	[MFT_CH_0] = {
+		.module = NPCX_MFT_MODULE_1,
+		.clk_src = TCKC_LFCLK,
+		.pwm_id = PWM_CH_FAN,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
+
+static const struct fan_conf fan_conf_0 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
+	.pgood_gpio = -1,
+	.enable_gpio = GPIO_EN_PP5000_FAN,
+};
+
+/*
+ * TOOD(b/180681346): need to update for real fan
+ *
+ * Prototype fan spins at about 7200 RPM at 100% PWM.
+ * Set minimum at around 30% PWM.
+ */
+static const struct fan_rpm fan_rpm_0 = {
+	.rpm_min = 2200,
+	.rpm_start = 2200,
+	.rpm_max = 7200,
+};
+
+const struct fan_t fans[FAN_CH_COUNT] = {
+	[FAN_CH_0] = {
+		.conf = &fan_conf_0,
+		.rpm = &fan_rpm_0,
+	},
+};
+
+#ifndef CONFIG_FANS
+
+/*
+ * TODO(b/181271666): use static fan speeds until fan and sensors are
+ * tuned. for now, use:
+ *
+ *   AP off:  33%
+ *   AP  on: 100%
+ */
+
+static void fan_slow(void)
+{
+	const int duty_pct = 33;
+
+	ccprints("%s: speed %d%%", __func__, duty_pct);
+
+	pwm_enable(PWM_CH_FAN, 1);
+	pwm_set_duty(PWM_CH_FAN, duty_pct);
+}
+
+static void fan_max(void)
+{
+	const int duty_pct = 100;
+
+	ccprints("%s: speed %d%%", __func__, duty_pct);
+
+	pwm_enable(PWM_CH_FAN, 1);
+	pwm_set_duty(PWM_CH_FAN, duty_pct);
+}
+
+DECLARE_HOOK(HOOK_INIT, fan_slow, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, fan_slow, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, fan_slow, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_RESET, fan_max, HOOK_PRIO_FIRST);
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, fan_max, HOOK_PRIO_DEFAULT);
+
+#endif /* CONFIG_FANS */
diff --git a/board/gimble/fw_config.c b/board/gimble/fw_config.c
new file mode 100644
index 0000000000..8698145efd
--- /dev/null
+++ b/board/gimble/fw_config.c
@@ -0,0 +1,65 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "fw_config.h"
+
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
+
+static union brya_cbi_fw_config fw_config;
+BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
+
+/*
+ * FW_CONFIG defaults for brya if the CBI.FW_CONFIG data is not
+ * initialized.
+ */
+static const union brya_cbi_fw_config fw_config_defaults = {
+	.usb_db = DB_USB3_PS8815,
+	.kb_bl = KEYBOARD_BACKLIGHT_ENABLED,
+};
+
+/****************************************************************************
+ * Brya FW_CONFIG access
+ */
+void board_init_fw_config(void)
+{
+	if (cbi_get_fw_config(&fw_config.raw_value)) {
+		CPRINTS("CBI: Read FW_CONFIG failed, using board defaults");
+		fw_config = fw_config_defaults;
+	}
+
+	if (get_board_id() == 0) {
+		/*
+		 * Early boards have a zero'd out FW_CONFIG, so replace
+		 * it with a sensible default value. If DB_USB_ABSENT2
+		 * was used as an alternate encoding of DB_USB_ABSENT to
+		 * avoid the zero check, then fix it.
+		 */
+		if (fw_config.raw_value == 0) {
+			CPRINTS("CBI: FW_CONFIG is zero, using board defaults");
+			fw_config = fw_config_defaults;
+		} else if (fw_config.usb_db == DB_USB_ABSENT2) {
+			fw_config.usb_db = DB_USB_ABSENT;
+		}
+	}
+}
+
+union brya_cbi_fw_config get_fw_config(void)
+{
+	return fw_config;
+}
+
+enum ec_cfg_keyboard_layout ec_cfg_keyboard_layout(void)
+{
+	return fw_config.kb_layout;
+}
+
+enum ec_cfg_usb_db_type ec_cfg_usb_db_type(void)
+{
+	return fw_config.usb_db;
+}
diff --git a/board/gimble/fw_config.h b/board/gimble/fw_config.h
new file mode 100644
index 0000000000..fcf24b4094
--- /dev/null
+++ b/board/gimble/fw_config.h
@@ -0,0 +1,66 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __BOARD_BRYA_FW_CONFIG_H_
+#define __BOARD_BRYA_FW_CONFIG_H_
+
+#include <stdint.h>
+
+/****************************************************************************
+ * CBI FW_CONFIG layout for Brya board.
+ *
+ * Source of truth is the project/brya/brya/config.star configuration file.
+ */
+
+enum ec_cfg_usb_db_type {
+	DB_USB_ABSENT = 0,
+	DB_USB3_PS8815 = 1,
+	DB_USB_ABSENT2 = 15
+};
+
+enum ec_cfg_keyboard_backlight_type {
+	KEYBOARD_BACKLIGHT_DISABLED = 0,
+	KEYBOARD_BACKLIGHT_ENABLED = 1
+};
+
+enum ec_cfg_keyboard_layout { KB_LAYOUT_DEFAULT = 0, KB_LAYOUT_1 = 1 };
+
+union brya_cbi_fw_config {
+	struct {
+		enum ec_cfg_usb_db_type usb_db : 4;
+		uint32_t sd_db : 2;
+		uint32_t reserved_0 : 1;
+		enum ec_cfg_keyboard_backlight_type kb_bl : 1;
+		uint32_t audio : 3;
+		uint32_t cellular_db : 2;
+		uint32_t wifi_sar_id : 1;
+		enum ec_cfg_keyboard_layout kb_layout : 2;
+		uint32_t reserved_1 : 16;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Read the cached FW_CONFIG.  Guaranteed to have valid values.
+ *
+ * @return the FW_CONFIG for the board.
+ */
+union brya_cbi_fw_config get_fw_config(void);
+
+/**
+ * Get keyboard type from FW_CONFIG.
+ *
+ * @return the keyboard type.
+ */
+enum ec_cfg_keyboard_layout ec_cfg_keyboard_layout(void);
+
+/**
+ * Get the USB daughter board type from FW_CONFIG.
+ *
+ * @return the USB daughter board type.
+ */
+enum ec_cfg_usb_db_type ec_cfg_usb_db_type(void);
+
+#endif /* __BOARD_BRYA_FW_CONFIG_H_ */
diff --git a/board/gimble/gpio.inc b/board/gimble/gpio.inc
new file mode 100644
index 0000000000..1961f1bcb4
--- /dev/null
+++ b/board/gimble/gpio.inc
@@ -0,0 +1,142 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define MODULE_KB		MODULE_KEYBOARD_SCAN
+
+/* INTERRUPT GPIOs: */
+GPIO_INT(ACOK_OD,                        PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
+GPIO_INT(EC_IMU_INT_R_L,                 PIN(5, 6), GPIO_SEL_1P8V | GPIO_INT_FALLING, motion_interrupt)
+GPIO_INT(EC_PROCHOT_IN_L,                PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
+GPIO_INT(EC_VOLDN_BTN_ODL,               PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(EC_VOLUP_BTN_ODL,               PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(EC_WP_ODL,                      PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(GSC_EC_PWR_BTN_ODL,             PIN(0, 1), GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW, power_button_interrupt)
+GPIO_INT(LID_OPEN,                       PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
+GPIO_INT(SEQ_EC_ALL_SYS_PG,              PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_DSW_PWROK,               PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_RSMRST_ODL,              PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,                       PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,                      PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SYS_SLP_S0IX_L,                 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(TABLET_MODE_L,                  PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
+GPIO_INT(USB_C0_BC12_INT_ODL,            PIN(C, 6), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C0_TCPC_INT_ODL,            PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C0_PPC_INT_ODL,             PIN(6, 2), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C1_BC12_INT_ODL,            PIN(5, 0), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C1_PPC_INT_ODL,             PIN(F, 5), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C1_TCPC_INT_ODL,            PIN(A, 2), GPIO_INT_FALLING, tcpc_alert_event)
+
+/* USED GPIOs: */
+GPIO(CCD_MODE_ODL,                   PIN(E, 5), GPIO_INPUT)
+GPIO(CHARGER_VAP_OTG_EN,             PIN(7, 3), GPIO_OUT_LOW)
+GPIO(CPU_C10_GATE_L,                 PIN(6, 7), GPIO_INPUT)
+GPIO(EC_BATT_PRES_ODL,               PIN(A, 3), GPIO_INPUT)
+GPIO(EC_ENTERING_RW,                 PIN(0, 3), GPIO_OUT_LOW)
+GPIO(EC_EN_EDP_BL,                   PIN(D, 3), GPIO_OUT_HIGH)
+GPIO(EC_GSC_PACKET_MODE,             PIN(7, 5), GPIO_OUT_LOW)
+GPIO(EC_I2C_BAT_SCL,                 PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_BAT_SDA,                 PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SCL_R,              PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SDA_R,              PIN(B, 2), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,              PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SENSOR_SDA,              PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_USB_C0_C2_PPC_BC_SCL,    PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_PPC_BC_SDA,    PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_TCPC_SCL,      PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_TCPC_SDA,      PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_MIX_SCL,          PIN(E, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_MIX_SDA,          PIN(E, 3), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_TCPC_SCL,         PIN(F, 3), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_TCPC_SDA,         PIN(F, 2), GPIO_INPUT)
+GPIO(EC_KB_LOCK,                     PIN(0, 4), GPIO_INPUT)
+GPIO(EC_PCHHOT_ODL,                  PIN(7, 4), GPIO_INPUT)
+GPIO(EC_PCH_INT_ODL,                 PIN(B, 0), GPIO_ODR_HIGH)
+GPIO(EC_PCH_PWR_BTN_ODL,             PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(EC_PCH_RSMRST_L,                PIN(A, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_RTCRST,                  PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_SYS_PWROK,               PIN(3, 7), GPIO_OUT_LOW)
+GPIO(EC_PCH_WAKE_R_ODL,              PIN(C, 0), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_ODL,                 PIN(6, 3), GPIO_ODR_HIGH)
+GPIO(EN_PP5000_FAN,                  PIN(6, 1), GPIO_OUT_HIGH)
+GPIO(EN_PP5000_USBA_R,               PIN(D, 7), GPIO_OUT_LOW)
+GPIO(EN_S5_RAILS,                    PIN(E, 1), GPIO_OUT_LOW)
+GPIO(IMVP9_VRRDY_OD,                 PIN(4, 3), GPIO_INPUT)
+GPIO(PCH_PWROK,                      PIN(7, 2), GPIO_OUT_LOW)
+GPIO(POWER_LED_GATE,		         PIN(B, 6), GPIO_OUT_LOW)	/* Power LED: White */
+GPIO(SYS_RST_ODL,                    PIN(C, 5), GPIO_ODR_HIGH)
+GPIO(USB_C0_TCPC_RST_ODL,            PIN(A, 7), GPIO_ODR_LOW)
+GPIO(USB_C1_FRS_EN,                  PIN(9, 4), GPIO_INPUT)
+GPIO(USB_C1_RT_RST_R_ODL,            PIN(0, 2), GPIO_ODR_HIGH)
+GPIO(VCCST_PWRGD_OD,                 PIN(A, 4), GPIO_ODR_LOW)
+
+/* UART alternate functions */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)              /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */
+
+/* I2C alternate functions */
+ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)               /* GPIO33/I2C5_SCL0/CTS_L, GPIO36/RTS_L/I2C5_SDA0 */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)               /* GPIO87/I2C1_SDA0 */
+ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)               /* GPIO92/I2C2_SCL0, GPIO91/I2C2_SDA0, GPIO90/I2C1_SCL0 */
+ALTERNATE(PIN_MASK(B, 0x0c), 0, MODULE_I2C, 0)               /* GPIOB3/I2C7_SCL0/DCD_L, GPIOB2/I2C7_SDA0/DSR_L */
+ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, GPIO_SEL_1P8V)   /* GPIOB5/I2C0_SCL0, GPIOB4/I2C0_SDA0 */
+ALTERNATE(PIN_MASK(E, 0x18), 0, MODULE_I2C, 0)               /* GPIOE4/I2C6_SCL1/I3C_SCL, GPIOE3/I2C6_SDA1/I3C_SDA */
+ALTERNATE(PIN_MASK(F, 0x0c), 0, MODULE_I2C, 0)               /* GPIOF3/I2C4_SCL1, GPIOF2/I2C4_SDA1 */
+
+/* PWM alternate functions */
+ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0)               /* GPIO40/TA1 */
+ALTERNATE(PIN_MASK(6, 0x01), 0, MODULE_PWM, 0)               /* GPIO60/PWM7 */
+ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)               /* GPIO80/PWM3 */
+ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)               /* GPIOB7/PWM5 */
+ALTERNATE(PIN_MASK(C, 0x1c), 0, MODULE_PWM, 0)               /* GPIOC4/PWM2, GPIOC3/PWM0, GPIOC2/PWM1/I2C6_SCL0 */
+
+/* ADC alternate functions */
+ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0)               /* GPIO34/PS2_DAT2/ADC6 */
+ALTERNATE(PIN_MASK(4, 0x34), 0, MODULE_ADC, 0)               /* GPIO42/ADC3/RI_L, GPIO45/ADC0, GPIO44/ADC1 */
+
+/* KB alternate functions */
+ALTERNATE(PIN_MASK(0, 0xf0), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO10&P80_CLK/GPIO07, KSO11&P80_DAT/GPIO06, KSO12/GPIO05, KSO13/GPIO04 */
+ALTERNATE(PIN_MASK(1, 0x7f), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO06/GPO13/GP_SEL_L, KSO07/GPO12/JEN_L, KSO03/GPIO16/JTAG_TDO0_SWO, KSO04/GPIO15/XNOR, KSO05/GPIO14, KSO08/GPIO11/CR_SOUT1, KSO09/GPIO10/CR_SIN1 */
+ALTERNATE(PIN_MASK(2, 0xfc), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI2/GPIO27/TRACEDATA1, KSI3/GPIO26/TRACEDATA0, KSI4/GPIO25/TRACECLK/GP_SCLK, KSI5/GPIO24/GP_MISO, KSI6/GPIO23/S_SBUB, KSI7/GPIO22/S_SBUA */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO00/GPIO21/JTAG_TCK_SWCLK, KSO01/GPIO20/JTAG_TMS_SWIO */
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI0/GPIO31/TRACEDATA3/GP_MOSI, KSI1/GPIO30/TRACEDATA2/GP_CS_L */
+
+/* PMU alternate functions */
+ALTERNATE(PIN_MASK(0, 0x01), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN2_L&GPI00/GPIO00 */
+ALTERNATE(PIN_MASK(0, 0x02), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW) /* GPIO01/PSL_IN3_L&GPI01 */
+ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN1_L&GPID2/GPIOD2 */
+
+/* Unused Pins */
+UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
+UNUSED(PIN(3, 2))       /* GPO32/TRIS_L */
+UNUSED(PIN(3, 5))       /* GPO35/CR_SOUT4/TEST_L */
+UNUSED(PIN(6, 6))       /* GPO66/ARM_L_x86 */
+UNUSED(PIN(8, 6))       /* GPIO86/TXD/CR_SOUT2 */
+UNUSED(PIN(D, 4))       /* GPIOD4/CR_SIN3 */
+UNUSED(PIN(D, 1))       /* GPIOD1/I2C3_SCL0 */
+UNUSED(PIN(D, 0))       /* GPIOD0/I2C3_SDA0 */
+UNUSED(PIN(8, 3))       /* KSO15/GPIO83 */
+UNUSED(PIN(B, 1))       /* KSO17/GPIOB1/CR_SIN4 */
+UNUSED(PIN(4, 1))       /* GPIO41/ADC4 */
+UNUSED(PIN(A, 0))       /* F_CS0_L/GPIOA0 */
+UNUSED(PIN(9, 6))       /* F_DIO1/GPIO96 */
+UNUSED(PIN(7, 0))       /* GPIO70/PS2_DAT0 */
+UNUSED(PIN(8, 1))       /* PECI DATA/GPIO81 */
+UNUSED(PIN(5, 7))       /* GPIO57/SER_IRQ/ESPI_ALERT_L */
+UNUSED(PIN(8, 2))       /* KSO14/GPIO82 */
+
+/* Pre-configured PSL balls:  J8  K6 */
+
+
+/*
+ * The NPCX keyboard driver does not use named GPIOs to access
+ * keyboard scan pins, so we do not list them in *gpio.inc. However, when
+ * KEYBOARD_COL2_INVERTED is defined, this name is required.
+ */
+GPIO(EC_KSO_02_INV,               PIN(1, 7), GPIO_OUT_LOW)
+
+IOEX(USB_C0_RT_RST_ODL,      EXPIN(IOEX_C0_NCT38XX, 0, 2), GPIO_ODR_LOW)
+IOEX(USB_C0_OC_ODL,          EXPIN(IOEX_C0_NCT38XX, 0, 4), GPIO_ODR_HIGH)
+IOEX(USB_C0_FRS_EN,          EXPIN(IOEX_C0_NCT38XX, 0, 6), GPIO_OUT_LOW)
diff --git a/board/gimble/i2c.c b/board/gimble/i2c.c
new file mode 100644
index 0000000000..621e7bf3f0
--- /dev/null
+++ b/board/gimble/i2c.c
@@ -0,0 +1,62 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "i2c.h"
+
+/* I2C port map configuration */
+const struct i2c_port_t i2c_ports[] = {
+	{
+		/* I2C0 */
+		.name = "sensor",
+		.port = I2C_PORT_SENSOR,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_SENSOR_SCL,
+		.sda = GPIO_EC_I2C_SENSOR_SDA,
+	},
+	{
+		/* I2C1 */
+		.name = "tcpc0",
+		.port = I2C_PORT_USB_C0_TCPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C2_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C2_TCPC_SDA,
+	},
+	{
+		/* I2C2 */
+		.name = "ppc0",
+		.port = I2C_PORT_USB_C0_PPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C2_PPC_BC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C2_PPC_BC_SDA,
+	},
+	{
+		/* I2C4 C1 TCPC */
+		.name = "tcpc1",
+		.port = I2C_PORT_USB_C1_TCPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C1_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C1_TCPC_SDA,
+		.flags = I2C_PORT_FLAG_DYNAMIC_SPEED,
+	},
+	{
+		/* I2C5 */
+		.name = "battery",
+		.port = I2C_PORT_BATTERY,
+		.kbps = 100,
+		.scl = GPIO_EC_I2C_BAT_SCL,
+		.sda = GPIO_EC_I2C_BAT_SDA,
+	},
+	{
+		/* I2C7 */
+		.name = "eeprom",
+		.port = I2C_PORT_EEPROM,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_MISC_SCL_R,
+		.sda = GPIO_EC_I2C_MISC_SDA_R,
+	},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/board/gimble/keyboard.c b/board/gimble/keyboard.c
new file mode 100644
index 0000000000..e1b0ca8a21
--- /dev/null
+++ b/board/gimble/keyboard.c
@@ -0,0 +1,51 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "ec_commands.h"
+#include "keyboard_scan.h"
+#include "timer.h"
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/* Increase from 50 us, because KSO_02 passes through the H1. */
+	.output_settle_us = 80,
+	/* Other values should be the same as the default configuration. */
+	.debounce_down_us = 9 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x1c, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
+		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
+	},
+};
+
+static const struct ec_response_keybd_config gimble_kb = {
+	.num_top_row_keys = 13,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_KBD_BKLIGHT_TOGGLE,	/* T8 */
+		TK_PLAY_PAUSE,		/* T9 */
+		TK_MICMUTE,		/* T10 */
+		TK_VOL_MUTE,		/* T11 */
+		TK_VOL_DOWN,		/* T12 */
+		TK_VOL_UP,		/* T13 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &gimble_kb;
+}
diff --git a/board/gimble/led.c b/board/gimble/led.c
new file mode 100644
index 0000000000..b56ccbbdca
--- /dev/null
+++ b/board/gimble/led.c
@@ -0,0 +1,173 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+#include "pwm.h"
+#include "util.h"
+
+#include <stdint.h>
+
+#define BAT_LED_ON_LVL 100
+#define BAT_LED_OFF_LVL 0
+
+#define PWR_LED_ON_LVL 1
+#define PWR_LED_OFF_LVL 0
+
+#define LED_SIDESEL_MB_PORT 0
+#define LED_SIDESEL_DB_PORT 1
+
+__override const int led_charge_lvl_1 = 5;
+__override const int led_charge_lvl_2 = 95;
+
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    0.5 * LED_ONE_SEC },
+					  { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 1 * LED_ONE_SEC } },
+	};
+
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_BATTERY_LED,
+	EC_LED_ID_POWER_LED,
+};
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	int port;
+
+	/* There are four battery leds, LED1/LED2 are on MB side and
+	 * LED3/LED4 are on DB side. All leds are OFF by default.
+	 */
+	int led1_duty, led2_duty, led3_duty, led4_duty;
+
+	led1_duty = led2_duty = led3_duty = led4_duty = BAT_LED_OFF_LVL;
+
+	/* Check which port is the charging port,
+	 * and turn on the corresponding led.
+	 */
+	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
+		port = charge_manager_get_active_charge_port();
+		switch (port) {
+		case LED_SIDESEL_MB_PORT:
+			switch (color) {
+			case EC_LED_COLOR_AMBER:
+				led1_duty = BAT_LED_ON_LVL;
+				break;
+			case EC_LED_COLOR_WHITE:
+				led2_duty = BAT_LED_ON_LVL;
+				break;
+			default: /* LED_OFF and other unsupported colors */
+				break;
+			}
+			break;
+		case LED_SIDESEL_DB_PORT:
+			switch (color) {
+			case EC_LED_COLOR_AMBER:
+				led3_duty = BAT_LED_ON_LVL;
+				break;
+			case EC_LED_COLOR_WHITE:
+				led4_duty = BAT_LED_ON_LVL;
+				break;
+			default: /* LED_OFF and other unsupported colors */
+				break;
+			}
+			break;
+		default: /* Unknown charging port */
+			break;
+		}
+	} else {
+		switch (color) {
+		case EC_LED_COLOR_AMBER:
+			led1_duty = BAT_LED_ON_LVL;
+			led3_duty = BAT_LED_ON_LVL;
+			break;
+		case EC_LED_COLOR_WHITE:
+			led2_duty = BAT_LED_ON_LVL;
+			led4_duty = BAT_LED_ON_LVL;
+			break;
+		default: /* LED_OFF and other unsupported colors */
+			break;
+		}
+	}
+
+	pwm_set_duty(PWM_CH_LED1, led1_duty);
+	pwm_set_duty(PWM_CH_LED2, led2_duty);
+	pwm_set_duty(PWM_CH_LED3, led3_duty);
+	pwm_set_duty(PWM_CH_LED4, led4_duty);
+}
+
+__override void led_set_color_power(enum ec_led_colors color)
+{
+	if (color == EC_LED_COLOR_WHITE)
+		gpio_set_level(GPIO_POWER_LED_GATE, PWR_LED_ON_LVL);
+	else
+		/* LED_OFF and unsupported colors */
+		gpio_set_level(GPIO_POWER_LED_GATE, PWR_LED_OFF_LVL);
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		led_auto_control(led_id, 0);
+		if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(EC_LED_COLOR_AMBER);
+		else if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_battery(EC_LED_COLOR_WHITE);
+		else if (brightness[LED_OFF] != 0)
+			led_set_color_battery(LED_OFF);
+		else {
+			led_auto_control(led_id, 1);
+			led_set_color_battery(LED_OFF);
+		}
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_power(EC_LED_COLOR_WHITE);
+		else
+			led_set_color_power(LED_OFF);
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/board/gimble/pwm.c b/board/gimble/pwm.c
new file mode 100644
index 0000000000..9f9a8ed94f
--- /dev/null
+++ b/board/gimble/pwm.c
@@ -0,0 +1,70 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "chipset.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "hooks.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_LED2] = {
+		.channel = 0,
+		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+		.freq = 4800,
+	},
+	[PWM_CH_LED3] = {
+		.channel = 1,
+		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+		.freq = 4800,
+	},
+	[PWM_CH_LED1] = {
+		.channel = 2,
+		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+		.freq = 4800,
+	},
+	[PWM_CH_KBLIGHT] = {
+		.channel = 3,
+		.flags = 0,
+		/*
+		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
+		 * flicker. Higher frequencies consume similar average power to
+		 * lower PWM frequencies, but higher frequencies record a much
+		 * lower maximum power.
+		 */
+		.freq = 2400,
+	},
+	[PWM_CH_FAN] = {
+		.channel = 5,
+		.flags = PWM_CONFIG_OPEN_DRAIN,
+		.freq = 25000
+	},
+	[PWM_CH_LED4] = {
+		.channel = 7,
+		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+		.freq = 4800,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+static void board_pwm_init(void)
+{
+	/* Turn off LED1 to LED4 */
+	pwm_enable(PWM_CH_LED1, 1);
+	pwm_set_duty(PWM_CH_LED1, 0);
+	pwm_enable(PWM_CH_LED2, 1);
+	pwm_set_duty(PWM_CH_LED2, 0);
+	pwm_enable(PWM_CH_LED3, 1);
+	pwm_set_duty(PWM_CH_LED3, 0);
+	pwm_enable(PWM_CH_LED4, 1);
+	pwm_set_duty(PWM_CH_LED4, 0);
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return;
+	/* Turn on KB LED at 50%. */
+	pwm_enable(PWM_CH_KBLIGHT, 1);
+	pwm_set_duty(PWM_CH_KBLIGHT, 50);
+}
+DECLARE_HOOK(HOOK_INIT, board_pwm_init, HOOK_PRIO_DEFAULT);
diff --git a/board/gimble/sensors.c b/board/gimble/sensors.c
new file mode 100644
index 0000000000..0f415f168f
--- /dev/null
+++ b/board/gimble/sensors.c
@@ -0,0 +1,387 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "accelgyro.h"
+#include "adc_chip.h"
+#include "common.h"
+#include "driver/accel_bma2x2.h"
+#include "driver/accel_bma2x2_public.h"
+#include "driver/accel_bma422.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "driver/accelgyro_lsm6dsm.h"
+#include "driver/tcpm/ps8xxx_public.h"
+#include "driver/tcpm/tcpci.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "keyboard_scan.h"
+#include "motion_sense.h"
+#include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
+#include "thermal.h"
+
+/* ADC configuration */
+const struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_1_DDR_SOC] = {
+		.name = "TEMP_DDR_SOC",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_2_FAN] = {
+		.name = "TEMP_FAN",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_3_CHARGER] = {
+		.name = "TEMP_CHARGER",
+		.input_ch = NPCX_ADC_CH6,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_IADPT] = {
+		.name = "CHARGER_IADPT",
+		.input_ch = NPCX_ADC_CH3,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+K_MUTEX_DEFINE(g_lid_accel_mutex);
+K_MUTEX_DEFINE(g_base_accel_mutex);
+/* BMA253 private data */
+static struct accelgyro_saved_data_t g_bma253_data;
+
+/* BMI160 private data */
+static struct bmi_drv_data_t g_bmi160_data;
+
+/* LSM6DSM private data */
+static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
+
+/* BMA422 private data */
+static struct accelgyro_saved_data_t g_bma422_data;
+
+/* TODO(b/192477578): calibrate the orientation matrix on later board stage */
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					     { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
+
+static const mat33_fp_t lid_standard_ref_id_1 = { { 0, FLOAT_TO_FP(1), 0 },
+						  { FLOAT_TO_FP(1), 0, 0 },
+						  { 0, 0, FLOAT_TO_FP(-1) } };
+
+/* TODO(b/192477578): calibrate the orientation matrix on later board stage */
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, FLOAT_TO_FP(-1), 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
+
+static const mat33_fp_t base_standard_ref_id_1 = { { 0, FLOAT_TO_FP(1), 0 },
+						   { FLOAT_TO_FP(-1), 0, 0 },
+						   { 0, 0, FLOAT_TO_FP(1) } };
+
+struct motion_sensor_t motion_sensors[] = {
+	[LID_ACCEL] = {
+		.name = "Lid Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMA255,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &bma2x2_accel_drv,
+		.mutex = &g_lid_accel_mutex,
+		.drv_data = &g_bma253_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR2_FLAGS,
+		.rot_standard_ref = &lid_standard_ref,
+		.min_frequency = BMA255_ACCEL_MIN_FREQ,
+		.max_frequency = BMA255_ACCEL_MAX_FREQ,
+		.default_range = 2, /* g, to support tablet mode */
+		.config = {
+			/* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+			/* Sensor on in S3 */
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+		},
+	},
+
+	[BASE_ACCEL] = {
+		.name = "Base Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMI160,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &bmi160_drv,
+		.mutex = &g_base_accel_mutex,
+		.drv_data = &g_bmi160_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = BMI_ACCEL_MIN_FREQ,
+		.max_frequency = BMI_ACCEL_MAX_FREQ,
+		.default_range = 4, /* g */
+		.config = {
+			/* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+			/* Sensor on in S3 */
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+		},
+	},
+
+	[BASE_GYRO] = {
+		.name = "Base Gyro",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMI160,
+		.type = MOTIONSENSE_TYPE_GYRO,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &bmi160_drv,
+		.mutex = &g_base_accel_mutex,
+		.drv_data = &g_bmi160_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+		.default_range = 1000, /* dps */
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = BMI_GYRO_MIN_FREQ,
+		.max_frequency = BMI_GYRO_MAX_FREQ,
+	},
+};
+const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+struct motion_sensor_t bma422_lid_accel = {
+	.name = "Lid Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_BMA422,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_LID,
+	.drv = &bma4_accel_drv,
+	.mutex = &g_lid_accel_mutex,
+	.drv_data = &g_bma422_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = BMA4_I2C_ADDR_SECONDARY,
+	.rot_standard_ref = &lid_standard_ref_id_1,
+	.min_frequency = BMA4_ACCEL_MIN_FREQ,
+	.max_frequency = BMA4_ACCEL_MAX_FREQ,
+	.default_range = 2, /* g, enough for laptop. */
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 12500 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+		/* Sensor on in S3 */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 12500 | ROUND_UP_FLAG,
+			.ec_rate = 0,
+		},
+	},
+};
+
+struct motion_sensor_t lsm6dsm_base_accel = {
+	.name = "Base Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_LSM6DSM,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &lsm6dsm_drv,
+	.mutex = &g_base_accel_mutex,
+	.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
+			MOTIONSENSE_TYPE_ACCEL),
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
+	.rot_standard_ref = &base_standard_ref_id_1,
+	.default_range = 4,  /* g */
+	.min_frequency = LSM6DSM_ODR_MIN_VAL,
+	.max_frequency = LSM6DSM_ODR_MAX_VAL,
+	.config = {
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 13000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+	},
+};
+
+struct motion_sensor_t lsm6dsm_base_gyro = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_LSM6DSM,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &lsm6dsm_drv,
+	.mutex = &g_base_accel_mutex,
+	.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
+			MOTIONSENSE_TYPE_GYRO),
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
+	.default_range = 1000 | ROUND_UP_FLAG, /* dps */
+	.rot_standard_ref = &base_standard_ref_id_1,
+	.min_frequency = LSM6DSM_ODR_MIN_VAL,
+	.max_frequency = LSM6DSM_ODR_MAX_VAL,
+	.config = {
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 13000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+	},
+};
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	if (get_board_id() >= 1)
+		lsm6dsm_interrupt(signal);
+	else
+		bmi160_interrupt(signal);
+}
+
+static void update_sensor_array(void)
+{
+	if (get_board_id() >= 1) {
+		motion_sensors[LID_ACCEL] = bma422_lid_accel;
+		motion_sensors[BASE_ACCEL] = lsm6dsm_base_accel;
+		motion_sensors[BASE_GYRO] = lsm6dsm_base_gyro;
+		ccprints("LID ACCEL is BMA422");
+		ccprints("BASE IMU is LSM6DSM");
+	} else {
+		ccprints("LID ACCEL is BMA253");
+		ccprints("BASE IMU is BMI160");
+	}
+}
+DECLARE_HOOK(HOOK_INIT, update_sensor_array, HOOK_PRIO_INIT_I2C);
+
+static void baseboard_sensors_init(void)
+{
+	/* Enable gpio interrupt for base accelgyro sensor */
+	gpio_enable_interrupt(GPIO_EC_IMU_INT_R_L);
+}
+DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_INIT_I2C + 1);
+
+/* Temperature sensor configuration */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1_DDR_SOC] = { .name = "DDR and SOC",
+				    .type = TEMP_SENSOR_TYPE_BOARD,
+				    .read = get_temp_3v3_30k9_47k_4050b,
+				    .idx = ADC_TEMP_SENSOR_1_DDR_SOC },
+	[TEMP_SENSOR_2_FAN] = { .name = "Fan",
+				.type = TEMP_SENSOR_TYPE_BOARD,
+				.read = get_temp_3v3_30k9_47k_4050b,
+				.idx = ADC_TEMP_SENSOR_2_FAN },
+	[TEMP_SENSOR_3_CHARGER] = { .name = "Charger",
+				    .type = TEMP_SENSOR_TYPE_BOARD,
+				    .read = get_temp_3v3_30k9_47k_4050b,
+				    .idx = ADC_TEMP_SENSOR_3_CHARGER },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/*
+ * TODO(b/194318801): confirm thermal limits setting for gimble
+ *
+ * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
+ * 130 C.  However, sensor is located next to DDR, so we need to use the lower
+ * DDR temperature limit (85 C)
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
+
+/*
+ * TODO(b/194318801): confirm thermal limits setting for gimble
+ *
+ * Inductor limits - used for both charger and PP3300 regulator
+ *
+ * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
+ *
+ * Charger max recommended temperature 100C, max absolute temperature 125C
+ * PP3300 regulator: operating range -40 C to 145 C
+ *
+ * Inductors: limit of 125c
+ * PCB: limit is 80c
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_INDUCTOR         \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_inductor =
+	THERMAL_INDUCTOR;
+
+#define THERMAL_FAN_MISSING      \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(100), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_fan_missing =
+	THERMAL_FAN_MISSING;
+
+/* this should really be "const" */
+struct ec_thermal_config thermal_params[] = {
+	[TEMP_SENSOR_1_DDR_SOC] = THERMAL_CPU,
+	/* TODO(b/194318801): confirm thermal limits setting for gimble */
+	[TEMP_SENSOR_2_FAN] = THERMAL_INDUCTOR,
+	[TEMP_SENSOR_3_CHARGER] = THERMAL_INDUCTOR,
+};
+
+struct ec_thermal_config temp_sensor_2_fan_set[] = {
+	[TEMP_SENSOR_2_FAN] = THERMAL_FAN_MISSING,
+};
+
+static void config_thermal_params(void)
+{
+	int rv, val;
+
+	rv = tcpc_addr_read16_no_lpm_exit(USBC_PORT_C1, PS8XXX_I2C_ADDR1_FLAGS,
+					  TCPC_REG_VENDOR_ID, &val);
+
+	if (rv != 0) {
+		thermal_params[TEMP_SENSOR_2_FAN] =
+			temp_sensor_2_fan_set[TEMP_SENSOR_2_FAN];
+	}
+}
+DECLARE_HOOK(HOOK_INIT, config_thermal_params, HOOK_PRIO_INIT_I2C + 1);
+
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
diff --git a/board/gimble/thermal.c b/board/gimble/thermal.c
new file mode 100644
index 0000000000..37184f92f2
--- /dev/null
+++ b/board/gimble/thermal.c
@@ -0,0 +1,156 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "fan.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "tablet_mode.h"
+#include "temp_sensor.h"
+#include "thermal.h"
+#include "util.h"
+/* Console output macros */
+#define CPUTS(outstr) cputs(CC_THERMAL, outstr)
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
+
+struct fan_step {
+	/*
+	 * Sensor 1~4 trigger point, set -1 if we're not using this
+	 * sensor to determine fan speed.
+	 */
+	int8_t on[TEMP_SENSOR_COUNT];
+	/*
+	 * Sensor 1~4 trigger point, set -1 if we're not using this
+	 * sensor to determine fan speed.
+	 */
+	int8_t off[TEMP_SENSOR_COUNT];
+	/* Fan rpm */
+	uint16_t rpm[FAN_CH_COUNT];
+	/* Fan rpm for tablet mode */
+	uint16_t rpm_tablet[FAN_CH_COUNT];
+};
+/*
+ * TODO(b/167931578) Only monitor sensor3 for now.
+ * Will add more sensors support if needed.
+ */
+static const struct fan_step fan_table[] = {
+	{
+		/* level 0 */
+		.on = { 43, -1, -1 },
+		.off = { 0, -1, -1 },
+		.rpm = { 0 },
+		.rpm_tablet = { 0 },
+	},
+	{
+		/* level 1 */
+		.on = { 45, -1, -1 },
+		.off = { 43, -1, -1 },
+		.rpm = { 3400 },
+		.rpm_tablet = { 3400 },
+	},
+	{
+		/* level 2 */
+		.on = { 46, -1, -1 },
+		.off = { 44, -1, -1 },
+		.rpm = { 3800 },
+		.rpm_tablet = { 3700 },
+	},
+	{
+		/* level 3 */
+		.on = { 48, -1, -1 },
+		.off = { 45, -1, -1 },
+		.rpm = { 4200 },
+		.rpm_tablet = { 4100 },
+	},
+	{
+		/* level 4 */
+		.on = { 50, -1, -1 },
+		.off = { 47, -1, -1 },
+		.rpm = { 4800 },
+		.rpm_tablet = { 4800 },
+	},
+	{
+		/* level 5 */
+		.on = { 52, -1, -1 },
+		.off = { 49, -1, -1 },
+		.rpm = { 5400 },
+		.rpm_tablet = { 5200 },
+	},
+};
+const int num_fan_levels = ARRAY_SIZE(fan_table);
+
+int fan_table_to_rpm(int fan, int *temp, enum temp_sensor_id temp_sensor)
+{
+	/* current fan level */
+	static int current_level;
+	/* previous fan level */
+	static int prev_current_level;
+
+	/* previous sensor temperature */
+	static int prev_temp[TEMP_SENSOR_COUNT];
+	int i;
+	int new_rpm = 0;
+
+	/*
+	 * Compare the current and previous temperature, we have
+	 * the three paths :
+	 *  1. decreasing path. (check the release point)
+	 *  2. increasing path. (check the trigger point)
+	 *  3. invariant path. (return the current RPM)
+	 */
+	if (temp[temp_sensor] < prev_temp[temp_sensor]) {
+		for (i = current_level; i > 0; i--) {
+			if (temp[temp_sensor] < fan_table[i].off[temp_sensor])
+				current_level = i - 1;
+			else
+				break;
+		}
+	} else if (temp[temp_sensor] > prev_temp[temp_sensor]) {
+		for (i = current_level; i < num_fan_levels; i++) {
+			if (temp[temp_sensor] >= fan_table[i].on[temp_sensor])
+				current_level = i;
+			else
+				break;
+		}
+	}
+	if (current_level < 0)
+		current_level = 0;
+
+	if (current_level != prev_current_level) {
+		CPRINTS("temp: %d, prev_temp: %d", temp[temp_sensor],
+			prev_temp[temp_sensor]);
+		CPRINTS("current_level: %d", current_level);
+	}
+
+	prev_temp[temp_sensor] = temp[temp_sensor];
+	prev_current_level = current_level;
+
+	switch (fan) {
+	case FAN_CH_0:
+		if (tablet_get_mode())
+			new_rpm = fan_table[current_level].rpm_tablet[FAN_CH_0];
+		else
+			new_rpm = fan_table[current_level].rpm[FAN_CH_0];
+		break;
+	default:
+		break;
+	}
+	return new_rpm;
+}
+void board_override_fan_control(int fan, int *temp)
+{
+	if (chipset_in_state(CHIPSET_STATE_ON)) {
+		fan_set_rpm_mode(FAN_CH(fan), 1);
+		fan_set_rpm_target(FAN_CH(fan),
+				   fan_table_to_rpm(FAN_CH(fan), temp,
+						    TEMP_SENSOR_1_DDR_SOC));
+	} else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
+		/* Stop fan when enter S0ix */
+		fan_set_rpm_mode(FAN_CH(fan), 1);
+		fan_set_rpm_target(FAN_CH(fan), 0);
+	}
+}
diff --git a/board/gimble/usbc_config.c b/board/gimble/usbc_config.c
new file mode 100644
index 0000000000..c566cbdcf6
--- /dev/null
+++ b/board/gimble/usbc_config.c
@@ -0,0 +1,279 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/bc12/pi3usb9201_public.h"
+#include "driver/ppc/nx20p348x.h"
+#include "driver/ppc/syv682x_public.h"
+#include "driver/tcpm/nct38xx.h"
+#include "driver/tcpm/ps8xxx.h"
+#include "driver/tcpm/ps8xxx_public.h"
+#include "driver/tcpm/tcpci.h"
+#include "ec_commands.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "ioexpander.h"
+#include "system.h"
+#include "task.h"
+#include "task_id.h"
+#include "timer.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+/* USBC TCPC configuration */
+const struct tcpc_config_t tcpc_config[] = {
+	[USBC_PORT_C0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0_TCPC,
+			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+	},
+	[USBC_PORT_C1] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C1_TCPC,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
+			 TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V |
+			 TCPC_FLAGS_CONTROL_VCONN |
+			 TCPC_FLAGS_CONTROL_FRS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
+BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
+
+/* USBC PPC configuration */
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_PPC,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.frs_en = IOEX_USB_C0_FRS_EN,
+		.drv = &syv682x_drv,
+	},
+	[USBC_PORT_C1] = {
+		/* Compatible with Silicon Mitus SM536A0 */
+		.i2c_port = I2C_PORT_USB_C1_PPC,
+		.i2c_addr_flags = NX20P3483_ADDR2_FLAGS,
+		.drv = &nx20p348x_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
+
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/*
+ * USB3 DB mux configuration - the top level mux still needs to be set
+ * to the virtual_usb_mux_driver so the AP gets notified of mux changes
+ * and updates the TCSS configuration on state changes.
+ */
+static const struct usb_mux_chain usbc1_usb3_db_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
+	.next = NULL,
+};
+
+/* USBC mux configuration - Alder Lake includes internal mux */
+const struct usb_mux_chain usb_muxes[] = {
+	[USBC_PORT_C0] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+	},
+	[USBC_PORT_C1] = {
+		.mux = &(const struct usb_mux) {
+			/* PS8815 DB */
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc1_usb3_db_retimer,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
+
+/* BC1.2 charger detect configuration */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C1_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
+
+/*
+ * ioex_init() is normally called before we take the TCPCs out of
+ * reset, so we need to start in disabled mode, then explicitly
+ * call ioex_init().
+ */
+
+struct ioexpander_config_t ioex_config[] = {
+	[IOEX_C0_NCT38XX] = {
+		.i2c_host_port = I2C_PORT_USB_C0_TCPC,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT);
+
+void config_usb_db_type(void)
+{
+	enum ec_cfg_usb_db_type db_type = ec_cfg_usb_db_type();
+
+	/*
+	 * TODO(b/180434685): implement multiple DB types
+	 */
+
+	CPRINTS("Configured USB DB type number is %d", db_type);
+}
+
+void board_reset_pd_mcu(void)
+{
+	/* Port0 */
+	gpio_set_level(GPIO_USB_C0_TCPC_RST_ODL, 0);
+
+	if (battery_hw_present())
+		gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 0);
+
+	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS));
+
+	gpio_set_level(GPIO_USB_C0_TCPC_RST_ODL, 1);
+	gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 1);
+
+	/* wait for chips to come up */
+	msleep(PS8815_FW_INIT_DELAY_MS);
+}
+
+static void board_tcpc_init(void)
+{
+	int i;
+
+	/* Don't reset TCPCs after initial reset */
+	if (!system_jumped_late()) {
+		board_reset_pd_mcu();
+
+		for (i = 0; i < CONFIG_IO_EXPANDER_PORT_COUNT; ++i)
+			ioex_init(i);
+	}
+
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
+
+	/* Enable BC1.2 interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_0;
+
+	if (gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
+
+int ppc_get_alert_status(int port)
+{
+	if (port == USBC_PORT_C0)
+		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
+	else if (port == USBC_PORT_C1)
+		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
+	return 0;
+}
+
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C1);
+		break;
+	default:
+		break;
+	}
+}
+
+void bc12_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_BC12_INT_ODL:
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+		break;
+	case GPIO_USB_C1_BC12_INT_ODL:
+		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+		break;
+	default:
+		break;
+	}
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_PPC_INT_ODL:
+		nx20p348x_interrupt(USBC_PORT_C1);
+		break;
+	default:
+		break;
+	}
+}
+
+void retimer_interrupt(enum gpio_signal signal)
+{
+	/*
+	 * TODO(b/179513527): add USB-C support
+	 */
+}
+
+__override bool board_is_dts_port(int port)
+{
+	return port == USBC_PORT_C0;
+}
diff --git a/board/gimble/usbc_config.h b/board/gimble/usbc_config.h
new file mode 100644
index 0000000000..ab2dabc1e9
--- /dev/null
+++ b/board/gimble/usbc_config.h
@@ -0,0 +1,17 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Brya board-specific USB-C configuration */
+
+#ifndef __CROS_EC_USBC_CONFIG_H
+#define __CROS_EC_USBC_CONFIG_H
+
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
+
+void config_usb_db_type(void);
+
+#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/gimble/vif_override.xml b/board/gimble/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/gimble/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/gingerbread/board.c b/board/gingerbread/board.c
index 00e7eedc2e..62f871b55a 100644
--- a/board/gingerbread/board.c
+++ b/board/gingerbread/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,15 +6,95 @@
 /* Gingerbread board-specific configuration */
 
 #include "common.h"
+#include "cros_board_info.h"
+#include "driver/ppc/sn5s330.h"
+#include "driver/tcpm/ps8xxx.h"
+#include "driver/tcpm/stm32gx.h"
+#include "driver/tcpm/tcpci.h"
+#include "driver/usb_mux/tusb1064.h"
+#include "ec_version.h"
 #include "gpio.h"
 #include "hooks.h"
+#include "mp4245.h"
 #include "switch.h"
 #include "system.h"
 #include "task.h"
+#include "timer.h"
 #include "uart.h"
+#include "usb_descriptor.h"
+#include "usb_pd.h"
+#include "usb_pd_dp_ufp.h"
+#include "usb_pe_sm.h"
+#include "usb_prl_sm.h"
+#include "usb_tc_sm.h"
+#include "usbc_ppc.h"
 #include "util.h"
 
-#include "gpio_list.h" /* Must come after other header files. */
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+
+#define QUICHE_PD_DEBUG_LVL 1
+
+#ifdef SECTION_IS_RW
+#define CROS_EC_SECTION "RW"
+#else
+#define CROS_EC_SECTION "RO"
+#endif
+
+#ifdef SECTION_IS_RW
+/*
+ * C1 port on gingerbread does not have a PPC. However, C0 port does have a PPC
+ * and therefore PPC related config options are defined. Defining a null driver
+ * here so that functions from usbc_ppc.c will correctly dereference to a NULL
+ * function pointer.
+ */
+const struct ppc_drv board_ppc_null_drv = {};
+
+static int pd_dual_role_init[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	PD_DRP_TOGGLE_ON,
+	PD_DRP_FORCE_SOURCE,
+};
+
+static void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_HOST_USBC_PPC_INT_ODL:
+		sn5s330_interrupt(USB_PD_PORT_HOST);
+		break;
+
+	default:
+		break;
+	}
+}
+
+static void tcpc_alert_event(enum gpio_signal s)
+{
+	int port = -1;
+
+	switch (s) {
+	case GPIO_USBC_DP_MUX_ALERT_ODL:
+		port = USB_PD_PORT_DP;
+		break;
+	default:
+		return;
+	}
+
+	schedule_deferred_pd_interrupt(port);
+}
+
+void hpd_interrupt(enum gpio_signal signal)
+{
+	usb_pd_hpd_edge_event(signal);
+}
+
+static void board_pwr_btn_interrupt(enum gpio_signal signal)
+{
+	baseboard_power_button_evt(gpio_get_level(signal));
+}
+#endif /* SECTION_IS_RW */
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
 
 /*
  * Table GPIO signals control both power rails and reset lines to various chips
@@ -22,35 +102,300 @@
  * signals is driven by USB/MST hub power sequencing requirements.
  */
 const struct power_seq board_power_seq[] = {
-	{GPIO_EN_AC_JACK,               1, 20},
-	{GPIO_EN_PP5000_A,              1, 31},
-	{GPIO_EN_PP3300_A,              1, 35},
-	{GPIO_STATUS_LED1,              0, 100},
-	{GPIO_EN_BB,                    1, 30},
-	{GPIO_EN_PP1100_A,              1, 30},
-	{GPIO_EN_PP1000_A,              1, 20},
-	{GPIO_EN_PP1050_A,              1, 30},
-	{GPIO_EN_PP1200_A,              1, 20},
-	{GPIO_EN_PP5000_HSPORT,         1, 31},
-	{GPIO_EN_DP_SINK,               1, 80},
-	{GPIO_MST_LP_CTL_L,             1, 80},
-	{GPIO_MST_RST_L,                1, 41},
-	{GPIO_EC_HUB1_RESET_L,          1, 41},
-	{GPIO_EC_HUB2_RESET_L,          1, 33},
-	{GPIO_USBC_DP_PD_RST_L,         1, 100},
-	{GPIO_USBC_UF_RESET_L,          1, 33},
-	{GPIO_DEMUX_DUAL_DP_PD_N,       1, 100},
-	{GPIO_DEMUX_DUAL_DP_RESET_N,    1, 100},
-	{GPIO_DEMUX_DP_HDMI_PD_N,       1, 10},
-	{GPIO_DEMUX_DUAL_DP_MODE,       1, 10},
-	{GPIO_DEMUX_DP_HDMI_MODE,       1, 1},
-	{GPIO_STATUS_LED2,              0, 100},
+	{ GPIO_EN_AC_JACK, 1, 20 },
+	{ GPIO_EN_PP5000_A, 1, 31 },
+	{ GPIO_EN_PP3300_A, 1, 135 },
+	{ GPIO_EN_BB, 1, 30 },
+	{ GPIO_EN_PP1100_A, 1, 30 },
+	{ GPIO_EN_PP1000_A, 1, 20 },
+	{ GPIO_EN_PP1050_A, 1, 30 },
+	{ GPIO_EN_PP1200_A, 1, 20 },
+	{ GPIO_EN_PP5000_HSPORT, 1, 31 },
+	{ GPIO_EN_DP_SINK, 1, 80 },
+	{ GPIO_MST_LP_CTL_L, 1, 80 },
+	{ GPIO_MST_RST_L, 1, 41 },
+	{ GPIO_EC_HUB1_RESET_L, 1, 41 },
+	{ GPIO_EC_HUB2_RESET_L, 1, 33 },
+	{ GPIO_USBC_DP_PD_RST_L, 1, 100 },
+	{ GPIO_USBC_UF_RESET_L, 1, 33 },
+	{ GPIO_DEMUX_DUAL_DP_PD_N, 1, 100 },
+	{ GPIO_DEMUX_DUAL_DP_RESET_N, 1, 100 },
+	{ GPIO_DEMUX_DP_HDMI_PD_N, 1, 10 },
+	{ GPIO_DEMUX_DUAL_DP_MODE, 1, 10 },
+	{ GPIO_DEMUX_DP_HDMI_MODE, 1, 1 },
 };
 
 const size_t board_power_seq_count = ARRAY_SIZE(board_power_seq);
 
+/*
+ * Define the strings used in our USB descriptors.
+ */
+const void *const usb_strings[] = {
+	[USB_STR_DESC] = usb_string_desc,
+	[USB_STR_VENDOR] = USB_STRING_DESC("Google LLC"),
+	[USB_STR_PRODUCT] = USB_STRING_DESC("Gingerbread"),
+	[USB_STR_SERIALNO] = 0,
+	[USB_STR_VERSION] =
+		USB_STRING_DESC(CROS_EC_SECTION ":" CROS_EC_VERSION32),
+	[USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"),
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
+
+#ifndef SECTION_IS_RW
+/* USB-C PPC Configuration */
+struct ppc_config_t ppc_chips[] = {
+	[USB_PD_PORT_HOST] = {
+		.i2c_port = I2C_PORT_I2C3,
+		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	},
+};
+#endif
+
+#ifdef SECTION_IS_RW
+
+/* TUSB1064 set mux board tuning for DP Rx path */
+static int board_tusb1064_dp_rx_eq_set(const struct usb_mux *me,
+				       mux_state_t mux_state)
+{
+	int rv = EC_SUCCESS;
+
+	/* DP specific config */
+	if (mux_state & USB_PD_MUX_DP_ENABLED)
+		rv = tusb1064_set_dp_rx_eq(me, TUSB1064_DP_EQ_RX_8_9_DB);
+
+	return rv;
+}
+
+/*
+ * TCPCs: 2 USBC/PD ports
+ *     port 0 -> host port              -> STM32G4 UCPD
+ *     port 1 -> user data/display port -> PS8805
+ */
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_EMBEDDED,
+		.drv = &stm32gx_tcpm_drv,
+	},
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_I2C3,
+			.addr_flags = PS8XXX_I2C_ADDR2_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+	},
+};
+
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	[USB_PD_PORT_HOST] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_HOST,
+			.i2c_port = I2C_PORT_I2C1,
+			.i2c_addr_flags = TUSB1064_I2C_ADDR0_FLAGS,
+			.driver = &tusb1064_usb_mux_driver,
+			.board_set = &board_tusb1064_dp_rx_eq_set,
+		},
+	},
+	[USB_PD_PORT_DP] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_DP,
+			.i2c_port = I2C_PORT_I2C3,
+			.i2c_addr_flags = PS8XXX_I2C_ADDR2_FLAGS,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
+	},
+};
+
+/* USB-C PPC Configuration */
+struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	[USB_PD_PORT_HOST] = { .i2c_port = I2C_PORT_I2C3,
+			       .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+			       .drv = &sn5s330_drv },
+	[USB_PD_PORT_DP] = { .drv = &board_ppc_null_drv },
+};
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+const struct hpd_to_pd_config_t hpd_config = {
+	.port = USB_PD_PORT_HOST,
+	.signal = GPIO_DDI_MST_IN_HPD,
+};
+
+void board_reset_pd_mcu(void)
+{
+	cprints(CC_SYSTEM, "Resetting TCPCs...");
+	cflush();
+	/*
+	 * Reset all TCPCs.
+	 *   C0 -> ucpd (on chip TCPC)
+	 *   C1 -> PS8805 TCPC -> USBC_DP_PD_RST_L
+	 *   C2 -> PS8803 TCPC -> USBC_UF_RESET_L
+	 */
+	gpio_set_level(GPIO_USBC_DP_PD_RST_L, 0);
+	gpio_set_level(GPIO_USBC_UF_RESET_L, 0);
+	msleep(PS8805_FW_INIT_DELAY_MS);
+	gpio_set_level(GPIO_USBC_DP_PD_RST_L, 1);
+	gpio_set_level(GPIO_USBC_UF_RESET_L, 1);
+	msleep(PS8805_FW_INIT_DELAY_MS);
+}
+
+/* Power Delivery and charging functions */
+void board_enable_usbc_interrupts(void)
+{
+	board_reset_pd_mcu();
+
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_HOST_USBC_PPC_INT_ODL);
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USBC_DP_MUX_ALERT_ODL);
+
+	/* Enable HPD interrupt */
+	gpio_enable_interrupt(GPIO_DDI_MST_IN_HPD);
+}
+
+/* Power Delivery and charging functions */
+void board_disable_usbc_interrupts(void)
+{
+	/* Disable PPC interrupts. */
+	gpio_disable_interrupt(GPIO_HOST_USBC_PPC_INT_ODL);
+
+	/* Disable TCPC interrupts. */
+	gpio_disable_interrupt(GPIO_USBC_DP_MUX_ALERT_ODL);
+
+	/* Disable HPD interrupt */
+	gpio_disable_interrupt(GPIO_DDI_MST_IN_HPD);
+}
+
+void board_tcpc_init(void)
+{
+	board_reset_pd_mcu();
+
+	/* Enable board usbc interrupts */
+	board_enable_usbc_interrupts();
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 2);
+
+enum pd_dual_role_states board_tc_get_initial_drp_mode(int port)
+{
+	return pd_dual_role_init[port];
+}
+
+int ppc_get_alert_status(int port)
+{
+	if (port == USB_PD_PORT_HOST)
+		return gpio_get_level(GPIO_HOST_USBC_PPC_INT_ODL) == 0;
+
+	return 0;
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (!gpio_get_level(GPIO_USBC_DP_MUX_ALERT_ODL) &&
+	    gpio_get_level(GPIO_USBC_DP_PD_RST_L))
+		status |= PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
+
+void board_overcurrent_event(int port, int is_overcurrented)
+{
+	/* TODO: b/ - check correct operation for honeybuns */
+}
+
+int dock_get_mf_preference(void)
+{
+	int rv;
+	uint32_t fw_config;
+	int mf = MF_OFF;
+
+	/*
+	 * MF (multi function) preferece is indicated by bit 0 of the fw_config
+	 * data field. If this data field does not exist, then default to 4 lane
+	 * mode.
+	 */
+	rv = cbi_get_fw_config(&fw_config);
+	if (!rv)
+		mf = CBI_FW_MF_PREFERENCE(fw_config);
+
+	return mf;
+}
+
+static void board_usb_tc_connect(void)
+{
+	int port = TASK_ID_TO_PD_PORT(task_get_current());
+
+	/*
+	 * The EC needs to keep the USB hubs in reset until the host port is
+	 * attached so that the USB-EP can be properly enumerated.
+	 */
+	if (port == USB_PD_PORT_HOST) {
+		gpio_set_level(GPIO_EC_HUB1_RESET_L, 1);
+		gpio_set_level(GPIO_EC_HUB2_RESET_L, 1);
+	}
+}
+DECLARE_HOOK(HOOK_USB_PD_CONNECT, board_usb_tc_connect, HOOK_PRIO_DEFAULT);
+
+static void board_usb_tc_disconnect(void)
+{
+	int port = TASK_ID_TO_PD_PORT(task_get_current());
+
+	/* Only the host port disconnect is relevant */
+	if (port == USB_PD_PORT_HOST) {
+		gpio_set_level(GPIO_EC_HUB1_RESET_L, 0);
+		gpio_set_level(GPIO_EC_HUB2_RESET_L, 0);
+	}
+}
+DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, board_usb_tc_disconnect,
+	     HOOK_PRIO_DEFAULT);
+
+#endif /* SECTION_IS_RW */
+
 static void board_init(void)
 {
-	/* TODO */
+#ifdef SECTION_IS_RW
+	/*
+	 * Set current limit for USB 3.1 Gen 2 ports to 1.5 A. Note, this is
+	 * also done in gpio.inc, but needs to be in RW for platforms which
+	 * shipped with RO that set these 2 lines to the 900 mA level.
+	 */
+	gpio_set_level(GPIO_USB3_P3_CDP_EN, 1);
+	gpio_set_level(GPIO_USB3_P4_CDP_EN, 1);
+#endif
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+static void board_debug_gpio_1_pulse(void)
+{
+	gpio_set_level(GPIO_TRIGGER_1, 0);
+}
+DECLARE_DEFERRED(board_debug_gpio_1_pulse);
+
+static void board_debug_gpio_2_pulse(void)
+{
+	gpio_set_level(GPIO_TRIGGER_2, 0);
+}
+DECLARE_DEFERRED(board_debug_gpio_2_pulse);
+
+void board_debug_gpio(enum debug_gpio trigger, int level, int pulse_usec)
+{
+	switch (trigger) {
+	case TRIGGER_1:
+		gpio_set_level(GPIO_TRIGGER_1, level);
+		if (pulse_usec)
+			hook_call_deferred(&board_debug_gpio_1_pulse_data,
+					   pulse_usec);
+		break;
+	case TRIGGER_2:
+		gpio_set_level(GPIO_TRIGGER_2, level);
+		if (pulse_usec)
+			hook_call_deferred(&board_debug_gpio_2_pulse_data,
+					   pulse_usec);
+		break;
+	default:
+		CPRINTS("bad debug gpio selection");
+		break;
+	}
+}
diff --git a/board/gingerbread/board.h b/board/gingerbread/board.h
index c3052f3f59..09e9e0b7fe 100644
--- a/board/gingerbread/board.h
+++ b/board/gingerbread/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,24 +12,44 @@
 #include "baseboard.h"
 
 /* Optional features */
+/*
+ * For MP release, CONFIG_SYSTEM_UNLOCKED must be undefined, and
+ * CONFIG_FLASH_PSTATE_LOCKED must be defined in order to enable write protect
+ * using option bytes WRP registers.
+ */
 #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
+#undef CONFIG_FLASH_PSTATE_LOCKED
 
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* Keyboard features */
+#define CONFIG_WP_ACTIVE_HIGH
 
-/* Sensors */
+/* Console */
+#define CONFIG_UART_CONSOLE 3
+#define CONFIG_UART_TX_DMA_CH STM32_DMAC_USART3_TX
+#define CONFIG_UART_TX_DMA_PH DMAMUX_REQ_USART3_TX
 
 /* USB Type C and USB PD defines */
-
-/* USB Type A Features */
-
-/* BC 1.2 */
-
-/* Volume Button feature */
-
-/* Fan features */
+#define USB_PD_PORT_HOST 0
+#define USB_PD_PORT_DP 1
+
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#define CONFIG_USB_MUX_TUSB1064
+#define CONFIG_USB_PD_VBUS_DETECT_TCPC
+#define BOARD_C1_NO_PPC
+#define BOARD_C1_1A5_LIMIT
+
+#define CONFIG_USB_PID 0x5049
+#define CONFIG_USB_BCD_DEV 0x0001 /* v 0.01 */
+#define CONFIG_USB_PD_IDENTITY_HW_VERS 1
+#define CONFIG_USB_PD_IDENTITY_SW_VERS 1
+
+/* I2C port names */
+#define I2C_PORT_I2C1 0
+#define I2C_PORT_I2C2 1
+#define I2C_PORT_I2C3 2
+/* Required symbolic I2C port names */
+#define I2C_PORT_MP4245 I2C_PORT_I2C3
+#define I2C_PORT_EEPROM I2C_PORT_I2C1
+#define MP4245_I2C_ADDR_FLAGS MP4245_I2C_ADDR_0_FLAGS
 
 /*
  * Macros for GPIO signals used in common code that don't match the
@@ -37,16 +57,52 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_ENTERING_RW	GPIO_EC_ENTERING_RW
-#define GPIO_WP_L		GPIO_EC_WP_L
-
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_WP GPIO_EC_WP_L
 
+/* Include math_util for bitmask_uint64 used in pd_timers */
+#define CONFIG_MATH_UTIL
 
 #ifndef __ASSEMBLER__
 
-#include "gpio_signal.h"
 #include "registers.h"
 
+#define GPIO_DP_HPD GPIO_DDI_MST_IN_HPD
+#define GPIO_BPWR_DET GPIO_TP71
+#define GPIO_PWR_BUTTON_RED GPIO_EC_STATUS_LED1
+#define GPIO_PWR_BUTTON_GREEN GPIO_EC_STATUS_LED2
+
+#define BUTTON_PRESSED_LEVEL 0
+#define BUTTON_RELEASED_LEVEL 1
+
+#define GPIO_TRIGGER_1 GPIO_USB3_A1_CDP_EN
+#define GPIO_TRIGGER_2 GPIO_USB3_A2_CDP_EN
+
+enum debug_gpio {
+	TRIGGER_1 = 0,
+	TRIGGER_2,
+};
+
+/*
+ * Function used to control GPIO signals as a timing marker. This is intended to
+ * be used for development/debugging purposes.
+ *
+ * @param trigger GPIO debug signal selection
+ * @param level desired level of the debug gpio signal
+ * @param pulse_usec pulse width if non-zero
+ */
+void board_debug_gpio(enum debug_gpio trigger, int level, int pulse_usec);
+
+/*
+ * Function called in power on case to enable usbc related interrupts
+ */
+void board_enable_usbc_interrupts(void);
+
+/*
+ * Function called in power off case to disable usbc related interrupts
+ */
+void board_disable_usbc_interrupts(void);
 
 #endif /* !__ASSEMBLER__ */
 
diff --git a/board/gingerbread/build.mk b/board/gingerbread/build.mk
index bd3691f95a..d7ca7b35b5 100644
--- a/board/gingerbread/build.mk
+++ b/board/gingerbread/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -12,7 +12,7 @@ CHIP:=stm32
 # codebase. Currently, using a variant of the F family so the project will
 # build properly.
 CHIP_FAMILY:=stm32g4
-CHIP_VARIANT:=stm32g431xb
+CHIP_VARIANT:=stm32g473xc
 BASEBOARD:=honeybuns
 
 board-y=board.o
diff --git a/board/gingerbread/dev_key.pem b/board/gingerbread/dev_key.pem
new file mode 100644
index 0000000000..7b1df5d805
--- /dev/null
+++ b/board/gingerbread/dev_key.pem
@@ -0,0 +1,39 @@
+-----BEGIN RSA PRIVATE KEY-----
+MIIG5AIBAAKCAYEA2hyGIDxIS/jWNh3Nhg7V4/5Ce8KT4CIb1XaLd0mR2gWCkYdZ
+iRWSjAjMsMCLSLM0gUDnFU5xJgbUdg1GeafXdPlRQojG2ztZ/z+JBNgQvsWtdJhR
+m9dMm1cbq3rajU5NoVu1hiLIWpayYo91w1qMnf3LRFAgrVDvEUt8elCpTB60uZiS
+QL3PSCJhZiGyK2QGix+vNKxri+GnM+SxXggi3IrLMI2gqpCTiTZl4t8Ecnsn4QMC
+OvgRzDj2TnYJhhAdFeg7SuQ9TKCXAyw0LAR9AcuQ8tbf3ox04umLdbAj518ScXZB
+ef2xrnXIBkXcA5UXZ2J6+YP7tvm6XCEnwdhEq5gi65Mjc1i8vihzABXbXrKhFdKt
+ACLdQ8V6eM2nTK4NwNIeHdF0KRBvln5APxapNfjQh9Fz67ytvxt7TaBQWOheWB1V
+8NL7AzfcEPUH5blCjdWNfLcUXNqZa6+Jxk5Zug5dPazo1y1R5XoLFKpZ76c33fPr
+ngV8jwkTNaXVU84jAgEDAoIBgQCRaFlq0trdUI7OvokECePtVCxSgbfqwWfjpFz6
+MQvmrlcLr5EGDmGysIh11bIwd3hWK0S43vYZWeL5Xi77xTpN+4uBsISSJ5FU1QYD
+OrXUg8j4ZYu9OjMSOhJyUecI3t5rknkEFzA8ZHbsX6PXkbMT/oeC4BXI4J9g3P2m
+4HDdac3REGGAfoowFuuZa8wc7VmyFR94cvJdQRoimHY+sBc9sdzLCRXHCw0GJEPs
+lK2hp2/rV1bR+raIJfmJpAZZYBIn4W8yHD2LX6/ofgnTIxw9jAL1eheBviKwpYw8
+QOr46FlX3SZs8cupHbCf+DiPbcwZce3viPPMXSF+XW4wmiXgQeJnAh7sStcu4WjF
+TWxppqto6mr/5D5uI+NWjm13puJVL6OsPkJrhEZ1gSW6u3pPxAotkj4sppIg2qUJ
+pmxohz4D8gChOyedxtg1DRBqMY9VDnfRN5DMuPiF9t77KkOuHfZI3tUwWIeZeRKV
+tJEldJjnTBZfqZirjznlIBq1oasCgcEA/9RLDoX70KACdkki4o8MOrqHvmU3fgtZ
+MWIxrbjFoR9JhjFIZm41Ak8/sMhbs0dOskS4FmNaeKgkhsalZR997HvZXDxAsB7X
+tWkYcqKI1XaB48rIB5g5rxFmnxh/vVrchlUh80YQS/jvetD+fmjzXHeyrC2OCAgR
+2cfrl0ZwbXDbvoWoUcAl9C8YuUWUYurJsyqnwNLg6uiGB5anjBITNVGOXYD8hdcv
+2RoOOSnuGwTHRtytphO1WJiUqn9yOV5jAoHBANpByXEz5SrxDLAmAozAxmq/BMQ6
+hR3j56iPB22V/dDjQud5P3Akyy55/2WJK3kpFo7y3fvTM4vF45fOXRPRje65dfTT
+tGDJokJtPWV/L+rCHhSoRHi0Re9+Ptffg1vY3bq1hqguADvRFmtriSiUfmHbDpdI
+iKC6wLQLmCfgPU6spZOsrK06GaJefwgb2uOEIdsVMgIQ2j7cnpsmk8F84P+P3XLd
+rIjRVqYqYPrxkhxzizwlHGhzYjUZp7N2Own9QQKBwQCqjYdfA/01wAGkMMHsX118
+fFp+7iT+sjt2QXZz0IPAv4ZZdjBESXisNNUghZJ3hN8hgyVkQjxQcBhZ2cOYv6lI
+UpDoKCsgFI/ORhBMbFs4+avtMdqvutEfYO8Uuv/TkehZjhaiLrWH+0pR4Kmpm0zo
+T8xyyQlasAvmhUe6LvWeSz0prnA2gBlNdLsmLmLsnIZ3ccUrN0CcmwQFDxpdYWIj
+i7Q+Vf2uj3U7ZrQmG/QSAy+Ekx5ut847EGMcVPbQ6ZcCgcEAkYEw9iKYx0tdysQB
+sysu8dSt2CcDaUKacF9aSQ6pNezXRPt/oBiHdFFU7ltyUMYPCfc+p+IiXS6XuomT
+Youz9Huj+I0i6zEW1vN+Q6of8da+uHAtpc2D9P7Uj+pXkpCT0c5ZxXQAJ+C5nPJb
+cGL+6+dfD4WwaycrIrJlb+rTichuYnMdyNFmbD7/Wr08l61r52N2rAs8KehpvMRi
+gP3rVQqToekdsIuPGXGV/KEMEveyKBi9mveWzhEad6QnW/4rAoHBAM1TgJVVYCKl
+tmUf8XcC8+bNQ+dlqPdBQa3cAPFlQdRZUzDIYU+ZHa66GWUWb2uuD2hFCDDEpC1l
+Ke34tNROiruDfj9lfD6UmJv8vw/wPG3m52Qb5iWdA+B1512MK8p7KZg9YQJot/Yj
+B2rNxv1O+IjWPxxtUEVsFpx/XGoEemc85iS+icjNXvtOwyEGdNliRFiQtVkh2mtX
+7uKbkUAL2HKzxfnJ/LbWZwDlW45x/qDQtncp93sTcM3k8FVE+MtLbw==
+-----END RSA PRIVATE KEY-----
diff --git a/board/gingerbread/ec.tasklist b/board/gingerbread/ec.tasklist
index c272906fc7..ffd4a604c9 100644
--- a/board/gingerbread/ec.tasklist
+++ b/board/gingerbread/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,5 +8,11 @@
  */
 
 #define CONFIG_TASK_LIST \
+	TASK_ALWAYS_RO(RWSIG,    rwsig_task,   NULL, 1280) \
 	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE)
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS_RW(POWER_BUTTON, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS_RW(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS_RW(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS_RW(PD_INT_C1, pd_interrupt_handler_task, 1, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS_RW(UCPD, ucpd_task, 0, LARGER_TASK_STACK_SIZE)
diff --git a/board/gingerbread/gpio.inc b/board/gingerbread/gpio.inc
index 052124289c..4da3c973c1 100644
--- a/board/gingerbread/gpio.inc
+++ b/board/gingerbread/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,8 +8,14 @@
 /* Declare symbolic names for all the GPIOs that we care about.
  * Note: Those with interrupt handlers must be declared first. */
 
-/* Power sequencing interrupts */
-GPIO(PWR_BTN,                       PIN(A, 0),  GPIO_INPUT)
+#ifdef SECTION_IS_RW
+GPIO_INT(HOST_USBC_PPC_INT_ODL,  PIN(C, 1),       GPIO_INT_FALLING | GPIO_PULL_UP,  ppc_interrupt)
+GPIO_INT(USBC_DP_MUX_ALERT_ODL,  PIN(C, 12),       GPIO_INT_FALLING | GPIO_PULL_UP,   tcpc_alert_event)
+GPIO_INT(DDI_MST_IN_HPD,         PIN(C, 14),      GPIO_INT_BOTH, hpd_interrupt)
+GPIO_INT(PWR_BTN,                PIN(A,  0),      GPIO_INT_BOTH, board_pwr_btn_interrupt)
+#endif
+
+/* Power sequencing signals */
 GPIO(EN_AC_JACK,                    PIN(A, 1),  GPIO_OUT_LOW)
 GPIO(EN_BB,                         PIN(C, 0),  GPIO_OUT_LOW)
 GPIO(EN_PP3300_A,                   PIN(C, 10), GPIO_OUT_LOW)
@@ -19,12 +25,13 @@ GPIO(EN_PP1100_A,                   PIN(C, 4),  GPIO_OUT_LOW)
 GPIO(EN_PP1000_A,                   PIN(C, 5),  GPIO_OUT_LOW)
 GPIO(EN_PP1050_A,                   PIN(C, 6),  GPIO_OUT_LOW)
 GPIO(EN_PP5000_HSPORT,              PIN(C, 7),  GPIO_OUT_LOW)
-GPIO(STATUS_LED1,                   PIN(A, 2),  GPIO_OUT_HIGH)
-GPIO(STATUS_LED2,                   PIN(B, 12), GPIO_OUT_HIGH)
+GPIO(EC_STATUS_LED1,                PIN(A, 2),  GPIO_OUT_HIGH)
+GPIO(EC_STATUS_LED2,                PIN(B, 12), GPIO_OUT_HIGH)
 
 /* MST Hub signals */
-GPIO(MST_LP_CTL_L,                  PIN(B, 9),  GPIO_ODR_LOW)
+GPIO(MST_LP_CTL_L,                  PIN(B, 9),  GPIO_OUT_LOW)
 GPIO(MST_RST_L,                     PIN(B, 3),  GPIO_ODR_LOW)
+GPIO(MST_HUB_LANE_SWITCH,           PIN(C, 15), GPIO_OUT_HIGH)
 
 /* Display Demux signals */
 GPIO(DEMUX_DUAL_DP_MODE,            PIN(D, 8),  GPIO_OUT_LOW)
@@ -43,7 +50,30 @@ GPIO(USBC_UF_RESET_L,               PIN(C, 11), GPIO_ODR_LOW)
 GPIO(EC_HUB1_RESET_L,               PIN(E, 13), GPIO_ODR_LOW)
 GPIO(EC_HUB2_RESET_L,               PIN(E, 14), GPIO_ODR_LOW)
 
-/* Misc Signals */
+/* DEBUG signals */
+GPIO(DEBUG_GPIO1,                   PIN(B, 13),      GPIO_OUT_LOW)
+
+/* Configure as output to enable @1.5A on USBA Ports
+* USB CDP enables. */
+GPIO(USB3_A1_CDP_EN,                PIN(E, 7),       GPIO_OUT_LOW)
+GPIO(USB3_A2_CDP_EN,                PIN(E, 8),       GPIO_OUT_LOW)
+GPIO(USB3_P3_CDP_EN,                PIN(D, 1),       GPIO_OUT_HIGH)
+GPIO(USB3_P4_CDP_EN,                PIN(E, 12),      GPIO_OUT_HIGH)
+
+/* Write protect */
+GPIO(EC_FLASH_WP_ODL,               PIN(A, 3),       GPIO_ODR_HIGH)
+GPIO(EC_WP_L,                       PIN(E, 11),      GPIO_INT_BOTH)
+
+
+/* SPI Bus */
+GPIO(FLASH_SPI1_NSS,                PIN(A, 4),       GPIO_INT_FALLING)
+GPIO(FLASH_SPI1_SCK,                PIN(A, 5),       GPIO_INT_BOTH)
+GPIO(FLASH_SPI1_MISO,               PIN(A, 6),       GPIO_INT_BOTH)
+GPIO(FLASH_SPI1_MOSI,               PIN(A, 7),       GPIO_INT_BOTH)
+
+/* misc signals */
+GPIO(EC_DFU_MUX_CTRL,               PIN(A, 8),       GPIO_OUT_HIGH)
+GPIO(TP71,               PIN(B, 0),       GPIO_OUT_LOW)
 
 /*
  * I2C SCL/SDA pins. These will normally be under control of the peripheral from
@@ -52,16 +82,13 @@ GPIO(EC_HUB2_RESET_L,               PIN(E, 14), GPIO_ODR_LOW)
  */
 GPIO(EC_I2C1_SCL,                   PIN(A, 15),  GPIO_ODR_HIGH)
 GPIO(EC_I2C1_SDA,                   PIN(B,  7),  GPIO_ODR_HIGH)
-GPIO(EC_I2C2_SDA,                   PIN(A,  8),  GPIO_ODR_HIGH)
-GPIO(EC_I2C2_SCL,                   PIN(A,  9),  GPIO_ODR_HIGH)
 GPIO(EC_I2C3_SCL,                   PIN(C,  8),  GPIO_ODR_HIGH)
 GPIO(EC_I2C3_SDA,                   PIN(C,  9),  GPIO_ODR_HIGH)
 
 UNIMPLEMENTED(EC_ENTERING_RW)
-UNIMPLEMENTED(EC_WP_L)
-
-/* UART */
 
+ALTERNATE(PIN_MASK(B, 0x0C00), GPIO_ALT_USART,   MODULE_UART,     GPIO_PULL_UP) /* GPIOB 10-11:USART3_TX/RX */
+ALTERNATE(PIN_MASK(A, 0x00F0),      5,           MODULE_SPI,      0) /* GPIOA4-7: SPI Signals */
 /* I2C Ports
  *   I2C1: SDA/SCL -> PB7/PA15
  *   I2C2: SDA/SCL -> PA8/PA9
@@ -69,5 +96,4 @@ UNIMPLEMENTED(EC_WP_L)
  */
 ALTERNATE(PIN_MASK(B, 0x0080),  4, MODULE_I2C,   GPIO_OPEN_DRAIN)
 ALTERNATE(PIN_MASK(A, 0X8000),  4, MODULE_I2C,   GPIO_OPEN_DRAIN)
-ALTERNATE(PIN_MASK(A, 0x0300),  4, MODULE_I2C,   GPIO_OPEN_DRAIN)
 ALTERNATE(PIN_MASK(C, 0x0300),  8, MODULE_I2C,   GPIO_OPEN_DRAIN)
diff --git a/board/gladios/board.c b/board/gladios/board.c
new file mode 100644
index 0000000000..898d85a9d0
--- /dev/null
+++ b/board/gladios/board.c
@@ -0,0 +1,534 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "adc.h"
+#include "builtin/assert.h"
+#include "button.h"
+#include "cec.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "driver/cec/bitbang.h"
+#include "driver/tcpm/tcpci.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "power.h"
+#include "power_button.h"
+#include "switch.h"
+#include "throttle_ap.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+#include <stdbool.h>
+
+/* Console output macros */
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+
+static void power_monitor(void);
+DECLARE_DEFERRED(power_monitor);
+
+/******************************************************************************/
+/* USB-A charging control */
+
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_PP5000_USBA,
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
+
+/******************************************************************************/
+
+/* CEC ports */
+const struct cec_config_t cec_config[] = {
+	[CEC_PORT_0] = {
+		.drv = &bitbang_cec_drv,
+		.offline_policy = NULL,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(cec_config) == CEC_PORT_COUNT);
+
+int board_set_active_charge_port(int port)
+{
+	CPRINTS("Requested charge port change to %d", port);
+
+	/*
+	 * The charge manager may ask us to switch to no charger if we're
+	 * running off USB-C only but upstream doesn't support PD. It requires
+	 * that we accept this switch otherwise it triggers an assert and EC
+	 * reset; it's not possible to boot the AP anyway, but we want to avoid
+	 * resetting the EC so we can continue to do the "low power" LED blink.
+	 */
+	if (port == CHARGE_PORT_NONE)
+		return EC_SUCCESS;
+
+	if (port < 0 || CHARGE_PORT_COUNT <= port)
+		return EC_ERROR_INVAL;
+
+	if (port == charge_manager_get_active_charge_port())
+		return EC_SUCCESS;
+
+	/* Don't charge from a source port */
+	if (board_vbus_source_enabled(port))
+		return EC_ERROR_INVAL;
+
+	if (!chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
+		int bj_active, bj_requested;
+
+		if (charge_manager_get_active_charge_port() != CHARGE_PORT_NONE)
+			/* Change is only permitted while the system is off */
+			return EC_ERROR_INVAL;
+
+		/*
+		 * Current setting is no charge port but the AP is on, so the
+		 * charge manager is out of sync (probably because we're
+		 * reinitializing after sysjump). Reject requests that aren't
+		 * in sync with our outputs.
+		 */
+		bj_active = !gpio_get_level(GPIO_EN_PPVAR_BJ_ADP_L);
+		bj_requested = port == CHARGE_PORT_BARRELJACK;
+		if (bj_active != bj_requested)
+			return EC_ERROR_INVAL;
+	}
+
+	CPRINTS("New charger p%d", port);
+
+	switch (port) {
+	case CHARGE_PORT_TYPEC0:
+		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 1);
+		break;
+	case CHARGE_PORT_BARRELJACK:
+		/* Make sure BJ adapter is sourcing power */
+		if (gpio_get_level(GPIO_BJ_ADP_PRESENT_ODL))
+			return EC_ERROR_INVAL;
+		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 0);
+		break;
+	default:
+		return EC_ERROR_INVAL;
+	}
+
+	return EC_SUCCESS;
+}
+
+static uint8_t usbc_overcurrent;
+static int32_t base_5v_power_s5;
+static int32_t base_5v_power_z1;
+
+/*
+ * Power usage for each port as measured or estimated.
+ * Units are milliwatts (5v x ma current)
+ */
+
+/* PP5000_S5 loads */
+#define PWR_S5_BASE_LOAD (5 * 1431)
+#define PWR_S5_FRONT_HIGH (5 * 1737)
+#define PWR_S5_FRONT_LOW (5 * 1055)
+#define PWR_S5_REAR_HIGH (5 * 1737)
+#define PWR_S5_REAR_LOW (5 * 1055)
+#define PWR_S5_HDMI (5 * 580)
+#define PWR_S5_MAX (5 * 10000)
+#define FRONT_DELTA (PWR_S5_FRONT_HIGH - PWR_S5_FRONT_LOW)
+#define REAR_DELTA (PWR_S5_REAR_HIGH - PWR_S5_REAR_LOW)
+
+/* PP5000_Z1 loads */
+#define PWR_Z1_BASE_LOAD (5 * 5)
+#define PWR_Z1_C_HIGH (5 * 3600)
+#define PWR_Z1_C_LOW (5 * 2000)
+#define PWR_Z1_MAX (5 * 9000)
+/*
+ * Update the 5V power usage, assuming no throttling,
+ * and invoke the power monitoring.
+ */
+static void update_5v_usage(void)
+{
+	int front_ports = 0;
+	int rear_ports = 0;
+
+	/*
+	 * Recalculate the 5V load, assuming no throttling.
+	 */
+	base_5v_power_s5 = PWR_S5_BASE_LOAD;
+	if (!gpio_get_level(GPIO_USB_A0_OC_ODL)) {
+		front_ports++;
+		base_5v_power_s5 += PWR_S5_FRONT_LOW;
+	}
+	if (!gpio_get_level(GPIO_USB_A1_OC_ODL)) {
+		front_ports++;
+		base_5v_power_s5 += PWR_S5_FRONT_LOW;
+	}
+	/*
+	 * Only 1 front port can run higher power at a time.
+	 */
+	if (front_ports > 0)
+		base_5v_power_s5 += PWR_S5_FRONT_HIGH - PWR_S5_FRONT_LOW;
+
+	if (!gpio_get_level(GPIO_USB_A2_OC_ODL)) {
+		rear_ports++;
+		base_5v_power_s5 += PWR_S5_REAR_LOW;
+	}
+	if (!gpio_get_level(GPIO_USB_A3_OC_ODL)) {
+		rear_ports++;
+		base_5v_power_s5 += PWR_S5_REAR_LOW;
+	}
+	/*
+	 * Only 1 rear port can run higher power at a time.
+	 */
+	if (rear_ports > 0)
+		base_5v_power_s5 += PWR_S5_REAR_HIGH - PWR_S5_REAR_LOW;
+	if (!gpio_get_level(GPIO_HDMIA_CONN_OC_ODL))
+		base_5v_power_s5 += PWR_S5_HDMI;
+	if (!gpio_get_level(GPIO_HDMIB_CONN_OC_ODL))
+		base_5v_power_s5 += PWR_S5_HDMI;
+	base_5v_power_z1 = PWR_Z1_BASE_LOAD;
+	if (usbc_overcurrent)
+		base_5v_power_z1 += PWR_Z1_C_HIGH;
+	/*
+	 * Invoke the power handler immediately.
+	 */
+	hook_call_deferred(&power_monitor_data, 0);
+}
+DECLARE_DEFERRED(update_5v_usage);
+/*
+ * Start power monitoring after ADCs have been initialised.
+ */
+DECLARE_HOOK(HOOK_INIT, update_5v_usage, HOOK_PRIO_INIT_ADC + 1);
+
+static void port_ocp_interrupt(enum gpio_signal signal)
+{
+	hook_call_deferred(&update_5v_usage_data, 0);
+}
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/******************************************************************************/
+/*
+ * Barrel jack power supply handling
+ *
+ * EN_PPVAR_BJ_ADP_L must default active to ensure we can power on when the
+ * barrel jack is connected, and the USB-C port can bring the EC up fine in
+ * dead-battery mode. Both the USB-C and barrel jack switches do reverse
+ * protection, so we're safe to turn one on then the other off- but we should
+ * only do that if the system is off since it might still brown out.
+ */
+
+#define ADP_DEBOUNCE_MS 1000 /* Debounce time for BJ plug/unplug */
+/* Debounced connection state of the barrel jack */
+static int8_t adp_connected = -1;
+static void adp_connect_deferred(void)
+{
+	struct charge_port_info pi = { 0 };
+	int connected = !gpio_get_level(GPIO_BJ_ADP_PRESENT_ODL);
+
+	/* Debounce */
+	if (connected == adp_connected)
+		return;
+	if (connected)
+		ec_bj_power(&pi.voltage, &pi.current);
+	charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED,
+				     DEDICATED_CHARGE_PORT, &pi);
+	adp_connected = connected;
+}
+DECLARE_DEFERRED(adp_connect_deferred);
+
+/* IRQ for BJ plug/unplug. It shouldn't be called if BJ is the power source. */
+void adp_connect_interrupt(enum gpio_signal signal)
+{
+	hook_call_deferred(&adp_connect_deferred_data, ADP_DEBOUNCE_MS * MSEC);
+}
+
+static void adp_state_init(void)
+{
+	ASSERT(CHARGE_PORT_ENUM_COUNT == CHARGE_PORT_COUNT);
+	/*
+	 * Initialize all charge suppliers to 0. The charge manager waits until
+	 * all ports have reported in before doing anything.
+	 */
+	for (int i = 0; i < CHARGE_PORT_COUNT; i++) {
+		for (int j = 0; j < CHARGE_SUPPLIER_COUNT; j++)
+			charge_manager_update_charge(j, i, NULL);
+	}
+
+	/* Report charge state from the barrel jack. */
+	adp_connect_deferred();
+}
+DECLARE_HOOK(HOOK_INIT, adp_state_init, HOOK_PRIO_INIT_CHARGE_MANAGER + 1);
+
+static void board_init(void)
+{
+	gpio_enable_interrupt(GPIO_BJ_ADP_PRESENT_ODL);
+	gpio_enable_interrupt(GPIO_HDMIA_CONN_OC_ODL);
+	gpio_enable_interrupt(GPIO_HDMIB_CONN_OC_ODL);
+	gpio_enable_interrupt(GPIO_USB_A0_OC_ODL);
+	gpio_enable_interrupt(GPIO_USB_A1_OC_ODL);
+	gpio_enable_interrupt(GPIO_USB_A2_OC_ODL);
+	gpio_enable_interrupt(GPIO_USB_A3_OC_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+void board_overcurrent_event(int port, int is_overcurrented)
+{
+	/* Check that port number is valid. */
+	if ((port < 0) || (port >= CONFIG_USB_PD_PORT_MAX_COUNT))
+		return;
+	usbc_overcurrent = is_overcurrented;
+	update_5v_usage();
+}
+/*
+ * Power monitoring and management.
+ *
+ * the power budgets are met without letting the system fall into
+ * power deficit (perhaps causing a brownout).
+ *
+ * There are 2 power budgets that need to be managed:
+ * The overall goal is to gracefully manage the power demand so that
+ *  - overall system power as measured on the main power supply rail.
+ *  - 5V power delivered to the USB and HDMI ports.
+ *
+ * The actual system power demand is calculated from the VBUS voltage and
+ * the input current (read from a shunt), averaged over 5 readings.
+ * The power budget limit is from the charge manager.
+ *
+ * The 5V power cannot be read directly. Instead, we rely on overcurrent
+ * inputs from the USB and HDMI ports to indicate that the port is in use
+ * (and drawing maximum power).
+ *
+ * There are 3 throttles that can be applied (in priority order):
+ *
+ *  - Type A BC1.2 front port restriction (3W)
+ *  - Type A BC1.2 rear port restriction (3W)
+ *  - Type C PD (throttle to 1.5A if sourcing)
+ *  - Turn on PROCHOT, which immediately throttles the CPU.
+ *
+ *  The first 3 throttles affect both the system power and the 5V rails.
+ *  The third is a last resort to force an immediate CPU throttle to
+ *  reduce the overall power use.
+ *
+ *  The strategy is to determine what the state of the throttles should be,
+ *  and to then turn throttles off or on as needed to match this.
+ *
+ *  This function runs on demand, or every 2 ms when the CPU is up,
+ *  and continually monitors the power usage, applying the
+ *  throttles when necessary.
+ *
+ *  All measurements are in milliwatts.
+ */
+#define THROT_TYPE_A_FRONT BIT(0)
+#define THROT_TYPE_A_REAR BIT(1)
+#define THROT_TYPE_C0 BIT(2)
+#define THROT_PROCHOT BIT(5)
+
+/*
+ * Power gain if front USB A ports are limited.
+ */
+#define POWER_GAIN_TYPE_A 3200
+/*
+ * Power gain if Type C port is limited.
+ */
+#define POWER_GAIN_TYPE_C 8800
+/*
+ * Power is averaged over 10 ms, with a reading every 2 ms.
+ */
+#define POWER_DELAY_MS 2
+#define POWER_READINGS (10 / POWER_DELAY_MS)
+
+static void power_monitor(void)
+{
+	static uint32_t current_state;
+	static uint32_t history[POWER_READINGS];
+	static uint8_t index;
+	int32_t delay;
+	uint32_t new_state = 0, diff;
+	int32_t headroom_5v_s5 = PWR_S5_MAX - base_5v_power_s5;
+	int32_t headroom_5v_z1 = PWR_Z1_MAX - base_5v_power_z1;
+
+	/*
+	 * If CPU is off or suspended, no need to throttle
+	 * or restrict power.
+	 */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF | CHIPSET_STATE_SUSPEND)) {
+		/*
+		 * Slow down monitoring, assume no throttling required.
+		 */
+		delay = 20 * MSEC;
+		/*
+		 * Clear the first entry of the power table so that
+		 * it is re-initilalised when the CPU starts.
+		 */
+		history[0] = 0;
+	} else {
+		int32_t charger_mw;
+
+		delay = POWER_DELAY_MS * MSEC;
+		/*
+		 * Get current charger limit (in mw).
+		 * If not configured yet, skip.
+		 */
+		charger_mw = charge_manager_get_power_limit_uw() / 1000;
+		if (charger_mw != 0) {
+			int32_t gap, total, max, power;
+			int i;
+
+			/*
+			 * Read power usage.
+			 */
+			power = (adc_read_channel(ADC_VBUS) *
+				 adc_read_channel(ADC_PPVAR_IMON)) /
+				1000;
+			/* Init power table */
+			if (history[0] == 0) {
+				for (i = 0; i < POWER_READINGS; i++)
+					history[i] = power;
+			}
+			/*
+			 * Update the power readings and
+			 * calculate the average and max.
+			 */
+			history[index] = power;
+			index = (index + 1) % POWER_READINGS;
+			total = 0;
+			max = history[0];
+			for (i = 0; i < POWER_READINGS; i++) {
+				total += history[i];
+				if (history[i] > max)
+					max = history[i];
+			}
+			/*
+			 * For Type-C power supplies, there is
+			 * less tolerance for exceeding the rating,
+			 * so use the max power that has been measured
+			 * over the measuring period.
+			 * For barrel-jack supplies, the rating can be
+			 * exceeded briefly, so use the average.
+			 */
+			if (charge_manager_get_supplier() == CHARGE_SUPPLIER_PD)
+				power = max;
+			else
+				power = total / POWER_READINGS;
+			/*
+			 * Calculate gap, and if negative, power
+			 * demand is exceeding configured power budget, so
+			 * throttling is required to reduce the demand.
+			 */
+			gap = charger_mw - power;
+			/*
+			 * Limiting type-A power rear ports.
+			 */
+			if (gap <= 0) {
+				new_state |= THROT_TYPE_A_REAR;
+				headroom_5v_s5 += REAR_DELTA;
+				if (!(current_state & THROT_TYPE_A_REAR))
+					gap += POWER_GAIN_TYPE_A;
+			}
+			/*
+			 * Limiting type-A power front ports.
+			 */
+			if (gap <= 0) {
+				new_state |= THROT_TYPE_A_FRONT;
+				headroom_5v_s5 += FRONT_DELTA;
+				if (!(current_state & THROT_TYPE_A_REAR))
+					gap += POWER_GAIN_TYPE_A;
+			}
+			/*
+			 * If the type-C port is sourcing power,
+			 * check whether it should be throttled.
+			 */
+			if (ppc_is_sourcing_vbus(0) && gap <= 0) {
+				new_state |= THROT_TYPE_C0;
+				headroom_5v_z1 += PWR_Z1_C_HIGH - PWR_Z1_C_LOW;
+				if (!(current_state & THROT_TYPE_C0))
+					gap += POWER_GAIN_TYPE_C;
+			}
+			/*
+			 * As a last resort, turn on PROCHOT to
+			 * throttle the CPU.
+			 */
+			if (gap <= 0)
+				new_state |= THROT_PROCHOT;
+		}
+	}
+	/*
+	 * Check the 5v power usage and if necessary,
+	 * adjust the throttles in priority order.
+	 *
+	 * Either throttle may have already been activated by
+	 * the overall power control.
+	 *
+	 * We rely on the overcurrent detection to inform us
+	 * if the port is in use.
+	 *
+	 *  - If type C not already throttled:
+	 *	* If not overcurrent, prefer to limit type C [1].
+	 *	* If in overcurrentuse:
+	 *		- limit type A first [2]
+	 *		- If necessary, limit type C [3].
+	 *  - If type A not throttled, if necessary limit it [2].
+	 */
+	if (headroom_5v_z1 < 0) {
+		/*
+		 * Check whether type C is not throttled,
+		 * and is not overcurrent.
+		 */
+		if (!((new_state & THROT_TYPE_C0) || usbc_overcurrent)) {
+			/*
+			 * [1] Type C not in overcurrent, throttle it.
+			 */
+			headroom_5v_z1 += PWR_Z1_C_HIGH - PWR_Z1_C_LOW;
+			new_state |= THROT_TYPE_C0;
+		}
+		/*
+		 * [2] If still under-budget, limit type C.
+		 * No need to check if it is already throttled or not.
+		 */
+		if (headroom_5v_z1 < 0)
+			new_state |= THROT_TYPE_C0;
+	}
+	if (headroom_5v_s5 < 0) {
+		/*
+		 * [1] If type A rear not already throttled, and power still
+		 * needed, limit type A rear.
+		 */
+		if (!(new_state & THROT_TYPE_A_REAR) && headroom_5v_s5 < 0) {
+			headroom_5v_s5 += PWR_S5_REAR_HIGH - PWR_S5_REAR_LOW;
+			new_state |= THROT_TYPE_A_REAR;
+		}
+		/*
+		 * [2] If type A front not already throttled, and power still
+		 * needed, limit type A front.
+		 */
+		if (!(new_state & THROT_TYPE_A_FRONT) && headroom_5v_s5 < 0) {
+			headroom_5v_s5 += PWR_S5_FRONT_HIGH - PWR_S5_FRONT_LOW;
+			new_state |= THROT_TYPE_A_FRONT;
+		}
+	}
+	/*
+	 * Turn the throttles on or off if they have changed.
+	 */
+	diff = new_state ^ current_state;
+	current_state = new_state;
+	if (diff & THROT_PROCHOT) {
+		int prochot = (new_state & THROT_PROCHOT) ? 0 : 1;
+
+		gpio_set_level(GPIO_EC_PROCHOT_ODL, prochot);
+	}
+	if (diff & THROT_TYPE_C0) {
+		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C0) ?
+						TYPEC_RP_1A5 :
+						TYPEC_RP_3A0;
+
+		ppc_set_vbus_source_current_limit(0, rp);
+		tcpm_select_rp_value(0, rp);
+		pd_update_contract(0);
+	}
+	if (diff & THROT_TYPE_A_REAR) {
+		int typea_bc = (new_state & THROT_TYPE_A_REAR) ? 1 : 0;
+
+		gpio_set_level(GPIO_USB_A_LOW_PWR0_OD, typea_bc);
+		gpio_set_level(GPIO_USB_A_LOW_PWR1_OD, typea_bc);
+	}
+	hook_call_deferred(&power_monitor_data, delay);
+}
diff --git a/board/gladios/board.h b/board/gladios/board.h
new file mode 100644
index 0000000000..fd2db92a46
--- /dev/null
+++ b/board/gladios/board.h
@@ -0,0 +1,163 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Gladios board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "compile_time_macros.h"
+
+/* Baseboard features */
+#include "baseboard.h"
+
+/* Barrel Jack */
+#define DEDICATED_CHARGE_PORT 1
+
+/* HDMI CEC */
+#define CONFIG_CEC
+#define CONFIG_CEC_BITBANG
+#define CEC_GPIO_OUT GPIO_HDMIB_CEC_OUT
+#define CEC_GPIO_IN GPIO_HDMIB_CEC_IN
+#define CEC_GPIO_PULL_UP GPIO_HDMIB_CEC_PULL_UP
+
+/* USB Type A Features */
+#define USB_PORT_COUNT 4
+#define CONFIG_USB_PORT_POWER_DUMB
+#define CONFIG_USBC_RETIMER_PS8811
+
+/* USB Type C and USB PD defines */
+#define CONFIG_USB_PD_PPC
+#define CONFIG_USB_PD_TCPM_RT1715
+#define CONFIG_USBC_RETIMER_PS8818
+#define CONFIG_USBC_PPC_SYV682X
+#undef CONFIG_SYV682X_HV_ILIM
+#define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_5_50
+
+/* TODO: b/177608416 - measure and check these values on brya */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
+
+/* The design should support up to 100W. */
+/* TODO(b/197702356): Set the max PD to 60W now and change it
+ * to 100W after we verify it.
+ */
+#define PD_OPERATING_POWER_MW CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
+#define PD_MAX_POWER_MW 100000
+#define PD_MAX_CURRENT_MA 5000
+#define PD_MAX_VOLTAGE_MV 20000
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
+
+/*
+ * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
+ * signal.
+ */
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
+#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_OD
+#define GPIO_RECOVERY_L_2 GPIO_GSC_EC_RECOVERY_BTN_OD
+
+/* I2C Bus Configuration */
+#define I2C_PORT_USB_C0_TCPC NPCX_I2C_PORT1_0
+
+#define I2C_PORT_USB_C0_PPC_BC12 NPCX_I2C_PORT2_0
+
+#define I2C_PORT_USB_C0_MUX NPCX_I2C_PORT3_0
+
+#define I2C_PORT_USB_A2_A3_RT NPCX_I2C_PORT6_1
+
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+
+/* Thermal features */
+#define CONFIG_THERMISTOR
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_TEMP_SENSOR_POWER
+#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
+
+/* ADC */
+#define CONFIG_ADC
+
+/*
+ * TODO(b/197478860): Enable the fan control. We need
+ * to check the sensor value and adjust the fan speed.
+ */
+#define CONFIG_FANS FAN_CH_COUNT
+
+/* Include math_util for bitmask_uint64 used in pd_timers */
+#define CONFIG_MATH_UTIL
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h" /* needed by registers.h */
+#include "registers.h"
+#include "usbc_config.h"
+
+enum charge_port {
+	CHARGE_PORT_TYPEC0,
+	CHARGE_PORT_BARRELJACK,
+	CHARGE_PORT_ENUM_COUNT
+};
+
+enum adc_channel {
+	ADC_TEMP_SENSOR_1_CPU,
+	ADC_TEMP_SENSOR_2_CPU_VR,
+	ADC_TEMP_SENSOR_3_WIFI,
+	ADC_TEMP_SENSOR_4_DIMM,
+	ADC_VBUS,
+	ADC_PPVAR_IMON, /* ADC3 */
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1_CPU,
+	TEMP_SENSOR_2_CPU_VR,
+	TEMP_SENSOR_3_WIFI,
+	TEMP_SENSOR_4_DIMM,
+	TEMP_SENSOR_COUNT
+};
+
+enum pwm_channel {
+	PWM_CH_LED_GREEN, /* PWM0 */
+	PWM_CH_FAN, /* PWM5 */
+	PWM_CH_LED_RED, /* PWM2 */
+	PWM_CH_COUNT
+};
+
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT };
+
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT };
+
+enum cec_port { CEC_PORT_0, CEC_PORT_COUNT };
+
+extern void adp_connect_interrupt(enum gpio_signal signal);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/gladios/build.mk b/board/gladios/build.mk
new file mode 100644
index 0000000000..637cdc2c22
--- /dev/null
+++ b/board/gladios/build.mk
@@ -0,0 +1,22 @@
+# -*- makefile -*-
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Gladios board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx9
+CHIP_VARIANT:=npcx9m3f
+BASEBOARD:=brask
+
+board-y=
+board-y+=board.o
+board-y+=fans.o
+board-y+=fw_config.o
+board-y+=i2c.o
+board-y+=led.o
+board-y+=pwm.o
+board-y+=sensors.o
+board-y+=usbc_config.o
diff --git a/board/gladios/ec.tasklist b/board/gladios/ec.tasklist
new file mode 100644
index 0000000000..072252f0cd
--- /dev/null
+++ b/board/gladios/ec.tasklist
@@ -0,0 +1,23 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ *
+ * USB_CHG_Px tasks must be contiguous (see USB_CHG_PORT_TO_TASK_ID(x)).
+ * PD_Cx tasks must be contiguous (see PD_PORT_TO_TASK_ID(x))
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CEC, cec_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/gladios/fans.c b/board/gladios/fans.c
new file mode 100644
index 0000000000..02172cd3e1
--- /dev/null
+++ b/board/gladios/fans.c
@@ -0,0 +1,48 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Physical fans. These are logically separate from pwm_channels. */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "fan.h"
+#include "fan_chip.h"
+#include "hooks.h"
+#include "pwm.h"
+
+/* MFT channels. These are logically separate from pwm_channels. */
+const struct mft_t mft_channels[] = {
+	[MFT_CH_0] = {
+		.module = NPCX_MFT_MODULE_2,
+		.clk_src = TCKC_LFCLK,
+		.pwm_id = PWM_CH_FAN,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
+
+static const struct fan_conf fan_conf_0 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
+	.pgood_gpio = -1,
+	.enable_gpio = GPIO_EN_PP5000_FAN,
+};
+
+/*
+ * Fan spins at about 4100 RPM at 100% PWM.
+ * Set minimum at around 30% PWM.
+ */
+static const struct fan_rpm fan_rpm_0 = {
+	.rpm_min = 2000,
+	.rpm_start = 2000,
+	.rpm_max = 4700,
+};
+
+const struct fan_t fans[FAN_CH_COUNT] = {
+	[FAN_CH_0] = {
+		.conf = &fan_conf_0,
+		.rpm = &fan_rpm_0,
+	},
+};
diff --git a/board/gladios/fw_config.c b/board/gladios/fw_config.c
new file mode 100644
index 0000000000..ed2b8b32ce
--- /dev/null
+++ b/board/gladios/fw_config.c
@@ -0,0 +1,66 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "fw_config.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+static union gladios_cbi_fw_config fw_config;
+BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
+
+/*
+ * FW_CONFIG defaults for gladios if the CBI.FW_CONFIG data is not
+ * initialized.
+ */
+static const union gladios_cbi_fw_config fw_config_defaults = {
+	.bj_power = BJ_65W,
+	.storage = EMMC,
+	.fvm_support = FVM_NO,
+};
+
+/*
+ * Barrel-jack power adapter ratings.
+ */
+static const struct {
+	int voltage;
+	int current;
+} bj_power[] = {
+	[BJ_65W] = { /* 0 - 65W (also default) */
+			.voltage = 19000,
+			.current = 3420
+	},
+	[BJ_90W] = { /* 1 - 90W */
+			.voltage = 19000,
+			.current = 4740
+	}
+};
+
+/****************************************************************************
+ * Gladios FW_CONFIG access
+ */
+void board_init_fw_config(void)
+{
+	if (cbi_get_fw_config(&fw_config.raw_value)) {
+		CPRINTS("CBI: Read FW_CONFIG failed, using board defaults");
+		fw_config = fw_config_defaults;
+	}
+}
+
+void ec_bj_power(uint32_t *voltage, uint32_t *current)
+{
+	unsigned int bj;
+
+	bj = fw_config.bj_power;
+	/* Out of range value defaults to 0 */
+	if (bj >= ARRAY_SIZE(bj_power))
+		bj = 0;
+	*voltage = bj_power[bj].voltage;
+	*current = bj_power[bj].current;
+}
diff --git a/board/gladios/fw_config.h b/board/gladios/fw_config.h
new file mode 100644
index 0000000000..ba0bd65047
--- /dev/null
+++ b/board/gladios/fw_config.h
@@ -0,0 +1,44 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __BOARD_GLADIOS_FW_CONFIG_H_
+#define __BOARD_GLADIOS_FW_CONFIG_H_
+
+#include <stdint.h>
+
+/****************************************************************************
+ * CBI FW_CONFIG layout for Gladios board.
+ *
+ * Source of truth is the project/brask/gladios/config.star configuration file.
+ */
+enum ec_cfg_bj_power { BJ_65W = 0, BJ_90W = 1 };
+
+enum ec_cfg_storage { EMMC = 0, SSD = 1 };
+
+enum ec_cfg_fvm_support { FVM_NO = 0, FVM_YES = 1 };
+
+union gladios_cbi_fw_config {
+	struct {
+		uint32_t bj_power : 1;
+		uint32_t storage : 1;
+		uint32_t fvm_support : 1;
+		uint32_t reserved_1 : 29;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Read the cached FW_CONFIG.  Guaranteed to have valid values.
+ *
+ * @return the FW_CONFIG for the board.
+ */
+union gladios_cbi_fw_config get_fw_config(void);
+
+/**
+ * Get the barrel-jack power from FW_CONFIG.
+ */
+void ec_bj_power(uint32_t *voltage, uint32_t *current);
+
+#endif /* __BOARD_GLADIOS_FW_CONFIG_H_ */
diff --git a/board/gladios/gpio.inc b/board/gladios/gpio.inc
new file mode 100644
index 0000000000..958b36c619
--- /dev/null
+++ b/board/gladios/gpio.inc
@@ -0,0 +1,162 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* INTERRUPT GPIOs: */
+
+GPIO_INT(ACOK_OD,                    PIN(0, 0), GPIO_INT_BOTH, extpower_interrupt)
+GPIO_INT(EC_PROCHOT_IN_L,            PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
+GPIO_INT(EC_WP_ODL,                  PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(GSC_EC_PWR_BTN_ODL,         PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
+GPIO_INT(SEQ_EC_ALL_SYS_PG,          PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_DSW_PWROK,           PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_RSMRST_ODL,          PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,                   PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,                  PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SYS_SLP_S0IX_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(USB_C0_BC12_INT_ODL,        PIN(C, 6), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C0_C2_TCPC_INT_ODL,     PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C0_PPC_INT_ODL,         PIN(6, 2), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(BJ_ADP_PRESENT_ODL,         PIN(8, 2), GPIO_INT_BOTH | GPIO_PULL_UP, adp_connect_interrupt)
+GPIO_INT(EC_RECOVERY_BTN_OD,         PIN(2, 3), GPIO_INT_BOTH, button_interrupt)
+GPIO_INT(HDMIA_CONN_OC_ODL,          PIN(5, 0), GPIO_INPUT | GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(HDMIB_CONN_OC_ODL,          PIN(2, 4), GPIO_INPUT | GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(USB_A0_OC_ODL,              PIN(3, 1), GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(USB_A1_OC_ODL,              PIN(3, 0), GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(USB_A2_OC_ODL,              PIN(2, 7), GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(USB_A3_OC_ODL,              PIN(2, 6), GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH, port_ocp_interrupt)
+
+/* CCD */
+GPIO(CCD_MODE_ODL,                   PIN(E, 5), GPIO_INPUT)
+
+/* Security */
+GPIO(EC_ENTERING_RW,                 PIN(0, 3), GPIO_OUT_LOW)
+GPIO(EC_GSC_PACKET_MODE,             PIN(7, 5), GPIO_OUT_LOW)
+
+/* Fan */
+GPIO(EN_PP5000_FAN,                  PIN(6, 1), GPIO_OUT_HIGH)
+
+/* ADC, need to check the usage */
+GPIO(ANALOG_PPVAR_PWR_IN_IMON_EC,    PIN(4, 2), GPIO_INPUT)
+
+/* BarrelJack */
+GPIO(EN_PPVAR_BJ_ADP_L,              PIN(0, 7), GPIO_OUT_LOW)
+
+/* Chipset PCH */
+GPIO(EC_PCHHOT_ODL,                  PIN(7, 4), GPIO_INPUT)
+GPIO(EC_PCH_INT_ODL,                 PIN(B, 0), GPIO_ODR_HIGH)
+GPIO(EC_PCH_RSMRST_L,                PIN(A, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_RTCRST,                  PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_SYS_PWROK,               PIN(3, 7), GPIO_OUT_LOW)
+GPIO(EC_PCH_WAKE_ODL,                PIN(C, 0), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_ODL,                 PIN(6, 3), GPIO_ODR_HIGH)
+GPIO(EN_S5_RAILS,                    PIN(B, 6), GPIO_OUT_LOW)
+GPIO(PCH_PWROK,                      PIN(7, 2), GPIO_OUT_LOW)
+GPIO(SYS_RST_ODL,                    PIN(C, 5), GPIO_ODR_HIGH)
+GPIO(VCCST_PWRGD_OD,                 PIN(A, 4), GPIO_ODR_LOW)
+GPIO(IMVP9_VRRDY_OD,                 PIN(6, 0), GPIO_INPUT)
+GPIO(CPU_C10_GATE_L,                 PIN(6, 7), GPIO_INPUT)
+
+/* Button */
+GPIO(EC_PCH_PWR_BTN_ODL,             PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(GSC_EC_RECOVERY_BTN_OD,         PIN(2, 2), GPIO_INPUT)
+
+/* HDMI CEC */
+/* TODO(b/197474873): Enable HDMI CEC */
+GPIO(HDMIB_CEC_IN,                   PIN(4, 0), GPIO_INPUT)
+GPIO(HDMIB_CEC_OUT,                  PIN(D, 3), GPIO_OUT_HIGH | GPIO_OPEN_DRAIN)
+GPIO(HDMIB_CEC_PULL_UP,              PIN(C, 2), GPIO_OUT_HIGH)
+GPIO(HDMIA_CEC_IN,                   PIN(A, 7), GPIO_INPUT)
+GPIO(HDMIA_CEC_OUT,                  PIN(F, 2), GPIO_OUT_HIGH | GPIO_OPEN_DRAIN)
+GPIO(HDMIA_CEC_PULL_UP,              PIN(F, 3), GPIO_OUT_HIGH)
+
+/* I2C SCL/SDA */
+GPIO(EC_I2C_MISC_SCL_R,              PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SDA_R,              PIN(B, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_PPC_BC_SCL,    PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_PPC_BC_SDA,    PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_RT_SCL,        PIN(D, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_RT_SDA,        PIN(D, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_TCPC_SCL,      PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_TCPC_SDA,      PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_USB_A2_A3_SCL,           PIN(E, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_A2_A3_SDA,           PIN(E, 3), GPIO_INPUT)
+
+/* USBA */
+GPIO(EN_PP5000_USBA,                 PIN(D, 7), GPIO_OUT_LOW)
+GPIO(USB_A0_STATUS_L,                PIN(2, 1), GPIO_INPUT)
+GPIO(USB_A1_STATUS_L,                PIN(2, 0), GPIO_INPUT)
+GPIO(USB_A_LOW_PWR0_OD,              PIN(1, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(USB_A_LOW_PWR1_OD,              PIN(1, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(USB_A_OC_SOC_L,                 PIN(8, 0), GPIO_OUT_HIGH)
+
+/* LED */
+/* TODO(b/197471359): LED implementation */
+GPIO(LED_GREEN_L,                    PIN(C, 3), GPIO_OUT_LOW)
+GPIO(LED_RED_L,                      PIN(C, 4), GPIO_OUT_LOW)
+
+/* USBC */
+GPIO(USB_C0_FRS_EN,                  PIN(9, 4), GPIO_OUT_LOW)
+GPIO(USB_C0_HPD,                     PIN(0, 4), GPIO_OUT_LOW)
+GPIO(USB_C0_OC_ODL,                  PIN(7, 0), GPIO_OUT_LOW)
+
+/* UART alternate functions */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)              /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */
+
+/* I2C alternate functions */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)               /* GPIO87/I2C1_SDA0 */
+ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)               /* GPIO92/I2C2_SCL0, GPIO91/I2C2_SDA0, GPIO90/I2C1_SCL0 */
+ALTERNATE(PIN_MASK(B, 0x0c), 0, MODULE_I2C, 0)               /* GPIOB3/I2C7_SCL0/DCD_L, GPIOB2/I2C7_SDA0/DSR_L */
+ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)               /* GPIOD1/I2C3_SCL0, GPIOD0/I2C3_SDA0 */
+ALTERNATE(PIN_MASK(E, 0x18), 0, MODULE_I2C, 0)               /* GPIOE4/I2C6_SCL1/I3C_SCL, GPIOE3/I2C6_SDA1/I3C_SDA */
+
+/* PWM alternate functions */
+ALTERNATE(PIN_MASK(7, 0x08), 0, MODULE_PWM, 0)               /* GPIO73/TA2 */
+ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)               /* GPIOB7/PWM5 */
+ALTERNATE(PIN_MASK(C, 0x18), 0, MODULE_PWM, 0)               /* GPIOC4/PWM2, GPIOC3/PWM0 */
+
+/* ADC alternate functions */
+ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0)               /* GPIO34/PS2_DAT2/ADC6 */
+ALTERNATE(PIN_MASK(4, 0x38), 0, MODULE_ADC, 0)               /* GPIO45/ADC0, GPIO44/ADC1, GPIO43/ADC2 */
+ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0)               /* GPIOE1/ADC7 */
+
+/* NC pins, enable internal pull-down to avoid floating state. */
+GPIO(GPIO02_NC,                      PIN(0, 2), GPIO_INPUT | GPIO_PULL_DOWN)
+
+/* Unused Pins */
+UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
+UNUSED(PIN(3, 2))       /* GPO32/TRIS_L */
+UNUSED(PIN(3, 5))       /* GPO35/CR_SOUT4/TEST_L */
+UNUSED(PIN(6, 6))       /* GPIO66 */
+UNUSED(PIN(8, 1))       /* GPIO81/PECI_DATA */
+UNUSED(PIN(5, 6))       /* GPIO56/CLKRUN# */
+UNUSED(PIN(9, 7))       /* GPIO97 */
+UNUSED(PIN(8, 6))       /* GPIO86/TXD/CR_SOUT2 */
+UNUSED(PIN(1, 3))       /* KSO06/GPO13/GP_SEL# */
+UNUSED(PIN(1, 2))       /* KSO07/GPO12/JEN# */
+UNUSED(PIN(0, 6))       /* KSO11/GPIO06/P80_CLK */
+UNUSED(PIN(A, 0))
+UNUSED(PIN(A, 2))
+UNUSED(PIN(A, 3))
+UNUSED(PIN(B, 1))
+UNUSED(PIN(B, 5))
+UNUSED(PIN(B, 4))
+UNUSED(PIN(D, 2))
+UNUSED(PIN(D, 4))
+UNUSED(PIN(F, 5))
+UNUSED(PIN(0, 5))
+UNUSED(PIN(1, 1))
+UNUSED(PIN(1, 0))
+UNUSED(PIN(1, 7))
+UNUSED(PIN(1, 6))
+UNUSED(PIN(2, 5))
+UNUSED(PIN(3, 3))
+UNUSED(PIN(3, 6))
+UNUSED(PIN(4, 1))
+UNUSED(PIN(8, 3))
+UNUSED(PIN(9, 3))
+UNUSED(PIN(9, 5))
+UNUSED(PIN(9, 6))
diff --git a/board/gladios/i2c.c b/board/gladios/i2c.c
new file mode 100644
index 0000000000..a58f75bfa7
--- /dev/null
+++ b/board/gladios/i2c.c
@@ -0,0 +1,53 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "i2c.h"
+
+/* I2C port map configuration */
+const struct i2c_port_t i2c_ports[] = {
+	{
+		/* I2C1 */
+		.name = "tcpc0",
+		.port = I2C_PORT_USB_C0_TCPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C2_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C2_TCPC_SDA,
+	},
+	{
+		/* I2C2 */
+		.name = "ppc, bc1.2 c0",
+		.port = I2C_PORT_USB_C0_PPC_BC12,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C2_PPC_BC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C2_PPC_BC_SDA,
+	},
+	{
+		/* I2C3 */
+		.name = "retimer0",
+		.port = I2C_PORT_USB_C0_MUX,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C2_RT_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C2_RT_SDA,
+	},
+	{
+		/* I2C6 */
+		.name = "usba2_retimer, usba3_retimer",
+		.port = I2C_PORT_USB_A2_A3_RT,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_A2_A3_SCL,
+		.sda = GPIO_EC_I2C_USB_A2_A3_SDA,
+	},
+	{
+		/* I2C7 */
+		.name = "eeprom",
+		.port = I2C_PORT_EEPROM,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_MISC_SCL_R,
+		.sda = GPIO_EC_I2C_MISC_SDA_R,
+	},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/board/gladios/led.c b/board/gladios/led.c
new file mode 100644
index 0000000000..e6248774a6
--- /dev/null
+++ b/board/gladios/led.c
@@ -0,0 +1,266 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power LED control for Gladios.
+ * Solid green - active power
+ * Green flashing - suspended
+ * Red flashing - alert
+ * Solid red - critical
+ */
+
+#include "chipset.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "led_common.h"
+#include "pwm.h"
+#include "timer.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
+
+/*
+ * Due to the CSME-Lite processing, upon startup the CPU transitions through
+ * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so
+ * delay turning off the LED during suspend/shutdown.
+ */
+#define LED_CPU_DELAY_MS (2000 * MSEC)
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED };
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+enum led_color {
+	LED_OFF = 0,
+	LED_RED,
+	LED_GREEN,
+
+	/* Number of colors, not a color itself */
+	LED_COLOR_COUNT
+};
+
+static int set_color_power(enum led_color color, int duty)
+{
+	int green = 0;
+	int red = 0;
+
+	if (duty < 0 || 100 < duty)
+		return EC_ERROR_UNKNOWN;
+
+	switch (color) {
+	case LED_OFF:
+		break;
+	case LED_GREEN:
+		green = 1;
+		break;
+	case LED_RED:
+		red = 1;
+		break;
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+
+	if (red)
+		pwm_set_duty(PWM_CH_LED_RED, duty);
+	else
+		pwm_set_duty(PWM_CH_LED_RED, 0);
+
+	if (green)
+		pwm_set_duty(PWM_CH_LED_GREEN, duty);
+	else
+		pwm_set_duty(PWM_CH_LED_GREEN, 0);
+
+	return EC_SUCCESS;
+}
+
+static int set_color(enum ec_led_id id, enum led_color color, int duty)
+{
+	switch (id) {
+	case EC_LED_ID_POWER_LED:
+		return set_color_power(color, duty);
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+}
+
+#define LED_PULSE_US (1500 * MSEC)
+#define LED_OFF_TIME_US (1500 * MSEC)
+/* 30 msec for nice and smooth transition. */
+#define LED_PULSE_TICK_US (30 * MSEC)
+
+/*
+ * When pulsing is enabled, brightness is incremented by <duty_inc> every
+ * <interval> usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented
+ * likewise in LED_PULSE_US usec. Stay 0 for <off_time>.
+ */
+static struct {
+	uint32_t interval;
+	int duty_inc;
+	enum led_color color;
+	uint32_t off_time;
+	int duty;
+} led_pulse;
+
+#define CONFIG_TICK(interval, color)                                        \
+	config_tick((interval), 100 / (LED_PULSE_US / (interval)), (color), \
+		    (LED_OFF_TIME_US))
+
+static void config_tick(uint32_t interval, int duty_inc, enum led_color color,
+			uint32_t off_time)
+{
+	led_pulse.interval = interval;
+	led_pulse.duty_inc = duty_inc;
+	led_pulse.color = color;
+	led_pulse.off_time = off_time;
+	led_pulse.duty = 0;
+}
+
+static void led_tick(void);
+DECLARE_DEFERRED(led_tick);
+static void led_tick(void)
+{
+	uint32_t elapsed;
+	uint32_t next = 0;
+	uint32_t start = get_time().le.lo;
+
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED)) {
+		set_color(EC_LED_ID_POWER_LED, led_pulse.color, led_pulse.duty);
+		if (led_pulse.duty + led_pulse.duty_inc > 100) {
+			led_pulse.duty_inc = led_pulse.duty_inc * -1;
+		} else if (led_pulse.duty + led_pulse.duty_inc < 0) {
+			led_pulse.duty_inc = led_pulse.duty_inc * -1;
+			next = led_pulse.off_time;
+		}
+		led_pulse.duty += led_pulse.duty_inc;
+	}
+
+	if (next == 0)
+		next = led_pulse.interval;
+	elapsed = get_time().le.lo - start;
+	next = next > elapsed ? next - elapsed : 0;
+	hook_call_deferred(&led_tick_data, next);
+}
+
+static void led_suspend(void)
+{
+	CONFIG_TICK(LED_PULSE_TICK_US, LED_GREEN);
+	led_tick();
+}
+DECLARE_DEFERRED(led_suspend);
+
+static void led_shutdown(void)
+{
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_OFF, 0);
+}
+DECLARE_DEFERRED(led_shutdown);
+
+static void led_shutdown_hook(void)
+{
+	hook_call_deferred(&led_tick_data, -1);
+	hook_call_deferred(&led_suspend_data, -1);
+	hook_call_deferred(&led_shutdown_data, LED_CPU_DELAY_MS);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, led_shutdown_hook, HOOK_PRIO_DEFAULT);
+
+static void led_suspend_hook(void)
+{
+	hook_call_deferred(&led_shutdown_data, -1);
+	hook_call_deferred(&led_suspend_data, LED_CPU_DELAY_MS);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, led_suspend_hook, HOOK_PRIO_DEFAULT);
+
+static void led_resume(void)
+{
+	/*
+	 * Assume there is no race condition with led_tick, which also
+	 * runs in hook_task.
+	 */
+	hook_call_deferred(&led_tick_data, -1);
+	/*
+	 * Avoid invoking the suspend/shutdown delayed hooks.
+	 */
+	hook_call_deferred(&led_suspend_data, -1);
+	hook_call_deferred(&led_shutdown_data, -1);
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_GREEN, 100);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, led_resume, HOOK_PRIO_DEFAULT);
+
+void led_alert(int enable)
+{
+	if (enable) {
+		/* Overwrite the current signal */
+		config_tick(1 * SECOND, 100, LED_RED, 0);
+		led_tick();
+	} else {
+		/* Restore the previous signal */
+		if (chipset_in_state(CHIPSET_STATE_ON))
+			led_resume();
+		else if (chipset_in_state(CHIPSET_STATE_SUSPEND))
+			led_suspend_hook();
+		else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+			led_shutdown_hook();
+	}
+}
+
+void show_critical_error(void)
+{
+	hook_call_deferred(&led_tick_data, -1);
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_RED, 100);
+}
+
+static int command_led(int argc, const char **argv)
+{
+	enum ec_led_id id = EC_LED_ID_POWER_LED;
+
+	if (argc < 2)
+		return EC_ERROR_PARAM_COUNT;
+
+	if (!strcasecmp(argv[1], "debug")) {
+		led_auto_control(id, !led_auto_control_is_enabled(id));
+		ccprintf("o%s\n", led_auto_control_is_enabled(id) ? "ff" : "n");
+	} else if (!strcasecmp(argv[1], "off")) {
+		set_color(id, LED_OFF, 0);
+	} else if (!strcasecmp(argv[1], "red")) {
+		set_color(id, LED_RED, 100);
+	} else if (!strcasecmp(argv[1], "green")) {
+		set_color(id, LED_GREEN, 100);
+	} else if (!strcasecmp(argv[1], "alert")) {
+		led_alert(1);
+	} else if (!strcasecmp(argv[1], "crit")) {
+		show_critical_error();
+	} else {
+		return EC_ERROR_PARAM1;
+	}
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(led, command_led, "[debug|red|green|off|alert|crit]",
+			"Turn on/off LED.");
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	brightness_range[EC_LED_COLOR_RED] = 100;
+	brightness_range[EC_LED_COLOR_GREEN] = 100;
+}
+
+int led_set_brightness(enum ec_led_id id, const uint8_t *brightness)
+{
+	if (brightness[EC_LED_COLOR_RED])
+		return set_color(id, LED_RED, brightness[EC_LED_COLOR_RED]);
+	else if (brightness[EC_LED_COLOR_GREEN])
+		return set_color(id, LED_GREEN, brightness[EC_LED_COLOR_GREEN]);
+	else
+		return set_color(id, LED_OFF, 0);
+}
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
+{
+	/* Blink alert if insufficient power per system_can_boot_ap(). */
+	int insufficient_power =
+		(charge_ma * charge_mv) <
+		(CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON * 1000);
+	led_alert(insufficient_power);
+}
diff --git a/board/gladios/pwm.c b/board/gladios/pwm.c
new file mode 100644
index 0000000000..db85952f41
--- /dev/null
+++ b/board/gladios/pwm.c
@@ -0,0 +1,33 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "hooks.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_LED_GREEN] = { .channel = 0,
+			       .flags = PWM_CONFIG_ACTIVE_LOW |
+					PWM_CONFIG_DSLEEP,
+			       .freq = 2000 },
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN | PWM_CONFIG_DSLEEP,
+			 .freq = 1000 },
+	[PWM_CH_LED_RED] = { .channel = 2,
+			     .flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+			     .freq = 2000 },
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+static void board_pwm_init(void)
+{
+	pwm_enable(PWM_CH_FAN, 1);
+
+	pwm_enable(PWM_CH_LED_RED, 1);
+	pwm_enable(PWM_CH_LED_GREEN, 1);
+}
+DECLARE_HOOK(HOOK_INIT, board_pwm_init, HOOK_PRIO_DEFAULT);
diff --git a/board/gladios/sensors.c b/board/gladios/sensors.c
new file mode 100644
index 0000000000..99bc0a4304
--- /dev/null
+++ b/board/gladios/sensors.c
@@ -0,0 +1,114 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc_chip.h"
+#include "common.h"
+#include "hooks.h"
+#include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
+#include "thermal.h"
+
+/* ADC configuration */
+const struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_1_CPU] = {
+		.name = "TEMP_CPU",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_2_CPU_VR] = {
+		.name = "TEMP_CPU_VR",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_3_WIFI] = {
+		.name = "TEMP_WIFI",
+		.input_ch = NPCX_ADC_CH6,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_4_DIMM] = {
+		.name = "TEMP_DIMM",
+		.input_ch = NPCX_ADC_CH7,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_VBUS] = {  /* 5/39 voltage divider */
+		.name = "VBUS",
+		.input_ch = NPCX_ADC_CH2,
+		.factor_mul = ADC_MAX_VOLT * 39,
+		.factor_div = (ADC_READ_MAX + 1) * 5,
+	},
+	[ADC_PPVAR_IMON] = {  /* 872.3 mV/A */
+		.name = "PPVAR_IMON",
+		.input_ch = NPCX_ADC_CH3,
+		.factor_mul = ADC_MAX_VOLT * 1433,
+		.factor_div = (ADC_READ_MAX + 1) * 1250,
+	},
+
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* Temperature sensor configuration */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1_CPU] = { .name = "CPU",
+				.type = TEMP_SENSOR_TYPE_BOARD,
+				.read = get_temp_3v3_30k9_47k_4050b,
+				.idx = ADC_TEMP_SENSOR_1_CPU },
+	[TEMP_SENSOR_2_CPU_VR] = { .name = "CPU VR",
+				   .type = TEMP_SENSOR_TYPE_BOARD,
+				   .read = get_temp_3v3_30k9_47k_4050b,
+				   .idx = ADC_TEMP_SENSOR_2_CPU_VR },
+	[TEMP_SENSOR_3_WIFI] = { .name = "WIFI",
+				 .type = TEMP_SENSOR_TYPE_BOARD,
+				 .read = get_temp_3v3_30k9_47k_4050b,
+				 .idx = ADC_TEMP_SENSOR_3_WIFI },
+	[TEMP_SENSOR_4_DIMM] = { .name = "DIMM",
+				 .type = TEMP_SENSOR_TYPE_BOARD,
+				 .read = get_temp_3v3_30k9_47k_4050b,
+				 .idx = ADC_TEMP_SENSOR_4_DIMM },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/*
+ * TODO(b/180681346): update for Alder Lake/brya
+ *
+ * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
+ * 130 C.  However, sensor is located next to DDR, so we need to use the lower
+ * DDR temperature limit (85 C)
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+		}, \
+		.temp_fan_off = C_TO_K(40), \
+		.temp_fan_max = C_TO_K(80), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
+
+/*
+ * TODO(b/197478860): add the thermal sensor setting
+ */
+/* this should really be "const" */
+struct ec_thermal_config thermal_params[] = {
+	[TEMP_SENSOR_1_CPU] = THERMAL_CPU,
+	[TEMP_SENSOR_2_CPU_VR] = THERMAL_CPU,
+	[TEMP_SENSOR_3_WIFI] = THERMAL_CPU,
+	[TEMP_SENSOR_4_DIMM] = THERMAL_CPU,
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
diff --git a/board/gladios/usbc_config.c b/board/gladios/usbc_config.c
new file mode 100644
index 0000000000..c010eb1333
--- /dev/null
+++ b/board/gladios/usbc_config.c
@@ -0,0 +1,162 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/bc12/pi3usb9201_public.h"
+#include "driver/ppc/syv682x_public.h"
+#include "driver/retimer/ps8818_public.h"
+#include "driver/tcpm/rt1715.h"
+#include "driver/tcpm/tcpci.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "system.h"
+#include "task.h"
+#include "task_id.h"
+#include "timer.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+/* USBC TCPC configuration */
+const struct tcpc_config_t tcpc_config[] = {
+	[USBC_PORT_C0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0_TCPC,
+			.addr_flags = RT1715_I2C_ADDR_FLAGS,
+		},
+		.drv = &rt1715_tcpm_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
+BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
+
+/* USBC PPC configuration */
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_PPC_BC12,
+		.i2c_addr_flags = SYV682X_ADDR2_FLAGS,
+		.drv = &syv682x_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
+
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/* USBC mux configuration - Alder Lake includes internal mux */
+static const struct usb_mux_chain usbc0_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+
+static int board_c0_ps8818_mux_set(const struct usb_mux *me,
+				   mux_state_t mux_state)
+{
+	if (mux_state & USB_PD_MUX_DP_ENABLED)
+		gpio_set_level(GPIO_USB_C0_HPD, 1);
+	else
+		gpio_set_level(GPIO_USB_C0_HPD, 0);
+
+	return 0;
+}
+
+const struct usb_mux_chain usb_muxes[] = {
+	[USBC_PORT_C0] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &ps8818_usb_retimer_driver,
+			.i2c_port = I2C_PORT_USB_C0_MUX,
+			.i2c_addr_flags = PS8818_I2C_ADDR3_FLAGS,
+			.board_set = &board_c0_ps8818_mux_set,
+		},
+		.next = &usbc0_tcss_usb_mux,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
+
+/* BC1.2 charger detect configuration */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_PPC_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
+
+void board_reset_pd_mcu(void)
+{
+	/* Using RT1716, no reset available for TCPC */
+}
+
+static void board_tcpc_init(void)
+{
+	/* Don't reset TCPCs after initial reset */
+	if (!system_jumped_late())
+		board_reset_pd_mcu();
+
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_C2_TCPC_INT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (gpio_get_level(GPIO_USB_C0_C2_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_0;
+
+	return status;
+}
+
+int ppc_get_alert_status(int port)
+{
+	if (port == USBC_PORT_C0)
+		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
+
+	return 0;
+}
+
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	schedule_deferred_pd_interrupt(USBC_PORT_C0);
+}
+
+void bc12_interrupt(enum gpio_signal signal)
+{
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	syv682x_interrupt(USBC_PORT_C0);
+}
+
+void retimer_interrupt(enum gpio_signal signal)
+{
+	/*
+	 * TODO(b/179513527): add USB-C support
+	 */
+}
diff --git a/board/gladios/usbc_config.h b/board/gladios/usbc_config.h
new file mode 100644
index 0000000000..4c3f7ee4d8
--- /dev/null
+++ b/board/gladios/usbc_config.h
@@ -0,0 +1,15 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Gladios board-specific USB-C configuration */
+
+#ifndef __CROS_EC_USBC_CONFIG_H
+#define __CROS_EC_USBC_CONFIG_H
+
+#define CONFIG_USB_PD_PORT_MAX_COUNT 1
+
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_COUNT };
+
+#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/gladios/vif_override.xml b/board/gladios/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/gladios/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/glkrvp/battery.c b/board/glkrvp/battery.c
deleted file mode 100644
index cccf3c1016..0000000000
--- a/board/glkrvp/battery.c
+++ /dev/null
@@ -1,241 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery.h"
-#include "charger_profile_override.h"
-#include "console.h"
-#include "pca9555.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-
-#define I2C_PORT_PCA555_BATT_PRESENT_GPIO	NPCX_I2C_PORT0_0
-#define I2C_ADDR_PCA555_BATT_PRESENT_GPIO_FLAGS	0x21
-#define PCA555_BATT_PRESENT_GPIO_READ(reg, data) \
-	pca9555_read(I2C_PORT_PCA555_BATT_PRESENT_GPIO,			\
-		     I2C_ADDR_PCA555_BATT_PRESENT_GPIO_FLAGS, (reg), (data))
-
-/* Shutdown mode parameter to write to manufacturer access register */
-#define SB_SHUTDOWN_DATA        0x0010
-
-enum fast_chg_voltage_ranges {
-	VOLTAGE_RANGE_0,
-	VOLTAGE_RANGE_1,
-	VOLTAGE_RANGE_2,
-};
-
-enum temp_range {
-	TEMP_RANGE_0,
-	TEMP_RANGE_1,
-	TEMP_RANGE_2,
-	TEMP_RANGE_3,
-	TEMP_RANGE_4,
-	TEMP_RANGE_5,
-};
-
-/* keep track of previous charge profile info */
-static const struct fast_charge_profile *prev_chg_profile_info;
-
-/* SMP-CA-445 battery & BQ30Z554 fuel gauge */
-static const struct battery_info batt_info_smp_ca445 = {
-	.voltage_max = 8700,		/* mV */
-	.voltage_normal = 7600,
-
-	/*
-	 * Actual value 6000mV, added 100mV for charger accuracy so that
-	 * unwanted low VSYS_Prochot# assertion can be avoided.
-	 */
-	.voltage_min = 6100,
-	.precharge_current = 150,	/* mA */
-	.start_charging_min_c = 0,
-	.start_charging_max_c = 45,
-	.charging_min_c = 0,
-	.charging_max_c = 45,
-	.discharging_min_c = -20,
-	.discharging_max_c = 60,
-};
-
-const struct battery_info *battery_get_info(void)
-{
-	static struct battery_info batt_info;
-
-	if (battery_is_present() == BP_YES)
-		return &batt_info_smp_ca445;
-
-	/*
-	 * In no battery condition, to avoid voltage drop on VBATA set
-	 * the battery minimum voltage to the battery maximum voltage.
-	 */
-
-	batt_info = batt_info_smp_ca445;
-	batt_info.voltage_min = batt_info.voltage_max;
-
-	return &batt_info;
-}
-
-static const struct fast_charge_profile fast_charge_smp_ca445_info[] = {
-	/* < 0C */
-	[TEMP_RANGE_0] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(-1),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 0,
-			[VOLTAGE_RANGE_1] = 0,
-			[VOLTAGE_RANGE_2] = 0,
-		},
-	},
-
-	/* 0C >= && <=15C */
-	[TEMP_RANGE_1] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(15),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 890,
-			[VOLTAGE_RANGE_1] = 445,
-			[VOLTAGE_RANGE_2] = 445,
-		},
-	},
-
-	/* 15C > && <=20C */
-	[TEMP_RANGE_2] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(20),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 1335,
-			[VOLTAGE_RANGE_1] = 1335,
-			[VOLTAGE_RANGE_2] = 1335,
-		},
-	},
-
-	/* 20C > && <=45C */
-	[TEMP_RANGE_3] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(45),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 2225,
-			[VOLTAGE_RANGE_1] = 2225,
-			[VOLTAGE_RANGE_2] = 2225,
-		},
-	},
-
-	/* 45C > && <=55C */
-	[TEMP_RANGE_4] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(55),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 1335,
-			[VOLTAGE_RANGE_1] = 1335,
-			[VOLTAGE_RANGE_2] = 0,
-		},
-	},
-
-	/* > 55C */
-	[TEMP_RANGE_5] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(CHARGER_PROF_TEMP_C_LAST_RANGE),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 0,
-			[VOLTAGE_RANGE_1] = 0,
-			[VOLTAGE_RANGE_2] = 0,
-		},
-	},
-};
-
-static const struct fast_charge_params fast_chg_params_smp_ca445 = {
-	.total_temp_ranges = ARRAY_SIZE(fast_charge_smp_ca445_info),
-	.default_temp_range_profile = TEMP_RANGE_3,
-	.voltage_mV = {
-		[VOLTAGE_RANGE_0] = 8000,
-		[VOLTAGE_RANGE_1] = 8200,
-		[VOLTAGE_RANGE_2] = CHARGER_PROF_VOLTAGE_MV_LAST_RANGE,
-	},
-	.chg_profile_info = &fast_charge_smp_ca445_info[0],
-};
-
-/*
- * This can override the smart battery's charging profile. To make a change,
- * modify one or more of requested_voltage, requested_current, or state.
- * Leave everything else unchanged.
- *
- * Return the next poll period in usec, or zero to use the default (which is
- * state dependent).
- */
-int charger_profile_override(struct charge_state_data *curr)
-{
-	/*
-	 * If battery present and not in cut off and almost full
-	 * then if it does not want charge then discharge on AC
-	 */
-	if ((battery_is_present() == BP_YES) &&
-	    !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
-	    (curr->batt.status & STATUS_FULLY_CHARGED)) {
-		charger_discharge_on_ac(1);
-		curr->state = ST_DISCHARGE;
-		return 0;
-	}
-
-	charger_discharge_on_ac(0);
-
-	return charger_profile_override_common(curr,
-			&fast_chg_params_smp_ca445,
-			&prev_chg_profile_info,
-			batt_info_smp_ca445.voltage_max);
-}
-
-int board_cut_off_battery(void)
-{
-	int rv;
-
-	/* Ship mode command must be sent twice to take effect */
-	rv = sb_write(SB_MANUFACTURER_ACCESS, SB_SHUTDOWN_DATA);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	return sb_write(SB_MANUFACTURER_ACCESS, SB_SHUTDOWN_DATA);
-}
-
-static inline int batt_smp_cos4870_is_initialized(void)
-{
-	int batt_status;
-
-	return battery_status(&batt_status) ? 0 :
-		batt_status & STATUS_INITIALIZED;
-}
-
-enum battery_present battery_hw_present(void)
-{
-	int data;
-	int rv;
-
-	rv = PCA555_BATT_PRESENT_GPIO_READ(PCA9555_CMD_INPUT_PORT_0, &data);
-
-	/* GPIO is low when the battery is physically present */
-	return rv || (data & PCA9555_IO_5) ? BP_NO : BP_YES;
-}
-
-/*
- * Physical detection of battery.
- */
-enum battery_present battery_is_present(void)
-{
-	static enum battery_present batt_pres_prev = BP_NOT_SURE;
-	enum battery_present batt_pres;
-
-	/* Get the physical hardware status */
-	batt_pres = battery_hw_present();
-
-	/*
-	 * Make sure battery status is implemented, I2C transactions are
-	 * success & the battery status is Initialized to find out if it
-	 * is a working battery and it is not in the cut-off mode.
-	 *
-	 * FETs are turned off after Power Shutdown time.
-	 * The device will wake up when a voltage is applied to PACK.
-	 * Battery status will be inactive until it is initialized.
-	 */
-	if (batt_pres == BP_YES && batt_pres_prev != batt_pres &&
-		!battery_is_cut_off() && !batt_smp_cos4870_is_initialized())
-		batt_pres = BP_NO;
-
-	batt_pres_prev = batt_pres;
-
-	return batt_pres;
-}
diff --git a/board/glkrvp/board.c b/board/glkrvp/board.c
deleted file mode 100644
index c4b3ce6e38..0000000000
--- a/board/glkrvp/board.c
+++ /dev/null
@@ -1,186 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel GLK-RVP board-specific configuration */
-
-#include "button.h"
-#include "charger.h"
-#include "chipset.h"
-#include "console.h"
-#include "driver/charger/isl923x.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "pca9555.h"
-#include "power.h"
-#include "power_button.h"
-#include "spi.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "uart.h"
-#include "util.h"
-
-#include "gpio_list.h"
-
-#define I2C_PORT_PCA555_PMIC_GPIO	NPCX_I2C_PORT0_0
-#define I2C_ADDR_PCA555_PMIC_GPIO_FLAGS	0x21
-#define PCA555_PMIC_GPIO_WRITE(reg, data) \
-		pca9555_write(I2C_PORT_PCA555_PMIC_GPIO, \
-			I2C_ADDR_PCA555_PMIC_GPIO_FLAGS, (reg), (data))
-#define PCA555_PMIC_GPIO_READ(reg, data) \
-		pca9555_read(I2C_PORT_PCA555_PMIC_GPIO, \
-			I2C_ADDR_PCA555_PMIC_GPIO_FLAGS, (reg), (data))
-
-#define I2C_PORT_PCA555_BOARD_ID_GPIO	NPCX_I2C_PORT0_0
-#define I2C_ADDR_PCA555_BOARD_ID_GPIO_FLAGS	0x20
-#define PCA555_BOARD_ID_GPIO_READ(reg, data) \
-		pca9555_read(I2C_PORT_PCA555_BOARD_ID_GPIO, \
-			I2C_ADDR_PCA555_BOARD_ID_GPIO_FLAGS, (reg), (data))
-
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"pmic",      NPCX_I2C_PORT0_0, 100, GPIO_I2C0_SCL, GPIO_I2C0_SDA},
-	{"typec",     NPCX_I2C_PORT7_0, 400, GPIO_I2C7_SCL, GPIO_I2C7_SDA},
-	{"master1",   NPCX_I2C_PORT1_0, 400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"master2",   NPCX_I2C_PORT2_0, 100, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-	{"charger",   NPCX_I2C_PORT3_0, 100, GPIO_I2C3_SCL, GPIO_I2C3_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* Charger chips */
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-/* Wake-up pins for hibernate */
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_AC_PRESENT,
-	GPIO_LID_OPEN,
-	GPIO_POWER_BUTTON_L,
-};
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-/* Called by APL power state machine when transitioning from G3 to S5 */
-void chipset_pre_init_callback(void)
-{
-	int data;
-
-	if (PCA555_PMIC_GPIO_READ(PCA9555_CMD_OUTPUT_PORT_0, &data))
-		return;
-
-	/*
-	 * No need to re-init PMIC since settings are sticky across sysjump.
-	 * However, be sure to check that PMIC is already enabled. If it is
-	 * then there's no need to re-sequence the PMIC.
-	 */
-	if (system_jumped_to_this_image() && (data & PCA9555_IO_0))
-		return;
-
-	/* Enable SOC_3P3_EN_L: Set the Output port O0.1 to low level */
-	data &= ~PCA9555_IO_1;
-	PCA555_PMIC_GPIO_WRITE(PCA9555_CMD_OUTPUT_PORT_0, data);
-
-	/* TODO: Find out from the spec */
-	msleep(10);
-
-	/* Enable PMIC_EN: Set the Output port O0.0 to high level */
-	PCA555_PMIC_GPIO_WRITE(PCA9555_CMD_OUTPUT_PORT_0, data | PCA9555_IO_0);
-}
-
-/* Initialize board. */
-static void board_init(void)
-{
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_FIRST);
-
-/* Called on AP S5 -> S3 transition */
-static void board_chipset_startup(void)
-{
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S5 transition */
-static void board_chipset_shutdown(void)
-{
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
-
-void chipset_do_shutdown(void)
-{
-	int data;
-
-	if (PCA555_PMIC_GPIO_READ(PCA9555_CMD_OUTPUT_PORT_0, &data))
-		return;
-
-	/* Disable SOC_3P3_EN_L: Set the Output port O0.1 to high level */
-	data |= PCA9555_IO_1;
-	PCA555_PMIC_GPIO_WRITE(PCA9555_CMD_OUTPUT_PORT_0, data);
-
-	/* TODO: Find out from the spec */
-	msleep(10);
-
-	/* Disable PMIC_EN: Set the Output port O0.0 to low level */
-	PCA555_PMIC_GPIO_WRITE(PCA9555_CMD_OUTPUT_PORT_0, data & ~PCA9555_IO_0);
-}
-
-void board_hibernate_late(void)
-{
-}
-
-void board_hibernate(void)
-{
-	/*
-	 * To support hibernate called from console commands, ectool commands
-	 * and key sequence, shutdown the AP before hibernating.
-	 */
-	chipset_do_shutdown();
-
-	/* Added delay to allow AP to settle down */
-	msleep(100);
-}
-
-int board_get_version(void)
-{
-	int data;
-
-	if (PCA555_BOARD_ID_GPIO_READ(PCA9555_CMD_INPUT_PORT_1, &data))
-		return -1;
-
-	return data & 0x0f;
-}
-
-static void pmic_init(void)
-{
-	/* No need to re-init PMIC since settings are sticky across sysjump. */
-	if (system_jumped_late())
-		return;
-
-	/*
-	 * PMIC INIT
-	 * Configure Port O0.0 as Output port - PMIC_EN
-	 * Configure Port O0.1 as Output port - SOC_3P3_EN_L
-	 */
-	PCA555_PMIC_GPIO_WRITE(PCA9555_CMD_CONFIGURATION_PORT_0, 0xfc);
-
-	/*
-	 * Set the Output port O0.0 to low level - PMIC_EN
-	 * Set the Output port O0.1 to high level - SOC_3P3_EN_L
-	 *
-	 * POR of PCA9555 port is input with high impedance hence explicitly
-	 * configure the SOC_3P3_EN_L to high level.
-	 */
-	PCA555_PMIC_GPIO_WRITE(PCA9555_CMD_OUTPUT_PORT_0, 0xfe);
-}
-DECLARE_HOOK(HOOK_INIT, pmic_init, HOOK_PRIO_INIT_I2C + 1);
diff --git a/board/glkrvp/board.h b/board/glkrvp/board.h
deleted file mode 100644
index 138aa478bf..0000000000
--- a/board/glkrvp/board.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel GLK-RVP board-specific configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/*
- * Allow dangerous commands.
- * TODO: Remove this config before production.
- */
-#define CONFIG_SYSTEM_UNLOCKED
-
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
-#undef CONFIG_HOSTCMD_DEBUG_MODE
-
-/*
- * By default, enable all console messages excepted HC, ACPI and event:
- * The sensor stack is generating a lot of activity.
- */
-#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
-
-/* EC console commands  */
-
-/* Battery */
-#define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_PRESENT_CUSTOM
-#define CONFIG_BATTERY_SMART
-
-/* Charger */
-#define CONFIG_CHARGE_MANAGER
-#define CONFIG_CHARGER
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT 512
-#define CONFIG_CHARGER_ISL9238
-#define CONFIG_CHARGER_PROFILE_OVERRIDE
-#define CONFIG_CHARGER_PROFILE_OVERRIDE_COMMON
-#undef  CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES
-#define CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES 3
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
-#undef  CONFIG_EXTPOWER_DEBOUNCE_MS
-#define CONFIG_EXTPOWER_DEBOUNCE_MS 1000
-#define CONFIG_EXTPOWER_GPIO
-
-/* DC Jack charge ports */
-#undef  CONFIG_DEDICATED_CHARGE_PORT_COUNT
-#define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1
-#define DEDICATED_CHARGE_PORT 2
-
-/* Keyboard */
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-
-/* UART */
-#define NPCX_UART_MODULE2    1 /* 0:GPIO10/11 1:GPIO64/65 as UART */
-#define NPCX7_PWM1_SEL       0 /* GPIO C2 is not used as PWM1. */
-
-/* USB-A config */
-
-/* USB PD config */
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT TYPEC_RP_3A0
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV1
-
-/* USB MUX */
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USB_MUX_PS8743
-
-/* SoC / PCH */
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_CHIPSET_GEMINILAKE
-#define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_X86
-#define CONFIG_POWER_COMMON
-#define CONFIG_POWER_S0IX
-#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-
-/* EC */
-#define CONFIG_BOARD_VERSION_CUSTOM
-#define CONFIG_VOLUME_BUTTONS
-#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
-#define CONFIG_WP_ALWAYS
-#define CONFIG_FLASH_READOUT_PROTECTION
-#define CONFIG_I2C
-#define CONFIG_I2C_MASTER
-
-#define CONFIG_LID_SWITCH
-#define CONFIG_LTO
-
-#define CONFIG_LOW_POWER_IDLE
-
-#define CONFIG_FLASH_SIZE 524288
-#define CONFIG_SPI_FLASH_REGS
-#define CONFIG_SPI_FLASH_W25Q40
-
-/* Verified boot */
-#define CONFIG_SHA256_UNROLLED
-#define CONFIG_VBOOT_HASH
-/*
- * Enable 1 slot of secure temporary storage to support
- * suspend/resume with read/write memory training.
- */
-#define CONFIG_VSTORE
-#define CONFIG_VSTORE_SLOT_COUNT 1
-
-/* Optional feature - used by nuvoton */
-#define NPCX_JTAG_MODULE2    0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/
-#define NPCX_TACH_SEL2       0 /* 0:GPIO40/A4 1:GPIO93/D3 as TACH */
-
-/* I2C ports */
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT3_0
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT3_0
-#define I2C_PORT_USB_MUX	NPCX_I2C_PORT7_0
-
-/* EC exclude modules */
-#undef CONFIG_ADC
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum adc_channel {
-	ADC_VBUS,
-	ADC_CH_COUNT,
-};
-
-int board_get_version(void);
-
-/* TODO: Verify the numbers below. */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
-
-/* Define typical operating power and max power */
-#define PD_OPERATING_POWER_MW  15000
-#define PD_MAX_POWER_MW        45000
-#define PD_MAX_CURRENT_MA      3000
-#define PD_MAX_VOLTAGE_MV      20000
-#define DC_JACK_MAX_VOLTAGE_MV 19000
-
-/* Reset PD MCU */
-void board_reset_pd_mcu(void);
-void tcpc_alert_event(enum gpio_signal signal);
-void board_charging_enable(int port, int enable);
-void board_vbus_enable(int port, int enable);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/glkrvp/build.mk b/board/glkrvp/build.mk
deleted file mode 100644
index 235514e22b..0000000000
--- a/board/glkrvp/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6g
-
-board-y=board.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
-board-$(CONFIG_USB_POWER_DELIVERY)+=chg_usb_pd.o usb_pd_policy.o
diff --git a/board/glkrvp/chg_usb_pd.c b/board/glkrvp/chg_usb_pd.c
deleted file mode 100644
index f8e8520b72..0000000000
--- a/board/glkrvp/chg_usb_pd.c
+++ /dev/null
@@ -1,263 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "console.h"
-#include "hooks.h"
-#include "task.h"
-#include "tcpci.h"
-#include "system.h"
-#include "usb_mux.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-#define PTN5110_EXT_GPIO_CONFIG		0x92
-#define PTN5110_EXT_GPIO_CONTROL	0x93
-
-#define PTN5110_EXT_GPIO_FRS_EN			BIT(6)
-#define PTN5110_EXT_GPIO_EN_SRC			BIT(5)
-#define PTN5110_EXT_GPIO_EN_SNK1		BIT(4)
-#define PTN5110_EXT_GPIO_IILIM_5V_VBUS_L	BIT(3)
-
-enum glkrvp_charge_ports {
-	TYPE_C_PORT_0,
-	TYPE_C_PORT_1,
-	DC_JACK_PORT_0 = DEDICATED_CHARGE_PORT,
-};
-
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = NPCX_I2C_PORT7_0,
-			.addr_flags = 0x50,
-		},
-		.drv = &tcpci_tcpm_drv,
-	},
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = NPCX_I2C_PORT7_0,
-			.addr_flags = 0x52,
-		},
-		.drv = &tcpci_tcpm_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == CONFIG_USB_PD_PORT_MAX_COUNT);
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = 0x10,
-		.driver = &ps8743_usb_mux_driver,
-	},
-	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = 0x11,
-		.driver = &ps8743_usb_mux_driver,
-	},
-};
-
-static int board_charger_port_is_sourcing_vbus(int port)
-{
-	int reg;
-
-	if (tcpc_read(port, PTN5110_EXT_GPIO_CONTROL, &reg))
-		return 0;
-
-	return !!(reg & PTN5110_EXT_GPIO_EN_SRC);
-}
-
-static int ptn5110_ext_gpio_enable(int port, int enable, int gpio)
-{
-	int reg;
-	int rv;
-
-	rv = tcpc_read(port, PTN5110_EXT_GPIO_CONTROL, &reg);
-	if (rv)
-		return rv;
-
-	if (enable)
-		reg |= gpio;
-	else
-		reg &= ~gpio;
-
-	return tcpc_write(port, PTN5110_EXT_GPIO_CONTROL, reg);
-}
-
-void board_charging_enable(int port, int enable)
-{
-	ptn5110_ext_gpio_enable(port, enable, PTN5110_EXT_GPIO_EN_SNK1);
-}
-
-void board_vbus_enable(int port, int enable)
-{
-	ptn5110_ext_gpio_enable(port, enable, PTN5110_EXT_GPIO_EN_SRC);
-}
-
-void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_PD_INT_ODL:
-		port = 0;
-		break;
-	case GPIO_USB_C1_PD_INT_ODL:
-		port = 1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-void board_tcpc_init(void)
-{
-	/* Only reset TCPC if not sysjump */
-	if (!system_jumped_late())
-		board_reset_pd_mcu();
-
-	/* Enable TCPC0/1 interrupt */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
-
-int board_tcpc_post_init(int port)
-{
-	int reg;
-	int rv;
-
-	rv = tcpc_read(port, PTN5110_EXT_GPIO_CONFIG, &reg);
-	if (rv)
-		return rv;
-
-	/* Configure PTN5110 External GPIOs as output */
-	reg |=  PTN5110_EXT_GPIO_EN_SRC | PTN5110_EXT_GPIO_EN_SNK1 |
-		PTN5110_EXT_GPIO_IILIM_5V_VBUS_L;
-	rv = tcpc_write(port, PTN5110_EXT_GPIO_CONFIG, reg);
-	if (rv)
-		return rv;
-
-	return ptn5110_ext_gpio_enable(port, 1,
-					PTN5110_EXT_GPIO_IILIM_5V_VBUS_L);
-}
-
-/* Reset PD MCU */
-void board_reset_pd_mcu(void)
-{
-	/* TODO: Add reset logic */
-}
-
-static inline int board_dc_jack_present(void)
-{
-	return !gpio_get_level(GPIO_DC_JACK_PRESENT_L);
-}
-
-static void board_dc_jack_handle(void)
-{
-	struct charge_port_info charge_dc_jack;
-
-	/* System is booted from DC Jack */
-	if (board_dc_jack_present()) {
-		charge_dc_jack.current = (PD_MAX_POWER_MW * 1000) /
-					DC_JACK_MAX_VOLTAGE_MV;
-		charge_dc_jack.voltage = DC_JACK_MAX_VOLTAGE_MV;
-	} else {
-		charge_dc_jack.current = 0;
-		charge_dc_jack.voltage = USB_CHARGER_VOLTAGE_MV;
-	}
-
-	charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED,
-				DC_JACK_PORT_0, &charge_dc_jack);
-}
-DECLARE_HOOK(HOOK_AC_CHANGE, board_dc_jack_handle, HOOK_PRIO_FIRST);
-
-static void board_charge_init(void)
-{
-	int port, supplier;
-
-	/* Initialize all charge suppliers to seed the charge manager */
-	for (port = 0; port < CHARGE_PORT_COUNT; port++) {
-		for (supplier = 0; supplier < CHARGE_SUPPLIER_COUNT; supplier++)
-			charge_manager_update_charge(supplier, port, NULL);
-	}
-
-	board_dc_jack_handle();
-}
-DECLARE_HOOK(HOOK_INIT, board_charge_init, HOOK_PRIO_DEFAULT);
-
-int board_set_active_charge_port(int port)
-{
-	/* if it's a PD port and sourcing VBUS, don't enable */
-	if (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT)
-		if (board_charger_port_is_sourcing_vbus(port)) {
-			CPRINTS("Skip enable p%d", port);
-			return EC_ERROR_INVAL;
-		}
-
-	/*
-	 * Do not enable Type-C port if the DC Jack is present.
-	 * When the Type-C is active port, hardware circuit will
-	 * block DC jack from enabling +VADP_OUT.
-	 */
-	if (port != DC_JACK_PORT_0 && board_dc_jack_present()) {
-		CPRINTS("DC Jack present, Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	/* Make sure non-charging port is disabled */
-	switch (port) {
-	case TYPE_C_PORT_0:
-		board_charging_enable(TYPE_C_PORT_1, 0);
-		board_charging_enable(TYPE_C_PORT_0, 1);
-		break;
-	case TYPE_C_PORT_1:
-		board_charging_enable(TYPE_C_PORT_0, 0);
-		board_charging_enable(TYPE_C_PORT_1, 1);
-		break;
-	case DC_JACK_PORT_0:
-	case CHARGE_PORT_NONE:
-	default:
-		/* Disable both Type-C ports */
-		board_charging_enable(TYPE_C_PORT_0, 0);
-		board_charging_enable(TYPE_C_PORT_1, 0);
-		break;
-	}
-
-	return EC_SUCCESS;
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_0;
-
-	if (!gpio_get_level(GPIO_USB_C1_PD_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_set_input_current_limit(MAX(charge_ma,
-				CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
-
-int adc_read_channel(enum adc_channel ch)
-{
-	return 0;
-}
diff --git a/board/glkrvp/ec.tasklist b/board/glkrvp/ec.tasklist
deleted file mode 100644
index 8fecf61480..0000000000
--- a/board/glkrvp/ec.tasklist
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel RVP board-specific configuration */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/glkrvp/gpio.inc b/board/glkrvp/gpio.inc
deleted file mode 100644
index a173ba6333..0000000000
--- a/board/glkrvp/gpio.inc
+++ /dev/null
@@ -1,180 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel GLK-RVP board-specific configuration */
-
-/*
- * Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first.
- */
-
-/* Power sequencing interrupts */
-GPIO_INT(SUSPWRDNACK,	PIN(0, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(RSMRST_L_PGOOD,PIN(3, 6), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(ALL_SYS_PGOOD,	PIN(7, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PCH_SLP_S0_L,	PIN(8, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PCH_SLP_S3_L,	PIN(8, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PCH_SLP_S4_L,	PIN(8, 6), GPIO_INT_BOTH, power_signal_interrupt)
-
-/* Button interrupts */
-GPIO_INT(LID_OPEN,		PIN(0, 3), GPIO_INT_BOTH | GPIO_PULL_UP, lid_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL,	PIN(3, 4), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLDN_BTN_ODL,	PIN(3, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(POWER_BUTTON_L,	PIN(A, 6), GPIO_INT_BOTH, power_button_interrupt)
-
-/* Type-C interrupts */
-GPIO_INT(USB_C0_PD_INT_ODL,	PIN(6, 2), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C1_PD_INT_ODL,	PIN(6, 3), GPIO_INT_FALLING, tcpc_alert_event)
-
-GPIO_INT(AC_PRESENT,	PIN(D, 2), GPIO_INT_BOTH, extpower_interrupt)
-GPIO_INT(WP_L,		PIN(9, 3), GPIO_INT_BOTH | GPIO_SEL_1P8V, switch_interrupt)
-
-UNIMPLEMENTED(PP3300_PG)
-UNIMPLEMENTED(PP5000_PG)
-
-/* Power sequencing GPIOs */
-GPIO(SYS_RESET_L,	PIN(0, 0), GPIO_ODR_HIGH)
-GPIO(PCH_RSMRST_L,	PIN(0, 1), GPIO_OUT_LOW)
-GPIO(SMC_SHUTDOWN,	PIN(3, 3), GPIO_OUT_LOW | GPIO_PULL_DOWN)
-GPIO(PCH_SYS_PWROK,	PIN(3, 5), GPIO_OUT_LOW)
-GPIO(PCH_PWRBTN_L,	PIN(7, 5), GPIO_ODR_HIGH)
-/*
- * PCH_PROCHOT_ODL is primarily for monitoring the PROCHOT# signal which is
- * normally driven by the PMIC. The EC can also drive this signal in the event
- * that the ambient or charger temperature sensors exceeds their thresholds.
- */
-GPIO(CPU_PROCHOT,	PIN(A, 3), GPIO_INPUT)		/* PCH_PROCHOT_ODL */
-
-/* Host communication GPIOs */
-GPIO(PCH_WAKE_L,	PIN(C, 1), GPIO_ODR_HIGH)
-
-GPIO(DC_JACK_PRESENT_L,	PIN(7, 0), GPIO_INPUT)		/* DC Jack presence coming from +V3P3_A_KBC */
-GPIO(USBC_LDO_ENABLE,	PIN(7, 1), GPIO_OUT_HIGH)	/* USB TCPC to enable LDO in dead battery */
-GPIO(ENABLE_BACKLIGHT,	PIN(9, 7), GPIO_ODR_HIGH)
-GPIO(ENTERING_RW,	PIN(A, 7), GPIO_OUTPUT)		/* EC_ENTERING_RW */
-
-/*
- * I2C pins should be configured as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-GPIO(I2C0_SCL,	PIN(B, 5), GPIO_ODR_HIGH)
-GPIO(I2C0_SDA,	PIN(B, 4), GPIO_ODR_HIGH)
-GPIO(I2C1_SCL,	PIN(9, 0), GPIO_ODR_HIGH)
-GPIO(I2C1_SDA,	PIN(8, 7), GPIO_ODR_HIGH)
-GPIO(I2C2_SCL,	PIN(9, 2), GPIO_ODR_HIGH)
-GPIO(I2C2_SDA,	PIN(9, 1), GPIO_ODR_HIGH)
-GPIO(I2C3_SCL,	PIN(D, 1), GPIO_ODR_HIGH)
-GPIO(I2C3_SDA,	PIN(D, 0), GPIO_ODR_HIGH)
-GPIO(I2C7_SCL,	PIN(B, 3), GPIO_ODR_HIGH)
-GPIO(I2C7_SDA,	PIN(B, 2), GPIO_ODR_HIGH)
-
-/* LPC / eSPI signals */
-#if 0
-GPIO(LAD0_eSPI_IO0,	PIN(4, 6), GPIO_INPUT)	/* LAD0 / eSPI_IO0 */
-GPIO(LAD1_eSPI_IO1,	PIN(4, 7), GPIO_INPUT)	/* LAD1 / eSPI_IO1 */
-GPIO(LAD2_eSPI_IO2,	PIN(5, 1), GPIO_INPUT)	/* LAD2 / eSPI_IO2 */
-GPIO(LAD3_eSPI_IO3,	PIN(5, 2), GPIO_INPUT)	/* LAD3 / eSPI_IO3 */
-GPIO(LFRAME_eSPI_CS,	PIN(5, 3), GPIO_INPUT)	/* LFRAME / eSPI_CS */
-GPIO(LRESET_eSPI_RST,	PIN(5, 4), GPIO_INPUT)	/* LRESET / eSPI_RST */
-GPIO(PCI_CLK_eSPI_CLK,	PIN(5, 5), GPIO_INPUT)	/* PCI_CLK / eSPI_CLK */
-GPIO(CLKRUN,		PIN(5, 6), GPIO_INPUT)	/* CLKRUN */
-GPIO(SER_IRQ_eSPI_ALERT,PIN(5, 7), GPIO_INPUT)	/* SER_IRQ / eSPI_ALERT */
-#endif
-
-/* Unused pins 3.3V & Interruptable */
-GPIO(NC_04,	PIN(0, 4), GPIO_INPUT | GPIO_PULL_UP)
-
-GPIO(NC_40,	PIN(4, 0), GPIO_INPUT)	/* TA1_TACH1 */
-GPIO(NC_41,	PIN(4, 1), GPIO_INPUT | GPIO_PULL_UP)	/* ADC4 */
-GPIO(NC_42,	PIN(4, 2), GPIO_INPUT | GPIO_PULL_UP)	/* ADC3 */
-GPIO(NC_43,	PIN(4, 3), GPIO_INPUT | GPIO_PULL_UP)	/* ADC2 */
-GPIO(NC_44,	PIN(4, 4), GPIO_INPUT | GPIO_PULL_UP)	/* ADC1 */
-GPIO(NC_45,	PIN(4, 5), GPIO_INPUT | GPIO_PULL_UP)	/* ADC5 */
-
-GPIO(NC_60,	PIN(6, 0), GPIO_INPUT)	/* PWM7 */
-GPIO(NC_61,	PIN(6, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(NC_67,	PIN(6, 7), GPIO_INPUT)	/* Wake-up button */
-
-GPIO(NC_73,	PIN(7, 3), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(NC_74,	PIN(7, 4), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(NC_76,	PIN(7, 6), GPIO_INPUT | GPIO_PULL_UP) /* SCI */
-
-GPIO(NC_80,	PIN(8, 0), GPIO_INPUT)	/* PWM3 */
-GPIO(NC_82,	PIN(8, 2), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(NC_83,	PIN(8, 3), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(NC_84,	PIN(8, 4), GPIO_INPUT | GPIO_PULL_UP)
-
-GPIO(NC_B1,	PIN(B, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(NC_B7,	PIN(B, 7), GPIO_INPUT)	/* PWM5 */
-
-GPIO(NC_C0,	PIN(C, 0), GPIO_INPUT)	/* PWM6 */
-GPIO(NC_C2,	PIN(C, 2), GPIO_INPUT)	/* PWM1 */
-GPIO(NC_C3,	PIN(C, 3), GPIO_INPUT)	/* PWM0 */
-GPIO(NC_C4,	PIN(C, 4), GPIO_INPUT)	/* PWM2 */
-GPIO(NC_C5,	PIN(C, 5), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(NC_C7,	PIN(C, 7), GPIO_INPUT | GPIO_PULL_UP)
-
-GPIO(NC_C6,	PIN(C, 6), GPIO_INPUT | GPIO_PULL_UP) /* SMI */
-
-GPIO(NC_D3,	PIN(D, 3), GPIO_INPUT)	/* TB1 */
-
-GPIO(NC_E7,	PIN(E, 7), GPIO_INPUT)	/* 32K_CLKIN */
-
-/* Unused pins: VSPI 3.3V or 1.8V & Interruptable */
-GPIO(NC_94,	PIN(9, 4), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(NC_95,	PIN(9, 5), GPIO_INPUT | GPIO_PULL_UP)
-
-GPIO(NC_A1,	PIN(A, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(NC_A5,	PIN(A, 5), GPIO_INPUT | GPIO_PULL_UP)
-
-GPIO(NC_B0,	PIN(B, 0), GPIO_INPUT | GPIO_PULL_UP)
-
-/* Unused pins 3.3V & Non-Interruptable */
-GPIO(NC_32,	PIN(3, 2), GPIO_INPUT | GPIO_PULL_UP)
-
-GPIO(NC_66,	PIN(6, 6), GPIO_INPUT | GPIO_PULL_UP)
-
-GPIO(NC_B6,	PIN(B, 6), GPIO_INPUT)	/* PWM4 */
-
-/* eSPI: VHIF Unused pins 1.8V & Interruptable */
-GPIO(NC_50,	PIN(5, 0), GPIO_INPUT | GPIO_PULL_UP)
-
-/* Alternate pins for UART */
-ALTERNATE(PIN_MASK(6, 0x30), 1, MODULE_UART, 0)	/* GPIO64/65    */
-
-/* Alternate pins for I2C */
-ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, 0)	/* I2C1:SDA GPIO87 */
-ALTERNATE(PIN_MASK(9, 0x01), 1, MODULE_I2C, 0)	/* I2C1:SCL GPIO90 */
-ALTERNATE(PIN_MASK(9, 0x06), 1, MODULE_I2C, 0)	/* I2C2:SDA/SCL GPIO91/92 */
-ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, 0)	/* I2C7:SDA/SCL GPIOB2/B3 */
-ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0)	/* I2C0:SDA/SCL GPIOB4/B5 */
-ALTERNATE(PIN_MASK(D, 0x03), 1, MODULE_I2C, 0)	/* I2C3:SDA/SCL GPIOD0/D1 */
-
-/* Keyboard pins */
-#define GPIO_KB_INPUT (GPIO_INPUT)
-#define GPIO_KB_OUTPUT (GPIO_ODR_HIGH)
-
-/* Keyboard Columns */
-/* GPIO05/06/07 */
-ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
-/* GPIO10/11/12/13/14/15/16/17 */
-ALTERNATE(PIN_MASK(1, 0xFF), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
-/* GPIO20/21 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
-
-/* Keyboard Rows */
-/* GPIO22/23/24/25/26/27 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)
-/* GPIO30/31 */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)
-
-/* EC SPI chip */
-#if 0
-GPIO(F_CS0_EC_L,	PIN(A, 0), GPIO_OUT_HIGH | GPIO_PULL_UP)
-ALTERNATE(PIN_MASK(A, 0x14), 1, MODULE_SPI, 0) /* SPI:MOSI/SCLK GPIOA4/A2 */
-ALTERNATE(PIN_MASK(9, 0x40), 1, MODULE_SPI, 0) /* SPI:MISO GPIO96 */
-#endif
diff --git a/board/glkrvp/usb_pd_policy.c b/board/glkrvp/usb_pd_policy.c
deleted file mode 100644
index 19572f7063..0000000000
--- a/board/glkrvp/usb_pd_policy.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "charge_manager.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "gpio.h"
-#include "stddef.h"
-#include "system.h"
-#include "usb_mux.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_set_power_supply_ready(int port)
-{
-	/* Disable charging */
-	board_charging_enable(port, 0);
-
-	/* Provide VBUS */
-	board_vbus_enable(port, 1);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS; /* we are ready */
-}
-
-void pd_power_supply_reset(int port)
-{
-	/* Disable VBUS */
-	board_vbus_enable(port, 0);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_check_vconn_swap(int port)
-{
-	/* in G3, do not allow vconn swap since pp5000_A rail is off */
-	/* TODO: return gpio_get_level(GPIO_PMIC_EN); */
-	return 1;
-}
-
-/* ----------------- Vendor Defined Messages ------------------ */
-#ifdef CONFIG_USB_PD_ALT_MODE_DFP
-static void svdm_dp_post_config(int port)
-{
-	dp_flags[port] |= DP_FLAGS_DP_ON;
-	if (!(dp_flags[port] & DP_FLAGS_HPD_HI_PENDING))
-		return;
-	/* TODO: Update HPD to host */
-}
-
-static int svdm_dp_attention(int port, uint32_t *payload)
-{
-	int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]);
-
-	/* TODO: Read HPD IRQ */
-
-	dp_status[port] = payload[1];
-	if (!(dp_flags[port] & DP_FLAGS_DP_ON)) {
-		if (lvl)
-			dp_flags[port] |= DP_FLAGS_HPD_HI_PENDING;
-		return 1;
-	}
-	/* TODO: Update HPD to host */
-
-	/* ack */
-	return 1;
-}
-#endif /* CONFIG_USB_PD_ALT_MODE_DFP */
diff --git a/board/glkrvp_ite/battery.c b/board/glkrvp_ite/battery.c
deleted file mode 100644
index b2dc6a11c8..0000000000
--- a/board/glkrvp_ite/battery.c
+++ /dev/null
@@ -1,237 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery.h"
-#include "charger_profile_override.h"
-#include "console.h"
-#include "pca9555.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-
-/* Shutdown mode parameter to write to manufacturer access register */
-#define SB_SHUTDOWN_DATA        0x0010
-
-enum fast_chg_voltage_ranges {
-	VOLTAGE_RANGE_0,
-	VOLTAGE_RANGE_1,
-	VOLTAGE_RANGE_2,
-};
-
-enum temp_range {
-	TEMP_RANGE_0,
-	TEMP_RANGE_1,
-	TEMP_RANGE_2,
-	TEMP_RANGE_3,
-	TEMP_RANGE_4,
-	TEMP_RANGE_5,
-};
-
-/* keep track of previous charge profile info */
-static const struct fast_charge_profile *prev_chg_profile_info;
-
-/* SMP-CA-445 battery & BQ30Z554 fuel gauge */
-static const struct battery_info batt_info_smp_ca445 = {
-	.voltage_max = 8700,		/* mV */
-	.voltage_normal = 7600,
-
-	/*
-	 * Actual value 6000mV, added 100mV for charger accuracy so that
-	 * unwanted low VSYS_Prochot# assertion can be avoided.
-	 */
-	.voltage_min = 6100,
-	.precharge_current = 150,	/* mA */
-	.start_charging_min_c = 0,
-	.start_charging_max_c = 45,
-	.charging_min_c = 0,
-	.charging_max_c = 45,
-	.discharging_min_c = -20,
-	.discharging_max_c = 60,
-};
-
-const struct battery_info *battery_get_info(void)
-{
-	static struct battery_info batt_info;
-
-	if (battery_is_present() == BP_YES)
-		return &batt_info_smp_ca445;
-
-	/*
-	 * In no battery condition, to avoid voltage drop on VBATA set
-	 * the battery minimum voltage to the battery maximum voltage.
-	 */
-
-	batt_info = batt_info_smp_ca445;
-	batt_info.voltage_min = batt_info.voltage_max;
-
-	return &batt_info;
-}
-
-static const struct fast_charge_profile fast_charge_smp_ca445_info[] = {
-	/* < 0C */
-	[TEMP_RANGE_0] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(-1),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 0,
-			[VOLTAGE_RANGE_1] = 0,
-			[VOLTAGE_RANGE_2] = 0,
-		},
-	},
-
-	/* 0C >= && <=15C */
-	[TEMP_RANGE_1] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(15),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 890,
-			[VOLTAGE_RANGE_1] = 445,
-			[VOLTAGE_RANGE_2] = 445,
-		},
-	},
-
-	/* 15C > && <=20C */
-	[TEMP_RANGE_2] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(20),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 1335,
-			[VOLTAGE_RANGE_1] = 1335,
-			[VOLTAGE_RANGE_2] = 1335,
-		},
-	},
-
-	/* 20C > && <=45C */
-	[TEMP_RANGE_3] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(45),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 2225,
-			[VOLTAGE_RANGE_1] = 2225,
-			[VOLTAGE_RANGE_2] = 2225,
-		},
-	},
-
-	/* 45C > && <=55C */
-	[TEMP_RANGE_4] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(55),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 1335,
-			[VOLTAGE_RANGE_1] = 1335,
-			[VOLTAGE_RANGE_2] = 0,
-		},
-	},
-
-	/* > 55C */
-	[TEMP_RANGE_5] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(CHARGER_PROF_TEMP_C_LAST_RANGE),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 0,
-			[VOLTAGE_RANGE_1] = 0,
-			[VOLTAGE_RANGE_2] = 0,
-		},
-	},
-};
-
-static const struct fast_charge_params fast_chg_params_smp_ca445 = {
-	.total_temp_ranges = ARRAY_SIZE(fast_charge_smp_ca445_info),
-	.default_temp_range_profile = TEMP_RANGE_3,
-	.voltage_mV = {
-		[VOLTAGE_RANGE_0] = 8000,
-		[VOLTAGE_RANGE_1] = 8200,
-		[VOLTAGE_RANGE_2] = CHARGER_PROF_VOLTAGE_MV_LAST_RANGE,
-	},
-	.chg_profile_info = &fast_charge_smp_ca445_info[0],
-};
-
-/*
- * This can override the smart battery's charging profile. To make a change,
- * modify one or more of requested_voltage, requested_current, or state.
- * Leave everything else unchanged.
- *
- * Return the next poll period in usec, or zero to use the default (which is
- * state dependent).
- */
-int charger_profile_override(struct charge_state_data *curr)
-{
-	/*
-	 * If battery present and not in cut off and almost full
-	 * then if it does not want charge then discharge on AC
-	 */
-	if ((battery_is_present() == BP_YES) &&
-	    !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
-	    (curr->batt.status & STATUS_FULLY_CHARGED)) {
-		charger_discharge_on_ac(1);
-		curr->state = ST_DISCHARGE;
-		return 0;
-	}
-
-	charger_discharge_on_ac(0);
-
-	return charger_profile_override_common(curr,
-			&fast_chg_params_smp_ca445,
-			&prev_chg_profile_info,
-			batt_info_smp_ca445.voltage_max);
-}
-
-int board_cut_off_battery(void)
-{
-	int rv;
-
-	/* Ship mode command must be sent twice to take effect */
-	rv = sb_write(SB_MANUFACTURER_ACCESS, SB_SHUTDOWN_DATA);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	return sb_write(SB_MANUFACTURER_ACCESS, SB_SHUTDOWN_DATA);
-}
-
-static inline int batt_smp_cos4870_is_initialized(void)
-{
-	int batt_status;
-
-	return battery_status(&batt_status) ? 0 :
-		batt_status & STATUS_INITIALIZED;
-}
-
-enum battery_present battery_hw_present(void)
-{
-	int data;
-	int rv;
-
-	rv = pca9555_read(I2C_PORT_PCA555_PMIC_BATT_GPIO,
-			I2C_ADDR_PCA555_PMIC_BATT_GPIO_FLAGS,
-			PCA9555_CMD_INPUT_PORT_0, &data);
-
-	/* GPIO is low when the battery is physically present */
-	return rv || (data & PCA9555_IO_5) ? BP_NO : BP_YES;
-}
-
-/*
- * Physical detection of battery.
- */
-enum battery_present battery_is_present(void)
-{
-	static enum battery_present batt_pres_prev = BP_NOT_SURE;
-	enum battery_present batt_pres;
-
-	/* Get the physical hardware status */
-	batt_pres = battery_hw_present();
-
-	/*
-	 * Make sure battery status is implemented, I2C transactions are
-	 * success & the battery status is Initialized to find out if it
-	 * is a working battery and it is not in the cut-off mode.
-	 *
-	 * FETs are turned off after Power Shutdown time.
-	 * The device will wake up when a voltage is applied to PACK.
-	 * Battery status will be inactive until it is initialized.
-	 */
-	if (batt_pres == BP_YES && batt_pres_prev != batt_pres &&
-		!battery_is_cut_off() && !batt_smp_cos4870_is_initialized())
-		batt_pres = BP_NO;
-
-	batt_pres_prev = batt_pres;
-
-	return batt_pres;
-}
diff --git a/board/glkrvp_ite/board.c b/board/glkrvp_ite/board.c
deleted file mode 100644
index b1102092b0..0000000000
--- a/board/glkrvp_ite/board.c
+++ /dev/null
@@ -1,209 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel GLK-RVP-ITE board-specific configuration */
-
-#include "button.h"
-#include "chipset.h"
-#include "charger.h"
-#include "console.h"
-#include "driver/charger/isl923x.h"
-#include "ec2i_chip.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "intc.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "pca9555.h"
-#include "power.h"
-#include "power_button.h"
-#include "spi.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "uart.h"
-#include "util.h"
-
-#include "gpio_list.h"
-
-#define I2C_PORT_PCA555_BOARD_ID_GPIO	IT83XX_I2C_CH_C
-#define I2C_ADDR_PCA555_BOARD_ID_GPIO_FLAGS	0x20
-
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"charger", IT83XX_I2C_CH_A, 100, GPIO_I2C_A_SCL, GPIO_I2C_A_SDA},
-	{"typec",   IT83XX_I2C_CH_B, 400, GPIO_I2C_B_SCL, GPIO_I2C_B_SDA},
-	{"pmic",    IT83XX_I2C_CH_C, 100, GPIO_I2C_C_SCL, GPIO_I2C_C_SDA},
-	{"ext_io",  IT83XX_I2C_CH_E, 400, GPIO_I2C_E_SCL, GPIO_I2C_E_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* Charger Chips */
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-/* Wake-up pins for hibernate */
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_AC_PRESENT,
-	GPIO_LID_OPEN,
-	GPIO_POWER_BUTTON_L,
-};
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-/* Called by APL power state machine when transitioning from G3 to S5 */
-void chipset_pre_init_callback(void)
-{
-	int data;
-
-	if (pca9555_read(I2C_PORT_PCA555_PMIC_BATT_GPIO,
-		I2C_ADDR_PCA555_PMIC_BATT_GPIO_FLAGS,
-		PCA9555_CMD_OUTPUT_PORT_0, &data))
-		return;
-
-	/*
-	 * No need to re-init PMIC since settings are sticky across sysjump.
-	 * However, be sure to check that PMIC is already enabled. If it is
-	 * then there's no need to re-sequence the PMIC.
-	 */
-	if (system_jumped_to_this_image() && (data & PCA9555_IO_0))
-		return;
-
-	/* Enable SOC_3P3_EN_L: Set the Output port O0.1 to low level */
-	data &= ~PCA9555_IO_1;
-	pca9555_write(I2C_PORT_PCA555_PMIC_BATT_GPIO,
-		I2C_ADDR_PCA555_PMIC_BATT_GPIO_FLAGS,
-		PCA9555_CMD_OUTPUT_PORT_0, data);
-
-	/* TODO: Find out from the spec */
-	msleep(10);
-
-	/* Enable PMIC_EN: Set the Output port O0.0 to high level */
-	pca9555_write(I2C_PORT_PCA555_PMIC_BATT_GPIO,
-		I2C_ADDR_PCA555_PMIC_BATT_GPIO_FLAGS,
-		PCA9555_CMD_OUTPUT_PORT_0,
-		data | PCA9555_IO_0);
-}
-
-/* Initialize board. */
-static void board_init(void)
-{
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_FIRST);
-
-/* Called on AP S5 -> S3 transition */
-static void board_chipset_startup(void)
-{
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S5 transition */
-static void board_chipset_shutdown(void)
-{
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
-
-void chipset_do_shutdown(void)
-{
-	int data;
-
-	if (pca9555_read(I2C_PORT_PCA555_PMIC_BATT_GPIO,
-		I2C_ADDR_PCA555_PMIC_BATT_GPIO_FLAGS,
-		PCA9555_CMD_OUTPUT_PORT_0, &data))
-		return;
-
-	/* Disable SOC_3P3_EN_L: Set the Output port O0.1 to high level */
-	data |= PCA9555_IO_1;
-	pca9555_write(I2C_PORT_PCA555_PMIC_BATT_GPIO,
-		I2C_ADDR_PCA555_PMIC_BATT_GPIO_FLAGS,
-		PCA9555_CMD_OUTPUT_PORT_0, data);
-
-	/* TODO: Find out from the spec */
-	msleep(10);
-
-	/* Disable PMIC_EN: Set the Output port O0.0 to low level */
-	pca9555_write(I2C_PORT_PCA555_PMIC_BATT_GPIO,
-		I2C_ADDR_PCA555_PMIC_BATT_GPIO_FLAGS,
-		PCA9555_CMD_OUTPUT_PORT_0,
-		data & ~PCA9555_IO_0);
-}
-
-void board_hibernate_late(void)
-{
-}
-
-void board_hibernate(void)
-{
-	/*
-	 * To support hibernate called from console commands, ectool commands
-	 * and key sequence, shutdown the AP before hibernating.
-	 */
-	chipset_do_shutdown();
-
-	/* Added delay to allow AP to settle down */
-	msleep(100);
-}
-
-int board_get_version(void)
-{
-	int data;
-
-	if (pca9555_read(I2C_PORT_PCA555_BOARD_ID_GPIO,
-			 I2C_ADDR_PCA555_BOARD_ID_GPIO_FLAGS,
-			 PCA9555_CMD_INPUT_PORT_1, &data))
-		return -1;
-
-	return data & 0x0f;
-}
-
-static void pmic_init(void)
-{
-	/* No need to re-init PMIC since settings are sticky across sysjump. */
-	if (system_jumped_late())
-		return;
-
-	/*
-	 * PMIC INIT
-	 * Configure Port O0.0 as Output port - PMIC_EN
-	 * Configure Port O0.1 as Output port - SOC_3P3_EN_L
-	 */
-	pca9555_write(I2C_PORT_PCA555_PMIC_BATT_GPIO,
-		      I2C_ADDR_PCA555_PMIC_BATT_GPIO_FLAGS,
-		      PCA9555_CMD_CONFIGURATION_PORT_0, 0xfc);
-
-	/*
-	 * Set the Output port O0.0 to low level - PMIC_EN
-	 * Set the Output port O0.1 to high level - SOC_3P3_EN_L
-	 *
-	 * POR of PCA9555 port is input with high impedance hence explicitly
-	 * configure the SOC_3P3_EN_L to high level.
-	 */
-	pca9555_write(I2C_PORT_PCA555_PMIC_BATT_GPIO,
-		      I2C_ADDR_PCA555_PMIC_BATT_GPIO_FLAGS,
-		      PCA9555_CMD_OUTPUT_PORT_0, 0xfe);
-}
-DECLARE_HOOK(HOOK_INIT, pmic_init, HOOK_PRIO_INIT_I2C + 1);
-
-/* Keyboard scan setting */
-struct keyboard_scan_config keyscan_config = {
-	.output_settle_us = 35,
-	.debounce_down_us = 5 * MSEC,
-	.debounce_up_us = 40 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
diff --git a/board/glkrvp_ite/board.h b/board/glkrvp_ite/board.h
deleted file mode 100644
index b131ac42c4..0000000000
--- a/board/glkrvp_ite/board.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel GLK-RVP-ITE board-specific configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/*
- * Allow dangerous commands.
- * TODO: Remove this config before production.
- */
-#define CONFIG_SYSTEM_UNLOCKED
-
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
-#undef CONFIG_HOSTCMD_DEBUG_MODE
-
-/*
- * By default, enable all console messages excepted HC, ACPI and event:
- * The sensor stack is generating a lot of activity.
- */
-#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
-
-/* EC console commands  */
-
-/* Battery */
-#define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_PRESENT_CUSTOM
-#define CONFIG_BATTERY_SMART
-
-/* Charger */
-#define CONFIG_CHARGE_MANAGER
-#define CONFIG_CHARGER
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT 512
-#define CONFIG_CHARGER_ISL9238
-#define CONFIG_CHARGER_PROFILE_OVERRIDE
-#define CONFIG_CHARGER_PROFILE_OVERRIDE_COMMON
-#undef  CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES
-#define CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES 3
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
-#undef  CONFIG_EXTPOWER_DEBOUNCE_MS
-#define CONFIG_EXTPOWER_DEBOUNCE_MS 200
-#define CONFIG_EXTPOWER_GPIO
-
-/* DC Jack charge ports */
-#undef  CONFIG_DEDICATED_CHARGE_PORT_COUNT
-#define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1
-#define DEDICATED_CHARGE_PORT 2
-
-/* Keyboard */
-#define CONFIG_KEYBOARD_BOARD_CONFIG
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-
-/* UART */
-#define CONFIG_LOW_POWER_IDLE
-
-/* USB-A config */
-
-/* USB PD config */
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT TYPEC_RP_3A0
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV1
-
-/* USB MUX */
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USB_MUX_PS8743
-
-/* SoC / PCH */
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_CHIPSET_GEMINILAKE
-#define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_X86
-#define CONFIG_POWER_COMMON
-#define CONFIG_POWER_S0IX
-#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-
-/* EC */
-#define CONFIG_BOARD_VERSION_CUSTOM
-#define CONFIG_VOLUME_BUTTONS
-#define CONFIG_LID_SWITCH
-#define CONFIG_WP_ALWAYS
-#define CONFIG_FLASH_READOUT_PROTECTION
-
-/* Verified boot */
-#define CONFIG_SHA256_UNROLLED
-#define CONFIG_VBOOT_HASH
-/*
- * Enable 1 slot of secure temporary storage to support
- * suspend/resume with read/write memory training.
- */
-#define CONFIG_VSTORE
-#define CONFIG_VSTORE_SLOT_COUNT 1
-
-/* Optional feature - used by ITE */
-#define CONFIG_IT83XX_ENABLE_MOUSE_DEVICE
-#define CONFIG_IT83XX_FLASH_CLOCK_48MHZ
-
-/* I2C ports */
-#define CONFIG_I2C
-#define CONFIG_I2C_MASTER
-#define CONFIG_IT83XX_SMCLK2_ON_GPC7
-
-#define I2C_PORT_CHARGER	IT83XX_I2C_CH_A
-#define I2C_PORT_BATTERY	IT83XX_I2C_CH_A
-#define I2C_PORT_USB_MUX	IT83XX_I2C_CH_B
-
-#define I2C_PORT_PCA555_PMIC_BATT_GPIO	IT83XX_I2C_CH_C
-#define I2C_ADDR_PCA555_PMIC_BATT_GPIO_FLAGS	0x21
-
-/* EC exclude modules */
-#undef CONFIG_ADC
-#undef CONFIG_WATCHDOG
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum adc_channel {
-	ADC_VBUS,
-	ADC_CH_COUNT,
-};
-
-int board_get_version(void);
-
-/* TODO: Verify the numbers below. */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
-
-/* Define typical operating power and max power */
-#define PD_OPERATING_POWER_MW  15000
-#define PD_MAX_POWER_MW        45000
-#define PD_MAX_CURRENT_MA      3000
-#define PD_MAX_VOLTAGE_MV      20000
-#define DC_JACK_MAX_VOLTAGE_MV 19000
-
-/* Reset PD MCU */
-void board_reset_pd_mcu(void);
-void tcpc_alert_event(enum gpio_signal signal);
-void board_charging_enable(int port, int enable);
-void board_vbus_enable(int port, int enable);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/glkrvp_ite/build.mk b/board/glkrvp_ite/build.mk
deleted file mode 100644
index b2e416c00b..0000000000
--- a/board/glkrvp_ite/build.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-# -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-#it8320
-CHIP:=it83xx
-CHIP_FAMILY:=it8320
-CHIP_VARIANT:=it8320bx
-
-board-y=board.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
-board-$(CONFIG_USB_POWER_DELIVERY)+=chg_usb_pd.o usb_pd_policy.o
diff --git a/board/glkrvp_ite/chg_usb_pd.c b/board/glkrvp_ite/chg_usb_pd.c
deleted file mode 100644
index 7bc60fd5c8..0000000000
--- a/board/glkrvp_ite/chg_usb_pd.c
+++ /dev/null
@@ -1,261 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "console.h"
-#include "hooks.h"
-#include "task.h"
-#include "tcpci.h"
-#include "system.h"
-#include "usb_mux.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-#define PTN5110_EXT_GPIO_CONFIG		0x92
-#define PTN5110_EXT_GPIO_CONTROL	0x93
-
-#define PTN5110_EXT_GPIO_FRS_EN			BIT(6)
-#define PTN5110_EXT_GPIO_EN_SRC			BIT(5)
-#define PTN5110_EXT_GPIO_EN_SNK1		BIT(4)
-#define PTN5110_EXT_GPIO_IILIM_5V_VBUS_L	BIT(3)
-
-enum glkrvp_charge_ports {
-	TYPE_C_PORT_0,
-	TYPE_C_PORT_1,
-	DC_JACK_PORT_0 = DEDICATED_CHARGE_PORT,
-};
-
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = IT83XX_I2C_CH_B,
-			.addr_flags = 0x50,
-		},
-		.drv = &tcpci_tcpm_drv,
-	},
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = IT83XX_I2C_CH_B,
-			.addr_flags = 0x52,
-		},
-		.drv = &tcpci_tcpm_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == CONFIG_USB_PD_PORT_MAX_COUNT);
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = 0x10,
-		.driver = &ps8743_usb_mux_driver,
-	},
-	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = 0x11,
-		.driver = &ps8743_usb_mux_driver,
-	},
-};
-
-static int board_charger_port_is_sourcing_vbus(int port)
-{
-	int reg;
-
-	/* DC Jack can't source VBUS */
-	if (port == DC_JACK_PORT_0)
-		return 0;
-
-	if (tcpc_read(port, PTN5110_EXT_GPIO_CONTROL, &reg))
-		return 0;
-
-	return !!(reg & PTN5110_EXT_GPIO_EN_SRC);
-}
-
-static int ptn5110_ext_gpio_enable(int port, int enable, int gpio)
-{
-	int reg;
-	int rv;
-
-	rv = tcpc_read(port, PTN5110_EXT_GPIO_CONTROL, &reg);
-	if (rv)
-		return rv;
-
-	if (enable)
-		reg |= gpio;
-	else
-		reg &= ~gpio;
-
-	return tcpc_write(port, PTN5110_EXT_GPIO_CONTROL, reg);
-}
-
-void board_charging_enable(int port, int enable)
-{
-	ptn5110_ext_gpio_enable(port, enable, PTN5110_EXT_GPIO_EN_SNK1);
-}
-
-void board_vbus_enable(int port, int enable)
-{
-	ptn5110_ext_gpio_enable(port, enable, PTN5110_EXT_GPIO_EN_SRC);
-}
-
-void tcpc_alert_event(enum gpio_signal signal)
-{
-#ifdef HAS_TASK_PDCMD
-	/* Exchange status with TCPCs */
-	host_command_pd_send_status(PD_CHARGE_NO_CHANGE);
-#endif
-}
-
-void board_tcpc_init(void)
-{
-	/* Only reset TCPC if not sysjump */
-	if (!system_jumped_late())
-		board_reset_pd_mcu();
-
-	/* Enable TCPC0/1 interrupt */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
-
-int board_tcpc_post_init(int port)
-{
-	int reg;
-	int rv;
-
-	rv = tcpc_read(port, PTN5110_EXT_GPIO_CONFIG, &reg);
-	if (rv)
-		return rv;
-
-	/* Configure PTN5110 External GPIOs as output */
-	reg |=  PTN5110_EXT_GPIO_EN_SRC | PTN5110_EXT_GPIO_EN_SNK1 |
-		PTN5110_EXT_GPIO_IILIM_5V_VBUS_L;
-	rv = tcpc_write(port, PTN5110_EXT_GPIO_CONFIG, reg);
-	if (rv)
-		return rv;
-
-	return ptn5110_ext_gpio_enable(port, 1,
-					PTN5110_EXT_GPIO_IILIM_5V_VBUS_L);
-}
-
-/* Reset PD MCU */
-void board_reset_pd_mcu(void)
-{
-	/* TODO: Add reset logic */
-}
-
-static inline int board_dc_jack_present(void)
-{
-	return !gpio_get_level(GPIO_DC_JACK_PRESENT_L);
-}
-
-static void board_dc_jack_handle(void)
-{
-	struct charge_port_info charge_dc_jack;
-
-	/* System is booted from DC Jack */
-	if (board_dc_jack_present()) {
-		charge_dc_jack.current = (PD_MAX_POWER_MW * 1000) /
-					DC_JACK_MAX_VOLTAGE_MV;
-		charge_dc_jack.voltage = DC_JACK_MAX_VOLTAGE_MV;
-	} else {
-		charge_dc_jack.current = 0;
-		charge_dc_jack.voltage = USB_CHARGER_VOLTAGE_MV;
-	}
-
-	charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED,
-				DC_JACK_PORT_0, &charge_dc_jack);
-}
-DECLARE_HOOK(HOOK_AC_CHANGE, board_dc_jack_handle, HOOK_PRIO_FIRST);
-
-static void board_charge_init(void)
-{
-	int port, supplier;
-
-	/* Initialize all charge suppliers to seed the charge manager */
-	for (port = 0; port < CHARGE_PORT_COUNT; port++) {
-		for (supplier = 0; supplier < CHARGE_SUPPLIER_COUNT; supplier++)
-			charge_manager_update_charge(supplier, port, NULL);
-	}
-
-	board_dc_jack_handle();
-}
-DECLARE_HOOK(HOOK_INIT, board_charge_init, HOOK_PRIO_DEFAULT);
-
-int board_set_active_charge_port(int port)
-{
-	/* charge port is a realy physical port */
-	int is_real_port = (port >= 0 &&
-			port < CHARGE_PORT_COUNT);
-	/* check if we are source vbus on that port */
-	int source = board_charger_port_is_sourcing_vbus(port);
-
-	if (is_real_port && source) {
-		CPRINTS("Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	/*
-	 * Do not enable Type-C port if the DC Jack is present.
-	 * When the Type-C is active port, hardware circuit will
-	 * block DC jack from enabling +VADP_OUT.
-	 */
-	if (port != DC_JACK_PORT_0 && board_dc_jack_present()) {
-		CPRINTS("DC Jack present, Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	/* Make sure non-charging port is disabled */
-	switch (port) {
-	case TYPE_C_PORT_0:
-		board_charging_enable(TYPE_C_PORT_1, 0);
-		board_charging_enable(TYPE_C_PORT_0, 1);
-		break;
-	case TYPE_C_PORT_1:
-		board_charging_enable(TYPE_C_PORT_0, 0);
-		board_charging_enable(TYPE_C_PORT_1, 1);
-		break;
-	case DC_JACK_PORT_0:
-	case CHARGE_PORT_NONE:
-	default:
-		/* Disable both Type-C ports */
-		board_charging_enable(TYPE_C_PORT_0, 0);
-		board_charging_enable(TYPE_C_PORT_1, 0);
-		break;
-	}
-
-	return EC_SUCCESS;
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_0;
-
-	if (!gpio_get_level(GPIO_USB_C1_PD_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_set_input_current_limit(MAX(charge_ma,
-				CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
-
-int adc_read_channel(enum adc_channel ch)
-{
-	return 0;
-}
diff --git a/board/glkrvp_ite/ec.tasklist b/board/glkrvp_ite/ec.tasklist
deleted file mode 100644
index 086a352bcb..0000000000
--- a/board/glkrvp_ite/ec.tasklist
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel GLK-RVP-ITE board-specific configuration */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(PDCMD, pd_command_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/glkrvp_ite/gpio.inc b/board/glkrvp_ite/gpio.inc
deleted file mode 100644
index a4f21a64f4..0000000000
--- a/board/glkrvp_ite/gpio.inc
+++ /dev/null
@@ -1,118 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel GLK-RVP-ITE board-specific configuration */
-
-/*
- * Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first.
- */
-
-/* Power sequencing interrupts */
-GPIO_INT(SUSPWRDNACK,	PIN(E, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PCH_SLP_S0_L,	PIN(F, 0), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PCH_SLP_S3_L,	PIN(F, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PCH_SLP_S4_L,	PIN(F, 3), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(RSMRST_L_PGOOD,PIN(G, 6), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(ALL_SYS_PGOOD,	PIN(I, 7), GPIO_INT_BOTH, power_signal_interrupt)
-
-/* Button interrupts */
-GPIO_INT(VOLUME_UP_L,	PIN(D, 5), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(VOLUME_DOWN_L,	PIN(D, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(LID_OPEN,	PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP, lid_interrupt)
-GPIO_INT(POWER_BUTTON_L,PIN(E, 4), GPIO_INT_BOTH, power_button_interrupt)
-
-GPIO_INT(AC_PRESENT,	PIN(A, 6), GPIO_INT_BOTH, extpower_interrupt)
-
-GPIO_INT(UART1_RX,	PIN(B, 0), GPIO_INT_FALLING, uart_deepsleep_interrupt) /* UART1 RX input */
-#ifdef CONFIG_HOSTCMD_ESPI
-/* enable 1.8v input of EC's espi_reset pin, and then this pin takes effect. */
-GPIO_INT(ESPI_RESET_L, 	 PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt) /* eSPI_reset# */
-#endif
-
-/* Type-C interrupts */
-UNIMPLEMENTED(USB_C0_PD_INT_ODL)
-UNIMPLEMENTED(USB_C1_PD_INT_ODL)
-
-UNIMPLEMENTED(WP_L)
-UNIMPLEMENTED(PP3300_PG)
-UNIMPLEMENTED(PP5000_PG)
-
-/* Power sequencing GPIOs */
-UNIMPLEMENTED(SYS_RESET_L)
-GPIO(PCH_RSMRST_L,	PIN(C, 6), GPIO_OUT_LOW)
-GPIO(PCH_PWRBTN_L,	PIN(D, 0), GPIO_ODR_HIGH)
-GPIO(PCH_SYS_PWROK,	PIN(K, 4), GPIO_OUT_LOW)
-GPIO(SMC_SHUTDOWN,	PIN(K, 5), GPIO_OUT_LOW | GPIO_PULL_DOWN)
-/*
- * PCH_PROCHOT_ODL is primarily for monitoring the PROCHOT# signal which is
- * normally driven by the PMIC. The EC can also drive this signal in the event
- * that the ambient or charger temperature sensors exceeds their thresholds.
- */
-GPIO(CPU_PROCHOT,	PIN(E, 5), GPIO_INPUT)		/* PCH_PROCHOT_ODL */
-
-/* Host communication GPIOs */
-GPIO(PCH_WAKE_L,	PIN(L, 0), GPIO_ODR_HIGH)
-GPIO(PCH_PLTRST_L,	PIN(E, 3), GPIO_INPUT | GPIO_PULL_UP)
-
-GPIO(DC_JACK_PRESENT_L,	PIN(C, 0), GPIO_INPUT)		/* DC Jack presence coming from +V3P3_A_KBC */
-GPIO(USBC_LDO_ENABLE,	PIN(K, 0), GPIO_OUT_HIGH)	/* USB TCPC to enable LDO in dead battery */
-UNIMPLEMENTED(ENABLE_BACKLIGHT)
-GPIO(ENTERING_RW,	PIN(C, 5), GPIO_OUTPUT)		/* EC_ENTERING_RW */
-
-/*
- * I2C pins should be configured as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-GPIO(I2C_A_SCL,	PIN(B, 3), GPIO_INPUT)
-GPIO(I2C_A_SDA,	PIN(B, 4), GPIO_INPUT)
-GPIO(I2C_B_SCL,	PIN(C, 1), GPIO_INPUT)
-GPIO(I2C_B_SDA,	PIN(C, 2), GPIO_INPUT)
-#ifdef CONFIG_IT83XX_SMCLK2_ON_GPC7
-GPIO(I2C_C_SCL,      PIN(C, 7), GPIO_INPUT)
-#else
-GPIO(I2C_C_SCL,	PIN(F, 6), GPIO_INPUT)
-#endif
-GPIO(I2C_C_SDA,	PIN(F, 7), GPIO_INPUT)
-GPIO(I2C_E_SCL,	PIN(E, 0), GPIO_INPUT)
-GPIO(I2C_E_SDA,	PIN(E, 7), GPIO_INPUT)
-
-/* LPC / eSPI signals */
-#if 0
-GPIO(LPC_ESPI_RST,	PIN(D, 2), GPIO_INPUT)
-GPIO(LAD_EIO_0,		PIN(M, 0), GPIO_INPUT)
-GPIO(LAD_EIO_1,		PIN(M, 1), GPIO_INPUT)
-GPIO(LAD_EIO_2,		PIN(M, 2), GPIO_INPUT)
-GPIO(LAD_EIO_3,		PIN(M, 3), GPIO_INPUT)
-GPIO(LPC_ESPI_CLK,	PIN(M, 4), GPIO_INPUT)
-GPIO(LFRAME_ESPI_CS,	PIN(M, 5), GPIO_INPUT)
-GPIO(SERIRQ_ALERT,	PIN(M, 6), GPIO_INPUT)
-#endif
-
-/* Unused pins 3.3V & Interruptable */
-
-/* Unused pins: VSPI 3.3V or 1.8V & Interruptable */
-
-/* Unused pins 3.3V & Non-Interruptable */
-
-/* eSPI: VHIF Unused pins 1.8V & Interruptable */
-
-/* eSPI: VHIF Unused pins 1.8V & Non-Interruptable */
-
-/* Alternate pins for UART */
-ALTERNATE(PIN_MASK(B, 0x03), 1, MODULE_UART, GPIO_PULL_UP) /* UART1 */
-
-/* Alternate pins for I2C */
-ALTERNATE(PIN_MASK(B, 0x18), 1, MODULE_I2C, 0)	/* I2C A SCL/SDA B3/B4 */
-ALTERNATE(PIN_MASK(C, 0x06), 1, MODULE_I2C, 0)	/* I2C B SCL/SDA C1/C2 */
-#ifdef CONFIG_IT83XX_SMCLK2_ON_GPC7
-ALTERNATE(PIN_MASK(C, 0x80), 1, MODULE_I2C, 0)	/* I2C C SCL C7 */
-#else
-ALTERNATE(PIN_MASK(F, 0x40), 1, MODULE_I2C, 0)	/* I2C C SCL F6 */
-#endif
-ALTERNATE(PIN_MASK(F, 0x80), 1, MODULE_I2C, 0)	/* I2C C SDA F7 */
-ALTERNATE(PIN_MASK(E, 0x81), 1, MODULE_I2C, 0)	/* I2C E SCL/SDA E0/E7 */
diff --git a/board/glkrvp_ite/usb_pd_policy.c b/board/glkrvp_ite/usb_pd_policy.c
deleted file mode 100644
index bfb395baf4..0000000000
--- a/board/glkrvp_ite/usb_pd_policy.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "charge_manager.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "gpio.h"
-#include "stddef.h"
-#include "system.h"
-#include "usb_mux.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_set_power_supply_ready(int port)
-{
-	/* Disable charging */
-	board_charging_enable(port, 0);
-
-	/* Provide VBUS */
-	board_vbus_enable(port, 1);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS; /* we are ready */
-}
-
-void pd_power_supply_reset(int port)
-{
-	/* Disable VBUS */
-	board_vbus_enable(port, 0);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_check_vconn_swap(int port)
-{
-	/* in G3, do not allow vconn swap since pp5000_A rail is off */
-	/* TODO: return gpio_get_level(GPIO_PMIC_EN); */
-	return 1;
-}
-
-void pd_execute_data_swap(int port,
-			  enum pd_data_role data_role)
-{
-	/* Do nothing */
-}
diff --git a/board/gooey/battery.c b/board/gooey/battery.c
new file mode 100644
index 0000000000..e8cec5af5f
--- /dev/null
+++ b/board/gooey/battery.c
@@ -0,0 +1,121 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "charge_state.h"
+#include "common.h"
+
+/*
+ * Battery info for all gooey battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	/* SMP L18D3PG1 Battery Information */
+	[BATTERY_SMP] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP",
+			.ship_mode = {
+				.reg_addr = 0x34,
+				.reg_data = { 0x0000, 0x1000 },
+			},
+			.fet = {
+				.reg_addr = 0x00,
+				.reg_mask = 0x0018,
+				.disconnect_val = 0x0000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13050, /* mV */
+			.voltage_normal		= 11250, /* mV */
+			.voltage_min		= 9000,  /* mV */
+			.precharge_current	= 256,	 /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 60,
+		},
+	},
+
+	/* LGC L17L3PB0 Battery Information */
+	[BATTERY_LGC] = {
+		.fuel_gauge = {
+			.manuf_name = "LGC",
+			.ship_mode = {
+				.reg_addr = 0x34,
+				.reg_data = { 0x0000, 0x1000 },
+			},
+			.fet = {
+				.reg_addr = 0x00,
+				.reg_mask = 0x0018,
+				.disconnect_val = 0x0000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13050, /* mV */
+			.voltage_normal		= 11400, /* mV */
+			.voltage_min		= 9000,  /* mV */
+			.precharge_current	= 256,	 /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 73,
+		},
+	},
+
+	/* Sunwoda L17M3PB0 Battery Information */
+	[BATTERY_SUNWODA] = {
+		.fuel_gauge = {
+			.manuf_name = "SUNWODA",
+			.ship_mode = {
+				.reg_addr = 0x34,
+				.reg_data = { 0x0000, 0x1000 },
+			},
+			.fet = {
+				.reg_addr = 0x00,
+				.reg_mask = 0x0018,
+				.disconnect_val = 0x0000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13050, /* mV */
+			.voltage_normal		= 11250, /* mV */
+			.voltage_min		= 9000,  /* mV */
+			.precharge_current	= 186,	 /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 60,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SMP;
diff --git a/board/gooey/board.c b/board/gooey/board.c
new file mode 100644
index 0000000000..0160832c04
--- /dev/null
+++ b/board/gooey/board.c
@@ -0,0 +1,490 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Gooey board-specific configuration */
+
+#include "adc_chip.h"
+#include "button.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "driver/accel_lis2dw12.h"
+#include "driver/accelgyro_lsm6dsm.h"
+#include "driver/bc12/pi3usb9201.h"
+#include "driver/charger/isl923x.h"
+#include "driver/tcpm/raa489000.h"
+#include "driver/tcpm/tcpci.h"
+#include "driver/temp_sensor/thermistor.h"
+#include "driver/usb_mux/it5205.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "intc.h"
+#include "keyboard_8042.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "switch.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "tcpm/tcpci.h"
+#include "temp_sensor.h"
+#include "uart.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+
+#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define INT_RECHECK_US 5000
+
+/* C0 interrupt line shared by BC 1.2 and charger */
+static void check_c0_line(void);
+DECLARE_DEFERRED(check_c0_line);
+
+static void hdmi_hpd_interrupt(enum gpio_signal s)
+{
+	gpio_set_level(GPIO_USB_C1_DP_HPD, !gpio_get_level(s));
+}
+
+static void notify_c0_chips(void)
+{
+	/*
+	 * The interrupt line is shared between the TCPC and BC 1.2 detection
+	 * chip.  Therefore we'll need to check both ICs.
+	 */
+	schedule_deferred_pd_interrupt(0);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+
+static void check_c0_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		notify_c0_chips();
+		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+	}
+}
+
+static void usb_c0_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c0_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c0_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+}
+
+static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
+{
+	cprints(CC_USBPD, "C0: CC OVP, SBU OVP, or thermal event");
+	pd_handle_cc_overvoltage(0);
+}
+
+/**
+ * Deferred function to handle pen detect change
+ */
+static void pendetect_deferred(void)
+{
+	static int debounced_pen_detect;
+	int pen_detect = !gpio_get_level(GPIO_PEN_DET_ODL);
+
+	if (pen_detect == debounced_pen_detect)
+		return;
+
+	debounced_pen_detect = pen_detect;
+
+	gpio_set_level(GPIO_EN_PP5000_PEN, debounced_pen_detect);
+	gpio_set_level(GPIO_PEN_DET_PCH, !debounced_pen_detect);
+}
+DECLARE_DEFERRED(pendetect_deferred);
+
+void pen_detect_interrupt(enum gpio_signal s)
+{
+	/* Trigger deferred notification of pen detect change */
+	hook_call_deferred(&pendetect_deferred_data, 500 * MSEC);
+}
+
+void board_hibernate(void)
+{
+	/*
+	 * Charger IC need to be put into their "low power mode" before
+	 * entering the Z-state.
+	 */
+	raa489000_hibernate(0, false);
+}
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	[ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH0 },
+	[ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH2 },
+	[ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH3 },
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* BC 1.2 chips */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	{
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+		.flags = PI3USB9201_ALWAYS_POWERED,
+	},
+};
+
+/* Charger chips */
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+};
+
+/* TCPCs */
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0,
+			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
+		},
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+		.drv = &raa489000_tcpm_drv,
+	},
+};
+
+/* USB Muxes */
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+			},
+	},
+};
+
+/* USB-A charging control */
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_USB_A0_VBUS,
+};
+
+void board_init(void)
+{
+	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C0_CCSBU_OVP_ODL);
+	/* Enable gpio interrupt for base accelgyro sensor */
+	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
+	gpio_enable_interrupt(GPIO_HDMI_HPD_SUB_ODL);
+	/* Enable gpio interrupt for pen detect */
+	gpio_enable_interrupt(GPIO_PEN_DET_ODL);
+
+	/* Make sure pen detection is triggered or not at sysjump */
+	if (!gpio_get_level(GPIO_PEN_DET_ODL))
+		gpio_set_level(GPIO_EN_PP5000_PEN, 1);
+	if (gpio_get_level(GPIO_PEN_DET_ODL))
+		gpio_set_level(GPIO_PEN_DET_PCH, 1);
+
+	/* Set LEDs luminance */
+	pwm_set_duty(PWM_CH_LED_RED, 70);
+	pwm_set_duty(PWM_CH_LED_GREEN, 70);
+	pwm_set_duty(PWM_CH_LED_WHITE, 70);
+
+	/*
+	 * If interrupt lines are already low, schedule them to be processed
+	 * after inits are completed.
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL))
+		hook_call_deferred(&check_c0_line_data, 0);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * Nothing to do.  TCPC C0 is internal, TCPC C1 reset pin is not
+	 * connected to the EC.
+	 */
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+	int regval;
+
+	/*
+	 * The interrupt line is shared between the TCPC and BC1.2 detector IC.
+	 * Therefore, go out and actually read the alert registers to report the
+	 * alert status.
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
+			/* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */
+			if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0))
+				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
+
+			if (regval)
+				status |= PD_STATUS_TCPC_ALERT_0;
+		}
+	}
+
+	return status;
+}
+
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	if (port < 0 || port > board_get_usb_pd_port_count())
+		return;
+
+	raa489000_set_output_current(port, rp);
+}
+
+int board_is_sourcing_vbus(int port)
+{
+	int regval;
+
+	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
+	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
+}
+
+int board_set_active_charge_port(int port)
+{
+	if (port != 0 && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	CPRINTUSB("New chg p%d", port);
+
+	/* Disable all ports. */
+	if (port == CHARGE_PORT_NONE) {
+		tcpc_write(0, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
+		raa489000_enable_asgate(0, false);
+		return EC_SUCCESS;
+	}
+
+	/* Check if port is sourcing VBUS. */
+	if (board_is_sourcing_vbus(port)) {
+		CPRINTUSB("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	/* Enable requested charge port. */
+	if (raa489000_enable_asgate(port, true) ||
+	    tcpc_write(0, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
+		CPRINTUSB("p%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_KBLIGHT] = {
+		.channel = 0,
+		.flags = PWM_CONFIG_DSLEEP,
+		.freq_hz = 10000,
+	},
+
+	[PWM_CH_LED_RED] = {
+		.channel = 1,
+		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
+		.freq_hz = 2400,
+	},
+
+	[PWM_CH_LED_GREEN] = {
+		.channel = 2,
+		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
+		.freq_hz = 2400,
+	},
+
+	[PWM_CH_LED_WHITE] = {
+		.channel = 3,
+		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
+		.freq_hz = 2400,
+	}
+
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+/* Sensor Mutexes */
+static struct mutex g_lid_mutex;
+static struct mutex g_base_mutex;
+
+/* Matrices to rotate accelerometers into the standard reference. */
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
+
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, FLOAT_TO_FP(1), 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
+
+/* Sensor Data */
+static struct stprivate_data g_lis2dwl_data;
+static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
+
+/* Drivers */
+struct motion_sensor_t motion_sensors[] = {
+	[LID_ACCEL] = {
+		.name = "Lid Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LIS2DWL,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &lis2dw12_drv,
+		.mutex = &g_lid_mutex,
+		.drv_data = &g_lis2dwl_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LIS2DWL_ADDR1_FLAGS,
+		.rot_standard_ref = &lid_standard_ref,
+		.default_range = 2, /* g */
+		.min_frequency = LIS2DW12_ODR_MIN_VAL,
+		.max_frequency = LIS2DW12_ODR_MAX_VAL,
+		.config = {
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 12500 | ROUND_UP_FLAG,
+			},
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+		},
+	},
+	[BASE_ACCEL] = {
+		.name = "Base Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LSM6DSM,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &lsm6dsm_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
+				MOTIONSENSE_TYPE_ACCEL),
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
+		.rot_standard_ref = &base_standard_ref,
+		.default_range = 4,  /* g */
+		.min_frequency = LSM6DSM_ODR_MIN_VAL,
+		.max_frequency = LSM6DSM_ODR_MAX_VAL,
+		.config = {
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 13000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+		},
+	},
+	[BASE_GYRO] = {
+		.name = "Base Gyro",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LSM6DSM,
+		.type = MOTIONSENSE_TYPE_GYRO,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &lsm6dsm_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
+				MOTIONSENSE_TYPE_GYRO),
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
+		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = LSM6DSM_ODR_MIN_VAL,
+		.max_frequency = LSM6DSM_ODR_MAX_VAL,
+	},
+};
+
+const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+/* Thermistors */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/* This callback disables keyboard when convertibles are fully open */
+__override void lid_angle_peripheral_enable(int enable)
+{
+	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
+
+	/*
+	 * If the lid is in tablet position via other sensors,
+	 * ignore the lid angle, which might be faulty then
+	 * disable keyboard.
+	 */
+	if (tablet_get_mode())
+		enable = 0;
+
+	if (enable) {
+		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
+	} else {
+		/*
+		 * Ensure that the chipset is off before disabling the keyboard.
+		 * When the chipset is on, the EC keeps the keyboard enabled and
+		 * the AP decides whether to ignore input devices or not.
+		 */
+		if (!chipset_in_s0)
+			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
+	}
+}
+
+static const struct ec_response_keybd_config gooey_keybd = {
+	/* Default Chromeos keyboard config */
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_FORWARD,		/* T2 */
+		TK_REFRESH,		/* T3 */
+		TK_FULLSCREEN,		/* T4 */
+		TK_OVERVIEW,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	/* No function keys, no numeric keypad, has screenlock key */
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &gooey_keybd;
+}
diff --git a/board/gooey/board.h b/board/gooey/board.h
new file mode 100644
index 0000000000..82aca107af
--- /dev/null
+++ b/board/gooey/board.h
@@ -0,0 +1,145 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Gooey board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* Select Baseboard features */
+#define VARIANT_KEEBY_EC_IT8320
+#include "baseboard.h"
+
+/* Battery */
+#define CONFIG_BATTERY_FUEL_GAUGE
+#define CONFIG_BATTERY_V2
+#define CONFIG_BATTERY_COUNT 1
+#define CONFIG_HOSTCMD_BATTERY_V2
+
+/* BC 1.2 */
+#define CONFIG_BC12_DETECT_PI3USB9201
+
+/* Charger */
+#define CONFIG_CHARGE_RAMP_HW
+#define CONFIG_CHARGER_RAA489000
+#define PD_MAX_VOLTAGE_MV 20000
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_OCPC_DEF_RBATT_MOHMS               \
+	22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \
+	    */
+#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
+#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
+/*
+ * b/147463641: The charger IC seems to overdraw ~4%, therefore we
+ * reduce our target accordingly.
+ */
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 4
+
+/* DAC for PSYS */
+#define CONFIG_DAC
+
+/* LED */
+#define CONFIG_LED_ONOFF_STATES
+
+/* PWM */
+#define CONFIG_PWM
+
+/* Sensors */
+#define CONFIG_ACCEL_LIS2DWL /* Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
+#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+/* Sensors without hardware FIFO are in forced mode */
+#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
+
+/* Enable sensor fifo, must also define the _SIZE and _THRES */
+#define CONFIG_ACCEL_FIFO
+/* Power of 2 - Too large of a fifo causes too much timestamp jitter */
+#define CONFIG_ACCEL_FIFO_SIZE 256
+#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
+
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_UPDATE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+
+#define CONFIG_TABLET_MODE
+#define CONFIG_TABLET_MODE_SWITCH
+#define CONFIG_GMR_TABLET_MODE
+
+/* TCPC */
+#define CONFIG_USB_PD_PORT_MAX_COUNT 1
+#define CONFIG_USB_PD_TCPM_RAA489000
+
+/* USB defines specific to external TCPCs */
+#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+#define CONFIG_USB_PD_VBUS_DETECT_TCPC
+#define CONFIG_USB_PD_DISCHARGE_TCPC
+#define CONFIG_USB_PD_TCPC_LOW_POWER
+
+/* EC console commands */
+#define CONFIG_CMD_TCPC_DUMP
+#define CONFIG_CMD_ACCELS
+#define CONFIG_CMD_ACCEL_INFO
+
+/* Variant references the TCPCs to determine Vbus sourcing */
+#define CONFIG_USB_PD_5V_EN_CUSTOM
+
+/* Thermistors */
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_THERMISTOR
+#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
+
+/* USB Mux */
+#define CONFIG_USB_MUX_IT5205
+
+/* USB Type A Features */
+#define USB_PORT_COUNT 1
+#define CONFIG_USB_PORT_POWER_DUMB
+
+/* Keyboard features */
+#define CONFIG_KEYBOARD_VIVALDI
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum pwm_channel {
+	PWM_CH_KBLIGHT,
+	PWM_CH_LED_RED,
+	PWM_CH_LED_GREEN,
+	PWM_CH_LED_WHITE,
+	PWM_CH_COUNT,
+};
+
+/* Motion sensors */
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
+
+/* ADC channels */
+enum adc_channel {
+	ADC_VSNS_PP3300_A, /* ADC0 */
+	ADC_TEMP_SENSOR_1, /* ADC2 */
+	ADC_TEMP_SENSOR_2, /* ADC3 */
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT };
+
+/* List of possible batteries */
+enum battery_type {
+	BATTERY_SMP,
+	BATTERY_LGC,
+	BATTERY_SUNWODA,
+	BATTERY_TYPE_COUNT,
+};
+
+void pen_detect_interrupt(enum gpio_signal s);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/gooey/build.mk b/board/gooey/build.mk
new file mode 100644
index 0000000000..f65b5e8f0c
--- /dev/null
+++ b/board/gooey/build.mk
@@ -0,0 +1,15 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=it83xx
+CHIP_FAMILY:=it8320
+CHIP_VARIANT:=it8320dx
+BASEBOARD:=keeby
+
+board-y=board.o led.o usb_pd_policy.o
+board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/gooey/ec.tasklist b/board/gooey/ec.tasklist
new file mode 100644
index 0000000000..8ccdfc81b2
--- /dev/null
+++ b/board/gooey/ec.tasklist
@@ -0,0 +1,22 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, TRENTA_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE)
diff --git a/board/gooey/gpio.inc b/board/gooey/gpio.inc
new file mode 100644
index 0000000000..8eb1f5ef22
--- /dev/null
+++ b/board/gooey/gpio.inc
@@ -0,0 +1,146 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+/* Power State interrupts */
+GPIO_INT(SLP_S4_L,		PIN(I, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,		PIN(H, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(SLP_S0_L,		PIN(E, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,		PIN(G, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID0,	PIN(D, 0), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(RSMRST_PWRGD_L,	PIN(E, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(CPU_C10_GATE_L,	PIN(G, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_DRAM_OD,		PIN(D, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(PG_PP1050_ST_OD,	PIN(L, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID1,	PIN(K, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_VCCIO_EXT_OD,	PIN(D, 7), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(ESPI_RESET_L, 	 PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt)
+
+GPIO_INT(EC_PWR_BTN_ODL,	PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
+#ifdef CONFIG_LOW_POWER_IDLE
+/* Used to wake up the EC from Deep Doze mode when writing to console */
+GPIO_INT(UART1_RX,	 PIN(B, 0), GPIO_INT_BOTH, uart_deepsleep_interrupt)	/* UART_DBG_TX_EC_RX */
+#endif
+
+/* USB-C interrupts */
+GPIO_INT(USB_C0_INT_ODL,	PIN(K, 0), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt) /* BC12 and charger */
+GPIO_INT(USB_C0_CCSBU_OVP_ODL,	PIN(K, 6), GPIO_INT_FALLING | GPIO_PULL_UP, c0_ccsbu_ovp_interrupt) /* Fault protection */
+
+/* Other interrupts */
+GPIO_INT(LID_OPEN,		PIN(F, 3), GPIO_INT_BOTH, lid_interrupt)
+GPIO_INT(LID_360_L,		PIN(A, 7), GPIO_INT_BOTH, gmr_tablet_switch_isr)
+GPIO_INT(VOLDN_BTN_ODL,		PIN(I, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(VOLUP_BTN_ODL,		PIN(I, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(J, 0), GPIO_INT_FALLING | GPIO_SEL_1P8V, lsm6dsm_interrupt)
+GPIO_INT(EC_WP_OD,		PIN(A, 6), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(HDMI_HPD_SUB_ODL,	PIN(E, 7), GPIO_INT_BOTH, hdmi_hpd_interrupt)
+
+/* Power sequence GPIOs */
+GPIO(EC_AP_RTCRST,		PIN(K, 2), GPIO_OUT_LOW)
+GPIO(EC_AP_PWR_BTN_ODL,		PIN(B, 6), GPIO_ODR_HIGH)
+GPIO(EC_AP_DPWROK,		PIN(L, 7), GPIO_OUT_LOW)
+GPIO(EC_AP_RSMRST_L,		PIN(H, 0), GPIO_OUT_LOW)
+GPIO(EC_AP_WAKE_ODL,		PIN(D, 5), GPIO_ODR_HIGH)
+GPIO(SYS_RST_ODL,		PIN(D, 1), GPIO_ODR_HIGH)
+GPIO(EC_AP_SYS_PWROK,		PIN(F, 2), GPIO_OUT_LOW)
+GPIO(PG_PP5000_U_OD,		PIN(E, 3), GPIO_INPUT)
+GPIO(EN_PP3300_A,		PIN(C, 5), GPIO_OUT_LOW)
+GPIO(EC_AP_PCH_PWROK_OD,	PIN(D, 6), GPIO_ODR_LOW)
+GPIO(EN_PP5000_U,		PIN(K, 5), GPIO_OUT_LOW)
+/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
+GPIO(EN_VCCST,			PIN(D, 4), GPIO_INPUT)
+GPIO(EN_VCCIO_EXT,		PIN(B, 2), GPIO_OUT_LOW)
+GPIO(EC_PROCHOT_ODL,		PIN(I, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(EC_AP_VCCST_PWRGD_OD,	PIN(E, 5), GPIO_ODR_LOW)
+GPIO(ALL_SYS_PWRGD,		PIN(B, 7), GPIO_OUT_LOW)
+GPIO(EN_SLP_Z,			PIN(K, 3), GPIO_OUT_LOW)
+
+/* Required for icelake chipset code, but implemented through other means for dedede */
+UNIMPLEMENTED(AC_PRESENT)
+UNIMPLEMENTED(PG_EC_DSW_PWROK)
+UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
+
+/* Used by baseboard z-state enable, but not present on gooey */
+UNIMPLEMENTED(USB_C1_INT_ODL)
+
+/* I2C pins - Alternate function below configures I2C module on these pins */
+GPIO(EC_I2C_EEPROM_SCL,		PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SDA,		PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SCL,	PIN(C, 1), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SDA,	PIN(C, 2), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,		PIN(F, 6), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SENSOR_SDA,		PIN(F, 7), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_USB_C0_SCL,		PIN(A, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SDA,		PIN(A, 5), GPIO_INPUT)
+
+/* USB pins */
+GPIO(EN_USB_A0_VBUS,		PIN(L, 6), GPIO_OUT_LOW)
+GPIO(EN_USB_A1_VBUS,		PIN(E, 6), GPIO_OUT_LOW)
+GPIO(EC_AP_USB_C0_HPD,		PIN(L, 4), GPIO_OUT_LOW)
+GPIO(EC_AP_USB_C1_HDMI_HPD,	PIN(K, 7), GPIO_OUT_LOW)
+GPIO(HDMI_SEL_L,		PIN(C, 6), GPIO_OUT_LOW)
+
+/* MKBP event synchronization */
+GPIO(EC_AP_MKBP_INT_L,	PIN(L, 5), GPIO_ODR_HIGH)
+
+/* Misc pins which will run to the I/O board */
+
+/* Misc */
+GPIO(EN_BL_OD,			PIN(K, 4), GPIO_ODR_LOW)
+GPIO(EC_ENTERING_RW,		PIN(C, 7), GPIO_OUT_LOW)
+GPIO(EC_BATTERY_PRES_ODL,	PIN(I, 4), GPIO_INPUT)
+GPIO_INT(PEN_DET_ODL,		PIN(J, 1), GPIO_INT_BOTH | GPIO_PULL_UP, pen_detect_interrupt)
+GPIO(EN_PP5000_PEN,	    	PIN(B, 5), GPIO_OUT_LOW)
+GPIO(PEN_DET_PCH,	    	PIN(F, 1), GPIO_OUT_LOW)
+GPIO(EN_KB_BL,			PIN(J, 3), GPIO_OUT_LOW) /* Currently unused */
+GPIO(EC_CBI_WP,			PIN(H, 5), GPIO_OUT_LOW)
+
+/* NC pins, enable internal pull-down to avoid floating state. */
+GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOC3_NC, PIN(C, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOC4_NC, PIN(C, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOE0_NC, PIN(E, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOF0_NC, PIN(F, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOF4_NC, PIN(F, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOF5_NC, PIN(F, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG0_NC, PIN(G, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG3_NC, PIN(G, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG4_NC, PIN(G, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG5_NC, PIN(G, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG6_NC, PIN(G, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG7_NC, PIN(G, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOH1_NC, PIN(H, 1), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOH4_NC, PIN(H, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOH6_NC, PIN(H, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ4_NC, PIN(J, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ5_NC, PIN(J, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ6_NC, PIN(J, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOL0_NC, PIN(L, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOL2_NC, PIN(L, 2), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOL3_NC, PIN(L, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOM6_NC, PIN(M, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+
+/* Alternate functions GPIO definitions */
+/* UART */
+ALTERNATE(PIN_MASK(B, BIT(0) | BIT(1)), 0, MODULE_UART, 0)		/* UART for debug */
+
+/* I2C */
+ALTERNATE(PIN_MASK(B, BIT(3) | BIT(4)), 0, MODULE_I2C, 0)		/* I2C0 */
+ALTERNATE(PIN_MASK(C, BIT(1) | BIT(2)), 0, MODULE_I2C, 0)		/* I2C1 */
+ALTERNATE(PIN_MASK(F, BIT(6) | BIT(7)), 0, MODULE_I2C, GPIO_SEL_1P8V)	/* I2C2 - 1.8V */
+ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), 0, MODULE_I2C, 0)		/* I2C5 */
+
+/* ADC */
+ALTERNATE(PIN_MASK(I, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0)	/* ADC0: EC_VSNS_PP3300_A, ADC2: TEMP_SENSOR_1, ADC3: TEMP_SENSOR_2 */
+
+/* DAC */
+ALTERNATE(PIN_MASK(J, BIT(2)), 0, MODULE_DAC, 0)			/* DAC2: EC_AP_PSYS */
+
+/* PWM */
+ALTERNATE(PIN_MASK(A, BIT(0) | BIT(1) | BIT(2) | BIT(3)), 0, MODULE_PWM, 0) /* KB_BL_PWM, LED_[R,G,B]_ODL */
diff --git a/board/gooey/led.c b/board/gooey/led.c
new file mode 100644
index 0000000000..751ffa30bf
--- /dev/null
+++ b/board/gooey/led.c
@@ -0,0 +1,117 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Gooey specific PWM LED settings.
+ */
+
+#include "common.h"
+#include "gpio.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+#include "pwm.h"
+
+#define LED_OFF_LVL 0
+#define LED_ON_LVL 1
+
+__override const int led_charge_lvl_1 = 5;
+
+__override const int led_charge_lvl_2 = 97;
+
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
+
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 3 * LED_ONE_SEC },
+					       { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    3 * LED_ONE_SEC },
+						  { LED_OFF,
+						    0.5 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_power(enum ec_led_colors color)
+{
+	if (color == EC_LED_COLOR_WHITE)
+		pwm_enable(PWM_CH_LED_WHITE, LED_ON_LVL);
+	else
+		pwm_enable(PWM_CH_LED_WHITE, LED_OFF_LVL);
+}
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_RED:
+		pwm_enable(PWM_CH_LED_RED, LED_ON_LVL);
+		pwm_enable(PWM_CH_LED_GREEN, LED_OFF_LVL);
+		break;
+	case EC_LED_COLOR_AMBER:
+		pwm_enable(PWM_CH_LED_RED, LED_ON_LVL);
+		pwm_enable(PWM_CH_LED_GREEN, LED_ON_LVL);
+		break;
+	case EC_LED_COLOR_GREEN:
+		pwm_enable(PWM_CH_LED_RED, LED_OFF_LVL);
+		pwm_enable(PWM_CH_LED_GREEN, LED_ON_LVL);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		pwm_enable(PWM_CH_LED_RED, LED_OFF_LVL);
+		pwm_enable(PWM_CH_LED_GREEN, LED_OFF_LVL);
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_RED] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		brightness_range[EC_LED_COLOR_GREEN] = 1;
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		if (brightness[EC_LED_COLOR_RED] != 0)
+			led_set_color_battery(EC_LED_COLOR_RED);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(EC_LED_COLOR_AMBER);
+		else if (brightness[EC_LED_COLOR_GREEN] != 0)
+			led_set_color_battery(EC_LED_COLOR_GREEN);
+		else
+			led_set_color_battery(LED_OFF);
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_power(EC_LED_COLOR_WHITE);
+		else
+			led_set_color_power(LED_OFF);
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/board/gooey/usb_pd_policy.c b/board/gooey/usb_pd_policy.c
new file mode 100644
index 0000000000..a7633b73ac
--- /dev/null
+++ b/board/gooey/usb_pd_policy.c
@@ -0,0 +1,71 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery_smart.h"
+#include "charge_manager.h"
+#include "charger.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "driver/charger/isl923x_public.h"
+#include "driver/tcpm/tcpci.h"
+#include "usb_pd.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+int pd_check_vconn_swap(int port)
+{
+	/* Allow VCONN swaps if the AP is on */
+	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
+}
+
+void pd_power_supply_reset(int port)
+{
+	if (port != 0)
+		return;
+
+	/* Disable VBUS */
+	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	if (port != 0)
+		return EC_ERROR_INVAL;
+
+	/* Disable charging. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
+	if (rv)
+		return rv;
+
+	/* Our policy is not to source VBUS when the AP is off. */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	/* Provide Vbus. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
+	if (rv)
+		return rv;
+
+	rv = raa489000_enable_asgate(port, true);
+	if (rv)
+		return rv;
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	return pd_check_vbus_level(port, VBUS_PRESENT);
+}
diff --git a/board/gooey/vif_override.xml b/board/gooey/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/gooey/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/goroh/battery.c b/board/goroh/battery.c
new file mode 100644
index 0000000000..4da7b255e0
--- /dev/null
+++ b/board/goroh/battery.c
@@ -0,0 +1,48 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "battery_fuel_gauge.h"
+#include "battery_smart.h"
+#include "charge_manager.h"
+#include "chipset.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "system.h"
+#include "usb_pd.h"
+
+const struct board_batt_params board_battery_info[] = {
+	[BATTERY_LGC_AP18C8K] = {
+		.fuel_gauge = {
+			.manuf_name = "LGC KT0030G020",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.reg_addr = 0x43,
+				.reg_mask = 0x0001,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0002,
+				.cfet_off_val = 0x0000,
+			},
+		},
+		.batt_info = {
+			.voltage_max            = 13050,
+			.voltage_normal         = 11250,
+			.voltage_min            = 9000,
+			.precharge_current      = 256,
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 50,
+			.charging_min_c         = 0,
+			.charging_max_c         = 60,
+			.discharging_min_c      = -20,
+			.discharging_max_c      = 75,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_LGC_AP18C8K;
diff --git a/board/goroh/board.c b/board/goroh/board.c
new file mode 100644
index 0000000000..d13c7cfb1b
--- /dev/null
+++ b/board/goroh/board.c
@@ -0,0 +1,98 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* Goroh board configuration */
+
+#include "adc.h"
+#include "button.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "driver/accel_lis2dw12.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "driver/als_tcs3400.h"
+#include "driver/charger/isl923x.h"
+#include "driver/ppc/syv682x.h"
+#include "driver/tcpm/it83xx_pd.h"
+#include "driver/temp_sensor/thermistor.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "motion_sense.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "spi.h"
+#include "switch.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "temp_sensor.h"
+#include "timer.h"
+#include "uart.h"
+#include "usb_mux.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_ppc.h"
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/* Initialize board. */
+static void board_init(void)
+{
+	/* Enable motion sensor interrupt */
+	gpio_enable_interrupt(GPIO_BASE_IMU_INT_L);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
+const struct adc_t adc_channels[] = {
+	{ "BOARD_ID", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH1 },
+	{ "TEMP_CPU", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH2 },
+	{ "TEMP_GPU", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH3 },
+	{ "TEMP_CHARGER", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH5 },
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* PWM channels.  */
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_LED_GREEN] = { .channel = PWM_HW_CH_DCR0,
+			       .flags = PWM_CONFIG_DSLEEP |
+					PWM_CONFIG_OPEN_DRAIN |
+					PWM_CONFIG_ACTIVE_LOW,
+			       .freq_hz = 324, /* maximum supported frequency */
+			       .pcfsr_sel = PWM_PRESCALER_C4 },
+	[PWM_CH_LED_RED] = { .channel = PWM_HW_CH_DCR1,
+			     .flags = PWM_CONFIG_DSLEEP |
+				      PWM_CONFIG_OPEN_DRAIN |
+				      PWM_CONFIG_ACTIVE_LOW,
+			     .freq_hz = 324, /* maximum supported frequency */
+			     .pcfsr_sel = PWM_PRESCALER_C4 },
+	[PWM_CH_FAN] = { .channel = PWM_HW_CH_DCR2,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq_hz = 25000, /* maximum supported frequency */
+			 .pcfsr_sel = PWM_PRESCALER_C4 },
+	[PWM_CH_KBLIGHT] = { .channel = PWM_HW_CH_DCR3,
+			     .flags = PWM_CONFIG_DSLEEP,
+			     .freq_hz = 25000,
+			     .pcfsr_sel = PWM_PRESCALER_C4 },
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+static void board_suspend(void)
+{
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_suspend, HOOK_PRIO_DEFAULT);
+
+static void board_resume(void)
+{
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_resume, HOOK_PRIO_DEFAULT);
diff --git a/board/goroh/board.h b/board/goroh/board.h
new file mode 100644
index 0000000000..d0f3733053
--- /dev/null
+++ b/board/goroh/board.h
@@ -0,0 +1,130 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* Goroh board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "baseboard.h"
+
+/* Chipset config */
+#define CONFIG_BRINGUP
+
+/* Optional features */
+#define CONFIG_LTO
+
+/*
+ * TODO: Remove this option once the VBAT no longer keeps high when
+ * system's power isn't presented.
+ */
+#define CONFIG_IT83XX_RESET_PD_CONTRACT_IN_BRAM
+
+/* LED */
+#define CONFIG_LED_PWM_COUNT 1
+#define CONFIG_LED_PWM
+#define CONFIG_LED_POWER_LED
+#undef CONFIG_LED_PWM_NEAR_FULL_COLOR
+#undef CONFIG_LED_PWM_CHARGE_COLOR
+#undef CONFIG_LED_PWM_CHARGE_ERROR_COLOR
+#undef CONFIG_LED_PWM_LOW_BATT_COLOR
+#undef CONFIG_LED_PWM_SOC_ON_COLOR
+#undef CONFIG_LED_PWM_SOC_SUSPEND_COLOR
+#define CONFIG_LED_PWM_NEAR_FULL_COLOR EC_LED_COLOR_GREEN
+#define CONFIG_LED_PWM_CHARGE_COLOR EC_LED_COLOR_GREEN
+#define CONFIG_LED_PWM_CHARGE_ERROR_COLOR EC_LED_COLOR_RED
+#define CONFIG_LED_PWM_LOW_BATT_COLOR EC_LED_COLOR_RED
+#define CONFIG_LED_PWM_SOC_ON_COLOR EC_LED_COLOR_COUNT /* OFF */
+#define CONFIG_LED_PWM_SOC_SUSPEND_COLOR EC_LED_COLOR_COUNT /* OFF */
+
+/* PD / USB-C / PPC */
+#define CONFIG_USB_PD_DEBUG_LEVEL 3
+
+/* Optional console commands */
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_SCRATCHPAD
+
+#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV 9000
+
+/* Sensor */
+#define CONFIG_GMR_TABLET_MODE
+#define CONFIG_TABLET_MODE
+#define CONFIG_TABLET_MODE_SWITCH
+
+#define CONFIG_ACCELGYRO_BMI160 /* Base accel */
+#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+#define CONFIG_LID_ANGLE_UPDATE
+
+#define CONFIG_ACCEL_BMA255 /* Lid accel BMA253 */
+
+/* Sensors without hardware FIFO are in forced mode */
+#define CONFIG_ACCEL_FORCE_MODE_MASK \
+	(BIT(LID_ACCEL) | BIT(BASE_GYRO) | BIT(BASE_ACCEL))
+
+/* Thermistors */
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_THERMISTOR
+#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
+
+/* SPI / Host Command */
+#undef CONFIG_HOSTCMD_DEBUG_MODE
+#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
+
+/* USB-A */
+#define USBA_PORT_COUNT 1
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum battery_type {
+	BATTERY_LGC_AP18C8K,
+	BATTERY_TYPE_COUNT,
+};
+
+enum sensor_id {
+	BASE_ACCEL = 0,
+	BASE_GYRO,
+	LID_ACCEL,
+
+	SENSOR_COUNT,
+};
+
+enum adc_channel {
+	ADC_BOARD_ID, /* ADC 1 */
+	ADC_TEMP_SENSOR_CPU, /* ADC 2 */
+	ADC_TEMP_SENSOR_GPU, /* ADC 3 */
+	ADC_TEMP_SENSOR_CHARGER, /* ADC 5 */
+
+	/* Number of ADC channels */
+	ADC_CH_COUNT,
+};
+
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
+
+enum pwm_channel {
+	PWM_CH_LED_GREEN,
+	PWM_CH_LED_RED,
+	PWM_CH_FAN,
+	PWM_CH_KBLIGHT,
+	PWM_CH_COUNT,
+};
+
+enum fan_channel { FAN_CH_0, FAN_CH_COUNT };
+
+enum temp_sensor_id {
+	TEMP_SENSOR_CPU,
+	TEMP_SENSOR_GPU,
+	TEMP_SENSOR_CHARGER,
+	TEMP_SENSOR_COUNT,
+};
+
+#endif /* !__ASSEMBLER__ */
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/goroh/build.mk b/board/goroh/build.mk
new file mode 100644
index 0000000000..5f2dea191a
--- /dev/null
+++ b/board/goroh/build.mk
@@ -0,0 +1,18 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+
+# the IC is ITE IT8xxx2
+CHIP:=it83xx
+CHIP_FAMILY:=it8xxx2
+CHIP_VARIANT:=it81202bx_1024
+BASEBOARD:=goroh
+
+board-y+=battery.o
+board-y+=board.o
+board-y+=fans.o
+board-y+=led.o
+board-y+=sensors.o
diff --git a/board/goroh/ec.tasklist b/board/goroh/ec.tasklist
new file mode 100644
index 0000000000..148b7679ae
--- /dev/null
+++ b/board/goroh/ec.tasklist
@@ -0,0 +1,20 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(PDCMD, pd_command_task, NULL, 1024) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 1024) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, 1280) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, 1280) \
+
diff --git a/board/goroh/fans.c b/board/goroh/fans.c
new file mode 100644
index 0000000000..1ac9a79acb
--- /dev/null
+++ b/board/goroh/fans.c
@@ -0,0 +1,91 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Physical fans. These are logically separate from pwm_channels. */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "fan.h"
+#include "hooks.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+
+const struct fan_conf fan_conf_0 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = PWM_CH_FAN,
+	.pgood_gpio = -1,
+	.enable_gpio = GPIO_EN_PP5000_FAN_X,
+};
+
+const struct fan_rpm fan_rpm_0 = {
+	.rpm_min = 2400,
+	.rpm_start = 2400,
+	.rpm_max = 5700,
+};
+
+const struct fan_t fans[] = {
+	[FAN_CH_0] = {
+		.conf = &fan_conf_0,
+		.rpm = &fan_rpm_0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(fans) == CONFIG_FANS);
+/*
+ * PWM HW channelx binding tachometer channelx for fan control.
+ * Four tachometer input pins but two tachometer modules only,
+ * so always binding [TACH_CH_TACH0A | TACH_CH_TACH0B] and/or
+ * [TACH_CH_TACH1A | TACH_CH_TACH1B]
+ */
+const struct fan_tach_t fan_tach[] = {
+	[PWM_HW_CH_DCR0] = {
+		.ch_tach = TACH_CH_NULL,
+		.fan_p = -1,
+		.rpm_re = -1,
+		.s_duty = -1,
+	},
+	[PWM_HW_CH_DCR1] = {
+		.ch_tach = TACH_CH_NULL,
+		.fan_p = -1,
+		.rpm_re = -1,
+		.s_duty = -1,
+	},
+	[PWM_HW_CH_DCR2] = {
+		.ch_tach = TACH_CH_TACH0A,
+		.fan_p = 2,
+		.rpm_re = 50,
+		.s_duty = 30,
+	},
+	[PWM_HW_CH_DCR3] = {
+		.ch_tach = TACH_CH_NULL,
+		.fan_p = -1,
+		.rpm_re = -1,
+		.s_duty = -1,
+	},
+	[PWM_HW_CH_DCR4] = {
+		.ch_tach = TACH_CH_NULL,
+		.fan_p = -1,
+		.rpm_re = -1,
+		.s_duty = -1,
+	},
+	[PWM_HW_CH_DCR5] = {
+		.ch_tach = TACH_CH_NULL,
+		.fan_p = -1,
+		.rpm_re = -1,
+		.s_duty = -1,
+	},
+	[PWM_HW_CH_DCR6] = {
+		.ch_tach = TACH_CH_NULL,
+		.fan_p = -1,
+		.rpm_re = -1,
+		.s_duty = -1,
+	},
+	[PWM_HW_CH_DCR7] = {
+		.ch_tach = TACH_CH_NULL,
+		.fan_p = -1,
+		.rpm_re = -1,
+		.s_duty = -1,
+	},
+};
diff --git a/board/goroh/gpio.inc b/board/goroh/gpio.inc
new file mode 100644
index 0000000000..5d534044fe
--- /dev/null
+++ b/board/goroh/gpio.inc
@@ -0,0 +1,156 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+/* Wake Source interrupts */
+GPIO_INT(POWER_BUTTON_L,     PIN(E, 4), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,
+	power_button_interrupt) /* H1_EC_PWR_BTN_ODL */
+GPIO_INT(LID_OPEN,           PIN(E, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,
+         lid_interrupt)
+GPIO_INT(TABLET_MODE_L,      PIN(J, 7), GPIO_INT_BOTH,
+         gmr_tablet_switch_isr)
+
+/* Power sequencing interrupts */
+GPIO_INT(AP_EC_WARM_RST_REQ, PIN(D, 3), GPIO_INT_RISING | GPIO_SEL_1P8V,
+         chipset_reset_request_interrupt)
+GPIO_INT(AP_EC_SHUTDOWN_REQ_L, PIN(F, 2),
+         GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V,
+         chipset_reset_request_interrupt)
+GPIO_INT(AP_EC_WATCHDOG_L,   PIN(C, 7), GPIO_INT_BOTH | GPIO_SEL_1P8V,
+         power_signal_interrupt)
+GPIO_INT(PG_S5_PWR_OD,           PIN(A, 6), GPIO_INT_BOTH,
+	 power_signal_interrupt)
+GPIO_INT(PG_VDD1_VDD2_OD,        PIN(M, 6), GPIO_INT_BOTH | GPIO_SEL_1P8V,
+	 power_signal_interrupt)
+GPIO_INT(PG_VDD_MEDIA_ML_OD,     PIN(J, 3), GPIO_INT_BOTH,
+	 power_signal_interrupt)
+GPIO_INT(PG_VDD_SOC_OD,          PIN(J, 4), GPIO_INT_BOTH,
+	 power_signal_interrupt)
+GPIO_INT(PG_VDD_DDR_OD,          PIN(J, 5), GPIO_INT_BOTH,
+	 power_signal_interrupt)
+
+/* Sensor Interrupts */
+GPIO_INT(BASE_IMU_INT_L,     PIN(M, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V,
+         bmi160_interrupt)
+
+/* USB-C interrupts */
+GPIO_INT(USB_C0_FAULT_ODL,   PIN(D, 1), GPIO_INT_BOTH, ppc_interrupt)
+GPIO_INT(USB_C1_FAULT_ODL,   PIN(B, 2), GPIO_INT_BOTH, ppc_interrupt)
+
+/* Volume button interrupts */
+GPIO_INT(EC_VOLUP_BTN_ODL,       PIN(D, 5), GPIO_INT_BOTH, button_interrupt)
+GPIO_INT(EC_VOLDN_BTN_ODL,       PIN(H, 6), GPIO_INT_BOTH, button_interrupt)
+
+/* Other interrupts */
+GPIO_INT(ACOK_OD,            PIN(E, 5), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,
+         extpower_interrupt) /* AC_OK / AC_PRESENT in rev1+ */
+GPIO_INT(UART1_RX,           PIN(B, 0), GPIO_INT_FALLING,
+         uart_deepsleep_interrupt) /* UART_DEBUG_TX_EC_RX */
+GPIO_INT(WP,                 PIN(I, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V,
+         switch_interrupt) /* EC_FLASH_WP_OD */
+GPIO_INT(SPI0_CS,            PIN(M, 5), GPIO_INT_FALLING,
+         spi_event)        /* SPI slave Chip Select -- AP_SPI_EC_CS_L */
+
+/* Power Sequencing Signals */
+GPIO(EN_PP1800_S5,           PIN(H, 0), GPIO_OUT_LOW)
+GPIO(EN_PP5000_S5,           PIN(C, 6), GPIO_OUT_HIGH) /* default high for PPC init on start up. */
+GPIO(EN_VDD_SOC,             PIN(E, 1), GPIO_OUT_LOW)
+GPIO(EN_VDD_MEDIA_ML,        PIN(F, 1), GPIO_OUT_LOW)
+GPIO(SYS_RST_ODL,            PIN(B, 6), GPIO_ODR_LOW)
+GPIO(EC_BL_EN_OD,            PIN(B, 5), GPIO_ODR_LOW | GPIO_SEL_1P8V)
+GPIO(EN_VDDQ_VR_D,           PIN(M, 3), GPIO_OUT_LOW)
+GPIO(EN_PP1820A_IO_X,        PIN(D, 4), GPIO_OUT_LOW)
+GPIO(EN_PP1800_VDD33_PMC_X,  PIN(D, 0), GPIO_OUT_LOW)
+GPIO(EN_PP0800_VDD_PMC_X,    PIN(D, 2), GPIO_OUT_LOW)
+GPIO(EN_VDD1_VDD2_VR,        PIN(A, 7), GPIO_OUT_LOW)
+GPIO(EN_PP3300A_IO_X,        PIN(D, 7), GPIO_OUT_LOW)
+GPIO(EN_VDD_DDR,             PIN(I, 0), GPIO_OUT_LOW)
+GPIO(EN_VDD_CPU,             PIN(F, 3), GPIO_OUT_LOW)
+GPIO(EN_PP1800_S3,           PIN(G, 2), GPIO_OUT_LOW)
+GPIO(EN_PP3300_S3,           PIN(G, 3), GPIO_OUT_LOW)
+GPIO(EN_VDD_GPU,             PIN(G, 1), GPIO_OUT_LOW)
+GPIO(EN_PP1800_VDDIO_PMC_X,    PIN(B, 7), GPIO_OUT_LOW)
+
+/* MKBP event synchronization */
+GPIO(EC_INT_L,               PIN(E, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V) /* EC_AP_INT_ODL */
+
+/* USB and USBC Signals */
+GPIO(USB_C1_HPD_3V3,         PIN(J, 0), GPIO_OUT_LOW)
+GPIO(USB_C0_HPD_3V3,         PIN(J, 1), GPIO_OUT_LOW)
+GPIO(USB_C1_HPD_IN,          PIN(J, 2), GPIO_OUT_LOW)
+GPIO(EN_USB_C1_MUX_PWR,      PIN(F, 0), GPIO_OUT_LOW)
+GPIO(USB_C0_SBU1_DC,         PIN(H, 4), GPIO_OUT_LOW)
+GPIO(USB_C0_SBU2_DC,         PIN(H, 5), GPIO_OUT_LOW)
+
+/* Misc Signals */
+GPIO(EC_BATT_PRES_ODL,       PIN(C, 0), GPIO_INPUT)
+GPIO(ENTERING_RW,            PIN(C, 5), GPIO_OUT_LOW) /* EC_ENTERING_RW */
+GPIO(EN_EC_ID_ODL,           PIN(C, 3), GPIO_OUT_LOW)
+GPIO(EN_PP5000_FAN_X,        PIN(E, 3), GPIO_OUT_LOW)
+GPIO(EN_PPVAR_KB_BL_X,       PIN(H, 3), GPIO_OUT_LOW)
+
+/* I2C pins - Alternate function below configures I2C module on these pins */
+GPIO(I2C_A_SCL,              PIN(B, 3), GPIO_INPUT) /* I2C_CHG_BATT_SCL */
+GPIO(I2C_A_SDA,              PIN(B, 4), GPIO_INPUT) /* I2C_CHG_BATT_SDA */
+GPIO(I2C_B_SCL,              PIN(C, 1), GPIO_INPUT | GPIO_SEL_1P8V) /* I2C_SENSOR_SCL */
+GPIO(I2C_B_SDA,              PIN(C, 2), GPIO_INPUT | GPIO_SEL_1P8V) /* I2C_SENSOR_SDA */
+GPIO(I2C_C_SCL,              PIN(F, 6), GPIO_INPUT) /* I2C_USB_C0_SCL */
+GPIO(I2C_C_SDA,              PIN(F, 7), GPIO_INPUT) /* I2C_USB_C0_SCL */
+GPIO(I2C_E_SCL,              PIN(E, 0), GPIO_INPUT) /* I2C_USB_C1_SCL */
+GPIO(I2C_E_SDA,              PIN(E, 7), GPIO_INPUT) /* I2C_USB_C1_SDA */
+
+/* SPI pins - Alternate function below configures SPI module on these pins */
+
+/* NC / TP */
+
+/* Keyboard pins */
+
+/* CLOCK */
+GPIO(CLK_32_EC,              PIN(J, 6), GPIO_INPUT)
+
+/* Alternate functions GPIO definitions */
+ALTERNATE(PIN_MASK(B, 0x18), 1, MODULE_I2C, 0) /* I2C A */
+ALTERNATE(PIN_MASK(C, 0x06), 1, MODULE_I2C, GPIO_SEL_1P8V) /* I2C B */
+ALTERNATE(PIN_MASK(F, 0xC0), 1, MODULE_I2C, 0) /* I2C C */
+ALTERNATE(PIN_MASK(E, 0x81), 1, MODULE_I2C, 0) /* I2C E */
+
+/* UART */
+ALTERNATE(PIN_MASK(B, 0x03), 1, MODULE_UART, 0) /* EC to Servo */
+
+/* PWM */
+ALTERNATE(PIN_MASK(A, 0x0F), 1, MODULE_PWM, 0) /* PWM 0~3 */
+ALTERNATE(PIN_MASK(D, 0x40), 3, MODULE_PWM, GPIO_PULL_UP) /* TACH0A for FAN1 */
+
+/* ADC */
+ALTERNATE(PIN_MASK(I, 0x2E), 0, MODULE_ADC, 0) /* ADC 1,2,3,5 */
+
+/* SPI */
+ALTERNATE(PIN_MASK(M, 0x33), 0, MODULE_SPI, 0) /* SPI */
+
+/* unused, configure as input pin */
+GPIO(LID_ACCEL_INT_L,    PIN(G, 0), GPIO_INPUT | GPIO_SEL_1P8V)
+
+/* *_ODL pin has external pullup so don't pull it down. */
+
+/* reserved for future use */
+GPIO(CCD_MODE_ODL,           PIN(C, 4), GPIO_INPUT)
+/*
+ * ADC pins don't have internal pull-down capability,
+ * so we set them as output low.
+ */
+GPIO(NC_GPI7,                PIN(I, 7), GPIO_OUT_LOW)
+/* NC pins, enable internal pull-up/down to avoid floating state. */
+GPIO(SPI_CLK_GPG6,           PIN(G, 6), GPIO_INPUT | GPIO_PULL_UP)
+/*
+ * These 3 pins don't have internal pull-down capability,
+ * so we set them as output low.
+ */
+GPIO(SPI_MOSI_GPG4,          PIN(G, 4), GPIO_OUT_LOW)
+GPIO(SPI_MISO_GPG5,          PIN(G, 5), GPIO_OUT_LOW)
+GPIO(SPI_CS_GPG7,            PIN(G, 7), GPIO_OUT_LOW)
diff --git a/board/goroh/led.c b/board/goroh/led.c
new file mode 100644
index 0000000000..7ed155acc0
--- /dev/null
+++ b/board/goroh/led.c
@@ -0,0 +1,63 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+#include "led_common.h"
+#include "led_pwm.h"
+#include "pwm.h"
+
+struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = {
+	/* Green, Red */
+	[EC_LED_COLOR_RED] = { 0, 100 }, [EC_LED_COLOR_GREEN] = { 100, 0 },
+	[EC_LED_COLOR_BLUE] = { 0, 0 },	 [EC_LED_COLOR_YELLOW] = { 0, 0 },
+	[EC_LED_COLOR_WHITE] = { 0, 0 }, [EC_LED_COLOR_AMBER] = { 0, 0 },
+};
+
+struct pwm_led pwm_leds[CONFIG_LED_PWM_COUNT] = {
+	[PWM_LED0] = {
+		/* left port LEDs */
+		.ch0 = PWM_CH_LED_GREEN,
+		.ch1 = PWM_CH_LED_RED,
+		.ch2 = PWM_LED_NO_CHANNEL,
+		.enable = &pwm_enable,
+		.set_duty = &pwm_set_duty,
+	},
+};
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_BATTERY_LED,
+	EC_LED_ID_POWER_LED,
+};
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED)
+		brightness_range[EC_LED_COLOR_RED] = 100;
+	else if (led_id == EC_LED_ID_POWER_LED)
+		brightness_range[EC_LED_COLOR_GREEN] = 100;
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	enum pwm_led_id pwm_id;
+
+	/* Convert ec_led_id to pwm_led_id. */
+	if (led_id == EC_LED_ID_POWER_LED || led_id == EC_LED_ID_BATTERY_LED)
+		pwm_id = PWM_LED0;
+	else
+		return EC_ERROR_UNKNOWN;
+
+	if (brightness[EC_LED_COLOR_RED])
+		set_pwm_led_color(pwm_id, EC_LED_COLOR_RED);
+	else if (brightness[EC_LED_COLOR_GREEN])
+		set_pwm_led_color(pwm_id, EC_LED_COLOR_GREEN);
+	else
+		/* Otherwise, the "color" is "off". */
+		set_pwm_led_color(pwm_id, -1);
+
+	return EC_SUCCESS;
+}
diff --git a/board/goroh/sensors.c b/board/goroh/sensors.c
new file mode 100644
index 0000000000..8236627e47
--- /dev/null
+++ b/board/goroh/sensors.c
@@ -0,0 +1,124 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* Goroh sensors configuration */
+
+#include "driver/accel_bma2x2.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "driver/als_tcs3400.h"
+#include "driver/temp_sensor/thermistor.h"
+#include "lid_switch.h"
+#include "motion_sense.h"
+#include "spi.h"
+#include "temp_sensor.h"
+#include "thermal.h"
+
+static struct mutex g_base_mutex;
+static struct mutex g_lid_mutex;
+
+static struct bmi_drv_data_t g_bmi160_data;
+static struct accelgyro_saved_data_t g_bma253_data;
+
+struct motion_sensor_t motion_sensors[] = {
+	/*
+	 * Note: bmi160: supports accelerometer and gyro sensor
+	 * Requirement: accelerometer sensor must init before gyro sensor
+	 * DO NOT change the order of the following table.
+	 */
+	[BASE_ACCEL] = {
+		.name = "Base Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMI160,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &bmi160_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = &g_bmi160_data,
+		.port = I2C_PORT_ACCEL,
+		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+		.rot_standard_ref = NULL, /* identity matrix */
+		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
+		.min_frequency = BMI_ACCEL_MIN_FREQ,
+		.max_frequency = BMI_ACCEL_MAX_FREQ,
+		.config = {
+			/* Sensor on for angle detection */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+			/* Sensor on for angle detection */
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+		},
+	},
+	[BASE_GYRO] = {
+		.name = "Base Gyro",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMI160,
+		.type = MOTIONSENSE_TYPE_GYRO,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &bmi160_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = &g_bmi160_data,
+		.port = I2C_PORT_ACCEL,
+		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+		.default_range = 1000, /* dps */
+		.rot_standard_ref = NULL, /* identity matrix */
+		.min_frequency = BMI_GYRO_MIN_FREQ,
+		.max_frequency = BMI_GYRO_MAX_FREQ,
+	},
+	[LID_ACCEL] = {
+		.name = "Lid Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMA255,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &bma2x2_accel_drv,
+		.mutex = &g_lid_mutex,
+		.drv_data = &g_bma253_data,
+		.port = I2C_PORT_ACCEL,
+		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
+		.rot_standard_ref = NULL, /* identity matrix */
+		.min_frequency = BMI_GYRO_MIN_FREQ,
+		.min_frequency = BMA255_ACCEL_MIN_FREQ,
+		.max_frequency = BMA255_ACCEL_MAX_FREQ,
+		.default_range = 2, /* g, to support tablet mode */
+		.config = {
+			/* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+			/* Sensor on in S3 */
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+		},
+	},
+};
+const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+/* Temperature sensor configuration */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_CPU] = {
+		.name = "CPU",
+		.type = TEMP_SENSOR_TYPE_CPU,
+		.read = get_temp_3v3_51k1_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_CPU,
+	},
+	[TEMP_SENSOR_GPU] = {
+		.name = "GPU",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_51k1_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_GPU,
+	},
+	[TEMP_SENSOR_CHARGER] = {
+		.name = "Charger",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_51k1_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_CHARGER,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
diff --git a/board/goroh/usbc_confg.c b/board/goroh/usbc_confg.c
new file mode 100644
index 0000000000..a2d268877f
--- /dev/null
+++ b/board/goroh/usbc_confg.c
@@ -0,0 +1,33 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/bc12/pi3usb9201_public.h"
+#include "driver/ppc/nx20p348x.h"
+#include "driver/ppc/syv682x_public.h"
+#include "driver/retimer/bb_retimer_public.h"
+#include "driver/tcpm/nct38xx.h"
+#include "driver/tcpm/ps8xxx_public.h"
+#include "driver/tcpm/tcpci.h"
+#include "ec_commands.h"
+#include "fw_config.h"
+#include "gpio.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+static void board_tcpc_init(void)
+{
+	/* Don't reset TCPCs after initial reset */
+	if (!system_jumped_late())
+		board_reset_pd_mcu();
+
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_FAULT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_FAULT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
diff --git a/board/goroh/vif_override.xml b/board/goroh/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/goroh/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/grunt/battery.c b/board/grunt/battery.c
index 359ec9785b..7c7ec44c56 100644
--- a/board/grunt/battery.c
+++ b/board/grunt/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/grunt/board.c b/board/grunt/board.c
index 45aa4f4421..96b8f986b7 100644
--- a/board/grunt/board.c
+++ b/board/grunt/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,6 +18,7 @@
 #include "pwm_chip.h"
 #include "switch.h"
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 const enum gpio_signal hibernate_wake_pins[] = {
@@ -25,16 +26,40 @@ const enum gpio_signal hibernate_wake_pins[] = {
 	GPIO_AC_PRESENT,
 	GPIO_POWER_BUTTON_L,
 };
-const int hibernate_wake_pins_used =  ARRAY_SIZE(hibernate_wake_pins);
+const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 
 /* I2C port map. */
 const struct i2c_port_t i2c_ports[] = {
-	{"power",   I2C_PORT_POWER,   100, GPIO_I2C0_SCL, GPIO_I2C0_SDA},
-	{"tcpc0",   I2C_PORT_TCPC0,   400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"tcpc1",   I2C_PORT_TCPC1,   400, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-	{"thermal", I2C_PORT_THERMAL_AP, 400, GPIO_I2C3_SCL, GPIO_I2C3_SDA},
-	{"kblight", I2C_PORT_KBLIGHT, 100, GPIO_I2C5_SCL, GPIO_I2C5_SDA},
-	{"sensor",  I2C_PORT_SENSOR,  400, GPIO_I2C7_SCL, GPIO_I2C7_SDA},
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_I2C0_SCL,
+	  .sda = GPIO_I2C0_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "tcpc1",
+	  .port = I2C_PORT_TCPC1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "thermal",
+	  .port = I2C_PORT_THERMAL_AP,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
+	{ .name = "kblight",
+	  .port = I2C_PORT_KBLIGHT,
+	  .kbps = 100,
+	  .scl = GPIO_I2C5_SCL,
+	  .sda = GPIO_I2C5_SDA },
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_I2C7_SCL,
+	  .sda = GPIO_I2C7_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
diff --git a/board/grunt/board.h b/board/grunt/board.h
index 2585db17fd..b8cb063dee 100644
--- a/board/grunt/board.h
+++ b/board/grunt/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,7 @@
  * By default, enable all console messages excepted HC, ACPI and event:
  * The sensor stack is generating a lot of activity.
  */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
 #undef CONFIG_HOSTCMD_DEBUG_MODE
 #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
 
@@ -51,7 +51,6 @@
 #define CONFIG_ACCELGYRO_BMI160
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCEL_INTERRUPTS
 #define CONFIG_ACCEL_KX022
 #define CONFIG_CMD_ACCELS
 #define CONFIG_CMD_ACCEL_INFO
@@ -63,7 +62,7 @@
 /*
  * Slew rate on the PP1800_SENSOR load switch requires a short delay on startup.
  */
-#undef  CONFIG_MOTION_SENSE_RESUME_DELAY_US
+#undef CONFIG_MOTION_SENSE_RESUME_DELAY_US
 #define CONFIG_MOTION_SENSE_RESUME_DELAY_US (10 * MSEC)
 
 #ifndef __ASSEMBLER__
diff --git a/board/grunt/build.mk b/board/grunt/build.mk
index c808e65aed..d24127ddae 100644
--- a/board/grunt/build.mk
+++ b/board/grunt/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/grunt/ec.tasklist b/board/grunt/ec.tasklist
index dc898c4502..9572d61c8f 100644
--- a/board/grunt/ec.tasklist
+++ b/board/grunt/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/grunt/gpio.inc b/board/grunt/gpio.inc
index 97f5afabfd..8c75686f47 100644
--- a/board/grunt/gpio.inc
+++ b/board/grunt/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/grunt/led.c b/board/grunt/led.c
index 9cd1122665..0a7a794bfd 100644
--- a/board/grunt/led.c
+++ b/board/grunt/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,14 +18,11 @@ const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
  * We only have a blue and an amber LED, so setting any other colour results in
  * both LEDs being off.
  */
-struct pwm_led led_color_map[EC_LED_COLOR_COUNT] = {
-				/* Amber, Blue */
-	[EC_LED_COLOR_RED]    = {   0,   0 },
-	[EC_LED_COLOR_GREEN]  = {   0,   0 },
-	[EC_LED_COLOR_BLUE]   = {   0, 100 },
-	[EC_LED_COLOR_YELLOW] = {   0,   0 },
-	[EC_LED_COLOR_WHITE]  = {   0,   0 },
-	[EC_LED_COLOR_AMBER]  = {  100,  0 },
+struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = {
+	/* Amber, Blue */
+	[EC_LED_COLOR_RED] = { 0, 0 },	  [EC_LED_COLOR_GREEN] = { 0, 0 },
+	[EC_LED_COLOR_BLUE] = { 0, 100 }, [EC_LED_COLOR_YELLOW] = { 0, 0 },
+	[EC_LED_COLOR_WHITE] = { 0, 0 },  [EC_LED_COLOR_AMBER] = { 100, 0 },
 };
 
 /* One logical LED with amber and blue channels. */
diff --git a/board/grunt/vif_override.xml b/board/grunt/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/grunt/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/gumboz/analyzestack.yaml b/board/gumboz/analyzestack.yaml
new file mode 100644
index 0000000000..7ff5f39644
--- /dev/null
+++ b/board/gumboz/analyzestack.yaml
@@ -0,0 +1,2 @@
+remove:
+- panic_assert_fail
diff --git a/board/gumboz/battery.c b/board/gumboz/battery.c
new file mode 100644
index 0000000000..8b9b3ddf96
--- /dev/null
+++ b/board/gumboz/battery.c
@@ -0,0 +1,211 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "common.h"
+#include "util.h"
+
+/*
+ * Battery info for all Gumboz battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	/* Simplo Coslight Battery Information */
+	[BATTERY_SIMPLO_COS] = {
+		.fuel_gauge = {
+			.manuf_name = "333-1C-DA-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,	/* mV */
+			.voltage_normal = 7700,
+			.voltage_min = 6000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
+
+	/* Simplo HIGHPOWER Battery Information */
+	[BATTERY_SIMPLO_HIGHPOWER] = {
+		.fuel_gauge = {
+			.manuf_name = "333-1D-DA-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,	/* mV */
+			.voltage_normal = 7700,
+			.voltage_min = 6000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
+
+	/* Samsung SDI Battery Information */
+	[BATTERY_SAMSUNG_SDI] = {
+		.fuel_gauge = {
+			.manuf_name = "333-54-DA-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,	/* mV */
+			.voltage_normal = 7700,
+			.voltage_min = 6000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
+
+	/* DynaPack ATL Battery Information */
+	[BATTERY_DYNAPACK_ATL] = {
+		.fuel_gauge = {
+			.manuf_name = "333-27-DA-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,	/* mV */
+			.voltage_normal = 7700,
+			.voltage_min = 6000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
+
+	/* DynaPack Cosmx Battery Information */
+	[BATTERY_DYNAPACK_COS] = {
+		.fuel_gauge = {
+			.manuf_name = "333-2C-DA-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,	/* mV */
+			.voltage_normal = 7700,
+			.voltage_min = 6000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
+
+	/* Cosmx Battery Information */
+	[BATTERY_COSMX] = {
+		.fuel_gauge = {
+			.manuf_name = "333-AC-DA-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,	/* mV */
+			.voltage_normal = 7700,
+			.voltage_min = 6000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SIMPLO_COS;
diff --git a/board/gumboz/board.c b/board/gumboz/board.c
new file mode 100644
index 0000000000..b6388983d7
--- /dev/null
+++ b/board/gumboz/board.c
@@ -0,0 +1,647 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery_smart.h"
+#include "button.h"
+#include "charge_state.h"
+#include "cros_board_info.h"
+#include "driver/accel_kionix.h"
+#include "driver/accelgyro_lsm6dsm.h"
+#include "driver/bc12/pi3usb9201.h"
+#include "driver/ppc/aoz1380_public.h"
+#include "driver/ppc/nx20p348x.h"
+#include "driver/tcpm/nct38xx.h"
+#include "driver/usb_mux/amd_fp5.h"
+#include "driver/usb_mux/ps8743.h"
+#include "extpower.h"
+#include "fan.h"
+#include "fan_chip.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "ioexpander.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "switch.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "temp_sensor.h"
+#include "thermal.h"
+#include "usb_charge.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_ppc.h"
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/* This I2C moved. Temporarily detect and support the V0 HW. */
+int I2C_PORT_BATTERY = I2C_PORT_BATTERY_V1;
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* Motion sensors */
+static struct mutex g_lid_mutex;
+static struct mutex g_base_mutex;
+
+/* sensor private data */
+static struct kionix_accel_data g_kx022_data;
+static struct lsm6dsm_data g_lsm6dsm_data = LSM6DSM_DATA;
+
+/* Matrix to rotate accelrator into standard reference frame */
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
+
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, FLOAT_TO_FP(-1), 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
+
+/* TODO(gcc >= 5.0) Remove the casts to const pointer at rot_standard_ref */
+struct motion_sensor_t motion_sensors[] = {
+	[LID_ACCEL] = {
+		.name = "Lid Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_KX022,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &kionix_accel_drv,
+		.mutex = &g_lid_mutex,
+		.drv_data = &g_kx022_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
+		.rot_standard_ref = &lid_standard_ref,
+		.default_range = 2, /* g */
+		/* We only use 2g because its resolution is only 8-bits */
+		.min_frequency = KX022_ACCEL_MIN_FREQ,
+		.max_frequency = KX022_ACCEL_MAX_FREQ,
+		.config = {
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+		},
+	},
+
+	[BASE_ACCEL] = {
+		.name = "Base Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LSM6DSM,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &lsm6dsm_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = LSM6DSM_ST_DATA(g_lsm6dsm_data,
+				MOTIONSENSE_TYPE_ACCEL),
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
+	  .default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = LSM6DSM_ODR_MIN_VAL,
+		.max_frequency = LSM6DSM_ODR_MAX_VAL,
+		.config = {
+			/* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 13000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+			/* Sensor on for angle detection */
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+		},
+	},
+
+	[BASE_GYRO] = {
+		.name = "Base Gyro",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LSM6DSM,
+		.type = MOTIONSENSE_TYPE_GYRO,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &lsm6dsm_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = LSM6DSM_ST_DATA(g_lsm6dsm_data,
+				MOTIONSENSE_TYPE_GYRO),
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
+		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = LSM6DSM_ODR_MIN_VAL,
+		.max_frequency = LSM6DSM_ODR_MAX_VAL,
+	},
+};
+
+unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+/*****************************************************************************
+ * Retimers
+ */
+
+static void retimers_on(void)
+{
+	/* usba retimer power on */
+	ioex_set_level(IOEX_USB_A1_RETIMER_EN, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, retimers_on, HOOK_PRIO_DEFAULT);
+
+static void retimers_off(void)
+{
+	/* usba retimer power off */
+	ioex_set_level(IOEX_USB_A1_RETIMER_EN, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, retimers_off, HOOK_PRIO_DEFAULT);
+
+/*****************************************************************************
+ * USB-C
+ */
+
+/*
+ * USB C0 port SBU mux use standalone PI3USB221
+ * chip and it need a board specific driver.
+ * Overall, it will use chained mux framework.
+ */
+static int pi3usb221_set_mux(const struct usb_mux *me, mux_state_t mux_state,
+			     bool *ack_required)
+{
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
+	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
+		ioex_set_level(IOEX_USB_C0_SBU_FLIP, 1);
+	else
+		ioex_set_level(IOEX_USB_C0_SBU_FLIP, 0);
+
+	return EC_SUCCESS;
+}
+
+/*
+ * .init is not necessary here because it has nothing
+ * to do. Primary mux will handle mux state so .get is
+ * not needed as well. usb_mux.c can handle the situation
+ * properly.
+ */
+const struct usb_mux_driver usbc0_sbu_mux_driver = {
+	.set = pi3usb221_set_mux,
+};
+
+/*
+ * Since PI3USB221 is not a i2c device, .i2c_port and
+ * .i2c_addr_flags are not required here.
+ */
+const struct usb_mux_chain usbc0_sbu_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &usbc0_sbu_mux_driver,
+		},
+};
+
+struct usb_mux_chain usbc1_amd_fp5_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.i2c_port = I2C_PORT_USB_AP_MUX,
+			.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
+			.driver = &amd_fp5_usb_mux_driver,
+			.flags = USB_MUX_FLAG_SET_WITHOUT_FLIP,
+		},
+};
+
+struct usb_mux_chain usb_muxes[] = {
+	[USBC_PORT_C0] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.i2c_port = I2C_PORT_USB_AP_MUX,
+			.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
+			.driver = &amd_fp5_usb_mux_driver,
+		},
+		.next = &usbc0_sbu_mux,
+	},
+	[USBC_PORT_C1] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.i2c_port = I2C_PORT_TCPC1,
+			.i2c_addr_flags = PS8743_I2C_ADDR1_FLAG,
+			.driver = &ps8743_usb_mux_driver,
+		},
+		.next = &usbc1_amd_fp5_usb_mux,
+	}
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
+
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C0] = {
+		/* Device does not talk I2C */
+		.drv = &aoz1380_drv
+	},
+
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_TCPC1,
+		.i2c_addr_flags = NX20P3483_ADDR1_FLAGS,
+		.drv = &nx20p348x_drv
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_FAULT_ODL:
+		aoz1380_interrupt(USBC_PORT_C0);
+		break;
+
+	case GPIO_USB_C1_PPC_INT_ODL:
+		/*
+		 * Sensitive only to falling edges; GPIO is configured for both
+		 * because this input may be used for HDMI HPD instead.
+		 */
+		if (!gpio_get_level(signal))
+			nx20p348x_interrupt(USBC_PORT_C1);
+		break;
+
+	default:
+		break;
+	}
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int i;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTSUSB("Disabling all charger ports");
+
+		/* Disable all ports. */
+		for (i = 0; i < ppc_cnt; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (ppc_vbus_sink_enable(i, 0))
+				CPRINTSUSB("Disabling C%d as sink failed.", i);
+		}
+
+		return EC_SUCCESS;
+	} else if (!is_valid_port) {
+		return EC_ERROR_INVAL;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (ppc_is_sourcing_vbus(port)) {
+		CPRINTFUSB("Skip enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTSUSB("New charge port: C%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < ppc_cnt; i++) {
+		if (i == port)
+			continue;
+
+		if (ppc_vbus_sink_enable(i, 0))
+			CPRINTSUSB("C%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTSUSB("C%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+void board_overcurrent_event(int port, int is_overcurrented)
+{
+	switch (port) {
+	case USBC_PORT_C0:
+		ioex_set_level(IOEX_USB_C0_FAULT_ODL, !is_overcurrented);
+		break;
+
+	case USBC_PORT_C1:
+		ioex_set_level(IOEX_USB_C1_FAULT_ODL, !is_overcurrented);
+		break;
+
+	default:
+		break;
+	}
+}
+
+const struct tcpc_config_t tcpc_config[] = {
+	[USBC_PORT_C0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TCPC0,
+			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+	},
+	[USBC_PORT_C1] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TCPC1,
+			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
+BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
+
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_TCPC0,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_TCPC1,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
+
+static void reset_nct38xx_port(int port)
+{
+	enum gpio_signal reset_gpio_l;
+
+	if (port == USBC_PORT_C0)
+		reset_gpio_l = GPIO_USB_C0_TCPC_RST_L;
+	else if (port == USBC_PORT_C1)
+		reset_gpio_l = GPIO_USB_C1_TCPC_RST_L;
+	else
+		/* Invalid port: do nothing */
+		return;
+
+	gpio_set_level(reset_gpio_l, 0);
+	msleep(NCT38XX_RESET_HOLD_DELAY_MS);
+	gpio_set_level(reset_gpio_l, 1);
+	nct38xx_reset_notify(port);
+	if (NCT3807_RESET_POST_DELAY_MS != 0)
+		msleep(NCT3807_RESET_POST_DELAY_MS);
+}
+
+void board_reset_pd_mcu(void)
+{
+	/* Reset TCPC0 */
+	reset_nct38xx_port(USBC_PORT_C0);
+
+	/* Reset TCPC1 */
+	reset_nct38xx_port(USBC_PORT_C1);
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	/*
+	 * Check which port has the ALERT line set and ignore if that TCPC has
+	 * its reset line active.
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL)) {
+		if (gpio_get_level(GPIO_USB_C0_TCPC_RST_L) != 0)
+			status |= PD_STATUS_TCPC_ALERT_0;
+	}
+
+	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL)) {
+		if (gpio_get_level(GPIO_USB_C1_TCPC_RST_L) != 0)
+			status |= PD_STATUS_TCPC_ALERT_1;
+	}
+
+	return status;
+}
+
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	int port = -1;
+
+	switch (signal) {
+	case GPIO_USB_C0_TCPC_INT_ODL:
+		port = 0;
+		break;
+	case GPIO_USB_C1_TCPC_INT_ODL:
+		port = 1;
+		break;
+	default:
+		return;
+	}
+
+	schedule_deferred_pd_interrupt(port);
+}
+
+void bc12_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_BC12_INT_ODL:
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+		break;
+
+	case GPIO_USB_C1_BC12_INT_ODL:
+		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+		break;
+
+	default:
+		break;
+	}
+}
+
+int board_pd_set_frs_enable(int port, int enable)
+{
+	int rv = EC_SUCCESS;
+
+	/* Use the TCPC to enable fast switch when FRS included */
+	if (port == USBC_PORT_C0) {
+		rv = ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN, !!enable);
+	} else {
+		rv = ioex_set_level(IOEX_USB_C1_TCPC_FASTSW_CTL_EN, !!enable);
+	}
+
+	return rv;
+}
+
+static void setup_fw_config(void)
+{
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_PPC_FAULT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
+
+	/* Enable BC 1.2 interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
+
+	/* Enable SBU fault interrupts */
+	ioex_enable_interrupt(IOEX_USB_C0_SBU_FAULT_ODL);
+	ioex_enable_interrupt(IOEX_USB_C1_SBU_FAULT_DB_ODL);
+
+	if (ec_config_has_lid_angle_tablet_mode()) {
+		/* Enable Gyro interrupts */
+		gpio_enable_interrupt(GPIO_6AXIS_INT_L);
+	} else {
+		motion_sensor_count = 0;
+		/* Device is clamshell only */
+		tablet_set_mode(0, TABLET_TRIGGER_LID);
+		/* Gyro is not present, don't allow line to float */
+		gpio_set_flags(GPIO_6AXIS_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, setup_fw_config, HOOK_PRIO_INIT_I2C + 2);
+
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_KBLIGHT] = {
+		.channel = 3,
+		.flags = PWM_CONFIG_DSLEEP,
+		.freq = 100,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+struct ioexpander_config_t ioex_config[] = {
+	[IOEX_C0_NCT3807] = {
+		.i2c_host_port = I2C_PORT_TCPC0,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+	},
+	[IOEX_C1_NCT3807] = {
+		.i2c_host_port = I2C_PORT_TCPC1,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT);
+
+int usb_port_enable[USBA_PORT_COUNT] = {
+	IOEX_EN_USB_A0_5V,
+	IOEX_EN_USB_A1_5V_DB,
+};
+
+#ifdef CONFIG_KEYBOARD_FACTORY_TEST
+/*
+ * Map keyboard connector pins to EC GPIO pins for factory test.
+ * Pins mapped to {-1, -1} are skipped.
+ * The connector has 24 pins total, and there is no pin 0.
+ */
+const int keyboard_factory_scan_pins[][2] = {
+	{ 0, 5 }, { 1, 1 }, { 1, 0 }, { 0, 6 },	  { 0, 7 },   { 1, 4 },
+	{ 1, 3 }, { 1, 6 }, { 1, 7 }, { 3, 1 },	  { 2, 0 },   { 1, 5 },
+	{ 2, 6 }, { 2, 7 }, { 2, 1 }, { 2, 4 },	  { 2, 5 },   { 1, 2 },
+	{ 2, 3 }, { 2, 2 }, { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 },
+};
+const int keyboard_factory_scan_pins_used =
+	ARRAY_SIZE(keyboard_factory_scan_pins);
+#endif
+
+#define CHARGING_CURRENT_500MA 500
+
+int charger_profile_override(struct charge_state_data *curr)
+{
+	int rv;
+	static int thermal_sensor_temp;
+	static int prev_thermal_sensor_temp;
+	static int limit_charge;
+	static int limit_usbc_power;
+	static int limit_usbc_power_backup;
+	enum tcpc_rp_value rp;
+
+	rv = temp_sensor_read(TEMP_SENSOR_CHARGER, &thermal_sensor_temp);
+
+	if (rv != EC_SUCCESS)
+		return 0;
+
+	if (thermal_sensor_temp > prev_thermal_sensor_temp) {
+		if (thermal_sensor_temp > C_TO_K(63))
+			limit_usbc_power = 1;
+
+		else if (thermal_sensor_temp > C_TO_K(58)) {
+			if (curr->state == ST_CHARGE)
+				limit_charge = 1;
+		}
+	} else if (thermal_sensor_temp < prev_thermal_sensor_temp) {
+		if (thermal_sensor_temp < C_TO_K(57)) {
+			if (curr->state == ST_CHARGE)
+				limit_charge = 0;
+
+		} else if (thermal_sensor_temp < C_TO_K(62))
+			limit_usbc_power = 0;
+	}
+
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return 0;
+
+	curr->requested_current = (limit_charge) ? CHARGING_CURRENT_500MA :
+						   curr->batt.desired_current;
+
+	if (limit_usbc_power != limit_usbc_power_backup) {
+		rp = (limit_usbc_power) ? TYPEC_RP_1A5 : TYPEC_RP_3A0;
+
+		ppc_set_vbus_source_current_limit(0, rp);
+		tcpm_select_rp_value(0, rp);
+		pd_update_contract(0);
+		limit_usbc_power_backup = limit_usbc_power;
+	}
+
+	prev_thermal_sensor_temp = thermal_sensor_temp;
+
+	return 0;
+}
+
+enum ec_status charger_profile_override_get_param(uint32_t param,
+						  uint32_t *value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+enum ec_status charger_profile_override_set_param(uint32_t param,
+						  uint32_t value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+__override struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT] = {
+	[TEMP_SENSOR_CHARGER] = {
+		.temp_host = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(63),
+			[EC_TEMP_THRESH_HALT] = C_TO_K(92),
+		},
+		.temp_host_release = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(62),
+		}
+	},
+	[TEMP_SENSOR_SOC] = {
+		.temp_host = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
+			[EC_TEMP_THRESH_HALT] = C_TO_K(85),
+		},
+		.temp_host_release = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(77),
+		}
+	},
+	[TEMP_SENSOR_CPU] = {
+		.temp_host = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(85),
+			[EC_TEMP_THRESH_HALT] = C_TO_K(90),
+		},
+		.temp_host_release = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(83),
+		}
+	},
+};
diff --git a/board/gumboz/board.h b/board/gumboz/board.h
new file mode 100644
index 0000000000..abf8280f74
--- /dev/null
+++ b/board/gumboz/board.h
@@ -0,0 +1,161 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Trembyle board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#define VARIANT_ZORK_DALBOZ
+
+#include "baseboard.h"
+
+#include <stdbool.h>
+
+#define CONFIG_USBC_PPC_NX20P3483
+#define CONFIG_USB_MUX_PS8743
+#define CONFIG_USB_MUX_RUNTIME_CONFIG
+
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#define CONFIG_USB_PORT_ENABLE_DYNAMIC
+
+#undef CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
+#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 40000
+
+#define CONFIG_CHARGER_PROFILE_OVERRIDE
+
+#define CONFIG_KEYBOARD_FACTORY_TEST
+
+/* USB-A config */
+#define GPIO_USB1_ILIM_SEL IOEX_USB_A0_CHARGE_EN_L
+#define GPIO_USB2_ILIM_SEL IOEX_USB_A1_CHARGE_EN_DB_L
+
+/* LED */
+#undef CONFIG_LED_ONOFF_STATES
+
+/* Motion sensing drivers */
+#define CONFIG_ACCELGYRO_LSM6DSM
+#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+#define CONFIG_ACCEL_KX022 /* Lid accel */
+#define CONFIG_CMD_ACCELS
+#define CONFIG_CMD_ACCEL_INFO
+#define CONFIG_TABLET_MODE
+#define CONFIG_GMR_TABLET_MODE
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_UPDATE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+
+/* GPIO mapping from board specific name to EC common name. */
+#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL
+#define CONFIG_SCI_GPIO GPIO_EC_FCH_SCI_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_AP_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_EDP_BL_DISABLE
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PCH_PWRBTN_L GPIO_EC_FCH_PWR_BTN_L
+#define GPIO_PCH_RSMRST_L GPIO_EC_FCH_RSMRST_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L
+#define GPIO_PCH_SYS_PWROK GPIO_EC_FCH_PWROK
+#define GPIO_PCH_WAKE_L GPIO_EC_FCH_WAKE_L
+#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL
+#define GPIO_S0_PGOOD GPIO_S0_PWROK_OD
+#define GPIO_S5_PGOOD GPIO_EC_PWROK_OD
+#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L
+#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
+
+#ifndef __ASSEMBLER__
+
+/* This I2C moved. Temporarily detect and support the V0 HW. */
+extern int I2C_PORT_BATTERY;
+
+enum adc_channel { ADC_TEMP_SENSOR_CHARGER, ADC_TEMP_SENSOR_SOC, ADC_CH_COUNT };
+
+enum battery_type {
+	BATTERY_SIMPLO_COS,
+	BATTERY_SIMPLO_HIGHPOWER,
+	BATTERY_SAMSUNG_SDI,
+	BATTERY_DYNAPACK_ATL,
+	BATTERY_DYNAPACK_COS,
+	BATTERY_COSMX,
+	BATTERY_TYPE_COUNT,
+};
+
+enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_COUNT };
+
+enum ioex_port { IOEX_C0_NCT3807 = 0, IOEX_C1_NCT3807, IOEX_PORT_COUNT };
+
+#define PORT_TO_HPD(port) ((port == 0) ? GPIO_USB3_C0_DP2_HPD : GPIO_DP1_HPD)
+
+enum temp_sensor_id {
+	TEMP_SENSOR_CHARGER = 0,
+	TEMP_SENSOR_SOC,
+	TEMP_SENSOR_CPU,
+	TEMP_SENSOR_COUNT
+};
+
+enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT };
+
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
+
+/*****************************************************************************
+ * CBI EC FW Configuration
+ */
+
+/**
+ * DALBOZ_MB_USBAC
+ *	USB-A0  Speed: 5 Gbps
+ *		Retimer: none
+ *	USB-C0  Speed: 5 Gbps
+ *		Retimer: none
+ *		TCPC: NCT3807
+ *		PPC: AOZ1380
+ *		IOEX: TCPC
+ */
+enum ec_cfg_usb_mb_type {
+	DALBOZ_MB_USBAC = 0,
+};
+
+/**
+ * GUMBOZ_DB_OPT1_USBC
+ *	USB-A1  Speed: 5 Gbps
+ *		Retimer: PS8719
+ *	USB-C1  Speed: 5 Gbps
+ *		Retimer: PS8743
+ *		TCPC: NCT3807
+ *		PPC: NX20P3483
+ *		IOEX: TCPC
+ *	HDMI    Exists: no
+ *		Retimer: none
+ *		MST Hub: none
+ */
+enum ec_cfg_usb_db_type {
+	GUMBOZ_DB_OPT1_USBC = 0,
+};
+
+#include "cbi_ec_fw_config.h"
+
+static inline bool ec_config_has_hdmi_retimer_pi3hdx1204(void)
+{
+	return 0;
+}
+
+void board_reset_pd_mcu(void);
+
+/* Common definition for the USB PD interrupt handlers. */
+void tcpc_alert_event(enum gpio_signal signal);
+void bc12_interrupt(enum gpio_signal signal);
+void ppc_interrupt(enum gpio_signal signal);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/gumboz/build.mk b/board/gumboz/build.mk
new file mode 100644
index 0000000000..45c71f962c
--- /dev/null
+++ b/board/gumboz/build.mk
@@ -0,0 +1,15 @@
+# -*- makefile -*-
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx7
+CHIP_VARIANT:=npcx7m7wc
+BASEBOARD:=zork
+
+board-y=board.o led.o
+board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/gumboz/ec.tasklist b/board/gumboz/ec.tasklist
new file mode 100644
index 0000000000..abc796f74f
--- /dev/null
+++ b/board/gumboz/ec.tasklist
@@ -0,0 +1,26 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/gumboz/gpio.inc b/board/gumboz/gpio.inc
new file mode 100644
index 0000000000..2e7e4b78a9
--- /dev/null
+++ b/board/gumboz/gpio.inc
@@ -0,0 +1,138 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(3, 4), GPIO_INT_FALLING,			tcpc_alert_event)
+GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(F, 1), GPIO_INT_FALLING,			tcpc_alert_event)
+GPIO_INT(USB_C0_PPC_FAULT_ODL,	PIN(6, 3), GPIO_INT_FALLING,			ppc_interrupt)
+GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(D, 4), GPIO_INT_BOTH | GPIO_PULL_UP,	ppc_interrupt)
+GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(9, 3), GPIO_INT_FALLING | GPIO_PULL_UP,	bc12_interrupt)
+GPIO_INT(USB_C1_BC12_INT_ODL, 	PIN(A, 4), GPIO_INT_FALLING | GPIO_PULL_UP,	bc12_interrupt)
+GPIO_INT(SLP_S3_L,		PIN(7, 4), GPIO_INT_BOTH,			power_signal_interrupt)
+GPIO_INT(SLP_S5_L,		PIN(E, 0), GPIO_INT_BOTH,			power_signal_interrupt)
+GPIO_INT(S0_PWROK_OD,		PIN(5, 6), GPIO_INT_BOTH,			power_signal_interrupt)
+GPIO_INT(EC_PWROK_OD,		PIN(3, 7), GPIO_INT_BOTH,			power_signal_interrupt)
+GPIO_INT(EC_PWR_BTN_ODL,	PIN(0, 1), GPIO_INT_BOTH,			power_button_interrupt)
+GPIO_INT(LID_OPEN,		PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	lid_interrupt)
+GPIO_INT(TABLET_MODE_L,		PIN(4, 4), GPIO_INT_BOTH,			gmr_tablet_switch_isr)
+GPIO_INT(ACOK_OD,		PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	extpower_interrupt)
+GPIO_INT(EC_WP_L,		PIN(5, 0), GPIO_INT_BOTH,			switch_interrupt)
+GPIO_INT(VOLDN_BTN_ODL,		PIN(A, 6), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
+GPIO_INT(VOLUP_BTN_ODL,		PIN(9, 5), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
+GPIO_INT(6AXIS_INT_L,		PIN(A, 0), GPIO_INT_FALLING | GPIO_PULL_UP,	lsm6dsm_interrupt)
+
+/* GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an interrupt handler. */
+GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH)
+
+GPIO(3AXIS_INT_L,		PIN(9, 6), GPIO_INPUT | GPIO_PULL_DOWN)		/* 3 Axis Accel */
+GPIO(CCD_MODE_ODL,		PIN(C, 6), GPIO_INPUT)				/* Case Closed Debug Mode */
+GPIO(PROCHOT_ODL,		PIN(D, 5), GPIO_ODR_HIGH)			/* PROCHOT to SOC */
+GPIO(EC_BATT_PRES_ODL,		PIN(4, 1), GPIO_INPUT)				/* Battery Present */
+GPIO(EC_AP_INT_ODL,		PIN(A, 3), GPIO_ODR_HIGH)			/* Sensor MKBP event to SOC */
+GPIO(EN_PWR_A,			PIN(B, 7), GPIO_OUT_LOW)			/* Enable Power */
+GPIO(EC_EDP_BL_DISABLE,		PIN(A, 2), GPIO_OUT_HIGH)			/* Enable Backlight */
+GPIO(EC_ENTERING_RW,		PIN(E, 5), GPIO_OUT_LOW)			/* EC Entering RW */
+GPIO(EC_FCH_PWR_BTN_L,		PIN(6, 7), GPIO_OUT_HIGH)			/* Power Button to SOC */
+GPIO(EC_FCH_RSMRST_L,		PIN(A, 1), GPIO_OUT_LOW)			/* RSMRST# to SOC */
+GPIO(EC_FCH_PWROK,		PIN(7, 0), GPIO_OUT_LOW)			/* Power OK to SOC */
+GPIO(EC_FCH_WAKE_L,		PIN(0, 3), GPIO_OUT_HIGH)			/* Wake SOC */
+GPIO(EC_FCH_SCI_ODL,		PIN(7, 6), GPIO_ODR_HIGH)			/* SCI to SOC */
+GPIO(EC_SYS_RST_L,		PIN(C, 7), GPIO_ODR_HIGH)			/* Cold Reset to SOC */
+GPIO(USB_C0_TCPC_RST_L,		PIN(E, 1), GPIO_OUT_HIGH)			/* C0 TCPC Reset */
+GPIO(USB_C1_TCPC_RST_L,		PIN(F, 0), GPIO_OUT_HIGH)			/* C1 TCPC Reset */
+GPIO(USB3_C0_DP2_HPD,		PIN(F, 5), GPIO_OUT_LOW)			/* C0 DP Hotplug Detect */
+GPIO(DP1_HPD,			PIN(F, 4), GPIO_OUT_LOW)			/* C1 DP Hotplug Detect */
+GPIO(EC_H1_PACKET_MODE,		PIN(8, 6), GPIO_OUT_LOW)			/* H1 Packet Mode */
+
+UNIMPLEMENTED(PCH_SMI_L)
+
+GPIO(LED_FULL_L,		PIN(6, 0), GPIO_OUT_HIGH)
+GPIO(LED_CHRG_L,		PIN(C, 0), GPIO_OUT_HIGH)
+GPIO(PWR_LED_WHITE_L,		PIN(C, 3), GPIO_OUT_HIGH)
+
+/*
+ * Gumboz has 1 DB options.
+ * IOEX_C1_NCT3807 is the DB (USB-C1).
+ */
+
+IOEX_INT(USB_C0_SBU_FAULT_ODL,	EXPIN(IOEX_C0_NCT3807, 1, 2), GPIO_INT_FALLING, sbu_fault_interrupt)
+IOEX_INT(USB_C1_SBU_FAULT_DB_ODL, EXPIN(IOEX_C1_NCT3807, 1, 2), GPIO_INT_FALLING, sbu_fault_interrupt)
+
+IOEX(USB_C0_FAULT_ODL,		EXPIN(IOEX_C0_NCT3807, 0, 3), GPIO_ODR_HIGH)	/* C0 Fault to SOC */
+IOEX(USB_C0_TCPC_FASTSW_CTL_EN,	EXPIN(IOEX_C0_NCT3807, 0, 4), GPIO_OUT_LOW)	/* C0 FastSwitch Control */
+IOEX(USB_C1_FAULT_ODL,		EXPIN(IOEX_C0_NCT3807, 1, 0), GPIO_ODR_HIGH)	/* C1 Fault to SOC */
+IOEX(USB_C0_PPC_ILIM_3A_EN,	EXPIN(IOEX_C0_NCT3807, 1, 1), GPIO_OUT_LOW)	/* C0 3A Current Limit Enable */
+IOEX(KB_BL_EN,			EXPIN(IOEX_C0_NCT3807, 1, 3), GPIO_OUT_LOW)	/* KB Backlight Enable */
+IOEX(EN_USB_A0_5V,		EXPIN(IOEX_C0_NCT3807, 1, 5), GPIO_OUT_LOW)	/* A0 5V Source Enable */
+IOEX(USB_A0_CHARGE_EN_L,	EXPIN(IOEX_C0_NCT3807, 1, 6), GPIO_OUT_HIGH)	/* A0 5V High Current Enable */
+IOEX(USB_C0_SBU_FLIP,		EXPIN(IOEX_C0_NCT3807, 1, 7), GPIO_OUT_LOW)	/* C0 SBU Flip */
+
+IOEX(USB_A1_RETIMER_EN,	EXPIN(IOEX_C1_NCT3807, 0, 0), GPIO_OUT_LOW)	/* A1 Retimer Enable */
+IOEX(USB_C1_HPD_IN_DB,		EXPIN(IOEX_C1_NCT3807, 0, 2), GPIO_OUT_LOW)	/* C1 HPD */
+IOEX(USB_C1_TCPC_FASTSW_CTL_EN,	EXPIN(IOEX_C1_NCT3807, 0, 4), GPIO_OUT_LOW)	/* C1 FastSwitch Control */
+IOEX(USB_C1_PPC_EN_L,		EXPIN(IOEX_C1_NCT3807, 1, 3), GPIO_OUT_LOW)	/* C1 PPC Enable */
+IOEX(USB_C1_DATA_EN,		EXPIN(IOEX_C1_NCT3807, 1, 5), GPIO_OUT_HIGH)	/* C1 Retimer Enable */
+IOEX(EN_USB_A1_5V_DB,	EXPIN(IOEX_C1_NCT3807, 1, 6), GPIO_OUT_LOW)	/* A1 5V Source Enable */
+IOEX(USB_A1_CHARGE_EN_DB_L,EXPIN(IOEX_C1_NCT3807, 1, 7), GPIO_OUT_HIGH)	/* A1 5V High Current Enable */
+IOEX(C1_CHARGER_LED_WHITE_DB,EXPIN(IOEX_C1_NCT3807, 1, 0), GPIO_OUT_HIGH)	/* C1 Charge LED White */
+IOEX(C1_CHARGER_LED_AMBER_DB,EXPIN(IOEX_C1_NCT3807, 1, 4), GPIO_OUT_HIGH)	/* C1 Charge LED Amber */
+
+
+/*
+ * The NPCX LPC driver configures and controls SCI, so PCH_SCI_ODL [PIN(7, 6)]
+ * is not defined here as GPIO.
+ */
+
+/* I2C pins - these will be reconfigured for alternate function below */
+GPIO(EC_I2C_USB_A0_C0_SCL,	PIN(B, 5), GPIO_INPUT)
+GPIO(EC_I2C_USB_A0_C0_SDA,	PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_A1_C1_SCL,	PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_A1_C1_SDA,	PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_POWER_SCL,		PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_POWER_SDA,		PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_USBC_AP_MUX_SCL,	PIN(D, 1), GPIO_INPUT)
+GPIO(EC_I2C_USBC_AP_MUX_SDA,	PIN(D, 0), GPIO_INPUT)
+GPIO(FCH_SIC,			PIN(F, 3), GPIO_INPUT)
+GPIO(FCH_SID,			PIN(F, 2), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_CBI_SCL,	PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_CBI_SDA,	PIN(3, 6), GPIO_INPUT)
+GPIO(I2C_AUDIO_USB_HUB_SCL,	PIN(E, 4), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(I2C_AUDIO_USB_HUB_SDA,	PIN(E, 3), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_BATT_SCL,		PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_BATT_SDA,		PIN(B, 2), GPIO_INPUT)
+
+ALTERNATE(PIN_MASK(6, BIT(4) | BIT(5)), 0, MODULE_UART, 0) /* Cr50 requires no pullups. */
+
+ALTERNATE(PIN_MASK(B, BIT(4) | BIT(5)), 0, MODULE_I2C, 0)			/* I2C0 */
+ALTERNATE(PIN_MASK(9, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_I2C, 0)		/* I2C1 SCL / I2C2 */
+ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)				/* I2C1 SDA */
+ALTERNATE(PIN_MASK(D, BIT(0) | BIT(1)), 0, MODULE_I2C, 0)			/* I2C3 */
+ALTERNATE(PIN_MASK(F, BIT(2) | BIT(3)), 0, MODULE_I2C, 0)			/* I2C4 */
+ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)			/* I2C5 */
+ALTERNATE(PIN_MASK(E, BIT(3) | BIT(4)), 0, MODULE_I2C, 0)			/* I2C6 */
+ALTERNATE(PIN_MASK(B, BIT(2) | BIT(3)), 0, MODULE_I2C, 0)			/* I2C7 */
+
+ALTERNATE(PIN_MASK(4, BIT(2) | BIT(3)), 0, MODULE_ADC, 0)			/* ADC2, ADC3 Temp Sensors */
+
+ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)				/* PWM3 KB Backlight */
+
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_00-01 */
+ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_02-07 */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_00-01 */
+GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW)					/* KSO_02 inverted */
+ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_03-09 */
+ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_10-12 */
+
+/* Power Switch Logic (PSL) inputs */
+ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)		/* AC_PRESENT, POWER_BUTTON_L, EC_RST_ODL */
+ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)				/* LID_OPEN */
+
+ALTERNATE(PIN_MASK(A, 0xA0), 1,  MODULE_WOV, 0) 				/* I2S_SYNC/I2S_SCLK  GPIOA5/A7 */
+ALTERNATE(PIN_MASK(B, 0x01), 1,  MODULE_WOV, 0) 				/* I2S_SDAT           GPIOB0    */
+ALTERNATE(PIN_MASK(9, 0x90), 1,  MODULE_WOV, 0) 				/* DMIC_CLK/DMIC_IN   GPIO94/97 */
diff --git a/board/gumboz/led.c b/board/gumboz/led.c
new file mode 100644
index 0000000000..9fa8c9bfb9
--- /dev/null
+++ b/board/gumboz/led.c
@@ -0,0 +1,234 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "chipset.h"
+#include "cros_board_info.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "led_common.h"
+
+#define BAT_LED_ON 0
+#define BAT_LED_OFF 1
+
+#define POWER_LED_ON 0
+#define POWER_LED_OFF 1
+
+#define LED_TICKS_PER_CYCLE 10
+#define LED_ON_TICKS 5
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_LEFT_LED,
+					     EC_LED_ID_RIGHT_LED,
+					     EC_LED_ID_POWER_LED };
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+enum led_color {
+	LED_OFF = 0,
+	LED_AMBER,
+	LED_WHITE,
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
+};
+
+enum led_port { LEFT_PORT = 0, RIGHT_PORT };
+
+static void led_set_color_battery(int port, enum led_color color)
+{
+	int amber_led, white_led;
+	uint32_t board_ver = 0;
+	int led_batt_on_lvl, led_batt_off_lvl;
+
+	cbi_get_board_version(&board_ver);
+	amber_led = (port == LEFT_PORT ? GPIO_LED_CHRG_L :
+					 IOEX_C1_CHARGER_LED_AMBER_DB);
+	white_led = (port == LEFT_PORT ? GPIO_LED_FULL_L :
+					 IOEX_C1_CHARGER_LED_WHITE_DB);
+
+	if ((board_ver >= 2) && (port == RIGHT_PORT)) {
+		led_batt_on_lvl = 1;
+		led_batt_off_lvl = 0;
+	} else {
+		led_batt_on_lvl = 0;
+		led_batt_off_lvl = 1;
+	}
+
+	switch (color) {
+	case LED_WHITE:
+		gpio_or_ioex_set_level(white_led, led_batt_on_lvl);
+		gpio_or_ioex_set_level(amber_led, led_batt_off_lvl);
+		break;
+	case LED_AMBER:
+		gpio_or_ioex_set_level(white_led, led_batt_off_lvl);
+		gpio_or_ioex_set_level(amber_led, led_batt_on_lvl);
+		break;
+	case LED_OFF:
+		gpio_or_ioex_set_level(white_led, led_batt_off_lvl);
+		gpio_or_ioex_set_level(amber_led, led_batt_off_lvl);
+		break;
+	default:
+		break;
+	}
+}
+
+void led_set_color_power(enum led_color color)
+{
+	switch (color) {
+	case LED_OFF:
+		gpio_set_level(GPIO_PWR_LED_WHITE_L, POWER_LED_OFF);
+		break;
+	case LED_WHITE:
+		gpio_set_level(GPIO_PWR_LED_WHITE_L, POWER_LED_ON);
+		break;
+	default:
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	switch (led_id) {
+	case EC_LED_ID_LEFT_LED:
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		break;
+	case EC_LED_ID_RIGHT_LED:
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		break;
+	case EC_LED_ID_POWER_LED:
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		break;
+	default:
+		break;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	switch (led_id) {
+	case EC_LED_ID_LEFT_LED:
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_battery(LEFT_PORT, LED_WHITE);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(LEFT_PORT, LED_AMBER);
+		else
+			led_set_color_battery(LEFT_PORT, LED_OFF);
+		break;
+	case EC_LED_ID_RIGHT_LED:
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_battery(RIGHT_PORT, LED_WHITE);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(RIGHT_PORT, LED_AMBER);
+		else
+			led_set_color_battery(RIGHT_PORT, LED_OFF);
+		break;
+	case EC_LED_ID_POWER_LED:
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_power(LED_WHITE);
+		else
+			led_set_color_power(LED_OFF);
+		break;
+	default:
+		return EC_ERROR_PARAM1;
+	}
+
+	return EC_SUCCESS;
+}
+
+/*
+ * Set active charge port color to the parameter, turn off all others.
+ * If no port is active (-1), turn off all LEDs.
+ */
+static void set_active_port_color(enum led_color color)
+{
+	int port = charge_manager_get_active_charge_port();
+
+	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
+		led_set_color_battery(RIGHT_PORT,
+				      (port == RIGHT_PORT) ? color : LED_OFF);
+	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
+		led_set_color_battery(LEFT_PORT,
+				      (port == LEFT_PORT) ? color : LED_OFF);
+}
+
+static void led_set_battery(void)
+{
+	static int battery_ticks;
+
+	battery_ticks++;
+
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
+		/* Always indicate when charging, even in suspend. */
+		set_active_port_color(LED_AMBER);
+		break;
+	case LED_PWRS_DISCHARGE:
+		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
+			if (charge_get_percent() < 10)
+				led_set_color_battery(
+					RIGHT_PORT,
+					(battery_ticks % LED_TICKS_PER_CYCLE <
+					 LED_ON_TICKS) ?
+						LED_WHITE :
+						LED_OFF);
+			else
+				led_set_color_battery(RIGHT_PORT, LED_OFF);
+		}
+
+		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
+			led_set_color_battery(LEFT_PORT, LED_OFF);
+		break;
+	case LED_PWRS_ERROR:
+		set_active_port_color((battery_ticks & 0x2) ? LED_WHITE :
+							      LED_OFF);
+		break;
+	case LED_PWRS_CHARGE_NEAR_FULL:
+		set_active_port_color(LED_WHITE);
+		break;
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		set_active_port_color(LED_WHITE);
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		set_active_port_color(
+			(battery_ticks % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
+				LED_AMBER :
+				LED_OFF);
+		break;
+	default:
+		/* Other states don't alter LED behavior */
+		break;
+	}
+}
+
+static void led_set_power(void)
+{
+	static int power_tick;
+
+	power_tick++;
+
+	if (chipset_in_state(CHIPSET_STATE_ON))
+		led_set_color_power(LED_WHITE);
+	else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
+		led_set_color_power(
+			(power_tick % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
+				LED_WHITE :
+				LED_OFF);
+	else
+		led_set_color_power(LED_OFF);
+}
+
+/* Called by hook task every TICK */
+static void led_tick(void)
+{
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		led_set_power();
+
+	led_set_battery();
+}
+DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
diff --git a/board/gumboz/vif_override.xml b/board/gumboz/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/gumboz/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/guybrush/battery.c b/board/guybrush/battery.c
new file mode 100644
index 0000000000..e7163c8a11
--- /dev/null
+++ b/board/guybrush/battery.c
@@ -0,0 +1,127 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+
+/*
+ * Battery info for all Guybrush battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	/* AEC 5477109 */
+	[BATTERY_AEC] = {
+		.fuel_gauge = {
+			.manuf_name = "AEC",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.sleep_mode = {
+				.sleep_supported = true,
+				.reg_addr = 0x00,
+				.reg_data = 0x0011,
+			},
+			.fet = {
+				.reg_addr = 0x0,
+				.reg_mask = 0x2000,
+				.disconnect_val = 0x2000,
+			}
+		},
+		.batt_info = {
+			.voltage_max          = 8700,	/* mV */
+			.voltage_normal       = 7600,
+			.voltage_min          = 6000,
+			.precharge_current    = 100,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c       = 0,
+			.charging_max_c       = 50,
+			.discharging_min_c    = -20,
+			.discharging_max_c    = 60,
+		},
+	},
+	/* AP18F4M / LIS4163ACPC */
+	[BATTERY_AP18F4M] = {
+		.fuel_gauge = {
+			.manuf_name = "Murata KT00404001",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.reg_addr = 0x0,
+				.reg_mask = 0x2000,
+				.disconnect_val = 0x2000,
+			}
+		},
+		.batt_info = {
+			.voltage_max          = 8700,	/* mV */
+			.voltage_normal       = 7600,
+			.voltage_min          = 5500,
+			.precharge_current    = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 50,
+			.charging_min_c       = 0,
+			.charging_max_c       = 60,
+			.discharging_min_c    = -20,
+			.discharging_max_c    = 75,
+		},
+	},
+	/* POW-TECH Battery Information */
+	[BATTERY_POWER_TECH] = {
+		.fuel_gauge = {
+			.manuf_name = "POW-TECH",
+			.ship_mode = {
+				.reg_addr = 0x0,
+				.reg_data = { 0x10, 0x10 },
+			},
+			.sleep_mode = {
+				.sleep_supported = true,
+				.reg_addr = 0x00,
+				.reg_data = 0x0011,
+			},
+			.fet = {
+				.reg_addr       = 0x00,
+				.reg_mask       = 0x2000,
+				.disconnect_val = 0x2000,
+			}
+		},
+		.batt_info = {
+			.voltage_max          = 8800,	/* mV */
+			.voltage_normal       = 7700,
+			.voltage_min          = 6000,
+			.precharge_current    = 88,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c       = 0,
+			.charging_max_c       = 45,
+			.discharging_min_c    = -20,
+			.discharging_max_c    = 60,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_AP18F4M;
diff --git a/board/guybrush/board.c b/board/guybrush/board.c
new file mode 100644
index 0000000000..cbe1049d98
--- /dev/null
+++ b/board/guybrush/board.c
@@ -0,0 +1,535 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Guybrush board-specific configuration */
+
+#include "adc.h"
+#include "base_fw_config.h"
+#include "board_fw_config.h"
+#include "builtin/assert.h"
+#include "button.h"
+#include "common.h"
+#include "cros_board_info.h"
+#include "driver/accel_bma422.h"
+#include "driver/accelgyro_bmi160.h"
+#include "driver/accelgyro_bmi323.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "driver/retimer/ps8811.h"
+#include "driver/retimer/ps8818_public.h"
+#include "driver/temp_sensor/sb_tsi.h"
+#include "driver/temp_sensor/tmp112.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "switch.h"
+#include "tablet_mode.h"
+#include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
+#include "temp_sensor/tmp112.h"
+#include "thermal.h"
+#include "usb_mux.h"
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* Motion sensor mutex */
+static struct mutex g_lid_mutex;
+static struct mutex g_base_mutex;
+
+/* Motion sensor private data */
+static struct bmi_drv_data_t g_bmi_data;
+static struct accelgyro_saved_data_t g_bma422_data;
+
+/* Matrix to rotate accelrator into standard reference frame */
+const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				       { 0, FLOAT_TO_FP(1), 0 },
+				       { 0, 0, FLOAT_TO_FP(-1) } };
+
+const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+				      { FLOAT_TO_FP(-1), 0, 0 },
+				      { 0, 0, FLOAT_TO_FP(-1) } };
+
+/*
+ * We have total 30 pins for keyboard connecter {-1, -1} mean
+ * the N/A pin that don't consider it and reserve index 0 area
+ * that we don't have pin 0.
+ */
+const int keyboard_factory_scan_pins[][2] = {
+	{ -1, -1 }, { 0, 5 },	{ 1, 1 }, { 1, 0 },   { 0, 6 },	  { 0, 7 },
+	{ -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 },   { -1, -1 }, { 1, 6 },
+	{ 1, 7 },   { 3, 1 },	{ 2, 0 }, { 1, 5 },   { 2, 6 },	  { 2, 7 },
+	{ 2, 1 },   { 2, 4 },	{ 2, 5 }, { 1, 2 },   { 2, 3 },	  { 2, 2 },
+	{ 3, 0 },   { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 },	  { -1, -1 },
+	{ -1, -1 },
+};
+const int keyboard_factory_scan_pins_used =
+	ARRAY_SIZE(keyboard_factory_scan_pins);
+
+struct motion_sensor_t motion_sensors[] = {
+	[LID_ACCEL] = {
+		.name = "Lid Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMA422,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &bma4_accel_drv,
+		.mutex = &g_lid_mutex,
+		.drv_data = &g_bma422_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMA4_I2C_ADDR_PRIMARY,
+		.rot_standard_ref = &lid_standard_ref,
+		.min_frequency = BMA4_ACCEL_MIN_FREQ,
+		.max_frequency = BMA4_ACCEL_MAX_FREQ,
+		.default_range = 2, /* g, enough for laptop. */
+		.config = {
+			/* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 12500 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+			/* Sensor on in S3 */
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 12500 | ROUND_UP_FLAG,
+				.ec_rate = 0,
+			},
+		},
+	},
+	[BASE_ACCEL] = {
+		.name = "Base Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMI323,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &bmi3xx_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = &g_bmi_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMI3_ADDR_I2C_PRIM,
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = BMI_ACCEL_MIN_FREQ,
+		.max_frequency = BMI_ACCEL_MAX_FREQ,
+		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
+		.config = {
+			/* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 12500 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+			/* Sensor on in S3 */
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 12500 | ROUND_UP_FLAG,
+				.ec_rate = 0,
+			},
+		},
+	},
+	[BASE_GYRO] = {
+		.name = "Base Gyro",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMI323,
+		.type = MOTIONSENSE_TYPE_GYRO,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &bmi3xx_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = &g_bmi_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMI3_ADDR_I2C_PRIM,
+		.default_range = 1000, /* dps */
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = BMI_GYRO_MIN_FREQ,
+		.max_frequency = BMI_GYRO_MAX_FREQ,
+	},
+};
+unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+struct motion_sensor_t bmi160_base_accel = {
+	.name = "Base Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_BMI160,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &bmi160_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_bmi_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+	.rot_standard_ref = &base_standard_ref,
+	.min_frequency = BMI_ACCEL_MIN_FREQ,
+	.max_frequency = BMI_ACCEL_MAX_FREQ,
+	.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+		/* Sensor on in S3 */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 0,
+		},
+	},
+};
+
+struct motion_sensor_t bmi160_base_gyro = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_BMI160,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &bmi160_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_bmi_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &base_standard_ref,
+	.min_frequency = BMI_GYRO_MIN_FREQ,
+	.max_frequency = BMI_GYRO_MAX_FREQ,
+};
+
+__override enum ec_error_list
+board_a1_ps8811_retimer_init(const struct usb_mux *me)
+{
+	/* Set channel A output swing */
+	RETURN_ERROR(ps8811_i2c_field_update(
+		me, PS8811_REG_PAGE1, PS8811_REG1_USB_CHAN_A_SWING,
+		PS8811_CHAN_A_SWING_MASK, 0x2 << PS8811_CHAN_A_SWING_SHIFT));
+
+	/* Set channel B output swing */
+	RETURN_ERROR(ps8811_i2c_field_update(
+		me, PS8811_REG_PAGE1, PS8811_REG1_USB_CHAN_B_SWING,
+		PS8811_CHAN_B_SWING_MASK, 0x2 << PS8811_CHAN_B_SWING_SHIFT));
+
+	/* Set channel B de-emphasis to -6dB and pre-shoot to 1.5 dB */
+	RETURN_ERROR(ps8811_i2c_field_update(
+		me, PS8811_REG_PAGE1, PS8811_REG1_USB_CHAN_B_DE_PS_LSB,
+		PS8811_CHAN_B_DE_PS_LSB_MASK, PS8811_CHAN_B_DE_6_PS_1_5_LSB));
+
+	RETURN_ERROR(ps8811_i2c_field_update(
+		me, PS8811_REG_PAGE1, PS8811_REG1_USB_CHAN_B_DE_PS_MSB,
+		PS8811_CHAN_B_DE_PS_MSB_MASK, PS8811_CHAN_B_DE_6_PS_1_5_MSB));
+
+	return EC_SUCCESS;
+}
+
+__override int board_c1_ps8818_mux_set(const struct usb_mux *me,
+				       mux_state_t mux_state)
+{
+	int rv = EC_SUCCESS;
+
+	/* USB specific config */
+	if (mux_state & USB_PD_MUX_USB_ENABLED) {
+		/* Boost the USB gain */
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_APTX1EQ_10G_LEVEL,
+					      PS8818_EQ_LEVEL_UP_MASK,
+					      PS8818_EQ_LEVEL_UP_19DB);
+		if (rv)
+			return rv;
+
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_APTX2EQ_10G_LEVEL,
+					      PS8818_EQ_LEVEL_UP_MASK,
+					      PS8818_EQ_LEVEL_UP_19DB);
+		if (rv)
+			return rv;
+
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_APTX1EQ_5G_LEVEL,
+					      PS8818_EQ_LEVEL_UP_MASK,
+					      PS8818_EQ_LEVEL_UP_19DB);
+		if (rv)
+			return rv;
+
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_APTX2EQ_5G_LEVEL,
+					      PS8818_EQ_LEVEL_UP_MASK,
+					      PS8818_EQ_LEVEL_UP_19DB);
+		if (rv)
+			return rv;
+
+		/* Set the RX input termination */
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_RX_PHY,
+					      PS8818_RX_INPUT_TERM_MASK,
+					      PS8818_RX_INPUT_TERM_112_OHM);
+		if (rv)
+			return rv;
+	}
+
+	/* DP specific config */
+	if (mux_state & USB_PD_MUX_DP_ENABLED) {
+		/* Boost the DP gain */
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_DPEQ_LEVEL,
+					      PS8818_DPEQ_LEVEL_UP_MASK,
+					      PS8818_DPEQ_LEVEL_UP_19DB);
+		if (rv)
+			return rv;
+
+		/* Enable HPD on the DB */
+		ioex_set_level(IOEX_USB_C1_IN_HPD, 1);
+	} else {
+		/* Disable HPD on the DB */
+		ioex_set_level(IOEX_USB_C1_IN_HPD, 0);
+	}
+
+	return rv;
+}
+
+/*
+ * ANX7491(A1) and ANX7451(C1) are on the same i2c bus. Both default
+ * to 0x29 for the USB i2c address. This moves ANX7451(C1) USB i2c
+ * address to 0x2A. ANX7491(A1) will stay at the default 0x29.
+ */
+uint16_t board_anx7451_get_usb_i2c_addr(const struct usb_mux *me)
+{
+	ASSERT(me->usb_port == USBC_PORT_C1);
+	return 0x2a;
+}
+
+/*
+ * Base Gyro Sensor dynamic configuration
+ */
+static int base_gyro_config;
+
+static void board_update_motion_sensor_config(void)
+{
+	if (board_is_convertible()) {
+		if (get_board_version() == 1) {
+			motion_sensors[BASE_ACCEL] = bmi160_base_accel;
+			motion_sensors[BASE_GYRO] = bmi160_base_gyro;
+			base_gyro_config = BASE_GYRO_BMI160;
+			ccprints("BASE GYRO is BMI160");
+		} else {
+			base_gyro_config = BASE_GYRO_BMI323;
+			ccprints("BASE GYRO is BMI323");
+		}
+
+		motion_sensor_count = ARRAY_SIZE(motion_sensors);
+		/* Enable Base Accel and Gyro interrupt */
+		gpio_enable_interrupt(GPIO_6AXIS_INT_L);
+	} else {
+		motion_sensor_count = 0;
+		gmr_tablet_switch_disable();
+		/* Base accel is not stuffed, don't allow line to float */
+		gpio_set_flags(GPIO_6AXIS_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
+	}
+}
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	switch (base_gyro_config) {
+	case BASE_GYRO_BMI160:
+		bmi160_interrupt(signal);
+		break;
+	case BASE_GYRO_BMI323:
+	default:
+		bmi3xx_interrupt(signal);
+		break;
+	}
+}
+
+static void board_init(void)
+{
+	board_update_motion_sensor_config();
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+static void board_chipset_startup(void)
+{
+	if (get_board_version() > 1)
+		tmp112_init();
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
+
+int board_get_soc_temp_k(int idx, int *temp_k)
+{
+	uint32_t board_version = get_board_version();
+
+	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	if (board_version == 1)
+		return get_temp_3v3_30k9_47k_4050b(ADC_TEMP_SENSOR_SOC, temp_k);
+
+	return tmp112_get_val_k(idx, temp_k);
+}
+
+int board_get_soc_temp_mk(int *temp_mk)
+{
+	uint32_t board_version = get_board_version();
+
+	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	if (board_version == 1)
+		return EC_ERROR_UNIMPLEMENTED;
+
+	return tmp112_get_val_mk(TMP112_SOC, temp_mk);
+}
+
+int board_get_ambient_temp_mk(int *temp_mk)
+{
+	uint32_t board_version = get_board_version();
+
+	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	if (board_version == 1)
+		return EC_ERROR_UNIMPLEMENTED;
+
+	return tmp112_get_val_mk(TMP112_AMB, temp_mk);
+}
+
+/* ADC Channels */
+const struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_SOC] = {
+		.name = "SOC",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_CHARGER] = {
+		.name = "CHARGER",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_MEMORY] = {
+		.name = "MEMORY",
+		.input_ch = NPCX_ADC_CH2,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_CORE_IMON1] = {
+		.name = "CORE_I",
+		.input_ch = NPCX_ADC_CH3,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_SOC_IMON2] = {
+		.name = "SOC_I",
+		.input_ch = NPCX_ADC_CH4,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* Temp Sensors */
+static int board_get_memory_temp(int, int *);
+
+const struct tmp112_sensor_t tmp112_sensors[] = {
+	{ I2C_PORT_SENSOR, TMP112_I2C_ADDR_FLAGS0 },
+	{ I2C_PORT_SENSOR, TMP112_I2C_ADDR_FLAGS1 },
+};
+BUILD_ASSERT(ARRAY_SIZE(tmp112_sensors) == TMP112_COUNT);
+
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_SOC] = {
+		.name = "SOC",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = board_get_soc_temp_k,
+		.idx = TMP112_SOC,
+	},
+	[TEMP_SENSOR_CHARGER] = {
+		.name = "Charger",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_CHARGER,
+	},
+	[TEMP_SENSOR_MEMORY] = {
+		.name = "Memory",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = board_get_memory_temp,
+		.idx = ADC_TEMP_SENSOR_MEMORY,
+	},
+	[TEMP_SENSOR_CPU] = {
+		.name = "CPU",
+		.type = TEMP_SENSOR_TYPE_CPU,
+		.read = sb_tsi_get_val,
+		.idx = 0,
+	},
+	[TEMP_SENSOR_AMBIENT] = {
+		.name = "Ambient",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = tmp112_get_val_k,
+		.idx = TMP112_AMB,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT] = {
+	[TEMP_SENSOR_SOC] = {
+		.temp_host = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(100),
+			[EC_TEMP_THRESH_HALT] = C_TO_K(105),
+		},
+		.temp_host_release = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
+		},
+		.temp_fan_off = C_TO_K(25),
+		.temp_fan_max = C_TO_K(70),
+	},
+	[TEMP_SENSOR_CHARGER] = {
+		.temp_host = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(100),
+			[EC_TEMP_THRESH_HALT] = C_TO_K(105),
+		},
+		.temp_host_release = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
+		},
+		.temp_fan_off = 0,
+		.temp_fan_max = 0,
+	},
+	[TEMP_SENSOR_MEMORY] = {
+		.temp_host = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(100),
+			[EC_TEMP_THRESH_HALT] = C_TO_K(105),
+		},
+		.temp_host_release = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
+		},
+		.temp_fan_off = 0,
+		.temp_fan_max = 0,
+	},
+	[TEMP_SENSOR_CPU] = {
+		.temp_host = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(100),
+			[EC_TEMP_THRESH_HALT] = C_TO_K(105),
+		},
+		.temp_host_release = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
+		},
+		/*
+		 * CPU temp sensor fan thresholds are high because they are a
+		 * backup for the SOC temp sensor fan thresholds.
+		 */
+		.temp_fan_off = C_TO_K(60),
+		.temp_fan_max = C_TO_K(90),
+	},
+	/*
+	 * Note: Leave ambient entries at 0, both as it does not represent a
+	 * hotspot and as not all boards have this sensor
+	 */
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
+
+static int board_get_memory_temp(int idx, int *temp_k)
+{
+	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
+		return EC_ERROR_NOT_POWERED;
+	return get_temp_3v3_30k9_47k_4050b(idx, temp_k);
+}
diff --git a/board/guybrush/board.h b/board/guybrush/board.h
new file mode 100644
index 0000000000..094b98f23e
--- /dev/null
+++ b/board/guybrush/board.h
@@ -0,0 +1,104 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Guybrush board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* Baseboard features */
+#include "baseboard.h"
+
+/* Motion sensing drivers */
+
+/* Keyboard features */
+#define CONFIG_KEYBOARD_FACTORY_TEST
+
+/* Sensors */
+#define CONFIG_ACCELGYRO_BMI160
+#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+#define CONFIG_ACCELGYRO_BMI3XX
+#define CONFIG_ACCELGYRO_BMI3XX_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+#define CONFIG_ACCEL_BMA4XX
+
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
+
+/* EC console commands */
+#define CONFIG_CMD_ACCELS
+#define CONFIG_CMD_ACCEL_INFO
+#define CONFIG_CMD_BUTTON
+
+/* USB Type C and USB PD defines */
+#define CONFIG_USB_MUX_ANX7451
+#define CONFIG_USBC_RETIMER_ANX7451
+
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_CURRENT_MA 5000
+#define PD_MAX_VOLTAGE_MV 20000
+/* Max Power = 100 W */
+#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
+
+/* USB Type A Features */
+
+/* BC 1.2 */
+
+/* Volume Button feature */
+
+/* Fan features */
+
+/* LED features */
+#define CONFIG_LED_COMMON
+#define CONFIG_LED_ONOFF_STATES
+
+/* Thermal Config */
+#define CONFIG_TEMP_SENSOR_TMP112
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+/* Motion sensor interrupt */
+void motion_interrupt(enum gpio_signal signal);
+
+/* Battery Types */
+enum battery_type {
+	BATTERY_AEC,
+	BATTERY_AP18F4M,
+	BATTERY_POWER_TECH,
+	BATTERY_TYPE_COUNT,
+};
+
+enum base_accelgyro_type {
+	BASE_GYRO_NONE = 0,
+	BASE_GYRO_BMI160 = 1,
+	BASE_GYRO_BMI323 = 2,
+};
+
+/* ADC Channels */
+enum adc_channel {
+	ADC_TEMP_SENSOR_SOC = 0,
+	ADC_TEMP_SENSOR_CHARGER,
+	ADC_TEMP_SENSOR_MEMORY,
+	ADC_CORE_IMON1,
+	ADC_SOC_IMON2,
+	ADC_CH_COUNT
+};
+
+/* Temp Sensors */
+enum temp_sensor_id {
+	TEMP_SENSOR_SOC = 0,
+	TEMP_SENSOR_CHARGER,
+	TEMP_SENSOR_MEMORY,
+	TEMP_SENSOR_CPU,
+	TEMP_SENSOR_AMBIENT,
+	TEMP_SENSOR_COUNT
+};
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/guybrush/board_fw_config.c b/board/guybrush/board_fw_config.c
new file mode 100644
index 0000000000..0484b82461
--- /dev/null
+++ b/board/guybrush/board_fw_config.c
@@ -0,0 +1,43 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "base_fw_config.h"
+#include "board_fw_config.h"
+
+bool board_is_convertible(void)
+{
+	return (get_fw_config_field(FW_CONFIG_FORM_FACTOR_OFFSET,
+				    FW_CONFIG_FORM_FACTOR_WIDTH) ==
+		FW_CONFIG_FORM_FACTOR_CONVERTIBLE);
+}
+
+bool board_has_kblight(void)
+{
+	return (get_fw_config_field(FW_CONFIG_KBLIGHT_OFFSET,
+				    FW_CONFIG_KBLIGHT_WIDTH) ==
+		FW_CONFIG_KBLIGHT_YES);
+}
+
+enum board_usb_c1_mux board_get_usb_c1_mux(void)
+{
+	int usb_db = get_fw_config_field(FW_CONFIG_USB_DB_OFFSET,
+					 FW_CONFIG_USB_DB_WIDTH);
+	if (usb_db == FW_CONFIG_USB_DB_A1_PS8811_C1_PS8818)
+		return USB_C1_MUX_PS8818;
+	if (usb_db == FW_CONFIG_USB_DB_A1_ANX7491_C1_ANX7451)
+		return USB_C1_MUX_ANX7451;
+	return USB_C1_MUX_UNKNOWN;
+};
+
+enum board_usb_a1_retimer board_get_usb_a1_retimer(void)
+{
+	int usb_db = get_fw_config_field(FW_CONFIG_USB_DB_OFFSET,
+					 FW_CONFIG_USB_DB_WIDTH);
+	if (usb_db == FW_CONFIG_USB_DB_A1_PS8811_C1_PS8818)
+		return USB_A1_RETIMER_PS8811;
+	if (usb_db == FW_CONFIG_USB_DB_A1_ANX7491_C1_ANX7451)
+		return USB_A1_RETIMER_ANX7491;
+	return USB_A1_RETIMER_UNKNOWN;
+};
diff --git a/board/guybrush/board_fw_config.h b/board/guybrush/board_fw_config.h
new file mode 100644
index 0000000000..4477aca6fd
--- /dev/null
+++ b/board/guybrush/board_fw_config.h
@@ -0,0 +1,37 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _GUYBRUSH_BOARD_FW_CONFIG__H_
+#define _GUYBRUSH_BOARD_FW_CONFIG__H_
+
+/****************************************************************************
+ * Guybrush CBI FW Configuration
+ */
+
+/*
+ * USB Daughter Board (2 bits)
+ */
+#define FW_CONFIG_USB_DB_OFFSET 0
+#define FW_CONFIG_USB_DB_WIDTH 2
+#define FW_CONFIG_USB_DB_A1_PS8811_C1_PS8818 0
+#define FW_CONFIG_USB_DB_A1_ANX7491_C1_ANX7451 1
+
+/*
+ * Form Factor (1 bits)
+ */
+#define FW_CONFIG_FORM_FACTOR_OFFSET 2
+#define FW_CONFIG_FORM_FACTOR_WIDTH 1
+#define FW_CONFIG_FORM_FACTOR_CLAMSHELL 0
+#define FW_CONFIG_FORM_FACTOR_CONVERTIBLE 1
+
+/*
+ * Keyboard Backlight (1 bit)
+ */
+#define FW_CONFIG_KBLIGHT_OFFSET 3
+#define FW_CONFIG_KBLIGHT_WIDTH 1
+#define FW_CONFIG_KBLIGHT_NO 0
+#define FW_CONFIG_KBLIGHT_YES 1
+
+#endif /* _GUYBRUSH_CBI_FW_CONFIG__H_ */
diff --git a/board/guybrush/build.mk b/board/guybrush/build.mk
new file mode 100644
index 0000000000..806e8988a2
--- /dev/null
+++ b/board/guybrush/build.mk
@@ -0,0 +1,12 @@
+# -*- makefile -*-
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+BASEBOARD:=guybrush
+
+board-y=board.o
+board-y+=board_fw_config.o led.o battery.o thermal.o
diff --git a/board/guybrush/ec.tasklist b/board/guybrush/ec.tasklist
new file mode 100644
index 0000000000..7a64850dfb
--- /dev/null
+++ b/board/guybrush/ec.tasklist
@@ -0,0 +1,26 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, VENTI_TASK_STACK_SIZE)
diff --git a/board/guybrush/gpio.inc b/board/guybrush/gpio.inc
new file mode 100644
index 0000000000..ffc567b261
--- /dev/null
+++ b/board/guybrush/gpio.inc
@@ -0,0 +1,28 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the board GPIOs that we care about. */
+
+#include "base_gpio.inc"
+
+GPIO_INT(6AXIS_INT_L,		PIN(A, 0), GPIO_INT_FALLING | GPIO_PULL_UP, motion_interrupt)		/* 6 Axis IMU */
+GPIO_INT(TABLET_MODE,		PIN(C, 1), GPIO_INT_BOTH, gmr_tablet_switch_isr)			/* 360 Tablet Mode */
+
+/* LED Signals */
+ALTERNATE(/*EC_PWM_LED_CHRG_L*/	PIN_MASK(C, BIT(4)), 0, 			MODULE_PWM, 0)		/* Charging LED */
+ALTERNATE(/*EC_PWM_LED_FULL_L*/	PIN_MASK(8, BIT(0)), 0, 			MODULE_PWM, 0)		/* Full LED */
+
+/* Test Points */
+GPIO(EC_GPIO56,			PIN(5, 6), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(EC_PS2_CLK,		PIN(6, 7), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(EC_PS2_DAT,		PIN(7, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(EC_PS2_RST,		PIN(6, 2), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(EC_GPIOB0,			PIN(B, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(EC_GPIO81,			PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(EC_FLPRG2,			PIN(8, 6), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(EC_PSL_GPO,		PIN(D, 7), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(EC_PWM7,			PIN(6, 0), GPIO_INPUT | GPIO_PULL_UP)
\ No newline at end of file
diff --git a/board/guybrush/led.c b/board/guybrush/led.c
new file mode 100644
index 0000000000..c61886de15
--- /dev/null
+++ b/board/guybrush/led.c
@@ -0,0 +1,99 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Guybrush specific PWM LED settings.
+ */
+
+#include "common.h"
+#include "gpio.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+#include "pwm.h"
+
+/* Note PWM LEDs are active low */
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
+
+#define CPRINTS(format, args...) cprints(CC_PWM, format, ##args)
+
+__override const int led_charge_lvl_1 = 5;
+
+__override const int led_charge_lvl_2 = 97;
+
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_WHITE,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC } },
+	};
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_BATTERY_LED,
+};
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_AMBER:
+		pwm_enable(PWM_CH_LED_CHRG, LED_ON_LVL);
+		pwm_enable(PWM_CH_LED_FULL, LED_OFF_LVL);
+		break;
+	case EC_LED_COLOR_WHITE:
+		pwm_enable(PWM_CH_LED_CHRG, LED_OFF_LVL);
+		pwm_enable(PWM_CH_LED_FULL, LED_ON_LVL);
+		break;
+	case LED_OFF:
+		pwm_enable(PWM_CH_LED_CHRG, LED_OFF_LVL);
+		pwm_enable(PWM_CH_LED_FULL, LED_OFF_LVL);
+		break;
+	default: /* Unsupported colors */
+		CPRINTS("Unsupported LED color: %d", color);
+		pwm_enable(PWM_CH_LED_CHRG, LED_OFF_LVL);
+		pwm_enable(PWM_CH_LED_FULL, LED_OFF_LVL);
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_battery(EC_LED_COLOR_WHITE);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(EC_LED_COLOR_AMBER);
+		else
+			led_set_color_battery(LED_OFF);
+	} else {
+		CPRINTS("Unsupported LED set: %d", led_id);
+		return EC_ERROR_INVAL;
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/board/guybrush/thermal.c b/board/guybrush/thermal.c
new file mode 100644
index 0000000000..5bb1295f84
--- /dev/null
+++ b/board/guybrush/thermal.c
@@ -0,0 +1,34 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Guybrush board-specific configuration */
+
+#include "console.h"
+#include "fan.h"
+#include "thermal.h"
+#include "util.h"
+
+/* Console output macros */
+#define CPUTS(outstr) cputs(CC_THERMAL, outstr)
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
+
+const struct fan_conf fan_conf_0 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
+	.pgood_gpio = GPIO_S0_PGOOD,
+	.enable_gpio = -1,
+};
+const struct fan_rpm fan_rpm_0 = {
+	.rpm_min = 1000,
+	.rpm_start = 1000,
+	.rpm_max = 6500,
+};
+const struct fan_t fans[] = {
+	[FAN_CH_0] = {
+		.conf = &fan_conf_0,
+		.rpm = &fan_rpm_0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
diff --git a/board/guybrush/vif_override.xml b/board/guybrush/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/guybrush/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/haboki/battery.c b/board/haboki/battery.c
new file mode 100644
index 0000000000..72ad9ad6cb
--- /dev/null
+++ b/board/haboki/battery.c
@@ -0,0 +1,349 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "charge_state.h"
+#include "common.h"
+
+/*
+ * Battery info for all haboki battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	/* DynaPack CosMX Battery Information */
+	[BATTERY_DYNAPACK_COS] = {
+		.fuel_gauge = {
+			.manuf_name = "333-2C-DA-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,	/* mV */
+			.voltage_normal = 7700,
+			.voltage_min = 6000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
+
+	/* DynaPack ATL Battery Information */
+	[BATTERY_DYNAPACK_ATL] = {
+		.fuel_gauge = {
+			.manuf_name = "333-27-DA-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,	/* mV */
+			.voltage_normal = 7700,
+			.voltage_min = 6000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
+
+	/* DynaPack HIGHPOWER Battery Information */
+	[BATTERY_DYNAPACK_HIGHPOWER] = {
+		.fuel_gauge = {
+			.manuf_name = "333-2D-0D-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,	/* mV */
+			.voltage_normal = 7700,
+			.voltage_min = 6000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
+
+	/* DynaPack BYD Battery Information */
+	[BATTERY_DYNAPACK_BYD] = {
+		.fuel_gauge = {
+			.manuf_name = "333-2E-0D-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,	/* mV */
+			.voltage_normal = 7700,
+			.voltage_min = 6000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
+
+	/* Samsung SDI Battery Information */
+	[BATTERY_SAMSUNG_SDI] = {
+		.fuel_gauge = {
+			.manuf_name = "333-54-DA-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,	/* mV */
+			.voltage_normal = 7700,
+			.voltage_min = 6000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
+
+	/* Simplo CosMX Battery Information */
+	[BATTERY_SIMPLO_COS] = {
+		.fuel_gauge = {
+			.manuf_name = "333-1C-DA-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,	/* mV */
+			.voltage_normal = 7700,
+			.voltage_min = 6000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
+
+	/* Simplo HIGHPOWER Battery Information */
+	[BATTERY_SIMPLO_HIGHPOWER] = {
+		.fuel_gauge = {
+			.manuf_name = "333-1D-DA-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,	/* mV */
+			.voltage_normal = 7700,
+			.voltage_min = 6000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
+
+	/* CosMX Battery Information */
+	[BATTERY_COS] = {
+		.fuel_gauge = {
+			.manuf_name = "333-AC-0D-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,	/* mV */
+			.voltage_normal = 7700,
+			.voltage_min = 6000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
+
+	/* CosMX B00C4473A9D0002 Battery Information */
+	[BATTERY_COS_2] = {
+		.fuel_gauge = {
+			.manuf_name = "333-AC-DA-A",
+			.ship_mode = {
+				.reg_addr = 0x0,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,		/* mV */
+			.voltage_normal = 7700,		/* mV */
+			.voltage_min = 6000,		/* mV */
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
+
+	/* ATL GB-S20-4473A9-01H&020H Battery Information
+	 * Gauge IC : RAJ240045
+	 */
+	[BATTERY_ATL] = {
+		.fuel_gauge = {
+			.manuf_name = "313-B7-0D-A",
+			.ship_mode = {
+				.reg_addr = 0x0,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 0,
+				.reg_addr = 0x43,
+				.reg_mask = 0x0003,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0002,
+				.cfet_off_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,		/* mV */
+			.voltage_normal = 7700,		/* mV */
+			.voltage_min = 6000,		/* mV */
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_DYNAPACK_COS;
diff --git a/board/haboki/board.c b/board/haboki/board.c
new file mode 100644
index 0000000000..74cf39483b
--- /dev/null
+++ b/board/haboki/board.c
@@ -0,0 +1,691 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Haboki board-specific configuration */
+
+#include "adc_chip.h"
+#include "button.h"
+#include "cbi_fw_config.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "cros_board_info.h"
+#include "driver/accel_bma2x2.h"
+#include "driver/accelgyro_lsm6dsm.h"
+#include "driver/bc12/pi3usb9201.h"
+#include "driver/charger/sm5803.h"
+#include "driver/tcpm/it83xx_pd.h"
+#include "driver/tcpm/ps8xxx.h"
+#include "driver/temp_sensor/thermistor.h"
+#include "driver/usb_mux/it5205.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "intc.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "switch.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "tcpm/tcpci.h"
+#include "temp_sensor.h"
+#include "uart.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+
+#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+
+#define INT_RECHECK_US 5000
+
+uint32_t board_version;
+
+/* GPIO to enable/disable the USB Type-A port. */
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_USB_A_5V,
+};
+
+__override void board_process_pd_alert(int port)
+{
+	/*
+	 * PD_INT task will process this alert, and that task is only needed on
+	 * C1.
+	 */
+	if (port != 1)
+		return;
+
+	if (gpio_get_level(GPIO_USB_C1_INT_ODL))
+		return;
+
+	sm5803_handle_interrupt(port);
+}
+
+/* C0 interrupt line shared by BC 1.2 and charger */
+static void check_c0_line(void);
+DECLARE_DEFERRED(check_c0_line);
+
+static void notify_c0_chips(void)
+{
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+	sm5803_interrupt(0);
+}
+
+static void check_c0_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		notify_c0_chips();
+		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+	}
+}
+
+static void usb_c0_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c0_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c0_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+}
+
+/* C1 interrupt line shared by BC 1.2, TCPC, and charger */
+static void check_c1_line(void);
+DECLARE_DEFERRED(check_c1_line);
+
+static void notify_c1_chips(void)
+{
+	schedule_deferred_pd_interrupt(1);
+	usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+}
+
+static void check_c1_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips.
+	 */
+	if (!gpio_get_level(GPIO_USB_C1_INT_ODL)) {
+		notify_c1_chips();
+		hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
+	}
+}
+
+static void usb_c1_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c1_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c1_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
+}
+
+static void button_sub_hdmi_hpd_interrupt(enum gpio_signal s)
+{
+	enum fw_config_db db = get_cbi_fw_config_db();
+	int hdmi_hpd = gpio_get_level(GPIO_VOLUP_BTN_ODL_HDMI_HPD);
+
+	if (db == DB_1A_HDMI || db == DB_LTE_HDMI || db == DB_1A_HDMI_LTE)
+		gpio_set_level(GPIO_EC_AP_USB_C1_HDMI_HPD, hdmi_hpd);
+	else
+		button_interrupt(s);
+}
+
+static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
+{
+	cprints(CC_USBPD, "C0: CC OVP, SBU OVP, or thermal event");
+	pd_handle_cc_overvoltage(0);
+}
+
+static void pen_detect_interrupt(enum gpio_signal s)
+{
+	int pen_detect = !gpio_get_level(GPIO_PEN_DET_ODL);
+
+	gpio_set_level(GPIO_EN_PP5000_PEN, pen_detect);
+}
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	[ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH0 },
+	[ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH2 },
+	[ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH3 },
+	[ADC_SUB_ANALOG] = { .name = "SUB_ANALOG",
+			     .factor_mul = ADC_MAX_MVOLT,
+			     .factor_div = ADC_READ_MAX + 1,
+			     .shift = 0,
+			     .channel = CHIP_ADC_CH13 },
+	[ADC_TEMP_SENSOR_3] = { .name = "TEMP_SENSOR3",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH15 },
+	[ADC_TEMP_SENSOR_4] = { .name = "TEMP_SENSOR4",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH16 },
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* BC 1.2 chips */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	{
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+		.flags = PI3USB9201_ALWAYS_POWERED,
+	},
+	{
+		.i2c_port = I2C_PORT_SUB_USB_C1,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+		.flags = PI3USB9201_ALWAYS_POWERED,
+	},
+};
+
+/* Charger chips */
+const struct charger_config_t chg_chips[] = {
+	[CHARGER_PRIMARY] = {
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = SM5803_ADDR_CHARGER_FLAGS,
+		.drv = &sm5803_drv,
+	},
+	[CHARGER_SECONDARY] = {
+		.i2c_port = I2C_PORT_SUB_USB_C1,
+		.i2c_addr_flags = SM5803_ADDR_CHARGER_FLAGS,
+		.drv = &sm5803_drv,
+	},
+};
+
+/* TCPCs */
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_EMBEDDED,
+		.drv = &it83xx_tcpm_drv,
+	},
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_SUB_USB_C1,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+	},
+};
+
+/* USB Muxes */
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+			},
+	},
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_SUB_USB_C1,
+				.i2c_addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
+	},
+};
+
+/* Sensor Mutexes */
+static struct mutex g_lid_mutex;
+static struct mutex g_base_mutex;
+
+/* Sensor Data */
+static struct accelgyro_saved_data_t g_bma253_data;
+static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
+
+/* Matrix to rotate accelrator into standard reference frame */
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, FLOAT_TO_FP(-1), 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
+
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
+
+/* Drivers */
+struct motion_sensor_t motion_sensors[] = {
+	[LID_ACCEL] = {
+		.name = "Lid Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMA255,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &bma2x2_accel_drv,
+		.mutex = &g_lid_mutex,
+		.drv_data = &g_bma253_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
+		.rot_standard_ref = &lid_standard_ref,
+		.default_range = 2,
+		.min_frequency = BMA255_ACCEL_MIN_FREQ,
+		.max_frequency = BMA255_ACCEL_MAX_FREQ,
+		.config = {
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+		},
+	},
+	[BASE_ACCEL] = {
+		.name = "Base Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LSM6DSM,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &lsm6dsm_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
+				MOTIONSENSE_TYPE_ACCEL),
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
+		.rot_standard_ref = &base_standard_ref,
+		.default_range = 4,  /* g */
+		.min_frequency = LSM6DSM_ODR_MIN_VAL,
+		.max_frequency = LSM6DSM_ODR_MAX_VAL,
+		.config = {
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 13000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+		},
+	},
+	[BASE_GYRO] = {
+		.name = "Base Gyro",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LSM6DSM,
+		.type = MOTIONSENSE_TYPE_GYRO,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &lsm6dsm_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
+				MOTIONSENSE_TYPE_GYRO),
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
+		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = LSM6DSM_ODR_MIN_VAL,
+		.max_frequency = LSM6DSM_ODR_MAX_VAL,
+	},
+};
+
+unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+void board_init(void)
+{
+	int on;
+	enum fw_config_db db = get_cbi_fw_config_db();
+
+	if (db == DB_1A_HDMI || db == DB_LTE_HDMI || db == DB_1A_HDMI_LTE) {
+		/* Select HDMI option */
+		gpio_set_level(GPIO_HDMI_SEL_L, 0);
+	} else {
+		/* Select AUX option */
+		gpio_set_level(GPIO_HDMI_SEL_L, 1);
+	}
+
+	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_INT_ODL);
+
+	/* Store board version for use in determining charge limits */
+	cbi_get_board_version(&board_version);
+
+	/*
+	 * If interrupt lines are already low, schedule them to be processed
+	 * after inits are completed.
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL))
+		hook_call_deferred(&check_c0_line_data, 0);
+	if (!gpio_get_level(GPIO_USB_C1_INT_ODL))
+		hook_call_deferred(&check_c1_line_data, 0);
+
+	gpio_enable_interrupt(GPIO_USB_C0_CCSBU_OVP_ODL);
+
+	if (get_cbi_fw_config_tablet_mode() == TABLET_MODE_PRESENT) {
+		motion_sensor_count = ARRAY_SIZE(motion_sensors);
+		/* Enable Base Accel interrupt */
+		gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
+	} else {
+		motion_sensor_count = 0;
+		gmr_tablet_switch_disable();
+		/* Base accel is not stuffed, don't allow line to float */
+		gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L,
+			       GPIO_INPUT | GPIO_PULL_DOWN);
+	}
+
+	gpio_enable_interrupt(GPIO_PEN_DET_ODL);
+
+	/* Make sure pen detection is triggered or not at sysjump */
+	if (!gpio_get_level(GPIO_PEN_DET_ODL))
+		gpio_set_level(GPIO_EN_PP5000_PEN, 1);
+
+	/* Charger on the MB will be outputting PROCHOT_ODL and OD CHG_DET */
+	sm5803_configure_gpio0(CHARGER_PRIMARY, GPIO0_MODE_PROCHOT, 1);
+	sm5803_configure_chg_det_od(CHARGER_PRIMARY, 1);
+
+	if (board_get_charger_chip_count() > 1) {
+		/* Charger on the sub-board will be a push-pull GPIO */
+		sm5803_configure_gpio0(CHARGER_SECONDARY, GPIO0_MODE_OUTPUT, 0);
+	}
+
+	/* Turn on 5V if the system is on, otherwise turn it off */
+	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
+			      CHIPSET_STATE_SOFT_OFF);
+	board_power_5v_enable(on);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+static void board_resume(void)
+{
+	sm5803_disable_low_power_mode(CHARGER_PRIMARY);
+	if (board_get_charger_chip_count() > 1)
+		sm5803_disable_low_power_mode(CHARGER_SECONDARY);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_resume, HOOK_PRIO_DEFAULT);
+
+static void board_suspend(void)
+{
+	sm5803_enable_low_power_mode(CHARGER_PRIMARY);
+	if (board_get_charger_chip_count() > 1)
+		sm5803_enable_low_power_mode(CHARGER_SECONDARY);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_suspend, HOOK_PRIO_DEFAULT);
+
+void board_hibernate(void)
+{
+	/*
+	 * Put all charger ICs present into low power mode before entering
+	 * z-state.
+	 */
+	sm5803_hibernate(CHARGER_PRIMARY);
+	if (board_get_charger_chip_count() > 1)
+		sm5803_hibernate(CHARGER_SECONDARY);
+}
+
+__override void board_ocpc_init(struct ocpc_data *ocpc)
+{
+	/* There's no provision to measure Isys */
+	ocpc->chg_flags[CHARGER_SECONDARY] |= OCPC_NO_ISYS_MEAS_CAP;
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * Nothing to do.  TCPC C0 is internal, TCPC C1 reset pin is not
+	 * connected to the EC.
+	 */
+}
+
+__override void board_power_5v_enable(int enable)
+{
+	/*
+	 * Motherboard has a GPIO to turn on the 5V regulator, but the sub-board
+	 * sets it through the charger GPIO.
+	 */
+	gpio_set_level(GPIO_EN_PP5000, !!enable);
+
+	if (board_get_charger_chip_count() > 1) {
+		if (sm5803_set_gpio0_level(1, !!enable))
+			CPRINTUSB("Failed to %sable sub rails!",
+				  enable ? "en" : "dis");
+	}
+}
+
+__override uint8_t board_get_usb_pd_port_count(void)
+{
+	enum fw_config_db db = get_cbi_fw_config_db();
+
+	if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI ||
+	    db == DB_1A_HDMI_LTE)
+		return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
+	else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A ||
+		 db == DB_1C_1A_LTE)
+		return CONFIG_USB_PD_PORT_MAX_COUNT;
+
+	ccprints("Unhandled DB configuration: %d", db);
+	return 0;
+}
+
+__override uint8_t board_get_charger_chip_count(void)
+{
+	enum fw_config_db db = get_cbi_fw_config_db();
+
+	if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI ||
+	    db == DB_1A_HDMI_LTE)
+		return CHARGER_NUM - 1;
+	else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A ||
+		 db == DB_1C_1A_LTE)
+		return CHARGER_NUM;
+
+	ccprints("Unhandled DB configuration: %d", db);
+	return 0;
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	/*
+	 * TCPC 0 is embedded in the EC and processes interrupts in the chip
+	 * code (it83xx/intc.c)
+	 */
+
+	uint16_t status = 0;
+	int regval;
+
+	/* Check whether TCPC 1 pulled the shared interrupt line */
+	if (!gpio_get_level(GPIO_USB_C1_INT_ODL)) {
+		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
+			if (regval)
+				status = PD_STATUS_TCPC_ALERT_1;
+		}
+	}
+
+	return status;
+}
+
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
+{
+	/* Limit C1 on board version 0 to 2.0 A */
+	if ((board_version == 0) && (port == 1))
+		charge_ma = MIN(charge_ma, 2000);
+	/*
+	 * TODO(b/151955431): Characterize the input current limit in case a
+	 * scaling needs to be applied here
+	 */
+	charge_set_input_current_limit(charge_ma, charge_mv);
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_valid_port = (port >= 0 && port < board_get_usb_pd_port_count());
+
+	if (!is_valid_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTUSB("Disabling all charge ports");
+
+		sm5803_vbus_sink_enable(CHARGER_PRIMARY, 0);
+
+		if (board_get_charger_chip_count() > 1)
+			sm5803_vbus_sink_enable(CHARGER_SECONDARY, 0);
+
+		return EC_SUCCESS;
+	}
+
+	CPRINTUSB("New chg p%d", port);
+
+	/*
+	 * Ensure other port is turned off, then enable new charge port
+	 */
+	if (port == 0) {
+		if (board_get_charger_chip_count() > 1)
+			sm5803_vbus_sink_enable(CHARGER_SECONDARY, 0);
+		sm5803_vbus_sink_enable(CHARGER_PRIMARY, 1);
+
+	} else {
+		sm5803_vbus_sink_enable(CHARGER_PRIMARY, 0);
+		sm5803_vbus_sink_enable(CHARGER_SECONDARY, 1);
+	}
+
+	return EC_SUCCESS;
+}
+
+/* Vconn control for integrated ITE TCPC */
+void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
+{
+	/* Vconn control is only for port 0 */
+	if (port)
+		return;
+
+	if (cc_pin == USBPD_CC_PIN_1)
+		gpio_set_level(GPIO_EN_USB_C0_CC1_VCONN, !!enabled);
+	else
+		gpio_set_level(GPIO_EN_USB_C0_CC2_VCONN, !!enabled);
+}
+
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	int current;
+
+	if (port < 0 || port > board_get_usb_pd_port_count())
+		return;
+
+	current = (rp == TYPEC_RP_3A0) ? 3000 : 1500;
+
+	charger_set_otg_current_voltage(port, current, 5000);
+}
+
+/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
+const struct pwm_t pwm_channels[] = { [PWM_CH_KBLIGHT] = {
+					      .channel = 0,
+					      .flags = PWM_CONFIG_DSLEEP,
+					      .freq_hz = 10000,
+				      } };
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+/* Thermistors */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "Charger",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
+	[TEMP_SENSOR_4] = { .name = "5V regular",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_4 },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/* This callback disables keyboard when convertibles are fully open */
+__override void lid_angle_peripheral_enable(int enable)
+{
+	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
+
+	/*
+	 * If the lid is in tablet position via other sensors,
+	 * ignore the lid angle, which might be faulty then
+	 * disable keyboard.
+	 */
+	if (tablet_get_mode())
+		enable = 0;
+
+	if (enable) {
+		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
+	} else {
+		/*
+		 * Ensure that the chipset is off before disabling the keyboard.
+		 * When the chipset is on, the EC keeps the keyboard enabled and
+		 * the AP decides whether to ignore input devices or not.
+		 */
+		if (!chipset_in_s0)
+			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
+	}
+}
+
+__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+				       int *ki_div, int *kd, int *kd_div)
+{
+	*kp = 3;
+	*kp_div = 20;
+
+	*ki = 3;
+	*ki_div = 125;
+
+	*kd = 4;
+	*kd_div = 40;
+}
+
+#ifdef CONFIG_KEYBOARD_FACTORY_TEST
+/*
+ * Map keyboard connector pins to EC GPIO pins for factory test.
+ * Pins mapped to {-1, -1} are skipped.
+ * The connector has 24 pins total, and there is no pin 0.
+ */
+const int keyboard_factory_scan_pins[][2] = {
+	{ -1, -1 },	   { GPIO_KSO_H, 4 }, { GPIO_KSO_H, 0 },
+	{ GPIO_KSO_H, 1 }, { GPIO_KSO_H, 3 }, { GPIO_KSO_H, 2 },
+	{ GPIO_KSO_L, 5 }, { GPIO_KSO_L, 6 }, { GPIO_KSO_L, 3 },
+	{ GPIO_KSO_L, 2 }, { GPIO_KSI, 0 },   { GPIO_KSO_L, 1 },
+	{ GPIO_KSO_L, 4 }, { GPIO_KSI, 3 },   { GPIO_KSI, 2 },
+	{ GPIO_KSO_L, 0 }, { GPIO_KSI, 5 },   { GPIO_KSI, 4 },
+	{ GPIO_KSO_L, 7 }, { GPIO_KSI, 6 },   { GPIO_KSI, 7 },
+	{ GPIO_KSI, 1 },   { -1, -1 },	      { -1, -1 },
+	{ -1, -1 },
+};
+
+const int keyboard_factory_scan_pins_used =
+	ARRAY_SIZE(keyboard_factory_scan_pins);
+#endif
diff --git a/board/haboki/board.h b/board/haboki/board.h
new file mode 100644
index 0000000000..0365d094ea
--- /dev/null
+++ b/board/haboki/board.h
@@ -0,0 +1,149 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Haboki board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* Select Baseboard features */
+#define VARIANT_KEEBY_EC_IT8320
+#include "baseboard.h"
+
+#undef GPIO_VOLUME_UP_L
+#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL_HDMI_HPD
+
+/* Battery */
+#define CONFIG_BATTERY_FUEL_GAUGE
+
+/* BC 1.2 */
+#define CONFIG_BC12_DETECT_PI3USB9201
+
+/* Charger */
+#define CONFIG_CHARGE_RAMP_HW
+#define CONFIG_CHARGER_SM5803 /* C0 and C1: Charger */
+#define PD_MAX_VOLTAGE_MV 15000
+#define CONFIG_USB_PD_VBUS_DETECT_CHARGER
+#define CONFIG_USB_PD_5V_CHARGER_CTRL
+#define CONFIG_CHARGER_OTG
+#undef CONFIG_CHARGER_SINGLE_CHIP
+#define CONFIG_OCPC
+#define CONFIG_OCPC_DEF_RBATT_MOHMS               \
+	21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr \
+	    */
+
+/* PWM */
+#define CONFIG_PWM
+
+/* Sensors */
+#define CONFIG_ACCEL_BMA255 /* Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
+/* Sensors without hardware FIFO are in forced mode */
+#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
+
+#define CONFIG_CMD_ACCELS
+#define CONFIG_CMD_ACCEL_INFO
+
+/* Enable sensor fifo, must also define the _SIZE and _THRES */
+#define CONFIG_ACCEL_FIFO
+/* Power of 2 - Too large of a fifo causes too much timestamp jitter */
+#define CONFIG_ACCEL_FIFO_SIZE 256
+#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
+
+#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
+
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_UPDATE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+
+#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+#define CONFIG_TABLET_MODE
+#define CONFIG_TABLET_MODE_SWITCH
+#define CONFIG_GMR_TABLET_MODE
+
+/* Keyboard */
+#define CONFIG_KEYBOARD_FACTORY_TEST
+#define CONFIG_PWM_KBLIGHT
+
+/* TCPC */
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0: ITE EC TCPC */
+#define CONFIG_USB_PD_TCPM_PS8705 /* C1: PS8705 TCPC*/
+#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1
+#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+#define CONFIG_USB_PD_TCPC_LOW_POWER
+
+/* Thermistors */
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_THERMISTOR
+#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
+
+/* USB Mux and Retimer */
+#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */
+
+/* USB Type A Features */
+#define USB_PORT_COUNT 1
+#define CONFIG_USB_PORT_POWER_DUMB
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum chg_id {
+	CHARGER_PRIMARY,
+	CHARGER_SECONDARY,
+	CHARGER_NUM,
+};
+
+enum pwm_channel {
+	PWM_CH_KBLIGHT,
+	PWM_CH_COUNT,
+};
+
+/* Motion sensors */
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
+
+/* ADC channels */
+enum adc_channel {
+	ADC_VSNS_PP3300_A, /* ADC0 */
+	ADC_TEMP_SENSOR_1, /* ADC2 */
+	ADC_TEMP_SENSOR_2, /* ADC3 */
+	ADC_SUB_ANALOG, /* ADC13 */
+	ADC_TEMP_SENSOR_3, /* ADC15 */
+	ADC_TEMP_SENSOR_4, /* ADC16 */
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1,
+	TEMP_SENSOR_2,
+	TEMP_SENSOR_3,
+	TEMP_SENSOR_4,
+	TEMP_SENSOR_COUNT
+};
+
+/* List of possible batteries */
+enum battery_type {
+	BATTERY_DYNAPACK_COS,
+	BATTERY_DYNAPACK_ATL,
+	BATTERY_DYNAPACK_HIGHPOWER,
+	BATTERY_DYNAPACK_BYD,
+	BATTERY_SAMSUNG_SDI,
+	BATTERY_SIMPLO_COS,
+	BATTERY_SIMPLO_HIGHPOWER,
+	BATTERY_COS,
+	BATTERY_COS_2,
+	BATTERY_ATL,
+	BATTERY_TYPE_COUNT,
+};
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/haboki/build.mk b/board/haboki/build.mk
new file mode 100644
index 0000000000..4362df50a4
--- /dev/null
+++ b/board/haboki/build.mk
@@ -0,0 +1,15 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=it83xx
+CHIP_FAMILY:=it8320
+CHIP_VARIANT:=it8320dx
+BASEBOARD:=keeby
+
+board-y=board.o cbi_ssfc.o led.o usb_pd_policy.o
+board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/haboki/cbi_ssfc.c b/board/haboki/cbi_ssfc.c
new file mode 100644
index 0000000000..81f3ee0dad
--- /dev/null
+++ b/board/haboki/cbi_ssfc.c
@@ -0,0 +1,36 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi_ssfc.h"
+#include "common.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "hooks.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+/* Cache SSFC on init since we don't expect it to change in runtime */
+static union dedede_cbi_ssfc cached_ssfc;
+BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
+
+static void cbi_ssfc_init(void)
+{
+	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
+		/* Default to 0 when CBI isn't populated */
+		cached_ssfc.raw_value = 0;
+
+	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
+}
+DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
+
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
+{
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
+}
+
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
+{
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
+}
diff --git a/board/haboki/cbi_ssfc.h b/board/haboki/cbi_ssfc.h
new file mode 100644
index 0000000000..bf8853a43a
--- /dev/null
+++ b/board/haboki/cbi_ssfc.h
@@ -0,0 +1,59 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _DEDEDE_CBI_SSFC__H_
+#define _DEDEDE_CBI_SSFC__H_
+
+#include "stdint.h"
+
+/****************************************************************************
+ * Dedede CBI Second Source Factory Cache
+ */
+
+/*
+ * Base Sensor (Bits 0-2)
+ */
+enum ec_ssfc_base_sensor {
+	SSFC_SENSOR_BASE_DEFAULT = 0,
+	SSFC_SENSOR_BMI160 = 1,
+	SSFC_SENSOR_ICM426XX = 2,
+	SSFC_SENSOR_LSM6DSM = 3,
+	SSFC_SENSOR_ICM42607 = 4
+};
+
+/*
+ * Lid Sensor (Bits 3-5)
+ */
+enum ec_ssfc_lid_sensor {
+	SSFC_SENSOR_LID_DEFAULT = 0,
+	SSFC_SENSOR_BMA255 = 1,
+	SSFC_SENSOR_KX022 = 2,
+	SSFC_SENSOR_LIS2DWL = 3
+};
+
+union dedede_cbi_ssfc {
+	struct {
+		uint32_t base_sensor : 3;
+		uint32_t lid_sensor : 3;
+		uint32_t reserved_2 : 26;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Get the Base sensor type from SSFC_CONFIG.
+ *
+ * @return the Base sensor board type.
+ */
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
+
+/**
+ * Get the Lid sensor type from SSFC_CONFIG.
+ *
+ * @return the Lid sensor board type.
+ */
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
+
+#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/haboki/ec.tasklist b/board/haboki/ec.tasklist
new file mode 100644
index 0000000000..c13df44543
--- /dev/null
+++ b/board/haboki/ec.tasklist
@@ -0,0 +1,24 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, TRENTA_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, ULTRA_TASK_STACK_SIZE) \
+        TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+        TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+        TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/haboki/gpio.inc b/board/haboki/gpio.inc
new file mode 100644
index 0000000000..8ecc458a19
--- /dev/null
+++ b/board/haboki/gpio.inc
@@ -0,0 +1,148 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+/* Power State interrupts */
+GPIO_INT(SLP_S4_L,		PIN(I, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,		PIN(H, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(SLP_S0_L,		PIN(E, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,		PIN(G, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID0,	PIN(D, 0), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(RSMRST_PWRGD_L,	PIN(E, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(CPU_C10_GATE_L,	PIN(G, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_DRAM_OD,		PIN(D, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(PG_PP1050_ST_OD,	PIN(L, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID1,	PIN(K, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_VCCIO_EXT_OD,	PIN(D, 7), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(ESPI_RESET_L, 	 PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt)
+
+GPIO_INT(EC_PWR_BTN_ODL,	PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
+#ifdef CONFIG_LOW_POWER_IDLE
+/* Used to wake up the EC from Deep Doze mode when writing to console */
+GPIO_INT(UART1_RX,	 PIN(B, 0), GPIO_INT_BOTH, uart_deepsleep_interrupt)	/* UART_DBG_TX_EC_RX */
+#endif
+
+/* USB-C interrupts */
+GPIO_INT(USB_C0_INT_ODL,	PIN(K, 0), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt) /* BC12 and charger */
+GPIO_INT(USB_C1_INT_ODL,	PIN(E, 6), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c1_interrupt) /* TCPC, charger, BC12 */
+GPIO_INT(USB_C0_CCSBU_OVP_ODL,	PIN(K, 6), GPIO_INT_FALLING | GPIO_PULL_UP, c0_ccsbu_ovp_interrupt) /* Fault protection */
+
+/* Other interrupts */
+GPIO_INT(LID_OPEN,		PIN(F, 3), GPIO_INT_BOTH, lid_interrupt)
+GPIO_INT(LID_360_L,		PIN(A, 7), GPIO_INT_BOTH, gmr_tablet_switch_isr)
+GPIO_INT(VOLDN_BTN_ODL,		PIN(I, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(VOLUP_BTN_ODL_HDMI_HPD,	PIN(I, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_sub_hdmi_hpd_interrupt)
+GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(J, 0), GPIO_INT_FALLING | GPIO_SEL_1P8V, lsm6dsm_interrupt)
+GPIO_INT(EC_WP_OD,		PIN(A, 6), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(PEN_DET_ODL,		PIN(J, 1), GPIO_INT_BOTH | GPIO_PULL_UP, pen_detect_interrupt)
+
+/* Power sequence GPIOs */
+GPIO(EC_AP_RTCRST,		PIN(K, 2), GPIO_OUT_LOW)
+GPIO(EC_AP_PWR_BTN_ODL,		PIN(B, 6), GPIO_ODR_HIGH)
+GPIO(EC_AP_DPWROK,		PIN(L, 7), GPIO_OUT_LOW)
+GPIO(EC_AP_RSMRST_L,		PIN(H, 0), GPIO_OUT_LOW)
+GPIO(EC_AP_WAKE_ODL,		PIN(D, 5), GPIO_ODR_HIGH)
+GPIO(SYS_RST_ODL,		PIN(D, 1), GPIO_ODR_HIGH)
+GPIO(EC_AP_SYS_PWROK,		PIN(F, 2), GPIO_OUT_LOW)
+GPIO(PG_PP5000_U_OD,		PIN(E, 3), GPIO_INPUT)
+GPIO(EN_PP3300_A,		PIN(C, 5), GPIO_OUT_LOW)
+GPIO(EC_AP_PCH_PWROK_OD,	PIN(D, 6), GPIO_ODR_LOW)
+GPIO(EN_PP5000_U,		PIN(K, 5), GPIO_OUT_LOW)
+/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
+GPIO(EN_VCCST,			PIN(D, 4), GPIO_INPUT)
+GPIO(EN_VCCIO_EXT,		PIN(B, 2), GPIO_OUT_LOW)
+GPIO(EC_PROCHOT_ODL,		PIN(I, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(EC_AP_VCCST_PWRGD_OD,	PIN(E, 5), GPIO_ODR_LOW)
+GPIO(ALL_SYS_PWRGD,		PIN(B, 7), GPIO_OUT_LOW)
+GPIO(EN_SLP_Z,			PIN(K, 3), GPIO_OUT_LOW)
+
+/* Required for icelake chipset code, but implemented through other means for dedede */
+UNIMPLEMENTED(AC_PRESENT)
+UNIMPLEMENTED(PG_EC_DSW_PWROK)
+UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
+
+/* I2C pins - Alternate function below configures I2C module on these pins */
+GPIO(EC_I2C_EEPROM_SCL,		PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SDA,		PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SCL,	PIN(C, 1), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SDA,	PIN(C, 2), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,		PIN(F, 6), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SENSOR_SDA,		PIN(F, 7), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SUB_USB_C1_SCL,	PIN(E, 0), GPIO_INPUT)
+GPIO(EC_I2C_SUB_USB_C1_SDA,	PIN(E, 7), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SCL,		PIN(A, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SDA,		PIN(A, 5), GPIO_INPUT)
+
+/* USB pins */
+GPIO(EN_USB_A_5V,			PIN(L, 6), GPIO_OUT_LOW)
+GPIO(EN_USB_C0_CC1_VCONN,	PIN(H, 4), GPIO_OUT_LOW)
+GPIO(EN_USB_C0_CC2_VCONN,	PIN(H, 6), GPIO_OUT_LOW)
+GPIO(EC_AP_USB_C0_HPD,		PIN(L, 4), GPIO_OUT_LOW)
+GPIO(EC_AP_USB_C1_HDMI_HPD,	PIN(K, 7), GPIO_OUT_LOW)
+GPIO(USB_C0_FRS,		PIN(C, 4), GPIO_OUT_LOW)
+GPIO(HDMI_SEL_L,		PIN(C, 6), GPIO_OUT_HIGH)
+
+/* MKBP event synchronization */
+GPIO(EC_AP_MKBP_INT_L,	PIN(L, 5), GPIO_ODR_HIGH)
+
+/* Misc pins which will run to the I/O board */
+GPIO(EC_SUB_IO_1_2, PIN(F, 0), GPIO_INPUT)
+GPIO(EC_SUB_IO_2_1, PIN(F, 1), GPIO_INPUT)
+
+/* Misc */
+GPIO(EN_BL_OD,			PIN(K, 4), GPIO_ODR_LOW)
+GPIO(EC_ENTERING_RW,		PIN(C, 7), GPIO_OUT_LOW)
+GPIO(EC_BATTERY_PRES_ODL,	PIN(I, 4), GPIO_INPUT)
+GPIO(EN_KB_BL,			PIN(J, 3), GPIO_OUT_LOW) /* Currently unused */
+GPIO(EN_PP5000_PEN,		PIN(B, 5), GPIO_OUT_LOW)
+GPIO(EC_CBI_WP,			PIN(H, 5), GPIO_OUT_LOW)
+
+/* NC pins, enable internal pull-down to avoid floating state. */
+GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOC3_NC, PIN(C, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG0_NC, PIN(G, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG3_NC, PIN(G, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG4_NC, PIN(G, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG5_NC, PIN(G, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG6_NC, PIN(G, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG7_NC, PIN(G, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOH1_NC, PIN(H, 1), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ4_NC, PIN(J, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ5_NC, PIN(J, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ6_NC, PIN(J, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOM6_NC, PIN(M, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+
+/* LED */
+GPIO(BAT_LED_AMBER_L,	 PIN(A, 1), GPIO_OUT_HIGH)
+GPIO(BAT_LED_WHITE_L,	 PIN(A, 2), GPIO_OUT_HIGH)
+GPIO(PWR_LED_WHITE_L,	 PIN(A, 3), GPIO_OUT_HIGH)
+
+/* Alternate functions GPIO definitions */
+/* Keyboard */
+ALTERNATE(PIN_MASK(KSI,   0xFF), 0, MODULE_KEYBOARD_SCAN, 0)		/* KSI0-7 */
+ALTERNATE(PIN_MASK(KSO_H, 0xFF), 0, MODULE_KEYBOARD_SCAN, 0)		/* KSO8-15 */
+ALTERNATE(PIN_MASK(KSO_L, 0xFB), 0, MODULE_KEYBOARD_SCAN, 0)		/* KSO0-1, 3-7 */
+GPIO(EC_KSO_02_INV, PIN(KSO_L, 2), GPIO_OUT_HIGH)			/* KSO2 inverted */
+
+/* UART */
+ALTERNATE(PIN_MASK(B, BIT(0) | BIT(1)), 0, MODULE_UART, 0)		/* UART for debug */
+
+/* I2C */
+ALTERNATE(PIN_MASK(B, BIT(3) | BIT(4)), 0, MODULE_I2C, 0)		/* I2C0 */
+ALTERNATE(PIN_MASK(C, BIT(1) | BIT(2)), 0, MODULE_I2C, 0)		/* I2C1 */
+ALTERNATE(PIN_MASK(F, BIT(6) | BIT(7)), 0, MODULE_I2C, GPIO_SEL_1P8V)	/* I2C2 - 1.8V */
+ALTERNATE(PIN_MASK(E, BIT(0) | BIT(7)), 0, MODULE_I2C, 0)		/* I2C4 */
+ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), 0, MODULE_I2C, 0)		/* I2C5 */
+
+/* ADC */
+ALTERNATE(PIN_MASK(L, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0)	/* ADC13: EC_SUB_ANALOG, ADC15: TEMP_SENSOR_3, ADC16: TEMP_SENSOR_4 */
+ALTERNATE(PIN_MASK(I, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0)	/* ADC0: EC_VSNS_PP3300_A, ADC2: TEMP_SENSOR_1, ADC3: TEMP_SENSOR_2 */
+
+/* PWM */
+ALTERNATE(PIN_MASK(A, BIT(0)), 0, MODULE_PWM, 0) 			/* KB_BL_PWM */
diff --git a/board/haboki/led.c b/board/haboki/led.c
new file mode 100644
index 0000000000..e353ba6f77
--- /dev/null
+++ b/board/haboki/led.c
@@ -0,0 +1,200 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Haboki specific LED settings. */
+
+#include "cbi_fw_config.h"
+#include "charge_state.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "led_common.h"
+
+#define BAT_LED_ON 0
+#define BAT_LED_OFF 1
+
+#define POWER_LED_ON 0
+#define POWER_LED_OFF 1
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+enum led_color {
+	LED_OFF = 0,
+	LED_AMBER,
+	LED_WHITE,
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
+};
+
+static int led_set_color_battery(enum led_color color)
+{
+	switch (color) {
+	case LED_OFF:
+		gpio_set_level(GPIO_BAT_LED_WHITE_L, BAT_LED_OFF);
+		gpio_set_level(GPIO_BAT_LED_AMBER_L, BAT_LED_OFF);
+		break;
+	case LED_WHITE:
+		gpio_set_level(GPIO_BAT_LED_WHITE_L, BAT_LED_ON);
+		gpio_set_level(GPIO_BAT_LED_AMBER_L, BAT_LED_OFF);
+		break;
+	case LED_AMBER:
+		gpio_set_level(GPIO_BAT_LED_WHITE_L, BAT_LED_OFF);
+		gpio_set_level(GPIO_BAT_LED_AMBER_L, BAT_LED_ON);
+		break;
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+	return EC_SUCCESS;
+}
+
+static int led_set_color_power(enum led_color color)
+{
+	switch (color) {
+	case LED_OFF:
+		gpio_set_level(GPIO_PWR_LED_WHITE_L, POWER_LED_OFF);
+		break;
+	case LED_WHITE:
+		gpio_set_level(GPIO_PWR_LED_WHITE_L, POWER_LED_ON);
+		break;
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+	return EC_SUCCESS;
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	switch (led_id) {
+	case EC_LED_ID_BATTERY_LED:
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		break;
+	case EC_LED_ID_POWER_LED:
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		break;
+	default:
+		break;
+	}
+}
+
+static int led_set_color(enum ec_led_id led_id, enum led_color color)
+{
+	int rv;
+
+	switch (led_id) {
+	case EC_LED_ID_BATTERY_LED:
+		rv = led_set_color_battery(color);
+		break;
+	case EC_LED_ID_POWER_LED:
+		rv = led_set_color_power(color);
+		break;
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+	return rv;
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (brightness[EC_LED_COLOR_WHITE] != 0)
+		led_set_color(led_id, LED_WHITE);
+	else if (brightness[EC_LED_COLOR_AMBER] != 0)
+		led_set_color(led_id, LED_AMBER);
+	else
+		led_set_color(led_id, LED_OFF);
+
+	return EC_SUCCESS;
+}
+
+static void led_set_battery(void)
+{
+	static int battery_ticks;
+	static int power_ticks;
+
+	battery_ticks++;
+
+	/*
+	 * Override battery LED for Drawlet/Drawman, Drawlet/Drawman
+	 * don't have power LED, blinking battery white LED to indicate
+	 * system suspend without charging.
+	 */
+	if (get_cbi_fw_config_tablet_mode() == TABLET_MODE_ABSENT) {
+		if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
+		    led_pwr_get_state() != LED_PWRS_CHARGE) {
+			led_set_color_battery(power_ticks++ & 0x2 ? LED_WHITE :
+								    LED_OFF);
+			return;
+		}
+	}
+
+	power_ticks = 0;
+
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
+		led_set_color_battery(LED_AMBER);
+		break;
+	case LED_PWRS_DISCHARGE_FULL:
+		if (extpower_is_present()) {
+			led_set_color_battery(LED_WHITE);
+			break;
+		}
+		__fallthrough;
+	case LED_PWRS_DISCHARGE:
+		/*
+		 * Blink white light (1 sec on, 1 sec off)
+		 * when battery capacity is less than 10%
+		 */
+		if (charge_get_percent() < 10)
+			led_set_color_battery(
+				(battery_ticks & 0x2) ? LED_WHITE : LED_OFF);
+		else
+			led_set_color_battery(LED_OFF);
+		break;
+	case LED_PWRS_ERROR:
+		led_set_color_battery((battery_ticks % 0x2) ? LED_WHITE :
+							      LED_OFF);
+		break;
+	case LED_PWRS_CHARGE_NEAR_FULL:
+		led_set_color_battery(LED_WHITE);
+		break;
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		led_set_color_battery(LED_WHITE);
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		led_set_color_battery((battery_ticks & 0x2) ? LED_AMBER :
+							      LED_OFF);
+		break;
+	default:
+		/* Other states don't alter LED behavior */
+		break;
+	}
+}
+
+static void led_set_power(void)
+{
+	static int power_tick;
+
+	power_tick++;
+
+	if (chipset_in_state(CHIPSET_STATE_ON))
+		led_set_color_power(LED_WHITE);
+	else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
+		led_set_color_power((power_tick & 0x2) ? LED_WHITE : LED_OFF);
+	else
+		led_set_color_power(LED_OFF);
+}
+
+/* Called by hook task every TICK */
+static void led_tick(void)
+{
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		led_set_power();
+
+	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
+		led_set_battery();
+}
+DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
diff --git a/board/haboki/usb_pd_policy.c b/board/haboki/usb_pd_policy.c
new file mode 100644
index 0000000000..8a2c07c575
--- /dev/null
+++ b/board/haboki/usb_pd_policy.c
@@ -0,0 +1,74 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery_smart.h"
+#include "charge_manager.h"
+#include "charger.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "driver/charger/sm5803.h"
+#include "driver/tcpm/tcpci.h"
+#include "usb_pd.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+int pd_check_vconn_swap(int port)
+{
+	/* Allow VCONN swaps if the AP is on */
+	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
+}
+
+void pd_power_supply_reset(int port)
+{
+	int prev_en;
+
+	if (port < 0 || port >= board_get_usb_pd_port_count())
+		return;
+
+	prev_en = charger_is_sourcing_otg_power(port);
+
+	/* Disable Vbus */
+	charger_enable_otg_power(port, 0);
+
+	/* Discharge Vbus if previously enabled */
+	if (prev_en)
+		sm5803_set_vbus_disch(port, 1);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	enum ec_error_list rv;
+
+	/* Disable sinking */
+	rv = sm5803_vbus_sink_enable(port, 0);
+	if (rv)
+		return rv;
+
+	/* Disable Vbus discharge */
+	sm5803_set_vbus_disch(port, 0);
+
+	/* Provide Vbus */
+	charger_enable_otg_power(port, 1);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+__override bool pd_check_vbus_level(int port, enum vbus_level level)
+{
+	return sm5803_check_vbus_level(port, level);
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	return sm5803_is_vbus_present(port);
+}
diff --git a/board/haboki/vif_override.xml b/board/haboki/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/haboki/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/hades/battery.c b/board/hades/battery.c
new file mode 100644
index 0000000000..29f73d76c4
--- /dev/null
+++ b/board/hades/battery.c
@@ -0,0 +1,80 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "cbi.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "gpio.h"
+/*
+ * Battery info for all Hades battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	/* LGC AP21A8T Battery Information */
+	[BATTERY_LGC_AP21A8T] = {
+		/* RAJ240045 Fuel Gauge */
+		.fuel_gauge = {
+			.manuf_name = "LGES KT0040G014",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.mfgacc_support = 0,
+				.reg_addr = 0x43,
+				.reg_mask = 0x0001,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0002,
+				.cfet_off_val = 0x0000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 17600,
+			.voltage_normal		= 15400, /* mV */
+			.voltage_min		= 12000, /* mV */
+			.precharge_current	= 256,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 75,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_LGC_AP21A8T;
+
+enum battery_present battery_hw_present(void)
+{
+	enum gpio_signal batt_pres;
+
+	batt_pres = GPIO_EC_BATT_PRES_ODL;
+
+	/* The GPIO is low when the battery is physically present */
+	return gpio_get_level(batt_pres) ? BP_NO : BP_YES;
+}
diff --git a/board/hades/board.c b/board/hades/board.c
new file mode 100644
index 0000000000..c4baf00f79
--- /dev/null
+++ b/board/hades/board.c
@@ -0,0 +1,106 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "anx7406.h"
+#include "battery.h"
+#include "button.h"
+#include "charge_ramp.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/nvidia_gpu.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "registers.h"
+#include "switch.h"
+#include "system.h"
+#include "throttle_ap.h"
+#include "usbc_config.h"
+#include "util.h"
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* Console output macros */
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+
+static int block_sequence;
+
+struct d_notify_policy d_notify_policies[] = {
+	[D_NOTIFY_1] = AC_ATLEAST_W(100),
+	[D_NOTIFY_2] = AC_ATLEAST_W(65),
+	[D_NOTIFY_3] = AC_DC,
+	[D_NOTIFY_4] = DC_ATMOST_SOC(20),
+	[D_NOTIFY_5] = DC_ATMOST_SOC(5),
+};
+BUILD_ASSERT(ARRAY_SIZE(d_notify_policies) == D_NOTIFY_COUNT);
+
+__override void board_cbi_init(void)
+{
+}
+
+/* Called on AP S3 -> S0 transition */
+static void board_chipset_resume(void)
+{
+	/* Allow keyboard backlight to be enabled */
+	gpio_set_level(GPIO_EN_EC_KB_BL_L, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S0 -> S3 transition */
+static void board_chipset_suspend(void)
+{
+	/* Turn off the keyboard backlight if it's on. */
+	gpio_set_level(GPIO_EN_EC_KB_BL_L, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
+
+static void board_init(void)
+{
+	const uint16_t i2c_sequencer_addr_flag = 0x10;
+	/* 0xaf: glitch filter reg address */
+	const uint8_t out[2] = { 0xaf, 0x01 };
+
+	int rv;
+
+	if ((system_get_reset_flags() & EC_RESET_FLAG_AP_OFF) ||
+	    (keyboard_scan_get_boot_keys() & BOOT_KEY_DOWN_ARROW)) {
+		CPRINTS("PG_PP3300_S5_OD block is enabled");
+		block_sequence = 1;
+	}
+
+	gpio_enable_interrupt(GPIO_BJ_ADP_PRESENT_ODL);
+
+	nvidia_gpu_init_policy(d_notify_policies);
+
+	/* Adjust glitch filtering on PPVAR_SYS (b/282181312) */
+	rv = i2c_xfer(I2C_PORT_MISC, i2c_sequencer_addr_flag, out, sizeof(out),
+		      NULL, 0);
+	if (rv)
+		CPRINTS("Failed to adjust sequencer timing (%d)", rv);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+void gpu_overt_interrupt(enum gpio_signal signal)
+{
+	nvidia_gpu_over_temp(gpio_get_level(signal));
+}
+
+int board_anx7406_init(int port)
+{
+	/* Unblock USB_C1_PPC_SNK_EN */
+	if (port == USBC_PORT_C1)
+		return anx7406_set_gpio(USBC_PORT_C1, 0, 1);
+
+	return EC_SUCCESS;
+}
diff --git a/board/hades/board.h b/board/hades/board.h
new file mode 100644
index 0000000000..c5e435f9a7
--- /dev/null
+++ b/board/hades/board.h
@@ -0,0 +1,232 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Hades board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "compile_time_macros.h"
+
+/* Baseboard features */
+#include "baseboard.h"
+
+#define CONFIG_SYSTEM_UNLOCKED
+
+/*
+ * Nvidia GPU
+ */
+#define CONFIG_GPU_NVIDIA
+
+/*
+ * This will happen automatically on NPCX9 ES2 and later. Do not remove
+ * until we can confirm all earlier chips are out of service.
+ */
+#define CONFIG_HIBERNATE_PSL_VCC1_RST_WAKEUP
+
+/*
+ * Hades blocks PG_PP3300_S5_OD instead to control AP power-on.
+ */
+#undef CONFIG_CHIPSET_X86_RSMRST_AFTER_S5
+
+/* Sensors */
+#undef CONFIG_TABLET_MODE
+#undef CONFIG_TABLET_MODE_SWITCH
+#undef CONFIG_GMR_TABLET_MODE
+
+/* Buttons */
+#undef CONFIG_VOLUME_BUTTONS
+
+/* USB Type A Features */
+#define USB_PORT_COUNT 1
+#define CONFIG_USB_PORT_POWER_DUMB
+
+/* USB-C0 */
+#define CONFIG_USB_PD_TCPM_NCT38XX
+#define CONFIG_USBC_PPC_TCPCI
+#define CONFIG_USBC_RETIMER_PI3DPX1207
+
+/* USB-C1 */
+#define CONFIG_USB_PD_TCPM_ANX7406
+#define CONFIG_USBC_PPC_TCPCI
+#define CONFIG_USBC_RETIMER_PS8818
+
+/* USB-C Common */
+#define CONFIG_USB_PD_FRS_TCPC
+
+/* I2C speed console command */
+#define CONFIG_CMD_I2C_SPEED
+
+/* I2C control host command */
+#define CONFIG_HOSTCMD_I2C_CONTROL
+
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
+
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 100000
+#define PD_MAX_CURRENT_MA 5000
+#define PD_MAX_VOLTAGE_MV 20000
+
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
+#define CONFIG_EXTPOWER_DEBOUNCE_MS 500
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
+
+/*
+ * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
+ * signal.
+ */
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PCH_DSW_PWROK GPIO_PCH_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
+
+/* System has back-lit keyboard */
+#define CONFIG_PWM_KBLIGHT
+
+/*
+ * I2C Bus Configuration
+ */
+/* 0: Unused */
+/* 1: USB-C0 */
+#define I2C_PORT_USB_C0_TCPC NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C0_PPC NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C0_BC12 NPCX_I2C_PORT1_0
+/* 2: USB-C1 */
+#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT2_0
+/* 3: Reserved for Accels */
+/* 4: Unused */
+/* 5: Battery */
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+/* 6: Unused */
+/* 7: Charger, EEPROM, IMVP9 VR, MONITOR, Power sequencer */
+#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_MISC NPCX_I2C_PORT7_0
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+
+/* Thermal features */
+#define CONFIG_THERMISTOR
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_TEMP_SENSOR_POWER
+#define CONFIG_TEMP_SENSOR_FIRST_READ_DELAY_MS 500
+#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
+
+#define CONFIG_FANS FAN_CH_COUNT
+
+/* Charger defines */
+#define CONFIG_CHARGER_BYPASS_MODE
+#define CONFIG_CHARGER_RAA489110
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20
+/* Round down 7700 max current to multiple of 128mA for ISL9241 AC prochot. */
+#define HADES_AC_PROCHOT_CURRENT_MA 7680
+
+/* Barrel jack adapter settings */
+#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT
+#define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1
+/* This is the next available port # after USB-C ports. */
+#define DEDICATED_CHARGE_PORT 2
+
+/*
+ * Older boards have a different ADC assignment.
+ */
+
+#define CONFIG_ADC_CHANNELS_RUNTIME_CONFIG
+
+/* Give SEQ_EC_DSW_PWROK IRQ higher priority to reduce latency for PCH_PWROK. */
+#define NPCX_MIWU0_GROUP_F 1
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h" /* needed by registers.h */
+#include "registers.h"
+#include "usbc_config.h"
+
+enum adc_channel {
+	ADC_TEMP_SENSOR_1_DDR_SOC,
+	ADC_TEMP_SENSOR_2_FAN,
+	ADC_TEMP_SENSOR_3_CHARGER,
+	ADC_TEMP_SENSOR_4_GPU_FBVDD,
+	ADC_CHARGER_IADP,
+	ADC_ADP_TYP,
+	ADC_USB_C1_VBUSM,
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1_DDR_SOC,
+	TEMP_SENSOR_2_GPU,
+	TEMP_SENSOR_3_CHARGER,
+	TEMP_SENSOR_4_GPU_FBVDD,
+	TEMP_SENSOR_COUNT
+};
+
+enum battery_type {
+	BATTERY_LGC_AP21A8T,
+
+	BATTERY_TYPE_COUNT
+};
+
+enum pwm_channel {
+	PWM_CH_KBLIGHT = 0, /* PWM3 */
+	PWM_CH_FAN, /* PWM5 */
+	PWM_CH_FAN2, /* PWM4 */
+	PWM_CH_COUNT
+};
+
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_1, FAN_CH_COUNT };
+
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_1, MFT_CH_COUNT };
+
+enum charge_port {
+	CHARGE_PORT_TYPEC0,
+	CHARGE_PORT_TYPEC1,
+	CHARGE_PORT_BARRELJACK,
+};
+
+/**
+ * Interrupt handler for PG_PP3300_S5_OD changes.
+ *
+ * @param signal	Signal which triggered the interrupt.
+ */
+void board_power_interrupt(enum gpio_signal signal);
+
+/* IRQ for BJ plug/unplug. */
+void bj_present_interrupt(enum gpio_signal signal);
+
+/* IRQ for over temperature. */
+void gpu_overt_interrupt(enum gpio_signal signal);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/hades/build.mk b/board/hades/build.mk
new file mode 100644
index 0000000000..e72f79992f
--- /dev/null
+++ b/board/hades/build.mk
@@ -0,0 +1,25 @@
+# -*- makefile -*-
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Hades board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx9
+CHIP_VARIANT:=npcx9m3f
+BASEBOARD:=brya
+
+board-y=
+board-y+=battery.o
+board-y+=board.o
+board-y+=charger_isl9241.o
+board-y+=fans.o
+board-y+=fw_config.o
+board-y+=i2c.o
+board-y+=keyboard.o
+board-y+=led.o
+board-y+=pwm.o
+board-y+=sensors.o
+board-y+=usbc_config.o
diff --git a/board/hades/charger_isl9241.c b/board/hades/charger_isl9241.c
new file mode 100644
index 0000000000..ad59c5f139
--- /dev/null
+++ b/board/hades/charger_isl9241.c
@@ -0,0 +1,275 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ *
+ * We need to deal with plug / unplug of AC chargers:
+ *
+ *  +---------+    +USB     +---------+
+ *  | BATTERY |------------>| BATTERY |
+ *  |         |<------------|    +USB |
+ *  +---------+    -USB     +---------+
+ *      | ^                     | ^
+ *  +BJ | | -BJ             +BJ | | -BJ
+ *      v |                     v |
+ *  +---------+    +USB     +---------+
+ *  | BATTERY |------------>| BATTERY |
+ *  |     +BJ |<------------| +BJ+USB |
+ *  +---------+    -USB     +---------+
+ *
+ * Depending on available battery charge, power rating of the new charger, and
+ * the system power state, transition/throttling may or may not occur but
+ * switching chargers is handled as follows:
+ *
+ * 1. Detects a new charger or removal of an existing charger.
+ * 2. charge_manager_update_charge is called with new charger's info.
+ * 3. board_set_active_charge_port is called.
+ *    3.1 It triggers hard & soft throttling for AP & GPU.
+ *    3.2 It disable active port then enables the new port.
+ * 4. HOOK_POWER_SUPPLY_CHANGE is called. We disables hard throttling.
+ * 5. charger task wakes up on HOOK_POWER_SUPPLY_CHANGE, enables (or disables)
+ *    bypass mode.
+ */
+
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/charger/isl9241.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "stdbool.h"
+#include "throttle_ap.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+
+/* Charger Chip Configuration */
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = ISL9241_ADDR_FLAGS,
+		.drv = &isl9241_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CHARGER_NUM);
+
+static int board_enable_bj_port(bool enable)
+{
+	if (enable) {
+		if (gpio_get_level(GPIO_BJ_ADP_PRESENT_ODL))
+			return EC_ERROR_INVAL;
+		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 0);
+	} else {
+		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 1);
+	}
+
+	CPRINTS("BJ power is %sabled", enable ? "en" : "dis");
+
+	return EC_SUCCESS;
+}
+
+static void board_throttle_ap_gpu(void)
+{
+	throttle_ap(THROTTLE_ON, THROTTLE_HARD, THROTTLE_SRC_AC);
+	throttle_gpu(THROTTLE_ON, THROTTLE_HARD, THROTTLE_SRC_AC);
+}
+
+/* Disable all VBUS sink ports except <port>. <port> = -1 disables all ports. */
+static int board_disable_other_vbus_sink(int except_port)
+{
+	int i, r, rv = EC_SUCCESS;
+
+	for (i = 0; i < ppc_cnt; i++) {
+		if (i == except_port)
+			continue;
+		/*
+		 * Do not return early if one fails otherwise we can get into a
+		 * boot loop assertion failure.
+		 */
+		r = ppc_vbus_sink_enable(i, 0);
+		if (r)
+			CPRINTS("Failed to disable sink path C%d (%d)", i, r);
+		rv |= r;
+	}
+
+	return rv;
+}
+
+/* Minimum battery SoC required for switching source port. */
+#define MIN_BATT_FOR_SWITCHING_SOURCE_PORT 1
+
+/*
+ * TODO: Recover from incomplete execution:
+ */
+int board_set_active_charge_port(int port)
+{
+	enum charge_supplier active_supplier = charge_manager_get_supplier();
+	int active_port = charge_manager_get_active_charge_port();
+
+	CPRINTS("Switching charger from P%d (supplier=%d) to P%d", active_port,
+		active_supplier, port);
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTS("Disabling all charger ports");
+
+		board_enable_bj_port(false);
+		board_disable_other_vbus_sink(-1);
+
+		return EC_SUCCESS;
+	}
+
+	/* Return on invalid or no-op call. */
+	if (port < 0 || CHARGE_PORT_COUNT <= port) {
+		return EC_ERROR_INVAL;
+	} else if (port == active_port) {
+		return EC_SUCCESS;
+	} else if (board_vbus_source_enabled(port)) {
+		/* Don't charge from a USBC source port */
+		CPRINTS("Don't enable P%d. It's sourcing.", port);
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * If we're in S0, throttle AP and GPU. They'll be unthrottled when
+	 * a port/supply switch completes (via HOOK_POWER_SUPPLY_CHANGE).
+	 *
+	 * If we're running currently on a battery (active_supplier == NONE), we
+	 * don't need to throttle because we're not disabling any port.
+	 */
+	if (chipset_in_state(CHIPSET_STATE_ON) &&
+	    active_supplier != CHARGE_SUPPLIER_NONE)
+		board_throttle_ap_gpu();
+
+	/*
+	 * We're here for the two cases:
+	 * 1. A new charger was connected.
+	 * 2. One charger was disconnected and we're switching to another.
+	 */
+
+	/*
+	 * We need to check the battery if we're switching a source port. If
+	 * we're just starting up or no AC was previously plugged, we shouldn't
+	 * check the battery. Both cases can be caught by supplier == NONE.
+	 */
+	if (active_supplier != CHARGE_SUPPLIER_NONE) {
+		if (charge_get_percent() < MIN_BATT_FOR_SWITCHING_SOURCE_PORT)
+			return EC_ERROR_NOT_POWERED;
+	}
+
+	/* Turn off other ports' sink paths before enabling requested port. */
+	if (is_pd_port(port)) {
+		/*
+		 * BJ port is enabled on start-up. So, we need to turn it off
+		 * even if we were not previously on BJ.
+		 */
+		board_enable_bj_port(false);
+		if (board_disable_other_vbus_sink(port))
+			return EC_ERROR_UNCHANGED;
+
+		/* Enable requested USBC charge port. */
+		if (ppc_vbus_sink_enable(port, 1)) {
+			CPRINTS("Failed to enable sink path for C%d", port);
+			return EC_ERROR_UNKNOWN;
+		}
+	} else if (port == CHARGE_PORT_BARRELJACK) {
+		/*
+		 * We can't proceed unless both ports are successfully
+		 * disconnected as sources.
+		 */
+		if (board_disable_other_vbus_sink(-1))
+			return EC_ERROR_UNKNOWN;
+		board_enable_bj_port(true);
+	}
+
+	CPRINTS("New charger P%d", port);
+
+	return EC_SUCCESS;
+}
+
+static const struct charge_port_info bj_power = {
+	/* 150W (also default) */
+	.voltage = 19500,
+	.current = 7700,
+};
+
+/* Debounce time for BJ plug/unplug */
+#define BJ_DEBOUNCE_MS CONFIG_EXTPOWER_DEBOUNCE_MS
+
+int board_should_charger_bypass(void)
+{
+	return charge_manager_get_active_charge_port() == DEDICATED_CHARGE_PORT;
+}
+
+static void bj_connect(void)
+{
+	static int8_t bj_connected = -1;
+	int connected = !gpio_get_level(GPIO_BJ_ADP_PRESENT_ODL);
+
+	/* Debounce */
+	if (connected == bj_connected)
+		return;
+
+	bj_connected = connected;
+	CPRINTS("BJ %sconnected", connected ? "" : "dis");
+
+	charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED,
+				     DEDICATED_CHARGE_PORT,
+				     connected ? &bj_power : NULL);
+}
+DECLARE_DEFERRED(bj_connect);
+
+/* This handler shouldn't be needed if ACOK from isl9241 is working. */
+void bj_present_interrupt(enum gpio_signal signal)
+{
+	hook_call_deferred(&bj_connect_data, BJ_DEBOUNCE_MS * MSEC);
+}
+
+void ac_change(void)
+{
+	/*
+	 * Serialize. We don't handle USB-C here because we'll get a
+	 * notification from TCPC.
+	 */
+	hook_call_deferred(&bj_connect_data, 0);
+}
+DECLARE_HOOK(HOOK_AC_CHANGE, ac_change, HOOK_PRIO_DEFAULT);
+
+static void power_supply_changed(void)
+{
+	/*
+	 * We've switched to a new charge port (or no port). Hardware throttles
+	 * can be removed now. Software throttles may stay enabled and change
+	 * as the situation changes.
+	 */
+	throttle_ap(THROTTLE_OFF, THROTTLE_HARD, THROTTLE_SRC_AC);
+	/*
+	 * Unthrottling GPU is done through a deferred call scheduled when it
+	 * was throttled.
+	 */
+}
+DECLARE_HOOK(HOOK_POWER_SUPPLY_CHANGE, power_supply_changed, HOOK_PRIO_DEFAULT);
+
+static void bj_state_init(void)
+{
+	/*
+	 * Initialize all charge suppliers to 0. The charge manager waits until
+	 * all ports have reported in before doing anything.
+	 */
+	for (int i = 0; i < CHARGE_PORT_COUNT; i++) {
+		for (int j = 0; j < CHARGE_SUPPLIER_COUNT; j++)
+			charge_manager_update_charge(j, i, NULL);
+	}
+
+	bj_connect();
+
+	isl9241_set_ac_prochot(CHARGER_SOLO, HADES_AC_PROCHOT_CURRENT_MA);
+}
+DECLARE_HOOK(HOOK_INIT, bj_state_init, HOOK_PRIO_INIT_CHARGE_MANAGER + 1);
diff --git a/board/hades/ec.tasklist b/board/hades/ec.tasklist
new file mode 100644
index 0000000000..905a3cceca
--- /dev/null
+++ b/board/hades/ec.tasklist
@@ -0,0 +1,29 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ *
+ * USB_CHG_Px tasks must be contiguous (see USB_CHG_PORT_TO_TASK_ID(x)).
+ * PD_Cx tasks must be contiguous (see PD_PORT_TO_TASK_ID(x))
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, HOOKS_TASK_STACK_SIZE) \
+	TASK_ALWAYS(LED, led_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, BASEBOARD_CHARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, BASEBOARD_CHIPSET_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, CONSOLE_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, BASEBOARD_POWERBTN_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, BASEBOARD_PD_INT_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, BASEBOARD_PD_INT_TASK_STACK_SIZE)
diff --git a/board/hades/fans.c b/board/hades/fans.c
new file mode 100644
index 0000000000..337ac21418
--- /dev/null
+++ b/board/hades/fans.c
@@ -0,0 +1,66 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Physical fans. These are logically separate from pwm_channels. */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "fan.h"
+#include "fan_chip.h"
+#include "hooks.h"
+#include "pwm.h"
+
+/* MFT channels. These are logically separate from pwm_channels. */
+const struct mft_t mft_channels[] = {
+	[MFT_CH_0] = {
+		.module = NPCX_MFT_MODULE_1,
+		.clk_src = TCKC_LFCLK,
+		.pwm_id = PWM_CH_FAN,
+	},
+	[MFT_CH_1] = {
+		.module = NPCX_MFT_MODULE_2,
+		.clk_src = TCKC_LFCLK,
+		.pwm_id = PWM_CH_FAN2,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
+
+static const struct fan_conf fan_conf_0 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
+	.pgood_gpio = -1,
+	.enable_gpio = GPIO_EN_PP5000_FAN,
+};
+
+static const struct fan_conf fan_conf_1 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_1, /* Use MFT id to control fan */
+	.pgood_gpio = -1,
+	.enable_gpio = GPIO_EN_PP12000_FAN_X,
+};
+
+static const struct fan_rpm fan_rpm_0 = {
+	.rpm_min = 2500,
+	.rpm_start = 2500,
+	.rpm_max = 4300,
+};
+
+static const struct fan_rpm fan_rpm_1 = {
+	.rpm_min = 2500,
+	.rpm_start = 2500,
+	.rpm_max = 4300,
+};
+
+const struct fan_t fans[FAN_CH_COUNT] = {
+	[FAN_CH_0] = {
+		.conf = &fan_conf_0,
+		.rpm = &fan_rpm_0,
+	},
+	[FAN_CH_1] = {
+		.conf = &fan_conf_1,
+		.rpm = &fan_rpm_1,
+	},
+};
diff --git a/board/hades/fw_config.c b/board/hades/fw_config.c
new file mode 100644
index 0000000000..a49079a9f1
--- /dev/null
+++ b/board/hades/fw_config.c
@@ -0,0 +1,40 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "fw_config.h"
+
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
+
+static union hades_cbi_fw_config fw_config;
+BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
+
+/*
+ * FW_CONFIG defaults for hades if the CBI.FW_CONFIG data is not
+ * initialized.
+ */
+static const union hades_cbi_fw_config fw_config_defaults = {
+	.kb_bl = KEYBOARD_BACKLIGHT_ENABLED,
+};
+
+/****************************************************************************
+ * Hades FW_CONFIG access
+ */
+void board_init_fw_config(void)
+{
+	if (cbi_get_fw_config(&fw_config.raw_value)) {
+		CPRINTS("CBI: Read FW_CONFIG failed, using board defaults");
+		fw_config = fw_config_defaults;
+	}
+}
+
+union hades_cbi_fw_config get_fw_config(void)
+{
+	return fw_config;
+}
diff --git a/board/hades/fw_config.h b/board/hades/fw_config.h
new file mode 100644
index 0000000000..5f7758bb2a
--- /dev/null
+++ b/board/hades/fw_config.h
@@ -0,0 +1,38 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __BOARD_HADES_FW_CONFIG_H_
+#define __BOARD_HADES_FW_CONFIG_H_
+
+#include <stdint.h>
+
+/****************************************************************************
+ * CBI FW_CONFIG layout for Hades board.
+ *
+ * Source of truth is the project/draco/agah/config.star configuration file.
+ */
+
+enum ec_cfg_keyboard_backlight_type {
+	KEYBOARD_BACKLIGHT_DISABLED = 0,
+	KEYBOARD_BACKLIGHT_ENABLED = 1
+};
+
+union hades_cbi_fw_config {
+	struct {
+		enum ec_cfg_keyboard_backlight_type kb_bl : 1;
+		uint32_t audio : 3;
+		uint32_t reserved_1 : 21;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Read the cached FW_CONFIG.  Guaranteed to have valid values.
+ *
+ * @return the FW_CONFIG for the board.
+ */
+union hades_cbi_fw_config get_fw_config(void);
+
+#endif /* __BOARD_HADES_FW_CONFIG_H_ */
diff --git a/board/hades/gpio.inc b/board/hades/gpio.inc
new file mode 100644
index 0000000000..1fac87c82f
--- /dev/null
+++ b/board/hades/gpio.inc
@@ -0,0 +1,143 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define MODULE_KB		MODULE_KEYBOARD_SCAN
+
+/* INTERRUPT GPIOs: */
+GPIO_INT(SEQ_EC_DSW_PWROK,               PIN(C, 7), GPIO_INT_BOTH, intel_x86_pwrok_signal_interrupt)
+GPIO_INT(ACOK_OD,                        PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
+GPIO_INT(EC_PROCHOT_IN_L,                PIN(A, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
+GPIO_INT(EC_WP_ODL,                      PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(GSC_EC_PWR_BTN_ODL,             PIN(0, 1), GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW, power_button_interrupt)
+GPIO_INT(LID_OPEN,                       PIN(D, 2), GPIO_INT_BOTH | GPIO_PULL_UP | GPIO_HIB_WAKE_HIGH, lid_interrupt)
+GPIO_INT(SEQ_EC_ALL_SYS_PG,              PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_RSMRST_ODL,              PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,                       PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,                      PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SYS_SLP_S0IX_L,                 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(USB_C0_BC12_INT_ODL,            PIN(C, 6), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C0_TCPC_INT_ODL,            PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C0_PPC_INT_ODL,             PIN(A, 7), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C1_BC12_INT_ODL,            PIN(8, 3), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C1_TCPC_INT_ODL,            PIN(7, 0), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C1_PPC_INT_ODL,             PIN(B, 1), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(BJ_ADP_PRESENT_ODL,             PIN(9, 5), GPIO_INT_BOTH | GPIO_PULL_UP, bj_present_interrupt)
+GPIO_INT(GPU_OVERT_ODL,                  PIN(5, 0), GPIO_INT_BOTH, gpu_overt_interrupt)
+
+/* USED GPIOs: */
+GPIO(CCD_MODE_ODL,                   PIN(E, 5), GPIO_INPUT)
+GPIO(CPU_C10_GATE_L,                 PIN(6, 7), GPIO_INPUT)
+GPIO(EC_BATT_PRES_ODL,               PIN(A, 3), GPIO_INPUT)
+GPIO(EC_ENTERING_RW,                 PIN(0, 3), GPIO_OUT_LOW)
+GPIO(EC_EN_EDP_BL,                   PIN(D, 3), GPIO_ODR_HIGH)
+GPIO(EC_GSC_PACKET_MODE,             PIN(7, 5), GPIO_OUT_LOW)
+GPIO(EC_I2C_BAT_SCL,                 PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_BAT_SDA,                 PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SCL_R,              PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SDA_R,              PIN(B, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_SCL,              PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_SDA,              PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SCL,              PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SDA,              PIN(8, 7), GPIO_INPUT)
+GPIO(EN_EC_KB_BL_L,                  PIN(8, 6), GPIO_ODR_HIGH)
+GPIO(IMVP91_PE_EC,                   PIN(E, 3), GPIO_OUT_LOW)
+GPIO(EC_PCHHOT_ODL,                  PIN(7, 4), GPIO_INPUT)
+GPIO(EC_PCH_INT_ODL,                 PIN(B, 0), GPIO_ODR_HIGH)
+GPIO(EC_PCH_PWR_BTN_ODL,             PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(EC_PCH_RSMRST_L,                PIN(A, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_RTCRST,                  PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_SYS_PWROK,               PIN(3, 7), GPIO_OUT_LOW)
+GPIO(EC_PCH_WAKE_R_ODL,              PIN(C, 0), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_ODL,                 PIN(6, 3), GPIO_ODR_HIGH)
+GPIO(EN_PP5000_FAN,                  PIN(6, 1), GPIO_OUT_LOW)
+GPIO(EN_PP12000_FAN_X,               PIN(F, 5), GPIO_OUT_LOW)
+GPIO(EN_PP5000_USBA_R,               PIN(D, 7), GPIO_OUT_LOW)
+GPIO(EN_S5_RAILS,                    PIN(9, 6), GPIO_OUT_LOW)
+GPIO(IMVP9_VRRDY_OD,                 PIN(4, 3), GPIO_INPUT)
+GPIO(PCH_PWROK,                      PIN(7, 2), GPIO_OUT_LOW)
+GPIO(SYS_RST_ODL,                    PIN(C, 5), GPIO_ODR_HIGH)
+GPIO(EC_USB_PCH_C0_OC_ODL,           PIN(9, 4), GPIO_ODR_HIGH)
+GPIO(EC_USB_PCH_C1_OC_ODL,           PIN(9, 7), GPIO_ODR_HIGH)
+GPIO(VCCST_PWRGD_OD,                 PIN(A, 4), GPIO_ODR_LOW)
+GPIO(EN_USB_A_LOW_POWER,             PIN(9, 3), GPIO_OUT_LOW)
+GPIO(EN_USB_C1_28V,                  PIN(B, 5), GPIO_OUT_LOW)
+GPIO(USB_C0_TCPC_RST_ODL,            PIN(D, 4), GPIO_OUT_HIGH)
+GPIO(NVIDIA_GPU_ACOFF_ODL,           PIN(5, 6), GPIO_ODR_HIGH)
+GPIO(LED_4_L,                        PIN(6, 0), GPIO_OUT_HIGH)
+GPIO(LED_3_L,                        PIN(C, 2), GPIO_OUT_HIGH)
+GPIO(LED_2_L,                        PIN(C, 3), GPIO_OUT_HIGH)
+GPIO(LED_1_L,                        PIN(C, 4), GPIO_OUT_HIGH)
+GPIO(USB_C0_PPC_HI_ILIM,             PIN(F, 2), GPIO_OUT_HIGH)
+GPIO(USB_C1_PPC_HI_ILIM,             PIN(F, 3), GPIO_OUT_HIGH)
+GPIO(USB_C0_IN_HPD,                  PIN(6, 2), GPIO_OUT_LOW)
+/* Block AP power sequencing (b/279214842) */
+GPIO(PG_PP3300_S5_OD,                PIN(B, 4), GPIO_ODR_HIGH)
+
+/*
+ * Barrel-jack adapter enable switch. When starting up on a depleted battery,
+ * we'll be powered by either BJ or USB-C but not both. The EC will detect BJ
+ * or USBC and disable the other ports.
+ */
+GPIO(EN_PPVAR_BJ_ADP_L,              PIN(A, 2), GPIO_OUT_LOW)
+
+/*
+ * The NPCX keyboard driver does not use named GPIOs to access
+ * keyboard scan pins, so we do not list them in *gpio.inc. However, when
+ * KEYBOARD_COL2_INVERTED is defined, this name is required.
+ */
+GPIO(EC_KSO_02_INV,               PIN(1, 7), GPIO_OUT_LOW)
+
+/* UART alternate functions */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0) /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */
+
+/* I2C alternate functions */
+ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)  /* GPIO33/I2C5_SCL0/CTS_L, GPIO36/RTS_L/I2C5_SDA0 */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)  /* GPIO87/I2C1_SDA0 */
+ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)  /* GPIO92/I2C2_SCL0, GPIO91/I2C2_SDA0, GPIO90/I2C1_SCL0 */
+ALTERNATE(PIN_MASK(B, 0x0c), 0, MODULE_I2C, 0)  /* GPIOB3/I2C7_SCL0/DCD_L, GPIOB2/I2C7_SDA0/DSR_L */
+
+/* PWM alternate functions */
+ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0)  /* GPIO40/TA1 EC_FAN1_TACH */
+ALTERNATE(PIN_MASK(7, 0x08), 0, MODULE_PWM, 0)  /* GPIO73/TA2 EC_FAN2_TACH */
+ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)  /* GPIO80/PWM3 EC_KB_BL_PWM */
+ALTERNATE(PIN_MASK(B, 0xC0), 0, MODULE_PWM, 0)  /* GPIOB7/PWM5=FAN1_PWM,
+                                                   GPIOB6/PWM4=FAN2_PWM */
+
+/* ADC alternate functions */
+ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0)  /* GPIO34/PS2_DAT2/ADC6=TEMP_SENSOR_3 */
+ALTERNATE(PIN_MASK(4, 0x36), 0, MODULE_ADC, 0)  /* GPIO42/ADC3/RI_L=CHARGER_IADP_R,
+                                                   GPIO45/ADC0=TEMP_SENSOR_1,
+                                                   GPIO44/ADC1=TEMP_SENSOR_2,
+                                                   GPIO41/ADC4=ADP_TYP. */
+ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0)  /* GPIOE1/ADC7=TEMP_SENSOR_4 */
+ALTERNATE(PIN_MASK(F, 0x01), 0, MODULE_ADC, 0)  /* GPIOF0/ADC9=USB_C1_VBUSM */
+
+/* KB alternate functions */
+ALTERNATE(PIN_MASK(0, 0xf0), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO10&P80_CLK/GPIO07, KSO11&P80_DAT/GPIO06, KSO12/GPIO05, KSO13/GPIO04 */
+ALTERNATE(PIN_MASK(1, 0x7f), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO06/GPO13/GP_SEL_L, KSO07/GPO12/JEN_L, KSO03/GPIO16/JTAG_TDO0_SWO, KSO04/GPIO15/XNOR, KSO05/GPIO14, KSO08/GPIO11/CR_SOUT1, KSO09/GPIO10/CR_SIN1 */
+ALTERNATE(PIN_MASK(2, 0xfc), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI2/GPIO27/TRACEDATA1, KSI3/GPIO26/TRACEDATA0, KSI4/GPIO25/TRACECLK/GP_SCLK, KSI5/GPIO24/GP_MISO, KSI6/GPIO23/S_SBUB, KSI7/GPIO22/S_SBUA */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO00/GPIO21/JTAG_TCK_SWCLK, KSO01/GPIO20/JTAG_TMS_SWIO */
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI0/GPIO31/TRACEDATA3/GP_MOSI, KSI1/GPIO30/TRACEDATA2/GP_CS_L */
+ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO14/GPIO82 */
+
+/* PMU alternate functions */
+ALTERNATE(PIN_MASK(0, 0x01), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN2_L&GPI00/GPIO00 */
+ALTERNATE(PIN_MASK(0, 0x02), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW) /* GPIO01/PSL_IN3_L&GPI01 */
+ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN1_L&GPID2/GPIOD2 */
+
+/* Unused Pins */
+UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
+UNUSED(PIN(D, 0))
+UNUSED(PIN(D, 1))
+UNUSED(PIN(3, 2))       /* GPO32/TRIS_L */
+UNUSED(PIN(3, 5))       /* GPO35/CR_SOUT4/TEST_L */
+UNUSED(PIN(6, 6))       /* GPIO66 */
+UNUSED(PIN(8, 1))       /* GPIO81 */
+UNUSED(PIN(E, 1))       /* GPIOE1 */
+UNUSED(PIN(E, 4))
+UNUSED(PIN(0, 2))       /* USB_C1_TCPC_RST_ODL. Not connected because R564 is
+                           DNS. */
diff --git a/board/hades/i2c.c b/board/hades/i2c.c
new file mode 100644
index 0000000000..a09be51cd3
--- /dev/null
+++ b/board/hades/i2c.c
@@ -0,0 +1,48 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "hooks.h"
+#include "i2c.h"
+
+#define BOARD_ID_FAST_PLUS_CAPABLE 2
+
+/* I2C port map configuration */
+const struct i2c_port_t i2c_ports[] = {
+	{
+		/* I2C1 */
+		.name = "tcpc0",
+		.port = I2C_PORT_USB_C0_TCPC,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_USB_C0_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_SDA,
+	},
+	{
+		/* I2C2 */
+		.name = "tcpc1",
+		.port = I2C_PORT_USB_C1_TCPC,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_USB_C1_SCL,
+		.sda = GPIO_EC_I2C_USB_C1_SDA,
+	},
+	{
+		/* I2C5 */
+		.name = "battery",
+		.port = I2C_PORT_BATTERY,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_BAT_SCL,
+		.sda = GPIO_EC_I2C_BAT_SDA,
+	},
+	{
+		/* I2C7 */
+		.name = "misc",
+		.port = I2C_PORT_MISC,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_MISC_SCL_R,
+		.sda = GPIO_EC_I2C_MISC_SDA_R,
+	},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/board/hades/keyboard.c b/board/hades/keyboard.c
new file mode 100644
index 0000000000..a420ec8a4a
--- /dev/null
+++ b/board/hades/keyboard.c
@@ -0,0 +1,65 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "ec_commands.h"
+#include "keyboard_scan.h"
+#include "timer.h"
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/* Increase from 50 us, because KSO_02 passes through the H1. */
+	.output_settle_us = 80,
+	/* Other values should be the same as the default configuration. */
+	.debounce_down_us = 9 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x1c, 0xfe, 0xff, 0xff, 0xff, 0xf5, 0xff,
+		0xa4, 0xff, 0xf6, 0x55, 0xfe, 0xff, 0xff, 0xff, /* full set */
+	},
+};
+
+static const struct ec_response_keybd_config keybd = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_FORWARD,		/* T2 */
+		TK_REFRESH,		/* T3 */
+		TK_FULLSCREEN,		/* T4 */
+		TK_OVERVIEW,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	/* There's no screen lock key on hades */
+	.capabilities = KEYBD_CAP_NUMERIC_KEYPAD,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &keybd;
+}
+
+/*
+ * We have total 30 pins for keyboard connecter {-1, -1} mean
+ * the N/A pin that don't consider it and reserve index 0 area
+ * that we don't have pin 0.
+ */
+const int keyboard_factory_scan_pins[][2] = {
+	{ -1, -1 }, { 0, 5 },	{ 1, 1 }, { 1, 0 },   { 0, 6 },	  { 0, 7 },
+	{ -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 },   { -1, -1 }, { 1, 6 },
+	{ 1, 7 },   { 3, 1 },	{ 2, 0 }, { 1, 5 },   { 2, 6 },	  { 2, 7 },
+	{ 2, 1 },   { 2, 4 },	{ 2, 5 }, { 1, 2 },   { 2, 3 },	  { 2, 2 },
+	{ 3, 0 },   { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 },	  { -1, -1 },
+	{ -1, -1 },
+};
+const int keyboard_factory_scan_pins_used =
+	ARRAY_SIZE(keyboard_factory_scan_pins);
diff --git a/board/hades/led.c b/board/hades/led.c
new file mode 100644
index 0000000000..1e34229a47
--- /dev/null
+++ b/board/hades/led.c
@@ -0,0 +1,200 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery LED control for Hades
+ */
+
+#include "battery.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "chipset.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "host_command.h"
+#include "led_common.h"
+#include "task.h"
+
+#include <stdint.h>
+
+#define BAT_LED_ON 0
+#define BAT_LED_OFF 1
+
+#define BATT_LOW_BCT 10
+
+#define LED_TICK_INTERVAL_MS (500 * MSEC)
+#define LED_CYCLE_TIME_MS (2000 * MSEC)
+#define LED_TICKS_PER_CYCLE (LED_CYCLE_TIME_MS / LED_TICK_INTERVAL_MS)
+#define LED_ON_TIME_MS (1000 * MSEC)
+#define LED_ON_TICKS (LED_ON_TIME_MS / LED_TICK_INTERVAL_MS)
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+enum led_color {
+	LED_OFF = 0,
+	LED_AMBER,
+	LED_WHITE,
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
+};
+
+static void led_set_color_battery(enum led_color color)
+{
+	enum gpio_signal amber_led1, white_led1, amber_led2, white_led2;
+
+	amber_led1 = GPIO_LED_1_L;
+	white_led1 = GPIO_LED_2_L;
+	amber_led2 = GPIO_LED_3_L;
+	white_led2 = GPIO_LED_4_L;
+
+	switch (color) {
+	case LED_WHITE:
+		gpio_set_level(white_led1, BAT_LED_ON);
+		gpio_set_level(amber_led1, BAT_LED_OFF);
+		gpio_set_level(white_led2, BAT_LED_ON);
+		gpio_set_level(amber_led2, BAT_LED_OFF);
+		break;
+	case LED_AMBER:
+		gpio_set_level(white_led1, BAT_LED_OFF);
+		gpio_set_level(amber_led1, BAT_LED_ON);
+		gpio_set_level(white_led2, BAT_LED_OFF);
+		gpio_set_level(amber_led2, BAT_LED_ON);
+		break;
+	case LED_OFF:
+		gpio_set_level(white_led1, BAT_LED_OFF);
+		gpio_set_level(amber_led1, BAT_LED_OFF);
+		gpio_set_level(white_led2, BAT_LED_OFF);
+		gpio_set_level(amber_led2, BAT_LED_OFF);
+		break;
+	default:
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	switch (led_id) {
+	case EC_LED_ID_BATTERY_LED:
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		break;
+	default:
+		break;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	switch (led_id) {
+	case EC_LED_ID_BATTERY_LED:
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_battery(LED_WHITE);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(LED_AMBER);
+		else
+			led_set_color_battery(LED_OFF);
+		break;
+	default:
+		return EC_ERROR_PARAM1;
+	}
+
+	return EC_SUCCESS;
+}
+
+/*
+ * Set active charge port color to the parameter, turn off all others.
+ * If no port is active (-1), turn off all LEDs.
+ */
+static void set_active_port_color(enum led_color color)
+{
+	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
+		led_set_color_battery(color);
+}
+
+static void led_set_battery(void)
+{
+	static unsigned int battery_ticks;
+	static unsigned int suspend_ticks;
+
+	battery_ticks++;
+
+	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
+	    led_pwr_get_state() != LED_PWRS_CHARGE) {
+		suspend_ticks++;
+
+		led_set_color_battery(
+			(suspend_ticks % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
+				LED_WHITE :
+				LED_OFF);
+
+		return;
+	}
+
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
+		/* Always indicate when charging, even in suspend. */
+		set_active_port_color(LED_AMBER);
+		break;
+	case LED_PWRS_DISCHARGE:
+		/*
+		 * Blinking amber LEDs slowly if battery is lower 10
+		 * percentage.
+		 */
+		if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
+			if (charge_get_percent() < BATT_LOW_BCT)
+				led_set_color_battery(
+					(battery_ticks % LED_TICKS_PER_CYCLE <
+					 LED_ON_TICKS) ?
+						LED_AMBER :
+						LED_OFF);
+			else
+				led_set_color_battery(LED_OFF);
+		}
+
+		break;
+	case LED_PWRS_ERROR:
+		if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
+			led_set_color_battery(
+				(battery_ticks & 0x1) ? LED_AMBER : LED_OFF);
+		}
+
+		break;
+	case LED_PWRS_CHARGE_NEAR_FULL:
+		set_active_port_color(LED_WHITE);
+		break;
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		set_active_port_color(LED_WHITE);
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		set_active_port_color(
+			(battery_ticks % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
+				LED_AMBER :
+				LED_OFF);
+		break;
+	default:
+		/* Other states don't alter LED behavior */
+		break;
+	}
+}
+
+void led_task(void *u)
+{
+	uint32_t start_time;
+	uint32_t task_duration;
+
+	while (1) {
+		start_time = get_time().le.lo;
+
+		led_set_battery();
+
+		/* Compute time for this iteration */
+		task_duration = get_time().le.lo - start_time;
+		/*
+		 * Compute wait time required to for next desired LED tick. If
+		 * the duration exceeds the tick time, then don't sleep.
+		 */
+		if (task_duration < LED_TICK_INTERVAL_MS)
+			usleep(LED_TICK_INTERVAL_MS - task_duration);
+	}
+}
diff --git a/board/hades/pwm.c b/board/hades/pwm.c
new file mode 100644
index 0000000000..22c01fc6d9
--- /dev/null
+++ b/board/hades/pwm.c
@@ -0,0 +1,47 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "hooks.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_KBLIGHT] = {
+		.channel = 3,
+		.flags = 0,
+		/*
+		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
+		 * flicker. Higher frequencies consume similar average power to
+		 * lower PWM frequencies, but higher frequencies record a much
+		 * lower maximum power.
+		 */
+		.freq = 2400,
+	},
+	[PWM_CH_FAN] = {
+		.channel = 5,
+		.flags = PWM_CONFIG_OPEN_DRAIN,
+		.freq = 25000
+	},
+	[PWM_CH_FAN2] = {
+		.channel = 4,
+		.flags = PWM_CONFIG_OPEN_DRAIN,
+		.freq = 25000
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+static void board_pwm_init(void)
+{
+	/*
+	 * Turn off all the LEDs.
+	 * Turn on the fan at 100%.
+	 */
+
+	pwm_enable(PWM_CH_KBLIGHT, 1);
+	pwm_set_duty(PWM_CH_KBLIGHT, 50);
+}
+DECLARE_HOOK(HOOK_INIT, board_pwm_init, HOOK_PRIO_DEFAULT);
diff --git a/board/hades/sensors.c b/board/hades/sensors.c
new file mode 100644
index 0000000000..87d1e2a625
--- /dev/null
+++ b/board/hades/sensors.c
@@ -0,0 +1,156 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc.h"
+#include "common.h"
+#include "hooks.h"
+#include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
+#include "thermal.h"
+
+/* ADC configuration */
+struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_1_DDR_SOC] = {
+		.name = "TEMP_DDR_SOC",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_2_FAN] = {
+		.name = "TEMP_FAN",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_3_CHARGER] = {
+		.name = "TEMP_CHARGER",
+		.input_ch = NPCX_ADC_CH6,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_4_GPU_FBVDD] = {
+		.name = "TEMP_GPU_FBVDD",
+		.input_ch = NPCX_ADC_CH7,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_CHARGER_IADP] = {
+		.name = "CHARGER_IADP",
+		.input_ch = NPCX_ADC_CH3,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_ADP_TYP] = {
+		.name = "ADP_TYP",
+		.input_ch = NPCX_ADC_CH4,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_USB_C1_VBUSM] = {
+		.name = "USB_C1_VBUSM",
+		.input_ch = NPCX_ADC_CH9,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* Temperature sensor configuration */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1_DDR_SOC] = {
+		.name = "DDR and SOC",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_1_DDR_SOC,
+	},
+	[TEMP_SENSOR_2_GPU] = {
+		.name = "GPU",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_2_FAN,
+	},
+	[TEMP_SENSOR_3_CHARGER] = {
+		.name = "Charger",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_3_CHARGER,
+	},
+	[TEMP_SENSOR_4_GPU_FBVDD] = {
+		.name = "GPU FBVDD",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_4_GPU_FBVDD,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(85), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(90), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(80), \
+		}, \
+		.temp_fan_off = C_TO_K(35), \
+		.temp_fan_max = C_TO_K(60), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
+
+#define THERMAL_GPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(85), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(90), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(80), \
+		}, \
+		.temp_fan_off = C_TO_K(35), \
+		.temp_fan_max = C_TO_K(60), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_gpu = THERMAL_GPU;
+
+/*
+ * Inductor limits - used for both charger and PP3300 regulator
+ *
+ * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
+ *
+ * Charger max recommended temperature 125C, max absolute temperature 150C
+ * PP3300 regulator: operating range -40 C to 125 C
+ *
+ * Inductors: limit of 125c
+ * PCB: limit is 80c
+ */
+#define THERMAL_CHARGER          \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(105), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(120), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(90), \
+		}, \
+		.temp_fan_off = C_TO_K(35), \
+		.temp_fan_max = C_TO_K(65), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_charger =
+	THERMAL_CHARGER;
+
+struct ec_thermal_config thermal_params[] = {
+	[TEMP_SENSOR_1_DDR_SOC] = THERMAL_CPU,
+	[TEMP_SENSOR_2_GPU] = THERMAL_GPU,
+	[TEMP_SENSOR_3_CHARGER] = THERMAL_CHARGER,
+	[TEMP_SENSOR_4_GPU_FBVDD] = THERMAL_GPU,
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
diff --git a/board/hades/usbc_config.c b/board/hades/usbc_config.c
new file mode 100644
index 0000000000..d8df38c6b6
--- /dev/null
+++ b/board/hades/usbc_config.c
@@ -0,0 +1,422 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi.h"
+#include "charge_ramp.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/bc12/pi3usb9201_public.h"
+#include "driver/ppc/tcpci_ppc.h"
+#include "driver/retimer/pi3dpx1207.h"
+#include "driver/retimer/ps8818_public.h"
+#include "driver/tcpm/anx7406.h"
+#include "driver/tcpm/nct38xx.h"
+#include "driver/tcpm/tcpci.h"
+#include "ec_commands.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "system.h"
+#include "task.h"
+#include "task_id.h"
+#include "timer.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+/* USBC TCPC configuration */
+const struct tcpc_config_t tcpc_config[] = {
+	[USBC_PORT_C0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0_TCPC,
+			/* Circuit 1 (p1 = 0x70, p2 = 0x74) */
+			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+	},
+	[USBC_PORT_C1] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C1_TCPC,
+			.addr_flags = ANX7406_TCPC0_I2C_ADDR_FLAGS,
+		},
+		.drv = &anx7406_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
+BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
+
+/******************************************************************************/
+/* USB-A charging control */
+
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_PP5000_USBA_R,
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
+
+/******************************************************************************/
+
+/* USBC PPC configuration */
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_PPC,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		.drv = &tcpci_ppc_drv,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C1_PPC,
+		.i2c_addr_flags = ANX7406_TCPC0_I2C_ADDR_FLAGS,
+		.drv = &tcpci_ppc_drv,
+	},
+};
+
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+const static struct ps8818_reg_val equalizer_default_table[] = {
+	{
+		.reg = PS8818_REG1_APTX1EQ_10G_LEVEL,
+		.mask = PS8818_EQ_LEVEL_UP_MASK,
+		.val = PS8818_EQ_LEVEL_UP_19DB,
+	},
+	{
+		.reg = PS8818_REG1_APTX2EQ_10G_LEVEL,
+		.mask = PS8818_EQ_LEVEL_UP_MASK,
+		.val = PS8818_EQ_LEVEL_UP_19DB,
+	},
+	{
+		.reg = PS8818_REG1_APTX1EQ_5G_LEVEL,
+		.mask = PS8818_EQ_LEVEL_UP_MASK,
+		.val = PS8818_EQ_LEVEL_UP_19DB,
+	},
+	{
+		.reg = PS8818_REG1_APTX2EQ_5G_LEVEL,
+		.mask = PS8818_EQ_LEVEL_UP_MASK,
+		.val = PS8818_EQ_LEVEL_UP_19DB,
+	},
+	{
+		.reg = PS8818_REG1_RX_PHY,
+		.mask = PS8818_RX_INPUT_TERM_MASK,
+		.val = PS8818_RX_INPUT_TERM_112_OHM,
+	},
+};
+
+#define NUM_EQ_DEFAULT_ARRAY ARRAY_SIZE(equalizer_default_table)
+
+int board_ps8818_mux_set(const struct usb_mux *me, mux_state_t mux_state)
+{
+	int rv = EC_SUCCESS;
+	int i;
+
+	/* USB specific config */
+	if (mux_state & USB_PD_MUX_USB_ENABLED) {
+		/* Boost the USB gain */
+		for (i = 0; i < NUM_EQ_DEFAULT_ARRAY; i++)
+			rv |= ps8818_i2c_field_update8(
+				me, PS8818_REG_PAGE1,
+				equalizer_default_table[i].reg,
+				equalizer_default_table[i].mask,
+				equalizer_default_table[i].val);
+	}
+
+	/* DP specific config */
+	if (mux_state & USB_PD_MUX_DP_ENABLED) {
+		/* Boost the DP gain */
+		rv |= ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					       PS8818_REG1_DPEQ_LEVEL,
+					       PS8818_DPEQ_LEVEL_UP_MASK,
+					       PS8818_DPEQ_LEVEL_UP_19DB);
+	}
+
+	return rv;
+}
+
+const static struct usb_mux_chain usbc2_ps8818 = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.i2c_port = I2C_PORT_USB_C1_TCPC,
+			.i2c_addr_flags = PS8818_I2C_ADDR0_FLAGS,
+			.driver = &ps8818_usb_retimer_driver,
+			.board_set = &board_ps8818_mux_set,
+		},
+};
+
+const struct pi3dpx1207_usb_control pi3dpx1207_controls[] = {
+	[USBC_PORT_C0] = {
+		.dp_enable_gpio = GPIO_USB_C0_IN_HPD,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pi3dpx1207_controls) == 1);
+
+const struct usb_mux_chain usbc0_pi3dpx1207_usb_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.i2c_port = I2C_PORT_USB_C0_TCPC,
+			.i2c_addr_flags = PI3DPX1207_I2C_ADDR_FLAGS,
+			.driver = &pi3dpx1207_usb_retimer,
+		},
+};
+
+/* USBC mux configuration - Alder Lake includes internal mux */
+const struct usb_mux_chain usb_muxes[] = {
+	[USBC_PORT_C0] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc0_pi3dpx1207_usb_retimer,
+	},
+	[USBC_PORT_C1] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc2_ps8818,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
+
+/* BC1.2 charger detect configuration */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C1_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
+
+#ifdef CONFIG_CHARGE_RAMP_SW
+
+#define BC12_MIN_VOLTAGE 4400
+
+/**
+ * Return true if VBUS is too low
+ */
+int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
+{
+	int voltage;
+
+	if (charger_get_vbus_voltage(port, &voltage))
+		voltage = 0;
+
+	if (voltage == 0) {
+		CPRINTS("%s: must be disconnected", __func__);
+		return 1;
+	}
+
+	if (voltage < BC12_MIN_VOLTAGE) {
+		CPRINTS("%s: port %d: vbus %d lower than %d", __func__, port,
+			voltage, BC12_MIN_VOLTAGE);
+		return 1;
+	}
+
+	return 0;
+}
+
+#endif /* CONFIG_CHARGE_RAMP_SW */
+
+void board_reset_pd_mcu(void)
+{
+	gpio_set_level(GPIO_USB_C0_TCPC_RST_ODL, 0);
+
+	/*
+	 * delay for power-on to reset-off and min. assertion time
+	 */
+	msleep(NCT38XX_RESET_HOLD_DELAY_MS);
+
+	gpio_set_level(GPIO_USB_C0_TCPC_RST_ODL, 1);
+
+	nct38xx_reset_notify(USBC_PORT_C0);
+
+	/* wait for chips to come up */
+	if (NCT3808_RESET_POST_DELAY_MS != 0)
+		msleep(NCT3808_RESET_POST_DELAY_MS);
+}
+
+int board_tcpc_post_init(int port)
+{
+	int rv;
+
+	if (port != USBC_PORT_C0)
+		return EC_SUCCESS;
+
+	/* Disable P2 on C0 */
+	rv = i2c_write16(tcpc_config[port].i2c_info.port,
+			 NCT38XX_I2C_ADDR2_1_FLAGS, TCPC_REG_ALERT_MASK,
+			 TCPC_REG_ALERT_NONE);
+	rv |= i2c_write16(tcpc_config[port].i2c_info.port,
+			  NCT38XX_I2C_ADDR2_1_FLAGS, TCPC_REG_RX_DETECT,
+			  TCPC_REG_RX_DETECT_NONE);
+	rv |= i2c_write16(tcpc_config[port].i2c_info.port,
+			  NCT38XX_I2C_ADDR2_1_FLAGS, TCPC_REG_COMMAND,
+			  TCPC_REG_COMMAND_DISABLE_VBUS_DETECT);
+	if (rv)
+		CPRINTS("C0: Failed to disable P2 (0x%x)", rv);
+
+	return rv;
+}
+
+static void board_tcpc_init(void)
+{
+	/* Don't reset TCPCs after initial reset */
+	if (!system_jumped_late())
+		board_reset_pd_mcu();
+
+	board_tcpc_post_init(USBC_PORT_C0);
+
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
+
+	/* Enable BC1.2 interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_0;
+
+	if (gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
+
+int ppc_get_alert_status(int port)
+{
+	if (port == USBC_PORT_C0)
+		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
+
+	if (port == USBC_PORT_C1)
+		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
+
+	return 0;
+}
+
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C1);
+		break;
+	default:
+		break;
+	}
+}
+
+void bc12_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_BC12_INT_ODL:
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+		break;
+	case GPIO_USB_C1_BC12_INT_ODL:
+		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+		break;
+	default:
+		break;
+	}
+}
+
+static void ppc_handle_interrupt(int port)
+{
+	/*
+	 * Ignore false positives (which may happen when we're already
+	 * disconnected).
+	 */
+	if (!ppc_chips[port].drv->is_sourcing_vbus(port))
+		return;
+
+	/*
+	 * If this is triggered by AOZ15333, it's either over current, short
+	 * circuit, or over temperature. If this is triggered by AOZ13937, it's
+	 * either over temperature, over voltage, or reverse current.
+	 */
+	ppc_prints("C%d: Vbus OC/OT/SC/OV/RC", port);
+	pd_handle_overcurrent(port);
+}
+
+static atomic_t irq_pending; /* Bitmask of ports signaling an interrupt. */
+
+static void ppc_irq_deferred(void)
+{
+	uint32_t pending = atomic_clear(&irq_pending);
+
+	for (int i = 0; i < board_get_usb_pd_port_count(); i++)
+		if (pending & BIT(i))
+			ppc_handle_interrupt(i);
+}
+DECLARE_DEFERRED(ppc_irq_deferred);
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		atomic_or(&irq_pending, BIT(0));
+		break;
+	case GPIO_USB_C1_PPC_INT_ODL:
+		atomic_or(&irq_pending, BIT(1));
+		break;
+	default:
+		break;
+	}
+	hook_call_deferred(&ppc_irq_deferred_data, 0);
+}
+
+void retimer_interrupt(enum gpio_signal signal)
+{
+}
+
+__override bool board_is_dts_port(int port)
+{
+	return port == USBC_PORT_C0;
+}
+
+__override bool board_is_tbt_usb4_port(int port)
+{
+	return false;
+}
+
+__override enum tbt_compat_cable_speed board_get_max_tbt_speed(int port)
+{
+	if (!board_is_tbt_usb4_port(port))
+		return TBT_SS_RES_0;
+
+	return TBT_SS_TBT_GEN3;
+}
diff --git a/board/hades/usbc_config.h b/board/hades/usbc_config.h
new file mode 100644
index 0000000000..fa3c5d241b
--- /dev/null
+++ b/board/hades/usbc_config.h
@@ -0,0 +1,21 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Hades board-specific USB-C configuration */
+
+#ifndef __CROS_EC_USBC_CONFIG_H
+#define __CROS_EC_USBC_CONFIG_H
+
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
+
+struct ps8818_reg_val {
+	uint8_t reg;
+	uint8_t mask;
+	uint16_t val;
+};
+
+#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/hades/vif_override.xml b/board/hades/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/hades/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/hadoken/board.c b/board/hadoken/board.c
deleted file mode 100644
index d9c8ed322f..0000000000
--- a/board/hadoken/board.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#include "gpio.h"
-#include "registers.h"
-#include "util.h"
-
-
-/* To define the gpio_list[] instance. */
-#include "gpio_list.h"
-
diff --git a/board/hadoken/board.h b/board/hadoken/board.h
deleted file mode 100644
index e8d71b7ee8..0000000000
--- a/board/hadoken/board.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Hadoken board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#ifndef __ASSEMBLER__
-
-#undef CONFIG_FLASH /* TODO: implement me */
-#undef CONFIG_FLASH_PHYSICAL /* TODO: implement me */
-#undef CONFIG_FMAP /* TODO: implement me */
-#undef CONFIG_WATCHDOG
-#undef CONFIG_LID_SWITCH
-
-/*
- *  nRF51 board specific configuration.
- */
-#define NRF51_UART_TX_PIN 24
-#define NRF51_UART_RX_PIN 28
-
-#define BATTERY_VOLTAGE_MAX         4425 /* mV */
-#define BATTERY_VOLTAGE_NORMAL      3800 /* mV */
-#define BATTERY_VOLTAGE_MIN         3000 /* mV */
-
-#define CONFIG_BLUETOOTH_LE
-#define CONFIG_BLUETOOTH_LE_STACK
-#define CONFIG_BLUETOOTH_LE_RADIO_TEST
-#define CONFIG_BLUETOOTH_LL_DEBUG
-#define CONFIG_BLUETOOTH_HCI_DEBUG
-
-#include "gpio_signal.h"
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
-
diff --git a/board/hadoken/build.mk b/board/hadoken/build.mk
deleted file mode 100644
index b2fee56f23..0000000000
--- a/board/hadoken/build.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-# -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-# the IC is Nordic nRF51822
-CHIP:=nrf51
-CHIP_FAMILY:=nrf51x22
-CHIP_VARIANT:=nrf51822
-
-# Hadoken does not support scratchpad
-test-list-y=
-
-board-y=board.o
diff --git a/board/hadoken/ec.tasklist b/board/hadoken/ec.tasklist
deleted file mode 100644
index 0bb461ecb8..0000000000
--- a/board/hadoken/ec.tasklist
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(BLE_LL, bluetooth_ll_task, NULL, TASK_STACK_SIZE)
-
diff --git a/board/hadoken/gpio.inc b/board/hadoken/gpio.inc
deleted file mode 100644
index ac4127992c..0000000000
--- a/board/hadoken/gpio.inc
+++ /dev/null
@@ -1,59 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-#define GPIO_KB_INPUT  (GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH)
-#define GPIO_KB_OUTPUT GPIO_ODR_HIGH
-
-/* Keyboard inputs */
-/*
- * TODO(yjlou): call keyboard_raw_gpio_interrupt() in chip/nrf51/keyboard_raw.c
- */
-GPIO(KB_IN00, PIN(0, 6),  GPIO_KB_INPUT)
-GPIO(KB_IN01, PIN(0, 23), GPIO_KB_INPUT)
-GPIO(KB_IN02, PIN(0, 1),  GPIO_KB_INPUT)
-GPIO(KB_IN03, PIN(0, 4),  GPIO_KB_INPUT)
-GPIO(KB_IN04, PIN(0, 0),  GPIO_KB_INPUT)
-GPIO(KB_IN05, PIN(0, 29), GPIO_KB_INPUT)
-GPIO(KB_IN06, PIN(0, 22), GPIO_KB_INPUT)
-GPIO(KB_IN07, PIN(0, 25), GPIO_KB_INPUT)
-
-/* Other inputs */
-GPIO(LID_PRESENT_L, PIN(0, 30), GPIO_INPUT)    /* Hall sensor */
-
-/* Useful for test software */
-GPIO(IND_CHRG_DISABLE, PIN(0, 20), GPIO_INPUT)
-
-/* Outputs */
-GPIO(KB_OUT00, PIN(0, 2),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT01, PIN(0, 10), GPIO_KB_OUTPUT)
-GPIO(KB_OUT02, PIN(0, 7),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT03, PIN(0, 5),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT04, PIN(0, 3),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT05, PIN(0, 9),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT06, PIN(0, 8),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT07, PIN(0, 27), GPIO_KB_OUTPUT)
-GPIO(KB_OUT08, PIN(0, 18), GPIO_KB_OUTPUT)
-GPIO(KB_OUT09, PIN(0, 16), GPIO_KB_OUTPUT)
-GPIO(KB_OUT10, PIN(0, 12), GPIO_KB_OUTPUT)
-GPIO(KB_OUT11, PIN(0, 15), GPIO_KB_OUTPUT)
-GPIO(KB_OUT12, PIN(0, 11), GPIO_KB_OUTPUT)
-
-/* SPI */
-GPIO(MCU_SPI_MOSI, PIN(0, 13), GPIO_OUTPUT)
-GPIO(MCU_SPI_MISO, PIN(0, 14), GPIO_INPUT)
-GPIO(MCU_SPI_SCLK, PIN(0, 17), GPIO_OUTPUT)
-GPIO(MCU_SPI_CS_L, PIN(0, 19), GPIO_OUT_HIGH)
-
-/* VBATT_SENSE */
-GPIO(VBATT_SENSE, PIN(0, 26), GPIO_ANALOG)
-GPIO(VBATT_SENSE_EN, PIN(0, 21), GPIO_OUT_LOW)
-
-/* Unimplemented */
-UNIMPLEMENTED(ENTERING_RW)
diff --git a/board/halvor/battery.c b/board/halvor/battery.c
deleted file mode 100644
index 828220fd49..0000000000
--- a/board/halvor/battery.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Volteer battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* AEC AEC335181 Battery Information */
-	/*
-	 * Battery info provided by ODM on b/162908664, comment #4
-	 */
-	[BATTERY_AEC] = {
-		.fuel_gauge = {
-			.manuf_name = "AEC",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8700, /* mV */
-			.voltage_normal		= 7600, /* mV */
-			.voltage_min		= 6000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 50,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_AEC;
diff --git a/board/halvor/board.c b/board/halvor/board.c
deleted file mode 100644
index fc12ccfb85..0000000000
--- a/board/halvor/board.c
+++ /dev/null
@@ -1,528 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer board-specific configuration */
-#include "accelgyro.h"
-#include "assert.h"
-#include "bb_retimer.h"
-#include "button.h"
-#include "common.h"
-#include "cbi_ec_fw_config.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/als_tcs3400.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/ppc/syv682x.h"
-#include "driver/sync.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/tusb422.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "tablet_mode.h"
-#include "uart.h"
-#include "usb_pd_tbt.h"
-#include "usbc_ppc.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "usb_mux.h"
-#include "util.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/* Keyboard scan setting */
-struct keyboard_scan_config keyscan_config = {
-	/* Increase from 50 us, because KSO_02 passes through the H1. */
-	.output_settle_us = 80,
-	/* Other values should be the same as the default configuration. */
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf4, 0xff,
-		0xa0, 0xff, 0xfe, 0x41, 0xfa, 0xc0, 0x02,
-		0x08, /* full set */
-	},
-};
-
-/******************************************************************************/
-static const struct ec_response_keybd_config halvor_kb = {
-	.num_top_row_keys = 10,
-	.action_keys = {
-		TK_BACK,		/* T1 */
-		TK_REFRESH,		/* T2 */
-		TK_FULLSCREEN,		/* T3 */
-		TK_OVERVIEW,		/* T4 */
-		TK_BRIGHTNESS_DOWN,	/* T5 */
-		TK_BRIGHTNESS_UP,	/* T6 */
-		TK_PLAY_PAUSE,		/* T7 */
-		TK_VOL_MUTE,		/* T8 */
-		TK_VOL_DOWN,		/* T9 */
-		TK_VOL_UP,		/* T10 */
-	},
-	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
-};
-
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
-{
-	return &halvor_kb;
-}
-
-/*
- * FW_CONFIG defaults for Halvor if the CBI data is not initialized.
- */
-union volteer_cbi_fw_config fw_config_defaults = {
-	/* Set all FW_CONFIG fields default to 0 */
-	.raw_value = 0,
-};
-
-static void board_init(void)
-{
-	/* Illuminate motherboard and daughter board LEDs equally to start. */
-	pwm_enable(PWM_CH_LED4_SIDESEL, 1);
-	pwm_set_duty(PWM_CH_LED4_SIDESEL, 50);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-__override enum tbt_compat_cable_speed board_get_max_tbt_speed(int port)
-{
-	/* Routing length exceeds 205mm prior to connection to re-timer */
-	if (port == USBC_PORT_C1)
-		return TBT_SS_U32_GEN1_GEN2;
-
-	/*
-	 * Thunderbolt-compatible mode not supported
-	 *
-	 * TODO (b/153995632): All the USB-C ports need to support same speed.
-	 * Need to fix once USB-C feature set is known for Halvor.
-	 */
-	return TBT_SS_RES_0;
-}
-
-__override bool board_is_tbt_usb4_port(int port)
-{
-	/*
-	 * On the volteer reference board 1 only port 1 supports TBT & USB4
-	 *
-	 * TODO (b/153995632): All the USB-C ports need to support same
-	 * features. Need to fix once USB-C feature set is known for Halvor.
-	 */
-	return port == USBC_PORT_C1;
-}
-
-/******************************************************************************/
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_0_SCL,
-		.sda = GPIO_EC_I2C_0_SDA,
-	},
-	{
-		.name = "usb_c0",
-		.port = I2C_PORT_USB_C0,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C_1_SCL,
-		.sda = GPIO_EC_I2C_1_SDA,
-	},
-	{
-		.name = "usb_c1",
-		.port = I2C_PORT_USB_C1,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C_2_SCL,
-		.sda = GPIO_EC_I2C_2_SDA,
-	},
-	{
-		.name = "usb_bb_retimer",
-		.port = I2C_PORT_USB_BB_RETIMER,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C_3_SCL,
-		.sda = GPIO_EC_I2C_3_SDA,
-	},
-	{
-		.name = "usb_c2",
-		.port = I2C_PORT_USB_C2,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C_4_SCL,
-		.sda = GPIO_EC_I2C_4_SDA,
-	},
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C_5_SCL,
-		.sda = GPIO_EC_I2C_5_SDA,
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_7_SCL,
-		.sda = GPIO_EC_I2C_7_SDA,
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* PWM configuration */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED1_BLUE] = {
-		.channel = 2,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 2400,
-	},
-	[PWM_CH_LED2_GREEN] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 2400,
-	},
-	[PWM_CH_LED3_RED] = {
-		.channel = 1,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 2400,
-	},
-	[PWM_CH_LED4_SIDESEL] = {
-		.channel = 7,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		/* Run at a higher frequency than the color PWM signals to avoid
-		 * timing-based color shifts.
-		 */
-		.freq = 4800,
-	},
-	[PWM_CH_FAN] = {
-		.channel = 5,
-		.flags = PWM_CONFIG_OPEN_DRAIN,
-		.freq = 25000
-	},
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = 0,
-		/*
-		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
-		 * flicker. Higher frequencies consume similar average power to
-		 * lower PWM frequencies, but higher frequencies record a much
-		 * lower maximum power.
-		 */
-		.freq = 2400,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/******************************************************************************/
-/* EC thermal management configuration */
-
-/*
- * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
- * 130 C.  However, sensor is located next to DDR, so we need to use the lower
- * DDR temperature limit (85 C)
- */
-const static struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(35),
-	.temp_fan_max = C_TO_K(50),
-};
-
-/*
- * Inductor limits - used for both charger and PP3300 regulator
- *
- * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
- *
- * Charger max recommended temperature 100C, max absolute temperature 125C
- * PP3300 regulator: operating range -40 C to 145 C
- *
- * Inductors: limit of 125c
- * PCB: limit is 80c
- */
-const static struct ec_thermal_config thermal_inductor = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(55),
-};
-
-
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_CHARGER]			= thermal_inductor,
-	[TEMP_SENSOR_2_PP3300_REGULATOR]	= thermal_inductor,
-	[TEMP_SENSOR_3_DDR_SOC]			= thermal_cpu,
-	[TEMP_SENSOR_4_FAN]			= thermal_cpu,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-/******************************************************************************/
-void halvor_tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_TCPC_INT_ODL:
-		port = USBC_PORT_C0;
-		break;
-	case GPIO_USB_C1_TCPC_INT_ODL:
-		port = USBC_PORT_C1;
-		break;
-	case GPIO_USB_C2_TCPC_INT_ODL:
-		port = USBC_PORT_C2;
-		break;
-	default:
-		return;
-	}
-
-	ASSERT(port != -1);
-	schedule_deferred_pd_interrupt(port);
-}
-
-void halvor_ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C0);
-		break;
-	case GPIO_USB_C1_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C1);
-		break;
-	case GPIO_USB_C2_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C2);
-		break;
-	default:
-		break;
-	}
-}
-
-void halvor_bc12_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
-		break;
-	case GPIO_USB_C1_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12, 0);
-		break;
-	case GPIO_USB_C2_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P2, USB_CHG_EVENT_BC12, 0);
-		break;
-
-	default:
-		break;
-	}
-}
-
-void board_reset_pd_mcu(void)
-{
-	/* TODO (b/153705222): Need to implement three USB-C function */
-}
-
-__override void board_cbi_init(void)
-{
-	/* TODO (b/153705222): Check FW_CONFIG for USB DB options */
-}
-
-/******************************************************************************/
-/* USBC PPC configuration */
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-	},
-	[USBC_PORT_C2] = {
-		.i2c_port = I2C_PORT_USB_C2,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/******************************************************************************/
-/* BC1.2 charger detect configuration */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	[USBC_PORT_C2] = {
-		.i2c_port = I2C_PORT_USB_C2,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC TCPC configuration */
-struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
-		},
-		.drv = &tusb422_tcpm_drv,
-		.usb23 = USBC_PORT_0_USB2_NUM | (USBC_PORT_0_USB3_NUM << 4),
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C1,
-			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
-		},
-		.drv = &tusb422_tcpm_drv,
-		.usb23 = USBC_PORT_1_USB2_NUM | (USBC_PORT_1_USB3_NUM << 4),
-	},
-	[USBC_PORT_C2] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C2,
-			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
-		},
-		.drv = &tusb422_tcpm_drv,
-		.usb23 = USBC_PORT_2_USB2_NUM | (USBC_PORT_2_USB3_NUM << 4),
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC mux configuration - Tiger Lake includes internal mux */
-struct usb_mux usbc0_usb4_db_retimer = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &bb_usb_retimer,
-	.i2c_port = I2C_PORT_USB_1_MIX,
-	.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
-};
-struct usb_mux usbc1_usb4_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &bb_usb_retimer,
-	.i2c_port = I2C_PORT_USB_1_MIX,
-	.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
-};
-struct usb_mux usbc2_usb4_db_retimer = {
-	.usb_port = USBC_PORT_C2,
-	.driver = &bb_usb_retimer,
-	.i2c_port = I2C_PORT_USB_1_MIX,
-	.i2c_addr_flags = USBC_PORT_C2_BB_RETIMER_I2C_ADDR,
-};
-struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc0_usb4_db_retimer,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc1_usb4_db_retimer,
-	},
-	[USBC_PORT_C2] = {
-		.usb_port = USBC_PORT_C2,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc2_usb4_db_retimer,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-struct bb_usb_control bb_controls[] = {
-	[USBC_PORT_C0] = {
-		.usb_ls_en_gpio = GPIO_USB_C0_LS_EN,
-		.retimer_rst_gpio = GPIO_USB_C0_RT_RST_ODL,
-	},
-	[USBC_PORT_C1] = {
-		.usb_ls_en_gpio = GPIO_USB_C1_LS_EN,
-		.retimer_rst_gpio = GPIO_USB_C1_RT_RST_ODL,
-	},
-	[USBC_PORT_C2] = {
-		.usb_ls_en_gpio = GPIO_USB_C2_LS_EN,
-		.retimer_rst_gpio = GPIO_USB_C2_RT_RST_ODL,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(bb_controls) == USBC_PORT_COUNT);
-
-static void board_usb_chip_init(void)
-{
-	/* Don't reset TCPCs after initial reset */
-	if (!system_jumped_late())
-		board_reset_pd_mcu();
-
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C2_PPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C2_TCPC_INT_ODL);
-
-	/* Enable BC1.2 interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C2_BC12_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_usb_chip_init, HOOK_PRIO_INIT_CHIPSET);
-
-/******************************************************************************/
-/* TCPC support routines */
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	/*
-	 * Check which port has the ALERT line set
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_0;
-	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_1;
-	if (!gpio_get_level(GPIO_USB_C2_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_2;
-
-	return status;
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (port == USBC_PORT_C0)
-		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
-	else if (port == USBC_PORT_C1)
-		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
-	else
-		return gpio_get_level(GPIO_USB_C2_PPC_INT_ODL) == 0;
-}
-
diff --git a/board/halvor/board.h b/board/halvor/board.h
deleted file mode 100644
index b1db5627fa..0000000000
--- a/board/halvor/board.h
+++ /dev/null
@@ -1,191 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Baseboard features */
-#include "baseboard.h"
-
-/* Optional features */
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
-
-#define CONFIG_POWER_BUTTON
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* LED defines */
-#define CONFIG_LED_POWER_LED
-#define CONFIG_LED_ONOFF_STATES
-#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
-
-/* Keyboard features */
-
-/* Sensors */
-/* BMA253 accelerometer in base */
-#define CONFIG_ACCEL_BMA255
-
-/* TCS3400 ALS */
-#define CONFIG_ALS
-#define ALS_COUNT		1
-#define CONFIG_ALS_TCS3400
-#define CONFIG_ALS_TCS3400_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS)
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
-	(BIT(LID_ACCEL) | BIT(CLEAR_ALS))
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_PORT_MAX_COUNT			3
-
-/*
- * USB-C port's USB2 & USB3 mapping from schematics
- * USB2 numbering on PCH - 1 to n
- * USB3 numbering on AP - 0 to n (PMC's USB3 numbering for MUX
- * configuration is - 1 to n hence add +1)
- */
-#define USBC_PORT_0_USB2_NUM	2
-#define USBC_PORT_0_USB3_NUM	1
-#define USBC_PORT_1_USB2_NUM	4
-#define USBC_PORT_1_USB3_NUM	2
-#define USBC_PORT_2_USB2_NUM	6
-#define USBC_PORT_2_USB3_NUM	3
-
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	250000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
-
-/*
- * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
- * cables only support up to 60W.
- */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		65000
-#define PD_MAX_CURRENT_MA	3250
-#define PD_MAX_VOLTAGE_MV	20000
-
-/* Enabling Thunderbolt-compatible mode */
-#define CONFIG_USB_PD_TBT_COMPAT_MODE
-
-/* Enabling USB4 mode */
-#define CONFIG_USB_PD_USB4
-#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR	0x40
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x41
-#define USBC_PORT_C2_BB_RETIMER_I2C_ADDR	0x42
-
-/* USB Type A Features */
-
-/* USBC PPC*/
-#define CONFIG_USBC_PPC_SYV682X		/* USBC port C0 C1 C2 */
-
-/* BC 1.2 */
-
-/* Volume Button feature */
-
-/* Fan features */
-
-/* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		5
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SYS_PWROK		GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PG_EC_DSW_PWROK		GPIO_DSW_PWROK
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD		GPIO_PG_EC_RSMRST_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_USB_C0_BC12_INT_ODL	GPIO_USB_C0_MIX_INT_ODL
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-#define GPIO_USB_C2_BC12_INT_ODL	GPIO_USB_C2_MIX_INT_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE_L
-
-#undef CONFIG_FANS
-#undef CONFIG_VOLUME_BUTTONS
-
-/* I2C Bus Configuration */
-#define CONFIG_I2C
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_BB_RETIMER	NPCX_I2C_PORT3_0
-#define I2C_PORT_USB_C2		NPCX_I2C_PORT4_1
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
-#define I2C_PORT_USB_1_MIX	I2C_PORT_USB_BB_RETIMER
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-#define CONFIG_I2C_MASTER
-
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum battery_type {
-	BATTERY_AEC,
-	BATTERY_TYPE_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_LED1_BLUE = 0,
-	PWM_CH_LED2_GREEN,
-	PWM_CH_LED3_RED,
-	PWM_CH_LED4_SIDESEL,
-	PWM_CH_FAN,
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL = 0,
-	CLEAR_ALS,
-	RGB_ALS,
-	SENSOR_COUNT,
-};
-
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_C2,
-	USBC_PORT_COUNT
-};
-
-/* Definition for Halvor USB PD interrupt handlers. */
-void halvor_tcpc_alert_event(enum gpio_signal signal);
-void halvor_ppc_interrupt(enum gpio_signal signal);
-void halvor_bc12_interrupt(enum gpio_signal signal);
-
-void board_reset_pd_mcu(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/halvor/build.mk b/board/halvor/build.mk
deleted file mode 100644
index b78172d3cf..0000000000
--- a/board/halvor/build.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
-BASEBOARD:=volteer
-
-board-y=board.o
-board-y+=battery.o
-board-y+=led.o
-board-y+=sensors.o
diff --git a/board/halvor/ec.tasklist b/board/halvor/ec.tasklist
deleted file mode 100644
index 936a4276e6..0000000000
--- a/board/halvor/ec.tasklist
+++ /dev/null
@@ -1,29 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P2, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C2, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C2, pd_interrupt_handler_task, 2, TASK_STACK_SIZE)
diff --git a/board/halvor/gpio.inc b/board/halvor/gpio.inc
deleted file mode 100644
index 7631415318..0000000000
--- a/board/halvor/gpio.inc
+++ /dev/null
@@ -1,180 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(EC_LID_OPEN,          PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(EC_WP_L,              PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(H1_EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
-GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_RSMRST_ODL,     PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(DSW_PWROK,            PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4),  GPIO_INT_BOTH, power_signal_interrupt)
-
-/* Sensor Interrupts */
-GPIO_INT(EC_ALS_RGB_INT_L,     PIN(D, 4), GPIO_INT_FALLING, tcs3400_interrupt)
-GPIO_INT(TABLET_MODE_L,        PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(E, 0), GPIO_INT_BOTH, halvor_tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(A, 2), GPIO_INT_BOTH, halvor_tcpc_alert_event)
-GPIO_INT(USB_C2_TCPC_INT_ODL,	PIN(A, 0), GPIO_INT_BOTH, halvor_tcpc_alert_event)
-
-GPIO_INT(USB_C0_PPC_INT_ODL,	PIN(6, 2), GPIO_INT_BOTH, halvor_ppc_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(F, 5), GPIO_INT_BOTH, halvor_ppc_interrupt)
-GPIO_INT(USB_C2_PPC_INT_ODL,	PIN(A, 4), GPIO_INT_BOTH, halvor_ppc_interrupt)
-
-GPIO_INT(USB_C0_MIX_INT_ODL,	PIN(E, 4), GPIO_INT_BOTH, halvor_bc12_interrupt)
-GPIO_INT(USB_C1_MIX_INT_ODL,	PIN(0, 3), GPIO_INT_BOTH, halvor_bc12_interrupt)
-GPIO_INT(USB_C2_MIX_INT_ODL,	PIN(6, 1), GPIO_INT_BOTH, halvor_bc12_interrupt)
-
-/* HDMI interrupts */
-
-/* Volume button interrupts */
-
-/* Unused signals */
-GPIO(EN_PP1050_STG,		PIN(C, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(CPU_C10_GATE_L,		PIN(6, 7), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(EN_PP1050_ST_S0,		PIN(3, 4), GPIO_INPUT | GPIO_PULL_UP)
-/* Power Sequencing Signals */
-GPIO(EN_PP3300_A,              PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EN_PPVAR_VCCIN,	       PIN(4, 3), GPIO_OUT_LOW)
-GPIO(EN_PP5000_USB_AG,		PIN(A, 7), GPIO_OUT_HIGH)
-
-/* The EC does not buffer this signal on Halvor. */
-UNIMPLEMENTED(PCH_DSW_PWROK)
-UNIMPLEMENTED(EN_PP5000_A)
-
-/* Other wake sources */
-/*
- * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an
- * interrupt handler because it is automatically handled by the PSL.
- *
- * We need to lock the setting so this gpio can't be reconfigured to overdrive
- * the real reset signal. (This is the PSL input pin not the real reset pin).
- */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH |
-					   GPIO_HIB_WAKE_HIGH |
-					   GPIO_LOCKED)
-
-/* AP/PCH Signals */
-GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
-GPIO(EC_PCH_RSMRST_ODL,        PIN(A, 6), GPIO_ODR_LOW) /* TODO - b/140950085 - implement TGL sequencing requirement */
-GPIO(EC_PCH_PWR_BTN_ODL,       PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
-GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
-GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
-
-GPIO(EC_PCH_INT_ODL,           PIN(B, 0), GPIO_ODR_HIGH)
-
-/* USB and USBC Signals */
-GPIO(USB_C0_RT_RST_ODL,        PIN(6, 6), GPIO_ODR_LOW)
-GPIO(USB_C1_RT_RST_ODL,        PIN(8, 6), GPIO_ODR_LOW)
-GPIO(USB_C2_RT_RST_ODL,        PIN(9, 6), GPIO_ODR_LOW)
-
-GPIO(USB_C0_OC_ODL,            PIN(B, 1), GPIO_ODR_HIGH)
-GPIO(USB_C1_OC_ODL,            PIN(5, 0), GPIO_ODR_HIGH)
-GPIO(USB_C2_OC_ODL,            PIN(3, 2), GPIO_ODR_HIGH)
-
-
-
-/* Don't have a load switch for retimer */
-UNIMPLEMENTED(USB_C0_LS_EN)
-UNIMPLEMENTED(USB_C1_LS_EN)
-UNIMPLEMENTED(USB_C2_LS_EN)
-UNIMPLEMENTED(USB_C0_BC12_INT_ODL)
-UNIMPLEMENTED(USB_C1_BC12_INT_ODL)
-
-/* Other input pins */
-GPIO(CCD_MODE_ODL,		PIN(E, 5),  GPIO_INPUT)
-GPIO(EC_PROCHOT_IN_L,		PIN(F, 0),  GPIO_INPUT)
-GPIO(CHARGER_INT_L,		PIN(7, 3),  GPIO_INPUT)
-
-/* Other output pins */
-GPIO(EC_PPEXT_EN1,		PIN(C, 2), GPIO_OUT_HIGH)
-GPIO(EC_I2CBUFFER_EN,		PIN(9, 3), GPIO_OUT_LOW)
-GPIO(UART2_EC_RX,		PIN(7, 5), GPIO_OUT_LOW)
-
-/* LED Signals */
-GPIO(LED_1_L,		PIN(C, 4), GPIO_OUT_LOW)
-GPIO(LED_2_L,		PIN(C, 3), GPIO_OUT_LOW)
-
-/* Misc Signals */
-
-/*
- * eDP backlight - both PCH and EC have enable pins that must be high
- * for the backlight to turn on. Default state is high, and can be turned
- * off during sleep states.
- */
-GPIO(EC_EDP_BL_EN,             PIN(D, 3), GPIO_OUT_HIGH)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(EC_I2C_0_SCL,       PIN(B, 5), GPIO_INPUT)
-GPIO(EC_I2C_0_SDA,       PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_1_SCL,       PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_1_SDA,       PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C_2_SCL,       PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C_2_SDA,       PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C_3_SCL,       PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C_3_SDA,       PIN(D, 0), GPIO_INPUT)
-GPIO(EC_I2C_4_SCL,       PIN(F, 3), GPIO_INPUT)
-GPIO(EC_I2C_4_SDA,       PIN(F, 2), GPIO_INPUT)
-GPIO(EC_I2C_5_SCL,       PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_5_SDA,       PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C_7_SCL,       PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_7_SDA,       PIN(B, 2), GPIO_INPUT)
-
-/* Battery signals */
-GPIO(EC_BATT_PRES_ODL, 		PIN(E, 1), GPIO_INPUT)
-
-/* Physical HPD pins are not needed on EC as these are configured by PMC */
-GPIO(USB_C0_DP_HPD,		PIN(C, 6), GPIO_INPUT)
-GPIO(USB_C1_DP_HPD,		PIN(7, 0), GPIO_INPUT)
-GPIO(USB_C2_DP_HPD,		PIN(B, 7), GPIO_INPUT)
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, BIT(5) | BIT(4)), 0, MODULE_I2C, 0)                            /* I2C0 */
-ALTERNATE(PIN_MASK(9, BIT(0) | BIT(2) | BIT(1)), 0, MODULE_I2C, 0)                   /* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)                                     /* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, BIT(1) | BIT(0)), 0, MODULE_I2C, 0)                            /* I2C3 */
-ALTERNATE(PIN_MASK(F, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)                            /* I2C4 */
-ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)                            /* I2C5 */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)                            /* I2C7 */
-
-/* Fan signals */
-
-/* Keyboard pins */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_00-01 */
-GPIO(EC_KSO_02_INV, PIN(1, 7),                        GPIO_OUT_LOW)  /* KSO_02 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x0C), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_14-15 */
-ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)                     /* EC_KB_BL_PWM */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, BIT(5) | BIT(4)), 0, MODULE_UART, 0)                           /* UART from EC to Servo */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)                    /* GPIOD2 = EC_LID_OPEN */
-ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)  /* GPIO00 = ACOK_OD,
-                                                                       GPIO01 = H1_EC_PWR_BTN_ODL
-                                                                       GPIO02 = EC_RST_ODL */
-
diff --git a/board/halvor/led.c b/board/halvor/led.c
deleted file mode 100644
index 47753899bf..0000000000
--- a/board/halvor/led.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Halvor
- */
-
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-#include "chipset.h"
-
-#define LED_ON_LVL 1
-#define LED_OFF_LVL 0
-
-const int led_charge_lvl_1 = 10;
-
-const int led_charge_lvl_2 = 100;
-
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_S5]     = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC},
-					{LED_OFF,	     2 * LED_ONE_SEC} },
-};
-
-const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED,
-};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-void led_set_color_battery(enum ec_led_colors color)
-{
-	gpio_set_level(GPIO_LED_2_L,
-		(color == EC_LED_COLOR_AMBER) ? LED_ON_LVL : LED_OFF_LVL);
-}
-
-void led_set_color_power(enum ec_led_colors color)
-{
-	gpio_set_level(GPIO_LED_1_L,
-		(color == EC_LED_COLOR_WHITE) ? LED_ON_LVL : LED_OFF_LVL);
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED)
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-	else if (led_id == EC_LED_ID_POWER_LED)
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else
-			led_set_color_battery(LED_OFF);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
diff --git a/board/halvor/sensors.c b/board/halvor/sensors.c
deleted file mode 100644
index b2795ee904..0000000000
--- a/board/halvor/sensors.c
+++ /dev/null
@@ -1,170 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer family-specific sensor configuration */
-#include "common.h"
-#include "accelgyro.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/als_tcs3400.h"
-#include "driver/sync.h"
-#include "keyboard_scan.h"
-#include "hooks.h"
-#include "task.h"
-#include "util.h"
-
-/******************************************************************************/
-/* Sensors */
-static struct mutex g_lid_accel_mutex;
-
-/* BMA253 private data */
-static struct accelgyro_saved_data_t g_bma253_data;
-
-/* TCS3400 private data */
-static struct als_drv_data_t g_tcs3400_data = {
-	.als_cal.scale = 1,
-	.als_cal.uscale = 0,
-	.als_cal.offset = 0,
-	.als_cal.channel_scale = {
-		.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kc from VPD */
-		.cover_scale = ALS_CHANNEL_SCALE(1.0),     /* CT */
-	},
-};
-
-/*
- * TODO: b/146166425 need to calibrate ALS/RGB sensor. At default settings,
- * shining phone flashlight on sensor pegs all readings at 0xFFFF.
- */
-static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
-	.calibration.rgb_cal[X] = {
-		.offset = 0,
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kr */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		}
-	},
-	.calibration.rgb_cal[Y] = {
-		.offset = 0,
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kg */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		},
-	},
-	.calibration.rgb_cal[Z] = {
-		.offset = 0,
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kb */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		}
-	},
-	.calibration.irt = INT_TO_FP(1),
-	.saturation.again = TCS_DEFAULT_AGAIN,
-	.saturation.atime = TCS_DEFAULT_ATIME,
-};
-
-/* Rotation matrix for the lid accelerometer */
-/* TODO: b/146144170 - the accelerometer is on the motherboard for proto1
- * for testing. Once the sensor moves to the lid, the rotation matrix needs
- * to be updated for correct behavior.
- */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_lid_accel_mutex,
-		.drv_data = &g_bma253_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.default_range = 2, /* g, to support tablet mode */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-
-	[CLEAR_ALS] = {
-		.name = "Clear Light",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_TCS3400,
-		.type = MOTIONSENSE_TYPE_LIGHT,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &tcs3400_drv,
-		.drv_data = &g_tcs3400_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = TCS3400_I2C_ADDR_FLAGS,
-		.rot_standard_ref = NULL,
-		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
-		.min_frequency = TCS3400_LIGHT_MIN_FREQ,
-		.max_frequency = TCS3400_LIGHT_MAX_FREQ,
-		.config = {
-			/* Run ALS sensor in S0 */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 1000,
-			},
-		},
-	},
-
-	[RGB_ALS] = {
-		/*
-		 * RGB channels read by CLEAR_ALS and so the i2c port and
-		 * address do not need to be defined for RGB_ALS.
-		 */
-		.name = "RGB Light",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_TCS3400,
-		.type = MOTIONSENSE_TYPE_LIGHT_RGB,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &tcs3400_rgb_drv,
-		.drv_data = &g_tcs3400_rgb_data,
-		.rot_standard_ref = NULL,
-		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
-	},
-};
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/* ALS instances when LPC mapping is needed. Each entry directs to a sensor. */
-const struct motion_sensor_t *motion_als_sensors[] = {
-	&motion_sensors[CLEAR_ALS],
-};
-BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
-
-static void baseboard_sensors_init(void)
-{
-	/* Note - BMA253 interrupt unused by EC */
-
-	/* Enable interrupt for the TCS3400 color light sensor */
-	gpio_enable_interrupt(GPIO_EC_ALS_RGB_INT_L);
-}
-DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_DEFAULT);
diff --git a/board/hammer/battery.c b/board/hammer/battery.c
index 4025a08b14..df6a716cd7 100644
--- a/board/hammer/battery.c
+++ b/board/hammer/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,8 +13,8 @@
 #include "util.h"
 
 /* Shutdown mode parameter to write to manufacturer access register */
-#define SB_SHIP_MODE_REG	SB_MANUFACTURER_ACCESS
-#define SB_SHUTDOWN_DATA        0x0010
+#define SB_SHIP_MODE_REG SB_MANUFACTURER_ACCESS
+#define SB_SHUTDOWN_DATA 0x0010
 
 static const struct battery_info info = {
 	.voltage_max = 8800,
diff --git a/board/hammer/board.c b/board/hammer/board.c
index c6149a678c..2e46a636f3 100644
--- a/board/hammer/board.c
+++ b/board/hammer/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,8 +9,8 @@
 #include "common.h"
 #include "driver/charger/isl923x.h"
 #include "driver/led/lm3630a.h"
+#include "ec_ec_comm_server.h"
 #include "ec_version.h"
-#include "ec_ec_comm_slave.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "hwtimer.h"
@@ -28,18 +28,19 @@
 #include "system.h"
 #include "tablet_mode.h"
 #include "task.h"
-#include "touchpad.h"
 #include "timer.h"
+#include "touchpad.h"
 #include "update_fw.h"
 #include "usart-stm32f0.h"
-#include "usart_tx_dma.h"
 #include "usart_rx_dma.h"
+#include "usart_tx_dma.h"
 #include "usb_api.h"
 #include "usb_descriptor.h"
 #include "usb_i2c.h"
 #include "usb_spi.h"
 #include "util.h"
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 #ifdef SECTION_IS_RW
@@ -48,20 +49,21 @@
 #define CROS_EC_SECTION "RO"
 #endif
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 /******************************************************************************
  * Define the strings used in our USB descriptors.
  */
 const void *const usb_strings[] = {
-	[USB_STR_DESC]         = usb_string_desc,
-	[USB_STR_VENDOR]       = USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]      = USB_STRING_DESC("Hammer"),
-	[USB_STR_SERIALNO]     = 0,
-	[USB_STR_VERSION]      =
-			USB_STRING_DESC(CROS_EC_SECTION ":" CROS_EC_VERSION32),
-	[USB_STR_I2C_NAME]     = USB_STRING_DESC("I2C"),
-	[USB_STR_UPDATE_NAME]  = USB_STRING_DESC("Firmware update"),
+	[USB_STR_DESC] = usb_string_desc,
+	[USB_STR_VENDOR] = USB_STRING_DESC("Google LLC"),
+	[USB_STR_PRODUCT] = USB_STRING_DESC("Hammer"),
+	[USB_STR_SERIALNO] = 0,
+	[USB_STR_VERSION] =
+		USB_STRING_DESC(CROS_EC_SECTION ":" CROS_EC_VERSION32),
+	[USB_STR_SPI_NAME] = USB_STRING_DESC("SPI"),
+	[USB_STR_I2C_NAME] = USB_STRING_DESC("I2C"),
+	[USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"),
 #ifdef CONFIG_USB_ISOCHRONOUS
 	[USB_STR_HEATMAP_NAME] = USB_STRING_DESC("Heatmap"),
 #endif
@@ -77,24 +79,34 @@ BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
 #ifdef HAS_SPI_TOUCHPAD
 /* SPI devices */
 const struct spi_device_t spi_devices[] = {
-	[SPI_ST_TP_DEVICE_ID] = { CONFIG_SPI_TOUCHPAD_PORT, 2, GPIO_SPI1_NSS },
+	[SPI_ST_TP_DEVICE_ID] = { CONFIG_SPI_TOUCHPAD_PORT, 2, GPIO_SPI1_NSS,
+				  USB_SPI_ENABLED },
 };
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
-USB_SPI_CONFIG(usb_spi, USB_IFACE_I2C_SPI, USB_EP_I2C_SPI, 0);
 /* SPI interface is always enabled, no need to do anything. */
-void usb_spi_board_enable(struct usb_spi_config const *config) {}
-void usb_spi_board_disable(struct usb_spi_config const *config) {}
-#endif  /* !HAS_SPI_TOUCHPAD */
+void usb_spi_board_enable(void)
+{
+}
+void usb_spi_board_disable(void)
+{
+}
+#endif /* !HAS_SPI_TOUCHPAD */
 
 #ifdef CONFIG_I2C
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{"master", I2C_PORT_MASTER, 400,
-		GPIO_MASTER_I2C_SCL, GPIO_MASTER_I2C_SDA},
+	{ .name = "master",
+	  .port = I2C_PORT_MASTER,
+	  .kbps = 400,
+	  .scl = GPIO_MASTER_I2C_SCL,
+	  .sda = GPIO_MASTER_I2C_SDA },
 #ifdef BOARD_WAND
-	{"charger", I2C_PORT_CHARGER, 100,
-		GPIO_CHARGER_I2C_SCL, GPIO_CHARGER_I2C_SDA},
+	{ .name = "charger",
+	  .port = I2C_PORT_CHARGER,
+	  .kbps = 100,
+	  .scl = GPIO_CHARGER_I2C_SCL,
+	  .sda = GPIO_CHARGER_I2C_SDA },
 #endif
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
@@ -114,7 +126,7 @@ const struct charger_config_t chg_chips[] = {
 #ifdef HAS_BACKLIGHT
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	{STM32_TIM(TIM_KBLIGHT), STM32_TIM_CH(1), 0, KBLIGHT_PWM_FREQ},
+	{ STM32_TIM(TIM_KBLIGHT), STM32_TIM_CH(1), 0, KBLIGHT_PWM_FREQ },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 #endif /* HAS_BACKLIGHT */
@@ -125,8 +137,7 @@ int usb_i2c_board_is_enabled(void)
 	return !system_is_locked();
 }
 
-#ifdef CONFIG_KEYBOARD_BOARD_CONFIG
-struct keyboard_scan_config keyscan_config = {
+__override struct keyboard_scan_config keyscan_config = {
 	.output_settle_us = 50,
 	.debounce_down_us = 9 * MSEC,
 	.debounce_up_us = 30 * MSEC,
@@ -139,32 +150,27 @@ struct keyboard_scan_config keyscan_config = {
 	},
 };
 #endif
-#endif
 
 #if defined(BOARD_WAND) && defined(SECTION_IS_RW)
 struct consumer const ec_ec_usart_consumer;
 static struct usart_config const ec_ec_usart;
 
-struct queue const ec_ec_comm_slave_input = QUEUE_DIRECT(64, uint8_t,
-				ec_ec_usart.producer, ec_ec_usart_consumer);
-struct queue const ec_ec_comm_slave_output = QUEUE_DIRECT(64, uint8_t,
-				null_producer, ec_ec_usart.consumer);
+struct queue const ec_ec_comm_server_input =
+	QUEUE_DIRECT(64, uint8_t, ec_ec_usart.producer, ec_ec_usart_consumer);
+struct queue const ec_ec_comm_server_output =
+	QUEUE_DIRECT(64, uint8_t, null_producer, ec_ec_usart.consumer);
 
 struct consumer const ec_ec_usart_consumer = {
-	.queue = &ec_ec_comm_slave_input,
-	.ops   = &((struct consumer_ops const) {
-		.written = ec_ec_comm_slave_written,
+	.queue = &ec_ec_comm_server_input,
+	.ops = &((struct consumer_ops const){
+		.written = ec_ec_comm_server_written,
 	}),
 };
 
 static struct usart_config const ec_ec_usart =
-	USART_CONFIG(EC_EC_UART,
-		usart_rx_interrupt,
-		usart_tx_interrupt,
-		115200,
-		USART_CONFIG_FLAG_HDSEL,
-		ec_ec_comm_slave_input,
-		ec_ec_comm_slave_output);
+	USART_CONFIG(EC_EC_UART, usart_rx_interrupt, usart_tx_interrupt, 115200,
+		     USART_CONFIG_FLAG_HDSEL, ec_ec_comm_server_input,
+		     ec_ec_comm_server_output);
 #endif /* BOARD_WAND && SECTION_IS_RW */
 
 /******************************************************************************
@@ -184,8 +190,8 @@ static void board_init(void)
 
 #ifdef BOARD_WAND
 	/* USB to serial queues */
-	queue_init(&ec_ec_comm_slave_input);
-	queue_init(&ec_ec_comm_slave_output);
+	queue_init(&ec_ec_comm_server_input);
+	queue_init(&ec_ec_comm_server_output);
 
 	/* UART init */
 	usart_init(&ec_ec_usart);
@@ -196,10 +202,10 @@ static void board_init(void)
 #endif
 
 #ifdef HAS_SPI_TOUCHPAD
-	spi_enable(CONFIG_SPI_TOUCHPAD_PORT, 0);
+	spi_enable(&spi_devices[SPI_ST_TP_DEVICE_ID], 0);
 
 	/* Disable SPI passthrough when the system is locked */
-	usb_spi_enable(&usb_spi, system_is_locked());
+	usb_spi_enable(system_is_locked());
 
 	/* Set all four SPI pins to high speed */
 	/* pins B3/5, A15 */
@@ -214,8 +220,8 @@ static void board_init(void)
 
 	clock_wait_bus_cycles(BUS_APB, 1);
 	/* Enable SPI for touchpad */
-	gpio_config_module(MODULE_SPI_MASTER, 1);
-	spi_enable(CONFIG_SPI_TOUCHPAD_PORT, 1);
+	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
+	spi_enable(&spi_devices[SPI_ST_TP_DEVICE_ID], 1);
 #endif /* HAS_SPI_TOUCHPAD */
 }
 /* This needs to happen before PWM is initialized. */
@@ -271,9 +277,9 @@ static void board_tablet_mode_change(void)
 		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
 }
 DECLARE_HOOK(HOOK_TABLET_MODE_CHANGE, board_tablet_mode_change,
-		HOOK_PRIO_DEFAULT);
+	     HOOK_PRIO_DEFAULT);
 /* Run after tablet_mode_init. */
-DECLARE_HOOK(HOOK_INIT, board_tablet_mode_change, HOOK_PRIO_DEFAULT+1);
+DECLARE_HOOK(HOOK_INIT, board_tablet_mode_change, HOOK_PRIO_DEFAULT + 1);
 #endif
 
 /*
@@ -286,7 +292,7 @@ int board_get_entropy(void *buffer, int len)
 	uint8_t *data = buffer;
 	uint32_t start;
 	/* We expect one SOF per ms, so wait at most 2ms. */
-	const uint32_t timeout = 2*MSEC;
+	const uint32_t timeout = 2 * MSEC;
 
 	for (i = 0; i < len; i++) {
 		STM32_CRS_ICR |= STM32_CRS_ICR_SYNCOKC;
@@ -317,8 +323,9 @@ __override const char *board_read_serial(void)
 		int i;
 
 		for (i = 0; i < idlen && pos < sizeof(str); i++, pos += 2) {
-			snprintf(&str[pos], sizeof(str)-pos,
-				"%02x", id[i]);
+			if (snprintf(&str[pos], sizeof(str) - pos, "%02x",
+				     id[i]) < 0)
+				return NULL;
 		}
 	}
 
@@ -329,3 +336,68 @@ __override int board_write_serial(const char *serialno)
 {
 	return 0;
 }
+
+static const struct ec_response_keybd_config zed_kb = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,
+		TK_REFRESH,
+		TK_FULLSCREEN,
+		TK_OVERVIEW,
+		TK_SNAPSHOT,
+		TK_BRIGHTNESS_DOWN,
+		TK_BRIGHTNESS_UP,
+		TK_VOL_MUTE,
+		TK_VOL_DOWN,
+		TK_VOL_UP,
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+static const struct ec_response_keybd_config bland_kb = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,
+		TK_REFRESH,
+		TK_FULLSCREEN,
+		TK_OVERVIEW,
+		TK_BRIGHTNESS_DOWN,
+		TK_BRIGHTNESS_UP,
+		TK_MICMUTE,
+		TK_VOL_MUTE,
+		TK_VOL_DOWN,
+		TK_VOL_UP,
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+static const struct ec_response_keybd_config duck_kb = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,
+		TK_FORWARD,
+		TK_REFRESH,
+		TK_FULLSCREEN,
+		TK_OVERVIEW,
+		TK_BRIGHTNESS_DOWN,
+		TK_BRIGHTNESS_UP,
+		TK_VOL_MUTE,
+		TK_VOL_DOWN,
+		TK_VOL_UP,
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	if (IS_ENABLED(BOARD_ZED) || IS_ENABLED(BOARD_STAR) ||
+	    IS_ENABLED(BOARD_GELATIN))
+		return &zed_kb;
+	if (IS_ENABLED(BOARD_BLAND) || IS_ENABLED(BOARD_EEL))
+		return &bland_kb;
+	if (IS_ENABLED(BOARD_DUCK))
+		return &duck_kb;
+
+	return NULL;
+}
diff --git a/board/hammer/board.h b/board/hammer/board.h
index d1a7af0bfe..d5ab4699ac 100644
--- a/board/hammer/board.h
+++ b/board/hammer/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -46,28 +46,27 @@
 /* Do not use a dedicated PSTATE bank */
 #undef CONFIG_FLASH_PSTATE_BANK
 
-#define CONFIG_SHAREDLIB_SIZE	0
+#define CONFIG_SHAREDLIB_SIZE 0
 
-#define CONFIG_RO_MEM_OFF	0
-#define CONFIG_RO_STORAGE_OFF	0
-#define CONFIG_RO_SIZE		(44*1024)
+#define CONFIG_RO_MEM_OFF 0
+#define CONFIG_RO_STORAGE_OFF 0
+#define CONFIG_RO_SIZE (44 * 1024)
 
 /* EC rollback protection block */
 #define CONFIG_ROLLBACK_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
 #define CONFIG_ROLLBACK_SIZE CONFIG_FLASH_BANK_SIZE
 
-#define CONFIG_RW_MEM_OFF	(CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE)
-#define CONFIG_RW_STORAGE_OFF	0
-#define CONFIG_RW_SIZE		(CONFIG_FLASH_SIZE - \
-				(CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF))
+#define CONFIG_RW_MEM_OFF (CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE)
+#define CONFIG_RW_STORAGE_OFF 0
+#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE_BYTES - CONFIG_RW_MEM_OFF)
 
-#define CONFIG_EC_PROTECTED_STORAGE_OFF		CONFIG_RO_MEM_OFF
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE	CONFIG_RO_SIZE
-#define CONFIG_EC_WRITABLE_STORAGE_OFF		CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE		CONFIG_RW_SIZE
+#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF
+#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE
+#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE
 
-#define CONFIG_WP_STORAGE_OFF		CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE		CONFIG_EC_PROTECTED_STORAGE_SIZE
+#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
+#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
 
 /* The UART console is on USART1 (PA9/PA10) */
 #undef CONFIG_UART_CONSOLE
@@ -83,7 +82,7 @@
 #endif
 #define CONFIG_LTO
 #define CONFIG_FORCE_CONSOLE_RESUME
-#define CONFIG_STM_HWTIMER32
+#define CONFIG_MATH_UTIL
 
 /* USB Configuration */
 #define CONFIG_USB
@@ -91,8 +90,8 @@
 #define CONFIG_USB_UPDATE
 
 #undef CONFIG_UPDATE_PDU_SIZE
-#ifdef BOARD_WAND
-/* Wand does not have enough space to fit 4k PDU. */
+#if defined(BOARD_WAND) || defined(VARIANT_HAMMER_TP_LARGE_PAGE)
+/* Wand/Zed does not have enough space to fit 4k PDU. */
 #define CONFIG_UPDATE_PDU_SIZE 2048
 #else
 #define CONFIG_UPDATE_PDU_SIZE 4096
@@ -110,48 +109,48 @@
 
 /* USB interface indexes (use define rather than enum to expand them) */
 #ifdef SECTION_IS_RW
-#define USB_IFACE_HID_KEYBOARD	0
-#define USB_IFACE_UPDATE	1
+#define USB_IFACE_HID_KEYBOARD 0
+#define USB_IFACE_UPDATE 1
 #ifdef HAS_NO_TOUCHPAD
-#define USB_IFACE_COUNT		2
+#define USB_IFACE_COUNT 2
 #else /* !HAS_NO_TOUCHPAD */
-#define USB_IFACE_HID_TOUCHPAD	2
+#define USB_IFACE_HID_TOUCHPAD 2
 /* Can be either I2C or SPI passthrough, depending on the board. */
-#define USB_IFACE_I2C_SPI	3
+#define USB_IFACE_I2C_SPI 3
 #if defined(CONFIG_USB_ISOCHRONOUS)
-#define USB_IFACE_ST_TOUCHPAD	4
-#define USB_IFACE_COUNT		5
-#else  /* !CONFIG_USB_ISOCHRONOUS */
-#define USB_IFACE_COUNT		4
-#endif  /* CONFIG_USB_ISOCHRONOUS */
+#define USB_IFACE_ST_TOUCHPAD 4
+#define USB_IFACE_COUNT 5
+#else /* !CONFIG_USB_ISOCHRONOUS */
+#define USB_IFACE_COUNT 4
+#endif /* CONFIG_USB_ISOCHRONOUS */
 #endif /* !HAS_NO_TOUCHPAD */
-#else  /* !SECTION_IS_RW */
-#define USB_IFACE_UPDATE	0
-#define USB_IFACE_COUNT		1
-#endif  /* SECTION_IS_RW */
+#else /* !SECTION_IS_RW */
+#define USB_IFACE_UPDATE 0
+#define USB_IFACE_COUNT 1
+#endif /* SECTION_IS_RW */
 
 /* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL		0
-#define USB_EP_UPDATE		1
+#define USB_EP_CONTROL 0
+#define USB_EP_UPDATE 1
 #ifdef SECTION_IS_RW
-#define USB_EP_HID_KEYBOARD	2
+#define USB_EP_HID_KEYBOARD 2
 #ifdef HAS_NO_TOUCHPAD
-#define USB_EP_COUNT		3
+#define USB_EP_COUNT 3
 #else /* !HAS_NO_TOUCHPAD */
-#define USB_EP_HID_TOUCHPAD	3
+#define USB_EP_HID_TOUCHPAD 3
 /* Can be either I2C or SPI passthrough, depending on the board. */
-#define USB_EP_I2C_SPI		4
+#define USB_EP_I2C_SPI 4
 #if defined(CONFIG_USB_ISOCHRONOUS)
-#define USB_EP_ST_TOUCHPAD	5
-#define USB_EP_ST_TOUCHPAD_INT	6
-#define USB_EP_COUNT		7
+#define USB_EP_ST_TOUCHPAD 5
+#define USB_EP_ST_TOUCHPAD_INT 6
+#define USB_EP_COUNT 7
 #else /* !CONFIG_USB_ISOCHRONOUS */
-#define USB_EP_COUNT		5
+#define USB_EP_COUNT 5
 #endif /* CONFIG_USB_ISOCHRONOUS */
 #endif /* !HAS_NO_TOUCHPAD */
-#else  /* !SECTION_IS_RW */
-#define USB_EP_COUNT		2
-#endif  /* SECTION_IS_RW */
+#else /* !SECTION_IS_RW */
+#define USB_EP_COUNT 2
+#endif /* SECTION_IS_RW */
 
 /* Optional features */
 #define CONFIG_BOARD_PRE_INIT
@@ -175,12 +174,23 @@
  * buffer size have to be power of two.
  */
 #undef CONFIG_USB_I2C_MAX_WRITE_COUNT
-#define CONFIG_USB_I2C_MAX_WRITE_COUNT (128 - 4) /* 4 is maximum header size */
+#ifdef VARIANT_HAMMER_TP_LARGE_PAGE
+/* Zed requires 516 byte per packet for touchpad update */
+#define CONFIG_USB_I2C_MAX_WRITE_COUNT         \
+	(1024 - 4) /* 4 is maximum header size \
+		    */
+#else
+#define CONFIG_USB_I2C_MAX_WRITE_COUNT        \
+	(128 - 4) /* 4 is maximum header size \
+		   */
+#endif
 
 #undef CONFIG_USB_I2C_MAX_READ_COUNT
-#define CONFIG_USB_I2C_MAX_READ_COUNT (1024 - 6) /* 6 is maximum header size */
+#define CONFIG_USB_I2C_MAX_READ_COUNT          \
+	(1024 - 6) /* 6 is maximum header size \
+		    */
 
-#define CONFIG_I2C_XFER_LARGE_READ
+#define CONFIG_I2C_XFER_LARGE_TRANSFER
 
 /* No lid switch */
 #undef CONFIG_LID_SWITCH
@@ -196,7 +206,7 @@
 #define CONFIG_USB_HID_TOUCHPAD
 
 /* Virtual address for touchpad FW in USB updater. */
-#define CONFIG_TOUCHPAD_VIRTUAL_OFF	0x80000000
+#define CONFIG_TOUCHPAD_VIRTUAL_OFF 0x80000000
 
 /* Include touchpad FW hashes in image */
 #define CONFIG_TOUCHPAD_HASH_FW
@@ -210,7 +220,7 @@
 
 #if defined(HAS_I2C_TOUCHPAD) || defined(CONFIG_LED_DRIVER_LM3630A)
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_CONTROLLER
 #define I2C_PORT_MASTER 0
 #define I2C_PORT_KBLIGHT 0
 #define I2C_PORT_CHARGER 1
@@ -223,19 +233,20 @@
 
 #ifdef CONFIG_GMR_TABLET_MODE
 #define CONFIG_TABLET_MODE
-#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L
 #define CONFIG_KEYBOARD_TABLET_MODE_SWITCH
 #endif
 
 #ifdef HAS_SPI_TOUCHPAD
 /* Enable control of SPI over USB */
 #define CONFIG_USB_SPI
-#define CONFIG_SPI_MASTER
+#define USB_IFACE_SPI USB_IFACE_I2C_SPI
+#define USB_EP_SPI USB_EP_I2C_SPI
+#define CONFIG_SPI_CONTROLLER
 #define CONFIG_SPI_HALFDUPLEX
-#define CONFIG_STM32_SPI1_MASTER
+#define CONFIG_STM32_SPI1_CONTROLLER
 #define CONFIG_SPI_TOUCHPAD_PORT 0
 #define SPI_ST_TP_DEVICE_ID 0
-/* Enable SPI master xfer command */
+/* Enable SPI controller xfer command */
 #define CONFIG_CMD_SPI_XFER
 #define CONFIG_TOUCHPAD
 #define CONFIG_TOUCHPAD_ST
@@ -260,7 +271,7 @@
 #ifdef BOARD_WAND
 /* Battery and charger options. */
 #define CONFIG_CHARGER
-#define CONFIG_CHARGER_INPUT_CURRENT 128
+#define CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT 128
 #define CONFIG_CHARGER_ISL9238
 #define CONFIG_CHARGER_SENSE_RESISTOR 10
 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 20
@@ -278,7 +289,7 @@
 #define CONFIG_STREAM_USART2
 #define CONFIG_STREAM_USART
 
-#define CONFIG_EC_EC_COMM_SLAVE
+#define CONFIG_EC_EC_COMM_SERVER
 #define CONFIG_EC_EC_COMM_BATTERY
 #define CONFIG_CRC8
 #endif /* BOARD_WAND */
@@ -302,6 +313,7 @@
 /*
  * Add rollback protection, and independent RW region protection.
  */
+#define CONFIG_LIBCRYPTOC
 #define CONFIG_ROLLBACK
 #define CONFIG_ROLLBACK_SECRET_SIZE 32
 #define CONFIG_ROLLBACK_SECRET_LOCAL_ENTROPY_SIZE 32
@@ -311,10 +323,10 @@
 #endif
 
 /* Maximum current to draw. */
-#define MAX_CURRENT_MA			2000
+#define MAX_CURRENT_MA 2000
 /* Maximum current/voltage to provide over OTG. */
-#define MAX_OTG_CURRENT_MA		2000
-#define MAX_OTG_VOLTAGE_MV		20000
+#define MAX_OTG_CURRENT_MA 2000
+#define MAX_OTG_VOLTAGE_MV 20000
 
 #ifndef __ASSEMBLER__
 
@@ -332,6 +344,7 @@ enum usb_strings {
 	USB_STR_PRODUCT,
 	USB_STR_SERIALNO,
 	USB_STR_VERSION,
+	USB_STR_SPI_NAME,
 	USB_STR_I2C_NAME,
 	USB_STR_UPDATE_NAME,
 #ifdef CONFIG_USB_ISOCHRONOUS
diff --git a/board/hammer/build.mk b/board/hammer/build.mk
index b32a6b768a..d41aed0d84 100644
--- a/board/hammer/build.mk
+++ b/board/hammer/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/hammer/ec.tasklist b/board/hammer/ec.tasklist
index ecdb6db120..e528d20cd8 100644
--- a/board/hammer/ec.tasklist
+++ b/board/hammer/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,7 +13,7 @@
 	TASK_ALWAYS_RW(TOUCHPAD, touchpad_task, NULL, LARGER_TASK_STACK_SIZE) \
 	TASK_ALWAYS_RW(CHARGER,  charger_task, NULL, LARGER_TASK_STACK_SIZE) \
 	TASK_ALWAYS   (CONSOLE,  console_task, NULL, 1024) \
-	TASK_ALWAYS_RW(ECCOMM,   ec_ec_comm_slave_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS_RW(ECCOMM,   ec_ec_comm_server_task, NULL, TASK_STACK_SIZE) \
 	TASK_NOTEST_RW(KEYSCAN,  keyboard_scan_task, NULL, TASK_STACK_SIZE)
 #elif defined(CONFIG_USB_ISOCHRONOUS)
 #define CONFIG_TASK_LIST \
diff --git a/board/hammer/gpio.inc b/board/hammer/gpio.inc
index a94c0aa7e4..d79895564d 100644
--- a/board/hammer/gpio.inc
+++ b/board/hammer/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -126,7 +126,7 @@ ALTERNATE(PIN_MASK(B, 0x0c00), 1, MODULE_I2C, 0) /* I2C CHARGER: PB10/11  GPIO_O
 #endif
 
 #ifdef HAS_SPI_TOUCHPAD
-ALTERNATE(PIN_MASK(B, 0x0038), 0, MODULE_SPI_MASTER, 0) /* SPI MASTER:PB3/4/5 */
+ALTERNATE(PIN_MASK(B, 0x0038), 0, MODULE_SPI_CONTROLLER, 0) /* SPI MASTER:PB3/4/5 */
 #endif
 
 #ifdef CONFIG_I2C
diff --git a/board/hammer/variants.h b/board/hammer/variants.h
index 7829e3a34a..12b955dc43 100644
--- a/board/hammer/variants.h
+++ b/board/hammer/variants.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,6 +15,18 @@
 /* USB ID */
 #ifdef BOARD_HAMMER
 #define CONFIG_USB_PID 0x5022
+#elif defined(BOARD_BLAND)
+#define CONFIG_USB_PID 0x5056
+#elif defined(BOARD_DON)
+#define CONFIG_USB_PID 0x5050
+#elif defined(BOARD_DUCK)
+#define CONFIG_USB_PID 0x505b
+#elif defined(BOARD_EEL)
+#define CONFIG_USB_PID 0x5057
+#elif defined(BOARD_GELATIN)
+#define CONFIG_USB_PID 0x505D
+#elif defined(BOARD_JEWEL)
+#define CONFIG_USB_PID 0x5061
 #elif defined(BOARD_MAGNEMITE)
 #define CONFIG_USB_PID 0x503d
 #elif defined(BOARD_MASTERBALL)
@@ -23,13 +35,14 @@
 #define CONFIG_USB_PID 0x5044
 #elif defined(BOARD_STAFF)
 #define CONFIG_USB_PID 0x502b
+#elif defined(BOARD_STAR)
+#define CONFIG_USB_PID 0x5052
 #elif defined(BOARD_WAND)
 #define CONFIG_USB_PID 0x502d
 #elif defined(BOARD_WHISKERS)
 #define CONFIG_USB_PID 0x5030
 #elif defined(BOARD_ZED)
-/* TODO: update PID */
-#define CONFIG_USB_PID 0x5022
+#define CONFIG_USB_PID 0x504c
 #else
 #error "Invalid board"
 #endif
@@ -44,7 +57,64 @@
 #define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 511
 #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 1018 /* tenth of mm */
 #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 566 /* tenth of mm */
-#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (48*1024)
+#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (48 * 1024)
+#elif defined(BOARD_BLAND)
+#define CONFIG_USB_HID_KEYBOARD_VIVALDI
+#define CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS 10
+#define HAS_I2C_TOUCHPAD
+#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X 2644
+#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y 1440
+#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 511
+#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 839 /* tenth of mm */
+#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 457 /* tenth of mm */
+#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (64 * 1024)
+#elif defined(BOARD_DON)
+#define HAS_I2C_TOUCHPAD
+#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X 2925
+#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y 1440
+#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 511
+#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 929 /* tenth of mm */
+#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 457 /* tenth of mm */
+#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (56 * 1024)
+#elif defined(BOARD_DUCK)
+#define CONFIG_USB_HID_KEYBOARD_VIVALDI
+#define CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS 10
+#define HAS_I2C_TOUCHPAD
+#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X 2644
+#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y 1440
+#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 511
+#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 839 /* tenth of mm */
+#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 457 /* tenth of mm */
+#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (64 * 1024)
+#elif defined(BOARD_EEL)
+#define CONFIG_USB_HID_KEYBOARD_VIVALDI
+#define CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS 10
+#define HAS_I2C_TOUCHPAD
+#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X 2644
+#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y 1440
+#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 511
+#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 839 /* tenth of mm */
+#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 457 /* tenth of mm */
+#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (64 * 1024)
+#elif defined(BOARD_GELATIN)
+#define CONFIG_USB_HID_KEYBOARD_VIVALDI
+#define CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS 10
+#define HAS_I2C_TOUCHPAD
+/* TODO: update correct parameters */
+#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X 3340
+#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y 1811
+#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 511
+#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 1060 /* tenth of mm */
+#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 575 /* tenth of mm */
+#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (64 * 1024)
+#elif defined(BOARD_JEWEL)
+#define HAS_I2C_TOUCHPAD
+#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X 2925
+#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y 1440
+#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 511
+#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 929 /* tenth of mm */
+#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 457 /* tenth of mm */
+#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (56 * 1024)
 #elif defined(BOARD_MAGNEMITE)
 #define HAS_NO_TOUCHPAD
 #elif defined(BOARD_MASTERBALL)
@@ -54,56 +124,69 @@
 #define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 511
 #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 839 /* tenth of mm */
 #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 457 /* tenth of mm */
-#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (64*1024)
+#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (64 * 1024)
 #elif defined(BOARD_MOONBALL)
 #define HAS_I2C_TOUCHPAD
-#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X 2926
-#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y 1441
+#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X 2925
+#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y 1440
 #define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 511
-#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 950 /* tenth of mm */
-#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 480 /* tenth of mm */
-#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (56*1024)
+#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 929 /* tenth of mm */
+#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 457 /* tenth of mm */
+#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (56 * 1024)
 #elif defined(BOARD_STAFF)
 #define HAS_I2C_TOUCHPAD
 #define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X 3206
 #define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y 1832
 #define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 511
-#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 1017 /* tenth of mm */
-#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 581 /* tenth of mm */
-#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (56*1024)
+#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 1018 /* tenth of mm */
+#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 582 /* tenth of mm */
+#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (56 * 1024)
+#elif defined(BOARD_STAR)
+#define CONFIG_USB_HID_KEYBOARD_VIVALDI
+#define CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS 10
+#define HAS_I2C_TOUCHPAD
+#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X 3282
+#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y 1793
+#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 511
+#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 1042 /* tenth of mm */
+#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 569 /* tenth of mm */
+#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (64 * 1024)
 #elif defined(BOARD_WHISKERS)
 #define HAS_SPI_TOUCHPAD
 #define HAS_EN_PP3300_TP_ACTIVE_HIGH
 #define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X 2160
 #define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y 1573
 #define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 255
-#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 1030 /* tenth of mm */
-#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 750 /* tenth of mm */
-#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (CONFIG_UPDATE_PDU_SIZE + 128*1024)
+#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 1031 /* tenth of mm */
+#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 751 /* tenth of mm */
+#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (CONFIG_UPDATE_PDU_SIZE + 128 * 1024)
 /* Enable to send heatmap to AP */
 #define CONFIG_USB_ISOCHRONOUS
 #elif defined(BOARD_ZED)
+#define CONFIG_USB_HID_KEYBOARD_VIVALDI
+#define CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS 10
+
 /* TODO: update correct parameters */
 #define HAS_I2C_TOUCHPAD
-#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X 3207
-#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y 1783
+#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X 3340
+#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y 1811
 #define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 511
-#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 1018 /* tenth of mm */
-#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 566 /* tenth of mm */
-#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (48*1024)
+#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 1060 /* tenth of mm */
+#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 575 /* tenth of mm */
+#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (64 * 1024)
 #else
 #error "No touchpad information for board."
 #endif
 
 /* Assistant key */
 #if defined(BOARD_HAMMER) || defined(BOARD_WAND) || defined(BOARD_WHISKERS)
-#define CONFIG_KEYBOARD_BOARD_CONFIG
+
 #define CONFIG_KEYBOARD_ASSISTANT_KEY
 #endif
 
 /* Backlight */
-#if defined(BOARD_HAMMER) || defined(BOARD_STAFF) || \
-    defined(BOARD_WAND) || defined(BOARD_WHISKERS)
+#if defined(BOARD_HAMMER) || defined(BOARD_STAFF) || defined(BOARD_WAND) || \
+	defined(BOARD_WHISKERS)
 /*
  * Even with this option, we detect the backlight presence using a PU/PD on the
  * PWM pin. Not defining this totally disables support.
@@ -123,11 +206,17 @@
 #endif /* BOARD_HAMMER/WAND/WHISKERS */
 
 /* GMR sensor for tablet mode detection */
-#if defined(BOARD_MASTERBALL) || defined(BOARD_MOONBALL) || \
-    defined(BOARD_WHISKERS)
+#if defined(BOARD_DON) || defined(BOARD_MASTERBALL) ||        \
+	defined(BOARD_MOONBALL) || defined(BOARD_WHISKERS) || \
+	defined(BOARD_EEL) || defined(BOARD_JEWEL)
 #define CONFIG_GMR_TABLET_MODE
 #endif
 
 #endif /* SECTION_IS_RW */
 
+/* Enable if the touchpad has >= 128 bytes per page */
+#if defined(BOARD_ZED) || defined(BOARD_DUCK)
+#define VARIANT_HAMMER_TP_LARGE_PAGE
+#endif
+
 #endif /* __CROS_EC_VARIANTS_H */
diff --git a/board/hatch/battery.c b/board/hatch/battery.c
index b81fa795b9..444262b353 100644
--- a/board/hatch/battery.c
+++ b/board/hatch/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/hatch/board.c b/board/hatch/board.c
index 69da3f5328..373afcaea6 100644
--- a/board/hatch/board.c
+++ b/board/hatch/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,6 @@
 /* Hatch board-specific configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "button.h"
 #include "common.h"
 #include "cros_board_info.h"
@@ -35,16 +34,16 @@
 #include "system.h"
 #include "task.h"
 #include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
 #include "thermal.h"
-#include "thermistor.h"
 #include "uart.h"
 #include "usb_charge.h"
 #include "usb_pd.h"
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* GPIO to enable/disable the USB Type-A port. */
 const int usb_port_enable[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT] = {
@@ -94,11 +93,11 @@ static void bc12_interrupt(enum gpio_signal signal)
 {
 	switch (signal) {
 	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
 		break;
 
 	case GPIO_USB_C1_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12, 0);
+		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
 		break;
 
 	default:
@@ -106,20 +105,21 @@ static void bc12_interrupt(enum gpio_signal signal)
 	}
 }
 
-#include "gpio_list.h" /* Must come after other header files. */
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
 
 /******************************************************************************/
 /* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
+const struct spi_device_t spi_devices[] = {};
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
 /******************************************************************************/
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT]   = { .channel = 3, .flags = 0, .freq = 10000 },
-	[PWM_CH_FAN] = {.channel = 5, .flags = PWM_CONFIG_OPEN_DRAIN,
-			.freq = 25000},
+	[PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 },
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
@@ -139,22 +139,26 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = I2C_PORT_TCPC1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
 		},
 		.drv = &ps8xxx_tcpm_drv,
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_TCPC_0] = {
-		.usb_port = USB_PD_PORT_TCPC_0,
-		.driver = &anx7447_usb_mux_driver,
-		.hpd_update = &anx7447_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_0,
+			.driver = &anx7447_usb_mux_driver,
+			.hpd_update = &anx7447_tcpc_update_hpd_status,
+		},
 	},
 	[USB_PD_PORT_TCPC_1] = {
-		.usb_port = USB_PD_PORT_TCPC_1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 	}
 };
 
@@ -221,22 +225,18 @@ static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
 };
 
 /* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					      { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
 
 /*
  * TODO(b/124337208): P0 boards don't have this sensor mounted so the rotation
  * matrix can't be tested properly. This needs to be revisited after EVT to make
  * sure the rotaiton matrix for the lid sensor is correct.
  */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+					     { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
@@ -360,7 +360,7 @@ BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
 
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
@@ -379,52 +379,56 @@ const struct fan_t fans[FAN_CH_COUNT] = {
 /******************************************************************************/
 /* MFT channels. These are logically separate from pwm_channels. */
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN },
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_2] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_1] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_2] = { "TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Temp1",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Temp2",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_2},
+	[TEMP_SENSOR_1] = { .name = "Temp1",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Temp2",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
-
 /* Hatch Temperature sensors */
 /*
  * TODO(b/124316213): These setting need to be reviewed and set appropriately
  * for Hatch. They matter when the EC is controlling the fan as opposed to DPTF
  * control.
  */
-const static struct ec_thermal_config thermal_a = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(25),
-	.temp_fan_max = C_TO_K(50),
-};
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_A                \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+		.temp_fan_off = C_TO_K(25), \
+		.temp_fan_max = C_TO_K(50), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A;
 
 struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
 
@@ -465,7 +469,6 @@ static void board_gpio_set_pp5000(void)
 	} else if (board_id >= 1) {
 		reset_gpio_flags(GPIO_EN_PP5000_A_V1, GPIO_OUT_LOW);
 	}
-
 }
 
 static void board_init(void)
diff --git a/board/hatch/board.h b/board/hatch/board.h
index 057475cb55..0de9a4828f 100644
--- a/board/hatch/board.h
+++ b/board/hatch/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,7 @@
 #define CONFIG_LED_COMMON
 #define CONFIG_LOW_POWER_IDLE
 
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 
 #undef CONFIG_UART_TX_BUF_SIZE
 #define CONFIG_UART_TX_BUF_SIZE 4096
@@ -26,7 +26,6 @@
 
 /* Sensors */
 /* BMI160 Base accel/gyro */
-#define CONFIG_ACCEL_INTERRUPTS
 #define CONFIG_ACCELGYRO_BMI160
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
@@ -44,7 +43,7 @@
 #define CONFIG_ALS_TCS3400
 #define CONFIG_ALS_TCS3400_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS)
-#define I2C_PORT_ALS      I2C_PORT_SENSOR
+#define I2C_PORT_ALS I2C_PORT_SENSOR
 
 /* USB Type C and USB PD defines */
 #define CONFIG_USB_PD_COMM_LOCKED
@@ -89,7 +88,7 @@
 #define CONFIG_FANS 1
 #undef CONFIG_FAN_INIT_SPEED
 #define CONFIG_FAN_INIT_SPEED 50
-#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_A_RAILS
+#define CONFIG_TEMP_SENSOR_POWER
 #define CONFIG_THERMISTOR
 #define CONFIG_THROTTLE_AP
 #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
@@ -108,15 +107,16 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_AC_PRESENT		GPIO_ACOK_OD
-#define GPIO_RSMRST_L_PGOOD	GPIO_PG_EC_RSMRST_L
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L
+#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
 
 #ifndef __ASSEMBLER__
 
@@ -128,8 +128,8 @@
 extern enum gpio_signal gpio_en_pp5000_a;
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_1,	/* ADC0 */
-	ADC_TEMP_SENSOR_2,	/* ADC1 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
 	ADC_CH_COUNT
 };
 
@@ -142,11 +142,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_FAN,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_FAN, PWM_CH_COUNT };
 
 enum fan_channel {
 	FAN_CH_0 = 0,
@@ -160,11 +156,7 @@ enum mft_channel {
 	MFT_CH_COUNT,
 };
 
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_COUNT
-};
+enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
diff --git a/board/hatch/build.mk b/board/hatch/build.mk
index 733912454f..13153c1526 100644
--- a/board/hatch/build.mk
+++ b/board/hatch/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/hatch/ec.tasklist b/board/hatch/ec.tasklist
index 4a1024a091..829be2b7c8 100644
--- a/board/hatch/ec.tasklist
+++ b/board/hatch/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/hatch/gpio.inc b/board/hatch/gpio.inc
index cd241f15f5..22cda73feb 100644
--- a/board/hatch/gpio.inc
+++ b/board/hatch/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,10 +16,10 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(PG_EC_RSMRST_L,       PIN(E, 2), GPIO_INT_BOTH, intel_x86_rsmrst_signal_interrupt)
diff --git a/board/hatch/led.c b/board/hatch/led.c
index d6da1d098f..92332d5978 100644
--- a/board/hatch/led.c
+++ b/board/hatch/led.c
@@ -1,43 +1,48 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Power and battery LED control for Hatch
  */
 
+#include "chipset.h"
 #include "ec_commands.h"
 #include "gpio.h"
 #include "led_common.h"
 #include "led_onoff_states.h"
-#include "chipset.h"
 
 #define LED_ON_LVL 0
 #define LED_OFF_LVL 1
 
-const int led_charge_lvl_1 = 5;
+__override const int led_charge_lvl_1 = 5;
 
-const int led_charge_lvl_2 = 95;
+__override const int led_charge_lvl_2 = 95;
 
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-void led_set_color_battery(enum ec_led_colors color)
+__override void led_set_color_battery(enum ec_led_colors color)
 {
 	switch (color) {
 	case EC_LED_COLOR_AMBER:
@@ -76,4 +81,3 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 
 	return EC_SUCCESS;
 }
-
diff --git a/board/hatch/vif_override.xml b/board/hatch/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/hatch/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/hatch_fp/board.c b/board/hatch_fp/board.c
index e42f576ad8..b213d1ab9e 100644
--- a/board/hatch_fp/board.c
+++ b/board/hatch_fp/board.c
@@ -1,8 +1,7 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
-/* Meowth Fingerprint MCU configuration */
 
 #include "common.h"
 #include "console.h"
@@ -14,7 +13,6 @@
 #include "system.h"
 #include "task.h"
 #include "usart_host_command.h"
-#include "util.h"
 
 /**
  * Disable restricted commands when the system is locked.
@@ -26,22 +24,31 @@ int console_is_restricted(void)
 	return system_is_locked();
 }
 
-#ifndef HAS_TASK_FPSENSOR
-void fps_event(enum gpio_signal signal)
-{
-}
-#endif
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/*
+ * Some platforms have a broken SLP_S0_L signal (stuck to 0 in S0)
+ * if set, ignore it and only uses SLP_S3_L for the AP state.
+ */
+static bool broken_slp;
 
 static void ap_deferred(void)
 {
 	/*
-	 * in S3:   SLP_S3_L is 0 and SLP_S0_L is X.
-	 * in S0ix: SLP_S3_L is X and SLP_S0_L is 0.
-	 * in S0:   SLP_S3_L is 1 and SLP_S0_L is 1.
+	 * Behavior:
+	 * AP Active  (ex. Intel S0):   SLP_L is 1
+	 * AP Suspend (ex. Intel S0ix): SLP_L is 0
+	 * The alternative SLP_ALT_L should be pulled high at all the times.
+	 *
+	 * Legacy Intel behavior:
+	 * in S3:   SLP_ALT_L is 0 and SLP_L is X.
+	 * in S0ix: SLP_ALT_L is 1 and SLP_L is 0.
+	 * in S0:   SLP_ALT_L is 1 and SLP_L is 1.
 	 * in S5/G3, the FP MCU should not be running.
 	 */
-	int running = gpio_get_level(GPIO_PCH_SLP_S3_L)
-			&& gpio_get_level(GPIO_PCH_SLP_S0_L);
+	int running = gpio_get_level(GPIO_SLP_ALT_L) &&
+		      (gpio_get_level(GPIO_SLP_L) || broken_slp);
 
 	if (running) { /* S0 */
 		disable_sleep(SLEEP_MASK_AP_RUN);
@@ -59,44 +66,24 @@ void slp_event(enum gpio_signal signal)
 	hook_call_deferred(&ap_deferred_data, 0);
 }
 
-#include "gpio_list.h"
-
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-	/* Fingerprint sensor (SCLK at 4Mhz) */
-	{ .port = CONFIG_SPI_FP_PORT, .div = 3, .gpio_cs = GPIO_SPI2_NSS }
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-static void configure_fp_sensor_spi(void)
-{
-	/* Configure SPI GPIOs */
-	gpio_config_module(MODULE_SPI_MASTER, 1);
-
-	/* Set all SPI master signal pins to very high speed: B12/13/14/15 */
-	STM32_GPIO_OSPEEDR(GPIO_B) |= 0xff000000;
-
-	/* Enable clocks to SPI2 module (master) */
-	STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
-
-	spi_enable(CONFIG_SPI_FP_PORT, 1);
-}
-
-/* Initialize board. */
-static void board_init(void)
+static void board_init_transport(void)
 {
 	enum fp_transport_type ret_transport = get_fp_transport_type();
 
-	/* Configure and enable SPI as master for FP sensor */
-	configure_fp_sensor_spi();
-
-	ccprints("TRANSPORT_SEL: %s",
-		fp_transport_type_to_str(ret_transport));
+	ccprints("TRANSPORT_SEL: %s", fp_transport_type_to_str(ret_transport));
 
 	/* Initialize transport based on bootstrap */
 	switch (ret_transport) {
-
 	case FP_TRANSPORT_TYPE_UART:
+		/*
+		 * The Zork variants currently have a broken SLP_S0_L signal
+		 * (stuck to 0 in S0). For now, unconditionally ignore it here
+		 * as they are the only UART users and the AP has no S0ix state.
+		 * TODO(b/174695987) once the RW AP firmware has been updated
+		 * on all those machines, remove this workaround.
+		 */
+		broken_slp = true;
+
 		/* Check if CONFIG_USART_HOST_COMMAND is enabled. */
 		if (IS_ENABLED(CONFIG_USART_HOST_COMMAND))
 			usart_host_command_init();
@@ -117,13 +104,29 @@ static void board_init(void)
 	}
 
 	ccprints("TRANSPORT_SEL: %s",
-		fp_transport_type_to_str(get_fp_transport_type()));
+		 fp_transport_type_to_str(get_fp_transport_type()));
+}
+
+/* Initialize board. */
+static void board_init(void)
+{
+	/* Run until the first S3 entry */
+	disable_sleep(SLEEP_MASK_AP_RUN);
+
+	board_init_transport();
 
 	/* Enable interrupt on PCH power signals */
-	gpio_enable_interrupt(GPIO_PCH_SLP_S3_L);
-	gpio_enable_interrupt(GPIO_PCH_SLP_S0_L);
+	gpio_enable_interrupt(GPIO_SLP_ALT_L);
+	gpio_enable_interrupt(GPIO_SLP_L);
 
-	/* enable the SPI slave interface if the PCH is up */
-	hook_call_deferred(&ap_deferred_data, 0);
+	if (IS_ENABLED(SECTION_IS_RW))
+		board_init_rw();
+
+	/*
+	 * Enable the SPI slave interface if the PCH is up.
+	 * Do not use hook_call_deferred(), because ap_deferred() will be
+	 * called after tasks with priority higher than HOOK task (very late).
+	 */
+	ap_deferred();
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/hatch_fp/board.h b/board/hatch_fp/board.h
index 001f437b86..721d216a44 100644
--- a/board/hatch_fp/board.h
+++ b/board/hatch_fp/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -59,28 +59,28 @@
 
 #define CONFIG_FLASH_WRITE_SIZE STM32_FLASH_WRITE_SIZE_3300
 
-#define CONFIG_SHAREDLIB_SIZE   0
+#define CONFIG_SHAREDLIB_SIZE 0
 
-#define CONFIG_RO_MEM_OFF       0
-#define CONFIG_RO_STORAGE_OFF   0
-#define CONFIG_RO_SIZE          (128 * 1024)
+#define CONFIG_RO_MEM_OFF 0
+#define CONFIG_RO_STORAGE_OFF 0
+#define CONFIG_RO_SIZE (128 * 1024)
 
 /* EC rollback protection block */
 #define CONFIG_ROLLBACK_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
 #define CONFIG_ROLLBACK_SIZE (128 * 1024 * 2) /* 2 blocks of 128KB each */
 
-#define CONFIG_RW_MEM_OFF	(CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE)
-#define CONFIG_RW_STORAGE_OFF	0
-#define CONFIG_RW_SIZE		(CONFIG_FLASH_SIZE -			\
-				(CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF))
+#define CONFIG_RW_MEM_OFF (CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE)
+#define CONFIG_RW_STORAGE_OFF 0
+#define CONFIG_RW_SIZE \
+	(CONFIG_FLASH_SIZE_BYTES - (CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF))
 
-#define CONFIG_EC_PROTECTED_STORAGE_OFF         CONFIG_RO_MEM_OFF
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE        CONFIG_RO_SIZE
-#define CONFIG_EC_WRITABLE_STORAGE_OFF          CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE         CONFIG_RW_SIZE
+#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF
+#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE
+#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE
 
-#define CONFIG_WP_STORAGE_OFF           CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE          CONFIG_EC_PROTECTED_STORAGE_SIZE
+#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
+#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
 
 /*
  * We want to prevent flash readout, and use it as indicator of protection
@@ -124,10 +124,10 @@
  *-------------------------------------------------------------------------*/
 
 #define CONFIG_CMD_FLASH
-#define CONFIG_CMD_SPI_XFER
 #define CONFIG_CMD_IDLE_STATS
 
 #ifdef SECTION_IS_RW
+#define CONFIG_CMD_SPI_XFER
 /* TODO(b/130249462): remove for release */
 #define CONFIG_CMD_FPSENSOR_DEBUG
 #endif
@@ -188,8 +188,9 @@
  *-------------------------------------------------------------------------*/
 
 /* SPI configuration for the fingerprint sensor */
-#define CONFIG_SPI_MASTER
-#define CONFIG_SPI_FP_PORT  0 /* SPI2: first master config */
+#define CONFIG_SPI_CONTROLLER
+#define CONFIG_SPI_FP_PORT 0 /* SPI2: first master config */
+#define CONFIG_FINGERPRINT_MCU
 #ifdef SECTION_IS_RW
 #define CONFIG_FP_SENSOR_FPC1025
 /*
@@ -221,36 +222,41 @@
  * Other
  *-------------------------------------------------------------------------*/
 
-#define CONFIG_AES
-#define CONFIG_AES_GCM
-#define CONFIG_DMA
-/*FIXME*/
-/*#define CONFIG_FORCE_CONSOLE_RESUME*/
+#define CONFIG_BORINGSSL_CRYPTO
+#define CONFIG_DMA_CROS
 #define CONFIG_FPU
+#define CONFIG_FPU_WARNINGS
 #define CONFIG_HOST_COMMAND_STATUS
-/*FIXME*/
-/*#define CONFIG_LOW_POWER_IDLE*/
 #define CONFIG_MKBP_EVENT
 #define CONFIG_MKBP_USE_GPIO
-#define CONFIG_PRINTF_LEGACY_LI_FORMAT
+#define CONFIG_PRINTF_LONG_IS_32BITS
 #define CONFIG_RNG
 #define CONFIG_SHA256
 #define CONFIG_SHA256_UNROLLED
 #define CONFIG_SPI
-#define CONFIG_STM_HWTIMER32
-#define CONFIG_SUPPRESSED_HOST_COMMANDS \
-	EC_CMD_CONSOLE_SNAPSHOT, EC_CMD_CONSOLE_READ, EC_CMD_PD_GET_LOG_ENTRY
 #define CONFIG_WP_ACTIVE_HIGH
+#define CONFIG_PANIC_STRIP_GPR
+
+/*
+ * Bloonchipper FPMCU RO has RV32I core panic data structure in their panic
+ * data structure, so expected size of the structure is 144 bytes.
+ */
+#define CONFIG_RO_PANIC_DATA_SIZE 144
+
+#ifdef SECTION_IS_RW
+#define CONFIG_LOW_POWER_IDLE
+#endif /* SECTION_IS_RW */
 
 #ifndef __ASSEMBLER__
 
 /* Timer selection */
 #define TIM_CLOCK32 2
-#define TIM_WATCHDOG 16
+#define TIM_WATCHDOG 9
 
+#include "board_rw.h"
 #include "gpio_signal.h"
 
-void fps_event(enum gpio_signal signal);
+void slp_event(enum gpio_signal signal);
 
 #endif /* !__ASSEMBLER__ */
 
diff --git a/board/hatch_fp/board_rw.c b/board/hatch_fp/board_rw.c
new file mode 100644
index 0000000000..58a0d62386
--- /dev/null
+++ b/board/hatch_fp/board_rw.c
@@ -0,0 +1,62 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "console.h"
+#include "fpsensor_detect.h"
+#include "gpio.h"
+#include "registers.h"
+#include "spi.h"
+#include "task.h"
+#include "usart_host_command.h"
+#include "util.h"
+
+#ifndef SECTION_IS_RW
+#error "This file should only be built for RW."
+#endif
+
+/* SPI devices */
+const struct spi_device_t spi_devices[] = {
+	/* Fingerprint sensor (SCLK at 4Mhz) */
+	{ .port = CONFIG_SPI_FP_PORT, .div = 3, .gpio_cs = GPIO_SPI2_NSS }
+};
+const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
+
+static void configure_fp_sensor_spi(void)
+{
+	/* The dragonclaw development board needs this enabled to enable the
+	 * AND gate (U10) to CS. Production boards could disable this to save
+	 * power since it's only needed for initial detection on those boards.
+	 */
+	gpio_set_level(GPIO_DIVIDER_HIGHSIDE, 1);
+
+	/* Configure SPI GPIOs */
+	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
+
+	/* Set all SPI controller signal pins to very high speed:
+	 * B12/13/14/15
+	 */
+	STM32_GPIO_OSPEEDR(GPIO_B) |= 0xff000000;
+
+	/* Enable clocks to SPI2 module (master) */
+	STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
+
+	spi_enable(&spi_devices[0], 1);
+}
+
+void board_init_rw(void)
+{
+	/*
+	 * FP_RST_ODL pin is defined in gpio_rw.inc (with GPIO_OUT_HIGH
+	 * flag) but not in gpio.inc, so RO leaves this pin set to 0 (reset
+	 * default), but RW doesn't initialize this pin to 1 because sysjump
+	 * to RW is a warm reset (see gpio_pre_init() in chip/stm32/gpio.c).
+	 * Explicitly reset FP_RST_ODL pin to default value.
+	 */
+	gpio_reset(GPIO_FP_RST_ODL);
+
+	/* Configure and enable SPI as master for FP sensor */
+	configure_fp_sensor_spi();
+}
diff --git a/board/hatch_fp/board_rw.h b/board/hatch_fp/board_rw.h
new file mode 100644
index 0000000000..22495ec6d4
--- /dev/null
+++ b/board/hatch_fp/board_rw.h
@@ -0,0 +1,15 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_BOARD_HATCH_FP_BOARD_RW_H
+#define __CROS_EC_BOARD_HATCH_FP_BOARD_RW_H
+
+#include "gpio_signal.h"
+
+void fps_event(enum gpio_signal signal);
+
+void board_init_rw(void);
+
+#endif /* __CROS_EC_BOARD_HATCH_FP_BOARD_RW_H */
diff --git a/board/hatch_fp/build.mk b/board/hatch_fp/build.mk
index 2e40d585fc..eb45551e41 100644
--- a/board/hatch_fp/build.mk
+++ b/board/hatch_fp/build.mk
@@ -1,4 +1,4 @@
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -9,24 +9,74 @@ CHIP:=stm32
 CHIP_FAMILY:=stm32f4
 CHIP_VARIANT:=stm32f412
 
-board-y=board.o fpsensor_detect.o
+# Don't forget that the board build.mk is included more than once to allow
+# conditional variables to be realized. This means that we need to redefine all
+# variable or the "+=" lines will compound.
+board-rw=board_rw.o
+board-y=board.o
 
+# If we're mocking the sensor detection for testing (so we can test
+# sensor/transport permutations in the unit tests), don't build the real sensor
+# detection.
+ifeq ($(HAS_MOCK_FPSENSOR_DETECT),)
+	board-y+=fpsensor_detect.o
+	board-rw+=fpsensor_detect_rw.o
+endif
+
+# Do not build rsa test because this board uses RSA exponent 3 and the rsa test
+# will fail on device.
 test-list-y=\
+       abort \
        aes \
+       always_memset \
+       benchmark \
+       boringssl_crypto \
        compile_time_macros \
-       crc32 \
+       cortexm_fpu \
+       crc \
+       debug \
+       exception \
        flash_physical \
        flash_write_protect \
+       fpsensor \
+       fpsensor_auth_crypto_stateless \
+       fpsensor_hw \
+       ftrapv \
+       global_initialization \
+       libc_printf \
+       libcxx \
+       malloc \
        mpu \
        mutex \
+       panic \
+       panic_data \
        pingpong \
+       printf \
+       queue \
+       rng_benchmark \
        rollback \
        rollback_entropy \
-       rsa \
        rsa3 \
        rtc \
+       sbrk \
        scratchpad \
        sha256 \
        sha256_unrolled \
+       static_if \
+       stdlib \
+       std_vector \
        stm32f_rtc \
+       system_is_locked \
+       timer \
+       timer_dos \
+       tpm_seed_clear \
        utils \
+       utils_str \
+
+       # TODO(b/274162810): Re-enable test on bloonchipper when LTO is
+       # re-enabled.
+       #fpsensor_auth_crypto_stateful \
+
+# Note that this variable includes the trailing "/"
+_hatch_fp_cur_dir:=$(dir $(lastword $(MAKEFILE_LIST)))
+-include $(_hatch_fp_cur_dir)../../private/board/hatch_fp/build.mk
diff --git a/board/hatch_fp/ec.tasklist b/board/hatch_fp/ec.tasklist
index ed1e6ed294..79b8531751 100644
--- a/board/hatch_fp/ec.tasklist
+++ b/board/hatch_fp/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,5 +10,5 @@
 	TASK_ALWAYS_RO(RWSIG, rwsig_task, NULL, 1280) \
 	TASK_ALWAYS(HOOKS, hook_task, NULL, 1024) \
 	TASK_ALWAYS_RW(FPSENSOR, fp_task, NULL, 4096) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 4096) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 6144) \
 	TASK_ALWAYS(CONSOLE, console_task, NULL, CONSOLE_TASK_STACK_SIZE)
diff --git a/board/hatch_fp/fpsensor_detect.c b/board/hatch_fp/fpsensor_detect.c
index e737052b77..7e3b99cac7 100644
--- a/board/hatch_fp/fpsensor_detect.c
+++ b/board/hatch_fp/fpsensor_detect.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,27 +7,6 @@
 #include "gpio.h"
 #include "timer.h"
 
-enum fp_sensor_type get_fp_sensor_type(void)
-{
-	enum fp_sensor_type ret;
-
-	gpio_set_level(GPIO_DIVIDER_HIGHSIDE, 1);
-	usleep(1);
-	switch (gpio_get_level(GPIO_FP_SENSOR_SEL)) {
-	case 0:
-		ret = FP_SENSOR_TYPE_ELAN;
-		break;
-	case 1:
-		ret = FP_SENSOR_TYPE_FPC;
-		break;
-	default:
-		ret = FP_SENSOR_TYPE_UNKNOWN;
-		break;
-	}
-	gpio_set_level(GPIO_DIVIDER_HIGHSIDE, 0);
-	return ret;
-}
-
 enum fp_transport_type get_fp_transport_type(void)
 {
 	enum fp_transport_type ret;
diff --git a/board/hatch_fp/fpsensor_detect_rw.c b/board/hatch_fp/fpsensor_detect_rw.c
new file mode 100644
index 0000000000..e69f0e0000
--- /dev/null
+++ b/board/hatch_fp/fpsensor_detect_rw.c
@@ -0,0 +1,38 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "fpsensor_detect.h"
+#include "gpio.h"
+#include "timer.h"
+
+enum fp_sensor_type fpsensor_detect_get_type(void)
+{
+	enum fp_sensor_type ret;
+
+	gpio_set_level(GPIO_DIVIDER_HIGHSIDE, 1);
+	usleep(1);
+	switch (gpio_get_level(GPIO_FP_SENSOR_SEL)) {
+	case 0:
+		ret = FP_SENSOR_TYPE_ELAN;
+		break;
+	case 1:
+		ret = FP_SENSOR_TYPE_FPC;
+		break;
+	default:
+		ret = FP_SENSOR_TYPE_UNKNOWN;
+		break;
+	}
+	/* We leave GPIO_DIVIDER_HIGHSIDE enabled, since the dragonclaw
+	 * development board use it to enable the AND gate (U10) to CS.
+	 * Production boards could disable this to save power since it's
+	 * only needed for initial detection on those boards.
+	 */
+	return ret;
+}
+
+enum fp_sensor_spi_select fpsensor_detect_get_spi_select(void)
+{
+	return FP_SENSOR_SPI_SELECT_PRODUCTION;
+}
diff --git a/board/hatch_fp/gpio.inc b/board/hatch_fp/gpio.inc
index 3f00642b69..dc185751bc 100644
--- a/board/hatch_fp/gpio.inc
+++ b/board/hatch_fp/gpio.inc
@@ -1,26 +1,21 @@
 /*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Interrupts */
-GPIO_INT(FPS_INT,         PIN(A, 0), GPIO_INT_RISING, fps_event)
-GPIO_INT(PCH_SLP_S0_L,    PIN(A, 8), GPIO_INT_BOTH, slp_event)
+GPIO_INT(SLP_L,           PIN(A, 8), GPIO_INT_BOTH, slp_event)
+GPIO_INT(SLP_ALT_L,       PIN(B, 6), GPIO_INT_BOTH, slp_event)
 GPIO_INT(SPI1_NSS,        PIN(A, 4), GPIO_INPUT, spi_event)
-GPIO_INT(PCH_SLP_S3_L,    PIN(B, 6), GPIO_INT_BOTH, slp_event)
 
 /* Inputs */
-GPIO(FP_SENSOR_SEL,       PIN(B, 0), GPIO_INPUT)
 GPIO(TRANSPORT_SEL,       PIN(B, 1), GPIO_INPUT)
 GPIO(WP,                  PIN(B, 7), GPIO_INPUT)
 
 /* Outputs */
 GPIO(EC_INT_L,            PIN(A, 1),  GPIO_OUT_HIGH)
-GPIO(FP_RST_ODL,          PIN(B,10),  GPIO_OUT_HIGH)
-GPIO(SPI2_NSS,            PIN(B,12),  GPIO_OUT_HIGH)
 GPIO(DIVIDER_HIGHSIDE,    PIN(B, 8),  GPIO_OUT_LOW)
-GPIO(USER_PRES_L,         PIN(B, 9),  GPIO_ODR_HIGH)
 
 /*
  * Unused pins.
@@ -38,16 +33,13 @@ UNUSED(PIN(H, 1))
 
 UNIMPLEMENTED(ENTERING_RW)
 
-/* USART1: PA9/PA10 (TX/RX) to AP*/
+/* USART1: PA9/PA10 (TX/RX) to AP */
 ALTERNATE(PIN_MASK(A, 0x0600), GPIO_ALT_USART,  MODULE_UART, GPIO_PULL_UP)
-/* USART2: PA2/PA3 (TX/RX) to servo*/
+/* USART2: PA2/PA3 (TX/RX) to servo */
 ALTERNATE(PIN_MASK(A, 0x000C), GPIO_ALT_USART,  MODULE_UART, GPIO_PULL_UP)
 /* SPI1 slave from the AP: PA4/5/6/7 (CS/CLK/MISO/MOSI) */
 ALTERNATE(PIN_MASK(A, 0x00f0), GPIO_ALT_SPI, MODULE_SPI,  0)
-/*
- * SPI2 master to sensor: PB13/14/15 (CLK/MISO/MOSI)
- * Note that we're not configuring NSS (PB12) here because we have already
- * configured it as a GPIO above and the SPI_MASTER module expects to use it
- * in software NSS management mode, not hardware management mode.
- */
-ALTERNATE(PIN_MASK(B, 0xE000), GPIO_ALT_SPI, MODULE_SPI_MASTER, GPIO_PULL_DOWN)
+
+#ifdef SECTION_IS_RW
+#include "gpio_rw.inc"
+#endif
diff --git a/board/hatch_fp/gpio_rw.inc b/board/hatch_fp/gpio_rw.inc
new file mode 100644
index 0000000000..dc82cd984a
--- /dev/null
+++ b/board/hatch_fp/gpio_rw.inc
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef SECTION_IS_RW
+#error "This file should only be included in RW."
+#endif
+
+/* Interrupts */
+GPIO_INT(FPS_INT,         PIN(A, 0), GPIO_INT_RISING, fps_event)
+
+/* Inputs */
+GPIO(FP_SENSOR_SEL,       PIN(B, 0), GPIO_INPUT)
+
+/* Outputs */
+GPIO(FP_RST_ODL,          PIN(B,10),  GPIO_OUT_HIGH)
+GPIO(SPI2_NSS,            PIN(B,12),  GPIO_OUT_HIGH)
+GPIO(USER_PRES_L,         PIN(B, 9),  GPIO_ODR_HIGH)
+
+/*
+ * SPI2 master to sensor: PB13/14/15 (CLK/MISO/MOSI)
+ * Note that we're not configuring NSS (PB12) here because we have already
+ * configured it as a GPIO above and the SPI_MASTER module expects to use it
+ * in software NSS management mode, not hardware management mode.
+ */
+ALTERNATE(PIN_MASK(B, 0xE000), GPIO_ALT_SPI, MODULE_SPI_CONTROLLER, GPIO_PULL_DOWN)
diff --git a/board/helios/battery.c b/board/helios/battery.c
index c7168caf8a..dcc9503244 100644
--- a/board/helios/battery.c
+++ b/board/helios/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/helios/board.c b/board/helios/board.c
index 87b2b89702..1cc7de762c 100644
--- a/board/helios/board.c
+++ b/board/helios/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,12 +6,13 @@
 /* Helios board-specific configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "button.h"
 #include "common.h"
 #include "cros_board_info.h"
 #include "driver/accel_bma2x2.h"
 #include "driver/accelgyro_bmi_common.h"
+#include "driver/accelgyro_icm426xx.h"
+#include "driver/accelgyro_icm_common.h"
 #include "driver/als_opt3001.h"
 #include "driver/bc12/pi3usb9201.h"
 #include "driver/ppc/sn5s330.h"
@@ -35,16 +36,16 @@
 #include "tablet_mode.h"
 #include "task.h"
 #include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
 #include "thermal.h"
-#include "thermistor.h"
 #include "uart.h"
 #include "usb_charge.h"
 #include "usb_pd.h"
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void ppc_interrupt(enum gpio_signal signal)
 {
@@ -84,11 +85,11 @@ static void bc12_interrupt(enum gpio_signal signal)
 {
 	switch (signal) {
 	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
 		break;
 
 	case GPIO_USB_C1_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12, 0);
+		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
 		break;
 
 	default:
@@ -129,20 +130,21 @@ static void board_gmr_tablet_switch_isr(enum gpio_signal signal)
 	gmr_tablet_switch_isr(signal);
 }
 
-#include "gpio_list.h" /* Must come after other header files. */
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
 
 /******************************************************************************/
 /* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
+const struct spi_device_t spi_devices[] = {};
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
 /******************************************************************************/
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT]   = { .channel = 3, .flags = 0, .freq = 10000 },
-	[PWM_CH_FAN] = {.channel = 5, .flags = PWM_CONFIG_OPEN_DRAIN,
-			.freq = 25000},
+	[PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 },
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
@@ -153,7 +155,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = I2C_PORT_TCPC0,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
 		},
 		.drv = &ps8xxx_tcpm_drv,
 	},
@@ -161,22 +163,26 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = I2C_PORT_TCPC1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
 		},
 		.drv = &ps8xxx_tcpm_drv,
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_TCPC_0] = {
-		.usb_port = USB_PD_PORT_TCPC_0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_0,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 	},
 	[USB_PD_PORT_TCPC_1] = {
-		.usb_port = USB_PD_PORT_TCPC_1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 	}
 };
 
@@ -200,21 +206,77 @@ static struct mutex g_lid_mutex;
 
 /* Base accel private data */
 static struct bmi_drv_data_t g_bmi160_data;
+static struct icm_drv_data_t g_icm426xx_data;
 
 /* BMA255 private data */
 static struct accelgyro_saved_data_t g_bma255_data;
 
+enum base_accelgyro_type {
+	BASE_GYRO_NONE = 0,
+	BASE_GYRO_BMI160 = 1,
+	BASE_GYRO_ICM426XX = 2,
+};
+
+static enum base_accelgyro_type base_accelgyro_config;
+
 /* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					      { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
+
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					     { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
+
+static const mat33_fp_t base_standard_ref_icm = {
+	{ FLOAT_TO_FP(-1), 0, 0 },
+	{ 0, FLOAT_TO_FP(1), 0 },
+	{ 0, 0, FLOAT_TO_FP(-1) },
+};
+
+struct motion_sensor_t icm426xx_base_accel = {
+	.name = "Base Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.rot_standard_ref = &base_standard_ref_icm,
+	.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
+	.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
+	.default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs. */
+	.config = {
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+		/* Sensor on in S3 */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+	},
 };
 
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
+struct motion_sensor_t icm426xx_base_gyro = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &base_standard_ref_icm,
+	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
+	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
 };
 
 struct motion_sensor_t motion_sensors[] = {
@@ -290,12 +352,43 @@ struct motion_sensor_t motion_sensors[] = {
 };
 unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
+void motion_interrupt(enum gpio_signal signal)
+{
+	if (base_accelgyro_config == BASE_GYRO_ICM426XX)
+		icm426xx_interrupt(signal);
+	else
+		bmi160_interrupt(signal);
+}
+
+static void board_detect_motionsense(void)
+{
+	int val;
+
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return;
+	if (base_accelgyro_config != BASE_GYRO_NONE)
+		return;
+
+	icm_read8(&icm426xx_base_accel, ICM426XX_REG_WHO_AM_I, &val);
+	if (val == ICM426XX_CHIP_ICM40608) {
+		motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
+		motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
+		base_accelgyro_config = BASE_GYRO_ICM426XX;
+		ccprints("Base Accelgyro: ICM40608");
+	} else {
+		base_accelgyro_config = BASE_GYRO_BMI160;
+		ccprints("Base Accelgyro: BMI160");
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_detect_motionsense, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_INIT, board_detect_motionsense, HOOK_PRIO_INIT_I2C + 1);
+
 /******************************************************************************/
 /* Physical fans. These are logically separate from pwm_channels. */
 
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
@@ -314,58 +407,63 @@ const struct fan_t fans[FAN_CH_COUNT] = {
 /******************************************************************************/
 /* MFT channels. These are logically separate from pwm_channels. */
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN },
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		"TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_2] = {
-		"TEMP_5V_REG", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_3] = {
-		"TEMP_AMB", NPCX_ADC_CH3, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_4] = {
-		"TEMP_CPU", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_1] = { "TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_2] = { "TEMP_5V_REG", NPCX_ADC_CH1, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_3] = { "TEMP_AMB", NPCX_ADC_CH3, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_4] = { "TEMP_CPU", NPCX_ADC_CH2, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Temp1",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Temp2",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "Temp3",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_3},
-	[TEMP_SENSOR_4] = {.name = "Temp4",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_4},
+	[TEMP_SENSOR_1] = { .name = "Temp1",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Temp2",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "Temp3",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
+	[TEMP_SENSOR_4] = { .name = "Temp4",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_4 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
 /* Helios temperature control thresholds */
-const static struct ec_thermal_config thermal_a = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(90),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(60),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(65),
-	.temp_fan_max = C_TO_K(80),
-};
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_A                \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(90), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(60), \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+		.temp_fan_off = C_TO_K(65), \
+		.temp_fan_max = C_TO_K(80), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A;
 
 struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
 
@@ -402,8 +500,8 @@ int board_tcpc_post_init(int port)
 		/* Set MUX_DP_EQ to 3.6dB (0x98) */
 		rv = tcpc_write(port, PS8XXX_REG_MUX_DP_EQ_CONFIGURATION, 0x98);
 	else if (port == USB_PD_PORT_TCPC_1)
-		rv = tcpc_write(port,
-				PS8XXX_REG_MUX_USB_C2SS_HS_THRESHOLD, 0x80);
+		rv = tcpc_write(port, PS8XXX_REG_MUX_USB_C2SS_HS_THRESHOLD,
+				0x80);
 
 	return rv;
 }
diff --git a/board/helios/board.h b/board/helios/board.h
index 17e719abb0..83ffd2b4b7 100644
--- a/board/helios/board.h
+++ b/board/helios/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,10 +14,9 @@
 #define CONFIG_POWER_BUTTON
 #define CONFIG_KEYBOARD_PROTOCOL_8042
 #define CONFIG_LED_COMMON
-#define CONFIG_LED_POWER_LED
 #define CONFIG_LOW_POWER_IDLE
 
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 
 #undef CONFIG_UART_TX_BUF_SIZE
 #define CONFIG_UART_TX_BUF_SIZE 4096
@@ -27,10 +26,12 @@
 
 /* Sensors */
 /* BMI160 Base accel/gyro */
-#define CONFIG_ACCEL_INTERRUPTS
 #define CONFIG_ACCELGYRO_BMI160
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+#define CONFIG_ACCELGYRO_ICM426XX
+#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 #define CONFIG_ACCELGYRO_BMI160_INT2_OUTPUT
 /* BMA253 Lid accel */
 #define CONFIG_ACCEL_BMA255
@@ -40,7 +41,6 @@
 #define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
 #define CONFIG_LID_ANGLE_UPDATE
 #define CONFIG_GMR_TABLET_MODE
-#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L
 
 /* USB Type C and USB PD defines */
 #define CONFIG_USB_PD_COMM_LOCKED
@@ -56,7 +56,7 @@
  * Helios' battery takes several seconds to come back out of its disconnect
  * state (~4.2 seconds on the unit I have, so give it a little more for margin).
  */
-#undef  CONFIG_POWER_BUTTON_INIT_TIMEOUT
+#undef CONFIG_POWER_BUTTON_INIT_TIMEOUT
 #define CONFIG_POWER_BUTTON_INIT_TIMEOUT 6
 
 /* BC 1.2 */
@@ -71,7 +71,7 @@
 #define CONFIG_FANS 1
 #undef CONFIG_FAN_INIT_SPEED
 #define CONFIG_FAN_INIT_SPEED 50
-#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_A_RAILS
+#define CONFIG_TEMP_SENSOR_POWER
 #define CONFIG_THERMISTOR
 #define CONFIG_THROTTLE_AP
 #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
@@ -85,15 +85,16 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_AC_PRESENT		GPIO_ACOK_OD
-#define GPIO_RSMRST_L_PGOOD	GPIO_PG_EC_RSMRST_L
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L
+#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
 
 #ifndef __ASSEMBLER__
 
@@ -101,10 +102,10 @@
 #include "registers.h"
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_1,	/* ADC0 */
-	ADC_TEMP_SENSOR_2,	/* ADC1 */
-	ADC_TEMP_SENSOR_3,	/* ADC3 */
-	ADC_TEMP_SENSOR_4,	/* ADC2 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
+	ADC_TEMP_SENSOR_3, /* ADC3 */
+	ADC_TEMP_SENSOR_4, /* ADC2 */
 	ADC_CH_COUNT
 };
 
@@ -116,11 +117,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_FAN,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_FAN, PWM_CH_COUNT };
 
 enum fan_channel {
 	FAN_CH_0 = 0,
@@ -149,6 +146,8 @@ enum battery_type {
 	BATTERY_TYPE_COUNT,
 };
 
+void motion_interrupt(enum gpio_signal signal);
+
 #endif /* !__ASSEMBLER__ */
 
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/helios/build.mk b/board/helios/build.mk
index 733912454f..13153c1526 100644
--- a/board/helios/build.mk
+++ b/board/helios/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/helios/ec.tasklist b/board/helios/ec.tasklist
index 63d366a33b..7fb3e38b63 100644
--- a/board/helios/ec.tasklist
+++ b/board/helios/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/helios/gpio.inc b/board/helios/gpio.inc
index ab8d9f4388..65fc10f761 100644
--- a/board/helios/gpio.inc
+++ b/board/helios/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,10 +17,10 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(PG_EC_RSMRST_L,       PIN(E, 2), GPIO_INT_BOTH, intel_x86_rsmrst_signal_interrupt)
@@ -28,7 +28,7 @@ GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
 GPIO_INT(PP5000_A_PG_OD,       PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
 
 /* Sensor Interrupts */
-GPIO_INT(BASE_SIXAXIS_INT_L,   PIN(5, 6), GPIO_INT_FALLING, bmi160_interrupt)
+GPIO_INT(BASE_SIXAXIS_INT_L,   PIN(5, 6), GPIO_INT_FALLING, motion_interrupt)
 
 /* USB-C interrupts */
 GPIO_INT(USB_C0_PPC_INT_ODL,   PIN(E, 0), GPIO_INT_FALLING, ppc_interrupt)
diff --git a/board/helios/led.c b/board/helios/led.c
index 2c064fb1ea..262f6a055a 100644
--- a/board/helios/led.c
+++ b/board/helios/led.c
@@ -1,46 +1,55 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Power and battery LED control for Helios
  */
 
+#include "chipset.h"
 #include "ec_commands.h"
 #include "gpio.h"
 #include "led_common.h"
 #include "led_onoff_states.h"
-#include "chipset.h"
 
 #define LED_ON_LVL 0
 #define LED_OFF_LVL 1
 
-const int led_charge_lvl_1 = 5;
-
-const int led_charge_lvl_2 = 95;
+__override const int led_charge_lvl_1 = 5;
 
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+__override const int led_charge_lvl_2 = 95;
 
-const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	     3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	     3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    1 * LED_ONE_SEC },
+						  { LED_OFF,
+						    3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
 const enum ec_led_id supported_led_ids[] = {
 	EC_LED_ID_BATTERY_LED,
@@ -49,7 +58,7 @@ const enum ec_led_id supported_led_ids[] = {
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-void led_set_color_battery(enum ec_led_colors color)
+__override void led_set_color_battery(enum ec_led_colors color)
 {
 	switch (color) {
 	case EC_LED_COLOR_AMBER:
@@ -67,7 +76,7 @@ void led_set_color_battery(enum ec_led_colors color)
 	}
 }
 
-void led_set_color_power(enum ec_led_colors color)
+__override void led_set_color_power(enum ec_led_colors color)
 {
 	if (color == EC_LED_COLOR_WHITE)
 		gpio_set_level(GPIO_LED_3_L, LED_ON_LVL);
@@ -104,4 +113,3 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 
 	return EC_SUCCESS;
 }
-
diff --git a/board/helios/vif_override.xml b/board/helios/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/helios/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/helipilot/board.c b/board/helipilot/board.c
new file mode 100644
index 0000000000..abaec801da
--- /dev/null
+++ b/board/helipilot/board.c
@@ -0,0 +1,143 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "fpsensor_detect.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "registers.h"
+#include "shi_chip.h"
+#include "spi.h"
+#include "switch.h"
+#include "system.h"
+#include "task.h"
+#include "uart.h"
+#include "uartn.h"
+
+/* TODO(b/279096907): Investigate de-duping with other FPMCU boards*/
+
+/**
+ * Disable restricted commands when the system is locked.
+ *
+ * @see console.h system.c
+ */
+int console_is_restricted(void)
+{
+	return system_is_locked();
+}
+
+/* Must come after other header files. */
+#include "gpio_list.h"
+
+/*
+ * Some platforms have a broken SLP_S0_L signal (stuck to 0 in S0)
+ * if set, ignore it and only uses SLP_S3_L for the AP state.
+ */
+static bool broken_slp;
+
+static void ap_deferred(void)
+{
+	/*
+	 * Behavior:
+	 * AP Active  (ex. Intel S0):   SLP_L is 1
+	 * AP Suspend (ex. Intel S0ix): SLP_L is 0
+	 * The alternative SLP_ALT_L should be pulled high at all the times.
+	 *
+	 * Legacy Intel behavior:
+	 * in S3:   SLP_ALT_L is 0 and SLP_L is X.
+	 * in S0ix: SLP_ALT_L is 1 and SLP_L is 0.
+	 * in S0:   SLP_ALT_L is 1 and SLP_L is 1.
+	 * in S5/G3, the FP MCU should not be running.
+	 */
+	int running = gpio_get_level(GPIO_SLP_ALT_L) &&
+		      (gpio_get_level(GPIO_SLP_L) || broken_slp);
+
+	if (running) { /* S0 */
+		disable_sleep(SLEEP_MASK_AP_RUN);
+		hook_notify(HOOK_CHIPSET_RESUME);
+	} else { /* S0ix/S3 */
+		hook_notify(HOOK_CHIPSET_SUSPEND);
+		enable_sleep(SLEEP_MASK_AP_RUN);
+	}
+}
+DECLARE_DEFERRED(ap_deferred);
+
+static void board_init_transport(void)
+{
+	enum fp_transport_type ret_transport = get_fp_transport_type();
+
+	ccprints("TRANSPORT_SEL: %s", fp_transport_type_to_str(ret_transport));
+
+	/* Initialize transport based on bootstrap */
+	switch (ret_transport) {
+	case FP_TRANSPORT_TYPE_UART:
+		/*
+		 * The Zork variants currently have a broken SLP_S0_L signal
+		 * (stuck to 0 in S0). For now, unconditionally ignore it here
+		 * as they are the only UART users and the AP has no S0ix state.
+		 * TODO(b/174695987) once the RW AP firmware has been updated
+		 * on all those machines, remove this workaround.
+		 */
+		broken_slp = true;
+
+		/* Check if CONFIG_USART_HOST_COMMAND is enabled. */
+		if (IS_ENABLED(CONFIG_USART_HOST_COMMAND))
+			/*TODO (b/279035335): implement protocol */
+			ccprints("TODO: CONFIG_USART_HOST_COMMAND protocol not "
+				 "yet implemented on helipilot");
+		else
+			ccprints("ERROR: UART not supported in fw build.");
+
+		/* Disable SPI interrupt to disable SPI transport layer */
+		gpio_disable_interrupt(GPIO_SHI_CS_L);
+		break;
+
+	case FP_TRANSPORT_TYPE_SPI:
+		/* SPI transport is enabled. */
+		break;
+	default:
+		ccprints("ERROR: Selected transport is not valid.");
+	}
+
+	ccprints("TRANSPORT_SEL: %s",
+		 fp_transport_type_to_str(get_fp_transport_type()));
+}
+
+static void board_init(void)
+{
+	/* Run until the first S3 entry */
+	disable_sleep(SLEEP_MASK_AP_RUN);
+
+	board_init_transport();
+
+	/* Enable interrupt on PCH power signals */
+	gpio_enable_interrupt(GPIO_SLP_ALT_L);
+	gpio_enable_interrupt(GPIO_SLP_L);
+
+	if (IS_ENABLED(SECTION_IS_RW)) {
+		board_init_rw();
+	}
+
+	/*
+	 * Enable the SPI slave interface if the PCH is up.
+	 * Do not use hook_call_deferred(), because ap_deferred() will be
+	 * called after tasks with priority higher than HOOK task (very late).
+	 */
+	ap_deferred();
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+/* PCH power state changes */
+void slp_event(enum gpio_signal signal)
+{
+	hook_call_deferred(&ap_deferred_data, 0);
+}
+#ifndef HAS_TASK_FPSENSOR
+void fps_event(enum gpio_signal signal)
+{
+}
+#endif
diff --git a/board/helipilot/board.h b/board/helipilot/board.h
new file mode 100644
index 0000000000..1c55017082
--- /dev/null
+++ b/board/helipilot/board.h
@@ -0,0 +1,303 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Helipilot board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "compile_time_macros.h"
+
+#undef CONFIG_SYSTEM_UNLOCKED
+
+#define CONFIG_LTO
+
+/*-------------------------------------------------------------------------*
+ * Flash layout:
+ *
+ * +++++++++++++
+ * |    RO     |
+ * | ......... |
+ * |  Rollback | (two sectors)
+ * +-----------+
+ * |    RW     |
+ * |           |
+ * |           |
+ * |           |
+ * |           |
+ * +++++++++++++
+ *
+ * We adjust the following macros to accommodate for a rollback, RO,
+ * and RW region of different sizes.
+ *
+ *-------------------------------------------------------------------------*
+ */
+
+#undef _IMAGE_SIZE
+#undef CONFIG_ROLLBACK_OFF
+#undef CONFIG_ROLLBACK_SIZE
+#undef CONFIG_FLASH_PSTATE
+#undef CONFIG_FW_PSTATE_SIZE
+#undef CONFIG_FW_PSTATE_OFF
+#undef CONFIG_SHAREDLIB_SIZE
+#undef CONFIG_RO_MEM_OFF
+#undef CONFIG_RO_STORAGE_OFF
+#undef CONFIG_RO_SIZE
+#undef CONFIG_RW_MEM_OFF
+#undef CONFIG_RW_STORAGE_OFF
+#undef CONFIG_RW_SIZE
+#undef CONFIG_EC_PROTECTED_STORAGE_OFF
+#undef CONFIG_EC_PROTECTED_STORAGE_SIZE
+#undef CONFIG_EC_WRITABLE_STORAGE_OFF
+#undef CONFIG_EC_WRITABLE_STORAGE_SIZE
+#undef CONFIG_WP_STORAGE_OFF
+#undef CONFIG_WP_STORAGE_SIZE
+
+/*-------------------------------------------------------------------------*
+ * Patch for reducing program memory size to increase data RAM
+ *-------------------------------------------------------------------------*
+ */
+#undef NPCX_PROGRAM_MEMORY_SIZE
+/* 384 KB program RAM */
+#define NPCX_PROGRAM_MEMORY_SIZE ((416 - 32) * 1024)
+
+#undef CONFIG_PROGRAM_MEMORY_BASE
+#define CONFIG_PROGRAM_MEMORY_BASE 0x10058000
+
+#undef CONFIG_RAM_BASE
+/*
+ * Adjust the base address of the Data RAM
+ * 0x200C0000 - 32K (0x8000) memory address of Data RAM
+ */
+#define CONFIG_RAM_BASE 0x200B8000
+
+#undef CONFIG_DATA_RAM_SIZE
+/*
+ * Define Data RAM size  = 128KB - 4KB (Reserved for booter).
+ */
+#define CONFIG_DATA_RAM_SIZE ((96 + 32) * 1024 - 0x1000)
+/*-------------------------------------------------------------------------*/
+
+#define CONFIG_SHAREDLIB_SIZE 0
+
+#define CONFIG_RO_MEM_OFF 0
+#define CONFIG_RO_STORAGE_OFF 0
+#define CONFIG_RO_SIZE (128 * 1024)
+
+#define CONFIG_RO_PUBKEY_READ_ADDR                                      \
+	(CONFIG_MAPPED_STORAGE_BASE + CONFIG_EC_PROTECTED_STORAGE_OFF + \
+	 CONFIG_RO_PUBKEY_STORAGE_OFF)
+
+#define CONFIG_RWSIG_READ_ADDR                                          \
+	((CONFIG_MAPPED_STORAGE_BASE + CONFIG_EC_WRITABLE_STORAGE_OFF + \
+	  CONFIG_RW_STORAGE_OFF + RW_SIG_OFFSET))
+/*
+ * Since NPCX9 executes out of SRAM and only one image (RO/RW) is loaded
+ * from flash at a time, we don't apply an offset to program memory
+ */
+#define CONFIG_RW_MEM_OFF 0
+#define CONFIG_RW_STORAGE_OFF 0
+
+/*
+ * The remaining flash size (CONFIG_FLASH_SIZE_BYTES -
+ * (CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF) exceeds available program memory,
+ * can only execute a program as big as the available program SRAM
+ */
+#define CONFIG_RW_SIZE                                          \
+	((NPCX_PROGRAM_MEMORY_SIZE / CONFIG_FLASH_ERASE_SIZE) * \
+	 CONFIG_FLASH_ERASE_SIZE)
+
+#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF
+#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE
+#define CONFIG_EC_WRITABLE_STORAGE_OFF \
+	(CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE)
+
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE
+
+#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
+#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
+
+/*
+ * We want to prevent flash readout, and use it as indicator of protection
+ * status.
+ */
+#define CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE
+
+/*-------------------------------------------------------------------------*
+ * Console Defines
+ *-------------------------------------------------------------------------*
+ */
+
+/* Select which UART Controller is the Console UART */
+#undef CONFIG_CONSOLE_UART
+#define CONFIG_CONSOLE_UART 0 /* 0:UART1 1:UART2 */
+#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART1 */
+
+#undef CONSOLE_TASK_STACK_SIZE
+#define CONSOLE_TASK_STACK_SIZE 4096
+
+/*-------------------------------------------------------------------------*
+ * Disable Features
+ *-------------------------------------------------------------------------*
+ */
+#undef CONFIG_ADC
+#undef CONFIG_CMD_ADC
+#undef CONFIG_CMD_POWER_AP
+#undef CONFIG_HIBERNATE
+#undef CONFIG_LID_SWITCH
+#undef CONFIG_SWITCH
+#undef CONFIG_TEMP_SENSOR
+#undef CONFIG_I2C
+#undef CONFIG_TASK_PROFILING
+
+/*-------------------------------------------------------------------------*
+ * Enable Features
+ *-------------------------------------------------------------------------*
+ */
+#define CONFIG_BORINGSSL_CRYPTO
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IDLE_STATS
+#define CONFIG_FPU
+#define CONFIG_FPU_WARNINGS
+#define CONFIG_HOST_INTERFACE_SHI
+#define CONFIG_MKBP_EVENT
+#define CONFIG_MKBP_USE_GPIO
+#define CONFIG_PRINTF_LONG_IS_32BITS
+#define CONFIG_RNG
+#define CONFIG_SHA256
+#define CONFIG_SHA256_UNROLLED
+#ifdef SECTION_IS_RW
+#define CONFIG_SPI
+#define CONFIG_CMD_SPI_XFER
+/* TODO(b/130249462): remove for release */
+#define CONFIG_CMD_FPSENSOR_DEBUG
+#endif
+
+/*-------------------------------------------------------------------------*
+ * Watchdog
+ *-------------------------------------------------------------------------*
+ */
+
+/*
+ * RW does slow compute, RO does slow flash erase.
+ */
+#undef CONFIG_WATCHDOG_PERIOD_MS
+#define CONFIG_WATCHDOG_PERIOD_MS 10000
+#define CONFIG_WATCHDOG_HELP
+
+/*-------------------------------------------------------------------------*
+ * Fingerprint Specific
+ *-------------------------------------------------------------------------*
+ */
+
+/* SPI configuration for the fingerprint sensor */
+#define CONFIG_SPI_CONTROLLER
+#define CONFIG_SPI_FP_PORT 0 /* SPI0: only one SPIP (SPI Peripheral) */
+#define CONFIG_FINGERPRINT_MCU
+#ifdef SECTION_IS_RW
+#define CONFIG_FP_SENSOR_FPC1025
+/*
+ * Use the malloc code only in the RW section (for the private library),
+ * we cannot enable it in RO since it is not compatible with the RW
+ * verification  (shared_mem_init done too late).
+ */
+#define CONFIG_MALLOC
+/*
+ * FP buffers are allocated in regular SRAM
+ * TODO(b/124773209): Instead of defining to empty, #undef once all CLs that
+ * depend on FP_*_SECTION have landed. Also rename the variables to CONFIG_*.
+ */
+#define FP_FRAME_SECTION
+#define FP_TEMPLATE_SECTION
+#endif /* SECTION_IS_RW */
+
+/*
+ * These allow console commands to be flagged as restricted.
+ * Restricted commands will only be permitted to run when
+ * console_is_restricted() returns false.
+ * See console_is_restricted's definition in board.c.
+ */
+#define CONFIG_CONSOLE_COMMAND_FLAGS
+#define CONFIG_RESTRICTED_CONSOLE_COMMANDS
+
+/*-------------------------------------------------------------------------*
+ * Rollback Block
+ *-------------------------------------------------------------------------*
+ */
+
+#define CONFIG_ROLLBACK
+#define CONFIG_ROLLBACK_SECRET_SIZE 32
+#define CONFIG_MPU
+#define CONFIG_ROLLBACK_MPU_PROTECT
+
+/*
+ * We do not use any "locally" generated entropy: this is normally used
+ * to add local entropy when the main source of entropy is remote.
+ */
+#undef CONFIG_ROLLBACK_SECRET_LOCAL_ENTROPY_SIZE
+#ifdef SECTION_IS_RW
+#undef CONFIG_ROLLBACK_UPDATE
+#endif
+
+/* EC rollback protection block */
+#define CONFIG_ROLLBACK_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
+#define CONFIG_ROLLBACK_SIZE (128 * 1024 * 2) /* 2 blocks of 128KB each */
+
+/*-------------------------------------------------------------------------*
+ * RW Signature Verification
+ *-------------------------------------------------------------------------*
+ */
+
+#ifdef SECTION_IS_RO
+/* RO verifies the RW partition signature */
+#define CONFIG_RSA
+#define CONFIG_RWSIG
+#endif /* SECTION_IS_RO */
+#define CONFIG_RSA_KEY_SIZE 3072
+#define CONFIG_RSA_EXPONENT_3
+#define CONFIG_RWSIG_TYPE_RWSIG
+
+/*-------------------------------------------------------------------------*
+ * Chip Specific
+ *-------------------------------------------------------------------------*
+ */
+
+/*
+ * TODO (b/281751547): Remove once Quincy brought up
+ * Board should be set to CONFIG_HW_MRIDER or CONFIG_HW_QUINCY, only needed
+ * until Quincy stable, re-assigns WP GPIO
+ */
+#undef CONFIG_HW_MRIDER
+#define CONFIG_HW_QUINCY
+
+/*
+ * TODO (b/279032946): should eventually be removed, required to avoid
+ * chip_pre_init disabling JTAG internally
+ */
+#define CONFIG_ENABLE_JTAG_SELECTION
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+#define GPIO_WP_L GPIO_HOST_MCU_WP_OD
+#define GPIO_SHI_CS_L GPIO_SPI_HOST_CS_MCU_ODL
+#define GPIO_FPS_INT GPIO_FP_MCU_INT_L
+#define GPIO_EC_INT_L GPIO_MCU_PLATFORM_INT_L
+#define GPIO_SLP_ALT_L GPIO_SLP_L
+
+#ifndef __ASSEMBLER__
+
+#include "board_rw.h"
+#include "gpio_signal.h" /* needed by registers.h */
+#include "registers.h"
+
+void slp_event(enum gpio_signal signal);
+void fps_event(enum gpio_signal signal);
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/helipilot/board_rw.c b/board/helipilot/board_rw.c
new file mode 100644
index 0000000000..2c6a8b8a0a
--- /dev/null
+++ b/board/helipilot/board_rw.c
@@ -0,0 +1,44 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "console.h"
+#include "fpsensor_detect.h"
+#include "gpio.h"
+#include "registers.h"
+#include "spi.h"
+#include "task.h"
+/*#include "usart_host_command.h"*/
+#include "util.h"
+
+#ifndef SECTION_IS_RW
+#error "This file should only be built for RW."
+#endif
+
+/* TODO(b/279096907): Investigate de-duping with other FPMCU boards*/
+
+/* create alias to fit spi_devices declaration in 80 chars */
+#define FP_SPI_CS GPIO_SPI_MCU_CS_FP_L
+
+/* SPI devices */
+const struct spi_device_t spi_devices[] = {
+	/* Fingerprint sensor (SCLK at 4Mhz) */
+	{ .port = CONFIG_SPI_FP_PORT, .div = 3, .gpio_cs = FP_SPI_CS }
+};
+const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
+
+static void configure_fp_sensor_spi(void)
+{
+	/* Configure SPI GPIOs */
+	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
+
+	spi_enable(&spi_devices[0], 1);
+}
+
+void board_init_rw(void)
+{
+	/* Configure and enable SPI as master for FP sensor */
+	configure_fp_sensor_spi();
+}
diff --git a/board/helipilot/board_rw.h b/board/helipilot/board_rw.h
new file mode 120000
index 0000000000..909a66e760
--- /dev/null
+++ b/board/helipilot/board_rw.h
@@ -0,0 +1 @@
+../hatch_fp/board_rw.h
\ No newline at end of file
diff --git a/board/helipilot/build.mk b/board/helipilot/build.mk
new file mode 100644
index 0000000000..0d1e722289
--- /dev/null
+++ b/board/helipilot/build.mk
@@ -0,0 +1,78 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Helipilot board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx9
+CHIP_VARIANT:=npcx9m8s
+
+board-y=
+board-y+=board.o
+board-rw=board_rw.o
+
+# If we're mocking the sensor detection for testing (so we can test
+# sensor/transport permutations in the unit tests), don't build the real sensor
+# detection.
+ifeq ($(HAS_MOCK_FPSENSOR_DETECT),)
+	board-y+=fpsensor_detect.o
+	board-rw+=fpsensor_detect_rw.o
+endif
+
+# Do not build rsa test because this board uses RSA exponent 3 and the rsa test
+# will fail on device.
+test-list-y=\
+       abort \
+       aes \
+       always_memset \
+       benchmark \
+       boringssl_crypto \
+       compile_time_macros \
+       cortexm_fpu \
+       crc \
+       debug \
+       exception \
+       flash_physical \
+       flash_write_protect \
+       fpsensor \
+       fpsensor_auth_crypto_stateful \
+       fpsensor_auth_crypto_stateless \
+       fpsensor_hw \
+       ftrapv \
+       global_initialization \
+       libc_printf \
+       libcxx \
+       malloc \
+       mpu \
+       mutex \
+       panic \
+       panic_data \
+       pingpong \
+       printf \
+       queue \
+       rng_benchmark \
+       rollback \
+       rollback_entropy \
+       rsa3 \
+       rtc \
+       sbrk \
+       scratchpad \
+       sha256 \
+       sha256_unrolled \
+       static_if \
+       stdlib \
+       std_vector \
+       stm32f_rtc \
+       system_is_locked \
+       timer \
+       timer_dos \
+       tpm_seed_clear \
+       unaligned_access \
+       utils \
+       utils_str \
+
+# Note that this variable includes the trailing "/"
+_hatch_fp_cur_dir:=$(dir $(lastword $(MAKEFILE_LIST)))
+-include $(_hatch_fp_cur_dir)../../private/board/hatch_fp/build.mk
diff --git a/board/helipilot/dev_key.pem b/board/helipilot/dev_key.pem
new file mode 100644
index 0000000000..1319b85136
--- /dev/null
+++ b/board/helipilot/dev_key.pem
@@ -0,0 +1,40 @@
+-----BEGIN PRIVATE KEY-----
+MIIG/AIBADANBgkqhkiG9w0BAQEFAASCBuYwggbiAgEAAoIBgQCeXIneAYNlR6mp
+cqkaQrGwfOTwZaz6i1jgra6Uj0RcNzr6qNzkz228vcjRtkFW/ZpJf79Kw6RlOc+M
+U2dRh7JThK+M0glzR6PtXtfCoH1qcRWIRjwm1F5FrlyTT+wqOolkgZ++tN5iUK/A
+eSo7Mt4FOigCXAmKeVVgk0l0VuedTe6sezeV5eL6jY1ot6F/oOhtpNUP9Hn731Cx
+1EdwAvOZQROx6i2MUUMvqY38kc7t6s71JHG1Y7boytIr/IR+9cLzzahV9Z5nqyti
+YO+PPtCeSRCCcpYsOh/mZ1WItXc5AaD3licq7bzsBc0TXZy20dTs6DsyvrVbp1N+
+wL0U9/Gc3NC+YdId3LfL9q05jY0gJsChC85ZshP87/q97grzLytQ1vCBSdHIyUfq
+eipzs+vLz/YG3FFigto/7nOSOp6wZrcQSa6gkhc+5QhkopmuijxmLjHIyPYemVX5
+OVOcdLTDLorVceO03shVGe88j8Rbk/RrhjlUVYb3141fzk28WDsCAQMCggGAaZMG
+lAECQ4UbxkxwvCx2daiYoEPIpweQlckfDbTYPXonUcXomIpJKH6F4SQrj1O8MP/U
+3IJtmNE1CDeaNlp24lh1CIwGTNptSOnlLGr+RvYOWtl9bzg+2R7oYjVIHCcGQwEV
+Kc3pluB1KvtxfMyUA3warD1bsaY46wzbouSaaN6fHad6Y+6XUbOzmyUWVRXwSRiO
+CqL7/T+LITgvoAH3u4C3y/FzsuDXdRuz/baJ8/HfThhLzkJ58Ic2x/2tqfkrlfgP
+V6VkEg8955Ox/cbu7JV7d8GZW6pCcygAAT/Nrg4V+urcZOg1z9YSYW8SThyDIVyO
+U3MAAlPUibEG8P0J8Ym5daD1NPytKzPX42DNijmFWekA8fD/TC8BiIvAXwANt4Iu
+nInKb0+INACkxZZzQiFqqzHga0w5n/w1vlJDce4roKv8Ygau8RHIs/vt27e2uzAj
+vYRU8n7OxKC0y3G9qscdfzdgWhOy6odOvAbBM22B1dFEsUNWdontKO486Ai7AoHB
+AM8I0bmKYb0v9ROty6wa25aVaY2X2ZRIQq/mYrtVnlCx0Kcf4IV0ZSirSFt0fGka
+POuPlqCJnkSqSnIJjCkTzy3V/9GrA8GwvoX40NrTYhKCmJXi441WFGRcQfzrU0/I
+Ex2ze0Bwz3Pmt4ReO3kLVcExpalAi7gPBUtJXZY7ywkdBnver0mo1QWHmA1V/5V+
+/uYZPcKrodmSLXf8XJY4YRt1Nc5NN00D59Patgdrf6BjzDvyZH39NNe8qKPJTJ1T
+DwKBwQDD0L+Y8yaPZFlzVZjmeY6k023BOFaOcnmJxPLLgCRjOq9YFfwOHQcLmWkl
+woTYjNNPTc8VCJcTf0o+LaaCaJOEuDq8RV6MsPWFMBiJqPa+TeAES2lhcoCmTTZ0
+MRcU5wOf4C9WClKt60QYGvfSRuknbDBc0PUJgX6EqsVeg258ZG8jaQTD3zvPwsNJ
+UrVPd6tnTL5p1tTZSPJaS+fVEbcnjqjIUZvgvVQhdEMbGiLuC+Vu2e3Mc1BuTAD+
+n6XC+BUCgcEAigXhJlxBKMqjYnPdHWc9Dw5GXmU7uDAsdURB0jkUNcvgb2qVrk2Y
+xceFkk2oRhF98l+5wFu+2HGG9rEIG2KKHo6qi8dX1nXUWVCLPIzsDFcQY+yXs464
+Qugr/fI3ioViE8z81aCKTUR6WD7SULI5K3ZucNWyerSuMjDpDtKHW2iu/T8fhnCO
+A6+6s46qY6n/RBDT1x0WkQweT/2TDtBAvPjOiYjPiK1FN+ckBPJVFZfdfUxC/qjN
+5ShwbTDdvjdfAoHBAIKLKmX3bwpC5kzju0RRCcM3noDQObRMUQaDTIeqwuzRyjq5
+UrQTWge7m26BreWzN4oz32NbD2JU3ClzxFbwYlh60dLY6bMgo64gEFvF+dQz6q2H
+m5ZMVcQzeaLLZLiaAmqVdOQG4clHgrq8pTbZ8MTyyuiLTgZWVFhx2Oms9FLtn2zw
+rdfqJ9/XLNuMeN+lHO+IfvE54zuF9ubdRTi2ehpfGzA2Z+so4sD4LLy8F0ldQ587
+892iNZ7dVf8VGSylYwKBwEnwpTIwvAlMEEhritgi1qUCwUBp0amNw25vWOEWTMdG
+4EGW4UJtuLmHjaiibbDrqD0bq7bg9J8cgNSJWUpJje/tCC5XxMasx2VndD27zy30
+pWqt7tl7lrvEUhsfB/ZFbM/IepDuzyqGD/VzK0uGzzXW1/OwFCI8Yya1jn8ah61p
+wOyt6Sc1U03ROsHS6K5v0D38U5r1707DkNfZrFFe9QnQceAtbNsGvUyQIht17dj9
+XnknJc8icroJS5SPuZs32g==
+-----END PRIVATE KEY-----
diff --git a/board/helipilot/ec.tasklist b/board/helipilot/ec.tasklist
new file mode 100644
index 0000000000..3fac320eec
--- /dev/null
+++ b/board/helipilot/ec.tasklist
@@ -0,0 +1,17 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#undef HOOKS_TASK_STACK_SIZE
+#define HOOKS_TASK_STACK_SIZE 2048
+
+#define CONFIG_TASK_LIST                                                  \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, HOOKS_TASK_STACK_SIZE)        \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, CONSOLE_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 6144)               \
+	TASK_ALWAYS_RO(RWSIG, rwsig_task, NULL, 1280)                     \
+	TASK_ALWAYS_RW(FPSENSOR, fp_task, NULL, 4096)
diff --git a/board/helipilot/fpsensor_detect.c b/board/helipilot/fpsensor_detect.c
new file mode 120000
index 0000000000..141c5a5af9
--- /dev/null
+++ b/board/helipilot/fpsensor_detect.c
@@ -0,0 +1 @@
+../hatch_fp/fpsensor_detect.c
\ No newline at end of file
diff --git a/board/helipilot/fpsensor_detect_rw.c b/board/helipilot/fpsensor_detect_rw.c
new file mode 120000
index 0000000000..b33a47500d
--- /dev/null
+++ b/board/helipilot/fpsensor_detect_rw.c
@@ -0,0 +1 @@
+../hatch_fp/fpsensor_detect_rw.c
\ No newline at end of file
diff --git a/board/helipilot/gpio.inc b/board/helipilot/gpio.inc
new file mode 100644
index 0000000000..275d3764a3
--- /dev/null
+++ b/board/helipilot/gpio.inc
@@ -0,0 +1,58 @@
+/*
+ * Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Interrupts */
+GPIO_INT(FP_MCU_INT_L,         PIN(B, 0), GPIO_INT_RISING, fps_event)
+
+/* A4 is the assignment on QUINCY, need to use 45 on MRIDER to set pin */
+#ifdef CONFIG_HW_QUINCY
+GPIO_INT(HOST_MCU_WP_OD,       PIN(A, 4), GPIO_INT_BOTH, switch_interrupt)
+#elif defined(CONFIG_HW_MRIDER)
+GPIO_INT(HOST_MCU_WP_OD,       PIN(4, 5), GPIO_INT_BOTH, switch_interrupt)
+#else
+#error "No hardware configured (CONFIG_HW_QUINCY, CONFIG_HW_MRIDER)"
+#endif
+
+/* SHI CS Ready, Low Active. */
+GPIO_INT(SPI_HOST_CS_MCU_ODL,  PIN(5, 3), GPIO_INT_FALLING,shi_cs_event)
+GPIO_INT(SLP_L,                PIN(A, 0), GPIO_INT_BOTH, slp_event)
+
+/* Inputs */
+GPIO(TRANSPORT_SEL,            PIN(4, 3), GPIO_INPUT)
+GPIO(FP_SENSOR_SEL,            PIN(4, 4), GPIO_INPUT)
+/*
+ * SPI host interface - enable PDs by default. These will be made functional
+ * by the SHI driver when the AP powers up, and restored back to GPIO when
+ * the AP powers down.
+ */
+GPIO(SPI_HOST_DO_MCU_DI,       PIN(4, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(SPI_HOST_DI_MCU_DO,       PIN(4, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(SPI_HOST_CLK_MCU,         PIN(5, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(MCU_PLATFORM_INT_L,       PIN(A, 7),  GPIO_ODR_HIGH)
+
+/* Outputs */
+GPIO(FP_RST_ODL,               PIN(9, 6),  GPIO_OUT_HIGH)
+GPIO(SPI_MCU_CS_FP_L,          PIN(A, 6),  GPIO_OUT_HIGH)
+GPIO(DIVIDER_HIGHSIDE,         PIN(9, 3),  GPIO_OUT_LOW)
+
+/* UART1 Tx/Rx */
+#if NPCX_UART_MODULE2
+ALTERNATE(PIN_MASK(6, 0x30), 1, MODULE_UART, 0) /* CR_SIN/SOUT  GPIO64/65 */
+#else
+ALTERNATE(PIN_MASK(1, 0x03), 1, MODULE_UART, 0) /* CR_SIN/SOUT  GPIO10/11 */
+#endif
+
+/* UART2 Tx/Rx */
+ALTERNATE(PIN_MASK(7, 0x20), 1, MODULE_UART, 0) /* CR_SIN2  GPIO75 */
+ALTERNATE(PIN_MASK(8, 0x40), 1, MODULE_UART, 0) /* CR_SOUT2 GPIO86 */
+
+/* SPIP - to FPC Sensor */
+/* SPIP_MOSI/SPIP_SCLK GPIOA3/A1 */
+ALTERNATE(PIN_MASK(A, 0x0A), 1, MODULE_SPI, 0)
+/* SPIP_MISO GPIO95    */
+ALTERNATE(PIN_MASK(9, 0x20), 1, MODULE_SPI, 0)
+
+UNIMPLEMENTED(ENTERING_RW)
\ No newline at end of file
diff --git a/board/herobrine/battery.c b/board/herobrine/battery.c
new file mode 100644
index 0000000000..84c43cc263
--- /dev/null
+++ b/board/herobrine/battery.c
@@ -0,0 +1,68 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "common.h"
+#include "util.h"
+
+/*
+ * Battery info for all herobrine battery types. Note that the fields start
+ * charging_min/max and charging_min/max are not used for the charger. The
+ * effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+
+const struct board_batt_params board_battery_info[] = {
+	/* AP16L5J */
+	[BATTERY_AP16L5J] = {
+		.fuel_gauge = {
+			.manuf_name = "PANASONIC",
+			.device_name = "AP16L5J",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.mfgacc_support = 0,
+				.reg_addr = 0x0,
+				.reg_mask = 0x4000,
+				.disconnect_val = 0x0,
+			}
+		},
+		.batt_info = {
+			.voltage_max            = 8800,
+			.voltage_normal         = 7700, /* mV */
+			.voltage_min            = 6000, /* mV */
+			.precharge_current      = 256,  /* mA */
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 50,
+			.charging_min_c         = 0,
+			.charging_max_c         = 60,
+			.discharging_min_c      = -20,
+			.discharging_max_c      = 75,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_AP16L5J;
diff --git a/board/herobrine/board.c b/board/herobrine/board.c
new file mode 100644
index 0000000000..37c88818b0
--- /dev/null
+++ b/board/herobrine/board.c
@@ -0,0 +1,271 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Herobrine board-specific configuration */
+
+#include "adc_chip.h"
+#include "button.h"
+#include "driver/accel_bma2x2.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "shi_chip.h"
+#include "switch.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+static uint8_t sku_id;
+
+/* Wake-up pins for hibernate */
+const enum gpio_signal hibernate_wake_pins[] = {
+	GPIO_LID_OPEN,
+	GPIO_AC_PRESENT,
+	GPIO_POWER_BUTTON_L,
+	GPIO_RTC_EC_WAKE_ODL,
+};
+const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/* Use 80 us, because KSO_02 passes through the H1. */
+	.output_settle_us = 80,
+	/*
+	 * Unmask 0x08 in [0] (KSO_00/KSI_03, the new location of Search key);
+	 * as it still uses the legacy location (KSO_01/KSI_00).
+	 */
+	.actual_key_mask = { 0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, 0xa4,
+			     0xff, 0xfe, 0x55, 0xfa, 0xca },
+	/* Other values should be the same as the default configuration. */
+	.debounce_down_us = 9 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+};
+
+/* I2C port map */
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_POWER_SCL,
+	  .sda = GPIO_EC_I2C_POWER_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C0_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C0_PD_SDA },
+	{ .name = "tcpc1",
+	  .port = I2C_PORT_TCPC1,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C1_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C1_PD_SDA },
+	{ .name = "rtc",
+	  .port = I2C_PORT_RTC,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_RTC_SCL,
+	  .sda = GPIO_EC_I2C_RTC_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_EEPROM_SCL,
+	  .sda = GPIO_EC_I2C_EEPROM_SDA },
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_SENSOR_SCL,
+	  .sda = GPIO_EC_I2C_SENSOR_SDA },
+};
+
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	/* Measure VBUS through a 1/10 voltage divider */
+	[ADC_VBUS] = { "VBUS", NPCX_ADC_CH1, ADC_MAX_VOLT * 10,
+		       ADC_READ_MAX + 1, 0 },
+	/*
+	 * Adapter current output or battery charging/discharging current (uV)
+	 * 18x amplification on charger side.
+	 */
+	[ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH2, ADC_MAX_VOLT * 1000 / 18,
+			    ADC_READ_MAX + 1, 0 },
+	/*
+	 * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read
+	 * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and
+	 * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we
+	 * only divide by 2 (enough to avoid precision issues).
+	 */
+	[ADC_PSYS] = { "PSYS", NPCX_ADC_CH3,
+		       ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), 2, 0 },
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 },
+	/* TODO(waihong): Assign a proper frequency. */
+	[PWM_CH_DISPLIGHT] = { .channel = 5, .flags = 0, .freq = 4800 },
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+/* Read SKU ID from GPIO and initialize variables for board variants */
+static void sku_id_init(void)
+{
+	int bits[3];
+
+	bits[0] = gpio_get_ternary(GPIO_SKU_ID0);
+	bits[1] = gpio_get_ternary(GPIO_SKU_ID1);
+	bits[2] = gpio_get_ternary(GPIO_SKU_ID2);
+
+	sku_id = binary_first_base3_from_bits(bits, ARRAY_SIZE(bits));
+	CPRINTS("SKU ID: %u", sku_id);
+}
+DECLARE_HOOK(HOOK_INIT, sku_id_init, HOOK_PRIO_INIT_I2C + 1);
+
+__override uint32_t board_get_sku_id(void)
+{
+	return sku_id;
+}
+
+/* Initialize board. */
+static void board_init(void)
+{
+	/* Enable interrupt for BMI260 sensor */
+	gpio_enable_interrupt(GPIO_ACCEL_GYRO_INT_L);
+
+	/* Set the backlight duty cycle to 0. AP will override it later. */
+	pwm_set_duty(PWM_CH_DISPLIGHT, 0);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S0 -> S3 transition */
+static void board_chipset_suspend(void)
+{
+	/*
+	 * Turn off display backlight in S3. AP has its own control. The EC's
+	 * and the AP's will be AND'ed together in hardware.
+	 */
+	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 0);
+	pwm_enable(PWM_CH_DISPLIGHT, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S3 -> S0 transition */
+static void board_chipset_resume(void)
+{
+	/* Turn on display and keyboard backlight in S0. */
+	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 1);
+	if (pwm_get_duty(PWM_CH_DISPLIGHT))
+		pwm_enable(PWM_CH_DISPLIGHT, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
+
+/* Mutexes */
+static struct mutex g_base_mutex;
+static struct mutex g_lid_mutex;
+
+static struct bmi_drv_data_t g_bmi260_data;
+static struct accelgyro_saved_data_t g_bma255_data;
+
+/* Matrix to rotate accelerometer into standard reference frame */
+const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+				       { 0, FLOAT_TO_FP(-1), 0 },
+				       { 0, 0, FLOAT_TO_FP(-1) } };
+
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					     { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
+
+struct motion_sensor_t motion_sensors[] = {
+	[LID_ACCEL] = {
+	 .name = "Lid Accel",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_BMA255,
+	 .type = MOTIONSENSE_TYPE_ACCEL,
+	 .location = MOTIONSENSE_LOC_LID,
+	 .drv = &bma2x2_accel_drv,
+	 .mutex = &g_lid_mutex,
+	 .drv_data = &g_bma255_data,
+	 .port = I2C_PORT_SENSOR,
+	 .i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
+	 .rot_standard_ref = &lid_standard_ref,
+	 .default_range = 2, /* g, to support lid angle calculation. */
+	 .min_frequency = BMA255_ACCEL_MIN_FREQ,
+	 .max_frequency = BMA255_ACCEL_MAX_FREQ,
+	 .config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+		/* Sensor on for lid angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	 },
+	},
+	/*
+	 * Note: BMI260: supports accelerometer and gyro sensor
+	 * Requirement: accelerometer sensor must init before gyro sensor
+	 * DO NOT change the order of the following table.
+	 */
+	[BASE_ACCEL] = {
+	 .name = "Base Accel",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_BMI260,
+	 .type = MOTIONSENSE_TYPE_ACCEL,
+	 .location = MOTIONSENSE_LOC_BASE,
+	 .drv = &bmi260_drv,
+	 .mutex = &g_base_mutex,
+	 .drv_data = &g_bmi260_data,
+	 .port = I2C_PORT_SENSOR,
+	 .i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
+	 .rot_standard_ref = &base_standard_ref,
+	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
+	 .min_frequency = BMI_ACCEL_MIN_FREQ,
+	 .max_frequency = BMI_ACCEL_MAX_FREQ,
+	 .config = {
+		 [SENSOR_CONFIG_EC_S0] = {
+			 .odr = 10000 | ROUND_UP_FLAG,
+		 },
+		 /* Sensor on for lid angle detection */
+		 [SENSOR_CONFIG_EC_S3] = {
+			 .odr = 10000 | ROUND_UP_FLAG,
+		 },
+	 },
+	},
+	[BASE_GYRO] = {
+	 .name = "Gyro",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_BMI260,
+	 .type = MOTIONSENSE_TYPE_GYRO,
+	 .location = MOTIONSENSE_LOC_BASE,
+	 .drv = &bmi260_drv,
+	 .mutex = &g_base_mutex,
+	 .drv_data = &g_bmi260_data,
+	 .port = I2C_PORT_SENSOR,
+	 .i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
+	 .default_range = 1000, /* dps */
+	 .rot_standard_ref = &base_standard_ref,
+	 .min_frequency = BMI_GYRO_MIN_FREQ,
+	 .max_frequency = BMI_GYRO_MAX_FREQ,
+	},
+};
+const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
diff --git a/board/herobrine/board.h b/board/herobrine/board.h
new file mode 100644
index 0000000000..59580826f5
--- /dev/null
+++ b/board/herobrine/board.h
@@ -0,0 +1,103 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Herobrine board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "baseboard.h"
+
+/* TODO(waihong): Remove the following bringup features */
+#define CONFIG_BRINGUP
+#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands. */
+#define CONFIG_USB_PD_DEBUG_LEVEL 3
+#define CONFIG_CMD_GPIO_EXTENDED
+#define CONFIG_CMD_POWERINDEBUG
+#define CONFIG_I2C_DEBUG
+
+/* Keyboard */
+#define CONFIG_KEYBOARD_PROTOCOL_MKBP
+#define CONFIG_KEYBOARD_REFRESH_ROW3
+
+#define CONFIG_PWM_KBLIGHT
+
+/* Battery */
+#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
+#define CONFIG_BATTERY_REVIVE_DISCONNECT
+#define CONFIG_BATTERY_FUEL_GAUGE
+
+/* BC 1.2 Charger */
+#define CONFIG_BC12_DETECT_PI3USB9201
+
+/* USB */
+#define CONFIG_USB_PD_TCPM_PS8805
+#define CONFIG_USBC_PPC_SN5S330
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+
+/* USB-A */
+#define USB_PORT_COUNT 1
+#define CONFIG_USB_PORT_POWER_DUMB
+
+/* Sensors */
+/* BMI260 Base accel/gyro */
+#define CONFIG_ACCELGYRO_BMI260
+#define CONFIG_ACCELGYRO_BMI260_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+#define OPT3001_I2C_ADDR_FLAGS OPT3001_I2C_ADDR1_FLAGS
+
+/* BMA253 lid accel */
+#define CONFIG_ACCEL_BMA255
+#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
+
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+#define CONFIG_LID_ANGLE_UPDATE
+
+#define CONFIG_TABLET_MODE
+#define CONFIG_TABLET_MODE_SWITCH
+#define CONFIG_GMR_TABLET_MODE
+
+/* GPIO alias */
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_WP_L GPIO_EC_WP_ODL
+#define GPIO_SWITCHCAP_PG GPIO_SRC_VPH_PWR_PG
+#define GPIO_ACOK_OD GPIO_CHG_ACOK_OD
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_S5
+#define GPIO_POWER_GOOD GPIO_MB_POWER_GOOD
+#define GPIO_EC_INT_L GPIO_AP_EC_INT_L
+#define GPIO_DP_HOT_PLUG_DET GPIO_DP_HOT_PLUG_DET_R
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum adc_channel { ADC_VBUS, ADC_AMON_BMON, ADC_PSYS, ADC_CH_COUNT };
+
+/* Motion sensors */
+enum sensor_id {
+	LID_ACCEL = 0,
+	BASE_ACCEL,
+	BASE_GYRO,
+	SENSOR_COUNT,
+};
+
+enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_DISPLIGHT, PWM_CH_COUNT };
+
+/* List of possible batteries */
+enum battery_type {
+	BATTERY_AP16L5J,
+	BATTERY_TYPE_COUNT,
+};
+
+/* Reset all TCPCs. */
+void board_reset_pd_mcu(void);
+void board_set_tcpc_power_mode(int port, int mode);
+
+#endif /* !defined(__ASSEMBLER__) */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/herobrine/build.mk b/board/herobrine/build.mk
new file mode 100644
index 0000000000..6827780a6c
--- /dev/null
+++ b/board/herobrine/build.mk
@@ -0,0 +1,18 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx9
+CHIP_VARIANT:=npcx9m3f
+BASEBOARD:=herobrine
+
+board-y+=battery.o
+board-y+=board.o
+board-y+=led.o
+board-y+=switchcap.o
+board-y+=usbc_config.o
diff --git a/board/herobrine/ec.tasklist b/board/herobrine/ec.tasklist
new file mode 100644
index 0000000000..228828af3c
--- /dev/null
+++ b/board/herobrine/ec.tasklist
@@ -0,0 +1,23 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/herobrine/gpio.inc b/board/herobrine/gpio.inc
new file mode 100644
index 0000000000..9628684737
--- /dev/null
+++ b/board/herobrine/gpio.inc
@@ -0,0 +1,177 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+/* USB interrupts */
+GPIO_INT(USB_C0_PD_INT_ODL,    PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-0 TCPC */
+GPIO_INT(USB_C1_PD_INT_ODL,    PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-1 TCPC */
+GPIO_INT(USB_C0_SWCTL_INT_ODL, PIN(0, 3), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-0 PPC */
+GPIO_INT(USB_C1_SWCTL_INT_ODL, PIN(4, 0), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-1 PPC */
+GPIO_INT(USB_C0_BC12_INT_L,    PIN(6, 1), GPIO_INT_FALLING | GPIO_PULL_UP, usb0_evt)  /* Interrupt from port-0 BC1.2 */
+GPIO_INT(USB_C1_BC12_INT_L,    PIN(8, 2), GPIO_INT_FALLING | GPIO_PULL_UP, usb1_evt)  /* Interrupt from port-1 BC1.2 */
+GPIO_INT(USB_A0_OC_ODL,        PIN(F, 4), GPIO_INT_BOTH | GPIO_PULL_UP, usba_oc_interrupt)
+
+/* System interrupts */
+GPIO_INT(CHG_ACOK_OD,       PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)  /* ACOK */
+GPIO_INT(EC_PWR_BTN_ODL,    PIN(0, 0), GPIO_INT_BOTH, power_button_interrupt)  /* Power button */
+GPIO_INT(EC_VOLDN_BTN_ODL,  PIN(6, 2), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Up button */
+GPIO_INT(EC_VOLUP_BTN_ODL,  PIN(C, 2), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Down button */
+GPIO_INT(EC_WP_ODL,         PIN(D, 3), GPIO_INT_BOTH, switch_interrupt)  /* Write protection */
+GPIO_INT(LID_OPEN_EC,       PIN(0, 1), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)  /* Lid open */
+GPIO_INT(AP_RST_L,          PIN(5, 1), GPIO_INT_BOTH, chipset_ap_rst_interrupt)  /* PMIC to signal AP reset */
+GPIO_INT(PS_HOLD,           PIN(A, 6), GPIO_INT_BOTH | GPIO_PULL_DOWN, power_signal_interrupt)  /* Indicate when AP triggers reset/shutdown */
+GPIO_INT(AP_SUSPEND,        PIN(5, 7), GPIO_INT_BOTH, power_signal_interrupt)  /* Suspend signal from PMIC */
+/*
+ * When switch-cap is off, the POWER_GOOD signal is floating. Need a pull-down
+ * to make it low.
+ */
+GPIO_INT(MB_POWER_GOOD,     PIN(3, 7), GPIO_INT_BOTH | GPIO_PULL_DOWN, power_signal_interrupt)  /* PP1800_L18B from PMIC */
+GPIO_INT(WARM_RESET_L,      PIN(B, 0), GPIO_INT_BOTH, power_signal_interrupt)  /* AP warm reset */
+GPIO_INT(AP_EC_SPI_CS_L,    PIN(5, 3), GPIO_INT_FALLING | GPIO_PULL_DOWN, shi_cs_event)  /* EC SPI Chip Select */
+
+/* Sensor interrupts */
+GPIO_INT(TABLET_MODE_L,     PIN(C, 6), GPIO_INT_BOTH, gmr_tablet_switch_isr)
+GPIO_INT(ACCEL_GYRO_INT_L,  PIN(A, 3), GPIO_INT_FALLING, bmi260_interrupt)  /* Accelerometer/gyro interrupt */
+
+GPIO(RTC_EC_WAKE_ODL ,      PIN(0, 2), GPIO_INPUT)     /* RTC interrupt */
+GPIO(EC_ENTERING_RW,        PIN(7, 2), GPIO_OUT_LOW)   /* Indicate when EC is entering RW code */
+GPIO(CCD_MODE_ODL,          PIN(6, 3), GPIO_INPUT)     /* Case Closed Debug Mode */
+GPIO(EC_BATT_PRES_ODL,      PIN(E, 5), GPIO_INPUT)     /* Battery Present */
+GPIO(EC_GSC_PACKET_MODE,    PIN(8, 3), GPIO_OUT_LOW)   /* GSC Packet Mode */
+
+/* PMIC/AP 1.8V */
+GPIO(PMIC_RESIN_L,          PIN(A, 0), GPIO_ODR_HIGH)  /* PMIC reset trigger */
+GPIO(PMIC_KPD_PWR_ODL,      PIN(A, 2), GPIO_ODR_HIGH)  /* PMIC power button */
+GPIO(AP_EC_INT_L,           PIN(5, 6), GPIO_ODR_HIGH)  /* Interrupt line between AP and EC */
+
+/* Power enables */
+GPIO(SWITCHCAP_ON,          PIN(D, 5), GPIO_OUT_LOW)   /* Enable switch cap */
+GPIO(EN_PP5000_S5,          PIN(7, 3), GPIO_OUT_HIGH)  /* Enable PP5000 */
+GPIO(EC_BL_DISABLE_L,       PIN(B, 6), GPIO_OUT_LOW)   /* Backlight disable signal from EC */
+
+/* Sensors */
+GPIO(LID_ACCEL_INT_L,       PIN(A, 1), GPIO_INPUT)     /* Lid accel sensor interrupt */
+/* Control the gate for trackpad IRQ. High closes the gate.
+ * This is always set low so that the OS can manage the trackpad. */
+GPIO(TP_INT_GATE,           PIN(7, 4), GPIO_OUT_LOW)
+
+/* USB-C */
+GPIO(USB_C0_PD_RST_L,       PIN(F, 1), GPIO_OUT_HIGH)  /* Port-0 TCPC chip reset */
+GPIO(USB_C1_PD_RST_L,       PIN(E, 4), GPIO_OUT_HIGH)  /* Port-1 TCPC chip reset */
+GPIO(DP_MUX_OE_L,           PIN(B, 1), GPIO_ODR_HIGH)  /* DP mux enable, actually Open-Drain */
+GPIO(DP_MUX_SEL,            PIN(4, 5), GPIO_OUT_LOW)   /* DP mux selection: L:C0, H:C1 */
+GPIO(DP_HOT_PLUG_DET_R,     PIN(9, 5), GPIO_OUT_LOW)   /* DP HPD to AP */
+
+/* USB-A */
+GPIO(EN_USB_A_5V,           PIN(F, 0), GPIO_OUT_LOW)
+GPIO(USB_A_CDP_ILIM_EN_L,   PIN(7, 5), GPIO_OUT_HIGH)  /* H:CDP, L:SDP. Only one USB-A port, always CDP */
+
+/* LEDs */
+GPIO(EC_CHG_LED_Y_C0,       PIN(6, 0), GPIO_OUT_LOW)
+GPIO(EC_CHG_LED_W_C0,       PIN(C, 0), GPIO_OUT_LOW)
+GPIO(EC_CHG_LED_Y_C1,       PIN(C, 3), GPIO_OUT_LOW)
+GPIO(EC_CHG_LED_W_C1,       PIN(C, 4), GPIO_OUT_LOW)
+
+/*
+ * SPI host interface - enable PDs by default. These will be made functional
+ * by the SHI driver when the AP powers up, and restored back to GPIO when
+ * the AP powers down.
+ */
+GPIO(AP_EC_SPI_MOSI,        PIN(4, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(AP_EC_SPI_MISO,        PIN(4, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(AP_EC_SPI_CLK,         PIN(5, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+
+/* I2C */
+GPIO(EC_I2C_POWER_SCL,      PIN(B, 5), GPIO_INPUT)
+GPIO(EC_I2C_POWER_SDA,      PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_PD_SCL,  PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_PD_SDA,  PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_PD_SCL,  PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_PD_SDA,  PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_RTC_SCL,        PIN(F, 3), GPIO_INPUT)
+GPIO(EC_I2C_RTC_SDA,        PIN(F, 2), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SCL,     PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SDA,     PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,     PIN(B, 3), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SENSOR_SDA,     PIN(B, 2), GPIO_INPUT | GPIO_SEL_1P8V)
+
+/* Board/SKU IDs */
+GPIO(BRD_ID0,               PIN(9, 4), GPIO_INPUT)
+GPIO(BRD_ID1,               PIN(9, 7), GPIO_INPUT)
+GPIO(BRD_ID2,               PIN(A, 5), GPIO_INPUT)
+GPIO(SKU_ID0,               PIN(6, 7), GPIO_INPUT)
+GPIO(SKU_ID1,               PIN(7, 0), GPIO_INPUT)
+GPIO(SKU_ID2,               PIN(E, 1), GPIO_INPUT)
+
+/* Switchcap */
+/*
+ * GPIO0 is configured as PVC_PG. When the chip in power down mode, it outputs
+ * high-Z. Set pull-down to avoid floating.
+ */
+GPIO(SRC_VPH_PWR_PG,        PIN(E, 2), GPIO_INPUT | GPIO_PULL_DOWN) /* Switchcap GPIO0 */
+
+/* Special straps */
+GPIO(ARM_X86,               PIN(6, 6), GPIO_OUT_LOW)  /* NC, low for power saving */
+
+/* Unused GPIOs, NC. */
+UNUSED(PIN(5, 2))
+UNUSED(PIN(5, 4))
+UNUSED(PIN(7, 6))
+UNUSED(PIN(C, 5))
+UNUSED(PIN(D, 1))
+UNUSED(PIN(D, 0))
+UNUSED(PIN(E, 3))
+UNUSED(PIN(C, 1))
+UNUSED(PIN(0, 4))
+UNUSED(PIN(D, 6))
+UNUSED(PIN(3, 2))
+UNUSED(PIN(3, 5))
+UNUSED(PIN(D, 7))
+UNUSED(PIN(8, 6))
+UNUSED(PIN(D, 4))
+UNUSED(PIN(4, 1))
+UNUSED(PIN(3, 4))
+UNUSED(PIN(C, 7))
+UNUSED(PIN(A, 4))
+UNUSED(PIN(9, 6))
+UNUSED(PIN(9, 3))
+UNUSED(PIN(A, 7))
+UNUSED(PIN(5, 0))
+UNUSED(PIN(8, 1))
+
+/* Alternate functions GPIO definitions */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)            /* UART (GPIO64/65) */
+ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0)             /* I2C0 (GPIOB4/B5) */
+ALTERNATE(PIN_MASK(9, 0x07), 1, MODULE_I2C, 0)             /* I2C1 SDA (GPIO90), I2C2 (GPIO91/92) */
+ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, 0)             /* I2C1 SCL (GPIO87) */
+ALTERNATE(PIN_MASK(F, 0x0C), 1, MODULE_I2C, 0)             /* I2C4 (GPIOF2/F3) */
+ALTERNATE(PIN_MASK(3, 0x48), 1, MODULE_I2C, 0)             /* I2C5 (GPIO33/36) */
+ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, GPIO_SEL_1P8V) /* I2C7 (GPIOB2/B3) - 1.8V */
+ALTERNATE(PIN_MASK(4, 0x1C), 0, MODULE_ADC, 0)             /* ADC1 (GPIO44), ADC2 (GPIO43), ADC3 (GPIO42) */
+ALTERNATE(PIN_MASK(4, 0xC0), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SDO (GPIO47), SHI_SDI (GPIO46) */
+ALTERNATE(PIN_MASK(5, 0x28), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SCLK (GPIO55), SHI_CS# (GPIO53) */
+ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)             /* PWM3 (GPIO80) - KB_BL_PWM */
+ALTERNATE(PIN_MASK(B, 0x80), 1, MODULE_PWM, 0)             /* PWM5 (GPIOB7) - EDP_BKLTCTL */
+ALTERNATE(PIN_MASK(D, 0x04), 1, MODULE_PMU, 0)             /* PSL_IN1 (GPIOD2) - ACOK_OD */
+ALTERNATE(PIN_MASK(0, 0x01), 1, MODULE_PMU, 0)             /* PSL_IN2 (GPIO00) - EC_PWR_BTN_ODL */
+ALTERNATE(PIN_MASK(0, 0x02), 1, MODULE_PMU, 0)             /* PSL_IN3 (GPIO01) - LID_OPEN_EC */
+ALTERNATE(PIN_MASK(0, 0x04), 1, MODULE_PMU, 0)             /* PSL_IN4 (GPIO02) - RTC_EC_WAKE_ODL */
+
+/* Keyboard */
+#define GPIO_KB_INPUT           (GPIO_INPUT | GPIO_PULL_UP)
+#define GPIO_KB_OUTPUT          (GPIO_ODR_HIGH)
+#define GPIO_KB_OUTPUT_COL2     (GPIO_OUT_LOW)
+
+/* Keyboard alternate functions */
+ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)  /* KSO10 (GPIO07), KSO11 (GPIO06), KSO12 (GPIO05) */
+ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)  /* KSO03 (GPIO16), KSO04 (GPIO15), KSO05 (GPIO14), KSO06 (GPIO13), KSO07 (GPIO12), KSO08 (GPIO11), KSO09 (GPIO10) */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)  /* KSO00 (GPIO21), KSO01 (GPIO20) */
+ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)   /* KSI2 (GPIO27), KSI3 (GPIO26), KSI4 (GPIO25), KSI5 (GPIO24), KSI6 (GPIO23), KSI7 (GPIO22) */
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)   /* KSI0 (GPIO31), KSI1 (GPIO30) */
+GPIO(EC_KSO_02_INV,       PIN(1, 7), GPIO_KB_OUTPUT_COL2)              /* KSO02 (GPIO17) */
diff --git a/board/herobrine/led.c b/board/herobrine/led.c
new file mode 100644
index 0000000000..27205e0257
--- /dev/null
+++ b/board/herobrine/led.c
@@ -0,0 +1,163 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power and battery LED control.
+ */
+
+#include "battery.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "chipset.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "led_common.h"
+#include "system.h"
+#include "util.h"
+
+#define BAT_LED_ON 1
+#define BAT_LED_OFF 0
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_RIGHT_LED,
+	EC_LED_ID_LEFT_LED,
+};
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+enum led_color {
+	LED_OFF = 0,
+	LED_AMBER,
+	LED_WHITE,
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
+};
+
+static void side_led_set_color(int port, enum led_color color)
+{
+	gpio_set_level(port ? GPIO_EC_CHG_LED_Y_C1 : GPIO_EC_CHG_LED_Y_C0,
+		       (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
+	gpio_set_level(port ? GPIO_EC_CHG_LED_W_C1 : GPIO_EC_CHG_LED_W_C0,
+		       (color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF);
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	brightness_range[EC_LED_COLOR_AMBER] = 1;
+	brightness_range[EC_LED_COLOR_WHITE] = 1;
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	int port;
+
+	switch (led_id) {
+	case EC_LED_ID_RIGHT_LED:
+		port = 0;
+		break;
+	case EC_LED_ID_LEFT_LED:
+		port = 1;
+		break;
+	default:
+		return EC_ERROR_PARAM1;
+	}
+
+	if (brightness[EC_LED_COLOR_WHITE] != 0)
+		side_led_set_color(port, LED_WHITE);
+	else if (brightness[EC_LED_COLOR_AMBER] != 0)
+		side_led_set_color(port, LED_AMBER);
+	else
+		side_led_set_color(port, LED_OFF);
+
+	return EC_SUCCESS;
+}
+
+/*
+ * Set active charge port color to the parameter, turn off all others.
+ * If no port is active (-1), turn off all LEDs.
+ */
+static void set_active_port_color(enum led_color color)
+{
+	int port = charge_manager_get_active_charge_port();
+
+	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
+		side_led_set_color(0, (port == 0) ? color : LED_OFF);
+	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
+		side_led_set_color(1, (port == 1) ? color : LED_OFF);
+}
+
+static void board_led_set_battery(void)
+{
+	static int battery_ticks;
+
+	battery_ticks++;
+
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
+		/* Always indicate when charging, even in suspend. */
+		set_active_port_color(LED_AMBER);
+		break;
+	case LED_PWRS_DISCHARGE:
+		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
+			if (charge_get_percent() <= 10)
+				side_led_set_color(0, (battery_ticks & 0x4) ?
+							      LED_WHITE :
+							      LED_OFF);
+			else
+				side_led_set_color(0, LED_OFF);
+		}
+
+		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
+			side_led_set_color(1, LED_OFF);
+		break;
+	case LED_PWRS_ERROR:
+		set_active_port_color((battery_ticks & 0x2) ? LED_WHITE :
+							      LED_OFF);
+		break;
+	case LED_PWRS_CHARGE_NEAR_FULL:
+		set_active_port_color(LED_WHITE);
+		break;
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		set_active_port_color(LED_WHITE);
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		set_active_port_color((battery_ticks & 0x4) ? LED_AMBER :
+							      LED_OFF);
+		break;
+	default:
+		/* Other states don't alter LED behavior */
+		break;
+	}
+}
+
+/* Called by hook task every TICK */
+static void led_tick(void)
+{
+	board_led_set_battery();
+}
+DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
+
+void led_control(enum ec_led_id led_id, enum ec_led_state state)
+{
+	enum led_color color;
+
+	if ((led_id != EC_LED_ID_RECOVERY_HW_REINIT_LED) &&
+	    (led_id != EC_LED_ID_SYSRQ_DEBUG_LED))
+		return;
+
+	if (state == LED_STATE_RESET) {
+		led_auto_control(EC_LED_ID_LEFT_LED, 1);
+		led_auto_control(EC_LED_ID_RIGHT_LED, 1);
+		board_led_set_battery();
+		return;
+	}
+
+	color = state ? LED_WHITE : LED_OFF;
+
+	led_auto_control(EC_LED_ID_LEFT_LED, 0);
+	led_auto_control(EC_LED_ID_RIGHT_LED, 0);
+
+	side_led_set_color(0, color);
+	side_led_set_color(1, color);
+}
diff --git a/board/herobrine/switchcap.c b/board/herobrine/switchcap.c
new file mode 100644
index 0000000000..5173e27f75
--- /dev/null
+++ b/board/herobrine/switchcap.c
@@ -0,0 +1,22 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "gpio.h"
+#include "power/qcom.h"
+
+void board_set_switchcap_power(int enable)
+{
+	gpio_set_level(GPIO_SWITCHCAP_ON, enable);
+}
+
+int board_is_switchcap_enabled(void)
+{
+	return gpio_get_level(GPIO_SWITCHCAP_ON);
+}
+
+int board_is_switchcap_power_good(void)
+{
+	return gpio_get_level(GPIO_SWITCHCAP_PG);
+}
diff --git a/board/herobrine/usbc_config.c b/board/herobrine/usbc_config.c
new file mode 100644
index 0000000000..7709a3ba25
--- /dev/null
+++ b/board/herobrine/usbc_config.c
@@ -0,0 +1,317 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Herobrine board-specific USB-C configuration */
+
+#include "bc12/pi3usb9201_public.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "common.h"
+#include "config.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "ppc/sn5s330_public.h"
+#include "system.h"
+#include "tcpm/ps8xxx_public.h"
+#include "tcpm/tcpci.h"
+#include "timer.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usbc_config.h"
+#include "usbc_ocp.h"
+#include "usbc_ppc.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/* GPIO Interrupt Handlers */
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	int port = -1;
+
+	switch (signal) {
+	case GPIO_USB_C0_PD_INT_ODL:
+		port = 0;
+		break;
+	case GPIO_USB_C1_PD_INT_ODL:
+		port = 1;
+		break;
+	default:
+		return;
+	}
+
+	schedule_deferred_pd_interrupt(port);
+}
+
+void usb0_evt(enum gpio_signal signal)
+{
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+
+void usb1_evt(enum gpio_signal signal)
+{
+	usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+}
+
+static void usba_oc_deferred(void)
+{
+	/* Use next number after all USB-C ports to indicate the USB-A port */
+	board_overcurrent_event(CONFIG_USB_PD_PORT_MAX_COUNT,
+				!gpio_get_level(GPIO_USB_A0_OC_ODL));
+}
+DECLARE_DEFERRED(usba_oc_deferred);
+
+void usba_oc_interrupt(enum gpio_signal signal)
+{
+	hook_call_deferred(&usba_oc_deferred_data, 0);
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_SWCTL_INT_ODL:
+		sn5s330_interrupt(0);
+		break;
+	case GPIO_USB_C1_SWCTL_INT_ODL:
+		sn5s330_interrupt(1);
+		break;
+	default:
+		break;
+	}
+}
+
+/* Power Path Controller */
+struct ppc_config_t ppc_chips[] = {
+	{ .i2c_port = I2C_PORT_TCPC0,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
+	{ .i2c_port = I2C_PORT_TCPC1,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
+};
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/* TCPC mux configuration */
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TCPC0,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+	},
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TCPC1,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+	},
+};
+
+/*
+ * Port-0/1 USB mux driver.
+ *
+ * The USB mux is handled by TCPC chip and the HPD update is through a GPIO
+ * to AP. But the TCPC chip is also needed to know the HPD status; otherwise,
+ * the mux misbehaves.
+ */
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
+	},
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
+	}
+};
+
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_USB_A_5V,
+};
+
+/* BC1.2 */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	{
+		.i2c_port = I2C_PORT_POWER,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+	{
+		.i2c_port = I2C_PORT_EEPROM,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+};
+
+/* Initialize board USC-C things */
+static void board_init_usbc(void)
+{
+	/* Enable BC1.2 interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_L);
+	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L);
+
+	/* Enable USB-A overcurrent interrupt */
+	gpio_enable_interrupt(GPIO_USB_A0_OC_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_init_usbc, HOOK_PRIO_DEFAULT);
+
+void board_tcpc_init(void)
+{
+	/* Only reset TCPC if not sysjump */
+	if (!system_jumped_late()) {
+		/* TODO(crosbug.com/p/61098): How long do we need to wait? */
+		board_reset_pd_mcu();
+	}
+
+	/* Enable PPC interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_SWCTL_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_SWCTL_INT_ODL);
+
+	/* Enable TCPC interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL);
+
+	/*
+	 * Initialize HPD to low; after sysjump SOC needs to see
+	 * HPD pulse to enable video path
+	 */
+	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
+		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
+
+void board_reset_pd_mcu(void)
+{
+	cprints(CC_USB, "Resetting TCPCs...");
+	cflush();
+
+	gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
+	gpio_set_level(GPIO_USB_C1_PD_RST_L, 0);
+	msleep(PS8XXX_RESET_DELAY_MS);
+	gpio_set_level(GPIO_USB_C0_PD_RST_L, 1);
+	gpio_set_level(GPIO_USB_C1_PD_RST_L, 1);
+	msleep(PS8805_FW_INIT_DELAY_MS);
+}
+
+void board_set_tcpc_power_mode(int port, int mode)
+{
+	/* Ignore the "mode" to turn the chip on.  We can only do a reset. */
+	if (mode)
+		return;
+
+	board_reset_pd_mcu();
+}
+
+int board_vbus_sink_enable(int port, int enable)
+{
+	/* Both ports are controlled by PPC SN5S330 */
+	return ppc_vbus_sink_enable(port, enable);
+}
+
+int board_is_sourcing_vbus(int port)
+{
+	/* Both ports are controlled by PPC SN5S330 */
+	return ppc_is_sourcing_vbus(port);
+}
+
+void board_overcurrent_event(int port, int is_overcurrented)
+{
+	/* TODO(b/120231371): Notify AP */
+	CPRINTS("p%d: overcurrent!", port);
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int i;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTS("Disabling all charging port");
+
+		/* Disable all ports. */
+		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (board_vbus_sink_enable(i, 0))
+				CPRINTS("Disabling p%d sink path failed.", i);
+		}
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (board_is_sourcing_vbus(port)) {
+		CPRINTS("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTS("New charge port: p%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		if (i == port)
+			continue;
+
+		if (board_vbus_sink_enable(i, 0))
+			CPRINTS("p%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (board_vbus_sink_enable(port, 1)) {
+		CPRINTS("p%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
+{
+	/*
+	 * Ignore lower charge ceiling on PD transition if our battery is
+	 * critical, as we may brownout.
+	 */
+	if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 &&
+	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
+		CPRINTS("Using max ilim %d", max_ma);
+		charge_ma = max_ma;
+	}
+
+	charge_set_input_current_limit(charge_ma, charge_mv);
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
+		if (gpio_get_level(GPIO_USB_C0_PD_RST_L))
+			status |= PD_STATUS_TCPC_ALERT_0;
+	if (!gpio_get_level(GPIO_USB_C1_PD_INT_ODL))
+		if (gpio_get_level(GPIO_USB_C1_PD_RST_L))
+			status |= PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
diff --git a/board/herobrine/usbc_config.h b/board/herobrine/usbc_config.h
new file mode 100644
index 0000000000..da19a67d2d
--- /dev/null
+++ b/board/herobrine/usbc_config.h
@@ -0,0 +1,19 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Herobrine board-specific USB-C configuration */
+
+#ifndef __CROS_EC_USBC_CONFIG_H
+#define __CROS_EC_USBC_CONFIG_H
+
+#include "gpio.h"
+
+void tcpc_alert_event(enum gpio_signal signal);
+void usb0_evt(enum gpio_signal signal);
+void usb1_evt(enum gpio_signal signal);
+void usba_oc_interrupt(enum gpio_signal signal);
+void ppc_interrupt(enum gpio_signal signal);
+
+#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/herobrine/vif_override.xml b/board/herobrine/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/herobrine/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/hoho/board.c b/board/hoho/board.c
index fe2bcf1476..a671ef707d 100644
--- a/board/hoho/board.c
+++ b/board/hoho/board.c
@@ -1,11 +1,10 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 /* Hoho dongle configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "common.h"
 #include "ec_commands.h"
 #include "ec_version.h"
@@ -14,16 +13,17 @@
 #include "mcdp28x0.h"
 #include "registers.h"
 #include "task.h"
+#include "timer.h"
 #include "usb_bb.h"
 #include "usb_descriptor.h"
 #include "usb_pd.h"
-#include "timer.h"
 #include "util.h"
 
 static volatile uint64_t hpd_prev_ts;
 static volatile int hpd_prev_level;
 
 void hpd_event(enum gpio_signal signal);
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /**
@@ -99,7 +99,7 @@ void board_config_pre_init(void)
 	/* enable SYSCFG clock */
 	STM32_RCC_APB2ENR |= BIT(0);
 	/* Remap USART DMA to match the USART driver */
-	STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10);/* Remap USART1 RX/TX DMA */
+	STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10); /* Remap USART1 RX/TX DMA */
 }
 
 #ifdef CONFIG_SPI_FLASH
@@ -143,11 +143,10 @@ static void factory_validation_deferred(void)
 
 	/* test mcdp via serial to validate function */
 	if (!mcdp_get_info(&info) && (MCDP_FAMILY(info.family) == 0x0010) &&
-	(MCDP_CHIPID(info.chipid) == 0x2850)) {
+	    (MCDP_CHIPID(info.chipid) == 0x2850)) {
 		gpio_set_level(GPIO_MCDP_READY, 1);
 		pd_log_event(PD_EVENT_VIDEO_CODEC,
-			     PD_LOG_PORT_SIZE(0, sizeof(info)),
-			     0, &info);
+			     PD_LOG_PORT_SIZE(0, sizeof(info)), 0, &info);
 	}
 
 	mcdp_disable();
@@ -168,7 +167,7 @@ static void board_init(void)
 
 	gpio_set_level(GPIO_STM_READY, 1); /* factory test only */
 	/* Delay needed to allow HDMI MCU to boot. */
-	hook_call_deferred(&factory_validation_deferred_data, 200*MSEC);
+	hook_call_deferred(&factory_validation_deferred_data, 200 * MSEC);
 }
 
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
@@ -176,13 +175,13 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* USB PD CC lines sensing. Converted to mV (3300mV/4096). */
-	[ADC_CH_CC1_PD] = {"USB_C_CC1_PD", 3300, 4096, 0, STM32_AIN(1)},
+	[ADC_CH_CC1_PD] = { "USB_C_CC1_PD", 3300, 4096, 0, STM32_AIN(1) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
-const void * const usb_strings[] = {
+const void *const usb_strings[] = {
 	[USB_STR_DESC] = usb_string_desc,
-	[USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."),
+	[USB_STR_VENDOR] = USB_STRING_DESC("Google LLC"),
 	[USB_STR_PRODUCT] = USB_STRING_DESC("Hoho"),
 	[USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32),
 	[USB_STR_BB_URL] = USB_STRING_DESC(USB_GOOGLE_TYPEC_URL),
diff --git a/board/hoho/board.h b/board/hoho/board.h
index 21fb536a6f..f6421fdaf0 100644
--- a/board/hoho/board.h
+++ b/board/hoho/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,7 +15,6 @@
 #define CONFIG_UART_CONSOLE 1
 
 /* Optional features */
-#define CONFIG_STM_HWTIMER32
 #define CONFIG_ADC
 #define CONFIG_BOARD_PRE_INIT
 #define CONFIG_CMD_SPI_FLASH
@@ -24,10 +23,9 @@
 #define CONFIG_RWSIG
 #define CONFIG_RWSIG_TYPE_USBPD1
 #define CONFIG_SHA256
-/* TODO(tbroch) Re-enable once STM spi master can be inhibited at boot so it
+/* TODO(tbroch) Re-enable once STM spi controller can be inhibited at boot so it
    doesn't interfere with HDMI loading its f/w */
 #undef CONFIG_SPI_FLASH
-#define CONFIG_SPI_MASTER_PORT 2
 #define CONFIG_SPI_CS_GPIO GPIO_PD_MCDP_SPI_CS_L
 #define CONFIG_USB
 #define CONFIG_USB_BOS
@@ -44,7 +42,7 @@
 #define CONFIG_USB_PD_IDENTITY_HW_VERS 1
 #define CONFIG_USB_PD_IDENTITY_SW_VERS 1
 #define CONFIG_USB_PD_LOGGING
-#undef  CONFIG_EVENT_LOG_SIZE
+#undef CONFIG_EVENT_LOG_SIZE
 #define CONFIG_EVENT_LOG_SIZE 256
 #define CONFIG_USB_PD_PORT_MAX_COUNT 1
 #define CONFIG_USB_PD_TCPC
@@ -73,7 +71,7 @@
 
 /* Timer selection */
 #define TIM_CLOCK32 2
-#define TIM_ADC     3
+#define TIM_ADC 3
 
 #include "gpio_signal.h"
 
@@ -96,14 +94,14 @@ enum usb_strings {
 };
 
 /* we are never a source : don't care about power supply */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  0 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 0 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 0 /* us */
 
 /* Define typical operating power and max power */
 #define PD_OPERATING_POWER_MW 1000
-#define PD_MAX_POWER_MW       1500
-#define PD_MAX_CURRENT_MA     300
-#define PD_MAX_VOLTAGE_MV     5000
+#define PD_MAX_POWER_MW 1500
+#define PD_MAX_CURRENT_MA 300
+#define PD_MAX_VOLTAGE_MV 5000
 
 #endif /* !__ASSEMBLER__ */
 
@@ -111,10 +109,10 @@ enum usb_strings {
 #define USB_DEV_CLASS USB_CLASS_BILLBOARD
 
 /* USB interface indexes (use define rather than enum to expand them) */
-#define USB_IFACE_COUNT     0
+#define USB_IFACE_COUNT 0
 
 /* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL   0
-#define USB_EP_COUNT     1
+#define USB_EP_CONTROL 0
+#define USB_EP_COUNT 1
 
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/hoho/build.mk b/board/hoho/build.mk
index 18799c3b9f..b6fbbe7a9e 100644
--- a/board/hoho/build.mk
+++ b/board/hoho/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
+# Copyright 2014 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -11,4 +11,4 @@ CHIP_FAMILY:=stm32f0
 CHIP_VARIANT:=stm32f07x
 
 board-y=board.o
-board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
+board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o usb_pd_pdo.o
diff --git a/board/hoho/ec.tasklist b/board/hoho/ec.tasklist
index 41fc047d6a..5a82344122 100644
--- a/board/hoho/ec.tasklist
+++ b/board/hoho/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/hoho/gpio.inc b/board/hoho/gpio.inc
index 6d0701ded1..56a4f8808e 100644
--- a/board/hoho/gpio.inc
+++ b/board/hoho/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
+ * Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/hoho/usb_pd_config.h b/board/hoho/usb_pd_config.h
index 2f01c275a8..5a7dfd12a6 100644
--- a/board/hoho/usb_pd_config.h
+++ b/board/hoho/usb_pd_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -49,7 +49,7 @@ static inline void spi_enable_clock(int port)
 
 #define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
 #define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
-#define TIM_CCR_CS  1
+#define TIM_CCR_CS 1
 #define EXTI_COMP_MASK(p) BIT(21)
 #define IRQ_COMP STM32_IRQ_COMP
 /* triggers packet detection on comparator falling edge */
@@ -88,9 +88,8 @@ static inline void pd_tx_enable(int port, int polarity)
 static inline void pd_tx_disable(int port, int polarity)
 {
 	/* output low on SPI TX (PB4) to disable the FET */
-	STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B)
-				   & ~(3 << (2*4)))
-				   |  (1 << (2*4));
+	STM32_GPIO_MODER(GPIO_B) =
+		(STM32_GPIO_MODER(GPIO_B) & ~(3 << (2 * 4))) | (1 << (2 * 4));
 	/* put the low level reference in Hi-Z */
 	gpio_set_level(GPIO_PD_CC1_TX_EN, 0);
 }
@@ -101,8 +100,8 @@ static inline void pd_select_polarity(int port, int polarity)
 	 * use the right comparator : CC1 -> PA1 (COMP1 INP)
 	 * use VrefInt / 2 as INM (about 600mV)
 	 */
-	STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK)
-		| STM32_COMP_CMP1EN | STM32_COMP_CMP1INSEL_VREF12;
+	STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK) |
+			 STM32_COMP_CMP1EN | STM32_COMP_CMP1INSEL_VREF12;
 }
 
 /* Initialize pins used for TX and put them in Hi-Z */
@@ -111,7 +110,9 @@ static inline void pd_tx_init(void)
 	gpio_config_module(MODULE_USB_PD, 1);
 }
 
-static inline void pd_set_host_mode(int port, int enable) {}
+static inline void pd_set_host_mode(int port, int enable)
+{
+}
 
 static inline void pd_config_init(int port, uint8_t power_role)
 {
diff --git a/board/hoho/usb_pd_pdo.c b/board/hoho/usb_pd_pdo.c
new file mode 100644
index 0000000000..c52179acfc
--- /dev/null
+++ b/board/hoho/usb_pd_pdo.c
@@ -0,0 +1,18 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "compile_time_macros.h"
+#include "usb_pd.h"
+#include "usb_pd_pdo.h"
+
+/* Source PDOs */
+const uint32_t pd_src_pdo[] = {};
+const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
+
+/* Fake PDOs : we just want our pre-defined voltages */
+const uint32_t pd_snk_pdo[] = {
+	PDO_FIXED(5000, 500, PDO_FIXED_COMM_CAP),
+};
+const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
diff --git a/board/hoho/usb_pd_pdo.h b/board/hoho/usb_pd_pdo.h
new file mode 100644
index 0000000000..e04c3aa677
--- /dev/null
+++ b/board/hoho/usb_pd_pdo.h
@@ -0,0 +1,17 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_BOARD_HOHO_USB_PD_PDO_H
+#define __CROS_EC_BOARD_HOHO_USB_PD_PDO_H
+
+#include "stdint.h"
+
+extern const uint32_t pd_src_pdo[0];
+extern const int pd_src_pdo_cnt;
+
+extern const uint32_t pd_snk_pdo[1];
+extern const int pd_snk_pdo_cnt;
+
+#endif /* __CROS_EC_BOARD_HOHO_USB_PD_PDO_H */
diff --git a/board/hoho/usb_pd_policy.c b/board/hoho/usb_pd_policy.c
index 4fe82320e8..baf05d0e71 100644
--- a/board/hoho/usb_pd_policy.c
+++ b/board/hoho/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,6 +7,7 @@
 #include "board.h"
 #include "common.h"
 #include "console.h"
+#include "cros_version.h"
 #include "ec_commands.h"
 #include "gpio.h"
 #include "hooks.h"
@@ -16,21 +17,12 @@
 #include "usb_api.h"
 #include "usb_bb.h"
 #include "usb_pd.h"
+#include "usb_pd_pdo.h"
+#include "usb_pd_tcpm.h"
 #include "util.h"
-#include "version.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-/* Source PDOs */
-const uint32_t pd_src_pdo[] = {};
-const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
-
-/* Fake PDOs : we just want our pre-defined voltages */
-const uint32_t pd_snk_pdo[] = {
-		PDO_FIXED(5000, 500, PDO_FIXED_COMM_CAP),
-};
-const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 /* Holds valid object position (opos) for entered mode */
 static int alt_mode[PD_AMODE_COUNT];
@@ -62,22 +54,18 @@ __override int pd_check_power_swap(int port)
 	return 0;
 }
 
-__override int pd_check_data_swap(int port,
-				  enum pd_data_role data_role)
+__override int pd_check_data_swap(int port, enum pd_data_role data_role)
 {
 	/* Always refuse data swap */
 	return 0;
 }
 
-__override void pd_check_pr_role(int port,
-				 enum pd_power_role pr_role,
+__override void pd_check_pr_role(int port, enum pd_power_role pr_role,
 				 int flags)
 {
 }
 
-__override void pd_check_dr_role(int port,
-				 enum pd_data_role dr_role,
-				 int flags)
+__override void pd_check_dr_role(int port, enum pd_data_role dr_role, int flags)
 {
 }
 /* ----------------- Vendor Defined Messages ------------------ */
@@ -90,8 +78,8 @@ const uint32_t vdo_idh = VDO_IDH(0, /* data caps as USB host */
 const uint32_t vdo_product = VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV);
 
 const uint32_t vdo_ama = VDO_AMA(CONFIG_USB_PD_IDENTITY_HW_VERS,
-				 CONFIG_USB_PD_IDENTITY_SW_VERS,
-				 0, 0, 0, 0, /* SS[TR][12] */
+				 CONFIG_USB_PD_IDENTITY_SW_VERS, 0, 0, 0,
+				 0, /* SS[TR][12] */
 				 0, /* Vconn power */
 				 0, /* Vconn power required */
 				 1, /* Vbus power required */
@@ -117,18 +105,16 @@ static int svdm_response_svids(int port, uint32_t *payload)
 #define OPOS_DP 1
 #define OPOS_GFU 1
 
-const uint32_t vdo_dp_modes[1] =  {
-	VDO_MODE_DP(0,		   /* UFP pin cfg supported : none */
+const uint32_t vdo_dp_modes[1] = {
+	VDO_MODE_DP(0, /* UFP pin cfg supported : none */
 		    MODE_DP_PIN_C, /* DFP pin cfg supported */
-		    1,		   /* no usb2.0	signalling in AMode */
-		    CABLE_PLUG,	   /* its a plug */
-		    MODE_DP_V13,   /* DPv1.3 Support, no Gen2 */
-		    MODE_DP_SNK)   /* Its a sink only */
+		    1, /* no usb2.0	signalling in AMode */
+		    CABLE_PLUG, /* its a plug */
+		    MODE_DP_V13, /* DPv1.3 Support, no Gen2 */
+		    MODE_DP_SNK) /* Its a sink only */
 };
 
-const uint32_t vdo_goog_modes[1] =  {
-	VDO_MODE_GOOGLE(MODE_GOOGLE_FU)
-};
+const uint32_t vdo_goog_modes[1] = { VDO_MODE_GOOGLE(MODE_GOOGLE_FU) };
 
 static int svdm_response_modes(int port, uint32_t *payload)
 {
@@ -150,13 +136,15 @@ static int dp_status(int port, uint32_t *payload)
 	if (opos != OPOS_DP)
 		return 0; /* nak */
 
-	payload[1] = VDO_DP_STATUS(0,                /* IRQ_HPD */
-				   (hpd == 1),       /* HPD_HI|LOW */
-				   0,		     /* request exit DP */
-				   0,		     /* request exit USB */
-				   0,		     /* MF pref */
+	payload[1] = VDO_DP_STATUS(0, /* IRQ_HPD */
+				   (hpd == 1), /* HPD_HI|LOW */
+				   0, /* request exit DP */
+				   0, /* request exit USB */
+				   0, /* MF pref */
 				   gpio_get_level(GPIO_PD_SBU_ENABLE),
-				   0,		     /* power low */
+				   0, /* power
+					 low
+				       */
 				   0x2);
 	return 2;
 }
@@ -194,9 +182,9 @@ static int svdm_enter_mode(int port, uint32_t *payload)
 	return rv;
 }
 
-int pd_alt_mode(int port, enum tcpm_transmit_type type, uint16_t svid)
+int pd_alt_mode(int port, enum tcpci_msg_type type, uint16_t svid)
 {
-	if (type != TCPC_TX_SOP)
+	if (type != TCPCI_MSG_SOP)
 		return 0;
 
 	if (svid == USB_SID_DISPLAYPORT)
@@ -235,8 +223,7 @@ const struct svdm_response svdm_rsp = {
 	.exit_mode = &svdm_exit_mode,
 };
 
-int pd_custom_vdm(int port, int cnt, uint32_t *payload,
-		  uint32_t **rpayload)
+int pd_custom_vdm(int port, int cnt, uint32_t *payload, uint32_t **rpayload)
 {
 	int rsize;
 
diff --git a/board/hoho/vif_override.xml b/board/hoho/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/hoho/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/homestar/base_detect.c b/board/homestar/base_detect.c
new file mode 100644
index 0000000000..7625db02d7
--- /dev/null
+++ b/board/homestar/base_detect.c
@@ -0,0 +1,233 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Homestar base detection code */
+
+#include "adc.h"
+#include "base_state.h"
+#include "board.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "timer.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+
+/* Make sure POGO VBUS starts later then PP3300_HUB when power on  */
+#define BASE_DETECT_EN_LATER_US (600 * MSEC)
+
+/* Base detection and debouncing */
+#define BASE_DETECT_EN_DEBOUNCE_US (350 * MSEC)
+#define BASE_DETECT_DIS_DEBOUNCE_US (20 * MSEC)
+
+/*
+ * If the base status is unclear (i.e. not within expected ranges, read
+ * the ADC value again every 500ms.
+ */
+#define BASE_DETECT_RETRY_US (500 * MSEC)
+
+/*
+ * Lid has 604K pull-up, base has 30.1K pull-down, so the
+ * ADC value should be around 30.1/(604+30.1)*3300 = 156
+ *
+ * We add a significant margin on the maximum value, due to noise on the line,
+ * especially when PWM is active. See b/64193554 for details.
+ */
+#define BASE_DETECT_MIN_MV 120
+#define BASE_DETECT_MAX_MV 300
+
+/* Minimum ADC value to indicate base is disconnected for sure */
+#define BASE_DETECT_DISCONNECT_MIN_MV 1500
+
+/*
+ * Base EC pulses detection pin for 500 us to signal out of band USB wake (that
+ * can be used to wake system from deep S3).
+ */
+#define BASE_DETECT_PULSE_MIN_US 400
+#define BASE_DETECT_PULSE_MAX_US 650
+
+static uint64_t base_detect_debounce_time;
+
+static void base_detect_deferred(void);
+DECLARE_DEFERRED(base_detect_deferred);
+
+enum base_status {
+	BASE_UNKNOWN = 0,
+	BASE_DISCONNECTED = 1,
+	BASE_CONNECTED = 2,
+};
+
+static enum base_status current_base_status;
+
+/*
+ * This function is called whenever there is a change in the base detect
+ * status. Actions taken include:
+ * 1. Change in power to base
+ * 2. Indicate mode change to host.
+ * 3. Indicate tablet mode to host. Current assumption is that if base is
+ * disconnected then the system is in tablet mode, else if the base is
+ * connected, then the system is not in tablet mode.
+ */
+static void base_detect_change(enum base_status status)
+{
+	int connected = (status == BASE_CONNECTED);
+
+	if (current_base_status == status)
+		return;
+
+	gpio_set_level(GPIO_EN_BASE, connected);
+	tablet_set_mode(!connected, TABLET_TRIGGER_BASE);
+	base_set_state(connected);
+	current_base_status = status;
+}
+
+/* Measure detection pin pulse duration (used to wake AP from deep S3). */
+static uint64_t pulse_start;
+static uint32_t pulse_width;
+
+static void print_base_detect_value(int v, int tmp_pulse_width)
+{
+	CPRINTS("%s = %d (pulse %d)", adc_channels[ADC_BASE_DET].name, v,
+		tmp_pulse_width);
+}
+
+static void base_detect_deferred(void)
+{
+	uint64_t time_now = get_time().val;
+	int v;
+	uint32_t tmp_pulse_width = pulse_width;
+
+	if (base_detect_debounce_time > time_now) {
+		hook_call_deferred(&base_detect_deferred_data,
+				   base_detect_debounce_time - time_now);
+		return;
+	}
+
+	v = adc_read_channel(ADC_BASE_DET);
+	if (v == ADC_READ_ERROR)
+		return;
+
+	print_base_detect_value(v, tmp_pulse_width);
+
+	if (v >= BASE_DETECT_MIN_MV && v <= BASE_DETECT_MAX_MV) {
+		if (current_base_status != BASE_CONNECTED) {
+			base_detect_change(BASE_CONNECTED);
+		} else if (tmp_pulse_width >= BASE_DETECT_PULSE_MIN_US &&
+			   tmp_pulse_width <= BASE_DETECT_PULSE_MAX_US) {
+			CPRINTS("Sending event to AP");
+			host_set_single_event(EC_HOST_EVENT_KEY_PRESSED);
+		}
+		return;
+	}
+
+	if (v >= BASE_DETECT_DISCONNECT_MIN_MV) {
+		base_detect_change(BASE_DISCONNECTED);
+		return;
+	}
+
+	/* Unclear base status, schedule again in a while. */
+	hook_call_deferred(&base_detect_deferred_data, BASE_DETECT_RETRY_US);
+}
+
+static inline int detect_pin_connected(enum gpio_signal det_pin)
+{
+	return gpio_get_level(det_pin) == 0;
+}
+
+void base_detect_interrupt(enum gpio_signal signal)
+{
+	uint64_t time_now = get_time().val;
+	int debounce_us;
+
+	if (detect_pin_connected(signal))
+		debounce_us = BASE_DETECT_EN_DEBOUNCE_US;
+	else
+		debounce_us = BASE_DETECT_DIS_DEBOUNCE_US;
+
+	if (base_detect_debounce_time <= time_now) {
+		/*
+		 * Detect and measure detection pin pulse, when base is
+		 * connected. Only a single pulse is measured over a debounce
+		 * period. If no pulse, or multiple pulses are detected,
+		 * pulse_width is set to 0.
+		 */
+		if (current_base_status == BASE_CONNECTED &&
+		    !detect_pin_connected(signal)) {
+			pulse_start = time_now;
+		} else {
+			pulse_start = 0;
+		}
+		pulse_width = 0;
+
+		hook_call_deferred(&base_detect_deferred_data, debounce_us);
+	} else {
+		if (current_base_status == BASE_CONNECTED &&
+		    detect_pin_connected(signal) && !pulse_width &&
+		    pulse_start) {
+			/* First pulse within period. */
+			pulse_width = time_now - pulse_start;
+		} else {
+			pulse_start = 0;
+			pulse_width = 0;
+		}
+	}
+
+	base_detect_debounce_time = time_now + debounce_us;
+}
+
+static void base_enable(void)
+{
+	/* Enable base detection interrupt. */
+	base_detect_debounce_time = get_time().val;
+	hook_call_deferred(&base_detect_deferred_data, BASE_DETECT_EN_LATER_US);
+	gpio_enable_interrupt(GPIO_BASE_DET_L);
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, base_enable, HOOK_PRIO_DEFAULT);
+
+static void base_disable(void)
+{
+	/*
+	 * Disable base detection interrupt and disable power to base.
+	 * Set the state UNKNOWN so the next startup will initialize a
+	 * correct state and notify AP.
+	 */
+	gpio_disable_interrupt(GPIO_BASE_DET_L);
+	base_detect_change(BASE_UNKNOWN);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, base_disable, HOOK_PRIO_DEFAULT);
+
+static void base_init(void)
+{
+	/*
+	 * If we jumped to this image and chipset is already in S0, enable
+	 * base.
+	 */
+	if (system_jumped_late() && chipset_in_state(CHIPSET_STATE_ON))
+		base_enable();
+}
+DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT + 1);
+
+void base_force_state(enum ec_set_base_state_cmd state)
+{
+	if (state == EC_SET_BASE_STATE_ATTACH) {
+		gpio_disable_interrupt(GPIO_BASE_DET_L);
+		base_detect_change(BASE_CONNECTED);
+		CPRINTS("BD forced connected");
+	} else if (state == EC_SET_BASE_STATE_DETACH) {
+		gpio_disable_interrupt(GPIO_BASE_DET_L);
+		base_detect_change(BASE_DISCONNECTED);
+		CPRINTS("BD forced disconnected");
+	} else {
+		base_enable();
+		CPRINTS("BD forced reset");
+	}
+}
diff --git a/board/homestar/battery.c b/board/homestar/battery.c
new file mode 100644
index 0000000000..01fdb29f6a
--- /dev/null
+++ b/board/homestar/battery.c
@@ -0,0 +1,219 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "common.h"
+#include "util.h"
+
+/*
+ * Battery info for all homestar battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+
+const struct board_batt_params board_battery_info[] = {
+	/* COSMX GH02047XL 333-1C-DA-A */
+	[BATTERY_GH02047XL_1C] = {
+		.fuel_gauge = {
+			.manuf_name = "333-1C-DA-A",
+			.device_name = "GH02047XL",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0002,
+				.disconnect_val = 0x0,
+			}
+		},
+		.batt_info = {
+			.voltage_max            = 8800, /* mV */
+			.voltage_normal         = 7700, /* mV */
+			.voltage_min            = 6000, /* mV */
+			.precharge_current      = 256,  /* mA */
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 45,
+			.charging_min_c         = 0,
+			.charging_max_c         = 45,
+			.discharging_min_c      = -10,
+			.discharging_max_c      = 60,
+			.vendor_param_start     = 0x70,
+		},
+	},
+	/* COSMX GH02047XL */
+	[BATTERY_GH02047XL] = {
+		.fuel_gauge = {
+			.manuf_name = "333-AC-DA-A",
+			.device_name = "GH02047XL",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0002,
+				.disconnect_val = 0x0,
+			}
+		},
+		.batt_info = {
+			.voltage_max            = 8800, /* mV */
+			.voltage_normal         = 7700, /* mV */
+			.voltage_min            = 6000, /* mV */
+			.precharge_current      = 256,  /* mA */
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 45,
+			.charging_min_c         = 0,
+			.charging_max_c         = 45,
+			.discharging_min_c      = -10,
+			.discharging_max_c      = 60,
+			.vendor_param_start     = 0x70,
+		},
+	},
+	/* COSMX DS02032XL */
+	[BATTERY_DS02032XL] = {
+		.fuel_gauge = {
+			.manuf_name = "333-AC-13-A",
+			.device_name = "DS02032XL",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0002,
+				.disconnect_val = 0x0,
+			}
+		},
+		.batt_info = {
+			.voltage_max            = 8800, /* mV */
+			.voltage_normal         = 7700, /* mV */
+			.voltage_min            = 6000, /* mV */
+			.precharge_current      = 256,  /* mA */
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 45,
+			.charging_min_c         = 0,
+			.charging_max_c         = 45,
+			.discharging_min_c      = -10,
+			.discharging_max_c      = 60,
+			.vendor_param_start     = 0x70,
+		},
+	},
+	/* SMP DS02032XL */
+	[BATTERY_DS02032XL_1C] = {
+		.fuel_gauge = {
+			.manuf_name = "333-1C-13-A",
+			.device_name = "DS02032XL",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0002,
+				.disconnect_val = 0x0,
+			}
+		},
+		.batt_info = {
+			.voltage_max            = 8800, /* mV */
+			.voltage_normal         = 7700, /* mV */
+			.voltage_min            = 6000, /* mV */
+			.precharge_current      = 256,  /* mA */
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 45,
+			.charging_min_c         = 0,
+			.charging_max_c         = 45,
+			.discharging_min_c      = -10,
+			.discharging_max_c      = 60,
+			.vendor_param_start     = 0x70,
+		},
+	},
+	/* Sunwoda L21D4PG0 */
+	[BATTERY_L21D4PG0] = {
+		.fuel_gauge = {
+			.manuf_name = "Sunwoda",
+			.device_name = "L21D4PG0",
+			.ship_mode = {
+				.reg_addr = 0x34,
+				.reg_data = { 0x0000, 0x1000 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x34,
+				.reg_mask = 0x0100,
+				.disconnect_val = 0x0,
+			}
+		},
+		.batt_info = {
+			.voltage_max            = 8900, /* mV */
+			.voltage_normal         = 7720, /* mV */
+			.voltage_min            = 6000, /* mV */
+			.precharge_current      = 274,  /* mA */
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 50,
+			.charging_min_c         = 0,
+			.charging_max_c         = 60,
+			.discharging_min_c      = -20,
+			.discharging_max_c      = 60,
+			.vendor_param_start     = 0x2f,
+		},
+	},
+	/* SMP L21M4PG0 */
+	[BATTERY_L21M4PG0] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP",
+			.device_name = "L21M4PG0",
+			.ship_mode = {
+				.reg_addr = 0x34,
+				.reg_data = { 0x0000, 0x1000 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x34,
+				.reg_mask = 0x0100,
+				.disconnect_val = 0x0,
+			}
+		},
+		.batt_info = {
+			.voltage_max            = 8900, /* mV */
+			.voltage_normal         = 7720, /* mV */
+			.voltage_min            = 6000, /* mV */
+			.precharge_current      = 274,  /* mA */
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 50,
+			.charging_min_c         = 0,
+			.charging_max_c         = 60,
+			.discharging_min_c      = -20,
+			.discharging_max_c      = 60,
+			.vendor_param_start     = 0x2f,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_L21D4PG0;
diff --git a/board/homestar/board.c b/board/homestar/board.c
new file mode 100644
index 0000000000..306fd7c2a3
--- /dev/null
+++ b/board/homestar/board.c
@@ -0,0 +1,663 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Homestar board-specific configuration */
+
+#include "adc_chip.h"
+#include "button.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "common.h"
+#include "driver/accel_bma2x2.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "driver/accelgyro_icm42607.h"
+#include "driver/accelgyro_icm_common.h"
+#include "driver/ln9310.h"
+#include "driver/ppc/sn5s330.h"
+#include "driver/tcpm/ps8xxx.h"
+#include "driver/tcpm/tcpci.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "keyboard_mkbp.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "peripheral_charger.h"
+#include "pi3usb9201.h"
+#include "power.h"
+#include "power/qcom.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "queue.h"
+#include "shi_chip.h"
+#include "switch.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "usbc_ppc.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+#define KS_DEBOUNCE_US (30 * MSEC) /* Debounce time for kickstand switch */
+
+/* Forward declaration */
+static void tcpc_alert_event(enum gpio_signal signal);
+static void usb0_evt(enum gpio_signal signal);
+static void usb1_evt(enum gpio_signal signal);
+static void ppc_interrupt(enum gpio_signal signal);
+static void board_connect_c0_sbu(enum gpio_signal s);
+static void switchcap_interrupt(enum gpio_signal signal);
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* GPIO Interrupt Handlers */
+static void tcpc_alert_event(enum gpio_signal signal)
+{
+	int port = -1;
+
+	switch (signal) {
+	case GPIO_USB_C0_PD_INT_ODL:
+		port = 0;
+		break;
+	case GPIO_USB_C1_PD_INT_ODL:
+		port = 1;
+		break;
+	default:
+		return;
+	}
+
+	schedule_deferred_pd_interrupt(port);
+}
+
+static void usb0_evt(enum gpio_signal signal)
+{
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+
+static void usb1_evt(enum gpio_signal signal)
+{
+	usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+}
+
+static void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_SWCTL_INT_ODL:
+		sn5s330_interrupt(0);
+		break;
+	case GPIO_USB_C1_SWCTL_INT_ODL:
+		sn5s330_interrupt(1);
+		break;
+	default:
+		break;
+	}
+}
+
+static void board_connect_c0_sbu_deferred(void)
+{
+	/*
+	 * If CCD_MODE_ODL asserts, it means there's a debug accessory connected
+	 * and we should enable the SBU FETs.
+	 */
+	ppc_set_sbu(0, 1);
+}
+DECLARE_DEFERRED(board_connect_c0_sbu_deferred);
+
+static void board_connect_c0_sbu(enum gpio_signal s)
+{
+	hook_call_deferred(&board_connect_c0_sbu_deferred_data, 0);
+}
+
+static void switchcap_interrupt(enum gpio_signal signal)
+{
+	ln9310_interrupt(signal);
+}
+
+/* I2C port map */
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_POWER_SCL,
+	  .sda = GPIO_EC_I2C_POWER_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C0_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C0_PD_SDA },
+	{ .name = "tcpc1",
+	  .port = I2C_PORT_TCPC1,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C1_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C1_PD_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_EEPROM_SCL,
+	  .sda = GPIO_EC_I2C_EEPROM_SDA },
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_SENSOR_SCL,
+	  .sda = GPIO_EC_I2C_SENSOR_SDA },
+};
+
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	/* Measure VBUS through a 1/10 voltage divider */
+	[ADC_VBUS] = { "VBUS", NPCX_ADC_CH1, ADC_MAX_VOLT * 10,
+		       ADC_READ_MAX + 1, 0 },
+	/*
+	 * Adapter current output or battery charging/discharging current (uV)
+	 * 18x amplification on charger side.
+	 */
+	[ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH2, ADC_MAX_VOLT * 1000 / 18,
+			    ADC_READ_MAX + 1, 0 },
+	/*
+	 * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read
+	 * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and
+	 * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we
+	 * only divide by 2 (enough to avoid precision issues).
+	 */
+	[ADC_PSYS] = { "PSYS", NPCX_ADC_CH3,
+		       ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), 2, 0 },
+	/* Base detection */
+	[ADC_BASE_DET] = { "BASE_DET", NPCX_ADC_CH5, ADC_MAX_VOLT,
+			   ADC_READ_MAX + 1, 0 },
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+const struct pwm_t pwm_channels[] = {
+	/* TODO(waihong): Assign a proper frequency. */
+	[PWM_CH_DISPLIGHT] = { .channel = 5, .flags = 0, .freq = 4800 },
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+/* LN9310 switchcap */
+const struct ln9310_config_t ln9310_config = {
+	.i2c_port = I2C_PORT_POWER,
+	.i2c_addr_flags = LN9310_I2C_ADDR_0_FLAGS,
+};
+
+/* Power Path Controller */
+struct ppc_config_t ppc_chips[] = {
+	{ .i2c_port = I2C_PORT_TCPC0,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
+	{ .i2c_port = I2C_PORT_TCPC1,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
+};
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/* TCPC mux configuration */
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TCPC0,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+	},
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TCPC1,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+	},
+};
+
+/*
+ * Port-0/1 USB mux driver.
+ *
+ * The USB mux is handled by TCPC chip and the HPD update is through a GPIO
+ * to AP. But the TCPC chip is also needed to know the HPD status; otherwise,
+ * the mux misbehaves.
+ */
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
+	},
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
+	}
+};
+
+/* BC1.2 */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	{
+		.i2c_port = I2C_PORT_POWER,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+	{
+		.i2c_port = I2C_PORT_EEPROM,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+};
+
+/* Mutexes */
+static struct mutex g_lid_mutex;
+
+static struct bmi_drv_data_t g_bmi160_data;
+static struct icm_drv_data_t g_icm42607_data;
+
+enum lid_accelgyro_type {
+	LID_GYRO_NONE = 0,
+	LID_GYRO_BMI160 = 1,
+	LID_GYRO_ICM42607 = 2,
+};
+
+static enum lid_accelgyro_type lid_accelgyro_config;
+
+/* Matrix to rotate accelerometer into standard reference frame */
+const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				      { 0, FLOAT_TO_FP(-1), 0 },
+				      { 0, 0, FLOAT_TO_FP(1) } };
+
+const mat33_fp_t lid_standard_ref_icm42607 = { { 0, FLOAT_TO_FP(1), 0 },
+					       { FLOAT_TO_FP(-1), 0, 0 },
+					       { 0, 0, FLOAT_TO_FP(1) } };
+
+struct motion_sensor_t icm42607_lid_accel = {
+	.name = "Lid Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM42607,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_LID,
+	.drv = &icm42607_drv,
+	.mutex = &g_lid_mutex,
+	.drv_data = &g_icm42607_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
+	.rot_standard_ref = &lid_standard_ref_icm42607,
+	.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
+	.min_frequency = ICM42607_ACCEL_MIN_FREQ,
+	.max_frequency = ICM42607_ACCEL_MAX_FREQ,
+	.config = {
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	},
+};
+
+struct motion_sensor_t icm42607_lid_gyro = {
+	.name = "Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM42607,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_LID,
+	.drv = &icm42607_drv,
+	.mutex = &g_lid_mutex,
+	.drv_data = &g_icm42607_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &lid_standard_ref_icm42607,
+	.min_frequency = ICM42607_GYRO_MIN_FREQ,
+	.max_frequency = ICM42607_GYRO_MAX_FREQ,
+};
+
+struct motion_sensor_t motion_sensors[] = {
+	/*
+	 * Note: bmi160: supports accelerometer and gyro sensor
+	 * Requirement: accelerometer sensor must init before gyro sensor
+	 * DO NOT change the order of the following table.
+	 */
+	[LID_ACCEL] = {
+	 .name = "Lid Accel",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_BMI160,
+	 .type = MOTIONSENSE_TYPE_ACCEL,
+	 .location = MOTIONSENSE_LOC_LID,
+	 .drv = &bmi160_drv,
+	 .mutex = &g_lid_mutex,
+	 .drv_data = &g_bmi160_data,
+	 .port = I2C_PORT_SENSOR,
+	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+	 .rot_standard_ref = &lid_standard_ref,
+	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
+	 .min_frequency = BMI_ACCEL_MIN_FREQ,
+	 .max_frequency = BMI_ACCEL_MAX_FREQ,
+	 .config = {
+		 [SENSOR_CONFIG_EC_S0] = {
+			 .odr = 10000 | ROUND_UP_FLAG,
+		 },
+	 },
+	},
+	[LID_GYRO] = {
+	 .name = "Gyro",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_BMI160,
+	 .type = MOTIONSENSE_TYPE_GYRO,
+	 .location = MOTIONSENSE_LOC_LID,
+	 .drv = &bmi160_drv,
+	 .mutex = &g_lid_mutex,
+	 .drv_data = &g_bmi160_data,
+	 .port = I2C_PORT_SENSOR,
+	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+	 .default_range = 1000, /* dps */
+	 .rot_standard_ref = &lid_standard_ref,
+	 .min_frequency = BMI_GYRO_MIN_FREQ,
+	 .max_frequency = BMI_GYRO_MAX_FREQ,
+	},
+};
+const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+static void board_detect_motionsensor(void)
+{
+	int val = -1;
+
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return;
+	if (lid_accelgyro_config != LID_GYRO_NONE)
+		return;
+
+	/* Check base accelgyro chip */
+	icm_read8(&icm42607_lid_accel, ICM42607_REG_WHO_AM_I, &val);
+	if (val == ICM42607_CHIP_ICM42607P) {
+		motion_sensors[LID_ACCEL] = icm42607_lid_accel;
+		motion_sensors[LID_GYRO] = icm42607_lid_gyro;
+		lid_accelgyro_config = LID_GYRO_ICM42607;
+		CPRINTS("LID Accelgyro: ICM42607");
+	} else {
+		lid_accelgyro_config = LID_GYRO_BMI160;
+		CPRINTS("LID Accelgyro: BMI160");
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_detect_motionsensor,
+	     HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_INIT, board_detect_motionsensor, HOOK_PRIO_DEFAULT + 1);
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	switch (lid_accelgyro_config) {
+	case LID_GYRO_ICM42607:
+		icm42607_interrupt(signal);
+		break;
+	case LID_GYRO_BMI160:
+	default:
+		bmi160_interrupt(signal);
+		break;
+	}
+}
+
+enum battery_cell_type board_get_battery_cell_type(void)
+{
+	return BATTERY_CELL_TYPE_2S;
+}
+
+static void board_switchcap_init(void)
+{
+	CPRINTS("Use switchcap: LN9310");
+
+	/* Configure and enable interrupt for LN9310 */
+	gpio_set_flags(GPIO_SWITCHCAP_PG_INT_L, GPIO_INT_FALLING);
+	gpio_enable_interrupt(GPIO_SWITCHCAP_PG_INT_L);
+
+	/* Only configure the switchcap if not sysjump */
+	if (!system_jumped_late()) {
+		ln9310_init();
+	}
+}
+
+/* Initialize board. */
+static void board_init(void)
+{
+	/* Enable BC1.2 interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_L);
+	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L);
+	gpio_enable_interrupt(GPIO_ACCEL_GYRO_INT_L);
+
+	/*
+	 * The H1 SBU line for CCD are behind PPC chip. The PPC internal FETs
+	 * for SBU may be disconnected after DP alt mode is off. Should enable
+	 * the CCD_MODE_ODL interrupt to make sure the SBU FETs are connected.
+	 */
+	gpio_enable_interrupt(GPIO_CCD_MODE_ODL);
+
+	/* Set the backlight duty cycle to 0. AP will override it later. */
+	pwm_set_duty(PWM_CH_DISPLIGHT, 0);
+
+	board_switchcap_init();
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+__overridable uint16_t board_get_ps8xxx_product_id(int port)
+{
+	if (check_ps8755_chip(port))
+		return PS8755_PRODUCT_ID;
+
+	return PS8805_PRODUCT_ID;
+}
+
+void board_tcpc_init(void)
+{
+	/* Only reset TCPC if not sysjump */
+	if (!system_jumped_late()) {
+		/* TODO(crosbug.com/p/61098): How long do we need to wait? */
+		board_reset_pd_mcu();
+	}
+
+	/* Enable PPC interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_SWCTL_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_SWCTL_INT_ODL);
+
+	/* Enable TCPC interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL);
+
+	/*
+	 * Initialize HPD to low; after sysjump SOC needs to see
+	 * HPD pulse to enable video path
+	 */
+	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
+		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
+
+void board_hibernate(void)
+{
+	int i;
+
+	/*
+	 * Sensors are unpowered in hibernate. Apply PD to the
+	 * interrupt lines such that they don't float.
+	 */
+	gpio_set_flags(GPIO_ACCEL_GYRO_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
+
+	/*
+	 * Board rev 1+ has the hardware fix. Don't need the following
+	 * workaround.
+	 */
+	if (system_get_board_version() >= 1)
+		return;
+
+	/*
+	 * Enable the PPC power sink path before EC enters hibernate;
+	 * otherwise, ACOK won't go High and can't wake EC up. Check the
+	 * bug b/170324206 for details.
+	 */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
+		ppc_vbus_sink_enable(i, 1);
+}
+
+/* Called on AP S0 -> S3 transition */
+static void board_chipset_suspend(void)
+{
+	/*
+	 * Turn off display backlight in S3. AP has its own control. The EC's
+	 * and the AP's will be AND'ed together in hardware.
+	 */
+	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 0);
+	pwm_enable(PWM_CH_DISPLIGHT, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S3 -> S0 transition */
+static void board_chipset_resume(void)
+{
+	/* Turn on display and keyboard backlight in S0. */
+	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 1);
+	if (pwm_get_duty(PWM_CH_DISPLIGHT))
+		pwm_enable(PWM_CH_DISPLIGHT, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
+
+void board_set_switchcap_power(int enable)
+{
+	gpio_set_level(GPIO_SWITCHCAP_ON_L, !enable);
+	ln9310_software_enable(enable);
+}
+
+int board_is_switchcap_enabled(void)
+{
+	return !gpio_get_level(GPIO_SWITCHCAP_ON_L);
+}
+
+int board_is_switchcap_power_good(void)
+{
+	return ln9310_power_good();
+}
+
+void board_reset_pd_mcu(void)
+{
+	cprints(CC_USB, "Resetting TCPCs...");
+	cflush();
+
+	gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
+	gpio_set_level(GPIO_USB_C1_PD_RST_L, 0);
+	msleep(PS8XXX_RESET_DELAY_MS);
+	gpio_set_level(GPIO_USB_C0_PD_RST_L, 1);
+	gpio_set_level(GPIO_USB_C1_PD_RST_L, 1);
+}
+
+void board_set_tcpc_power_mode(int port, int mode)
+{
+	/* Ignore the "mode" to turn the chip on.  We can only do a reset. */
+	if (mode)
+		return;
+
+	board_reset_pd_mcu();
+}
+
+int board_vbus_sink_enable(int port, int enable)
+{
+	/* Both ports are controlled by PPC SN5S330 */
+	return ppc_vbus_sink_enable(port, enable);
+}
+
+int board_is_sourcing_vbus(int port)
+{
+	/* Both ports are controlled by PPC SN5S330 */
+	return ppc_is_sourcing_vbus(port);
+}
+
+void board_overcurrent_event(int port, int is_overcurrented)
+{
+	/* TODO(b/120231371): Notify AP */
+	CPRINTS("p%d: overcurrent!", port);
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int i;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTS("Disabling all charging port");
+
+		/* Disable all ports. */
+		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (board_vbus_sink_enable(i, 0))
+				CPRINTS("Disabling p%d sink path failed.", i);
+		}
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (board_is_sourcing_vbus(port)) {
+		CPRINTS("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTS("New charge port: p%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		if (i == port)
+			continue;
+
+		if (board_vbus_sink_enable(i, 0))
+			CPRINTS("p%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (board_vbus_sink_enable(port, 1)) {
+		CPRINTS("p%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
+{
+	/*
+	 * Ignore lower charge ceiling on PD transition if our battery is
+	 * critical, as we may brownout.
+	 */
+	if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 &&
+	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
+		CPRINTS("Using max ilim %d", max_ma);
+		charge_ma = max_ma;
+	}
+
+	charge_set_input_current_limit(charge_ma, charge_mv);
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
+		if (gpio_get_level(GPIO_USB_C0_PD_RST_L))
+			status |= PD_STATUS_TCPC_ALERT_0;
+	if (!gpio_get_level(GPIO_USB_C1_PD_INT_ODL))
+		if (gpio_get_level(GPIO_USB_C1_PD_RST_L))
+			status |= PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
diff --git a/board/homestar/board.h b/board/homestar/board.h
new file mode 100644
index 0000000000..fff7ad7f77
--- /dev/null
+++ b/board/homestar/board.h
@@ -0,0 +1,123 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Homestar board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "baseboard.h"
+
+/* Free up flash space */
+#undef CONFIG_CONSOLE_CMDHELP
+
+#define CONFIG_BUTTON_TRIGGERED_RECOVERY
+
+/* Internal SPI flash on NPCX7 */
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */
+
+/* Switchcap */
+#define CONFIG_LN9310
+
+/* Battery */
+#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
+#define CONFIG_BATTERY_REVIVE_DISCONNECT
+#define CONFIG_BATTERY_FUEL_GAUGE
+#define CONFIG_BATTERY_VENDOR_PARAM
+
+/* charger margin */
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 5
+
+/* Enable PD3.0 */
+#define CONFIG_USB_PD_REV30
+
+/* BC 1.2 Charger */
+#define CONFIG_BC12_DETECT_PI3USB9201
+
+/* USB */
+#define CONFIG_USB_PD_TCPM_MULTI_PS8XXX
+#define CONFIG_USB_PD_TCPM_PS8755
+#define CONFIG_USB_PD_TCPM_PS8805
+#define CONFIG_USB_PD_TCPM_PS8805_FORCE_DID
+#define CONFIG_USBC_PPC_SN5S330
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+
+/* Lid accel/gyro */
+#define CONFIG_ACCELGYRO_BMI160
+#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
+#define OPT3001_I2C_ADDR_FLAGS OPT3001_I2C_ADDR1_FLAGS
+#define CONFIG_ACCELGYRO_ICM42607
+#define CONFIG_ACCELGYRO_ICM42607_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
+
+#define CONFIG_TABLET_MODE
+#define CONFIG_TABLET_MODE_SWITCH
+#define CONFIG_FRONT_PROXIMITY_SWITCH
+
+#define CONFIG_DETACHABLE_BASE
+#define CONFIG_BASE_ATTACHED_SWITCH
+
+/*
+ * Oled panel need to setup both vcc and backlight, AP will ctrl them.
+ * BL_DISABLE does not need to be controlled by ec.
+ */
+#ifdef CONFIG_BACKLIGHT_LID
+#undef CONFIG_BACKLIGHT_LID
+#endif
+
+/* GPIO alias */
+#define GPIO_AC_PRESENT GPIO_CHG_ACOK_OD
+#define GPIO_WP_L GPIO_EC_FLASH_WP_ODL
+#define GPIO_PMIC_RESIN_L GPIO_PM845_RESIN_L
+#define GPIO_SWITCHCAP_PG_INT_L GPIO_LN9310_INT
+
+#define CONFIG_MKBP_INPUT_DEVICES
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum adc_channel {
+	ADC_VBUS,
+	ADC_AMON_BMON,
+	ADC_PSYS,
+	ADC_BASE_DET,
+	ADC_CH_COUNT
+};
+
+/* Motion sensors */
+enum sensor_id {
+	LID_ACCEL = 0,
+	LID_GYRO,
+	SENSOR_COUNT,
+};
+
+enum pwm_channel { PWM_CH_DISPLIGHT = 0, PWM_CH_COUNT };
+
+/* List of possible batteries */
+enum battery_type {
+	BATTERY_GH02047XL_1C,
+	BATTERY_GH02047XL,
+	BATTERY_DS02032XL,
+	BATTERY_DS02032XL_1C,
+	BATTERY_L21D4PG0,
+	BATTERY_L21M4PG0,
+	BATTERY_TYPE_COUNT,
+};
+
+/* Reset all TCPCs. */
+void board_reset_pd_mcu(void);
+void board_set_tcpc_power_mode(int port, int mode);
+/* Base detection */
+void base_detect_interrupt(enum gpio_signal signal);
+
+void motion_interrupt(enum gpio_signal signal);
+
+#endif /* !defined(__ASSEMBLER__) */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/homestar/build.mk b/board/homestar/build.mk
new file mode 100644
index 0000000000..363ef59a16
--- /dev/null
+++ b/board/homestar/build.mk
@@ -0,0 +1,14 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx7
+CHIP_VARIANT:=npcx7m6fc
+BASEBOARD:=trogdor
+
+board-y=battery.o board.o led.o base_detect.o usbc_config.o
diff --git a/board/homestar/ec.tasklist b/board/homestar/ec.tasklist
new file mode 100644
index 0000000000..8fc8115afc
--- /dev/null
+++ b/board/homestar/ec.tasklist
@@ -0,0 +1,22 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/homestar/gpio.inc b/board/homestar/gpio.inc
new file mode 100644
index 0000000000..37e71977ac
--- /dev/null
+++ b/board/homestar/gpio.inc
@@ -0,0 +1,196 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+/* USB-C interrupts */
+GPIO_INT(USB_C0_PD_INT_ODL,    PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-0 TCPC */
+GPIO_INT(USB_C1_PD_INT_ODL,    PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-1 TCPC */
+GPIO_INT(USB_C0_SWCTL_INT_ODL, PIN(0, 3), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-0 PPC */
+GPIO_INT(USB_C1_SWCTL_INT_ODL, PIN(4, 0), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-1 PPC */
+GPIO_INT(USB_C0_BC12_INT_L,    PIN(6, 1), GPIO_INT_FALLING | GPIO_PULL_UP, usb0_evt)  /* Interrupt from port-0 BC1.2 */
+GPIO_INT(USB_C1_BC12_INT_L,    PIN(8, 2), GPIO_INT_FALLING | GPIO_PULL_UP, usb1_evt)  /* Interrupt from port-1 BC1.2 */
+
+/* System interrupts */
+GPIO_INT(CHG_ACOK_OD,       PIN(0, 0), GPIO_INT_BOTH, extpower_interrupt)  /* ACOK */
+GPIO_INT(CCD_MODE_ODL,      PIN(E, 3), GPIO_INT_FALLING, board_connect_c0_sbu)  /* Case Closed Debug Mode */
+GPIO_INT(EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)  /* Power button */
+GPIO_INT(EC_VOLDN_BTN_ODL,  PIN(7, 0), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Down button */
+GPIO_INT(EC_VOLUP_BTN_ODL,  PIN(F, 2), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Up button */
+GPIO_INT(EC_FLASH_WP_ODL,   PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)  /* Write protection */
+GPIO_INT(LID_OPEN_EC,       PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)  /* Lid open */
+GPIO_INT(AP_RST_L,          PIN(C, 1), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_ap_rst_interrupt)  /* PMIC to signal AP reset */
+GPIO_INT(PS_HOLD,           PIN(A, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, power_signal_interrupt)  /* Indicate when AP triggers reset/shutdown */
+GPIO_INT(AP_SUSPEND,        PIN(5, 7), GPIO_INT_BOTH, power_signal_interrupt)  /* Suspend signal from PMIC */
+GPIO_INT(DEPRECATED_AP_RST_REQ, PIN(C, 2), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V, power_signal_interrupt) /* Deprecated AP initiated reset indicator */
+
+/*
+ * When switch-cap is off, the POWER_GOOD signal is floating. Need a pull-down
+ * to make it low. Overload the interrupt function chipset_warm_reset_interrupt
+ * for not only signalling power_signal_interrupt but also handling the logic
+ * of WARM_RESET_L which is pulled-up by the same rail of POWER_GOOD.
+ */
+GPIO_INT(POWER_GOOD,        PIN(5, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, chipset_power_good_interrupt)  /* SRC_PP1800_S10A from PMIC */
+GPIO_INT(WARM_RESET_L,      PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_warm_reset_interrupt)  /* AP warm reset */
+GPIO_INT(AP_EC_SPI_CS_L,    PIN(5, 3), GPIO_INT_FALLING | GPIO_PULL_DOWN, shi_cs_event)  /* EC SPI Chip Select */
+
+GPIO_INT(BASE_DET_L,        PIN(3, 7), GPIO_INT_BOTH, base_detect_interrupt)  /* Detachable base attached? */
+
+/* Sensor interrupts */
+GPIO_INT(ACCEL_GYRO_INT_L,  PIN(A, 0), GPIO_INT_FALLING, motion_interrupt)  /* Accelerometer/gyro interrupt */
+
+/* Switchcap, for LN9310, it is the interrupt line of LN9310. */
+GPIO_INT(LN9310_INT,      PIN(E, 2), GPIO_INT_FALLING, switchcap_interrupt)
+
+/*
+ * EC_RST_ODL acts as a wake source from hibernate mode. However, it does not
+ * need to be an interrupt for normal EC operations. Simply set it an INPUT.
+ */
+GPIO(EC_RST_ODL,            PIN(0, 2), GPIO_INPUT)     /* EC reset */
+GPIO(EC_ENTERING_RW,        PIN(E, 1), GPIO_OUT_LOW)   /* Indicate when EC is entering RW code */
+GPIO(EC_BATT_PRES_ODL,      PIN(E, 5), GPIO_INPUT)     /* Battery Present */
+
+/* PMIC/AP 1.8V */
+GPIO(PM845_RESIN_L,         PIN(3, 2), GPIO_ODR_HIGH)  /* PMIC reset trigger */
+GPIO(PMIC_KPD_PWR_ODL,      PIN(D, 6), GPIO_ODR_HIGH)  /* PMIC power button */
+GPIO(EC_INT_L,              PIN(A, 2), GPIO_ODR_HIGH)  /* Interrupt line between AP and EC */
+GPIO(QSIP_ON,               PIN(5, 0), GPIO_OUT_LOW)   /* Not used, for non-switchcap testing */
+
+/* Power enables */
+GPIO(HIBERNATE_L,           PIN(5, 2), GPIO_ODR_HIGH)  /* EC hibernate */
+GPIO(SWITCHCAP_ON_L,        PIN(D, 5), GPIO_ODR_HIGH)  /* Enable switch cap */
+GPIO(EN_PP3300_A,           PIN(A, 6), GPIO_OUT_LOW)   /* Enable PP3300 */
+GPIO(EN_PP5000_A,           PIN(6, 7), GPIO_OUT_LOW)   /* Enable PP5000 */
+GPIO(EC_BL_DISABLE_L,       PIN(B, 6), GPIO_OUT_LOW)   /* Backlight disable signal from EC */
+
+/* Base detection */
+GPIO(EN_BASE,               PIN(0, 4), GPIO_OUT_LOW)   /* Enable power to detachable base */
+
+/* POGO */
+GPIO(POGO_VBUS_PRESENT,     PIN(6, 2), GPIO_INPUT)    /* POGO PIN */
+
+/* USB-C */
+GPIO(USB_C0_PD_RST_L,       PIN(F, 1), GPIO_ODR_HIGH)  /* Port-0 TCPC chip reset, actaully Open-Drain */
+GPIO(USB_C1_PD_RST_L,       PIN(E, 4), GPIO_ODR_HIGH)  /* Port-1 TCPC chip reset, actually Open-Drain */
+GPIO(DP_MUX_OE_L,           PIN(9, 6), GPIO_ODR_HIGH)  /* DP mux enable, actually Open-Drain */
+GPIO(DP_MUX_SEL,            PIN(4, 5), GPIO_OUT_LOW)   /* DP mux selection: L:C0, H:C1 */
+GPIO(DP_HOT_PLUG_DET,       PIN(9, 5), GPIO_OUT_LOW)   /* DP HPD to AP */
+
+/* LEDs */
+GPIO(EC_CHG_LED_R_C0,       PIN(C, 3), GPIO_OUT_LOW)
+GPIO(EC_CHG_LED_G_C0,       PIN(C, 4), GPIO_OUT_LOW)
+
+/*
+ * SPI host interface - enable PDs by default. These will be made functional
+ * by the SHI driver when the AP powers up, and restored back to GPIO when
+ * the AP powers down.
+ */
+GPIO(AP_EC_SPI_MOSI,        PIN(4, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(AP_EC_SPI_MISO,        PIN(4, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(AP_EC_SPI_CLK,         PIN(5, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+
+/* PWM */
+GPIO(EDP_BKLTCTL,           PIN(B, 7), GPIO_INPUT)     /* PWM5 */
+GPIO(WCAM_EC_VSYNC,         PIN(C, 0), GPIO_INPUT)     /* PWM6 */
+GPIO(FCAM_EC_VSYNC,         PIN(6, 0), GPIO_INPUT)     /* PWM7 */
+
+/* ADC */
+GPIO(PPVAR_BOOSTIN_SENSE,   PIN(4, 4), GPIO_INPUT)     /* ADC1 */
+GPIO(CHARGER_IADP,          PIN(4, 3), GPIO_INPUT)     /* ADC2 */
+GPIO(CHARGER_PMON,          PIN(4, 2), GPIO_INPUT)     /* ADC3 */
+
+/* I2C */
+GPIO(EC_I2C_POWER_SCL,      PIN(B, 5), GPIO_INPUT)
+GPIO(EC_I2C_POWER_SDA,      PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_PD_SCL,  PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_PD_SDA,  PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_PD_SCL,  PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_PD_SDA,  PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SCL,     PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SDA,     PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,     PIN(B, 3), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SENSOR_SDA,     PIN(B, 2), GPIO_INPUT | GPIO_SEL_1P8V)
+
+/* Board/SKU IDs */
+GPIO(BRD_ID0,               PIN(C, 7), GPIO_INPUT)
+GPIO(BRD_ID1,               PIN(9, 3), GPIO_INPUT)
+GPIO(BRD_ID2,               PIN(6, 3), GPIO_INPUT)
+GPIO(SKU_ID0,               PIN(F, 0), GPIO_INPUT)
+GPIO(SKU_ID1,               PIN(4, 1), GPIO_INPUT)
+GPIO(SKU_ID2,               PIN(D, 4), GPIO_INPUT)
+
+/* Special straps */
+GPIO(ARM_X86,               PIN(6, 6), GPIO_OUT_LOW)  /* NC, low for power saving */
+
+/* Unused GPIOs, NC. Apply PU for power saving */
+UNUSED(PIN(5, 1))
+UNUSED(PIN(F, 3))
+UNUSED(PIN(3, 1))
+UNUSED(PIN(3, 0))
+UNUSED(PIN(2, 7))
+UNUSED(PIN(2, 6))
+UNUSED(PIN(2, 5))
+UNUSED(PIN(2, 4))
+UNUSED(PIN(2, 3))
+UNUSED(PIN(2, 2))
+UNUSED(PIN(2, 1))
+UNUSED(PIN(2, 0))
+UNUSED(PIN(1, 7))
+UNUSED(PIN(1, 6))
+UNUSED(PIN(1, 5))
+UNUSED(PIN(1, 4))
+UNUSED(PIN(1, 3))
+UNUSED(PIN(1, 2))
+UNUSED(PIN(1, 1))
+UNUSED(PIN(1, 0))
+UNUSED(PIN(0, 7))
+UNUSED(PIN(0, 6))
+UNUSED(PIN(0, 5))
+UNUSED(PIN(9, 4))
+UNUSED(PIN(9, 7))
+UNUSED(PIN(A, 7))
+UNUSED(PIN(B, 0))
+UNUSED(PIN(A, 5))
+UNUSED(PIN(3, 5))
+UNUSED(PIN(7, 2))
+UNUSED(PIN(8, 1))
+UNUSED(PIN(7, 6))
+UNUSED(PIN(3, 4))
+UNUSED(PIN(C, 5))
+UNUSED(PIN(C, 6))
+UNUSED(PIN(A, 3))
+UNUSED(PIN(8, 3))
+UNUSED(PIN(B, 1))
+UNUSED(PIN(5, 6))
+UNUSED(PIN(8, 0))
+UNUSED(PIN(D, 0))
+UNUSED(PIN(D, 1))
+UNUSED(PIN(D, 3))
+UNUSED(PIN(7, 5))
+UNUSED(PIN(8, 6))
+UNUSED(PIN(7, 3))
+UNUSED(PIN(7, 4))
+UNUSED(PIN(D, 7))
+UNUSED(PIN(8, 5))
+
+/* Alternate functions GPIO definitions */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)            /* UART (GPIO64/65) */
+ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0)             /* I2C0 (GPIOB4/B5) */
+ALTERNATE(PIN_MASK(9, 0x07), 1, MODULE_I2C, 0)             /* I2C1 SDA (GPIO90), I2C2 (GPIO91/92) */
+ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, 0)             /* I2C1 SCL (GPIO87) */
+ALTERNATE(PIN_MASK(3, 0x48), 1, MODULE_I2C, 0)             /* I2C5 (GPIO33/36) */
+ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, GPIO_SEL_1P8V) /* I2C7 (GPIOB2/B3) - 1.8V */
+ALTERNATE(PIN_MASK(4, 0x1C), 0, MODULE_ADC, 0)             /* ADC1 (GPIO44), ADC2 (GPIO43), ADC3 (GPIO42) */
+ALTERNATE(PIN_MASK(4, 0xC0), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SDO (GPIO47), SHI_SDI (GPIO46) */
+ALTERNATE(PIN_MASK(5, 0x28), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SCLK (GPIO55), SHI_CS# (GPIO53) */
+ALTERNATE(PIN_MASK(B, 0x80), 1, MODULE_PWM, 0)             /* PWM5 (GPIOB7) - EDP_BKLTCTL */
+/* TODO(Camera?) should have a poper config for this, PWM or not */
+ALTERNATE(PIN_MASK(C, 0x01), 1, MODULE_PWM, 0)             /* PWM6 (GPIOC0) - WCAM_EC_VSYNC */
+ALTERNATE(PIN_MASK(6, 0x01), 1, MODULE_PWM, 0)             /* PWM7 (GPIO60) - FCAM_EC_VSYNC */
+
+
diff --git a/board/homestar/led.c b/board/homestar/led.c
new file mode 100644
index 0000000000..0b6f177b5a
--- /dev/null
+++ b/board/homestar/led.c
@@ -0,0 +1,163 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power and battery LED control.
+ */
+
+#include "battery.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "chipset.h"
+#include "ec_commands.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "led_common.h"
+#include "system.h"
+#include "util.h"
+
+#define LED_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS)
+/* Battery LED blinks every per 400ms */
+#define LED_HALF_ONE_SEC (500 / HOOK_TICK_INTERVAL_MS)
+
+#define BAT_LED_ON 1
+#define BAT_LED_OFF 0
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_BATTERY_LED,
+};
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+enum led_color {
+	LED_OFF = 0,
+	LED_RED,
+	LED_GREEN,
+	LED_AMBER,
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
+};
+
+static void led_set_color(enum led_color color)
+{
+	gpio_set_level(GPIO_EC_CHG_LED_R_C0,
+		       (color == LED_RED) ? BAT_LED_ON : BAT_LED_OFF);
+	gpio_set_level(GPIO_EC_CHG_LED_G_C0,
+		       (color == LED_GREEN) ? BAT_LED_ON : BAT_LED_OFF);
+	if (color == LED_AMBER) {
+		gpio_set_level(GPIO_EC_CHG_LED_R_C0, BAT_LED_ON);
+		gpio_set_level(GPIO_EC_CHG_LED_G_C0, BAT_LED_ON);
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	brightness_range[EC_LED_COLOR_RED] = 1;
+	brightness_range[EC_LED_COLOR_GREEN] = 1;
+	brightness_range[EC_LED_COLOR_AMBER] = 1;
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (brightness[EC_LED_COLOR_RED] != 0)
+		led_set_color(LED_RED);
+	else if (brightness[EC_LED_COLOR_GREEN] != 0)
+		led_set_color(LED_GREEN);
+	else if (brightness[EC_LED_COLOR_AMBER] != 0)
+		led_set_color(LED_AMBER);
+	else
+		led_set_color(LED_OFF);
+
+	return EC_SUCCESS;
+}
+
+static void board_led_set_battery(void)
+{
+	static int battery_ticks;
+	int color = LED_OFF;
+	int period = 0;
+	int percent = DIV_ROUND_NEAREST(charge_get_display_charge(), 10);
+
+	battery_ticks++;
+
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
+	case LED_PWRS_CHARGE_NEAR_FULL:
+		if (chipset_in_state(CHIPSET_STATE_ON |
+				     CHIPSET_STATE_ANY_SUSPEND |
+				     CHIPSET_STATE_ANY_OFF)) {
+			if (percent <= BATTERY_LEVEL_CRITICAL) {
+				/* battery capa <= 5%, Red */
+				color = LED_RED;
+			} else if (percent > BATTERY_LEVEL_CRITICAL &&
+				   percent < CONFIG_BATT_HOST_FULL_FACTOR) {
+				/* 5% < battery capa < 97%, Orange */
+				color = LED_AMBER;
+			} else {
+				/* battery capa >= 97%, Green */
+				color = LED_GREEN;
+			}
+		}
+		break;
+	case LED_PWRS_DISCHARGE:
+		/* Always indicate off on when discharging */
+		color = LED_OFF;
+		break;
+	case LED_PWRS_ERROR:
+		/* Battery error, Red on 1sec off 1sec */
+		period = (1 + 1) * LED_ONE_SEC;
+		battery_ticks = battery_ticks % period;
+		if (battery_ticks < 1 * LED_ONE_SEC)
+			color = LED_RED;
+		else
+			color = LED_OFF;
+		break;
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		color = LED_RED;
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		/* Factory mode, Red 2 sec, green 2 sec */
+		period = (2 + 2) * LED_ONE_SEC;
+		battery_ticks = battery_ticks % period;
+		if (battery_ticks < 2 * LED_ONE_SEC)
+			color = LED_RED;
+		else
+			color = LED_GREEN;
+		break;
+	default:
+		/* Other states don't alter LED behavior */
+		break;
+	}
+
+	led_set_color(color);
+}
+
+/* Called by hook task every TICK */
+static void led_tick(void)
+{
+	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
+		board_led_set_battery();
+}
+DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
+
+void led_control(enum ec_led_id led_id, enum ec_led_state state)
+{
+	enum led_color color;
+
+	if ((led_id != EC_LED_ID_RECOVERY_HW_REINIT_LED) &&
+	    (led_id != EC_LED_ID_SYSRQ_DEBUG_LED))
+		return;
+
+	if (state == LED_STATE_RESET) {
+		led_auto_control(EC_LED_ID_BATTERY_LED, 1);
+		board_led_set_battery();
+		return;
+	}
+
+	color = state ? LED_RED : LED_OFF;
+
+	led_auto_control(EC_LED_ID_BATTERY_LED, 0);
+
+	led_set_color(color);
+}
diff --git a/board/homestar/usbc_config.c b/board/homestar/usbc_config.c
new file mode 100644
index 0000000000..28f6b7a1c9
--- /dev/null
+++ b/board/homestar/usbc_config.c
@@ -0,0 +1,61 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Trogdor family-specific USB-C configuration */
+
+#include "charge_state.h"
+#include "charger.h"
+#include "charger/isl923x_public.h"
+#include "console.h"
+#include "usb_pd.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+};
+
+int charger_profile_override(struct charge_state_data *curr)
+{
+	int usb_mv;
+	int port;
+
+	if (curr->state != ST_CHARGE)
+		return 0;
+
+	/* Lower the max requested voltage to 5V when battery is full. */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
+	    !(curr->batt.flags & BATT_FLAG_BAD_STATUS) &&
+	    !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
+	    (curr->batt.status & STATUS_FULLY_CHARGED))
+		usb_mv = 5000;
+	else
+		usb_mv = PD_MAX_VOLTAGE_MV;
+
+	if (pd_get_max_voltage() != usb_mv) {
+		CPRINTS("VBUS limited to %dmV", usb_mv);
+		for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++)
+			pd_set_external_voltage_limit(port, usb_mv);
+	}
+
+	return 0;
+}
+
+enum ec_status charger_profile_override_get_param(uint32_t param,
+						  uint32_t *value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+enum ec_status charger_profile_override_set_param(uint32_t param,
+						  uint32_t value)
+{
+	return EC_RES_INVALID_PARAM;
+}
diff --git a/board/homestar/vif_override.xml b/board/homestar/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/homestar/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/host/battery.c b/board/host/battery.c
index 1228485ab7..ff87a118b7 100644
--- a/board/host/battery.c
+++ b/board/host/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -6,6 +6,7 @@
  */
 
 #include "battery.h"
+#include "battery_fuel_gauge.h"
 #include "battery_smart.h"
 #include "common.h"
 #include "console.h"
@@ -14,16 +15,15 @@
 
 static uint16_t mock_smart_battery[SB_MANUFACTURER_DATA + 1];
 
-int sb_i2c_xfer(int port, uint16_t slave_addr_flags,
-		const uint8_t *out, int out_size,
+int sb_i2c_xfer(int port, uint16_t addr_flags, const uint8_t *out, int out_size,
 		uint8_t *in, int in_size, int flags)
 {
 	if (out_size == 0)
 		return EC_SUCCESS;
 
-	if (port != I2C_PORT_BATTERY || slave_addr_flags != BATTERY_ADDR_FLAGS)
+	if (port != I2C_PORT_BATTERY || addr_flags != BATTERY_ADDR_FLAGS)
 		return EC_ERROR_INVAL;
-	if (out[0]  >= ARRAY_SIZE(mock_smart_battery))
+	if (out[0] >= ARRAY_SIZE(mock_smart_battery))
 		return EC_ERROR_UNIMPLEMENTED;
 	if (out_size == 1) {
 		/* Read */
@@ -56,12 +56,12 @@ static const struct battery_info bat_info = {
 	 *   normal = 7.4V
 	 *   min    = 6.0V
 	 */
-	.voltage_max    = 8400,
+	.voltage_max = 8400,
 	.voltage_normal = 7400,
-	.voltage_min    = 6000,
+	.voltage_min = 6000,
 
 	/* Pre-charge current: I <= 0.01C */
-	.precharge_current  = 64, /* mA */
+	.precharge_current = 64, /* mA */
 
 	/*
 	 * Operational temperature range
@@ -70,10 +70,10 @@ static const struct battery_info bat_info = {
 	 */
 	.start_charging_min_c = 0,
 	.start_charging_max_c = 50,
-	.charging_min_c       = 0,
-	.charging_max_c       = 50,
-	.discharging_min_c    = -20,
-	.discharging_max_c    = 60,
+	.charging_min_c = 0,
+	.charging_max_c = 50,
+	.discharging_min_c = -20,
+	.discharging_max_c = 60,
 };
 
 const struct battery_info *battery_get_info(void)
diff --git a/board/host/board.c b/board/host/board.c
index 25abd9a0ad..00367a5a54 100644
--- a/board/host/board.c
+++ b/board/host/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,13 +13,15 @@
 #include "i2c.h"
 #include "inductive_charging.h"
 #include "lid_switch.h"
-#include "motion_sense.h"
 #include "motion_lid.h"
+#include "motion_sense.h"
 #include "power_button.h"
 #include "spi.h"
+#include "tablet_mode.h"
 #include "temp_sensor.h"
 #include "test_util.h"
 #include "timer.h"
+#include "usb_pd_tcpm.h"
 #include "util.h"
 
 /*
@@ -27,10 +29,15 @@
  * GPIO ports.  This maps back to 0, which is then ignored by the host GPIO mock
  * code.
  */
-#define GPIO_0  0
+#define GPIO_0 0
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
+test_mockable const struct tcpc_config_t tcpc_config[] = {
+	[0] = {},
+};
+
 test_mockable enum battery_present battery_is_present(void)
 {
 	return BP_YES;
@@ -43,10 +50,10 @@ test_mockable_static int mock_temp_get_val(int idx, int *temp_ptr)
 }
 
 const struct temp_sensor_t temp_sensors[] = {
-	{"CPU", TEMP_SENSOR_TYPE_CPU, mock_temp_get_val, 0},
-	{"Board", TEMP_SENSOR_TYPE_BOARD, mock_temp_get_val, 1},
-	{"Case", TEMP_SENSOR_TYPE_CASE, mock_temp_get_val, 2},
-	{"Battery", TEMP_SENSOR_TYPE_BOARD, mock_temp_get_val, 3},
+	{ "CPU", TEMP_SENSOR_TYPE_CPU, mock_temp_get_val, 0 },
+	{ "Board", TEMP_SENSOR_TYPE_BOARD, mock_temp_get_val, 1 },
+	{ "Case", TEMP_SENSOR_TYPE_CASE, mock_temp_get_val, 2 },
+	{ "Battery", TEMP_SENSOR_TYPE_BOARD, mock_temp_get_val, 3 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -58,24 +65,46 @@ test_mockable void fps_event(enum gpio_signal signal)
 {
 }
 
+test_mockable void gmr_tablet_switch_isr(enum gpio_signal signal)
+{
+}
+
 #ifdef CONFIG_I2C
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
 #ifdef I2C_PORT_BATTERY
-	{"battery", I2C_PORT_BATTERY, 100,  0, 0},
+	{ .name = "battery",
+	  .port = I2C_PORT_BATTERY,
+	  .kbps = 100,
+	  .scl = 0,
+	  .sda = 0 },
 #elif defined I2C_PORT_LIGHTBAR
-	{"lightbar", I2C_PORT_LIGHTBAR, 100,  0, 0},
+	{ .name = "lightbar",
+	  .port = I2C_PORT_LIGHTBAR,
+	  .kbps = 100,
+	  .scl = 0,
+	  .sda = 0 },
 #elif defined I2C_PORT_HOST_TCPC
-	{"tcpc", I2C_PORT_HOST_TCPC, 100,  0, 0},
+	{ .name = "tcpc",
+	  .port = I2C_PORT_HOST_TCPC,
+	  .kbps = 100,
+	  .scl = 0,
+	  .sda = 0 },
 #elif defined I2C_PORT_EEPROM
-	{"eeprom", I2C_PORT_EEPROM, 100, 0, 0},
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 100,
+	  .scl = 0,
+	  .sda = 0 },
+#elif defined I2C_PORT_WLC
+	{ .name = "wlc", .port = I2C_PORT_WLC, .kbps = 100, .scl = 0, .sda = 0 },
 #endif
 };
 
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 #endif
 
-#ifdef CONFIG_SPI_MASTER
+#ifdef CONFIG_SPI_CONTROLLER
 /* SPI devices */
 const struct spi_device_t spi_devices[] = {
 	/* Fingerprint sensor (SCLK at 4Mhz) */
@@ -102,11 +131,10 @@ int board_get_entropy(void *buffer, int len)
 }
 #endif
 
-static uint8_t eeprom[CBI_EEPROM_SIZE];
+static uint8_t eeprom[CBI_IMAGE_SIZE];
 
-int eeprom_i2c_xfer(int port, uint16_t addr_flags,
-		    const uint8_t *out, int out_size,
-		    uint8_t *in, int in_size, int flags)
+int eeprom_i2c_xfer(int port, uint16_t addr_flags, const uint8_t *out,
+		    int out_size, uint8_t *in, int in_size, int flags)
 {
 	static int offset;
 
diff --git a/board/host/board.h b/board/host/board.h
index 0eafedc2bc..eb6eecb14e 100644
--- a/board/host/board.h
+++ b/board/host/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,7 +12,7 @@
 /* Default-yes, override to no by including fake_battery module. */
 #define CONFIG_BATTERY_PRESENT_CUSTOM
 #undef CONFIG_CMD_PD
-#define CONFIG_CROS_BOARD_INFO
+#define CONFIG_CBI_EEPROM
 #define CONFIG_EXTPOWER_GPIO
 #undef CONFIG_FMAP
 #define CONFIG_POWER_BUTTON
@@ -30,6 +30,8 @@
 #define CONFIG_USB_PD_CUSTOM_PDO
 #define CONFIG_USB_PD_DUAL_ROLE
 
+#define CONFIG_CMD_AP_RESET_LOG
+
 #include "gpio_signal.h"
 
 enum temp_sensor_id {
@@ -44,10 +46,13 @@ enum temp_sensor_id {
 enum adc_channel {
 	ADC_CH_CHARGER_CURRENT,
 	ADC_AC_ADAPTER_ID_VOLTAGE,
+	ADC_VBUS,
 
 	ADC_CH_COUNT
 };
 
+enum cec_port { CEC_PORT_0, CEC_PORT_COUNT };
+
 /* Fake test charge suppliers */
 enum {
 	CHARGE_SUPPLIER_TEST1,
@@ -64,25 +69,25 @@ enum {
 };
 
 /* Standard-current Rp */
-#define PD_SRC_VNC           PD_SRC_DEF_VNC_MV
-#define PD_SRC_RD_THRESHOLD  PD_SRC_DEF_RD_THRESH_MV
+#define PD_SRC_VNC PD_SRC_DEF_VNC_MV
+#define PD_SRC_RD_THRESHOLD PD_SRC_DEF_RD_THRESH_MV
 
 /* delay necessary for the voltage transition on the power supply */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  20000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 20000 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 20000 /* us */
 
 /* Define typical operating power and max power */
 #define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       60000
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_VOLTAGE_MV     20000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
-#define PD_MIN_CURRENT_MA     500
-#define PD_MIN_POWER_MW       7500
+#define PD_MIN_CURRENT_MA 500
+#define PD_MIN_POWER_MW 7500
 
 /* Configuration for fake Fingerprint Sensor */
-#define CONFIG_SPI_MASTER
-#define CONFIG_SPI_FP_PORT    1 /* SPI1: third master config */
+#define CONFIG_SPI_CONTROLLER
+#define CONFIG_SPI_FP_PORT 1 /* SPI1: third master config */
 
 #define CONFIG_RNG
 void fps_event(enum gpio_signal signal);
@@ -90,8 +95,8 @@ void fps_event(enum gpio_signal signal);
 #define CONFIG_CRC8
 
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
-#define I2C_PORT_EEPROM		0
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define CONFIG_I2C_CONTROLLER
+#define I2C_PORT_EEPROM 0
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/host/build.mk b/board/host/build.mk
index 241f197342..c17ed65d95 100644
--- a/board/host/build.mk
+++ b/board/host/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
+# Copyright 2013 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -12,4 +12,5 @@ board-y=board.o
 board-$(HAS_TASK_CHIPSET)+=chipset.o
 board-$(CONFIG_BATTERY_MOCK)+=battery.o charger.o
 board-$(CONFIG_FANS)+=fan.o
-board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o usb_pd_config.o
+board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o usb_pd_config.o usb_pd_pdo.o
+board-$(CONFIG_CEC)+=cec.o
diff --git a/board/host/cec.c b/board/host/cec.c
new file mode 100644
index 0000000000..f0a86a591e
--- /dev/null
+++ b/board/host/cec.c
@@ -0,0 +1,62 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Mock CEC driver.
+ */
+
+#include "cec.h"
+#include "util.h"
+
+static int mock_cec_send(int port, const uint8_t *msg, uint8_t len)
+{
+	return EC_SUCCESS;
+}
+
+static int mock_cec_get_received_message(int port, uint8_t **msg, uint8_t *len)
+{
+	return EC_SUCCESS;
+}
+
+static int mock_cec_get_enable(int port, uint8_t *enable)
+{
+	return EC_SUCCESS;
+}
+
+static int mock_cec_set_enable(int port, uint8_t enable)
+{
+	return EC_SUCCESS;
+}
+
+static int mock_cec_get_logical_addr(int port, uint8_t *logical_addr)
+{
+	return EC_SUCCESS;
+}
+
+static int mock_cec_set_logical_addr(int port, uint8_t logical_addr)
+{
+	return EC_SUCCESS;
+}
+
+static int mock_cec_init(int port)
+{
+	return EC_SUCCESS;
+}
+
+static const struct cec_drv mock_cec_drv = {
+	.init = &mock_cec_init,
+	.get_enable = &mock_cec_get_enable,
+	.set_enable = &mock_cec_set_enable,
+	.get_logical_addr = &mock_cec_get_logical_addr,
+	.set_logical_addr = &mock_cec_set_logical_addr,
+	.send = &mock_cec_send,
+	.get_received_message = &mock_cec_get_received_message,
+};
+
+const struct cec_config_t cec_config[] = {
+	[CEC_PORT_0] = {
+		.drv = &mock_cec_drv,
+		.offline_policy = NULL,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(cec_config) == CEC_PORT_COUNT);
diff --git a/board/host/charger.c b/board/host/charger.c
index 01f29571d0..7fa9b78dd1 100644
--- a/board/host/charger.c
+++ b/board/host/charger.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -7,20 +7,20 @@
 
 #include "battery_smart.h"
 #include "charger.h"
-#include "console.h"
 #include "common.h"
+#include "console.h"
 #include "util.h"
 
 static const struct charger_info mock_charger_info = {
-	.name         = "MockCharger",
-	.voltage_max  = 19200,
-	.voltage_min  = 1024,
+	.name = "MockCharger",
+	.voltage_max = 19200,
+	.voltage_min = 1024,
 	.voltage_step = 16,
-	.current_max  = 8192,
-	.current_min  = 128,
+	.current_max = 8192,
+	.current_min = 128,
 	.current_step = 128,
-	.input_current_max  = 8064,
-	.input_current_min  = 128,
+	.input_current_max = 8064,
+	.input_current_min = 128,
 	.input_current_step = 128,
 };
 
@@ -37,7 +37,6 @@ static const struct charger_info *mock_get_info(int chgnum)
 	return &mock_charger_info;
 }
 
-
 static enum ec_error_list mock_get_status(int chgnum, int *status)
 {
 	*status = CHARGER_LEVEL_2;
@@ -47,7 +46,6 @@ static enum ec_error_list mock_get_status(int chgnum, int *status)
 	return EC_SUCCESS;
 }
 
-
 static enum ec_error_list mock_set_mode(int chgnum, int mode)
 {
 	if (mode & CHARGE_FLAG_INHIBIT_CHARGE)
@@ -57,14 +55,12 @@ static enum ec_error_list mock_set_mode(int chgnum, int mode)
 	return EC_SUCCESS;
 }
 
-
 static enum ec_error_list mock_get_current(int chgnum, int *current)
 {
 	*current = mock_current;
 	return EC_SUCCESS;
 }
 
-
 static enum ec_error_list mock_set_current(int chgnum, int current)
 {
 	const struct charger_info *info = mock_get_info(chgnum);
@@ -86,7 +82,6 @@ static enum ec_error_list mock_get_voltage(int chgnum, int *voltage)
 	return EC_SUCCESS;
 }
 
-
 static enum ec_error_list mock_set_voltage(int chgnum, int voltage)
 {
 	mock_voltage = voltage;
@@ -94,41 +89,36 @@ static enum ec_error_list mock_set_voltage(int chgnum, int voltage)
 	return EC_SUCCESS;
 }
 
-
 static enum ec_error_list mock_get_option(int chgnum, int *option)
 {
 	*option = mock_option;
 	return EC_SUCCESS;
 }
 
-
 static enum ec_error_list mock_set_option(int chgnum, int option)
 {
 	mock_option = option;
 	return EC_SUCCESS;
 }
 
-
 static enum ec_error_list mock_manufacturer_id(int chgnum, int *id)
 {
 	return EC_SUCCESS;
 }
 
-
 static enum ec_error_list mock_device_id(int chgnum, int *id)
 {
 	return EC_SUCCESS;
 }
 
-
-static enum ec_error_list mock_get_input_current(int chgnum, int *input_current)
+static enum ec_error_list mock_get_input_current_limit(int chgnum,
+						       int *input_current)
 {
 	*input_current = mock_input_current;
 	return EC_SUCCESS;
 }
 
-
-static enum ec_error_list mock_set_input_current(int chgnum, int current)
+static enum ec_error_list mock_set_input_current_limit(int chgnum, int current)
 {
 	const struct charger_info *info = mock_get_info(chgnum);
 
@@ -144,10 +134,10 @@ static enum ec_error_list mock_set_input_current(int chgnum, int current)
 	return EC_SUCCESS;
 }
 
-
 static enum ec_error_list mock_post_init(int chgnum)
 {
-	mock_current = mock_input_current = CONFIG_CHARGER_INPUT_CURRENT;
+	mock_current = mock_input_current =
+		CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT;
 	return EC_SUCCESS;
 }
 
@@ -160,8 +150,8 @@ const struct charger_drv mock_drv = {
 	.set_current = &mock_set_current,
 	.get_voltage = &mock_get_voltage,
 	.set_voltage = &mock_set_voltage,
-	.set_input_current = &mock_set_input_current,
-	.get_input_current = &mock_get_input_current,
+	.set_input_current_limit = &mock_set_input_current_limit,
+	.get_input_current_limit = &mock_get_input_current_limit,
 	.manufacturer_id = &mock_manufacturer_id,
 	.device_id = &mock_device_id,
 	.get_option = &mock_get_option,
diff --git a/board/host/chipset.c b/board/host/chipset.c
index 3cb859eb29..ece97dc4fd 100644
--- a/board/host/chipset.c
+++ b/board/host/chipset.c
@@ -1,22 +1,26 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Chipset module for emulator */
 
-#include <stdio.h>
+/* Does not run a chipset task, but does emulate an AP chipset */
+#define CONFIG_AP_POWER_CONTROL
+
 #include "chipset.h"
 #include "common.h"
 #include "hooks.h"
 #include "task.h"
 #include "test_util.h"
 
+#include <stdio.h>
+
 static int chipset_state = CHIPSET_STATE_SOFT_OFF;
 static int power_on_req;
 static int power_off_req;
 
-test_mockable void chipset_reset(enum chipset_reset_reason reason)
+test_mockable void chipset_reset(enum chipset_shutdown_reason reason)
 {
 	fprintf(stderr, "Chipset reset: %d!\n", reason);
 }
diff --git a/board/host/ec.tasklist b/board/host/ec.tasklist
index c056c51e8a..0195800932 100644
--- a/board/host/ec.tasklist
+++ b/board/host/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/host/fan.c b/board/host/fan.c
index 1e1001f1cd..de335afa06 100644
--- a/board/host/fan.c
+++ b/board/host/fan.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,7 +22,10 @@ const struct fan_rpm fan_rpm_0 = {
 };
 
 const struct fan_t fans[CONFIG_FANS] = {
-	{ .conf = &fan_conf_0, .rpm = &fan_rpm_0, },
+	{
+		.conf = &fan_conf_0,
+		.rpm = &fan_rpm_0,
+	},
 };
 
 static int mock_enabled;
diff --git a/board/host/gpio.inc b/board/host/gpio.inc
index c567aa0277..e9855b686f 100644
--- a/board/host/gpio.inc
+++ b/board/host/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
+ * Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,6 +14,7 @@ GPIO_INT(AC_PRESENT,           PIN(0, 2), GPIO_INT_BOTH, extpower_interrupt)
 GPIO_INT(VOLUME_DOWN_L,        PIN(0, 3), GPIO_INT_BOTH, button_interrupt)
 GPIO_INT(VOLUME_UP_L,          PIN(0, 4), GPIO_INT_BOTH, button_interrupt)
 GPIO_INT(CHARGE_DONE,          PIN(0, 5), GPIO_INT_BOTH, inductive_charging_interrupt)
+GPIO_INT(TABLET_MODE_L,        PIN(0, 19), GPIO_INT_BOTH, gmr_tablet_switch_isr)
 /* Fingerprint */
 GPIO_INT(FPS_INT,              PIN(0, 14), GPIO_INT_RISING, fps_event)
 
@@ -34,3 +35,5 @@ GPIO(USB_C0_DISCHARGE,     PIN(0, 15), 0)
 
 GPIO(I2C_SCL,             PIN(0, 16),  GPIO_INPUT)
 GPIO(I2C_SDA,             PIN(0, 17),  GPIO_INPUT)
+
+GPIO(EC_CBI_WP,           PIN(0, 18), GPIO_OUT_LOW)
diff --git a/board/host/usb_pd_config.c b/board/host/usb_pd_config.c
index 91c30d1755..10ed9536fa 100644
--- a/board/host/usb_pd_config.c
+++ b/board/host/usb_pd_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -32,4 +32,3 @@ test_mockable int pd_adc_read(int port, int cc)
 	/* Not implemented */
 	return 0;
 }
-
diff --git a/board/host/usb_pd_config.h b/board/host/usb_pd_config.h
index fb12b2ce7d..0fff2af019 100644
--- a/board/host/usb_pd_config.h
+++ b/board/host/usb_pd_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/host/usb_pd_pdo.c b/board/host/usb_pd_pdo.c
new file mode 100644
index 0000000000..a352148ecb
--- /dev/null
+++ b/board/host/usb_pd_pdo.c
@@ -0,0 +1,23 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "compile_time_macros.h"
+#include "usb_pd.h"
+#include "usb_pd_pdo.h"
+
+#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP)
+
+const uint32_t pd_src_pdo[] = {
+	PDO_FIXED(5000, 900, PDO_FIXED_FLAGS),
+	PDO_FIXED(12000, 3000, PDO_FIXED_FLAGS),
+};
+const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
+
+const uint32_t pd_snk_pdo[] = {
+	PDO_FIXED(5000, 500, PDO_FIXED_FLAGS),
+	PDO_BATT(4750, 21000, 15000),
+	PDO_VAR(4750, 21000, 3000),
+};
+const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
diff --git a/board/host/usb_pd_pdo.h b/board/host/usb_pd_pdo.h
new file mode 100644
index 0000000000..4f1a64dced
--- /dev/null
+++ b/board/host/usb_pd_pdo.h
@@ -0,0 +1,17 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_BOARD_HOST_USB_PD_PDO_H
+#define __CROS_EC_BOARD_HOST_USB_PD_PDO_H
+
+#include "stdint.h"
+
+extern const uint32_t pd_src_pdo[2];
+extern const int pd_src_pdo_cnt;
+
+extern const uint32_t pd_snk_pdo[3];
+extern const int pd_snk_pdo_cnt;
+
+#endif /* __CROS_EC_BOARD_HOST_USB_PD_PDO_H */
diff --git a/board/host/usb_pd_policy.c b/board/host/usb_pd_policy.c
index 1ea28dcbe9..dc965ca192 100644
--- a/board/host/usb_pd_policy.c
+++ b/board/host/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,39 +6,25 @@
 #include "common.h"
 #include "console.h"
 #include "usb_pd.h"
+#include "usb_pd_pdo.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
-#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP)
-
-const uint32_t pd_src_pdo[] = {
-		PDO_FIXED(5000,   900, PDO_FIXED_FLAGS),
-		PDO_FIXED(12000,  3000, PDO_FIXED_FLAGS),
-};
-const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
-
-const uint32_t pd_snk_pdo[] = {
-		PDO_FIXED(5000, 500, PDO_FIXED_FLAGS),
-		PDO_BATT(4750, 21000, 15000),
-		PDO_VAR(4750, 21000, 3000),
-};
-const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
-
-int pd_set_power_supply_ready(int port)
+test_mockable int pd_set_power_supply_ready(int port)
 {
 	/* Not implemented */
 	return EC_SUCCESS;
 }
 
-void pd_power_supply_reset(int port)
+test_mockable void pd_power_supply_reset(int port)
 {
 	/* Not implemented */
 }
 
-void pd_set_input_current_limit(int port, uint32_t max_ma,
-				uint32_t supply_voltage)
+__overridable void pd_set_input_current_limit(int port, uint32_t max_ma,
+					      uint32_t supply_voltage)
 {
 	/* Not implemented */
 }
@@ -55,22 +41,18 @@ __override int pd_check_power_swap(int port)
 	return 1;
 }
 
-__override int pd_check_data_swap(int port,
-				  enum pd_data_role data_role)
+__override int pd_check_data_swap(int port, enum pd_data_role data_role)
 {
 	/* Always allow data swap */
 	return 1;
 }
 
-__override void pd_check_pr_role(int port,
-				 enum pd_power_role pr_role,
+__override void pd_check_pr_role(int port, enum pd_power_role pr_role,
 				 int flags)
 {
 }
 
-__override void pd_check_dr_role(int port,
-				 enum pd_data_role dr_role,
-				 int flags)
+__override void pd_check_dr_role(int port, enum pd_data_role dr_role, int flags)
 {
 }
 
diff --git a/board/host/vif_override.xml b/board/host/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/host/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/hyperdebug/board.c b/board/hyperdebug/board.c
new file mode 100644
index 0000000000..50d7855b1e
--- /dev/null
+++ b/board/hyperdebug/board.c
@@ -0,0 +1,287 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* HyperDebug board configuration */
+
+#include "adc.h"
+#include "common.h"
+#include "ec_version.h"
+#include "queue_policies.h"
+#include "registers.h"
+#include "spi.h"
+#include "stm32-dma.h"
+#include "timer.h"
+#include "usart-stm32l5.h"
+#include "usb-stream.h"
+#include "usb_spi.h"
+
+#include <stdio.h>
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+void board_config_pre_init(void)
+{
+	/* enable SYSCFG clock */
+	STM32_RCC_APB2ENR |= STM32_RCC_SYSCFGEN;
+}
+
+/******************************************************************************
+ * Forward UARTs as a USB serial interface.
+ */
+
+#define USB_STREAM_RX_SIZE 16
+#define USB_STREAM_TX_SIZE 16
+
+/******************************************************************************
+ * Forward USART2 as a simple USB serial interface.
+ */
+
+static struct usart_config const usart2;
+struct usb_stream_config const usart2_usb;
+
+static struct queue const usart2_to_usb =
+	QUEUE_DIRECT(64, uint8_t, usart2.producer, usart2_usb.consumer);
+static struct queue const usb_to_usart2 =
+	QUEUE_DIRECT(64, uint8_t, usart2_usb.producer, usart2.consumer);
+
+static struct usart_config const usart2 =
+	USART_CONFIG(usart2_hw, usart_rx_interrupt, usart_tx_interrupt, 115200,
+		     0, usart2_to_usb, usb_to_usart2);
+
+USB_STREAM_CONFIG(usart2_usb, USB_IFACE_USART2_STREAM,
+		  USB_STR_USART2_STREAM_NAME, USB_EP_USART2_STREAM,
+		  USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE, usb_to_usart2,
+		  usart2_to_usb)
+
+/******************************************************************************
+ * Forward USART3 as a simple USB serial interface.
+ */
+
+static struct usart_config const usart3;
+struct usb_stream_config const usart3_usb;
+
+static struct queue const usart3_to_usb =
+	QUEUE_DIRECT(64, uint8_t, usart3.producer, usart3_usb.consumer);
+static struct queue const usb_to_usart3 =
+	QUEUE_DIRECT(64, uint8_t, usart3_usb.producer, usart3.consumer);
+
+static struct usart_config const usart3 =
+	USART_CONFIG(usart3_hw, usart_rx_interrupt, usart_tx_interrupt, 115200,
+		     0, usart3_to_usb, usb_to_usart3);
+
+USB_STREAM_CONFIG(usart3_usb, USB_IFACE_USART3_STREAM,
+		  USB_STR_USART3_STREAM_NAME, USB_EP_USART3_STREAM,
+		  USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE, usb_to_usart3,
+		  usart3_to_usb)
+
+/******************************************************************************
+ * Forward USART4 as a simple USB serial interface.
+ */
+
+static struct usart_config const usart4;
+struct usb_stream_config const usart4_usb;
+
+static struct queue const usart4_to_usb =
+	QUEUE_DIRECT(64, uint8_t, usart4.producer, usart4_usb.consumer);
+static struct queue const usb_to_usart4 =
+	QUEUE_DIRECT(64, uint8_t, usart4_usb.producer, usart4.consumer);
+
+static struct usart_config const usart4 =
+	USART_CONFIG(usart4_hw, usart_rx_interrupt, usart_tx_interrupt, 115200,
+		     0, usart4_to_usb, usb_to_usart4);
+
+USB_STREAM_CONFIG(usart4_usb, USB_IFACE_USART4_STREAM,
+		  USB_STR_USART4_STREAM_NAME, USB_EP_USART4_STREAM,
+		  USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE, usb_to_usart4,
+		  usart4_to_usb)
+
+/******************************************************************************
+ * Forward USART5 as a simple USB serial interface.
+ */
+
+static struct usart_config const usart5;
+struct usb_stream_config const usart5_usb;
+
+static struct queue const usart5_to_usb =
+	QUEUE_DIRECT(64, uint8_t, usart5.producer, usart5_usb.consumer);
+static struct queue const usb_to_usart5 =
+	QUEUE_DIRECT(64, uint8_t, usart5_usb.producer, usart5.consumer);
+
+static struct usart_config const usart5 =
+	USART_CONFIG(usart5_hw, usart_rx_interrupt, usart_tx_interrupt, 115200,
+		     0, usart5_to_usb, usb_to_usart5);
+
+USB_STREAM_CONFIG(usart5_usb, USB_IFACE_USART5_STREAM,
+		  USB_STR_USART5_STREAM_NAME, USB_EP_USART5_STREAM,
+		  USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE, usb_to_usart5,
+		  usart5_to_usb)
+
+/******************************************************************************
+ * Define the strings used in our USB descriptors.
+ */
+
+const void *const usb_strings[] = {
+	[USB_STR_DESC] = usb_string_desc,
+	[USB_STR_VENDOR] = USB_STRING_DESC("Google LLC"),
+	[USB_STR_PRODUCT] = USB_STRING_DESC("HyperDebug"),
+	[USB_STR_SERIALNO] = 0,
+	[USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32),
+	[USB_STR_CONSOLE_NAME] = USB_STRING_DESC("HyperDebug Shell"),
+	[USB_STR_SPI_NAME] = USB_STRING_DESC("SPI"),
+	[USB_STR_I2C_NAME] = USB_STRING_DESC("I2C"),
+	[USB_STR_USART2_STREAM_NAME] = USB_STRING_DESC("UART2"),
+	[USB_STR_USART3_STREAM_NAME] = USB_STRING_DESC("UART3"),
+	[USB_STR_USART4_STREAM_NAME] = USB_STRING_DESC("UART4"),
+	[USB_STR_USART5_STREAM_NAME] = USB_STRING_DESC("UART5"),
+	[USB_STR_DFU_NAME] = USB_STRING_DESC("DFU"),
+};
+
+BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
+
+/******************************************************************************
+ * Set up USB PD
+ */
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	/*
+	 * All available ADC signals, converted to mV (3300mV/4096).  Every one
+	 * is declared with same name as the GPIO signal on the same pin, that
+	 * is how opentitantool identifies the signal.
+	 *
+	 * Technically, the Nucleo-L552ZE-Q board can run at either 1v8 or 3v3
+	 * supply, but we use HyperDebug only on 3v3 setting.  If in the future
+	 * we want to detect actual voltage, Vrefint could be used.  This would
+	 * also serve as calibration as the supply voltage may not be 3300mV
+	 * exactly.
+	 */
+	[ADC_CN9_11] = { "CN9_11", 3300, 4096, 0, STM32_AIN(1) },
+	[ADC_CN9_9] = { "CN9_9", 3300, 4096, 0, STM32_AIN(2) },
+	/*[ADC_CN10_9] = { "CN10_9", 3300, 4096, 0, STM32_AIN(3) },*/
+	[ADC_CN9_5] = { "CN9_5", 3300, 4096, 0, STM32_AIN(4) },
+	[ADC_CN10_29] = { "CN10_29", 3300, 4096, 0, STM32_AIN(5) },
+	[ADC_CN10_11] = { "CN10_11", 3300, 4096, 0, STM32_AIN(6) },
+	[ADC_CN9_3] = { "CN9_3", 3300, 4096, 0, STM32_AIN(7) },
+	[ADC_CN9_1] = { "CN9_1", 3300, 4096, 0, STM32_AIN(8) },
+	[ADC_CN7_9] = { "CN7_9", 3300, 4096, 0, STM32_AIN(9) },
+	[ADC_CN7_10] = { "CN7_10", 3300, 4096, 0, STM32_AIN(10) },
+	[ADC_CN7_12] = { "CN7_12", 3300, 4096, 0, STM32_AIN(11) },
+	[ADC_CN7_14] = { "CN7_14", 3300, 4096, 0, STM32_AIN(12) },
+	[ADC_CN9_7] = { "CN9_7", 3300, 4096, 0, STM32_AIN(15) },
+	[ADC_CN10_7] = { "CN10_7", 3300, 4096, 0, STM32_AIN(16) },
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/******************************************************************************
+ * Initialize board.
+ */
+
+static void board_init(void)
+{
+	timestamp_t deadline;
+
+	STM32_GPIO_BSRR(STM32_GPIOE_BASE) |= 0x0000FF00;
+
+	/* We know VDDIO2 is present, enable the GPIO circuit. */
+	STM32_PWR_CR2 |= STM32_PWR_CR2_IOSV;
+
+	/* USB to serial queues */
+	queue_init(&usart2_to_usb);
+	queue_init(&usb_to_usart2);
+	queue_init(&usart3_to_usb);
+	queue_init(&usb_to_usart3);
+	queue_init(&usart4_to_usb);
+	queue_init(&usb_to_usart4);
+	queue_init(&usart5_to_usb);
+	queue_init(&usb_to_usart5);
+
+	/* UART init */
+	usart_init(&usart2);
+	usart_init(&usart3);
+	usart_init(&usart4);
+	usart_init(&usart5);
+
+	/* Structured endpoints */
+	usb_spi_enable(1);
+
+	/* Configure SPI GPIOs */
+	gpio_config_module(MODULE_SPI, 1);
+
+	/* Enable ADC */
+	STM32_RCC_AHB2ENR |= STM32_RCC_AHB2ENR_ADCEN;
+	/* Initialize the ADC by performing a fake reading */
+	adc_read_channel(ADC_CN9_11);
+
+	/* Enable DAC */
+	STM32_RCC_APB1ENR |= STM32_RCC_APB1ENR1_DAC1EN;
+
+	/*
+	 * Enable SPI2.
+	 */
+
+	/* Enable clocks to SPI2 module */
+	STM32_RCC_APB1ENR1 |= STM32_RCC_APB1ENR1_SPI2EN;
+
+	/* Reset SPI2 */
+	STM32_RCC_APB1RSTR1 |= STM32_RCC_APB1RSTR1_SPI2RST;
+	STM32_RCC_APB1RSTR1 &= ~STM32_RCC_APB1RSTR1_SPI2RST;
+
+	spi_enable(&spi_devices[0], 1);
+
+	/*
+	 * Enable OCTOSPI, no driver for this in chip/stm32.
+	 */
+	deadline.val = get_time().val + OCTOSPI_INIT_TIMEOUT_US;
+
+	STM32_RCC_AHB3ENR |= STM32_RCC_AHB3ENR_QSPIEN;
+	while (STM32_OCTOSPI_SR & STM32_OCTOSPI_SR_BUSY) {
+		timestamp_t now = get_time();
+		if (timestamp_expired(deadline, &now)) {
+			/*
+			 * Ideally, the USB host would have a way of
+			 * discovering our failure to initialize OctoSPI.  But
+			 * for now, log and move on, this would happen only on
+			 * code bug or hardware failure.
+			 */
+			cprints(CC_SPI, "Initialization of OctoSPI failed");
+			break;
+		}
+	}
+
+	/*
+	 * Declare that a "Standard" SPI flash device, maximum size is connected
+	 * to OCTOSPI.  This allows the controller to send arbitrary 32-bit
+	 * addresses, which is needed as we use the instruction and address
+	 * bytes as arbitrary data to send via SPI.
+	 */
+	STM32_OCTOSPI_DCR1 = STM32_OCTOSPI_DCR1_MTYP_STANDARD |
+			     STM32_OCTOSPI_DCR1_DEVSIZE_MSK;
+	/* Clock prescaler (max value 255) */
+	STM32_OCTOSPI_DCR2 = spi_devices[1].div;
+
+	/* Select DMA channel */
+	dma_select_channel(STM32_DMAC_CH13, DMAMUX_REQ_OCTOSPI1);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+const char *board_read_serial(void)
+{
+	const uint32_t *stm32_unique_id =
+		(const uint32_t *)STM32_UNIQUE_ID_BASE;
+	static char serial[13];
+
+	// Compute 12 hex digits from three factory programmed 32-bit "Unique
+	// ID" words in a manner that has been observed to be consistent with
+	// how the STM DFU ROM bootloader presents its serial number.  This
+	// means that the serial number of any particular HyperDebug board will
+	// remain the same as it enters and leaves DFU mode for software
+	// upgrade.
+	int rc = snprintf(serial, sizeof(serial), "%08X%04X",
+			  stm32_unique_id[0] + stm32_unique_id[2],
+			  stm32_unique_id[1] >> 16);
+	if (12 != rc)
+		return NULL;
+	return serial;
+}
diff --git a/board/hyperdebug/board.h b/board/hyperdebug/board.h
new file mode 100644
index 0000000000..a0b533b758
--- /dev/null
+++ b/board/hyperdebug/board.h
@@ -0,0 +1,243 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* HyperDebug configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#define CONFIG_LTO
+
+/* Disable deferred (async) flash protect*/
+#undef CONFIG_FLASH_PROTECT_DEFERRED
+
+/* Configure the flash */
+#undef CONFIG_RO_SIZE
+#undef CONFIG_FW_PSTATE_OFF
+#undef CONFIG_FW_PSTATE_SIZE
+#undef CONFIG_RW_MEM_OFF
+#undef CONFIG_RW_SIZE
+
+#define CONFIG_RO_SIZE (4 * 1024)
+#define CONFIG_RW_MEM_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
+#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE_BYTES - CONFIG_RW_MEM_OFF)
+#undef CONFIG_IMAGE_PADDING
+
+#ifdef SECTION_IS_RO
+
+/* Configure the Boot Manager. */
+#define CONFIG_MALLOC
+#define CONFIG_DFU_BOOTMANAGER_MAIN
+#define CONFIG_DFU_BOOTMANAGER_SHARED
+#undef CONFIG_COMMON_RUNTIME
+#undef CONFIG_COMMON_PANIC_OUTPUT
+#undef CONFIG_COMMON_GPIO
+#undef CONFIG_COMMON_TIMER
+#undef CONFIG_WATCHDOG
+
+#else /* !SECTION_IS_RO */
+
+/*
+ * PLL configuration. Freq = STM32_HSE_CLOCK or HSI (16MHz) * N / M / R.
+ *
+ * In our case, 16MHz * 13 / 1 / 2 = 104MHz.
+ */
+
+#undef STM32_PLLM
+#undef STM32_PLLN
+#undef STM32_PLLR
+#define STM32_PLLM 1
+#define STM32_PLLN 13
+#define STM32_PLLR 2
+
+#define STM32_USE_PLL
+#define CPU_CLOCK 104000000
+
+#define CONFIG_ADC
+#define CONFIG_ADC_SAMPLE_TIME STM32_ADC_SMPR_247_5_CY
+#undef CONFIG_ADC_WATCHDOG
+#define CONFIG_BOARD_PRE_INIT
+
+#define CONFIG_ROM_BASE 0x0
+#define CONFIG_ROM_SIZE (CONFIG_RAM_BASE - CONFIG_ROM_BASE)
+
+/* DFU Firmware Update */
+#define CONFIG_DFU_RUNTIME
+#define CONFIG_DFU_BOOTMANAGER_SHARED
+
+/* Enable USB forwarding on UART 2, 3, 4, and 5. */
+#define CONFIG_STREAM_USART
+#undef CONFIG_STREAM_USART1
+#define CONFIG_STREAM_USART2
+#define CONFIG_STREAM_USART3
+#define CONFIG_STREAM_USART4
+#define CONFIG_STREAM_USART5
+#undef CONFIG_STREAM_USART9
+#define CONFIG_STREAM_USB
+#define CONFIG_CMD_USART_INFO
+
+/* The UART console is on LPUART (UART9), connected to st-link debugger. */
+#undef CONFIG_UART_CONSOLE
+#define CONFIG_UART_CONSOLE 9
+#undef CONFIG_UART_TX_DMA
+#undef CONFIG_UART_RX_DMA
+
+/* Optional features */
+#define CONFIG_HW_CRC
+#undef CONFIG_PVD
+
+/*
+ * See 'Programmable voltage detector characteristics' in the
+ * STM32F072x8 Datasheet.  PVD Threshold 1 corresponds to a falling
+ * voltage threshold of min:2.09V, max:2.27V.
+ */
+#define PVD_THRESHOLD (1)
+
+/* USB Configuration */
+
+#define CONFIG_USB
+#define CONFIG_USB_PID 0x520e
+#define CONFIG_USB_CONSOLE
+
+/*
+ * Enabling USB updating would exceed the number of USB endpoints
+ * supported by the hardware.  We will have to rely on the built-in
+ * DFU support of STM32 chips.
+ */
+#undef CONFIG_USB_UPDATE
+
+#undef CONFIG_USB_MAXPOWER_MA
+#define CONFIG_USB_MAXPOWER_MA 100
+
+#define CONFIG_USB_SERIALNO
+#define DEFAULT_SERIALNO "Uninitialized"
+
+/* USB interface indexes (use define rather than enum to expand them) */
+#define USB_IFACE_CONSOLE 0
+#define USB_IFACE_SPI 1
+#define USB_IFACE_I2C 2
+#define USB_IFACE_USART2_STREAM 3
+#define USB_IFACE_USART3_STREAM 4
+#define USB_IFACE_USART4_STREAM 5
+#define USB_IFACE_USART5_STREAM 6
+#define USB_IFACE_DFU 7
+#define USB_IFACE_COUNT 8
+
+/* USB endpoint indexes (use define rather than enum to expand them) */
+#define USB_EP_CONTROL 0
+#define USB_EP_CONSOLE 1
+#define USB_EP_SPI 2
+#define USB_EP_I2C 3
+#define USB_EP_USART2_STREAM 4
+#define USB_EP_USART3_STREAM 5
+#define USB_EP_USART4_STREAM 6
+#define USB_EP_USART5_STREAM 7
+#define USB_EP_COUNT 8
+
+/*
+ * Do not enable the common EC command gpioset for recasting of GPIO
+ * type. Instead, board specific commands are used for implementing
+ * the OpenTitan tool requirements.
+ */
+#undef CONFIG_CMD_GPIO_EXTENDED
+#define CONFIG_GPIO_GET_EXTENDED
+
+/* Enable control of SPI over USB */
+#define CONFIG_USB_SPI
+#define CONFIG_USB_SPI_BUFFER_SIZE 2048
+#define CONFIG_USB_SPI_FLASH_EXTENSIONS
+#define CONFIG_SPI_CONTROLLER
+#define CONFIG_STM32_SPI1_CONTROLLER
+#define CONFIG_SPI_MUTABLE_DEVICE_LIST
+
+/* Enable control of I2C over USB */
+#define CONFIG_USB_I2C
+#define CONFIG_I2C
+#define CONFIG_I2C_CONTROLLER
+
+/* See i2c_ite_flash_support.c for more information about these values */
+/*#define CONFIG_ITE_FLASH_SUPPORT */
+/*#define CONFIG_I2C_XFER_LARGE_TRANSFER */
+#undef CONFIG_USB_I2C_MAX_WRITE_COUNT
+#undef CONFIG_USB_I2C_MAX_READ_COUNT
+#define CONFIG_USB_I2C_MAX_WRITE_COUNT ((1 << 9) - 4)
+#define CONFIG_USB_I2C_MAX_READ_COUNT ((1 << 9) - 6)
+
+#endif /* SECTION_IS_RO */
+
+/* This is not actually an EC so disable some features. */
+#undef CONFIG_WATCHDOG_HELP
+#undef CONFIG_LID_SWITCH
+#undef CONFIG_FLASH_PSTATE
+
+/*
+ * Allow dangerous commands all the time, since we don't have a write protect
+ * switch.
+ */
+#define CONFIG_SYSTEM_UNLOCKED
+
+#ifndef __ASSEMBLER__
+
+/* Timer selection */
+#define TIM_CLOCK32 2
+
+#include "gpio_signal.h"
+
+/* USB string indexes */
+enum usb_strings {
+	USB_STR_DESC = 0,
+	USB_STR_VENDOR,
+	USB_STR_PRODUCT,
+	USB_STR_SERIALNO,
+	USB_STR_VERSION,
+	USB_STR_CONSOLE_NAME,
+	USB_STR_SPI_NAME,
+	USB_STR_I2C_NAME,
+	USB_STR_USART2_STREAM_NAME,
+	USB_STR_USART3_STREAM_NAME,
+	USB_STR_USART4_STREAM_NAME,
+	USB_STR_USART5_STREAM_NAME,
+	USB_STR_DFU_NAME,
+
+	USB_STR_COUNT
+};
+
+/* ADC signal */
+enum adc_channel {
+	ADC_CN9_11, /* ADC12_IN1 */
+	ADC_CN9_9, /* ADC12_IN2 */
+	/* ADC_CN10_9, */ /* ADC12_IN3, Nucleo USB VBUS sense */
+	ADC_CN9_5, /* ADC12_IN4 */
+	ADC_CN10_29, /* ADC12_IN5 */
+	ADC_CN10_11, /* ADC12_IN6 */
+	ADC_CN9_3, /* ADC12_IN7 */
+	ADC_CN9_1, /* ADC12_IN8 */
+	ADC_CN7_9, /* ADC12_IN9 */
+	ADC_CN7_10, /* ADC12_IN10 */
+	ADC_CN7_12, /* ADC12_IN11 */
+	ADC_CN7_14, /* ADC12_IN12 */
+	/* PC4, not on connectors */ /* ADC12_IN13 */
+	/* PC5, not on connectors */ /* ADC12_IN14 */
+	ADC_CN9_7, /* ADC12_IN15 */
+	ADC_CN10_7, /* ADC12_IN16 */
+	/* Number of ADC channels */
+	ADC_CH_COUNT
+};
+
+/* Timeout for initializing the OctoSPI controller. */
+#define OCTOSPI_INIT_TIMEOUT_US (100 * MSEC)
+
+/*
+ * Timeout for a complete SPI transaction.  Users can potentially set the clock
+ * down to 62.5 kHz and transfer up to 2048 bytes, which would take 262ms
+ * assuming no FIFO stalls.
+ */
+#define OCTOSPI_TRANSACTION_TIMEOUT_US (500 * MSEC)
+
+/* Interrupt handler, called by common/gpio.c. */
+void gpio_edge(enum gpio_signal signal);
+
+#endif /* !__ASSEMBLER__ */
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/hyperdebug/build.mk b/board/hyperdebug/build.mk
new file mode 100644
index 0000000000..2d8291043c
--- /dev/null
+++ b/board/hyperdebug/build.mk
@@ -0,0 +1,16 @@
+# -*- makefile -*-
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+
+# the IC is STmicro STM32F302R8
+CHIP:=stm32
+CHIP_FAMILY:=stm32l5
+CHIP_VARIANT:=stm32l552xe
+
+# These files are compiled into RO
+chip-ro=bkpdata.o system.o
+
+board-rw=board.o gpio.o spi.o i2c.o
diff --git a/board/hyperdebug/ec.tasklist b/board/hyperdebug/ec.tasklist
new file mode 100644
index 0000000000..731007e9fe
--- /dev/null
+++ b/board/hyperdebug/ec.tasklist
@@ -0,0 +1,11 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS_RW(HOOKS,   hook_task,    NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS_RW(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE)
diff --git a/board/hyperdebug/gpio.c b/board/hyperdebug/gpio.c
new file mode 100644
index 0000000000..dbffa7fefb
--- /dev/null
+++ b/board/hyperdebug/gpio.c
@@ -0,0 +1,972 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* HyperDebug GPIO logic and console commands */
+
+#include "atomic.h"
+#include "builtin/assert.h"
+#include "common.h"
+#include "console.h"
+#include "cpu.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "registers.h"
+#include "task.h"
+#include "timer.h"
+#include "util.h"
+
+struct dac_t {
+	uint32_t enable_mask;
+	volatile uint32_t *data_register;
+};
+
+/* Sparse array of DAC capabilities for GPIO pins. */
+const struct dac_t dac_channels[GPIO_COUNT] = {
+	[GPIO_CN7_9] = { STM32_DAC_CR_EN1, &STM32_DAC_DHR12R1 },
+	[GPIO_CN7_10] = { STM32_DAC_CR_EN2, &STM32_DAC_DHR12R2 },
+};
+
+/*
+ * GPIO structure for keeping extra flags such as GPIO_OPEN_DRAIN, to be applied
+ * whenever the pin is switched into "alternate" mode.
+ */
+struct gpio_alt_flags {
+	/* Port base address */
+	uint32_t port;
+
+	/* Bitmask on that port (multiple bits allowed) */
+	uint32_t mask;
+
+	/* Flags (GPIO_*; see above). */
+	uint32_t flags;
+};
+
+/*
+ * Construct the gpio_alt_flags array, this really is just a subset of the
+ * columns in the gpio_alt_funcs array in common/gpio.c (which is not accessible
+ * from here).  This array is used by extra_alternate_flags().
+ */
+#define ALTERNATE(pinmask, function, module, flagz) \
+	{ GPIO_##pinmask, .flags = (flagz) },
+
+static __const_data const struct gpio_alt_flags gpio_alt_flags[] = {
+#include "gpio.wrap"
+};
+#undef ALTERNATE
+
+/*
+ * A cyclic buffer is used to record events (edges) of one or more GPIO
+ * signals.  Each event records the time since the previous event, and the
+ * signal that changed (the direction of change is not explicitly recorded).
+ *
+ * So conceptually the buffer entries are pairs of (diff: u64, signal_no: u8).
+ * These entries are encoded as bytes in the following way: First the timestamp
+ * diff is shifted left by signal_bits, and the signal_no value put into the
+ * lower bits freed up this way.  Now we have a single u64, which often will be
+ * a small value (or at least, when the edges happen rapidly, and the need to
+ * store many of them the highest, then the u64 will be a small value).  This
+ * u64 is then stored 7 bits at a time in successive bytes, with the most
+ * significant bit indicating whether more bytes belong to the same entry.
+ *
+ * The chain of relative timestamps are resolved by keeping two absolute
+ * timestamps: head_time is the time of the most recently inserted event, and is
+ * accessed and updated only by the interrupt handler.  tail_time is the past
+ * timestamp on which the diff of the oldest record in the buffer is based (the
+ * timestamp of the last record to be removed from the buffer), it is accessed
+ * and updated only from the non-interrupt code that removes records from the
+ * buffer.
+ *
+ * In a similar fashion, the signal level is recorded "at both ends" in for each
+ * monitored signal by head_level and tail_level, the former only accessed from
+ * the interrupt handler, and the latter only accessed from non-interrupt code.
+ */
+struct cyclic_buffer_header_t {
+	/* Number of signals being monitored in this buffer. */
+	uint8_t num_signals;
+	/* The number of bits required to represent 0..num_signals-1. */
+	uint8_t signal_bits;
+	/* Sticky bit recording if overflow occurred. */
+	volatile uint8_t overflow;
+	/* Time of the most recent event, updated from interrupt context. */
+	volatile timestamp_t head_time;
+	/* Time base that the oldest event is relative to. */
+	timestamp_t tail_time;
+	/* Index at which new records are placed, updated from interrupt. */
+	volatile uint32_t head;
+	/* Index af oldest record. */
+	uint32_t tail;
+	/*
+	 * Size of cyclic byte buffer, determined at runtime, not necessarily
+	 * power of two.  Head and tail wrap to zero here.
+	 */
+	uint32_t size;
+	/* Data contents */
+	uint8_t data[];
+};
+
+/*
+ * The STM32L5 has 16 edge detection circuits.  Each pin can only be used with
+ * one of them.  That is, detector 0 can take its input from one of pins A0,
+ * B0, C0, ..., while detector 1 can choose between A1, B1, etc.
+ *
+ * Information about the current use of each detection circuit is stored in 16
+ * "slots" below.
+ */
+struct monitoring_slot_t {
+	/* Link to buffer recording edges of this signal. */
+	struct cyclic_buffer_header_t *buffer;
+	/* EC enum id of the signal used by this detection slot. */
+	int gpio_signal;
+	/* The index of the signal as used in the recording buffer. */
+	uint8_t signal_no;
+	/* Most recently recorded level of the signal. */
+	volatile uint8_t head_level;
+	/* Level as of the current oldest end (tail) of the recording. */
+	uint8_t tail_level;
+};
+struct monitoring_slot_t monitoring_slots[16];
+
+/*
+ * Memory area used for allocation of cyclic buffers.  (Currently the
+ * implementation supports only a single allocation.)
+ */
+uint8_t buffer_area[sizeof(struct cyclic_buffer_header_t) + 8192];
+bool buffer_area_in_use = false;
+
+static struct cyclic_buffer_header_t *allocate_cyclic_buffer(size_t size)
+{
+	struct cyclic_buffer_header_t *res =
+		(struct cyclic_buffer_header_t *)buffer_area;
+	if (buffer_area_in_use) {
+		/* No support for multiple smaller allocations, yet. */
+		return 0;
+	}
+	if (sizeof(struct cyclic_buffer_header_t) + size >
+	    sizeof(buffer_area)) {
+		/* Requested size exceeds the capacity of the area. */
+		return 0;
+	}
+	buffer_area_in_use = true;
+	res->size = size;
+	return res;
+}
+
+static void free_cyclic_buffer(struct cyclic_buffer_header_t *buf)
+{
+	buffer_area_in_use = false;
+}
+
+/*
+ * Counts unacknowledged buffer overflows.  Whenever non-zero, the red LED
+ * will flash.
+ */
+atomic_t num_cur_error_conditions;
+
+/*
+ * Counts the number of cyclic buffers currently in existence, the green LED
+ * will flash whenever this is non-zero, indicating the monitoring activity.
+ */
+int num_cur_monitoring = 0;
+
+static __attribute__((noinline)) void overflow(struct monitoring_slot_t *slot)
+{
+	struct cyclic_buffer_header_t *buffer_header = slot->buffer;
+	gpio_disable_interrupt(slot->gpio_signal);
+	buffer_header->overflow = 1;
+	atomic_add(&num_cur_error_conditions, 1);
+}
+
+void gpio_edge(enum gpio_signal signal)
+{
+	/*
+	 * Hardware has detected one or more edges since last time.  We
+	 * process by looking at the current level of the signal.  If opposite
+	 * the most recent level, we record one edge, if the same as most
+	 * recent level, we record two edges, that is, a zero-width pulse.
+	 * This is useful for tests trying to verify e.g. that there are no
+	 * glitches on a particular signal, and want to know about any pulses,
+	 * however narrow.
+	 */
+	timestamp_t now = get_time();
+	int gpio_num = GPIO_MASK_TO_NUM(gpio_list[signal].mask);
+	struct monitoring_slot_t *slot = monitoring_slots + gpio_num;
+	int current_level = gpio_get_level(signal);
+	struct cyclic_buffer_header_t *buffer_header = slot->buffer;
+	uint8_t *buffer_data = buffer_header->data;
+	uint32_t tail = buffer_header->tail, head = buffer_header->head,
+		 size = buffer_header->size;
+	uint64_t diff = now.val - buffer_header->head_time.val;
+
+	uint8_t signal_bits = buffer_header->signal_bits;
+
+	/*
+	 * Race condition here!  If three or more edges happen in
+	 * rapid succession, we may fail to record some of them, but
+	 * we should never over-report edges.
+	 *
+	 * Since the edge interrupts pending bit has been cleared before the
+	 * "current_level" was polled, if an edge happened between the two, then
+	 * an interrupt is currently pending, and when handled after this method
+	 * returns, the logic below would wrongly conclude that the signal must
+	 * have seen two transitions, in order to end up at the same level as
+	 * before.  In order to avoid such over-reporting, we clear "pending"
+	 * interrupt bit below, but only for the direction that goes "towards"
+	 * the level measured above.
+	 */
+	if (current_level)
+		STM32_EXTI_RPR = BIT(gpio_num);
+	else
+		STM32_EXTI_FPR = BIT(gpio_num);
+
+	/*
+	 * Insert an entry recording the time since last event, and which
+	 * signal changed (the direction of the edge is not explicitly
+	 * recorded, as it can be inferred from the initial level).
+	 *
+	 * The time difference and pin index are encoded in `diff`, which will
+	 * be a small integer if the event arrive rapidly.  7 bits of this
+	 * integer is then put into one byte at a time, using the high bit of
+	 * each byte to indicate if more are to come.  This encoding will use
+	 * only one byte per event, in the best case, allowing tens of
+	 * thousands of events to be buffered.
+	 */
+	diff <<= signal_bits;
+	diff |= slot->signal_no;
+	do {
+		buffer_data[head++] = ((diff >= 0x80) ? 0x80 : 0x00) |
+				      (diff & 0x7F);
+		diff >>= 7;
+		if (head == size)
+			head = 0;
+		if (head == tail) {
+			/*
+			 * The new head will not be persisted, maintaining the
+			 * invatiant that head and tail are equal only when the
+			 * buffer is empty.
+			 */
+			return overflow(slot);
+		}
+	} while (diff);
+
+	/*
+	 * If current level equals the previous level, then record an
+	 * additional edge 0ms after the previous.
+	 */
+	if (!!current_level == !!slot->head_level) {
+		/*
+		 * Add a record with zero diff, and the same signal no.  (Will
+		 * always fit in one byte, as signal_no never uses more than 7
+		 * bits.)
+		 */
+		buffer_data[head++] = slot->signal_no;
+		if (head == size)
+			head = 0;
+		if (head == tail) {
+			/*
+			 * The new head will not be persisted, maintaining the
+			 * invatiant that head and tail are equal only when the
+			 * buffer is empty.
+			 */
+			return overflow(slot);
+		}
+	} else {
+		slot->head_level = current_level;
+	}
+	buffer_header->head = head;
+	buffer_header->head_time = now;
+}
+
+static void board_gpio_init(void)
+{
+	/* Mark every slot as unused. */
+	for (int i = 0; i < ARRAY_SIZE(monitoring_slots); i++)
+		monitoring_slots[i].gpio_signal = GPIO_COUNT;
+}
+DECLARE_HOOK(HOOK_INIT, board_gpio_init, HOOK_PRIO_DEFAULT);
+
+static void stop_all_gpio_monitoring(void)
+{
+	struct monitoring_slot_t *slot;
+	struct cyclic_buffer_header_t *buffer_header;
+	for (int i = 0; i < ARRAY_SIZE(monitoring_slots); i++) {
+		slot = monitoring_slots + i;
+		if (!slot->buffer)
+			continue;
+
+		/* Disable interrupts for all signals feeding into the same
+		 * cyclic buffer. */
+		buffer_header = slot->buffer;
+		for (int j = i; j < ARRAY_SIZE(monitoring_slots); j++) {
+			slot = monitoring_slots + i;
+			if (slot->buffer != buffer_header)
+				continue;
+			gpio_disable_interrupt(slot->gpio_signal);
+			slot->gpio_signal = GPIO_COUNT;
+		}
+		/* Deallocate this one cyclic buffer. */
+		num_cur_monitoring--;
+		if (buffer_header->overflow)
+			atomic_sub(&num_cur_error_conditions, 1);
+		free_cyclic_buffer(buffer_header);
+	}
+}
+
+/*
+ * Return GPIO_OPEN_DRAIN or any other special flags to apply when the given
+ * signal is in "alternate" mode.
+ */
+static uint32_t extra_alternate_flags(enum gpio_signal signal)
+{
+	const struct gpio_info *g = gpio_list + signal;
+	const struct gpio_alt_flags *af;
+
+	/* Find the first ALTERNATE() declaration for the given pin. */
+	for (af = gpio_alt_flags;
+	     af < gpio_alt_flags + ARRAY_SIZE(gpio_alt_flags); af++) {
+		if (af->port != g->port)
+			continue;
+
+		if (af->mask & g->mask) {
+			return af->flags;
+		}
+	}
+
+	/* No ALTERNATE() declaration mention the given pin. */
+	return 0;
+}
+
+/**
+ * Find a GPIO signal by name.
+ *
+ * This is copied from gpio.c unfortunately, as it is static over there.
+ *
+ * @param name		Signal name to find
+ *
+ * @return the signal index, or GPIO_COUNT if no match.
+ */
+static enum gpio_signal find_signal_by_name(const char *name)
+{
+	int i;
+
+	if (!name || !*name)
+		return GPIO_COUNT;
+
+	for (i = 0; i < GPIO_COUNT; i++)
+		if (gpio_is_implemented(i) &&
+		    !strcasecmp(name, gpio_get_name(i)))
+			return i;
+
+	return GPIO_COUNT;
+}
+
+/*
+ * Set the mode of a GPIO pin: input/opendrain/pushpull/alternate.
+ */
+static int command_gpio_mode(int argc, const char **argv)
+{
+	int gpio;
+	int flags;
+	uint32_t dac_enable_value = STM32_DAC_CR;
+
+	if (argc < 3)
+		return EC_ERROR_PARAM_COUNT;
+
+	gpio = find_signal_by_name(argv[1]);
+	if (gpio == GPIO_COUNT)
+		return EC_ERROR_PARAM1;
+	flags = gpio_get_flags(gpio);
+
+	flags &= ~(GPIO_INPUT | GPIO_OUTPUT | GPIO_OPEN_DRAIN | GPIO_ANALOG);
+	dac_enable_value &= ~dac_channels[gpio].enable_mask;
+	if (strcasecmp(argv[2], "input") == 0)
+		flags |= GPIO_INPUT;
+	else if (strcasecmp(argv[2], "opendrain") == 0)
+		flags |= GPIO_OUTPUT | GPIO_OPEN_DRAIN;
+	else if (strcasecmp(argv[2], "pushpull") == 0)
+		flags |= GPIO_OUTPUT;
+	else if (strcasecmp(argv[2], "adc") == 0)
+		flags |= GPIO_ANALOG;
+	else if (strcasecmp(argv[2], "dac") == 0) {
+		if (dac_channels[gpio].enable_mask == 0) {
+			ccprintf("Error: Pin does not support dac\n");
+			return EC_ERROR_PARAM2;
+		}
+		dac_enable_value |= dac_channels[gpio].enable_mask;
+		/* Disable digital output, when DAC is overriding. */
+		flags |= GPIO_INPUT;
+	} else if (strcasecmp(argv[2], "alternate") == 0)
+		flags |= GPIO_ALTERNATE | extra_alternate_flags(gpio);
+	else
+		return EC_ERROR_PARAM2;
+
+	/* Update GPIO flags. */
+	gpio_set_flags(gpio, flags);
+	STM32_DAC_CR = dac_enable_value;
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND_FLAGS(
+	gpiomode, command_gpio_mode,
+	"name <input | opendrain | pushpull | adc | dac | alternate>",
+	"Set a GPIO mode", CMD_FLAG_RESTRICTED);
+
+/*
+ * Set the weak pulling of a GPIO pin: up/down/none.
+ */
+static int command_gpio_pull_mode(int argc, const char **argv)
+{
+	int gpio;
+	int flags;
+
+	if (argc < 3)
+		return EC_ERROR_PARAM_COUNT;
+
+	gpio = find_signal_by_name(argv[1]);
+	if (gpio == GPIO_COUNT)
+		return EC_ERROR_PARAM1;
+	flags = gpio_get_flags(gpio);
+
+	flags = flags & ~(GPIO_PULL_UP | GPIO_PULL_DOWN);
+	if (strcasecmp(argv[2], "none") == 0)
+		;
+	else if (strcasecmp(argv[2], "up") == 0)
+		flags |= GPIO_PULL_UP;
+	else if (strcasecmp(argv[2], "down") == 0)
+		flags |= GPIO_PULL_DOWN;
+	else
+		return EC_ERROR_PARAM2;
+
+	/* Update GPIO flags. */
+	gpio_set_flags(gpio, flags);
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND_FLAGS(gpiopullmode, command_gpio_pull_mode,
+			      "name <none | up | down>",
+			      "Set a GPIO weak pull mode", CMD_FLAG_RESTRICTED);
+
+static int set_dac(int gpio, const char *value)
+{
+	int milli_volts;
+	char *e;
+	if (dac_channels[gpio].enable_mask == 0) {
+		ccprintf("Error: Pin does not support dac\n");
+		return EC_ERROR_PARAM6;
+	}
+
+	milli_volts = strtoi(value, &e, 0);
+	if (*e)
+		return EC_ERROR_PARAM6;
+
+	if (milli_volts <= 0)
+		*dac_channels[gpio].data_register = 0;
+	else if (milli_volts >= 3300)
+		*dac_channels[gpio].data_register = 4095;
+	else
+		*dac_channels[gpio].data_register = milli_volts * 4096 / 3300;
+
+	return EC_SUCCESS;
+}
+
+/*
+ * Set the value in millivolts for driving the DAC of a given pin.
+ */
+static int command_gpio_analog_set(int argc, const char **argv)
+{
+	int gpio;
+
+	if (argc < 4)
+		return EC_ERROR_PARAM_COUNT;
+
+	gpio = find_signal_by_name(argv[2]);
+	if (gpio == GPIO_COUNT)
+		return EC_ERROR_PARAM2;
+
+	if (set_dac(gpio, argv[3]) != EC_SUCCESS)
+		return EC_ERROR_PARAM3;
+	return EC_SUCCESS;
+}
+
+/*
+ * Set multiple aspects of a GPIO pin simultaneously, that is, can switch output
+ * level, opendrain/pushpull, and pullup simultaneously, eliminating the risk of
+ * glitches.
+ */
+static int command_gpio_multiset(int argc, const char **argv)
+{
+	int gpio;
+	int flags;
+	uint32_t dac_enable_value = STM32_DAC_CR;
+
+	if (argc < 4)
+		return EC_ERROR_PARAM_COUNT;
+
+	gpio = find_signal_by_name(argv[2]);
+	if (gpio == GPIO_COUNT)
+		return EC_ERROR_PARAM2;
+	flags = gpio_get_flags(gpio);
+
+	if (argc > 3 && strcasecmp(argv[3], "-") != 0) {
+		flags = flags & ~(GPIO_LOW | GPIO_HIGH);
+		if (strcasecmp(argv[3], "0") == 0)
+			flags |= GPIO_LOW;
+		else if (strcasecmp(argv[3], "1") == 0)
+			flags |= GPIO_HIGH;
+		else
+			return EC_ERROR_PARAM3;
+	}
+
+	if (argc > 4 && strcasecmp(argv[4], "-") != 0) {
+		flags &= ~(GPIO_INPUT | GPIO_OUTPUT | GPIO_OPEN_DRAIN |
+			   GPIO_ANALOG);
+		dac_enable_value &= ~dac_channels[gpio].enable_mask;
+		if (strcasecmp(argv[4], "input") == 0)
+			flags |= GPIO_INPUT;
+		else if (strcasecmp(argv[4], "opendrain") == 0)
+			flags |= GPIO_OUTPUT | GPIO_OPEN_DRAIN;
+		else if (strcasecmp(argv[4], "pushpull") == 0)
+			flags |= GPIO_OUTPUT;
+		else if (strcasecmp(argv[4], "adc") == 0)
+			flags |= GPIO_ANALOG;
+		else if (strcasecmp(argv[4], "dac") == 0) {
+			if (dac_channels[gpio].enable_mask == 0) {
+				ccprintf("Error: Pin does not support dac\n");
+				return EC_ERROR_PARAM2;
+			}
+			dac_enable_value |= dac_channels[gpio].enable_mask;
+			/* Disable digital output, when DAC is overriding. */
+			flags |= GPIO_INPUT;
+		} else if (strcasecmp(argv[4], "alternate") == 0)
+			flags |= GPIO_ALTERNATE | extra_alternate_flags(gpio);
+		else
+			return EC_ERROR_PARAM4;
+	}
+
+	if (argc > 5 && strcasecmp(argv[5], "-") != 0) {
+		flags = flags & ~(GPIO_PULL_UP | GPIO_PULL_DOWN);
+		if (strcasecmp(argv[5], "none") == 0)
+			;
+		else if (strcasecmp(argv[5], "up") == 0)
+			flags |= GPIO_PULL_UP;
+		else if (strcasecmp(argv[5], "down") == 0)
+			flags |= GPIO_PULL_DOWN;
+		else
+			return EC_ERROR_PARAM5;
+	}
+
+	if (argc > 6 && strcasecmp(argv[6], "-") != 0) {
+		if (set_dac(gpio, argv[6]) != EC_SUCCESS)
+			return EC_ERROR_PARAM6;
+	}
+
+	/* Update GPIO flags. */
+	gpio_set_flags(gpio, flags);
+	STM32_DAC_CR = dac_enable_value;
+	return EC_SUCCESS;
+}
+
+static int command_gpio_monitoring_start(int argc, const char **argv)
+{
+	BUILD_ASSERT(STM32_IRQ_EXTI15 < 32);
+	int gpios[16];
+	int gpio_num = argc - 3;
+	int i;
+	timestamp_t now;
+	int rv;
+	uint32_t nvic_mask;
+	size_t cyclic_buffer_size = 8192; /* Maybe configurable by parameter */
+	struct cyclic_buffer_header_t *buf;
+	struct monitoring_slot_t *slot;
+
+	if (gpio_num <= 0 || gpio_num > 16)
+		return EC_ERROR_PARAM_COUNT;
+
+	for (i = 0; i < gpio_num; i++) {
+		gpios[i] = find_signal_by_name(argv[3 + i]);
+		if (gpios[i] == GPIO_COUNT) {
+			rv = EC_ERROR_PARAM3 + i;
+			goto out_partial_cleanup;
+		}
+		slot = monitoring_slots +
+		       GPIO_MASK_TO_NUM(gpio_list[gpios[i]].mask);
+		if (slot->gpio_signal != GPIO_COUNT) {
+			ccprintf("Error: Monitoring of %s conflicts with %s\n",
+				 argv[3 + i],
+				 gpio_list[slot->gpio_signal].name);
+			rv = EC_ERROR_PARAM3 + i;
+			goto out_partial_cleanup;
+		}
+		slot->gpio_signal = gpios[i];
+	}
+
+	/*
+	 * All the requested signals were available for monitoring, and their
+	 * slots have been marked as reserved for the respective signal.
+	 */
+	buf = allocate_cyclic_buffer(cyclic_buffer_size);
+	if (!buf) {
+		rv = EC_ERROR_BUSY;
+		goto out_cleanup;
+	}
+
+	buf->head = buf->tail = 0;
+	buf->overflow = 0;
+	buf->num_signals = gpio_num;
+	buf->signal_bits = 0;
+	/* Compute how many bits are required to represent 0..gpio_num-1. */
+	while ((gpio_num - 1) >> buf->signal_bits)
+		buf->signal_bits++;
+
+	for (i = 0; i < gpio_num; i++) {
+		slot = monitoring_slots +
+		       GPIO_MASK_TO_NUM(gpio_list[gpios[i]].mask);
+		slot->buffer = buf;
+		slot->signal_no = i;
+	}
+
+	/*
+	 * The code relies on all EXTIn interrupts belonging to the same 32-bit
+	 * NVIC register, so that multiple interrupts can be "unleashed"
+	 * simultaneously.
+	 */
+	nvic_mask = 0;
+
+	/*
+	 * Disable interrupts in GPIO/EXTI detection circuits (should be
+	 * disabled already, but disabled and clear pending bit to be on the
+	 * safe side).
+	 */
+	for (i = 0; i < gpio_num; i++) {
+		int gpio_num = GPIO_MASK_TO_NUM(gpio_list[gpios[i]].mask);
+		gpio_disable_interrupt(gpios[i]);
+		gpio_clear_pending_interrupt(gpios[i]);
+		nvic_mask |= BIT(STM32_IRQ_EXTI0 + gpio_num);
+	}
+	/* Also disable interrupts at NVIC (interrupt controller) level. */
+	CPU_NVIC_UNPEND(0) = nvic_mask;
+	CPU_NVIC_DIS(0) = nvic_mask;
+
+	for (i = 0; i < gpio_num; i++) {
+		int gpio_num = GPIO_MASK_TO_NUM(gpio_list[gpios[i]].mask);
+		slot = monitoring_slots + gpio_num;
+		/*
+		 * Tell the GPIO block to start detecting rising and falling
+		 * edges, and latch them in STM32_EXTI_RPR and STM32_EXTI_FPR
+		 * respectively.  Interrupts are still disabled in the NVIC,
+		 * meaning that the execution will not be interrupted, yet, even
+		 * if the GPIO block requests interrupt.
+		 */
+		gpio_enable_interrupt(gpios[i]);
+		slot->tail_level = slot->head_level = gpio_get_level(gpios[i]);
+		/*
+		 * Race condition here!  If three or more edges happen in
+		 * rapid succession, we may fail to record some of them, but
+		 * we should never over-report edges.
+		 *
+		 * Since edge detection was enabled before the "head_level"
+		 * was polled, if an edge happened between the two, then an
+		 * interrupt is currently pending, and when handled after this
+		 * loop, the logic in the gpio_edge interrupt handler would
+		 * wrongly conclude that the signal must have seen two
+		 * transitions, in order to end up at the same level as before.
+		 * In order to avoid such over-reporting, we clear "pending"
+		 * interrupt bit below, but only for the direction that goes
+		 * "towards" the level measured above.
+		 */
+		if (slot->head_level)
+			STM32_EXTI_RPR = BIT(gpio_num);
+		else
+			STM32_EXTI_FPR = BIT(gpio_num);
+	}
+	/*
+	 * Now enable the handling of the set of interrupts.
+	 */
+	now = get_time();
+	buf->head_time = now;
+	CPU_NVIC_EN(0) = nvic_mask;
+
+	buf->tail_time = now;
+	num_cur_monitoring++;
+	ccprintf("  @%lld\n", buf->tail_time.val);
+
+	/*
+	 * Dump the initial level of each input, for the convenience of the
+	 * caller.  (Allow makes monitoring useful, even if a signal has no
+	 * transitions during the monitoring period.
+	 */
+	for (i = 0; i < gpio_num; i++) {
+		slot = monitoring_slots +
+		       GPIO_MASK_TO_NUM(gpio_list[gpios[i]].mask);
+		ccprintf("  %d %s %d\n", i, gpio_list[gpios[i]].name,
+			 slot->tail_level);
+	}
+
+	return EC_SUCCESS;
+
+out_cleanup:
+	i = gpio_num;
+out_partial_cleanup:
+	while (i-- > 0) {
+		monitoring_slots[GPIO_MASK_TO_NUM(gpio_list[gpios[i]].mask)]
+			.gpio_signal = GPIO_COUNT;
+	}
+	return rv;
+}
+
+static int command_gpio_monitoring_read(int argc, const char **argv)
+{
+	int gpios[16];
+	int gpio_num = argc - 3;
+	int i;
+	struct cyclic_buffer_header_t *buf = NULL;
+	struct monitoring_slot_t *slot;
+	int gpio_signals_by_no[16];
+	uint8_t signal_bits;
+	uint32_t tail, head;
+	timestamp_t tail_time, now;
+
+	if (gpio_num <= 0 || gpio_num > 16)
+		return EC_ERROR_PARAM_COUNT;
+
+	for (i = 0; i < gpio_num; i++) {
+		gpios[i] = find_signal_by_name(argv[3 + i]);
+		if (gpios[i] == GPIO_COUNT)
+			return EC_ERROR_PARAM3 + i; /* May overflow */
+		slot = monitoring_slots +
+		       GPIO_MASK_TO_NUM(gpio_list[gpios[i]].mask);
+		if (slot->gpio_signal != gpios[i]) {
+			ccprintf("Error: Not monitoring %s\n",
+				 gpio_list[gpios[i]].name);
+			return EC_ERROR_PARAM3 + i;
+		}
+		if (slot->signal_no != i) {
+			ccprintf("Error: Inconsistent order at %s\n",
+				 gpio_list[gpios[i]].name);
+			return EC_ERROR_PARAM3 + i;
+		}
+		if (buf == NULL) {
+			buf = slot->buffer;
+		} else if (buf != slot->buffer) {
+			ccprintf(
+				"Error: Not monitoring %s as part of same groups as %s\n",
+				gpio_list[gpios[i]].name,
+				gpio_list[gpios[0]].name);
+			return EC_ERROR_PARAM3 + i;
+		}
+		gpio_signals_by_no[slot->signal_no] = gpios[i];
+	}
+	if (gpio_num != buf->num_signals) {
+		ccprintf("Error: Not full set of signals monitored\n");
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * We read current time, before taking a snapshot of the head pointer as
+	 * set by the interrupt handler.  This way, we can guarantee that the
+	 * transcript will include any edge happening at or before the `now`
+	 * timestamp.  If an interrupt happens between the two lines below,
+	 * causing our head pointer to include an event that happened after
+	 * "now", then it will be skipped in the loop below, and kept for the
+	 * next invocation of `gpio monitoring read`.
+	 */
+	now = get_time();
+	head = buf->head;
+
+	ccprintf("  @%lld\n", now.val);
+	signal_bits = buf->signal_bits;
+	tail = buf->tail;
+	tail_time = buf->tail_time;
+	while (tail != head) {
+		uint8_t *buffer = buf->data;
+		timestamp_t diff;
+		uint8_t byte;
+		uint8_t signal_no;
+		int shift = 0;
+		uint32_t tentative_tail = tail;
+		struct monitoring_slot_t *slot;
+		diff.val = 0;
+		do {
+			byte = buffer[tentative_tail++];
+			if (tentative_tail == buf->size)
+				tentative_tail = 0;
+			diff.val |= (byte & 0x7F) << shift;
+			shift += 7;
+		} while (byte & 0x80);
+		signal_no = diff.val & (0xFF >> (8 - signal_bits));
+		diff.val >>= signal_bits;
+		if (tail_time.val + diff.val > now.val) {
+			/*
+			 * Do not consume this or subsequent records, which
+			 * apparently happened after our "now" timestamp from
+			 * earlier in the execution of this method.
+			 */
+			break;
+		}
+		tail = tentative_tail;
+		tail_time.val += diff.val;
+		slot = monitoring_slots +
+		       GPIO_MASK_TO_NUM(
+			       gpio_list[gpio_signals_by_no[signal_no]].mask);
+		/* To conserve bandwidth, timestamps are relative to `now`. */
+		ccprintf("  %d %lld %s\n", signal_no, tail_time.val - now.val,
+			 slot->tail_level ? "F" : "R");
+		/* Flush console to avoid truncating output */
+		cflush();
+		slot->tail_level = !slot->tail_level;
+	}
+	buf->tail = tail;
+	buf->tail_time = tail_time;
+	if (buf->overflow) {
+		ccprintf("Error: Buffer overflow\n");
+	}
+
+	return EC_SUCCESS;
+}
+
+static int command_gpio_monitoring_stop(int argc, const char **argv)
+{
+	int gpios[16];
+	int gpio_num = argc - 3;
+	int i;
+	struct cyclic_buffer_header_t *buf = NULL;
+	struct monitoring_slot_t *slot;
+
+	if (gpio_num <= 0 || gpio_num > 16)
+		return EC_ERROR_PARAM_COUNT;
+
+	for (i = 0; i < gpio_num; i++) {
+		gpios[i] = find_signal_by_name(argv[3 + i]);
+		if (gpios[i] == GPIO_COUNT)
+			return EC_ERROR_PARAM3 + i; /* May overflow */
+		slot = monitoring_slots +
+		       GPIO_MASK_TO_NUM(gpio_list[gpios[i]].mask);
+		if (slot->gpio_signal != gpios[i]) {
+			ccprintf("Error: Not monitoring %s\n",
+				 gpio_list[gpios[i]].name);
+			return EC_ERROR_PARAM3 + i;
+		}
+		if (buf == NULL) {
+			buf = slot->buffer;
+		} else if (buf != slot->buffer) {
+			ccprintf(
+				"Error: Not monitoring %s as part of same groups as %s\n",
+				gpio_list[gpios[i]].name,
+				gpio_list[gpios[0]].name);
+			return EC_ERROR_PARAM3 + i;
+		}
+	}
+	if (gpio_num != buf->num_signals) {
+		ccprintf("Error: Not full set of signals monitored\n");
+		return EC_ERROR_INVAL;
+	}
+
+	for (i = 0; i < gpio_num; i++) {
+		gpio_disable_interrupt(gpios[i]);
+	}
+
+	/*
+	 * With no more interrupts modifying the buffer, it can be deallocated.
+	 */
+	num_cur_monitoring--;
+	for (i = 0; i < gpio_num; i++) {
+		slot = monitoring_slots +
+		       GPIO_MASK_TO_NUM(gpio_list[gpios[i]].mask);
+		slot->gpio_signal = GPIO_COUNT;
+		slot->buffer = NULL;
+	}
+
+	if (buf->overflow)
+		atomic_sub(&num_cur_error_conditions, 1);
+
+	free_cyclic_buffer(buf);
+	return EC_SUCCESS;
+}
+
+static int command_gpio_monitoring(int argc, const char **argv)
+{
+	if (argc < 3)
+		return EC_ERROR_PARAM_COUNT;
+	if (!strcasecmp(argv[2], "start"))
+		return command_gpio_monitoring_start(argc, argv);
+	if (!strcasecmp(argv[2], "read"))
+		return command_gpio_monitoring_read(argc, argv);
+	if (!strcasecmp(argv[2], "stop"))
+		return command_gpio_monitoring_stop(argc, argv);
+	return EC_ERROR_PARAM2;
+}
+
+static int command_gpio(int argc, const char **argv)
+{
+	if (argc < 2)
+		return EC_ERROR_PARAM_COUNT;
+	if (!strcasecmp(argv[1], "analog-set"))
+		return command_gpio_analog_set(argc, argv);
+	if (!strcasecmp(argv[1], "monitoring"))
+		return command_gpio_monitoring(argc, argv);
+	if (!strcasecmp(argv[1], "multiset"))
+		return command_gpio_multiset(argc, argv);
+	return EC_ERROR_PARAM1;
+}
+DECLARE_CONSOLE_COMMAND_FLAGS(
+	gpio, command_gpio,
+	"multiset name [level] [mode] [pullmode] [milli_volts]"
+	"\nanalog-set name milli_volts"
+	"\nmonitoring start name..."
+	"\nmonitoring read name..."
+	"\nmonitoring stop name...",
+	"GPIO manipulation", CMD_FLAG_RESTRICTED);
+
+static int command_reinit(int argc, const char **argv)
+{
+	const struct gpio_info *g = gpio_list;
+	int i;
+
+	stop_all_gpio_monitoring();
+
+	/* Set all GPIOs to defaults */
+	for (i = 0; i < GPIO_COUNT; i++, g++) {
+		int flags = g->flags;
+
+		if (flags & GPIO_DEFAULT)
+			continue;
+
+		if (flags & GPIO_ALTERNATE)
+			flags |= extra_alternate_flags(i);
+
+		/* Set up GPIO based on flags */
+		gpio_set_flags_by_mask(g->port, g->mask, flags);
+	}
+
+	/* Disable any DAC (which would override GPIO function of pins) */
+	STM32_DAC_CR = 0;
+
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND_FLAGS(reinit, command_reinit, "",
+			      "Stop any ongoing operation",
+			      CMD_FLAG_RESTRICTED);
+
+static void led_tick(void)
+{
+	/* Indicate ongoing GPIO monitoring by flashing the green LED. */
+	if (num_cur_monitoring)
+		gpio_set_level(GPIO_NUCLEO_LED1,
+			       !gpio_get_level(GPIO_NUCLEO_LED1));
+	else {
+		/*
+		 * If not flashing, leave the green LED on, to indicate that
+		 * HyperDebug firmware is running and ready.
+		 */
+		gpio_set_level(GPIO_NUCLEO_LED1, 1);
+	}
+	/* Indicate error conditions by flashing red LED. */
+	if (atomic_add(&num_cur_error_conditions, 0))
+		gpio_set_level(GPIO_NUCLEO_LED3,
+			       !gpio_get_level(GPIO_NUCLEO_LED3));
+	else {
+		/*
+		 * If not flashing, leave the red LED off.
+		 */
+		gpio_set_level(GPIO_NUCLEO_LED3, 0);
+	}
+}
+DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
diff --git a/board/hyperdebug/gpio.inc b/board/hyperdebug/gpio.inc
new file mode 100644
index 0000000000..f02c55b793
--- /dev/null
+++ b/board/hyperdebug/gpio.inc
@@ -0,0 +1,161 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * List of all GPIO pins available for Host computer to manipulate.
+ * The are named based on their location on the two 70-pin DIL
+ * connectors on either side of the HyperDebug board.  Pins with
+ * special functions are commented out, and declared with relevant
+ * symbolic name further below.
+ */
+
+/*
+ * The common define GPIO_INT_BOTH includes GPIO_INPUT, which interferes with
+ * GPIO_ALTERNATE.  Instead we want to declare the intent to detect either
+ * rising or falling edges, making it conditional on the pins possibly later
+ * being re-configured as GPIO inputs.
+ */
+#define ANY_EDGE (GPIO_INT_F_RISING | GPIO_INT_F_FALLING)
+
+GPIO_INT(CN7_1,			PIN(C, 6),  GPIO_INPUT | ANY_EDGE, gpio_edge)
+GPIO_INT(CN7_2,			PIN(B, 8),  GPIO_ALTERNATE | ANY_EDGE, gpio_edge) /* I2C1 SCL */
+GPIO_INT(CN7_3,			PIN(D, 11), GPIO_INPUT | ANY_EDGE, gpio_edge)
+GPIO_INT(CN7_4,			PIN(B, 9),  GPIO_ALTERNATE | ANY_EDGE, gpio_edge) /* I2C1 SDA */
+GPIO_INT(CN7_5,			PIN(B, 13), GPIO_INPUT | ANY_EDGE, gpio_edge)
+/* CN7_6 is VREFP */
+GPIO_INT(CN7_7,			PIN(D, 12), GPIO_INPUT | ANY_EDGE, gpio_edge)
+/* CN7_8 is GND */
+GPIO_INT(CN7_9,			PIN(A, 4),  GPIO_INPUT | ANY_EDGE, gpio_edge) /* DAC0, ADC12_IN9 */
+GPIO_INT(CN7_10,		PIN(A, 5),  GPIO_INPUT | ANY_EDGE, gpio_edge) /* DAC1, ADC12_IN10 */
+GPIO_INT(CN7_11,		PIN(B, 4),  GPIO_INPUT | ANY_EDGE, gpio_edge)
+GPIO_INT(CN7_12,		PIN(A, 6),  GPIO_INPUT | ANY_EDGE, gpio_edge) /* ADC12_IN11 */
+/*GPIO_INT(CN7_13,		PIN(B, 5),  GPIO_INPUT | ANY_EDGE, gpio_edge) Nucleo USB-C */
+GPIO_INT(CN7_14,		PIN(A, 7),  GPIO_INPUT | ANY_EDGE, gpio_edge) /* ADC12_IN12 */
+GPIO_INT(CN7_15,		PIN(B, 3),  GPIO_INPUT | ANY_EDGE, gpio_edge)
+GPIO_INT(CN7_16,		PIN(D, 14), GPIO_INPUT | ANY_EDGE, gpio_edge)
+/*GPIO_INT(CN7_17,		PIN(A, 4),  GPIO_INPUT | ANY_EDGE, gpio_edge)*/
+GPIO_INT(CN7_18,		PIN(D, 15), GPIO_INPUT | ANY_EDGE, gpio_edge)
+/*GPIO_INT(CN7_19,		PIN(B, 4),  GPIO_INPUT | ANY_EDGE, gpio_edge)*/
+GPIO_INT(CN7_20,		PIN(F, 12), GPIO_INPUT | ANY_EDGE, gpio_edge)
+
+/* CN8_1 is NC */
+GPIO_INT(CN8_2,			PIN(C, 8),  GPIO_INPUT | ANY_EDGE, gpio_edge)
+/* CN8_3 is IOREF */
+GPIO_INT(CN8_4,			PIN(C, 9),  GPIO_INPUT | ANY_EDGE, gpio_edge)
+/* CN8_5 is NRST */
+GPIO_INT(CN8_6,			PIN(C, 10), GPIO_ALTERNATE | ANY_EDGE, gpio_edge) /* UART4 TX */
+/* CN8_7 is 3V3 */
+GPIO_INT(CN8_8,			PIN(C, 11), GPIO_ALTERNATE | ANY_EDGE, gpio_edge) /* UART4 RX */
+/* CN8_9 is 5V */
+GPIO_INT(CN8_10,		PIN(C, 12), GPIO_ALTERNATE | ANY_EDGE, gpio_edge) /* UART5 TX */
+/* CN8_11 is GND */
+GPIO_INT(CN8_12,		PIN(D, 2),  GPIO_ALTERNATE | ANY_EDGE, gpio_edge) /* UART5 RX */
+/* CN8_13 is GND */
+GPIO_INT(CN8_14,		PIN(F, 3),  GPIO_INPUT | ANY_EDGE, gpio_edge)
+/* CN8_15 is VIN */
+GPIO_INT(CN8_16,		PIN(F, 5),  GPIO_INPUT | ANY_EDGE, gpio_edge)
+
+GPIO_INT(CN9_1,			PIN(A, 3),  GPIO_INPUT | ANY_EDGE, gpio_edge)     /* ADC12_IN8 */
+GPIO_INT(CN9_2,			PIN(D, 7),  GPIO_INPUT | ANY_EDGE, gpio_edge)
+GPIO_INT(CN9_3,			PIN(A, 2),  GPIO_INPUT | ANY_EDGE, gpio_edge)     /* ADC12_IN7 */
+GPIO_INT(CN9_4,			PIN(D, 6),  GPIO_ALTERNATE | ANY_EDGE, gpio_edge) /* UART2 RX */
+GPIO_INT(CN9_5,			PIN(C, 3),  GPIO_INPUT | ANY_EDGE, gpio_edge)     /* ADC12_IN4 */
+GPIO_INT(CN9_6,			PIN(D, 5),  GPIO_ALTERNATE | ANY_EDGE, gpio_edge) /* UART2 TX */
+GPIO_INT(CN9_7,			PIN(B, 0),  GPIO_INPUT | ANY_EDGE, gpio_edge)     /* ADC12_IN15 */
+GPIO_INT(CN9_8,			PIN(D, 4),  GPIO_ALTERNATE | ANY_EDGE, gpio_edge) /* SPI2 CODI */
+GPIO_INT(CN9_9,			PIN(C, 1),  GPIO_ALTERNATE | ANY_EDGE, gpio_edge) /* I2C3 SDA, ADC12_IN2 */
+GPIO_INT(CN9_10,		PIN(D, 3),  GPIO_ALTERNATE | ANY_EDGE, gpio_edge) /* SPI2 CIDO */
+GPIO_INT(CN9_11,		PIN(C, 0),  GPIO_ALTERNATE | ANY_EDGE, gpio_edge) /* I2C3 SCL, ADC12_IN1 */
+/* CN9_12 is GND */
+GPIO_INT(CN9_13,		PIN(B, 2),  GPIO_INPUT | ANY_EDGE, gpio_edge)
+GPIO_INT(CN9_14,		PIN(E, 2),  GPIO_INPUT | ANY_EDGE, gpio_edge)
+GPIO_INT(CN9_15,		PIN(B, 6),  GPIO_INPUT | ANY_EDGE, gpio_edge)
+GPIO_INT(CN9_16,		PIN(E, 4),  GPIO_INPUT | ANY_EDGE, gpio_edge)
+GPIO_INT(CN9_17,		PIN(F, 2),  GPIO_INPUT | ANY_EDGE, gpio_edge)
+GPIO_INT(CN9_18,		PIN(E, 5),  GPIO_INPUT | ANY_EDGE, gpio_edge)
+GPIO_INT(CN9_19,		PIN(F, 1),  GPIO_ALTERNATE | ANY_EDGE, gpio_edge) /* I2C2 SCL */
+GPIO_INT(CN9_20,		PIN(E, 6),  GPIO_INPUT | ANY_EDGE, gpio_edge)
+GPIO_INT(CN9_21,		PIN(F, 0),  GPIO_ALTERNATE | ANY_EDGE, gpio_edge) /* I2C2 SDA */
+GPIO_INT(CN9_22,		PIN(E, 3),  GPIO_INPUT | ANY_EDGE, gpio_edge)
+/* CN9_23 is GND */
+GPIO_INT(CN9_24,		PIN(F, 8),  GPIO_INPUT | ANY_EDGE, gpio_edge)
+GPIO_INT(CN9_25,		PIN(D, 0),  GPIO_OUT_HIGH | ANY_EDGE, gpio_edge) /* SPI2 CS */
+GPIO_INT(CN9_26,		PIN(F, 7),  GPIO_INPUT | ANY_EDGE, gpio_edge)
+GPIO_INT(CN9_27,		PIN(D, 1),  GPIO_ALTERNATE | ANY_EDGE, gpio_edge) /* SPI2 CLK */
+GPIO_INT(CN9_28,		PIN(F, 9),  GPIO_INPUT | ANY_EDGE, gpio_edge)
+GPIO_INT(CN9_29,		PIN(G, 0),  GPIO_INPUT | ANY_EDGE, gpio_edge)
+GPIO_INT(CN9_30,		PIN(G, 1),  GPIO_INPUT | ANY_EDGE, gpio_edge)
+
+/* CN10_1 is AVDD */
+GPIO_INT(CN10_2,		PIN(F, 13), GPIO_INPUT | ANY_EDGE, gpio_edge)
+/* CN10_3 is AGND */
+GPIO_INT(CN10_4,		PIN(E, 9),  GPIO_INPUT | ANY_EDGE, gpio_edge)
+/* CN10_5 is GND */
+GPIO_INT(CN10_6,		PIN(E, 11), GPIO_OUT_HIGH | ANY_EDGE, gpio_edge) /* QSPI CS */
+GPIO_INT(CN10_7,		PIN(B, 1),  GPIO_INPUT | ANY_EDGE, gpio_edge)    /* ADC12_IN16 */
+GPIO_INT(CN10_8,		PIN(F, 14), GPIO_ALTERNATE | ANY_EDGE, gpio_edge) /* I2C4 SCL */
+/*GPIO_INT(CN10_9,		PIN(C, 2),  GPIO_INPUT | ANY_EDGE, gpio_edge) Nucleo USB VBUS sense, ADC12_IN3 */
+GPIO_INT(CN10_10,		PIN(E, 13), GPIO_ALTERNATE | ANY_EDGE, gpio_edge) /* QSPI D1 */
+GPIO_INT(CN10_11,		PIN(A, 1),  GPIO_INPUT | ANY_EDGE, gpio_edge)     /* ADC12_IN6 */
+GPIO_INT(CN10_12,		PIN(F, 15), GPIO_ALTERNATE | ANY_EDGE, gpio_edge) /* I2C4 SDA */
+/*GPIO_INT(CN10_13,		PIN(A, 2),  GPIO_INPUT | ANY_EDGE, gpio_edge)*/
+GPIO_INT(CN10_14,		PIN(D, 8),  GPIO_ALTERNATE | ANY_EDGE, gpio_edge) /* UART3 TX */
+GPIO_INT(CN10_15,		PIN(B, 10), GPIO_INPUT | ANY_EDGE, gpio_edge)
+GPIO_INT(CN10_16,		PIN(D, 9),  GPIO_ALTERNATE | ANY_EDGE, gpio_edge) /* UART3 RX */
+/* CN10_17 is GND */
+GPIO_INT(CN10_18,		PIN(E, 8),  GPIO_INPUT | ANY_EDGE, gpio_edge)
+GPIO_INT(CN10_19,		PIN(E, 15), GPIO_ALTERNATE | ANY_EDGE, gpio_edge) /* QSPI D3 */
+GPIO_INT(CN10_20,		PIN(E, 7),  GPIO_INPUT | ANY_EDGE, gpio_edge)
+/*GPIO_INT(CN10_21,		PIN(B, 0),  GPIO_INPUT | ANY_EDGE, gpio_edge)*/
+/* CN10_22 is GND */
+GPIO_INT(CN10_23,		PIN(E, 12), GPIO_ALTERNATE | ANY_EDGE, gpio_edge) /* QSPI D0 */
+GPIO_INT(CN10_24,		PIN(E, 10), GPIO_ALTERNATE | ANY_EDGE, gpio_edge) /* QSPI CLK */
+GPIO_INT(CN10_25,		PIN(E, 14), GPIO_ALTERNATE | ANY_EDGE, gpio_edge) /* QSPI D2 */
+/*GPIO_INT(CN10_26,		PIN(E, 12), GPIO_INPUT | ANY_EDGE, gpio_edge) QSPI */
+/* CN10_27 is GND */
+/*GPIO_INT(CN10_28,		PIN(E, 14), GPIO_INPUT | ANY_EDGE, gpio_edge) QSPI */
+GPIO_INT(CN10_29,		PIN(A, 0),  GPIO_INPUT | ANY_EDGE, gpio_edge)     /* ADC12_IN5 */
+/*GPIO_INT(CN10_30,		PIN(E, 15), GPIO_INPUT | ANY_EDGE, gpio_edge) QSPI */
+GPIO_INT(CN10_31,		PIN(A, 8),  GPIO_INPUT | ANY_EDGE, gpio_edge)
+/*GPIO_INT(CN10_32,		PIN(B, 10), GPIO_INPUT | ANY_EDGE, gpio_edge)*/
+GPIO_INT(CN10_33,		PIN(E, 0),  GPIO_INPUT | ANY_EDGE, gpio_edge)
+GPIO_INT(CN10_34,		PIN(B, 11), GPIO_INPUT | ANY_EDGE, gpio_edge)
+
+/* These pins are used for USART and are set to alternate mode below */
+GPIO_INT(HYPER_CONSOLE_TX,	PIN(G, 7),  GPIO_ALTERNATE | ANY_EDGE, gpio_edge)
+GPIO_INT(HYPER_CONSOLE_RX,	PIN(G, 8),  GPIO_ALTERNATE | ANY_EDGE, gpio_edge)
+
+/* USB pins */
+GPIO(USB_FS_DM,			PIN(A, 11), GPIO_ALTERNATE)
+GPIO(USB_FS_DP,			PIN(A, 12), GPIO_ALTERNATE)
+
+/* Signals for hardware on the Nucleo board itself */
+GPIO_INT(NUCLEO_LED1,		PIN(C, 7),  GPIO_OUT_HIGH | ANY_EDGE, gpio_edge) /* Green */
+GPIO_INT(NUCLEO_LED2,		PIN(B, 7),  GPIO_OUT_LOW | ANY_EDGE, gpio_edge) /* Blue */
+GPIO_INT(NUCLEO_LED3,		PIN(A, 9),  GPIO_OUT_LOW | ANY_EDGE, gpio_edge) /* Red */
+GPIO_INT(NUCLEO_USER_BTN,	PIN(C, 13), GPIO_INPUT | ANY_EDGE, gpio_edge) /* User button */
+
+/* Unimplemented signals since we are not an EC */
+UNIMPLEMENTED(ENTERING_RW)
+UNIMPLEMENTED(WP_L)
+
+
+ALTERNATE(PIN_MASK(A, 0x1800), 10, MODULE_USB, 0) /* USB: PA11/12 */
+
+ALTERNATE(PIN_MASK(D, 0x0060), 7, MODULE_UART, 0) /* USART2: PD5/PD6 - OT UART */
+ALTERNATE(PIN_MASK(C, 0x0C00), 8, MODULE_UART, 0) /* USART4: PC10/PC11 - AP UART */
+ALTERNATE(PIN_MASK(D, 0x0300), 7, MODULE_UART, 0) /* USART3: PD8/PD9 - EC UART */
+ALTERNATE(PIN_MASK(C, 0x1000), 8, MODULE_UART, 0) /* USART5: PC12 - FP MCU UART */
+ALTERNATE(PIN_MASK(D, 0x0004), 8, MODULE_UART, 0) /* USART5: PD2 - FP MCU UART */
+ALTERNATE(PIN_MASK(G, 0x0180), 8, MODULE_UART, 0) /* LPUART1: PG7/PG8 - HyperDebug console */
+
+ALTERNATE(PIN_MASK(F, 0x0003), 4, MODULE_I2C, GPIO_OPEN_DRAIN) /* I2C2: PF0/PF1 */
+ALTERNATE(PIN_MASK(B, 0x0300), 4, MODULE_I2C, GPIO_OPEN_DRAIN) /* I2C1: PB8/PB9 */
+ALTERNATE(PIN_MASK(C, 0x0003), 4, MODULE_I2C, GPIO_OPEN_DRAIN) /* I2C3: PC0/PC1 */
+ALTERNATE(PIN_MASK(F, 0xC000), 4, MODULE_I2C, GPIO_OPEN_DRAIN) /* I2C4: PF14/PF15 */
+ALTERNATE(PIN_MASK(E, 0xF400), 10, MODULE_SPI, 0) /* QSPI: PE10/PE12-15 */
+ALTERNATE(PIN_MASK(D, 0x001A), 5, MODULE_SPI, 0) /* SPI2: PD1/PD3/PD4 SCK/CIDO/CODI */
diff --git a/board/hyperdebug/i2c.c b/board/hyperdebug/i2c.c
new file mode 100644
index 0000000000..bbb86d0d6b
--- /dev/null
+++ b/board/hyperdebug/i2c.c
@@ -0,0 +1,155 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* HyperDebug I2C logic and console commands */
+
+#include "common.h"
+#include "console.h"
+#include "gpio.h"
+#include "i2c.h"
+#include "util.h"
+
+/* I2C ports */
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "I2C1",
+	  .port = 0,
+	  .kbps = 100,
+	  .scl = GPIO_CN7_2,
+	  .sda = GPIO_CN7_4,
+	  .flags = I2C_PORT_FLAG_DYNAMIC_SPEED },
+	{ .name = "I2C2",
+	  .port = 1,
+	  .kbps = 100,
+	  .scl = GPIO_CN9_19,
+	  .sda = GPIO_CN9_21,
+	  .flags = I2C_PORT_FLAG_DYNAMIC_SPEED },
+	{ .name = "I2C3",
+	  .port = 2,
+	  .kbps = 100,
+	  .scl = GPIO_CN9_11,
+	  .sda = GPIO_CN9_9,
+	  .flags = I2C_PORT_FLAG_DYNAMIC_SPEED },
+	{ .name = "I2C4",
+	  .port = 3,
+	  .kbps = 100,
+	  .scl = GPIO_CN10_8,
+	  .sda = GPIO_CN10_12,
+	  .flags = I2C_PORT_FLAG_DYNAMIC_SPEED },
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+int usb_i2c_board_is_enabled(void)
+{
+	return 1;
+}
+
+/*
+ * Find i2c port by name or by number.  Returns an index into i2c_ports[], or on
+ * error a negative value.
+ */
+static int find_i2c_by_name(const char *name)
+{
+	int i;
+	char *e;
+	i = strtoi(name, &e, 0);
+
+	if (!*e && i < i2c_ports_used)
+		return i;
+
+	for (i = 0; i < i2c_ports_used; i++) {
+		if (!strcasecmp(name, i2c_ports[i].name))
+			return i;
+	}
+
+	/* I2C device not found */
+	return -1;
+}
+
+static void print_i2c_info(int index)
+{
+	uint32_t bits_per_second = 1000 * i2c_freq_to_khz(i2c_get_freq(index));
+
+	ccprintf("  %d %s %d bps\n", index, i2c_ports[index].name,
+		 bits_per_second);
+
+	/* Flush console to avoid truncating output */
+	cflush();
+}
+
+/*
+ * Get information about one or all I2C ports.
+ */
+static int command_i2c_info(int argc, const char **argv)
+{
+	int i;
+
+	/* If a I2C port is specified, print only that one */
+	if (argc == 3) {
+		int index = find_i2c_by_name(argv[2]);
+		if (index < 0) {
+			ccprintf("I2C port not found\n");
+			return EC_ERROR_PARAM2;
+		}
+
+		print_i2c_info(index);
+		return EC_SUCCESS;
+	}
+
+	/* Otherwise print them all */
+	for (i = 0; i < i2c_ports_used; i++) {
+		print_i2c_info(i);
+	}
+
+	return EC_SUCCESS;
+}
+
+static int command_i2c_set_speed(int argc, const char **argv)
+{
+	int index;
+	uint32_t desired_speed;
+	char *e;
+	if (argc < 5)
+		return EC_ERROR_PARAM_COUNT;
+
+	index = find_i2c_by_name(argv[3]);
+	if (index < 0)
+		return EC_ERROR_PARAM3;
+
+	desired_speed = strtoi(argv[4], &e, 0);
+	if (*e)
+		return EC_ERROR_PARAM4;
+
+	if (desired_speed >= 1000000) {
+		i2c_set_freq(index, I2C_FREQ_1000KHZ);
+	} else if (desired_speed >= 400000) {
+		i2c_set_freq(index, I2C_FREQ_400KHZ);
+	} else {
+		i2c_set_freq(index, I2C_FREQ_100KHZ);
+	}
+	return EC_SUCCESS;
+}
+
+static int command_i2c_set(int argc, const char **argv)
+{
+	if (argc < 3)
+		return EC_ERROR_PARAM_COUNT;
+	if (!strcasecmp(argv[2], "speed"))
+		return command_i2c_set_speed(argc, argv);
+	return EC_ERROR_PARAM2;
+}
+
+static int command_i2c(int argc, const char **argv)
+{
+	if (argc < 2)
+		return EC_ERROR_PARAM_COUNT;
+	if (!strcasecmp(argv[1], "info"))
+		return command_i2c_info(argc, argv);
+	if (!strcasecmp(argv[1], "set"))
+		return command_i2c_set(argc, argv);
+	return EC_ERROR_PARAM1;
+}
+DECLARE_CONSOLE_COMMAND_FLAGS(i2c, command_i2c,
+			      "info [PORT]"
+			      "\nset speed PORT BPS",
+			      "I2C bus manipulation", CMD_FLAG_RESTRICTED);
diff --git a/board/hyperdebug/spi.c b/board/hyperdebug/spi.c
new file mode 100644
index 0000000000..eee1626281
--- /dev/null
+++ b/board/hyperdebug/spi.c
@@ -0,0 +1,479 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* HyperDebug SPI logic and console commands */
+
+#include "common.h"
+#include "console.h"
+#include "dma.h"
+#include "gpio.h"
+#include "registers.h"
+#include "spi.h"
+#include "stm32-dma.h"
+#include "timer.h"
+#include "usb_spi.h"
+#include "util.h"
+
+#define OCTOSPI_CLOCK (CPU_CLOCK)
+#define SPI_CLOCK (CPU_CLOCK)
+
+/* SPI devices, default to 406 kb/s for all. */
+struct spi_device_t spi_devices[] = {
+	{ .name = "SPI2",
+	  .port = 1,
+	  .div = 7,
+	  .gpio_cs = GPIO_CN9_25,
+	  .usb_flags = USB_SPI_ENABLED },
+	{ .name = "QSPI",
+	  .port = -1 /* OCTOSPI */,
+	  .div = 255,
+	  .gpio_cs = GPIO_CN10_6,
+	  .usb_flags = USB_SPI_ENABLED | USB_SPI_CUSTOM_SPI_DEVICE |
+		       USB_SPI_FLASH_DUAL_SUPPORT | USB_SPI_FLASH_QUAD_SUPPORT |
+		       USB_SPI_FLASH_DTR_SUPPORT },
+};
+const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
+
+/*
+ * Find spi device by name or by number.  Returns an index into spi_devices[],
+ * or on error a negative value.
+ */
+static int find_spi_by_name(const char *name)
+{
+	int i;
+	char *e;
+	i = strtoi(name, &e, 0);
+
+	if (!*e && i < spi_devices_used)
+		return i;
+
+	for (i = 0; i < spi_devices_used; i++) {
+		if (!strcasecmp(name, spi_devices[i].name))
+			return i;
+	}
+
+	/* SPI device not found */
+	return -1;
+}
+
+static void print_spi_info(int index)
+{
+	uint32_t bits_per_second;
+
+	if (spi_devices[index].usb_flags & USB_SPI_CUSTOM_SPI_DEVICE) {
+		// OCTOSPI as 8 bit prescaler, dividing clock by 1..256.
+		bits_per_second = OCTOSPI_CLOCK / (spi_devices[index].div + 1);
+	} else {
+		// Other SPIs have prescaler by power of two 2, 4, 8, ..., 256.
+		bits_per_second = SPI_CLOCK / (2 << spi_devices[index].div);
+	}
+
+	ccprintf("  %d %s %d bps\n", index, spi_devices[index].name,
+		 bits_per_second);
+
+	/* Flush console to avoid truncating output */
+	cflush();
+}
+
+/*
+ * Get information about one or all SPI ports.
+ */
+static int command_spi_info(int argc, const char **argv)
+{
+	int i;
+
+	/* If a SPI target is specified, print only that one */
+	if (argc == 3) {
+		int index = find_spi_by_name(argv[2]);
+		if (index < 0) {
+			ccprintf("SPI device not found\n");
+			return EC_ERROR_PARAM2;
+		}
+
+		print_spi_info(index);
+		return EC_SUCCESS;
+	}
+
+	/* Otherwise print them all */
+	for (i = 0; i < spi_devices_used; i++) {
+		print_spi_info(i);
+	}
+
+	return EC_SUCCESS;
+}
+
+static int command_spi_set_speed(int argc, const char **argv)
+{
+	int index;
+	uint32_t desired_speed;
+	char *e;
+	if (argc < 5)
+		return EC_ERROR_PARAM_COUNT;
+
+	index = find_spi_by_name(argv[3]);
+	if (index < 0)
+		return EC_ERROR_PARAM3;
+
+	desired_speed = strtoi(argv[4], &e, 0);
+	if (*e)
+		return EC_ERROR_PARAM4;
+
+	if (spi_devices[index].usb_flags & USB_SPI_CUSTOM_SPI_DEVICE) {
+		/*
+		 * Find prescaler value by division, rounding up in order to get
+		 * slightly slower speed than requested, if it cannot be matched
+		 * exactly.
+		 */
+		int divisor =
+			(OCTOSPI_CLOCK + desired_speed - 1) / desired_speed - 1;
+		if (divisor >= 256)
+			divisor = 255;
+		STM32_OCTOSPI_DCR2 = spi_devices[index].div = divisor;
+	} else {
+		int divisor = 7;
+		/*
+		 * Find the smallest divisor that result in a speed not faster
+		 * than what was requested.
+		 */
+		while (divisor > 0) {
+			if (SPI_CLOCK / (2 << (divisor - 1)) > desired_speed) {
+				/* One step further would make the clock too
+				 * fast, stop here. */
+				break;
+			}
+			divisor--;
+		}
+
+		/*
+		 * Re-initialize spi controller to apply the new clock divisor.
+		 */
+		spi_enable(&spi_devices[index], 0);
+		spi_devices[index].div = divisor;
+		spi_enable(&spi_devices[index], 1);
+	}
+
+	return EC_SUCCESS;
+}
+
+static int command_spi_set(int argc, const char **argv)
+{
+	if (argc < 3)
+		return EC_ERROR_PARAM_COUNT;
+	if (!strcasecmp(argv[2], "speed"))
+		return command_spi_set_speed(argc, argv);
+	return EC_ERROR_PARAM2;
+}
+
+static int command_spi(int argc, const char **argv)
+{
+	if (argc < 2)
+		return EC_ERROR_PARAM_COUNT;
+	if (!strcasecmp(argv[1], "info"))
+		return command_spi_info(argc, argv);
+	if (!strcasecmp(argv[1], "set"))
+		return command_spi_set(argc, argv);
+	return EC_ERROR_PARAM1;
+}
+DECLARE_CONSOLE_COMMAND_FLAGS(spi, command_spi,
+			      "info [PORT]"
+			      "\nset speed PORT BPS",
+			      "SPI bus manipulation", CMD_FLAG_RESTRICTED);
+
+/******************************************************************************
+ * OCTOSPI driver.
+ */
+
+/*
+ * Wait for a certain set of status bits to all be asserted.
+ */
+static int octospi_wait_for(uint32_t flags, timestamp_t deadline)
+{
+	while ((STM32_OCTOSPI_SR & flags) != flags) {
+		timestamp_t now = get_time();
+		if (timestamp_expired(deadline, &now))
+			return EC_ERROR_TIMEOUT;
+	}
+	return EC_SUCCESS;
+}
+
+/*
+ * Board-specific SPI driver entry point, called by usb_spi.c.
+ */
+void usb_spi_board_enable(void)
+{
+	/* All initialization already done in board_init(). */
+}
+
+void usb_spi_board_disable(void)
+{
+}
+
+static const struct dma_option dma_octospi_option = {
+	.channel = STM32_DMAC_CH13,
+	.periph = (void *)&STM32_OCTOSPI_DR,
+	.flags = STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT,
+};
+
+static bool previous_cs;
+static timestamp_t deadline;
+
+/*
+ * Board-specific SPI driver entry point, called by usb_spi.c.  On this board,
+ * the only spi device declared as requiring board specific driver is OCTOSPI.
+ *
+ * Actually, there is nothing board-specific in the code below, as it merely
+ * implements the serial flash USB protocol extensions on the OctoSPI hardware
+ * found on STM32L5 chips (and probably others).  For now, however, HyperDebug
+ * is the only board that uses a chip with such an OctoSPI controller, so until
+ * we have seen this code being generally useful, it will live in
+ * board/hyperdebug.
+ */
+int usb_spi_board_transaction_async(const struct spi_device_t *spi_device,
+				    uint32_t flash_flags, const uint8_t *txdata,
+				    int txlen, uint8_t *rxdata, int rxlen)
+{
+	uint32_t opcode = 0, address = 0;
+	const uint32_t mode = flash_flags & FLASH_FLAG_MODE_MSK;
+	const uint8_t width = (flash_flags & FLASH_FLAG_WIDTH_MSK) >>
+			      FLASH_FLAG_WIDTH_POS;
+	uint8_t opcode_len = (flash_flags & FLASH_FLAG_OPCODE_LEN_MSK) >>
+			     FLASH_FLAG_OPCODE_LEN_POS;
+	uint8_t addr_len = (flash_flags & FLASH_FLAG_ADDR_LEN_MSK) >>
+			   FLASH_FLAG_ADDR_LEN_POS;
+	const uint8_t dummy_cycles =
+		(flash_flags & FLASH_FLAG_DUMMY_CYCLES_MSK) >>
+		FLASH_FLAG_DUMMY_CYCLES_POS;
+	uint32_t data_len;
+	uint32_t control_value = 0;
+
+	if (!flash_flags) {
+		/*
+		 * This is a request does not use the extended format with SPI
+		 * flash flags, but is for doing plain write-then-read of single
+		 * lane (COPI/CIPO) SPI data.
+		 */
+		if (rxlen == SPI_READBACK_ALL) {
+			cprints(CC_SPI,
+				"Full duplex not supported by OctoSPI hardware");
+			return EC_ERROR_UNIMPLEMENTED;
+		} else if (!rxlen && !txlen) {
+			/* No operation requested, done. */
+			return EC_SUCCESS;
+		} else if (!rxlen) {
+			/*
+			 * Transmit-only transaction.  This is implemented by
+			 * not using any of the up to 12 bytes of instructions,
+			 * but as all "data".
+			 */
+			flash_flags |= FLASH_FLAG_READ_WRITE_WRITE;
+		} else if (txlen <= 12) {
+			/*
+			 * Sending of up to 12 bytes, followed by reading a
+			 * possibly large number of bytes.  This is implemented
+			 * by a "read" transaction using the instruction and
+			 * address feature of OctoSPI.
+			 */
+			if (txlen <= 4) {
+				opcode_len = txlen;
+			} else {
+				opcode_len = 4;
+				addr_len = txlen - 4;
+			}
+		} else {
+			/*
+			 * Sending many bytes, followed by reading.  This would
+			 * have to be implemented as two separate OctoSPI
+			 * transactions.
+			 */
+			cprints(CC_SPI,
+				"General write-then-read not supported by OctoSPI hardware");
+			return EC_ERROR_UNIMPLEMENTED;
+		}
+	}
+
+	previous_cs = gpio_get_level(spi_device->gpio_cs);
+
+	/* Drive chip select low */
+	gpio_set_level(spi_device->gpio_cs, 0);
+
+	/* Deadline on the entire SPI transaction. */
+	deadline.val = get_time().val + OCTOSPI_TRANSACTION_TIMEOUT_US;
+
+	if ((flash_flags & FLASH_FLAG_READ_WRITE_MSK) ==
+	    FLASH_FLAG_READ_WRITE_WRITE) {
+		data_len = txlen - opcode_len - addr_len;
+		/* Enable OCTOSPI, indirect write mode. */
+		STM32_OCTOSPI_CR = STM32_OCTOSPI_CR_FMODE_IND_WRITE |
+				   STM32_OCTOSPI_CR_DMAEN | STM32_OCTOSPI_CR_EN;
+	} else {
+		data_len = rxlen;
+		/* Enable OCTOSPI, indirect read mode. */
+		STM32_OCTOSPI_CR = STM32_OCTOSPI_CR_FMODE_IND_READ |
+				   STM32_OCTOSPI_CR_DMAEN | STM32_OCTOSPI_CR_EN;
+	}
+
+	/* Clear completion flag from last transaction. */
+	STM32_OCTOSPI_FCR = STM32_OCTOSPI_FCR_CTCF;
+
+	/* Data length. */
+	STM32_OCTOSPI_DLR = data_len - 1;
+
+	/*
+	 * Set up the number of bytes and data width of each of the opcode,
+	 * address, and "alternate" stages of the initial command bytes.
+	 */
+	if (opcode_len == 0) {
+		control_value |= STM32_OCTOSPI_CCR_IMODE_NONE;
+	} else {
+		control_value |= (opcode_len - 1)
+				 << STM32_OCTOSPI_CCR_ISIZE_POS;
+		if (mode < FLASH_FLAG_MODE_NNN) {
+			// Opcode phase is single-lane
+			control_value |= 1 << STM32_OCTOSPI_CCR_IMODE_POS;
+		} else {
+			// Opcode phase is multi-lane
+			control_value |= (width + 1)
+					 << STM32_OCTOSPI_CCR_IMODE_POS;
+			if (flash_flags & FLASH_FLAG_DTR)
+				control_value |= STM32_OCTOSPI_CCR_IDTR;
+		}
+		for (int i = 0; i < opcode_len; i++) {
+			opcode <<= 8;
+			opcode |= *txdata++;
+			txlen--;
+		}
+	}
+	if (addr_len == 0) {
+		control_value |= STM32_OCTOSPI_CCR_ADMODE_NONE;
+		control_value |= STM32_OCTOSPI_CCR_ABMODE_NONE;
+	} else if (addr_len <= 4) {
+		control_value |= (addr_len - 1) << STM32_OCTOSPI_CCR_ADSIZE_POS;
+		if (mode < FLASH_FLAG_MODE_1NN) {
+			// Address phase is single-lane
+			control_value |= 1 << STM32_OCTOSPI_CCR_ADMODE_POS;
+		} else {
+			// Address phase is multi-lane
+			control_value |= (width + 1)
+					 << STM32_OCTOSPI_CCR_ADMODE_POS;
+			if (flash_flags & FLASH_FLAG_DTR)
+				control_value |= STM32_OCTOSPI_CCR_ADDTR;
+		}
+		for (int i = 0; i < addr_len; i++) {
+			address <<= 8;
+			address |= *txdata++;
+			txlen--;
+		}
+		control_value |= STM32_OCTOSPI_CCR_ABMODE_NONE;
+	} else {
+		uint32_t alternate = 0;
+		control_value |= 3 << STM32_OCTOSPI_CCR_ADSIZE_POS;
+		control_value |= (addr_len - 5) << STM32_OCTOSPI_CCR_ABSIZE_POS;
+		if (mode < FLASH_FLAG_MODE_1NN) {
+			// Address phase is single-lane
+			control_value |= 1 << STM32_OCTOSPI_CCR_ADMODE_POS;
+			control_value |= 1 << STM32_OCTOSPI_CCR_ABMODE_POS;
+		} else {
+			// Address phase is multi-lane
+			control_value |= (width + 1)
+					 << STM32_OCTOSPI_CCR_ADMODE_POS;
+			control_value |= (width + 1)
+					 << STM32_OCTOSPI_CCR_ABMODE_POS;
+			if (flash_flags & FLASH_FLAG_DTR)
+				control_value |= STM32_OCTOSPI_CCR_ADDTR |
+						 STM32_OCTOSPI_CCR_ABDTR;
+		}
+		for (int i = 0; i < 4; i++) {
+			address <<= 8;
+			address |= *txdata++;
+			txlen--;
+		}
+		for (int i = 0; i < addr_len - 4; i++) {
+			alternate <<= 8;
+			alternate |= *txdata++;
+			txlen--;
+		}
+		STM32_OCTOSPI_ABR = alternate;
+	}
+	/* Set up how many bytes to read/write after the initial command. */
+	if (data_len == 0) {
+		control_value |= STM32_OCTOSPI_CCR_DMODE_NONE;
+	} else {
+		if (mode < FLASH_FLAG_MODE_11N) {
+			// Data phase is single-lane
+			control_value |= 1 << STM32_OCTOSPI_CCR_DMODE_POS;
+		} else {
+			// Data phase is multi-lane
+			control_value |= (width + 1)
+					 << STM32_OCTOSPI_CCR_DMODE_POS;
+			if (flash_flags & FLASH_FLAG_DTR)
+				control_value |= STM32_OCTOSPI_CCR_DDTR;
+		}
+	}
+
+	/* Dummy cycles. */
+	STM32_OCTOSPI_TCR = dummy_cycles << STM32_OCTOSPI_TCR_DCYC_POS;
+
+	STM32_OCTOSPI_CCR = control_value;
+
+	/* Set instruction and address registers, triggering the start of the
+	 * write+read transaction. */
+	STM32_OCTOSPI_IR = opcode;
+	STM32_OCTOSPI_AR = address;
+
+	if ((flash_flags & FLASH_FLAG_READ_WRITE_MSK) ==
+	    FLASH_FLAG_READ_WRITE_WRITE) {
+		if (txlen > 0) {
+			dma_chan_t *txdma = dma_get_channel(STM32_DMAC_CH13);
+			dma_prepare_tx(&dma_octospi_option, txlen, txdata);
+			dma_go(txdma);
+		}
+	} else {
+		if (rxlen > 0) {
+			dma_start_rx(&dma_octospi_option, rxlen, rxdata);
+		}
+	}
+
+	return EC_SUCCESS;
+}
+
+int usb_spi_board_transaction_is_complete(const struct spi_device_t *spi_device)
+{
+	/* Query the "transaction complete flag" of the status register. */
+	return STM32_OCTOSPI_SR & STM32_OCTOSPI_SR_TCF;
+}
+
+int usb_spi_board_transaction_flush(const struct spi_device_t *spi_device)
+{
+	/*
+	 * Wait until DMA transfer is complete (no-op if DMA not started because
+	 * of zero-length transfer).
+	 */
+	int rv = dma_wait(STM32_DMAC_CH13);
+	dma_disable(STM32_DMAC_CH13);
+	if (rv != EC_SUCCESS)
+		return rv;
+
+	/*
+	 * Ensure that all bits of the last byte has been shifted onto the SPI
+	 * bus.
+	 */
+	rv = octospi_wait_for(STM32_OCTOSPI_SR_TCF, deadline);
+
+	/* Return chip select to previous level. */
+	gpio_set_level(spi_device->gpio_cs, previous_cs);
+
+	return rv;
+}
+
+int usb_spi_board_transaction(const struct spi_device_t *spi_device,
+			      uint32_t flash_flags, const uint8_t *txdata,
+			      int txlen, uint8_t *rxdata, int rxlen)
+{
+	int rv = usb_spi_board_transaction_async(spi_device, flash_flags,
+						 txdata, txlen, rxdata, rxlen);
+	if (rv == EC_SUCCESS) {
+		rv = usb_spi_board_transaction_flush(spi_device);
+	}
+	return rv;
+}
diff --git a/board/icarus/battery.c b/board/icarus/battery.c
new file mode 100644
index 0000000000..5e1671f5f3
--- /dev/null
+++ b/board/icarus/battery.c
@@ -0,0 +1,189 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "battery_fuel_gauge.h"
+#include "gpio.h"
+
+const struct board_batt_params board_battery_info[] = {
+	/* LGC AP18C8K Battery Information */
+	[BATTERY_LGC_AP18C8K] = {
+		.fuel_gauge = {
+			.manuf_name = "LGC KT0030G020",
+			.device_name = "AP18C8K",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.reg_addr = 0x43,
+				.reg_mask = 0x0001,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max		= 13050,
+			.voltage_normal		= 11250,
+			.voltage_min		= 9000,
+			.precharge_current	= 256,
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 75,
+		},
+	},
+	/* Murata AP18C4K Battery Information */
+	[BATTERY_MURATA_AP18C4K] = {
+		.fuel_gauge = {
+			.manuf_name = "Murata KT00304012",
+			.device_name = "AP18C4K",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.reg_addr = 0x0,
+				.reg_mask = 0x2000,
+				.disconnect_val = 0x2000,
+			},
+		},
+		.batt_info = {
+			.voltage_max		= 13200,
+			.voltage_normal		= 11400,
+			.voltage_min		= 9000,
+			.precharge_current	= 256,
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 75,
+		},
+	},
+	/* Panasonic AP19B5K Battery Information */
+	[BATTERY_PANASONIC_AP19B5K_KT00305011] = {
+		.fuel_gauge = {
+			.manuf_name = "PANASONIC KT00305011",
+			.device_name = "AP19B5K",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.reg_addr = 0x0,
+				.reg_mask = 0x4000,
+				.disconnect_val = 0x0,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13200,
+			.voltage_normal		= 11550,
+			.voltage_min		= 9000,
+			.precharge_current	= 256,
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 75,
+		},
+	},
+	/* LGC AP19B8K Battery Information */
+	 [BATTERY_LGC_AP19B8K] = {
+		.fuel_gauge = {
+			.manuf_name = "LGC KT0030G022",
+			.device_name = "AP19B8K",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.reg_addr = 0x43,
+				.reg_mask = 0x0001,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max            = 13050,
+			.voltage_normal         = 11250,
+			.voltage_min            = 9000,
+			.precharge_current      = 256,
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 50,
+			.charging_min_c         = 0,
+			.charging_max_c         = 60,
+			.discharging_min_c      = -20,
+			.discharging_max_c      = 75,
+		},
+	},
+	/* COSMX AP20CBL Battery Information */
+	 [BATTERY_COSMX_AP20CBL] = {
+		.fuel_gauge = {
+			.manuf_name = "COSMX KT0030B002",
+			.device_name = "AP20CBL",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0002,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max            = 13200,
+			.voltage_normal         = 11550,
+			.voltage_min            = 9000,
+			.precharge_current      = 256,
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 50,
+			.charging_min_c         = 0,
+			.charging_max_c         = 60,
+			.discharging_min_c      = -20,
+			.discharging_max_c      = 75,
+		},
+	},
+	/* SMP AP18C7K Battery Information */
+	 [BATTERY_SMP_AP18C7K] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP KT00307010",
+			.device_name = "AP18C7K",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0002,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max            = 13200,
+			.voltage_normal         = 11550,
+			.voltage_min            = 9000,
+			.precharge_current      = 256,
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 45,
+			.charging_min_c         = 0,
+			.charging_max_c         = 60,
+			.discharging_min_c      = -20,
+			.discharging_max_c      = 75,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_LGC_AP18C8K;
+
+enum battery_present battery_hw_present(void)
+{
+	return gpio_get_level(GPIO_EC_BATT_PRES_ODL) ? BP_NO : BP_YES;
+}
diff --git a/board/icarus/board.c b/board/icarus/board.c
new file mode 100644
index 0000000000..33b2d7768c
--- /dev/null
+++ b/board/icarus/board.c
@@ -0,0 +1,286 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc.h"
+#include "backlight.h"
+#include "button.h"
+#include "charge_manager.h"
+#include "charge_ramp.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "driver/battery/max17055.h"
+#include "driver/bc12/pi3usb9201.h"
+#include "driver/charger/isl923x.h"
+#include "driver/tcpm/it83xx_pd.h"
+#include "driver/usb_mux/it5205.h"
+#include "ec_commands.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "i2c.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "panic.h"
+#include "power.h"
+#include "power_button.h"
+#include "registers.h"
+#include "spi.h"
+#include "system.h"
+#include "task.h"
+#include "tcpm/tcpm.h"
+#include "timer.h"
+#include "uart.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd_tcpm.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/*
+ * Map keyboard connector pins to EC GPIO pins for factory test.
+ * Pins mapped to {-1, -1} are skipped.
+ * The connector has 24 pins total, and there is no pin 0.
+ */
+const int keyboard_factory_scan_pins[][2] = {
+	{ -1, -1 },	   { GPIO_KSO_H, 4 }, { GPIO_KSO_H, 0 },
+	{ GPIO_KSO_H, 1 }, { GPIO_KSO_H, 3 }, { GPIO_KSO_H, 2 },
+	{ -1, -1 },	   { -1, -1 },	      { GPIO_KSO_L, 5 },
+	{ GPIO_KSO_L, 6 }, { -1, -1 },	      { GPIO_KSO_L, 3 },
+	{ GPIO_KSO_L, 2 }, { GPIO_KSI, 0 },   { GPIO_KSO_L, 1 },
+	{ GPIO_KSO_L, 4 }, { GPIO_KSI, 3 },   { GPIO_KSI, 2 },
+	{ GPIO_KSO_L, 0 }, { GPIO_KSI, 5 },   { GPIO_KSI, 4 },
+	{ GPIO_KSO_L, 7 }, { GPIO_KSI, 6 },   { GPIO_KSI, 7 },
+	{ GPIO_KSI, 1 },   { -1, -1 },	      { GPIO_KSO_H, 5 },
+	{ -1, -1 },	   { GPIO_KSO_H, 6 }, { -1, -1 },
+	{ -1, -1 },
+};
+
+const int keyboard_factory_scan_pins_used =
+	ARRAY_SIZE(keyboard_factory_scan_pins);
+
+/* Wake-up pins for hibernate */
+const enum gpio_signal hibernate_wake_pins[] = {
+	GPIO_AC_PRESENT,
+	GPIO_LID_OPEN,
+	GPIO_POWER_BUTTON_L,
+};
+const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
+
+/******************************************************************************/
+/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
+const struct adc_t adc_channels[] = {
+	[ADC_BOARD_ID] = { "BOARD_ID", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0,
+			   CHIP_ADC_CH1 },
+	[ADC_EC_SKU_ID] = { "EC_SKU_ID", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0,
+			    CHIP_ADC_CH2 },
+	[ADC_VBUS] = { "VBUS", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0,
+		       CHIP_ADC_CH0 },
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/******************************************************************************/
+/* I2C ports */
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "typec",
+	  .port = IT83XX_I2C_CH_C,
+	  .kbps = 400,
+	  .scl = GPIO_I2C_C_SCL,
+	  .sda = GPIO_I2C_C_SDA },
+	{ .name = "other",
+	  .port = IT83XX_I2C_CH_B,
+	  .kbps = 100,
+	  .scl = GPIO_I2C_B_SCL,
+	  .sda = GPIO_I2C_B_SDA },
+	{ .name = "battery",
+	  .port = IT83XX_I2C_CH_A,
+	  .kbps = 100,
+	  .scl = GPIO_I2C_A_SCL,
+	  .sda = GPIO_I2C_A_SDA },
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+#define BC12_I2C_ADDR PI3USB9201_I2C_ADDR_3
+
+/* power signal list.  Must match order of enum power_signal. */
+const struct power_signal_info power_signal_list[] = {
+	{ GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" },
+	{ GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" },
+};
+BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
+
+/******************************************************************************/
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	{
+		.i2c_port = I2C_PORT_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+};
+
+/******************************************************************************/
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_EMBEDDED,
+		/* TCPC is embedded within EC so no i2c config needed */
+		.drv = &it8xxx2_tcpm_drv,
+		/* Alert is active-low, push-pull */
+		.flags = 0,
+	},
+};
+
+static void board_hpd_status(const struct usb_mux *me, mux_state_t mux_state,
+			     bool *ack_required)
+{
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
+	/*
+	 * svdm_dp_attention() did most of the work, we only need to notify
+	 * host here.
+	 */
+	host_set_single_event(EC_HOST_EVENT_USB_MUX);
+}
+
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+				.hpd_update = &board_hpd_status,
+			},
+	},
+};
+
+/* Charger config.  Start i2c address at 1, update during runtime */
+struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+};
+
+static int force_discharge;
+
+int board_set_active_charge_port(int charge_port)
+{
+	CPRINTS("New chg p%d", charge_port);
+
+	/* ignore all request when discharge mode is on */
+	if (force_discharge && charge_port != CHARGE_PORT_NONE)
+		return EC_SUCCESS;
+
+	switch (charge_port) {
+	case CHARGE_PORT_USB_C:
+		/* Don't charge from a source port */
+		if (board_vbus_source_enabled(charge_port))
+			return -1;
+		break;
+	default:
+		/*
+		 * To ensure the fuel gauge (max17055) is always powered
+		 * even when battery is disconnected, keep VBAT rail on but
+		 * set the charging current to minimum.
+		 */
+		charger_set_current(CHARGER_SOLO, 0);
+		break;
+	}
+
+	return EC_SUCCESS;
+}
+
+int board_discharge_on_ac(int enable)
+{
+	int ret, port;
+
+	if (enable) {
+		port = CHARGE_PORT_NONE;
+	} else {
+		/* restore the charge port state */
+		port = charge_manager_get_override();
+		if (port == OVERRIDE_OFF)
+			port = charge_manager_get_active_charge_port();
+	}
+
+	ret = charger_discharge_on_ac(enable);
+	if (ret)
+		return ret;
+
+	force_discharge = enable;
+	return board_set_active_charge_port(port);
+}
+
+#define VBUS_THRESHOLD_MV 4200
+int pd_snk_is_vbus_provided(int port)
+{
+	/* This board has only one port. */
+	if (!port)
+		return adc_read_channel(ADC_VBUS) > VBUS_THRESHOLD_MV ? 1 : 0;
+	else
+		return 0;
+}
+
+void bc12_interrupt(enum gpio_signal signal)
+{
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+
+static void board_init(void)
+{
+	/* If the reset cause is external, pulse PMIC force reset. */
+	if (system_get_reset_flags() == EC_RESET_FLAG_RESET_PIN) {
+		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 0);
+		msleep(100);
+		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 1);
+	}
+
+	/* Enable interrupts from BMI160 sensor. */
+	gpio_enable_interrupt(GPIO_ACCEL_INT_ODL);
+
+	/* Enable interrupt from PMIC. */
+	gpio_enable_interrupt(GPIO_PMIC_EC_RESETB);
+
+	/* Enable BC12 interrupt */
+	gpio_enable_interrupt(GPIO_BC12_EC_INT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+/* Vconn control for integrated ITE TCPC */
+void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
+{
+	/* Vconn control is only for port 0 */
+	if (port)
+		return;
+
+	if (cc_pin == USBPD_CC_PIN_1)
+		gpio_set_level(GPIO_EN_USB_C0_CC1_VCONN, !!enabled);
+	else
+		gpio_set_level(GPIO_EN_USB_C0_CC2_VCONN, !!enabled);
+}
+
+/* Called on AP S5 -> S3 transition */
+static void board_chipset_startup(void)
+{
+	gpio_set_level(GPIO_EN_USBA_5V, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S3 -> S5 transition */
+static void board_chipset_shutdown(void)
+{
+	gpio_set_level(GPIO_EN_USBA_5V, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
diff --git a/board/icarus/board.h b/board/icarus/board.h
new file mode 100644
index 0000000000..5fa752c518
--- /dev/null
+++ b/board/icarus/board.h
@@ -0,0 +1,139 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Configuration for Kukui */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#define VARIANT_KUKUI_JACUZZI
+#define VARIANT_KUKUI_BATTERY_SMART
+#define VARIANT_KUKUI_CHARGER_ISL9238
+#define VARIANT_KUKUI_EC_IT81202
+
+#include "baseboard.h"
+
+/* TODO: remove me once we fix IT83XX_ILM_BLOCK_SIZE out of space issue */
+#undef CONFIG_LTO
+
+#undef CONFIG_CHIPSET_POWER_SEQ_VERSION
+#define CONFIG_CHIPSET_POWER_SEQ_VERSION 1
+
+#define CONFIG_BATTERY_HW_PRESENT_CUSTOM
+
+#define CONFIG_CHARGER_PSYS
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 5
+
+#define CONFIG_CHARGER_RUNTIME_CONFIG
+
+#define CONFIG_BC12_DETECT_PI3USB9201
+
+#define CONFIG_EXTPOWER_GPIO
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
+#define CONFIG_EXTPOWER_DEBOUNCE_MS 200
+
+#undef CONFIG_I2C_NACK_RETRY_COUNT
+#define CONFIG_I2C_NACK_RETRY_COUNT 10
+#define CONFIG_SMBUS_PEC
+
+#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP
+#define CONFIG_USB_PD_DISCHARGE_GPIO
+#define CONFIG_USB_PD_TCPC_LOW_POWER
+
+#define CONFIG_USB_MUX_IT5205
+
+#undef CONFIG_ACCEL_FIFO
+#undef CONFIG_ACCEL_FIFO_SIZE
+#undef CONFIG_ACCEL_FIFO_THRES
+
+/* I2C ports */
+#define I2C_PORT_BC12 IT83XX_I2C_CH_C
+#define I2C_PORT_TCPC0 IT83XX_I2C_CH_C
+#define I2C_PORT_USB_MUX IT83XX_I2C_CH_C
+#define I2C_PORT_CHARGER IT83XX_I2C_CH_A
+#define I2C_PORT_SENSORS IT83XX_I2C_CH_B
+#define I2C_PORT_ACCEL I2C_PORT_SENSORS
+#define I2C_PORT_BATTERY IT83XX_I2C_CH_A
+#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
+
+#define CONFIG_KEYBOARD_PROTOCOL_MKBP
+#define CONFIG_MKBP_EVENT
+#define CONFIG_MKBP_USE_GPIO
+
+#define CONFIG_LED_ONOFF_STATES
+
+#undef CONFIG_GMR_TABLET_MODE
+#undef GPIO_TABLET_MODE_L
+#undef CONFIG_TABLET_MODE
+#undef CONFIG_TABLET_MODE_SWITCH
+
+#ifndef __ASSEMBLER__
+
+enum adc_channel {
+	/* Real ADC channels begin here */
+	ADC_BOARD_ID = 0,
+	ADC_EC_SKU_ID,
+	ADC_VBUS,
+	ADC_CH_COUNT
+};
+
+/* power signal definitions */
+enum power_signal {
+	AP_IN_S3_L,
+	PMIC_PWR_GOOD,
+
+	/* Number of signals */
+	POWER_SIGNAL_COUNT,
+};
+
+/* Motion sensors */
+enum sensor_id {
+	LID_ACCEL = 0,
+	BASE_ACCEL,
+	BASE_GYRO,
+	SENSOR_COUNT,
+};
+
+enum charge_port {
+	CHARGE_PORT_USB_C,
+};
+
+enum battery_type {
+	BATTERY_LGC_AP18C8K,
+	BATTERY_MURATA_AP18C4K,
+	BATTERY_PANASONIC_AP19B5K_KT00305011,
+	BATTERY_LGC_AP19B8K,
+	BATTERY_COSMX_AP20CBL,
+	BATTERY_SMP_AP18C7K,
+	BATTERY_TYPE_COUNT,
+};
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+/* support factory keyboard test */
+#define CONFIG_KEYBOARD_FACTORY_TEST
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+
+#ifdef SECTION_IS_RO
+/* Interrupt handler for AP jump to BL */
+void emmc_ap_jump_to_bl(enum gpio_signal signal);
+#endif
+
+void bc12_interrupt(enum gpio_signal signal);
+void board_reset_pd_mcu(void);
+int board_get_version(void);
+
+/* returns the i2c port number of charger/battery */
+int board_get_charger_i2c(void);
+int board_get_battery_i2c(void);
+
+/* Motion sensor interrupt */
+void motion_interrupt(enum gpio_signal signal);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/icarus/build.mk b/board/icarus/build.mk
new file mode 100644
index 0000000000..a1ca27116e
--- /dev/null
+++ b/board/icarus/build.mk
@@ -0,0 +1,15 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+#
+# IC is ITE IT81202
+CHIP:=it83xx
+CHIP_FAMILY:=it8xxx2
+CHIP_VARIANT:=it81202bx_1024
+BASEBOARD:=kukui
+
+board-y=battery.o board.o led.o
diff --git a/board/icarus/ec.tasklist b/board/icarus/ec.tasklist
new file mode 100644
index 0000000000..9b6e29ea07
--- /dev/null
+++ b/board/icarus/ec.tasklist
@@ -0,0 +1,17 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 1024) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, 1280)
diff --git a/board/icarus/gpio.inc b/board/icarus/gpio.inc
new file mode 100644
index 0000000000..1ec4c9cc41
--- /dev/null
+++ b/board/icarus/gpio.inc
@@ -0,0 +1,148 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first.
+ */
+
+/* Interrupts */
+GPIO_INT(POWER_BUTTON_L,    PIN(E, 4), GPIO_INT_BOTH,
+         power_button_interrupt) /* EC_PWR_BTN_ODL */
+GPIO_INT(AP_IN_SLEEP_L,     PIN(F, 2), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V,
+         power_signal_interrupt)
+GPIO_INT(PMIC_EC_RESETB,    PIN(F, 3), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V,
+         power_signal_interrupt)
+GPIO_INT(WARM_RESET_REQ,    PIN(D, 3), GPIO_INT_RISING | GPIO_PULL_DOWN | GPIO_SEL_1P8V,
+         chipset_reset_request_interrupt)
+GPIO_INT_RO(BOOTBLOCK_EN_L, PIN(J, 1), GPIO_INT_RISING | GPIO_SEL_1P8V,
+         emmc_ap_jump_to_bl)
+GPIO_INT(SPI0_CS,           PIN(M, 5), GPIO_INT_FALLING,
+         spi_event)        /* SPI slave Chip Select -- AP_SPI_EC_CS_L */
+GPIO_INT(LID_OPEN,          PIN(E, 2), GPIO_INT_BOTH,
+         lid_interrupt)
+GPIO_INT(AC_PRESENT,        PIN(E, 5), GPIO_INT_BOTH,
+         extpower_interrupt) /* ACOK_OD */
+GPIO_INT(BC12_EC_INT_ODL,   PIN(J, 6), GPIO_INT_FALLING,
+         bc12_interrupt)
+GPIO_INT(AP_EC_WATCHDOG_L,  PIN(C, 7), GPIO_INT_FALLING | GPIO_SEL_1P8V,
+         chipset_watchdog_interrupt)
+GPIO_INT(UART1_RX,          PIN(B, 0), GPIO_INT_FALLING,
+         uart_deepsleep_interrupt) /* UART_DEBUG_TX_EC_RX */
+/* Unimplemented interrupts */
+GPIO(ACCEL_INT_ODL,         PIN(J, 2), GPIO_INPUT)
+GPIO(TABLET_MODE_L,         PIN(J, 7), GPIO_INPUT)
+GPIO(VOLUME_DOWN_L,         PIN(D, 5), GPIO_INPUT)
+GPIO(VOLUME_UP_L,           PIN(D, 6), GPIO_INPUT)
+GPIO(ALS_RGB_INT_ODL,       PIN(F, 0), GPIO_INPUT)
+GPIO(LID_ACCEL_INT_ODL,     PIN(J, 3), GPIO_INPUT | GPIO_SEL_1P8V)
+
+/* Reset pins */
+GPIO(AP_SYS_RST_L,          PIN(B, 6), GPIO_OUT_LOW)
+/* 1.8V PP or 1.8V OD output with external 10K PU  */
+GPIO(PMIC_WATCHDOG_L,       PIN(H, 0), GPIO_ODR_LOW | GPIO_SEL_1P8V)
+/* OD output with 5VT (there is 5V internal PU on PWRKEY of MT6358) */
+GPIO(PMIC_EN_ODL,           PIN(E, 1), GPIO_ODR_HIGH)
+
+/*
+ * I2C pins should be configured as inputs until I2C module is
+ * initialized. This will avoid driving the lines unintentionally.
+ */
+/* EC programming */
+GPIO(I2C_E_SCL,              PIN(A, 4), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(I2C_E_SDA,              PIN(A, 5), GPIO_INPUT | GPIO_SEL_1P8V)
+/* battery and charger */
+GPIO(I2C_A_SCL,              PIN(B, 3), GPIO_INPUT)
+GPIO(I2C_A_SDA,              PIN(B, 4), GPIO_INPUT)
+/* sensor */
+GPIO(I2C_B_SCL,              PIN(C, 1), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(I2C_B_SDA,              PIN(C, 2), GPIO_INPUT | GPIO_SEL_1P8V)
+/* typec */
+GPIO(I2C_C_SCL,              PIN(F, 6), GPIO_INPUT)
+GPIO(I2C_C_SDA,              PIN(F, 7), GPIO_INPUT)
+
+/* Other input pins */
+/* TODO(WP_L): change to interrupt pin ? */
+GPIO(WP_L,                 PIN(I, 4), GPIO_INPUT | GPIO_SEL_1P8V) /* EC_FLASH_WP_ODL */
+GPIO(CCD_MODE_ODL,         PIN(C, 4), GPIO_INPUT)
+
+/* Other output pins */
+GPIO(EC_BATT_PRES_ODL,     PIN(C, 0), GPIO_INPUT)
+GPIO(EC_BL_EN_OD,          PIN(B, 5), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(EN_USBA_5V,           PIN(B, 7), GPIO_OUT_LOW)
+GPIO(ENTERING_RW,          PIN(C, 5), GPIO_ODR_HIGH)  /* EC_ENTERING_RW_ODL */
+GPIO(EC_INT_L,             PIN(E, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V)  /* EC_AP_INT_ODL */
+GPIO(EC_BOARD_ID_EN_L,     PIN(H, 5), GPIO_ODR_HIGH)  /* EC_BOARD_ID_EN_ODL */
+GPIO(USB_C0_HPD_OD,        PIN(J, 0), GPIO_ODR_LOW)
+GPIO(USB_C0_DISCHARGE,     PIN(H, 3), GPIO_OUT_LOW)
+GPIO(EN_USB_C0_CC1_VCONN,  PIN(H, 1), GPIO_OUT_LOW)
+GPIO(EN_USB_C0_CC2_VCONN,  PIN(H, 2), GPIO_OUT_LOW)
+
+/* LEDs */
+GPIO(LED_BLUE,             PIN(A, 2), GPIO_OUT_HIGH)
+GPIO(LED_GREEN,            PIN(A, 1), GPIO_OUT_HIGH)
+GPIO(LED_ORANGE,           PIN(A, 0), GPIO_OUT_HIGH)
+GPIO(EN_PP1800_S5_L,       PIN(D, 0), GPIO_OUT_LOW)
+
+/* Unimplemented Pins  */
+GPIO(PG_PP5000_A_OD,       PIN(A, 6), GPIO_INPUT)
+GPIO(USB_A0_OC_ODL,        PIN(A, 7), GPIO_INPUT)
+GPIO(EC_PROCHOT_ODL,       PIN(C, 3), GPIO_INPUT)
+GPIO(PMIC_FORCE_RESET_ODL, PIN(C, 6), GPIO_INPUT)
+GPIO(USB_C0_PD_INT_ODL,    PIN(D, 1), GPIO_INPUT) /* no used on this board */
+GPIO(EN_PP5000A_USM,       PIN(D, 7), GPIO_INPUT)
+GPIO(EN_USBC_CHARGE_L,     PIN(F, 1), GPIO_INPUT)
+GPIO(EN_PP5000_USBC,       PIN(H, 4), GPIO_INPUT)
+GPIO(PP1800_H1_PG,         PIN(H, 6), GPIO_INPUT)
+
+/* NC pins, ensure they aren't in floating state. */
+GPIO(NC_GPA3,              PIN(A, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(NC_GPB2,              PIN(B, 2), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(NC_GPD2,              PIN(D, 2), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(NC_GPD4,              PIN(D, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(NC_GPE0,              PIN(E, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(NC_GPE3,              PIN(E, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(NC_GPE7,              PIN(E, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+/*
+ * ADC pins don't have internal pull-down capability,
+ * so we set them as output low.
+ */
+GPIO(NC_GPI5,              PIN(I, 5), GPIO_OUT_LOW)
+GPIO(NC_GPI7,              PIN(I, 7), GPIO_OUT_LOW)
+
+GPIO(NC_GPJ4,              PIN(J, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(NC_GPJ5,              PIN(J, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+/*
+ * GPG3,4,5,7 don't have internal pull-down capability,
+ * so we set them as output low.
+ */
+GPIO(NC_GPG0,              PIN(G, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+/* Don't touch GPG1 and GPG2 */
+GPIO(NC_GPG3,              PIN(G, 3), GPIO_OUT_LOW)
+GPIO(EC_SPI_FLASH_MOSI,    PIN(G, 4), GPIO_OUT_LOW)
+GPIO(EC_SPI_FLASH_MISO,    PIN(G, 5), GPIO_OUT_LOW)
+GPIO(EC_SPI_FLASH_CLK,     PIN(G, 6), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(EC_SPI_FLASH_CS_L,    PIN(G, 7), GPIO_OUT_LOW)
+
+/* Alternate functions GPIO definitions */
+/* Keyboard */
+ALTERNATE(PIN_MASK(KSI,   0xFF), 0, MODULE_KEYBOARD_SCAN, 0) /* KSI0-7 */
+ALTERNATE(PIN_MASK(KSO_H, 0xFF), 0, MODULE_KEYBOARD_SCAN, 0) /* KSO8-15 */
+ALTERNATE(PIN_MASK(KSO_L, 0xFB), 0, MODULE_KEYBOARD_SCAN, 0) /* KSO0-1, 3-7 */
+GPIO(EC_KSO_02_INV, PIN(KSO_L, 2), GPIO_OUT_LOW)	     /* KSO2 inverted */
+/* I2C */
+ALTERNATE(PIN_MASK(B, 0x18), 1, MODULE_I2C, 0) /* I2C A */
+ALTERNATE(PIN_MASK(C, 0x06), 1, MODULE_I2C, GPIO_SEL_1P8V) /* I2C B */
+ALTERNATE(PIN_MASK(F, 0xC0), 1, MODULE_I2C, 0) /* I2C C */
+/* ADC */
+ALTERNATE(PIN_MASK(I, 0x4F), 0, MODULE_ADC, 0)  /* ADC 0,1,2,3,6 */
+/* UART */
+ALTERNATE(PIN_MASK(B, 0x03), 1, MODULE_UART, 0) /* EC to Servo */
+/* EMMC SPI SLAVE M2:CLK, M3:CMD, M6:DATA0 */
+ALTERNATE(PIN_MASK(M, 0x4C), 0, MODULE_SPI_FLASH,  0)
+/* SPI */
+ALTERNATE(PIN_MASK(M, 0x33), 0, MODULE_SPI, 0) /* SPI for communication */
diff --git a/board/icarus/led.c b/board/icarus/led.c
new file mode 100644
index 0000000000..bbbad7ceb8
--- /dev/null
+++ b/board/icarus/led.c
@@ -0,0 +1,85 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power and battery LED control for Jacuzzi
+ */
+#include "common.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+#define LED_ON_LVL 0
+#define LED_OFF_LVL 1
+__override const int led_charge_lvl_1 = 5;
+__override const int led_charge_lvl_2 = 95;
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_AMBER:
+		gpio_set_level(GPIO_LED_ORANGE, LED_ON_LVL);
+		gpio_set_level(GPIO_LED_BLUE, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_GREEN, LED_OFF_LVL);
+		break;
+	case EC_LED_COLOR_BLUE:
+		gpio_set_level(GPIO_LED_BLUE, LED_ON_LVL);
+		gpio_set_level(GPIO_LED_ORANGE, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_GREEN, LED_OFF_LVL);
+		break;
+	case EC_LED_COLOR_GREEN:
+		gpio_set_level(GPIO_LED_GREEN, LED_ON_LVL);
+		gpio_set_level(GPIO_LED_BLUE, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_ORANGE, LED_OFF_LVL);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		gpio_set_level(GPIO_LED_GREEN, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_BLUE, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_ORANGE, LED_OFF_LVL);
+		break;
+	}
+}
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		brightness_range[EC_LED_COLOR_BLUE] = 1;
+		brightness_range[EC_LED_COLOR_GREEN] = 1;
+	}
+}
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(EC_LED_COLOR_AMBER);
+		else if (brightness[EC_LED_COLOR_BLUE] != 0)
+			led_set_color_battery(EC_LED_COLOR_BLUE);
+		else if (brightness[EC_LED_COLOR_GREEN] != 0)
+			led_set_color_battery(EC_LED_COLOR_GREEN);
+		else
+			led_set_color_battery(LED_OFF);
+	}
+	return EC_SUCCESS;
+}
diff --git a/board/icarus/vif_override.xml b/board/icarus/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/icarus/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/it83xx_evb/board.c b/board/it83xx_evb/board.c
index a18b8b3b70..37ee2f48ed 100644
--- a/board/it83xx_evb/board.c
+++ b/board/it83xx_evb/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/it83xx_evb/board.h b/board/it83xx_evb/board.h
index 754474174c..d3eec7f09e 100644
--- a/board/it83xx_evb/board.h
+++ b/board/it83xx_evb/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/it83xx_evb/build.mk b/board/it83xx_evb/build.mk
index e4c8c01b89..9a78775633 100644
--- a/board/it83xx_evb/build.mk
+++ b/board/it83xx_evb/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
+# Copyright 2013 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/it83xx_evb/ec.tasklist b/board/it83xx_evb/ec.tasklist
index 3ca78d55db..e5d2d246df 100644
--- a/board/it83xx_evb/ec.tasklist
+++ b/board/it83xx_evb/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/it83xx_evb/gpio.inc b/board/it83xx_evb/gpio.inc
index 9f96b5f325..e3014814d7 100644
--- a/board/it83xx_evb/gpio.inc
+++ b/board/it83xx_evb/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
+ * Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,7 +9,7 @@
  * Note: Those with interrupt handlers must be declared first. */
 
 GPIO_INT(POWER_BUTTON_L, PIN(E, 4), GPIO_INT_BOTH | GPIO_PULL_UP,   power_button_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
 GPIO_INT(PCH_PLTRST_L,   PIN(E, 3), GPIO_INT_BOTH | GPIO_PULL_UP,   lpcrst_interrupt)
 #endif
 GPIO_INT(LID_OPEN,       PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_DOWN, lid_interrupt)
@@ -56,10 +56,10 @@ ALTERNATE(PIN_MASK(B, 0x03), 1, MODULE_UART, GPIO_PULL_UP) /* UART1 */
 #ifdef CONFIG_UART_HOST
 ALTERNATE(PIN_MASK(H, 0x06), 1, MODULE_UART, 0)            /* UART2 */
 #endif
-ALTERNATE(PIN_MASK(A, 0x40), 3, MODULE_SPI_MASTER, 0)      /* SSCK of SPI */
-ALTERNATE(PIN_MASK(C, 0x28), 3, MODULE_SPI_MASTER, 0)      /* SMOSI/SMISO of SPI */
-ALTERNATE(PIN_MASK(G, 0x01), 3, MODULE_SPI_MASTER, 0)      /* SSCE1# of SPI */
-ALTERNATE(PIN_MASK(G, 0x04), 3, MODULE_SPI_MASTER, 0)      /* SSCE0# of SPI */
+ALTERNATE(PIN_MASK(A, 0x40), 3, MODULE_SPI_CONTROLLER, 0)  /* SSCK of SPI */
+ALTERNATE(PIN_MASK(C, 0x28), 3, MODULE_SPI_CONTROLLER, 0)  /* SMOSI/SMISO of SPI */
+ALTERNATE(PIN_MASK(G, 0x01), 3, MODULE_SPI_CONTROLLER, 0)  /* SSCE1# of SPI */
+ALTERNATE(PIN_MASK(G, 0x04), 3, MODULE_SPI_CONTROLLER, 0)  /* SSCE0# of SPI */
 ALTERNATE(PIN_MASK(A, 0x80), 1, MODULE_PWM, 0)             /* PWM7 for FAN1 */
 ALTERNATE(PIN_MASK(D, 0x40), 3, MODULE_PWM, 0)             /* TACH0A for FAN1 */
 ALTERNATE(PIN_MASK(B, 0x18), 1, MODULE_I2C, 0)             /* I2C A SCL/SDA */
diff --git a/board/it8xxx2_evb/board.c b/board/it8xxx2_evb/board.c
index 0daa3d48cd..404a575e42 100644
--- a/board/it8xxx2_evb/board.c
+++ b/board/it8xxx2_evb/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/it8xxx2_evb/board.h b/board/it8xxx2_evb/board.h
index 1369e43496..766f0fab4f 100644
--- a/board/it8xxx2_evb/board.h
+++ b/board/it8xxx2_evb/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/it8xxx2_evb/build.mk b/board/it8xxx2_evb/build.mk
index b54a2fcbb6..6fefa1fc6c 100644
--- a/board/it8xxx2_evb/build.mk
+++ b/board/it8xxx2_evb/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/it8xxx2_evb/ec.tasklist b/board/it8xxx2_evb/ec.tasklist
index ff184489e3..a25dab19eb 100644
--- a/board/it8xxx2_evb/ec.tasklist
+++ b/board/it8xxx2_evb/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/it8xxx2_evb/gpio.inc b/board/it8xxx2_evb/gpio.inc
index 008034cfb3..32d9de4a05 100644
--- a/board/it8xxx2_evb/gpio.inc
+++ b/board/it8xxx2_evb/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,7 +9,7 @@
  * Note: Those with interrupt handlers must be declared first. */
 
 GPIO_INT(POWER_BUTTON_L, PIN(E, 4), GPIO_INT_BOTH | GPIO_PULL_UP,   power_button_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
 GPIO_INT(PCH_PLTRST_L,   PIN(E, 3), GPIO_INT_BOTH | GPIO_PULL_UP,   lpcrst_interrupt)
 #endif
 GPIO_INT(LID_OPEN,       PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP,   lid_interrupt)
@@ -56,10 +56,10 @@ ALTERNATE(PIN_MASK(B, 0x03), 1, MODULE_UART, GPIO_PULL_UP) /* UART1 */
 #ifdef CONFIG_UART_HOST
 ALTERNATE(PIN_MASK(H, 0x06), 1, MODULE_UART, 0)            /* UART2 */
 #endif
-ALTERNATE(PIN_MASK(A, 0x40), 3, MODULE_SPI_MASTER, 0)      /* SSCK of SPI */
-ALTERNATE(PIN_MASK(C, 0x28), 3, MODULE_SPI_MASTER, 0)      /* SMOSI/SMISO of SPI */
-ALTERNATE(PIN_MASK(G, 0x01), 3, MODULE_SPI_MASTER, 0)      /* SSCE1# of SPI */
-ALTERNATE(PIN_MASK(G, 0x04), 3, MODULE_SPI_MASTER, 0)      /* SSCE0# of SPI */
+ALTERNATE(PIN_MASK(A, 0x40), 3, MODULE_SPI_CONTROLLER, 0)  /* SSCK of SPI */
+ALTERNATE(PIN_MASK(C, 0x28), 3, MODULE_SPI_CONTROLLER, 0)  /* SMOSI/SMISO of SPI */
+ALTERNATE(PIN_MASK(G, 0x01), 3, MODULE_SPI_CONTROLLER, 0)  /* SSCE1# of SPI */
+ALTERNATE(PIN_MASK(G, 0x04), 3, MODULE_SPI_CONTROLLER, 0)  /* SSCE0# of SPI */
 ALTERNATE(PIN_MASK(A, 0x80), 1, MODULE_PWM, 0)             /* PWM7 for FAN1 */
 ALTERNATE(PIN_MASK(D, 0x40), 3, MODULE_PWM, 0)             /* TACH0A for FAN1 */
 ALTERNATE(PIN_MASK(B, 0x18), 1, MODULE_I2C, 0)             /* I2C A SCL/SDA */
diff --git a/board/it8xxx2_pdevb/board.c b/board/it8xxx2_pdevb/board.c
index 22f204258b..2bcc58a58c 100644
--- a/board/it8xxx2_pdevb/board.c
+++ b/board/it8xxx2_pdevb/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,18 +7,19 @@
 #include "adc_chip.h"
 #include "battery.h"
 #include "console.h"
+#include "gpio.h"
 #include "it83xx_pd.h"
 #include "pwm.h"
 #include "pwm_chip.h"
 #include "timer.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
-#define USB_PD_PORT_ITE_0   0
-#define USB_PD_PORT_ITE_1   1
-#define USB_PD_PORT_ITE_2   2
-#define RESISTIVE_DIVIDER   11
+#define USB_PD_PORT_ITE_0 0
+#define USB_PD_PORT_ITE_1 1
+#define USB_PD_PORT_ITE_2 2
+#define RESISTIVE_DIVIDER 11
 
 int board_get_battery_soc(void)
 {
@@ -36,14 +37,14 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_ITE_0] = {
 		.bus_type = EC_BUS_TYPE_EMBEDDED,
 		/* TCPC is embedded within EC so needn't i2c config */
-		.drv = &it83xx_tcpm_drv,
+		.drv = &it8xxx2_tcpm_drv,
 		/* Alert is active-low, push-pull */
 		.flags = 0,
 	},
 	[USB_PD_PORT_ITE_1] = {
 		.bus_type = EC_BUS_TYPE_EMBEDDED,
 		/* TCPC is embedded within EC so needn't i2c config */
-		.drv = &it83xx_tcpm_drv,
+		.drv = &it8xxx2_tcpm_drv,
 		/* Alert is active-low, push-pull */
 		.flags = 0,
 	},
@@ -82,7 +83,7 @@ void board_pd_vbus_ctrl(int port, int enabled)
 		gpio_set_level(GPIO_USBPD_PORTA_VBUS_OUTPUT, enabled);
 		if (!enabled) {
 			gpio_set_level(GPIO_USBPD_PORTA_VBUS_DROP, 1);
-			udelay(10*MSEC); /* 10ms is a try and error value */
+			udelay(10 * MSEC); /* 10ms is a try and error value */
 		}
 		gpio_set_level(GPIO_USBPD_PORTA_VBUS_DROP, 0);
 	} else if (port == USBPD_PORT_B) {
@@ -90,7 +91,7 @@ void board_pd_vbus_ctrl(int port, int enabled)
 		gpio_set_level(GPIO_USBPD_PORTB_VBUS_OUTPUT, enabled);
 		if (!enabled) {
 			gpio_set_level(GPIO_USBPD_PORTB_VBUS_DROP, 1);
-			udelay(10*MSEC); /* 10ms is a try and error value */
+			udelay(10 * MSEC); /* 10ms is a try and error value */
 		}
 		gpio_set_level(GPIO_USBPD_PORTB_VBUS_DROP, 0);
 	} else if (port == USBPD_PORT_C) {
@@ -98,13 +99,13 @@ void board_pd_vbus_ctrl(int port, int enabled)
 		gpio_set_level(GPIO_USBPD_PORTC_VBUS_OUTPUT, enabled);
 		if (!enabled) {
 			gpio_set_level(GPIO_USBPD_PORTC_VBUS_DROP, 1);
-			udelay(10*MSEC); /* 10ms is a try and error value */
+			udelay(10 * MSEC); /* 10ms is a try and error value */
 		}
 		gpio_set_level(GPIO_USBPD_PORTC_VBUS_DROP, 0);
 	}
 
 	if (enabled)
-		udelay(10*MSEC); /* 10ms is a try and error value */
+		udelay(10 * MSEC); /* 10ms is a try and error value */
 }
 
 void pd_set_input_current_limit(int port, uint32_t max_ma,
@@ -119,8 +120,7 @@ void pd_set_input_current_limit(int port, uint32_t max_ma,
  * so use the same frequency and prescaler register setting is required if
  * number of pwm channel greater than three.
  */
-const struct pwm_t pwm_channels[] = {
-};
+const struct pwm_t pwm_channels[] = {};
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
diff --git a/board/it8xxx2_pdevb/board.h b/board/it8xxx2_pdevb/board.h
index 7c40a1ffc7..e617a015bd 100644
--- a/board/it8xxx2_pdevb/board.h
+++ b/board/it8xxx2_pdevb/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,17 +22,16 @@
 #undef CONFIG_FANS
 #undef CONFIG_IT83XX_ENABLE_MOUSE_DEVICE
 #undef CONFIG_IT83XX_SMCLK2_ON_GPC7
-#undef CONFIG_KEYBOARD_BOARD_CONFIG
 #undef CONFIG_KEYBOARD_PROTOCOL_8042
 #undef CONFIG_PECI
 #undef CONFIG_PECI_COMMON
 #undef CONFIG_PECI_TJMAX
 #undef CONFIG_POWER_BUTTON
 #undef CONFIG_PWM
-#undef CONFIG_SPI_MASTER
+#undef CONFIG_SPI_CONTROLLER
 #undef CONFIG_SPI_FLASH_PORT
 #undef CONFIG_UART_HOST
-#undef CONFIG_HOSTCMD_LPC
+#undef CONFIG_HOST_INTERFACE_LPC
 #undef CONFIG_CMD_MMAPINFO
 #undef CONFIG_SWITCH
 
@@ -41,13 +40,14 @@
 #define CONFIG_USB_PD_ALT_MODE_DFP
 #define CONFIG_USB_PD_CHECK_MAX_REQUEST_ALLOWED
 #define CONFIG_USB_PD_CUSTOM_PDO
+#define CONFIG_USB_PD_3A_PORTS 0
 #define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_PORT_MAX_COUNT    2
-#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT   2
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 2
 #define CONFIG_USB_PD_TCPMV2
 #define CONFIG_USB_DRP_ACC_TRYSRC
 #define CONFIG_USB_PD_REV30
-#define CONFIG_USB_PID 0x1234            /* Invalid PID for development board */
+#define CONFIG_USB_PID 0x1234 /* Invalid PID for development board */
 #define CONFIG_USB_PD_DEBUG_LEVEL 2
 #define CONFIG_USB_PD_TCPM_ITE_ON_CHIP
 #define CONFIG_USB_PD_TRY_SRC
@@ -82,20 +82,19 @@ enum adc_channel {
 
 /* Define typical operating power and max power */
 #define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       60000
-#define PD_MAX_CURRENT_MA     3000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
 /* Try to negotiate to 20V since i2c noise problems should be fixed. */
-#define PD_MAX_VOLTAGE_MV     20000
+#define PD_MAX_VOLTAGE_MV 20000
 /* TODO: determine the following board specific type-C power constants */
 /*
  * delay to turn on the power supply max is ~16ms.
  * delay to turn off the power supply max is about ~180ms.
  */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* delay to turn on/off vconn */
-#define PD_VCONN_SWAP_DELAY 5000 /* us */
 
 void board_pd_vbus_ctrl(int port, int enabled);
 
diff --git a/board/it8xxx2_pdevb/build.mk b/board/it8xxx2_pdevb/build.mk
index b54a2fcbb6..6fefa1fc6c 100644
--- a/board/it8xxx2_pdevb/build.mk
+++ b/board/it8xxx2_pdevb/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/it8xxx2_pdevb/ec.tasklist b/board/it8xxx2_pdevb/ec.tasklist
index 41fc733526..ef1195fe7e 100644
--- a/board/it8xxx2_pdevb/ec.tasklist
+++ b/board/it8xxx2_pdevb/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/it8xxx2_pdevb/gpio.inc b/board/it8xxx2_pdevb/gpio.inc
index afc83a82c3..a03509507b 100644
--- a/board/it8xxx2_pdevb/gpio.inc
+++ b/board/it8xxx2_pdevb/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/it8xxx2_pdevb/vif_override.xml b/board/it8xxx2_pdevb/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/it8xxx2_pdevb/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/jacuzzi/battery.c b/board/jacuzzi/battery.c
index 443bf1e98a..1caeb7e3c5 100644
--- a/board/jacuzzi/battery.c
+++ b/board/jacuzzi/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -120,7 +120,8 @@ const struct board_batt_params board_battery_info[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
 
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_PANASONIC_AC16L5J_KT00205009;
+const enum battery_type DEFAULT_BATTERY_TYPE =
+	BATTERY_PANASONIC_AC16L5J_KT00205009;
 
 enum battery_present battery_hw_present(void)
 {
diff --git a/board/jacuzzi/board.c b/board/jacuzzi/board.c
index 8b6478c26a..c19c41d6c2 100644
--- a/board/jacuzzi/board.c
+++ b/board/jacuzzi/board.c
@@ -1,10 +1,9 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "backlight.h"
 #include "button.h"
 #include "charge_manager.h"
@@ -16,6 +15,8 @@
 #include "console.h"
 #include "driver/accel_kionix.h"
 #include "driver/accelgyro_bmi_common.h"
+#include "driver/accelgyro_icm426xx.h"
+#include "driver/accelgyro_icm_common.h"
 #include "driver/battery/max17055.h"
 #include "driver/bc12/pi3usb9201.h"
 #include "driver/charger/isl923x.h"
@@ -31,6 +32,7 @@
 #include "it8801.h"
 #include "keyboard_scan.h"
 #include "lid_switch.h"
+#include "panic.h"
 #include "power.h"
 #include "power_button.h"
 #include "registers.h"
@@ -38,45 +40,63 @@
 #include "system.h"
 #include "tablet_mode.h"
 #include "task.h"
-#include "tcpm.h"
+#include "tcpm/tcpm.h"
 #include "timer.h"
 #include "usb_charge.h"
 #include "usb_mux.h"
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
 	schedule_deferred_pd_interrupt(0 /* port */);
 }
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /******************************************************************************/
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] =  {"BOARD_ID",  3300, 4096, 0, STM32_AIN(10)},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)},
+	[ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(10) },
+	[ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /******************************************************************************/
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{"typec", 0, 400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
+	{ .name = "typec",
+	  .port = 0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
 #ifdef BOARD_JACUZZI
-	{"other", 1, 100, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
+	{ .name = "other",
+	  .port = 1,
+	  .kbps = 100,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
 #else /* Juniper */
-	{"other", 1, 400, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
+	{ .name = "other",
+	  .port = 1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
 #endif
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
 const struct i2c_port_t i2c_bitbang_ports[] = {
-	{"battery", 2, 100, GPIO_I2C3_SCL, GPIO_I2C3_SDA, .drv = &bitbang_drv},
+	{ .name = "battery",
+	  .port = 2,
+	  .kbps = 100,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA,
+	  .drv = &bitbang_drv },
 };
 const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
 
@@ -84,13 +104,13 @@ const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
 
 /* power signal list.  Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
+	{ GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" },
+	{ GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" },
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
 /* Keyboard scan setting */
-struct keyboard_scan_config keyscan_config = {
+__override struct keyboard_scan_config keyscan_config = {
 	/*
 	 * TODO(b/133200075): Tune this once we have the final performance
 	 * out of the driver and the i2c bus.
@@ -109,8 +129,8 @@ struct keyboard_scan_config keyscan_config = {
 
 struct ioexpander_config_t ioex_config[CONFIG_IO_EXPANDER_PORT_COUNT] = {
 	[0] = {
-		.i2c_host_port = I2C_PORT_IO_EXPANDER_IT8801,
-		.i2c_slave_addr = IT8801_I2C_ADDR,
+		.i2c_host_port = I2C_PORT_KB_DISCRETE,
+		.i2c_addr_flags = IT8801_I2C_ADDR1,
 		.drv = &it8801_ioexpander_drv,
 	},
 };
@@ -135,15 +155,18 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = I2C_PORT_TCPC0,
-			.addr_flags = FUSB302_I2C_SLAVE_ADDR_FLAGS,
+			.addr_flags = FUSB302_I2C_ADDR_FLAGS,
 		},
 		.drv = &fusb302_tcpm_drv,
 	},
 };
 
-static void board_hpd_status(const struct usb_mux *me,
-			     int hpd_lvl, int hpd_irq)
+static void board_hpd_status(const struct usb_mux *me, mux_state_t mux_state,
+			     bool *ack_required)
 {
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
 	/*
 	 * svdm_dp_attention() did most of the work, we only need to notify
 	 * host here.
@@ -151,13 +174,16 @@ static void board_hpd_status(const struct usb_mux *me,
 	host_set_single_event(EC_HOST_EVENT_USB_MUX);
 }
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+				.hpd_update = &board_hpd_status,
+			},
 	},
 };
 
@@ -203,7 +229,7 @@ int board_set_active_charge_port(int charge_port)
 		if (board_vbus_source_enabled(charge_port))
 			return -1;
 		break;
-	case CHARGE_PORT_NONE:
+	default:
 		/*
 		 * To ensure the fuel gauge (max17055) is always powered
 		 * even when battery is disconnected, keep VBAT rail on but
@@ -211,22 +237,11 @@ int board_set_active_charge_port(int charge_port)
 		 */
 		charger_set_current(CHARGER_SOLO, 0);
 		break;
-	default:
-		panic("Invalid charge port\n");
-		break;
 	}
 
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-			       CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
-
 int board_discharge_on_ac(int enable)
 {
 	int ret, port;
@@ -256,7 +271,7 @@ int pd_snk_is_vbus_provided(int port)
 
 void bc12_interrupt(enum gpio_signal signal)
 {
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
 }
 
 #ifndef VARIANT_KUKUI_NO_SENSORS
@@ -276,13 +291,12 @@ static void board_spi_enable(void)
 	STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
 
 	/* Reinitialize spi peripheral. */
-	spi_enable(CONFIG_SPI_ACCEL_PORT, 1);
+	spi_enable(&spi_devices[0], 1);
 
 	/* Pin mux spi peripheral toward the sensor. */
-	gpio_config_module(MODULE_SPI_MASTER, 1);
+	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
 }
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP,
-	     board_spi_enable,
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_spi_enable,
 	     MOTION_SENSE_HOOK_PRIO - 1);
 
 static void board_spi_disable(void)
@@ -290,19 +304,23 @@ static void board_spi_disable(void)
 	/* Set pins to a state calming the sensor down. */
 	gpio_set_flags(GPIO_EC_SENSOR_SPI_CK, GPIO_OUT_LOW);
 	gpio_set_level(GPIO_EC_SENSOR_SPI_CK, 0);
-	gpio_config_module(MODULE_SPI_MASTER, 0);
+	/* Pull SPI_NSS pin to low to prevent a leakage. */
+	gpio_set_flags(GPIO_EC_SENSOR_SPI_NSS, GPIO_OUT_LOW);
+	gpio_set_level(GPIO_EC_SENSOR_SPI_NSS, 0);
+	gpio_config_module(MODULE_SPI_CONTROLLER, 0);
 
 	/* Disable spi peripheral and clocks. */
-	spi_enable(CONFIG_SPI_ACCEL_PORT, 0);
+	spi_enable(&spi_devices[0], 0);
 	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
 }
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN,
-	     board_spi_disable,
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_spi_disable,
 	     MOTION_SENSE_HOOK_PRIO + 1);
 #endif /* !VARIANT_KUKUI_NO_SENSORS */
 
 static void board_init(void)
 {
+	int board_version;
+
 	/* If the reset cause is external, pulse PMIC force reset. */
 	if (system_get_reset_flags() == EC_RESET_FLAG_RESET_PIN) {
 		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 0);
@@ -326,6 +344,20 @@ static void board_init(void)
 
 	/* Enable BC12 interrupt */
 	gpio_enable_interrupt(GPIO_BC12_EC_INT_ODL);
+
+	board_version = board_get_version();
+	if (board_version == 8 || board_version == 9) {
+		/* Disable motion sense. */
+#ifndef VARIANT_KUKUI_NO_SENSORS
+		motion_sensor_count = 0;
+		gpio_disable_interrupt(GPIO_ACCEL_INT_ODL);
+		gpio_set_flags(GPIO_ACCEL_INT_ODL, GPIO_INPUT | GPIO_PULL_DOWN);
+#endif /* !VARIANT_KUKUI_NO_SENSORS */
+		/* Disable tablet mode. */
+		tablet_set_mode(0, TABLET_TRIGGER_LID);
+		gmr_tablet_switch_disable();
+		gpio_set_flags(GPIO_TABLET_MODE_L, GPIO_INPUT | GPIO_PULL_UP);
+	}
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
@@ -336,15 +368,24 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Rotation matrixes */
-static const mat33_fp_t base_standard_ref = {
-	{FLOAT_TO_FP(1), 0, 0},
-	{0, FLOAT_TO_FP(1), 0},
-	{0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t base_bmi160_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					    { 0, FLOAT_TO_FP(1), 0 },
+					    { 0, 0, FLOAT_TO_FP(1) } };
+
+static const mat33_fp_t base_icm426xx_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+					      { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
 
 /* sensor private data */
 static struct kionix_accel_data g_kx022_data;
 static struct bmi_drv_data_t g_bmi160_data;
+static struct icm_drv_data_t g_icm426xx_data;
+
+enum base_accelgyro_type {
+	BASE_GYRO_NONE = 0,
+	BASE_GYRO_BMI160 = 1,
+	BASE_GYRO_ICM426XX = 2,
+};
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
@@ -359,7 +400,7 @@ struct motion_sensor_t motion_sensors[] = {
 	 .port = I2C_PORT_SENSORS,
 	 .i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
 	 .rot_standard_ref = NULL, /* Identity matrix. */
-	 .default_range = 2, /* g, to meet CDD 7.3.1/C-1-4 reqs */
+	 .default_range = 2, /* g, enough to calculate lid angle. */
 	 .config = {
 		/* EC use accel for angle detection */
 		[SENSOR_CONFIG_EC_S0] = {
@@ -386,9 +427,9 @@ struct motion_sensor_t motion_sensors[] = {
 	 .mutex = &g_base_mutex,
 	 .drv_data = &g_bmi160_data,
 	 .port = CONFIG_SPI_ACCEL_PORT,
-	 .i2c_spi_addr_flags = SLAVE_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
-	 .rot_standard_ref = &base_standard_ref,
-	 .default_range = 2,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
+	 .i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
+	 .rot_standard_ref = &base_bmi160_ref,
+	 .default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
 	 .min_frequency = BMI_ACCEL_MIN_FREQ,
 	 .max_frequency = BMI_ACCEL_MAX_FREQ,
 	 .config = {
@@ -414,15 +455,104 @@ struct motion_sensor_t motion_sensors[] = {
 	 .mutex = &g_base_mutex,
 	 .drv_data = &g_bmi160_data,
 	 .port = CONFIG_SPI_ACCEL_PORT,
-	 .i2c_spi_addr_flags = SLAVE_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
+	 .i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
 	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &base_standard_ref,
+	 .rot_standard_ref = &base_bmi160_ref,
 	 .min_frequency = BMI_GYRO_MIN_FREQ,
 	 .max_frequency = BMI_GYRO_MAX_FREQ,
 	},
 };
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+struct motion_sensor_t icm426xx_base_accel = {
+	.name = "Base Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = CONFIG_SPI_ACCEL_PORT,
+	.i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
+	.default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
+	.rot_standard_ref = &base_icm426xx_ref,
+	.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
+	.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	},
+};
+
+struct motion_sensor_t icm426xx_base_gyro = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = CONFIG_SPI_ACCEL_PORT,
+	.i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &base_icm426xx_ref,
+	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
+	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
+};
 
+static int base_accelgyro_config;
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	switch (base_accelgyro_config) {
+	case BASE_GYRO_ICM426XX:
+		icm426xx_interrupt(signal);
+		break;
+	case BASE_GYRO_BMI160:
+	default:
+		bmi160_interrupt(signal);
+		break;
+	}
+}
+
+static void board_detect_motionsensor(void)
+{
+	int val;
+	/* Check base accelgyro chip */
+	if (base_accelgyro_config != BASE_GYRO_NONE)
+		return;
+
+	icm_read8(&icm426xx_base_accel, ICM426XX_REG_WHO_AM_I, &val);
+	if (val == ICM426XX_CHIP_ICM40608) {
+		motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
+		motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
+	}
+	base_accelgyro_config = (val == ICM426XX_CHIP_ICM40608) ?
+					BASE_GYRO_ICM426XX :
+					BASE_GYRO_BMI160;
+	CPRINTS("Base Accelgyro: %s",
+		(val == ICM426XX_CHIP_ICM40608) ? "ICM40608" : "BMI160");
+}
+DECLARE_HOOK(HOOK_INIT, board_detect_motionsensor, HOOK_PRIO_DEFAULT);
+
+int board_sensor_at_360(void)
+{
+	int board_version;
+
+	board_version = board_get_version();
+	if (board_version == 8 || board_version == 9)
+		return 0;
+	else
+		return !gpio_get_level(GPIO_TABLET_MODE_L);
+}
 #endif /* !VARIANT_KUKUI_NO_SENSORS */
 
 /* Called on AP S5 -> S3 transition */
diff --git a/board/jacuzzi/board.h b/board/jacuzzi/board.h
index 0303d87433..3d50b41297 100644
--- a/board/jacuzzi/board.h
+++ b/board/jacuzzi/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,6 +11,12 @@
 #define VARIANT_KUKUI_JACUZZI
 #define VARIANT_KUKUI_BATTERY_SMART
 #define VARIANT_KUKUI_CHARGER_ISL9238
+#define VARIANT_KUKUI_EC_STM32F098
+#undef CONFIG_CMD_MFALLOW
+
+/* Free up flash space */
+#define CONFIG_DEBUG_ASSERT_BRIEF
+#define CONFIG_USB_PD_DEBUG_LEVEL 2
 
 #ifndef SECTION_IS_RW
 #define VARIANT_KUKUI_NO_SENSORS
@@ -28,6 +34,8 @@
 #define CONFIG_BATTERY_HW_PRESENT_CUSTOM
 
 #define CONFIG_CHARGER_PSYS
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 5
 
 #define CONFIG_CHARGER_RUNTIME_CONFIG
 
@@ -51,46 +59,54 @@
 
 /* Motion Sensors */
 #ifndef VARIANT_KUKUI_NO_SENSORS
-#define CONFIG_ACCEL_KX022	/* Lid accel */
+#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
+#define CONFIG_ACCEL_KX022 /* Lid accel */
 #define CONFIG_ACCELGYRO_BMI160 /* Base accel */
-#define CONFIG_ACCEL_INTERRUPTS
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+/* ICM426XX Base accel/gyro */
+#define CONFIG_ACCELGYRO_ICM426XX
+#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
 #define CONFIG_ALS
 #define CONFIG_CMD_ACCEL_INFO
 
 #define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_UPDATE
 #define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
 #define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
 
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
 
+#define CONFIG_GMR_TABLET_MODE_CUSTOM
+
 #endif /* VARIANT_KUKUI_NO_SENSORS */
 
 /* I2C ports */
-#define I2C_PORT_BC12               0
-#define I2C_PORT_TCPC0              0
-#define I2C_PORT_USB_MUX            0
-#define I2C_PORT_CHARGER            board_get_charger_i2c()
-#define I2C_PORT_SENSORS            1
-#define I2C_PORT_IO_EXPANDER_IT8801 1
-#define I2C_PORT_VIRTUAL_BATTERY    I2C_PORT_BATTERY
+#define I2C_PORT_BC12 0
+#define I2C_PORT_TCPC0 0
+#define I2C_PORT_USB_MUX 0
+#define I2C_PORT_CHARGER board_get_charger_i2c()
+#define I2C_PORT_SENSORS 1
+#define I2C_PORT_KB_DISCRETE 1
+#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
 #ifdef BOARD_JACUZZI
-#define I2C_PORT_BATTERY            1
+#define I2C_PORT_BATTERY 1
 #else /* Juniper */
-#define I2C_PORT_BATTERY            2
+#define I2C_PORT_BATTERY 2
 #endif
 
+/* IT8801 I2C address */
+#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1
+
 /* Enable Accel over SPI */
-#define CONFIG_SPI_ACCEL_PORT    0  /* The first SPI master port (SPI2) */
+#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */
 
 #define CONFIG_KEYBOARD_PROTOCOL_MKBP
 #define CONFIG_MKBP_EVENT
 #define CONFIG_MKBP_USE_GPIO
-/* Define the MKBP events which are allowed to wakeup AP in S3. */
-#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \
-		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
 
 #define CONFIG_LED_ONOFF_STATES
 
@@ -143,12 +159,14 @@ void emmc_cmd_interrupt(enum gpio_signal signal);
 void bc12_interrupt(enum gpio_signal signal);
 void board_reset_pd_mcu(void);
 int board_get_version(void);
-int board_is_sourcing_vbus(int port);
 
 /* returns the i2c port number of charger/battery */
 int board_get_charger_i2c(void);
 int board_get_battery_i2c(void);
 
+/* Motion sensor interrupt */
+void motion_interrupt(enum gpio_signal signal);
+
 #endif /* !__ASSEMBLER__ */
 
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/jacuzzi/build.mk b/board/jacuzzi/build.mk
index e449fce9fc..80c34a4e46 100644
--- a/board/jacuzzi/build.mk
+++ b/board/jacuzzi/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/jacuzzi/ec.tasklist b/board/jacuzzi/ec.tasklist
index b695d05a71..dd3b853c27 100644
--- a/board/jacuzzi/ec.tasklist
+++ b/board/jacuzzi/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/jacuzzi/gpio.inc b/board/jacuzzi/gpio.inc
index b0f5f25645..b534ad2ea1 100644
--- a/board/jacuzzi/gpio.inc
+++ b/board/jacuzzi/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,7 +22,7 @@ GPIO_INT(PMIC_EC_RESETB,    PIN(B, 7),  GPIO_INT_BOTH | GPIO_PULL_DOWN,
 GPIO_INT(WARM_RESET_REQ,    PIN(A, 3),  GPIO_INT_RISING | GPIO_PULL_DOWN,
          chipset_reset_request_interrupt)
 GPIO_INT_RW(ACCEL_INT_ODL,  PIN(A, 4), GPIO_INT_FALLING | GPIO_SEL_1P8V | GPIO_PULL_UP,
-         bmi160_interrupt)
+         motion_interrupt)
 GPIO_INT_RO(EMMC_CMD,       PIN(B, 15), GPIO_INT_FALLING,
          emmc_cmd_interrupt)
 GPIO_INT(SPI1_NSS,          PIN(A, 15), GPIO_INT_BOTH | GPIO_PULL_UP,
@@ -122,5 +122,5 @@ ALTERNATE(PIN_MASK(A, 0x8000), 0, MODULE_SPI,        0)
 /* EMMC SPI SLAVE: PB13/14/15 */
 ALTERNATE(PIN_MASK(B, 0xE000), 0, MODULE_SPI_FLASH,  0)
 /* SENSORS SPI MASTER: PB10, PB12, PC2, PC3 */
-ALTERNATE(PIN_MASK(B, 0x0400), 5, MODULE_SPI_MASTER, 0)
-ALTERNATE(PIN_MASK(C, 0x000C), 1, MODULE_SPI_MASTER, 0)
+ALTERNATE(PIN_MASK(B, 0x0400), 5, MODULE_SPI_CONTROLLER, 0)
+ALTERNATE(PIN_MASK(C, 0x000C), 1, MODULE_SPI_CONTROLLER, 0)
diff --git a/board/jacuzzi/led.c b/board/jacuzzi/led.c
index d0039cbfae..ee4df43121 100644
--- a/board/jacuzzi/led.c
+++ b/board/jacuzzi/led.c
@@ -1,37 +1,43 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Power and battery LED control for Jacuzzi
  */
 #include "common.h"
-#include "ioexpander.h"
 #include "driver/ioexpander/it8801.h"
 #include "ec_commands.h"
+#include "ioexpander.h"
 #include "led_common.h"
 #include "led_onoff_states.h"
 #define LED_ON_LVL 0
 #define LED_OFF_LVL 1
-const int led_charge_lvl_1 = 5;
-const int led_charge_lvl_2 = 95;
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
+__override const int led_charge_lvl_1 = 5;
+__override const int led_charge_lvl_2 = 95;
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-void led_set_color_battery(enum ec_led_colors color)
+__override void led_set_color_battery(enum ec_led_colors color)
 {
 	switch (color) {
 	case EC_LED_COLOR_AMBER:
@@ -77,4 +83,4 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 			led_set_color_battery(LED_OFF);
 	}
 	return EC_SUCCESS;
-}
\ No newline at end of file
+}
diff --git a/board/jacuzzi/vif_override.xml b/board/jacuzzi/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/jacuzzi/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/jerry/battery.c b/board/jerry/battery.c
deleted file mode 100644
index 4f127c9458..0000000000
--- a/board/jerry/battery.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery.h"
-#include "battery_smart.h"
-#include "console.h"
-#include "gpio.h"
-#include "host_command.h"
-#include "util.h"
-
-/* Shutdown mode parameter to write to manufacturer access register */
-#define SB_SHUTDOWN_DATA	0x0010
-
-static const struct battery_info info = {
-	.voltage_max    = 8400,		/* mV */
-	.voltage_normal = 7400,
-	.voltage_min    = 6000,
-	.precharge_current  = 256,	/* mA */
-	.start_charging_min_c = 0,
-	.start_charging_max_c = 45,
-	.charging_min_c       = 0,
-	.charging_max_c       = 45,
-	.discharging_min_c    = 0,
-	.discharging_max_c    = 60,
-};
-
-const struct battery_info *battery_get_info(void)
-{
-	return &info;
-}
-
-static int cutoff(void)
-{
-	int rv;
-
-	/* Ship mode command must be sent twice to take effect */
-	rv = sb_write(SB_MANUFACTURER_ACCESS, SB_SHUTDOWN_DATA);
-
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	return sb_write(SB_MANUFACTURER_ACCESS, SB_SHUTDOWN_DATA);
-}
-
-
-int board_cut_off_battery(void)
-{
-	return cutoff();
-}
-
diff --git a/board/jerry/board.c b/board/jerry/board.c
deleted file mode 100644
index 9583f7ef41..0000000000
--- a/board/jerry/board.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Veyron board-specific configuration */
-
-#include "battery.h"
-#include "battery_smart.h"
-#include "chipset.h"
-#include "common.h"
-#include "driver/charger/bq24715.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "i2c.h"
-#include "keyboard_raw.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "power.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "spi.h"
-#include "task.h"
-#include "util.h"
-#include "timer.h"
-#include "charger.h"
-#include "gpio_list.h"
-
-/* power signal list.  Must match order of enum power_signal. */
-const struct power_signal_info power_signal_list[] = {
-	{GPIO_SOC_POWER_GOOD, POWER_SIGNAL_ACTIVE_HIGH, "POWER_GOOD"},
-	{GPIO_SUSPEND_L,      POWER_SIGNAL_ACTIVE_HIGH, "SUSPEND#_ASSERTED"},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"master", I2C_PORT_MASTER, 100},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	{STM32_TIM(2), STM32_TIM_CH(3),
-	 PWM_CONFIG_ACTIVE_LOW},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* Charger chips */
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = CHARGER_ADDR_FLAGS,
-		.drv = &bq24715_drv,
-	},
-};
-
-void board_config_pre_init(void)
-{
-	/* enable SYSCFG clock */
-	STM32_RCC_APB2ENR |= BIT(0);
-
-	/* Remap USART DMA to match the USART driver */
-	/*
-	 * the DMA mapping is :
-	 *  Chan 2 : TIM1_CH1
-	 *  Chan 3 : SPI1_TX
-	 *  Chan 4 : USART1_TX
-	 *  Chan 5 : USART1_RX
-	 */
-	STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10); /* Remap USART1 RX/TX DMA */
-}
diff --git a/board/jerry/board.h b/board/jerry/board.h
deleted file mode 100644
index 2671e20fbb..0000000000
--- a/board/jerry/board.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Veyron board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Increase size of UART TX buffer. */
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 1024
-
-/* Optional features */
-#define CONFIG_AP_HANG_DETECT
-#define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_SMART
-#define CONFIG_BOARD_PRE_INIT
-#define CONFIG_CHARGER
-#define CONFIG_CHARGER_BQ24715
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHIPSET_RK3288
-#define CONFIG_EXTPOWER_GPIO
-#define CONFIG_FORCE_CONSOLE_RESUME
-#define CONFIG_HOST_COMMAND_STATUS
-#define CONFIG_HOSTCMD_VBNV_CONTEXT
-#define CONFIG_I2C
-#define CONFIG_I2C_MASTER
-#define CONFIG_I2C_VIRTUAL_BATTERY
-#define CONFIG_KEYBOARD_COL2_INVERTED
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
-#define CONFIG_LED_COMMON
-#define CONFIG_LED_POLICY_STD
-#define CONFIG_LED_BAT_ACTIVE_LOW
-#define CONFIG_LED_POWER_ACTIVE_LOW
-#define CONFIG_LOW_POWER_IDLE
-#define CONFIG_LOW_POWER_S0
-#define CONFIG_MKBP_USE_GPIO
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_FLAGS BUTTON_FLAG_ACTIVE_HIGH
-#define CONFIG_POWER_COMMON
-#define CONFIG_PWM
-#define CONFIG_SPI
-#define CONFIG_STM_HWTIMER32
-#define CONFIG_UART_RX_DMA
-#define CONFIG_VBOOT_HASH
-
-#define CONFIG_HOSTCMD_ALIGNED
-
-#define CONFIG_LTO
-
-#undef CONFIG_CONSOLE_CMDHELP
-#undef CONFIG_CONSOLE_HISTORY
-#undef CONFIG_SOFTWARE_PANIC
-#undef CONFIG_WATCHDOG_HELP
-#undef CONFIG_CMD_KEYBOARD
-
-/* Not enough RO flash space */
-#undef CONFIG_HOSTCMD_GET_UPTIME_INFO
-
-#define CONFIG_HIBERNATE_WAKEUP_PINS (STM32_PWR_CSR_EWUP1 | STM32_PWR_CSR_EWUP6)
-
-#ifndef __ASSEMBLER__
-
-/* 48 MHz SYSCLK clock frequency */
-#define CPU_CLOCK 48000000
-
-/* Keyboard output port list */
-#define KB_OUT_PORT_LIST GPIO_A, GPIO_B, GPIO_C
-
-/* Single I2C port, where the EC is the master. */
-#define I2C_PORT_MASTER 0
-#define I2C_PORT_BATTERY I2C_PORT_MASTER
-#define I2C_PORT_CHARGER I2C_PORT_MASTER
-#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_MASTER
-
-/* Timer selection */
-#define TIM_CLOCK32  2
-#define TIM_WATCHDOG 4
-
-#include "gpio_signal.h"
-
-enum power_signal {
-	RK_POWER_GOOD = 0,
-	RK_SUSPEND_ASSERTED,
-	/* Number of power signals */
-	POWER_SIGNAL_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_POWER_LED = 0,
-	/* Number of PWM channels */
-	PWM_CH_COUNT
-};
-
-/* Charger module */
-#define CONFIG_CHARGER_SENSE_RESISTOR 10 /* Charge sense resistor, mOhm */
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 /* Input sensor resistor, mOhm */
-/* Input current limit for 45W AC adapter:
- * 45W/19V*85%=2013mA, choose the closest charger setting = 2048mA
- */
-#define CONFIG_CHARGER_INPUT_CURRENT 2048 /* mA, based on Link HW design */
-#define CONFIG_CHARGER_CURRENT_LIMIT 3000 /* PL102 inductor 3.0A(3.8A) */
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/jerry/build.mk b/board/jerry/build.mk
deleted file mode 100644
index 05f23ede25..0000000000
--- a/board/jerry/build.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-# -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-# the IC is STmicro STM32F071RB
-CHIP:=stm32
-CHIP_FAMILY:=stm32f0
-CHIP_VARIANT:=stm32f07x
-
-board-y=board.o battery.o
diff --git a/board/jerry/ec.tasklist b/board/jerry/ec.tasklist
deleted file mode 100644
index 672a633bcd..0000000000
--- a/board/jerry/ec.tasklist
+++ /dev/null
@@ -1,15 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE)
diff --git a/board/jerry/gpio.inc b/board/jerry/gpio.inc
deleted file mode 100644
index 8dfaa6417b..0000000000
--- a/board/jerry/gpio.inc
+++ /dev/null
@@ -1,64 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-GPIO_INT(POWER_BUTTON_L, PIN(B, 5),  GPIO_INT_BOTH,                power_button_interrupt) /* wk6 */ /* active high, the name is for compatibility with existing code */
-GPIO_INT(SOC_POWER_GOOD, PIN(A, 3),  GPIO_INT_BOTH,                power_signal_interrupt)
-GPIO_INT(LID_OPEN,       PIN(C, 13), GPIO_INT_BOTH,                lid_interrupt)
-GPIO_INT(SUSPEND_L,      PIN(C, 7),  GPIO_INT_BOTH,                power_signal_interrupt)
-GPIO_INT(SPI1_NSS,       PIN(A, 4),  GPIO_INT_BOTH,                spi_event)
-GPIO_INT(AC_PRESENT,     PIN(C, 6),  GPIO_INT_BOTH | GPIO_PULL_UP, extpower_interrupt)
-
-/* Keyboard inputs */
-#define GPIO_KB_INPUT  (GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH)
-#define GPIO_KB_OUTPUT GPIO_ODR_HIGH
-
-GPIO_INT(KB_IN00, PIN(C, 8),  GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
-GPIO_INT(KB_IN01, PIN(C, 9),  GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
-GPIO_INT(KB_IN02, PIN(C, 10), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
-GPIO_INT(KB_IN03, PIN(C, 11), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
-GPIO_INT(KB_IN04, PIN(C, 12), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
-GPIO_INT(KB_IN05, PIN(C, 14), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
-GPIO_INT(KB_IN06, PIN(C, 15), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
-GPIO_INT(KB_IN07, PIN(D, 2),  GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
-
-/* Other inputs */
-GPIO(EC_WAKE, PIN(A, 0), GPIO_INPUT | GPIO_PULL_DOWN) /* wk1 */
-GPIO(WP_L,    PIN(B, 4), GPIO_INPUT)
-
-/* Outputs */
-GPIO(BAT_LED_RED,       PIN(B, 11), GPIO_OUT_HIGH)
-GPIO(BAT_LED_GREEN,     PIN(A, 11), GPIO_OUT_HIGH)
-GPIO(EC_BL_OVERRIDE,    PIN(F, 1),  GPIO_OUT_LOW)
-GPIO(EC_INT_L,          PIN(B, 9),  GPIO_OUT_LOW)
-GPIO(ENTERING_RW,       PIN(F, 0),  GPIO_OUT_LOW)
-GPIO(I2C1_SCL,          PIN(B, 6),  GPIO_ODR_HIGH)
-GPIO(I2C1_SDA,          PIN(B, 7),  GPIO_ODR_HIGH)
-GPIO(KB_OUT00,          PIN(B, 0),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT01,          PIN(B, 8),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT02,          PIN(B, 12), GPIO_OUT_LOW) /* Inverted from silegro */
-GPIO(KB_OUT03,          PIN(B, 13), GPIO_KB_OUTPUT)
-GPIO(KB_OUT04,          PIN(B, 14), GPIO_KB_OUTPUT)
-GPIO(KB_OUT05,          PIN(B, 15), GPIO_KB_OUTPUT)
-GPIO(KB_OUT06,          PIN(C, 0),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT07,          PIN(C, 1),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT08,          PIN(C, 2),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT09,          PIN(B, 1),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT10,          PIN(C, 5),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT11,          PIN(C, 4),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT12,          PIN(A, 13), GPIO_KB_OUTPUT)
-GPIO(POWER_LED,         PIN(A, 2),  GPIO_OUT_HIGH)
-GPIO(PMIC_PWRON,        PIN(A, 12), GPIO_OUT_LOW)
-GPIO(PMIC_RESET,        PIN(B, 3),  GPIO_OUT_LOW)
-GPIO(PMIC_SOURCE_PWREN, PIN(B, 10), GPIO_OUT_LOW)
-GPIO(PMIC_WARM_RESET_L, PIN(C, 3),  GPIO_ODR_HIGH)
-
-ALTERNATE(PIN_MASK(A, 0x00f0), 0, MODULE_SPI,  0)
-ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART, 0)
-ALTERNATE(PIN_MASK(B, 0x00c0), 1, MODULE_I2C,  0)
diff --git a/board/jewel b/board/jewel
new file mode 120000
index 0000000000..7f4a914148
--- /dev/null
+++ b/board/jewel
@@ -0,0 +1 @@
+hammer
\ No newline at end of file
diff --git a/board/jinlon/battery.c b/board/jinlon/battery.c
index cf3941221c..9cf4c15458 100644
--- a/board/jinlon/battery.c
+++ b/board/jinlon/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -36,7 +36,7 @@
  */
 const struct board_batt_params board_battery_info[] = {
 	/* DynaPack CosMX Battery Information */
-	[BATTERY_DANAPACK_COS] = {
+	[BATTERY_DYNAPACK_COS] = {
 		.fuel_gauge = {
 			.manuf_name = "333-2C-14-A",
 			.ship_mode = {
@@ -66,28 +66,4 @@ const struct board_batt_params board_battery_info[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
 
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_DANAPACK_COS;
-
-/* Lower our input voltage to 5V in S5/G3 when battery is full. */
-static void reduce_input_voltage_when_full(void)
-{
-	int max_pd_voltage_mv;
-	int port;
-
-	if (charge_get_percent() == 100 &&
-	    chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF))
-		max_pd_voltage_mv = 5000;
-	else
-		max_pd_voltage_mv = PD_MAX_VOLTAGE_MV;
-
-	if (pd_get_max_voltage() != max_pd_voltage_mv) {
-		for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++)
-			pd_set_external_voltage_limit(port, max_pd_voltage_mv);
-	}
-}
-DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, reduce_input_voltage_when_full,
-	     HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, reduce_input_voltage_when_full,
-	     HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, reduce_input_voltage_when_full,
-	     HOOK_PRIO_DEFAULT);
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_DYNAPACK_COS;
diff --git a/board/jinlon/board.c b/board/jinlon/board.c
index f789b15590..290fa19000 100644
--- a/board/jinlon/board.c
+++ b/board/jinlon/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,6 @@
 /* Hatch board-specific configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "button.h"
 #include "common.h"
 #include "cros_board_info.h"
@@ -37,16 +36,16 @@
 #include "tablet_mode.h"
 #include "task.h"
 #include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
 #include "thermal.h"
-#include "thermistor.h"
 #include "uart.h"
 #include "usb_charge.h"
 #include "usb_pd.h"
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void check_reboot_deferred(void);
 DECLARE_DEFERRED(check_reboot_deferred);
@@ -99,11 +98,11 @@ static void bc12_interrupt(enum gpio_signal signal)
 {
 	switch (signal) {
 	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
 		break;
 
 	case GPIO_USB_C1_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12, 0);
+		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
 		break;
 
 	default:
@@ -111,22 +110,24 @@ static void bc12_interrupt(enum gpio_signal signal)
 	}
 }
 
-#include "gpio_list.h" /* Must come after other header files. */
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
 
 /******************************************************************************/
 /* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
+const struct spi_device_t spi_devices[] = {};
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
 /******************************************************************************/
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT]   = { .channel = 3, .flags = 0, .freq = 100 },
-	[PWM_CH_FAN] = {.channel = 5, .flags = PWM_CONFIG_OPEN_DRAIN,
-			.freq = 25000},
-	[PWM_CH_FAN2] = {.channel = 6, .flags = PWM_CONFIG_OPEN_DRAIN,
-			.freq = 25000},
+	[PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 100 },
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
+	[PWM_CH_FAN2] = { .channel = 6,
+			  .flags = PWM_CONFIG_OPEN_DRAIN,
+			  .freq = 25000 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
@@ -137,7 +138,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = I2C_PORT_TCPC0,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
 		},
 		.drv = &ps8xxx_tcpm_drv,
 	},
@@ -145,22 +146,26 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = I2C_PORT_TCPC1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
 		},
 		.drv = &ps8xxx_tcpm_drv,
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_TCPC_0] = {
-		.usb_port = USB_PD_PORT_TCPC_0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_0,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 	},
 	[USB_PD_PORT_TCPC_1] = {
-		.usb_port = USB_PD_PORT_TCPC_1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 	}
 };
 
@@ -189,17 +194,13 @@ static struct bmi_drv_data_t g_bmi160_data;
 static struct accelgyro_saved_data_t g_bma255_data;
 
 /* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+					      { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
 
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
@@ -279,14 +280,14 @@ unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
 
 const struct fan_conf fan_conf_1 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_1,	/* Use MFT id to control fan */
+	.ch = MFT_CH_1, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN2,
 };
@@ -312,71 +313,76 @@ const struct fan_t fans[FAN_CH_COUNT] = {
 /******************************************************************************/
 /* MFT channels. These are logically separate from pwm_channels. */
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN},
-	[MFT_CH_1] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN2},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN },
+	[MFT_CH_1] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN2 },
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		"TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_2] = {
-		"TEMP_5V_REG", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_3] = {
-		"TEMP_CPU", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_1] = { "TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_2] = { "TEMP_5V_REG", NPCX_ADC_CH1, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_3] = { "TEMP_CPU", NPCX_ADC_CH2, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "5v Reg",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "CPU",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_3},
-	[TEMP_SENSOR_4] = {.name = "IR Sensor",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = oti502_get_val,
-				 .idx = OTI502_IDX_OBJECT},
+	[TEMP_SENSOR_1] = { .name = "Charger",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "5v Reg",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "CPU",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
+	[TEMP_SENSOR_4] = { .name = "IR Sensor",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = oti502_get_val,
+			    .idx = OTI502_IDX_OBJECT },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
-
 /* Dratini Temperature sensors */
-const static struct ec_thermal_config thermal_a = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(25),
-	.temp_fan_max = C_TO_K(70),
-};
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_A                \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A;
 
-const static struct ec_thermal_config thermal_b = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(86),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(25),
-	.temp_fan_max = C_TO_K(50),
-};
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_B                \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(86), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_b = THERMAL_B;
 
 struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
 
@@ -433,8 +439,8 @@ static const struct ec_response_keybd_config keybd2 = {
 	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
 };
 
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	/*
 	 * Future boards should use fw_config instead of SKU ID
@@ -482,15 +488,15 @@ void board_overcurrent_event(int port, int is_overcurrented)
  * The connector has 24 pins total, and there is no pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-		{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-		{0, 7}, {1, 4}, {1, 3}, {1, 6}, {1, 7},
-		{3, 1}, {2, 0}, {1, 5}, {2, 6}, {2, 7},
-		{2, 1}, {2, 4}, {2, 5}, {1, 2}, {2, 3},
-		{2, 2}, {3, 0}, {-1, -1}, {-1, -1}, {-1, -1},
+	{ -1, -1 }, { 0, 5 }, { 1, 1 },	  { 1, 0 },   { 0, 6 },
+	{ 0, 7 },   { 1, 4 }, { 1, 3 },	  { 1, 6 },   { 1, 7 },
+	{ 3, 1 },   { 2, 0 }, { 1, 5 },	  { 2, 6 },   { 2, 7 },
+	{ 2, 1 },   { 2, 4 }, { 2, 5 },	  { 1, 2 },   { 2, 3 },
+	{ 2, 2 },   { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 },
 };
 
 const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 #endif
 
 bool board_is_convertible(void)
@@ -498,10 +504,9 @@ bool board_is_convertible(void)
 	const uint8_t sku = get_board_sku();
 
 	return (sku == 255) || (sku == 1) || (sku == 2) || (sku == 21) ||
-		(sku == 22);
+	       (sku == 22);
 }
 
-
 void all_sys_pgood_check_reboot(void)
 {
 	hook_call_deferred(&check_reboot_deferred_data, 3000 * MSEC);
@@ -512,7 +517,7 @@ __override void board_chipset_forced_shutdown(void)
 	hook_call_deferred(&check_reboot_deferred_data, -1);
 }
 DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_forced_shutdown,
-	HOOK_PRIO_DEFAULT);
+	     HOOK_PRIO_DEFAULT);
 
 static void check_reboot_deferred(void)
 {
diff --git a/board/jinlon/board.h b/board/jinlon/board.h
index f898b90c9a..350376dd63 100644
--- a/board/jinlon/board.h
+++ b/board/jinlon/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,7 +19,7 @@
 #define CONFIG_LED_COMMON
 #define CONFIG_LOW_POWER_IDLE
 
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 
 #undef CONFIG_UART_TX_BUF_SIZE
 #define CONFIG_UART_TX_BUF_SIZE 4096
@@ -32,12 +32,13 @@
  * Jinlon's battery takes several seconds to come back out of its disconnect
  * state (~4 seconds, but give it 6 for margin).
  */
-#undef  CONFIG_POWER_BUTTON_INIT_TIMEOUT
+#undef CONFIG_POWER_BUTTON_INIT_TIMEOUT
 #define CONFIG_POWER_BUTTON_INIT_TIMEOUT 6
 
+#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV 5000
+
 /* Sensors */
 /* BMI160 Base accel/gyro */
-#define CONFIG_ACCEL_INTERRUPTS
 #define CONFIG_ACCELGYRO_BMI160
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
@@ -50,7 +51,6 @@
 #define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
 #define CONFIG_LID_ANGLE_UPDATE
 #define CONFIG_GMR_TABLET_MODE
-#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L
 
 /* USB Type C and USB PD defines */
 #define CONFIG_USB_PD_COMM_LOCKED
@@ -98,7 +98,7 @@
 #define CONFIG_FAN_INIT_SPEED 50
 #define RPM_DEVIATION 1
 #define CONFIG_TEMP_SENSOR_OTI502
-#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_A_RAILS
+#define CONFIG_TEMP_SENSOR_POWER
 #define CONFIG_THERMISTOR
 #define CONFIG_THROTTLE_AP
 #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
@@ -117,15 +117,16 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_AC_PRESENT		GPIO_ACOK_OD
-#define GPIO_RSMRST_L_PGOOD	GPIO_PG_EC_RSMRST_L
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L
+#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
 
 #ifndef __ASSEMBLER__
 
@@ -133,9 +134,9 @@
 #include "registers.h"
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_1,	/* ADC0 */
-	ADC_TEMP_SENSOR_2,	/* ADC1 */
-	ADC_TEMP_SENSOR_3,	/* ADC2 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
+	ADC_TEMP_SENSOR_3, /* ADC2 */
 	ADC_CH_COUNT
 };
 
@@ -146,12 +147,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_FAN,
-	PWM_CH_FAN2,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_FAN, PWM_CH_FAN2, PWM_CH_COUNT };
 
 enum fan_channel {
 	FAN_CH_0 = 0,
@@ -177,15 +173,10 @@ enum temp_sensor_id {
 
 /* List of possible batteries */
 enum battery_type {
-	BATTERY_DANAPACK_COS,
+	BATTERY_DYNAPACK_COS,
 	BATTERY_TYPE_COUNT,
 };
 
-#ifdef CONFIG_KEYBOARD_FACTORY_TEST
-extern const int keyboard_factory_scan_pins[][2];
-extern const int keyboard_factory_scan_pins_used;
-#endif
-
 #endif /* !__ASSEMBLER__ */
 
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/jinlon/build.mk b/board/jinlon/build.mk
index 2d6118ea70..4e42a0616e 100644
--- a/board/jinlon/build.mk
+++ b/board/jinlon/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/jinlon/ec.tasklist b/board/jinlon/ec.tasklist
index 4a1024a091..829be2b7c8 100644
--- a/board/jinlon/ec.tasklist
+++ b/board/jinlon/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/jinlon/gpio.inc b/board/jinlon/gpio.inc
index f57a331436..91002dacc1 100644
--- a/board/jinlon/gpio.inc
+++ b/board/jinlon/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,10 +17,10 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(PG_EC_RSMRST_L,       PIN(E, 2), GPIO_INT_BOTH, intel_x86_rsmrst_signal_interrupt)
diff --git a/board/jinlon/led.c b/board/jinlon/led.c
index 18dfb67f78..f9441fd78e 100644
--- a/board/jinlon/led.c
+++ b/board/jinlon/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,9 +11,9 @@
 #include "chipset.h"
 #include "ec_commands.h"
 #include "gpio.h"
+#include "hooks.h"
 #include "host_command.h"
 #include "led_common.h"
-#include "hooks.h"
 
 #define BAT_LED_ON 0
 #define BAT_LED_OFF 1
@@ -25,11 +25,9 @@
 #define LED_ON_TICKS 5
 #define POWER_LED_ON_TICKS 2
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_LEFT_LED,
-	EC_LED_ID_RIGHT_LED,
-	EC_LED_ID_POWER_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_LEFT_LED,
+					     EC_LED_ID_RIGHT_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -37,7 +35,7 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static void led_set_color_battery(int port, enum led_color color)
@@ -65,7 +63,7 @@ static void led_set_color_battery(int port, enum led_color color)
 	}
 }
 
-void led_set_color_power(enum ec_led_colors color)
+void led_set_color_power(enum led_color color)
 {
 	switch (color) {
 	case LED_OFF:
@@ -147,21 +145,23 @@ static void set_active_port_color(enum led_color color)
 static void led_set_battery(void)
 {
 	static int battery_ticks;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
 		/* Always indicate when charging, even in suspend. */
 		set_active_port_color(LED_AMBER);
 		break;
-	case PWR_STATE_DISCHARGE:
+	case LED_PWRS_DISCHARGE:
 		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
 			if (charge_get_percent() < 10)
-				led_set_color_battery(0, (battery_ticks %
-					LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-					LED_WHITE : LED_OFF);
+				led_set_color_battery(
+					0,
+					(battery_ticks % LED_TICKS_PER_CYCLE <
+					 LED_ON_TICKS) ?
+						LED_WHITE :
+						LED_OFF);
 			else
 				led_set_color_battery(0, LED_OFF);
 		}
@@ -169,20 +169,21 @@ static void led_set_battery(void)
 		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
 			led_set_color_battery(1, LED_OFF);
 		break;
-	case PWR_STATE_ERROR:
-		set_active_port_color((battery_ticks & 0x2) ?
-				LED_WHITE : LED_OFF);
+	case LED_PWRS_ERROR:
+		set_active_port_color((battery_ticks & 0x2) ? LED_WHITE :
+							      LED_OFF);
 		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
+	case LED_PWRS_CHARGE_NEAR_FULL:
 		set_active_port_color(LED_WHITE);
 		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			set_active_port_color((battery_ticks %
-				LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-				LED_AMBER : LED_OFF);
-		else
-			set_active_port_color(LED_WHITE);
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		set_active_port_color(LED_WHITE);
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		set_active_port_color(
+			(battery_ticks % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
+				LED_AMBER :
+				LED_OFF);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
@@ -200,9 +201,10 @@ static void led_set_power(void)
 		led_set_color_power(LED_WHITE);
 	else if (chipset_in_state(CHIPSET_STATE_SUSPEND |
 				  CHIPSET_STATE_STANDBY))
-		led_set_color_power((power_tick %
-			LED_TICKS_PER_CYCLE < POWER_LED_ON_TICKS) ?
-			LED_WHITE : LED_OFF);
+		led_set_color_power((power_tick % LED_TICKS_PER_CYCLE <
+				     POWER_LED_ON_TICKS) ?
+					    LED_WHITE :
+					    LED_OFF);
 	else
 		led_set_color_power(LED_OFF);
 }
diff --git a/board/jinlon/thermal.c b/board/jinlon/thermal.c
index 4d75f70738..6a18861af3 100644
--- a/board/jinlon/thermal.c
+++ b/board/jinlon/thermal.c
@@ -1,8 +1,9 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "builtin/assert.h"
 #include "chipset.h"
 #include "common.h"
 #include "console.h"
@@ -16,7 +17,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_THERMAL, outstr)
-#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
 
 struct fan_step {
 	/*
@@ -40,109 +41,108 @@ static const struct fan_step *fan_step_table;
 static const struct fan_step fan_table_clamshell[] = {
 	{
 		/* level 0 */
-		.on = {0, -1, 54, 34},
-		.off = {99, -1, 99, 99},
-		.rpm = {0, 0},
+		.on = { 0, -1, 54, 41 },
+		.off = { 99, -1, 99, 99 },
+		.rpm = { 0, 0 },
 	},
 	{
 		/* level 1 */
-		.on = {0, -1, 57, 35},
-		.off = {99, -1, 54, 34},
-		.rpm = {3950, 3850},
+		.on = { 0, -1, 57, 42 },
+		.off = { 99, -1, 54, 41 },
+		.rpm = { 3950, 3850 },
 	},
 	{
 		/* level 2 */
-		.on = {0, -1, 58, 36},
-		.off = {99, -1, 57, 35},
-		.rpm = {4200, 4100},
+		.on = { 0, -1, 58, 43 },
+		.off = { 99, -1, 57, 42 },
+		.rpm = { 4200, 4100 },
 	},
 	{
 		/* level 3 */
-		.on = {0, -1, 59, 37},
-		.off = {99, -1, 58, 36},
-		.rpm = {4550, 4450},
+		.on = { 0, -1, 59, 44 },
+		.off = { 99, -1, 58, 43 },
+		.rpm = { 4550, 4450 },
 	},
 	{
 		/* level 4 */
-		.on = {60, -1, 60, 38},
-		.off = {58, -1, 59, 37},
-		.rpm = {4900, 4800},
+		.on = { 62, -1, 60, 45 },
+		.off = { 58, -1, 59, 44 },
+		.rpm = { 4900, 4800 },
 	},
 	{
 		/* level 5 */
-		.on = {62, -1, 61, 39},
-		.off = {60, -1, 60, 38},
-		.rpm = {5250, 5150},
+		.on = { 64, -1, 61, 46 },
+		.off = { 62, -1, 60, 45 },
+		.rpm = { 5250, 5150 },
 	},
 	{
 		/* level 6 */
-		.on = {65, -1, 64, 40},
-		.off = {62, -1, 61, 39},
-		.rpm = {5400, 5300},
+		.on = { 65, -1, 64, 47 },
+		.off = { 63, -1, 61, 46 },
+		.rpm = { 5400, 5300 },
 	},
 	{
 		/* level 7 */
-		.on = {100, -1, 100, 100},
-		.off = {65, -1, 62, 40},
-		.rpm = {6000, 6150},
+		.on = { 100, -1, 100, 100 },
+		.off = { 65, -1, 62, 47 },
+		.rpm = { 6000, 5900 },
 	},
 };
 
 static const struct fan_step fan_table_tablet[] = {
 	{
 		/* level 0 */
-		.on = {0, -1, 55, 39},
-		.off = {99, -1, 99, 99},
-		.rpm = {0, 0},
+		.on = { 0, -1, 55, 41 },
+		.off = { 99, -1, 99, 99 },
+		.rpm = { 0, 0 },
 	},
 	{
 		/* level 1 */
-		.on = {0, -1, 56, 40},
-		.off = {99, -1, 55, 39},
-		.rpm = {0, 0},
+		.on = { 0, -1, 56, 42 },
+		.off = { 99, -1, 55, 41 },
+		.rpm = { 0, 0 },
 	},
 	{
 		/* level 2 */
-		.on = {0, -1, 57, 41},
-		.off = {99, -1, 56, 40},
-		.rpm = {4000, 3350},
+		.on = { 0, -1, 57, 43 },
+		.off = { 99, -1, 56, 42 },
+		.rpm = { 4000, 3350 },
 	},
 	{
 		/* level 3 */
-		.on = {0, -1, 58, 42},
-		.off = {99, -1, 57, 41},
-		.rpm = {4200, 3400},
+		.on = { 0, -1, 58, 44 },
+		.off = { 99, -1, 57, 43 },
+		.rpm = { 4200, 3400 },
 	},
 	{
 		/* level 4 */
-		.on = {60, -1, 59, 43},
-		.off = {58, -1, 58, 42},
-		.rpm = {4400, 3500},
+		.on = { 60, -1, 59, 45 },
+		.off = { 58, -1, 58, 44 },
+		.rpm = { 4400, 3500 },
 	},
 	{
 		/* level 5 */
-		.on = {62, -1, 60, 44},
-		.off = {60, -1, 59, 43},
-		.rpm = {4800, 4350},
+		.on = { 62, -1, 60, 46 },
+		.off = { 60, -1, 59, 45 },
+		.rpm = { 4800, 4350 },
 	},
 	{
 		/* level 6 */
-		.on = {65, -1, 61, 45},
-		.off = {62, -1, 60, 44},
-		.rpm = {5000, 4500},
+		.on = { 65, -1, 61, 47 },
+		.off = { 62, -1, 60, 46 },
+		.rpm = { 5000, 4500 },
 	},
 	{
 		/* level 7 */
-		.on = {100, -1, 100, 100},
-		.off = {65, -1, 61, 45},
-		.rpm = {5200, 5100},
+		.on = { 100, -1, 100, 100 },
+		.off = { 65, -1, 61, 47 },
+		.rpm = { 5200, 5100 },
 	},
 };
 
 #define NUM_FAN_LEVELS ARRAY_SIZE(fan_table_clamshell)
 
-BUILD_ASSERT(ARRAY_SIZE(fan_table_clamshell) ==
-	ARRAY_SIZE(fan_table_tablet));
+BUILD_ASSERT(ARRAY_SIZE(fan_table_clamshell) == ARRAY_SIZE(fan_table_tablet));
 
 int fan_table_to_rpm(int fan, int *temp)
 {
@@ -165,12 +165,15 @@ int fan_table_to_rpm(int fan, int *temp)
 	 */
 
 	if (temp[TEMP_SENSOR_1] < prev_tmp[TEMP_SENSOR_1] ||
-		temp[TEMP_SENSOR_3] < prev_tmp[TEMP_SENSOR_3] ||
-		temp[TEMP_SENSOR_4] < prev_tmp[TEMP_SENSOR_4]) {
+	    temp[TEMP_SENSOR_3] < prev_tmp[TEMP_SENSOR_3] ||
+	    temp[TEMP_SENSOR_4] < prev_tmp[TEMP_SENSOR_4]) {
 		for (i = current_level; i > 0; i--) {
-			if (temp[TEMP_SENSOR_1] < fan_step_table[i].off[TEMP_SENSOR_1] &&
-				 temp[TEMP_SENSOR_4] < fan_step_table[i].off[TEMP_SENSOR_4] &&
-				 temp[TEMP_SENSOR_3] < fan_step_table[i].off[TEMP_SENSOR_3])
+			if (temp[TEMP_SENSOR_1] <
+				    fan_step_table[i].off[TEMP_SENSOR_1] &&
+			    temp[TEMP_SENSOR_4] <
+				    fan_step_table[i].off[TEMP_SENSOR_4] &&
+			    temp[TEMP_SENSOR_3] <
+				    fan_step_table[i].off[TEMP_SENSOR_3])
 				current_level = i - 1;
 			else
 				break;
@@ -179,9 +182,12 @@ int fan_table_to_rpm(int fan, int *temp)
 		   temp[TEMP_SENSOR_3] > prev_tmp[TEMP_SENSOR_3] ||
 		   temp[TEMP_SENSOR_4] > prev_tmp[TEMP_SENSOR_4]) {
 		for (i = current_level; i < NUM_FAN_LEVELS; i++) {
-			if ((temp[TEMP_SENSOR_1] > fan_step_table[i].on[TEMP_SENSOR_1] &&
-				 temp[TEMP_SENSOR_4] > fan_step_table[i].on[TEMP_SENSOR_4]) ||
-				 temp[TEMP_SENSOR_3] > fan_step_table[i].on[TEMP_SENSOR_3])
+			if ((temp[TEMP_SENSOR_1] >
+				     fan_step_table[i].on[TEMP_SENSOR_1] &&
+			     temp[TEMP_SENSOR_4] >
+				     fan_step_table[i].on[TEMP_SENSOR_4]) ||
+			    temp[TEMP_SENSOR_3] >
+				    fan_step_table[i].on[TEMP_SENSOR_3])
 				current_level = i + 1;
 			else
 				break;
@@ -212,10 +218,8 @@ int fan_table_to_rpm(int fan, int *temp)
 
 void board_override_fan_control(int fan, int *tmp)
 {
-	if (chipset_in_state(CHIPSET_STATE_ON |
-		CHIPSET_STATE_ANY_SUSPEND)) {
+	if (chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND)) {
 		fan_set_rpm_mode(FAN_CH(fan), 1);
-		fan_set_rpm_target(FAN_CH(fan),
-			fan_table_to_rpm(fan, tmp));
+		fan_set_rpm_target(FAN_CH(fan), fan_table_to_rpm(fan, tmp));
 	}
 }
diff --git a/board/jinlon/vif_override.xml b/board/jinlon/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/jinlon/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/jslrvp_ite/board.c b/board/jslrvp_ite/board.c
deleted file mode 100644
index 6a8cc3972b..0000000000
--- a/board/jslrvp_ite/board.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel Jasperlake RVP with ITE EC board specific configuration */
-
-#include "button.h"
-#include "charger.h"
-#include "driver/charger/isl923x.h"
-#include "extpower.h"
-#include "i2c.h"
-#include "icelake.h"
-#include "intc.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "uart.h"
-
-#include "gpio_list.h"
-
-#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ## args)
-
-/* TCPC gpios */
-const struct tcpc_gpio_config_t tcpc_gpios[] = {
-	[TYPE_C_PORT_0] = {
-		.vbus = {
-			.pin = GPIO_USB_C0_VBUS_INT,
-			.pin_pol = 1,
-		},
-		.src = {
-			.pin = GPIO_USB_C0_SRC_EN,
-			.pin_pol = 1,
-		},
-		.snk = {
-			.pin = GPIO_USB_C0_SNK_EN_L,
-			.pin_pol = 0,
-		},
-	},
-	[TYPE_C_PORT_1] = {
-		.vbus = {
-			.pin = GPIO_USB_C1_VBUS_INT,
-			.pin_pol = 1,
-		},
-		.src = {
-			.pin = GPIO_USB_C1_SRC_EN,
-			.pin_pol = 1,
-		},
-		.snk = {
-			.pin = GPIO_USB_C1_SNK_EN_L,
-			.pin_pol = 0,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_gpios) == CONFIG_USB_PD_PORT_MAX_COUNT);
-
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	/* Flash EC */
-	[I2C_CHAN_FLASH] = {
-		.name = "chan-A",
-		.port = IT83XX_I2C_CH_A,
-		.kbps = 100,
-		.scl = GPIO_I2C_A_SCL,
-		.sda = GPIO_I2C_A_SDA,
-	},
-	/*
-	 * Port-80 Display, Charger, Battery, IO-expanders, EEPROM,
-	 * IMVP9, AUX-rail, power-monitor.
-	 */
-	[I2C_CHAN_BATT_CHG] = {
-		.name = "batt_chg",
-		.port = IT83XX_I2C_CH_B,
-		.kbps = 100,
-		.scl = GPIO_I2C_B_SCL,
-		.sda = GPIO_I2C_B_SDA,
-	},
-	/* Retimers, PDs */
-	[I2C_CHAN_RETIMER] = {
-		.name = "retimer",
-		.port = IT83XX_I2C_CH_E,
-		.kbps = 100,
-		.scl = GPIO_I2C_E_SCL,
-		.sda = GPIO_I2C_E_SDA,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(i2c_ports) == I2C_CHAN_COUNT);
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* Charger Chips */
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-/******************************************************************************/
-/* PWROK signal configuration */
-/*
- * On JSLRVP the ALL_SYS_PWRGD, VCCST_PWRGD, PCH_PWROK, and SYS_PWROK
- * signals are handled by the board. No EC control needed.
- */
-const struct intel_x86_pwrok_signal pwrok_signal_assert_list[] = {};
-const int pwrok_signal_assert_count = ARRAY_SIZE(pwrok_signal_assert_list);
-
-const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[] = {};
-const int pwrok_signal_deassert_count = ARRAY_SIZE(pwrok_signal_assert_list);
-
-/*
- * Returns board information (board id[7:0] and Fab id[15:8]) on success
- * -1 on error.
- */
-int board_get_version(void)
-{
-	int fab_id;
-	int board_id;
-	int bom_id;
-
-	if (ioexpander_read_intelrvp_version(&fab_id, &board_id))
-		return -1;
-	/*
-	 * Port0: bit 1:0 - FAB ID(1:0) + 1
-	 * Port1: bit 7:5 - BOM ID(2:0)
-	 *        bit 4:0 - BOARD ID(4:0)
-	 */
-	fab_id = (fab_id & 0x03) + 1;
-	bom_id = ((board_id & 0xE0) >> 5);
-	board_id &= 0x1F;
-
-	CPRINTS("BID:0x%x, FID:0x%x, BOM:0x%x", board_id, fab_id, bom_id);
-
-	return board_id | (fab_id << 8);
-}
diff --git a/board/jslrvp_ite/board.h b/board/jslrvp_ite/board.h
deleted file mode 100644
index 2ac8afa8d9..0000000000
--- a/board/jslrvp_ite/board.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel Jasperlake RVP with ITE EC board specific configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define CONFIG_CHIPSET_JASPERLAKE
-#define GPIO_PG_EC_RSMRST_ODL		GPIO_RSMRST_L_PGOOD
-#define GPIO_PCH_DSW_PWROK		GPIO_EC_PCH_DSW_PWROK
-#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_ALL_SYS_PWRGD
-
-/* Fan features */
-#define CONFIG_FANS 1
-#define BOARD_FAN_MIN_RPM 3000
-#define BOARD_FAN_MAX_RPM 10000
-
-/* Temperature sensor */
-#define CONFIG_TEMP_SENSOR
-
-#include "baseboard.h"
-
-/* Charger */
-#define CONFIG_CHARGER_ISL9238
-
-/* DC Jack charge ports */
-#undef  CONFIG_DEDICATED_CHARGE_PORT_COUNT
-#define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1
-
-/* USB ports */
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define DEDICATED_CHARGE_PORT 2
-
-/* USB MUX */
-#define CONFIG_USB_MUX_ANX7440
-
-/* USB HPD */
-#define CONFIG_USB_PD_DP_HPD_GPIO
-
-/* Thermal configs */
-
-/* I2C ports */
-#define CONFIG_IT83XX_SMCLK2_ON_GPC7
-
-#define I2C_PORT_CHARGER	IT83XX_I2C_CH_B
-#define I2C_PORT_BATTERY	IT83XX_I2C_CH_B
-#define I2C_PORT_PCA9555_BOARD_ID_GPIO	IT83XX_I2C_CH_B
-#define I2C_PORT_PORT80		IT83XX_I2C_CH_B
-#define I2C_PORT_USB_MUX    IT83XX_I2C_CH_E
-
-#define I2C_ADDR_PCA9555_BOARD_ID_GPIO	0x22
-#define PORT80_I2C_ADDR			MAX695X_I2C_ADDR1_FLAGS
-
-#ifndef __ASSEMBLER__
-
-enum jslrvp_charge_ports {
-	TYPE_C_PORT_0,
-	TYPE_C_PORT_1,
-};
-
-enum jslrvp_i2c_channel {
-	I2C_CHAN_FLASH,
-	I2C_CHAN_BATT_CHG,
-	I2C_CHAN_RETIMER,
-	I2C_CHAN_COUNT,
-};
-
-/* Define max power */
-#define PD_MAX_POWER_MW        45000
-
-int board_get_version(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/jslrvp_ite/build.mk b/board/jslrvp_ite/build.mk
deleted file mode 100644
index 31f33208ba..0000000000
--- a/board/jslrvp_ite/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Intel Jasperlake RVP with ITE EC board specific configuration
-#
-
-#it8320
-CHIP:=it83xx
-CHIP_FAMILY:=it8320
-CHIP_VARIANT:=it8320dx
-BASEBOARD:=intelrvp
-
-board-y=board.o
diff --git a/board/jslrvp_ite/ec.tasklist b/board/jslrvp_ite/ec.tasklist
deleted file mode 100644
index 768211c95f..0000000000
--- a/board/jslrvp_ite/ec.tasklist
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel Jasperlake RVP with ITE EC board specific configuration.
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/jslrvp_ite/gpio.inc b/board/jslrvp_ite/gpio.inc
deleted file mode 100644
index 5c0219263e..0000000000
--- a/board/jslrvp_ite/gpio.inc
+++ /dev/null
@@ -1,184 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel Jasperlake RVP with ITE EC board specific configuration */
-
-/*
- * Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first.
- */
-
-/* Power sequencing interrupts */
-GPIO_INT(PG_EC_DSW_PWROK,	PIN(C, 0), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_SUS_L,	PIN(K, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(ALL_SYS_PWRGD,	PIN(F, 0), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(RSMRST_L_PGOOD,PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PCH_SLP_S0_L,	PIN(G, 6), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(PCH_SLP_S3_L,		PIN(F, 2), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-GPIO_INT(PCH_SLP_S4_L,		PIN(F, 3), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-
-/* Button interrupts */
-GPIO_INT(VOLUME_UP_L,	PIN(D, 5), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(VOLUME_DOWN_L,	PIN(D, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(LID_OPEN,	PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP, lid_interrupt)
-GPIO_INT(POWER_BUTTON_L,PIN(L, 3), GPIO_INT_BOTH, power_button_interrupt)
-
-GPIO_INT(AC_PRESENT,	PIN(A, 7), GPIO_INT_BOTH, extpower_interrupt)
-
-GPIO_INT(UART1_RX,	PIN(B, 0), GPIO_INT_FALLING, uart_deepsleep_interrupt)	/* UART1 RX input */
-
-GPIO_INT(WP_L,      PIN(I, 4), GPIO_INT_BOTH, switch_interrupt)     /* EC_WP_ODL */
-
-#ifdef CONFIG_HOSTCMD_ESPI
-/* enable 1.8v input of EC's espi_reset pin, and then this pin takes effect. */
-GPIO_INT(ESPI_RESET_L,	PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt) /* eSPI_reset# */
-#endif
-
-GPIO_INT(TABLET_MODE_L,	PIN(K, 1), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-
-/* DC Jack presence coming from +VADP_OUT */
-GPIO_INT(DC_JACK_PRESENT,   PIN(J, 2), GPIO_INT_BOTH, board_dc_jack_interrupt)
-
-/* Type-C interrupts */
-GPIO_INT(USB_C0_VBUS_INT,	PIN(L, 5), GPIO_INT_BOTH, tcpc_alert_event)
-GPIO_INT(USB_C1_VBUS_INT,	PIN(D, 4), GPIO_INT_BOTH, tcpc_alert_event)
-
-/* Power sequencing GPIOs */
-GPIO(CPU_PROCHOT,	PIN(B, 2), GPIO_INPUT)
-GPIO(SYS_RESET_L,	PIN(B, 6), GPIO_ODR_HIGH)
-GPIO(PCH_RSMRST_L,	PIN(C, 6), GPIO_OUT_LOW)
-GPIO(PCH_PWRBTN_L,	PIN(D, 0), GPIO_ODR_HIGH)
-GPIO(EC_SPI_OE_N,	PIN(I, 2), GPIO_OUT_LOW)
-/*
- * PCH_SYS_PWROK is an input, driven by the Silego chip. The common x86
- * power sequencing expects that PCH_SYS_PWROK is an output and will drive
- * this signal if GPIO_PCH_SYS_PWROK is configured. Map this pin as no-connect
- * so that state can be monitored using the console.
- */
-GPIO(NC_PCH_SYS_PWROK,	PIN(K, 4), GPIO_INPUT)
-GPIO(EN_PP5000, 	PIN(L, 4), GPIO_OUT_LOW)
-GPIO(EN_PP3300_A,	PIN(C, 3), GPIO_OUT_LOW)
-GPIO(EC_PCH_DSW_PWROK,	PIN(L, 6), GPIO_OUT_LOW)
-
-UNIMPLEMENTED(EN_VCCIO_EXT)
-
-/* Host communication GPIOs */
-GPIO(PCH_WAKE_L,	PIN(J, 0), GPIO_ODR_HIGH)
-#ifndef CONFIG_HOSTCMD_ESPI
-GPIO(PCH_PLTRST_L,	PIN(E, 3), GPIO_INPUT | GPIO_PULL_UP)
-#endif
-
-/* Battery present */
-GPIO(EC_BATT_PRES_L,	PIN(K, 0), GPIO_INPUT)
-
-/* Type-C GPIOs */
-GPIO(USB_C0_SRC_EN,	PIN(L, 1), GPIO_OUT_LOW)
-GPIO(USB_C0_SNK_EN_L,	PIN(H, 6), GPIO_ODR_LOW)
-GPIO(USB_C0_SRC_HI_ILIM, PIN(M, 6), GPIO_OUT_LOW)
-GPIO(USB_C0_DP_HPD,	PIN(E, 6), GPIO_OUT_LOW)
-GPIO(USB_C0_FRS_EN,	PIN(L, 7), GPIO_INPUT)
-
-GPIO(USB_C1_SRC_EN,	PIN(G, 1), GPIO_OUT_LOW)
-GPIO(USB_C1_SNK_EN_L,	PIN(I, 5), GPIO_ODR_LOW)
-GPIO(USB_C1_SRC_HI_ILIM, PIN(A, 0), GPIO_OUT_LOW)
-GPIO(USB_C1_DP_HPD,	PIN(D, 3), GPIO_OUT_LOW)
-GPIO(USB_C1_FRS_EN,	PIN(K, 5), GPIO_INPUT)
-
-/*
- * Type-C USB MUX GPIOs
- * TODO(b/146683781): drive initial level to low and
- * handle the low power mode
- */
-GPIO(USB_C0_LS_EN,		PIN(J, 1), GPIO_OUT_HIGH)
-GPIO(USB_C1_LS_EN,		PIN(C, 4), GPIO_OUT_HIGH)
-
-/* Type-C BC1.2 GPIOs */
-GPIO(USB_C0_BC12_CHG_DET_L,	PIN(A, 1), GPIO_INPUT)
-GPIO(USB_C0_BC12_VBUS_ON_ODL,	PIN(H, 4), GPIO_ODR_HIGH)
-
-GPIO(USB_C1_BC12_CHG_DET_L,	PIN(B, 7), GPIO_INPUT)
-GPIO(USB_C1_BC12_VBUS_ON_ODL,	PIN(J, 6), GPIO_ODR_HIGH)
-
-/* USB-A GPIOs */
-GPIO(USB_A_5V_EN,	PIN(K, 3), GPIO_INPUT)
-
-/* LED */
-GPIO(BAT_LED_GREEN_L,	PIN(A, 6), GPIO_OUT_HIGH)	/* LED_2_L */
-GPIO(AC_LED_GREEN_L,	PIN(A, 3), GPIO_OUT_HIGH)	/* LED_1_L */
-
-/* FAN control pins */
-GPIO(FAN_POWER_EN,	PIN(K, 6), GPIO_OUT_LOW)
-
-/* H1 pins */
-GPIO(CCD_MODE_ODL,	PIN(B, 5), GPIO_INPUT)
-GPIO(ENTERING_RW,	PIN(C, 5), GPIO_OUT_LOW)
-
-/* Used if Type-A ports have BC1.2 */
-GPIO(NC_USB_A_CHG_EN,		PIN(D, 1), GPIO_INPUT)
-
-/* Used if dead battery LDO present */
-GPIO(NC_USBC_LDO_ENABLE,	PIN(G, 2), GPIO_INPUT)
-
-/* Used with Discreate TBT and or with PD on RVP */
-GPIO(NC_TBT_C0_RESET_N,		PIN(KSO_H, 7), GPIO_INPUT)
-GPIO(NC_TBT_C1_RESET_N,		PIN(K, 7), GPIO_INPUT)
-GPIO(NC_USB_C0_RETIMER_ALRT,	PIN(I, 7), GPIO_INPUT)
-GPIO(NC_USB_C1_RETIMER_ALRT,	PIN(G, 0), GPIO_INPUT)
-
-/* Used if PMIC is used */
-GPIO(NC_PMIC_EN,		PIN(H, 3), GPIO_INPUT)
-
-/* Used if Base EC is present */
-GPIO(NC_EC_BASE_DET,		PIN(I, 3), GPIO_INPUT)
-
-#ifndef CONFIG_HOSTCMD_ESPI
-GPIO_INT(ESPI_RESET_L,	PIN(D, 2), GPIO_INPUT)
-#endif
-
-/* Unused pins */
-GPIO(NC_SUSWARN,		PIN(E, 1), GPIO_INPUT)
-GPIO(NC_SD_CARD_DETECT,		PIN(E, 5), GPIO_INPUT)
-GPIO(NC_BATT_DISABLE,		PIN(H, 0), GPIO_INPUT)
-GPIO(NC_SLP_S0_CS_N,		PIN(I, 0), GPIO_INPUT)
-
-/*
- * I2C pins should be configure as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-GPIO(I2C_A_SCL,	PIN(B, 3), GPIO_INPUT)
-GPIO(I2C_A_SDA,	PIN(B, 4), GPIO_INPUT)
-GPIO(I2C_B_SCL,	PIN(C, 1), GPIO_INPUT)
-GPIO(I2C_B_SDA,	PIN(C, 2), GPIO_INPUT)
-GPIO(I2C_C_SCL,	PIN(C, 7), GPIO_INPUT)
-GPIO(I2C_C_SDA,	PIN(F, 7), GPIO_INPUT)
-GPIO(I2C_E_SCL,	PIN(E, 0), GPIO_INPUT)
-GPIO(I2C_E_SDA,	PIN(E, 7), GPIO_INPUT)
-GPIO(I2C_F_SCL,	PIN(A, 4), GPIO_INPUT)
-GPIO(I2C_F_SDA,	PIN(A, 5), GPIO_INPUT)
-
-/* Alternate pins for I2C */
-ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C F SCL/SDA A4/A5 */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(4)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C A SCL/SDA B3/B4 */
-ALTERNATE(PIN_MASK(C, BIT(1) | BIT(2)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C B SCL/SDA C1/C2 */
-ALTERNATE(PIN_MASK(E, BIT(0) | BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C E SCL/SDA E0/E7 */
-ALTERNATE(PIN_MASK(C, BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C C SCL C7 */
-ALTERNATE(PIN_MASK(F, BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C C SDA F7 */
-
-/* Alternate pins for UART */
-ALTERNATE(PIN_MASK(B, BIT(0) | BIT(1)), GPIO_ALT_FUNC_DEFAULT, MODULE_UART, GPIO_PULL_UP) /* UART1 B0/B1 */
-
-/* Alternate pins for ADC */
-ALTERNATE(PIN_MASK(I, BIT(1) | BIT(6)), GPIO_ALT_FUNC_DEFAULT, MODULE_ADC, GPIO_FLAG_NONE)	/* ADC 1,6 -> I1,I6 */
-ALTERNATE(PIN_MASK(L, BIT(0) | BIT(2)), GPIO_ALT_FUNC_DEFAULT, MODULE_ADC, GPIO_FLAG_NONE)	/* ADC 13,15 -> L0,L2 */
-
-/* Alternate pins for FAN */
-ALTERNATE(PIN_MASK(A, BIT(2)), GPIO_ALT_FUNC_DEFAULT, MODULE_PWM, GPIO_FLAG_NONE)	/* PWM2 A2 */
-ALTERNATE(PIN_MASK(D, BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_PWM, GPIO_FLAG_NONE)	/* TACH1A D7 */
diff --git a/board/kakadu/board.c b/board/kakadu/board.c
index 47cf5ee3be..fa7ff1c09e 100644
--- a/board/kakadu/board.c
+++ b/board/kakadu/board.c
@@ -1,10 +1,9 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "button.h"
 #include "charge_manager.h"
 #include "charge_ramp.h"
@@ -14,7 +13,9 @@
 #include "chipset.h"
 #include "common.h"
 #include "console.h"
-#include "driver/accelgyro_lsm6dsm.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "driver/accelgyro_icm42607.h"
+#include "driver/accelgyro_icm_common.h"
 #include "driver/charger/rt946x.h"
 #include "driver/sync.h"
 #include "driver/tcpm/mt6370.h"
@@ -26,6 +27,7 @@
 #include "host_command.h"
 #include "i2c.h"
 #include "lid_switch.h"
+#include "panic.h"
 #include "power.h"
 #include "power_button.h"
 #include "pwm.h"
@@ -34,7 +36,7 @@
 #include "spi.h"
 #include "system.h"
 #include "task.h"
-#include "tcpm.h"
+#include "tcpm/tcpm.h"
 #include "timer.h"
 #include "usb_charge.h"
 #include "usb_mux.h"
@@ -42,8 +44,8 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
@@ -55,37 +57,46 @@ static void gauge_interrupt(enum gpio_signal signal)
 	task_wake(TASK_ID_CHARGER);
 }
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /******************************************************************************/
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] = {"BOARD_ID", 3300, 4096, 0, STM32_AIN(10)},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)},
-	[ADC_BATT_ID] = {"BATT_ID", 3300, 4096, 0, STM32_AIN(7)},
-	[ADC_POGO_ADC_INT_L] = {"POGO_ADC_INT_L", 3300, 4096, 0, STM32_AIN(6)},
+	[ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(10) },
+	[ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8) },
+	[ADC_BATT_ID] = { "BATT_ID", 3300, 4096, 0, STM32_AIN(7) },
+	[ADC_POGO_ADC_INT_L] = { "POGO_ADC_INT_L", 3300, 4096, 0,
+				 STM32_AIN(6) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /******************************************************************************/
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{"typec", 0, 400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"other", 1, 400, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
+	{ .name = "typec",
+	  .port = 0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "other",
+	  .port = 1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
 /* power signal list.  Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
+	{ GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" },
+	{ GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" },
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
 /******************************************************************************/
 /* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
+const struct spi_device_t spi_devices[] = {};
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
 /******************************************************************************/
@@ -101,13 +112,16 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 };
 
 struct mt6370_thermal_bound thermal_bound = {
-	.target = 90,
+	.target = 80,
 	.err = 4,
 };
 
-static void board_hpd_update(const struct usb_mux *me,
-			     int hpd_lvl, int hpd_irq)
+static void board_hpd_update(const struct usb_mux *me, mux_state_t mux_state,
+			     bool *ack_required)
 {
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
 	/*
 	 * svdm_dp_attention() did most of the work, we only need to notify
 	 * host here.
@@ -118,7 +132,7 @@ static void board_hpd_update(const struct usb_mux *me,
 __override const struct rt946x_init_setting *board_rt946x_init_setting(void)
 {
 	static const struct rt946x_init_setting battery_init_setting = {
-		.eoc_current = 500,
+		.eoc_current = 140,
 		.mivr = 4000,
 		.ircmp_vclamp = 32,
 		.ircmp_res = 25,
@@ -129,13 +143,16 @@ __override const struct rt946x_init_setting *board_rt946x_init_setting(void)
 	return &battery_init_setting;
 }
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_update,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+				.hpd_update = &board_hpd_update,
+			},
 	},
 };
 
@@ -173,7 +190,7 @@ int board_set_active_charge_port(int charge_port)
 		gpio_set_level(GPIO_EN_POGO_CHARGE_L, 0);
 		break;
 #endif
-	case CHARGE_PORT_NONE:
+	default:
 		/*
 		 * To ensure the fuel gauge (max17055) is always powered
 		 * even when battery is disconnected, keep VBAT rail on but
@@ -183,9 +200,6 @@ int board_set_active_charge_port(int charge_port)
 		gpio_set_level(GPIO_EN_USBC_CHARGE_L, 1);
 		charger_set_current(CHARGER_SOLO, 0);
 		break;
-	default:
-		panic("Invalid charge port\n");
-		break;
 	}
 
 	return EC_SUCCESS;
@@ -226,9 +240,8 @@ int extpower_is_present(void)
 	if (board_vbus_source_enabled(CHARGE_PORT_USB_C))
 		usb_c_extpower_present = 0;
 	else
-		usb_c_extpower_present = tcpm_check_vbus_level(
-							CHARGE_PORT_USB_C,
-							VBUS_PRESENT);
+		usb_c_extpower_present =
+			tcpm_check_vbus_level(CHARGE_PORT_USB_C, VBUS_PRESENT);
 
 	return usb_c_extpower_present;
 }
@@ -241,20 +254,8 @@ int pd_snk_is_vbus_provided(int port)
 	return rt946x_is_vbus_ready();
 }
 
-
-#define CHARGER_I2C_ADDR_FLAGS RT946X_ADDR_FLAGS
-
 static void board_init(void)
 {
-
-#ifdef SECTION_IS_RW
-	int val;
-	i2c_read8(I2C_PORT_CHARGER, CHARGER_I2C_ADDR_FLAGS,
-		RT946X_REG_CHGCTRL1, &val);
-	val &= RT946X_MASK_OPA_MODE;
-	i2c_write8(I2C_PORT_CHARGER, CHARGER_I2C_ADDR_FLAGS,
-		RT946X_REG_CHGCTRL1, (val | RT946X_MASK_STAT_EN));
-#endif
 	/* If the reset cause is external, pulse PMIC force reset. */
 	if (system_get_reset_flags() == EC_RESET_FLAG_RESET_PIN) {
 		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 0);
@@ -269,7 +270,7 @@ static void board_init(void)
 	gpio_enable_interrupt(GPIO_CHARGER_INT_ODL);
 
 #ifdef SECTION_IS_RW
-	/* Enable interrupts from LSM6DS3TR sensor. */
+	/* Enable interrupts from BMI160 sensor. */
 	gpio_enable_interrupt(GPIO_ACCEL_INT_ODL);
 
 	/* Enable interrupt for the camera vsync. */
@@ -300,18 +301,9 @@ static void board_rev_init(void)
 	 * Keep this pin defaults to P1 setting since that eMMC enabled with
 	 * High-Z stat.
 	 */
-
 	/* TODO */
 	/* Put initial code here for different EC board reversion */
-
-	/* Display bias settings. */
-	mt6370_db_set_voltages(6000, 5800, 5800);
-
-	/*
-	 * Enable MT6370 DB_POSVOUT/DB_NEGVOUT (controlled by _EN pins).
-	 */
-	mt6370_db_external_control(1);
-
+	return;
 }
 DECLARE_HOOK(HOOK_INIT, board_rev_init, HOOK_PRIO_INIT_ADC + 1);
 
@@ -325,13 +317,64 @@ void sensor_board_proc_double_tap(void)
 #ifndef VARIANT_KUKUI_NO_SENSORS
 static struct mutex g_lid_mutex;
 
-static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
+static struct bmi_drv_data_t g_bmi160_data;
+static struct icm_drv_data_t g_icm42607_data;
+
+enum lid_accelgyro_type {
+	LID_GYRO_NONE = 0,
+	LID_GYRO_BMI160 = 1,
+	LID_GYRO_ICM426XX = 2,
+};
+
+static enum lid_accelgyro_type lid_accelgyro_config;
 
 /* Matrix to rotate accelerometer into standard reference frame */
-static const mat33_fp_t lid_standard_ref = {
-	{0, FLOAT_TO_FP(1), 0},
-	{FLOAT_TO_FP(-1), 0, 0},
-	{0, 0, FLOAT_TO_FP(1)}
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
+
+const mat33_fp_t lid_standard_ref_icm42607 = { { 0, FLOAT_TO_FP(1), 0 },
+					       { FLOAT_TO_FP(-1), 0, 0 },
+					       { 0, 0, FLOAT_TO_FP(1) } };
+struct motion_sensor_t icm42607_lid_accel = {
+	 .name = "Accel",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_ICM42607,
+	 .type = MOTIONSENSE_TYPE_ACCEL,
+	 .location = MOTIONSENSE_LOC_LID,
+	 .drv = &icm42607_drv,
+	 .mutex = &g_lid_mutex,
+	 .drv_data = &g_icm42607_data,
+	 .port = I2C_PORT_ACCEL,
+	 .i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
+	 .default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
+	 .rot_standard_ref = &lid_standard_ref_icm42607,
+	 .min_frequency = ICM42607_ACCEL_MIN_FREQ,
+	 .max_frequency = ICM42607_ACCEL_MAX_FREQ,
+	 .config = {
+		 /* Enable accel in S0 */
+		 [SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		 },
+	 },
+};
+
+struct motion_sensor_t icm42607_lid_gyro = {
+	.name = "Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM42607,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_LID,
+	.drv = &icm42607_drv,
+	.mutex = &g_lid_mutex,
+	.drv_data = &g_icm42607_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &lid_standard_ref_icm42607,
+	.min_frequency = ICM42607_GYRO_MIN_FREQ,
+	.max_frequency = ICM42607_GYRO_MAX_FREQ,
 };
 
 struct motion_sensor_t motion_sensors[] = {
@@ -341,61 +384,103 @@ struct motion_sensor_t motion_sensors[] = {
 	 * DO NOT change the order of the following table.
 	 */
 	[LID_ACCEL] = {
-		.name = "Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-					    MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_ACCEL_INT_ODL,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-		.config = {
-		/* Enable accel in S0 */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 13000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-			},
-		},
+	 .name = "Accel",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_BMI160,
+	 .type = MOTIONSENSE_TYPE_ACCEL,
+	 .location = MOTIONSENSE_LOC_LID,
+	 .drv = &bmi160_drv,
+	 .mutex = &g_lid_mutex,
+	 .drv_data = &g_bmi160_data,
+	 .port = I2C_PORT_ACCEL,
+	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+	 .rot_standard_ref = &lid_standard_ref,
+	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
+	 .min_frequency = BMI_ACCEL_MIN_FREQ,
+	 .max_frequency = BMI_ACCEL_MAX_FREQ,
+	 .config = {
+		 /* Enable accel in S0 */
+		 [SENSOR_CONFIG_EC_S0] = {
+			 .odr = TAP_ODR,
+			 .ec_rate = 100 * MSEC,
+		 },
+		 /* For double tap detection */
+		 [SENSOR_CONFIG_EC_S3] = {
+			 .odr = TAP_ODR,
+			 .ec_rate = 100 * MSEC,
+		 },
+	 },
 	},
 	[LID_GYRO] = {
-		.name = "Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-					    MOTIONSENSE_TYPE_GYRO),
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
-		.rot_standard_ref = &lid_standard_ref,
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
+	 .name = "Gyro",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_BMI160,
+	 .type = MOTIONSENSE_TYPE_GYRO,
+	 .location = MOTIONSENSE_LOC_LID,
+	 .drv = &bmi160_drv,
+	 .mutex = &g_lid_mutex,
+	 .drv_data = &g_bmi160_data,
+	 .port = I2C_PORT_ACCEL,
+	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+	 .default_range = 1000, /* dps */
+	 .rot_standard_ref = &lid_standard_ref,
+	 .min_frequency = BMI_GYRO_MIN_FREQ,
+	 .max_frequency = BMI_GYRO_MAX_FREQ,
 	},
 	[VSYNC] = {
-		.name = "Camera vsync",
-		.active_mask = SENSOR_ACTIVE_S0,
-		.chip = MOTIONSENSE_CHIP_GPIO,
-		.type = MOTIONSENSE_TYPE_SYNC,
-		.location = MOTIONSENSE_LOC_CAMERA,
-		.drv = &sync_drv,
-		.default_range = 0,
-		.min_frequency = 0,
-		.max_frequency = 1,
+	 .name = "Camera vsync",
+	 .active_mask = SENSOR_ACTIVE_S0,
+	 .chip = MOTIONSENSE_CHIP_GPIO,
+	 .type = MOTIONSENSE_TYPE_SYNC,
+	 .location = MOTIONSENSE_LOC_CAMERA,
+	 .drv = &sync_drv,
+	 .default_range = 0,
+	 .min_frequency = 0,
+	 .max_frequency = 1,
 	},
 };
 const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+static void board_detect_motionsensor(void)
+{
+	int ret;
+	int val;
+
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return;
+	if (lid_accelgyro_config != LID_GYRO_NONE)
+		return;
+	/* Check base accelgyro chip */
+	ret = icm_read8(&icm42607_lid_accel, ICM42607_REG_WHO_AM_I, &val);
+	if (ret)
+		ccprints("Get ICM fail.");
+	if (val == ICM42607_CHIP_ICM42607P) {
+		motion_sensors[LID_ACCEL] = icm42607_lid_accel;
+		motion_sensors[LID_GYRO] = icm42607_lid_gyro;
+	}
+	lid_accelgyro_config = (val == ICM42607_CHIP_ICM42607P) ?
+				       LID_GYRO_ICM426XX :
+				       LID_GYRO_BMI160;
+	ccprints("LID Accelgyro: %s",
+		 (val == ICM42607_CHIP_ICM42607P) ? "ICM42607" : "BMI160");
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_detect_motionsensor,
+	     HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_INIT, board_detect_motionsensor, HOOK_PRIO_INIT_ADC + 2);
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	switch (lid_accelgyro_config) {
+	case LID_GYRO_ICM426XX:
+		icm42607_interrupt(signal);
+		break;
+	case LID_GYRO_BMI160:
+	default:
+		bmi160_interrupt(signal);
+		break;
+	}
+}
+
 #endif /* VARIANT_KUKUI_NO_SENSORS */
 
 /*
@@ -431,9 +516,8 @@ __override int board_charge_port_is_connected(int port)
 	return gpio_get_level(GPIO_POGO_VBUS_PRESENT);
 }
 
-__override
-void board_fill_source_power_info(int port,
-				  struct ec_response_usb_pd_power_info *r)
+__override void
+board_fill_source_power_info(int port, struct ec_response_usb_pd_power_info *r)
 {
 	r->meas.voltage_now = 3300;
 	r->meas.voltage_max = 3300;
@@ -442,3 +526,14 @@ void board_fill_source_power_info(int port,
 	r->max_power = r->meas.voltage_now * r->meas.current_max;
 }
 
+/* b/207456334: bugged reserved bits causes device not charging */
+static void mt6370_reg_fix(void)
+{
+	i2c_update8(chg_chips[CHARGER_SOLO].i2c_port,
+		    chg_chips[CHARGER_SOLO].i2c_addr_flags, RT946X_REG_CHGCTRL1,
+		    BIT(3) | BIT(5), MASK_CLR);
+	i2c_update8(chg_chips[CHARGER_SOLO].i2c_port,
+		    chg_chips[CHARGER_SOLO].i2c_addr_flags, RT946X_REG_CHGCTRL2,
+		    BIT(5) | BIT(RT946X_SHIFT_BATDET_DIS_DLY), MASK_CLR);
+}
+DECLARE_HOOK(HOOK_INIT, mt6370_reg_fix, HOOK_PRIO_DEFAULT);
diff --git a/board/kakadu/board.h b/board/kakadu/board.h
index 5bb59705fb..5d64af2f6b 100644
--- a/board/kakadu/board.h
+++ b/board/kakadu/board.h
@@ -1,16 +1,19 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-/* Configuration for kakadu */
+/* Configuration for Kakadu */
 
 #ifndef __CROS_EC_BOARD_H
 #define __CROS_EC_BOARD_H
 
-#define VARIANT_KUKUI_BATTERY_MAX17055
-#define VARIANT_KUKUI_CHARGER_MT6370
+#define BQ27541_ADDR 0x55
+#define VARIANT_KUKUI_BATTERY_BQ27541
 #define VARIANT_KUKUI_POGO_KEYBOARD
+
+#define VARIANT_KUKUI_CHARGER_MT6370
+#define VARIANT_KUKUI_EC_STM32F098
 #define VARIANT_KUKUI_TABLET_PWRBTN
 
 #ifndef SECTION_IS_RW
@@ -21,50 +24,42 @@
 
 #define CONFIG_USB_MUX_IT5205
 #define CONFIG_VOLUME_BUTTONS
+#define CONFIG_USB_MUX_RUNTIME_CONFIG
 
 /* Battery */
-#define BATTERY_DESIRED_CHARGING_CURRENT    3500  /* mA */
+#define BATTERY_DESIRED_CHARGING_CURRENT 3500 /* mA */
 
 #define CONFIG_CHARGER_MT6370_BACKLIGHT
-#ifdef BOARD_KAKADU
-#define CHARGER_LIMIT_TIMEOUT_HOURS 48
-#define CHARGER_LIMIT_TIMEOUT_HOURS_TEMP 2
-#endif
 
 /* Motion Sensors */
 #ifdef SECTION_IS_RW
-#define CONFIG_ACCELGYRO_LSM6DSM
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
+#define CONFIG_ACCELGYRO_BMI160
+#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
+#define CONFIG_ACCELGYRO_ICM42607 /* Base accel second source*/
+#define CONFIG_ACCELGYRO_ICM42607_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
 
 /* Camera VSYNC */
 #define CONFIG_SYNC
 #define CONFIG_SYNC_COMMAND
-#define CONFIG_SYNC_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
+#define CONFIG_SYNC_INT_EVENT TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
 #endif /* SECTION_IS_RW */
 
 /* I2C ports */
-#define I2C_PORT_CHARGER  0
-#define I2C_PORT_TCPC0    0
-#define I2C_PORT_USB_MUX  0
-#define I2C_PORT_BATTERY  1
+#define I2C_PORT_CHARGER 0
+#define I2C_PORT_TCPC0 0
+#define I2C_PORT_USB_MUX 0
+#define I2C_PORT_BATTERY 1
 #define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
-#define I2C_PORT_ACCEL    1
-#define I2C_PORT_BC12     1
-#define I2C_PORT_ALS      1
+#define I2C_PORT_ACCEL 1
+#define I2C_PORT_BC12 1
 
 /* Route sbs host requests to virtual battery driver */
 #define VIRTUAL_BATTERY_ADDR_FLAGS 0x0B
 
-/* Define the host events which are allowed to wakeup AP in S3. */
-#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \
-		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
-
 /* MKBP */
+#define CONFIG_MKBP_INPUT_DEVICES
 #define CONFIG_MKBP_EVENT
 #define CONFIG_MKBP_EVENT_WAKEUP_MASK \
 	(BIT(EC_MKBP_EVENT_SENSOR_FIFO) | BIT(EC_MKBP_EVENT_HOST_EVENT))
@@ -113,10 +108,19 @@ void emmc_cmd_interrupt(enum gpio_signal signal);
 
 void board_reset_pd_mcu(void);
 int board_get_version(void);
-int board_is_sourcing_vbus(int port);
 void pogo_adc_interrupt(enum gpio_signal signal);
 int board_discharge_on_ac(int enable);
-
+void motion_interrupt(enum gpio_signal signal);
+
+/* Enable double tap detection */
+#define CONFIG_GESTURE_DETECTION
+#define CONFIG_GESTURE_SENSOR_DOUBLE_TAP
+#define CONFIG_GESTURE_TAP_SENSOR 0
+#define CONFIG_GESTURE_SENSOR_DOUBLE_TAP_FOR_HOST
+#define CONFIG_GESTURE_SAMPLING_INTERVAL_MS 5
+#define CONFIG_GESTURE_TAP_THRES_MG 100
+#define CONFIG_GESTURE_TAP_MAX_INTERSTICE_T 500
+#define CONFIG_GESTURE_DETECTION_MASK BIT(CONFIG_GESTURE_TAP_SENSOR)
 
 #endif /* !__ASSEMBLER__ */
 
diff --git a/board/kakadu/build.mk b/board/kakadu/build.mk
index 7a3953b8bb..52ee1b3354 100644
--- a/board/kakadu/build.mk
+++ b/board/kakadu/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/kakadu/ec.tasklist b/board/kakadu/ec.tasklist
index fc26f445b2..8be28c373d 100644
--- a/board/kakadu/ec.tasklist
+++ b/board/kakadu/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/kakadu/gpio.inc b/board/kakadu/gpio.inc
index 308520ceda..6f494a9388 100644
--- a/board/kakadu/gpio.inc
+++ b/board/kakadu/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -30,7 +30,7 @@ GPIO_INT(AP_EC_WATCHDOG_L,  PIN(C, 2),  GPIO_INT_FALLING,
          chipset_watchdog_interrupt)
 
 GPIO_INT_RW(ACCEL_INT_ODL,  PIN(A, 4), GPIO_INT_FALLING | GPIO_SEL_1P8V | GPIO_PULL_UP,
-         lsm6dsm_interrupt)
+         motion_interrupt)
 GPIO_INT(CHARGER_INT_ODL,   PIN(C, 13), GPIO_INT_FALLING | GPIO_PULL_UP,
          rt946x_interrupt)
 GPIO_INT_RO(EMMC_CMD,       PIN(B, 15), GPIO_INT_FALLING,
@@ -48,8 +48,10 @@ GPIO_INT(POGO_ADC_INT_L,    PIN(A, 6),  GPIO_INT_BOTH,
 
 /* unused */
 GPIO(POGO_VBUS_PRESENT, PIN(A, 14), GPIO_INPUT)
-/* To support Apple dongle b/155242849 */
-GPIO(USB_C0_VCONN_EN_OD, PIN(C, 14), GPIO_ODR_HIGH)
+/* unused after board rev 5 */
+GPIO(USB_C0_DP_POLARITY,   PIN(C, 14), GPIO_INPUT)
+GPIO(USB_C0_DP_OE_L,       PIN(A, 5),  GPIO_INPUT)
+
 
 /* Reset pins */
 GPIO(AP_SYS_RST_L,         PIN(C, 11), GPIO_OUT_LOW)
diff --git a/board/kakadu/led.c b/board/kakadu/led.c
index 3931c392e7..d652563378 100644
--- a/board/kakadu/led.c
+++ b/board/kakadu/led.c
@@ -1,8 +1,8 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
- * Battery LED control for kakadu board.
+ * Battery LED control for Kakadu board.
  */
 
 #include "battery.h"
@@ -10,62 +10,123 @@
 #include "driver/charger/rt946x.h"
 #include "hooks.h"
 #include "led_common.h"
+#include "power.h"
 
 const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-static enum charge_state prv_chstate = PWR_STATE_INIT;
+#define LED_OFF MT6370_LED_ID_OFF
+#define LED_AMBER MT6370_LED_ID1
+#define LED_WHITE MT6370_LED_ID2
 
-#define LED_OFF		MT6370_LED_ID_OFF
-#define LED_RED		MT6370_LED_ID1
-#define LED_GREEN	MT6370_LED_ID2
-
-#define LED_MASK_OFF	0
-#define LED_MASK_RED	MT6370_MASK_RGB_ISNK1DIM_EN
-#define LED_MASK_GREEN	MT6370_MASK_RGB_ISNK2DIM_EN
+#define LED_MASK_OFF 0
+#define LED_MASK_AMBER MT6370_MASK_RGB_ISNK1DIM_EN
+#define LED_MASK_WHITE MT6370_MASK_RGB_ISNK2DIM_EN
 
 static void kakadu_led_set_battery(void)
 {
-	enum charge_state chstate;
-	static uint8_t prv_r, prv_g;
+	enum led_pwr_state chstate;
+	enum power_state powerstate;
+	static uint8_t prv_white, prv_amber;
+	static uint8_t time_cnt;
 	uint8_t br[EC_LED_COLOR_COUNT] = { 0 };
 
-	chstate = charge_get_state();
-
-	if (prv_chstate == chstate &&
-		chstate != PWR_STATE_DISCHARGE)
-		return;
-
-	prv_chstate = chstate;
+	chstate = led_pwr_get_state();
+	powerstate = power_get_state();
 
 	switch (chstate) {
-	case PWR_STATE_CHARGE:
-		br[EC_LED_COLOR_GREEN] = 255;
-		br[EC_LED_COLOR_RED] = 255;
-		break;
-	case PWR_STATE_DISCHARGE:
-		/* real battery SoC 5%*/
-		if (charge_get_percent() <= 5)
-			br[EC_LED_COLOR_RED] = 255;
+	case LED_PWRS_CHARGE:
+	case LED_PWRS_CHARGE_NEAR_FULL:
+		if (charge_get_percent() < 94) {
+			br[EC_LED_COLOR_AMBER] = 1;
+			br[EC_LED_COLOR_WHITE] = 0;
+			break;
+		}
+		br[EC_LED_COLOR_WHITE] = 1;
+		br[EC_LED_COLOR_AMBER] = 0;
 		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		br[EC_LED_COLOR_GREEN] = 255;
+	case LED_PWRS_DISCHARGE:
+		if (powerstate == POWER_S0) {
+			/* display SoC 10% = real battery SoC 13%*/
+			if (charge_get_percent() < 14) {
+				if (time_cnt < 1) {
+					time_cnt++;
+					br[EC_LED_COLOR_WHITE] = 0;
+					br[EC_LED_COLOR_AMBER] = 1;
+				} else {
+					time_cnt++;
+					br[EC_LED_COLOR_WHITE] = 0;
+					br[EC_LED_COLOR_AMBER] = 0;
+					if (time_cnt > 3)
+						time_cnt = 0;
+				}
+				break;
+			}
+			br[EC_LED_COLOR_WHITE] = 1;
+			br[EC_LED_COLOR_AMBER] = 0;
+			break;
+		} else if (powerstate == POWER_S3) {
+			if (time_cnt < 2) {
+				time_cnt++;
+				br[EC_LED_COLOR_WHITE] = 1;
+				br[EC_LED_COLOR_AMBER] = 0;
+			} else {
+				time_cnt++;
+				br[EC_LED_COLOR_WHITE] = 0;
+				br[EC_LED_COLOR_AMBER] = 0;
+				if (time_cnt > 3)
+					time_cnt = 0;
+			}
+			break;
+		} else if (powerstate == POWER_S5 || powerstate == POWER_G3) {
+			br[EC_LED_COLOR_WHITE] = 0;
+			br[EC_LED_COLOR_AMBER] = 0;
+		}
 		break;
-	case PWR_STATE_ERROR:
-		br[EC_LED_COLOR_RED] = 255;
+	case LED_PWRS_ERROR:
+		if (powerstate == POWER_S0) {
+			if (time_cnt < 1) {
+				time_cnt++;
+				br[EC_LED_COLOR_WHITE] = 0;
+				br[EC_LED_COLOR_AMBER] = 1;
+			} else {
+				time_cnt++;
+				br[EC_LED_COLOR_WHITE] = 0;
+				br[EC_LED_COLOR_AMBER] = 0;
+				if (time_cnt > 1)
+					time_cnt = 0;
+			}
+			break;
+		} else if (powerstate == POWER_S3) {
+			if (time_cnt < 2) {
+				time_cnt++;
+				br[EC_LED_COLOR_WHITE] = 1;
+				br[EC_LED_COLOR_AMBER] = 0;
+			} else {
+				time_cnt++;
+				br[EC_LED_COLOR_WHITE] = 0;
+				br[EC_LED_COLOR_AMBER] = 0;
+				if (time_cnt > 3)
+					time_cnt = 0;
+			}
+			break;
+		} else if (powerstate == POWER_S5 || powerstate == POWER_G3) {
+			br[EC_LED_COLOR_WHITE] = 0;
+			br[EC_LED_COLOR_AMBER] = 0;
+		}
 		break;
 	default:
 		/* Other states don't alter LED behavior */
 		return;
 	}
 
-	if (prv_r == br[EC_LED_COLOR_RED] &&
-	    prv_g == br[EC_LED_COLOR_GREEN])
+	if (prv_white == br[EC_LED_COLOR_WHITE] &&
+	    prv_amber == br[EC_LED_COLOR_AMBER])
 		return;
 
-	prv_r = br[EC_LED_COLOR_RED];
-	prv_g = br[EC_LED_COLOR_GREEN];
+	prv_white = br[EC_LED_COLOR_WHITE];
+	prv_amber = br[EC_LED_COLOR_AMBER];
 	led_set_brightness(EC_LED_ID_BATTERY_LED, br);
 }
 
@@ -74,50 +135,40 @@ void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
 	if (led_id != EC_LED_ID_BATTERY_LED)
 		return;
 
-	brightness_range[EC_LED_COLOR_RED] = MT6370_LED_BRIGHTNESS_MAX;
-	brightness_range[EC_LED_COLOR_GREEN] = MT6370_LED_BRIGHTNESS_MAX;
+	brightness_range[EC_LED_COLOR_WHITE] = MT6370_LED_BRIGHTNESS_MAX;
+	brightness_range[EC_LED_COLOR_AMBER] = MT6370_LED_BRIGHTNESS_MAX;
 }
 
 int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 {
-	uint8_t red, green;
+	uint8_t white, amber;
 
 	if (led_id != EC_LED_ID_BATTERY_LED)
 		return EC_ERROR_INVAL;
 
-	red = brightness[EC_LED_COLOR_RED];
-	green = brightness[EC_LED_COLOR_GREEN];
+	white = brightness[EC_LED_COLOR_WHITE];
+	amber = brightness[EC_LED_COLOR_AMBER];
 
-	mt6370_led_set_brightness(LED_RED, red);
-	mt6370_led_set_brightness(LED_GREEN, green);
+	mt6370_led_set_brightness(LED_WHITE, white);
+	mt6370_led_set_brightness(LED_AMBER, amber);
 
 	/* Enables LED sink power if necessary. */
-	mt6370_led_set_color((red ? LED_MASK_RED : 0) |
-			     (green ? LED_MASK_GREEN : 0));
+	mt6370_led_set_color((white ? LED_MASK_WHITE : 0) |
+			     (amber ? LED_MASK_AMBER : 0));
 	return EC_SUCCESS;
 }
 
-/*
- * Reset prv_chstate so that led can be updated immediately once
- * auto-controlled.
- */
-static void led_reset_auto_control(void)
-{
-	prv_chstate = PWR_STATE_INIT;
-}
-
 static void kakadu_led_init(void)
 {
 	const enum mt6370_led_dim_mode dim = MT6370_LED_DIM_MODE_PWM;
 	const enum mt6370_led_pwm_freq freq = MT6370_LED_PWM_FREQ1000;
-
 	mt6370_led_set_color(0);
-	mt6370_led_set_dim_mode(LED_RED, dim);
-	mt6370_led_set_dim_mode(LED_GREEN, dim);
-	mt6370_led_set_pwm_frequency(LED_RED, freq);
-	mt6370_led_set_pwm_frequency(LED_GREEN, freq);
-	mt6370_led_set_pwm_dim_duty(LED_RED, 12);
-	mt6370_led_set_pwm_dim_duty(LED_GREEN, 31);
+	mt6370_led_set_dim_mode(LED_WHITE, dim);
+	mt6370_led_set_dim_mode(LED_AMBER, dim);
+	mt6370_led_set_pwm_frequency(LED_WHITE, freq);
+	mt6370_led_set_pwm_frequency(LED_AMBER, freq);
+	mt6370_led_set_pwm_dim_duty(LED_WHITE, 255);
+	mt6370_led_set_pwm_dim_duty(LED_AMBER, 255);
 }
 DECLARE_HOOK(HOOK_INIT, kakadu_led_init, HOOK_PRIO_DEFAULT);
 
@@ -126,8 +177,6 @@ static void led_second(void)
 {
 	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
 		kakadu_led_set_battery();
-	else
-		led_reset_auto_control();
 }
 DECLARE_HOOK(HOOK_SECOND, led_second, HOOK_PRIO_DEFAULT);
 
@@ -140,13 +189,12 @@ __override void led_control(enum ec_led_id led_id, enum ec_led_state state)
 		return;
 
 	if (state == LED_STATE_RESET) {
-		led_reset_auto_control();
 		led_auto_control(EC_LED_ID_BATTERY_LED, 1);
 		return;
 	}
 
 	if (state)
-		br[EC_LED_COLOR_GREEN] = 1;
+		br[EC_LED_COLOR_WHITE] = 1;
 
 	led_auto_control(EC_LED_ID_BATTERY_LED, 0);
 	led_set_brightness(EC_LED_ID_BATTERY_LED, br);
diff --git a/board/kakadu/vif_override.xml b/board/kakadu/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/kakadu/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/kano/battery.c b/board/kano/battery.c
new file mode 100644
index 0000000000..0b1d956173
--- /dev/null
+++ b/board/kano/battery.c
@@ -0,0 +1,67 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "common.h"
+#include "compile_time_macros.h"
+
+/*
+ * Battery info for all Kano battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	/* LGC AP19B8M Battery Information */
+	[BATTERY_AP19B8M] = {
+		.fuel_gauge = {
+			.manuf_name = "LGC KT0030G024",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.reg_addr = 0x43,
+				.reg_mask = 0x0001,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0002,
+				.cfet_off_val = 0x0000,
+			}
+		},
+		.batt_info = {
+			.voltage_max          = 13350,
+			.voltage_normal       = 11610,
+			.voltage_min          = 9000,
+			.precharge_current    = 256,
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 50,
+			.charging_min_c       = 0,
+			.charging_max_c       = 60,
+			.discharging_min_c    = -20,
+			.discharging_max_c    = 75,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_AP19B8M;
diff --git a/board/kano/board.c b/board/kano/board.c
new file mode 100644
index 0000000000..0d40a655bb
--- /dev/null
+++ b/board/kano/board.c
@@ -0,0 +1,121 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "button.h"
+#include "charge_ramp.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "registers.h"
+#include "switch.h"
+#include "tablet_mode.h"
+#include "throttle_ap.h"
+#include "usbc_config.h"
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* Console output macros */
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+
+/******************************************************************************/
+/* USB-A charging control */
+
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_PP5000_USBA_R,
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
+
+/* Called on AP S3 -> S0 transition */
+static void board_chipset_resume(void)
+{
+	/* Allow keyboard backlight to be enabled */
+
+	gpio_set_level(GPIO_EC_KB_BL_EN_L, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S0 -> S3 transition */
+static void board_chipset_suspend(void)
+{
+	/* Turn off the keyboard backlight if it's on. */
+
+	gpio_set_level(GPIO_EC_KB_BL_EN_L, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
+
+#ifdef CONFIG_CHARGE_RAMP_SW
+
+/*
+ * TODO(b/181508008): tune this threshold
+ */
+
+#define BC12_MIN_VOLTAGE 4400
+
+/**
+ * Return true if VBUS is too low
+ */
+int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
+{
+	int voltage;
+
+	if (charger_get_vbus_voltage(port, &voltage))
+		voltage = 0;
+
+	if (voltage == 0) {
+		CPRINTS("%s: must be disconnected", __func__);
+		return 1;
+	}
+
+	if (voltage < BC12_MIN_VOLTAGE) {
+		CPRINTS("%s: port %d: vbus %d lower than %d", __func__, port,
+			voltage, BC12_MIN_VOLTAGE);
+		return 1;
+	}
+
+	return 0;
+}
+
+#endif /* CONFIG_CHARGE_RAMP_SW */
+
+enum battery_present battery_hw_present(void)
+{
+	enum gpio_signal batt_pres;
+
+	batt_pres = GPIO_EC_BATT_PRES_ODL;
+
+	/* The GPIO is low when the battery is physically present */
+	return gpio_get_level(batt_pres) ? BP_NO : BP_YES;
+}
+
+/* keyboard factory test */
+#ifdef CONFIG_KEYBOARD_FACTORY_TEST
+/*
+ * We have total 30 pins for keyboard connecter {-1, -1} mean
+ * the N/A pin that don't consider it and reserve index 0 area
+ * that we don't have pin 0.
+ */
+const int keyboard_factory_scan_pins[][2] = {
+	{ -1, -1 }, { 0, 5 },	{ 1, 1 }, { 1, 0 },   { 0, 6 },	  { 0, 7 },
+	{ -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 },   { -1, -1 }, { 1, 6 },
+	{ 1, 7 },   { 3, 1 },	{ 2, 0 }, { 1, 5 },   { 2, 6 },	  { 2, 7 },
+	{ 2, 1 },   { 2, 4 },	{ 2, 5 }, { 1, 2 },   { 2, 3 },	  { 2, 2 },
+	{ 3, 0 },   { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 },	  { -1, -1 },
+	{ -1, -1 },
+};
+
+const int keyboard_factory_scan_pins_used =
+	ARRAY_SIZE(keyboard_factory_scan_pins);
+#endif
diff --git a/board/kano/board.h b/board/kano/board.h
new file mode 100644
index 0000000000..156df67af0
--- /dev/null
+++ b/board/kano/board.h
@@ -0,0 +1,227 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Kano board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "compile_time_macros.h"
+
+/* Baseboard features */
+#include "baseboard.h"
+
+/*
+ * This will happen automatically on NPCX9 ES2 and later. Do not remove
+ * until we can confirm all earlier chips are out of service.
+ */
+#define CONFIG_HIBERNATE_PSL_VCC1_RST_WAKEUP
+
+#define CONFIG_MP2964
+
+/* LED */
+#define CONFIG_LED_ONOFF_STATES
+
+/* Sensors */
+#define CONFIG_ACCELGYRO_ICM426XX /* Base accel */
+#define CONFIG_ACCELGYRO_ICM_COMM_I2C
+#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+#define CONFIG_ACCELGYRO_BMI260
+#define CONFIG_ACCELGYRO_BMI260_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+/* Enable sensor fifo, must also define the _SIZE and _THRES */
+#define CONFIG_ACCEL_FIFO
+/* FIFO size is in power of 2. */
+#define CONFIG_ACCEL_FIFO_SIZE 256
+/* Depends on how fast the AP boots and typical ODRs */
+#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
+
+/* Sensors without hardware FIFO are in forced mode */
+#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
+
+/* Lid accel */
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_UPDATE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+#define CONFIG_ACCEL_KX022
+#define CONFIG_ACCEL_BMA4XX
+
+/* Sensor console commands */
+#define CONFIG_CMD_ACCELS
+#define CONFIG_CMD_ACCEL_INFO
+
+/* Keyboard */
+#define CONFIG_KEYBOARD_VIVALDI
+#define CONFIG_KEYBOARD_REFRESH_ROW3
+#define CONFIG_KEYBOARD_FACTORY_TEST
+
+/* USB Type A Features */
+#define USB_PORT_COUNT 1
+#define CONFIG_USB_PORT_POWER_DUMB
+
+/* USB Type C and USB PD defines */
+#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
+
+#define CONFIG_USBC_RETIMER_INTEL_BB
+
+#define CONFIG_USBC_PPC_SYV682X
+
+#undef CONFIG_USB_PD_TCPM_NCT38XX
+#define CONFIG_USB_PD_TCPM_RT1715
+
+/* TODO: b/177608416 - measure and check these values on brya */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
+
+/*
+ * Passive USB-C cables only support up to 60W.
+ */
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
+
+/*
+ * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
+ * signal.
+ */
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
+
+/* System has back-lit keyboard */
+#define CONFIG_PWM_KBLIGHT
+
+/* I2C Bus Configuration */
+
+#define I2C_PORT_ACCEL NPCX_I2C_PORT0_0
+
+#define I2C_PORT_USB_C0_C2_TCPC NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1
+
+#define I2C_PORT_USB_C0_C2_PPC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1
+
+#define I2C_PORT_USB_C0_C2_BC12 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1
+
+#define I2C_PORT_USB_C0_C2_MUX NPCX_I2C_PORT3_0
+#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1
+
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+
+#define I2C_ADDR_MP2964_FLAGS 0x20
+
+/*
+ * see b/174768555#comment22
+ */
+#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x54
+/* SOC facing Burnside Bridge retimer */
+#define USBC_PORT_C1_SOC_BB_RETIMER_I2C_ADDR 0x55
+/* Type-C connector facing Burnside Bridge retimer */
+#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x56
+
+/* Enabling Thunderbolt-compatible mode */
+#define CONFIG_USB_PD_TBT_COMPAT_MODE
+
+/* Enabling USB4 mode */
+#define CONFIG_USB_PD_USB4
+
+/* Retimer */
+#define CONFIG_USBC_RETIMER_FW_UPDATE
+
+/* Thermal features */
+#define CONFIG_THERMISTOR
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_TEMP_SENSOR_POWER
+#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
+
+#define CONFIG_FANS FAN_CH_COUNT
+
+/* Charger defines */
+#define CONFIG_CHARGER_ISL9241
+#define CONFIG_CHARGE_RAMP_SW
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h" /* needed by registers.h */
+#include "registers.h"
+#include "usbc_config.h"
+
+enum adc_channel {
+	ADC_TEMP_SENSOR_1_DDR_SOC,
+	ADC_TEMP_SENSOR_2_FAN,
+	ADC_TEMP_SENSOR_3_CHARGER,
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1_DDR_SOC,
+	TEMP_SENSOR_2_FAN,
+	TEMP_SENSOR_3_CHARGER,
+	TEMP_SENSOR_COUNT
+};
+
+enum sensor_id { LID_ACCEL = 0, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
+
+enum battery_type { BATTERY_AP19B8M, BATTERY_TYPE_COUNT };
+
+enum pwm_channel {
+	PWM_CH_KBLIGHT = 0, /* PWM3 */
+	PWM_CH_FAN, /* PWM5 */
+	PWM_CH_COUNT
+};
+
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT };
+
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT };
+
+void motion_interrupt(enum gpio_signal signal);
+
+#ifdef CONFIG_KEYBOARD_FACTORY_TEST
+extern const int keyboard_factory_scan_pins[][2];
+extern const int keyboard_factory_scan_pins_used;
+#endif
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/kano/build.mk b/board/kano/build.mk
new file mode 100644
index 0000000000..0393829e6e
--- /dev/null
+++ b/board/kano/build.mk
@@ -0,0 +1,25 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Brya board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx9
+CHIP_VARIANT:=npcx9m3f
+BASEBOARD:=brya
+
+board-y=
+board-y+=battery.o
+board-y+=board.o
+board-y+=charger.o
+board-y+=fans.o
+board-y+=fw_config.o
+board-y+=i2c.o
+board-y+=keyboard.o
+board-y+=led.o
+board-y+=pwm.o
+board-y+=sensors.o
+board-y+=usbc_config.o
diff --git a/board/kano/charger.c b/board/kano/charger.c
new file mode 100644
index 0000000000..b86d92965b
--- /dev/null
+++ b/board/kano/charger.c
@@ -0,0 +1,80 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/charger/isl9241.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/* Charger Chip Configuration */
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = ISL9241_ADDR_FLAGS,
+		.drv = &isl9241_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CHARGER_NUM);
+
+int board_set_active_charge_port(int port)
+{
+	int is_valid_port = board_is_usb_pd_port_present(port);
+	int i;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTSUSB("Disabling all charger ports");
+
+		/* Disable all ports. */
+		for (i = 0; i < ppc_cnt; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (ppc_vbus_sink_enable(i, 0))
+				CPRINTSUSB("Disabling C%d as sink failed.", i);
+		}
+
+		return EC_SUCCESS;
+	} else if (!is_valid_port) {
+		return EC_ERROR_INVAL;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (ppc_is_sourcing_vbus(port)) {
+		CPRINTFUSB("Skip enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTSUSB("New charge port: C%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < ppc_cnt; i++) {
+		if (i == port)
+			continue;
+
+		if (ppc_vbus_sink_enable(i, 0))
+			CPRINTSUSB("C%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTSUSB("C%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/board/kano/ec.tasklist b/board/kano/ec.tasklist
new file mode 100644
index 0000000000..64edf7bf2e
--- /dev/null
+++ b/board/kano/ec.tasklist
@@ -0,0 +1,30 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ *
+ * USB_CHG_Px tasks must be contiguous (see USB_CHG_PORT_TO_TASK_ID(x)).
+ * PD_Cx tasks must be contiguous (see PD_PORT_TO_TASK_ID(x))
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, HOOKS_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, BASEBOARD_CHG_RAMP_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, BASEBOARD_CHARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, BASEBOARD_CHIPSET_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, CONSOLE_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, BASEBOARD_POWERBTN_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_shared_alert_task, (BIT(2) | BIT(0)), BASEBOARD_PD_INT_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, BASEBOARD_PD_INT_TASK_STACK_SIZE)
diff --git a/board/kano/fans.c b/board/kano/fans.c
new file mode 100644
index 0000000000..4ae6edf1c3
--- /dev/null
+++ b/board/kano/fans.c
@@ -0,0 +1,50 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Physical fans. These are logically separate from pwm_channels. */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "fan.h"
+#include "fan_chip.h"
+#include "hooks.h"
+#include "pwm.h"
+
+/* MFT channels. These are logically separate from pwm_channels. */
+const struct mft_t mft_channels[] = {
+	[MFT_CH_0] = {
+		.module = NPCX_MFT_MODULE_1,
+		.clk_src = TCKC_LFCLK,
+		.pwm_id = PWM_CH_FAN,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
+
+static const struct fan_conf fan_conf_0 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
+	.pgood_gpio = -1,
+	.enable_gpio = GPIO_EN_PP5000_FAN,
+};
+
+/*
+ * TOOD(b/180681346): need to update for real fan
+ *
+ * Prototype fan spins at about 7200 RPM at 100% PWM.
+ * Set minimum at around 30% PWM.
+ */
+static const struct fan_rpm fan_rpm_0 = {
+	.rpm_min = 2400,
+	.rpm_start = 2400,
+	.rpm_max = 6000,
+};
+
+const struct fan_t fans[FAN_CH_COUNT] = {
+	[FAN_CH_0] = {
+		.conf = &fan_conf_0,
+		.rpm = &fan_rpm_0,
+	},
+};
diff --git a/board/kano/fw_config.c b/board/kano/fw_config.c
new file mode 100644
index 0000000000..f04fd0063b
--- /dev/null
+++ b/board/kano/fw_config.c
@@ -0,0 +1,61 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "fw_config.h"
+
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
+
+static union kano_cbi_fw_config fw_config;
+BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
+
+/*
+ * FW_CONFIG defaults for kano if the CBI.FW_CONFIG data is not
+ * initialized.
+ */
+static const union kano_cbi_fw_config fw_config_defaults = {
+	.kb_bl = KEYBOARD_BACKLIGHT_ENABLED,
+	.thermal_solution = THERMAL_SOLUTION_15W,
+};
+
+/****************************************************************************
+ * Kano FW_CONFIG access
+ */
+void board_init_fw_config(void)
+{
+	if (cbi_get_fw_config(&fw_config.raw_value)) {
+		CPRINTS("CBI: Read FW_CONFIG failed, using board defaults");
+		fw_config = fw_config_defaults;
+	}
+
+	if (get_board_id() == 0) {
+		/*
+		 * Early boards have a zero'd out FW_CONFIG, so replace
+		 * it with a sensible default value.
+		 */
+		if (fw_config.raw_value == 0) {
+			CPRINTS("CBI: FW_CONFIG is zero, using board defaults");
+			fw_config = fw_config_defaults;
+		}
+	}
+}
+
+union kano_cbi_fw_config get_fw_config(void)
+{
+	return fw_config;
+}
+
+bool ec_cfg_has_kblight(void)
+{
+	return (fw_config.kb_bl == KEYBOARD_BACKLIGHT_ENABLED);
+}
+
+enum ec_cfg_thermal_solution_type ec_cfg_thermal_solution(void)
+{
+	return fw_config.thermal_solution;
+}
diff --git a/board/kano/fw_config.h b/board/kano/fw_config.h
new file mode 100644
index 0000000000..9f0c1c3373
--- /dev/null
+++ b/board/kano/fw_config.h
@@ -0,0 +1,61 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __BOARD_KANO_FW_CONFIG_H_
+#define __BOARD_KANO_FW_CONFIG_H_
+
+#include <stdint.h>
+
+/****************************************************************************
+ * CBI FW_CONFIG layout for Kano board.
+ *
+ * Source of truth is the project/brya/kano/config.star configuration file.
+ */
+
+enum ec_cfg_keyboard_backlight_type {
+	KEYBOARD_BACKLIGHT_DISABLED = 0,
+	KEYBOARD_BACKLIGHT_ENABLED = 1
+};
+
+enum ec_cfg_thermal_solution_type {
+	THERMAL_SOLUTION_15W = 0,
+	THERMAL_SOLUTION_28W = 1
+};
+
+union kano_cbi_fw_config {
+	struct {
+		enum ec_cfg_keyboard_backlight_type kb_bl : 1;
+		uint32_t audio : 3;
+		uint32_t ufc : 2;
+		uint32_t stylus : 1;
+		enum ec_cfg_thermal_solution_type thermal_solution : 1;
+		uint32_t reserved_1 : 24;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Read the cached FW_CONFIG.  Guaranteed to have valid values.
+ *
+ * @return the FW_CONFIG for the board.
+ */
+union kano_cbi_fw_config get_fw_config(void);
+
+/**
+ * Check if the FW_CONFIG has enabled keyboard backlight.
+ *
+ * @return true if board supports keyboard backlight, false if the board
+ * doesn't support it.
+ */
+bool ec_cfg_has_kblight(void);
+
+/**
+ * Read the thermal solution config.
+ *
+ * @return thermal solution config.
+ */
+enum ec_cfg_thermal_solution_type ec_cfg_thermal_solution(void);
+
+#endif /* __BOARD_KANO_FW_CONFIG_H_ */
diff --git a/board/kano/gpio.inc b/board/kano/gpio.inc
new file mode 100644
index 0000000000..2ace5cbbca
--- /dev/null
+++ b/board/kano/gpio.inc
@@ -0,0 +1,135 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define MODULE_KB		MODULE_KEYBOARD_SCAN
+
+/* INTERRUPT GPIOs: */
+GPIO_INT(ACOK_OD,                        PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
+GPIO_INT(EC_IMU_INT_R_L,                 PIN(5, 6), GPIO_SEL_1P8V | GPIO_INT_FALLING, motion_interrupt)
+GPIO_INT(EC_PROCHOT_IN_L,                PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
+GPIO_INT(EC_VOLDN_BTN_ODL,               PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(EC_VOLUP_BTN_ODL,               PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(EC_WP_ODL,                      PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(GSC_EC_PWR_BTN_ODL,             PIN(0, 1), GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW, power_button_interrupt)
+GPIO_INT(LID_OPEN,                       PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
+GPIO_INT(SEQ_EC_ALL_SYS_PG,              PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_DSW_PWROK,               PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_RSMRST_ODL,              PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,                       PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,                      PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SYS_SLP_S0IX_L,                 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(TABLET_MODE_L,                  PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
+GPIO_INT(USB_C0_BC12_INT_ODL,            PIN(C, 6), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C0_C2_TCPC_INT_ODL,         PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C0_PPC_INT_ODL,             PIN(6, 2), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C0_RT_INT_ODL,              PIN(B, 1), GPIO_INT_FALLING, retimer_interrupt)
+GPIO_INT(USB_C1_BC12_INT_ODL,            PIN(5, 0), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C1_PPC_INT_ODL,             PIN(F, 5), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C1_TCPC_INT_ODL,            PIN(A, 2), GPIO_INT_FALLING, tcpc_alert_event)
+
+/* USED GPIOs: */
+GPIO(CCD_MODE_ODL,                   PIN(E, 5), GPIO_INPUT)
+GPIO(CHARGER_VAP_OTG_EN,             PIN(7, 3), GPIO_OUT_LOW)
+GPIO(CPU_C10_GATE_L,                 PIN(6, 7), GPIO_INPUT)
+GPIO(EC_BATT_PRES_ODL,               PIN(A, 3), GPIO_INPUT)
+GPIO(EC_ENTERING_RW,                 PIN(0, 3), GPIO_OUT_LOW)
+GPIO(EC_EN_EDP_BL,                   PIN(D, 3), GPIO_OUT_HIGH)
+GPIO(EC_GSC_PACKET_MODE,             PIN(7, 5), GPIO_OUT_LOW)
+GPIO(EC_I2C_BAT_SCL,                 PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_BAT_SDA,                 PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SCL_R,              PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SDA_R,              PIN(B, 2), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,              PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SENSOR_SDA,              PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_USB_C0_C2_PPC_BC_SCL,    PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_PPC_BC_SDA,    PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_RT_SCL,        PIN(D, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_RT_SDA,        PIN(D, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_TCPC_SCL,      PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_TCPC_SDA,      PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_MIX_SCL,          PIN(E, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_MIX_SDA,          PIN(E, 3), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_TCPC_SCL,         PIN(F, 3), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_TCPC_SDA,         PIN(F, 2), GPIO_INPUT)
+GPIO(EC_KB_BL_EN_L,                  PIN(8, 6), GPIO_OUT_HIGH)
+GPIO(EC_PCHHOT_ODL,                  PIN(7, 4), GPIO_INPUT)
+GPIO(EC_PCH_INT_ODL,                 PIN(B, 0), GPIO_ODR_HIGH)
+GPIO(EC_PCH_PWR_BTN_ODL,             PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(EC_PCH_RSMRST_L,                PIN(A, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_RTCRST,                  PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_SYS_PWROK,               PIN(3, 7), GPIO_OUT_LOW)
+GPIO(EC_PCH_WAKE_R_ODL,              PIN(C, 0), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_ODL,                 PIN(6, 3), GPIO_ODR_HIGH)
+GPIO(EN_PP5000_FAN,                  PIN(6, 1), GPIO_OUT_HIGH)
+GPIO(EN_PP5000_USBA_R,               PIN(D, 7), GPIO_OUT_LOW)
+GPIO(EN_S5_RAILS,                    PIN(B, 6), GPIO_OUT_LOW)
+GPIO(IMVP9_VRRDY_OD,                 PIN(4, 3), GPIO_INPUT)
+GPIO(PCH_PWROK,                      PIN(7, 2), GPIO_OUT_LOW)
+GPIO(SYS_RST_ODL,                    PIN(C, 5), GPIO_ODR_HIGH)
+GPIO(USB_C1_FRS_EN,                  PIN(9, 4), GPIO_OUT_LOW)
+GPIO(USB_C1_RT_INT_ODL,              PIN(A, 0), GPIO_INPUT)
+GPIO(USB_C1_RT_RST_R_ODL,            PIN(0, 2), GPIO_ODR_LOW)
+GPIO(VCCST_PWRGD_OD,                 PIN(A, 4), GPIO_ODR_LOW)
+GPIO(LED_1_L,                        PIN(C, 4), GPIO_OUT_HIGH)
+GPIO(LED_2_L,                        PIN(C, 3), GPIO_OUT_HIGH)
+
+/* UART alternate functions */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)              /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */
+
+/* I2C alternate functions */
+ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)               /* GPIO33/I2C5_SCL0/CTS_L, GPIO36/RTS_L/I2C5_SDA0 */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)               /* GPIO87/I2C1_SDA0 */
+ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)               /* GPIO92/I2C2_SCL0, GPIO91/I2C2_SDA0, GPIO90/I2C1_SCL0 */
+ALTERNATE(PIN_MASK(B, 0x0c), 0, MODULE_I2C, 0)               /* GPIOB3/I2C7_SCL0/DCD_L, GPIOB2/I2C7_SDA0/DSR_L */
+ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, GPIO_SEL_1P8V)   /* GPIOB5/I2C0_SCL0, GPIOB4/I2C0_SDA0 */
+ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)               /* GPIOD1/I2C3_SCL0, GPIOD0/I2C3_SDA0 */
+ALTERNATE(PIN_MASK(E, 0x18), 0, MODULE_I2C, 0)               /* GPIOE4/I2C6_SCL1/I3C_SCL, GPIOE3/I2C6_SDA1/I3C_SDA */
+ALTERNATE(PIN_MASK(F, 0x0c), 0, MODULE_I2C, 0)               /* GPIOF3/I2C4_SCL1, GPIOF2/I2C4_SDA1 */
+
+/* PWM alternate functions */
+ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0)               /* GPIO40/TA1 */
+ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)               /* GPIO80/PWM3 */
+ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)               /* GPIOB7/PWM5 */
+
+/* ADC alternate functions */
+ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0)               /* GPIO34/PS2_DAT2/ADC6 */
+ALTERNATE(PIN_MASK(4, 0x34), 0, MODULE_ADC, 0)               /* GPIO42/ADC3/RI_L, GPIO45/ADC0, GPIO44/ADC1 */
+
+/* KB alternate functions */
+ALTERNATE(PIN_MASK(0, 0xf0), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO10&P80_CLK/GPIO07, KSO11&P80_DAT/GPIO06, KSO12/GPIO05, KSO13/GPIO04 */
+ALTERNATE(PIN_MASK(1, 0x7f), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO06/GPO13/GP_SEL_L, KSO07/GPO12/JEN_L, KSO03/GPIO16/JTAG_TDO0_SWO, KSO04/GPIO15/XNOR, KSO05/GPIO14, KSO08/GPIO11/CR_SOUT1, KSO09/GPIO10/CR_SIN1 */
+ALTERNATE(PIN_MASK(2, 0xfc), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI2/GPIO27/TRACEDATA1, KSI3/GPIO26/TRACEDATA0, KSI4/GPIO25/TRACECLK/GP_SCLK, KSI5/GPIO24/GP_MISO, KSI6/GPIO23/S_SBUB, KSI7/GPIO22/S_SBUA */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO00/GPIO21/JTAG_TCK_SWCLK, KSO01/GPIO20/JTAG_TMS_SWIO */
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI0/GPIO31/TRACEDATA3/GP_MOSI, KSI1/GPIO30/TRACEDATA2/GP_CS_L */
+ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO14/GPIO82 */
+
+/* PMU alternate functions */
+ALTERNATE(PIN_MASK(0, 0x01), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN2_L&GPI00/GPIO00 */
+ALTERNATE(PIN_MASK(0, 0x02), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW) /* GPIO01/PSL_IN3_L&GPI01 */
+ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN1_L&GPID2/GPIOD2 */
+
+/* Unused Pins */
+UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
+UNUSED(PIN(3, 2))       /* GPO32/TRIS_L */
+UNUSED(PIN(3, 5))       /* GPO35/CR_SOUT4/TEST_L */
+UNUSED(PIN(6, 6))       /* GPIO66 */
+UNUSED(PIN(5, 7))       /* GPIO57/SER_IRQ/ESPI_ALERT_L */
+
+/* Pre-configured PSL balls:  J8  K6 */
+
+/*
+ * The NPCX keyboard driver does not use named GPIOs to access
+ * keyboard scan pins, so we do not list them in *gpio.inc. However, when
+ * KEYBOARD_COL2_INVERTED is defined, this name is required.
+ */
+GPIO(EC_KSO_02_INV,               PIN(1, 7), GPIO_OUT_LOW)
+
+GPIO(USB_C0_OC_ODL,     PIN(D, 4), GPIO_ODR_HIGH)
+GPIO(USB_C0_FRS_EN,     PIN(6, 0), GPIO_LOW)
+GPIO(USB_C0_RT_RST_ODL, PIN(C, 2), GPIO_ODR_LOW)
+
+GPIO(USB_C1_OC_ODL,     PIN(E, 1), GPIO_ODR_HIGH)
diff --git a/board/kano/i2c.c b/board/kano/i2c.c
new file mode 100644
index 0000000000..70ca87f1b0
--- /dev/null
+++ b/board/kano/i2c.c
@@ -0,0 +1,77 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "i2c.h"
+
+/* I2C port map configuration */
+const struct i2c_port_t i2c_ports[] = {
+	{
+		/* I2C0 */
+		.name = "sensor",
+		.port = I2C_PORT_ACCEL,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_SENSOR_SCL,
+		.sda = GPIO_EC_I2C_SENSOR_SDA,
+	},
+	{
+		/* I2C1 */
+		.name = "tcpc0,2",
+		.port = I2C_PORT_USB_C0_C2_TCPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C2_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C2_TCPC_SDA,
+	},
+	{
+		/* I2C2 */
+		.name = "ppc0,2",
+		.port = I2C_PORT_USB_C0_C2_PPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C2_PPC_BC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C2_PPC_BC_SDA,
+	},
+	{
+		/* I2C3 */
+		.name = "retimer0,2",
+		.port = I2C_PORT_USB_C0_C2_MUX,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C2_RT_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C2_RT_SDA,
+	},
+	{
+		/* I2C4 C1 TCPC */
+		.name = "tcpc1",
+		.port = I2C_PORT_USB_C1_TCPC,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_USB_C1_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C1_TCPC_SDA,
+	},
+	{
+		/* I2C5 */
+		.name = "battery",
+		.port = I2C_PORT_BATTERY,
+		.kbps = 100,
+		.scl = GPIO_EC_I2C_BAT_SCL,
+		.sda = GPIO_EC_I2C_BAT_SDA,
+	},
+	{
+		/* I2C6 */
+		.name = "ppc1",
+		.port = I2C_PORT_USB_C1_PPC,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_USB_C1_MIX_SCL,
+		.sda = GPIO_EC_I2C_USB_C1_MIX_SDA,
+	},
+	{
+		/* I2C7 */
+		.name = "eeprom",
+		.port = I2C_PORT_EEPROM,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_MISC_SCL_R,
+		.sda = GPIO_EC_I2C_MISC_SDA_R,
+	},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/board/kano/keyboard.c b/board/kano/keyboard.c
new file mode 100644
index 0000000000..3a15831adc
--- /dev/null
+++ b/board/kano/keyboard.c
@@ -0,0 +1,47 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "ec_commands.h"
+#include "keyboard_scan.h"
+#include "timer.h"
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/* Increase from 50 us, because KSO_02 passes through the H1. */
+	.output_settle_us = 80,
+	/* Other values should be the same as the default configuration. */
+	.debounce_down_us = 9 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
+		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
+	},
+};
+
+static const struct ec_response_keybd_config kano_kb = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &kano_kb;
+}
diff --git a/board/kano/led.c b/board/kano/led.c
new file mode 100644
index 0000000000..6539ec3819
--- /dev/null
+++ b/board/kano/led.c
@@ -0,0 +1,84 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ * Power and battery LED control for kano
+ */
+
+#include "chipset.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+
+#define LED_ON_LVL 0
+#define LED_OFF_LVL 1
+
+__override const int led_charge_lvl_1 = 5;
+
+__override const int led_charge_lvl_2 = 95;
+
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_AMBER:
+		gpio_set_level(GPIO_LED_2_L, LED_ON_LVL);
+		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
+		break;
+	case EC_LED_COLOR_BLUE:
+		gpio_set_level(GPIO_LED_1_L, LED_ON_LVL);
+		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		brightness_range[EC_LED_COLOR_BLUE] = 1;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(EC_LED_COLOR_AMBER);
+		else if (brightness[EC_LED_COLOR_BLUE] != 0)
+			led_set_color_battery(EC_LED_COLOR_BLUE);
+		else
+			led_set_color_battery(LED_OFF);
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/board/kano/pwm.c b/board/kano/pwm.c
new file mode 100644
index 0000000000..3286e37631
--- /dev/null
+++ b/board/kano/pwm.c
@@ -0,0 +1,40 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "hooks.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_KBLIGHT] = {
+		.channel = 3,
+		.flags = 0,
+		/*
+		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
+		 * flicker. Higher frequencies consume similar average power to
+		 * lower PWM frequencies, but higher frequencies record a much
+		 * lower maximum power.
+		 */
+		.freq = 25000,
+	},
+	[PWM_CH_FAN] = {
+		.channel = 5,
+		.flags = PWM_CONFIG_OPEN_DRAIN,
+		.freq = 25000
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+static void board_pwm_init(void)
+{
+	/*
+	 * Turn on the fan at 50%.
+	 */
+	pwm_enable(PWM_CH_KBLIGHT, 1);
+	pwm_set_duty(PWM_CH_KBLIGHT, 50);
+}
+DECLARE_HOOK(HOOK_INIT, board_pwm_init, HOOK_PRIO_DEFAULT);
diff --git a/board/kano/sensors.c b/board/kano/sensors.c
new file mode 100644
index 0000000000..cce5adcef9
--- /dev/null
+++ b/board/kano/sensors.c
@@ -0,0 +1,413 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "accelgyro.h"
+#include "adc_chip.h"
+#include "common.h"
+#include "driver/accel_bma422.h"
+#include "driver/accel_kionix.h"
+#include "driver/accelgyro_bmi260.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "driver/accelgyro_icm426xx.h"
+#include "driver/accelgyro_icm_common.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "motion_sense.h"
+#include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
+#include "thermal.h"
+
+/* ADC configuration */
+const struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_1_DDR_SOC] = {
+		.name = "TEMP_DDR_SOC",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_2_FAN] = {
+		.name = "TEMP_FAN",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_3_CHARGER] = {
+		.name = "TEMP_CHARGER",
+		.input_ch = NPCX_ADC_CH6,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+K_MUTEX_DEFINE(g_lid_accel_mutex);
+K_MUTEX_DEFINE(g_base_accel_mutex);
+static struct kionix_accel_data g_kx022_data;
+static struct icm_drv_data_t g_icm426xx_data;
+static struct bmi_drv_data_t g_bmi260_data;
+static struct accelgyro_saved_data_t g_bma422_data;
+
+enum base_accelgyro_type {
+	BASE_GYRO_NONE = 0,
+	BASE_GYRO_BMI260 = 1,
+	BASE_GYRO_ICM426XX = 2,
+};
+
+static enum base_accelgyro_type base_accelgyro_config;
+
+/*
+ * TODO:(b/197200940): Verify lid and base orientation
+ * matrix on proto board.
+ */
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, FLOAT_TO_FP(1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, FLOAT_TO_FP(1), 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
+
+static const mat33_fp_t lid_bma422_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+						    { FLOAT_TO_FP(-1), 0, 0 },
+						    { 0, 0, FLOAT_TO_FP(-1) } };
+static const mat33_fp_t base_bmi260_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+						     { FLOAT_TO_FP(-1), 0, 0 },
+						     { 0, 0, FLOAT_TO_FP(1) } };
+
+static struct motion_sensor_t bmi260_base_accel = {
+	.name = "Base Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_BMI260,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &bmi260_drv,
+	.mutex = &g_base_accel_mutex,
+	.drv_data = &g_bmi260_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
+	.rot_standard_ref = &base_bmi260_standard_ref,
+	.min_frequency = BMI_ACCEL_MIN_FREQ,
+	.max_frequency = BMI_ACCEL_MAX_FREQ,
+	.default_range = 4, /* g */
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+		/* Sensor on in S3 */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+	},
+};
+
+static struct motion_sensor_t bmi260_base_gyro = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_BMI260,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &bmi260_drv,
+	.mutex = &g_base_accel_mutex,
+	.drv_data = &g_bmi260_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &base_bmi260_standard_ref,
+	.min_frequency = BMI_GYRO_MIN_FREQ,
+	.max_frequency = BMI_GYRO_MAX_FREQ,
+};
+
+static struct motion_sensor_t bma422_lid_accel = {
+	.name = "Lid Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_BMA422,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_LID,
+	.drv = &bma4_accel_drv,
+	.mutex = &g_lid_accel_mutex,
+	.drv_data = &g_bma422_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = BMA4_I2C_ADDR_SECONDARY,
+	.rot_standard_ref = &lid_bma422_standard_ref,
+	.min_frequency = BMA4_ACCEL_MIN_FREQ,
+	.max_frequency = BMA4_ACCEL_MAX_FREQ,
+	.default_range = 2, /* g, enough for laptop. */
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 12500 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+		/* Sensor on in S3 */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 12500 | ROUND_UP_FLAG,
+			.ec_rate = 0,
+		},
+	},
+};
+
+struct motion_sensor_t motion_sensors[] = {
+	[LID_ACCEL] = {
+		.name = "Lid Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_KX022,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &kionix_accel_drv,
+		.mutex = &g_lid_accel_mutex,
+		.drv_data = &g_kx022_data,
+		.port = I2C_PORT_ACCEL,
+		.i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
+		.rot_standard_ref = &lid_standard_ref, /* identity matrix */
+		.default_range = 2, /* g */
+		.min_frequency = KX022_ACCEL_MIN_FREQ,
+		.max_frequency = KX022_ACCEL_MAX_FREQ,
+		.config = {
+			/* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 12500 | ROUND_UP_FLAG,
+			},
+			/* Sensor on for lid angle detection */
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+		},
+	},
+
+	[BASE_ACCEL] = {
+		.name = "Base Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_ICM426XX,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &icm426xx_drv,
+		.mutex = &g_base_accel_mutex,
+		.drv_data = &g_icm426xx_data,
+		.port = I2C_PORT_ACCEL,
+		.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+		.rot_standard_ref = &base_standard_ref,
+		.default_range = 4,  /* g */
+		.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
+		.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
+		.config = {
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 13000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+		},
+	},
+
+	[BASE_GYRO] = {
+		.name = "Base Gyro",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_ICM426XX,
+		.type = MOTIONSENSE_TYPE_GYRO,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &icm426xx_drv,
+		.mutex = &g_base_accel_mutex,
+		.drv_data = &g_icm426xx_data,
+		.port = I2C_PORT_ACCEL,
+		.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = ICM426XX_GYRO_MIN_FREQ,
+		.max_frequency = ICM426XX_GYRO_MAX_FREQ,
+	},
+};
+const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+static void baseboard_sensors_detect(void)
+{
+	int ret, val;
+
+	if (base_accelgyro_config != BASE_GYRO_NONE)
+		return;
+
+	ret = i2c_read8(I2C_PORT_ACCEL, BMA4_I2C_ADDR_SECONDARY,
+			BMA4_CHIP_ID_ADDR, &val);
+	if (ret == 0 && val == BMA422_CHIP_ID) {
+		motion_sensors[LID_ACCEL] = bma422_lid_accel;
+		ccprints("LID_ACCEL is BMA422");
+	} else
+		ccprints("LID_ACCEL is KX022");
+
+	ret = bmi_read8(I2C_PORT_ACCEL, BMI260_ADDR0_FLAGS, BMI260_CHIP_ID,
+			&val);
+	if (ret == 0 && val == BMI260_CHIP_ID_MAJOR) {
+		motion_sensors[BASE_ACCEL] = bmi260_base_accel;
+		motion_sensors[BASE_GYRO] = bmi260_base_gyro;
+		base_accelgyro_config = BASE_GYRO_BMI260;
+		ccprints("BASE ACCEL is BMI260");
+	} else {
+		base_accelgyro_config = BASE_GYRO_ICM426XX;
+		ccprints("BASE ACCEL IS ICM426XX");
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, baseboard_sensors_detect, HOOK_PRIO_DEFAULT);
+
+static void baseboard_sensors_init(void)
+{
+	/* Enable gpio interrupt for base accelgyro sensor */
+	gpio_enable_interrupt(GPIO_EC_IMU_INT_R_L);
+}
+DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_INIT_I2C + 1);
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	if (base_accelgyro_config == BASE_GYRO_NONE)
+		return;
+	if (base_accelgyro_config == BASE_GYRO_BMI260)
+		bmi260_interrupt(signal);
+	else
+		icm426xx_interrupt(signal);
+}
+
+/* Temperature sensor configuration */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1_DDR_SOC] = { .name = "DDR and SOC",
+				    .type = TEMP_SENSOR_TYPE_BOARD,
+				    .read = get_temp_3v3_30k9_47k_4050b,
+				    .idx = ADC_TEMP_SENSOR_1_DDR_SOC },
+	[TEMP_SENSOR_2_FAN] = { .name = "FAN",
+				.type = TEMP_SENSOR_TYPE_BOARD,
+				.read = get_temp_3v3_30k9_47k_4050b,
+				.idx = ADC_TEMP_SENSOR_2_FAN },
+	[TEMP_SENSOR_3_CHARGER] = { .name = "CHARGER",
+				    .type = TEMP_SENSOR_TYPE_BOARD,
+				    .read = get_temp_3v3_30k9_47k_4050b,
+				    .idx = ADC_TEMP_SENSOR_3_CHARGER },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/*
+ * TODO(b/180681346): update for Alder Lake/brya
+ *
+ * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
+ * 130 C.  However, sensor is located next to DDR, so we need to use the lower
+ * DDR temperature limit (85 C)
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = 0, \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = 0, \
+		}, \
+		.temp_fan_off = 0, \
+		.temp_fan_max = 0, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
+
+/*
+ * TODO(b/180681346): update for Alder Lake/brya
+ *
+ * Inductor limits - used for both charger and PP3300 regulator
+ *
+ * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
+ *
+ * Charger max recommended temperature 100C, max absolute temperature 125C
+ * PP3300 regulator: operating range -40 C to 145 C
+ *
+ * Inductors: limit of 125c
+ * PCB: limit is 80c
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_FAN              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(85), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(90), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(68), \
+		}, \
+		.temp_fan_off = C_TO_K(37), \
+		.temp_fan_max = C_TO_K(90), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_fan = THERMAL_FAN;
+
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_FAN_28W          \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(85), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(90), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(68), \
+		}, \
+		.temp_fan_off = C_TO_K(37), \
+		.temp_fan_max = C_TO_K(62), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_fan_28w =
+	THERMAL_FAN_28W;
+
+/*
+ * Set value to zero to disable charger thermal control.
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CHARGER          \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = 0, \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = 0, \
+		}, \
+		.temp_fan_off = 0, \
+		.temp_fan_max = 0, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_charger =
+	THERMAL_CHARGER;
+
+/* this should really be "const" */
+struct ec_thermal_config thermal_params[] = {
+	[TEMP_SENSOR_1_DDR_SOC] = THERMAL_CPU,
+	[TEMP_SENSOR_2_FAN] = THERMAL_FAN,
+	[TEMP_SENSOR_3_CHARGER] = THERMAL_CHARGER,
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
+
+static void setup_thermal(void)
+{
+	unsigned int table = ec_cfg_thermal_solution();
+	/* Configure Fan */
+	switch (table) {
+	/* 28w CPU fan table */
+	case THERMAL_SOLUTION_28W:
+		cprints(CC_THERMAL, "Fan table set to 28w CPU scheme");
+		thermal_params[TEMP_SENSOR_2_FAN] = thermal_fan_28w;
+		break;
+	/* Default fan table */
+	case THERMAL_SOLUTION_15W:
+	default:
+		cprints(CC_THERMAL, "Fan table set to 15w CPU scheme");
+		break;
+	}
+}
+/* setup_thermal should be called before HOOK_INIT/HOOK_PRIO_DEFAULT */
+DECLARE_HOOK(HOOK_INIT, setup_thermal, HOOK_PRIO_DEFAULT - 1);
diff --git a/board/kano/usbc_config.c b/board/kano/usbc_config.c
new file mode 100644
index 0000000000..d725ab91d2
--- /dev/null
+++ b/board/kano/usbc_config.c
@@ -0,0 +1,304 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/bc12/pi3usb9201_public.h"
+#include "driver/ppc/syv682x_public.h"
+#include "driver/retimer/bb_retimer_public.h"
+#include "driver/tcpm/rt1715.h"
+#include "driver/tcpm/tcpci.h"
+#include "ec_commands.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "ioexpander.h"
+#include "system.h"
+#include "task.h"
+#include "task_id.h"
+#include "timer.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+/* USBC TCPC configuration */
+const struct tcpc_config_t tcpc_config[] = {
+	[USBC_PORT_C0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0_C2_TCPC,
+			.addr_flags = RT1715_I2C_ADDR_FLAGS,
+		},
+		.drv = &rt1715_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
+			 TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V,
+	},
+	[USBC_PORT_C1] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C1_TCPC,
+			.addr_flags = RT1715_I2C_ADDR_FLAGS,
+		},
+		.drv = &rt1715_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
+			 TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
+BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
+
+/* USBC PPC configuration */
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_C2_PPC,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.drv = &syv682x_drv,
+	},
+	[USBC_PORT_C1] = {
+		/* Compatible with Silicon Mitus SM536A0 */
+		.i2c_port = I2C_PORT_USB_C1_PPC,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.drv = &syv682x_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
+
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/* USBC mux configuration - Alder Lake includes internal mux */
+static const struct usb_mux_chain usbc0_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+
+static const struct usb_mux_chain usbc1_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+
+struct usb_mux_chain soc_side_bb_retimer_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C1_MUX,
+			.i2c_addr_flags = USBC_PORT_C1_SOC_BB_RETIMER_I2C_ADDR,
+		},
+	.next = &usbc1_tcss_usb_mux,
+};
+
+const struct usb_mux_chain usb_muxes[] = {
+	[USBC_PORT_C0] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C0_C2_MUX,
+			.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc0_tcss_usb_mux,
+	},
+	[USBC_PORT_C1] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C1_MUX,
+			.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &soc_side_bb_retimer_usb_mux,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
+
+/* BC1.2 charger detect configuration */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_C2_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C1_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_2_FLAGS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
+
+__override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
+{
+	enum gpio_signal rst_signal;
+
+	if (me->usb_port == USBC_PORT_C0) {
+		rst_signal = GPIO_USB_C0_RT_RST_ODL;
+	} else if (me->usb_port == USBC_PORT_C1) {
+		rst_signal = GPIO_USB_C1_RT_RST_R_ODL;
+	} else {
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * We do not have a load switch for the burnside bridge chips,
+	 * so we only need to sequence reset.
+	 */
+
+	if (enable) {
+		/*
+		 * Tpw, minimum time from VCC to RESET_N de-assertion is 100us.
+		 * For boards that don't provide a load switch control, the
+		 * retimer_init() function ensures power is up before calling
+		 * this function.
+		 */
+		gpio_set_level(rst_signal, 1);
+		/*
+		 * Allow 1ms time for the retimer to power up lc_domain
+		 * which powers I2C controller within retimer
+		 */
+		msleep(1);
+	} else {
+		gpio_set_level(rst_signal, 0);
+		msleep(1);
+	}
+	return EC_SUCCESS;
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * TODO(b/179648104): figure out correct timing
+	 */
+
+	gpio_set_level(GPIO_USB_C0_RT_RST_ODL, 0);
+	gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 0);
+
+	/*
+	 * delay for power-on to reset-off and min. assertion time
+	 */
+
+	msleep(20);
+
+	gpio_set_level(GPIO_USB_C0_RT_RST_ODL, 1);
+	gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 1);
+
+	/* wait for chips to come up */
+
+	msleep(50);
+}
+
+static void board_tcpc_init(void)
+{
+	/* Don't reset TCPCs after initial reset */
+	if (!system_jumped_late())
+		board_reset_pd_mcu();
+
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_C2_TCPC_INT_ODL);
+
+	/* Enable BC1.2 interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
+
+	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (gpio_get_level(GPIO_USB_C0_C2_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_0 | PD_STATUS_TCPC_ALERT_2;
+
+	if (gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
+
+int ppc_get_alert_status(int port)
+{
+	if (port == USBC_PORT_C0)
+		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
+	else if (port == USBC_PORT_C1)
+		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
+	return 0;
+}
+
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_C2_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C1);
+		break;
+	default:
+		break;
+	}
+}
+
+void bc12_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_BC12_INT_ODL:
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+		break;
+	case GPIO_USB_C1_BC12_INT_ODL:
+		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+		break;
+	default:
+		break;
+	}
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C1);
+		break;
+	default:
+		break;
+	}
+}
+
+void retimer_interrupt(enum gpio_signal signal)
+{
+	/*
+	 * TODO(b/179513527): add USB-C support
+	 */
+}
+
+__override bool board_is_dts_port(int port)
+{
+	return port == USBC_PORT_C0;
+}
diff --git a/board/kano/usbc_config.h b/board/kano/usbc_config.h
new file mode 100644
index 0000000000..72e26c31c1
--- /dev/null
+++ b/board/kano/usbc_config.h
@@ -0,0 +1,17 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Kano board-specific USB-C configuration */
+
+#ifndef __CROS_EC_USBC_CONFIG_H
+#define __CROS_EC_USBC_CONFIG_H
+
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
+
+void config_usb_db_type(void);
+
+#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/kano/vif_override.xml b/board/kano/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/kano/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/kappa/battery.c b/board/kappa/battery.c
index c09ac72730..bd8f05b418 100644
--- a/board/kappa/battery.c
+++ b/board/kappa/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,7 +9,7 @@
 
 const struct board_batt_params board_battery_info[] = {
 	/* Dynapack HIGHPOWER DAK124960-W110703HT Battery Information */
-	[BATTERY_DANAPACK_HIGHPOWER] = {
+	[BATTERY_DYNAPACK_HIGHPOWER] = {
 		.fuel_gauge = {
 			.manuf_name = "333-2D-14-A",
 			.ship_mode = {
@@ -34,10 +34,11 @@ const struct board_batt_params board_battery_info[] = {
 			.charging_max_c = 45,
 			.discharging_min_c = -10,
 			.discharging_max_c = 60,
+			.vendor_param_start = 0x70,
 		},
 	},
 	/* Dynapack CosMX DAK124960-W0P0707HT Battery Information */
-	[BATTERY_DANAPACK_COS] = {
+	[BATTERY_DYNAPACK_COS] = {
 		.fuel_gauge = {
 			.manuf_name = "333-2C-14-A",
 			.ship_mode = {
@@ -62,12 +63,42 @@ const struct board_batt_params board_battery_info[] = {
 			.charging_max_c = 45,
 			.discharging_min_c = -10,
 			.discharging_max_c = 60,
+			.vendor_param_start = 0x70,
+		},
+	},
+	/* LGC MPPHPPFO021C Battery Information, BMU RAJ240045 */
+	[BATTERY_LGC] = {
+		.fuel_gauge = {
+			.manuf_name = "313-42-14-A",
+			.ship_mode = {
+				.reg_addr = 0x0,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 0,
+				.reg_addr = 0x43,
+				.reg_mask = 0x0003,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8700,		/* mV */
+			.voltage_normal = 7520,		/* mV */
+			.voltage_min = 6000,		/* mV */
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+			.vendor_param_start = 0x70,
 		},
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
 
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_DANAPACK_HIGHPOWER;
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_DYNAPACK_HIGHPOWER;
 
 enum battery_present battery_hw_present(void)
 {
diff --git a/board/kappa/board.c b/board/kappa/board.c
index 89dd4648c6..4a6b2d282e 100644
--- a/board/kappa/board.c
+++ b/board/kappa/board.c
@@ -1,10 +1,9 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "backlight.h"
 #include "button.h"
 #include "charge_manager.h"
@@ -31,6 +30,7 @@
 #include "it8801.h"
 #include "keyboard_scan.h"
 #include "lid_switch.h"
+#include "panic.h"
 #include "power.h"
 #include "power_button.h"
 #include "registers.h"
@@ -38,41 +38,55 @@
 #include "system.h"
 #include "tablet_mode.h"
 #include "task.h"
-#include "tcpm.h"
+#include "tcpm/tcpm.h"
 #include "timer.h"
 #include "usb_charge.h"
 #include "usb_mux.h"
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
 	schedule_deferred_pd_interrupt(0 /* port */);
 }
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /******************************************************************************/
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] =  {"BOARD_ID",  3300, 4096, 0, STM32_AIN(10)},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)},
+	[ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(10) },
+	[ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /******************************************************************************/
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{"typec", 0, 400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"other", 1, 100, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
+	{ .name = "typec",
+	  .port = 0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "other",
+	  .port = 1,
+	  .kbps = 100,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
 const struct i2c_port_t i2c_bitbang_ports[] = {
-	{"battery", 2, 100, GPIO_I2C3_SCL, GPIO_I2C3_SDA, .drv = &bitbang_drv},
+	{ .name = "battery",
+	  .port = 2,
+	  .kbps = 100,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA,
+	  .drv = &bitbang_drv },
 };
 const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
 
@@ -80,13 +94,13 @@ const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
 
 /* power signal list.  Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
+	{ GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" },
+	{ GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" },
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
 /* Keyboard scan setting */
-struct keyboard_scan_config keyscan_config = {
+__override struct keyboard_scan_config keyscan_config = {
 	/*
 	 * TODO(b/133200075): Tune this once we have the final performance
 	 * out of the driver and the i2c bus.
@@ -105,8 +119,8 @@ struct keyboard_scan_config keyscan_config = {
 
 struct ioexpander_config_t ioex_config[CONFIG_IO_EXPANDER_PORT_COUNT] = {
 	[0] = {
-		.i2c_host_port = I2C_PORT_IO_EXPANDER_IT8801,
-		.i2c_slave_addr = IT8801_I2C_ADDR,
+		.i2c_host_port = I2C_PORT_KB_DISCRETE,
+		.i2c_addr_flags = IT8801_I2C_ADDR1,
 		.drv = &it8801_ioexpander_drv,
 	},
 };
@@ -114,8 +128,7 @@ struct ioexpander_config_t ioex_config[CONFIG_IO_EXPANDER_PORT_COUNT] = {
 /******************************************************************************/
 /* SPI devices */
 /* TODO: to be added once sensors land via CL:1714436 */
-const struct spi_device_t spi_devices[] = {
-};
+const struct spi_device_t spi_devices[] = {};
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
 const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
@@ -131,15 +144,18 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = I2C_PORT_TCPC0,
-			.addr_flags = FUSB302_I2C_SLAVE_ADDR_FLAGS,
+			.addr_flags = FUSB302_I2C_ADDR_FLAGS,
 		},
 		.drv = &fusb302_tcpm_drv,
 	},
 };
 
-static void board_hpd_status(const struct usb_mux *me,
-			     int hpd_lvl, int hpd_irq)
+static void board_hpd_status(const struct usb_mux *me, mux_state_t mux_state,
+			     bool *ack_required)
 {
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
 	/*
 	 * svdm_dp_attention() did most of the work, we only need to notify
 	 * host here.
@@ -147,13 +163,16 @@ static void board_hpd_status(const struct usb_mux *me,
 	host_set_single_event(EC_HOST_EVENT_USB_MUX);
 }
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+				.hpd_update = &board_hpd_status,
+			},
 	},
 };
 
@@ -183,7 +202,7 @@ int board_set_active_charge_port(int charge_port)
 		if (board_vbus_source_enabled(charge_port))
 			return -1;
 		break;
-	case CHARGE_PORT_NONE:
+	default:
 		/*
 		 * To ensure the fuel gauge (max17055) is always powered
 		 * even when battery is disconnected, keep VBAT rail on but
@@ -191,22 +210,11 @@ int board_set_active_charge_port(int charge_port)
 		 */
 		charger_set_current(CHARGER_SOLO, 0);
 		break;
-	default:
-		panic("Invalid charge port\n");
-		break;
 	}
 
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-			       CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
-
 int board_discharge_on_ac(int enable)
 {
 	int ret, port;
@@ -236,7 +244,7 @@ int pd_snk_is_vbus_provided(int port)
 
 void bc12_interrupt(enum gpio_signal signal)
 {
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
 }
 
 static void board_init(void)
@@ -251,11 +259,6 @@ static void board_init(void)
 	/* Enable TCPC alert interrupts */
 	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
 
-#ifdef SECTION_IS_RW
-	/* Enable interrupts from BMI160 sensor. */
-	gpio_enable_interrupt(GPIO_ACCEL_INT_ODL);
-#endif /* SECTION_IS_RW */
-
 	/* Enable interrupt from PMIC. */
 	gpio_enable_interrupt(GPIO_PMIC_EC_RESETB);
 
@@ -264,16 +267,6 @@ static void board_init(void)
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
-/* Motion sensors */
-/* Mutexes */
-#ifdef SECTION_IS_RW
-/* TODO: to be added once sensors land via CL:1714436 */
-struct motion_sensor_t motion_sensors[] = {
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-#endif /* SECTION_IS_RW */
-
 /* Called on AP S5 -> S3 transition */
 static void board_chipset_startup(void)
 {
@@ -287,25 +280,3 @@ static void board_chipset_shutdown(void)
 	gpio_set_level(GPIO_EN_USBA_5V, 0);
 }
 DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
-
-int battery_get_vendor_param(uint32_t param, uint32_t *value)
-{
-	int rv;
-	uint8_t data[16] = {};
-
-	/* only allow reading 0x70~0x7F, 16 byte data */
-	if (param < 0x70 || param >= 0x80)
-		return EC_ERROR_ACCESS_DENIED;
-
-	rv = sb_read_string(0x70, data, sizeof(data));
-	if (rv)
-		return rv;
-
-	*value = data[param - 0x70];
-	return EC_SUCCESS;
-}
-
-int battery_set_vendor_param(uint32_t param, uint32_t value)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
diff --git a/board/kappa/board.h b/board/kappa/board.h
index 81ac819cf9..0911d50951 100644
--- a/board/kappa/board.h
+++ b/board/kappa/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,10 +11,9 @@
 #define VARIANT_KUKUI_JACUZZI
 #define VARIANT_KUKUI_BATTERY_SMART
 #define VARIANT_KUKUI_CHARGER_ISL9238
+#define VARIANT_KUKUI_EC_STM32F098
 
-#ifndef SECTION_IS_RW
 #define VARIANT_KUKUI_NO_SENSORS
-#endif /* SECTION_IS_RW */
 
 #include "baseboard.h"
 
@@ -23,8 +22,12 @@
 
 #define CONFIG_BATTERY_HW_PRESENT_CUSTOM
 #define CONFIG_BATTERY_VENDOR_PARAM
+#define CONFIG_BATTERY_V2
+#define CONFIG_BATTERY_COUNT 1
 
 #define CONFIG_CHARGER_PSYS
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 5
 
 #define CONFIG_BC12_DETECT_PI3USB9201
 
@@ -44,45 +47,25 @@
 
 #define CONFIG_USB_MUX_IT5205
 
-/* Motion Sensors */
-#ifdef SECTION_IS_RW
-#define CONFIG_MAG_BMI_BMM150
-#define CONFIG_ACCELGYRO_SEC_ADDR_FLAGS BMM150_ADDR0_FLAGS
-#define CONFIG_MAG_CALIBRATE
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
-#define CONFIG_ALS
-
-#define ALS_COUNT 1
-#define CONFIG_ALS_TCS3400
-#define CONFIG_ALS_TCS3400_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS)
-#define CONFIG_ALS_TCS3400_EMULATED_IRQ_EVENT
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(CLEAR_ALS)
-
-#endif /* SECTION_IS_RW */
+#undef CONFIG_GMR_TABLET_MODE
+#undef CONFIG_TABLET_MODE
+#undef CONFIG_TABLET_MODE_SWITCH
 
 /* I2C ports */
-#define I2C_PORT_BC12               0
-#define I2C_PORT_TCPC0              0
-#define I2C_PORT_USB_MUX            0
-#define I2C_PORT_BATTERY            2
-#define I2C_PORT_CHARGER            1
-#define I2C_PORT_IO_EXPANDER_IT8801 1
-#define I2C_PORT_VIRTUAL_BATTERY    I2C_PORT_BATTERY
+#define I2C_PORT_BC12 0
+#define I2C_PORT_TCPC0 0
+#define I2C_PORT_USB_MUX 0
+#define I2C_PORT_BATTERY 2
+#define I2C_PORT_CHARGER 1
+#define I2C_PORT_KB_DISCRETE 1
+#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
 
-/* Enable Accel over SPI */
-#define CONFIG_SPI_ACCEL_PORT    0  /* The first SPI master port (SPI2) */
+/* IT8801 I2C address */
+#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1
 
 #define CONFIG_KEYBOARD_PROTOCOL_MKBP
 #define CONFIG_MKBP_EVENT
 #define CONFIG_MKBP_USE_GPIO
-/* Define the MKBP events which are allowed to wakeup AP in S3. */
-#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \
-		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
 
 #ifndef __ASSEMBLER__
 
@@ -118,8 +101,9 @@ enum charge_port {
 };
 
 enum battery_type {
-	BATTERY_DANAPACK_HIGHPOWER,
-	BATTERY_DANAPACK_COS,
+	BATTERY_DYNAPACK_HIGHPOWER,
+	BATTERY_DYNAPACK_COS,
+	BATTERY_LGC,
 	BATTERY_TYPE_COUNT,
 };
 
@@ -134,7 +118,6 @@ void emmc_cmd_interrupt(enum gpio_signal signal);
 void bc12_interrupt(enum gpio_signal signal);
 void board_reset_pd_mcu(void);
 int board_get_version(void);
-int board_is_sourcing_vbus(int port);
 
 /* returns the i2c port number of charger */
 int board_get_charger_i2c(void);
diff --git a/board/kappa/build.mk b/board/kappa/build.mk
index e449fce9fc..80c34a4e46 100644
--- a/board/kappa/build.mk
+++ b/board/kappa/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/kappa/ec.tasklist b/board/kappa/ec.tasklist
index b695d05a71..3705823bac 100644
--- a/board/kappa/ec.tasklist
+++ b/board/kappa/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,7 +11,6 @@
 	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
 	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, VENTI_TASK_STACK_SIZE) \
 	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS_RW(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
 	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 1024) \
 	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
 	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, LARGER_TASK_STACK_SIZE) \
diff --git a/board/kappa/gpio.inc b/board/kappa/gpio.inc
index 1f3bd6cd9d..d7d6c5267b 100644
--- a/board/kappa/gpio.inc
+++ b/board/kappa/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,8 +21,6 @@ GPIO_INT(PMIC_EC_RESETB,    PIN(B, 7),  GPIO_INT_BOTH | GPIO_PULL_DOWN,
          power_signal_interrupt)
 GPIO_INT(WARM_RESET_REQ,    PIN(A, 3),  GPIO_INT_RISING | GPIO_PULL_DOWN,
          chipset_reset_request_interrupt)
-GPIO_INT_RW(ACCEL_INT_ODL,  PIN(A, 4), GPIO_INT_FALLING | GPIO_SEL_1P8V | GPIO_PULL_UP,
-         bmi160_interrupt)
 GPIO_INT_RO(EMMC_CMD,       PIN(B, 15), GPIO_INT_FALLING,
          emmc_cmd_interrupt)
 GPIO_INT(SPI1_NSS,          PIN(A, 15), GPIO_INT_BOTH | GPIO_PULL_UP,
@@ -37,8 +35,6 @@ GPIO_INT(IT8801_SMB_INT,    PIN(A, 8),  GPIO_INT_FALLING | GPIO_PULL_UP,
          io_expander_it8801_interrupt) /* KB_INT_ODL */
 GPIO_INT(AP_EC_WATCHDOG_L,  PIN(D, 2),  GPIO_INT_FALLING,
          chipset_watchdog_interrupt)
-GPIO_INT(TABLET_MODE_L,     PIN(B, 11), GPIO_INT_BOTH,
-         gmr_tablet_switch_isr)
 
 /* Unimplemented interrupts */
 GPIO(ALS_RGB_INT_ODL,      PIN(C, 10), GPIO_INPUT)
diff --git a/board/kappa/led.c b/board/kappa/led.c
index 5b65d7b948..e17657d421 100644
--- a/board/kappa/led.c
+++ b/board/kappa/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -14,7 +14,7 @@
 #define BAT_LED_ON 0
 #define BAT_LED_OFF 1
 
-const enum ec_led_id supported_led_ids[] = {EC_LED_ID_BATTERY_LED};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -22,7 +22,7 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static int led_set_color_battery(enum led_color color)
@@ -82,32 +82,30 @@ static void led_set_battery(void)
 {
 	static int battery_ticks;
 	static int power_ticks;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
 	/* override battery led for system suspend */
-	if (chipset_in_state(CHIPSET_STATE_SUSPEND |
-			     CHIPSET_STATE_STANDBY) &&
-	    charge_get_state() != PWR_STATE_CHARGE) {
-		led_set_color_battery(power_ticks++ & 0x2 ?
-				      LED_WHITE : LED_OFF);
+	if (chipset_in_state(CHIPSET_STATE_SUSPEND | CHIPSET_STATE_STANDBY) &&
+	    led_pwr_get_state() != LED_PWRS_CHARGE) {
+		led_set_color_battery(power_ticks++ & 0x2 ? LED_WHITE :
+							    LED_OFF);
 		return;
 	}
 
 	power_ticks = 0;
 
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
 		led_set_color_battery(LED_AMBER);
 		break;
-	case PWR_STATE_DISCHARGE_FULL:
+	case LED_PWRS_DISCHARGE_FULL:
 		if (extpower_is_present()) {
 			led_set_color_battery(LED_WHITE);
 			break;
 		}
-		/* Intentional fall-through */
-	case PWR_STATE_DISCHARGE:
+		__fallthrough;
+	case LED_PWRS_DISCHARGE:
 		/*
 		 * Blink white light (1 sec on, 1 sec off)
 		 * when battery capacity is less than 10%
@@ -118,19 +116,19 @@ static void led_set_battery(void)
 		else
 			led_set_color_battery(LED_OFF);
 		break;
-	case PWR_STATE_ERROR:
-		led_set_color_battery(
-			(battery_ticks % 0x2) ? LED_WHITE : LED_OFF);
+	case LED_PWRS_ERROR:
+		led_set_color_battery((battery_ticks % 0x2) ? LED_WHITE :
+							      LED_OFF);
 		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
+	case LED_PWRS_CHARGE_NEAR_FULL:
 		led_set_color_battery(LED_WHITE);
 		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			led_set_color_battery(
-				(battery_ticks & 0x2) ? LED_AMBER : LED_OFF);
-		else
-			led_set_color_battery(LED_WHITE);
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		led_set_color_battery(LED_WHITE);
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		led_set_color_battery((battery_ticks & 0x2) ? LED_AMBER :
+							      LED_OFF);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
diff --git a/board/kappa/vif_override.xml b/board/kappa/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/kappa/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/karma/board.c b/board/karma/board.c
index 7bac35bd64..df053ad782 100644
--- a/board/karma/board.c
+++ b/board/karma/board.c
@@ -1,16 +1,17 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "console.h"
 #include "gpio.h"
+#include "hooks.h"
 #include "oz554.h"
 
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args)
 
-__override void oz554_board_init(void)
+void oz554_board_init(void)
 {
 	int pin_status = 0;
 
@@ -40,3 +41,10 @@ __override void oz554_board_init(void)
 		break;
 	}
 }
+
+static void init_oz554(void)
+{
+	oz554_board_init();
+	gpio_enable_interrupt(GPIO_PANEL_BACKLIGHT_EN);
+}
+DECLARE_HOOK(HOOK_INIT, init_oz554, HOOK_PRIO_DEFAULT);
diff --git a/board/karma/board.h b/board/karma/board.h
index 372b18509b..c3b6cd074a 100644
--- a/board/karma/board.h
+++ b/board/karma/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/karma/build.mk b/board/karma/build.mk
index 2554425920..bee5d9f886 100644
--- a/board/karma/build.mk
+++ b/board/karma/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/karma/ec.tasklist b/board/karma/ec.tasklist
index ca4e3b5ee6..829c9f19bc 100644
--- a/board/karma/ec.tasklist
+++ b/board/karma/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/karma/gpio.inc b/board/karma/gpio.inc
index 1b265ed6ca..2f0fef053e 100644
--- a/board/karma/gpio.inc
+++ b/board/karma/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,7 +11,7 @@
 GPIO_INT(USB_C0_PD_INT_ODL,	PIN(3, 7), GPIO_INT_FALLING | GPIO_PULL_UP,	tcpc_alert_event)
 GPIO_INT(AC_PRESENT,		PIN(C, 1), GPIO_INT_BOTH,			extpower_interrupt)
 GPIO_INT(POWER_BUTTON_L,	PIN(0, 4), GPIO_INT_BOTH | GPIO_PULL_UP,	power_button_interrupt)	/* MECH_PWR_BTN_ODL */
-GPIO_INT(PANEL_BACKLIGHT_EN,	PIN(4, 4), GPIO_INT_RISING, backlight_enable_interrupt)
+GPIO_INT(PANEL_BACKLIGHT_EN,	PIN(4, 4), GPIO_INT_RISING, oz554_interrupt)
 
 GPIO_INT(PCH_SLP_S0_L,		PIN(7, 5), GPIO_INT_BOTH,			power_signal_interrupt)
 GPIO_INT(PCH_SLP_SUS_L,		PIN(6, 2), GPIO_INT_BOTH,			power_signal_interrupt)
diff --git a/board/karma/vif_override.xml b/board/karma/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/karma/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/katsu/board.c b/board/katsu/board.c
new file mode 100644
index 0000000000..a7f7347814
--- /dev/null
+++ b/board/katsu/board.c
@@ -0,0 +1,452 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc.h"
+#include "button.h"
+#include "charge_manager.h"
+#include "charge_ramp.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "charger_mt6370.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "driver/accelgyro_icm426xx.h"
+#include "driver/accelgyro_icm_common.h"
+#include "driver/charger/rt946x.h"
+#include "driver/sync.h"
+#include "driver/tcpm/mt6370.h"
+#include "driver/usb_mux/it5205.h"
+#include "extpower.h"
+#include "gesture.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "i2c.h"
+#include "lid_switch.h"
+#include "panic.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "registers.h"
+#include "spi.h"
+#include "system.h"
+#include "task.h"
+#include "tcpm/tcpm.h"
+#include "timer.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd_policy.h"
+#include "usb_pd_tcpm.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+static void tcpc_alert_event(enum gpio_signal signal)
+{
+	schedule_deferred_pd_interrupt(0 /* port */);
+}
+
+static void gauge_interrupt(enum gpio_signal signal)
+{
+	task_wake(TASK_ID_CHARGER);
+}
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/******************************************************************************/
+/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
+const struct adc_t adc_channels[] = {
+	[ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(10) },
+	[ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8) },
+	[ADC_BATT_ID] = { "BATT_ID", 3300, 4096, 0, STM32_AIN(7) },
+	[ADC_POGO_ADC_INT_L] = { "POGO_ADC_INT_L", 3300, 4096, 0,
+				 STM32_AIN(6) },
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/******************************************************************************/
+/* I2C ports */
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "typec",
+	  .port = 0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "other",
+	  .port = 1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+/* power signal list.  Must match order of enum power_signal. */
+const struct power_signal_info power_signal_list[] = {
+	{ GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" },
+	{ GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" },
+};
+BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
+
+/******************************************************************************/
+/* SPI devices */
+const struct spi_device_t spi_devices[] = {};
+const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
+
+/******************************************************************************/
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TCPC0,
+			.addr_flags = MT6370_TCPC_I2C_ADDR_FLAGS,
+		},
+		.drv = &mt6370_tcpm_drv,
+	},
+};
+
+struct mt6370_thermal_bound thermal_bound = {
+	.target = 80,
+	.err = 4,
+};
+
+static void board_hpd_update(const struct usb_mux *me, mux_state_t mux_state,
+			     bool *ack_required)
+{
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
+	/*
+	 * svdm_dp_attention() did most of the work, we only need to notify
+	 * host here.
+	 */
+	host_set_single_event(EC_HOST_EVENT_USB_MUX);
+}
+
+__override const struct rt946x_init_setting *board_rt946x_init_setting(void)
+{
+	static const struct rt946x_init_setting battery_init_setting = {
+		.eoc_current = 140,
+		.mivr = 4000,
+		.ircmp_vclamp = 32,
+		.ircmp_res = 25,
+		.boost_voltage = 5050,
+		.boost_current = 1500,
+	};
+
+	return &battery_init_setting;
+}
+
+struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+				.hpd_update = &board_hpd_update,
+			},
+	},
+};
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
+		status |= PD_STATUS_TCPC_ALERT_0;
+
+	return status;
+}
+
+static int force_discharge;
+
+int board_set_active_charge_port(int charge_port)
+{
+	CPRINTS("New chg p%d", charge_port);
+
+	/* ignore all request when discharge mode is on */
+	if (force_discharge && charge_port != CHARGE_PORT_NONE)
+		return EC_SUCCESS;
+
+	switch (charge_port) {
+	case CHARGE_PORT_USB_C:
+		/* Don't charge from a source port */
+		if (board_vbus_source_enabled(charge_port))
+			return -1;
+		gpio_set_level(GPIO_EN_POGO_CHARGE_L, 1);
+		gpio_set_level(GPIO_EN_USBC_CHARGE_L, 0);
+		break;
+#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
+	case CHARGE_PORT_POGO:
+		gpio_set_level(GPIO_EN_USBC_CHARGE_L, 1);
+		gpio_set_level(GPIO_EN_POGO_CHARGE_L, 0);
+		break;
+#endif
+	default:
+		/*
+		 * To ensure the fuel gauge (max17055) is always powered
+		 * even when battery is disconnected, keep VBAT rail on but
+		 * set the charging current to minimum.
+		 */
+		gpio_set_level(GPIO_EN_POGO_CHARGE_L, 1);
+		gpio_set_level(GPIO_EN_USBC_CHARGE_L, 1);
+		charger_set_current(CHARGER_SOLO, 0);
+		break;
+	}
+
+	return EC_SUCCESS;
+}
+
+int board_discharge_on_ac(int enable)
+{
+	int ret, port;
+
+	if (enable) {
+		port = CHARGE_PORT_NONE;
+	} else {
+		/* restore the charge port state */
+		port = charge_manager_get_override();
+		if (port == OVERRIDE_OFF)
+			port = charge_manager_get_active_charge_port();
+	}
+
+	ret = charger_discharge_on_ac(enable);
+	if (ret)
+		return ret;
+
+	if (force_discharge && !enable)
+		rt946x_toggle_bc12_detection();
+
+	force_discharge = enable;
+	return board_set_active_charge_port(port);
+}
+
+int extpower_is_present(void)
+{
+	/*
+	 * The charger will indicate VBUS presence if we're sourcing 5V,
+	 * so exclude such ports.
+	 */
+	int usb_c_extpower_present;
+	static int prev_usb_c_extpower_present;
+
+	if (board_vbus_source_enabled(CHARGE_PORT_USB_C))
+		usb_c_extpower_present = 0;
+	else
+		usb_c_extpower_present =
+			tcpm_check_vbus_level(CHARGE_PORT_USB_C, VBUS_PRESENT);
+
+	if (prev_usb_c_extpower_present != usb_c_extpower_present) {
+		if (usb_c_extpower_present)
+			host_set_single_event(EC_HOST_EVENT_AC_CONNECTED);
+		else
+			host_set_single_event(EC_HOST_EVENT_AC_DISCONNECTED);
+		prev_usb_c_extpower_present = usb_c_extpower_present;
+	}
+
+	return usb_c_extpower_present;
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	if (port)
+		panic("Invalid charge port\n");
+
+	return rt946x_is_vbus_ready();
+}
+
+static void board_init(void)
+{
+	/* If the reset cause is external, pulse PMIC force reset. */
+	if (system_get_reset_flags() == EC_RESET_FLAG_RESET_PIN) {
+		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 0);
+		msleep(100);
+		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 1);
+	}
+
+	/* Enable TCPC alert interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
+
+	/* Enable charger interrupts */
+	gpio_enable_interrupt(GPIO_CHARGER_INT_ODL);
+
+#ifdef SECTION_IS_RW
+	/* Enable interrupts from ICM40608 sensor. */
+	gpio_enable_interrupt(GPIO_ACCEL_INT_ODL);
+
+	/* Enable interrupt for the camera vsync. */
+	gpio_enable_interrupt(GPIO_SYNC_INT);
+#endif /* SECTION_IS_RW */
+
+	/* Enable interrupt from PMIC. */
+	gpio_enable_interrupt(GPIO_PMIC_EC_RESETB);
+
+	/* Enable gauge interrupt from max17055 */
+	gpio_enable_interrupt(GPIO_GAUGE_INT_ODL);
+
+	/*
+	 * Fix backlight led maximum current:
+	 * tolerance 120mA * 0.75 = 90mA.
+	 * (b/133655155)
+	 */
+	mt6370_backlight_set_dim(MT6370_BLDIM_DEFAULT * 3 / 4);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+static void board_rev_init(void)
+{
+	/* Board revision specific configs. */
+
+	/*
+	 * It's a P1 pin BOOTBLOCK_MUX_OE, also a P2 pin BC12_DET_EN.
+	 * Keep this pin defaults to P1 setting since that eMMC enabled with
+	 * High-Z stat.
+	 */
+	/* TODO */
+	/* Put initial code here for different EC board reversion */
+}
+DECLARE_HOOK(HOOK_INIT, board_rev_init, HOOK_PRIO_INIT_ADC + 1);
+
+void sensor_board_proc_double_tap(void)
+{
+	CPRINTS("Detect double tap");
+}
+
+/* Motion sensors */
+/* Mutexes */
+#ifndef VARIANT_KUKUI_NO_SENSORS
+static struct mutex g_lid_mutex;
+
+static struct icm_drv_data_t g_icm426xx_data;
+
+/* Matrix to rotate accelerometer into standard reference frame */
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					     { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
+
+struct motion_sensor_t motion_sensors[] = {
+	/*
+	 * Note: ICM40608: supports accelerometer and gyro sensor
+	 * Requirement: accelerometer sensor must init before gyro sensor
+	 * DO NOT change the order of the following table.
+	 */
+	[LID_ACCEL] = {
+	 .name = "Accel",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_ICM426XX,
+	 .type = MOTIONSENSE_TYPE_ACCEL,
+	 .location = MOTIONSENSE_LOC_LID,
+	 .drv = &icm426xx_drv,
+	 .mutex = &g_lid_mutex,
+	 .drv_data = &g_icm426xx_data,
+	 .port = I2C_PORT_ACCEL,
+	 .i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	 .rot_standard_ref = &lid_standard_ref,
+	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
+	 .min_frequency = ICM426XX_ACCEL_MIN_FREQ,
+	 .max_frequency = ICM426XX_ACCEL_MAX_FREQ,
+	 .config = {
+		 /* Enable accel in S0 */
+		 [SENSOR_CONFIG_EC_S0] = {
+			 .odr = TAP_ODR,
+			 .ec_rate = 100 * MSEC,
+		 },
+		 /* For double tap detection */
+		 [SENSOR_CONFIG_EC_S3] = {
+			 .odr = TAP_ODR,
+			 .ec_rate = 100 * MSEC,
+		 },
+	 },
+	},
+	[LID_GYRO] = {
+	 .name = "Gyro",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_ICM426XX,
+	 .type = MOTIONSENSE_TYPE_GYRO,
+	 .location = MOTIONSENSE_LOC_LID,
+	 .drv = &icm426xx_drv,
+	 .mutex = &g_lid_mutex,
+	 .drv_data = &g_icm426xx_data,
+	 .port = I2C_PORT_ACCEL,
+	 .i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	 .default_range = 1000, /* dps */
+	 .rot_standard_ref = &lid_standard_ref,
+	 .min_frequency = ICM426XX_GYRO_MIN_FREQ,
+	 .max_frequency = ICM426XX_GYRO_MAX_FREQ,
+	},
+	[VSYNC] = {
+	 .name = "Camera vsync",
+	 .active_mask = SENSOR_ACTIVE_S0,
+	 .chip = MOTIONSENSE_CHIP_GPIO,
+	 .type = MOTIONSENSE_TYPE_SYNC,
+	 .location = MOTIONSENSE_LOC_CAMERA,
+	 .drv = &sync_drv,
+	 .default_range = 0,
+	 .min_frequency = 0,
+	 .max_frequency = 1,
+	},
+};
+const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+#endif /* VARIANT_KUKUI_NO_SENSORS */
+
+/*
+ * Return if VBUS is sagging too low
+ */
+int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
+{
+	int voltage;
+	/*
+	 * Though we have a more tolerant range (3.9V~13.4V), setting 4400 to
+	 * prevent from a bad charger crashed.
+	 *
+	 * TODO(b:131284131): mt6370 VBUS reading is not accurate currently.
+	 * Vendor will provide a workaround solution to fix the gap between ADC
+	 * reading and actual voltage.  After the workaround applied, we could
+	 * try to raise this value to 4600.  (when it says it read 4400, it is
+	 * actually close to 4600)
+	 */
+	if (charger_get_vbus_voltage(port, &voltage))
+		voltage = 0;
+
+	return voltage < 4400;
+}
+
+__override int board_charge_port_is_sink(int port)
+{
+	/* TODO(b:128386458): Check POGO_ADC_INT_L */
+	return 1;
+}
+
+__override int board_charge_port_is_connected(int port)
+{
+	return gpio_get_level(GPIO_POGO_VBUS_PRESENT);
+}
+
+__override void
+board_fill_source_power_info(int port, struct ec_response_usb_pd_power_info *r)
+{
+	r->meas.voltage_now = 3300;
+	r->meas.voltage_max = 3300;
+	r->meas.current_max = 1500;
+	r->meas.current_lim = 1500;
+	r->max_power = r->meas.voltage_now * r->meas.current_max;
+}
+
+/* b/207456334: bugged reserved bits causes device not charging */
+static void mt6370_reg_fix(void)
+{
+	i2c_update8(chg_chips[CHARGER_SOLO].i2c_port,
+		    chg_chips[CHARGER_SOLO].i2c_addr_flags, RT946X_REG_CHGCTRL1,
+		    BIT(3) | BIT(5), MASK_CLR);
+	i2c_update8(chg_chips[CHARGER_SOLO].i2c_port,
+		    chg_chips[CHARGER_SOLO].i2c_addr_flags, RT946X_REG_CHGCTRL2,
+		    BIT(5) | BIT(RT946X_SHIFT_BATDET_DIS_DLY), MASK_CLR);
+}
+DECLARE_HOOK(HOOK_INIT, mt6370_reg_fix, HOOK_PRIO_DEFAULT);
diff --git a/board/katsu/board.h b/board/katsu/board.h
new file mode 100644
index 0000000000..6f53801ffc
--- /dev/null
+++ b/board/katsu/board.h
@@ -0,0 +1,130 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Configuration for Katsu */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#define BQ27541_ADDR 0x55
+#define VARIANT_KUKUI_BATTERY_BQ27541
+#define VARIANT_KUKUI_POGO_KEYBOARD
+
+#define VARIANT_KUKUI_CHARGER_MT6370
+#define VARIANT_KUKUI_EC_STM32F098
+#define VARIANT_KUKUI_TABLET_PWRBTN
+
+#ifndef SECTION_IS_RW
+#define VARIANT_KUKUI_NO_SENSORS
+#endif /* SECTION_IS_RW */
+
+#include "baseboard.h"
+
+#define CONFIG_USB_MUX_IT5205
+#define CONFIG_VOLUME_BUTTONS
+#define CONFIG_USB_MUX_RUNTIME_CONFIG
+
+/* Battery */
+#define BATTERY_DESIRED_CHARGING_CURRENT 3500 /* mA */
+
+#define CONFIG_CHARGER_MT6370_BACKLIGHT
+
+/* Motion Sensors */
+#ifdef SECTION_IS_RW
+#define CONFIG_ACCELGYRO_ICM426XX
+#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
+
+/* Camera VSYNC */
+#define CONFIG_SYNC
+#define CONFIG_SYNC_COMMAND
+#define CONFIG_SYNC_INT_EVENT TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
+#endif /* SECTION_IS_RW */
+
+/* I2C ports */
+#define I2C_PORT_CHARGER 0
+#define I2C_PORT_TCPC0 0
+#define I2C_PORT_USB_MUX 0
+#define I2C_PORT_BATTERY 1
+#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
+#define I2C_PORT_ACCEL 1
+#define I2C_PORT_BC12 1
+
+/* Route sbs host requests to virtual battery driver */
+#define VIRTUAL_BATTERY_ADDR_FLAGS 0x0B
+
+/* MKBP */
+#define CONFIG_MKBP_INPUT_DEVICES
+#define CONFIG_MKBP_EVENT
+#define CONFIG_MKBP_EVENT_WAKEUP_MASK \
+	(BIT(EC_MKBP_EVENT_SENSOR_FIFO) | BIT(EC_MKBP_EVENT_HOST_EVENT))
+#undef CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK
+#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK                   \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |        \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |    \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |    \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
+
+#define PD_OPERATING_POWER_MW 15000
+
+#ifndef __ASSEMBLER__
+
+enum adc_channel {
+	/* Real ADC channels begin here */
+	ADC_BOARD_ID = 0,
+	ADC_EC_SKU_ID,
+	ADC_BATT_ID,
+	ADC_POGO_ADC_INT_L,
+	ADC_CH_COUNT
+};
+
+/* power signal definitions */
+enum power_signal {
+	AP_IN_S3_L,
+	PMIC_PWR_GOOD,
+
+	/* Number of signals */
+	POWER_SIGNAL_COUNT,
+};
+
+/* Motion sensors */
+enum sensor_id {
+	LID_ACCEL = 0,
+	LID_GYRO,
+	VSYNC,
+	SENSOR_COUNT,
+};
+
+enum charge_port {
+	CHARGE_PORT_USB_C,
+};
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+#ifdef SECTION_IS_RO
+/* Interrupt handler for emmc task */
+void emmc_cmd_interrupt(enum gpio_signal signal);
+#endif
+
+void board_reset_pd_mcu(void);
+int board_get_version(void);
+void pogo_adc_interrupt(enum gpio_signal signal);
+int board_discharge_on_ac(int enable);
+
+/* Enable double tap detection */
+#define CONFIG_GESTURE_DETECTION
+#define CONFIG_GESTURE_SENSOR_DOUBLE_TAP
+#define CONFIG_GESTURE_TAP_SENSOR 0
+#define CONFIG_GESTURE_SENSOR_DOUBLE_TAP_FOR_HOST
+#define CONFIG_GESTURE_SAMPLING_INTERVAL_MS 5
+#define CONFIG_GESTURE_TAP_THRES_MG 100
+#define CONFIG_GESTURE_TAP_MAX_INTERSTICE_T 500
+#define CONFIG_GESTURE_DETECTION_MASK BIT(CONFIG_GESTURE_TAP_SENSOR)
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/katsu/build.mk b/board/katsu/build.mk
new file mode 100644
index 0000000000..52ee1b3354
--- /dev/null
+++ b/board/katsu/build.mk
@@ -0,0 +1,15 @@
+# -*- makefile -*-
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+#
+# STmicro STM32F098VC
+CHIP:=stm32
+CHIP_FAMILY:=stm32f0
+CHIP_VARIANT:=stm32f09x
+BASEBOARD:=kukui
+
+board-y=board.o led.o
diff --git a/board/katsu/ec.tasklist b/board/katsu/ec.tasklist
new file mode 100644
index 0000000000..8be28c373d
--- /dev/null
+++ b/board/katsu/ec.tasklist
@@ -0,0 +1,20 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG, usb_charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS_RW(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 1024) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, 1280) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, 1024) \
+	TASK_ALWAYS_RO(EMMC, emmc_task, NULL, LARGER_TASK_STACK_SIZE)
+
diff --git a/board/katsu/gpio.inc b/board/katsu/gpio.inc
new file mode 100644
index 0000000000..82f7ddb3af
--- /dev/null
+++ b/board/katsu/gpio.inc
@@ -0,0 +1,107 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first.
+ */
+
+/* Interrupts */
+GPIO_INT(USB_C0_PD_INT_ODL, PIN(B, 1), GPIO_INT_FALLING | GPIO_PULL_UP,
+         tcpc_alert_event)
+GPIO_INT(VOLUME_UP_L,       PIN(B, 10), GPIO_INT_BOTH | GPIO_PULL_UP,
+         button_interrupt) /* EC_VOLUP_BTN_ODL */
+GPIO_INT(VOLUME_DOWN_L,     PIN(B, 11), GPIO_INT_BOTH | GPIO_PULL_UP,
+         button_interrupt) /* EC_VOLDN_BTN_ODL */
+GPIO_INT(POWER_BUTTON_L,    PIN(A, 0),  GPIO_INT_BOTH | GPIO_PULL_UP,
+         power_button_interrupt) /* EC_PWR_BTN_ODL */
+
+GPIO_INT(AP_IN_SLEEP_L,     PIN(C, 12), GPIO_INT_BOTH | GPIO_PULL_DOWN,
+         power_signal_interrupt)
+GPIO_INT(PMIC_EC_RESETB,    PIN(B, 7),  GPIO_INT_BOTH | GPIO_PULL_DOWN,
+         power_signal_interrupt)
+GPIO_INT(WARM_RESET_REQ,    PIN(A, 3),  GPIO_INT_RISING | GPIO_PULL_DOWN,
+         chipset_reset_request_interrupt)
+GPIO_INT(AP_EC_WATCHDOG_L,  PIN(C, 2),  GPIO_INT_FALLING,
+         chipset_watchdog_interrupt)
+
+GPIO_INT_RW(ACCEL_INT_ODL,  PIN(A, 4), GPIO_INT_FALLING | GPIO_SEL_1P8V | GPIO_PULL_UP,
+         icm426xx_interrupt)
+GPIO_INT(CHARGER_INT_ODL,   PIN(C, 13), GPIO_INT_FALLING | GPIO_PULL_UP,
+         rt946x_interrupt)
+GPIO_INT_RO(EMMC_CMD,       PIN(B, 15), GPIO_INT_FALLING,
+         emmc_cmd_interrupt)
+GPIO_INT(SPI1_NSS,          PIN(A, 15), GPIO_INT_BOTH | GPIO_PULL_UP,
+         spi_event)
+GPIO_INT_RW(SYNC_INT,       PIN(A, 8),  GPIO_INT_RISING | GPIO_PULL_DOWN,
+         sync_interrupt)
+GPIO_INT(HALL_INT_L,        PIN(C, 5),  GPIO_INT_BOTH,
+         lid_interrupt)
+GPIO_INT(GAUGE_INT_ODL,     PIN(C, 9),  GPIO_INT_FALLING | GPIO_PULL_UP,
+         gauge_interrupt)
+GPIO_INT(POGO_ADC_INT_L,    PIN(A, 6),  GPIO_INT_BOTH,
+         pogo_adc_interrupt)
+
+/* unused */
+GPIO(POGO_VBUS_PRESENT, PIN(A, 14), GPIO_INPUT)
+/* unused after board rev 5 */
+GPIO(USB_C0_DP_POLARITY,   PIN(C, 14), GPIO_INPUT)
+GPIO(USB_C0_DP_OE_L,       PIN(A, 5),  GPIO_INPUT)
+
+
+/* Reset pins */
+GPIO(AP_SYS_RST_L,         PIN(C, 11), GPIO_OUT_LOW)
+GPIO(PMIC_WATCHDOG_L,      PIN(C, 3),  GPIO_OUT_LOW)
+GPIO(PMIC_EN_ODL,          PIN(C, 10), GPIO_ODR_HIGH)
+GPIO(PMIC_FORCE_RESET_ODL, PIN(A, 2),  GPIO_ODR_HIGH)
+GPIO(MT6370_RST_L,         PIN(F, 0),  GPIO_OUT_LOW)
+
+/*
+ * I2C pins should be configured as inputs until I2C module is
+ * initialized. This will avoid driving the lines unintentionally.
+ */
+GPIO(I2C1_SCL,             PIN(B, 8),  GPIO_INPUT)
+GPIO(I2C1_SDA,             PIN(B, 9),  GPIO_INPUT)
+GPIO(I2C2_SCL,             PIN(A, 11), GPIO_INPUT)
+GPIO(I2C2_SDA,             PIN(A, 12), GPIO_INPUT)
+
+/* Analog pins */
+GPIO(BATT_ID,              PIN(A, 7),  GPIO_ANALOG)
+GPIO(BOARD_ID,             PIN(C, 0),  GPIO_ANALOG)
+GPIO(EC_SKU_ID,            PIN(B, 0),  GPIO_ANALOG)
+
+/* Other input pins */
+GPIO(WP_L,                 PIN(C, 8),  GPIO_INPUT) /* EC_FLASH_WP_ODL */
+GPIO(BOOT0,                PIN(F, 11), GPIO_INPUT)
+GPIO(CCD_MODE_ODL,         PIN(A, 1),  GPIO_INPUT)
+
+/* Other output pins */
+GPIO(ENTERING_RW,          PIN(C, 6),  GPIO_ODR_HIGH) /* EC_ENTERING_RW_ODL */
+GPIO(EC_INT_L,             PIN(B, 12), GPIO_ODR_HIGH) /* EC_AP_INT_ODL */
+GPIO(EC_BOARD_ID_EN_L,     PIN(C, 15), GPIO_ODR_HIGH) /* EC_BOARD_ID_EN_ODL */
+GPIO(USB_C0_HPD_OD,        PIN(F, 1),  GPIO_ODR_LOW)
+GPIO(BOOTBLOCK_EN_L,       PIN(C, 1),  GPIO_ODR_HIGH)
+GPIO(EN_PP3300_POGO,     PIN(A, 13), GPIO_OUT_LOW)
+GPIO(EN_POGO_CHARGE_L,   PIN(B, 6),  GPIO_OUT_HIGH)
+GPIO(EN_USBC_CHARGE_L,   PIN(C, 7),  GPIO_OUT_LOW)
+GPIO(EN_PP5000_USBC,     PIN(D, 2),  GPIO_OUT_LOW)
+GPIO(BC12_DET_EN,        PIN(C, 4),  GPIO_OUT_LOW)
+
+/* USART1: PA9/PA10 */
+ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART,       0)
+/* I2C MASTER: PB8/9 */
+ALTERNATE(PIN_MASK(B, 0x0300), 1, MODULE_I2C,        GPIO_ODR_HIGH )
+/* I2C MASTER: PA11/12 */
+ALTERNATE(PIN_MASK(A, 0x1800), 5, MODULE_I2C,        GPIO_ODR_HIGH )
+/* SPI SLAVE: PB3/4/5 */
+ALTERNATE(PIN_MASK(B, 0x0038), 0, MODULE_SPI,        0)
+#ifdef SECTION_IS_RO
+/* SPI SLAVE: PB13/14/15 */
+ALTERNATE(PIN_MASK(B, 0xE000), 0, MODULE_SPI_FLASH,        0)
+#endif
+/* SPI SLAVE CS: PA15 */
+ALTERNATE(PIN_MASK(A, 0x8000), 0, MODULE_SPI,        0)
diff --git a/board/katsu/led.c b/board/katsu/led.c
new file mode 100644
index 0000000000..64f0982e20
--- /dev/null
+++ b/board/katsu/led.c
@@ -0,0 +1,202 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery LED control for Katsu board.
+ */
+
+#include "battery.h"
+#include "charge_state.h"
+#include "driver/charger/rt946x.h"
+#include "hooks.h"
+#include "led_common.h"
+#include "power.h"
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+#define LED_OFF MT6370_LED_ID_OFF
+#define LED_AMBER MT6370_LED_ID1
+#define LED_WHITE MT6370_LED_ID2
+
+#define LED_MASK_OFF 0
+#define LED_MASK_AMBER MT6370_MASK_RGB_ISNK1DIM_EN
+#define LED_MASK_WHITE MT6370_MASK_RGB_ISNK2DIM_EN
+
+static void katsu_led_set_battery(void)
+{
+	enum led_pwr_state chstate;
+	enum power_state powerstate;
+	static uint8_t prv_white, prv_amber;
+	static uint8_t time_cnt;
+	uint8_t br[EC_LED_COLOR_COUNT] = { 0 };
+
+	chstate = led_pwr_get_state();
+	powerstate = power_get_state();
+
+	switch (chstate) {
+	case LED_PWRS_CHARGE:
+	case LED_PWRS_CHARGE_NEAR_FULL:
+		if (charge_get_percent() < 94) {
+			br[EC_LED_COLOR_AMBER] = 1;
+			br[EC_LED_COLOR_WHITE] = 0;
+			break;
+		}
+		br[EC_LED_COLOR_WHITE] = 1;
+		br[EC_LED_COLOR_AMBER] = 0;
+		break;
+	case LED_PWRS_DISCHARGE:
+		if (powerstate == POWER_S0) {
+			/* display SoC 10% = real battery SoC 13%*/
+			if (charge_get_percent() < 14) {
+				if (time_cnt < 1) {
+					time_cnt++;
+					br[EC_LED_COLOR_WHITE] = 0;
+					br[EC_LED_COLOR_AMBER] = 1;
+				} else {
+					time_cnt++;
+					br[EC_LED_COLOR_WHITE] = 0;
+					br[EC_LED_COLOR_AMBER] = 0;
+					if (time_cnt > 3)
+						time_cnt = 0;
+				}
+				break;
+			}
+			br[EC_LED_COLOR_WHITE] = 1;
+			br[EC_LED_COLOR_AMBER] = 0;
+			break;
+		} else if (powerstate == POWER_S3) {
+			if (time_cnt < 2) {
+				time_cnt++;
+				br[EC_LED_COLOR_WHITE] = 1;
+				br[EC_LED_COLOR_AMBER] = 0;
+			} else {
+				time_cnt++;
+				br[EC_LED_COLOR_WHITE] = 0;
+				br[EC_LED_COLOR_AMBER] = 0;
+				if (time_cnt > 3)
+					time_cnt = 0;
+			}
+			break;
+		} else if (powerstate == POWER_S5 || powerstate == POWER_G3) {
+			br[EC_LED_COLOR_WHITE] = 0;
+			br[EC_LED_COLOR_AMBER] = 0;
+		}
+		break;
+	case LED_PWRS_ERROR:
+		if (powerstate == POWER_S0) {
+			if (time_cnt < 1) {
+				time_cnt++;
+				br[EC_LED_COLOR_WHITE] = 0;
+				br[EC_LED_COLOR_AMBER] = 1;
+			} else {
+				time_cnt++;
+				br[EC_LED_COLOR_WHITE] = 0;
+				br[EC_LED_COLOR_AMBER] = 0;
+				if (time_cnt > 1)
+					time_cnt = 0;
+			}
+			break;
+		} else if (powerstate == POWER_S3) {
+			if (time_cnt < 2) {
+				time_cnt++;
+				br[EC_LED_COLOR_WHITE] = 1;
+				br[EC_LED_COLOR_AMBER] = 0;
+			} else {
+				time_cnt++;
+				br[EC_LED_COLOR_WHITE] = 0;
+				br[EC_LED_COLOR_AMBER] = 0;
+				if (time_cnt > 3)
+					time_cnt = 0;
+			}
+			break;
+		} else if (powerstate == POWER_S5 || powerstate == POWER_G3) {
+			br[EC_LED_COLOR_WHITE] = 0;
+			br[EC_LED_COLOR_AMBER] = 0;
+		}
+		break;
+	default:
+		/* Other states don't alter LED behavior */
+		return;
+	}
+
+	if (prv_white == br[EC_LED_COLOR_WHITE] &&
+	    prv_amber == br[EC_LED_COLOR_AMBER])
+		return;
+
+	prv_white = br[EC_LED_COLOR_WHITE];
+	prv_amber = br[EC_LED_COLOR_AMBER];
+	led_set_brightness(EC_LED_ID_BATTERY_LED, br);
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id != EC_LED_ID_BATTERY_LED)
+		return;
+
+	brightness_range[EC_LED_COLOR_WHITE] = MT6370_LED_BRIGHTNESS_MAX;
+	brightness_range[EC_LED_COLOR_AMBER] = MT6370_LED_BRIGHTNESS_MAX;
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	uint8_t white, amber;
+
+	if (led_id != EC_LED_ID_BATTERY_LED)
+		return EC_ERROR_INVAL;
+
+	white = brightness[EC_LED_COLOR_WHITE];
+	amber = brightness[EC_LED_COLOR_AMBER];
+
+	mt6370_led_set_brightness(LED_WHITE, white);
+	mt6370_led_set_brightness(LED_AMBER, amber);
+
+	/* Enables LED sink power if necessary. */
+	mt6370_led_set_color((white ? LED_MASK_WHITE : 0) |
+			     (amber ? LED_MASK_AMBER : 0));
+	return EC_SUCCESS;
+}
+
+static void katsu_led_init(void)
+{
+	const enum mt6370_led_dim_mode dim = MT6370_LED_DIM_MODE_PWM;
+	const enum mt6370_led_pwm_freq freq = MT6370_LED_PWM_FREQ1000;
+
+	mt6370_led_set_color(0);
+	mt6370_led_set_dim_mode(LED_WHITE, dim);
+	mt6370_led_set_dim_mode(LED_AMBER, dim);
+	mt6370_led_set_pwm_frequency(LED_WHITE, freq);
+	mt6370_led_set_pwm_frequency(LED_AMBER, freq);
+	mt6370_led_set_pwm_dim_duty(LED_WHITE, 255);
+	mt6370_led_set_pwm_dim_duty(LED_AMBER, 255);
+}
+DECLARE_HOOK(HOOK_INIT, katsu_led_init, HOOK_PRIO_DEFAULT);
+
+/* Called by hook task every 1 sec */
+static void led_second(void)
+{
+	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
+		katsu_led_set_battery();
+}
+DECLARE_HOOK(HOOK_SECOND, led_second, HOOK_PRIO_DEFAULT);
+
+__override void led_control(enum ec_led_id led_id, enum ec_led_state state)
+{
+	uint8_t br[EC_LED_COLOR_COUNT] = { 0 };
+
+	if ((led_id != EC_LED_ID_RECOVERY_HW_REINIT_LED) &&
+	    (led_id != EC_LED_ID_SYSRQ_DEBUG_LED))
+		return;
+
+	if (state == LED_STATE_RESET) {
+		led_auto_control(EC_LED_ID_BATTERY_LED, 1);
+		return;
+	}
+
+	if (state)
+		br[EC_LED_COLOR_WHITE] = 1;
+
+	led_auto_control(EC_LED_ID_BATTERY_LED, 0);
+	led_set_brightness(EC_LED_ID_BATTERY_LED, br);
+}
diff --git a/board/katsu/vif_override.xml b/board/katsu/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/katsu/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/kindred/battery.c b/board/kindred/battery.c
index 9db25ac059..a087d0a85f 100644
--- a/board/kindred/battery.c
+++ b/board/kindred/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/kindred/board.c b/board/kindred/board.c
index 0ee52f7095..3358b86583 100644
--- a/board/kindred/board.c
+++ b/board/kindred/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,12 +6,14 @@
 /* Hatch board-specific configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "button.h"
 #include "common.h"
 #include "cros_board_info.h"
 #include "driver/accel_bma2x2.h"
+#include "driver/accel_kionix.h"
 #include "driver/accelgyro_bmi_common.h"
+#include "driver/accelgyro_icm426xx.h"
+#include "driver/accelgyro_icm_common.h"
 #include "driver/bc12/pi3usb9201.h"
 #include "driver/ppc/sn5s330.h"
 #include "driver/tcpm/anx7447.h"
@@ -29,23 +31,26 @@
 #include "power_button.h"
 #include "pwm.h"
 #include "pwm_chip.h"
-#include "stdbool.h"
 #include "spi.h"
+#include "stdbool.h"
 #include "switch.h"
 #include "system.h"
 #include "tablet_mode.h"
 #include "task.h"
 #include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
 #include "thermal.h"
-#include "thermistor.h"
 #include "uart.h"
 #include "usb_charge.h"
 #include "usb_pd.h"
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+static int lid_device_id;
+static int base_device_id;
 
 static void check_reboot_deferred(void);
 DECLARE_DEFERRED(check_reboot_deferred);
@@ -61,17 +66,16 @@ const int usb_port_enable[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT] = {
  * that we don't have pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-		{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-		{0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3},
-		{-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0},
-		{1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4},
-		{2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0},
-		{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1},
-		{-1, -1},
+	{ -1, -1 }, { 0, 5 },	{ 1, 1 },   { 1, 0 },	{ 0, 6 },   { 0, 7 },
+	{ -1, -1 }, { -1, -1 }, { 1, 4 },   { 1, 3 },	{ -1, -1 }, { 1, 6 },
+	{ 1, 7 },   { 3, 1 },	{ 2, 0 },   { 1, 5 },	{ 2, 6 },   { 2, 7 },
+	{ 2, 1 },   { 2, 4 },	{ 2, 5 },   { 1, 2 },	{ 2, 3 },   { 2, 2 },
+	{ 3, 0 },   { -1, -1 }, { -1, -1 }, { -1, -1 }, { -1, -1 }, { -1, -1 },
+	{ -1, -1 },
 };
 
 const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 
 static void ppc_interrupt(enum gpio_signal signal)
 {
@@ -116,11 +120,11 @@ static void bc12_interrupt(enum gpio_signal signal)
 {
 	switch (signal) {
 	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
 		break;
 
 	case GPIO_USB_C1_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12, 0);
+		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
 		break;
 
 	default:
@@ -128,20 +132,21 @@ static void bc12_interrupt(enum gpio_signal signal)
 	}
 }
 
-#include "gpio_list.h" /* Must come after other header files. */
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
 
 /******************************************************************************/
 /* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
+const struct spi_device_t spi_devices[] = {};
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
 /******************************************************************************/
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT]   = { .channel = 3, .flags = 0, .freq = 10000 },
-	[PWM_CH_FAN] = {.channel = 5, .flags = PWM_CONFIG_OPEN_DRAIN,
-			.freq = 25000},
+	[PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 },
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
@@ -161,23 +166,51 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = I2C_PORT_TCPC1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
 		},
 		.drv = &ps8xxx_tcpm_drv,
 		.flags = 0,
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+static int board_anx7447_mux_set_c0(const struct usb_mux *me,
+				    mux_state_t mux_state)
+{
+	int port = me->usb_port;
+	int rv = EC_SUCCESS;
+
+	if (port != USB_PD_PORT_TCPC_0)
+		return rv;
+
+	if (gpio_get_level(GPIO_CCD_MODE_ODL))
+		return rv;
+
+	/*
+	 * Expect to set AUX_SWITCH to 0, but 0xc isolates the DP_AUX
+	 * signal from SBU.
+	 */
+	CPRINTS("C%d: AUX_SW_SEL=0x%x", port, 0xc);
+	if (tcpc_write(port, ANX7447_REG_TCPC_AUX_SWITCH, 0xc))
+		CPRINTS("C%d: Setting AUX_SW_SEL failed", port);
+
+	return rv;
+}
+
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_TCPC_0] = {
-		.usb_port = USB_PD_PORT_TCPC_0,
-		.driver = &anx7447_usb_mux_driver,
-		.hpd_update = &anx7447_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_0,
+			.driver = &anx7447_usb_mux_driver,
+			.board_set = &board_anx7447_mux_set_c0,
+			.hpd_update = &anx7447_tcpc_update_hpd_status,
+		},
 	},
 	[USB_PD_PORT_TCPC_1] = {
-		.usb_port = USB_PD_PORT_TCPC_1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 	}
 };
 
@@ -201,21 +234,94 @@ static struct mutex g_lid_mutex;
 
 /* Base accel private data */
 static struct bmi_drv_data_t g_bmi160_data;
+static struct icm_drv_data_t g_icm426xx_data;
 
 /* BMA255 private data */
 static struct accelgyro_saved_data_t g_bma255_data;
+static struct kionix_accel_data g_kx022_data;
 
 /* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, FLOAT_TO_FP(-1), 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
+
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
+
+static const mat33_fp_t base_icm_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					 { FLOAT_TO_FP(-1), 0, 0 },
+					 { 0, 0, FLOAT_TO_FP(1) } };
+
+struct motion_sensor_t kx022_lid_accel = {
+	.name = "Lid Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_KX022,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_LID,
+	.drv = &kionix_accel_drv,
+	.mutex = &g_lid_mutex,
+	.drv_data = &g_kx022_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = KX022_ADDR0_FLAGS,
+	.rot_standard_ref = &lid_standard_ref,
+	.min_frequency = KX022_ACCEL_MIN_FREQ,
+	.max_frequency = KX022_ACCEL_MAX_FREQ,
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	},
+};
+
+struct motion_sensor_t icm426xx_base_accel = {
+	.name = "Base Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 2, /* g, enough for laptop */
+	.rot_standard_ref = &base_icm_ref,
+	.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
+	.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100,
+		},
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	},
 };
 
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
+struct motion_sensor_t icm426xx_base_gyro = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &base_icm_ref,
+	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
+	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
 };
 
 struct motion_sensor_t motion_sensors[] = {
@@ -264,6 +370,7 @@ struct motion_sensor_t motion_sensors[] = {
 		.config = {
 			[SENSOR_CONFIG_EC_S0] = {
 				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100,
 			},
 			/* Sensor on in S3 */
 			[SENSOR_CONFIG_EC_S3] = {
@@ -296,7 +403,7 @@ unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
@@ -315,58 +422,62 @@ const struct fan_t fans[FAN_CH_COUNT] = {
 /******************************************************************************/
 /* MFT channels. These are logically separate from pwm_channels. */
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN },
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_2] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_3] = {
-		"TEMP_WIFI", NPCX_ADC_CH3, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_1] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_2] = { "TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_3] = { "TEMP_WIFI", NPCX_ADC_CH3, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Temp1",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Temp2",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "Temp3",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_3},
+	[TEMP_SENSOR_1] = { .name = "Temp1",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Temp2",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "Temp3",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
-
 /* Hatch Temperature sensors */
 /*
  * TODO(b/124316213): These setting need to be reviewed and set appropriately
  * for Hatch. They matter when the EC is controlling the fan as opposed to DPTF
  * control.
  */
-const static struct ec_thermal_config thermal_a = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(75),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(55),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(25),
-	.temp_fan_max = C_TO_K(55),
-};
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_A                \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(75), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(55), \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+		.temp_fan_off = C_TO_K(25), \
+		.temp_fan_max = C_TO_K(55), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A;
 
 struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
 
@@ -407,7 +518,6 @@ static void board_gpio_set_pp5000(void)
 	} else if (board_id >= 1) {
 		reset_gpio_flags(GPIO_EN_PP5000_A_V1, GPIO_OUT_LOW);
 	}
-
 }
 
 bool board_is_convertible(void)
@@ -455,6 +565,55 @@ static void board_init(void)
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
+static void determine_accel_devices(void)
+{
+	static uint8_t read_time;
+
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return;
+
+	if (read_time == 0 && board_is_convertible()) {
+		/* Read g sensor chip id*/
+		i2c_read8(I2C_PORT_ACCEL, KX022_ADDR0_FLAGS, KX022_WHOAMI,
+			  &lid_device_id);
+		/* Read gyro sensor id*/
+		i2c_read8(I2C_PORT_ACCEL, ICM426XX_ADDR0_FLAGS,
+			  ICM426XX_REG_WHO_AM_I, &base_device_id);
+
+		CPRINTS("Motion Sensor Base id = %d Lid id =%d", base_device_id,
+			lid_device_id);
+
+		if (lid_device_id == KX022_WHO_AM_I_VAL) {
+			motion_sensors[LID_ACCEL] = kx022_lid_accel;
+			ccprints("Lid Accel is KX022");
+		} else
+			ccprints("Lid Accel is BMA255");
+
+		if (base_device_id == ICM426XX_CHIP_ICM40608) {
+			motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
+			motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
+			ccprints("BASE Accel is ICM426XX");
+		} else
+			ccprints("BASE Accel is BMI160");
+
+		read_time++;
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, determine_accel_devices, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_INIT, determine_accel_devices, HOOK_PRIO_INIT_ADC + 2);
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	switch (base_device_id) {
+	case ICM426XX_CHIP_ICM40608:
+		icm426xx_interrupt(signal);
+		break;
+	default:
+		bmi160_interrupt(signal);
+		break;
+	}
+}
+
 void board_overcurrent_event(int port, int is_overcurrented)
 {
 	/* Check that port number is valid. */
@@ -489,7 +648,8 @@ __override void board_chipset_forced_shutdown(void)
 {
 	hook_call_deferred(&check_reboot_deferred_data, -1);
 }
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_forced_shutdown, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_forced_shutdown,
+	     HOOK_PRIO_DEFAULT);
 
 static void check_reboot_deferred(void)
 {
diff --git a/board/kindred/board.h b/board/kindred/board.h
index 54c2d173d7..1372887446 100644
--- a/board/kindred/board.h
+++ b/board/kindred/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,13 +12,13 @@
 #include "baseboard.h"
 
 #define CONFIG_POWER_BUTTON
-#undef  CONFIG_POWER_BUTTON_INIT_TIMEOUT
+#undef CONFIG_POWER_BUTTON_INIT_TIMEOUT
 #define CONFIG_POWER_BUTTON_INIT_TIMEOUT 2
 #define CONFIG_KEYBOARD_PROTOCOL_8042
 #define CONFIG_LED_COMMON
 #define CONFIG_LOW_POWER_IDLE
 
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 
 #undef CONFIG_UART_TX_BUF_SIZE
 #define CONFIG_UART_TX_BUF_SIZE 4096
@@ -31,13 +31,19 @@
 
 /* Sensors */
 /* BMI160 Base accel/gyro */
-#define CONFIG_ACCEL_INTERRUPTS
+
 #define CONFIG_ACCELGYRO_BMI160
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+#define CONFIG_ACCELGYRO_ICM426XX
+#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
 #define CONFIG_ACCELGYRO_BMI160_INT2_OUTPUT
 /* BMA253 Lid accel */
 #define CONFIG_ACCEL_BMA255
+#define CONFIG_ACCEL_KX022
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
 #define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
@@ -86,7 +92,7 @@
 #define CONFIG_FANS 1
 #undef CONFIG_FAN_INIT_SPEED
 #define CONFIG_FAN_INIT_SPEED 50
-#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_A_RAILS
+#define CONFIG_TEMP_SENSOR_POWER
 #define CONFIG_THERMISTOR
 #define CONFIG_THROTTLE_AP
 #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
@@ -105,15 +111,16 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_AC_PRESENT		GPIO_ACOK_OD
-#define GPIO_RSMRST_L_PGOOD	GPIO_PG_EC_RSMRST_L
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L
+#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
 
 #ifndef __ASSEMBLER__
 #include "gpio_signal.h"
@@ -124,9 +131,9 @@
 extern enum gpio_signal gpio_en_pp5000_a;
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_1,	/* ADC0 */
-	ADC_TEMP_SENSOR_2,	/* ADC1 */
-	ADC_TEMP_SENSOR_3,	/* ADC3 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
+	ADC_TEMP_SENSOR_3, /* ADC3 */
 	ADC_CH_COUNT
 };
 
@@ -137,11 +144,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_FAN,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_FAN, PWM_CH_COUNT };
 
 enum fan_channel {
 	FAN_CH_0 = 0,
@@ -172,8 +175,9 @@ enum battery_type {
 /* Sensors without hardware FIFO are in forced mode */
 #define CONFIG_ACCEL_FORCE_MODE_MASK (1 << LID_ACCEL)
 
-extern const int keyboard_factory_scan_pins[][2];
-extern const int keyboard_factory_scan_pins_used;
+void motion_interrupt(enum gpio_signal signal);
+
+void ccd_mode_isr(enum gpio_signal signal);
 
 #endif /* !__ASSEMBLER__ */
 
diff --git a/board/kindred/build.mk b/board/kindred/build.mk
index 733912454f..13153c1526 100644
--- a/board/kindred/build.mk
+++ b/board/kindred/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/kindred/ec.tasklist b/board/kindred/ec.tasklist
index 4a1024a091..829be2b7c8 100644
--- a/board/kindred/ec.tasklist
+++ b/board/kindred/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/kindred/gpio.inc b/board/kindred/gpio.inc
index 91b41a4730..cde4305f16 100644
--- a/board/kindred/gpio.inc
+++ b/board/kindred/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,10 +16,10 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(PG_EC_RSMRST_L,       PIN(E, 2), GPIO_INT_BOTH, intel_x86_rsmrst_signal_interrupt)
@@ -27,7 +27,7 @@ GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
 GPIO_INT(PP5000_A_PG_OD,       PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
 
 /* Sensor Interrupts */
-GPIO_INT(BASE_SIXAXIS_INT_L,   PIN(5, 6), GPIO_INT_FALLING, bmi160_interrupt)
+GPIO_INT(BASE_SIXAXIS_INT_L,   PIN(5, 6), GPIO_INT_FALLING, motion_interrupt)
 
 /* USB-C interrupts */
 GPIO_INT(USB_C0_PPC_INT_ODL,   PIN(E, 0), GPIO_INT_FALLING, ppc_interrupt)
@@ -37,6 +37,9 @@ GPIO_INT(USB_C1_TCPC_INT_ODL,  PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)
 GPIO_INT(USB_C0_BC12_INT_ODL,  PIN(9, 5), GPIO_INT_FALLING, bc12_interrupt)
 GPIO_INT(USB_C1_BC12_INT_ODL,  PIN(E, 4), GPIO_INT_FALLING, bc12_interrupt)
 
+/* CCD mode line*/
+GPIO(CCD_MODE_ODL,             PIN(E, 5), GPIO_INPUT)
+
 GPIO_INT(HDMI_CONN_HPD,        PIN(7, 2), GPIO_INT_BOTH, hdmi_hpd_interrupt)
 
 /* Volume button interrupts */
diff --git a/board/kindred/led.c b/board/kindred/led.c
index f47ee7e101..21be931889 100644
--- a/board/kindred/led.c
+++ b/board/kindred/led.c
@@ -1,44 +1,50 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Power and battery LED control for Hatch
  */
 
+#include "chipset.h"
 #include "ec_commands.h"
 #include "gpio.h"
 #include "led_common.h"
 #include "led_onoff_states.h"
-#include "chipset.h"
 
 #define LED_ON_LVL 0
 #define LED_OFF_LVL 1
 
-const int led_charge_lvl_1 = 5;
+__override const int led_charge_lvl_1 = 5;
 
-const int led_charge_lvl_2 = 95;
+__override const int led_charge_lvl_2 = 95;
 
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-void led_set_color_battery(enum ec_led_colors color)
+__override void led_set_color_battery(enum ec_led_colors color)
 {
 	switch (color) {
 	case EC_LED_COLOR_AMBER:
@@ -77,4 +83,3 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 
 	return EC_SUCCESS;
 }
-
diff --git a/board/kindred/vif_override.xml b/board/kindred/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/kindred/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/kingoftown/battery.c b/board/kingoftown/battery.c
new file mode 100644
index 0000000000..3a74f99907
--- /dev/null
+++ b/board/kingoftown/battery.c
@@ -0,0 +1,160 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "common.h"
+#include "util.h"
+
+/*
+ * Battery info for all kingoftown battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+
+const struct board_batt_params board_battery_info[] = {
+	/* DynaPack HIGHPOWER Battery Information */
+	[BATTERY_DYNAPACK_HIGHPOWER] = {
+		.fuel_gauge = {
+			.manuf_name = "333-2D-0D-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,	/* mV */
+			.voltage_normal = 7700,
+			.voltage_min = 6000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+			.vendor_param_start = 0x70,
+		},
+	},
+
+	/* DynaPack BYD Battery Information */
+	[BATTERY_DYNAPACK_BYD] = {
+		.fuel_gauge = {
+			.manuf_name = "333-2E-0D-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,	/* mV */
+			.voltage_normal = 7700,
+			.voltage_min = 6000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+			.vendor_param_start = 0x70,
+		},
+	},
+
+	/* CosMX Battery Information */
+	[BATTERY_COS] = {
+		.fuel_gauge = {
+			.manuf_name = "333-AC-0D-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,	/* mV */
+			.voltage_normal = 7700,
+			.voltage_min = 6000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+			.vendor_param_start = 0x70,
+		},
+	},
+
+	/* ATL GB-S20-4473A9-01H&020H Battery Information
+	 * Gauge IC : RAJ240045
+	 */
+	[BATTERY_ATL] = {
+		.fuel_gauge = {
+			.manuf_name = "313-B7-0D-A",
+			.ship_mode = {
+				.reg_addr = 0x0,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 0,
+				.reg_addr = 0x43,
+				.reg_mask = 0x0003,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,		/* mV */
+			.voltage_normal = 7700,		/* mV */
+			.voltage_min = 6000,		/* mV */
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+			.vendor_param_start = 0x70,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_DYNAPACK_HIGHPOWER;
diff --git a/board/kingoftown/board.c b/board/kingoftown/board.c
new file mode 100644
index 0000000000..b8bbd08d2e
--- /dev/null
+++ b/board/kingoftown/board.c
@@ -0,0 +1,251 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Kingoftown board-specific configuration */
+
+#include "adc_chip.h"
+#include "button.h"
+#include "driver/accel_bma2x2.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "shi_chip.h"
+#include "switch.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/* Use 80 us, because KSO_02 passes through the H1. */
+	.output_settle_us = 80,
+	/*
+	 * Unmask 0x08 in [0] (KSO_00/KSI_03, the new location of Search key);
+	 * as it still uses the legacy location (KSO_01/KSI_00).
+	 */
+	.actual_key_mask = { 0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, 0xa4,
+			     0xff, 0xfe, 0x55, 0xfa, 0xca },
+	/* Other values should be the same as the default configuration. */
+	.debounce_down_us = 9 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+};
+
+/*
+ * Map keyboard connector pins to EC GPIO pins for factory test.
+ * Pins mapped to {-1, -1} are skipped.
+ * The connector has 24 pins total, and there is no pin 0.
+ */
+const int keyboard_factory_scan_pins[][2] = {
+	{ -1, -1 }, { 0, 5 }, { 1, 1 },	  { 1, 0 },   { 0, 6 },
+	{ 0, 7 },   { 1, 4 }, { 1, 3 },	  { 1, 6 },   { 1, 7 },
+	{ 3, 1 },   { 2, 0 }, { 1, 5 },	  { 2, 6 },   { 2, 7 },
+	{ 2, 1 },   { 2, 4 }, { 2, 5 },	  { 1, 2 },   { 2, 3 },
+	{ 2, 2 },   { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 },
+};
+const int keyboard_factory_scan_pins_used =
+	ARRAY_SIZE(keyboard_factory_scan_pins);
+
+/* I2C port map */
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_POWER_SCL,
+	  .sda = GPIO_EC_I2C_POWER_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C0_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C0_PD_SDA },
+	{ .name = "tcpc1",
+	  .port = I2C_PORT_TCPC1,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C1_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C1_PD_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_EEPROM_SCL,
+	  .sda = GPIO_EC_I2C_EEPROM_SDA },
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_SENSOR_SCL,
+	  .sda = GPIO_EC_I2C_SENSOR_SDA },
+};
+
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	/* Measure VBUS through a 1/10 voltage divider */
+	[ADC_VBUS] = { "VBUS", NPCX_ADC_CH1, ADC_MAX_VOLT * 10,
+		       ADC_READ_MAX + 1, 0 },
+	/*
+	 * Adapter current output or battery charging/discharging current (uV)
+	 * 18x amplification on charger side.
+	 */
+	[ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH2, ADC_MAX_VOLT * 1000 / 18,
+			    ADC_READ_MAX + 1, 0 },
+	/*
+	 * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read
+	 * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and
+	 * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we
+	 * only divide by 2 (enough to avoid precision issues).
+	 */
+	[ADC_PSYS] = { "PSYS", NPCX_ADC_CH3,
+		       ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), 2, 0 },
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 },
+	/* TODO(waihong): Assign a proper frequency. */
+	[PWM_CH_DISPLIGHT] = { .channel = 5, .flags = 0, .freq = 4800 },
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+/* Initialize board. */
+static void board_init(void)
+{
+	/* Enable interrupt for BMI160 sensor */
+	gpio_enable_interrupt(GPIO_ACCEL_GYRO_INT_L);
+
+	/* Set the backlight duty cycle to 0. AP will override it later. */
+	pwm_set_duty(PWM_CH_DISPLIGHT, 0);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S0 -> S3 transition */
+static void board_chipset_suspend(void)
+{
+	/*
+	 * Turn off display backlight in S3. AP has its own control. The EC's
+	 * and the AP's will be AND'ed together in hardware.
+	 */
+	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 0);
+	pwm_enable(PWM_CH_DISPLIGHT, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S3 -> S0 transition */
+static void board_chipset_resume(void)
+{
+	/* Turn on display and keyboard backlight in S0. */
+	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 1);
+	if (pwm_get_duty(PWM_CH_DISPLIGHT))
+		pwm_enable(PWM_CH_DISPLIGHT, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
+
+/* Mutexes */
+static struct mutex g_base_mutex;
+static struct mutex g_lid_mutex;
+
+static struct bmi_drv_data_t g_bmi160_data;
+static struct accelgyro_saved_data_t g_bma255_data;
+
+/* Matrix to rotate accelerometer into standard reference frame */
+const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+				       { 0, FLOAT_TO_FP(-1), 0 },
+				       { 0, 0, FLOAT_TO_FP(-1) } };
+
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					     { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
+
+struct motion_sensor_t motion_sensors[] = {
+	[LID_ACCEL] = {
+	 .name = "Lid Accel",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_BMA255,
+	 .type = MOTIONSENSE_TYPE_ACCEL,
+	 .location = MOTIONSENSE_LOC_LID,
+	 .drv = &bma2x2_accel_drv,
+	 .mutex = &g_lid_mutex,
+	 .drv_data = &g_bma255_data,
+	 .port = I2C_PORT_SENSOR,
+	 .i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
+	 .rot_standard_ref = &lid_standard_ref,
+	 .default_range = 2, /* g, to support lid angle calculation. */
+	 .min_frequency = BMA255_ACCEL_MIN_FREQ,
+	 .max_frequency = BMA255_ACCEL_MAX_FREQ,
+	 .config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+		/* Sensor on for lid angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	 },
+	},
+	/*
+	 * Note: bmi160: supports accelerometer and gyro sensor
+	 * Requirement: accelerometer sensor must init before gyro sensor
+	 * DO NOT change the order of the following table.
+	 */
+	[BASE_ACCEL] = {
+	 .name = "Base Accel",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_BMI160,
+	 .type = MOTIONSENSE_TYPE_ACCEL,
+	 .location = MOTIONSENSE_LOC_BASE,
+	 .drv = &bmi160_drv,
+	 .mutex = &g_base_mutex,
+	 .drv_data = &g_bmi160_data,
+	 .port = I2C_PORT_SENSOR,
+	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+	 .rot_standard_ref = &base_standard_ref,
+	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
+	 .min_frequency = BMI_ACCEL_MIN_FREQ,
+	 .max_frequency = BMI_ACCEL_MAX_FREQ,
+	 .config = {
+		 [SENSOR_CONFIG_EC_S0] = {
+			 .odr = 10000 | ROUND_UP_FLAG,
+		 },
+		 /* Sensor on for lid angle detection */
+		 [SENSOR_CONFIG_EC_S3] = {
+			 .odr = 10000 | ROUND_UP_FLAG,
+		 },
+	 },
+	},
+	[BASE_GYRO] = {
+	 .name = "Gyro",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_BMI160,
+	 .type = MOTIONSENSE_TYPE_GYRO,
+	 .location = MOTIONSENSE_LOC_BASE,
+	 .drv = &bmi160_drv,
+	 .mutex = &g_base_mutex,
+	 .drv_data = &g_bmi160_data,
+	 .port = I2C_PORT_SENSOR,
+	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+	 .default_range = 1000, /* dps */
+	 .rot_standard_ref = &base_standard_ref,
+	 .min_frequency = BMI_GYRO_MIN_FREQ,
+	 .max_frequency = BMI_GYRO_MAX_FREQ,
+	},
+};
+const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
diff --git a/board/kingoftown/board.h b/board/kingoftown/board.h
new file mode 100644
index 0000000000..6b553f65fa
--- /dev/null
+++ b/board/kingoftown/board.h
@@ -0,0 +1,103 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Kingoftown board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "baseboard.h"
+
+/* Internal SPI flash on NPCX7 */
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */
+
+/* Keyboard */
+#define CONFIG_KEYBOARD_PROTOCOL_MKBP
+#define CONFIG_KEYBOARD_REFRESH_ROW3
+
+#define CONFIG_PWM_KBLIGHT
+
+/* Battery */
+#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
+#define CONFIG_BATTERY_REVIVE_DISCONNECT
+#define CONFIG_BATTERY_FUEL_GAUGE
+#define CONFIG_BATTERY_VENDOR_PARAM
+
+/* BC 1.2 Charger */
+#define CONFIG_BC12_DETECT_PI3USB9201
+
+/* USB */
+#define CONFIG_USB_PD_TCPM_PS8805
+#define CONFIG_USB_PD_TCPM_PS8805_FORCE_DID
+#define CONFIG_USBC_PPC_SN5S330
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+
+/* USB-A */
+#define USB_PORT_COUNT 1
+#define CONFIG_USB_PORT_POWER_DUMB
+
+/* No side volume button */
+#undef CONFIG_VOLUME_BUTTONS
+
+/* Sensors */
+/* BMI160 Base accel/gyro */
+#define CONFIG_ACCELGYRO_BMI160
+#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+#define OPT3001_I2C_ADDR_FLAGS OPT3001_I2C_ADDR1_FLAGS
+
+/* BMA253 lid accel */
+#define CONFIG_ACCEL_BMA255
+#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
+
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+#define CONFIG_LID_ANGLE_UPDATE
+
+/* GPIO alias */
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_WP_L GPIO_EC_WP_ODL
+#define GPIO_SWITCHCAP_PG GPIO_SWITCHCAP_GPIO_1
+#define GPIO_ACOK_OD GPIO_CHG_ACOK_OD
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum adc_channel { ADC_VBUS, ADC_AMON_BMON, ADC_PSYS, ADC_CH_COUNT };
+
+/* Motion sensors */
+enum sensor_id {
+	LID_ACCEL = 0,
+	BASE_ACCEL,
+	BASE_GYRO,
+	SENSOR_COUNT,
+};
+
+enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_DISPLIGHT, PWM_CH_COUNT };
+
+/* List of possible batteries */
+enum battery_type {
+	BATTERY_DYNAPACK_HIGHPOWER,
+	BATTERY_DYNAPACK_BYD,
+	BATTERY_COS,
+	BATTERY_ATL,
+	BATTERY_TYPE_COUNT,
+};
+
+/* Reset all TCPCs. */
+void board_reset_pd_mcu(void);
+void board_set_tcpc_power_mode(int port, int mode);
+
+/* support factory keyboard test */
+#define CONFIG_KEYBOARD_FACTORY_TEST
+extern const int keyboard_factory_scan_pins[][2];
+extern const int keyboard_factory_scan_pins_used;
+
+#endif /* !defined(__ASSEMBLER__) */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/kingoftown/build.mk b/board/kingoftown/build.mk
new file mode 100644
index 0000000000..2c5eb4ae2e
--- /dev/null
+++ b/board/kingoftown/build.mk
@@ -0,0 +1,19 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx7
+CHIP_VARIANT:=npcx7m6fc
+BASEBOARD:=trogdor
+
+board-y+=battery.o
+board-y+=board.o
+board-y+=hibernate.o
+board-y+=led.o
+board-y+=switchcap.o
+board-y+=usbc_config.o
diff --git a/board/kingoftown/ec.tasklist b/board/kingoftown/ec.tasklist
new file mode 100644
index 0000000000..228828af3c
--- /dev/null
+++ b/board/kingoftown/ec.tasklist
@@ -0,0 +1,23 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/kingoftown/gpio.inc b/board/kingoftown/gpio.inc
new file mode 100644
index 0000000000..7147869ea3
--- /dev/null
+++ b/board/kingoftown/gpio.inc
@@ -0,0 +1,187 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+/* USB interrupts */
+GPIO_INT(USB_C0_PD_INT_ODL,    PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-0 TCPC */
+GPIO_INT(USB_C1_PD_INT_ODL,    PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-1 TCPC */
+GPIO_INT(USB_C0_SWCTL_INT_ODL, PIN(0, 3), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-0 PPC */
+GPIO_INT(USB_C1_SWCTL_INT_ODL, PIN(4, 0), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-1 PPC */
+GPIO_INT(USB_C0_BC12_INT_L,    PIN(6, 1), GPIO_INT_FALLING | GPIO_PULL_UP, usb0_evt)  /* Interrupt from port-0 BC1.2 */
+GPIO_INT(USB_C1_BC12_INT_L,    PIN(8, 2), GPIO_INT_FALLING | GPIO_PULL_UP, usb1_evt)  /* Interrupt from port-1 BC1.2 */
+GPIO_INT(USB_A0_OC_ODL,        PIN(D, 1), GPIO_INT_BOTH | GPIO_PULL_UP, usba_oc_interrupt)
+
+/* System interrupts */
+GPIO_INT(CHG_ACOK_OD,       PIN(0, 0), GPIO_INT_BOTH, extpower_interrupt)  /* ACOK */
+GPIO_INT(EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)  /* Power button */
+GPIO_INT(EC_WP_ODL,         PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)  /* Write protection */
+GPIO_INT(LID_OPEN_EC,       PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)  /* Lid open */
+GPIO_INT(AP_RST_L,          PIN(C, 1), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_ap_rst_interrupt)  /* PMIC to signal AP reset */
+GPIO_INT(PS_HOLD,           PIN(A, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, power_signal_interrupt)  /* Indicate when AP triggers reset/shutdown */
+GPIO_INT(AP_SUSPEND,        PIN(5, 7), GPIO_INT_BOTH, power_signal_interrupt)  /* Suspend signal from PMIC */
+GPIO_INT(DEPRECATED_AP_RST_REQ, PIN(C, 2), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V, power_signal_interrupt) /* Deprecated AP initiated reset indicator */
+/*
+ * When switch-cap is off, the POWER_GOOD signal is floating. Need a pull-down
+ * to make it low. Overload the interrupt function chipset_warm_reset_interrupt
+ * for not only signalling power_signal_interrupt but also handling the logic
+ * of WARM_RESET_L which is pulled-up by the same rail of POWER_GOOD.
+ */
+GPIO_INT(POWER_GOOD,        PIN(5, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, chipset_power_good_interrupt)  /* SRC_PP1800_S10A from PMIC */
+GPIO_INT(WARM_RESET_L,      PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_warm_reset_interrupt)  /* AP warm reset */
+GPIO_INT(AP_EC_SPI_CS_L,    PIN(5, 3), GPIO_INT_FALLING | GPIO_PULL_DOWN, shi_cs_event)  /* EC SPI Chip Select */
+
+/* Sensor interrupts */
+GPIO_INT(ACCEL_GYRO_INT_L,  PIN(A, 0), GPIO_INT_FALLING, bmi160_interrupt)  /* Accelerometer/gyro interrupt */
+
+/*
+ * EC_RST_ODL used to be a wake source from PSL mode. However, we disabled
+ * the PSL mode. This GPIO does nothing now. Simply set it an INPUT.
+ */
+GPIO(EC_RST_ODL,            PIN(0, 2), GPIO_INPUT)     /* EC reset */
+GPIO(EC_ENTERING_RW,        PIN(E, 1), GPIO_OUT_LOW)   /* Indicate when EC is entering RW code */
+GPIO(CCD_MODE_ODL,          PIN(E, 3), GPIO_INPUT)     /* Case Closed Debug Mode */
+GPIO(EC_BATT_PRES_ODL,      PIN(E, 5), GPIO_INPUT)     /* Battery Present */
+
+/* PMIC/AP 1.8V */
+GPIO(PMIC_RESIN_L,          PIN(3, 2), GPIO_ODR_HIGH)  /* PMIC reset trigger */
+GPIO(PMIC_KPD_PWR_ODL,      PIN(D, 6), GPIO_ODR_HIGH)  /* PMIC power button */
+GPIO(EC_INT_L,              PIN(A, 2), GPIO_ODR_HIGH)  /* Interrupt line between AP and EC */
+
+/* Power enables */
+GPIO(HIBERNATE_L,           PIN(5, 2), GPIO_ODR_HIGH)  /* EC hibernate */
+GPIO(SWITCHCAP_ON,          PIN(D, 5), GPIO_OUT_LOW)   /* Enable switch cap */
+GPIO(EN_PP3300_A,           PIN(A, 6), GPIO_OUT_LOW)   /* Enable PP3300 */
+GPIO(EN_PP5000_A,           PIN(6, 7), GPIO_OUT_LOW)   /* Enable PP5000 */
+GPIO(EC_BL_DISABLE_L,       PIN(B, 6), GPIO_OUT_LOW)   /* Backlight disable signal from EC */
+
+/* Sensors */
+GPIO(LID_ACCEL_INT_L,       PIN(5, 6), GPIO_INPUT)     /* Lid accel sensor interrupt */
+/* Control the gate for trackpad IRQ. High closes the gate.
+ * This is always set low so that the OS can manage the trackpad. */
+GPIO(TRACKPAD_INT_GATE,     PIN(7, 4), GPIO_OUT_LOW)
+
+/* USB-C */
+GPIO(USB_C0_PD_RST_L,       PIN(F, 1), GPIO_OUT_HIGH)  /* Port-0 TCPC chip reset */
+GPIO(USB_C1_PD_RST_L,       PIN(E, 4), GPIO_OUT_HIGH)  /* Port-1 TCPC chip reset */
+GPIO(DP_MUX_OE_L,           PIN(9, 6), GPIO_ODR_HIGH)  /* DP mux enable, actually Open-Drain */
+GPIO(DP_MUX_SEL,            PIN(4, 5), GPIO_OUT_LOW)   /* DP mux selection: L:C0, H:C1 */
+GPIO(DP_HOT_PLUG_DET,       PIN(9, 5), GPIO_OUT_LOW)   /* DP HPD to AP */
+
+/* USB-A */
+GPIO(EN_USB_A_5V,           PIN(8, 6), GPIO_OUT_LOW)
+GPIO(USB_A_CDP_ILIM_EN_L,   PIN(7, 5), GPIO_OUT_HIGH)  /* H:CDP, L:SDP. Only one USB-A port, always CDP */
+
+/* LEDs */
+GPIO(EC_CHG_LED_Y_C0,       PIN(6, 0), GPIO_OUT_LOW)
+GPIO(EC_CHG_LED_W_C0,       PIN(C, 0), GPIO_OUT_LOW)
+GPIO(EC_CHG_LED_Y_C1,       PIN(C, 3), GPIO_OUT_LOW)
+GPIO(EC_CHG_LED_W_C1,       PIN(C, 4), GPIO_OUT_LOW)
+
+/*
+ * SPI host interface - enable PDs by default. These will be made functional
+ * by the SHI driver when the AP powers up, and restored back to GPIO when
+ * the AP powers down.
+ */
+GPIO(AP_EC_SPI_MOSI,        PIN(4, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(AP_EC_SPI_MISO,        PIN(4, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(AP_EC_SPI_CLK,         PIN(5, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+
+/* PWM */
+GPIO(KB_BL_PWM,             PIN(8, 0), GPIO_INPUT)     /* PWM3 */
+GPIO(EDP_BKLTCTL,           PIN(B, 7), GPIO_INPUT)     /* PWM5 */
+
+/* ADC */
+GPIO(PPVAR_BOOSTIN_SENSE,   PIN(4, 4), GPIO_INPUT)     /* ADC1 */
+GPIO(CHARGER_IADP,          PIN(4, 3), GPIO_INPUT)     /* ADC2 */
+GPIO(CHARGER_PMON,          PIN(4, 2), GPIO_INPUT)     /* ADC3 */
+
+/* I2C */
+GPIO(EC_I2C_POWER_SCL,      PIN(B, 5), GPIO_INPUT)
+GPIO(EC_I2C_POWER_SDA,      PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_PD_SCL,  PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_PD_SDA,  PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_PD_SCL,  PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_PD_SDA,  PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SCL,     PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SDA,     PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,     PIN(B, 3), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SENSOR_SDA,     PIN(B, 2), GPIO_INPUT | GPIO_SEL_1P8V)
+
+/* Board/SKU IDs */
+GPIO(BRD_ID0,               PIN(C, 7), GPIO_INPUT)
+GPIO(BRD_ID1,               PIN(9, 3), GPIO_INPUT)
+GPIO(BRD_ID2,               PIN(6, 3), GPIO_INPUT)
+GPIO(SKU_ID0,               PIN(F, 0), GPIO_INPUT)
+GPIO(SKU_ID1,               PIN(4, 1), GPIO_INPUT)
+GPIO(SKU_ID2,               PIN(D, 4), GPIO_INPUT)
+
+/* Switchcap */
+/*
+ * GPIO0 is configured as PVC_PG. When the chip in power down mode, it outputs
+ * high-Z. Set pull-down to avoid floating.
+ */
+GPIO(SWITCHCAP_GPIO_1,      PIN(E, 2), GPIO_INPUT | GPIO_PULL_DOWN) /* Switchcap GPIO0 */
+
+/* Special straps */
+GPIO(ARM_X86,               PIN(6, 6), GPIO_OUT_LOW)  /* NC, low for power saving */
+
+/* Unused GPIOs, NC. */
+UNUSED(PIN(5, 1))
+UNUSED(PIN(D, 0))
+UNUSED(PIN(F, 3))
+UNUSED(PIN(9, 4))
+UNUSED(PIN(9, 7))
+UNUSED(PIN(A, 7))
+UNUSED(PIN(B, 0))
+UNUSED(PIN(A, 5))
+UNUSED(PIN(3, 5))
+UNUSED(PIN(7, 2))
+UNUSED(PIN(8, 1))
+UNUSED(PIN(3, 7))
+UNUSED(PIN(7, 6))
+UNUSED(PIN(3, 4))
+UNUSED(PIN(C, 5))
+UNUSED(PIN(7, 3))
+UNUSED(PIN(D, 7))
+UNUSED(PIN(A, 3))
+UNUSED(PIN(6, 2))
+UNUSED(PIN(0, 4))
+UNUSED(PIN(8, 3))
+UNUSED(PIN(B, 1))
+UNUSED(PIN(5, 0))
+UNUSED(PIN(D, 3))
+UNUSED(PIN(C, 6))
+UNUSED(PIN(7, 0))
+UNUSED(PIN(F, 2))
+
+/* Alternate functions GPIO definitions */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)            /* UART (GPIO64/65) */
+ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0)             /* I2C0 (GPIOB4/B5) */
+ALTERNATE(PIN_MASK(9, 0x07), 1, MODULE_I2C, 0)             /* I2C1 SDA (GPIO90), I2C2 (GPIO91/92) */
+ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, 0)             /* I2C1 SCL (GPIO87) */
+ALTERNATE(PIN_MASK(3, 0x48), 1, MODULE_I2C, 0)             /* I2C5 (GPIO33/36) */
+ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, GPIO_SEL_1P8V) /* I2C7 (GPIOB2/B3) - 1.8V */
+ALTERNATE(PIN_MASK(4, 0x1C), 0, MODULE_ADC, 0)             /* ADC1 (GPIO44), ADC2 (GPIO43), ADC3 (GPIO42) */
+ALTERNATE(PIN_MASK(4, 0xC0), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SDO (GPIO47), SHI_SDI (GPIO46) */
+ALTERNATE(PIN_MASK(5, 0x28), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SCLK (GPIO55), SHI_CS# (GPIO53) */
+ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)             /* PWM3 (GPIO80) - KB_BL_PWM */
+ALTERNATE(PIN_MASK(B, 0x80), 1, MODULE_PWM, 0)             /* PWM5 (GPIOB7) - EDP_BKLTCTL */
+
+/* Keyboard */
+#define GPIO_KB_INPUT           (GPIO_INPUT | GPIO_PULL_UP)
+#define GPIO_KB_OUTPUT          (GPIO_ODR_HIGH)
+#define GPIO_KB_OUTPUT_COL2     (GPIO_OUT_LOW)
+
+/* Keyboard alternate functions */
+ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)  /* KSO10 (GPIO07), KSO11 (GPIO06), KSO12 (GPIO05) */
+ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)  /* KSO03 (GPIO16), KSO04 (GPIO15), KSO05 (GPIO14), KSO06 (GPIO13), KSO07 (GPIO12), KSO08 (GPIO11), KSO09 (GPIO10) */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)  /* KSO00 (GPIO21), KSO01 (GPIO20) */
+ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)   /* KSI2 (GPIO27), KSI3 (GPIO26), KSI4 (GPIO25), KSI5 (GPIO24), KSI6 (GPIO23), KSI7 (GPIO22) */
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)   /* KSI0 (GPIO31), KSI1 (GPIO30) */
+GPIO(EC_KSO_02_INV,       PIN(1, 7), GPIO_KB_OUTPUT_COL2)              /* KSO02 (GPIO17) */
diff --git a/board/kingoftown/hibernate.c b/board/kingoftown/hibernate.c
new file mode 100644
index 0000000000..9b64e85053
--- /dev/null
+++ b/board/kingoftown/hibernate.c
@@ -0,0 +1,16 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "gpio.h"
+
+void board_hibernate(void)
+{
+	/*
+	 * Sensors are unpowered in hibernate. Apply PD to the
+	 * interrupt lines such that they don't float.
+	 */
+	gpio_set_flags(GPIO_ACCEL_GYRO_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
+	gpio_set_flags(GPIO_LID_ACCEL_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
+}
diff --git a/board/kingoftown/led.c b/board/kingoftown/led.c
new file mode 100644
index 0000000000..1a7f503cb7
--- /dev/null
+++ b/board/kingoftown/led.c
@@ -0,0 +1,210 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power and battery LED control.
+ */
+
+#include "battery.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "chipset.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "led_common.h"
+#include "system.h"
+#include "util.h"
+
+/* Times of tick per 1 second */
+#define TIMES_TICK_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS)
+/* Times of tick per half second */
+#define TIMES_TICK_HALF_SEC (500 / HOOK_TICK_INTERVAL_MS)
+
+#define BAT_LED_ON 1
+#define BAT_LED_OFF 0
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_LEFT_LED,
+	EC_LED_ID_RIGHT_LED,
+};
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+enum led_color {
+	LED_OFF = 0,
+	LED_AMBER,
+	LED_WHITE,
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
+};
+
+static void side_led_set_color(int port, enum led_color color)
+{
+	gpio_set_level(port ? GPIO_EC_CHG_LED_Y_C1 : GPIO_EC_CHG_LED_Y_C0,
+		       (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
+	gpio_set_level(port ? GPIO_EC_CHG_LED_W_C1 : GPIO_EC_CHG_LED_W_C0,
+		       (color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF);
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	brightness_range[EC_LED_COLOR_AMBER] = 1;
+	brightness_range[EC_LED_COLOR_WHITE] = 1;
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	int port;
+
+	switch (led_id) {
+	case EC_LED_ID_LEFT_LED:
+		port = 0;
+		break;
+	case EC_LED_ID_RIGHT_LED:
+		port = 1;
+		break;
+	default:
+		return EC_ERROR_PARAM1;
+	}
+
+	if (brightness[EC_LED_COLOR_WHITE] != 0)
+		side_led_set_color(port, LED_WHITE);
+	else if (brightness[EC_LED_COLOR_AMBER] != 0)
+		side_led_set_color(port, LED_AMBER);
+	else
+		side_led_set_color(port, LED_OFF);
+
+	return EC_SUCCESS;
+}
+
+/*
+ * Set active charge port color to the parameter, turn off all others.
+ * If no port is active (-1), turn off all LEDs.
+ */
+static void set_active_port_color(enum led_color color)
+{
+	int port = charge_manager_get_active_charge_port();
+
+	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
+		side_led_set_color(0, (port == 0) ? color : LED_OFF);
+	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
+		side_led_set_color(1, (port == 1) ? color : LED_OFF);
+}
+
+static void board_led_set_battery(void)
+{
+	static int battery_ticks;
+	static int power_ticks;
+	int led_blink_cycle;
+
+	battery_ticks++;
+
+	/*
+	 * Override battery LED for kingoftown which doesn't have power LED,
+	 * blinking battery white LED to indicate system suspend without
+	 * charging.
+	 */
+	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
+	    led_pwr_get_state() != LED_PWRS_CHARGE) {
+		power_ticks++;
+		led_blink_cycle = power_ticks % (2 * TIMES_TICK_ONE_SEC);
+
+		side_led_set_color(0, (led_blink_cycle < TIMES_TICK_ONE_SEC) ?
+					      LED_WHITE :
+					      LED_OFF);
+		side_led_set_color(1, (led_blink_cycle < TIMES_TICK_ONE_SEC) ?
+					      LED_WHITE :
+					      LED_OFF);
+		return;
+	}
+
+	power_ticks = 0;
+
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
+		/* Always indicate when charging, even in suspend. */
+		set_active_port_color(LED_AMBER);
+		break;
+	case LED_PWRS_DISCHARGE:
+		if (charge_get_percent() <= 10) {
+			led_blink_cycle =
+				battery_ticks % (2 * TIMES_TICK_ONE_SEC);
+			if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
+				side_led_set_color(1, (led_blink_cycle <
+						       TIMES_TICK_ONE_SEC) ?
+							      LED_AMBER :
+							      LED_OFF);
+			if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
+				side_led_set_color(0, (led_blink_cycle <
+						       TIMES_TICK_ONE_SEC) ?
+							      LED_AMBER :
+							      LED_OFF);
+		} else {
+			if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
+				side_led_set_color(1, LED_OFF);
+			if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
+				side_led_set_color(0, LED_OFF);
+		}
+		break;
+	case LED_PWRS_ERROR:
+		led_blink_cycle = battery_ticks % TIMES_TICK_ONE_SEC;
+		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
+			side_led_set_color(1, (led_blink_cycle <
+					       TIMES_TICK_HALF_SEC) ?
+						      LED_AMBER :
+						      LED_OFF);
+		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
+			side_led_set_color(0, (led_blink_cycle <
+					       TIMES_TICK_HALF_SEC) ?
+						      LED_AMBER :
+						      LED_OFF);
+		break;
+	case LED_PWRS_CHARGE_NEAR_FULL:
+		set_active_port_color(LED_WHITE);
+		break;
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		set_active_port_color(LED_WHITE);
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		led_blink_cycle = battery_ticks % (2 * TIMES_TICK_ONE_SEC);
+		set_active_port_color((led_blink_cycle < TIMES_TICK_ONE_SEC) ?
+					      LED_AMBER :
+					      LED_OFF);
+		break;
+	default:
+		/* Other states don't alter LED behavior */
+		break;
+	}
+}
+
+/* Called by hook task every TICK */
+static void led_tick(void)
+{
+	board_led_set_battery();
+}
+DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
+
+void led_control(enum ec_led_id led_id, enum ec_led_state state)
+{
+	enum led_color color;
+
+	if ((led_id != EC_LED_ID_RECOVERY_HW_REINIT_LED) &&
+	    (led_id != EC_LED_ID_SYSRQ_DEBUG_LED))
+		return;
+
+	if (state == LED_STATE_RESET) {
+		led_auto_control(EC_LED_ID_LEFT_LED, 1);
+		led_auto_control(EC_LED_ID_RIGHT_LED, 1);
+		board_led_set_battery();
+		return;
+	}
+
+	color = state ? LED_WHITE : LED_OFF;
+
+	led_auto_control(EC_LED_ID_LEFT_LED, 0);
+	led_auto_control(EC_LED_ID_RIGHT_LED, 0);
+
+	side_led_set_color(0, color);
+	side_led_set_color(1, color);
+}
diff --git a/board/kingoftown/switchcap.c b/board/kingoftown/switchcap.c
new file mode 100644
index 0000000000..5173e27f75
--- /dev/null
+++ b/board/kingoftown/switchcap.c
@@ -0,0 +1,22 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "gpio.h"
+#include "power/qcom.h"
+
+void board_set_switchcap_power(int enable)
+{
+	gpio_set_level(GPIO_SWITCHCAP_ON, enable);
+}
+
+int board_is_switchcap_enabled(void)
+{
+	return gpio_get_level(GPIO_SWITCHCAP_ON);
+}
+
+int board_is_switchcap_power_good(void)
+{
+	return gpio_get_level(GPIO_SWITCHCAP_PG);
+}
diff --git a/board/kingoftown/usbc_config.c b/board/kingoftown/usbc_config.c
new file mode 100644
index 0000000000..b18b43ed37
--- /dev/null
+++ b/board/kingoftown/usbc_config.c
@@ -0,0 +1,365 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Kingoftown board-specific USB-C configuration */
+
+#include "bc12/pi3usb9201_public.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "charger/isl923x_public.h"
+#include "common.h"
+#include "config.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "ppc/sn5s330_public.h"
+#include "system.h"
+#include "tcpm/ps8xxx_public.h"
+#include "tcpm/tcpci.h"
+#include "timer.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usbc_config.h"
+#include "usbc_ocp.h"
+#include "usbc_ppc.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+};
+
+int charger_profile_override(struct charge_state_data *curr)
+{
+	int usb_mv;
+	int port;
+
+	if (curr->state != ST_CHARGE)
+		return 0;
+
+	/* Lower the max requested voltage to 5V when battery is full. */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
+	    !(curr->batt.flags & BATT_FLAG_BAD_STATUS) &&
+	    !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
+	    (curr->batt.status & STATUS_FULLY_CHARGED))
+		usb_mv = 5000;
+	else
+		usb_mv = PD_MAX_VOLTAGE_MV;
+
+	if (pd_get_max_voltage() != usb_mv) {
+		CPRINTS("VBUS limited to %dmV", usb_mv);
+		for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++)
+			pd_set_external_voltage_limit(port, usb_mv);
+	}
+
+	return 0;
+}
+
+enum ec_status charger_profile_override_get_param(uint32_t param,
+						  uint32_t *value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+enum ec_status charger_profile_override_set_param(uint32_t param,
+						  uint32_t value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+/* GPIO Interrupt Handlers */
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	int port = -1;
+
+	switch (signal) {
+	case GPIO_USB_C0_PD_INT_ODL:
+		port = 0;
+		break;
+	case GPIO_USB_C1_PD_INT_ODL:
+		port = 1;
+		break;
+	default:
+		return;
+	}
+
+	schedule_deferred_pd_interrupt(port);
+}
+
+void usb0_evt(enum gpio_signal signal)
+{
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+
+void usb1_evt(enum gpio_signal signal)
+{
+	usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+}
+
+static void usba_oc_deferred(void)
+{
+	/* Use next number after all USB-C ports to indicate the USB-A port */
+	board_overcurrent_event(CONFIG_USB_PD_PORT_MAX_COUNT,
+				!gpio_get_level(GPIO_USB_A0_OC_ODL));
+}
+DECLARE_DEFERRED(usba_oc_deferred);
+
+void usba_oc_interrupt(enum gpio_signal signal)
+{
+	hook_call_deferred(&usba_oc_deferred_data, 0);
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_SWCTL_INT_ODL:
+		sn5s330_interrupt(0);
+		break;
+	case GPIO_USB_C1_SWCTL_INT_ODL:
+		sn5s330_interrupt(1);
+		break;
+	default:
+		break;
+	}
+}
+
+/* Power Path Controller */
+struct ppc_config_t ppc_chips[] = {
+	{ .i2c_port = I2C_PORT_TCPC0,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
+	{ .i2c_port = I2C_PORT_TCPC1,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
+};
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/* TCPC mux configuration */
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TCPC0,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+	},
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TCPC1,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+	},
+};
+
+/*
+ * Port-0/1 USB mux driver.
+ *
+ * The USB mux is handled by TCPC chip and the HPD update is through a GPIO
+ * to AP. But the TCPC chip is also needed to know the HPD status; otherwise,
+ * the mux misbehaves.
+ */
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
+	},
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
+	}
+};
+
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_USB_A_5V,
+};
+
+/* BC1.2 */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	{
+		.i2c_port = I2C_PORT_POWER,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+	{
+		.i2c_port = I2C_PORT_EEPROM,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+};
+
+/* Initialize board USC-C things */
+static void board_init_usbc(void)
+{
+	/* Enable BC1.2 interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_L);
+	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L);
+
+	/* Enable USB-A overcurrent interrupt */
+	gpio_enable_interrupt(GPIO_USB_A0_OC_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_init_usbc, HOOK_PRIO_DEFAULT);
+
+void board_tcpc_init(void)
+{
+	/* Only reset TCPC if not sysjump */
+	if (!system_jumped_late()) {
+		/* TODO(crosbug.com/p/61098): How long do we need to wait? */
+		board_reset_pd_mcu();
+	}
+
+	/* Enable PPC interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_SWCTL_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_SWCTL_INT_ODL);
+
+	/* Enable TCPC interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL);
+
+	/*
+	 * Initialize HPD to low; after sysjump SOC needs to see
+	 * HPD pulse to enable video path
+	 */
+	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
+		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
+
+void board_reset_pd_mcu(void)
+{
+	cprints(CC_USB, "Resetting TCPCs...");
+	cflush();
+
+	gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
+	gpio_set_level(GPIO_USB_C1_PD_RST_L, 0);
+	msleep(PS8XXX_RESET_DELAY_MS);
+	gpio_set_level(GPIO_USB_C0_PD_RST_L, 1);
+	gpio_set_level(GPIO_USB_C1_PD_RST_L, 1);
+	msleep(PS8805_FW_INIT_DELAY_MS);
+}
+
+void board_set_tcpc_power_mode(int port, int mode)
+{
+	/* Ignore the "mode" to turn the chip on.  We can only do a reset. */
+	if (mode)
+		return;
+
+	board_reset_pd_mcu();
+}
+
+int board_vbus_sink_enable(int port, int enable)
+{
+	/* Both ports are controlled by PPC SN5S330 */
+	return ppc_vbus_sink_enable(port, enable);
+}
+
+int board_is_sourcing_vbus(int port)
+{
+	/* Both ports are controlled by PPC SN5S330 */
+	return ppc_is_sourcing_vbus(port);
+}
+
+void board_overcurrent_event(int port, int is_overcurrented)
+{
+	/* TODO(b/120231371): Notify AP */
+	CPRINTS("p%d: overcurrent!", port);
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int i;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTS("Disabling all charging port");
+
+		/* Disable all ports. */
+		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (board_vbus_sink_enable(i, 0))
+				CPRINTS("Disabling p%d sink path failed.", i);
+		}
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (board_is_sourcing_vbus(port)) {
+		CPRINTS("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTS("New charge port: p%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		if (i == port)
+			continue;
+
+		if (board_vbus_sink_enable(i, 0))
+			CPRINTS("p%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (board_vbus_sink_enable(port, 1)) {
+		CPRINTS("p%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
+{
+	/*
+	 * Ignore lower charge ceiling on PD transition if our battery is
+	 * critical, as we may brownout.
+	 */
+	if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 &&
+	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
+		CPRINTS("Using max ilim %d", max_ma);
+		charge_ma = max_ma;
+	}
+
+	charge_set_input_current_limit(charge_ma, charge_mv);
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
+		if (gpio_get_level(GPIO_USB_C0_PD_RST_L))
+			status |= PD_STATUS_TCPC_ALERT_0;
+	if (!gpio_get_level(GPIO_USB_C1_PD_INT_ODL))
+		if (gpio_get_level(GPIO_USB_C1_PD_RST_L))
+			status |= PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
diff --git a/board/kingoftown/usbc_config.h b/board/kingoftown/usbc_config.h
new file mode 100644
index 0000000000..7718aea74c
--- /dev/null
+++ b/board/kingoftown/usbc_config.h
@@ -0,0 +1,19 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Kingoftown board-specific USB-C configuration */
+
+#ifndef __CROS_EC_USBC_CONFIG_H
+#define __CROS_EC_USBC_CONFIG_H
+
+#include "gpio.h"
+
+void tcpc_alert_event(enum gpio_signal signal);
+void usb0_evt(enum gpio_signal signal);
+void usb1_evt(enum gpio_signal signal);
+void usba_oc_interrupt(enum gpio_signal signal);
+void ppc_interrupt(enum gpio_signal signal);
+
+#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/kingoftown/vif_override.xml b/board/kingoftown/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/kingoftown/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/kinox/board.c b/board/kinox/board.c
new file mode 100644
index 0000000000..af36a3bbc7
--- /dev/null
+++ b/board/kinox/board.c
@@ -0,0 +1,138 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "builtin/assert.h"
+#include "button.h"
+#include "cec.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "driver/cec/bitbang.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "power.h"
+#include "power_button.h"
+#include "switch.h"
+#include "throttle_ap.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* Console output macros */
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+
+/******************************************************************************/
+/* USB-A charging control */
+
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_PP5000_USBA,
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
+
+/******************************************************************************/
+
+/* CEC ports */
+const struct cec_config_t cec_config[] = {
+	[CEC_PORT_0] = {
+		.drv = &bitbang_cec_drv,
+		.offline_policy = NULL,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(cec_config) == CEC_PORT_COUNT);
+
+int board_set_active_charge_port(int port)
+{
+	CPRINTS("Requested charge port change to %d", port);
+
+	/*
+	 * The charge manager may ask us to switch to no charger if we're
+	 * running off USB-C only but upstream doesn't support PD. It requires
+	 * that we accept this switch otherwise it triggers an assert and EC
+	 * reset; it's not possible to boot the AP anyway, but we want to avoid
+	 * resetting the EC so we can continue to do the "low power" LED blink.
+	 */
+	if (port == CHARGE_PORT_NONE)
+		return EC_SUCCESS;
+
+	if (port < 0 || CHARGE_PORT_COUNT <= port)
+		return EC_ERROR_INVAL;
+
+	if (port == charge_manager_get_active_charge_port())
+		return EC_SUCCESS;
+
+	/* Don't charge from a source port */
+	if (board_vbus_source_enabled(port))
+		return EC_ERROR_INVAL;
+
+	if (!chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
+		int bj_active, bj_requested;
+
+		if (charge_manager_get_active_charge_port() != CHARGE_PORT_NONE)
+			/* Change is only permitted while the system is off */
+			return EC_ERROR_INVAL;
+
+		/*
+		 * Current setting is no charge port but the AP is on, so the
+		 * charge manager is out of sync (probably because we're
+		 * reinitializing after sysjump). Reject requests that aren't
+		 * in sync with our outputs.
+		 */
+		bj_active = !gpio_get_level(GPIO_EN_PPVAR_BJ_ADP_L);
+		bj_requested = port == CHARGE_PORT_BARRELJACK;
+		if (bj_active != bj_requested)
+			return EC_ERROR_INVAL;
+	}
+
+	CPRINTS("New charger p%d", port);
+
+	switch (port) {
+	case CHARGE_PORT_TYPEC0:
+		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 1);
+		break;
+	case CHARGE_PORT_BARRELJACK:
+		/* Make sure BJ adapter is sourcing power */
+		if (gpio_get_level(GPIO_BJ_ADP_PRESENT_ODL))
+			return EC_ERROR_INVAL;
+		ppc_vbus_sink_enable(0, 0);
+		break;
+	default:
+		return EC_ERROR_INVAL;
+	}
+
+	return EC_SUCCESS;
+}
+
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
+{
+}
+
+static void adp_state_init(void)
+{
+	ASSERT(CHARGE_PORT_ENUM_COUNT == CHARGE_PORT_COUNT);
+	/*
+	 * Initialize all charge suppliers to 0. The charge manager waits until
+	 * all ports have reported in before doing anything.
+	 */
+	for (int i = 0; i < CHARGE_PORT_COUNT; i++) {
+		for (int j = 0; j < CHARGE_SUPPLIER_COUNT; j++)
+			charge_manager_update_charge(j, i, NULL);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, adp_state_init, HOOK_PRIO_INIT_CHARGE_MANAGER + 1);
+
+static void board_init(void)
+{
+	gpio_enable_interrupt(GPIO_BJ_ADP_PRESENT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/kinox/board.h b/board/kinox/board.h
new file mode 100644
index 0000000000..a1179167a8
--- /dev/null
+++ b/board/kinox/board.h
@@ -0,0 +1,178 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Kinox board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "compile_time_macros.h"
+
+/* Baseboard features */
+#include "baseboard.h"
+
+/* Barrel Jack */
+#define DEDICATED_CHARGE_PORT 1
+
+/* HDMI CEC */
+#define CONFIG_CEC
+#define CONFIG_CEC_BITBANG
+#define CEC_GPIO_OUT GPIO_HDMI_CEC_OUT
+#define CEC_GPIO_IN GPIO_HDMI_CEC_IN
+#define CEC_GPIO_PULL_UP GPIO_HDMI_CEC_PULL_UP
+
+/* USB Type A Features */
+#define USB_PORT_COUNT 4
+#define CONFIG_USB_PORT_POWER_DUMB
+
+/* USB Type C and USB PD defines */
+#define CONFIG_USB_PD_PPC
+#define CONFIG_USB_PD_TCPM_PS8815
+#define CONFIG_USB_PD_TCPM_PS8815_FORCE_DID
+#undef CONFIG_USB_PD_TCPM_NCT38XX
+
+#define CONFIG_USBC_PPC_SYV682X
+#undef CONFIG_SYV682X_HV_ILIM
+#define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_5_50
+
+/* TODO: b/177608416 - measure and check these values on brya */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
+
+/* The design should support up to 100W. */
+/* TODO(b/197702356): Set the max PD to 60W now and change it
+ * to 100W after we verify it.
+ */
+#define PD_OPERATING_POWER_MW CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
+#define PD_MAX_POWER_MW 100000
+#define PD_MAX_CURRENT_MA 5000
+#define PD_MAX_VOLTAGE_MV 20000
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
+
+/*
+ * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
+ * signal.
+ */
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
+#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_OD
+#define GPIO_RECOVERY_L_2 GPIO_GSC_EC_RECOVERY_BTN_OD
+
+/* I2C Bus Configuration */
+#define I2C_PORT_USB_C0_PPC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C0_TCPC NPCX_I2C_PORT4_1
+#define I2C_PORT_USB_C0_BC12 NPCX_I2C_PORT6_1
+
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+
+/* I2C control host command */
+#define CONFIG_HOSTCMD_I2C_CONTROL
+
+/* Thermal features */
+#define CONFIG_THERMISTOR
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_TEMP_SENSOR_POWER
+#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
+
+/* ADC */
+#define CONFIG_ADC
+
+/*
+ * TODO(b/197478860): Enable the fan control. We need
+ * to check the sensor value and adjust the fan speed.
+ */
+#define CONFIG_FANS FAN_CH_COUNT
+
+/* Include math_util for bitmask_uint64 used in pd_timers */
+#define CONFIG_MATH_UTIL
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h" /* needed by registers.h */
+#include "registers.h"
+#include "usbc_config.h"
+
+enum adp_id { UNKNOWN, TINY, TIO1, TIO2, TYPEC };
+
+struct adpater_id_params {
+	int min_voltage;
+	int max_voltage;
+	int charge_voltage;
+	int charge_current;
+	int watt;
+	int obp95;
+	int obp85;
+};
+
+enum charge_port {
+	CHARGE_PORT_TYPEC0,
+	CHARGE_PORT_BARRELJACK,
+	CHARGE_PORT_ENUM_COUNT
+};
+
+enum adc_channel {
+	ADC_TEMP_SENSOR_1_CPU,
+	ADC_TEMP_SENSOR_2_CPU_VR,
+	ADC_TEMP_SENSOR_3_WIFI,
+	ADC_TEMP_SENSOR_4_DIMM,
+	ADC_PWR_IN_IMON,
+	ADC_VBUS,
+	ADC_ADP_ID,
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1_CPU,
+	TEMP_SENSOR_2_CPU_VR,
+	TEMP_SENSOR_3_WIFI,
+	TEMP_SENSOR_4_DIMM,
+	TEMP_SENSOR_COUNT
+};
+
+enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_PORT_COUNT };
+
+enum pwm_channel {
+	PWM_CH_LED_GREEN, /* PWM0 */
+	PWM_CH_FAN, /* PWM5 */
+	PWM_CH_LED_RED, /* PWM2 */
+	PWM_CH_COUNT
+};
+
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT };
+
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT };
+
+enum cec_port { CEC_PORT_0, CEC_PORT_COUNT };
+
+extern void adp_connect_interrupt(enum gpio_signal signal);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/kinox/build.mk b/board/kinox/build.mk
new file mode 100644
index 0000000000..3eb2d2b2d5
--- /dev/null
+++ b/board/kinox/build.mk
@@ -0,0 +1,23 @@
+# -*- makefile -*-
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Brask board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx9
+CHIP_VARIANT:=npcx9m3f
+BASEBOARD:=brask
+
+board-y=
+board-y+=board.o
+board-y+=power_detection.o
+board-y+=fans.o
+board-y+=fw_config.o
+board-y+=i2c.o
+board-y+=led.o
+board-y+=pwm.o
+board-y+=sensors.o
+board-y+=usbc_config.o
diff --git a/board/kinox/ec.tasklist b/board/kinox/ec.tasklist
new file mode 100644
index 0000000000..6524d9c2b0
--- /dev/null
+++ b/board/kinox/ec.tasklist
@@ -0,0 +1,23 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ *
+ * USB_CHG_Px tasks must be contiguous (see USB_CHG_PORT_TO_TASK_ID(x)).
+ * PD_Cx tasks must be contiguous (see PD_PORT_TO_TASK_ID(x))
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_shared_alert_task, BIT(0), LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CEC, cec_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/kinox/fans.c b/board/kinox/fans.c
new file mode 100644
index 0000000000..e5724e345a
--- /dev/null
+++ b/board/kinox/fans.c
@@ -0,0 +1,50 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Physical fans. These are logically separate from pwm_channels. */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "fan.h"
+#include "fan_chip.h"
+#include "hooks.h"
+#include "pwm.h"
+
+/* MFT channels. These are logically separate from pwm_channels. */
+const struct mft_t mft_channels[] = {
+	[MFT_CH_0] = {
+		.module = NPCX_MFT_MODULE_2,
+		.clk_src = TCKC_LFCLK,
+		.pwm_id = PWM_CH_FAN,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
+
+static const struct fan_conf fan_conf_0 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
+	.pgood_gpio = -1,
+	.enable_gpio = GPIO_EN_PP12000_FAN,
+};
+
+/*
+ * TOOD(b/197478860): need to update for real fan
+ *
+ * Prototype fan spins at about 7200 RPM at 100% PWM.
+ * Set minimum at around 30% PWM.
+ */
+static const struct fan_rpm fan_rpm_0 = {
+	.rpm_min = 1000,
+	.rpm_start = 1000,
+	.rpm_max = 4200,
+};
+
+const struct fan_t fans[FAN_CH_COUNT] = {
+	[FAN_CH_0] = {
+		.conf = &fan_conf_0,
+		.rpm = &fan_rpm_0,
+	},
+};
diff --git a/board/kinox/fw_config.c b/board/kinox/fw_config.c
new file mode 100644
index 0000000000..9736de1110
--- /dev/null
+++ b/board/kinox/fw_config.c
@@ -0,0 +1,35 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "fw_config.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+static union kinox_cbi_fw_config fw_config;
+BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
+
+/*
+ * FW_CONFIG defaults for kinox if the CBI.FW_CONFIG data is not
+ * initialized.
+ */
+static const union kinox_cbi_fw_config fw_config_defaults = {
+	.dp_display = ABSENT,
+};
+
+/****************************************************************************
+ * Kinox FW_CONFIG access
+ */
+void board_init_fw_config(void)
+{
+	if (cbi_get_fw_config(&fw_config.raw_value)) {
+		CPRINTS("CBI: Read FW_CONFIG failed, using board defaults");
+		fw_config = fw_config_defaults;
+	}
+}
diff --git a/board/kinox/fw_config.h b/board/kinox/fw_config.h
new file mode 100644
index 0000000000..a3efa7bfe9
--- /dev/null
+++ b/board/kinox/fw_config.h
@@ -0,0 +1,34 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __BOARD_KINOX_FW_CONFIG_H_
+#define __BOARD_KINOX_FW_CONFIG_H_
+
+#include <stdint.h>
+
+/****************************************************************************
+ * CBI FW_CONFIG layout for kinox board.
+ *
+ * Source of truth is the project/brask/kinox/config.star configuration file.
+ */
+
+enum ec_cfg_dp_display { ABSENT = 0, DB_HDMI = 1, DB_DP = 2 };
+
+union kinox_cbi_fw_config {
+	struct {
+		uint32_t dp_display : 4;
+		uint32_t reserved_1 : 28;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Read the cached FW_CONFIG.  Guaranteed to have valid values.
+ *
+ * @return the FW_CONFIG for the board.
+ */
+union kinox_cbi_fw_config get_fw_config(void);
+
+#endif /* __BOARD_KINOX_FW_CONFIG_H_ */
diff --git a/board/kinox/gpio.inc b/board/kinox/gpio.inc
new file mode 100644
index 0000000000..f3d94ebf07
--- /dev/null
+++ b/board/kinox/gpio.inc
@@ -0,0 +1,163 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* INTERRUPT GPIOs: */
+GPIO_INT(ACOK_OD,                    PIN(0, 0), GPIO_INT_BOTH, extpower_interrupt)
+GPIO_INT(EC_PROCHOT_IN_L,            PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
+GPIO_INT(EC_WP_ODL,                  PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(GSC_EC_PWR_BTN_ODL,         PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
+GPIO_INT(SEQ_EC_ALL_SYS_PG,          PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_DSW_PWROK,           PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_RSMRST_ODL,          PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,                   PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,                  PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SYS_SLP_S0IX_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(USB_C0_BC12_INT_ODL,        PIN(C, 6), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C0_PPC_INT_ODL,         PIN(F, 5), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C0_TCPC_INT_ODL,        PIN(A, 2), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(BJ_ADP_PRESENT_ODL,         PIN(8, 2), GPIO_INT_BOTH | GPIO_PULL_UP, adp_connect_interrupt)
+GPIO_INT(EC_RECOVERY_BTN_OD,         PIN(2, 3), GPIO_INT_BOTH, button_interrupt)
+
+/* CCD */
+GPIO(CCD_MODE_ODL,                   PIN(E, 5), GPIO_INPUT)
+
+/* Security */
+GPIO(EC_ENTERING_RW,                 PIN(0, 3), GPIO_OUT_LOW)
+GPIO(EC_GSC_PACKET_MODE,             PIN(7, 5), GPIO_OUT_LOW)
+
+/* Fan */
+GPIO(EN_PP12000_FAN,                 PIN(6, 1), GPIO_OUT_LOW)
+
+/* Display */
+GPIO(DP_CONN_OC_ODL,                 PIN(2, 5), GPIO_INPUT)
+GPIO(HDMI_CONN_OC_ODL,               PIN(2, 4), GPIO_INPUT)
+
+/* BarrelJack */
+GPIO(EN_PPVAR_BJ_ADP_L,              PIN(0, 7), GPIO_OUT_LOW)
+
+/* Chipset PCH */
+GPIO(EC_PCHHOT_ODL,                  PIN(7, 4), GPIO_INPUT)
+GPIO(EC_PCH_INT_ODL,                 PIN(B, 0), GPIO_ODR_HIGH)
+GPIO(EC_PCH_RSMRST_L,                PIN(A, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_RTCRST,                  PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_SYS_PWROK,               PIN(3, 7), GPIO_OUT_LOW)
+GPIO(EC_PCH_WAKE_ODL,                PIN(C, 0), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_ODL,                 PIN(6, 3), GPIO_ODR_HIGH)
+GPIO(EN_S5_RAILS,                    PIN(B, 6), GPIO_OUT_LOW)
+GPIO(PCH_PWROK,                      PIN(7, 2), GPIO_OUT_LOW)
+GPIO(SYS_RST_ODL,                    PIN(C, 5), GPIO_ODR_HIGH)
+GPIO(VCCST_PWRGD_OD,                 PIN(A, 4), GPIO_ODR_LOW)
+GPIO(IMVP9_VRRDY_OD,                 PIN(6, 0), GPIO_INPUT)
+GPIO(CPU_C10_GATE_L,                 PIN(6, 7), GPIO_INPUT)
+
+/* Button */
+GPIO(EC_PCH_PWR_BTN_ODL,             PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(GSC_EC_RECOVERY_BTN_OD,         PIN(2, 2), GPIO_INPUT)
+
+GPIO(SIO_LEGO_EN_L,                  PIN(9, 6), GPIO_OUT_LOW)
+
+/* HDMI CEC */
+/* TODO(b/197474873): Enable HDMI CEC */
+GPIO(HDMI_CEC_IN,                    PIN(4, 0), GPIO_INPUT)
+GPIO(HDMI_CEC_OUT,                   PIN(D, 3), GPIO_OUT_HIGH | GPIO_OPEN_DRAIN)
+GPIO(HDMI_CEC_PULL_UP,               PIN(C, 2), GPIO_OUT_HIGH)
+
+/* I2C SCL/SDA */
+GPIO(EC_I2C_MISC_SCL_R,              PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SDA_R,              PIN(B, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_PPC_SCL,       PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_PPC_SDA,       PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_MIX_SCL,          PIN(E, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_MIX_SDA,          PIN(E, 3), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_TCPC_SCL,         PIN(F, 3), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_TCPC_SDA,         PIN(F, 2), GPIO_INPUT)
+
+/* USBA */
+GPIO(EN_PP5000_USBA,                 PIN(D, 7), GPIO_OUT_LOW)
+GPIO(USB_A0_OC_ODL,                  PIN(3, 1), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(USB_A1_OC_ODL,                  PIN(3, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(USB_A2_OC_ODL,                  PIN(2, 7), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(USB_HUB_A1_OC_ODL,              PIN(2, 6), GPIO_INPUT)
+GPIO(USB_HUB_A2_OC_ODL,              PIN(2, 1), GPIO_INPUT)
+GPIO(USB_HUB_A3_OC_ODL,              PIN(2, 0), GPIO_INPUT)
+GPIO(BTB1_USB_DET_L,                 PIN(1, 5), GPIO_INPUT)
+GPIO(BTB1_DP_DET_L,                  PIN(1, 4), GPIO_INPUT)
+GPIO(BTB1_COM_DET_L,                 PIN(1, 1), GPIO_INPUT)
+GPIO(USB_A_OC_SOC_L,                 PIN(8, 0), GPIO_OUT_HIGH)
+
+/* LED */
+/* TODO(b/197471359): LED implementation */
+GPIO(LED_PWR_L,                      PIN(C, 3), GPIO_OUT_LOW)
+GPIO(LED_HDD_L,                      PIN(C, 4), GPIO_OUT_LOW)
+
+/* USBC */
+GPIO(USB_C0_FRS_EN,                  PIN(9, 4), GPIO_OUT_LOW)
+GPIO(USB_C0_RT_RST_R_ODL,            PIN(0, 2), GPIO_OUT_LOW)
+
+/* UART alternate functions */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)              /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */
+
+/* I2C alternate functions */
+ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)               /* GPIO33/I2C5_SCL0/CTS_L, GPIO36/RTS_L/I2C5_SDA0 */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)               /* GPIO87/I2C1_SDA0 */
+ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)               /* GPIO92/I2C2_SCL0, GPIO91/I2C2_SDA0, GPIO90/I2C1_SCL0 */
+ALTERNATE(PIN_MASK(B, 0x0c), 0, MODULE_I2C, 0)               /* GPIOB3/I2C7_SCL0/DCD_L, GPIOB2/I2C7_SDA0/DSR_L */
+ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, 0)               /* GPIOB5/I2C0_SCL0, GPIOB4/I2C0_SDA0 */
+ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)               /* GPIOD1/I2C3_SCL0, GPIOD0/I2C3_SDA0 */
+ALTERNATE(PIN_MASK(E, 0x18), 0, MODULE_I2C, 0)               /* GPIOE4/I2C6_SCL1/I3C_SCL, GPIOE3/I2C6_SDA1/I3C_SDA */
+ALTERNATE(PIN_MASK(F, 0x0c), 0, MODULE_I2C, 0)               /* GPIOF3/I2C4_SCL1, GPIOF2/I2C4_SDA1 */
+
+/* PWM alternate functions */
+ALTERNATE(PIN_MASK(7, 0x08), 0, MODULE_PWM, 0)               /* GPIO73/TA2 */
+ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)               /* GPIOB7/PWM5 */
+ALTERNATE(PIN_MASK(C, 0x18), 0, MODULE_PWM, 0)               /* GPIOC4/PWM2, GPIOC3/PWM0 */
+
+/* ADC alternate functions */
+ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0)               /* GPIO34/PS2_DAT2/ADC6 */
+ALTERNATE(PIN_MASK(4, 0x38), 0, MODULE_ADC, 0)               /* GPIO45/ADC0, GPIO44/ADC1, GPIO43/ADC2 */
+ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0)               /* GPIOE1/ADC7 */
+ALTERNATE(PIN_MASK(4, 0x02), 0, MODULE_ADC, 0)               /* GPIO41/ADC4 */
+ALTERNATE(PIN_MASK(4, 0x04), 0, MODULE_ADC, 0)               /* GPIO42/ADC3 */
+
+/* Unused Pins */
+UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
+UNUSED(PIN(3, 2))       /* GPO32/TRIS_L */
+UNUSED(PIN(3, 5))       /* GPO35/CR_SOUT4/TEST_L */
+UNUSED(PIN(6, 6))       /* GPIO66 */
+UNUSED(PIN(8, 1))       /* GPIO81/PECI_DATA */
+UNUSED(PIN(5, 6))       /* GPIO56/CLKRUN# */
+UNUSED(PIN(9, 7))       /* GPIO97 */
+UNUSED(PIN(8, 6))       /* GPIO86/TXD/CR_SOUT2 */
+UNUSED(PIN(1, 3))       /* KSO06/GPO13/GP_SEL# */
+UNUSED(PIN(1, 2))       /* KSO07/GPO12/JEN# */
+UNUSED(PIN(0, 6))       /* KSO11/GPIO06/P80_CLK */
+UNUSED(PIN(0, 4))       /* KSO13/GPIO04 */
+UNUSED(PIN(0, 5))       /* KSO12/GPIO05 */
+UNUSED(PIN(1, 0))       /* KSO09/GPIO10 */
+UNUSED(PIN(1, 6))       /* KSO03/GPIO16 */
+UNUSED(PIN(1, 7))       /* KSO02/GPIO17 */
+UNUSED(PIN(3, 3))       /* GPIO33 */
+UNUSED(PIN(3, 6))       /* GPIO36 */
+UNUSED(PIN(E, 0))       /* GPIOE0/ADC10 */
+UNUSED(PIN(5, 0))       /* GPIO50 */
+UNUSED(PIN(6, 2))       /* GPIO62/PS2_CLK1 */
+UNUSED(PIN(7, 0))       /* GPIO70/PS2_DAT0 */
+UNUSED(PIN(8, 3))       /* KSO15/GPIO83 */
+UNUSED(PIN(8, 7))       /* GPIO87/I2C1_SDA0 */
+UNUSED(PIN(9, 0))       /* GPIO90/I2C1_SCL0 */
+UNUSED(PIN(9, 3))       /* GPIO93 */
+UNUSED(PIN(9, 5))       /* GPIO95/SPIP_MISO */
+UNUSED(PIN(A, 0))       /* F_CS0#/GPIOA0 */
+UNUSED(PIN(A, 3))       /* GPIOA3/SPIP_MOSI */
+UNUSED(PIN(A, 7))       /* GPIOA7/PS2_DAT3 */
+UNUSED(PIN(B, 1))       /* KSO17/GPIOB1 */
+UNUSED(PIN(B, 4))       /* GPIOB4/I2C0_SDA0 */
+UNUSED(PIN(B, 5))       /* GPIOB5/I2C0_SCL0 */
+UNUSED(PIN(D, 0))       /* GPIOD0/I2C3_SDA0 */
+UNUSED(PIN(D, 1))       /* GPIOD1/I2C3_SCL0 */
+UNUSED(PIN(D, 2))       /* PSL_IN1#/GPIOD2 */
+UNUSED(PIN(D, 4))       /* GPIOD4/CR_SIN3 */
\ No newline at end of file
diff --git a/board/kinox/i2c.c b/board/kinox/i2c.c
new file mode 100644
index 0000000000..0412640a19
--- /dev/null
+++ b/board/kinox/i2c.c
@@ -0,0 +1,46 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "i2c.h"
+
+/* I2C port map configuration */
+const struct i2c_port_t i2c_ports[] = {
+	{
+		/* I2C2 C0 PPC*/
+		.name = "ppc C0",
+		.port = I2C_PORT_USB_C0_PPC,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_USB_C0_C2_PPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C2_PPC_SDA,
+	},
+	{
+		/* I2C4 C0 TCPC */
+		.name = "tcpc C0",
+		.port = I2C_PORT_USB_C0_TCPC,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_USB_C0_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_TCPC_SDA,
+		.flags = I2C_PORT_FLAG_DYNAMIC_SPEED,
+	},
+	{
+		/* I2C6 C0 BC1.2 */
+		.name = "bc12 C0",
+		.port = I2C_PORT_USB_C0_BC12,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_MIX_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_MIX_SDA,
+	},
+	{
+		/* I2C7 */
+		.name = "eeprom",
+		.port = I2C_PORT_EEPROM,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_MISC_SCL_R,
+		.sda = GPIO_EC_I2C_MISC_SDA_R,
+	},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/board/kinox/led.c b/board/kinox/led.c
new file mode 100644
index 0000000000..d2a9a599cf
--- /dev/null
+++ b/board/kinox/led.c
@@ -0,0 +1,262 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power LED control for Brask.
+ * Solid green - active power
+ * Green flashing - suspended
+ * Red flashing - alert
+ * Solid red - critical
+ */
+
+#include "chipset.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "led_common.h"
+#include "pwm.h"
+#include "timer.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
+
+/*
+ * Due to the CSME-Lite processing, upon startup the CPU transitions through
+ * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so
+ * delay turning off the LED during suspend/shutdown.
+ */
+#define LED_CPU_DELAY_MS (2000 * MSEC)
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED };
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+enum led_color {
+	LED_OFF = 0,
+	LED_RED,
+	LED_GREEN,
+
+	/* Number of colors, not a color itself */
+	LED_COLOR_COUNT
+};
+
+static int set_color_power(enum led_color color, int duty)
+{
+	int green = 0;
+	int red = 0;
+
+	if (duty < 0 || 100 < duty)
+		return EC_ERROR_UNKNOWN;
+
+	switch (color) {
+	case LED_OFF:
+		break;
+	case LED_GREEN:
+		green = 1;
+		break;
+	case LED_RED:
+		red = 1;
+		break;
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+
+	if (red)
+		pwm_set_duty(PWM_CH_LED_RED, duty);
+	else
+		pwm_set_duty(PWM_CH_LED_RED, 0);
+
+	if (green)
+		pwm_set_duty(PWM_CH_LED_GREEN, duty);
+	else
+		pwm_set_duty(PWM_CH_LED_GREEN, 0);
+
+	return EC_SUCCESS;
+}
+
+static int set_color(enum ec_led_id id, enum led_color color, int duty)
+{
+	switch (id) {
+	case EC_LED_ID_POWER_LED:
+		return set_color_power(color, duty);
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+}
+
+#define LED_PULSE_US (2 * SECOND)
+/* 40 msec for nice and smooth transition. */
+#define LED_PULSE_TICK_US (40 * MSEC)
+
+/*
+ * When pulsing is enabled, brightness is incremented by <duty_inc> every
+ * <interval> usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented
+ * likewise in LED_PULSE_US usec.
+ */
+static struct {
+	uint32_t interval;
+	int duty_inc;
+	enum led_color color;
+	int duty;
+} led_pulse;
+
+#define CONFIG_TICK(interval, color) \
+	config_tick((interval), 100 / (LED_PULSE_US / (interval)), (color))
+
+static void config_tick(uint32_t interval, int duty_inc, enum led_color color)
+{
+	led_pulse.interval = interval;
+	led_pulse.duty_inc = duty_inc;
+	led_pulse.color = color;
+	led_pulse.duty = 0;
+}
+
+static void pulse_power_led(enum led_color color)
+{
+	set_color(EC_LED_ID_POWER_LED, color, led_pulse.duty);
+	if (led_pulse.duty + led_pulse.duty_inc > 100)
+		led_pulse.duty_inc = led_pulse.duty_inc * -1;
+	else if (led_pulse.duty + led_pulse.duty_inc < 0)
+		led_pulse.duty_inc = led_pulse.duty_inc * -1;
+	led_pulse.duty += led_pulse.duty_inc;
+}
+
+static void led_tick(void);
+DECLARE_DEFERRED(led_tick);
+static void led_tick(void)
+{
+	uint32_t elapsed;
+	uint32_t next = 0;
+	uint32_t start = get_time().le.lo;
+
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		pulse_power_led(led_pulse.color);
+	elapsed = get_time().le.lo - start;
+	next = led_pulse.interval > elapsed ? led_pulse.interval - elapsed : 0;
+	hook_call_deferred(&led_tick_data, next);
+}
+
+static void led_suspend(void)
+{
+	CONFIG_TICK(LED_PULSE_TICK_US, LED_GREEN);
+	led_tick();
+}
+DECLARE_DEFERRED(led_suspend);
+
+static void led_shutdown(void)
+{
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_OFF, 0);
+}
+DECLARE_DEFERRED(led_shutdown);
+
+static void led_shutdown_hook(void)
+{
+	hook_call_deferred(&led_tick_data, -1);
+	hook_call_deferred(&led_suspend_data, -1);
+	hook_call_deferred(&led_shutdown_data, LED_CPU_DELAY_MS);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, led_shutdown_hook, HOOK_PRIO_DEFAULT);
+
+static void led_suspend_hook(void)
+{
+	hook_call_deferred(&led_shutdown_data, -1);
+	hook_call_deferred(&led_suspend_data, LED_CPU_DELAY_MS);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, led_suspend_hook, HOOK_PRIO_DEFAULT);
+
+static void led_resume(void)
+{
+	/*
+	 * Assume there is no race condition with led_tick, which also
+	 * runs in hook_task.
+	 */
+	hook_call_deferred(&led_tick_data, -1);
+	/*
+	 * Avoid invoking the suspend/shutdown delayed hooks.
+	 */
+	hook_call_deferred(&led_suspend_data, -1);
+	hook_call_deferred(&led_shutdown_data, -1);
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_GREEN, 100);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, led_resume, HOOK_PRIO_DEFAULT);
+
+void board_led_auto_control(void)
+{
+	/* Restore the previous signal */
+	if (chipset_in_state(CHIPSET_STATE_ON))
+		led_resume();
+	else if (chipset_in_state(CHIPSET_STATE_SUSPEND))
+		led_suspend_hook();
+	else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		led_shutdown_hook();
+}
+
+void led_alert(int enable)
+{
+	if (enable) {
+		/* Overwrite the current signal */
+		config_tick(1 * SECOND, 100, LED_RED);
+		led_tick();
+	} else {
+		/* Restore the previous signal */
+		if (chipset_in_state(CHIPSET_STATE_ON))
+			led_resume();
+		else if (chipset_in_state(CHIPSET_STATE_SUSPEND))
+			led_suspend_hook();
+		else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+			led_shutdown_hook();
+	}
+}
+
+void show_critical_error(void)
+{
+	hook_call_deferred(&led_tick_data, -1);
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_RED, 100);
+}
+
+static int command_led(int argc, const char **argv)
+{
+	enum ec_led_id id = EC_LED_ID_POWER_LED;
+
+	if (argc < 2)
+		return EC_ERROR_PARAM_COUNT;
+
+	if (!strcasecmp(argv[1], "debug")) {
+		led_auto_control(id, !led_auto_control_is_enabled(id));
+		ccprintf("o%s\n", led_auto_control_is_enabled(id) ? "ff" : "n");
+	} else if (!strcasecmp(argv[1], "off")) {
+		set_color(id, LED_OFF, 0);
+	} else if (!strcasecmp(argv[1], "red")) {
+		set_color(id, LED_RED, 100);
+	} else if (!strcasecmp(argv[1], "green")) {
+		set_color(id, LED_GREEN, 100);
+	} else if (!strcasecmp(argv[1], "alert")) {
+		led_alert(1);
+	} else if (!strcasecmp(argv[1], "crit")) {
+		show_critical_error();
+	} else {
+		return EC_ERROR_PARAM1;
+	}
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(led, command_led, "[debug|red|green|off|alert|crit]",
+			"Turn on/off LED.");
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	brightness_range[EC_LED_COLOR_RED] = 100;
+	brightness_range[EC_LED_COLOR_GREEN] = 100;
+}
+
+int led_set_brightness(enum ec_led_id id, const uint8_t *brightness)
+{
+	if (brightness[EC_LED_COLOR_RED])
+		return set_color(id, LED_RED, brightness[EC_LED_COLOR_RED]);
+	else if (brightness[EC_LED_COLOR_GREEN])
+		return set_color(id, LED_GREEN, brightness[EC_LED_COLOR_GREEN]);
+	else
+		return set_color(id, LED_OFF, 0);
+}
diff --git a/board/kinox/power_detection.c b/board/kinox/power_detection.c
new file mode 100644
index 0000000000..3fece05749
--- /dev/null
+++ b/board/kinox/power_detection.c
@@ -0,0 +1,438 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "adc.h"
+#include "charge_manager.h"
+#include "chipset.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "power.h"
+#include "registers.h"
+#include "task.h"
+#include "timer.h"
+#include "util.h"
+
+/* Console output macros */
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+/******************************************************************************/
+
+static const char *const adp_id_names[] = {
+	"unknown", "tiny", "tio1", "tio2", "typec",
+};
+
+/* ADP_ID control */
+struct adpater_id_params tio1_power[] = {
+	{
+		.min_voltage = 2816,
+		.max_voltage = 2816,
+		.charge_voltage = 20000,
+		.charge_current = 6000,
+		.watt = 120,
+		.obp95 = 1990,
+		.obp85 = 1780,
+	},
+};
+
+struct adpater_id_params tio2_power[] = {
+	{
+		.min_voltage = 0,
+		.max_voltage = 68,
+		.charge_voltage = 20000,
+		.charge_current = 8500,
+		.watt = 170,
+		.obp95 = 2816,
+		.obp85 = 2520,
+	},
+	{
+		.min_voltage = 68,
+		.max_voltage = 142,
+		.charge_voltage = 20000,
+		.charge_current = 2250,
+		.watt = 45,
+		.obp95 = 750,
+		.obp85 = 670,
+	},
+	{
+		.min_voltage = 200,
+		.max_voltage = 288,
+		.charge_voltage = 20000,
+		.charge_current = 3250,
+		.watt = 65,
+		.obp95 = 1080,
+		.obp85 = 960,
+	},
+	{
+		.min_voltage = 384,
+		.max_voltage = 480,
+		.charge_voltage = 20000,
+		.charge_current = 7500,
+		.watt = 150,
+		.obp95 = 2490,
+		.obp85 = 2220,
+	},
+	{
+		.min_voltage = 531,
+		.max_voltage = 607,
+		.charge_voltage = 20000,
+		.charge_current = 6000,
+		.watt = 120,
+		.obp95 = 1990,
+		.obp85 = 1780,
+	},
+	{
+		.min_voltage = 1062,
+		.max_voltage = 1126,
+		.charge_voltage = 20000,
+		.charge_current = 8500,
+		.watt = 170,
+		.obp95 = 2816,
+		.obp85 = 2520,
+	},
+	{
+		.min_voltage = 2816,
+		.max_voltage = 2816,
+		.charge_voltage = 20000,
+		.charge_current = 6000,
+		.watt = 120,
+		.obp95 = 1990,
+		.obp85 = 1780,
+	},
+};
+
+struct adpater_id_params tiny_power[] = {
+	{
+		.min_voltage = 68,
+		.max_voltage = 142,
+		.charge_voltage = 20000,
+		.charge_current = 2250,
+		.watt = 45,
+		.obp95 = 750,
+		.obp85 = 670,
+	},
+	{
+		.min_voltage = 200,
+		.max_voltage = 288,
+		.charge_voltage = 20000,
+		.charge_current = 3250,
+		.watt = 65,
+		.obp95 = 1080,
+		.obp85 = 960,
+	},
+	{
+		.min_voltage = 384,
+		.max_voltage = 480,
+		.charge_voltage = 20000,
+		.charge_current = 4500,
+		.watt = 90,
+		.obp95 = 1490,
+		.obp85 = 1330,
+	},
+	{
+		.min_voltage = 531,
+		.max_voltage = 607,
+		.charge_voltage = 20000,
+		.charge_current = 6000,
+		.watt = 120,
+		.obp95 = 1990,
+		.obp85 = 1780,
+	},
+	{
+		.min_voltage = 653,
+		.max_voltage = 783,
+		.charge_voltage = 20000,
+		.charge_current = 6750,
+		.watt = 135,
+		.obp95 = 2240,
+		.obp85 = 2000,
+	},
+	{
+		.min_voltage = 851,
+		.max_voltage = 997,
+		.charge_voltage = 20000,
+		.charge_current = 7500,
+		.watt = 150,
+		.obp95 = 2490,
+		.obp85 = 2220,
+	},
+	{
+		.min_voltage = 1063,
+		.max_voltage = 1226,
+		.charge_voltage = 20000,
+		.charge_current = 8500,
+		.watt = 170,
+		.obp95 = 2816,
+		.obp85 = 2520,
+	},
+	{
+		.min_voltage = 1749,
+		.max_voltage = 1968,
+		.charge_voltage = 20000,
+		.charge_current = 11500,
+		.watt = 230,
+		.obp95 = 2816,
+		.obp85 = 2815,
+	},
+};
+
+struct adpater_id_params typec_power[] = {
+	{
+		.charge_voltage = 20000,
+		.charge_current = 1500,
+		.watt = 30,
+		.obp95 = 500,
+		.obp85 = 440,
+	},
+	{
+		.charge_voltage = 15000,
+		.charge_current = 2000,
+		.watt = 30,
+		.obp95 = 660,
+		.obp85 = 590,
+	},
+	{
+		.charge_voltage = 20000,
+		.charge_current = 2250,
+		.watt = 45,
+		.obp95 = 750,
+		.obp85 = 670,
+	},
+	{
+		.charge_voltage = 15000,
+		.charge_current = 3000,
+		.watt = 45,
+		.obp95 = 990,
+		.obp85 = 890,
+	},
+	{
+		.charge_voltage = 20000,
+		.charge_current = 3250,
+		.watt = 65,
+		.obp95 = 1080,
+		.obp85 = 960,
+	},
+	{
+		.charge_voltage = 20000,
+		.charge_current = 5000,
+		.watt = 100,
+		.obp95 = 1660,
+		.obp85 = 1480,
+	},
+};
+
+struct adpater_id_params power_type[8];
+static int adp_id_value_debounce;
+
+void obp_point_95(void)
+{
+	/* Disable this interrupt while it's asserted. */
+	npcx_adc_thresh_int_enable(NPCX_ADC_THRESH1, 0);
+	/* Enable the voltage low interrupt. */
+	npcx_adc_thresh_int_enable(NPCX_ADC_THRESH2, 1);
+
+	/* Trigger the PROCHOT */
+	gpio_set_level(GPIO_EC_PROCHOT_ODL, 0);
+	CPRINTS("Adapter voltage over 95%% trigger prochot.");
+}
+
+void obp_point_85(void)
+{
+	/* Disable this interrupt while it's asserted. */
+	npcx_adc_thresh_int_enable(NPCX_ADC_THRESH2, 0);
+	/* Enable the voltage high interrupt. */
+	npcx_adc_thresh_int_enable(NPCX_ADC_THRESH1, 1);
+
+	/* Release the PROCHOT */
+	gpio_set_level(GPIO_EC_PROCHOT_ODL, 1);
+	CPRINTS("Adapter voltage lower than 85%% release prochot.");
+}
+
+struct npcx_adc_thresh_t adc_obp_point_95 = {
+	.adc_ch = ADC_PWR_IN_IMON,
+	.adc_thresh_cb = obp_point_95,
+	.thresh_assert = 3300, /* Default */
+};
+
+struct npcx_adc_thresh_t adc_obp_point_85 = {
+	.adc_ch = ADC_PWR_IN_IMON,
+	.adc_thresh_cb = obp_point_85,
+	.lower_or_higher = 1,
+	.thresh_assert = 0, /* Default */
+};
+
+static void set_up_adc_irqs(void)
+{
+	/* Set interrupt thresholds for the ADC. */
+	CPRINTS("%s", __func__);
+	npcx_adc_register_thresh_irq(NPCX_ADC_THRESH1, &adc_obp_point_95);
+	npcx_adc_register_thresh_irq(NPCX_ADC_THRESH2, &adc_obp_point_85);
+	npcx_set_adc_repetitive(adc_channels[ADC_PWR_IN_IMON].input_ch, 1);
+	npcx_adc_thresh_int_enable(NPCX_ADC_THRESH1, 1);
+	npcx_adc_thresh_int_enable(NPCX_ADC_THRESH2, 1);
+}
+
+void set_the_obp(int power_type_index, int adp_type)
+{
+	struct charge_port_info pi = { 0 };
+
+	adc_obp_point_95.thresh_assert = power_type[power_type_index].obp95;
+	adc_obp_point_85.thresh_assert = power_type[power_type_index].obp85;
+	set_up_adc_irqs();
+	if (adp_type != TYPEC) {
+		/* Only the TIO and Tiny need to update */
+		pi.voltage = power_type[power_type_index].charge_voltage;
+		pi.current = power_type[power_type_index].charge_current;
+
+		switch (adp_type) {
+		case TIO1:
+		case TIO2:
+			gpio_set_level(GPIO_SIO_LEGO_EN_L, 0);
+			charge_manager_update_charge(
+				CHARGE_SUPPLIER_PROPRIETARY,
+				DEDICATED_CHARGE_PORT, &pi);
+			break;
+		case TINY:
+			gpio_set_level(GPIO_SIO_LEGO_EN_L, 1);
+			charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED,
+						     DEDICATED_CHARGE_PORT,
+						     &pi);
+			break;
+		}
+	}
+
+	CPRINTS("Power type %s, %dW", adp_id_names[adp_type],
+		power_type[power_type_index].watt);
+}
+
+/*
+ *       Scalar change to   Scalar change to
+ *      downgrade voltage    3.3V voltage
+ *               |                |
+ *               |   SIO collect  |   SIO collect
+ *               |   1st adapter  |   2nd adapter
+ *               |   information  |   information
+ *               |   |  |  |  |   |   |  |  |  |
+ * -------------------------------------------------------
+ *  |            |                |
+ *  |---220 ms---|-----400 ms-----|
+ *
+ * Tiny: Twice adapter ADC values are less than 2.816v.
+ * TIO1: Twice adapter ADC values are 2.816v.
+ * TIO2: First adapter ADC value less than 2.816v.
+ *       Second adpater ADC value is 2.816v.
+ */
+static void adp_id_deferred(void);
+DECLARE_DEFERRED(adp_id_deferred);
+void adp_id_deferred(void)
+{
+	int i = 0;
+	int adp_type = 0;
+	int adp_id_value;
+	int adp_finial_adc_value;
+	int power_type_len = 0;
+
+	adp_id_value = adc_read_channel(ADC_ADP_ID);
+
+	if (!adp_id_value_debounce) {
+		adp_id_value_debounce = adp_id_value;
+		/* for delay the 400ms to get the next APD_ID value */
+		hook_call_deferred(&adp_id_deferred_data, 400 * MSEC);
+	} else if (adp_id_value_debounce == ADC_MAX_VOLT &&
+		   adp_id_value == ADC_MAX_VOLT) {
+		adp_finial_adc_value = adp_id_value;
+		adp_type = TIO1;
+	} else if (adp_id_value_debounce < ADC_MAX_VOLT &&
+		   adp_id_value == ADC_MAX_VOLT) {
+		adp_finial_adc_value = adp_id_value_debounce;
+		adp_type = TIO2;
+	} else if (adp_id_value_debounce < ADC_MAX_VOLT &&
+		   adp_id_value < ADC_MAX_VOLT) {
+		adp_finial_adc_value = adp_id_value;
+		adp_type = TINY;
+	} else {
+		CPRINTS("ADP_ID mismatch anything!");
+		/* Set the default TINY 45w adapter */
+		adp_finial_adc_value = 142;
+		adp_type = TINY;
+	}
+
+	switch (adp_type) {
+	case TIO1:
+		power_type_len =
+			sizeof(tio1_power) / sizeof(struct adpater_id_params);
+		memcpy(&power_type, &tio1_power, sizeof(tio1_power));
+		break;
+	case TIO2:
+		power_type_len =
+			sizeof(tio2_power) / sizeof(struct adpater_id_params);
+		memcpy(&power_type, &tio2_power, sizeof(tio2_power));
+		break;
+	case TINY:
+		power_type_len =
+			sizeof(tiny_power) / sizeof(struct adpater_id_params);
+		memcpy(&power_type, &tiny_power, sizeof(tiny_power));
+		break;
+	}
+
+	for (i = 0; (i < power_type_len) && adp_type; i++) {
+		if (adp_finial_adc_value <= power_type[i].max_voltage) {
+			set_the_obp(i, adp_type);
+			break;
+		}
+	}
+}
+
+static void barrel_jack_setting(void)
+{
+	struct charge_port_info pi = { 0 };
+	/* Check ADP_ID when barrel jack is present */
+	if (!gpio_get_level(GPIO_BJ_ADP_PRESENT_ODL)) {
+		/* Set the default TINY 45w adapter */
+		pi.voltage = 20000;
+		pi.current = 2250;
+
+		charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED,
+					     DEDICATED_CHARGE_PORT, &pi);
+
+		/* Delay 220ms to get the first ADP_ID value */
+		hook_call_deferred(&adp_id_deferred_data, 220 * MSEC);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, barrel_jack_setting, HOOK_PRIO_DEFAULT);
+
+static void typec_adapter_setting(void)
+{
+	int i = 0;
+	int adp_type = TYPEC;
+	int adapter_current_ma;
+	int power_type_len;
+
+	/* Check the barrel jack is not present */
+	if (gpio_get_level(GPIO_BJ_ADP_PRESENT_ODL)) {
+		adapter_current_ma = charge_manager_get_charger_current();
+		power_type_len =
+			sizeof(typec_power) / sizeof(struct adpater_id_params);
+
+		memcpy(&power_type, &typec_power, sizeof(typec_power));
+		for (i = (power_type_len - 1); i >= 0; i--) {
+			if (adapter_current_ma >=
+			    power_type[i].charge_current) {
+				set_the_obp(i, adp_type);
+				break;
+			}
+		}
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, typec_adapter_setting, HOOK_PRIO_DEFAULT);
+
+/* IRQ for BJ plug/unplug. It shouldn't be called if BJ is the power source. */
+void adp_connect_interrupt(enum gpio_signal signal)
+{
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		hook_call_deferred(&adp_id_deferred_data, 0);
+}
diff --git a/board/kinox/pwm.c b/board/kinox/pwm.c
new file mode 100644
index 0000000000..cee2bfd59c
--- /dev/null
+++ b/board/kinox/pwm.c
@@ -0,0 +1,33 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "hooks.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_LED_GREEN] = { .channel = 0,
+			       .flags = PWM_CONFIG_ACTIVE_LOW |
+					PWM_CONFIG_DSLEEP |
+					PWM_CONFIG_OPEN_DRAIN,
+			       .freq = 2000 },
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
+	[PWM_CH_LED_RED] = { .channel = 2,
+			     .flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+			     .freq = 2000 },
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+static void board_pwm_init(void)
+{
+	pwm_enable(PWM_CH_FAN, 1);
+	pwm_enable(PWM_CH_LED_RED, 1);
+	pwm_enable(PWM_CH_LED_GREEN, 1);
+}
+DECLARE_HOOK(HOOK_INIT, board_pwm_init, HOOK_PRIO_DEFAULT);
diff --git a/board/kinox/sensors.c b/board/kinox/sensors.c
new file mode 100644
index 0000000000..ea193ddc53
--- /dev/null
+++ b/board/kinox/sensors.c
@@ -0,0 +1,122 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc_chip.h"
+#include "common.h"
+#include "hooks.h"
+#include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
+#include "thermal.h"
+
+/* ADC configuration */
+const struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_1_CPU] = {
+		.name = "TEMP_CPU",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_2_CPU_VR] = {
+		.name = "TEMP_CPU_VR",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_3_WIFI] = {
+		.name = "TEMP_WIFI",
+		.input_ch = NPCX_ADC_CH6,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_4_DIMM] = {
+		.name = "TEMP_DIMM",
+		.input_ch = NPCX_ADC_CH7,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_VBUS] = {  /* 5/39 voltage divider */
+		.name = "VBUS",
+		.input_ch = NPCX_ADC_CH2,
+		.factor_mul = ADC_MAX_VOLT * 39,
+		.factor_div = (ADC_READ_MAX + 1) * 5,
+	},
+	[ADC_PWR_IN_IMON] = {
+		.name = "PWR_IN_IMON",
+		.input_ch = NPCX_ADC_CH3,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX,
+	},
+	[ADC_ADP_ID] = {
+		.name = "ADP_ID",
+		.input_ch = NPCX_ADC_CH4,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* Temperature sensor configuration */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1_CPU] = { .name = "CPU",
+				.type = TEMP_SENSOR_TYPE_BOARD,
+				.read = get_temp_3v3_30k9_47k_4050b,
+				.idx = ADC_TEMP_SENSOR_1_CPU },
+	[TEMP_SENSOR_2_CPU_VR] = { .name = "CPU VR",
+				   .type = TEMP_SENSOR_TYPE_BOARD,
+				   .read = get_temp_3v3_30k9_47k_4050b,
+				   .idx = ADC_TEMP_SENSOR_2_CPU_VR },
+	[TEMP_SENSOR_3_WIFI] = { .name = "WIFI",
+				 .type = TEMP_SENSOR_TYPE_BOARD,
+				 .read = get_temp_3v3_30k9_47k_4050b,
+				 .idx = ADC_TEMP_SENSOR_3_WIFI },
+	[TEMP_SENSOR_4_DIMM] = { .name = "DIMM",
+				 .type = TEMP_SENSOR_TYPE_BOARD,
+				 .read = get_temp_3v3_30k9_47k_4050b,
+				 .idx = ADC_TEMP_SENSOR_4_DIMM },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/*
+ * TODO(b/180681346): update for Alder Lake/brya
+ *
+ * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
+ * 130 C.  However, sensor is located next to DDR, so we need to use the lower
+ * DDR temperature limit (85 C)
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(95), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(100), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(90), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(90), \
+		}, \
+		.temp_fan_off = C_TO_K(25), \
+		.temp_fan_max = C_TO_K(75), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
+
+/*
+ * TODO(b/197478860): add the thermal sensor setting
+ */
+/* this should really be "const" */
+struct ec_thermal_config thermal_params[] = {
+	[TEMP_SENSOR_1_CPU] = THERMAL_CPU,
+	[TEMP_SENSOR_2_CPU_VR] = THERMAL_CPU,
+	[TEMP_SENSOR_3_WIFI] = THERMAL_CPU,
+	[TEMP_SENSOR_4_DIMM] = THERMAL_CPU,
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
diff --git a/board/kinox/usbc_config.c b/board/kinox/usbc_config.c
new file mode 100644
index 0000000000..381f82be44
--- /dev/null
+++ b/board/kinox/usbc_config.c
@@ -0,0 +1,183 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/bc12/pi3usb9201_public.h"
+#include "driver/ppc/syv682x_public.h"
+#include "driver/tcpm/ps8xxx_public.h"
+#include "driver/tcpm/tcpci.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "system.h"
+#include "task.h"
+#include "task_id.h"
+#include "timer.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+/* USBC TCPC configuration */
+const struct tcpc_config_t tcpc_config[] = {
+	[USBC_PORT_C0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0_TCPC,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V |
+			TCPC_FLAGS_CONTROL_VCONN |
+			TCPC_FLAGS_CONTROL_FRS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
+BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
+
+/* USBC PPC configuration */
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_PPC,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.drv = &syv682x_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/* USBC mux configuration - Alder Lake includes internal mux */
+static const struct usb_mux_chain usbc0_usb3_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
+};
+
+const struct usb_mux_chain usb_muxes[] = {
+	[USBC_PORT_C0] = {
+		.mux = &(const struct usb_mux) {
+			/* PS8815 */
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc0_usb3_retimer,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
+
+/* BC1.2 charger detect configuration */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * TODO(b/179648104): figure out correct timing
+	 */
+
+	gpio_set_level(GPIO_USB_C0_RT_RST_R_ODL, 0);
+
+	/*
+	 * delay for power-on to reset-off and min. assertion time
+	 */
+	msleep(20);
+
+	gpio_set_level(GPIO_USB_C0_RT_RST_R_ODL, 1);
+
+	/* wait for chips to come up */
+	msleep(50);
+}
+
+static void board_tcpc_init(void)
+{
+	/* Don't reset TCPCs after initial reset */
+	if (!system_jumped_late())
+		board_reset_pd_mcu();
+
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_0;
+
+	return status;
+}
+
+int ppc_get_alert_status(int port)
+{
+	if (port == USBC_PORT_C0)
+		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
+	return 0;
+}
+
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C0);
+		break;
+	default:
+		break;
+	}
+}
+
+void bc12_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_BC12_INT_ODL:
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+		break;
+	default:
+		break;
+	}
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C0);
+		break;
+	default:
+		break;
+	}
+}
+
+void retimer_interrupt(enum gpio_signal signal)
+{
+	/*
+	 * TODO(b/179513527): add USB-C support
+	 */
+}
diff --git a/board/kinox/usbc_config.h b/board/kinox/usbc_config.h
new file mode 100644
index 0000000000..7a212f8fb6
--- /dev/null
+++ b/board/kinox/usbc_config.h
@@ -0,0 +1,15 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Brya board-specific USB-C configuration */
+
+#ifndef __CROS_EC_USBC_CONFIG_H
+#define __CROS_EC_USBC_CONFIG_H
+
+#define CONFIG_USB_PD_PORT_MAX_COUNT 1
+
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_COUNT };
+
+#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/kinox/vif_override.xml b/board/kinox/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/kinox/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/kodama/battery.c b/board/kodama/battery.c
index 1dbff92a00..1c6737bd3a 100644
--- a/board/kodama/battery.c
+++ b/board/kodama/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,7 +14,7 @@
 #include "usb_pd.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 const struct board_batt_params board_battery_info[] = {
 	[BATTERY_SIMPLO] = {
@@ -95,9 +95,9 @@ int charger_profile_override(struct charge_state_data *curr)
 	 * When smart battery temperature is more than 45 deg C, the max
 	 * charging voltage is 4100mV.
 	 */
-	if (curr->state == ST_CHARGE && bat_temp_c >= 450
-		&& !(curr->batt.flags & BATT_FLAG_BAD_TEMPERATURE))
-		curr->requested_voltage	= 4100;
+	if (curr->state == ST_CHARGE && bat_temp_c >= 450 &&
+	    !(curr->batt.flags & BATT_FLAG_BAD_TEMPERATURE))
+		curr->requested_voltage = 4100;
 	else
 		curr->requested_voltage = batt_info->voltage_max;
 
diff --git a/board/kodama/board.c b/board/kodama/board.c
index 2fab43d3ac..d378410639 100644
--- a/board/kodama/board.c
+++ b/board/kodama/board.c
@@ -1,10 +1,9 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "button.h"
 #include "charge_manager.h"
 #include "charge_ramp.h"
@@ -26,6 +25,7 @@
 #include "i2c.h"
 #include "i2c_bitbang.h"
 #include "lid_switch.h"
+#include "panic.h"
 #include "power.h"
 #include "power_button.h"
 #include "pwm.h"
@@ -34,57 +34,71 @@
 #include "spi.h"
 #include "system.h"
 #include "task.h"
-#include "tcpm.h"
+#include "tcpm/tcpm.h"
 #include "timer.h"
 #include "usb_charge.h"
 #include "usb_mux.h"
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
 	schedule_deferred_pd_interrupt(0 /* port */);
 }
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /******************************************************************************/
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] = {"BOARD_ID", 3300, 4096, 0, STM32_AIN(10)},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)},
-	[ADC_POGO_ADC_INT_L] = {"POGO_ADC_INT_L", 3300, 4096, 0, STM32_AIN(6)},
+	[ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(10) },
+	[ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8) },
+	[ADC_POGO_ADC_INT_L] = { "POGO_ADC_INT_L", 3300, 4096, 0,
+				 STM32_AIN(6) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /******************************************************************************/
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{"typec", 0, 400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"other", 1, 400, GPIO_I2C2_SCL, GPIO_I2C2_SDA,
-		.flags = I2C_PORT_FLAG_DYNAMIC_SPEED},
+	{ .name = "typec",
+	  .port = 0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "other",
+	  .port = 1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA,
+	  .flags = I2C_PORT_FLAG_DYNAMIC_SPEED },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
 const struct i2c_port_t i2c_bitbang_ports[] = {
-	{"battery", 2, 100, GPIO_I2C3_SCL, GPIO_I2C3_SDA, .drv = &bitbang_drv},
+	{ .name = "battery",
+	  .port = 2,
+	  .kbps = 100,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA,
+	  .drv = &bitbang_drv },
 };
 const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
 
 /* power signal list.  Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
+	{ GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" },
+	{ GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" },
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
 /******************************************************************************/
 /* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
+const struct spi_device_t spi_devices[] = {};
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
 /******************************************************************************/
@@ -104,9 +118,12 @@ struct mt6370_thermal_bound thermal_bound = {
 	.err = 4,
 };
 
-static void board_hpd_status(const struct usb_mux *me,
-			     int hpd_lvl, int hpd_irq)
+static void board_hpd_status(const struct usb_mux *me, mux_state_t mux_state,
+			     bool *ack_required)
 {
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
 	/*
 	 * svdm_dp_attention() did most of the work, we only need to notify
 	 * host here.
@@ -114,7 +131,6 @@ static void board_hpd_status(const struct usb_mux *me,
 	host_set_single_event(EC_HOST_EVENT_USB_MUX);
 }
 
-
 __override const struct rt946x_init_setting *board_rt946x_init_setting(void)
 {
 	static const struct rt946x_init_setting battery_init_setting = {
@@ -129,13 +145,16 @@ __override const struct rt946x_init_setting *board_rt946x_init_setting(void)
 	return &battery_init_setting;
 }
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+				.hpd_update = &board_hpd_status,
+			},
 	},
 };
 
@@ -165,7 +184,7 @@ int board_set_active_charge_port(int charge_port)
 		if (board_vbus_source_enabled(charge_port))
 			return -1;
 		break;
-	case CHARGE_PORT_NONE:
+	default:
 		/*
 		 * To ensure the fuel gauge (max17055) is always powered
 		 * even when battery is disconnected, keep VBAT rail on but
@@ -173,9 +192,6 @@ int board_set_active_charge_port(int charge_port)
 		 */
 		charger_set_current(CHARGER_SOLO, 0);
 		break;
-	default:
-		panic("Invalid charge port\n");
-		break;
 	}
 
 	return EC_SUCCESS;
@@ -216,9 +232,8 @@ int extpower_is_present(void)
 	if (board_vbus_source_enabled(CHARGE_PORT_USB_C))
 		usb_c_extpower_present = 0;
 	else
-		usb_c_extpower_present = tcpm_check_vbus_level(
-							CHARGE_PORT_USB_C,
-							VBUS_PRESENT);
+		usb_c_extpower_present =
+			tcpm_check_vbus_level(CHARGE_PORT_USB_C, VBUS_PRESENT);
 
 	return usb_c_extpower_present;
 }
@@ -238,11 +253,11 @@ static void board_init(void)
 #ifdef SECTION_IS_RW
 	int val;
 
-	i2c_read8(I2C_PORT_CHARGER, CHARGER_I2C_ADDR_FLAGS,
-			RT946X_REG_CHGCTRL1, &val);
+	i2c_read8(I2C_PORT_CHARGER, CHARGER_I2C_ADDR_FLAGS, RT946X_REG_CHGCTRL1,
+		  &val);
 	val &= RT946X_MASK_OPA_MODE;
 	i2c_write8(I2C_PORT_CHARGER, CHARGER_I2C_ADDR_FLAGS,
-		RT946X_REG_CHGCTRL1, (val | RT946X_MASK_STAT_EN));
+		   RT946X_REG_CHGCTRL1, (val | RT946X_MASK_STAT_EN));
 #endif
 
 	/* If the reset cause is external, pulse PMIC force reset. */
@@ -295,7 +310,7 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 static void board_i2c_init(void)
 {
 	if (board_get_version() < 2)
-		i2c_set_freq(1,  I2C_FREQ_100KHZ);
+		i2c_set_freq(1, I2C_FREQ_100KHZ);
 }
 DECLARE_HOOK(HOOK_INIT, board_i2c_init, HOOK_PRIO_INIT_I2C);
 
@@ -307,11 +322,9 @@ static struct mutex g_lid_mutex;
 static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
 
 /* Matrix to rotate accelerometer into standard reference frame */
-static const mat33_fp_t lid_standard_ref = {
-	{0, FLOAT_TO_FP(1), 0},
-	{FLOAT_TO_FP(-1), 0, 0},
-	{0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					     { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
@@ -323,8 +336,6 @@ struct motion_sensor_t motion_sensors[] = {
 	 .drv = &lsm6dsm_drv,
 	 .mutex = &g_lid_mutex,
 	 .drv_data = LSM6DSM_ST_DATA(lsm6dsm_data, MOTIONSENSE_TYPE_ACCEL),
-	 .int_signal = GPIO_ACCEL_INT_ODL,
-	 .flags = MOTIONSENSE_FLAG_INT_SIGNAL,
 	 .port = I2C_PORT_ACCEL,
 	 .i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
 	 .rot_standard_ref = &lid_standard_ref,
diff --git a/board/kodama/board.h b/board/kodama/board.h
index cf71fe5dd2..b22ab2153f 100644
--- a/board/kodama/board.h
+++ b/board/kodama/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,8 +10,10 @@
 
 #define VARIANT_KUKUI_BATTERY_SMART
 #define VARIANT_KUKUI_CHARGER_MT6370
+#define VARIANT_KUKUI_EC_STM32F098
 #define VARIANT_KUKUI_POGO_KEYBOARD
 #define VARIANT_KUKUI_TABLET_PWRBTN
+#undef CONFIG_CMD_MFALLOW
 
 #ifndef SECTION_IS_RW
 #define VARIANT_KUKUI_NO_SENSORS
@@ -19,12 +21,13 @@
 
 #include "baseboard.h"
 
+#define CONFIG_DEBUG_ASSERT_BRIEF
+
 #define CONFIG_VOLUME_BUTTONS
 
 #define CONFIG_USB_MUX_IT5205
 
 #define CONFIG_LED_ONOFF_STATES
-#define CONFIG_LED_POWER_LED
 
 #define CONFIG_BATTERY_HW_PRESENT_CUSTOM
 
@@ -35,7 +38,7 @@
 #define CONFIG_SMBUS_PEC
 
 /* Battery */
-#define BATTERY_DESIRED_CHARGING_CURRENT    2000  /* mA */
+#define BATTERY_DESIRED_CHARGING_CURRENT 2000 /* mA */
 
 #define CONFIG_CHARGER_MT6370_BACKLIGHT
 #define CONFIG_CHARGER_MAINTAIN_VBAT
@@ -43,32 +46,37 @@
 /* Motion Sensors */
 #ifdef SECTION_IS_RW
 #define CONFIG_ACCELGYRO_LSM6DSM
-#define CONFIG_ACCEL_INTERRUPTS
 #define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
 
 /* Camera VSYNC */
 #define CONFIG_SYNC
 #define CONFIG_SYNC_COMMAND
-#define CONFIG_SYNC_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
+#define CONFIG_SYNC_INT_EVENT TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
 #endif /* SECTION_IS_RW */
 
+/* Disable verbose output in EC pd */
+#define CONFIG_CMD_PD_SRCCAPS_REDUCED_SIZE
+
 /* I2C ports */
-#define I2C_PORT_CHARGER  0
-#define I2C_PORT_TCPC0    0
-#define I2C_PORT_USB_MUX  0
-#define I2C_PORT_ACCEL    1
-#define I2C_PORT_BATTERY  board_get_battery_i2c()
+#define I2C_PORT_CHARGER 0
+#define I2C_PORT_TCPC0 0
+#define I2C_PORT_USB_MUX 0
+#define I2C_PORT_ACCEL 1
+#define I2C_PORT_BATTERY board_get_battery_i2c()
 #define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
 
 /* Define the host events which are allowed to wakeup AP in S3. */
-#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \
-		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+#define CONFIG_MKBP_INPUT_DEVICES
 
 #define PD_OPERATING_POWER_MW 15000
 
+/* Free up flash in RO. */
+#ifdef SECTION_IS_RO
+#undef CONFIG_USB_PD_HOST_CMD
+#undef CONFIG_USB_PD_CONSOLE_CMD
+#endif
+
 #ifndef __ASSEMBLER__
 
 enum adc_channel {
@@ -116,7 +124,6 @@ void emmc_cmd_interrupt(enum gpio_signal signal);
 
 void board_reset_pd_mcu(void);
 int board_get_version(void);
-int board_is_sourcing_vbus(int port);
 void pogo_adc_interrupt(enum gpio_signal signal);
 int board_discharge_on_ac(int enable);
 /* returns the i2c port number of battery */
diff --git a/board/kodama/build.mk b/board/kodama/build.mk
index 0b3565fd84..6a7e557a0e 100644
--- a/board/kodama/build.mk
+++ b/board/kodama/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/kodama/ec.tasklist b/board/kodama/ec.tasklist
index f71a208dd6..e66c52616b 100644
--- a/board/kodama/ec.tasklist
+++ b/board/kodama/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/kodama/gpio.inc b/board/kodama/gpio.inc
index 75a3db7d20..d72532ff70 100644
--- a/board/kodama/gpio.inc
+++ b/board/kodama/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/kodama/led.c b/board/kodama/led.c
index 61d29f9d16..8ea6f2e308 100644
--- a/board/kodama/led.c
+++ b/board/kodama/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -6,49 +6,53 @@
  */
 #include "charge_state.h"
 #include "driver/charger/rt946x.h"
+#include "ec_commands.h"
 #include "hooks.h"
 #include "led_common.h"
 #include "led_onoff_states.h"
-#include "ec_commands.h"
 
-#define LED_RED		MT6370_LED_ID1
-#define LED_GREEN	MT6370_LED_ID2
-#define LED_WHITE	MT6370_LED_ID3
-
-#define LED_MASK_OFF	0
-#define LED_MASK_RED	MT6370_MASK_RGB_ISNK1DIM_EN
-#define LED_MASK_GREEN	MT6370_MASK_RGB_ISNK2DIM_EN
-#define LED_MASK_WHITE	MT6370_MASK_RGB_ISNK3DIM_EN
-
-const int led_charge_lvl_1 = 5;
-const int led_charge_lvl_2 = 97;
-
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
-
-const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-					{LED_OFF,	   LED_ONE_SEC / 2} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-	EC_LED_ID_BATTERY_LED
-};
+#define LED_RED MT6370_LED_ID1
+#define LED_GREEN MT6370_LED_ID2
+#define LED_WHITE MT6370_LED_ID3
+
+#define LED_MASK_OFF 0
+#define LED_MASK_RED MT6370_MASK_RGB_ISNK1DIM_EN
+#define LED_MASK_GREEN MT6370_MASK_RGB_ISNK2DIM_EN
+#define LED_MASK_WHITE MT6370_MASK_RGB_ISNK3DIM_EN
+
+__override const int led_charge_lvl_1 = 5;
+__override const int led_charge_lvl_2 = 97;
+
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
+
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 3 * LED_ONE_SEC },
+					       { LED_OFF, LED_ONE_SEC / 2 } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED,
+					     EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -66,7 +70,7 @@ static void led_set_color(int mask)
 	mt6370_led_set_color(led_mask);
 }
 
-void led_set_color_power(enum ec_led_colors color)
+__override void led_set_color_power(enum ec_led_colors color)
 {
 	if (color == EC_LED_COLOR_WHITE)
 		led_mask |= LED_MASK_WHITE;
@@ -75,7 +79,7 @@ void led_set_color_power(enum ec_led_colors color)
 	led_set_color(led_mask);
 }
 
-void led_set_color_battery(enum ec_led_colors color)
+__override void led_set_color_battery(enum ec_led_colors color)
 {
 	switch (color) {
 	case EC_LED_COLOR_RED:
diff --git a/board/kodama/vif_override.xml b/board/kodama/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/kodama/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/kohaku/battery.c b/board/kohaku/battery.c
index 1d311d69f1..693c5b5221 100644
--- a/board/kohaku/battery.c
+++ b/board/kohaku/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -6,6 +6,7 @@
  */
 
 #include "battery_fuel_gauge.h"
+#include "charge_state.h"
 #include "common.h"
 #include "system.h"
 #include "util.h"
@@ -32,6 +33,10 @@
  * status can be read with a sb_read() command and therefore, only the register
  * address, mask, and disconnect value need to be provided.
  */
+
+/* charging current is limited to 0.45C */
+#define CHARGING_CURRENT_45C 2804
+
 const struct board_batt_params board_battery_info[] = {
 	/* Dyna Battery Information */
 	[BATTERY_DYNA] = {
@@ -106,3 +111,29 @@ enum battery_present variant_battery_present(void)
 	 */
 	return BP_YES;
 }
+
+int charger_profile_override(struct charge_state_data *curr)
+{
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return 0;
+
+	if (curr->requested_current > CHARGING_CURRENT_45C)
+		curr->requested_current = CHARGING_CURRENT_45C;
+
+	return 0;
+}
+
+/* Customs options controllable by host command. */
+#define PARAM_FASTCHARGE (CS_PARAM_CUSTOM_PROFILE_MIN + 0)
+
+enum ec_status charger_profile_override_get_param(uint32_t param,
+						  uint32_t *value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+enum ec_status charger_profile_override_set_param(uint32_t param,
+						  uint32_t value)
+{
+	return EC_RES_INVALID_PARAM;
+}
diff --git a/board/kohaku/board.c b/board/kohaku/board.c
index 8f261dff23..fc7f77b369 100644
--- a/board/kohaku/board.c
+++ b/board/kohaku/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,6 @@
 /* Kohaku board-specific configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "button.h"
 #include "common.h"
 #include "cros_board_info.h"
@@ -14,8 +13,8 @@
 #include "driver/accelgyro_bmi_common.h"
 #include "driver/als_bh1730.h"
 #include "driver/als_tcs3400.h"
-#include "driver/ppc/sn5s330.h"
 #include "driver/bc12/max14637.h"
+#include "driver/ppc/sn5s330.h"
 #include "driver/sync.h"
 #include "driver/tcpm/ps8xxx.h"
 #include "driver/tcpm/tcpci.h"
@@ -34,16 +33,16 @@
 #include "system.h"
 #include "task.h"
 #include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
 #include "thermal.h"
-#include "thermistor.h"
 #include "uart.h"
 #include "usb_charge.h"
 #include "usb_pd.h"
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void ppc_interrupt(enum gpio_signal signal)
 {
@@ -83,11 +82,11 @@ static void bc12_interrupt(enum gpio_signal signal)
 {
 	switch (signal) {
 	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
 		break;
 
 	case GPIO_USB_C1_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12, 0);
+		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
 		break;
 
 	default:
@@ -95,18 +94,18 @@ static void bc12_interrupt(enum gpio_signal signal)
 	}
 }
 
-#include "gpio_list.h" /* Must come after other header files. */
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
 
 /******************************************************************************/
 /* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
+const struct spi_device_t spi_devices[] = {};
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
 /******************************************************************************/
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT]   = { .channel = 3, .flags = 0, .freq = 10000 },
+	[PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
@@ -117,7 +116,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = I2C_PORT_TCPC0,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
 		},
 		.drv = &ps8xxx_tcpm_drv,
 	},
@@ -125,22 +124,26 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = I2C_PORT_TCPC1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
 		},
 		.drv = &ps8xxx_tcpm_drv,
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_TCPC_0] = {
-		.usb_port = USB_PD_PORT_TCPC_0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_0,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 	},
 	[USB_PD_PORT_TCPC_1] = {
-		.usb_port = USB_PD_PORT_TCPC_1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 	}
 };
 
@@ -224,11 +227,9 @@ static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
 };
 
 /* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					      { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
@@ -313,12 +314,11 @@ struct motion_sensor_t motion_sensors[] = {
 		.i2c_spi_addr_flags = BH1730_I2C_ADDR_FLAGS,
 		.rot_standard_ref = NULL,
 		.default_range = 65535,
-		.min_frequency = 10,
-		.max_frequency = 10,
+		.min_frequency = BH1730_MIN_FREQ,
+		.max_frequency = BH1730_MAX_FREQ,
 		.config = {
 			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 100000,
-				.ec_rate = 0,
+				.odr = BH1730_10000_MHZ,
 			},
 		},
 	},
@@ -385,34 +385,34 @@ BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
 /**********************************************************************/
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		"TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_2] = {
-		"TEMP_AMB", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_3] = {
-		"TEMP_GT", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_4] = {
-		"TEMP_IA", NPCX_ADC_CH3, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_1] = { "TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_2] = { "TEMP_AMB", NPCX_ADC_CH1, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_3] = { "TEMP_GT", NPCX_ADC_CH2, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_4] = { "TEMP_IA", NPCX_ADC_CH3, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "GT",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_3},
-	[TEMP_SENSOR_4] = {.name = "IA",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_4},
+	[TEMP_SENSOR_1] = { .name = "Charger",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "GT",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
+	[TEMP_SENSOR_4] = { .name = "IA",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_4 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -422,26 +422,31 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
  * for Kohaku. They matter when the EC is controlling the fan as opposed to DPTF
  * control.
  */
-const static struct ec_thermal_config thermal_a = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(90),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(25),
-	.temp_fan_max = C_TO_K(50),
-};
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_A                \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(90), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+		.temp_fan_off = C_TO_K(25), \
+		.temp_fan_max = C_TO_K(50), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A;
 
 struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1] = thermal_a,
-	[TEMP_SENSOR_2] = thermal_a,
-	[TEMP_SENSOR_3] = thermal_a,
-	[TEMP_SENSOR_4] = thermal_a,
+	[TEMP_SENSOR_1] = THERMAL_A,
+	[TEMP_SENSOR_2] = THERMAL_A,
+	[TEMP_SENSOR_3] = THERMAL_A,
+	[TEMP_SENSOR_4] = THERMAL_A,
 };
 BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
 
diff --git a/board/kohaku/board.h b/board/kohaku/board.h
index 196365b9da..d120e308aa 100644
--- a/board/kohaku/board.h
+++ b/board/kohaku/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,9 +18,8 @@
 #define CONFIG_KEYBOARD_PROTOCOL_8042
 #define CONFIG_LED_COMMON
 #define CONFIG_LOW_POWER_IDLE
-#define CONFIG_LED_POWER_LED
 
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 
 #undef CONFIG_UART_TX_BUF_SIZE
 #define CONFIG_UART_TX_BUF_SIZE 4096
@@ -30,15 +29,13 @@
 
 /* Sensors */
 /* BMI160 Base accel/gyro */
-#define CONFIG_ACCEL_INTERRUPTS
 #define CONFIG_ACCELGYRO_BMI160
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 #define CONFIG_ACCELGYRO_BMI160_INT2_OUTPUT
 /* Camera VSYNC */
 #define CONFIG_SYNC
-#define CONFIG_SYNC_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
+#define CONFIG_SYNC_INT_EVENT TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
 /* BMA253 Lid accel */
 #define CONFIG_ACCEL_BMA255
 #define CONFIG_LID_ANGLE
@@ -48,7 +45,7 @@
 /* BH1730 and TCS3400 ALS */
 #define CONFIG_ALS
 #define ALS_COUNT 2
-#define I2C_PORT_ALS      I2C_PORT_SENSOR
+#define I2C_PORT_ALS I2C_PORT_SENSOR
 #define CONFIG_ALS_BH1730
 #define CONFIG_ALS_TCS3400
 #define CONFIG_ALS_TCS3400_INT_EVENT \
@@ -72,18 +69,18 @@
  * Kohaku will not use both BH1730_LUXTH3_1K condition
  * and BH1730_LUXTH4_1K condition.
  */
-#define BH1730_LUXTH1_1K                270
-#define BH1730_LUXTH1_D0_1K             19200
-#define BH1730_LUXTH1_D1_1K             30528
-#define BH1730_LUXTH2_1K                655360000
-#define BH1730_LUXTH2_D0_1K             11008
-#define BH1730_LUXTH2_D1_1K             10752
-#define BH1730_LUXTH3_1K                1030
-#define BH1730_LUXTH3_D0_1K             11008
-#define BH1730_LUXTH3_D1_1K             10752
-#define BH1730_LUXTH4_1K                3670
-#define BH1730_LUXTH4_D0_1K             11008
-#define BH1730_LUXTH4_D1_1K             10752
+#define BH1730_LUXTH1_1K 270
+#define BH1730_LUXTH1_D0_1K 19200
+#define BH1730_LUXTH1_D1_1K 30528
+#define BH1730_LUXTH2_1K 655360000
+#define BH1730_LUXTH2_D0_1K 11008
+#define BH1730_LUXTH2_D1_1K 10752
+#define BH1730_LUXTH3_1K 1030
+#define BH1730_LUXTH3_D0_1K 11008
+#define BH1730_LUXTH3_D1_1K 10752
+#define BH1730_LUXTH4_1K 3670
+#define BH1730_LUXTH4_D0_1K 11008
+#define BH1730_LUXTH4_D1_1K 10752
 
 /* USB Type C and USB PD defines */
 #define CONFIG_USB_PD_COMM_LOCKED
@@ -113,6 +110,7 @@
  */
 #define CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA 6144
 #define CONFIG_BATTERY_CHECK_CHARGE_TEMP_LIMITS
+#define CONFIG_CHARGER_PROFILE_OVERRIDE
 
 /* Volume Button feature */
 #define CONFIG_VOLUME_BUTTONS
@@ -120,7 +118,7 @@
 #define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
 
 /* Thermal features */
-#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_A_RAILS
+#define CONFIG_TEMP_SENSOR_POWER
 #define CONFIG_THERMISTOR
 #define CONFIG_THROTTLE_AP
 #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
@@ -131,15 +129,16 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_AC_PRESENT		GPIO_ACOK_OD
-#define GPIO_RSMRST_L_PGOOD	GPIO_PG_EC_RSMRST_L
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L
+#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
 
 #ifndef __ASSEMBLER__
 
@@ -150,10 +149,10 @@
 extern enum gpio_signal gpio_en_pp5000_a;
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_1,	/* ADC0 */
-	ADC_TEMP_SENSOR_2,	/* ADC1 */
-	ADC_TEMP_SENSOR_3,	/* ADC2 */
-	ADC_TEMP_SENSOR_4,	/* ADC3 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
+	ADC_TEMP_SENSOR_3, /* ADC2 */
+	ADC_TEMP_SENSOR_4, /* ADC3 */
 	ADC_CH_COUNT
 };
 
@@ -168,10 +167,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_COUNT };
 
 enum temp_sensor_id {
 	TEMP_SENSOR_1,
diff --git a/board/kohaku/build.mk b/board/kohaku/build.mk
index 733912454f..13153c1526 100644
--- a/board/kohaku/build.mk
+++ b/board/kohaku/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/kohaku/ec.tasklist b/board/kohaku/ec.tasklist
index 63d366a33b..7fb3e38b63 100644
--- a/board/kohaku/ec.tasklist
+++ b/board/kohaku/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/kohaku/gpio.inc b/board/kohaku/gpio.inc
index 742a570cf8..eaddb14e2b 100644
--- a/board/kohaku/gpio.inc
+++ b/board/kohaku/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,10 +16,10 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(PG_EC_RSMRST_L,       PIN(E, 2), GPIO_INT_BOTH, intel_x86_rsmrst_signal_interrupt)
diff --git a/board/kohaku/led.c b/board/kohaku/led.c
index 58cdf6f175..2fbf2da3a5 100644
--- a/board/kohaku/led.c
+++ b/board/kohaku/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -12,53 +12,56 @@
 #include "led_common.h"
 #include "led_onoff_states.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
-const int led_charge_lvl_1 = 0;
+__override const int led_charge_lvl_1;
 
-const int led_charge_lvl_2 = 100;
+__override const int led_charge_lvl_2 = 100;
 
 /* Kohaku : There are 3 leds for AC, Battery and Power */
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED, 0.5 * LED_ONE_SEC},
-					{LED_OFF, 0.5 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC},
-					{LED_OFF, 1 * LED_ONE_SEC} },
-};
-
-const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_GREEN,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED,
+					    0.5 * LED_ONE_SEC },
+					  { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					 { LED_OFF, 1 * LED_ONE_SEC } },
+	};
+
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_BLUE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-void led_set_color_power(enum ec_led_colors color)
+__override void led_set_color_power(enum ec_led_colors color)
 {
 	/* Don't set led if led_auto_control is disabled. */
 	if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) ||
-		!led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
+	    !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
 		return;
 	}
 
-	if (color == EC_LED_COLOR_BLUE)
-	{
+	if (color == EC_LED_COLOR_BLUE) {
 		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
 		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
 		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_ON_LVL);
@@ -68,19 +71,18 @@ void led_set_color_power(enum ec_led_colors color)
 	}
 }
 
-void led_set_color_battery(enum ec_led_colors color)
+__override void led_set_color_battery(enum ec_led_colors color)
 {
 	/* Don't set led if led_auto_control is disabled. */
 	if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) ||
-		!led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
+	    !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
 		return;
 	}
 
 	/* Battery leds must be turn off when blue led is on
 	 * because kohaku has 3-in-1 led.
 	 */
-	if(!gpio_get_level(GPIO_PWR_LED_BLUE_L))
-	{
+	if (!gpio_get_level(GPIO_PWR_LED_BLUE_L)) {
 		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
 		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
 		return;
@@ -116,10 +118,13 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 {
 	if (led_id == EC_LED_ID_BATTERY_LED) {
 		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, !brightness[EC_LED_COLOR_GREEN]);
-		gpio_set_level(GPIO_BAT_LED_RED_L, !brightness[EC_LED_COLOR_RED]);
+		gpio_set_level(GPIO_BAT_LED_GREEN_L,
+			       !brightness[EC_LED_COLOR_GREEN]);
+		gpio_set_level(GPIO_BAT_LED_RED_L,
+			       !brightness[EC_LED_COLOR_RED]);
 	} else if (led_id == EC_LED_ID_POWER_LED) {
-		gpio_set_level(GPIO_PWR_LED_BLUE_L, !brightness[EC_LED_COLOR_BLUE]);
+		gpio_set_level(GPIO_PWR_LED_BLUE_L,
+			       !brightness[EC_LED_COLOR_BLUE]);
 		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
 		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
 	}
diff --git a/board/kohaku/vif_override.xml b/board/kohaku/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/kohaku/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/kracko/battery.c b/board/kracko/battery.c
new file mode 100644
index 0000000000..4b8bbb7351
--- /dev/null
+++ b/board/kracko/battery.c
@@ -0,0 +1,99 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "charge_state.h"
+#include "common.h"
+
+/*
+ * Battery info for all kracko battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	/* Simplo Battery Information */
+	[BATTERY_SIMPLO] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP-4473A9PU",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,	/* mV */
+			.voltage_normal = 7700,
+			.voltage_min = 6000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -20,
+			.discharging_max_c = 60,
+		},
+	},
+
+	/* CosMX Battery Information */
+	[BATTERY_COS] = {
+		.fuel_gauge = {
+			.manuf_name = "333-AC-0D-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,	/* mV */
+			.voltage_normal = 7700,
+			.voltage_min = 6000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SIMPLO;
diff --git a/board/kracko/board.c b/board/kracko/board.c
new file mode 100644
index 0000000000..2f69f43632
--- /dev/null
+++ b/board/kracko/board.c
@@ -0,0 +1,763 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Kracko board-specific configuration */
+
+#include "adc_chip.h"
+#include "button.h"
+#include "cbi_fw_config.h"
+#include "cbi_ssfc.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "cros_board_info.h"
+#include "driver/accel_bma2x2.h"
+#include "driver/accel_kionix.h"
+#include "driver/accelgyro_lsm6dsm.h"
+#include "driver/bc12/pi3usb9201.h"
+#include "driver/charger/sm5803.h"
+#include "driver/tcpm/it83xx_pd.h"
+#include "driver/tcpm/ps8xxx.h"
+#include "driver/temp_sensor/thermistor.h"
+#include "driver/usb_mux/it5205.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "intc.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "switch.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "tcpm/tcpci.h"
+#include "temp_sensor.h"
+#include "uart.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+
+#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+
+#define INT_RECHECK_US 5000
+
+uint32_t board_version;
+
+/* GPIO to enable/disable the USB Type-A port. */
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_USB_A_5V,
+};
+
+__override void board_process_pd_alert(int port)
+{
+	/*
+	 * PD_INT task will process this alert, and that task is only needed on
+	 * C1.
+	 */
+	if (port != 1)
+		return;
+
+	if (gpio_get_level(GPIO_USB_C1_INT_ODL))
+		return;
+
+	sm5803_handle_interrupt(port);
+}
+
+/* C0 interrupt line shared by BC 1.2 and charger */
+static void check_c0_line(void);
+DECLARE_DEFERRED(check_c0_line);
+
+static void notify_c0_chips(void)
+{
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+	sm5803_interrupt(0);
+}
+
+static void check_c0_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		notify_c0_chips();
+		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+	}
+}
+
+static void usb_c0_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c0_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c0_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+}
+
+/* C1 interrupt line shared by BC 1.2, TCPC, and charger */
+static void check_c1_line(void);
+DECLARE_DEFERRED(check_c1_line);
+
+static void notify_c1_chips(void)
+{
+	schedule_deferred_pd_interrupt(1);
+	usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+}
+
+static void check_c1_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips.
+	 */
+	if (!gpio_get_level(GPIO_USB_C1_INT_ODL)) {
+		notify_c1_chips();
+		hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
+	}
+}
+
+static void usb_c1_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c1_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c1_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
+}
+
+static void button_sub_hdmi_hpd_interrupt(enum gpio_signal s)
+{
+	enum fw_config_db db = get_cbi_fw_config_db();
+	int hdmi_hpd = gpio_get_level(GPIO_VOLUP_BTN_ODL_HDMI_HPD);
+
+	if (db == DB_1A_HDMI || db == DB_LTE_HDMI || db == DB_1A_HDMI_LTE)
+		gpio_set_level(GPIO_EC_AP_USB_C1_HDMI_HPD, hdmi_hpd);
+	else
+		button_interrupt(s);
+}
+
+static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
+{
+	cprints(CC_USBPD, "C0: CC OVP, SBU OVP, or thermal event");
+	pd_handle_cc_overvoltage(0);
+}
+
+static void pen_detect_interrupt(enum gpio_signal s)
+{
+	int pen_detect = !gpio_get_level(GPIO_PEN_DET_ODL);
+
+	gpio_set_level(GPIO_EN_PP5000_PEN, pen_detect);
+}
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	[ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH0 },
+	[ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH2 },
+	[ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH3 },
+	[ADC_SUB_ANALOG] = { .name = "SUB_ANALOG",
+			     .factor_mul = ADC_MAX_MVOLT,
+			     .factor_div = ADC_READ_MAX + 1,
+			     .shift = 0,
+			     .channel = CHIP_ADC_CH13 },
+	[ADC_TEMP_SENSOR_3] = { .name = "TEMP_SENSOR3",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH15 },
+	[ADC_TEMP_SENSOR_4] = { .name = "TEMP_SENSOR4",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH16 },
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* BC 1.2 chips */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	{
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+		.flags = PI3USB9201_ALWAYS_POWERED,
+	},
+	{
+		.i2c_port = I2C_PORT_SUB_USB_C1,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+		.flags = PI3USB9201_ALWAYS_POWERED,
+	},
+};
+
+/* Charger chips */
+const struct charger_config_t chg_chips[] = {
+	[CHARGER_PRIMARY] = {
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = SM5803_ADDR_CHARGER_FLAGS,
+		.drv = &sm5803_drv,
+	},
+	[CHARGER_SECONDARY] = {
+		.i2c_port = I2C_PORT_SUB_USB_C1,
+		.i2c_addr_flags = SM5803_ADDR_CHARGER_FLAGS,
+		.drv = &sm5803_drv,
+	},
+};
+
+/* TCPCs */
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_EMBEDDED,
+		.drv = &it83xx_tcpm_drv,
+	},
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_SUB_USB_C1,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+	},
+};
+
+/* USB Muxes */
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+			},
+	},
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_SUB_USB_C1,
+				.i2c_addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
+	},
+};
+
+/* Sensor Mutexes */
+static struct mutex g_lid_mutex;
+static struct mutex g_base_mutex;
+
+/* Sensor Data */
+static struct accelgyro_saved_data_t g_bma253_data;
+static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
+static struct kionix_accel_data g_kx022_data;
+
+/* Matrix to rotate accelrator into standard reference frame */
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, FLOAT_TO_FP(-1), 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
+
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
+
+static const mat33_fp_t lid_kx022_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					  { 0, FLOAT_TO_FP(1), 0 },
+					  { 0, 0, FLOAT_TO_FP(-1) } };
+
+/* Drivers */
+struct motion_sensor_t kx022_lid_accel = {
+	.name = "Lid Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_KX022,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &kionix_accel_drv,
+		.mutex = &g_lid_mutex,
+		.drv_data = &g_kx022_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
+		.rot_standard_ref = &lid_kx022_ref,
+		.default_range = 2, /* g, enough for laptop. */
+		.min_frequency = KX022_ACCEL_MIN_FREQ,
+		.max_frequency = KX022_ACCEL_MAX_FREQ,
+		.config = {
+			/* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100,
+			},
+			/* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+		},
+};
+
+struct motion_sensor_t motion_sensors[] = {
+	[LID_ACCEL] = {
+		.name = "Lid Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMA255,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &bma2x2_accel_drv,
+		.mutex = &g_lid_mutex,
+		.drv_data = &g_bma253_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
+		.rot_standard_ref = &lid_standard_ref,
+		.default_range = 2,
+		.min_frequency = BMA255_ACCEL_MIN_FREQ,
+		.max_frequency = BMA255_ACCEL_MAX_FREQ,
+		.config = {
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+		},
+	},
+	[BASE_ACCEL] = {
+		.name = "Base Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LSM6DSM,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &lsm6dsm_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
+				MOTIONSENSE_TYPE_ACCEL),
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
+		.rot_standard_ref = &base_standard_ref,
+		.default_range = 4,  /* g */
+		.min_frequency = LSM6DSM_ODR_MIN_VAL,
+		.max_frequency = LSM6DSM_ODR_MAX_VAL,
+		.config = {
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 13000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+		},
+	},
+	[BASE_GYRO] = {
+		.name = "Base Gyro",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LSM6DSM,
+		.type = MOTIONSENSE_TYPE_GYRO,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &lsm6dsm_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
+				MOTIONSENSE_TYPE_GYRO),
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
+		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = LSM6DSM_ODR_MIN_VAL,
+		.max_frequency = LSM6DSM_ODR_MAX_VAL,
+	},
+};
+
+unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+void board_init(void)
+{
+	int on;
+	enum fw_config_db db = get_cbi_fw_config_db();
+
+	if (db == DB_1A_HDMI || db == DB_LTE_HDMI || db == DB_1A_HDMI_LTE) {
+		/* Select HDMI option */
+		gpio_set_level(GPIO_HDMI_SEL_L, 0);
+	} else {
+		/* Select AUX option */
+		gpio_set_level(GPIO_HDMI_SEL_L, 1);
+	}
+
+	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_INT_ODL);
+
+	/* Store board version for use in determining charge limits */
+	cbi_get_board_version(&board_version);
+
+	/*
+	 * If interrupt lines are already low, schedule them to be processed
+	 * after inits are completed.
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL))
+		hook_call_deferred(&check_c0_line_data, 0);
+	if (!gpio_get_level(GPIO_USB_C1_INT_ODL))
+		hook_call_deferred(&check_c1_line_data, 0);
+
+	gpio_enable_interrupt(GPIO_USB_C0_CCSBU_OVP_ODL);
+
+	if (get_cbi_fw_config_tablet_mode() == TABLET_MODE_PRESENT) {
+		motion_sensor_count = ARRAY_SIZE(motion_sensors);
+		/* Second source LID ACCEL */
+		if (get_cbi_ssfc_lid_sensor() == SSFC_SENSOR_KX022) {
+			motion_sensors[LID_ACCEL] = kx022_lid_accel;
+			ccprints("LID ACCEL is KX022");
+		} else
+			ccprints("LID ACCEL is BMA253");
+		/* Enable Base Accel interrupt */
+		gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
+	} else {
+		motion_sensor_count = 0;
+		gmr_tablet_switch_disable();
+		/* Base accel is not stuffed, don't allow line to float */
+		gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L,
+			       GPIO_INPUT | GPIO_PULL_DOWN);
+	}
+
+	gpio_enable_interrupt(GPIO_PEN_DET_ODL);
+
+	/* Make sure pen detection is triggered or not at sysjump */
+	if (!gpio_get_level(GPIO_PEN_DET_ODL))
+		gpio_set_level(GPIO_EN_PP5000_PEN, 1);
+
+	/* Charger on the MB will be outputting PROCHOT_ODL and OD CHG_DET */
+	sm5803_configure_gpio0(CHARGER_PRIMARY, GPIO0_MODE_PROCHOT, 1);
+	sm5803_configure_chg_det_od(CHARGER_PRIMARY, 1);
+
+	if (board_get_charger_chip_count() > 1) {
+		/* Charger on the sub-board will be a push-pull GPIO */
+		sm5803_configure_gpio0(CHARGER_SECONDARY, GPIO0_MODE_OUTPUT, 0);
+	}
+
+	/* Turn on 5V if the system is on, otherwise turn it off */
+	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
+			      CHIPSET_STATE_SOFT_OFF);
+	board_power_5v_enable(on);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+static void board_resume(void)
+{
+	sm5803_disable_low_power_mode(CHARGER_PRIMARY);
+	if (board_get_charger_chip_count() > 1)
+		sm5803_disable_low_power_mode(CHARGER_SECONDARY);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_resume, HOOK_PRIO_DEFAULT);
+
+static void board_suspend(void)
+{
+	sm5803_enable_low_power_mode(CHARGER_PRIMARY);
+	if (board_get_charger_chip_count() > 1)
+		sm5803_enable_low_power_mode(CHARGER_SECONDARY);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_suspend, HOOK_PRIO_DEFAULT);
+
+void board_hibernate(void)
+{
+	/*
+	 * Put all charger ICs present into low power mode before entering
+	 * z-state.
+	 */
+	sm5803_hibernate(CHARGER_PRIMARY);
+	if (board_get_charger_chip_count() > 1)
+		sm5803_hibernate(CHARGER_SECONDARY);
+}
+
+__override void board_ocpc_init(struct ocpc_data *ocpc)
+{
+	/* There's no provision to measure Isys */
+	ocpc->chg_flags[CHARGER_SECONDARY] |= OCPC_NO_ISYS_MEAS_CAP;
+}
+
+__override void board_pulse_entering_rw(void)
+{
+	/*
+	 * On the ITE variants, the EC_ENTERING_RW signal was connected to a pin
+	 * which is active high by default.  This causes Cr50 to think that the
+	 * EC has jumped to its RW image even though this may not be the case.
+	 * The pin is changed to GPIO_EC_ENTERING_RW2.
+	 */
+	gpio_set_level(GPIO_EC_ENTERING_RW, 1);
+	gpio_set_level(GPIO_EC_ENTERING_RW2, 1);
+	usleep(MSEC);
+	gpio_set_level(GPIO_EC_ENTERING_RW, 0);
+	gpio_set_level(GPIO_EC_ENTERING_RW2, 0);
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * Nothing to do.  TCPC C0 is internal, TCPC C1 reset pin is not
+	 * connected to the EC.
+	 */
+}
+
+__override void board_power_5v_enable(int enable)
+{
+	/*
+	 * Motherboard has a GPIO to turn on the 5V regulator, but the sub-board
+	 * sets it through the charger GPIO.
+	 */
+	gpio_set_level(GPIO_EN_PP5000, !!enable);
+
+	if (board_get_charger_chip_count() > 1) {
+		if (sm5803_set_gpio0_level(1, !!enable))
+			CPRINTUSB("Failed to %sable sub rails!",
+				  enable ? "en" : "dis");
+	}
+}
+
+__override uint8_t board_get_usb_pd_port_count(void)
+{
+	enum fw_config_db db = get_cbi_fw_config_db();
+
+	if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI ||
+	    db == DB_1A_HDMI_LTE)
+		return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
+	else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A ||
+		 db == DB_1C_1A_LTE)
+		return CONFIG_USB_PD_PORT_MAX_COUNT;
+
+	ccprints("Unhandled DB configuration: %d", db);
+	return 0;
+}
+
+__override uint8_t board_get_charger_chip_count(void)
+{
+	enum fw_config_db db = get_cbi_fw_config_db();
+
+	if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI ||
+	    db == DB_1A_HDMI_LTE)
+		return CHARGER_NUM - 1;
+	else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A ||
+		 db == DB_1C_1A_LTE)
+		return CHARGER_NUM;
+
+	ccprints("Unhandled DB configuration: %d", db);
+	return 0;
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	/*
+	 * TCPC 0 is embedded in the EC and processes interrupts in the chip
+	 * code (it83xx/intc.c)
+	 */
+
+	uint16_t status = 0;
+	int regval;
+
+	/* Check whether TCPC 1 pulled the shared interrupt line */
+	if (!gpio_get_level(GPIO_USB_C1_INT_ODL)) {
+		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
+			if (regval)
+				status = PD_STATUS_TCPC_ALERT_1;
+		}
+	}
+
+	return status;
+}
+
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
+{
+	/* Limit C1 on board version 0 to 2.0 A */
+	if ((board_version == 0) && (port == 1))
+		charge_ma = MIN(charge_ma, 2000);
+	/*
+	 * TODO(b/151955431): Characterize the input current limit in case a
+	 * scaling needs to be applied here
+	 */
+	charge_set_input_current_limit(charge_ma, charge_mv);
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_valid_port = (port >= 0 && port < board_get_usb_pd_port_count());
+
+	if (!is_valid_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTUSB("Disabling all charge ports");
+
+		sm5803_vbus_sink_enable(CHARGER_PRIMARY, 0);
+
+		if (board_get_charger_chip_count() > 1)
+			sm5803_vbus_sink_enable(CHARGER_SECONDARY, 0);
+
+		return EC_SUCCESS;
+	}
+
+	CPRINTUSB("New chg p%d", port);
+
+	/*
+	 * Ensure other port is turned off, then enable new charge port
+	 */
+	if (port == 0) {
+		if (board_get_charger_chip_count() > 1)
+			sm5803_vbus_sink_enable(CHARGER_SECONDARY, 0);
+		sm5803_vbus_sink_enable(CHARGER_PRIMARY, 1);
+
+	} else {
+		sm5803_vbus_sink_enable(CHARGER_PRIMARY, 0);
+		sm5803_vbus_sink_enable(CHARGER_SECONDARY, 1);
+	}
+
+	return EC_SUCCESS;
+}
+
+/* Vconn control for integrated ITE TCPC */
+void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
+{
+	/* Vconn control is only for port 0 */
+	if (port)
+		return;
+
+	if (cc_pin == USBPD_CC_PIN_1)
+		gpio_set_level(GPIO_EN_USB_C0_CC1_VCONN, !!enabled);
+	else
+		gpio_set_level(GPIO_EN_USB_C0_CC2_VCONN, !!enabled);
+}
+
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	int current;
+
+	if (port < 0 || port > board_get_usb_pd_port_count())
+		return;
+
+	current = (rp == TYPEC_RP_3A0) ? 3000 : 1500;
+
+	charger_set_otg_current_voltage(port, current, 5000);
+}
+
+__override uint16_t board_get_ps8xxx_product_id(int port)
+{
+	/* Kracko variant doesn't have ps8xxx product in the port 0 */
+	if (port == 0)
+		return 0;
+
+	switch (get_cbi_ssfc_tcpc_p1()) {
+	case SSFC_TCPC_P1_PS8805:
+		return PS8805_PRODUCT_ID;
+	case SSFC_TCPC_P1_DEFAULT:
+	case SSFC_TCPC_P1_PS8705:
+	default:
+		return PS8705_PRODUCT_ID;
+	}
+}
+
+/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
+const struct pwm_t pwm_channels[] = { [PWM_CH_KBLIGHT] = {
+					      .channel = 0,
+					      .flags = PWM_CONFIG_DSLEEP,
+					      .freq_hz = 10000,
+				      } };
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+/* Thermistors */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "Charger",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
+	[TEMP_SENSOR_4] = { .name = "5V regular",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_4 },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/* This callback disables keyboard when convertibles are fully open */
+__override void lid_angle_peripheral_enable(int enable)
+{
+	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
+
+	/*
+	 * If the lid is in tablet position via other sensors,
+	 * ignore the lid angle, which might be faulty then
+	 * disable keyboard.
+	 */
+	if (tablet_get_mode())
+		enable = 0;
+
+	if (enable) {
+		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
+	} else {
+		/*
+		 * Ensure that the chipset is off before disabling the keyboard.
+		 * When the chipset is on, the EC keeps the keyboard enabled and
+		 * the AP decides whether to ignore input devices or not.
+		 */
+		if (!chipset_in_s0)
+			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
+	}
+}
+
+__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+				       int *ki_div, int *kd, int *kd_div)
+{
+	*kp = 3;
+	*kp_div = 20;
+
+	*ki = 3;
+	*ki_div = 125;
+
+	*kd = 4;
+	*kd_div = 40;
+}
+
+#ifdef CONFIG_KEYBOARD_FACTORY_TEST
+/*
+ * Map keyboard connector pins to EC GPIO pins for factory test.
+ * Pins mapped to {-1, -1} are skipped.
+ * The connector has 24 pins total, and there is no pin 0.
+ */
+const int keyboard_factory_scan_pins[][2] = {
+	{ -1, -1 },	   { GPIO_KSO_H, 4 }, { GPIO_KSO_H, 0 },
+	{ GPIO_KSO_H, 1 }, { GPIO_KSO_H, 3 }, { GPIO_KSO_H, 2 },
+	{ GPIO_KSO_L, 5 }, { GPIO_KSO_L, 6 }, { GPIO_KSO_L, 3 },
+	{ GPIO_KSO_L, 2 }, { GPIO_KSI, 0 },   { GPIO_KSO_L, 1 },
+	{ GPIO_KSO_L, 4 }, { GPIO_KSI, 3 },   { GPIO_KSI, 2 },
+	{ GPIO_KSO_L, 0 }, { GPIO_KSI, 5 },   { GPIO_KSI, 4 },
+	{ GPIO_KSO_L, 7 }, { GPIO_KSI, 6 },   { GPIO_KSI, 7 },
+	{ GPIO_KSI, 1 },   { -1, -1 },	      { -1, -1 },
+	{ -1, -1 },
+};
+
+const int keyboard_factory_scan_pins_used =
+	ARRAY_SIZE(keyboard_factory_scan_pins);
+#endif
diff --git a/board/kracko/board.h b/board/kracko/board.h
new file mode 100644
index 0000000000..387680203c
--- /dev/null
+++ b/board/kracko/board.h
@@ -0,0 +1,148 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Kracko board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* Select Baseboard features */
+#define VARIANT_DEDEDE_EC_IT8320
+#include "baseboard.h"
+
+#undef GPIO_VOLUME_UP_L
+#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL_HDMI_HPD
+
+/* Battery */
+#define CONFIG_BATTERY_FUEL_GAUGE
+
+/* BC 1.2 */
+#define CONFIG_BC12_DETECT_PI3USB9201
+
+/* Charger */
+#define CONFIG_CHARGE_RAMP_HW
+#define CONFIG_CHARGER_SM5803 /* C0 and C1: Charger */
+#define PD_MAX_VOLTAGE_MV 15000
+#define CONFIG_USB_PD_VBUS_DETECT_CHARGER
+#define CONFIG_USB_PD_5V_CHARGER_CTRL
+#define CONFIG_CHARGER_OTG
+#undef CONFIG_CHARGER_SINGLE_CHIP
+#define CONFIG_OCPC
+#define CONFIG_OCPC_DEF_RBATT_MOHMS               \
+	21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr \
+	    */
+
+/* PWM */
+#define CONFIG_PWM
+
+/* LED defines */
+#define CONFIG_LED_ONOFF_STATES
+
+/* Sensors */
+#define CONFIG_ACCEL_BMA255 /* Lid accel */
+#define CONFIG_ACCEL_KX022 /* Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
+/* Sensors without hardware FIFO are in forced mode */
+#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
+
+#define CONFIG_CMD_ACCELS
+#define CONFIG_CMD_ACCEL_INFO
+
+/* Enable sensor fifo, must also define the _SIZE and _THRES */
+#define CONFIG_ACCEL_FIFO
+/* Power of 2 - Too large of a fifo causes too much timestamp jitter */
+#define CONFIG_ACCEL_FIFO_SIZE 256
+#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
+
+#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
+
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_UPDATE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+
+#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+#define CONFIG_TABLET_MODE
+#define CONFIG_TABLET_MODE_SWITCH
+#define CONFIG_GMR_TABLET_MODE
+
+/* Keyboard */
+#define CONFIG_KEYBOARD_FACTORY_TEST
+#define CONFIG_PWM_KBLIGHT
+
+/* TCPC */
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0: ITE EC TCPC */
+#define CONFIG_USB_PD_TCPM_MULTI_PS8XXX
+#define CONFIG_USB_PD_TCPM_PS8705 /* C1: PS8705 TCPC */
+#define CONFIG_USB_PD_TCPM_PS8805 /* C1: second source PS8805 TCPC */
+#define CONFIG_USB_PD_TCPM_PS8805_FORCE_DID
+#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1
+#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+#define CONFIG_USB_PD_TCPC_LOW_POWER
+
+/* Thermistors */
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_THERMISTOR
+#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
+
+/* USB Mux and Retimer */
+#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */
+
+/* USB Type A Features */
+#define USB_PORT_COUNT 1
+#define CONFIG_USB_PORT_POWER_DUMB
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum chg_id {
+	CHARGER_PRIMARY,
+	CHARGER_SECONDARY,
+	CHARGER_NUM,
+};
+
+enum pwm_channel {
+	PWM_CH_KBLIGHT,
+	PWM_CH_COUNT,
+};
+
+/* Motion sensors */
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
+
+/* ADC channels */
+enum adc_channel {
+	ADC_VSNS_PP3300_A, /* ADC0 */
+	ADC_TEMP_SENSOR_1, /* ADC2 */
+	ADC_TEMP_SENSOR_2, /* ADC3 */
+	ADC_SUB_ANALOG, /* ADC13 */
+	ADC_TEMP_SENSOR_3, /* ADC15 */
+	ADC_TEMP_SENSOR_4, /* ADC16 */
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1,
+	TEMP_SENSOR_2,
+	TEMP_SENSOR_3,
+	TEMP_SENSOR_4,
+	TEMP_SENSOR_COUNT
+};
+
+/* List of possible batteries */
+enum battery_type {
+	BATTERY_SIMPLO,
+	BATTERY_COS,
+	BATTERY_TYPE_COUNT,
+};
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/kracko/build.mk b/board/kracko/build.mk
new file mode 100644
index 0000000000..01b890bf29
--- /dev/null
+++ b/board/kracko/build.mk
@@ -0,0 +1,15 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=it83xx
+CHIP_FAMILY:=it8320
+CHIP_VARIANT:=it8320dx
+BASEBOARD:=dedede
+
+board-y=board.o cbi_ssfc.o led.o usb_pd_policy.o
+board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/kracko/cbi_ssfc.c b/board/kracko/cbi_ssfc.c
new file mode 100644
index 0000000000..324ceffb63
--- /dev/null
+++ b/board/kracko/cbi_ssfc.c
@@ -0,0 +1,41 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi_ssfc.h"
+#include "common.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "hooks.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+/* Cache SSFC on init since we don't expect it to change in runtime */
+static union dedede_cbi_ssfc cached_ssfc;
+BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
+
+static void cbi_ssfc_init(void)
+{
+	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
+		/* Default to 0 when CBI isn't populated */
+		cached_ssfc.raw_value = 0;
+
+	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
+}
+DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
+
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
+{
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
+}
+
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
+{
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
+}
+
+enum ec_ssfc_tcpc_p1 get_cbi_ssfc_tcpc_p1(void)
+{
+	return (enum ec_ssfc_tcpc_p1)cached_ssfc.tcpc_type;
+}
diff --git a/board/kracko/cbi_ssfc.h b/board/kracko/cbi_ssfc.h
new file mode 100644
index 0000000000..ad35b1a139
--- /dev/null
+++ b/board/kracko/cbi_ssfc.h
@@ -0,0 +1,86 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _DEDEDE_CBI_SSFC__H_
+#define _DEDEDE_CBI_SSFC__H_
+
+#include "stdint.h"
+
+/****************************************************************************
+ * Dedede CBI Second Source Factory Cache
+ */
+
+/*
+ * Base Sensor (Bits 0-2)
+ */
+enum ec_ssfc_base_sensor {
+	SSFC_SENSOR_BASE_DEFAULT = 0,
+	SSFC_SENSOR_BMI160 = 1,
+	SSFC_SENSOR_ICM426XX = 2,
+	SSFC_SENSOR_LSM6DSM = 3,
+	SSFC_SENSOR_ICM42607 = 4
+};
+
+/*
+ * Lid Sensor (Bits 3-5)
+ */
+enum ec_ssfc_lid_sensor {
+	SSFC_SENSOR_LID_DEFAULT = 0,
+	SSFC_SENSOR_BMA255 = 1,
+	SSFC_SENSOR_KX022 = 2,
+	SSFC_SENSOR_LIS2DWL = 3
+};
+
+/*
+ * TCPC Port 1 (Bits 6-7)
+ */
+enum ec_ssfc_tcpc_p1 {
+	SSFC_TCPC_P1_DEFAULT,
+	SSFC_TCPC_P1_PS8705,
+	SSFC_TCPC_P1_PS8805,
+};
+
+/*
+ * Audio Codec Source(Bit 8-10)
+ */
+enum ec_ssfc_audio_codec_source {
+	SSFC_AUDIO_CODEC_DEFAULT = 0,
+	SSFC_AUDIO_CODEC_VD = 1,
+	SSFC_ADUIO_CODEC_VS = 2,
+};
+
+union dedede_cbi_ssfc {
+	struct {
+		uint32_t base_sensor : 3;
+		uint32_t lid_sensor : 3;
+		uint32_t tcpc_type : 2;
+		uint32_t audio_codec_source : 3;
+		uint32_t reserved_2 : 21;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Get the Base sensor type from SSFC_CONFIG.
+ *
+ * @return the Base sensor board type.
+ */
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
+
+/**
+ * Get the Lid sensor type from SSFC_CONFIG.
+ *
+ * @return the Lid sensor board type.
+ */
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
+
+/**
+ * Get the TCPC port 1 type from SSFC_CONFIG.
+ *
+ * @return the TCPC type.
+ */
+enum ec_ssfc_tcpc_p1 get_cbi_ssfc_tcpc_p1(void);
+
+#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/kracko/ec.tasklist b/board/kracko/ec.tasklist
new file mode 100644
index 0000000000..c13df44543
--- /dev/null
+++ b/board/kracko/ec.tasklist
@@ -0,0 +1,24 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, TRENTA_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, ULTRA_TASK_STACK_SIZE) \
+        TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+        TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+        TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/kracko/gpio.inc b/board/kracko/gpio.inc
new file mode 100644
index 0000000000..a138a925f3
--- /dev/null
+++ b/board/kracko/gpio.inc
@@ -0,0 +1,148 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+/* Power State interrupts */
+GPIO_INT(SLP_S4_L,		PIN(I, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,		PIN(H, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(SLP_S0_L,		PIN(E, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,		PIN(G, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID0,	PIN(D, 0), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(RSMRST_PWRGD_L,	PIN(E, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(CPU_C10_GATE_L,	PIN(G, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_DRAM_OD,		PIN(D, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(PG_PP1050_ST_OD,	PIN(L, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID1,	PIN(K, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_VCCIO_EXT_OD,	PIN(D, 7), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(ESPI_RESET_L, 	 PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt)
+
+GPIO_INT(H1_EC_PWR_BTN_ODL,	PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
+#ifdef CONFIG_LOW_POWER_IDLE
+/* Used to wake up the EC from Deep Doze mode when writing to console */
+GPIO_INT(UART1_RX,	 PIN(B, 0), GPIO_INT_BOTH, uart_deepsleep_interrupt)	/* UART_DBG_TX_EC_RX */
+#endif
+
+/* USB-C interrupts */
+GPIO_INT(USB_C0_INT_ODL,	PIN(K, 0), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt) /* BC12 and charger */
+GPIO_INT(USB_C1_INT_ODL,	PIN(E, 6), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c1_interrupt) /* TCPC, charger, BC12 */
+GPIO_INT(USB_C0_CCSBU_OVP_ODL,	PIN(K, 6), GPIO_INT_FALLING | GPIO_PULL_UP, c0_ccsbu_ovp_interrupt) /* Fault protection */
+
+/* Other interrupts */
+GPIO_INT(LID_OPEN,		PIN(F, 3), GPIO_INT_BOTH, lid_interrupt)
+GPIO_INT(LID_360_L,		PIN(A, 7), GPIO_INT_BOTH, gmr_tablet_switch_isr)
+GPIO_INT(VOLDN_BTN_ODL,		PIN(I, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(VOLUP_BTN_ODL_HDMI_HPD,	PIN(I, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_sub_hdmi_hpd_interrupt)
+GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(J, 0), GPIO_INT_FALLING | GPIO_SEL_1P8V, lsm6dsm_interrupt)
+GPIO_INT(EC_WP_OD,		PIN(A, 6), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(PEN_DET_ODL,		PIN(J, 1), GPIO_INT_BOTH | GPIO_PULL_UP, pen_detect_interrupt)
+
+/* Power sequence GPIOs */
+GPIO(EC_AP_RTCRST,		PIN(K, 2), GPIO_OUT_LOW)
+GPIO(EC_AP_PWR_BTN_ODL,		PIN(B, 6), GPIO_ODR_HIGH)
+GPIO(EC_AP_DPWROK,		PIN(L, 7), GPIO_OUT_LOW)
+GPIO(EC_AP_RSMRST_L,		PIN(H, 0), GPIO_OUT_LOW)
+GPIO(EC_AP_WAKE_ODL,		PIN(D, 5), GPIO_ODR_HIGH)
+GPIO(SYS_RST_ODL,		PIN(D, 1), GPIO_ODR_HIGH)
+GPIO(EC_AP_SYS_PWROK,		PIN(F, 2), GPIO_OUT_LOW)
+GPIO(PG_PP5000_U_OD,		PIN(E, 3), GPIO_INPUT)
+GPIO(EN_PP3300_A,		PIN(C, 5), GPIO_OUT_LOW)
+GPIO(EC_AP_PCH_PWROK_OD,	PIN(D, 6), GPIO_ODR_LOW)
+GPIO(EN_PP5000_U,		PIN(K, 5), GPIO_OUT_LOW)
+/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
+GPIO(EN_VCCST,			PIN(D, 4), GPIO_INPUT)
+GPIO(EN_VCCIO_EXT,		PIN(B, 2), GPIO_OUT_LOW)
+GPIO(EC_PROCHOT_ODL,		PIN(I, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(EC_AP_VCCST_PWRGD_OD,	PIN(E, 5), GPIO_ODR_LOW)
+GPIO(ALL_SYS_PWRGD,		PIN(B, 7), GPIO_OUT_LOW)
+GPIO(EN_SLP_Z,			PIN(K, 3), GPIO_OUT_LOW)
+
+/* Required for icelake chipset code, but implemented through other means for dedede */
+UNIMPLEMENTED(AC_PRESENT)
+UNIMPLEMENTED(PG_EC_DSW_PWROK)
+UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
+
+/* I2C pins - Alternate function below configures I2C module on these pins */
+GPIO(EC_I2C_EEPROM_SCL,		PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SDA,		PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SCL,	PIN(C, 1), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SDA,	PIN(C, 2), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,		PIN(F, 6), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SENSOR_SDA,		PIN(F, 7), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SUB_USB_C1_SCL,	PIN(E, 0), GPIO_INPUT)
+GPIO(EC_I2C_SUB_USB_C1_SDA,	PIN(E, 7), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SCL,		PIN(A, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SDA,		PIN(A, 5), GPIO_INPUT)
+
+/* USB pins */
+GPIO(EN_USB_A_5V,			PIN(L, 6), GPIO_OUT_LOW)
+GPIO(EN_USB_C0_CC1_VCONN,	PIN(H, 4), GPIO_OUT_LOW)
+GPIO(EN_USB_C0_CC2_VCONN,	PIN(H, 6), GPIO_OUT_LOW)
+GPIO(EC_AP_USB_C0_HPD,		PIN(L, 4), GPIO_OUT_LOW)
+GPIO(EC_AP_USB_C1_HDMI_HPD,	PIN(K, 7), GPIO_OUT_LOW)
+GPIO(USB_C0_FRS,		PIN(C, 4), GPIO_OUT_LOW)
+GPIO(HDMI_SEL_L,		PIN(C, 6), GPIO_OUT_HIGH)
+
+/* MKBP event synchronization */
+GPIO(EC_AP_MKBP_INT_L,	PIN(L, 5), GPIO_ODR_HIGH)
+
+/* Misc pins which will run to the I/O board */
+GPIO(EC_SUB_IO_1_2, PIN(F, 0), GPIO_INPUT)
+GPIO(EC_SUB_IO_2_1, PIN(F, 1), GPIO_INPUT)
+
+/* Misc */
+GPIO(EN_BL_OD,			PIN(K, 4), GPIO_ODR_LOW)
+GPIO(EC_ENTERING_RW,		PIN(G, 0), GPIO_OUT_LOW)
+GPIO(EC_ENTERING_RW2,		PIN(C, 7), GPIO_OUT_LOW)
+GPIO(CCD_MODE_ODL,		PIN(H, 5), GPIO_ODR_HIGH)
+GPIO(EC_BATTERY_PRES_ODL,	PIN(I, 4), GPIO_INPUT)
+GPIO(EN_KB_BL,			PIN(J, 3), GPIO_OUT_LOW) /* Currently unused */
+GPIO(ECH1_PACKET_MODE,		PIN(H, 1), GPIO_OUT_LOW)
+GPIO(EN_PP5000_PEN,		PIN(B, 5), GPIO_OUT_LOW)
+
+/* NC pins, enable internal pull-down to avoid floating state. */
+GPIO(GPIOA3_NC,	PIN(A, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOC3_NC, PIN(C, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG3_NC, PIN(G, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG4_NC, PIN(G, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG5_NC, PIN(G, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG6_NC, PIN(G, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG7_NC, PIN(G, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ4_NC, PIN(J, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ5_NC, PIN(J, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ6_NC, PIN(J, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOM6_NC, PIN(M, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+
+/* LED */
+GPIO(BAT_LED_ORANGE_L,	 PIN(A, 1), GPIO_OUT_HIGH)	/* LED_1_L */
+GPIO(BAT_LED_BLUE_L,	 PIN(A, 2), GPIO_OUT_HIGH)	/* LED_2_L */
+
+/* Alternate functions GPIO definitions */
+/* Keyboard */
+ALTERNATE(PIN_MASK(KSI,   0xFF), 0, MODULE_KEYBOARD_SCAN, 0)		/* KSI0-7 */
+ALTERNATE(PIN_MASK(KSO_H, 0xFF), 0, MODULE_KEYBOARD_SCAN, 0)		/* KSO8-15 */
+ALTERNATE(PIN_MASK(KSO_L, 0xFB), 0, MODULE_KEYBOARD_SCAN, 0)		/* KSO0-1, 3-7 */
+GPIO(EC_KSO_02_INV, PIN(KSO_L, 2), GPIO_OUT_HIGH)			/* KSO2 inverted */
+
+/* UART */
+ALTERNATE(PIN_MASK(B, BIT(0) | BIT(1)), 0, MODULE_UART, 0)		/* UART for debug */
+
+/* I2C */
+ALTERNATE(PIN_MASK(B, BIT(3) | BIT(4)), 0, MODULE_I2C, 0)		/* I2C0 */
+ALTERNATE(PIN_MASK(C, BIT(1) | BIT(2)), 0, MODULE_I2C, 0)		/* I2C1 */
+ALTERNATE(PIN_MASK(F, BIT(6) | BIT(7)), 0, MODULE_I2C, GPIO_SEL_1P8V)	/* I2C2 - 1.8V */
+ALTERNATE(PIN_MASK(E, BIT(0) | BIT(7)), 0, MODULE_I2C, 0)		/* I2C4 */
+ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), 0, MODULE_I2C, 0)		/* I2C5 */
+
+/* ADC */
+ALTERNATE(PIN_MASK(L, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0)	/* ADC13: EC_SUB_ANALOG, ADC15: TEMP_SENSOR_3, ADC16: TEMP_SENSOR_4 */
+ALTERNATE(PIN_MASK(I, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0)	/* ADC0: EC_VSNS_PP3300_A, ADC2: TEMP_SENSOR_1, ADC3: TEMP_SENSOR_2 */
+
+/* PWM */
+ALTERNATE(PIN_MASK(A, BIT(0)), 0, MODULE_PWM, 0) 			/* KB_BL_PWM */
diff --git a/board/kracko/led.c b/board/kracko/led.c
new file mode 100644
index 0000000000..22a906807b
--- /dev/null
+++ b/board/kracko/led.c
@@ -0,0 +1,79 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Power and battery LED control for Kracko. */
+
+#include "ec_commands.h"
+#include "gpio.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
+
+__override const int led_charge_lvl_1;
+
+__override const int led_charge_lvl_2 = 100;
+
+/* Kracko: Note there is only LED for charge / power */
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_BLUE:
+		gpio_set_level(GPIO_BAT_LED_BLUE_L, LED_ON_LVL);
+		gpio_set_level(GPIO_BAT_LED_ORANGE_L, LED_OFF_LVL);
+		break;
+	case EC_LED_COLOR_AMBER:
+		gpio_set_level(GPIO_BAT_LED_BLUE_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_BAT_LED_ORANGE_L, LED_ON_LVL);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		gpio_set_level(GPIO_BAT_LED_BLUE_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_BAT_LED_ORANGE_L, LED_OFF_LVL);
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	brightness_range[EC_LED_COLOR_BLUE] = 1;
+	brightness_range[EC_LED_COLOR_AMBER] = 1;
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (brightness[EC_LED_COLOR_BLUE] != 0)
+		led_set_color_battery(EC_LED_COLOR_BLUE);
+	else if (brightness[EC_LED_COLOR_AMBER] != 0)
+		led_set_color_battery(EC_LED_COLOR_AMBER);
+	else
+		led_set_color_battery(LED_OFF);
+
+	return EC_SUCCESS;
+}
diff --git a/board/kracko/usb_pd_policy.c b/board/kracko/usb_pd_policy.c
new file mode 100644
index 0000000000..8a2c07c575
--- /dev/null
+++ b/board/kracko/usb_pd_policy.c
@@ -0,0 +1,74 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery_smart.h"
+#include "charge_manager.h"
+#include "charger.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "driver/charger/sm5803.h"
+#include "driver/tcpm/tcpci.h"
+#include "usb_pd.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+int pd_check_vconn_swap(int port)
+{
+	/* Allow VCONN swaps if the AP is on */
+	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
+}
+
+void pd_power_supply_reset(int port)
+{
+	int prev_en;
+
+	if (port < 0 || port >= board_get_usb_pd_port_count())
+		return;
+
+	prev_en = charger_is_sourcing_otg_power(port);
+
+	/* Disable Vbus */
+	charger_enable_otg_power(port, 0);
+
+	/* Discharge Vbus if previously enabled */
+	if (prev_en)
+		sm5803_set_vbus_disch(port, 1);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	enum ec_error_list rv;
+
+	/* Disable sinking */
+	rv = sm5803_vbus_sink_enable(port, 0);
+	if (rv)
+		return rv;
+
+	/* Disable Vbus discharge */
+	sm5803_set_vbus_disch(port, 0);
+
+	/* Provide Vbus */
+	charger_enable_otg_power(port, 1);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+__override bool pd_check_vbus_level(int port, enum vbus_level level)
+{
+	return sm5803_check_vbus_level(port, level);
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	return sm5803_is_vbus_present(port);
+}
diff --git a/board/kracko/vif_override.xml b/board/kracko/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/kracko/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/kukui/board.c b/board/kukui/board.c
index 0f6107ceaa..c76768f7d8 100644
--- a/board/kukui/board.c
+++ b/board/kukui/board.c
@@ -1,10 +1,9 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "button.h"
 #include "charge_manager.h"
 #include "charge_ramp.h"
@@ -28,6 +27,7 @@
 #include "host_command.h"
 #include "i2c.h"
 #include "lid_switch.h"
+#include "panic.h"
 #include "power.h"
 #include "power_button.h"
 #include "pwm.h"
@@ -36,7 +36,7 @@
 #include "spi.h"
 #include "system.h"
 #include "task.h"
-#include "tcpm.h"
+#include "tcpm/tcpm.h"
 #include "timer.h"
 #include "usb_charge.h"
 #include "usb_mux.h"
@@ -44,8 +44,8 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
@@ -57,23 +57,37 @@ static void gauge_interrupt(enum gpio_signal signal)
 	task_wake(TASK_ID_CHARGER);
 }
 
+#ifdef SECTION_IS_RW
+static void motion_interrupt(enum gpio_signal signal);
+#endif /* SECTION_IS_RW */
+
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /******************************************************************************/
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] = {"BOARD_ID", 3300, 4096, 0, STM32_AIN(10)},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)},
-	[ADC_BATT_ID] = {"BATT_ID", 3300, 4096, 0, STM32_AIN(7)},
-	[ADC_POGO_ADC_INT_L] = {"POGO_ADC_INT_L", 3300, 4096, 0, STM32_AIN(6)},
+	[ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(10) },
+	[ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8) },
+	[ADC_BATT_ID] = { "BATT_ID", 3300, 4096, 0, STM32_AIN(7) },
+	[ADC_POGO_ADC_INT_L] = { "POGO_ADC_INT_L", 3300, 4096, 0,
+				 STM32_AIN(6) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /******************************************************************************/
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{"typec", 0, 400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"other", 1, 400, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
+	{ .name = "typec",
+	  .port = 0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "other",
+	  .port = 1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -81,15 +95,14 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
 /* power signal list.  Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
+	{ GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" },
+	{ GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" },
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
 /******************************************************************************/
 /* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
+const struct spi_device_t spi_devices[] = {};
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
 /******************************************************************************/
@@ -119,9 +132,12 @@ void board_set_dp_mux_control(int output_enable, int polarity)
 		gpio_set_level(GPIO_USB_C0_DP_POLARITY, polarity);
 }
 
-static void board_hpd_update(const struct usb_mux *me,
-			     int hpd_lvl, int hpd_irq)
+static void board_hpd_update(const struct usb_mux *me, mux_state_t mux_state,
+			     bool *ack_required)
 {
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
 	/*
 	 * svdm_dp_attention() did most of the work, we only need to notify
 	 * host here.
@@ -143,13 +159,17 @@ __override const struct rt946x_init_setting *board_rt946x_init_setting(void)
 	return &battery_init_setting;
 }
 
-struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+struct usb_mux usbc0_mux0 = {
+	.usb_port = 0,
+	.i2c_port = I2C_PORT_USB_MUX,
+	.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+	.driver = &it5205_usb_mux_driver,
+	.hpd_update = &board_hpd_update,
+};
+
+struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_update,
+		.mux = &usbc0_mux0,
 	},
 };
 
@@ -187,7 +207,7 @@ int board_set_active_charge_port(int charge_port)
 		gpio_set_level(GPIO_EN_POGO_CHARGE_L, 0);
 		break;
 #endif
-	case CHARGE_PORT_NONE:
+	default:
 		/*
 		 * To ensure the fuel gauge (max17055) is always powered
 		 * even when battery is disconnected, keep VBAT rail on but
@@ -197,9 +217,6 @@ int board_set_active_charge_port(int charge_port)
 		gpio_set_level(GPIO_EN_USBC_CHARGE_L, 1);
 		charger_set_current(CHARGER_SOLO, 0);
 		break;
-	default:
-		panic("Invalid charge port\n");
-		break;
 	}
 
 	return EC_SUCCESS;
@@ -247,9 +264,8 @@ int extpower_is_present(void)
 	if (board_vbus_source_enabled(CHARGE_PORT_USB_C))
 		usb_c_extpower_present = 0;
 	else
-		usb_c_extpower_present = tcpm_check_vbus_level(
-							CHARGE_PORT_USB_C,
-							VBUS_PRESENT);
+		usb_c_extpower_present =
+			tcpm_check_vbus_level(CHARGE_PORT_USB_C, VBUS_PRESENT);
 
 	return usb_c_extpower_present || kukui_pogo_extpower_present();
 }
@@ -338,15 +354,15 @@ static void board_rev_init(void)
 		/* configure PI3USB9201 to USB Path ON Mode */
 		i2c_write8(I2C_PORT_BC12, BC12_I2C_ADDR_FLAGS,
 			   PI3USB9201_REG_CTRL_1,
-			   (PI3USB9201_USB_PATH_ON <<
-			    PI3USB9201_REG_CTRL_1_MODE_SHIFT));
+			   (PI3USB9201_USB_PATH_ON
+			    << PI3USB9201_REG_CTRL_1_MODE_SHIFT));
 	}
 
 	if (board_get_version() < 5) {
 		gpio_set_flags(GPIO_USB_C0_DP_OE_L, GPIO_OUT_HIGH);
 		gpio_set_flags(GPIO_USB_C0_DP_POLARITY, GPIO_OUT_LOW);
-		usb_muxes[0].driver = &virtual_usb_mux_driver;
-		usb_muxes[0].hpd_update = &virtual_hpd_update;
+		usbc0_mux0.driver = &virtual_usb_mux_driver;
+		usbc0_mux0.hpd_update = &virtual_hpd_update;
 	}
 }
 DECLARE_HOOK(HOOK_INIT, board_rev_init, HOOK_PRIO_INIT_ADC + 1);
@@ -419,26 +435,20 @@ static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
 
 /* Matrix to rotate accelerometer into standard reference frame */
 #ifdef BOARD_KUKUI
-static const mat33_fp_t lid_standard_ref = {
-	{FLOAT_TO_FP(1), 0, 0},
-	{0, FLOAT_TO_FP(1), 0},
-	{0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(1), 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
 #else
-static const mat33_fp_t lid_standard_ref = {
-	{FLOAT_TO_FP(-1), 0, 0},
-	{0, FLOAT_TO_FP(-1), 0},
-	{0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
 #endif /* BOARD_KUKUI */
 
 #ifdef CONFIG_MAG_BMI_BMM150
 /* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t mag_standard_ref = {
-	{0, FLOAT_TO_FP(-1), 0},
-	{FLOAT_TO_FP(-1), 0, 0},
-	{0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t mag_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+					     { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 #endif /* CONFIG_MAG_BMI_BMM150 */
 
 struct motion_sensor_t motion_sensors[] = {
@@ -506,7 +516,10 @@ struct motion_sensor_t motion_sensors[] = {
 	 .default_range = BIT(11), /* 16LSB / uT, fixed */
 	 .rot_standard_ref = &mag_standard_ref,
 	 .min_frequency = BMM150_MAG_MIN_FREQ,
+/* TODO(b/253292373): Remove when clang is fixed. */
+DISABLE_CLANG_WARNING("-Wshift-count-negative")
 	 .max_frequency = BMM150_MAG_MAX_FREQ(SPECIAL),
+ENABLE_CLANG_WARNING("-Wshift-count-negative")
 	},
 #endif /* CONFIG_MAG_BMI_BMM150 */
 	[CLEAR_ALS] = {
@@ -560,8 +573,62 @@ const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 const struct motion_sensor_t *motion_als_sensors[] = {
 	&motion_sensors[CLEAR_ALS],
 };
+
+#ifdef BOARD_KRANE
+
+static bool is_bmi220_present;
+
+static void board_detect_bmi220(void)
+{
+	int id = -1;
+	struct motion_sensor_t *s;
+
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return;
+
+	/* Detect accelgyro chip */
+	bmi_read8(I2C_PORT_ACCEL, BMI260_ADDR0_FLAGS, BMI260_CHIP_ID, &id);
+	if (id == BMI220_CHIP_ID_MAJOR) {
+		is_bmi220_present = true;
+		/* Lid Accel*/
+		s = &motion_sensors[LID_ACCEL];
+		s->chip = MOTIONSENSE_CHIP_BMI220;
+		s->drv = &bmi260_drv;
+		s->i2c_spi_addr_flags = BMI260_ADDR0_FLAGS;
+		/* Lid Gyro */
+		s = &motion_sensors[LID_GYRO];
+		s->chip = MOTIONSENSE_CHIP_BMI220;
+		s->drv = &bmi260_drv;
+		s->i2c_spi_addr_flags = BMI260_ADDR0_FLAGS;
+#ifdef CONFIG_MAG_BMI_BMM150
+		/* Lid Mag */
+		s = &motion_sensors[LID_MAG];
+		s->chip = MOTIONSENSE_CHIP_BMI220;
+		s->drv = &bmi260_drv;
+		s->i2c_spi_addr_flags = BMI260_ADDR0_FLAGS;
+#endif /* CONFIG_MAG_BMI_BMM150 */
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_detect_bmi220, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_INIT, board_detect_bmi220, HOOK_PRIO_DEFAULT + 1);
+#endif /* BOARD_KRANE */
+
 #endif /* VARIANT_KUKUI_NO_SENSORS */
 
+#ifdef SECTION_IS_RW
+static void motion_interrupt(enum gpio_signal signal)
+{
+#if defined(BOARD_KRANE)
+	if (is_bmi220_present)
+		bmi260_interrupt(signal);
+	else
+		bmi160_interrupt(signal);
+#elif !defined(VARIANT_KUKUI_NO_SENSORS)
+	bmi160_interrupt(signal);
+#endif /* BOARD_KRANE, !VARIANT_KUKUI_NO_SENSORS */
+}
+#endif /* SECTION_IS_RW */
+
 /*
  * Return if VBUS is sagging too low
  */
@@ -595,9 +662,8 @@ __override int board_charge_port_is_connected(int port)
 	return gpio_get_level(GPIO_POGO_VBUS_PRESENT);
 }
 
-__override
-void board_fill_source_power_info(int port,
-				  struct ec_response_usb_pd_power_info *r)
+__override void
+board_fill_source_power_info(int port, struct ec_response_usb_pd_power_info *r)
 {
 	r->meas.voltage_now = 3300;
 	r->meas.voltage_max = 3300;
diff --git a/board/kukui/board.h b/board/kukui/board.h
index 3320a53472..94c05a1209 100644
--- a/board/kukui/board.h
+++ b/board/kukui/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,6 +16,7 @@
 #endif
 
 #define VARIANT_KUKUI_CHARGER_MT6370
+#define VARIANT_KUKUI_EC_STM32F098
 #define VARIANT_KUKUI_DP_MUX_GPIO
 #define VARIANT_KUKUI_TABLET_PWRBTN
 
@@ -30,11 +31,15 @@
 #define CONFIG_VOLUME_BUTTONS
 #define CONFIG_USB_MUX_RUNTIME_CONFIG
 
+#ifdef SECTION_IS_RO
+#define CONFIG_CMD_PD_SRCCAPS_REDUCED_SIZE
+#endif /* SECTION_IS_RO */
+
 /* Battery */
 #ifdef BOARD_KRANE
-#define BATTERY_DESIRED_CHARGING_CURRENT    3500  /* mA */
+#define BATTERY_DESIRED_CHARGING_CURRENT 3500 /* mA */
 #else
-#define BATTERY_DESIRED_CHARGING_CURRENT    2000  /* mA */
+#define BATTERY_DESIRED_CHARGING_CURRENT 2000 /* mA */
 #endif /* BOARD_KRANE */
 
 #ifdef BOARD_KRANE
@@ -54,9 +59,14 @@
 #define CONFIG_MAG_CALIBRATE
 #endif /* !BOARD_KRANE */
 #define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCEL_INTERRUPTS
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
+#ifdef BOARD_KRANE
+#define CONFIG_I2C_XFER_LARGE_TRANSFER
+#define CONFIG_ACCELGYRO_BMI220
+#define CONFIG_ACCELGYRO_BMI260_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
+#endif /* BOARD_KRANE */
 #define CONFIG_ALS
 
 #define ALS_COUNT 1
@@ -69,30 +79,24 @@
 /* Camera VSYNC */
 #define CONFIG_SYNC
 #define CONFIG_SYNC_COMMAND
-#define CONFIG_SYNC_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
+#define CONFIG_SYNC_INT_EVENT TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
 #endif /* SECTION_IS_RW */
 
 /* I2C ports */
-#define I2C_PORT_CHARGER  0
-#define I2C_PORT_TCPC0    0
-#define I2C_PORT_USB_MUX  0
-#define I2C_PORT_BATTERY  1
+#define I2C_PORT_CHARGER 0
+#define I2C_PORT_TCPC0 0
+#define I2C_PORT_USB_MUX 0
+#define I2C_PORT_BATTERY 1
 #define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
-#define I2C_PORT_ACCEL    1
-#define I2C_PORT_BC12     1
-#define I2C_PORT_ALS      1
+#define I2C_PORT_ACCEL 1
+#define I2C_PORT_BC12 1
+#define I2C_PORT_ALS 1
 
 /* Route sbs host requests to virtual battery driver */
 #define VIRTUAL_BATTERY_ADDR_FLAGS 0x0B
 
-/* Define the host events which are allowed to wakeup AP in S3. */
-#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \
-		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
-
 /* MKBP */
+#define CONFIG_MKBP_INPUT_DEVICES
 #define CONFIG_MKBP_EVENT
 #define CONFIG_MKBP_EVENT_WAKEUP_MASK \
 	(BIT(EC_MKBP_EVENT_SENSOR_FIFO) | BIT(EC_MKBP_EVENT_HOST_EVENT))
@@ -149,20 +153,19 @@ void emmc_cmd_interrupt(enum gpio_signal signal);
 
 void board_reset_pd_mcu(void);
 int board_get_version(void);
-int board_is_sourcing_vbus(int port);
 void pogo_adc_interrupt(enum gpio_signal signal);
 int board_discharge_on_ac(int enable);
 
 /* Enable double tap detection */
 #define CONFIG_GESTURE_DETECTION
 #define CONFIG_GESTURE_HOST_DETECTION
-#define CONFIG_GESTURE_SENSOR_DOUBLE_TAP 0
-#define CONFIG_GESTURE_SENSOR_DOUBLE_TAP_FOR_HOST
+#define CONFIG_GESTURE_SENSOR_DOUBLE_TAP
+#define CONFIG_GESTURE_TAP_FOR_HOST
 #define CONFIG_GESTURE_SAMPLING_INTERVAL_MS 5
 #define CONFIG_GESTURE_TAP_THRES_MG 100
 #define CONFIG_GESTURE_TAP_MAX_INTERSTICE_T 500
-#define CONFIG_GESTURE_DETECTION_MASK \
-	BIT(CONFIG_GESTURE_SENSOR_DOUBLE_TAP)
+#define CONFIG_GESTURE_TAP_SENSOR 0
+#define CONFIG_GESTURE_DETECTION_MASK BIT(CONFIG_GESTURE_TAP_SENSOR)
 
 #endif /* !__ASSEMBLER__ */
 
diff --git a/board/kukui/build.mk b/board/kukui/build.mk
index 694879cee6..b60b9cf091 100644
--- a/board/kukui/build.mk
+++ b/board/kukui/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/kukui/ec.tasklist b/board/kukui/ec.tasklist
index 9ba564ce52..2551038b66 100644
--- a/board/kukui/ec.tasklist
+++ b/board/kukui/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/kukui/gpio.inc b/board/kukui/gpio.inc
index 1f17a24bcd..efac70d681 100644
--- a/board/kukui/gpio.inc
+++ b/board/kukui/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -30,7 +30,7 @@ GPIO_INT(AP_EC_WATCHDOG_L,  PIN(C, 2),  GPIO_INT_FALLING,
          chipset_watchdog_interrupt)
 
 GPIO_INT_RW(ACCEL_INT_ODL,  PIN(A, 4), GPIO_INT_FALLING | GPIO_SEL_1P8V | GPIO_PULL_UP,
-         bmi160_interrupt)
+         motion_interrupt)
 GPIO_INT(CHARGER_INT_ODL,   PIN(C, 13), GPIO_INT_FALLING | GPIO_PULL_UP,
          rt946x_interrupt)
 GPIO_INT_RO(EMMC_CMD,       PIN(B, 15), GPIO_INT_FALLING,
diff --git a/board/kukui/led.c b/board/kukui/led.c
index 59f7681754..b6836f49fb 100644
--- a/board/kukui/led.c
+++ b/board/kukui/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -15,46 +15,45 @@ const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-static enum charge_state prv_chstate = PWR_STATE_INIT;
+static enum led_pwr_state prv_chstate = LED_PWRS_INIT;
 
-#define LED_OFF		MT6370_LED_ID_OFF
-#define LED_RED		MT6370_LED_ID1
-#define LED_GREEN	MT6370_LED_ID2
-#define LED_BLUE	MT6370_LED_ID3
+#define LED_OFF MT6370_LED_ID_OFF
+#define LED_RED MT6370_LED_ID1
+#define LED_GREEN MT6370_LED_ID2
+#define LED_BLUE MT6370_LED_ID3
 
-#define LED_MASK_OFF	0
-#define LED_MASK_RED	MT6370_MASK_RGB_ISNK1DIM_EN
-#define LED_MASK_GREEN	MT6370_MASK_RGB_ISNK2DIM_EN
-#define LED_MASK_BLUE	MT6370_MASK_RGB_ISNK3DIM_EN
+#define LED_MASK_OFF 0
+#define LED_MASK_RED MT6370_MASK_RGB_ISNK1DIM_EN
+#define LED_MASK_GREEN MT6370_MASK_RGB_ISNK2DIM_EN
+#define LED_MASK_BLUE MT6370_MASK_RGB_ISNK3DIM_EN
 
 static void kukui_led_set_battery(void)
 {
-	enum charge_state chstate;
+	enum led_pwr_state chstate;
 	static uint8_t prv_r, prv_g, prv_b;
 	uint8_t br[EC_LED_COLOR_COUNT] = { 0 };
 
-	chstate = charge_get_state();
+	chstate = led_pwr_get_state();
 
-	if (prv_chstate == chstate &&
-		chstate != PWR_STATE_DISCHARGE)
+	if (prv_chstate == chstate && chstate != LED_PWRS_DISCHARGE)
 		return;
 
 	prv_chstate = chstate;
 
 	switch (chstate) {
-	case PWR_STATE_CHARGE:
+	case LED_PWRS_CHARGE:
 		/* RGB(current, duty) = (4mA,1/32)*/
 		br[EC_LED_COLOR_BLUE] = 1;
 		break;
-	case PWR_STATE_DISCHARGE:
+	case LED_PWRS_DISCHARGE:
 		/* display SoC 10% = real battery SoC 13%*/
 		if (charge_get_percent() <= 13)
 			br[EC_LED_COLOR_RED] = 1;
 		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
+	case LED_PWRS_CHARGE_NEAR_FULL:
 		br[EC_LED_COLOR_GREEN] = 1;
 		break;
-	case PWR_STATE_ERROR:
+	case LED_PWRS_ERROR:
 		br[EC_LED_COLOR_RED] = 1;
 		break;
 	default:
@@ -62,8 +61,7 @@ static void kukui_led_set_battery(void)
 		return;
 	}
 
-	if (prv_r == br[EC_LED_COLOR_RED] &&
-	    prv_g == br[EC_LED_COLOR_GREEN] &&
+	if (prv_r == br[EC_LED_COLOR_RED] && prv_g == br[EC_LED_COLOR_GREEN] &&
 	    prv_b == br[EC_LED_COLOR_BLUE])
 		return;
 
@@ -111,7 +109,7 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
  */
 static void led_reset_auto_control(void)
 {
-	prv_chstate = PWR_STATE_INIT;
+	prv_chstate = LED_PWRS_INIT;
 }
 
 static void krane_led_init(void)
diff --git a/board/kukui/vif_override.xml b/board/kukui/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/kukui/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/kukui_scp/board.c b/board/kukui_scp/board.c
index e5c4f0c760..e961b91a94 100644
--- a/board/kukui_scp/board.c
+++ b/board/kukui_scp/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,6 +16,5 @@
 #include "timer.h"
 #include "util.h"
 
-/* Build GPIO tables */
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
-
diff --git a/board/kukui_scp/board.h b/board/kukui_scp/board.h
index fcd9fb6399..fb074c59e0 100644
--- a/board/kukui_scp/board.h
+++ b/board/kukui_scp/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,9 +10,14 @@
 
 #define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_HOSTCMD) | CC_MASK(CC_IPI)))
 
-#define CONFIG_FLASH_SIZE 0x58000 /* Image file size: 256KB */
-#undef  CONFIG_LID_SWITCH
-#undef  CONFIG_FW_INCLUDE_RO
+#ifdef CHIP_VARIANT_MT8186
+#define CONFIG_FLASH_SIZE_BYTES 0x2C000 /* SRAM Size: 256KB */
+#else
+#define CONFIG_FLASH_SIZE_BYTES 0x58000 /* Image file size: 256KB */
+#endif
+
+#undef CONFIG_LID_SWITCH
+#undef CONFIG_FW_INCLUDE_RO
 #define CONFIG_MKBP_EVENT
 /* Sent MKBP event via IPI. */
 #define CONFIG_MKBP_USE_CUSTOM
@@ -22,10 +27,12 @@
 #define CONFIG_HOSTCMD_ALIGNED
 
 /*
+ * mt8183:
+ *
  * RW only, no flash
  * +-------------------- 0x0
  * | ROM vectortable, .text, .rodata, .data LMA
- * +-------------------- 0x10000
+ * +-------------------- 0x58000
  * | RAM .bss, .data
  * +-------------------- 0x7BDB0
  * | IPI shared buffer with AP (288 + 8) * 2
@@ -35,9 +42,38 @@
  * | 8KB D-CACHE
  * +-------------------- 0x80000
  */
-#define ICACHE_BASE 0x7C000
+
+/*
+ * mt8186:
+ *
+ * RW only, no flash
+ * +-------------------- 0x0
+ * | ROM vectortable, .text, .rodata, .data LMA
+ * +-------------------- 0x2C000
+ * | RAM .bss, .data
+ * +-------------------- 0x3BDB0
+ * | IPI shared buffer with AP (288 + 8) * 2 => 0x250
+ * +-------------------- 0x3C000
+ * | 8KB I-CACHE
+ * +-------------------- 0x3E000
+ * | 8KB D-CACHE
+ * +-------------------- 0x40000
+ */
+
 #define CONFIG_ROM_BASE 0x0
+
+#ifdef CHIP_VARIANT_MT8186
+#define CONFIG_RAM_BASE 0x2C000
+#else
 #define CONFIG_RAM_BASE 0x58000
+#endif
+
+#ifdef CHIP_VARIANT_MT8186
+#define ICACHE_BASE 0x3C000
+#else
+#define ICACHE_BASE 0x7C000
+#endif
+
 #define CONFIG_ROM_SIZE (CONFIG_RAM_BASE - CONFIG_ROM_BASE)
 #define CONFIG_RAM_SIZE (CONFIG_IPC_SHARED_OBJ_ADDR - CONFIG_RAM_BASE)
 #define CONFIG_CODE_RAM_SIZE CONFIG_RAM_BASE
@@ -48,12 +84,19 @@
 #define CONFIG_DRAM_BASE 0x10000000
 /* Shared memory address in AP physical address space. */
 #define CONFIG_DRAM_BASE_LOAD 0x50000000
+
+#ifdef CHIP_VARIANT_MT8186
+#define CONFIG_DRAM_SIZE 0x010a0000 /* 16 MB */
+#define CACHE_TRANS_AP_SIZE 0x010a0000
+#else
 #define CONFIG_DRAM_SIZE 0x01400000 /* 20 MB */
+#define CACHE_TRANS_AP_SIZE 0x00400000
+#endif
 
 /* IPI configs */
 #define CONFIG_IPC_SHARED_OBJ_BUF_SIZE 288
-#define CONFIG_IPC_SHARED_OBJ_ADDR                                             \
-	(ICACHE_BASE -                                                         \
+#define CONFIG_IPC_SHARED_OBJ_ADDR \
+	(ICACHE_BASE -             \
 	 (CONFIG_IPC_SHARED_OBJ_BUF_SIZE + 2 * 4 /* int32_t */) * 2)
 #define CONFIG_IPI
 #define CONFIG_RPMSG_NAME_SERVICE
@@ -75,28 +118,30 @@
 #define IPI_ISP_FRAME 11
 #define IPI_FD_CMD 12
 #define IPI_HOST_COMMAND 13
-#define IPI_COUNT 14
+#define SCP_IPI_VDEC_LAT 14
+#define SCP_IPI_VDEC_CORE 15
+#define IPI_COUNT 16
 
 #define IPI_NS_SERVICE 0xFF
 
-#define CONFIG_SUPPRESSED_HOST_COMMANDS \
-	EC_CMD_CONSOLE_SNAPSHOT, EC_CMD_CONSOLE_READ
-
 #undef CONFIG_UART_TX_BUF_SIZE
 #define CONFIG_UART_TX_BUF_SIZE 8192
 
-#undef  CONFIG_UART_CONSOLE
+#undef CONFIG_UART_CONSOLE
 /*
  * CONFIG_UART_CONSOLE
  *   0 - SCP UART0
  *   1 - SCP UART1
  *   2 - share with AP UART0
  */
+#ifdef CHIP_VARIANT_MT8186
+#define CONFIG_UART_CONSOLE 1
+#else
 #define CONFIG_UART_CONSOLE 0
-
+#endif
 /* We let AP setup the correct pinmux. */
-#undef    UART0_PINMUX_11_12
-#undef    UART0_PINMUX_110_112
+#undef UART0_PINMUX_11_12
+#undef UART0_PINMUX_110_112
 
 /* Track AP power state */
 #define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
diff --git a/board/kukui_scp/build.mk b/board/kukui_scp/build.mk
index 19355b5af5..f04d506057 100644
--- a/board/kukui_scp/build.mk
+++ b/board/kukui_scp/build.mk
@@ -1,12 +1,17 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
 # Board specific files build
 #
 CHIP:=mt_scp
+
+ifeq ($(BOARD), corsola_scp)
+CHIP_VARIANT:=mt8186
+else
 CHIP_VARIANT:=mt8183
+endif
 
 board-y=board.o
 board-$(HAS_TASK_VDEC_SERVICE)+=vdec.o
diff --git a/board/kukui_scp/ec.tasklist b/board/kukui_scp/ec.tasklist
index 935d409b00..179e1b7c7f 100644
--- a/board/kukui_scp/ec.tasklist
+++ b/board/kukui_scp/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,13 +14,24 @@
 #define UART_TASK
 #endif
 
+#ifdef HAVE_PRIVATE_MT8183
 #define S3_SUSPEND_TASK_LIST \
 	TASK_ALWAYS(VDEC_SERVICE, vdec_service_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(VENC_SERVICE, venc_service_task, NULL, LARGER_TASK_STACK_SIZE) \
 	TASK_ALWAYS(FD_SERVICE, fd_service_task, NULL, 760) \
 	TASK_ALWAYS(DIP_SERVICE, dip_service_task, NULL, 6400) \
+	TASK_ALWAYS(ISP_SERVICE, isp_service_task, NULL, 880) \
 	TASK_ALWAYS(MDP_SERVICE, mdp_service_task, NULL, 1800) \
-	TASK_ALWAYS(ISP_SERVICE, isp_service_task, NULL, 880)
+	TASK_ALWAYS(VENC_SERVICE, venc_service_task, NULL, LARGER_TASK_STACK_SIZE)
+#else
+#define S3_SUSPEND_TASK_LIST \
+	TASK_ALWAYS(VDEC_SERVICE, vdec_service_task, NULL, 4096) \
+	TASK_ALWAYS(VDEC_CORE_SERVICE, vdec_core_service_task, NULL, 4096) \
+	TASK_ALWAYS(MDP_SERVICE, mdp_service_task, NULL, 1800) \
+	TASK_ALWAYS(FD_SERVICE, fd_service_task, NULL, 760) \
+	TASK_ALWAYS(DIP_SERVICE, dip_service_task, NULL, 6400) \
+	TASK_ALWAYS(ISP_SERVICE, isp_service_task, NULL, 880) \
+	TASK_ALWAYS(VENC_SERVICE, venc_service_task, NULL, LARGER_TASK_STACK_SIZE)
+#endif
 
 #define CONFIG_TASK_LIST \
 	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
diff --git a/board/kukui_scp/fd.c b/board/kukui_scp/fd.c
index 11f27cf945..be0bdeab57 100644
--- a/board/kukui_scp/fd.c
+++ b/board/kukui_scp/fd.c
@@ -1,17 +1,17 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include "chip/mt_scp/ipi_chip.h"
-#include "chip/mt_scp/registers.h"
 #include "console.h"
-#include "hooks.h"
-#include "task.h"
-#include "util.h"
 #include "fd.h"
+#include "hooks.h"
+#include "ipi_chip.h"
 #include "queue.h"
 #include "queue_policies.h"
+#include "registers.h"
+#include "task.h"
+#include "util.h"
 
 #define CPRINTF(format, args...) cprintf(CC_IPI, format, ##args)
 #define CPRINTS(format, args...) cprints(CC_IPI, format, ##args)
@@ -20,12 +20,11 @@
 static struct consumer const event_fd_consumer;
 static void event_fd_written(struct consumer const *consumer, size_t count);
 
-static struct queue const fd_queue = QUEUE_DIRECT(4, struct fd_msg,
-						  null_producer,
-						  event_fd_consumer);
+static struct queue const fd_queue =
+	QUEUE_DIRECT(4, struct fd_msg, null_producer, event_fd_consumer);
 static struct consumer const event_fd_consumer = {
 	.queue = &fd_queue,
-	.ops = &((struct consumer_ops const) {
+	.ops = &((struct consumer_ops const){
 		.written = event_fd_written,
 	}),
 };
@@ -33,7 +32,9 @@ static struct consumer const event_fd_consumer = {
 /* Stub functions only provided by private overlays. */
 // Jerry TODO implement private part and remove this
 #ifndef HAVE_PRIVATE_MT8183
-void fd_ipi_msg_handler(void *data) {}
+void fd_ipi_msg_handler(void *data)
+{
+}
 #endif
 
 static void event_fd_written(struct consumer const *consumer, size_t count)
diff --git a/board/kukui_scp/fd.h b/board/kukui_scp/fd.h
index 07554f7e15..cea5817942 100644
--- a/board/kukui_scp/fd.h
+++ b/board/kukui_scp/fd.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,9 +6,9 @@
 #ifndef __CROS_EC_SCP_FD_H
 #define __CROS_EC_SCP_FD_H
 
-#include "chip/mt_scp/registers.h"
-#include "queue.h"
 #include "compile_time_macros.h"
+#include "queue.h"
+#include "registers.h"
 
 enum fd_msg_type {
 	FD_IPI_MSG,
diff --git a/board/kukui_scp/gpio.inc b/board/kukui_scp/gpio.inc
index b186904aad..6cc2e0495e 100644
--- a/board/kukui_scp/gpio.inc
+++ b/board/kukui_scp/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/kukui_scp/isp_p1_srv.c b/board/kukui_scp/isp_p1_srv.c
index 92048f98c1..40dd37ff90 100644
--- a/board/kukui_scp/isp_p1_srv.c
+++ b/board/kukui_scp/isp_p1_srv.c
@@ -1,17 +1,17 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include "chip/mt_scp/ipi_chip.h"
-#include "chip/mt_scp/registers.h"
 #include "console.h"
 #include "dma.h"
 #include "hooks.h"
+#include "ipi_chip.h"
 #include "isp_p1_srv.h"
-#include "task.h"
 #include "queue.h"
 #include "queue_policies.h"
+#include "registers.h"
+#include "task.h"
 #include "util.h"
 
 #define CPRINTS(format, args...) cprints(CC_IPI, format, ##args)
@@ -20,19 +20,21 @@
 static struct consumer const event_isp_consumer;
 static void event_isp_written(struct consumer const *consumer, size_t count);
 
-static struct queue const event_isp_queue = QUEUE_DIRECT(8,
-	struct isp_msg, null_producer, event_isp_consumer);
+static struct queue const event_isp_queue =
+	QUEUE_DIRECT(8, struct isp_msg, null_producer, event_isp_consumer);
 
 static struct consumer const event_isp_consumer = {
 	.queue = &event_isp_queue,
-	.ops = &((struct consumer_ops const) {
+	.ops = &((struct consumer_ops const){
 		.written = event_isp_written,
 	}),
 };
 
 /* Stub functions only provided by private overlays. */
 #ifndef HAVE_PRIVATE_MT8183
-void isp_msg_handler(void *data) {}
+void isp_msg_handler(void *data)
+{
+}
 #endif
 
 static void event_isp_written(struct consumer const *consumer, size_t count)
diff --git a/board/kukui_scp/isp_p1_srv.h b/board/kukui_scp/isp_p1_srv.h
index 6e262b55e4..e0abe9e4c8 100644
--- a/board/kukui_scp/isp_p1_srv.h
+++ b/board/kukui_scp/isp_p1_srv.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,14 +6,15 @@
 #ifndef __CROS_EC_ISP_P1_SRV_H
 #define __CROS_EC_ISP_P1_SRV_H
 
-#include "chip/mt_scp/ipi_chip.h"
+#include "ipi_chip.h"
 
 struct isp_msg {
 	unsigned char id;
 	unsigned char msg[140];
 };
 
-BUILD_ASSERT(member_size(struct isp_msg, msg) <= CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
+BUILD_ASSERT(member_size(struct isp_msg, msg) <=
+	     CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
 
 /* Functions provided by private overlay. */
 void isp_msg_handler(void *data);
diff --git a/board/kukui_scp/isp_p2_srv.c b/board/kukui_scp/isp_p2_srv.c
old mode 100755
new mode 100644
index 5acb81ae0f..f38d4401ff
--- a/board/kukui_scp/isp_p2_srv.c
+++ b/board/kukui_scp/isp_p2_srv.c
@@ -1,17 +1,17 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include "isp_p2_srv.h"
-#include "chip/mt_scp/ipi_chip.h"
-#include "chip/mt_scp/registers.h"
-#include "queue_policies.h"
 #include "console.h"
 #include "hooks.h"
+#include "ipi_chip.h"
+#include "isp_p2_srv.h"
+#include "queue.h"
+#include "queue_policies.h"
+#include "registers.h"
 #include "task.h"
 #include "util.h"
-#include "queue.h"
 
 #define CPRINTS(format, args...) cprints(CC_IPI, format, ##args)
 
@@ -19,19 +19,21 @@
 static struct consumer const event_dip_consumer;
 static void event_dip_written(struct consumer const *consumer, size_t count);
 
-static struct queue const event_dip_queue = QUEUE_DIRECT(4,
-	struct dip_msg_service, null_producer, event_dip_consumer);
+static struct queue const event_dip_queue = QUEUE_DIRECT(
+	4, struct dip_msg_service, null_producer, event_dip_consumer);
 
 static struct consumer const event_dip_consumer = {
 	.queue = &event_dip_queue,
-	.ops = &((struct consumer_ops const) {
+	.ops = &((struct consumer_ops const){
 		.written = event_dip_written,
 	}),
 };
 
 /* Stub functions only provided by private overlays. */
 #ifndef HAVE_PRIVATE_MT8183
-void dip_msg_handler(void *data) {}
+void dip_msg_handler(void *data)
+{
+}
 #endif
 
 static void event_dip_written(struct consumer const *consumer, size_t count)
diff --git a/board/kukui_scp/isp_p2_srv.h b/board/kukui_scp/isp_p2_srv.h
index 196de3e092..3c1ba50f1c 100644
--- a/board/kukui_scp/isp_p2_srv.h
+++ b/board/kukui_scp/isp_p2_srv.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,14 +6,15 @@
 #ifndef __CROS_EC_ISP_P2_SRV_H
 #define __CROS_EC_ISP_P2_SRV_H
 
-#include "chip/mt_scp/ipi_chip.h"
+#include "ipi_chip.h"
 
 struct dip_msg_service {
 	unsigned char id;
 	unsigned char msg[288];
 };
 
-BUILD_ASSERT(member_size(struct dip_msg_service, msg) <= CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
+BUILD_ASSERT(member_size(struct dip_msg_service, msg) <=
+	     CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
 
 /* Functions provided by private overlay. */
 void dip_msg_handler(void *data);
diff --git a/board/kukui_scp/mdp_ipi_message.c b/board/kukui_scp/mdp_ipi_message.c
index a33048821f..fd6da65a07 100644
--- a/board/kukui_scp/mdp_ipi_message.c
+++ b/board/kukui_scp/mdp_ipi_message.c
@@ -1,17 +1,16 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "console.h"
+#include "ipi_chip.h"
+#include "mdp_ipi_message.h"
 #include "queue_policies.h"
+#include "registers.h"
 #include "task.h"
 #include "util.h"
 
-#include "chip/mt_scp/ipi_chip.h"
-#include "chip/mt_scp/registers.h"
-#include "mdp_ipi_message.h"
-
 #define CPRINTF(format, args...) cprintf(CC_IPI, format, ##args)
 #define CPRINTS(format, args...) cprints(CC_IPI, format, ##args)
 
@@ -19,19 +18,25 @@
 static struct consumer const event_mdp_consumer;
 static void event_mdp_written(struct consumer const *consumer, size_t count);
 
-static struct queue const event_mdp_queue = QUEUE_DIRECT(4,
-	struct mdp_msg_service, null_producer, event_mdp_consumer);
+static struct queue const event_mdp_queue = QUEUE_DIRECT(
+	4, struct mdp_msg_service, null_producer, event_mdp_consumer);
 static struct consumer const event_mdp_consumer = {
 	.queue = &event_mdp_queue,
-	.ops = &((struct consumer_ops const) {
+	.ops = &((struct consumer_ops const){
 		.written = event_mdp_written,
 	}),
 };
 
 /* Stub functions only provided by private overlays. */
 #ifndef HAVE_PRIVATE_MT8183
-void mdp_common_init(void) {}
-void mdp_ipi_task_handler(void *pvParameters) {}
+#ifndef HAVE_PRIVATE_MT8186
+void mdp_common_init(void)
+{
+}
+void mdp_ipi_task_handler(void *pvParameters)
+{
+}
+#endif
 #endif
 
 static void event_mdp_written(struct consumer const *consumer, size_t count)
diff --git a/board/kukui_scp/mdp_ipi_message.h b/board/kukui_scp/mdp_ipi_message.h
index bcedb58504..0e46b947b2 100644
--- a/board/kukui_scp/mdp_ipi_message.h
+++ b/board/kukui_scp/mdp_ipi_message.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,9 +11,10 @@ struct mdp_msg_service {
 	unsigned char msg[20];
 };
 
-BUILD_ASSERT(member_size(struct mdp_msg_service, msg) <= CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
+BUILD_ASSERT(member_size(struct mdp_msg_service, msg) <=
+	     CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
 
 void mdp_common_init(void);
 void mdp_ipi_task_handler(void *pvParameters);
 
-#endif  // _MDP_IPI_MESSAGE_H
+#endif // _MDP_IPI_MESSAGE_H
diff --git a/board/kukui_scp/update_scp b/board/kukui_scp/update_scp
index 846095a7f9..67aaacdcdc 100755
--- a/board/kukui_scp/update_scp
+++ b/board/kukui_scp/update_scp
@@ -1,12 +1,12 @@
 #!/bin/bash
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 usage() {
-  echo "Usage: $0 [IP] [bin/elf]" >&2
+  echo "Usage: $0 [kukui_scp/corsola_scp] [IP] [bin/elf]" >&2
   echo >&2
-  echo "Deploy kukui_scp image to DUT, and restart the remoteproc driver" >&2
+  echo "Deploy kukui_scp/corsola_scp image to DUT, and restart the remoteproc driver" >&2
   exit 2
 }
 
@@ -14,25 +14,31 @@ if [[ -z "$1" ]]; then
    usage
 fi
 
-KUKUI_IP="$1"
-INFILE="build/kukui_scp/ec.bin"
+if [ "$1" = "kukui_scp" ] || [ "$1" = "corsola_scp" ]; then
+   BOARD="$1"
+else
+   usage
+fi
+
+DUT_IP="$2"
+INFILE="build/$BOARD/ec.bin"
 
-case "$2" in
+case "$3" in
 bin)
   ;;
 elf|"") # Default
   # ec.obj is an elf file that has the right memory layout to be loaded
   # from the AP/kernel.
-  INFILE="build/kukui_scp/ec.obj"
+  INFILE="build/$BOARD/ec.obj"
   ;;
 *)
   usage
   ;;
 esac
 
-scp "$INFILE" "$KUKUI_IP":/lib/firmware/scp.img
+scp "$INFILE" "$DUT_IP":/lib/firmware/scp.img
 
-ssh "$KUKUI_IP" sh -x -c "'
+ssh "$DUT_IP" sh -x -c "'
     sync;
     echo stop > /sys/class/remoteproc/remoteproc0/state;
     echo start > /sys/class/remoteproc/remoteproc0/state'"
diff --git a/board/kukui_scp/vdec.c b/board/kukui_scp/vdec.c
index 6ab257b08e..fcc327d764 100644
--- a/board/kukui_scp/vdec.c
+++ b/board/kukui_scp/vdec.c
@@ -1,55 +1,89 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include "chip/mt_scp/ipi_chip.h"
-#include "chip/mt_scp/registers.h"
 #include "console.h"
-#include "hooks.h"
+#include "ipi_chip.h"
+#include "queue_policies.h"
+#include "registers.h"
 #include "task.h"
 #include "util.h"
 #include "vdec.h"
+#ifdef HAVE_PRIVATE_MT8183
+#include "hooks.h"
 #include "queue.h"
-#include "queue_policies.h"
+#else
+#include "link_defs.h"
+#endif
 
 #define CPRINTF(format, args...) cprintf(CC_IPI, format, ##args)
 #define CPRINTS(format, args...) cprints(CC_IPI, format, ##args)
 
-/* Forwad declaration. */
+static void event_vdec_written(struct consumer const *consumer, size_t count)
+{
+	task_wake(TASK_ID_VDEC_SERVICE);
+}
 static struct consumer const event_vdec_consumer;
-static void event_vdec_written(struct consumer const *consumer, size_t count);
-
-static struct queue const event_vdec_queue = QUEUE_DIRECT(8,
-	struct vdec_msg, null_producer, event_vdec_consumer);
+static struct queue const event_vdec_queue =
+	QUEUE_DIRECT(8, struct vdec_msg, null_producer, event_vdec_consumer);
 static struct consumer const event_vdec_consumer = {
 	.queue = &event_vdec_queue,
-	.ops = &((struct consumer_ops const) {
+	.ops = &((struct consumer_ops const){
 		.written = event_vdec_written,
 	}),
 };
 
-/* Stub functions only provided by private overlays. */
+/*
+ * Only need to separate 8183 and others.
+ * 8183's architecture is different with other platforms.
+ * 8186 and future platform's architecture is the same, won't change anymore.
+ */
 #ifndef HAVE_PRIVATE_MT8183
-void vdec_h264_service_init(void) {}
-void vdec_h264_msg_handler(void *data) {}
-#endif
-
+static void event_vdec_core_written(struct consumer const *consumer,
+				    size_t count)
+{
+	task_wake(TASK_ID_VDEC_CORE_SERVICE);
+}
+static struct consumer const event_vdec_core_consumer;
+static struct queue const event_vdec_core_queue = QUEUE_DIRECT(
+	8, struct vdec_msg, null_producer, event_vdec_core_consumer);
+static struct consumer const event_vdec_core_consumer = {
+	.queue = &event_vdec_core_queue,
+	.ops = &((struct consumer_ops const){
+		.written = event_vdec_core_written,
+	}),
+};
+#else
 static vdec_msg_handler mtk_vdec_msg_handle[VDEC_MAX];
+#endif
 
-static void event_vdec_written(struct consumer const *consumer, size_t count)
+/* Stub functions only provided by private overlays. */
+#ifndef HAVE_PRIVATE_MT8183
+#ifndef HAVE_PRIVATE_MT8186
+void vdec_msg_handler(void *data)
+{
+}
+void vdec_core_msg_handler(void *data)
 {
-	task_wake(TASK_ID_VDEC_SERVICE);
 }
+#endif
+#endif
 
 static void vdec_h264_ipi_handler(int id, void *data, uint32_t len)
 {
 	struct vdec_msg rsv_msg;
 
-	if (!len)
+	if (!len) {
+		CPRINTS("len is zero.");
 		return;
+	}
 
+#ifdef HAVE_PRIVATE_MT8183
 	rsv_msg.type = VDEC_H264;
+#else
+	rsv_msg.type = VDEC_LAT;
+#endif
 	memcpy(rsv_msg.msg, data, MIN(len, sizeof(rsv_msg.msg)));
 
 	/*
@@ -59,17 +93,21 @@ static void vdec_h264_ipi_handler(int id, void *data, uint32_t len)
 	if (!queue_add_unit(&event_vdec_queue, &rsv_msg))
 		CPRINTS("Could not send vdec %d to the queue.", rsv_msg.type);
 }
+#ifdef HAVE_PRIVATE_MT8183
 DECLARE_IPI(IPI_VDEC_H264, vdec_h264_ipi_handler, 0);
+#else
+DECLARE_IPI(SCP_IPI_VDEC_LAT, vdec_h264_ipi_handler, 0);
+#endif
 
-/* This function renames from vdec_service_entry. */
 void vdec_service_task(void *u)
 {
 	struct vdec_msg rsv_msg;
 	size_t size;
 
+#ifdef HAVE_PRIVATE_MT8183
 	vdec_h264_service_init();
 	mtk_vdec_msg_handle[VDEC_H264] = vdec_h264_msg_handler;
-
+#endif
 	while (1) {
 		/*
 		 * Queue unit is added in IPI handler, which is in ISR context.
@@ -79,11 +117,62 @@ void vdec_service_task(void *u)
 		size = queue_remove_unit(&event_vdec_queue, &rsv_msg);
 		ipi_enable_irq(SCP_IRQ_IPC0);
 
-		if (!size)
+		if (!size) {
 			task_wait_event(-1);
-		else if (mtk_vdec_msg_handle[rsv_msg.type])
+			continue;
+		}
+#ifndef HAVE_PRIVATE_MT8183
+		vdec_msg_handler(rsv_msg.msg);
+#else
+		if (mtk_vdec_msg_handle[rsv_msg.type])
 			vdec_h264_msg_handler(rsv_msg.msg);
 		else
 			CPRINTS("vdec handler %d not exists.", rsv_msg.type);
+#endif
 	}
 }
+
+#ifndef HAVE_PRIVATE_MT8183
+static void vdec_h264_ipi_core_handler(int id, void *data, uint32_t len)
+{
+	struct vdec_msg rsv_msg;
+
+	if (!len) {
+		CPRINTS("len is zero.");
+		return;
+	}
+
+	rsv_msg.type = VDEC_CORE;
+	memcpy(rsv_msg.msg, data, MIN(len, sizeof(rsv_msg.msg)));
+
+	/*
+	 * If there is no other IPI handler touch this queue, we don't need to
+	 * interrupt_disable() or task_disable_irq().
+	 */
+	if (!queue_add_unit(&event_vdec_core_queue, &rsv_msg))
+		CPRINTS("Could not send vdec %d to core queue.", rsv_msg.type);
+}
+DECLARE_IPI(SCP_IPI_VDEC_CORE, vdec_h264_ipi_core_handler, 0);
+
+void vdec_core_service_task(void *u)
+{
+	struct vdec_msg rsv_msg;
+	size_t size;
+
+	while (1) {
+		/*
+		 * Queue unit is added in IPI handler, which is in ISR context.
+		 * Disable IRQ to prevent a clobbered queue.
+		 */
+		ipi_disable_irq(SCP_IRQ_IPC0);
+		size = queue_remove_unit(&event_vdec_core_queue, &rsv_msg);
+		ipi_enable_irq(SCP_IRQ_IPC0);
+
+		if (!size) {
+			task_wait_event(-1);
+			continue;
+		}
+		vdec_core_msg_handler(rsv_msg.msg);
+	}
+}
+#endif
diff --git a/board/kukui_scp/vdec.h b/board/kukui_scp/vdec.h
index 6e4c9b40e7..411c1cbd15 100644
--- a/board/kukui_scp/vdec.h
+++ b/board/kukui_scp/vdec.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,9 +6,11 @@
 #ifndef __CROS_EC_SCP_VDEC_H
 #define __CROS_EC_SCP_VDEC_H
 
-#include "chip/mt_scp/registers.h"
 #include "compile_time_macros.h"
+
+#ifdef HAVE_PRIVATE_MT8183
 #include "queue.h"
+#include "registers.h"
 
 enum vdec_type {
 	VDEC_H264,
@@ -18,16 +20,29 @@ enum vdec_type {
 };
 
 typedef void (*vdec_msg_handler)(void *msg);
+#else
+enum vdec_type {
+	VDEC_LAT,
+	VDEC_CORE,
+	VDEC_MAX,
+};
+#endif
 
 struct vdec_msg {
 	enum vdec_type type;
 	unsigned char msg[48];
 };
 
-BUILD_ASSERT(member_size(struct vdec_msg, msg) <= CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
+BUILD_ASSERT(member_size(struct vdec_msg, msg) <=
+	     CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
 
 /* Functions provided by private overlay. */
+#ifdef HAVE_PRIVATE_MT8183
 void vdec_h264_service_init(void);
 void vdec_h264_msg_handler(void *data);
+#else
+void vdec_core_msg_handler(void *msg);
+void vdec_msg_handler(void *msg);
+#endif
 
 #endif /* __CROS_EC_SCP_VDEC_H */
diff --git a/board/kukui_scp/venc.c b/board/kukui_scp/venc.c
index ef1df894a0..ca5fc08429 100644
--- a/board/kukui_scp/venc.c
+++ b/board/kukui_scp/venc.c
@@ -1,17 +1,17 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include "chip/mt_scp/ipi_chip.h"
-#include "chip/mt_scp/registers.h"
 #include "console.h"
 #include "hooks.h"
+#include "ipi_chip.h"
+#include "queue.h"
+#include "queue_policies.h"
+#include "registers.h"
 #include "task.h"
 #include "util.h"
 #include "venc.h"
-#include "queue.h"
-#include "queue_policies.h"
 
 #define CPRINTF(format, args...) cprintf(CC_IPI, format, ##args)
 #define CPRINTS(format, args...) cprints(CC_IPI, format, ##args)
@@ -20,11 +20,11 @@
 static struct consumer const event_venc_consumer;
 static void event_venc_written(struct consumer const *consumer, size_t count);
 
-static struct queue const event_venc_queue = QUEUE_DIRECT(8,
-	struct venc_msg, null_producer, event_venc_consumer);
+static struct queue const event_venc_queue =
+	QUEUE_DIRECT(8, struct venc_msg, null_producer, event_venc_consumer);
 static struct consumer const event_venc_consumer = {
 	.queue = &event_venc_queue,
-	.ops = &((struct consumer_ops const) {
+	.ops = &((struct consumer_ops const){
 		.written = event_venc_written,
 	}),
 };
@@ -33,7 +33,11 @@ static venc_msg_handler mtk_venc_msg_handle[VENC_MAX];
 
 /* Stub functions only provided by private overlays. */
 #ifndef HAVE_PRIVATE_MT8183
-void venc_h264_msg_handler(void *data) {}
+#ifndef HAVE_PRIVATE_MT8186
+void venc_h264_msg_handler(void *data)
+{
+}
+#endif
 #endif
 
 static void event_venc_written(struct consumer const *consumer, size_t count)
diff --git a/board/kukui_scp/venc.h b/board/kukui_scp/venc.h
index 1172efd1b1..dcb74dbd87 100644
--- a/board/kukui_scp/venc.h
+++ b/board/kukui_scp/venc.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,9 +6,13 @@
 #ifndef __CROS_EC_SCP_VENC_H
 #define __CROS_EC_SCP_VENC_H
 
-#include "chip/mt_scp/registers.h"
 #include "compile_time_macros.h"
 #include "queue.h"
+#include "registers.h"
+
+#ifdef HAVE_PRIVATE_MT8186
+#include "venc_h264_srv.h"
+#endif
 
 enum venc_type {
 	VENC_H264,
@@ -22,7 +26,8 @@ struct venc_msg {
 	unsigned char msg[288];
 };
 
-BUILD_ASSERT(member_size(struct venc_msg, msg) <= CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
+BUILD_ASSERT(member_size(struct venc_msg, msg) <=
+	     CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
 
 /* Functions provided by private overlay. */
 void venc_h264_msg_handler(void *data);
diff --git a/board/kuldax/board.c b/board/kuldax/board.c
new file mode 100644
index 0000000000..37c2a6920c
--- /dev/null
+++ b/board/kuldax/board.c
@@ -0,0 +1,607 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "adc.h"
+#include "builtin/assert.h"
+#include "button.h"
+#include "cec.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "driver/cec/bitbang.h"
+#include "driver/tcpm/tcpci.h"
+#include "driver/wpc/cps8100.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "peripheral_charger.h"
+#include "power.h"
+#include "power_button.h"
+#include "switch.h"
+#include "throttle_ap.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+#include <stdbool.h>
+
+/* Console output macros */
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+
+static void power_monitor(void);
+DECLARE_DEFERRED(power_monitor);
+
+/******************************************************************************/
+/* USB-A charging control */
+
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_PP5000_USBA,
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
+
+struct pchg pchgs[] = {
+	[0] = {
+		.cfg = &(const struct pchg_config) {
+			.drv = &cps8200_drv,
+			.i2c_port = I2C_PORT_QI,
+			.irq_pin = GPIO_QI_INT_ODL,
+			.full_percent = 96,
+			.block_size = 128,
+			.flags = PCHG_CFG_FW_UPDATE_SYNC,
+		},
+		.policy = {
+			[PCHG_CHIPSET_STATE_ON] = &pchg_policy_on,
+			[PCHG_CHIPSET_STATE_SUSPEND] = &pchg_policy_suspend,
+		},
+		.events = QUEUE_NULL(PCHG_EVENT_QUEUE_SIZE, enum pchg_event),
+	},
+};
+
+__override void board_pchg_power_on(int port, bool on)
+{
+	if (port == 0)
+		gpio_set_level(GPIO_EC_QI_PWR, on);
+	else
+		CPRINTS("%s: Invalid port=%d", __func__, port);
+}
+
+int board_get_pchg_count(void)
+{
+	if (ec_cfg_has_peripheral_charger()) {
+		return ARRAY_SIZE(pchgs);
+	} else {
+		return 0;
+	}
+}
+
+/******************************************************************************/
+
+/* Power on Kuldax through CEC */
+struct cec_offline_policy kuldax_cec_policy[] = {
+	{
+		.command = CEC_MSG_REPORT_PHYSICAL_ADDRESS,
+		.action = CEC_ACTION_POWER_BUTTON,
+	},
+	{
+		.command = CEC_MSG_DEVICE_VENDOR_ID,
+		.action = CEC_ACTION_POWER_BUTTON,
+	},
+	/* Terminator */
+	{ 0 },
+};
+
+/* CEC ports */
+const struct cec_config_t cec_config[] = {
+	[CEC_PORT_0] = {
+		.drv = &bitbang_cec_drv,
+		.offline_policy = kuldax_cec_policy,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(cec_config) == CEC_PORT_COUNT);
+
+int board_set_active_charge_port(int port)
+{
+	CPRINTS("Requested charge port change to %d", port);
+
+	/*
+	 * The charge manager may ask us to switch to no charger if we're
+	 * running off USB-C only but upstream doesn't support PD. It requires
+	 * that we accept this switch otherwise it triggers an assert and EC
+	 * reset; it's not possible to boot the AP anyway, but we want to avoid
+	 * resetting the EC so we can continue to do the "low power" LED blink.
+	 */
+	if (port == CHARGE_PORT_NONE)
+		return EC_SUCCESS;
+
+	if (port < 0 || CHARGE_PORT_COUNT <= port)
+		return EC_ERROR_INVAL;
+
+	if (port == charge_manager_get_active_charge_port())
+		return EC_SUCCESS;
+
+	/* Don't charge from a source port */
+	if (board_vbus_source_enabled(port))
+		return EC_ERROR_INVAL;
+
+	if (!chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
+		int bj_active, bj_requested;
+
+		if (charge_manager_get_active_charge_port() != CHARGE_PORT_NONE)
+			/* Change is only permitted while the system is off */
+			return EC_ERROR_INVAL;
+
+		/*
+		 * Current setting is no charge port but the AP is on, so the
+		 * charge manager is out of sync (probably because we're
+		 * reinitializing after sysjump). Reject requests that aren't
+		 * in sync with our outputs.
+		 */
+		bj_active = !gpio_get_level(GPIO_EN_PPVAR_BJ_ADP_L);
+		bj_requested = port == CHARGE_PORT_BARRELJACK;
+		if (bj_active != bj_requested)
+			return EC_ERROR_INVAL;
+	}
+
+	CPRINTS("New charger p%d", port);
+
+	switch (port) {
+	case CHARGE_PORT_TYPEC0:
+		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 1);
+		break;
+	case CHARGE_PORT_BARRELJACK:
+		/* Make sure BJ adapter is sourcing power */
+		if (gpio_get_level(GPIO_BJ_ADP_PRESENT_ODL))
+			return EC_ERROR_INVAL;
+		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 0);
+		break;
+	default:
+		return EC_ERROR_INVAL;
+	}
+
+	return EC_SUCCESS;
+}
+
+static uint8_t usbc_overcurrent;
+static int32_t base_5v_power_s5;
+static int32_t base_5v_power_z1;
+
+/*
+ * Power usage for each port as measured or estimated.
+ * Units are milliwatts (5v x ma current)
+ */
+
+/* PP5000_S5 loads */
+#define PWR_S5_BASE_LOAD (5 * 1431)
+#define PWR_S5_FRONT_HIGH (5 * 1737)
+#define PWR_S5_FRONT_LOW (5 * 1055)
+#define PWR_S5_REAR_HIGH (5 * 1737)
+#define PWR_S5_REAR_LOW (5 * 1055)
+#define PWR_S5_HDMI (5 * 580)
+#define PWR_S5_MAX (5 * 10000)
+#define FRONT_DELTA (PWR_S5_FRONT_HIGH - PWR_S5_FRONT_LOW)
+#define REAR_DELTA (PWR_S5_REAR_HIGH - PWR_S5_REAR_LOW)
+
+/* PP5000_Z1 loads */
+#define PWR_Z1_BASE_LOAD (5 * 5)
+#define PWR_Z1_C_HIGH (5 * 3600)
+#define PWR_Z1_C_LOW (5 * 2000)
+#define PWR_Z1_MAX (5 * 9000)
+/*
+ * Update the 5V power usage, assuming no throttling,
+ * and invoke the power monitoring.
+ */
+static void update_5v_usage(void)
+{
+	int front_ports = 0;
+	int rear_ports = 0;
+
+	/*
+	 * Recalculate the 5V load, assuming no throttling.
+	 */
+	base_5v_power_s5 = PWR_S5_BASE_LOAD;
+	if (!gpio_get_level(GPIO_USB_A0_OC_ODL)) {
+		front_ports++;
+		base_5v_power_s5 += PWR_S5_FRONT_LOW;
+	}
+	if (!gpio_get_level(GPIO_USB_A1_OC_ODL)) {
+		front_ports++;
+		base_5v_power_s5 += PWR_S5_FRONT_LOW;
+	}
+	/*
+	 * Only 1 front port can run higher power at a time.
+	 */
+	if (front_ports > 0)
+		base_5v_power_s5 += PWR_S5_FRONT_HIGH - PWR_S5_FRONT_LOW;
+
+	if (!gpio_get_level(GPIO_USB_A2_OC_ODL)) {
+		rear_ports++;
+		base_5v_power_s5 += PWR_S5_REAR_LOW;
+	}
+	if (!gpio_get_level(GPIO_USB_A3_OC_ODL)) {
+		rear_ports++;
+		base_5v_power_s5 += PWR_S5_REAR_LOW;
+	}
+	/*
+	 * Only 1 rear port can run higher power at a time.
+	 */
+	if (rear_ports > 0)
+		base_5v_power_s5 += PWR_S5_REAR_HIGH - PWR_S5_REAR_LOW;
+	if (!gpio_get_level(GPIO_HDMI_CONN_OC_ODL))
+		base_5v_power_s5 += PWR_S5_HDMI;
+	base_5v_power_z1 = PWR_Z1_BASE_LOAD;
+	if (usbc_overcurrent)
+		base_5v_power_z1 += PWR_Z1_C_HIGH;
+	/*
+	 * Invoke the power handler immediately.
+	 */
+	hook_call_deferred(&power_monitor_data, 0);
+}
+DECLARE_DEFERRED(update_5v_usage);
+/*
+ * Start power monitoring after ADCs have been initialised.
+ */
+DECLARE_HOOK(HOOK_INIT, update_5v_usage, HOOK_PRIO_INIT_ADC + 1);
+
+static void port_ocp_interrupt(enum gpio_signal signal)
+{
+	hook_call_deferred(&update_5v_usage_data, 0);
+}
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/******************************************************************************/
+/*
+ * Barrel jack power supply handling
+ *
+ * EN_PPVAR_BJ_ADP_L must default active to ensure we can power on when the
+ * barrel jack is connected, and the USB-C port can bring the EC up fine in
+ * dead-battery mode. Both the USB-C and barrel jack switches do reverse
+ * protection, so we're safe to turn one on then the other off- but we should
+ * only do that if the system is off since it might still brown out.
+ */
+
+#define ADP_DEBOUNCE_MS 1000 /* Debounce time for BJ plug/unplug */
+/* Debounced connection state of the barrel jack */
+static int8_t adp_connected = -1;
+static void adp_connect_deferred(void)
+{
+	struct charge_port_info pi = { 0 };
+	int connected = !gpio_get_level(GPIO_BJ_ADP_PRESENT_ODL);
+
+	/* Debounce */
+	if (connected == adp_connected)
+		return;
+	if (connected)
+		ec_bj_power(&pi.voltage, &pi.current);
+	charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED,
+				     DEDICATED_CHARGE_PORT, &pi);
+	adp_connected = connected;
+}
+DECLARE_DEFERRED(adp_connect_deferred);
+
+/* IRQ for BJ plug/unplug. It shouldn't be called if BJ is the power source. */
+void adp_connect_interrupt(enum gpio_signal signal)
+{
+	hook_call_deferred(&adp_connect_deferred_data, ADP_DEBOUNCE_MS * MSEC);
+}
+
+static void adp_state_init(void)
+{
+	ASSERT(CHARGE_PORT_ENUM_COUNT == CHARGE_PORT_COUNT);
+	/*
+	 * Initialize all charge suppliers to 0. The charge manager waits until
+	 * all ports have reported in before doing anything.
+	 */
+	for (int i = 0; i < CHARGE_PORT_COUNT; i++) {
+		for (int j = 0; j < CHARGE_SUPPLIER_COUNT; j++)
+			charge_manager_update_charge(j, i, NULL);
+	}
+
+	/* Report charge state from the barrel jack. */
+	adp_connect_deferred();
+}
+DECLARE_HOOK(HOOK_INIT, adp_state_init, HOOK_PRIO_INIT_CHARGE_MANAGER + 1);
+
+static void board_init(void)
+{
+	gpio_enable_interrupt(GPIO_BJ_ADP_PRESENT_ODL);
+	gpio_enable_interrupt(GPIO_HDMI_CONN_OC_ODL);
+	gpio_enable_interrupt(GPIO_USB_A0_OC_ODL);
+	gpio_enable_interrupt(GPIO_USB_A1_OC_ODL);
+	gpio_enable_interrupt(GPIO_USB_A2_OC_ODL);
+	gpio_enable_interrupt(GPIO_USB_A3_OC_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+void board_overcurrent_event(int port, int is_overcurrented)
+{
+	/* Check that port number is valid. */
+	if ((port < 0) || (port >= CONFIG_USB_PD_PORT_MAX_COUNT))
+		return;
+	usbc_overcurrent = is_overcurrented;
+	update_5v_usage();
+}
+/*
+ * Power monitoring and management.
+ *
+ * the power budgets are met without letting the system fall into
+ * power deficit (perhaps causing a brownout).
+ *
+ * There are 2 power budgets that need to be managed:
+ * The overall goal is to gracefully manage the power demand so that
+ *  - overall system power as measured on the main power supply rail.
+ *  - 5V power delivered to the USB and HDMI ports.
+ *
+ * The actual system power demand is calculated from the VBUS voltage and
+ * the input current (read from a shunt), averaged over 5 readings.
+ * The power budget limit is from the charge manager.
+ *
+ * The 5V power cannot be read directly. Instead, we rely on overcurrent
+ * inputs from the USB and HDMI ports to indicate that the port is in use
+ * (and drawing maximum power).
+ *
+ * There are 3 throttles that can be applied (in priority order):
+ *
+ *  - Type A BC1.2 front port restriction (3W)
+ *  - Type A BC1.2 rear port restriction (3W)
+ *  - Type C PD (throttle to 1.5A if sourcing)
+ *  - Turn on PROCHOT, which immediately throttles the CPU.
+ *
+ *  The first 3 throttles affect both the system power and the 5V rails.
+ *  The third is a last resort to force an immediate CPU throttle to
+ *  reduce the overall power use.
+ *
+ *  The strategy is to determine what the state of the throttles should be,
+ *  and to then turn throttles off or on as needed to match this.
+ *
+ *  This function runs on demand, or every 2 ms when the CPU is up,
+ *  and continually monitors the power usage, applying the
+ *  throttles when necessary.
+ *
+ *  All measurements are in milliwatts.
+ */
+#define THROT_TYPE_A_FRONT BIT(0)
+#define THROT_TYPE_A_REAR BIT(1)
+#define THROT_TYPE_C0 BIT(2)
+#define THROT_TYPE_C1 BIT(3)
+#define THROT_TYPE_C2 BIT(4)
+#define THROT_PROCHOT BIT(5)
+
+/*
+ * Power gain if front USB A ports are limited.
+ */
+#define POWER_GAIN_TYPE_A 3200
+/*
+ * Power gain if Type C port is limited.
+ */
+#define POWER_GAIN_TYPE_C 8800
+/*
+ * Power is averaged over 10 ms, with a reading every 2 ms.
+ */
+#define POWER_DELAY_MS 2
+#define POWER_READINGS (10 / POWER_DELAY_MS)
+
+static void power_monitor(void)
+{
+	static uint32_t current_state;
+	static uint32_t history[POWER_READINGS];
+	static uint8_t index;
+	int32_t delay;
+	uint32_t new_state = 0, diff;
+	int32_t headroom_5v_s5 = PWR_S5_MAX - base_5v_power_s5;
+	int32_t headroom_5v_z1 = PWR_Z1_MAX - base_5v_power_z1;
+
+	/*
+	 * If CPU is off or suspended, no need to throttle
+	 * or restrict power.
+	 */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF | CHIPSET_STATE_SUSPEND)) {
+		/*
+		 * Slow down monitoring, assume no throttling required.
+		 */
+		delay = 20 * MSEC;
+		/*
+		 * Clear the first entry of the power table so that
+		 * it is re-initilalised when the CPU starts.
+		 */
+		history[0] = 0;
+	} else {
+		int32_t charger_mw;
+
+		delay = POWER_DELAY_MS * MSEC;
+		/*
+		 * Get current charger limit (in mw).
+		 * If not configured yet, skip.
+		 */
+		charger_mw = charge_manager_get_power_limit_uw() / 1000;
+		if (charger_mw != 0) {
+			int32_t gap, total, max, power;
+			int i;
+
+			/*
+			 * Read power usage.
+			 */
+			power = (adc_read_channel(ADC_VBUS) *
+				 adc_read_channel(ADC_PPVAR_IMON)) /
+				1000;
+			/* Init power table */
+			if (history[0] == 0) {
+				for (i = 0; i < POWER_READINGS; i++)
+					history[i] = power;
+			}
+			/*
+			 * Update the power readings and
+			 * calculate the average and max.
+			 */
+			history[index] = power;
+			index = (index + 1) % POWER_READINGS;
+			total = 0;
+			max = history[0];
+			for (i = 0; i < POWER_READINGS; i++) {
+				total += history[i];
+				if (history[i] > max)
+					max = history[i];
+			}
+			/*
+			 * For Type-C power supplies, there is
+			 * less tolerance for exceeding the rating,
+			 * so use the max power that has been measured
+			 * over the measuring period.
+			 * For barrel-jack supplies, the rating can be
+			 * exceeded briefly, so use the average.
+			 */
+			if (charge_manager_get_supplier() == CHARGE_SUPPLIER_PD)
+				power = max;
+			else
+				power = total / POWER_READINGS;
+			/*
+			 * Calculate gap, and if negative, power
+			 * demand is exceeding configured power budget, so
+			 * throttling is required to reduce the demand.
+			 */
+			gap = charger_mw - power;
+			/*
+			 * Limiting type-A power rear ports.
+			 */
+			if (gap <= 0) {
+				new_state |= THROT_TYPE_A_REAR;
+				headroom_5v_s5 += REAR_DELTA;
+				if (!(current_state & THROT_TYPE_A_REAR))
+					gap += POWER_GAIN_TYPE_A;
+			}
+			/*
+			 * Limiting type-A power front ports.
+			 */
+			if (gap <= 0) {
+				new_state |= THROT_TYPE_A_FRONT;
+				headroom_5v_s5 += FRONT_DELTA;
+				if (!(current_state & THROT_TYPE_A_REAR))
+					gap += POWER_GAIN_TYPE_A;
+			}
+			/*
+			 * If the type-C port is sourcing power,
+			 * check whether it should be throttled.
+			 */
+			if (ppc_is_sourcing_vbus(0) && gap <= 0) {
+				new_state |= THROT_TYPE_C0;
+				headroom_5v_z1 += PWR_Z1_C_HIGH - PWR_Z1_C_LOW;
+				if (!(current_state & THROT_TYPE_C0))
+					gap += POWER_GAIN_TYPE_C;
+			}
+			/*
+			 * As a last resort, turn on PROCHOT to
+			 * throttle the CPU.
+			 */
+			if (gap <= 0)
+				new_state |= THROT_PROCHOT;
+		}
+	}
+	/*
+	 * Check the 5v power usage and if necessary,
+	 * adjust the throttles in priority order.
+	 *
+	 * Either throttle may have already been activated by
+	 * the overall power control.
+	 *
+	 * We rely on the overcurrent detection to inform us
+	 * if the port is in use.
+	 *
+	 *  - If type C not already throttled:
+	 *	* If not overcurrent, prefer to limit type C [1].
+	 *	* If in overcurrentuse:
+	 *		- limit type A first [2]
+	 *		- If necessary, limit type C [3].
+	 *  - If type A not throttled, if necessary limit it [2].
+	 */
+	if (headroom_5v_z1 < 0) {
+		/*
+		 * Check whether type C is not throttled,
+		 * and is not overcurrent.
+		 */
+		if (!((new_state & THROT_TYPE_C0) || usbc_overcurrent)) {
+			/*
+			 * [1] Type C not in overcurrent, throttle it.
+			 */
+			headroom_5v_z1 += PWR_Z1_C_HIGH - PWR_Z1_C_LOW;
+			new_state |= THROT_TYPE_C0;
+		}
+		/*
+		 * [2] If still under-budget, limit type C.
+		 * No need to check if it is already throttled or not.
+		 */
+		if (headroom_5v_z1 < 0)
+			new_state |= THROT_TYPE_C0;
+	}
+	if (headroom_5v_s5 < 0) {
+		/*
+		 * [1] If type A rear not already throttled, and power still
+		 * needed, limit type A rear.
+		 */
+		if (!(new_state & THROT_TYPE_A_REAR) && headroom_5v_s5 < 0) {
+			headroom_5v_s5 += PWR_S5_REAR_HIGH - PWR_S5_REAR_LOW;
+			new_state |= THROT_TYPE_A_REAR;
+		}
+		/*
+		 * [2] If type A front not already throttled, and power still
+		 * needed, limit type A front.
+		 */
+		if (!(new_state & THROT_TYPE_A_FRONT) && headroom_5v_s5 < 0) {
+			headroom_5v_s5 += PWR_S5_FRONT_HIGH - PWR_S5_FRONT_LOW;
+			new_state |= THROT_TYPE_A_FRONT;
+		}
+	}
+	/*
+	 * Turn the throttles on or off if they have changed.
+	 */
+	diff = new_state ^ current_state;
+	current_state = new_state;
+	if (diff & THROT_PROCHOT) {
+		int prochot = (new_state & THROT_PROCHOT) ? 0 : 1;
+
+		gpio_set_level(GPIO_EC_PROCHOT_ODL, prochot);
+	}
+	if (diff & THROT_TYPE_C0) {
+		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C0) ?
+						TYPEC_RP_1A5 :
+						TYPEC_RP_3A0;
+
+		ppc_set_vbus_source_current_limit(0, rp);
+		tcpm_select_rp_value(0, rp);
+		pd_update_contract(0);
+	}
+	if (diff & THROT_TYPE_C1) {
+		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C1) ?
+						TYPEC_RP_1A5 :
+						TYPEC_RP_3A0;
+
+		ppc_set_vbus_source_current_limit(1, rp);
+		tcpm_select_rp_value(1, rp);
+		pd_update_contract(1);
+	}
+	if (diff & THROT_TYPE_C2) {
+		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C2) ?
+						TYPEC_RP_1A5 :
+						TYPEC_RP_3A0;
+
+		ppc_set_vbus_source_current_limit(2, rp);
+		tcpm_select_rp_value(2, rp);
+		pd_update_contract(2);
+	}
+	if (diff & THROT_TYPE_A_REAR) {
+		int typea_bc = (new_state & THROT_TYPE_A_REAR) ? 1 : 0;
+
+		gpio_set_level(GPIO_USB_A_LOW_PWR0_OD, typea_bc);
+		gpio_set_level(GPIO_USB_A_LOW_PWR1_OD, typea_bc);
+	}
+	if (diff & THROT_TYPE_A_FRONT) {
+		int typea_bc = (new_state & THROT_TYPE_A_FRONT) ? 1 : 0;
+
+		gpio_set_level(GPIO_USB_A_LOW_PWR2_OD, typea_bc);
+	}
+	hook_call_deferred(&power_monitor_data, delay);
+}
diff --git a/board/kuldax/board.h b/board/kuldax/board.h
new file mode 100644
index 0000000000..1665815114
--- /dev/null
+++ b/board/kuldax/board.h
@@ -0,0 +1,199 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Brask board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "compile_time_macros.h"
+
+/* Baseboard features */
+#include "baseboard.h"
+
+/* Disable console commands to help save space */
+#undef CONFIG_CMD_POWERINDEBUG
+
+#define CONFIG_MP2964
+
+/* Barrel Jack */
+#define DEDICATED_CHARGE_PORT 1
+
+/* HDMI CEC */
+#define CONFIG_CEC
+#define CONFIG_CEC_BITBANG
+#define CEC_GPIO_OUT GPIO_HDMI_CEC_OUT
+#define CEC_GPIO_IN GPIO_HDMI_CEC_IN
+#define CEC_GPIO_PULL_UP GPIO_HDMI_CEC_PULL_UP
+
+/* USB Type A Features */
+#define USB_PORT_COUNT 4
+#define CONFIG_USB_PORT_POWER_DUMB
+
+/* USB Type C and USB PD defines */
+#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
+
+#define CONFIG_USB_PD_PPC
+#define CONFIG_USB_PD_TCPM_RT1715
+#define CONFIG_USBC_RETIMER_INTEL_BB
+
+#define CONFIG_USBC_PPC_SYV682X
+#undef CONFIG_SYV682X_HV_ILIM
+#define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_5_50
+
+/* TODO: b/177608416 - measure and check these values on brya */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
+
+/* The design should support up to 100W. */
+/* TODO(b/197702356): Set the max PD to 60W now and change it
+ * to 100W after we verify it.
+ */
+#define PD_OPERATING_POWER_MW CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
+#define PD_MAX_POWER_MW 100000
+#define PD_MAX_CURRENT_MA 5000
+#define PD_MAX_VOLTAGE_MV 20000
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
+
+/*
+ * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
+ * signal.
+ */
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
+#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_OD
+#define GPIO_RECOVERY_L_2 GPIO_GSC_EC_RECOVERY_BTN_OD
+
+/* I2C Bus Configuration */
+
+#define I2C_PORT_DP_REDRIVER NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0_C2_TCPC NPCX_I2C_PORT1_0
+
+#define I2C_PORT_USB_C0_C2_PPC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1
+
+#define I2C_PORT_USB_C0_C2_BC12 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1
+
+#define I2C_PORT_USB_C0_C2_MUX NPCX_I2C_PORT3_0
+#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1
+
+#define I2C_PORT_QI NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+
+#define I2C_ADDR_MP2964_FLAGS 0x20
+
+#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x58
+#define USBC_PORT_C2_BB_RETIMER_I2C_ADDR 0x59
+
+/* Enabling Thunderbolt-compatible mode */
+#define CONFIG_USB_PD_TBT_COMPAT_MODE
+
+/* Enabling USB4 mode */
+#define CONFIG_USB_PD_USB4
+#define CONFIG_USB_PD_DATA_RESET_MSG
+
+/* Retimer */
+#define CONFIG_USBC_RETIMER_FW_UPDATE
+
+/* Thermal features */
+#define CONFIG_THERMISTOR
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_TEMP_SENSOR_POWER
+#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
+
+/* ADC */
+#define CONFIG_ADC
+
+/*
+ * TODO(b/197478860): Enable the fan control. We need
+ * to check the sensor value and adjust the fan speed.
+ */
+#define CONFIG_FANS FAN_CH_COUNT
+
+/* Include math_util for bitmask_uint64 used in pd_timers */
+#define CONFIG_MATH_UTIL
+
+/* WPC/Qi charger */
+#ifdef SECTION_IS_RW
+#define CONFIG_PERIPHERAL_CHARGER
+#define CONFIG_CPS8100
+#define CONFIG_SW_CRC
+#endif
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h" /* needed by registers.h */
+#include "registers.h"
+#include "usbc_config.h"
+
+enum charge_port {
+	CHARGE_PORT_TYPEC0,
+	CHARGE_PORT_BARRELJACK,
+	CHARGE_PORT_ENUM_COUNT
+};
+
+enum adc_channel {
+	ADC_TEMP_SENSOR_1_CPU,
+	ADC_TEMP_SENSOR_2_CPU_VR,
+	ADC_TEMP_SENSOR_3_WIFI,
+	ADC_TEMP_SENSOR_4_DIMM,
+	ADC_VBUS,
+	ADC_PPVAR_IMON, /* ADC3 */
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1_CPU,
+	TEMP_SENSOR_2_CPU_VR,
+	TEMP_SENSOR_3_WIFI,
+	TEMP_SENSOR_4_DIMM,
+	TEMP_SENSOR_COUNT
+};
+
+enum pwm_channel {
+	PWM_CH_LED_WHITE, /* PWM0 */
+	PWM_CH_FAN, /* PWM5 */
+	PWM_CH_LED_RED, /* PWM2 */
+	PWM_CH_COUNT
+};
+
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT };
+
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT };
+
+enum cec_port { CEC_PORT_0, CEC_PORT_COUNT };
+
+extern void adp_connect_interrupt(enum gpio_signal signal);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/kuldax/build.mk b/board/kuldax/build.mk
new file mode 100644
index 0000000000..3de758d1bd
--- /dev/null
+++ b/board/kuldax/build.mk
@@ -0,0 +1,22 @@
+# -*- makefile -*-
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Brask board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx9
+CHIP_VARIANT:=npcx9m3f
+BASEBOARD:=brask
+
+board-y=
+board-y+=board.o
+board-y+=fans.o
+board-y+=fw_config.o
+board-y+=i2c.o
+board-y+=led.o
+board-y+=pwm.o
+board-y+=sensors.o
+board-y+=usbc_config.o
diff --git a/board/kuldax/ec.tasklist b/board/kuldax/ec.tasklist
new file mode 100644
index 0000000000..23218133a8
--- /dev/null
+++ b/board/kuldax/ec.tasklist
@@ -0,0 +1,26 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ *
+ * USB_CHG_Px tasks must be contiguous (see USB_CHG_PORT_TO_TASK_ID(x)).
+ * PD_Cx tasks must be contiguous (see PD_PORT_TO_TASK_ID(x))
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS_RW(PCHG, pchg_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P2, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CEC, cec_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/kuldax/fans.c b/board/kuldax/fans.c
new file mode 100644
index 0000000000..6e3740a894
--- /dev/null
+++ b/board/kuldax/fans.c
@@ -0,0 +1,50 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Physical fans. These are logically separate from pwm_channels. */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "fan.h"
+#include "fan_chip.h"
+#include "hooks.h"
+#include "pwm.h"
+
+/* MFT channels. These are logically separate from pwm_channels. */
+const struct mft_t mft_channels[] = {
+	[MFT_CH_0] = {
+		.module = NPCX_MFT_MODULE_2,
+		.clk_src = TCKC_LFCLK,
+		.pwm_id = PWM_CH_FAN,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
+
+static const struct fan_conf fan_conf_0 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
+	.pgood_gpio = -1,
+	.enable_gpio = GPIO_EN_PP5000_FAN,
+};
+
+/*
+ * TOOD(b/197478860): need to update for real fan
+ *
+ * Prototype fan spins at about 7200 RPM at 100% PWM.
+ * Set minimum at around 30% PWM.
+ */
+static const struct fan_rpm fan_rpm_0 = {
+	.rpm_min = 2400,
+	.rpm_start = 2400,
+	.rpm_max = 4500,
+};
+
+const struct fan_t fans[FAN_CH_COUNT] = {
+	[FAN_CH_0] = {
+		.conf = &fan_conf_0,
+		.rpm = &fan_rpm_0,
+	},
+};
diff --git a/board/kuldax/fw_config.c b/board/kuldax/fw_config.c
new file mode 100644
index 0000000000..7f0204f667
--- /dev/null
+++ b/board/kuldax/fw_config.c
@@ -0,0 +1,78 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "fw_config.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+static union brask_cbi_fw_config fw_config;
+BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
+
+/*
+ * FW_CONFIG defaults for brask if the CBI.FW_CONFIG data is not
+ * initialized.
+ */
+static const union brask_cbi_fw_config fw_config_defaults = {
+	.audio = DB_NAU88L25B_I2S,
+	.bj_power = BJ_135W,
+};
+
+/*
+ * Barrel-jack power adapter ratings.
+ */
+static const struct {
+	int voltage;
+	int current;
+} bj_power[] = {
+	[BJ_150W] = { /* 0 - 150W (also default)*/
+			.voltage = 20000,
+			.current = 7500
+	},
+	[BJ_230W] = { /* 1 - 230W */
+			.voltage = 19500,
+			.current = 11800
+	},
+	[BJ_65W] = { /* 2 - 65W */
+			.voltage = 19000,
+			.current = 3420
+	},
+	[BJ_135W] = { /* 4 - 135W */
+			.voltage = 19500,
+			.current = 6920
+	}
+};
+
+/****************************************************************************
+ * Brask FW_CONFIG access
+ */
+void board_init_fw_config(void)
+{
+	if (cbi_get_fw_config(&fw_config.raw_value)) {
+		CPRINTS("CBI: Read FW_CONFIG failed, using board defaults");
+		fw_config = fw_config_defaults;
+	}
+}
+
+void ec_bj_power(uint32_t *voltage, uint32_t *current)
+{
+	unsigned int bj;
+
+	bj = fw_config.bj_power;
+	/* Out of range value defaults to 0 */
+	if (bj >= ARRAY_SIZE(bj_power))
+		bj = 0;
+	*voltage = bj_power[bj].voltage;
+	*current = bj_power[bj].current;
+}
+
+bool ec_cfg_has_peripheral_charger(void)
+{
+	return (fw_config.peripheral_charger == PERIPHERAL_CHARGER_ENABLE);
+}
diff --git a/board/kuldax/fw_config.h b/board/kuldax/fw_config.h
new file mode 100644
index 0000000000..cdba1b16d7
--- /dev/null
+++ b/board/kuldax/fw_config.h
@@ -0,0 +1,55 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __BOARD_BRASK_FW_CONFIG_H_
+#define __BOARD_BRASK_FW_CONFIG_H_
+
+#include <stdint.h>
+
+/****************************************************************************
+ * CBI FW_CONFIG layout for Brask board.
+ *
+ * Source of truth is the project/brask/brask/config.star configuration file.
+ */
+enum ec_cfg_audio_type { DB_AUDIO_UNKNOWN = 0, DB_NAU88L25B_I2S = 1 };
+
+enum ec_cfg_bj_power { BJ_150W = 0, BJ_230W = 1, BJ_65W = 2, BJ_135W = 3 };
+
+/*
+ * Peripheral charger  (Bits 5)
+ */
+enum ec_cfg_peripheral_charger {
+	PERIPHERAL_CHARGER_ENABLE = 0,
+	PERIPHERAL_CHARGER_DISABLE = 1
+};
+
+union brask_cbi_fw_config {
+	struct {
+		uint32_t audio : 3;
+		uint32_t bj_power : 2;
+		uint32_t peripheral_charger : 1;
+		uint32_t reserved_1 : 26;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Read the cached FW_CONFIG.  Guaranteed to have valid values.
+ *
+ * @return the FW_CONFIG for the board.
+ */
+union brask_cbi_fw_config get_fw_config(void);
+
+/**
+ * Get the barrel-jack power from FW_CONFIG.
+ */
+void ec_bj_power(uint32_t *voltage, uint32_t *current);
+
+/**
+ * SWITCH the peripheral charger function enable/disable from FW_CONFIG.
+ */
+bool ec_cfg_has_peripheral_charger(void);
+
+#endif /* __BOARD_BRASK_FW_CONFIG_H_ */
diff --git a/board/kuldax/gpio.inc b/board/kuldax/gpio.inc
new file mode 100644
index 0000000000..253d9b7fc3
--- /dev/null
+++ b/board/kuldax/gpio.inc
@@ -0,0 +1,172 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* INTERRUPT GPIOs: */
+
+GPIO_INT(ACOK_OD,                    PIN(0, 0), GPIO_INT_BOTH, extpower_interrupt)
+GPIO_INT(EC_PROCHOT_IN_L,            PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
+GPIO_INT(EC_WP_ODL,                  PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(GSC_EC_PWR_BTN_ODL,         PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
+GPIO_INT(SEQ_EC_ALL_SYS_PG,          PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_DSW_PWROK,           PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_RSMRST_ODL,          PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,                   PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,                  PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SYS_SLP_S0IX_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(USB_C0_BC12_INT_ODL,        PIN(C, 6), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C0_C2_TCPC_INT_ODL,     PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C0_PPC_INT_ODL,         PIN(6, 2), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C0_RT_INT_ODL,          PIN(B, 1), GPIO_INT_FALLING, retimer_interrupt)
+GPIO_INT(BJ_ADP_PRESENT_ODL,         PIN(8, 2), GPIO_INT_BOTH | GPIO_PULL_UP, adp_connect_interrupt)
+GPIO_INT(EC_RECOVERY_BTN_OD,         PIN(2, 3), GPIO_INT_BOTH, button_interrupt)
+GPIO_INT(HDMI_CONN_OC_ODL,           PIN(2, 4), GPIO_INPUT | GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(USB_A0_OC_ODL,              PIN(3, 1), GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(USB_A1_OC_ODL,              PIN(3, 0), GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(USB_A2_OC_ODL,              PIN(2, 7), GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(USB_A3_OC_ODL,              PIN(2, 6), GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH, port_ocp_interrupt)
+#ifdef SECTION_IS_RW
+GPIO_INT(QI_INT_ODL,                 PIN(9, 6), GPIO_INT_FALLING, pchg_irq)
+#else
+UNIMPLEMENTED(QI_INT_ODL)
+#endif
+
+/* CCD */
+GPIO(CCD_MODE_ODL,                   PIN(E, 5), GPIO_INPUT)
+
+/* Security */
+GPIO(EC_ENTERING_RW,                 PIN(0, 3), GPIO_OUT_LOW)
+GPIO(EC_GSC_PACKET_MODE,             PIN(7, 5), GPIO_OUT_LOW)
+
+/* Fan */
+GPIO(EN_PP5000_FAN,                  PIN(6, 1), GPIO_OUT_HIGH)
+
+/* ADC, need to check the usage */
+GPIO(ANALOG_PPVAR_PWR_IN_IMON_EC,    PIN(4, 2), GPIO_INPUT)
+
+/* Display */
+GPIO(DP_CONN_OC_ODL,                 PIN(2, 5), GPIO_INPUT)
+
+
+/* BarrelJack */
+GPIO(EN_PPVAR_BJ_ADP_L,              PIN(0, 7), GPIO_OUT_LOW)
+
+/* Chipset PCH */
+GPIO(EC_PCHHOT_ODL,                  PIN(7, 4), GPIO_INPUT)
+GPIO(EC_PCH_INT_ODL,                 PIN(B, 0), GPIO_ODR_HIGH)
+GPIO(EC_PCH_RSMRST_L,                PIN(A, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_RTCRST,                  PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_SYS_PWROK,               PIN(3, 7), GPIO_OUT_LOW)
+GPIO(EC_PCH_WAKE_ODL,                PIN(C, 0), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_ODL,                 PIN(6, 3), GPIO_ODR_HIGH)
+GPIO(EN_S5_RAILS,                    PIN(B, 6), GPIO_OUT_LOW)
+GPIO(PCH_PWROK,                      PIN(7, 2), GPIO_OUT_LOW)
+GPIO(SYS_RST_ODL,                    PIN(C, 5), GPIO_ODR_HIGH)
+GPIO(VCCST_PWRGD_OD,                 PIN(A, 4), GPIO_ODR_LOW)
+GPIO(IMVP9_VRRDY_OD,                 PIN(6, 0), GPIO_INPUT)
+GPIO(CPU_C10_GATE_L,                 PIN(6, 7), GPIO_INPUT)
+
+/* Button */
+GPIO(EC_PCH_PWR_BTN_ODL,             PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(GSC_EC_RECOVERY_BTN_OD,         PIN(2, 2), GPIO_INPUT)
+
+/* Wireless Charger */
+GPIO(EC_QI_PWR,                      PIN(D, 2), GPIO_OUT_LOW)
+GPIO(QI_RESET_L,                     PIN(9, 3), GPIO_OUT_HIGH)
+
+/* HDMI CEC */
+/* TODO(b/197474873): Enable HDMI CEC */
+GPIO(HDMI_CEC_IN,                    PIN(4, 0), GPIO_INPUT)
+GPIO(HDMI_CEC_OUT,                   PIN(D, 3), GPIO_OUT_HIGH | GPIO_OPEN_DRAIN)
+GPIO(HDMI_CEC_PULL_UP,               PIN(C, 2), GPIO_OUT_HIGH)
+
+/* I2C SCL/SDA */
+GPIO(EC_I2C_QI_SCL,                  PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_QI_SDA,                  PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SCL_R,              PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SDA_R,              PIN(B, 2), GPIO_INPUT)
+GPIO(EC_I2C_DP_SCL,                  PIN(B, 5), GPIO_INPUT)
+GPIO(EC_I2C_DP_SDA,                  PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_PPC_SCL,       PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_PPC_SDA,       PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_RT_SCL,        PIN(D, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_RT_SDA,        PIN(D, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_TCPC_SCL,      PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_TCPC_SDA,      PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_MIX_SCL,          PIN(E, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_MIX_SDA,          PIN(E, 3), GPIO_INPUT)
+
+/* USBA */
+GPIO(EN_PP5000_USBA,                 PIN(D, 7), GPIO_OUT_LOW)
+GPIO(USB_A0_STATUS_L,                PIN(2, 1), GPIO_INPUT)
+GPIO(USB_A1_STATUS_L,                PIN(2, 0), GPIO_INPUT)
+GPIO(USB_A_LOW_PWR0_OD,              PIN(1, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(USB_A_LOW_PWR1_OD,              PIN(1, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(USB_A_LOW_PWR2_OD,              PIN(1, 1), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(USB_A_OC_SOC_L,                 PIN(8, 0), GPIO_OUT_HIGH)
+
+/* LED */
+/* TODO(b/197471359): LED implementation */
+GPIO(LED_GREEN_L,                    PIN(C, 3), GPIO_OUT_LOW)
+GPIO(LED_RED_L,                      PIN(C, 4), GPIO_OUT_LOW)
+
+/* USBC */
+GPIO(USB_C0_FRS_EN,                  PIN(A, 3), GPIO_OUT_LOW)
+GPIO(USB_C1_RT_INT_ODL,              PIN(A, 0), GPIO_INPUT)
+GPIO(USB_C0_RT_RST_ODL,              PIN(9, 5), GPIO_ODR_LOW)
+
+/* UART alternate functions */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)              /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */
+
+/* I2C alternate functions */
+ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)               /* GPIO33/I2C5_SCL0/CTS_L, GPIO36/RTS_L/I2C5_SDA0 */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)               /* GPIO87/I2C1_SDA0 */
+ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)               /* GPIO92/I2C2_SCL0, GPIO91/I2C2_SDA0, GPIO90/I2C1_SCL0 */
+ALTERNATE(PIN_MASK(B, 0x0c), 0, MODULE_I2C, 0)               /* GPIOB3/I2C7_SCL0/DCD_L, GPIOB2/I2C7_SDA0/DSR_L */
+ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, 0)               /* GPIOB5/I2C0_SCL0, GPIOB4/I2C0_SDA0 */
+ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)               /* GPIOD1/I2C3_SCL0, GPIOD0/I2C3_SDA0 */
+ALTERNATE(PIN_MASK(E, 0x18), 0, MODULE_I2C, 0)               /* GPIOE4/I2C6_SCL1/I3C_SCL, GPIOE3/I2C6_SDA1/I3C_SDA */
+ALTERNATE(PIN_MASK(F, 0x0c), 0, MODULE_I2C, 0)               /* GPIOF3/I2C4_SCL1, GPIOF2/I2C4_SDA1 */
+
+/* PWM alternate functions */
+ALTERNATE(PIN_MASK(7, 0x08), 0, MODULE_PWM, 0)               /* GPIO73/TA2 */
+ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)               /* GPIOB7/PWM5 */
+ALTERNATE(PIN_MASK(C, 0x18), 0, MODULE_PWM, 0)               /* GPIOC4/PWM2, GPIOC3/PWM0 */
+
+/* ADC alternate functions */
+ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0)               /* GPIO34/PS2_DAT2/ADC6 */
+ALTERNATE(PIN_MASK(4, 0x38), 0, MODULE_ADC, 0)               /* GPIO45/ADC0, GPIO44/ADC1, GPIO43/ADC2 */
+ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0)               /* GPIOE1/ADC7 */
+
+/* Unused Pins */
+UNUSED(PIN(0, 2))       /* GPIO02/PSL_IN4 */
+UNUSED(PIN(0, 4))       /* KSO13/GPIO04 */
+UNUSED(PIN(0, 5))       /* KSO13/GPIO05 */
+UNUSED(PIN(0, 6))       /* KSO11/GPIO06/P80_CLK */
+UNUSED(PIN(1, 0))       /* KSO9/GPIO10/CR_SIN1 */
+UNUSED(PIN(1, 2))       /* KSO07/GPO12/JEN# */
+UNUSED(PIN(1, 3))       /* KSO06/GPO13/GP_SEL# */
+UNUSED(PIN(1, 6))       /* KSO3/GPIO16 */
+UNUSED(PIN(1, 7))       /* KSO2/GPIO17/JTAG_TDI */
+UNUSED(PIN(3, 2))       /* GPO32/TRIS_L */
+UNUSED(PIN(3, 5))       /* GPO35/CR_SOUT4/TEST_L */
+UNUSED(PIN(4, 1))       /* GPIO41/ADC4 */
+UNUSED(PIN(5, 0))       /* GPIO50 */
+UNUSED(PIN(5, 6))       /* GPIO56/CLKRUN# */
+UNUSED(PIN(6, 6))       /* GPIO66 */
+UNUSED(PIN(7, 0))       /* GPIO70/PS2_DAT0*/
+UNUSED(PIN(8, 1))       /* GPIO81/PECI_DATA */
+UNUSED(PIN(8, 3))       /* KSO15/GPIO83 */
+UNUSED(PIN(8, 6))       /* GPIO86/TXD/CR_SOUT2 */
+UNUSED(PIN(9, 7))       /* GPIO97 */
+UNUSED(PIN(9, 4))       /* GPIO94*/
+UNUSED(PIN(A, 2))       /* F_SCLK/GPIOA2 */
+UNUSED(PIN(A, 7))       /* GPIOA7 */
+UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
+UNUSED(PIN(D, 4))       /* GPIOD4/CR_SIN3 */
+UNUSED(PIN(F, 2))       /* GPIOF2/I2C4_SDA1*/
+UNUSED(PIN(F, 3))       /* GPIOF3/I2C4_SCL1*/
+UNUSED(PIN(F, 5))       /* GPIOF5/I2C5_SCL1*/
diff --git a/board/kuldax/i2c.c b/board/kuldax/i2c.c
new file mode 100644
index 0000000000..e7868b4b08
--- /dev/null
+++ b/board/kuldax/i2c.c
@@ -0,0 +1,69 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "i2c.h"
+
+/* I2C port map configuration */
+const struct i2c_port_t i2c_ports[] = {
+	{
+		/* I2C0 */
+		.name = "dp_redriver",
+		.port = I2C_PORT_DP_REDRIVER,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_DP_SCL,
+		.sda = GPIO_EC_I2C_DP_SDA,
+	},
+	{
+		/* I2C1 */
+		.name = "tcpc0,2",
+		.port = I2C_PORT_USB_C0_C2_TCPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C2_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C2_TCPC_SDA,
+	},
+	{
+		/* I2C2 */
+		.name = "ppc0,2",
+		.port = I2C_PORT_USB_C0_C2_PPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C2_PPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C2_PPC_SDA,
+	},
+	{
+		/* I2C3 */
+		.name = "retimer0,2",
+		.port = I2C_PORT_USB_C0_C2_MUX,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C2_RT_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C2_RT_SDA,
+	},
+	{
+		/* I2C5 */
+		.name = "wireless_charger",
+		.port = I2C_PORT_QI,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_QI_SCL,
+		.sda = GPIO_EC_I2C_QI_SDA,
+	},
+	{
+		/* I2C6 */
+		.name = "ppc1",
+		.port = I2C_PORT_USB_C1_PPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C1_MIX_SCL,
+		.sda = GPIO_EC_I2C_USB_C1_MIX_SDA,
+	},
+	{
+		/* I2C7 */
+		.name = "eeprom",
+		.port = I2C_PORT_EEPROM,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_MISC_SCL_R,
+		.sda = GPIO_EC_I2C_MISC_SDA_R,
+	},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/board/kuldax/led.c b/board/kuldax/led.c
new file mode 100644
index 0000000000..2fabc26a9a
--- /dev/null
+++ b/board/kuldax/led.c
@@ -0,0 +1,270 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power LED control for Brask.
+ * Solid white - active power
+ * White flashing - suspended
+ * Red flashing - alert
+ * Solid red - critical
+ */
+
+#include "chipset.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "led_common.h"
+#include "pwm.h"
+#include "timer.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
+
+/*
+ * Due to the CSME-Lite processing, upon startup the CPU transitions through
+ * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so
+ * delay turning off the LED during suspend/shutdown.
+ */
+#define LED_CPU_DELAY_MS (2000 * MSEC)
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED };
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+enum led_color {
+	LED_OFF = 0,
+	LED_RED,
+	LED_WHITE,
+
+	/* Number of colors, not a color itself */
+	LED_COLOR_COUNT
+};
+
+static int set_color_power(enum led_color color, int duty)
+{
+	int white = 0;
+	int red = 0;
+
+	if (duty < 0 || 100 < duty)
+		return EC_ERROR_UNKNOWN;
+
+	switch (color) {
+	case LED_OFF:
+		break;
+	case LED_WHITE:
+		white = 1;
+		break;
+	case LED_RED:
+		red = 1;
+		break;
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+
+	if (red)
+		pwm_set_duty(PWM_CH_LED_RED, duty);
+	else
+		pwm_set_duty(PWM_CH_LED_RED, 0);
+
+	if (white)
+		pwm_set_duty(PWM_CH_LED_WHITE, duty);
+	else
+		pwm_set_duty(PWM_CH_LED_WHITE, 0);
+
+	return EC_SUCCESS;
+}
+
+static int set_color(enum ec_led_id id, enum led_color color, int duty)
+{
+	switch (id) {
+	case EC_LED_ID_POWER_LED:
+		return set_color_power(color, duty);
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+}
+
+#define LED_PULSE_US (2 * SECOND)
+/* 40 msec for nice and smooth transition. */
+#define LED_PULSE_TICK_US (40 * MSEC)
+
+/*
+ * When pulsing is enabled, brightness is incremented by <duty_inc> every
+ * <interval> usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented
+ * likewise in LED_PULSE_US usec.
+ */
+static struct {
+	uint32_t interval;
+	int duty_inc;
+	enum led_color color;
+	int duty;
+} led_pulse;
+
+#define CONFIG_TICK(interval, color) \
+	config_tick((interval), 100 / (LED_PULSE_US / (interval)), (color))
+
+static void config_tick(uint32_t interval, int duty_inc, enum led_color color)
+{
+	led_pulse.interval = interval;
+	led_pulse.duty_inc = duty_inc;
+	led_pulse.color = color;
+	led_pulse.duty = 0;
+}
+
+static void pulse_power_led(enum led_color color)
+{
+	set_color(EC_LED_ID_POWER_LED, color, led_pulse.duty);
+	if (led_pulse.duty + led_pulse.duty_inc > 100)
+		led_pulse.duty_inc = led_pulse.duty_inc * -1;
+	else if (led_pulse.duty + led_pulse.duty_inc < 0)
+		led_pulse.duty_inc = led_pulse.duty_inc * -1;
+	led_pulse.duty += led_pulse.duty_inc;
+}
+
+static void led_tick(void);
+DECLARE_DEFERRED(led_tick);
+static void led_tick(void)
+{
+	uint32_t elapsed;
+	uint32_t next = 0;
+	uint32_t start = get_time().le.lo;
+
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		pulse_power_led(led_pulse.color);
+	elapsed = get_time().le.lo - start;
+	next = led_pulse.interval > elapsed ? led_pulse.interval - elapsed : 0;
+	hook_call_deferred(&led_tick_data, next);
+}
+
+static void led_suspend(void)
+{
+	CONFIG_TICK(LED_PULSE_TICK_US, LED_WHITE);
+	led_tick();
+}
+DECLARE_DEFERRED(led_suspend);
+
+static void led_shutdown(void)
+{
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_OFF, 0);
+}
+DECLARE_DEFERRED(led_shutdown);
+
+static void led_shutdown_hook(void)
+{
+	hook_call_deferred(&led_tick_data, -1);
+	hook_call_deferred(&led_suspend_data, -1);
+	hook_call_deferred(&led_shutdown_data, LED_CPU_DELAY_MS);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, led_shutdown_hook, HOOK_PRIO_DEFAULT);
+
+static void led_suspend_hook(void)
+{
+	hook_call_deferred(&led_shutdown_data, -1);
+	hook_call_deferred(&led_suspend_data, LED_CPU_DELAY_MS);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, led_suspend_hook, HOOK_PRIO_DEFAULT);
+
+static void led_resume(void)
+{
+	/*
+	 * Assume there is no race condition with led_tick, which also
+	 * runs in hook_task.
+	 */
+	hook_call_deferred(&led_tick_data, -1);
+	/*
+	 * Avoid invoking the suspend/shutdown delayed hooks.
+	 */
+	hook_call_deferred(&led_suspend_data, -1);
+	hook_call_deferred(&led_shutdown_data, -1);
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_WHITE, 100);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, led_resume, HOOK_PRIO_DEFAULT);
+
+void board_led_auto_control(void)
+{
+	if (chipset_in_state(CHIPSET_STATE_ON))
+		led_resume();
+	else if (chipset_in_state(CHIPSET_STATE_SUSPEND))
+		led_suspend_hook();
+	else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		led_shutdown_hook();
+}
+
+void led_alert(int enable)
+{
+	if (enable) {
+		/* Overwrite the current signal */
+		config_tick(1 * SECOND, 100, LED_RED);
+		led_tick();
+	} else {
+		/* Restore the previous signal */
+		if (chipset_in_state(CHIPSET_STATE_ON))
+			led_resume();
+		else if (chipset_in_state(CHIPSET_STATE_SUSPEND))
+			led_suspend_hook();
+		else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+			led_shutdown_hook();
+	}
+}
+
+void show_critical_error(void)
+{
+	hook_call_deferred(&led_tick_data, -1);
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_RED, 100);
+}
+
+static int command_led(int argc, const char **argv)
+{
+	enum ec_led_id id = EC_LED_ID_POWER_LED;
+
+	if (argc < 2)
+		return EC_ERROR_PARAM_COUNT;
+
+	if (!strcasecmp(argv[1], "debug")) {
+		led_auto_control(id, !led_auto_control_is_enabled(id));
+		ccprintf("o%s\n", led_auto_control_is_enabled(id) ? "ff" : "n");
+	} else if (!strcasecmp(argv[1], "off")) {
+		set_color(id, LED_OFF, 0);
+	} else if (!strcasecmp(argv[1], "red")) {
+		set_color(id, LED_RED, 100);
+	} else if (!strcasecmp(argv[1], "white")) {
+		set_color(id, LED_WHITE, 100);
+	} else if (!strcasecmp(argv[1], "alert")) {
+		led_alert(1);
+	} else if (!strcasecmp(argv[1], "crit")) {
+		show_critical_error();
+	} else {
+		return EC_ERROR_PARAM1;
+	}
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(led, command_led, "[debug|red|white|off|alert|crit]",
+			"Turn on/off LED.");
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	brightness_range[EC_LED_COLOR_RED] = 100;
+	brightness_range[EC_LED_COLOR_WHITE] = 100;
+}
+
+int led_set_brightness(enum ec_led_id id, const uint8_t *brightness)
+{
+	if (brightness[EC_LED_COLOR_RED])
+		return set_color(id, LED_RED, brightness[EC_LED_COLOR_RED]);
+	else if (brightness[EC_LED_COLOR_WHITE])
+		return set_color(id, LED_WHITE, brightness[EC_LED_COLOR_WHITE]);
+	else
+		return set_color(id, LED_OFF, 0);
+}
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
+{
+	/* Blink alert if insufficient power per system_can_boot_ap(). */
+	int insufficient_power =
+		(charge_ma * charge_mv) <
+		(CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON * 1000);
+	led_alert(insufficient_power);
+}
diff --git a/board/kuldax/pwm.c b/board/kuldax/pwm.c
new file mode 100644
index 0000000000..52cc1c2886
--- /dev/null
+++ b/board/kuldax/pwm.c
@@ -0,0 +1,40 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "hooks.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_LED_WHITE] = { .channel = 0,
+			       .flags = PWM_CONFIG_ACTIVE_LOW |
+					PWM_CONFIG_DSLEEP,
+			       .freq = 2000 },
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
+	[PWM_CH_LED_RED] = { .channel = 2,
+			     .flags = PWM_CONFIG_ACTIVE_LOW |
+				      PWM_CONFIG_DSLEEP | PWM_CONFIG_OPEN_DRAIN,
+			     .freq = 2000 },
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+static void board_pwm_init(void)
+{
+	/*
+	 * TODO(b/197478860): Turn on the fan at 100% by default
+	 * We need to find tune the fan speed according to the
+	 * thermal sensor value.
+	 */
+	pwm_enable(PWM_CH_FAN, 1);
+	pwm_set_duty(PWM_CH_FAN, 100);
+
+	pwm_enable(PWM_CH_LED_RED, 1);
+	pwm_enable(PWM_CH_LED_WHITE, 1);
+}
+DECLARE_HOOK(HOOK_INIT, board_pwm_init, HOOK_PRIO_DEFAULT);
diff --git a/board/kuldax/sensors.c b/board/kuldax/sensors.c
new file mode 100644
index 0000000000..687bfe3851
--- /dev/null
+++ b/board/kuldax/sensors.c
@@ -0,0 +1,117 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc_chip.h"
+#include "common.h"
+#include "hooks.h"
+#include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
+#include "thermal.h"
+
+/* ADC configuration */
+const struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_1_CPU] = {
+		.name = "TEMP_CPU",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_2_CPU_VR] = {
+		.name = "TEMP_CPU_VR",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_3_WIFI] = {
+		.name = "TEMP_WIFI",
+		.input_ch = NPCX_ADC_CH6,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_4_DIMM] = {
+		.name = "TEMP_DIMM",
+		.input_ch = NPCX_ADC_CH7,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_VBUS] = {  /* 5/39 voltage divider */
+		.name = "VBUS",
+		.input_ch = NPCX_ADC_CH2,
+		.factor_mul = ADC_MAX_VOLT * 39,
+		.factor_div = (ADC_READ_MAX + 1) * 5,
+	},
+	[ADC_PPVAR_IMON] = {  /* 20/(20+8.66)*50/200 */
+		.name = "PPVAR_IMON",
+		.input_ch = NPCX_ADC_CH3,
+		.factor_mul = ADC_MAX_VOLT * 143,
+		.factor_div = (ADC_READ_MAX + 1) * 25,
+	},
+
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* Temperature sensor configuration */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1_CPU] = { .name = "CPU",
+				.type = TEMP_SENSOR_TYPE_BOARD,
+				.read = get_temp_3v3_30k9_47k_4050b,
+				.idx = ADC_TEMP_SENSOR_1_CPU },
+	[TEMP_SENSOR_2_CPU_VR] = { .name = "CPU VR",
+				   .type = TEMP_SENSOR_TYPE_BOARD,
+				   .read = get_temp_3v3_30k9_47k_4050b,
+				   .idx = ADC_TEMP_SENSOR_2_CPU_VR },
+	[TEMP_SENSOR_3_WIFI] = { .name = "WIFI",
+				 .type = TEMP_SENSOR_TYPE_BOARD,
+				 .read = get_temp_3v3_30k9_47k_4050b,
+				 .idx = ADC_TEMP_SENSOR_3_WIFI },
+	[TEMP_SENSOR_4_DIMM] = { .name = "DIMM",
+				 .type = TEMP_SENSOR_TYPE_BOARD,
+				 .read = get_temp_3v3_30k9_47k_4050b,
+				 .idx = ADC_TEMP_SENSOR_4_DIMM },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/*
+ * TODO(b/238260272): add the thermal sensor setting
+ */
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(90), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(70), \
+		}, \
+		.temp_fan_off = C_TO_K(35), \
+		.temp_fan_max = C_TO_K(89), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
+
+#define THERMAL_FAN              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = 0, \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = 0, \
+		}, \
+		.temp_fan_off = 0, \
+		.temp_fan_max = 0, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_fan = THERMAL_FAN;
+
+struct ec_thermal_config thermal_params[] = {
+	[TEMP_SENSOR_1_CPU] = THERMAL_CPU,
+	[TEMP_SENSOR_2_CPU_VR] = THERMAL_FAN,
+	[TEMP_SENSOR_3_WIFI] = THERMAL_FAN,
+	[TEMP_SENSOR_4_DIMM] = THERMAL_FAN,
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
diff --git a/board/kuldax/usbc_config.c b/board/kuldax/usbc_config.c
new file mode 100644
index 0000000000..a485dfb326
--- /dev/null
+++ b/board/kuldax/usbc_config.c
@@ -0,0 +1,235 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/bc12/pi3usb9201_public.h"
+#include "driver/ppc/syv682x_public.h"
+#include "driver/retimer/bb_retimer_public.h"
+#include "driver/retimer/kb800x.h"
+#include "driver/tcpm/rt1715.h"
+#include "driver/tcpm/tcpci.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "system.h"
+#include "task.h"
+#include "task_id.h"
+#include "timer.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+/* USBC TCPC configuration */
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	[USBC_PORT_C0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0_C2_TCPC,
+			.addr_flags = RT1715_I2C_ADDR_FLAGS,
+		},
+		.drv = &rt1715_tcpm_drv,
+	},
+};
+
+/* USBC PPC configuration */
+struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_C2_PPC,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.drv = &syv682x_drv,
+	},
+};
+
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/* USBC mux configuration - Alder Lake includes internal mux */
+static const struct usb_mux_chain usbc0_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	[USBC_PORT_C0] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C0_C2_MUX,
+			.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc0_tcss_usb_mux,
+	},
+};
+
+/* BC1.2 charger detect configuration */
+const struct pi3usb9201_config_t
+	pi3usb9201_bc12_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_C2_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+};
+
+__override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
+{
+	enum gpio_signal rst_signal;
+
+	if (me->usb_port == USBC_PORT_C0) {
+		rst_signal = GPIO_USB_C0_RT_RST_ODL;
+	} else {
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * We do not have a load switch for the burnside bridge chips,
+	 * so we only need to sequence reset.
+	 */
+
+	if (enable) {
+		/*
+		 * Tpw, minimum time from VCC to RESET_N de-assertion is 100us.
+		 * For boards that don't provide a load switch control, the
+		 * retimer_init() function ensures power is up before calling
+		 * this function.
+		 */
+		gpio_set_level(rst_signal, 1);
+		/*
+		 * Allow 1ms time for the retimer to power up lc_domain
+		 * which powers I2C controller within retimer
+		 */
+		msleep(1);
+	} else {
+		gpio_set_level(rst_signal, 0);
+		msleep(1);
+	}
+	return EC_SUCCESS;
+}
+
+__override int bb_retimer_reset(const struct usb_mux *me)
+{
+	/*
+	 * TODO(b/193402306, b/195375738): Remove this once transition to
+	 * QS Silicon is complete
+	 */
+	bb_retimer_power_enable(me, false);
+	msleep(5);
+	bb_retimer_power_enable(me, true);
+	msleep(25);
+
+	return EC_SUCCESS;
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * TODO(b/179648104): figure out correct timing
+	 */
+}
+
+static void board_tcpc_init(void)
+{
+	/* Don't reset TCPCs after initial reset */
+	if (!system_jumped_late()) {
+		board_reset_pd_mcu();
+	}
+
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_C2_TCPC_INT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (gpio_get_level(GPIO_USB_C0_C2_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_0 | PD_STATUS_TCPC_ALERT_2;
+
+	return status;
+}
+
+int ppc_get_alert_status(int port)
+{
+	if (port == USBC_PORT_C0)
+		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
+	return 0;
+}
+
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_C2_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C0);
+		break;
+	default:
+		break;
+	}
+}
+
+void bc12_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_BC12_INT_ODL:
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+		break;
+	default:
+		break;
+	}
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C0);
+		break;
+	default:
+		break;
+	}
+}
+
+void retimer_interrupt(enum gpio_signal signal)
+{
+	/*
+	 * TODO(b/179513527): add USB-C support
+	 */
+}
+
+__override bool board_is_dts_port(int port)
+{
+	return port == USBC_PORT_C0;
+}
+
+__override bool board_is_tbt_usb4_port(int port)
+{
+	return true;
+}
+
+__override enum tbt_compat_cable_speed board_get_max_tbt_speed(int port)
+{
+	if (!board_is_tbt_usb4_port(port))
+		return TBT_SS_RES_0;
+
+	return TBT_SS_TBT_GEN3;
+}
diff --git a/board/kuldax/usbc_config.h b/board/kuldax/usbc_config.h
new file mode 100644
index 0000000000..7a212f8fb6
--- /dev/null
+++ b/board/kuldax/usbc_config.h
@@ -0,0 +1,15 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Brya board-specific USB-C configuration */
+
+#ifndef __CROS_EC_USBC_CONFIG_H
+#define __CROS_EC_USBC_CONFIG_H
+
+#define CONFIG_USB_PD_PORT_MAX_COUNT 1
+
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_COUNT };
+
+#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/kuldax/vif_override.xml b/board/kuldax/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/kuldax/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/lalala/battery.c b/board/lalala/battery.c
new file mode 100644
index 0000000000..4edf5fa864
--- /dev/null
+++ b/board/lalala/battery.c
@@ -0,0 +1,128 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+#include "battery.h"
+#include "battery_fuel_gauge.h"
+#include "common.h"
+#include "gpio.h"
+#include "util.h"
+
+/*
+ * Battery info for lalala battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+		/* LGC AP18C8K Battery Information */
+	 [BATTERY_LGC_AP18C8K] = {
+		.fuel_gauge = {
+			.manuf_name = "LGC KT0030G020",
+			.device_name = "AP18C8K",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.reg_addr = 0x43,
+				.reg_mask = 0x0001,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0002,
+				.cfet_off_val = 0x0000,
+			},
+		},
+		.batt_info = {
+			.voltage_max            = 13050,
+			.voltage_normal         = 11250,
+			.voltage_min            = 9000,
+			.precharge_current      = 256,
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 50,
+			.charging_min_c         = 0,
+			.charging_max_c         = 60,
+			.discharging_min_c      = -20,
+			.discharging_max_c      = 75,
+		},
+	},
+	/* Murata AP18C4K Battery Information */
+	[BATTERY_MURATA_AP18C4K] = {
+		.fuel_gauge = {
+			.manuf_name = "Murata KT00304012",
+			.device_name = "AP18C4K",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.reg_addr = 0x0,
+				.reg_mask = 0x2000,
+				.disconnect_val = 0x2000,
+				.cfet_mask = 0x4000,
+				.cfet_off_val = 0x4000,
+			},
+		},
+		.batt_info = {
+			.voltage_max		= 13200,
+			.voltage_normal		= 11400,
+			.voltage_min		= 9000,
+			.precharge_current	= 256,
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 75,
+		},
+	},
+	/* AP19B8M */
+	[BATTERY_AP19B8M] = {
+		.fuel_gauge = {
+			.manuf_name = "LGC KT0030G024",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.reg_addr = 0x43,
+				.reg_mask = 0x0001,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0002,
+				.cfet_off_val = 0x0000,
+			}
+		},
+		.batt_info = {
+			.voltage_max          = 13350,
+			.voltage_normal       = 11610,
+			.voltage_min          = 9000,
+			.precharge_current    = 256,
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 50,
+			.charging_min_c       = 0,
+			.charging_max_c       = 60,
+			.discharging_min_c    = -20,
+			.discharging_max_c    = 75,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_LGC_AP18C8K;
diff --git a/board/lalala/board.c b/board/lalala/board.c
new file mode 100644
index 0000000000..2d9c004f20
--- /dev/null
+++ b/board/lalala/board.c
@@ -0,0 +1,843 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Lalala board-specific configuration */
+
+#include "adc.h"
+#include "button.h"
+#include "cbi_fw_config.h"
+#include "cbi_ssfc.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "chipset.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "driver/accel_bma2x2.h"
+#include "driver/accel_kionix.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "driver/accelgyro_icm426xx.h"
+#include "driver/accelgyro_icm_common.h"
+#include "driver/bc12/pi3usb9201.h"
+#include "driver/charger/isl923x.h"
+#include "driver/retimer/ps8802.h"
+#include "driver/tcpm/raa489000.h"
+#include "driver/tcpm/tcpci.h"
+#include "driver/temp_sensor/thermistor.h"
+#include "driver/usb_mux/pi3usb3x532.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "keyboard_config.h"
+#include "keyboard_raw.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "motion_sense.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "stdbool.h"
+#include "switch.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "temp_sensor.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+#define INT_RECHECK_US 5000
+
+#define ADC_VOL_UP_MASK BIT(0)
+#define ADC_VOL_DOWN_MASK BIT(1)
+
+static uint8_t new_adc_key_state;
+
+static void ps8762_chaddr_deferred(void);
+DECLARE_DEFERRED(ps8762_chaddr_deferred);
+
+/******************************************************************************/
+/* USB-A Configuration */
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_USB_A0_VBUS,
+	GPIO_EN_USB_A1_VBUS,
+};
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/*
+	 * F3 key scan cycle completed but scan input is not
+	 * charging to logic high when EC start scan next
+	 * column for "T" key, so we set .output_settle_us
+	 * to 80us from 50us.
+	 */
+	.output_settle_us = 80,
+	.debounce_down_us = 9 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x1c, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
+		0xa4, 0xff, 0xfe, 0x55, 0xfe, 0xff, 0xff, 0xff,  /* full set */
+	},
+};
+
+static const struct ec_response_keybd_config lalala_keybd = {
+	/* Default Chromeos keyboard config */
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_FORWARD,		/* T2 */
+		TK_REFRESH,		/* T3 */
+		TK_FULLSCREEN,		/* T4 */
+		TK_OVERVIEW,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	/* No function keys, no numeric keypad, has screenlock key */
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &lalala_keybd;
+}
+
+/* C0 interrupt line shared by BC 1.2 and charger */
+static void check_c0_line(void);
+DECLARE_DEFERRED(check_c0_line);
+
+static void notify_c0_chips(void)
+{
+	/*
+	 * The interrupt line is shared between the TCPC and BC 1.2 detection
+	 * chip.  Therefore we'll need to check both ICs.
+	 */
+	schedule_deferred_pd_interrupt(0);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+
+static void check_c0_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		notify_c0_chips();
+		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+	}
+}
+
+static void usb_c0_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c0_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c0_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+}
+
+/* C1 interrupt line shared by BC 1.2, TCPC, and charger */
+static void check_c1_line(void);
+DECLARE_DEFERRED(check_c1_line);
+
+static void notify_c1_chips(void)
+{
+	schedule_deferred_pd_interrupt(1);
+	usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+}
+
+static void check_c1_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips.
+	 */
+	if (!gpio_get_level(GPIO_SUB_USB_C1_INT_ODL)) {
+		notify_c1_chips();
+		hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
+	}
+}
+
+static void sub_usb_c1_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c1_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c1_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
+}
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_1] = {
+		.name = "TEMP_SENSOR1",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_2] = {
+		.name = "TEMP_SENSOR2",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_SUB_ANALOG] = {
+		.name = "SUB_ANALOG",
+		.input_ch = NPCX_ADC_CH2,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_VSNS_PP3300_A] = {
+		.name = "PP3300_A_PGOOD",
+		.input_ch = NPCX_ADC_CH9,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* Thermistors */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_A                \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(85), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A;
+
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_B                \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(73), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(85), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_b = THERMAL_B;
+
+struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
+
+static void setup_thermal(void)
+{
+	thermal_params[TEMP_SENSOR_1] = thermal_a;
+	thermal_params[TEMP_SENSOR_2] = thermal_b;
+}
+
+void board_hibernate(void)
+{
+	/*
+	 * Both charger ICs need to be put into their "low power mode" before
+	 * entering the Z-state.
+	 */
+	raa489000_hibernate(1, true);
+	raa489000_hibernate(0, true);
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * TODO(b:147316511): Here we could issue a digital reset to the IC,
+	 * unsure if we actually want to do that or not yet.
+	 */
+}
+
+static void ps8762_chaddr_deferred(void)
+{
+	/* Switch PS8762 I2C Address to 0x50*/
+	if (ps8802_chg_i2c_addr(I2C_PORT_SUB_USB_C1) == EC_SUCCESS)
+		CPRINTS("Switch PS8762 address to 0x50 success");
+	else
+		CPRINTS("Switch PS8762 address to 0x50 failed");
+}
+
+__override void board_power_5v_enable(int enable)
+{
+	/*
+	 * Port 0 simply has a GPIO to turn on the 5V regulator, however, 5V is
+	 * generated locally on the sub board and we need to set the comparator
+	 * polarity on the sub board charger IC.
+	 */
+	gpio_set_level(GPIO_EN_PP5000, !!enable);
+	if (isl923x_set_comparator_inversion(1, !!enable))
+		CPRINTS("Failed to %sable sub rails!", enable ? "en" : "dis");
+
+	if (!enable)
+		return;
+	/*
+	 * Port C1 the PP3300_USB_C1  assert, delay 15ms
+	 * colud be accessed PS8762 by I2C.
+	 */
+	hook_call_deferred(&ps8762_chaddr_deferred_data, 15 * MSEC);
+}
+
+int board_is_sourcing_vbus(int port)
+{
+	int regval;
+
+	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
+	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int i;
+	int old_port;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	old_port = charge_manager_get_active_charge_port();
+
+	CPRINTS("New chg p%d", port);
+
+	/* Disable all ports. */
+	if (port == CHARGE_PORT_NONE) {
+		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
+			tcpc_write(i, TCPC_REG_COMMAND,
+				   TCPC_REG_COMMAND_SNK_CTRL_LOW);
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if port is sourcing VBUS. */
+	if (board_is_sourcing_vbus(port)) {
+		CPRINTS("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		if (i == port)
+			continue;
+
+		if (tcpc_write(i, TCPC_REG_COMMAND,
+			       TCPC_REG_COMMAND_SNK_CTRL_LOW))
+			CPRINTS("p%d: sink path disable failed.", i);
+	}
+
+	/*
+	 * Stop the charger IC from switching while changing ports.  Otherwise,
+	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
+	 */
+	if (old_port != CHARGE_PORT_NONE)
+		charger_discharge_on_ac(1);
+
+	/* Enable requested charge port. */
+	if (tcpc_write(port, TCPC_REG_COMMAND,
+		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
+		CPRINTS("p%d: sink path enable failed.", port);
+		charger_discharge_on_ac(0);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	/* Allow the charger IC to begin/continue switching. */
+	charger_discharge_on_ac(0);
+
+	return EC_SUCCESS;
+}
+
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	if (port < 0 || port > board_get_usb_pd_port_count())
+		return;
+
+	raa489000_set_output_current(port, rp);
+}
+
+/* Sensors */
+static struct mutex g_lid_mutex;
+static struct mutex g_base_mutex;
+
+/* Matrices to rotate accelerometers into the standard reference. */
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
+
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					      { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
+
+/* BMA253 private data */
+static struct accelgyro_saved_data_t g_bma253_data;
+
+/* BMI160 private data */
+static struct bmi_drv_data_t g_bmi160_data;
+
+static const mat33_fp_t base_icm_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					 { 0, FLOAT_TO_FP(1), 0 },
+					 { 0, 0, FLOAT_TO_FP(-1) } };
+
+/* ICM426 private data */
+static struct icm_drv_data_t g_icm426xx_data;
+/* KX022 private data */
+static struct kionix_accel_data g_kx022_data;
+
+struct motion_sensor_t kx022_lid_accel = {
+	.name = "Lid Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_KX022,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_LID,
+	.drv = &kionix_accel_drv,
+	.mutex = &g_lid_mutex,
+	.drv_data = &g_kx022_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = KX022_ADDR0_FLAGS,
+	.rot_standard_ref = &lid_standard_ref,
+	.min_frequency = KX022_ACCEL_MIN_FREQ,
+	.max_frequency = KX022_ACCEL_MAX_FREQ,
+	.default_range = 2, /* g, to support tablet mode */
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	},
+};
+
+struct motion_sensor_t icm426xx_base_accel = {
+	.name = "Base Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
+	.rot_standard_ref = &base_icm_ref,
+	.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
+	.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 13000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+	},
+};
+
+struct motion_sensor_t icm426xx_base_gyro = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &base_icm_ref,
+	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
+	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
+};
+
+struct motion_sensor_t motion_sensors[] = {
+	[LID_ACCEL] = {
+		.name = "Lid Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMA255,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &bma2x2_accel_drv,
+		.mutex = &g_lid_mutex,
+		.drv_data = &g_bma253_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
+		.rot_standard_ref = &lid_standard_ref,
+		.default_range = 2,
+		.min_frequency = BMA255_ACCEL_MIN_FREQ,
+		.max_frequency = BMA255_ACCEL_MAX_FREQ,
+		.config = {
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+		},
+	},
+	[BASE_ACCEL] = {
+		.name = "Base Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMI160,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &bmi160_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = &g_bmi160_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+		.rot_standard_ref = &base_standard_ref,
+		.default_range = 4,
+		.min_frequency = BMI_ACCEL_MIN_FREQ,
+		.max_frequency = BMI_ACCEL_MAX_FREQ,
+		.config = {
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 13000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+		},
+	},
+	[BASE_GYRO] = {
+		.name = "Base Gyro",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMI160,
+		.type = MOTIONSENSE_TYPE_GYRO,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &bmi160_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = &g_bmi160_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+		.default_range = 1000, /* dps */
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = BMI_GYRO_MIN_FREQ,
+		.max_frequency = BMI_GYRO_MAX_FREQ,
+	},
+};
+
+unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+void board_init(void)
+{
+	int on;
+
+	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
+	gpio_enable_interrupt(GPIO_SUB_USB_C1_INT_ODL);
+	check_c0_line();
+	check_c1_line();
+
+	/* Enable gpio interrupt for base accelgyro sensor */
+	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
+	if (get_cbi_fw_config_tablet_mode()) {
+		if (get_cbi_ssfc_base_sensor() == SSFC_SENSOR_ICM426XX) {
+			motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
+			motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
+			cprints(CC_SYSTEM, "BASE GYRO is ICM426XX");
+		} else
+			cprints(CC_SYSTEM, "BASE GYRO is BMI160");
+
+		if (get_cbi_ssfc_lid_sensor() == SSFC_SENSOR_KX022) {
+			motion_sensors[LID_ACCEL] = kx022_lid_accel;
+			cprints(CC_SYSTEM, "LID_ACCEL is KX022");
+		} else
+			cprints(CC_SYSTEM, "LID_ACCEL is BMA253");
+
+		motion_sensor_count = ARRAY_SIZE(motion_sensors);
+		/* Enable gpio interrupt for base accelgyro sensor */
+		gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
+	} else {
+		motion_sensor_count = 0;
+		gmr_tablet_switch_disable();
+		/* Base accel is not stuffed, don't allow line to float */
+		gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L,
+			       GPIO_INPUT | GPIO_PULL_DOWN);
+	}
+
+	/* Turn on 5V if the system is on, otherwise turn it off. */
+	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
+			      CHIPSET_STATE_SOFT_OFF);
+	board_power_5v_enable(on);
+
+	/* Initialize THERMAL */
+	setup_thermal();
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	switch (get_cbi_ssfc_base_sensor()) {
+	case SSFC_SENSOR_ICM426XX:
+		icm426xx_interrupt(signal);
+		break;
+	case SSFC_SENSOR_BMI160:
+	default:
+		bmi160_interrupt(signal);
+		break;
+	}
+}
+
+__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+				       int *ki_div, int *kd, int *kd_div)
+{
+	*kp = 1;
+	*kp_div = 20;
+	*ki = 1;
+	*ki_div = 250;
+	*kd = 0;
+	*kd_div = 1;
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	return pd_check_vbus_level(port, VBUS_PRESENT);
+}
+
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+
+	{
+		.i2c_port = I2C_PORT_SUB_USB_C1,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+};
+const unsigned int chg_cnt = ARRAY_SIZE(chg_chips);
+
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	{
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+		.flags = PI3USB9201_ALWAYS_POWERED,
+	},
+
+	{
+		.i2c_port = I2C_PORT_SUB_USB_C1,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+		.flags = PI3USB9201_ALWAYS_POWERED,
+	},
+};
+
+/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_KBLIGHT] = {
+		.channel = 3,
+		.flags = PWM_CONFIG_DSLEEP,
+		.freq = 10000,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0,
+			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
+		},
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+		.drv = &raa489000_tcpm_drv,
+	},
+
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_SUB_USB_C1,
+			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
+		},
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+		.drv = &raa489000_tcpm_drv,
+	},
+};
+
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
+				.driver = &pi3usb3x532_usb_mux_driver,
+			},
+	},
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_SUB_USB_C1,
+				.i2c_addr_flags = PS8802_I2C_ADDR_FLAGS_CUSTOM,
+				.driver = &ps8802_usb_mux_driver,
+			},
+	}
+};
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+	int regval;
+
+	/*
+	 * The interrupt line is shared between the TCPC and BC1.2 detector IC.
+	 * Therefore, go out and actually read the alert registers to report the
+	 * alert status.
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
+			/* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */
+			if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0))
+				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
+
+			if (regval)
+				status |= PD_STATUS_TCPC_ALERT_0;
+		}
+	}
+
+	if (!gpio_get_level(GPIO_SUB_USB_C1_INT_ODL)) {
+		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
+			/* TCPCI spec Rev 1.0 says to ignore bits 14:12. */
+			if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0))
+				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
+
+			if (regval)
+				status |= PD_STATUS_TCPC_ALERT_1;
+		}
+	}
+
+	return status;
+}
+
+int adc_to_physical_value(enum gpio_signal gpio)
+{
+	if (gpio == GPIO_VOLUME_UP_L)
+		return !!(new_adc_key_state & ADC_VOL_UP_MASK);
+	else if (gpio == GPIO_VOLUME_DOWN_L)
+		return !!(new_adc_key_state & ADC_VOL_DOWN_MASK);
+
+	CPRINTS("Not a volume up or down key");
+	return 0;
+}
+
+int button_is_adc_detected(enum gpio_signal gpio)
+{
+	return (gpio == GPIO_VOLUME_DOWN_L) || (gpio == GPIO_VOLUME_UP_L);
+}
+
+static void adc_vol_key_press_check(void)
+{
+	int volt = adc_read_channel(ADC_SUB_ANALOG);
+	static uint8_t old_adc_key_state;
+	uint8_t adc_key_state_change;
+
+	if (volt > 2400 && volt < 2490) {
+		/* volume-up is pressed */
+		new_adc_key_state = ADC_VOL_UP_MASK;
+	} else if (volt > 2600 && volt < 2690) {
+		/* volume-down is pressed */
+		new_adc_key_state = ADC_VOL_DOWN_MASK;
+	} else if (volt < 2290) {
+		/* both volumn-up and volume-down are pressed */
+		new_adc_key_state = ADC_VOL_UP_MASK | ADC_VOL_DOWN_MASK;
+	} else if (volt > 2700) {
+		/* both volumn-up and volume-down are released */
+		new_adc_key_state = 0;
+	}
+	if (new_adc_key_state != old_adc_key_state) {
+		adc_key_state_change = old_adc_key_state ^ new_adc_key_state;
+		if (adc_key_state_change & ADC_VOL_UP_MASK)
+			button_interrupt(GPIO_VOLUME_UP_L);
+		if (adc_key_state_change & ADC_VOL_DOWN_MASK)
+			button_interrupt(GPIO_VOLUME_DOWN_L);
+
+		old_adc_key_state = new_adc_key_state;
+	}
+}
+DECLARE_HOOK(HOOK_TICK, adc_vol_key_press_check, HOOK_PRIO_DEFAULT);
+
+/* This callback disables keyboard when convertibles are fully open */
+__override void lid_angle_peripheral_enable(int enable)
+{
+	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
+
+	/*
+	 * If the lid is in tablet position via other sensors,
+	 * ignore the lid angle, which might be faulty then
+	 * disable keyboard.
+	 */
+	if (tablet_get_mode())
+		enable = 0;
+
+	if (enable) {
+		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
+	} else {
+		/*
+		 * Ensure that the chipset is off before disabling the keyboard.
+		 * When the chipset is on, the EC keeps the keyboard enabled and
+		 * the AP decides whether to ignore input devices or not.
+		 */
+		if (!chipset_in_s0)
+			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
+	}
+}
diff --git a/board/lalala/board.h b/board/lalala/board.h
new file mode 100644
index 0000000000..f9aa2482b0
--- /dev/null
+++ b/board/lalala/board.h
@@ -0,0 +1,181 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Lalala board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#define VARIANT_KEEBY_EC_NPCX797FC
+#include "baseboard.h"
+
+/*
+ * The RAM and flash size combination on the the NPCX797FC does not leave
+ * any unused flash space that can be used to store the .init_rom section.
+ */
+#undef CONFIG_CHIP_INIT_ROM_REGION
+
+/* Battery */
+#define CONFIG_BATTERY_FUEL_GAUGE
+
+/* Charger */
+#define CONFIG_CHARGER_RAA489000
+#define PD_MAX_VOLTAGE_MV 20000
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_OCPC_DEF_RBATT_MOHMS               \
+	22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \
+	    */
+#define CONFIG_OCPC
+#undef CONFIG_CHARGER_SINGLE_CHIP
+#undef CONFIG_CMD_CHARGER_DUMP
+#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
+#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
+/*
+ * b/147463641: The charger IC seems to overdraw ~4%, therefore we
+ * reduce our target accordingly.
+ */
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 4
+
+/* GPIO for C1 interrupts, for baseboard use */
+#define GPIO_USB_C1_INT_ODL GPIO_SUB_USB_C1_INT_ODL
+
+/* Keyboard */
+
+#define CONFIG_KEYBOARD_KEYPAD
+#define CONFIG_PWM_KBLIGHT
+
+/* LED defines */
+#define CONFIG_LED_ONOFF_STATES
+
+/* PWM */
+#define CONFIG_PWM
+#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */
+
+/* Temp sensor */
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_THROTTLE_AP
+#define CONFIG_THERMISTOR_NCP15WB
+#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
+
+/* USB */
+#define CONFIG_BC12_DETECT_PI3USB9201
+#define CONFIG_USBC_RETIMER_PS8802
+
+/* Common USB-A defines */
+#define USB_PORT_COUNT 2
+#define CONFIG_USB_PORT_POWER_SMART
+#define CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY
+#define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_CDP
+#define CONFIG_USB_PORT_POWER_SMART_INVERTED
+#define GPIO_USB1_ILIM_SEL GPIO_USB_A0_CHARGE_EN_L
+#define GPIO_USB2_ILIM_SEL GPIO_USB_A1_CHARGE_EN_L
+
+/******************************************************************************/
+
+/* USB PD */
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#define CONFIG_USB_PD_TCPM_RAA489000
+
+/* USB defines specific to external TCPCs */
+#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+#define CONFIG_USB_PD_VBUS_DETECT_TCPC
+#define CONFIG_USB_PD_DISCHARGE_TCPC
+#define CONFIG_USB_PD_TCPC_LOW_POWER
+
+/* Variant references the TCPCs to determine Vbus sourcing */
+#define CONFIG_USB_PD_5V_EN_CUSTOM
+
+/* I2C configuration */
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
+#define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0
+/* TODO(b:147440290): Need to handle multiple charger ICs */
+#define I2C_PORT_CHARGER I2C_PORT_USB_C0
+
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */
+
+/* Sensors */
+#define CONFIG_CMD_ACCELS
+#define CONFIG_CMD_ACCEL_INFO
+#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
+
+#define CONFIG_ACCEL_BMA255 /* Lid accel */
+#define CONFIG_ACCELGYRO_BMI160 /* Base accel */
+#define CONFIG_ACCEL_KX022 /* Lid accel */
+#define CONFIG_ACCELGYRO_ICM426XX /* Base accel second source*/
+
+/* Lid operates in forced mode, base in FIFO */
+#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
+#define CONFIG_ACCEL_FIFO
+#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */
+#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
+
+#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_UPDATE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+
+#define CONFIG_TABLET_MODE
+#define CONFIG_TABLET_MODE_SWITCH
+#define CONFIG_GMR_TABLET_MODE
+
+/* Volume Button feature */
+#define CONFIG_ADC_BUTTONS
+#define CONFIG_VOLUME_BUTTONS
+#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum chg_id {
+	CHARGER_PRIMARY,
+	CHARGER_SECONDARY,
+	CHARGER_NUM,
+};
+
+enum adc_channel {
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
+	ADC_SUB_ANALOG, /* ADC2 */
+	ADC_VSNS_PP3300_A, /* ADC9 */
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT };
+
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
+
+enum pwm_channel {
+	PWM_CH_KBLIGHT,
+	PWM_CH_COUNT,
+};
+
+enum battery_type {
+	BATTERY_AP19B8M,
+	BATTERY_LGC_AP18C8K,
+	BATTERY_MURATA_AP18C4K,
+	BATTERY_TYPE_COUNT,
+};
+
+int board_is_sourcing_vbus(int port);
+void motion_interrupt(enum gpio_signal signal);
+#endif /* !__ASSEMBLER__ */
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/lalala/build.mk b/board/lalala/build.mk
new file mode 100644
index 0000000000..eb422dae93
--- /dev/null
+++ b/board/lalala/build.mk
@@ -0,0 +1,14 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx7
+CHIP_VARIANT:=npcx7m7fc
+BASEBOARD:=keeby
+
+board-y=board.o battery.o cbi_ssfc.o led.o usb_pd_policy.o
diff --git a/board/lalala/cbi_ssfc.c b/board/lalala/cbi_ssfc.c
new file mode 100644
index 0000000000..81f3ee0dad
--- /dev/null
+++ b/board/lalala/cbi_ssfc.c
@@ -0,0 +1,36 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi_ssfc.h"
+#include "common.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "hooks.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+/* Cache SSFC on init since we don't expect it to change in runtime */
+static union dedede_cbi_ssfc cached_ssfc;
+BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
+
+static void cbi_ssfc_init(void)
+{
+	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
+		/* Default to 0 when CBI isn't populated */
+		cached_ssfc.raw_value = 0;
+
+	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
+}
+DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
+
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
+{
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
+}
+
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
+{
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
+}
diff --git a/board/lalala/cbi_ssfc.h b/board/lalala/cbi_ssfc.h
new file mode 100644
index 0000000000..bf8853a43a
--- /dev/null
+++ b/board/lalala/cbi_ssfc.h
@@ -0,0 +1,59 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _DEDEDE_CBI_SSFC__H_
+#define _DEDEDE_CBI_SSFC__H_
+
+#include "stdint.h"
+
+/****************************************************************************
+ * Dedede CBI Second Source Factory Cache
+ */
+
+/*
+ * Base Sensor (Bits 0-2)
+ */
+enum ec_ssfc_base_sensor {
+	SSFC_SENSOR_BASE_DEFAULT = 0,
+	SSFC_SENSOR_BMI160 = 1,
+	SSFC_SENSOR_ICM426XX = 2,
+	SSFC_SENSOR_LSM6DSM = 3,
+	SSFC_SENSOR_ICM42607 = 4
+};
+
+/*
+ * Lid Sensor (Bits 3-5)
+ */
+enum ec_ssfc_lid_sensor {
+	SSFC_SENSOR_LID_DEFAULT = 0,
+	SSFC_SENSOR_BMA255 = 1,
+	SSFC_SENSOR_KX022 = 2,
+	SSFC_SENSOR_LIS2DWL = 3
+};
+
+union dedede_cbi_ssfc {
+	struct {
+		uint32_t base_sensor : 3;
+		uint32_t lid_sensor : 3;
+		uint32_t reserved_2 : 26;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Get the Base sensor type from SSFC_CONFIG.
+ *
+ * @return the Base sensor board type.
+ */
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
+
+/**
+ * Get the Lid sensor type from SSFC_CONFIG.
+ *
+ * @return the Lid sensor board type.
+ */
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
+
+#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/lalala/ec.tasklist b/board/lalala/ec.tasklist
new file mode 100644
index 0000000000..29666dd959
--- /dev/null
+++ b/board/lalala/ec.tasklist
@@ -0,0 +1,25 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/lalala/gpio.inc b/board/lalala/gpio.inc
new file mode 100644
index 0000000000..8d37079ca4
--- /dev/null
+++ b/board/lalala/gpio.inc
@@ -0,0 +1,145 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first.
+ */
+
+/* Power Interrupts */
+GPIO_INT(SLP_S0_L,		 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,		 PIN(A, 5), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(SLP_S4_L,		 PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,		 PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(RSMRST_PWRGD_L,	 PIN(C, 6), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID1,	 PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(CPU_C10_GATE_L,	 PIN(6, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID0,	 PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, power_signal_interrupt)
+GPIO_INT(PG_VCCIO_EXT_OD,	 PIN(B, 0), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(PG_PP5000_U_OD,	 PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_DRAM_OD,		 PIN(E, 4), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(PG_PP1050_ST_OD,	 PIN(4, 2), GPIO_INT_BOTH, power_signal_interrupt)
+
+/* USB-C interrupts */
+GPIO_INT(USB_C0_INT_ODL,	 PIN(6, 2), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt)
+GPIO_INT(SUB_USB_C1_INT_ODL,	 PIN(F, 5), GPIO_INT_FALLING | GPIO_PULL_UP, sub_usb_c1_interrupt)
+
+/* Button interrupts */
+GPIO_INT(EC_PWR_BTN_ODL,	 PIN(0, 1), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
+
+/* Other interrupts */
+GPIO_INT(LID_OPEN,		 PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)
+GPIO_INT(EC_WP_OD,		 PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(BASE_SIXAXIS_INT_L,	 PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, motion_interrupt)
+GPIO_INT(LID_360_L,		 PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
+
+/* I2C Ports */
+GPIO(EC_I2C_EEPROM_SCL,	      PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SDA,	      PIN(B, 2), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SCL,      PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SDA,      PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,	      PIN(B, 5), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SDA,	      PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SCL,	      PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SDA,	      PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_SUB_USB_C1_SCL,   PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_SUB_USB_C1_SDA,   PIN(9, 1), GPIO_INPUT)
+
+/* Extra Sub-board I/O pins */
+
+GPIO(EC_SUB_IO_2,  PIN(3, 4), GPIO_OUT_LOW)
+
+/* Misc Enables */
+GPIO(EN_VCCIO_EXT,   PIN(6, 1), GPIO_OUT_LOW)
+/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
+GPIO(EN_VCCST,		PIN(A, 7), GPIO_INPUT)
+GPIO(EN_PP3300_PEN,	PIN(6, 3), GPIO_OUT_LOW)
+GPIO(EN_PP3300_A,	PIN(0, 3), GPIO_OUT_LOW)
+GPIO(EN_PP5000_U,	PIN(A, 4), GPIO_OUT_LOW)
+GPIO(EN_SLP_Z,		PIN(8, 3), GPIO_OUT_LOW)
+GPIO(EN_KB_BL,		PIN(6, 0), GPIO_OUT_LOW)
+GPIO(EN_BL_OD,		PIN(D, 3), GPIO_ODR_LOW)
+GPIO(EC_CBI_WP,		PIN(E, 5), GPIO_OUT_LOW)
+
+/* LED */
+GPIO(LED_B_ODL,                  PIN(C, 2), GPIO_OUT_HIGH)        /* PWM_CH_LED2_BLUE */
+GPIO(LED_G_ODL,                  PIN(C, 3), GPIO_OUT_HIGH)        /* PWM_CH_LED1_GREEN */
+GPIO(LED_R_ODL,                  PIN(C, 4), GPIO_OUT_HIGH)        /* PWM_CH_LED2_ORANGE */
+
+/* Power Sequencing */
+GPIO(EC_AP_PSYS,	     PIN(B, 7), GPIO_OUT_LOW)
+GPIO(EC_AP_RSMRST_L,         PIN(A, 6), GPIO_OUT_LOW)
+GPIO(EC_AP_PWR_BTN_ODL,      PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(EC_AP_RTCRST,           PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_AP_WAKE_ODL,         PIN(7, 4), GPIO_ODR_HIGH)
+GPIO(EC_AP_DPWROK,	     PIN(A, 3), GPIO_OUT_LOW)
+GPIO(EC_AP_PCH_PWROK_OD,     PIN(9, 4), GPIO_ODR_LOW)
+GPIO(EC_AP_VCCST_PWRGD_OD,   PIN(B, 1), GPIO_ODR_LOW)
+GPIO(EC_AP_SYS_PWROK,	     PIN(0, 2), GPIO_OUT_LOW)
+GPIO(EC_AP_MKBP_INT_L,	     PIN(7, 0), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_ODL,	     PIN(F, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(EC_ENTERING_RW,	     PIN(E, 3), GPIO_OUT_LOW)
+GPIO(ALL_SYS_PWRGD,	     PIN(A, 0), GPIO_OUT_LOW)
+GPIO(SYS_RST_ODL,	     PIN(C, 5), GPIO_ODR_HIGH)
+
+/* USB pins */
+GPIO(EC_AP_USB_C1_HDMI_HPD,  PIN(9, 6), GPIO_OUT_LOW)
+GPIO(EC_AP_USB_C0_HPD,	     PIN(9, 3), GPIO_OUT_LOW)
+GPIO(HDMI_SEL_L,	     PIN(7, 2), GPIO_OUT_HIGH)
+GPIO(EC_BATTERY_PRES_ODL,    PIN(E, 1), GPIO_INPUT)
+GPIO(USB_A0_CHARGE_EN_L, PIN(3, 7), GPIO_OUT_HIGH)	/* Enable A0 1.5A Charging */
+GPIO(USB_A1_CHARGE_EN_L, PIN(F, 3), GPIO_OUT_HIGH)	/* Enable A1 1.5A Charging */
+GPIO(EN_USB_A0_VBUS,	 PIN(4, 1), GPIO_OUT_LOW)		/* Enable A1 5V Charging */
+GPIO(EN_USB_A1_VBUS,	 PIN(F, 2), GPIO_OUT_LOW)		/* Enable A1 5V Charging */
+/*
+ * Lalala doesn't have these physical pins coming to the EC but uses other
+ * logic.
+ */
+UNIMPLEMENTED(AC_PRESENT)
+UNIMPLEMENTED(PG_EC_DSW_PWROK)
+UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
+UNIMPLEMENTED(VOLDN_BTN_ODL)
+UNIMPLEMENTED(VOLUP_BTN_ODL)
+
+/* Alternate Functions */
+/* ADC */
+ALTERNATE(PIN_MASK(F, BIT(0)), 0, MODULE_ADC, 0) /* ADC9 */
+ALTERNATE(PIN_MASK(4, 0x38), 0, MODULE_ADC, 0)   /* ADC0-2 */
+
+/* Keyboard */
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI0, KSI1 */
+ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI2-7 */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO0, KSO1 */
+ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO3-9 */
+ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO10-13 */
+ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO14 */
+GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW)	/* KSO2 inverted */
+
+/* PWM */
+ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0) /* PWM3 */
+
+/* UART */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)  /* UART1 */
+
+/* I2C */
+ALTERNATE(PIN_MASK(B, 0x3C), 0, MODULE_I2C, 0)   /* I2C7,I2C0 */
+ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)   /* I2C5 */
+ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)   /* I2C2, I2C1 SCL */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)   /* I2C1 SDA */
+
+/* NC pins, enable internal pull-up to avoid floating state. */
+GPIO(GPIO32_NC, PIN(3, 2), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO35_NC, PIN(3, 5), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO57_NC, PIN(5, 7), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO81_NC, PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO86_NC, PIN(8, 6), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOD0_NC, PIN(D, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOD1_NC, PIN(D, 1), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOD6_NC, PIN(D, 6), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOE0_NC, PIN(E, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO40_NC, PIN(4, 0), GPIO_INPUT | GPIO_PULL_UP)
diff --git a/board/lalala/led.c b/board/lalala/led.c
new file mode 100644
index 0000000000..94e55a8597
--- /dev/null
+++ b/board/lalala/led.c
@@ -0,0 +1,84 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power and battery LED control for lalala
+ */
+
+#include "chipset.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+
+#define LED_ON_LVL 0
+#define LED_OFF_LVL 1
+
+__override const int led_charge_lvl_1 = 5;
+
+__override const int led_charge_lvl_2 = 95;
+
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_AMBER:
+		gpio_set_level(GPIO_LED_R_ODL, LED_ON_LVL);
+		gpio_set_level(GPIO_LED_B_ODL, LED_OFF_LVL);
+		break;
+	case EC_LED_COLOR_BLUE:
+		gpio_set_level(GPIO_LED_R_ODL, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_B_ODL, LED_ON_LVL);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		gpio_set_level(GPIO_LED_R_ODL, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_B_ODL, LED_OFF_LVL);
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		brightness_range[EC_LED_COLOR_BLUE] = 1;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		if (brightness[EC_LED_COLOR_BLUE] != 0)
+			led_set_color_battery(EC_LED_COLOR_BLUE);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(EC_LED_COLOR_AMBER);
+		else
+			led_set_color_battery(LED_OFF);
+	}
+	return EC_SUCCESS;
+}
diff --git a/board/lalala/usb_pd_policy.c b/board/lalala/usb_pd_policy.c
new file mode 100644
index 0000000000..3410726e87
--- /dev/null
+++ b/board/lalala/usb_pd_policy.c
@@ -0,0 +1,56 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "driver/tcpm/tcpci.h"
+#include "usb_pd.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+int pd_check_vconn_swap(int port)
+{
+	/* Allow VCONN swaps if the AP is on. */
+	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
+}
+
+void pd_power_supply_reset(int port)
+{
+	/* Disable VBUS */
+	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	if (port >= CONFIG_USB_PD_PORT_MAX_COUNT)
+		return EC_ERROR_INVAL;
+
+	/* Disable charging. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
+	if (rv)
+		return rv;
+
+	/* Our policy is not to source VBUS when the AP is off. */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	/* Provide Vbus. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
+	if (rv)
+		return rv;
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
diff --git a/board/lalala/vif_override.xml b/board/lalala/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/lalala/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/lantis/battery.c b/board/lantis/battery.c
new file mode 100644
index 0000000000..6dfb91ef50
--- /dev/null
+++ b/board/lantis/battery.c
@@ -0,0 +1,285 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "charge_state.h"
+#include "common.h"
+
+/*
+ * Battery info for all lantis battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	/* DynaPack CosMX Battery Information */
+	[BATTERY_DYNAPACK_COS] = {
+		.fuel_gauge = {
+			.manuf_name = "333-2C-DA-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,	/* mV */
+			.voltage_normal = 7700,
+			.voltage_min = 6000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
+
+	/* DynaPack ATL Battery Information */
+	[BATTERY_DYNAPACK_ATL] = {
+		.fuel_gauge = {
+			.manuf_name = "333-27-DA-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,	/* mV */
+			.voltage_normal = 7700,
+			.voltage_min = 6000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
+
+	/* Simplo CosMX Battery Information */
+	[BATTERY_SIMPLO_COS] = {
+		.fuel_gauge = {
+			.manuf_name = "333-1C-DA-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,	/* mV */
+			.voltage_normal = 7700,
+			.voltage_min = 6000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
+
+	/* Simplo HIGHPOWER Battery Information */
+	[BATTERY_SIMPLO_HIGHPOWER] = {
+		.fuel_gauge = {
+			.manuf_name = "333-1D-DA-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,	/* mV */
+			.voltage_normal = 7700,
+			.voltage_min = 6000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
+
+	/* CosMX B00C4473A9D0002 Battery Information */
+	[BATTERY_COS] = {
+		.fuel_gauge = {
+			.manuf_name = "333-AC-DA-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,	/* mV */
+			.voltage_normal = 7700,
+			.voltage_min = 6000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
+
+	/* DynaPack CosMX DAK125720-W0P0701HT Battery Information */
+	[BATTERY_DYNAPACK_COS_44WH] = {
+		.fuel_gauge = {
+			.manuf_name = "333-2C-DB-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,	/* mV */
+			.voltage_normal = 7700,
+			.voltage_min = 6000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
+
+	/* DynaPack ATL DAK125720-W0G0701HT Battery Information */
+	[BATTERY_DYNAPACK_ATL_44WH] = {
+		.fuel_gauge = {
+			.manuf_name = "333-27-DB-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,	/* mV */
+			.voltage_normal = 7700,
+			.voltage_min = 6000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
+
+	/* Simplo HIGHPOWER 996Q4242H Battery Information */
+	[BATTERY_SIMPLO_HIGHPOWER_44WH] = {
+		.fuel_gauge = {
+			.manuf_name = "333-1D-DB-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,	/* mV */
+			.voltage_normal = 7700,
+			.voltage_min = 6000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_DYNAPACK_COS;
diff --git a/board/lantis/board.c b/board/lantis/board.c
new file mode 100644
index 0000000000..600f141639
--- /dev/null
+++ b/board/lantis/board.c
@@ -0,0 +1,887 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Lantis board-specific configuration */
+
+#include "adc_chip.h"
+#include "button.h"
+#include "cbi_fw_config.h"
+#include "cbi_ssfc.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "cros_board_info.h"
+#include "driver/accel_bma2x2.h"
+#include "driver/accel_bma422.h"
+#include "driver/accelgyro_lsm6dsm.h"
+#include "driver/bc12/pi3usb9201.h"
+#include "driver/charger/sm5803.h"
+#include "driver/tcpm/it83xx_pd.h"
+#include "driver/tcpm/ps8xxx.h"
+#include "driver/temp_sensor/thermistor.h"
+#include "driver/usb_mux/it5205.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "intc.h"
+#include "keyboard_8042.h"
+#include "keyboard_8042_sharedlib.h"
+#include "keyboard_raw.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "switch.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "tcpm/tcpci.h"
+#include "temp_sensor.h"
+#include "uart.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+
+#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+
+#define INT_RECHECK_US 5000
+
+uint32_t board_version;
+
+/* GPIO to enable/disable the USB Type-A port. */
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_USB_A_5V,
+};
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	.output_settle_us = 80,
+	.debounce_down_us = 9 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x1c, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xa4, 0xff, 0xfe, 0x55, 0xfe, 0xff, 0xff, 0xff,  /* full set */
+	},
+};
+
+__override void board_process_pd_alert(int port)
+{
+	/*
+	 * PD_INT task will process this alert, and that task is only needed on
+	 * C1.
+	 */
+	if (port != 1)
+		return;
+
+	if (gpio_get_level(GPIO_USB_C1_INT_ODL))
+		return;
+
+	sm5803_handle_interrupt(port);
+}
+
+/* C0 interrupt line shared by BC 1.2 and charger */
+static void check_c0_line(void);
+DECLARE_DEFERRED(check_c0_line);
+
+static void notify_c0_chips(void)
+{
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+	sm5803_interrupt(0);
+}
+
+static void check_c0_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		notify_c0_chips();
+		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+	}
+}
+
+static void usb_c0_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c0_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c0_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+}
+
+/* C1 interrupt line shared by BC 1.2, TCPC, and charger */
+static void check_c1_line(void);
+DECLARE_DEFERRED(check_c1_line);
+
+static void notify_c1_chips(void)
+{
+	schedule_deferred_pd_interrupt(1);
+	usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+}
+
+static void check_c1_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips.
+	 */
+	if (!gpio_get_level(GPIO_USB_C1_INT_ODL)) {
+		notify_c1_chips();
+		hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
+	}
+}
+
+static void usb_c1_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c1_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c1_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
+}
+
+static void button_sub_hdmi_hpd_interrupt(enum gpio_signal s)
+{
+	enum fw_config_db db = get_cbi_fw_config_db();
+	int hdmi_hpd = gpio_get_level(GPIO_VOLUP_BTN_ODL_HDMI_HPD);
+
+	if (db == DB_1A_HDMI || db == DB_LTE_HDMI || db == DB_1A_HDMI_LTE)
+		gpio_set_level(GPIO_EC_AP_USB_C1_HDMI_HPD, hdmi_hpd);
+	else
+		button_interrupt(s);
+}
+
+static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
+{
+	cprints(CC_USBPD, "C0: CC OVP, SBU OVP, or thermal event");
+	pd_handle_cc_overvoltage(0);
+}
+
+static void pen_detect_interrupt(enum gpio_signal s)
+{
+	int pen_detect = !gpio_get_level(GPIO_PEN_DET_ODL);
+
+	gpio_set_level(GPIO_EN_PP5000_PEN, pen_detect);
+}
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	[ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH0 },
+	[ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH2 },
+	[ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH3 },
+	[ADC_SUB_ANALOG] = { .name = "SUB_ANALOG",
+			     .factor_mul = ADC_MAX_MVOLT,
+			     .factor_div = ADC_READ_MAX + 1,
+			     .shift = 0,
+			     .channel = CHIP_ADC_CH13 },
+	[ADC_TEMP_SENSOR_3] = { .name = "TEMP_SENSOR3",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH15 },
+	[ADC_TEMP_SENSOR_4] = { .name = "TEMP_SENSOR4",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH16 },
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* BC 1.2 chips */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	{
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+		.flags = PI3USB9201_ALWAYS_POWERED,
+	},
+	{
+		.i2c_port = I2C_PORT_SUB_USB_C1,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+		.flags = PI3USB9201_ALWAYS_POWERED,
+	},
+};
+
+/* Charger chips */
+const struct charger_config_t chg_chips[] = {
+	[CHARGER_PRIMARY] = {
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = SM5803_ADDR_CHARGER_FLAGS,
+		.drv = &sm5803_drv,
+	},
+	[CHARGER_SECONDARY] = {
+		.i2c_port = I2C_PORT_SUB_USB_C1,
+		.i2c_addr_flags = SM5803_ADDR_CHARGER_FLAGS,
+		.drv = &sm5803_drv,
+	},
+};
+
+/* TCPCs */
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_EMBEDDED,
+		.drv = &it83xx_tcpm_drv,
+	},
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_SUB_USB_C1,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+	},
+};
+
+/* USB Muxes */
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+			},
+	},
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_SUB_USB_C1,
+				.i2c_addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
+	},
+};
+
+/* Sensor Mutexes */
+static struct mutex g_lid_mutex;
+static struct mutex g_base_mutex;
+
+/* Sensor Data */
+static struct accelgyro_saved_data_t g_bma253_data;
+static struct accelgyro_saved_data_t g_bma422_data;
+static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
+
+/* Matrix to rotate accelrator into standard reference frame */
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+					      { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
+
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
+
+/* Drivers */
+struct motion_sensor_t motion_sensors[] = {
+	[LID_ACCEL] = {
+		.name = "Lid Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMA255,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &bma2x2_accel_drv,
+		.mutex = &g_lid_mutex,
+		.drv_data = &g_bma253_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
+		.rot_standard_ref = &lid_standard_ref,
+		.default_range = 2,
+		.min_frequency = BMA255_ACCEL_MIN_FREQ,
+		.max_frequency = BMA255_ACCEL_MAX_FREQ,
+		.config = {
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+		},
+	},
+	[BASE_ACCEL] = {
+		.name = "Base Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LSM6DSM,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &lsm6dsm_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
+				MOTIONSENSE_TYPE_ACCEL),
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
+		.rot_standard_ref = &base_standard_ref,
+		.default_range = 4,  /* g */
+		.min_frequency = LSM6DSM_ODR_MIN_VAL,
+		.max_frequency = LSM6DSM_ODR_MAX_VAL,
+		.config = {
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 13000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+		},
+	},
+	[BASE_GYRO] = {
+		.name = "Base Gyro",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LSM6DSM,
+		.type = MOTIONSENSE_TYPE_GYRO,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &lsm6dsm_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
+				MOTIONSENSE_TYPE_GYRO),
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
+		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = LSM6DSM_ODR_MIN_VAL,
+		.max_frequency = LSM6DSM_ODR_MAX_VAL,
+	},
+};
+
+unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+struct motion_sensor_t bma422_lid_accel = {
+	.name = "Lid Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_BMA422,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_LID,
+	.drv = &bma4_accel_drv,
+	.mutex = &g_lid_mutex,
+	.drv_data = &g_bma422_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = BMA4_I2C_ADDR_PRIMARY,
+	.rot_standard_ref = &lid_standard_ref,
+	.default_range = 2,
+	.min_frequency = BMA4_ACCEL_MIN_FREQ,
+	.max_frequency = BMA4_ACCEL_MAX_FREQ,
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 12500 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+		/* Sensor on in S3 */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 12500 | ROUND_UP_FLAG,
+			.ec_rate = 0,
+		},
+	},
+};
+
+static void board_update_motion_sensor_config(void)
+{
+	if (get_cbi_ssfc_lid_sensor() == SSFC_SENSOR_BMA422)
+		motion_sensors[LID_ACCEL] = bma422_lid_accel;
+}
+
+static const struct ec_response_keybd_config lantis_keybd_backlight = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_FORWARD,		/* T2 */
+		TK_REFRESH,		/* T3 */
+		TK_FULLSCREEN,		/* T4 */
+		TK_OVERVIEW,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	/* No function keys, no numeric keypad and no screenlock key */
+};
+
+static const struct ec_response_keybd_config landia_keybd = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_FORWARD,		/* T2 */
+		TK_REFRESH,		/* T3 */
+		TK_FULLSCREEN,		/* T4 */
+		TK_OVERVIEW,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+	/* No function keys and no numeric keypad */
+};
+
+static const struct ec_response_keybd_config landrid_keybd_backlight = {
+	.num_top_row_keys = 13,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_KBD_BKLIGHT_TOGGLE,	/* T8 */
+		TK_PLAY_PAUSE,		/* T9 */
+		TK_MICMUTE,		/* T10 */
+		TK_VOL_MUTE,		/* T11 */
+		TK_VOL_DOWN,		/* T12 */
+		TK_VOL_UP,		/* T13 */
+	},
+	.capabilities = KEYBD_CAP_NUMERIC_KEYPAD,
+	/* No function keys and no screenlock key */
+};
+
+static const struct ec_response_keybd_config landrid_keybd = {
+	.num_top_row_keys = 13,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_PLAY_PAUSE,		/* T8 */
+		TK_MICMUTE,		/* T9 */
+		TK_VOL_MUTE,		/* T10 */
+		TK_VOL_DOWN,		/* T11 */
+		TK_VOL_UP,		/* T12 */
+		TK_MENU,		/* T13 */
+	},
+	.capabilities = KEYBD_CAP_NUMERIC_KEYPAD,
+	/* No function keys and no screenlock key */
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	if (get_cbi_fw_config_numeric_pad()) {
+		if (get_cbi_fw_config_kblight())
+			return &landrid_keybd_backlight;
+		else
+			return &landrid_keybd;
+	} else {
+		if (get_cbi_fw_config_tablet_mode())
+			return &landia_keybd;
+		else
+			return &lantis_keybd_backlight;
+	}
+}
+
+__override uint8_t board_keyboard_row_refresh(void)
+{
+	if (gpio_get_level(GPIO_EC_VIVALDIKEYBOARD_ID))
+		return 3;
+	else
+		return 2;
+}
+
+static void board_update_no_keypad_by_fwconfig(void)
+{
+	if (!get_cbi_fw_config_numeric_pad()) {
+		/* Disable scanning KSO13 & 14 if keypad isn't present. */
+		keyboard_raw_set_cols(KEYBOARD_COLS_NO_KEYPAD);
+		keyscan_config.actual_key_mask[11] = 0xfa;
+		keyscan_config.actual_key_mask[12] = 0xca;
+	}
+}
+
+static void board_update_keyboard_layout(void)
+{
+	if (get_cbi_fw_config_keyboard() == KB_LAYOUT_1) {
+		/*
+		 * If keyboard is UK(KB_LAYOUT_1), we need translate right ctrl
+		 * to backslash(\|) key.
+		 */
+		set_scancode_set2(4, 0, get_scancode_set2(2, 7));
+	}
+}
+
+void board_init(void)
+{
+	int on;
+	enum fw_config_db db = get_cbi_fw_config_db();
+
+	if (db == DB_1A_HDMI || db == DB_LTE_HDMI || db == DB_1A_HDMI_LTE) {
+		/* Select HDMI option */
+		gpio_set_level(GPIO_HDMI_SEL_L, 0);
+	} else {
+		/* Select AUX option */
+		gpio_set_level(GPIO_HDMI_SEL_L, 1);
+	}
+
+	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_INT_ODL);
+
+	/* Store board version for use in determining charge limits */
+	cbi_get_board_version(&board_version);
+
+	/*
+	 * If interrupt lines are already low, schedule them to be processed
+	 * after inits are completed.
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL))
+		hook_call_deferred(&check_c0_line_data, 0);
+	if (!gpio_get_level(GPIO_USB_C1_INT_ODL))
+		hook_call_deferred(&check_c1_line_data, 0);
+
+	gpio_enable_interrupt(GPIO_USB_C0_CCSBU_OVP_ODL);
+
+	if (get_cbi_fw_config_tablet_mode() == TABLET_MODE_PRESENT) {
+		motion_sensor_count = ARRAY_SIZE(motion_sensors);
+		/* Enable Base Accel interrupt */
+		gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
+
+		board_update_motion_sensor_config();
+	} else {
+		motion_sensor_count = 0;
+		gmr_tablet_switch_disable();
+		/* Base accel is not stuffed, don't allow line to float */
+		gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L,
+			       GPIO_INPUT | GPIO_PULL_DOWN);
+	}
+
+	gpio_enable_interrupt(GPIO_PEN_DET_ODL);
+
+	/* Charger on the MB will be outputting PROCHOT_ODL and OD CHG_DET */
+	sm5803_configure_gpio0(CHARGER_PRIMARY, GPIO0_MODE_PROCHOT, 1);
+	sm5803_configure_chg_det_od(CHARGER_PRIMARY, 1);
+
+	if (board_get_charger_chip_count() > 1) {
+		/* Charger on the sub-board will be a push-pull GPIO */
+		sm5803_configure_gpio0(CHARGER_SECONDARY, GPIO0_MODE_OUTPUT, 0);
+	}
+
+	/* Turn on 5V if the system is on, otherwise turn it off */
+	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
+			      CHIPSET_STATE_SOFT_OFF);
+	board_power_5v_enable(on);
+
+	board_update_no_keypad_by_fwconfig();
+	board_update_keyboard_layout();
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+static void board_resume(void)
+{
+	sm5803_disable_low_power_mode(CHARGER_PRIMARY);
+	if (board_get_charger_chip_count() > 1)
+		sm5803_disable_low_power_mode(CHARGER_SECONDARY);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_resume, HOOK_PRIO_DEFAULT);
+
+static void board_suspend(void)
+{
+	sm5803_enable_low_power_mode(CHARGER_PRIMARY);
+	if (board_get_charger_chip_count() > 1)
+		sm5803_enable_low_power_mode(CHARGER_SECONDARY);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_suspend, HOOK_PRIO_DEFAULT);
+
+void board_hibernate(void)
+{
+	/*
+	 * Put all charger ICs present into low power mode before entering
+	 * z-state.
+	 */
+	sm5803_hibernate(CHARGER_PRIMARY);
+	if (board_get_charger_chip_count() > 1)
+		sm5803_hibernate(CHARGER_SECONDARY);
+}
+
+__override void board_ocpc_init(struct ocpc_data *ocpc)
+{
+	/* There's no provision to measure Isys */
+	ocpc->chg_flags[CHARGER_SECONDARY] |= OCPC_NO_ISYS_MEAS_CAP;
+}
+
+__override void board_pulse_entering_rw(void)
+{
+	/*
+	 * On the ITE variants, the EC_ENTERING_RW signal was connected to a pin
+	 * which is active high by default.  This causes Cr50 to think that the
+	 * EC has jumped to its RW image even though this may not be the case.
+	 * The pin is changed to GPIO_EC_ENTERING_RW2.
+	 */
+	gpio_set_level(GPIO_EC_ENTERING_RW, 1);
+	gpio_set_level(GPIO_EC_ENTERING_RW2, 1);
+	usleep(MSEC);
+	gpio_set_level(GPIO_EC_ENTERING_RW, 0);
+	gpio_set_level(GPIO_EC_ENTERING_RW2, 0);
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * Nothing to do.  TCPC C0 is internal, TCPC C1 reset pin is not
+	 * connected to the EC.
+	 */
+}
+
+__override void board_power_5v_enable(int enable)
+{
+	/*
+	 * Motherboard has a GPIO to turn on the 5V regulator, but the sub-board
+	 * sets it through the charger GPIO.
+	 */
+	gpio_set_level(GPIO_EN_PP5000, !!enable);
+
+	if (board_get_charger_chip_count() > 1) {
+		if (sm5803_set_gpio0_level(1, !!enable))
+			CPRINTUSB("Failed to %sable sub rails!",
+				  enable ? "en" : "dis");
+	}
+}
+
+__override uint8_t board_get_usb_pd_port_count(void)
+{
+	enum fw_config_db db = get_cbi_fw_config_db();
+
+	if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI ||
+	    db == DB_1A_HDMI_LTE)
+		return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
+	else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A ||
+		 db == DB_1C_1A_LTE)
+		return CONFIG_USB_PD_PORT_MAX_COUNT;
+
+	ccprints("Unhandled DB configuration: %d", db);
+	return 0;
+}
+
+__override uint8_t board_get_charger_chip_count(void)
+{
+	enum fw_config_db db = get_cbi_fw_config_db();
+
+	if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI ||
+	    db == DB_1A_HDMI_LTE)
+		return CHARGER_NUM - 1;
+	else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A ||
+		 db == DB_1C_1A_LTE)
+		return CHARGER_NUM;
+
+	ccprints("Unhandled DB configuration: %d", db);
+	return 0;
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	/*
+	 * TCPC 0 is embedded in the EC and processes interrupts in the chip
+	 * code (it83xx/intc.c)
+	 */
+
+	uint16_t status = 0;
+	int regval;
+
+	/* Check whether TCPC 1 pulled the shared interrupt line */
+	if (!gpio_get_level(GPIO_USB_C1_INT_ODL)) {
+		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
+			if (regval)
+				status = PD_STATUS_TCPC_ALERT_1;
+		}
+	}
+
+	return status;
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_valid_port = (port >= 0 && port < board_get_usb_pd_port_count());
+
+	if (!is_valid_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTUSB("Disabling all charge ports");
+
+		sm5803_vbus_sink_enable(CHARGER_PRIMARY, 0);
+
+		if (board_get_charger_chip_count() > 1)
+			sm5803_vbus_sink_enable(CHARGER_SECONDARY, 0);
+
+		return EC_SUCCESS;
+	}
+
+	CPRINTUSB("New chg p%d", port);
+
+	/*
+	 * Ensure other port is turned off, then enable new charge port
+	 */
+	if (port == 0) {
+		if (board_get_charger_chip_count() > 1)
+			sm5803_vbus_sink_enable(CHARGER_SECONDARY, 0);
+		sm5803_vbus_sink_enable(CHARGER_PRIMARY, 1);
+
+	} else {
+		sm5803_vbus_sink_enable(CHARGER_PRIMARY, 0);
+		sm5803_vbus_sink_enable(CHARGER_SECONDARY, 1);
+	}
+
+	return EC_SUCCESS;
+}
+
+/* Vconn control for integrated ITE TCPC */
+void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
+{
+	/* Vconn control is only for port 0 */
+	if (port)
+		return;
+
+	if (cc_pin == USBPD_CC_PIN_1)
+		gpio_set_level(GPIO_EN_USB_C0_CC1_VCONN, !!enabled);
+	else
+		gpio_set_level(GPIO_EN_USB_C0_CC2_VCONN, !!enabled);
+}
+
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	int current;
+
+	if (port < 0 || port > board_get_usb_pd_port_count())
+		return;
+
+	current = (rp == TYPEC_RP_3A0) ? 3000 : 1500;
+
+	charger_set_otg_current_voltage(port, current, 5000);
+}
+
+__override uint16_t board_get_ps8xxx_product_id(int port)
+{
+	/* Lantis variant doesn't have ps8xxx product in the port 0 */
+	if (port == 0)
+		return 0;
+
+	switch (get_cbi_ssfc_tcpc_p1()) {
+	case SSFC_TCPC_P1_PS8805:
+		return PS8805_PRODUCT_ID;
+	case SSFC_TCPC_P1_DEFAULT:
+	case SSFC_TCPC_P1_PS8705:
+	default:
+		return PS8705_PRODUCT_ID;
+	}
+}
+
+/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
+const struct pwm_t pwm_channels[] = { [PWM_CH_KBLIGHT] = {
+					      .channel = 0,
+					      .flags = PWM_CONFIG_DSLEEP,
+					      .freq_hz = 100,
+				      } };
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+/* Thermistors */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "Charger",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
+	[TEMP_SENSOR_4] = { .name = "5V regular",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_4 },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/* This callback disables keyboard when convertibles are fully open */
+__override void lid_angle_peripheral_enable(int enable)
+{
+	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
+
+	/*
+	 * If the lid is in tablet position via other sensors,
+	 * ignore the lid angle, which might be faulty then
+	 * disable keyboard.
+	 */
+	if (tablet_get_mode())
+		enable = 0;
+
+	if (enable) {
+		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
+	} else {
+		/*
+		 * Ensure that the chipset is off before disabling the keyboard.
+		 * When the chipset is on, the EC keeps the keyboard enabled and
+		 * the AP decides whether to ignore input devices or not.
+		 */
+		if (!chipset_in_s0)
+			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
+	}
+}
+
+__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+				       int *ki_div, int *kd, int *kd_div)
+{
+	*kp = 3;
+	*kp_div = 20;
+
+	*ki = 3;
+	*ki_div = 125;
+
+	*kd = 4;
+	*kd_div = 40;
+}
+
+#ifdef CONFIG_KEYBOARD_FACTORY_TEST
+/*
+ * Map keyboard connector pins to EC GPIO pins for factory test.
+ * Pins mapped to {-1, -1} are skipped.
+ * The connector has 24 pins total, and there is no pin 0.
+ */
+const int keyboard_factory_scan_pins[][2] = {
+	{ -1, -1 },	   { GPIO_KSO_H, 4 }, { GPIO_KSO_H, 0 },
+	{ GPIO_KSO_H, 1 }, { GPIO_KSO_H, 3 }, { GPIO_KSO_H, 2 },
+	{ GPIO_KSO_L, 5 }, { GPIO_KSO_L, 6 }, { GPIO_KSO_L, 3 },
+	{ GPIO_KSO_L, 2 }, { GPIO_KSI, 0 },   { GPIO_KSO_L, 1 },
+	{ GPIO_KSO_L, 4 }, { GPIO_KSI, 3 },   { GPIO_KSI, 2 },
+	{ GPIO_KSO_L, 0 }, { GPIO_KSI, 5 },   { GPIO_KSI, 4 },
+	{ GPIO_KSO_L, 7 }, { GPIO_KSI, 6 },   { GPIO_KSI, 7 },
+	{ GPIO_KSI, 1 },   { -1, -1 },	      { -1, -1 },
+	{ -1, -1 },
+};
+
+const int keyboard_factory_scan_pins_used =
+	ARRAY_SIZE(keyboard_factory_scan_pins);
+#endif
diff --git a/board/lantis/board.h b/board/lantis/board.h
new file mode 100644
index 0000000000..7447dcbf31
--- /dev/null
+++ b/board/lantis/board.h
@@ -0,0 +1,151 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Lantis board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* Select Baseboard features */
+#define VARIANT_DEDEDE_EC_IT8320
+#include "baseboard.h"
+
+#undef GPIO_VOLUME_UP_L
+#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL_HDMI_HPD
+
+/* Battery */
+#define CONFIG_BATTERY_FUEL_GAUGE
+
+/* BC 1.2 */
+#define CONFIG_BC12_DETECT_PI3USB9201
+
+/* Charger */
+#define CONFIG_CHARGE_RAMP_HW
+#define CONFIG_CHARGER_SM5803 /* C0 and C1: Charger */
+#define PD_MAX_VOLTAGE_MV 15000
+#define CONFIG_USB_PD_VBUS_DETECT_CHARGER
+#define CONFIG_USB_PD_5V_CHARGER_CTRL
+#define CONFIG_CHARGER_OTG
+#undef CONFIG_CHARGER_SINGLE_CHIP
+#define CONFIG_OCPC
+#define CONFIG_OCPC_DEF_RBATT_MOHMS               \
+	21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr \
+	    */
+
+/* PWM */
+#define CONFIG_PWM
+
+/* Sensors */
+#define CONFIG_ACCEL_BMA255 /* Lid accel */
+#define CONFIG_ACCEL_BMA4XX /* 2nd source Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
+/* Sensors without hardware FIFO are in forced mode */
+#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
+
+/* Enable sensor fifo, must also define the _SIZE and _THRES */
+#define CONFIG_ACCEL_FIFO
+/* Power of 2 - Too large of a fifo causes too much timestamp jitter */
+#define CONFIG_ACCEL_FIFO_SIZE 256
+#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
+
+#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
+
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_UPDATE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+
+#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+#define CONFIG_TABLET_MODE
+#define CONFIG_TABLET_MODE_SWITCH
+#define CONFIG_GMR_TABLET_MODE
+
+/* Keyboard */
+#define CONFIG_KEYBOARD_FACTORY_TEST
+#define CONFIG_PWM_KBLIGHT
+#define CONFIG_KEYBOARD_KEYPAD
+
+/* TCPC */
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0: ITE EC TCPC */
+#define CONFIG_USB_PD_TCPM_MULTI_PS8XXX
+#define CONFIG_USB_PD_TCPM_PS8705 /* C1: PS8705 TCPC */
+#define CONFIG_USB_PD_TCPM_PS8805 /* C1: second source PS8805 TCPC */
+#define CONFIG_USB_PD_TCPM_PS8805_FORCE_DID
+#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1
+#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+#define CONFIG_USB_PD_TCPC_LOW_POWER
+
+/* Thermistors */
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_THERMISTOR
+#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
+
+/* USB Mux and Retimer */
+#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */
+
+/* USB Type A Features */
+#define USB_PORT_COUNT 1
+#define CONFIG_USB_PORT_POWER_DUMB
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum chg_id {
+	CHARGER_PRIMARY,
+	CHARGER_SECONDARY,
+	CHARGER_NUM,
+};
+
+enum pwm_channel {
+	PWM_CH_KBLIGHT,
+	PWM_CH_COUNT,
+};
+
+/* Motion sensors */
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
+
+/* ADC channels */
+enum adc_channel {
+	ADC_VSNS_PP3300_A, /* ADC0 */
+	ADC_TEMP_SENSOR_1, /* ADC2 */
+	ADC_TEMP_SENSOR_2, /* ADC3 */
+	ADC_SUB_ANALOG, /* ADC13 */
+	ADC_TEMP_SENSOR_3, /* ADC15 */
+	ADC_TEMP_SENSOR_4, /* ADC16 */
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1,
+	TEMP_SENSOR_2,
+	TEMP_SENSOR_3,
+	TEMP_SENSOR_4,
+	TEMP_SENSOR_COUNT
+};
+
+/* List of possible batteries */
+enum battery_type {
+	BATTERY_DYNAPACK_COS,
+	BATTERY_DYNAPACK_ATL,
+	BATTERY_SIMPLO_COS,
+	BATTERY_SIMPLO_HIGHPOWER,
+	BATTERY_COS,
+	BATTERY_DYNAPACK_COS_44WH,
+	BATTERY_DYNAPACK_ATL_44WH,
+	BATTERY_SIMPLO_HIGHPOWER_44WH,
+	BATTERY_TYPE_COUNT,
+};
+
+enum ec_cfg_keyboard_layout { KB_LAYOUT_DEFAULT = 0, KB_LAYOUT_1 = 1 };
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/lantis/build.mk b/board/lantis/build.mk
new file mode 100644
index 0000000000..9b862c7624
--- /dev/null
+++ b/board/lantis/build.mk
@@ -0,0 +1,15 @@
+# -*- makefile -*-
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=it83xx
+CHIP_FAMILY:=it8320
+CHIP_VARIANT:=it8320dx
+BASEBOARD:=dedede
+
+board-y=board.o cbi_ssfc.o led.o usb_pd_policy.o
+board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/lantis/cbi_ssfc.c b/board/lantis/cbi_ssfc.c
new file mode 100644
index 0000000000..324ceffb63
--- /dev/null
+++ b/board/lantis/cbi_ssfc.c
@@ -0,0 +1,41 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi_ssfc.h"
+#include "common.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "hooks.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+/* Cache SSFC on init since we don't expect it to change in runtime */
+static union dedede_cbi_ssfc cached_ssfc;
+BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
+
+static void cbi_ssfc_init(void)
+{
+	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
+		/* Default to 0 when CBI isn't populated */
+		cached_ssfc.raw_value = 0;
+
+	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
+}
+DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
+
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
+{
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
+}
+
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
+{
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
+}
+
+enum ec_ssfc_tcpc_p1 get_cbi_ssfc_tcpc_p1(void)
+{
+	return (enum ec_ssfc_tcpc_p1)cached_ssfc.tcpc_type;
+}
diff --git a/board/lantis/cbi_ssfc.h b/board/lantis/cbi_ssfc.h
new file mode 100644
index 0000000000..626fe62498
--- /dev/null
+++ b/board/lantis/cbi_ssfc.h
@@ -0,0 +1,95 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _DEDEDE_CBI_SSFC__H_
+#define _DEDEDE_CBI_SSFC__H_
+
+#include "stdint.h"
+
+/****************************************************************************
+ * Dedede CBI Second Source Factory Cache
+ */
+
+/*
+ * Base Sensor (Bits 0-2)
+ */
+enum ec_ssfc_base_sensor {
+	SSFC_SENSOR_BASE_DEFAULT = 0,
+	SSFC_SENSOR_BMI160 = 1,
+	SSFC_SENSOR_ICM426XX = 2,
+	SSFC_SENSOR_LSM6DSM = 3,
+	SSFC_SENSOR_ICM42607 = 4
+};
+
+/*
+ * Lid Sensor (Bits 3-5)
+ */
+enum ec_ssfc_lid_sensor {
+	SSFC_SENSOR_LID_DEFAULT = 0,
+	SSFC_SENSOR_BMA255 = 1,
+	SSFC_SENSOR_BMA422 = 2,
+};
+
+/*
+ * TCPC Port 1 (Bits 6-7)
+ */
+enum ec_ssfc_tcpc_p1 {
+	SSFC_TCPC_P1_DEFAULT,
+	SSFC_TCPC_P1_PS8705,
+	SSFC_TCPC_P1_PS8805,
+};
+
+/*
+ * Audio Codec Source(Bit 8-10)
+ */
+enum ec_ssfc_audio_codec_source {
+	SSFC_AUDIO_CODEC_DEFAULT = 0,
+	SSFC_AUDIO_CODEC_VD = 1,
+	SSFC_ADUIO_CODEC_VS = 2,
+};
+
+/*
+ * Touchscreen Driver Source(Bit 11-13)
+ */
+enum ec_ssfc_ts_driver_source {
+	SSFC_TS_DRIVER_DEFAULT = 0,
+	SSFC_TS_DRIVER_GENERIC = 1,
+	SSFC_TS_DRIVER_HID = 2,
+};
+
+union dedede_cbi_ssfc {
+	struct {
+		uint32_t base_sensor : 3;
+		uint32_t lid_sensor : 3;
+		uint32_t tcpc_type : 2;
+		uint32_t audio_codec_source : 3;
+		uint32_t ts_driver_source : 3;
+		uint32_t reserved_2 : 18;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Get the Base sensor type from SSFC_CONFIG.
+ *
+ * @return the Base sensor board type.
+ */
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
+
+/**
+ * Get the Lid sensor type from SSFC_CONFIG.
+ *
+ * @return the Lid sensor board type.
+ */
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
+
+/**
+ * Get the TCPC port 1 type from SSFC_CONFIG.
+ *
+ * @return the TCPC type.
+ */
+enum ec_ssfc_tcpc_p1 get_cbi_ssfc_tcpc_p1(void);
+
+#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/lantis/ec.tasklist b/board/lantis/ec.tasklist
new file mode 100644
index 0000000000..c3c360febb
--- /dev/null
+++ b/board/lantis/ec.tasklist
@@ -0,0 +1,24 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, TRENTA_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, ULTRA_TASK_STACK_SIZE) \
+        TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+        TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+        TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/lantis/gpio.inc b/board/lantis/gpio.inc
new file mode 100644
index 0000000000..6afb9ccc4b
--- /dev/null
+++ b/board/lantis/gpio.inc
@@ -0,0 +1,146 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+/* Power State interrupts */
+GPIO_INT(SLP_S4_L,		PIN(I, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,		PIN(H, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(SLP_S0_L,		PIN(E, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,		PIN(G, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID0,	PIN(D, 0), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(RSMRST_PWRGD_L,	PIN(E, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(CPU_C10_GATE_L,	PIN(G, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_DRAM_OD,		PIN(D, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(PG_PP1050_ST_OD,	PIN(L, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID1,	PIN(K, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_VCCIO_EXT_OD,	PIN(D, 7), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(ESPI_RESET_L, 	 PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt)
+
+GPIO_INT(H1_EC_PWR_BTN_ODL,	PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
+#ifdef CONFIG_LOW_POWER_IDLE
+/* Used to wake up the EC from Deep Doze mode when writing to console */
+GPIO_INT(UART1_RX,	 PIN(B, 0), GPIO_INT_BOTH, uart_deepsleep_interrupt)	/* UART_DBG_TX_EC_RX */
+#endif
+
+/* USB-C interrupts */
+GPIO_INT(USB_C0_INT_ODL,	PIN(K, 0), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt) /* BC12 and charger */
+GPIO_INT(USB_C1_INT_ODL,	PIN(E, 6), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c1_interrupt) /* TCPC, charger, BC12 */
+GPIO_INT(USB_C0_CCSBU_OVP_ODL,	PIN(K, 6), GPIO_INT_FALLING | GPIO_PULL_UP, c0_ccsbu_ovp_interrupt) /* Fault protection */
+
+/* Other interrupts */
+GPIO_INT(LID_OPEN,		PIN(F, 3), GPIO_INT_BOTH, lid_interrupt)
+GPIO_INT(LID_360_L,		PIN(A, 7), GPIO_INT_BOTH, gmr_tablet_switch_isr)
+GPIO_INT(VOLDN_BTN_ODL,		PIN(I, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(VOLUP_BTN_ODL_HDMI_HPD,	PIN(I, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_sub_hdmi_hpd_interrupt)
+GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(J, 0), GPIO_INT_FALLING | GPIO_SEL_1P8V, lsm6dsm_interrupt)
+GPIO_INT(EC_WP_OD,		PIN(A, 6), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(PEN_DET_ODL,		PIN(J, 1), GPIO_INT_BOTH | GPIO_PULL_UP, pen_detect_interrupt)
+
+/* Power sequence GPIOs */
+GPIO(EC_AP_RTCRST,		PIN(K, 2), GPIO_OUT_LOW)
+GPIO(EC_AP_PWR_BTN_ODL,		PIN(B, 6), GPIO_ODR_HIGH)
+GPIO(EC_AP_DPWROK,		PIN(L, 7), GPIO_OUT_LOW)
+GPIO(EC_AP_RSMRST_L,		PIN(H, 0), GPIO_OUT_LOW)
+GPIO(EC_AP_WAKE_ODL,		PIN(D, 5), GPIO_ODR_HIGH)
+GPIO(SYS_RST_ODL,		PIN(D, 1), GPIO_ODR_HIGH)
+GPIO(EC_AP_SYS_PWROK,		PIN(F, 2), GPIO_OUT_LOW)
+GPIO(PG_PP5000_U_OD,		PIN(E, 3), GPIO_INPUT)
+GPIO(EN_PP3300_A,		PIN(C, 5), GPIO_OUT_LOW)
+GPIO(EC_AP_PCH_PWROK_OD,	PIN(D, 6), GPIO_ODR_LOW)
+GPIO(EN_PP5000_U,		PIN(K, 5), GPIO_OUT_LOW)
+/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
+GPIO(EN_VCCST,			PIN(D, 4), GPIO_INPUT)
+GPIO(EN_VCCIO_EXT,		PIN(B, 2), GPIO_OUT_LOW)
+GPIO(EC_PROCHOT_ODL,		PIN(I, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(EC_AP_VCCST_PWRGD_OD,	PIN(E, 5), GPIO_ODR_LOW)
+GPIO(ALL_SYS_PWRGD,		PIN(B, 7), GPIO_OUT_LOW)
+GPIO(EN_SLP_Z,			PIN(K, 3), GPIO_OUT_LOW)
+
+/* Required for icelake chipset code, but implemented through other means for dedede */
+UNIMPLEMENTED(AC_PRESENT)
+UNIMPLEMENTED(PG_EC_DSW_PWROK)
+UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
+
+/* I2C pins - Alternate function below configures I2C module on these pins */
+GPIO(EC_I2C_EEPROM_SCL,		PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SDA,		PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SCL,	PIN(C, 1), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SDA,	PIN(C, 2), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,		PIN(F, 6), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SENSOR_SDA,		PIN(F, 7), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SUB_USB_C1_SCL,	PIN(E, 0), GPIO_INPUT)
+GPIO(EC_I2C_SUB_USB_C1_SDA,	PIN(E, 7), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SCL,		PIN(A, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SDA,		PIN(A, 5), GPIO_INPUT)
+
+/* USB pins */
+GPIO(EN_USB_A_5V,			PIN(L, 6), GPIO_OUT_LOW)
+GPIO(EN_USB_C0_CC1_VCONN,	PIN(H, 4), GPIO_OUT_LOW)
+GPIO(EN_USB_C0_CC2_VCONN,	PIN(H, 6), GPIO_OUT_LOW)
+GPIO(EC_AP_USB_C0_HPD,		PIN(L, 4), GPIO_OUT_LOW)
+GPIO(EC_AP_USB_C1_HDMI_HPD,	PIN(K, 7), GPIO_OUT_LOW)
+GPIO(USB_C0_FRS,		PIN(C, 4), GPIO_OUT_LOW)
+GPIO(HDMI_SEL_L,		PIN(C, 6), GPIO_OUT_HIGH)
+
+/* MKBP event synchronization */
+GPIO(EC_AP_MKBP_INT_L,	PIN(L, 5), GPIO_ODR_HIGH)
+
+/* Misc */
+GPIO(EN_BL_OD,			PIN(K, 4), GPIO_ODR_LOW)
+GPIO(EC_ENTERING_RW,		PIN(G, 0), GPIO_OUT_LOW)
+GPIO(EC_ENTERING_RW2,		PIN(C, 7), GPIO_OUT_LOW)
+GPIO(CCD_MODE_ODL,		PIN(H, 5), GPIO_ODR_HIGH)
+GPIO(EC_BATTERY_PRES_ODL,	PIN(I, 4), GPIO_INPUT)
+GPIO(EN_KB_BL,			PIN(J, 3), GPIO_OUT_LOW) /* Currently unused */
+GPIO(ECH1_PACKET_MODE,		PIN(H, 1), GPIO_OUT_LOW)
+GPIO(EN_PP5000_PEN,		PIN(B, 5), GPIO_OUT_LOW)
+GPIO(EC_VIVALDIKEYBOARD_ID, PIN(J, 4), GPIO_INPUT | GPIO_PULL_DOWN)	/* keyboard ID */
+
+/* NC pins, enable internal pull-down to avoid floating state. */
+GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOC3_NC, PIN(C, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG3_NC, PIN(G, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG4_NC, PIN(G, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG5_NC, PIN(G, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG6_NC, PIN(G, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG7_NC, PIN(G, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ5_NC, PIN(J, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ6_NC, PIN(J, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOM6_NC, PIN(M, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+
+/* LED */
+GPIO(BAT_LED_AMBER_C0,	 PIN(A, 1), GPIO_OUT_HIGH)
+GPIO(BAT_LED_WHITE_C0,	 PIN(A, 2), GPIO_OUT_HIGH)
+GPIO(BAT_LED_AMBER_C1,	 PIN(F, 1), GPIO_OUT_HIGH)
+GPIO(BAT_LED_WHITE_C1,	 PIN(F, 0), GPIO_OUT_HIGH)
+GPIO(PWR_LED_WHITE_L,	 PIN(A, 3), GPIO_OUT_HIGH)
+
+/* Alternate functions GPIO definitions */
+/* Keyboard */
+ALTERNATE(PIN_MASK(KSI,   0xFF), 0, MODULE_KEYBOARD_SCAN, 0)		/* KSI0-7 */
+ALTERNATE(PIN_MASK(KSO_H, 0xFF), 0, MODULE_KEYBOARD_SCAN, 0)		/* KSO8-15 */
+ALTERNATE(PIN_MASK(KSO_L, 0xFB), 0, MODULE_KEYBOARD_SCAN, 0)		/* KSO0-1, 3-7 */
+GPIO(EC_KSO_02_INV, PIN(KSO_L, 2), GPIO_OUT_HIGH)			/* KSO2 inverted */
+
+/* UART */
+ALTERNATE(PIN_MASK(B, BIT(0) | BIT(1)), 0, MODULE_UART, 0)		/* UART for debug */
+
+/* I2C */
+ALTERNATE(PIN_MASK(B, BIT(3) | BIT(4)), 0, MODULE_I2C, 0)		/* I2C0 */
+ALTERNATE(PIN_MASK(C, BIT(1) | BIT(2)), 0, MODULE_I2C, 0)		/* I2C1 */
+ALTERNATE(PIN_MASK(F, BIT(6) | BIT(7)), 0, MODULE_I2C, GPIO_SEL_1P8V)	/* I2C2 - 1.8V */
+ALTERNATE(PIN_MASK(E, BIT(0) | BIT(7)), 0, MODULE_I2C, 0)		/* I2C4 */
+ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), 0, MODULE_I2C, 0)		/* I2C5 */
+
+/* ADC */
+ALTERNATE(PIN_MASK(L, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0)	/* ADC13: EC_SUB_ANALOG, ADC15: TEMP_SENSOR_3, ADC16: TEMP_SENSOR_4 */
+ALTERNATE(PIN_MASK(I, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0)	/* ADC0: EC_VSNS_PP3300_A, ADC2: TEMP_SENSOR_1, ADC3: TEMP_SENSOR_2 */
+
+/* PWM */
+ALTERNATE(PIN_MASK(A, BIT(0)), 0, MODULE_PWM, 0) 			/* KB_BL_PWM */
diff --git a/board/lantis/led.c b/board/lantis/led.c
new file mode 100644
index 0000000000..cef6f57a5e
--- /dev/null
+++ b/board/lantis/led.c
@@ -0,0 +1,280 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Lantis specific LED settings. */
+
+#include "cbi_fw_config.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "led_common.h"
+
+#define BAT_LED_ON 0
+#define BAT_LED_OFF 1
+
+#define POWER_LED_ON 0
+#define POWER_LED_OFF 1
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_LEFT_LED,
+					     EC_LED_ID_RIGHT_LED,
+					     EC_LED_ID_POWER_LED };
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+enum led_color {
+	LED_OFF = 0,
+	LED_AMBER,
+	LED_WHITE,
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
+};
+
+enum led_port { LEFT_PORT = 0, RIGHT_PORT };
+
+static int led_set_color_battery(int port, enum led_color color)
+{
+	enum gpio_signal amber_led, white_led;
+
+	amber_led = (port == RIGHT_PORT ? GPIO_BAT_LED_AMBER_C1 :
+					  GPIO_BAT_LED_AMBER_C0);
+	white_led = (port == RIGHT_PORT ? GPIO_BAT_LED_WHITE_C1 :
+					  GPIO_BAT_LED_WHITE_C0);
+
+	switch (color) {
+	case LED_OFF:
+		gpio_set_level(white_led, BAT_LED_OFF);
+		gpio_set_level(amber_led, BAT_LED_OFF);
+		break;
+	case LED_WHITE:
+		gpio_set_level(white_led, BAT_LED_ON);
+		gpio_set_level(amber_led, BAT_LED_OFF);
+		break;
+	case LED_AMBER:
+		gpio_set_level(white_led, BAT_LED_OFF);
+		gpio_set_level(amber_led, BAT_LED_ON);
+		break;
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+	return EC_SUCCESS;
+}
+
+static int led_set_color_power(enum led_color color)
+{
+	switch (color) {
+	case LED_OFF:
+		gpio_set_level(GPIO_PWR_LED_WHITE_L, POWER_LED_OFF);
+		break;
+	case LED_WHITE:
+		gpio_set_level(GPIO_PWR_LED_WHITE_L, POWER_LED_ON);
+		break;
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+	return EC_SUCCESS;
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	switch (led_id) {
+	case EC_LED_ID_LEFT_LED:
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		break;
+	case EC_LED_ID_RIGHT_LED:
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		break;
+	case EC_LED_ID_POWER_LED:
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		break;
+	default:
+		break;
+	}
+}
+
+static int led_set_color(enum ec_led_id led_id, enum led_color color)
+{
+	int rv;
+
+	switch (led_id) {
+	case EC_LED_ID_RIGHT_LED:
+		rv = led_set_color_battery(RIGHT_PORT, color);
+		break;
+	case EC_LED_ID_LEFT_LED:
+		rv = led_set_color_battery(LEFT_PORT, color);
+		break;
+	case EC_LED_ID_POWER_LED:
+		rv = led_set_color_power(color);
+		break;
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+	return rv;
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (brightness[EC_LED_COLOR_WHITE] != 0)
+		led_set_color(led_id, LED_WHITE);
+	else if (brightness[EC_LED_COLOR_AMBER] != 0)
+		led_set_color(led_id, LED_AMBER);
+	else
+		led_set_color(led_id, LED_OFF);
+
+	return EC_SUCCESS;
+}
+
+/*
+ * lantis use old led policy.
+ * Use cbi fw_config to distinguish lantis from other boards.
+ *		numeric_pad	tablet mode
+ * lantis	N		N
+ * landrid	Y		N
+ * landia	N		Y
+ */
+static bool is_led_old_policy(void)
+{
+	if (get_cbi_fw_config_numeric_pad() == NUMERIC_PAD_ABSENT &&
+	    get_cbi_fw_config_tablet_mode() == TABLET_MODE_ABSENT)
+		return 1;
+	else
+		return 0;
+}
+
+/*
+ * Set active charge port color to the parameter, turn off all others.
+ * If no port is active (-1), turn off all LEDs.
+ */
+static void set_active_port_color(enum led_color color)
+{
+	int port = charge_manager_get_active_charge_port();
+
+	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
+		led_set_color_battery(RIGHT_PORT,
+				      (port == RIGHT_PORT) ? color : LED_OFF);
+	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
+		led_set_color_battery(LEFT_PORT,
+				      (port == LEFT_PORT) ? color : LED_OFF);
+}
+
+static void led_set_battery(void)
+{
+	static int battery_ticks;
+	static int power_ticks;
+
+	battery_ticks++;
+
+	/*
+	 * Override battery LED for clamshell SKU, which doesn't have power
+	 * LED, blinking battery white LED to indicate system suspend without
+	 * charging.
+	 */
+	if (get_cbi_fw_config_tablet_mode() == TABLET_MODE_ABSENT) {
+		if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
+		    led_pwr_get_state() != LED_PWRS_CHARGE) {
+			power_ticks++;
+
+			led_set_color_battery(RIGHT_PORT, power_ticks & 0x2 ?
+								  LED_WHITE :
+								  LED_OFF);
+			led_set_color_battery(LEFT_PORT, power_ticks & 0x2 ?
+								 LED_WHITE :
+								 LED_OFF);
+			return;
+		}
+	}
+
+	power_ticks = 0;
+
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
+		set_active_port_color(LED_AMBER);
+		break;
+	case LED_PWRS_DISCHARGE_FULL:
+		if (extpower_is_present()) {
+			set_active_port_color(LED_WHITE);
+			break;
+		}
+		__fallthrough;
+	case LED_PWRS_DISCHARGE:
+		/*
+		 * Blink white/amber light (1 sec on, 1 sec off)
+		 * when battery capacity is less than 10%
+		 */
+		if (charge_get_percent() < 10) {
+			if (is_led_old_policy()) {
+				led_set_color_battery(RIGHT_PORT,
+						      (battery_ticks & 0x2) ?
+							      LED_WHITE :
+							      LED_OFF);
+			} else {
+				if (led_auto_control_is_enabled(
+					    EC_LED_ID_RIGHT_LED))
+					led_set_color_battery(
+						RIGHT_PORT,
+						(battery_ticks & 0x2) ?
+							LED_AMBER :
+							LED_OFF);
+				if (led_auto_control_is_enabled(
+					    EC_LED_ID_LEFT_LED))
+					led_set_color_battery(
+						LEFT_PORT,
+						(battery_ticks & 0x2) ?
+							LED_AMBER :
+							LED_OFF);
+			}
+		} else {
+			set_active_port_color(LED_OFF);
+		}
+		break;
+	case LED_PWRS_ERROR:
+		if (is_led_old_policy())
+			set_active_port_color(
+				(battery_ticks % 0x2) ? LED_WHITE : LED_OFF);
+		else
+			set_active_port_color(
+				(battery_ticks % 0x2) ? LED_AMBER : LED_OFF);
+		break;
+	case LED_PWRS_CHARGE_NEAR_FULL:
+		set_active_port_color(LED_WHITE);
+		break;
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		set_active_port_color(LED_WHITE);
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		set_active_port_color((battery_ticks & 0x2) ? LED_AMBER :
+							      LED_OFF);
+		break;
+	default:
+		/* Other states don't alter LED behavior */
+		break;
+	}
+}
+
+static void led_set_power(void)
+{
+	static int power_tick;
+
+	power_tick++;
+
+	if (chipset_in_state(CHIPSET_STATE_ON))
+		led_set_color_power(LED_WHITE);
+	else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
+		led_set_color_power((power_tick & 0x2) ? LED_WHITE : LED_OFF);
+	else
+		led_set_color_power(LED_OFF);
+}
+
+/* Called by hook task every TICK */
+static void led_tick(void)
+{
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		led_set_power();
+
+	led_set_battery();
+}
+DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
diff --git a/board/lantis/usb_pd_policy.c b/board/lantis/usb_pd_policy.c
new file mode 100644
index 0000000000..2433b25431
--- /dev/null
+++ b/board/lantis/usb_pd_policy.c
@@ -0,0 +1,74 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery_smart.h"
+#include "charge_manager.h"
+#include "charger.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "driver/charger/sm5803.h"
+#include "driver/tcpm/tcpci.h"
+#include "usb_pd.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+int pd_check_vconn_swap(int port)
+{
+	/* Allow VCONN swaps if the AP is on */
+	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
+}
+
+void pd_power_supply_reset(int port)
+{
+	int prev_en;
+
+	if (port < 0 || port >= board_get_usb_pd_port_count())
+		return;
+
+	prev_en = charger_is_sourcing_otg_power(port);
+
+	/* Disable Vbus */
+	charger_enable_otg_power(port, 0);
+
+	/* Discharge Vbus if previously enabled */
+	if (prev_en)
+		sm5803_set_vbus_disch(port, 1);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	enum ec_error_list rv;
+
+	/* Disable sinking */
+	rv = sm5803_vbus_sink_enable(port, 0);
+	if (rv)
+		return rv;
+
+	/* Disable Vbus discharge */
+	sm5803_set_vbus_disch(port, 0);
+
+	/* Provide Vbus */
+	charger_enable_otg_power(port, 1);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+__override bool pd_check_vbus_level(int port, enum vbus_level level)
+{
+	return sm5803_check_vbus_level(port, level);
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	return sm5803_is_vbus_present(port);
+}
diff --git a/board/lantis/vif_override.xml b/board/lantis/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/lantis/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/lazor/battery.c b/board/lazor/battery.c
index 6cad716e2c..61de35da12 100644
--- a/board/lazor/battery.c
+++ b/board/lazor/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/lazor/board.c b/board/lazor/board.c
index 6ef3e2c0f9..ecfa4ace6b 100644
--- a/board/lazor/board.c
+++ b/board/lazor/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,121 +7,49 @@
 
 #include "adc_chip.h"
 #include "button.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "extpower.h"
 #include "driver/accel_bma2x2.h"
+#include "driver/accel_kionix.h"
+#include "driver/accel_kx022.h"
 #include "driver/accelgyro_bmi_common.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
+#include "driver/accelgyro_icm426xx.h"
+#include "driver/accelgyro_icm_common.h"
+#include "driver/ln9310.h"
+#include "extpower.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "keyboard_scan.h"
 #include "lid_switch.h"
-#include "ln9310.h"
-#include "pi3usb9201.h"
+#include "mkbp_info.h"
 #include "power.h"
 #include "power_button.h"
 #include "pwm.h"
 #include "pwm_chip.h"
-#include "system.h"
 #include "shi_chip.h"
+#include "sku.h"
 #include "switch.h"
+#include "system.h"
 #include "tablet_mode.h"
 #include "task.h"
+#include "usbc_config.h"
 #include "usbc_ppc.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-/* Forward declaration */
-static void tcpc_alert_event(enum gpio_signal signal);
-static void usb0_evt(enum gpio_signal signal);
-static void usb1_evt(enum gpio_signal signal);
-static void ppc_interrupt(enum gpio_signal signal);
-static void board_connect_c0_sbu(enum gpio_signal s);
-static void switchcap_interrupt(enum gpio_signal signal);
+/* Disable debug messages to free flash space */
+#define CPRINTS(format, args...)
+#define CPRINTF(format, args...)
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
-static uint8_t sku_id;
-
-/* GPIO Interrupt Handlers */
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_PD_INT_ODL:
-		port = 0;
-		break;
-	case GPIO_USB_C1_PD_INT_ODL:
-		port = 1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-static void usb0_evt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
-}
-
-static void usb1_evt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12, 0);
-}
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_SWCTL_INT_ODL:
-		sn5s330_interrupt(0);
-		break;
-	case GPIO_USB_C1_SWCTL_INT_ODL:
-		sn5s330_interrupt(1);
-		break;
-	default:
-		break;
-	}
-}
-
-static void board_connect_c0_sbu_deferred(void)
-{
-	/*
-	 * If CCD_MODE_ODL asserts, it means there's a debug accessory connected
-	 * and we should enable the SBU FETs.
-	 */
-	ppc_set_sbu(0, 1);
-}
-DECLARE_DEFERRED(board_connect_c0_sbu_deferred);
-
-static void board_connect_c0_sbu(enum gpio_signal s)
-{
-	hook_call_deferred(&board_connect_c0_sbu_deferred_data, 0);
-}
-
-static void switchcap_interrupt(enum gpio_signal signal)
-{
-	ln9310_interrupt(signal);
-}
-
 /* Keyboard scan setting */
-struct keyboard_scan_config keyscan_config = {
+__override struct keyboard_scan_config keyscan_config = {
 	/* Use 80 us, because KSO_02 passes through the H1. */
 	.output_settle_us = 80,
 	/*
 	 * Unmask 0x08 in [0] (KSO_00/KSI_03, the new location of Search key);
 	 * as it still uses the legacy location (KSO_01/KSI_00).
 	 */
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca
-	},
+	.actual_key_mask = { 0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, 0xa4,
+			     0xff, 0xfe, 0x55, 0xfa, 0xca },
 	/* Other values should be the same as the default configuration. */
 	.debounce_down_us = 9 * MSEC,
 	.debounce_up_us = 30 * MSEC,
@@ -130,18 +58,50 @@ struct keyboard_scan_config keyscan_config = {
 	.poll_timeout_us = 100 * MSEC,
 };
 
+/*
+ * We have total 30 pins for keyboard connecter {-1, -1} mean
+ * the N/A pin that don't consider it and reserve index 0 area
+ * that we don't have pin 0.
+ */
+const int keyboard_factory_scan_pins[][2] = {
+	{ -1, -1 }, { 0, 5 },	{ 1, 1 },   { 1, 0 },	{ 0, 6 },   { 0, 7 },
+	{ -1, -1 }, { -1, -1 }, { 1, 4 },   { 1, 3 },	{ -1, -1 }, { 1, 6 },
+	{ 1, 7 },   { 3, 1 },	{ 2, 0 },   { 1, 5 },	{ 2, 6 },   { 2, 7 },
+	{ 2, 1 },   { 2, 4 },	{ 2, 5 },   { 1, 2 },	{ 2, 3 },   { 2, 2 },
+	{ 3, 0 },   { -1, -1 }, { -1, -1 }, { -1, -1 }, { -1, -1 }, { -1, -1 },
+	{ -1, -1 },
+};
+
+const int keyboard_factory_scan_pins_used =
+	ARRAY_SIZE(keyboard_factory_scan_pins);
+
 /* I2C port map */
 const struct i2c_port_t i2c_ports[] = {
-	{"power",   I2C_PORT_POWER,  100, GPIO_EC_I2C_POWER_SCL,
-					  GPIO_EC_I2C_POWER_SDA},
-	{"tcpc0",   I2C_PORT_TCPC0, 1000, GPIO_EC_I2C_USB_C0_PD_SCL,
-					  GPIO_EC_I2C_USB_C0_PD_SDA},
-	{"tcpc1",   I2C_PORT_TCPC1, 1000, GPIO_EC_I2C_USB_C1_PD_SCL,
-					  GPIO_EC_I2C_USB_C1_PD_SDA},
-	{"eeprom",  I2C_PORT_EEPROM, 400, GPIO_EC_I2C_EEPROM_SCL,
-					  GPIO_EC_I2C_EEPROM_SDA},
-	{"sensor",  I2C_PORT_SENSOR, 400, GPIO_EC_I2C_SENSOR_SCL,
-					  GPIO_EC_I2C_SENSOR_SDA},
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_POWER_SCL,
+	  .sda = GPIO_EC_I2C_POWER_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C0_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C0_PD_SDA },
+	{ .name = "tcpc1",
+	  .port = I2C_PORT_TCPC1,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C1_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C1_PD_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_EEPROM_SCL,
+	  .sda = GPIO_EC_I2C_EEPROM_SDA },
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_SENSOR_SCL,
+	  .sda = GPIO_EC_I2C_SENSOR_SDA },
 };
 
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
@@ -149,37 +109,22 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* Measure VBUS through a 1/10 voltage divider */
-	[ADC_VBUS] = {
-		"VBUS",
-		NPCX_ADC_CH1,
-		ADC_MAX_VOLT * 10,
-		ADC_READ_MAX + 1,
-		0
-	},
+	[ADC_VBUS] = { "VBUS", NPCX_ADC_CH1, ADC_MAX_VOLT * 10,
+		       ADC_READ_MAX + 1, 0 },
 	/*
 	 * Adapter current output or battery charging/discharging current (uV)
 	 * 18x amplification on charger side.
 	 */
-	[ADC_AMON_BMON] = {
-		"AMON_BMON",
-		NPCX_ADC_CH2,
-		ADC_MAX_VOLT * 1000 / 18,
-		ADC_READ_MAX + 1,
-		0
-	},
+	[ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH2, ADC_MAX_VOLT * 1000 / 18,
+			    ADC_READ_MAX + 1, 0 },
 	/*
 	 * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read
 	 * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and
 	 * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we
 	 * only divide by 2 (enough to avoid precision issues).
 	 */
-	[ADC_PSYS] = {
-		"PSYS",
-		NPCX_ADC_CH3,
-		ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1),
-		2,
-		0
-	},
+	[ADC_PSYS] = { "PSYS", NPCX_ADC_CH3,
+		       ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), 2, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
@@ -190,107 +135,42 @@ const struct pwm_t pwm_channels[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
-/* LN9310 switchcap */
-const struct ln9310_config_t ln9310_config = {
-	.i2c_port = I2C_PORT_POWER,
-	.i2c_addr_flags = LN9310_I2C_ADDR_0_FLAGS,
-};
-
-/* Power Path Controller */
-struct ppc_config_t ppc_chips[] = {
-	{
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	{
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-};
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/* TCPC mux configuration */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-
-/*
- * Port-0/1 USB mux driver.
- *
- * The USB mux is handled by TCPC chip and the HPD update is through a GPIO
- * to AP. But the TCPC chip is also needed to know the HPD status; otherwise,
- * the mux misbehaves.
- */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	},
-	{
-		.usb_port = 1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	}
-};
-
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_USB_A_5V,
-};
-
-/* BC1.2 */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_POWER,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	{
-		.i2c_port = I2C_PORT_EEPROM,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-
 /* Mutexes */
 static struct mutex g_base_mutex;
 static struct mutex g_lid_mutex;
 
+static struct kionix_accel_data g_kx022_data;
 static struct bmi_drv_data_t g_bmi160_data;
+static struct icm_drv_data_t g_icm426xx_data;
 static struct accelgyro_saved_data_t g_bma255_data;
 
-/* Matrix to rotate accelerometer into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0,  0},
-	{ 0,  FLOAT_TO_FP(-1),  0},
-	{ 0,  0, FLOAT_TO_FP(-1)}
+enum base_accelgyro_type {
+	BASE_GYRO_NONE = 0,
+	BASE_GYRO_BMI160 = 1,
+	BASE_GYRO_ICM426XX = 2,
 };
 
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+/* Matrix to rotate accelerometer into standard reference frame */
+const mat33_fp_t base_standard_ref_bmi160 = { { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, FLOAT_TO_FP(-1), 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
+
+const mat33_fp_t base_standard_ref_icm426xx = { { 0, FLOAT_TO_FP(1), 0 },
+						{ FLOAT_TO_FP(1), 0, 0 },
+						{ 0, 0, FLOAT_TO_FP(-1) } };
+
+static const mat33_fp_t lid_standard_ref_bma255 = { { FLOAT_TO_FP(-1), 0, 0 },
+						    { 0, FLOAT_TO_FP(-1), 0 },
+						    { 0, 0, FLOAT_TO_FP(1) } };
+
+static const mat33_fp_t lid_standard_ref_kx022 = { { FLOAT_TO_FP(-1), 0, 0 },
+						   { 0, FLOAT_TO_FP(-1), 0 },
+						   { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
 	 .name = "Lid Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .active_mask = SENSOR_ACTIVE_S0_S3_S5,
 	 .chip = MOTIONSENSE_CHIP_BMA255,
 	 .type = MOTIONSENSE_TYPE_ACCEL,
 	 .location = MOTIONSENSE_LOC_LID,
@@ -299,7 +179,7 @@ struct motion_sensor_t motion_sensors[] = {
 	 .drv_data = &g_bma255_data,
 	 .port = I2C_PORT_SENSOR,
 	 .i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-	 .rot_standard_ref = &lid_standard_ref,
+	 .rot_standard_ref = &lid_standard_ref_bma255,
 	 .default_range = 2, /* g, to support lid angle calculation. */
 	 .min_frequency = BMA255_ACCEL_MIN_FREQ,
 	 .max_frequency = BMA255_ACCEL_MAX_FREQ,
@@ -330,14 +210,19 @@ struct motion_sensor_t motion_sensors[] = {
 	 .drv_data = &g_bmi160_data,
 	 .port = I2C_PORT_SENSOR,
 	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .rot_standard_ref = &base_standard_ref,
+	 .rot_standard_ref = &base_standard_ref_bmi160,
 	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
 	 .min_frequency = BMI_ACCEL_MIN_FREQ,
 	 .max_frequency = BMI_ACCEL_MAX_FREQ,
 	 .config = {
-		 [SENSOR_CONFIG_EC_S0] = {
-			 .odr = 10000 | ROUND_UP_FLAG,
-		 },
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+		/* Sensor on for lid angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
 	 },
 	},
 	[BASE_GYRO] = {
@@ -352,46 +237,124 @@ struct motion_sensor_t motion_sensors[] = {
 	 .port = I2C_PORT_SENSOR,
 	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
 	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &base_standard_ref,
+	 .rot_standard_ref = &base_standard_ref_bmi160,
 	 .min_frequency = BMI_GYRO_MIN_FREQ,
 	 .max_frequency = BMI_GYRO_MAX_FREQ,
 	},
 };
 unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
-#ifndef TEST_BUILD
-/* This callback disables keyboard when convertibles are fully open */
-void lid_angle_peripheral_enable(int enable)
-{
-	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
+struct motion_sensor_t kx022_lid_accel = {
+	.name = "Lid Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3_S5,
+	.chip = MOTIONSENSE_CHIP_KX022,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_LID,
+	.drv = &kionix_accel_drv,
+	.mutex = &g_lid_mutex,
+	.drv_data = &g_kx022_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = KX022_ADDR0_FLAGS,
+	.rot_standard_ref = &lid_standard_ref_kx022,
+	.default_range = 2, /* g, enough for laptop. */
+	.min_frequency = KX022_ACCEL_MIN_FREQ,
+	.max_frequency = KX022_ACCEL_MAX_FREQ,
+	.config = {
+		 /* EC use accel for angle detection */
+		 [SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		 },
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	},
+};
 
-	if (enable) {
-		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
-	} else {
-		/*
-		 * Ensure that the chipset is off before disabling the keyboard.
-		 * When the chipset is on, the EC keeps the keyboard enabled and
-		 * the AP decides whether to ignore input devices or not.
-		 */
-		if (!chipset_in_s0)
-			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
-	}
-}
-#endif
+struct motion_sensor_t icm426xx_base_accel = {
+	.name = "Base Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3_S5,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
+	.rot_standard_ref = &base_standard_ref_icm426xx,
+	.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
+	.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	},
+};
+
+struct motion_sensor_t icm426xx_base_gyro = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3_S5,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &base_standard_ref_icm426xx,
+	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
+	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
+};
 
-static int board_is_clamshell(void)
+static int base_accelgyro_config;
+
+void motion_interrupt(enum gpio_signal signal)
 {
-	/* SKU ID of Limozeen: 4, 5 */
-	return sku_id == 4 || sku_id == 5;
+	switch (base_accelgyro_config) {
+	case BASE_GYRO_ICM426XX:
+		icm426xx_interrupt(signal);
+		break;
+	case BASE_GYRO_BMI160:
+	default:
+		bmi160_interrupt(signal);
+		break;
+	}
 }
 
-enum battery_cell_type board_get_battery_cell_type(void)
+static void board_detect_motionsensor(void)
 {
-	/* SKU ID of Limozeen: 4, 5 -> 3S battery */
-	if (sku_id == 4 || sku_id == 5)
-		return BATTERY_CELL_TYPE_3S;
+	int ret;
+	int val;
+
+	/* Check lid accel chip */
+	ret = i2c_read8(I2C_PORT_SENSOR, BMA2x2_I2C_ADDR1_FLAGS,
+			BMA2x2_CHIP_ID_ADDR, &val);
+	if (ret)
+		motion_sensors[LID_ACCEL] = kx022_lid_accel;
+
+	CPRINTS("Lid Accel: %s", ret ? "KX022" : "BMA255");
+
+	/* Check base accelgyro chip */
+	ret = icm_read8(&icm426xx_base_accel, ICM426XX_REG_WHO_AM_I, &val);
+	if (val == ICM426XX_CHIP_ICM40608) {
+		motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
+		motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
+	}
 
-	return BATTERY_CELL_TYPE_UNKNOWN;
+	base_accelgyro_config = (val == ICM426XX_CHIP_ICM40608) ?
+					BASE_GYRO_ICM426XX :
+					BASE_GYRO_BMI160;
+	CPRINTS("Base Accelgyro: %s",
+		(val == ICM426XX_CHIP_ICM40608) ? "ICM40608" : "BMI160");
 }
 
 static void board_update_sensor_config_from_sku(void)
@@ -399,175 +362,29 @@ static void board_update_sensor_config_from_sku(void)
 	if (board_is_clamshell()) {
 		motion_sensor_count = 0;
 		gmr_tablet_switch_disable();
-		/* The base accel is not stuffed; don't allow line to float */
+		/* The sensors are not stuffed; don't allow lines to float */
 		gpio_set_flags(GPIO_ACCEL_GYRO_INT_L,
 			       GPIO_INPUT | GPIO_PULL_DOWN);
+		gpio_set_flags(GPIO_LID_ACCEL_INT_L,
+			       GPIO_INPUT | GPIO_PULL_DOWN);
 	} else {
+		board_detect_motionsensor();
 		motion_sensor_count = ARRAY_SIZE(motion_sensors);
 		/* Enable interrupt for the base accel sensor */
 		gpio_enable_interrupt(GPIO_ACCEL_GYRO_INT_L);
 	}
 }
-
-/* Read SKU ID from GPIO and initialize variables for board variants */
-static void sku_init(void)
-{
-	uint8_t val = 0;
-
-	if (gpio_get_level(GPIO_SKU_ID0))
-		val |= 0x01;
-	if (gpio_get_level(GPIO_SKU_ID1))
-		val |= 0x02;
-	if (gpio_get_level(GPIO_SKU_ID2))
-		val |= 0x04;
-
-	sku_id = val;
-	CPRINTS("SKU: %u", sku_id);
-
-	board_update_sensor_config_from_sku();
-}
-DECLARE_HOOK(HOOK_INIT, sku_init, HOOK_PRIO_INIT_I2C + 1);
-
-static int board_has_ln9310(void)
-{
-	static int ln9310_present = -1;
-	int status, val;
-
-	/* Cache the status of LN9310 present or not */
-	if (ln9310_present == -1) {
-		status = i2c_read8(ln9310_config.i2c_port,
-				   ln9310_config.i2c_addr_flags,
-				   LN9310_REG_CHIP_ID,
-				   &val);
-
-		/*
-		 * Any error reading LN9310 CHIP_ID over I2C means the chip
-		 * not present. Fallback to use DA9313 switchcap.
-		 */
-		ln9310_present = !status && val == LN9310_CHIP_ID;
-	}
-
-	return ln9310_present;
-}
-
-static void board_switchcap_init(void)
-{
-	if (board_has_ln9310()) {
-		CPRINTS("Use switchcap: LN9310");
-
-		/* Configure and enable interrupt for LN9310 */
-		gpio_set_flags(GPIO_SWITCHCAP_PG_INT_L, GPIO_INT_FALLING);
-		gpio_enable_interrupt(GPIO_SWITCHCAP_PG_INT_L);
-
-		/*
-		 * Configure LN9310 enable, open-drain output. Don't set the
-		 * level here; otherwise, it will override its value and
-		 * shutdown the switchcap when sysjump to RW.
-		 *
-		 * Note that the gpio.inc configures it GPIO_OUT_LOW. When
-		 * sysjump to RW, will output push-pull a short period of
-		 * time. As it outputs LOW, should be fine.
-		 *
-		 * This GPIO changes like:
-		 * (1) EC boots from RO -> high-Z
-		 * (2) GPIO init according to gpio.inc -> push-pull LOW
-		 * (3) This function configures it -> open-drain HIGH
-		 * (4) Power sequence turns on the switchcap -> open-drain LOW
-		 * (5) EC sysjumps to RW
-		 * (6) GPIO init according to gpio.inc -> push-pull LOW
-		 * (7) This function configures it -> open-drain LOW
-		 */
-		gpio_set_flags(GPIO_SWITCHCAP_ON_L,
-			       GPIO_OUTPUT | GPIO_OPEN_DRAIN);
-
-		/* Only configure the switchcap if not sysjump */
-		if (!system_jumped_late()) {
-			/*
-			 * Deassert the enable pin (set it HIGH), so the
-			 * switchcap won't be enabled after the switchcap is
-			 * configured from standby mode to switching mode.
-			 */
-			gpio_set_level(GPIO_SWITCHCAP_ON_L, 1);
-			ln9310_init();
-		}
-	} else {
-		CPRINTS("Use switchcap: DA9313");
-
-		/*
-		 * When the chip in power down mode, it outputs high-Z.
-		 * Set pull-down to avoid floating.
-		 */
-		gpio_set_flags(GPIO_DA9313_GPIO0, GPIO_INPUT | GPIO_PULL_DOWN);
-
-		/*
-		 * Configure DA9313 enable, push-pull output. Don't set the
-		 * level here; otherwise, it will override its value and
-		 * shutdown the switchcap when sysjump to RW.
-		 */
-		gpio_set_flags(GPIO_SWITCHCAP_ON, GPIO_OUTPUT);
-	}
-}
+DECLARE_HOOK(HOOK_INIT, board_update_sensor_config_from_sku,
+	     HOOK_PRIO_INIT_I2C + 2);
 
 /* Initialize board. */
 static void board_init(void)
 {
-	/* Enable BC1.2 interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_L);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L);
-
-	/*
-	 * The H1 SBU line for CCD are behind PPC chip. The PPC internal FETs
-	 * for SBU may be disconnected after DP alt mode is off. Should enable
-	 * the CCD_MODE_ODL interrupt to make sure the SBU FETs are connected.
-	 */
-	gpio_enable_interrupt(GPIO_CCD_MODE_ODL);
-
 	/* Set the backlight duty cycle to 0. AP will override it later. */
 	pwm_set_duty(PWM_CH_DISPLIGHT, 0);
-
-	board_switchcap_init();
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
-__override uint16_t board_get_ps8xxx_product_id(int port)
-{
-	/*
-	 * Lazor (SKU_ID: 0, 1, 2, 3) rev 3+ changes TCPC from PS8751 to
-	 * PS8805.
-	 *
-	 * Limozeen (SKU_ID: 4, 5) all-rev uses PS8805.
-	 */
-	if ((sku_id == 0 || sku_id == 1 || sku_id == 2 || sku_id == 3) &&
-	    system_get_board_version() < 3)
-		return PS8751_PRODUCT_ID;
-
-	return PS8805_PRODUCT_ID;
-}
-
-void board_tcpc_init(void)
-{
-	/* Only reset TCPC if not sysjump */
-	if (!system_jumped_late()) {
-		/* TODO(crosbug.com/p/61098): How long do we need to wait? */
-		board_reset_pd_mcu();
-	}
-
-	/* Enable PPC interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_SWCTL_INT_ODL);
-
-	/* Enable TCPC interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL);
-
-	/*
-	 * Initialize HPD to low; after sysjump SOC needs to see
-	 * HPD pulse to enable video path
-	 */
-	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		usb_mux_hpd_update(port, 0, 0);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
-
 /* Called on AP S0 -> S3 transition */
 static void board_chipset_suspend(void)
 {
@@ -590,154 +407,23 @@ static void board_chipset_resume(void)
 }
 DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
 
-void board_set_switchcap_power(int enable)
-{
-	if (board_has_ln9310())
-		gpio_set_level(GPIO_SWITCHCAP_ON_L, !enable);
-	else
-		gpio_set_level(GPIO_SWITCHCAP_ON, enable);
-}
-
-int board_is_switchcap_enabled(void)
-{
-	if (board_has_ln9310())
-		return !gpio_get_level(GPIO_SWITCHCAP_ON_L);
-	else
-		return gpio_get_level(GPIO_SWITCHCAP_ON);
-}
-
-int board_is_switchcap_power_good(void)
-{
-	if (board_has_ln9310())
-		return ln9310_power_good();
-	else
-		return gpio_get_level(GPIO_DA9313_GPIO0);
-}
-
-void board_reset_pd_mcu(void)
-{
-	cprints(CC_USB, "Resetting TCPCs...");
-	cflush();
-
-	gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
-	gpio_set_level(GPIO_USB_C1_PD_RST_L, 0);
-	msleep(PS8XXX_RESET_DELAY_MS);
-	gpio_set_level(GPIO_USB_C0_PD_RST_L, 1);
-	gpio_set_level(GPIO_USB_C1_PD_RST_L, 1);
-}
-
-void board_set_tcpc_power_mode(int port, int mode)
-{
-	/* Ignore the "mode" to turn the chip on.  We can only do a reset. */
-	if (mode)
-		return;
-
-	board_reset_pd_mcu();
-}
-
-int board_vbus_sink_enable(int port, int enable)
-{
-	/* Both ports are controlled by PPC SN5S330 */
-	return ppc_vbus_sink_enable(port, enable);
-}
-
-int board_is_sourcing_vbus(int port)
+__override uint32_t board_get_sku_id(void)
 {
-	/* Both ports are controlled by PPC SN5S330 */
-	return ppc_is_sourcing_vbus(port);
-}
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* TODO(b/120231371): Notify AP */
-	CPRINTS("p%d: overcurrent!", port);
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	int i;
-
-	if (!is_real_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	if (port == CHARGE_PORT_NONE) {
-		CPRINTS("Disabling all charging port");
-
-		/* Disable all ports. */
-		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-			/*
-			 * Do not return early if one fails otherwise we can
-			 * get into a boot loop assertion failure.
-			 */
-			if (board_vbus_sink_enable(i, 0))
-				CPRINTS("Disabling p%d sink path failed.", i);
-		}
-
-		return EC_SUCCESS;
-	}
+	static int sku_id = -1;
 
-	/* Check if the port is sourcing VBUS. */
-	if (board_is_sourcing_vbus(port)) {
-		CPRINTS("Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-
-	CPRINTS("New charge port: p%d", port);
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		if (i == port)
-			continue;
+	if (sku_id == -1) {
+		int bits[3];
 
-		if (board_vbus_sink_enable(i, 0))
-			CPRINTS("p%d: sink path disable failed.", i);
+		bits[0] = gpio_get_ternary(GPIO_SKU_ID0);
+		bits[1] = gpio_get_ternary(GPIO_SKU_ID1);
+		bits[2] = gpio_get_ternary(GPIO_SKU_ID2);
+		sku_id = binary_first_base3_from_bits(bits, ARRAY_SIZE(bits));
 	}
 
-	/* Enable requested charge port. */
-	if (board_vbus_sink_enable(port, 1)) {
-		CPRINTS("p%d: sink path enable failed.", port);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	/*
-	 * Ignore lower charge ceiling on PD transition if our battery is
-	 * critical, as we may brownout.
-	 */
-	if (supplier == CHARGE_SUPPLIER_PD &&
-	    charge_ma < 1500 &&
-	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
-		CPRINTS("Using max ilim %d", max_ma);
-		charge_ma = max_ma;
-	}
-
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
+	return (uint32_t)sku_id;
 }
 
-uint16_t tcpc_get_alert_status(void)
+__override int mkbp_support_volume_buttons(void)
 {
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
-		if (gpio_get_level(GPIO_USB_C0_PD_RST_L))
-			status |= PD_STATUS_TCPC_ALERT_0;
-	if (!gpio_get_level(GPIO_USB_C1_PD_INT_ODL))
-		if (gpio_get_level(GPIO_USB_C1_PD_RST_L))
-			status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
+	return board_has_side_volume_buttons();
 }
-
diff --git a/board/lazor/board.h b/board/lazor/board.h
index 162e03b08e..427db5e82e 100644
--- a/board/lazor/board.h
+++ b/board/lazor/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,27 +10,23 @@
 
 #include "baseboard.h"
 
-/* TODO(waihong): Remove the following bringup features */
-#define CONFIG_BRINGUP
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands. */
-#define CONFIG_USB_PD_DEBUG_LEVEL 3
-#define CONFIG_CMD_AP_RESET_LOG
-#define CONFIG_CMD_GPIO_EXTENDED
-#define CONFIG_CMD_POWERINDEBUG
-#define CONFIG_I2C_DEBUG
-
 /* Internal SPI flash on NPCX7 */
-#define CONFIG_FLASH_SIZE (512 * 1024)  /* 512KB internal spi flash */
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */
+
+/* Reduce flash usage */
+#define CONFIG_LTO
+#define CONFIG_USB_PD_DEBUG_LEVEL 2
 
 /* Switchcap */
 #define CONFIG_LN9310
 
 /* Keyboard */
-#define CONFIG_KEYBOARD_BOARD_CONFIG
+#define CONFIG_KEYBOARD_PROTOCOL_MKBP
+
 #define CONFIG_PWM_KBLIGHT
 
 /* Battery */
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY  "LION"
+#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
 #define CONFIG_BATTERY_REVIVE_DISCONNECT
 #define CONFIG_BATTERY_FUEL_GAUGE
 
@@ -41,6 +37,7 @@
 #define CONFIG_USB_PD_TCPM_MULTI_PS8XXX
 #define CONFIG_USB_PD_TCPM_PS8751
 #define CONFIG_USB_PD_TCPM_PS8805
+#define CONFIG_USB_PD_TCPM_PS8805_FORCE_DID
 #define CONFIG_USBC_PPC_SN5S330
 #define CONFIG_USB_PD_PORT_MAX_COUNT 2
 
@@ -53,11 +50,18 @@
 
 /* BMI160 Base accel/gyro */
 #define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCEL_INTERRUPTS
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 #define OPT3001_I2C_ADDR_FLAGS OPT3001_I2C_ADDR1_FLAGS
 
+/* ICM426XX Base accel/gyro */
+#define CONFIG_ACCELGYRO_ICM426XX
+#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+/* KX022 lid accel */
+#define CONFIG_ACCEL_KX022
+
 /* BMA253 lid accel */
 #define CONFIG_ACCEL_BMA255
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
@@ -70,7 +74,6 @@
 #define CONFIG_TABLET_MODE
 #define CONFIG_TABLET_MODE_SWITCH
 #define CONFIG_GMR_TABLET_MODE
-#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L
 
 /* GPIO alias */
 #define GPIO_AC_PRESENT GPIO_ACOK_OD
@@ -79,17 +82,17 @@
 #define GPIO_SWITCHCAP_PG_INT_L GPIO_DA9313_GPIO0
 #define GPIO_SWITCHCAP_ON_L GPIO_SWITCHCAP_ON
 
+/* Disable console commands to help save space */
+#undef CONFIG_CMD_BATTFAKE
+#undef CONFIG_CMD_CHARGE_SUPPLIER_INFO
+
 #ifndef __ASSEMBLER__
 
 #include "gpio_signal.h"
 #include "registers.h"
+#include "sku.h"
 
-enum adc_channel {
-	ADC_VBUS,
-	ADC_AMON_BMON,
-	ADC_PSYS,
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_VBUS, ADC_AMON_BMON, ADC_PSYS, ADC_CH_COUNT };
 
 /* Motion sensors */
 enum sensor_id {
@@ -99,11 +102,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_DISPLIGHT,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_DISPLIGHT, PWM_CH_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
@@ -115,18 +114,14 @@ enum battery_type {
 	BATTERY_TYPE_COUNT,
 };
 
-/* Swithcap functions */
-void board_set_switchcap_power(int enable);
-int board_is_switchcap_enabled(void);
-int board_is_switchcap_power_good(void);
-enum battery_cell_type board_get_battery_cell_type(void);
-/* Custom function to indicate if sourcing VBUS */
-int board_is_sourcing_vbus(int port);
-/* Enable VBUS sink for a given port */
-int board_vbus_sink_enable(int port, int enable);
+/* support factory keyboard test */
+#define CONFIG_KEYBOARD_FACTORY_TEST
+
 /* Reset all TCPCs. */
 void board_reset_pd_mcu(void);
 void board_set_tcpc_power_mode(int port, int mode);
+/* Motion sensor interrupt */
+void motion_interrupt(enum gpio_signal signal);
 
 #endif /* !defined(__ASSEMBLER__) */
 
diff --git a/board/lazor/build.mk b/board/lazor/build.mk
index a044fa58cb..c17ab5e40c 100644
--- a/board/lazor/build.mk
+++ b/board/lazor/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -11,4 +11,10 @@ CHIP_FAMILY:=npcx7
 CHIP_VARIANT:=npcx7m6fc
 BASEBOARD:=trogdor
 
-board-y=battery.o board.o led.o
+board-y+=battery.o
+board-y+=board.o
+board-y+=hibernate.o
+board-y+=led.o
+board-y+=sku.o
+board-y+=switchcap.o
+board-y+=usbc_config.o
diff --git a/board/lazor/ec.tasklist b/board/lazor/ec.tasklist
index 2b55c26c20..92d5a1dde1 100644
--- a/board/lazor/ec.tasklist
+++ b/board/lazor/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/lazor/gpio.inc b/board/lazor/gpio.inc
index 744cfd96fa..c7af05eb3b 100644
--- a/board/lazor/gpio.inc
+++ b/board/lazor/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,26 +8,26 @@
 /* Declare symbolic names for all the GPIOs that we care about.
  * Note: Those with interrupt handlers must be declared first. */
 
-/* USB-C interrupts */
+/* USB interrupts */
 GPIO_INT(USB_C0_PD_INT_ODL,    PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-0 TCPC */
 GPIO_INT(USB_C1_PD_INT_ODL,    PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-1 TCPC */
 GPIO_INT(USB_C0_SWCTL_INT_ODL, PIN(0, 3), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-0 PPC */
 GPIO_INT(USB_C1_SWCTL_INT_ODL, PIN(4, 0), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-1 PPC */
-GPIO_INT(USB_C0_BC12_INT_L,    PIN(6, 1), GPIO_INT_FALLING, usb0_evt)  /* Interrupt from port-0 BC1.2 */
-GPIO_INT(USB_C1_BC12_INT_L,    PIN(8, 2), GPIO_INT_FALLING, usb1_evt)  /* Interrupt from port-1 BC1.2 */
+GPIO_INT(USB_C0_BC12_INT_L,    PIN(6, 1), GPIO_INT_FALLING | GPIO_PULL_UP, usb0_evt)  /* Interrupt from port-0 BC1.2 */
+GPIO_INT(USB_C1_BC12_INT_L,    PIN(8, 2), GPIO_INT_FALLING | GPIO_PULL_UP, usb1_evt)  /* Interrupt from port-1 BC1.2 */
+GPIO_INT(USB_A0_OC_ODL,        PIN(D, 1), GPIO_INT_BOTH | GPIO_PULL_UP, usba_oc_interrupt)
 
 /* System interrupts */
-GPIO_INT(ACOK_OD,           PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)  /* AC OK? */
+GPIO_INT(ACOK_OD,           PIN(0, 0), GPIO_INT_BOTH, extpower_interrupt)  /* ACOK */
 GPIO_INT(CCD_MODE_ODL,      PIN(E, 3), GPIO_INT_FALLING, board_connect_c0_sbu)  /* Case Closed Debug Mode */
 GPIO_INT(EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)  /* Power button */
 GPIO_INT(EC_VOLDN_BTN_ODL,  PIN(7, 0), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Up button */
 GPIO_INT(EC_VOLUP_BTN_ODL,  PIN(F, 2), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Down button */
 GPIO_INT(EC_WP_ODL,         PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)  /* Write protection */
-GPIO_INT(LID_OPEN_EC,       PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)  /* Lid open? */
+GPIO_INT(LID_OPEN_EC,       PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)  /* Lid open */
 GPIO_INT(AP_RST_L,          PIN(C, 1), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_ap_rst_interrupt)  /* PMIC to signal AP reset */
-GPIO_INT(PS_HOLD,           PIN(A, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V, power_signal_interrupt)  /* Indicate when AP triggers reset/shutdown */
-GPIO_INT(PMIC_FAULT_L,      PIN(A, 3), GPIO_INT_BOTH | GPIO_SEL_1P8V, power_signal_interrupt)  /* Any PMIC fault? */
-GPIO_INT(AP_SUSPEND,        PIN(5, 7), GPIO_INT_BOTH | GPIO_SEL_1P8V, power_signal_interrupt)  /* Suspend signal from PMIC */
+GPIO_INT(PS_HOLD,           PIN(A, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, power_signal_interrupt)  /* Indicate when AP triggers reset/shutdown */
+GPIO_INT(AP_SUSPEND,        PIN(5, 7), GPIO_INT_BOTH, power_signal_interrupt)  /* Suspend signal from PMIC */
 GPIO_INT(DEPRECATED_AP_RST_REQ, PIN(C, 2), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V, power_signal_interrupt) /* Deprecated AP initiated reset indicator */
 /*
  * When switch-cap is off, the POWER_GOOD signal is floating. Need a pull-down
@@ -41,36 +41,31 @@ GPIO_INT(AP_EC_SPI_CS_L,    PIN(5, 3), GPIO_INT_FALLING | GPIO_PULL_DOWN, shi_cs
 
 /* Sensor interrupts */
 GPIO_INT(TABLET_MODE_L,     PIN(C, 6), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-GPIO_INT(ACCEL_GYRO_INT_L,  PIN(A, 0), GPIO_INT_FALLING | GPIO_SEL_1P8V, bmi160_interrupt)  /* Accelerometer/gyro interrupt */
+GPIO_INT(ACCEL_GYRO_INT_L,  PIN(A, 0), GPIO_INT_FALLING, motion_interrupt)  /* Accelerometer/gyro interrupt */
 
 /* Switchcap
  *
  * For DA9313 SKUs, it is GPIO0 of DA9313. The GPIO0 is configured as PVC_PG.
  * For LN9310 SKUs, it is the interrupt line of LN9310.
  */
-GPIO_INT(DA9313_GPIO0,      PIN(E, 2), GPIO_INT_FALLING, switchcap_interrupt)
+GPIO_INT(DA9313_GPIO0,      PIN(E, 2), GPIO_INT_FALLING, ln9310_interrupt)
 
 /*
- * EC_RST_ODL acts as a wake source from PSL hibernate mode. However, it does
- * not need to be an interrupt for normal EC operations. Thus, configure it as
- * GPIO_INT_BOTH with wake on low-to-high edge using GPIO_HIB_WAKE_HIGH so that
- * PSL common code can configure PSL_IN correctly.
- *
- * Use the rising edge to wake EC up. If we chose the falling edge, it would
- * still wake EC up, but EC is in an intermediate state until the signal goes
- * back to high.
+ * EC_RST_ODL used to be a wake source from PSL mode. However, we disabled
+ * the PSL mode. This GPIO does nothing now. Simply set it an INPUT.
  */
-GPIO(EC_RST_ODL,            PIN(0, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH)  /* Wake source: EC reset */
+GPIO(EC_RST_ODL,            PIN(0, 2), GPIO_INPUT)     /* EC reset */
 GPIO(EC_ENTERING_RW,        PIN(E, 1), GPIO_OUT_LOW)   /* Indicate when EC is entering RW code */
 GPIO(EC_BATT_PRES_ODL,      PIN(E, 5), GPIO_INPUT)     /* Battery Present */
 
 /* PMIC/AP 1.8V */
-GPIO(PM845_RESIN_L,         PIN(3, 2), GPIO_ODR_HIGH | GPIO_SEL_1P8V)  /* PMIC reset trigger */
-GPIO(PMIC_KPD_PWR_ODL,      PIN(D, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V)  /* PMIC power button */
+GPIO(PM845_RESIN_L,         PIN(3, 2), GPIO_ODR_HIGH)  /* PMIC reset trigger */
+GPIO(PMIC_KPD_PWR_ODL,      PIN(D, 6), GPIO_ODR_HIGH)  /* PMIC power button */
 GPIO(EC_INT_L,              PIN(A, 2), GPIO_ODR_HIGH)  /* Interrupt line between AP and EC */
 GPIO(QSIP_ON,               PIN(5, 0), GPIO_OUT_LOW)   /* Not used, for non-switchcap testing */
 
 /* Power enables */
+GPIO(HIBERNATE_L,           PIN(5, 2), GPIO_ODR_HIGH)  /* EC hibernate */
 GPIO(SWITCHCAP_ON,          PIN(D, 5), GPIO_OUT_LOW)   /* Enable switch cap; will be configured in the board init */
 /* TODO(waihong): Remove it. The VBOB switch is for backup. */
 GPIO(VBOB_EN,               PIN(D, 3), GPIO_OUT_LOW)   /* Enable VBOB */
@@ -87,23 +82,27 @@ GPIO(TRACKPAD_INT_GATE,     PIN(7, 4), GPIO_OUT_LOW)
 /* USB-C */
 GPIO(USB_C0_PD_RST_L,       PIN(F, 1), GPIO_ODR_HIGH)  /* Port-0 TCPC chip reset, actaully Open-Drain */
 GPIO(USB_C1_PD_RST_L,       PIN(E, 4), GPIO_ODR_HIGH)  /* Port-1 TCPC chip reset, actually Open-Drain */
-GPIO(DP_MUX_OE_L,           PIN(9, 6), GPIO_OUT_HIGH)  /* DP mux enable */
-GPIO(DP_MUX_SEL,            PIN(4, 5), GPIO_OUT_HIGH)  /* DP mux selection: L:C0, H:C1 */
+GPIO(DP_MUX_OE_L,           PIN(9, 6), GPIO_ODR_HIGH)  /* DP mux enable, actually Open-Drain */
+GPIO(DP_MUX_SEL,            PIN(4, 5), GPIO_OUT_LOW)   /* DP mux selection: L:C0, H:C1 */
 GPIO(DP_HOT_PLUG_DET,       PIN(9, 5), GPIO_OUT_LOW)   /* DP HPD to AP */
-/* TODO(waihong): Remove it from schematic. No use. */
-GPIO(USBC_MUX_CONF0,        PIN(5, 1), GPIO_INPUT)
-GPIO(USB_C0_VBUS_DET_L,     PIN(6, 2), GPIO_INPUT)     /* Deprecated BC1.2 VBUS detection on port-0 */
-GPIO(USB_C1_VBUS_DET_L,     PIN(8, 3), GPIO_INPUT)     /* Deprecated BC1.2 VBUS detection on port-1 */
 
 /* USB-A */
 GPIO(EN_USB_A_5V,           PIN(8, 6), GPIO_OUT_LOW)
 GPIO(USB_A_CDP_ILIM_EN,     PIN(7, 5), GPIO_OUT_HIGH)  /* H: CDP, L:SDP. Only one USB-A port, always CDP */
-GPIO(USB_A0_OC_ODL,         PIN(D, 1), GPIO_ODR_HIGH)
 
 /* LEDs */
 GPIO(EC_CHG_LED_Y_C1,       PIN(C, 3), GPIO_OUT_LOW)
 GPIO(EC_CHG_LED_B_C1,       PIN(C, 4), GPIO_OUT_LOW)
 
+/*
+ * SPI host interface - enable PDs by default. These will be made functional
+ * by the SHI driver when the AP powers up, and restored back to GPIO when
+ * the AP powers down.
+ */
+GPIO(AP_EC_SPI_MOSI,        PIN(4, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(AP_EC_SPI_MISO,        PIN(4, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(AP_EC_SPI_CLK,         PIN(5, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+
 /* PWM */
 GPIO(KB_BL_PWM,             PIN(8, 0), GPIO_INPUT)     /* PWM3 */
 GPIO(EDP_BKLTCTL,           PIN(B, 7), GPIO_INPUT)     /* PWM5 */
@@ -133,6 +132,35 @@ GPIO(SKU_ID0,               PIN(F, 0), GPIO_INPUT)
 GPIO(SKU_ID1,               PIN(4, 1), GPIO_INPUT)
 GPIO(SKU_ID2,               PIN(D, 4), GPIO_INPUT)
 
+/* Special straps */
+GPIO(ARM_X86,               PIN(6, 6), GPIO_OUT_LOW)  /* NC, low for power saving */
+
+/* Unused GPIOs, NC. */
+UNUSED(PIN(5, 1))
+UNUSED(PIN(D, 0))
+UNUSED(PIN(F, 3))
+UNUSED(PIN(0, 4))
+UNUSED(PIN(C, 0))
+UNUSED(PIN(A, 7))
+UNUSED(PIN(8, 3))
+UNUSED(PIN(8, 1))
+UNUSED(PIN(3, 7))
+UNUSED(PIN(7, 6))
+UNUSED(PIN(3, 4))
+UNUSED(PIN(C, 5))
+UNUSED(PIN(A, 3))
+UNUSED(PIN(7, 3))
+UNUSED(PIN(D, 7))
+UNUSED(PIN(A, 5))
+UNUSED(PIN(B, 0))
+UNUSED(PIN(9, 4))
+UNUSED(PIN(B, 1))
+UNUSED(PIN(6, 2))
+UNUSED(PIN(3, 5))
+UNUSED(PIN(9, 7))
+UNUSED(PIN(6, 0))
+UNUSED(PIN(7, 2))
+
 /* Alternate functions GPIO definitions */
 ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)            /* UART (GPIO64/65) */
 ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0)             /* I2C0 (GPIOB4/B5) */
@@ -145,10 +173,6 @@ ALTERNATE(PIN_MASK(4, 0xC0), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SDO (GPIO47),
 ALTERNATE(PIN_MASK(5, 0x28), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SCLK (GPIO55), SHI_CS# (GPIO53) */
 ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)             /* PWM3 (GPIO80) - KB_BL_PWM */
 ALTERNATE(PIN_MASK(B, 0x80), 1, MODULE_PWM, 0)             /* PWM5 (GPIOB7) - EDP_BKLTCTL */
-ALTERNATE(PIN_MASK(D, 0x04), 1, MODULE_PMU, 0)             /* PSL_IN1 (GPIOD2) - LID_OPEN_EC */
-ALTERNATE(PIN_MASK(0, 0x01), 1, MODULE_PMU, 0)             /* PSL_IN2 (GPIO00) - ACOK_OD */
-ALTERNATE(PIN_MASK(0, 0x02), 1, MODULE_PMU, 0)             /* PSL_IN3 (GPIO01) - EC_PWR_BTN_ODL */
-ALTERNATE(PIN_MASK(0, 0x04), 1, MODULE_PMU, 0)             /* PSL_IN4 (GPIO02) - EC_RST_ODL */
 
 /* Keyboard */
 #define GPIO_KB_INPUT           (GPIO_INPUT | GPIO_PULL_UP)
diff --git a/board/lazor/hibernate.c b/board/lazor/hibernate.c
new file mode 100644
index 0000000000..67d9b30791
--- /dev/null
+++ b/board/lazor/hibernate.c
@@ -0,0 +1,41 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "gpio.h"
+#include "sku.h"
+#include "system.h"
+#include "usbc_ppc.h"
+
+void board_hibernate(void)
+{
+	int i;
+
+	if (!board_is_clamshell()) {
+		/*
+		 * Sensors are unpowered in hibernate. Apply PD to the
+		 * interrupt lines such that they don't float.
+		 */
+		gpio_set_flags(GPIO_ACCEL_GYRO_INT_L,
+			       GPIO_INPUT | GPIO_PULL_DOWN);
+		gpio_set_flags(GPIO_LID_ACCEL_INT_L,
+			       GPIO_INPUT | GPIO_PULL_DOWN);
+	}
+
+	/*
+	 * Board rev 5+ has the hardware fix. Don't need the following
+	 * workaround.
+	 */
+	if (system_get_board_version() >= 5)
+		return;
+
+	/*
+	 * Enable the PPC power sink path before EC enters hibernate;
+	 * otherwise, ACOK won't go High and can't wake EC up. Check the
+	 * bug b/170324206 for details.
+	 */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
+		ppc_vbus_sink_enable(i, 1);
+}
diff --git a/board/lazor/led.c b/board/lazor/led.c
index f9c91c1c6a..bb41dfb8f7 100644
--- a/board/lazor/led.c
+++ b/board/lazor/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -32,15 +32,15 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_BLUE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static void led_set_color(enum led_color color)
 {
 	gpio_set_level(GPIO_EC_CHG_LED_Y_C1,
-		(color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
+		       (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
 	gpio_set_level(GPIO_EC_CHG_LED_B_C1,
-		(color == LED_BLUE) ? BAT_LED_ON : BAT_LED_OFF);
+		       (color == LED_BLUE) ? BAT_LED_ON : BAT_LED_OFF);
 }
 
 void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
@@ -66,16 +66,15 @@ static void board_led_set_battery(void)
 	static int battery_ticks;
 	int color = LED_OFF;
 	int period = 0;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
 		/* Always indicate amber on when charging. */
 		color = LED_AMBER;
 		break;
-	case PWR_STATE_DISCHARGE:
+	case LED_PWRS_DISCHARGE:
 		if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
 			/* Discharging in S3: Amber 1 sec, off 3 sec */
 			period = (1 + 3) * LED_ONE_SEC;
@@ -92,7 +91,7 @@ static void board_led_set_battery(void)
 			color = LED_BLUE;
 		}
 		break;
-	case PWR_STATE_ERROR:
+	case LED_PWRS_ERROR:
 		/* Battery error: Amber 1 sec, off 1 sec */
 		period = (1 + 1) * LED_ONE_SEC;
 		battery_ticks = battery_ticks % period;
@@ -101,21 +100,21 @@ static void board_led_set_battery(void)
 		else
 			color = LED_OFF;
 		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
+	case LED_PWRS_CHARGE_NEAR_FULL:
 		/* Full Charged: Blue on */
 		color = LED_BLUE;
 		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE) {
-			/* Factory mode: Blue 2 sec, Amber 2 sec */
-			period = (2 + 2) * LED_ONE_SEC;
-			battery_ticks = battery_ticks % period;
-			if (battery_ticks < 2 * LED_ONE_SEC)
-				color = LED_BLUE;
-			else
-				color = LED_AMBER;
-		} else
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		color = LED_BLUE;
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		/* Factory mode: Blue 2 sec, Amber 2 sec */
+		period = (2 + 2) * LED_ONE_SEC;
+		battery_ticks = battery_ticks % period;
+		if (battery_ticks < 2 * LED_ONE_SEC)
 			color = LED_BLUE;
+		else
+			color = LED_AMBER;
 		break;
 	default:
 		/* Other states don't alter LED behavior */
diff --git a/board/lazor/sku.c b/board/lazor/sku.c
new file mode 100644
index 0000000000..0b622046a7
--- /dev/null
+++ b/board/lazor/sku.c
@@ -0,0 +1,98 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "config.h"
+#include "console.h"
+#include "driver/ln9310.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "sku.h"
+#include "system.h"
+#include "tcpm/ps8xxx_public.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+static uint8_t sku_id;
+
+enum board_model {
+	LAZOR,
+	LIMOZEEN,
+	UNKNOWN,
+};
+
+static const char *const model_name[] = {
+	"LAZOR",
+	"LIMOZEEN",
+	"UNKNOWN",
+};
+
+static enum board_model get_model(void)
+{
+	if (sku_id == 0 || sku_id == 1 || sku_id == 2 || sku_id == 3)
+		return LAZOR;
+	if (sku_id == 4 || sku_id == 5 || sku_id == 6)
+		return LIMOZEEN;
+	return UNKNOWN;
+}
+
+/* Read SKU ID from GPIO and initialize variables for board variants */
+static void sku_init(void)
+{
+	sku_id = system_get_sku_id();
+	CPRINTS("SKU: %u (%s)", sku_id, model_name[get_model()]);
+}
+DECLARE_HOOK(HOOK_INIT, sku_init, HOOK_PRIO_INIT_I2C + 1);
+
+enum battery_cell_type board_get_battery_cell_type(void)
+{
+	switch (get_model()) {
+	case LIMOZEEN:
+		return BATTERY_CELL_TYPE_3S;
+	default:
+		return BATTERY_CELL_TYPE_UNKNOWN;
+	}
+}
+
+int board_is_clamshell(void)
+{
+	return get_model() == LIMOZEEN;
+}
+
+__override uint16_t board_get_ps8xxx_product_id(int port)
+{
+	/*
+	 * Lazor (SKU_ID: 0, 1, 2, 3) rev 3+ changes TCPC from PS8751 to
+	 * PS8805.
+	 *
+	 * Limozeen (SKU_ID: 4, 5, 6) all-rev uses PS8805.
+	 */
+	if (get_model() == LAZOR && system_get_board_version() < 3)
+		return PS8751_PRODUCT_ID;
+
+	return PS8805_PRODUCT_ID;
+}
+
+int board_has_da9313(void)
+{
+	return get_model() == LAZOR;
+}
+
+int board_has_buck_ic(void)
+{
+	return get_model() == LIMOZEEN && system_get_board_version() >= 8;
+}
+
+int board_has_ln9310(void)
+{
+	return get_model() == LIMOZEEN && system_get_board_version() < 8;
+}
+
+int board_has_side_volume_buttons(void)
+{
+	return get_model() == LAZOR;
+}
diff --git a/board/lazor/sku.h b/board/lazor/sku.h
new file mode 100644
index 0000000000..3ba687939d
--- /dev/null
+++ b/board/lazor/sku.h
@@ -0,0 +1,18 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Lazor board-specific SKU configuration */
+
+#ifndef __CROS_EC_SKU_H
+#define __CROS_EC_SKU_H
+
+int board_get_version(void);
+int board_is_clamshell(void);
+int board_has_da9313(void);
+int board_has_ln9310(void);
+int board_has_buck_ic(void);
+int board_has_side_volume_buttons(void);
+
+#endif /* __CROS_EC_SKU_H */
diff --git a/board/lazor/switchcap.c b/board/lazor/switchcap.c
new file mode 100644
index 0000000000..fc9dce3ada
--- /dev/null
+++ b/board/lazor/switchcap.c
@@ -0,0 +1,121 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "config.h"
+#include "console.h"
+#include "driver/ln9310.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "power/qcom.h"
+#include "sku.h"
+#include "system.h"
+
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args)
+
+/* LN9310 switchcap */
+const struct ln9310_config_t ln9310_config = {
+	.i2c_port = I2C_PORT_POWER,
+	.i2c_addr_flags = LN9310_I2C_ADDR_0_FLAGS,
+};
+
+static void switchcap_init(void)
+{
+	if (board_has_da9313()) {
+		CPRINTS("Use switchcap: DA9313");
+
+		/*
+		 * When the chip in power down mode, it outputs high-Z.
+		 * Set pull-down to avoid floating.
+		 */
+		gpio_set_flags(GPIO_DA9313_GPIO0, GPIO_INPUT | GPIO_PULL_DOWN);
+
+		/*
+		 * Configure DA9313 enable, push-pull output. Don't set the
+		 * level here; otherwise, it will override its value and
+		 * shutdown the switchcap when sysjump to RW.
+		 */
+		gpio_set_flags(GPIO_SWITCHCAP_ON, GPIO_OUTPUT);
+	} else if (board_has_ln9310()) {
+		CPRINTS("Use switchcap: LN9310");
+
+		/* Configure and enable interrupt for LN9310 */
+		gpio_set_flags(GPIO_SWITCHCAP_PG_INT_L, GPIO_INT_FALLING);
+		gpio_enable_interrupt(GPIO_SWITCHCAP_PG_INT_L);
+
+		/*
+		 * Configure LN9310 enable, open-drain output. Don't set the
+		 * level here; otherwise, it will override its value and
+		 * shutdown the switchcap when sysjump to RW.
+		 *
+		 * Note that the gpio.inc configures it GPIO_OUT_LOW. When
+		 * sysjump to RW, will output push-pull a short period of
+		 * time. As it outputs LOW, should be fine.
+		 *
+		 * This GPIO changes like:
+		 * (1) EC boots from RO -> high-Z
+		 * (2) GPIO init according to gpio.inc -> push-pull LOW
+		 * (3) This function configures it -> open-drain HIGH
+		 * (4) Power sequence turns on the switchcap -> open-drain LOW
+		 * (5) EC sysjumps to RW
+		 * (6) GPIO init according to gpio.inc -> push-pull LOW
+		 * (7) This function configures it -> open-drain LOW
+		 */
+		gpio_set_flags(GPIO_SWITCHCAP_ON_L,
+			       GPIO_OUTPUT | GPIO_OPEN_DRAIN);
+
+		/* Only configure the switchcap if not sysjump */
+		if (!system_jumped_late()) {
+			/*
+			 * Deassert the enable pin (set it HIGH), so the
+			 * switchcap won't be enabled after the switchcap is
+			 * configured from standby mode to switching mode.
+			 */
+			gpio_set_level(GPIO_SWITCHCAP_ON_L, 1);
+			ln9310_init();
+		}
+	} else if (board_has_buck_ic()) {
+		CPRINTS("Use Buck IC");
+	} else {
+		CPRINTS("ERROR: No switchcap solution");
+	}
+}
+DECLARE_HOOK(HOOK_INIT, switchcap_init, HOOK_PRIO_DEFAULT);
+
+void board_set_switchcap_power(int enable)
+{
+	if (board_has_da9313()) {
+		gpio_set_level(GPIO_SWITCHCAP_ON, enable);
+	} else if (board_has_ln9310()) {
+		gpio_set_level(GPIO_SWITCHCAP_ON_L, !enable);
+		ln9310_software_enable(enable);
+	} else if (board_has_buck_ic()) {
+		gpio_set_level(GPIO_VBOB_EN, enable);
+	}
+}
+
+int board_is_switchcap_enabled(void)
+{
+	if (board_has_da9313())
+		return gpio_get_level(GPIO_SWITCHCAP_ON);
+	else if (board_has_ln9310())
+		return !gpio_get_level(GPIO_SWITCHCAP_ON_L);
+
+	/* Board has buck ic*/
+	return gpio_get_level(GPIO_VBOB_EN);
+}
+
+int board_is_switchcap_power_good(void)
+{
+	if (board_has_da9313())
+		return gpio_get_level(GPIO_DA9313_GPIO0);
+	else if (board_has_ln9310())
+		return ln9310_power_good();
+
+	/* Board has buck ic no way to check POWER GOOD */
+	return 1;
+}
diff --git a/board/lazor/usbc_config.c b/board/lazor/usbc_config.c
new file mode 100644
index 0000000000..410d0c19d1
--- /dev/null
+++ b/board/lazor/usbc_config.c
@@ -0,0 +1,402 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Lazor board-specific USB-C configuration */
+
+#include "battery_fuel_gauge.h"
+#include "bc12/pi3usb9201_public.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "charger/isl923x_public.h"
+#include "common.h"
+#include "config.h"
+#include "driver/ln9310.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "ppc/sn5s330_public.h"
+#include "system.h"
+#include "tcpm/ps8xxx_public.h"
+#include "tcpm/tcpci.h"
+#include "timer.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usbc_config.h"
+#include "usbc_ocp.h"
+#include "usbc_ppc.h"
+
+/* Disable debug messages to free flash space */
+#define CPRINTS(format, args...)
+#define CPRINTF(format, args...)
+
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+};
+
+int charger_profile_override(struct charge_state_data *curr)
+{
+	int usb_mv;
+	int port;
+
+	if (curr->state != ST_CHARGE)
+		return 0;
+
+	/* Lower the max requested voltage to 5V when battery is full. */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
+	    !(curr->batt.flags & BATT_FLAG_BAD_STATUS) &&
+	    !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
+	    (curr->batt.status & STATUS_FULLY_CHARGED))
+		usb_mv = 5000;
+	else
+		usb_mv = PD_MAX_VOLTAGE_MV;
+
+	if (pd_get_max_voltage() != usb_mv) {
+		CPRINTS("VBUS limited to %dmV", usb_mv);
+		for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++)
+			pd_set_external_voltage_limit(port, usb_mv);
+	}
+
+	return 0;
+}
+
+enum ec_status charger_profile_override_get_param(uint32_t param,
+						  uint32_t *value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+enum ec_status charger_profile_override_set_param(uint32_t param,
+						  uint32_t value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+void usb0_evt(enum gpio_signal signal)
+{
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+
+void usb1_evt(enum gpio_signal signal)
+{
+	usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+}
+
+static void usba_oc_deferred(void)
+{
+	/* Use next number after all USB-C ports to indicate the USB-A port */
+	board_overcurrent_event(CONFIG_USB_PD_PORT_MAX_COUNT,
+				!gpio_get_level(GPIO_USB_A0_OC_ODL));
+}
+DECLARE_DEFERRED(usba_oc_deferred);
+
+void usba_oc_interrupt(enum gpio_signal signal)
+{
+	hook_call_deferred(&usba_oc_deferred_data, 0);
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_SWCTL_INT_ODL:
+		sn5s330_interrupt(0);
+		break;
+	case GPIO_USB_C1_SWCTL_INT_ODL:
+		sn5s330_interrupt(1);
+		break;
+	default:
+		break;
+	}
+}
+
+static void board_connect_c0_sbu_deferred(void)
+{
+	/*
+	 * If CCD_MODE_ODL asserts, it means there's a debug accessory connected
+	 * and we should enable the SBU FETs.
+	 */
+	ppc_set_sbu(0, 1);
+}
+DECLARE_DEFERRED(board_connect_c0_sbu_deferred);
+
+void board_connect_c0_sbu(enum gpio_signal s)
+{
+	hook_call_deferred(&board_connect_c0_sbu_deferred_data, 0);
+}
+
+/* GPIO Interrupt Handlers */
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	int port = -1;
+
+	switch (signal) {
+	case GPIO_USB_C0_PD_INT_ODL:
+		port = 0;
+		break;
+	case GPIO_USB_C1_PD_INT_ODL:
+		port = 1;
+		break;
+	default:
+		return;
+	}
+
+	schedule_deferred_pd_interrupt(port);
+}
+
+/* Power Path Controller */
+struct ppc_config_t ppc_chips[] = {
+	{ .i2c_port = I2C_PORT_TCPC0,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
+	{ .i2c_port = I2C_PORT_TCPC1,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
+};
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/* TCPC mux configuration */
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TCPC0,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+	},
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TCPC1,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+	},
+};
+
+/*
+ * Port-0/1 USB mux driver.
+ *
+ * The USB mux is handled by TCPC chip and the HPD update is through a GPIO
+ * to AP. But the TCPC chip is also needed to know the HPD status; otherwise,
+ * the mux misbehaves.
+ */
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
+	},
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
+	}
+};
+
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_USB_A_5V,
+};
+
+/* BC1.2 */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	{
+		.i2c_port = I2C_PORT_POWER,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+	{
+		.i2c_port = I2C_PORT_EEPROM,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+};
+
+__override int board_get_default_battery_type(void)
+{
+	/*
+	 * A 2S battery is set as default. If the board is configured to use
+	 * a 3S battery, according to its SKU_ID, return a 3S battery as
+	 * default. It helps to configure the charger to output a correct
+	 * voltage in case the battery is not attached.
+	 */
+	if (board_get_battery_cell_type() == BATTERY_CELL_TYPE_3S)
+		return BATTERY_LGC_AP18C8K;
+
+	return DEFAULT_BATTERY_TYPE;
+}
+
+/* Initialize board USC-C things */
+static void board_init_usbc(void)
+{
+	/* Enable BC1.2 interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_L);
+	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L);
+
+	/* Enable USB-A overcurrent interrupt */
+	gpio_enable_interrupt(GPIO_USB_A0_OC_ODL);
+	/*
+	 * The H1 SBU line for CCD are behind PPC chip. The PPC internal FETs
+	 * for SBU may be disconnected after DP alt mode is off. Should enable
+	 * the CCD_MODE_ODL interrupt to make sure the SBU FETs are connected.
+	 */
+	gpio_enable_interrupt(GPIO_CCD_MODE_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_init_usbc, HOOK_PRIO_DEFAULT);
+
+void board_tcpc_init(void)
+{
+	/* Only reset TCPC if not sysjump */
+	if (!system_jumped_late()) {
+		/* TODO(crosbug.com/p/61098): How long do we need to wait? */
+		board_reset_pd_mcu();
+	}
+
+	/* Enable PPC interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_SWCTL_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_SWCTL_INT_ODL);
+
+	/* Enable TCPC interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL);
+
+	/*
+	 * Initialize HPD to low; after sysjump SOC needs to see
+	 * HPD pulse to enable video path
+	 */
+	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
+		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
+
+void board_reset_pd_mcu(void)
+{
+	cprints(CC_USB, "Resetting TCPCs...");
+	cflush();
+
+	gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
+	gpio_set_level(GPIO_USB_C1_PD_RST_L, 0);
+	msleep(PS8XXX_RESET_DELAY_MS);
+	gpio_set_level(GPIO_USB_C0_PD_RST_L, 1);
+	gpio_set_level(GPIO_USB_C1_PD_RST_L, 1);
+}
+
+void board_set_tcpc_power_mode(int port, int mode)
+{
+	/* Ignore the "mode" to turn the chip on.  We can only do a reset. */
+	if (mode)
+		return;
+
+	board_reset_pd_mcu();
+}
+
+int board_vbus_sink_enable(int port, int enable)
+{
+	/* Both ports are controlled by PPC SN5S330 */
+	return ppc_vbus_sink_enable(port, enable);
+}
+
+int board_is_sourcing_vbus(int port)
+{
+	/* Both ports are controlled by PPC SN5S330 */
+	return ppc_is_sourcing_vbus(port);
+}
+
+void board_overcurrent_event(int port, int is_overcurrented)
+{
+	/* TODO(b/120231371): Notify AP */
+	CPRINTS("p%d: overcurrent!", port);
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int i;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTS("Disabling all charging port");
+
+		/* Disable all ports. */
+		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (board_vbus_sink_enable(i, 0))
+				CPRINTS("Disabling p%d sink path failed.", i);
+		}
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (board_is_sourcing_vbus(port)) {
+		CPRINTS("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTS("New charge port: p%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		if (i == port)
+			continue;
+
+		if (board_vbus_sink_enable(i, 0))
+			CPRINTS("p%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (board_vbus_sink_enable(port, 1)) {
+		CPRINTS("p%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
+{
+	/*
+	 * Ignore lower charge ceiling on PD transition if our battery is
+	 * critical, as we may brownout.
+	 */
+	if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 &&
+	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
+		CPRINTS("Using max ilim %d", max_ma);
+		charge_ma = max_ma;
+	}
+
+	charge_set_input_current_limit(charge_ma, charge_mv);
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
+		if (gpio_get_level(GPIO_USB_C0_PD_RST_L))
+			status |= PD_STATUS_TCPC_ALERT_0;
+	if (!gpio_get_level(GPIO_USB_C1_PD_INT_ODL))
+		if (gpio_get_level(GPIO_USB_C1_PD_RST_L))
+			status |= PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
diff --git a/board/lazor/usbc_config.h b/board/lazor/usbc_config.h
new file mode 100644
index 0000000000..53d6df3983
--- /dev/null
+++ b/board/lazor/usbc_config.h
@@ -0,0 +1,20 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* lazor board-specific USB-C configuration */
+
+#ifndef __CROS_EC_USBC_CONFIG_H
+#define __CROS_EC_USBC_CONFIG_H
+
+#include "gpio.h"
+
+void tcpc_alert_event(enum gpio_signal signal);
+void usb0_evt(enum gpio_signal signal);
+void usb1_evt(enum gpio_signal signal);
+void usba_oc_interrupt(enum gpio_signal signal);
+void ppc_interrupt(enum gpio_signal signal);
+void board_connect_c0_sbu(enum gpio_signal s);
+
+#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/lazor/vif_override.xml b/board/lazor/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/lazor/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/liara/battery.c b/board/liara/battery.c
index 25df841018..291925cd06 100644
--- a/board/liara/battery.c
+++ b/board/liara/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -165,27 +165,3 @@ const struct board_batt_params board_battery_info[] = {
 BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
 
 const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_PANASONIC;
-
-/* Lower our input voltage to 5V in S5/G3 when battery is full. */
-static void reduce_input_voltage_when_full(void)
-{
-	int max_pd_voltage_mv;
-	int port;
-
-	if (charge_get_percent() == 100 &&
-	    chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF))
-		max_pd_voltage_mv = 5000;
-	else
-		max_pd_voltage_mv = PD_MAX_VOLTAGE_MV;
-
-	if (pd_get_max_voltage() != max_pd_voltage_mv) {
-		for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++)
-			pd_set_external_voltage_limit(port, max_pd_voltage_mv);
-	}
-}
-DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, reduce_input_voltage_when_full,
-	     HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, reduce_input_voltage_when_full,
-	     HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, reduce_input_voltage_when_full,
-	     HOOK_PRIO_DEFAULT);
diff --git a/board/liara/board.c b/board/liara/board.c
index 4f8b552d1f..e919cdb4e7 100644
--- a/board/liara/board.c
+++ b/board/liara/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,6 +17,7 @@
 #include "pwm_chip.h"
 #include "switch.h"
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 const enum gpio_signal hibernate_wake_pins[] = {
@@ -25,16 +26,40 @@ const enum gpio_signal hibernate_wake_pins[] = {
 	GPIO_POWER_BUTTON_L,
 	GPIO_EC_RST_ODL,
 };
-const int hibernate_wake_pins_used =  ARRAY_SIZE(hibernate_wake_pins);
+const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 
 /* I2C port map. */
 const struct i2c_port_t i2c_ports[] = {
-	{"power",   I2C_PORT_POWER,   100, GPIO_I2C0_SCL, GPIO_I2C0_SDA},
-	{"tcpc0",   I2C_PORT_TCPC0,   400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"tcpc1",   I2C_PORT_TCPC1,   400, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-	{"thermal", I2C_PORT_THERMAL_AP, 400, GPIO_I2C3_SCL, GPIO_I2C3_SDA},
-	{"kblight", I2C_PORT_KBLIGHT, 100, GPIO_I2C5_SCL, GPIO_I2C5_SDA},
-	{"sensor",  I2C_PORT_SENSOR,  400, GPIO_I2C7_SCL, GPIO_I2C7_SDA},
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_I2C0_SCL,
+	  .sda = GPIO_I2C0_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "tcpc1",
+	  .port = I2C_PORT_TCPC1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "thermal",
+	  .port = I2C_PORT_THERMAL_AP,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
+	{ .name = "kblight",
+	  .port = I2C_PORT_KBLIGHT,
+	  .kbps = 100,
+	  .scl = GPIO_I2C5_SCL,
+	  .sda = GPIO_I2C5_SDA },
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_I2C7_SCL,
+	  .sda = GPIO_I2C7_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
diff --git a/board/liara/board.h b/board/liara/board.h
index b869f9f8c1..4ef9a11793 100644
--- a/board/liara/board.h
+++ b/board/liara/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,12 +17,14 @@
  * By default, enable all console messages excepted HC, ACPI and event:
  * The sensor stack is generating a lot of activity.
  */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
 #undef CONFIG_HOSTCMD_DEBUG_MODE
 #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
 
 #define CONFIG_MKBP_USE_HOST_EVENT
 
+#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV 5000
+
 /* Power and battery LEDs */
 #define CONFIG_LED_COMMON
 #define CONFIG_LED_PWM_CHARGE_STATE_ONLY
diff --git a/board/liara/build.mk b/board/liara/build.mk
index c808e65aed..d24127ddae 100644
--- a/board/liara/build.mk
+++ b/board/liara/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/liara/ec.tasklist b/board/liara/ec.tasklist
index b562761311..24300fe7da 100644
--- a/board/liara/ec.tasklist
+++ b/board/liara/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/liara/gpio.inc b/board/liara/gpio.inc
index 343c50f503..a1c3e1a25f 100644
--- a/board/liara/gpio.inc
+++ b/board/liara/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/liara/led.c b/board/liara/led.c
index 8efb6150fc..45cc43edc8 100644
--- a/board/liara/led.c
+++ b/board/liara/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,14 +18,11 @@ const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
  * We only have a blue and an amber LED, so setting any other colour results in
  * both LEDs being off.
  */
-struct pwm_led led_color_map[EC_LED_COLOR_COUNT] = {
-				/* White, Amber */
-	[EC_LED_COLOR_RED]    = {   0,   0 },
-	[EC_LED_COLOR_GREEN]  = {   0,   0 },
-	[EC_LED_COLOR_BLUE]   = {   0,   0 },
-	[EC_LED_COLOR_YELLOW] = {   0,   0 },
-	[EC_LED_COLOR_WHITE]  = { 100,   0 },
-	[EC_LED_COLOR_AMBER]  = {   0, 100 },
+struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = {
+	/* White, Amber */
+	[EC_LED_COLOR_RED] = { 0, 0 },	   [EC_LED_COLOR_GREEN] = { 0, 0 },
+	[EC_LED_COLOR_BLUE] = { 0, 0 },	   [EC_LED_COLOR_YELLOW] = { 0, 0 },
+	[EC_LED_COLOR_WHITE] = { 100, 0 }, [EC_LED_COLOR_AMBER] = { 0, 100 },
 };
 
 /* One logical LED with amber and blue channels. */
diff --git a/board/liara/vif_override.xml b/board/liara/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/liara/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/lick/battery.c b/board/lick/battery.c
index fa746a8c9f..01ab23dd3b 100644
--- a/board/lick/battery.c
+++ b/board/lick/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/lick/board.c b/board/lick/board.c
index 71512249be..2aea264d69 100644
--- a/board/lick/board.c
+++ b/board/lick/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,7 @@
 /* Lick board-specific configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
+#include "battery_smart.h"
 #include "button.h"
 #include "charge_state.h"
 #include "common.h"
@@ -24,19 +24,18 @@
 #include "power.h"
 #include "power_button.h"
 #include "switch.h"
-#include "task.h"
 #include "tablet_mode.h"
-#include "tcpci.h"
+#include "task.h"
+#include "tcpm/tcpci.h"
 #include "temp_sensor.h"
-#include "thermistor.h"
+#include "temp_sensor/thermistor.h"
 #include "util.h"
-#include "battery_smart.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define USB_PD_PORT_ANX7447	0
-#define USB_PD_PORT_PS8751	1
+#define USB_PD_PORT_ANX7447 0
+#define USB_PD_PORT_PS8751 1
 
 static uint8_t sku_id;
 
@@ -61,31 +60,31 @@ static void ppc_interrupt(enum gpio_signal signal)
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_AMB] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_AMB] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				  ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_CHARGER] = { "TEMP_CHARGER", NPCX_ADC_CH1,
+				      ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 },
 	/* Vbus sensing (1/10 voltage divider). */
-	[ADC_VBUS_C0] = {
-		"VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
-	[ADC_VBUS_C1] = {
-		"VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
+	[ADC_VBUS_C0] = { "VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT * 10,
+			  ADC_READ_MAX + 1, 0 },
+	[ADC_VBUS_C1] = { "VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT * 10,
+			  ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp,
-				 .idx = 0},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
+	[TEMP_SENSOR_BATTERY] = { .name = "Battery",
+				  .type = TEMP_SENSOR_TYPE_BATTERY,
+				  .read = charge_get_battery_temp,
+				  .idx = 0 },
+	[TEMP_SENSOR_AMBIENT] = { .name = "Ambient",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_51k1_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_AMB },
+	[TEMP_SENSOR_CHARGER] = { .name = "Charger",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_13k7_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_CHARGER },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -95,11 +94,9 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrix to rotate lid and base sensor into standard reference frame */
-const mat33_fp_t standard_rot_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
+const mat33_fp_t standard_rot_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				      { 0, FLOAT_TO_FP(-1), 0 },
+				      { 0, 0, FLOAT_TO_FP(1) } };
 
 /* sensor private data */
 static struct stprivate_data g_lis2dh_data;
@@ -145,8 +142,6 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_base_mutex,
 		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
 				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
 		.port = I2C_PORT_SENSOR,
 		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
 		.rot_standard_ref = &standard_rot_ref,
@@ -177,8 +172,6 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_base_mutex,
 		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
 				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
 		.port = I2C_PORT_SENSOR,
 		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
 		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
@@ -197,11 +190,10 @@ static int board_is_convertible(void)
 
 static void board_update_sensor_config_from_sku(void)
 {
-		motion_sensor_count = 0;
-		gmr_tablet_switch_disable();
-		/* Base accel is not stuffed, don't allow line to float */
-		gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L,
-			       GPIO_INPUT | GPIO_PULL_DOWN);
+	motion_sensor_count = 0;
+	gmr_tablet_switch_disable();
+	/* Base accel is not stuffed, don't allow line to float */
+	gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
 }
 
 static void cbi_init(void)
@@ -216,9 +208,8 @@ static void cbi_init(void)
 }
 DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1);
 
-#ifndef TEST_BUILD
 /* This callback disables keyboard when convertibles are fully open */
-void lid_angle_peripheral_enable(int enable)
+__override void lid_angle_peripheral_enable(int enable)
 {
 	/*
 	 * If the lid is in tablet position via other sensors,
@@ -231,7 +222,6 @@ void lid_angle_peripheral_enable(int enable)
 	if (board_is_convertible())
 		keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
 }
-#endif
 
 int board_is_lid_angle_tablet_mode(void)
 {
@@ -239,11 +229,11 @@ int board_is_lid_angle_tablet_mode(void)
 }
 
 /* Battery functions */
-#define SB_OPTIONALMFG_FUNCTION2		0x3e
+#define SB_OPTIONALMFG_FUNCTION2 0x3e
 /* Optional mfg function2 */
-#define SMART_QUICK_CHARGE			(1<<12)
+#define SMART_QUICK_CHARGE (1 << 12)
 /* Quick charge support */
-#define MODE_QUICK_CHARGE_SUPPORT		(1<<4)
+#define MODE_QUICK_CHARGE_SUPPORT (1 << 4)
 
 static void sb_quick_charge_mode(int enable)
 {
diff --git a/board/lick/board.h b/board/lick/board.h
index cf3a7c013a..05f24f141d 100644
--- a/board/lick/board.h
+++ b/board/lick/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,12 +13,13 @@
 #define VARIANT_OCTOPUS_CHARGER_ISL9238
 #include "baseboard.h"
 
+#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD
+
 #define CONFIG_VOLUME_BUTTONS
 #define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
 #define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
 
 #define CONFIG_LED_COMMON
-#define CONFIG_LED_POWER_LED
 #define CONFIG_TEMP_SENSOR
 #define CONFIG_THERMISTOR
 #define CONFIG_STEINHART_HART_3V3_13K7_47K_4050B
@@ -29,8 +30,8 @@
 #define CONFIG_CMD_ACCEL_INFO
 
 /* Sensors */
-#define CONFIG_ACCEL_LIS2DE             /* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM        /* Base accel */
+#define CONFIG_ACCEL_LIS2DE /* Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
 /* Sensors without hardware FIFO are in forced mode */
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
 
@@ -49,10 +50,10 @@
 #include "registers.h"
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_AMB,		/* ADC0 */
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC1 */
-	ADC_VBUS_C0,			/* ADC9 */
-	ADC_VBUS_C1,			/* ADC4 */
+	ADC_TEMP_SENSOR_AMB, /* ADC0 */
+	ADC_TEMP_SENSOR_CHARGER, /* ADC1 */
+	ADC_VBUS_C0, /* ADC9 */
+	ADC_VBUS_C1, /* ADC4 */
 	ADC_CH_COUNT,
 };
 
@@ -63,18 +64,10 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_COUNT };
 
 /* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
diff --git a/board/lick/build.mk b/board/lick/build.mk
index 137e208b53..fee77e38b5 100644
--- a/board/lick/build.mk
+++ b/board/lick/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/lick/ec.tasklist b/board/lick/ec.tasklist
index 6eac78a042..6c56976091 100644
--- a/board/lick/ec.tasklist
+++ b/board/lick/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/lick/gpio.inc b/board/lick/gpio.inc
index ad6773a211..3a553f6e91 100644
--- a/board/lick/gpio.inc
+++ b/board/lick/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/lick/led.c b/board/lick/led.c
index 3985c519f3..1d5bd17c0d 100644
--- a/board/lick/led.c
+++ b/board/lick/led.c
@@ -1,53 +1,57 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Power and battery LED control for Lick
  */
 
+#include "chipset.h"
 #include "ec_commands.h"
 #include "gpio.h"
 #include "led_common.h"
 #include "led_onoff_states.h"
-#include "chipset.h"
 
 #define LED_ON_LVL 0
 #define LED_OFF_LVL 1
 
-const int led_charge_lvl_1 = 5;
+__override const int led_charge_lvl_1 = 5;
 
-const int led_charge_lvl_2 = 97;
+__override const int led_charge_lvl_2 = 97;
 
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
 
-const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-					{LED_OFF,	   0.5 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 3 * LED_ONE_SEC },
+					       { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-	EC_LED_ID_BATTERY_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED,
+					     EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-void led_set_color_power(enum ec_led_colors color)
+__override void led_set_color_power(enum ec_led_colors color)
 {
 	if (color == EC_LED_COLOR_WHITE)
 		gpio_set_level(GPIO_PWR_LED_WHITE_L, LED_ON_LVL);
@@ -56,7 +60,7 @@ void led_set_color_power(enum ec_led_colors color)
 		gpio_set_level(GPIO_PWR_LED_WHITE_L, LED_OFF_LVL);
 }
 
-void led_set_color_battery(enum ec_led_colors color)
+__override void led_set_color_battery(enum ec_led_colors color)
 {
 	switch (color) {
 	case EC_LED_COLOR_RED:
@@ -109,4 +113,3 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 
 	return EC_SUCCESS;
 }
-
diff --git a/board/lick/vif_override.xml b/board/lick/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/lick/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/lindar/battery.c b/board/lindar/battery.c
index 7f37c6fe10..e206a5c6aa 100644
--- a/board/lindar/battery.c
+++ b/board/lindar/battery.c
@@ -1,11 +1,13 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Battery pack vendor provided charging profile
  */
 
+#include "battery.h"
 #include "battery_fuel_gauge.h"
+#include "battery_smart.h"
 #include "common.h"
 #include "util.h"
 
@@ -121,3 +123,15 @@ const struct board_batt_params board_battery_info[] = {
 BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
 
 const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SMP;
+
+__override bool board_battery_is_initialized(void)
+{
+	bool batt_initialization_state;
+	int batt_status;
+
+	batt_initialization_state =
+		(battery_status(&batt_status) ?
+			 false :
+			 !!(batt_status & STATUS_INITIALIZED));
+	return batt_initialization_state;
+}
diff --git a/board/lindar/board.c b/board/lindar/board.c
index ce30e301c9..49d90502ba 100644
--- a/board/lindar/board.c
+++ b/board/lindar/board.c
@@ -1,10 +1,9 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-/* Malefor board-specific configuration */
-#include "bb_retimer.h"
+/* lindar board-specific configuration */
 #include "button.h"
 #include "cbi_ec_fw_config.h"
 #include "common.h"
@@ -15,6 +14,7 @@
 #include "driver/ppc/syv682x.h"
 #include "driver/sync.h"
 #include "driver/tcpm/ps8xxx.h"
+#include "driver/tcpm/rt1715.h"
 #include "driver/tcpm/tcpci.h"
 #include "driver/tcpm/tusb422.h"
 #include "extpower.h"
@@ -30,8 +30,8 @@
 #include "pwm_chip.h"
 #include "switch.h"
 #include "system.h"
-#include "task.h"
 #include "tablet_mode.h"
+#include "task.h"
 #include "uart.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
@@ -39,13 +39,14 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#include "gpio_list.h" /* Must come after other header files. */
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ##args)
 
 /* Keyboard scan setting */
-struct keyboard_scan_config keyscan_config = {
+__override struct keyboard_scan_config keyscan_config = {
 	/* Increase from 50 us, because KSO_02 passes through the H1. */
 	.output_settle_us = 80,
 	/* Other values should be the same as the default configuration. */
@@ -76,7 +77,7 @@ static void board_init(void)
 	} else {
 		motion_sensor_count = 0;
 		/* Device is clamshell only */
-		tablet_set_mode(0);
+		tablet_set_mode(0, TABLET_TRIGGER_LID);
 		/* Gyro is not present, don't allow line to float */
 		gpio_set_flags(GPIO_EC_IMU_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
 	}
@@ -91,23 +92,33 @@ static void board_init(void)
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
+int board_is_i2c_port_powered(int port)
+{
+	if (port != I2C_PORT_LIGHTBAR)
+		return 1;
+
+	/*
+	 * Lightbar rails are off in S5/G3
+	 * Refer CL-2739008.
+	 */
+	return chipset_in_state(CHIPSET_STATE_ANY_OFF) ? 0 : 1;
+}
+
 int board_is_lid_angle_tablet_mode(void)
 {
 	return ec_cfg_has_tabletmode();
 }
 
 /* Enable or disable input devices, based on tablet mode or chipset state */
-#ifndef TEST_BUILD
-void lid_angle_peripheral_enable(int enable)
+__override void lid_angle_peripheral_enable(int enable)
 {
 	if (ec_cfg_has_tabletmode()) {
 		if (chipset_in_state(CHIPSET_STATE_ANY_OFF) ||
-			tablet_get_mode())
+		    tablet_get_mode())
 			enable = 0;
 		keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
 	}
 }
-#endif
 
 /******************************************************************************/
 /* Sensors */
@@ -120,17 +131,13 @@ static struct stprivate_data g_lis2dh_data;
 static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
 
 /* Matrix to rotate lid and base sensor into standard reference frame */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					     { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, FLOAT_TO_FP(-1), 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
@@ -170,8 +177,6 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_base_mutex,
 		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
 				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_EC_IMU_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
 		.port = I2C_PORT_SENSOR,
 		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
 		.rot_standard_ref = &base_standard_ref,
@@ -202,8 +207,6 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_base_mutex,
 		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
 				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_EC_IMU_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
 		.port = I2C_PORT_SENSOR,
 		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
 		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
@@ -219,7 +222,7 @@ unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
@@ -250,19 +253,24 @@ const struct fan_t fans[FAN_CH_COUNT] = {
 /*
  * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
  * 130 C.  However, sensor is located next to DDR, so we need to use the lower
- * DDR temperature limit (85 C)
+ * DDR temperature limit (100 C)
  */
-const static struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(35),
-	.temp_fan_max = C_TO_K(50),
-};
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(90), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(100), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(85), \
+		}, \
+		.temp_fan_off = C_TO_K(30), \
+		.temp_fan_max = C_TO_K(60), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 
 /*
  * Inductor limits - used for both charger and PP3300 regulator
@@ -273,26 +281,31 @@ const static struct ec_thermal_config thermal_cpu = {
  * PP3300 regulator: operating range -40 C to 145 C
  *
  * Inductors: limit of 125c
- * PCB: limit is 80c
+ * PCB: limit is 100c
  */
-const static struct ec_thermal_config thermal_inductor = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(55),
-};
-
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_INDUCTOR         \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(90), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(100), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(85), \
+		}, \
+		.temp_fan_off = C_TO_K(30), \
+		.temp_fan_max = C_TO_K(60), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_inductor =
+	THERMAL_INDUCTOR;
 
 struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_CHARGER]			= thermal_inductor,
-	[TEMP_SENSOR_2_PP3300_REGULATOR]	= thermal_inductor,
-	[TEMP_SENSOR_3_DDR_SOC]			= thermal_cpu,
-	[TEMP_SENSOR_4_FAN]			= thermal_cpu,
+	[TEMP_SENSOR_1_CHARGER] = THERMAL_INDUCTOR,
+	[TEMP_SENSOR_2_PP3300_REGULATOR] = THERMAL_INDUCTOR,
+	[TEMP_SENSOR_3_DDR_SOC] = THERMAL_CPU,
+	[TEMP_SENSOR_4_FAN] = THERMAL_CPU,
 };
 BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
 
@@ -385,42 +398,59 @@ const struct pwm_t pwm_channels[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
-/* USBC TCPC configuration for port 1 on USB3 board */
-static const struct tcpc_config_t tcpc_config_p1_usb3 = {
-	.bus_type = EC_BUS_TYPE_I2C,
-	.i2c_info = {
-		.port = I2C_PORT_USB_C1,
-		.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-	},
-	.flags = TCPC_FLAGS_TCPCI_REV2_0 | TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V,
-	.drv = &ps8xxx_tcpm_drv,
-	.usb23 = USBC_PORT_1_USB2_NUM | (USBC_PORT_1_USB3_NUM << 4),
-};
+static void kb_backlight_enable(void)
+{
+	if (ec_cfg_has_keyboard_backlight() == 1)
+		gpio_set_level(GPIO_EC_KB_BL_EN, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, kb_backlight_enable, HOOK_PRIO_DEFAULT);
 
-static const struct usb_mux usbc1_usb3_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	.next_mux = NULL,
-};
+static void kb_backlight_disable(void)
+{
+	if (ec_cfg_has_keyboard_backlight() == 1)
+		gpio_set_level(GPIO_EC_KB_BL_EN, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, kb_backlight_disable, HOOK_PRIO_DEFAULT);
 
-static const struct usb_mux mux_config_p1_usb3 = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-	.next_mux = &usbc1_usb3_db_retimer,
+/* USB-A charging control */
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_PP5000_USBA,
 };
 
-void board_reset_pd_mcu(void)
+static void ps8815_reset(void)
 {
-	/* TODO(b/159024035): Malefor: check USB PD reset operation */
+	int val;
+
+	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 0);
+	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS));
+	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 1);
+	msleep(PS8815_FW_INIT_DELAY_MS);
+
+	/*
+	 * b/144397088
+	 * ps8815 firmware 0x01 needs special configuration
+	 */
+
+	CPRINTS("%s: patching ps8815 registers", __func__);
+
+	if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) ==
+	    EC_SUCCESS)
+		CPRINTS("ps8815: reg 0x0f was %02x", val);
+
+	if (i2c_write8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f,
+		       0x31) == EC_SUCCESS)
+		CPRINTS("ps8815: reg 0x0f set to 0x31");
+
+	if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) ==
+	    EC_SUCCESS)
+		CPRINTS("ps8815: reg 0x0f now %02x", val);
 }
 
-__override void board_cbi_init(void)
+void board_reset_pd_mcu(void)
 {
-	/* Config DB USB3 */
-	tcpc_config[USBC_PORT_C1] = tcpc_config_p1_usb3;
-	usb_muxes[USBC_PORT_C1] = mux_config_p1_usb3;
+	ps8815_reset();
+	usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
 
 /******************************************************************************/
@@ -450,6 +480,7 @@ void ppc_interrupt(enum gpio_signal signal)
 		break;
 	case GPIO_USB_C1_PPC_INT_ODL:
 		syv682x_interrupt(USBC_PORT_C1);
+		break;
 	default:
 		break;
 	}
@@ -476,19 +507,19 @@ struct tcpc_config_t tcpc_config[] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = I2C_PORT_USB_C0,
-			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
+			.addr_flags = RT1715_I2C_ADDR_FLAGS,
 		},
-		.drv = &tusb422_tcpm_drv,
-		.usb23 = USBC_PORT_0_USB2_NUM | (USBC_PORT_0_USB3_NUM << 4),
+		.drv = &rt1715_tcpm_drv,
 	},
 	[USBC_PORT_C1] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = I2C_PORT_USB_C1,
-			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
 		},
-		.drv = &tusb422_tcpm_drv,
-		.usb23 = USBC_PORT_1_USB2_NUM | (USBC_PORT_1_USB3_NUM << 4),
+		.flags = TCPC_FLAGS_TCPCI_REV2_0
+		 | TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V,
+		.drv = &ps8xxx_tcpm_drv,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
@@ -496,37 +527,35 @@ BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
 
 /******************************************************************************/
 /* USBC mux configuration - Tiger Lake includes internal mux */
-struct usb_mux usbc1_usb4_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &bb_usb_retimer,
-	.i2c_port = I2C_PORT_USB_1_MIX,
-	.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
-};
-struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc1_usb4_db_retimer,
-	},
+static const struct usb_mux_chain usbc1_usb3_db_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
+	.next = NULL,
 };
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
 
-struct bb_usb_control bb_controls[] = {
+const struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		/* USB-C port 0 doesn't have a retimer */
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = NULL,
 	},
 	[USBC_PORT_C1] = {
-		.usb_ls_en_gpio = GPIO_USB_C1_LS_EN,
-		.retimer_rst_gpio = GPIO_USB_C1_RT_RST_ODL,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc1_usb3_db_retimer,
 	},
 };
-BUILD_ASSERT(ARRAY_SIZE(bb_controls) == USBC_PORT_COUNT);
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
 
 static void board_tcpc_init(void)
 {
@@ -545,6 +574,13 @@ static void board_tcpc_init(void)
 	/* Enable BC1.2 interrupts. */
 	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
 	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
+
+	if (get_board_id() <= 1) {
+		tcpc_config[USBC_PORT_C0].i2c_info.addr_flags =
+			TUSB422_I2C_ADDR_FLAGS;
+		tcpc_config[USBC_PORT_C0].drv = &tusb422_tcpm_drv;
+		tcpc_config[USBC_PORT_C0].flags = 0;
+	}
 }
 DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
 
diff --git a/board/lindar/board.h b/board/lindar/board.h
index bacac9d015..7c407d05a7 100644
--- a/board/lindar/board.h
+++ b/board/lindar/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,9 @@
 /* Baseboard features */
 #include "baseboard.h"
 
-/* Optional features */
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
+#undef CONFIG_CHIP_INIT_ROM_REGION
+
+#define CONFIG_VBOOT_EFS2
 
 #define CONFIG_POWER_BUTTON
 
@@ -20,19 +21,17 @@
 #define CONFIG_UART_TX_BUF_SIZE 4096
 
 /* LED defines */
-#define CONFIG_LED_POWER_LED
 #define CONFIG_LED_ONOFF_STATES
 
 /* Keyboard features */
 
 /* Sensors */
 #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-#define CONFIG_ACCEL_LIS2DE             /* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM        /* Base accel */
+#define CONFIG_ACCEL_LIS2DE /* Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
 
 /* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
-	BIT(LID_ACCEL)
+#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
 
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_UPDATE
@@ -43,39 +42,29 @@
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 
 /* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
-
-/*
- * USB-C port's USB2 & USB3 mapping from schematics
- * USB2 numbering on PCH - 1 to n
- * USB3 numbering on AP - 0 to n (PMC's USB3 numbering for MUX
- * configuration is - 1 to n hence add +1)
- */
-#define USBC_PORT_0_USB2_NUM	9
-#define USBC_PORT_0_USB3_NUM	1
-#define USBC_PORT_1_USB2_NUM	4
-#define USBC_PORT_1_USB3_NUM	2
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
 
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
 
 /*
  * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
  * cables only support up to 60W.
  */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
-/* Enabling USB4 mode */
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x40
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 45000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
+
+#undef CONFIG_USB_MUX_RUNTIME_CONFIG
 
 /* USB Type A Features */
+#define USB_PORT_COUNT 1
+#define CONFIG_USB_PORT_POWER_DUMB
 
 /* USBC PPC*/
-#define CONFIG_USBC_PPC_SN5S330		/* USBC port C0 */
-#define CONFIG_USBC_PPC_SYV682X		/* USBC port C1 */
+#define CONFIG_USBC_PPC_SN5S330 /* USBC port C0 */
+#define CONFIG_USBC_PPC_SYV682X /* USBC port C1 */
 
 /* BC 1.2 */
 
@@ -84,8 +73,15 @@
 /* Fan features */
 
 /* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+
+/* Retimer */
+#undef CONFIG_USBC_RETIMER_INTEL_BB
+#undef CONFIG_USBC_RETIMER_INTEL_BB_RUNTIME_CONFIG
+
+/* EC console commands */
+#define CONFIG_CMD_TCPC_DUMP
 
 /*
  * Macros for GPIO signals used in common code that don't match the
@@ -93,45 +89,43 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SYS_PWROK		GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD		GPIO_PG_EC_RSMRST_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_MUTE_BTN_ODL
-#define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE_L
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_LID_OPEN GPIO_EC_LID_OPEN
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_MUTE_BTN_ODL
 
 /* I2C Bus Configuration */
 #define CONFIG_I2C
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_LIGHTBAR	NPCX_I2C_PORT3_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-#define I2C_PORT_USB_1_MIX	NPCX_I2C_COUNT
+#define CONFIG_I2C_BUS_MAY_BE_UNPOWERED
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0
+#define I2C_PORT_LIGHTBAR NPCX_I2C_PORT3_0
+#define I2C_PORT_POWER NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
 
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
+#define I2C_PORT_BATTERY I2C_PORT_POWER
+#define I2C_PORT_CHARGER I2C_PORT_EEPROM
 
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-#define CONFIG_I2C_MASTER
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+#define CONFIG_I2C_CONTROLLER
 
 #ifndef __ASSEMBLER__
 
@@ -159,11 +153,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 void board_reset_pd_mcu(void);
 
diff --git a/board/lindar/build.mk b/board/lindar/build.mk
index 279b2e559e..d590255d2a 100644
--- a/board/lindar/build.mk
+++ b/board/lindar/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -8,7 +8,7 @@
 
 CHIP:=npcx
 CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
+CHIP_VARIANT:=npcx7m7fc
 BASEBOARD:=volteer
 
 board-y=board.o
diff --git a/board/lindar/ec.tasklist b/board/lindar/ec.tasklist
index 292de51cdb..c29125d517 100644
--- a/board/lindar/ec.tasklist
+++ b/board/lindar/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,6 +16,7 @@
 	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
 	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
 	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
 	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
 	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
 	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
diff --git a/board/lindar/gpio.inc b/board/lindar/gpio.inc
index 611512a7b6..f8c036b96c 100644
--- a/board/lindar/gpio.inc
+++ b/board/lindar/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,7 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
@@ -83,6 +83,9 @@ GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
 GPIO(EC_PCH_INT_ODL,           PIN(B, 0), GPIO_ODR_HIGH)
 
 /* USB and USBC Signals */
+GPIO(EN_PP5000_USBA,		PIN(C, 6), GPIO_OUT_LOW)	/* Enable USB-A charging - all ports */
+GPIO(USB_A_LOW_PWR_OD,		PIN(6, 6), GPIO_ODR_LOW)	/* Don't limit USB-A charging by default - all ports */
+
 GPIO(USB_C1_RT_RST_ODL,			PIN(8, 3), GPIO_ODR_LOW) /* USB_C1 Reset on boards board ID >=1 */
 GPIO(USB_C0_OC_ODL,			PIN(B, 1), GPIO_ODR_HIGH)
 GPIO(USB_C1_OC_ODL,			PIN(5, 0), GPIO_ODR_HIGH)
@@ -92,12 +95,13 @@ UNIMPLEMENTED(USB_C1_LS_EN)
 
 /* Misc Signals */
 GPIO(EC_H1_PACKET_MODE,		PIN(7, 5), GPIO_OUT_LOW)	/* H1 Packet Mode */
+GPIO(CCD_MODE_ODL,		PIN(E, 5), GPIO_INPUT)		/* Case Closed Debug Mode */
 
 /*
- * Determine the polarity of these SSD signals and whether
- * they are open-drain.
+ * Despite their names, M2_SSD_PLN and M2_SSD_PLA are active-low, and M2_SSD_PLN
+ * is open-drain.
  */
-GPIO(M2_SSD_PLN,		PIN(A, 0), GPIO_OUT_HIGH)	/* SSD power-loss notification */
+GPIO(M2_SSD_PLN,		PIN(A, 0), GPIO_ODR_HIGH)	/* SSD power-loss notification */
 GPIO(M2_SSD_PLA,		PIN(7, 0), GPIO_INPUT)		/* SSD power-loss acknoledgement */
 
 /*
@@ -144,6 +148,7 @@ ALTERNATE(PIN_MASK(4, BIT(0)), 0, MODULE_PWM, 0)	/* FAN_SPEED_TACH */
 
 /* Keyboard pins */
 #define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
+GPIO(EC_KB_BL_EN,              PIN(8, 6), GPIO_OUT_LOW)     /* Keyboard backlight */
 ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_00-01 */
 ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_02-07 */
 ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_00-01 */
@@ -162,6 +167,10 @@ ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)  /* GPIO00 =
                                                                        GPIO01 = H1_EC_PWR_BTN_ODL
                                                                        GPIO02 = EC_RST_ODL */
 
+/* Temperature sensors */
+ALTERNATE(PIN_MASK(4, BIT(2) | BIT(4) | BIT(5)), 0, MODULE_ADC, 0) /* TEMP_SENSOR1,2,4 */
+ALTERNATE(PIN_MASK(F, BIT(1)), 0, MODULE_ADC, 0) /* TEMP_SENSOR3 */
+
 /* Unused signals */
 GPIO(UNUSED_GPIO60,    PIN(6, 0), GPIO_INPUT | GPIO_PULL_UP)
 GPIO(UNUSED_GPIO34,    PIN(3, 4), GPIO_INPUT | GPIO_PULL_UP)
diff --git a/board/lindar/ktd20xx.h b/board/lindar/ktd20xx.h
new file mode 100644
index 0000000000..63e3bfb363
--- /dev/null
+++ b/board/lindar/ktd20xx.h
@@ -0,0 +1,141 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Public header for Kinetic 36-Channel RGB LED Drivers with I2C control,
+ * including KTD2061/58/59/60.
+ */
+
+#ifndef __CROS_EC_DRIVER_RGB_LED_DRIVER_KTD20XX_PUBLIC_H
+#define __CROS_EC_DRIVER_RGB_LED_DRIVER_KTD20XX_PUBLIC_H
+
+/*
+ * KTD20xx Register Definition
+ *
+ * Reg0x00: ID Data Register
+ *   skip...
+ * Reg0x01: MONITOR Status Register
+ *   skip...
+ * Reg0x02: CONTROL Configuration Register
+ *   BIT7:6 is EN_MODE[1:0]
+ *     00 = global off, 01 = Night mode,
+ *     10 = Normal mode, 11 = reset as default
+ *   BIT5 is BrightExtendTM Enable
+ *     0 = disable/1 = enable
+ *   BIT4:3 is CoolExtendTM Temperature Setting
+ *     00 = 135°C rising, 01 = 120°C
+ *     10 = 105°C, 11 = 90°C
+ *   BIT2:0 is Fade Rate Exponential Time-Constant Setting
+ *     000 = 31ms, 001 = 63ms, 010 = 125ms, 011 = 250ms
+ *     100 = 500ms, 101 = 1s, 110 = 2s, 111 = 4s
+ *
+ * Reg0x03: IRED0 Color Configuration Register
+ *   IRED_SET0[7:0] Red Current Setting 0
+ *     0000 0000 = 0μA
+ *     0000 0001 = 125μA
+ *     ...
+ *     0010 1000 = 5mA
+ *     ...
+ *     1100 0000 = 24mA
+ *     1100 0001 = 24mA (reads back as 1100 0000)
+ *     ...
+ *     1111 1111 = 24mA (reads back as 1100 0000)
+ * Reg0x04: IGRN0 Color Configuration Register
+ *   IGRN_SET0[7:0] Green Current Setting 0
+ * Reg0x05: IBLU0 Color Configuration Register
+ *   IBLU_SET0[7:0] Blue Current Setting 0
+ * Reg0x06: IRED1 Color Configuration Register
+ *   IRED_SET1[7:0] Red Current Setting 1
+ * Reg0x07: IGRN1 Color Configuration Register
+ *   IGRN_SET1[7:0] Green Current Setting 1
+ * Reg0x08: IBLU1 Color Configuration Register
+ *   IBLU_SET1[7:0] Blue Current Setting 1
+ *
+ * Reg0x09: ISELA12 Selection Configuration Register
+ *   BIT7 is ENA1, Enable RGB with anode connected to LEDA1 pin
+ *     0 = use 0μA for these LEDs (includes fade to 0μA)
+ *     1 = use the settings selected by RGBA1_SEL[2:0]
+ *   BIT6:4 is RGBA1_SEL[2:0]
+ *     Current Selection for RGB with anode connected to LEDA1 pin
+ *     0XX = I LEDA3 selects IRED_SET0[7:0]
+ *     1XX = I LEDA3 selects IRED_SET1[7:0]
+ *     X0X = I LEDA2 selects IGRN_SET0[7:0]
+ *     X1X = I LEDA2 selects IGRN_SET1[7:0]
+ *     XX0 = I LEDA4 selects IBLU_SET0[7:0]
+ *     XX1 = I LEDA4 selects IBLU_SET1[7:0]
+ *   BIT3 IS ENA2
+ *     0 = use 0μA for these LEDs (includes fade to 0μA)
+ *     1 = use the settings selected by RGBA2_SEL[2:0]
+ *   BIT2:0 is RGBA2_SEL[2:0]
+ *     Current Selection for RGB with anode connected to LEDA2 pin
+ *     0XX = I LEDA4 selects IRED_SET0[7:0]
+ *     1XX = I LEDA4 selects IRED_SET1[7:0]
+ *     X0X = I LEDA3 selects IGRN_SET0[7:0]
+ *     X1X = I LEDA3 selects IGRN_SET1[7:0]
+ *     XX0 = I LEDA1 selects IBLU_SET0[7:0]
+ *     XX1 = I LEDA1 selects IBLU_SET1[7:0]
+ * Reg0x0A: ISELA34 Selection Configuration Register
+ *   BIT7 is ENA3, Enable RGB with anode connected to LEDA3 pin
+ *     0 = use 0μA for these LEDs (includes fade to 0μA)
+ *     1 = use the settings selected by RGBA3_SEL[2:0]
+ *   BIT6:4 is RGBA3_SEL[2:0]
+ *     Current Selection for RGB with anode connected to LEDA3 pin
+ *     0XX = I LEDA1 selects IRED_SET0[7:0]
+ *     1XX = I LEDA1 selects IRED_SET1[7:0]
+ *     X0X = I LEDA4 selects IGRN_SET0[7:0]
+ *     X1X = I LEDA4 selects IGRN_SET1[7:0]
+ *     XX0 = I LEDA2 selects IBLU_SET0[7:0]
+ *     XX1 = I LEDA2 selects IBLU_SET1[7:0]
+ *   BIT3 IS ENA4
+ *     0 = use 0μA for these LEDs (includes fade to 0μA)
+ *     1 = use the settings selected by RGBA4_SEL[2:0]
+ *   BIT2:0 is RGBA4_SEL[2:0]
+ *     Current Selection for RGB with anode connected to LEDA4 pin
+ *     0XX = I LEDA2 selects IRED_SET0[7:0]
+ *     1XX = I LEDA2 selects IRED_SET1[7:0]
+ *     X0X = I LEDA1 selects IGRN_SET0[7:0]
+ *     X1X = I LEDA1 selects IGRN_SET1[7:0]
+ *     XX0 = I LEDA3 selects IBLU_SET0[7:0]
+ *     XX1 = I LEDA3 selects IBLU_SET1[7:0]
+ * Reg0x0B: ISELB12 Selection Configuration Register
+ *     BIT7 is ENB1, Enable RGB with anode connected to LEDB1 pin
+ *     0 = use 0μA for these LEDs (includes fade to 0μA)
+ *     1 = use the settings selected by RGB1_SEL[2:0]
+ *   BIT6:4 is RGBB1_SEL[2:0]
+ *     Current Selection for RGB with anode connected to LEDB1 pin
+ *     0XX = I LEDB3 selects IRED_SET0[7:0]
+ *     1XX = I LEDB3 selects IRED_SET1[7:0]
+ *     X0X = I LEDB2 selects IGRN_SET0[7:0]
+ *     X1X = I LEDB2 selects IGRN_SET1[7:0]
+ *     XX0 = I LEDB4 selects IBLU_SET0[7:0]
+ *     XX1 = I LEDB4 selects IBLU_SET1[7:0]
+ *   BIT3 IS ENB2
+ *     ...
+ * Reg0x0C: ISELB34 Selection Configuration Register
+ *   ...
+ * Reg0x0D: ISELC12 Selection Configuration Register
+ *   ...
+ * Reg0x0E: ISELC34 Selection Configuration Register
+ *   ...
+ */
+
+enum ktd20xx_register {
+	KTD20XX_ID_DATA = 0x00,
+	KTD20XX_STATUS_REG = 0x01,
+	KTD20XX_CTRL_CFG = 0x02,
+	KTD20XX_IRED_SET0 = 0x03,
+	KTD20XX_IGRN_SET0 = 0x04,
+	KTD20XX_IBLU_SET0 = 0x05,
+	KTD20XX_IRED_SET1 = 0x06,
+	KTD20XX_IGRN_SET1 = 0x07,
+	KTD20XX_IBLU_SET1 = 0x08,
+	KTD20XX_ISEL_A12 = 0x09,
+	KTD20XX_ISEL_A34 = 0x0A,
+	KTD20XX_ISEL_B12 = 0x0B,
+	KTD20XX_ISEL_B34 = 0x0C,
+	KTD20XX_ISEL_C12 = 0x0D,
+	KTD20XX_ISEL_C34 = 0x0E,
+	KTD20XX_TOTOAL_REG
+};
+
+#endif /* __CROS_EC_DRIVER_RGB_LED_DRIVER_KTD20XX_PUBLIC_H */
diff --git a/board/lindar/led.c b/board/lindar/led.c
index 6f4e781404..9ad7b48fb2 100644
--- a/board/lindar/led.c
+++ b/board/lindar/led.c
@@ -1,52 +1,75 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Power and battery LED control for Malefor
  */
 
+#include "cbi_ssfc.h"
+#include "charge_state.h"
 #include "common.h"
-#include "led_onoff_states.h"
-#include "led_common.h"
+#include "cros_board_info.h"
+#include "extpower.h"
 #include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "i2c.h"
+#include "ktd20xx.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+#include "lid_switch.h"
+#include "stdbool.h"
+#include "task.h"
+#include "timer.h"
+#include "util.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
 
-const int led_charge_lvl_1 = 5;
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
-const int led_charge_lvl_2 = 97;
+__override const int led_charge_lvl_1 = 5;
 
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED,   LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,   1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
+__override const int led_charge_lvl_2 = 97;
 
-const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]            = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]    = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-					 {LED_OFF,         0.5 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF,            LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF,            LED_INDEFINITE} },
-};
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    1 * LED_ONE_SEC },
+						  { LED_OFF,
+						    3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-void led_set_color_power(enum ec_led_colors color)
+__override void led_set_color_power(enum ec_led_colors color)
 {
 	if (color == EC_LED_COLOR_WHITE)
 		gpio_set_level(GPIO_LED_3_L, LED_ON_LVL);
@@ -55,17 +78,17 @@ void led_set_color_power(enum ec_led_colors color)
 		gpio_set_level(GPIO_LED_3_L, LED_OFF_LVL);
 }
 
-void led_set_color_battery(enum ec_led_colors color)
+__override void led_set_color_battery(enum ec_led_colors color)
 {
 	switch (color) {
-	case EC_LED_COLOR_RED:
-		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_ON_LVL);
-		break;
 	case EC_LED_COLOR_AMBER:
 		gpio_set_level(GPIO_LED_1_L, LED_ON_LVL);
 		gpio_set_level(GPIO_LED_2_L, LED_ON_LVL);
 		break;
+	case EC_LED_COLOR_RED:
+		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_2_L, LED_ON_LVL);
+		break;
 	case EC_LED_COLOR_GREEN:
 		gpio_set_level(GPIO_LED_1_L, LED_ON_LVL);
 		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
@@ -108,3 +131,631 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 
 	return EC_SUCCESS;
 }
+
+static const uint16_t ktd2061_i2c_addr = 0x68;
+static void controller_write(uint8_t reg, uint8_t val)
+{
+	uint8_t buf[2];
+
+	buf[0] = reg;
+	buf[1] = val;
+
+	i2c_xfer_unlocked(I2C_PORT_LIGHTBAR, ktd2061_i2c_addr, buf, 2, 0, 0,
+			  I2C_XFER_SINGLE);
+}
+
+enum lightbar_states {
+	LB_STATE_OFF,
+	LB_STATE_LID_CLOSE,
+	LB_STATE_SLEEP_AC_ONLY,
+	LB_STATE_SLEEP_AC_BAT_LOW,
+	LB_STATE_SLEEP_AC_BAT_LV1,
+	LB_STATE_SLEEP_AC_BAT_LV2,
+	LB_STATE_SLEEP_AC_BAT_LV3,
+	LB_STATE_SLEEP_AC_BAT_LV4,
+	LB_STATE_SLEEP_BAT_LOW,
+	LB_STATE_SLEEP_BAT_ONLY,
+	LB_STATE_S0_AC_ONLY,
+	LB_STATE_S0_BAT_LOW,
+	LB_STATE_S0_BAT_LV1,
+	LB_STATE_S0_BAT_LV2,
+	LB_STATE_S0_BAT_LV3,
+	LB_STATE_S0_BAT_LV4,
+	LB_NUM_STATES
+};
+
+/*
+ * All lightbar states should have one phase defined,
+ * and an additional phase can be defined for blinking
+ */
+enum lightbar_phase {
+	LIGHTBAR_PHASE_0 = 0,
+	LIGHTBAR_PHASE_1 = 1,
+	LIGHTBAR_NUM_PHASES
+};
+
+enum ec_lightbar_colors {
+	BAR_RESET,
+	BAR_OFF,
+	BAR_COLOR_ORG_20_PERCENT,
+	BAR_COLOR_GRN_40_PERCENT,
+	BAR_COLOR_GRN_60_PERCENT,
+	BAR_COLOR_GRN_80_PERCENT,
+	BAR_COLOR_GRN_FULL,
+	BAR_COLOR_ORG_FULL,
+	LIGHTBAR_COLOR_TOTAL
+};
+
+struct lightbar_descriptor {
+	enum ec_lightbar_colors color;
+	uint8_t ticks;
+};
+
+#define BAR_INFINITE UINT8_MAX
+#define LIGHTBAR_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS)
+#define LIGHTBAR_COUNT_FOR_RESUME_FROM_SLEEP (3 * LIGHTBAR_ONE_SEC)
+int lightbar_resume_tick;
+
+const struct lightbar_descriptor lb_table[LB_NUM_STATES][LIGHTBAR_NUM_PHASES] = {
+	[LB_STATE_OFF] = { { BAR_OFF, BAR_INFINITE } },
+	[LB_STATE_LID_CLOSE] = { { BAR_OFF, BAR_INFINITE } },
+	[LB_STATE_SLEEP_AC_ONLY] = { { BAR_OFF, BAR_INFINITE } },
+	[LB_STATE_SLEEP_AC_BAT_LOW] = { { BAR_COLOR_ORG_20_PERCENT,
+					  BAR_INFINITE } },
+	[LB_STATE_SLEEP_AC_BAT_LV1] = { { BAR_COLOR_GRN_40_PERCENT,
+					  BAR_INFINITE } },
+	[LB_STATE_SLEEP_AC_BAT_LV2] = { { BAR_COLOR_GRN_60_PERCENT,
+					  BAR_INFINITE } },
+	[LB_STATE_SLEEP_AC_BAT_LV3] = { { BAR_COLOR_GRN_80_PERCENT,
+					  BAR_INFINITE } },
+	[LB_STATE_SLEEP_AC_BAT_LV4] = { { BAR_COLOR_GRN_FULL, BAR_INFINITE } },
+	[LB_STATE_SLEEP_BAT_LOW] = { { BAR_OFF, 5 * LIGHTBAR_ONE_SEC },
+				     { BAR_COLOR_ORG_FULL, LIGHTBAR_ONE_SEC } },
+	[LB_STATE_SLEEP_BAT_ONLY] = { { BAR_OFF, BAR_INFINITE } },
+	[LB_STATE_S0_AC_ONLY] = { { BAR_OFF, BAR_INFINITE } },
+	[LB_STATE_S0_BAT_LOW] = { { BAR_COLOR_ORG_20_PERCENT, BAR_INFINITE } },
+	[LB_STATE_S0_BAT_LV1] = { { BAR_COLOR_GRN_40_PERCENT, BAR_INFINITE } },
+	[LB_STATE_S0_BAT_LV2] = { { BAR_COLOR_GRN_60_PERCENT, BAR_INFINITE } },
+	[LB_STATE_S0_BAT_LV3] = { { BAR_COLOR_GRN_80_PERCENT, BAR_INFINITE } },
+	[LB_STATE_S0_BAT_LV4] = { { BAR_COLOR_GRN_FULL, BAR_INFINITE } },
+};
+
+#define DISABLE_LIGHTBAR 0x00
+#define ENABLE_LIGHTBAR 0x80
+#define I_OFF 0x00
+#define GRN_I_ON 0x1E
+#define ORG_I_ON 0x28
+#define SEL_OFF 0x00
+#define SEL_1ST_LED BIT(7)
+#define SEL_2ND_LED BIT(3)
+#define SEL_BOTH (SEL_1ST_LED | SEL_2ND_LED)
+#define SKU_ID_NONE 0x00
+#define SKU_ID_INVALID 0x01
+#define LB_SUPPORTED_SKUID_LOWER 458700
+#define LB_SUPPORTED_SKUID_UPPER 458800
+
+static bool lightbar_is_supported(void)
+{
+	static uint32_t skuid = SKU_ID_NONE;
+	bool result;
+
+	/* lindar add SSFC tag to cbi image from "board_id = 3". */
+	if (get_board_id() >= 3) {
+		if (get_cbi_ssfc_lightbar() == SSFC_LIGHTBAR_NONE)
+			return false;
+		return true;
+	}
+
+	if (skuid == SKU_ID_NONE) {
+		if (cbi_get_sku_id(&skuid)) {
+			CPRINTS("Cannot get skuid for lightbar supported");
+			skuid = SKU_ID_INVALID;
+		}
+	}
+
+	/*
+	 * If board_id = 1 or 2, it needs to check sku_id to know
+	 * if system support lightbar or not.
+	 */
+	if (skuid >= LB_SUPPORTED_SKUID_LOWER &&
+	    skuid <= LB_SUPPORTED_SKUID_UPPER)
+		result = true;
+	else
+		result = false;
+
+	return result;
+}
+
+/*
+ * lightbar_enter_s0ix_s3:
+ * This flag is used to know if system ever enter S0ix/S3.
+ * Lightbar V9 SPEC define lightbar resuming behavior, "S0ix/S3 -> S0",
+ * but not include "G3/S5/S4 -> S0". "G3/S5/S4 -> S0" need to keep off.
+ */
+static bool lightbar_enter_s0ix_s3;
+
+/*
+ * lightbar_auto_control:
+ * We need some command for testing lightbar in factory.
+ * So, create this flag to stop regular action in lightbar_update().
+ *
+ * lightbar_demo_state:
+ * It's used for testing lightbar via executing command under
+ * console.
+ */
+static bool lightbar_auto_control;
+static enum lightbar_states lightbar_demo_state;
+
+static void lightbar_set_auto_control(bool state)
+{
+	lightbar_auto_control = state;
+}
+
+static bool lightbar_is_auto_control(void)
+{
+	return lightbar_auto_control;
+}
+
+static void lightbar_set_demo_state(enum lightbar_states tmp_state)
+{
+	if (tmp_state >= LB_NUM_STATES || tmp_state < LB_STATE_OFF) {
+		lightbar_demo_state = LB_NUM_STATES;
+		lightbar_resume_tick = 0;
+	} else {
+		lightbar_demo_state = tmp_state;
+
+		if (lightbar_demo_state >= LB_STATE_S0_AC_ONLY)
+			lightbar_resume_tick =
+				LIGHTBAR_COUNT_FOR_RESUME_FROM_SLEEP;
+	}
+	ccprintf("lightbar_demo_state = %d; lightbar_resume_tick %d.\n",
+		 lightbar_demo_state, lightbar_resume_tick);
+}
+
+static enum lightbar_states lightbar_get_demo_state(void)
+{
+	/*
+	 * Once tick count to zero, it needs to return LB_STATE_OFF to
+	 * simulate lightbar off.
+	 */
+	if ((lightbar_demo_state != LB_NUM_STATES) &&
+	    (lightbar_demo_state >= LB_STATE_S0_AC_ONLY) &&
+	    (lightbar_resume_tick == 0))
+		return LB_STATE_OFF;
+
+	return lightbar_demo_state;
+}
+
+static bool lightbar_is_enabled(void)
+{
+	if (!lightbar_is_supported())
+		return false;
+
+	/*
+	 * Lightbar's I2C is powered by PP3300_A, and its power will be turn
+	 * when system enter S4/S5. It may get I2C error if EC keep polling
+	 * lightbar. We should stop it when EC doesn't turn on PP330_A.
+	 */
+	if (!board_is_i2c_port_powered(I2C_PORT_LIGHTBAR))
+		return false;
+
+	return true;
+}
+
+/*
+ * From "board_id = 3", HW change lightbar circuit, and it only support
+ * two colors, orange (amber) and green. It connects KTD20xx's red-channel
+ * green color led, and green-channel to orange color led.
+ * Blue-channel is unused.
+ *
+ * The configuration format of lightbar_xx_led_cfg's is as below.
+ * ID_DAT, STATUS_REG, CTRL_CFG
+ * IRED_SET0, IGRN_SET0, IBLU_SET0, IRED_SET1, IGRN_SET1, IBLU_SET1
+ * ISEL_A12, ISEL_A34, ISEL_B12, ISEL_B34, ISEL_C12, ISEL_C34
+ */
+const uint8_t lightbar_10_led_cfg[LIGHTBAR_COLOR_TOTAL][KTD20XX_TOTOAL_REG] = {
+	[BAR_RESET] = { 0x00, 0x00, DISABLE_LIGHTBAR, I_OFF, I_OFF, I_OFF,
+			I_OFF, I_OFF, I_OFF, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF,
+			SEL_OFF, SEL_OFF },
+	[BAR_OFF] = { 0x00, 0x00, DISABLE_LIGHTBAR, I_OFF, I_OFF, I_OFF, I_OFF,
+		      I_OFF, I_OFF, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF,
+		      SEL_OFF },
+	[BAR_COLOR_ORG_20_PERCENT] = { 0x00, 0x00, ENABLE_LIGHTBAR, I_OFF,
+				       ORG_I_ON, I_OFF, I_OFF, I_OFF, I_OFF,
+				       SEL_OFF, SEL_BOTH, SEL_OFF, SEL_OFF,
+				       SEL_OFF, SEL_OFF },
+	[BAR_COLOR_GRN_40_PERCENT] = { 0x00, 0x00, ENABLE_LIGHTBAR, GRN_I_ON,
+				       I_OFF, I_OFF, I_OFF, I_OFF, I_OFF,
+				       SEL_BOTH, SEL_BOTH, SEL_OFF, SEL_OFF,
+				       SEL_OFF, SEL_OFF },
+	[BAR_COLOR_GRN_60_PERCENT] = { 0x00, 0x00, ENABLE_LIGHTBAR, GRN_I_ON,
+				       I_OFF, I_OFF, I_OFF, I_OFF, I_OFF,
+				       SEL_BOTH, SEL_BOTH, SEL_OFF, SEL_BOTH,
+				       SEL_OFF, SEL_OFF },
+	[BAR_COLOR_GRN_80_PERCENT] = { 0x00, 0x00, ENABLE_LIGHTBAR, GRN_I_ON,
+				       I_OFF, I_OFF, I_OFF, I_OFF, I_OFF,
+				       SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH,
+				       SEL_OFF, SEL_OFF },
+	[BAR_COLOR_GRN_FULL] = { 0x00, 0x00, ENABLE_LIGHTBAR, GRN_I_ON, I_OFF,
+				 I_OFF, I_OFF, I_OFF, I_OFF, SEL_BOTH, SEL_BOTH,
+				 SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_OFF },
+	[BAR_COLOR_ORG_FULL] = { 0x00, 0x00, ENABLE_LIGHTBAR, I_OFF, ORG_I_ON,
+				 I_OFF, I_OFF, I_OFF, I_OFF, SEL_BOTH, SEL_BOTH,
+				 SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_OFF }
+};
+
+const uint8_t lightbar_12_led_cfg[LIGHTBAR_COLOR_TOTAL][KTD20XX_TOTOAL_REG] = {
+	[BAR_RESET] = { 0x00, 0x00, DISABLE_LIGHTBAR, I_OFF, I_OFF, I_OFF,
+			I_OFF, I_OFF, I_OFF, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF,
+			SEL_OFF, SEL_OFF },
+	[BAR_OFF] = { 0x00, 0x00, DISABLE_LIGHTBAR, I_OFF, I_OFF, I_OFF, I_OFF,
+		      I_OFF, I_OFF, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF,
+		      SEL_OFF },
+	[BAR_COLOR_ORG_20_PERCENT] = { 0x00, 0x00, ENABLE_LIGHTBAR, I_OFF,
+				       ORG_I_ON, I_OFF, I_OFF, I_OFF, I_OFF,
+				       SEL_2ND_LED, SEL_BOTH, SEL_OFF, SEL_OFF,
+				       SEL_OFF, SEL_OFF },
+	[BAR_COLOR_GRN_40_PERCENT] = { 0x00, 0x00, ENABLE_LIGHTBAR, GRN_I_ON,
+				       I_OFF, I_OFF, I_OFF, I_OFF, I_OFF,
+				       SEL_BOTH, SEL_BOTH, SEL_OFF, SEL_2ND_LED,
+				       SEL_OFF, SEL_OFF },
+	[BAR_COLOR_GRN_60_PERCENT] = { 0x00, 0x00, ENABLE_LIGHTBAR, GRN_I_ON,
+				       I_OFF, I_OFF, I_OFF, I_OFF, I_OFF,
+				       SEL_BOTH, SEL_BOTH, SEL_2ND_LED,
+				       SEL_BOTH, SEL_OFF, SEL_OFF },
+	[BAR_COLOR_GRN_80_PERCENT] = { 0x00, 0x00, ENABLE_LIGHTBAR, GRN_I_ON,
+				       I_OFF, I_OFF, I_OFF, I_OFF, I_OFF,
+				       SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH,
+				       SEL_OFF, SEL_2ND_LED },
+	[BAR_COLOR_GRN_FULL] = { 0x00, 0x00, ENABLE_LIGHTBAR, GRN_I_ON, I_OFF,
+				 I_OFF, I_OFF, I_OFF, I_OFF, SEL_BOTH, SEL_BOTH,
+				 SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH },
+	[BAR_COLOR_ORG_FULL] = { 0x00, 0x00, ENABLE_LIGHTBAR, I_OFF, ORG_I_ON,
+				 I_OFF, I_OFF, I_OFF, I_OFF, SEL_BOTH, SEL_BOTH,
+				 SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH }
+};
+
+/*
+ * lightbar_ctrl is a pointer to 2-dimension lightbar configuration. It's used
+ * to base on DUT type to load different cfg.
+ * Default is lightbar_10_led_cfg.
+ */
+const uint8_t (*lightbar_ctrl)[KTD20XX_TOTOAL_REG] = lightbar_10_led_cfg;
+
+static void lightbar_set_color(enum ec_lightbar_colors color)
+{
+	enum ktd20xx_register i;
+
+	if (color >= LIGHTBAR_COLOR_TOTAL) {
+		CPRINTS("Lightbar Error! Incorrect lightbard color %d", color);
+		color = BAR_RESET;
+	}
+
+	i2c_lock(I2C_PORT_LIGHTBAR, 1);
+	for (i = KTD20XX_IRED_SET0; i <= KTD20XX_ISEL_C34; i++)
+		controller_write(i, lightbar_ctrl[color][i]);
+
+	controller_write(KTD20XX_CTRL_CFG,
+			 lightbar_ctrl[color][KTD20XX_CTRL_CFG]);
+
+	i2c_lock(I2C_PORT_LIGHTBAR, 0);
+}
+
+static void lightbar_init(void)
+{
+	if (!lightbar_is_enabled())
+		return;
+
+	if (get_cbi_ssfc_lightbar() == SSFC_LIGHTBAR_12_LED)
+		lightbar_ctrl = lightbar_12_led_cfg;
+	else
+		lightbar_ctrl = lightbar_10_led_cfg;
+
+	/* Clear this flag if system doesn't enter S0ix/S3 */
+	lightbar_enter_s0ix_s3 = false;
+	lightbar_resume_tick = 0;
+
+	lightbar_set_color(BAR_RESET);
+}
+
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, lightbar_init, HOOK_PRIO_DEFAULT);
+
+static void lightbar_sleep_entry(void)
+{
+	if (!lightbar_is_enabled())
+		return;
+
+	lightbar_set_auto_control(true);
+	/*
+	 * Set this flag, then EC'll base on it to set resume tick after
+	 * S0ix/S3 exit.
+	 */
+	lightbar_enter_s0ix_s3 = true;
+	lightbar_resume_tick = 0;
+
+	lightbar_set_color(BAR_RESET);
+}
+
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, lightbar_sleep_entry, HOOK_PRIO_DEFAULT);
+
+static void lightbar_sleep_exit(void)
+{
+	if (!lightbar_is_enabled())
+		return;
+
+	lightbar_set_auto_control(true);
+	if (lightbar_enter_s0ix_s3)
+		lightbar_resume_tick = LIGHTBAR_COUNT_FOR_RESUME_FROM_SLEEP;
+	else
+		lightbar_resume_tick = 0;
+	lightbar_enter_s0ix_s3 = false;
+}
+
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, lightbar_sleep_exit, HOOK_PRIO_DEFAULT);
+
+#define LB_BAT_THRESHOLD_1 16
+#define LB_BAT_THRESHOLD_2 40
+#define LB_BAT_THRESHOLD_3 60
+#define LB_BAT_THRESHOLD_4 80
+
+static enum lightbar_states lightbar_get_state(void)
+{
+	enum lightbar_states new_state = LB_NUM_STATES;
+	int cur_bat_percent;
+
+	cur_bat_percent = charge_get_percent();
+
+	if (!lid_is_open())
+		return LB_STATE_LID_CLOSE;
+
+	if (lightbar_resume_tick) {
+		if ((battery_is_present() == BP_YES) &&
+		    charge_get_display_charge()) {
+			if (cur_bat_percent < LB_BAT_THRESHOLD_1)
+				new_state = LB_STATE_S0_BAT_LOW;
+			else if (cur_bat_percent < LB_BAT_THRESHOLD_2)
+				new_state = LB_STATE_S0_BAT_LV1;
+			else if (cur_bat_percent < LB_BAT_THRESHOLD_3)
+				new_state = LB_STATE_S0_BAT_LV2;
+			else if (cur_bat_percent < LB_BAT_THRESHOLD_4)
+				new_state = LB_STATE_S0_BAT_LV3;
+			else
+				new_state = LB_STATE_S0_BAT_LV4;
+		} else
+			new_state = LB_STATE_S0_AC_ONLY;
+		return new_state;
+	}
+
+	if (!chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
+		return LB_STATE_OFF;
+
+	if (extpower_is_present()) {
+		if ((battery_is_present() == BP_YES) &&
+		    charge_get_display_charge()) {
+			if (cur_bat_percent < LB_BAT_THRESHOLD_1)
+				new_state = LB_STATE_SLEEP_AC_BAT_LOW;
+			else if (cur_bat_percent < LB_BAT_THRESHOLD_2)
+				new_state = LB_STATE_SLEEP_AC_BAT_LV1;
+			else if (cur_bat_percent < LB_BAT_THRESHOLD_3)
+				new_state = LB_STATE_SLEEP_AC_BAT_LV2;
+			else if (cur_bat_percent < LB_BAT_THRESHOLD_4)
+				new_state = LB_STATE_SLEEP_AC_BAT_LV3;
+			else
+				new_state = LB_STATE_SLEEP_AC_BAT_LV4;
+		} else
+			new_state = LB_STATE_SLEEP_AC_ONLY;
+	} else {
+		if (cur_bat_percent < LB_BAT_THRESHOLD_1)
+			new_state = LB_STATE_SLEEP_BAT_LOW;
+		else
+			new_state = LB_STATE_SLEEP_BAT_ONLY;
+	}
+
+	return new_state;
+}
+
+#define LIGHTBAR_DEBOUNCE_TICKS 1
+static void lightbar_update(void)
+{
+	static uint8_t ticks, period;
+	static enum lightbar_states lb_cur_state = LB_NUM_STATES;
+	static int debounce_lightbar_state_update;
+	enum lightbar_states desired_state;
+	int phase;
+
+	if (!lightbar_is_enabled())
+		return;
+
+	if (lightbar_is_auto_control())
+		desired_state = lightbar_get_state();
+	else {
+		desired_state = lightbar_get_demo_state();
+		/*
+		 * Stop to update lb_cur_state if desired_state is equal to
+		 * LB_NUM_STATES.
+		 */
+		if (desired_state == LB_NUM_STATES)
+			return;
+	}
+
+	if (lightbar_resume_tick)
+		lightbar_resume_tick--;
+
+	if (desired_state != lb_cur_state && desired_state < LB_NUM_STATES) {
+		/* State is changing */
+		lb_cur_state = desired_state;
+		/* Reset ticks and period when state changes */
+		ticks = 0;
+
+		period = lb_table[lb_cur_state][LIGHTBAR_PHASE_0].ticks +
+			 lb_table[lb_cur_state][LIGHTBAR_PHASE_1].ticks;
+
+		/*
+		 * System will be waken up when AC status change in S0ix. Due to
+		 * EC may be late to update chipset state and cause lightbar
+		 * flash a while when system transfer to S0. We add to debounce
+		 * for any lightbar status change.
+		 * It can make sure lightbar state is ready to to update.
+		 */
+		debounce_lightbar_state_update = LIGHTBAR_DEBOUNCE_TICKS;
+	}
+
+	/* If this state is undefined, turn lightbar off */
+	if (period == 0) {
+		CPRINTS("Undefined lightbar behavior for lightbar state %d,"
+			"turning off lightbar",
+			lb_cur_state);
+		lightbar_set_color(BAR_OFF);
+		return;
+	}
+
+	if (debounce_lightbar_state_update != 0) {
+		debounce_lightbar_state_update--;
+		return;
+	}
+
+	/*
+	 * Determine which phase of the state table to use. The phase is
+	 * determined if it falls within first phase time duration.
+	 */
+	phase = ticks < lb_table[lb_cur_state][LIGHTBAR_PHASE_0].ticks ? 0 : 1;
+	ticks = (ticks + 1) % period;
+
+	/* Set the color for the given state and phase */
+	lightbar_set_color(lb_table[lb_cur_state][phase].color);
+}
+
+DECLARE_HOOK(HOOK_TICK, lightbar_update, HOOK_PRIO_DEFAULT);
+
+/****************************************************************************/
+/* EC console commands for lightbar */
+/****************************************************************************/
+static void lightbar_dump_status(void)
+{
+	uint32_t cbi_bid, cbi_skuid;
+	int cbi_ssfc_lightbar;
+
+	ccprintf("lightbar is %ssupported, %sabled, auto_control: %sabled\n",
+		 lightbar_is_supported() ? "" : "un-",
+		 lightbar_is_enabled() ? "en" : "dis",
+		 lightbar_is_auto_control() ? "en" : "dis");
+
+	cbi_bid = get_board_id();
+	cbi_get_sku_id(&cbi_skuid);
+	cbi_ssfc_lightbar = get_cbi_ssfc_lightbar();
+	ccprintf("board id = %d, skuid = %d, ssfc_lightbar = %d\n", cbi_bid,
+		 cbi_skuid, cbi_ssfc_lightbar);
+}
+
+#ifdef CONFIG_CONSOLE_CMDHELP
+static int help(const char *cmd)
+{
+	ccprintf("Usage:\n");
+	ccprintf("  %s                       - dump lightbar status\n", cmd);
+	ccprintf("  %s on                    - set on lightbar auto control\n",
+		 cmd);
+	ccprintf("  %s off                   - set off lightbar auto control\n",
+		 cmd);
+	ccprintf("  %s demo [%x - %x]          - demo lightbar state\n", cmd,
+		 LB_STATE_OFF, (LB_NUM_STATES - 1));
+	return EC_SUCCESS;
+}
+#endif
+
+static int command_lightbar(int argc, const char **argv)
+{
+	/* no args = dump lightbar status */
+	if (argc == 1) {
+		lightbar_dump_status();
+		return EC_SUCCESS;
+	}
+
+	if (!strcasecmp(argv[1], "help")) {
+#ifdef CONFIG_CONSOLE_CMDHELP
+		help(argv[0]);
+#endif
+		return EC_SUCCESS;
+	}
+
+	if (!lightbar_is_enabled()) {
+		lightbar_dump_status();
+		return EC_ERROR_UNIMPLEMENTED;
+	}
+
+	if (!strcasecmp(argv[1], "on")) {
+		lightbar_set_auto_control(true);
+		return EC_SUCCESS;
+	}
+
+	if (!strcasecmp(argv[1], "off")) {
+		lightbar_set_auto_control(false);
+		lightbar_set_demo_state(LB_NUM_STATES);
+		return EC_SUCCESS;
+	}
+
+	if (!strcasecmp(argv[1], "demo")) {
+		int lb_demo_state;
+		char *e;
+
+		/* Need to disable auto_control before demo */
+		if (lightbar_is_auto_control()) {
+			ccprintf("Please set off auto control before demo.\n");
+			return EC_ERROR_ACCESS_DENIED;
+		}
+
+		lb_demo_state = 0xff & strtoi(argv[2], &e, 16);
+		lightbar_set_demo_state(lb_demo_state);
+		return EC_SUCCESS;
+	}
+
+#ifdef CONFIG_CONSOLE_CMDHELP
+	help(argv[0]);
+#endif
+
+	return EC_ERROR_INVAL;
+}
+
+DECLARE_CONSOLE_COMMAND(lightbar, command_lightbar, "[help | on | off | demo]",
+			"get/set lightbar status");
+
+/****************************************************************************/
+/* EC host commands (ectool) for lightbar */
+/****************************************************************************/
+static enum ec_status lpc_cmd_lightbar(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_lightbar *in = args->params;
+	int lb_demo_state;
+
+	/*
+	 * HOST_CMD is binded with ectool. From ectool.c, it already define
+	 * command format.
+	 * We only base on "off", "on", and "seq" to do what we can do
+	 * now.
+	 * Originally, I expect to use "demo", but it limit "in->demo.num"
+	 * within 0~1. So, adopt "seq" command for basic testing.
+	 */
+	switch (in->cmd) {
+	case LIGHTBAR_CMD_OFF:
+		lightbar_set_auto_control(false);
+		lightbar_set_demo_state(LB_NUM_STATES);
+		break;
+	case LIGHTBAR_CMD_ON:
+		lightbar_set_auto_control(true);
+		break;
+	case LIGHTBAR_CMD_SEQ:
+		lb_demo_state = in->seq.num;
+		if (lightbar_is_auto_control()) {
+			CPRINTS("Please set off auto control before demo.");
+			return EC_RES_ACCESS_DENIED;
+		}
+		lightbar_set_demo_state(lb_demo_state);
+		break;
+	default:
+		CPRINTS("LB bad cmd 0x%x", in->cmd);
+		return EC_RES_INVALID_PARAM;
+	}
+
+	return EC_RES_SUCCESS;
+}
+
+DECLARE_HOST_COMMAND(EC_CMD_LIGHTBAR_CMD, lpc_cmd_lightbar, EC_VER_MASK(0));
diff --git a/board/lindar/vif_override.xml b/board/lindar/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/lindar/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/lingcod/battery.c b/board/lingcod/battery.c
deleted file mode 100644
index 7f37c6fe10..0000000000
--- a/board/lingcod/battery.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Volteer battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	[BATTERY_SMP] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP",
-			.device_name = "L19M4PG2",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8800, /* mV */
-			.voltage_normal		= 7680, /* mV */
-			.voltage_min		= 6000, /* mV */
-			.precharge_current	= 332,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-	[BATTERY_LGC] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC",
-			.device_name = "L19L4PG2",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8800, /* mV */
-			.voltage_normal		= 7700, /* mV */
-			/*
-			 * voltage min value and precharge current value are
-			 * specified by LGC directly and not shown in the SPEC.
-			 */
-			.voltage_min		= 6000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 73,
-		},
-	},
-	[BATTERY_SUNWODA] = {
-		.fuel_gauge = {
-			.manuf_name = "SUNWODA",
-			.device_name = "L19D4PG2",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8800, /* mV */
-			.voltage_normal		= 7680, /* mV */
-			.voltage_min		= 6000, /* mV */
-			.precharge_current	= 333,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SMP;
diff --git a/board/lingcod/board.c b/board/lingcod/board.c
deleted file mode 100644
index 28edcce5ae..0000000000
--- a/board/lingcod/board.c
+++ /dev/null
@@ -1,545 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Malefor board-specific configuration */
-#include "bb_retimer.h"
-#include "button.h"
-#include "cbi_ec_fw_config.h"
-#include "common.h"
-#include "driver/accel_lis2dh.h"
-#include "driver/accelgyro_lsm6dsm.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/ppc/syv682x.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/tusb422.h"
-#include "driver/sync.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "tablet_mode.h"
-#include "uart.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ## args)
-
-/* Keyboard scan setting */
-struct keyboard_scan_config keyscan_config = {
-	/* Increase from 50 us, because KSO_02 passes through the H1. */
-	.output_settle_us = 80,
-	/* Other values should be the same as the default configuration. */
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-/******************************************************************************/
-/*
- * FW_CONFIG defaults for Malefor if the CBI data is not initialized.
- */
-union volteer_cbi_fw_config fw_config_defaults = {
-	.usb_db = DB_USB3_NO_A,
-};
-
-static void board_init(void)
-{
-	if (ec_cfg_has_tabletmode()) {
-		/* Enable gpio interrupt for base accelgyro sensor */
-		gpio_enable_interrupt(GPIO_EC_IMU_INT_L);
-	} else {
-		motion_sensor_count = 0;
-		/* Device is clamshell only */
-		tablet_set_mode(0);
-		/* Gyro is not present, don't allow line to float */
-		gpio_set_flags(GPIO_EC_IMU_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
-	}
-
-	/*
-	 * TODO: b/154447182 - Malefor will control power LED and battery LED
-	 * independently, and keep the max brightness of power LED and battery
-	 * LED as 50%.
-	 */
-	pwm_enable(PWM_CH_LED4_SIDESEL, 1);
-	pwm_set_duty(PWM_CH_LED4_SIDESEL, 50);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-int board_is_lid_angle_tablet_mode(void)
-{
-	return ec_cfg_has_tabletmode();
-}
-
-/* Enable or disable input devices, based on tablet mode or chipset state */
-#ifndef TEST_BUILD
-void lid_angle_peripheral_enable(int enable)
-{
-	if (ec_cfg_has_tabletmode()) {
-		if (chipset_in_state(CHIPSET_STATE_ANY_OFF) ||
-			tablet_get_mode())
-			enable = 0;
-		keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
-	}
-}
-#endif
-
-/******************************************************************************/
-/* Sensors */
-/* Lid and base Sensor mutex */
-static struct mutex g_lid_accel_mutex;
-static struct mutex g_base_mutex;
-
-/* Lid and base accel private data */
-static struct stprivate_data g_lis2dh_data;
-static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
-
-/* Matrix to rotate lid and base sensor into standard reference frame */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LIS2DE,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &lis2dh_drv,
-		.mutex = &g_lid_accel_mutex,
-		.drv_data = &g_lis2dh_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LIS2DH_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.min_frequency = LIS2DH_ODR_MIN_VAL,
-		.max_frequency = LIS2DH_ODR_MAX_VAL,
-		.default_range = 2, /* g, to support tablet mode */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_EC_IMU_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 13000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			/* Sensor on for angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_EC_IMU_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-	},
-};
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/******************************************************************************/
-/* Physical fans. These are logically separate from pwm_channels. */
-
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = GPIO_EN_PP5000_FAN,
-};
-
-/*
- * Fan specs from datasheet:
- * Max speed 5900 rpm (+/- 7%), minimum duty cycle 30%.
- * Minimum speed not specified by RPM. Set minimum RPM to max speed (with
- * margin) x 30%.
- *    5900 x 1.07 x 0.30 = 1894, round up to 1900
- */
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 1900,
-	.rpm_start = 1900,
-	.rpm_max = 5900,
-};
-
-const struct fan_t fans[FAN_CH_COUNT] = {
-	[FAN_CH_0] = {
-		.conf = &fan_conf_0,
-		.rpm = &fan_rpm_0,
-	},
-};
-
-/******************************************************************************/
-/* EC thermal management configuration */
-
-/*
- * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
- * 130 C.  However, sensor is located next to DDR, so we need to use the lower
- * DDR temperature limit (85 C)
- */
-const static struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(35),
-	.temp_fan_max = C_TO_K(50),
-};
-
-/*
- * Inductor limits - used for both charger and PP3300 regulator
- *
- * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
- *
- * Charger max recommended temperature 100C, max absolute temperature 125C
- * PP3300 regulator: operating range -40 C to 145 C
- *
- * Inductors: limit of 125c
- * PCB: limit is 80c
- */
-const static struct ec_thermal_config thermal_inductor = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(55),
-};
-
-
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_CHARGER]			= thermal_inductor,
-	[TEMP_SENSOR_2_PP3300_REGULATOR]	= thermal_inductor,
-	[TEMP_SENSOR_3_DDR_SOC]			= thermal_cpu,
-	[TEMP_SENSOR_4_FAN]			= thermal_cpu,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-/******************************************************************************/
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {
-		.module = NPCX_MFT_MODULE_1,
-		.clk_src = TCKC_LFCLK,
-		.pwm_id = PWM_CH_FAN,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-/******************************************************************************/
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C0_SENSOR_SCL,
-		.sda = GPIO_EC_I2C0_SENSOR_SDA,
-	},
-	{
-		.name = "usb_c0",
-		.port = I2C_PORT_USB_C0,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C1_USB_C0_SCL,
-		.sda = GPIO_EC_I2C1_USB_C0_SDA,
-	},
-	{
-		.name = "usb_c1",
-		.port = I2C_PORT_USB_C1,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C2_USB_C1_SCL,
-		.sda = GPIO_EC_I2C2_USB_C1_SDA,
-	},
-	{
-		.name = "usb_1_mix",
-		.port = I2C_PORT_USB_1_MIX,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C3_USB_1_MIX_SCL,
-		.sda = GPIO_EC_I2C3_USB_1_MIX_SDA,
-	},
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C5_POWER_SCL,
-		.sda = GPIO_EC_I2C5_POWER_SDA,
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C7_EEPROM_SCL,
-		.sda = GPIO_EC_I2C7_EEPROM_SDA,
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/******************************************************************************/
-/* PWM configuration */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED4_SIDESEL] = {
-		.channel = 7,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		/* Run at a higher frequency than the color PWM signals to avoid
-		 * timing-based color shifts.
-		 */
-		.freq = 4800,
-	},
-	[PWM_CH_FAN] = {
-		.channel = 5,
-		.flags = PWM_CONFIG_OPEN_DRAIN,
-		.freq = 25000
-	},
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = 0,
-		/*
-		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
-		 * flicker. Higher frequencies consume similar average power to
-		 * lower PWM frequencies, but higher frequencies record a much
-		 * lower maximum power.
-		 */
-		.freq = 2400,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-void board_reset_pd_mcu(void)
-{
-	/* TODO(b/159024035): Malefor: check USB PD reset operation */
-}
-
-__override void board_cbi_init(void)
-{
-	/* TODO(b/159024035): Malefor: check FW_CONFIG fields for USB DB type */
-}
-
-/******************************************************************************/
-/* USBC PPC configuration */
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/******************************************************************************/
-/* PPC support routines */
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		sn5s330_interrupt(USBC_PORT_C0);
-		break;
-	case GPIO_USB_C1_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C1);
-	default:
-		break;
-	}
-}
-
-/******************************************************************************/
-/* BC1.2 charger detect configuration */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC TCPC configuration */
-struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
-		},
-		.drv = &tusb422_tcpm_drv,
-		.usb23 = USBC_PORT_0_USB2_NUM | (USBC_PORT_0_USB3_NUM << 4),
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C1,
-			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
-		},
-		.drv = &tusb422_tcpm_drv,
-		.usb23 = USBC_PORT_1_USB2_NUM | (USBC_PORT_1_USB3_NUM << 4),
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC mux configuration - Tiger Lake includes internal mux */
-struct usb_mux usbc1_usb4_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &bb_usb_retimer,
-	.i2c_port = I2C_PORT_USB_1_MIX,
-	.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
-};
-struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc1_usb4_db_retimer,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-struct bb_usb_control bb_controls[] = {
-	[USBC_PORT_C0] = {
-		/* USB-C port 0 doesn't have a retimer */
-	},
-	[USBC_PORT_C1] = {
-		.usb_ls_en_gpio = GPIO_USB_C1_LS_EN,
-		.retimer_rst_gpio = GPIO_USB_C1_RT_RST_ODL,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(bb_controls) == USBC_PORT_COUNT);
-
-static void board_tcpc_init(void)
-{
-	/* Don't reset TCPCs after initial reset */
-	if (!system_jumped_late())
-		board_reset_pd_mcu();
-
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
-
-	/* Enable BC1.2 interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
-
-/******************************************************************************/
-/* TCPC support routines */
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	/*
-	 * Check which port has the ALERT line set
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_0;
-	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (port == USBC_PORT_C0)
-		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
-	else
-		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
-}
diff --git a/board/lingcod/board.h b/board/lingcod/board.h
deleted file mode 100644
index 230b40fd84..0000000000
--- a/board/lingcod/board.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Baseboard features */
-#include "baseboard.h"
-
-/* Optional features */
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
-
-#define CONFIG_POWER_BUTTON
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* LED defines */
-#define CONFIG_LED_POWER_LED
-#define CONFIG_LED_ONOFF_STATES
-
-/* Keyboard features */
-
-/* Sensors */
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-#define CONFIG_ACCEL_LIS2DE             /* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM        /* Base accel */
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
-	BIT(LID_ACCEL)
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
-
-/*
- * USB-C port's USB2 & USB3 mapping from schematics
- * USB2 numbering on PCH - 1 to n
- * USB3 numbering on AP - 0 to n (PMC's USB3 numbering for MUX
- * configuration is - 1 to n hence add +1)
- */
-#define USBC_PORT_0_USB2_NUM	9
-#define USBC_PORT_0_USB3_NUM	1
-#define USBC_PORT_1_USB2_NUM	4
-#define USBC_PORT_1_USB3_NUM	2
-
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
-
-/*
- * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
- * cables only support up to 60W.
- */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
-/* Enabling USB4 mode */
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x40
-
-/* USB Type A Features */
-
-/* USBC PPC*/
-#define CONFIG_USBC_PPC_SN5S330		/* USBC port C0 */
-#define CONFIG_USBC_PPC_SYV682X		/* USBC port C1 */
-
-/* BC 1.2 */
-
-/* Volume Button feature */
-
-/* Fan features */
-
-/* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SYS_PWROK		GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PG_EC_DSW_PWROK		GPIO_DSW_PWROK
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD		GPIO_PG_EC_RSMRST_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
-#define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE_L
-
-/* I2C Bus Configuration */
-#define CONFIG_I2C
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_1_MIX	NPCX_I2C_PORT3_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-#define CONFIG_I2C_MASTER
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum battery_type {
-	BATTERY_SMP,
-	BATTERY_LGC,
-	BATTERY_SUNWODA,
-	BATTERY_TYPE_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_LED4_SIDESEL = 0,
-	PWM_CH_FAN,
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT,
-};
-
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
-
-void board_reset_pd_mcu(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/lingcod/build.mk b/board/lingcod/build.mk
deleted file mode 100644
index 279b2e559e..0000000000
--- a/board/lingcod/build.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
-BASEBOARD:=volteer
-
-board-y=board.o
-board-y+=battery.o
-board-y+=led.o
diff --git a/board/lingcod/ec.tasklist b/board/lingcod/ec.tasklist
deleted file mode 100644
index 292de51cdb..0000000000
--- a/board/lingcod/ec.tasklist
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/lingcod/gpio.inc b/board/lingcod/gpio.inc
deleted file mode 100644
index 6144bba66f..0000000000
--- a/board/lingcod/gpio.inc
+++ /dev/null
@@ -1,159 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(EC_LID_OPEN,          PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(EC_WP_L,              PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(H1_EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
-GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_RSMRST_ODL,     PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(DSW_PWROK,            PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4),  GPIO_INT_BOTH, power_signal_interrupt)
-
-/* Sensor Interrupts */
-GPIO_INT(EC_IMU_INT_L,         PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, lsm6dsm_interrupt)
-GPIO_INT(TABLET_MODE_L,        PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(E, 0), GPIO_INT_BOTH, tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(A, 2), GPIO_INT_BOTH, tcpc_alert_event)
-
-GPIO_INT(USB_C0_PPC_INT_ODL,	PIN(6, 2), GPIO_INT_BOTH, ppc_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(F, 5), GPIO_INT_BOTH, ppc_interrupt)
-
-GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(E, 4), GPIO_INT_BOTH, bc12_interrupt)
-GPIO_INT(USB_C1_MIX_INT_ODL,	PIN(0, 3), GPIO_INT_BOTH, bc12_interrupt)
-
-/* HDMI interrupts */
-
-/* Volume button interrupts */
-GPIO_INT(EC_VOLDN_BTN_ODL,		PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL,		PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-
-/* Power Sequencing Signals */
-GPIO(EN_PP3300_A,              PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_PPVAR_VCCIN,           PIN(4, 3), GPIO_OUT_LOW) /* Enables VCCIN IMPV9 */
-/* The EC does not buffer this signal on Volteer. */
-UNIMPLEMENTED(PCH_DSW_PWROK)
-
-/* Other wake sources */
-/*
- * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an
- * interrupt handler because it is automatically handled by the PSL.
- *
- * We need to lock the setting so this gpio can't be reconfigured to overdrive
- * the real reset signal. (This is the PSL input pin not the real reset pin).
- */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH |
-					   GPIO_HIB_WAKE_HIGH |
-					   GPIO_LOCKED)
-
-/* AP/PCH Signals */
-GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
-GPIO(EC_PCH_RSMRST_ODL,        PIN(A, 6), GPIO_ODR_LOW) /* TODO - b/140950085 - implement TGL sequencing requirement */
-GPIO(EC_PCH_PWR_BTN_ODL,       PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
-GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
-UNIMPLEMENTED(EC_PROCHOT_IN_L)
-GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
-
-GPIO(EC_PCH_INT_ODL,           PIN(B, 0), GPIO_ODR_HIGH)
-
-/* USB and USBC Signals */
-GPIO(USB_C1_RT_RST_ODL,			PIN(8, 3), GPIO_ODR_LOW) /* USB_C1 Reset on boards board ID >=1 */
-GPIO(USB_C0_OC_ODL,			PIN(B, 1), GPIO_ODR_HIGH)
-GPIO(USB_C1_OC_ODL,			PIN(5, 0), GPIO_ODR_HIGH)
-
-/* Don't have a load switch for retimer */
-UNIMPLEMENTED(USB_C1_LS_EN)
-
-/* Misc Signals */
-
-/*
- * eDP backlight - both PCH and EC have enable pins that must be high
- * for the backlight to turn on. Default state is high, and can be turned
- * off during sleep states.
- */
-GPIO(EC_EDP_BL_EN,             PIN(D, 3), GPIO_OUT_HIGH)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(EC_I2C0_SENSOR_SCL,       PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C0_SENSOR_SDA,       PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C1_USB_C0_SCL,       PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C1_USB_C0_SDA,       PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SCL,       PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SDA,       PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C3_USB_1_MIX_SCL,    PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C3_USB_1_MIX_SDA,    PIN(D, 0), GPIO_INPUT)
-GPIO(EC_I2C5_POWER_SCL,        PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C5_POWER_SDA,        PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_SCL,       PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_SDA,       PIN(B, 2), GPIO_INPUT)
-
-/* Battery signals */
-GPIO(EC_BATT_PRES_ODL, 		PIN(E, 1), GPIO_INPUT)
-
-/* Physical HPD pins are not needed on EC as these are configured by PMC */
-GPIO(USB_C0_DP_HPD,		PIN(F, 3), GPIO_INPUT)
-GPIO(USB_C1_DP_HPD,		PIN(7, 0), GPIO_INPUT)
-
-/* LED */
-GPIO(LED_1_L,	 PIN(C, 4), GPIO_OUT_HIGH)	/* Battery - Green LED */
-GPIO(LED_2_L,	 PIN(C, 3), GPIO_OUT_HIGH)	/* Battery - Red LED */
-GPIO(LED_3_L,	 PIN(C, 2), GPIO_OUT_HIGH)	/* Power - White LED */
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, BIT(5) | BIT(4)), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V)) /* I2C0 */
-ALTERNATE(PIN_MASK(9, BIT(0) | BIT(2) | BIT(1)), 0, MODULE_I2C, 0)                   /* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)                                     /* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, BIT(1) | BIT(0)), 0, MODULE_I2C, 0)                            /* I2C3 */
-ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)                            /* I2C5 */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)                            /* I2C7 */
-
-/* This selects between an LED module on the motherboard and one on the daughter
- * board, to be controlled by LED_{1,2,3}_L. PWM allows driving both modules at
- * the same time. */
-ALTERNATE(PIN_MASK(6, BIT(0)), 0, MODULE_PWM, 0)                                     /* LED_SIDESEL_4_L */
-
-/* Fan signals */
-GPIO(EN_PP5000_FAN,            PIN(6, 1), GPIO_OUT_LOW)
-ALTERNATE(PIN_MASK(B, BIT(7)), 0, MODULE_PWM, 0)	/* FAN_PWM */
-ALTERNATE(PIN_MASK(4, BIT(0)), 0, MODULE_PWM, 0)	/* FAN_SPEED_TACH */
-
-/* Keyboard pins */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_00-01 */
-GPIO(EC_KSO_02_INV, PIN(1, 7),                        GPIO_OUT_LOW)  /* KSO_02 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_14 */
-ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)                     /* EC_KB_BL_PWM */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, BIT(5) | BIT(4)), 0, MODULE_UART, 0)                           /* UART from EC to Servo */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)                    /* GPIOD2 = EC_LID_OPEN */
-ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)  /* GPIO00 = ACOK_OD,
-                                                                       GPIO01 = H1_EC_PWR_BTN_ODL
-                                                                       GPIO02 = EC_RST_ODL */
-
diff --git a/board/lingcod/led.c b/board/lingcod/led.c
deleted file mode 100644
index 6f4e781404..0000000000
--- a/board/lingcod/led.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Malefor
- */
-
-#include "common.h"
-#include "led_onoff_states.h"
-#include "led_common.h"
-#include "gpio.h"
-
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
-
-const int led_charge_lvl_1 = 5;
-
-const int led_charge_lvl_2 = 97;
-
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED,   LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,   1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
-
-const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]            = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]    = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-					 {LED_OFF,         0.5 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF,            LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF,            LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-void led_set_color_power(enum ec_led_colors color)
-{
-	if (color == EC_LED_COLOR_WHITE)
-		gpio_set_level(GPIO_LED_3_L, LED_ON_LVL);
-	else
-		/* LED_OFF and unsupported colors */
-		gpio_set_level(GPIO_LED_3_L, LED_OFF_LVL);
-}
-
-void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_RED:
-		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_LED_1_L, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_GREEN:
-		gpio_set_level(GPIO_LED_1_L, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_RED] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_GREEN] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_RED] != 0)
-			led_set_color_battery(EC_LED_COLOR_RED);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if (brightness[EC_LED_COLOR_GREEN] != 0)
-			led_set_color_battery(EC_LED_COLOR_GREEN);
-		else
-			led_set_color_battery(LED_OFF);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
diff --git a/board/lisbon/board.c b/board/lisbon/board.c
new file mode 100644
index 0000000000..898d85a9d0
--- /dev/null
+++ b/board/lisbon/board.c
@@ -0,0 +1,534 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "adc.h"
+#include "builtin/assert.h"
+#include "button.h"
+#include "cec.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "driver/cec/bitbang.h"
+#include "driver/tcpm/tcpci.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "power.h"
+#include "power_button.h"
+#include "switch.h"
+#include "throttle_ap.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+#include <stdbool.h>
+
+/* Console output macros */
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+
+static void power_monitor(void);
+DECLARE_DEFERRED(power_monitor);
+
+/******************************************************************************/
+/* USB-A charging control */
+
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_PP5000_USBA,
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
+
+/******************************************************************************/
+
+/* CEC ports */
+const struct cec_config_t cec_config[] = {
+	[CEC_PORT_0] = {
+		.drv = &bitbang_cec_drv,
+		.offline_policy = NULL,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(cec_config) == CEC_PORT_COUNT);
+
+int board_set_active_charge_port(int port)
+{
+	CPRINTS("Requested charge port change to %d", port);
+
+	/*
+	 * The charge manager may ask us to switch to no charger if we're
+	 * running off USB-C only but upstream doesn't support PD. It requires
+	 * that we accept this switch otherwise it triggers an assert and EC
+	 * reset; it's not possible to boot the AP anyway, but we want to avoid
+	 * resetting the EC so we can continue to do the "low power" LED blink.
+	 */
+	if (port == CHARGE_PORT_NONE)
+		return EC_SUCCESS;
+
+	if (port < 0 || CHARGE_PORT_COUNT <= port)
+		return EC_ERROR_INVAL;
+
+	if (port == charge_manager_get_active_charge_port())
+		return EC_SUCCESS;
+
+	/* Don't charge from a source port */
+	if (board_vbus_source_enabled(port))
+		return EC_ERROR_INVAL;
+
+	if (!chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
+		int bj_active, bj_requested;
+
+		if (charge_manager_get_active_charge_port() != CHARGE_PORT_NONE)
+			/* Change is only permitted while the system is off */
+			return EC_ERROR_INVAL;
+
+		/*
+		 * Current setting is no charge port but the AP is on, so the
+		 * charge manager is out of sync (probably because we're
+		 * reinitializing after sysjump). Reject requests that aren't
+		 * in sync with our outputs.
+		 */
+		bj_active = !gpio_get_level(GPIO_EN_PPVAR_BJ_ADP_L);
+		bj_requested = port == CHARGE_PORT_BARRELJACK;
+		if (bj_active != bj_requested)
+			return EC_ERROR_INVAL;
+	}
+
+	CPRINTS("New charger p%d", port);
+
+	switch (port) {
+	case CHARGE_PORT_TYPEC0:
+		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 1);
+		break;
+	case CHARGE_PORT_BARRELJACK:
+		/* Make sure BJ adapter is sourcing power */
+		if (gpio_get_level(GPIO_BJ_ADP_PRESENT_ODL))
+			return EC_ERROR_INVAL;
+		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 0);
+		break;
+	default:
+		return EC_ERROR_INVAL;
+	}
+
+	return EC_SUCCESS;
+}
+
+static uint8_t usbc_overcurrent;
+static int32_t base_5v_power_s5;
+static int32_t base_5v_power_z1;
+
+/*
+ * Power usage for each port as measured or estimated.
+ * Units are milliwatts (5v x ma current)
+ */
+
+/* PP5000_S5 loads */
+#define PWR_S5_BASE_LOAD (5 * 1431)
+#define PWR_S5_FRONT_HIGH (5 * 1737)
+#define PWR_S5_FRONT_LOW (5 * 1055)
+#define PWR_S5_REAR_HIGH (5 * 1737)
+#define PWR_S5_REAR_LOW (5 * 1055)
+#define PWR_S5_HDMI (5 * 580)
+#define PWR_S5_MAX (5 * 10000)
+#define FRONT_DELTA (PWR_S5_FRONT_HIGH - PWR_S5_FRONT_LOW)
+#define REAR_DELTA (PWR_S5_REAR_HIGH - PWR_S5_REAR_LOW)
+
+/* PP5000_Z1 loads */
+#define PWR_Z1_BASE_LOAD (5 * 5)
+#define PWR_Z1_C_HIGH (5 * 3600)
+#define PWR_Z1_C_LOW (5 * 2000)
+#define PWR_Z1_MAX (5 * 9000)
+/*
+ * Update the 5V power usage, assuming no throttling,
+ * and invoke the power monitoring.
+ */
+static void update_5v_usage(void)
+{
+	int front_ports = 0;
+	int rear_ports = 0;
+
+	/*
+	 * Recalculate the 5V load, assuming no throttling.
+	 */
+	base_5v_power_s5 = PWR_S5_BASE_LOAD;
+	if (!gpio_get_level(GPIO_USB_A0_OC_ODL)) {
+		front_ports++;
+		base_5v_power_s5 += PWR_S5_FRONT_LOW;
+	}
+	if (!gpio_get_level(GPIO_USB_A1_OC_ODL)) {
+		front_ports++;
+		base_5v_power_s5 += PWR_S5_FRONT_LOW;
+	}
+	/*
+	 * Only 1 front port can run higher power at a time.
+	 */
+	if (front_ports > 0)
+		base_5v_power_s5 += PWR_S5_FRONT_HIGH - PWR_S5_FRONT_LOW;
+
+	if (!gpio_get_level(GPIO_USB_A2_OC_ODL)) {
+		rear_ports++;
+		base_5v_power_s5 += PWR_S5_REAR_LOW;
+	}
+	if (!gpio_get_level(GPIO_USB_A3_OC_ODL)) {
+		rear_ports++;
+		base_5v_power_s5 += PWR_S5_REAR_LOW;
+	}
+	/*
+	 * Only 1 rear port can run higher power at a time.
+	 */
+	if (rear_ports > 0)
+		base_5v_power_s5 += PWR_S5_REAR_HIGH - PWR_S5_REAR_LOW;
+	if (!gpio_get_level(GPIO_HDMIA_CONN_OC_ODL))
+		base_5v_power_s5 += PWR_S5_HDMI;
+	if (!gpio_get_level(GPIO_HDMIB_CONN_OC_ODL))
+		base_5v_power_s5 += PWR_S5_HDMI;
+	base_5v_power_z1 = PWR_Z1_BASE_LOAD;
+	if (usbc_overcurrent)
+		base_5v_power_z1 += PWR_Z1_C_HIGH;
+	/*
+	 * Invoke the power handler immediately.
+	 */
+	hook_call_deferred(&power_monitor_data, 0);
+}
+DECLARE_DEFERRED(update_5v_usage);
+/*
+ * Start power monitoring after ADCs have been initialised.
+ */
+DECLARE_HOOK(HOOK_INIT, update_5v_usage, HOOK_PRIO_INIT_ADC + 1);
+
+static void port_ocp_interrupt(enum gpio_signal signal)
+{
+	hook_call_deferred(&update_5v_usage_data, 0);
+}
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/******************************************************************************/
+/*
+ * Barrel jack power supply handling
+ *
+ * EN_PPVAR_BJ_ADP_L must default active to ensure we can power on when the
+ * barrel jack is connected, and the USB-C port can bring the EC up fine in
+ * dead-battery mode. Both the USB-C and barrel jack switches do reverse
+ * protection, so we're safe to turn one on then the other off- but we should
+ * only do that if the system is off since it might still brown out.
+ */
+
+#define ADP_DEBOUNCE_MS 1000 /* Debounce time for BJ plug/unplug */
+/* Debounced connection state of the barrel jack */
+static int8_t adp_connected = -1;
+static void adp_connect_deferred(void)
+{
+	struct charge_port_info pi = { 0 };
+	int connected = !gpio_get_level(GPIO_BJ_ADP_PRESENT_ODL);
+
+	/* Debounce */
+	if (connected == adp_connected)
+		return;
+	if (connected)
+		ec_bj_power(&pi.voltage, &pi.current);
+	charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED,
+				     DEDICATED_CHARGE_PORT, &pi);
+	adp_connected = connected;
+}
+DECLARE_DEFERRED(adp_connect_deferred);
+
+/* IRQ for BJ plug/unplug. It shouldn't be called if BJ is the power source. */
+void adp_connect_interrupt(enum gpio_signal signal)
+{
+	hook_call_deferred(&adp_connect_deferred_data, ADP_DEBOUNCE_MS * MSEC);
+}
+
+static void adp_state_init(void)
+{
+	ASSERT(CHARGE_PORT_ENUM_COUNT == CHARGE_PORT_COUNT);
+	/*
+	 * Initialize all charge suppliers to 0. The charge manager waits until
+	 * all ports have reported in before doing anything.
+	 */
+	for (int i = 0; i < CHARGE_PORT_COUNT; i++) {
+		for (int j = 0; j < CHARGE_SUPPLIER_COUNT; j++)
+			charge_manager_update_charge(j, i, NULL);
+	}
+
+	/* Report charge state from the barrel jack. */
+	adp_connect_deferred();
+}
+DECLARE_HOOK(HOOK_INIT, adp_state_init, HOOK_PRIO_INIT_CHARGE_MANAGER + 1);
+
+static void board_init(void)
+{
+	gpio_enable_interrupt(GPIO_BJ_ADP_PRESENT_ODL);
+	gpio_enable_interrupt(GPIO_HDMIA_CONN_OC_ODL);
+	gpio_enable_interrupt(GPIO_HDMIB_CONN_OC_ODL);
+	gpio_enable_interrupt(GPIO_USB_A0_OC_ODL);
+	gpio_enable_interrupt(GPIO_USB_A1_OC_ODL);
+	gpio_enable_interrupt(GPIO_USB_A2_OC_ODL);
+	gpio_enable_interrupt(GPIO_USB_A3_OC_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+void board_overcurrent_event(int port, int is_overcurrented)
+{
+	/* Check that port number is valid. */
+	if ((port < 0) || (port >= CONFIG_USB_PD_PORT_MAX_COUNT))
+		return;
+	usbc_overcurrent = is_overcurrented;
+	update_5v_usage();
+}
+/*
+ * Power monitoring and management.
+ *
+ * the power budgets are met without letting the system fall into
+ * power deficit (perhaps causing a brownout).
+ *
+ * There are 2 power budgets that need to be managed:
+ * The overall goal is to gracefully manage the power demand so that
+ *  - overall system power as measured on the main power supply rail.
+ *  - 5V power delivered to the USB and HDMI ports.
+ *
+ * The actual system power demand is calculated from the VBUS voltage and
+ * the input current (read from a shunt), averaged over 5 readings.
+ * The power budget limit is from the charge manager.
+ *
+ * The 5V power cannot be read directly. Instead, we rely on overcurrent
+ * inputs from the USB and HDMI ports to indicate that the port is in use
+ * (and drawing maximum power).
+ *
+ * There are 3 throttles that can be applied (in priority order):
+ *
+ *  - Type A BC1.2 front port restriction (3W)
+ *  - Type A BC1.2 rear port restriction (3W)
+ *  - Type C PD (throttle to 1.5A if sourcing)
+ *  - Turn on PROCHOT, which immediately throttles the CPU.
+ *
+ *  The first 3 throttles affect both the system power and the 5V rails.
+ *  The third is a last resort to force an immediate CPU throttle to
+ *  reduce the overall power use.
+ *
+ *  The strategy is to determine what the state of the throttles should be,
+ *  and to then turn throttles off or on as needed to match this.
+ *
+ *  This function runs on demand, or every 2 ms when the CPU is up,
+ *  and continually monitors the power usage, applying the
+ *  throttles when necessary.
+ *
+ *  All measurements are in milliwatts.
+ */
+#define THROT_TYPE_A_FRONT BIT(0)
+#define THROT_TYPE_A_REAR BIT(1)
+#define THROT_TYPE_C0 BIT(2)
+#define THROT_PROCHOT BIT(5)
+
+/*
+ * Power gain if front USB A ports are limited.
+ */
+#define POWER_GAIN_TYPE_A 3200
+/*
+ * Power gain if Type C port is limited.
+ */
+#define POWER_GAIN_TYPE_C 8800
+/*
+ * Power is averaged over 10 ms, with a reading every 2 ms.
+ */
+#define POWER_DELAY_MS 2
+#define POWER_READINGS (10 / POWER_DELAY_MS)
+
+static void power_monitor(void)
+{
+	static uint32_t current_state;
+	static uint32_t history[POWER_READINGS];
+	static uint8_t index;
+	int32_t delay;
+	uint32_t new_state = 0, diff;
+	int32_t headroom_5v_s5 = PWR_S5_MAX - base_5v_power_s5;
+	int32_t headroom_5v_z1 = PWR_Z1_MAX - base_5v_power_z1;
+
+	/*
+	 * If CPU is off or suspended, no need to throttle
+	 * or restrict power.
+	 */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF | CHIPSET_STATE_SUSPEND)) {
+		/*
+		 * Slow down monitoring, assume no throttling required.
+		 */
+		delay = 20 * MSEC;
+		/*
+		 * Clear the first entry of the power table so that
+		 * it is re-initilalised when the CPU starts.
+		 */
+		history[0] = 0;
+	} else {
+		int32_t charger_mw;
+
+		delay = POWER_DELAY_MS * MSEC;
+		/*
+		 * Get current charger limit (in mw).
+		 * If not configured yet, skip.
+		 */
+		charger_mw = charge_manager_get_power_limit_uw() / 1000;
+		if (charger_mw != 0) {
+			int32_t gap, total, max, power;
+			int i;
+
+			/*
+			 * Read power usage.
+			 */
+			power = (adc_read_channel(ADC_VBUS) *
+				 adc_read_channel(ADC_PPVAR_IMON)) /
+				1000;
+			/* Init power table */
+			if (history[0] == 0) {
+				for (i = 0; i < POWER_READINGS; i++)
+					history[i] = power;
+			}
+			/*
+			 * Update the power readings and
+			 * calculate the average and max.
+			 */
+			history[index] = power;
+			index = (index + 1) % POWER_READINGS;
+			total = 0;
+			max = history[0];
+			for (i = 0; i < POWER_READINGS; i++) {
+				total += history[i];
+				if (history[i] > max)
+					max = history[i];
+			}
+			/*
+			 * For Type-C power supplies, there is
+			 * less tolerance for exceeding the rating,
+			 * so use the max power that has been measured
+			 * over the measuring period.
+			 * For barrel-jack supplies, the rating can be
+			 * exceeded briefly, so use the average.
+			 */
+			if (charge_manager_get_supplier() == CHARGE_SUPPLIER_PD)
+				power = max;
+			else
+				power = total / POWER_READINGS;
+			/*
+			 * Calculate gap, and if negative, power
+			 * demand is exceeding configured power budget, so
+			 * throttling is required to reduce the demand.
+			 */
+			gap = charger_mw - power;
+			/*
+			 * Limiting type-A power rear ports.
+			 */
+			if (gap <= 0) {
+				new_state |= THROT_TYPE_A_REAR;
+				headroom_5v_s5 += REAR_DELTA;
+				if (!(current_state & THROT_TYPE_A_REAR))
+					gap += POWER_GAIN_TYPE_A;
+			}
+			/*
+			 * Limiting type-A power front ports.
+			 */
+			if (gap <= 0) {
+				new_state |= THROT_TYPE_A_FRONT;
+				headroom_5v_s5 += FRONT_DELTA;
+				if (!(current_state & THROT_TYPE_A_REAR))
+					gap += POWER_GAIN_TYPE_A;
+			}
+			/*
+			 * If the type-C port is sourcing power,
+			 * check whether it should be throttled.
+			 */
+			if (ppc_is_sourcing_vbus(0) && gap <= 0) {
+				new_state |= THROT_TYPE_C0;
+				headroom_5v_z1 += PWR_Z1_C_HIGH - PWR_Z1_C_LOW;
+				if (!(current_state & THROT_TYPE_C0))
+					gap += POWER_GAIN_TYPE_C;
+			}
+			/*
+			 * As a last resort, turn on PROCHOT to
+			 * throttle the CPU.
+			 */
+			if (gap <= 0)
+				new_state |= THROT_PROCHOT;
+		}
+	}
+	/*
+	 * Check the 5v power usage and if necessary,
+	 * adjust the throttles in priority order.
+	 *
+	 * Either throttle may have already been activated by
+	 * the overall power control.
+	 *
+	 * We rely on the overcurrent detection to inform us
+	 * if the port is in use.
+	 *
+	 *  - If type C not already throttled:
+	 *	* If not overcurrent, prefer to limit type C [1].
+	 *	* If in overcurrentuse:
+	 *		- limit type A first [2]
+	 *		- If necessary, limit type C [3].
+	 *  - If type A not throttled, if necessary limit it [2].
+	 */
+	if (headroom_5v_z1 < 0) {
+		/*
+		 * Check whether type C is not throttled,
+		 * and is not overcurrent.
+		 */
+		if (!((new_state & THROT_TYPE_C0) || usbc_overcurrent)) {
+			/*
+			 * [1] Type C not in overcurrent, throttle it.
+			 */
+			headroom_5v_z1 += PWR_Z1_C_HIGH - PWR_Z1_C_LOW;
+			new_state |= THROT_TYPE_C0;
+		}
+		/*
+		 * [2] If still under-budget, limit type C.
+		 * No need to check if it is already throttled or not.
+		 */
+		if (headroom_5v_z1 < 0)
+			new_state |= THROT_TYPE_C0;
+	}
+	if (headroom_5v_s5 < 0) {
+		/*
+		 * [1] If type A rear not already throttled, and power still
+		 * needed, limit type A rear.
+		 */
+		if (!(new_state & THROT_TYPE_A_REAR) && headroom_5v_s5 < 0) {
+			headroom_5v_s5 += PWR_S5_REAR_HIGH - PWR_S5_REAR_LOW;
+			new_state |= THROT_TYPE_A_REAR;
+		}
+		/*
+		 * [2] If type A front not already throttled, and power still
+		 * needed, limit type A front.
+		 */
+		if (!(new_state & THROT_TYPE_A_FRONT) && headroom_5v_s5 < 0) {
+			headroom_5v_s5 += PWR_S5_FRONT_HIGH - PWR_S5_FRONT_LOW;
+			new_state |= THROT_TYPE_A_FRONT;
+		}
+	}
+	/*
+	 * Turn the throttles on or off if they have changed.
+	 */
+	diff = new_state ^ current_state;
+	current_state = new_state;
+	if (diff & THROT_PROCHOT) {
+		int prochot = (new_state & THROT_PROCHOT) ? 0 : 1;
+
+		gpio_set_level(GPIO_EC_PROCHOT_ODL, prochot);
+	}
+	if (diff & THROT_TYPE_C0) {
+		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C0) ?
+						TYPEC_RP_1A5 :
+						TYPEC_RP_3A0;
+
+		ppc_set_vbus_source_current_limit(0, rp);
+		tcpm_select_rp_value(0, rp);
+		pd_update_contract(0);
+	}
+	if (diff & THROT_TYPE_A_REAR) {
+		int typea_bc = (new_state & THROT_TYPE_A_REAR) ? 1 : 0;
+
+		gpio_set_level(GPIO_USB_A_LOW_PWR0_OD, typea_bc);
+		gpio_set_level(GPIO_USB_A_LOW_PWR1_OD, typea_bc);
+	}
+	hook_call_deferred(&power_monitor_data, delay);
+}
diff --git a/board/lisbon/board.h b/board/lisbon/board.h
new file mode 100644
index 0000000000..804a3a4ce7
--- /dev/null
+++ b/board/lisbon/board.h
@@ -0,0 +1,163 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Lisbon board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "compile_time_macros.h"
+
+/* Baseboard features */
+#include "baseboard.h"
+
+/* Barrel Jack */
+#define DEDICATED_CHARGE_PORT 1
+
+/* HDMI CEC */
+#define CONFIG_CEC
+#define CONFIG_CEC_BITBANG
+#define CEC_GPIO_OUT GPIO_HDMIB_CEC_OUT
+#define CEC_GPIO_IN GPIO_HDMIB_CEC_IN
+#define CEC_GPIO_PULL_UP GPIO_HDMIB_CEC_PULL_UP
+
+/* USB Type A Features */
+#define USB_PORT_COUNT 4
+#define CONFIG_USB_PORT_POWER_DUMB
+#define CONFIG_USBC_RETIMER_PS8811
+
+/* USB Type C and USB PD defines */
+#define CONFIG_USB_PD_PPC
+#define CONFIG_USB_PD_TCPM_RT1715
+#define CONFIG_USBC_RETIMER_PS8818
+#define CONFIG_USBC_PPC_SYV682X
+#undef CONFIG_SYV682X_HV_ILIM
+#define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_5_50
+
+/* TODO: b/177608416 - measure and check these values on brya */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
+
+/* The design should support up to 100W. */
+/* TODO(b/197702356): Set the max PD to 60W now and change it
+ * to 100W after we verify it.
+ */
+#define PD_OPERATING_POWER_MW CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
+#define PD_MAX_POWER_MW 100000
+#define PD_MAX_CURRENT_MA 5000
+#define PD_MAX_VOLTAGE_MV 20000
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
+
+/*
+ * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
+ * signal.
+ */
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
+#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_OD
+#define GPIO_RECOVERY_L_2 GPIO_GSC_EC_RECOVERY_BTN_OD
+
+/* I2C Bus Configuration */
+#define I2C_PORT_USB_C0_TCPC NPCX_I2C_PORT1_0
+
+#define I2C_PORT_USB_C0_PPC_BC12 NPCX_I2C_PORT2_0
+
+#define I2C_PORT_USB_C0_MUX NPCX_I2C_PORT3_0
+
+#define I2C_PORT_USB_A2_A3_RT NPCX_I2C_PORT6_1
+
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+
+/* Thermal features */
+#define CONFIG_THERMISTOR
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_TEMP_SENSOR_POWER
+#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
+
+/* ADC */
+#define CONFIG_ADC
+
+/*
+ * TODO(b/197478860): Enable the fan control. We need
+ * to check the sensor value and adjust the fan speed.
+ */
+#define CONFIG_FANS FAN_CH_COUNT
+
+/* Include math_util for bitmask_uint64 used in pd_timers */
+#define CONFIG_MATH_UTIL
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h" /* needed by registers.h */
+#include "registers.h"
+#include "usbc_config.h"
+
+enum charge_port {
+	CHARGE_PORT_TYPEC0,
+	CHARGE_PORT_BARRELJACK,
+	CHARGE_PORT_ENUM_COUNT
+};
+
+enum adc_channel {
+	ADC_TEMP_SENSOR_1_CPU,
+	ADC_TEMP_SENSOR_2_CPU_VR,
+	ADC_TEMP_SENSOR_3_WIFI,
+	ADC_TEMP_SENSOR_4_DIMM,
+	ADC_VBUS,
+	ADC_PPVAR_IMON, /* ADC3 */
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1_CPU,
+	TEMP_SENSOR_2_CPU_VR,
+	TEMP_SENSOR_3_WIFI,
+	TEMP_SENSOR_4_DIMM,
+	TEMP_SENSOR_COUNT
+};
+
+enum pwm_channel {
+	PWM_CH_LED_GREEN, /* PWM0 */
+	PWM_CH_FAN, /* PWM5 */
+	PWM_CH_LED_RED, /* PWM2 */
+	PWM_CH_COUNT
+};
+
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT };
+
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT };
+
+enum cec_port { CEC_PORT_0, CEC_PORT_COUNT };
+
+extern void adp_connect_interrupt(enum gpio_signal signal);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/lisbon/build.mk b/board/lisbon/build.mk
new file mode 100644
index 0000000000..ef82fc1347
--- /dev/null
+++ b/board/lisbon/build.mk
@@ -0,0 +1,22 @@
+# -*- makefile -*-
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Lisbon board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx9
+CHIP_VARIANT:=npcx9m3f
+BASEBOARD:=brask
+
+board-y=
+board-y+=board.o
+board-y+=fans.o
+board-y+=fw_config.o
+board-y+=i2c.o
+board-y+=led.o
+board-y+=pwm.o
+board-y+=sensors.o
+board-y+=usbc_config.o
diff --git a/board/lisbon/ec.tasklist b/board/lisbon/ec.tasklist
new file mode 100644
index 0000000000..072252f0cd
--- /dev/null
+++ b/board/lisbon/ec.tasklist
@@ -0,0 +1,23 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ *
+ * USB_CHG_Px tasks must be contiguous (see USB_CHG_PORT_TO_TASK_ID(x)).
+ * PD_Cx tasks must be contiguous (see PD_PORT_TO_TASK_ID(x))
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CEC, cec_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/lisbon/fans.c b/board/lisbon/fans.c
new file mode 100644
index 0000000000..2bf4c43912
--- /dev/null
+++ b/board/lisbon/fans.c
@@ -0,0 +1,50 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Physical fans. These are logically separate from pwm_channels. */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "fan.h"
+#include "fan_chip.h"
+#include "hooks.h"
+#include "pwm.h"
+
+/* MFT channels. These are logically separate from pwm_channels. */
+const struct mft_t mft_channels[] = {
+	[MFT_CH_0] = {
+		.module = NPCX_MFT_MODULE_2,
+		.clk_src = TCKC_LFCLK,
+		.pwm_id = PWM_CH_FAN,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
+
+static const struct fan_conf fan_conf_0 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
+	.pgood_gpio = -1,
+	.enable_gpio = GPIO_EN_PP5000_FAN,
+};
+
+/*
+ * TOOD(b/197478860): need to update for real fan
+ *
+ * Prototype fan spins at about 7200 RPM at 100% PWM.
+ * Set minimum at around 30% PWM.
+ */
+static const struct fan_rpm fan_rpm_0 = {
+	.rpm_min = 2000,
+	.rpm_start = 2000,
+	.rpm_max = 4700,
+};
+
+const struct fan_t fans[FAN_CH_COUNT] = {
+	[FAN_CH_0] = {
+		.conf = &fan_conf_0,
+		.rpm = &fan_rpm_0,
+	},
+};
diff --git a/board/lisbon/fw_config.c b/board/lisbon/fw_config.c
new file mode 100644
index 0000000000..0de818c18f
--- /dev/null
+++ b/board/lisbon/fw_config.c
@@ -0,0 +1,66 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "fw_config.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+static union lisbon_cbi_fw_config fw_config;
+BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
+
+/*
+ * FW_CONFIG defaults for lisbon if the CBI.FW_CONFIG data is not
+ * initialized.
+ */
+static const union lisbon_cbi_fw_config fw_config_defaults = {
+	.bj_power = BJ_65W,
+	.storage = EMMC,
+	.fvm_support = FVM_NO,
+};
+
+/*
+ * Barrel-jack power adapter ratings.
+ */
+static const struct {
+	int voltage;
+	int current;
+} bj_power[] = {
+	[BJ_65W] = { /* 0 - 65W (also default) */
+			.voltage = 19000,
+			.current = 3420
+	},
+	[BJ_90W] = { /* 1 - 90W */
+			.voltage = 19000,
+			.current = 4740
+	}
+};
+
+/****************************************************************************
+ * Lisbon FW_CONFIG access
+ */
+void board_init_fw_config(void)
+{
+	if (cbi_get_fw_config(&fw_config.raw_value)) {
+		CPRINTS("CBI: Read FW_CONFIG failed, using board defaults");
+		fw_config = fw_config_defaults;
+	}
+}
+
+void ec_bj_power(uint32_t *voltage, uint32_t *current)
+{
+	unsigned int bj;
+
+	bj = fw_config.bj_power;
+	/* Out of range value defaults to 0 */
+	if (bj >= ARRAY_SIZE(bj_power))
+		bj = 0;
+	*voltage = bj_power[bj].voltage;
+	*current = bj_power[bj].current;
+}
diff --git a/board/lisbon/fw_config.h b/board/lisbon/fw_config.h
new file mode 100644
index 0000000000..e9cd6bd338
--- /dev/null
+++ b/board/lisbon/fw_config.h
@@ -0,0 +1,44 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __BOARD_LISBON_FW_CONFIG_H_
+#define __BOARD_LISBON_FW_CONFIG_H_
+
+#include <stdint.h>
+
+/****************************************************************************
+ * CBI FW_CONFIG layout for Lisbon board.
+ *
+ * Source of truth is the project/brask/lisbon/config.star configuration file.
+ */
+enum ec_cfg_bj_power { BJ_65W = 0, BJ_90W = 1 };
+
+enum ec_cfg_storage { EMMC = 0, SSD = 1 };
+
+enum ec_cfg_fvm_support { FVM_NO = 0, FVM_YES = 1 };
+
+union lisbon_cbi_fw_config {
+	struct {
+		uint32_t bj_power : 1;
+		uint32_t storage : 1;
+		uint32_t fvm_support : 1;
+		uint32_t reserved_1 : 29;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Read the cached FW_CONFIG.  Guaranteed to have valid values.
+ *
+ * @return the FW_CONFIG for the board.
+ */
+union lisbon_cbi_fw_config get_fw_config(void);
+
+/**
+ * Get the barrel-jack power from FW_CONFIG.
+ */
+void ec_bj_power(uint32_t *voltage, uint32_t *current);
+
+#endif /* __BOARD_LISBON_FW_CONFIG_H_ */
diff --git a/board/lisbon/gpio.inc b/board/lisbon/gpio.inc
new file mode 100644
index 0000000000..958b36c619
--- /dev/null
+++ b/board/lisbon/gpio.inc
@@ -0,0 +1,162 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* INTERRUPT GPIOs: */
+
+GPIO_INT(ACOK_OD,                    PIN(0, 0), GPIO_INT_BOTH, extpower_interrupt)
+GPIO_INT(EC_PROCHOT_IN_L,            PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
+GPIO_INT(EC_WP_ODL,                  PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(GSC_EC_PWR_BTN_ODL,         PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
+GPIO_INT(SEQ_EC_ALL_SYS_PG,          PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_DSW_PWROK,           PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_RSMRST_ODL,          PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,                   PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,                  PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SYS_SLP_S0IX_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(USB_C0_BC12_INT_ODL,        PIN(C, 6), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C0_C2_TCPC_INT_ODL,     PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C0_PPC_INT_ODL,         PIN(6, 2), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(BJ_ADP_PRESENT_ODL,         PIN(8, 2), GPIO_INT_BOTH | GPIO_PULL_UP, adp_connect_interrupt)
+GPIO_INT(EC_RECOVERY_BTN_OD,         PIN(2, 3), GPIO_INT_BOTH, button_interrupt)
+GPIO_INT(HDMIA_CONN_OC_ODL,          PIN(5, 0), GPIO_INPUT | GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(HDMIB_CONN_OC_ODL,          PIN(2, 4), GPIO_INPUT | GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(USB_A0_OC_ODL,              PIN(3, 1), GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(USB_A1_OC_ODL,              PIN(3, 0), GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(USB_A2_OC_ODL,              PIN(2, 7), GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(USB_A3_OC_ODL,              PIN(2, 6), GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH, port_ocp_interrupt)
+
+/* CCD */
+GPIO(CCD_MODE_ODL,                   PIN(E, 5), GPIO_INPUT)
+
+/* Security */
+GPIO(EC_ENTERING_RW,                 PIN(0, 3), GPIO_OUT_LOW)
+GPIO(EC_GSC_PACKET_MODE,             PIN(7, 5), GPIO_OUT_LOW)
+
+/* Fan */
+GPIO(EN_PP5000_FAN,                  PIN(6, 1), GPIO_OUT_HIGH)
+
+/* ADC, need to check the usage */
+GPIO(ANALOG_PPVAR_PWR_IN_IMON_EC,    PIN(4, 2), GPIO_INPUT)
+
+/* BarrelJack */
+GPIO(EN_PPVAR_BJ_ADP_L,              PIN(0, 7), GPIO_OUT_LOW)
+
+/* Chipset PCH */
+GPIO(EC_PCHHOT_ODL,                  PIN(7, 4), GPIO_INPUT)
+GPIO(EC_PCH_INT_ODL,                 PIN(B, 0), GPIO_ODR_HIGH)
+GPIO(EC_PCH_RSMRST_L,                PIN(A, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_RTCRST,                  PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_SYS_PWROK,               PIN(3, 7), GPIO_OUT_LOW)
+GPIO(EC_PCH_WAKE_ODL,                PIN(C, 0), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_ODL,                 PIN(6, 3), GPIO_ODR_HIGH)
+GPIO(EN_S5_RAILS,                    PIN(B, 6), GPIO_OUT_LOW)
+GPIO(PCH_PWROK,                      PIN(7, 2), GPIO_OUT_LOW)
+GPIO(SYS_RST_ODL,                    PIN(C, 5), GPIO_ODR_HIGH)
+GPIO(VCCST_PWRGD_OD,                 PIN(A, 4), GPIO_ODR_LOW)
+GPIO(IMVP9_VRRDY_OD,                 PIN(6, 0), GPIO_INPUT)
+GPIO(CPU_C10_GATE_L,                 PIN(6, 7), GPIO_INPUT)
+
+/* Button */
+GPIO(EC_PCH_PWR_BTN_ODL,             PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(GSC_EC_RECOVERY_BTN_OD,         PIN(2, 2), GPIO_INPUT)
+
+/* HDMI CEC */
+/* TODO(b/197474873): Enable HDMI CEC */
+GPIO(HDMIB_CEC_IN,                   PIN(4, 0), GPIO_INPUT)
+GPIO(HDMIB_CEC_OUT,                  PIN(D, 3), GPIO_OUT_HIGH | GPIO_OPEN_DRAIN)
+GPIO(HDMIB_CEC_PULL_UP,              PIN(C, 2), GPIO_OUT_HIGH)
+GPIO(HDMIA_CEC_IN,                   PIN(A, 7), GPIO_INPUT)
+GPIO(HDMIA_CEC_OUT,                  PIN(F, 2), GPIO_OUT_HIGH | GPIO_OPEN_DRAIN)
+GPIO(HDMIA_CEC_PULL_UP,              PIN(F, 3), GPIO_OUT_HIGH)
+
+/* I2C SCL/SDA */
+GPIO(EC_I2C_MISC_SCL_R,              PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SDA_R,              PIN(B, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_PPC_BC_SCL,    PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_PPC_BC_SDA,    PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_RT_SCL,        PIN(D, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_RT_SDA,        PIN(D, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_TCPC_SCL,      PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_TCPC_SDA,      PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_USB_A2_A3_SCL,           PIN(E, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_A2_A3_SDA,           PIN(E, 3), GPIO_INPUT)
+
+/* USBA */
+GPIO(EN_PP5000_USBA,                 PIN(D, 7), GPIO_OUT_LOW)
+GPIO(USB_A0_STATUS_L,                PIN(2, 1), GPIO_INPUT)
+GPIO(USB_A1_STATUS_L,                PIN(2, 0), GPIO_INPUT)
+GPIO(USB_A_LOW_PWR0_OD,              PIN(1, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(USB_A_LOW_PWR1_OD,              PIN(1, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(USB_A_OC_SOC_L,                 PIN(8, 0), GPIO_OUT_HIGH)
+
+/* LED */
+/* TODO(b/197471359): LED implementation */
+GPIO(LED_GREEN_L,                    PIN(C, 3), GPIO_OUT_LOW)
+GPIO(LED_RED_L,                      PIN(C, 4), GPIO_OUT_LOW)
+
+/* USBC */
+GPIO(USB_C0_FRS_EN,                  PIN(9, 4), GPIO_OUT_LOW)
+GPIO(USB_C0_HPD,                     PIN(0, 4), GPIO_OUT_LOW)
+GPIO(USB_C0_OC_ODL,                  PIN(7, 0), GPIO_OUT_LOW)
+
+/* UART alternate functions */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)              /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */
+
+/* I2C alternate functions */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)               /* GPIO87/I2C1_SDA0 */
+ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)               /* GPIO92/I2C2_SCL0, GPIO91/I2C2_SDA0, GPIO90/I2C1_SCL0 */
+ALTERNATE(PIN_MASK(B, 0x0c), 0, MODULE_I2C, 0)               /* GPIOB3/I2C7_SCL0/DCD_L, GPIOB2/I2C7_SDA0/DSR_L */
+ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)               /* GPIOD1/I2C3_SCL0, GPIOD0/I2C3_SDA0 */
+ALTERNATE(PIN_MASK(E, 0x18), 0, MODULE_I2C, 0)               /* GPIOE4/I2C6_SCL1/I3C_SCL, GPIOE3/I2C6_SDA1/I3C_SDA */
+
+/* PWM alternate functions */
+ALTERNATE(PIN_MASK(7, 0x08), 0, MODULE_PWM, 0)               /* GPIO73/TA2 */
+ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)               /* GPIOB7/PWM5 */
+ALTERNATE(PIN_MASK(C, 0x18), 0, MODULE_PWM, 0)               /* GPIOC4/PWM2, GPIOC3/PWM0 */
+
+/* ADC alternate functions */
+ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0)               /* GPIO34/PS2_DAT2/ADC6 */
+ALTERNATE(PIN_MASK(4, 0x38), 0, MODULE_ADC, 0)               /* GPIO45/ADC0, GPIO44/ADC1, GPIO43/ADC2 */
+ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0)               /* GPIOE1/ADC7 */
+
+/* NC pins, enable internal pull-down to avoid floating state. */
+GPIO(GPIO02_NC,                      PIN(0, 2), GPIO_INPUT | GPIO_PULL_DOWN)
+
+/* Unused Pins */
+UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
+UNUSED(PIN(3, 2))       /* GPO32/TRIS_L */
+UNUSED(PIN(3, 5))       /* GPO35/CR_SOUT4/TEST_L */
+UNUSED(PIN(6, 6))       /* GPIO66 */
+UNUSED(PIN(8, 1))       /* GPIO81/PECI_DATA */
+UNUSED(PIN(5, 6))       /* GPIO56/CLKRUN# */
+UNUSED(PIN(9, 7))       /* GPIO97 */
+UNUSED(PIN(8, 6))       /* GPIO86/TXD/CR_SOUT2 */
+UNUSED(PIN(1, 3))       /* KSO06/GPO13/GP_SEL# */
+UNUSED(PIN(1, 2))       /* KSO07/GPO12/JEN# */
+UNUSED(PIN(0, 6))       /* KSO11/GPIO06/P80_CLK */
+UNUSED(PIN(A, 0))
+UNUSED(PIN(A, 2))
+UNUSED(PIN(A, 3))
+UNUSED(PIN(B, 1))
+UNUSED(PIN(B, 5))
+UNUSED(PIN(B, 4))
+UNUSED(PIN(D, 2))
+UNUSED(PIN(D, 4))
+UNUSED(PIN(F, 5))
+UNUSED(PIN(0, 5))
+UNUSED(PIN(1, 1))
+UNUSED(PIN(1, 0))
+UNUSED(PIN(1, 7))
+UNUSED(PIN(1, 6))
+UNUSED(PIN(2, 5))
+UNUSED(PIN(3, 3))
+UNUSED(PIN(3, 6))
+UNUSED(PIN(4, 1))
+UNUSED(PIN(8, 3))
+UNUSED(PIN(9, 3))
+UNUSED(PIN(9, 5))
+UNUSED(PIN(9, 6))
diff --git a/board/lisbon/i2c.c b/board/lisbon/i2c.c
new file mode 100644
index 0000000000..a58f75bfa7
--- /dev/null
+++ b/board/lisbon/i2c.c
@@ -0,0 +1,53 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "i2c.h"
+
+/* I2C port map configuration */
+const struct i2c_port_t i2c_ports[] = {
+	{
+		/* I2C1 */
+		.name = "tcpc0",
+		.port = I2C_PORT_USB_C0_TCPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C2_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C2_TCPC_SDA,
+	},
+	{
+		/* I2C2 */
+		.name = "ppc, bc1.2 c0",
+		.port = I2C_PORT_USB_C0_PPC_BC12,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C2_PPC_BC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C2_PPC_BC_SDA,
+	},
+	{
+		/* I2C3 */
+		.name = "retimer0",
+		.port = I2C_PORT_USB_C0_MUX,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C2_RT_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C2_RT_SDA,
+	},
+	{
+		/* I2C6 */
+		.name = "usba2_retimer, usba3_retimer",
+		.port = I2C_PORT_USB_A2_A3_RT,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_A2_A3_SCL,
+		.sda = GPIO_EC_I2C_USB_A2_A3_SDA,
+	},
+	{
+		/* I2C7 */
+		.name = "eeprom",
+		.port = I2C_PORT_EEPROM,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_MISC_SCL_R,
+		.sda = GPIO_EC_I2C_MISC_SDA_R,
+	},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/board/lisbon/led.c b/board/lisbon/led.c
new file mode 100644
index 0000000000..711b914660
--- /dev/null
+++ b/board/lisbon/led.c
@@ -0,0 +1,260 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power LED control for Lisbon.
+ * Solid green - active power
+ * Green flashing - suspended
+ * Red flashing - alert
+ * Solid red - critical
+ */
+
+#include "chipset.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "led_common.h"
+#include "pwm.h"
+#include "timer.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
+
+/*
+ * Due to the CSME-Lite processing, upon startup the CPU transitions through
+ * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so
+ * delay turning off the LED during suspend/shutdown.
+ */
+#define LED_CPU_DELAY_MS (2000 * MSEC)
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED };
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+enum led_color {
+	LED_OFF = 0,
+	LED_RED,
+	LED_GREEN,
+
+	/* Number of colors, not a color itself */
+	LED_COLOR_COUNT
+};
+
+static int set_color_power(enum led_color color, int duty)
+{
+	int green = 0;
+	int red = 0;
+
+	if (duty < 0 || 100 < duty)
+		return EC_ERROR_UNKNOWN;
+
+	switch (color) {
+	case LED_OFF:
+		break;
+	case LED_GREEN:
+		green = 1;
+		break;
+	case LED_RED:
+		red = 1;
+		break;
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+
+	if (red)
+		pwm_set_duty(PWM_CH_LED_RED, duty);
+	else
+		pwm_set_duty(PWM_CH_LED_RED, 0);
+
+	if (green)
+		pwm_set_duty(PWM_CH_LED_GREEN, duty);
+	else
+		pwm_set_duty(PWM_CH_LED_GREEN, 0);
+
+	return EC_SUCCESS;
+}
+
+static int set_color(enum ec_led_id id, enum led_color color, int duty)
+{
+	switch (id) {
+	case EC_LED_ID_POWER_LED:
+		return set_color_power(color, duty);
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+}
+
+#define LED_PULSE_US (2 * SECOND)
+/* 40 msec for nice and smooth transition. */
+#define LED_PULSE_TICK_US (40 * MSEC)
+
+/*
+ * When pulsing is enabled, brightness is incremented by <duty_inc> every
+ * <interval> usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented
+ * likewise in LED_PULSE_US usec.
+ */
+static struct {
+	uint32_t interval;
+	int duty_inc;
+	enum led_color color;
+	int duty;
+} led_pulse;
+
+#define CONFIG_TICK(interval, color) \
+	config_tick((interval), 100 / (LED_PULSE_US / (interval)), (color))
+
+static void config_tick(uint32_t interval, int duty_inc, enum led_color color)
+{
+	led_pulse.interval = interval;
+	led_pulse.duty_inc = duty_inc;
+	led_pulse.color = color;
+	led_pulse.duty = 0;
+}
+
+static void pulse_power_led(enum led_color color)
+{
+	set_color(EC_LED_ID_POWER_LED, color, led_pulse.duty);
+	if (led_pulse.duty + led_pulse.duty_inc > 100)
+		led_pulse.duty_inc = led_pulse.duty_inc * -1;
+	else if (led_pulse.duty + led_pulse.duty_inc < 0)
+		led_pulse.duty_inc = led_pulse.duty_inc * -1;
+	led_pulse.duty += led_pulse.duty_inc;
+}
+
+static void led_tick(void);
+DECLARE_DEFERRED(led_tick);
+static void led_tick(void)
+{
+	uint32_t elapsed;
+	uint32_t next = 0;
+	uint32_t start = get_time().le.lo;
+
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		pulse_power_led(led_pulse.color);
+	elapsed = get_time().le.lo - start;
+	next = led_pulse.interval > elapsed ? led_pulse.interval - elapsed : 0;
+	hook_call_deferred(&led_tick_data, next);
+}
+
+static void led_suspend(void)
+{
+	CONFIG_TICK(LED_PULSE_TICK_US, LED_GREEN);
+	led_tick();
+}
+DECLARE_DEFERRED(led_suspend);
+
+static void led_shutdown(void)
+{
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_OFF, 0);
+}
+DECLARE_DEFERRED(led_shutdown);
+
+static void led_shutdown_hook(void)
+{
+	hook_call_deferred(&led_tick_data, -1);
+	hook_call_deferred(&led_suspend_data, -1);
+	hook_call_deferred(&led_shutdown_data, LED_CPU_DELAY_MS);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, led_shutdown_hook, HOOK_PRIO_DEFAULT);
+
+static void led_suspend_hook(void)
+{
+	hook_call_deferred(&led_shutdown_data, -1);
+	hook_call_deferred(&led_suspend_data, LED_CPU_DELAY_MS);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, led_suspend_hook, HOOK_PRIO_DEFAULT);
+
+static void led_resume(void)
+{
+	/*
+	 * Assume there is no race condition with led_tick, which also
+	 * runs in hook_task.
+	 */
+	hook_call_deferred(&led_tick_data, -1);
+	/*
+	 * Avoid invoking the suspend/shutdown delayed hooks.
+	 */
+	hook_call_deferred(&led_suspend_data, -1);
+	hook_call_deferred(&led_shutdown_data, -1);
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_GREEN, 100);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, led_resume, HOOK_PRIO_DEFAULT);
+
+void led_alert(int enable)
+{
+	if (enable) {
+		/* Overwrite the current signal */
+		config_tick(1 * SECOND, 100, LED_RED);
+		led_tick();
+	} else {
+		/* Restore the previous signal */
+		if (chipset_in_state(CHIPSET_STATE_ON))
+			led_resume();
+		else if (chipset_in_state(CHIPSET_STATE_SUSPEND))
+			led_suspend_hook();
+		else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+			led_shutdown_hook();
+	}
+}
+
+void show_critical_error(void)
+{
+	hook_call_deferred(&led_tick_data, -1);
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_RED, 100);
+}
+
+static int command_led(int argc, const char **argv)
+{
+	enum ec_led_id id = EC_LED_ID_POWER_LED;
+
+	if (argc < 2)
+		return EC_ERROR_PARAM_COUNT;
+
+	if (!strcasecmp(argv[1], "debug")) {
+		led_auto_control(id, !led_auto_control_is_enabled(id));
+		ccprintf("o%s\n", led_auto_control_is_enabled(id) ? "ff" : "n");
+	} else if (!strcasecmp(argv[1], "off")) {
+		set_color(id, LED_OFF, 0);
+	} else if (!strcasecmp(argv[1], "red")) {
+		set_color(id, LED_RED, 100);
+	} else if (!strcasecmp(argv[1], "green")) {
+		set_color(id, LED_GREEN, 100);
+	} else if (!strcasecmp(argv[1], "alert")) {
+		led_alert(1);
+	} else if (!strcasecmp(argv[1], "crit")) {
+		show_critical_error();
+	} else {
+		return EC_ERROR_PARAM1;
+	}
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(led, command_led, "[debug|red|green|off|alert|crit]",
+			"Turn on/off LED.");
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	brightness_range[EC_LED_COLOR_RED] = 100;
+	brightness_range[EC_LED_COLOR_GREEN] = 100;
+}
+
+int led_set_brightness(enum ec_led_id id, const uint8_t *brightness)
+{
+	if (brightness[EC_LED_COLOR_RED])
+		return set_color(id, LED_RED, brightness[EC_LED_COLOR_RED]);
+	else if (brightness[EC_LED_COLOR_GREEN])
+		return set_color(id, LED_GREEN, brightness[EC_LED_COLOR_GREEN]);
+	else
+		return set_color(id, LED_OFF, 0);
+}
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
+{
+	/* Blink alert if insufficient power per system_can_boot_ap(). */
+	int insufficient_power =
+		(charge_ma * charge_mv) <
+		(CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON * 1000);
+	led_alert(insufficient_power);
+}
diff --git a/board/lisbon/pwm.c b/board/lisbon/pwm.c
new file mode 100644
index 0000000000..db85952f41
--- /dev/null
+++ b/board/lisbon/pwm.c
@@ -0,0 +1,33 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "hooks.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_LED_GREEN] = { .channel = 0,
+			       .flags = PWM_CONFIG_ACTIVE_LOW |
+					PWM_CONFIG_DSLEEP,
+			       .freq = 2000 },
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN | PWM_CONFIG_DSLEEP,
+			 .freq = 1000 },
+	[PWM_CH_LED_RED] = { .channel = 2,
+			     .flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+			     .freq = 2000 },
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+static void board_pwm_init(void)
+{
+	pwm_enable(PWM_CH_FAN, 1);
+
+	pwm_enable(PWM_CH_LED_RED, 1);
+	pwm_enable(PWM_CH_LED_GREEN, 1);
+}
+DECLARE_HOOK(HOOK_INIT, board_pwm_init, HOOK_PRIO_DEFAULT);
diff --git a/board/lisbon/sensors.c b/board/lisbon/sensors.c
new file mode 100644
index 0000000000..99bc0a4304
--- /dev/null
+++ b/board/lisbon/sensors.c
@@ -0,0 +1,114 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc_chip.h"
+#include "common.h"
+#include "hooks.h"
+#include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
+#include "thermal.h"
+
+/* ADC configuration */
+const struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_1_CPU] = {
+		.name = "TEMP_CPU",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_2_CPU_VR] = {
+		.name = "TEMP_CPU_VR",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_3_WIFI] = {
+		.name = "TEMP_WIFI",
+		.input_ch = NPCX_ADC_CH6,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_4_DIMM] = {
+		.name = "TEMP_DIMM",
+		.input_ch = NPCX_ADC_CH7,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_VBUS] = {  /* 5/39 voltage divider */
+		.name = "VBUS",
+		.input_ch = NPCX_ADC_CH2,
+		.factor_mul = ADC_MAX_VOLT * 39,
+		.factor_div = (ADC_READ_MAX + 1) * 5,
+	},
+	[ADC_PPVAR_IMON] = {  /* 872.3 mV/A */
+		.name = "PPVAR_IMON",
+		.input_ch = NPCX_ADC_CH3,
+		.factor_mul = ADC_MAX_VOLT * 1433,
+		.factor_div = (ADC_READ_MAX + 1) * 1250,
+	},
+
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* Temperature sensor configuration */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1_CPU] = { .name = "CPU",
+				.type = TEMP_SENSOR_TYPE_BOARD,
+				.read = get_temp_3v3_30k9_47k_4050b,
+				.idx = ADC_TEMP_SENSOR_1_CPU },
+	[TEMP_SENSOR_2_CPU_VR] = { .name = "CPU VR",
+				   .type = TEMP_SENSOR_TYPE_BOARD,
+				   .read = get_temp_3v3_30k9_47k_4050b,
+				   .idx = ADC_TEMP_SENSOR_2_CPU_VR },
+	[TEMP_SENSOR_3_WIFI] = { .name = "WIFI",
+				 .type = TEMP_SENSOR_TYPE_BOARD,
+				 .read = get_temp_3v3_30k9_47k_4050b,
+				 .idx = ADC_TEMP_SENSOR_3_WIFI },
+	[TEMP_SENSOR_4_DIMM] = { .name = "DIMM",
+				 .type = TEMP_SENSOR_TYPE_BOARD,
+				 .read = get_temp_3v3_30k9_47k_4050b,
+				 .idx = ADC_TEMP_SENSOR_4_DIMM },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/*
+ * TODO(b/180681346): update for Alder Lake/brya
+ *
+ * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
+ * 130 C.  However, sensor is located next to DDR, so we need to use the lower
+ * DDR temperature limit (85 C)
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+		}, \
+		.temp_fan_off = C_TO_K(40), \
+		.temp_fan_max = C_TO_K(80), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
+
+/*
+ * TODO(b/197478860): add the thermal sensor setting
+ */
+/* this should really be "const" */
+struct ec_thermal_config thermal_params[] = {
+	[TEMP_SENSOR_1_CPU] = THERMAL_CPU,
+	[TEMP_SENSOR_2_CPU_VR] = THERMAL_CPU,
+	[TEMP_SENSOR_3_WIFI] = THERMAL_CPU,
+	[TEMP_SENSOR_4_DIMM] = THERMAL_CPU,
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
diff --git a/board/lisbon/usbc_config.c b/board/lisbon/usbc_config.c
new file mode 100644
index 0000000000..c010eb1333
--- /dev/null
+++ b/board/lisbon/usbc_config.c
@@ -0,0 +1,162 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/bc12/pi3usb9201_public.h"
+#include "driver/ppc/syv682x_public.h"
+#include "driver/retimer/ps8818_public.h"
+#include "driver/tcpm/rt1715.h"
+#include "driver/tcpm/tcpci.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "system.h"
+#include "task.h"
+#include "task_id.h"
+#include "timer.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+/* USBC TCPC configuration */
+const struct tcpc_config_t tcpc_config[] = {
+	[USBC_PORT_C0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0_TCPC,
+			.addr_flags = RT1715_I2C_ADDR_FLAGS,
+		},
+		.drv = &rt1715_tcpm_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
+BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
+
+/* USBC PPC configuration */
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_PPC_BC12,
+		.i2c_addr_flags = SYV682X_ADDR2_FLAGS,
+		.drv = &syv682x_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
+
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/* USBC mux configuration - Alder Lake includes internal mux */
+static const struct usb_mux_chain usbc0_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+
+static int board_c0_ps8818_mux_set(const struct usb_mux *me,
+				   mux_state_t mux_state)
+{
+	if (mux_state & USB_PD_MUX_DP_ENABLED)
+		gpio_set_level(GPIO_USB_C0_HPD, 1);
+	else
+		gpio_set_level(GPIO_USB_C0_HPD, 0);
+
+	return 0;
+}
+
+const struct usb_mux_chain usb_muxes[] = {
+	[USBC_PORT_C0] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &ps8818_usb_retimer_driver,
+			.i2c_port = I2C_PORT_USB_C0_MUX,
+			.i2c_addr_flags = PS8818_I2C_ADDR3_FLAGS,
+			.board_set = &board_c0_ps8818_mux_set,
+		},
+		.next = &usbc0_tcss_usb_mux,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
+
+/* BC1.2 charger detect configuration */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_PPC_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
+
+void board_reset_pd_mcu(void)
+{
+	/* Using RT1716, no reset available for TCPC */
+}
+
+static void board_tcpc_init(void)
+{
+	/* Don't reset TCPCs after initial reset */
+	if (!system_jumped_late())
+		board_reset_pd_mcu();
+
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_C2_TCPC_INT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (gpio_get_level(GPIO_USB_C0_C2_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_0;
+
+	return status;
+}
+
+int ppc_get_alert_status(int port)
+{
+	if (port == USBC_PORT_C0)
+		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
+
+	return 0;
+}
+
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	schedule_deferred_pd_interrupt(USBC_PORT_C0);
+}
+
+void bc12_interrupt(enum gpio_signal signal)
+{
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	syv682x_interrupt(USBC_PORT_C0);
+}
+
+void retimer_interrupt(enum gpio_signal signal)
+{
+	/*
+	 * TODO(b/179513527): add USB-C support
+	 */
+}
diff --git a/board/lisbon/usbc_config.h b/board/lisbon/usbc_config.h
new file mode 100644
index 0000000000..9e7f05a676
--- /dev/null
+++ b/board/lisbon/usbc_config.h
@@ -0,0 +1,15 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Lisbon board-specific USB-C configuration */
+
+#ifndef __CROS_EC_USBC_CONFIG_H
+#define __CROS_EC_USBC_CONFIG_H
+
+#define CONFIG_USB_PD_PORT_MAX_COUNT 1
+
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_COUNT };
+
+#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/lisbon/vif_override.xml b/board/lisbon/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/lisbon/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/madoo/battery.c b/board/madoo/battery.c
index 9d17d9b0fd..b37cb463dd 100644
--- a/board/madoo/battery.c
+++ b/board/madoo/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -12,7 +12,7 @@
 #include "extpower.h"
 
 /* Shutdown mode parameter to write to manufacturer access register */
-#define SB_SHUTDOWN_DATA	0x0010
+#define SB_SHUTDOWN_DATA 0x0010
 
 const struct board_batt_params board_battery_info[] = {
 	[BATTERY_SIMPLO_HIGHPOWER] = {
@@ -123,7 +123,7 @@ const struct board_batt_params board_battery_info[] = {
 			.discharging_max_c = 60,
 		},
 	},
-	[BATTERY_DynaPack_COS] = {
+	[BATTERY_DYNAPACK_COS] = {
 		.fuel_gauge = {
 			.manuf_name = "333-2C-DA-A",
 			.ship_mode = {
@@ -150,7 +150,7 @@ const struct board_batt_params board_battery_info[] = {
 			.discharging_max_c = 60,
 		},
 	},
-	[BATTERY_DANAPACK_ATL] = {
+	[BATTERY_DYNAPACK_ATL] = {
 		.fuel_gauge = {
 			.manuf_name = "333-27-DA-A",
 			.ship_mode = {
diff --git a/board/madoo/board.c b/board/madoo/board.c
index 9ced2a0ecb..bb031c3acf 100644
--- a/board/madoo/board.c
+++ b/board/madoo/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,7 +9,7 @@
 #include "button.h"
 #include "cbi_fw_config.h"
 #include "charge_manager.h"
-#include "charge_state_v2.h"
+#include "charge_state.h"
 #include "charger.h"
 #include "chipset.h"
 #include "common.h"
@@ -28,8 +28,8 @@
 #include "gpio.h"
 #include "hooks.h"
 #include "i2c.h"
-#include "keyboard_scan.h"
 #include "keyboard_8042_sharedlib.h"
+#include "keyboard_scan.h"
 #include "lid_switch.h"
 #include "motion_sense.h"
 #include "power.h"
@@ -46,34 +46,81 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-static void tcpc_alert_event(enum gpio_signal s)
-{
-	int port = (s == GPIO_USB_C0_INT_ODL) ? 0 : 1;
+#define INT_RECHECK_US 5000
 
-	schedule_deferred_pd_interrupt(port);
-}
+/* C0 interrupt line shared by BC 1.2 and charger */
+static void check_c0_line(void);
+DECLARE_DEFERRED(check_c0_line);
 
-static void usb_c0_interrupt(enum gpio_signal s)
+static void notify_c0_chips(void)
 {
 	/*
 	 * The interrupt line is shared between the TCPC and BC 1.2 detection
 	 * chip.  Therefore we'll need to check both ICs.
 	 */
-	tcpc_alert_event(s);
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
+	schedule_deferred_pd_interrupt(0);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
 }
 
-static void sub_usb_c1_interrupt(enum gpio_signal s)
+static void check_c0_line(void)
 {
 	/*
-	 * The interrupt line is shared between the TCPC and BC 1.2 detection
-	 * chip.  Therefore we'll need to check both ICs.
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		notify_c0_chips();
+		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+	}
+}
+
+static void usb_c0_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c0_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c0_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+}
+
+/* C1 interrupt line shared by BC 1.2, TCPC, and charger */
+static void check_c1_line(void);
+DECLARE_DEFERRED(check_c1_line);
+
+static void notify_c1_chips(void)
+{
+	schedule_deferred_pd_interrupt(1);
+	usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+}
+
+static void check_c1_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips.
 	 */
-	tcpc_alert_event(s);
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12, 0);
+	if (!gpio_get_level(GPIO_USB_C1_INT_ODL)) {
+		notify_c1_chips();
+		hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
+	}
+}
+
+static void sub_usb_c1_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c1_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c1_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
 }
 
 static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
@@ -82,6 +129,7 @@ static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
 	pd_handle_cc_overvoltage(0);
 }
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /* ADC channels */
@@ -128,8 +176,18 @@ void board_init(void)
 	/* Enable gpio interrupt for base accelgyro sensor */
 	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
 
+	/*
+	 * If interrupt lines are already low, schedule them to be processed
+	 * after inits are completed.
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL))
+		hook_call_deferred(&check_c0_line_data, 0);
+	if (!gpio_get_level(GPIO_USB_C1_INT_ODL))
+		hook_call_deferred(&check_c1_line_data, 0);
+
 	/* Turn on 5V if the system is on, otherwise turn it off. */
-	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND);
+	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
+			      CHIPSET_STATE_SOFT_OFF);
 	board_power_5v_enable(on);
 	if (get_cbi_fw_config_keyboard() == CUST_UK2_KB) {
 		/*
@@ -151,8 +209,8 @@ void board_hibernate(void)
 	 * Both charger ICs need to be put into their "low power mode" before
 	 * entering the Z-state.
 	 */
-	raa489000_hibernate(1);
-	raa489000_hibernate(0);
+	raa489000_hibernate(1, true);
+	raa489000_hibernate(0, false);
 }
 
 void board_reset_pd_mcu(void)
@@ -163,40 +221,9 @@ void board_reset_pd_mcu(void)
 	 */
 }
 
-static void reconfigure_5v_gpio(void)
-{
-	/*
-	 * b/147257497: On early boards, GPIO_EN_PP5000 was swapped with
-	 * GPIO_VOLUP_BTN_ODL. Therefore, we'll actually need to set that GPIO
-	 * instead for those boards.  Note that this breaks the volume up button
-	 * functionality.
-	 */
-	if (system_get_board_version() < 0) {
-		CPRINTS("old board - remapping 5V en");
-		gpio_set_flags(GPIO_VOLUP_BTN_ODL, GPIO_OUT_LOW);
-	}
-}
-DECLARE_HOOK(HOOK_INIT, reconfigure_5v_gpio, HOOK_PRIO_INIT_I2C+1);
-
 static void set_5v_gpio(int level)
 {
-	int version;
-	enum gpio_signal gpio;
-
-	/*
-	 * b/147257497: On early boards, GPIO_EN_PP5000 was swapped with
-	 * GPIO_VOLUP_BTN_ODL. Therefore, we'll actually need to set that GPIO
-	 * instead for those boards.  Note that this breaks the volume up button
-	 * functionality.
-	 */
-	version = system_get_board_version();
-
-	/*
-	 * If the CBI EEPROM wasn't formatted, assume it's a very early board.
-	 */
-	gpio = version < 0 ? GPIO_VOLUP_BTN_ODL : GPIO_EN_PP5000;
-
-	gpio_set_level(gpio, level);
+	gpio_set_level(GPIO_EN_PP5000, level);
 }
 
 __override void board_power_5v_enable(int enable)
@@ -209,8 +236,7 @@ __override void board_power_5v_enable(int enable)
 	set_5v_gpio(!!enable);
 
 	if (isl923x_set_comparator_inversion(1, !!enable))
-		CPRINTS("Failed to %sable sub rails!", enable ?
-								"en" : "dis");
+		CPRINTS("Failed to %sable sub rails!", enable ? "en" : "dis");
 }
 
 int board_is_sourcing_vbus(int port)
@@ -219,13 +245,11 @@ int board_is_sourcing_vbus(int port)
 
 	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
 	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
-
 }
 
 int board_set_active_charge_port(int port)
 {
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	int i;
 	int old_port;
 
@@ -238,9 +262,11 @@ int board_set_active_charge_port(int port)
 
 	/* Disable all ports. */
 	if (port == CHARGE_PORT_NONE) {
-		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
+		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
 			tcpc_write(i, TCPC_REG_COMMAND,
 				   TCPC_REG_COMMAND_SNK_CTRL_LOW);
+			raa489000_enable_asgate(i, false);
+		}
 
 		return EC_SUCCESS;
 	}
@@ -262,6 +288,7 @@ int board_set_active_charge_port(int port)
 		if (tcpc_write(i, TCPC_REG_COMMAND,
 			       TCPC_REG_COMMAND_SNK_CTRL_LOW))
 			CPRINTS("p%d: sink path disable failed.", i);
+		raa489000_enable_asgate(i, false);
 	}
 
 	/*
@@ -272,7 +299,8 @@ int board_set_active_charge_port(int port)
 		charger_discharge_on_ac(1);
 
 	/* Enable requested charge port. */
-	if (tcpc_write(port, TCPC_REG_COMMAND,
+	if (raa489000_enable_asgate(port, true) ||
+	    tcpc_write(port, TCPC_REG_COMMAND,
 		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
 		CPRINTS("p%d: sink path enable failed.", port);
 		charger_discharge_on_ac(0);
@@ -285,16 +313,12 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
 {
-	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
+	if (port < 0 || port > board_get_usb_pd_port_count())
+		return;
 
-	/*
-	 * TODO(b:147463641): Characterize the input current limit in case that
-	 * a scaling needs to be applied here.
-	 */
-	charge_set_input_current_limit(icl, charge_mv);
+	raa489000_set_output_current(port, rp);
 }
 
 /* Sensors */
@@ -302,17 +326,13 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrices to rotate accelerometers into the standard reference. */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					     { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					      { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
 
 static struct accelgyro_saved_data_t g_bma253_data;
 static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
@@ -352,8 +372,6 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_base_mutex,
 		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
 				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
 		.port = I2C_PORT_SENSOR,
 		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
 		.rot_standard_ref = &base_standard_ref,
@@ -381,8 +399,6 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_base_mutex,
 		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
 				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
 		.port = I2C_PORT_SENSOR,
 		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
 		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
@@ -396,40 +412,26 @@ const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
 /* Thermistors */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Charger",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Charger",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
+__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+				       int *ki_div, int *kd, int *kd_div)
 {
-	/*
-	 * Early boards need different constants due to a change in charger IC
-	 * silicon revision.
-	 */
-	if (system_get_board_version() >= 0) {
-		*kp = 1;
-		*kp_div = 128;
-		*ki = 1;
-		*ki_div = 1024;
-		*kd = 0;
-		*kd_div = 1;
-	} else {
-		*kp = 1;
-		*kp_div = 4;
-		*ki = 1;
-		*ki_div = 15;
-		*kd = 1;
-		*kd_div = 10;
-	}
+	*kp = 1;
+	*kp_div = 20;
+	*ki = 1;
+	*ki_div = 250;
+	*kd = 0;
+	*kd_div = 1;
 }
 
 int pd_snk_is_vbus_provided(int port)
@@ -497,31 +499,43 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usbc0_retimer = {
-	.usb_port = 0,
-	.i2c_port = I2C_PORT_USB_C0,
-	.i2c_addr_flags = NB7V904M_I2C_ADDR0,
-	.driver = &nb7v904m_usb_redriver_drv,
+const struct usb_mux_chain usbc0_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = 0,
+			.i2c_port = I2C_PORT_USB_C0,
+			.i2c_addr_flags = NB7V904M_I2C_ADDR0,
+			.driver = &nb7v904m_usb_redriver_drv,
+		},
 };
-const struct usb_mux usbc1_retimer = {
-	.usb_port = 1,
-	.i2c_port = I2C_PORT_SUB_USB_C1,
-	.i2c_addr_flags = NB7V904M_I2C_ADDR0,
-	.driver = &nb7v904m_usb_redriver_drv,
+const struct usb_mux_chain usbc1_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = 1,
+			.i2c_port = I2C_PORT_SUB_USB_C1,
+			.i2c_addr_flags = NB7V904M_I2C_ADDR0,
+			.driver = &nb7v904m_usb_redriver_drv,
+		},
 };
-struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
-		.driver = &pi3usb3x532_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
+				.driver = &pi3usb3x532_usb_mux_driver,
+			},
 	},
 	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
-		.driver = &pi3usb3x532_usb_mux_driver,
-		.next_mux = &usbc1_retimer,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_SUB_USB_C1,
+				.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
+				.driver = &pi3usb3x532_usb_mux_driver,
+			},
+		.next = &usbc1_retimer,
 	}
 };
 
@@ -529,10 +543,10 @@ static void reconfigure_usbmux(void)
 {
 	if (system_get_board_version() < 2) {
 		CPRINTS("add redriver at usbc0");
-		usb_muxes[0].next_mux = &usbc0_retimer;
+		usb_muxes[0].next = &usbc0_retimer;
 	}
 }
-DECLARE_HOOK(HOOK_INIT, reconfigure_usbmux, HOOK_PRIO_INIT_I2C+1);
+DECLARE_HOOK(HOOK_INIT, reconfigure_usbmux, HOOK_PRIO_INIT_I2C + 1);
 
 uint16_t tcpc_get_alert_status(void)
 {
@@ -569,9 +583,8 @@ uint16_t tcpc_get_alert_status(void)
 	return status;
 }
 
-#ifndef TEST_BUILD
 /* This callback disables keyboard when convertibles are fully open */
-void lid_angle_peripheral_enable(int enable)
+__override void lid_angle_peripheral_enable(int enable)
 {
 	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
 
@@ -595,4 +608,3 @@ void lid_angle_peripheral_enable(int enable)
 			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
 	}
 }
-#endif
diff --git a/board/madoo/board.h b/board/madoo/board.h
index 100e39e842..1e7118ba28 100644
--- a/board/madoo/board.h
+++ b/board/madoo/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,19 +11,22 @@
 #define VARIANT_DEDEDE_EC_NPCX796FC
 #include "baseboard.h"
 
-/*
- * Keep the system unlocked in early development.
- * TODO(b/151264302): Make sure to remove this before production!
- */
-#define CONFIG_SYSTEM_UNLOCKED
-
 /* Charger */
 #define CONFIG_CHARGER_RAA489000
+#define PD_MAX_VOLTAGE_MV 20000
 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 #define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */
+#define CONFIG_OCPC_DEF_RBATT_MOHMS               \
+	22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \
+	    */
+/*
+ * b/147463641: The charger IC seems to overdraw ~4%, therefore we
+ * reduce our target accordingly.
+ */
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 4
 #define CONFIG_OCPC
-#undef  CONFIG_CHARGER_SINGLE_CHIP
+#undef CONFIG_CHARGER_SINGLE_CHIP
 
 /* EC console commands */
 #define CONFIG_CMD_TCPC_DUMP
@@ -37,7 +40,7 @@
 
 /* PWM */
 #define CONFIG_PWM
-#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
+#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */
 
 /* USB */
 #define CONFIG_BC12_DETECT_PI3USB9201
@@ -45,12 +48,14 @@
 
 /* LED */
 #define CONFIG_LED_COMMON
-#define CONFIG_LED_POWER_LED
 #define CONFIG_LED_ONOFF_STATES
+#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
 
 /* USB PD */
 #define CONFIG_USB_PD_PORT_MAX_COUNT 2
 #define CONFIG_USB_PD_TCPM_RAA489000
+#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
+#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
 
 /* USB defines specific to external TCPCs */
 #define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
@@ -62,16 +67,16 @@
 #define CONFIG_USB_PD_5V_EN_CUSTOM
 
 /* I2C configuration */
-#define I2C_PORT_EEPROM     NPCX_I2C_PORT7_0
-#define I2C_PORT_BATTERY    NPCX_I2C_PORT5_0
-#define I2C_PORT_SENSOR     NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0     NPCX_I2C_PORT1_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
 #define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_MUX    I2C_PORT_USB_C0
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0
 /* TODO(b:147440290): Need to handle multiple charger ICs */
-#define I2C_PORT_CHARGER    I2C_PORT_USB_C0
+#define I2C_PORT_CHARGER I2C_PORT_USB_C0
 
-#define I2C_PORT_ACCEL      I2C_PORT_SENSOR
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
 
 #define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */
 
@@ -79,17 +84,15 @@
 #define CONFIG_CMD_ACCELS
 #define CONFIG_CMD_ACCEL_INFO
 
-#define CONFIG_ACCEL_BMA255		/* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM	/* Base accel */
+#define CONFIG_ACCEL_BMA255 /* Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
 
 /* Lid operates in forced mode, base in FIFO */
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
 #define CONFIG_ACCEL_FIFO
-#define CONFIG_ACCEL_FIFO_SIZE 256	/* Must be a power of 2 */
+#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */
 #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
 
-#define CONFIG_ACCEL_INTERRUPTS
-
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_UPDATE
 #define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
@@ -102,9 +105,6 @@
 #define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_GPIO
-
 #define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
 #define CONFIG_BATTERY_FUEL_GAUGE
 
@@ -114,7 +114,6 @@
 #define CONFIG_TEMP_SENSOR
 #define CONFIG_THERMISTOR
 #define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_PP3300_A
 
 #ifndef __ASSEMBLER__
 
@@ -128,25 +127,16 @@ enum chg_id {
 };
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_1,     /* ADC0 */
-	ADC_TEMP_SENSOR_2,     /* ADC1 */
-	ADC_SUB_ANALOG,	       /* ADC2 */
-	ADC_VSNS_PP3300_A,     /* ADC9 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
+	ADC_SUB_ANALOG, /* ADC2 */
+	ADC_VSNS_PP3300_A, /* ADC9 */
 	ADC_CH_COUNT
 };
 
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_COUNT
-};
+enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT };
 
 enum pwm_channel {
 	PWM_CH_KBLIGHT,
@@ -158,8 +148,8 @@ enum battery_type {
 	BATTERY_SIMPLO_COS,
 	BATTERY_CosMX,
 	BATTERY_SAMSUNG_SDI,
-	BATTERY_DynaPack_COS,
-	BATTERY_DANAPACK_ATL,
+	BATTERY_DYNAPACK_COS,
+	BATTERY_DYNAPACK_ATL,
 	BATTERY_TYPE_COUNT,
 };
 
@@ -169,7 +159,5 @@ enum fw_config_keyboard_type {
 	CUST_UK2_KB = 1,
 };
 
-int board_is_sourcing_vbus(int port);
-
 #endif /* !__ASSEMBLER__ */
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/madoo/build.mk b/board/madoo/build.mk
index e262a6aabc..1531d1f3ae 100644
--- a/board/madoo/build.mk
+++ b/board/madoo/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -11,4 +11,4 @@ CHIP_FAMILY:=npcx7
 CHIP_VARIANT:=npcx7m7fc
 BASEBOARD:=dedede
 
-board-y=board.o battery.o led.o usb_pd_policy.o
+board-y=board.o battery.o cbi_ssfc.o led.o usb_pd_policy.o
diff --git a/board/madoo/cbi_ssfc.c b/board/madoo/cbi_ssfc.c
new file mode 100644
index 0000000000..81f3ee0dad
--- /dev/null
+++ b/board/madoo/cbi_ssfc.c
@@ -0,0 +1,36 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi_ssfc.h"
+#include "common.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "hooks.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+/* Cache SSFC on init since we don't expect it to change in runtime */
+static union dedede_cbi_ssfc cached_ssfc;
+BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
+
+static void cbi_ssfc_init(void)
+{
+	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
+		/* Default to 0 when CBI isn't populated */
+		cached_ssfc.raw_value = 0;
+
+	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
+}
+DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
+
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
+{
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
+}
+
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
+{
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
+}
diff --git a/board/madoo/cbi_ssfc.h b/board/madoo/cbi_ssfc.h
new file mode 100644
index 0000000000..13800bcc85
--- /dev/null
+++ b/board/madoo/cbi_ssfc.h
@@ -0,0 +1,60 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _DEDEDE_CBI_SSFC__H_
+#define _DEDEDE_CBI_SSFC__H_
+
+#include "stdint.h"
+
+/****************************************************************************
+ * Dedede CBI Second Source Factory Cache
+ */
+
+/*
+ * Base Sensor (Bits 0-2)
+ */
+enum ec_ssfc_base_sensor {
+	SSFC_SENSOR_BASE_DEFAULT = 0,
+	SSFC_SENSOR_BMI160 = 1,
+	SSFC_SENSOR_ICM426XX = 2,
+	SSFC_SENSOR_LSM6DSM = 3,
+	SSFC_SENSOR_ICM42607 = 4
+};
+
+/*
+ * Lid Sensor (Bits 3-5)
+ */
+enum ec_ssfc_lid_sensor {
+	SSFC_SENSOR_LID_DEFAULT = 0,
+	SSFC_SENSOR_BMA255 = 1,
+	SSFC_SENSOR_KX022 = 2,
+	SSFC_SENSOR_LIS2DWL = 3
+};
+
+union dedede_cbi_ssfc {
+	struct {
+		uint32_t base_sensor : 3;
+		uint32_t lid_sensor : 3;
+		uint32_t usb_ss_mux : 3;
+		uint32_t reserved_2 : 23;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Get the Base sensor type from SSFC_CONFIG.
+ *
+ * @return the Base sensor board type.
+ */
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
+
+/**
+ * Get the Lid sensor type from SSFC_CONFIG.
+ *
+ * @return the Lid sensor board type.
+ */
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
+
+#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/madoo/ec.tasklist b/board/madoo/ec.tasklist
index 0aba1fabeb..ba5855412d 100644
--- a/board/madoo/ec.tasklist
+++ b/board/madoo/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/madoo/gpio.inc b/board/madoo/gpio.inc
index 53dece4e13..d3eb97ed11 100644
--- a/board/madoo/gpio.inc
+++ b/board/madoo/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -52,10 +52,6 @@ GPIO(EC_I2C_USB_C0_SDA,			PIN(8, 7), GPIO_INPUT)
 GPIO(EC_I2C_SUB_USB_C1_SCL,	PIN(9, 2), GPIO_INPUT)
 GPIO(EC_I2C_SUB_USB_C1_SDA,   PIN(9, 1), GPIO_INPUT)
 
-/* Extra Sub-board I/O pins */
-GPIO(EC_SUB_IO_1,  PIN(3, 7), GPIO_OUT_LOW)
-GPIO(EC_SUB_IO_2,  PIN(3, 4), GPIO_OUT_LOW)
-
 /* Misc Enables */
 GPIO(EN_VCCIO_EXT,   PIN(6, 1), GPIO_OUT_LOW)
 /* TODO(b:149775160) - Modify if needed if we ever use this signal. */
@@ -84,7 +80,7 @@ GPIO(EC_PROCHOT_ODL,	     PIN(F, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
 GPIO(EC_ENTERING_RW,	     PIN(E, 3), GPIO_OUT_LOW)
 GPIO(ALL_SYS_PWRGD,	     PIN(A, 0), GPIO_OUT_LOW)
 GPIO(SYS_RST_ODL,	     PIN(C, 5), GPIO_ODR_HIGH)
-GPIO(CCD_MODE_ODL,	     PIN(E, 5), GPIO_INPUT)
+GPIO(CCD_MODE_ODL,	     PIN(E, 5), GPIO_ODR_HIGH)
 
 GPIO(USB_C0_RST_ODL,	     PIN(9, 7), GPIO_OUT_HIGH) /* currently unused */
 GPIO(EC_AP_USB_C1_HDMI_HPD,  PIN(9, 6), GPIO_OUT_LOW)
@@ -96,6 +92,8 @@ GPIO(EC_BATTERY_PRES_ODL,    PIN(E, 1), GPIO_INPUT)
 GPIO(BAT_LED_AMBER_L,  PIN(C, 4), GPIO_OUT_HIGH)
 GPIO(BAT_LED_WHITE_L,  PIN(C, 3), GPIO_OUT_HIGH)
 GPIO(PWR_LED_WHITE_L,  PIN(C, 2), GPIO_OUT_HIGH)
+GPIO(EC_CHG_LED_R_Y,  PIN(F, 2), GPIO_OUT_HIGH)
+GPIO(EC_CHG_LED_R_W,  PIN(F, 3), GPIO_OUT_HIGH)
 
 /*
  * Waddledoo doesn't have these physical pins coming to the EC but uses other
@@ -130,3 +128,18 @@ ALTERNATE(PIN_MASK(B, 0x3C), 0, MODULE_I2C, 0)   /* I2C7,I2C0 */
 ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)   /* I2C5 */
 ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)   /* I2C2, I2C1 SCL */
 ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)   /* I2C1 SDA */
+
+/* NC pins, enable internal pull-up to avoid floating state. */
+GPIO(GPIO00_NC, PIN(0, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO32_NC, PIN(3, 2), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO34_NC, PIN(3, 4), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO35_NC, PIN(3, 5), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO37_NC, PIN(3, 7), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO41_NC, PIN(4, 1), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO57_NC, PIN(5, 7), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO81_NC, PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO86_NC, PIN(8, 6), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOD0_NC, PIN(D, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOD1_NC, PIN(D, 1), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOD6_NC, PIN(D, 6), GPIO_INPUT | GPIO_PULL_UP)
diff --git a/board/madoo/led.c b/board/madoo/led.c
index e22f9cff42..3aabcb171c 100644
--- a/board/madoo/led.c
+++ b/board/madoo/led.c
@@ -1,56 +1,66 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Power and battery LED control for madoo
  */
 
+#include "charge_state.h"
+#include "driver/tcpm/tcpci.h"
 #include "ec_commands.h"
 #include "gpio.h"
+#include "hooks.h"
 #include "led_common.h"
 #include "led_onoff_states.h"
-#include "hooks.h"
+#include "system.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
-const int led_charge_lvl_1;
+__override const int led_charge_lvl_1;
 
-const int led_charge_lvl_2 = 100;
+__override const int led_charge_lvl_2 = 100;
 
 /* madoo: Note there is only LED for charge / power */
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF, 1 * LED_ONE_SEC} },
-	/* STATE_DISCHARGE_S3 will changed if sku is clamshells */
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER, 0.5 * LED_ONE_SEC},
-					{LED_OFF, 0.5 * LED_ONE_SEC} },
-};
-
-const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   1 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   1 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 1 * LED_ONE_SEC } },
+		/* STATE_DISCHARGE_S3 will changed if sku is clamshells */
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    0.5 * LED_ONE_SEC },
+					  { LED_OFF, 0.5 * LED_ONE_SEC } },
+	};
+
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 1 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    1 * LED_ONE_SEC },
+						  { LED_OFF,
+						    1 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-void led_set_color_power(enum ec_led_colors color)
+__override void led_set_color_power(enum ec_led_colors color)
 {
 	if (color == EC_LED_COLOR_WHITE)
 		gpio_set_level(GPIO_PWR_LED_WHITE_L, LED_ON_LVL);
@@ -59,20 +69,90 @@ void led_set_color_power(enum ec_led_colors color)
 		gpio_set_level(GPIO_PWR_LED_WHITE_L, LED_OFF_LVL);
 }
 
-void led_set_color_battery(enum ec_led_colors color)
+/*
+ * Turn off battery LED, if AC is present but battery is not charging.
+ * It could be caused by battery's protection like OTP.
+ */
+int battery_safety_check(void)
+{
+	uint8_t data[6];
+	int rv;
+
+	/* ignore battery in error state because it has other behavior */
+	if (led_pwr_get_state() == LED_PWRS_ERROR)
+		return false;
+
+	/* turn off LED due to a safety fault */
+	rv = sb_read_mfgacc(PARAM_SAFETY_STATUS, SB_ALT_MANUFACTURER_ACCESS,
+			    data, sizeof(data));
+	if (rv)
+		return false;
+	/*
+	 * Each bit represents for one safey status, and normally they should
+	 * all be 0. Data reads from LSB to MSB.
+	 * data[2] - BIT 7-0
+	 * AOLDL, AOLD, OCD2, OCD1, OCC2, OCC1, COV, CUV
+	 *
+	 * data[3] - BIT 15-8
+	 * RSVD, CUVC, OTD, OTC, ASCDL, ASCD, ASCCL, ASCC
+	 *
+	 * data[4] - BIT 23-16
+	 * CHGC, OC, RSVD, CTO, RSVD, PTO, RSVD, OTF
+	 *
+	 * data[5] - BIT 31-24
+	 * RSVD, RSVD, OCDL, COVL, UTD, UTC, PCHGC, CHGV
+	 */
+	if (data[2] || data[3] || data[4] || data[5])
+		return true;
+
+	return false;
+}
+
+__override void led_set_color_battery(enum ec_led_colors color)
 {
 	switch (color) {
 	case EC_LED_COLOR_WHITE:
-		gpio_set_level(GPIO_BAT_LED_WHITE_L, LED_ON_LVL);
-		gpio_set_level(GPIO_BAT_LED_AMBER_L, LED_OFF_LVL);
+		/* Ports are controlled by different GPIO */
+		if (battery_safety_check()) {
+			gpio_set_level(GPIO_BAT_LED_WHITE_L, LED_OFF_LVL);
+			gpio_set_level(GPIO_EC_CHG_LED_R_W, LED_OFF_LVL);
+		} else if (charge_manager_get_active_charge_port() == 1 ||
+			   system_get_board_version() < 3) {
+			gpio_set_level(GPIO_BAT_LED_WHITE_L, LED_ON_LVL);
+			gpio_set_level(GPIO_BAT_LED_AMBER_L, LED_OFF_LVL);
+		} else if (charge_manager_get_active_charge_port() == 0) {
+			gpio_set_level(GPIO_EC_CHG_LED_R_W, LED_ON_LVL);
+			gpio_set_level(GPIO_EC_CHG_LED_R_Y, LED_OFF_LVL);
+		}
 		break;
 	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_BAT_LED_WHITE_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_AMBER_L, LED_ON_LVL);
+		/* Ports are controlled by different GPIO */
+		if (battery_safety_check()) {
+			gpio_set_level(GPIO_BAT_LED_AMBER_L, LED_OFF_LVL);
+			gpio_set_level(GPIO_EC_CHG_LED_R_Y, LED_OFF_LVL);
+		} else if (led_pwr_get_state() == LED_PWRS_ERROR &&
+			   system_get_board_version() >= 3) {
+			gpio_set_level(GPIO_EC_CHG_LED_R_W, LED_OFF_LVL);
+			gpio_set_level(GPIO_EC_CHG_LED_R_Y, LED_ON_LVL);
+		} else if (charge_manager_get_active_charge_port() == 1 ||
+			   system_get_board_version() < 3) {
+			gpio_set_level(GPIO_BAT_LED_WHITE_L, LED_OFF_LVL);
+			gpio_set_level(GPIO_BAT_LED_AMBER_L, LED_ON_LVL);
+			gpio_set_level(GPIO_EC_CHG_LED_R_Y, LED_OFF_LVL);
+		} else if (charge_manager_get_active_charge_port() == 0) {
+			gpio_set_level(GPIO_EC_CHG_LED_R_W, LED_OFF_LVL);
+			gpio_set_level(GPIO_EC_CHG_LED_R_Y, LED_ON_LVL);
+		} else if (charge_get_percent() <
+			   CONFIG_LED_ONOFF_STATES_BAT_LOW) {
+			gpio_set_level(GPIO_EC_CHG_LED_R_W, LED_OFF_LVL);
+			gpio_set_level(GPIO_EC_CHG_LED_R_Y, LED_ON_LVL);
+		}
 		break;
 	default: /* LED_OFF and other unsupported colors */
 		gpio_set_level(GPIO_BAT_LED_WHITE_L, LED_OFF_LVL);
 		gpio_set_level(GPIO_BAT_LED_AMBER_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_EC_CHG_LED_R_W, LED_OFF_LVL);
+		gpio_set_level(GPIO_EC_CHG_LED_R_Y, LED_OFF_LVL);
 		break;
 	}
 }
@@ -105,4 +185,3 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 
 	return EC_SUCCESS;
 }
-
diff --git a/board/madoo/usb_pd_policy.c b/board/madoo/usb_pd_policy.c
index bcdf8300c5..2bad4d6931 100644
--- a/board/madoo/usb_pd_policy.c
+++ b/board/madoo/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,11 +7,12 @@
 #include "chipset.h"
 #include "common.h"
 #include "console.h"
+#include "driver/charger/isl923x_public.h"
 #include "driver/tcpm/tcpci.h"
 #include "usb_pd.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
@@ -24,11 +25,6 @@ void pd_power_supply_reset(int port)
 	/* Disable VBUS */
 	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
 
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	/* Give back the current quota we are no longer using */
-	charge_manager_source_port(port, 0);
-#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
-
 	/* Notify host of power info change. */
 	pd_send_host_event(PD_EVENT_POWER_CHANGE);
 }
@@ -54,10 +50,9 @@ int pd_set_power_supply_ready(int port)
 	if (rv)
 		return rv;
 
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	/* Ensure we advertise the proper available current quota */
-	charge_manager_source_port(port, 1);
-#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
+	rv = raa489000_enable_asgate(port, true);
+	if (rv)
+		return rv;
 
 	/* Notify host of power info change. */
 	pd_send_host_event(PD_EVENT_POWER_CHANGE);
diff --git a/board/madoo/vif_override.xml b/board/madoo/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/madoo/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/magolor/battery.c b/board/magolor/battery.c
index e7572946b2..748c079890 100644
--- a/board/magolor/battery.c
+++ b/board/magolor/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -93,6 +93,127 @@ const struct board_batt_params board_battery_info[] = {
 			.discharging_max_c	= 75,
 		},
 	},
+	/* AP19B8M */
+	[BATTERY_AP19B8M] = {
+		.fuel_gauge = {
+			.manuf_name = "LGC KT0030G024",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.reg_addr = 0x43,
+				.reg_mask = 0x0001,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0002,
+				.cfet_off_val = 0x0000,
+			}
+		},
+		.batt_info = {
+			.voltage_max          = 13350,
+			.voltage_normal       = 11610,
+			.voltage_min          = 9000,
+			.precharge_current    = 256,
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 50,
+			.charging_min_c       = 0,
+			.charging_max_c       = 60,
+			.discharging_min_c    = -20,
+			.discharging_max_c    = 75,
+		},
+	},
+	/* AP18C7M */
+	[BATTERY_AP18C7M] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP KT00407008",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0002,
+				.disconnect_val = 0x0000,
+				.cfet_mask = 0x4000,
+				.cfet_off_val = 0x4000,
+			}
+		},
+		.batt_info = {
+			.voltage_max          = 17600,
+			.voltage_normal       = 15400,
+			.voltage_min          = 12000,
+			.precharge_current    = 256,
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c       = 0,
+			.charging_max_c       = 60,
+			.discharging_min_c    = -20,
+			.discharging_max_c    = 70,
+		},
+	},
+	/* COSMX AP20CBL Battery Information */
+	 [BATTERY_COSMX_AP20CBL] = {
+		.fuel_gauge = {
+			.manuf_name = "COSMX KT0030B002",
+			.device_name = "AP20CBL",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x2000,
+				.disconnect_val = 0x2000,
+				.cfet_mask = 0x4000,
+				.cfet_off_val = 0x4000,
+			},
+		},
+		.batt_info = {
+			.voltage_max            = 13200,
+			.voltage_normal         = 11550,
+			.voltage_min            = 9000,
+			.precharge_current      = 256,
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 50,
+			.charging_min_c         = 0,
+			.charging_max_c         = 60,
+			.discharging_min_c      = -20,
+			.discharging_max_c      = 75,
+		},
+	},
+	/* COSMX AP20CBL Battery Information (new firmware ver) */
+	[BATTERY_COSMX_AP20CBL_004] = {
+		.fuel_gauge = {
+			.manuf_name = "COSMX KT0030B004",
+			.device_name = "AP20CBL",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x2000,
+				.disconnect_val = 0x2000,
+				.cfet_mask = 0x4000,
+				.cfet_off_val = 0x4000,
+			},
+		},
+		.batt_info = {
+			.voltage_max            = 13200,
+			.voltage_normal         = 11550,
+			.voltage_min            = 9000,
+			.precharge_current      = 256,
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 50,
+			.charging_min_c         = 0,
+			.charging_max_c         = 60,
+			.discharging_min_c      = -20,
+			.discharging_max_c      = 75,
+		},
+	},
 };
 BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
 
diff --git a/board/magolor/board.c b/board/magolor/board.c
index d173c25716..92505e1928 100644
--- a/board/magolor/board.c
+++ b/board/magolor/board.c
@@ -1,33 +1,40 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Waddledoo board-specific configuration */
 
-#include "adc_chip.h"
+#include "adc.h"
+#include "battery_fuel_gauge.h"
 #include "button.h"
+#include "cbi_fw_config.h"
+#include "cbi_ssfc.h"
 #include "charge_manager.h"
-#include "charge_state_v2.h"
+#include "charge_state.h"
 #include "charger.h"
 #include "chipset.h"
 #include "common.h"
 #include "compile_time_macros.h"
 #include "driver/accel_bma2x2.h"
+#include "driver/accel_kionix.h"
 #include "driver/accelgyro_bmi_common.h"
-#include "driver/temp_sensor/thermistor.h"
-#include "temp_sensor.h"
+#include "driver/accelgyro_icm426xx.h"
+#include "driver/accelgyro_icm_common.h"
 #include "driver/bc12/pi3usb9201.h"
 #include "driver/charger/isl923x.h"
-#include "driver/retimer/nb7v904m.h"
+#include "driver/retimer/ps8802.h"
 #include "driver/tcpm/raa489000.h"
 #include "driver/tcpm/tcpci.h"
+#include "driver/temp_sensor/thermistor.h"
 #include "driver/usb_mux/pi3usb3x532.h"
-#include "driver/retimer/ps8802.h"
+#include "driver/usb_mux/ps8743.h"
 #include "extpower.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "i2c.h"
+#include "keyboard_config.h"
+#include "keyboard_raw.h"
 #include "keyboard_scan.h"
 #include "lid_switch.h"
 #include "motion_sense.h"
@@ -40,18 +47,24 @@
 #include "system.h"
 #include "tablet_mode.h"
 #include "task.h"
+#include "temp_sensor.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+#define INT_RECHECK_US 5000
 
-#define ADC_VOL_UP_MASK     BIT(0)
-#define ADC_VOL_DOWN_MASK   BIT(1)
+#define ADC_VOL_UP_MASK BIT(0)
+#define ADC_VOL_DOWN_MASK BIT(1)
 
 static uint8_t new_adc_key_state;
 
+static void ps8762_chaddr_deferred(void);
+DECLARE_DEFERRED(ps8762_chaddr_deferred);
+
 /******************************************************************************/
 /* USB-A Configuration */
 const int usb_port_enable[USB_PORT_COUNT] = {
@@ -59,33 +72,220 @@ const int usb_port_enable[USB_PORT_COUNT] = {
 	GPIO_EN_USB_A1_VBUS,
 };
 
-static void tcpc_alert_event(enum gpio_signal s)
+#ifdef BOARD_MAGOLOR
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/*
+	 * F3 key scan cycle completed but scan input is not
+	 * charging to logic high when EC start scan next
+	 * column for "T" key, so we set .output_settle_us
+	 * to 80us from 50us.
+	 */
+	.output_settle_us = 80,
+	.debounce_down_us = 9 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x1c, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
+		0xa4, 0xff, 0xfe, 0x55, 0xfe, 0xff, 0xff, 0xff,  /* full set */
+	},
+};
+
+static const struct ec_response_keybd_config magolor_keybd = {
+	/* Default Chromeos keyboard config */
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_FORWARD,		/* T2 */
+		TK_REFRESH,		/* T3 */
+		TK_FULLSCREEN,		/* T4 */
+		TK_OVERVIEW,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	/* No function keys, no numeric keypad, has screenlock key */
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+static const struct ec_response_keybd_config magister_keybd = {
+	/* Default Chromeos keyboard config */
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	/* No function keys, no numeric keypad, has screenlock key */
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+static const struct ec_response_keybd_config magpie_keybd = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_FORWARD,		/* T2 */
+		TK_REFRESH,		/* T3 */
+		TK_FULLSCREEN,		/* T4 */
+		TK_OVERVIEW,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY | KEYBD_CAP_NUMERIC_KEYPAD,
+};
+
+static const struct ec_response_keybd_config magma_keybd = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY | KEYBD_CAP_NUMERIC_KEYPAD,
+};
+
+__override uint8_t board_keyboard_row_refresh(void)
 {
-	int port = (s == GPIO_USB_C0_INT_ODL) ? 0 : 1;
+	if (gpio_get_level(GPIO_EC_VIVALDIKEYBOARD_ID))
+		return 3;
+	else
+		return 2;
+}
 
-	schedule_deferred_pd_interrupt(port);
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	if (get_cbi_fw_config_numeric_pad()) {
+		if (gpio_get_level(GPIO_EC_VIVALDIKEYBOARD_ID))
+			return &magma_keybd;
+		else
+			return &magpie_keybd;
+	} else {
+		if (gpio_get_level(GPIO_EC_VIVALDIKEYBOARD_ID))
+			return &magister_keybd;
+		else
+			return &magolor_keybd;
+	}
 }
+#endif
 
-static void usb_c0_interrupt(enum gpio_signal s)
+/*
+ * We have total 30 pins for keyboard connecter {-1, -1} mean
+ * the N/A pin that don't consider it and reserve index 0 area
+ * that we don't have pin 0.
+ */
+const int keyboard_factory_scan_pins[][2] = {
+	{ -1, -1 }, { 0, 5 },	{ 1, 1 }, { 1, 0 },   { 0, 6 },	  { 0, 7 },
+	{ -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 },   { -1, -1 }, { 1, 6 },
+	{ 1, 7 },   { 3, 1 },	{ 2, 0 }, { 1, 5 },   { 2, 6 },	  { 2, 7 },
+	{ 2, 1 },   { 2, 4 },	{ 2, 5 }, { 1, 2 },   { 2, 3 },	  { 2, 2 },
+	{ 3, 0 },   { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 },	  { -1, -1 },
+	{ -1, -1 },
+};
+const int keyboard_factory_scan_pins_used =
+	ARRAY_SIZE(keyboard_factory_scan_pins);
+
+/* C0 interrupt line shared by BC 1.2 and charger */
+static void check_c0_line(void);
+DECLARE_DEFERRED(check_c0_line);
+
+static void notify_c0_chips(void)
 {
 	/*
 	 * The interrupt line is shared between the TCPC and BC 1.2 detection
 	 * chip.  Therefore we'll need to check both ICs.
 	 */
-	tcpc_alert_event(s);
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
+	schedule_deferred_pd_interrupt(0);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
 }
 
-static void sub_usb_c1_interrupt(enum gpio_signal s)
+static void check_c0_line(void)
 {
 	/*
-	 * The interrupt line is shared between the TCPC and BC 1.2 detection
-	 * chip.  Therefore we'll need to check both ICs.
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		notify_c0_chips();
+		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+	}
+}
+
+static void usb_c0_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c0_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c0_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+}
+
+/* C1 interrupt line shared by BC 1.2, TCPC, and charger */
+static void check_c1_line(void);
+DECLARE_DEFERRED(check_c1_line);
+
+static void notify_c1_chips(void)
+{
+	schedule_deferred_pd_interrupt(1);
+	usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+}
+
+static void check_c1_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips.
 	 */
-	tcpc_alert_event(s);
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12, 0);
+	if (!gpio_get_level(GPIO_SUB_C1_INT_EN_RAILS_ODL)) {
+		notify_c1_chips();
+		hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
+	}
+}
+
+static void sub_usb_c1_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c1_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c1_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
+}
+
+static void sub_hdmi_hpd_interrupt(enum gpio_signal s)
+{
+	int hdmi_hpd_odl = gpio_get_level(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL);
+
+	gpio_set_level(GPIO_EC_AP_USB_C1_HDMI_HPD, !hdmi_hpd_odl);
 }
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /* ADC channels */
@@ -123,56 +323,89 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* Thermistors */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_A                \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(85), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A;
 
-const static struct ec_thermal_config thermal_a = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(73),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-};
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_B                \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(73), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(85), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_b = THERMAL_B;
 
 struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
 
 static void setup_thermal(void)
 {
 	thermal_params[TEMP_SENSOR_1] = thermal_a;
-	thermal_params[TEMP_SENSOR_2] = thermal_a;
+	thermal_params[TEMP_SENSOR_2] = thermal_b;
 }
 
-void board_init(void)
+#ifdef BOARD_MAGOLOR
+static void board_update_no_keypad_by_fwconfig(void)
 {
-	int on;
-
-	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
-	gpio_enable_interrupt(GPIO_SUB_USB_C1_INT_ODL);
-	/* Enable gpio interrupt for base accelgyro sensor */
-	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
+	if (!get_cbi_fw_config_numeric_pad()) {
+#ifndef TEST_BUILD
+		/* Disable scanning KSO13 & 14 if keypad isn't present. */
+		keyboard_raw_set_cols(KEYBOARD_COLS_NO_KEYPAD);
+		keyscan_config.actual_key_mask[11] = 0xfa;
+		keyscan_config.actual_key_mask[12] = 0xca;
+#endif
+	}
+}
+#endif
 
-	/* Turn on 5V if the system is on, otherwise turn it off. */
-	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND);
-	board_power_5v_enable(on);
+/* Enable HDMI any time the SoC is on */
+static void hdmi_enable(void)
+{
+	if (get_cbi_fw_config_db() == DB_1A_HDMI)
+		gpio_set_level(GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, hdmi_enable, HOOK_PRIO_DEFAULT);
 
-	/* Initialize THERMAL */
-	setup_thermal();
+static void hdmi_disable(void)
+{
+	if (get_cbi_fw_config_db() == DB_1A_HDMI)
+		gpio_set_level(GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL, 1);
 }
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, hdmi_disable, HOOK_PRIO_DEFAULT);
 
 void board_hibernate(void)
 {
@@ -180,8 +413,11 @@ void board_hibernate(void)
 	 * Both charger ICs need to be put into their "low power mode" before
 	 * entering the Z-state.
 	 */
-	raa489000_hibernate(1);
-	raa489000_hibernate(0);
+	if (board_get_charger_chip_count() > 1)
+		raa489000_hibernate(1, true);
+	raa489000_hibernate(0, true);
+
+	msleep(1000); /* Wait for charger to enter low power mode */
 }
 
 void board_reset_pd_mcu(void)
@@ -192,42 +428,56 @@ void board_reset_pd_mcu(void)
 	 */
 }
 
+#ifdef BOARD_WADDLEDOO
 static void reconfigure_5v_gpio(void)
 {
 	/*
-	 * b/147257497: On early boards, GPIO_EN_PP5000 was swapped with
-	 * GPIO_VOLUP_BTN_ODL. Therefore, we'll actually need to set that GPIO
-	 * instead for those boards.  Note that this breaks the volume up button
-	 * functionality.
+	 * b/147257497: On early waddledoo boards, GPIO_EN_PP5000 was swapped
+	 * with GPIO_VOLUP_BTN_ODL. Therefore, we'll actually need to set that
+	 * GPIO instead for those boards.  Note that this breaks the volume up
+	 * button functionality.
 	 */
 	if (system_get_board_version() < 0) {
 		CPRINTS("old board - remapping 5V en");
 		gpio_set_flags(GPIO_VOLUP_BTN_ODL, GPIO_OUT_LOW);
 	}
 }
-DECLARE_HOOK(HOOK_INIT, reconfigure_5v_gpio, HOOK_PRIO_INIT_I2C+1);
+DECLARE_HOOK(HOOK_INIT, reconfigure_5v_gpio, HOOK_PRIO_INIT_I2C + 1);
+#endif /* BOARD_WADDLEDOO */
 
 static void set_5v_gpio(int level)
 {
 	int version;
-	enum gpio_signal gpio;
+	enum gpio_signal gpio = GPIO_EN_PP5000;
 
 	/*
-	 * b/147257497: On early boards, GPIO_EN_PP5000 was swapped with
-	 * GPIO_VOLUP_BTN_ODL. Therefore, we'll actually need to set that GPIO
-	 * instead for those boards.  Note that this breaks the volume up button
-	 * functionality.
+	 * b/147257497: On early waddledoo boards, GPIO_EN_PP5000 was swapped
+	 * with GPIO_VOLUP_BTN_ODL. Therefore, we'll actually need to set that
+	 * GPIO instead for those boards.  Note that this breaks the volume up
+	 * button functionality.
 	 */
-	version = system_get_board_version();
+	if (IS_ENABLED(BOARD_WADDLEDOO)) {
+		version = system_get_board_version();
 
-	/*
-	 * If the CBI EEPROM wasn't formatted, assume it's a very early board.
-	 */
-	gpio = version < 0 ? GPIO_VOLUP_BTN_ODL : GPIO_EN_PP5000;
+		/*
+		 * If the CBI EEPROM wasn't formatted, assume it's a very early
+		 * board.
+		 */
+		gpio = version < 0 ? GPIO_VOLUP_BTN_ODL : GPIO_EN_PP5000;
+	}
 
 	gpio_set_level(gpio, level);
 }
 
+static void ps8762_chaddr_deferred(void)
+{
+	/* Switch PS8762 I2C Address to 0x50*/
+	if (ps8802_chg_i2c_addr(I2C_PORT_SUB_USB_C1) == EC_SUCCESS)
+		CPRINTS("Switch PS8762 address to 0x50 success");
+	else
+		CPRINTS("Switch PS8762 address to 0x50 failed");
+}
+
 __override void board_power_5v_enable(int enable)
 {
 	/*
@@ -236,9 +486,40 @@ __override void board_power_5v_enable(int enable)
 	 * polarity on the sub board charger IC.
 	 */
 	set_5v_gpio(!!enable);
-	if (isl923x_set_comparator_inversion(1, !!enable))
-		CPRINTS("Failed to %sable sub rails!", enable ? "en" : "dis");
 
+	if (get_cbi_fw_config_db() == DB_1A_HDMI) {
+		gpio_set_level(GPIO_SUB_C1_INT_EN_RAILS_ODL, !enable);
+	} else {
+		if (isl923x_set_comparator_inversion(1, !!enable))
+			CPRINTS("Failed to %sable sub rails!",
+				enable ? "en" : "dis");
+
+		if (!enable)
+			return;
+		/*
+		 * Port C1 the PP3300_USB_C1  assert, delay 15ms
+		 * colud be accessed PS8762 by I2C.
+		 */
+		if (get_cbi_ssfc_usb_mux() == SSFC_USBMUX_PS8762)
+			hook_call_deferred(&ps8762_chaddr_deferred_data,
+					   15 * MSEC);
+	}
+}
+
+__override uint8_t board_get_usb_pd_port_count(void)
+{
+	if (get_cbi_fw_config_db() == DB_1A_HDMI)
+		return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
+	else
+		return CONFIG_USB_PD_PORT_MAX_COUNT;
+}
+
+__override uint8_t board_get_charger_chip_count(void)
+{
+	if (get_cbi_fw_config_db() == DB_1A_HDMI)
+		return CHARGER_NUM - 1;
+	else
+		return CHARGER_NUM;
 }
 
 int board_is_sourcing_vbus(int port)
@@ -247,13 +528,11 @@ int board_is_sourcing_vbus(int port)
 
 	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
 	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
-
 }
 
 int board_set_active_charge_port(int port)
 {
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count());
 	int i;
 	int old_port;
 
@@ -266,9 +545,11 @@ int board_set_active_charge_port(int port)
 
 	/* Disable all ports. */
 	if (port == CHARGE_PORT_NONE) {
-		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
+		for (i = 0; i < board_get_usb_pd_port_count(); i++) {
 			tcpc_write(i, TCPC_REG_COMMAND,
 				   TCPC_REG_COMMAND_SNK_CTRL_LOW);
+			raa489000_enable_asgate(i, false);
+		}
 
 		return EC_SUCCESS;
 	}
@@ -283,13 +564,14 @@ int board_set_active_charge_port(int port)
 	 * Turn off the other ports' sink path FETs, before enabling the
 	 * requested charge port.
 	 */
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
 		if (i == port)
 			continue;
 
 		if (tcpc_write(i, TCPC_REG_COMMAND,
 			       TCPC_REG_COMMAND_SNK_CTRL_LOW))
 			CPRINTS("p%d: sink path disable failed.", i);
+		raa489000_enable_asgate(i, false);
 	}
 
 	/*
@@ -300,7 +582,8 @@ int board_set_active_charge_port(int port)
 		charger_discharge_on_ac(1);
 
 	/* Enable requested charge port. */
-	if (tcpc_write(port, TCPC_REG_COMMAND,
+	if (raa489000_enable_asgate(port, true) ||
+	    tcpc_write(port, TCPC_REG_COMMAND,
 		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
 		CPRINTS("p%d: sink path enable failed.", port);
 		charger_discharge_on_ac(0);
@@ -313,16 +596,12 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
 {
-	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
+	if (port < 0 || port > board_get_usb_pd_port_count())
+		return;
 
-	/*
-	 * TODO(b:147463641): Characterize the input current limit in case that
-	 * a scaling needs to be applied here.
-	 */
-	charge_set_input_current_limit(icl, charge_mv);
+	raa489000_set_output_current(port, rp);
 }
 
 /* Sensors */
@@ -330,21 +609,109 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrices to rotate accelerometers into the standard reference. */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+/* Matrices to rotate accelerometers into the magister reference. */
+static const mat33_fp_t lid_magister_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
+
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					      { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
 
+/* BMA253 private data */
 static struct accelgyro_saved_data_t g_bma253_data;
+
+/* BMI160 private data */
 static struct bmi_drv_data_t g_bmi160_data;
 
+#ifdef BOARD_MAGOLOR
+static const mat33_fp_t base_icm_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					 { 0, FLOAT_TO_FP(1), 0 },
+					 { 0, 0, FLOAT_TO_FP(-1) } };
+
+/* ICM426 private data */
+static struct icm_drv_data_t g_icm426xx_data;
+/* KX022 private data */
+static struct kionix_accel_data g_kx022_data;
+
+struct motion_sensor_t kx022_lid_accel = {
+	.name = "Lid Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_KX022,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_LID,
+	.drv = &kionix_accel_drv,
+	.mutex = &g_lid_mutex,
+	.drv_data = &g_kx022_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = KX022_ADDR0_FLAGS,
+	.rot_standard_ref = &lid_standard_ref,
+	.min_frequency = KX022_ACCEL_MIN_FREQ,
+	.max_frequency = KX022_ACCEL_MAX_FREQ,
+	.default_range = 2, /* g, to support tablet mode */
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	},
+};
+
+struct motion_sensor_t icm426xx_base_accel = {
+	.name = "Base Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
+	.rot_standard_ref = &base_icm_ref,
+	.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
+	.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 13000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+	},
+};
+
+struct motion_sensor_t icm426xx_base_gyro = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &base_icm_ref,
+	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
+	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
+};
+#endif
+
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
 		.name = "Lid Accel",
@@ -414,31 +781,180 @@ struct motion_sensor_t motion_sensors[] = {
 	},
 };
 
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
+/**
+ * Handle debounced pen input changing state.
+ */
+static void pendetect_deferred(void)
 {
-	/*
-	 * Early boards need different constants due to a change in charger IC
-	 * silicon revision.
-	 */
-	if (system_get_board_version() >= 0) {
-		*kp = 1;
-		*kp_div = 128;
-		*ki = 1;
-		*ki_div = 1024;
-		*kd = 0;
-		*kd_div = 1;
+	int pen_charge_enable = !gpio_get_level(GPIO_PEN_DET_ODL) &&
+				!chipset_in_state(CHIPSET_STATE_ANY_OFF);
+
+	if (pen_charge_enable)
+		gpio_set_level(GPIO_EN_PP5000_PEN, 1);
+	else
+		gpio_set_level(GPIO_EN_PP5000_PEN, 0);
+
+	CPRINTS("Pen charge %sable", pen_charge_enable ? "en" : "dis");
+}
+DECLARE_DEFERRED(pendetect_deferred);
+
+void pen_detect_interrupt(enum gpio_signal signal)
+{
+	/* pen input debounce time */
+	hook_call_deferred(&pendetect_deferred_data, (100 * MSEC));
+}
+
+static void pen_charge_check(void)
+{
+	if (get_cbi_fw_config_stylus() == STYLUS_PRESENT)
+		hook_call_deferred(&pendetect_deferred_data, (100 * MSEC));
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, pen_charge_check, HOOK_PRIO_LAST);
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, pen_charge_check, HOOK_PRIO_LAST);
+
+/*****************************************************************************
+ * USB-C MUX/Retimer dynamic configuration
+ */
+struct usb_mux usbc1_mux0 = {
+	.usb_port = 1,
+	.i2c_port = I2C_PORT_SUB_USB_C1,
+	.i2c_addr_flags = PS8802_I2C_ADDR_FLAGS_CUSTOM,
+	.driver = &ps8802_usb_mux_driver,
+};
+
+static void setup_mux(void)
+{
+	if (get_cbi_ssfc_usb_mux() == SSFC_USBMUX_PS8743) {
+		usbc1_mux0.i2c_addr_flags = PS8743_I2C_ADDR0_FLAG;
+		usbc1_mux0.driver = &ps8743_usb_mux_driver;
+		ccprints("PS8743 USB MUX");
+	} else
+		ccprints("PS8762 USB MUX");
+}
+
+void board_init(void)
+{
+	int on;
+
+	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
+	check_c0_line();
+
+	if (get_cbi_fw_config_db() == DB_1A_HDMI) {
+		/* Disable i2c on HDMI pins */
+		gpio_config_pin(MODULE_I2C, GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL,
+				0);
+		gpio_config_pin(MODULE_I2C, GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL,
+				0);
+
+		/* Set HDMI and sub-rail enables to output */
+		gpio_set_flags(GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL,
+			       chipset_in_state(CHIPSET_STATE_ON) ?
+				       GPIO_ODR_LOW :
+				       GPIO_ODR_HIGH);
+		gpio_set_flags(GPIO_SUB_C1_INT_EN_RAILS_ODL, GPIO_ODR_HIGH);
+
+		/* Select HDMI option */
+		gpio_set_level(GPIO_HDMI_SEL_L, 0);
+
+		/* Enable interrupt for passing through HPD */
+		gpio_enable_interrupt(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL);
+
+	} else {
+		/* Set SDA as an input */
+		gpio_set_flags(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL, GPIO_INPUT);
+
+		/* Enable C1 interrupt and check if it needs processing */
+		gpio_enable_interrupt(GPIO_SUB_C1_INT_EN_RAILS_ODL);
+		check_c1_line();
+	}
+
+	setup_mux();
+
+	/* Enable gpio interrupt for base accelgyro sensor */
+	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
+	if (get_cbi_fw_config_tablet_mode()) {
+#ifdef BOARD_MAGOLOR
+		if (get_cbi_ssfc_base_sensor() == SSFC_SENSOR_ICM426XX) {
+			motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
+			motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
+			ccprints("BASE GYRO is ICM426XX");
+		} else
+			ccprints("BASE GYRO is BMI160");
+
+		if (get_cbi_ssfc_lid_sensor() == SSFC_SENSOR_KX022) {
+			motion_sensors[LID_ACCEL] = kx022_lid_accel;
+			ccprints("LID_ACCEL is KX022");
+		} else {
+			if (system_get_board_version() >= 5) {
+				motion_sensors[LID_ACCEL].rot_standard_ref =
+					&lid_magister_ref;
+			}
+			ccprints("LID_ACCEL is BMA253");
+		}
+#endif
+		motion_sensor_count = ARRAY_SIZE(motion_sensors);
+		/* Enable gpio interrupt for base accelgyro sensor */
+		gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
+	} else {
+		motion_sensor_count = 0;
+		gmr_tablet_switch_disable();
+		/* Base accel is not stuffed, don't allow line to float */
+		gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L,
+			       GPIO_INPUT | GPIO_PULL_DOWN);
+	}
+
+	if (get_cbi_fw_config_stylus() == STYLUS_PRESENT) {
+		gpio_enable_interrupt(GPIO_PEN_DET_ODL);
+		/* Make sure pen detection is triggered or not at sysjump */
+		pen_charge_check();
 	} else {
-		*kp = 1;
-		*kp_div = 4;
-		*ki = 1;
-		*ki_div = 15;
-		*kd = 1;
-		*kd_div = 10;
+		gpio_disable_interrupt(GPIO_PEN_DET_ODL);
+		gpio_set_flags(GPIO_PEN_DET_ODL, GPIO_INPUT | GPIO_PULL_DOWN);
 	}
+
+	/* Turn on 5V if the system is on, otherwise turn it off. */
+	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
+			      CHIPSET_STATE_SOFT_OFF);
+	board_power_5v_enable(on);
+
+	/* Initialize THERMAL */
+	setup_thermal();
+
+#ifdef BOARD_MAGOLOR
+	/* Support Keyboard Pad */
+	board_update_no_keypad_by_fwconfig();
+#endif
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+void motion_interrupt(enum gpio_signal signal)
+{
+#ifdef BOARD_MAGOLOR
+	switch (get_cbi_ssfc_base_sensor()) {
+	case SSFC_SENSOR_ICM426XX:
+		icm426xx_interrupt(signal);
+		break;
+	case SSFC_SENSOR_BMI160:
+	default:
+		bmi160_interrupt(signal);
+		break;
+	}
+#else
+	bmi160_interrupt(signal);
+#endif
+}
+
+__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+				       int *ki_div, int *kd, int *kd_div)
+{
+	*kp = 1;
+	*kp_div = 20;
+	*ki = 1;
+	*ki_div = 250;
+	*kd = 0;
+	*kd_div = 1;
 }
 
 int pd_snk_is_vbus_provided(int port)
@@ -507,25 +1023,17 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usbc1_retimer = {
-	.usb_port = 1,
-	.i2c_port = I2C_PORT_SUB_USB_C1,
-	.i2c_addr_flags = NB7V904M_I2C_ADDR0,
-	.driver = &nb7v904m_usb_redriver_drv,
-};
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
-		.driver = &pi3usb3x532_usb_mux_driver,
+struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	[USBC_PORT_C0] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = 0,
+			.i2c_port = I2C_PORT_USB_C0,
+			.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
+			.driver = &pi3usb3x532_usb_mux_driver,
+		},
 	},
-	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PS8802_I2C_ADDR_FLAGS,
-		.driver = &ps8802_usb_mux_driver,
+	[USBC_PORT_C1] = {
+		.mux = &usbc1_mux0,
 	}
 };
 
@@ -550,7 +1058,8 @@ uint16_t tcpc_get_alert_status(void)
 		}
 	}
 
-	if (!gpio_get_level(GPIO_SUB_USB_C1_INT_ODL)) {
+	if (board_get_usb_pd_port_count() > 1 &&
+	    !gpio_get_level(GPIO_SUB_C1_INT_EN_RAILS_ODL)) {
 		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
 			/* TCPCI spec Rev 1.0 says to ignore bits 14:12. */
 			if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0))
@@ -586,24 +1095,24 @@ static void adc_vol_key_press_check(void)
 	static uint8_t old_adc_key_state;
 	uint8_t adc_key_state_change;
 
-	if (volt > 2400 && volt < 2490) {
+	if (volt > 2400 && volt < 2540) {
 		/* volume-up is pressed */
 		new_adc_key_state = ADC_VOL_UP_MASK;
-	} else if (volt > 2600 && volt < 2690) {
+	} else if (volt > 2600 && volt < 2740) {
 		/* volume-down is pressed */
 		new_adc_key_state = ADC_VOL_DOWN_MASK;
-	} else if (volt < 2290) {
+	} else if (volt < 2300) {
 		/* both volumn-up and volume-down are pressed */
 		new_adc_key_state = ADC_VOL_UP_MASK | ADC_VOL_DOWN_MASK;
-	} else if (volt > 2700) {
+	} else if (volt > 2780) {
 		/* both volumn-up and volume-down are released */
 		new_adc_key_state = 0;
 	}
 	if (new_adc_key_state != old_adc_key_state) {
 		adc_key_state_change = old_adc_key_state ^ new_adc_key_state;
-		if (adc_key_state_change && ADC_VOL_UP_MASK)
+		if (adc_key_state_change & ADC_VOL_UP_MASK)
 			button_interrupt(GPIO_VOLUME_UP_L);
-		if (adc_key_state_change && ADC_VOL_DOWN_MASK)
+		if (adc_key_state_change & ADC_VOL_DOWN_MASK)
 			button_interrupt(GPIO_VOLUME_DOWN_L);
 
 		old_adc_key_state = new_adc_key_state;
@@ -611,9 +1120,8 @@ static void adc_vol_key_press_check(void)
 }
 DECLARE_HOOK(HOOK_TICK, adc_vol_key_press_check, HOOK_PRIO_DEFAULT);
 
-#ifndef TEST_BUILD
 /* This callback disables keyboard when convertibles are fully open */
-void lid_angle_peripheral_enable(int enable)
+__override void lid_angle_peripheral_enable(int enable)
 {
 	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
 
@@ -637,4 +1145,16 @@ void lid_angle_peripheral_enable(int enable)
 			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
 	}
 }
-#endif
+
+__override int board_get_leave_safe_mode_delay_ms(void)
+{
+	const struct fuel_gauge_info *const fuel_gauge =
+		&get_batt_params()->fuel_gauge;
+
+	/* If it's COSMX battery, there's need more delay time. */
+	if (!strcasecmp(fuel_gauge->manuf_name, "COSMX KT0030B002") ||
+	    !strcasecmp(fuel_gauge->manuf_name, "COSMX KT0030B004"))
+		return 2000;
+	else
+		return 500;
+}
diff --git a/board/magolor/board.h b/board/magolor/board.h
index 2fb9f30908..07ddf79744 100644
--- a/board/magolor/board.h
+++ b/board/magolor/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,31 +12,55 @@
 #include "baseboard.h"
 
 #define CONFIG_USB_PD_DEBUG_LEVEL 2
+
+#ifdef BOARD_MAGOLOR_LEGACY
 /* this change saves 1656 bytes of RW flash space */
 #define CONFIG_CHIP_INIT_ROM_REGION
-
+#define CONFIG_DEBUG_ASSERT_BRIEF
+#else
 /*
- * Keep the system unlocked in early development.
- * TODO(b/151264302): Make sure to remove this before production!
+ * The RAM and flash size combination on the the NPCX797FC does not leave
+ * any unused flash space that can be used to store the .init_rom section.
  */
-#define CONFIG_SYSTEM_UNLOCKED
+#undef CONFIG_CHIP_INIT_ROM_REGION
+#endif
+
+/* Remove default commands to free flash space */
+#undef CONFIG_CMD_ACCELSPOOF
+#undef CONFIG_CMD_BATTFAKE
 
 /* Battery */
 #define CONFIG_BATTERY_FUEL_GAUGE
 
 /* Charger */
 #define CONFIG_CHARGER_RAA489000
+#define PD_MAX_VOLTAGE_MV 20000
 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 #define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */
+#define CONFIG_OCPC_DEF_RBATT_MOHMS               \
+	22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \
+	    */
 #define CONFIG_OCPC
-#undef  CONFIG_CHARGER_SINGLE_CHIP
+#undef CONFIG_CHARGER_SINGLE_CHIP
 #undef CONFIG_CMD_CHARGER_DUMP
+#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
+#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
+/*
+ * b/147463641: The charger IC seems to overdraw ~4%, therefore we
+ * reduce our target accordingly.
+ */
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 4
 
 /* GPIO for C1 interrupts, for baseboard use */
-#define GPIO_USB_C1_INT_ODL GPIO_SUB_USB_C1_INT_ODL
+#define GPIO_USB_C1_INT_ODL GPIO_SUB_C1_INT_EN_RAILS_ODL
 
 /* Keyboard */
+#define CONFIG_KEYBOARD_FACTORY_TEST
+#ifdef BOARD_MAGOLOR
+
+#define CONFIG_KEYBOARD_KEYPAD
+#endif
 #define CONFIG_PWM_KBLIGHT
 
 /* LED defines */
@@ -44,7 +68,7 @@
 
 /* PWM */
 #define CONFIG_PWM
-#define NPCX7_PWM1_SEL    1  /* GPIO C2 is used as PWM1. */
+#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */
 
 /* Temp sensor */
 #define CONFIG_TEMP_SENSOR
@@ -54,8 +78,9 @@
 
 /* USB */
 #define CONFIG_BC12_DETECT_PI3USB9201
-#define CONFIG_USBC_RETIMER_NB7V904M
 #define CONFIG_USBC_RETIMER_PS8802
+#define CONFIG_USB_MUX_PS8743
+#define CONFIG_USB_MUX_RUNTIME_CONFIG
 
 /* Common USB-A defines */
 #define USB_PORT_COUNT 2
@@ -82,36 +107,55 @@
 #define CONFIG_USB_PD_5V_EN_CUSTOM
 
 /* I2C configuration */
-#define I2C_PORT_EEPROM     NPCX_I2C_PORT7_0
-#define I2C_PORT_BATTERY    NPCX_I2C_PORT5_0
-#define I2C_PORT_SENSOR     NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0     NPCX_I2C_PORT1_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
 #define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_MUX    I2C_PORT_USB_C0
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0
 /* TODO(b:147440290): Need to handle multiple charger ICs */
-#define I2C_PORT_CHARGER    I2C_PORT_USB_C0
+#define I2C_PORT_CHARGER I2C_PORT_USB_C0
 
-#define I2C_PORT_ACCEL      I2C_PORT_SENSOR
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
 
 #define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */
 
+/*
+ * I2C pin names for baseboard
+ *
+ * Note: these lines will be set as i2c on start-up, but this should be
+ * okay since they're ODL.
+ */
+#define GPIO_EC_I2C_SUB_USB_C1_SCL GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL
+#define GPIO_EC_I2C_SUB_USB_C1_SDA GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL
+
 /* Sensors */
 #define CONFIG_CMD_ACCELS
 #define CONFIG_CMD_ACCEL_INFO
+#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
+
+#define CONFIG_ACCEL_BMA255 /* Lid accel */
+#define CONFIG_ACCELGYRO_BMI160 /* Base accel */
 
-#define CONFIG_ACCEL_BMA255		/* Lid accel */
-#define CONFIG_ACCELGYRO_BMI160		/* Base accel */
+#ifdef BOARD_MAGOLOR
+#define CONFIG_ACCEL_KX022 /* Lid accel */
+#define CONFIG_ACCELGYRO_ICM426XX /* Base accel second source*/
+#endif
 
 /* Lid operates in forced mode, base in FIFO */
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
 #define CONFIG_ACCEL_FIFO
-#define CONFIG_ACCEL_FIFO_SIZE 256	/* Must be a power of 2 */
+#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */
 #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
 
-#define CONFIG_ACCEL_INTERRUPTS
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 
+#ifdef BOARD_MAGOLOR
+#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+#endif
+
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_UPDATE
 #define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
@@ -121,9 +165,6 @@
 #define CONFIG_TABLET_MODE_SWITCH
 #define CONFIG_GMR_TABLET_MODE
 
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_GPIO
-
 /* Volume Button feature */
 #define CONFIG_ADC_BUTTONS
 #define CONFIG_VOLUME_BUTTONS
@@ -142,25 +183,16 @@ enum chg_id {
 };
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_1,     /* ADC0 */
-	ADC_TEMP_SENSOR_2,     /* ADC1 */
-	ADC_SUB_ANALOG,	       /* ADC2 */
-	ADC_VSNS_PP3300_A,     /* ADC9 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
+	ADC_SUB_ANALOG, /* ADC2 */
+	ADC_VSNS_PP3300_A, /* ADC9 */
 	ADC_CH_COUNT
 };
 
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_COUNT
-};
+enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT };
 
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
 enum pwm_channel {
 	PWM_CH_KBLIGHT,
@@ -168,11 +200,18 @@ enum pwm_channel {
 };
 
 enum battery_type {
+	BATTERY_AP19B8M,
+	BATTERY_AP18C7M,
 	BATTERY_LGC_AP18C8K,
 	BATTERY_MURATA_AP18C4K,
+	BATTERY_COSMX_AP20CBL,
+	BATTERY_COSMX_AP20CBL_004,
 	BATTERY_TYPE_COUNT,
 };
 
-int board_is_sourcing_vbus(int port);
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
+
+void motion_interrupt(enum gpio_signal signal);
+void pen_detect_interrupt(enum gpio_signal s);
 #endif /* !__ASSEMBLER__ */
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/magolor/build.mk b/board/magolor/build.mk
index 3cbadc55d7..c69e903608 100644
--- a/board/magolor/build.mk
+++ b/board/magolor/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -8,7 +8,13 @@
 
 CHIP:=npcx
 CHIP_FAMILY:=npcx7
+# A limited Magolor_legacy boards are reworked with NPCX796FC variant.
+# Set the modify the variant type to match.
+ifeq ($(BOARD),magolor_legacy)
 CHIP_VARIANT:=npcx7m6fc
+else
+CHIP_VARIANT:=npcx7m7fc
+endif
 BASEBOARD:=dedede
 
-board-y=board.o battery.o led.o usb_pd_policy.o
+board-y=board.o battery.o cbi_ssfc.o led.o usb_pd_policy.o
diff --git a/board/magolor/cbi_ssfc.c b/board/magolor/cbi_ssfc.c
new file mode 100644
index 0000000000..155ecae6bf
--- /dev/null
+++ b/board/magolor/cbi_ssfc.c
@@ -0,0 +1,41 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi_ssfc.h"
+#include "common.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "hooks.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+/* Cache SSFC on init since we don't expect it to change in runtime */
+static union dedede_cbi_ssfc cached_ssfc;
+BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
+
+static void cbi_ssfc_init(void)
+{
+	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
+		/* Default to 0 when CBI isn't populated */
+		cached_ssfc.raw_value = 0;
+
+	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
+}
+DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
+
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
+{
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
+}
+
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
+{
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
+}
+
+enum ec_ssfc_usb_mux get_cbi_ssfc_usb_mux(void)
+{
+	return (enum ec_ssfc_usb_mux)cached_ssfc.usb_mux;
+}
diff --git a/board/magolor/cbi_ssfc.h b/board/magolor/cbi_ssfc.h
new file mode 100644
index 0000000000..78e32f5810
--- /dev/null
+++ b/board/magolor/cbi_ssfc.h
@@ -0,0 +1,80 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _DEDEDE_CBI_SSFC__H_
+#define _DEDEDE_CBI_SSFC__H_
+
+#include "stdint.h"
+
+/****************************************************************************
+ * Dedede CBI Second Source Factory Cache
+ */
+
+/*
+ * Base Sensor (Bits 0-2)
+ */
+enum ec_ssfc_base_sensor {
+	SSFC_SENSOR_BASE_DEFAULT = 0,
+	SSFC_SENSOR_BMI160 = 1,
+	SSFC_SENSOR_ICM426XX = 2,
+	SSFC_SENSOR_LSM6DSM = 3,
+	SSFC_SENSOR_ICM42607 = 4
+};
+
+/*
+ * Lid Sensor (Bits 3-5)
+ */
+enum ec_ssfc_lid_sensor {
+	SSFC_SENSOR_LID_DEFAULT = 0,
+	SSFC_SENSOR_BMA255 = 1,
+	SSFC_SENSOR_KX022 = 2,
+	SSFC_SENSOR_LIS2DWL = 3
+};
+
+/*
+ * Usb Mux (Bits 20-21)
+ */
+enum ec_ssfc_usb_mux {
+	SSFC_USBMUX_PS8762 = 0,
+	SSFC_USBMUX_PS8743 = 1,
+};
+
+union dedede_cbi_ssfc {
+	struct {
+		uint32_t base_sensor : 3;
+		uint32_t lid_sensor : 3;
+		uint32_t cam_wfc : 3;
+		uint32_t cam_ufc : 2;
+		uint32_t cam_vcm : 2;
+		uint32_t TS_Source : 4;
+		uint32_t AUDIO_CODEC_SOURCE : 3;
+		uint32_t usb_mux : 2;
+		uint32_t reserved_2 : 10;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Get the Base sensor type from SSFC_CONFIG.
+ *
+ * @return the Base sensor board type.
+ */
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
+
+/**
+ * Get the Lid sensor type from SSFC_CONFIG.
+ *
+ * @return the Lid sensor board type.
+ */
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
+
+/**
+ * Get the Usb Mux type from SSFC_CONFIG.
+ *
+ * @return the Usb Mux board type.
+ */
+enum ec_ssfc_usb_mux get_cbi_ssfc_usb_mux(void);
+
+#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/magolor/ec.tasklist b/board/magolor/ec.tasklist
index 0aba1fabeb..ba5855412d 100644
--- a/board/magolor/ec.tasklist
+++ b/board/magolor/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/magolor/gpio.inc b/board/magolor/gpio.inc
index 68861fa7f7..77cf523de1 100644
--- a/board/magolor/gpio.inc
+++ b/board/magolor/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,7 +26,8 @@ GPIO_INT(PG_PP1050_ST_OD,	 PIN(4, 2), GPIO_INT_BOTH, power_signal_interrupt)
 
 /* USB-C interrupts */
 GPIO_INT(USB_C0_INT_ODL,	 PIN(6, 2), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt)
-GPIO_INT(SUB_USB_C1_INT_ODL,	 PIN(F, 5), GPIO_INT_FALLING | GPIO_PULL_UP, sub_usb_c1_interrupt)
+GPIO_INT(SUB_C1_INT_EN_RAILS_ODL,	PIN(F, 5), GPIO_INT_FALLING | GPIO_PULL_UP, sub_usb_c1_interrupt) /* C1 interrupt OR 5V power en */
+GPIO_INT(EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL,	PIN(9, 1), GPIO_INT_BOTH, sub_hdmi_hpd_interrupt) /* C1 I2C SDA OR HDMI_HPD */
 
 /* Button interrupts */
 GPIO_INT(H1_EC_PWR_BTN_ODL,	 PIN(0, 1), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
@@ -34,8 +35,9 @@ GPIO_INT(H1_EC_PWR_BTN_ODL,	 PIN(0, 1), GPIO_INT_BOTH | GPIO_PULL_UP, power_butt
 /* Other interrupts */
 GPIO_INT(LID_OPEN,		 PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)
 GPIO_INT(EC_WP_OD,		 PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(BASE_SIXAXIS_INT_L,	 PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, bmi160_interrupt)
+GPIO_INT(BASE_SIXAXIS_INT_L,	 PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, motion_interrupt)
 GPIO_INT(LID_360_L,		 PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
+GPIO_INT(PEN_DET_ODL,            PIN(5, 0), GPIO_INT_BOTH, pen_detect_interrupt)
 
 /* I2C Ports */
 GPIO(EC_I2C_EEPROM_SCL,	      PIN(B, 3), GPIO_INPUT)
@@ -46,8 +48,7 @@ GPIO(EC_I2C_SENSOR_SCL,	      PIN(B, 5), GPIO_INPUT)
 GPIO(EC_I2C_SENSOR_SDA,	      PIN(B, 4), GPIO_INPUT)
 GPIO(EC_I2C_USB_C0_SCL,	      PIN(9, 0), GPIO_INPUT)
 GPIO(EC_I2C_USB_C0_SDA,	      PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C_SUB_USB_C1_SCL,   PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C_SUB_USB_C1_SDA,   PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_SUB_C1_SCL_HDMI_EN_ODL,	PIN(9, 2), GPIO_INPUT) /* C1 I2C SCL OR HDMI en */
 
 /* Extra Sub-board I/O pins */
 
@@ -57,14 +58,14 @@ GPIO(EC_SUB_IO_2,  PIN(3, 4), GPIO_OUT_LOW)
 GPIO(EN_VCCIO_EXT,   PIN(6, 1), GPIO_OUT_LOW)
 /* TODO(b:149775160) - Modify if needed if we ever use this signal. */
 GPIO(EN_VCCST,		PIN(A, 7), GPIO_INPUT)
-GPIO(EN_PP3300_PEN,	PIN(6, 3), GPIO_OUT_LOW)
+GPIO(EN_PP5000_PEN,	PIN(6, 3), GPIO_OUT_LOW)
 GPIO(EN_PP3300_A,	PIN(0, 3), GPIO_OUT_LOW)
 GPIO(EN_PP5000_U,	PIN(A, 4), GPIO_OUT_LOW)
 GPIO(EN_SLP_Z,		PIN(8, 3), GPIO_OUT_LOW)
 GPIO(EN_KB_BL,		PIN(6, 0), GPIO_OUT_LOW)
 GPIO(EN_BL_OD,		PIN(D, 3), GPIO_ODR_LOW)
-GPIO(IMVP9_PE,		PIN(E, 0), GPIO_OUT_LOW)
 GPIO(ECH1_PACKET_MODE,	PIN(7, 5), GPIO_OUT_LOW)
+GPIO(EC_VIVALDIKEYBOARD_ID,	PIN(4, 0), GPIO_INPUT + GPIO_PULL_DOWN)	/* keyboard ID */
 
 /* LED */
 GPIO(LED_B_ODL,                  PIN(C, 2), GPIO_OUT_HIGH)        /* PWM_CH_LED2_BLUE */
@@ -86,7 +87,7 @@ GPIO(EC_PROCHOT_ODL,	     PIN(F, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
 GPIO(EC_ENTERING_RW,	     PIN(E, 3), GPIO_OUT_LOW)
 GPIO(ALL_SYS_PWRGD,	     PIN(A, 0), GPIO_OUT_LOW)
 GPIO(SYS_RST_ODL,	     PIN(C, 5), GPIO_ODR_HIGH)
-GPIO(CCD_MODE_ODL,	     PIN(E, 5), GPIO_INPUT)
+GPIO(CCD_MODE_ODL,	     PIN(E, 5), GPIO_ODR_HIGH)
 
 /* USB pins */
 GPIO(USB_C0_RST_ODL,	     PIN(9, 7), GPIO_OUT_HIGH) /* currently unused */
@@ -133,3 +134,15 @@ ALTERNATE(PIN_MASK(B, 0x3C), 0, MODULE_I2C, 0)   /* I2C7,I2C0 */
 ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)   /* I2C5 */
 ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)   /* I2C2, I2C1 SCL */
 ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)   /* I2C1 SDA */
+
+/* NC pins, enable internal pull-up to avoid floating state. */
+GPIO(GPIO32_NC, PIN(3, 2), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO35_NC, PIN(3, 5), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO57_NC, PIN(5, 7), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO81_NC, PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO86_NC, PIN(8, 6), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOD0_NC, PIN(D, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOD1_NC, PIN(D, 1), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOD6_NC, PIN(D, 6), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOE0_NC, PIN(E, 0), GPIO_INPUT | GPIO_PULL_UP)
diff --git a/board/magolor/led.c b/board/magolor/led.c
index e682e5fd48..2076532142 100644
--- a/board/magolor/led.c
+++ b/board/magolor/led.c
@@ -1,44 +1,50 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Power and battery LED control for Magolor
  */
 
+#include "chipset.h"
 #include "ec_commands.h"
 #include "gpio.h"
 #include "led_common.h"
 #include "led_onoff_states.h"
-#include "chipset.h"
 
 #define LED_ON_LVL 0
 #define LED_OFF_LVL 1
 
-const int led_charge_lvl_1 = 5;
+__override const int led_charge_lvl_1 = 5;
 
-const int led_charge_lvl_2 = 95;
+__override const int led_charge_lvl_2 = 95;
 
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-void led_set_color_battery(enum ec_led_colors color)
+__override void led_set_color_battery(enum ec_led_colors color)
 {
 	switch (color) {
 	case EC_LED_COLOR_AMBER:
diff --git a/board/magolor/usb_pd_policy.c b/board/magolor/usb_pd_policy.c
index bcdf8300c5..2bad4d6931 100644
--- a/board/magolor/usb_pd_policy.c
+++ b/board/magolor/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,11 +7,12 @@
 #include "chipset.h"
 #include "common.h"
 #include "console.h"
+#include "driver/charger/isl923x_public.h"
 #include "driver/tcpm/tcpci.h"
 #include "usb_pd.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
@@ -24,11 +25,6 @@ void pd_power_supply_reset(int port)
 	/* Disable VBUS */
 	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
 
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	/* Give back the current quota we are no longer using */
-	charge_manager_source_port(port, 0);
-#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
-
 	/* Notify host of power info change. */
 	pd_send_host_event(PD_EVENT_POWER_CHANGE);
 }
@@ -54,10 +50,9 @@ int pd_set_power_supply_ready(int port)
 	if (rv)
 		return rv;
 
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	/* Ensure we advertise the proper available current quota */
-	charge_manager_source_port(port, 1);
-#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
+	rv = raa489000_enable_asgate(port, true);
+	if (rv)
+		return rv;
 
 	/* Notify host of power info change. */
 	pd_send_host_event(PD_EVENT_POWER_CHANGE);
diff --git a/board/magolor/vif_override.xml b/board/magolor/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/magolor/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/makomo/battery.c b/board/makomo/battery.c
new file mode 100644
index 0000000000..1f5be3dbe3
--- /dev/null
+++ b/board/makomo/battery.c
@@ -0,0 +1,104 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "battery_fuel_gauge.h"
+#include "gpio.h"
+
+const struct board_batt_params board_battery_info[] = {
+	/* LGC L20L3PG2, Gauge IC: RAJ240047A20DNP. */
+	[BATTERY_LGC] = {
+		.fuel_gauge = {
+			.manuf_name = "LGC",
+			.device_name = "L20L3PG2",
+			.ship_mode = {
+				.reg_addr = 0x34,
+				.reg_data = { 0x0000, 0x1000 },
+			},
+			.fet = {
+				.reg_addr = 0x34,
+				.reg_mask = 0x0100,
+				.disconnect_val = 0x0100,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13050,   /* mV */
+			.voltage_normal		= 11400,   /* mV */
+			.voltage_min		= 9000,    /* mV */
+			.precharge_current	= 256,     /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 73,
+		},
+	},
+	/* Sunwoda L20D3PG2, Gauge IC: BQ40Z697A. */
+	[BATTERY_SUNWODA] = {
+		.fuel_gauge = {
+			.manuf_name = "Sunwoda",
+			.device_name = "L20D3PG2",
+			.ship_mode = {
+				.reg_addr = 0x34,
+				.reg_data = { 0x0000, 0x1000 },
+			},
+			.fet = {
+				.reg_addr = 0x34,
+				.reg_mask = 0x0100,
+				.disconnect_val = 0x0100,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13050, /* mV */
+			.voltage_normal		= 11250, /* mV */
+			.voltage_min		= 9000,  /* mV */
+			.precharge_current	= 200,	 /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 60,
+		},
+	},
+
+	/* SIMPLO L20M3PG2, Gauge IC: BQ40Z697A. */
+	[BATTERY_SMP] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP",
+			.device_name = "L20M3PG2",
+			.ship_mode = {
+				.reg_addr = 0x34,
+				.reg_data = { 0x0000, 0x1000 },
+			},
+			.fet = {
+				.reg_addr = 0x34,
+				.reg_mask = 0x0100,
+				.disconnect_val = 0x0100,
+			},
+		},
+		.batt_info = {
+			.voltage_max		= 13050, /* mV */
+			.voltage_normal		= 11250, /* mV */
+			.voltage_min		= 9000,  /* mV */
+			.precharge_current	= 256,   /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 45,
+			.charging_min_c		= 0,
+			.charging_max_c		= 45,
+			.discharging_min_c	= -40,
+			.discharging_max_c	= 73,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_LGC;
+
+enum battery_present battery_hw_present(void)
+{
+	return gpio_get_level(GPIO_EC_BATT_PRES_ODL) ? BP_NO : BP_YES;
+}
diff --git a/board/makomo/board.c b/board/makomo/board.c
new file mode 100644
index 0000000000..ff6a8c19d5
--- /dev/null
+++ b/board/makomo/board.c
@@ -0,0 +1,579 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc.h"
+#include "backlight.h"
+#include "button.h"
+#include "charge_manager.h"
+#include "charge_ramp.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "driver/accel_lis2dw12.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "driver/battery/max17055.h"
+#include "driver/bc12/pi3usb9201.h"
+#include "driver/charger/isl923x.h"
+#include "driver/tcpm/fusb302.h"
+#include "driver/usb_mux/it5205.h"
+#include "ec_commands.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "i2c.h"
+#include "i2c_bitbang.h"
+#include "it8801.h"
+#include "keyboard_backlight.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "panic.h"
+#include "power.h"
+#include "power_button.h"
+#include "registers.h"
+#include "spi.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "tcpm/tcpm.h"
+#include "timer.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd_tcpm.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+static void tcpc_alert_event(enum gpio_signal signal)
+{
+	schedule_deferred_pd_interrupt(0 /* port */);
+}
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/******************************************************************************/
+/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
+const struct adc_t adc_channels[] = {
+	[ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(10) },
+	[ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8) },
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/******************************************************************************/
+/* I2C ports */
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "typec",
+	  .port = 0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "other",
+	  .port = 1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+const struct i2c_port_t i2c_bitbang_ports[] = {
+	{ .name = "battery",
+	  .port = 2,
+	  .kbps = 100,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA,
+	  .drv = &bitbang_drv },
+};
+const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
+
+#define BC12_I2C_ADDR PI3USB9201_I2C_ADDR_3
+
+/* power signal list.  Must match order of enum power_signal. */
+const struct power_signal_info power_signal_list[] = {
+	{ GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" },
+	{ GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" },
+};
+BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/*
+	 * TODO(b/133200075): Tune this once we have the final performance
+	 * out of the driver and the i2c bus.
+	 */
+	.output_settle_us = 35,
+	.debounce_down_us = 5 * MSEC,
+	.debounce_up_us = 40 * MSEC,
+	.scan_period_us = 10 * MSEC,
+	.min_post_scan_delay_us = 10 * MSEC,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
+		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
+	},
+};
+
+struct ioexpander_config_t ioex_config[CONFIG_IO_EXPANDER_PORT_COUNT] = {
+	[0] = {
+		.i2c_host_port = I2C_PORT_KB_DISCRETE,
+		.i2c_addr_flags = IT8801_I2C_ADDR1,
+		.drv = &it8801_ioexpander_drv,
+	},
+};
+
+/******************************************************************************/
+/* SPI devices */
+const struct spi_device_t spi_devices[] = {
+	{ CONFIG_SPI_ACCEL_PORT, 2, GPIO_EC_SENSOR_SPI_NSS },
+};
+const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
+
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	{
+		.i2c_port = I2C_PORT_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+};
+
+/******************************************************************************/
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TCPC0,
+			.addr_flags = FUSB302_I2C_ADDR_FLAGS,
+		},
+		.drv = &fusb302_tcpm_drv,
+	},
+};
+
+static void board_hpd_status(const struct usb_mux *me, mux_state_t mux_state,
+			     bool *ack_required)
+{
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
+	/*
+	 * svdm_dp_attention() did most of the work, we only need to notify
+	 * host here.
+	 */
+	host_set_single_event(EC_HOST_EVENT_USB_MUX);
+}
+
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+				.hpd_update = &board_hpd_status,
+			},
+	},
+};
+
+/* Charger config.  Start i2c address at 1, update during runtime */
+struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = 1,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+};
+
+/* Board version depends on ADCs, so init i2c port after ADC */
+static void charger_config_complete(void)
+{
+	chg_chips[0].i2c_port = board_get_charger_i2c();
+}
+DECLARE_HOOK(HOOK_INIT, charger_config_complete, HOOK_PRIO_INIT_ADC + 1);
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
+		status |= PD_STATUS_TCPC_ALERT_0;
+
+	return status;
+}
+
+static int force_discharge;
+
+int board_set_active_charge_port(int charge_port)
+{
+	CPRINTS("New chg p%d", charge_port);
+
+	/* ignore all request when discharge mode is on */
+	if (force_discharge && charge_port != CHARGE_PORT_NONE)
+		return EC_SUCCESS;
+
+	switch (charge_port) {
+	case CHARGE_PORT_USB_C:
+		/* Don't charge from a source port */
+		if (board_vbus_source_enabled(charge_port))
+			return -1;
+		break;
+	default:
+		/*
+		 * To ensure the fuel gauge (max17055) is always powered
+		 * even when battery is disconnected, keep VBAT rail on but
+		 * set the charging current to minimum.
+		 */
+		charger_set_current(CHARGER_SOLO, 0);
+		break;
+	}
+
+	return EC_SUCCESS;
+}
+
+int board_discharge_on_ac(int enable)
+{
+	int ret, port;
+
+	if (enable) {
+		port = CHARGE_PORT_NONE;
+	} else {
+		/* restore the charge port state */
+		port = charge_manager_get_override();
+		if (port == OVERRIDE_OFF)
+			port = charge_manager_get_active_charge_port();
+	}
+
+	ret = charger_discharge_on_ac(enable);
+	if (ret)
+		return ret;
+
+	force_discharge = enable;
+	return board_set_active_charge_port(port);
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	/* TODO(b:138352732): read IT8801 GPIO EN_USBC_CHARGE_L */
+	return EC_ERROR_UNIMPLEMENTED;
+}
+
+void bc12_interrupt(enum gpio_signal signal)
+{
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+
+#ifndef VARIANT_KUKUI_NO_SENSORS
+static void board_spi_enable(void)
+{
+	/*
+	 * Pin mux spi peripheral away from emmc, since RO might have
+	 * left them there.
+	 */
+	gpio_config_module(MODULE_SPI_FLASH, 0);
+
+	/* Enable clocks to SPI2 module. */
+	STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
+
+	/* Reset SPI2 to clear state left over from the emmc slave. */
+	STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2;
+	STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
+
+	/* Reinitialize spi peripheral. */
+	spi_enable(&spi_devices[0], 1);
+
+	/* Pin mux spi peripheral toward the sensor. */
+	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_spi_enable,
+	     MOTION_SENSE_HOOK_PRIO - 1);
+
+static void board_spi_disable(void)
+{
+	/* Set pins to a state calming the sensor down. */
+	gpio_set_flags(GPIO_EC_SENSOR_SPI_CK, GPIO_OUT_LOW);
+	gpio_set_level(GPIO_EC_SENSOR_SPI_CK, 0);
+	gpio_config_module(MODULE_SPI_CONTROLLER, 0);
+
+	/* Disable spi peripheral and clocks. */
+	spi_enable(&spi_devices[0], 0);
+	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_spi_disable,
+	     MOTION_SENSE_HOOK_PRIO + 1);
+#endif /* !VARIANT_KUKUI_NO_SENSORS */
+
+static void board_init(void)
+{
+	/* If the reset cause is external, pulse PMIC force reset. */
+	if (system_get_reset_flags() == EC_RESET_FLAG_RESET_PIN) {
+		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 0);
+		msleep(100);
+		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 1);
+	}
+
+	/* Enable TCPC alert interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
+
+#ifndef VARIANT_KUKUI_NO_SENSORS
+	/* Enable interrupts from BMI160 sensor. */
+	gpio_enable_interrupt(GPIO_ACCEL_INT_ODL);
+
+	/* For some reason we have to do this again in case of sysjump */
+	board_spi_enable();
+#endif /* !VARIANT_KUKUI_NO_SENSORS */
+
+	/* Enable interrupt from PMIC. */
+	gpio_enable_interrupt(GPIO_PMIC_EC_RESETB);
+
+	/* Enable BC12 interrupt */
+	gpio_enable_interrupt(GPIO_BC12_EC_INT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+#ifndef VARIANT_KUKUI_NO_SENSORS
+/* Motion sensors */
+/* Mutexes */
+static struct mutex g_lid_mutex;
+static struct mutex g_base_mutex;
+
+/* Rotation matrixes */
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					      { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
+
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, FLOAT_TO_FP(1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
+
+/* sensor private data */
+/* Lid accel private data */
+static struct stprivate_data g_lis2dwl_data;
+/* Base accel private data */
+static struct bmi_drv_data_t g_bmi160_data;
+
+struct motion_sensor_t motion_sensors[] = {
+	[LID_ACCEL] = {
+	 .name = "Lid Accel",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_LIS2DWL,
+	 .type = MOTIONSENSE_TYPE_ACCEL,
+	 .location = MOTIONSENSE_LOC_LID,
+	 .drv = &lis2dw12_drv,
+	 .mutex = &g_lid_mutex,
+	 .drv_data = &g_lis2dwl_data,
+	 .port = I2C_PORT_SENSORS,
+	 .i2c_spi_addr_flags = LIS2DWL_ADDR1_FLAGS,
+	 .rot_standard_ref = &lid_standard_ref,
+	 .default_range = 2, /* g */
+	 .min_frequency = LIS2DW12_ODR_MIN_VAL,
+	 .max_frequency = LIS2DW12_ODR_MAX_VAL,
+	 .config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 12500 | ROUND_UP_FLAG,
+		},
+		/* Sensor on for lid angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	 },
+	},
+	/*
+	 * Note: bmi160: supports accelerometer and gyro sensor
+	 * Requirement: accelerometer sensor must init before gyro sensor
+	 * DO NOT change the order of the following table.
+	 */
+	[BASE_ACCEL] = {
+	 .name = "Accel",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_BMI160,
+	 .type = MOTIONSENSE_TYPE_ACCEL,
+	 .location = MOTIONSENSE_LOC_BASE,
+	 .drv = &bmi160_drv,
+	 .mutex = &g_base_mutex,
+	 .drv_data = &g_bmi160_data,
+	 .port = CONFIG_SPI_ACCEL_PORT,
+	 .i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
+	 .rot_standard_ref = &base_standard_ref,
+	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
+	 .min_frequency = BMI_ACCEL_MIN_FREQ,
+	 .max_frequency = BMI_ACCEL_MAX_FREQ,
+	 .config = {
+		 /* EC use accel for angle detection */
+		 [SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		 },
+		 /* Sensor on for angle detection */
+		 [SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		 },
+	 },
+	},
+	[BASE_GYRO] = {
+	 .name = "Gyro",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_BMI160,
+	 .type = MOTIONSENSE_TYPE_GYRO,
+	 .location = MOTIONSENSE_LOC_BASE,
+	 .drv = &bmi160_drv,
+	 .mutex = &g_base_mutex,
+	 .drv_data = &g_bmi160_data,
+	 .port = CONFIG_SPI_ACCEL_PORT,
+	 .i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
+	 .default_range = 1000, /* dps */
+	 .rot_standard_ref = &base_standard_ref,
+	 .min_frequency = BMI_GYRO_MIN_FREQ,
+	 .max_frequency = BMI_GYRO_MAX_FREQ,
+	},
+};
+const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+const struct it8801_pwm_t it8801_pwm_channels[] = {
+	[IT8801_PWM_CH_KBLIGHT] = { .index = 4 },
+};
+
+void board_kblight_init(void)
+{
+	kblight_register(&kblight_it8801);
+}
+
+bool board_has_kb_backlight(void)
+{
+	/* Default enable keyboard backlight */
+	return true;
+}
+#endif /* !VARIANT_KUKUI_NO_SENSORS */
+
+/* Battery functions */
+#define SB_SMARTCHARGE 0x26
+/* Quick charge enable bit */
+#define SMART_QUICK_CHARGE 0x02
+/* Quick charge support bit */
+#define MODE_QUICK_CHARGE_SUPPORT 0x01
+
+static void sb_quick_charge_mode(int enable)
+{
+	int val, rv;
+
+	rv = sb_read(SB_SMARTCHARGE, &val);
+	if (rv || !(val & MODE_QUICK_CHARGE_SUPPORT))
+		return;
+
+	if (enable)
+		val |= SMART_QUICK_CHARGE;
+	else
+		val &= ~SMART_QUICK_CHARGE;
+
+	sb_write(SB_SMARTCHARGE, val);
+}
+
+/* Called on AP S0iX -> S0 transition */
+static void board_chipset_resume(void)
+{
+#ifndef VARIANT_KUKUI_NO_SENSORS
+	if (board_has_kb_backlight())
+		ioex_set_level(IOEX_KB_BL_EN, 1);
+#endif
+
+	/* Normal charge mode */
+	sb_quick_charge_mode(0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_INIT, board_chipset_resume, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S0 -> S0iX transition */
+static void board_chipset_suspend(void)
+{
+#ifndef VARIANT_KUKUI_NO_SENSORS
+	if (board_has_kb_backlight())
+		ioex_set_level(IOEX_KB_BL_EN, 0);
+#endif
+
+	/* Quick charge mode */
+	sb_quick_charge_mode(1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S5 -> S3 transition */
+static void board_chipset_startup(void)
+{
+	gpio_set_level(GPIO_EN_USBA_5V, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S3 -> S5 transition */
+static void board_chipset_shutdown(void)
+{
+	gpio_set_level(GPIO_EN_USBA_5V, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
+
+int board_get_charger_i2c(void)
+{
+	/* TODO(b:138415463): confirm the bus allocation for future builds */
+	return board_get_version() == 1 ? 2 : 1;
+}
+
+int board_get_battery_i2c(void)
+{
+	return board_get_version() >= 1 ? 2 : 1;
+}
+
+#ifdef SECTION_IS_RW
+static int it8801_get_target_channel(enum pwm_channel *channel, int type,
+				     int index)
+{
+	switch (type) {
+	case EC_PWM_TYPE_GENERIC:
+		*channel = index;
+		break;
+	default:
+		return -1;
+	}
+
+	return *channel >= 1;
+}
+
+static enum ec_status
+host_command_pwm_set_duty(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_pwm_set_duty *p = args->params;
+	enum pwm_channel channel;
+	uint16_t duty;
+
+	if (it8801_get_target_channel(&channel, p->pwm_type, p->index))
+		return EC_RES_INVALID_PARAM;
+
+	duty = (uint32_t)p->duty * 255 / 65535;
+	it8801_pwm_set_raw_duty(channel, duty);
+	it8801_pwm_enable(channel, p->duty > 0);
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_DUTY, host_command_pwm_set_duty,
+		     EC_VER_MASK(0));
+
+static enum ec_status
+host_command_pwm_get_duty(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_pwm_get_duty *p = args->params;
+	struct ec_response_pwm_get_duty *r = args->response;
+
+	enum pwm_channel channel;
+
+	if (it8801_get_target_channel(&channel, p->pwm_type, p->index))
+		return EC_RES_INVALID_PARAM;
+
+	r->duty = (uint32_t)it8801_pwm_get_raw_duty(channel) * 65535 / 255;
+	args->response_size = sizeof(*r);
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_DUTY, host_command_pwm_get_duty,
+		     EC_VER_MASK(0));
+#endif
diff --git a/board/makomo/board.h b/board/makomo/board.h
new file mode 100644
index 0000000000..e05e15c13d
--- /dev/null
+++ b/board/makomo/board.h
@@ -0,0 +1,158 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Configuration for Makomo */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#define VARIANT_KUKUI_JACUZZI
+#define VARIANT_KUKUI_BATTERY_SMART
+#define VARIANT_KUKUI_CHARGER_ISL9238
+#define VARIANT_KUKUI_EC_STM32F098
+
+#ifndef SECTION_IS_RW
+#define VARIANT_KUKUI_NO_SENSORS
+#undef CONFIG_CMD_MFALLOW
+#endif /* SECTION_IS_RW */
+
+#include "baseboard.h"
+
+#undef CONFIG_CHIPSET_POWER_SEQ_VERSION
+#define CONFIG_CHIPSET_POWER_SEQ_VERSION 1
+#undef CONFIG_SYSTEM_UNLOCKED
+
+#define CONFIG_BATTERY_HW_PRESENT_CUSTOM
+
+#define CONFIG_CHARGER_PSYS
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 5
+
+#define CONFIG_CHARGER_RUNTIME_CONFIG
+
+#define CONFIG_BC12_DETECT_PI3USB9201
+
+#define CONFIG_EXTPOWER_GPIO
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
+#define CONFIG_EXTPOWER_DEBOUNCE_MS 200
+
+#define CONFIG_I2C_BITBANG
+#undef I2C_BITBANG_PORT_COUNT
+#define I2C_BITBANG_PORT_COUNT 1
+#undef CONFIG_I2C_NACK_RETRY_COUNT
+#define CONFIG_I2C_NACK_RETRY_COUNT 10
+#define CONFIG_SMBUS_PEC
+
+#define CONFIG_USB_PD_TCPM_FUSB302
+#define CONFIG_USB_PD_DISCHARGE_GPIO
+#define CONFIG_USB_PD_TCPC_LOW_POWER
+
+#define CONFIG_USB_MUX_IT5205
+
+#define CONFIG_LED_ONOFF_STATES
+
+/* Motion Sensors */
+#ifndef VARIANT_KUKUI_NO_SENSORS
+#define CONFIG_ACCEL_LIS2DWL /* Lid accel */
+#define CONFIG_ACCELGYRO_BMI160 /* Base accel */
+#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+#define CONFIG_ALS
+#define CONFIG_CMD_ACCEL_INFO
+
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_UPDATE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+
+#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
+
+#ifdef SECTION_IS_RW
+#define CONFIG_IO_EXPANDER_IT8801_PWM
+#define CONFIG_KEYBOARD_BACKLIGHT
+#endif
+
+#endif /* VARIANT_KUKUI_NO_SENSORS */
+
+/* I2C ports */
+#define I2C_PORT_BC12 0
+#define I2C_PORT_TCPC0 0
+#define I2C_PORT_USB_MUX 0
+#define I2C_PORT_CHARGER board_get_charger_i2c()
+#define I2C_PORT_SENSORS 1
+#define I2C_PORT_KB_DISCRETE 1
+#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
+#define I2C_PORT_BATTERY 2
+
+/* IT8801 I2C address */
+#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1
+
+/* Enable Accel over SPI */
+#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */
+
+#define CONFIG_KEYBOARD_PROTOCOL_MKBP
+#define CONFIG_MKBP_EVENT
+#define CONFIG_MKBP_USE_GPIO
+
+#ifndef __ASSEMBLER__
+
+enum adc_channel {
+	/* Real ADC channels begin here */
+	ADC_BOARD_ID = 0,
+	ADC_EC_SKU_ID,
+	ADC_CH_COUNT
+};
+
+/* power signal definitions */
+enum power_signal {
+	AP_IN_S3_L,
+	PMIC_PWR_GOOD,
+
+	/* Number of signals */
+	POWER_SIGNAL_COUNT,
+};
+
+/* Motion sensors */
+enum sensor_id {
+	LID_ACCEL = 0,
+	BASE_ACCEL,
+	BASE_GYRO,
+	SENSOR_COUNT,
+};
+
+enum charge_port {
+	CHARGE_PORT_USB_C,
+};
+
+enum battery_type {
+	BATTERY_LGC,
+	BATTERY_SUNWODA,
+	BATTERY_SMP,
+	BATTERY_TYPE_COUNT,
+};
+
+enum pwm_channel {
+	IT8801_PWM_CH_KBLIGHT = 0,
+};
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+#ifdef SECTION_IS_RO
+/* Interrupt handler for emmc task */
+void emmc_cmd_interrupt(enum gpio_signal signal);
+#endif
+
+void bc12_interrupt(enum gpio_signal signal);
+void board_reset_pd_mcu(void);
+int board_get_version(void);
+
+/* returns the i2c port number of charger/battery */
+int board_get_charger_i2c(void);
+int board_get_battery_i2c(void);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/makomo/build.mk b/board/makomo/build.mk
new file mode 100644
index 0000000000..5b31bc2d67
--- /dev/null
+++ b/board/makomo/build.mk
@@ -0,0 +1,15 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+#
+# STmicro STM32F098VC
+CHIP:=stm32
+CHIP_FAMILY:=stm32f0
+CHIP_VARIANT:=stm32f09x
+BASEBOARD:=kukui
+
+board-y=battery.o board.o led.o
diff --git a/board/makomo/ec.tasklist b/board/makomo/ec.tasklist
new file mode 100644
index 0000000000..23b568cb28
--- /dev/null
+++ b/board/makomo/ec.tasklist
@@ -0,0 +1,20 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS_RW(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 1024) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, 1280) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, 1024) \
+	TASK_ALWAYS_RO(EMMC, emmc_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/makomo/gpio.inc b/board/makomo/gpio.inc
new file mode 100644
index 0000000000..8cbdef529e
--- /dev/null
+++ b/board/makomo/gpio.inc
@@ -0,0 +1,121 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first.
+ */
+
+/* Interrupts */
+GPIO_INT(USB_C0_PD_INT_ODL, PIN(B, 1), GPIO_INT_FALLING | GPIO_PULL_UP,
+         tcpc_alert_event)
+GPIO_INT(POWER_BUTTON_L,    PIN(A, 0),  GPIO_INT_BOTH | GPIO_PULL_UP,
+         power_button_interrupt) /* EC_PWR_BTN_ODL */
+GPIO_INT(AP_IN_SLEEP_L,     PIN(C, 12), GPIO_INT_BOTH | GPIO_PULL_DOWN,
+         power_signal_interrupt)
+GPIO_INT(PMIC_EC_RESETB,    PIN(B, 7),  GPIO_INT_BOTH | GPIO_PULL_DOWN,
+         power_signal_interrupt)
+GPIO_INT(WARM_RESET_REQ,    PIN(A, 3),  GPIO_INT_RISING | GPIO_PULL_DOWN,
+         chipset_reset_request_interrupt)
+GPIO_INT_RW(ACCEL_INT_ODL,  PIN(A, 4), GPIO_INT_FALLING | GPIO_SEL_1P8V | GPIO_PULL_UP,
+         bmi160_interrupt)
+GPIO_INT_RO(EMMC_CMD,       PIN(B, 15), GPIO_INT_FALLING,
+         emmc_cmd_interrupt)
+GPIO_INT(SPI1_NSS,          PIN(A, 15), GPIO_INT_BOTH | GPIO_PULL_UP,
+         spi_event) /* SPI_AP_EC_CS_L */
+GPIO_INT(LID_OPEN,          PIN(C, 5),  GPIO_INT_BOTH,
+         lid_interrupt)
+GPIO_INT(AC_PRESENT,        PIN(A, 6),  GPIO_INT_BOTH,
+         extpower_interrupt) /* ACOK_OD */
+GPIO_INT(BC12_EC_INT_ODL,   PIN(C, 9),  GPIO_INT_FALLING,
+         bc12_interrupt)
+GPIO_INT(IT8801_SMB_INT,    PIN(A, 8),  GPIO_INT_FALLING | GPIO_PULL_UP,
+         io_expander_it8801_interrupt) /* KB_INT_ODL */
+GPIO_INT(AP_EC_WATCHDOG_L,  PIN(D, 2),  GPIO_INT_FALLING,
+         chipset_watchdog_interrupt)
+GPIO_INT(TABLET_MODE_L,     PIN(B, 11), GPIO_INT_BOTH,
+         gmr_tablet_switch_isr)
+
+/* Unimplemented interrupts */
+GPIO(ALS_RGB_INT_ODL,      PIN(C, 10), GPIO_INPUT)
+
+/* Reset pins */
+GPIO(AP_SYS_RST_L,         PIN(C, 11), GPIO_OUT_LOW)
+GPIO(PMIC_WATCHDOG_L,      PIN(A, 2),  GPIO_OUT_LOW)
+GPIO(PMIC_EN_ODL,          PIN(F, 0),  GPIO_ODR_HIGH)
+
+/*
+ * I2C pins should be configured as inputs until I2C module is
+ * initialized. This will avoid driving the lines unintentionally.
+ */
+GPIO(I2C1_SCL,             PIN(B, 8),  GPIO_INPUT)
+GPIO(I2C1_SDA,             PIN(B, 9),  GPIO_INPUT)
+GPIO(I2C2_SCL,             PIN(A, 11), GPIO_INPUT)
+GPIO(I2C2_SDA,             PIN(A, 12), GPIO_INPUT)
+GPIO(I2C3_SCL,             PIN(A, 5),  GPIO_ODR_HIGH)
+GPIO(I2C3_SDA,             PIN(C, 4),  GPIO_ODR_HIGH)
+
+/* Analog pins */
+GPIO(BOARD_ID,             PIN(C, 0),  GPIO_ANALOG)
+GPIO(EC_SKU_ID,            PIN(B, 0),  GPIO_ANALOG)
+
+/* Other input pins */
+GPIO(WP_L,                 PIN(C, 8),  GPIO_INPUT) /* EC_FLASH_WP_ODL */
+GPIO(BOOT0,                PIN(F, 11), GPIO_INPUT)
+GPIO(CCD_MODE_ODL,         PIN(A, 1),  GPIO_INPUT)
+
+/* Other output pins */
+GPIO(EC_BATT_PRES_ODL,     PIN(A, 7),  GPIO_INPUT)
+GPIO(EC_BL_EN_OD,          PIN(A, 13), GPIO_ODR_HIGH)
+GPIO(EN_USBA_5V,           PIN(C, 14), GPIO_OUT_LOW)
+GPIO(EC_SENSOR_SPI_MISO,   PIN(C, 2),  GPIO_INPUT)
+GPIO(EC_SENSOR_SPI_MOSI,   PIN(C, 3),  GPIO_OUT_LOW)
+GPIO(EC_SENSOR_SPI_NSS,    PIN(B, 12), GPIO_OUT_HIGH)
+GPIO(EC_SENSOR_SPI_CK,     PIN(B, 10), GPIO_OUT_LOW)
+GPIO(ENTERING_RW,          PIN(C, 6),  GPIO_ODR_HIGH) /* EC_ENTERING_RW_ODL */
+GPIO(EC_INT_L,             PIN(C, 7),  GPIO_ODR_HIGH) /* EC_AP_INT_ODL */
+GPIO(EC_BOARD_ID_EN_L,     PIN(C, 15), GPIO_ODR_HIGH) /* EC_BOARD_ID_EN_ODL */
+GPIO(USB_C0_HPD_OD,        PIN(F, 1),  GPIO_ODR_LOW)
+GPIO(BOOTBLOCK_EN_L,       PIN(C, 1),  GPIO_ODR_HIGH)
+GPIO(EN_PP1800_S5_L,       PIN(A, 14), GPIO_OUT_LOW)
+GPIO(USB_C0_DISCHARGE,     PIN(B, 6),  GPIO_OUT_LOW)
+
+IOEX(PWR_LED_WHITE_L,      EXPIN(0, 1, 4), GPIO_OUT_HIGH)
+IOEX(BAT_LED_GREEN_FULL_L, EXPIN(0, 1, 3), GPIO_OUT_HIGH)
+IOEX(BAT_LED_RED_L,        EXPIN(0, 1, 2), GPIO_OUT_HIGH)
+IOEX(KB_BL_EN,             EXPIN(0, 0, 7), GPIO_OUT_LOW)
+
+/*
+ * TODO(b:138352732): On IT88801 expander, To be readded once IT8801 driver and
+ * gpio expander framework has landed.
+ */
+UNIMPLEMENTED(EN_PP5000_USBC)
+UNIMPLEMENTED(PMIC_FORCE_RESET_ODL)
+UNIMPLEMENTED(EN_USBC_CHARGE_L)
+
+/* USART1: PA9/PA10 */
+ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART,       0)
+/* I2C MASTER: PB8/9 */
+ALTERNATE(PIN_MASK(B, 0x0300), 1, MODULE_I2C,        GPIO_ODR_HIGH )
+/* I2C MASTER: PA11/12 */
+ALTERNATE(PIN_MASK(A, 0x1800), 5, MODULE_I2C,        GPIO_ODR_HIGH )
+
+
+/* SPI1 */
+/* SPI SLAVE: PB3/4/5 */
+ALTERNATE(PIN_MASK(B, 0x0038), 0, MODULE_SPI,        0)
+/* SPI SLAVE CS: PA15 */
+ALTERNATE(PIN_MASK(A, 0x8000), 0, MODULE_SPI,        0)
+
+/* SPI2 */
+/* Shared between slave for emmc and master for bmi160 */
+/* They're mutually exclusive with gpio_config_module. */
+/* EMMC SPI SLAVE: PB13/14/15 */
+ALTERNATE(PIN_MASK(B, 0xE000), 0, MODULE_SPI_FLASH,  0)
+/* SENSORS SPI MASTER: PB10, PB12, PC2, PC3 */
+ALTERNATE(PIN_MASK(B, 0x0400), 5, MODULE_SPI_CONTROLLER, 0)
+ALTERNATE(PIN_MASK(C, 0x000C), 1, MODULE_SPI_CONTROLLER, 0)
diff --git a/board/makomo/led.c b/board/makomo/led.c
new file mode 100644
index 0000000000..d0a7f7165c
--- /dev/null
+++ b/board/makomo/led.c
@@ -0,0 +1,120 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power and battery LED control for Makomo
+ */
+#include "common.h"
+#include "driver/ioexpander/it8801.h"
+#include "ec_commands.h"
+#include "ioexpander.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+
+#define LED_ON_LVL 0
+#define LED_OFF_LVL 1
+
+__override const int led_charge_lvl_1 = 5;
+__override const int led_charge_lvl_2 = 97;
+
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
+
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    1 * LED_ONE_SEC },
+						  { LED_OFF,
+						    3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_GREEN:
+		ioex_set_level(IOEX_BAT_LED_GREEN_FULL_L, LED_ON_LVL);
+		ioex_set_level(IOEX_BAT_LED_RED_L, LED_OFF_LVL);
+		break;
+	case EC_LED_COLOR_AMBER:
+		ioex_set_level(IOEX_BAT_LED_GREEN_FULL_L, LED_ON_LVL);
+		ioex_set_level(IOEX_BAT_LED_RED_L, LED_ON_LVL);
+		break;
+	case EC_LED_COLOR_RED:
+		ioex_set_level(IOEX_BAT_LED_GREEN_FULL_L, LED_OFF_LVL);
+		ioex_set_level(IOEX_BAT_LED_RED_L, LED_ON_LVL);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		ioex_set_level(IOEX_BAT_LED_GREEN_FULL_L, LED_OFF_LVL);
+		ioex_set_level(IOEX_BAT_LED_RED_L, LED_OFF_LVL);
+		break;
+	}
+}
+
+__override void led_set_color_power(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_WHITE:
+		ioex_set_level(IOEX_PWR_LED_WHITE_L, LED_ON_LVL);
+		break;
+	default:
+		ioex_set_level(IOEX_PWR_LED_WHITE_L, LED_OFF_LVL);
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_GREEN] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		brightness_range[EC_LED_COLOR_RED] = 1;
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		if (brightness[EC_LED_COLOR_GREEN] != 0)
+			led_set_color_battery(EC_LED_COLOR_GREEN);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(EC_LED_COLOR_AMBER);
+		else if (brightness[EC_LED_COLOR_RED] != 0)
+			led_set_color_battery(EC_LED_COLOR_RED);
+		else
+			led_set_color_battery(LED_OFF);
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_power(EC_LED_COLOR_WHITE);
+		else
+			led_set_color_power(LED_OFF);
+	} else {
+		return EC_ERROR_INVAL;
+	}
+	return EC_SUCCESS;
+}
diff --git a/board/makomo/vif_override.xml b/board/makomo/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/makomo/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/malefor/battery.c b/board/malefor/battery.c
deleted file mode 100644
index 7f37c6fe10..0000000000
--- a/board/malefor/battery.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Volteer battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	[BATTERY_SMP] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP",
-			.device_name = "L19M4PG2",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8800, /* mV */
-			.voltage_normal		= 7680, /* mV */
-			.voltage_min		= 6000, /* mV */
-			.precharge_current	= 332,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-	[BATTERY_LGC] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC",
-			.device_name = "L19L4PG2",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8800, /* mV */
-			.voltage_normal		= 7700, /* mV */
-			/*
-			 * voltage min value and precharge current value are
-			 * specified by LGC directly and not shown in the SPEC.
-			 */
-			.voltage_min		= 6000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 73,
-		},
-	},
-	[BATTERY_SUNWODA] = {
-		.fuel_gauge = {
-			.manuf_name = "SUNWODA",
-			.device_name = "L19D4PG2",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8800, /* mV */
-			.voltage_normal		= 7680, /* mV */
-			.voltage_min		= 6000, /* mV */
-			.precharge_current	= 333,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SMP;
diff --git a/board/malefor/board.c b/board/malefor/board.c
deleted file mode 100644
index 2532369dc8..0000000000
--- a/board/malefor/board.c
+++ /dev/null
@@ -1,599 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Malefor board-specific configuration */
-#include "bb_retimer.h"
-#include "button.h"
-#include "cbi_ec_fw_config.h"
-#include "common.h"
-#include "driver/accel_lis2dh.h"
-#include "driver/accelgyro_lsm6dsm.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/ppc/syv682x.h"
-#include "driver/sync.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/tusb422.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "tablet_mode.h"
-#include "uart.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ## args)
-
-/* Keyboard scan setting */
-struct keyboard_scan_config keyscan_config = {
-	/* Increase from 50 us, because KSO_02 passes through the H1. */
-	.output_settle_us = 80,
-	/* Other values should be the same as the default configuration. */
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-/******************************************************************************/
-/*
- * FW_CONFIG defaults for Malefor if the CBI data is not initialized.
- */
-union volteer_cbi_fw_config fw_config_defaults = {
-	.usb_db = DB_USB3_NO_A,
-};
-
-static void board_init(void)
-{
-	if (ec_cfg_has_tabletmode()) {
-		/* Enable gpio interrupt for base accelgyro sensor */
-		gpio_enable_interrupt(GPIO_EC_IMU_INT_L);
-	} else {
-		motion_sensor_count = 0;
-		/* Device is clamshell only */
-		tablet_set_mode(0);
-		/* Gyro is not present, don't allow line to float */
-		gpio_set_flags(GPIO_EC_IMU_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
-	}
-
-	/*
-	 * TODO: b/154447182 - Malefor will control power LED and battery LED
-	 * independently, and keep the max brightness of power LED and battery
-	 * LED as 50%.
-	 */
-	pwm_enable(PWM_CH_LED4_SIDESEL, 1);
-	pwm_set_duty(PWM_CH_LED4_SIDESEL, 50);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-int board_is_lid_angle_tablet_mode(void)
-{
-	return ec_cfg_has_tabletmode();
-}
-
-/* Enable or disable input devices, based on tablet mode or chipset state */
-#ifndef TEST_BUILD
-void lid_angle_peripheral_enable(int enable)
-{
-	if (ec_cfg_has_tabletmode()) {
-		if (chipset_in_state(CHIPSET_STATE_ANY_OFF) ||
-			tablet_get_mode())
-			enable = 0;
-		keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
-	}
-}
-#endif
-
-/******************************************************************************/
-/* Sensors */
-/* Lid and base Sensor mutex */
-static struct mutex g_lid_accel_mutex;
-static struct mutex g_base_mutex;
-
-/* Lid and base accel private data */
-static struct stprivate_data g_lis2dh_data;
-static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
-
-/* Matrix to rotate lid and base sensor into standard reference frame */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LIS2DE,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &lis2dh_drv,
-		.mutex = &g_lid_accel_mutex,
-		.drv_data = &g_lis2dh_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LIS2DH_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.min_frequency = LIS2DH_ODR_MIN_VAL,
-		.max_frequency = LIS2DH_ODR_MAX_VAL,
-		.default_range = 2, /* g, to support tablet mode */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_EC_IMU_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 13000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			/* Sensor on for angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_EC_IMU_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-	},
-};
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/******************************************************************************/
-/* Physical fans. These are logically separate from pwm_channels. */
-
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = GPIO_EN_PP5000_FAN,
-};
-
-/*
- * Fan specs from datasheet:
- * Max speed 5900 rpm (+/- 7%), minimum duty cycle 30%.
- * Minimum speed not specified by RPM. Set minimum RPM to max speed (with
- * margin) x 30%.
- *    5900 x 1.07 x 0.30 = 1894, round up to 1900
- */
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 1900,
-	.rpm_start = 1900,
-	.rpm_max = 5900,
-};
-
-const struct fan_t fans[FAN_CH_COUNT] = {
-	[FAN_CH_0] = {
-		.conf = &fan_conf_0,
-		.rpm = &fan_rpm_0,
-	},
-};
-
-/******************************************************************************/
-/* EC thermal management configuration */
-
-/*
- * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
- * 130 C.  However, sensor is located next to DDR, so we need to use the lower
- * DDR temperature limit (85 C)
- */
-const static struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(35),
-	.temp_fan_max = C_TO_K(50),
-};
-
-/*
- * Inductor limits - used for both charger and PP3300 regulator
- *
- * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
- *
- * Charger max recommended temperature 100C, max absolute temperature 125C
- * PP3300 regulator: operating range -40 C to 145 C
- *
- * Inductors: limit of 125c
- * PCB: limit is 80c
- */
-const static struct ec_thermal_config thermal_inductor = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(55),
-};
-
-
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_CHARGER]			= thermal_inductor,
-	[TEMP_SENSOR_2_PP3300_REGULATOR]	= thermal_inductor,
-	[TEMP_SENSOR_3_DDR_SOC]			= thermal_cpu,
-	[TEMP_SENSOR_4_FAN]			= thermal_cpu,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-/******************************************************************************/
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {
-		.module = NPCX_MFT_MODULE_1,
-		.clk_src = TCKC_LFCLK,
-		.pwm_id = PWM_CH_FAN,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-/******************************************************************************/
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C0_SENSOR_SCL,
-		.sda = GPIO_EC_I2C0_SENSOR_SDA,
-	},
-	{
-		.name = "usb_c0",
-		.port = I2C_PORT_USB_C0,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C1_USB_C0_SCL,
-		.sda = GPIO_EC_I2C1_USB_C0_SDA,
-	},
-	{
-		.name = "usb_c1",
-		.port = I2C_PORT_USB_C1,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C2_USB_C1_SCL,
-		.sda = GPIO_EC_I2C2_USB_C1_SDA,
-	},
-	{
-		.name = "usb_1_mix",
-		.port = I2C_PORT_USB_1_MIX,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C3_USB_1_MIX_SCL,
-		.sda = GPIO_EC_I2C3_USB_1_MIX_SDA,
-	},
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C5_POWER_SCL,
-		.sda = GPIO_EC_I2C5_POWER_SDA,
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C7_EEPROM_SCL,
-		.sda = GPIO_EC_I2C7_EEPROM_SDA,
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/******************************************************************************/
-/* PWM configuration */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED4_SIDESEL] = {
-		.channel = 7,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		/* Run at a higher frequency than the color PWM signals to avoid
-		 * timing-based color shifts.
-		 */
-		.freq = 4800,
-	},
-	[PWM_CH_FAN] = {
-		.channel = 5,
-		.flags = PWM_CONFIG_OPEN_DRAIN,
-		.freq = 25000
-	},
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = 0,
-		/*
-		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
-		 * flicker. Higher frequencies consume similar average power to
-		 * lower PWM frequencies, but higher frequencies record a much
-		 * lower maximum power.
-		 */
-		.freq = 2400,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* USBC TCPC configuration for port 1 on USB3 board */
-static const struct tcpc_config_t tcpc_config_p1_usb3 = {
-	.bus_type = EC_BUS_TYPE_I2C,
-	.i2c_info = {
-		.port = I2C_PORT_USB_C1,
-		.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-	},
-	.flags = TCPC_FLAGS_TCPCI_REV2_0 | TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V,
-	.drv = &ps8xxx_tcpm_drv,
-	.usb23 = USBC_PORT_1_USB2_NUM | (USBC_PORT_1_USB3_NUM << 4),
-};
-
-static const struct usb_mux usbc1_usb3_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	.next_mux = NULL,
-};
-
-static const struct usb_mux mux_config_p1_usb3 = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-	.next_mux = &usbc1_usb3_db_retimer,
-};
-
-void board_reset_pd_mcu(void)
-{
-	int val;
-
-	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 0);
-	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS,
-			   PS8815_PWR_H_RST_H_DELAY_MS));
-	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 1);
-	msleep(PS8815_FW_INIT_DELAY_MS);
-
-	/*
-	 * b/144397088
-	 * ps8815 firmware 0x01 needs special configuration
-	 */
-
-	CPRINTS("%s: patching ps8815 registers", __func__);
-
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
-		CPRINTS("ps8815: reg 0x0f was %02x", val);
-
-	if (i2c_write8(I2C_PORT_USB_C1,
-		       PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) == EC_SUCCESS)
-		CPRINTS("ps8815: reg 0x0f set to 0x31");
-
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
-		CPRINTS("ps8815: reg 0x0f now %02x", val);
-}
-
-__override void board_cbi_init(void)
-{
-	/* Config DB USB3 */
-	tcpc_config[USBC_PORT_C1] = tcpc_config_p1_usb3;
-	usb_muxes[USBC_PORT_C1] = mux_config_p1_usb3;
-}
-
-/******************************************************************************/
-/* USBC PPC configuration */
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/******************************************************************************/
-/* PPC support routines */
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		sn5s330_interrupt(USBC_PORT_C0);
-		break;
-	case GPIO_USB_C1_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C1);
-	default:
-		break;
-	}
-}
-
-/******************************************************************************/
-/* BC1.2 charger detect configuration */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC TCPC configuration */
-struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
-		},
-		.drv = &tusb422_tcpm_drv,
-		.usb23 = USBC_PORT_0_USB2_NUM | (USBC_PORT_0_USB3_NUM << 4),
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C1,
-			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
-		},
-		.drv = &tusb422_tcpm_drv,
-		.usb23 = USBC_PORT_1_USB2_NUM | (USBC_PORT_1_USB3_NUM << 4),
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC mux configuration - Tiger Lake includes internal mux */
-struct usb_mux usbc1_usb4_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &bb_usb_retimer,
-	.i2c_port = I2C_PORT_USB_1_MIX,
-	.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
-};
-struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc1_usb4_db_retimer,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-struct bb_usb_control bb_controls[] = {
-	[USBC_PORT_C0] = {
-		/* USB-C port 0 doesn't have a retimer */
-	},
-	[USBC_PORT_C1] = {
-		.usb_ls_en_gpio = GPIO_USB_C1_LS_EN,
-		.retimer_rst_gpio = GPIO_USB_C1_RT_RST_ODL,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(bb_controls) == USBC_PORT_COUNT);
-
-static void board_tcpc_init(void)
-{
-	/* Don't reset TCPCs after initial reset */
-	if (!system_jumped_late())
-		board_reset_pd_mcu();
-
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
-
-	/* Enable BC1.2 interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
-
-/******************************************************************************/
-/* TCPC support routines */
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	/*
-	 * Check which port has the ALERT line set
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_0;
-	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (port == USBC_PORT_C0)
-		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
-	else
-		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
-}
diff --git a/board/malefor/board.h b/board/malefor/board.h
deleted file mode 100644
index 321fbc130f..0000000000
--- a/board/malefor/board.h
+++ /dev/null
@@ -1,172 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Baseboard features */
-#include "baseboard.h"
-
-/* Optional features */
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
-
-#define CONFIG_POWER_BUTTON
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* LED defines */
-#define CONFIG_LED_POWER_LED
-#define CONFIG_LED_ONOFF_STATES
-
-/* Keyboard features */
-
-/* Sensors */
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-#define CONFIG_ACCEL_LIS2DE             /* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM        /* Base accel */
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
-	BIT(LID_ACCEL)
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
-
-/*
- * USB-C port's USB2 & USB3 mapping from schematics
- * USB2 numbering on PCH - 1 to n
- * USB3 numbering on AP - 0 to n (PMC's USB3 numbering for MUX
- * configuration is - 1 to n hence add +1)
- */
-#define USBC_PORT_0_USB2_NUM	9
-#define USBC_PORT_0_USB3_NUM	1
-#define USBC_PORT_1_USB2_NUM	4
-#define USBC_PORT_1_USB3_NUM	2
-
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
-
-/*
- * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
- * cables only support up to 60W.
- */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
-/* Enabling USB4 mode */
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x40
-
-/* USB Type A Features */
-
-/* USBC PPC*/
-#define CONFIG_USBC_PPC_SN5S330		/* USBC port C0 */
-#define CONFIG_USBC_PPC_SYV682X		/* USBC port C1 */
-
-/* BC 1.2 */
-
-/* Volume Button feature */
-
-/* Fan features */
-
-/* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SYS_PWROK		GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PG_EC_DSW_PWROK		GPIO_DSW_PWROK
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD		GPIO_PG_EC_RSMRST_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
-#define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE_L
-
-/* I2C Bus Configuration */
-#define CONFIG_I2C
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_1_MIX	NPCX_I2C_PORT3_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-#define CONFIG_I2C_MASTER
-
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum battery_type {
-	BATTERY_SMP,
-	BATTERY_LGC,
-	BATTERY_SUNWODA,
-	BATTERY_TYPE_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_LED4_SIDESEL = 0,
-	PWM_CH_FAN,
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT,
-};
-
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
-
-void board_reset_pd_mcu(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/malefor/build.mk b/board/malefor/build.mk
deleted file mode 100644
index 279b2e559e..0000000000
--- a/board/malefor/build.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
-BASEBOARD:=volteer
-
-board-y=board.o
-board-y+=battery.o
-board-y+=led.o
diff --git a/board/malefor/ec.tasklist b/board/malefor/ec.tasklist
deleted file mode 100644
index 292de51cdb..0000000000
--- a/board/malefor/ec.tasklist
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/malefor/gpio.inc b/board/malefor/gpio.inc
deleted file mode 100644
index 6144bba66f..0000000000
--- a/board/malefor/gpio.inc
+++ /dev/null
@@ -1,159 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(EC_LID_OPEN,          PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(EC_WP_L,              PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(H1_EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
-GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_RSMRST_ODL,     PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(DSW_PWROK,            PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4),  GPIO_INT_BOTH, power_signal_interrupt)
-
-/* Sensor Interrupts */
-GPIO_INT(EC_IMU_INT_L,         PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, lsm6dsm_interrupt)
-GPIO_INT(TABLET_MODE_L,        PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(E, 0), GPIO_INT_BOTH, tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(A, 2), GPIO_INT_BOTH, tcpc_alert_event)
-
-GPIO_INT(USB_C0_PPC_INT_ODL,	PIN(6, 2), GPIO_INT_BOTH, ppc_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(F, 5), GPIO_INT_BOTH, ppc_interrupt)
-
-GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(E, 4), GPIO_INT_BOTH, bc12_interrupt)
-GPIO_INT(USB_C1_MIX_INT_ODL,	PIN(0, 3), GPIO_INT_BOTH, bc12_interrupt)
-
-/* HDMI interrupts */
-
-/* Volume button interrupts */
-GPIO_INT(EC_VOLDN_BTN_ODL,		PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL,		PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-
-/* Power Sequencing Signals */
-GPIO(EN_PP3300_A,              PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_PPVAR_VCCIN,           PIN(4, 3), GPIO_OUT_LOW) /* Enables VCCIN IMPV9 */
-/* The EC does not buffer this signal on Volteer. */
-UNIMPLEMENTED(PCH_DSW_PWROK)
-
-/* Other wake sources */
-/*
- * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an
- * interrupt handler because it is automatically handled by the PSL.
- *
- * We need to lock the setting so this gpio can't be reconfigured to overdrive
- * the real reset signal. (This is the PSL input pin not the real reset pin).
- */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH |
-					   GPIO_HIB_WAKE_HIGH |
-					   GPIO_LOCKED)
-
-/* AP/PCH Signals */
-GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
-GPIO(EC_PCH_RSMRST_ODL,        PIN(A, 6), GPIO_ODR_LOW) /* TODO - b/140950085 - implement TGL sequencing requirement */
-GPIO(EC_PCH_PWR_BTN_ODL,       PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
-GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
-UNIMPLEMENTED(EC_PROCHOT_IN_L)
-GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
-
-GPIO(EC_PCH_INT_ODL,           PIN(B, 0), GPIO_ODR_HIGH)
-
-/* USB and USBC Signals */
-GPIO(USB_C1_RT_RST_ODL,			PIN(8, 3), GPIO_ODR_LOW) /* USB_C1 Reset on boards board ID >=1 */
-GPIO(USB_C0_OC_ODL,			PIN(B, 1), GPIO_ODR_HIGH)
-GPIO(USB_C1_OC_ODL,			PIN(5, 0), GPIO_ODR_HIGH)
-
-/* Don't have a load switch for retimer */
-UNIMPLEMENTED(USB_C1_LS_EN)
-
-/* Misc Signals */
-
-/*
- * eDP backlight - both PCH and EC have enable pins that must be high
- * for the backlight to turn on. Default state is high, and can be turned
- * off during sleep states.
- */
-GPIO(EC_EDP_BL_EN,             PIN(D, 3), GPIO_OUT_HIGH)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(EC_I2C0_SENSOR_SCL,       PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C0_SENSOR_SDA,       PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C1_USB_C0_SCL,       PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C1_USB_C0_SDA,       PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SCL,       PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SDA,       PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C3_USB_1_MIX_SCL,    PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C3_USB_1_MIX_SDA,    PIN(D, 0), GPIO_INPUT)
-GPIO(EC_I2C5_POWER_SCL,        PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C5_POWER_SDA,        PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_SCL,       PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_SDA,       PIN(B, 2), GPIO_INPUT)
-
-/* Battery signals */
-GPIO(EC_BATT_PRES_ODL, 		PIN(E, 1), GPIO_INPUT)
-
-/* Physical HPD pins are not needed on EC as these are configured by PMC */
-GPIO(USB_C0_DP_HPD,		PIN(F, 3), GPIO_INPUT)
-GPIO(USB_C1_DP_HPD,		PIN(7, 0), GPIO_INPUT)
-
-/* LED */
-GPIO(LED_1_L,	 PIN(C, 4), GPIO_OUT_HIGH)	/* Battery - Green LED */
-GPIO(LED_2_L,	 PIN(C, 3), GPIO_OUT_HIGH)	/* Battery - Red LED */
-GPIO(LED_3_L,	 PIN(C, 2), GPIO_OUT_HIGH)	/* Power - White LED */
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, BIT(5) | BIT(4)), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V)) /* I2C0 */
-ALTERNATE(PIN_MASK(9, BIT(0) | BIT(2) | BIT(1)), 0, MODULE_I2C, 0)                   /* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)                                     /* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, BIT(1) | BIT(0)), 0, MODULE_I2C, 0)                            /* I2C3 */
-ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)                            /* I2C5 */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)                            /* I2C7 */
-
-/* This selects between an LED module on the motherboard and one on the daughter
- * board, to be controlled by LED_{1,2,3}_L. PWM allows driving both modules at
- * the same time. */
-ALTERNATE(PIN_MASK(6, BIT(0)), 0, MODULE_PWM, 0)                                     /* LED_SIDESEL_4_L */
-
-/* Fan signals */
-GPIO(EN_PP5000_FAN,            PIN(6, 1), GPIO_OUT_LOW)
-ALTERNATE(PIN_MASK(B, BIT(7)), 0, MODULE_PWM, 0)	/* FAN_PWM */
-ALTERNATE(PIN_MASK(4, BIT(0)), 0, MODULE_PWM, 0)	/* FAN_SPEED_TACH */
-
-/* Keyboard pins */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_00-01 */
-GPIO(EC_KSO_02_INV, PIN(1, 7),                        GPIO_OUT_LOW)  /* KSO_02 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_14 */
-ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)                     /* EC_KB_BL_PWM */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, BIT(5) | BIT(4)), 0, MODULE_UART, 0)                           /* UART from EC to Servo */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)                    /* GPIOD2 = EC_LID_OPEN */
-ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)  /* GPIO00 = ACOK_OD,
-                                                                       GPIO01 = H1_EC_PWR_BTN_ODL
-                                                                       GPIO02 = EC_RST_ODL */
-
diff --git a/board/malefor/led.c b/board/malefor/led.c
deleted file mode 100644
index 6f4e781404..0000000000
--- a/board/malefor/led.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Malefor
- */
-
-#include "common.h"
-#include "led_onoff_states.h"
-#include "led_common.h"
-#include "gpio.h"
-
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
-
-const int led_charge_lvl_1 = 5;
-
-const int led_charge_lvl_2 = 97;
-
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED,   LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,   1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
-
-const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]            = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]    = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-					 {LED_OFF,         0.5 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF,            LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF,            LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-void led_set_color_power(enum ec_led_colors color)
-{
-	if (color == EC_LED_COLOR_WHITE)
-		gpio_set_level(GPIO_LED_3_L, LED_ON_LVL);
-	else
-		/* LED_OFF and unsupported colors */
-		gpio_set_level(GPIO_LED_3_L, LED_OFF_LVL);
-}
-
-void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_RED:
-		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_LED_1_L, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_GREEN:
-		gpio_set_level(GPIO_LED_1_L, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_RED] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_GREEN] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_RED] != 0)
-			led_set_color_battery(EC_LED_COLOR_RED);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if (brightness[EC_LED_COLOR_GREEN] != 0)
-			led_set_color_battery(EC_LED_COLOR_GREEN);
-		else
-			led_set_color_battery(LED_OFF);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
diff --git a/board/marasov/battery.c b/board/marasov/battery.c
new file mode 100644
index 0000000000..b974930d5b
--- /dev/null
+++ b/board/marasov/battery.c
@@ -0,0 +1,77 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "cbi.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "gpio.h"
+/*
+ * Battery info for all Brya battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	/* C490-42 Battery Information */
+	[BATTERY_C490] = {
+		.fuel_gauge = {
+			.manuf_name = "AS3GWQd3jB",
+			.device_name = "C490-42",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr = 0x99,
+				.reg_mask = 0x000c,
+				.disconnect_val = 0x000c,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13200, /* mV */
+			.voltage_normal		= 11880, /* mV */
+			.voltage_min		= 9000, /* mV */
+			.precharge_current	= 256,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 45,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 60,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_C490;
+
+enum battery_present battery_hw_present(void)
+{
+	enum gpio_signal batt_pres;
+
+	batt_pres = GPIO_EC_BATT_PRES_ODL;
+
+	/* The GPIO is low when the battery is physically present */
+	return gpio_get_level(batt_pres) ? BP_NO : BP_YES;
+}
diff --git a/board/marasov/board.c b/board/marasov/board.c
new file mode 100644
index 0000000000..94ef52a8c4
--- /dev/null
+++ b/board/marasov/board.c
@@ -0,0 +1,64 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "button.h"
+#include "cbi.h"
+#include "charge_ramp.h"
+#include "charger.h"
+#include "common.h"
+#include "console.h"
+#include "driver/accel_lis2dw12.h"
+#include "driver/accelgyro_lsm6dso.h"
+#include "driver/als_tcs3400.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "registers.h"
+#include "switch.h"
+#include "tablet_mode.h"
+#include "throttle_ap.h"
+#include "usbc_config.h"
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* Console output macros */
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+
+/* Called on AP S3 -> S0 transition */
+static void board_chipset_resume(void)
+{
+	/* Allow keyboard backlight to be enabled */
+
+	if (ec_cfg_kb_bl_type())
+		gpio_set_level(GPIO_EC_KB_BL_EN_L, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S0 -> S3 transition */
+static void board_chipset_suspend(void)
+{
+	/* Turn off the keyboard backlight if it's on. */
+
+	if (ec_cfg_kb_bl_type())
+		gpio_set_level(GPIO_EC_KB_BL_EN_L, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
+
+__override uint32_t board_override_feature_flags0(uint32_t flags0)
+{
+	/*
+	 * Remove keyboard backlight feature for devices that don't support it.
+	 */
+	if (!ec_cfg_kb_bl_type())
+		return (flags0 & ~EC_FEATURE_MASK_0(EC_FEATURE_PWM_KEYB));
+	else
+		return flags0;
+}
diff --git a/board/marasov/board.h b/board/marasov/board.h
new file mode 100644
index 0000000000..b34e69224b
--- /dev/null
+++ b/board/marasov/board.h
@@ -0,0 +1,192 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Brya board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "compile_time_macros.h"
+
+/* Baseboard features */
+#include "baseboard.h"
+
+/*
+ * This will happen automatically on NPCX9 ES2 and later. Do not remove
+ * until we can confirm all earlier chips are out of service.
+ */
+#define CONFIG_HIBERNATE_PSL_VCC1_RST_WAKEUP
+
+#define CONFIG_MP2964
+
+/* LED */
+#define CONFIG_LED_ONOFF_STATES
+#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
+
+#undef CONFIG_TABLET_MODE
+#undef CONFIG_TABLET_MODE_SWITCH
+#undef CONFIG_GMR_TABLET_MODE
+#undef CONFIG_VOLUME_BUTTONS
+
+/* USB Type A Features */
+#define USB_PORT_COUNT 2
+#define CONFIG_USB_PORT_POWER_DUMB
+
+#define CONFIG_IO_EXPANDER
+#define CONFIG_IO_EXPANDER_NCT38XX
+#define CONFIG_IO_EXPANDER_PORT_COUNT 1
+
+#define CONFIG_USB_PD_FRS_PPC
+#define CONFIG_USB_PD_VBUS_DETECT_PPC
+#undef CONFIG_USB_PD_VBUS_DETECT_TCPC
+
+#define CONFIG_USB_PD_TCPM_PS8815
+#define CONFIG_USB_PD_TCPM_PS8815_FORCE_DID
+#undef CONFIG_BC12_DETECT_PI3USB9201
+#undef CONFIG_USB_CHARGER
+
+/* Battery Configuration */
+#define CONFIG_SMBUS_PEC
+#undef CONFIG_BATT_HOST_FULL_FACTOR
+#define CONFIG_BATT_HOST_FULL_FACTOR 99
+
+/* I2C speed console command */
+#define CONFIG_CMD_I2C_SPEED
+
+/* I2C control host command */
+#define CONFIG_HOSTCMD_I2C_CONTROL
+
+#define CONFIG_USBC_PPC_SYV682X
+
+/* TODO: b/177608416 - measure and check these values on brya */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
+
+/*
+ * Passive USB-C cables only support up to 60W.
+ */
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
+
+/*
+ * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
+ * signal.
+ */
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
+
+/* System has back-lit keyboard */
+#define CONFIG_PWM_KBLIGHT
+
+/* I2C Bus Configuration */
+
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+
+#define I2C_PORT_USB_C0_TCPC NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1
+
+#define I2C_PORT_USB_C0_PPC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1
+
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+
+#define I2C_ADDR_MP2964_FLAGS 0x20
+
+/* Thermal features */
+#define CONFIG_THERMISTOR
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_TEMP_SENSOR_POWER
+#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
+
+#define CONFIG_FANS FAN_CH_COUNT
+
+/* Charger defines */
+#define CONFIG_CHARGER_BQ25720
+#define CONFIG_CHARGER_BQ25720_VSYS_TH2_CUSTOM
+#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV 70
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10
+#define CONFIG_CHARGER_BQ25710_PSYS_SENSING
+
+/*
+ * Older boards have a different ADC assignment.
+ */
+
+#define CONFIG_ADC_CHANNELS_RUNTIME_CONFIG
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h" /* needed by registers.h */
+#include "registers.h"
+#include "usbc_config.h"
+
+enum adc_channel {
+	ADC_TEMP_SENSOR_1_DDR_SOC,
+	ADC_TEMP_SENSOR_2_AMBIENT,
+	ADC_TEMP_SENSOR_3_CHARGER,
+	ADC_TEMP_SENSOR_4_WWAN,
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1_DDR_SOC,
+	TEMP_SENSOR_2_AMBIENT,
+	TEMP_SENSOR_3_CHARGER,
+	TEMP_SENSOR_4_WWAN,
+	TEMP_SENSOR_COUNT
+};
+
+enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_PORT_COUNT };
+
+enum battery_type { BATTERY_C490, BATTERY_TYPE_COUNT };
+
+enum pwm_channel {
+	PWM_CH_KBLIGHT, /* PWM3 */
+	PWM_CH_FAN, /* PWM5 */
+	PWM_CH_COUNT
+};
+
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT };
+
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT };
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/marasov/build.mk b/board/marasov/build.mk
new file mode 100644
index 0000000000..8b85854cf0
--- /dev/null
+++ b/board/marasov/build.mk
@@ -0,0 +1,25 @@
+# -*- makefile -*-
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Brya board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx9
+CHIP_VARIANT:=npcx9m3f
+BASEBOARD:=brya
+
+board-y=
+board-y+=battery.o
+board-y+=board.o
+board-y+=charger.o
+board-y+=fans.o
+board-y+=fw_config.o
+board-y+=i2c.o
+board-y+=keyboard.o
+board-y+=led.o
+board-y+=pwm.o
+board-y+=sensors.o
+board-y+=usbc_config.o
diff --git a/board/marasov/charger.c b/board/marasov/charger.c
new file mode 100644
index 0000000000..d78c345f94
--- /dev/null
+++ b/board/marasov/charger.c
@@ -0,0 +1,82 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/charger/bq25710.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+#ifndef CONFIG_ZEPHYR
+/* Charger Chip Configuration */
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = BQ25710_SMBUS_ADDR1_FLAGS,
+		.drv = &bq25710_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CHARGER_NUM);
+#endif
+
+int board_set_active_charge_port(int port)
+{
+	int is_valid_port = board_is_usb_pd_port_present(port);
+	int i;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTSUSB("Disabling all charger ports");
+
+		/* Disable all ports. */
+		for (i = 0; i < ppc_cnt; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (ppc_vbus_sink_enable(i, 0))
+				CPRINTSUSB("Disabling C%d as sink failed.", i);
+		}
+
+		return EC_SUCCESS;
+	} else if (!is_valid_port) {
+		return EC_ERROR_INVAL;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (ppc_is_sourcing_vbus(port)) {
+		CPRINTFUSB("Skip enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTSUSB("New charge port: C%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < ppc_cnt; i++) {
+		if (i == port)
+			continue;
+
+		if (ppc_vbus_sink_enable(i, 0))
+			CPRINTSUSB("C%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTSUSB("C%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/board/marasov/ec.tasklist b/board/marasov/ec.tasklist
new file mode 100644
index 0000000000..a4039fc94f
--- /dev/null
+++ b/board/marasov/ec.tasklist
@@ -0,0 +1,26 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ *
+ * USB_CHG_Px tasks must be contiguous (see USB_CHG_PORT_TO_TASK_ID(x)).
+ * PD_Cx tasks must be contiguous (see PD_PORT_TO_TASK_ID(x))
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, HOOKS_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, BASEBOARD_CHARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, BASEBOARD_CHIPSET_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, CONSOLE_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, BASEBOARD_POWERBTN_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, BASEBOARD_PD_INT_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, BASEBOARD_PD_INT_TASK_STACK_SIZE)
diff --git a/board/marasov/fans.c b/board/marasov/fans.c
new file mode 100644
index 0000000000..d9b4d0d99a
--- /dev/null
+++ b/board/marasov/fans.c
@@ -0,0 +1,89 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Physical fans. These are logically separate from pwm_channels. */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "fan.h"
+#include "fan_chip.h"
+#include "hooks.h"
+#include "pwm.h"
+
+/* MFT channels. These are logically separate from pwm_channels. */
+const struct mft_t mft_channels[] = {
+	[MFT_CH_0] = {
+		.module = NPCX_MFT_MODULE_1,
+		.clk_src = TCKC_LFCLK,
+		.pwm_id = PWM_CH_FAN,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
+
+static const struct fan_conf fan_conf_0 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
+	.pgood_gpio = -1,
+	.enable_gpio = GPIO_EN_PP5000_FAN,
+};
+
+/*
+ * TOOD(b/181271666): thermistor placement and calibration
+ *
+ * Prototype fan spins at about 4200 RPM at 100% PWM, this
+ * is specific to board ID 2 and might also apears in later
+ * boards as well.
+ */
+static const struct fan_rpm fan_rpm_0 = {
+	.rpm_min = 2200,
+	.rpm_start = 2200,
+	.rpm_max = 4200,
+};
+
+const struct fan_t fans[FAN_CH_COUNT] = {
+	[FAN_CH_0] = {
+		.conf = &fan_conf_0,
+		.rpm = &fan_rpm_0,
+	},
+};
+
+#ifndef CONFIG_FANS
+
+/*
+ * TODO(b/181271666): use static fan speeds until fan and sensors are
+ * tuned. for now, use:
+ *
+ *   AP off:  33%
+ *   AP  on: 100%
+ */
+
+static void fan_slow(void)
+{
+	const int duty_pct = 33;
+
+	ccprints("%s: speed %d%%", __func__, duty_pct);
+
+	pwm_enable(PWM_CH_FAN, 1);
+	pwm_set_duty(PWM_CH_FAN, duty_pct);
+}
+
+static void fan_max(void)
+{
+	const int duty_pct = 100;
+
+	ccprints("%s: speed %d%%", __func__, duty_pct);
+
+	pwm_enable(PWM_CH_FAN, 1);
+	pwm_set_duty(PWM_CH_FAN, duty_pct);
+}
+
+DECLARE_HOOK(HOOK_INIT, fan_slow, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, fan_slow, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, fan_slow, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_RESET, fan_max, HOOK_PRIO_FIRST);
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, fan_max, HOOK_PRIO_DEFAULT);
+
+#endif /* CONFIG_FANS */
diff --git a/board/marasov/fw_config.c b/board/marasov/fw_config.c
new file mode 100644
index 0000000000..39c5488331
--- /dev/null
+++ b/board/marasov/fw_config.c
@@ -0,0 +1,45 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "fw_config.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+static union marasov_cbi_fw_config fw_config;
+BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
+
+/*
+ * FW_CONFIG defaults for brya if the CBI.FW_CONFIG data is not
+ * initialized.
+ */
+static const union marasov_cbi_fw_config fw_config_defaults = {
+	.kb_bl = KEYBOARD_BACKLIGHT_ENABLED,
+};
+
+/****************************************************************************
+ * Brya FW_CONFIG access
+ */
+void board_init_fw_config(void)
+{
+	if (cbi_get_fw_config(&fw_config.raw_value)) {
+		CPRINTS("CBI: Read FW_CONFIG failed, using board defaults");
+		fw_config = fw_config_defaults;
+	}
+}
+
+union marasov_cbi_fw_config get_fw_config(void)
+{
+	return fw_config;
+}
+
+enum ec_cfg_keyboard_backlight_type ec_cfg_kb_bl_type(void)
+{
+	return fw_config.kb_bl;
+}
diff --git a/board/marasov/fw_config.h b/board/marasov/fw_config.h
new file mode 100644
index 0000000000..e208e80ca0
--- /dev/null
+++ b/board/marasov/fw_config.h
@@ -0,0 +1,47 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __BOARD_MARASOV_FW_CONFIG_H_
+#define __BOARD_MARASOV_FW_CONFIG_H_
+
+#include <stdint.h>
+
+/****************************************************************************
+ * CBI FW_CONFIG layout for marasov board.
+ *
+ * Source of truth is the project/brya/marasov/config.star configuration file.
+ */
+
+enum ec_cfg_keyboard_backlight_type {
+	KEYBOARD_BACKLIGHT_DISABLED = 0,
+	KEYBOARD_BACKLIGHT_ENABLED = 1
+};
+
+union marasov_cbi_fw_config {
+	struct {
+		enum ec_cfg_keyboard_backlight_type kb_bl : 1;
+		uint32_t audio : 3;
+		uint32_t ufc : 1;
+		uint32_t reserved_1 : 25;
+		uint32_t storage : 2;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Read the cached FW_CONFIG.  Guaranteed to have valid values.
+ *
+ * @return the FW_CONFIG for the board.
+ */
+union marasov_cbi_fw_config get_fw_config(void);
+
+/**
+ * Get the keyboard backlight type from FW_CONFIG.
+ *
+ * @return the keyboard backlight type.
+ */
+enum ec_cfg_keyboard_backlight_type ec_cfg_kb_bl_type(void);
+
+#endif /* __BOARD_MARASOV_FW_CONFIG_H_ */
diff --git a/board/marasov/generated-gpio.inc b/board/marasov/generated-gpio.inc
new file mode 100644
index 0000000000..e3a76ab142
--- /dev/null
+++ b/board/marasov/generated-gpio.inc
@@ -0,0 +1,126 @@
+/*
+ * This file was auto-generated.
+ */
+
+/* INTERRUPT GPIOs: */
+GPIO_INT(ACOK_OD,                        PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
+GPIO_INT(EC_PROCHOT_IN_L,                PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
+GPIO_INT(EC_WP_ODL,                      PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(GSC_EC_PWR_BTN_ODL,             PIN(0, 1), GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW, power_button_interrupt)
+GPIO_INT(LID_OPEN,                       PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
+GPIO_INT(SEQ_EC_ALL_SYS_PG,              PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_DSW_PWROK,               PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_RSMRST_ODL,              PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,                       PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,                      PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SYS_SLP_S0IX_L,                 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(USB_C0_TCPC_INT_ODL,            PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C0_PPC_INT_ODL,             PIN(6, 2), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C1_PPC_INT_ODL,             PIN(F, 5), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C1_TCPC_INT_ODL,            PIN(A, 2), GPIO_INT_FALLING, tcpc_alert_event)
+
+/* USED GPIOs: */
+GPIO(CCD_MODE_ODL,                   PIN(E, 5), GPIO_INPUT)
+GPIO(CHARGER_VAP_OTG_EN,             PIN(7, 3), GPIO_OUT_LOW)
+GPIO(CPU_C10_GATE_L,                 PIN(6, 7), GPIO_INPUT)
+GPIO(EC_BATT_PRES_ODL,               PIN(A, 3), GPIO_INPUT)
+GPIO(EC_ENTERING_RW,                 PIN(0, 3), GPIO_OUT_LOW)
+GPIO(EC_EN_EDP_BL,                   PIN(D, 3), GPIO_OUT_HIGH)
+GPIO(EC_GSC_PACKET_MODE,             PIN(7, 5), GPIO_OUT_LOW)
+GPIO(EC_I2C_BAT_SCL,                 PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_BAT_SDA,                 PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SCL_R,              PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SDA_R,              PIN(B, 2), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,              PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SENSOR_SDA,              PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_USB_C0_PPC_BC_SCL,       PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_PPC_BC_SDA,       PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_TCPC_SCL,         PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_TCPC_SDA,         PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_MIX_SCL,          PIN(E, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_MIX_SDA,          PIN(E, 3), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_TCPC_SCL,         PIN(F, 3), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_TCPC_SDA,         PIN(F, 2), GPIO_INPUT)
+GPIO(EC_KB_BL_EN_L,                  PIN(8, 6), GPIO_OUT_HIGH)
+GPIO(EC_PCHHOT_ODL,                  PIN(7, 4), GPIO_INPUT)
+GPIO(EC_PCH_INT_ODL,                 PIN(B, 0), GPIO_ODR_HIGH)
+GPIO(EC_PCH_PWR_BTN_ODL,             PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(EC_PCH_RSMRST_L,                PIN(A, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_RTCRST,                  PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_SYS_PWROK,               PIN(3, 7), GPIO_OUT_LOW)
+GPIO(EC_PCH_WAKE_R_ODL,              PIN(C, 0), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_ODL,                 PIN(6, 3), GPIO_ODR_HIGH)
+GPIO(EN_PP5000_FAN,                  PIN(6, 1), GPIO_OUT_LOW)
+GPIO(EN_PP5000_USBA_R,               PIN(D, 7), GPIO_OUT_LOW)
+GPIO(EN_S5_RAILS,                    PIN(B, 6), GPIO_OUT_LOW)
+GPIO(IMVP9_VRRDY_OD,                 PIN(4, 3), GPIO_INPUT)
+GPIO(PCH_PWROK,                      PIN(7, 2), GPIO_OUT_LOW)
+GPIO(SYS_RST_ODL,                    PIN(C, 5), GPIO_ODR_HIGH)
+GPIO(USB_C0_TCPC_RST_ODL,            PIN(A, 7), GPIO_ODR_LOW)
+GPIO(USB_C1_FRS_EN,                  PIN(9, 4), GPIO_OUT_LOW)
+GPIO(USB_C1_OC_ODL,                  PIN(9, 6), GPIO_ODR_HIGH)
+GPIO(USB_C1_RT_INT_ODL,              PIN(A, 0), GPIO_INPUT)
+GPIO(USB_C1_RT_RST_R_ODL,            PIN(0, 2), GPIO_ODR_LOW)
+GPIO(VCCST_PWRGD_OD,                 PIN(A, 4), GPIO_ODR_LOW)
+GPIO(PWR_LED_W_ODL,                  PIN(6, 0), GPIO_OUT_HIGH)
+GPIO(PWR_LED_A_ODL,                  PIN(C, 2), GPIO_OUT_HIGH)
+
+/* UART alternate functions */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)              /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */
+
+/* I2C alternate functions */
+ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)               /* GPIO33/I2C5_SCL0/CTS_L, GPIO36/RTS_L/I2C5_SDA0 */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)               /* GPIO87/I2C1_SDA0 */
+ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)               /* GPIO92/I2C2_SCL0, GPIO91/I2C2_SDA0, GPIO90/I2C1_SCL0 */
+ALTERNATE(PIN_MASK(B, 0x0c), 0, MODULE_I2C, 0)               /* GPIOB3/I2C7_SCL0/DCD_L, GPIOB2/I2C7_SDA0/DSR_L */
+ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, GPIO_SEL_1P8V)   /* GPIOB5/I2C0_SCL0, GPIOB4/I2C0_SDA0 */
+ALTERNATE(PIN_MASK(E, 0x18), 0, MODULE_I2C, 0)               /* GPIOE4/I2C6_SCL1/I3C_SCL, GPIOE3/I2C6_SDA1/I3C_SDA */
+ALTERNATE(PIN_MASK(F, 0x0c), 0, MODULE_I2C, 0)               /* GPIOF3/I2C4_SCL1, GPIOF2/I2C4_SDA1 */
+
+/* PWM alternate functions */
+ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0)               /* GPIO40/TA1 */
+ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)               /* GPIO80/PWM3 */
+ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)               /* GPIOB7/PWM5 */
+
+/* ADC alternate functions */
+ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0)               /* GPIO34/PS2_DAT2/ADC6 */
+ALTERNATE(PIN_MASK(4, 0x34), 0, MODULE_ADC, 0)               /* GPIO42/ADC3/RI_L, GPIO45/ADC0, GPIO44/ADC1 */
+ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0)               /* GPIOE1/ADC7 */
+
+/* KB alternate functions */
+ALTERNATE(PIN_MASK(0, 0xf0), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO10&P80_CLK/GPIO07, KSO11&P80_DAT/GPIO06, KSO12/GPIO05, KSO13/GPIO04 */
+ALTERNATE(PIN_MASK(1, 0x7f), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO06/GPO13/GP_SEL_L, KSO07/GPO12/JEN_L, KSO03/GPIO16/JTAG_TDO0_SWO, KSO04/GPIO15/XNOR, KSO05/GPIO14, KSO08/GPIO11/CR_SOUT1, KSO09/GPIO10/CR_SIN1 */
+ALTERNATE(PIN_MASK(2, 0xfc), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI2/GPIO27/TRACEDATA1, KSI3/GPIO26/TRACEDATA0, KSI4/GPIO25/TRACECLK/GP_SCLK, KSI5/GPIO24/GP_MISO, KSI6/GPIO23/S_SBUB, KSI7/GPIO22/S_SBUA */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO00/GPIO21/JTAG_TCK_SWCLK, KSO01/GPIO20/JTAG_TMS_SWIO */
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI0/GPIO31/TRACEDATA3/GP_MOSI, KSI1/GPIO30/TRACEDATA2/GP_CS_L */
+ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO14/GPIO82 */
+
+/* PMU alternate functions */
+ALTERNATE(PIN_MASK(0, 0x01), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN2_L&GPI00/GPIO00 */
+ALTERNATE(PIN_MASK(0, 0x02), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW) /* GPIO01/PSL_IN3_L&GPI01 */
+ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN1_L&GPID2/GPIOD2 */
+
+/* Unused Pins */
+UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
+UNUSED(PIN(3, 2))       /* GPO32/TRIS_L */
+UNUSED(PIN(3, 5))       /* GPO35/CR_SOUT4/TEST_L */
+UNUSED(PIN(6, 6))       /* GPIO66 */
+UNUSED(PIN(5, 7))       /* GPIO57/SER_IRQ/ESPI_ALERT_L */
+UNUSED(PIN(9, 5))	/* GPIO95 */
+UNUSED(PIN(8, 1))	/* GPIO81 */
+UNUSED(PIN(5, 6))	/* GPIO56 */
+UNUSED(PIN(D, 4))	/* GPIOD4 */
+UNUSED(PIN(9, 3))	/* GPIO93 */
+UNUSED(PIN(9, 7))	/* GPIO97 */
+UNUSED(PIN(C, 3))	/* GPIOC3 */
+UNUSED(PIN(C, 4))	/* GPIOC4 */
+UNUSED(PIN(C, 6))	/* GPIOC6 */
+UNUSED(PIN(5, 0))	/* GPIO50 */
+UNUSED(PIN(8, 3))	/* GPIO83 */
+UNUSED(PIN(7, 0))	/* GPIO70 */
+UNUSED(PIN(4, 1))	/* GPIO41 */
+UNUSED(PIN(B, 1))	/* GPIOB1 */
+UNUSED(PIN(D, 0))	/* GPIOD0 */
+UNUSED(PIN(D, 1))	/* GPIOD1 */
+
+/* Pre-configured PSL balls:  J8  K6 */
diff --git a/board/marasov/gpio.inc b/board/marasov/gpio.inc
new file mode 100644
index 0000000000..d4a2ff2d67
--- /dev/null
+++ b/board/marasov/gpio.inc
@@ -0,0 +1,38 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define MODULE_KB		MODULE_KEYBOARD_SCAN
+
+/*
+ * Generated-gpio.inc is produced using a Brya specific tool that
+ * parses the GPIO definitions derived from the board schematics and
+ * EC pinout descriptions derived form the chip datasheets to generate
+ * the Chrome EC GPIO pinout definitions. Due to the confidential
+ * nature of schematics and datasheets, they are not provided here.
+ *
+ * Variants that do not auto-generate their GPIO definitions should
+ * combine the Brya gpio.inc and generated-gpio.inc into their
+ * gpio.inc and customize as appropriate.
+ */
+
+#include "generated-gpio.inc"
+
+/*
+ * The NPCX keyboard driver does not use named GPIOs to access
+ * keyboard scan pins, so we do not list them in *gpio.inc. However, when
+ * KEYBOARD_COL2_INVERTED is defined, this name is required.
+ */
+GPIO(EC_KSO_02_INV,               PIN(1, 7), GPIO_OUT_LOW)
+
+/* IO expander configuration */
+
+/* GPIO02_P2 to PU */
+/* GPIO03_P2 to PU */
+IOEX(USB_C0_OC_ODL,          EXPIN(IOEX_C0_NCT38XX, 0, 4), GPIO_ODR_HIGH)
+IOEX(USB_C0_FRS_EN,          EXPIN(IOEX_C0_NCT38XX, 0, 6), GPIO_OUT_LOW)
+IOEX(USB_C0_RT_RST_ODL,      EXPIN(IOEX_C0_NCT38XX, 0, 7), GPIO_ODR_LOW)
+/* GPIO07_P2 to PU */
diff --git a/board/marasov/i2c.c b/board/marasov/i2c.c
new file mode 100644
index 0000000000..846be8947a
--- /dev/null
+++ b/board/marasov/i2c.c
@@ -0,0 +1,73 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "hooks.h"
+#include "i2c.h"
+
+/* I2C port map configuration */
+const struct i2c_port_t i2c_ports[] = {
+	{
+		/* I2C0 */
+		.name = "sensor",
+		.port = I2C_PORT_SENSOR,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_SENSOR_SCL,
+		.sda = GPIO_EC_I2C_SENSOR_SDA,
+	},
+	{
+		/* I2C1 */
+		.name = "tcpc0,2",
+		.port = I2C_PORT_USB_C0_TCPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_TCPC_SDA,
+	},
+	{
+		/* I2C2 */
+		.name = "ppc0,2",
+		.port = I2C_PORT_USB_C0_PPC,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_USB_C0_PPC_BC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_PPC_BC_SDA,
+	},
+	{
+		/* I2C4 C1 TCPC */
+		.name = "tcpc1",
+		.port = I2C_PORT_USB_C1_TCPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C1_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C1_TCPC_SDA,
+		.flags = I2C_PORT_FLAG_DYNAMIC_SPEED,
+	},
+	{
+		/* I2C5 */
+		.name = "battery",
+		.port = I2C_PORT_BATTERY,
+		.kbps = 100,
+		.scl = GPIO_EC_I2C_BAT_SCL,
+		.sda = GPIO_EC_I2C_BAT_SDA,
+	},
+	{
+		/* I2C6 */
+		.name = "ppc1",
+		.port = I2C_PORT_USB_C1_PPC,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_USB_C1_MIX_SCL,
+		.sda = GPIO_EC_I2C_USB_C1_MIX_SDA,
+		.flags = I2C_PORT_FLAG_DYNAMIC_SPEED,
+	},
+	{
+		/* I2C7 */
+		.name = "eeprom",
+		.port = I2C_PORT_EEPROM,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_MISC_SCL_R,
+		.sda = GPIO_EC_I2C_MISC_SDA_R,
+	},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/board/marasov/keyboard.c b/board/marasov/keyboard.c
new file mode 100644
index 0000000000..e75af0b516
--- /dev/null
+++ b/board/marasov/keyboard.c
@@ -0,0 +1,48 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "ec_commands.h"
+#include "keyboard_scan.h"
+#include "timer.h"
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/* Increase from 50 us, because KSO_02 passes through the H1. */
+	.output_settle_us = 80,
+	/* Other values should be the same as the default configuration. */
+	.debounce_down_us = 9 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x1c, 0xfe, 0xff, 0xff, 0xff, 0xf5, 0xff,
+		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
+	},
+};
+
+static const struct ec_response_keybd_config marasov_kb = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &marasov_kb;
+}
diff --git a/board/marasov/led.c b/board/marasov/led.c
new file mode 100644
index 0000000000..74005005cb
--- /dev/null
+++ b/board/marasov/led.c
@@ -0,0 +1,101 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "chipset.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
+
+__override const int led_charge_lvl_1;
+__override const int led_charge_lvl_2 = 95;
+
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_WHITE,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_BATTERY_LED,
+};
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_WHITE:
+		gpio_set_level(GPIO_PWR_LED_A_ODL, LED_OFF_LVL);
+		gpio_set_level(GPIO_PWR_LED_W_ODL, LED_ON_LVL);
+		break;
+	case EC_LED_COLOR_AMBER:
+		gpio_set_level(GPIO_PWR_LED_A_ODL, LED_ON_LVL);
+		gpio_set_level(GPIO_PWR_LED_W_ODL, LED_OFF_LVL);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		gpio_set_level(GPIO_PWR_LED_W_ODL, LED_OFF_LVL);
+		gpio_set_level(GPIO_PWR_LED_A_ODL, LED_OFF_LVL);
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_battery(EC_LED_COLOR_WHITE);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(EC_LED_COLOR_AMBER);
+		else
+			led_set_color_battery(LED_OFF);
+	}
+
+	return EC_SUCCESS;
+}
+
+__override enum led_states board_led_get_state(enum led_states desired_state)
+{
+	if (desired_state == STATE_BATTERY_ERROR) {
+		if (chipset_in_state(CHIPSET_STATE_ON))
+			return desired_state;
+		else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
+			return STATE_DISCHARGE_S3;
+		else
+			return STATE_DISCHARGE_S5;
+	}
+	return desired_state;
+}
diff --git a/board/marasov/pwm.c b/board/marasov/pwm.c
new file mode 100644
index 0000000000..a1ffcbef30
--- /dev/null
+++ b/board/marasov/pwm.c
@@ -0,0 +1,37 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "hooks.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_KBLIGHT] = {
+		.channel = 3,
+		.flags = 0,
+		/*
+		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
+		 * flicker. Higher frequencies consume similar average power to
+		 * lower PWM frequencies, but higher frequencies record a much
+		 * lower maximum power.
+		 */
+		.freq = 12000,
+	},
+	[PWM_CH_FAN] = {
+		.channel = 5,
+		.flags = PWM_CONFIG_OPEN_DRAIN,
+		.freq = 25000,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+static void board_pwm_init(void)
+{
+	pwm_enable(PWM_CH_KBLIGHT, 1);
+	pwm_set_duty(PWM_CH_KBLIGHT, 50);
+}
+DECLARE_HOOK(HOOK_INIT, board_pwm_init, HOOK_PRIO_DEFAULT);
diff --git a/board/marasov/sensors.c b/board/marasov/sensors.c
new file mode 100644
index 0000000000..090377419d
--- /dev/null
+++ b/board/marasov/sensors.c
@@ -0,0 +1,141 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc.h"
+#include "common.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
+#include "thermal.h"
+
+/* ADC configuration */
+struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_1_DDR_SOC] = {
+		.name = "TEMP_DDR_SOC",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_2_AMBIENT] = {
+		.name = "TEMP_AMBIENT",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_3_CHARGER] = {
+		.name = "TEMP_CHARGER",
+		.input_ch = NPCX_ADC_CH6,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_4_WWAN] = {
+		.name = "TEMP_WWAN",
+		.input_ch = NPCX_ADC_CH7,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* Temperature sensor configuration */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1_DDR_SOC] = {
+		.name = "DDR and SOC",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_1_DDR_SOC,
+	},
+	[TEMP_SENSOR_2_AMBIENT] = {
+		.name = "Ambient",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_2_AMBIENT,
+	},
+	[TEMP_SENSOR_3_CHARGER] = {
+		.name = "Charger",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_3_CHARGER,
+	},
+	[TEMP_SENSOR_4_WWAN] = {
+		.name = "WWAN",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_4_WWAN,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(80), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(92), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+		}, \
+		.temp_fan_off = C_TO_K(40), \
+		.temp_fan_max = C_TO_K(80), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
+
+#define THERMAL_AMBIENT          \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(80), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(92), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+		}, \
+		.temp_fan_off = C_TO_K(40), \
+		.temp_fan_max = C_TO_K(80), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_ambient =
+	THERMAL_AMBIENT;
+
+#define THERMAL_CHARGER          \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(80), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(92), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+		}, \
+		.temp_fan_off = C_TO_K(40), \
+		.temp_fan_max = C_TO_K(80), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_charger =
+	THERMAL_CHARGER;
+
+#define THERMAL_WWAN             \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(80), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(65), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(92), \
+		}, \
+		.temp_fan_off = C_TO_K(40), \
+		.temp_fan_max = C_TO_K(80), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_wwan =
+	THERMAL_WWAN;
+
+struct ec_thermal_config thermal_params[] = {
+	[TEMP_SENSOR_1_DDR_SOC] = THERMAL_CPU,
+	[TEMP_SENSOR_2_AMBIENT] = THERMAL_AMBIENT,
+	[TEMP_SENSOR_3_CHARGER] = THERMAL_CHARGER,
+	[TEMP_SENSOR_4_WWAN] = THERMAL_WWAN,
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
diff --git a/board/marasov/usbc_config.c b/board/marasov/usbc_config.c
new file mode 100644
index 0000000000..2fa5efea5f
--- /dev/null
+++ b/board/marasov/usbc_config.c
@@ -0,0 +1,327 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/ppc/syv682x_public.h"
+#include "driver/tcpm/nct38xx.h"
+#include "driver/tcpm/ps8xxx_public.h"
+#include "driver/tcpm/tcpci.h"
+#include "ec_commands.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "ioexpander.h"
+#include "system.h"
+#include "task.h"
+#include "task_id.h"
+#include "timer.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+#ifdef CONFIG_ZEPHYR
+enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_PORT_COUNT };
+#endif /* CONFIG_ZEPHYR */
+
+#ifndef CONFIG_ZEPHYR
+/* USBC TCPC configuration */
+const struct tcpc_config_t tcpc_config[] = {
+	[USBC_PORT_C0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0_TCPC,
+			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_NO_DEBUG_ACC_CONTROL,
+	},
+	[USBC_PORT_C1] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C1_TCPC,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
+			 TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V |
+			 TCPC_FLAGS_CONTROL_FRS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
+BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
+#endif /* !CONFIG_ZEPHYR */
+
+/******************************************************************************/
+/* USB-A charging control */
+
+#ifndef CONFIG_ZEPHYR
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_PP5000_USBA_R,
+};
+#endif
+BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
+
+/******************************************************************************/
+
+#ifndef CONFIG_ZEPHYR
+/* USBC PPC configuration */
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_PPC,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.frs_en = IOEX_USB_C0_FRS_EN,
+		.drv = &syv682x_drv,
+	},
+	[USBC_PORT_C1] = {
+		/* Compatible with Silicon Mitus SM5360A */
+		.i2c_port = I2C_PORT_USB_C1_PPC,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.drv = &syv682x_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
+
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/* USBC mux configuration - Alder Lake includes internal mux */
+static const struct usb_mux_chain usbc0_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+
+/*
+ * USB3 DB mux configuration - the top level mux still needs to be set
+ * to the virtual_usb_mux_driver so the AP gets notified of mux changes
+ * and updates the TCSS configuration on state changes.
+ */
+static const struct usb_mux_chain usbc1_usb3_db_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
+};
+
+const struct usb_mux_chain usb_muxes[] = {
+	[USBC_PORT_C0] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc0_tcss_usb_mux,
+	},
+	[USBC_PORT_C1] = {
+		.mux = &(const struct usb_mux) {
+			/* PS8815 DB */
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc1_usb3_db_retimer,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
+
+/*
+ * USB C0 uses burnside bridge chips and have their reset
+ * controlled by their respective TCPC chips acting as GPIO expanders.
+ *
+ * ioex_init() is normally called before we take the TCPCs out of
+ * reset, so we need to start in disabled mode, then explicitly
+ * call ioex_init().
+ */
+
+struct ioexpander_config_t ioex_config[] = {
+	[IOEX_C0_NCT38XX] = {
+		.i2c_host_port = I2C_PORT_USB_C0_TCPC,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT);
+#endif /* !CONFIG_ZEPHYR */
+
+__override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
+{
+	enum ioex_signal rst_signal;
+
+	if (me->usb_port == USBC_PORT_C0) {
+/* TODO: explore how to handle board id in zephyr*/
+#ifndef CONFIG_ZEPHYR
+		rst_signal = IOEX_USB_C0_RT_RST_ODL;
+#else
+		/* On Zephyr use bb_controls generated from DTS */
+		rst_signal = bb_controls[me->usb_port].retimer_rst_gpio;
+#endif /* !CONFIG_ZEPHYR */
+	} else {
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * We do not have a load switch for the burnside bridge chips,
+	 * so we only need to sequence reset.
+	 */
+
+	if (enable) {
+		/*
+		 * Tpw, minimum time from VCC to RESET_N de-assertion is 100us.
+		 * For boards that don't provide a load switch control, the
+		 * retimer_init() function ensures power is up before calling
+		 * this function.
+		 */
+		ioex_set_level(rst_signal, 1);
+		/*
+		 * Allow 1ms time for the retimer to power up lc_domain
+		 * which powers I2C controller within retimer
+		 */
+		msleep(1);
+	} else {
+		ioex_set_level(rst_signal, 0);
+		msleep(1);
+	}
+	return EC_SUCCESS;
+}
+
+void board_reset_pd_mcu(void)
+{
+	enum gpio_signal tcpc_rst;
+
+#ifndef CONFIG_ZEPHYR
+	tcpc_rst = GPIO_USB_C0_TCPC_RST_ODL;
+#else
+	tcpc_rst = GPIO_UNIMPLEMENTED;
+#endif /* !CONFIG_ZEPHYR */
+
+	/*
+	 * TODO(b/179648104): figure out correct timing
+	 */
+
+	gpio_set_level(tcpc_rst, 0);
+	gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 0);
+
+	/*
+	 * delay for power-on to reset-off and min. assertion time
+	 */
+
+	msleep(20);
+
+	gpio_set_level(tcpc_rst, 1);
+	gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 1);
+
+	/* wait for chips to come up */
+
+	msleep(50);
+}
+
+static void board_tcpc_init(void)
+{
+	/* Don't reset TCPCs after initial reset */
+	if (!system_jumped_late())
+		board_reset_pd_mcu();
+
+		/*
+		 * These IO expander pins are implemented using the
+		 * C0 TCPC, so they must be set up after the TCPC has
+		 * been taken out of reset.
+		 */
+#ifndef CONFIG_ZEPHYR
+	ioex_init(IOEX_C0_NCT38XX);
+#else
+	gpio_reset_port(DEVICE_DT_GET(DT_NODELABEL(ioex_port1)));
+#endif
+
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
+
+	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_0;
+
+	if (gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
+
+int ppc_get_alert_status(int port)
+{
+	if (port == USBC_PORT_C0)
+		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
+	else if (port == USBC_PORT_C1)
+		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
+	return 0;
+}
+
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C1);
+		break;
+	default:
+		break;
+	}
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C1);
+		break;
+	default:
+		break;
+	}
+}
+
+__override bool board_is_dts_port(int port)
+{
+	return port == USBC_PORT_C0;
+}
+
+#ifdef CONFIG_USB_PD_VBUS_DETECT_PPC
+int pd_snk_is_vbus_provided(int port)
+{
+	return ppc_is_vbus_present(port);
+}
+#endif
diff --git a/board/marasov/usbc_config.h b/board/marasov/usbc_config.h
new file mode 100644
index 0000000000..1fa7ad4c7a
--- /dev/null
+++ b/board/marasov/usbc_config.h
@@ -0,0 +1,17 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Brya board-specific USB-C configuration */
+
+#ifndef __CROS_EC_USBC_CONFIG_H
+#define __CROS_EC_USBC_CONFIG_H
+
+#ifndef CONFIG_ZEPHYR
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#endif
+
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
+
+#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/marasov/vif_override.xml b/board/marasov/vif_override.xml
new file mode 100644
index 0000000000..6ade5d2f92
--- /dev/null
+++ b/board/marasov/vif_override.xml
@@ -0,0 +1,148 @@
+<?xml version="1.0" encoding="utf-8"?>
+<vif:VIF xmlns="http://usb.org/VendorInfoFile.xsd">
+  <vif:Product_Revision>2</vif:Product_Revision>
+  <vif:TID>0</vif:TID>
+  <vif:Product>
+    <vif:USB4_Num_Internal_Host_Controllers value="1" />
+    <vif:USB4_Num_PCIe_DN_Bridges value="0" />
+    <vif:USB4RouterList>
+      <vif:Usb4Router>
+        <!--USB4 Router 0-->
+        <vif:USB4_Router_ID value="0" />
+        <vif:USB4_Silicon_VID value="32903">8087</vif:USB4_Silicon_VID>
+        <vif:USB4_Num_Lane_Adapters value="4" />
+        <vif:USB4_Num_USB3_DN_Adapters value="1" />
+        <vif:USB4_Num_DP_IN_Adapters value="1" />
+        <vif:USB4_Num_DP_OUT_Adapters value="0" />
+        <vif:USB4_Num_PCIe_DN_Adapters value="4" />
+        <vif:USB4_TBT3_Not_Supported value="0">TBT3 Compatible</vif:USB4_TBT3_Not_Supported>
+        <vif:USB4_PCIe_Wake_Supported value="true" />
+        <vif:USB4_USB3_Wake_Supported value="false" />
+        <vif:USB4_Num_Unused_Adapters value="0" />
+        <vif:USB4_TBT3_VID value="32903">8087</vif:USB4_TBT3_VID>
+        <vif:USB4_PCIe_Switch_Vendor_ID value="32902">8086</vif:USB4_PCIe_Switch_Vendor_ID>
+        <vif:USB4_PCIe_Switch_Device_ID value="39451">9A1B</vif:USB4_PCIe_Switch_Device_ID>
+      </vif:Usb4Router>
+    </vif:USB4RouterList>
+  </vif:Product>
+
+  <vif:Component>
+    <vif:USB4_Max_Speed value="1">Gen 3 (40Gb)</vif:USB4_Max_Speed>
+
+    <!--;USB Host-->
+
+    <vif:Host_Speed value="4">USB 3.2 Gen 2x2</vif:Host_Speed>
+    <vif:Host_Contains_Captive_Retimer value="true" />
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:Host_Suspend_Supported value="true" />
+
+    <!--;PD Source-->
+    <!-- will we ever clear USB_Suspend_Supported? -->
+    <vif:USB_Suspend_May_Be_Cleared value="true" />
+
+    <!-- remove FR_Swap_* when we enable CONFIG_USB_PD_FRS -->
+    <!--;Dual Role-->
+    <vif:FR_Swap_Supported_As_Initial_Sink value="true" />
+    <!--;PD Source-->
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="3">3A @ 5V</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!--Source PDO 1-->
+        <vif:Src_PD_OCP_OC_Debounce value="50">50 msec</vif:Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="360">3600 mA</vif:Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+
+    <!-- SOP Discover ID -->
+    <vif:Product_Type_UFP_SOP value="2">PDUSB Peripheral</vif:Product_Type_UFP_SOP>
+    <vif:Product_Type_DFP_SOP value="2">PDUSB Host</vif:Product_Type_DFP_SOP>
+
+    <!-- USB4 Port -->
+    <vif:USB4_Lane_0_Adapter value="1" />
+    <vif:USB4_UFP_Supported value="false" />
+    <vif:USB4_DFP_Supported value="true" />
+    <vif:USB4_USB3_Tunneling_Supported value="true" />
+    <vif:USB4_DP_Tunneling_Supported value="true" />
+    <vif:USB4_CL1_State_Supported value="true" />
+    <vif:USB4_CL2_State_Supported value="true" />
+    <vif:USB4_Num_Retimers value="1" />
+    <vif:USB4_DP_Bit_Rate value="3">HBR3</vif:USB4_DP_Bit_Rate>
+    <vif:USB4_Num_DP_Lanes value="4">4 Lanes</vif:USB4_Num_DP_Lanes>
+
+  </vif:Component>
+
+  <vif:Component>
+    <vif:USB4_Supported value="false" />
+
+    <!--;USB Host-->
+    <vif:Host_Speed value="2">USB 3.2 Gen 2x1</vif:Host_Speed>
+    <vif:Host_Contains_Captive_Retimer value="true" />
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:Host_Suspend_Supported value="true" />
+
+    <!--;PD Source-->
+    <!-- will we ever clear USB_Suspend_Supported? -->
+    <vif:USB_Suspend_May_Be_Cleared value="true" />
+
+    <!-- remove FR_Swap_* when we enable CONFIG_USB_PD_FRS -->
+    <!--;Dual Role-->
+    <vif:FR_Swap_Supported_As_Initial_Sink value="true" />
+    <!--;PD Source-->
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="3">3A @ 5V</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!--Source PDO 1-->
+        <vif:Src_PD_OCP_OC_Debounce value="50">50 msec</vif:Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="360">3600 mA</vif:Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+
+    <!-- SOP Discover ID -->
+    <vif:Product_Type_UFP_SOP value="3">PSD</vif:Product_Type_UFP_SOP>
+    <vif:Product_Type_DFP_SOP value="2">PDUSB Host</vif:Product_Type_DFP_SOP>
+
+  </vif:Component>
+
+  <vif:Component>
+    <vif:USB4_Max_Speed value="1">Gen 3 (40Gb)</vif:USB4_Max_Speed>
+    <!--;USB Host-->
+    <vif:Host_Speed value="4">USB 3.2 Gen 2x2</vif:Host_Speed>
+    <vif:Host_Contains_Captive_Retimer value="true" />
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:Host_Suspend_Supported value="true" />
+
+    <!--;PD Source-->
+    <!-- will we ever clear USB_Suspend_Supported? -->
+    <vif:USB_Suspend_May_Be_Cleared value="true" />
+
+    <!-- remove FR_Swap_* when we enable CONFIG_USB_PD_FRS -->
+    <!--;Dual Role-->
+    <vif:FR_Swap_Supported_As_Initial_Sink value="true" />
+    <!--;PD Source-->
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="3">3A @ 5V</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!--Source PDO 1-->
+        <vif:Src_PD_OCP_OC_Debounce value="50">50 msec</vif:Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="360">3600 mA</vif:Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+
+    <!-- SOP Discover ID -->
+    <vif:Product_Type_UFP_SOP value="2">PDUSB Peripheral</vif:Product_Type_UFP_SOP>
+    <vif:Product_Type_DFP_SOP value="2">PDUSB Host</vif:Product_Type_DFP_SOP>
+
+    <!-- USB4 Port -->
+    <vif:USB4_Lane_0_Adapter value="1" />
+    <vif:USB4_UFP_Supported value="false" />
+    <vif:USB4_DFP_Supported value="true" />
+    <vif:USB4_USB3_Tunneling_Supported value="true" />
+    <vif:USB4_DP_Tunneling_Supported value="true" />
+    <vif:USB4_CL1_State_Supported value="true" />
+    <vif:USB4_CL2_State_Supported value="true" />
+    <vif:USB4_Num_Retimers value="1" />
+    <vif:USB4_DP_Bit_Rate value="3">HBR3</vif:USB4_DP_Bit_Rate>
+    <vif:USB4_Num_DP_Lanes value="4">4 Lanes</vif:USB4_Num_DP_Lanes>
+
+  </vif:Component>
+</vif:VIF>
diff --git a/board/marzipan/battery.c b/board/marzipan/battery.c
new file mode 100644
index 0000000000..fa3a4ec189
--- /dev/null
+++ b/board/marzipan/battery.c
@@ -0,0 +1,97 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "common.h"
+#include "util.h"
+
+/*
+ * Battery info for all marzipan battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+
+const struct board_batt_params board_battery_info[] = {
+	/* COSMX DM02032XL 333-AC-13-A */
+	[BATTERY_COSMX] = {
+		.fuel_gauge = {
+			.manuf_name = "333-AC-13-A",
+			.device_name = "DM02032XL",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+			}
+		},
+		.batt_info = {
+			.voltage_max            = 8800, /* mV */
+			.voltage_normal         = 7700, /* mV */
+			.voltage_min            = 6000, /* mV */
+			.precharge_current      = 256,  /* mA */
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 45,
+			.charging_min_c         = 0,
+			.charging_max_c         = 45,
+			.discharging_min_c      = -10,
+			.discharging_max_c      = 60,
+		},
+	},
+	/* Simplo DM02032XL 333-AC-13-A */
+	[BATTERY_SIMPLO] = {
+		.fuel_gauge = {
+			.manuf_name = "333-1D-13-A",
+			.device_name = "DM02032XL",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+			}
+		},
+		.batt_info = {
+			.voltage_max            = 8800, /* mV */
+			.voltage_normal         = 7700, /* mV */
+			.voltage_min            = 6000, /* mV */
+			.precharge_current      = 256,  /* mA */
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 45,
+			.charging_min_c         = 0,
+			.charging_max_c         = 45,
+			.discharging_min_c      = -10,
+			.discharging_max_c      = 60,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_COSMX;
diff --git a/board/marzipan/board.c b/board/marzipan/board.c
new file mode 100644
index 0000000000..b2f7ade2ba
--- /dev/null
+++ b/board/marzipan/board.c
@@ -0,0 +1,658 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Marzipan board-specific configuration */
+
+#include "adc_chip.h"
+#include "battery_fuel_gauge.h"
+#include "button.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "driver/accel_bma2x2.h"
+#include "driver/accel_kionix.h"
+#include "driver/accel_kx022.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "driver/accelgyro_icm426xx.h"
+#include "driver/accelgyro_icm_common.h"
+#include "driver/ppc/sn5s330.h"
+#include "driver/tcpm/ps8xxx.h"
+#include "driver/tcpm/tcpci.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "pi3usb9201.h"
+#include "power.h"
+#include "power/qcom.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "shi_chip.h"
+#include "switch.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "usbc_config.h"
+#include "usbc_ocp.h"
+#include "usbc_ppc.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+void usb0_evt(enum gpio_signal signal)
+{
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+
+void usb1_evt(enum gpio_signal signal)
+{
+	usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_SWCTL_INT_ODL:
+		sn5s330_interrupt(0);
+		break;
+	case GPIO_USB_C1_SWCTL_INT_ODL:
+		sn5s330_interrupt(1);
+		break;
+	default:
+		break;
+	}
+}
+
+static void board_connect_c0_sbu_deferred(void)
+{
+	/*
+	 * If CCD_MODE_ODL asserts, it means there's a debug accessory connected
+	 * and we should enable the SBU FETs.
+	 */
+	ppc_set_sbu(0, 1);
+}
+DECLARE_DEFERRED(board_connect_c0_sbu_deferred);
+
+void board_connect_c0_sbu(enum gpio_signal s)
+{
+	hook_call_deferred(&board_connect_c0_sbu_deferred_data, 0);
+}
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/* Use 80 us, because KSO_02 passes through the H1. */
+	.output_settle_us = 80,
+	/*
+	 * Unmask 0x08 in [0] (KSO_00/KSI_03, the new location of Search key);
+	 * as it still uses the legacy location (KSO_01/KSI_00).
+	 */
+	.actual_key_mask = { 0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, 0xa4,
+			     0xff, 0xfe, 0x55, 0xfa, 0xca },
+	/* Other values should be the same as the default configuration. */
+	.debounce_down_us = 9 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+};
+
+/* I2C port map */
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_POWER_SCL,
+	  .sda = GPIO_EC_I2C_POWER_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C0_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C0_PD_SDA },
+	{ .name = "tcpc1",
+	  .port = I2C_PORT_TCPC1,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C1_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C1_PD_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_EEPROM_SCL,
+	  .sda = GPIO_EC_I2C_EEPROM_SDA },
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_SENSOR_SCL,
+	  .sda = GPIO_EC_I2C_SENSOR_SDA },
+};
+
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	/* Measure VBUS through a 1/10 voltage divider */
+	[ADC_VBUS] = { "VBUS", NPCX_ADC_CH1, ADC_MAX_VOLT * 10,
+		       ADC_READ_MAX + 1, 0 },
+	/*
+	 * Adapter current output or battery charging/discharging current (uV)
+	 * 18x amplification on charger side.
+	 */
+	[ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH2, ADC_MAX_VOLT * 1000 / 18,
+			    ADC_READ_MAX + 1, 0 },
+	/*
+	 * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read
+	 * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and
+	 * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we
+	 * only divide by 2 (enough to avoid precision issues).
+	 */
+	[ADC_PSYS] = { "PSYS", NPCX_ADC_CH3,
+		       ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), 2, 0 },
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 },
+	/* TODO(waihong): Assign a proper frequency. */
+	[PWM_CH_DISPLIGHT] = { .channel = 5, .flags = 0, .freq = 4800 },
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+/* Power Path Controller */
+struct ppc_config_t ppc_chips[] = {
+	{ .i2c_port = I2C_PORT_TCPC0,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
+	{ .i2c_port = I2C_PORT_TCPC1,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
+};
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/* TCPC mux configuration */
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TCPC0,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+	},
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TCPC1,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+	},
+};
+
+/*
+ * Port-0/1 USB mux driver.
+ *
+ * The USB mux is handled by TCPC chip and the HPD update is through a GPIO
+ * to AP. But the TCPC chip is also needed to know the HPD status; otherwise,
+ * the mux misbehaves.
+ */
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
+	},
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
+	}
+};
+
+/* BC1.2 */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	{
+		.i2c_port = I2C_PORT_POWER,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+	{
+		.i2c_port = I2C_PORT_EEPROM,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+};
+
+/* Mutexes */
+static struct mutex g_base_mutex;
+static struct mutex g_lid_mutex;
+
+static struct kionix_accel_data g_kx022_data;
+static struct bmi_drv_data_t g_bmi160_data;
+static struct icm_drv_data_t g_icm426xx_data;
+static struct accelgyro_saved_data_t g_bma255_data;
+
+enum base_accelgyro_type {
+	BASE_GYRO_NONE = 0,
+	BASE_GYRO_BMI160 = 1,
+	BASE_GYRO_ICM426XX = 2,
+};
+
+/* Matrix to rotate accelerometer into standard reference frame */
+const mat33_fp_t base_standard_ref_bmi160 = { { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, FLOAT_TO_FP(-1), 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
+
+const mat33_fp_t base_standard_ref_icm426xx = { { 0, FLOAT_TO_FP(1), 0 },
+						{ FLOAT_TO_FP(1), 0, 0 },
+						{ 0, 0, FLOAT_TO_FP(-1) } };
+
+static const mat33_fp_t lid_standard_ref_bma255 = { { FLOAT_TO_FP(-1), 0, 0 },
+						    { 0, FLOAT_TO_FP(-1), 0 },
+						    { 0, 0, FLOAT_TO_FP(1) } };
+
+static const mat33_fp_t lid_standard_ref_kx022 = { { FLOAT_TO_FP(-1), 0, 0 },
+						   { 0, FLOAT_TO_FP(-1), 0 },
+						   { 0, 0, FLOAT_TO_FP(1) } };
+
+struct motion_sensor_t motion_sensors[] = {
+	[LID_ACCEL] = {
+		.name = "Lid Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3_S5,
+		.chip = MOTIONSENSE_CHIP_BMA255,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &bma2x2_accel_drv,
+		.mutex = &g_lid_mutex,
+		.drv_data = &g_bma255_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
+		.rot_standard_ref = &lid_standard_ref_bma255,
+		.default_range = 2, /* g, to support lid angle calculation. */
+		.min_frequency = BMA255_ACCEL_MIN_FREQ,
+		.max_frequency = BMA255_ACCEL_MAX_FREQ,
+		.config = {
+			/* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+			/* Sensor on for lid angle detection */
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+		},
+	},
+	/*
+	 * Note: bmi160: supports accelerometer and gyro sensor
+	 * Requirement: accelerometer sensor must init before gyro sensor
+	 * DO NOT change the order of the following table.
+	 */
+	[BASE_ACCEL] = {
+		.name = "Base Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3_S5,
+		.chip = MOTIONSENSE_CHIP_BMI160,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &bmi160_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = &g_bmi160_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+		.rot_standard_ref = &base_standard_ref_bmi160,
+		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
+		.min_frequency = BMI_ACCEL_MIN_FREQ,
+		.max_frequency = BMI_ACCEL_MAX_FREQ,
+		.config = {
+			/* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+			/* Sensor on for lid angle detection */
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+		},
+	},
+	[BASE_GYRO] = {
+		.name = "Gyro",
+		.active_mask = SENSOR_ACTIVE_S0_S3_S5,
+		.chip = MOTIONSENSE_CHIP_BMI160,
+		.type = MOTIONSENSE_TYPE_GYRO,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &bmi160_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = &g_bmi160_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+		.default_range = 1000, /* dps */
+		.rot_standard_ref = &base_standard_ref_bmi160,
+		.min_frequency = BMI_GYRO_MIN_FREQ,
+		.max_frequency = BMI_GYRO_MAX_FREQ,
+	},
+};
+unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+struct motion_sensor_t kx022_lid_accel = {
+	.name = "Lid Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3_S5,
+	.chip = MOTIONSENSE_CHIP_KX022,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_LID,
+	.drv = &kionix_accel_drv,
+	.mutex = &g_lid_mutex,
+	.drv_data = &g_kx022_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = KX022_ADDR0_FLAGS,
+	.rot_standard_ref = &lid_standard_ref_kx022,
+	.default_range = 2, /* g, enough for laptop. */
+	.min_frequency = KX022_ACCEL_MIN_FREQ,
+	.max_frequency = KX022_ACCEL_MAX_FREQ,
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	},
+};
+
+struct motion_sensor_t icm426xx_base_accel = {
+	.name = "Base Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3_S5,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
+	.rot_standard_ref = &base_standard_ref_icm426xx,
+	.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
+	.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	},
+};
+
+struct motion_sensor_t icm426xx_base_gyro = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3_S5,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &base_standard_ref_icm426xx,
+	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
+	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
+};
+
+static int base_accelgyro_config;
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	switch (base_accelgyro_config) {
+	case BASE_GYRO_ICM426XX:
+		icm426xx_interrupt(signal);
+		break;
+	case BASE_GYRO_BMI160:
+	default:
+		bmi160_interrupt(signal);
+		break;
+	}
+}
+
+static void board_detect_motionsensor(void)
+{
+	int ret;
+	int val;
+
+	/* Check lid accel chip */
+	ret = i2c_read8(I2C_PORT_SENSOR, BMA2x2_I2C_ADDR1_FLAGS,
+			BMA2x2_CHIP_ID_ADDR, &val);
+	if (ret)
+		motion_sensors[LID_ACCEL] = kx022_lid_accel;
+
+	CPRINTS("Lid Accel: %s", ret ? "KX022" : "BMA255");
+
+	/* Check base accelgyro chip */
+	ret = icm_read8(&icm426xx_base_accel, ICM426XX_REG_WHO_AM_I, &val);
+	if (val == ICM426XX_CHIP_ICM40608) {
+		motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
+		motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
+	}
+
+	base_accelgyro_config = (val == ICM426XX_CHIP_ICM40608) ?
+					BASE_GYRO_ICM426XX :
+					BASE_GYRO_BMI160;
+	CPRINTS("Base Accelgyro: %s",
+		(val == ICM426XX_CHIP_ICM40608) ? "ICM40608" : "BMI160");
+}
+
+/* Initialize board. */
+static void board_init(void)
+{
+	/* Enable BC1.2 interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_L);
+	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L);
+
+	/*
+	 * The H1 SBU line for CCD are behind PPC chip. The PPC internal FETs
+	 * for SBU may be disconnected after DP alt mode is off. Should enable
+	 * the CCD_MODE_ODL interrupt to make sure the SBU FETs are connected.
+	 */
+	gpio_enable_interrupt(GPIO_CCD_MODE_ODL);
+
+	/* Set the backlight duty cycle to 0. AP will override it later. */
+	pwm_set_duty(PWM_CH_DISPLIGHT, 0);
+
+	board_detect_motionsensor();
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+void board_hibernate(void)
+{
+	int i;
+
+	/*
+	 * Enable the PPC power sink path before EC enters hibernate;
+	 * otherwise, ACOK won't go High and can't wake EC up. Check the
+	 * bug b/170324206 for details.
+	 */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
+		ppc_vbus_sink_enable(i, 1);
+}
+
+void board_tcpc_init(void)
+{
+	/* Only reset TCPC if not sysjump */
+	if (!system_jumped_late()) {
+		/* TODO(crosbug.com/p/61098): How long do we need to wait? */
+		board_reset_pd_mcu();
+	}
+
+	/* Enable PPC interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_SWCTL_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_SWCTL_INT_ODL);
+
+	/* Enable TCPC interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL);
+
+	/*
+	 * Initialize HPD to low; after sysjump SOC needs to see
+	 * HPD pulse to enable video path
+	 */
+	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
+		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
+
+/* Called on AP S0 -> S3 transition */
+static void board_chipset_suspend(void)
+{
+	/*
+	 * Turn off display backlight in S3. AP has its own control. The EC's
+	 * and the AP's will be AND'ed together in hardware.
+	 */
+	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 0);
+	pwm_enable(PWM_CH_DISPLIGHT, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S3 -> S0 transition */
+static void board_chipset_resume(void)
+{
+	/* Turn on display and keyboard backlight in S0. */
+	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 1);
+	if (pwm_get_duty(PWM_CH_DISPLIGHT))
+		pwm_enable(PWM_CH_DISPLIGHT, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
+
+void board_reset_pd_mcu(void)
+{
+	cprints(CC_USB, "Resetting TCPCs...");
+	cflush();
+
+	gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
+	gpio_set_level(GPIO_USB_C1_PD_RST_L, 0);
+	msleep(PS8XXX_RESET_DELAY_MS);
+	gpio_set_level(GPIO_USB_C0_PD_RST_L, 1);
+	gpio_set_level(GPIO_USB_C1_PD_RST_L, 1);
+}
+
+void board_set_tcpc_power_mode(int port, int mode)
+{
+	/* Ignore the "mode" to turn the chip on.  We can only do a reset. */
+	if (mode)
+		return;
+
+	board_reset_pd_mcu();
+}
+
+int board_vbus_sink_enable(int port, int enable)
+{
+	/* Both ports are controlled by PPC SN5S330 */
+	return ppc_vbus_sink_enable(port, enable);
+}
+
+int board_is_sourcing_vbus(int port)
+{
+	/* Both ports are controlled by PPC SN5S330 */
+	return ppc_is_sourcing_vbus(port);
+}
+
+void board_overcurrent_event(int port, int is_overcurrented)
+{
+	/* TODO(b/120231371): Notify AP */
+	CPRINTS("p%d: overcurrent!", port);
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int i;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTS("Disabling all charging port");
+
+		/* Disable all ports. */
+		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (board_vbus_sink_enable(i, 0))
+				CPRINTS("Disabling p%d sink path failed.", i);
+		}
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (board_is_sourcing_vbus(port)) {
+		CPRINTS("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTS("New charge port: p%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		if (i == port)
+			continue;
+
+		if (board_vbus_sink_enable(i, 0))
+			CPRINTS("p%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (board_vbus_sink_enable(port, 1)) {
+		CPRINTS("p%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
+{
+	/*
+	 * Ignore lower charge ceiling on PD transition if our battery is
+	 * critical, as we may brownout.
+	 */
+	if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 &&
+	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
+		CPRINTS("Using max ilim %d", max_ma);
+		charge_ma = max_ma;
+	}
+
+	charge_set_input_current_limit(charge_ma, charge_mv);
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
+		if (gpio_get_level(GPIO_USB_C0_PD_RST_L))
+			status |= PD_STATUS_TCPC_ALERT_0;
+	if (!gpio_get_level(GPIO_USB_C1_PD_INT_ODL))
+		if (gpio_get_level(GPIO_USB_C1_PD_RST_L))
+			status |= PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
diff --git a/board/marzipan/board.h b/board/marzipan/board.h
new file mode 100644
index 0000000000..c651e55965
--- /dev/null
+++ b/board/marzipan/board.h
@@ -0,0 +1,101 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Marzipan board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "baseboard.h"
+
+/* Internal SPI flash on NPCX7 */
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */
+
+/* Keyboard */
+#define CONFIG_KEYBOARD_PROTOCOL_MKBP
+
+#define CONFIG_PWM_KBLIGHT
+
+/* Battery */
+#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
+#define CONFIG_BATTERY_REVIVE_DISCONNECT
+#define CONFIG_BATTERY_FUEL_GAUGE
+
+/* BC 1.2 Charger */
+#define CONFIG_BC12_DETECT_PI3USB9201
+
+/* USB */
+#define CONFIG_USB_PD_TCPM_PS8755
+#define CONFIG_USBC_PPC_SN5S330
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+
+/* Sensors */
+#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
+
+/* BMI160 Base accel/gyro */
+#define CONFIG_ACCELGYRO_BMI160
+#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+#define OPT3001_I2C_ADDR_FLAGS OPT3001_I2C_ADDR1_FLAGS
+
+/* ICM426XX Base accel/gyro */
+#define CONFIG_ACCELGYRO_ICM426XX
+#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+/* KX022 lid accel */
+#define CONFIG_ACCEL_KX022
+
+/* BMA253 lid accel */
+#define CONFIG_ACCEL_BMA255
+#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
+
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+#define CONFIG_LID_ANGLE_UPDATE
+
+#define CONFIG_TABLET_MODE
+#define CONFIG_TABLET_MODE_SWITCH
+#define CONFIG_GMR_TABLET_MODE
+
+/* GPIO alias */
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_WP_L GPIO_EC_WP_ODL
+#define GPIO_PMIC_RESIN_L GPIO_PM845_RESIN_L
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum adc_channel { ADC_VBUS, ADC_AMON_BMON, ADC_PSYS, ADC_CH_COUNT };
+
+/* Motion sensors */
+enum sensor_id {
+	LID_ACCEL = 0,
+	BASE_ACCEL,
+	BASE_GYRO,
+	SENSOR_COUNT,
+};
+
+enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_DISPLIGHT, PWM_CH_COUNT };
+
+/* List of possible batteries */
+enum battery_type {
+	BATTERY_COSMX,
+	BATTERY_SIMPLO,
+	BATTERY_TYPE_COUNT,
+};
+
+/* Reset all TCPCs. */
+void board_reset_pd_mcu(void);
+void board_set_tcpc_power_mode(int port, int mode);
+/* Motion sensor interrupt */
+void motion_interrupt(enum gpio_signal signal);
+
+#endif /* !defined(__ASSEMBLER__) */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/marzipan/build.mk b/board/marzipan/build.mk
new file mode 100644
index 0000000000..048f0787f7
--- /dev/null
+++ b/board/marzipan/build.mk
@@ -0,0 +1,18 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx7
+CHIP_VARIANT:=npcx7m6fc
+BASEBOARD:=trogdor
+
+board-y+=battery.o
+board-y+=board.o
+board-y+=led.o
+board-y+=switchcap.o
+board-y+=usbc_config.o
diff --git a/board/marzipan/ec.tasklist b/board/marzipan/ec.tasklist
new file mode 100644
index 0000000000..228828af3c
--- /dev/null
+++ b/board/marzipan/ec.tasklist
@@ -0,0 +1,23 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/marzipan/gpio.inc b/board/marzipan/gpio.inc
new file mode 100644
index 0000000000..633f689c66
--- /dev/null
+++ b/board/marzipan/gpio.inc
@@ -0,0 +1,185 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+/* USB interrupts */
+GPIO_INT(USB_C0_PD_INT_ODL,    PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-0 TCPC */
+GPIO_INT(USB_C1_PD_INT_ODL,    PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-1 TCPC */
+GPIO_INT(USB_C0_SWCTL_INT_ODL, PIN(0, 3), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-0 PPC */
+GPIO_INT(USB_C1_SWCTL_INT_ODL, PIN(4, 0), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-1 PPC */
+GPIO_INT(USB_C0_BC12_INT_L,    PIN(6, 1), GPIO_INT_FALLING | GPIO_PULL_UP, usb0_evt)  /* Interrupt from port-0 BC1.2 */
+GPIO_INT(USB_C1_BC12_INT_L,    PIN(8, 2), GPIO_INT_FALLING | GPIO_PULL_UP, usb1_evt)  /* Interrupt from port-1 BC1.2 */
+
+/* System interrupts */
+GPIO_INT(ACOK_OD,           PIN(0, 0), GPIO_INT_BOTH, extpower_interrupt)  /* ACOK */
+GPIO_INT(CCD_MODE_ODL,      PIN(E, 3), GPIO_INT_FALLING, board_connect_c0_sbu)  /* Case Closed Debug Mode */
+GPIO_INT(EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)  /* Power button */
+GPIO_INT(EC_VOLDN_BTN_ODL,  PIN(7, 0), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Up button */
+GPIO_INT(EC_VOLUP_BTN_ODL,  PIN(F, 2), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Down button */
+GPIO_INT(EC_WP_ODL,         PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)  /* Write protection */
+GPIO_INT(LID_OPEN_EC,       PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)  /* Lid open */
+GPIO_INT(AP_RST_L,          PIN(C, 1), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_ap_rst_interrupt)  /* PMIC to signal AP reset */
+GPIO_INT(PS_HOLD,           PIN(A, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, power_signal_interrupt)  /* Indicate when AP triggers reset/shutdown */
+GPIO_INT(AP_SUSPEND,        PIN(5, 7), GPIO_INT_BOTH, power_signal_interrupt)  /* Suspend signal from PMIC */
+GPIO_INT(DEPRECATED_AP_RST_REQ, PIN(C, 2), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V, power_signal_interrupt) /* Deprecated AP initiated reset indicator */
+/*
+ * When switch-cap is off, the POWER_GOOD signal is floating. Need a pull-down
+ * to make it low. Overload the interrupt function chipset_warm_reset_interrupt
+ * for not only signalling power_signal_interrupt but also handling the logic
+ * of WARM_RESET_L which is pulled-up by the same rail of POWER_GOOD.
+ */
+GPIO_INT(POWER_GOOD,        PIN(5, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, chipset_power_good_interrupt)  /* SRC_PP1800_S10A from PMIC */
+GPIO_INT(WARM_RESET_L,      PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_warm_reset_interrupt)  /* AP warm reset */
+GPIO_INT(AP_EC_SPI_CS_L,    PIN(5, 3), GPIO_INT_FALLING | GPIO_PULL_DOWN, shi_cs_event)  /* EC SPI Chip Select */
+
+/* Sensor interrupts */
+GPIO_INT(TABLET_MODE_L,     PIN(C, 6), GPIO_INT_BOTH, gmr_tablet_switch_isr)
+GPIO_INT(ACCEL_GYRO_INT_L,  PIN(A, 0), GPIO_INT_FALLING, motion_interrupt)  /* Accelerometer/gyro interrupt */
+
+/*
+ * EC_RST_ODL used to be a wake source from PSL mode. However, we disabled
+ * the PSL mode. This GPIO does nothing now. Simply set it an INPUT.
+ */
+GPIO(EC_RST_ODL,            PIN(0, 2), GPIO_INPUT)     /* EC reset */
+GPIO(EC_ENTERING_RW,        PIN(E, 1), GPIO_OUT_LOW)   /* Indicate when EC is entering RW code */
+GPIO(EC_BATT_PRES_ODL,      PIN(E, 5), GPIO_INPUT)     /* Battery Present */
+
+/* PMIC/AP 1.8V */
+GPIO(PM845_RESIN_L,         PIN(3, 2), GPIO_ODR_HIGH)  /* PMIC reset trigger */
+GPIO(PMIC_KPD_PWR_ODL,      PIN(D, 6), GPIO_ODR_HIGH)  /* PMIC power button */
+GPIO(EC_INT_L,              PIN(A, 2), GPIO_ODR_HIGH)  /* Interrupt line between AP and EC */
+GPIO(QSIP_ON,               PIN(5, 0), GPIO_OUT_LOW)   /* Not used, for non-switchcap testing */
+
+/* Power enables */
+GPIO(HIBERNATE_L,           PIN(5, 2), GPIO_ODR_HIGH)  /* EC hibernate */
+GPIO(SWITCHCAP_ON,          PIN(D, 5), GPIO_OUT_LOW)   /* Enable switch cap; will be configured in the board init */
+GPIO(EN_PP3300_A,           PIN(A, 6), GPIO_OUT_LOW)   /* Enable PP3300 */
+GPIO(EN_PP5000_A,           PIN(6, 7), GPIO_OUT_LOW)   /* Enable PP5000 */
+GPIO(EC_BL_DISABLE_L,       PIN(B, 6), GPIO_OUT_LOW)   /* Backlight disable signal from EC */
+
+/* Sensors */
+GPIO(LID_ACCEL_INT_L,       PIN(5, 6), GPIO_INPUT)     /* Lid accel sensor interrupt */
+/* Control the gate for trackpad IRQ. High closes the gate.
+ * This is always set low so that the OS can manage the trackpad. */
+GPIO(TRACKPAD_INT_GATE,     PIN(7, 4), GPIO_OUT_LOW)
+
+/* USB-C */
+GPIO(USB_C0_PD_RST_L,       PIN(F, 1), GPIO_ODR_HIGH)  /* Port-0 TCPC chip reset, actaully Open-Drain */
+GPIO(USB_C1_PD_RST_L,       PIN(E, 4), GPIO_ODR_HIGH)  /* Port-1 TCPC chip reset, actually Open-Drain */
+GPIO(DP_MUX_OE_L,           PIN(9, 6), GPIO_ODR_HIGH)  /* DP mux enable, actually Open-Drain */
+GPIO(DP_MUX_SEL,            PIN(4, 5), GPIO_OUT_LOW)   /* DP mux selection: L:C0, H:C1 */
+GPIO(DP_HOT_PLUG_DET,       PIN(9, 5), GPIO_OUT_LOW)   /* DP HPD to AP */
+
+/* LEDs */
+GPIO(EC_CHG_LED_Y_C1,       PIN(C, 3), GPIO_OUT_LOW)
+GPIO(EC_CHG_LED_B_C1,       PIN(C, 4), GPIO_OUT_LOW)
+
+/*
+ * SPI host interface - enable PDs by default. These will be made functional
+ * by the SHI driver when the AP powers up, and restored back to GPIO when
+ * the AP powers down.
+ */
+GPIO(AP_EC_SPI_MOSI,        PIN(4, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(AP_EC_SPI_MISO,        PIN(4, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(AP_EC_SPI_CLK,         PIN(5, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+
+/* PWM */
+GPIO(KB_BL_PWM,             PIN(8, 0), GPIO_INPUT)     /* PWM3 */
+GPIO(EDP_BKLTCTL,           PIN(B, 7), GPIO_INPUT)     /* PWM5 */
+
+/* ADC */
+GPIO(PPVAR_BOOSTIN_SENSE,   PIN(4, 4), GPIO_INPUT)     /* ADC1 */
+GPIO(CHARGER_IADP,          PIN(4, 3), GPIO_INPUT)     /* ADC2 */
+GPIO(CHARGER_PMON,          PIN(4, 2), GPIO_INPUT)     /* ADC3 */
+
+/* I2C */
+GPIO(EC_I2C_POWER_SCL,      PIN(B, 5), GPIO_INPUT)
+GPIO(EC_I2C_POWER_SDA,      PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_PD_SCL,  PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_PD_SDA,  PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_PD_SCL,  PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_PD_SDA,  PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SCL,     PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SDA,     PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,     PIN(B, 3), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SENSOR_SDA,     PIN(B, 2), GPIO_INPUT | GPIO_SEL_1P8V)
+
+/* Board/SKU IDs */
+GPIO(BRD_ID0,               PIN(C, 7), GPIO_INPUT)
+GPIO(BRD_ID1,               PIN(9, 3), GPIO_INPUT)
+GPIO(BRD_ID2,               PIN(6, 3), GPIO_INPUT)
+GPIO(SKU_ID0,               PIN(F, 0), GPIO_INPUT)
+GPIO(SKU_ID1,               PIN(4, 1), GPIO_INPUT)
+GPIO(SKU_ID2,               PIN(D, 4), GPIO_INPUT)
+
+/* Switchcap */
+/*
+ * GPIO0 is configured as PVC_PG. When the chip in power down mode, it outputs
+ * high-Z. Set pull-down to avoid floating.
+ */
+GPIO(DA9313_GPIO0,          PIN(E, 2), GPIO_INPUT | GPIO_PULL_DOWN) /* Switchcap GPIO0 */
+
+/* Special straps */
+GPIO(ARM_X86,               PIN(6, 6), GPIO_OUT_LOW)  /* NC, low for power saving */
+
+/* Unused GPIOs, NC. */
+UNUSED(PIN(5, 1))
+UNUSED(PIN(D, 0))
+UNUSED(PIN(F, 3))
+UNUSED(PIN(0, 4))
+UNUSED(PIN(C, 0))
+UNUSED(PIN(A, 7))
+UNUSED(PIN(8, 3))
+UNUSED(PIN(8, 1))
+UNUSED(PIN(3, 7))
+UNUSED(PIN(7, 6))
+UNUSED(PIN(3, 4))
+UNUSED(PIN(C, 5))
+UNUSED(PIN(A, 3))
+UNUSED(PIN(7, 3))
+UNUSED(PIN(D, 7))
+UNUSED(PIN(A, 5))
+UNUSED(PIN(B, 0))
+UNUSED(PIN(9, 4))
+UNUSED(PIN(B, 1))
+UNUSED(PIN(6, 2))
+UNUSED(PIN(3, 5))
+UNUSED(PIN(9, 7))
+UNUSED(PIN(6, 0))
+UNUSED(PIN(7, 2))
+UNUSED(PIN(D, 3))
+UNUSED(PIN(8, 6))
+UNUSED(PIN(7, 5))
+UNUSED(PIN(D, 1))
+
+/* Alternate functions GPIO definitions */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)            /* UART (GPIO64/65) */
+ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0)             /* I2C0 (GPIOB4/B5) */
+ALTERNATE(PIN_MASK(9, 0x07), 1, MODULE_I2C, 0)             /* I2C1 SDA (GPIO90), I2C2 (GPIO91/92) */
+ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, 0)             /* I2C1 SCL (GPIO87) */
+ALTERNATE(PIN_MASK(3, 0x48), 1, MODULE_I2C, 0)             /* I2C5 (GPIO33/36) */
+ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, GPIO_SEL_1P8V) /* I2C7 (GPIOB2/B3) - 1.8V */
+ALTERNATE(PIN_MASK(4, 0x1C), 0, MODULE_ADC, 0)             /* ADC1 (GPIO44), ADC2 (GPIO43), ADC3 (GPIO42) */
+ALTERNATE(PIN_MASK(4, 0xC0), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SDO (GPIO47), SHI_SDI (GPIO46) */
+ALTERNATE(PIN_MASK(5, 0x28), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SCLK (GPIO55), SHI_CS# (GPIO53) */
+ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)             /* PWM3 (GPIO80) - KB_BL_PWM */
+ALTERNATE(PIN_MASK(B, 0x80), 1, MODULE_PWM, 0)             /* PWM5 (GPIOB7) - EDP_BKLTCTL */
+
+/* Keyboard */
+#define GPIO_KB_INPUT           (GPIO_INPUT | GPIO_PULL_UP)
+#define GPIO_KB_OUTPUT          (GPIO_ODR_HIGH)
+#define GPIO_KB_OUTPUT_COL2     (GPIO_OUT_LOW)
+
+/* Keyboard alternate functions */
+ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)  /* KSO10 (GPIO07), KSO11 (GPIO06), KSO12 (GPIO05) */
+ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)  /* KSO03 (GPIO16), KSO04 (GPIO15), KSO05 (GPIO14), KSO06 (GPIO13), KSO07 (GPIO12), KSO08 (GPIO11), KSO09 (GPIO10) */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)  /* KSO00 (GPIO21), KSO01 (GPIO20) */
+ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)   /* KSI2 (GPIO27), KSI3 (GPIO26), KSI4 (GPIO25), KSI5 (GPIO24), KSI6 (GPIO23), KSI7 (GPIO22) */
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)   /* KSI0 (GPIO31), KSI1 (GPIO30) */
+GPIO(EC_KSO_02_INV,       PIN(1, 7), GPIO_KB_OUTPUT_COL2)              /* KSO02 (GPIO17) */
diff --git a/board/marzipan/led.c b/board/marzipan/led.c
new file mode 100644
index 0000000000..b2fc45abe1
--- /dev/null
+++ b/board/marzipan/led.c
@@ -0,0 +1,154 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power and battery LED control.
+ */
+
+#include "battery.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "chipset.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "led_common.h"
+#include "system.h"
+#include "util.h"
+
+#define LED_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS)
+
+#define BAT_LED_ON 1
+#define BAT_LED_OFF 0
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_BATTERY_LED,
+};
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+enum led_color {
+	LED_OFF = 0,
+	LED_AMBER,
+	LED_BLUE,
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
+};
+
+static void led_set_color(enum led_color color)
+{
+	gpio_set_level(GPIO_EC_CHG_LED_Y_C1,
+		       (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
+	gpio_set_level(GPIO_EC_CHG_LED_B_C1,
+		       (color == LED_BLUE) ? BAT_LED_ON : BAT_LED_OFF);
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	brightness_range[EC_LED_COLOR_AMBER] = 1;
+	brightness_range[EC_LED_COLOR_BLUE] = 1;
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (brightness[EC_LED_COLOR_BLUE] != 0)
+		led_set_color(LED_BLUE);
+	else if (brightness[EC_LED_COLOR_AMBER] != 0)
+		led_set_color(LED_AMBER);
+	else
+		led_set_color(LED_OFF);
+
+	return EC_SUCCESS;
+}
+
+static void board_led_set_battery(void)
+{
+	static int battery_ticks;
+	int color = LED_OFF;
+	int period = 0;
+
+	battery_ticks++;
+
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
+		/* Always indicate amber on when charging. */
+		color = LED_AMBER;
+		break;
+	case LED_PWRS_DISCHARGE:
+		if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
+			/* Discharging in S3: Amber 1 sec, off 3 sec */
+			period = (1 + 3) * LED_ONE_SEC;
+			battery_ticks = battery_ticks % period;
+			if (battery_ticks < 1 * LED_ONE_SEC)
+				color = LED_AMBER;
+			else
+				color = LED_OFF;
+		} else if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
+			/* Discharging in S5: off */
+			color = LED_OFF;
+		} else if (chipset_in_state(CHIPSET_STATE_ON)) {
+			/* Discharging in S0: Blue on */
+			color = LED_BLUE;
+		}
+		break;
+	case LED_PWRS_ERROR:
+		/* Battery error: Amber 1 sec, off 1 sec */
+		period = (1 + 1) * LED_ONE_SEC;
+		battery_ticks = battery_ticks % period;
+		if (battery_ticks < 1 * LED_ONE_SEC)
+			color = LED_AMBER;
+		else
+			color = LED_OFF;
+		break;
+	case LED_PWRS_CHARGE_NEAR_FULL:
+		/* Full Charged: Blue on */
+		color = LED_BLUE;
+		break;
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		color = LED_BLUE;
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		/* Factory mode: Blue 2 sec, Amber 2 sec */
+		period = (2 + 2) * LED_ONE_SEC;
+		battery_ticks = battery_ticks % period;
+		if (battery_ticks < 2 * LED_ONE_SEC)
+			color = LED_BLUE;
+		else
+			color = LED_AMBER;
+		break;
+	default:
+		/* Other states don't alter LED behavior */
+		break;
+	}
+
+	led_set_color(color);
+}
+
+/* Called by hook task every TICK */
+static void led_tick(void)
+{
+	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
+		board_led_set_battery();
+}
+DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
+
+void led_control(enum ec_led_id led_id, enum ec_led_state state)
+{
+	enum led_color color;
+
+	if ((led_id != EC_LED_ID_RECOVERY_HW_REINIT_LED) &&
+	    (led_id != EC_LED_ID_SYSRQ_DEBUG_LED))
+		return;
+
+	if (state == LED_STATE_RESET) {
+		led_auto_control(EC_LED_ID_BATTERY_LED, 1);
+		board_led_set_battery();
+		return;
+	}
+
+	color = state ? LED_BLUE : LED_OFF;
+
+	led_auto_control(EC_LED_ID_BATTERY_LED, 0);
+
+	led_set_color(color);
+}
diff --git a/board/marzipan/switchcap.c b/board/marzipan/switchcap.c
new file mode 100644
index 0000000000..853f677f27
--- /dev/null
+++ b/board/marzipan/switchcap.c
@@ -0,0 +1,31 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "config.h"
+#include "console.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "power/qcom.h"
+#include "system.h"
+
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args)
+
+void board_set_switchcap_power(int enable)
+{
+	gpio_set_level(GPIO_SWITCHCAP_ON, enable);
+}
+
+int board_is_switchcap_enabled(void)
+{
+	return gpio_get_level(GPIO_SWITCHCAP_ON);
+}
+
+int board_is_switchcap_power_good(void)
+{
+	return gpio_get_level(GPIO_DA9313_GPIO0);
+}
diff --git a/board/marzipan/usbc_config.c b/board/marzipan/usbc_config.c
new file mode 100644
index 0000000000..f7e9bd6220
--- /dev/null
+++ b/board/marzipan/usbc_config.c
@@ -0,0 +1,80 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Marzipan board-specific USB-C configuration */
+
+#include "charge_state.h"
+#include "charger.h"
+#include "charger/isl923x_public.h"
+#include "usb_pd.h"
+#include "usbc_config.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+};
+
+int charger_profile_override(struct charge_state_data *curr)
+{
+	int usb_mv;
+	int port;
+
+	if (curr->state != ST_CHARGE)
+		return 0;
+
+	/* Lower the max requested voltage to 5V when battery is full. */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
+	    !(curr->batt.flags & BATT_FLAG_BAD_STATUS) &&
+	    !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
+	    (curr->batt.status & STATUS_FULLY_CHARGED))
+		usb_mv = 5000;
+	else
+		usb_mv = PD_MAX_VOLTAGE_MV;
+
+	if (pd_get_max_voltage() != usb_mv) {
+		CPRINTS("VBUS limited to %dmV", usb_mv);
+		for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++)
+			pd_set_external_voltage_limit(port, usb_mv);
+	}
+
+	return 0;
+}
+
+enum ec_status charger_profile_override_get_param(uint32_t param,
+						  uint32_t *value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+enum ec_status charger_profile_override_set_param(uint32_t param,
+						  uint32_t value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+/* GPIO Interrupt Handlers */
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	int port = -1;
+
+	switch (signal) {
+	case GPIO_USB_C0_PD_INT_ODL:
+		port = 0;
+		break;
+	case GPIO_USB_C1_PD_INT_ODL:
+		port = 1;
+		break;
+	default:
+		return;
+	}
+
+	schedule_deferred_pd_interrupt(port);
+}
diff --git a/board/marzipan/usbc_config.h b/board/marzipan/usbc_config.h
new file mode 100644
index 0000000000..56cdb155ea
--- /dev/null
+++ b/board/marzipan/usbc_config.h
@@ -0,0 +1,19 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Marzipan board-specific USB-C configuration */
+
+#ifndef __CROS_EC_USBC_CONFIG_H
+#define __CROS_EC_USBC_CONFIG_H
+
+#include "gpio.h"
+
+void tcpc_alert_event(enum gpio_signal signal);
+void usb0_evt(enum gpio_signal signal);
+void usb1_evt(enum gpio_signal signal);
+void ppc_interrupt(enum gpio_signal signal);
+void board_connect_c0_sbu(enum gpio_signal s);
+
+#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/marzipan/vif_override.xml b/board/marzipan/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/marzipan/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/max32660-eval/board.c b/board/max32660-eval/board.c
index 15a856ab4e..442469ba27 100644
--- a/board/max32660-eval/board.c
+++ b/board/max32660-eval/board.c
@@ -1,19 +1,21 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* MAX32660 EvalKit Board Specific Configuration */
 
-#include "i2c.h"
-#include "board.h"
+#include "config.h"
 #include "console.h"
 #include "ec_commands.h"
 #include "gpio.h"
 #include "hooks.h"
-#include "timer.h"
+#include "i2c.h"
 #include "registers.h"
+#include "timer.h"
 #include "util.h"
+
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 #define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
diff --git a/board/max32660-eval/board.h b/board/max32660-eval/board.h
index 87a4b65fa1..9061b0b958 100644
--- a/board/max32660-eval/board.h
+++ b/board/max32660-eval/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,7 +11,7 @@
 /* Optional features */
 #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands */
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_CONTROLLER
 
 #define CONFIG_FPU
 
@@ -24,8 +24,8 @@
 #undef CONFIG_HOSTCMD_EVENTS
 #define CONFIG_I2C
 
-#define CONFIG_I2C_SLAVE
-#define CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS (0x51) /* 7 bit right-aligned, bits 6 to 0 */
+#define CONFIG_I2C_PERIPHERAL
+#define CONFIG_HOSTCMD_I2C_ADDR_FLAGS (0x51) /* 7 bit right-aligned */
 
 /* Slave I2C port configuration */
 #define I2C_PORT_SLAVE 1
diff --git a/board/max32660-eval/build.mk b/board/max32660-eval/build.mk
index a613922cd2..3e50dd9a00 100644
--- a/board/max32660-eval/build.mk
+++ b/board/max32660-eval/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/max32660-eval/ec.tasklist b/board/max32660-eval/ec.tasklist
index 5e58b9dea8..c92b25295b 100644
--- a/board/max32660-eval/ec.tasklist
+++ b/board/max32660-eval/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/max32660-eval/gpio.inc b/board/max32660-eval/gpio.inc
index 3ced37a77f..e7397e11a4 100644
--- a/board/max32660-eval/gpio.inc
+++ b/board/max32660-eval/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/mchpevb1/battery.c b/board/mchpevb1/battery.c
index fcc09994bf..d8f7496fa0 100644
--- a/board/mchpevb1/battery.c
+++ b/board/mchpevb1/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -14,15 +14,15 @@
 #include "util.h"
 
 /* Shutdown mode parameter to write to manufacturer access register */
-#define PARAM_CUT_OFF_LOW  0x10
+#define PARAM_CUT_OFF_LOW 0x10
 #define PARAM_CUT_OFF_HIGH 0x00
 
 /* Battery info for BQ40Z55 */
 static const struct battery_info info = {
-	.voltage_max = 8700,        /* mV */
+	.voltage_max = 8700, /* mV */
 	.voltage_normal = 7600,
 	.voltage_min = 6000,
-	.precharge_current = 256,   /* mA */
+	.precharge_current = 256, /* mA */
 	.start_charging_min_c = 0,
 	.start_charging_max_c = 46,
 	.charging_min_c = 0,
@@ -47,10 +47,10 @@ int board_cut_off_battery(void)
 	buf[2] = PARAM_CUT_OFF_HIGH;
 
 	i2c_lock(I2C_PORT_BATTERY, 1);
-	rv = i2c_xfer_unlocked(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS,
-			       buf, 3, NULL, 0, I2C_XFER_SINGLE);
-	rv |= i2c_xfer_unlocked(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS,
-				buf, 3, NULL, 0, I2C_XFER_SINGLE);
+	rv = i2c_xfer_unlocked(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS, buf, 3,
+			       NULL, 0, I2C_XFER_SINGLE);
+	rv |= i2c_xfer_unlocked(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS, buf, 3,
+				NULL, 0, I2C_XFER_SINGLE);
 	i2c_lock(I2C_PORT_BATTERY, 0);
 
 	return rv;
@@ -214,7 +214,7 @@ enum ec_status charger_profile_override_set_param(uint32_t param,
 	return EC_RES_INVALID_PARAM;
 }
 
-static int command_fastcharge(int argc, char **argv)
+static int command_fastcharge(int argc, const char **argv)
 {
 	if (argc > 1 && !parse_bool(argv[1], &fast_charging_allowed))
 		return EC_ERROR_PARAM1;
@@ -223,8 +223,7 @@ static int command_fastcharge(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(fastcharge, command_fastcharge,
-			"[on|off]",
+DECLARE_CONSOLE_COMMAND(fastcharge, command_fastcharge, "[on|off]",
 			"Get or set fast charging profile");
 
-#endif	/* CONFIG_CHARGER_PROFILE_OVERRIDE */
+#endif /* CONFIG_CHARGER_PROFILE_OVERRIDE */
diff --git a/board/mchpevb1/board.c b/board/mchpevb1/board.c
index 79f104ff55..c10520276b 100644
--- a/board/mchpevb1/board.c
+++ b/board/mchpevb1/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,8 @@
  */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "als.h"
+#include "battery_smart.h"
 #include "bd99992gw.h"
 #include "button.h"
 #include "charge_manager.h"
@@ -20,24 +20,24 @@
 #include "charger.h"
 #include "chipset.h"
 #include "console.h"
-#include "driver/als_opt3001.h"
 #include "driver/accel_kionix.h"
 #include "driver/accel_kx022.h"
 #include "driver/accelgyro_bmi_common.h"
+#include "driver/als_opt3001.h"
 #include "driver/tcpm/tcpci.h"
+#include "espi.h"
 #include "extpower.h"
-#include "gpio_chip.h"
 #include "gpio.h"
+#include "gpio_chip.h"
 #include "hooks.h"
 #include "host_command.h"
 #include "i2c.h"
-#include "espi.h"
-#include "lpc_chip.h"
 #include "keyboard_scan.h"
 #include "lid_switch.h"
+#include "lpc_chip.h"
 #include "math_util.h"
-#include "motion_sense.h"
 #include "motion_lid.h"
+#include "motion_sense.h"
 #include "pi3usb9281.h"
 #include "power.h"
 #include "power_button.h"
@@ -54,31 +54,28 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 #include "util.h"
-#include "espi.h"
-#include "battery_smart.h"
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* NOTE: MEC17xx EVB + SKL RVP3 does not use BD99992 PMIC.
  * RVP3 PMIC controlled by RVP3 logic.
  */
-#define I2C_ADDR_BD99992_FLAGS	0x30
+#define I2C_ADDR_BD99992_FLAGS 0x30
 
 /*
  * Maxim DS1624 I2C temperature sensor used for testing I2C.
  * DS1624 contains one internal temperature sensor
  * and EEPROM. It has no external temperature inputs.
  */
-#define DS1624_I2C_ADDR_FLAGS	(0x48 | I2C_FLAG_BIG_ENDIAN)
-#define DS1624_IDX_LOCAL	0
-#define DS1624_READ_TEMP16	0xAA	/* read 16-bit temperature */
-#define DS1624_ACCESS_CFG	0xAC	/* read/write 8-bit config */
-#define DS1624_CMD_START	0xEE
-#define DS1624_CMD_STOP		0x22
+#define DS1624_I2C_ADDR_FLAGS (0x48 | I2C_FLAG_BIG_ENDIAN)
+#define DS1624_IDX_LOCAL 0
+#define DS1624_READ_TEMP16 0xAA /* read 16-bit temperature */
+#define DS1624_ACCESS_CFG 0xAC /* read/write 8-bit config */
+#define DS1624_CMD_START 0xEE
+#define DS1624_CMD_STOP 0x22
 
 /*
  * static global and routine to return smart battery
@@ -88,10 +85,8 @@ static int smart_batt_temp;
 static int ds1624_temp;
 static int sb_temp(int idx, int *temp_ptr);
 static int ds1624_get_val(int idx, int *temp_ptr);
-#ifdef HAS_TASK_MOTIONSENSE
 static void board_spi_enable(void);
 static void board_spi_disable(void);
-#endif
 
 #ifdef CONFIG_BOARD_PRE_INIT
 /*
@@ -119,7 +114,6 @@ void board_config_pre_init(void)
 }
 #endif /* #ifdef CONFIG_BOARD_PRE_INIT */
 
-
 /*
  * Use EC to handle ALL_SYS_PWRGD signal.
  * MEC17xx connected to SKL/KBL RVP3 reference board
@@ -138,8 +132,8 @@ static void board_all_sys_pwrgd(void)
 
 	CPRINTS("ALL_SYS_PWRGD=%d SYS_RESET_L=%d", allsys_in, allsys_out);
 
-	trace2(0, BRD, 0, "ALL_SYS_PWRGD=%d SYS_RESET_L=%d",
-			allsys_in, allsys_out);
+	trace2(0, BRD, 0, "ALL_SYS_PWRGD=%d SYS_RESET_L=%d", allsys_in,
+	       allsys_out);
 
 	/*
 	 * Wait at least 10 ms between power signals going high
@@ -164,14 +158,12 @@ void all_sys_pwrgd_interrupt(enum gpio_signal signal)
 }
 #endif /* #ifdef CONFIG_BOARD_HAS_ALL_SYS_PWRGD */
 
-
 #ifdef HAS_TASK_PDCMD
 /* Exchange status with PD MCU. */
 static void pd_mcu_interrupt(enum gpio_signal signal)
 {
 	/* Exchange status with PD MCU to determine interrupt cause */
 	host_command_pd_send_status(0);
-
 }
 #endif
 
@@ -192,12 +184,12 @@ void vbus1_evt(enum gpio_signal signal)
 
 void usb0_evt(enum gpio_signal signal)
 {
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
 }
 
 void usb1_evt(enum gpio_signal signal)
 {
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12, 0);
+	usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
 }
 #endif
 
@@ -213,6 +205,7 @@ void tablet_mode_interrupt(enum gpio_signal signal)
 	hook_call_deferred(&enable_input_devices_data, 0);
 }
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /* ADC channels
@@ -220,21 +213,29 @@ void tablet_mode_interrupt(enum gpio_signal signal)
  */
 const struct adc_t adc_channels[] = {
 	/* Vbus sensing. Converted to mV, full ADC is equivalent to 30V. */
-	[ADC_VBUS] = {"VBUS", 30000, 1024, 0, 1},
+	[ADC_VBUS] = { "VBUS", 30000, 1024, 0, 1 },
 	/* Adapter current output or battery discharging current */
-	[ADC_AMON_BMON] = {"AMON_BMON", 25000, 3072, 0, 3},
+	[ADC_AMON_BMON] = { "AMON_BMON", 25000, 3072, 0, 3 },
 	/* System current consumption */
-	[ADC_PSYS] = {"PSYS", 1, 1, 0, 4},
-	[ADC_CASE] = {"CASE", 1, 1, 0, 7},
+	[ADC_PSYS] = { "PSYS", 1, 1, 0, 4 },
+	[ADC_CASE] = { "CASE", 1, 1, 0, 7 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /*
  * MCHP EVB connected to KBL RVP3
  */
-const struct i2c_port_t i2c_ports[]  = {
-	{"sensors",  MCHP_I2C_PORT4, 100,  GPIO_SMB04_SCL, GPIO_SMB04_SDA},
-	{"batt",     MCHP_I2C_PORT5, 100,  GPIO_SMB05_SCL, GPIO_SMB05_SDA},
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "sensors",
+	  .port = MCHP_I2C_PORT4,
+	  .kbps = 100,
+	  .scl = GPIO_SMB04_SCL,
+	  .sda = GPIO_SMB04_SDA },
+	{ .name = "batt",
+	  .port = MCHP_I2C_PORT5,
+	  .kbps = 100,
+	  .scl = GPIO_SMB05_SCL,
+	  .sda = GPIO_SMB05_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -264,53 +265,15 @@ int board_i2c_p2c(int port)
 
 #ifdef CONFIG_USB_POWER_DELIVERY
 const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{I2C_PORT_TCPC,
-	 CONFIG_TCPC_I2C_BASE_ADDR_FLAGS,
-	 &tcpci_tcpm_drv},
+	{ I2C_PORT_TCPC, CONFIG_TCPC_I2C_BASE_ADDR_FLAGS, &tcpci_tcpm_drv },
 
-	{I2C_PORT_TCPC,
-	 CONFIG_TCPC_I2C_BASE_ADDR_FLAGS + 1,
-	 &tcpci_tcpm_drv},
+	{ I2C_PORT_TCPC, CONFIG_TCPC_I2C_BASE_ADDR_FLAGS + 1, &tcpci_tcpm_drv },
 };
 #endif
 
-const uint32_t i2c_ctrl_slave_addrs[I2C_CONTROLLER_COUNT] = {
-#ifdef CONFIG_BOARD_MCHP_I2C0_SLAVE_ADDRS
-	(MCHP_I2C_CTRL0 + (CONFIG_BOARD_MCHP_I2C0_SLAVE_ADDRS << 16)),
-#else
-	(MCHP_I2C_CTRL0 + (CONFIG_MCHP_I2C0_SLAVE_ADDRS << 16)),
-#endif
-#ifdef CONFIG_BOARD_MCHP_I2C1_SLAVE_ADDRS
-	(MCHP_I2C_CTRL1 + (CONFIG_BOARD_MCHP_I2C1_SLAVE_ADDRS << 16)),
-#else
-	(MCHP_I2C_CTRL1 + (CONFIG_MCHP_I2C1_SLAVE_ADDRS << 16)),
-#endif
-};
-
-/* Return the two slave addresses the specified
- * controller will respond to when controller
- * is acting as a slave.
- * b[6:0]  = b[7:1] of I2C address 1
- * b[14:8] = b[7:1] of I2C address 2
- * When not using I2C controllers as slaves we can use
- * the same value for all controllers. The address should
- * not be 0x00 as this is the general call address.
- */
-uint16_t board_i2c_slave_addrs(int controller)
-{
-	int i;
-
-	for (i = 0; i < I2C_CONTROLLER_COUNT; i++)
-		if ((i2c_ctrl_slave_addrs[i] & 0xffff) == controller)
-			return (i2c_ctrl_slave_addrs[i] >> 16);
-
-	return CONFIG_MCHP_I2C0_SLAVE_ADDRS;
-}
-
-
 /* SPI devices */
 const struct spi_device_t spi_devices[] = {
-	{ QMSPI0_PORT, 4, GPIO_QMSPI_CS0},
+	{ QMSPI0_PORT, 4, GPIO_QMSPI_CS0 },
 #if defined(CONFIG_SPI_ACCEL_PORT)
 	{ GPSPI0_PORT, 2, GPIO_SPI0_CS0 },
 #endif
@@ -324,7 +287,6 @@ const enum gpio_signal hibernate_wake_pins[] = {
 };
 const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 
-
 /*
  * Deep sleep support, called by chip level.
  */
@@ -340,7 +302,7 @@ void board_prepare_for_deep_sleep(void)
 #if defined(CONFIG_GPIO_POWER_DOWN) && \
 	defined(CONFIG_MCHP_DEEP_SLP_GPIO_PWR_DOWN)
 	gpio_power_down_module(MODULE_SPI_FLASH);
-	gpio_power_down_module(MODULE_SPI_MASTER);
+	gpio_power_down_module(MODULE_SPI_CONTROLLER);
 	gpio_power_down_module(MODULE_I2C);
 	/* powering down keyscan is causing an issue with keyscan task
 	 * probably due to spurious interrupts on keyscan pins.
@@ -367,7 +329,7 @@ void board_resume_from_deep_sleep(void)
 #endif
 	/* gpio_config_module(MODULE_KEYBOARD_SCAN, 1); */
 	gpio_config_module(MODULE_SPI_FLASH, 1);
-	gpio_config_module(MODULE_SPI_MASTER, 1);
+	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
 	gpio_config_module(MODULE_I2C, 1);
 #endif
 }
@@ -387,18 +349,24 @@ struct pi3usb9281_config pi3usb9281_chips[] = {
 BUILD_ASSERT(ARRAY_SIZE(pi3usb9281_chips) ==
 	     CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT);
 
-struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
-		.driver = &pi3usb3x532_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX,
+				.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
+				.driver = &pi3usb3x532_usb_mux_driver,
+			},
 	},
 	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = 0x10,
-		.driver = &ps8740_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_USB_MUX,
+				.i2c_addr_flags = 0x10,
+				.driver = &ps8740_usb_mux_driver,
+			},
 	}
 };
 #endif
@@ -454,9 +422,9 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
  * a static global in this module.
  */
 const struct temp_sensor_t temp_sensors[] = {
-	{"Battery", TEMP_SENSOR_TYPE_BATTERY, sb_temp, 0},
-	{"Ambient", TEMP_SENSOR_TYPE_BOARD, ds1624_get_val, 0},
-	{"Case", TEMP_SENSOR_TYPE_CASE, therm_get_val, (int)ADC_CASE},
+	{ "Battery", TEMP_SENSOR_TYPE_BATTERY, sb_temp, 0 },
+	{ "Ambient", TEMP_SENSOR_TYPE_BOARD, ds1624_get_val, 0 },
+	{ "Case", TEMP_SENSOR_TYPE_CASE, therm_get_val, (int)ADC_CASE },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 #endif
@@ -465,16 +433,16 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 #ifdef CONFIG_ALS
 /* ALS instances. Must be in same order as enum als_id. */
 struct als_t als[] = {
-	{"TI", opt3001_init, opt3001_read_lux, 5},
+	{ "TI", opt3001_init, opt3001_read_lux, 5 },
 };
 BUILD_ASSERT(ARRAY_SIZE(als) == ALS_COUNT);
 #endif
 
 const struct button_config buttons[CONFIG_BUTTON_COUNT] = {
-	{"Volume Down", KEYBOARD_BUTTON_VOLUME_DOWN, GPIO_VOLUME_DOWN_L,
-	 30 * MSEC, 0},
-	{"Volume Up", KEYBOARD_BUTTON_VOLUME_UP, GPIO_VOLUME_UP_L,
-	 30 * MSEC, 0},
+	{ "Volume Down", KEYBOARD_BUTTON_VOLUME_DOWN, GPIO_VOLUME_DOWN_L,
+	  30 * MSEC, 0 },
+	{ "Volume Up", KEYBOARD_BUTTON_VOLUME_UP, GPIO_VOLUME_UP_L, 30 * MSEC,
+	  0 },
 };
 
 /* MCHP mec1701_evb connected to Intel SKL RVP3 with Kabylake
@@ -515,8 +483,7 @@ static void board_pmic_init(void)
 	cfg = 0x66;
 	rv = i2c_read8(I2C_PORT_THERMAL, DS1624_I2C_ADDR_FLAGS,
 		       DS1624_ACCESS_CFG, &cfg);
-	trace2(0, BRD, 0, "Read DS1624 Config rv = %d  cfg = 0x%02X",
-	       rv, cfg);
+	trace2(0, BRD, 0, "Read DS1624 Config rv = %d  cfg = 0x%02X", rv, cfg);
 
 	if ((rv == EC_SUCCESS) && (cfg & (1u << 0))) {
 		/* one-shot mode switch to continuous */
@@ -561,18 +528,13 @@ static void board_init(void)
 	/* Provide AC status to the PCH */
 	gpio_set_level(GPIO_PCH_ACOK, extpower_is_present());
 
-#ifdef HAS_TASK_MOTIONSENSE
-	if (system_jumped_late() &&
-	    chipset_in_state(CHIPSET_STATE_ON)) {
+	if (system_jumped_late() && chipset_in_state(CHIPSET_STATE_ON)) {
 		trace0(0, BRD, 0, "board_init: S0 call board_spi_enable");
 		board_spi_enable();
 	}
-#endif
-
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
-
 /**
  * Buffer the AC present GPIO to the PCH.
  */
@@ -604,8 +566,7 @@ int board_set_active_charge_port(int charge_port)
 
 	if (is_real_port && source) {
 		CPRINTS("MEC1701 Skip enable p%d", charge_port);
-		trace1(0, BOARD, 0, "Skip enable charge port %d",
-			charge_port);
+		trace1(0, BOARD, 0, "Skip enable charge port %d", charge_port);
 		return EC_ERROR_INVAL;
 	}
 
@@ -619,45 +580,16 @@ int board_set_active_charge_port(int charge_port)
 	} else {
 		/* Make sure non-charging port is disabled */
 		gpio_set_level(charge_port ? GPIO_USB_C0_CHARGE_EN_L :
-					     GPIO_USB_C1_CHARGE_EN_L, 1);
+					     GPIO_USB_C1_CHARGE_EN_L,
+			       1);
 		/* Enable charging port */
 		gpio_set_level(charge_port ? GPIO_USB_C1_CHARGE_EN_L :
-					     GPIO_USB_C0_CHARGE_EN_L, 0);
+					     GPIO_USB_C0_CHARGE_EN_L,
+			       0);
 	}
 
 	return EC_SUCCESS;
 }
-
-/**
- * Set the charge limit based upon desired maximum.
- *
- * @param port          Port number.
- * @param supplier      Charge supplier type.
- * @param charge_ma     Desired charge limit (mA).
- * @param charge_mv     Negotiated charge voltage (mV).
- */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_set_input_current_limit(MAX(charge_ma,
-				   CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
-#else
-/*
- * TODO HACK providing functions from common/charge_state_v2.c
- * which is not compiled in when no charger
- */
-int charge_want_shutdown(void)
-{
-	return 0;
-}
-
-int charge_prevent_power_on(int power_button_pressed)
-{
-	return 0;
-}
-
-
 #endif
 
 /*
@@ -689,23 +621,18 @@ static void board_chipset_startup(void)
 	gpio_set_level(GPIO_USB2_ENABLE, 1);
 	hook_call_deferred(&enable_input_devices_data, 0);
 }
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP,
-		board_chipset_startup,
-		HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
 
 /* Called on AP S3 -> S5 transition */
 static void board_chipset_shutdown(void)
 {
 	CPRINTS("MEC1701 HOOK_CHIPSET_SHUTDOWN board_chipset_shutdown");
-	trace0(0, HOOK, 0,
-	       "HOOK_CHIPSET_SHUTDOWN board_chipset_shutdown");
+	trace0(0, HOOK, 0, "HOOK_CHIPSET_SHUTDOWN board_chipset_shutdown");
 	gpio_set_level(GPIO_USB1_ENABLE, 0);
 	gpio_set_level(GPIO_USB2_ENABLE, 0);
 	hook_call_deferred(&enable_input_devices_data, 0);
 }
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN,
-		board_chipset_shutdown,
-		HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
 
 /* Called on AP S3 -> S0 transition */
 static void board_chipset_resume(void)
@@ -717,10 +644,9 @@ static void board_chipset_resume(void)
 	gpio_set_level(GPIO_PP1800_DX_AUDIO_EN, 1);
 	gpio_set_level(GPIO_PP1800_DX_SENSOR_EN, 1);
 #endif
-
 }
 DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume,
-	     MOTION_SENSE_HOOK_PRIO-1);
+	     MOTION_SENSE_HOOK_PRIO - 1);
 
 /* Called on AP S0 -> S3 transition */
 static void board_chipset_suspend(void)
@@ -733,9 +659,7 @@ static void board_chipset_suspend(void)
 	gpio_set_level(GPIO_PP1800_DX_SENSOR_EN, 0);
 #endif
 }
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND,
-		board_chipset_suspend,
-		HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
 
 void board_hibernate_late(void)
 {
@@ -812,7 +736,6 @@ static void board_handle_reboot(void)
 }
 DECLARE_HOOK(HOOK_INIT, board_handle_reboot, HOOK_PRIO_FIRST);
 
-
 static int sb_temp(int idx, int *temp_ptr)
 {
 	if (idx != 0)
@@ -849,8 +772,8 @@ static void sb_update(void)
 	rv = sb_read(SB_TEMPERATURE, &smart_batt_temp);
 	smart_batt_temp = smart_batt_temp / 10;
 
-	trace12(0, BRD, 0, "sb_read temperature rv=%d  temp=%d K",
-		rv, smart_batt_temp);
+	trace12(0, BRD, 0, "sb_read temperature rv=%d  temp=%d K", rv,
+		smart_batt_temp);
 }
 
 /*
@@ -906,7 +829,6 @@ static void board_one_sec(void)
 }
 DECLARE_HOOK(HOOK_SECOND, board_one_sec, HOOK_PRIO_DEFAULT);
 
-#ifdef HAS_TASK_MOTIONSENSE
 /* Motion sensors */
 
 static struct mutex g_base_mutex;
@@ -935,7 +857,7 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_base_mutex,
 		.drv_data = &g_bmi160_data,
 		.port = CONFIG_SPI_ACCEL_PORT,
-		.i2c_spi_addr_flags = SLAVE_MK_SPI_ADDR_FLAGS(
+		.i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(
 			CONFIG_SPI_ACCEL_PORT),
 		.rot_standard_ref = NULL, /* Identity matrix. */
 		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
@@ -960,7 +882,7 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_base_mutex,
 		.drv_data = &g_bmi160_data,
 		.port = CONFIG_SPI_ACCEL_PORT,
-		.i2c_spi_addr_flags = SLAVE_MK_SPI_ADDR_FLAGS(
+		.i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(
 			CONFIG_SPI_ACCEL_PORT),
 		.default_range = 1000, /* dps */
 		.rot_standard_ref = NULL, /* Identity Matrix. */
@@ -999,7 +921,7 @@ static void board_spi_enable(void)
 {
 	trace0(0, BRD, 0, "HOOK_CHIPSET_STARTUP - board_spi_enable");
 
-	spi_enable(CONFIG_SPI_ACCEL_PORT, 1);
+	spi_enable(&spi_devices[1], 1);
 
 	/* Toggle SPI chip select to switch BMI160 from I2C mode
 	 * to SPI mode
@@ -1014,14 +936,13 @@ DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_spi_enable,
 static void board_spi_disable(void)
 {
 	trace0(0, BRD, 0, "HOOK_CHIPSET_SHUTDOWN - board_spi_disable");
-	spi_enable(CONFIG_SPI_ACCEL_PORT, 0);
+	spi_enable(&spi_devices[1], 0);
 }
 DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_spi_disable,
 	     MOTION_SENSE_HOOK_PRIO + 1);
-#endif /* defined(HAS_TASK_MOTIONSENSE) */
 
 #ifdef MEC1701_EVB_TACH_TEST /* PWM/TACH test */
-void tach0_isr(void)
+static void tach0_isr(void)
 {
 	MCHP_INT_DISABLE(MCHP_TACH_GIRQ) = MCHP_TACH_GIRQ_BIT(0);
 	MCHP_INT_SOURCE(MCHP_TACH_GIRQ) = MCHP_TACH_GIRQ_BIT(0);
diff --git a/board/mchpevb1/board.h b/board/mchpevb1/board.h
index e46a1dced4..dd7c87fd6f 100644
--- a/board/mchpevb1/board.h
+++ b/board/mchpevb1/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -39,6 +39,10 @@
  * #define CONFIG_MCHP_LFW_DEBUG
  */
 
+/*
+ * EC UART console on UART 0 or 1
+ */
+#define CONFIG_UART_CONSOLE 0
 
 /*
  * Override Boot-ROM JTAG mode
@@ -84,7 +88,6 @@
  * #define EVB_NO_ESPI_TEST_MODE
  */
 
-
 /*
  * DEBUG
  * Disable ARM Cortex-M4 write buffer so
@@ -93,24 +96,24 @@
  * #define CONFIG_DEBUG_DISABLE_WRITE_BUFFER
  */
 
-/* New eSPI slave configuration items */
+/* New eSPI configuration items */
 
 /*
- * Maximum clock frequence eSPI EC slave advertises
+ * Maximum clock frequence eSPI EC advertises
  * Values in MHz are 20, 25, 33, 50, and 66
  */
 /* KBL + EVB fly-wire hook up only supports 20MHz */
-#define CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ		20
+#define CONFIG_HOST_INTERFACE_ESPI_EC_MAX_FREQ MCHP_ESPI_CAP1_MAX_FREQ_20M
 
 /*
- * EC eSPI slave advertises IO lanes
+ * EC eSPI advertises IO lanes
  * 0 = Single
  * 1 = Single and Dual
  * 2 = Single and Quad
  * 3 = Single, Dual, and Quad
  */
 /* KBL + EVB fly-wire hook up only support Single mode */
-#define CONFIG_HOSTCMD_ESPI_EC_MODE		0
+#define CONFIG_HOST_INTERFACE_ESPI_EC_MODE MCHP_ESPI_CAP1_SINGLE_MODE
 
 /*
  * Bit map of eSPI channels EC advertises
@@ -119,7 +122,7 @@
  * bit[2] = 1 OOB channel
  * bit[3] = 1 Flash channel
  */
-#define CONFIG_HOSTCMD_ESPI_EC_CHAN_BITMAP	0x0F
+#define CONFIG_HOST_INTERFACE_ESPI_EC_CHAN_BITMAP MCHP_ESPI_CAP0_ALL_CHAN_SUPP
 
 #define CONFIG_MCHP_ESPI_VW_SAVE_ON_SLEEP
 
@@ -142,18 +145,13 @@
 /* #define CONFIG_CHARGE_MANAGER */
 /* #define CONFIG_CHARGE_RAMP_SW */
 
-
 /* #define CONFIG_CHARGER */
 
 /* #define CONFIG_CHARGER_DISCHARGE_ON_AC */
 /* #define CONFIG_CHARGER_ISL9237 */
 /* #define CONFIG_CHARGER_ILIM_PIN_DISABLED */
-/* #define CONFIG_CHARGER_INPUT_CURRENT 512 */
-
-/*
- * MCHP disable this for Kabylake eSPI bring up
- * #define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 1
- */
+/* #define CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT 512 */
+/* #define CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT 512 */
 
 /* #define CONFIG_CHARGER_NARROW_VDC */
 /* #define CONFIG_CHARGER_PROFILE_OVERRIDE */
@@ -164,16 +162,17 @@
 #define CONFIG_CHIPSET_SKYLAKE
 #define CONFIG_CHIPSET_RESET_HOOK
 
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#define CONFIG_HOST_INTERFACE_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
+#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD
 
 #define CONFIG_CLOCK_CRYSTAL
 #define CONFIG_EXTPOWER_GPIO
 /* #define CONFIG_HOSTCMD_PD */
 /* #define CONFIG_HOSTCMD_PD_PANIC */
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_CONTROLLER
 #define CONFIG_KEYBOARD_PROTOCOL_8042
 #define CONFIG_LED_COMMON
 
@@ -190,7 +189,6 @@
  * #define CONFIG_LOW_POWER_IDLE
  */
 
-
 /* #define CONFIG_GPIO_POWER_DOWN */
 
 /*
@@ -270,10 +268,10 @@
  * Configure for smaller flash is OK for testing except
  * for SPI flash lock bit.
  */
- #define CONFIG_FLASH_SIZE 524288
- #define CONFIG_SPI_FLASH_W25X40
+#define CONFIG_FLASH_SIZE_BYTES 524288
+#define CONFIG_SPI_FLASH_W25X40
 /*
- * #define CONFIG_FLASH_SIZE 0x1000000
+ * #define CONFIG_FLASH_SIZE_BYTES 0x1000000
  * #define CONFIG_SPI_FLASH_W25Q128
  */
 
@@ -321,7 +319,7 @@
  * Make sure to not include GPSPI in little-firmware(LFW)
  */
 #ifndef LFW
-#define CONFIG_MCHP_GPSPI	0x01
+#define CONFIG_MCHP_GPSPI 0x01
 #endif
 
 /* SPI Accelerometer
@@ -360,9 +358,8 @@
 #define GPIO_BAT_LED_GREEN GPIO_CHARGE_LED_2
 
 /* I2C ports */
-#define I2C_CONTROLLER_COUNT	2
-#define I2C_PORT_COUNT		2
-
+#define I2C_CONTROLLER_COUNT 2
+#define I2C_PORT_COUNT 2
 
 /*
  * Map I2C Ports to Controllers for this board.
@@ -377,26 +374,26 @@
  * All other ports set to 0xff (not used)
  */
 
-#define I2C_PORT_PMIC           MCHP_I2C_PORT10
-#define I2C_PORT_USB_CHARGER_1	MCHP_I2C_PORT2
-#define I2C_PORT_USB_MUX        MCHP_I2C_PORT2
-#define I2C_PORT_USB_CHARGER_2	MCHP_I2C_PORT2
-#define I2C_PORT_PD_MCU         MCHP_I2C_PORT3
-#define I2C_PORT_TCPC           MCHP_I2C_PORT3
-#define I2C_PORT_ALS            MCHP_I2C_PORT4
-#define I2C_PORT_ACCEL          MCHP_I2C_PORT4
-#define I2C_PORT_BATTERY        MCHP_I2C_PORT5
-#define I2C_PORT_CHARGER        MCHP_I2C_PORT5
+#define I2C_PORT_PMIC MCHP_I2C_PORT10
+#define I2C_PORT_USB_CHARGER_1 MCHP_I2C_PORT2
+#define I2C_PORT_USB_MUX MCHP_I2C_PORT2
+#define I2C_PORT_USB_CHARGER_2 MCHP_I2C_PORT2
+#define I2C_PORT_PD_MCU MCHP_I2C_PORT3
+#define I2C_PORT_TCPC MCHP_I2C_PORT3
+#define I2C_PORT_ALS MCHP_I2C_PORT4
+#define I2C_PORT_ACCEL MCHP_I2C_PORT4
+#define I2C_PORT_BATTERY MCHP_I2C_PORT5
+#define I2C_PORT_CHARGER MCHP_I2C_PORT5
 
 /* Thermal sensors read through PMIC ADC interface */
 #if 0
-#define I2C_PORT_THERMAL	I2C_PORT_PMIC
+#define I2C_PORT_THERMAL I2C_PORT_PMIC
 #else
-#define I2C_PORT_THERMAL	MCHP_I2C_PORT4
+#define I2C_PORT_THERMAL MCHP_I2C_PORT4
 #endif
 
 /* Ambient Light Sensor address */
-#define OPT3001_I2C_ADDR_FLAGS	OPT3001_I2C_ADDR1_FLAGS
+#define OPT3001_I2C_ADDR_FLAGS OPT3001_I2C_ADDR1_FLAGS
 
 /* Modules we want to exclude */
 #undef CONFIG_CMD_HASH
@@ -425,9 +422,9 @@ enum temp_sensor_id {
 	/* These temp sensors are only readable in S0 */
 	TEMP_SENSOR_AMBIENT,
 	TEMP_SENSOR_CASE,
-/*	TEMP_SENSOR_CHARGER, */
-/*	TEMP_SENSOR_DRAM, */
-/*	TEMP_SENSOR_WIFI, */
+	/*	TEMP_SENSOR_CHARGER, */
+	/*	TEMP_SENSOR_DRAM, */
+	/*	TEMP_SENSOR_WIFI, */
 
 	TEMP_SENSOR_COUNT
 };
@@ -453,37 +450,27 @@ enum als_id {
  * delay to turn on the power supply max is ~16ms.
  * delay to turn off the power supply max is about ~180ms.
  */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* delay to turn on/off vconn */
-#define PD_VCONN_SWAP_DELAY 5000 /* us */
 
 /* Define typical operating power and max power */
 #define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       45000
-#define PD_MAX_CURRENT_MA     3000
+#define PD_MAX_POWER_MW 45000
+#define PD_MAX_CURRENT_MA 3000
 
 /* Try to negotiate to 20V since i2c noise problems should be fixed. */
-#define PD_MAX_VOLTAGE_MV     20000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /*
  * include TFDP macros from mchp chip level
  */
 #include "tfdp_chip.h"
 
-
 /* Map I2C port to controller */
 int board_i2c_p2c(int port);
 
-/* Return the two slave addresses the specified
- * controller will respond to when controller
- * is acting as a slave.
- * b[6:0]  = b[7:1] of I2C address 1
- * b[14:8] = b[7:1] of I2C address 2
- */
-uint16_t board_i2c_slave_addrs(int controller);
-
 /* Reset PD MCU */
 void board_reset_pd_mcu(void);
 
diff --git a/board/mchpevb1/build.mk b/board/mchpevb1/build.mk
index ffac227688..c92a045646 100644
--- a/board/mchpevb1/build.mk
+++ b/board/mchpevb1/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -10,8 +10,8 @@
 # external SPI is 512KB
 # external clock is crystal
 CHIP:=mchp
-CHIP_FAMILY:=mec17xx
-CHIP_VARIANT:=mec17xx_2E00
+CHIP_FAMILY:=mec170x
+CHIP_VARIANT:=mec1701
 CHIP_SPI_SIZE_KB:=512
 
 board-y=board.o led.o
diff --git a/board/mchpevb1/ec.tasklist b/board/mchpevb1/ec.tasklist
index cdfdd45163..f187bb914a 100644
--- a/board/mchpevb1/ec.tasklist
+++ b/board/mchpevb1/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,10 +9,10 @@
 #define CONFIG_TASK_LIST \
 	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
 	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-        TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, LARGER_TASK_STACK_SIZE) \
 	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
 	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
 	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
 	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-        TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE)
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE)
 
diff --git a/board/mchpevb1/gpio.inc b/board/mchpevb1/gpio.inc
index f3341b959a..b3aa29941e 100644
--- a/board/mchpevb1/gpio.inc
+++ b/board/mchpevb1/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,10 +22,13 @@
  * GPIO_0150 is JTAG_TMS
  */
 
+/* include common gpio.inc under chip/mchp/lfw/... */
+#include "chip/mchp/lfw/gpio.inc"
+
 #define GPIO_BOTH_EDGES_PU (GPIO_INT_BOTH | GPIO_PULL_UP)
 
-/* Only needed if CONFIG_HOSTCMD_ESPI is not set, using LPC interface to PCH */
-#ifndef CONFIG_HOSTCMD_ESPI
+/* Only needed if CONFIG_HOST_INTERFACE_ESPI is not set, using LPC interface to PCH */
+#ifndef CONFIG_HOST_INTERFACE_ESPI
 GPIO_INT(PCH_PLTRST_L, PIN(064), GPIO_BOTH_EDGES_PU, lpcrst_interrupt)
 #endif
 
@@ -294,23 +297,6 @@ GPIO(BOARD_VERSION1,        PIN(0114),  GPIO_INPUT)
 GPIO(BOARD_VERSION2,        PIN(0207),  GPIO_INPUT)
 GPIO(BOARD_VERSION3,        PIN(0011),  GPIO_INPUT)
 
-
-/* SPI
- * Chip select must be open drain and driven high before SPI controller
- * configuration.
- */
-/*
- * MEC1701H
- * GPIO_0055/PWM2/SHD_CS0#/RSMRST#
- * GPIO_0124/GPTP-OUT6/PVT_CS#/KSO11
- * QMSPI controller drives chip select, must be
- * configured to alternative function. See below.
- * Always use the name QMSPI_CS0 for chip select.
- * Actual GPIO could be GPIO_0055 QMSPI shared chip select or
- * GPIO_0124 private chip select.
- */
-GPIO(QMSPI_CS0,		PIN(055),  GPIO_ODR_HIGH)
-
 /*
  * MEC1701H GP-SPI0 chip select is GPIO_0003
  * It is used as GPIO output. GPSPI chip level
@@ -341,14 +327,6 @@ GPIO(TFDP_DATA,		PIN(0171), GPIO_INPUT)
 #define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
 #define GPIO_KB_OUTPUT (GPIO_ODR_HIGH)
 
-
-/*
- * GPIO_0104(UART0_TX) Func1
- * GPIO_0105(UART0_RX) Func1
- * Bank 2 bits[4:5]
- */
-ALTERNATE(PIN_MASK(2, 0x30), 1, MODULE_UART, 0)
-
 /* KB pins */
 /*
  * MEC1704H (144 pin package)
@@ -413,25 +391,6 @@ ALTERNATE(PIN_MASK(1, 0xf000000), 2, MODULE_LPC, 0)
  * Function 1, Bank 1 bit[20] */
 ALTERNATE(PIN_MASK(1, 0x100000), 1, MODULE_LPC, GPIO_PULL_UP)
 
-/* MECC card SPI flash is connected to QMSPI Shared Port
- * Also, MEC1701H Private SPI Port (Port 1) has pins multiplexed
- * with KSO pins used in key scan!
- * QMSPI Shared SPI Port (Port 0)
- * NOTE: QMSPI Shared SPI Port pins are on VTR2
- */
-/*
- * MEC1701H SHD SPI is connected to QMSPI controller.
- * QMSPI drives chip select. SHD_CS0#(GPIO_0055) must be set
- * to alternate function 2 and GPIO_ODR_HIGH.
- * GPIO_0055 Function 2, Bank 1 bit[13]
- */
-ALTERNATE(PIN_MASK(1, 0x2000), 2, MODULE_SPI_FLASH, GPIO_ODR_HIGH)
-/* SHD_CLK - GPIO_0056 Function 2, Bank 1 bit[14] */
-ALTERNATE(PIN_MASK(1, 0x4000), 2, MODULE_SPI_FLASH, 0)
-/* MOSI(SHD_IO0) - GPIO_0223 Function 2, Bank 4 bit[19] */
-/* MISO(SHD_IO1) - GPIO_0224 Function 2, Bank 4 bit[20] */
-ALTERNATE(PIN_MASK(4, 0x180000), 2, MODULE_SPI_FLASH, 0)
-
 /*
  * MEC1701H GP-SPI0 Master
  * SPI0_CS# = GPIO_0003 Func 0(GPIO) Bank 0, bit 3
@@ -439,8 +398,8 @@ ALTERNATE(PIN_MASK(4, 0x180000), 2, MODULE_SPI_FLASH, 0)
  * SPI0_MISO = GPIO_0036 Func 2	Bank 0, bit 30
  * SPI0_MOSI = GPIO_0004 Func 2	Bank 0, bit 4
  */
-ALTERNATE(PIN_MASK(0,  0x00000008), 0, MODULE_SPI_MASTER, GPIO_ODR_HIGH)
-ALTERNATE(PIN_MASK(0,  0x50000010), 2, MODULE_SPI_MASTER, 0)
+ALTERNATE(PIN_MASK(0,  0x00000008), 0, MODULE_SPI_CONTROLLER, GPIO_ODR_HIGH)
+ALTERNATE(PIN_MASK(0,  0x50000010), 2, MODULE_SPI_CONTROLLER, 0)
 
 /* I2C pins */
 /* Using SMB00 as function 2 GP-SPI0
diff --git a/board/mchpevb1/led.c b/board/mchpevb1/led.c
index 7b9f7646cb..6400b0a466 100644
--- a/board/mchpevb1/led.c
+++ b/board/mchpevb1/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -30,8 +30,7 @@
  * NOTE: GPIO_BAT_LED_xxx defined in board.h
  */
 
-const enum ec_led_id supported_led_ids[] = {
-			EC_LED_ID_BATTERY_LED};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -40,7 +39,7 @@ enum led_color {
 	LED_RED,
 	LED_AMBER,
 	LED_GREEN,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static int bat_led_set_color(enum led_color color)
@@ -68,8 +67,7 @@ static int bat_led_set_color(enum led_color color)
 	return EC_SUCCESS;
 }
 
-void led_get_brightness_range(enum ec_led_id led_id,
-		uint8_t *brightness_range)
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
 {
 	brightness_range[EC_LED_COLOR_RED] = 1;
 	brightness_range[EC_LED_COLOR_GREEN] = 1;
@@ -114,7 +112,6 @@ static void board_led_set_battery(void)
 {
 #ifdef CONFIG_CHARGER
 	static int battery_ticks;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
@@ -122,41 +119,49 @@ static void board_led_set_battery(void)
 	 * Same as the chromeos spec
 	 * Green/Amber for CHARGE_FLAG_FORCE_IDLE
 	 */
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
 		board_led_set_color_battery(LED_AMBER);
 		break;
-	case PWR_STATE_DISCHARGE:
+	case LED_PWRS_DISCHARGE:
 		/* Less than 3%, blink one second every two second */
 		if (!chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
-			charge_get_percent() < CRITICAL_LOW_BATTERY_PERCENTAGE)
+		    charge_get_percent() < CRITICAL_LOW_BATTERY_PERCENTAGE)
 			board_led_set_color_battery(
 				(battery_ticks % LED_TOTAL_2SECS_TICKS <
-				 LED_ON_1SEC_TICKS) ? LED_AMBER : LED_OFF);
+				 LED_ON_1SEC_TICKS) ?
+					LED_AMBER :
+					LED_OFF);
 		/* Less than 10%, blink one second every four seconds */
 		else if (!chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
-			charge_get_percent() < LOW_BATTERY_PERCENTAGE)
+			 charge_get_percent() < LOW_BATTERY_PERCENTAGE)
 			board_led_set_color_battery(
 				(battery_ticks % LED_TOTAL_4SECS_TICKS <
-				 LED_ON_1SEC_TICKS) ? LED_AMBER : LED_OFF);
+				 LED_ON_1SEC_TICKS) ?
+					LED_AMBER :
+					LED_OFF);
 		else
 			board_led_set_color_battery(LED_OFF);
 		break;
-	case PWR_STATE_ERROR:
+	case LED_PWRS_ERROR:
 		board_led_set_color_battery(
 			(battery_ticks % LED_TOTAL_2SECS_TICKS <
-			 LED_ON_1SEC_TICKS) ? LED_RED : LED_OFF);
+			 LED_ON_1SEC_TICKS) ?
+				LED_RED :
+				LED_OFF);
 		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
+	case LED_PWRS_CHARGE_NEAR_FULL:
 		board_led_set_color_battery(LED_GREEN);
 		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			board_led_set_color_battery(
-				(battery_ticks % LED_TOTAL_4SECS_TICKS <
-				 LED_ON_2SECS_TICKS) ? LED_GREEN : LED_AMBER);
-		else
-			board_led_set_color_battery(LED_GREEN);
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		board_led_set_color_battery(LED_GREEN);
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		board_led_set_color_battery(
+			(battery_ticks % LED_TOTAL_4SECS_TICKS <
+			 LED_ON_2SECS_TICKS) ?
+				LED_GREEN :
+				LED_AMBER);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
@@ -165,7 +170,6 @@ static void board_led_set_battery(void)
 #endif
 }
 
-
 static void led_second(void)
 {
 	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
diff --git a/board/mchpevb1/lfw/gpio.inc b/board/mchpevb1/lfw/gpio.inc
deleted file mode 100644
index f4142d3c29..0000000000
--- a/board/mchpevb1/lfw/gpio.inc
+++ /dev/null
@@ -1,43 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Minimal set of GPIOs needed for LFW loader
- */
-
-/*
- * MEC1701H GPIO_0055/PWM2/SHD_CS0#/RSMRST#
- * MEC1701H QMSPI controller drives chip select, must be
- * configured to alternative function. See below.
- * GPIO_SHD_CS0 is used in board level spi_devices[] table
- */
-GPIO(QMSPI_CS0,	PIN(055),  GPIO_ODR_HIGH)
-
-
-/* Alternate functions GPIO definition */
-
-/*
- * UART
- * GPIO_0104(UART0_TX) Func1
- * GPIO_0105(UART0_RX) Func1
- * Bank 2 bits[4:5]
-*/
-ALTERNATE(PIN_MASK(2, 0x30), 1, MODULE_UART, 0)
-
-/* SPI pins */
-/*
- * MEC1701H SHD SPI is connected to QMSPI controller.
- * QMSPI drives chip select. SHD_CS0#(GPIO_0055) must be set
- * to alternate function 2 and GPIO_ODR_HIGH.
- * GPIO_0055 Function 2, Bank 1 bit[13]
- */
-ALTERNATE(PIN_MASK(1, 0x2000), 2, MODULE_SPI_FLASH, GPIO_ODR_HIGH)
-/* SHD_CLK - GPIO_0056 Function 2, Bank 1 bit[14] */
-ALTERNATE(PIN_MASK(1, 0x4000), 2, MODULE_SPI_FLASH, 0)
-/* MOSI(SHD_IO0) - GPIO_0223 Function 2, Bank 4 bit[19] */
-/* MISO(SHD_IO1) - GPIO_0224 Function 2, Bank 4 bit[20] */
-ALTERNATE(PIN_MASK(4, 0x180000), 2, MODULE_SPI_FLASH, 0)
-
-
diff --git a/board/mchpevb1/lfw/vif_override.xml b/board/mchpevb1/lfw/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/mchpevb1/lfw/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/mchpevb1/usb_pd_policy.c b/board/mchpevb1/usb_pd_policy.c
index 690f8b8a3c..107b5029cf 100644
--- a/board/mchpevb1/usb_pd_policy.c
+++ b/board/mchpevb1/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,23 +14,20 @@
 #include "system.h"
 #include "task.h"
 #include "timer.h"
-#include "util.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
+#include "util.h"
 
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_set_power_supply_ready(int port)
 {
 	/* Disable charging */
-	gpio_set_level(port ? GPIO_USB_C1_CHARGE_EN_L :
-			      GPIO_USB_C0_CHARGE_EN_L, 1);
+	gpio_set_level(port ? GPIO_USB_C1_CHARGE_EN_L : GPIO_USB_C0_CHARGE_EN_L,
+		       1);
 	/* Provide VBUS */
-	gpio_set_level(port ? GPIO_USB_C1_5V_EN :
-			      GPIO_USB_C0_5V_EN, 1);
+	gpio_set_level(port ? GPIO_USB_C1_5V_EN : GPIO_USB_C0_5V_EN, 1);
 
 	/* notify host of power info change */
 	pd_send_host_event(PD_EVENT_POWER_CHANGE);
@@ -41,8 +38,7 @@ int pd_set_power_supply_ready(int port)
 void pd_power_supply_reset(int port)
 {
 	/* Disable VBUS */
-	gpio_set_level(port ? GPIO_USB_C1_5V_EN :
-			      GPIO_USB_C0_5V_EN, 0);
+	gpio_set_level(port ? GPIO_USB_C1_5V_EN : GPIO_USB_C0_5V_EN, 0);
 
 	/* notify host of power info change */
 	pd_send_host_event(PD_EVENT_POWER_CHANGE);
diff --git a/board/meep/battery.c b/board/meep/battery.c
index eced940973..56434d98da 100644
--- a/board/meep/battery.c
+++ b/board/meep/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -33,7 +33,7 @@
  */
 const struct board_batt_params board_battery_info[] = {
 	/* DynaPack Coslight Battery Information */
-	[BATTERY_DANAPACK_COS] = {
+	[BATTERY_DYNAPACK_COS] = {
 		.fuel_gauge = {
 			.manuf_name = "333-2C-DA-A",
 			.ship_mode = {
@@ -62,7 +62,7 @@ const struct board_batt_params board_battery_info[] = {
 	},
 
 	/* DynaPack ATL Battery Information */
-	[BATTERY_DANAPACK_ATL] = {
+	[BATTERY_DYNAPACK_ATL] = {
 		.fuel_gauge = {
 			.manuf_name = "333-27-DA-A",
 			.ship_mode = {
@@ -91,7 +91,7 @@ const struct board_batt_params board_battery_info[] = {
 	},
 
 	/* DynaPack SDI Battery Information */
-	[BATTERY_DANAPACK_SDI] = {
+	[BATTERY_DYNAPACK_SDI] = {
 		.fuel_gauge = {
 			.manuf_name = "333-24-DA-A",
 			.ship_mode = {
@@ -234,7 +234,36 @@ const struct board_batt_params board_battery_info[] = {
 			.discharging_max_c = 60,
 		},
 	},
+
+	/* CosMX B00C4473A9D0002 Battery Information */
+	[BATTERY_COS] = {
+		.fuel_gauge = {
+			.manuf_name = "333-AC-DA-A",
+			.ship_mode = {
+				.reg_addr = 0x0,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,		/* mV */
+			.voltage_normal = 7700,		/* mV */
+			.voltage_min = 6000,		/* mV */
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
 };
 BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
 
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_DANAPACK_COS;
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_DYNAPACK_COS;
diff --git a/board/meep/board.c b/board/meep/board.c
index 0577671755..62e4881b1b 100644
--- a/board/meep/board.c
+++ b/board/meep/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,6 @@
 /* Meep/Mimrock board-specific configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "battery.h"
 #include "button.h"
 #include "cbi_ssfc.h"
@@ -36,20 +35,20 @@
 #include "switch.h"
 #include "system.h"
 #include "tablet_mode.h"
-#include "tcpci.h"
+#include "tcpm/tcpci.h"
 #include "temp_sensor.h"
-#include "thermistor.h"
+#include "temp_sensor/thermistor.h"
 #include "usb_mux.h"
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
-#define USB_PD_PORT_ANX7447	0
-#define USB_PD_PORT_PS8751	1
+#define USB_PD_PORT_ANX7447 0
+#define USB_PD_PORT_PS8751 1
 
 #ifdef CONFIG_KEYBOARD_KEYPAD
 #error "KSO_14 was repurposed to PPC_ID pin so CONFIG_KEYBOARD_KEYPAD \
@@ -87,32 +86,32 @@ static void ppc_interrupt(enum gpio_signal signal)
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_AMB] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_AMB] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				  ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_CHARGER] = { "TEMP_CHARGER", NPCX_ADC_CH1,
+				      ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 },
 	/* Vbus C0 sensing (10x voltage divider). PPVAR_USB_C0_VBUS */
-	[ADC_VBUS_C0] = {
-		"VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
+	[ADC_VBUS_C0] = { "VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT * 10,
+			  ADC_READ_MAX + 1, 0 },
 	/* Vbus C1 sensing (10x voltage divider). PPVAR_USB_C1_VBUS */
-	[ADC_VBUS_C1] = {
-		"VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
+	[ADC_VBUS_C1] = { "VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT * 10,
+			  ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp,
-				 .idx = 0},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
+	[TEMP_SENSOR_BATTERY] = { .name = "Battery",
+				  .type = TEMP_SENSOR_TYPE_BATTERY,
+				  .read = charge_get_battery_temp,
+				  .idx = 0 },
+	[TEMP_SENSOR_AMBIENT] = { .name = "Ambient",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_51k1_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_AMB },
+	[TEMP_SENSOR_CHARGER] = { .name = "Charger",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_13k7_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_CHARGER },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -122,17 +121,13 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t lid_standrd_ref = {
-	{ FLOAT_TO_FP(1),  0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t lid_standrd_ref = { { FLOAT_TO_FP(1), 0, 0 },
+				     { 0, FLOAT_TO_FP(-1), 0 },
+				     { 0, 0, FLOAT_TO_FP(-1) } };
 
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1),  0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+				       { 0, FLOAT_TO_FP(-1), 0 },
+				       { 0, 0, FLOAT_TO_FP(-1) } };
 
 /* sensor private data */
 static struct kionix_accel_data kx022_data;
@@ -177,8 +172,6 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_base_mutex,
 		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
 				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
 		.port = I2C_PORT_SENSOR,
 		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
 		.rot_standard_ref = &base_standard_ref,
@@ -209,8 +202,6 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_base_mutex,
 		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
 				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
 		.port = I2C_PORT_SENSOR,
 		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
 		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
@@ -233,9 +224,9 @@ int board_is_convertible(void)
 	 * Vortininja: 49, 50, 51, 52
 	 * Unprovisioned: 255
 	 */
-	return sku_id == 1 || sku_id == 2 || sku_id == 3 ||
-	       sku_id == 4 || sku_id == 49 || sku_id == 50 ||
-	       sku_id == 51 || sku_id == 52 || sku_id == 255;
+	return sku_id == 1 || sku_id == 2 || sku_id == 3 || sku_id == 4 ||
+	       sku_id == 49 || sku_id == 50 || sku_id == 51 || sku_id == 52 ||
+	       sku_id == 255;
 }
 
 static void board_update_sensor_config_from_sku(void)
@@ -311,17 +302,16 @@ void board_hibernate_late(void)
 
 	const uint32_t hibernate_pins[][2] = {
 		/* Turn off LEDs before going to hibernate */
-		{GPIO_BAT_LED_WHITE_L, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_BAT_LED_AMBER_L, GPIO_INPUT | GPIO_PULL_UP},
+		{ GPIO_BAT_LED_WHITE_L, GPIO_INPUT | GPIO_PULL_UP },
+		{ GPIO_BAT_LED_AMBER_L, GPIO_INPUT | GPIO_PULL_UP },
 	};
 
 	for (i = 0; i < ARRAY_SIZE(hibernate_pins); ++i)
 		gpio_set_flags(hibernate_pins[i][0], hibernate_pins[i][1]);
 }
 
-#ifndef TEST_BUILD
 /* This callback disables keyboard when convertibles are fully open */
-void lid_angle_peripheral_enable(int enable)
+__override void lid_angle_peripheral_enable(int enable)
 {
 	/*
 	 * If the lid is in tablet position via other sensors,
@@ -334,7 +324,6 @@ void lid_angle_peripheral_enable(int enable)
 	if (board_is_convertible())
 		keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
 }
-#endif
 
 #ifdef CONFIG_KEYBOARD_FACTORY_TEST
 /*
@@ -343,15 +332,15 @@ void lid_angle_peripheral_enable(int enable)
  * The connector has 24 pins total, and there is no pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-		{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-		{0, 7}, {1, 4}, {1, 3}, {1, 6}, {1, 7},
-		{3, 1}, {2, 0}, {1, 5}, {2, 6}, {2, 7},
-		{2, 1}, {2, 4}, {2, 5}, {1, 2}, {2, 3},
-		{2, 2}, {3, 0}, {-1, -1}, {-1, -1}, {-1, -1},
+	{ -1, -1 }, { 0, 5 }, { 1, 1 },	  { 1, 0 },   { 0, 6 },
+	{ 0, 7 },   { 1, 4 }, { 1, 3 },	  { 1, 6 },   { 1, 7 },
+	{ 3, 1 },   { 2, 0 }, { 1, 5 },	  { 2, 6 },   { 2, 7 },
+	{ 2, 1 },   { 2, 4 }, { 2, 5 },	  { 1, 2 },   { 2, 3 },
+	{ 2, 2 },   { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 },
 };
 
 const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 #endif
 
 void board_overcurrent_event(int port, int is_overcurrented)
@@ -396,31 +385,29 @@ __override uint16_t board_get_ps8xxx_product_id(int port)
 }
 
 static const struct ppc_config_t ppc_syv682x_port0 = {
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
+	.i2c_port = I2C_PORT_TCPC0,
+	.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+	.drv = &syv682x_drv,
 };
 
 static const struct ppc_config_t ppc_syv682x_port1 = {
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
+	.i2c_port = I2C_PORT_TCPC1,
+	.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+	.drv = &syv682x_drv,
 };
 
 static void board_setup_ppc(void)
 {
 	if (c0_port_ppc == PPC_SYV682X) {
-		memcpy(&ppc_chips[USB_PD_PORT_TCPC_0],
-			   &ppc_syv682x_port0,
-			   sizeof(struct ppc_config_t));
+		memcpy(&ppc_chips[USB_PD_PORT_TCPC_0], &ppc_syv682x_port0,
+		       sizeof(struct ppc_config_t));
 
 		gpio_set_flags(GPIO_USB_PD_C0_INT_ODL, GPIO_INT_BOTH);
 	}
 
 	if (c1_port_ppc == PPC_SYV682X) {
-		memcpy(&ppc_chips[USB_PD_PORT_TCPC_1],
-			   &ppc_syv682x_port1,
-			   sizeof(struct ppc_config_t));
+		memcpy(&ppc_chips[USB_PD_PORT_TCPC_1], &ppc_syv682x_port1,
+		       sizeof(struct ppc_config_t));
 
 		gpio_set_flags(GPIO_USB_PD_C1_INT_ODL, GPIO_INT_BOTH);
 	}
diff --git a/board/meep/board.h b/board/meep/board.h
index 570cbd5f7c..6f437fb852 100644
--- a/board/meep/board.h
+++ b/board/meep/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,20 +13,17 @@
 #define VARIANT_OCTOPUS_CHARGER_ISL9238
 #include "baseboard.h"
 
+#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD
+
 #define CONFIG_VOLUME_BUTTONS
 #define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
 #define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
 
-/* EC console commands  */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-
 #define CONFIG_LED_COMMON
-#define CONFIG_LED_POWER_LED
 
 /* Sensors */
-#define CONFIG_ACCEL_KX022		/* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM	/* Base accel */
+#define CONFIG_ACCEL_KX022 /* Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
 
 /* Sensors without hardware FIFO are in forced mode */
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
@@ -56,6 +53,8 @@
 #define CONFIG_USBC_PPC_DEDICATED_INT
 #undef CONFIG_SYV682X_HV_ILIM
 #define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_5_50
+/* SYV682 isn't connected to CC, so TCPC must provide VCONN */
+#define CONFIG_USBC_PPC_SYV682X_NO_CC
 
 /* Additional TCPC second source in Port 1 */
 #define CONFIG_USB_PD_TCPM_MULTI_PS8XXX
@@ -67,10 +66,10 @@
 #include "registers.h"
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_AMB,		/* ADC0 */
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC1 */
-	ADC_VBUS_C0,			/* ADC9 */
-	ADC_VBUS_C1,			/* ADC4 */
+	ADC_TEMP_SENSOR_AMB, /* ADC0 */
+	ADC_TEMP_SENSOR_CHARGER, /* ADC1 */
+	ADC_VBUS_C0, /* ADC9 */
+	ADC_VBUS_C1, /* ADC4 */
 	ADC_CH_COUNT
 };
 
@@ -81,27 +80,20 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_COUNT };
 
 /* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
 enum battery_type {
-	BATTERY_DANAPACK_COS,
-	BATTERY_DANAPACK_ATL,
-	BATTERY_DANAPACK_SDI,
+	BATTERY_DYNAPACK_COS,
+	BATTERY_DYNAPACK_ATL,
+	BATTERY_DYNAPACK_SDI,
 	BATTERY_SAMSUNG_SDI,
 	BATTERY_SIMPLO_COS,
 	BATTERY_SIMPLO_ATL,
 	BATTERY_SIMPLO_HIGHPOWER,
+	BATTERY_COS,
 	BATTERY_TYPE_COUNT,
 };
 
@@ -111,11 +103,6 @@ enum ppc_type {
 	PPC_TYPE_COUNT,
 };
 
-#ifdef CONFIG_KEYBOARD_FACTORY_TEST
-extern const int keyboard_factory_scan_pins[][2];
-extern const int keyboard_factory_scan_pins_used;
-#endif
-
 int board_is_convertible(void);
 
 #endif /* !__ASSEMBLER__ */
diff --git a/board/meep/build.mk b/board/meep/build.mk
index 3d04b75731..998a65a3de 100644
--- a/board/meep/build.mk
+++ b/board/meep/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/meep/ec.tasklist b/board/meep/ec.tasklist
index d98db145e7..977b8b01be 100644
--- a/board/meep/ec.tasklist
+++ b/board/meep/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/meep/gpio.inc b/board/meep/gpio.inc
index ebb69bdf53..aeb659624a 100644
--- a/board/meep/gpio.inc
+++ b/board/meep/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/meep/led.c b/board/meep/led.c
index 7baedca253..dab78ccad4 100644
--- a/board/meep/led.c
+++ b/board/meep/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -7,48 +7,56 @@
 
 #include "ec_commands.h"
 #include "gpio.h"
+#include "hooks.h"
 #include "led_common.h"
 #include "led_onoff_states.h"
-#include "hooks.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
-const int led_charge_lvl_1;
+__override const int led_charge_lvl_1;
 
-const int led_charge_lvl_2 = 100;
+__override const int led_charge_lvl_2 = 100;
 
 /* Meep: Note there is only LED for charge / power */
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF, 1 * LED_ONE_SEC} },
-	/* STATE_DISCHARGE_S3 will changed if sku is clamshells */
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_WHITE, 0.5 * LED_ONE_SEC},
-					{LED_OFF, 0.5 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF, 1 * LED_ONE_SEC} },
-};
-
-const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   1 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   1 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_WHITE,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 1 * LED_ONE_SEC } },
+		/* STATE_DISCHARGE_S3 will changed if sku is clamshells */
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_WHITE,
+					    0.5 * LED_ONE_SEC },
+					  { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 1 * LED_ONE_SEC } },
+	};
+
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 1 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    1 * LED_ONE_SEC },
+						  { LED_OFF,
+						    1 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 
 static void s3_led_init(void)
 {
@@ -68,7 +76,7 @@ DECLARE_HOOK(HOOK_INIT, s3_led_init, HOOK_PRIO_DEFAULT);
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-void led_set_color_power(enum ec_led_colors color)
+__override void led_set_color_power(enum ec_led_colors color)
 {
 	if (color == EC_LED_COLOR_WHITE)
 		gpio_set_level(GPIO_PWR_LED_WHITE_L, LED_ON_LVL);
@@ -77,7 +85,7 @@ void led_set_color_power(enum ec_led_colors color)
 		gpio_set_level(GPIO_PWR_LED_WHITE_L, LED_OFF_LVL);
 }
 
-void led_set_color_battery(enum ec_led_colors color)
+__override void led_set_color_battery(enum ec_led_colors color)
 {
 	switch (color) {
 	case EC_LED_COLOR_WHITE:
@@ -123,4 +131,3 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 
 	return EC_SUCCESS;
 }
-
diff --git a/board/meep/vif_override.xml b/board/meep/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/meep/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/metaknight/battery.c b/board/metaknight/battery.c
new file mode 100644
index 0000000000..cff274ae4f
--- /dev/null
+++ b/board/metaknight/battery.c
@@ -0,0 +1,68 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "charge_state.h"
+#include "common.h"
+
+/*
+ * Battery info for all metaknight battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	/* Simplo PC-VP-BP44 Battery Information */
+	[BATTERY_SMP_PCVPBP144] = {
+		.fuel_gauge = {
+			.manuf_name  = "SIMPLO",
+			.device_name = "PC-VP-BP144",
+			.ship_mode = {
+				.reg_addr = 0x34,
+				.reg_data = { 0x0000, 0x1000 },
+			},
+			.fet = {
+				.reg_addr       = 0x00,
+				.reg_mask       = 0x10,
+				.disconnect_val = 0x00,
+				.cfet_mask      = 0x08,
+				.cfet_off_val   = 0x00,
+			}
+		},
+		.batt_info = {
+			.voltage_max            = 13050,  /* mV */
+			.voltage_normal         = 11250,
+			.voltage_min            = 9000,
+			.precharge_current      = 128,    /* mA */
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 45,
+			.charging_min_c         = 0,
+			.charging_max_c         = 60,
+			.discharging_min_c      = -20,
+			.discharging_max_c      = 60,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SMP_PCVPBP144;
diff --git a/board/metaknight/board.c b/board/metaknight/board.c
new file mode 100644
index 0000000000..7675c7c8f5
--- /dev/null
+++ b/board/metaknight/board.c
@@ -0,0 +1,880 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* metaknight board-specific configuration */
+
+#include "adc.h"
+#include "button.h"
+#include "cbi_fw_config.h"
+#include "cbi_ssfc.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "chipset.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "driver/accel_bma2x2.h"
+#include "driver/accel_kionix.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "driver/accelgyro_icm426xx.h"
+#include "driver/accelgyro_icm_common.h"
+#include "driver/accelgyro_lsm6dsm.h"
+#include "driver/bc12/pi3usb9201.h"
+#include "driver/charger/isl923x.h"
+#include "driver/retimer/nb7v904m.h"
+#include "driver/tcpm/raa489000.h"
+#include "driver/tcpm/tcpci.h"
+#include "driver/temp_sensor/thermistor.h"
+#include "driver/usb_mux/pi3usb3x532.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "motion_sense.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "stdbool.h"
+#include "switch.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "temp_sensor.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+#define INT_RECHECK_US 5000
+
+#define ADC_VOL_UP_MASK BIT(0)
+#define ADC_VOL_DOWN_MASK BIT(1)
+
+static uint8_t new_adc_key_state;
+
+/* USB-A Configuration */
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_USB_A0_VBUS,
+	GPIO_EN_USB_A1_VBUS,
+};
+
+/* C0 interrupt line shared by BC 1.2 and charger */
+static void check_c0_line(void);
+DECLARE_DEFERRED(check_c0_line);
+
+static void notify_c0_chips(void)
+{
+	/*
+	 * The interrupt line is shared between the TCPC and BC 1.2 detection
+	 * chip.  Therefore we'll need to check both ICs.
+	 */
+	schedule_deferred_pd_interrupt(0);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+
+static void check_c0_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		notify_c0_chips();
+		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+	}
+}
+
+static void usb_c0_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c0_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c0_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+}
+
+static void sub_hdmi_hpd_interrupt(enum gpio_signal s)
+{
+	int hdmi_hpd_odl = gpio_get_level(GPIO_HDMI_HPD_SUB_ODL);
+
+	gpio_set_level(GPIO_EC_AP_USB_C1_HDMI_HPD, !hdmi_hpd_odl);
+
+	cprints(CC_SYSTEM, "HDMI plug-%s", !hdmi_hpd_odl ? "in" : "out");
+}
+
+/**
+ * Handle debounced pen input changing state.
+ */
+static void pen_input_deferred(void)
+{
+	int pen_charge_enable = !gpio_get_level(GPIO_PEN_DET_ODL) &&
+				!chipset_in_state(CHIPSET_STATE_ANY_OFF);
+
+	if (pen_charge_enable)
+		gpio_set_level(GPIO_EN_PP3300_PEN, 1);
+	else
+		gpio_set_level(GPIO_EN_PP3300_PEN, 0);
+
+	CPRINTS("Pen charge %sable", pen_charge_enable ? "en" : "dis");
+}
+DECLARE_DEFERRED(pen_input_deferred);
+
+void pen_input_interrupt(enum gpio_signal signal)
+{
+	/* pen input debounce time */
+	hook_call_deferred(&pen_input_deferred_data, (100 * MSEC));
+}
+
+static void pen_charge_check(void)
+{
+	hook_call_deferred(&pen_input_deferred_data, (100 * MSEC));
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, pen_charge_check, HOOK_PRIO_LAST);
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, pen_charge_check, HOOK_PRIO_LAST);
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_1] = {
+		.name = "TEMP_SENSOR1",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_2] = {
+		.name = "TEMP_SENSOR2",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_SUB_ANALOG] = {
+		.name = "SUB_ANALOG",
+		.input_ch = NPCX_ADC_CH2,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_VSNS_PP3300_A] = {
+		.name = "PP3300_A_PGOOD",
+		.input_ch = NPCX_ADC_CH9,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* Thermistors */
+const struct temp_sensor_t temp_sensors[] = {
+
+	[TEMP_SENSOR_MEMORY] = { .name = "Memory",
+				 .type = TEMP_SENSOR_TYPE_BOARD,
+				 .read = get_temp_3v3_51k1_47k_4050b,
+				 .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_CPU] = { .name = "CPU",
+			      .type = TEMP_SENSOR_TYPE_BOARD,
+			      .read = get_temp_3v3_51k1_47k_4050b,
+			      .idx = ADC_TEMP_SENSOR_2 },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_MEMORY           \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(85), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_memory =
+	THERMAL_MEMORY;
+
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
+
+struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
+
+static void setup_thermal(void)
+{
+	thermal_params[TEMP_SENSOR_MEMORY] = thermal_memory;
+	thermal_params[TEMP_SENSOR_CPU] = thermal_cpu;
+}
+
+void board_hibernate(void)
+{
+	/*
+	 * Both charger ICs need to be put into their "low power mode" before
+	 * entering the Z-state.
+	 */
+	if (board_get_charger_chip_count() > 1)
+		raa489000_hibernate(1, true);
+	raa489000_hibernate(0, true);
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * TODO(b:147316511): Here we could issue a digital reset to the IC,
+	 * unsure if we actually want to do that or not yet.
+	 */
+}
+
+#ifdef BOARD_WADDLEDOO
+static void reconfigure_5v_gpio(void)
+{
+	/*
+	 * b/147257497: On early waddledoo boards, GPIO_EN_PP5000 was swapped
+	 * with GPIO_VOLUP_BTN_ODL. Therefore, we'll actually need to set that
+	 * GPIO instead for those boards.  Note that this breaks the volume up
+	 * button functionality.
+	 */
+	if (system_get_board_version() < 0) {
+		CPRINTS("old board - remapping 5V en");
+		gpio_set_flags(GPIO_VOLUP_BTN_ODL, GPIO_OUT_LOW);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, reconfigure_5v_gpio, HOOK_PRIO_INIT_I2C + 1);
+#endif /* BOARD_WADDLEDOO */
+
+static void set_5v_gpio(int level)
+{
+	int version;
+	enum gpio_signal gpio = GPIO_EN_PP5000;
+
+	/*
+	 * b/147257497: On early waddledoo boards, GPIO_EN_PP5000 was swapped
+	 * with GPIO_VOLUP_BTN_ODL. Therefore, we'll actually need to set that
+	 * GPIO instead for those boards.  Note that this breaks the volume up
+	 * button functionality.
+	 */
+	if (IS_ENABLED(BOARD_WADDLEDOO)) {
+		version = system_get_board_version();
+
+		/*
+		 * If the CBI EEPROM wasn't formatted, assume it's a very early
+		 * board.
+		 */
+		gpio = version < 0 ? GPIO_VOLUP_BTN_ODL : GPIO_EN_PP5000;
+	}
+
+	gpio_set_level(gpio, level);
+}
+
+__override void board_power_5v_enable(int enable)
+{
+	/*
+	 * Port 0 simply has a GPIO to turn on the 5V regulator, however, 5V is
+	 * generated locally on the sub board and we need to set the comparator
+	 * polarity on the sub board charger IC, or send enable signal to HDMI
+	 * DB.
+	 */
+	set_5v_gpio(!!enable);
+
+	if (get_cbi_fw_config_db() == DB_1A_HDMI ||
+	    get_cbi_fw_config_db() == DB_LTE_HDMI) {
+		gpio_set_level(GPIO_SUB_C1_INT_EN_RAILS_ODL, !enable);
+	}
+}
+
+__override uint8_t board_get_usb_pd_port_count(void)
+{
+	return CONFIG_USB_PD_PORT_MAX_COUNT;
+}
+
+__override uint8_t board_get_charger_chip_count(void)
+{
+	return CHARGER_NUM;
+}
+
+int board_is_sourcing_vbus(int port)
+{
+	int regval;
+
+	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
+	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count());
+	int i;
+	int old_port;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	old_port = charge_manager_get_active_charge_port();
+
+	CPRINTS("New chg p%d", port);
+
+	/* Disable all ports. */
+	if (port == CHARGE_PORT_NONE) {
+		for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+			tcpc_write(i, TCPC_REG_COMMAND,
+				   TCPC_REG_COMMAND_SNK_CTRL_LOW);
+			raa489000_enable_asgate(i, false);
+		}
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if port is sourcing VBUS. */
+	if (board_is_sourcing_vbus(port)) {
+		CPRINTS("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+		if (i == port)
+			continue;
+
+		if (tcpc_write(i, TCPC_REG_COMMAND,
+			       TCPC_REG_COMMAND_SNK_CTRL_LOW))
+			CPRINTS("p%d: sink path disable failed.", i);
+		raa489000_enable_asgate(i, false);
+	}
+
+	/*
+	 * Stop the charger IC from switching while changing ports.  Otherwise,
+	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
+	 */
+	if (old_port != CHARGE_PORT_NONE)
+		charger_discharge_on_ac(1);
+
+	/* Enable requested charge port. */
+	if (raa489000_enable_asgate(port, true) ||
+	    tcpc_write(port, TCPC_REG_COMMAND,
+		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
+		CPRINTS("p%d: sink path enable failed.", port);
+		charger_discharge_on_ac(0);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	/* Allow the charger IC to begin/continue switching. */
+	charger_discharge_on_ac(0);
+
+	return EC_SUCCESS;
+}
+
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	if (port < 0 || port > board_get_usb_pd_port_count())
+		return;
+
+	raa489000_set_output_current(port, rp);
+}
+
+/* Sensors */
+static struct mutex g_lid_mutex;
+static struct mutex g_base_mutex;
+
+/* Matrices to rotate accelerometers into the standard reference. */
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
+
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					      { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
+
+static const mat33_fp_t base_lsm6dsm_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, FLOAT_TO_FP(1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
+
+static const mat33_fp_t base_icm_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					 { 0, FLOAT_TO_FP(1), 0 },
+					 { 0, 0, FLOAT_TO_FP(-1) } };
+
+static struct accelgyro_saved_data_t g_bma253_data;
+static struct bmi_drv_data_t g_bmi160_data;
+static struct kionix_accel_data g_kx022_data;
+static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
+static struct icm_drv_data_t g_icm426xx_data;
+
+struct motion_sensor_t motion_sensors[] = {
+	[LID_ACCEL] = {
+		.name = "Lid Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMA255,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &bma2x2_accel_drv,
+		.mutex = &g_lid_mutex,
+		.drv_data = &g_bma253_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
+		.rot_standard_ref = &lid_standard_ref,
+		.default_range = 2,
+		.min_frequency = BMA255_ACCEL_MIN_FREQ,
+		.max_frequency = BMA255_ACCEL_MAX_FREQ,
+		.config = {
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+		},
+	},
+	[BASE_ACCEL] = {
+		.name = "Base Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMI160,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &bmi160_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = &g_bmi160_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+		.rot_standard_ref = &base_standard_ref,
+		.default_range = 4,
+		.min_frequency = BMI_ACCEL_MIN_FREQ,
+		.max_frequency = BMI_ACCEL_MAX_FREQ,
+		.config = {
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 13000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+		},
+	},
+	[BASE_GYRO] = {
+		.name = "Base Gyro",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMI160,
+		.type = MOTIONSENSE_TYPE_GYRO,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &bmi160_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = &g_bmi160_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+		.default_range = 1000, /* dps */
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = BMI_GYRO_MIN_FREQ,
+		.max_frequency = BMI_GYRO_MAX_FREQ,
+	},
+};
+
+const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+struct motion_sensor_t kx022_lid_accel = {
+	.name = "Lid Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_KX022,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_LID,
+	.drv = &kionix_accel_drv,
+	.mutex = &g_lid_mutex,
+	.drv_data = &g_kx022_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = KX022_ADDR0_FLAGS,
+	.rot_standard_ref = &lid_standard_ref,
+	.min_frequency = KX022_ACCEL_MIN_FREQ,
+	.max_frequency = KX022_ACCEL_MAX_FREQ,
+	.default_range = 2, /* g, to support tablet mode */
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	},
+};
+
+struct motion_sensor_t lsm6dsm_base_accel = {
+	.name = "Base Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_LSM6DS3,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &lsm6dsm_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
+			MOTIONSENSE_TYPE_ACCEL),
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
+	.rot_standard_ref = &base_lsm6dsm_ref,
+	.default_range = 4,  /* g */
+	.min_frequency = LSM6DSM_ODR_MIN_VAL,
+	.max_frequency = LSM6DSM_ODR_MAX_VAL,
+	.config = {
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 13000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+	},
+};
+
+struct motion_sensor_t lsm6dsm_base_gyro = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_LSM6DS3,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &lsm6dsm_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data, MOTIONSENSE_TYPE_GYRO),
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
+	.default_range = 1000 | ROUND_UP_FLAG, /* dps */
+	.rot_standard_ref = &base_lsm6dsm_ref,
+	.min_frequency = LSM6DSM_ODR_MIN_VAL,
+	.max_frequency = LSM6DSM_ODR_MAX_VAL,
+};
+
+struct motion_sensor_t icm426xx_base_accel = {
+	.name = "Base Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 4, /* g, enough for laptop */
+	.rot_standard_ref = &base_icm_ref,
+	.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
+	.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 13000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+	},
+};
+
+struct motion_sensor_t icm426xx_base_gyro = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &base_icm_ref,
+	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
+	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
+};
+
+static int base_gyro_config;
+
+void board_init(void)
+{
+	int on;
+
+	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
+	check_c0_line();
+
+	if (get_cbi_fw_config_db() == DB_1A_HDMI ||
+	    get_cbi_fw_config_db() == DB_LTE_HDMI) {
+		/* Disable i2c on HDMI pins */
+		gpio_config_pin(MODULE_I2C, GPIO_HDMI_HPD_SUB_ODL, 0);
+		gpio_config_pin(MODULE_I2C, GPIO_GPIO92_NC, 0);
+
+		gpio_set_flags(GPIO_SUB_C1_INT_EN_RAILS_ODL, GPIO_ODR_HIGH);
+
+		/* Select HDMI option */
+		gpio_set_level(GPIO_HDMI_SEL_L, 0);
+
+		/* Enable interrupt for passing through HPD */
+		gpio_enable_interrupt(GPIO_HDMI_HPD_SUB_ODL);
+	} else {
+		/* Set SDA as an input */
+		gpio_set_flags(GPIO_HDMI_HPD_SUB_ODL, GPIO_INPUT);
+	}
+	/* Enable gpio interrupt for base accelgyro sensor */
+	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
+
+	/* Enable gpio interrupt for pen detect */
+	gpio_enable_interrupt(GPIO_PEN_DET_ODL);
+
+	/* Turn on 5V if the system is on, otherwise turn it off. */
+	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
+			      CHIPSET_STATE_SOFT_OFF);
+	board_power_5v_enable(on);
+
+	/* Initialize g-sensor */
+	base_gyro_config = get_cbi_ssfc_base_sensor();
+
+	if (base_gyro_config == SSFC_SENSOR_LSM6DSM) {
+		motion_sensors[BASE_ACCEL] = lsm6dsm_base_accel;
+		motion_sensors[BASE_GYRO] = lsm6dsm_base_gyro;
+		cprints(CC_SYSTEM, "SSFC: BASE GYRO is LSM6DSM");
+	} else if (get_cbi_ssfc_base_sensor() == SSFC_SENSOR_ICM426XX) {
+		motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
+		motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
+		cprints(CC_SYSTEM, "SSFC: BASE GYRO is ICM426XX");
+	} else
+		cprints(CC_SYSTEM, "SSFC: BASE GYRO is BMI160");
+
+	if (get_cbi_ssfc_lid_sensor() == SSFC_SENSOR_KX022) {
+		motion_sensors[LID_ACCEL] = kx022_lid_accel;
+		cprints(CC_SYSTEM, "SSFC: LID ACCEL is KX022");
+	} else
+		cprints(CC_SYSTEM, "SSFC: LID ACCEL is BMA253");
+
+	/* Initial thermal */
+	setup_thermal();
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+int pd_snk_is_vbus_provided(int port)
+{
+	return pd_check_vbus_level(port, VBUS_PRESENT);
+}
+
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+};
+
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	{
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+		.flags = PI3USB9201_ALWAYS_POWERED,
+	},
+};
+
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0,
+			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
+		},
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+		.drv = &raa489000_tcpm_drv,
+		.alert_signal = GPIO_USB_C0_INT_ODL,
+	},
+};
+
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
+				.driver = &pi3usb3x532_usb_mux_driver,
+			},
+	},
+};
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+	int regval;
+	int p;
+
+	/*
+	 * The interrupt line is shared between the TCPC and BC1.2
+	 * detector IC. Therefore, go out and actually read the alert
+	 * registers to report the alert status.
+	 */
+	for (p = 0; p < board_get_usb_pd_port_count(); p++) {
+		if (gpio_get_level(tcpc_config[p].alert_signal) ||
+		    tcpc_read16(p, TCPC_REG_ALERT, &regval))
+			continue;
+		/* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */
+		if (!(tcpc_config[p].flags & TCPC_FLAGS_TCPCI_REV2_0))
+			regval &= ~(BIT(14) | BIT(13) | BIT(12));
+		if (regval)
+			status |= (PD_STATUS_TCPC_ALERT_0 << p);
+	}
+
+	return status;
+}
+
+int adc_to_physical_value(enum gpio_signal gpio)
+{
+	if (gpio == GPIO_VOLUME_UP_L)
+		return !!(new_adc_key_state & ADC_VOL_UP_MASK);
+	else if (gpio == GPIO_VOLUME_DOWN_L)
+		return !!(new_adc_key_state & ADC_VOL_DOWN_MASK);
+
+	CPRINTS("Not a volume up or down key");
+	return 0;
+}
+
+int button_is_adc_detected(enum gpio_signal gpio)
+{
+	return (gpio == GPIO_VOLUME_DOWN_L) || (gpio == GPIO_VOLUME_UP_L);
+}
+
+static void adc_vol_key_press_check(void)
+{
+	int volt = adc_read_channel(ADC_SUB_ANALOG);
+	static uint8_t old_adc_key_state;
+	uint8_t adc_key_state_change;
+
+	if (volt > 2400 && volt < 2540) {
+		/* volume-up is pressed */
+		new_adc_key_state = ADC_VOL_UP_MASK;
+	} else if (volt > 2600 && volt < 2740) {
+		/* volume-down is pressed */
+		new_adc_key_state = ADC_VOL_DOWN_MASK;
+	} else if (volt < 2300) {
+		/* both volumn-up and volume-down are pressed */
+		new_adc_key_state = ADC_VOL_UP_MASK | ADC_VOL_DOWN_MASK;
+	} else if (volt > 2780) {
+		/* both volumn-up and volume-down are released */
+		new_adc_key_state = 0;
+	}
+	if (new_adc_key_state != old_adc_key_state) {
+		adc_key_state_change = old_adc_key_state ^ new_adc_key_state;
+		if (adc_key_state_change & ADC_VOL_UP_MASK)
+			button_interrupt(GPIO_VOLUME_UP_L);
+		if (adc_key_state_change & ADC_VOL_DOWN_MASK)
+			button_interrupt(GPIO_VOLUME_DOWN_L);
+
+		old_adc_key_state = new_adc_key_state;
+	}
+}
+DECLARE_HOOK(HOOK_TICK, adc_vol_key_press_check, HOOK_PRIO_DEFAULT);
+
+/* This callback disables keyboard when convertibles are fully open */
+__override void lid_angle_peripheral_enable(int enable)
+{
+	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
+
+	/*
+	 * If the lid is in tablet position via other sensors,
+	 * ignore the lid angle, which might be faulty then
+	 * disable keyboard.
+	 */
+	if (tablet_get_mode())
+		enable = 0;
+
+	if (enable) {
+		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
+	} else {
+		/*
+		 * Ensure that the chipset is off before disabling the keyboard.
+		 * When the chipset is on, the EC keeps the keyboard enabled and
+		 * the AP decides whether to ignore input devices or not.
+		 */
+		if (!chipset_in_s0)
+			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
+	}
+}
+
+#ifndef TEST_BUILD
+void motion_interrupt(enum gpio_signal signal)
+{
+	switch (base_gyro_config) {
+	case SSFC_SENSOR_LSM6DSM:
+		lsm6dsm_interrupt(signal);
+		break;
+	case SSFC_SENSOR_ICM426XX:
+		icm426xx_interrupt(signal);
+		break;
+	case SSFC_SENSOR_BMI160:
+	default:
+		bmi160_interrupt(signal);
+		break;
+	}
+}
+
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_EEPROM_SCL,
+	  .sda = GPIO_EC_I2C_EEPROM_SDA },
+
+	{ .name = "battery",
+	  .port = I2C_PORT_BATTERY,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_BATTERY_SCL,
+	  .sda = GPIO_EC_I2C_BATTERY_SDA },
+
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_SENSOR_SCL,
+	  .sda = GPIO_EC_I2C_SENSOR_SDA },
+
+	{ .name = "usbc0",
+	  .port = I2C_PORT_USB_C0,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C0_SCL,
+	  .sda = GPIO_EC_I2C_USB_C0_SDA },
+#if CONFIG_USB_PD_PORT_MAX_COUNT > 1
+	{ .name = "sub_usbc1",
+	  .port = I2C_PORT_SUB_USB_C1,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_SUB_USB_C1_SCL,
+	  .sda = GPIO_EC_I2C_SUB_USB_C1_SDA },
+#endif
+};
+
+#endif
diff --git a/board/metaknight/board.h b/board/metaknight/board.h
new file mode 100644
index 0000000000..cab1501256
--- /dev/null
+++ b/board/metaknight/board.h
@@ -0,0 +1,186 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* metaknight board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#define VARIANT_DEDEDE_EC_NPCX796FC
+#include "baseboard.h"
+
+/* Battery */
+#define CONFIG_BATTERY_FUEL_GAUGE
+
+/* Charger */
+#define CONFIG_CHARGER_RAA489000
+#define PD_MAX_VOLTAGE_MV 20000
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#undef CONFIG_CHARGER_SINGLE_CHIP
+#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
+#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
+/*
+ * b/147463641: The charger IC seems to overdraw ~4%, therefore we
+ * reduce our target accordingly.
+ */
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 4
+
+/*
+ * GPIO for C1 interrupts, for baseboard use
+ *
+ * Note this line might already have its pull up disabled for HDMI DBs, but
+ * it should be fine to set again before z-state.
+ */
+#define GPIO_USB_C1_INT_ODL GPIO_SUB_C1_INT_EN_RAILS_ODL
+
+/* LED defines */
+#define CONFIG_LED_ONOFF_STATES
+
+/* PWM */
+#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */
+
+/* Temp sensor */
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_THROTTLE_AP
+#define CONFIG_THERMISTOR_NCP15WB
+#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
+
+/* USB */
+#define CONFIG_BC12_DETECT_PI3USB9201
+#define CONFIG_USBC_RETIMER_NB7V904M
+
+/* Common USB-A defines */
+#define USB_PORT_COUNT 2
+#define CONFIG_USB_PORT_POWER_SMART
+#define CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY
+#define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_CDP
+#define CONFIG_USB_PORT_POWER_SMART_INVERTED
+#define GPIO_USB1_ILIM_SEL GPIO_USB_A0_CHARGE_EN_L
+#define GPIO_USB2_ILIM_SEL GPIO_USB_A1_CHARGE_EN_L
+
+/* USB PD */
+#define CONFIG_USB_PD_PORT_MAX_COUNT 1
+#define CONFIG_USB_PD_TCPM_RAA489000
+
+/* USB defines specific to external TCPCs */
+#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+#define CONFIG_USB_PD_VBUS_DETECT_TCPC
+#define CONFIG_USB_PD_DISCHARGE_TCPC
+#define CONFIG_USB_PD_TCPC_LOW_POWER
+
+/* Variant references the TCPCs to determine Vbus sourcing */
+#define CONFIG_USB_PD_5V_EN_CUSTOM
+
+/* I2C configuration */
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
+#define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0
+/* TODO(b:147440290): Need to handle multiple charger ICs */
+#define I2C_PORT_CHARGER I2C_PORT_USB_C0
+
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */
+
+/*
+ * I2C pin names for baseboard
+ *
+ * Note: these lines will be set as i2c on start-up, but this should be
+ * okay since they're ODL.
+ */
+#define GPIO_EC_I2C_SUB_USB_C1_SCL GPIO_GPIO92_NC
+#define GPIO_EC_I2C_SUB_USB_C1_SDA GPIO_HDMI_HPD_SUB_ODL
+
+/* Sensors */
+#define CONFIG_CMD_ACCELS
+#define CONFIG_CMD_ACCEL_INFO
+
+#define CONFIG_ACCEL_BMA255 /* Lid accel */
+#define CONFIG_ACCEL_KX022 /* Lid accel second source */
+#define CONFIG_ACCELGYRO_BMI160 /* Base accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel second source */
+#define CONFIG_ACCELGYRO_ICM426XX /* Base accel second source */
+
+/* Lid operates in forced mode, base in FIFO */
+#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
+#define CONFIG_ACCEL_FIFO
+#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */
+#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
+
+#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_UPDATE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+
+#define CONFIG_TABLET_MODE
+#define CONFIG_TABLET_MODE_SWITCH
+#define CONFIG_GMR_TABLET_MODE
+
+/* Volume Button feature */
+#define CONFIG_ADC_BUTTONS
+#define CONFIG_VOLUME_BUTTONS
+#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL
+
+#ifdef BOARD_METAKNIGHT_LEGACY
+/* this change saves 1656 bytes of RW flash space */
+#define CONFIG_CHIP_INIT_ROM_REGION
+#define CONFIG_DEBUG_ASSERT_BRIEF
+#else
+/*
+ * The RAM and flash size combination on the the NPCX797FC does not leave
+ * any unused flash space that can be used to store the .init_rom section.
+ */
+#undef CONFIG_CHIP_INIT_ROM_REGION
+#endif
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum chg_id {
+	CHARGER_PRIMARY,
+	CHARGER_NUM,
+};
+
+enum adc_channel {
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
+	ADC_SUB_ANALOG, /* ADC2 */
+	ADC_VSNS_PP3300_A, /* ADC9 */
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id { TEMP_SENSOR_MEMORY, TEMP_SENSOR_CPU, TEMP_SENSOR_COUNT };
+
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
+
+enum pwm_channel {
+	PWM_CH_COUNT,
+};
+
+/* List of possible batteries */
+enum battery_type {
+	BATTERY_SMP_PCVPBP144,
+	BATTERY_TYPE_COUNT,
+};
+
+void motion_interrupt(enum gpio_signal signal);
+
+#endif /* !__ASSEMBLER__ */
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/metaknight/build.mk b/board/metaknight/build.mk
new file mode 100644
index 0000000000..1531d1f3ae
--- /dev/null
+++ b/board/metaknight/build.mk
@@ -0,0 +1,14 @@
+# -*- makefile -*-
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx7
+CHIP_VARIANT:=npcx7m7fc
+BASEBOARD:=dedede
+
+board-y=board.o battery.o cbi_ssfc.o led.o usb_pd_policy.o
diff --git a/board/metaknight/cbi_ssfc.c b/board/metaknight/cbi_ssfc.c
new file mode 100644
index 0000000000..81f3ee0dad
--- /dev/null
+++ b/board/metaknight/cbi_ssfc.c
@@ -0,0 +1,36 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi_ssfc.h"
+#include "common.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "hooks.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+/* Cache SSFC on init since we don't expect it to change in runtime */
+static union dedede_cbi_ssfc cached_ssfc;
+BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
+
+static void cbi_ssfc_init(void)
+{
+	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
+		/* Default to 0 when CBI isn't populated */
+		cached_ssfc.raw_value = 0;
+
+	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
+}
+DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
+
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
+{
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
+}
+
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
+{
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
+}
diff --git a/board/metaknight/cbi_ssfc.h b/board/metaknight/cbi_ssfc.h
new file mode 100644
index 0000000000..bf8853a43a
--- /dev/null
+++ b/board/metaknight/cbi_ssfc.h
@@ -0,0 +1,59 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _DEDEDE_CBI_SSFC__H_
+#define _DEDEDE_CBI_SSFC__H_
+
+#include "stdint.h"
+
+/****************************************************************************
+ * Dedede CBI Second Source Factory Cache
+ */
+
+/*
+ * Base Sensor (Bits 0-2)
+ */
+enum ec_ssfc_base_sensor {
+	SSFC_SENSOR_BASE_DEFAULT = 0,
+	SSFC_SENSOR_BMI160 = 1,
+	SSFC_SENSOR_ICM426XX = 2,
+	SSFC_SENSOR_LSM6DSM = 3,
+	SSFC_SENSOR_ICM42607 = 4
+};
+
+/*
+ * Lid Sensor (Bits 3-5)
+ */
+enum ec_ssfc_lid_sensor {
+	SSFC_SENSOR_LID_DEFAULT = 0,
+	SSFC_SENSOR_BMA255 = 1,
+	SSFC_SENSOR_KX022 = 2,
+	SSFC_SENSOR_LIS2DWL = 3
+};
+
+union dedede_cbi_ssfc {
+	struct {
+		uint32_t base_sensor : 3;
+		uint32_t lid_sensor : 3;
+		uint32_t reserved_2 : 26;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Get the Base sensor type from SSFC_CONFIG.
+ *
+ * @return the Base sensor board type.
+ */
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
+
+/**
+ * Get the Lid sensor type from SSFC_CONFIG.
+ *
+ * @return the Lid sensor board type.
+ */
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
+
+#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/metaknight/ec.tasklist b/board/metaknight/ec.tasklist
new file mode 100644
index 0000000000..6316569c9a
--- /dev/null
+++ b/board/metaknight/ec.tasklist
@@ -0,0 +1,22 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE)
diff --git a/board/metaknight/gpio.inc b/board/metaknight/gpio.inc
new file mode 100644
index 0000000000..4d68595d65
--- /dev/null
+++ b/board/metaknight/gpio.inc
@@ -0,0 +1,152 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first.
+ */
+
+/* Power Interrupts */
+GPIO_INT(SLP_S0_L,		 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,		 PIN(A, 5), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(SLP_S4_L,		 PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,		 PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(RSMRST_PWRGD_L,	 PIN(C, 6), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID1,	 PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(CPU_C10_GATE_L,	 PIN(6, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID0,	 PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, power_signal_interrupt)
+GPIO_INT(PG_VCCIO_EXT_OD,	 PIN(B, 0), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(PG_PP5000_U_OD,	 PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_DRAM_OD,		 PIN(E, 4), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(PG_PP1050_ST_OD,	 PIN(4, 2), GPIO_INT_BOTH, power_signal_interrupt)
+
+/* USB-C interrupts */
+GPIO_INT(USB_C0_INT_ODL,	 		PIN(6, 2), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt)
+
+
+/* Button interrupts */
+GPIO_INT(H1_EC_PWR_BTN_ODL,	 PIN(0, 1), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
+
+/* Other interrupts */
+GPIO_INT(LID_OPEN,		 PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)
+GPIO_INT(EC_WP_OD,		 PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(BASE_SIXAXIS_INT_L,	 PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, motion_interrupt)
+GPIO_INT(LID_360_L,		 PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
+GPIO_INT(PEN_DET_ODL,    PIN(5, 0), GPIO_INT_BOTH, pen_input_interrupt)
+GPIO_INT(HDMI_HPD_SUB_ODL,	PIN(9, 1), GPIO_INT_BOTH, sub_hdmi_hpd_interrupt) /* HDMI_HPD */
+
+/* I2C Ports */
+GPIO(EC_I2C_EEPROM_SCL,			PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SDA,			PIN(B, 2), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SCL,		PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SDA,		PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,			PIN(B, 5), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SDA,			PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SCL,			PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SDA,			PIN(8, 7), GPIO_INPUT)
+
+/* Extra Sub-board I/O pins */
+GPIO(EC_SUB_IO_2,  PIN(3, 4), GPIO_OUT_LOW)
+
+/* Misc Enables */
+GPIO(EN_VCCIO_EXT,   PIN(6, 1), GPIO_OUT_LOW)
+/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
+GPIO(EN_VCCST,				PIN(A, 7), GPIO_INPUT)
+GPIO(EN_PP3300_PEN,			PIN(6, 3), GPIO_OUT_LOW)
+GPIO(EN_PP3300_A,			PIN(0, 3), GPIO_OUT_LOW)
+GPIO(EN_PP5000_U,			PIN(A, 4), GPIO_OUT_LOW)
+GPIO(EN_SLP_Z,				PIN(8, 3), GPIO_OUT_LOW)
+GPIO(EN_BL_OD,				PIN(D, 3), GPIO_ODR_LOW)
+GPIO(ECH1_PACKET_MODE,			PIN(7, 5), GPIO_OUT_LOW)
+GPIO(SUB_C1_INT_EN_RAILS_ODL,		PIN(F, 5), GPIO_ODR_LOW)/* 5V power en */
+
+/* LED */
+GPIO(LED_W_ODL,         PIN(C, 3), GPIO_OUT_HIGH | GPIO_OPEN_DRAIN) /* LED White */
+GPIO(LED_Y_ODL,         PIN(C, 4), GPIO_OUT_HIGH | GPIO_OPEN_DRAIN) /* LED Amber */
+
+/* Power Sequencing */
+GPIO(EC_AP_PSYS,	     PIN(B, 7), GPIO_OUT_LOW)
+GPIO(EC_AP_RSMRST_L,         PIN(A, 6), GPIO_OUT_LOW)
+GPIO(EC_AP_PWR_BTN_ODL,      PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(EC_AP_RTCRST,           PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_AP_WAKE_ODL,         PIN(7, 4), GPIO_ODR_HIGH)
+GPIO(EC_AP_DPWROK,	     PIN(A, 3), GPIO_OUT_LOW)
+GPIO(EC_AP_PCH_PWROK_OD,     PIN(9, 4), GPIO_ODR_LOW)
+GPIO(EC_AP_VCCST_PWRGD_OD,   PIN(B, 1), GPIO_ODR_LOW)
+GPIO(EC_AP_SYS_PWROK,	     PIN(0, 2), GPIO_OUT_LOW)
+GPIO(EC_AP_MKBP_INT_L,	     PIN(7, 0), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_ODL,	     PIN(F, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(EC_ENTERING_RW,	     PIN(E, 3), GPIO_OUT_LOW)
+GPIO(ALL_SYS_PWRGD,	     PIN(A, 0), GPIO_OUT_LOW)
+GPIO(SYS_RST_ODL,	     PIN(C, 5), GPIO_ODR_HIGH)
+GPIO(CCD_MODE_ODL,	     PIN(E, 5), GPIO_ODR_HIGH)
+
+/* USB pins */
+GPIO(USB_C0_RST_ODL,	     PIN(9, 7), GPIO_OUT_HIGH) /* currently unused */
+GPIO(EC_AP_USB_C1_HDMI_HPD,  PIN(9, 6), GPIO_OUT_LOW)
+GPIO(EC_AP_USB_C0_HPD,	     PIN(9, 3), GPIO_OUT_LOW)
+GPIO(HDMI_SEL_L,	     PIN(7, 2), GPIO_OUT_HIGH)
+GPIO(EC_BATTERY_PRES_ODL,    PIN(E, 1), GPIO_INPUT)
+GPIO(USB_A0_CHARGE_EN_L, PIN(3, 7), GPIO_OUT_HIGH)	/* Enable A0 1.5A Charging */
+GPIO(USB_A1_CHARGE_EN_L, PIN(F, 3), GPIO_OUT_HIGH)	/* Enable A1 1.5A Charging */
+GPIO(EN_USB_A0_VBUS,	 PIN(4, 1), GPIO_OUT_LOW)	/* Enable A1 5V Charging */
+GPIO(EN_USB_A1_VBUS,	 PIN(F, 2), GPIO_OUT_LOW)	/* Enable A1 5V Charging */
+
+/*
+ * metaknight doesn't have these physical pins coming to the EC but uses other
+ * logic.
+ */
+UNIMPLEMENTED(AC_PRESENT)
+UNIMPLEMENTED(PG_EC_DSW_PWROK)
+UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
+UNIMPLEMENTED(VOLDN_BTN_ODL)
+UNIMPLEMENTED(VOLUP_BTN_ODL)
+
+/* Alternate Functions */
+/* ADC */
+ALTERNATE(PIN_MASK(F, BIT(0)), 0, MODULE_ADC, 0) /* ADC9 */
+ALTERNATE(PIN_MASK(4, 0x38), 0, MODULE_ADC, 0)   /* ADC0-2 */
+
+/* Keyboard */
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI0, KSI1 */
+ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI2-7 */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO0, KSO1 */
+ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO3-9 */
+ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO10-13 */
+ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO14 */
+GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW)	/* KSO2 inverted */
+
+/* PWM */
+ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0) /* PWM3 */
+
+/* UART */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)  /* UART1 */
+
+/* I2C */
+ALTERNATE(PIN_MASK(B, 0x3C), 0, MODULE_I2C, 0)   /* I2C7,I2C0 */
+ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)   /* I2C5 */
+ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)   /* I2C2, I2C1 SCL */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)   /* I2C1 SDA */
+
+/* NC pins, enable internal pull-up to avoid floating state. */
+GPIO(GPIO00_NC, PIN(0, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO32_NC, PIN(3, 2), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO35_NC, PIN(3, 5), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO40_NC, PIN(4, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO57_NC, PIN(5, 7), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO60_NC, PIN(6, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO73_NC, PIN(7, 3), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO80_NC, PIN(8, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO81_NC, PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO86_NC, PIN(8, 6), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO92_NC, PIN(9, 2), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOC2_NC, PIN(C, 2), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOD0_NC, PIN(D, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOD1_NC, PIN(D, 1), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOD6_NC, PIN(D, 6), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOE0_NC, PIN(E, 0), GPIO_INPUT | GPIO_PULL_UP)
diff --git a/board/metaknight/led.c b/board/metaknight/led.c
new file mode 100644
index 0000000000..f117146f48
--- /dev/null
+++ b/board/metaknight/led.c
@@ -0,0 +1,86 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power and battery LED control for Metaknight
+ */
+
+#include "chipset.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+
+#define LED_ON_LVL 0
+#define LED_OFF_LVL 1
+
+__override const int led_charge_lvl_1;
+
+__override const int led_charge_lvl_2 = 100;
+
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_BATTERY_LED,
+};
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_WHITE:
+		gpio_set_level(GPIO_LED_W_ODL, LED_ON_LVL);
+		gpio_set_level(GPIO_LED_Y_ODL, LED_OFF_LVL);
+		break;
+	case EC_LED_COLOR_AMBER:
+		gpio_set_level(GPIO_LED_W_ODL, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_Y_ODL, LED_ON_LVL);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		gpio_set_level(GPIO_LED_W_ODL, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_Y_ODL, LED_OFF_LVL);
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_battery(EC_LED_COLOR_WHITE);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(EC_LED_COLOR_AMBER);
+		else
+			led_set_color_battery(LED_OFF);
+	}
+	return EC_SUCCESS;
+}
diff --git a/board/metaknight/usb_pd_policy.c b/board/metaknight/usb_pd_policy.c
new file mode 100644
index 0000000000..23166f7fca
--- /dev/null
+++ b/board/metaknight/usb_pd_policy.c
@@ -0,0 +1,61 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "driver/charger/isl923x_public.h"
+#include "driver/tcpm/tcpci.h"
+#include "usb_pd.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+int pd_check_vconn_swap(int port)
+{
+	/* Allow VCONN swaps if the AP is on. */
+	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
+}
+
+void pd_power_supply_reset(int port)
+{
+	/* Disable VBUS */
+	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	if (port >= board_get_usb_pd_port_count())
+		return EC_ERROR_INVAL;
+
+	/* Disable charging. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
+	if (rv)
+		return rv;
+
+	/* Our policy is not to source VBUS when the AP is off. */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	/* Provide Vbus. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
+	if (rv)
+		return rv;
+
+	rv = raa489000_enable_asgate(port, true);
+	if (rv)
+		return rv;
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
diff --git a/board/metaknight/vif_override.xml b/board/metaknight/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/metaknight/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/mithrax/battery.c b/board/mithrax/battery.c
new file mode 100644
index 0000000000..16840d5b3d
--- /dev/null
+++ b/board/mithrax/battery.c
@@ -0,0 +1,122 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "common.h"
+#include "compile_time_macros.h"
+
+/*
+ * Battery info for all Mithrax battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	[BATTERY_C536] = {
+		/* BQ40Z50 Fuel Gauge */
+		.fuel_gauge = {
+			.manuf_name = "AS3GXAE3jB",
+			.device_name = "C536-49",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr = 0x00,
+				.reg_mask = 0x2000,		/* XDSG */
+				.disconnect_val = 0x2000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13200,
+			.voltage_normal		= 11800, /* mV */
+			.voltage_min		= 9000, /* mV */
+			.precharge_current	= 256,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 45,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 60,
+		},
+	},
+	[BATTERY_C490] = {
+		.fuel_gauge = {
+			.manuf_name = "AS3GWQd3jB",
+			.device_name = "C490-42",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr = 0x00,
+				.reg_mask = 0x2000,		/* XDSG */
+				.disconnect_val = 0x2000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13200,
+			.voltage_normal		= 11800, /* mV */
+			.voltage_min		= 9000, /* mV */
+			.precharge_current	= 256,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 45,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 60,
+		},
+	},
+	[BATTERY_C340] = {
+		.fuel_gauge = {
+			.manuf_name = "AS3FXXD3KB",
+			.device_name = "C340152",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr = 0x99,
+				.reg_mask       = 0x000C,
+				.disconnect_val = 0x000C,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0004,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13350,
+			.voltage_normal		= 11985, /* mV */
+			.voltage_min		= 9000, /* mV */
+			.precharge_current	= 256,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 45,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 60,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_C536;
diff --git a/board/mithrax/board.c b/board/mithrax/board.c
new file mode 100644
index 0000000000..49d2849ab1
--- /dev/null
+++ b/board/mithrax/board.c
@@ -0,0 +1,184 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "button.h"
+#include "charge_ramp.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/accel_lis2dw12.h"
+#include "driver/accelgyro_lsm6dso.h"
+#include "ec_commands.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "keyboard_backlight.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "registers.h"
+#include "rgb_keyboard.h"
+#include "switch.h"
+#include "tablet_mode.h"
+#include "throttle_ap.h"
+#include "usbc_config.h"
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* Console output macros */
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+
+static void rgb_backlight_config(void);
+
+/******************************************************************************/
+/* USB-A charging control */
+
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_PP5000_USBA_R,
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
+
+/******************************************************************************/
+
+__override void board_cbi_init(void)
+{
+	config_usb_db_type();
+}
+
+/* Called on AP S3 -> S0 transition */
+static void board_chipset_resume(void)
+{
+	/* Allow keyboard backlight to be enabled */
+	gpio_set_level(GPIO_EC_KB_BL_EN_L, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S5 -> S3 transition */
+static void board_chipset_startup(void)
+{
+	pen_config();
+	rgb_backlight_config();
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
+
+#ifdef CONFIG_CHARGE_RAMP_SW
+
+/*
+ * TODO(b/181508008): tune this threshold
+ */
+
+#define BC12_MIN_VOLTAGE 4400
+
+/**
+ * Return true if VBUS is too low
+ */
+int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
+{
+	int voltage;
+
+	if (charger_get_vbus_voltage(port, &voltage))
+		voltage = 0;
+
+	if (voltage == 0) {
+		CPRINTS("%s: must be disconnected", __func__);
+		return 1;
+	}
+
+	if (voltage < BC12_MIN_VOLTAGE) {
+		CPRINTS("%s: port %d: vbus %d lower than %d", __func__, port,
+			voltage, BC12_MIN_VOLTAGE);
+		return 1;
+	}
+
+	return 0;
+}
+
+#endif /* CONFIG_CHARGE_RAMP_SW */
+
+enum battery_present battery_hw_present(void)
+{
+	enum gpio_signal batt_pres;
+
+	batt_pres = GPIO_EC_BATT_PRES_ODL;
+
+	/* The GPIO is low when the battery is physically present */
+	return gpio_get_level(batt_pres) ? BP_NO : BP_YES;
+}
+
+static void board_init(void)
+{
+	if (ec_cfg_stylus() == STYLUS_PRSENT)
+		gpio_enable_interrupt(GPIO_PEN_DET_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+/**
+ * Deferred function to handle pen detect change
+ */
+static void pendetect_deferred(void)
+{
+	static int debounced_pen_detect;
+	int pen_detect = !gpio_get_level(GPIO_PEN_DET_ODL);
+
+	if (pen_detect == debounced_pen_detect)
+		return;
+
+	debounced_pen_detect = pen_detect;
+
+	if (!chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		gpio_set_level(GPIO_EN_PP5000_PEN, debounced_pen_detect);
+}
+DECLARE_DEFERRED(pendetect_deferred);
+DECLARE_HOOK(HOOK_INIT, pendetect_deferred, HOOK_PRIO_DEFAULT);
+
+void pen_detect_interrupt(enum gpio_signal s)
+{
+	/* Trigger deferred notification of pen detect change */
+	hook_call_deferred(&pendetect_deferred_data, 500 * MSEC);
+}
+
+void pen_config(void)
+{
+	if (ec_cfg_stylus() == STYLUS_PRSENT) {
+		/* Make sure pen detection is triggered or not at resume */
+		if (!gpio_get_level(GPIO_PEN_DET_ODL))
+			gpio_set_level(GPIO_EN_PP5000_PEN, 1);
+		else
+			gpio_set_level(GPIO_EN_PP5000_PEN, 0);
+	}
+}
+
+static void board_chipset_shutdown(void)
+{
+	gpio_set_level(GPIO_EN_PP5000_PEN, 0);
+	gpio_set_level(GPIO_EN_PP5000_LED, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
+
+static void rgb_backlight_config(void)
+{
+	if (ec_cfg_kb_backlight() == RGB)
+		gpio_set_level(GPIO_EN_PP5000_LED, 1);
+	else
+		gpio_set_level(GPIO_EN_PP5000_LED, 0);
+}
+
+void board_kblight_init(void)
+{
+	if ((IS_ENABLED(CONFIG_PWM_KBLIGHT)) &&
+	    (ec_cfg_kb_backlight() == SOLID_COLOR)) {
+		kblight_register(&kblight_pwm);
+		rgbkbd_type = EC_RGBKBD_TYPE_UNKNOWN;
+	} else if ((IS_ENABLED(CONFIG_RGB_KEYBOARD)) &&
+		   (ec_cfg_kb_backlight() == RGB)) {
+		kblight_register(&kblight_rgbkbd);
+		rgbkbd_type = EC_RGBKBD_TYPE_FOUR_ZONES_4_LEDS;
+	}
+}
diff --git a/board/mithrax/board.h b/board/mithrax/board.h
new file mode 100644
index 0000000000..22878a936d
--- /dev/null
+++ b/board/mithrax/board.h
@@ -0,0 +1,240 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Mithrax board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "compile_time_macros.h"
+
+/* Baseboard features */
+#include "baseboard.h"
+
+/*
+ * This will happen automatically on NPCX9 ES2 and later. Do not remove
+ * until we can confirm all earlier chips are out of service.
+ */
+#define CONFIG_HIBERNATE_PSL_VCC1_RST_WAKEUP
+
+#define CONFIG_MP2964
+
+/* KEYBOARD */
+#define CONFIG_KEYBOARD_CUSTOMIZATION
+#define CONFIG_KEYBOARD_VIVALDI
+#define CONFIG_KEYBOARD_REFRESH_ROW3
+
+/* LED */
+#define CONFIG_LED_ONOFF_STATES
+#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
+#define GPIO_BAT_LED_AMBER_L GPIO_LED_3_L
+#define GPIO_BAT_LED_WHITE_L GPIO_LED_4_L
+
+/* Sensors */
+#define CONFIG_ACCELGYRO_LSM6DSO /* Base accel */
+#define CONFIG_ACCEL_LSM6DSO_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+/* Enable sensor fifo, must also define the _SIZE and _THRES */
+#define CONFIG_ACCEL_FIFO
+/* FIFO size is in power of 2. */
+#define CONFIG_ACCEL_FIFO_SIZE 256
+/* Depends on how fast the AP boots and typical ODRs */
+#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
+
+/* Sensors without hardware FIFO are in forced mode */
+#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
+/* Lid accel */
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_UPDATE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+#define CONFIG_ACCEL_LIS2DWL
+#define CONFIG_ACCEL_LIS2DW_AS_BASE
+#define CONFIG_ACCEL_LIS2DW12_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
+
+/* Sensor console commands */
+#define CONFIG_CMD_ACCELS
+#define CONFIG_CMD_ACCEL_INFO
+
+/* USB Type A Features */
+#define USB_PORT_COUNT 1
+#define CONFIG_USB_PORT_POWER_DUMB
+
+/* USB Type C and USB PD defines */
+#define CONFIG_IO_EXPANDER
+#define CONFIG_IO_EXPANDER_NCT38XX
+#define CONFIG_IO_EXPANDER_PORT_COUNT 2
+
+#define CONFIG_USB_PD_TCPM_PS8815
+
+/* I2C control host command */
+#define CONFIG_HOSTCMD_I2C_CONTROL
+
+/* Disable console commands to help save space */
+#undef CONFIG_CMD_POWERINDEBUG
+
+#define CONFIG_USBC_PPC_SYV682X
+#define CONFIG_USBC_PPC_NX20P3483
+
+/* TODO: b/177608416 - measure and check these values on mithrax */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
+
+/*
+ * Passive USB-C cables only support up to 60W.
+ */
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 65000
+#define PD_MAX_CURRENT_MA 3250
+#define PD_MAX_VOLTAGE_MV 20000
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
+
+/*
+ * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
+ * signal.
+ */
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
+
+/* System has back-lit keyboard */
+#define CONFIG_KEYBOARD_BACKLIGHT
+
+/* I2C Bus Configuration */
+
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+
+#define I2C_PORT_USB_C2_TCPC NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1
+
+#define I2C_PORT_USB_C2_PPC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1
+
+#define I2C_PORT_USB_C2_BC12 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1
+
+#define I2C_PORT_USB_C2_MUX NPCX_I2C_PORT3_0
+#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1
+
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0
+#define I2C_PORT_KBMCU NPCX_I2C_PORT3_0
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+
+#define I2C_ADDR_MP2964_FLAGS 0x20
+
+/*
+ *
+ */
+
+/* Retimer */
+#define CONFIG_USBC_RETIMER_FW_UPDATE
+
+/* Thermal features */
+#define CONFIG_THERMISTOR
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_TEMP_SENSOR_POWER
+#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
+
+#define CONFIG_FANS FAN_CH_COUNT
+
+/* Charger defines */
+#define CONFIG_CHARGER_ISL9241
+#define CONFIG_CHARGE_RAMP_SW
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 10
+
+/* RGB Keyboard */
+#ifdef SECTION_IS_RW
+#define CONFIG_RGB_KEYBOARD
+#define CONFIG_LED_DRIVER_TLC59116F /* TLC59116F on I2C */
+#define TLC59116F_I2C_ADDR_FLAG TLC59116F_ADDR3_FLAG
+#endif /* SECTION_IS_RW */
+#define RGB_GRID0_COL 4
+#define RGB_GRID0_ROW 1
+
+#define CONFIG_PWM_KBLIGHT
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h" /* needed by registers.h */
+#include "registers.h"
+#include "usbc_config.h"
+
+enum adc_channel {
+	ADC_TEMP_SENSOR_1_DDR_SOC,
+	ADC_TEMP_SENSOR_2_FAN,
+	ADC_TEMP_SENSOR_3_CHARGER,
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1_DDR_SOC,
+	TEMP_SENSOR_2_FAN,
+	TEMP_SENSOR_3_CHARGER,
+	TEMP_SENSOR_COUNT
+};
+
+enum sensor_id { LID_ACCEL = 0, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
+
+enum ioex_port { IOEX_C2_NCT38XX = 0, IOEX_C1_NCT38XX, IOEX_PORT_COUNT };
+
+enum battery_type {
+	BATTERY_C536,
+	BATTERY_C490,
+	BATTERY_C340,
+	BATTERY_TYPE_COUNT
+};
+
+enum pwm_channel {
+	PWM_CH_KBLIGHT = 0, /* PWM3 */
+	PWM_CH_FAN, /* PWM5 */
+	PWM_CH_COUNT
+};
+
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT };
+
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT };
+
+void pen_detect_interrupt(enum gpio_signal s);
+
+void pen_config(void);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/mithrax/build.mk b/board/mithrax/build.mk
new file mode 100644
index 0000000000..ca2d2e6c70
--- /dev/null
+++ b/board/mithrax/build.mk
@@ -0,0 +1,26 @@
+# -*- makefile -*-
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Mithrax board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx9
+CHIP_VARIANT:=npcx9m3f
+BASEBOARD:=brya
+
+board-y=
+board-y+=battery.o
+board-y+=board.o
+board-y+=charger_isl9241.o
+board-y+=fans.o
+board-y+=fw_config.o
+board-y+=i2c.o
+board-y+=keyboard.o
+board-y+=led.o
+board-y+=pwm.o
+board-y+=sensors.o
+board-y+=usbc_config.o
+board-y+=keyboard_customization.o
diff --git a/board/mithrax/charger_isl9241.c b/board/mithrax/charger_isl9241.c
new file mode 100644
index 0000000000..76e2712181
--- /dev/null
+++ b/board/mithrax/charger_isl9241.c
@@ -0,0 +1,80 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/charger/isl9241.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/* Charger Chip Configuration */
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = ISL9241_ADDR_FLAGS,
+		.drv = &isl9241_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CHARGER_NUM);
+
+int board_set_active_charge_port(int port)
+{
+	int is_valid_port = board_is_usb_pd_port_present(port);
+	int i;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTSUSB("Disabling all charger ports");
+
+		/* Disable all ports. */
+		for (i = 0; i < ppc_cnt; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (ppc_vbus_sink_enable(i, 0))
+				CPRINTSUSB("Disabling C%d as sink failed.", i);
+		}
+
+		return EC_SUCCESS;
+	} else if (!is_valid_port) {
+		return EC_ERROR_INVAL;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (ppc_is_sourcing_vbus(port)) {
+		CPRINTFUSB("Skip enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTSUSB("New charge port: C%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < ppc_cnt; i++) {
+		if (i == port)
+			continue;
+
+		if (ppc_vbus_sink_enable(i, 0))
+			CPRINTSUSB("C%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTSUSB("C%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/board/mithrax/ec.tasklist b/board/mithrax/ec.tasklist
new file mode 100644
index 0000000000..8949bb98e7
--- /dev/null
+++ b/board/mithrax/ec.tasklist
@@ -0,0 +1,31 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ *
+ * USB_CHG_Px tasks must be contiguous (see USB_CHG_PORT_TO_TASK_ID(x)).
+ * PD_Cx tasks must be contiguous (see PD_PORT_TO_TASK_ID(x))
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, HOOKS_TASK_STACK_SIZE) \
+	TASK_ALWAYS_RW(RGBKBD, rgbkbd_task, NULL, BASEBOARD_RGBKBD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, BASEBOARD_CHG_RAMP_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, BASEBOARD_CHARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, BASEBOARD_CHIPSET_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, CONSOLE_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, BASEBOARD_POWERBTN_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, BASEBOARD_PD_INT_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, BASEBOARD_PD_INT_TASK_STACK_SIZE)
diff --git a/board/mithrax/fans.c b/board/mithrax/fans.c
new file mode 100644
index 0000000000..9dbc34589e
--- /dev/null
+++ b/board/mithrax/fans.c
@@ -0,0 +1,82 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Physical fans. These are logically separate from pwm_channels. */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "fan.h"
+#include "fan_chip.h"
+#include "hooks.h"
+#include "pwm.h"
+
+/* MFT channels. These are logically separate from pwm_channels. */
+const struct mft_t mft_channels[] = {
+	[MFT_CH_0] = {
+		.module = NPCX_MFT_MODULE_1,
+		.clk_src = TCKC_LFCLK,
+		.pwm_id = PWM_CH_FAN,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
+
+static const struct fan_conf fan_conf_0 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
+	.pgood_gpio = -1,
+	.enable_gpio = GPIO_EN_PP5000_FAN,
+};
+
+static const struct fan_rpm fan_rpm_0 = {
+	.rpm_min = 1100,
+	.rpm_start = 2000,
+	.rpm_max = 5000,
+};
+
+const struct fan_t fans[FAN_CH_COUNT] = {
+	[FAN_CH_0] = {
+		.conf = &fan_conf_0,
+		.rpm = &fan_rpm_0,
+	},
+};
+
+#ifndef CONFIG_FANS
+
+/*
+ * TODO(b/181271666): use static fan speeds until fan and sensors are
+ * tuned. for now, use:
+ *
+ *   AP off:  33%
+ *   AP  on: 100%
+ */
+
+static void fan_slow(void)
+{
+	const int duty_pct = 33;
+
+	ccprints("%s: speed %d%%", __func__, duty_pct);
+
+	pwm_enable(PWM_CH_FAN, 1);
+	pwm_set_duty(PWM_CH_FAN, duty_pct);
+}
+
+static void fan_max(void)
+{
+	const int duty_pct = 100;
+
+	ccprints("%s: speed %d%%", __func__, duty_pct);
+
+	pwm_enable(PWM_CH_FAN, 1);
+	pwm_set_duty(PWM_CH_FAN, duty_pct);
+}
+
+DECLARE_HOOK(HOOK_INIT, fan_slow, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, fan_slow, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, fan_slow, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_RESET, fan_max, HOOK_PRIO_FIRST);
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, fan_max, HOOK_PRIO_DEFAULT);
+
+#endif /* CONFIG_FANS */
diff --git a/board/mithrax/fw_config.c b/board/mithrax/fw_config.c
new file mode 100644
index 0000000000..17b623371f
--- /dev/null
+++ b/board/mithrax/fw_config.c
@@ -0,0 +1,60 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "fw_config.h"
+
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
+
+static union mithrax_cbi_fw_config fw_config;
+BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
+
+/*
+ * FW_CONFIG defaults for mithrax if the CBI.FW_CONFIG data is not
+ * initialized.
+ */
+static const union mithrax_cbi_fw_config fw_config_defaults = {
+	.usb_db = DB_USB3_PS8815,
+	.kb_bl = KEYBOARD_BACKLIGHT_ENABLED,
+};
+
+/****************************************************************************
+ * Mithrax FW_CONFIG access
+ */
+void board_init_fw_config(void)
+{
+	if (cbi_get_fw_config(&fw_config.raw_value)) {
+		CPRINTS("CBI: Read FW_CONFIG failed, using board defaults");
+		fw_config = fw_config_defaults;
+	}
+}
+
+union mithrax_cbi_fw_config get_fw_config(void)
+{
+	return fw_config;
+}
+
+enum ec_cfg_usb_db_type ec_cfg_usb_db_type(void)
+{
+	return fw_config.usb_db;
+}
+
+enum ec_cfg_usb_mb_type ec_cfg_usb_mb_type(void)
+{
+	return fw_config.usb_mb;
+}
+
+enum ec_cfg_stylus_type ec_cfg_stylus(void)
+{
+	return fw_config.stylus;
+}
+
+enum ec_cfg_kb_backlight_type ec_cfg_kb_backlight(void)
+{
+	return fw_config.rgb;
+}
diff --git a/board/mithrax/fw_config.h b/board/mithrax/fw_config.h
new file mode 100644
index 0000000000..c7053c0da4
--- /dev/null
+++ b/board/mithrax/fw_config.h
@@ -0,0 +1,81 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __BOARD_MITHRAX_FW_CONFIG_H_
+#define __BOARD_MITHRAX_FW_CONFIG_H_
+
+#include <stdint.h>
+
+/****************************************************************************
+ * CBI FW_CONFIG layout for mithrax board.
+ *
+ * Source of truth is the project/brya/mithrax/config.star configuration file.
+ */
+
+enum ec_cfg_usb_db_type { DB_USB_ABSENT = 0, DB_USB3_PS8815 = 1 };
+
+enum ec_cfg_keyboard_backlight_type {
+	KEYBOARD_BACKLIGHT_DISABLED = 0,
+	KEYBOARD_BACKLIGHT_ENABLED = 1
+};
+
+enum ec_cfg_usb_mb_type { NA = 0, MB_USB3_NON_TBT = 1 };
+
+enum ec_cfg_stylus_type { STYLUS_ABSENT = 0, STYLUS_PRSENT = 1 };
+
+enum ec_cfg_kb_backlight_type { SOLID_COLOR = 0, RGB = 1 };
+
+union mithrax_cbi_fw_config {
+	struct {
+		enum ec_cfg_usb_db_type usb_db : 3;
+		uint32_t wifi : 1;
+		enum ec_cfg_kb_backlight_type rgb : 1;
+		enum ec_cfg_stylus_type stylus : 1;
+		enum ec_cfg_keyboard_backlight_type kb_bl : 1;
+		uint32_t audio : 3;
+		uint32_t thermal : 2;
+		uint32_t table_mode : 1;
+		enum ec_cfg_usb_mb_type usb_mb : 3;
+		uint32_t reserved_1 : 16;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Read the cached FW_CONFIG.  Guaranteed to have valid values.
+ *
+ * @return the FW_CONFIG for the board.
+ */
+union mithrax_cbi_fw_config get_fw_config(void);
+
+/**
+ * Get the USB daughter board type from FW_CONFIG.
+ *
+ * @return the USB daughter board type.
+ */
+enum ec_cfg_usb_db_type ec_cfg_usb_db_type(void);
+
+/**
+ * Get the USB main board type from FW_CONFIG.
+ *
+ * @return the USB main board type.
+ */
+enum ec_cfg_usb_mb_type ec_cfg_usb_mb_type(void);
+
+#endif /* __BOARD_MITHRAX_FW_CONFIG_H_ */
+
+/**
+ * Get the stylus type from FW_CONFIG.
+ *
+ * @return the stylus type.
+ */
+enum ec_cfg_stylus_type ec_cfg_stylus(void);
+
+/**
+ * Get the rgb type from FW_CONFIG.
+ *
+ * @return the rgb type.
+ */
+enum ec_cfg_kb_backlight_type ec_cfg_kb_backlight(void);
diff --git a/board/mithrax/gpio.inc b/board/mithrax/gpio.inc
new file mode 100644
index 0000000000..1ee2ae40f0
--- /dev/null
+++ b/board/mithrax/gpio.inc
@@ -0,0 +1,154 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define MODULE_KB		MODULE_KEYBOARD_SCAN
+
+/* INTERRUPT GPIOs: */
+GPIO_INT(ACOK_OD,                        PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
+GPIO_INT(EC_ACCEL_INT_R_L,               PIN(8, 1), GPIO_SEL_1P8V | GPIO_INT_FALLING, lis2dw12_interrupt)
+GPIO_INT(EC_IMU_INT_R_L,                 PIN(5, 6), GPIO_SEL_1P8V | GPIO_INT_FALLING, lsm6dso_interrupt)
+GPIO_INT(EC_PROCHOT_IN_L,                PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
+GPIO_INT(EC_VOLDN_BTN_ODL,               PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(EC_VOLUP_BTN_ODL,               PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(EC_WP_ODL,                      PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(GSC_EC_PWR_BTN_ODL,             PIN(0, 1), GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW, power_button_interrupt)
+GPIO_INT(LID_OPEN,                       PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
+GPIO_INT(SEQ_EC_ALL_SYS_PG,              PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_DSW_PWROK,               PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_RSMRST_ODL,              PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,                       PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,                      PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SYS_SLP_S0IX_L,                 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(TABLET_MODE_L,                  PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
+GPIO_INT(USB_C2_TCPC_INT_ODL,            PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C1_BC12_INT_ODL,            PIN(5, 0), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C1_PPC_INT_ODL,             PIN(F, 5), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C1_TCPC_INT_ODL,            PIN(A, 2), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C2_BC12_INT_ODL,            PIN(8, 3), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C2_PPC_INT_ODL,             PIN(7, 0), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C2_RT_INT_ODL,              PIN(4, 1), GPIO_INT_FALLING, retimer_interrupt)
+GPIO_INT(PEN_DET_ODL,                    PIN(D, 4), GPIO_INT_BOTH, pen_detect_interrupt)
+
+/* USED GPIOs: */
+GPIO(CCD_MODE_ODL,                   PIN(E, 5), GPIO_INPUT)
+GPIO(CHARGER_VAP_OTG_EN,             PIN(7, 3), GPIO_OUT_LOW)
+GPIO(CPU_C10_GATE_L,                 PIN(6, 7), GPIO_INPUT)
+GPIO(EC_BATT_PRES_ODL,               PIN(A, 3), GPIO_INPUT)
+GPIO(EC_ENTERING_RW,                 PIN(0, 3), GPIO_OUT_LOW)
+GPIO(EC_EN_EDP_BL,                   PIN(D, 3), GPIO_OUT_HIGH)
+GPIO(EC_GSC_PACKET_MODE,             PIN(7, 5), GPIO_OUT_LOW)
+GPIO(EC_I2C_BAT_SCL,                 PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_BAT_SDA,                 PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SCL_R,              PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SDA_R,              PIN(B, 2), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,              PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SENSOR_SDA,              PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_USB_C0_C2_PPC_BC_SCL,    PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_PPC_BC_SDA,    PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_RT_SCL,        PIN(D, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_RT_SDA,        PIN(D, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_TCPC_SCL,      PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_TCPC_SDA,      PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_MIX_SCL,          PIN(E, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_MIX_SDA,          PIN(E, 3), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_TCPC_SCL,         PIN(F, 3), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_TCPC_SDA,         PIN(F, 2), GPIO_INPUT)
+GPIO(EC_KB_BL_EN_L,                  PIN(8, 6), GPIO_OUT_HIGH)
+GPIO(EC_PCHHOT_ODL,                  PIN(7, 4), GPIO_INPUT)
+GPIO(EC_PCH_INT_ODL,                 PIN(B, 0), GPIO_ODR_HIGH)
+GPIO(EC_PCH_PWR_BTN_ODL,             PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(EC_PCH_RSMRST_L,                PIN(A, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_RTCRST,                  PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_SYS_PWROK,               PIN(3, 7), GPIO_OUT_LOW)
+GPIO(EC_PCH_WAKE_R_ODL,              PIN(C, 0), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_ODL,                 PIN(6, 3), GPIO_ODR_HIGH)
+GPIO(EN_PP5000_FAN,                  PIN(6, 1), GPIO_OUT_HIGH)
+GPIO(EN_PP5000_LED,                  PIN(C, 6), GPIO_OUT_LOW)
+GPIO(EN_PP5000_USBA_R,               PIN(D, 7), GPIO_OUT_LOW)
+GPIO(EN_PP5000_PEN,                  PIN(E, 1), GPIO_OUT_LOW)
+GPIO(EN_S5_RAILS,                    PIN(B, 6), GPIO_OUT_LOW)
+GPIO(IMVP9_VRRDY_OD,                 PIN(4, 3), GPIO_INPUT)
+GPIO(PCH_PWROK,                      PIN(7, 2), GPIO_OUT_LOW)
+GPIO(SYS_RST_ODL,                    PIN(C, 5), GPIO_ODR_HIGH)
+GPIO(USB_C0_C2_TCPC_RST_ODL,         PIN(A, 7), GPIO_ODR_LOW)
+GPIO(USB_C1_FRS_EN,                  PIN(9, 4), GPIO_OUT_LOW)
+GPIO(USB_C1_RST_ODL,                 PIN(9, 6), GPIO_ODR_LOW)
+GPIO(USB_C1_RT_INT_ODL,              PIN(A, 0), GPIO_INPUT)
+GPIO(USB_C1_RT_RST_R_ODL,            PIN(0, 2), GPIO_ODR_LOW)
+GPIO(VCCST_PWRGD_OD,                 PIN(A, 4), GPIO_ODR_LOW)
+
+/* LED */
+GPIO(LED_4_L,                        PIN(6, 0), GPIO_OUT_HIGH) /* battery led white */
+GPIO(LED_3_L,                        PIN(C, 2), GPIO_OUT_HIGH) /* battery led amber */
+
+/* UART alternate functions */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)              /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */
+
+/* I2C alternate functions */
+ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)               /* GPIO33/I2C5_SCL0/CTS_L, GPIO36/RTS_L/I2C5_SDA0 */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)               /* GPIO87/I2C1_SDA0 */
+ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)               /* GPIO92/I2C2_SCL0, GPIO91/I2C2_SDA0, GPIO90/I2C1_SCL0 */
+ALTERNATE(PIN_MASK(B, 0x0c), 0, MODULE_I2C, 0)               /* GPIOB3/I2C7_SCL0/DCD_L, GPIOB2/I2C7_SDA0/DSR_L */
+ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, GPIO_SEL_1P8V)   /* GPIOB5/I2C0_SCL0, GPIOB4/I2C0_SDA0 */
+ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)               /* GPIOD1/I2C3_SCL0, GPIOD0/I2C3_SDA0 */
+ALTERNATE(PIN_MASK(E, 0x18), 0, MODULE_I2C, 0)               /* GPIOE4/I2C6_SCL1/I3C_SCL, GPIOE3/I2C6_SDA1/I3C_SDA */
+ALTERNATE(PIN_MASK(F, 0x0c), 0, MODULE_I2C, 0)               /* GPIOF3/I2C4_SCL1, GPIOF2/I2C4_SDA1 */
+
+/* PWM alternate functions */
+ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0)               /* GPIO40/TA1 */
+ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)               /* GPIO80/PWM3 */
+ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)               /* GPIOB7/PWM5 */
+
+/* ADC alternate functions */
+ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0)               /* GPIO34/PS2_DAT2/ADC6 */
+ALTERNATE(PIN_MASK(4, 0x34), 0, MODULE_ADC, 0)               /* GPIO42/ADC3/RI_L, GPIO45/ADC0, GPIO44/ADC1 */
+
+/* KB alternate functions */
+ALTERNATE(PIN_MASK(0, 0xf0), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO10&P80_CLK/GPIO07, KSO11&P80_DAT/GPIO06, KSO12/GPIO05, KSO13/GPIO04 */
+ALTERNATE(PIN_MASK(1, 0x7f), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO06/GPO13/GP_SEL_L, KSO07/GPO12/JEN_L, KSO03/GPIO16/JTAG_TDO0_SWO, KSO04/GPIO15/XNOR, KSO05/GPIO14, KSO08/GPIO11/CR_SOUT1, KSO09/GPIO10/CR_SIN1 */
+ALTERNATE(PIN_MASK(2, 0xfc), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI2/GPIO27/TRACEDATA1, KSI3/GPIO26/TRACEDATA0, KSI4/GPIO25/TRACECLK/GP_SCLK, KSI5/GPIO24/GP_MISO, KSI6/GPIO23/S_SBUB, KSI7/GPIO22/S_SBUA */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO00/GPIO21/JTAG_TCK_SWCLK, KSO01/GPIO20/JTAG_TMS_SWIO */
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI0/GPIO31/TRACEDATA3/GP_MOSI, KSI1/GPIO30/TRACEDATA2/GP_CS_L */
+ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO14/GPIO82 */
+
+/* PMU alternate functions */
+ALTERNATE(PIN_MASK(0, 0x01), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN2_L&GPI00/GPIO00 */
+ALTERNATE(PIN_MASK(0, 0x02), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW) /* GPIO01/PSL_IN3_L&GPI01 */
+ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN1_L&GPID2/GPIOD2 */
+
+/* Unused Pins */
+UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
+UNUSED(PIN(3, 2))       /* GPO32/TRIS_L */
+UNUSED(PIN(3, 5))       /* GPO35/CR_SOUT4/TEST_L */
+UNUSED(PIN(6, 6))       /* GPIO66 */
+UNUSED(PIN(C, 3))       /* GPIOC3 */
+UNUSED(PIN(C, 4))       /* GPIOC4 */
+UNUSED(PIN(6, 2))       /* GPIO62 */
+UNUSED(PIN(B, 1))       /* GPIOB1 */
+UNUSED(PIN(5, 7))       /* GPIO57/SER_IRQ/ESPI_ALERT_L */
+
+/* Pre-configured PSL balls:  J8  K6 */
+
+
+/*
+ * The NPCX keyboard driver does not use named GPIOs to access
+ * keyboard scan pins, so we do not list them in *gpio.inc. However, when
+ * KEYBOARD_COL2_INVERTED is defined, this name is required.
+ */
+GPIO(EC_KSO_02_INV,               PIN(1, 7), GPIO_OUT_LOW)
+
+/* GPIO02_P2 to PU */
+/* GPIO03_P2 to PU */
+
+IOEX(USB_C1_RT_RST_ODL,      EXPIN(IOEX_C1_NCT38XX, 0, 2), GPIO_ODR_LOW)
+IOEX(USB_C1_OC_ODL,          EXPIN(IOEX_C1_NCT38XX, 0, 4), GPIO_ODR_HIGH)
+IOEX(USB_C1_FRS_EN,          EXPIN(IOEX_C1_NCT38XX, 0, 6), GPIO_LOW)
+
+IOEX(USB_C2_RT_RST_ODL,      EXPIN(IOEX_C2_NCT38XX, 0, 2), GPIO_ODR_LOW)
+IOEX(USB_C2_OC_ODL,          EXPIN(IOEX_C2_NCT38XX, 0, 4), GPIO_ODR_HIGH)
+IOEX(USB_C2_FRS_EN,          EXPIN(IOEX_C2_NCT38XX, 0, 6), GPIO_LOW)
+/* GPIO07_P2 to PU */
diff --git a/board/mithrax/i2c.c b/board/mithrax/i2c.c
new file mode 100644
index 0000000000..1a5d348c30
--- /dev/null
+++ b/board/mithrax/i2c.c
@@ -0,0 +1,78 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "i2c.h"
+
+/* I2C port map configuration */
+const struct i2c_port_t i2c_ports[] = {
+	{
+		/* I2C0 */
+		.name = "sensor",
+		.port = I2C_PORT_SENSOR,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_SENSOR_SCL,
+		.sda = GPIO_EC_I2C_SENSOR_SDA,
+	},
+	{
+		/* I2C1 */
+		.name = "tcpc2",
+		.port = I2C_PORT_USB_C2_TCPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C2_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C2_TCPC_SDA,
+	},
+	{
+		/* I2C2 */
+		.name = "ppc2",
+		.port = I2C_PORT_USB_C2_PPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C2_PPC_BC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C2_PPC_BC_SDA,
+	},
+	{
+		/* I2C3 */
+		.name = "retimer2",
+		.port = I2C_PORT_USB_C2_MUX,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C2_RT_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C2_RT_SDA,
+	},
+	{
+		/* I2C4 C1 TCPC */
+		.name = "tcpc1",
+		.port = I2C_PORT_USB_C1_TCPC,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_USB_C1_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C1_TCPC_SDA,
+		.flags = I2C_PORT_FLAG_DYNAMIC_SPEED,
+	},
+	{
+		/* I2C5 */
+		.name = "battery",
+		.port = I2C_PORT_BATTERY,
+		.kbps = 100,
+		.scl = GPIO_EC_I2C_BAT_SCL,
+		.sda = GPIO_EC_I2C_BAT_SDA,
+	},
+	{
+		/* I2C6 */
+		.name = "ppc1",
+		.port = I2C_PORT_USB_C1_PPC,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_USB_C1_MIX_SCL,
+		.sda = GPIO_EC_I2C_USB_C1_MIX_SDA,
+	},
+	{
+		/* I2C7 */
+		.name = "eeprom",
+		.port = I2C_PORT_EEPROM,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_MISC_SCL_R,
+		.sda = GPIO_EC_I2C_MISC_SDA_R,
+	},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/board/mithrax/keyboard.c b/board/mithrax/keyboard.c
new file mode 100644
index 0000000000..36830958f5
--- /dev/null
+++ b/board/mithrax/keyboard.c
@@ -0,0 +1,107 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "ec_commands.h"
+#include "keyboard_scan.h"
+#include "rgb_keyboard.h"
+#include "timer.h"
+#include "tlc59116f.h"
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/* Increase from 50 us, because KSO_02 passes through the H1. */
+	.output_settle_us = 80,
+	/* Other values should be the same as the default configuration. */
+	.debounce_down_us = 9 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x1c, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0x86, 0xff, 0xff, 0x55, 0xff, 0xff, 0xff, 0xff,  /* full set */
+	},
+};
+
+static const struct ec_response_keybd_config mithrax_kb = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+static struct rgb_s grid0[RGB_GRID0_COL * RGB_GRID0_ROW];
+
+struct rgbkbd rgbkbds[] = {
+	[0] = {
+		.cfg = &(const struct rgbkbd_cfg) {
+			.drv = &tlc59116f_drv,
+			.i2c = I2C_PORT_KBMCU,
+			.col_len = RGB_GRID0_COL,
+			.row_len = RGB_GRID0_ROW,
+		},
+		.buf = grid0,
+	},
+};
+const uint8_t rgbkbd_count = ARRAY_SIZE(rgbkbds);
+
+const uint8_t rgbkbd_hsize = RGB_GRID0_COL;
+const uint8_t rgbkbd_vsize = RGB_GRID0_ROW;
+
+enum ec_rgbkbd_type rgbkbd_type;
+#define LED(x, y) RGBKBD_COORD((x), (y))
+#define DELM RGBKBD_DELM
+
+const uint8_t rgbkbd_map[] = {
+	DELM,	   LED(0, 0), DELM,	 LED(1, 0), DELM,
+	LED(2, 0), DELM,      LED(3, 0), DELM,	    DELM,
+};
+#undef LED
+#undef DELM
+const size_t rgbkbd_map_size = ARRAY_SIZE(rgbkbd_map);
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &mithrax_kb;
+}
+
+/*
+ * Row Column info for Top row keys T1 - T15.
+ * on mithrax_kb keyboard Row Column is customization
+ * need define row col to mapping matrix layout.
+ */
+__override const struct key {
+	uint8_t row;
+	uint8_t col;
+} vivaldi_keys[] = {
+	{ .row = 4, .col = 2 }, /* T1 */
+	{ .row = 3, .col = 2 }, /* T2 */
+	{ .row = 2, .col = 2 }, /* T3 */
+	{ .row = 1, .col = 2 }, /* T4 */
+	{ .row = 4, .col = 4 }, /* T5 */
+	{ .row = 3, .col = 4 }, /* T6 */
+	{ .row = 2, .col = 4 }, /* T7 */
+	{ .row = 2, .col = 9 }, /* T8 */
+	{ .row = 1, .col = 9 }, /* T9 */
+	{ .row = 1, .col = 4 }, /* T10 */
+	{ .row = 0, .col = 4 }, /* T11 */
+	{ .row = 1, .col = 5 }, /* T12 */
+	{ .row = 3, .col = 5 }, /* T13 */
+	{ .row = 2, .col = 1 }, /* T14 */
+	{ .row = 0, .col = 1 }, /* T15 */
+};
+BUILD_ASSERT(ARRAY_SIZE(vivaldi_keys) == MAX_TOP_ROW_KEYS);
diff --git a/board/mithrax/keyboard_customization.c b/board/mithrax/keyboard_customization.c
new file mode 100644
index 0000000000..f9b2dd27ce
--- /dev/null
+++ b/board/mithrax/keyboard_customization.c
@@ -0,0 +1,104 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "gpio.h"
+#include "keyboard_8042_sharedlib.h"
+#include "keyboard_config.h"
+#include "keyboard_customization.h"
+#include "keyboard_protocol.h"
+#include "keyboard_raw.h"
+
+static uint16_t scancode_set2[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = {
+	{ 0x0000, 0x0000, 0x0014, 0xe01f, 0xe014, 0x0000, 0x0000, 0x0000 },
+	{ 0x001f, 0x0076, 0x0017, 0x000e, 0x001c, 0x003a, 0x000d, 0x0016 },
+	{ 0x006c, 0xe024, 0xe01d, 0xe020, 0xe038, 0xe071, 0x0026, 0x002a },
+	{ 0x0032, 0x0034, 0x002c, 0x002e, 0x002b, 0x0029, 0x0025, 0x002d },
+	{ 0x0078, 0xe032, 0xe035, 0xe02c, 0xe02d, 0x0041, 0x001e, 0x001d },
+	{ 0x0051, 0x0007, 0x005b, 0x000f, 0x0042, 0x0022, 0x003e, 0x0043 },
+	{ 0x0031, 0x0033, 0x0035, 0x0036, 0x003b, 0x001b, 0x003d, 0x003c },
+	{ 0x0000, 0x0012, 0x0061, 0x0000, 0x0000, 0x0000, 0x0000, 0x0059 },
+	{ 0x0055, 0x0052, 0x0054, 0x004e, 0x004c, 0x0024, 0x0044, 0x004d },
+	{ 0x0045, 0xe021, 0xe023, 0x002f, 0x004b, 0x0049, 0x0046, 0x001a },
+	{ 0xe011, 0x0000, 0x006a, 0x0000, 0x005d, 0x0000, 0x0011, 0x0000 },
+	{ 0xe07a, 0x005d, 0xe075, 0x006b, 0x005a, 0xe072, 0x004a, 0x0066 },
+	{ 0xe06b, 0xe074, 0xe069, 0x0067, 0xe06c, 0x0064, 0x0015, 0xe07d },
+	{ 0x0073, 0x007c, 0x007b, 0x0074, 0x0071, 0xe04a, 0x0070, 0x0021 },
+	{ 0x0023, 0xe05a, 0x0075, 0x0079, 0x007a, 0x0072, 0x007d, 0x0069 },
+};
+
+uint16_t get_scancode_set2(uint8_t row, uint8_t col)
+{
+	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS)
+		return scancode_set2[col][row];
+	return 0;
+}
+
+void set_scancode_set2(uint8_t row, uint8_t col, uint16_t val)
+{
+	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS)
+		scancode_set2[col][row] = val;
+}
+
+void board_keyboard_drive_col(int col)
+{
+	/* Drive all lines to high */
+	if (col == KEYBOARD_COLUMN_NONE)
+		gpio_set_level(GPIO_KBD_KSO2, 0);
+
+	/* Set KBSOUT to zero to detect key-press */
+	else if (col == KEYBOARD_COLUMN_ALL)
+		gpio_set_level(GPIO_KBD_KSO2, 1);
+
+	/* Drive one line for detection */
+	else {
+		if (col == 2)
+			gpio_set_level(GPIO_KBD_KSO2, 1);
+		else
+			gpio_set_level(GPIO_KBD_KSO2, 0);
+	}
+}
+
+#ifdef CONFIG_KEYBOARD_DEBUG
+static uint8_t keycap_label[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = {
+	{ 'c', KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO },
+	{ KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO },
+	{ 'q', KLLI_UNKNO, KLLI_UNKNO, KLLI_TAB, '`', '1', KLLI_UNKNO, 'a' },
+	{ KLLI_R_ALT, KLLI_L_ALT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO },
+	{ KLLI_UNKNO, KLLI_SPACE, 'e', KLLI_F4, KLLI_SEARC, '3', KLLI_F3,
+	  KLLI_UNKNO },
+	{ 'x', 'z', KLLI_F2, KLLI_F1, 's', '2', 'w', KLLI_ESC },
+	{ 'v', 'b', 'g', 't', '5', '4', 'r', 'f' },
+	{ 'm', 'n', 'h', 'y', '6', '7', 'u', 'j' },
+	{ '.', KLLI_DOWN, '\\', 'o', KLLI_F10, '9', KLLI_UNKNO, 'l' },
+	{ KLLI_R_SHT, KLLI_L_SHT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO },
+	{ ',', KLLI_UNKNO, KLLI_F7, KLLI_F6, KLLI_F5, '8', 'i', 'k' },
+	{ KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_F9, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_LEFT, KLLI_UNKNO },
+	{ KLLI_R_CTR, KLLI_L_CTR, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO },
+	{ '/', KLLI_UP, '-', KLLI_UNKNO, '0', 'p', '[', ';' },
+	{ '\'', KLLI_ENTER, KLLI_UNKNO, KLLI_UNKNO, '=', KLLI_B_SPC, ']', 'd' },
+	{ KLLI_UNKNO, KLLI_F8, KLLI_RIGHT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO },
+};
+
+uint8_t get_keycap_label(uint8_t row, uint8_t col)
+{
+	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS)
+		return keycap_label[col][row];
+	return KLLI_UNKNO;
+}
+
+void set_keycap_label(uint8_t row, uint8_t col, uint8_t val)
+{
+	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS)
+		keycap_label[col][row] = val;
+}
+#endif
diff --git a/board/mithrax/keyboard_customization.h b/board/mithrax/keyboard_customization.h
new file mode 100644
index 0000000000..1d0e6ec483
--- /dev/null
+++ b/board/mithrax/keyboard_customization.h
@@ -0,0 +1,73 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Keyboard configuration */
+
+#ifndef __KEYBOARD_CUSTOMIZATION_H
+#define __KEYBOARD_CUSTOMIZATION_H
+
+/*
+ * KEYBOARD_COLS_MAX has the build time column size. It's used to allocate
+ * exact spaces for arrays. Actual keyboard scanning is done using
+ * keyboard_cols, which holds a runtime column size.
+ */
+#define KEYBOARD_COLS_MAX 15
+#define KEYBOARD_ROWS 8
+
+/*
+ * WARNING: Do not directly modify it. You should call keyboard_raw_set_cols,
+ * instead. It checks whether you're eligible or not.
+ */
+extern uint8_t keyboard_cols;
+
+#define KEYBOARD_ROW_TO_MASK(r) (1 << (r))
+
+/* Columns and masks for keys we particularly care about */
+#define KEYBOARD_COL_DOWN 11
+#define KEYBOARD_ROW_DOWN 5
+#define KEYBOARD_MASK_DOWN KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_DOWN)
+#define KEYBOARD_COL_ESC 1
+#define KEYBOARD_ROW_ESC 1
+#define KEYBOARD_MASK_ESC KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_ESC)
+#define KEYBOARD_COL_KEY_H 6
+#define KEYBOARD_ROW_KEY_H 1
+#define KEYBOARD_MASK_KEY_H KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_H)
+#define KEYBOARD_COL_KEY_R 3
+#define KEYBOARD_ROW_KEY_R 7
+#define KEYBOARD_MASK_KEY_R KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_R)
+#define KEYBOARD_COL_LEFT_ALT 10
+#define KEYBOARD_ROW_LEFT_ALT 6
+#define KEYBOARD_MASK_LEFT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_ALT)
+#define KEYBOARD_COL_REFRESH 2
+#define KEYBOARD_ROW_REFRESH 3
+#define KEYBOARD_MASK_REFRESH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_REFRESH)
+#define KEYBOARD_COL_RIGHT_ALT 10
+#define KEYBOARD_ROW_RIGHT_ALT 0
+#define KEYBOARD_MASK_RIGHT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_ALT)
+#define KEYBOARD_DEFAULT_COL_VOL_UP 4
+#define KEYBOARD_DEFAULT_ROW_VOL_UP 1
+#define KEYBOARD_COL_LEFT_CTRL 0
+#define KEYBOARD_ROW_LEFT_CTRL 2
+#define KEYBOARD_MASK_LEFT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_CTRL)
+#define KEYBOARD_COL_RIGHT_CTRL 0
+#define KEYBOARD_ROW_RIGHT_CTRL 4
+#define KEYBOARD_MASK_RIGHT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_CTRL)
+#define KEYBOARD_COL_SEARCH 0
+#define KEYBOARD_ROW_SEARCH 3
+#define KEYBOARD_MASK_SEARCH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_SEARCH)
+#define KEYBOARD_COL_KEY_0 9
+#define KEYBOARD_ROW_KEY_0 0
+#define KEYBOARD_MASK_KEY_0 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_0)
+#define KEYBOARD_COL_KEY_1 1
+#define KEYBOARD_ROW_KEY_1 7
+#define KEYBOARD_MASK_KEY_1 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_1)
+#define KEYBOARD_COL_KEY_2 4
+#define KEYBOARD_ROW_KEY_2 6
+#define KEYBOARD_MASK_KEY_2 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_2)
+#define KEYBOARD_COL_LEFT_SHIFT 7
+#define KEYBOARD_ROW_LEFT_SHIFT 1
+#define KEYBOARD_MASK_LEFT_SHIFT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_SHIFT)
+
+#endif /* __KEYBOARD_CUSTOMIZATION_H */
diff --git a/board/mithrax/led.c b/board/mithrax/led.c
new file mode 100644
index 0000000000..660fc8ce2d
--- /dev/null
+++ b/board/mithrax/led.c
@@ -0,0 +1,99 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power and battery LED control for mithrax
+ */
+
+#include "chipset.h"
+#include "gpio.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+#include "system.h"
+
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
+
+__override const int led_charge_lvl_1;
+__override const int led_charge_lvl_2 = 95;
+
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_WHITE,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+	};
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_BATTERY_LED,
+};
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_WHITE:
+		gpio_set_level(GPIO_BAT_LED_WHITE_L, LED_ON_LVL);
+		gpio_set_level(GPIO_BAT_LED_AMBER_L, LED_OFF_LVL);
+		break;
+	case EC_LED_COLOR_AMBER:
+		gpio_set_level(GPIO_BAT_LED_WHITE_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_BAT_LED_AMBER_L, LED_ON_LVL);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		gpio_set_level(GPIO_BAT_LED_WHITE_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_BAT_LED_AMBER_L, LED_OFF_LVL);
+		break;
+	}
+}
+
+__override enum led_states board_led_get_state(enum led_states desired_state)
+{
+	if (desired_state == STATE_BATTERY_ERROR) {
+		if (chipset_in_state(CHIPSET_STATE_ON))
+			return desired_state;
+		else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
+			return STATE_DISCHARGE_S3;
+		else
+			return STATE_DISCHARGE_S5;
+	}
+	return desired_state;
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_battery(EC_LED_COLOR_WHITE);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(EC_LED_COLOR_AMBER);
+		else
+			led_set_color_battery(LED_OFF);
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/board/mithrax/pwm.c b/board/mithrax/pwm.c
new file mode 100644
index 0000000000..c889b1d70e
--- /dev/null
+++ b/board/mithrax/pwm.c
@@ -0,0 +1,37 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "hooks.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_KBLIGHT] = {
+		.channel = 3,
+		.flags = 0,
+		/*
+		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
+		 * flicker. Higher frequencies consume similar average power to
+		 * lower PWM frequencies, but higher frequencies record a much
+		 * lower maximum power.
+		 */
+		.freq = 2400,
+	},
+	[PWM_CH_FAN] = {
+		.channel = 5,
+		.flags = PWM_CONFIG_OPEN_DRAIN,
+		.freq = 25000,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+static void board_pwm_init(void)
+{
+	pwm_enable(PWM_CH_KBLIGHT, 1);
+	pwm_set_duty(PWM_CH_KBLIGHT, 0);
+}
+DECLARE_HOOK(HOOK_INIT, board_pwm_init, HOOK_PRIO_DEFAULT);
diff --git a/board/mithrax/sensors.c b/board/mithrax/sensors.c
new file mode 100644
index 0000000000..215b0cd2c5
--- /dev/null
+++ b/board/mithrax/sensors.c
@@ -0,0 +1,235 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "accelgyro.h"
+#include "adc_chip.h"
+#include "common.h"
+#include "driver/accel_lis2dw12.h"
+#include "driver/accelgyro_lsm6dso.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "motion_sense.h"
+#include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
+#include "thermal.h"
+
+/* ADC configuration */
+const struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_1_DDR_SOC] = {
+		.name = "TEMP_DDR_SOC",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_2_FAN] = {
+		.name = "TEMP_FAN",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_3_CHARGER] = {
+		.name = "TEMP_CHARGER",
+		.input_ch = NPCX_ADC_CH6,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+K_MUTEX_DEFINE(g_lid_accel_mutex);
+K_MUTEX_DEFINE(g_base_accel_mutex);
+static struct stprivate_data g_lis2dw12_data;
+static struct lsm6dso_data lsm6dso_data;
+
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(1), 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
+
+/* TODO(b/184779743): verify orientation matrix */
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, FLOAT_TO_FP(-1), 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
+
+struct motion_sensor_t motion_sensors[] = {
+	[LID_ACCEL] = {
+		.name = "Lid Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LIS2DW12,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &lis2dw12_drv,
+		.mutex = &g_lid_accel_mutex,
+		.drv_data = &g_lis2dw12_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LIS2DW12_ADDR0,
+		.rot_standard_ref = &lid_standard_ref, /* identity matrix */
+		.default_range = 2, /* g */
+		.min_frequency = LIS2DW12_ODR_MIN_VAL,
+		.max_frequency = LIS2DW12_ODR_MAX_VAL,
+		.config = {
+			/* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 12500 | ROUND_UP_FLAG,
+			},
+			/* Sensor on for lid angle detection */
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+		},
+	},
+
+	[BASE_ACCEL] = {
+		.name = "Base Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LSM6DSO,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &lsm6dso_drv,
+		.mutex = &g_base_accel_mutex,
+		.drv_data = LSM6DSO_ST_DATA(lsm6dso_data,
+				MOTIONSENSE_TYPE_ACCEL),
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LSM6DSO_ADDR0_FLAGS,
+		.rot_standard_ref = &base_standard_ref,
+		.default_range = 4,  /* g */
+		.min_frequency = LSM6DSO_ODR_MIN_VAL,
+		.max_frequency = LSM6DSO_ODR_MAX_VAL,
+		.config = {
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 13000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+		},
+	},
+
+	[BASE_GYRO] = {
+		.name = "Base Gyro",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LSM6DSO,
+		.type = MOTIONSENSE_TYPE_GYRO,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &lsm6dso_drv,
+		.mutex = &g_base_accel_mutex,
+		.drv_data = LSM6DSO_ST_DATA(lsm6dso_data,
+				MOTIONSENSE_TYPE_GYRO),
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LSM6DSO_ADDR0_FLAGS,
+		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = LSM6DSO_ODR_MIN_VAL,
+		.max_frequency = LSM6DSO_ODR_MAX_VAL,
+	},
+};
+const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+static void baseboard_sensors_init(void)
+{
+	/* Enable gpio interrupt for lid accel sensor */
+	gpio_enable_interrupt(GPIO_EC_ACCEL_INT_R_L);
+	/* Enable gpio interrupt for base accelgyro sensor */
+	gpio_enable_interrupt(GPIO_EC_IMU_INT_R_L);
+}
+DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_INIT_I2C + 1);
+
+/* Temperature sensor configuration */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1_DDR_SOC] = { .name = "DDR and SOC",
+				    .type = TEMP_SENSOR_TYPE_BOARD,
+				    .read = get_temp_3v3_30k9_47k_4050b,
+				    .idx = ADC_TEMP_SENSOR_1_DDR_SOC },
+	[TEMP_SENSOR_2_FAN] = { .name = "FAN",
+				.type = TEMP_SENSOR_TYPE_BOARD,
+				.read = get_temp_3v3_30k9_47k_4050b,
+				.idx = ADC_TEMP_SENSOR_2_FAN },
+	[TEMP_SENSOR_3_CHARGER] = { .name = "Charger",
+				    .type = TEMP_SENSOR_TYPE_BOARD,
+				    .read = get_temp_3v3_30k9_47k_4050b,
+				    .idx = ADC_TEMP_SENSOR_3_CHARGER },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/*
+ * TODO(b/180681346): update for Alder Lake/mithrax
+ *
+ * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
+ * 130 C.  However, sensor is located next to DDR, so we need to use the lower
+ * DDR temperature limit (85 C)
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(60), \
+		}, \
+		.temp_fan_off = C_TO_K(30), \
+		.temp_fan_max = C_TO_K(73), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
+
+/*
+ * TODO(b/180681346): update for Alder Lake/mithrax
+ *
+ * Inductor limits - used for both charger and PP3300 regulator
+ *
+ * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
+ *
+ * Charger max recommended temperature 100C, max absolute temperature 125C
+ * PP3300 regulator: operating range -40 C to 145 C
+ *
+ * Inductors: limit of 125c
+ * PCB: limit is 80c
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_FAN              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(60), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(70), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(50), \
+		}, \
+		.temp_fan_off = C_TO_K(30), \
+		.temp_fan_max = C_TO_K(63), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_fan = THERMAL_FAN;
+
+#define THERMAL_CHARGER          \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(60), \
+		}, \
+		.temp_fan_off = C_TO_K(30), \
+		.temp_fan_max = C_TO_K(73), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_charger =
+	THERMAL_CHARGER;
+
+/* this should really be "const" */
+struct ec_thermal_config thermal_params[] = {
+	[TEMP_SENSOR_1_DDR_SOC] = THERMAL_CPU,
+	[TEMP_SENSOR_2_FAN] = THERMAL_FAN,
+	[TEMP_SENSOR_3_CHARGER] = THERMAL_CHARGER,
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
diff --git a/board/mithrax/usbc_config.c b/board/mithrax/usbc_config.c
new file mode 100644
index 0000000000..8557da622f
--- /dev/null
+++ b/board/mithrax/usbc_config.c
@@ -0,0 +1,346 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/bc12/pi3usb9201_public.h"
+#include "driver/ppc/nx20p348x.h"
+#include "driver/ppc/syv682x_public.h"
+#include "driver/retimer/bb_retimer_public.h"
+#include "driver/tcpm/nct38xx.h"
+#include "driver/tcpm/ps8xxx_public.h"
+#include "driver/tcpm/tcpci.h"
+#include "ec_commands.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "ioexpander.h"
+#include "system.h"
+#include "task.h"
+#include "task_id.h"
+#include "timer.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+/* USBC TCPC configuration */
+struct tcpc_config_t tcpc_config[] = {
+	[USBC_PORT_C2] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C2_TCPC,
+			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_NO_DEBUG_ACC_CONTROL,
+	},
+	[USBC_PORT_C1] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C1_TCPC,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
+			 TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V |
+			 TCPC_FLAGS_CONTROL_VCONN,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
+BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
+
+/* USBC PPC configuration */
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C2] = {
+		.i2c_port = I2C_PORT_USB_C2_PPC,
+		.i2c_addr_flags = SYV682X_ADDR2_FLAGS,
+		.drv = &syv682x_drv,
+	},
+	[USBC_PORT_C1] = {
+		/* Compatible with Silicon Mitus SM536A0 */
+		.i2c_port = I2C_PORT_USB_C1_PPC,
+		.i2c_addr_flags = NX20P3483_ADDR2_FLAGS,
+		.drv = &nx20p348x_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
+
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/*
+ * USB3 DB mux configuration - the top level mux still needs to be set
+ * to the virtual_usb_mux_driver so the AP gets notified of mux changes
+ * and updates the TCSS configuration on state changes.
+ */
+static const struct usb_mux_chain usbc1_usb3_db_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
+};
+
+struct usb_mux_chain usb_muxes[] = {
+	[USBC_PORT_C2] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C2,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+	},
+	[USBC_PORT_C1] = {
+		.mux = &(const struct usb_mux) {
+			/* PS8815 DB */
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc1_usb3_db_retimer,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
+
+/* BC1.2 charger detect configuration */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	[USBC_PORT_C2] = {
+		.i2c_port = I2C_PORT_USB_C2_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_1_FLAGS,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C1_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
+
+/*
+ * USB C0 and C2 uses burnside bridge chips and have their reset
+ * controlled by their respective TCPC chips acting as GPIO expanders.
+ *
+ * ioex_init() is normally called before we take the TCPCs out of
+ * reset, so we need to start in disabled mode, then explicitly
+ * call ioex_init().
+ */
+
+struct ioexpander_config_t ioex_config[] = {
+	[IOEX_C1_NCT38XX] = {
+		.i2c_host_port = I2C_PORT_USB_C1_TCPC,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
+	},
+	[IOEX_C2_NCT38XX] = {
+		.i2c_host_port = I2C_PORT_USB_C2_TCPC,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT);
+
+void config_usb_db_type(void)
+{
+	enum ec_cfg_usb_db_type db_type = ec_cfg_usb_db_type();
+
+	/*
+	 * TODO(b/180434685): implement multiple DB types
+	 */
+
+	CPRINTS("Configured USB DB type number is %d", db_type);
+}
+
+__override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
+{
+	int rst_signal;
+
+	if (me->usb_port == USBC_PORT_C1)
+		rst_signal = IOEX_USB_C1_RT_RST_ODL;
+	else if (me->usb_port == USBC_PORT_C2)
+		rst_signal = IOEX_USB_C2_RT_RST_ODL;
+	else
+		return EC_ERROR_INVAL;
+
+	/*
+	 * We do not have a load switch for the burnside bridge chips,
+	 * so we only need to sequence reset.
+	 */
+
+	if (enable) {
+		/*
+		 * Tpw, minimum time from VCC to RESET_N de-assertion is 100us.
+		 * For boards that don't provide a load switch control, the
+		 * retimer_init() function ensures power is up before calling
+		 * this function.
+		 */
+		gpio_or_ioex_set_level(rst_signal, 1);
+		/*
+		 * Allow 1ms time for the retimer to power up lc_domain
+		 * which powers I2C controller within retimer
+		 */
+		msleep(1);
+	} else {
+		gpio_or_ioex_set_level(rst_signal, 0);
+		msleep(1);
+	}
+	return EC_SUCCESS;
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * TODO(b/179648104): figure out correct timing
+	 */
+
+	gpio_set_level(GPIO_USB_C0_C2_TCPC_RST_ODL, 0);
+	gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 0);
+
+	/*
+	 * delay for power-on to reset-off and min. assertion time
+	 */
+
+	msleep(20);
+
+	gpio_set_level(GPIO_USB_C0_C2_TCPC_RST_ODL, 1);
+	gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 1);
+
+	/* wait for chips to come up */
+
+	msleep(50);
+}
+
+static void enable_ioex(int ioex)
+{
+	ioex_init(ioex);
+}
+
+static void board_tcpc_init(void)
+{
+	/* Don't reset TCPCs after initial reset */
+	if (!system_jumped_late()) {
+		board_reset_pd_mcu();
+
+		/*
+		 * These IO expander pins are implemented using the
+		 * C0/C2 TCPC, so they must be set up after the TCPC has
+		 * been taken out of reset.
+		 */
+		enable_ioex(IOEX_C2_NCT38XX);
+	}
+
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C2_PPC_INT_ODL);
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C2_TCPC_INT_ODL);
+
+	/* Enable BC1.2 interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C2_BC12_INT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (gpio_get_level(GPIO_USB_C2_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_0;
+
+	if (gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
+
+int ppc_get_alert_status(int port)
+{
+	if (port == USBC_PORT_C2)
+		return gpio_get_level(GPIO_USB_C2_PPC_INT_ODL) == 0;
+	else if (port == USBC_PORT_C1)
+		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
+	return 0;
+}
+
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C2_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C2);
+		break;
+	case GPIO_USB_C1_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C1);
+		break;
+	default:
+		break;
+	}
+}
+
+void bc12_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C2_BC12_INT_ODL:
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+		break;
+	case GPIO_USB_C1_BC12_INT_ODL:
+		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+		break;
+	default:
+		break;
+	}
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C1_PPC_INT_ODL:
+		nx20p348x_interrupt(USBC_PORT_C1);
+		break;
+	case GPIO_USB_C2_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C2);
+		break;
+	default:
+		break;
+	}
+}
+
+void retimer_interrupt(enum gpio_signal signal)
+{
+	/*
+	 * TODO(b/179513527): add USB-C support
+	 */
+}
+
+__override bool board_is_dts_port(int port)
+{
+	return port == USBC_PORT_C2;
+}
+
+__override bool board_is_tbt_usb4_port(int port)
+{
+	return false;
+}
+
+__override enum tbt_compat_cable_speed board_get_max_tbt_speed(int port)
+{
+	if (!board_is_tbt_usb4_port(port))
+		return TBT_SS_RES_0;
+
+	return TBT_SS_TBT_GEN3;
+}
diff --git a/board/mithrax/usbc_config.h b/board/mithrax/usbc_config.h
new file mode 100644
index 0000000000..22242d7c5b
--- /dev/null
+++ b/board/mithrax/usbc_config.h
@@ -0,0 +1,19 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Mithrax board-specific USB-C configuration */
+
+#ifndef __CROS_EC_USBC_CONFIG_H
+#define __CROS_EC_USBC_CONFIG_H
+
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#define CONFIG_USB_PD_TCPC_RUNTIME_CONFIG
+#define CONFIG_USB_MUX_RUNTIME_CONFIG
+
+enum usbc_port { USBC_PORT_C2 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
+
+void config_usb_db_type(void);
+
+#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/mithrax/vif_override.xml b/board/mithrax/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/mithrax/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/moli/board.c b/board/moli/board.c
new file mode 100644
index 0000000000..61f8580af2
--- /dev/null
+++ b/board/moli/board.c
@@ -0,0 +1,529 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc.h"
+#include "builtin/assert.h"
+#include "button.h"
+#include "cec.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "chipset.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "driver/cec/bitbang.h"
+#include "driver/tcpm/tcpci.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "power.h"
+#include "power_button.h"
+#include "switch.h"
+#include "throttle_ap.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+/* Console output macros */
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+
+static void power_monitor(void);
+DECLARE_DEFERRED(power_monitor);
+
+/******************************************************************************/
+/* Power on by HDMI/ DP monitor */
+struct monitor_config {
+	enum gpio_signal gpio;
+	uint8_t state;
+};
+
+static struct monitor_config monitors[MONITOR_COUNT] = {
+	[HDMI1_MONITOR] = {
+		.gpio = GPIO_HDMI1_MONITOR_ON,
+		.state = MONITOR_OFF,
+	},
+
+	[HDMI2_MONITOR] = {
+		.gpio = GPIO_HDMI2_MONITOR_ON,
+		.state = MONITOR_OFF,
+	},
+
+	[OPTION_MONITOR] = {
+		.gpio = GPIO_OPTION_MONITOR_ON,
+		.state = MONITOR_OFF,
+	},
+};
+
+/******************************************************************************/
+
+/******************************************************************************/
+/* USB-A charging control */
+
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_PP5000_USBA,
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
+
+/******************************************************************************/
+
+/* CEC ports */
+const struct cec_config_t cec_config[] = {
+	[CEC_PORT_0] = {
+		.drv = &bitbang_cec_drv,
+		.offline_policy = NULL,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(cec_config) == CEC_PORT_COUNT);
+
+int board_set_active_charge_port(int port)
+{
+	CPRINTS("Requested charge port change to %d", port);
+
+	/*
+	 * The charge manager may ask us to switch to no charger if we're
+	 * running off USB-C only but upstream doesn't support PD. It requires
+	 * that we accept this switch otherwise it triggers an assert and EC
+	 * reset; it's not possible to boot the AP anyway, but we want to avoid
+	 * resetting the EC so we can continue to do the "low power" LED blink.
+	 */
+	if (port == CHARGE_PORT_NONE)
+		return EC_SUCCESS;
+
+	if (port < 0 || CHARGE_PORT_COUNT <= port)
+		return EC_ERROR_INVAL;
+
+	if (port == charge_manager_get_active_charge_port())
+		return EC_SUCCESS;
+
+	/* Don't charge from a source port */
+	if (board_vbus_source_enabled(port))
+		return EC_ERROR_INVAL;
+
+	if (!chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
+		int bj_active, bj_requested;
+
+		if (charge_manager_get_active_charge_port() != CHARGE_PORT_NONE)
+			/* Change is only permitted while the system is off */
+			return EC_ERROR_INVAL;
+
+		/*
+		 * Current setting is no charge port but the AP is on, so the
+		 * charge manager is out of sync (probably because we're
+		 * reinitializing after sysjump). Reject requests that aren't
+		 * in sync with our outputs.
+		 */
+		bj_active = !gpio_get_level(GPIO_EN_PPVAR_BJ_ADP_L);
+		bj_requested = port == CHARGE_PORT_BARRELJACK;
+		if (bj_active != bj_requested)
+			return EC_ERROR_INVAL;
+	}
+
+	CPRINTS("New charger p%d", port);
+
+	switch (port) {
+	case CHARGE_PORT_TYPEC0:
+	case CHARGE_PORT_TYPEC1:
+		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 1);
+		break;
+	case CHARGE_PORT_BARRELJACK:
+		/* Make sure BJ adapter is sourcing power */
+		if (gpio_get_level(GPIO_BJ_ADP_PRESENT_ODL))
+			return EC_ERROR_INVAL;
+		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 0);
+		break;
+	default:
+		return EC_ERROR_INVAL;
+	}
+
+	return EC_SUCCESS;
+}
+
+static uint8_t usbc_overcurrent;
+
+/******************************************************************************/
+/*
+ * Barrel jack power supply handling
+ *
+ * EN_PPVAR_BJ_ADP_L must default active to ensure we can power on when the
+ * barrel jack is connected, and the USB-C port can bring the EC up fine in
+ * dead-battery mode. Both the USB-C and barrel jack switches do reverse
+ * protection, so we're safe to turn one on then the other off- but we should
+ * only do that if the system is off since it might still brown out.
+ */
+
+#define ADP_DEBOUNCE_MS 1000 /* Debounce time for BJ plug/unplug */
+/* Debounced connection state of the barrel jack */
+static int8_t adp_connected = -1;
+static void adp_connect_deferred(void)
+{
+	struct charge_port_info pi = { 0 };
+	int connected = !gpio_get_level(GPIO_BJ_ADP_PRESENT_ODL);
+
+	/* Debounce */
+	if (connected == adp_connected)
+		return;
+	if (connected)
+		ec_bj_power(&pi.voltage, &pi.current);
+
+	charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED,
+				     DEDICATED_CHARGE_PORT, &pi);
+	adp_connected = connected;
+}
+DECLARE_DEFERRED(adp_connect_deferred);
+
+/* IRQ for BJ plug/unplug. It shouldn't be called if BJ is the power source. */
+void adp_connect_interrupt(enum gpio_signal signal)
+{
+	hook_call_deferred(&adp_connect_deferred_data, ADP_DEBOUNCE_MS * MSEC);
+}
+
+static void adp_state_init(void)
+{
+	ASSERT(CHARGE_PORT_ENUM_COUNT == CHARGE_PORT_COUNT);
+	/*
+	 * Initialize all charge suppliers to 0. The charge manager waits until
+	 * all ports have reported in before doing anything.
+	 */
+	for (int i = 0; i < CHARGE_PORT_COUNT; i++) {
+		for (int j = 0; j < CHARGE_SUPPLIER_COUNT; j++)
+			charge_manager_update_charge(j, i, NULL);
+	}
+
+	/* Report charge state from the barrel jack. */
+	adp_connect_deferred();
+}
+DECLARE_HOOK(HOOK_INIT, adp_state_init, HOOK_PRIO_INIT_CHARGE_MANAGER + 1);
+
+static void board_init(void)
+{
+	int i;
+
+	gpio_enable_interrupt(GPIO_BJ_ADP_PRESENT_ODL);
+	gpio_enable_interrupt(GPIO_HDMI_CONN_OC_ODL);
+	gpio_enable_interrupt(GPIO_USB_A1_OC_ODL);
+	gpio_enable_interrupt(GPIO_USB_A2_OC_ODL);
+	gpio_enable_interrupt(GPIO_USB_A3_OC_ODL);
+	gpio_enable_interrupt(GPIO_USB_A4_OC_ODL);
+
+	if (ec_cfg_power_on_monitor() == POWER_ON_MONITOR_ENABLE) {
+		/*
+		 * Only enable interrupt when fw_config set it as enable.
+		 */
+		gpio_enable_interrupt(GPIO_HDMI1_MONITOR_ON);
+		gpio_enable_interrupt(GPIO_HDMI2_MONITOR_ON);
+		gpio_enable_interrupt(GPIO_OPTION_MONITOR_ON);
+
+		/*
+		 * Initialize the monitor state to corresponding gpio state.
+		 */
+		for (i = 0; i < MONITOR_COUNT; i++)
+			monitors[i].state = gpio_get_level(monitors[i].gpio);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+void board_overcurrent_event(int port, int is_overcurrented)
+{
+	/* Check that port number is valid. */
+	if ((port < 0) || (port >= CONFIG_USB_PD_PORT_MAX_COUNT))
+		return;
+	usbc_overcurrent = is_overcurrented;
+}
+/*
+ * Power monitoring and management.
+ *
+ * the power budgets are met without letting the system fall into
+ * power deficit (perhaps causing a brownout).
+ *
+ * There are 2 power budgets that need to be managed:
+ * The overall goal is to gracefully manage the power demand so that
+ *  - overall system power as measured on the main power supply rail.
+ *  - 5V power delivered to the USB and HDMI ports.
+ *
+ * The actual system power demand is calculated from the VBUS voltage and
+ * the input current (read from a shunt), averaged over 5 readings.
+ * The power budget limit is from the charge manager.
+ *
+ * The 5V power cannot be read directly. Instead, we rely on overcurrent
+ * inputs from the USB and HDMI ports to indicate that the port is in use
+ * (and drawing maximum power).
+ *
+ * There are 3 throttles that can be applied (in priority order):
+ *
+ *  - Type A BC1.2 front port restriction (3W)
+ *  - Type A BC1.2 rear port restriction (3W)
+ *  - Type C PD (throttle to 1.5A if sourcing)
+ *  - Turn on PROCHOT, which immediately throttles the CPU.
+ *
+ *  The first 3 throttles affect both the system power and the 5V rails.
+ *  The third is a last resort to force an immediate CPU throttle to
+ *  reduce the overall power use.
+ *
+ *  The strategy is to determine what the state of the throttles should be,
+ *  and to then turn throttles off or on as needed to match this.
+ *
+ *  This function runs on demand, or every 2 ms when the CPU is up,
+ *  and continually monitors the power usage, applying the
+ *  throttles when necessary.
+ *
+ *  All measurements are in milliwatts.
+ */
+#define THROT_TYPE_A_FRONT BIT(0)
+#define THROT_TYPE_A_REAR BIT(1)
+#define THROT_TYPE_C0 BIT(2)
+#define THROT_TYPE_C1 BIT(3)
+#define THROT_PROCHOT BIT(5)
+
+/*
+ * Power gain if front USB A ports are limited.
+ */
+#define POWER_GAIN_TYPE_A 3200
+/*
+ * Power gain if Type C port is limited.
+ */
+#define POWER_GAIN_TYPE_C 8800
+/*
+ * Power is averaged over 10 ms, with a reading every 2 ms.
+ */
+#define POWER_DELAY_MS 2
+#define POWER_READINGS (10 / POWER_DELAY_MS)
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+static void power_monitor(void)
+{
+	static uint32_t current_state;
+	static uint32_t history[POWER_READINGS];
+	static uint8_t index;
+	int32_t delay;
+	uint32_t new_state = 0, diff;
+
+	/*
+	 * If CPU is off or suspended, no need to throttle
+	 * or restrict power.
+	 */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF | CHIPSET_STATE_SUSPEND)) {
+		/*
+		 * Slow down monitoring, assume no throttling required.
+		 */
+		delay = 20 * MSEC;
+		/*
+		 * Clear the first entry of the power table so that
+		 * it is re-initilalised when the CPU starts.
+		 */
+		history[0] = 0;
+	} else {
+		int32_t charger_mw;
+
+		delay = POWER_DELAY_MS * MSEC;
+		/*
+		 * Get current charger limit (in mw).
+		 * If not configured yet, skip.
+		 */
+		charger_mw = charge_manager_get_power_limit_uw() / 1000;
+		if (charger_mw != 0) {
+			int32_t gap, total, max, power;
+			int i;
+
+			/*
+			 * Read power usage.
+			 */
+			power = (adc_read_channel(ADC_VBUS) *
+				 adc_read_channel(ADC_PPVAR_IMON)) /
+				1000;
+			/* Init power table */
+			if (history[0] == 0) {
+				for (i = 0; i < POWER_READINGS; i++)
+					history[i] = power;
+			}
+			/*
+			 * Update the power readings and
+			 * calculate the average and max.
+			 */
+			history[index] = power;
+			index = (index + 1) % POWER_READINGS;
+			total = 0;
+			max = history[0];
+			for (i = 0; i < POWER_READINGS; i++) {
+				total += history[i];
+				if (history[i] > max)
+					max = history[i];
+			}
+			/*
+			 * For Type-C power supplies, there is
+			 * less tolerance for exceeding the rating,
+			 * so use the max power that has been measured
+			 * over the measuring period.
+			 * For barrel-jack supplies, the rating can be
+			 * exceeded briefly, so use the average.
+			 */
+			if (charge_manager_get_supplier() == CHARGE_SUPPLIER_PD)
+				power = max;
+			else
+				power = total / POWER_READINGS;
+			/*
+			 * Calculate gap, and if negative, power
+			 * demand is exceeding configured power budget, so
+			 * throttling is required to reduce the demand.
+			 */
+			gap = charger_mw - power;
+			/*
+			 * Limiting type-A power rear ports.
+			 */
+			if (gap <= 0) {
+				new_state |= THROT_TYPE_A_REAR;
+				if (!(current_state & THROT_TYPE_A_REAR))
+					gap += POWER_GAIN_TYPE_A;
+			}
+			/*
+			 * Limiting type-A power front ports.
+			 */
+			if (gap <= 0) {
+				new_state |= THROT_TYPE_A_FRONT;
+				if (!(current_state & THROT_TYPE_A_FRONT))
+					gap += POWER_GAIN_TYPE_A;
+			}
+			/*
+			 * If the type-C port is sourcing power,
+			 * check whether it should be throttled.
+			 */
+			if (ppc_is_sourcing_vbus(0) && gap <= 0) {
+				new_state |= THROT_TYPE_C0;
+				if (!(current_state & THROT_TYPE_C0))
+					gap += POWER_GAIN_TYPE_C;
+			}
+			/*
+			 * If the type-C port is sourcing power,
+			 * check whether it should be throttled.
+			 */
+			if (ppc_is_sourcing_vbus(1) && gap <= 0) {
+				new_state |= THROT_TYPE_C1;
+				if (!(current_state & THROT_TYPE_C1))
+					gap += POWER_GAIN_TYPE_C;
+			}
+			/*
+			 * As a last resort, turn on PROCHOT to
+			 * throttle the CPU.
+			 */
+			if (gap <= 0)
+				new_state |= THROT_PROCHOT;
+		}
+	}
+	/*
+	 * Turn the throttles on or off if they have changed.
+	 */
+	diff = new_state ^ current_state;
+	current_state = new_state;
+	if (diff & THROT_PROCHOT) {
+		int prochot = (new_state & THROT_PROCHOT) ? 0 : 1;
+
+		gpio_set_level(GPIO_EC_PROCHOT_ODL, prochot);
+	}
+	if (diff & THROT_TYPE_C0) {
+		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C0) ?
+						TYPEC_RP_1A5 :
+						TYPEC_RP_3A0;
+
+		ppc_set_vbus_source_current_limit(0, rp);
+		tcpm_select_rp_value(0, rp);
+		pd_update_contract(0);
+	}
+	if (diff & THROT_TYPE_C1) {
+		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C1) ?
+						TYPEC_RP_1A5 :
+						TYPEC_RP_3A0;
+
+		ppc_set_vbus_source_current_limit(1, rp);
+		tcpm_select_rp_value(1, rp);
+		pd_update_contract(1);
+	}
+	if (diff & THROT_TYPE_A_REAR) {
+		int typea_bc = (new_state & THROT_TYPE_A_REAR) ? 1 : 0;
+
+		gpio_set_level(GPIO_USB_A_LOW_PWR1_OD, typea_bc);
+	}
+	if (diff & THROT_TYPE_A_FRONT) {
+		int typea_bc = (new_state & THROT_TYPE_A_FRONT) ? 1 : 0;
+
+		gpio_set_level(GPIO_USB_A_LOW_PWR2_OD, typea_bc);
+	}
+	hook_call_deferred(&power_monitor_data, delay);
+}
+/*
+ * Start power monitoring after ADCs have been initialised.
+ */
+DECLARE_HOOK(HOOK_INIT, power_monitor, HOOK_PRIO_INIT_ADC + 1);
+
+/******************************************************************************/
+/*
+ * System power on and wake up by monitor power button.
+ *
+ * After pressing power button of monitor for power on, monitor will send power
+ * on signal with 3.3V / 200ms to DT. If DT detect that pulse, there are three
+ * DT behavior:
+ *
+ *  - Do nothing in state S0.
+ *  - Wake up from state S0ix.
+ *  - Power on from state S5 and G3.
+ */
+
+/* Debounce time for HDMI power button press */
+#define MONITOR_DEBOUNCE_MS 100
+
+static void monitor_irq_deferred(void);
+DECLARE_DEFERRED(monitor_irq_deferred);
+
+static void monitor_irq_deferred(void)
+{
+	int i;
+
+	for (i = 0; i < MONITOR_COUNT; i++) {
+		if (monitors[i].state && gpio_get_level(monitors[i].gpio)) {
+			/*
+			 * System power on from state S5 and G3.
+			 */
+			if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+				chipset_power_on();
+			/*
+			 * System wake up from state S0ix.
+			 */
+			else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
+				power_button_simulate_press(200);
+		}
+		monitors[i].state = MONITOR_OFF;
+	}
+}
+
+/* Power on by HDMI/ DP monitor. */
+void monitor_interrupt(enum gpio_signal signal)
+{
+	/*
+	 * Power on by HDMI/ DP monitor only works
+	 * when system is not in S0.
+	 */
+	if (chipset_in_state(CHIPSET_STATE_ON))
+		return;
+
+	if (ec_cfg_power_on_monitor() == POWER_ON_MONITOR_ENABLE) {
+		switch (signal) {
+		case GPIO_HDMI1_MONITOR_ON:
+			monitors[HDMI1_MONITOR].state = MONITOR_ON;
+			break;
+		case GPIO_HDMI2_MONITOR_ON:
+			monitors[HDMI2_MONITOR].state = MONITOR_ON;
+			break;
+		case GPIO_OPTION_MONITOR_ON:
+			monitors[OPTION_MONITOR].state = MONITOR_ON;
+			break;
+		default:
+			break;
+		}
+		hook_call_deferred(&monitor_irq_deferred_data,
+				   MONITOR_DEBOUNCE_MS * MSEC);
+	}
+}
diff --git a/board/moli/board.h b/board/moli/board.h
new file mode 100644
index 0000000000..9f4003ccfe
--- /dev/null
+++ b/board/moli/board.h
@@ -0,0 +1,201 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Brask board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "compile_time_macros.h"
+
+/* Baseboard features */
+#include "baseboard.h"
+
+#define CONFIG_MP2964
+
+/* Barrel Jack */
+#define DEDICATED_CHARGE_PORT 2
+
+/* HDMI CEC */
+#define CONFIG_CEC
+#define CONFIG_CEC_BITBANG
+#define CEC_GPIO_OUT GPIO_HDMI_CEC_OUT
+#define CEC_GPIO_IN GPIO_HDMI_CEC_IN
+#define CEC_GPIO_PULL_UP GPIO_HDMI_CEC_PULL_UP
+
+/* USB Type A Features */
+#define USB_PORT_COUNT 4
+#define CONFIG_USB_PORT_POWER_DUMB
+
+/* USB Type C and USB PD defines */
+#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
+
+#define CONFIG_IO_EXPANDER
+#define CONFIG_IO_EXPANDER_NCT38XX
+#define CONFIG_IO_EXPANDER_PORT_COUNT 2
+
+#define CONFIG_USB_PD_PPC
+#define CONFIG_USBC_RETIMER_INTEL_BB
+
+#undef CONFIG_CMD_POWERINDEBUG
+
+#define CONFIG_USBC_PPC_SYV682X
+#undef CONFIG_SYV682X_HV_ILIM
+#define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_5_50
+
+/* TODO: b/177608416 - measure and check these values on brya */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
+
+/* The design should support up to 100W. */
+/* TODO(b/197702356): Set the max PD to 60W now and change it
+ * to 100W after we verify it.
+ */
+#define PD_OPERATING_POWER_MW CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
+#define PD_MAX_POWER_MW 100000
+#define PD_MAX_CURRENT_MA 5000
+#define PD_MAX_VOLTAGE_MV 20000
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
+
+/*
+ * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
+ * signal.
+ */
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
+#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_ODL
+#define GPIO_RECOVERY_L_2 GPIO_GSC_EC_RECOVERY_BTN_ODL
+
+/* I2C Bus Configuration */
+
+#define I2C_PORT_USB_C0_C1_TCPC NPCX_I2C_PORT1_0
+
+#define I2C_PORT_USB_C0_C1_PPC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_A0_A1_MIX NPCX_I2C_PORT6_1
+
+#define I2C_PORT_USB_C0_C1_BC12 NPCX_I2C_PORT2_0
+
+#define I2C_PORT_USB_C0_C1_MUX NPCX_I2C_PORT3_0
+
+#define I2C_PORT_QI NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+
+#define I2C_ADDR_MP2964_FLAGS 0x20
+
+#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x56
+#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x57
+
+/* Enabling Thunderbolt-compatible mode */
+#define CONFIG_USB_PD_TBT_COMPAT_MODE
+
+/* Enabling USB4 mode */
+#define CONFIG_USB_PD_USB4
+#define CONFIG_USB_PD_DATA_RESET_MSG
+
+/* Retimer */
+#define CONFIG_USBC_RETIMER_FW_UPDATE
+
+/* Thermal features */
+#define CONFIG_THERMISTOR
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_TEMP_SENSOR_POWER
+#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
+
+/* ADC */
+#define CONFIG_ADC
+
+/* Fan */
+#define CONFIG_FANS FAN_CH_COUNT
+#define RPM_DEVIATION 1
+#define CONFIG_CUSTOM_FAN_CONTROL
+
+/* Include math_util for bitmask_uint64 used in pd_timers */
+#define CONFIG_MATH_UTIL
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h" /* needed by registers.h */
+#include "registers.h"
+#include "usbc_config.h"
+
+enum charge_port {
+	CHARGE_PORT_TYPEC0,
+	CHARGE_PORT_TYPEC1,
+	CHARGE_PORT_BARRELJACK,
+	CHARGE_PORT_ENUM_COUNT
+};
+
+enum adc_channel {
+	ADC_TEMP_SENSOR_1_SSD,
+	ADC_TEMP_SENSOR_2_CPU_VR,
+	ADC_TEMP_SENSOR_4_DIMM,
+	ADC_VBUS,
+	ADC_PPVAR_IMON, /* ADC3 */
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1_SSD,
+	TEMP_SENSOR_2_CPU_VR,
+	TEMP_SENSOR_4_DIMM,
+	TEMP_SENSOR_COUNT
+};
+
+enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_C1_NCT38XX, IOEX_PORT_COUNT };
+
+enum pwm_channel {
+	PWM_CH_LED_AMBER, /* PWM0 */
+	PWM_CH_FAN, /* PWM5 */
+	PWM_CH_LED_BLUE, /* PWM2 */
+	PWM_CH_COUNT
+};
+
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT };
+
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT };
+
+enum monitor_port {
+	HDMI1_MONITOR,
+	HDMI2_MONITOR,
+	OPTION_MONITOR,
+	MONITOR_COUNT
+};
+
+enum monitor_state { MONITOR_OFF, MONITOR_ON };
+
+enum cec_port { CEC_PORT_0, CEC_PORT_COUNT };
+
+extern void adp_connect_interrupt(enum gpio_signal signal);
+extern void monitor_interrupt(enum gpio_signal signal);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/moli/build.mk b/board/moli/build.mk
new file mode 100644
index 0000000000..4ddfaaf181
--- /dev/null
+++ b/board/moli/build.mk
@@ -0,0 +1,23 @@
+# -*- makefile -*-
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Brask board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx9
+CHIP_VARIANT:=npcx9m3f
+BASEBOARD:=brask
+
+board-y=
+board-y+=board.o
+board-y+=fans.o
+board-y+=i2c.o
+board-y+=led.o
+board-y+=pwm.o
+board-y+=sensors.o
+board-y+=thermal.o
+board-y+=usbc_config.o
+board-y+=fw_config.o
diff --git a/board/moli/ec.tasklist b/board/moli/ec.tasklist
new file mode 100644
index 0000000000..2fda1cfb5e
--- /dev/null
+++ b/board/moli/ec.tasklist
@@ -0,0 +1,25 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ *
+ * USB_CHG_Px tasks must be contiguous (see USB_CHG_PORT_TO_TASK_ID(x)).
+ * PD_Cx tasks must be contiguous (see PD_PORT_TO_TASK_ID(x))
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_shared_alert_task, (BIT(1) | BIT(0)), LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CEC, cec_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/moli/fans.c b/board/moli/fans.c
new file mode 100644
index 0000000000..88eb45935e
--- /dev/null
+++ b/board/moli/fans.c
@@ -0,0 +1,44 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Physical fans. These are logically separate from pwm_channels. */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "fan.h"
+#include "fan_chip.h"
+#include "hooks.h"
+#include "pwm.h"
+
+/* MFT channels. These are logically separate from pwm_channels. */
+const struct mft_t mft_channels[] = {
+	[MFT_CH_0] = {
+		.module = NPCX_MFT_MODULE_2,
+		.clk_src = TCKC_LFCLK,
+		.pwm_id = PWM_CH_FAN,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
+
+static const struct fan_conf fan_conf_0 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
+	.pgood_gpio = -1,
+	.enable_gpio = GPIO_EN_PP5000_FAN,
+};
+
+static const struct fan_rpm fan_rpm_0 = {
+	.rpm_min = 1500,
+	.rpm_start = 1500,
+	.rpm_max = 5200,
+};
+
+const struct fan_t fans[FAN_CH_COUNT] = {
+	[FAN_CH_0] = {
+		.conf = &fan_conf_0,
+		.rpm = &fan_rpm_0,
+	},
+};
diff --git a/board/moli/fw_config.c b/board/moli/fw_config.c
new file mode 100644
index 0000000000..5807ee9111
--- /dev/null
+++ b/board/moli/fw_config.c
@@ -0,0 +1,73 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "fw_config.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+static union moli_cbi_fw_config fw_config;
+BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
+
+/*
+ * FW_CONFIG defaults for moli if the CBI.FW_CONFIG data is not
+ * initialized.
+ */
+static const union moli_cbi_fw_config fw_config_defaults = {
+	.bj_power = BJ_90W,
+	.po_mon = POWER_ON_MONITOR_ENABLE,
+};
+
+/*
+ * Barrel-jack power adapter ratings.
+ */
+static const struct {
+	int voltage;
+	int current;
+} bj_power[] = {
+	[BJ_90W] = { /* 0 - 90W (also default) */
+	  .voltage = 19000,
+	  .current = 4740 },
+	[BJ_135W] = { /* 1 - 135W */
+	  .voltage = 19500,
+	  .current = 6920 },
+};
+
+/****************************************************************************
+ * Moli FW_CONFIG access
+ */
+void board_init_fw_config(void)
+{
+	if (cbi_get_fw_config(&fw_config.raw_value)) {
+		CPRINTS("CBI: Read FW_CONFIG failed, using board defaults");
+		fw_config = fw_config_defaults;
+	}
+}
+
+union moli_cbi_fw_config get_fw_config(void)
+{
+	return fw_config;
+}
+
+void ec_bj_power(uint32_t *voltage, uint32_t *current)
+{
+	unsigned int bj;
+
+	bj = fw_config.bj_power;
+	/* Out of range value defaults to 0 */
+	if (bj >= ARRAY_SIZE(bj_power))
+		bj = 0;
+	*voltage = bj_power[bj].voltage;
+	*current = bj_power[bj].current;
+}
+
+enum ec_cfg_power_on_monitor ec_cfg_power_on_monitor(void)
+{
+	return fw_config.po_mon;
+}
diff --git a/board/moli/fw_config.h b/board/moli/fw_config.h
new file mode 100644
index 0000000000..ee3dcd274d
--- /dev/null
+++ b/board/moli/fw_config.h
@@ -0,0 +1,53 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __BOARD_MOLI_FW_CONFIG_H_
+#define __BOARD_MOLI_FW_CONFIG_H_
+
+#include <stdint.h>
+
+/****************************************************************************
+ * CBI FW_CONFIG layout for Moli board.
+ *
+ * Source of truth is the project/brask/moli/config.star configuration file.
+ */
+
+enum ec_cfg_bj_power { BJ_90W = 0, BJ_135W = 1 };
+
+enum ec_cfg_power_on_monitor {
+	POWER_ON_MONITOR_ENABLE = 0,
+	POWER_ON_MONITOR_DISABLE = 1
+};
+
+union moli_cbi_fw_config {
+	struct {
+		uint32_t bj_power : 2;
+		uint32_t mlb_usb_tbt : 2;
+		uint32_t storage : 2;
+		uint32_t audio : 1;
+		enum ec_cfg_power_on_monitor po_mon : 1;
+		uint32_t reserved_1 : 24;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Read the cached FW_CONFIG.  Guaranteed to have valid values.
+ *
+ * @return the FW_CONFIG for the board.
+ */
+union moli_cbi_fw_config get_fw_config(void);
+
+/**
+ * Get the barrel-jack power from FW_CONFIG.
+ */
+void ec_bj_power(uint32_t *voltage, uint32_t *current);
+
+/**
+ * Get enable/disable power on by monitor from FW_CONFIG.
+ */
+enum ec_cfg_power_on_monitor ec_cfg_power_on_monitor(void);
+
+#endif /* __BOARD_MOLI_FW_CONFIG_H_ */
diff --git a/board/moli/gpio.inc b/board/moli/gpio.inc
new file mode 100644
index 0000000000..e8473f8c95
--- /dev/null
+++ b/board/moli/gpio.inc
@@ -0,0 +1,177 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* INTERRUPT GPIOs: */
+GPIO_INT(ACOK_OD,                    PIN(0, 0), GPIO_INT_BOTH, extpower_interrupt)
+GPIO_INT(EC_PROCHOT_IN_L,            PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
+GPIO_INT(EC_WP_ODL,                  PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(GSC_EC_PWR_BTN_ODL,         PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
+GPIO_INT(SEQ_EC_ALL_SYS_PG,          PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_DSW_PWROK,           PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_RSMRST_ODL,          PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,                   PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,                  PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SYS_SLP_S0IX_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(USB_C0_BC12_INT_ODL,        PIN(C, 6), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C0_C1_TCPC_INT_ODL,     PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C0_PPC_INT_ODL,         PIN(6, 2), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C0_RT_INT_ODL,          PIN(B, 1), GPIO_INT_FALLING, retimer_interrupt)
+GPIO_INT(BJ_ADP_PRESENT_ODL,         PIN(8, 2), GPIO_INT_BOTH | GPIO_PULL_UP, adp_connect_interrupt)
+GPIO_INT(EC_RECOVERY_BTN_ODL,        PIN(2, 3), GPIO_INT_BOTH, button_interrupt)
+GPIO_INT(USB_C1_RT_INT_ODL,          PIN(4, 1), GPIO_INT_FALLING, retimer_interrupt)
+GPIO_INT(USB_C1_BC12_INT_ODL,        PIN(8, 3), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C1_PPC_INT_ODL,         PIN(7, 0), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(HDMI1_MONITOR_ON,           PIN(B, 4), GPIO_INT_RISING, monitor_interrupt)
+GPIO_INT(HDMI2_MONITOR_ON,           PIN(B, 5), GPIO_INT_RISING, monitor_interrupt)
+GPIO_INT(OPTION_MONITOR_ON,          PIN(1, 0), GPIO_INT_RISING, monitor_interrupt)
+
+/* CCD */
+GPIO(CCD_MODE_ODL,                   PIN(E, 5), GPIO_INPUT)
+
+/* Security */
+GPIO(EC_ENTERING_RW,                 PIN(0, 3), GPIO_OUT_LOW)
+GPIO(EC_GSC_PACKET_MODE,             PIN(7, 5), GPIO_OUT_LOW)
+
+/* Fan */
+GPIO(EN_PP5000_FAN,                  PIN(6, 1), GPIO_OUT_HIGH)
+
+/* ADC, need to check the usage */
+GPIO(ANALOG_PPVAR_PWR_IN_IMON_EC,    PIN(4, 2), GPIO_INPUT)
+
+/* BarrelJack */
+GPIO(EN_PPVAR_BJ_ADP_L,              PIN(0, 7), GPIO_OUT_LOW)
+
+/* Chipset PCH */
+GPIO(EC_PCHHOT_ODL,                  PIN(7, 4), GPIO_INPUT)
+GPIO(EC_PCH_INT_ODL,                 PIN(B, 0), GPIO_ODR_HIGH)
+GPIO(EC_PCH_RSMRST_L,                PIN(A, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_RTCRST,                  PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_SYS_PWROK,               PIN(3, 7), GPIO_OUT_LOW)
+GPIO(EC_PCH_WAKE_ODL,                PIN(C, 0), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_ODL,                 PIN(6, 3), GPIO_ODR_HIGH)
+GPIO(EN_S5_RAILS,                    PIN(B, 6), GPIO_OUT_LOW)
+GPIO(PCH_PWROK,                      PIN(7, 2), GPIO_OUT_LOW)
+GPIO(SYS_RST_ODL,                    PIN(C, 5), GPIO_ODR_HIGH)
+GPIO(VCCST_PWRGD_OD,                 PIN(A, 4), GPIO_ODR_LOW)
+GPIO(IMVP9_VRRDY_OD,                 PIN(6, 0), GPIO_INPUT)
+GPIO(CPU_C10_GATE_L,                 PIN(6, 7), GPIO_INPUT)
+
+/* Button */
+GPIO(EC_PCH_PWR_BTN_ODL,             PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(GSC_EC_RECOVERY_BTN_ODL,        PIN(2, 2), GPIO_INPUT)
+
+/* NFC */
+/* TODO(b/194068530): Enable NFC */
+GPIO(NFC_COIL_ACT_L,                 PIN(D, 4), GPIO_INPUT)
+GPIO(NFC_LOW_POWER_MODE,             PIN(9, 5), GPIO_OUT_HIGH)
+GPIO(NFC_CARD_DET_L,                 PIN(A, 3), GPIO_INPUT)
+GPIO(EN_NFC_BUZZER,                  PIN(0, 5), GPIO_OUT_LOW)
+
+/* Wireless Charger */
+/* TODO(b/191418683): Implement Qi Driver */
+GPIO(EC_QI_PWR,                      PIN(D, 2), GPIO_OUT_HIGH)
+GPIO(EC_I2C_QI_RESET_L,              PIN(9, 3), GPIO_OUT_HIGH)
+GPIO(EC_I2C_QI_INT_ODL,              PIN(9, 6), GPIO_INPUT)
+
+/* HDMI */
+GPIO(HDMI_CONN_OC_ODL,               PIN(2, 4), GPIO_INPUT)
+
+/* HDMI CEC */
+/* TODO(b/197474873): Enable HDMI CEC */
+GPIO(HDMI_CEC_IN,                    PIN(4, 0), GPIO_INPUT)
+GPIO(HDMI_CEC_OUT,                   PIN(D, 3), GPIO_OUT_HIGH | GPIO_OPEN_DRAIN)
+GPIO(HDMI_CEC_PULL_UP,               PIN(C, 2), GPIO_OUT_HIGH)
+
+/* I2C SCL/SDA */
+GPIO(EC_I2C_QI_SCL,                  PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_QI_SDA,                  PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SCL,                PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SDA,                PIN(B, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C1_PPC_BC_SCL,    PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C1_PPC_BC_SDA,    PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C1_RT_SCL,        PIN(D, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C1_RT_SDA,        PIN(D, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C1_TCPC_SCL,      PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C1_TCPC_SDA,      PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_USB_A0_A1_MIX_SCL,       PIN(E, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_A0_A1_MIX_SDA,       PIN(E, 3), GPIO_INPUT)
+
+/* USBA */
+GPIO(EN_PP5000_USBA,                 PIN(D, 7), GPIO_OUT_LOW)
+GPIO(USB_A1_STATUS_L,                PIN(2, 0), GPIO_INPUT)
+GPIO(USB_A2_STATUS_L,                PIN(1, 7), GPIO_INPUT)
+GPIO(USB_A_LOW_PWR1_OD,              PIN(1, 4), GPIO_OUT_LOW)
+GPIO(USB_A_LOW_PWR2_OD,              PIN(1, 1), GPIO_OUT_LOW)
+GPIO(USB_A_OC_SOC_L,                 PIN(8, 0), GPIO_OUT_HIGH)
+GPIO(USB_A1_OC_ODL,                  PIN(3, 0), GPIO_INPUT)
+GPIO(USB_A2_OC_ODL,                  PIN(2, 7), GPIO_INPUT)
+GPIO(USB_A3_OC_ODL,                  PIN(2, 6), GPIO_INPUT)
+GPIO(USB_A4_OC_ODL,                  PIN(0, 6), GPIO_INPUT)
+
+/* USBC */
+GPIO(USB_C0_C1_TCPC_RST_ODL,         PIN(F, 5), GPIO_ODR_LOW)
+
+/* LAN */
+GPIO(LAN_PWR_GOOD,                   PIN(0, 2), GPIO_INPUT)
+
+/* LED */
+GPIO(LED_ORANGE_CONTROL,             PIN(3, 1), GPIO_ODR_LOW)
+GPIO(LED_BLUE_CONTROL,               PIN(2, 5), GPIO_ODR_LOW)
+
+/* Option Board */
+GPIO(HDMI1_MONON_SIO,                PIN(1, 6), GPIO_INPUT)
+GPIO(HDMI2_MONON_SIO,                PIN(1, 5), GPIO_INPUT)
+GPIO(OPTION_MONON_SIO,               PIN(2, 1), GPIO_INPUT)
+
+IOEX(USB_C0_OC_ODL,          EXPIN(IOEX_C0_NCT38XX, 0, 4), GPIO_ODR_HIGH)
+IOEX(USB_C0_FRS_EN,          EXPIN(IOEX_C0_NCT38XX, 0, 6), GPIO_LOW)
+IOEX(USB_C0_RT_RST_ODL,      EXPIN(IOEX_C0_NCT38XX, 0, 7), GPIO_ODR_LOW)
+
+IOEX(USB_C1_OC_ODL,          EXPIN(IOEX_C1_NCT38XX, 0, 4), GPIO_ODR_HIGH)
+IOEX(USB_C1_RT_RST_ODL,      EXPIN(IOEX_C1_NCT38XX, 0, 2), GPIO_ODR_LOW)
+IOEX(USB_C1_FRS_EN,          EXPIN(IOEX_C1_NCT38XX, 0, 6), GPIO_LOW)
+
+/* UART alternate functions */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)              /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */
+
+/* I2C alternate functions */
+ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)               /* GPIO33/I2C5_SCL0/CTS_L, GPIO36/RTS_L/I2C5_SDA0 */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)               /* GPIO87/I2C1_SDA0 */
+ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)               /* GPIO92/I2C2_SCL0, GPIO91/I2C2_SDA0, GPIO90/I2C1_SCL0 */
+ALTERNATE(PIN_MASK(B, 0x0c), 0, MODULE_I2C, 0)               /* GPIOB3/I2C7_SCL0/DCD_L, GPIOB2/I2C7_SDA0/DSR_L */
+ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)               /* GPIOD1/I2C3_SCL0, GPIOD0/I2C3_SDA0 */
+ALTERNATE(PIN_MASK(E, 0x18), 0, MODULE_I2C, 0)               /* GPIOE4/I2C6_SCL1/I3C_SCL, GPIOE3/I2C6_SDA1/I3C_SDA */
+
+/* PWM alternate functions */
+ALTERNATE(PIN_MASK(7, 0x08), 0, MODULE_PWM, 0)               /* GPIO73/TA2 */
+ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)               /* GPIOB7/PWM5 */
+ALTERNATE(PIN_MASK(C, 0x18), 0, MODULE_PWM, 0)               /* GPIOC4/PWM2, GPIOC3/PWM0 */
+
+/* ADC alternate functions */
+ALTERNATE(PIN_MASK(4, 0x38), 0, MODULE_ADC, 0)               /* GPIO45/ADC0, GPIO44/ADC1, GPIO43/ADC2 */
+ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0)               /* GPIOE1/ADC7 */
+
+/* Unused Pins */
+UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
+UNUSED(PIN(3, 2))       /* GPO32/TRIS_L */
+UNUSED(PIN(3, 5))       /* GPO35/CR_SOUT4/TEST_L */
+UNUSED(PIN(6, 6))       /* GPIO66 */
+UNUSED(PIN(8, 1))       /* GPIO81/PECI_DATA */
+UNUSED(PIN(5, 6))       /* GPIO56/CLKRUN# */
+UNUSED(PIN(9, 7))       /* GPIO97 */
+UNUSED(PIN(8, 6))       /* GPIO86/TXD/CR_SOUT2/FLPRG2_L */
+UNUSED(PIN(1, 3))       /* KSO06/GPO13/GP_SEL# */
+UNUSED(PIN(1, 2))       /* KSO07/GPO12/JEN# */
+UNUSED(PIN(0, 4))       /* KSO13/GPIO04 */
+UNUSED(PIN(A, 2))       /* F_SCLK/GPIOA2 */
+UNUSED(PIN(5, 0))       /* GPIO50 */
+UNUSED(PIN(9, 4))       /* GPIO94 */
+UNUSED(PIN(A, 0))       /* F_CS0_L/GPIOA0 */
+UNUSED(PIN(3, 4))       /* GPIO34/PS2_DAT2/ADC6 */
+UNUSED(PIN(F, 3))       /* GPIOF3/I2C4_SCL1 */
+UNUSED(PIN(F, 2))       /* GPIOF2/I2C4_SDA1 */
+UNUSED(PIN(A, 7))       /* GPIOA7/PS2_DAT3/TB2/F_DIO3 */
diff --git a/board/moli/i2c.c b/board/moli/i2c.c
new file mode 100644
index 0000000000..472eb35424
--- /dev/null
+++ b/board/moli/i2c.c
@@ -0,0 +1,61 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "i2c.h"
+
+/* I2C port map configuration */
+const struct i2c_port_t i2c_ports[] = {
+	{
+		/* I2C1 */
+		.name = "tcpc0,1",
+		.port = I2C_PORT_USB_C0_C1_TCPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C1_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C1_TCPC_SDA,
+	},
+	{
+		/* I2C2 */
+		.name = "ppc0,1",
+		.port = I2C_PORT_USB_C0_C1_PPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C1_PPC_BC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C1_PPC_BC_SDA,
+	},
+	{
+		/* I2C3 */
+		.name = "retimer0,1",
+		.port = I2C_PORT_USB_C0_C1_MUX,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C1_RT_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C1_RT_SDA,
+	},
+	{
+		/* I2C5 */
+		.name = "wireless_charger",
+		.port = I2C_PORT_QI,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_QI_SCL,
+		.sda = GPIO_EC_I2C_QI_SDA,
+	},
+	{
+		/* I2C6 */
+		.name = "usba_mix0,1",
+		.port = I2C_PORT_USB_A0_A1_MIX,
+		.kbps = 100,
+		.scl = GPIO_EC_I2C_USB_A0_A1_MIX_SCL,
+		.sda = GPIO_EC_I2C_USB_A0_A1_MIX_SDA,
+	},
+	{
+		/* I2C7 */
+		.name = "eeprom",
+		.port = I2C_PORT_EEPROM,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_MISC_SCL,
+		.sda = GPIO_EC_I2C_MISC_SDA,
+	},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/board/moli/led.c b/board/moli/led.c
new file mode 100644
index 0000000000..edb429e530
--- /dev/null
+++ b/board/moli/led.c
@@ -0,0 +1,281 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power LED control for Brask.
+ * Solid green - active power
+ * Green flashing - suspended
+ * Red flashing - alert
+ * Solid red - critical
+ */
+
+#include "chipset.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "led_common.h"
+#include "pwm.h"
+#include "timer.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
+
+/*
+ * Due to the CSME-Lite processing, upon startup the CPU transitions through
+ * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so
+ * delay turning off the LED during suspend/shutdown.
+ */
+#define LED_CPU_DELAY_MS (2000 * MSEC)
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED };
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+enum led_color {
+	LED_OFF = 0,
+	LED_BLUE,
+	LED_AMBER,
+
+	/* Number of colors, not a color itself */
+	LED_COLOR_COUNT
+};
+
+static int set_color_power(enum led_color color, int duty)
+{
+	int amber = 0;
+	int blue = 0;
+
+	if (duty < 0 || 100 < duty)
+		return EC_ERROR_UNKNOWN;
+
+	switch (color) {
+	case LED_OFF:
+		break;
+	case LED_AMBER:
+		amber = 1;
+		break;
+	case LED_BLUE:
+		blue = 1;
+		break;
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+
+	if (blue && duty) {
+		gpio_set_level(GPIO_LED_BLUE_CONTROL, 1);
+		pwm_set_duty(PWM_CH_LED_BLUE, duty);
+	} else {
+		gpio_set_level(GPIO_LED_BLUE_CONTROL, 0);
+		pwm_set_duty(PWM_CH_LED_BLUE, 0);
+	}
+
+	if (amber && duty) {
+		gpio_set_level(GPIO_LED_ORANGE_CONTROL, 1);
+		pwm_set_duty(PWM_CH_LED_AMBER, duty);
+	} else {
+		gpio_set_level(GPIO_LED_ORANGE_CONTROL, 0);
+		pwm_set_duty(PWM_CH_LED_AMBER, 0);
+	}
+
+	return EC_SUCCESS;
+}
+
+static int set_color(enum ec_led_id id, enum led_color color, int duty)
+{
+	switch (id) {
+	case EC_LED_ID_POWER_LED:
+		return set_color_power(color, duty);
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+}
+
+#define LED_PERIOD (4 * SECOND)
+#define LED_DUTY_CYCLE (25)
+#define LED_PULSE_US (LED_PERIOD * LED_DUTY_CYCLE / 100 / 2)
+/* 10 msec for nice and smooth transition. */
+#define LED_PULSE_TICK_US (10 * MSEC)
+
+/*
+ * When pulsing is enabled, brightness is incremented by <duty_inc> every
+ * <interval> usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented
+ * likewise in LED_PULSE_US usec.
+ */
+static struct {
+	uint32_t interval;
+	int duty_inc;
+	enum led_color color;
+	int duty;
+	uint32_t time_off;
+} led_pulse;
+
+/*
+ * LED_PERIOD = time_on + time_off;
+ * time_on = LED_PULSE_US * 2;
+ * time_off = LED_PERIOD - LED_PULSE_US * 2;
+ */
+#define CONFIG_TICK(interval, period, color)                       \
+	config_tick((interval), 100 / (LED_PULSE_US / (interval)), \
+		    LED_PERIOD - LED_PULSE_US * 2, (color))
+
+static void config_tick(uint32_t interval, int duty_inc, int time_off,
+			enum led_color color)
+{
+	led_pulse.interval = interval;
+	led_pulse.duty_inc = duty_inc;
+	led_pulse.color = color;
+	led_pulse.duty = 0;
+	led_pulse.time_off = time_off;
+}
+
+static void pulse_power_led(enum led_color color)
+{
+	set_color(EC_LED_ID_POWER_LED, color, led_pulse.duty);
+	if (led_pulse.duty + led_pulse.duty_inc > 100)
+		led_pulse.duty_inc = led_pulse.duty_inc * -1;
+	else if (led_pulse.duty + led_pulse.duty_inc < 0)
+		led_pulse.duty_inc = led_pulse.duty_inc * -1;
+	led_pulse.duty += led_pulse.duty_inc;
+}
+
+static void led_tick(void);
+DECLARE_DEFERRED(led_tick);
+static void led_tick(void)
+{
+	uint32_t elapsed;
+	uint32_t next = 0;
+	uint32_t start = get_time().le.lo;
+
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		pulse_power_led(led_pulse.color);
+	elapsed = get_time().le.lo - start;
+	next = led_pulse.interval > elapsed ? led_pulse.interval - elapsed : 0;
+	next = (led_pulse.duty - led_pulse.duty_inc) ?
+		       next :
+		       next + led_pulse.time_off;
+	hook_call_deferred(&led_tick_data, next);
+}
+
+static void led_suspend(void)
+{
+	CONFIG_TICK(LED_PULSE_TICK_US, LED_PERIOD, LED_BLUE);
+	led_tick();
+}
+DECLARE_DEFERRED(led_suspend);
+
+static void led_shutdown(void)
+{
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_OFF, 0);
+}
+DECLARE_DEFERRED(led_shutdown);
+
+static void led_shutdown_hook(void)
+{
+	hook_call_deferred(&led_tick_data, -1);
+	hook_call_deferred(&led_suspend_data, -1);
+	hook_call_deferred(&led_shutdown_data, LED_CPU_DELAY_MS);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, led_shutdown_hook, HOOK_PRIO_DEFAULT);
+
+static void led_suspend_hook(void)
+{
+	hook_call_deferred(&led_shutdown_data, -1);
+	hook_call_deferred(&led_suspend_data, LED_CPU_DELAY_MS);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, led_suspend_hook, HOOK_PRIO_DEFAULT);
+
+static void led_resume(void)
+{
+	/*
+	 * Assume there is no race condition with led_tick, which also
+	 * runs in hook_task.
+	 */
+	hook_call_deferred(&led_tick_data, -1);
+	/*
+	 * Avoid invoking the suspend/shutdown delayed hooks.
+	 */
+	hook_call_deferred(&led_suspend_data, -1);
+	hook_call_deferred(&led_shutdown_data, -1);
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_BLUE, 100);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, led_resume, HOOK_PRIO_DEFAULT);
+
+void led_alert(int enable)
+{
+	if (enable) {
+		/* Overwrite the current signal */
+		config_tick(1 * SECOND, 100, 0, LED_AMBER);
+		led_tick();
+	} else {
+		/* Restore the previous signal */
+		if (chipset_in_state(CHIPSET_STATE_ON))
+			led_resume();
+		else if (chipset_in_state(CHIPSET_STATE_SUSPEND))
+			led_suspend_hook();
+		else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+			led_shutdown_hook();
+	}
+}
+
+void show_critical_error(void)
+{
+	hook_call_deferred(&led_tick_data, -1);
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_AMBER, 100);
+}
+
+static int command_led(int argc, const char **argv)
+{
+	enum ec_led_id id = EC_LED_ID_POWER_LED;
+
+	if (argc < 2)
+		return EC_ERROR_PARAM_COUNT;
+
+	if (!strcasecmp(argv[1], "debug")) {
+		led_auto_control(id, !led_auto_control_is_enabled(id));
+		ccprintf("o%s\n", led_auto_control_is_enabled(id) ? "ff" : "n");
+	} else if (!strcasecmp(argv[1], "off")) {
+		set_color(id, LED_OFF, 0);
+	} else if (!strcasecmp(argv[1], "blue")) {
+		set_color(id, LED_BLUE, 100);
+	} else if (!strcasecmp(argv[1], "amber")) {
+		set_color(id, LED_AMBER, 100);
+	} else if (!strcasecmp(argv[1], "alert")) {
+		led_alert(1);
+	} else if (!strcasecmp(argv[1], "crit")) {
+		show_critical_error();
+	} else {
+		return EC_ERROR_PARAM1;
+	}
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(led, command_led, "[debug|blue|amber|off|alert|crit]",
+			"Turn on/off LED.");
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	brightness_range[EC_LED_COLOR_AMBER] = 100;
+	brightness_range[EC_LED_COLOR_BLUE] = 100;
+}
+
+int led_set_brightness(enum ec_led_id id, const uint8_t *brightness)
+{
+	if (brightness[EC_LED_COLOR_BLUE])
+		return set_color(id, LED_BLUE, brightness[EC_LED_COLOR_BLUE]);
+	else if (brightness[EC_LED_COLOR_AMBER])
+		return set_color(id, LED_AMBER, brightness[EC_LED_COLOR_AMBER]);
+	else
+		return set_color(id, LED_OFF, 0);
+}
+
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
+{
+	/* Blink alert if insufficient power per system_can_boot_ap(). */
+	int insufficient_power =
+		(charge_ma * charge_mv) <
+		(CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON * 1000);
+	led_alert(insufficient_power);
+}
diff --git a/board/moli/pwm.c b/board/moli/pwm.c
new file mode 100644
index 0000000000..405dcddcae
--- /dev/null
+++ b/board/moli/pwm.c
@@ -0,0 +1,33 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "hooks.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_LED_AMBER] = { .channel = 0,
+			       .flags = PWM_CONFIG_ACTIVE_LOW |
+					PWM_CONFIG_DSLEEP,
+			       .freq = 2000 },
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
+	[PWM_CH_LED_BLUE] = { .channel = 2,
+			      .flags = PWM_CONFIG_ACTIVE_LOW |
+				       PWM_CONFIG_DSLEEP,
+			      .freq = 2000 },
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+static void board_pwm_init(void)
+{
+	pwm_enable(PWM_CH_FAN, 1);
+	pwm_enable(PWM_CH_LED_BLUE, 1);
+	pwm_enable(PWM_CH_LED_AMBER, 1);
+}
+DECLARE_HOOK(HOOK_INIT, board_pwm_init, HOOK_PRIO_DEFAULT);
diff --git a/board/moli/sensors.c b/board/moli/sensors.c
new file mode 100644
index 0000000000..2ad327617e
--- /dev/null
+++ b/board/moli/sensors.c
@@ -0,0 +1,102 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc_chip.h"
+#include "common.h"
+#include "hooks.h"
+#include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
+#include "thermal.h"
+
+/* ADC configuration */
+const struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_1_SSD] = {
+		.name = "TEMP_SSD",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_2_CPU_VR] = {
+		.name = "TEMP_CPU_VR",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_4_DIMM] = {
+		.name = "TEMP_DIMM",
+		.input_ch = NPCX_ADC_CH7,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_VBUS] = {  /* 5/39 voltage divider */
+		.name = "VBUS",
+		.input_ch = NPCX_ADC_CH2,
+		.factor_mul = ADC_MAX_VOLT * 39,
+		.factor_div = (ADC_READ_MAX + 1) * 5,
+	},
+	[ADC_PPVAR_IMON] = {  /* 20/(20+8.66)*50/200 current divider */
+		.name = "PPVAR_IMON",
+		.input_ch = NPCX_ADC_CH3,
+		.factor_mul = ADC_MAX_VOLT * 1433,
+		.factor_div = (ADC_READ_MAX + 1) * 250,
+	},
+
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* Temperature sensor configuration */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1_SSD] = { .name = "SSD",
+				.type = TEMP_SENSOR_TYPE_BOARD,
+				.read = get_temp_3v3_30k9_47k_4050b,
+				.idx = ADC_TEMP_SENSOR_1_SSD },
+	[TEMP_SENSOR_2_CPU_VR] = { .name = "CPU VR",
+				   .type = TEMP_SENSOR_TYPE_BOARD,
+				   .read = get_temp_3v3_30k9_47k_4050b,
+				   .idx = ADC_TEMP_SENSOR_2_CPU_VR },
+	[TEMP_SENSOR_4_DIMM] = { .name = "DIMM",
+				 .type = TEMP_SENSOR_TYPE_BOARD,
+				 .read = get_temp_3v3_30k9_47k_4050b,
+				 .idx = ADC_TEMP_SENSOR_4_DIMM },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+#define THERMAL_SSD                                         \
+	{                                                   \
+		.temp_host = {                              \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(64), \
+		},                                          \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_ssd = THERMAL_SSD;
+
+#define THERMAL_CPU                                          \
+	{                                                    \
+		.temp_host = {                               \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(100), \
+		},                                           \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
+
+#define THERMAL_DIMM                                        \
+	{                                                   \
+		.temp_host = {                              \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(67), \
+		},                                          \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_dimm =
+	THERMAL_DIMM;
+/*
+ * TODO(b/197478860): add the thermal sensor setting
+ */
+/* this should really be "const" */
+struct ec_thermal_config thermal_params[] = {
+	[TEMP_SENSOR_1_SSD] = THERMAL_SSD,
+	[TEMP_SENSOR_2_CPU_VR] = THERMAL_CPU,
+	[TEMP_SENSOR_4_DIMM] = THERMAL_DIMM,
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
diff --git a/board/moli/thermal.c b/board/moli/thermal.c
new file mode 100644
index 0000000000..16aaa5c069
--- /dev/null
+++ b/board/moli/thermal.c
@@ -0,0 +1,143 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "fan.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "temp_sensor.h"
+#include "thermal.h"
+#include "util.h"
+/* Console output macros */
+#define CPUTS(outstr) cputs(CC_THERMAL, outstr)
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
+
+struct fan_step {
+	/*
+	 * Sensor 1~4 trigger point, set -1 if we're not using this
+	 * sensor to determine fan speed.
+	 */
+	int8_t on[TEMP_SENSOR_COUNT];
+	/*
+	 * Sensor 1~4 trigger point, set -1 if we're not using this
+	 * sensor to determine fan speed.
+	 */
+	int8_t off[TEMP_SENSOR_COUNT];
+	/* Fan rpm */
+	uint16_t rpm[FAN_CH_COUNT];
+};
+
+static const struct fan_step fan_table[] = {
+	{
+		/* level 0 */
+		.on = { -1, 47, -1 },
+		.off = { -1, 0, -1 },
+		.rpm = { 1900 },
+	},
+	{
+		/* level 1 */
+		.on = { -1, 50, -1 },
+		.off = { -1, 47, -1 },
+		.rpm = { 2400 },
+	},
+	{
+		/* level 2 */
+		.on = { -1, 60, -1 },
+		.off = { -1, 57, -1 },
+		.rpm = { 3000 },
+	},
+	{
+		/* level 3 */
+		.on = { -1, 64, -1 },
+		.off = { -1, 61, -1 },
+		.rpm = { 3700 },
+	},
+	{
+		/* level 4 */
+		.on = { -1, 67, -1 },
+		.off = { -1, 64, -1 },
+		.rpm = { 4400 },
+	},
+	{
+		/* level 5 */
+		.on = { -1, 70, -1 },
+		.off = { -1, 67, -1 },
+		.rpm = { 5000 },
+	},
+};
+const int num_fan_levels = ARRAY_SIZE(fan_table);
+
+int fan_table_to_rpm(int fan, int *temp, enum temp_sensor_id temp_sensor)
+{
+	/* current fan level */
+	static int current_level;
+	/* previous fan level */
+	static int prev_current_level;
+	/* previous sensor temperature */
+	static int prev_temp[TEMP_SENSOR_COUNT];
+	int i;
+	int new_rpm = 0;
+
+	/*
+	 * Compare the current and previous temperature, we have
+	 * the three paths :
+	 *  1. decreasing path. (check the release point)
+	 *  2. increasing path. (check the trigger point)
+	 *  3. invariant path. (return the current RPM)
+	 */
+	if (temp[temp_sensor] < prev_temp[temp_sensor]) {
+		for (i = current_level; i > 0; i--) {
+			if (temp[temp_sensor] < fan_table[i].off[temp_sensor])
+				current_level = i - 1;
+			else
+				break;
+		}
+	} else if (temp[temp_sensor] > prev_temp[temp_sensor]) {
+		for (i = current_level; i < num_fan_levels; i++) {
+			if (temp[temp_sensor] >= fan_table[i].on[temp_sensor])
+				current_level = i;
+			else
+				break;
+		}
+	}
+	if (current_level < 0)
+		current_level = 0;
+	if (current_level >= num_fan_levels)
+		current_level = num_fan_levels - 1;
+
+	if (current_level != prev_current_level) {
+		CPRINTS("temp: %d, prev_temp: %d", temp[temp_sensor],
+			prev_temp[temp_sensor]);
+		CPRINTS("current_level: %d", current_level);
+	}
+
+	prev_temp[temp_sensor] = temp[temp_sensor];
+	prev_current_level = current_level;
+
+	switch (fan) {
+	case FAN_CH_0:
+		new_rpm = fan_table[current_level].rpm[FAN_CH_0];
+		break;
+	default:
+		break;
+	}
+	return new_rpm;
+}
+
+void board_override_fan_control(int fan, int *temp)
+{
+	if (chipset_in_state(CHIPSET_STATE_ON)) {
+		fan_set_rpm_mode(FAN_CH(fan), 1);
+		fan_set_rpm_target(FAN_CH(fan),
+				   fan_table_to_rpm(FAN_CH(fan), temp,
+						    TEMP_SENSOR_2_CPU_VR));
+	} else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
+		/* Stop fan when enter S0ix */
+		fan_set_rpm_mode(FAN_CH(fan), 1);
+		fan_set_rpm_target(FAN_CH(fan), 0);
+	}
+}
diff --git a/board/moli/usbc_config.c b/board/moli/usbc_config.c
new file mode 100644
index 0000000000..1c2f7eccf8
--- /dev/null
+++ b/board/moli/usbc_config.c
@@ -0,0 +1,345 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/bc12/pi3usb9201_public.h"
+#include "driver/ppc/syv682x_public.h"
+#include "driver/retimer/bb_retimer_public.h"
+#include "driver/tcpm/nct38xx.h"
+#include "driver/tcpm/tcpci.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "ioexpander.h"
+#include "system.h"
+#include "task.h"
+#include "task_id.h"
+#include "timer.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+/* USBC TCPC configuration */
+const struct tcpc_config_t tcpc_config[] = {
+	[USBC_PORT_C0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0_C1_TCPC,
+			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_NO_DEBUG_ACC_CONTROL,
+	},
+	[USBC_PORT_C1] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0_C1_TCPC,
+			.addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
+BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
+
+/* USBC PPC configuration */
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_C1_PPC,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.drv = &syv682x_drv,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C0_C1_PPC,
+		.i2c_addr_flags = SYV682X_ADDR2_FLAGS,
+		.drv = &syv682x_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
+
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/* USBC mux configuration - Alder Lake includes internal mux */
+static const struct usb_mux_chain usbc0_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+
+static const struct usb_mux_chain usbc1_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+
+const struct usb_mux_chain usb_muxes[] = {
+	[USBC_PORT_C0] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C0_C1_MUX,
+			.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc0_tcss_usb_mux,
+	},
+	[USBC_PORT_C1] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C0_C1_MUX,
+			.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc1_tcss_usb_mux,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
+
+/* BC1.2 charger detect configuration */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_C1_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C0_C1_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_1_FLAGS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
+
+/*
+ * USB C0 and C2 uses burnside bridge chips and have their reset
+ * controlled by their respective TCPC chips acting as GPIO expanders.
+ *
+ * ioex_init() is normally called before we take the TCPCs out of
+ * reset, so we need to start in disabled mode, then explicitly
+ * call ioex_init().
+ */
+
+struct ioexpander_config_t ioex_config[] = {
+	[IOEX_C0_NCT38XX] = {
+		.i2c_host_port = I2C_PORT_USB_C0_C1_TCPC,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
+	},
+	[IOEX_C1_NCT38XX] = {
+		.i2c_host_port = I2C_PORT_USB_C0_C1_TCPC,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT);
+
+__override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
+{
+	enum ioex_signal rst_signal;
+
+	if (me->usb_port == USBC_PORT_C0) {
+		rst_signal = IOEX_USB_C0_RT_RST_ODL;
+	} else if (me->usb_port == USBC_PORT_C1) {
+		rst_signal = IOEX_USB_C1_RT_RST_ODL;
+	} else {
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * We do not have a load switch for the burnside bridge chips,
+	 * so we only need to sequence reset.
+	 */
+
+	if (enable) {
+		/*
+		 * Tpw, minimum time from VCC to RESET_N de-assertion is 100us.
+		 * For boards that don't provide a load switch control, the
+		 * retimer_init() function ensures power is up before calling
+		 * this function.
+		 */
+		ioex_set_level(rst_signal, 1);
+		/*
+		 * Allow 1ms time for the retimer to power up lc_domain
+		 * which powers I2C controller within retimer
+		 */
+		msleep(1);
+	} else {
+		ioex_set_level(rst_signal, 0);
+		msleep(1);
+	}
+	return EC_SUCCESS;
+}
+
+__override int bb_retimer_reset(const struct usb_mux *me)
+{
+	/*
+	 * TODO(b/193402306, b/195375738): Remove this once transition to
+	 * QS Silicon is complete
+	 */
+	bb_retimer_power_enable(me, false);
+	msleep(5);
+	bb_retimer_power_enable(me, true);
+	msleep(25);
+
+	return EC_SUCCESS;
+}
+
+void board_reset_pd_mcu(void)
+{
+	enum gpio_signal tcpc_rst;
+
+	tcpc_rst = GPIO_USB_C0_C1_TCPC_RST_ODL;
+
+	/*
+	 * TODO(b/179648104): figure out correct timing
+	 */
+
+	gpio_set_level(tcpc_rst, 0);
+
+	/*
+	 * delay for power-on to reset-off and min. assertion time
+	 */
+
+	msleep(20);
+
+	gpio_set_level(tcpc_rst, 1);
+
+	/* wait for chips to come up */
+
+	msleep(50);
+}
+
+static void enable_ioex(int ioex)
+{
+	ioex_init(ioex);
+}
+
+static void board_tcpc_init(void)
+{
+	/* Don't reset TCPCs after initial reset */
+	if (!system_jumped_late()) {
+		board_reset_pd_mcu();
+
+		/*
+		 * These IO expander pins are implemented using the
+		 * C0/C1 TCPC, so they must be set up after the TCPC has
+		 * been taken out of reset.
+		 */
+		enable_ioex(IOEX_C0_NCT38XX);
+		enable_ioex(IOEX_C1_NCT38XX);
+	}
+
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_C1_TCPC_INT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (gpio_get_level(GPIO_USB_C0_C1_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_0 | PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
+
+int ppc_get_alert_status(int port)
+{
+	if (port == USBC_PORT_C0)
+		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
+	else if (port == USBC_PORT_C1)
+		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
+	return 0;
+}
+
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_C1_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C0);
+		break;
+	default:
+		break;
+	}
+}
+
+void bc12_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_BC12_INT_ODL:
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+		break;
+	case GPIO_USB_C1_BC12_INT_ODL:
+		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+		break;
+	default:
+		break;
+	}
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C1);
+		break;
+	default:
+		break;
+	}
+}
+
+void retimer_interrupt(enum gpio_signal signal)
+{
+	/*
+	 * TODO(b/179513527): add USB-C support
+	 */
+}
+
+__override bool board_is_dts_port(int port)
+{
+	return port == USBC_PORT_C0;
+}
+
+__override bool board_is_tbt_usb4_port(int port)
+{
+	return true;
+}
+
+__override enum tbt_compat_cable_speed board_get_max_tbt_speed(int port)
+{
+	if (!board_is_tbt_usb4_port(port))
+		return TBT_SS_RES_0;
+
+	return TBT_SS_TBT_GEN3;
+}
diff --git a/board/moli/usbc_config.h b/board/moli/usbc_config.h
new file mode 100644
index 0000000000..219ad9a745
--- /dev/null
+++ b/board/moli/usbc_config.h
@@ -0,0 +1,15 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Brya board-specific USB-C configuration */
+
+#ifndef __CROS_EC_USBC_CONFIG_H
+#define __CROS_EC_USBC_CONFIG_H
+
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
+
+#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/moli/vif_override.xml b/board/moli/vif_override.xml
new file mode 100644
index 0000000000..9fc397cd40
--- /dev/null
+++ b/board/moli/vif_override.xml
@@ -0,0 +1,129 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
+
+<?xml version="1.0" encoding="utf-8"?>
+<vif:VIF xmlns="http://usb.org/VendorInfoFile.xsd">
+  <vif:Product_Revision>2</vif:Product_Revision>
+  <vif:TID>0</vif:TID>
+  <vif:Product>
+    <!--Product Level Content:-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;USB4™ Product-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:USB4_Num_Internal_Host_Controllers value="1" />
+    <vif:USB4_Num_PCIe_DN_Bridges value="0" />
+    <!--Bundle: USB4RouterList-->
+    <vif:USB4RouterList>
+      <vif:Usb4Router>
+        <!--USB4 Router 0-->
+        <vif:USB4_Router_ID value="0" />
+        <vif:USB4_Silicon_VID value="32903">8087</vif:USB4_Silicon_VID>
+        <vif:USB4_Num_Lane_Adapters value="4" />
+        <vif:USB4_Num_USB3_DN_Adapters value="1" />
+        <vif:USB4_Num_DP_IN_Adapters value="1" />
+        <vif:USB4_Num_DP_OUT_Adapters value="0" />
+        <vif:USB4_Num_PCIe_DN_Adapters value="4" />
+        <vif:USB4_TBT3_Not_Supported value="0">TBT3 Compatible</vif:USB4_TBT3_Not_Supported>
+        <vif:USB4_PCIe_Wake_Supported value="true" />
+        <vif:USB4_USB3_Wake_Supported value="false" />
+        <vif:USB4_Num_Unused_Adapters value="0" />
+        <vif:USB4_TBT3_VID value="32903">8087</vif:USB4_TBT3_VID>
+        <vif:USB4_PCIe_Switch_Vendor_ID value="32902">8086</vif:USB4_PCIe_Switch_Vendor_ID>
+        <vif:USB4_PCIe_Switch_Device_ID value="17982">463E</vif:USB4_PCIe_Switch_Device_ID>
+      </vif:Usb4Router>
+    </vif:USB4RouterList>
+  </vif:Product>
+  <vif:Component>
+    <!--Component 0: Port 0-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;USB4™ Port-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:USB4_Lane_0_Adapter value="1" />
+    <vif:USB4_Max_Speed value="1">Gen 3 (40Gb)</vif:USB4_Max_Speed>
+    <vif:USB4_DFP_Supported value="true" />
+    <vif:USB4_UFP_Supported value="false" />
+    <vif:USB4_USB3_Tunneling_Supported value="true" />
+    <vif:USB4_DP_Tunneling_Supported value="true" />
+    <vif:USB4_CL1_State_Supported value="true" />
+    <vif:USB4_CL2_State_Supported value="true" />
+    <vif:USB4_Num_Retimers value="1" />
+    <vif:USB4_DP_Bit_Rate value="3">HBR3</vif:USB4_DP_Bit_Rate>
+    <vif:USB4_Num_DP_Lanes value="4">4 Lanes</vif:USB4_Num_DP_Lanes>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;USB Host-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Host_Speed value="2">USB 3.2 Gen 2x1</vif:Host_Speed>
+    <vif:Host_Contains_Captive_Retimer value="true" />
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:Host_Suspend_Supported value="true" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Source-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:USB_Suspend_May_Be_Cleared value="true" />
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="3">3A @ 5V</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <!--Bundle: SrcPdoList-->
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!--Source PDO 1-->
+        <vif:Src_PD_OCP_OC_Debounce value="50">50 msec</vif:Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="360">3600 mA</vif:Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Dual Role-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:FR_Swap_Supported_As_Initial_Sink value="true" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;SOP Discover ID-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Product_Type_UFP_SOP value="3">PSD</vif:Product_Type_UFP_SOP>
+    <vif:Product_Type_DFP_SOP value="2">PDUSB Host</vif:Product_Type_DFP_SOP>
+  </vif:Component>
+  <vif:Component>
+    <!--Component 1: Port 1-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;USB4™ Port-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:USB4_Lane_0_Adapter value="1" />
+    <vif:USB4_Max_Speed value="1">Gen 3 (40Gb)</vif:USB4_Max_Speed>
+    <vif:USB4_DFP_Supported value="true" />
+    <vif:USB4_UFP_Supported value="false" />
+    <vif:USB4_USB3_Tunneling_Supported value="true" />
+    <vif:USB4_DP_Tunneling_Supported value="true" />
+    <vif:USB4_CL1_State_Supported value="true" />
+    <vif:USB4_CL2_State_Supported value="true" />
+    <vif:USB4_Num_Retimers value="1" />
+    <vif:USB4_DP_Bit_Rate value="3">HBR3</vif:USB4_DP_Bit_Rate>
+    <vif:USB4_Num_DP_Lanes value="4">4 Lanes</vif:USB4_Num_DP_Lanes>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;USB Host-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Host_Speed value="2">USB 3.2 Gen 2x1</vif:Host_Speed>
+    <vif:Host_Contains_Captive_Retimer value="true" />
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:Host_Suspend_Supported value="true" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Source-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:USB_Suspend_May_Be_Cleared value="true" />
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="3">3A @ 5V</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <!--Bundle: SrcPdoList-->
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!--Source PDO 1-->
+        <vif:Src_PD_OCP_OC_Debounce value="50">50 msec</vif:Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="360">3600 mA</vif:Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Dual Role-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:FR_Swap_Supported_As_Initial_Sink value="true" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;SOP Discover ID-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Product_Type_UFP_SOP value="3">PSD</vif:Product_Type_UFP_SOP>
+    <vif:Product_Type_DFP_SOP value="2">PDUSB Host</vif:Product_Type_DFP_SOP>
+  </vif:Component>
+</vif:VIF>
diff --git a/board/moonbuggy/board.c b/board/moonbuggy/board.c
new file mode 100644
index 0000000000..9ee309d2fe
--- /dev/null
+++ b/board/moonbuggy/board.c
@@ -0,0 +1,561 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Puff board-specific configuration */
+
+#include "adc.h"
+#include "button.h"
+#include "chipset.h"
+#include "common.h"
+#include "core/cortex-m/cpu.h"
+#include "cros_board_info.h"
+#include "driver/ina3221.h"
+#include "ec_commands.h"
+#include "extpower.h"
+#include "fan.h"
+#include "fan_chip.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power/cometlake-discrete.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "spi.h"
+#include "switch.h"
+#include "system.h"
+#include "task.h"
+#include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
+#include "thermal.h"
+#include "uart.h"
+#include "usb_common.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+
+static void power_monitor(void);
+DECLARE_DEFERRED(power_monitor);
+
+static uint8_t usbc_overcurrent;
+static int32_t base_5v_power;
+
+/*
+ * Power usage for each port as measured or estimated.
+ * Units are milliwatts (5v x ma current)
+ */
+#define PWR_BASE_LOAD (5 * 1335)
+#define PWR_FRONT_HIGH (5 * 1500)
+#define PWR_FRONT_LOW (5 * 900)
+#define PWR_REAR (5 * 1500)
+#define PWR_HDMI (5 * 562)
+#define PWR_C_HIGH (5 * 3740)
+#define PWR_C_LOW (5 * 2090)
+#define PWR_MAX (5 * 10000)
+
+/*
+ * Update the 5V power usage, assuming no throttling,
+ * and invoke the power monitoring.
+ */
+static void update_5v_usage(void)
+{
+	int front_ports = 0;
+	/*
+	 * Recalculate the 5V load, assuming no throttling.
+	 */
+	base_5v_power = PWR_BASE_LOAD;
+	/*
+	 * Only 1 front port can run higher power at a time.
+	 */
+	if (front_ports > 0)
+		base_5v_power += PWR_FRONT_HIGH - PWR_FRONT_LOW;
+	if (!gpio_get_level(GPIO_USB_A1_OC_ODL))
+		base_5v_power += PWR_REAR;
+	if (!gpio_get_level(GPIO_HDMI_CONN0_OC_ODL))
+		base_5v_power += PWR_HDMI;
+	if (!gpio_get_level(GPIO_HDMI_CONN1_OC_ODL))
+		base_5v_power += PWR_HDMI;
+	if (!gpio_get_level(GPIO_HDMI_CONN2_OC_ODL))
+		base_5v_power += PWR_HDMI;
+	if (usbc_overcurrent)
+		base_5v_power += PWR_C_HIGH;
+	/*
+	 * Invoke the power handler immediately.
+	 */
+	hook_call_deferred(&power_monitor_data, 0);
+}
+DECLARE_DEFERRED(update_5v_usage);
+/*
+ * Start power monitoring after ADCs have been initialised.
+ */
+DECLARE_HOOK(HOOK_INIT, update_5v_usage, HOOK_PRIO_INIT_ADC + 1);
+
+static void port_ocp_interrupt(enum gpio_signal signal)
+{
+	hook_call_deferred(&update_5v_usage_data, 0);
+}
+
+/*
+ * Reverse current protection:
+ * When the board asserts +5Vs_V2_ADP_PRESENT_L active low, the EC needs
+ * to turn off the jack charger by setting EN_AC_JACK_CHARGER_EC_L high.
+ *
+ * When the board asserts BJ_ADP_PRESENT_L active low, the EC needs to
+ * enable the jack charger by setting EN_AC_JACK_CHARGER_EC_L low.
+ */
+static void ads_5v_deferred(void)
+{
+	int ads_5v_enable = !gpio_get_level(GPIO_ADS_5VS_V2_ADP_PRESENT_L);
+
+	if (ads_5v_enable)
+		gpio_set_level(GPIO_EN_AC_JACK_CHARGER_EC_L, 1);
+}
+DECLARE_DEFERRED(ads_5v_deferred);
+
+void ads_5v_interrupt(enum gpio_signal signal)
+{
+	/* ADS 5v control time*/
+	hook_call_deferred(&ads_5v_deferred_data, (5 * MSEC));
+}
+
+/**
+ * Handle debounced ADS 12v handler.
+ */
+static void ads_12v_deferred(void)
+{
+	int ads_12v_enable = !gpio_get_level(GPIO_BJ_ADP_PRESENT_L);
+
+	if (ads_12v_enable)
+		gpio_set_level(GPIO_EN_AC_JACK_CHARGER_EC_L, 0);
+}
+DECLARE_DEFERRED(ads_12v_deferred);
+
+void ads_12v_interrupt(enum gpio_signal signal)
+{
+	/* ADS 12v control time */
+	hook_call_deferred(&ads_12v_deferred_data, (5 * MSEC));
+}
+
+/******************************************************************************/
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/******************************************************************************/
+/* SPI devices */
+const struct spi_device_t spi_devices[] = {};
+const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
+
+/******************************************************************************/
+/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
+	[PWM_CH_LED_RED] = { .channel = 0,
+			     .flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+			     .freq = 2000 },
+	[PWM_CH_LED_WHITE] = { .channel = 2,
+			       .flags = PWM_CONFIG_ACTIVE_LOW |
+					PWM_CONFIG_DSLEEP,
+			       .freq = 2000 },
+};
+
+/******************************************************************************/
+/* I2C port map configuration */
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "ina",
+	  .port = I2C_PORT_INA,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_SCL,
+	  .sda = GPIO_I2C0_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
+	{ .name = "pse",
+	  .port = I2C_PORT_PSE,
+	  .kbps = 400,
+	  .scl = GPIO_I2C4_SCL,
+	  .sda = GPIO_I2C4_SDA },
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 400,
+	  .scl = GPIO_I2C5_SCL,
+	  .sda = GPIO_I2C5_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_I2C7_SCL,
+	  .sda = GPIO_I2C7_SDA },
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+const struct adc_t adc_channels[] = {
+	[ADC_SNS_PP3300] = {
+		/*
+		 * 4700/5631 voltage divider: can take the value out of range
+		 * for 32-bit signed integers, so truncate to 470/563 yielding
+		 * <0.1% error and a maximum intermediate value of 1623457792,
+		 * which comfortably fits in int32.
+		 */
+		.name = "SNS_PP3300",
+		.input_ch = NPCX_ADC_CH2,
+		.factor_mul = ADC_MAX_VOLT * 563,
+		.factor_div = (ADC_READ_MAX + 1) * 470,
+	},
+	[ADC_SNS_PP1050] = {
+		.name = "SNS_PP1050",
+		.input_ch = NPCX_ADC_CH7,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+	},
+	[ADC_VBUS] = {  /* 5/39 voltage divider */
+		.name = "VBUS",
+		.input_ch = NPCX_ADC_CH4,
+		.factor_mul = ADC_MAX_VOLT * 39,
+		.factor_div = (ADC_READ_MAX + 1) * 5,
+	},
+	[ADC_PPVAR_IMON] = {  /* 500 mV/A */
+		.name = "PPVAR_IMON",
+		.input_ch = NPCX_ADC_CH9,
+		.factor_mul = ADC_MAX_VOLT * 2, /* Milliamps */
+		.factor_div = ADC_READ_MAX + 1,
+	},
+	[ADC_TEMP_SENSOR_1] = {
+		.name = "TEMP_SENSOR_1",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_CORE] = {
+		.name = "Core",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_1,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/******************************************************************************/
+/* Wake up pins */
+const enum gpio_signal hibernate_wake_pins[] = {};
+const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
+
+/******************************************************************************/
+/* Physical fans. These are logically separate from pwm_channels. */
+const struct fan_conf fan_conf_0 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
+	.pgood_gpio = -1,
+	.enable_gpio = -1,
+};
+
+const struct fan_rpm fan_rpm_0 = {
+	.rpm_min = 2500,
+	.rpm_start = 2500,
+	.rpm_max = 5300,
+};
+
+const struct fan_t fans[] = {
+	[FAN_CH_0] = { .conf = &fan_conf_0, .rpm = &fan_rpm_0, },
+};
+BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
+
+/******************************************************************************/
+/* MFT channels. These are logically separate from pwm_channels. */
+const struct mft_t mft_channels[] = {
+	[MFT_CH_0] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN },
+};
+BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
+
+/******************************************************************************/
+/* Thermal control; drive fan based on temperature sensors. */
+static const int temp_fan_off = C_TO_K(35);
+static const int temp_fan_max = C_TO_K(55);
+struct ec_thermal_config thermal_params[] = {
+	[TEMP_SENSOR_CORE] = {
+		.temp_host = {
+			[EC_TEMP_THRESH_WARN] = 0,
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(85),
+			[EC_TEMP_THRESH_HALT] = C_TO_K(90),
+		},
+		.temp_host_release = {
+			[EC_TEMP_THRESH_WARN] = 0,
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(78),
+			[EC_TEMP_THRESH_HALT] = 0,
+		},
+		.temp_fan_off = temp_fan_off,
+		.temp_fan_max = temp_fan_max,
+	},
+};
+
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
+
+static const struct fan_step_1_1 fan_table0[] = {
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(35),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(41),
+	  .rpm = 2500 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(40),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(44),
+	  .rpm = 2900 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(42),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(46),
+	  .rpm = 3400 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(44),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(48),
+	  .rpm = 3900 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(46),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(50),
+	  .rpm = 4400 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(48),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(52),
+	  .rpm = 4900 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(50),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(55),
+	  .rpm = 5300 },
+};
+#define NUM_FAN_LEVELS ARRAY_SIZE(fan_table0)
+
+static const struct fan_step_1_1 *fan_table = fan_table0;
+
+int fan_percent_to_rpm(int fan, int temp_ratio)
+{
+	return temp_ratio_to_rpm_hysteresis(fan_table, NUM_FAN_LEVELS, fan,
+					    temp_ratio, NULL);
+}
+
+/* Power sensors */
+const struct ina3221_t ina3221[] = {
+	{ I2C_PORT_INA, 0x40, { "PP3300_G", "PP5000_A", "PP3300_WLAN" } },
+	{ I2C_PORT_INA, 0x42, { "PP3300_A", "PP3300_SSD", "PP3300_LAN" } },
+	{ I2C_PORT_INA, 0x43, { NULL, "PP1200_U", "PP2500_DRAM" } }
+};
+const unsigned int ina3221_count = ARRAY_SIZE(ina3221);
+
+static uint16_t board_version;
+static uint32_t sku_id;
+static uint32_t fw_config;
+
+static void cbi_init(void)
+{
+	/*
+	 * Load board info from CBI to control per-device configuration.
+	 *
+	 * If unset it's safe to treat the board as a proto, just C10 gating
+	 * won't be enabled.
+	 */
+	uint32_t val;
+
+	if (cbi_get_board_version(&val) == EC_SUCCESS && val <= UINT16_MAX)
+		board_version = val;
+	if (cbi_get_sku_id(&val) == EC_SUCCESS)
+		sku_id = val;
+	if (cbi_get_fw_config(&val) == EC_SUCCESS)
+		fw_config = val;
+	CPRINTS("Board Version: %d, SKU ID: 0x%08x, F/W config: 0x%08x",
+		board_version, sku_id, fw_config);
+}
+DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1);
+
+static void board_init(void)
+{
+	uint8_t *memmap_batt_flags;
+
+	/* Override some GPIO interrupt priorities.
+	 *
+	 * These interrupts are timing-critical for AP power sequencing, so we
+	 * increase their NVIC priority from the default of 3. This affects
+	 * whole MIWU groups of 8 GPIOs since they share an IRQ.
+	 *
+	 * Latency at the default priority level can be hundreds of
+	 * microseconds while other equal-priority IRQs are serviced, so GPIOs
+	 * requiring faster response must be higher priority.
+	 */
+	/* CPU_C10_GATE_L on GPIO6.7: must be ~instant for ~60us response. */
+	cpu_set_interrupt_priority(NPCX_IRQ_WKINTH_1, 1);
+	/*
+	 * slp_s3_interrupt (GPIOA.5 on WKINTC_0) must respond within 200us
+	 * (tPLT18); less critical than the C10 gate.
+	 */
+	cpu_set_interrupt_priority(NPCX_IRQ_WKINTC_0, 2);
+
+	/* Always claim AC is online, because we don't have a battery. */
+	memmap_batt_flags = host_get_memmap(EC_MEMMAP_BATT_FLAG);
+	*memmap_batt_flags |= EC_BATT_FLAG_AC_PRESENT;
+	/*
+	 * For board version < 2, the directly connected recovery
+	 * button is not available.
+	 */
+	if (board_version < 2)
+		button_disable_gpio(BUTTON_RECOVERY);
+
+	/* ADS GPIO interrupt enable*/
+	gpio_enable_interrupt(GPIO_ADS_5VS_V2_ADP_PRESENT_L);
+	gpio_enable_interrupt(GPIO_BJ_ADP_PRESENT_L);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+/******************************************************************************/
+/* USB-A port control */
+const int usb_port_enable[USB_PORT_COUNT] = {};
+
+int64_t get_time_dsw_pwrok(void)
+{
+	/* DSW_PWROK is turned on before EC was powered. */
+	return -20 * MSEC;
+}
+
+int extpower_is_present(void)
+{
+	/* genesis: If the EC is running, then there is external power */
+	return 1;
+}
+
+int board_is_c10_gate_enabled(void)
+{
+	return 0;
+}
+
+void board_enable_s0_rails(int enable)
+{
+}
+
+/*
+ * Power monitoring and management.
+ *
+ * The overall goal is to gracefully manage the power demand so that
+ * the power budgets are met without letting the system fall into
+ * power deficit (perhaps causing a brownout).
+ *
+ * There are 2 power budgets that need to be managed:
+ *  - overall system power as measured on the main power supply rail.
+ *  - 5V power delivered to the USB and HDMI ports.
+ *
+ * The actual system power demand is calculated from the VBUS voltage and
+ * the input current (read from a shunt), averaged over 5 readings.
+ * The power budget limit is from the charge manager.
+ *
+ * The 5V power cannot be read directly. Instead, we rely on overcurrent
+ * inputs from the USB and HDMI ports to indicate that the port is in use
+ * (and drawing maximum power).
+ *
+ * There are 3 throttles that can be applied (in priority order):
+ *
+ *  - Type A BC1.2 front port restriction (3W)
+ *  - Type C PD (throttle to 1.5A if sourcing)
+ *  - Turn on PROCHOT, which immediately throttles the CPU.
+ *
+ *  The first 2 throttles affect both the system power and the 5V rails.
+ *  The third is a last resort to force an immediate CPU throttle to
+ *  reduce the overall power use.
+ *
+ *  The strategy is to determine what the state of the throttles should be,
+ *  and to then turn throttles off or on as needed to match this.
+ *
+ *  This function runs on demand, or every 2 ms when the CPU is up,
+ *  and continually monitors the power usage, applying the
+ *  throttles when necessary.
+ *
+ *  All measurements are in milliwatts.
+ */
+#define THROT_TYPE_A BIT(0)
+#define THROT_TYPE_C BIT(1)
+#define THROT_PROCHOT BIT(2)
+
+/*
+ * Power gain if front USB A ports are limited.
+ */
+#define POWER_GAIN_TYPE_A 3200
+/*
+ * Power gain if Type C port is limited.
+ */
+#define POWER_GAIN_TYPE_C 8800
+/*
+ * Power is averaged over 10 ms, with a reading every 2 ms.
+ */
+#define POWER_DELAY_MS 2
+#define POWER_READINGS (10 / POWER_DELAY_MS)
+
+static void power_monitor(void)
+{
+	static uint32_t current_state;
+	int32_t delay;
+	uint32_t new_state = 0, diff;
+	int32_t headroom_5v = PWR_MAX - base_5v_power;
+
+	/*
+	 * If CPU is off or suspended, no need to throttle
+	 * or restrict power.
+	 */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF | CHIPSET_STATE_SUSPEND)) {
+		/*
+		 * Slow down monitoring, assume no throttling required.
+		 */
+		delay = 20 * MSEC;
+	} else {
+		delay = POWER_DELAY_MS * MSEC;
+	}
+	/*
+	 * Check the 5v power usage and if necessary,
+	 * adjust the throttles in priority order.
+	 *
+	 * Either throttle may have already been activated by
+	 * the overall power control.
+	 *
+	 * We rely on the overcurrent detection to inform us
+	 * if the port is in use.
+	 *
+	 *  - If type C not already throttled:
+	 *	* If not overcurrent, prefer to limit type C [1].
+	 *	* If in overcurrentuse:
+	 *		- limit type A first [2]
+	 *		- If necessary, limit type C [3].
+	 *  - If type A not throttled, if necessary limit it [2].
+	 */
+	if (headroom_5v < 0) {
+		/*
+		 * Check whether type C is not throttled,
+		 * and is not overcurrent.
+		 */
+		if (!((new_state & THROT_TYPE_C) || usbc_overcurrent)) {
+			/*
+			 * [1] Type C not in overcurrent, throttle it.
+			 */
+			headroom_5v += PWR_C_HIGH - PWR_C_LOW;
+			new_state |= THROT_TYPE_C;
+		}
+		/*
+		 * [2] If type A not already throttled, and power still
+		 * needed, limit type A.
+		 */
+		/* No front USB A ports on moonbuggy. */
+		/*
+		 * [3] If still under-budget, limit type C.
+		 * No need to check if it is already throttled or not.
+		 */
+		if (headroom_5v < 0)
+			new_state |= THROT_TYPE_C;
+	}
+	/*
+	 * Turn the throttles on or off if they have changed.
+	 */
+	diff = new_state ^ current_state;
+	current_state = new_state;
+	if (diff & THROT_PROCHOT) {
+		int prochot = (new_state & THROT_PROCHOT) ? 0 : 1;
+
+		gpio_set_level(GPIO_EC_PROCHOT_ODL, prochot);
+	}
+	hook_call_deferred(&power_monitor_data, delay);
+}
diff --git a/board/moonbuggy/board.h b/board/moonbuggy/board.h
new file mode 100644
index 0000000000..96e1e60e6e
--- /dev/null
+++ b/board/moonbuggy/board.h
@@ -0,0 +1,230 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Puff board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#undef CONFIG_UART_TX_BUF_SIZE
+#define CONFIG_UART_TX_BUF_SIZE 4096
+
+/* NPCX7 config */
+#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */
+#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */
+
+/* Internal SPI flash on NPCX796FC is 512 kB */
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
+#define CONFIG_SPI_FLASH_REGS
+#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
+
+/* EC Defines */
+#define CONFIG_ADC
+#define CONFIG_BOARD_HAS_RTC_RESET
+#define CONFIG_BOARD_VERSION_CBI
+#define CONFIG_DEDICATED_RECOVERY_BUTTON
+#define CONFIG_DEDICATED_RECOVERY_BUTTON_2
+#define CONFIG_BUTTONS_RUNTIME_CONFIG
+#define CONFIG_BOARD_RESET_AFTER_POWER_ON
+/* TODO: (b/143496253) re-enable CEC */
+/* #define CONFIG_CEC */
+#define CONFIG_CRC8
+#define CONFIG_CBI_EEPROM
+#define CONFIG_EMULATED_SYSRQ
+#undef CONFIG_KEYBOARD_BOOT_KEYS
+#define CONFIG_MKBP_INPUT_DEVICES
+#define CONFIG_MKBP_USE_HOST_EVENT
+#undef CONFIG_KEYBOARD_RUNTIME_KEYS
+#undef CONFIG_HIBERNATE
+#define CONFIG_HOST_INTERFACE_ESPI
+#define CONFIG_LED_COMMON
+#undef CONFIG_LID_SWITCH
+#define CONFIG_LTO
+#define CONFIG_PWM
+#define CONFIG_VBOOT_EFS2
+#define CONFIG_VBOOT_HASH
+#define CONFIG_VSTORE
+#define CONFIG_VSTORE_SLOT_COUNT 1
+#define CONFIG_SHA256
+
+/* EC Commands */
+#define CONFIG_CMD_BUTTON
+/* Include CLI command needed to support CCD testing. */
+#define CONFIG_CMD_CHARGEN
+#undef CONFIG_CMD_FASTCHARGE
+#undef CONFIG_CMD_KEYBOARD
+#define CONFIG_HOSTCMD_PD_CONTROL
+#undef CONFIG_CMD_PWR_AVG
+#define CONFIG_CMD_PPC_DUMP
+#define CONFIG_CMD_TCPC_DUMP
+#ifdef SECTION_IS_RO
+/* Reduce RO size by removing less-relevant commands. */
+#undef CONFIG_CMD_APTHROTTLE
+#undef CONFIG_CMD_CHARGEN
+#undef CONFIG_CMD_HCDEBUG
+#undef CONFIG_CMD_MMAPINFO
+#endif
+
+#undef CONFIG_CONSOLE_CMDHELP
+
+/* Don't generate host command debug by default */
+#undef CONFIG_HOSTCMD_DEBUG_MODE
+#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
+
+/* Enable AP Reset command for TPM with old firmware version to detect it. */
+#define CONFIG_CMD_AP_RESET_LOG
+#define CONFIG_HOSTCMD_AP_RESET
+
+/* Chipset config */
+#define CONFIG_CHIPSET_COMETLAKE_DISCRETE
+/* check */
+#define CONFIG_CHIPSET_CAN_THROTTLE
+#define CONFIG_CHIPSET_RESET_HOOK
+#define CONFIG_CPU_PROCHOT_ACTIVE_LOW
+
+#define CONFIG_POWER_BUTTON
+#define CONFIG_POWER_BUTTON_IGNORE_LID
+#define CONFIG_POWER_BUTTON_X86
+/* Check: */
+#define CONFIG_POWER_BUTTON_INIT_IDLE
+#define CONFIG_POWER_COMMON
+#define CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD 30
+#define CONFIG_DELAY_DSW_PWROK_TO_PWRBTN
+#define CONFIG_POWER_PP5000_CONTROL
+#define CONFIG_POWER_S0IX
+#define CONFIG_POWER_S0IX_FAILURE_DETECTION
+#define CONFIG_POWER_SLEEP_FAILURE_DETECTION
+#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
+#define CONFIG_INA3221
+
+/* Fan and temp. */
+#define CONFIG_FANS 1
+#undef CONFIG_FAN_INIT_SPEED
+#define CONFIG_FAN_INIT_SPEED 0
+#define CONFIG_FAN_RPM_CUSTOM
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_TEMP_SENSOR_POWER
+#define CONFIG_THERMISTOR
+#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
+#define CONFIG_THROTTLE_AP
+
+#define CONFIG_USB_PD_PORT_MAX_COUNT 0
+
+/* USB Type A Features */
+#define CONFIG_USB_PORT_POWER_DUMB
+/* There are five ports, but power enable is ganged across all of them. */
+#define USB_PORT_COUNT 0
+
+/* I2C Bus Configuration */
+#define CONFIG_I2C
+#define CONFIG_I2C_CONTROLLER
+#define I2C_PORT_INA NPCX_I2C_PORT0_0
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT3_0
+#define I2C_PORT_PSE NPCX_I2C_PORT4_1
+#define I2C_PORT_POWER NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+
+#define PP5000_PGOOD_POWER_SIGNAL_MASK POWER_SIGNAL_MASK(PP5000_A_PGOOD)
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum adc_channel {
+	ADC_SNS_PP3300, /* ADC2 */
+	ADC_SNS_PP1050, /* ADC7 */
+	ADC_VBUS, /* ADC4 */
+	ADC_PPVAR_IMON, /* ADC9 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	/* Number of ADC channels */
+	ADC_CH_COUNT
+};
+
+enum pwm_channel {
+	PWM_CH_FAN,
+	PWM_CH_LED_RED,
+	PWM_CH_LED_WHITE,
+	/* Number of PWM channels */
+	PWM_CH_COUNT
+};
+
+enum fan_channel {
+	FAN_CH_0,
+	/* Number of FAN channels */
+	FAN_CH_COUNT
+};
+
+enum mft_channel {
+	MFT_CH_0 = 0,
+	/* Number of MFT channels */
+	MFT_CH_COUNT,
+};
+
+enum temp_sensor_id { TEMP_SENSOR_CORE, TEMP_SENSOR_COUNT };
+
+/* Board specific handlers */
+void led_alert(int enable);
+void show_critical_error(void);
+
+/* Board ADS control handlers */
+void ads_5v_interrupt(enum gpio_signal signal);
+void ads_12v_interrupt(enum gpio_signal signal);
+
+/*
+ * firmware config fields
+ */
+/*
+ * Barrel-jack power (4 bits).
+ */
+#define EC_CFG_BJ_POWER_L 0
+#define EC_CFG_BJ_POWER_H 3
+#define EC_CFG_BJ_POWER_MASK GENMASK(EC_CFG_BJ_POWER_H, EC_CFG_BJ_POWER_L)
+/*
+ * USB Connector 4 not present (1 bit).
+ */
+#define EC_CFG_NO_USB4_L 4
+#define EC_CFG_NO_USB4_H 4
+#define EC_CFG_NO_USB4_MASK GENMASK(EC_CFG_NO_USB4_H, EC_CFG_NO_USB4_L)
+/*
+ * Thermal solution config (3 bits).
+ */
+#define EC_CFG_THERMAL_L 5
+#define EC_CFG_THERMAL_H 7
+#define EC_CFG_THERMAL_MASK GENMASK(EC_CFG_THERMAL_H, EC_CFG_THERMAL_L)
+
+unsigned int ec_config_get_thermal_solution(void);
+
+#endif /* !__ASSEMBLER__ */
+
+/* Pin renaming */
+#define GPIO_WP_L GPIO_EC_WP_ODL
+#define GPIO_PP5000_A_PG_OD GPIO_PG_PP5000_A_OD
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
+#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_ODL
+#define GPIO_RECOVERY_L_2 GPIO_H1_EC_RECOVERY_BTN_ODL
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_EN_ROA_RAILS
+#define GPIO_AC_PRESENT GPIO_BJ_ADP_PRESENT_L
+
+/*
+ * There is no RSMRST input, so alias it to the output. This short-circuits
+ * common_intel_x86_handle_rsmrst.
+ */
+#define GPIO_PG_EC_RSMRST_ODL GPIO_PCH_RSMRST_L
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/moonbuggy/build.mk b/board/moonbuggy/build.mk
new file mode 100644
index 0000000000..aca2a91e5c
--- /dev/null
+++ b/board/moonbuggy/build.mk
@@ -0,0 +1,15 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx7
+CHIP_VARIANT:=npcx7m6fc
+
+board-y=board.o
+board-y+=led.o
+board-y+=pse.o
diff --git a/board/moonbuggy/ec.tasklist b/board/moonbuggy/ec.tasklist
new file mode 100644
index 0000000000..c43d643410
--- /dev/null
+++ b/board/moonbuggy/ec.tasklist
@@ -0,0 +1,15 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 2048) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/moonbuggy/gpio.inc b/board/moonbuggy/gpio.inc
new file mode 100644
index 0000000000..bb914d2254
--- /dev/null
+++ b/board/moonbuggy/gpio.inc
@@ -0,0 +1,176 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Pin names follow the schematic, and are aliased to other names if necessary.
+ * Note: Those with interrupt handlers must be declared first. */
+
+/* Latency on this interrupt is extremely critical, so it comes first to ensure
+ * it gets placed first in gpio_wui_table so gpio_interrupt() needs to do
+ * minimal scanning. */
+GPIO_INT(CPU_C10_GATE_L,       PIN(6, 7), GPIO_INT_BOTH, c10_gate_interrupt)
+
+/* Wake Source interrupts */
+GPIO_INT(EC_WP_ODL,            PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(H1_EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
+
+/* Power sequencing interrupts */
+GPIO_INT(PG_PP5000_A_OD,       PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_PP1800_A_OD,       PIN(3, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_VPRIM_CORE_A_OD,   PIN(2, 3), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_PP1050_A_OD,       PIN(2, 2), GPIO_INT_BOTH, power_signal_interrupt)
+/* EC output, but also interrupt so this can be polled as a power signal */
+GPIO_INT(EC_PCH_RSMRST_L,      PIN(A, 6), GPIO_OUTPUT | GPIO_INT_F_RISING | GPIO_INT_F_FALLING, power_signal_interrupt)
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
+GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
+#endif
+GPIO_INT(PG_PP2500_DRAM_U_OD,  PIN(2, 0), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_PP1200_U_OD,       PIN(2, 1), GPIO_INT_BOTH, power_signal_interrupt)
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, slp_s3_interrupt)
+#endif
+GPIO_INT(PG_PP950_VCCIO_OD,    PIN(1, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(IMVP8_VRRDY_OD,       PIN(1, 6), GPIO_INT_BOTH, power_signal_interrupt)
+
+/*
+ * Directly connected recovery button (not available on some boards).
+ */
+GPIO_INT(EC_RECOVERY_BTN_ODL,  PIN(F, 1), GPIO_INT_BOTH, button_interrupt)
+/*
+ * Recovery button input from H1.
+ */
+GPIO_INT(H1_EC_RECOVERY_BTN_ODL, PIN(2, 4), GPIO_INT_BOTH, button_interrupt)
+GPIO_INT(BJ_ADP_PRESENT_L,       PIN(8, 2), GPIO_INT_FALLING | GPIO_PULL_UP,
+ads_12v_interrupt)
+
+/* Port power control interrupts */
+GPIO_INT(HDMI_CONN0_OC_ODL,    PIN(0, 7), GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(HDMI_CONN1_OC_ODL,    PIN(0, 6), GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(HDMI_CONN2_OC_ODL,    PIN(8, 3), GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(USB_A1_OC_ODL,        PIN(A, 2), GPIO_INT_BOTH, port_ocp_interrupt)
+
+/* PCH/CPU signals */
+GPIO(EC_PCH_PWROK,             PIN(0, 5), GPIO_OUT_LOW)
+GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
+GPIO(EC_PCH_PWR_BTN_ODL,       PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_IN_OD,         PIN(3, 4), GPIO_INPUT)
+GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
+GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
+
+/* ADB Scaler signals */
+GPIO(ADB_WAKEUP_EC,            PIN(B, 1), GPIO_INPUT)
+
+/* Power control outputs */
+GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
+GPIO(EN_PP3300_INA_H1_EC_ODL,  PIN(5, 7), GPIO_ODR_HIGH)
+GPIO(EN_PP1800_A,              PIN(1, 5), GPIO_OUT_LOW)
+GPIO(VCCST_PG_OD,              PIN(1, 4), GPIO_ODR_LOW)
+GPIO(EN_S0_RAILS,              PIN(1, 1), GPIO_OUT_LOW)
+GPIO(EN_ROA_RAILS,             PIN(A, 3), GPIO_OUT_LOW)
+GPIO(EN_PP950_VCCIO,           PIN(1, 0), GPIO_OUT_LOW)
+GPIO(EC_IMVP8_PE,              PIN(A, 7), GPIO_OUT_LOW)
+GPIO(EN_IMVP8_VR,              PIN(F, 4), GPIO_OUT_LOW)
+
+/* Barreljack */
+GPIO(EN_PPVAR_BJ_ADP_L,        PIN(0, 4), GPIO_OUT_LOW)
+
+/* USB type A */
+GPIO(USB_A_LOW_PWR_OD,         PIN(9, 4), GPIO_ODR_LOW)
+
+/* USB type C */
+GPIO(USB_C0_POL_L,             PIN(0, 0), GPIO_INPUT | GPIO_SEL_1P8V) /* USB-C Polarity */
+UNUSED(PIN(7, 2))              /* EN_USB_C0_5V_OUT only works if set unused */
+GPIO(SBU_C0_FAULT_ODL,         PIN(5, 6), GPIO_INPUT)
+
+/* TPU */
+GPIO(PP3300_TPU_EN,            PIN(E, 4), GPIO_OUT_HIGH)
+
+/* PSE controller */
+GPIO(EC_PSE_PWM_INT,           PIN(B, 0), GPIO_INPUT)		/* PSE controller interrupt */
+GPIO(EC_RST_LTC4291_L,         PIN(9, 6), GPIO_OUT_HIGH)	/* PSE controller reset */
+
+/* Misc. */
+GPIO(M2_SSD_PLN,               PIN(A, 0), GPIO_INPUT)
+GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
+GPIO(CCD_MODE_ODL,             PIN(E, 5), GPIO_ODR_HIGH)
+GPIO(PACKET_MODE_EN,           PIN(7, 5), GPIO_OUT_LOW)
+GPIO_INT(ADS_5VS_V2_ADP_PRESENT_L,   PIN(0, 3), GPIO_INT_FALLING | GPIO_PULL_UP,
+ads_5v_interrupt)
+GPIO(EN_AC_JACK_CHARGER_EC_L,        PIN(C, 0), GPIO_OUT_LOW)
+GPIO(LAN_WAKE_ODL_EC,                PIN(8, 0), GPIO_INPUT)       /* LAN_WAKE */
+
+/* HDMI/CEC */
+GPIO(HDMI_CONN0_CEC_IN,        PIN(4, 0), GPIO_INPUT)
+GPIO(HDMI_CONN1_CEC_OUT,       PIN(9, 5), GPIO_ODR_HIGH)
+GPIO(HDMI_CONN1_CEC_IN,        PIN(D, 3), GPIO_INPUT)
+GPIO(HDMI_DATA_EN_DB,          PIN(6, 1), GPIO_OUT_HIGH)
+
+/* I2C pins - Alternate function below configures I2C module on these pins */
+GPIO(I2C0_SCL,                 PIN(B, 5), GPIO_INPUT)           /* EC_I2C_INA_SCL */
+GPIO(I2C0_SDA,                 PIN(B, 4), GPIO_INPUT)           /* EC_I2C_INA_SDA */
+GPIO(I2C3_SCL,                 PIN(D, 1), GPIO_INPUT)           /* EC_I2C_ADB_SCL */
+GPIO(I2C3_SDA,                 PIN(D, 0), GPIO_INPUT)           /* EC_I2C_ADB_SDA */
+GPIO(I2C4_SCL,                 PIN(F, 3), GPIO_INPUT)           /* EC_I2C_LTC_SCL */
+GPIO(I2C4_SDA,                 PIN(F, 2), GPIO_INPUT)           /* EC_I2C_LTC_SDA */
+GPIO(I2C5_SCL,                 PIN(3, 3), GPIO_INPUT)           /* EC_I2C_IMVP8_SCL */
+GPIO(I2C5_SDA,                 PIN(3, 6), GPIO_INPUT)           /* EC_I2C_IMVP8_SDA */
+GPIO(I2C7_SCL,                 PIN(B, 3), GPIO_INPUT)           /* EC_I2C_EEPROM_SCL */
+GPIO(I2C7_SDA,                 PIN(B, 2), GPIO_INPUT)           /* EC_I2C_EEPROM_SDA */
+
+/* Alternate functions GPIO definitions */
+ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, 0)                  /* I2C0 */
+ALTERNATE(PIN_MASK(9, 0x01), 0, MODULE_I2C, 0)                  /* I2C1 SCL */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)                  /* I2C1 SDA */
+ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)                  /* I2C3 */
+ALTERNATE(PIN_MASK(F, 0x0C), 0, MODULE_I2C, 0)                  /* I2C4 */
+ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)                  /* I2C5 */
+ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, 0)                  /* I2C7 */
+
+/* PWM */
+ALTERNATE(PIN_MASK(C, 0x08), 0, MODULE_PWM, 0)                  /* PWM0 - Red Led */
+ALTERNATE(PIN_MASK(C, 0x10), 0, MODULE_PWM, 0)                  /* PWM2 - White Led */
+ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)                  /* PWM5 - Fan 1 */
+ALTERNATE(PIN_MASK(7, 0x08), 0, MODULE_PWM, 0)                  /* TA2 - Fan Tachometer */
+
+/* ADC */
+ALTERNATE(PIN_MASK(4, 0x2A), 0, MODULE_ADC, 0)                  /* ADC0, ADC2, ADC4 */
+ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0)                  /* ADC7 */
+ALTERNATE(PIN_MASK(F, 0x01), 0, MODULE_ADC, 0)                  /* ADC9 */
+
+/* UART */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)                 /* UART from EC to Servo */
+
+/* Unused pins */
+UNUSED(PIN(1, 3))						/* EC_GP_SEL1_ODL */
+UNUSED(PIN(4, 4))						/* ADC1/TEMP_SENSOR_2 */
+UNUSED(PIN(4, 2))						/* ADC3/TEMP_SENSOR_3 */
+UNUSED(PIN(9, 2))						/* K8  NC */
+UNUSED(PIN(9, 1))						/* L8  NC */
+UNUSED(PIN(1, 2))						/* C6  NC */
+UNUSED(PIN(6, 6))						/* H4  NC */
+UNUSED(PIN(8, 1))						/* L6  NC */
+UNUSED(PIN(C, 6))						/* B11 NC */
+UNUSED(PIN(E, 2))						/* B8  NC */
+UNUSED(PIN(8, 5))						/* L7  NC */
+UNUSED(PIN(3, 2))						/* E5  NC */
+UNUSED(PIN(D, 6))						/* F6  NC */
+UNUSED(PIN(3, 5))						/* F5  NC */
+UNUSED(PIN(8, 6))						/* J8  NC */
+UNUSED(PIN(9, 3))						/* M11 NC */
+UNUSED(PIN(C, 7))						/* B9  NC */
+UNUSED(PIN(D, 2))						/* C11 NC */
+UNUSED(PIN(F, 5))						/* E7  NC */
+UNUSED(PIN(5, 0))						/* G4  NC */
+UNUSED(PIN(9, 0))						/* J10 NC */
+UNUSED(PIN(8, 7))						/* M7  NC */
+UNUSED(PIN(6, 2))						/* J2  NC */
+UNUSED(PIN(9, 7))						/* J9  NC */
+UNUSED(PIN(0, 2))						/* D10 NC */
+UNUSED(PIN(C, 2))						/* A12 NC */
diff --git a/board/moonbuggy/led.c b/board/moonbuggy/led.c
new file mode 100644
index 0000000000..cc76c36dce
--- /dev/null
+++ b/board/moonbuggy/led.c
@@ -0,0 +1,263 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power LED control for Puff.
+ * Solid green - active power
+ * Green flashing - suspended
+ * Red flashing - alert
+ * Solid red - critical
+ */
+
+#include "chipset.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "led_common.h"
+#include "pwm.h"
+#include "timer.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
+
+/*
+ * Due to the CSME-Lite processing, upon startup the CPU transitions through
+ * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so
+ * delay turning off the LED during suspend/shutdown.
+ */
+#define LED_CPU_DELAY_MS (2000 * MSEC)
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED };
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+enum led_color {
+	LED_OFF = 0,
+	LED_RED,
+	LED_WHITE,
+
+	/* Number of colors, not a color itself */
+	LED_COLOR_COUNT
+};
+
+static int set_color_power(enum led_color color, int duty)
+{
+	int white = 0;
+	int red = 0;
+
+	if (duty < 0 || 100 < duty)
+		return EC_ERROR_UNKNOWN;
+
+	switch (color) {
+	case LED_OFF:
+		break;
+	case LED_WHITE:
+		white = 1;
+		break;
+	case LED_RED:
+		red = 1;
+		break;
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+
+	if (red)
+		pwm_set_duty(PWM_CH_LED_RED, duty);
+	else
+		pwm_set_duty(PWM_CH_LED_RED, 0);
+
+	if (white)
+		pwm_set_duty(PWM_CH_LED_WHITE, duty);
+	else
+		pwm_set_duty(PWM_CH_LED_WHITE, 0);
+
+	return EC_SUCCESS;
+}
+
+static int set_color(enum ec_led_id id, enum led_color color, int duty)
+{
+	switch (id) {
+	case EC_LED_ID_POWER_LED:
+		return set_color_power(color, duty);
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+}
+
+#define LED_PULSE_US (2 * SECOND)
+/* 40 msec for nice and smooth transition. */
+#define LED_PULSE_TICK_US (40 * MSEC)
+
+/* When pulsing is enabled, brightness is incremented by <duty_inc> every
+ * <interval> usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented
+ * likewise in LED_PULSE_US usec.
+ */
+static struct {
+	uint32_t interval;
+	int duty_inc;
+	enum led_color color;
+	int duty;
+} led_pulse;
+
+#define CONFIG_TICK(interval, color) \
+	config_tick((interval), 100 / (LED_PULSE_US / (interval)), (color))
+
+static void config_tick(uint32_t interval, int duty_inc, enum led_color color)
+{
+	led_pulse.interval = interval;
+	led_pulse.duty_inc = duty_inc;
+	led_pulse.color = color;
+	led_pulse.duty = 0;
+}
+
+static void pulse_power_led(enum led_color color)
+{
+	set_color(EC_LED_ID_POWER_LED, color, led_pulse.duty);
+	if (led_pulse.duty + led_pulse.duty_inc > 100)
+		led_pulse.duty_inc = led_pulse.duty_inc * -1;
+	else if (led_pulse.duty + led_pulse.duty_inc < 0)
+		led_pulse.duty_inc = led_pulse.duty_inc * -1;
+	led_pulse.duty += led_pulse.duty_inc;
+}
+
+static void led_tick(void);
+DECLARE_DEFERRED(led_tick);
+static void led_tick(void)
+{
+	uint32_t elapsed;
+	uint32_t next = 0;
+	uint32_t start = get_time().le.lo;
+
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		pulse_power_led(led_pulse.color);
+	elapsed = get_time().le.lo - start;
+	next = led_pulse.interval > elapsed ? led_pulse.interval - elapsed : 0;
+	hook_call_deferred(&led_tick_data, next);
+}
+
+static void led_suspend(void)
+{
+	CONFIG_TICK(LED_PULSE_TICK_US, LED_WHITE);
+	led_tick();
+}
+DECLARE_DEFERRED(led_suspend);
+
+static void led_shutdown(void)
+{
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_OFF, 0);
+}
+DECLARE_DEFERRED(led_shutdown);
+
+static void led_shutdown_hook(void)
+{
+	hook_call_deferred(&led_tick_data, -1);
+	hook_call_deferred(&led_suspend_data, -1);
+	hook_call_deferred(&led_shutdown_data, LED_CPU_DELAY_MS);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, led_shutdown_hook, HOOK_PRIO_DEFAULT);
+
+static void led_suspend_hook(void)
+{
+	hook_call_deferred(&led_shutdown_data, -1);
+	hook_call_deferred(&led_suspend_data, LED_CPU_DELAY_MS);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, led_suspend_hook, HOOK_PRIO_DEFAULT);
+
+static void led_resume(void)
+{
+	/* Assume there is no race condition with led_tick, which also
+	 * runs in hook_task.
+	 */
+	hook_call_deferred(&led_tick_data, -1);
+	/*
+	 * Avoid invoking the suspend/shutdown delayed hooks.
+	 */
+	hook_call_deferred(&led_suspend_data, -1);
+	hook_call_deferred(&led_shutdown_data, -1);
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_WHITE, 100);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, led_resume, HOOK_PRIO_DEFAULT);
+
+static void led_init(void)
+{
+	pwm_enable(PWM_CH_LED_RED, 1);
+	pwm_enable(PWM_CH_LED_WHITE, 1);
+
+	if (chipset_in_state(CHIPSET_STATE_ON))
+		led_resume();
+	else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
+		led_suspend();
+	else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		led_shutdown();
+}
+DECLARE_HOOK(HOOK_INIT, led_init, HOOK_PRIO_INIT_PWM + 1);
+
+void led_alert(int enable)
+{
+	if (enable) {
+		/* Overwrite the current signal */
+		config_tick(1 * SECOND, 100, LED_RED);
+		led_tick();
+	} else {
+		/* Restore the previous signal */
+		if (chipset_in_state(CHIPSET_STATE_ON))
+			led_resume();
+		else if (chipset_in_state(CHIPSET_STATE_SUSPEND))
+			led_suspend_hook();
+		else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+			led_shutdown_hook();
+	}
+}
+
+void show_critical_error(void)
+{
+	hook_call_deferred(&led_tick_data, -1);
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_RED, 100);
+}
+
+static int command_led(int argc, const char **argv)
+{
+	enum ec_led_id id = EC_LED_ID_POWER_LED;
+
+	if (argc < 2)
+		return EC_ERROR_PARAM_COUNT;
+
+	if (!strcasecmp(argv[1], "debug")) {
+		led_auto_control(id, !led_auto_control_is_enabled(id));
+		ccprintf("o%s\n", led_auto_control_is_enabled(id) ? "ff" : "n");
+	} else if (!strcasecmp(argv[1], "off")) {
+		set_color(id, LED_OFF, 0);
+	} else if (!strcasecmp(argv[1], "red")) {
+		set_color(id, LED_RED, 100);
+	} else if (!strcasecmp(argv[1], "white")) {
+		set_color(id, LED_WHITE, 100);
+	} else if (!strcasecmp(argv[1], "alert")) {
+		led_alert(1);
+	} else if (!strcasecmp(argv[1], "crit")) {
+		show_critical_error();
+	} else {
+		return EC_ERROR_PARAM1;
+	}
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(led, command_led, "[debug|red|white|off|alert|crit]",
+			"Turn on/off LED.");
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	brightness_range[EC_LED_COLOR_RED] = 100;
+	brightness_range[EC_LED_COLOR_WHITE] = 100;
+}
+
+int led_set_brightness(enum ec_led_id id, const uint8_t *brightness)
+{
+	if (brightness[EC_LED_COLOR_RED])
+		return set_color(id, LED_RED, brightness[EC_LED_COLOR_RED]);
+	else if (brightness[EC_LED_COLOR_WHITE])
+		return set_color(id, LED_WHITE, brightness[EC_LED_COLOR_WHITE]);
+	else
+		return set_color(id, LED_OFF, 0);
+}
diff --git a/board/moonbuggy/pse.c b/board/moonbuggy/pse.c
new file mode 100644
index 0000000000..c309db887a
--- /dev/null
+++ b/board/moonbuggy/pse.c
@@ -0,0 +1,264 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * The LTC4291 is a power over ethernet (PoE) power sourcing equipment (PSE)
+ * controller.
+ */
+
+#include "common.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "i2c.h"
+#include "string.h"
+#include "timer.h"
+#include "util.h"
+
+#define LTC4291_I2C_ADDR 0x2C
+
+#define LTC4291_REG_SUPEVN_COR 0x0B
+#define LTC4291_REG_STATPWR 0x10
+#define LTC4291_REG_STATPIN 0x11
+#define LTC4291_REG_OPMD 0x12
+#define LTC4291_REG_DISENA 0x13
+#define LTC4291_REG_DETENA 0x14
+#define LTC4291_REG_DETPB 0x18
+#define LTC4291_REG_PWRPB 0x19
+#define LTC4291_REG_RSTPB 0x1A
+#define LTC4291_REG_ID 0x1B
+#define LTC4291_REG_DEVID 0x43
+#define LTC4291_REG_HPMD1 0x46
+#define LTC4291_REG_HPMD2 0x4B
+#define LTC4291_REG_HPMD3 0x50
+#define LTC4291_REG_HPMD4 0x55
+#define LTC4291_REG_LPWRPB 0x6E
+
+#define LTC4291_FLD_STATPIN_AUTO BIT(0)
+#define LTC4291_FLD_RSTPB_RSTALL BIT(4)
+
+#define LTC4291_STATPWR_ON_PORT(port) (0x01 << (port))
+#define LTC4291_DETENA_EN_PORT(port) (0x11 << (port))
+#define LTC4291_DETPB_EN_PORT(port) (0x11 << (port))
+#define LTC4291_PWRPB_OFF_PORT(port) (0x10 << (port))
+
+#define LTC4291_OPMD_AUTO 0xFF
+#define LTC4291_DISENA_ALL 0x0F
+#define LTC4291_DETENA_ALL 0xFF
+#define LTC4291_ID 0x64
+#define LTC4291_DEVID 0x38
+#define LTC4291_HPMD_MIN 0x00
+#define LTC4291_HPMD_MAX 0xA8
+
+#define LTC4291_PORT_MAX 4
+
+#define LTC4291_RESET_DELAY_US (20 * MSEC)
+
+#define I2C_PSE_READ(reg, data) \
+	i2c_read8(I2C_PORT_PSE, LTC4291_I2C_ADDR, LTC4291_REG_##reg, (data))
+
+#define I2C_PSE_WRITE(reg, data) \
+	i2c_write8(I2C_PORT_PSE, LTC4291_I2C_ADDR, LTC4291_REG_##reg, (data))
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+static int pse_write_hpmd(int port, int val)
+{
+	switch (port) {
+	case 0:
+		return I2C_PSE_WRITE(HPMD1, val);
+	case 1:
+		return I2C_PSE_WRITE(HPMD2, val);
+	case 2:
+		return I2C_PSE_WRITE(HPMD3, val);
+	case 3:
+		return I2C_PSE_WRITE(HPMD4, val);
+	default:
+		return EC_ERROR_INVAL;
+	}
+}
+
+/*
+ * Port 1-4: 15W
+ */
+static int pse_port_hpmd[LTC4291_PORT_MAX] = {
+	LTC4291_HPMD_MIN,
+	LTC4291_HPMD_MIN,
+	LTC4291_HPMD_MIN,
+	LTC4291_HPMD_MIN,
+};
+
+static int pse_port_enable(int port)
+{
+	/* Enable detection and classification */
+	return I2C_PSE_WRITE(DETPB, LTC4291_DETPB_EN_PORT(port));
+}
+
+static int pse_port_disable(int port)
+{
+	/* Request power off (this also disables detection/classification) */
+	return I2C_PSE_WRITE(PWRPB, LTC4291_PWRPB_OFF_PORT(port));
+}
+
+static int pse_init_worker(void)
+{
+	timestamp_t deadline;
+	int err, id, devid, statpin, port;
+
+	/* Ignore errors -- may already be resetting */
+	I2C_PSE_WRITE(RSTPB, LTC4291_FLD_RSTPB_RSTALL);
+
+	deadline.val = get_time().val + LTC4291_RESET_DELAY_US;
+	while ((err = I2C_PSE_READ(ID, &id)) != 0) {
+		if (timestamp_expired(deadline, NULL))
+			return err;
+	}
+
+	err = I2C_PSE_READ(DEVID, &devid);
+	if (err != 0)
+		return err;
+
+	if (id != LTC4291_ID || devid != LTC4291_DEVID)
+		return EC_ERROR_INVAL;
+
+	err = I2C_PSE_READ(STATPIN, &statpin);
+	if (err != 0)
+		return err;
+
+	/*
+	 * We don't want to supply power until we've had a chance to set the
+	 * limits.
+	 */
+	if (statpin & LTC4291_FLD_STATPIN_AUTO)
+		CPRINTS("WARN: PSE reset in AUTO mode");
+
+	err = I2C_PSE_WRITE(OPMD, LTC4291_OPMD_AUTO);
+	if (err != 0)
+		return err;
+
+	/* Set maximum power each port is allowed to allocate. */
+	for (port = 0; port < LTC4291_PORT_MAX; port++) {
+		err = pse_write_hpmd(port, pse_port_hpmd[port]);
+		if (err != 0)
+			return err;
+	}
+
+	err = I2C_PSE_WRITE(DISENA, LTC4291_DISENA_ALL);
+	if (err != 0)
+		return err;
+
+	err = I2C_PSE_WRITE(DETENA, LTC4291_DETENA_ALL);
+	if (err != 0)
+		return err;
+
+	return 0;
+}
+
+static void pse_init(void)
+{
+	int err;
+
+	err = pse_init_worker();
+	if (err != 0)
+		CPRINTS("PSE init failed: %d", err);
+	else
+		CPRINTS("PSE init done");
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, pse_init, HOOK_PRIO_DEFAULT);
+
+/* Also reset the PSE on a reboot to toggle the power. */
+DECLARE_HOOK(HOOK_CHIPSET_RESET, pse_init, HOOK_PRIO_DEFAULT);
+
+static int command_pse(int argc, const char **argv)
+{
+	int port;
+
+	/*
+	 *  TODO(b/156399232): endeavour: PSE controller reset by PLTRST
+	 *
+	 *  Initialization does not reliably work after reset because the device
+	 *  is held in reset by the AP. Running this command after boot finishes
+	 *  always succeeds. Remove once the reset signal changes.
+	 */
+	if (!strncmp(argv[1], "init", 4))
+		return pse_init_worker();
+
+	if (argc != 3)
+		return EC_ERROR_PARAM_COUNT;
+
+	port = atoi(argv[1]);
+	if (port < 0 || port >= LTC4291_PORT_MAX)
+		return EC_ERROR_PARAM1;
+
+	if (!strncmp(argv[2], "off", 3))
+		return pse_port_disable(port);
+	else if (!strncmp(argv[2], "on", 2))
+		return pse_port_enable(port);
+	else if (!strncmp(argv[2], "min", 3))
+		return pse_write_hpmd(port, LTC4291_HPMD_MIN);
+	else if (!strncmp(argv[2], "max", 3))
+		return pse_write_hpmd(port, LTC4291_HPMD_MAX);
+	else
+		return EC_ERROR_PARAM2;
+}
+DECLARE_CONSOLE_COMMAND(pse, command_pse, "<port# 0-3> <off | on | min | max>",
+			"Set PSE port power");
+
+static int ec_command_pse_status(int port, uint8_t *status)
+{
+	int detena, statpwr;
+	int err;
+
+	err = I2C_PSE_READ(DETENA, &detena);
+	if (err != 0)
+		return err;
+
+	err = I2C_PSE_READ(STATPWR, &statpwr);
+	if (err != 0)
+		return err;
+
+	if ((detena & LTC4291_DETENA_EN_PORT(port)) == 0)
+		*status = EC_PSE_STATUS_DISABLED;
+	else if ((statpwr & LTC4291_STATPWR_ON_PORT(port)) == 0)
+		*status = EC_PSE_STATUS_ENABLED;
+	else
+		*status = EC_PSE_STATUS_POWERED;
+
+	return 0;
+}
+
+static enum ec_status ec_command_pse(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_pse *p = args->params;
+	int err = 0;
+
+	if (p->port >= LTC4291_PORT_MAX)
+		return EC_RES_INVALID_PARAM;
+
+	switch (p->cmd) {
+	case EC_PSE_STATUS: {
+		struct ec_response_pse_status *r = args->response;
+
+		args->response_size = sizeof(*r);
+		err = ec_command_pse_status(p->port, &r->status);
+		break;
+	}
+	case EC_PSE_ENABLE:
+		err = pse_port_enable(p->port);
+		break;
+	case EC_PSE_DISABLE:
+		err = pse_port_disable(p->port);
+		break;
+	default:
+		return EC_RES_INVALID_PARAM;
+	}
+
+	if (err)
+		return EC_RES_ERROR;
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_PSE, ec_command_pse, EC_VER_MASK(0));
diff --git a/board/morphius/battery.c b/board/morphius/battery.c
index 6d8a8190b2..6867bcd8bd 100644
--- a/board/morphius/battery.c
+++ b/board/morphius/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/morphius/board.c b/board/morphius/board.c
index 8dca1c99ed..03a141e98b 100644
--- a/board/morphius/board.c
+++ b/board/morphius/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,15 +6,17 @@
 /* Morphius board configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "battery_smart.h"
 #include "button.h"
+#include "cbi_ssfc.h"
 #include "charger.h"
 #include "cros_board_info.h"
-#include "driver/accelgyro_bmi_common.h"
 #include "driver/accel_kionix.h"
 #include "driver/accel_kx022.h"
-#include "driver/ppc/aoz1380.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "driver/accelgyro_icm426xx.h"
+#include "driver/accelgyro_icm_common.h"
+#include "driver/ppc/aoz1380_public.h"
 #include "driver/ppc/nx20p348x.h"
 #include "driver/retimer/pi3dpx1207.h"
 #include "driver/retimer/pi3hdx1204.h"
@@ -22,12 +24,13 @@
 #include "driver/temp_sensor/tmp432.h"
 #include "driver/usb_mux/amd_fp5.h"
 #include "extpower.h"
-#include "gpio.h"
 #include "fan.h"
 #include "fan_chip.h"
+#include "gpio.h"
 #include "hooks.h"
 #include "keyboard_8042.h"
 #include "lid_switch.h"
+#include "mkbp_event.h"
 #include "power.h"
 #include "power_button.h"
 #include "ps2_chip.h"
@@ -38,39 +41,39 @@
 #include "tablet_mode.h"
 #include "task.h"
 #include "temp_sensor.h"
-#include "thermistor.h"
-#include "usb_mux.h"
+#include "temp_sensor/thermistor.h"
 #include "usb_charge.h"
+#include "usb_mux.h"
 #include "usbc_ppc.h"
 
 static void hdmi_hpd_interrupt_v2(enum ioex_signal signal);
 static void hdmi_hpd_interrupt_v3(enum gpio_signal signal);
 static void board_gmr_tablet_switch_isr(enum gpio_signal signal);
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 static bool support_aoz_ppc;
-
-#ifdef HAS_TASK_MOTIONSENSE
+static bool ignore_c1_dp;
 
 /* Motion sensors */
 static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
-mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0,  0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+				 { FLOAT_TO_FP(1), 0, 0 },
+				 { 0, 0, FLOAT_TO_FP(-1) } };
+const mat33_fp_t base_standard_ref_1 = { { FLOAT_TO_FP(-1), 0, 0 },
+					 { 0, FLOAT_TO_FP(1), 0 },
+					 { 0, 0, FLOAT_TO_FP(-1) } };
+mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+				{ FLOAT_TO_FP(-1), 0, 0 },
+				{ 0, 0, FLOAT_TO_FP(1) } };
 
 /* sensor private data */
 static struct kionix_accel_data g_kx022_data;
 static struct bmi_drv_data_t g_bmi160_data;
+static struct icm_drv_data_t g_icm426xx_data;
 
 /* TODO(gcc >= 5.0) Remove the casts to const pointer at rot_standard_ref */
 struct motion_sensor_t motion_sensors[] = {
@@ -113,7 +116,7 @@ struct motion_sensor_t motion_sensors[] = {
 	 .drv_data = &g_bmi160_data,
 	 .port = I2C_PORT_SENSOR,
 	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 2, /* g, enough for laptop */
+	 .default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
 	 .rot_standard_ref = (const mat33_fp_t *)&base_standard_ref,
 	 .min_frequency = BMI_ACCEL_MIN_FREQ,
 	 .max_frequency = BMI_ACCEL_MAX_FREQ,
@@ -150,7 +153,49 @@ struct motion_sensor_t motion_sensors[] = {
 
 unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
-#endif /* HAS_TASK_MOTIONSENSE */
+struct motion_sensor_t icm426xx_base_accel = {
+	.name = "Base Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
+	.rot_standard_ref = &base_standard_ref_1,
+	.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
+	.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100,
+		},
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	},
+};
+struct motion_sensor_t icm426xx_base_gyro = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &base_standard_ref_1,
+	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
+	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
+};
 
 const struct pwm_t pwm_channels[] = {
 	[PWM_CH_KBLIGHT] = {
@@ -189,13 +234,64 @@ const int usb_port_enable[USBA_PORT_COUNT] = {
 const struct pi3hdx1204_tuning pi3hdx1204_tuning = {
 	.eq_ch0_ch1_offset = PI3HDX1204_EQ_DB710,
 	.eq_ch2_ch3_offset = PI3HDX1204_EQ_DB710,
-	.vod_offset = PI3HDX1204_VOD_115_ALL_CHANNELS,
+	.vod_offset = PI3HDX1204_VOD_130_ALL_CHANNELS,
 	.de_offset = PI3HDX1204_DE_DB_MINUS7,
 };
 
+/*****************************************************************************
+ * Base Gyro Sensor dynamic configuration
+ */
+static enum ec_ssfc_base_gyro_sensor base_gyro_config = SSFC_BASE_GYRO_NONE;
+
+enum ec_ssfc_base_gyro_sensor get_base_gyro_sensor(void)
+{
+	switch (get_cbi_ssfc_base_sensor()) {
+	case SSFC_BASE_GYRO_NONE:
+		return ec_config_has_base_gyro_sensor();
+	default:
+		return get_cbi_ssfc_base_sensor();
+	}
+}
+
+static void setup_base_gyro_config(void)
+{
+	base_gyro_config = get_base_gyro_sensor();
+
+	switch (base_gyro_config) {
+	case SSFC_BASE_GYRO_BMI160:
+		ccprints("BASE GYRO is BMI160");
+		break;
+	case SSFC_BASE_GYRO_ICM426XX:
+		motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
+		motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
+		ccprints("BASE GYRO is ICM426XX");
+		break;
+	default:
+		break;
+	}
+}
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	switch (base_gyro_config) {
+	case SSFC_BASE_GYRO_BMI160:
+		bmi160_interrupt(signal);
+		break;
+	case SSFC_BASE_GYRO_ICM426XX:
+		icm426xx_interrupt(signal);
+		break;
+	default:
+		break;
+	}
+}
+
 /*****************************************************************************
  * USB-C MUX/Retimer dynamic configuration
  */
+
+/* Place holder for second mux in USBC1 chain */
+struct usb_mux_chain usbc1_mux1;
+
 static void setup_mux(void)
 {
 	if (ec_config_has_usbc1_retimer_ps8802()) {
@@ -207,12 +303,10 @@ static void setup_mux(void)
 		 * Replace usb_muxes[USBC_PORT_C1] with the PS8802
 		 * table entry.
 		 */
-		memcpy(&usb_muxes[USBC_PORT_C1],
-		       &usbc1_ps8802,
-		       sizeof(struct usb_mux));
+		usb_muxes[USBC_PORT_C1].mux = &usbc1_ps8802;
 
 		/* Set the AMD FP5 as the secondary MUX */
-		usb_muxes[USBC_PORT_C1].next_mux = &usbc1_amd_fp5_usb_mux;
+		usbc1_mux1.mux = &usbc1_amd_fp5_usb_mux;
 
 		/* Don't have the AMD FP5 flip */
 		usbc1_amd_fp5_usb_mux.flags = USB_MUX_FLAG_SET_WITHOUT_FLIP;
@@ -226,12 +320,10 @@ static void setup_mux(void)
 		 * Replace usb_muxes[USBC_PORT_C1] with the AMD FP5
 		 * table entry.
 		 */
-		memcpy(&usb_muxes[USBC_PORT_C1],
-		       &usbc1_amd_fp5_usb_mux,
-		       sizeof(struct usb_mux));
+		usb_muxes[USBC_PORT_C1].mux = &usbc1_amd_fp5_usb_mux;
 
 		/* Set the PS8818 as the secondary MUX */
-		usb_muxes[USBC_PORT_C1].next_mux = &usbc1_ps8818;
+		usbc1_mux1.mux = &usbc1_ps8818;
 	}
 }
 
@@ -245,23 +337,29 @@ const struct pi3dpx1207_usb_control pi3dpx1207_controls[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(pi3dpx1207_controls) == USBC_PORT_COUNT);
 
-const struct usb_mux usbc0_pi3dpx1207_usb_retimer = {
-	.usb_port = USBC_PORT_C0,
-	.i2c_port = I2C_PORT_TCPC0,
-	.i2c_addr_flags = PI3DPX1207_I2C_ADDR_FLAGS,
-	.driver = &pi3dpx1207_usb_retimer,
+const struct usb_mux_chain usbc0_pi3dpx1207_usb_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.i2c_port = I2C_PORT_TCPC0,
+			.i2c_addr_flags = PI3DPX1207_I2C_ADDR_FLAGS,
+			.driver = &pi3dpx1207_usb_retimer,
+		},
 };
 
-struct usb_mux usb_muxes[] = {
+struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.i2c_port = I2C_PORT_USB_AP_MUX,
-		.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
-		.driver = &amd_fp5_usb_mux_driver,
-		.next_mux = &usbc0_pi3dpx1207_usb_retimer,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.i2c_port = I2C_PORT_USB_AP_MUX,
+			.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
+			.driver = &amd_fp5_usb_mux_driver,
+		},
+		.next = &usbc0_pi3dpx1207_usb_retimer,
 	},
 	[USBC_PORT_C1] = {
 		/* Filled in dynamically at startup */
+		.next = &usbc1_mux1,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
@@ -286,7 +384,7 @@ static void setup_v0_charger(void)
  */
 DECLARE_HOOK(HOOK_INIT, setup_v0_charger, HOOK_PRIO_INIT_I2C);
 
-enum gpio_signal board_usbc_port_to_hpd_gpio(int port)
+int board_usbc_port_to_hpd_gpio_or_ioex(int port)
 {
 	/* USB-C0 always uses USB_C0_HPD (= DP3_HPD). */
 	if (port == 0)
@@ -303,11 +401,9 @@ enum gpio_signal board_usbc_port_to_hpd_gpio(int port)
 	 * this will be removed when version_2 hardware is retired.
 	 */
 	else if (ec_config_has_mst_hub_rtd2141b())
-		return (board_ver >= 4)
-				? GPIO_USB_C1_HPD_IN_DB_V1
-				: (board_ver == 3)
-					? IOEX_USB_C1_HPD_IN_DB
-					: GPIO_EC_DP1_HPD;
+		return (board_ver >= 4) ? GPIO_USB_C1_HPD_IN_DB_V1 :
+		       (board_ver == 3) ? IOEX_USB_C1_HPD_IN_DB :
+					  GPIO_EC_DP1_HPD;
 
 	/* USB-C1 OPT1 DB uses DP2_HPD. */
 	return GPIO_DP2_HPD;
@@ -376,6 +472,8 @@ static void setup_fw_config(void)
 	setup_mux();
 
 	board_remap_gpio();
+
+	setup_base_gyro_config();
 }
 /* Use HOOK_PRIO_INIT_I2C + 2 to be after ioex_init(). */
 DECLARE_HOOK(HOOK_INIT, setup_fw_config, HOOK_PRIO_INIT_I2C + 2);
@@ -387,7 +485,7 @@ DECLARE_HOOK(HOOK_INIT, setup_fw_config, HOOK_PRIO_INIT_I2C + 2);
 /* Physical fans. These are logically separate from pwm_channels. */
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = -1,
 };
@@ -482,17 +580,20 @@ const struct temp_sensor_t temp_sensors[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
-const static struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(90),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(105),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
-	},
-	.temp_fan_off = C_TO_K(98),
-	.temp_fan_max = C_TO_K(99),
-};
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(90), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(105), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(80), \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 
 struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
 
@@ -503,11 +604,11 @@ static void setup_fans(void)
 DECLARE_HOOK(HOOK_INIT, setup_fans, HOOK_PRIO_DEFAULT);
 
 /* Battery functions */
-#define SB_OPTIONALMFG_FUNCTION2        0x26
-#define SMART_CHARGE_SUPPORT            0x01
-#define SMART_CHARGE_ENABLE             0x02
-#define SB_SMART_CHARGE_ENABLE          1
-#define SB_SMART_CHARGE_DISABLE         0
+#define SB_OPTIONALMFG_FUNCTION2 0x26
+#define SMART_CHARGE_SUPPORT 0x01
+#define SMART_CHARGE_ENABLE 0x02
+#define SB_SMART_CHARGE_ENABLE 1
+#define SB_SMART_CHARGE_DISABLE 0
 
 static void sb_smart_charge_mode(int enable)
 {
@@ -549,18 +650,18 @@ __override void ppc_interrupt(enum gpio_signal signal)
  * the attached NCT3807 to control a GPIO to indicate 1A5 or 3A0
  * current limits.
  */
-__override int board_aoz1380_set_vbus_source_current_limit(int port,
-						enum tcpc_rp_value rp)
+__override int
+board_aoz1380_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp)
 {
 	int rv;
 
 	/* Use the TCPC to set the current limit */
 	if (port == 0) {
 		rv = ioex_set_level(IOEX_USB_C0_PPC_ILIM_3A_EN,
-			    (rp == TYPEC_RP_3A0) ? 1 : 0);
+				    (rp == TYPEC_RP_3A0) ? 1 : 0);
 	} else if (board_ver >= 3) {
 		rv = ioex_set_level(IOEX_USB_C1_PPC_ILIM_3A_EN,
-			    (rp == TYPEC_RP_3A0) ? 1 : 0);
+				    (rp == TYPEC_RP_3A0) ? 1 : 0);
 	} else {
 		rv = 1;
 	}
@@ -614,26 +715,37 @@ static void board_chipset_resume(void)
 			ioex_set_level(IOEX_HDMI_POWER_EN_DB, 1);
 			msleep(PI3HDX1204_POWER_ON_DELAY_MS);
 		}
-		pi3hdx1204_enable(I2C_PORT_TCPC1,
-				  PI3HDX1204_I2C_ADDR_FLAGS,
+		pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS,
 				  check_hdmi_hpd_status());
 	}
 }
 DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
 
+static void board_chipset_suspend_delay(void)
+{
+	ignore_c1_dp = false;
+}
+DECLARE_DEFERRED(board_chipset_suspend_delay);
+
 static void board_chipset_suspend(void)
 {
 	/* SMART charge current */
 	sb_smart_charge_mode(SB_SMART_CHARGE_ENABLE);
 
 	if (ec_config_has_hdmi_retimer_pi3hdx1204()) {
-		pi3hdx1204_enable(I2C_PORT_TCPC1,
-				  PI3HDX1204_I2C_ADDR_FLAGS,
-				  0);
+		pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS, 0);
 		if (board_ver >= 3)
 			ioex_set_level(IOEX_HDMI_POWER_EN_DB, 0);
 	}
 
+	/* Wait 500ms before allowing DP event to cause resume. */
+	if (ec_config_has_mst_hub_rtd2141b() &&
+	    (dp_flags[USBC_PORT_C1] & DP_FLAGS_DP_ON)) {
+		ignore_c1_dp = true;
+		hook_call_deferred(&board_chipset_suspend_delay_data,
+				   500 * MSEC);
+	}
+
 	ioex_set_level(IOEX_HDMI_DATA_EN_DB, 0);
 }
 DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
@@ -673,15 +785,14 @@ BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
  * The connector has 24 pins total, and there is no pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-		{3, 0}, {2, 2}, {2, 3}, {1, 2}, {2, 5},
-		{2, 4}, {2, 1}, {2, 7}, {2, 6}, {1, 5},
-		{2, 0}, {3, 1}, {1, 7}, {1, 6}, {-1, -1},
-		{1, 3}, {1, 4}, {-1, -1}, {-1, -1}, {0, 7},
-		{0, 6}, {1, 0}, {1, 1}, {0, 5},
+	{ 3, 0 },   { 2, 2 }, { 2, 3 },	  { 1, 2 }, { 2, 5 }, { 2, 4 },
+	{ 2, 1 },   { 2, 7 }, { 2, 6 },	  { 1, 5 }, { 2, 0 }, { 3, 1 },
+	{ 1, 7 },   { 1, 6 }, { -1, -1 }, { 1, 3 }, { 1, 4 }, { -1, -1 },
+	{ -1, -1 }, { 0, 7 }, { 0, 6 },	  { 1, 0 }, { 1, 1 }, { 0, 5 },
 };
 
 const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 #endif
 
 /*****************************************************************************
@@ -724,10 +835,9 @@ static void hdmi_hpd_handler(void)
 
 	gpio_set_level(GPIO_EC_DP1_HPD, hpd);
 	ccprints("HDMI HPD %d", hpd);
-	pi3hdx1204_enable(I2C_PORT_TCPC1,
-			  PI3HDX1204_I2C_ADDR_FLAGS,
-			  chipset_in_or_transitioning_to_state(CHIPSET_STATE_ON)
-			  && hpd);
+	pi3hdx1204_enable(
+		I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS,
+		chipset_in_or_transitioning_to_state(CHIPSET_STATE_ON) && hpd);
 }
 DECLARE_DEFERRED(hdmi_hpd_handler);
 
@@ -758,7 +868,20 @@ int board_sensor_at_360(void)
 	 * mode.
 	 */
 	if (board_ver >= 3)
-		return !gpio_get_level(GMR_TABLET_MODE_GPIO_L);
+		return !gpio_get_level(GPIO_TABLET_MODE_L);
 
 	return 0;
 }
+
+/*
+ * b/167949458: Suppress setting the host event for 500ms after entering S3.
+ * Otherwise turning off the MST hub in S3 (via IOEX_HDMI_DATA_EN_DB) causes
+ * a VDM:Attention that immediately wakes us back up from S3.
+ */
+__override void pd_notify_dp_alt_mode_entry(int port)
+{
+	if (port == USBC_PORT_C1 && ignore_c1_dp)
+		return;
+	cprints(CC_USBPD, "Notifying AP of DP Alt Mode Entry...");
+	mkbp_send_event(EC_MKBP_EVENT_DP_ALT_MODE_ENTERED);
+}
diff --git a/board/morphius/board.h b/board/morphius/board.h
index 2375a186c0..ca3ecf4f03 100644
--- a/board/morphius/board.h
+++ b/board/morphius/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,25 +10,32 @@
 
 #define VARIANT_ZORK_TREMBYLE
 
-#include <stdbool.h>
 #include "baseboard.h"
 
+#include <stdbool.h>
+
 #define CONFIG_USBC_RETIMER_PI3DPX1207
-#define CONFIG_MKBP_USE_GPIO
 #define CONFIG_8042_AUX
 #define CONFIG_PS2
 #define CONFIG_CMD_PS2
 #define CONFIG_KEYBOARD_FACTORY_TEST
 #define CONFIG_DEVICE_EVENT
+#define CONFIG_ASSERT_CCD_MODE_ON_DTS_CONNECT
 
 #undef CONFIG_LED_ONOFF_STATES
-#define CONFIG_BATTERY_LEVEL_NEAR_FULL 91
+#undef CONFIG_BATT_HOST_FULL_FACTOR
+#define CONFIG_BATT_HOST_FULL_FACTOR 91
+
+#undef ZORK_PS8818_RX_INPUT_TERM
+#define ZORK_PS8818_RX_INPUT_TERM PS8818_RX_INPUT_TERM_85_OHM
 
 /* Motion sensing drivers */
+#define CONFIG_ACCELGYRO_ICM426XX
+#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 #define CONFIG_ACCELGYRO_BMI160
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCEL_INTERRUPTS
 #define CONFIG_ACCEL_KX022
 #define CONFIG_CMD_ACCELS
 #define CONFIG_CMD_ACCEL_INFO
@@ -36,46 +43,46 @@
 #define CONFIG_TABLET_MODE
 #define CONFIG_TEMP_SENSOR
 #define CONFIG_TEMP_SENSOR_TMP432
-#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_PWR_A
+#define CONFIG_TEMP_SENSOR_POWER
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_UPDATE
 #define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
 #define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
 #define CONFIG_GMR_TABLET_MODE
 #define CONFIG_GMR_TABLET_MODE_CUSTOM
-#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE
+#define GPIO_TABLET_MODE_L GPIO_TABLET_MODE
 #define RPM_DEVIATION 1
 
 /* GPIO mapping from board specific name to EC common name. */
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_EC_BATT_PRES_ODL
-#define CONFIG_SCI_GPIO			GPIO_EC_FCH_SCI_ODL
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_AP_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT_L		GPIO_EC_EDP_BL_DISABLE
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_FCH_PWR_BTN_L
-#define GPIO_PCH_RSMRST_L		GPIO_EC_FCH_RSMRST_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S5_L		GPIO_SLP_S5_L
-#define GPIO_PCH_SYS_PWROK		GPIO_EC_FCH_PWROK
-#define GPIO_PCH_WAKE_L			GPIO_EC_FCH_WAKE_L
-#define GPIO_POWER_BUTTON_L		GPIO_EC_PWR_BTN_ODL
-#define GPIO_S0_PGOOD			GPIO_S0_PWROK_OD
-#define GPIO_S5_PGOOD			GPIO_EC_PWROK_OD
-#define GPIO_SYS_RESET_L		GPIO_EC_SYS_RST_L
-#define GPIO_VOLUME_DOWN_L		GPIO_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
+#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL
+#define CONFIG_SCI_GPIO GPIO_EC_FCH_SCI_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_AP_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_EDP_BL_DISABLE
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PCH_PWRBTN_L GPIO_EC_FCH_PWR_BTN_L
+#define GPIO_PCH_RSMRST_L GPIO_EC_FCH_RSMRST_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L
+#define GPIO_PCH_SYS_PWROK GPIO_EC_FCH_PWROK
+#define GPIO_PCH_WAKE_L GPIO_EC_FCH_WAKE_L
+#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL
+#define GPIO_S0_PGOOD GPIO_S0_PWROK_OD
+#define GPIO_S5_PGOOD GPIO_EC_PWROK_OD
+#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_EN_PWR_A
+#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
 
 /* I2C mapping from board specific function*/
-#define I2C_PORT_THERMAL	I2C_PORT_AP_HDMI
+#define I2C_PORT_THERMAL I2C_PORT_AP_HDMI
 
 #ifndef __ASSEMBLER__
 
-
 void ps2_pwr_en_interrupt(enum gpio_signal signal);
 
 enum adc_channel {
@@ -112,16 +119,11 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum usba_port {
-	USBA_PORT_A0 = 0,
-	USBA_PORT_A1,
-	USBA_PORT_COUNT
-};
+enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT };
 
 /*****************************************************************************
  * CBI EC FW Configuration
  */
-#include "cbi_ec_fw_config.h"
 
 /**
  * MORPHIUS_MB_USBAC
@@ -165,57 +167,52 @@ enum ec_cfg_usb_db_type {
 	MORPHIUS_DB_T_OPT3_USBC_HDMI_MSTHUB = 1,
 };
 
+#include "cbi_ec_fw_config.h"
 
-#define HAS_USBC1_RETIMER_PS8802 \
-			(BIT(MORPHIUS_DB_T_OPT3_USBC_HDMI_MSTHUB))
+#define HAS_USBC1_RETIMER_PS8802 (BIT(MORPHIUS_DB_T_OPT3_USBC_HDMI_MSTHUB))
 
 static inline bool ec_config_has_usbc1_retimer_ps8802(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_USBC1_RETIMER_PS8802);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_USBC1_RETIMER_PS8802);
 }
 
-#define HAS_USBC1_RETIMER_PS8818 \
-			(BIT(MORPHIUS_DB_T_OPT1_USBC_HDMI))
+#define HAS_USBC1_RETIMER_PS8818 (BIT(MORPHIUS_DB_T_OPT1_USBC_HDMI))
 
 static inline bool ec_config_has_usbc1_retimer_ps8818(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_USBC1_RETIMER_PS8818);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_USBC1_RETIMER_PS8818);
 }
 
-#define HAS_HDMI_RETIMER_PI3HDX1204 \
-			(BIT(MORPHIUS_DB_T_OPT1_USBC_HDMI))
+#define HAS_HDMI_RETIMER_PI3HDX1204 (BIT(MORPHIUS_DB_T_OPT1_USBC_HDMI))
 
 static inline bool ec_config_has_hdmi_retimer_pi3hdx1204(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_HDMI_RETIMER_PI3HDX1204);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_HDMI_RETIMER_PI3HDX1204);
 }
 
-#define HAS_MST_HUB_RTD2141B \
-			(BIT(MORPHIUS_DB_T_OPT3_USBC_HDMI_MSTHUB))
+#define HAS_MST_HUB_RTD2141B (BIT(MORPHIUS_DB_T_OPT3_USBC_HDMI_MSTHUB))
 
 static inline bool ec_config_has_mst_hub_rtd2141b(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_MST_HUB_RTD2141B);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_MST_HUB_RTD2141B);
 }
 
-enum gpio_signal board_usbc_port_to_hpd_gpio(int port);
-#define PORT_TO_HPD(port) board_usbc_port_to_hpd_gpio(port)
+void motion_interrupt(enum gpio_signal signal);
 
-extern const struct usb_mux usbc0_pi3dpx1207_usb_retimer;
-extern const struct usb_mux usbc1_ps8802;
+/**
+ * @warning Callers must use gpio_or_ioex_set_level to handle the return result
+ * since either type of signal can be returned.
+ *
+ * @return GPIO (gpio_signal) or IOEX (ioex_signal)
+ */
+int board_usbc_port_to_hpd_gpio_or_ioex(int port);
+#define PORT_TO_HPD(port) board_usbc_port_to_hpd_gpio_or_ioex(port)
+
+extern const struct usb_mux_chain usbc0_pi3dpx1207_usb_retimer;
 extern const struct usb_mux usbc1_ps8818;
+extern struct usb_mux usbc1_ps8802;
 extern struct usb_mux usbc1_amd_fp5_usb_mux;
 
-#ifdef CONFIG_KEYBOARD_FACTORY_TEST
-extern const int keyboard_factory_scan_pins[][2];
-extern const int keyboard_factory_scan_pins_used;
-#endif
-
 #endif /* !__ASSEMBLER__ */
 
-
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/morphius/build.mk b/board/morphius/build.mk
index 4c2a6c5546..d6a15192ec 100644
--- a/board/morphius/build.mk
+++ b/board/morphius/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/morphius/ec.tasklist b/board/morphius/ec.tasklist
index 41b83cf4f3..4bb60ed55d 100644
--- a/board/morphius/ec.tasklist
+++ b/board/morphius/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/morphius/gpio.inc b/board/morphius/gpio.inc
index 5ec5875a3a..0597419c63 100644
--- a/board/morphius/gpio.inc
+++ b/board/morphius/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,7 +25,7 @@ GPIO_INT(ACOK_OD,		PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	extpower_inter
 GPIO_INT(EC_WP_L,		PIN(5, 0), GPIO_INT_BOTH,			switch_interrupt)
 GPIO_INT(VOLDN_BTN_ODL,		PIN(A, 6), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
 GPIO_INT(VOLUP_BTN_ODL,		PIN(9, 5), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-GPIO_INT(6AXIS_INT_L,		PIN(A, 0), GPIO_INT_FALLING | GPIO_PULL_UP,	bmi160_interrupt)
+GPIO_INT(6AXIS_INT_L,		PIN(A, 0), GPIO_INT_FALLING | GPIO_PULL_UP,	motion_interrupt)
 GPIO_INT(EN_PWR_TOUCHPAD_PS2,	PIN(C, 2), GPIO_INT_RISING,			ps2_pwr_en_interrupt)
 GPIO_INT(DP1_HPD_EC_IN,		PIN(7, 5), GPIO_INT_BOTH,			hdmi_hpd_interrupt_v3)
 
@@ -33,7 +33,7 @@ GPIO_INT(DP1_HPD_EC_IN,		PIN(7, 5), GPIO_INT_BOTH,			hdmi_hpd_interrupt_v3)
 GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH)
 
 GPIO(3AXIS_INT_L,		PIN(9, 6), GPIO_INPUT | GPIO_PULL_DOWN)		/* 3 Axis Accel */
-GPIO(CCD_MODE_ODL,		PIN(C, 6), GPIO_INPUT)				/* Case Closed Debug Mode */
+GPIO(CCD_MODE_ODL,		PIN(C, 6), GPIO_ODR_HIGH)			/* Case Closed Debug Mode */
 GPIO(PROCHOT_ODL,		PIN(D, 5), GPIO_ODR_HIGH)			/* PROCHOT to SOC */
 GPIO(EC_BATT_PRES_ODL,		PIN(4, 1), GPIO_INPUT)				/* Battery Present */
 GPIO(EC_AP_INT_ODL,		PIN(A, 3), GPIO_ODR_HIGH)			/* Sensor MKBP event to SOC */
@@ -55,7 +55,7 @@ GPIO(DP2_HPD,			PIN(C, 1), GPIO_OUT_LOW)			/* C1 DP Hotplug Detect */
 GPIO(EC_PS2_RESET_V0,		PIN(3, 2), GPIO_OUT_LOW)			/* Trackpoint reset pin V0*/
 GPIO(EC_PS2_RESET_V1,		PIN(4, 5), GPIO_OUT_LOW)			/* Trackpoint reset pin V1 */
 GPIO(EC_H1_PACKET_MODE,		PIN(8, 6), GPIO_OUT_LOW)			/* H1 Packet Mode */
-GPIO(FAN_ID,			PIN(8, 2), GPIO_INPUT)				/* Fan ID*/
+GPIO(FAN_ID,			PIN(8, 2), GPIO_INPUT | GPIO_PULL_UP)		/* Fan ID*/
 GPIO(USB_C1_HPD_IN_DB_V1,	PIN(B, 1), GPIO_OUT_LOW)			/* C1 HPD V1 */
 
 UNIMPLEMENTED(NO_HPD)
diff --git a/board/morphius/led.c b/board/morphius/led.c
index fc57b46d6b..55d29f1b2d 100644
--- a/board/morphius/led.c
+++ b/board/morphius/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,8 +17,8 @@
 #include "timer.h"
 #include "util.h"
 
-#define LED_BAT_OFF_LVL	0
-#define LED_BAT_ON_LVL	1
+#define LED_BAT_OFF_LVL 0
+#define LED_BAT_ON_LVL 1
 #define LED_BAT_S3_OFF_TIME_MS 3000
 #define LED_BAT_S3_PWM_RESCALE 5
 #define LED_BAT_S3_TICK_MS 50
@@ -34,10 +34,8 @@
 
 static int ticks;
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -45,21 +43,21 @@ enum led_color {
 	LED_OFF = 0,
 	LED_WHITE,
 	LED_AMBER,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 /* PWM brightness vs. color, in the order of off, white */
 static const uint8_t color_brightness[2] = {
-	[LED_OFF]   = 0,
-	[LED_WHITE]   = 100,
+	[LED_OFF] = 0,
+	[LED_WHITE] = 100,
 };
 
-void led_set_color_power(enum ec_led_colors color)
+void led_set_color_power(enum led_color color)
 {
 	pwm_set_duty(PWM_CH_POWER_LED, color_brightness[color]);
 }
 
-void led_set_color_battery(enum ec_led_colors color)
+void led_set_color_battery(enum led_color color)
 {
 	uint32_t board_ver = 0;
 	int led_batt_on_lvl, led_batt_off_lvl;
@@ -111,10 +109,10 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 	} else if (led_id == EC_LED_ID_POWER_LED) {
 		if (brightness[EC_LED_COLOR_WHITE] != 0)
 			pwm_set_duty(PWM_CH_POWER_LED,
-						color_brightness[LED_WHITE]);
+				     color_brightness[LED_WHITE]);
 		else
 			pwm_set_duty(PWM_CH_POWER_LED,
-						color_brightness[LED_OFF]);
+				     color_brightness[LED_OFF]);
 	}
 
 	return EC_SUCCESS;
@@ -133,8 +131,8 @@ static void suspend_led_update_deferred(void)
 	if (ticks <= TICKS_STEP2_DIMMER) {
 		pwm_set_duty(PWM_CH_POWER_LED, ticks * LED_BAT_S3_PWM_RESCALE);
 	} else if (ticks <= TICKS_STEP3_OFF) {
-		pwm_set_duty(PWM_CH_POWER_LED,
-					(TICKS_STEP3_OFF - ticks) * LED_BAT_S3_PWM_RESCALE);
+		pwm_set_duty(PWM_CH_POWER_LED, (TICKS_STEP3_OFF - ticks) *
+						       LED_BAT_S3_PWM_RESCALE);
 	} else {
 		ticks = TICKS_STEP1_BRIGHTER;
 		delay = LED_BAT_S3_OFF_TIME_MS * MSEC;
@@ -161,27 +159,26 @@ DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, suspend_led_deinit, HOOK_PRIO_DEFAULT);
 static void led_set_battery(void)
 {
 	static int battery_ticks;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
 		/* Always indicate when charging, even in suspend. */
 		led_set_color_battery(LED_AMBER);
 		break;
-	case PWR_STATE_DISCHARGE:
+	case LED_PWRS_DISCHARGE:
 		led_set_color_battery(LED_OFF);
 		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
+	case LED_PWRS_CHARGE_NEAR_FULL:
 		led_set_color_battery(LED_WHITE);
 		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			led_set_color_battery(
-				(battery_ticks & 0x4) ? LED_AMBER : LED_OFF);
-		else
-			led_set_color_battery(LED_WHITE);
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		led_set_color_battery(LED_WHITE);
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		led_set_color_battery((battery_ticks & 0x4) ? LED_AMBER :
+							      LED_OFF);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
@@ -204,9 +201,10 @@ static void led_set_power(void)
 			power_ticks = 0;
 
 		while (blink_ticks < LED_PWR_TICKS_PER_CYCLE) {
-			led_set_color_power(
-				(power_ticks % LED_TOTAL_TICKS) < LED_ON_TICKS ?
-				LED_WHITE : LED_OFF);
+			led_set_color_power((power_ticks % LED_TOTAL_TICKS) <
+							    LED_ON_TICKS ?
+						    LED_WHITE :
+						    LED_OFF);
 
 			previous_state_suspend = 1;
 			return;
diff --git a/board/morphius/thermal.c b/board/morphius/thermal.c
index 019e377aca..2ffc2d105b 100644
--- a/board/morphius/thermal.c
+++ b/board/morphius/thermal.c
@@ -1,13 +1,15 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "builtin/assert.h"
 #include "chipset.h"
 #include "common.h"
 #include "console.h"
 #include "extpower.h"
 #include "fan.h"
+#include "gpio.h"
 #include "hooks.h"
 #include "host_command.h"
 #include "lid_switch.h"
@@ -19,7 +21,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_THERMAL, outstr)
-#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
 
 struct fan_step {
 	/*
@@ -43,316 +45,315 @@ static const struct fan_step *fan_step_table;
 static const struct fan_step fan1_table_clamshell[] = {
 	{
 		/* level 0 */
-		.on = {-1, -1, -1, -1},
-		.off = {-1, -1, -1, -1},
-		.rpm = {0},
+		.on = { -1, -1, -1, -1 },
+		.off = { -1, -1, -1, -1 },
+		.rpm = { 0 },
 	},
 	{
 		/* level 1 */
-		.on = {-1, -1, 40, -1},
-		.off = {-1, -1, 31, -1},
-		.rpm = {1900},
+		.on = { -1, -1, 40, -1 },
+		.off = { -1, -1, 31, -1 },
+		.rpm = { 1900 },
 	},
 	{
 		/* level 2 */
-		.on = {-1, -1, 45, -1},
-		.off = {-1, -1, 43, -1},
-		.rpm = {2900},
+		.on = { -1, -1, 45, -1 },
+		.off = { -1, -1, 43, -1 },
+		.rpm = { 2900 },
 	},
 	{
 		/* level 3 */
-		.on = {-1, -1, 48, -1},
-		.off = {-1, -1, 46, -1},
-		.rpm = {3200},
+		.on = { -1, -1, 48, -1 },
+		.off = { -1, -1, 46, -1 },
+		.rpm = { 3200 },
 	},
 	{
 		/* level 4 */
-		.on = {-1, -1, 51, -1},
-		.off = {-1, -1, 49, -1},
-		.rpm = {3550},
+		.on = { -1, -1, 51, -1 },
+		.off = { -1, -1, 49, -1 },
+		.rpm = { 3550 },
 	},
 	{
 		/* level 5 */
-		.on = {-1, -1, 54, -1},
-		.off = {-1, -1, 52, -1},
-		.rpm = {3950},
+		.on = { -1, -1, 54, -1 },
+		.off = { -1, -1, 52, -1 },
+		.rpm = { 3950 },
 	},
 	{
 		/* level 6 */
-		.on = {-1, -1, 57, -1},
-		.off = {-1, -1, 55, -1},
-		.rpm = {4250},
+		.on = { -1, -1, 57, -1 },
+		.off = { -1, -1, 55, -1 },
+		.rpm = { 4250 },
 	},
 	{
 		/* level 7 */
-		.on = {-1, -1, 60, -1},
-		.off = {-1, -1, 58, -1},
-		.rpm = {4650},
+		.on = { -1, -1, 60, -1 },
+		.off = { -1, -1, 58, -1 },
+		.rpm = { 4650 },
 	},
 };
 
 static const struct fan_step fan1_table_tablet[] = {
 	{
 		/* level 0 */
-		.on = {-1, -1, -1, -1},
-		.off = {-1, -1, -1, -1},
-		.rpm = {0},
+		.on = { -1, -1, -1, -1 },
+		.off = { -1, -1, -1, -1 },
+		.rpm = { 0 },
 	},
 	{
 		/* level 1 */
-		.on = {-1, -1, 41, -1},
-		.off = {-1, -1, 31, -1},
-		.rpm = {2100},
+		.on = { -1, -1, 41, -1 },
+		.off = { -1, -1, 31, -1 },
+		.rpm = { 2100 },
 	},
 	{
 		/* level 2 */
-		.on = {-1, -1, 50, -1},
-		.off = {-1, -1, 48, -1},
-		.rpm = {2600},
+		.on = { -1, -1, 50, -1 },
+		.off = { -1, -1, 48, -1 },
+		.rpm = { 2600 },
 	},
 	{
 		/* level 3 */
-		.on = {-1, -1, 54, -1},
-		.off = {-1, -1, 52, -1},
-		.rpm = {2800},
+		.on = { -1, -1, 54, -1 },
+		.off = { -1, -1, 52, -1 },
+		.rpm = { 2800 },
 	},
 	{
 		/* level 4 */
-		.on = {-1, -1, 57, -1},
-		.off = {-1, -1, 55, -1},
-		.rpm = {3300},
+		.on = { -1, -1, 57, -1 },
+		.off = { -1, -1, 55, -1 },
+		.rpm = { 3300 },
 	},
 	{
 		/* level 5 */
-		.on = {-1, -1, 60, -1},
-		.off = {-1, -1, 58, -1},
-		.rpm = {3800},
+		.on = { -1, -1, 60, -1 },
+		.off = { -1, -1, 58, -1 },
+		.rpm = { 3800 },
 	},
 	{
 		/* level 6 */
-		.on = {-1, -1, 72, -1},
-		.off = {-1, -1, 69, -1},
-		.rpm = {4000},
+		.on = { -1, -1, 72, -1 },
+		.off = { -1, -1, 69, -1 },
+		.rpm = { 4000 },
 	},
 	{
 		/* level 7 */
-		.on = {-1, -1, 74, -1},
-		.off = {-1, -1, 73, -1},
-		.rpm = {4300},
+		.on = { -1, -1, 74, -1 },
+		.off = { -1, -1, 73, -1 },
+		.rpm = { 4300 },
 	},
 };
 
 static const struct fan_step fan1_table_stand[] = {
 	{
 		/* level 0 */
-		.on = {-1, -1, -1, -1},
-		.off = {-1, -1, -1, -1},
-		.rpm = {0},
+		.on = { -1, -1, -1, -1 },
+		.off = { -1, -1, -1, -1 },
+		.rpm = { 0 },
 	},
 	{
 		/* level 1 */
-		.on = {-1, -1, 34, -1},
-		.off = {-1, -1, 31, -1},
-		.rpm = {1850},
+		.on = { -1, -1, 34, -1 },
+		.off = { -1, -1, 31, -1 },
+		.rpm = { 1850 },
 	},
 	{
 		/* level 2 */
-		.on = {-1, -1, 42, -1},
-		.off = {-1, -1, 39, -1},
-		.rpm = {2550},
+		.on = { -1, -1, 42, -1 },
+		.off = { -1, -1, 39, -1 },
+		.rpm = { 2550 },
 	},
 	{
 		/* level 3 */
-		.on = {-1, -1, 49, -1},
-		.off = {-1, -1, 48, -1},
-		.rpm = {2900},
+		.on = { -1, -1, 49, -1 },
+		.off = { -1, -1, 48, -1 },
+		.rpm = { 2900 },
 	},
 	{
 		/* level 4 */
-		.on = {-1, -1, 51, -1},
-		.off = {-1, -1, 50, -1},
-		.rpm = {3350},
+		.on = { -1, -1, 51, -1 },
+		.off = { -1, -1, 50, -1 },
+		.rpm = { 3350 },
 	},
 	{
 		/* level 5 */
-		.on = {-1, -1, 53, -1},
-		.off = {-1, -1, 52, -1},
-		.rpm = {3700},
+		.on = { -1, -1, 53, -1 },
+		.off = { -1, -1, 52, -1 },
+		.rpm = { 3700 },
 	},
 	{
 		/* level 6 */
-		.on = {-1, -1, 55, -1},
-		.off = {-1, -1, 54, -1},
-		.rpm = {3900},
+		.on = { -1, -1, 55, -1 },
+		.off = { -1, -1, 54, -1 },
+		.rpm = { 3900 },
 	},
 	{
 		/* level 7 */
-		.on = {-1, -1, 57, -1},
-		.off = {-1, -1, 56, -1},
-		.rpm = {4250},
+		.on = { -1, -1, 57, -1 },
+		.off = { -1, -1, 56, -1 },
+		.rpm = { 4250 },
 	},
 };
 
 static const struct fan_step fan0_table_clamshell[] = {
 	{
 		/* level 0 */
-		.on = {-1, -1, -1, -1},
-		.off = {-1, -1, -1, -1},
-		.rpm = {0},
+		.on = { -1, -1, -1, -1 },
+		.off = { -1, -1, -1, -1 },
+		.rpm = { 0 },
 	},
 	{
 		/* level 1 */
-		.on = {-1, -1, 41, -1},
-		.off = {-1, -1, 31, -1},
-		.rpm = {2350},
+		.on = { -1, -1, 41, -1 },
+		.off = { -1, -1, 31, -1 },
+		.rpm = { 2350 },
 	},
 	{
 		/* level 2 */
-		.on = {-1, -1, 44, -1},
-		.off = {-1, -1, 42, -1},
-		.rpm = {3300},
+		.on = { -1, -1, 44, -1 },
+		.off = { -1, -1, 42, -1 },
+		.rpm = { 3300 },
 	},
 	{
 		/* level 3 */
-		.on = {-1, -1, 47, -1},
-		.off = {-1, -1, 45, -1},
-		.rpm = {3600},
+		.on = { -1, -1, 47, -1 },
+		.off = { -1, -1, 45, -1 },
+		.rpm = { 3600 },
 	},
 	{
 		/* level 4 */
-		.on = {-1, -1, 50, -1},
-		.off = {-1, -1, 48, -1},
-		.rpm = {4050},
+		.on = { -1, -1, 50, -1 },
+		.off = { -1, -1, 48, -1 },
+		.rpm = { 4050 },
 	},
 	{
 		/* level 5 */
-		.on = {-1, -1, 53, -1},
-		.off = {-1, -1, 51, -1},
-		.rpm = {4450},
+		.on = { -1, -1, 53, -1 },
+		.off = { -1, -1, 51, -1 },
+		.rpm = { 4450 },
 	},
 	{
 		/* level 6 */
-		.on = {-1, -1, 56, -1},
-		.off = {-1, -1, 54, -1},
-		.rpm = {4750},
+		.on = { -1, -1, 56, -1 },
+		.off = { -1, -1, 54, -1 },
+		.rpm = { 4750 },
 	},
 	{
 		/* level 7 */
-		.on = {-1, -1, 59, -1},
-		.off = {-1, -1, 57, -1},
-		.rpm = {5150},
+		.on = { -1, -1, 59, -1 },
+		.off = { -1, -1, 57, -1 },
+		.rpm = { 5150 },
 	},
 };
 
 static const struct fan_step fan0_table_tablet[] = {
 	{
 		/* level 0 */
-		.on = {-1, -1, -1, -1},
-		.off = {-1, -1, -1, -1},
-		.rpm = {0},
+		.on = { -1, -1, -1, -1 },
+		.off = { -1, -1, -1, -1 },
+		.rpm = { 0 },
 	},
 	{
 		/* level 1 */
-		.on = {-1, -1, 41, -1},
-		.off = {-1, -1, 31, -1},
-		.rpm = {2250},
+		.on = { -1, -1, 41, -1 },
+		.off = { -1, -1, 31, -1 },
+		.rpm = { 2250 },
 	},
 	{
 		/* level 2 */
-		.on = {-1, -1, 50, -1},
-		.off = {-1, -1, 48, -1},
-		.rpm = {2850},
+		.on = { -1, -1, 50, -1 },
+		.off = { -1, -1, 48, -1 },
+		.rpm = { 2850 },
 	},
 	{
 		/* level 3 */
-		.on = {-1, -1, 54, -1},
-		.off = {-1, -1, 51, -1},
-		.rpm = {3100},
+		.on = { -1, -1, 54, -1 },
+		.off = { -1, -1, 51, -1 },
+		.rpm = { 3100 },
 	},
 	{
 		/* level 4 */
-		.on = {-1, -1, 57, -1},
-		.off = {-1, -1, 55, -1},
-		.rpm = {3500},
+		.on = { -1, -1, 57, -1 },
+		.off = { -1, -1, 55, -1 },
+		.rpm = { 3500 },
 	},
 	{
 		/* level 5 */
-		.on = {-1, -1, 60, -1},
-		.off = {-1, -1, 58, -1},
-		.rpm = {3900},
+		.on = { -1, -1, 60, -1 },
+		.off = { -1, -1, 58, -1 },
+		.rpm = { 3900 },
 	},
 	{
 		/* level 6 */
-		.on = {-1, -1, 72, -1},
-		.off = {-1, -1, 69, -1},
-		.rpm = {4150},
+		.on = { -1, -1, 72, -1 },
+		.off = { -1, -1, 69, -1 },
+		.rpm = { 4150 },
 	},
 	{
 		/* level 7 */
-		.on = {-1, -1, 74, -1},
-		.off = {-1, -1, 73, -1},
-		.rpm = {4400},
+		.on = { -1, -1, 74, -1 },
+		.off = { -1, -1, 73, -1 },
+		.rpm = { 4400 },
 	},
 };
 
 static const struct fan_step fan0_table_stand[] = {
 	{
 		/* level 0 */
-		.on = {-1, -1, -1, -1},
-		.off = {-1, -1, -1, -1},
-		.rpm = {0},
+		.on = { -1, -1, -1, -1 },
+		.off = { -1, -1, -1, -1 },
+		.rpm = { 0 },
 	},
 	{
 		/* level 1 */
-		.on = {-1, -1, 34, -1},
-		.off = {-1, -1, 31, -1},
-		.rpm = {2250},
+		.on = { -1, -1, 34, -1 },
+		.off = { -1, -1, 31, -1 },
+		.rpm = { 2250 },
 	},
 	{
 		/* level 2 */
-		.on = {-1, -1, 42, -1},
-		.off = {-1, -1, 39, -1},
-		.rpm = {2800},
+		.on = { -1, -1, 42, -1 },
+		.off = { -1, -1, 39, -1 },
+		.rpm = { 2800 },
 	},
 	{
 		/* level 3 */
-		.on = {-1, -1, 49, -1},
-		.off = {-1, -1, 48, -1},
-		.rpm = {3150},
+		.on = { -1, -1, 49, -1 },
+		.off = { -1, -1, 48, -1 },
+		.rpm = { 3150 },
 	},
 	{
 		/* level 4 */
-		.on = {-1, -1, 51, -1},
-		.off = {-1, -1, 50, -1},
-		.rpm = {3550},
+		.on = { -1, -1, 51, -1 },
+		.off = { -1, -1, 50, -1 },
+		.rpm = { 3550 },
 	},
 	{
 		/* level 5 */
-		.on = {-1, -1, 53, -1},
-		.off = {-1, -1, 52, -1},
-		.rpm = {3900},
+		.on = { -1, -1, 53, -1 },
+		.off = { -1, -1, 52, -1 },
+		.rpm = { 3900 },
 	},
 	{
 		/* level 6 */
-		.on = {-1, -1, 55, -1},
-		.off = {-1, -1, 54, -1},
-		.rpm = {4150},
+		.on = { -1, -1, 55, -1 },
+		.off = { -1, -1, 54, -1 },
+		.rpm = { 4150 },
 	},
 	{
 		/* level 7 */
-		.on = {-1, -1, 57, -1},
-		.off = {-1, -1, 56, -1},
-		.rpm = {4400},
+		.on = { -1, -1, 57, -1 },
+		.off = { -1, -1, 56, -1 },
+		.rpm = { 4400 },
 	},
 };
 
 #define NUM_FAN_LEVELS ARRAY_SIZE(fan1_table_clamshell)
 
-#define lid_angle_tablet	340
+#define lid_angle_tablet 340
 static int throttle_on;
 
-BUILD_ASSERT(ARRAY_SIZE(fan1_table_clamshell) ==
-	ARRAY_SIZE(fan1_table_tablet));
+BUILD_ASSERT(ARRAY_SIZE(fan1_table_clamshell) == ARRAY_SIZE(fan1_table_tablet));
 
 #define average_time 60
 int fan_table_to_rpm(int fan, int *temp)
@@ -403,7 +404,7 @@ int fan_table_to_rpm(int fan, int *temp)
 	for (j = 0; j < average_time; j++)
 		avg_sum = avg_sum + avg_calc_tmp[TEMP_SENSOR_CPU][j];
 
-	avg_tmp[TEMP_SENSOR_CPU] = avg_sum/average_time;
+	avg_tmp[TEMP_SENSOR_CPU] = avg_sum / average_time;
 
 	/*
 	 * Compare the current and previous temperature, we have
@@ -415,10 +416,10 @@ int fan_table_to_rpm(int fan, int *temp)
 	if (avg_tmp[TEMP_SENSOR_CPU] < prev_tmp[TEMP_SENSOR_CPU]) {
 		for (i = current_level; i >= 0; i--) {
 			if (avg_tmp[TEMP_SENSOR_CPU] <
-				fan_step_table[i].off[TEMP_SENSOR_CPU]) {
-			/*
-			 * fan step down debounce
-			 */
+			    fan_step_table[i].off[TEMP_SENSOR_CPU]) {
+				/*
+				 * fan step down debounce
+				 */
 				if (fan_down_count < 10) {
 					fan_down_count++;
 					fan_up_count = 0;
@@ -433,12 +434,12 @@ int fan_table_to_rpm(int fan, int *temp)
 				break;
 		}
 	} else if (avg_tmp[TEMP_SENSOR_CPU] > prev_tmp[TEMP_SENSOR_CPU]) {
-		for (i = current_level+1; i < NUM_FAN_LEVELS; i++) {
+		for (i = current_level + 1; i < NUM_FAN_LEVELS; i++) {
 			if ((avg_tmp[TEMP_SENSOR_CPU] >
-				 fan_step_table[i].on[TEMP_SENSOR_CPU])) {
-			/*
-			 * fan step up debounce
-			 */
+			     fan_step_table[i].on[TEMP_SENSOR_CPU])) {
+				/*
+				 * fan step up debounce
+				 */
 				if (fan_up_count < 10) {
 					fan_up_count++;
 					fan_down_count = 0;
@@ -495,21 +496,33 @@ void board_override_fan_control(int fan, int *tmp)
 
 void thermal_protect(void)
 {
+	int rv1, rv2;
 	int thermal_sensor1, thermal_sensor2;
 
-	temp_sensor_read(TEMP_SENSOR_5V_REGULATOR, &thermal_sensor1);
-	temp_sensor_read(TEMP_SENSOR_CPU, &thermal_sensor2);
-
-	if ((!lid_is_open()) && (!extpower_is_present())) {
-		if (thermal_sensor2 > C_TO_K(70)) {
-			chipset_throttle_cpu(1);
-			throttle_on = 1;
-		} else if (thermal_sensor2 < C_TO_K(60) && throttle_on) {
-			chipset_throttle_cpu(0);
-			throttle_on = 0;
+	rv1 = temp_sensor_read(TEMP_SENSOR_5V_REGULATOR, &thermal_sensor1);
+	rv2 = temp_sensor_read(TEMP_SENSOR_CPU, &thermal_sensor2);
+
+	if (rv2 == EC_SUCCESS) {
+		if ((!lid_is_open()) && (!extpower_is_present())) {
+			if (thermal_sensor2 > C_TO_K(70)) {
+				chipset_throttle_cpu(1);
+				throttle_on = 1;
+			} else if (thermal_sensor2 < C_TO_K(60) &&
+				   throttle_on) {
+				chipset_throttle_cpu(0);
+				throttle_on = 0;
+			}
+		} else {
+			if (throttle_on == 1) {
+				chipset_throttle_cpu(0);
+				throttle_on = 0;
+			}
 		}
+	}
 
-		if (thermal_sensor1 > C_TO_K(51))
+	if (rv1 == EC_SUCCESS) {
+		if ((!lid_is_open()) && (!extpower_is_present()) &&
+		    thermal_sensor1 > C_TO_K(51))
 			chipset_force_shutdown(CHIPSET_SHUTDOWN_THERMAL);
 	}
 }
diff --git a/board/morphius/vif_override.xml b/board/morphius/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/morphius/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/mrbland/base_detect.c b/board/mrbland/base_detect.c
new file mode 100644
index 0000000000..82326ab456
--- /dev/null
+++ b/board/mrbland/base_detect.c
@@ -0,0 +1,246 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Mrbland base detection code */
+
+#include "adc.h"
+#include "base_state.h"
+#include "board.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "lid_switch.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "timer.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+
+/* Make sure POGO VBUS starts later then PP3300_HUB when power on  */
+#define BASE_DETECT_EN_LATER_US (600 * MSEC)
+
+/* Base detection and debouncing */
+#define BASE_DETECT_EN_DEBOUNCE_US (350 * MSEC)
+#define BASE_DETECT_DIS_DEBOUNCE_US (20 * MSEC)
+
+/*
+ * If the base status is unclear (i.e. not within expected ranges, read
+ * the ADC value again every 500ms.
+ */
+#define BASE_DETECT_RETRY_US (500 * MSEC)
+
+/*
+ * Lid has 604K pull-up, base has 30.1K pull-down, so the
+ * ADC value should be around 30.1/(604+30.1)*3300 = 156
+ *
+ * We add a significant margin on the maximum value, due to noise on the line,
+ * especially when PWM is active. See b/64193554 for details.
+ */
+#define BASE_DETECT_MIN_MV 120
+#define BASE_DETECT_MAX_MV 300
+
+/* Minimum ADC value to indicate base is disconnected for sure */
+#define BASE_DETECT_DISCONNECT_MIN_MV 1500
+
+/*
+ * Base EC pulses detection pin for 500 us to signal out of band USB wake (that
+ * can be used to wake system from deep S3).
+ */
+#define BASE_DETECT_PULSE_MIN_US 400
+#define BASE_DETECT_PULSE_MAX_US 650
+
+static uint64_t base_detect_debounce_time;
+
+static void base_detect_deferred(void);
+DECLARE_DEFERRED(base_detect_deferred);
+
+enum base_status {
+	BASE_UNKNOWN = 0,
+	BASE_DISCONNECTED = 1,
+	BASE_CONNECTED = 2,
+};
+
+static enum base_status current_base_status;
+static bool current_base_enable_allow;
+
+/*
+ * This function is called whenever there is a change in the base detect
+ * status. Actions taken include:
+ * 1. Change in power to base after chipset startup, and disable the base
+ * power at chipset shutdown.
+ * 2. Indicate mode change to host.
+ * 3. Indicate tablet mode to host. Current assumption is that if base is
+ * disconnected then the system is in tablet mode, else if the base is
+ * connected, then the system is not in tablet mode.
+ * 4. Change lid dectect according to base status.
+ */
+static void base_detect_change(enum base_status status)
+{
+	int connected = (status == BASE_CONNECTED);
+	bool base_enable_allow =
+		!chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF);
+
+	if ((current_base_status == status) &&
+	    (current_base_enable_allow == base_enable_allow))
+		return;
+
+	if (base_enable_allow)
+		gpio_set_level(GPIO_EN_BASE, connected);
+	else
+		gpio_set_level(GPIO_EN_BASE, 0);
+
+	tablet_set_mode(!connected, TABLET_TRIGGER_BASE);
+	base_set_state(connected);
+	current_base_status = status;
+	current_base_enable_allow = base_enable_allow;
+	enable_lid_detect(connected);
+}
+
+/* Measure detection pin pulse duration (used to wake AP from deep S3). */
+static uint64_t pulse_start;
+static uint32_t pulse_width;
+
+static void print_base_detect_value(int v, int tmp_pulse_width)
+{
+	CPRINTS("%s = %d (pulse %d)", adc_channels[ADC_BASE_DET].name, v,
+		tmp_pulse_width);
+}
+
+static void base_detect_deferred(void)
+{
+	uint64_t time_now = get_time().val;
+	int v;
+	uint32_t tmp_pulse_width = pulse_width;
+
+	if (base_detect_debounce_time > time_now) {
+		hook_call_deferred(&base_detect_deferred_data,
+				   base_detect_debounce_time - time_now);
+		return;
+	}
+
+	v = adc_read_channel(ADC_BASE_DET);
+	if (v == ADC_READ_ERROR)
+		return;
+
+	print_base_detect_value(v, tmp_pulse_width);
+
+	if (v >= BASE_DETECT_MIN_MV && v <= BASE_DETECT_MAX_MV) {
+		if ((current_base_status != BASE_CONNECTED) ||
+		    (current_base_enable_allow != true)) {
+			base_detect_change(BASE_CONNECTED);
+		} else if (tmp_pulse_width >= BASE_DETECT_PULSE_MIN_US &&
+			   tmp_pulse_width <= BASE_DETECT_PULSE_MAX_US) {
+			CPRINTS("Sending event to AP");
+			host_set_single_event(EC_HOST_EVENT_KEY_PRESSED);
+		}
+		return;
+	}
+
+	if (v >= BASE_DETECT_DISCONNECT_MIN_MV) {
+		base_detect_change(BASE_DISCONNECTED);
+		return;
+	}
+
+	/* Unclear base status, schedule again in a while. */
+	hook_call_deferred(&base_detect_deferred_data, BASE_DETECT_RETRY_US);
+}
+
+static inline int detect_pin_connected(enum gpio_signal det_pin)
+{
+	return gpio_get_level(det_pin) == 0;
+}
+
+void base_detect_interrupt(enum gpio_signal signal)
+{
+	uint64_t time_now = get_time().val;
+	int debounce_us;
+
+	if (detect_pin_connected(signal))
+		debounce_us = BASE_DETECT_EN_DEBOUNCE_US;
+	else
+		debounce_us = BASE_DETECT_DIS_DEBOUNCE_US;
+
+	if (base_detect_debounce_time <= time_now) {
+		/*
+		 * Detect and measure detection pin pulse, when base is
+		 * connected. Only a single pulse is measured over a debounce
+		 * period. If no pulse, or multiple pulses are detected,
+		 * pulse_width is set to 0.
+		 */
+		if (current_base_status == BASE_CONNECTED &&
+		    !detect_pin_connected(signal)) {
+			pulse_start = time_now;
+		} else {
+			pulse_start = 0;
+		}
+		pulse_width = 0;
+
+		hook_call_deferred(&base_detect_deferred_data, debounce_us);
+	} else {
+		if (current_base_status == BASE_CONNECTED &&
+		    detect_pin_connected(signal) && !pulse_width &&
+		    pulse_start) {
+			/* First pulse within period. */
+			pulse_width = time_now - pulse_start;
+		} else {
+			pulse_start = 0;
+			pulse_width = 0;
+		}
+	}
+
+	base_detect_debounce_time = time_now + debounce_us;
+}
+
+static void base_enable(void)
+{
+	/* Enable base detection interrupt. */
+	base_detect_debounce_time = get_time().val;
+	hook_call_deferred(&base_detect_deferred_data, BASE_DETECT_EN_LATER_US);
+	gpio_enable_interrupt(GPIO_BASE_DET_L);
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, base_enable, HOOK_PRIO_DEFAULT);
+
+static void base_disable(void)
+{
+	/*
+	 * Disable power to base and update the base dectect status,
+	 * so the next startup will initialize a correct state
+	 * and notify AP.
+	 */
+	base_detect_change(current_base_status);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, base_disable, HOOK_PRIO_DEFAULT);
+
+static void base_init(void)
+{
+	/*
+	 * If we jumped to this image and chipset is already in S0, enable
+	 * base.
+	 */
+	if (system_jumped_late() && chipset_in_state(CHIPSET_STATE_ON))
+		base_enable();
+}
+DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT + 1);
+
+void base_force_state(enum ec_set_base_state_cmd state)
+{
+	if (state == EC_SET_BASE_STATE_ATTACH) {
+		gpio_disable_interrupt(GPIO_BASE_DET_L);
+		base_detect_change(BASE_CONNECTED);
+		CPRINTS("BD forced connected");
+	} else if (state == EC_SET_BASE_STATE_DETACH) {
+		gpio_disable_interrupt(GPIO_BASE_DET_L);
+		base_detect_change(BASE_DISCONNECTED);
+		CPRINTS("BD forced disconnected");
+	} else {
+		base_enable();
+		CPRINTS("BD forced reset");
+	}
+}
diff --git a/board/mrbland/battery.c b/board/mrbland/battery.c
new file mode 100644
index 0000000000..d6dda523be
--- /dev/null
+++ b/board/mrbland/battery.c
@@ -0,0 +1,129 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "common.h"
+#include "util.h"
+
+/*
+ * Battery info for all mrbland battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+
+const struct board_batt_params board_battery_info[] = {
+	/* Celxpert L21C2PG1 */
+	[BATTERY_L21C2PG1] = {
+		.fuel_gauge = {
+			.manuf_name = "Celxpert",
+			.device_name = "LNV-5B11F38374",
+			.ship_mode = {
+				.reg_addr = 0x34,
+				.reg_data = { 0x0000, 0x1000 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x34,
+				.reg_mask = 0x0100,
+				.disconnect_val = 0x0,
+			}
+		},
+		.batt_info = {
+			.voltage_max            = 8800, /* mV */
+			.voltage_normal         = 7680, /* mV */
+			.voltage_min            = 6000, /* mV */
+			.precharge_current      = 384,  /* mA */
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 50,
+			.charging_min_c         = 0,
+			.charging_max_c         = 60,
+			.discharging_min_c      = -20,
+			.discharging_max_c      = 60,
+			.vendor_param_start     = 0x70,
+		},
+	},
+	/* Sunwoda L21D2PG1 */
+	[BATTERY_L21D2PG1] = {
+		.fuel_gauge = {
+			.manuf_name = "Sunwoda",
+			.device_name = "LNV-5B11F38370",
+			.ship_mode = {
+				.reg_addr = 0x34,
+				.reg_data = { 0x0000, 0x1000 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x34,
+				.reg_mask = 0x0100,
+				.disconnect_val = 0x0,
+			}
+		},
+		.batt_info = {
+			.voltage_max            = 8800, /* mV */
+			.voltage_normal         = 7680, /* mV */
+			.voltage_min            = 6000, /* mV */
+			.precharge_current      = 200,  /* mA */
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 50,
+			.charging_min_c         = 0,
+			.charging_max_c         = 63,
+			.discharging_min_c      = -20,
+			.discharging_max_c      = 63,
+			.vendor_param_start     = 0x70,
+		},
+	},
+	/* SMP L21M2PG1 */
+	[BATTERY_L21M2PG1] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP",
+			.device_name = "LNV-5B11F38381",
+			.ship_mode = {
+				.reg_addr = 0x34,
+				.reg_data = { 0x0000, 0x1000 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x34,
+				.reg_mask = 0x0100,
+				.disconnect_val = 0x0,
+			}
+		},
+		.batt_info = {
+			.voltage_max            = 8800, /* mV */
+			.voltage_normal         = 7680, /* mV */
+			.voltage_min            = 6000, /* mV */
+			.precharge_current      = 128,  /* mA */
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 50,
+			.charging_min_c         = 0,
+			.charging_max_c         = 60,
+			.discharging_min_c      = -20,
+			.discharging_max_c      = 60,
+			.vendor_param_start     = 0x70,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_L21D2PG1;
diff --git a/board/mrbland/board.c b/board/mrbland/board.c
new file mode 100644
index 0000000000..c078d29ef7
--- /dev/null
+++ b/board/mrbland/board.c
@@ -0,0 +1,614 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Mrbland board-specific configuration */
+
+#include "adc_chip.h"
+#include "button.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "common.h"
+#include "driver/accel_bma2x2.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "driver/accelgyro_icm42607.h"
+#include "driver/accelgyro_icm_common.h"
+#include "driver/ln9310.h"
+#include "driver/ppc/sn5s330.h"
+#include "driver/tcpm/ps8xxx.h"
+#include "driver/tcpm/tcpci.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "keyboard_mkbp.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "peripheral_charger.h"
+#include "pi3usb9201.h"
+#include "power.h"
+#include "power/qcom.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "queue.h"
+#include "shi_chip.h"
+#include "switch.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "usbc_ppc.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+#define KS_DEBOUNCE_US (30 * MSEC) /* Debounce time for kickstand switch */
+
+/* Forward declaration */
+static void tcpc_alert_event(enum gpio_signal signal);
+static void usb0_evt(enum gpio_signal signal);
+static void ppc_interrupt(enum gpio_signal signal);
+static void board_connect_c0_sbu(enum gpio_signal s);
+static void switchcap_interrupt(enum gpio_signal signal);
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* GPIO Interrupt Handlers */
+static void tcpc_alert_event(enum gpio_signal signal)
+{
+	int port = -1;
+
+	switch (signal) {
+	case GPIO_USB_C0_PD_INT_ODL:
+		port = 0;
+		break;
+	default:
+		return;
+	}
+
+	schedule_deferred_pd_interrupt(port);
+}
+
+static void usb0_evt(enum gpio_signal signal)
+{
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+
+static void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_SWCTL_INT_ODL:
+		sn5s330_interrupt(0);
+		break;
+	default:
+		break;
+	}
+}
+
+static void board_connect_c0_sbu_deferred(void)
+{
+	/*
+	 * If CCD_MODE_ODL asserts, it means there's a debug accessory connected
+	 * and we should enable the SBU FETs.
+	 */
+	ppc_set_sbu(0, 1);
+}
+DECLARE_DEFERRED(board_connect_c0_sbu_deferred);
+
+static void board_connect_c0_sbu(enum gpio_signal s)
+{
+	hook_call_deferred(&board_connect_c0_sbu_deferred_data, 0);
+}
+
+static void switchcap_interrupt(enum gpio_signal signal)
+{
+	ln9310_interrupt(signal);
+}
+
+/* I2C port map */
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_POWER_SCL,
+	  .sda = GPIO_EC_I2C_POWER_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C0_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C0_PD_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_EEPROM_SCL,
+	  .sda = GPIO_EC_I2C_EEPROM_SDA },
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_SENSOR_SCL,
+	  .sda = GPIO_EC_I2C_SENSOR_SDA },
+};
+
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	/* Measure VBUS through a 1/10 voltage divider */
+	[ADC_VBUS] = { "VBUS", NPCX_ADC_CH1, ADC_MAX_VOLT * 10,
+		       ADC_READ_MAX + 1, 0 },
+	/*
+	 * Adapter current output or battery charging/discharging current (uV)
+	 * 18x amplification on charger side.
+	 */
+	[ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH2, ADC_MAX_VOLT * 1000 / 18,
+			    ADC_READ_MAX + 1, 0 },
+	/*
+	 * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read
+	 * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and
+	 * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we
+	 * only divide by 2 (enough to avoid precision issues).
+	 */
+	[ADC_PSYS] = { "PSYS", NPCX_ADC_CH3,
+		       ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), 2, 0 },
+	/* Base detection */
+	[ADC_BASE_DET] = { "BASE_DET", NPCX_ADC_CH5, ADC_MAX_VOLT,
+			   ADC_READ_MAX + 1, 0 },
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+const struct pwm_t pwm_channels[] = {
+	/* TODO(waihong): Assign a proper frequency. */
+	[PWM_CH_DISPLIGHT] = { .channel = 5, .flags = 0, .freq = 4800 },
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+/* LN9310 switchcap */
+const struct ln9310_config_t ln9310_config = {
+	.i2c_port = I2C_PORT_POWER,
+	.i2c_addr_flags = LN9310_I2C_ADDR_0_FLAGS,
+};
+
+/* Power Path Controller */
+struct ppc_config_t ppc_chips[] = {
+	{ .i2c_port = I2C_PORT_TCPC0,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
+};
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/* TCPC mux configuration */
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TCPC0,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+	},
+};
+
+/*
+ * Port-0/1 USB mux driver.
+ *
+ * The USB mux is handled by TCPC chip and the HPD update is through a GPIO
+ * to AP. But the TCPC chip is also needed to know the HPD status; otherwise,
+ * the mux misbehaves.
+ */
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
+	},
+};
+
+/* BC1.2 */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	{
+		.i2c_port = I2C_PORT_EEPROM,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+};
+
+/* Mutexes */
+static struct mutex g_lid_mutex;
+
+static struct bmi_drv_data_t g_bmi160_data;
+static struct icm_drv_data_t g_icm42607_data;
+
+enum lid_accelgyro_type {
+	LID_GYRO_NONE = 0,
+	LID_GYRO_BMI160 = 1,
+	LID_GYRO_ICM42607 = 2,
+};
+
+static enum lid_accelgyro_type lid_accelgyro_config;
+
+/* Matrix to rotate accelerometer into standard reference frame */
+const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+				      { 0, FLOAT_TO_FP(1), 0 },
+				      { 0, 0, FLOAT_TO_FP(1) } };
+
+const mat33_fp_t lid_standard_ref_icm42607 = { { 0, FLOAT_TO_FP(-1), 0 },
+					       { FLOAT_TO_FP(1), 0, 0 },
+					       { 0, 0, FLOAT_TO_FP(1) } };
+
+struct motion_sensor_t icm42607_lid_accel = {
+	.name = "Lid Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM42607,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_LID,
+	.drv = &icm42607_drv,
+	.mutex = &g_lid_mutex,
+	.drv_data = &g_icm42607_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
+	.rot_standard_ref = &lid_standard_ref_icm42607,
+	.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
+	.min_frequency = ICM42607_ACCEL_MIN_FREQ,
+	.max_frequency = ICM42607_ACCEL_MAX_FREQ,
+	.config = {
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	},
+};
+
+struct motion_sensor_t icm42607_lid_gyro = {
+	.name = "Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM42607,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_LID,
+	.drv = &icm42607_drv,
+	.mutex = &g_lid_mutex,
+	.drv_data = &g_icm42607_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &lid_standard_ref_icm42607,
+	.min_frequency = ICM42607_GYRO_MIN_FREQ,
+	.max_frequency = ICM42607_GYRO_MAX_FREQ,
+};
+
+struct motion_sensor_t motion_sensors[] = {
+	/*
+	 * Note: bmi160: supports accelerometer and gyro sensor
+	 * Requirement: accelerometer sensor must init before gyro sensor
+	 * DO NOT change the order of the following table.
+	 */
+	[LID_ACCEL] = {
+	 .name = "Lid Accel",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_BMI160,
+	 .type = MOTIONSENSE_TYPE_ACCEL,
+	 .location = MOTIONSENSE_LOC_LID,
+	 .drv = &bmi160_drv,
+	 .mutex = &g_lid_mutex,
+	 .drv_data = &g_bmi160_data,
+	 .port = I2C_PORT_SENSOR,
+	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+	 .rot_standard_ref = &lid_standard_ref,
+	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
+	 .min_frequency = BMI_ACCEL_MIN_FREQ,
+	 .max_frequency = BMI_ACCEL_MAX_FREQ,
+	 .config = {
+		 [SENSOR_CONFIG_EC_S0] = {
+			 .odr = 10000 | ROUND_UP_FLAG,
+		 },
+	 },
+	},
+	[LID_GYRO] = {
+	 .name = "Gyro",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_BMI160,
+	 .type = MOTIONSENSE_TYPE_GYRO,
+	 .location = MOTIONSENSE_LOC_LID,
+	 .drv = &bmi160_drv,
+	 .mutex = &g_lid_mutex,
+	 .drv_data = &g_bmi160_data,
+	 .port = I2C_PORT_SENSOR,
+	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+	 .default_range = 1000, /* dps */
+	 .rot_standard_ref = &lid_standard_ref,
+	 .min_frequency = BMI_GYRO_MIN_FREQ,
+	 .max_frequency = BMI_GYRO_MAX_FREQ,
+	},
+};
+const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+static void board_detect_motionsensor(void)
+{
+	int val = -1;
+
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return;
+	if (lid_accelgyro_config != LID_GYRO_NONE)
+		return;
+
+	/* Check base accelgyro chip */
+	icm_read8(&icm42607_lid_accel, ICM42607_REG_WHO_AM_I, &val);
+	if (val == ICM42607_CHIP_ICM42607P) {
+		motion_sensors[LID_ACCEL] = icm42607_lid_accel;
+		motion_sensors[LID_GYRO] = icm42607_lid_gyro;
+		lid_accelgyro_config = LID_GYRO_ICM42607;
+		CPRINTS("LID Accelgyro: ICM42607");
+	} else {
+		lid_accelgyro_config = LID_GYRO_BMI160;
+		CPRINTS("LID Accelgyro: BMI160");
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_detect_motionsensor,
+	     HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_INIT, board_detect_motionsensor, HOOK_PRIO_DEFAULT + 1);
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	switch (lid_accelgyro_config) {
+	case LID_GYRO_ICM42607:
+		icm42607_interrupt(signal);
+		break;
+	case LID_GYRO_BMI160:
+	default:
+		bmi160_interrupt(signal);
+		break;
+	}
+}
+
+enum battery_cell_type board_get_battery_cell_type(void)
+{
+	return BATTERY_CELL_TYPE_2S;
+}
+
+static void board_switchcap_init(void)
+{
+	CPRINTS("Use switchcap: LN9310");
+
+	/* Configure and enable interrupt for LN9310 */
+	gpio_set_flags(GPIO_SWITCHCAP_PG_INT_L, GPIO_INT_FALLING);
+	gpio_enable_interrupt(GPIO_SWITCHCAP_PG_INT_L);
+
+	/* Only configure the switchcap if not sysjump */
+	if (!system_jumped_late())
+		ln9310_init();
+}
+
+/* Initialize board. */
+static void board_init(void)
+{
+	/* Enable BC1.2 interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_L);
+	gpio_enable_interrupt(GPIO_ACCEL_GYRO_INT_L);
+
+	/*
+	 * The H1 SBU line for CCD are behind PPC chip. The PPC internal FETs
+	 * for SBU may be disconnected after DP alt mode is off. Should enable
+	 * the CCD_MODE_ODL interrupt to make sure the SBU FETs are connected.
+	 */
+	gpio_enable_interrupt(GPIO_CCD_MODE_ODL);
+
+	/* Set the backlight duty cycle to 0. AP will override it later. */
+	pwm_set_duty(PWM_CH_DISPLIGHT, 0);
+
+	board_switchcap_init();
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+__overridable uint16_t board_get_ps8xxx_product_id(int port)
+{
+	if (check_ps8755_chip(port))
+		return PS8755_PRODUCT_ID;
+
+	return PS8805_PRODUCT_ID;
+}
+
+void board_tcpc_init(void)
+{
+	/* Only reset TCPC if not sysjump */
+	if (!system_jumped_late()) {
+		/* TODO(crosbug.com/p/61098): How long do we need to wait? */
+		board_reset_pd_mcu();
+	}
+
+	/* Enable PPC interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_SWCTL_INT_ODL);
+
+	/* Enable TCPC interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
+
+	/*
+	 * Initialize HPD to low; after sysjump SOC needs to see
+	 * HPD pulse to enable video path
+	 */
+	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
+		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
+
+void board_hibernate(void)
+{
+	int i;
+
+	/*
+	 * Sensors are unpowered in hibernate. Apply PD to the
+	 * interrupt lines such that they don't float.
+	 */
+	gpio_set_flags(GPIO_ACCEL_GYRO_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
+
+	/*
+	 * Board rev 1+ has the hardware fix. Don't need the following
+	 * workaround.
+	 */
+	if (system_get_board_version() >= 1)
+		return;
+
+	/*
+	 * Enable the PPC power sink path before EC enters hibernate;
+	 * otherwise, ACOK won't go High and can't wake EC up. Check the
+	 * bug b/170324206 for details.
+	 */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
+		ppc_vbus_sink_enable(i, 1);
+}
+
+/* Called on AP S0 -> S3 transition */
+static void board_chipset_suspend(void)
+{
+	/*
+	 * Turn off display backlight in S3. AP has its own control. The EC's
+	 * and the AP's will be AND'ed together in hardware.
+	 */
+	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 0);
+	pwm_enable(PWM_CH_DISPLIGHT, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S3 -> S0 transition */
+static void board_chipset_resume(void)
+{
+	/* Turn on display and keyboard backlight in S0. */
+	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 1);
+	if (pwm_get_duty(PWM_CH_DISPLIGHT))
+		pwm_enable(PWM_CH_DISPLIGHT, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
+
+void board_set_switchcap_power(int enable)
+{
+	gpio_set_level(GPIO_SWITCHCAP_ON_L, !enable);
+	ln9310_software_enable(enable);
+}
+
+int board_is_switchcap_enabled(void)
+{
+	return !gpio_get_level(GPIO_SWITCHCAP_ON_L);
+}
+
+int board_is_switchcap_power_good(void)
+{
+	return ln9310_power_good();
+}
+
+void board_reset_pd_mcu(void)
+{
+	cprints(CC_USB, "Resetting TCPCs...");
+	cflush();
+
+	gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
+	msleep(PS8XXX_RESET_DELAY_MS);
+	gpio_set_level(GPIO_USB_C0_PD_RST_L, 1);
+}
+
+void board_set_tcpc_power_mode(int port, int mode)
+{
+	/* Ignore the "mode" to turn the chip on.  We can only do a reset. */
+	if (mode)
+		return;
+
+	board_reset_pd_mcu();
+}
+
+int board_vbus_sink_enable(int port, int enable)
+{
+	/* Both ports are controlled by PPC SN5S330 */
+	return ppc_vbus_sink_enable(port, enable);
+}
+
+int board_is_sourcing_vbus(int port)
+{
+	/* Both ports are controlled by PPC SN5S330 */
+	return ppc_is_sourcing_vbus(port);
+}
+
+void board_overcurrent_event(int port, int is_overcurrented)
+{
+	/* TODO(b/120231371): Notify AP */
+	CPRINTS("p%d: overcurrent!", port);
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int i;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTS("Disabling all charging port");
+
+		/* Disable all ports. */
+		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (board_vbus_sink_enable(i, 0))
+				CPRINTS("Disabling p%d sink path failed.", i);
+		}
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (board_is_sourcing_vbus(port)) {
+		CPRINTS("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTS("New charge port: p%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		if (i == port)
+			continue;
+
+		if (board_vbus_sink_enable(i, 0))
+			CPRINTS("p%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (board_vbus_sink_enable(port, 1)) {
+		CPRINTS("p%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
+{
+	/*
+	 * Ignore lower charge ceiling on PD transition if our battery is
+	 * critical, as we may brownout.
+	 */
+	if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 &&
+	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
+		CPRINTS("Using max ilim %d", max_ma);
+		charge_ma = max_ma;
+	}
+
+	charge_set_input_current_limit(charge_ma, charge_mv);
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
+		if (gpio_get_level(GPIO_USB_C0_PD_RST_L))
+			status |= PD_STATUS_TCPC_ALERT_0;
+
+	return status;
+}
diff --git a/board/mrbland/board.h b/board/mrbland/board.h
new file mode 100644
index 0000000000..25b1805e2a
--- /dev/null
+++ b/board/mrbland/board.h
@@ -0,0 +1,112 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Mrbland board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "baseboard.h"
+
+#define CONFIG_BUTTON_TRIGGERED_RECOVERY
+
+/* Internal SPI flash on NPCX7 */
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */
+
+/* Switchcap */
+#define CONFIG_LN9310
+
+/* Battery */
+#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
+#define CONFIG_BATTERY_REVIVE_DISCONNECT
+#define CONFIG_BATTERY_FUEL_GAUGE
+#define CONFIG_BATTERY_VENDOR_PARAM
+
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 5
+
+/* Enable PD3.0 */
+#define CONFIG_USB_PD_REV30
+
+/* BC 1.2 Charger */
+#define CONFIG_BC12_DETECT_PI3USB9201
+
+/* USB */
+#define CONFIG_USB_PD_TCPM_MULTI_PS8XXX
+#define CONFIG_USB_PD_TCPM_PS8755
+#define CONFIG_USB_PD_TCPM_PS8805
+#define CONFIG_USB_PD_TCPM_PS8805_FORCE_DID
+#define CONFIG_USBC_PPC_SN5S330
+#define CONFIG_USB_PD_PORT_MAX_COUNT 1
+
+/* I2C */
+#undef I2C_PORT_TCPC0
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT2_0
+
+/* Lid accel/gyro */
+#define CONFIG_ACCELGYRO_BMI160
+#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
+#define OPT3001_I2C_ADDR_FLAGS OPT3001_I2C_ADDR1_FLAGS
+#define CONFIG_ACCELGYRO_ICM42607
+#define CONFIG_ACCELGYRO_ICM42607_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
+
+#define CONFIG_TABLET_MODE
+#define CONFIG_TABLET_MODE_SWITCH
+#define CONFIG_FRONT_PROXIMITY_SWITCH
+
+#define CONFIG_DETACHABLE_BASE
+#define CONFIG_BASE_ATTACHED_SWITCH
+
+/* GPIO alias */
+#define GPIO_AC_PRESENT GPIO_CHG_ACOK_OD
+#define GPIO_WP_L GPIO_EC_FLASH_WP_ODL
+#define GPIO_PMIC_RESIN_L GPIO_PM845_RESIN_L
+#define GPIO_SWITCHCAP_PG_INT_L GPIO_LN9310_INT
+
+#define CONFIG_MKBP_INPUT_DEVICES
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum adc_channel {
+	ADC_VBUS,
+	ADC_AMON_BMON,
+	ADC_PSYS,
+	ADC_BASE_DET,
+	ADC_CH_COUNT
+};
+
+/* Motion sensors */
+enum sensor_id {
+	LID_ACCEL = 0,
+	LID_GYRO,
+	SENSOR_COUNT,
+};
+
+enum pwm_channel { PWM_CH_DISPLIGHT = 0, PWM_CH_COUNT };
+
+/* List of possible batteries */
+enum battery_type {
+	BATTERY_L21C2PG1,
+	BATTERY_L21D2PG1,
+	BATTERY_L21M2PG1,
+	BATTERY_TYPE_COUNT,
+};
+
+/* Reset all TCPCs. */
+void board_reset_pd_mcu(void);
+void board_set_tcpc_power_mode(int port, int mode);
+/* Base detection */
+void base_detect_interrupt(enum gpio_signal signal);
+
+void motion_interrupt(enum gpio_signal signal);
+
+#endif /* !defined(__ASSEMBLER__) */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/mrbland/build.mk b/board/mrbland/build.mk
new file mode 100644
index 0000000000..363ef59a16
--- /dev/null
+++ b/board/mrbland/build.mk
@@ -0,0 +1,14 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx7
+CHIP_VARIANT:=npcx7m6fc
+BASEBOARD:=trogdor
+
+board-y=battery.o board.o led.o base_detect.o usbc_config.o
diff --git a/board/mrbland/ec.tasklist b/board/mrbland/ec.tasklist
new file mode 100644
index 0000000000..fc40a8b684
--- /dev/null
+++ b/board/mrbland/ec.tasklist
@@ -0,0 +1,19 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE)
diff --git a/board/mrbland/gpio.inc b/board/mrbland/gpio.inc
new file mode 100644
index 0000000000..b5ff32f0b8
--- /dev/null
+++ b/board/mrbland/gpio.inc
@@ -0,0 +1,195 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+/* USB-C interrupts */
+GPIO_INT(USB_C0_PD_INT_ODL,    PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-0 TCPC */
+GPIO_INT(USB_C0_SWCTL_INT_ODL, PIN(4, 0), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-0 PPC */
+GPIO_INT(USB_C0_BC12_INT_L,    PIN(8, 2), GPIO_INT_FALLING | GPIO_PULL_UP, usb0_evt)  /* Interrupt from port-0 BC1.2 */
+
+/* System interrupts */
+GPIO_INT(CHG_ACOK_OD,       PIN(0, 0), GPIO_INT_BOTH, extpower_interrupt)  /* ACOK */
+GPIO_INT(CCD_MODE_ODL,      PIN(E, 3), GPIO_INT_FALLING, board_connect_c0_sbu)  /* Case Closed Debug Mode */
+GPIO_INT(EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)  /* Power button */
+GPIO_INT(EC_VOLDN_BTN_ODL,  PIN(7, 0), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Down button */
+GPIO_INT(EC_VOLUP_BTN_ODL,  PIN(F, 2), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Up button */
+GPIO_INT(EC_FLASH_WP_ODL,   PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)  /* Write protection */
+GPIO_INT(LID_OPEN_EC,       PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)  /* Lid open */
+GPIO_INT(AP_RST_L,          PIN(C, 1), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_ap_rst_interrupt)  /* PMIC to signal AP reset */
+GPIO_INT(PS_HOLD,           PIN(A, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, power_signal_interrupt)  /* Indicate when AP triggers reset/shutdown */
+GPIO_INT(AP_SUSPEND,        PIN(5, 7), GPIO_INT_BOTH, power_signal_interrupt)  /* Suspend signal from PMIC */
+GPIO_INT(DEPRECATED_AP_RST_REQ, PIN(C, 2), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V, power_signal_interrupt) /* Deprecated AP initiated reset indicator */
+
+/*
+ * When switch-cap is off, the POWER_GOOD signal is floating. Need a pull-down
+ * to make it low. Overload the interrupt function chipset_warm_reset_interrupt
+ * for not only signalling power_signal_interrupt but also handling the logic
+ * of WARM_RESET_L which is pulled-up by the same rail of POWER_GOOD.
+ */
+GPIO_INT(POWER_GOOD,        PIN(5, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, chipset_power_good_interrupt)  /* SRC_PP1800_S10A from PMIC */
+GPIO_INT(WARM_RESET_L,      PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_warm_reset_interrupt)  /* AP warm reset */
+GPIO_INT(AP_EC_SPI_CS_L,    PIN(5, 3), GPIO_INT_FALLING | GPIO_PULL_DOWN, shi_cs_event)  /* EC SPI Chip Select */
+
+GPIO_INT(BASE_DET_L,        PIN(3, 7), GPIO_INT_BOTH, base_detect_interrupt)  /* Detachable base attached? */
+
+/* Sensor interrupts */
+GPIO_INT(ACCEL_GYRO_INT_L,  PIN(A, 0), GPIO_INT_FALLING, motion_interrupt)  /* Accelerometer/gyro interrupt */
+
+/* Switchcap, for LN9310, it is the interrupt line of LN9310. */
+GPIO_INT(LN9310_INT,      PIN(E, 2), GPIO_INT_FALLING, switchcap_interrupt)
+
+/*
+ * EC_RST_ODL acts as a wake source from hibernate mode. However, it does not
+ * need to be an interrupt for normal EC operations. Simply set it an INPUT.
+ */
+GPIO(EC_RST_ODL,            PIN(0, 2), GPIO_INPUT)     /* EC reset */
+GPIO(EC_ENTERING_RW,        PIN(E, 1), GPIO_OUT_LOW)   /* Indicate when EC is entering RW code */
+GPIO(EC_BATT_PRES_ODL,      PIN(E, 5), GPIO_INPUT)     /* Battery Present */
+
+/* PMIC/AP 1.8V */
+GPIO(PM845_RESIN_L,         PIN(3, 2), GPIO_ODR_HIGH)  /* PMIC reset trigger */
+GPIO(PMIC_KPD_PWR_ODL,      PIN(D, 6), GPIO_ODR_HIGH)  /* PMIC power button */
+GPIO(EC_INT_L,              PIN(A, 2), GPIO_ODR_HIGH)  /* Interrupt line between AP and EC */
+GPIO(QSIP_ON,               PIN(5, 0), GPIO_OUT_LOW)   /* Not used, for non-switchcap testing */
+
+/* Power enables */
+GPIO(HIBERNATE_L,           PIN(5, 2), GPIO_ODR_HIGH)  /* EC hibernate */
+GPIO(SWITCHCAP_ON_L,        PIN(D, 5), GPIO_ODR_HIGH)  /* Enable switch cap */
+GPIO(EN_PP3300_A,           PIN(A, 6), GPIO_OUT_LOW)   /* Enable PP3300 */
+GPIO(EN_PP5000_A,           PIN(6, 7), GPIO_OUT_LOW)   /* Enable PP5000 */
+GPIO(EC_BL_DISABLE_L,       PIN(B, 6), GPIO_OUT_LOW)   /* Backlight disable signal from EC */
+
+/* Base detection */
+GPIO(EN_BASE,               PIN(0, 4), GPIO_OUT_LOW)   /* Enable power to detachable base */
+
+/* POGO */
+GPIO(POGO_VBUS_PRESENT,     PIN(6, 2), GPIO_INPUT)    /* POGO PIN */
+
+/* USB-C */
+GPIO(USB_C0_PD_RST_L,       PIN(E, 4), GPIO_ODR_HIGH)  /* Port-0 TCPC chip reset, actually Open-Drain */
+GPIO(DP_MUX_OE_L,           PIN(9, 6), GPIO_ODR_HIGH)  /* DP mux enable, actually Open-Drain */
+GPIO(DP_MUX_SEL,            PIN(4, 5), GPIO_OUT_LOW)   /* DP mux selection: L:C0, H:C1 */
+GPIO(DP_HOT_PLUG_DET,       PIN(9, 5), GPIO_OUT_LOW)   /* DP HPD to AP */
+
+/* LEDs */
+GPIO(EC_CHG_LED_R_C0,       PIN(C, 3), GPIO_OUT_LOW)
+GPIO(EC_CHG_LED_G_C0,       PIN(C, 4), GPIO_OUT_LOW)
+GPIO(EC_PWRBTN_LED,         PIN(7, 3), GPIO_OUT_LOW)
+
+/*
+ * SPI host interface - enable PDs by default. These will be made functional
+ * by the SHI driver when the AP powers up, and restored back to GPIO when
+ * the AP powers down.
+ */
+GPIO(AP_EC_SPI_MOSI,        PIN(4, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(AP_EC_SPI_MISO,        PIN(4, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(AP_EC_SPI_CLK,         PIN(5, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+
+/* PWM */
+GPIO(EDP_BKLTCTL,           PIN(B, 7), GPIO_INPUT)     /* PWM5 */
+GPIO(WCAM_EC_VSYNC,         PIN(C, 0), GPIO_INPUT)     /* PWM6 */
+GPIO(FCAM_EC_VSYNC,         PIN(6, 0), GPIO_INPUT)     /* PWM7 */
+
+/* ADC */
+GPIO(PPVAR_BOOSTIN_SENSE,   PIN(4, 4), GPIO_INPUT)     /* ADC1 */
+GPIO(CHARGER_IADP,          PIN(4, 3), GPIO_INPUT)     /* ADC2 */
+GPIO(CHARGER_PMON,          PIN(4, 2), GPIO_INPUT)     /* ADC3 */
+
+/* I2C */
+GPIO(EC_I2C_POWER_SCL,      PIN(B, 5), GPIO_INPUT)
+GPIO(EC_I2C_POWER_SDA,      PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_PD_SCL,  PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_PD_SDA,  PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SCL,     PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SDA,     PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,     PIN(B, 3), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SENSOR_SDA,     PIN(B, 2), GPIO_INPUT | GPIO_SEL_1P8V)
+
+/* Board/SKU IDs */
+GPIO(BRD_ID0,               PIN(C, 7), GPIO_INPUT)
+GPIO(BRD_ID1,               PIN(9, 3), GPIO_INPUT)
+GPIO(BRD_ID2,               PIN(6, 3), GPIO_INPUT)
+GPIO(SKU_ID0,               PIN(F, 0), GPIO_INPUT)
+GPIO(SKU_ID1,               PIN(4, 1), GPIO_INPUT)
+GPIO(SKU_ID2,               PIN(D, 4), GPIO_INPUT)
+
+/* Special straps */
+GPIO(ARM_X86,               PIN(6, 6), GPIO_OUT_LOW)  /* NC, low for power saving */
+
+/* Unused GPIOs, NC. Apply PU for power saving */
+UNUSED(PIN(5, 1))
+UNUSED(PIN(F, 3))
+UNUSED(PIN(3, 1))
+UNUSED(PIN(3, 0))
+UNUSED(PIN(2, 7))
+UNUSED(PIN(2, 6))
+UNUSED(PIN(2, 5))
+UNUSED(PIN(2, 4))
+UNUSED(PIN(2, 3))
+UNUSED(PIN(2, 2))
+UNUSED(PIN(2, 1))
+UNUSED(PIN(2, 0))
+UNUSED(PIN(1, 7))
+UNUSED(PIN(1, 6))
+UNUSED(PIN(1, 5))
+UNUSED(PIN(1, 4))
+UNUSED(PIN(1, 3))
+UNUSED(PIN(1, 2))
+UNUSED(PIN(1, 1))
+UNUSED(PIN(1, 0))
+UNUSED(PIN(0, 7))
+UNUSED(PIN(0, 6))
+UNUSED(PIN(0, 5))
+UNUSED(PIN(9, 4))
+UNUSED(PIN(9, 7))
+UNUSED(PIN(A, 7))
+UNUSED(PIN(B, 0))
+UNUSED(PIN(A, 5))
+UNUSED(PIN(3, 5))
+UNUSED(PIN(7, 2))
+UNUSED(PIN(8, 1))
+UNUSED(PIN(7, 6))
+UNUSED(PIN(3, 4))
+UNUSED(PIN(C, 5))
+UNUSED(PIN(C, 6))
+UNUSED(PIN(A, 3))
+UNUSED(PIN(8, 3))
+UNUSED(PIN(B, 1))
+UNUSED(PIN(5, 6))
+UNUSED(PIN(8, 0))
+UNUSED(PIN(D, 0))
+UNUSED(PIN(D, 1))
+UNUSED(PIN(D, 3))
+UNUSED(PIN(7, 5))
+UNUSED(PIN(8, 6))
+UNUSED(PIN(7, 4))
+UNUSED(PIN(D, 7))
+UNUSED(PIN(8, 5))
+UNUSED(PIN(E, 0))
+UNUSED(PIN(0, 3))
+UNUSED(PIN(6, 1))
+UNUSED(PIN(F, 1))
+UNUSED(PIN(9, 0))
+UNUSED(PIN(8, 7))
+
+/* Alternate functions GPIO definitions */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)            /* UART (GPIO64/65) */
+ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0)             /* I2C0 (GPIOB4/B5) */
+ALTERNATE(PIN_MASK(9, 0x06), 1, MODULE_I2C, 0)             /* I2C2 (GPIO91/92) */
+ALTERNATE(PIN_MASK(3, 0x48), 1, MODULE_I2C, 0)             /* I2C5 (GPIO33/36) */
+ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, GPIO_SEL_1P8V) /* I2C7 (GPIOB2/B3) - 1.8V */
+ALTERNATE(PIN_MASK(4, 0x1C), 0, MODULE_ADC, 0)             /* ADC1 (GPIO44), ADC2 (GPIO43), ADC3 (GPIO42) */
+ALTERNATE(PIN_MASK(4, 0xC0), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SDO (GPIO47), SHI_SDI (GPIO46) */
+ALTERNATE(PIN_MASK(5, 0x28), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SCLK (GPIO55), SHI_CS# (GPIO53) */
+ALTERNATE(PIN_MASK(B, 0x80), 1, MODULE_PWM, 0)             /* PWM5 (GPIOB7) - EDP_BKLTCTL */
+/* TODO(Camera?) should have a poper config for this, PWM or not */
+ALTERNATE(PIN_MASK(C, 0x01), 1, MODULE_PWM, 0)             /* PWM6 (GPIOC0) - WCAM_EC_VSYNC */
+ALTERNATE(PIN_MASK(6, 0x01), 1, MODULE_PWM, 0)             /* PWM7 (GPIO60) - FCAM_EC_VSYNC */
+
+
diff --git a/board/mrbland/led.c b/board/mrbland/led.c
new file mode 100644
index 0000000000..3eb236e162
--- /dev/null
+++ b/board/mrbland/led.c
@@ -0,0 +1,219 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power and battery LED control.
+ */
+
+#include "battery.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "chipset.h"
+#include "ec_commands.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "led_common.h"
+#include "system.h"
+#include "util.h"
+
+#define LED_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS)
+/* Battery LED blinks every per 400ms */
+#define LED_HALF_ONE_SEC (500 / HOOK_TICK_INTERVAL_MS)
+
+#define BAT_LED_ON 1
+#define BAT_LED_OFF 0
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_BATTERY_LED,
+	EC_LED_ID_POWER_LED,
+};
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+enum led_color {
+	LED_OFF = 0,
+	LED_RED,
+	LED_GREEN,
+	LED_AMBER,
+	LED_WHITE,
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
+};
+
+static void led_set_color_battery(enum led_color color)
+{
+	gpio_set_level(GPIO_EC_CHG_LED_R_C0,
+		       (color == LED_RED) ? BAT_LED_ON : BAT_LED_OFF);
+	gpio_set_level(GPIO_EC_CHG_LED_G_C0,
+		       (color == LED_GREEN) ? BAT_LED_ON : BAT_LED_OFF);
+	if (color == LED_AMBER) {
+		gpio_set_level(GPIO_EC_CHG_LED_R_C0, BAT_LED_ON);
+		gpio_set_level(GPIO_EC_CHG_LED_G_C0, BAT_LED_ON);
+	}
+}
+
+static void led_set_color_power(enum led_color color)
+{
+	gpio_set_level(GPIO_EC_PWRBTN_LED,
+		       (color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF);
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_RED] = 1;
+		brightness_range[EC_LED_COLOR_GREEN] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		if (brightness[EC_LED_COLOR_RED] != 0)
+			led_set_color_battery(LED_RED);
+		else if (brightness[EC_LED_COLOR_GREEN] != 0)
+			led_set_color_battery(LED_GREEN);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(LED_AMBER);
+		else
+			led_set_color_battery(LED_OFF);
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_power(LED_WHITE);
+		else
+			led_set_color_power(LED_OFF);
+	}
+
+	return EC_SUCCESS;
+}
+
+static void board_led_set_battery(void)
+{
+	static int battery_ticks;
+	int color = LED_OFF;
+	int period = 0;
+	int percent = DIV_ROUND_NEAREST(charge_get_display_charge(), 10);
+
+	battery_ticks++;
+
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
+	case LED_PWRS_CHARGE_NEAR_FULL:
+		if (chipset_in_state(CHIPSET_STATE_ON |
+				     CHIPSET_STATE_ANY_SUSPEND |
+				     CHIPSET_STATE_ANY_OFF)) {
+			if (percent <= BATTERY_LEVEL_CRITICAL) {
+				/* battery capa <= 5%, Red */
+				color = LED_RED;
+			} else if (percent > BATTERY_LEVEL_CRITICAL &&
+				   percent < CONFIG_BATT_HOST_FULL_FACTOR) {
+				/* 5% < battery capa < 97%, Orange */
+				color = LED_AMBER;
+			} else {
+				/* battery capa >= 97%, Green */
+				color = LED_GREEN;
+			}
+		}
+		break;
+	case LED_PWRS_DISCHARGE:
+		color = LED_OFF;
+		break;
+	case LED_PWRS_ERROR:
+		/* Battery error, Red on 1sec off 1sec */
+		period = (1 + 1) * LED_ONE_SEC;
+		battery_ticks = battery_ticks % period;
+		if (battery_ticks < 1 * LED_ONE_SEC)
+			color = LED_RED;
+		else
+			color = LED_OFF;
+		break;
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		color = LED_RED;
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		/* Factory mode, Red 2 sec, green 2 sec */
+		period = (2 + 2) * LED_ONE_SEC;
+		battery_ticks = battery_ticks % period;
+		if (battery_ticks < 2 * LED_ONE_SEC)
+			color = LED_RED;
+		else
+			color = LED_GREEN;
+		break;
+	default:
+		/* Other states don't alter LED behavior */
+		break;
+	}
+
+	led_set_color_battery(color);
+}
+
+static void board_led_set_power(void)
+{
+	static int power_ticks;
+	int color = LED_OFF;
+	int period = 0;
+
+	power_ticks++;
+
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
+	case LED_PWRS_CHARGE_NEAR_FULL:
+	case LED_PWRS_DISCHARGE:
+		if (chipset_in_state(CHIPSET_STATE_ON)) {
+			/* S0, White (soild on) */
+			color = LED_WHITE;
+		} else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
+			/* S3, white (3s on 500ms off) */
+			period = 1 * LED_HALF_ONE_SEC + 3 * LED_ONE_SEC;
+			power_ticks = power_ticks % period;
+			if (power_ticks < 3 * LED_ONE_SEC)
+				color = LED_WHITE;
+			else
+				color = LED_OFF;
+		} else if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
+			/* S5, off */
+			color = LED_OFF;
+		}
+		break;
+	default:
+		/* Other states don't alter LED behavior */
+		break;
+	}
+
+	led_set_color_power(color);
+}
+
+/* Called by hook task every TICK */
+static void led_tick(void)
+{
+	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
+		board_led_set_battery();
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		board_led_set_power();
+}
+DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
+
+void led_control(enum ec_led_id led_id, enum ec_led_state state)
+{
+	enum led_color color;
+
+	if ((led_id != EC_LED_ID_RECOVERY_HW_REINIT_LED) &&
+	    (led_id != EC_LED_ID_SYSRQ_DEBUG_LED))
+		return;
+
+	if (state == LED_STATE_RESET) {
+		led_auto_control(EC_LED_ID_BATTERY_LED, 1);
+		board_led_set_battery();
+		return;
+	}
+
+	color = state ? LED_RED : LED_OFF;
+
+	led_auto_control(EC_LED_ID_BATTERY_LED, 0);
+
+	led_set_color_battery(color);
+}
diff --git a/board/mrbland/usbc_config.c b/board/mrbland/usbc_config.c
new file mode 100644
index 0000000000..28f6b7a1c9
--- /dev/null
+++ b/board/mrbland/usbc_config.c
@@ -0,0 +1,61 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Trogdor family-specific USB-C configuration */
+
+#include "charge_state.h"
+#include "charger.h"
+#include "charger/isl923x_public.h"
+#include "console.h"
+#include "usb_pd.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+};
+
+int charger_profile_override(struct charge_state_data *curr)
+{
+	int usb_mv;
+	int port;
+
+	if (curr->state != ST_CHARGE)
+		return 0;
+
+	/* Lower the max requested voltage to 5V when battery is full. */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
+	    !(curr->batt.flags & BATT_FLAG_BAD_STATUS) &&
+	    !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
+	    (curr->batt.status & STATUS_FULLY_CHARGED))
+		usb_mv = 5000;
+	else
+		usb_mv = PD_MAX_VOLTAGE_MV;
+
+	if (pd_get_max_voltage() != usb_mv) {
+		CPRINTS("VBUS limited to %dmV", usb_mv);
+		for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++)
+			pd_set_external_voltage_limit(port, usb_mv);
+	}
+
+	return 0;
+}
+
+enum ec_status charger_profile_override_get_param(uint32_t param,
+						  uint32_t *value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+enum ec_status charger_profile_override_set_param(uint32_t param,
+						  uint32_t value)
+{
+	return EC_RES_INVALID_PARAM;
+}
diff --git a/board/mrbland/vif_override.xml b/board/mrbland/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/mrbland/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/munna/battery.c b/board/munna/battery.c
new file mode 100644
index 0000000000..1f5be3dbe3
--- /dev/null
+++ b/board/munna/battery.c
@@ -0,0 +1,104 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "battery_fuel_gauge.h"
+#include "gpio.h"
+
+const struct board_batt_params board_battery_info[] = {
+	/* LGC L20L3PG2, Gauge IC: RAJ240047A20DNP. */
+	[BATTERY_LGC] = {
+		.fuel_gauge = {
+			.manuf_name = "LGC",
+			.device_name = "L20L3PG2",
+			.ship_mode = {
+				.reg_addr = 0x34,
+				.reg_data = { 0x0000, 0x1000 },
+			},
+			.fet = {
+				.reg_addr = 0x34,
+				.reg_mask = 0x0100,
+				.disconnect_val = 0x0100,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13050,   /* mV */
+			.voltage_normal		= 11400,   /* mV */
+			.voltage_min		= 9000,    /* mV */
+			.precharge_current	= 256,     /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 73,
+		},
+	},
+	/* Sunwoda L20D3PG2, Gauge IC: BQ40Z697A. */
+	[BATTERY_SUNWODA] = {
+		.fuel_gauge = {
+			.manuf_name = "Sunwoda",
+			.device_name = "L20D3PG2",
+			.ship_mode = {
+				.reg_addr = 0x34,
+				.reg_data = { 0x0000, 0x1000 },
+			},
+			.fet = {
+				.reg_addr = 0x34,
+				.reg_mask = 0x0100,
+				.disconnect_val = 0x0100,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13050, /* mV */
+			.voltage_normal		= 11250, /* mV */
+			.voltage_min		= 9000,  /* mV */
+			.precharge_current	= 200,	 /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 60,
+		},
+	},
+
+	/* SIMPLO L20M3PG2, Gauge IC: BQ40Z697A. */
+	[BATTERY_SMP] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP",
+			.device_name = "L20M3PG2",
+			.ship_mode = {
+				.reg_addr = 0x34,
+				.reg_data = { 0x0000, 0x1000 },
+			},
+			.fet = {
+				.reg_addr = 0x34,
+				.reg_mask = 0x0100,
+				.disconnect_val = 0x0100,
+			},
+		},
+		.batt_info = {
+			.voltage_max		= 13050, /* mV */
+			.voltage_normal		= 11250, /* mV */
+			.voltage_min		= 9000,  /* mV */
+			.precharge_current	= 256,   /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 45,
+			.charging_min_c		= 0,
+			.charging_max_c		= 45,
+			.discharging_min_c	= -40,
+			.discharging_max_c	= 73,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_LGC;
+
+enum battery_present battery_hw_present(void)
+{
+	return gpio_get_level(GPIO_EC_BATT_PRES_ODL) ? BP_NO : BP_YES;
+}
diff --git a/board/munna/board.c b/board/munna/board.c
new file mode 100644
index 0000000000..9830869476
--- /dev/null
+++ b/board/munna/board.c
@@ -0,0 +1,595 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc.h"
+#include "backlight.h"
+#include "button.h"
+#include "charge_manager.h"
+#include "charge_ramp.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "driver/accel_lis2dw12.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "driver/battery/max17055.h"
+#include "driver/bc12/pi3usb9201.h"
+#include "driver/charger/isl923x.h"
+#include "driver/tcpm/fusb302.h"
+#include "driver/usb_mux/it5205.h"
+#include "ec_commands.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "i2c.h"
+#include "i2c_bitbang.h"
+#include "it8801.h"
+#include "keyboard_backlight.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "panic.h"
+#include "power.h"
+#include "power_button.h"
+#include "registers.h"
+#include "spi.h"
+#include "system.h"
+#include "task.h"
+#include "tcpm/tcpm.h"
+#include "timer.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd_tcpm.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+static void tcpc_alert_event(enum gpio_signal signal)
+{
+	schedule_deferred_pd_interrupt(0 /* port */);
+}
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/******************************************************************************/
+/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
+const struct adc_t adc_channels[] = {
+	[ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(5) },
+	[ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(15) },
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/******************************************************************************/
+/* I2C ports */
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "typec",
+	  .port = 0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "other",
+	  .port = 2,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+const struct i2c_port_t i2c_bitbang_ports[] = {
+	{ .name = "battery",
+	  .port = 3,
+	  .kbps = 100,
+	  .scl = GPIO_I2C4_SCL,
+	  .sda = GPIO_I2C4_SDA,
+	  .drv = &bitbang_drv },
+};
+const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
+
+#define BC12_I2C_ADDR PI3USB9201_I2C_ADDR_3
+
+/* power signal list.  Must match order of enum power_signal. */
+const struct power_signal_info power_signal_list[] = {
+	{ GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" },
+	{ GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" },
+};
+BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/*
+	 * TODO(b/133200075): Tune this once we have the final performance
+	 * out of the driver and the i2c bus.
+	 */
+	.output_settle_us = 35,
+	.debounce_down_us = 5 * MSEC,
+	.debounce_up_us = 40 * MSEC,
+	.scan_period_us = 10 * MSEC,
+	.min_post_scan_delay_us = 10 * MSEC,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
+		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
+	},
+};
+
+struct ioexpander_config_t ioex_config[CONFIG_IO_EXPANDER_PORT_COUNT] = {
+	[0] = {
+		.i2c_host_port = I2C_PORT_KB_DISCRETE,
+		.i2c_addr_flags = IT8801_I2C_ADDR1,
+		.drv = &it8801_ioexpander_drv,
+	},
+};
+
+/******************************************************************************/
+/* SPI devices */
+const struct spi_device_t spi_devices[] = {
+	{ CONFIG_SPI_ACCEL_PORT, 2, GPIO_EC_SENSOR_SPI_NSS },
+};
+const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
+
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	{
+		.i2c_port = I2C_PORT_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+};
+
+/******************************************************************************/
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TCPC0,
+			.addr_flags = FUSB302_I2C_ADDR_FLAGS,
+		},
+		.drv = &fusb302_tcpm_drv,
+	},
+};
+
+static void board_hpd_status(const struct usb_mux *me, mux_state_t mux_state,
+			     bool *ack_required)
+{
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
+	/*
+	 * svdm_dp_attention() did most of the work, we only need to notify
+	 * host here.
+	 */
+	host_set_single_event(EC_HOST_EVENT_USB_MUX);
+}
+
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+				.hpd_update = &board_hpd_status,
+			},
+	},
+};
+
+/* Charger config.  Start i2c address at 1, update during runtime */
+struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = 2,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+};
+
+/* Board version depends on ADCs, so init i2c port after ADC */
+static void charger_config_complete(void)
+{
+	chg_chips[0].i2c_port = board_get_charger_i2c();
+}
+DECLARE_HOOK(HOOK_INIT, charger_config_complete, HOOK_PRIO_INIT_ADC + 1);
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
+		status |= PD_STATUS_TCPC_ALERT_0;
+
+	return status;
+}
+
+static int force_discharge;
+
+int board_set_active_charge_port(int charge_port)
+{
+	CPRINTS("New chg p%d", charge_port);
+
+	/* ignore all request when discharge mode is on */
+	if (force_discharge && charge_port != CHARGE_PORT_NONE)
+		return EC_SUCCESS;
+
+	switch (charge_port) {
+	case CHARGE_PORT_USB_C:
+		/* Don't charge from a source port */
+		if (board_vbus_source_enabled(charge_port))
+			return -1;
+		break;
+	default:
+		/*
+		 * To ensure the fuel gauge (max17055) is always powered
+		 * even when battery is disconnected, keep VBAT rail on but
+		 * set the charging current to minimum.
+		 */
+		charger_set_current(CHARGER_SOLO, 0);
+		break;
+	}
+
+	return EC_SUCCESS;
+}
+
+int board_discharge_on_ac(int enable)
+{
+	int ret, port;
+
+	if (enable) {
+		port = CHARGE_PORT_NONE;
+	} else {
+		/* restore the charge port state */
+		port = charge_manager_get_override();
+		if (port == OVERRIDE_OFF)
+			port = charge_manager_get_active_charge_port();
+	}
+
+	ret = charger_discharge_on_ac(enable);
+	if (ret)
+		return ret;
+
+	force_discharge = enable;
+	return board_set_active_charge_port(port);
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	/* TODO(b:138352732): read IT8801 GPIO EN_USBC_CHARGE_L */
+	return EC_ERROR_UNIMPLEMENTED;
+}
+
+void bc12_interrupt(enum gpio_signal signal)
+{
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+
+#ifndef VARIANT_KUKUI_NO_SENSORS
+static void board_spi_enable(void)
+{
+	/*
+	 * Pin mux spi peripheral away from emmc, since RO might have
+	 * left them there.
+	 */
+	gpio_config_module(MODULE_SPI_FLASH, 0);
+#ifdef CHIP_FAMILY_STM32L4
+	/* Set I/O speed before AF configured */
+	/* EMMC SPI SLAVE: PB13/14/15 */
+	/* SENSORS SPI controller: PB10, PB12, PC2, PC3 */
+	STM32_GPIO_OSPEEDR(GPIO_B) |= 0xFF300000;
+	STM32_GPIO_OSPEEDR(GPIO_C) |= 0x000000F0;
+
+	/* Enable clocks to SPI2 module. */
+	STM32_RCC_APB1ENR1 |= STM32_RCC_PB1_SPI2;
+
+	/* Reset SPI2 to clear state left over from the emmc slave. */
+	STM32_RCC_APB1RSTR1 |= STM32_RCC_PB1_SPI2;
+	STM32_RCC_APB1RSTR1 &= ~STM32_RCC_PB1_SPI2;
+#else
+	/* Enable clocks to SPI2 module. */
+	STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
+
+	/* Reset SPI2 to clear state left over from the emmc slave. */
+	STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2;
+	STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
+#endif
+	/* Reinitialize spi peripheral. */
+	spi_enable(&spi_devices[0], 1);
+
+	/* Pin mux spi peripheral toward the sensor. */
+	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_spi_enable,
+	     MOTION_SENSE_HOOK_PRIO - 1);
+
+static void board_spi_disable(void)
+{
+	/* Set pins to a state calming the sensor down. */
+	gpio_set_flags(GPIO_EC_SENSOR_SPI_CK, GPIO_OUT_LOW);
+	gpio_set_level(GPIO_EC_SENSOR_SPI_CK, 0);
+	gpio_config_module(MODULE_SPI_CONTROLLER, 0);
+
+	/* Disable spi peripheral and clocks. */
+	spi_enable(&spi_devices[0], 0);
+#ifdef CHIP_FAMILY_STM32L4
+	STM32_RCC_APB1ENR1 &= ~STM32_RCC_PB1_SPI2;
+#else
+	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
+#endif
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_spi_disable,
+	     MOTION_SENSE_HOOK_PRIO + 1);
+#endif /* !VARIANT_KUKUI_NO_SENSORS */
+
+static void board_init(void)
+{
+	/* If the reset cause is external, pulse PMIC force reset. */
+	if (system_get_reset_flags() == EC_RESET_FLAG_RESET_PIN) {
+		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 0);
+		msleep(100);
+		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 1);
+	}
+
+	/* Enable TCPC alert interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
+
+#ifndef VARIANT_KUKUI_NO_SENSORS
+	/* Enable interrupts from BMI160 sensor. */
+	gpio_enable_interrupt(GPIO_ACCEL_INT_ODL);
+
+	/* For some reason we have to do this again in case of sysjump */
+	board_spi_enable();
+#endif /* !VARIANT_KUKUI_NO_SENSORS */
+
+	/* Enable interrupt from PMIC. */
+	gpio_enable_interrupt(GPIO_PMIC_EC_RESETB);
+
+	/* Enable BC12 interrupt */
+	gpio_enable_interrupt(GPIO_BC12_EC_INT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+#ifndef VARIANT_KUKUI_NO_SENSORS
+/* Motion sensors */
+/* Mutexes */
+static struct mutex g_lid_mutex;
+static struct mutex g_base_mutex;
+
+/* Rotation matrixes */
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					      { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
+
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, FLOAT_TO_FP(1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
+
+/* sensor private data */
+/* Lid accel private data */
+static struct stprivate_data g_lis2dwl_data;
+/* Base accel private data */
+static struct bmi_drv_data_t g_bmi160_data;
+
+struct motion_sensor_t motion_sensors[] = {
+	[LID_ACCEL] = {
+	 .name = "Lid Accel",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_LIS2DWL,
+	 .type = MOTIONSENSE_TYPE_ACCEL,
+	 .location = MOTIONSENSE_LOC_LID,
+	 .drv = &lis2dw12_drv,
+	 .mutex = &g_lid_mutex,
+	 .drv_data = &g_lis2dwl_data,
+	 .port = I2C_PORT_SENSORS,
+	 .i2c_spi_addr_flags = LIS2DWL_ADDR1_FLAGS,
+	 .rot_standard_ref = &lid_standard_ref,
+	 .default_range = 2, /* g */
+	 .min_frequency = LIS2DW12_ODR_MIN_VAL,
+	 .max_frequency = LIS2DW12_ODR_MAX_VAL,
+	 .config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 12500 | ROUND_UP_FLAG,
+		},
+		/* Sensor on for lid angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	 },
+	},
+	/*
+	 * Note: bmi160: supports accelerometer and gyro sensor
+	 * Requirement: accelerometer sensor must init before gyro sensor
+	 * DO NOT change the order of the following table.
+	 */
+	[BASE_ACCEL] = {
+	 .name = "Accel",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_BMI160,
+	 .type = MOTIONSENSE_TYPE_ACCEL,
+	 .location = MOTIONSENSE_LOC_BASE,
+	 .drv = &bmi160_drv,
+	 .mutex = &g_base_mutex,
+	 .drv_data = &g_bmi160_data,
+	 .port = CONFIG_SPI_ACCEL_PORT,
+	 .i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
+	 .rot_standard_ref = &base_standard_ref,
+	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
+	 .min_frequency = BMI_ACCEL_MIN_FREQ,
+	 .max_frequency = BMI_ACCEL_MAX_FREQ,
+	 .config = {
+		 /* EC use accel for angle detection */
+		 [SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		 },
+		 /* Sensor on for angle detection */
+		 [SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		 },
+	 },
+	},
+	[BASE_GYRO] = {
+	 .name = "Gyro",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_BMI160,
+	 .type = MOTIONSENSE_TYPE_GYRO,
+	 .location = MOTIONSENSE_LOC_BASE,
+	 .drv = &bmi160_drv,
+	 .mutex = &g_base_mutex,
+	 .drv_data = &g_bmi160_data,
+	 .port = CONFIG_SPI_ACCEL_PORT,
+	 .i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
+	 .default_range = 1000, /* dps */
+	 .rot_standard_ref = &base_standard_ref,
+	 .min_frequency = BMI_GYRO_MIN_FREQ,
+	 .max_frequency = BMI_GYRO_MAX_FREQ,
+	},
+};
+const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+const struct it8801_pwm_t it8801_pwm_channels[] = {
+	[IT8801_PWM_CH_KBLIGHT] = { .index = 4 },
+};
+
+void board_kblight_init(void)
+{
+	kblight_register(&kblight_it8801);
+}
+
+bool board_has_kb_backlight(void)
+{
+	/* Default enable keyboard backlight */
+	return true;
+}
+#endif /* !VARIANT_KUKUI_NO_SENSORS */
+
+/* Battery functions */
+#define SB_SMARTCHARGE 0x26
+/* Quick charge enable bit */
+#define SMART_QUICK_CHARGE 0x02
+/* Quick charge support bit */
+#define MODE_QUICK_CHARGE_SUPPORT 0x01
+
+static void sb_quick_charge_mode(int enable)
+{
+	int val, rv;
+
+	rv = sb_read(SB_SMARTCHARGE, &val);
+	if (rv || !(val & MODE_QUICK_CHARGE_SUPPORT))
+		return;
+
+	if (enable)
+		val |= SMART_QUICK_CHARGE;
+	else
+		val &= ~SMART_QUICK_CHARGE;
+
+	sb_write(SB_SMARTCHARGE, val);
+}
+
+/* Called on AP S0iX -> S0 transition */
+static void board_chipset_resume(void)
+{
+#ifndef VARIANT_KUKUI_NO_SENSORS
+	if (board_has_kb_backlight())
+		ioex_set_level(IOEX_KB_BL_EN, 1);
+#endif
+
+	/* Normal charge mode */
+	sb_quick_charge_mode(0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_INIT, board_chipset_resume, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S0 -> S0iX transition */
+static void board_chipset_suspend(void)
+{
+#ifndef VARIANT_KUKUI_NO_SENSORS
+	if (board_has_kb_backlight())
+		ioex_set_level(IOEX_KB_BL_EN, 0);
+#endif
+
+	/* Quick charge mode */
+	sb_quick_charge_mode(1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S5 -> S3 transition */
+static void board_chipset_startup(void)
+{
+	gpio_set_level(GPIO_EN_USBA_5V, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S3 -> S5 transition */
+static void board_chipset_shutdown(void)
+{
+	gpio_set_level(GPIO_EN_USBA_5V, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
+
+int board_get_charger_i2c(void)
+{
+	/* TODO(b:138415463): confirm the bus allocation for future builds */
+	return I2C_PORT_CHARGER;
+}
+
+int board_get_battery_i2c(void)
+{
+	return I2C_PORT_BATTERY;
+}
+
+#ifdef SECTION_IS_RW
+static int it8801_get_target_channel(enum pwm_channel *channel, int type,
+				     int index)
+{
+	switch (type) {
+	case EC_PWM_TYPE_GENERIC:
+		*channel = index;
+		break;
+	default:
+		return -1;
+	}
+
+	return *channel >= 1;
+}
+
+static enum ec_status
+host_command_pwm_set_duty(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_pwm_set_duty *p = args->params;
+	enum pwm_channel channel;
+	uint16_t duty;
+
+	if (it8801_get_target_channel(&channel, p->pwm_type, p->index))
+		return EC_RES_INVALID_PARAM;
+
+	duty = (uint32_t)p->duty * 255 / 65535;
+	it8801_pwm_set_raw_duty(channel, duty);
+	it8801_pwm_enable(channel, p->duty > 0);
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_DUTY, host_command_pwm_set_duty,
+		     EC_VER_MASK(0));
+
+static enum ec_status
+host_command_pwm_get_duty(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_pwm_get_duty *p = args->params;
+	struct ec_response_pwm_get_duty *r = args->response;
+
+	enum pwm_channel channel;
+
+	if (it8801_get_target_channel(&channel, p->pwm_type, p->index))
+		return EC_RES_INVALID_PARAM;
+
+	r->duty = (uint32_t)it8801_pwm_get_raw_duty(channel) * 65535 / 255;
+	args->response_size = sizeof(*r);
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_DUTY, host_command_pwm_get_duty,
+		     EC_VER_MASK(0));
+#endif
diff --git a/board/munna/board.h b/board/munna/board.h
new file mode 100644
index 0000000000..286f80aa38
--- /dev/null
+++ b/board/munna/board.h
@@ -0,0 +1,190 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Configuration for Munna */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#define VARIANT_KUKUI_JACUZZI
+#define VARIANT_KUKUI_BATTERY_SMART
+#define VARIANT_KUKUI_CHARGER_ISL9238
+#define VARIANT_KUKUI_EC_STM32L431
+
+#ifndef SECTION_IS_RW
+#define VARIANT_KUKUI_NO_SENSORS
+#endif /* SECTION_IS_RW */
+
+#include "baseboard.h"
+
+#undef CONFIG_CHIPSET_POWER_SEQ_VERSION
+#define CONFIG_CHIPSET_POWER_SEQ_VERSION 1
+#undef CONFIG_SYSTEM_UNLOCKED
+
+/* PLL configuration. Freq = STM32_HSE_CLOCK or HSI (16MHz) * n/m/r */
+#undef STM32_PLLM
+#undef STM32_PLLN
+#undef STM32_PLLR
+#define STM32_PLLM 1
+#ifdef STM32_HSE_CLOCK
+#define STM32_PLLN 12
+#else
+#define STM32_PLLN 10
+#endif
+#define STM32_PLLR 2
+
+#define STM32_USE_PLL
+
+#define CONFIG_BATTERY_HW_PRESENT_CUSTOM
+
+#define CONFIG_CHARGER_PSYS
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 5
+
+#define CONFIG_CHARGER_RUNTIME_CONFIG
+
+#define CONFIG_BC12_DETECT_PI3USB9201
+
+#define CONFIG_EXTPOWER_GPIO
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
+#define CONFIG_EXTPOWER_DEBOUNCE_MS 200
+
+#define CONFIG_I2C_BITBANG
+#undef I2C_BITBANG_PORT_COUNT
+#define I2C_BITBANG_PORT_COUNT 1
+#undef CONFIG_I2C_NACK_RETRY_COUNT
+#define CONFIG_I2C_NACK_RETRY_COUNT 10
+#define CONFIG_SMBUS_PEC
+
+#define CONFIG_USB_PD_TCPM_FUSB302
+#define CONFIG_USB_PD_DISCHARGE_GPIO
+#define CONFIG_USB_PD_TCPC_LOW_POWER
+
+#define CONFIG_USB_MUX_IT5205
+
+#define CONFIG_LED_ONOFF_STATES
+#define CONFIG_LED_POWER_LED
+
+#undef CONFIG_WATCHDOG_PERIOD_MS
+#define CONFIG_WATCHDOG_PERIOD_MS 4000
+
+/* Motion Sensors */
+#ifndef VARIANT_KUKUI_NO_SENSORS
+#define CONFIG_ACCEL_LIS2DWL /* Lid accel */
+#define CONFIG_ACCELGYRO_BMI160 /* Base accel */
+#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+#define CONFIG_ALS
+#define CONFIG_CMD_ACCEL_INFO
+
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_UPDATE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+
+#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
+
+#ifdef SECTION_IS_RW
+#define CONFIG_IO_EXPANDER_IT8801_PWM
+#define CONFIG_KEYBOARD_BACKLIGHT
+#endif
+
+#endif /* VARIANT_KUKUI_NO_SENSORS */
+
+/* I2C ports */
+#define I2C_PORT_BC12 0
+#define I2C_PORT_TCPC0 0
+#define I2C_PORT_USB_MUX 0
+#define I2C_PORT_CHARGER 2
+#define I2C_PORT_SENSORS 2
+#define I2C_PORT_KB_DISCRETE 2
+#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
+#define I2C_PORT_BATTERY 3
+#define I2C_PORT_TCPC0 0
+
+#undef I2C_CONTROLLER_COUNT
+#undef I2C_PORT_COUNT
+#define I2C_CONTROLLER_COUNT 3
+#define I2C_PORT_COUNT 3
+
+/* IT8801 I2C address */
+#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1
+
+/* Enable Accel over SPI */
+#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */
+
+#define CONFIG_KEYBOARD_PROTOCOL_MKBP
+#define CONFIG_MKBP_EVENT
+#define CONFIG_MKBP_USE_GPIO
+/* Define the MKBP events which are allowed to wakeup AP in S3. */
+#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK            \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+#undef CONFIG_GMR_TABLET_MODE
+#undef GPIO_TABLET_MODE_L
+#undef CONFIG_TABLET_MODE
+#undef CONFIG_TABLET_MODE_SWITCH
+
+#ifndef __ASSEMBLER__
+
+enum adc_channel {
+	/* Real ADC channels begin here */
+	ADC_BOARD_ID = 0,
+	ADC_EC_SKU_ID,
+	ADC_CH_COUNT
+};
+
+/* power signal definitions */
+enum power_signal {
+	AP_IN_S3_L,
+	PMIC_PWR_GOOD,
+
+	/* Number of signals */
+	POWER_SIGNAL_COUNT,
+};
+
+/* Motion sensors */
+enum sensor_id {
+	LID_ACCEL = 0,
+	BASE_ACCEL,
+	BASE_GYRO,
+	SENSOR_COUNT,
+};
+
+enum charge_port {
+	CHARGE_PORT_USB_C,
+};
+
+enum battery_type {
+	BATTERY_LGC,
+	BATTERY_SUNWODA,
+	BATTERY_SMP,
+	BATTERY_TYPE_COUNT,
+};
+
+enum pwm_channel {
+	IT8801_PWM_CH_KBLIGHT = 0,
+};
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+#ifdef SECTION_IS_RO
+/* Interrupt handler for emmc task */
+void emmc_cmd_interrupt(enum gpio_signal signal);
+#endif
+
+void bc12_interrupt(enum gpio_signal signal);
+void board_reset_pd_mcu(void);
+int board_get_version(void);
+
+/* returns the i2c port number of charger/battery */
+int board_get_charger_i2c(void);
+int board_get_battery_i2c(void);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/munna/build.mk b/board/munna/build.mk
new file mode 100644
index 0000000000..aab7974af2
--- /dev/null
+++ b/board/munna/build.mk
@@ -0,0 +1,15 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+#
+# STmicro STM32L431RCI
+CHIP:=stm32
+CHIP_FAMILY:=stm32l4
+CHIP_VARIANT:=stm32l431x
+BASEBOARD:=kukui
+
+board-y=battery.o board.o led.o
diff --git a/board/munna/ec.tasklist b/board/munna/ec.tasklist
new file mode 100644
index 0000000000..1e7e61108b
--- /dev/null
+++ b/board/munna/ec.tasklist
@@ -0,0 +1,20 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, TRENTA_TASK_STACK_SIZE) \
+	TASK_ALWAYS_RW(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 1024) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, 1280) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, 1024) \
+	TASK_ALWAYS_RO(EMMC, emmc_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/munna/gpio.inc b/board/munna/gpio.inc
new file mode 100644
index 0000000000..72de7677dc
--- /dev/null
+++ b/board/munna/gpio.inc
@@ -0,0 +1,120 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first.
+ */
+
+/* Interrupts */
+GPIO_INT(USB_C0_PD_INT_ODL, PIN(B, 1), GPIO_INT_FALLING | GPIO_PULL_UP,
+         tcpc_alert_event)
+GPIO_INT(POWER_BUTTON_L,    PIN(A, 11),  GPIO_INT_BOTH | GPIO_PULL_UP,
+         power_button_interrupt) /* EC_PWR_BTN_ODL */
+GPIO_INT(AP_IN_SLEEP_L,     PIN(C, 12), GPIO_INT_BOTH | GPIO_PULL_DOWN,
+         power_signal_interrupt)
+GPIO_INT(PMIC_EC_RESETB,    PIN(B, 7),  GPIO_INT_BOTH | GPIO_PULL_DOWN,
+         power_signal_interrupt)
+GPIO_INT(WARM_RESET_REQ,    PIN(A, 3),  GPIO_INT_RISING | GPIO_PULL_DOWN,
+         chipset_reset_request_interrupt)
+GPIO_INT_RW(ACCEL_INT_ODL,  PIN(A, 4),  GPIO_INT_FALLING | GPIO_SEL_1P8V | GPIO_PULL_UP,
+         bmi160_interrupt)
+GPIO_INT_RO(EMMC_CMD,       PIN(B, 15), GPIO_INT_FALLING,
+         emmc_cmd_interrupt)
+GPIO_INT(SPI1_NSS,          PIN(A, 15), GPIO_INT_BOTH | GPIO_PULL_UP,
+         spi_event) /* SPI_AP_EC_CS_L */
+GPIO_INT(LID_OPEN,          PIN(C, 5),  GPIO_INT_BOTH,
+         lid_interrupt)
+GPIO_INT(AC_PRESENT,        PIN(A, 6),  GPIO_INT_BOTH,
+         extpower_interrupt) /* ACOK_OD */
+GPIO_INT(BC12_EC_INT_ODL,   PIN(C, 9),  GPIO_INT_FALLING,
+         bc12_interrupt)
+GPIO_INT(IT8801_SMB_INT,    PIN(A, 8),  GPIO_INT_FALLING | GPIO_PULL_UP,
+         io_expander_it8801_interrupt) /* KB_INT_ODL */
+GPIO_INT(AP_EC_WATCHDOG_L,  PIN(D, 2),  GPIO_INT_FALLING,
+         chipset_watchdog_interrupt)
+
+/* Unimplemented interrupts */
+GPIO(ALS_RGB_INT_ODL,      PIN(C, 10), GPIO_INPUT)
+GPIO(TABLET_MODE_L,        PIN(B, 11), GPIO_INPUT)
+
+/* Reset pins */
+GPIO(AP_SYS_RST_L,         PIN(C, 11), GPIO_OUT_LOW)
+GPIO(PMIC_WATCHDOG_L,      PIN(A, 2),  GPIO_OUT_LOW)
+GPIO(PMIC_EN_ODL,          PIN(H, 0),  GPIO_ODR_HIGH)
+
+/*
+ * I2C pins should be configured as inputs until I2C module is
+ * initialized. This will avoid driving the lines unintentionally.
+ */
+GPIO(I2C1_SCL,             PIN(B, 8),  GPIO_INPUT)
+GPIO(I2C1_SDA,             PIN(B, 9),  GPIO_INPUT)
+GPIO(I2C3_SCL,             PIN(C, 0),  GPIO_INPUT)
+GPIO(I2C3_SDA,             PIN(C, 1),  GPIO_INPUT)
+GPIO(I2C4_SCL,             PIN(A, 5),  GPIO_ODR_HIGH)
+GPIO(I2C4_SDA,             PIN(C, 4),  GPIO_ODR_HIGH)
+
+/* Analog pins */
+GPIO(BOARD_ID,             PIN(A, 0),  GPIO_ANALOG)
+GPIO(EC_SKU_ID,            PIN(B, 0),  GPIO_ANALOG)
+
+/* Other input pins */
+GPIO(WP_L,                 PIN(C, 8),  GPIO_INPUT) /* EC_FLASH_WP_ODL */
+GPIO(BOOT0,                PIN(H, 3),  GPIO_INPUT)
+GPIO(CCD_MODE_ODL,         PIN(A, 1),  GPIO_INPUT)
+
+/* Other output pins */
+GPIO(EC_BATT_PRES_ODL,     PIN(A, 7),  GPIO_INPUT)
+GPIO(EC_BL_EN_OD,          PIN(A, 13), GPIO_ODR_HIGH)
+GPIO(EN_USBA_5V,           PIN(C, 14), GPIO_OUT_LOW)
+GPIO(EC_SENSOR_SPI_MISO,   PIN(C, 2),  GPIO_INPUT)
+GPIO(EC_SENSOR_SPI_MOSI,   PIN(C, 3),  GPIO_OUT_LOW)
+GPIO(EC_SENSOR_SPI_NSS,    PIN(B, 12), GPIO_OUT_HIGH)
+GPIO(EC_SENSOR_SPI_CK,     PIN(B, 10), GPIO_OUT_LOW)
+GPIO(ENTERING_RW,          PIN(C, 6),  GPIO_ODR_HIGH) /* EC_ENTERING_RW_ODL */
+GPIO(EC_INT_L,             PIN(C, 7),  GPIO_ODR_HIGH) /* EC_AP_INT_ODL */
+GPIO(EC_BOARD_ID_EN_L,     PIN(C, 15), GPIO_ODR_HIGH) /* EC_BOARD_ID_EN_ODL */
+GPIO(USB_C0_HPD_OD,        PIN(H, 1),  GPIO_ODR_LOW)
+GPIO(BOOTBLOCK_EN_L,       PIN(A, 12), GPIO_ODR_HIGH)
+GPIO(EN_PP1800_S5_L,       PIN(A, 14), GPIO_OUT_LOW)
+GPIO(USB_C0_DISCHARGE,     PIN(B, 6),  GPIO_OUT_LOW)
+
+IOEX(PWR_LED_WHITE_L,      EXPIN(0, 1, 4), GPIO_OUT_HIGH)
+IOEX(BAT_LED_GREEN_FULL_L, EXPIN(0, 1, 3), GPIO_OUT_HIGH)
+IOEX(BAT_LED_RED_L,        EXPIN(0, 1, 2), GPIO_OUT_HIGH)
+IOEX(KB_BL_EN,             EXPIN(0, 0, 7), GPIO_OUT_LOW)
+
+/*
+ * TODO(b:138352732): On IT88801 expander, To be readded once IT8801 driver and
+ * gpio expander framework has landed.
+ */
+UNIMPLEMENTED(EN_PP5000_USBC)
+UNIMPLEMENTED(PMIC_FORCE_RESET_ODL)
+UNIMPLEMENTED(EN_USBC_CHARGE_L)
+
+/* USART1: PA9/PA10 */
+ALTERNATE(PIN_MASK(A, 0x0600), 7, MODULE_UART,       0)
+/* I2C MASTER: PB8/9 */
+ALTERNATE(PIN_MASK(B, 0x0300), 4, MODULE_I2C,        GPIO_ODR_HIGH )
+/* I2C MASTER: PC0/C1 */
+ALTERNATE(PIN_MASK(C, 0x0003), 4, MODULE_I2C,        GPIO_ODR_HIGH )
+
+
+/* SPI1 */
+/* SPI SLAVE: PB3/4/5 */
+ALTERNATE(PIN_MASK(B, 0x0038), 5, MODULE_SPI,        0)
+/* SPI SLAVE CS: PA15 */
+ALTERNATE(PIN_MASK(A, 0x8000), 5, MODULE_SPI,        0)
+
+/* SPI2 */
+/* Shared between slave for emmc and master for bmi160 */
+/* They're mutually exclusive with gpio_config_module. */
+/* EMMC SPI SLAVE: PB13/14/15 */
+ALTERNATE(PIN_MASK(B, 0xE000), 5, MODULE_SPI_FLASH,  0)
+/* SENSORS SPI MASTER: PB10, PB12, PC2, PC3 */
+ALTERNATE(PIN_MASK(B, 0x0400), 5, MODULE_SPI_CONTROLLER, 0)
+ALTERNATE(PIN_MASK(C, 0x000C), 5, MODULE_SPI_CONTROLLER, 0)
diff --git a/board/munna/led.c b/board/munna/led.c
new file mode 100644
index 0000000000..e537863e80
--- /dev/null
+++ b/board/munna/led.c
@@ -0,0 +1,120 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power and battery LED control for Munna
+ */
+#include "common.h"
+#include "driver/ioexpander/it8801.h"
+#include "ec_commands.h"
+#include "ioexpander.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+
+#define LED_ON_LVL 0
+#define LED_OFF_LVL 1
+
+__override const int led_charge_lvl_1 = 5;
+__override const int led_charge_lvl_2 = 97;
+
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
+
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    1 * LED_ONE_SEC },
+						  { LED_OFF,
+						    3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_GREEN:
+		ioex_set_level(IOEX_BAT_LED_GREEN_FULL_L, LED_ON_LVL);
+		ioex_set_level(IOEX_BAT_LED_RED_L, LED_OFF_LVL);
+		break;
+	case EC_LED_COLOR_AMBER:
+		ioex_set_level(IOEX_BAT_LED_GREEN_FULL_L, LED_ON_LVL);
+		ioex_set_level(IOEX_BAT_LED_RED_L, LED_ON_LVL);
+		break;
+	case EC_LED_COLOR_RED:
+		ioex_set_level(IOEX_BAT_LED_GREEN_FULL_L, LED_OFF_LVL);
+		ioex_set_level(IOEX_BAT_LED_RED_L, LED_ON_LVL);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		ioex_set_level(IOEX_BAT_LED_GREEN_FULL_L, LED_OFF_LVL);
+		ioex_set_level(IOEX_BAT_LED_RED_L, LED_OFF_LVL);
+		break;
+	}
+}
+
+__override void led_set_color_power(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_WHITE:
+		ioex_set_level(IOEX_PWR_LED_WHITE_L, LED_ON_LVL);
+		break;
+	default:
+		ioex_set_level(IOEX_PWR_LED_WHITE_L, LED_OFF_LVL);
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_GREEN] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		brightness_range[EC_LED_COLOR_RED] = 1;
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		if (brightness[EC_LED_COLOR_GREEN] != 0)
+			led_set_color_battery(EC_LED_COLOR_GREEN);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(EC_LED_COLOR_AMBER);
+		else if (brightness[EC_LED_COLOR_RED] != 0)
+			led_set_color_battery(EC_LED_COLOR_RED);
+		else
+			led_set_color_battery(LED_OFF);
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_power(EC_LED_COLOR_WHITE);
+		else
+			led_set_color_power(LED_OFF);
+	} else {
+		return EC_ERROR_INVAL;
+	}
+	return EC_SUCCESS;
+}
diff --git a/board/munna/vif_override.xml b/board/munna/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/munna/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/mushu/battery.c b/board/mushu/battery.c
index 7e48dfdc19..d523d918f7 100644
--- a/board/mushu/battery.c
+++ b/board/mushu/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/mushu/board.c b/board/mushu/board.c
index dd407091c5..35c1972dce 100644
--- a/board/mushu/board.c
+++ b/board/mushu/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,6 @@
 /* Mushu board-specific configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "button.h"
 #include "common.h"
 #include "cros_board_info.h"
@@ -19,7 +18,6 @@
 #include "driver/tcpm/ps8xxx.h"
 #include "driver/tcpm/tcpci.h"
 #include "driver/temp_sensor/amd_r19me4070.h"
-#include "driver/temp_sensor/f75303.h"
 #include "ec_commands.h"
 #include "extpower.h"
 #include "fan.h"
@@ -37,16 +35,17 @@
 #include "system.h"
 #include "task.h"
 #include "temp_sensor.h"
+#include "temp_sensor/f75303.h"
+#include "temp_sensor/thermistor.h"
 #include "thermal.h"
-#include "thermistor.h"
 #include "uart.h"
 #include "usb_charge.h"
 #include "usb_pd.h"
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* GPIO to enable/disable the USB Type-A port. */
 const int usb_port_enable[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT] = {
@@ -96,11 +95,11 @@ static void bc12_interrupt(enum gpio_signal signal)
 {
 	switch (signal) {
 	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
 		break;
 
 	case GPIO_USB_C1_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12, 0);
+		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
 		break;
 
 	default:
@@ -108,22 +107,24 @@ static void bc12_interrupt(enum gpio_signal signal)
 	}
 }
 
-#include "gpio_list.h" /* Must come after other header files. */
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
 
 /******************************************************************************/
 /* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
+const struct spi_device_t spi_devices[] = {};
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
 /******************************************************************************/
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT]   = { .channel = 3, .flags = 0, .freq = 10000 },
-	[PWM_CH_FAN] = {.channel = 5, .flags = PWM_CONFIG_OPEN_DRAIN,
-			.freq = 25000},
-	[PWM_CH_FAN2] = {.channel = 6, .flags = PWM_CONFIG_OPEN_DRAIN,
-			.freq = 25000},
+	[PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 },
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
+	[PWM_CH_FAN2] = { .channel = 6,
+			  .flags = PWM_CONFIG_OPEN_DRAIN,
+			  .freq = 25000 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
@@ -143,22 +144,26 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = I2C_PORT_TCPC1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
 		},
 		.drv = &ps8xxx_tcpm_drv,
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_TCPC_0] = {
-		.usb_port = USB_PD_PORT_TCPC_0,
-		.driver = &anx7447_usb_mux_driver,
-		.hpd_update = &anx7447_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_0,
+			.driver = &anx7447_usb_mux_driver,
+			.hpd_update = &anx7447_tcpc_update_hpd_status,
+		},
 	},
 	[USB_PD_PORT_TCPC_1] = {
-		.usb_port = USB_PD_PORT_TCPC_1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 	}
 };
 
@@ -225,22 +230,18 @@ static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
 };
 
 /* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					      { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
 
 /*
  * TODO(b/124337208): P0 boards don't have this sensor mounted so the rotation
  * matrix can't be tested properly. This needs to be revisited after EVT to make
  * sure the rotation matrix for the lid sensor is correct.
  */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+					     { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
@@ -284,7 +285,7 @@ struct motion_sensor_t motion_sensors[] = {
 		.rot_standard_ref = &base_standard_ref,
 		.min_frequency = BMI_ACCEL_MIN_FREQ,
 		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.default_range = 2, /* g, to support tablet mode  */
+	  .default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
 		.config = {
 			[SENSOR_CONFIG_EC_S0] = {
 				.odr = 10000 | ROUND_UP_FLAG,
@@ -364,14 +365,14 @@ BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
 
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
 
 const struct fan_conf fan_conf_1 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_1,	/* Use MFT id to control fan */
+	.ch = MFT_CH_1, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
@@ -395,97 +396,93 @@ const struct fan_t fans[FAN_CH_COUNT] = {
 /******************************************************************************/
 /* MFT channels. These are logically separate from pwm_channels. */
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN},
-	[MFT_CH_1] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN2},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN },
+	[MFT_CH_1] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN2 },
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		"TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_2] = {
-		"TEMP_5V", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_1] = { "TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_2] = { "TEMP_5V", NPCX_ADC_CH1, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_CHARGER] = {
-		.name = "CHARGER",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_1
-	},
-	[TEMP_5V] = {
-		.name = "5V",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_2
-	},
-	[TEMP_GPU] = {
-		.name = "GPU",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_R19ME4070,
-		.idx = R19ME4070_LOCAL
-	},
-	[TEMP_F75303_LOCAL] = {
-		.name = "F75303_Local",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = f75303_get_val,
-		.idx = F75303_IDX_LOCAL
-	},
-	[TEMP_F75303_GPU] = {
-		.name = "F75303_GPU",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = f75303_get_val,
-		.idx = F75303_IDX_REMOTE1
-	},
-	[TEMP_F75303_GPU_POWER] = {
-		.name = "F75303_GPU_Power",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = f75303_get_val,
-		.idx = F75303_IDX_REMOTE2
-	},
+	[TEMP_CHARGER] = { .name = "CHARGER",
+			   .type = TEMP_SENSOR_TYPE_BOARD,
+			   .read = get_temp_3v3_30k9_47k_4050b,
+			   .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_5V] = { .name = "5V",
+		      .type = TEMP_SENSOR_TYPE_BOARD,
+		      .read = get_temp_3v3_30k9_47k_4050b,
+		      .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_GPU] = { .name = "GPU",
+		       .type = TEMP_SENSOR_TYPE_BOARD,
+		       .read = get_temp_R19ME4070,
+		       .idx = R19ME4070_LOCAL },
+	[TEMP_F75303_LOCAL] = { .name = "F75303_Local",
+				.type = TEMP_SENSOR_TYPE_BOARD,
+				.read = f75303_get_val,
+				.idx = F75303_IDX_LOCAL },
+	[TEMP_F75303_GPU] = { .name = "F75303_GPU",
+			      .type = TEMP_SENSOR_TYPE_BOARD,
+			      .read = f75303_get_val,
+			      .idx = F75303_IDX_REMOTE1 },
+	[TEMP_F75303_GPU_POWER] = { .name = "F75303_GPU_Power",
+				    .type = TEMP_SENSOR_TYPE_BOARD,
+				    .read = f75303_get_val,
+				    .idx = F75303_IDX_REMOTE2 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
-
 /* Hatch Temperature sensors */
 /*
  * TODO(b/124316213): These setting need to be reviewed and set appropriately
  * for Hatch. They matter when the EC is controlling the fan as opposed to DPTF
  * control.
  */
-const static struct ec_thermal_config thermal_a = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(0),
-	.temp_fan_max = C_TO_K(70),
-};
-
-const static struct ec_thermal_config thermal_b = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(0),
-	.temp_fan_max = C_TO_K(70),
-};
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_A                \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+		.temp_fan_off = C_TO_K(0), \
+		.temp_fan_max = C_TO_K(70), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A;
 
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_B                \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+		.temp_fan_off = C_TO_K(0), \
+		.temp_fan_max = C_TO_K(70), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_b = THERMAL_B;
 
 struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
 
@@ -527,7 +524,6 @@ static void board_gpio_set_pp5000(void)
 	} else if (board_id >= 1) {
 		reset_gpio_flags(GPIO_EN_PP5000_A_V1, GPIO_OUT_LOW);
 	}
-
 }
 
 static void board_init(void)
diff --git a/board/mushu/board.h b/board/mushu/board.h
index 40c4046350..c3cafaac93 100644
--- a/board/mushu/board.h
+++ b/board/mushu/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,12 +11,31 @@
 /* Baseboard features */
 #include "baseboard.h"
 
+/* Reduce flash usage */
+#undef CONFIG_ACCEL_SPOOF_MODE
+#undef CONFIG_CONSOLE_CMDHELP
+#undef CONFIG_CONSOLE_HISTORY
+#define CONFIG_USB_PD_DEBUG_LEVEL 0
+#undef CONFIG_CMD_ACCELSPOOF
+#undef CONFIG_CMD_ACCELS
+#undef CONFIG_CMD_APTHROTTLE
+#undef CONFIG_CMD_BATTFAKE
+#undef CONFIG_CMD_CHARGE_SUPPLIER_INFO
+#undef CONFIG_CMD_CHARGER_DUMP
+#undef CONFIG_CMD_HCDEBUG
+#undef CONFIG_CMD_I2C_SCAN
+#undef CONFIG_CMD_I2C_XFER
+#undef CONFIG_CMD_PPC_DUMP
+#undef CONFIG_CMD_SYSLOCK
+#undef CONFIG_CMD_TIMERINFO
+
 #define CONFIG_POWER_BUTTON
 #define CONFIG_KEYBOARD_PROTOCOL_8042
 #define CONFIG_LED_COMMON
 #define CONFIG_LOW_POWER_IDLE
 
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
+#undef CONFIG_CMD_MFALLOW
 
 #undef CONFIG_UART_TX_BUF_SIZE
 #define CONFIG_UART_TX_BUF_SIZE 4096
@@ -24,10 +43,8 @@
 /* Keyboard features */
 #define CONFIG_PWM_KBLIGHT
 
-
 /* Sensors */
 /* BMI160 Base accel/gyro */
-#define CONFIG_ACCEL_INTERRUPTS
 #define CONFIG_ACCELGYRO_BMI160
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
@@ -45,7 +62,7 @@
 #define CONFIG_ALS_TCS3400
 #define CONFIG_ALS_TCS3400_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS)
-#define I2C_PORT_ALS      I2C_PORT_SENSOR
+#define I2C_PORT_ALS I2C_PORT_SENSOR
 #define CONFIG_TEMP_SENSOR
 /* AMD SMBUS Temp sensors */
 #define CONFIG_TEMP_SENSOR_AMD_R19ME4070
@@ -56,7 +73,7 @@
 #define I2C_PORT_THERMAL I2C_PORT_SENSOR
 
 /* GPU features */
-#define I2C_PORT_GPU                    NPCX_I2C_PORT4_1
+#define I2C_PORT_GPU NPCX_I2C_PORT4_1
 
 /* USB Type C and USB PD defines */
 #undef CONFIG_USB_PD_TCPMV1
@@ -65,6 +82,7 @@
  * parade PS8751 TCPC
  */
 #define CONFIG_USB_PD_TCPMV2
+#undef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
 #define CONFIG_USB_PID 0x5047
 #define CONFIG_USB_PD_DECODE_SOP
 #define CONFIG_USB_PD_TRY_SRC
@@ -111,7 +129,7 @@
 #define CONFIG_CUSTOM_FAN_CONTROL
 #undef CONFIG_FAN_INIT_SPEED
 #define CONFIG_FAN_INIT_SPEED 50
-#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_A_RAILS
+#define CONFIG_TEMP_SENSOR_POWER
 #define CONFIG_THERMISTOR
 #define CONFIG_THROTTLE_AP
 #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
@@ -130,15 +148,16 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_AC_PRESENT		GPIO_ACOK_OD
-#define GPIO_RSMRST_L_PGOOD	GPIO_PG_EC_RSMRST_L
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L
+#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
 
 #ifndef __ASSEMBLER__
 
@@ -150,8 +169,8 @@
 extern enum gpio_signal gpio_en_pp5000_a;
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_1,	/* ADC0 */
-	ADC_TEMP_SENSOR_2,	/* ADC1 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
 	ADC_CH_COUNT
 };
 
@@ -164,12 +183,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_FAN,
-	PWM_CH_FAN2,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_FAN, PWM_CH_FAN2, PWM_CH_COUNT };
 
 enum fan_channel {
 	FAN_CH_0 = 0,
@@ -202,15 +216,14 @@ enum battery_type {
 	BATTERY_TYPE_COUNT,
 };
 
-
 #undef PD_OPERATING_POWER_MW
-#define PD_OPERATING_POWER_MW	15000
+#define PD_OPERATING_POWER_MW 15000
 #undef PD_MAX_POWER_MW
-#define PD_MAX_POWER_MW		100000
+#define PD_MAX_POWER_MW 100000
 #undef PD_MAX_CURRENT_MA
-#define PD_MAX_CURRENT_MA	5000
+#define PD_MAX_CURRENT_MA 5000
 #undef PD_MAX_VOLTAGE_MV
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_MAX_VOLTAGE_MV 20000
 
 #endif /* !__ASSEMBLER__ */
 
diff --git a/board/mushu/build.mk b/board/mushu/build.mk
index 2d6118ea70..4e42a0616e 100644
--- a/board/mushu/build.mk
+++ b/board/mushu/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/mushu/ec.tasklist b/board/mushu/ec.tasklist
index 4a1024a091..829be2b7c8 100644
--- a/board/mushu/ec.tasklist
+++ b/board/mushu/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/mushu/gpio.inc b/board/mushu/gpio.inc
index cc8c7a0154..e1711a87e1 100644
--- a/board/mushu/gpio.inc
+++ b/board/mushu/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,10 +16,10 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(PG_EC_RSMRST_L,       PIN(E, 2), GPIO_INT_BOTH, intel_x86_rsmrst_signal_interrupt)
diff --git a/board/mushu/led.c b/board/mushu/led.c
index 4e0c721c1b..1ec2075586 100644
--- a/board/mushu/led.c
+++ b/board/mushu/led.c
@@ -1,43 +1,48 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Power and battery LED control for Mushu
  */
 
+#include "chipset.h"
 #include "ec_commands.h"
 #include "gpio.h"
 #include "led_common.h"
 #include "led_onoff_states.h"
-#include "chipset.h"
 
 #define LED_ON_LVL 0
 #define LED_OFF_LVL 1
 
-const int led_charge_lvl_1 = 5;
+__override const int led_charge_lvl_1 = 5;
 
-const int led_charge_lvl_2 = 95;
+__override const int led_charge_lvl_2 = 95;
 
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-void led_set_color_battery(enum ec_led_colors color)
+__override void led_set_color_battery(enum ec_led_colors color)
 {
 	switch (color) {
 	case EC_LED_COLOR_AMBER:
@@ -76,4 +81,3 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 
 	return EC_SUCCESS;
 }
-
diff --git a/board/mushu/thermal.c b/board/mushu/thermal.c
index b61f36ab8a..da8f29de08 100644
--- a/board/mushu/thermal.c
+++ b/board/mushu/thermal.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,8 +23,7 @@ void fan_set_percent(int fan, int pct)
 	new_rpm = fan_percent_to_rpm(fan, pct);
 	actual_rpm = fan_get_rpm_actual(FAN_CH(fan));
 
-	if (new_rpm &&
-	    actual_rpm < min_rpm &&
+	if (new_rpm && actual_rpm < min_rpm &&
 	    new_rpm < fans[fan].rpm->rpm_start)
 		new_rpm = fans[fan].rpm->rpm_start;
 
diff --git a/board/mushu/vif_override.xml b/board/mushu/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/mushu/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/nami/battery.c b/board/nami/battery.c
index 149272c8c1..18f03fc9de 100644
--- a/board/nami/battery.c
+++ b/board/nami/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -16,8 +16,8 @@
 #include "hooks.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 /* Default, Nami, Vayne */
 static const struct battery_info info_0 = {
@@ -243,8 +243,9 @@ static int battery_init(void)
 	if (batt_status & STATUS_INITIALIZED)
 		return 1;
 
-	return battery_status(&batt_status) ? 0 :
-		!!(batt_status & STATUS_INITIALIZED);
+	return battery_status(&batt_status) ?
+		       0 :
+		       !!(batt_status & STATUS_INITIALIZED);
 }
 
 enum battery_disconnect_grace_period {
@@ -278,13 +279,13 @@ static int battery_check_disconnect_ti_bq40z50(void)
 	uint8_t data[6];
 
 	/* Check if battery charging + discharging is disabled. */
-	rv = sb_read_mfgacc(PARAM_OPERATION_STATUS,
-			    SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data));
+	rv = sb_read_mfgacc(PARAM_OPERATION_STATUS, SB_ALT_MANUFACTURER_ACCESS,
+			    data, sizeof(data));
 	if (rv)
 		return BATTERY_DISCONNECT_ERROR;
 
-	if ((data[3] & (BATTERY_DISCHARGING_DISABLED |
-			BATTERY_CHARGING_DISABLED)) ==
+	if ((data[3] &
+	     (BATTERY_DISCHARGING_DISABLED | BATTERY_CHARGING_DISABLED)) ==
 	    (BATTERY_DISCHARGING_DISABLED | BATTERY_CHARGING_DISABLED)) {
 		if (oem != PROJECT_SONA)
 			return BATTERY_DISCONNECTED;
@@ -298,10 +299,10 @@ static int battery_check_disconnect_ti_bq40z50(void)
 		 * stop charging and avoid damaging the battery.
 		 */
 		if (disconnect_grace_period ==
-				BATTERY_DISCONNECT_GRACE_PERIOD_OVER)
+		    BATTERY_DISCONNECT_GRACE_PERIOD_OVER)
 			return BATTERY_DISCONNECTED;
 		if (disconnect_grace_period ==
-				BATTERY_DISCONNECT_GRACE_PERIOD_OFF)
+		    BATTERY_DISCONNECT_GRACE_PERIOD_OFF)
 			hook_call_deferred(&battery_disconnect_timer_data,
 					   5 * SECOND);
 		ccprintf("Battery disconnect grace period\n");
diff --git a/board/nami/board.c b/board/nami/board.c
index 3ffed42ae0..c90fdb66dc 100644
--- a/board/nami/board.c
+++ b/board/nami/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,30 +6,31 @@
 /* Poppy board-specific configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "anx7447.h"
 #include "battery.h"
 #include "board_config.h"
 #include "button.h"
 #include "charge_manager.h"
-#include "charge_state.h"
 #include "charge_ramp.h"
+#include "charge_state.h"
 #include "charger.h"
 #include "chipset.h"
 #include "console.h"
 #include "cros_board_info.h"
-#include "driver/pmic_tps650x30.h"
-#include "driver/accelgyro_bmi_common.h"
 #include "driver/accel_bma2x2.h"
 #include "driver/accel_kionix.h"
+#include "driver/accelgyro_bmi_common.h"
 #include "driver/baro_bmp280.h"
 #include "driver/charger/isl923x.h"
 #include "driver/led/lm3509.h"
+#include "driver/pmic_tps650x30.h"
 #include "driver/tcpm/ps8xxx.h"
 #include "driver/tcpm/tcpci.h"
 #include "driver/tcpm/tcpm.h"
-#include "driver/temp_sensor/f75303.h"
+#include "espi.h"
 #include "extpower.h"
+#include "fan.h"
+#include "fan_chip.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "host_command.h"
@@ -55,6 +56,7 @@
 #include "tablet_mode.h"
 #include "task.h"
 #include "temp_sensor.h"
+#include "temp_sensor/f75303.h"
 #include "timer.h"
 #include "uart.h"
 #include "usb_charge.h"
@@ -62,15 +64,12 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 #include "util.h"
-#include "espi.h"
-#include "fan.h"
-#include "fan_chip.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define USB_PD_PORT_PS8751	0
-#define USB_PD_PORT_ANX7447	1
+#define USB_PD_PORT_PS8751 0
+#define USB_PD_PORT_ANX7447 1
 
 uint16_t board_version;
 uint8_t oem = PROJECT_NAMI;
@@ -83,17 +82,16 @@ uint8_t model;
  * that we don't have pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-	{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-	{0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3},
-	{-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0},
-	{1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4},
-	{2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0},
-	{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1},
-	{-1, -1},
+	{ -1, -1 }, { 0, 5 },	{ 1, 1 },   { 1, 0 },	{ 0, 6 },   { 0, 7 },
+	{ -1, -1 }, { -1, -1 }, { 1, 4 },   { 1, 3 },	{ -1, -1 }, { 1, 6 },
+	{ 1, 7 },   { 3, 1 },	{ 2, 0 },   { 1, 5 },	{ 2, 6 },   { 2, 7 },
+	{ 2, 1 },   { 2, 4 },	{ 2, 5 },   { 1, 2 },	{ 2, 3 },   { 2, 2 },
+	{ 3, 0 },   { -1, -1 }, { -1, -1 }, { -1, -1 }, { -1, -1 }, { -1, -1 },
+	{ -1, -1 },
 };
 
 const int keyboard_factory_scan_pins_used =
-		ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
@@ -139,26 +137,28 @@ void vbus1_evt(enum gpio_signal signal)
 
 void usb0_evt(enum gpio_signal signal)
 {
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
 }
 
 void usb1_evt(enum gpio_signal signal)
 {
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12, 0);
+	usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
 }
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* Vbus sensing (10x voltage divider). PPVAR_BOOSTIN_SENSE */
-	[ADC_VBUS] = {"VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
+	[ADC_VBUS] = { "VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT * 10,
+		       ADC_READ_MAX + 1, 0 },
 	/*
 	 * Adapter current output or battery charging/discharging current (uV)
 	 * 18x amplification on charger side.
 	 */
-	[ADC_AMON_BMON] = {"AMON_BMON", NPCX_ADC_CH1, ADC_MAX_VOLT*1000/18,
-			   ADC_READ_MAX+1, 0},
+	[ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH1, ADC_MAX_VOLT * 1000 / 18,
+			    ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
@@ -167,7 +167,7 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = -1,
 };
@@ -213,18 +213,42 @@ struct fan_t fans[FAN_CH_COUNT] = {
 /******************************************************************************/
 /* MFT channels. These are logically separate from pwm_channels. */
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN },
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 /* I2C port map */
-const struct i2c_port_t i2c_ports[]  = {
-	{"tcpc0",     NPCX_I2C_PORT0_0, 400, GPIO_I2C0_0_SCL, GPIO_I2C0_0_SDA},
-	{"tcpc1",     NPCX_I2C_PORT0_1, 400, GPIO_I2C0_1_SCL, GPIO_I2C0_1_SDA},
-	{"battery",   NPCX_I2C_PORT1,   100, GPIO_I2C1_SCL,   GPIO_I2C1_SDA},
-	{"charger",   NPCX_I2C_PORT2,   100, GPIO_I2C2_SCL,   GPIO_I2C2_SDA},
-	{"pmic",      NPCX_I2C_PORT2,   400, GPIO_I2C2_SCL,   GPIO_I2C2_SDA},
-	{"accelgyro", NPCX_I2C_PORT3,   400, GPIO_I2C3_SCL,   GPIO_I2C3_SDA},
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "tcpc0",
+	  .port = NPCX_I2C_PORT0_0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_0_SCL,
+	  .sda = GPIO_I2C0_0_SDA },
+	{ .name = "tcpc1",
+	  .port = NPCX_I2C_PORT0_1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_1_SCL,
+	  .sda = GPIO_I2C0_1_SDA },
+	{ .name = "battery",
+	  .port = NPCX_I2C_PORT1,
+	  .kbps = 100,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "charger",
+	  .port = NPCX_I2C_PORT2,
+	  .kbps = 100,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "pmic",
+	  .port = NPCX_I2C_PORT2,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "accelgyro",
+	  .port = NPCX_I2C_PORT3,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -234,7 +258,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = NPCX_I2C_PORT0_0,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
 		},
 		.drv = &ps8xxx_tcpm_drv,
 		/* Alert is active-low, push-pull */
@@ -259,16 +283,22 @@ static int ps8751_tune_mux(const struct usb_mux *me)
 	return EC_SUCCESS;
 }
 
-struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+struct usb_mux usb_mux_ps8751 = {
+	.usb_port = USB_PD_PORT_PS8751,
+	.driver = &tcpci_tcpm_usb_mux_driver,
+	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+};
+
+struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_PS8751] = {
-		.usb_port = USB_PD_PORT_PS8751,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux = &usb_mux_ps8751,
 	},
 	[USB_PD_PORT_ANX7447] = {
-		.usb_port = USB_PD_PORT_ANX7447,
-		.driver = &anx7447_usb_mux_driver,
-		.hpd_update = &anx7447_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_ANX7447,
+			.driver = &anx7447_usb_mux_driver,
+			.hpd_update = &anx7447_tcpc_update_hpd_status,
+		},
 	}
 };
 
@@ -298,7 +328,6 @@ void board_reset_pd_mcu(void)
 	if (oem == PROJECT_AKALI && board_version < 0x0200) {
 		if (anx7447_flash_erase(USB_PD_PORT_ANX7447))
 			CPRINTS("Failed to erase OCM flash");
-
 	}
 
 	/* Assert reset */
@@ -323,14 +352,15 @@ void board_tcpc_init(void)
 	gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL);
 
 	if (oem == PROJECT_SONA && model != MODEL_SYNDRA)
-		usb_muxes[USB_PD_PORT_PS8751].board_init = ps8751_tune_mux;
+		usb_mux_ps8751.board_init = ps8751_tune_mux;
 
 	/*
 	 * Initialize HPD to low; after sysjump SOC needs to see
 	 * HPD pulse to enable video path
 	 */
 	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		usb_mux_hpd_update(port, 0, 0);
+		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
 DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 2);
 
@@ -355,150 +385,188 @@ uint16_t tcpc_get_alert_status(void)
  * F75303_Remote1 is near CPU, and F75303_Remote2 is near 5V power IC.
  */
 const struct temp_sensor_t temp_sensors[TEMP_SENSOR_COUNT] = {
-	{"F75303_Local", TEMP_SENSOR_TYPE_BOARD, f75303_get_val,
-		F75303_IDX_LOCAL},
-	{"F75303_Remote1", TEMP_SENSOR_TYPE_CPU, f75303_get_val,
-		F75303_IDX_REMOTE1},
-	{"F75303_Remote2", TEMP_SENSOR_TYPE_BOARD, f75303_get_val,
-		F75303_IDX_REMOTE2},
+	{ "F75303_Local", TEMP_SENSOR_TYPE_BOARD, f75303_get_val,
+	  F75303_IDX_LOCAL },
+	{ "F75303_Remote1", TEMP_SENSOR_TYPE_CPU, f75303_get_val,
+	  F75303_IDX_REMOTE1 },
+	{ "F75303_Remote2", TEMP_SENSOR_TYPE_BOARD, f75303_get_val,
+	  F75303_IDX_REMOTE2 },
 };
 
 struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
 
 /* Nami/Vayne Remote 1, 2 */
-const static struct ec_thermal_config thermal_a = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(39),
-	.temp_fan_max = C_TO_K(50),
-};
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_A                \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+		.temp_fan_off = C_TO_K(39), \
+		.temp_fan_max = C_TO_K(50), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A;
 
 /* Sona Remote 1 */
-const static struct ec_thermal_config thermal_b1 = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(82),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(89),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(72),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(38),
-	.temp_fan_max = C_TO_K(58),
-};
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_B1               \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(82), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(89), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(72), \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+		.temp_fan_off = C_TO_K(38), \
+		.temp_fan_max = C_TO_K(58), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_b1 = THERMAL_B1;
 
 /* Sona Remote 2 */
-const static struct ec_thermal_config thermal_b2 = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(84),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(91),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(74),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(60),
-};
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_B2               \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(84), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(91), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(74), \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+		.temp_fan_off = C_TO_K(40), \
+		.temp_fan_max = C_TO_K(60), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_b2 = THERMAL_B2;
 
 /* Pantheon Remote 1 */
-const static struct ec_thermal_config thermal_c1 = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(66),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(56),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(38),
-	.temp_fan_max = C_TO_K(61),
-};
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_C1               \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(66), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(56), \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+		.temp_fan_off = C_TO_K(38), \
+		.temp_fan_max = C_TO_K(61), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_c1 = THERMAL_C1;
 
 /* Pantheon Remote 2 */
-const static struct ec_thermal_config thermal_c2 = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(74),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(82),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(64),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(38),
-	.temp_fan_max = C_TO_K(61),
-};
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_C2               \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(74), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(82), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(64), \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+		.temp_fan_off = C_TO_K(38), \
+		.temp_fan_max = C_TO_K(61), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_c2 = THERMAL_C2;
 
 /* Akali Local */
-const static struct ec_thermal_config thermal_d0 = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = C_TO_K(79),
-		[EC_TEMP_THRESH_HIGH] = 0,
-		[EC_TEMP_THRESH_HALT] = C_TO_K(81),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = C_TO_K(80),
-		[EC_TEMP_THRESH_HIGH] = 0,
-		[EC_TEMP_THRESH_HALT] = C_TO_K(82),
-	},
-	.temp_fan_off = C_TO_K(35),
-	.temp_fan_max = C_TO_K(70),
-};
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_D0               \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = C_TO_K(79), \
+			[EC_TEMP_THRESH_HIGH] = 0, \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(81), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = C_TO_K(80), \
+			[EC_TEMP_THRESH_HIGH] = 0, \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(82), \
+		}, \
+		.temp_fan_off = C_TO_K(35), \
+		.temp_fan_max = C_TO_K(70), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_d0 = THERMAL_D0;
 
 /* Akali Remote 1 */
-const static struct ec_thermal_config thermal_d1 = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = C_TO_K(59),
-		[EC_TEMP_THRESH_HIGH] = 0,
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = C_TO_K(60),
-		[EC_TEMP_THRESH_HIGH] = 0,
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = 0,
-	.temp_fan_max = 0,
-};
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_D1               \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = C_TO_K(59), \
+			[EC_TEMP_THRESH_HIGH] = 0, \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = C_TO_K(60), \
+			[EC_TEMP_THRESH_HIGH] = 0, \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+		.temp_fan_off = 0, \
+		.temp_fan_max = 0, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_d1 = THERMAL_D1;
 
 /* Akali Remote 2 */
-const static struct ec_thermal_config thermal_d2 = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = C_TO_K(59),
-		[EC_TEMP_THRESH_HIGH] = 0,
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = C_TO_K(60),
-		[EC_TEMP_THRESH_HIGH] = 0,
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = 0,
-	.temp_fan_max = 0,
-};
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_D2               \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = C_TO_K(59), \
+			[EC_TEMP_THRESH_HIGH] = 0, \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = C_TO_K(60), \
+			[EC_TEMP_THRESH_HIGH] = 0, \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+		.temp_fan_off = 0, \
+		.temp_fan_max = 0, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_d2 = THERMAL_D2;
 
 #define I2C_PMIC_READ(reg, data) \
-		i2c_read8(I2C_PORT_PMIC, TPS650X30_I2C_ADDR1_FLAGS,\
-			  (reg), (data))
+	i2c_read8(I2C_PORT_PMIC, TPS650X30_I2C_ADDR1_FLAGS, (reg), (data))
 #define I2C_PMIC_WRITE(reg, data) \
-		i2c_write8(I2C_PORT_PMIC, TPS650X30_I2C_ADDR1_FLAGS,\
-			   (reg), (data))
+	i2c_write8(I2C_PORT_PMIC, TPS650X30_I2C_ADDR1_FLAGS, (reg), (data))
 
 static void board_pmic_init(void)
 {
@@ -650,8 +718,8 @@ int board_set_active_charge_port(int charge_port)
 			    charge_port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	/* check if we are sourcing VBUS on the port */
 	/* dnojiri: revisit */
-	int is_source = gpio_get_level(charge_port == 0 ?
-			GPIO_USB_C0_5V_EN : GPIO_USB_C1_5V_EN);
+	int is_source = gpio_get_level(charge_port == 0 ? GPIO_USB_C0_5V_EN :
+							  GPIO_USB_C1_5V_EN);
 
 	if (is_real_port && is_source) {
 		CPRINTF("No charging on source port p%d is ", charge_port);
@@ -669,17 +737,19 @@ int board_set_active_charge_port(int charge_port)
 		/* dnojiri: revisit. there is always this assumption that
 		 * battery is present. If not, this may cause brownout. */
 		gpio_set_level(charge_port ? GPIO_USB_C0_CHARGE_L :
-					     GPIO_USB_C1_CHARGE_L, 1);
+					     GPIO_USB_C1_CHARGE_L,
+			       1);
 		/* Enable charging port */
 		gpio_set_level(charge_port ? GPIO_USB_C1_CHARGE_L :
-					     GPIO_USB_C0_CHARGE_L, 0);
+					     GPIO_USB_C0_CHARGE_L,
+			       0);
 	}
 
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
 {
 	/*
 	 * Limit the input current to 96% negotiated limit,
@@ -688,12 +758,10 @@ void board_set_charge_limit(int port, int supplier, int charge_ma,
 	int factor = 96;
 
 	if (oem == PROJECT_AKALI &&
-		(model == MODEL_EKKO || model == MODEL_BARD))
+	    (model == MODEL_EKKO || model == MODEL_BARD))
 		factor = 95;
 	charge_ma = charge_ma * factor / 100;
-	charge_set_input_current_limit(
-			MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT),
-			charge_mv);
+	charge_set_input_current_limit(charge_ma, charge_mv);
 }
 
 void board_hibernate(void)
@@ -706,9 +774,9 @@ void board_hibernate(void)
 }
 
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED1]   = { 3, PWM_CONFIG_DSLEEP, 1200 },
+	[PWM_CH_LED1] = { 3, PWM_CONFIG_DSLEEP, 1200 },
 	[PWM_CH_LED2] = { 5, PWM_CONFIG_DSLEEP, 1200 },
-	[PWM_CH_FAN] = {4, PWM_CONFIG_OPEN_DRAIN, 25000},
+	[PWM_CH_FAN] = { 4, PWM_CONFIG_OPEN_DRAIN, 25000 },
 	/*
 	 * 1.2kHz is a multiple of both 50 and 60. So a video recorder
 	 * (generally designed to ignore either 50 or 60 Hz flicker) will not
@@ -730,23 +798,17 @@ static struct kionix_accel_data g_kx022_data;
 static struct accelgyro_saved_data_t g_bma255_data;
 
 /* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+				       { FLOAT_TO_FP(1), 0, 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
 
-const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+				      { 0, FLOAT_TO_FP(-1), 0 },
+				      { 0, 0, FLOAT_TO_FP(-1) } };
 
-const mat33_fp_t rotation_x180_z90 = {
-	{ 0, FLOAT_TO_FP(-1), 0 },
-	{ FLOAT_TO_FP(-1), 0, 0 },
-	{ 0, 0, FLOAT_TO_FP(-1) }
-};
+const mat33_fp_t rotation_x180_z90 = { { 0, FLOAT_TO_FP(-1), 0 },
+				       { FLOAT_TO_FP(-1), 0, 0 },
+				       { 0, 0, FLOAT_TO_FP(-1) } };
 
 const struct motion_sensor_t lid_accel_1 = {
 	.name = "Lid Accel",
@@ -852,8 +914,7 @@ struct motion_sensor_t motion_sensors[] = {
 unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
 /* Enable or disable input devices, based on chipset state and tablet mode */
-#ifndef TEST_BUILD
-void lid_angle_peripheral_enable(int enable)
+__override void lid_angle_peripheral_enable(int enable)
 {
 	/* If the lid is in 360 position, ignore the lid angle,
 	 * which might be faulty. Disable keyboard.
@@ -862,7 +923,6 @@ void lid_angle_peripheral_enable(int enable)
 		enable = 0;
 	keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
 }
-#endif
 
 /* Called on AP S3 -> S0 transition */
 static void board_chipset_resume(void)
@@ -963,7 +1023,7 @@ static void cbi_init(void)
 DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1);
 
 /* Keyboard scan setting */
-struct keyboard_scan_config keyscan_config = {
+__override struct keyboard_scan_config keyscan_config = {
 	/*
 	 * F3 key scan cycle completed but scan input is not
 	 * charging to logic high when EC start scan next
@@ -982,6 +1042,26 @@ struct keyboard_scan_config keyscan_config = {
 	},
 };
 
+static void anx7447_set_aux_switch(void)
+{
+	const int port = USB_PD_PORT_ANX7447;
+
+	/* Debounce */
+	if (gpio_get_level(GPIO_CCD_MODE_ODL))
+		return;
+
+	CPRINTS("C%d: AUX_SW_SEL=0x%x", port, 0xc);
+	if (tcpc_write(port, ANX7447_REG_TCPC_AUX_SWITCH, 0xc))
+		CPRINTS("C%d: Setting AUX_SW_SEL failed", port);
+}
+DECLARE_DEFERRED(anx7447_set_aux_switch);
+
+void ccd_mode_isr(enum gpio_signal signal)
+{
+	/* Wait 2 seconds until all mux setting is done by PD task */
+	hook_call_deferred(&anx7447_set_aux_switch_data, 2 * SECOND);
+}
+
 static void board_init(void)
 {
 	int reg;
@@ -1002,7 +1082,7 @@ static void board_init(void)
 		       ISL9238_REG_CONTROL3, &reg) == EC_SUCCESS) {
 		reg |= ISL9238_C3_BB_SWITCHING_PERIOD;
 		if (i2c_write16(I2C_PORT_CHARGER, I2C_ADDR_CHARGER_FLAGS,
-			    ISL9238_REG_CONTROL3, reg))
+				ISL9238_REG_CONTROL3, reg))
 			CPRINTF("Failed to set isl9238\n");
 	}
 
@@ -1014,6 +1094,10 @@ static void board_init(void)
 	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_L);
 	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L);
 
+	/* Trigger once to set mux in case CCD cable is already connected. */
+	ccd_mode_isr(GPIO_CCD_MODE_ODL);
+	gpio_enable_interrupt(GPIO_CCD_MODE_ODL);
+
 	/* Enable Accel/Gyro interrupt for convertibles. */
 	if (sku & SKU_ID_MASK_CONVERTIBLE)
 		gpio_enable_interrupt(GPIO_ACCELGYRO3_INT_L);
@@ -1090,14 +1174,13 @@ void board_kblight_init(void)
 	}
 }
 
-enum critical_shutdown board_critical_shutdown_check(
-		struct charge_state_data *curr)
+enum critical_shutdown
+board_critical_shutdown_check(struct charge_state_data *curr)
 {
 	if (oem == PROJECT_VAYNE)
 		return CRITICAL_SHUTDOWN_CUTOFF;
 	else
 		return CRITICAL_SHUTDOWN_HIBERNATE;
-
 }
 
 uint8_t board_set_battery_level_shutdown(void)
diff --git a/board/nami/board.h b/board/nami/board.h
index b12d8133bd..652db4826d 100644
--- a/board/nami/board.h
+++ b/board/nami/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,7 +12,7 @@
  * By default, enable all console messages except ACPI and host event because
  * the sensor stack is generating a lot of activity.
  */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
 
 /* EC */
 #define CONFIG_ADC
@@ -21,14 +21,14 @@
 #define CONFIG_BOARD_VERSION_CBI
 #define CONFIG_BOARD_FORCE_RESET_PIN
 #define CONFIG_CRC8
-#define CONFIG_CROS_BOARD_INFO
+#define CONFIG_CBI_EEPROM
 #define CONFIG_CASE_CLOSED_DEBUG_EXTERNAL
 #define CONFIG_DPTF
-#define CONFIG_FLASH_SIZE 0x80000
+#define CONFIG_FLASH_SIZE_BYTES 0x80000
 #define CONFIG_FPU
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
-#define CONFIG_KEYBOARD_BOARD_CONFIG
+#define CONFIG_I2C_CONTROLLER
+
 #define CONFIG_KEYBOARD_COL2_INVERTED
 #define CONFIG_KEYBOARD_PROTOCOL_8042
 #define CONFIG_KEYBOARD_KEYPAD
@@ -38,7 +38,6 @@
 #define CONFIG_LTO
 #define CONFIG_CHIP_PANIC_BACKUP
 #define CONFIG_PWM
-#define CONFIG_SOFTWARE_PANIC
 #define CONFIG_SPI_FLASH_REGS
 #define CONFIG_SPI_FLASH_W25X40
 #define CONFIG_VBOOT_HASH
@@ -58,9 +57,6 @@
 #define CONFIG_FAN_DYNAMIC
 #define CONFIG_THROTTLE_AP
 #define CONFIG_PWM_KBLIGHT
-#define CONFIG_SUPPRESSED_HOST_COMMANDS \
-	EC_CMD_CONSOLE_SNAPSHOT, EC_CMD_CONSOLE_READ, EC_CMD_PD_GET_LOG_ENTRY, \
-	EC_CMD_MOTION_SENSE_CMD
 
 /* EC console commands */
 #define CONFIG_CMD_ACCELS
@@ -76,10 +72,11 @@
 #define CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET
 #define CONFIG_CHIPSET_HAS_PRE_INIT_CALLBACK
 #define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#define CONFIG_HOST_INTERFACE_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 #define CONFIG_HOSTCMD_FLASH_SPI_INFO
+#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD
 
 /* Battery */
 #define CONFIG_BATTERY_CUT_OFF
@@ -89,8 +86,8 @@
 #define CONFIG_BATTERY_SMART
 #define CONFIG_PWR_STATE_DISCHARGE_FULL
 #define CONFIG_BATTERY_REQUESTS_NIL_WHEN_DEAD
-#undef  CONFIG_BATT_HOST_FULL_FACTOR
-#define CONFIG_BATT_HOST_FULL_FACTOR	100
+#undef CONFIG_BATT_HOST_FULL_FACTOR
+#define CONFIG_BATT_HOST_FULL_FACTOR 100
 
 /* Charger */
 #define CONFIG_CHARGE_MANAGER
@@ -99,12 +96,10 @@
 #define CONFIG_CHARGER
 #define CONFIG_CHARGER_ISL9238
 #define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT 512
-/* EC's thresholds. 3%: boot, 2%: no boot. Required for soft sync. */
-#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON		3
-#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC 1
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON		27000
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT	15000
+#define CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT 512
+#define CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT 512
+#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 27000
+#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT 15000
 /* AP's thresholds. */
 #define CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT 3
 #define CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW 27000
@@ -115,11 +110,11 @@
 #define CONFIG_CMD_CHARGER_ADC_AMON_BMON
 #define CONFIG_HOSTCMD_PD_CONTROL
 #define CONFIG_EXTPOWER_GPIO
-#undef  CONFIG_EXTPOWER_DEBOUNCE_MS
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
 #define CONFIG_EXTPOWER_DEBOUNCE_MS 1000
 #define CONFIG_POWER_BUTTON
 #define CONFIG_POWER_BUTTON_X86
-#undef  CONFIG_POWER_BUTTON_INIT_TIMEOUT
+#undef CONFIG_POWER_BUTTON_INIT_TIMEOUT
 #define CONFIG_POWER_BUTTON_INIT_TIMEOUT 6
 #define CONFIG_POWER_COMMON
 #define CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD 30
@@ -138,7 +133,6 @@
 #define CONFIG_ACCELGYRO_BMI160_INT2_OUTPUT
 #define CONFIG_ACCEL_BMA255
 #define CONFIG_ACCEL_KX022
-#define CONFIG_ACCEL_INTERRUPTS
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
 #define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
@@ -158,7 +152,6 @@
 #define CONFIG_TABLET_MODE
 #define CONFIG_TABLET_MODE_SWITCH
 #define CONFIG_GMR_TABLET_MODE
-#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L
 
 /* USB */
 #define CONFIG_USB_CHARGER
@@ -187,41 +180,38 @@
 #define CONFIG_USBC_VCONN_SWAP
 #define CONFIG_USB_MUX_RUNTIME_CONFIG
 
-
 /* BC 1.2 charger */
 #define CONFIG_BC12_DETECT_PI3USB9281
 #define CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT 2
 
 /* Optional feature to configure npcx chip */
-#define NPCX_UART_MODULE2	1 /* 1:GPIO64/65 as UART */
-#define NPCX_JTAG_MODULE2	0 /* 0:GPIO21/17/16/20 as JTAG */
-#define NPCX_TACH_SEL2		1 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
+#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART */
+#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 as JTAG */
+#define NPCX_TACH_SEL2 1 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
 
 /* I2C ports */
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT0_0
-#define I2C_PORT_TCPC1		NPCX_I2C_PORT0_1
-#define I2C_PORT_USB_CHARGER_0	NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_CHARGER_1	NPCX_I2C_PORT0_1
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT0_0
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT1
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT1
-#define I2C_PORT_PMIC		NPCX_I2C_PORT2
-#define I2C_PORT_KBLIGHT	NPCX_I2C_PORT2
-#define I2C_PORT_GYRO		NPCX_I2C_PORT3
-#define I2C_PORT_ACCEL		NPCX_I2C_PORT3
-#define I2C_PORT_THERMAL	NPCX_I2C_PORT3
-#define I2C_PORT_ALS		NPCX_I2C_PORT3
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0
+#define I2C_PORT_TCPC1 NPCX_I2C_PORT0_1
+#define I2C_PORT_USB_CHARGER_0 NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_CHARGER_1 NPCX_I2C_PORT0_1
+#define I2C_PORT_EEPROM NPCX_I2C_PORT0_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT1
+#define I2C_PORT_CHARGER NPCX_I2C_PORT1
+#define I2C_PORT_PMIC NPCX_I2C_PORT2
+#define I2C_PORT_KBLIGHT NPCX_I2C_PORT2
+#define I2C_PORT_GYRO NPCX_I2C_PORT3
+#define I2C_PORT_ACCEL NPCX_I2C_PORT3
+#define I2C_PORT_THERMAL NPCX_I2C_PORT3
+#define I2C_PORT_ALS NPCX_I2C_PORT3
 
 /* I2C addresses */
-#define I2C_ADDR_MP2949_FLAGS	0x20
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_ADDR_MP2949_FLAGS 0x20
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 
 #ifndef __ASSEMBLER__
 
 /* support factory keyboard test */
 #define CONFIG_KEYBOARD_FACTORY_TEST
-extern const int keyboard_factory_scan_pins[][2];
-extern const int keyboard_factory_scan_pins_used;
 
 #include "gpio_signal.h"
 #include "registers.h"
@@ -293,27 +283,26 @@ enum model_id {
 	MODEL_BARD = 2,
 };
 
-#define SKU_ID_MASK_KBLIGHT	BIT(0)
-#define SKU_ID_MASK_CONVERTIBLE	BIT(9)
-#define SKU_ID_MASK_KEYPAD	BIT(15)
-#define SKU_ID_MASK_UK2		BIT(18)
+#define SKU_ID_MASK_KBLIGHT BIT(0)
+#define SKU_ID_MASK_CONVERTIBLE BIT(9)
+#define SKU_ID_MASK_KEYPAD BIT(15)
+#define SKU_ID_MASK_UK2 BIT(18)
 
 /* TODO(crosbug.com/p/61098): Verify the numbers below. */
 /*
  * delay to turn on the power supply max is ~16ms.
  * delay to turn off the power supply max is about ~180ms.
  */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	250000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* delay to turn on/off vconn */
-#define PD_VCONN_SWAP_DELAY		5000   /* us */
 
 /* Define typical operating power and max power */
-#define PD_OPERATING_POWER_MW		15000
-#define PD_MAX_POWER_MW			70000
-#define PD_MAX_CURRENT_MA		3500
-#define PD_MAX_VOLTAGE_MV		20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 70000
+#define PD_MAX_CURRENT_MA 3500
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Board specific handlers */
 void board_reset_pd_mcu(void);
@@ -329,7 +318,9 @@ extern uint32_t sku;
 extern uint8_t model;
 
 /* SKU_ID[24:31] are dedicated to OEM customization */
-#define CBI_SKU_CUSTOM_FIELD(val)	((val) >> 24)
+#define CBI_SKU_CUSTOM_FIELD(val) ((val) >> 24)
+
+void ccd_mode_isr(enum gpio_signal signal);
 
 #endif /* !__ASSEMBLER__ */
 
diff --git a/board/nami/build.mk b/board/nami/build.mk
index f4bf21113d..8f3a138f56 100644
--- a/board/nami/build.mk
+++ b/board/nami/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/nami/ec.tasklist b/board/nami/ec.tasklist
index 93fcda9f91..99d0f15b70 100644
--- a/board/nami/ec.tasklist
+++ b/board/nami/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nami/gpio.inc b/board/nami/gpio.inc
index 7bc922edaa..124af79f49 100644
--- a/board/nami/gpio.inc
+++ b/board/nami/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -35,6 +35,7 @@ GPIO_INT(USB_C0_BC12_INT_L,	PIN(D, 2), GPIO_INT_FALLING,		usb0_evt)
 GPIO_INT(USB_C1_BC12_INT_L,	PIN(D, 3), GPIO_INT_FALLING,		usb1_evt)
 GPIO_INT(ACCELGYRO3_INT_L,	PIN(3, 6), GPIO_INT_FALLING | GPIO_PULL_UP, bmi160_interrupt)
 GPIO_INT(TABLET_MODE_L,		PIN(7, 2), GPIO_INT_BOTH,		gmr_tablet_switch_isr)
+GPIO_INT(CCD_MODE_ODL,		PIN(6, 3), GPIO_INT_FALLING,		ccd_mode_isr)
 
 GPIO(ENABLE_BACKLIGHT_L,		PIN(6, 7), GPIO_OUT_LOW)	/* LCD backlight */
 GPIO(PP3300_DX_WLAN,		PIN(B, 1), GPIO_OUT_LOW)	/* Enable WLAN 3.3V Power */
@@ -47,7 +48,6 @@ GPIO(EC_PLATFORM_RST,		PIN(4, 5), GPIO_OUT_LOW)	/* EC Reset to LDO_EN */
 GPIO(SYS_RESET_L,		PIN(6, 1), GPIO_ODR_HIGH)	/* Cold Reset to SOC */
 GPIO(PMIC_SLP_SUS_L,		PIN(8, 5), GPIO_OUT_LOW)	/* SLP_SUS# to PMIC */
 GPIO(BATTERY_PRESENT_L,		PIN(3, 4), GPIO_INPUT)		/* Battery Present */
-GPIO(CCD_MODE_ODL,		PIN(6, 3), GPIO_INPUT)		/* Case Closed Debug Mode */
 GPIO(ENTERING_RW,		PIN(7, 6), GPIO_OUTPUT)		/* EC Entering RW */
 GPIO(PMIC_INT_L,		PIN(6, 0), GPIO_INPUT)		/* PMIC interrupt */
 #ifndef CONFIG_POWER_S0IX
diff --git a/board/nami/led.c b/board/nami/led.c
index 17af4d5f82..cf5c864045 100644
--- a/board/nami/led.c
+++ b/board/nami/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -25,10 +25,10 @@
  * connected to a regular GPIO pin.
  */
 
-#include "cros_board_info.h"
 #include "charge_state.h"
 #include "chipset.h"
 #include "console.h"
+#include "cros_board_info.h"
 #include "ec_commands.h"
 #include "gpio.h"
 #include "hooks.h"
@@ -38,8 +38,8 @@
 #include "timer.h"
 #include "util.h"
 
-const enum ec_led_id supported_led_ids[] = {
-		EC_LED_ID_BATTERY_LED, EC_LED_ID_POWER_LED};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 enum led_color {
@@ -79,19 +79,19 @@ struct led_pattern {
 	uint8_t pulse;
 };
 
-#define PULSE_NO		0
-#define PULSE(interval)		(BIT(7) | (interval))
-#define BLINK(interval) 	(interval)
-#define ALTERNATE(interval)	(BIT(6) | (interval))
-#define IS_PULSING(pulse)	((pulse) & 0x80)
-#define IS_ALTERNATE(pulse)	((pulse) & 0x40)
-#define PULSE_INTERVAL(pulse)	(((pulse) & 0x3f) * 100 * MSEC)
+#define PULSE_NO 0
+#define PULSE(interval) (BIT(7) | (interval))
+#define BLINK(interval) (interval)
+#define ALTERNATE(interval) (BIT(6) | (interval))
+#define IS_PULSING(pulse) ((pulse)&0x80)
+#define IS_ALTERNATE(pulse) ((pulse)&0x40)
+#define PULSE_INTERVAL(pulse) (((pulse)&0x3f) * 100 * MSEC)
 
 /* 40 msec for nice and smooth transition. */
-#define LED_PULSE_TICK_US	(40 * MSEC)
+#define LED_PULSE_TICK_US (40 * MSEC)
 
 typedef struct led_pattern led_patterns[LED_CHARGE_STATE_COUNT]
-					[LED_POWER_STATE_COUNT];
+				       [LED_POWER_STATE_COUNT];
 
 /*
  * Nami/Vayne - One dual color LED:
@@ -105,11 +105,17 @@ typedef struct led_pattern led_patterns[LED_CHARGE_STATE_COUNT]
  */
 const static led_patterns battery_pattern_0 = {
 	/* discharging: s0, s3, s5 */
-	{{LED_WHITE, PULSE_NO}, {LED_WHITE, PULSE(10)}, {LED_OFF,  PULSE_NO}},
+	{ { LED_WHITE, PULSE_NO },
+	  { LED_WHITE, PULSE(10) },
+	  { LED_OFF, PULSE_NO } },
 	/* charging: s0, s3, s5 */
-	{{LED_AMBER, PULSE_NO}, {LED_AMBER, PULSE_NO}, {LED_AMBER, PULSE_NO}},
+	{ { LED_AMBER, PULSE_NO },
+	  { LED_AMBER, PULSE_NO },
+	  { LED_AMBER, PULSE_NO } },
 	/* full: s0, s3, s5 */
-	{{LED_WHITE, PULSE_NO}, {LED_WHITE, PULSE_NO}, {LED_WHITE, PULSE_NO}},
+	{ { LED_WHITE, PULSE_NO },
+	  { LED_WHITE, PULSE_NO },
+	  { LED_WHITE, PULSE_NO } },
 };
 
 /*
@@ -117,11 +123,15 @@ const static led_patterns battery_pattern_0 = {
  */
 const static led_patterns battery_pattern_1 = {
 	/* discharging: s0, s3, s5 */
-	{{LED_OFF,   PULSE_NO}, {LED_OFF,   PULSE_NO}, {LED_OFF,   PULSE_NO}},
+	{ { LED_OFF, PULSE_NO }, { LED_OFF, PULSE_NO }, { LED_OFF, PULSE_NO } },
 	/* charging: s0, s3, s5 */
-	{{LED_AMBER, PULSE_NO}, {LED_AMBER, PULSE_NO}, {LED_AMBER, PULSE_NO}},
+	{ { LED_AMBER, PULSE_NO },
+	  { LED_AMBER, PULSE_NO },
+	  { LED_AMBER, PULSE_NO } },
 	/* full: s0, s3, s5 */
-	{{LED_WHITE, PULSE_NO}, {LED_WHITE, PULSE_NO}, {LED_WHITE, PULSE_NO}},
+	{ { LED_WHITE, PULSE_NO },
+	  { LED_WHITE, PULSE_NO },
+	  { LED_WHITE, PULSE_NO } },
 };
 
 /*
@@ -132,11 +142,15 @@ const static led_patterns battery_pattern_1 = {
  */
 const static led_patterns battery_pattern_2 = {
 	/* discharging: s0, s3, s5 */
-	{{LED_OFF,   PULSE_NO}, {LED_OFF,   PULSE_NO}, {LED_OFF,   PULSE_NO}},
+	{ { LED_OFF, PULSE_NO }, { LED_OFF, PULSE_NO }, { LED_OFF, PULSE_NO } },
 	/* charging: s0, s3, s5 */
-	{{LED_AMBER, PULSE_NO}, {LED_AMBER, PULSE_NO}, {LED_AMBER, PULSE_NO}},
+	{ { LED_AMBER, PULSE_NO },
+	  { LED_AMBER, PULSE_NO },
+	  { LED_AMBER, PULSE_NO } },
 	/* full: s0, s3, s5 */
-	{{LED_WHITE, PULSE_NO}, {LED_WHITE, PULSE_NO}, {LED_WHITE, PULSE_NO}},
+	{ { LED_WHITE, PULSE_NO },
+	  { LED_WHITE, PULSE_NO },
+	  { LED_WHITE, PULSE_NO } },
 };
 
 /*
@@ -144,11 +158,17 @@ const static led_patterns battery_pattern_2 = {
  */
 const static led_patterns power_pattern_1 = {
 	/* discharging: s0, s3, s5 */
-	{{LED_WHITE, PULSE_NO}, {LED_WHITE, BLINK(10)}, {LED_OFF, PULSE_NO}},
+	{ { LED_WHITE, PULSE_NO },
+	  { LED_WHITE, BLINK(10) },
+	  { LED_OFF, PULSE_NO } },
 	/* charging: s0, s3, s5 */
-	{{LED_WHITE, PULSE_NO}, {LED_WHITE, BLINK(10)}, {LED_OFF, PULSE_NO}},
+	{ { LED_WHITE, PULSE_NO },
+	  { LED_WHITE, BLINK(10) },
+	  { LED_OFF, PULSE_NO } },
 	/* full: s0, s3, s5 */
-	{{LED_WHITE, PULSE_NO}, {LED_WHITE, BLINK(10)}, {LED_OFF, PULSE_NO}},
+	{ { LED_WHITE, PULSE_NO },
+	  { LED_WHITE, BLINK(10) },
+	  { LED_OFF, PULSE_NO } },
 };
 
 /*
@@ -159,11 +179,17 @@ const static led_patterns power_pattern_1 = {
  */
 const static led_patterns power_pattern_2 = {
 	/* discharging: s0, s3, s5 */
-	{{LED_WHITE, 0}, {LED_WHITE, ALTERNATE(BLINK(10))}, {LED_OFF, 0}},
+	{ { LED_WHITE, 0 },
+	  { LED_WHITE, ALTERNATE(BLINK(10)) },
+	  { LED_OFF, 0 } },
 	/* charging: s0, s3, s5 */
-	{{LED_WHITE, 0}, {LED_WHITE, ALTERNATE(BLINK(10))}, {LED_OFF, 0}},
+	{ { LED_WHITE, 0 },
+	  { LED_WHITE, ALTERNATE(BLINK(10)) },
+	  { LED_OFF, 0 } },
 	/* full: s0, s3, s5 */
-	{{LED_WHITE, 0}, {LED_WHITE, ALTERNATE(BLINK(10))}, {LED_OFF, 0}},
+	{ { LED_WHITE, 0 },
+	  { LED_WHITE, ALTERNATE(BLINK(10)) },
+	  { LED_OFF, 0 } },
 };
 
 /*
@@ -178,30 +204,42 @@ const static led_patterns power_pattern_2 = {
  */
 const static led_patterns battery_pattern_3 = {
 	/* discharging: s0, s3, s5 */
-	{{LED_WHITE, 0}, {LED_AMBER, ALTERNATE(BLINK(10))}, {LED_OFF, 0}},
+	{ { LED_WHITE, 0 },
+	  { LED_AMBER, ALTERNATE(BLINK(10)) },
+	  { LED_OFF, 0 } },
 	/* charging: s0, s3, s5 */
-	{{LED_AMBER, PULSE_NO}, {LED_AMBER, PULSE_NO}, {LED_AMBER,  PULSE_NO}},
+	{ { LED_AMBER, PULSE_NO },
+	  { LED_AMBER, PULSE_NO },
+	  { LED_AMBER, PULSE_NO } },
 	/* full: s0, s3, s5 */
-	{{LED_WHITE, PULSE_NO}, {LED_WHITE, PULSE_NO}, {LED_WHITE,  PULSE_NO}},
+	{ { LED_WHITE, PULSE_NO },
+	  { LED_WHITE, PULSE_NO },
+	  { LED_WHITE, PULSE_NO } },
 };
 
 const static led_patterns battery_pattern_4 = {
 	/* discharging: s0, s3, s5 */
-	{{LED_WHITE, PULSE_NO}, {LED_WHITE, BLINK(10)}, {LED_OFF, PULSE_NO}},
+	{ { LED_WHITE, PULSE_NO },
+	  { LED_WHITE, BLINK(10) },
+	  { LED_OFF, PULSE_NO } },
 	/* charging: s0, s3, s5 */
-	{{LED_AMBER, PULSE_NO}, {LED_AMBER, PULSE_NO},  {LED_AMBER, PULSE_NO}},
+	{ { LED_AMBER, PULSE_NO },
+	  { LED_AMBER, PULSE_NO },
+	  { LED_AMBER, PULSE_NO } },
 	/* full: s0, s3, s5 */
-	{{LED_WHITE, PULSE_NO}, {LED_WHITE, PULSE_NO},  {LED_WHITE, PULSE_NO}},
+	{ { LED_WHITE, PULSE_NO },
+	  { LED_WHITE, PULSE_NO },
+	  { LED_WHITE, PULSE_NO } },
 };
 
 /* Patterns for battery LED and power LED. Initialized at run-time. */
 static led_patterns const *patterns[2];
 /* Pattern for battery error. Only blinking battery LED is supported. */
-static struct led_pattern battery_error = {LED_AMBER, BLINK(10)};
+static struct led_pattern battery_error = { LED_AMBER, BLINK(10) };
 /* Pattern for low state of charge. Only battery LED is supported. */
-static struct led_pattern low_battery = {LED_WHITE, BLINK(10)};
+static struct led_pattern low_battery = { LED_WHITE, BLINK(10) };
 /* Pattern for factory mode. Blinking 2-color battery LED. */
-static struct led_pattern battery_factory = {LED_FACTORY, BLINK(20)};
+static struct led_pattern battery_factory = { LED_FACTORY, BLINK(20) };
 static int low_battery_soc;
 static void led_charge_hook(void);
 static enum led_power_state power_state;
@@ -222,7 +260,7 @@ static void led_init(void)
 			patterns[1] = &power_pattern_1;
 		}
 		battery_error.pulse = BLINK(5);
-		low_battery_soc = 100;  /* 10.0% */
+		low_battery_soc = 100; /* 10.0% */
 		break;
 	case PROJECT_PANTHEON:
 		patterns[0] = &battery_pattern_2;
@@ -452,7 +490,7 @@ void config_led(enum ec_led_id id, enum led_charge_state charge)
 
 	pattern = patterns[id];
 	if (!pattern)
-		return;	/* This LED isn't present */
+		return; /* This LED isn't present */
 
 	start_tick(id, &(*pattern)[charge][power_state]);
 }
@@ -466,47 +504,48 @@ void config_leds(enum led_charge_state charge)
 static void call_handler(void)
 {
 	int soc;
-	enum charge_state cs;
+	enum led_pwr_state cs;
 
 	if (!led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
 		return;
 
-	cs = charge_get_state();
+	cs = led_pwr_get_state();
 	soc = charge_get_display_charge();
 	if (soc < 0)
-		cs = PWR_STATE_ERROR;
+		cs = LED_PWRS_ERROR;
 
 	switch (cs) {
-	case PWR_STATE_DISCHARGE:
-	case PWR_STATE_DISCHARGE_FULL:
+	case LED_PWRS_DISCHARGE:
+	case LED_PWRS_DISCHARGE_FULL:
 		if (soc < low_battery_soc)
 			start_tick(EC_LED_ID_BATTERY_LED, &low_battery);
 		else
 			config_led(EC_LED_ID_BATTERY_LED, LED_STATE_DISCHARGE);
 		config_led(EC_LED_ID_POWER_LED, LED_STATE_DISCHARGE);
 		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-	case PWR_STATE_CHARGE:
+	case LED_PWRS_CHARGE_NEAR_FULL:
+	case LED_PWRS_CHARGE:
 		if (soc >= 1000)
 			config_leds(LED_STATE_FULL);
 		else
 			config_leds(LED_STATE_CHARGE);
 		break;
-	case PWR_STATE_ERROR:
+	case LED_PWRS_ERROR:
 		/* It doesn't matter what 'charge' state we pass because power
 		 * LED (if it exists) is orthogonal to battery state. */
 		config_led(EC_LED_ID_POWER_LED, 0);
 		led_alert(1);
 		break;
-	case PWR_STATE_IDLE:
-		/* External power connected in IDLE. This is also used to show
-		 * factory mode when 'ectool chargecontrol idle' is run during
-		 * factory process. */
-		if (charge_get_flags() & CHARGE_FLAG_FORCE_IDLE)
-			led_factory(1);
+	case LED_PWRS_IDLE:
+		/* External power connected in IDLE. */
 		break;
-	default:
-		;
+	case LED_PWRS_FORCED_IDLE:
+		/* This is used to show factory mode when
+		 * 'ectool chargecontrol idle' is run during factory process.
+		 */
+		led_factory(1);
+		break;
+	default:;
 	}
 }
 
@@ -548,7 +587,7 @@ static void print_config(enum ec_led_id id)
 	ccprintf("  Interval:%d\n", tick[id].interval);
 }
 
-static int command_led(int argc, char **argv)
+static int command_led(int argc, const char **argv)
 {
 	enum ec_led_id id = EC_LED_ID_BATTERY_LED;
 	static int alert = 0;
@@ -587,9 +626,10 @@ static int command_led(int argc, char **argv)
 	}
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(led, command_led,
-			"[debug|red|green|amber|off|alert|s0|s3|s5|conf|factory]",
-			"Turn on/off LED.");
+DECLARE_CONSOLE_COMMAND(
+	led, command_led,
+	"[debug|red|green|amber|off|alert|s0|s3|s5|conf|factory]",
+	"Turn on/off LED.");
 
 void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
 {
diff --git a/board/nami/usb_pd_policy.c b/board/nami/usb_pd_policy.c
index c1d5591d7c..e8111e7cbd 100644
--- a/board/nami/usb_pd_policy.c
+++ b/board/nami/usb_pd_policy.c
@@ -1,15 +1,15 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "atomic.h"
-#include "extpower.h"
 #include "charge_manager.h"
 #include "chipset.h"
 #include "common.h"
 #include "console.h"
 #include "driver/tcpm/ps8xxx.h"
+#include "extpower.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "host_command.h"
@@ -17,17 +17,17 @@
 #include "system.h"
 #include "task.h"
 #include "timer.h"
-#include "util.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
+#include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT];
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5,
-							TYPEC_RP_1A5};
+static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5,
+							 TYPEC_RP_1A5 };
 int board_vbus_source_enabled(int port)
 {
 	return vbus_en[port];
@@ -52,8 +52,7 @@ __override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
 int pd_set_power_supply_ready(int port)
 {
 	/* Disable charging */
-	gpio_set_level(port ? GPIO_USB_C1_CHARGE_L :
-			      GPIO_USB_C0_CHARGE_L, 1);
+	gpio_set_level(port ? GPIO_USB_C1_CHARGE_L : GPIO_USB_C0_CHARGE_L, 1);
 
 	/* Ensure we advertise the proper available current quota */
 	charge_manager_source_port(port, 1);
@@ -103,8 +102,7 @@ int pd_check_vconn_swap(int port)
 	return gpio_get_level(GPIO_PMIC_SLP_SUS_L);
 }
 
-__override void pd_execute_data_swap(int port,
-				     enum pd_data_role data_role)
+__override void pd_execute_data_swap(int port, enum pd_data_role data_role)
 {
 	/* Only port 0 supports device mode. */
 	if (port != 0)
diff --git a/board/nami/vif_override.xml b/board/nami/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/nami/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/nautilus/battery.c b/board/nautilus/battery.c
index 642497cdfe..8f0c4baa4e 100644
--- a/board/nautilus/battery.c
+++ b/board/nautilus/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -17,22 +17,24 @@
 static enum battery_present batt_pres_prev = BP_NOT_SURE;
 
 /* Shutdown mode parameters to write to manufacturer access register */
-#define SB_SHIP_MODE_REG	SB_MANUFACTURER_ACCESS
-#define SB_SHUTDOWN_DATA	0x0010
+#define SB_SHIP_MODE_REG SB_MANUFACTURER_ACCESS
+#define SB_SHUTDOWN_DATA 0x0010
 
 /*
  * Unlike other smart batteries, Nautilus battery uses different bit fields
  * in manufacturer access register for the conditions of the CHG/DSG FETs.
  */
-#define BATFETS_SHIFT		(14)
-#define BATFETS_MASK		(0x3)
-#define BATFETS_DISABLED	(0x2)
+#define BATFETS_SHIFT (14)
+#define BATFETS_MASK (0x3)
+#define BATFETS_DISABLED (0x2)
 
-#define CHARGING_VOLTAGE_MV_SAFE	8400
-#define CHARGING_CURRENT_MA_SAFE	1500
+#define CHARGING_VOLTAGE_MV_SAFE 8400
+#define CHARGING_CURRENT_MA_SAFE 1500
+#define CHARGING_VOLTAGE_MV_ADJUST 8600
+#define CHARGING_CURRENT_MA_ADJUST 3200
 
 static const struct battery_info info = {
-	.voltage_max = 8700,
+	.voltage_max = 8600,
 	.voltage_normal = 7700,
 	.voltage_min = 6000,
 	/* Pre-charge values. */
@@ -88,7 +90,11 @@ int charger_profile_override(struct charge_state_data *curr)
 	} temp_zone;
 
 	current = curr->requested_current;
+	if (current > CHARGING_CURRENT_MA_ADJUST)
+		current = CHARGING_CURRENT_MA_ADJUST;
 	voltage = curr->requested_voltage;
+	if (voltage > CHARGING_VOLTAGE_MV_ADJUST)
+		voltage = CHARGING_VOLTAGE_MV_ADJUST;
 	bat_temp_c = curr->batt.temperature - 2731;
 
 	/*
@@ -160,8 +166,9 @@ static int battery_init(void)
 {
 	int batt_status;
 
-	return battery_status(&batt_status) ? 0 :
-		!!(batt_status & STATUS_INITIALIZED);
+	return battery_status(&batt_status) ?
+		       0 :
+		       !!(batt_status & STATUS_INITIALIZED);
 }
 
 /*
@@ -185,8 +192,7 @@ static int battery_check_disconnect(void)
 	if (rv)
 		return BATTERY_DISCONNECT_ERROR;
 
-	if (((batt_mfgacc >> BATFETS_SHIFT) & BATFETS_MASK) ==
-	    BATFETS_DISABLED)
+	if (((batt_mfgacc >> BATFETS_SHIFT) & BATFETS_MASK) == BATFETS_DISABLED)
 		return BATTERY_DISCONNECTED;
 
 	return BATTERY_NOT_DISCONNECTED;
@@ -221,4 +227,3 @@ enum battery_present battery_is_present(void)
 	batt_pres_prev = batt_pres;
 	return batt_pres;
 }
-
diff --git a/board/nautilus/board.c b/board/nautilus/board.c
index e538010814..c3569ce56b 100644
--- a/board/nautilus/board.c
+++ b/board/nautilus/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,25 +6,25 @@
 /* Poppy board-specific configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
+#include "battery_smart.h"
 #include "bd99992gw.h"
 #include "board_config.h"
-#include "battery_smart.h"
 #include "button.h"
 #include "charge_manager.h"
-#include "charge_state.h"
 #include "charge_ramp.h"
+#include "charge_state.h"
 #include "charger.h"
 #include "chipset.h"
 #include "console.h"
-#include "driver/accelgyro_bmi_common.h"
 #include "driver/accel_bma2x2.h"
+#include "driver/accelgyro_bmi_common.h"
 #include "driver/baro_bmp280.h"
 #include "driver/charger/isl923x.h"
 #include "driver/tcpm/ps8xxx.h"
 #include "driver/tcpm/tcpci.h"
 #include "driver/tcpm/tcpm.h"
 #include "driver/temp_sensor/bd99992gw.h"
+#include "espi.h"
 #include "extpower.h"
 #include "gpio.h"
 #include "hooks.h"
@@ -35,6 +35,7 @@
 #include "math_util.h"
 #include "motion_lid.h"
 #include "motion_sense.h"
+#include "panic.h"
 #include "pi3usb9281.h"
 #include "power.h"
 #include "power_button.h"
@@ -51,10 +52,9 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 #include "util.h"
-#include "espi.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
@@ -76,9 +76,9 @@ static void vbus_discharge_handler(void)
 {
 	if (system_get_board_version() >= 2) {
 		pd_set_vbus_discharge(0,
-				gpio_get_level(GPIO_USB_C0_VBUS_WAKE_L));
+				      gpio_get_level(GPIO_USB_C0_VBUS_WAKE_L));
 		pd_set_vbus_discharge(1,
-				gpio_get_level(GPIO_USB_C1_VBUS_WAKE_L));
+				      gpio_get_level(GPIO_USB_C1_VBUS_WAKE_L));
 	}
 }
 DECLARE_DEFERRED(vbus_discharge_handler);
@@ -103,14 +103,15 @@ void vbus1_evt(enum gpio_signal signal)
 
 void usb0_evt(enum gpio_signal signal)
 {
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
 }
 
 void usb1_evt(enum gpio_signal signal)
 {
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12, 0);
+	usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
 }
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /* Hibernate wake configuration */
@@ -123,26 +124,47 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* Base detection */
-	[ADC_BASE_DET] = {"BASE_DET", NPCX_ADC_CH0,
-			  ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_BASE_DET] = { "BASE_DET", NPCX_ADC_CH0, ADC_MAX_VOLT,
+			   ADC_READ_MAX + 1, 0 },
 	/* Vbus sensing (10x voltage divider). */
-	[ADC_VBUS] = {"VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
+	[ADC_VBUS] = { "VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT * 10,
+		       ADC_READ_MAX + 1, 0 },
 	/*
 	 * Adapter current output or battery charging/discharging current (uV)
 	 * 18x amplification on charger side.
 	 */
-	[ADC_AMON_BMON] = {"AMON_BMON", NPCX_ADC_CH1, ADC_MAX_VOLT*1000/18,
-			   ADC_READ_MAX+1, 0},
+	[ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH1, ADC_MAX_VOLT * 1000 / 18,
+			    ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* I2C port map */
-const struct i2c_port_t i2c_ports[]  = {
-	{"tcpc0",     NPCX_I2C_PORT0_0, 400, GPIO_I2C0_0_SCL, GPIO_I2C0_0_SDA},
-	{"tcpc1",     NPCX_I2C_PORT0_1, 400, GPIO_I2C0_1_SCL, GPIO_I2C0_1_SDA},
-	{"charger",   NPCX_I2C_PORT1,   100, GPIO_I2C1_SCL,   GPIO_I2C1_SDA},
-	{"pmic",      NPCX_I2C_PORT2,   400, GPIO_I2C2_SCL,   GPIO_I2C2_SDA},
-	{"accelgyro", NPCX_I2C_PORT3,   400, GPIO_I2C3_SCL,   GPIO_I2C3_SDA},
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "tcpc0",
+	  .port = NPCX_I2C_PORT0_0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_0_SCL,
+	  .sda = GPIO_I2C0_0_SDA },
+	{ .name = "tcpc1",
+	  .port = NPCX_I2C_PORT0_1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_1_SCL,
+	  .sda = GPIO_I2C0_1_SDA },
+	{ .name = "charger",
+	  .port = NPCX_I2C_PORT1,
+	  .kbps = 100,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "pmic",
+	  .port = NPCX_I2C_PORT2,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "accelgyro",
+	  .port = NPCX_I2C_PORT3,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -152,7 +174,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = NPCX_I2C_PORT0_0,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
 		},
 		.drv = &ps8xxx_tcpm_drv,
 	},
@@ -160,22 +182,28 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = NPCX_I2C_PORT0_1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
 		},
 		.drv = &ps8xxx_tcpm_drv,
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	},
 	{
-		.usb_port = 1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	}
 };
 
@@ -193,7 +221,7 @@ BUILD_ASSERT(ARRAY_SIZE(pi3usb9281_chips) ==
 	     CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT);
 
 const int usb_port_enable[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT] = {
-        GPIO_USB1_ENABLE,
+	GPIO_USB1_ENABLE,
 };
 
 const struct charger_config_t chg_chips[] = {
@@ -230,9 +258,10 @@ void board_tcpc_init(void)
 	 * HPD pulse to enable video path
 	 */
 	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		usb_mux_hpd_update(port, 0, 0);
+		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
 
 uint16_t tcpc_get_alert_status(void)
 {
@@ -252,13 +281,13 @@ uint16_t tcpc_get_alert_status(void)
 }
 
 const struct temp_sensor_t temp_sensors[] = {
-	{"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0},
+	{ "Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0 },
 
 	/* These BD99992GW temp sensors are only readable in S0 */
-	{"Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM1},
-	{"DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM2},
+	{ "Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM1 },
+	{ "DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM2 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -274,8 +303,8 @@ static void board_report_pmic_fault(const char *str)
 	uint32_t info;
 
 	/* RESETIRQ1 -- Bit 4: VRFAULT */
-	if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x8, &vrfault)
-	    != EC_SUCCESS)
+	if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x8, &vrfault) !=
+	    EC_SUCCESS)
 		return;
 
 	if (!(vrfault & BIT(4)))
@@ -384,8 +413,7 @@ static void board_pmic_enable_slp_s0_vr_decay(void)
 	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x38, 0x7a);
 }
 
-__override void power_board_handle_host_sleep_event(
-		enum host_sleep_event state)
+__override void power_board_handle_host_sleep_event(enum host_sleep_event state)
 {
 	if (state == HOST_SLEEP_EVENT_S0IX_SUSPEND)
 		board_pmic_enable_slp_s0_vr_decay();
@@ -433,13 +461,13 @@ static void board_init(void)
 	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L);
 
 	/* Level of sensor's I2C and interrupt are 3.3V on proto board */
-	if(system_get_board_version() < 2) {
+	if (system_get_board_version() < 2) {
 		/* ACCELGYRO3_INT_L */
 		gpio_set_flags(GPIO_ACCELGYRO3_INT_L, GPIO_INT_FALLING);
 		/* I2C3_SCL / I2C3_SDA */
 		gpio_set_flags(GPIO_I2C3_SCL, GPIO_INPUT);
 		gpio_set_flags(GPIO_I2C3_SDA, GPIO_INPUT);
-        }
+	}
 
 	/* Enable Gyro interrupts */
 	gpio_enable_interrupt(GPIO_ACCELGYRO3_INT_L);
@@ -489,35 +517,17 @@ int board_set_active_charge_port(int charge_port)
 	} else {
 		/* Make sure non-charging port is disabled */
 		gpio_set_level(charge_port ? GPIO_USB_C0_CHARGE_L :
-					     GPIO_USB_C1_CHARGE_L, 1);
+					     GPIO_USB_C1_CHARGE_L,
+			       1);
 		/* Enable charging port */
 		gpio_set_level(charge_port ? GPIO_USB_C1_CHARGE_L :
-					     GPIO_USB_C0_CHARGE_L, 0);
+					     GPIO_USB_C0_CHARGE_L,
+			       0);
 	}
 
 	return EC_SUCCESS;
 }
 
-/**
- * Set the charge limit based upon desired maximum.
- *
- * @param port          Port number.
- * @param supplier      Charge supplier type.
- * @param charge_ma     Desired charge limit (mA).
- * @param charge_mv     Negotiated charge voltage (mV).
- */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-        /*
-         * Limit the input current to 96% negotiated limit,
-         * to account for the charger chip margin.
-         */
-	charge_ma = charge_ma * 96 / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-				   CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
-
 /**
  * Return the maximum allowed input current
  */
@@ -541,7 +551,7 @@ void board_hibernate(void)
 	CPRINTS("Triggering PMIC shutdown.");
 	uart_flush_output();
 
-    /* Trigger PMIC shutdown. */
+	/* Trigger PMIC shutdown. */
 	if (i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x49, 0x01)) {
 		/*
 		 * If we can't tell the PMIC to shutdown, instead reset
@@ -595,17 +605,13 @@ static struct bmi_drv_data_t g_bmi160_data;
 static struct accelgyro_saved_data_t g_bma255_data;
 
 /* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0 },
-	{ 0,  FLOAT_TO_FP(1), 0 },
-	{ 0, 0, FLOAT_TO_FP(-1) }
-};
+const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				       { 0, FLOAT_TO_FP(1), 0 },
+				       { 0, 0, FLOAT_TO_FP(-1) } };
 
-const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0 },
-	{ 0,  FLOAT_TO_FP(1), 0 },
-	{ 0, 0, FLOAT_TO_FP(-1) }
-};
+const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				      { 0, FLOAT_TO_FP(1), 0 },
+				      { 0, 0, FLOAT_TO_FP(-1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
@@ -681,8 +687,7 @@ struct motion_sensor_t motion_sensors[] = {
 const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
 /* Enable or disable input devices, based on chipset state and tablet mode */
-#ifndef TEST_BUILD
-void lid_angle_peripheral_enable(int enable)
+__override void lid_angle_peripheral_enable(int enable)
 {
 	/* If the lid is in 360 position, ignore the lid angle,
 	 * which might be faulty. Disable keyboard.
@@ -691,7 +696,6 @@ void lid_angle_peripheral_enable(int enable)
 		enable = 0;
 	keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
 }
-#endif
 
 static void board_chipset_reset(void)
 {
@@ -751,20 +755,19 @@ int board_has_working_reset_flags(void)
  * I2C callbacks to ensure bus free time for battery I2C transactions is at
  * least 5ms.
  */
-#define BATTERY_FREE_MIN_DELTA_US		(5 * MSEC)
+#define BATTERY_FREE_MIN_DELTA_US (5 * MSEC)
 static timestamp_t battery_last_i2c_time;
 
-static int is_battery_i2c(const int port, const uint16_t slave_addr_flags)
+static int is_battery_i2c(const int port, const uint16_t addr_flags)
 {
-	return (port == I2C_PORT_BATTERY)
-		&& (slave_addr_flags == BATTERY_ADDR_FLAGS);
+	return (port == I2C_PORT_BATTERY) && (addr_flags == BATTERY_ADDR_FLAGS);
 }
 
-void i2c_start_xfer_notify(const int port, const uint16_t slave_addr_flags)
+void i2c_start_xfer_notify(const int port, const uint16_t addr_flags)
 {
 	unsigned int time_delta_us;
 
-	if (!is_battery_i2c(port, slave_addr_flags))
+	if (!is_battery_i2c(port, addr_flags))
 		return;
 
 	time_delta_us = time_since32(battery_last_i2c_time);
@@ -774,9 +777,9 @@ void i2c_start_xfer_notify(const int port, const uint16_t slave_addr_flags)
 	usleep(BATTERY_FREE_MIN_DELTA_US - time_delta_us);
 }
 
-void i2c_end_xfer_notify(const int port, const uint16_t slave_addr_flags)
+void i2c_end_xfer_notify(const int port, const uint16_t addr_flags)
 {
-	if (!is_battery_i2c(port, slave_addr_flags))
+	if (!is_battery_i2c(port, addr_flags))
 		return;
 
 	battery_last_i2c_time = get_time();
diff --git a/board/nautilus/board.h b/board/nautilus/board.h
index 958e3d202c..e3a136c261 100644
--- a/board/nautilus/board.h
+++ b/board/nautilus/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,16 +17,15 @@
 /* EC */
 #define CONFIG_ADC
 #define CONFIG_BACKLIGHT_LID
-#define CONFIG_BOARD_VERSION_CUSTOM
 #define CONFIG_BOARD_FORCE_RESET_PIN
 #define CONFIG_CASE_CLOSED_DEBUG_EXTERNAL
 #define CONFIG_DPTF
 #define CONFIG_DPTF_MOTION_LID_NO_GMR_SENSOR
 #define CONFIG_DPTF_MULTI_PROFILE
-#define CONFIG_FLASH_SIZE 0x80000
+#define CONFIG_FLASH_SIZE_BYTES 0x80000
 #define CONFIG_FPU
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_CONTROLLER
 #define CONFIG_I2C_XFER_BOARD_CALLBACK
 #define CONFIG_KEYBOARD_COL2_INVERTED
 #define CONFIG_KEYBOARD_PROTOCOL_8042
@@ -35,7 +34,6 @@
 #define CONFIG_LOW_POWER_IDLE
 #define CONFIG_LTO
 #define CONFIG_CHIP_PANIC_BACKUP
-#define CONFIG_SOFTWARE_PANIC
 #define CONFIG_SPI_FLASH_REGS
 #define CONFIG_SPI_FLASH_W25X40
 #define CONFIG_VBOOT_HASH
@@ -63,9 +61,10 @@
 #define CONFIG_CHIPSET_SKYLAKE
 #define CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET
 #define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#define CONFIG_HOST_INTERFACE_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
+#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD
 
 /* Battery */
 #define CONFIG_BATTERY_CUT_OFF
@@ -80,17 +79,19 @@
 #define CONFIG_CHARGER
 #define CONFIG_CHARGER_ISL9238
 #define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT 512
-#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 2
+#define CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT 512
+#define CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT 512
 #define CONFIG_CHARGER_PROFILE_OVERRIDE
 #define CONFIG_CHARGER_PSYS
 #define CONFIG_CHARGER_SENSE_RESISTOR 10
 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 20
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 4 /* margining */
 #define CONFIG_CMD_CHARGER_ADC_AMON_BMON
 #define CONFIG_HOSTCMD_PD_CONTROL
 #define CONFIG_EXTPOWER_GPIO
-#undef   CONFIG_EXTPOWER_DEBOUNCE_MS
-#define  CONFIG_EXTPOWER_DEBOUNCE_MS 1000
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
+#define CONFIG_EXTPOWER_DEBOUNCE_MS 1000
 #define CONFIG_POWER_BUTTON
 #define CONFIG_POWER_BUTTON_X86
 #define CONFIG_POWER_COMMON
@@ -117,7 +118,6 @@
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 #define CONFIG_ACCELGYRO_BMI160_INT2_OUTPUT
 #define CONFIG_ACCEL_BMA255
-#define CONFIG_ACCEL_INTERRUPTS
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
 #define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
@@ -130,7 +130,7 @@
 /* Depends on how fast the AP boots and typical ODRs */
 #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
 
-#undef  CONFIG_UART_TX_BUF_SIZE
+#undef CONFIG_UART_TX_BUF_SIZE
 #define CONFIG_UART_TX_BUF_SIZE 2048
 
 #define CONFIG_TABLET_MODE
@@ -164,27 +164,27 @@
 #define CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT 2
 
 /* Optional feature to configure npcx chip */
-#define NPCX_UART_MODULE2	1 /* 1:GPIO64/65 as UART */
-#define NPCX_JTAG_MODULE2	0 /* 0:GPIO21/17/16/20 as JTAG */
-#define NPCX_TACH_SEL2		0 /* 0:GPIO40/73 as TACH */
+#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART */
+#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 as JTAG */
+#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 as TACH */
 
 /* I2C ports */
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT0_0
-#define I2C_PORT_TCPC1		NPCX_I2C_PORT0_1
-#define I2C_PORT_USB_CHARGER_1	NPCX_I2C_PORT0_1
-#define I2C_PORT_USB_CHARGER_0	NPCX_I2C_PORT1
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT1
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT1
-#define I2C_PORT_PMIC		NPCX_I2C_PORT2
-#define I2C_PORT_MP2949		NPCX_I2C_PORT2
-#define I2C_PORT_GYRO		NPCX_I2C_PORT3
-#define I2C_PORT_BARO		NPCX_I2C_PORT3
-#define I2C_PORT_ACCEL		I2C_PORT_GYRO
-#define I2C_PORT_THERMAL	I2C_PORT_PMIC
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0
+#define I2C_PORT_TCPC1 NPCX_I2C_PORT0_1
+#define I2C_PORT_USB_CHARGER_1 NPCX_I2C_PORT0_1
+#define I2C_PORT_USB_CHARGER_0 NPCX_I2C_PORT1
+#define I2C_PORT_CHARGER NPCX_I2C_PORT1
+#define I2C_PORT_BATTERY NPCX_I2C_PORT1
+#define I2C_PORT_PMIC NPCX_I2C_PORT2
+#define I2C_PORT_MP2949 NPCX_I2C_PORT2
+#define I2C_PORT_GYRO NPCX_I2C_PORT3
+#define I2C_PORT_BARO NPCX_I2C_PORT3
+#define I2C_PORT_ACCEL I2C_PORT_GYRO
+#define I2C_PORT_THERMAL I2C_PORT_PMIC
 
 /* I2C addresses */
-#define I2C_ADDR_BD99992_FLAGS	0x30
-#define I2C_ADDR_MP2949_FLAGS	0x20
+#define I2C_ADDR_BD99992_FLAGS 0x30
+#define I2C_ADDR_MP2949_FLAGS 0x20
 
 #ifndef __ASSEMBLER__
 
@@ -193,9 +193,9 @@
 
 /* Nautilus doesn't have systherm0 and systherm3 */
 enum temp_sensor_id {
-	TEMP_SENSOR_BATTERY,	/* BD99956GW TSENSE */
-	TEMP_SENSOR_CHARGER,	/* BD99992GW SYSTHERM1 */
-	TEMP_SENSOR_DRAM,	/* BD99992GW SYSTHERM2 */
+	TEMP_SENSOR_BATTERY, /* BD99956GW TSENSE */
+	TEMP_SENSOR_CHARGER, /* BD99992GW SYSTHERM1 */
+	TEMP_SENSOR_DRAM, /* BD99992GW SYSTHERM2 */
 	TEMP_SENSOR_COUNT
 };
 
@@ -213,29 +213,23 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum adc_channel {
-	ADC_BASE_DET,
-	ADC_VBUS,
-	ADC_AMON_BMON,
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_BASE_DET, ADC_VBUS, ADC_AMON_BMON, ADC_CH_COUNT };
 
 /* TODO(crosbug.com/p/61098): Verify the numbers below. */
 /*
  * delay to turn on the power supply max is ~16ms.
  * delay to turn off the power supply max is about ~180ms.
  */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	250000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* delay to turn on/off vconn */
-#define PD_VCONN_SWAP_DELAY		5000   /* us */
 
 /* Define typical operating power and max power */
-#define PD_OPERATING_POWER_MW		15000
-#define PD_MAX_POWER_MW			45000
-#define PD_MAX_CURRENT_MA		3000
-#define PD_MAX_VOLTAGE_MV		20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 45000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Board specific handlers */
 int board_get_version(void);
diff --git a/board/nautilus/build.mk b/board/nautilus/build.mk
index f4bf21113d..8f3a138f56 100644
--- a/board/nautilus/build.mk
+++ b/board/nautilus/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/nautilus/ec.tasklist b/board/nautilus/ec.tasklist
index 8257734572..bcc5fc37e5 100644
--- a/board/nautilus/ec.tasklist
+++ b/board/nautilus/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nautilus/gpio.inc b/board/nautilus/gpio.inc
index 9cfc1e0bfd..13305d50fb 100644
--- a/board/nautilus/gpio.inc
+++ b/board/nautilus/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,10 +14,10 @@ GPIO_INT(USB_C1_PD_INT_ODL,	PIN(C, 5), GPIO_INT_FALLING,			tcpc_alert_event)
 GPIO_INT(PCH_SLP_S0_L,		PIN(7, 5), GPIO_INT_BOTH,			power_signal_interrupt)
 #endif
 /* Use VW signals instead of GPIOs */
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(PCH_SLP_S3_L,		PIN(7, 3), GPIO_INT_BOTH,			power_signal_interrupt)
 #endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 GPIO_INT(PCH_SLP_S4_L,		PIN(8, 6), GPIO_INT_BOTH,			power_signal_interrupt)
 #endif
 GPIO_INT(PCH_SLP_SUS_L,		PIN(6, 2), GPIO_INT_BOTH,			power_signal_interrupt)
diff --git a/board/nautilus/led.c b/board/nautilus/led.c
index 86567701f0..96b9334a5c 100644
--- a/board/nautilus/led.c
+++ b/board/nautilus/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -23,9 +23,8 @@
 #define LED_TOTAL_TICKS 16
 #define LED_ON_TICKS 8
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-	EC_LED_ID_BATTERY_LED};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED,
+					     EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -67,12 +66,11 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 	return EC_SUCCESS;
 }
 
-
 static void nautilus_led_set_power_battery(void)
 {
 	static unsigned int power_ticks;
 	enum led_color cur_led_color = LED_RED;
-	enum charge_state chg_state = charge_get_state();
+	enum led_pwr_state chg_state = led_pwr_get_state();
 	int charge_percent = charge_get_percent();
 
 	if (chipset_in_state(CHIPSET_STATE_ON)) {
@@ -82,34 +80,37 @@ static void nautilus_led_set_power_battery(void)
 
 	/* Flash red on critical battery, which usually inhibits AP power-on. */
 	if (battery_is_present() != BP_YES ||
-		charge_percent < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
-			set_color(((power_ticks++ % LED_TOTAL_TICKS) < LED_ON_TICKS) ?
-						  LED_RED : LED_OFF);
+	    charge_percent < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
+		set_color(((power_ticks++ % LED_TOTAL_TICKS) < LED_ON_TICKS) ?
+				  LED_RED :
+				  LED_OFF);
 		return;
 	}
 
 	/* CHIPSET_STATE_OFF */
 	switch (chg_state) {
-	case PWR_STATE_DISCHARGE:
+	case LED_PWRS_DISCHARGE:
 		if ((charge_get_flags() & CHARGE_FLAG_EXTERNAL_POWER) &&
-			charge_percent >= BATTERY_LEVEL_NEAR_FULL)
+		    charge_percent >= CONFIG_BATT_HOST_FULL_FACTOR)
 			cur_led_color = LED_GREEN;
 		else
 			cur_led_color = LED_OFF;
 		break;
-	case PWR_STATE_CHARGE:
+	case LED_PWRS_CHARGE:
 		cur_led_color = LED_RED;
 		break;
-	case PWR_STATE_ERROR:
-		cur_led_color = ((power_ticks++ % LED_TOTAL_TICKS)
-					  < LED_ON_TICKS) ? LED_RED : LED_GREEN;
+	case LED_PWRS_ERROR:
+		cur_led_color =
+			((power_ticks++ % LED_TOTAL_TICKS) < LED_ON_TICKS) ?
+				LED_RED :
+				LED_GREEN;
 		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-	case PWR_STATE_IDLE:
-		if(charge_get_flags() & CHARGE_FLAG_EXTERNAL_POWER)
-			cur_led_color = LED_GREEN;
-		else
-			cur_led_color = LED_OFF;
+	case LED_PWRS_CHARGE_NEAR_FULL:
+	case LED_PWRS_IDLE:
+		cur_led_color = LED_OFF;
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		cur_led_color = LED_GREEN;
 		break;
 	default:
 		cur_led_color = LED_RED;
@@ -118,7 +119,7 @@ static void nautilus_led_set_power_battery(void)
 
 	set_color(cur_led_color);
 
-	if (chg_state != PWR_STATE_ERROR)
+	if (chg_state != LED_PWRS_ERROR)
 		power_ticks = 0;
 }
 
@@ -128,8 +129,8 @@ static void nautilus_led_set_power_battery(void)
 static void led_tick(void)
 {
 	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED) &&
-		led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
-			nautilus_led_set_power_battery();
+	    led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
+		nautilus_led_set_power_battery();
 	}
 }
 
diff --git a/board/nautilus/usb_pd_policy.c b/board/nautilus/usb_pd_policy.c
index be4716b860..050eae9a64 100644
--- a/board/nautilus/usb_pd_policy.c
+++ b/board/nautilus/usb_pd_policy.c
@@ -1,14 +1,14 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "atomic.h"
-#include "extpower.h"
 #include "charge_manager.h"
 #include "common.h"
 #include "console.h"
 #include "driver/tcpm/ps8xxx.h"
+#include "extpower.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "host_command.h"
@@ -16,17 +16,17 @@
 #include "system.h"
 #include "task.h"
 #include "timer.h"
-#include "util.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
+#include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT];
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5,
-							TYPEC_RP_1A5};
+static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5,
+							 TYPEC_RP_1A5 };
 
 int board_vbus_source_enabled(int port)
 {
@@ -47,8 +47,8 @@ static void board_vbus_update_source_current(int port)
 		 * is controlled by GPIO_USB_C0/1_5V_EN. Both of these signals
 		 * can remain outputs.
 		 */
-		gpio_set_level(gpio_3a_en, vbus_rp[port] == TYPEC_RP_3A0 ?
-				1 : 0);
+		gpio_set_level(gpio_3a_en,
+			       vbus_rp[port] == TYPEC_RP_3A0 ? 1 : 0);
 		gpio_set_level(gpio_5v_en, vbus_en[port]);
 	} else {
 		/*
@@ -60,8 +60,8 @@ static void board_vbus_update_source_current(int port)
 		 * 1505 mA.
 		 */
 		int flags = (vbus_rp[port] == TYPEC_RP_1A5 && vbus_en[port]) ?
-			(GPIO_INPUT | GPIO_PULL_UP) :
-			(GPIO_OUTPUT | GPIO_PULL_UP);
+				    (GPIO_INPUT | GPIO_PULL_UP) :
+				    (GPIO_OUTPUT | GPIO_PULL_UP);
 		gpio_set_level(gpio_5v_en, vbus_en[port]);
 		gpio_set_flags(gpio_5v_en, flags);
 	}
@@ -78,8 +78,7 @@ __override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
 int pd_set_power_supply_ready(int port)
 {
 	/* Disable charging */
-	gpio_set_level(port ? GPIO_USB_C1_CHARGE_L :
-			      GPIO_USB_C0_CHARGE_L, 1);
+	gpio_set_level(port ? GPIO_USB_C1_CHARGE_L : GPIO_USB_C0_CHARGE_L, 1);
 
 	/* Ensure we advertise the proper available current quota */
 	charge_manager_source_port(port, 1);
@@ -124,22 +123,19 @@ int pd_snk_is_vbus_provided(int port)
 				      GPIO_USB_C0_VBUS_WAKE_L);
 }
 
-
 int pd_check_vconn_swap(int port)
 {
 	/* in G3, do not allow vconn swap since pp5000_A rail is off */
 	return gpio_get_level(GPIO_PMIC_SLP_SUS_L);
 }
 
-__override void pd_execute_data_swap(int port,
-				     enum pd_data_role data_role)
+__override void pd_execute_data_swap(int port, enum pd_data_role data_role)
 {
 	/* Only port 0 supports device mode. */
 	if (port != 0)
 		return;
 
-	gpio_set_level(GPIO_USB2_OTG_ID,
-		      (data_role == PD_ROLE_UFP) ? 1 : 0);
+	gpio_set_level(GPIO_USB2_OTG_ID, (data_role == PD_ROLE_UFP) ? 1 : 0);
 	gpio_set_level(GPIO_USB2_OTG_VBUSSENSE,
-		      (data_role == PD_ROLE_UFP) ? 1 : 0);
+		       (data_role == PD_ROLE_UFP) ? 1 : 0);
 }
diff --git a/board/nautilus/vif_override.xml b/board/nautilus/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/nautilus/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/nightfury/battery.c b/board/nightfury/battery.c
index a3b251229b..9e9b9baa74 100644
--- a/board/nightfury/battery.c
+++ b/board/nightfury/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -111,10 +111,10 @@ enum battery_present variant_battery_present(void)
 
 int charger_profile_override(struct charge_state_data *curr)
 {
-	if(chipset_in_state(CHIPSET_STATE_ANY_OFF))
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
 		return 0;
 
-	if(curr->requested_current > CHARGING_CURRENT_45C)
+	if (curr->requested_current > CHARGING_CURRENT_45C)
 		curr->requested_current = CHARGING_CURRENT_45C;
 
 	return 0;
@@ -124,13 +124,13 @@ int charger_profile_override(struct charge_state_data *curr)
 #define PARAM_FASTCHARGE (CS_PARAM_CUSTOM_PROFILE_MIN + 0)
 
 enum ec_status charger_profile_override_get_param(uint32_t param,
-                                                  uint32_t *value)
+						  uint32_t *value)
 {
-        return EC_RES_INVALID_PARAM;
+	return EC_RES_INVALID_PARAM;
 }
 
 enum ec_status charger_profile_override_set_param(uint32_t param,
-                                                  uint32_t value)
+						  uint32_t value)
 {
-        return EC_RES_INVALID_PARAM;
+	return EC_RES_INVALID_PARAM;
 }
diff --git a/board/nightfury/board.c b/board/nightfury/board.c
index 0dcee3a1cf..bc1c26de12 100644
--- a/board/nightfury/board.c
+++ b/board/nightfury/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,6 @@
 /* Nightfury board-specific configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "button.h"
 #include "common.h"
 #include "cros_board_info.h"
@@ -14,8 +13,8 @@
 #include "driver/accelgyro_bmi_common.h"
 #include "driver/als_opt3001.h"
 #include "driver/als_tcs3400.h"
-#include "driver/ppc/sn5s330.h"
 #include "driver/bc12/pi3usb9201.h"
+#include "driver/ppc/sn5s330.h"
 #include "driver/sync.h"
 #include "driver/tcpm/ps8xxx.h"
 #include "driver/tcpm/tcpci.h"
@@ -26,6 +25,7 @@
 #include "gpio.h"
 #include "hooks.h"
 #include "host_command.h"
+#include "keyboard_scan.h"
 #include "lid_switch.h"
 #include "power.h"
 #include "power_button.h"
@@ -36,16 +36,16 @@
 #include "system.h"
 #include "task.h"
 #include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
 #include "thermal.h"
-#include "thermistor.h"
 #include "uart.h"
 #include "usb_charge.h"
 #include "usb_pd.h"
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void ppc_interrupt(enum gpio_signal signal)
 {
@@ -85,11 +85,11 @@ static void bc12_interrupt(enum gpio_signal signal)
 {
 	switch (signal) {
 	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
 		break;
 
 	case GPIO_USB_C1_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12, 0);
+		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
 		break;
 
 	default:
@@ -97,27 +97,21 @@ static void bc12_interrupt(enum gpio_signal signal)
 	}
 }
 
-#include "gpio_list.h" /* Must come after other header files. */
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
 
 /******************************************************************************/
 /* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
+const struct spi_device_t spi_devices[] = {};
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
 /******************************************************************************/
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = 0,
-		.freq = 10000
-	},
-	[PWM_CH_FAN] = {
-		.channel = 5,
-		.flags = PWM_CONFIG_OPEN_DRAIN,
-		.freq = 25000
-	},
+	[PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 },
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
@@ -128,7 +122,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = I2C_PORT_TCPC0,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
 		},
 		.drv = &ps8xxx_tcpm_drv,
 	},
@@ -136,20 +130,24 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = I2C_PORT_TCPC1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
 		},
 		.drv = &ps8xxx_tcpm_drv,
 	},
 };
 
-struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_TCPC_0] = {
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 	},
 	[USB_PD_PORT_TCPC_1] = {
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 	}
 };
 
@@ -186,22 +184,18 @@ static struct opt3001_drv_data_t g_opt3001_data = {
 static struct stprivate_data g_lis2ds_data;
 
 /* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					      { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
 
 /*
  * TODO(b/124337208): P0 boards don't have this sensor mounted so the rotation
  * matrix can't be tested properly. This needs to be revisited after EVT to make
  * sure the rotation matrix for the lid sensor is correct.
  */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+					     { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
@@ -304,6 +298,19 @@ const struct motion_sensor_t *motion_als_sensors[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
 
+__override struct keyboard_scan_config keyscan_config = {
+	.output_settle_us = 80,
+	.debounce_down_us = 30 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x1c, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
+		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
+	},
+};
+
 /******************************************************************************/
 /* Physical fans. These are logically separate from pwm_channels. */
 
@@ -328,63 +335,68 @@ const struct fan_t fans[FAN_CH_COUNT] = {
 /******************************************************************************/
 /* MFT channels. These are logically separate from pwm_channels. */
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN },
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 /**********************************************************************/
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		"TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_2] = {
-		"TEMP_IA", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_3] = {
-		"TEMP_GT", NPCX_ADC_CH3, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_1] = { "TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_2] = { "TEMP_IA", NPCX_ADC_CH1, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_3] = { "TEMP_GT", NPCX_ADC_CH3, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "IA",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "GT",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_3},
+	[TEMP_SENSOR_1] = { .name = "Charger",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "IA",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "GT",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
 /* Nightfury Temperature sensors */
 /*
  * TODO(b/138578073): These setting need to be reviewed and set appropriately
- * for Nightfury. They matter when the EC is controlling the fan as opposed to DPTF
- * control.
+ * for Nightfury. They matter when the EC is controlling the fan as opposed to
+ * DPTF control.
  */
-const static struct ec_thermal_config thermal_a = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(90),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(25),
-	.temp_fan_max = C_TO_K(50),
-};
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_A                \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(90), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+		.temp_fan_off = C_TO_K(25), \
+		.temp_fan_max = C_TO_K(50), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A;
 
 struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1] = thermal_a,
-	[TEMP_SENSOR_2] = thermal_a,
-	[TEMP_SENSOR_3] = thermal_a,
+	[TEMP_SENSOR_1] = THERMAL_A,
+	[TEMP_SENSOR_2] = THERMAL_A,
+	[TEMP_SENSOR_3] = THERMAL_A,
 };
 BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
 
@@ -424,5 +436,5 @@ bool board_is_convertible(void)
 {
 	const uint8_t sku = get_board_sku();
 
-	return (sku == 255) || (sku == 1);
+	return (sku == 255) || (sku == 1) || (sku == 2);
 }
diff --git a/board/nightfury/board.h b/board/nightfury/board.h
index 7f06cd2ae2..9831741d5a 100644
--- a/board/nightfury/board.h
+++ b/board/nightfury/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,11 +16,11 @@
 
 #define CONFIG_POWER_BUTTON
 #define CONFIG_KEYBOARD_PROTOCOL_8042
+
 #define CONFIG_LED_COMMON
 #define CONFIG_LOW_POWER_IDLE
-#define CONFIG_LED_POWER_LED
 
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 
 #undef CONFIG_UART_TX_BUF_SIZE
 #define CONFIG_UART_TX_BUF_SIZE 4096
@@ -30,7 +30,6 @@
 
 /* Sensors */
 /* BMI160 Base accel/gyro */
-#define CONFIG_ACCEL_INTERRUPTS
 #define CONFIG_ACCELGYRO_BMI160
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
@@ -46,7 +45,7 @@
 /* BH1730 and TCS3400 ALS */
 #define CONFIG_ALS
 #define ALS_COUNT 1
-#define I2C_PORT_ALS      I2C_PORT_SENSOR
+#define I2C_PORT_ALS I2C_PORT_SENSOR
 #define CONFIG_ALS_OPT3001
 #define OPT3001_I2C_ADDR_FLAGS OPT3001_I2C_ADDR1_FLAGS
 
@@ -67,18 +66,18 @@
  * Nightfury will not use both BH1730_LUXTH3_1K condition
  * and BH1730_LUXTH4_1K condition.
  */
-#define BH1730_LUXTH1_1K                270
-#define BH1730_LUXTH1_D0_1K             19200
-#define BH1730_LUXTH1_D1_1K             30528
-#define BH1730_LUXTH2_1K                655360000
-#define BH1730_LUXTH2_D0_1K             11008
-#define BH1730_LUXTH2_D1_1K             10752
-#define BH1730_LUXTH3_1K                1030
-#define BH1730_LUXTH3_D0_1K             11008
-#define BH1730_LUXTH3_D1_1K             10752
-#define BH1730_LUXTH4_1K                3670
-#define BH1730_LUXTH4_D0_1K             11008
-#define BH1730_LUXTH4_D1_1K             10752
+#define BH1730_LUXTH1_1K 270
+#define BH1730_LUXTH1_D0_1K 19200
+#define BH1730_LUXTH1_D1_1K 30528
+#define BH1730_LUXTH2_1K 655360000
+#define BH1730_LUXTH2_D0_1K 11008
+#define BH1730_LUXTH2_D1_1K 10752
+#define BH1730_LUXTH3_1K 1030
+#define BH1730_LUXTH3_D0_1K 11008
+#define BH1730_LUXTH3_D1_1K 10752
+#define BH1730_LUXTH4_1K 3670
+#define BH1730_LUXTH4_D0_1K 11008
+#define BH1730_LUXTH4_D1_1K 10752
 
 /* USB Type C and USB PD defines */
 #define CONFIG_USB_MUX_RUNTIME_CONFIG
@@ -117,7 +116,7 @@
 #define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
 
 /* Thermal features */
-#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_A_RAILS
+#define CONFIG_TEMP_SENSOR_POWER
 #define CONFIG_THERMISTOR
 #define CONFIG_THROTTLE_AP
 #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
@@ -133,15 +132,16 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_AC_PRESENT		GPIO_ACOK_OD
-#define GPIO_RSMRST_L_PGOOD	GPIO_PG_EC_RSMRST_L
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L
+#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
 
 #ifndef __ASSEMBLER__
 
@@ -152,9 +152,9 @@
 extern enum gpio_signal gpio_en_pp5000_a;
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_1,	/* ADC0 */
-	ADC_TEMP_SENSOR_2,	/* ADC1 */
-	ADC_TEMP_SENSOR_3,	/* ADC3 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
+	ADC_TEMP_SENSOR_3, /* ADC3 */
 	ADC_CH_COUNT
 };
 
@@ -166,11 +166,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_FAN,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_FAN, PWM_CH_COUNT };
 
 enum fan_channel {
 	FAN_CH_0 = 0,
diff --git a/board/nightfury/build.mk b/board/nightfury/build.mk
index e91262fd43..169668e64c 100644
--- a/board/nightfury/build.mk
+++ b/board/nightfury/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/nightfury/ec.tasklist b/board/nightfury/ec.tasklist
index 101713dc6e..507845b304 100644
--- a/board/nightfury/ec.tasklist
+++ b/board/nightfury/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nightfury/gpio.inc b/board/nightfury/gpio.inc
index 68d847fe92..710bf07c17 100644
--- a/board/nightfury/gpio.inc
+++ b/board/nightfury/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,10 +16,10 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(PG_EC_RSMRST_L,       PIN(E, 2), GPIO_INT_BOTH, intel_x86_rsmrst_signal_interrupt)
diff --git a/board/nightfury/led.c b/board/nightfury/led.c
index b20dbbd6f0..9d2c367ab5 100644
--- a/board/nightfury/led.c
+++ b/board/nightfury/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -12,54 +12,57 @@
 #include "led_common.h"
 #include "led_onoff_states.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
-const int led_charge_lvl_1 = 1;
+__override const int led_charge_lvl_1 = 1;
 
-const int led_charge_lvl_2 = 100;
+__override const int led_charge_lvl_2 = 100;
 
 /* Nightfury : There are 3 leds for AC, Battery and Power */
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED, 0.5 * LED_ONE_SEC},
-                                        {LED_OFF, 0.5 * LED_ONE_SEC} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED, 0.5 * LED_ONE_SEC},
-					{LED_OFF, 0.5 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC},
-					{LED_OFF, 1 * LED_ONE_SEC} },
-};
-
-const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     0.5 * LED_ONE_SEC },
+					   { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_GREEN,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED,
+					    0.5 * LED_ONE_SEC },
+					  { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					 { LED_OFF, 1 * LED_ONE_SEC } },
+	};
+
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_BLUE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-void led_set_color_power(enum ec_led_colors color)
+__override void led_set_color_power(enum ec_led_colors color)
 {
 	/* Don't set led if led_auto_control is disabled. */
 	if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) ||
-		!led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
+	    !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
 		return;
 	}
 
-	if (color == EC_LED_COLOR_BLUE)
-	{
+	if (color == EC_LED_COLOR_BLUE) {
 		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
 		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
 		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_ON_LVL);
@@ -69,19 +72,18 @@ void led_set_color_power(enum ec_led_colors color)
 	}
 }
 
-void led_set_color_battery(enum ec_led_colors color)
+__override void led_set_color_battery(enum ec_led_colors color)
 {
 	/* Don't set led if led_auto_control is disabled. */
 	if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) ||
-		!led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
+	    !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
 		return;
 	}
 
 	/* Battery leds must be turn off when blue led is on
 	 * because Nightfury has 3-in-1 led.
 	 */
-	if(!gpio_get_level(GPIO_PWR_LED_BLUE_L))
-	{
+	if (!gpio_get_level(GPIO_PWR_LED_BLUE_L)) {
 		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
 		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
 		return;
@@ -117,10 +119,13 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 {
 	if (led_id == EC_LED_ID_BATTERY_LED) {
 		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, !brightness[EC_LED_COLOR_GREEN]);
-		gpio_set_level(GPIO_BAT_LED_RED_L, !brightness[EC_LED_COLOR_RED]);
+		gpio_set_level(GPIO_BAT_LED_GREEN_L,
+			       !brightness[EC_LED_COLOR_GREEN]);
+		gpio_set_level(GPIO_BAT_LED_RED_L,
+			       !brightness[EC_LED_COLOR_RED]);
 	} else if (led_id == EC_LED_ID_POWER_LED) {
-		gpio_set_level(GPIO_PWR_LED_BLUE_L, !brightness[EC_LED_COLOR_BLUE]);
+		gpio_set_level(GPIO_PWR_LED_BLUE_L,
+			       !brightness[EC_LED_COLOR_BLUE]);
 		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
 		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
 	}
diff --git a/board/nightfury/vif_override.xml b/board/nightfury/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/nightfury/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/nipperkin/battery.c b/board/nipperkin/battery.c
new file mode 100644
index 0000000000..b8bedb535e
--- /dev/null
+++ b/board/nipperkin/battery.c
@@ -0,0 +1,92 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+
+/*
+ * Battery info for all Guybrush battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	/* SMP 996QA193H Battery Information */
+	[BATTERY_SIMPLO_HIGHPOWER] = {
+		.fuel_gauge = {
+			.manuf_name = "333-1D-11-A",
+			.ship_mode = {
+				.reg_addr = 0x0,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 13200,		/* mV */
+			.voltage_normal = 11550,	/* mV */
+			.voltage_min = 9000,		/* mV */
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -20,
+			.discharging_max_c = 60,
+		},
+	},
+/* Cosmx CA407792G Battery Information */
+	[BATTERY_COSMX] = {
+		.fuel_gauge = {
+			.manuf_name = "333-AC-11-A",
+			.ship_mode = {
+				.reg_addr = 0x0,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 13200,		/* mV */
+			.voltage_normal = 11550,	/* mV */
+			.voltage_min = 9000,		/* mV */
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SIMPLO_HIGHPOWER;
diff --git a/board/nipperkin/board.c b/board/nipperkin/board.c
new file mode 100644
index 0000000000..0111f9c04e
--- /dev/null
+++ b/board/nipperkin/board.c
@@ -0,0 +1,531 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Nipperkin board-specific configuration */
+
+#include "adc.h"
+#include "base_fw_config.h"
+#include "battery.h"
+#include "board_fw_config.h"
+#include "button.h"
+#include "charger.h"
+#include "chipset.h"
+#include "common.h"
+#include "cros_board_info.h"
+#include "driver/charger/isl9241.h"
+#include "driver/retimer/pi3hdx1204.h"
+#include "driver/retimer/ps8811.h"
+#include "driver/retimer/ps8818_public.h"
+#include "driver/temp_sensor/pct2075.h"
+#include "driver/temp_sensor/sb_tsi.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "switch.h"
+#include "tablet_mode.h"
+#include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
+#include "thermal.h"
+#include "timer.h"
+#include "usb_mux.h"
+
+static void hdmi_hpd_interrupt(enum gpio_signal signal);
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/*
+ * We have total 30 pins for keyboard connecter {-1, -1} mean
+ * the N/A pin that don't consider it and reserve index 0 area
+ * that we don't have pin 0.
+ */
+const int keyboard_factory_scan_pins[][2] = {
+	{ -1, -1 }, { 0, 5 },	{ 1, 1 }, { 1, 0 },   { 0, 6 },	  { 0, 7 },
+	{ -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 },   { -1, -1 }, { 1, 6 },
+	{ 1, 7 },   { 3, 1 },	{ 2, 0 }, { 1, 5 },   { 2, 6 },	  { 2, 7 },
+	{ 2, 1 },   { 2, 4 },	{ 2, 5 }, { 1, 2 },   { 2, 3 },	  { 2, 2 },
+	{ 3, 0 },   { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 },	  { -1, -1 },
+	{ -1, -1 },
+};
+const int keyboard_factory_scan_pins_used =
+	ARRAY_SIZE(keyboard_factory_scan_pins);
+
+__override enum ec_error_list
+board_a1_ps8811_retimer_init(const struct usb_mux *me)
+{
+	return EC_SUCCESS;
+}
+
+__override int board_c1_ps8818_mux_set(const struct usb_mux *me,
+				       mux_state_t mux_state)
+{
+	int rv = EC_SUCCESS;
+
+	/* USB specific config */
+	if (mux_state & USB_PD_MUX_USB_ENABLED) {
+		/* Boost the USB gain */
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_APTX1EQ_10G_LEVEL,
+					      PS8818_EQ_LEVEL_UP_MASK,
+					      PS8818_EQ_LEVEL_UP_19DB);
+		if (rv)
+			return rv;
+
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_APTX2EQ_10G_LEVEL,
+					      PS8818_EQ_LEVEL_UP_MASK,
+					      PS8818_EQ_LEVEL_UP_19DB);
+		if (rv)
+			return rv;
+
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_APTX1EQ_5G_LEVEL,
+					      PS8818_EQ_LEVEL_UP_MASK,
+					      PS8818_EQ_LEVEL_UP_19DB);
+		if (rv)
+			return rv;
+
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_APTX2EQ_5G_LEVEL,
+					      PS8818_EQ_LEVEL_UP_MASK,
+					      PS8818_EQ_LEVEL_UP_19DB);
+		if (rv)
+			return rv;
+
+		/* Set the RX input termination */
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_RX_PHY,
+					      PS8818_RX_INPUT_TERM_MASK,
+					      PS8818_RX_INPUT_TERM_112_OHM);
+		if (rv)
+			return rv;
+	}
+
+	/* DP specific config */
+	if (mux_state & USB_PD_MUX_DP_ENABLED) {
+		/* Boost the DP gain */
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_DPEQ_LEVEL,
+					      PS8818_DPEQ_LEVEL_UP_MASK,
+					      PS8818_DPEQ_LEVEL_UP_19DB);
+		if (rv)
+			return rv;
+
+		/* Enable HPD on the DB */
+		ioex_set_level(IOEX_USB_C1_IN_HPD, 1);
+	} else {
+		/* Disable HPD on the DB */
+		ioex_set_level(IOEX_USB_C1_IN_HPD, 0);
+	}
+
+	return rv;
+}
+
+static void board_init(void)
+{
+	if (get_board_version() > 1)
+		gpio_enable_interrupt(GPIO_HPD_EC_IN);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+static void board_chipset_startup(void)
+{
+	if (get_board_version() > 1)
+		pct2075_init();
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
+
+int board_get_soc_temp_k(int idx, int *temp_k)
+{
+	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	return pct2075_get_val_k(idx, temp_k);
+}
+
+int board_get_soc_temp_mk(int *temp_mk)
+{
+	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	return pct2075_get_val_mk(PCT2075_SOC, temp_mk);
+}
+
+int board_get_ambient_temp_mk(int *temp_mk)
+{
+	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	return pct2075_get_val_mk(PCT2075_AMB, temp_mk);
+}
+
+/* ADC Channels */
+const struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_MEMORY] = {
+		.name = "MEMORY",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_CHARGER] = {
+		.name = "CHARGER",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_5V_REGULATOR] = {
+		.name = "5V_REGULATOR",
+		.input_ch = NPCX_ADC_CH2,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_CORE_IMON1] = {
+		.name = "CORE_I",
+		.input_ch = NPCX_ADC_CH3,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_SOC_IMON2] = {
+		.name = "SOC_I",
+		.input_ch = NPCX_ADC_CH4,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* Temp Sensors */
+static int board_get_temp(int, int *);
+
+const struct pct2075_sensor_t pct2075_sensors[] = {
+	{ I2C_PORT_SENSOR, PCT2075_I2C_ADDR_FLAGS0 },
+	{ I2C_PORT_SENSOR, PCT2075_I2C_ADDR_FLAGS7 },
+};
+BUILD_ASSERT(ARRAY_SIZE(pct2075_sensors) == PCT2075_COUNT);
+
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_SOC] = {
+		.name = "SOC",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = board_get_soc_temp_k,
+		.idx = PCT2075_SOC,
+	},
+	[TEMP_SENSOR_CHARGER] = {
+		.name = "Charger",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_CHARGER,
+	},
+	[TEMP_SENSOR_MEMORY] = {
+		.name = "Memory",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = board_get_temp,
+		.idx = ADC_TEMP_SENSOR_MEMORY,
+	},
+	[TEMP_SENSOR_5V_REGULATOR] = {
+		.name = "5V_REGULATOR",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = board_get_temp,
+		.idx = ADC_TEMP_SENSOR_5V_REGULATOR,
+	},
+	[TEMP_SENSOR_CPU] = {
+		.name = "CPU",
+		.type = TEMP_SENSOR_TYPE_CPU,
+		.read = sb_tsi_get_val,
+		.idx = 0,
+	},
+	[TEMP_SENSOR_AMBIENT] = {
+		.name = "Ambient",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = pct2075_get_val_k,
+		.idx = PCT2075_AMB,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT] = {
+	[TEMP_SENSOR_SOC] = {
+		.temp_host = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
+			[EC_TEMP_THRESH_HALT] = C_TO_K(83),
+		},
+		.temp_host_release = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
+		},
+	},
+	[TEMP_SENSOR_CHARGER] = {
+		.temp_host = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(77),
+			[EC_TEMP_THRESH_HALT] = C_TO_K(81),
+		},
+		.temp_host_release = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(72),
+		},
+	},
+	[TEMP_SENSOR_MEMORY] = {
+		.temp_host = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
+			[EC_TEMP_THRESH_HALT] = C_TO_K(83),
+		},
+		.temp_host_release = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
+		},
+	},
+	[TEMP_SENSOR_5V_REGULATOR] = {
+		.temp_host = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(55),
+			[EC_TEMP_THRESH_HALT] = C_TO_K(58),
+		},
+		.temp_host_release = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(47),
+		},
+	},
+	[TEMP_SENSOR_CPU] = {
+		.temp_host = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(100),
+			[EC_TEMP_THRESH_HALT] = C_TO_K(105),
+		},
+		.temp_host_release = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
+		},
+	},
+	/*
+	 * Note: Leave ambient entries at 0, both as it does not represent a
+	 * hotspot and as not all boards have this sensor
+	 */
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
+
+static int board_get_temp(int idx, int *temp_k)
+{
+	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
+		return EC_ERROR_NOT_POWERED;
+	return get_temp_3v3_30k9_47k_4050b(idx, temp_k);
+}
+
+static int check_hdmi_hpd_status(void)
+{
+	if (get_board_version() > 1)
+		return gpio_get_level(GPIO_HPD_EC_IN);
+	else
+		return true;
+}
+
+/* Called on AP resume to S0 */
+static void board_chipset_resume(void)
+{
+	ioex_set_level(IOEX_USB_A1_PD_R_L, 1);
+	ioex_set_level(IOEX_EN_PWR_HDMI, 1);
+	ioex_set_level(IOEX_HDMI_DATA_EN, 1);
+	msleep(PI3HDX1204_POWER_ON_DELAY_MS);
+	pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS,
+			  check_hdmi_hpd_status());
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
+
+/* Called on AP suspend */
+static void board_chipset_suspend(void)
+{
+	pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS, 0);
+	ioex_set_level(IOEX_HDMI_DATA_EN, 0);
+	ioex_set_level(IOEX_EN_PWR_HDMI, 0);
+	ioex_set_level(IOEX_USB_A1_PD_R_L, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
+
+/*
+ * With privacy screen, with keyboard backlight
+ */
+static const struct ec_response_keybd_config
+	keybd_w_privacy_w_kblight = {
+	.num_top_row_keys = 13,
+	.action_keys = {
+		TK_BACK,			/* T1 */
+		TK_REFRESH,			/* T2 */
+		TK_FULLSCREEN,			/* T3 */
+		TK_OVERVIEW,			/* T4 */
+		TK_SNAPSHOT,			/* T5 */
+		TK_BRIGHTNESS_DOWN,		/* T6 */
+		TK_BRIGHTNESS_UP,		/* T7 */
+		TK_PRIVACY_SCRN_TOGGLE,		/* T8 */
+		TK_KBD_BKLIGHT_TOGGLE,		/* T9 */
+		TK_MICMUTE,			/* T10 */
+		TK_VOL_MUTE,			/* T11 */
+		TK_VOL_DOWN,			/* T12 */
+		TK_VOL_UP,			/* T13 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+/*
+ * Without privacy screen, with keyboard backlight
+ */
+static const struct ec_response_keybd_config
+	keybd_wo_privacy_w_kblight = {
+	.num_top_row_keys = 13,
+	.action_keys = {
+		TK_BACK,			/* T1 */
+		TK_REFRESH,			/* T2 */
+		TK_FULLSCREEN,			/* T3 */
+		TK_OVERVIEW,			/* T4 */
+		TK_SNAPSHOT,			/* T5 */
+		TK_BRIGHTNESS_DOWN,		/* T6 */
+		TK_BRIGHTNESS_UP,		/* T7 */
+		TK_KBD_BKLIGHT_TOGGLE,		/* T8 */
+		TK_PLAY_PAUSE,			/* T9 */
+		TK_MICMUTE,			/* T10 */
+		TK_VOL_MUTE,			/* T11 */
+		TK_VOL_DOWN,			/* T12 */
+		TK_VOL_UP,			/* T13 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+/*
+ * With privacy screen, without keyboard backlight
+ */
+static const struct ec_response_keybd_config
+	keybd_w_privacy_wo_kblight = {
+	.num_top_row_keys = 13,
+	.action_keys = {
+		TK_BACK,			/* T1 */
+		TK_REFRESH,			/* T2 */
+		TK_FULLSCREEN,			/* T3 */
+		TK_OVERVIEW,			/* T4 */
+		TK_SNAPSHOT,			/* T5 */
+		TK_BRIGHTNESS_DOWN,		/* T6 */
+		TK_BRIGHTNESS_UP,		/* T7 */
+		TK_PRIVACY_SCRN_TOGGLE,		/* T8 */
+		TK_PLAY_PAUSE,			/* T9 */
+		TK_MICMUTE,			/* T10 */
+		TK_VOL_MUTE,			/* T11 */
+		TK_VOL_DOWN,			/* T12 */
+		TK_VOL_UP,			/* T13 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+/*
+ * Without privacy screen, without keyboard backlight
+ */
+static const struct ec_response_keybd_config
+	keybd_wo_privacy_wo_kblight_V0 = {
+	.num_top_row_keys = 13,
+	.action_keys = {
+		TK_BACK,			/* T1 */
+		TK_REFRESH,			/* T2 */
+		TK_FULLSCREEN,			/* T3 */
+		TK_OVERVIEW,			/* T4 */
+		TK_SNAPSHOT,			/* T5 */
+		TK_BRIGHTNESS_DOWN,		/* T6 */
+		TK_BRIGHTNESS_UP,		/* T7 */
+		TK_PREV_TRACK,			/* T8 */
+		TK_PLAY_PAUSE,			/* T9 */
+		TK_MICMUTE,			/* T10 */
+		TK_VOL_MUTE,			/* T11 */
+		TK_VOL_DOWN,			/* T12 */
+		TK_VOL_UP,			/* T13 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+static const struct ec_response_keybd_config
+	keybd_wo_privacy_wo_kblight_V1 = {
+	.num_top_row_keys = 13,
+	.action_keys = {
+		TK_BACK,			/* T1 */
+		TK_REFRESH,			/* T2 */
+		TK_FULLSCREEN,			/* T3 */
+		TK_OVERVIEW,			/* T4 */
+		TK_SNAPSHOT,			/* T5 */
+		TK_BRIGHTNESS_DOWN,		/* T6 */
+		TK_BRIGHTNESS_UP,		/* T7 */
+		TK_PLAY_PAUSE,			/* T8 */
+		TK_MICMUTE,			/* T9 */
+		TK_VOL_MUTE,			/* T10 */
+		TK_VOL_DOWN,			/* T11 */
+		TK_VOL_UP,			/* T12 */
+		TK_MENU,			/* T13 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	if (board_has_privacy_panel() && board_has_kblight())
+		return &keybd_w_privacy_w_kblight;
+	else if (!board_has_privacy_panel() && board_has_kblight())
+		return &keybd_wo_privacy_w_kblight;
+	else if (board_has_privacy_panel() && !board_has_kblight())
+		return &keybd_w_privacy_wo_kblight;
+	else {
+		if (get_board_version() <= 3)
+			return &keybd_wo_privacy_wo_kblight_V0;
+		else
+			return &keybd_wo_privacy_wo_kblight_V1;
+	}
+}
+
+const struct pi3hdx1204_tuning pi3hdx1204_tuning = {
+	.eq_ch0_ch1_offset = PI3HDX1204_EQ_DB710,
+	.eq_ch2_ch3_offset = PI3HDX1204_EQ_DB710,
+	.vod_offset = PI3HDX1204_VOD_115_ALL_CHANNELS,
+	.de_offset = PI3HDX1204_DE_DB_MINUS5,
+};
+
+static void hdmi_hpd_handler(void)
+{
+	int hpd = check_hdmi_hpd_status();
+
+	ccprints("HDMI HPD %d", hpd);
+	pi3hdx1204_enable(
+		I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS,
+		chipset_in_or_transitioning_to_state(CHIPSET_STATE_ON) && hpd);
+}
+DECLARE_DEFERRED(hdmi_hpd_handler);
+
+static void hdmi_hpd_interrupt(enum gpio_signal signal)
+{
+	/* Debounce for 2 msec */
+	hook_call_deferred(&hdmi_hpd_handler_data, (2 * MSEC));
+}
+
+void board_set_current_limit(void)
+{
+	const int no_battery_current_limit_override_ma = 6000;
+	/*
+	 * When there is no battery, override charger current limit to
+	 * prevent brownout during boot.
+	 */
+	if (battery_is_present() == BP_NO) {
+		ccprints("No Battery Found - Override Current Limit to %dmA",
+			 no_battery_current_limit_override_ma);
+		charger_set_input_current_limit(
+			CHARGER_SOLO, no_battery_current_limit_override_ma);
+	}
+}
+DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, board_set_current_limit,
+	     HOOK_PRIO_INIT_EXTPOWER);
+
+/* Set the DCPROCHOT base on battery over discharging current 5.888A */
+static void set_dc_prochot(void)
+{
+	/*
+	 * Only bits 13:8 are usable for this register, any other bits will be
+	 * truncated.  Valid values are 256 mA to 16128 mA at 256 mA intervals.
+	 */
+	isl9241_set_dc_prochot(CHARGER_SOLO, 5888);
+}
+DECLARE_HOOK(HOOK_INIT, set_dc_prochot, HOOK_PRIO_DEFAULT);
diff --git a/board/nipperkin/board.h b/board/nipperkin/board.h
new file mode 100644
index 0000000000..af684e1f49
--- /dev/null
+++ b/board/nipperkin/board.h
@@ -0,0 +1,91 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Guybrush board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* Baseboard features */
+#include "baseboard.h"
+
+/* Motion sensing drivers */
+
+/* Keyboard features */
+#define CONFIG_KEYBOARD_FACTORY_TEST
+#define CONFIG_KEYBOARD_REFRESH_ROW3
+
+/* EC console commands */
+#define CONFIG_CMD_BUTTON
+
+/* USB Type C and USB PD defines */
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_CURRENT_MA 5000
+#define PD_MAX_VOLTAGE_MV 20000
+/* Max Power = 100 W */
+#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
+
+#define CONFIG_CHARGER_PROFILE_OVERRIDE
+
+/* USB Type A Features */
+
+/* BC 1.2 */
+
+/* Volume Button feature */
+
+/* Fan features */
+#define CONFIG_CUSTOM_FAN_CONTROL
+#define RPM_DEVIATION 1
+
+/* LED features */
+#define CONFIG_LED_COMMON
+#define CONFIG_LED_ONOFF_STATES
+
+/* Thermal Config */
+#define CONFIG_TEMP_SENSOR_PCT2075
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+/* Battery Types */
+enum battery_type {
+	BATTERY_SIMPLO_HIGHPOWER,
+	BATTERY_COSMX,
+	BATTERY_TYPE_COUNT,
+};
+
+/* ADC Channels */
+enum adc_channel {
+	ADC_TEMP_SENSOR_MEMORY = 0,
+	ADC_TEMP_SENSOR_CHARGER,
+	ADC_TEMP_SENSOR_5V_REGULATOR,
+	ADC_CORE_IMON1,
+	ADC_SOC_IMON2,
+	ADC_CH_COUNT
+};
+
+/* Temp Sensors */
+enum temp_sensor_id {
+	TEMP_SENSOR_SOC = 0,
+	TEMP_SENSOR_CHARGER,
+	TEMP_SENSOR_MEMORY,
+	TEMP_SENSOR_5V_REGULATOR,
+	TEMP_SENSOR_CPU,
+	TEMP_SENSOR_AMBIENT,
+	TEMP_SENSOR_COUNT
+};
+
+/* PCT2075 sensors */
+enum pct2075_sensor {
+	PCT2075_SOC,
+	PCT2075_AMB,
+	PCT2075_COUNT,
+};
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/nipperkin/board_fw_config.c b/board/nipperkin/board_fw_config.c
new file mode 100644
index 0000000000..e21e42689f
--- /dev/null
+++ b/board/nipperkin/board_fw_config.c
@@ -0,0 +1,31 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "base_fw_config.h"
+#include "board_fw_config.h"
+
+bool board_has_kblight(void)
+{
+	return (get_fw_config_field(FW_CONFIG_KBLIGHT_OFFSET,
+				    FW_CONFIG_KBLIGHT_WIDTH) ==
+		FW_CONFIG_KBLIGHT_YES);
+}
+
+enum board_usb_c1_mux board_get_usb_c1_mux(void)
+{
+	return USB_C1_MUX_PS8818;
+};
+
+enum board_usb_a1_retimer board_get_usb_a1_retimer(void)
+{
+	return USB_A1_RETIMER_PS8811;
+};
+
+bool board_has_privacy_panel(void)
+{
+	return (get_fw_config_field(FW_CONFIG_KEYBOARD_OFFSET,
+				    FW_CONFIG_KEYBOARD_WIDTH) ==
+		FW_CONFIG_KEYBOARD_PRIVACY_YES);
+}
diff --git a/board/nipperkin/board_fw_config.h b/board/nipperkin/board_fw_config.h
new file mode 100644
index 0000000000..f4673f732e
--- /dev/null
+++ b/board/nipperkin/board_fw_config.h
@@ -0,0 +1,35 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _NIPPERKIN_BOARD_FW_CONFIG__H_
+#define _NIPPERKIN_BOARD_FW_CONFIG__H_
+
+/****************************************************************************
+ * Nipperkin CBI FW Configuration
+ */
+
+/*
+ * Keyboard Backlight (1 bit)
+ */
+#define FW_CONFIG_KBLIGHT_OFFSET 0
+#define FW_CONFIG_KBLIGHT_WIDTH 1
+#define FW_CONFIG_KBLIGHT_NO 0
+#define FW_CONFIG_KBLIGHT_YES 1
+
+/*
+ * Bit 1 ~ 6 not related to EC function
+ */
+
+/*
+ * Keyboard (1 bit)
+ */
+#define FW_CONFIG_KEYBOARD_OFFSET 7
+#define FW_CONFIG_KEYBOARD_WIDTH 1
+#define FW_CONFIG_KEYBOARD_PRIVACY_YES 0
+#define FW_CONFIG_KEYBOARD_PRIVACY_NO 1
+
+bool board_has_privacy_panel(void);
+
+#endif /* _NIPPERKIN_BOARD_FW_CONFIG__H_ */
diff --git a/board/nipperkin/build.mk b/board/nipperkin/build.mk
new file mode 100644
index 0000000000..aad8b2ae09
--- /dev/null
+++ b/board/nipperkin/build.mk
@@ -0,0 +1,13 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+BASEBOARD:=guybrush
+
+board-y=board.o
+board-y+=board_fw_config.o led.o battery.o
+board-y+=thermal.o
diff --git a/board/nipperkin/ec.tasklist b/board/nipperkin/ec.tasklist
new file mode 100644
index 0000000000..a127b13eba
--- /dev/null
+++ b/board/nipperkin/ec.tasklist
@@ -0,0 +1,25 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, VENTI_TASK_STACK_SIZE)
diff --git a/board/nipperkin/gpio.inc b/board/nipperkin/gpio.inc
new file mode 100644
index 0000000000..0a8c6d9a65
--- /dev/null
+++ b/board/nipperkin/gpio.inc
@@ -0,0 +1,32 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the board GPIOs that we care about. */
+
+#include "base_gpio.inc"
+
+/* LED Signals */
+GPIO(C0_CHARGE_LED_AMBER_L,		PIN(C, 4), GPIO_OUT_HIGH)
+GPIO(C0_CHARGE_LED_WHITE_L,		PIN(8, 0), GPIO_OUT_HIGH)
+GPIO(C1_CHARGE_LED_AMBER_L,		PIN(6, 7), GPIO_OUT_HIGH)
+GPIO(C1_CHARGE_LED_WHITE_L,		PIN(7, 0), GPIO_OUT_HIGH)
+
+/* HDMI */
+IOEX(EN_PWR_HDMI,		EXPIN(USBC_PORT_C0, 0, 3), GPIO_OUT_LOW)
+IOEX(HDMI_DATA_EN,		EXPIN(USBC_PORT_C0, 1, 4), GPIO_OUT_LOW)
+GPIO_INT(HPD_EC_IN,		PIN(6, 2), GPIO_INT_BOTH, hdmi_hpd_interrupt)
+
+/* Power Signals */
+IOEX(USB_A1_PD_R_L,		EXPIN(USBC_PORT_C1, 1, 7), GPIO_OUT_LOW)
+
+/* Test Points */
+GPIO(EC_GPIO56,			PIN(5, 6), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(EC_GPIOB0,			PIN(B, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(EC_GPIO81,			PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(EC_FLPRG2,			PIN(8, 6), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(EC_PSL_GPO,		PIN(D, 7), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(EC_PWM7,			PIN(6, 0), GPIO_INPUT | GPIO_PULL_UP)
diff --git a/board/nipperkin/led.c b/board/nipperkin/led.c
new file mode 100644
index 0000000000..72598f8a21
--- /dev/null
+++ b/board/nipperkin/led.c
@@ -0,0 +1,228 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "chipset.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "led_common.h"
+
+#define BAT_LED_ON 0
+#define BAT_LED_OFF 1
+
+#define POWER_LED_ON 0
+#define POWER_LED_OFF 1
+
+#define LED_TICKS_PER_CYCLE 10
+#define LED_TICKS_PER_CYCLE_S3 10
+#define LED_ON_TICKS 5
+#define POWER_LED_ON_S3_TICKS 5
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_LEFT_LED,
+	EC_LED_ID_RIGHT_LED,
+};
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+enum led_color {
+	LED_OFF = 0,
+	LED_AMBER,
+	LED_WHITE,
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
+};
+
+enum led_port { LED_LEFT_PORT = 0, LED_RIGHT_PORT };
+
+static void led_set_color_battery(enum led_port port, enum led_color color)
+{
+	enum gpio_signal amber_led, white_led;
+
+	amber_led = (port == LED_LEFT_PORT ? GPIO_C0_CHARGE_LED_AMBER_L :
+					     GPIO_C1_CHARGE_LED_AMBER_L);
+	white_led = (port == LED_LEFT_PORT ? GPIO_C0_CHARGE_LED_WHITE_L :
+					     GPIO_C1_CHARGE_LED_WHITE_L);
+
+	switch (color) {
+	case LED_WHITE:
+		gpio_set_level(white_led, BAT_LED_ON);
+		gpio_set_level(amber_led, BAT_LED_OFF);
+		break;
+	case LED_AMBER:
+		gpio_set_level(white_led, BAT_LED_OFF);
+		gpio_set_level(amber_led, BAT_LED_ON);
+		break;
+	case LED_OFF:
+		gpio_set_level(white_led, BAT_LED_OFF);
+		gpio_set_level(amber_led, BAT_LED_OFF);
+		break;
+	default:
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	switch (led_id) {
+	case EC_LED_ID_LEFT_LED:
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		break;
+	case EC_LED_ID_RIGHT_LED:
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		break;
+	default:
+		break;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	switch (led_id) {
+	case EC_LED_ID_LEFT_LED:
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_battery(LED_LEFT_PORT, LED_WHITE);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(LED_LEFT_PORT, LED_AMBER);
+		else
+			led_set_color_battery(LED_LEFT_PORT, LED_OFF);
+		break;
+	case EC_LED_ID_RIGHT_LED:
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_battery(LED_RIGHT_PORT, LED_WHITE);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(LED_RIGHT_PORT, LED_AMBER);
+		else
+			led_set_color_battery(LED_RIGHT_PORT, LED_OFF);
+		break;
+	default:
+		return EC_ERROR_PARAM1;
+	}
+
+	return EC_SUCCESS;
+}
+
+/*
+ * Set active charge port color to the parameter, turn off all others.
+ * If no port is active (-1), turn off all LEDs.
+ */
+static void set_active_port_color(enum led_color color)
+{
+	int port = charge_manager_get_active_charge_port();
+
+	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
+		led_set_color_battery(LED_RIGHT_PORT, (port == LED_RIGHT_PORT) ?
+							      color :
+							      LED_OFF);
+	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
+		led_set_color_battery(LED_LEFT_PORT, (port == LED_LEFT_PORT) ?
+							     color :
+							     LED_OFF);
+}
+
+static void led_set_battery(void)
+{
+	static int battery_ticks;
+	static int power_ticks;
+
+	battery_ticks++;
+
+	/*
+	 * Override battery LEDs for Nipperkin, Nipperkin is non-power LED
+	 * design, blinking both two side battery white LEDs to indicate
+	 * system suspend with non-charging state.
+	 */
+	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
+	    led_pwr_get_state() != LED_PWRS_CHARGE) {
+		power_ticks++;
+
+		led_set_color_battery(LED_RIGHT_PORT,
+				      power_ticks % LED_TICKS_PER_CYCLE_S3 <
+						      POWER_LED_ON_S3_TICKS ?
+					      LED_WHITE :
+					      LED_OFF);
+		led_set_color_battery(LED_LEFT_PORT,
+				      power_ticks % LED_TICKS_PER_CYCLE_S3 <
+						      POWER_LED_ON_S3_TICKS ?
+					      LED_WHITE :
+					      LED_OFF);
+		return;
+	}
+
+	power_ticks = 0;
+
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
+		/* Always indicate when charging, even in suspend. */
+		set_active_port_color(LED_AMBER);
+		break;
+	case LED_PWRS_DISCHARGE:
+		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
+			if (charge_get_percent() < 10)
+				led_set_color_battery(
+					LED_RIGHT_PORT,
+					(battery_ticks % LED_TICKS_PER_CYCLE <
+					 LED_ON_TICKS) ?
+						LED_AMBER :
+						LED_OFF);
+			else
+				led_set_color_battery(LED_RIGHT_PORT, LED_OFF);
+		}
+
+		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) {
+			if (charge_get_percent() < 10)
+				led_set_color_battery(
+					LED_LEFT_PORT,
+					(battery_ticks % LED_TICKS_PER_CYCLE <
+					 LED_ON_TICKS) ?
+						LED_AMBER :
+						LED_OFF);
+			else
+				led_set_color_battery(LED_LEFT_PORT, LED_OFF);
+		}
+		break;
+	case LED_PWRS_ERROR:
+		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
+			led_set_color_battery(
+				LED_RIGHT_PORT,
+				(battery_ticks & 0x1) ? LED_AMBER : LED_OFF);
+		}
+
+		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) {
+			led_set_color_battery(
+				LED_LEFT_PORT,
+				(battery_ticks & 0x1) ? LED_AMBER : LED_OFF);
+		}
+		break;
+
+	case LED_PWRS_CHARGE_NEAR_FULL:
+		set_active_port_color(LED_WHITE);
+		break;
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		set_active_port_color(LED_WHITE);
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		set_active_port_color(
+			(battery_ticks % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
+				LED_AMBER :
+				LED_OFF);
+		break;
+	default:
+		/* Other states don't alter LED behavior */
+		break;
+	}
+}
+
+/* Called by hook task every TICK */
+static void led_tick(void)
+{
+	led_set_battery();
+}
+DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
diff --git a/board/nipperkin/thermal.c b/board/nipperkin/thermal.c
new file mode 100644
index 0000000000..117a6d08fa
--- /dev/null
+++ b/board/nipperkin/thermal.c
@@ -0,0 +1,239 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery_smart.h"
+#include "charge_state.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "fan.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "tablet_mode.h"
+#include "temp_sensor.h"
+#include "thermal.h"
+#include "util.h"
+
+/* Console output macros */
+#define CPUTS(outstr) cputs(CC_THERMAL, outstr)
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
+
+const struct fan_conf fan_conf_0 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
+	.pgood_gpio = GPIO_S0_PGOOD,
+	.enable_gpio = -1,
+};
+const struct fan_rpm fan_rpm_0 = {
+	.rpm_min = 1000,
+	.rpm_start = 1000,
+	.rpm_max = 6500,
+};
+const struct fan_t fans[] = {
+	[FAN_CH_0] = {
+		.conf = &fan_conf_0,
+		.rpm = &fan_rpm_0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
+
+struct fan_step {
+	/*
+	 * Sensor 1~4 trigger point, set -1 if we're not using this
+	 * sensor to determine fan speed.
+	 */
+	int8_t on[TEMP_SENSOR_COUNT];
+
+	/*
+	 * Sensor 1~4 trigger point, set -1 if we're not using this
+	 * sensor to determine fan speed.
+	 */
+	int8_t off[TEMP_SENSOR_COUNT];
+
+	/* Fan 1~2 rpm */
+	uint16_t rpm[FAN_CH_COUNT];
+};
+
+static const struct fan_step fan_step_table[] = {
+	{
+		/* level 0 */
+		.on = { 51, 0, 44, -1, -1, -1 },
+		.off = { 99, 99, 99, -1, -1, -1 },
+		.rpm = { 0 },
+	},
+	{
+		/* level 1 */
+		.on = { 52, 0, 47, -1, -1, -1 },
+		.off = { 50, 99, 43, -1, -1, -1 },
+		.rpm = { 3000 },
+	},
+	{
+		/* level 2 */
+		.on = { 53, 0, 49, -1, -1, -1 },
+		.off = { 51, 99, 45, -1, -1, -1 },
+		.rpm = { 3400 },
+	},
+	{
+		/* level 3 */
+		.on = { 54, 0, 51, -1, -1, -1 },
+		.off = { 52, 99, 47, -1, -1, -1 },
+		.rpm = { 3800 },
+	},
+	{
+		/* level 4 */
+		.on = { 56, 50, 53, -1, -1, -1 },
+		.off = { 53, 47, 49, -1, -1, -1 },
+		.rpm = { 4100 },
+	},
+	{
+		/* level 5 */
+		.on = { 57, 52, 55, -1, -1, -1 },
+		.off = { 55, 49, 51, -1, -1, -1 },
+		.rpm = { 4400 },
+	},
+	{
+		/* level 6 */
+		.on = { 100, 100, 100, -1, -1, -1 },
+		.off = { 56, 51, 53, -1, -1, -1 },
+		.rpm = { 4900 },
+	},
+};
+
+#define NUM_FAN_LEVELS ARRAY_SIZE(fan_step_table)
+
+BUILD_ASSERT(ARRAY_SIZE(fan_step_table) == ARRAY_SIZE(fan_step_table));
+
+int fan_table_to_rpm(int fan, int *temp)
+{
+	static int current_level;
+	static int prev_tmp[TEMP_SENSOR_COUNT];
+	int new_rpm = 0;
+	int i;
+
+	/*
+	 * Compare the current and previous temperature, we have
+	 * the three paths :
+	 *  1. decreasing path. (check the release point)
+	 *  2. increasing path. (check the trigger point)
+	 *  3. invariant path. (return the current RPM)
+	 */
+	if (temp[TEMP_SENSOR_CHARGER] < prev_tmp[TEMP_SENSOR_CHARGER] ||
+	    temp[TEMP_SENSOR_MEMORY] < prev_tmp[TEMP_SENSOR_MEMORY] ||
+	    temp[TEMP_SENSOR_SOC] < prev_tmp[TEMP_SENSOR_SOC]) {
+		for (i = current_level; i > 0; i--) {
+			if (temp[TEMP_SENSOR_CHARGER] <
+				    fan_step_table[i].off[TEMP_SENSOR_CHARGER] &&
+			    temp[TEMP_SENSOR_MEMORY] <
+				    fan_step_table[i].off[TEMP_SENSOR_MEMORY] &&
+			    temp[TEMP_SENSOR_SOC] <
+				    fan_step_table[i].off[TEMP_SENSOR_SOC]) {
+				current_level = i - 1;
+			} else
+				break;
+		}
+	} else if (temp[TEMP_SENSOR_CHARGER] > prev_tmp[TEMP_SENSOR_CHARGER] ||
+		   temp[TEMP_SENSOR_MEMORY] > prev_tmp[TEMP_SENSOR_MEMORY] ||
+		   temp[TEMP_SENSOR_SOC] > prev_tmp[TEMP_SENSOR_SOC]) {
+		for (i = current_level; i < NUM_FAN_LEVELS; i++) {
+			if ((temp[TEMP_SENSOR_CHARGER] >
+				     fan_step_table[i].on[TEMP_SENSOR_CHARGER] &&
+			     temp[TEMP_SENSOR_MEMORY] >
+				     fan_step_table[i].on[TEMP_SENSOR_MEMORY]) ||
+			    temp[TEMP_SENSOR_SOC] >
+				    fan_step_table[i].on[TEMP_SENSOR_SOC]) {
+				current_level = i + 1;
+			} else
+				break;
+		}
+	}
+
+	if (current_level < 0)
+		current_level = 0;
+
+	if (current_level >= NUM_FAN_LEVELS)
+		current_level = NUM_FAN_LEVELS - 1;
+
+	for (i = 0; i < TEMP_SENSOR_COUNT; ++i)
+		prev_tmp[i] = temp[i];
+
+	new_rpm = fan_step_table[current_level].rpm[FAN_CH_0];
+
+	return new_rpm;
+}
+
+void board_override_fan_control(int fan, int *tmp)
+{
+	if (chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND)) {
+		fan_set_rpm_mode(FAN_CH(fan), 1);
+		fan_set_rpm_target(FAN_CH(fan), fan_table_to_rpm(fan, tmp));
+	}
+}
+
+struct chg_curr_step {
+	int on;
+	int off;
+	int curr_ma;
+};
+
+static const struct chg_curr_step chg_curr_table[] = {
+	{ .on = 0, .off = 0, .curr_ma = 3566 },
+	{ .on = 66, .off = 65, .curr_ma = 2500 },
+	{ .on = 70, .off = 69, .curr_ma = 1500 },
+};
+
+#define NUM_CHG_CURRENT_LEVELS ARRAY_SIZE(chg_curr_table)
+
+int charger_profile_override(struct charge_state_data *curr)
+{
+	int rv;
+	int chg_temp_c;
+	int current;
+	int thermal_sensor_chrg;
+	static int current_level;
+	static int prev_tmp;
+
+	if (!(curr->batt.flags & BATT_FLAG_RESPONSIVE))
+		return 0;
+
+	current = curr->requested_current;
+
+	rv = temp_sensor_read(TEMP_SENSOR_CHARGER, &thermal_sensor_chrg);
+	chg_temp_c = K_TO_C(thermal_sensor_chrg);
+
+	if (rv != EC_SUCCESS)
+		return rv;
+
+	if (chipset_in_state(CHIPSET_STATE_ON)) {
+		if (chg_temp_c < prev_tmp) {
+			if ((chg_temp_c <= chg_curr_table[current_level].off) &&
+			    (current_level > 0))
+				current_level -= 1;
+		} else if (chg_temp_c > prev_tmp) {
+			if ((chg_temp_c >=
+			     chg_curr_table[current_level + 1].on) &&
+			    (current_level < NUM_CHG_CURRENT_LEVELS - 1))
+				current_level += 1;
+		}
+
+		prev_tmp = chg_temp_c;
+		current = chg_curr_table[current_level].curr_ma;
+
+		curr->requested_current = MIN(curr->requested_current, current);
+	}
+
+	return 0;
+}
+
+enum ec_status charger_profile_override_get_param(uint32_t param,
+						  uint32_t *value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+enum ec_status charger_profile_override_set_param(uint32_t param,
+						  uint32_t value)
+{
+	return EC_RES_INVALID_PARAM;
+}
diff --git a/board/nipperkin/vif_override.xml b/board/nipperkin/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/nipperkin/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/nocturne/base_detect.c b/board/nocturne/base_detect.c
index 3735080c49..807aa3e14a 100644
--- a/board/nocturne/base_detect.c
+++ b/board/nocturne/base_detect.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,8 +26,8 @@
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USB, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args)
 
 #define DEFAULT_POLL_TIMEOUT_US (250 * MSEC)
 #define DEBOUNCE_TIMEOUT_US (20 * MSEC)
@@ -62,7 +62,6 @@
  */
 #define WINDOW_SIZE 5
 
-
 enum base_detect_state {
 	BASE_DETACHED = 0,
 	BASE_ATTACHED_DEBOUNCE,
@@ -82,7 +81,7 @@ static timestamp_t detached_decision_deadline;
 static void enable_base_interrupts(int enable)
 {
 	int (*fn)(enum gpio_signal) = enable ? gpio_enable_interrupt :
-		gpio_disable_interrupt;
+					       gpio_disable_interrupt;
 
 	/* This pin is present on boards newer than rev 0. */
 	if (board_get_version() > 0)
@@ -141,28 +140,26 @@ static void base_detect_changed(void)
 static int base_seems_attached(int attach_pin_mv, int detach_pin_mv)
 {
 	/* We can't tell if we don't have good readings. */
-	if (attach_pin_mv == ADC_READ_ERROR ||
-	    detach_pin_mv == ADC_READ_ERROR)
+	if (attach_pin_mv == ADC_READ_ERROR || detach_pin_mv == ADC_READ_ERROR)
 		return 0;
 
 	if (gpio_get_level(GPIO_BASE_PWR_EN))
 		return (attach_pin_mv >= PWREN_ATTACH_MIN_MV) &&
-			(detach_pin_mv >= DETACH_MIN_MV);
+		       (detach_pin_mv >= DETACH_MIN_MV);
 	else
 		return (attach_pin_mv <= ATTACH_MAX_MV) &&
-			(attach_pin_mv >= ATTACH_MIN_MV) &&
-			(detach_pin_mv <= DETACH_MIN_MV);
+		       (attach_pin_mv >= ATTACH_MIN_MV) &&
+		       (detach_pin_mv <= DETACH_MIN_MV);
 }
 
 static int base_seems_detached(int attach_pin_mv, int detach_pin_mv)
 {
 	/* We can't tell if we don't have good readings. */
-	if (attach_pin_mv == ADC_READ_ERROR ||
-	    detach_pin_mv == ADC_READ_ERROR)
+	if (attach_pin_mv == ADC_READ_ERROR || detach_pin_mv == ADC_READ_ERROR)
 		return 0;
 
 	return (attach_pin_mv >= PWREN_ATTACH_MIN_MV) &&
-		(detach_pin_mv <= DETACH_MIN_MV);
+	       (detach_pin_mv <= DETACH_MIN_MV);
 }
 
 static void set_state(enum base_detect_state new_state)
@@ -194,9 +191,9 @@ static void base_detect_deferred(void)
 
 	if (forced_state != BASE_NO_FORCED_STATE) {
 		if (state != forced_state) {
-			CPRINTS("BD forced  %s",
-				forced_state == BASE_ATTACHED ?
-				"attached" : "detached");
+			CPRINTS("BD forced  %s", forced_state == BASE_ATTACHED ?
+							 "attached" :
+							 "detached");
 			set_state(forced_state);
 			base_detect_changed();
 		}
@@ -212,8 +209,7 @@ static void base_detect_deferred(void)
 	if (debug) {
 		int i;
 
-		CPRINTS("BD st%d: att: %dmV det: %dmV", state,
-			attach_reading,
+		CPRINTS("BD st%d: att: %dmV det: %dmV", state, attach_reading,
 			detach_reading);
 		CPRINTF("det readings = [");
 		for (i = 0; i < WINDOW_SIZE; i++)
@@ -341,7 +337,6 @@ static void check_and_reapply_base_power_deferred(void)
 		hook_call_deferred(&clear_base_power_on_attempts_deferred_data,
 				   SECOND);
 	}
-
 }
 DECLARE_DEFERRED(check_and_reapply_base_power_deferred);
 
@@ -366,25 +361,24 @@ void base_pwr_fault_interrupt(enum gpio_signal s)
 	}
 }
 
-static int command_basedetectdebug(int argc, char **argv)
+static int command_basedetectdebug(int argc, const char **argv)
 {
 	if ((argc > 1) && !parse_bool(argv[1], &debug))
 		return EC_ERROR_PARAM1;
 
-	CPRINTS("BD: %sst%d", forced_state != BASE_NO_FORCED_STATE ?
-						  "forced " : "", state);
+	CPRINTS("BD: %sst%d",
+		forced_state != BASE_NO_FORCED_STATE ? "forced " : "", state);
 	return EC_SUCCESS;
 }
 
 DECLARE_CONSOLE_COMMAND(basedebug, command_basedetectdebug, "[ena|dis]",
 			"En/Disable base detection debug");
 
-
-void base_force_state(int state)
+void base_force_state(enum ec_set_base_state_cmd state)
 {
-	if (state == 1)
+	if (state == EC_SET_BASE_STATE_ATTACH)
 		forced_state = BASE_ATTACHED;
-	else if (state == 0)
+	else if (state == EC_SET_BASE_STATE_DETACH)
 		forced_state = BASE_DETACHED;
 	else
 		forced_state = BASE_NO_FORCED_STATE;
diff --git a/board/nocturne/battery.c b/board/nocturne/battery.c
index 67c5346063..4914f89b2e 100644
--- a/board/nocturne/battery.c
+++ b/board/nocturne/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,38 +8,39 @@
 #include "battery.h"
 #include "battery_smart.h"
 #include "charge_manager.h"
+#include "charge_state.h"
 #include "charger.h"
 #include "chipset.h"
-#include "charge_state_v2.h"
 #include "common.h"
 #include "console.h"
 #include "ec_commands.h"
 #include "extpower.h"
+#include "gpio.h"
 #include "hooks.h"
 #include "temp_sensor.h"
 #include "usb_pd.h"
 
 /* Shutdown mode parameter to write to manufacturer access register */
-#define SB_SHUTDOWN_DATA	0x0010
+#define SB_SHUTDOWN_DATA 0x0010
 
 /*
  * We need to stop charging the battery when the DRAM temperature sensor gets
  * over 47 C (320 K), and resume charging once it cools back down.
  */
-#define DRAM_STOPCHARGE_TEMP_K	320
+#define DRAM_STOPCHARGE_TEMP_K 320
 
 /* Battery info */
 static const struct battery_info info = {
-	.voltage_max		= 8880,
-	.voltage_normal		= 7700,
-	.voltage_min		= 6000,
-	.precharge_current	= 160,
-	.start_charging_min_c	= 10,
-	.start_charging_max_c	= 50,
-	.charging_min_c		= 10,
-	.charging_max_c		= 50,
-	.discharging_min_c	= -20,
-	.discharging_max_c	= 60,
+	.voltage_max = 8880,
+	.voltage_normal = 7700,
+	.voltage_min = 6000,
+	.precharge_current = 160,
+	.start_charging_min_c = 10,
+	.start_charging_max_c = 50,
+	.charging_min_c = 10,
+	.charging_max_c = 50,
+	.discharging_min_c = -20,
+	.discharging_max_c = 60,
 };
 
 int board_cut_off_battery(void)
@@ -77,8 +78,8 @@ enum battery_disconnect_state battery_get_disconnect_state(void)
 		return BATTERY_NOT_DISCONNECTED;
 
 	/* Check if battery discharge FET is disabled. */
-	rv = sb_read_mfgacc(PARAM_OPERATION_STATUS,
-			    SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data));
+	rv = sb_read_mfgacc(PARAM_OPERATION_STATUS, SB_ALT_MANUFACTURER_ACCESS,
+			    data, sizeof(data));
 	if (rv)
 		return BATTERY_DISCONNECT_ERROR;
 	if (~data[3] & (BATTERY_DISCHARGING_DISABLED)) {
@@ -90,8 +91,8 @@ enum battery_disconnect_state battery_get_disconnect_state(void)
 	 * Battery discharge FET is disabled.  Verify that we didn't enter this
 	 * state due to a safety fault.
 	 */
-	rv = sb_read_mfgacc(PARAM_SAFETY_STATUS,
-			    SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data));
+	rv = sb_read_mfgacc(PARAM_SAFETY_STATUS, SB_ALT_MANUFACTURER_ACCESS,
+			    data, sizeof(data));
 	if (rv || data[2] || data[3] || data[4] || data[5])
 		return BATTERY_DISCONNECT_ERROR;
 
@@ -99,32 +100,6 @@ enum battery_disconnect_state battery_get_disconnect_state(void)
 	return BATTERY_DISCONNECTED;
 }
 
-static void reduce_input_voltage_when_full(void)
-{
-	struct batt_params batt;
-	int max_pd_voltage_mv;
-	int active_chg_port;
-
-	active_chg_port = charge_manager_get_active_charge_port();
-	if (active_chg_port == CHARGE_PORT_NONE)
-		return;
-
-	battery_get_params(&batt);
-	if (!(batt.flags & BATT_FLAG_BAD_STATUS)) {
-		/* Lower our input voltage to 9V when battery is full. */
-		if ((batt.status & STATUS_FULLY_CHARGED) &&
-		    chipset_in_state(CHIPSET_STATE_ANY_OFF))
-			max_pd_voltage_mv = 9000;
-		else
-			max_pd_voltage_mv = PD_MAX_VOLTAGE_MV;
-
-		if (pd_get_max_voltage() != max_pd_voltage_mv)
-			pd_set_external_voltage_limit(active_chg_port,
-						      max_pd_voltage_mv);
-	}
-}
-DECLARE_HOOK(HOOK_SECOND, reduce_input_voltage_when_full, HOOK_PRIO_DEFAULT);
-
 enum ec_status charger_profile_override_get_param(uint32_t param,
 						  uint32_t *value)
 {
diff --git a/board/nocturne/board.c b/board/nocturne/board.c
index 6a45cabf4c..de7671163b 100644
--- a/board/nocturne/board.c
+++ b/board/nocturne/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,11 +9,10 @@
 #include "button.h"
 #include "charge_manager.h"
 #include "charge_state.h"
-#include "charge_state_v2.h"
 #include "chipset.h"
 #include "common.h"
-#include "console.h"
 #include "compile_time_macros.h"
+#include "console.h"
 #include "driver/accelgyro_bmi_common.h"
 #include "driver/als_opt3001.h"
 #include "driver/charger/isl923x.h"
@@ -30,24 +29,25 @@
 #include "lpc.h"
 #include "mkbp_event.h"
 #include "motion_sense.h"
+#include "panic.h"
 #include "power.h"
 #include "power_button.h"
 #include "pwm.h"
 #include "pwm_chip.h"
 #include "registers.h"
+#include "switch.h"
 #include "system.h"
 #include "system_chip.h"
-#include "switch.h"
 #include "task.h"
-#include "tcpci.h"
+#include "tcpm/tcpci.h"
 #include "temp_sensor.h"
 #include "usb_mux.h"
 #include "usb_pd_tcpm.h"
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void tcpc_alert_event(enum gpio_signal s)
 {
@@ -94,6 +94,7 @@ static void board_connect_c0_sbu(enum gpio_signal s)
 	hook_call_deferred(&board_connect_c0_sbu_deferred_data, 0);
 }
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 const enum gpio_signal hibernate_wake_pins[] = {
@@ -101,63 +102,67 @@ const enum gpio_signal hibernate_wake_pins[] = {
 	GPIO_AC_PRESENT,
 	GPIO_POWER_BUTTON_L,
 };
-const int hibernate_wake_pins_used =  ARRAY_SIZE(hibernate_wake_pins);
+const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 
 const struct adc_t adc_channels[] = {
-	[ADC_BASE_ATTACH] = {
-		"BASE ATTACH", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0
-	},
+	[ADC_BASE_ATTACH] = { "BASE ATTACH", NPCX_ADC_CH0, ADC_MAX_VOLT,
+			      ADC_READ_MAX + 1, 0 },
 
-	[ADC_BASE_DETACH] = {
-		"BASE DETACH", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0
-	},
+	[ADC_BASE_DETACH] = { "BASE DETACH", NPCX_ADC_CH1, ADC_MAX_VOLT,
+			      ADC_READ_MAX + 1, 0 },
 };
 
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_DB0_LED_RED] =   { 3, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-				   986 },
+	[PWM_CH_DB0_LED_RED] = { 3, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+				 986 },
 	[PWM_CH_DB0_LED_GREEN] = { 0, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
 				   986 },
-	[PWM_CH_DB0_LED_BLUE] =  { 2, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-				   986 },
-	[PWM_CH_DB1_LED_RED] =   { 7, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-				   986 },
+	[PWM_CH_DB0_LED_BLUE] = { 2, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+				  986 },
+	[PWM_CH_DB1_LED_RED] = { 7, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+				 986 },
 	[PWM_CH_DB1_LED_GREEN] = { 5, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
 				   986 },
-	[PWM_CH_DB1_LED_BLUE] =  { 6, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-				   986 },
+	[PWM_CH_DB1_LED_BLUE] = { 6, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+				  986 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
 /* I2C port map */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		"battery", I2C_PORT_BATTERY, 100, GPIO_EC_I2C4_BATTERY_SCL,
-		GPIO_EC_I2C4_BATTERY_SDA
-	},
-
-	{
-		"power", I2C_PORT_POWER, 100, GPIO_EC_I2C0_POWER_SCL,
-		GPIO_EC_I2C0_POWER_SDA
-	},
-
-	{
-		"als_gyro", I2C_PORT_ALS_GYRO, 400, GPIO_EC_I2C5_ALS_GYRO_SCL,
-		GPIO_EC_I2C5_ALS_GYRO_SDA
-	},
-
-	{
-		"usbc0", I2C_PORT_USB_C0, 100, GPIO_USB_C0_SCL, GPIO_USB_C0_SDA
-	},
-
-	{
-		"usbc1", I2C_PORT_USB_C1, 100, GPIO_USB_C1_SCL, GPIO_USB_C1_SDA
-	},
+	{ .name = "battery",
+	  .port = I2C_PORT_BATTERY,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C4_BATTERY_SCL,
+	  .sda = GPIO_EC_I2C4_BATTERY_SDA },
+
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C0_POWER_SCL,
+	  .sda = GPIO_EC_I2C0_POWER_SDA },
+
+	{ .name = "als_gyro",
+	  .port = I2C_PORT_ALS_GYRO,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C5_ALS_GYRO_SCL,
+	  .sda = GPIO_EC_I2C5_ALS_GYRO_SDA },
+
+	{ .name = "usbc0",
+	  .port = I2C_PORT_USB_C0,
+	  .kbps = 100,
+	  .scl = GPIO_USB_C0_SCL,
+	  .sda = GPIO_USB_C0_SDA },
+
+	{ .name = "usbc1",
+	  .port = I2C_PORT_USB_C1,
+	  .kbps = 100,
+	  .scl = GPIO_USB_C1_SCL,
+	  .sda = GPIO_USB_C1_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
-
 /*
  * Motion Sense
  */
@@ -174,11 +179,9 @@ static struct opt3001_drv_data_t g_opt3001_data = {
 };
 
 /* Matrix to rotate accel/gyro into standard reference frame. */
-const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1),  0},
-	{ FLOAT_TO_FP(-1), 0,  0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+				      { FLOAT_TO_FP(-1), 0, 0 },
+				      { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
@@ -286,11 +289,9 @@ static void enable_sensor_irqs(void)
 DECLARE_HOOK(HOOK_CHIPSET_RESUME, enable_sensor_irqs, HOOK_PRIO_DEFAULT);
 
 struct ppc_config_t ppc_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
+	{ .i2c_port = I2C_PORT_USB_C0,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
 	{
 		.i2c_port = I2C_PORT_USB_C1,
 		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
@@ -304,7 +305,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = I2C_PORT_USB_C0,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
 		},
 		.drv = &ps8xxx_tcpm_drv,
 	},
@@ -312,23 +313,29 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = I2C_PORT_USB_C1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
 		},
 		.drv = &ps8xxx_tcpm_drv,
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	},
 
 	{
-		.usb_port = 1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	},
 };
 
@@ -349,8 +356,7 @@ DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
 static void imvp8_tune_deferred(void)
 {
 	/* For the IMVP8, reduce the steps during decay from 3 to 1. */
-	if (i2c_write16(I2C_PORT_POWER, I2C_ADDR_MP2949_FLAGS,
-			0xFA, 0x0AC5))
+	if (i2c_write16(I2C_PORT_POWER, I2C_ADDR_MP2949_FLAGS, 0xFA, 0x0AC5))
 		CPRINTS("Failed to change step decay!");
 }
 DECLARE_DEFERRED(imvp8_tune_deferred);
@@ -505,8 +511,7 @@ static void board_pmic_enable_slp_s0_vr_decay(void)
 	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x38, 0x6a);
 }
 
-__override void power_board_handle_host_sleep_event(
-		enum host_sleep_event state)
+__override void power_board_handle_host_sleep_event(enum host_sleep_event state)
 {
 	if (state == HOST_SLEEP_EVENT_S0IX_SUSPEND)
 		board_pmic_enable_slp_s0_vr_decay();
@@ -519,8 +524,7 @@ static void board_pmic_init(void)
 	int pgmask1;
 
 	/* Mask V5A_DS3_PG from PMIC PGMASK1. */
-	if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS,
-		      0x18, &pgmask1))
+	if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x18, &pgmask1))
 		return;
 	pgmask1 |= BIT(2);
 	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x18, pgmask1);
@@ -594,19 +598,19 @@ static int read_gyro_sensor_temp(int idx, int *temp_ptr)
 }
 
 const struct temp_sensor_t temp_sensors[] = {
-	{"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0},
+	{ "Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0 },
 
 	/* These BD99992GW temp sensors are only readable in S0 */
-	{"Ambient", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM0},
-	{"Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM1},
-	{"DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM2},
-	{"eMMC", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM3},
+	{ "Ambient", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM0 },
+	{ "Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM1 },
+	{ "DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM2 },
+	{ "eMMC", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM3 },
 	/* The Gyro temperature sensor is only readable in S0. */
-	{"Gyro", TEMP_SENSOR_TYPE_BOARD, read_gyro_sensor_temp, LID_GYRO}
+	{ "Gyro", TEMP_SENSOR_TYPE_BOARD, read_gyro_sensor_temp, LID_GYRO }
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -616,16 +620,15 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
  */
 struct ec_thermal_config thermal_params[] = {
 	/* {Twarn, Thigh, Thalt}, fan_off, fan_max */
-	{{0,          0, 0}, {0, 0, 0}, 0, 0}, /* Battery */
-	{{0,          0, 0}, {0, 0, 0}, 0, 0}, /* Ambient */
-	{{0,          0, 0}, {0, 0, 0}, 0, 0}, /* Charger */
-	{{0, C_TO_K(52), 0}, {0, 0, 0}, 0, 0}, /* DRAM */
-	{{0,          0, 0}, {0, 0, 0}, 0, 0}, /* eMMC */
-	{{0,          0, 0}, {0, 0, 0}, 0, 0}  /* Gyro */
+	{ { 0, 0, 0 }, { 0, 0, 0 }, 0, 0 }, /* Battery */
+	{ { 0, 0, 0 }, { 0, 0, 0 }, 0, 0 }, /* Ambient */
+	{ { 0, 0, 0 }, { 0, 0, 0 }, 0, 0 }, /* Charger */
+	{ { 0, C_TO_K(52), 0 }, { 0, 0, 0 }, 0, 0 }, /* DRAM */
+	{ { 0, 0, 0 }, { 0, 0, 0 }, 0, 0 }, /* eMMC */
+	{ { 0, 0, 0 }, { 0, 0, 0 }, 0, 0 } /* Gyro */
 };
 BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
 
-
 /*
  * Check if PMIC fault registers indicate VR fault. If yes, print out fault
  * register info to console. Additionally, set panic reason so that the OS can
@@ -638,8 +641,8 @@ static void board_report_pmic_fault(const char *str)
 	uint32_t info;
 
 	/* RESETIRQ1 -- Bit 4: VRFAULT */
-	if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x8, &vrfault)
-	    != EC_SUCCESS)
+	if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x8, &vrfault) !=
+	    EC_SUCCESS)
 		return;
 
 	if (!(vrfault & BIT(4)))
@@ -692,8 +695,7 @@ void board_set_tcpc_power_mode(int port, int mode)
 
 int board_set_active_charge_port(int port)
 {
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	int i;
 	int rv;
 	int old_port;
@@ -758,19 +760,6 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
-
-	/*
-	 * Nocturne seems to overdraw its set input current limit by about 5%.
-	 * Request at most 95% of what's desired.
-	 */
-	icl = icl * 95 / 100;
-	charge_set_input_current_limit(icl, charge_mv);
-}
-
 static void board_chipset_reset(void)
 {
 	board_report_pmic_fault("CHIPSET RESET");
diff --git a/board/nocturne/board.h b/board/nocturne/board.h
index a97b242978..6c46a2949b 100644
--- a/board/nocturne/board.h
+++ b/board/nocturne/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,36 +8,35 @@
 #ifndef __CROS_EC_BOARD_H
 #define __CROS_EC_BOARD_H
 
+#define CONFIG_LTO
+
 /*
  * By default, enable all console messages excepted HC, ACPI and event:
  * The sensor stack is generating a lot of activity.
  */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
 #undef CONFIG_HOSTCMD_DEBUG_MODE
 #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
 
-#define CONFIG_SUPPRESSED_HOST_COMMANDS \
-	EC_CMD_CONSOLE_SNAPSHOT, EC_CMD_CONSOLE_READ, EC_CMD_PD_GET_LOG_ENTRY
-
 /* NPCX7 config */
-#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
-#define NPCX_TACH_SEL2    0  /* No tach. */
-#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
+#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */
+#define NPCX_TACH_SEL2 0 /* No tach. */
+#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */
 #define CONFIG_HIBERNATE_PSL
 
 /* Internal SPI flash on NPCX7 */
-#define CONFIG_FLASH_SIZE (512 * 1024) /* It's really 1MB. */
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* It's really 1MB. */
 #define CONFIG_SPI_FLASH_REGS
 #define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
 
 /* EC modules */
 #define CONFIG_ADC
 #define CONFIG_BACKLIGHT_LID
-#define CONFIG_BOARD_VERSION_CUSTOM
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
+#define CONFIG_FPU
 #define CONFIG_I2C
 #define CONFIG_I2C_BUS_MAY_BE_UNPOWERED
-#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_CONTROLLER
 #define CONFIG_LOW_POWER_IDLE
 #define CONFIG_PWM
 #define CONFIG_THROTTLE_AP
@@ -60,6 +59,7 @@
 #define CONFIG_BATTERY_SMART
 #define CONFIG_BATTERY_REVIVE_DISCONNECT
 #define CONFIG_BATTERY_PRESENT_GPIO GPIO_BAT_PRESENT_L
+#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV 9000
 
 /* Buttons / Switches */
 #define CONFIG_BASE_ATTACHED_SWITCH
@@ -70,8 +70,16 @@
 #define CONFIG_CHARGE_MANAGER
 #define CONFIG_CHARGER
 #define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT 128
+#define CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT 128
+#define CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT 128
 #define CONFIG_CHARGER_ISL9238
+/*
+ * Nocturne seems to overdraw its set input current limit by about 5%.
+ * Request at most 95% of what's desired.
+ */
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 5
+#undef CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON
 #define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 1
 #define CONFIG_CHARGER_PROFILE_OVERRIDE
 #define CONFIG_CHARGER_SENSE_RESISTOR 10
@@ -87,8 +95,8 @@
 
 /* MKBP */
 #define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_EVENT_WAKEUP_MASK (1<<EC_MKBP_EVENT_SWITCH)
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
+#define CONFIG_MKBP_EVENT_WAKEUP_MASK (1 << EC_MKBP_EVENT_SWITCH)
+#define CONFIG_MKBP_INPUT_DEVICES
 #define CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT
 
 /* Sensors */
@@ -102,13 +110,11 @@
 #define CONFIG_ACCEL_FIFO_SIZE 512
 /* Depends on how fast the AP boots and typical ODRs */
 #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-#define CONFIG_ACCEL_INTERRUPTS
 #define CONFIG_ACCELGYRO_BMI160
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
 #define CONFIG_SYNC
-#define CONFIG_SYNC_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
+#define CONFIG_SYNC_INT_EVENT TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
 #define CONFIG_TEMP_SENSOR
 #define CONFIG_TEMP_SENSOR_BD99992GW
 #define CONFIG_THERMISTOR_NCP15WB
@@ -121,6 +127,7 @@
 #define CONFIG_CHIPSET_RESET_HOOK
 #define CONFIG_CPU_PROCHOT_ACTIVE_LOW
 #define CONFIG_DPTF
+#define CONFIG_DO_NOT_INCLUDE_RV32I_PANIC_DATA
 #define CONFIG_POWER_COMMON
 #define CONFIG_POWER_BUTTON
 #define CONFIG_POWER_BUTTON_X86
@@ -131,6 +138,7 @@
 
 /* USB PD */
 #define CONFIG_USB_DRP_ACC_TRYSRC
+#define CONFIG_USB_PD_3A_PORTS 0
 #define CONFIG_USB_PD_ALT_MODE
 #define CONFIG_USB_PD_ALT_MODE_DFP
 #define CONFIG_USB_PD_COMM_LOCKED
@@ -161,63 +169,62 @@
 #define CONFIG_USBC_VCONN_SWAP
 
 /* Define typical operating power and max power. */
-#define PD_MAX_VOLTAGE_MV     20000
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_POWER_MW       45000
+#define PD_MAX_VOLTAGE_MV 20000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_POWER_MW 45000
 #define PD_OPERATING_POWER_MW 15000
-#define PD_VCONN_SWAP_DELAY   5000 /* us */
 
 /* TODO(aaboagye): Verify these timings. */
 /*
  * delay to turn on the power supply max is ~16ms.
  * delay to turn off the power supply max is about ~180ms.
  */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY   30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY  250000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* I2C config */
-#define I2C_PORT_CHARGER  I2C_PORT_POWER
-#define I2C_PORT_PMIC     I2C_PORT_POWER
-#define I2C_PORT_POWER    NPCX_I2C_PORT0_0
-#define I2C_PORT_BATTERY  NPCX_I2C_PORT4_1
+#define I2C_PORT_CHARGER I2C_PORT_POWER
+#define I2C_PORT_PMIC I2C_PORT_POWER
+#define I2C_PORT_POWER NPCX_I2C_PORT0_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT4_1
 #define I2C_PORT_ALS_GYRO NPCX_I2C_PORT5_0
-#define I2C_PORT_ACCEL    I2C_PORT_ALS_GYRO
-#define I2C_PORT_USB_C0   NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1   NPCX_I2C_PORT2_0
-#define I2C_PORT_THERMAL  I2C_PORT_PMIC
+#define I2C_PORT_ACCEL I2C_PORT_ALS_GYRO
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0
+#define I2C_PORT_THERMAL I2C_PORT_PMIC
 
 #define GPIO_USB_C0_SCL GPIO_EC_I2C1_USB_C0_SCL
 #define GPIO_USB_C0_SDA GPIO_EC_I2C1_USB_C0_SDA
 #define GPIO_USB_C1_SCL GPIO_EC_I2C2_USB_C1_SCL
 #define GPIO_USB_C1_SDA GPIO_EC_I2C2_USB_C1_SDA
 
-#define I2C_ADDR_MP2949_FLAGS  0x20
+#define I2C_ADDR_MP2949_FLAGS 0x20
 #define I2C_ADDR_BD99992_FLAGS 0x30
 
 /*
  * Remapping of schematic GPIO names to common GPIO names expected (hardcoded)
  * in the EC code base.
  */
-#define GPIO_AC_PRESENT       GPIO_ACOK_OD
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
 #define GPIO_ENABLE_BACKLIGHT GPIO_EC_BL_DISABLE_ODL
-#define GPIO_BAT_PRESENT_L    GPIO_EC_BATT_PRES_L
-#define GPIO_ENTERING_RW      GPIO_EC_ENTERING_RW
-#define GPIO_PCH_PWRBTN_L     GPIO_EC_PCH_PWR_BTN_L
-#define GPIO_PCH_RSMRST_L     GPIO_RSMRST_L
-#define GPIO_PCH_RTCRST       GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L     GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L     GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L     GPIO_SLP_S4_L
-#define GPIO_PCH_SLP_SUS_L    GPIO_SLP_SUS_L_PCH
-#define GPIO_PCH_WAKE_L       GPIO_EC_PCH_WAKE_L
-#define GPIO_PMIC_DPWROK      GPIO_ROP_DSW_PWROK_EC
-#define GPIO_PMIC_SLP_SUS_L   GPIO_SLP_SUS_L_PMIC
-#define GPIO_POWER_BUTTON_L   GPIO_EC_PWR_BTN_IN_ODL
-#define GPIO_CPU_PROCHOT      GPIO_EC_PROCHOT_ODL
-#define GPIO_RSMRST_L_PGOOD   GPIO_ROP_EC_RSMRST_L
-#define GPIO_VOLUME_UP_L      GPIO_H1_EC_VOL_UP_ODL
-#define GPIO_VOLUME_DOWN_L    GPIO_H1_EC_VOL_DOWN_ODL
-#define GPIO_WP_L             GPIO_EC_WP_L
+#define GPIO_BAT_PRESENT_L GPIO_EC_BATT_PRES_L
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_L
+#define GPIO_PCH_RSMRST_L GPIO_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L
+#define GPIO_PCH_SLP_SUS_L GPIO_SLP_SUS_L_PCH
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_L
+#define GPIO_PMIC_DPWROK GPIO_ROP_DSW_PWROK_EC
+#define GPIO_PMIC_SLP_SUS_L GPIO_SLP_SUS_L_PMIC
+#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_IN_ODL
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_PG_EC_RSMRST_ODL GPIO_ROP_EC_RSMRST_L
+#define GPIO_VOLUME_UP_L GPIO_H1_EC_VOL_UP_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_H1_EC_VOL_DOWN_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
 
 #define PORT_TO_HPD(port) ((port) ? GPIO_USB_C1_DP_HPD : GPIO_USB_C0_DP_HPD)
 
@@ -227,19 +234,15 @@
 #include "registers.h"
 
 /* ADC signal */
-enum adc_channel {
-	ADC_BASE_ATTACH,
-	ADC_BASE_DETACH,
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_BASE_ATTACH, ADC_BASE_DETACH, ADC_CH_COUNT };
 
 enum temp_sensor_id {
-	TEMP_SENSOR_BATTERY,	/* BD99956GW TSENSE */
-	TEMP_SENSOR_AMBIENT,	/* BD99992GW SYSTHERM0 */
-	TEMP_SENSOR_CHARGER,	/* BD99992GW SYSTHERM1 */
-	TEMP_SENSOR_DRAM,	/* BD99992GW SYSTHERM2 */
-	TEMP_SENSOR_EMMC,	/* BD99992GW SYSTHERM3 */
-	TEMP_SENSOR_GYRO,	/* BMI160 */
+	TEMP_SENSOR_BATTERY, /* BD99956GW TSENSE */
+	TEMP_SENSOR_AMBIENT, /* BD99992GW SYSTHERM0 */
+	TEMP_SENSOR_CHARGER, /* BD99992GW SYSTHERM1 */
+	TEMP_SENSOR_DRAM, /* BD99992GW SYSTHERM2 */
+	TEMP_SENSOR_EMMC, /* BD99992GW SYSTHERM3 */
+	TEMP_SENSOR_GYRO, /* BMI160 */
 	TEMP_SENSOR_COUNT
 };
 
diff --git a/board/nocturne/build.mk b/board/nocturne/build.mk
index 1c2e1e04f2..3a43716534 100644
--- a/board/nocturne/build.mk
+++ b/board/nocturne/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/nocturne/ec.tasklist b/board/nocturne/ec.tasklist
index 4fb7a035a9..5c7988f1d6 100644
--- a/board/nocturne/ec.tasklist
+++ b/board/nocturne/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nocturne/gpio.inc b/board/nocturne/gpio.inc
index 75d2275424..e820bca8f0 100644
--- a/board/nocturne/gpio.inc
+++ b/board/nocturne/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nocturne/led.c b/board/nocturne/led.c
index a569f5b49f..ba3320cd22 100644
--- a/board/nocturne/led.c
+++ b/board/nocturne/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,39 +18,39 @@ const enum ec_led_id supported_led_ids[] = {
 };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-struct pwm_led led_color_map_v3[EC_LED_COLOR_COUNT] = {
-				/* Red, Green, Blue */
-	[EC_LED_COLOR_RED]    = {  36,   0,   0 },
-	[EC_LED_COLOR_GREEN]  = {   0,  15,   0 },
-	[EC_LED_COLOR_BLUE]   = {   0,   0, 100 },
-	[EC_LED_COLOR_YELLOW] = {  36,  15,   0 },
-	[EC_LED_COLOR_WHITE]  = {  30,   9,  15 },
-	[EC_LED_COLOR_AMBER]  = {  30,   1,   0 },
+struct pwm_led_color_map led_color_map_v3[EC_LED_COLOR_COUNT] = {
+	/* Red, Green, Blue */
+	[EC_LED_COLOR_RED] = { 36, 0, 0 },
+	[EC_LED_COLOR_GREEN] = { 0, 15, 0 },
+	[EC_LED_COLOR_BLUE] = { 0, 0, 100 },
+	[EC_LED_COLOR_YELLOW] = { 36, 15, 0 },
+	[EC_LED_COLOR_WHITE] = { 30, 9, 15 },
+	[EC_LED_COLOR_AMBER] = { 30, 1, 0 },
 };
 
 /* Map for board rev 2 */
-struct pwm_led led_color_map_v2[EC_LED_COLOR_COUNT] = {
-				/* Red, Green, Blue */
-	[EC_LED_COLOR_RED]    = {  62,   0,   0 },
-	[EC_LED_COLOR_GREEN]  = {   0,  31,   0 },
-	[EC_LED_COLOR_BLUE]   = {   0,   0, 100 },
-	[EC_LED_COLOR_YELLOW] = { 100,  54,   0 },
-	[EC_LED_COLOR_WHITE]  = {  70,  54, 100 },
-	[EC_LED_COLOR_AMBER]  = { 100,  15,   0 },
+struct pwm_led_color_map led_color_map_v2[EC_LED_COLOR_COUNT] = {
+	/* Red, Green, Blue */
+	[EC_LED_COLOR_RED] = { 62, 0, 0 },
+	[EC_LED_COLOR_GREEN] = { 0, 31, 0 },
+	[EC_LED_COLOR_BLUE] = { 0, 0, 100 },
+	[EC_LED_COLOR_YELLOW] = { 100, 54, 0 },
+	[EC_LED_COLOR_WHITE] = { 70, 54, 100 },
+	[EC_LED_COLOR_AMBER] = { 100, 15, 0 },
 };
 
 /* Map for board rev 0 and 1 */
-struct pwm_led led_color_map_v0_1[EC_LED_COLOR_COUNT] = {
-				/* Red, Green, Blue */
-	[EC_LED_COLOR_RED]    = {   1,   0,   0 },
-	[EC_LED_COLOR_GREEN]  = {   0,   1,   0 },
-	[EC_LED_COLOR_BLUE]   = {   0,   0,   1 },
-	[EC_LED_COLOR_YELLOW] = {   1,   1,   0 },
-	[EC_LED_COLOR_WHITE]  = {   9,  15,  15 },
-	[EC_LED_COLOR_AMBER]  = {  15,   1,   0 },
+struct pwm_led_color_map led_color_map_v0_1[EC_LED_COLOR_COUNT] = {
+	/* Red, Green, Blue */
+	[EC_LED_COLOR_RED] = { 1, 0, 0 },
+	[EC_LED_COLOR_GREEN] = { 0, 1, 0 },
+	[EC_LED_COLOR_BLUE] = { 0, 0, 1 },
+	[EC_LED_COLOR_YELLOW] = { 1, 1, 0 },
+	[EC_LED_COLOR_WHITE] = { 9, 15, 15 },
+	[EC_LED_COLOR_AMBER] = { 15, 1, 0 },
 };
 
-struct pwm_led led_color_map[EC_LED_COLOR_COUNT] = { { 0 } };
+struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = { { 0 } };
 
 /* Two tri-color LEDs with red, green, and blue channels. */
 struct pwm_led pwm_leds[CONFIG_LED_PWM_COUNT] = {
@@ -112,9 +112,10 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 	return EC_SUCCESS;
 }
 
-static void fill_led_color_map(struct pwm_led map[])
+static void fill_led_color_map(struct pwm_led_color_map map[])
 {
-	memcpy(led_color_map, map, EC_LED_COLOR_COUNT * sizeof(struct pwm_led));
+	memcpy(led_color_map, map,
+	       EC_LED_COLOR_COUNT * sizeof(struct pwm_led_color_map));
 }
 
 static void select_color_map(void)
@@ -134,4 +135,4 @@ static void select_color_map(void)
 		break;
 	}
 }
-DECLARE_HOOK(HOOK_INIT, select_color_map, HOOK_PRIO_INIT_PWM-1);
+DECLARE_HOOK(HOOK_INIT, select_color_map, HOOK_PRIO_INIT_PWM - 1);
diff --git a/board/nocturne/usb_pd_policy.c b/board/nocturne/usb_pd_policy.c
index e2951f291e..26c654d346 100644
--- a/board/nocturne/usb_pd_policy.c
+++ b/board/nocturne/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,8 +6,8 @@
 #include "charge_manager.h"
 #include "chipset.h"
 #include "common.h"
-#include "console.h"
 #include "compile_time_macros.h"
+#include "console.h"
 #include "ec_commands.h"
 #include "gpio.h"
 #include "system.h"
@@ -16,8 +16,8 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
@@ -25,8 +25,7 @@ int pd_check_vconn_swap(int port)
 	return gpio_get_level(GPIO_EN_5V);
 }
 
-__override void pd_execute_data_swap(int port,
-				     enum pd_data_role data_role)
+__override void pd_execute_data_swap(int port, enum pd_data_role data_role)
 {
 	int level;
 
@@ -96,8 +95,8 @@ int pd_set_power_supply_ready(int port)
 __override void svdm_safe_dp_mode(int port)
 {
 	/* make DP interface safe until configure */
-	usb_mux_set(port, USB_PD_MUX_NONE,
-		USB_SWITCH_CONNECT, pd_get_polarity(port));
+	usb_mux_set(port, USB_PD_MUX_NONE, USB_SWITCH_CONNECT,
+		    polarity_rm_dts(pd_get_polarity(port)));
 
 	/*
 	 * Isolate the SBU lines.
diff --git a/board/nocturne/vif_override.xml b/board/nocturne/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/nocturne/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/nocturne_fp/board.c b/board/nocturne_fp/board.c
deleted file mode 100644
index c12003577f..0000000000
--- a/board/nocturne_fp/board.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Meowth Fingerprint MCU configuration */
-
-#include "common.h"
-#include "console.h"
-#include "fpsensor_detect.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "spi.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-
-/**
- * Disable restricted commands when the system is locked.
- *
- * @see console.h system.c
- */
-int console_is_restricted(void)
-{
-	return system_is_locked();
-}
-
-#ifndef HAS_TASK_FPSENSOR
-void fps_event(enum gpio_signal signal)
-{
-}
-#endif
-
-static void ap_deferred(void)
-{
-	/*
-	 * in S3:   SLP_S3_L is 0 and SLP_S0_L is X.
-	 * in S0ix: SLP_S3_L is X and SLP_S0_L is 0.
-	 * in S0:   SLP_S3_L is 1 and SLP_S0_L is 1.
-	 * in S5/G3, the FP MCU should not be running.
-	 */
-	int running = gpio_get_level(GPIO_PCH_SLP_S3_L)
-			&& gpio_get_level(GPIO_PCH_SLP_S0_L);
-
-	if (running) { /* S0 */
-		disable_sleep(SLEEP_MASK_AP_RUN);
-		hook_notify(HOOK_CHIPSET_RESUME);
-	} else { /* S0ix/S3 */
-		hook_notify(HOOK_CHIPSET_SUSPEND);
-		enable_sleep(SLEEP_MASK_AP_RUN);
-	}
-}
-DECLARE_DEFERRED(ap_deferred);
-
-/* PCH power state changes */
-void slp_event(enum gpio_signal signal)
-{
-	hook_call_deferred(&ap_deferred_data, 0);
-}
-
-#include "gpio_list.h"
-
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-	/* Fingerprint sensor (SCLK at 4Mhz) */
-	{ .port = CONFIG_SPI_FP_PORT, .div = 3, .gpio_cs = GPIO_SPI4_NSS }
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-static void spi_configure(void)
-{
-	/* Configure SPI GPIOs */
-	gpio_config_module(MODULE_SPI_MASTER, 1);
-	/* Set all SPI master signal pins to very high speed: pins E2/4/5/6 */
-	STM32_GPIO_OSPEEDR(GPIO_E) |= 0x00003f30;
-	/* Enable clocks to SPI4 module (master) */
-	STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI4;
-
-	spi_enable(CONFIG_SPI_FP_PORT, 1);
-}
-
-/* Initialize board. */
-static void board_init(void)
-{
-	spi_configure();
-
-	ccprints("TRANSPORT_SEL: %s",
-		fp_transport_type_to_str(get_fp_transport_type()));
-
-	/* Enable interrupt on PCH power signals */
-	gpio_enable_interrupt(GPIO_PCH_SLP_S3_L);
-	gpio_enable_interrupt(GPIO_PCH_SLP_S0_L);
-	/* enable the SPI slave interface if the PCH is up */
-	hook_call_deferred(&ap_deferred_data, 0);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/nocturne_fp/board.h b/board/nocturne_fp/board.h
index 1774e8483f..1a34c05ed8 100644
--- a/board/nocturne_fp/board.h
+++ b/board/nocturne_fp/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -51,28 +51,28 @@
 #undef CONFIG_WP_STORAGE_OFF
 #undef CONFIG_WP_STORAGE_SIZE
 
-#define CONFIG_SHAREDLIB_SIZE   0
+#define CONFIG_SHAREDLIB_SIZE 0
 
-#define CONFIG_RO_MEM_OFF       0
-#define CONFIG_RO_STORAGE_OFF   0
-#define CONFIG_RO_SIZE          (768*1024)
+#define CONFIG_RO_MEM_OFF 0
+#define CONFIG_RO_STORAGE_OFF 0
+#define CONFIG_RO_SIZE (768 * 1024)
 
 /* EC rollback protection block */
 #define CONFIG_ROLLBACK_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
 #define CONFIG_ROLLBACK_SIZE (CONFIG_FLASH_BANK_SIZE * 2)
 
-#define CONFIG_RW_MEM_OFF	(CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE)
-#define CONFIG_RW_STORAGE_OFF	0
-#define CONFIG_RW_SIZE		(CONFIG_FLASH_SIZE -			\
-				(CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF))
+#define CONFIG_RW_MEM_OFF (CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE)
+#define CONFIG_RW_STORAGE_OFF 0
+#define CONFIG_RW_SIZE \
+	(CONFIG_FLASH_SIZE_BYTES - (CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF))
 
-#define CONFIG_EC_PROTECTED_STORAGE_OFF         CONFIG_RO_MEM_OFF
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE        CONFIG_RO_SIZE
-#define CONFIG_EC_WRITABLE_STORAGE_OFF          CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE         CONFIG_RW_SIZE
+#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF
+#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE
+#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE
 
-#define CONFIG_WP_STORAGE_OFF           CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE          CONFIG_EC_PROTECTED_STORAGE_SIZE
+#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
+#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
 
 /*
  * We want to prevent flash readout, and use it as indicator of protection
@@ -91,30 +91,73 @@
 /* Optional features */
 #undef CONFIG_ADC
 #define CONFIG_CMD_IDLE_STATS
-#define CONFIG_DMA
+#define CONFIG_DMA_CROS
 #define CONFIG_FORCE_CONSOLE_RESUME
 #define CONFIG_FPU
+/*
+ * Don't enable FPU warnings on STM32H7, because FPU interrupt is not triggered
+ * (see, errata ES0392 Rev 8, 2.1.2 Cortex-M7 FPU interrupt not present on NVIC
+ * line 81).
+ */
+#undef CONFIG_FPU_WARNINGS
 #undef CONFIG_HIBERNATE
 #define CONFIG_HOST_COMMAND_STATUS
 #undef CONFIG_I2C
 #undef CONFIG_LID_SWITCH
-#define CONFIG_LOW_POWER_IDLE
 #define CONFIG_MKBP_EVENT
 #define CONFIG_MKBP_USE_GPIO
-#define CONFIG_PRINTF_LEGACY_LI_FORMAT
+#define CONFIG_PRINTF_LONG_IS_32BITS
 #define CONFIG_SHA256
 #define CONFIG_SHA256_UNROLLED
 #define CONFIG_SPI
-#define CONFIG_STM_HWTIMER32
-#define CONFIG_SUPPRESSED_HOST_COMMANDS \
-	EC_CMD_CONSOLE_SNAPSHOT, EC_CMD_CONSOLE_READ, EC_CMD_PD_GET_LOG_ENTRY
 #undef CONFIG_TASK_PROFILING
 #define CONFIG_WATCHDOG_HELP
 #define CONFIG_WP_ACTIVE_HIGH
+#define CONFIG_PANIC_STRIP_GPR
+
+#if defined(BOARD_NOCTURNE_FP) || defined(BOARD_NAMI_FP)
+/*
+ * FPMCU RO for nocturne (nocturne_fp_v2.2.64-58cf5974e) and
+ * FPMCU RO for nami (nami_fp_v2.2.144-7a08e07eb)
+ * don't have the RV32I core panic data in their panic data structure.
+ * As a consequence the size of panic data structure is different between RO
+ * and RW (RO panic data structure is smaller). This results in overwriting RW
+ * panic data (if it exists) by RO when jumping to RW. Another problem is that
+ * RW can't find the jump data, because owerwritten panic data structure created
+ * by RW still contains RW panic data structure size (bigger than RO's), so
+ * calculated jump data address is wrong.
+ *
+ * The problem is fixed by excluding RV32I core panic data from RW, only when
+ * compiling firmware for nami_fp and nocturne_fp. Expected size of the
+ * structure is 116 bytes.
+ */
+#define CONFIG_DO_NOT_INCLUDE_RV32I_PANIC_DATA
+#define CONFIG_RO_PANIC_DATA_SIZE 116
+
+/*
+ * FPMCU RO for nocturne and nami don't support extended reset flags in backup
+ * RAM. RO interprets the register as saved panic reason, so it tries to restore
+ * panic data when value in the register is different than 0. Another problem is
+ * that panic data saved in backup RAM on hard reset is restored incorrectly.
+ *
+ * CL:1295890 is the change which introduced extended reset flags.
+ */
+#undef CONFIG_STM32_EXTENDED_RESET_FLAGS
+#else
+/*
+ * Dartmonkey FPMCU RO (dartmonkey_v2.0.2887-311310808) has RV32I core panic
+ * data structure in their panic data structure, so expected size of the
+ * structure is 144 bytes.
+ */
+#define CONFIG_RO_PANIC_DATA_SIZE 144
+#endif /* defined(BOARD_NOCTURNE_FP) || defined(BOARD_NAMI_FP) */
 
 /* SPI configuration for the fingerprint sensor */
-#define CONFIG_SPI_MASTER
-#define CONFIG_SPI_FP_PORT  2 /* SPI4: third master config */
+#define CONFIG_SPI_CONTROLLER
+#define CONFIG_SPI_FP_PORT 2 /* SPI4: third master config */
+#define CONFIG_SPI_MUTABLE_DEVICE_LIST
+
+#define CONFIG_FINGERPRINT_MCU
 #ifdef SECTION_IS_RW
 #define CONFIG_FP_SENSOR_FPC1145
 #define CONFIG_CMD_FPSENSOR_DEBUG
@@ -125,7 +168,7 @@
  */
 #define CONFIG_MALLOC
 /* Special memory regions to store large arrays */
-#define FP_FRAME_SECTION    __SECTION(ahb4)
+#define FP_FRAME_SECTION __SECTION(ahb4)
 #define FP_TEMPLATE_SECTION __SECTION(ahb)
 
 #else /* SECTION_IS_RO */
@@ -159,13 +202,16 @@
 #undef CONFIG_ROLLBACK_UPDATE
 #endif
 
-#define CONFIG_AES
-#define CONFIG_AES_GCM
+#define CONFIG_BORINGSSL_CRYPTO
 
 #define CONFIG_RNG
 
 #define CONFIG_CMD_FLASH
+
+#ifdef SECTION_IS_RW
+#define CONFIG_LOW_POWER_IDLE
 #define CONFIG_CMD_SPI_XFER
+#endif
 
 #ifdef SECTION_IS_RW
 /*
@@ -180,12 +226,10 @@
 #define TIM_CLOCK32 2
 #define TIM_WATCHDOG 16
 
+#include "board_rw.h"
 #include "gpio_signal.h"
 
-void fps_event(enum gpio_signal signal);
-
-/* Defined in ro_workarounds.c */
-void wp_event(enum gpio_signal signal);
+void slp_event(enum gpio_signal signal);
 
 #endif /* !__ASSEMBLER__ */
 
diff --git a/board/nocturne_fp/board_ro.c b/board/nocturne_fp/board_ro.c
new file mode 100644
index 0000000000..7350e5bded
--- /dev/null
+++ b/board/nocturne_fp/board_ro.c
@@ -0,0 +1,77 @@
+/* Copyright 2017 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* Meowth Fingerprint MCU configuration */
+
+#include "common.h"
+#include "hooks.h"
+#include "registers.h"
+#include "spi.h"
+#include "system.h"
+#include "task.h"
+
+#ifndef SECTION_IS_RO
+#error "This file should only be built for RO."
+#endif
+
+/**
+ * Disable restricted commands when the system is locked.
+ *
+ * @see console.h system.c
+ */
+int console_is_restricted(void)
+{
+	return system_is_locked();
+}
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+static void ap_deferred(void)
+{
+	/*
+	 * Behavior:
+	 * AP Active  (ex. Intel S0):   SLP_L is 1
+	 * AP Suspend (ex. Intel S0ix): SLP_L is 0
+	 * The alternative SLP_ALT_L should be pulled high at all the times.
+	 *
+	 * Legacy Intel behavior:
+	 * in S3:   SLP_ALT_L is 0 and SLP_L is X.
+	 * in S0ix: SLP_ALT_L is X and SLP_L is 0.
+	 * in S0:   SLP_ALT_L is 1 and SLP_L is 1.
+	 * in S5/G3, the FP MCU should not be running.
+	 */
+	int running = gpio_get_level(GPIO_SLP_ALT_L) &&
+		      gpio_get_level(GPIO_SLP_L);
+
+	if (running) { /* AP is S0 */
+		disable_sleep(SLEEP_MASK_AP_RUN);
+		hook_notify(HOOK_CHIPSET_RESUME);
+	} else { /* AP is suspend/S0ix/S3 */
+		hook_notify(HOOK_CHIPSET_SUSPEND);
+		enable_sleep(SLEEP_MASK_AP_RUN);
+	}
+}
+DECLARE_DEFERRED(ap_deferred);
+
+/* PCH power state changes */
+void slp_event(enum gpio_signal signal)
+{
+	hook_call_deferred(&ap_deferred_data, 0);
+}
+
+void board_init(void)
+{
+	/* Enable interrupt on PCH power signals */
+	gpio_enable_interrupt(GPIO_SLP_ALT_L);
+	gpio_enable_interrupt(GPIO_SLP_L);
+
+	/*
+	 * Enable the SPI slave interface if the PCH is up.
+	 * Do not use hook_call_deferred(), because ap_deferred() will be
+	 * called after tasks with priority higher than HOOK task (very late).
+	 */
+	ap_deferred();
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/nocturne_fp/board_rw.c b/board/nocturne_fp/board_rw.c
new file mode 100644
index 0000000000..c8bc225aa7
--- /dev/null
+++ b/board/nocturne_fp/board_rw.c
@@ -0,0 +1,137 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "board_rw.h"
+#include "common.h"
+#include "console.h"
+#include "fpsensor_detect.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "registers.h"
+#include "spi.h"
+#include "system.h"
+#include "task.h"
+#include "util.h"
+
+#ifndef SECTION_IS_RW
+#error "This file should only be built for RW."
+#endif
+
+/**
+ * Disable restricted commands when the system is locked.
+ *
+ * @see console.h system.c
+ */
+int console_is_restricted(void)
+{
+	return system_is_locked();
+}
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* SPI devices */
+struct spi_device_t spi_devices[] = {
+	/* Fingerprint sensor (SCLK at 4Mhz) */
+	{ .port = CONFIG_SPI_FP_PORT, .div = 3, .gpio_cs = GPIO_SPI4_NSS }
+};
+const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
+
+/* Allow changing the signal used for alt sleep depending on the board being
+ * used: http://b/179946521.
+ */
+static int gpio_slp_alt_l = GPIO_SLP_ALT_L;
+
+static void ap_deferred(void)
+{
+	/*
+	 * Behavior:
+	 * AP Active  (ex. Intel S0):   SLP_L is 1
+	 * AP Suspend (ex. Intel S0ix): SLP_L is 0
+	 * The alternative SLP_ALT_L should be pulled high at all the times.
+	 *
+	 * Legacy Intel behavior:
+	 * in S3:   SLP_ALT_L is 0 and SLP_L is X.
+	 * in S0ix: SLP_ALT_L is X and SLP_L is 0.
+	 * in S0:   SLP_ALT_L is 1 and SLP_L is 1.
+	 * in S5/G3, the FP MCU should not be running.
+	 */
+	int running = gpio_get_level(gpio_slp_alt_l) &&
+		      gpio_get_level(GPIO_SLP_L);
+
+	if (running) { /* AP is S0 */
+		disable_sleep(SLEEP_MASK_AP_RUN);
+		hook_notify(HOOK_CHIPSET_RESUME);
+	} else { /* AP is suspend/S0ix/S3 */
+		hook_notify(HOOK_CHIPSET_SUSPEND);
+		enable_sleep(SLEEP_MASK_AP_RUN);
+	}
+}
+DECLARE_DEFERRED(ap_deferred);
+
+/* PCH power state changes */
+void slp_event(enum gpio_signal signal)
+{
+	hook_call_deferred(&ap_deferred_data, 0);
+}
+
+static void spi_configure(enum fp_sensor_spi_select spi_select)
+{
+	if (spi_select == FP_SENSOR_SPI_SELECT_DEVELOPMENT) {
+		/* SPI4 master to sensor: PE12/13/14 (CLK/MISO/MOSI) */
+		gpio_set_flags_by_mask(GPIO_E, 0x7000, 0);
+		gpio_set_alternate_function(GPIO_E, 0x7000, GPIO_ALT_SPI);
+	} else {
+		gpio_config_module(MODULE_SPI_CONTROLLER, 1);
+	}
+
+	/* Set all SPI controller signal pins to very high speed:
+	 * pins E2/4/5/6
+	 */
+	STM32_GPIO_OSPEEDR(GPIO_E) |= 0x00003f30;
+	/* Enable clocks to SPI4 module (master) */
+	STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI4;
+
+	if (spi_select == FP_SENSOR_SPI_SELECT_DEVELOPMENT)
+		spi_devices[0].gpio_cs = GPIO_SPI4_ALT_NSS;
+	spi_enable(&spi_devices[0], 1);
+}
+
+void board_init(void)
+{
+	enum fp_sensor_spi_select spi_select = fpsensor_detect_get_spi_select();
+
+	/*
+	 * FP_RST_ODL pin is defined in gpio_rw.inc (with GPIO_OUT_HIGH
+	 * flag) but not in gpio.inc, so RO leaves this pin set to 0 (reset
+	 * default), but RW doesn't initialize this pin to 1 because sysjump
+	 * to RW is a warm reset (see gpio_pre_init() in chip/stm32/gpio.c).
+	 * Explicitly reset FP_RST_ODL pin to default value.
+	 */
+	gpio_reset(GPIO_FP_RST_ODL);
+
+	ccprints("FP_SPI_SEL: %s", fp_sensor_spi_select_to_str(spi_select));
+
+	spi_configure(spi_select);
+
+	ccprints("TRANSPORT_SEL: %s",
+		 fp_transport_type_to_str(get_fp_transport_type()));
+
+	/* Use SPI select as a proxy for running on the icetower dev board. */
+	if (spi_select == FP_SENSOR_SPI_SELECT_DEVELOPMENT)
+		gpio_slp_alt_l = GPIO_SLP_ALT_DEV_L;
+
+	/* Enable interrupt on PCH power signals */
+	gpio_enable_interrupt(gpio_slp_alt_l);
+	gpio_enable_interrupt(GPIO_SLP_L);
+
+	/*
+	 * Enable the SPI peripheral interface if the PCH is up.
+	 * Do not use hook_call_deferred(), because ap_deferred() will be
+	 * called after tasks with priority higher than HOOK task (very late).
+	 */
+	ap_deferred();
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/nocturne_fp/board_rw.h b/board/nocturne_fp/board_rw.h
new file mode 100644
index 0000000000..ebb0892829
--- /dev/null
+++ b/board/nocturne_fp/board_rw.h
@@ -0,0 +1,17 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_BOARD_NOCTURNE_FP_BOARD_RW_H
+#define __CROS_EC_BOARD_NOCTURNE_FP_BOARD_RW_H
+
+#include "config.h"
+#include "gpio_signal.h"
+
+void fps_event(enum gpio_signal signal);
+
+/* Defined in ro_workarounds.c */
+void wp_event(enum gpio_signal signal);
+
+#endif /* __CROS_EC_BOARD_NOCTURNE_FP_BOARD_RW_H */
diff --git a/board/nocturne_fp/build.mk b/board/nocturne_fp/build.mk
index fca1dc62e3..9116581442 100644
--- a/board/nocturne_fp/build.mk
+++ b/board/nocturne_fp/build.mk
@@ -1,4 +1,4 @@
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -9,25 +9,70 @@ CHIP:=stm32
 CHIP_FAMILY:=stm32h7
 CHIP_VARIANT:=stm32h7x3
 
-board-rw=ro_workarounds.o
-board-y=board.o fpsensor_detect.o
+# Don't forget that the board build.mk is included more than once to allow
+# conditional variables to be realized. This means that we need to redefine all
+# variable or the "+=" lines will compound.
+board-y=
+board-rw=ro_workarounds.o board_rw.o
+board-ro=board_ro.o
+# If we're mocking the sensor detection for testing (so we can test
+# sensor/transport permutations in the unit tests), don't build the real sensor
+# detection.
+ifeq ($(HAS_MOCK_FPSENSOR_DETECT),)
+	board-rw+=fpsensor_detect_rw.o
+	board-y+=fpsensor_detect.o
+endif
 
+# Do not build rsa test because this board uses RSA exponent 3 and the rsa test
+# will fail on device.
 test-list-y=\
+       abort \
        aes \
+       always_memset \
+       benchmark \
+       boringssl_crypto \
        compile_time_macros \
-       crc32 \
+       cortexm_fpu \
+       crc \
+       debug \
+       exception \
        flash_physical \
        flash_write_protect \
+       fpsensor \
+       fpsensor_auth_crypto_stateful \
+       fpsensor_auth_crypto_stateless \
+       fpsensor_hw \
+       ftrapv \
+       global_initialization \
+       libc_printf \
+       libcxx \
+       malloc \
        mpu \
        mutex \
+       panic \
+       panic_data \
        pingpong \
+       printf \
+       queue \
+       rng_benchmark \
        rollback \
        rollback_entropy \
-       rsa \
        rsa3 \
        rtc \
+       sbrk \
        scratchpad \
        sha256 \
        sha256_unrolled \
-       stm32f_rtc \
+       static_if \
+       stdlib \
+       std_vector \
+       system_is_locked \
+       timer \
+       timer_dos \
+       tpm_seed_clear \
        utils \
+       utils_str \
+
+# Note that this variable includes the trailing "/"
+_nocturne_fp_cur_dir:=$(dir $(lastword $(MAKEFILE_LIST)))
+-include $(_nocturne_fp_cur_dir)../../private/board/nocturne_fp/build.mk
diff --git a/board/nocturne_fp/ec.tasklist b/board/nocturne_fp/ec.tasklist
index ed1e6ed294..79b8531751 100644
--- a/board/nocturne_fp/ec.tasklist
+++ b/board/nocturne_fp/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,5 +10,5 @@
 	TASK_ALWAYS_RO(RWSIG, rwsig_task, NULL, 1280) \
 	TASK_ALWAYS(HOOKS, hook_task, NULL, 1024) \
 	TASK_ALWAYS_RW(FPSENSOR, fp_task, NULL, 4096) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 4096) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 6144) \
 	TASK_ALWAYS(CONSOLE, console_task, NULL, CONSOLE_TASK_STACK_SIZE)
diff --git a/board/nocturne_fp/fpsensor_detect.c b/board/nocturne_fp/fpsensor_detect.c
index 72b9b89e11..2541aa3c68 100644
--- a/board/nocturne_fp/fpsensor_detect.c
+++ b/board/nocturne_fp/fpsensor_detect.c
@@ -1,15 +1,10 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "fpsensor_detect.h"
 
-enum fp_sensor_type get_fp_sensor_type(void)
-{
-	return FP_SENSOR_TYPE_FPC;
-}
-
 enum fp_transport_type get_fp_transport_type(void)
 {
 	return FP_TRANSPORT_TYPE_SPI;
diff --git a/board/nocturne_fp/fpsensor_detect_rw.c b/board/nocturne_fp/fpsensor_detect_rw.c
new file mode 100644
index 0000000000..adc2690998
--- /dev/null
+++ b/board/nocturne_fp/fpsensor_detect_rw.c
@@ -0,0 +1,34 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "fpsensor_detect.h"
+#include "gpio.h"
+#include "timer.h"
+
+enum fp_sensor_type fpsensor_detect_get_type(void)
+{
+	return FP_SENSOR_TYPE_FPC;
+}
+
+enum fp_sensor_spi_select fpsensor_detect_get_spi_select(void)
+{
+	enum fp_sensor_spi_select ret;
+
+	gpio_set_level(GPIO_DIVIDER_HIGHSIDE, 1);
+	usleep(1);
+	switch (gpio_get_level(GPIO_FP_SPI_SEL)) {
+	case 0:
+		ret = FP_SENSOR_SPI_SELECT_DEVELOPMENT;
+		break;
+	case 1:
+		ret = FP_SENSOR_SPI_SELECT_PRODUCTION;
+		break;
+	default:
+		ret = FP_SENSOR_SPI_SELECT_UNKNOWN;
+		break;
+	}
+	gpio_set_level(GPIO_DIVIDER_HIGHSIDE, 0);
+	return ret;
+}
diff --git a/board/nocturne_fp/gpio.inc b/board/nocturne_fp/gpio.inc
index 48a15209ba..b0e1c3a80b 100644
--- a/board/nocturne_fp/gpio.inc
+++ b/board/nocturne_fp/gpio.inc
@@ -1,29 +1,21 @@
 /*
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Interrupts */
-GPIO_INT(FPS_INT,         PIN(A, 0), GPIO_INT_RISING, fps_event)
+GPIO_INT(SLP_L,           PIN(D,13), GPIO_INT_BOTH, slp_event)
+GPIO_INT(SLP_ALT_L,       PIN(A,11), GPIO_INT_BOTH, slp_event)
 GPIO_INT(SPI1_NSS,        PIN(A, 4), GPIO_INPUT, spi_event)
 
-GPIO_INT(PCH_SLP_S0_L,    PIN(D,13), GPIO_INT_BOTH, slp_event)
-GPIO_INT(PCH_SLP_S3_L,    PIN(A,11), GPIO_INT_BOTH, slp_event)
-
-GPIO(PCH_SLP_S4_L,        PIN(D, 8), GPIO_INPUT)
-GPIO(PCH_SLP_SUS_L,       PIN(D, 3), GPIO_INPUT)
-#if defined(APPLY_RESET_LOOP_FIX) && defined(SECTION_IS_RW)
-GPIO_INT(WP,              PIN(B, 7), GPIO_INT_BOTH, wp_event)
-#else
+/* Inputs */
+#ifndef APPLY_RESET_LOOP_FIX
 GPIO(WP,                  PIN(B, 7), GPIO_INPUT)
 #endif
 
 /* Outputs */
 GPIO(EC_INT_L,            PIN(A, 1),  GPIO_OUT_HIGH)
-GPIO(FP_RST_ODL,          PIN(E, 0),  GPIO_OUT_HIGH)
-GPIO(SPI4_NSS,            PIN(E, 4),  GPIO_OUT_HIGH)
-GPIO(USER_PRES_L,         PIN(C, 5),  GPIO_ODR_HIGH)
 
 UNIMPLEMENTED(ENTERING_RW)
 
@@ -31,5 +23,7 @@ UNIMPLEMENTED(ENTERING_RW)
 ALTERNATE(PIN_MASK(A, 0x0600), GPIO_ALT_USART,  MODULE_UART, GPIO_PULL_UP)
 /* SPI1 slave from the AP: PA4/5/6/7 (CS/CLK/MISO/MOSI) */
 ALTERNATE(PIN_MASK(A, 0x00f0), GPIO_ALT_SPI, MODULE_SPI,  0)
-/* SPI4 master to sensor: PE2/5/6 (CLK/MISO/MOSI) */
-ALTERNATE(PIN_MASK(E, 0x0064), GPIO_ALT_SPI, MODULE_SPI_MASTER,  0)
+
+#ifdef SECTION_IS_RW
+#include "gpio_rw.inc"
+#endif
diff --git a/board/nocturne_fp/gpio_rw.inc b/board/nocturne_fp/gpio_rw.inc
new file mode 100644
index 0000000000..9ee3af139f
--- /dev/null
+++ b/board/nocturne_fp/gpio_rw.inc
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef SECTION_IS_RW
+#error "This file should only be included in RW."
+#endif
+
+/* Interrupts */
+GPIO_INT(FPS_INT,         PIN(A, 0), GPIO_INT_RISING, fps_event)
+
+#ifdef APPLY_RESET_LOOP_FIX
+GPIO_INT(WP,              PIN(B, 7), GPIO_INT_BOTH, wp_event)
+#endif
+
+/* Inputs */
+GPIO_INT(SLP_ALT_DEV_L,   PIN(D,14), GPIO_INT_BOTH, slp_event)
+/*
+ * The S4 and SUS sleep lines are unused in code, but are maintained in this
+ * gpio list to ensure that they are not repurposed. This is because these
+ * inputs are driven on nocturne.
+ */
+GPIO(PCH_SLP_S4_L,        PIN(D, 8), GPIO_INPUT)
+GPIO(PCH_SLP_SUS_L,       PIN(D, 3), GPIO_INPUT)
+/* TODO(b/178808871): Only enable pull up when doing detection. */
+GPIO(FP_SPI_SEL,          PIN(E, 1), GPIO_INPUT | GPIO_PULL_UP)
+
+/* Outputs */
+GPIO(DIVIDER_HIGHSIDE,    PIN(B, 8),  GPIO_OUT_LOW)
+GPIO(FP_RST_ODL,          PIN(E, 0),  GPIO_OUT_HIGH)
+GPIO(SPI4_NSS,            PIN(E, 4),  GPIO_OUT_HIGH)
+GPIO(SPI4_ALT_NSS,        PIN(E, 11), GPIO_OUT_HIGH)
+GPIO(USER_PRES_L,         PIN(C, 5),  GPIO_ODR_HIGH)
+
+/* Default SPI4 master to sensor: PE2/5/6 (CLK/MISO/MOSI) */
+ALTERNATE(PIN_MASK(E, 0x0064), GPIO_ALT_SPI, MODULE_SPI_CONTROLLER,  0)
+
+/* See board_rw.c for the alternate configuration that we use on
+ * development boards, which overrides the UNUSED values below.
+ */
+UNUSED(PIN(E, 12))  /* Alternate SPI4 master to sensor CLK */
+UNUSED(PIN(E, 13))  /* Alternate SPI4 master to sensor MISO */
+UNUSED(PIN(E, 14))  /* Alternate SPI4 master to sensor MOSI */
diff --git a/board/nocturne_fp/ro_workarounds.c b/board/nocturne_fp/ro_workarounds.c
index 333f1ed9da..92f7dacd28 100644
--- a/board/nocturne_fp/ro_workarounds.c
+++ b/board/nocturne_fp/ro_workarounds.c
@@ -1,13 +1,10 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* A place to organize workarounds for legacy RO */
 
-#include <assert.h>
-#include <stdbool.h>
-
 #include "bkpdata.h"
 #include "common.h"
 #include "console.h"
@@ -18,8 +15,11 @@
 #include "task.h"
 #include "watchdog.h"
 
+#include <assert.h>
+#include <stdbool.h>
+
 /* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 /*
  * We only patch RW to ensure that future ROs have correct behavior.
@@ -30,7 +30,7 @@
  * Add in ap-off flag to be able to detect on next boot.
  * No other code in this build uses this ap-off reset flag.
  */
-#define FORGE_PORFLAG_FLAGS (EC_RESET_FLAG_POWER_ON|EC_RESET_FLAG_AP_OFF)
+#define FORGE_PORFLAG_FLAGS (EC_RESET_FLAG_POWER_ON | EC_RESET_FLAG_AP_OFF)
 
 static void wp_change_deferred(void)
 {
@@ -75,20 +75,15 @@ void wp_event(enum gpio_signal signal)
  * This function is also called from system_reset to set the final save
  * reset flags, before an actual planned reset.
  */
-__override
-void bkpdata_write_reset_flags(uint32_t save_flags)
+__override void bkpdata_write_reset_flags(uint32_t save_flags)
 {
 	/* Preserve flags in case a reset pulse occurs */
 	if (!gpio_get_level(GPIO_WP))
 		save_flags |= FORGE_PORFLAG_FLAGS;
 
-#ifdef CONFIG_STM32_RESET_FLAGS_EXTENDED
 	bkpdata_write(BKPDATA_INDEX_SAVED_RESET_FLAGS, save_flags & 0xffff);
+#ifdef CONFIG_STM32_EXTENDED_RESET_FLAGS
 	bkpdata_write(BKPDATA_INDEX_SAVED_RESET_FLAGS_2, save_flags >> 16);
-#else
-	/* Reset flags are 32-bits, but BBRAM entry is only 16 bits. */
-	ASSERT(!(save_flags >> 16));
-	bkpdata_write(BKPDATA_INDEX_SAVED_RESET_FLAGS, save_flags);
 #endif
 }
 
diff --git a/board/npcx7_evb/board.c b/board/npcx7_evb/board.c
index 5fa421d917..250f963b88 100644
--- a/board/npcx7_evb/board.c
+++ b/board/npcx7_evb/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,6 @@
 /* Nuvoton M4 EB board-specific configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "backlight.h"
 #include "chipset.h"
 #include "common.h"
@@ -28,27 +27,33 @@
 #include "switch.h"
 #include "temp_sensor.h"
 #include "temp_sensor_chip.h"
-#include "timer.h"
 #include "thermal.h"
+#include "timer.h"
 #include "util.h"
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /******************************************************************************/
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
-	[ADC_CH_0] = {"ADC0", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_1] = {"ADC1", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_2] = {"ADC2", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_3] = {"ADC3", NPCX_ADC_CH3, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_4] = {"ADC4", NPCX_ADC_CH4, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_CH_0] = { "ADC0", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+		       0 },
+	[ADC_CH_1] = { "ADC1", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+		       0 },
+	[ADC_CH_2] = { "ADC2", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+		       0 },
+	[ADC_CH_3] = { "ADC3", NPCX_ADC_CH3, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+		       0 },
+	[ADC_CH_4] = { "ADC4", NPCX_ADC_CH4, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+		       0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /******************************************************************************/
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN] = { 0, PWM_CONFIG_OPEN_DRAIN, 25000},
+	[PWM_CH_FAN] = { 0, PWM_CONFIG_OPEN_DRAIN, 25000 },
 	[PWM_CH_KBLIGHT] = { 2, 0, 10000 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
@@ -57,7 +62,7 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 /* Physical fans. These are logically separate from pwm_channels. */
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = 0,	/* Use MFT id to control fan */
+	.ch = 0, /* Use MFT id to control fan */
 	.pgood_gpio = GPIO_PGOOD_FAN,
 	.enable_gpio = -1,
 };
@@ -76,25 +81,45 @@ BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
 /******************************************************************************/
 /* MFT channels. These are logically separate from pwm_channels. */
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN },
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 /******************************************************************************/
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{"master0-0", NPCX_I2C_PORT0_0, 100, GPIO_I2C0_SCL0, GPIO_I2C0_SDA0},
-	{"master1-0", NPCX_I2C_PORT1_0, 100, GPIO_I2C1_SCL0, GPIO_I2C1_SDA0},
-	{"master2-0", NPCX_I2C_PORT2_0, 100, GPIO_I2C2_SCL0, GPIO_I2C2_SDA0},
-	{"master3-0", NPCX_I2C_PORT3_0, 100, GPIO_I2C3_SCL0, GPIO_I2C3_SDA0},
-	{"master7-0", NPCX_I2C_PORT7_0, 100, GPIO_I2C7_SCL0, GPIO_I2C7_SDA0},
+	{ .name = "master0-0",
+	  .port = NPCX_I2C_PORT0_0,
+	  .kbps = 100,
+	  .scl = GPIO_I2C0_SCL0,
+	  .sda = GPIO_I2C0_SDA0 },
+	{ .name = "master1-0",
+	  .port = NPCX_I2C_PORT1_0,
+	  .kbps = 100,
+	  .scl = GPIO_I2C1_SCL0,
+	  .sda = GPIO_I2C1_SDA0 },
+	{ .name = "master2-0",
+	  .port = NPCX_I2C_PORT2_0,
+	  .kbps = 100,
+	  .scl = GPIO_I2C2_SCL0,
+	  .sda = GPIO_I2C2_SDA0 },
+	{ .name = "master3-0",
+	  .port = NPCX_I2C_PORT3_0,
+	  .kbps = 100,
+	  .scl = GPIO_I2C3_SCL0,
+	  .sda = GPIO_I2C3_SDA0 },
+	{ .name = "master7-0",
+	  .port = NPCX_I2C_PORT7_0,
+	  .kbps = 100,
+	  .scl = GPIO_I2C7_SCL0,
+	  .sda = GPIO_I2C7_SDA0 },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
 /******************************************************************************/
 /* SPI devices */
 const struct spi_device_t spi_devices[] = {
-	{ CONFIG_SPI_FLASH_PORT, 0, GPIO_SPI_CS_L},
+	{ CONFIG_SPI_FLASH_PORT, 0, GPIO_SPI_CS_L },
 };
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
@@ -109,7 +134,7 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 
 /******************************************************************************/
 /* Keyboard scan setting */
-struct keyboard_scan_config keyscan_config = {
+__override struct keyboard_scan_config keyscan_config = {
 	.output_settle_us = 40,
 	.debounce_down_us = 6 * MSEC,
 	.debounce_up_us = 30 * MSEC,
diff --git a/board/npcx7_evb/board.h b/board/npcx7_evb/board.h
index 6d36f901b0..ae3392ab16 100644
--- a/board/npcx7_evb/board.h
+++ b/board/npcx7_evb/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,11 +15,11 @@
  *     npcx7m6f/npcx7m6fb/npcx7m6fc/npcx7m7fc/npcx7m7wb/npcx7m7wc
  */
 #if defined(CHIP_VARIANT_NPCX7M6G)
-#define BOARD_VERSION  1
-#elif defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \
+#define BOARD_VERSION 1
+#elif defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) ||    \
 	defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M7FC) || \
 	defined(CHIP_VARIANT_NPCX7M7WB) || defined(CHIP_VARIANT_NPCX7M7WC)
-#define BOARD_VERSION  2
+#define BOARD_VERSION 2
 #endif
 
 /* EC modules */
@@ -28,27 +28,26 @@
 #define CONFIG_SPI
 #define CONFIG_I2C
 /* Features of eSPI */
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#define CONFIG_HOST_INTERFACE_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 
 /* Optional features */
 #define CONFIG_ENABLE_JTAG_SELECTION
 #define CONFIG_BOARD_VERSION_GPIO
 #define CONFIG_EXTPOWER_GPIO
-#define CONFIG_I2C_MASTER
-#define CONFIG_KEYBOARD_BOARD_CONFIG
+#define CONFIG_I2C_CONTROLLER
+
 #define CONFIG_KEYBOARD_PROTOCOL_8042
-#undef  CONFIG_LOW_POWER_IDLE /* Deep Sleep Support */
+#undef CONFIG_LOW_POWER_IDLE /* Deep Sleep Support */
 #define CONFIG_POWER_BUTTON
-#undef  CONFIG_PSTORE
+#undef CONFIG_PSTORE
 #define CONFIG_PWM_KBLIGHT
 #define CONFIG_VBOOT_HASH
 #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands */
 
 /* EC console commands */
 #define CONFIG_CMD_TASKREADY
-#define CONFIG_CMD_STACKOVERFLOW
 #define CONFIG_CMD_JUMPTAGS
 #define CONFIG_CMD_FLASH
 #define CONFIG_CMD_SPI_FLASH
@@ -57,7 +56,7 @@
 
 /* I2C port for CONFIG_CMD_I2CWEDGE */
 #define I2C_PORT_MASTER NPCX_I2C_PORT0_0
-#define I2C_PORT_HOST   0
+#define I2C_PORT_HOST 0
 
 /* Fans for testing */
 #define CONFIG_FANS 1
@@ -69,10 +68,10 @@
 #if defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M7FC) || \
 	defined(CHIP_VARIANT_NPCX7M7WC)
 #define CONFIG_SPI_FLASH_W25Q40 /* Internal spi flash type */
-#define CONFIG_FLASH_SIZE 0x00080000 /* 512 KB internal spi flash */
+#define CONFIG_FLASH_SIZE_BYTES 0x00080000 /* 512 KB internal spi flash */
 #else
 #define CONFIG_SPI_FLASH_W25Q80 /* Internal spi flash type */
-#define CONFIG_FLASH_SIZE 0x00100000 /* 1 MB internal spi flash */
+#define CONFIG_FLASH_SIZE_BYTES 0x00100000 /* 1 MB internal spi flash */
 #endif
 
 /* New features on npcx7 ec */
@@ -86,7 +85,6 @@
 #define CONFIG_AUDIO_CODEC_I2S_RX /* Use Audio front-end for Wake-on-Voice */
 #endif
 #undef CONFIG_FANS /* Remove fan application */
-#define CONFIG_FANS 0
 #else
 #undef CONFIG_HIBERNATE_PSL /* Use PSL (Power Switch Logic) for hibernate */
 #undef CONFIG_CLOCK_SRC_EXTERNAL /* Use external 32kHz OSC as LFCLK source */
@@ -96,20 +94,20 @@
 
 /* Select which UART Controller is the Console UART */
 #undef CONFIG_CONSOLE_UART
-#define CONFIG_CONSOLE_UART    0 /* 0:UART1 1:UART2 */
+#define CONFIG_CONSOLE_UART 0 /* 0:UART1 1:UART2 */
 /*
  * This definition below actually doesn't define which UART controller to be
  * used. Instead, it defines which pinouts (GPIO10/11 or GPIO64/65) are
  * connected to "UART1" controller.
  */
 #if (BOARD_VERSION == 2)
-#define NPCX_UART_MODULE2  1 /* 1:GPIO64/65 as UART1 */
+#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART1 */
 #else
-#define NPCX_UART_MODULE2  0 /* 0:GPIO10/11 as UART1 */
+#define NPCX_UART_MODULE2 0 /* 0:GPIO10/11 as UART1 */
 #endif
-#define NPCX_JTAG_MODULE2  0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG */
-#define NPCX_TACH_SEL2     0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
-#define NPCX7_PWM1_SEL     0 /* 0:GPIOC2 as I2CSCL0 1:as PWM1 (only in npcx7) */
+#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG */
+#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
+#define NPCX7_PWM1_SEL 0 /* 0:GPIOC2 as I2CSCL0 1:as PWM1 (only in npcx7) */
 
 #ifndef __ASSEMBLER__
 
diff --git a/board/npcx7_evb/build.mk b/board/npcx7_evb/build.mk
index 4bd829202c..e51c3bdc5c 100644
--- a/board/npcx7_evb/build.mk
+++ b/board/npcx7_evb/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/npcx7_evb/ec.tasklist b/board/npcx7_evb/ec.tasklist
index 88b5ffaa62..24e3b42d7c 100644
--- a/board/npcx7_evb/ec.tasklist
+++ b/board/npcx7_evb/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/npcx7_evb/gpio.inc b/board/npcx7_evb/gpio.inc
index 145a48de85..b8cfa1d8d5 100644
--- a/board/npcx7_evb/gpio.inc
+++ b/board/npcx7_evb/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/npcx9_evb/board.c b/board/npcx9_evb/board.c
index 892c0d1031..27b1651a0c 100644
--- a/board/npcx9_evb/board.c
+++ b/board/npcx9_evb/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,10 +6,10 @@
 /* Nuvoton M4 EB board-specific configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "backlight.h"
 #include "chipset.h"
 #include "common.h"
+#include "driver/temp_sensor/tmp112.h"
 #include "extpower.h"
 #include "fan.h"
 #include "fan_chip.h"
@@ -27,34 +27,47 @@
 #include "switch.h"
 #include "temp_sensor.h"
 #include "temp_sensor_chip.h"
-#include "timer.h"
 #include "thermal.h"
+#include "timer.h"
 #include "util.h"
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /******************************************************************************/
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
-	[ADC_CH_0] = {"ADC0", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_1] = {"ADC1", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_2] = {"ADC2", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_3] = {"ADC3", NPCX_ADC_CH3, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_4] = {"ADC4", NPCX_ADC_CH4, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_5] = {"ADC5", NPCX_ADC_CH5, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_6] = {"ADC6", NPCX_ADC_CH6, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_7] = {"ADC7", NPCX_ADC_CH7, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_8] = {"ADC8", NPCX_ADC_CH8, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_9] = {"ADC9", NPCX_ADC_CH9, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_10] = {"ADC10", NPCX_ADC_CH10, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_11] = {"ADC11", NPCX_ADC_CH11, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_CH_0] = { "ADC0", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+		       0 },
+	[ADC_CH_1] = { "ADC1", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+		       0 },
+	[ADC_CH_2] = { "ADC2", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+		       0 },
+	[ADC_CH_3] = { "ADC3", NPCX_ADC_CH3, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+		       0 },
+	[ADC_CH_4] = { "ADC4", NPCX_ADC_CH4, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+		       0 },
+	[ADC_CH_5] = { "ADC5", NPCX_ADC_CH5, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+		       0 },
+	[ADC_CH_6] = { "ADC6", NPCX_ADC_CH6, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+		       0 },
+	[ADC_CH_7] = { "ADC7", NPCX_ADC_CH7, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+		       0 },
+	[ADC_CH_8] = { "ADC8", NPCX_ADC_CH8, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+		       0 },
+	[ADC_CH_9] = { "ADC9", NPCX_ADC_CH9, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+		       0 },
+	[ADC_CH_10] = { "ADC10", NPCX_ADC_CH10, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+			0 },
+	[ADC_CH_11] = { "ADC11", NPCX_ADC_CH11, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+			0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /******************************************************************************/
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN] = { 0, PWM_CONFIG_OPEN_DRAIN, 25000},
+	[PWM_CH_FAN] = { 0, PWM_CONFIG_OPEN_DRAIN, 25000 },
 	[PWM_CH_KBLIGHT] = { 2, 0, 10000 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
@@ -63,7 +76,7 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 /* Physical fans. These are logically separate from pwm_channels. */
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = 0,	/* Use MFT id to control fan */
+	.ch = 0, /* Use MFT id to control fan */
 	.pgood_gpio = GPIO_PGOOD_FAN,
 	.enable_gpio = -1,
 };
@@ -79,31 +92,58 @@ const struct fan_t fans[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
 
+/******************************************************************************/
+/* TMP112 sensors. Must be in the exactly same order as in enum tmp112_sensor */
+const struct tmp112_sensor_t tmp112_sensors[] = {
+	{ I2C_PORT_THERMAL, TMP112_I2C_ADDR_FLAGS0 },
+};
+BUILD_ASSERT(ARRAY_SIZE(tmp112_sensors) == TMP112_COUNT);
+
+/******************************************************************************/
+/* Temperature sensor. */
+const struct temp_sensor_t temp_sensors[] = {
+	{ "System", TEMP_SENSOR_TYPE_BOARD, tmp112_get_val_k, TMP112_0 },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
 /******************************************************************************/
 /* MFT channels. These are logically separate from pwm_channels. */
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN },
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 /******************************************************************************/
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{"master0-0", NPCX_I2C_PORT0_0, 100, GPIO_I2C0_SCL0, GPIO_I2C0_SDA0},
-	{"master1-0", NPCX_I2C_PORT1_0, 100, GPIO_I2C1_SCL0, GPIO_I2C1_SDA0},
-	{"master2-0", NPCX_I2C_PORT2_0, 100, GPIO_I2C2_SCL0, GPIO_I2C2_SDA0},
-	{"master3-0", NPCX_I2C_PORT3_0, 100, GPIO_I2C3_SCL0, GPIO_I2C3_SDA0},
-	{"master7-0", NPCX_I2C_PORT7_0, 100, GPIO_I2C7_SCL0, GPIO_I2C7_SDA0},
+	{ .name = "master0-0",
+	  .port = NPCX_I2C_PORT0_0,
+	  .kbps = 100,
+	  .scl = GPIO_I2C0_SCL0,
+	  .sda = GPIO_I2C0_SDA0 },
+	{ .name = "master1-0",
+	  .port = NPCX_I2C_PORT1_0,
+	  .kbps = 100,
+	  .scl = GPIO_I2C1_SCL0,
+	  .sda = GPIO_I2C1_SDA0 },
+	{ .name = "master2-0",
+	  .port = NPCX_I2C_PORT2_0,
+	  .kbps = 100,
+	  .scl = GPIO_I2C2_SCL0,
+	  .sda = GPIO_I2C2_SDA0 },
+	{ .name = "master3-0",
+	  .port = NPCX_I2C_PORT3_0,
+	  .kbps = 100,
+	  .scl = GPIO_I2C3_SCL0,
+	  .sda = GPIO_I2C3_SDA0 },
+	{ .name = "master7-0",
+	  .port = NPCX_I2C_PORT7_0,
+	  .kbps = 100,
+	  .scl = GPIO_I2C7_SCL0,
+	  .sda = GPIO_I2C7_SDA0 },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
-/******************************************************************************/
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-	{ CONFIG_SPI_FLASH_PORT, 0, GPIO_SPI_CS_L},
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
 /******************************************************************************/
 /* Wake-up pins for hibernate */
 const enum gpio_signal hibernate_wake_pins[] = {
@@ -115,7 +155,7 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 
 /******************************************************************************/
 /* Keyboard scan setting */
-struct keyboard_scan_config keyscan_config = {
+__override struct keyboard_scan_config keyscan_config = {
 	.output_settle_us = 40,
 	.debounce_down_us = 6 * MSEC,
 	.debounce_up_us = 30 * MSEC,
diff --git a/board/npcx9_evb/board.h b/board/npcx9_evb/board.h
index cac7ea99be..a613a712f5 100644
--- a/board/npcx9_evb/board.h
+++ b/board/npcx9_evb/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,43 +11,46 @@
 /* EC modules */
 #define CONFIG_ADC
 #define CONFIG_PWM
-#define CONFIG_SPI
 #define CONFIG_I2C
 /* Features of eSPI */
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#define CONFIG_HOST_INTERFACE_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 
 /* Optional features */
 #define CONFIG_ENABLE_JTAG_SELECTION
 #define CONFIG_BOARD_VERSION_GPIO
 #define CONFIG_EXTPOWER_GPIO
-#define CONFIG_I2C_MASTER
-#define CONFIG_KEYBOARD_BOARD_CONFIG
+#define CONFIG_HIBERNATE_PSL_COMPENSATE_RTC
+#define CONFIG_I2C_CONTROLLER
+
 #define CONFIG_KEYBOARD_PROTOCOL_8042
-#undef  CONFIG_LOW_POWER_IDLE /* Deep Sleep Support */
+#undef CONFIG_LOW_POWER_IDLE /* Deep Sleep Support */
 #define CONFIG_POWER_BUTTON
-#undef  CONFIG_PSTORE
+#undef CONFIG_PSTORE
 #define CONFIG_PWM_KBLIGHT
 #define CONFIG_VBOOT_HASH
 #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands */
 
 /* EC console commands */
 #define CONFIG_CMD_TASKREADY
-#define CONFIG_CMD_STACKOVERFLOW
 #define CONFIG_CMD_JUMPTAGS
 #define CONFIG_CMD_FLASH
-#define CONFIG_CMD_SPI_FLASH
+#define CONFIG_CMD_RTC
 #define CONFIG_CMD_SCRATCHPAD
 #define CONFIG_CMD_I2CWEDGE
 
 /* I2C port for CONFIG_CMD_I2CWEDGE */
 #define I2C_PORT_MASTER NPCX_I2C_PORT0_0
-#define I2C_PORT_HOST   0
+#define I2C_PORT_HOST 0
 
 /* Fans for testing */
 #define CONFIG_FANS 1
 
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_TEMP_SENSOR_TMP112
+#define I2C_PORT_THERMAL NPCX_I2C_PORT2_0
+
 #define CONFIG_KEYBOARD_KSO_HIGH_DRIVE /* Quasi-bidirectional buf for KSOs */
 #define CONFIG_HIBERNATE_PSL /* Use PSL (Power Switch Logic) for hibernate */
 #undef CONFIG_CLOCK_SRC_EXTERNAL /* Use external 32kHz OSC as LFCLK source */
@@ -56,15 +59,15 @@
 
 /* Select which UART Controller is the Console UART */
 #undef CONFIG_CONSOLE_UART
-#define CONFIG_CONSOLE_UART    0 /* 0:UART1 1:UART2 */
+#define CONFIG_CONSOLE_UART 0 /* 0:UART1 1:UART2 */
 /*
  * This definition below actually doesn't define which UART controller to be
  * used. Instead, it defines which pinouts (GPIO10/11 or GPIO64/65) are
  * connected to "UART1" controller.
  */
-#define NPCX_UART_MODULE2  1 /* 1:GPIO64/65 as UART1 */
-#define NPCX_TACH_SEL2     0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
-#define NPCX9_PWM1_SEL     0 /* 0:GPIOC2 as I2CSCL0 1:as PWM1 */
+#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART1 */
+#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
+#define NPCX9_PWM1_SEL 0 /* 0:GPIOC2 as I2CSCL0 1:as PWM1 */
 
 #ifndef __ASSEMBLER__
 
@@ -84,6 +87,16 @@ enum adc_channel {
 	ADC_CH_COUNT
 };
 
+enum tmp112_sensor {
+	TMP112_0,
+	TMP112_COUNT,
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_SYSTHERM0, /* TMP100 */
+	TEMP_SENSOR_COUNT
+};
+
 enum pwm_channel {
 	PWM_CH_FAN,
 	PWM_CH_KBLIGHT,
@@ -104,6 +117,7 @@ enum mft_channel {
 };
 
 #include "gpio_signal.h"
+#include "registers.h"
 
 #endif /* !__ASSEMBLER__ */
 
diff --git a/board/npcx9_evb/build.mk b/board/npcx9_evb/build.mk
index 92bcc84144..d2526afb1b 100644
--- a/board/npcx9_evb/build.mk
+++ b/board/npcx9_evb/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/npcx9_evb/ec.tasklist b/board/npcx9_evb/ec.tasklist
index 9560b43561..d41f0ade2f 100644
--- a/board/npcx9_evb/ec.tasklist
+++ b/board/npcx9_evb/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/npcx9_evb/gpio.inc b/board/npcx9_evb/gpio.inc
index ec57c1afc5..28dbbba93a 100644
--- a/board/npcx9_evb/gpio.inc
+++ b/board/npcx9_evb/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/npcx_evb/board.c b/board/npcx_evb/board.c
index cee9acfeef..dab80f8531 100644
--- a/board/npcx_evb/board.c
+++ b/board/npcx_evb/board.c
@@ -1,11 +1,10 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 /* EC for Nuvoton M4 EB configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "backlight.h"
 #include "chipset.h"
 #include "common.h"
@@ -27,25 +26,29 @@
 #include "switch.h"
 #include "temp_sensor.h"
 #include "temp_sensor_chip.h"
-#include "timer.h"
 #include "thermal.h"
+#include "timer.h"
 #include "util.h"
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /******************************************************************************/
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
-	[ADC_CH_0] = {"ADC0", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_1] = {"ADC1", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_2] = {"ADC2", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_CH_0] = { "ADC0", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+		       0 },
+	[ADC_CH_1] = { "ADC1", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+		       0 },
+	[ADC_CH_2] = { "ADC2", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+		       0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /******************************************************************************/
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN] = { 0, PWM_CONFIG_OPEN_DRAIN, 25000},
+	[PWM_CH_FAN] = { 0, PWM_CONFIG_OPEN_DRAIN, 25000 },
 #if (CONFIG_FANS == 2)
 	[PWM_CH_FAN2] = { 2, 0, 25000 },
 #endif
@@ -57,14 +60,14 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 /* Physical fans. These are logically separate from pwm_channels. */
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = 0,	/* Use MFT id to control fan */
+	.ch = 0, /* Use MFT id to control fan */
 	.pgood_gpio = GPIO_PGOOD_FAN,
 	.enable_gpio = -1,
 };
 
 const struct fan_conf fan_conf_1 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = 1,	/* Use MFT id to control fan */
+	.ch = 1, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = -1,
 };
@@ -92,9 +95,9 @@ BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
 /******************************************************************************/
 /* MFT channels. These are logically separate from pwm_channels. */
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN },
 #if (CONFIG_FANS == 2)
-	[MFT_CH_1] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN2},
+	[MFT_CH_1] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN2 },
 #endif
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
@@ -102,18 +105,38 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 /******************************************************************************/
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{"master0-0", NPCX_I2C_PORT0_0, 100, GPIO_I2C0_SCL0, GPIO_I2C0_SDA0},
-	{"master0-1", NPCX_I2C_PORT0_1, 100, GPIO_I2C0_SCL1, GPIO_I2C0_SDA1},
-	{"master1",   NPCX_I2C_PORT1,   100, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"master2",   NPCX_I2C_PORT2,   100, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-	{"master3",   NPCX_I2C_PORT3,   100, GPIO_I2C3_SCL, GPIO_I2C3_SDA},
+	{ .name = "master0-0",
+	  .port = NPCX_I2C_PORT0_0,
+	  .kbps = 100,
+	  .scl = GPIO_I2C0_SCL0,
+	  .sda = GPIO_I2C0_SDA0 },
+	{ .name = "master0-1",
+	  .port = NPCX_I2C_PORT0_1,
+	  .kbps = 100,
+	  .scl = GPIO_I2C0_SCL1,
+	  .sda = GPIO_I2C0_SDA1 },
+	{ .name = "master1",
+	  .port = NPCX_I2C_PORT1,
+	  .kbps = 100,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "master2",
+	  .port = NPCX_I2C_PORT2,
+	  .kbps = 100,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "master3",
+	  .port = NPCX_I2C_PORT3,
+	  .kbps = 100,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
 /******************************************************************************/
 /* SPI devices */
 const struct spi_device_t spi_devices[] = {
-	{ CONFIG_SPI_FLASH_PORT, 0, GPIO_SPI_CS_L},
+	{ CONFIG_SPI_FLASH_PORT, 0, GPIO_SPI_CS_L },
 };
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
@@ -126,7 +149,7 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 
 /******************************************************************************/
 /* Keyboard scan setting */
-struct keyboard_scan_config keyscan_config = {
+__override struct keyboard_scan_config keyscan_config = {
 	.output_settle_us = 40,
 	.debounce_down_us = 6 * MSEC,
 	.debounce_up_us = 30 * MSEC,
diff --git a/board/npcx_evb/board.h b/board/npcx_evb/board.h
index d7b7b6162a..08cf1176d3 100644
--- a/board/npcx_evb/board.h
+++ b/board/npcx_evb/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,19 +12,19 @@
 #define CONFIG_ADC
 #define CONFIG_PWM
 #define CONFIG_SPI
-#define CONFIG_HOSTCMD_LPC
+#define CONFIG_HOST_INTERFACE_LPC
 #define CONFIG_PECI
 
 /* Optional features */
 #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands for testing */
 #define CONFIG_SPI_FLASH_PORT 0
 #define CONFIG_SPI_FLASH
-#define CONFIG_FLASH_SIZE          0x00800000 /* 8MB spi flash */
+#define CONFIG_FLASH_SIZE_BYTES 0x00800000 /* 8MB spi flash */
 #define CONFIG_SPI_FLASH_REGS
 #define CONFIG_SPI_FLASH_W25Q64
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
-#define CONFIG_KEYBOARD_BOARD_CONFIG
+#define CONFIG_I2C_CONTROLLER
+
 #define CONFIG_KEYBOARD_PROTOCOL_8042
 #define CONFIG_POWER_BUTTON
 #define CONFIG_VBOOT_HASH
@@ -34,36 +34,30 @@
 
 /* Optional features for test commands */
 #define CONFIG_CMD_TASKREADY
-#define CONFIG_CMD_STACKOVERFLOW
 #define CONFIG_CMD_JUMPTAGS
 #define CONFIG_CMD_FLASH
 #define CONFIG_CMD_SPI_FLASH
 #define CONFIG_CMD_SCRATCHPAD
 #define CONFIG_CMD_I2CWEDGE
 
-#define CONFIG_FANS                     1
+#define CONFIG_FANS 1
 
 /* Optional feature - used by nuvoton */
-#define NPCX_UART_MODULE2    0 /* 0:GPIO10/11 1:GPIO64/65 as UART */
-#define NPCX_JTAG_MODULE2    0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/
-#define NPCX_TACH_SEL2       0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
+#define NPCX_UART_MODULE2 0 /* 0:GPIO10/11 1:GPIO64/65 as UART */
+#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/
+#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
 
 /* Optional for testing */
-#undef  CONFIG_PSTORE
-#undef  CONFIG_LOW_POWER_IDLE           /* Deep Sleep Support */
+#undef CONFIG_PSTORE
+#undef CONFIG_LOW_POWER_IDLE /* Deep Sleep Support */
 
 /* Single I2C port, where the EC is the master. */
-#define I2C_PORT_MASTER         NPCX_I2C_PORT0_0
-#define I2C_PORT_HOST           0
+#define I2C_PORT_MASTER NPCX_I2C_PORT0_0
+#define I2C_PORT_HOST 0
 
 #ifndef __ASSEMBLER__
 
-enum adc_channel {
-	ADC_CH_0 = 0,
-	ADC_CH_1,
-	ADC_CH_2,
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_CH_0 = 0, ADC_CH_1, ADC_CH_2, ADC_CH_COUNT };
 
 enum pwm_channel {
 	PWM_CH_FAN,
diff --git a/board/npcx_evb/build.mk b/board/npcx_evb/build.mk
index 7dfc4544f2..c86457489f 100644
--- a/board/npcx_evb/build.mk
+++ b/board/npcx_evb/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
+# Copyright 2014 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/npcx_evb/ec.tasklist b/board/npcx_evb/ec.tasklist
index b0d584174e..82d4d031a2 100644
--- a/board/npcx_evb/ec.tasklist
+++ b/board/npcx_evb/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/npcx_evb/gpio.inc b/board/npcx_evb/gpio.inc
index c4e673fd25..584cbfd9b2 100644
--- a/board/npcx_evb/gpio.inc
+++ b/board/npcx_evb/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
+ * Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/npcx_evb_arm/board.c b/board/npcx_evb_arm/board.c
index f99ab2e0f6..28b72d5f3c 100644
--- a/board/npcx_evb_arm/board.c
+++ b/board/npcx_evb_arm/board.c
@@ -1,11 +1,10 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 /* EC for Nuvoton M4 EB configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "backlight.h"
 #include "chipset.h"
 #include "common.h"
@@ -23,29 +22,33 @@
 #include "pwm.h"
 #include "pwm_chip.h"
 #include "registers.h"
+#include "shi_chip.h"
 #include "switch.h"
 #include "temp_sensor.h"
 #include "temp_sensor_chip.h"
-#include "timer.h"
 #include "thermal.h"
+#include "timer.h"
 #include "util.h"
-#include "shi_chip.h"
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /******************************************************************************/
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
-	[ADC_CH_0] = {"ADC0", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_1] = {"ADC1", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_2] = {"ADC2", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_CH_0] = { "ADC0", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+		       0 },
+	[ADC_CH_1] = { "ADC1", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+		       0 },
+	[ADC_CH_2] = { "ADC2", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+		       0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /******************************************************************************/
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN] = { 0, PWM_CONFIG_OPEN_DRAIN, 25000},
+	[PWM_CH_FAN] = { 0, PWM_CONFIG_OPEN_DRAIN, 25000 },
 	[PWM_CH_KBLIGHT] = { 1, 0, 10000 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
@@ -54,7 +57,7 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 /* Physical fans. These are logically separate from pwm_channels. */
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = 0,	/* Use MFT id to control fan */
+	.ch = 0, /* Use MFT id to control fan */
 	.pgood_gpio = GPIO_PGOOD_FAN,
 	.enable_gpio = -1,
 };
@@ -73,18 +76,38 @@ BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
 /******************************************************************************/
 /* MFT channels. These are logically separate from pwm_channels. */
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN },
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 /******************************************************************************/
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{"master0-0", NPCX_I2C_PORT0_0, 100, GPIO_I2C0_SCL0, GPIO_I2C0_SDA0},
-	{"master0-1", NPCX_I2C_PORT0_1, 100, GPIO_I2C0_SCL1, GPIO_I2C0_SDA1},
-	{"master1",   NPCX_I2C_PORT1,   100, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"master2",   NPCX_I2C_PORT2,   100, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-	{"master3",   NPCX_I2C_PORT3,   100, GPIO_I2C3_SCL, GPIO_I2C3_SDA},
+	{ .name = "master0-0",
+	  .port = NPCX_I2C_PORT0_0,
+	  .kbps = 100,
+	  .scl = GPIO_I2C0_SCL0,
+	  .sda = GPIO_I2C0_SDA0 },
+	{ .name = "master0-1",
+	  .port = NPCX_I2C_PORT0_1,
+	  .kbps = 100,
+	  .scl = GPIO_I2C0_SCL1,
+	  .sda = GPIO_I2C0_SDA1 },
+	{ .name = "master1",
+	  .port = NPCX_I2C_PORT1,
+	  .kbps = 100,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "master2",
+	  .port = NPCX_I2C_PORT2,
+	  .kbps = 100,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "master3",
+	  .port = NPCX_I2C_PORT3,
+	  .kbps = 100,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -97,7 +120,7 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 
 /******************************************************************************/
 /* Keyboard scan setting */
-struct keyboard_scan_config keyscan_config = {
+__override struct keyboard_scan_config keyscan_config = {
 	.output_settle_us = 40,
 	.debounce_down_us = 6 * MSEC,
 	.debounce_up_us = 30 * MSEC,
diff --git a/board/npcx_evb_arm/board.h b/board/npcx_evb_arm/board.h
index 5128bffd0a..a3cbacdc6d 100644
--- a/board/npcx_evb_arm/board.h
+++ b/board/npcx_evb_arm/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,17 +11,18 @@
 /* Optional modules */
 #define CONFIG_ADC
 #define CONFIG_PWM
-#define CONFIG_HOSTCMD_SPS /* Used in ARM-based platform for host interface */
+#define CONFIG_HOST_INTERFACE_SHI /* ARM-based platform for host interface */
 
 /* Optional features */
 #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands for testing */
-#define CONFIG_FLASH_SIZE          0x00800000 /* 8MB spi flash */
+#define CONFIG_FLASH_SIZE_BYTES 0x00800000 /* 8MB spi flash */
 #define CONFIG_SPI_FLASH_REGS
 #define CONFIG_SPI_FLASH_W25Q64
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
-#define CONFIG_KEYBOARD_BOARD_CONFIG
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP /* Instead of 8042 protocol of keyboard */
+#define CONFIG_I2C_CONTROLLER
+
+#define CONFIG_KEYBOARD_PROTOCOL_MKBP /* Instead of 8042 protocol of keyboard \
+				       */
 #define CONFIG_MKBP_USE_GPIO
 #define CONFIG_POWER_BUTTON
 #define CONFIG_VBOOT_HASH
@@ -31,41 +32,35 @@
 
 /* Optional features for test commands */
 #define CONFIG_CMD_TASKREADY
-#define CONFIG_CMD_STACKOVERFLOW
 #define CONFIG_CMD_JUMPTAGS
 #define CONFIG_CMD_FLASH
 #define CONFIG_CMD_SPI_FLASH
 #define CONFIG_CMD_SCRATCHPAD
 #define CONFIG_CMD_I2CWEDGE
 
-#define CONFIG_UART_HOST                0
-#define CONFIG_FANS                     1
+#define CONFIG_UART_HOST 0
+#define CONFIG_FANS 1
 
 /* Optional feature - used by nuvoton */
-#define NPCX_UART_MODULE2    0 /* 0:GPIO10/11 1:GPIO64/65 as UART */
-#define NPCX_JTAG_MODULE2    0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/
-#define NPCX_TACH_SEL2       0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
+#define NPCX_UART_MODULE2 0 /* 0:GPIO10/11 1:GPIO64/65 as UART */
+#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/
+#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
 /* Enable SHI PU on transition to S0. Disable the PU otherwise for leakage. */
 #define NPCX_SHI_CS_PU
 /* Enable bypass since shi outputs invalid data when across 256B boundary */
 #define NPCX_SHI_BYPASS_OVER_256B
 
 /* Optional for testing */
-#undef  CONFIG_PSTORE
-#undef  CONFIG_LOW_POWER_IDLE           /* Deep Sleep Support */
+#undef CONFIG_PSTORE
+#undef CONFIG_LOW_POWER_IDLE /* Deep Sleep Support */
 
 /* Single I2C port, where the EC is the master. */
-#define I2C_PORT_MASTER         NPCX_I2C_PORT0_0
-#define I2C_PORT_HOST           0
+#define I2C_PORT_MASTER NPCX_I2C_PORT0_0
+#define I2C_PORT_HOST 0
 
 #ifndef __ASSEMBLER__
 
-enum adc_channel {
-	ADC_CH_0 = 0,
-	ADC_CH_1,
-	ADC_CH_2,
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_CH_0 = 0, ADC_CH_1, ADC_CH_2, ADC_CH_COUNT };
 
 enum pwm_channel {
 	PWM_CH_FAN,
diff --git a/board/npcx_evb_arm/build.mk b/board/npcx_evb_arm/build.mk
index 48116c5454..e1a3762504 100644
--- a/board/npcx_evb_arm/build.mk
+++ b/board/npcx_evb_arm/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/npcx_evb_arm/ec.tasklist b/board/npcx_evb_arm/ec.tasklist
index a014b86350..078059e9d8 100644
--- a/board/npcx_evb_arm/ec.tasklist
+++ b/board/npcx_evb_arm/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/npcx_evb_arm/gpio.inc b/board/npcx_evb_arm/gpio.inc
index 1cdda98300..dc94a8ac7b 100644
--- a/board/npcx_evb_arm/gpio.inc
+++ b/board/npcx_evb_arm/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nucleo-dartmonkey/board.c b/board/nucleo-dartmonkey/board.c
index ea5a921aa7..9b8ba6c42c 100644
--- a/board/nucleo-dartmonkey/board.c
+++ b/board/nucleo-dartmonkey/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,13 +27,19 @@ int console_is_restricted(void)
 static void ap_deferred(void)
 {
 	/*
-	 * in S3:   SLP_S3_L is 0 and SLP_S0_L is X.
-	 * in S0ix: SLP_S3_L is X and SLP_S0_L is 0.
-	 * in S0:   SLP_S3_L is 1 and SLP_S0_L is 1.
+	 * Behavior:
+	 * AP Active  (ex. Intel S0):   SLP_L is 1
+	 * AP Suspend (ex. Intel S0ix): SLP_L is 0
+	 * The alternative SLP_ALT_L should be pulled high at all the times.
+	 *
+	 * Legacy Intel behavior:
+	 * in S3:   SLP_ALT_L is 0 and SLP_L is X.
+	 * in S0ix: SLP_ALT_L is X and SLP_L is 0.
+	 * in S0:   SLP_ALT_L is 1 and SLP_L is 1.
 	 * in S5/G3, the FP MCU should not be running.
 	 */
-	int running = gpio_get_level(GPIO_PCH_SLP_S3_L)
-			&& gpio_get_level(GPIO_PCH_SLP_S0_L);
+	int running = gpio_get_level(GPIO_SLP_ALT_L) &&
+		      gpio_get_level(GPIO_SLP_L);
 
 	if (running) { /* S0 */
 		disable_sleep(SLEEP_MASK_AP_RUN);
@@ -57,6 +63,7 @@ void fps_event(enum gpio_signal signal)
 }
 #endif
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /* SPI devices */
@@ -69,13 +76,15 @@ const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 static void spi_configure(void)
 {
 	/* Configure SPI GPIOs */
-	gpio_config_module(MODULE_SPI_MASTER, 1);
-	/* Set all SPI master signal pins to very high speed: pins E2/4/5/6 */
+	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
+	/* Set all SPI controller signal pins to very high speed:
+	 * pins E2/4/5/6
+	 */
 	STM32_GPIO_OSPEEDR(GPIO_E) |= 0x00003f30;
 	/* Enable clocks to SPI4 module (master) */
 	STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI4;
 
-	spi_enable(CONFIG_SPI_FP_PORT, 1);
+	spi_enable(&spi_devices[0], 1);
 }
 
 /* Initialize board. */
@@ -84,12 +93,17 @@ static void board_init(void)
 	spi_configure();
 
 	ccprints("TRANSPORT_SEL: %s",
-		fp_transport_type_to_str(get_fp_transport_type()));
+		 fp_transport_type_to_str(get_fp_transport_type()));
 
 	/* Enable interrupt on PCH power signals */
-	gpio_enable_interrupt(GPIO_PCH_SLP_S3_L);
-	gpio_enable_interrupt(GPIO_PCH_SLP_S0_L);
-	/* enable the SPI slave interface if the PCH is up */
-	hook_call_deferred(&ap_deferred_data, 0);
+	gpio_enable_interrupt(GPIO_SLP_ALT_L);
+	gpio_enable_interrupt(GPIO_SLP_L);
+
+	/*
+	 * Enable the SPI peripheral interface if the PCH is up.
+	 * Do not use hook_call_deferred(), because ap_deferred() will be
+	 * called after tasks with priority higher than HOOK task (very late).
+	 */
+	ap_deferred();
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/nucleo-dartmonkey/board.h b/board/nucleo-dartmonkey/board.h
index 00ef075129..4e070bf91b 100644
--- a/board/nucleo-dartmonkey/board.h
+++ b/board/nucleo-dartmonkey/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -31,27 +31,31 @@
 /* Fingerprint needs to store a secrect in the anti-rollback block */
 #define CONFIG_ROLLBACK_SECRET_SIZE 32
 
+#define CONFIG_BORINGSSL_CRYPTO
+
 /* SPI configuration for the fingerprint sensor */
-#define CONFIG_SPI_MASTER
-#define CONFIG_SPI_FP_PORT  2 /* SPI4: third master config */
+#define CONFIG_SPI_CONTROLLER
+#define CONFIG_SPI_FP_PORT 2 /* SPI4: third master config */
+
+#define CONFIG_FINGERPRINT_MCU
 
 #ifdef SECTION_IS_RW
-	/* Select fingerprint sensor */
-#	define CONFIG_FP_SENSOR_FPC1145
-#	define CONFIG_CMD_FPSENSOR_DEBUG
-	/* Special memory regions to store large arrays */
-#	define FP_FRAME_SECTION    __SECTION(ahb4)
-#	define FP_TEMPLATE_SECTION __SECTION(ahb)
-	/*
-	 * Use the malloc code only in the RW section (for the private library),
-	 * we cannot enable it in RO since it is not compatible with the RW
-	 * verification (shared_mem_init done too late).
-	 */
-#	define CONFIG_MALLOC
+/* Select fingerprint sensor */
+#define CONFIG_FP_SENSOR_FPC1145
+#define CONFIG_CMD_FPSENSOR_DEBUG
+/* Special memory regions to store large arrays */
+#define FP_FRAME_SECTION __SECTION(ahb4)
+#define FP_TEMPLATE_SECTION __SECTION(ahb)
+/*
+ * Use the malloc code only in the RW section (for the private library),
+ * we cannot enable it in RO since it is not compatible with the RW
+ * verification (shared_mem_init done too late).
+ */
+#define CONFIG_MALLOC
 #endif /* SECTION_IS_RW */
 
 #ifndef __ASSEMBLER__
-	void fps_event(enum gpio_signal signal);
+void fps_event(enum gpio_signal signal);
 #endif /* !__ASSEMBLER__ */
 
 #endif /* __BOARD_H */
diff --git a/board/nucleo-dartmonkey/build.mk b/board/nucleo-dartmonkey/build.mk
index 4d39121edc..c56a08af10 100644
--- a/board/nucleo-dartmonkey/build.mk
+++ b/board/nucleo-dartmonkey/build.mk
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -11,15 +11,36 @@ board-y+=fpsensor_detect.o
 
 # Enable on device tests
 test-list-y=\
+       abort \
        aes \
+       boringssl_crypto \
        compile_time_macros \
-       crc32 \
+       crc \
+       debug \
+       exception \
+       flash_physical \
+       flash_write_protect \
+       fpsensor \
+       fpsensor_auth_crypto_stateful \
+       fpsensor_auth_crypto_stateless \
+       fpsensor_hw \
+       libc_printf \
+       mpu \
        mutex \
        pingpong \
-       rsa \
+       printf \
+       queue \
+       rng_benchmark \
+       rollback \
+       rollback_entropy \
        rsa3 \
        rtc \
+       sbrk \
+       scratchpad \
        sha256 \
        sha256_unrolled \
-       stm32f_rtc \
+       static_if \
+       stdlib \
+       timer_dos \
        utils \
+       utils_str \
diff --git a/board/nucleo-dartmonkey/ec.tasklist b/board/nucleo-dartmonkey/ec.tasklist
index 80e226637b..7f35361949 100644
--- a/board/nucleo-dartmonkey/ec.tasklist
+++ b/board/nucleo-dartmonkey/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nucleo-dartmonkey/fpsensor_detect.c b/board/nucleo-dartmonkey/fpsensor_detect.c
index 72b9b89e11..07dee3d0cb 100644
--- a/board/nucleo-dartmonkey/fpsensor_detect.c
+++ b/board/nucleo-dartmonkey/fpsensor_detect.c
@@ -1,11 +1,11 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "fpsensor_detect.h"
 
-enum fp_sensor_type get_fp_sensor_type(void)
+enum fp_sensor_type fpsensor_detect_get_type(void)
 {
 	return FP_SENSOR_TYPE_FPC;
 }
diff --git a/board/nucleo-dartmonkey/gpio.inc b/board/nucleo-dartmonkey/gpio.inc
index e20027a8ff..a9e5101855 100644
--- a/board/nucleo-dartmonkey/gpio.inc
+++ b/board/nucleo-dartmonkey/gpio.inc
@@ -1,5 +1,5 @@
 /*
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,8 +14,8 @@
 #include "base-gpio.inc"
 
 /* Interrupts */
-GPIO_INT(PCH_SLP_S0_L,    PIN(D, 13), GPIO_INT_BOTH, slp_event)
-GPIO_INT(PCH_SLP_S3_L,    PIN(A, 11), GPIO_INT_BOTH, slp_event)
+GPIO_INT(SLP_L,           PIN(D, 13), GPIO_INT_BOTH, slp_event)
+GPIO_INT(SLP_ALT_L,       PIN(A, 11), GPIO_INT_BOTH, slp_event)
 
 /* Output for User Presence */
 GPIO(USER_PRES_L,         PIN(C, 5),  GPIO_ODR_HIGH)
@@ -25,4 +25,4 @@ GPIO_INT(FPS_INT,         PIN(A, 0),  GPIO_INT_RISING, fps_event)
 GPIO(FP_RST_ODL,          PIN(E, 0),  GPIO_OUT_HIGH)
 GPIO(SPI4_NSS,            PIN(E, 4),  GPIO_OUT_HIGH)
 /* SPI4 master to sensor: PE2/5/6 (CLK/MISO/MOSI) */
-ALTERNATE(PIN_MASK(E, 0x0064), GPIO_ALT_SPI, MODULE_SPI_MASTER,  0)
+ALTERNATE(PIN_MASK(E, 0x0064), GPIO_ALT_SPI, MODULE_SPI_CONTROLLER,  0)
diff --git a/board/nucleo-f072rb/board.c b/board/nucleo-f072rb/board.c
index 66e8960ce7..8d75379f97 100644
--- a/board/nucleo-f072rb/board.c
+++ b/board/nucleo-f072rb/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,9 +6,9 @@
 #include "common.h"
 #include "gpio.h"
 #include "hooks.h"
+#include "i2c.h"
 #include "registers.h"
 #include "task.h"
-#include "i2c.h"
 #include "timer.h"
 
 void button_event(enum gpio_signal signal)
@@ -21,10 +21,15 @@ void button_event(enum gpio_signal signal)
  * Mock interrupt handler. It's supposed to be overwritten by each suite
  * if needed.
  */
-__attribute__((weak)) void cts_irq1(enum gpio_signal signal) {}
-__attribute__((weak)) void cts_irq2(enum gpio_signal signal) {}
+__attribute__((weak)) void cts_irq1(enum gpio_signal signal)
+{
+}
+__attribute__((weak)) void cts_irq2(enum gpio_signal signal)
+{
+}
 #endif
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 void tick_event(void)
@@ -38,8 +43,12 @@ void tick_event(void)
 DECLARE_HOOK(HOOK_TICK, tick_event, HOOK_PRIO_DEFAULT);
 
 #ifdef CTS_MODULE_I2C
-const struct i2c_port_t i2c_ports[]  = {
-	{"test", STM32_I2C1_PORT, 100, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "test",
+	  .port = STM32_I2C1_PORT,
+	  .kbps = 100,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
 };
 
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
@@ -51,6 +60,5 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 static void board_init(void)
 {
 	gpio_enable_interrupt(GPIO_USER_BUTTON);
-
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/nucleo-f072rb/board.h b/board/nucleo-f072rb/board.h
index 9cc2fc2d0b..bd957d35db 100644
--- a/board/nucleo-f072rb/board.h
+++ b/board/nucleo-f072rb/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,14 +16,13 @@
 #define CONFIG_UART_CONSOLE 2
 
 /* Optional features */
-#define CONFIG_STM_HWTIMER32
 
 #ifdef CTS_MODULE
 #undef STM32_IRQ_EXT2_3_PRIORITY
-#define STM32_IRQ_EXT2_3_PRIORITY	2
+#define STM32_IRQ_EXT2_3_PRIORITY 2
 #ifdef CTS_MODULE_I2C
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_CONTROLLER
 #endif
 #endif
 
diff --git a/board/nucleo-f072rb/build.mk b/board/nucleo-f072rb/build.mk
index 0e069a31ad..7ac70706fc 100644
--- a/board/nucleo-f072rb/build.mk
+++ b/board/nucleo-f072rb/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/nucleo-f072rb/ec.tasklist b/board/nucleo-f072rb/ec.tasklist
index a6385530b5..3ddec80f41 100644
--- a/board/nucleo-f072rb/ec.tasklist
+++ b/board/nucleo-f072rb/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nucleo-f072rb/gpio.inc b/board/nucleo-f072rb/gpio.inc
index 6f3b592845..a14c7a5470 100644
--- a/board/nucleo-f072rb/gpio.inc
+++ b/board/nucleo-f072rb/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nucleo-f072rb/openocd-flash.cfg b/board/nucleo-f072rb/openocd-flash.cfg
index 91e3805c74..f06b3c22a2 100644
--- a/board/nucleo-f072rb/openocd-flash.cfg
+++ b/board/nucleo-f072rb/openocd-flash.cfg
@@ -1,4 +1,4 @@
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/board/nucleo-f411re/board.c b/board/nucleo-f411re/board.c
index 97f5a8a8d3..8fce43c988 100644
--- a/board/nucleo-f411re/board.c
+++ b/board/nucleo-f411re/board.c
@@ -1,11 +1,10 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 /* nucleo-f411re development board configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "common.h"
 #include "console.h"
 #include "driver/accelgyro_bmi_common.h"
@@ -14,8 +13,6 @@
 #include "hooks.h"
 #include "i2c.h"
 #include "motion_sense.h"
-
-#include "gpio.h"
 #include "registers.h"
 #include "task.h"
 #include "util.h"
@@ -25,6 +22,7 @@ void user_button_evt(enum gpio_signal signal)
 	ccprintf("Button %d, %d!\n", signal, gpio_get_level(signal));
 }
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /* Initialize board. */
@@ -44,17 +42,20 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* Arduino connectors analog pins */
-	[ADC1_0] = {"ADC1_0",  3000, 4096, 0, STM32_AIN(0)},
-	[ADC1_1] = {"ADC1_1",  3000, 4096, 0, STM32_AIN(1)},
-	[ADC1_4] = {"ADC1_4",  3000, 4096, 0, STM32_AIN(4)},
-	[ADC1_8] = {"ADC1_8",  3000, 4096, 0, STM32_AIN(8)},
+	[ADC1_0] = { "ADC1_0", 3000, 4096, 0, STM32_AIN(0) },
+	[ADC1_1] = { "ADC1_1", 3000, 4096, 0, STM32_AIN(1) },
+	[ADC1_4] = { "ADC1_4", 3000, 4096, 0, STM32_AIN(4) },
+	[ADC1_8] = { "ADC1_8", 3000, 4096, 0, STM32_AIN(8) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{"master", I2C_PORT_MASTER, 100,
-	 GPIO_MASTER_I2C_SCL, GPIO_MASTER_I2C_SDA},
+	{ .name = "master",
+	  .port = I2C_PORT_MASTER,
+	  .kbps = 100,
+	  .scl = GPIO_MASTER_I2C_SCL,
+	  .sda = GPIO_MASTER_I2C_SDA },
 };
 
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
@@ -113,13 +114,12 @@ const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
 #ifdef CONFIG_DMA_HELP
 #include "dma.h"
-int command_dma_help(int argc, char **argv)
+static int command_dma_help(int argc, const char **argv)
 {
 	dma_dump(STM32_DMA2_STREAM0);
 	dma_test(STM32_DMA2_STREAM0);
 	dma_dump(STM32_DMA2_STREAM0);
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(dmahelp, command_dma_help,
-			NULL, "Run DMA test");
+DECLARE_CONSOLE_COMMAND(dmahelp, command_dma_help, NULL, "Run DMA test");
 #endif
diff --git a/board/nucleo-f411re/board.h b/board/nucleo-f411re/board.h
index 069e1367f2..3b7d5f1bf1 100644
--- a/board/nucleo-f411re/board.h
+++ b/board/nucleo-f411re/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,7 +12,6 @@
 #define CPU_CLOCK 84000000
 #define CONFIG_FLASH_WRITE_SIZE STM32_FLASH_WRITE_SIZE_3300
 
-
 /* the UART console is on USART2 (PA2/PA3) */
 #undef CONFIG_UART_CONSOLE
 #define CONFIG_UART_CONSOLE 2
@@ -20,7 +19,6 @@
 /* Optional features */
 #undef CONFIG_LID_SWITCH
 #undef CONFIG_HIBERNATE
-#define CONFIG_STM_HWTIMER32
 #define CONFIG_WATCHDOG_HELP
 #define CONFIG_TASK_PROFILING
 
@@ -40,10 +38,10 @@
 #define CONFIG_CMD_FLASH
 
 /* I2C ports configuration */
-#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_CONTROLLER
 #define CONFIG_I2C_DEBUG
 #define I2C_PORT_MASTER 1
-#define I2C_PORT_SLAVE 0        /* needed for DMAC macros (ugh) */
+#define I2C_PORT_SLAVE 0 /* needed for DMAC macros (ugh) */
 #define I2C_PORT_ACCEL I2C_PORT_MASTER
 
 #ifndef __ASSEMBLER__
diff --git a/board/nucleo-f411re/build.mk b/board/nucleo-f411re/build.mk
index 3a5fc28558..93a0a02ecc 100644
--- a/board/nucleo-f411re/build.mk
+++ b/board/nucleo-f411re/build.mk
@@ -1,4 +1,4 @@
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/nucleo-f411re/ec.tasklist b/board/nucleo-f411re/ec.tasklist
index b5e3cb82b2..a9566a92aa 100644
--- a/board/nucleo-f411re/ec.tasklist
+++ b/board/nucleo-f411re/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nucleo-f411re/gpio.inc b/board/nucleo-f411re/gpio.inc
index 83a9e51a08..2fd98f2a4a 100644
--- a/board/nucleo-f411re/gpio.inc
+++ b/board/nucleo-f411re/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nucleo-f411re/openocd-flash.cfg b/board/nucleo-f411re/openocd-flash.cfg
index 7a6ea6316c..23da86c6ba 100644
--- a/board/nucleo-f411re/openocd-flash.cfg
+++ b/board/nucleo-f411re/openocd-flash.cfg
@@ -1,4 +1,4 @@
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/board/nucleo-f412zg/README.md b/board/nucleo-f412zg/README.md
index fcdd5e40df..f2fa682e6f 100644
--- a/board/nucleo-f412zg/README.md
+++ b/board/nucleo-f412zg/README.md
@@ -1,22 +1,19 @@
 # Nucleo F412ZG
 
-This is a simpler EC example for the ST Nucleo F412ZG
-development board.
+This is a simpler EC example for the ST Nucleo F412ZG development board.
 
 # Quick Start
 
-The Nucleo dev boards have lots of developer friendly features,
-like an in-circuit debugger/programmer/UART-bridge, programmable
-LEDs, and a button, to name a few.
+The Nucleo dev boards have lots of developer friendly features, like an
+in-circuit debugger/programmer/UART-bridge, programmable LEDs, and a button, to
+name a few.
 
-The built-in debugger can be connected to using a Micro USB cable.
-It provides three great interfaces to the host.
-1. Mass storage interface for drag-drop programming
-2. Full ST-Link in-circuit debugger
-3. UART bridge for logs/consoles
+The built-in debugger can be connected to using a Micro USB cable. It provides
+three great interfaces to the host. 1. Mass storage interface for drag-drop
+programming 2. Full ST-Link in-circuit debugger 3. UART bridge for logs/consoles
 
-We will use a few of these interfaces below to program and interact
-with out Nucleo dev board.
+We will use a few of these interfaces below to program and interact with out
+Nucleo dev board.
 
 ## Build
 
@@ -26,17 +23,17 @@ make BOARD=nucleo-f412zg -j
 
 ## Program
 
-The easiest way to flash the Nucleo board is to Copy-Paste/Drag-Drop
-the firmware image onto the exposed mass storage drive.
+The easiest way to flash the Nucleo board is to Copy-Paste/Drag-Drop the
+firmware image onto the exposed mass storage drive.
 
-Open a file browser and `Copy` the file in `build/nucleo-f412zg/ec.bin`.
-Now, find the removable storage that the Nucleo device has presented,
-and `Paste` the file into the directory.
+Open a file browser and `Copy` the file in `build/nucleo-f412zg/ec.bin`. Now,
+find the removable storage that the Nucleo device has presented, and `Paste` the
+file into the directory.
 
 ## Interact
 
-After the Nucelo finishes programming, you can open the EC console.
-On GNU/Linux, this is mapped to `/dev/ttyACM0`.
+After the Nucleo finishes programming, you can open the EC console. On
+GNU/Linux, this is mapped to `/dev/ttyACM0`.
 
 Install `minicom` and issue the following command:
 
@@ -48,9 +45,9 @@ minicom -D/dev/ttyACM0
 
 A fun EC feature is that unit tests can be run on-device.
 
-This is made possible by an alternative build rule that generates a
-test image per unit test. These test images use a unit test specific taskset
-and console command to trigger them.
+This is made possible by an alternative build rule that generates a test image
+per unit test. These test images use a unit test specific taskset and console
+command to trigger them.
 
 ## Create
 
@@ -67,19 +64,20 @@ To build all unit test images for this board, run the following command:
 make BOARD=nucleo-f412zg tests
 ```
 
-You can build a specific unit test image by changing `tests` to `test-aes`,
-for the `aes` unit test.
+You can build a specific unit test image by changing `tests` to `test-aes`, for
+the `aes` unit test.
 
 ## Flash
 
-Copy/paste the `build/nucleo-f412zg/${TEST}/${TEST}.bin` file to the
-Nucleo's mass storage drive, where `${TEST}` is the name of the unit test,
-like `aes`.
+Copy/paste the `build/nucleo-f412zg/${TEST}/${TEST}.bin` file to the Nucleo's
+mass storage drive, where `${TEST}` is the name of the unit test, like `aes`.
 
 ## Run
 
-1. Connect to UART console
-   ```bash
-   minicom -D/dev/ttyACM0
-   ```
-2. Run the `runtest` command
\ No newline at end of file
+1.  Connect to UART console
+
+```bash
+minicom -D/dev/ttyACM0
+```
+
+1.  Run the `runtest` command
diff --git a/board/nucleo-f412zg/board.c b/board/nucleo-f412zg/board.c
index e06408c404..39110cd82b 100644
--- a/board/nucleo-f412zg/board.c
+++ b/board/nucleo-f412zg/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -31,8 +31,8 @@ static void ap_deferred(void)
 	 * in S0:   SLP_S3_L is 1 and SLP_S0_L is 1.
 	 * in S5/G3, the FP MCU should not be running.
 	 */
-	int running = gpio_get_level(GPIO_PCH_SLP_S3_L)
-			&& gpio_get_level(GPIO_PCH_SLP_S0_L);
+	int running = gpio_get_level(GPIO_PCH_SLP_S3_L) &&
+		      gpio_get_level(GPIO_PCH_SLP_S0_L);
 
 	if (running) { /* S0 */
 		disable_sleep(SLEEP_MASK_AP_RUN);
@@ -50,6 +50,7 @@ static void slp_event(enum gpio_signal signal)
 	hook_call_deferred(&ap_deferred_data, 0);
 }
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /* Initialize board. */
@@ -58,7 +59,12 @@ static void board_init(void)
 	/* Enable interrupt on PCH power signals */
 	gpio_enable_interrupt(GPIO_PCH_SLP_S3_L);
 	gpio_enable_interrupt(GPIO_PCH_SLP_S0_L);
-	/* enable the SPI slave interface if the PCH is up */
-	hook_call_deferred(&ap_deferred_data, 0);
+
+	/*
+	 * Enable the SPI peripheral interface if the PCH is up.
+	 * Do not use hook_call_deferred(), because ap_deferred() will be
+	 * called after tasks with priority higher than HOOK task (very late).
+	 */
+	ap_deferred();
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/nucleo-f412zg/board.h b/board/nucleo-f412zg/board.h
index 331fa29578..7e3c8d976d 100644
--- a/board/nucleo-f412zg/board.h
+++ b/board/nucleo-f412zg/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,4 +22,10 @@
 #define CONFIG_CONSOLE_COMMAND_FLAGS
 #define CONFIG_RESTRICTED_CONSOLE_COMMANDS
 
+/*
+ * Enable the blink example that exercises the LEDs.
+ */
+#define CONFIG_BLINK
+#define CONFIG_BLINK_LEDS GPIO_LED1, GPIO_LED2, GPIO_LED3
+
 #endif /* __BOARD_H */
diff --git a/board/nucleo-f412zg/build.mk b/board/nucleo-f412zg/build.mk
index 4dbe987b39..02b2222d93 100644
--- a/board/nucleo-f412zg/build.mk
+++ b/board/nucleo-f412zg/build.mk
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -10,21 +10,33 @@ board-y=board.o
 
 # Enable on device tests
 test-list-y=\
+       abort \
        aes \
+       boringssl_crypto \
        compile_time_macros \
-       crc32 \
+       crc \
+       debug \
+       exception \
        flash_physical \
        flash_write_protect \
+       libc_printf \
        mpu \
        mutex \
        pingpong \
+       printf \
+       queue \
+       rng_benchmark \
        rollback \
        rollback_entropy \
-       rsa \
        rsa3 \
        rtc \
+       sbrk \
        scratchpad \
        sha256 \
        sha256_unrolled \
+       static_if \
+       stdlib \
        stm32f_rtc \
+       timer_dos \
        utils \
+       utils_str \
diff --git a/board/nucleo-f412zg/ec.tasklist b/board/nucleo-f412zg/ec.tasklist
index 896eb2fdb3..04e21000f9 100644
--- a/board/nucleo-f412zg/ec.tasklist
+++ b/board/nucleo-f412zg/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nucleo-f412zg/gpio.inc b/board/nucleo-f412zg/gpio.inc
index 57f78203ba..6cc09a20df 100644
--- a/board/nucleo-f412zg/gpio.inc
+++ b/board/nucleo-f412zg/gpio.inc
@@ -1,5 +1,5 @@
 /*
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nucleo-g431rb/board.c b/board/nucleo-g431rb/board.c
index 01f8a55629..5a6a0a6f5c 100644
--- a/board/nucleo-g431rb/board.c
+++ b/board/nucleo-g431rb/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,8 +9,8 @@
 #include "gpio.h"
 #include "hooks.h"
 
-#include "gpio_list.h" /* Must come after other header files. */
-
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
 
 static void board_init(void)
 {
@@ -31,4 +31,3 @@ static void led_second(void)
 	gpio_set_level(GPIO_LED1, count++ & 0x1);
 }
 DECLARE_HOOK(HOOK_SECOND, led_second, HOOK_PRIO_DEFAULT);
-
diff --git a/board/nucleo-g431rb/board.h b/board/nucleo-g431rb/board.h
index a65daa4364..e2df8d2547 100644
--- a/board/nucleo-g431rb/board.h
+++ b/board/nucleo-g431rb/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,16 +12,14 @@
 #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
 
 #define CPU_CLOCK 48000000
-#define CONFIG_STM_HWTIMER32
 #define TIM_CLOCK32 2
-#define TIM_CLOCK_MSB  3
+#define TIM_CLOCK_MSB 3
 #define TIM_CLOCK_LSB 15
 #define TIM_WATCHDOG 7
 
 /* Nucelo platform does not have a lid switch */
 #undef CONFIG_LID_SWITCH
 
-
 /* Setup UART console */
 /*
  * The STM32G431 Nucleo-64 has two UARTs which can be connected to the virtual
@@ -49,24 +47,20 @@
 #define CONFIG_UART_TX_DMA_PH DMAMUX_REQ_USART1_TX
 #endif
 
-
 /*
  * Macros for GPIO signals used in common code that don't match the
  * schematic names. Signal names in gpio.inc match the schematic and are
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_ENTERING_RW	GPIO_EC_ENTERING_RW
-#define GPIO_WP_L		GPIO_EC_WP_L
-
-
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_WP_L GPIO_EC_WP_L
 
 #ifndef __ASSEMBLER__
 
 #include "gpio_signal.h"
 #include "registers.h"
 
-
 #endif /* !__ASSEMBLER__ */
 
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/nucleo-g431rb/build.mk b/board/nucleo-g431rb/build.mk
index 8140048cdd..a5a00675ee 100644
--- a/board/nucleo-g431rb/build.mk
+++ b/board/nucleo-g431rb/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/nucleo-g431rb/ec.tasklist b/board/nucleo-g431rb/ec.tasklist
index c272906fc7..682e6d8290 100644
--- a/board/nucleo-g431rb/ec.tasklist
+++ b/board/nucleo-g431rb/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nucleo-g431rb/gpio.inc b/board/nucleo-g431rb/gpio.inc
index 4dd4a6d966..4c7507eff9 100644
--- a/board/nucleo-g431rb/gpio.inc
+++ b/board/nucleo-g431rb/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nucleo-h743zi/README.md b/board/nucleo-h743zi/README.md
index 58d47219da..7ba8a143a3 100644
--- a/board/nucleo-h743zi/README.md
+++ b/board/nucleo-h743zi/README.md
@@ -1,22 +1,19 @@
 # Nucleo H743ZI
 
-This is a simpler EC example for the ST Nucleo H743ZI
-development board.
+This is a simpler EC example for the ST Nucleo H743ZI development board.
 
 # Quick Start
 
-The Nucleo dev boards have lots of developer friendly features,
-like an in-circuit debugger/programmer/UART-bridge, programmable
-LEDs, and a button, to name a few.
+The Nucleo dev boards have lots of developer friendly features, like an
+in-circuit debugger/programmer/UART-bridge, programmable LEDs, and a button, to
+name a few.
 
-The built-in debugger can be connected to using a Micro USB cable.
-It provides three great interfaces to the host.
-1. Mass storage interface for drag-drop programming
-2. Full ST-Link in-circuit debugger
-3. UART bridge for logs/consoles
+The built-in debugger can be connected to using a Micro USB cable. It provides
+three great interfaces to the host. 1. Mass storage interface for drag-drop
+programming 2. Full ST-Link in-circuit debugger 3. UART bridge for logs/consoles
 
-We will use a few of these interfaces below to program and interact
-with out Nucleo dev board.
+We will use a few of these interfaces below to program and interact with out
+Nucleo dev board.
 
 ## Build
 
@@ -26,17 +23,17 @@ make BOARD=nucleo-h743zi -j
 
 ## Program
 
-The easiest way to flash the Nucleo board is to Copy-Paste/Drag-Drop
-the firmware image onto the exposed mass storage drive.
+The easiest way to flash the Nucleo board is to Copy-Paste/Drag-Drop the
+firmware image onto the exposed mass storage drive.
 
-Open a file browser and `Copy` the file in `build/nucleo-h743zi/ec.bin`.
-Now, find the removable storage that the Nucleo device has presented,
-and `Paste` the file into the directory.
+Open a file browser and `Copy` the file in `build/nucleo-h743zi/ec.bin`. Now,
+find the removable storage that the Nucleo device has presented, and `Paste` the
+file into the directory.
 
 ## Interact
 
-After the Nucelo finishes programming, you can open the EC console.
-On GNU/Linux, this is mapped to `/dev/ttyACM0`.
+After the Nucleo finishes programming, you can open the EC console. On
+GNU/Linux, this is mapped to `/dev/ttyACM0`.
 
 Install `minicom` and issue the following command:
 
@@ -48,9 +45,9 @@ minicom -D/dev/ttyACM0
 
 A fun EC feature is that unit tests can be run on-device.
 
-This is made possible by an alternative build rule that generates a
-test image per unit test. These test images use a unit test specific taskset
-and console command to trigger them.
+This is made possible by an alternative build rule that generates a test image
+per unit test. These test images use a unit test specific taskset and console
+command to trigger them.
 
 ## Create
 
@@ -67,19 +64,20 @@ To build all unit test images for this board, run the following command:
 make BOARD=nucleo-h743zi tests
 ```
 
-You can build a specific unit test image by changing `tests` to `test-aes`,
-for the `aes` unit test.
+You can build a specific unit test image by changing `tests` to `test-aes`, for
+the `aes` unit test.
 
 ## Flash
 
-Copy/paste the `build/nucleo-h743zi/${TEST}/${TEST}.bin` file to the
-Nucleo's mass storage drive, where `${TEST}` is the name of the unit test,
-like `aes`.
+Copy/paste the `build/nucleo-h743zi/${TEST}/${TEST}.bin` file to the Nucleo's
+mass storage drive, where `${TEST}` is the name of the unit test, like `aes`.
 
 ## Run
 
-1. Connect to UART console
-   ```bash
-   minicom -D/dev/ttyACM0
-   ```
-2. Run the `runtest` command
\ No newline at end of file
+1.  Connect to UART console
+
+```bash
+minicom -D/dev/ttyACM0
+```
+
+1.  Run the `runtest` command
diff --git a/board/nucleo-h743zi/board.c b/board/nucleo-h743zi/board.c
index c4c7e764c8..0752b02f0c 100644
--- a/board/nucleo-h743zi/board.c
+++ b/board/nucleo-h743zi/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -31,8 +31,8 @@ static void ap_deferred(void)
 	 * in S0:   SLP_S3_L is 1 and SLP_S0_L is 1.
 	 * in S5/G3, the FP MCU should not be running.
 	 */
-	int running = gpio_get_level(GPIO_PCH_SLP_S3_L)
-			&& gpio_get_level(GPIO_PCH_SLP_S0_L);
+	int running = gpio_get_level(GPIO_PCH_SLP_S3_L) &&
+		      gpio_get_level(GPIO_PCH_SLP_S0_L);
 
 	if (running) { /* S0 */
 		disable_sleep(SLEEP_MASK_AP_RUN);
@@ -50,6 +50,7 @@ static void slp_event(enum gpio_signal signal)
 	hook_call_deferred(&ap_deferred_data, 0);
 }
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /* Initialize board. */
@@ -58,7 +59,12 @@ static void board_init(void)
 	/* Enable interrupt on PCH power signals */
 	gpio_enable_interrupt(GPIO_PCH_SLP_S3_L);
 	gpio_enable_interrupt(GPIO_PCH_SLP_S0_L);
-	/* enable the SPI slave interface if the PCH is up */
-	hook_call_deferred(&ap_deferred_data, 0);
+
+	/*
+	 * Enable the SPI peripheral interface if the PCH is up.
+	 * Do not use hook_call_deferred(), because ap_deferred() will be
+	 * called after tasks with priority higher than HOOK task (very late).
+	 */
+	ap_deferred();
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/nucleo-h743zi/board.h b/board/nucleo-h743zi/board.h
index 966f2a8c94..81cdd60fc9 100644
--- a/board/nucleo-h743zi/board.h
+++ b/board/nucleo-h743zi/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -28,6 +28,6 @@
  * Enable the blink example that exercises the LEDs.
  */
 #define CONFIG_BLINK
-#define CONFIG_BLINK_LEDS    GPIO_LED1, GPIO_LED2, GPIO_LED3
+#define CONFIG_BLINK_LEDS GPIO_LED1, GPIO_LED2, GPIO_LED3
 
 #endif /* __BOARD_H */
diff --git a/board/nucleo-h743zi/build.mk b/board/nucleo-h743zi/build.mk
index ebb8d6b18f..2785b30d30 100644
--- a/board/nucleo-h743zi/build.mk
+++ b/board/nucleo-h743zi/build.mk
@@ -1,4 +1,4 @@
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -10,20 +10,32 @@ board-y=board.o
 
 # Enable on device tests
 test-list-y=\
+       abort \
        aes \
+       boringssl \
        compile_time_macros \
-       crc32 \
+       crc \
+       debug \
+       exception \
        flash_physical \
        flash_write_protect \
+       libc_printf \
        mpu \
        mutex \
        pingpong \
+       printf \
+       queue \
+       rng_benchmark \
        rollback \
        rollback_entropy \
-       rsa \
        rsa3 \
        rtc \
+       sbrk \
        scratchpad \
        sha256 \
        sha256_unrolled \
+       static_if \
+       stdlib \
+       timer_dos \
        utils \
+       utils_str \
diff --git a/board/nucleo-h743zi/ec.tasklist b/board/nucleo-h743zi/ec.tasklist
index 9c37e0b58b..ed124cd672 100644
--- a/board/nucleo-h743zi/ec.tasklist
+++ b/board/nucleo-h743zi/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nucleo-h743zi/gpio.inc b/board/nucleo-h743zi/gpio.inc
index 0f2bb32d75..a93133abd7 100644
--- a/board/nucleo-h743zi/gpio.inc
+++ b/board/nucleo-h743zi/gpio.inc
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nuwani/battery.c b/board/nuwani/battery.c
index 5cbbeb5123..e24b442049 100644
--- a/board/nuwani/battery.c
+++ b/board/nuwani/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/nuwani/board.c b/board/nuwani/board.c
index 3b64396976..de2506d0a1 100644
--- a/board/nuwani/board.c
+++ b/board/nuwani/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,16 +10,18 @@
 #include "driver/accelgyro_bmi_common.h"
 #include "driver/accelgyro_lsm6dsm.h"
 #include "extpower.h"
+#include "gpio.h"
 #include "i2c.h"
 #include "lid_switch.h"
 #include "power.h"
 #include "power_button.h"
 #include "pwm.h"
-#include "system.h"
 #include "switch.h"
+#include "system.h"
 #include "tablet_mode.h"
 #include "task.h"
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 const enum gpio_signal hibernate_wake_pins[] = {
@@ -28,20 +30,38 @@ const enum gpio_signal hibernate_wake_pins[] = {
 	GPIO_POWER_BUTTON_L,
 	GPIO_EC_RST_ODL,
 };
-const int hibernate_wake_pins_used =  ARRAY_SIZE(hibernate_wake_pins);
+const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 
 /* I2C port map. */
 const struct i2c_port_t i2c_ports[] = {
-	{"power",   I2C_PORT_POWER,   100, GPIO_I2C0_SCL, GPIO_I2C0_SDA},
-	{"tcpc0",   I2C_PORT_TCPC0,   400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"tcpc1",   I2C_PORT_TCPC1,   400, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-	{"thermal", I2C_PORT_THERMAL_AP, 400, GPIO_I2C3_SCL, GPIO_I2C3_SDA},
-	{"sensor",  I2C_PORT_SENSOR,  400, GPIO_I2C7_SCL, GPIO_I2C7_SDA},
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_I2C0_SCL,
+	  .sda = GPIO_I2C0_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "tcpc1",
+	  .port = I2C_PORT_TCPC1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "thermal",
+	  .port = I2C_PORT_THERMAL_AP,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_I2C7_SCL,
+	  .sda = GPIO_I2C7_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
-#ifdef HAS_TASK_MOTIONSENSE
-
 /* Motion sensors */
 static struct mutex g_lid_mutex_1;
 static struct mutex g_base_mutex_1;
@@ -51,19 +71,15 @@ static struct stprivate_data g_lis2dwl_data;
 /* Base accel private data */
 static struct lsm6dsm_data g_lsm6dsm_data = LSM6DSM_DATA;
 
-
 /* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t lsm6dsm_base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lsm6dsm_base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+						      { 0, FLOAT_TO_FP(-1), 0 },
+						      { 0, 0,
+							FLOAT_TO_FP(1) } };
 
-static const mat33_fp_t treeya_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t treeya_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+						{ FLOAT_TO_FP(1), 0, 0 },
+						{ 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t lid_accel_1 = {
 	.name = "Lid Accel",
@@ -102,8 +118,6 @@ struct motion_sensor_t base_accel_1 = {
 	.mutex = &g_base_mutex_1,
 	.drv_data = LSM6DSM_ST_DATA(g_lsm6dsm_data,
 			MOTIONSENSE_TYPE_ACCEL),
-	.int_signal = GPIO_6AXIS_INT_L,
-	.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
 	.port = I2C_PORT_ACCEL,
 	.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
 	.rot_standard_ref = &lsm6dsm_base_standard_ref,
@@ -132,10 +146,7 @@ struct motion_sensor_t base_gyro_1 = {
 	.location = MOTIONSENSE_LOC_BASE,
 	.drv = &lsm6dsm_drv,
 	.mutex = &g_base_mutex_1,
-	.drv_data = LSM6DSM_ST_DATA(g_lsm6dsm_data,
-			MOTIONSENSE_TYPE_GYRO),
-	.int_signal = GPIO_6AXIS_INT_L,
-	.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
+	.drv_data = LSM6DSM_ST_DATA(g_lsm6dsm_data, MOTIONSENSE_TYPE_GYRO),
 	.port = I2C_PORT_ACCEL,
 	.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
 	.default_range = 1000 | ROUND_UP_FLAG, /* dps */
@@ -163,10 +174,12 @@ void board_update_sensor_config_from_sku(void)
 			motion_sensors[LID_ACCEL] = lid_accel_1;
 			motion_sensors[BASE_ACCEL] = base_accel_1;
 			motion_sensors[BASE_GYRO] = base_gyro_1;
-		} else{
+		} else {
 			/*Need to change matrix for treeya*/
-			motion_sensors[BASE_ACCEL].rot_standard_ref = &treeya_standard_ref;
-			motion_sensors[BASE_GYRO].rot_standard_ref = &treeya_standard_ref;
+			motion_sensors[BASE_ACCEL].rot_standard_ref =
+				&treeya_standard_ref;
+			motion_sensors[BASE_GYRO].rot_standard_ref =
+				&treeya_standard_ref;
 		}
 
 		/* Enable Gyro interrupts */
@@ -174,10 +187,9 @@ void board_update_sensor_config_from_sku(void)
 	} else {
 		motion_sensor_count = 0;
 		/* Device is clamshell only */
-		tablet_set_mode(0);
+		tablet_set_mode(0, TABLET_TRIGGER_LID);
 		/* Gyro is not present, don't allow line to float */
-		gpio_set_flags(GPIO_6AXIS_INT_L,
-			       GPIO_INPUT | GPIO_PULL_DOWN);
+		gpio_set_flags(GPIO_6AXIS_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
 	}
 }
 
@@ -189,5 +201,3 @@ void board_bmi160_lsm6dsm_interrupt(enum gpio_signal signal)
 	else
 		bmi160_interrupt(signal);
 }
-
-#endif
diff --git a/board/nuwani/board.h b/board/nuwani/board.h
index 17d16110a5..b58102efe7 100644
--- a/board/nuwani/board.h
+++ b/board/nuwani/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,14 +16,13 @@
  * By default, enable all console messages excepted HC, ACPI and event:
  * The sensor stack is generating a lot of activity.
  */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
 #undef CONFIG_HOSTCMD_DEBUG_MODE
 #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
 
 /* Power and battery LEDs */
 #define CONFIG_LED_COMMON
 #define CONFIG_CMD_LEDTEST
-#define CONFIG_LED_POWER_LED
 
 #define CONFIG_LED_ONOFF_STATES
 
@@ -37,7 +36,6 @@
 #define CONFIG_ACCELGYRO_BMI160
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCEL_INTERRUPTS
 #define CONFIG_ACCEL_KX022
 #define CONFIG_CMD_ACCELS
 #define CONFIG_CMD_ACCEL_INFO
@@ -49,7 +47,7 @@
 /*
  * Slew rate on the PP1800_SENSOR load switch requires a short delay on startup.
  */
-#undef  CONFIG_MOTION_SENSE_RESUME_DELAY_US
+#undef CONFIG_MOTION_SENSE_RESUME_DELAY_US
 #define CONFIG_MOTION_SENSE_RESUME_DELAY_US (10 * MSEC)
 
 /* Second set of sensor drivers */
@@ -60,7 +58,6 @@
 
 #ifndef __ASSEMBLER__
 
-
 enum battery_type {
 	BATTERY_SMP,
 	BATTERY_LGC,
diff --git a/board/nuwani/build.mk b/board/nuwani/build.mk
index 85b141b15d..c754c96237 100644
--- a/board/nuwani/build.mk
+++ b/board/nuwani/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/nuwani/ec.tasklist b/board/nuwani/ec.tasklist
index 2874dff927..c5db864fe5 100644
--- a/board/nuwani/ec.tasklist
+++ b/board/nuwani/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nuwani/gpio.inc b/board/nuwani/gpio.inc
index 18c72c8125..e01af85e34 100644
--- a/board/nuwani/gpio.inc
+++ b/board/nuwani/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nuwani/led.c b/board/nuwani/led.c
index 9298075157..f04a422592 100644
--- a/board/nuwani/led.c
+++ b/board/nuwani/led.c
@@ -1,51 +1,54 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "common.h"
-#include "led_onoff_states.h"
-#include "led_common.h"
 #include "gpio.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
-const int led_charge_lvl_1 = 5;
+__override const int led_charge_lvl_1 = 5;
 
-const int led_charge_lvl_2 = 97;
+__override const int led_charge_lvl_2 = 97;
 
-struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,  2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
 
-const struct led_descriptor
-			led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-				{LED_OFF,          0.5 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 3 * LED_ONE_SEC },
+					       { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-void led_set_color_power(enum ec_led_colors color)
+__override void led_set_color_power(enum ec_led_colors color)
 {
 	if (color == EC_LED_COLOR_WHITE)
 		gpio_set_level(GPIO_POWER_LED_3_L, LED_ON_LVL);
@@ -54,7 +57,7 @@ void led_set_color_power(enum ec_led_colors color)
 		gpio_set_level(GPIO_POWER_LED_3_L, LED_OFF_LVL);
 }
 
-void led_set_color_battery(enum ec_led_colors color)
+__override void led_set_color_battery(enum ec_led_colors color)
 {
 	switch (color) {
 	case EC_LED_COLOR_RED:
diff --git a/board/nuwani/vif_override.xml b/board/nuwani/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/nuwani/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/oak/battery.c b/board/oak/battery.c
index fffd2f7763..b9b410932d 100644
--- a/board/oak/battery.c
+++ b/board/oak/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,7 +11,7 @@
 #include "util.h"
 
 /* Shutdown mode parameter to write to manufacturer access register */
-#define PARAM_CUT_OFF_LOW  0x10
+#define PARAM_CUT_OFF_LOW 0x10
 #define PARAM_CUT_OFF_HIGH 0x00
 
 static const struct battery_info info = {
@@ -21,7 +21,7 @@ static const struct battery_info info = {
 	/*
 	 * TODO(crosbug.com/p/44428):
 	 * In order to compatible with 2S battery, set min voltage as 6V rather
-         * than 9V. Should set voltage_min to 9V, when 2S battery
+	 * than 9V. Should set voltage_min to 9V, when 2S battery
 	 * phased out.
 	 */
 	.voltage_min = 6000,
@@ -57,10 +57,10 @@ static int cutoff(void)
 	buf[2] = PARAM_CUT_OFF_HIGH;
 
 	i2c_lock(I2C_PORT_BATTERY, 1);
-	rv = i2c_xfer_unlocked(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS,
-			       buf, 3, NULL, 0, I2C_XFER_SINGLE);
-	rv |= i2c_xfer_unlocked(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS,
-				buf, 3, NULL, 0, I2C_XFER_SINGLE);
+	rv = i2c_xfer_unlocked(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS, buf, 3,
+			       NULL, 0, I2C_XFER_SINGLE);
+	rv |= i2c_xfer_unlocked(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS, buf, 3,
+				NULL, 0, I2C_XFER_SINGLE);
 	i2c_lock(I2C_PORT_BATTERY, 0);
 
 	return rv;
diff --git a/board/oak/board.c b/board/oak/board.c
index eb16c03ab1..f53d61cd9d 100644
--- a/board/oak/board.c
+++ b/board/oak/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,6 @@
 /* Oak board configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "als.h"
 #include "atomic.h"
 #include "battery.h"
@@ -53,34 +52,33 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* Dispaly port hardware can connect to port 0, 1 or neither. */
 #define PD_PORT_NONE -1
 
 void pd_mcu_interrupt(enum gpio_signal signal)
 {
-#ifdef HAS_TASK_PDCMD
 	/* Exchange status with PD MCU to determine interrupt cause */
 	host_command_pd_send_status(0);
-#endif
 }
 
 #if BOARD_REV >= OAK_REV4
 void usb_evt(enum gpio_signal signal)
 {
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_INTR, 0);
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_INTR, 0);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_INTR);
+	usb_charger_task_set_event(1, USB_CHG_EVENT_INTR);
 }
 #endif /* BOARD_REV >= OAK_REV4 */
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /* power signal list.  Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
-	{GPIO_SOC_POWER_GOOD, POWER_SIGNAL_ACTIVE_HIGH, "POWER_GOOD"},
-	{GPIO_SUSPEND_L, POWER_SIGNAL_ACTIVE_LOW, "SUSPEND#_ASSERTED"},
+	{ GPIO_SOC_POWER_GOOD, POWER_SIGNAL_ACTIVE_HIGH, "POWER_GOOD" },
+	{ GPIO_SUSPEND_L, POWER_SIGNAL_ACTIVE_LOW, "SUSPEND#_ASSERTED" },
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
@@ -90,27 +88,32 @@ const struct adc_t adc_channels[] = {
 	 * PSYS_MONITOR(PA2): ADC_IN2, 1.44 uA/W on 6.05k Ohm
 	 * output in mW
 	 */
-	[ADC_PSYS] = {"PSYS", 379415, 4096, 0, STM32_AIN(2)},
+	[ADC_PSYS] = { "PSYS", 379415, 4096, 0, STM32_AIN(2) },
 	/* AMON_BMON(PC0): ADC_IN10, output in uV */
-	[ADC_AMON_BMON] = {"AMON_BMON", 183333, 4096, 0, STM32_AIN(10)},
+	[ADC_AMON_BMON] = { "AMON_BMON", 183333, 4096, 0, STM32_AIN(10) },
 	/* VDC_BOOSTIN_SENSE(PC1): ADC_IN11, output in mV */
-	[ADC_VBUS] = {"VBUS", 33000, 4096, 0, STM32_AIN(11)},
+	[ADC_VBUS] = { "VBUS", 33000, 4096, 0, STM32_AIN(11) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"battery", I2C_PORT_BATTERY, 100,  GPIO_I2C0_SCL, GPIO_I2C0_SDA},
-	{"pd",      I2C_PORT_PD_MCU,  1000, GPIO_I2C1_SCL, GPIO_I2C1_SDA}
-};
+const struct i2c_port_t i2c_ports[] = { { .name = "battery",
+					  .port = I2C_PORT_BATTERY,
+					  .kbps = 100,
+					  .scl = GPIO_I2C0_SCL,
+					  .sda = GPIO_I2C0_SDA },
+					{ .name = "pd",
+					  .port = I2C_PORT_PD_MCU,
+					  .kbps = 1000,
+					  .scl = GPIO_I2C1_SCL,
+					  .sda = GPIO_I2C1_SDA } };
 
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
 #ifdef CONFIG_ACCELGYRO_BMI160
 /* SPI devices */
-const struct spi_device_t spi_devices[] = {
-	{ CONFIG_SPI_ACCEL_PORT, 1, GPIO_SPI2_NSS }
-};
+const struct spi_device_t spi_devices[] = { { CONFIG_SPI_ACCEL_PORT, 1,
+					      GPIO_SPI2_NSS } };
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 #endif
 
@@ -175,42 +178,47 @@ const struct charger_config_t chg_chips[] = {
  *     src/mainboard/google/${board}/acpi/dptf.asl
  */
 const struct temp_sensor_t temp_sensors[] = {
-	{"TMP432_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-		TMP432_IDX_LOCAL},
-	{"TMP432_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-		TMP432_IDX_REMOTE1},
-	{"TMP432_Sensor_2", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-		TMP432_IDX_REMOTE2},
-	{"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp,
-		0},
+	{ "TMP432_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
+	  TMP432_IDX_LOCAL },
+	{ "TMP432_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
+	  TMP432_IDX_REMOTE1 },
+	{ "TMP432_Sensor_2", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
+	  TMP432_IDX_REMOTE2 },
+	{ "Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
 #ifdef HAS_TASK_ALS
 /* ALS instances. Must be in same order as enum als_id. */
 struct als_t als[] = {
-	{"TI", opt3001_init, opt3001_read_lux, 5},
+	{ "TI", opt3001_init, opt3001_read_lux, 5 },
 };
 BUILD_ASSERT(ARRAY_SIZE(als) == ALS_COUNT);
 #endif
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
-		.driver    = &pi3usb3x532_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX,
+				.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
+				.driver = &pi3usb3x532_usb_mux_driver,
+			},
 	},
 	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_USB_MUX,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_USB_MUX,
 #if (BOARD_REV <= OAK_REV4)
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR1,
-		.driver    = &pi3usb3x532_usb_mux_driver,
+				.i2c_addr_flags = PI3USB3X532_I2C_ADDR1,
+				.driver = &pi3usb3x532_usb_mux_driver,
 #else
-		.i2c_addr_flags = 0x10,
-		.driver = &ps8740_usb_mux_driver,
+				.i2c_addr_flags = 0x10,
+				.driver = &ps8740_usb_mux_driver,
 #endif
+			},
 	},
 };
 
@@ -281,7 +289,7 @@ static void board_init(void)
 	STM32_DMA_CSELR(STM32_DMAC_CH6) |= (3 << 20) | (3 << 24);
 
 	/* Enable SPI for BMI160 */
-	gpio_config_module(MODULE_SPI_MASTER, 1);
+	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
 
 	/* Set all four SPI pins to high speed */
 	/* pins D0/D1/D3/D4 */
@@ -294,7 +302,7 @@ static void board_init(void)
 	STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2;
 	STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
 
-	spi_enable(CONFIG_SPI_ACCEL_PORT, 1);
+	spi_enable(&spi_devices[0], 1);
 	CPRINTS("Board using SPI sensors");
 #endif
 }
@@ -331,10 +339,12 @@ int board_set_active_charge_port(int charge_port)
 	} else {
 		/* Make sure non-charging port is disabled */
 		gpio_set_level(charge_port ? GPIO_USB_C0_CHARGE_L :
-					     GPIO_USB_C1_CHARGE_L, 1);
+					     GPIO_USB_C1_CHARGE_L,
+			       1);
 		/* Enable charging port */
 		gpio_set_level(charge_port ? GPIO_USB_C1_CHARGE_L :
-					     GPIO_USB_C0_CHARGE_L, 0);
+					     GPIO_USB_C0_CHARGE_L,
+			       0);
 	}
 
 	return EC_SUCCESS;
@@ -348,11 +358,10 @@ int board_set_active_charge_port(int charge_port)
  * @param charge_ma     Desired charge limit (mA).
  * @param charge_mv     Negotiated charge voltage (mV).
  */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
 {
-	charge_set_input_current_limit(MAX(charge_ma,
-				   CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+	charge_set_input_current_limit(charge_ma, charge_mv);
 	pd_send_host_event(PD_EVENT_POWER_CHANGE);
 }
 
@@ -543,9 +552,8 @@ void vbus_task(void *u)
 			}
 
 			if (wake)
-				task_set_event(port ? TASK_ID_USB_CHG_P1 :
-						      TASK_ID_USB_CHG_P0,
-					       USB_CHG_EVENT_BC12, 0);
+				usb_charger_task_set_event(port,
+							   USB_CHG_EVENT_BC12);
 		}
 		task_wait_event(-1);
 	}
@@ -561,15 +569,15 @@ void vbus_task(void *u)
 #ifdef CONFIG_TEMP_SENSOR_TMP432
 static void tmp432_set_power_deferred(void)
 {
-       /* Shut tmp432 down if not in S0 && no external power */
-       if (!extpower_is_present() && !chipset_in_state(CHIPSET_STATE_ON)) {
-               if (EC_SUCCESS != tmp432_set_power(TMP432_POWER_OFF))
+	/* Shut tmp432 down if not in S0 && no external power */
+	if (!extpower_is_present() && !chipset_in_state(CHIPSET_STATE_ON)) {
+		if (EC_SUCCESS != tmp432_set_power(TMP432_POWER_OFF))
 			CPRINTS("ERROR: Can't shutdown TMP432.");
-               return;
-       }
+		return;
+	}
 
-       /*  else, turn it on. */
-       if (EC_SUCCESS != tmp432_set_power(TMP432_POWER_ON))
+	/*  else, turn it on. */
+	if (EC_SUCCESS != tmp432_set_power(TMP432_POWER_ON))
 		CPRINTS("ERROR: Can't turn on TMP432.");
 }
 DECLARE_DEFERRED(tmp432_set_power_deferred);
@@ -594,7 +602,7 @@ static void board_chipset_pre_init(void)
 	board_extpower_buffer_to_soc();
 #if BOARD_REV >= OAK_REV5
 	/* Enable DP muxer */
-	gpio_set_level(GPIO_DP_MUX_EN_L , 0);
+	gpio_set_level(GPIO_DP_MUX_EN_L, 0);
 	gpio_set_level(GPIO_PARADE_MUX_EN, 1);
 #endif
 }
@@ -607,13 +615,12 @@ static void board_chipset_shutdown(void)
 	gpio_set_level(GPIO_LEVEL_SHIFT_EN_L, 1);
 #if BOARD_REV >= OAK_REV5
 	/* Disable DP muxer */
-	gpio_set_level(GPIO_DP_MUX_EN_L , 1);
+	gpio_set_level(GPIO_DP_MUX_EN_L, 1);
 	gpio_set_level(GPIO_PARADE_MUX_EN, 0);
 #endif
 }
 DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
 
-
 /* Called on AP S3 -> S0 transition */
 static void board_chipset_resume(void)
 {
@@ -642,11 +649,9 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0,  0},
-	{ 0, FLOAT_TO_FP(-1),  0},
-	{ 0,  0,  FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				       { 0, FLOAT_TO_FP(-1), 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
 #endif
 
 static struct kionix_accel_data g_kx022_data;
@@ -669,7 +674,7 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_base_mutex,
 		.drv_data = &g_bmi160_data,
 		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = SLAVE_MK_SPI_ADDR_FLAGS(0),
+		.i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(0),
 		.rot_standard_ref = &base_standard_ref,
 		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
 		.min_frequency = BMI_ACCEL_MIN_FREQ,
@@ -693,7 +698,7 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_base_mutex,
 		.drv_data = &g_bmi160_data,
 		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = SLAVE_MK_SPI_ADDR_FLAGS(0),
+		.i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(0),
 		.default_range = 1000, /* dps */
 		.rot_standard_ref = &base_standard_ref,
 		.min_frequency = BMI_GYRO_MIN_FREQ,
@@ -728,7 +733,7 @@ struct motion_sensor_t motion_sensors[] = {
 };
 const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
-void lid_angle_peripheral_enable(int enable)
+__override void lid_angle_peripheral_enable(int enable)
 {
 	keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
 }
diff --git a/board/oak/board.h b/board/oak/board.h
index d959763853..c429a655c5 100644
--- a/board/oak/board.h
+++ b/board/oak/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,17 +11,20 @@
 /* board revision */
 #include "board_revs.h"
 
+/* Free up some flash space */
+#define CONFIG_DEBUG_ASSERT_BRIEF
+#define CONFIG_USB_PD_DEBUG_LEVEL 0
+#undef CONFIG_CONSOLE_CMDHELP
+
 #define CONFIG_LTO
 
 #if BOARD_REV >= OAK_REV5
 #define CONFIG_ACCELGYRO_BMI160
 #define CONFIG_ACCEL_KX022
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
 #endif
 
 #define CONFIG_ADC
-#undef  CONFIG_ADC_WATCHDOG
+#undef CONFIG_ADC_WATCHDOG
 
 #if BOARD_REV >= OAK_REV5
 /* Add for Ambient Light Sensor */
@@ -37,7 +40,8 @@
 #define CONFIG_CHARGE_MANAGER
 #define CONFIG_CHARGER
 
-#define CONFIG_CHARGER_INPUT_CURRENT 512
+#define CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT 512
+#define CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT 512
 
 #if BOARD_REV == OAK_REV1
 #define CONFIG_CHARGER_BQ24773
@@ -57,7 +61,6 @@
 #define CONFIG_CMD_TYPEC
 #define CONFIG_EXTPOWER_GPIO
 #define CONFIG_FORCE_CONSOLE_RESUME
-#define CONFIG_CMD_CHARGER_ADC_AMON_BMON
 
 /*
  * EC_WAKE: PA0 - WKUP1
@@ -77,7 +80,7 @@
 #define CONFIG_HOSTCMD_PD
 #define CONFIG_HOSTCMD_PD_PANIC
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_CONTROLLER
 #define CONFIG_KEYBOARD_COL2_INVERTED
 #define CONFIG_KEYBOARD_PROTOCOL_MKBP
 #define CONFIG_LED_COMMON
@@ -103,13 +106,12 @@
 #define CONFIG_USB_PD_TRY_SRC
 #define CONFIG_USB_PD_VBUS_DETECT_TCPC
 #define CONFIG_SPI
-#define CONFIG_SPI_MASTER
-#define CONFIG_STM_HWTIMER32
+#define CONFIG_SPI_CONTROLLER
 #define CONFIG_VBOOT_HASH
-#undef  CONFIG_WATCHDOG_HELP
+#undef CONFIG_WATCHDOG_HELP
 #define CONFIG_SWITCH
 #define CONFIG_BOARD_VERSION_GPIO
-#undef  CONFIG_UART_CONSOLE
+#undef CONFIG_UART_CONSOLE
 #define CONFIG_UART_CONSOLE 1
 #define CONFIG_TEMP_SENSOR
 #define CONFIG_TEMP_SENSOR_TMP432
@@ -127,6 +129,7 @@
 
 /* Optional features */
 #define CONFIG_CMD_HOSTCMD
+#undef CONFIG_CMD_MFALLOW
 
 /* Drivers */
 /* USB Mux */
@@ -147,19 +150,19 @@
 #define KB_OUT_PORT_LIST GPIO_A, GPIO_B, GPIO_C, GPIO_D
 
 /* 2 I2C master ports, connect to battery, charger, pd and USB switches */
-#define I2C_PORT_MASTER  0
-#define I2C_PORT_ACCEL   0
-#define I2C_PORT_ALS     0
+#define I2C_PORT_MASTER 0
+#define I2C_PORT_ACCEL 0
+#define I2C_PORT_ALS 0
 #define I2C_PORT_BATTERY 0
 #define I2C_PORT_CHARGER 0
 #define I2C_PORT_PERICOM 0
 #define I2C_PORT_THERMAL 0
-#define I2C_PORT_PD_MCU  1
+#define I2C_PORT_PD_MCU 1
 #define I2C_PORT_USB_MUX 1
-#define I2C_PORT_TCPC    1
+#define I2C_PORT_TCPC 1
 
 /* Enable Accel over SPI */
-#define CONFIG_SPI_ACCEL_PORT    0  /* First SPI master port (SPI2) */
+#define CONFIG_SPI_ACCEL_PORT 0 /* First SPI controller port (SPI2) */
 
 /* Ambient Light Sensor address */
 #define OPT3001_I2C_ADDR_FLAGS OPT3001_I2C_ADDR1_FLAGS
@@ -169,12 +172,12 @@
 #define TIM_WATCHDOG 4
 
 /* Define the host events which are allowed to wakeup AP in S3. */
-#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \
-		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_FASTBOOT))
+#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK                     \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |          \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |      \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |       \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_FASTBOOT))
 
 #include "gpio_signal.h"
 
@@ -192,9 +195,9 @@ enum pwm_channel {
 };
 
 enum adc_channel {
-	ADC_PSYS = 0,  /* PC1: STM32_AIN(2) */
+	ADC_PSYS = 0, /* PC1: STM32_AIN(2) */
 	ADC_AMON_BMON, /* PC0: STM32_AIN(10) */
-	ADC_VBUS,      /* PA2: STM32_AIN(11) */
+	ADC_VBUS, /* PA2: STM32_AIN(11) */
 	ADC_CH_COUNT
 };
 
@@ -233,17 +236,16 @@ enum als_id {
  * delay to turn on the power supply max is ~16ms.
  * delay to turn off the power supply max is about ~180ms.
  */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* delay to turn on/off vconn */
-#define PD_VCONN_SWAP_DELAY 5000 /* us */
 
 /* Define typical operating power and max power */
 #define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       60000
-#define PD_MAX_CURRENT_MA     CONFIG_CHARGER_MAX_INPUT_CURRENT
-#define PD_MAX_VOLTAGE_MV     20000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA CONFIG_CHARGER_MAX_INPUT_CURRENT
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Reset PD MCU */
 void board_reset_pd_mcu(void);
@@ -255,6 +257,6 @@ void board_typec_dp_on(int port);
 void board_typec_dp_off(int port, int *dp_flags);
 void board_typec_dp_set(int port, int level);
 
-#endif  /* !__ASSEMBLER__ */
+#endif /* !__ASSEMBLER__ */
 
-#endif  /* __CROS_EC_BOARD_H */
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/oak/board_revs.h b/board/oak/board_revs.h
index 34fc4bfc88..6220a05fb0 100644
--- a/board/oak/board_revs.h
+++ b/board/oak/board_revs.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,7 +12,7 @@
 #define OAK_REV3 3
 #define OAK_REV4 4
 #define OAK_REV5 5
-#define OAK_REV_LAST    OAK_REV5
+#define OAK_REV_LAST OAK_REV5
 #define OAK_REV_DEFAULT OAK_REV5
 
 #if !defined(BOARD_REV)
diff --git a/board/oak/build.mk b/board/oak/build.mk
index dc21970df0..1cbbb2ac63 100644
--- a/board/oak/build.mk
+++ b/board/oak/build.mk
@@ -1,5 +1,5 @@
 #-*- makefile -*-
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/oak/ec.tasklist b/board/oak/ec.tasklist
index 2af7da77eb..80c39f2617 100644
--- a/board/oak/ec.tasklist
+++ b/board/oak/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/oak/gpio.inc b/board/oak/gpio.inc
index 70bb3a7bba..b2ce008363 100644
--- a/board/oak/gpio.inc
+++ b/board/oak/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -210,5 +210,5 @@ ALTERNATE(PIN_MASK(B, 0x00c0), 1, MODULE_I2C,        0) /* I2C MASTER:PB6/7 */
 ALTERNATE(PIN_MASK(B, 0x6000), 5, MODULE_I2C,        0) /* I2C MASTER:PB13/14 */
 ALTERNATE(PIN_MASK(A, 0x00f0), 0, MODULE_SPI,        0) /* SPI SLAVE:PA4/5/6/7 */
 #if BOARD_REV >= OAK_REV5
-ALTERNATE(PIN_MASK(D, 0x001A), 1, MODULE_SPI_MASTER, 0) /* SPI MASTER:PD1/3/4 */
+ALTERNATE(PIN_MASK(D, 0x001A), 1, MODULE_SPI_CONTROLLER, 0) /* SPI MASTER:PD1/3/4 */
 #endif
diff --git a/board/oak/led.c b/board/oak/led.c
index 877f115a12..ac7d78118b 100644
--- a/board/oak/led.c
+++ b/board/oak/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,12 +11,10 @@
 #include "gpio.h"
 #include "hooks.h"
 #include "led_common.h"
-#include "util.h"
 #include "system.h"
+#include "util.h"
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -27,7 +25,7 @@ enum led_color {
 	BAT_LED_AMBER,
 	PWR_LED_GREEN,
 	PWR_LED_ORANGE,
-	LED_COLOR_COUNT		/* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static int bat_led_set(enum led_color color, int on)
@@ -113,7 +111,7 @@ static void oak_led_set_power(int board_version)
 
 	power_second++;
 
-	switch(board_version) {
+	switch (board_version) {
 	case OAK_REV3:
 	case OAK_REV4:
 		/*
@@ -131,8 +129,7 @@ static void oak_led_set_power(int board_version)
 			bat_led_set(PWR_LED_ORANGE, 0);
 		} else if (chipset_in_state(CHIPSET_STATE_SUSPEND)) {
 			bat_led_set(PWR_LED_GREEN, 0);
-			bat_led_set(PWR_LED_ORANGE,
-				    (power_second & 3) ? 0 : 1);
+			bat_led_set(PWR_LED_ORANGE, (power_second & 3) ? 0 : 1);
 		}
 		break;
 	default:
@@ -146,7 +143,7 @@ static void oak_led_set_battery(int board_version)
 
 	battery_second++;
 
-	switch(board_version) {
+	switch (board_version) {
 	case OAK_REV3:
 	case OAK_REV4:
 		/*
@@ -157,29 +154,29 @@ static void oak_led_set_battery(int board_version)
 		 * - Battery discharging capacity<10%, red blink
 		 * - Battery error: Red ON
 		 */
-		switch (charge_get_state()) {
-		case PWR_STATE_CHARGE:
+		switch (led_pwr_get_state()) {
+		case LED_PWRS_CHARGE:
 			bat_led_set(BAT_LED_AMBER, 1);
 			break;
-		case PWR_STATE_CHARGE_NEAR_FULL:
+		case LED_PWRS_CHARGE_NEAR_FULL:
 			bat_led_set(BAT_LED_GREEN, 1);
 			bat_led_set(BAT_LED_RED, 0);
 			break;
-		case PWR_STATE_DISCHARGE:
+		case LED_PWRS_DISCHARGE:
 			bat_led_set(BAT_LED_GREEN, 0);
 			if (charge_get_percent() < 3)
 				bat_led_set(BAT_LED_RED,
-					  (battery_second & 1) ? 0 : 1);
+					    (battery_second & 1) ? 0 : 1);
 			else if (charge_get_percent() < 10)
 				bat_led_set(BAT_LED_RED,
-					  (battery_second & 3) ? 0 : 1);
+					    (battery_second & 3) ? 0 : 1);
 			else
 				bat_led_set(BAT_LED_RED, 0);
 			break;
-		case PWR_STATE_ERROR:
+		case LED_PWRS_ERROR:
 			bat_led_set(BAT_LED_RED, 1);
 			break;
-		case PWR_STATE_IDLE: /* Ext. power connected in IDLE. */
+		case LED_PWRS_IDLE: /* Ext. power connected in IDLE. */
 			bat_led_set(BAT_LED_GREEN, 1);
 			bat_led_set(BAT_LED_RED, 0);
 			break;
@@ -191,7 +188,8 @@ static void oak_led_set_battery(int board_version)
 	default:
 		/*
 		 * Put power control here since we are using the "battery" LED.
-		 * This allows LED autocontrol to be turned off by cmd during factory test.
+		 * This allows LED autocontrol to be turned off by cmd during
+		 * factory test.
 		 *
 		 * PWR LED behavior:
 		 * Power on: Green
@@ -205,8 +203,8 @@ static void oak_led_set_battery(int board_version)
 		else if (chipset_in_state(CHIPSET_STATE_SUSPEND)) {
 			int cycle_time = 4;
 			/* Oak rev5 with GlaDOS ID has a extremely power
-			 * comsuming LED. Increase LED blink cycle time to reduce
-			 * S3 power comsuption. */
+			 * comsuming LED. Increase LED blink cycle time to
+			 * reduce S3 power comsuption. */
 			if (board_version >= OAK_REV5)
 				cycle_time = 10;
 			bat_led_set(BAT_LED_GREEN,
@@ -221,28 +219,28 @@ static void oak_led_set_battery(int board_version)
 		 *   situation: Orange in blinking mode (1s on, 1s off)
 		 * Using battery or not connected to AC power: OFF
 		 */
-		switch (charge_get_state()) {
-		case PWR_STATE_CHARGE:
+		switch (led_pwr_get_state()) {
+		case LED_PWRS_CHARGE:
 			bat_led_set(BAT_LED_ORANGE, 1);
 			break;
-		case PWR_STATE_CHARGE_NEAR_FULL:
+		case LED_PWRS_CHARGE_NEAR_FULL:
 			bat_led_set(BAT_LED_ORANGE, 1);
 			break;
-		case PWR_STATE_DISCHARGE:
+		case LED_PWRS_DISCHARGE:
 			if (charge_get_percent() < 3)
 				bat_led_set(BAT_LED_ORANGE,
-					  (battery_second & 1) ? 0 : 1);
+					    (battery_second & 1) ? 0 : 1);
 			else if (charge_get_percent() < 10)
 				bat_led_set(BAT_LED_ORANGE,
-					  (battery_second & 3) ? 0 : 1);
+					    (battery_second & 3) ? 0 : 1);
 			else
 				bat_led_set(BAT_LED_ORANGE, 0);
 			break;
-		case PWR_STATE_ERROR:
+		case LED_PWRS_ERROR:
 			bat_led_set(BAT_LED_ORANGE,
 				    (battery_second & 1) ? 0 : 1);
 			break;
-		case PWR_STATE_IDLE: /* Ext. power connected in IDLE. */
+		case LED_PWRS_IDLE: /* Ext. power connected in IDLE. */
 			bat_led_set(BAT_LED_ORANGE, 0);
 			break;
 		default:
diff --git a/board/oak/usb_pd_policy.c b/board/oak/usb_pd_policy.c
index bf2fca3f49..2419927c17 100644
--- a/board/oak/usb_pd_policy.c
+++ b/board/oak/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,21 +14,19 @@
 #include "system.h"
 #include "task.h"
 #include "timer.h"
-#include "util.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
+#include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_set_power_supply_ready(int port)
 {
 	/* Disable charging */
-	gpio_set_level(port ? GPIO_USB_C1_CHARGE_L :
-			      GPIO_USB_C0_CHARGE_L, 1);
+	gpio_set_level(port ? GPIO_USB_C1_CHARGE_L : GPIO_USB_C0_CHARGE_L, 1);
 	/* Provide VBUS */
-	gpio_set_level(port ? GPIO_USB_C1_5V_EN :
-			      GPIO_USB_C0_5V_EN, 1);
+	gpio_set_level(port ? GPIO_USB_C1_5V_EN : GPIO_USB_C0_5V_EN, 1);
 
 	/* notify host of power info change */
 	pd_send_host_event(PD_EVENT_POWER_CHANGE);
@@ -39,8 +37,7 @@ int pd_set_power_supply_ready(int port)
 void pd_power_supply_reset(int port)
 {
 	/* Disable VBUS */
-	gpio_set_level(port ? GPIO_USB_C1_5V_EN :
-			      GPIO_USB_C0_5V_EN, 0);
+	gpio_set_level(port ? GPIO_USB_C1_5V_EN : GPIO_USB_C0_5V_EN, 0);
 
 	/* notify host of power info change */
 	pd_send_host_event(PD_EVENT_POWER_CHANGE);
@@ -101,7 +98,6 @@ __override int svdm_dp_attention(int port, uint32_t *payload)
 
 __override void svdm_exit_dp_mode(int port)
 {
-	svdm_safe_dp_mode(port);
 	board_typec_dp_off(port, dp_flags);
 }
 #endif /* CONFIG_USB_PD_ALT_MODE_DFP */
diff --git a/board/oak/vif_override.xml b/board/oak/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/oak/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/omnigul/battery.c b/board/omnigul/battery.c
new file mode 100644
index 0000000000..0fae9dbe56
--- /dev/null
+++ b/board/omnigul/battery.c
@@ -0,0 +1,111 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "cbi.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "gpio.h"
+/*
+ * Battery info for all Brya battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	/* LGC AP19B8M Battery Information */
+	/*
+	 * Battery info provided by ODM on b/263691095, comment #2
+	 */
+	[BATTERY_AP19B8M] = {
+		.fuel_gauge = {
+			.manuf_name = "LGC KT0030G024",
+			.device_name = "AP19B8M",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.reg_addr = 0x43,
+				.reg_mask = 0x0003,	/* D-FET C-FET */
+				.disconnect_val = 0x0000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13350,
+			.voltage_normal		= 11610, /* mV */
+			.voltage_min		= 9000, /* mV */
+			.precharge_current	= 256,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 75,
+		},
+	},
+	/* COSMX AP20CBL Battery Information */
+	/*
+	 * Battery info provided by ODM on b/263691095, comment #2
+	 */
+	[BATTERY_AP20CBL] = {
+		.fuel_gauge = {
+			.manuf_name = "COSMX KT0030B004",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,	/* D-FET C-FET */
+				.disconnect_val = 0x0000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13200,
+			.voltage_normal		= 11550, /* mV */
+			.voltage_min		= 9000, /* mV */
+			.precharge_current	= 256,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 75,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_AP19B8M;
+
+enum battery_present battery_hw_present(void)
+{
+	enum gpio_signal batt_pres;
+
+	batt_pres = GPIO_EC_BATT_PRES_ODL;
+
+	/* The GPIO is low when the battery is physically present */
+	return gpio_get_level(batt_pres) ? BP_NO : BP_YES;
+}
diff --git a/board/omnigul/board.c b/board/omnigul/board.c
new file mode 100644
index 0000000000..0c963416f2
--- /dev/null
+++ b/board/omnigul/board.c
@@ -0,0 +1,50 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "button.h"
+#include "charger.h"
+#include "common.h"
+#include "console.h"
+#include "driver/accel_lis2dw12.h"
+#include "driver/accelgyro_lsm6dso.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "registers.h"
+#include "switch.h"
+#include "tablet_mode.h"
+#include "throttle_ap.h"
+#include "usbc_config.h"
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* Console output macros */
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+
+/* Called on AP S3 -> S0 transition */
+static void board_chipset_resume(void)
+{
+	/* Allow keyboard backlight to be enabled */
+
+	if (IS_ENABLED(CONFIG_PWM_KBLIGHT))
+		gpio_set_level(GPIO_EC_KB_BL_EN_L, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S0 -> S3 transition */
+static void board_chipset_suspend(void)
+{
+	/* Turn off the keyboard backlight if it's on. */
+
+	if (IS_ENABLED(CONFIG_PWM_KBLIGHT))
+		gpio_set_level(GPIO_EC_KB_BL_EN_L, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
diff --git a/board/omnigul/board.h b/board/omnigul/board.h
new file mode 100644
index 0000000000..f9d6f841a9
--- /dev/null
+++ b/board/omnigul/board.h
@@ -0,0 +1,255 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Brya board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "compile_time_macros.h"
+
+/*
+ * Early brya boards are not set up for vivaldi
+ */
+#undef CONFIG_KEYBOARD_VIVALDI
+
+/* Baseboard features */
+#include "baseboard.h"
+
+/*
+ * This will happen automatically on NPCX9 ES2 and later. Do not remove
+ * until we can confirm all earlier chips are out of service.
+ */
+#define CONFIG_HIBERNATE_PSL_VCC1_RST_WAKEUP
+
+#define CONFIG_MP2964
+
+/* LED */
+#define CONFIG_LED_PWM
+#define CONFIG_LED_PWM_COUNT 1
+#undef CONFIG_LED_PWM_NEAR_FULL_COLOR
+#undef CONFIG_LED_PWM_SOC_ON_COLOR
+#undef CONFIG_LED_PWM_SOC_SUSPEND_COLOR
+#undef CONFIG_LED_PWM_LOW_BATT_COLOR
+#undef CONFIG_LED_PWM_CHARGE_ERROR_COLOR
+#undef LED_CHARGER_ERROR_ON_TIME
+#undef LED_CHARGER_ERROR_PERIOD
+#define CONFIG_LED_PWM_NEAR_FULL_COLOR EC_LED_COLOR_BLUE
+#define CONFIG_LED_PWM_SOC_ON_COLOR EC_LED_COLOR_BLUE
+#define CONFIG_LED_PWM_SOC_SUSPEND_COLOR EC_LED_COLOR_AMBER
+#define CONFIG_LED_PWM_LOW_BATT_COLOR EC_LED_COLOR_AMBER
+#define CONFIG_LED_PWM_CHARGE_ERROR_COLOR EC_LED_COLOR_AMBER
+#define LED_CHARGER_ERROR_ON_TIME 5
+#define LED_CHARGER_ERROR_PERIOD 10
+
+/* Sensors */
+#define CONFIG_ACCELGYRO_LSM6DSO /* Base accel */
+#define CONFIG_ACCEL_LSM6DSO_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+/* Enable sensor fifo, must also define the _SIZE and _THRES */
+#define CONFIG_ACCEL_FIFO
+/* FIFO size is in power of 2. */
+#define CONFIG_ACCEL_FIFO_SIZE 256
+/* Depends on how fast the AP boots and typical ODRs */
+#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
+
+/* Lid accel */
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_UPDATE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+#define CONFIG_ACCEL_LIS2DWL
+#define CONFIG_ACCEL_LIS2DW12_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
+
+/* Sensor console commands */
+#define CONFIG_CMD_ACCELS
+#define CONFIG_CMD_ACCEL_INFO
+
+/* USB Type A Features */
+#define USB_PORT_COUNT 1
+#define CONFIG_USB_PORT_POWER_DUMB
+
+/* USB Type C and USB PD defines */
+#define CONFIG_IO_EXPANDER
+#define CONFIG_IO_EXPANDER_NCT38XX
+#define CONFIG_IO_EXPANDER_PORT_COUNT 1
+
+#define CONFIG_USB_PD_FRS_PPC
+
+#define CONFIG_USB_PD_TCPM_PS8815
+#define CONFIG_USB_PD_TCPM_PS8815_FORCE_DID
+#undef CONFIG_USB_CHARGER
+#undef CONFIG_BC12_DETECT_PI3USB9201
+
+#define CONFIG_USB_PD_COMM_LOCKED
+
+/* I2C speed console command */
+#define CONFIG_CMD_I2C_SPEED
+
+/* I2C control host command */
+#define CONFIG_HOSTCMD_I2C_CONTROL
+
+#define CONFIG_USBC_PPC_SYV682X
+#define CONFIG_USBC_PPC_NX20P3483
+
+/* TODO: b/177608416 - measure and check these values on brya */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
+
+/*
+ * Passive USB-C cables only support up to 65W.
+ */
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 65000
+#define PD_MAX_CURRENT_MA 3250
+#define PD_MAX_VOLTAGE_MV 20000
+
+/*
+ * Because of b:279526032, modify monitor Vbus from Charger to TCPC.
+ */
+#undef CONFIG_USB_PD_VBUS_MEASURE_CHARGER
+#define CONFIG_USB_PD_VBUS_MEASURE_TCPC
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
+
+/*
+ * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
+ * signal.
+ */
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
+
+/* System has back-lit keyboard */
+#define CONFIG_PWM_KBLIGHT
+
+/* I2C Bus Configuration */
+
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+
+#define I2C_PORT_USB_C0_TCPC NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1
+
+#define I2C_PORT_USB_C0_PPC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1
+
+#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1
+
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+
+#define I2C_ADDR_MP2964_FLAGS 0x20
+
+/*
+ * see b/174768555#comment22
+ */
+#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x56
+#define USBC_PORT_C2_BB_RETIMER_I2C_ADDR 0x57
+
+/* Retimer */
+#define CONFIG_USBC_RETIMER_FW_UPDATE
+
+/* Thermal features */
+#define CONFIG_THERMISTOR
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_TEMP_SENSOR_POWER
+#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
+
+#define CONFIG_FANS FAN_CH_COUNT
+#define RPM_DEVIATION 2
+
+/* Charger defines */
+#define CONFIG_CHARGER_ISL9241
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 10
+
+/* KEYBOARD */
+#define CONFIG_KEYBOARD_CUSTOMIZATION
+#define CONFIG_KEYBOARD_VIVALDI
+#define CONFIG_KEYBOARD_REFRESH_ROW3
+
+/* DISABLE POWERINDEBUG */
+#undef CONFIG_CMD_POWERINDEBUG
+
+/*
+ * Older boards have a different ADC assignment.
+ */
+
+#define CONFIG_ADC_CHANNELS_RUNTIME_CONFIG
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h" /* needed by registers.h */
+#include "registers.h"
+#include "usbc_config.h"
+
+enum adc_channel {
+	ADC_TEMP_SENSOR_1_DDR_SOC,
+	ADC_TEMP_SENSOR_2_AMBIENT,
+	ADC_TEMP_SENSOR_3_CHARGER,
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1_DDR_SOC,
+	TEMP_SENSOR_2_AMBIENT,
+	TEMP_SENSOR_3_CHARGER,
+	TEMP_SENSOR_COUNT
+};
+
+enum sensor_id { LID_ACCEL = 0, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
+
+enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_C2_NCT38XX, IOEX_PORT_COUNT };
+
+enum battery_type { BATTERY_AP19B8M, BATTERY_AP20CBL, BATTERY_TYPE_COUNT };
+
+enum pwm_channel {
+	PWM_CH_LED2 = 0, /* PWM0 (white charger) */
+	PWM_CH_LED1, /* PWM2 (orange charger) */
+	PWM_CH_KBLIGHT, /* PWM3 */
+	PWM_CH_FAN, /* PWM5 */
+	PWM_CH_COUNT
+};
+
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT };
+
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT };
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/omnigul/build.mk b/board/omnigul/build.mk
new file mode 100644
index 0000000000..d8488c6b9d
--- /dev/null
+++ b/board/omnigul/build.mk
@@ -0,0 +1,26 @@
+# -*- makefile -*-
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Brya board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx9
+CHIP_VARIANT:=npcx9m3f
+BASEBOARD:=brya
+
+board-y=
+board-y+=battery.o
+board-y+=board.o
+board-y+=charger.o
+board-y+=fans.o
+board-y+=fw_config.o
+board-y+=i2c.o
+board-y+=keyboard.o
+board-y+=led.o
+board-y+=pwm.o
+board-y+=sensors.o
+board-y+=usbc_config.o
+board-y+=keyboard_customization.o
diff --git a/board/omnigul/charger.c b/board/omnigul/charger.c
new file mode 100644
index 0000000000..b3ca8dc104
--- /dev/null
+++ b/board/omnigul/charger.c
@@ -0,0 +1,82 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/charger/isl9241.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+#ifndef CONFIG_ZEPHYR
+/* Charger Chip Configuration */
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = ISL9241_ADDR_FLAGS,
+		.drv = &isl9241_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CHARGER_NUM);
+#endif
+
+int board_set_active_charge_port(int port)
+{
+	int is_valid_port = board_is_usb_pd_port_present(port);
+	int i;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTSUSB("Disabling all charger ports");
+
+		/* Disable all ports. */
+		for (i = 0; i < ppc_cnt; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (ppc_vbus_sink_enable(i, 0))
+				CPRINTSUSB("Disabling C%d as sink failed.", i);
+		}
+
+		return EC_SUCCESS;
+	} else if (!is_valid_port) {
+		return EC_ERROR_INVAL;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (ppc_is_sourcing_vbus(port)) {
+		CPRINTFUSB("Skip enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTSUSB("New charge port: C%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < ppc_cnt; i++) {
+		if (i == port)
+			continue;
+
+		if (ppc_vbus_sink_enable(i, 0))
+			CPRINTSUSB("C%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTSUSB("C%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/board/omnigul/ec.tasklist b/board/omnigul/ec.tasklist
new file mode 100644
index 0000000000..c2ef5f48cc
--- /dev/null
+++ b/board/omnigul/ec.tasklist
@@ -0,0 +1,27 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ *
+ * USB_CHG_Px tasks must be contiguous (see USB_CHG_PORT_TO_TASK_ID(x)).
+ * PD_Cx tasks must be contiguous (see PD_PORT_TO_TASK_ID(x))
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, HOOKS_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, BASEBOARD_CHARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, BASEBOARD_CHIPSET_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, CONSOLE_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, BASEBOARD_POWERBTN_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_shared_alert_task, (BIT(2) | BIT(0)), BASEBOARD_PD_INT_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, BASEBOARD_PD_INT_TASK_STACK_SIZE)
diff --git a/board/omnigul/fans.c b/board/omnigul/fans.c
new file mode 100644
index 0000000000..714449696f
--- /dev/null
+++ b/board/omnigul/fans.c
@@ -0,0 +1,89 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Physical fans. These are logically separate from pwm_channels. */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "fan.h"
+#include "fan_chip.h"
+#include "hooks.h"
+#include "pwm.h"
+
+/* MFT channels. These are logically separate from pwm_channels. */
+const struct mft_t mft_channels[] = {
+	[MFT_CH_0] = {
+		.module = NPCX_MFT_MODULE_1,
+		.clk_src = TCKC_LFCLK,
+		.pwm_id = PWM_CH_FAN,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
+
+static const struct fan_conf fan_conf_0 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
+	.pgood_gpio = -1,
+	.enable_gpio = GPIO_EN_PP5000_FAN,
+};
+
+/*
+ * TOOD(b/181271666): thermistor placement and calibration
+ *
+ * Prototype fan spins at about 4200 RPM at 100% PWM, this
+ * is specific to board ID 2 and might also apears in later
+ * boards as well.
+ */
+static const struct fan_rpm fan_rpm_0 = {
+	.rpm_min = 2100,
+	.rpm_start = 2400,
+	.rpm_max = 4464,
+};
+
+const struct fan_t fans[FAN_CH_COUNT] = {
+	[FAN_CH_0] = {
+		.conf = &fan_conf_0,
+		.rpm = &fan_rpm_0,
+	},
+};
+
+#ifndef CONFIG_FANS
+
+/*
+ * TODO(b/181271666): use static fan speeds until fan and sensors are
+ * tuned. for now, use:
+ *
+ *   AP off:  33%
+ *   AP  on: 100%
+ */
+
+static void fan_slow(void)
+{
+	const int duty_pct = 33;
+
+	ccprints("%s: speed %d%%", __func__, duty_pct);
+
+	pwm_enable(PWM_CH_FAN, 1);
+	pwm_set_duty(PWM_CH_FAN, duty_pct);
+}
+
+static void fan_max(void)
+{
+	const int duty_pct = 100;
+
+	ccprints("%s: speed %d%%", __func__, duty_pct);
+
+	pwm_enable(PWM_CH_FAN, 1);
+	pwm_set_duty(PWM_CH_FAN, duty_pct);
+}
+
+DECLARE_HOOK(HOOK_INIT, fan_slow, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, fan_slow, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, fan_slow, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_RESET, fan_max, HOOK_PRIO_FIRST);
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, fan_max, HOOK_PRIO_DEFAULT);
+
+#endif /* CONFIG_FANS */
diff --git a/board/omnigul/fw_config.c b/board/omnigul/fw_config.c
new file mode 100644
index 0000000000..34b460dad1
--- /dev/null
+++ b/board/omnigul/fw_config.c
@@ -0,0 +1,48 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "fw_config.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+static union omnigul_cbi_fw_config fw_config;
+BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
+
+/*
+ * FW_CONFIG defaults for Omnigul if the CBI.FW_CONFIG data is not
+ * initialized.
+ */
+static const union omnigul_cbi_fw_config fw_config_defaults = {
+	.kb_bl = KEYBOARD_BACKLIGHT_ENABLED,
+	.tab_mode = TABLETMODE_DISABLED,
+	.aud = AUDIO_ALC5682I_ALC1019,
+	.sar_id = SAR_ID_0,
+};
+
+/****************************************************************************
+ * Omnigul FW_CONFIG access
+ */
+void board_init_fw_config(void)
+{
+	if (cbi_get_fw_config(&fw_config.raw_value)) {
+		CPRINTS("CBI: Read FW_CONFIG failed, using board defaults");
+		fw_config = fw_config_defaults;
+	}
+}
+
+union omnigul_cbi_fw_config get_fw_config(void)
+{
+	return fw_config;
+}
+
+bool ec_cfg_has_tabletmode(void)
+{
+	return (fw_config.tab_mode == TABLETMODE_ENABLED);
+}
diff --git a/board/omnigul/fw_config.h b/board/omnigul/fw_config.h
new file mode 100644
index 0000000000..d0facef0da
--- /dev/null
+++ b/board/omnigul/fw_config.h
@@ -0,0 +1,58 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __BOARD_OMNIGUL_FW_CONFIG_H_
+#define __BOARD_OMNIGUL_FW_CONFIG_H_
+
+#include <stdint.h>
+
+/****************************************************************************
+ * CBI FW_CONFIG layout for Omnigul board.
+ *
+ * Source of truth is the project/brya/brya/config.star configuration file.
+ */
+
+enum ec_cfg_keyboard_backlight_type {
+	KEYBOARD_BACKLIGHT_DISABLED = 0,
+	KEYBOARD_BACKLIGHT_ENABLED = 1
+};
+
+enum ec_cfg_tabletmode_type { TABLETMODE_DISABLED = 0, TABLETMODE_ENABLED = 1 };
+
+enum ec_cfg_storage_type {
+	STORAGE_UNPROVISION = 0,
+	STORAGE_UFS = 1,
+	STORAGE_NVMe = 2
+};
+
+enum ec_cfg_audio_type {
+	AUDIO_ALC5682I_ALC1019 = 0,
+	AUDIO_ALC5682I_ALC1019_3MIC = 1
+};
+
+enum ec_cfg_sar_id { SAR_ID_0 = 0, SAR_ID_1 = 1 };
+
+union omnigul_cbi_fw_config {
+	struct {
+		enum ec_cfg_keyboard_backlight_type kb_bl : 1;
+		enum ec_cfg_tabletmode_type tab_mode : 1;
+		enum ec_cfg_storage_type stg : 2;
+		enum ec_cfg_audio_type aud : 1;
+		enum ec_cfg_sar_id sar_id : 1;
+		uint32_t reserved_1 : 26;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Read the cached FW_CONFIG.  Guaranteed to have valid values.
+ *
+ * @return the FW_CONFIG for the board.
+ */
+union omnigul_cbi_fw_config get_fw_config(void);
+
+bool ec_cfg_has_tabletmode(void);
+
+#endif /* __BOARD_OMNIGUL_FW_CONFIG_H_ */
diff --git a/board/omnigul/generated-gpio.inc b/board/omnigul/generated-gpio.inc
new file mode 100644
index 0000000000..8fec026b96
--- /dev/null
+++ b/board/omnigul/generated-gpio.inc
@@ -0,0 +1,125 @@
+/*
+ * This file was auto-generated.
+ */
+
+/* INTERRUPT GPIOs: */
+GPIO_INT(ACOK_OD,                        PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
+GPIO_INT(EC_ACCEL_INT_R_L,               PIN(8, 1), GPIO_SEL_1P8V | GPIO_INT_FALLING, lis2dw12_interrupt)
+GPIO_INT(EC_IMU_INT_R_L,                 PIN(5, 6), GPIO_SEL_1P8V | GPIO_INT_FALLING, lsm6dso_interrupt)
+GPIO_INT(EC_PROCHOT_IN_L,                PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
+GPIO_INT(EC_VOLDN_BTN_ODL,               PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(EC_VOLUP_BTN_ODL,               PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(EC_WP_ODL,                      PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(GSC_EC_PWR_BTN_ODL,             PIN(0, 1), GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW, power_button_interrupt)
+GPIO_INT(LID_OPEN,                       PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
+GPIO_INT(SEQ_EC_ALL_SYS_PG,              PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_DSW_PWROK,               PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_RSMRST_ODL,              PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,                       PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,                      PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SYS_SLP_S0IX_L,                 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(TABLET_MODE_L,                  PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
+GPIO_INT(USB_C0_TCPC_INT_ODL,            PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C0_PPC_INT_ODL,             PIN(6, 2), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C1_PPC_INT_ODL,             PIN(F, 5), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C1_TCPC_INT_ODL,            PIN(A, 2), GPIO_INT_FALLING, tcpc_alert_event)
+
+/* USED GPIOs: */
+GPIO(CCD_MODE_ODL,                   PIN(E, 5), GPIO_INPUT)
+GPIO(CHARGER_VAP_OTG_EN,             PIN(7, 3), GPIO_OUT_LOW)
+GPIO(CPU_C10_GATE_L,                 PIN(6, 7), GPIO_INPUT)
+GPIO(EC_BATT_PRES_ODL,               PIN(A, 3), GPIO_INPUT)
+GPIO(EC_ENTERING_RW,                 PIN(0, 3), GPIO_OUT_LOW)
+GPIO(EC_EN_EDP_BL,                   PIN(D, 3), GPIO_OUT_HIGH)
+GPIO(EC_GSC_PACKET_MODE,             PIN(7, 5), GPIO_OUT_LOW)
+GPIO(EC_I2C_BAT_SCL,                 PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_BAT_SDA,                 PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SCL_R,              PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SDA_R,              PIN(B, 2), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,              PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SENSOR_SDA,              PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_USB_C0_PPC_BC_SCL,       PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_PPC_BC_SDA,       PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_TCPC_SCL,         PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_TCPC_SDA,         PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_MIX_SCL,          PIN(E, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_MIX_SDA,          PIN(E, 3), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_TCPC_SCL,         PIN(F, 3), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_TCPC_SDA,         PIN(F, 2), GPIO_INPUT)
+GPIO(EC_KB_BL_EN_L,                  PIN(8, 6), GPIO_OUT_HIGH)
+GPIO(EC_PCHHOT_ODL,                  PIN(7, 4), GPIO_INPUT)
+GPIO(EC_PCH_INT_ODL,                 PIN(B, 0), GPIO_ODR_HIGH)
+GPIO(EC_PCH_PWR_BTN_ODL,             PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(EC_PCH_RSMRST_L,                PIN(A, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_RTCRST,                  PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_SYS_PWROK,               PIN(3, 7), GPIO_OUT_LOW)
+GPIO(EC_PCH_WAKE_R_ODL,              PIN(C, 0), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_ODL,                 PIN(6, 3), GPIO_ODR_HIGH)
+GPIO(EN_PP5000_FAN,                  PIN(6, 1), GPIO_OUT_HIGH)
+GPIO(EN_PP5000_USBA_R,               PIN(D, 7), GPIO_OUT_LOW)
+GPIO(EN_S5_RAILS,                    PIN(B, 6), GPIO_OUT_LOW)
+GPIO(IMVP9_VRRDY_OD,                 PIN(4, 3), GPIO_INPUT)
+GPIO(PCH_PWROK,                      PIN(7, 2), GPIO_OUT_LOW)
+GPIO(SYS_RST_ODL,                    PIN(C, 5), GPIO_ODR_HIGH)
+GPIO(USB_C0_TCPC_RST_ODL,            PIN(A, 7), GPIO_ODR_LOW)
+GPIO(USB_C1_FRS_EN,                  PIN(9, 4), GPIO_OUT_LOW)
+GPIO(USB_C1_RT_INT_ODL,              PIN(A, 0), GPIO_INPUT)
+GPIO(USB_C1_RT_RST_R_ODL,            PIN(0, 2), GPIO_ODR_LOW)
+GPIO(VCCST_PWRGD_OD,                 PIN(A, 4), GPIO_ODR_LOW)
+GPIO(USB_C1_BC12_INT_ODL,            PIN(5, 0), GPIO_ODR_HIGH)
+
+/* UART alternate functions */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)              /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */
+
+/* I2C alternate functions */
+ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)               /* GPIO33/I2C5_SCL0/CTS_L, GPIO36/RTS_L/I2C5_SDA0 */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)               /* GPIO87/I2C1_SDA0 */
+ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)               /* GPIO92/I2C2_SCL0, GPIO91/I2C2_SDA0, GPIO90/I2C1_SCL0 */
+ALTERNATE(PIN_MASK(B, 0x0c), 0, MODULE_I2C, 0)               /* GPIOB3/I2C7_SCL0/DCD_L, GPIOB2/I2C7_SDA0/DSR_L */
+ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, GPIO_SEL_1P8V)   /* GPIOB5/I2C0_SCL0, GPIOB4/I2C0_SDA0 */
+ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)               /* GPIOD1/I2C3_SCL0, GPIOD0/I2C3_SDA0 */
+ALTERNATE(PIN_MASK(E, 0x18), 0, MODULE_I2C, 0)               /* GPIOE4/I2C6_SCL1/I3C_SCL, GPIOE3/I2C6_SDA1/I3C_SDA */
+ALTERNATE(PIN_MASK(F, 0x0c), 0, MODULE_I2C, 0)               /* GPIOF3/I2C4_SCL1, GPIOF2/I2C4_SDA1 */
+
+/* PWM alternate functions */
+ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0)               /* GPIO40/TA1 */
+ALTERNATE(PIN_MASK(6, 0x01), 0, MODULE_PWM, 0)               /* GPIO60/PWM7 */
+ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)               /* GPIO80/PWM3 */
+ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)               /* GPIOB7/PWM5 */
+ALTERNATE(PIN_MASK(C, 0x1c), 0, MODULE_PWM, 0)               /* GPIOC4/PWM2, GPIOC3/PWM0, GPIOC2/PWM1/I2C6_SCL0 */
+
+/* ADC alternate functions */
+ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0)               /* GPIO34/PS2_DAT2/ADC6 */
+ALTERNATE(PIN_MASK(4, 0x34), 0, MODULE_ADC, 0)               /* GPIO42/ADC3/RI_L, GPIO45/ADC0, GPIO44/ADC1 */
+ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0)               /* GPIOE1/ADC7 */
+
+/* KB alternate functions */
+ALTERNATE(PIN_MASK(0, 0xf0), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO10&P80_CLK/GPIO07, KSO11&P80_DAT/GPIO06, KSO12/GPIO05, KSO13/GPIO04 */
+ALTERNATE(PIN_MASK(1, 0x7f), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO06/GPO13/GP_SEL_L, KSO07/GPO12/JEN_L, KSO03/GPIO16/JTAG_TDO0_SWO, KSO04/GPIO15/XNOR, KSO05/GPIO14, KSO08/GPIO11/CR_SOUT1, KSO09/GPIO10/CR_SIN1 */
+ALTERNATE(PIN_MASK(2, 0xfc), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI2/GPIO27/TRACEDATA1, KSI3/GPIO26/TRACEDATA0, KSI4/GPIO25/TRACECLK/GP_SCLK, KSI5/GPIO24/GP_MISO, KSI6/GPIO23/S_SBUB, KSI7/GPIO22/S_SBUA */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO00/GPIO21/JTAG_TCK_SWCLK, KSO01/GPIO20/JTAG_TMS_SWIO */
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI0/GPIO31/TRACEDATA3/GP_MOSI, KSI1/GPIO30/TRACEDATA2/GP_CS_L */
+ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO14/GPIO82 */
+
+/* PMU alternate functions */
+ALTERNATE(PIN_MASK(0, 0x01), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN2_L&GPI00/GPIO00 */
+ALTERNATE(PIN_MASK(0, 0x02), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW) /* GPIO01/PSL_IN3_L&GPI01 */
+ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN1_L&GPID2/GPIOD2 */
+
+/* Unused Pins */
+UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
+UNUSED(PIN(3, 2))       /* GPO32/TRIS_L */
+UNUSED(PIN(3, 5))       /* GPO35/CR_SOUT4/TEST_L */
+UNUSED(PIN(6, 6))       /* GPIO66 */
+UNUSED(PIN(5, 7))       /* GPIO57/SER_IRQ/ESPI_ALERT_L */
+UNUSED(PIN(4, 1))       /* GPIO41/ADC4 */
+UNUSED(PIN(7, 0))       /* GPIO70/PS2_DAT0 */
+UNUSED(PIN(8, 3))       /* GPIO83/KSO15 */
+UNUSED(PIN(9, 6))       /* GPIO96/F_DIO1 */
+UNUSED(PIN(B, 1))       /* GPIOB1/KSO17/CR_SIN4 */
+UNUSED(PIN(D, 0))       /* GPIOD0/I2C3_SDA0 */
+UNUSED(PIN(D, 1))       /* GPIOD1/I2C3_SCL0 */
+UNUSED(PIN(D, 4))       /* GPIOD4/CR_SIN3 */
+UNUSED(PIN(C, 6))       /* GPIOC6/SMI */
+
+/* Pre-configured PSL balls:  J8  K6 */
diff --git a/board/omnigul/gpio.inc b/board/omnigul/gpio.inc
new file mode 100644
index 0000000000..0bb243eefe
--- /dev/null
+++ b/board/omnigul/gpio.inc
@@ -0,0 +1,38 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define MODULE_KB		MODULE_KEYBOARD_SCAN
+
+/*
+ * Generated-gpio.inc is produced using a Brya specific tool that
+ * parses the GPIO definitions derived from the board schematics and
+ * EC pinout descriptions derived form the chip datasheets to generate
+ * the Chrome EC GPIO pinout definitions. Due to the confidential
+ * nature of schematics and datasheets, they are not provided here.
+ *
+ * Variants that do not auto-generate their GPIO definitions should
+ * combine the Brya gpio.inc and generated-gpio.inc into their
+ * gpio.inc and customize as appropriate.
+ */
+
+#include "generated-gpio.inc"
+
+/*
+ * The NPCX keyboard driver does not use named GPIOs to access
+ * keyboard scan pins, so we do not list them in *gpio.inc. However, when
+ * KEYBOARD_COL2_INVERTED is defined, this name is required.
+ */
+GPIO(EC_KSO_02_INV,               PIN(1, 7), GPIO_OUT_LOW)
+
+/* IO expander configuration */
+
+/* GPIO02_P2 to PU */
+/* GPIO03_P2 to PU */
+IOEX(USB_C0_OC_ODL,          EXPIN(IOEX_C0_NCT38XX, 0, 4), GPIO_ODR_HIGH)
+IOEX(USB_C0_FRS_EN,          EXPIN(IOEX_C0_NCT38XX, 0, 6), GPIO_OUT_LOW)
+IOEX(USB_C0_RT_RST_ODL,      EXPIN(IOEX_C0_NCT38XX, 0, 7), GPIO_ODR_LOW)
+/* GPIO07_P2 to PU */
diff --git a/board/omnigul/i2c.c b/board/omnigul/i2c.c
new file mode 100644
index 0000000000..1dfad89ee4
--- /dev/null
+++ b/board/omnigul/i2c.c
@@ -0,0 +1,73 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "hooks.h"
+#include "i2c.h"
+
+/* I2C port map configuration */
+const struct i2c_port_t i2c_ports[] = {
+	{
+		/* I2C0 */
+		.name = "sensor",
+		.port = I2C_PORT_SENSOR,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_SENSOR_SCL,
+		.sda = GPIO_EC_I2C_SENSOR_SDA,
+	},
+	{
+		/* I2C1 */
+		.name = "tcpc0",
+		.port = I2C_PORT_USB_C0_TCPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_TCPC_SDA,
+	},
+	{
+		/* I2C2 */
+		.name = "ppc0",
+		.port = I2C_PORT_USB_C0_PPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_PPC_BC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_PPC_BC_SDA,
+	},
+	{
+		/* I2C4 C1 TCPC */
+		.name = "tcpc1",
+		.port = I2C_PORT_USB_C1_TCPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C1_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C1_TCPC_SDA,
+		.flags = I2C_PORT_FLAG_DYNAMIC_SPEED,
+	},
+	{
+		/* I2C5 */
+		.name = "battery",
+		.port = I2C_PORT_BATTERY,
+		.kbps = 100,
+		.scl = GPIO_EC_I2C_BAT_SCL,
+		.sda = GPIO_EC_I2C_BAT_SDA,
+	},
+	{
+		/* I2C6 */
+		.name = "ppc1",
+		.port = I2C_PORT_USB_C1_PPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C1_MIX_SCL,
+		.sda = GPIO_EC_I2C_USB_C1_MIX_SDA,
+		.flags = I2C_PORT_FLAG_DYNAMIC_SPEED,
+	},
+	{
+		/* I2C7 */
+		.name = "eeprom",
+		.port = I2C_PORT_EEPROM,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_MISC_SCL_R,
+		.sda = GPIO_EC_I2C_MISC_SDA_R,
+	},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/board/omnigul/keyboard.c b/board/omnigul/keyboard.c
new file mode 100644
index 0000000000..8e26876a73
--- /dev/null
+++ b/board/omnigul/keyboard.c
@@ -0,0 +1,75 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "ec_commands.h"
+#include "keyboard_scan.h"
+#include "timer.h"
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/* Increase from 50 us, because KSO_02 passes through the H1. */
+	.output_settle_us = 80,
+	/* Other values should be the same as the default configuration. */
+	.debounce_down_us = 9 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x1c, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xa4, 0xff, 0xf7, 0x55, 0xfb, 0xca  /* full set */
+	},
+};
+
+static const struct ec_response_keybd_config omnigul_kb = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &omnigul_kb;
+}
+
+/*
+ * Row Column info for Top row keys T1 - T15.
+ * on mithrax_kb keyboard Row Column is customization
+ * need define row col to mapping matrix layout.
+ */
+__override const struct key {
+	uint8_t row;
+	uint8_t col;
+} vivaldi_keys[] = {
+	{ .row = 0, .col = 2 }, /* T1 */
+	{ .row = 3, .col = 2 }, /* T2 */
+	{ .row = 2, .col = 2 }, /* T3 */
+	{ .row = 1, .col = 2 }, /* T4 */
+	{ .row = 3, .col = 4 }, /* T5 */
+	{ .row = 2, .col = 4 }, /* T6 */
+	{ .row = 1, .col = 4 }, /* T7 */
+	{ .row = 2, .col = 9 }, /* T8 */
+	{ .row = 1, .col = 9 }, /* T9 */
+	{ .row = 0, .col = 4 }, /* T10 */
+	{ .row = 3, .col = 0 }, /* T11 */
+	{ .row = 1, .col = 5 }, /* T12 */
+	{ .row = 3, .col = 5 }, /* T13 */
+	{ .row = 0, .col = 9 }, /* T14 */
+	{ .row = 0, .col = 11 }, /* T15 */
+};
+BUILD_ASSERT(ARRAY_SIZE(vivaldi_keys) == MAX_TOP_ROW_KEYS);
diff --git a/board/omnigul/keyboard_customization.c b/board/omnigul/keyboard_customization.c
new file mode 100644
index 0000000000..51d9e2d898
--- /dev/null
+++ b/board/omnigul/keyboard_customization.c
@@ -0,0 +1,102 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "gpio.h"
+#include "keyboard_8042_sharedlib.h"
+#include "keyboard_config.h"
+#include "keyboard_customization.h"
+#include "keyboard_protocol.h"
+#include "keyboard_raw.h"
+
+static uint16_t scancode_set2[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = {
+	{ 0x0000, 0x0000, 0x0014, 0x0000, 0xe014, 0x0000, 0x0000, 0x0000 },
+	{ 0xe01f, 0x0076, 0x000d, 0x000e, 0x001c, 0x001a, 0x0016, 0x0015 },
+	{ 0x0005, 0x000c, 0x0004, 0x0006, 0x0023, 0x0021, 0x0026, 0x0024 },
+	{ 0x0032, 0x0034, 0x002c, 0x002e, 0x002b, 0x002a, 0x0025, 0x002d },
+	{ 0x000a, 0x0083, 0x000b, 0x0003, 0x001b, 0x0022, 0x001e, 0x001d },
+	{ 0x0051, 0x0000, 0x005b, 0x0000, 0x0042, 0x0041, 0x003e, 0x0043 },
+	{ 0x0031, 0x0033, 0x0035, 0x0036, 0x003b, 0x003a, 0x003d, 0x003c },
+	{ 0x0000, 0x0000, 0x0061, 0x0000, 0x0000, 0x0012, 0x0000, 0x0059 },
+	{ 0x0055, 0x0052, 0x0054, 0x004e, 0x004c, 0x004a, 0x0045, 0x004d },
+	{ 0x0000, 0x0078, 0x0009, 0x0000, 0x004b, 0x0049, 0x0046, 0x0044 },
+	{ 0xe011, 0x0000, 0x006a, 0x0000, 0x005d, 0x0000, 0x0011, 0x0000 },
+	{ 0x0000, 0x0066, 0x0000, 0x005d, 0x005a, 0x0029, 0xe072, 0xe075 },
+	{ 0x0000, 0xe064, 0x0000, 0x0067, 0x0000, 0x0000, 0xe074, 0xe06b },
+};
+
+uint16_t get_scancode_set2(uint8_t row, uint8_t col)
+{
+	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS)
+		return scancode_set2[col][row];
+	return 0;
+}
+
+void set_scancode_set2(uint8_t row, uint8_t col, uint16_t val)
+{
+	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS)
+		scancode_set2[col][row] = val;
+}
+
+void board_keyboard_drive_col(int col)
+{
+	/* Drive all lines to high */
+	if (col == KEYBOARD_COLUMN_NONE)
+		gpio_set_level(GPIO_KBD_KSO2, 0);
+
+	/* Set KBSOUT to zero to detect key-press */
+	else if (col == KEYBOARD_COLUMN_ALL)
+		gpio_set_level(GPIO_KBD_KSO2, 1);
+
+	/* Drive one line for detection */
+	else {
+		if (col == 2)
+			gpio_set_level(GPIO_KBD_KSO2, 1);
+		else
+			gpio_set_level(GPIO_KBD_KSO2, 0);
+	}
+}
+
+#ifdef CONFIG_KEYBOARD_DEBUG
+static uint8_t keycap_label[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = {
+	{ 'c', KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO },
+	{ KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO },
+	{ 'q', KLLI_UNKNO, KLLI_UNKNO, KLLI_TAB, '`', '1', KLLI_UNKNO, 'a' },
+	{ KLLI_R_ALT, KLLI_L_ALT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO },
+	{ KLLI_UNKNO, KLLI_SPACE, 'e', KLLI_F4, KLLI_SEARC, '3', KLLI_F3,
+	  KLLI_UNKNO },
+	{ 'x', 'z', KLLI_F2, KLLI_F1, 's', '2', 'w', KLLI_ESC },
+	{ 'v', 'b', 'g', 't', '5', '4', 'r', 'f' },
+	{ 'm', 'n', 'h', 'y', '6', '7', 'u', 'j' },
+	{ '.', KLLI_DOWN, '\\', 'o', KLLI_F10, '9', KLLI_UNKNO, 'l' },
+	{ KLLI_R_SHT, KLLI_L_SHT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO },
+	{ ',', KLLI_UNKNO, KLLI_F7, KLLI_F6, KLLI_F5, '8', 'i', 'k' },
+	{ KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_F9, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_LEFT, KLLI_UNKNO },
+	{ KLLI_R_CTR, KLLI_L_CTR, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO },
+	{ '/', KLLI_UP, '-', KLLI_UNKNO, '0', 'p', '[', ';' },
+	{ '\'', KLLI_ENTER, KLLI_UNKNO, KLLI_UNKNO, '=', KLLI_B_SPC, ']', 'd' },
+	{ KLLI_UNKNO, KLLI_F8, KLLI_RIGHT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO },
+};
+
+uint8_t get_keycap_label(uint8_t row, uint8_t col)
+{
+	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS)
+		return keycap_label[col][row];
+	return KLLI_UNKNO;
+}
+
+void set_keycap_label(uint8_t row, uint8_t col, uint8_t val)
+{
+	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS)
+		keycap_label[col][row] = val;
+}
+#endif
diff --git a/board/omnigul/keyboard_customization.h b/board/omnigul/keyboard_customization.h
new file mode 100644
index 0000000000..8e7e3ee2c1
--- /dev/null
+++ b/board/omnigul/keyboard_customization.h
@@ -0,0 +1,80 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Keyboard configuration */
+
+#ifndef __KEYBOARD_CUSTOMIZATION_H
+#define __KEYBOARD_CUSTOMIZATION_H
+
+#define KEYBOARD_MASK_PWRBTN KEYBOARD_ROW_TO_MASK(3)
+
+/*
+ * KEYBOARD_COLS_MAX has the build time column size. It's used to allocate
+ * exact spaces for arrays. Actual keyboard scanning is done using
+ * keyboard_cols, which holds a runtime column size.
+ */
+#ifdef CONFIG_KEYBOARD_CUSTOMIZATION
+#undef KEYBOARD_COLS_MAX
+#undef KEYBOARD_ROWS
+
+#define KEYBOARD_COLS_MAX 13
+#define KEYBOARD_ROWS 8
+#endif
+
+/*
+ * WARNING: Do not directly modify it. You should call keyboard_raw_set_cols,
+ * instead. It checks whether you're eligible or not.
+ */
+extern uint8_t keyboard_cols;
+
+#define KEYBOARD_ROW_TO_MASK(r) (1 << (r))
+
+/* Columns and masks for keys we particularly care about */
+#define KEYBOARD_COL_DOWN 11
+#define KEYBOARD_ROW_DOWN 6
+#define KEYBOARD_MASK_DOWN KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_DOWN)
+#define KEYBOARD_COL_ESC 1
+#define KEYBOARD_ROW_ESC 1
+#define KEYBOARD_MASK_ESC KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_ESC)
+#define KEYBOARD_COL_KEY_H 6
+#define KEYBOARD_ROW_KEY_H 1
+#define KEYBOARD_MASK_KEY_H KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_H)
+#define KEYBOARD_COL_KEY_R 3
+#define KEYBOARD_ROW_KEY_R 7
+#define KEYBOARD_MASK_KEY_R KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_R)
+#define KEYBOARD_COL_LEFT_ALT 10
+#define KEYBOARD_ROW_LEFT_ALT 6
+#define KEYBOARD_MASK_LEFT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_ALT)
+#define KEYBOARD_COL_REFRESH 2
+#define KEYBOARD_ROW_REFRESH 3
+#define KEYBOARD_MASK_REFRESH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_REFRESH)
+#define KEYBOARD_COL_RIGHT_ALT 10
+#define KEYBOARD_ROW_RIGHT_ALT 0
+#define KEYBOARD_MASK_RIGHT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_ALT)
+#define KEYBOARD_DEFAULT_COL_VOL_UP 4
+#define KEYBOARD_DEFAULT_ROW_VOL_UP 0
+#define KEYBOARD_COL_LEFT_CTRL 0
+#define KEYBOARD_ROW_LEFT_CTRL 2
+#define KEYBOARD_MASK_LEFT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_CTRL)
+#define KEYBOARD_COL_RIGHT_CTRL 0
+#define KEYBOARD_ROW_RIGHT_CTRL 4
+#define KEYBOARD_MASK_RIGHT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_CTRL)
+#define KEYBOARD_COL_SEARCH 1
+#define KEYBOARD_ROW_SEARCH 0
+#define KEYBOARD_MASK_SEARCH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_SEARCH)
+#define KEYBOARD_COL_KEY_0 8
+#define KEYBOARD_ROW_KEY_0 6
+#define KEYBOARD_MASK_KEY_0 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_0)
+#define KEYBOARD_COL_KEY_1 1
+#define KEYBOARD_ROW_KEY_1 6
+#define KEYBOARD_MASK_KEY_1 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_1)
+#define KEYBOARD_COL_KEY_2 4
+#define KEYBOARD_ROW_KEY_2 6
+#define KEYBOARD_MASK_KEY_2 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_2)
+#define KEYBOARD_COL_LEFT_SHIFT 7
+#define KEYBOARD_ROW_LEFT_SHIFT 5
+#define KEYBOARD_MASK_LEFT_SHIFT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_SHIFT)
+
+#endif /* __KEYBOARD_CUSTOMIZATION_H */
diff --git a/board/omnigul/led.c b/board/omnigul/led.c
new file mode 100644
index 0000000000..8437e7d554
--- /dev/null
+++ b/board/omnigul/led.c
@@ -0,0 +1,79 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Brya specific PWM LED settings: there are 2 LEDs on each side of the board,
+ * each one can be controlled separately. The LED colors are blue or amber,
+ * and the default behavior is tied to the charging process: both sides are
+ * amber while charging the battery and blue when the battery is charged.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "ec_commands.h"
+#include "led_pwm.h"
+#include "pwm.h"
+#include "util.h"
+
+#include <stdint.h>
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_LEFT_LED,
+};
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+/*
+ * We only have a blue and an amber LED, so setting any other color results in
+ * both LEDs being off. Cap at 50% to save power.
+ */
+struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = {
+	/* Amber, Blue */
+	[EC_LED_COLOR_RED] = { 0, 0 },	 [EC_LED_COLOR_GREEN] = { 0, 0 },
+	[EC_LED_COLOR_BLUE] = { 0, 50 }, [EC_LED_COLOR_YELLOW] = { 0, 0 },
+	[EC_LED_COLOR_WHITE] = { 0, 0 }, [EC_LED_COLOR_AMBER] = { 50, 0 },
+};
+
+/* Two logical LEDs with amber and blue channels. */
+struct pwm_led pwm_leds[CONFIG_LED_PWM_COUNT] = {
+	{
+		.ch0 = PWM_CH_LED2,
+		.ch1 = PWM_CH_LED1,
+		.ch2 = PWM_LED_NO_CHANNEL,
+		.enable = &pwm_enable,
+		.set_duty = &pwm_set_duty,
+	},
+};
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	memset(brightness_range, '\0',
+	       sizeof(*brightness_range) * EC_LED_COLOR_COUNT);
+	brightness_range[EC_LED_COLOR_AMBER] = 100;
+	brightness_range[EC_LED_COLOR_BLUE] = 100;
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	enum pwm_led_id pwm_id;
+
+	/* Convert ec_led_id to pwm_led_id. */
+	switch (led_id) {
+	case EC_LED_ID_LEFT_LED:
+		pwm_id = PWM_LED0;
+		break;
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+
+	if (brightness[EC_LED_COLOR_BLUE])
+		set_pwm_led_color(pwm_id, EC_LED_COLOR_BLUE);
+	else if (brightness[EC_LED_COLOR_AMBER])
+		set_pwm_led_color(pwm_id, EC_LED_COLOR_AMBER);
+	else
+		/* Otherwise, the "color" is "off". */
+		set_pwm_led_color(pwm_id, -1);
+
+	return EC_SUCCESS;
+}
diff --git a/board/omnigul/pwm.c b/board/omnigul/pwm.c
new file mode 100644
index 0000000000..23046bac73
--- /dev/null
+++ b/board/omnigul/pwm.c
@@ -0,0 +1,56 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "hooks.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_LED2] = {
+		.channel = 0,
+		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+		.freq = 4800,
+	},
+	[PWM_CH_LED1] = {
+		.channel = 2,
+		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+		.freq = 4800,
+	},
+	[PWM_CH_KBLIGHT] = {
+		.channel = 3,
+		.flags = 0,
+		/*
+		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
+		 * flicker. Higher frequencies consume similar average power to
+		 * lower PWM frequencies, but higher frequencies record a much
+		 * lower maximum power.
+		 */
+		.freq = 12000,
+	},
+	[PWM_CH_FAN] = {
+		.channel = 5,
+		.flags = PWM_CONFIG_OPEN_DRAIN,
+		.freq = 25000,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+static void board_pwm_init(void)
+{
+	/*
+	 * Turn off all the LEDs.
+	 * Turn on the fan at 100%.
+	 */
+	pwm_enable(PWM_CH_LED1, 1);
+	pwm_set_duty(PWM_CH_LED1, 0);
+	pwm_enable(PWM_CH_LED2, 1);
+	pwm_set_duty(PWM_CH_LED2, 0);
+
+	pwm_enable(PWM_CH_KBLIGHT, 1);
+	pwm_set_duty(PWM_CH_KBLIGHT, 50);
+}
+DECLARE_HOOK(HOOK_INIT, board_pwm_init, HOOK_PRIO_DEFAULT);
diff --git a/board/omnigul/sensors.c b/board/omnigul/sensors.c
new file mode 100644
index 0000000000..a2d08bd045
--- /dev/null
+++ b/board/omnigul/sensors.c
@@ -0,0 +1,270 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "accelgyro.h"
+#include "adc.h"
+#include "common.h"
+#include "driver/accel_lis2dw12.h"
+#include "driver/accelgyro_lsm6dso.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "motion_sense.h"
+#include "tablet_mode.h"
+#include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
+#include "thermal.h"
+
+/* ADC configuration */
+struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_1_DDR_SOC] = {
+		.name = "TEMP_DDR_SOC",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_2_AMBIENT] = {
+		.name = "TEMP_AMBIENT",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_3_CHARGER] = {
+		.name = "TEMP_CHARGER",
+		.input_ch = NPCX_ADC_CH6,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+K_MUTEX_DEFINE(g_lid_accel_mutex);
+K_MUTEX_DEFINE(g_base_accel_mutex);
+static struct stprivate_data g_lis2dw12_data;
+static struct lsm6dso_data lsm6dso_data;
+
+/* TODO(b/184779333): calibrate the orientation matrix on later board stage */
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					     { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
+
+/* TODO(b/184779743): verify orientation matrix */
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, FLOAT_TO_FP(-1), 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
+
+struct motion_sensor_t motion_sensors[] = {
+	[LID_ACCEL] = {
+		.name = "Lid Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LIS2DW12,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &lis2dw12_drv,
+		.mutex = &g_lid_accel_mutex,
+		.drv_data = &g_lis2dw12_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LIS2DW12_ADDR0,
+		.rot_standard_ref = &lid_standard_ref, /* identity matrix */
+		.default_range = 2, /* g */
+		.min_frequency = LIS2DW12_ODR_MIN_VAL,
+		.max_frequency = LIS2DW12_ODR_MAX_VAL,
+		.config = {
+			/* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+			/* Sensor on for lid angle detection */
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+		},
+	},
+
+	[BASE_ACCEL] = {
+		.name = "Base Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LSM6DSO,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &lsm6dso_drv,
+		.mutex = &g_base_accel_mutex,
+		.drv_data = LSM6DSO_ST_DATA(lsm6dso_data,
+				MOTIONSENSE_TYPE_ACCEL),
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LSM6DSO_ADDR0_FLAGS,
+		.rot_standard_ref = &base_standard_ref,
+		.default_range = 4,  /* g */
+		.min_frequency = LSM6DSO_ODR_MIN_VAL,
+		.max_frequency = LSM6DSO_ODR_MAX_VAL,
+		.config = {
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 13000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+		},
+	},
+
+	[BASE_GYRO] = {
+		.name = "Base Gyro",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LSM6DSO,
+		.type = MOTIONSENSE_TYPE_GYRO,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &lsm6dso_drv,
+		.mutex = &g_base_accel_mutex,
+		.drv_data = LSM6DSO_ST_DATA(lsm6dso_data,
+				MOTIONSENSE_TYPE_GYRO),
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LSM6DSO_ADDR0_FLAGS,
+		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = LSM6DSO_ODR_MIN_VAL,
+		.max_frequency = LSM6DSO_ODR_MAX_VAL,
+	},
+};
+const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+static void baseboard_sensors_init(void)
+{
+	if (ec_cfg_has_tabletmode()) {
+		/* Enable gpio interrupt for lid accel sensor */
+		gpio_enable_interrupt(GPIO_EC_ACCEL_INT_R_L);
+		/* Enable gpio interrupt for base accelgyro sensor */
+		gpio_enable_interrupt(GPIO_EC_IMU_INT_R_L);
+	} else {
+		gmr_tablet_switch_disable();
+		/* Base accel is not stuffed, don't allow line to float */
+		gpio_set_flags(GPIO_EC_ACCEL_INT_R_L,
+			       GPIO_INPUT | GPIO_PULL_DOWN);
+		gpio_set_flags(GPIO_EC_IMU_INT_R_L,
+			       GPIO_INPUT | GPIO_PULL_DOWN);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_INIT_I2C + 1);
+
+/* Temperature sensor configuration */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1_DDR_SOC] = {
+		.name = "DDR and SOC",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_1_DDR_SOC,
+	},
+	[TEMP_SENSOR_2_AMBIENT] = {
+		.name = "Ambient",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_2_AMBIENT,
+	},
+	[TEMP_SENSOR_3_CHARGER] = {
+		.name = "Charger",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_3_CHARGER,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/*
+ * TODO(b/180681346): update for Alder Lake/brya
+ *
+ * Alder Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
+ * 130 C.  However, sensor is located next to DDR, so we need to use the lower
+ * DDR temperature limit (85 C)
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = 0, \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = 0, \
+		}, \
+		.temp_fan_off = 0, \
+		.temp_fan_max = 0, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
+
+/*
+ * TODO(b/180681346): update for Alder Lake/brya
+ *
+ * Inductor limits - used for both charger and PP3300 regulator
+ *
+ * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
+ *
+ * Charger max recommended temperature 100C, max absolute temperature 125C
+ * PP3300 regulator: operating range -40 C to 145 C
+ *
+ * Inductors: limit of 125c
+ * PCB: limit is 80c
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_AMBIENT          \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = C_TO_K(70), \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(73), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = C_TO_K(69), \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(68), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(70), \
+		}, \
+		.temp_fan_off = C_TO_K(40), \
+		.temp_fan_max = C_TO_K(65), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_ambient =
+	THERMAL_AMBIENT;
+
+/*
+ * Inductor limits - used for both charger and PP3300 regulator
+ *
+ * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
+ *
+ * Charger max recommended temperature 125C, max absolute temperature 150C
+ * PP3300 regulator: operating range -40 C to 125 C
+ *
+ * Inductors: limit of 125c
+ * PCB: limit is 80c
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CHARGER          \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = 0, \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = 0, \
+		}, \
+		.temp_fan_off = 0, \
+		.temp_fan_max = 0, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_charger =
+	THERMAL_CHARGER;
+
+struct ec_thermal_config thermal_params[] = {
+	[TEMP_SENSOR_1_DDR_SOC] = THERMAL_CPU,
+	[TEMP_SENSOR_2_AMBIENT] = THERMAL_AMBIENT,
+	[TEMP_SENSOR_3_CHARGER] = THERMAL_CHARGER,
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
diff --git a/board/omnigul/usbc_config.c b/board/omnigul/usbc_config.c
new file mode 100644
index 0000000000..307d4fccca
--- /dev/null
+++ b/board/omnigul/usbc_config.c
@@ -0,0 +1,242 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/ppc/nx20p348x.h"
+#include "driver/ppc/syv682x_public.h"
+#include "driver/tcpm/nct38xx.h"
+#include "driver/tcpm/ps8xxx_public.h"
+#include "driver/tcpm/tcpci.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "ioexpander.h"
+#include "system.h"
+#include "task.h"
+#include "task_id.h"
+#include "timer.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+/* USBC TCPC configuration */
+const struct tcpc_config_t tcpc_config[] = {
+	[USBC_PORT_C0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0_TCPC,
+			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_NO_DEBUG_ACC_CONTROL,
+	},
+	[USBC_PORT_C1] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C1_TCPC,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
+			 TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V |
+			 TCPC_FLAGS_CONTROL_VCONN |
+			 TCPC_FLAGS_CONTROL_FRS |
+			 TCPC_FLAGS_VBUS_MONITOR,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
+BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
+
+/******************************************************************************/
+/* USB-A charging control */
+
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_PP5000_USBA_R,
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
+
+/******************************************************************************/
+
+/* USBC PPC configuration */
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_PPC,
+		.i2c_addr_flags = SYV682X_ADDR2_FLAGS,
+		.frs_en = IOEX_USB_C0_FRS_EN,
+		.drv = &syv682x_drv,
+	},
+	[USBC_PORT_C1] = {
+		/* Compatible with Silicon Mitus SM5360A */
+		.i2c_port = I2C_PORT_USB_C1_PPC,
+		.i2c_addr_flags = NX20P3483_ADDR2_FLAGS,
+		.drv = &nx20p348x_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
+
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/*
+ * USB3 DB mux configuration - the top level mux still needs to be set
+ * to the virtual_usb_mux_driver so the AP gets notified of mux changes
+ * and updates the TCSS configuration on state changes.
+ */
+static const struct usb_mux_chain usbc1_usb3_db_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
+};
+
+const struct usb_mux_chain usb_muxes[] = {
+	[USBC_PORT_C0] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+	},
+	[USBC_PORT_C1] = {
+		.mux = &(const struct usb_mux) {
+			/* PS8815 DB */
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc1_usb3_db_retimer,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
+
+/*
+ * ioex_init() is normally called before we take the TCPCs out of
+ * reset, so we need to start in disabled mode, then explicitly
+ * call ioex_init().
+ */
+
+struct ioexpander_config_t ioex_config[] = {
+	[IOEX_C0_NCT38XX] = {
+		.i2c_host_port = I2C_PORT_USB_C0_TCPC,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT);
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * TODO(b/179648104): figure out correct timing
+	 */
+
+	gpio_set_level(GPIO_USB_C0_TCPC_RST_ODL, 0);
+	gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 0);
+
+	/*
+	 * delay for power-on to reset-off and min. assertion time
+	 */
+
+	msleep(20);
+
+	gpio_set_level(GPIO_USB_C0_TCPC_RST_ODL, 1);
+	gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 1);
+
+	/* wait for chips to come up */
+
+	msleep(50);
+}
+
+static void board_tcpc_init(void)
+{
+	/* Don't reset TCPCs after initial reset */
+	if (!system_jumped_late())
+		board_reset_pd_mcu();
+
+	/*
+	 * These IO expander pins are implemented using the
+	 * C0/C2 TCPC, so they must be set up after the TCPC has
+	 * been taken out of reset.
+	 */
+
+	ioex_init(IOEX_C0_NCT38XX);
+
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_0 | PD_STATUS_TCPC_ALERT_2;
+
+	if (gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
+
+int ppc_get_alert_status(int port)
+{
+	if (port == USBC_PORT_C0)
+		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
+	else if (port == USBC_PORT_C1)
+		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
+	return 0;
+}
+
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C1);
+		break;
+	default:
+		break;
+	}
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_PPC_INT_ODL:
+		nx20p348x_interrupt(USBC_PORT_C1);
+		break;
+	default:
+		break;
+	}
+}
+
+__override bool board_is_dts_port(int port)
+{
+	return port == USBC_PORT_C0;
+}
diff --git a/board/omnigul/usbc_config.h b/board/omnigul/usbc_config.h
new file mode 100644
index 0000000000..cd4e387406
--- /dev/null
+++ b/board/omnigul/usbc_config.h
@@ -0,0 +1,17 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Brya board-specific USB-C configuration */
+
+#ifndef __CROS_EC_USBC_CONFIG_H
+#define __CROS_EC_USBC_CONFIG_H
+
+#ifndef CONFIG_ZEPHYR
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#endif
+
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
+
+#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/omnigul/vif_override.xml b/board/omnigul/vif_override.xml
new file mode 100644
index 0000000000..6ade5d2f92
--- /dev/null
+++ b/board/omnigul/vif_override.xml
@@ -0,0 +1,148 @@
+<?xml version="1.0" encoding="utf-8"?>
+<vif:VIF xmlns="http://usb.org/VendorInfoFile.xsd">
+  <vif:Product_Revision>2</vif:Product_Revision>
+  <vif:TID>0</vif:TID>
+  <vif:Product>
+    <vif:USB4_Num_Internal_Host_Controllers value="1" />
+    <vif:USB4_Num_PCIe_DN_Bridges value="0" />
+    <vif:USB4RouterList>
+      <vif:Usb4Router>
+        <!--USB4 Router 0-->
+        <vif:USB4_Router_ID value="0" />
+        <vif:USB4_Silicon_VID value="32903">8087</vif:USB4_Silicon_VID>
+        <vif:USB4_Num_Lane_Adapters value="4" />
+        <vif:USB4_Num_USB3_DN_Adapters value="1" />
+        <vif:USB4_Num_DP_IN_Adapters value="1" />
+        <vif:USB4_Num_DP_OUT_Adapters value="0" />
+        <vif:USB4_Num_PCIe_DN_Adapters value="4" />
+        <vif:USB4_TBT3_Not_Supported value="0">TBT3 Compatible</vif:USB4_TBT3_Not_Supported>
+        <vif:USB4_PCIe_Wake_Supported value="true" />
+        <vif:USB4_USB3_Wake_Supported value="false" />
+        <vif:USB4_Num_Unused_Adapters value="0" />
+        <vif:USB4_TBT3_VID value="32903">8087</vif:USB4_TBT3_VID>
+        <vif:USB4_PCIe_Switch_Vendor_ID value="32902">8086</vif:USB4_PCIe_Switch_Vendor_ID>
+        <vif:USB4_PCIe_Switch_Device_ID value="39451">9A1B</vif:USB4_PCIe_Switch_Device_ID>
+      </vif:Usb4Router>
+    </vif:USB4RouterList>
+  </vif:Product>
+
+  <vif:Component>
+    <vif:USB4_Max_Speed value="1">Gen 3 (40Gb)</vif:USB4_Max_Speed>
+
+    <!--;USB Host-->
+
+    <vif:Host_Speed value="4">USB 3.2 Gen 2x2</vif:Host_Speed>
+    <vif:Host_Contains_Captive_Retimer value="true" />
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:Host_Suspend_Supported value="true" />
+
+    <!--;PD Source-->
+    <!-- will we ever clear USB_Suspend_Supported? -->
+    <vif:USB_Suspend_May_Be_Cleared value="true" />
+
+    <!-- remove FR_Swap_* when we enable CONFIG_USB_PD_FRS -->
+    <!--;Dual Role-->
+    <vif:FR_Swap_Supported_As_Initial_Sink value="true" />
+    <!--;PD Source-->
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="3">3A @ 5V</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!--Source PDO 1-->
+        <vif:Src_PD_OCP_OC_Debounce value="50">50 msec</vif:Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="360">3600 mA</vif:Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+
+    <!-- SOP Discover ID -->
+    <vif:Product_Type_UFP_SOP value="2">PDUSB Peripheral</vif:Product_Type_UFP_SOP>
+    <vif:Product_Type_DFP_SOP value="2">PDUSB Host</vif:Product_Type_DFP_SOP>
+
+    <!-- USB4 Port -->
+    <vif:USB4_Lane_0_Adapter value="1" />
+    <vif:USB4_UFP_Supported value="false" />
+    <vif:USB4_DFP_Supported value="true" />
+    <vif:USB4_USB3_Tunneling_Supported value="true" />
+    <vif:USB4_DP_Tunneling_Supported value="true" />
+    <vif:USB4_CL1_State_Supported value="true" />
+    <vif:USB4_CL2_State_Supported value="true" />
+    <vif:USB4_Num_Retimers value="1" />
+    <vif:USB4_DP_Bit_Rate value="3">HBR3</vif:USB4_DP_Bit_Rate>
+    <vif:USB4_Num_DP_Lanes value="4">4 Lanes</vif:USB4_Num_DP_Lanes>
+
+  </vif:Component>
+
+  <vif:Component>
+    <vif:USB4_Supported value="false" />
+
+    <!--;USB Host-->
+    <vif:Host_Speed value="2">USB 3.2 Gen 2x1</vif:Host_Speed>
+    <vif:Host_Contains_Captive_Retimer value="true" />
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:Host_Suspend_Supported value="true" />
+
+    <!--;PD Source-->
+    <!-- will we ever clear USB_Suspend_Supported? -->
+    <vif:USB_Suspend_May_Be_Cleared value="true" />
+
+    <!-- remove FR_Swap_* when we enable CONFIG_USB_PD_FRS -->
+    <!--;Dual Role-->
+    <vif:FR_Swap_Supported_As_Initial_Sink value="true" />
+    <!--;PD Source-->
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="3">3A @ 5V</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!--Source PDO 1-->
+        <vif:Src_PD_OCP_OC_Debounce value="50">50 msec</vif:Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="360">3600 mA</vif:Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+
+    <!-- SOP Discover ID -->
+    <vif:Product_Type_UFP_SOP value="3">PSD</vif:Product_Type_UFP_SOP>
+    <vif:Product_Type_DFP_SOP value="2">PDUSB Host</vif:Product_Type_DFP_SOP>
+
+  </vif:Component>
+
+  <vif:Component>
+    <vif:USB4_Max_Speed value="1">Gen 3 (40Gb)</vif:USB4_Max_Speed>
+    <!--;USB Host-->
+    <vif:Host_Speed value="4">USB 3.2 Gen 2x2</vif:Host_Speed>
+    <vif:Host_Contains_Captive_Retimer value="true" />
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:Host_Suspend_Supported value="true" />
+
+    <!--;PD Source-->
+    <!-- will we ever clear USB_Suspend_Supported? -->
+    <vif:USB_Suspend_May_Be_Cleared value="true" />
+
+    <!-- remove FR_Swap_* when we enable CONFIG_USB_PD_FRS -->
+    <!--;Dual Role-->
+    <vif:FR_Swap_Supported_As_Initial_Sink value="true" />
+    <!--;PD Source-->
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="3">3A @ 5V</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!--Source PDO 1-->
+        <vif:Src_PD_OCP_OC_Debounce value="50">50 msec</vif:Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="360">3600 mA</vif:Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+
+    <!-- SOP Discover ID -->
+    <vif:Product_Type_UFP_SOP value="2">PDUSB Peripheral</vif:Product_Type_UFP_SOP>
+    <vif:Product_Type_DFP_SOP value="2">PDUSB Host</vif:Product_Type_DFP_SOP>
+
+    <!-- USB4 Port -->
+    <vif:USB4_Lane_0_Adapter value="1" />
+    <vif:USB4_UFP_Supported value="false" />
+    <vif:USB4_DFP_Supported value="true" />
+    <vif:USB4_USB3_Tunneling_Supported value="true" />
+    <vif:USB4_DP_Tunneling_Supported value="true" />
+    <vif:USB4_CL1_State_Supported value="true" />
+    <vif:USB4_CL2_State_Supported value="true" />
+    <vif:USB4_Num_Retimers value="1" />
+    <vif:USB4_DP_Bit_Rate value="3">HBR3</vif:USB4_DP_Bit_Rate>
+    <vif:USB4_Num_DP_Lanes value="4">4 Lanes</vif:USB4_Num_DP_Lanes>
+
+  </vif:Component>
+</vif:VIF>
diff --git a/board/osiris/battery.c b/board/osiris/battery.c
new file mode 100644
index 0000000000..669b592b1b
--- /dev/null
+++ b/board/osiris/battery.c
@@ -0,0 +1,150 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery.h"
+#include "battery_fuel_gauge.h"
+#include "cbi.h"
+#include "charge_ramp.h"
+#include "charge_state.h"
+#include "charger_profile_override.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "gpio.h"
+/*
+ * Battery info for all Osiris battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	/* COSMX AP22ABN Battery Information */
+	[BATTERY_COSMX_AP22ABN] = {
+		.fuel_gauge = {
+			.manuf_name = "COSMX KT0030B003",
+			.device_name = "AP22ABN",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x8000,
+				.disconnect_val = 0x8000,
+				.cfet_mask = 0x4000,
+				.cfet_off_val = 0x4000,
+			},
+		},
+		.batt_info = {
+			.voltage_max            = 13440,
+			.voltage_normal         = 11670,
+			.voltage_min            = 9000,
+			.precharge_current      = 567,
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 50,
+			.charging_min_c         = 0,
+			.charging_max_c         = 60,
+			.discharging_min_c      = -20,
+			.discharging_max_c      = 75,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_COSMX_AP22ABN;
+
+enum battery_present battery_hw_present(void)
+{
+	/* The GPIO is low when the battery is physically present */
+	return gpio_get_level(GPIO_EC_BATT_PRES_ODL) ? BP_NO : BP_YES;
+}
+
+static int charger_should_discharge_on_ac(struct charge_state_data *curr)
+{
+	/* can not discharge on AC without battery */
+	if (curr->batt.is_present != BP_YES)
+		return 0;
+
+	/* Do not discharge when battery disconnect */
+	if (battery_get_disconnect_state() != BATTERY_NOT_DISCONNECTED)
+		return 0;
+
+	/* Do not discharge on AC if the battery is still waking up */
+	if ((curr->batt.flags & BATT_FLAG_BAD_STATUS) ||
+	    (!(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
+	     !(curr->batt.status & STATUS_FULLY_CHARGED)))
+		return 0;
+
+	/*
+	 * In heavy load (>3A being withdrawn from VSYS) the DCDC of the
+	 * charger operates on hybrid mode. This causes a slight voltage
+	 * ripple on VSYS that falls in the audible noise frequency (single
+	 * digit kHz range). This small ripple generates audible noise in
+	 * the output ceramic capacitors (caps on VSYS and any input of
+	 * DCDC under VSYS).
+	 *
+	 * To overcome this issue, force battery discharging when battery
+	 * full, So the battery MOS of NVDC charger will turn on always,
+	 * it make the Vsys same as Vbat and the noise has been improved.
+	 */
+	if (!battery_is_cut_off() &&
+	    !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
+	    (curr->batt.status & STATUS_FULLY_CHARGED))
+		return 1;
+
+	return 0;
+}
+
+/*
+ * This can override the smart battery's charging profile. To make a change,
+ * modify one or more of requested_voltage, requested_current, or state.
+ * Leave everything else unchanged.
+ *
+ * Return the next poll period in usec, or zero to use the default (which is
+ * state dependent).
+ */
+int charger_profile_override(struct charge_state_data *curr)
+{
+	int disch_on_ac = charger_should_discharge_on_ac(curr);
+
+	charger_discharge_on_ac(disch_on_ac);
+
+	if (disch_on_ac) {
+		curr->state = ST_DISCHARGE;
+		return 0;
+	}
+
+	return 0;
+}
+
+enum ec_status charger_profile_override_get_param(uint32_t param,
+						  uint32_t *value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+enum ec_status charger_profile_override_set_param(uint32_t param,
+						  uint32_t value)
+{
+	return EC_RES_INVALID_PARAM;
+}
diff --git a/board/osiris/board.c b/board/osiris/board.c
new file mode 100644
index 0000000000..20c1ae0993
--- /dev/null
+++ b/board/osiris/board.c
@@ -0,0 +1,78 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "button.h"
+#include "charge_ramp.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "registers.h"
+#include "switch.h"
+#include "throttle_ap.h"
+#include "usbc_config.h"
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* Console output macros */
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+
+/* Called on AP S3 -> S0 transition */
+static void board_chipset_resume(void)
+{
+	gpio_set_level(GPIO_AMP_PWR_EN, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S0 -> S3 transition */
+static void board_chipset_suspend(void)
+{
+	gpio_set_level(GPIO_AMP_PWR_EN, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
+
+__override void board_kblight_shutdown(void)
+{
+	/* turn off keyboard backlight power */
+	gpio_set_level(GPIO_KYBL_EN, 0);
+}
+
+__override void board_kblight_init(void)
+{
+	/* turn on keyboard backlight power */
+	gpio_set_level(GPIO_KYBL_EN, 1);
+	gpio_set_level(GPIO_EC_KB_BL_EN_L, 1);
+	msleep(10);
+}
+
+/* keyboard factory test */
+#ifdef CONFIG_KEYBOARD_FACTORY_TEST
+/*
+ * We have total 30 pins for keyboard connecter {-1, -1} mean
+ * the N/A pin that don't consider it and reserve index 0 area
+ * that we don't have pin 0.
+ */
+const int keyboard_factory_scan_pins[][2] = {
+	{ -1, -1 }, { 0, 5 },	{ 1, 1 }, { 1, 0 },   { 0, 6 },	  { 0, 7 },
+	{ -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 },   { -1, -1 }, { 1, 6 },
+	{ 1, 7 },   { 3, 1 },	{ 2, 0 }, { 1, 5 },   { 2, 6 },	  { 2, 7 },
+	{ 2, 1 },   { 2, 4 },	{ 2, 5 }, { 1, 2 },   { 2, 3 },	  { 2, 2 },
+	{ 3, 0 },   { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 },	  { -1, -1 },
+	{ -1, -1 },
+};
+
+const int keyboard_factory_scan_pins_used =
+	ARRAY_SIZE(keyboard_factory_scan_pins);
+#endif
diff --git a/board/osiris/board.h b/board/osiris/board.h
new file mode 100644
index 0000000000..0c6cf2397e
--- /dev/null
+++ b/board/osiris/board.h
@@ -0,0 +1,202 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Osiris board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "compile_time_macros.h"
+
+/* Baseboard features */
+#include "baseboard.h"
+
+/*
+ * This will happen automatically on NPCX9 ES2 and later. Do not remove
+ * until we can confirm all earlier chips are out of service.
+ */
+#define CONFIG_HIBERNATE_PSL_VCC1_RST_WAKEUP
+
+#define CONFIG_MP2964
+
+/* Tablet mode is not supported */
+#undef CONFIG_TABLET_MODE
+#undef CONFIG_TABLET_MODE_SWITCH
+#undef CONFIG_LID_ANGLE
+
+/* LED */
+#define CONFIG_LED_ONOFF_STATES
+
+/* USB Type A Features */
+#define USB_PORT_COUNT 1
+#define CONFIG_USB_PORT_POWER_DUMB
+
+#undef CONFIG_USB_PD_TCPM_NCT38XX
+#define CONFIG_USB_PD_TCPM_PS8815 /* C0 and C1 */
+
+#define CONFIG_USB_PD_FRS_PPC
+
+#define CONFIG_USB_PD_TCPM_PS8815
+#define CONFIG_USB_PD_TCPM_PS8815_FORCE_DID
+
+/* Retimer */
+#undef CONFIG_USBC_RETIMER_INTEL_BB
+
+/* I2C speed console command */
+#define CONFIG_CMD_I2C_SPEED
+
+/* I2C control host command */
+#define CONFIG_HOSTCMD_I2C_CONTROL
+
+#define CONFIG_USBC_PPC_SYV682X
+
+/* TODO: b/177608416 - measure and check these values on osiris */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
+
+/*
+ * Passive USB-C cables only support up to 60W.
+ */
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
+
+#define CONFIG_CHARGER_PROFILE_OVERRIDE
+#define CONFIG_PWR_STATE_DISCHARGE_FULL
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
+
+/*
+ * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
+ * signal.
+ */
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
+
+/* I2C Bus Configuration */
+
+#define I2C_PORT_RGBKB NPCX_I2C_PORT0_0
+
+#define I2C_PORT_USB_C0_C2_TCPC NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1
+
+#define I2C_PORT_USB_C0_C2_PPC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1
+
+#define I2C_PORT_USB_C0_C2_BC12 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1
+
+#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1
+
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+
+#define I2C_ADDR_MP2964_FLAGS 0x20
+
+/* Thermal features */
+#define CONFIG_THERMISTOR
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_TEMP_SENSOR_POWER
+#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
+
+#define CONFIG_FANS FAN_CH_COUNT
+#define CONFIG_FAN_RPM_CUSTOM
+
+/* Charger defines */
+#define CONFIG_CHARGER_ISL9241
+#define CONFIG_CHARGE_RAMP_SW
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+
+/* shutdown if soc <= 3%, default is 4% */
+#undef CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE
+#define CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE 3
+
+#undef CONFIG_VOLUME_BUTTONS
+
+/* RGB Keyboard */
+#define CONFIG_KEYBOARD_BACKLIGHT
+#define GPIO_RGBKBD_SDB_L GPIO_EC_KB_BL_EN_L
+#ifdef SECTION_IS_RW
+#define CONFIG_RGB_KEYBOARD
+#define CONFIG_LED_DRIVER_IS31FL3733B /* is31fl3733b on I2C */
+#endif
+#define RGB_GRID0_COL 12
+#define RGB_GRID0_ROW 1
+#define I2C_PORT_KBMCU I2C_PORT_RGBKB
+
+#define CONFIG_KEYBOARD_REFRESH_ROW3
+
+#define CONFIG_KEYBOARD_FACTORY_TEST
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h" /* needed by registers.h */
+#include "registers.h"
+#include "usbc_config.h"
+
+enum adc_channel {
+	ADC_TEMP_SENSOR_1_DDR_SOC,
+	ADC_TEMP_SENSOR_2_AMBIENT,
+	ADC_TEMP_SENSOR_3_CHARGER,
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1_DDR_SOC,
+	TEMP_SENSOR_2_AMBIENT,
+	TEMP_SENSOR_3_CHARGER,
+	TEMP_SENSOR_COUNT
+};
+
+enum battery_type { BATTERY_COSMX_AP22ABN, BATTERY_TYPE_COUNT };
+
+enum pwm_channel {
+	PWM_CH_FAN = 0, /* PWM5 */
+	PWM_CH_FAN2, /* PWM3 */
+	PWM_CH_COUNT
+};
+
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_1, FAN_CH_COUNT };
+
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_1, MFT_CH_COUNT };
+
+#ifdef CONFIG_KEYBOARD_FACTORY_TEST
+extern const int keyboard_factory_scan_pins[][2];
+extern const int keyboard_factory_scan_pins_used;
+#endif
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/osiris/build.mk b/board/osiris/build.mk
new file mode 100644
index 0000000000..fc29a4bb0e
--- /dev/null
+++ b/board/osiris/build.mk
@@ -0,0 +1,25 @@
+# -*- makefile -*-
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Osiris board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx9
+CHIP_VARIANT:=npcx9m3f
+BASEBOARD:=brya
+
+board-y=
+board-y+=battery.o
+board-y+=board.o
+board-y+=charger.o
+board-y+=fans.o
+board-y+=fw_config.o
+board-y+=i2c.o
+board-y+=keyboard.o
+board-y+=led.o
+board-y+=pwm.o
+board-y+=sensors.o
+board-y+=usbc_config.o
diff --git a/board/osiris/charger.c b/board/osiris/charger.c
new file mode 100644
index 0000000000..76e2712181
--- /dev/null
+++ b/board/osiris/charger.c
@@ -0,0 +1,80 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/charger/isl9241.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/* Charger Chip Configuration */
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = ISL9241_ADDR_FLAGS,
+		.drv = &isl9241_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CHARGER_NUM);
+
+int board_set_active_charge_port(int port)
+{
+	int is_valid_port = board_is_usb_pd_port_present(port);
+	int i;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTSUSB("Disabling all charger ports");
+
+		/* Disable all ports. */
+		for (i = 0; i < ppc_cnt; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (ppc_vbus_sink_enable(i, 0))
+				CPRINTSUSB("Disabling C%d as sink failed.", i);
+		}
+
+		return EC_SUCCESS;
+	} else if (!is_valid_port) {
+		return EC_ERROR_INVAL;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (ppc_is_sourcing_vbus(port)) {
+		CPRINTFUSB("Skip enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTSUSB("New charge port: C%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < ppc_cnt; i++) {
+		if (i == port)
+			continue;
+
+		if (ppc_vbus_sink_enable(i, 0))
+			CPRINTSUSB("C%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTSUSB("C%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/board/osiris/ec.tasklist b/board/osiris/ec.tasklist
new file mode 100644
index 0000000000..1b6c9cb361
--- /dev/null
+++ b/board/osiris/ec.tasklist
@@ -0,0 +1,30 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ *
+ * USB_CHG_Px tasks must be contiguous (see USB_CHG_PORT_TO_TASK_ID(x)).
+ * PD_Cx tasks must be contiguous (see PD_PORT_TO_TASK_ID(x))
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, HOOKS_TASK_STACK_SIZE) \
+	TASK_ALWAYS_RW(RGBKBD, rgbkbd_task, NULL, BASEBOARD_RGBKBD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, BASEBOARD_CHG_RAMP_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, BASEBOARD_CHARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, BASEBOARD_CHIPSET_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, CONSOLE_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, BASEBOARD_POWERBTN_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_shared_alert_task, (BIT(2) | BIT(0)), BASEBOARD_PD_INT_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, BASEBOARD_PD_INT_TASK_STACK_SIZE)
diff --git a/board/osiris/fans.c b/board/osiris/fans.c
new file mode 100644
index 0000000000..af7bc1e17f
--- /dev/null
+++ b/board/osiris/fans.c
@@ -0,0 +1,220 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Physical fans. These are logically separate from pwm_channels. */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "fan.h"
+#include "fan_chip.h"
+#include "hooks.h"
+#include "pwm.h"
+#include "util.h"
+
+/* MFT channels. These are logically separate from pwm_channels. */
+const struct mft_t mft_channels[] = {
+	[MFT_CH_0] = {
+		.module = NPCX_MFT_MODULE_1,
+		.clk_src = TCKC_LFCLK,
+		.pwm_id = PWM_CH_FAN,
+	},
+	[MFT_CH_1] = {
+		.module = NPCX_MFT_MODULE_2,
+		.clk_src = TCKC_LFCLK,
+		.pwm_id = PWM_CH_FAN2,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
+
+static const struct fan_conf fan_conf_0 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
+	.pgood_gpio = -1,
+	.enable_gpio = GPIO_EN_PP5000_FAN,
+};
+
+static const struct fan_conf fan_conf_1 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_1, /* Use MFT id to control fan */
+	.pgood_gpio = -1,
+	.enable_gpio = GPIO_EN_PP5000_FAN2,
+};
+
+/*
+ * TODO(b/234545460): thermistor placement and calibration
+ *
+ * Prototype fan spins at about 4200 RPM at 100% PWM, this
+ * is specific to board ID 2 and might also apears in later
+ * boards as well.
+ */
+static const struct fan_rpm fan_rpm_0 = {
+	.rpm_min = 2500,
+	.rpm_start = 2500,
+	.rpm_max = 6000,
+};
+
+static const struct fan_rpm fan_rpm_1 = {
+	.rpm_min = 2500,
+	.rpm_start = 2500,
+	.rpm_max = 6000,
+};
+
+const struct fan_t fans[FAN_CH_COUNT] = {
+	[FAN_CH_0] = {
+		.conf = &fan_conf_0,
+		.rpm = &fan_rpm_0,
+	},
+	[FAN_CH_1] = {
+		.conf = &fan_conf_1,
+		.rpm = &fan_rpm_1,
+	},
+};
+
+/* fan control */
+
+struct fan_step {
+	int on;
+	int off;
+	int rpm;
+};
+
+struct fan_table_config {
+	/* number of control_table */
+	uint8_t step;
+	/* fan control table */
+	const struct fan_step *control_table;
+};
+
+const struct fan_step fan_table0[] = {
+	{ .on = 25, .off = 0, .rpm = 0 },
+	{ .on = 37, .off = 34, .rpm = 2500 },
+	{ .on = 42, .off = 39, .rpm = 2800 },
+	{ .on = 46, .off = 43, .rpm = 3000 },
+	{ .on = 51, .off = 48, .rpm = 3200 },
+	{ .on = 55, .off = 52, .rpm = 3600 },
+	{ .on = 59, .off = 56, .rpm = 4000 },
+	{ .on = 66, .off = 63, .rpm = 4600 },
+	{ .on = 72, .off = 69, .rpm = 5000 },
+	{ .on = 74, .off = 71, .rpm = 5500 },
+};
+const int fan_table0_count = ARRAY_SIZE(fan_table0);
+
+const struct fan_step fan_table1[] = {
+	{ .on = 25, .off = 0, .rpm = 0 },
+	{ .on = 51, .off = 48, .rpm = 3200 },
+	{ .on = 55, .off = 52, .rpm = 3600 },
+	{ .on = 59, .off = 56, .rpm = 4000 },
+	{ .on = 66, .off = 63, .rpm = 4600 },
+	{ .on = 72, .off = 69, .rpm = 5000 },
+	{ .on = 74, .off = 71, .rpm = 5500 },
+};
+const int fan_table1_count = ARRAY_SIZE(fan_table1);
+
+/* Fan control configuration */
+static struct fan_table_config fan_tables[] = {
+	[FAN_CH_0] = {
+		.step = fan_table0_count,
+		.control_table = (const struct fan_step *) &fan_table0,
+	},
+	[FAN_CH_1] = {
+		.step = fan_table1_count,
+		.control_table = (const struct fan_step *) &fan_table1,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(fan_tables) == FAN_CH_COUNT);
+
+static int current_level[] = { 0, 0 };
+BUILD_ASSERT(ARRAY_SIZE(current_level) == FAN_CH_COUNT);
+
+static int previous_level[] = { 0, 0 };
+BUILD_ASSERT(ARRAY_SIZE(previous_level) == FAN_CH_COUNT);
+
+#undef BOARD_FAN_TEST
+
+#ifdef BOARD_FAN_TEST
+static int manual_temp = -1;
+#endif
+
+int fan_percent_to_rpm(int fan, int pct)
+{
+	static struct fan_table_config *fan_table;
+	static int previous_pct;
+	int i;
+
+	fan_table = &fan_tables[fan];
+
+#ifdef BOARD_FAN_TEST
+	if (manual_temp != -1)
+		pct = manual_temp;
+#endif
+
+	/*
+	 * Compare the pct and previous pct, we have the three paths :
+	 *  1. decreasing path. (check the off point)
+	 *  2. increasing path. (check the on point)
+	 *  3. invariant path. (return the current RPM)
+	 */
+	if (pct < previous_pct) {
+		for (i = current_level[fan]; i >= 0; i--) {
+			if (pct <= fan_table->control_table[i].off)
+				current_level[fan] = i - 1;
+			else
+				break;
+		}
+	} else if (pct > previous_pct) {
+		for (i = current_level[fan] + 1; i < fan_table->step; i++) {
+			if (pct >= fan_table->control_table[i].on)
+				current_level[fan] = i;
+			else
+				break;
+		}
+	}
+
+	if (current_level[fan] < 0)
+		current_level[fan] = 0;
+
+	if (current_level[fan] != previous_level[fan])
+		cprints(CC_THERMAL, "Fan %d: Set fan RPM to %d", fan,
+			fan_table->control_table[current_level[fan]].rpm);
+
+	if (fan == (FAN_CH_COUNT - 1))
+		previous_pct = pct;
+
+#ifdef BOARD_FAN_TEST
+	if (manual_temp != -1)
+		ccprints("Fan%d: temps:%d curr:%d prev:%d rpm:%d", fan, pct,
+			 current_level[fan], previous_level[fan],
+			 fan_table->control_table[current_level[fan]].rpm);
+#endif
+
+	previous_level[fan] = current_level[fan];
+
+	return fan_table->control_table[current_level[fan]].rpm;
+}
+
+#ifdef BOARD_FAN_TEST
+static int command_fan_test(int argc, const char **argv)
+{
+	char *e;
+	int t;
+
+	if (argc > 1) {
+		t = strtoi(argv[1], &e, 0);
+		if (*e) {
+			ccprints("Invalid test temp");
+			return EC_ERROR_INVAL;
+		}
+		manual_temp = t;
+		ccprints("manual temp is %d", manual_temp);
+		return EC_SUCCESS;
+	}
+	manual_temp = -1;
+	ccprints("manual temp reset");
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(fan_test, command_fan_test, "[temperature]",
+			"set manual temperature for fan test");
+#endif
diff --git a/board/osiris/fw_config.c b/board/osiris/fw_config.c
new file mode 100644
index 0000000000..1fb085fe6e
--- /dev/null
+++ b/board/osiris/fw_config.c
@@ -0,0 +1,40 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "fw_config.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+static union osiris_cbi_fw_config fw_config;
+BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
+
+/*
+ * FW_CONFIG defaults for osiris if the CBI.FW_CONFIG data is not
+ * initialized.
+ */
+static const union osiris_cbi_fw_config fw_config_defaults = {
+	.kb_bl = KEYBOARD_BACKLIGHT_ENABLED,
+};
+
+/****************************************************************************
+ * Osiris FW_CONFIG access
+ */
+void board_init_fw_config(void)
+{
+	if (cbi_get_fw_config(&fw_config.raw_value)) {
+		CPRINTS("CBI: Read FW_CONFIG failed, using board defaults");
+		fw_config = fw_config_defaults;
+	}
+}
+
+union osiris_cbi_fw_config get_fw_config(void)
+{
+	return fw_config;
+}
diff --git a/board/osiris/fw_config.h b/board/osiris/fw_config.h
new file mode 100644
index 0000000000..fb776dc5a4
--- /dev/null
+++ b/board/osiris/fw_config.h
@@ -0,0 +1,39 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __BOARD_OSIRIS_FW_CONFIG_H_
+#define __BOARD_OSIRIS_FW_CONFIG_H_
+
+#include <stdint.h>
+
+/****************************************************************************
+ * CBI FW_CONFIG layout for Osiris board.
+ *
+ * Source of truth is the project/brya/osiris/config.star configuration file.
+ */
+
+enum ec_cfg_keyboard_backlight_type {
+	KEYBOARD_BACKLIGHT_DISABLED = 0,
+	KEYBOARD_BACKLIGHT_ENABLED = 1
+};
+
+union osiris_cbi_fw_config {
+	struct {
+		enum ec_cfg_keyboard_backlight_type kb_bl : 1;
+		uint32_t reserved_1 : 1;
+		uint32_t audio : 2;
+		uint32_t reserved_2 : 28;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Read the cached FW_CONFIG.  Guaranteed to have valid values.
+ *
+ * @return the FW_CONFIG for the board.
+ */
+union osiris_cbi_fw_config get_fw_config(void);
+
+#endif /* __BOARD_OSIRIS_FW_CONFIG_H_ */
diff --git a/board/osiris/gpio.inc b/board/osiris/gpio.inc
new file mode 100644
index 0000000000..ea196571f8
--- /dev/null
+++ b/board/osiris/gpio.inc
@@ -0,0 +1,142 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define MODULE_KB		MODULE_KEYBOARD_SCAN
+
+/* INTERRUPT GPIOs: */
+GPIO_INT(ACOK_OD,                        PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
+GPIO_INT(EC_PROCHOT_IN_L,                PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
+GPIO_INT(EC_WP_ODL,                      PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(GSC_EC_PWR_BTN_ODL,             PIN(0, 1), GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW, power_button_interrupt)
+GPIO_INT(LID_OPEN,                       PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
+GPIO_INT(SEQ_EC_ALL_SYS_PG,              PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_DSW_PWROK,               PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_RSMRST_ODL,              PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,                       PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,                      PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SYS_SLP_S0IX_L,                 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(USB_C0_BC12_INT_ODL,            PIN(C, 6), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C0_C2_TCPC_INT_ODL,         PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C0_PPC_INT_ODL,             PIN(6, 2), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C0_RT_INT_ODL,              PIN(B, 1), GPIO_INT_FALLING, retimer_interrupt)
+GPIO_INT(USB_C1_BC12_INT_ODL,            PIN(5, 0), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C1_PPC_INT_ODL,             PIN(F, 5), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C1_TCPC_INT_ODL,            PIN(A, 2), GPIO_INT_FALLING, tcpc_alert_event)
+
+/* USED GPIOs: */
+GPIO(CCD_MODE_ODL,                   PIN(E, 5), GPIO_INPUT)
+GPIO(CHARGER_VAP_OTG_EN,             PIN(4, 1), GPIO_OUT_LOW)
+GPIO(CPU_C10_GATE_L,                 PIN(6, 7), GPIO_INPUT)
+GPIO(EC_BATT_PRES_ODL,               PIN(A, 3), GPIO_INPUT)
+GPIO(EC_ENTERING_RW,                 PIN(0, 3), GPIO_OUT_LOW)
+GPIO(EC_EN_EDP_BL,                   PIN(D, 3), GPIO_OUT_HIGH)
+GPIO(EC_GSC_PACKET_MODE,             PIN(7, 5), GPIO_OUT_LOW)
+GPIO(EC_I2C_BAT_SCL,                 PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_BAT_SDA,                 PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SCL_R,              PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SDA_R,              PIN(B, 2), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,              PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SENSOR_SDA,              PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_USB_C0_C2_PPC_BC_SCL,    PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_PPC_BC_SDA,    PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_TCPC_SCL,      PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_TCPC_SDA,      PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_MIX_SCL,          PIN(E, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_MIX_SDA,          PIN(E, 3), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_TCPC_SCL,         PIN(F, 3), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_TCPC_SDA,         PIN(F, 2), GPIO_INPUT)
+GPIO(EC_KB_BL_EN_L,                  PIN(8, 6), GPIO_OUT_LOW)
+GPIO(EC_PCHHOT_ODL,                  PIN(7, 4), GPIO_INPUT)
+GPIO(EC_PCH_INT_ODL,                 PIN(B, 0), GPIO_ODR_HIGH)
+GPIO(EC_PCH_PWR_BTN_ODL,             PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(EC_PCH_RSMRST_L,                PIN(A, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_RTCRST,                  PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_SYS_PWROK,               PIN(3, 7), GPIO_OUT_LOW)
+GPIO(EC_PCH_WAKE_R_ODL,              PIN(C, 0), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_ODL,                 PIN(6, 3), GPIO_ODR_HIGH)
+GPIO(EN_PP5000_FAN,                  PIN(6, 1), GPIO_OUT_LOW)
+GPIO(EN_PP5000_FAN2,                 PIN(9, 7), GPIO_OUT_LOW)
+GPIO(EN_PP5000_USBA_R,               PIN(D, 7), GPIO_OUT_LOW)
+GPIO(EN_S5_RAILS,                    PIN(B, 6), GPIO_OUT_LOW)
+GPIO(IMVP9_VRRDY_OD,                 PIN(4, 3), GPIO_INPUT)
+GPIO(PCH_PWROK,                      PIN(7, 2), GPIO_OUT_LOW)
+GPIO(SYS_RST_ODL,                    PIN(C, 5), GPIO_ODR_HIGH)
+GPIO(USB_C1_FRS_EN,                  PIN(9, 4), GPIO_OUT_LOW)
+GPIO(USB_C1_RST_ODL,                 PIN(9, 6), GPIO_ODR_LOW)
+GPIO(USB_C1_RT_INT_ODL,              PIN(A, 0), GPIO_INPUT)
+GPIO(USB_C1_RT_RST_R_ODL,            PIN(0, 2), GPIO_ODR_LOW)
+GPIO(VCCST_PWRGD_OD,                 PIN(A, 4), GPIO_ODR_LOW)
+GPIO(LED_1_L,                        PIN(C, 4), GPIO_OUT_HIGH)
+GPIO(LED_2_L,                        PIN(C, 3), GPIO_OUT_HIGH)
+GPIO(KYBL_EN,                        PIN(A, 7), GPIO_OUT_LOW)
+GPIO(AMP_PWR_EN,                     PIN(5, 7), GPIO_OUT_LOW)
+GPIO(RGB_KB_INT,                     PIN(5, 6), GPIO_INPUT)
+
+/* UART alternate functions */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)              /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */
+
+/* I2C alternate functions */
+ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)               /* GPIO33/I2C5_SCL0/CTS_L, GPIO36/RTS_L/I2C5_SDA0 */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)               /* GPIO87/I2C1_SDA0 */
+ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)               /* GPIO92/I2C2_SCL0, GPIO91/I2C2_SDA0, GPIO90/I2C1_SCL0 */
+ALTERNATE(PIN_MASK(B, 0x0c), 0, MODULE_I2C, 0)               /* GPIOB3/I2C7_SCL0/DCD_L, GPIOB2/I2C7_SDA0/DSR_L */
+ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, GPIO_SEL_1P8V)   /* GPIOB5/I2C0_SCL0, GPIOB4/I2C0_SDA0 */
+ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)               /* GPIOD1/I2C3_SCL0, GPIOD0/I2C3_SDA0 */
+ALTERNATE(PIN_MASK(E, 0x18), 0, MODULE_I2C, 0)               /* GPIOE4/I2C6_SCL1/I3C_SCL, GPIOE3/I2C6_SDA1/I3C_SDA */
+ALTERNATE(PIN_MASK(F, 0x0c), 0, MODULE_I2C, 0)               /* GPIOF3/I2C4_SCL1, GPIOF2/I2C4_SDA1 */
+
+/* PWM alternate functions */
+ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0)               /* GPIO40/TA1 */
+ALTERNATE(PIN_MASK(7, 0x08), 0, MODULE_PWM, 0)               /* GPIO73/TA2 */
+ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)               /* GPIO80/PWM3 */
+ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)               /* GPIOB7/PWM5 */
+
+/* ADC alternate functions */
+ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0)               /* GPIO34/PS2_DAT2/ADC6 */
+ALTERNATE(PIN_MASK(4, 0x34), 0, MODULE_ADC, 0)               /* GPIO42/ADC3/RI_L, GPIO45/ADC0, GPIO44/ADC1 */
+
+/* KB alternate functions */
+ALTERNATE(PIN_MASK(0, 0xf0), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO10&P80_CLK/GPIO07, KSO11&P80_DAT/GPIO06, KSO12/GPIO05, KSO13/GPIO04 */
+ALTERNATE(PIN_MASK(1, 0x7f), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO06/GPO13/GP_SEL_L, KSO07/GPO12/JEN_L, KSO03/GPIO16/JTAG_TDO0_SWO, KSO04/GPIO15/XNOR, KSO05/GPIO14, KSO08/GPIO11/CR_SOUT1, KSO09/GPIO10/CR_SIN1 */
+ALTERNATE(PIN_MASK(2, 0xfc), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI2/GPIO27/TRACEDATA1, KSI3/GPIO26/TRACEDATA0, KSI4/GPIO25/TRACECLK/GP_SCLK, KSI5/GPIO24/GP_MISO, KSI6/GPIO23/S_SBUB, KSI7/GPIO22/S_SBUA */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO00/GPIO21/JTAG_TCK_SWCLK, KSO01/GPIO20/JTAG_TMS_SWIO */
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI0/GPIO31/TRACEDATA3/GP_MOSI, KSI1/GPIO30/TRACEDATA2/GP_CS_L */
+ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO14/GPIO82 */
+
+/* PMU alternate functions */
+ALTERNATE(PIN_MASK(0, 0x01), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN2_L&GPI00/GPIO00 */
+ALTERNATE(PIN_MASK(0, 0x02), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW) /* GPIO01/PSL_IN3_L&GPI01 */
+ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN1_L&GPID2/GPIOD2 */
+
+/* Unused Pins */
+UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
+UNUSED(PIN(3, 2))       /* GPO32/TRIS_L */
+UNUSED(PIN(3, 4))       /* GPIO34 */
+UNUSED(PIN(3, 5))       /* GPO35/CR_SOUT4/TEST_L */
+UNUSED(PIN(6, 6))       /* GPIO66 */
+UNUSED(PIN(8, 3))       /* GPIO83 */
+UNUSED(PIN(7, 0))       /* GPIO70 */
+UNUSED(PIN(8, 1))       /* GPIO81 */
+UNUSED(PIN(9, 3))       /* GPIO93 */
+UNUSED(PIN(D, 0))       /* GPIOD0/I2C3_SDA0 */
+UNUSED(PIN(D, 1))       /* GPIOD1/I2C3_SCL0 */
+UNUSED(PIN(9, 5))       /* GPIO95 */
+
+/* Pre-configured PSL balls:  J8  K6 */
+
+/*
+ * The NPCX keyboard driver does not use named GPIOs to access
+ * keyboard scan pins, so we do not list them in *gpio.inc. However, when
+ * KEYBOARD_COL2_INVERTED is defined, this name is required.
+ */
+GPIO(EC_KSO_02_INV,               PIN(1, 7), GPIO_OUT_LOW)
+
+GPIO(USB_C0_OC_ODL,     PIN(D, 4), GPIO_ODR_HIGH)
+GPIO(USB_C0_FRS_EN,     PIN(6, 0), GPIO_LOW)
+GPIO(USB_C0_RT_RST_ODL, PIN(C, 2), GPIO_ODR_LOW)
+
+GPIO(USB_C1_OC_ODL,     PIN(E, 1), GPIO_ODR_HIGH)
\ No newline at end of file
diff --git a/board/osiris/i2c.c b/board/osiris/i2c.c
new file mode 100644
index 0000000000..2d0656c484
--- /dev/null
+++ b/board/osiris/i2c.c
@@ -0,0 +1,91 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "hooks.h"
+#include "i2c.h"
+
+#define BOARD_ID_FAST_PLUS_CAPABLE 2
+
+/* I2C port map configuration */
+const struct i2c_port_t i2c_ports[] = {
+	{
+		/* I2C0 */
+		.name = "rgbkb",
+		.port = I2C_PORT_RGBKB,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_SENSOR_SCL,
+		.sda = GPIO_EC_I2C_SENSOR_SDA,
+	},
+	{
+		/* I2C1 */
+		.name = "tcpc0,2",
+		.port = I2C_PORT_USB_C0_C2_TCPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C2_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C2_TCPC_SDA,
+	},
+	{
+		/* I2C2 */
+		.name = "ppc0,2",
+		.port = I2C_PORT_USB_C0_C2_PPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C2_PPC_BC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C2_PPC_BC_SDA,
+	},
+	{
+		/* I2C4 C1 TCPC */
+		.name = "tcpc1",
+		.port = I2C_PORT_USB_C1_TCPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C1_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C1_TCPC_SDA,
+		.flags = I2C_PORT_FLAG_DYNAMIC_SPEED,
+	},
+	{
+		/* I2C5 */
+		.name = "battery",
+		.port = I2C_PORT_BATTERY,
+		.kbps = 100,
+		.scl = GPIO_EC_I2C_BAT_SCL,
+		.sda = GPIO_EC_I2C_BAT_SDA,
+	},
+	{
+		/* I2C6 */
+		.name = "ppc1",
+		.port = I2C_PORT_USB_C1_PPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C1_MIX_SCL,
+		.sda = GPIO_EC_I2C_USB_C1_MIX_SDA,
+		.flags = I2C_PORT_FLAG_DYNAMIC_SPEED,
+	},
+	{
+		/* I2C7 */
+		.name = "eeprom",
+		.port = I2C_PORT_EEPROM,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_MISC_SCL_R,
+		.sda = GPIO_EC_I2C_MISC_SDA_R,
+	},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+/*
+ * I2C controllers are initialized in main.c. This sets the speed much
+ * later, but before I2C peripherals are initialized.
+ */
+static void set_board_legacy_i2c_speeds(void)
+{
+	if (get_board_id() >= BOARD_ID_FAST_PLUS_CAPABLE)
+		return;
+
+	ccprints("setting USB DB I2C buses to 400 kHz\n");
+
+	i2c_set_freq(I2C_PORT_USB_C1_TCPC, I2C_FREQ_400KHZ);
+	i2c_set_freq(I2C_PORT_USB_C1_PPC, I2C_FREQ_400KHZ);
+}
+DECLARE_HOOK(HOOK_INIT, set_board_legacy_i2c_speeds, HOOK_PRIO_INIT_I2C - 1);
diff --git a/board/osiris/keyboard.c b/board/osiris/keyboard.c
new file mode 100644
index 0000000000..cd557760eb
--- /dev/null
+++ b/board/osiris/keyboard.c
@@ -0,0 +1,140 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "hooks.h"
+#include "keyboard_8042_sharedlib.h"
+#include "keyboard_scan.h"
+#include "rgb_keyboard.h"
+#include "timer.h"
+
+#define CPRINTF(format, args...) cprintf(CC_KEYBOARD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ##args)
+
+const struct key {
+	uint8_t row;
+	uint8_t col;
+} vivaldi_keys[] = {
+	{ .row = 4, .col = 2 }, /* T1 */
+	{ .row = 3, .col = 2 }, /* T2 */
+	{ .row = 2, .col = 2 }, /* T3 */
+	{ .row = 1, .col = 2 }, /* T4 */
+	{ .row = 4, .col = 4 }, /* T5 */
+	{ .row = 3, .col = 4 }, /* T6 */
+	{ .row = 2, .col = 4 }, /* T7 */
+	{ .row = 2, .col = 9 }, /* T8 */
+	{ .row = 1, .col = 9 }, /* T9 */
+	{ .row = 1, .col = 4 }, /* T10 */
+	{ .row = 0, .col = 4 }, /* T11 */
+	{ .row = 1, .col = 5 }, /* T12 */
+	{ .row = 3, .col = 5 }, /* T13 */
+	{ .row = 2, .col = 1 }, /* T14 */
+	{ .row = 0, .col = 1 }, /* T15 */
+};
+BUILD_ASSERT(ARRAY_SIZE(vivaldi_keys) == MAX_TOP_ROW_KEYS);
+
+static const struct ec_response_keybd_config osiris_vivaldi_kb = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &osiris_vivaldi_kb;
+}
+
+extern struct rgbkbd_drv is31fl3733b_drv;
+
+static struct rgb_s grid0[RGB_GRID0_COL * RGB_GRID0_ROW];
+
+struct rgbkbd rgbkbds[] = {
+	[0] = {
+		.cfg = &(const struct rgbkbd_cfg) {
+			.drv = &is31fl3733b_drv,
+			.i2c = I2C_PORT_KBMCU,
+			.col_len = RGB_GRID0_COL,
+			.row_len = RGB_GRID0_ROW,
+		},
+		.buf = grid0,
+	},
+};
+const uint8_t rgbkbd_count = ARRAY_SIZE(rgbkbds);
+
+const uint8_t rgbkbd_hsize = RGB_GRID0_COL;
+const uint8_t rgbkbd_vsize = RGB_GRID0_ROW;
+
+enum ec_rgbkbd_type rgbkbd_type = EC_RGBKBD_TYPE_FOUR_ZONES_12_LEDS;
+
+#define LED(x, y) RGBKBD_COORD((x), (y))
+#define DELM RGBKBD_DELM
+
+const uint8_t rgbkbd_map[] = {
+	DELM, LED(0, 0), DELM, LED(1, 0), DELM, LED(2, 0),  DELM, LED(3, 0),
+	DELM, LED(4, 0), DELM, LED(5, 0), DELM, LED(6, 0),  DELM, LED(7, 0),
+	DELM, LED(8, 0), DELM, LED(9, 0), DELM, LED(10, 0), DELM, LED(11, 0),
+	DELM, DELM,
+};
+#undef LED
+#undef DELM
+const size_t rgbkbd_map_size = ARRAY_SIZE(rgbkbd_map);
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/* Increase from 50 us, because KSO_02 passes through the H1. */
+	.output_settle_us = 80,
+	/* Other values should be the same as the default configuration. */
+	.debounce_down_us = 9 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x1c, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0x86, 0xff, 0xff, 0x55, 0xff, 0xff, 0xff,
+		0xff  /* full set */
+	},
+};
+
+static uint16_t scancode_set2_rgb[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = {
+	{ 0x0000, 0x0000, 0x0014, 0xe01f, 0xe014, 0xe007, 0x0000, 0x0000 },
+	{ 0x001f, 0x0076, 0x0017, 0x000e, 0x001c, 0x003a, 0x000d, 0x0016 },
+	{ 0x006c, 0x000c, 0x0004, 0x0006, 0x0005, 0xe071, 0x0026, 0x002a },
+	{ 0x0032, 0x0034, 0x002c, 0x002e, 0x002b, 0x0029, 0x0025, 0x002d },
+	{ 0x0078, 0x0009, 0x0083, 0x000b, 0x0003, 0x0041, 0x001e, 0x001d },
+	{ 0x0051, 0x0007, 0x005b, 0x0000, 0x0042, 0x0022, 0x003e, 0x0043 },
+	{ 0x0031, 0x0033, 0x0035, 0x0036, 0x003b, 0x001b, 0x003d, 0x003c },
+	{ 0x0000, 0x0012, 0x0061, 0x0000, 0x0000, 0x0000, 0x0000, 0x0059 },
+	{ 0x0055, 0x0052, 0x0054, 0x004e, 0x004c, 0x0024, 0x0044, 0x004d },
+	{ 0x0045, 0x0001, 0x000a, 0x002f, 0x004b, 0x0049, 0x0046, 0x001A },
+	{ 0xe011, 0x0000, 0x006a, 0x0000, 0x005d, 0x0000, 0x0011, 0x0000 },
+	{ 0xe07a, 0x005d, 0xe075, 0x006b, 0x005a, 0xe072, 0x004a, 0x0066 },
+	{ 0xe06b, 0xe074, 0xe069, 0x0067, 0xe0c6, 0x0064, 0x0015, 0xe07d },
+	{ 0x0073, 0x0066, 0xe071, 0x005d, 0x005a, 0xe04a, 0x0070, 0x0021 },
+	{ 0x0023, 0xe05a, 0x0075, 0x0067, 0xe069, 0xe07a, 0x007d, 0x0069 },
+};
+
+static void keyboard_matrix_init(void)
+{
+	CPRINTS("%s", __func__);
+
+	register_scancode_set2((uint16_t *)&scancode_set2_rgb,
+			       sizeof(scancode_set2_rgb));
+}
+DECLARE_HOOK(HOOK_INIT, keyboard_matrix_init, HOOK_PRIO_PRE_DEFAULT);
diff --git a/board/osiris/led.c b/board/osiris/led.c
new file mode 100644
index 0000000000..f06cc17f8f
--- /dev/null
+++ b/board/osiris/led.c
@@ -0,0 +1,87 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ * Power and battery LED control for osiris
+ */
+
+#include "chipset.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+
+#define LED_ON_LVL 0
+#define LED_OFF_LVL 1
+
+#define GPIO_LED_BLUE_L GPIO_LED_1_L
+#define GPIO_LED_AMBER_L GPIO_LED_2_L
+
+__override const int led_charge_lvl_1 = 5;
+
+__override const int led_charge_lvl_2 = 95;
+
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_AMBER:
+		gpio_set_level(GPIO_LED_AMBER_L, LED_ON_LVL);
+		gpio_set_level(GPIO_LED_BLUE_L, LED_OFF_LVL);
+		break;
+	case EC_LED_COLOR_BLUE:
+		gpio_set_level(GPIO_LED_BLUE_L, LED_ON_LVL);
+		gpio_set_level(GPIO_LED_AMBER_L, LED_OFF_LVL);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		gpio_set_level(GPIO_LED_BLUE_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_AMBER_L, LED_OFF_LVL);
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		brightness_range[EC_LED_COLOR_BLUE] = 1;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(EC_LED_COLOR_AMBER);
+		else if (brightness[EC_LED_COLOR_BLUE] != 0)
+			led_set_color_battery(EC_LED_COLOR_BLUE);
+		else
+			led_set_color_battery(LED_OFF);
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/board/osiris/pwm.c b/board/osiris/pwm.c
new file mode 100644
index 0000000000..cc093a208f
--- /dev/null
+++ b/board/osiris/pwm.c
@@ -0,0 +1,20 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "hooks.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
+	[PWM_CH_FAN2] = { .channel = 3,
+			  .flags = PWM_CONFIG_OPEN_DRAIN,
+			  .freq = 25000 },
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
diff --git a/board/osiris/sensors.c b/board/osiris/sensors.c
new file mode 100644
index 0000000000..4232a1a3fa
--- /dev/null
+++ b/board/osiris/sensors.c
@@ -0,0 +1,107 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "accelgyro.h"
+#include "adc.h"
+#include "common.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "motion_sense.h"
+#include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
+#include "thermal.h"
+
+/* ADC configuration */
+const struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_1_DDR_SOC] = {
+		.name = "TEMP_DDR_SOC",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_2_AMBIENT] = {
+		.name = "TEMP_AMBIENT",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_3_CHARGER] = {
+		.name = "TEMP_CHARGER",
+		.input_ch = NPCX_ADC_CH6,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* Temperature sensor configuration */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1_DDR_SOC] = {
+		.name = "DDR and SOC",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_1_DDR_SOC,
+	},
+	[TEMP_SENSOR_2_AMBIENT] = {
+		.name = "Ambient",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_2_AMBIENT,
+	},
+	[TEMP_SENSOR_3_CHARGER] = {
+		.name = "Charger",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_3_CHARGER,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/*
+ * Temperature limit, See thermal table in b/234545460#comment16
+ * For real temperature in fan control table, set temp_fan_off
+ * and temp_fan_max to 0 and 99.
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(78), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
+		}, \
+		.temp_fan_off = C_TO_K(0), \
+		.temp_fan_max = C_TO_K(99), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
+
+#define THERMAL_UNUSED           \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = 0, \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = 0, \
+		}, \
+		.temp_fan_off = 0, \
+		.temp_fan_max = 0, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_unused =
+	THERMAL_UNUSED;
+
+struct ec_thermal_config thermal_params[] = {
+	[TEMP_SENSOR_1_DDR_SOC] = THERMAL_CPU,
+	[TEMP_SENSOR_2_AMBIENT] = THERMAL_UNUSED,
+	[TEMP_SENSOR_3_CHARGER] = THERMAL_UNUSED,
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
diff --git a/board/osiris/usbc_config.c b/board/osiris/usbc_config.c
new file mode 100644
index 0000000000..85d73b63cf
--- /dev/null
+++ b/board/osiris/usbc_config.c
@@ -0,0 +1,319 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi.h"
+#include "charge_ramp.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/bc12/pi3usb9201_public.h"
+#include "driver/ppc/syv682x_public.h"
+#include "driver/tcpm/ps8xxx_public.h"
+#include "driver/tcpm/tcpci.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "ioexpander.h"
+#include "system.h"
+#include "task.h"
+#include "task_id.h"
+#include "timer.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+/* USBC TCPC configuration */
+const struct tcpc_config_t tcpc_config[] = {
+	[USBC_PORT_C0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0_C2_TCPC,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
+			 TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V |
+			 TCPC_FLAGS_CONTROL_FRS,
+	},
+	[USBC_PORT_C1] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C1_TCPC,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
+			 TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V |
+			 TCPC_FLAGS_CONTROL_FRS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
+BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
+
+/******************************************************************************/
+/* USB-A charging control */
+
+#ifndef CONFIG_ZEPHYR
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_PP5000_USBA_R,
+};
+#endif
+BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
+
+/******************************************************************************/
+
+/* USBC PPC configuration */
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_C2_PPC,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.drv = &syv682x_drv,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C1_PPC,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.drv = &syv682x_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
+
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/*
+ * USB3 MB/DB mux configuration - the top level mux still needs to be set
+ * to the virtual_usb_mux_driver so the AP gets notified of mux changes
+ * and updates the TCSS configuration on state changes.
+ */
+
+static const struct usb_mux_chain usbc0_usb3_mb_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
+};
+
+static const struct usb_mux_chain usbc1_usb3_db_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
+};
+
+const struct usb_mux_chain usb_muxes[] = {
+	[USBC_PORT_C0] = {
+		.mux = &(const struct usb_mux) {
+			/* PS8815 MB */
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc0_usb3_mb_retimer,
+	},
+	[USBC_PORT_C1] = {
+		.mux = &(const struct usb_mux) {
+			/* PS8815 DB */
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc1_usb3_db_retimer,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
+
+/* BC1.2 charger detect configuration */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_C2_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C1_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
+
+#ifdef CONFIG_CHARGE_RAMP_SW
+
+/*
+ * TODO(b/181508008): tune this threshold
+ */
+
+#define BC12_MIN_VOLTAGE 4400
+
+/**
+ * Return true if VBUS is too low
+ */
+int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
+{
+	int voltage;
+
+	if (charger_get_vbus_voltage(port, &voltage))
+		voltage = 0;
+
+	if (voltage == 0) {
+		CPRINTS("%s: must be disconnected", __func__);
+		return 1;
+	}
+
+	if (voltage < BC12_MIN_VOLTAGE) {
+		CPRINTS("%s: port %d: vbus %d lower than %d", __func__, port,
+			voltage, BC12_MIN_VOLTAGE);
+		return 1;
+	}
+
+	return 0;
+}
+
+#endif /* CONFIG_CHARGE_RAMP_SW */
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * TODO(b/179648104): figure out correct timing
+	 */
+	gpio_set_level(GPIO_USB_C1_RST_ODL, 0);
+	gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 0);
+	gpio_set_level(GPIO_USB_C0_RT_RST_ODL, 0);
+
+	/*
+	 * delay for power-on to reset-off and min. assertion time
+	 */
+
+	msleep(20);
+
+	gpio_set_level(GPIO_USB_C1_RST_ODL, 1);
+	gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 1);
+	gpio_set_level(GPIO_USB_C0_RT_RST_ODL, 1);
+
+	/* wait for chips to come up */
+
+	msleep(50);
+}
+
+static void board_tcpc_init(void)
+{
+	/* Don't reset TCPCs after initial reset */
+	if (!system_jumped_late())
+		board_reset_pd_mcu();
+
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_C2_TCPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
+
+	/* Enable BC1.2 interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (gpio_get_level(GPIO_USB_C0_C2_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_0;
+
+	if (gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
+
+int ppc_get_alert_status(int port)
+{
+	if (port == USBC_PORT_C0)
+		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
+	else if (port == USBC_PORT_C1)
+		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
+	return 0;
+}
+
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_C2_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C1);
+		break;
+	default:
+		break;
+	}
+}
+
+void bc12_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_BC12_INT_ODL:
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+		break;
+	case GPIO_USB_C1_BC12_INT_ODL:
+		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+		break;
+	default:
+		break;
+	}
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C1);
+		break;
+	default:
+		break;
+	}
+}
+
+void retimer_interrupt(enum gpio_signal signal)
+{
+	/*
+	 * TODO(b/179513527): add USB-C support
+	 */
+}
+
+__override bool board_is_dts_port(int port)
+{
+	return port == USBC_PORT_C0;
+}
+
+__override bool board_is_tbt_usb4_port(int port)
+{
+	return false;
+}
+
+__override enum tbt_compat_cable_speed board_get_max_tbt_speed(int port)
+{
+	if (!board_is_tbt_usb4_port(port))
+		return TBT_SS_RES_0;
+
+	return TBT_SS_TBT_GEN3;
+}
diff --git a/board/osiris/usbc_config.h b/board/osiris/usbc_config.h
new file mode 100644
index 0000000000..dac4177f0c
--- /dev/null
+++ b/board/osiris/usbc_config.h
@@ -0,0 +1,19 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Osiris board-specific USB-C configuration */
+
+#ifndef __CROS_EC_USBC_CONFIG_H
+#define __CROS_EC_USBC_CONFIG_H
+
+#ifndef CONFIG_ZEPHYR
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#endif
+
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
+
+void config_usb_db_type(void);
+
+#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/osiris/vif_override.xml b/board/osiris/vif_override.xml
new file mode 100644
index 0000000000..6ade5d2f92
--- /dev/null
+++ b/board/osiris/vif_override.xml
@@ -0,0 +1,148 @@
+<?xml version="1.0" encoding="utf-8"?>
+<vif:VIF xmlns="http://usb.org/VendorInfoFile.xsd">
+  <vif:Product_Revision>2</vif:Product_Revision>
+  <vif:TID>0</vif:TID>
+  <vif:Product>
+    <vif:USB4_Num_Internal_Host_Controllers value="1" />
+    <vif:USB4_Num_PCIe_DN_Bridges value="0" />
+    <vif:USB4RouterList>
+      <vif:Usb4Router>
+        <!--USB4 Router 0-->
+        <vif:USB4_Router_ID value="0" />
+        <vif:USB4_Silicon_VID value="32903">8087</vif:USB4_Silicon_VID>
+        <vif:USB4_Num_Lane_Adapters value="4" />
+        <vif:USB4_Num_USB3_DN_Adapters value="1" />
+        <vif:USB4_Num_DP_IN_Adapters value="1" />
+        <vif:USB4_Num_DP_OUT_Adapters value="0" />
+        <vif:USB4_Num_PCIe_DN_Adapters value="4" />
+        <vif:USB4_TBT3_Not_Supported value="0">TBT3 Compatible</vif:USB4_TBT3_Not_Supported>
+        <vif:USB4_PCIe_Wake_Supported value="true" />
+        <vif:USB4_USB3_Wake_Supported value="false" />
+        <vif:USB4_Num_Unused_Adapters value="0" />
+        <vif:USB4_TBT3_VID value="32903">8087</vif:USB4_TBT3_VID>
+        <vif:USB4_PCIe_Switch_Vendor_ID value="32902">8086</vif:USB4_PCIe_Switch_Vendor_ID>
+        <vif:USB4_PCIe_Switch_Device_ID value="39451">9A1B</vif:USB4_PCIe_Switch_Device_ID>
+      </vif:Usb4Router>
+    </vif:USB4RouterList>
+  </vif:Product>
+
+  <vif:Component>
+    <vif:USB4_Max_Speed value="1">Gen 3 (40Gb)</vif:USB4_Max_Speed>
+
+    <!--;USB Host-->
+
+    <vif:Host_Speed value="4">USB 3.2 Gen 2x2</vif:Host_Speed>
+    <vif:Host_Contains_Captive_Retimer value="true" />
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:Host_Suspend_Supported value="true" />
+
+    <!--;PD Source-->
+    <!-- will we ever clear USB_Suspend_Supported? -->
+    <vif:USB_Suspend_May_Be_Cleared value="true" />
+
+    <!-- remove FR_Swap_* when we enable CONFIG_USB_PD_FRS -->
+    <!--;Dual Role-->
+    <vif:FR_Swap_Supported_As_Initial_Sink value="true" />
+    <!--;PD Source-->
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="3">3A @ 5V</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!--Source PDO 1-->
+        <vif:Src_PD_OCP_OC_Debounce value="50">50 msec</vif:Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="360">3600 mA</vif:Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+
+    <!-- SOP Discover ID -->
+    <vif:Product_Type_UFP_SOP value="2">PDUSB Peripheral</vif:Product_Type_UFP_SOP>
+    <vif:Product_Type_DFP_SOP value="2">PDUSB Host</vif:Product_Type_DFP_SOP>
+
+    <!-- USB4 Port -->
+    <vif:USB4_Lane_0_Adapter value="1" />
+    <vif:USB4_UFP_Supported value="false" />
+    <vif:USB4_DFP_Supported value="true" />
+    <vif:USB4_USB3_Tunneling_Supported value="true" />
+    <vif:USB4_DP_Tunneling_Supported value="true" />
+    <vif:USB4_CL1_State_Supported value="true" />
+    <vif:USB4_CL2_State_Supported value="true" />
+    <vif:USB4_Num_Retimers value="1" />
+    <vif:USB4_DP_Bit_Rate value="3">HBR3</vif:USB4_DP_Bit_Rate>
+    <vif:USB4_Num_DP_Lanes value="4">4 Lanes</vif:USB4_Num_DP_Lanes>
+
+  </vif:Component>
+
+  <vif:Component>
+    <vif:USB4_Supported value="false" />
+
+    <!--;USB Host-->
+    <vif:Host_Speed value="2">USB 3.2 Gen 2x1</vif:Host_Speed>
+    <vif:Host_Contains_Captive_Retimer value="true" />
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:Host_Suspend_Supported value="true" />
+
+    <!--;PD Source-->
+    <!-- will we ever clear USB_Suspend_Supported? -->
+    <vif:USB_Suspend_May_Be_Cleared value="true" />
+
+    <!-- remove FR_Swap_* when we enable CONFIG_USB_PD_FRS -->
+    <!--;Dual Role-->
+    <vif:FR_Swap_Supported_As_Initial_Sink value="true" />
+    <!--;PD Source-->
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="3">3A @ 5V</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!--Source PDO 1-->
+        <vif:Src_PD_OCP_OC_Debounce value="50">50 msec</vif:Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="360">3600 mA</vif:Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+
+    <!-- SOP Discover ID -->
+    <vif:Product_Type_UFP_SOP value="3">PSD</vif:Product_Type_UFP_SOP>
+    <vif:Product_Type_DFP_SOP value="2">PDUSB Host</vif:Product_Type_DFP_SOP>
+
+  </vif:Component>
+
+  <vif:Component>
+    <vif:USB4_Max_Speed value="1">Gen 3 (40Gb)</vif:USB4_Max_Speed>
+    <!--;USB Host-->
+    <vif:Host_Speed value="4">USB 3.2 Gen 2x2</vif:Host_Speed>
+    <vif:Host_Contains_Captive_Retimer value="true" />
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:Host_Suspend_Supported value="true" />
+
+    <!--;PD Source-->
+    <!-- will we ever clear USB_Suspend_Supported? -->
+    <vif:USB_Suspend_May_Be_Cleared value="true" />
+
+    <!-- remove FR_Swap_* when we enable CONFIG_USB_PD_FRS -->
+    <!--;Dual Role-->
+    <vif:FR_Swap_Supported_As_Initial_Sink value="true" />
+    <!--;PD Source-->
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="3">3A @ 5V</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!--Source PDO 1-->
+        <vif:Src_PD_OCP_OC_Debounce value="50">50 msec</vif:Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="360">3600 mA</vif:Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+
+    <!-- SOP Discover ID -->
+    <vif:Product_Type_UFP_SOP value="2">PDUSB Peripheral</vif:Product_Type_UFP_SOP>
+    <vif:Product_Type_DFP_SOP value="2">PDUSB Host</vif:Product_Type_DFP_SOP>
+
+    <!-- USB4 Port -->
+    <vif:USB4_Lane_0_Adapter value="1" />
+    <vif:USB4_UFP_Supported value="false" />
+    <vif:USB4_DFP_Supported value="true" />
+    <vif:USB4_USB3_Tunneling_Supported value="true" />
+    <vif:USB4_DP_Tunneling_Supported value="true" />
+    <vif:USB4_CL1_State_Supported value="true" />
+    <vif:USB4_CL2_State_Supported value="true" />
+    <vif:USB4_Num_Retimers value="1" />
+    <vif:USB4_DP_Bit_Rate value="3">HBR3</vif:USB4_DP_Bit_Rate>
+    <vif:USB4_Num_DP_Lanes value="4">4 Lanes</vif:USB4_Num_DP_Lanes>
+
+  </vif:Component>
+</vif:VIF>
diff --git a/board/palkia/battery.c b/board/palkia/battery.c
index 76e58aa618..ed7efdb423 100644
--- a/board/palkia/battery.c
+++ b/board/palkia/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/palkia/board.c b/board/palkia/board.c
index 939447fc17..342d3e05e9 100644
--- a/board/palkia/board.c
+++ b/board/palkia/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,6 @@
 /* Palkia board-specific configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "button.h"
 #include "common.h"
 #include "cros_board_info.h"
@@ -32,21 +31,20 @@
 #include "system.h"
 #include "task.h"
 #include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
 #include "thermal.h"
-#include "thermistor.h"
 #include "uart.h"
 #include "usb_charge.h"
 #include "usb_pd.h"
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static const uint8_t actual_key_mask[KEYBOARD_COLS_MAX] = {
-	0x01, 0x68, 0xbd, 0x03, 0x7e, 0xff, 0xff,
-	0xff, 0xff, 0x03, 0xfd, 0x48, 0x03, 0xff,
-	0xf7, 0x16  /* full set */
+	0x01, 0x68, 0xbd, 0x03, 0x7e, 0xff, 0xff, 0xff,
+	0xff, 0x03, 0xfd, 0x48, 0x03, 0xff, 0xf7, 0x16 /* full set */
 };
 
 /* GPIO to enable/disable the USB Type-A port. */
@@ -94,7 +92,7 @@ static void bc12_interrupt(enum gpio_signal signal)
 {
 	switch (signal) {
 	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
 		break;
 
 	default:
@@ -116,20 +114,21 @@ static void board_lid_interrupt(enum gpio_signal signal)
 	lid_interrupt(signal);
 }
 
-#include "gpio_list.h" /* Must come after other header files. */
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
 
 /******************************************************************************/
 /* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
+const struct spi_device_t spi_devices[] = {};
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
 /******************************************************************************/
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
 	[PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 },
-	[PWM_CH_FAN] = {.channel = 5, .flags = PWM_CONFIG_OPEN_DRAIN,
-			.freq = 25000},
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
@@ -140,17 +139,19 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = I2C_PORT_TCPC0,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
 		},
 		.drv = &ps8xxx_tcpm_drv,
 	}
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_TCPC_0] = {
-		.usb_port = USB_PD_PORT_TCPC_0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_0,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 	},
 };
 
@@ -166,7 +167,7 @@ const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
 
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
@@ -185,58 +186,63 @@ const struct fan_t fans[FAN_CH_COUNT] = {
 /******************************************************************************/
 /* MFT channels. These are logically separate from pwm_channels. */
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN },
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		"TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_2] = {
-		"TEMP_5V_REG", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_3] = {
-		"TEMP_AMB", NPCX_ADC_CH3, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_4] = {
-		"TEMP_CPU", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_1] = { "TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_2] = { "TEMP_5V_REG", NPCX_ADC_CH1, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_3] = { "TEMP_AMB", NPCX_ADC_CH3, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_4] = { "TEMP_CPU", NPCX_ADC_CH2, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Temp1",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Temp2",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "Temp3",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_3},
-	[TEMP_SENSOR_4] = {.name = "Temp4",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_4},
+	[TEMP_SENSOR_1] = { .name = "Temp1",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Temp2",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "Temp3",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
+	[TEMP_SENSOR_4] = { .name = "Temp4",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_4 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
 /* Palkia temperature control thresholds */
-const static struct ec_thermal_config thermal_a = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(90),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(60),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(65),
-	.temp_fan_max = C_TO_K(80),
-};
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_A                \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(90), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(60), \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+		.temp_fan_off = C_TO_K(65), \
+		.temp_fan_max = C_TO_K(80), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A;
 
 struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
 
diff --git a/board/palkia/board.h b/board/palkia/board.h
index 6164e872c1..d4de1aca39 100644
--- a/board/palkia/board.h
+++ b/board/palkia/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,10 +14,9 @@
 #define CONFIG_POWER_BUTTON
 #define CONFIG_KEYBOARD_PROTOCOL_8042
 #define CONFIG_LED_COMMON
-#define CONFIG_LED_POWER_LED
 #define CONFIG_LOW_POWER_IDLE
 
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 
 #undef CONFIG_UART_TX_BUF_SIZE
 #define CONFIG_UART_TX_BUF_SIZE 4096
@@ -47,7 +46,7 @@
  * Palkia' battery takes several seconds to come back out of its disconnect
  * state (~4.2 seconds on the unit I have, so give it a little more for margin).
  */
-#undef  CONFIG_POWER_BUTTON_INIT_TIMEOUT
+#undef CONFIG_POWER_BUTTON_INIT_TIMEOUT
 #define CONFIG_POWER_BUTTON_INIT_TIMEOUT 6
 
 /* BC 1.2 */
@@ -57,7 +56,7 @@
 #define CONFIG_FANS 1
 #undef CONFIG_FAN_INIT_SPEED
 #define CONFIG_FAN_INIT_SPEED 50
-#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_A_RAILS
+#define CONFIG_TEMP_SENSOR_POWER
 #define CONFIG_THERMISTOR
 #define CONFIG_THROTTLE_AP
 #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
@@ -71,15 +70,16 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_AC_PRESENT		GPIO_ACOK_OD
-#define GPIO_RSMRST_L_PGOOD	GPIO_PG_EC_RSMRST_L
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L
+#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
 
 #ifndef __ASSEMBLER__
 
@@ -87,18 +87,14 @@
 #include "registers.h"
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_1,	/* ADC0 */
-	ADC_TEMP_SENSOR_2,	/* ADC1 */
-	ADC_TEMP_SENSOR_3,	/* ADC3 */
-	ADC_TEMP_SENSOR_4,	/* ADC2 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
+	ADC_TEMP_SENSOR_3, /* ADC3 */
+	ADC_TEMP_SENSOR_4, /* ADC2 */
 	ADC_CH_COUNT
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_FAN,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_FAN, PWM_CH_COUNT };
 
 enum fan_channel {
 	FAN_CH_0 = 0,
diff --git a/board/palkia/build.mk b/board/palkia/build.mk
index cf0939b776..3ad9efe889 100644
--- a/board/palkia/build.mk
+++ b/board/palkia/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/palkia/ec.tasklist b/board/palkia/ec.tasklist
index be39ae64a2..2a0d89d14e 100644
--- a/board/palkia/ec.tasklist
+++ b/board/palkia/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/palkia/gpio.inc b/board/palkia/gpio.inc
index ec7ce25538..dfe92f8a81 100644
--- a/board/palkia/gpio.inc
+++ b/board/palkia/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,10 +16,10 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(PG_EC_RSMRST_L,       PIN(E, 2), GPIO_INT_BOTH, intel_x86_rsmrst_signal_interrupt)
diff --git a/board/palkia/keyboard_customization.c b/board/palkia/keyboard_customization.c
index 706ad18a4e..9356b5f152 100644
--- a/board/palkia/keyboard_customization.c
+++ b/board/palkia/keyboard_customization.c
@@ -1,32 +1,33 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "common.h"
-#include "keyboard_customization.h"
+#include "gpio.h"
 #include "keyboard_8042_sharedlib.h"
 #include "keyboard_config.h"
+#include "keyboard_customization.h"
 #include "keyboard_protocol.h"
 #include "keyboard_raw.h"
 
 static uint16_t scancode_set2[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = {
-	{0x0021, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
-	{0x0000, 0x0000, 0x0000, 0x0011, 0x0000, 0x0000, 0x0000, 0x0000},
-	{0x0015, 0x0000, 0x0014, 0x000d, 0x000e, 0x0016, 0x0000, 0x001c},
-	{0xe011, 0x0011, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
-	{0x0000, 0x0029, 0x0024, 0x000c, 0xe01f, 0x0026, 0x0004, 0x0000},
-	{0x0022, 0x001a, 0x0006, 0x0005, 0x001b, 0x001e, 0x001d, 0x0076},
-	{0x002a, 0x0032, 0x0034, 0x002c, 0x002e, 0x0025, 0x002d, 0x002b},
-	{0x003a, 0x0031, 0x0033, 0x0035, 0x0036, 0x003d, 0x003c, 0x003b},
-	{0x0049, 0xe072, 0x005d, 0x0044, 0x0009, 0x0046, 0x0000, 0x004b},
-	{0x0059, 0x0012, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
-	{0x0041, 0x0000, 0x0083, 0x000b, 0x0003, 0x003e, 0x0043, 0x0042},
-	{0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x0000, 0xe06b, 0x0000},
-	{0xe014, 0x0014, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
-	{0x004a, 0xe075, 0x004e, 0x0000, 0x0045, 0x004d, 0x0054, 0x004c},
-	{0x0052, 0x005a, 0x0000, 0x0000, 0x0055, 0x0066, 0x005b, 0x0023},
-	{0x0000, 0x000a, 0xe074, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
+	{ 0x0021, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 },
+	{ 0x0000, 0x0000, 0x0000, 0x0011, 0x0000, 0x0000, 0x0000, 0x0000 },
+	{ 0x0015, 0x0000, 0x0014, 0x000d, 0x000e, 0x0016, 0x0000, 0x001c },
+	{ 0xe011, 0x0011, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 },
+	{ 0x0000, 0x0029, 0x0024, 0x000c, 0xe01f, 0x0026, 0x0004, 0x0000 },
+	{ 0x0022, 0x001a, 0x0006, 0x0005, 0x001b, 0x001e, 0x001d, 0x0076 },
+	{ 0x002a, 0x0032, 0x0034, 0x002c, 0x002e, 0x0025, 0x002d, 0x002b },
+	{ 0x003a, 0x0031, 0x0033, 0x0035, 0x0036, 0x003d, 0x003c, 0x003b },
+	{ 0x0049, 0xe072, 0x005d, 0x0044, 0x0009, 0x0046, 0x0000, 0x004b },
+	{ 0x0059, 0x0012, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 },
+	{ 0x0041, 0x0000, 0x0083, 0x000b, 0x0003, 0x003e, 0x0043, 0x0042 },
+	{ 0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x0000, 0xe06b, 0x0000 },
+	{ 0xe014, 0x0014, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 },
+	{ 0x004a, 0xe075, 0x004e, 0x0000, 0x0045, 0x004d, 0x0054, 0x004c },
+	{ 0x0052, 0x005a, 0x0000, 0x0000, 0x0055, 0x0066, 0x005b, 0x0023 },
+	{ 0x0000, 0x000a, 0xe074, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 },
 };
 
 uint16_t get_scancode_set2(uint8_t row, uint8_t col)
@@ -62,49 +63,41 @@ void board_keyboard_drive_col(int col)
 }
 
 #ifdef CONFIG_KEYBOARD_DEBUG
-static char keycap_label[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = {
-	{'c',        KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
-		KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO},
-	{KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
-		KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO},
-	{'q',        KLLI_UNKNO, KLLI_UNKNO, KLLI_TAB,   '`',
-		'1',        KLLI_UNKNO, 'a'},
-	{KLLI_R_ALT, KLLI_L_ALT, KLLI_UNKNO, KLLI_UNKNO,
-		KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO},
-	{KLLI_UNKNO, KLLI_SPACE, 'e',        KLLI_F4,
-		KLLI_SEARC, '3',        KLLI_F3,    KLLI_UNKNO},
-	{'x',        'z',        KLLI_F2,    KLLI_F1,
-		's',        '2',        'w',        KLLI_ESC},
-	{'v',        'b',        'g',        't',
-		'5',        '4',        'r',        'f'},
-	{'m',        'n',        'h',        'y',
-		'6',        '7',        'u',        'j'},
-	{'.',        KLLI_DOWN,  '\\',       'o',
-		KLLI_F10,   '9',        KLLI_UNKNO, 'l'},
-	{KLLI_R_SHT, KLLI_L_SHT, KLLI_UNKNO, KLLI_UNKNO,
-		KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO},
-	{',',        KLLI_UNKNO, KLLI_F7,    KLLI_F6,
-		KLLI_F5,    '8',        'i',        'k'},
-	{KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_F9,
-		KLLI_UNKNO, KLLI_UNKNO, KLLI_LEFT,  KLLI_UNKNO},
-	{KLLI_R_CTR, KLLI_L_CTR, KLLI_UNKNO, KLLI_UNKNO,
-		KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO},
-	{'/',        KLLI_UP,    '-',        KLLI_UNKNO,
-		'0',        'p',        '[',        ';'},
-	{'\'',       KLLI_ENTER, KLLI_UNKNO, KLLI_UNKNO,
-		'=',        KLLI_B_SPC, ']',        'd'},
-	{KLLI_UNKNO, KLLI_F8,    KLLI_RIGHT, KLLI_UNKNO,
-		KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO},
+static uint8_t keycap_label[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = {
+	{ 'c', KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO },
+	{ KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO },
+	{ 'q', KLLI_UNKNO, KLLI_UNKNO, KLLI_TAB, '`', '1', KLLI_UNKNO, 'a' },
+	{ KLLI_R_ALT, KLLI_L_ALT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO },
+	{ KLLI_UNKNO, KLLI_SPACE, 'e', KLLI_F4, KLLI_SEARC, '3', KLLI_F3,
+	  KLLI_UNKNO },
+	{ 'x', 'z', KLLI_F2, KLLI_F1, 's', '2', 'w', KLLI_ESC },
+	{ 'v', 'b', 'g', 't', '5', '4', 'r', 'f' },
+	{ 'm', 'n', 'h', 'y', '6', '7', 'u', 'j' },
+	{ '.', KLLI_DOWN, '\\', 'o', KLLI_F10, '9', KLLI_UNKNO, 'l' },
+	{ KLLI_R_SHT, KLLI_L_SHT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO },
+	{ ',', KLLI_UNKNO, KLLI_F7, KLLI_F6, KLLI_F5, '8', 'i', 'k' },
+	{ KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_F9, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_LEFT, KLLI_UNKNO },
+	{ KLLI_R_CTR, KLLI_L_CTR, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO },
+	{ '/', KLLI_UP, '-', KLLI_UNKNO, '0', 'p', '[', ';' },
+	{ '\'', KLLI_ENTER, KLLI_UNKNO, KLLI_UNKNO, '=', KLLI_B_SPC, ']', 'd' },
+	{ KLLI_UNKNO, KLLI_F8, KLLI_RIGHT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO },
 };
 
-char get_keycap_label(uint8_t row, uint8_t col)
+uint8_t get_keycap_label(uint8_t row, uint8_t col)
 {
 	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS)
 		return keycap_label[col][row];
 	return KLLI_UNKNO;
 }
 
-void set_keycap_label(uint8_t row, uint8_t col, char val)
+void set_keycap_label(uint8_t row, uint8_t col, uint8_t val)
 {
 	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS)
 		keycap_label[col][row] = val;
diff --git a/board/palkia/keyboard_customization.h b/board/palkia/keyboard_customization.h
index 37ce1cf61f..fc97ffd728 100644
--- a/board/palkia/keyboard_customization.h
+++ b/board/palkia/keyboard_customization.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,47 +25,47 @@ extern uint8_t keyboard_cols;
 #define KEYBOARD_ROW_TO_MASK(r) (1 << (r))
 
 /* Columns and masks for keys we particularly care about */
-#define KEYBOARD_COL_DOWN	8
-#define KEYBOARD_ROW_DOWN	1
-#define KEYBOARD_MASK_DOWN	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_DOWN)
-#define KEYBOARD_COL_ESC	5
-#define KEYBOARD_ROW_ESC	7
-#define KEYBOARD_MASK_ESC	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_ESC)
-#define KEYBOARD_COL_KEY_H	7
-#define KEYBOARD_ROW_KEY_H	2
-#define KEYBOARD_MASK_KEY_H	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_H)
-#define KEYBOARD_COL_KEY_R	6
-#define KEYBOARD_ROW_KEY_R	6
-#define KEYBOARD_MASK_KEY_R	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_R)
-#define KEYBOARD_COL_LEFT_ALT	3
-#define KEYBOARD_ROW_LEFT_ALT	1
-#define KEYBOARD_MASK_LEFT_ALT	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_ALT)
-#define KEYBOARD_COL_REFRESH	4
-#define KEYBOARD_ROW_REFRESH	6
-#define KEYBOARD_MASK_REFRESH	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_REFRESH)
-#define KEYBOARD_COL_RIGHT_ALT	3
-#define KEYBOARD_ROW_RIGHT_ALT	0
-#define KEYBOARD_MASK_RIGHT_ALT	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_ALT)
-#define KEYBOARD_DEFAULT_COL_VOL_UP	8
-#define KEYBOARD_DEFAULT_ROW_VOL_UP	4
-#define KEYBOARD_COL_LEFT_CTRL  12
-#define KEYBOARD_ROW_LEFT_CTRL  1
+#define KEYBOARD_COL_DOWN 8
+#define KEYBOARD_ROW_DOWN 1
+#define KEYBOARD_MASK_DOWN KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_DOWN)
+#define KEYBOARD_COL_ESC 5
+#define KEYBOARD_ROW_ESC 7
+#define KEYBOARD_MASK_ESC KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_ESC)
+#define KEYBOARD_COL_KEY_H 7
+#define KEYBOARD_ROW_KEY_H 2
+#define KEYBOARD_MASK_KEY_H KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_H)
+#define KEYBOARD_COL_KEY_R 6
+#define KEYBOARD_ROW_KEY_R 6
+#define KEYBOARD_MASK_KEY_R KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_R)
+#define KEYBOARD_COL_LEFT_ALT 3
+#define KEYBOARD_ROW_LEFT_ALT 1
+#define KEYBOARD_MASK_LEFT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_ALT)
+#define KEYBOARD_COL_REFRESH 4
+#define KEYBOARD_ROW_REFRESH 6
+#define KEYBOARD_MASK_REFRESH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_REFRESH)
+#define KEYBOARD_COL_RIGHT_ALT 3
+#define KEYBOARD_ROW_RIGHT_ALT 0
+#define KEYBOARD_MASK_RIGHT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_ALT)
+#define KEYBOARD_DEFAULT_COL_VOL_UP 8
+#define KEYBOARD_DEFAULT_ROW_VOL_UP 4
+#define KEYBOARD_COL_LEFT_CTRL 12
+#define KEYBOARD_ROW_LEFT_CTRL 1
 #define KEYBOARD_MASK_LEFT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_CTRL)
 #define KEYBOARD_COL_RIGHT_CTRL 12
 #define KEYBOARD_ROW_RIGHT_CTRL 0
 #define KEYBOARD_MASK_RIGHT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_CTRL)
-#define KEYBOARD_COL_SEARCH     2
-#define KEYBOARD_ROW_SEARCH     3
-#define KEYBOARD_MASK_SEARCH    KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_SEARCH)
-#define KEYBOARD_COL_KEY_0      13
-#define KEYBOARD_ROW_KEY_0      4
-#define KEYBOARD_MASK_KEY_0     KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_0)
-#define KEYBOARD_COL_KEY_1      2
-#define KEYBOARD_ROW_KEY_1      5
-#define KEYBOARD_MASK_KEY_1     KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_1)
-#define KEYBOARD_COL_KEY_2      5
-#define KEYBOARD_ROW_KEY_2      5
-#define KEYBOARD_MASK_KEY_2     KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_2)
+#define KEYBOARD_COL_SEARCH 2
+#define KEYBOARD_ROW_SEARCH 3
+#define KEYBOARD_MASK_SEARCH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_SEARCH)
+#define KEYBOARD_COL_KEY_0 13
+#define KEYBOARD_ROW_KEY_0 4
+#define KEYBOARD_MASK_KEY_0 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_0)
+#define KEYBOARD_COL_KEY_1 2
+#define KEYBOARD_ROW_KEY_1 5
+#define KEYBOARD_MASK_KEY_1 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_1)
+#define KEYBOARD_COL_KEY_2 5
+#define KEYBOARD_ROW_KEY_2 5
+#define KEYBOARD_MASK_KEY_2 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_2)
 #define KEYBOARD_COL_LEFT_SHIFT 9
 #define KEYBOARD_ROW_LEFT_SHIFT 1
 #define KEYBOARD_MASK_LEFT_SHIFT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_SHIFT)
diff --git a/board/palkia/led.c b/board/palkia/led.c
index 1fa9295c80..a8ac1bcb44 100644
--- a/board/palkia/led.c
+++ b/board/palkia/led.c
@@ -1,46 +1,55 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Power and battery LED control for Palkia
  */
 
+#include "chipset.h"
 #include "ec_commands.h"
 #include "gpio.h"
 #include "led_common.h"
 #include "led_onoff_states.h"
-#include "chipset.h"
 
 #define LED_ON_LVL 0
 #define LED_OFF_LVL 1
 
-const int led_charge_lvl_1 = 5;
-
-const int led_charge_lvl_2 = 95;
+__override const int led_charge_lvl_1 = 5;
 
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+__override const int led_charge_lvl_2 = 95;
 
-const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	     3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	     3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    1 * LED_ONE_SEC },
+						  { LED_OFF,
+						    3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
 const enum ec_led_id supported_led_ids[] = {
 	EC_LED_ID_BATTERY_LED,
@@ -49,7 +58,7 @@ const enum ec_led_id supported_led_ids[] = {
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-void led_set_color_battery(enum ec_led_colors color)
+__override void led_set_color_battery(enum ec_led_colors color)
 {
 	switch (color) {
 	case EC_LED_COLOR_AMBER:
@@ -67,7 +76,7 @@ void led_set_color_battery(enum ec_led_colors color)
 	}
 }
 
-void led_set_color_power(enum ec_led_colors color)
+__override void led_set_color_power(enum ec_led_colors color)
 {
 	if (color == EC_LED_COLOR_WHITE)
 		gpio_set_level(GPIO_LED_3_L, LED_ON_LVL);
@@ -104,4 +113,3 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 
 	return EC_SUCCESS;
 }
-
diff --git a/board/palkia/vif_override.xml b/board/palkia/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/palkia/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/panqueque/board.c b/board/panqueque/board.c
new file mode 100644
index 0000000000..42df0896cb
--- /dev/null
+++ b/board/panqueque/board.c
@@ -0,0 +1,356 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Panqueque board-specific configuration */
+
+#include "common.h"
+#include "driver/ppc/sn5s330.h"
+#include "driver/tcpm/ps8xxx.h"
+#include "driver/tcpm/stm32gx.h"
+#include "driver/tcpm/tcpci.h"
+#include "driver/usb_mux/ps8822.h"
+#include "ec_version.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "switch.h"
+#include "system.h"
+#include "task.h"
+#include "uart.h"
+#include "usb_descriptor.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_dp_ufp.h"
+#include "usb_pe_sm.h"
+#include "usb_prl_sm.h"
+#include "usb_tc_sm.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+
+#define QUICHE_PD_DEBUG_LVL 1
+
+#ifdef SECTION_IS_RW
+#define CROS_EC_SECTION "RW"
+#else
+#define CROS_EC_SECTION "RO"
+#endif
+
+#ifdef SECTION_IS_RW
+static int pd_dual_role_init[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	PD_DRP_TOGGLE_ON,
+};
+
+static void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_HOST_USBC_PPC_INT_ODL:
+		sn5s330_interrupt(USB_PD_PORT_HOST);
+		break;
+	default:
+		break;
+	}
+}
+
+void hpd_interrupt(enum gpio_signal signal)
+{
+	usb_pd_hpd_edge_event(signal);
+}
+
+static void board_uf_manage_vbus_interrupt(enum gpio_signal signal)
+{
+	baseboard_usb3_check_state();
+}
+
+static void board_pwr_btn_interrupt(enum gpio_signal signal)
+{
+	baseboard_power_button_evt(gpio_get_level(signal));
+}
+
+static void board_usbc_usb3_interrupt(enum gpio_signal signal)
+{
+	baseboard_usbc_usb3_irq();
+}
+#endif /* SECTION_IS_RW */
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/*
+ * Table GPIO signals control both power rails and reset lines to various chips
+ * on the board. The order the signals are changed and the delay between GPIO
+ * signals is driven by USB/MST hub power sequencing requirements.
+ */
+const struct power_seq board_power_seq[] = {
+	{ GPIO_EN_AC_JACK, 1, 20 },
+	{ GPIO_EC_DFU_MUX_CTRL, 0, 0 },
+	{ GPIO_EN_PP5000_A, 1, 31 },
+	{ GPIO_MST_LP_CTL_L, 1, 0 },
+	{ GPIO_EN_PP3300_B, 1, 1 },
+	{ GPIO_EN_PP1100_A, 1, 100 + 30 },
+	{ GPIO_EN_BB, 1, 30 },
+	{ GPIO_EN_PP1050_A, 1, 30 },
+	{ GPIO_EN_PP1200_A, 1, 20 },
+	{ GPIO_EN_PP5000_C, 1, 20 },
+	{ GPIO_EN_PP5000_HSPORT, 1, 31 },
+	{ GPIO_EN_DP_SINK, 1, 80 },
+	{ GPIO_MST_RST_L, 1, 61 },
+	{ GPIO_EC_HUB2_RESET_L, 1, 41 },
+	{ GPIO_EC_HUB3_RESET_L, 1, 33 },
+	{ GPIO_DP_SINK_RESET, 1, 100 },
+	{ GPIO_USBC_UF_RESET_L, 1, 33 },
+	{ GPIO_DEMUX_DP_HDMI_PD_N, 1, 10 },
+	{ GPIO_DEMUX_DP_HDMI_MODE, 1, 5 },
+};
+const size_t board_power_seq_count = ARRAY_SIZE(board_power_seq);
+
+/*
+ * Define the strings used in our USB descriptors.
+ */
+const void *const usb_strings[] = {
+	[USB_STR_DESC] = usb_string_desc,
+	[USB_STR_VENDOR] = USB_STRING_DESC("Plugable"),
+	[USB_STR_PRODUCT] = USB_STRING_DESC("UC-MSTHDC"),
+	[USB_STR_SERIALNO] = 0,
+	[USB_STR_VERSION] =
+		USB_STRING_DESC(CROS_EC_SECTION ":" CROS_EC_VERSION32),
+	[USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"),
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
+
+#ifndef SECTION_IS_RW
+/* USB-C PPC Configuration */
+struct ppc_config_t ppc_chips[] = {
+	[USB_PD_PORT_HOST] = {
+		.i2c_port = I2C_PORT_I2C1,
+		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	},
+};
+#endif
+
+#ifdef SECTION_IS_RW
+/*
+ * PS8802 set mux board tuning.
+ * Adds in board specific gain and DP lane count configuration
+ */
+static int board_ps8822_mux_set(const struct usb_mux *me, mux_state_t mux_state)
+{
+	int rv = EC_SUCCESS;
+
+	/* DP specific config */
+	if (mux_state & USB_PD_MUX_DP_ENABLED)
+		rv = ps8822_set_dp_rx_eq(me, PS8822_DPEQ_LEVEL_UP_20DB);
+
+	return rv;
+}
+
+/* TCPCs */
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	[USB_PD_PORT_HOST] = {
+		.bus_type = EC_BUS_TYPE_EMBEDDED,
+		.drv = &stm32gx_tcpm_drv,
+	},
+};
+
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	[USB_PD_PORT_HOST] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_HOST,
+			.i2c_port = I2C_PORT_I2C1,
+			.i2c_addr_flags = PS8822_I2C_ADDR3_FLAG,
+			.driver = &ps8822_usb_mux_driver,
+			.board_set = &board_ps8822_mux_set,
+		},
+	},
+};
+
+/* USB-C PPC Configuration */
+struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	[USB_PD_PORT_HOST] = { .i2c_port = I2C_PORT_I2C1,
+			       .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+			       .drv = &sn5s330_drv },
+	[USB_PD_PORT_USB3] = { .i2c_port = I2C_PORT_I2C3,
+			       .i2c_addr_flags = SN5S330_ADDR1_FLAGS,
+			       .drv = &sn5s330_drv },
+};
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+const struct hpd_to_pd_config_t hpd_config = {
+	.port = USB_PD_PORT_HOST,
+	.signal = GPIO_DDI_MST_IN_HPD,
+};
+
+void board_reset_pd_mcu(void)
+{
+	cprints(CC_SYSTEM, "Resetting TCPCs...");
+	cflush();
+
+	gpio_set_level(GPIO_USBC_UF_RESET_L, 0);
+	msleep(PS8805_FW_INIT_DELAY_MS);
+	gpio_set_level(GPIO_USBC_UF_RESET_L, 1);
+	msleep(PS8805_FW_INIT_DELAY_MS);
+}
+
+void board_enable_usbc_interrupts(void)
+{
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_HOST_USBC_PPC_INT_ODL);
+	/* Enable HPD interrupt */
+	gpio_enable_interrupt(GPIO_DDI_MST_IN_HPD);
+	/* Enable VBUS control interrupt for C1 */
+	gpio_enable_interrupt(GPIO_USBC_UF_MUX_VBUS_EN);
+}
+
+void board_disable_usbc_interrupts(void)
+{
+	/* Disable PPC interrupts. */
+	gpio_disable_interrupt(GPIO_HOST_USBC_PPC_INT_ODL);
+	/* Disable HPD interrupt */
+	gpio_disable_interrupt(GPIO_DDI_MST_IN_HPD);
+	/* Disable VBUS control interrupt for C1 */
+	gpio_disable_interrupt(GPIO_USBC_UF_MUX_VBUS_EN);
+}
+
+void board_tcpc_init(void)
+{
+	board_reset_pd_mcu();
+
+	/* Enable board usbc interrupts */
+	board_enable_usbc_interrupts();
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 2);
+
+enum pd_dual_role_states board_tc_get_initial_drp_mode(int port)
+{
+	return pd_dual_role_init[port];
+}
+
+__override uint8_t board_get_usb_pd_port_count(void)
+{
+	/*
+	 * CONFIG_USB_PD_PORT_MAX_COUNT must be defined to account for C0
+	 * and C1, but TCPMv2 only knows about C0, as C1 is a type-c only
+	 * port that is managed directly by the PS8803 TCPC.
+	 */
+	return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
+}
+
+int ppc_get_alert_status(int port)
+{
+	if (port == USB_PD_PORT_HOST)
+		return gpio_get_level(GPIO_HOST_USBC_PPC_INT_ODL) == 0;
+
+	return 0;
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	return 0;
+}
+
+void board_overcurrent_event(int port, int is_overcurrented)
+{
+	/* TODO(b/174825406): check correct operation for honeybuns */
+}
+
+int dock_get_mf_preference(void)
+{
+	return MF_ON;
+}
+
+static void board_usb_tc_connect(void)
+{
+	int port = TASK_ID_TO_PD_PORT(task_get_current());
+
+	/*
+	 * The EC needs to indicate to the MST hub when the host port is
+	 * attached. GPIO_UFP_PLUG_DET is used for this purpose.
+	 */
+	if (port == USB_PD_PORT_HOST)
+		gpio_set_level(GPIO_UFP_PLUG_DET, 0);
+}
+DECLARE_HOOK(HOOK_USB_PD_CONNECT, board_usb_tc_connect, HOOK_PRIO_DEFAULT);
+
+static void board_usb_tc_disconnect(void)
+{
+	int port = TASK_ID_TO_PD_PORT(task_get_current());
+
+	/* Only the host port disconnect is relevant */
+	if (port == USB_PD_PORT_HOST)
+		gpio_set_level(GPIO_UFP_PLUG_DET, 1);
+}
+DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, board_usb_tc_disconnect,
+	     HOOK_PRIO_DEFAULT);
+
+#endif /* SECTION_IS_RW */
+
+static void board_init(void)
+{
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+static void board_debug_gpio_1_pulse(void)
+{
+	gpio_set_level(GPIO_TRIGGER_1, 0);
+}
+DECLARE_DEFERRED(board_debug_gpio_1_pulse);
+
+static void board_debug_gpio_2_pulse(void)
+{
+	gpio_set_level(GPIO_TRIGGER_2, 0);
+}
+DECLARE_DEFERRED(board_debug_gpio_2_pulse);
+
+void board_debug_gpio(enum debug_gpio trigger, int level, int pulse_usec)
+{
+	switch (trigger) {
+	case TRIGGER_1:
+		gpio_set_level(GPIO_TRIGGER_1, level);
+		if (pulse_usec)
+			hook_call_deferred(&board_debug_gpio_1_pulse_data,
+					   pulse_usec);
+		break;
+	case TRIGGER_2:
+		gpio_set_level(GPIO_TRIGGER_2, level);
+		if (pulse_usec)
+			hook_call_deferred(&board_debug_gpio_2_pulse_data,
+					   pulse_usec);
+		break;
+	default:
+		CPRINTS("bad debug gpio selection");
+		break;
+	}
+}
+
+static int command_dplane(int argc, const char **argv)
+{
+	char *e;
+	int lane;
+
+	if (argc < 2)
+		return EC_ERROR_PARAM_COUNT;
+
+	lane = strtoi(argv[1], &e, 10);
+
+	if ((lane != 2) && (lane != 4))
+		return EC_ERROR_PARAM1;
+
+	/* put MST into reset */
+	gpio_set_level(GPIO_MST_RST_L, 0);
+	msleep(1);
+	/* Set lane control to requested level */
+	gpio_set_level(GPIO_MST_HUB_LANE_SWITCH, lane == 2 ? 1 : 0);
+	msleep(1);
+	/* Take MST out of reset */
+	gpio_set_level(GPIO_MST_RST_L, 1);
+
+	ccprintf("MST lane set:  %s, lane_ctrl = %d\n",
+		 lane == 2 ? "2 lane" : "4 lane",
+		 gpio_get_level(GPIO_MST_HUB_LANE_SWITCH));
+
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(dplane, command_dplane, "<2 | 4>", "MST lane control.");
diff --git a/board/panqueque/board.h b/board/panqueque/board.h
new file mode 100644
index 0000000000..24eeebabe5
--- /dev/null
+++ b/board/panqueque/board.h
@@ -0,0 +1,98 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Panqueque board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* Baseboard features */
+#include "baseboard.h"
+
+/* Optional features */
+/*
+ * For MP release, CONFIG_SYSTEM_UNLOCKED must be undefined, and
+ * CONFIG_FLASH_PSTATE_LOCKED must be defined in order to enable write protect
+ * using option bytes WRP registers.
+ */
+#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
+#undef CONFIG_FLASH_PSTATE_LOCKED
+
+/* USB Type C and USB PD defines */
+#define USB_PD_PORT_HOST 0
+#define USB_PD_PORT_USB3 1
+
+/*
+ * Only the host and display usbc ports are usb-pd capable. There is a 2nd usbc
+ * port, but this is type-c capable only. Only the PPC for this port needs to be
+ * controlled by FW.
+ */
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#define CONFIG_USB_MUX_PS8822
+
+#undef CONFIG_USB_VID
+#define CONFIG_USB_VID 0x2230
+#define CONFIG_USB_PID 0x2018
+#define CONFIG_USB_BCD_DEV 0x0001 /* v 0.01 */
+#define CONFIG_USB_PD_IDENTITY_HW_VERS 1
+#define CONFIG_USB_PD_IDENTITY_SW_VERS 1
+
+/* I2C port names */
+#define I2C_PORT_I2C1 0
+#define I2C_PORT_I2C2 1
+#define I2C_PORT_I2C3 2
+
+/* Required symbolic I2C port names */
+#define I2C_PORT_MP4245 I2C_PORT_I2C3
+#define I2C_PORT_EEPROM I2C_PORT_I2C3
+#define MP4245_I2C_ADDR_FLAGS MP4245_I2C_ADDR_0_FLAGS
+
+/* Include math_util for bitmask_uint64 used in pd_timers */
+#define CONFIG_MATH_UTIL
+
+#ifndef __ASSEMBLER__
+
+#include "registers.h"
+
+#define GPIO_DP_HPD GPIO_DDI_MST_IN_HPD
+#define GPIO_USBC_UF_ATTACHED_SRC GPIO_USBC_UF_MUX_VBUS_EN
+#define GPIO_BPWR_DET GPIO_HUB_BPWRDET
+#define GPIO_USB_HUB_OCP_NOTIFY GPIO_USBC_DATA_OCP_NOTIFY
+#define GPIO_UFP_PLUG_DET GPIO_MST_UFP_PLUG_DET
+
+#define BUTTON_PRESSED_LEVEL 1
+#define BUTTON_RELEASED_LEVEL 0
+
+#define GPIO_TRIGGER_1 GPIO_USB3_A5_CDP_EN
+#define GPIO_TRIGGER_2 GPIO_USB3_A6_CDP_EN
+
+enum debug_gpio {
+	TRIGGER_1 = 0,
+	TRIGGER_2,
+};
+
+/*
+ * Function used to control GPIO signals as a timing marker. This is intended to
+ * be used for development/debugging purposes.
+ *
+ * @param trigger GPIO debug signal selection
+ * @param level desired level of the debug gpio signal
+ * @param pulse_usec pulse width if non-zero
+ */
+void board_debug_gpio(enum debug_gpio trigger, int level, int pulse_usec);
+
+/*
+ * Function called in power on case to enable usbc related interrupts
+ */
+void board_enable_usbc_interrupts(void);
+
+/*
+ * Function called in power off case to disable usbc related interrupts
+ */
+void board_disable_usbc_interrupts(void);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/panqueque/build.mk b/board/panqueque/build.mk
new file mode 100644
index 0000000000..8f9795eca9
--- /dev/null
+++ b/board/panqueque/build.mk
@@ -0,0 +1,14 @@
+# -*- makefile -*-
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=stm32
+CHIP_FAMILY:=stm32g4
+CHIP_VARIANT:=stm32g473xc
+BASEBOARD:=honeybuns
+
+board-y=board.o
diff --git a/board/panqueque/dev_key.pem b/board/panqueque/dev_key.pem
new file mode 100644
index 0000000000..4897ceb44e
--- /dev/null
+++ b/board/panqueque/dev_key.pem
@@ -0,0 +1,39 @@
+-----BEGIN RSA PRIVATE KEY-----
+MIIG4wIBAAKCAYEAyiT9PsD2wW3mhfuxMtihnLDKC+PY9l6j+j405G5Wd3BBtLLl
+2uEoSD8cFQfnVTeFH7wggVf+SMAP3Y2aTnXIfdTX3N0skAdq/kYNUlQAK0xsa3Z7
+bRZ8puvzu+XNqsSS/tvsdYbNE5WC5sXtt7Wkm3mKn7PAti7oQrKbW1beFD0FgdAq
+JoweIdpkuOwDYtFBcF92LWWGziDcEXlc2v5Xj3qvixMLnhy+Ny1Byr2ApVaYZ56H
+JfjHKxbirNj4IrgmhdzfBIKxDf4mGibG0K1aC1io+SixtRV1cS6JRB0D+GS4QIcq
+y9bCMkBeVQLHhSo1UYZqbB7Qef0blQ2sxsXklo8Q5EIQOd6yiXiTelApOWDn3zTi
+uTkUo+99SPDLw/S3sR3uESxt+OYO2Yt6BWe2JSYBhHWB0Xc0PGItq7DUpm2cEWke
+vS91I/lBfqhOxQOvnEx5NM97/RBQMa3jJ5Jv/72X5oU6OcGmaliBJy3Tv0CSiI06
+qgRgWxMym/XA0ui/AgEDAoIBgQCGw1N/K08rnpmup8t3OxZoddwH7TtO6cKm1CNC
+9Dmk9YEjIe6R63AwKhK4r++OJQNqfWsA5VQwgAqTs7w0ToWpOI/ok3MKr5yphAjh
+jVVyMvLyTvzzZFMZ8qJ9Q95x2GH/PUhOWd4NDldEg/PPzm28+7G/zSskH0WBzGeS
+Oeli01kBNXFvCBQWkZh7SAJB4NZK6k7I7lnewJK2UOiR/uUKUcpct10UEyl6Hivc
+flXDjxBFFFoZUITHZJcd5frB0Bh+EiqJ3CnkSIjD4sTnZs/TP8CKhmYriabfBHdH
+j6ffcr5y8VhqDJK/ISSmWQO1c/rSziJLhx/ZrWvWp1FAbRg+kdh+RmV8hYIdEOq8
+PYOiERihd+eHVhtzsc74+cRGxPbaFJ2rpuJt+xk1Zp7IfGyyPWDmvXFKZgX+vo2s
+vJL6q9pPR57uUHL0xsxDrMH3HFxkl1ta5PsiBGXs+zG0EUzNKGtoRTCi176xUWyo
+NG+eWiL9ddeZVBzWeKfJGfwQ53sCgcEA+JE2E5kjvVCasSqERfDfIkSeOKoqWdZ2
+sAvTHibq6+vMBkRubNA0glHcUrMEBblDg3ds2z1A9YvwjwEUq9UFpVH3qfX9vaTX
+lLYFRZjcA3PkCJvFAt5eIlVXp+vgaEo6OcodLjDiqkYKzbMC13k5uM1wsEEwo2vI
+38vhHQlH1PHVTd8pt2Y7mOpDgxOOJLrvwuew7Lj9QSBRZ0EJxqv+1QA4EQ1cPr1H
+hGqggtL0ChLRV7KBHiLz9ggS5vHTEkFNAoHBANAwaSIfTnpAvkMoGy+iQyw0afC0
+7hnwhHKcAzqenT1Mzo3Yt7/zsZE8ywjKPe9C+ZHZyh+W373tCUQRnjpNOpNiVHzi
+ekFxl8kpLhpbB8LTXuRlQmtZjVQPbyuORPGDCzA05GGBN6mnXju+iQEz2WD8f3oY
+Jz5yYl54eAuMsFl5/0yehqBQjRvky5YRna2eNUKBvz+/BgjpZeb0DtLMffcAvrkQ
+FQbAwNvzvagMOEemjLSp9iXjQSNWJAdc86dMOwKBwQCltiQNEMJ+Nbx2HFguoJTB
+gxQlxsbmjvnKsoy+xJydR91ZgvRIis2sNpLhzK1ZJi0CT53nfitOXUsKALhyjgPD
+i/pxTqkpGI+4eVjZEJKs9+1bEoNXPulsOOUanUBFhtF73BN0IJccLrHed1c6UNEl
+3ksgK3XCR9s/3UC+Bi/jS+OJP3Ek7tJl8YJXYl7DJ0qB78tIe1OAwDZE1gaEcqnj
+VXq2COgp04UC8cBXN01cDIuPzFYUF01OsAyZ9oy21jMCgcEAisrwwWo0UYB+13AS
+H8GCHXhGoHieu/Wtob1XfGm+KN3fCTslKqJ2YNMyBdwpSiymYTvcFQ8/0/NbgrZp
+fDN8YkGNqJb8K6EP23DJZudageI/Qu4sR5EI4rT0x7Qt9ldcys3tllYlG8TpfSmw
+q3fmQKhU/BAaKaGW6aWlXQh1kPv/iGmvFYsIvUMyZAu+c77OLFZ/f9SusJuZRKK0
+jIhT+gB/Jgq4rysrPU0pGrLQL8RdzcakGUIrbOQYBOiib4gnAoHAVrvbmZGxyeeA
+oDE2QlXXmd1higPaQe3u+7vmh6itVpJ71n9wmu9xei7IiTOtGDYjHLXa8Qg0y37/
+FVCUiFxhOz05hpnB1ts70tuIWUJbWttMnhZPTpKa1dzZFB6qrlk2o/ONaSfNzpOZ
+FgKxBURFVzNMTlIh7QOZGoOeRg5BkFG5z21g8egYQ/1cY61BhaxJTz93HGKb0jYn
+QnC0WfVF9amWNGwocKATkwjoSVC7rQRsB2FMbY/WCqgE92lXsU9W
+-----END RSA PRIVATE KEY-----
diff --git a/board/panqueque/ec.tasklist b/board/panqueque/ec.tasklist
new file mode 100644
index 0000000000..7bd8acaa5f
--- /dev/null
+++ b/board/panqueque/ec.tasklist
@@ -0,0 +1,16 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS_RO(RWSIG,    rwsig_task,   NULL, 1280) \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS_RW(POWER_BUTTON, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS_RW(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS_RW(UCPD, ucpd_task, 0, LARGER_TASK_STACK_SIZE)
diff --git a/board/panqueque/gpio.inc b/board/panqueque/gpio.inc
new file mode 100644
index 0000000000..4fd80ec754
--- /dev/null
+++ b/board/panqueque/gpio.inc
@@ -0,0 +1,93 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+#ifdef SECTION_IS_RW
+GPIO_INT(HOST_USBC_PPC_INT_ODL,  PIN(D,  9),      GPIO_INT_FALLING | GPIO_PULL_UP, ppc_interrupt)
+GPIO_INT(DDI_MST_IN_HPD,         PIN(C,  14),     GPIO_INT_BOTH, hpd_interrupt)
+GPIO_INT(USBC_UF_MUX_VBUS_EN,    PIN(C,  12),     GPIO_INT_BOTH, board_uf_manage_vbus_interrupt)
+GPIO_INT(PWR_BTN,                PIN(A,  0),      GPIO_INT_BOTH, board_pwr_btn_interrupt)
+GPIO_INT(USBC_UF_PPC_INT_ODL,    PIN(B,  5),      GPIO_INT_FALLING | GPIO_PULL_UP, board_usbc_usb3_interrupt)
+#endif
+
+/* Power sequencing signals */
+GPIO(EN_AC_JACK,                    PIN(A,  1), GPIO_OUT_LOW)
+GPIO(EN_BB,                         PIN(A,  8), GPIO_OUT_LOW)
+GPIO(EN_PP3300_B,                   PIN(B,  2), GPIO_OUT_LOW)
+GPIO(EN_PP5000_A,                   PIN(C,  6), GPIO_OUT_LOW)
+GPIO(EN_PP1200_A,                   PIN(E,  8), GPIO_OUT_LOW)
+GPIO(EN_PP1100_A,                   PIN(C,  7), GPIO_OUT_LOW)
+GPIO(EN_PP1050_A,                   PIN(A,  2), GPIO_OUT_LOW)
+GPIO(EN_PP5000_C,                   PIN(D,  1), GPIO_OUT_LOW)
+GPIO(EN_PP5000_HSPORT,              PIN(D,  0), GPIO_OUT_LOW)
+
+/* MST Hub signals */
+GPIO(MST_LP_CTL_L,                  PIN(D, 10), GPIO_ODR_LOW)
+GPIO(MST_RST_L,                     PIN(E, 14), GPIO_ODR_LOW)
+GPIO(MST_HUB_LANE_SWITCH,           PIN(C, 15), GPIO_OUT_HIGH)
+GPIO(MST_UFP_PLUG_DET,              PIN(B, 12), GPIO_OUT_HIGH)
+
+/* Display Demux signals */
+GPIO(DEMUX_DP_HDMI_MODE,            PIN(E, 15), GPIO_OUT_LOW)
+GPIO(DEMUX_DP_HDMI_PD_N,            PIN(B, 13), GPIO_ODR_LOW)
+
+/* USBC Mux and Demux Signals */
+GPIO(EN_DP_SINK,                    PIN(B, 14), GPIO_OUT_LOW)
+GPIO(DP_SINK_RESET,                 PIN(B, 15), GPIO_OUT_LOW)
+GPIO(USBC_UF_RESET_L,               PIN(D,  2), GPIO_ODR_LOW)
+
+/* USB Hubs signals */
+GPIO(EC_HUB2_RESET_L,               PIN(C,  5), GPIO_ODR_LOW)
+GPIO(EC_HUB3_RESET_L,               PIN(B, 10), GPIO_ODR_LOW)
+GPIO(USBC_DATA_OCP_NOTIFY,          PIN(C,  2), GPIO_OUT_HIGH)
+GPIO(HUB_BPWRDET,                   PIN(C,  1), GPIO_OUT_LOW)
+
+/* USB-A Current limit switches, set default to 1.5A */
+GPIO(GBE_RESET_EC,                  PIN(C,  0), GPIO_OUT_LOW)
+GPIO(EC_DFU_MUX_CTRL,               PIN(C,  3), GPIO_OUT_HIGH)
+GPIO(USB3_A5_CDP_EN,                PIN(B,  9), GPIO_OUT_LOW)
+GPIO(USB3_A6_CDP_EN,                PIN(C, 13), GPIO_OUT_LOW)
+
+
+/* Write protect */
+GPIO(EC_FLASH_WP_ODL,               PIN(A,  3), GPIO_ODR_HIGH)
+GPIO(EC_WP_L,                       PIN(E, 11), GPIO_INT_BOTH)
+
+/* UART Bus */
+GPIO(EC_UART_TX,                    PIN(C, 10), GPIO_INT_BOTH)
+GPIO(EC_UART_RX,                    PIN(C, 11), GPIO_INT_BOTH)
+
+/*
+ * I2C SCL/SDA pins. These will normally be under control of the peripheral from
+ * alt function setting below. But if a port gets wedged, the unwedge code uses
+ * these signals as regular GPIOs.
+ */
+GPIO(EC_I2C1_SCL,                   PIN(A, 15),  GPIO_ODR_HIGH)
+GPIO(EC_I2C1_SDA,                   PIN(B,  7),  GPIO_ODR_HIGH)
+GPIO(EC_I2C3_SCL,                   PIN(C,  8),  GPIO_ODR_HIGH)
+GPIO(EC_I2C3_SDA,                   PIN(C,  9),  GPIO_ODR_HIGH)
+
+/* misc signals */
+GPIO(BOOT0,                         PIN(B,  8),  GPIO_INPUT)
+
+/* Unimplemented signals since we are not an EC */
+UNIMPLEMENTED(ENTERING_RW)
+
+/* USART3_TX/RX GPIOC 10-11*/
+ALTERNATE(PIN_MASK(C, 0x0C00),  7, MODULE_UART,  GPIO_PULL_UP)
+/* I2C Ports
+ *   I2C1: SDA/SCL -> PB7/PA15
+ *   I2C2: SDA/SCL -> PA8/PA9
+ *   I2C3: SDA/SCL -> PC8/PC9
+ */
+ALTERNATE(PIN_MASK(B, 0x0080),  4, MODULE_I2C,   GPIO_OPEN_DRAIN)
+ALTERNATE(PIN_MASK(A, 0X8000),  4, MODULE_I2C,   GPIO_OPEN_DRAIN)
+ALTERNATE(PIN_MASK(C, 0x0300),  8, MODULE_I2C,   GPIO_OPEN_DRAIN)
+/* GPIOA4-7: SPI Signals */
+ALTERNATE(PIN_MASK(A, 0x00F0),  5, MODULE_SPI,   0)
diff --git a/board/pazquel/battery.c b/board/pazquel/battery.c
new file mode 100644
index 0000000000..bd600aed5b
--- /dev/null
+++ b/board/pazquel/battery.c
@@ -0,0 +1,72 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "common.h"
+
+const struct board_batt_params board_battery_info[] = {
+	/* GanFeng SG20 Battery Information */
+	[BATTERY_GANFENG] = {
+		.fuel_gauge = {
+			.manuf_name = "Ganfeng",
+			.device_name = "SG20",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr = 0x43,
+				.reg_mask = 0x0003,
+				.disconnect_val = 0x0000,
+			}
+		},
+		.batt_info = {
+			.voltage_max        = 8700, /* mV */
+			.voltage_normal     = 7600, /* mV */
+			.voltage_min        = 6000, /* mV */
+			.precharge_current  = 256,  /* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 50,
+			.charging_min_c     = 0,
+			.charging_max_c     = 60,
+			.discharging_min_c  = -20,
+			.discharging_max_c  = 60,
+		},
+	},
+	/* Pow-Tech SG20QT1C-2S4000-P1P1 Battery Information */
+	[BATTERY_POWTECH_SG20QT1C] = {
+		.fuel_gauge = {
+			.manuf_name = "POW-TECH",
+			.device_name = "SG20QT1C",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x54,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0000,
+			}
+		},
+		.batt_info = {
+			.voltage_max        = 8700, /* mV */
+			.voltage_normal     = 7600, /* mV */
+			.voltage_min        = 6000, /* mV */
+			.precharge_current  = 256,  /* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c     = 0,
+			.charging_max_c     = 53,
+			.discharging_min_c  = -23,
+			.discharging_max_c  = 63,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_GANFENG;
diff --git a/board/pazquel/board.c b/board/pazquel/board.c
new file mode 100644
index 0000000000..7502d18b4d
--- /dev/null
+++ b/board/pazquel/board.c
@@ -0,0 +1,725 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Trogdor board-specific configuration */
+
+#include "adc_chip.h"
+#include "button.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "driver/accel_bma2x2.h"
+#include "driver/accel_kionix.h"
+#include "driver/accelgyro_bmi323.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "driver/ppc/sn5s330.h"
+#include "driver/tcpm/ps8xxx.h"
+#include "driver/tcpm/tcpci.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "pi3usb9201.h"
+#include "power.h"
+#include "power/qcom.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "shi_chip.h"
+#include "switch.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "usbc_ocp.h"
+#include "usbc_ppc.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/* Forward declaration */
+static void tcpc_alert_event(enum gpio_signal signal);
+static void usb0_evt(enum gpio_signal signal);
+static void usb1_evt(enum gpio_signal signal);
+static void usba_oc_interrupt(enum gpio_signal signal);
+static void ppc_interrupt(enum gpio_signal signal);
+static void board_connect_c0_sbu(enum gpio_signal s);
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* GPIO Interrupt Handlers */
+static void tcpc_alert_event(enum gpio_signal signal)
+{
+	int port = -1;
+
+	switch (signal) {
+	case GPIO_USB_C0_PD_INT_ODL:
+		port = 0;
+		break;
+	case GPIO_USB_C1_PD_INT_ODL:
+		port = 1;
+		break;
+	default:
+		return;
+	}
+
+	schedule_deferred_pd_interrupt(port);
+}
+
+static void usb0_evt(enum gpio_signal signal)
+{
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+
+static void usb1_evt(enum gpio_signal signal)
+{
+	usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+}
+
+static void usba_oc_deferred(void)
+{
+	/* Use next number after all USB-C ports to indicate the USB-A port */
+	board_overcurrent_event(CONFIG_USB_PD_PORT_MAX_COUNT,
+				!gpio_get_level(GPIO_USB_A0_OC_ODL));
+}
+DECLARE_DEFERRED(usba_oc_deferred);
+
+static void usba_oc_interrupt(enum gpio_signal signal)
+{
+	hook_call_deferred(&usba_oc_deferred_data, 0);
+}
+
+static void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_SWCTL_INT_ODL:
+		sn5s330_interrupt(0);
+		break;
+	case GPIO_USB_C1_SWCTL_INT_ODL:
+		sn5s330_interrupt(1);
+		break;
+	default:
+		break;
+	}
+}
+
+static void board_connect_c0_sbu_deferred(void)
+{
+	/*
+	 * If CCD_MODE_ODL asserts, it means there's a debug accessory connected
+	 * and we should enable the SBU FETs.
+	 */
+	ppc_set_sbu(0, 1);
+}
+DECLARE_DEFERRED(board_connect_c0_sbu_deferred);
+
+static void board_connect_c0_sbu(enum gpio_signal s)
+{
+	hook_call_deferred(&board_connect_c0_sbu_deferred_data, 0);
+}
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/* Use 80 us, because KSO_02 passes through the H1. */
+	.output_settle_us = 80,
+	/*
+	 * 1. launcher key mapped to (KSI_3, KSO_0):
+	 *    change actual_key_mask[0] = 0x14 to 0x1c
+	 * 2. T11 key not in keyboard (KSI_0,KSO_1):
+	 *    change actual_key_mask[1] from 0xff to 0xfe
+	 */
+	.actual_key_mask = { 0x1c, 0xfe, 0xff, 0xff, 0xff, 0xf5, 0xff, 0xa4,
+			     0xff, 0xfe, 0x55, 0xfa, 0xca },
+	/* Other values should be the same as the default configuration. */
+	.debounce_down_us = 9 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+};
+
+/* I2C port map */
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_POWER_SCL,
+	  .sda = GPIO_EC_I2C_POWER_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C0_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C0_PD_SDA },
+	{ .name = "tcpc1",
+	  .port = I2C_PORT_TCPC1,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C1_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C1_PD_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_EEPROM_SCL,
+	  .sda = GPIO_EC_I2C_EEPROM_SDA },
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_SENSOR_SCL,
+	  .sda = GPIO_EC_I2C_SENSOR_SDA },
+};
+
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	/* Measure VBUS through a 1/10 voltage divider */
+	[ADC_VBUS] = { "VBUS", NPCX_ADC_CH1, ADC_MAX_VOLT * 10,
+		       ADC_READ_MAX + 1, 0 },
+	/*
+	 * Adapter current output or battery charging/discharging current (uV)
+	 * 18x amplification on charger side.
+	 */
+	[ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH2, ADC_MAX_VOLT * 1000 / 18,
+			    ADC_READ_MAX + 1, 0 },
+	/*
+	 * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read
+	 * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and
+	 * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we
+	 * only divide by 2 (enough to avoid precision issues).
+	 */
+	[ADC_PSYS] = { "PSYS", NPCX_ADC_CH3,
+		       ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), 2, 0 },
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 },
+	[PWM_CH_DISPLIGHT] = { .channel = 5, .flags = 0, .freq = 20000 },
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+/* Power Path Controller */
+struct ppc_config_t ppc_chips[] = {
+	{ .i2c_port = I2C_PORT_TCPC0,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
+	{ .i2c_port = I2C_PORT_TCPC1,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
+};
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/* TCPC mux configuration */
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TCPC0,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+	},
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TCPC1,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+	},
+};
+
+/*
+ * Port-0/1 USB mux driver.
+ *
+ * The USB mux is handled by TCPC chip and the HPD update is through a GPIO
+ * to AP. But the TCPC chip is also needed to know the HPD status; otherwise,
+ * the mux misbehaves.
+ */
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
+	},
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
+	}
+};
+
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_USB_A_5V,
+};
+
+/* BC1.2 */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	{
+		.i2c_port = I2C_PORT_POWER,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+	{
+		.i2c_port = I2C_PORT_EEPROM,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+};
+/* Initialize board. */
+static void board_init(void)
+{
+	/* Enable BC1.2 interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_L);
+	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L);
+
+	/* Enable USB-A overcurrent interrupt */
+	gpio_enable_interrupt(GPIO_USB_A0_OC_ODL);
+
+	/* Enable interrupt for BMI160 sensor */
+	gpio_enable_interrupt(GPIO_ACCEL_GYRO_INT_L);
+
+	/*
+	 * The H1 SBU line for CCD are behind PPC chip. The PPC internal FETs
+	 * for SBU may be disconnected after DP alt mode is off. Should enable
+	 * the CCD_MODE_ODL interrupt to make sure the SBU FETs are connected.
+	 */
+	gpio_enable_interrupt(GPIO_CCD_MODE_ODL);
+
+	/* Set the backlight duty cycle to 0. AP will override it later. */
+	pwm_set_duty(PWM_CH_DISPLIGHT, 0);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+void board_tcpc_init(void)
+{
+	/* Only reset TCPC if not sysjump */
+	if (!system_jumped_late()) {
+		/* TODO(crosbug.com/p/61098): How long do we need to wait? */
+		board_reset_pd_mcu();
+	}
+
+	/* Enable PPC interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_SWCTL_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_SWCTL_INT_ODL);
+
+	/* Enable TCPC interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL);
+
+	/*
+	 * Initialize HPD to low; after sysjump SOC needs to see
+	 * HPD pulse to enable video path
+	 */
+	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
+		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+	/*
+	 * Pazquel/pazquel360 share the same firmware ,only pazquel360 has
+	 * volume keys. So disable volume keys for pazquel board
+	 */
+	if (!board_has_side_volume_buttons()) {
+		button_disable_gpio(BUTTON_VOLUME_UP);
+		button_disable_gpio(BUTTON_VOLUME_DOWN);
+		gpio_set_flags(GPIO_VOLUME_DOWN_L, GPIO_INPUT | GPIO_PULL_DOWN);
+		gpio_set_flags(GPIO_VOLUME_UP_L, GPIO_INPUT | GPIO_PULL_DOWN);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
+
+static void da9313_pvc_mode_ctrl(int enable)
+{
+	/*
+	 * On enable, PVC operates in automatic frequency mode.
+	 * On disable, PVC operates in fixed frequency mode.
+	 */
+	if (enable)
+		i2c_update8(I2C_PORT_POWER, DA9313_I2C_ADDR_FLAGS,
+			    DA9313_REG_PVC_CTRL, DA9313_PVC_CTRL_PVC_MODE,
+			    MASK_SET);
+	else
+		i2c_update8(I2C_PORT_POWER, DA9313_I2C_ADDR_FLAGS,
+			    DA9313_REG_PVC_CTRL, DA9313_PVC_CTRL_PVC_MODE,
+			    MASK_CLR);
+}
+
+void da9313_init(void)
+{
+	/* PVC operates in fixed frequency mode in S0. */
+	da9313_pvc_mode_ctrl(0);
+}
+DECLARE_HOOK(HOOK_INIT, da9313_init, HOOK_PRIO_DEFAULT + 1);
+
+void board_hibernate(void)
+{
+	int i;
+
+	/*
+	 * Sensors are unpowered in hibernate. Apply PD to the
+	 * interrupt lines such that they don't float.
+	 */
+	gpio_set_flags(GPIO_ACCEL_GYRO_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
+	gpio_set_flags(GPIO_LID_ACCEL_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
+
+	/*
+	 * Enable the PPC power sink path before EC enters hibernate;
+	 * otherwise, ACOK won't go High and can't wake EC up. Check the
+	 * bug b/170324206 for details.
+	 */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
+		ppc_vbus_sink_enable(i, 1);
+}
+
+/* Called on AP S0 -> S3 transition */
+static void board_chipset_suspend(void)
+{
+	/*
+	 * Turn off display backlight in S3. AP has its own control. The EC's
+	 * and the AP's will be AND'ed together in hardware.
+	 */
+	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 0);
+
+	/* PVC operates in automatic frequency mode in S3. */
+	da9313_pvc_mode_ctrl(1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S3 -> S0 transition */
+static void board_chipset_resume(void)
+{
+	/* PVC operates in fixed frequency mode in S0. */
+	da9313_pvc_mode_ctrl(0);
+	/* Turn on display and keyboard backlight in S0. */
+	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 1);
+	if (pwm_get_duty(PWM_CH_DISPLIGHT))
+		pwm_enable(PWM_CH_DISPLIGHT, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
+
+/* Called on S3 -> S5 transition */
+static void board_shutdown_complete(void)
+{
+	if (pwm_get_duty(PWM_CH_DISPLIGHT)) {
+		pwm_set_duty(PWM_CH_DISPLIGHT, 0);
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN_COMPLETE, board_shutdown_complete,
+	     HOOK_PRIO_DEFAULT);
+
+__override uint32_t board_get_sku_id(void)
+{
+	static int sku_id = -1;
+
+	if (sku_id == -1) {
+		int bits[3];
+
+		bits[0] = gpio_get_ternary(GPIO_SKU_ID0);
+		bits[1] = gpio_get_ternary(GPIO_SKU_ID1);
+		bits[2] = gpio_get_ternary(GPIO_SKU_ID2);
+		sku_id = binary_first_base3_from_bits(bits, ARRAY_SIZE(bits));
+	}
+
+	return (uint32_t)sku_id;
+}
+
+void board_set_switchcap_power(int enable)
+{
+	gpio_set_level(GPIO_SWITCHCAP_ON, enable);
+}
+
+int board_is_switchcap_enabled(void)
+{
+	return gpio_get_level(GPIO_SWITCHCAP_ON);
+}
+
+int board_is_switchcap_power_good(void)
+{
+	return gpio_get_level(GPIO_SWITCHCAP_PG);
+}
+
+void board_reset_pd_mcu(void)
+{
+	cprints(CC_USB, "Resetting TCPCs...");
+	cflush();
+
+	gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
+	gpio_set_level(GPIO_USB_C1_PD_RST_L, 0);
+	msleep(PS8XXX_RESET_DELAY_MS);
+	gpio_set_level(GPIO_USB_C0_PD_RST_L, 1);
+	gpio_set_level(GPIO_USB_C1_PD_RST_L, 1);
+	msleep(PS8805_FW_INIT_DELAY_MS);
+}
+
+void board_set_tcpc_power_mode(int port, int mode)
+{
+	/* Ignore the "mode" to turn the chip on.  We can only do a reset. */
+	if (mode)
+		return;
+
+	board_reset_pd_mcu();
+}
+
+int board_vbus_sink_enable(int port, int enable)
+{
+	/* Both ports are controlled by PPC SN5S330 */
+	return ppc_vbus_sink_enable(port, enable);
+}
+
+int board_is_sourcing_vbus(int port)
+{
+	/* Both ports are controlled by PPC SN5S330 */
+	return ppc_is_sourcing_vbus(port);
+}
+
+void board_overcurrent_event(int port, int is_overcurrented)
+{
+	/* TODO(b/120231371): Notify AP */
+	CPRINTS("p%d: overcurrent!", port);
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int i;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTS("Disabling all charging port");
+
+		/* Disable all ports. */
+		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (board_vbus_sink_enable(i, 0))
+				CPRINTS("Disabling p%d sink path failed.", i);
+		}
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (board_is_sourcing_vbus(port)) {
+		CPRINTS("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTS("New charge port: p%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		if (i == port)
+			continue;
+
+		if (board_vbus_sink_enable(i, 0))
+			CPRINTS("p%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (board_vbus_sink_enable(port, 1)) {
+		CPRINTS("p%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
+{
+	/*
+	 * Ignore lower charge ceiling on PD transition if our battery is
+	 * critical, as we may brownout.
+	 */
+	if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 &&
+	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
+		CPRINTS("Using max ilim %d", max_ma);
+		charge_ma = max_ma;
+	}
+
+	charge_set_input_current_limit(charge_ma, charge_mv);
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
+		if (gpio_get_level(GPIO_USB_C0_PD_RST_L))
+			status |= PD_STATUS_TCPC_ALERT_0;
+	if (!gpio_get_level(GPIO_USB_C1_PD_INT_ODL))
+		if (gpio_get_level(GPIO_USB_C1_PD_RST_L))
+			status |= PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
+
+/* Mutexes */
+static struct mutex g_base_mutex;
+static struct mutex g_lid_mutex;
+
+/* Matrix to rotate accelerometer into standard reference frame */
+const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				       { 0, FLOAT_TO_FP(1), 0 },
+				       { 0, 0, FLOAT_TO_FP(-1) } };
+
+static struct kionix_accel_data g_kx022_data;
+
+static const mat33_fp_t lid_standard_ref_kx022 = { { FLOAT_TO_FP(1), 0, 0 },
+						   { 0, FLOAT_TO_FP(1), 0 },
+						   { 0, 0, FLOAT_TO_FP(1) } };
+
+static struct bmi_drv_data_t g_bmi_data;
+struct motion_sensor_t motion_sensors[] = {
+	[LID_ACCEL] = {
+		.name = "Lid Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_KX022,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &kionix_accel_drv,
+		.mutex = &g_lid_mutex,
+		.drv_data = &g_kx022_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
+		.rot_standard_ref = &lid_standard_ref_kx022,
+		.default_range = 2, /* g */
+		/* We only use 2g because its resolution is only 8-bits */
+		.min_frequency = KX022_ACCEL_MIN_FREQ,
+		.max_frequency = KX022_ACCEL_MAX_FREQ,
+		.config = {
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+		},
+	},
+	/*
+	 * Note: bmi232: supports accelerometer and gyro sensor
+	 * Requirement: accelerometer sensor must init before gyro sensor
+	 * DO NOT change the order of the following table.
+	 */
+	[BASE_ACCEL] = {
+		.name = "Base Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMI323,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &bmi3xx_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = &g_bmi_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMI3_ADDR_I2C_PRIM,
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = BMI_ACCEL_MIN_FREQ,
+		.max_frequency = BMI_ACCEL_MAX_FREQ,
+		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
+		.config = {
+			/* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 12500 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+			/* Sensor on in S3 */
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 12500 | ROUND_UP_FLAG,
+				.ec_rate = 0,
+			},
+		},
+	},
+	[BASE_GYRO] = {
+		.name = "Base Gyro",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMI323,
+		.type = MOTIONSENSE_TYPE_GYRO,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &bmi3xx_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = &g_bmi_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMI3_ADDR_I2C_PRIM,
+		.default_range = 1000, /* dps */
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = BMI_GYRO_MIN_FREQ,
+		.max_frequency = BMI_GYRO_MAX_FREQ,
+	},
+};
+unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+static void board_update_sensor_config_from_sku(void)
+{
+	if (board_is_clamshell()) {
+		motion_sensor_count = 0;
+		gmr_tablet_switch_disable();
+		/* The sensors are not stuffed; don't allow lines to float */
+		gpio_set_flags(GPIO_ACCEL_GYRO_INT_L,
+			       GPIO_INPUT | GPIO_PULL_DOWN);
+		gpio_set_flags(GPIO_LID_ACCEL_INT_L,
+			       GPIO_INPUT | GPIO_PULL_DOWN);
+	} else {
+		motion_sensor_count = ARRAY_SIZE(motion_sensors);
+		/* Enable interrupt for the base accel sensor */
+		gpio_enable_interrupt(GPIO_ACCEL_GYRO_INT_L);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, board_update_sensor_config_from_sku,
+	     HOOK_PRIO_INIT_I2C + 2);
+
+static uint8_t sku_id;
+
+enum board_model {
+	PAZQUEL,
+	PAZQUEL360,
+	UNKNOWN,
+};
+
+static const char *const model_name[] = {
+	"PAZQUEL",
+	"PAZQUEL360",
+	"UNKNOWN",
+};
+
+static enum board_model get_model(void)
+{
+	if (sku_id == 0 || sku_id == 1 || sku_id == 2 || sku_id == 3 ||
+	    sku_id == 4 || sku_id == 5 || sku_id == 6)
+		return PAZQUEL;
+	if (sku_id >= 8)
+		return PAZQUEL360;
+	return UNKNOWN;
+}
+
+int board_is_clamshell(void)
+{
+	return get_model() == PAZQUEL;
+}
+
+/* Read SKU ID from GPIO and initialize variables for board variants */
+static void sku_init(void)
+{
+	sku_id = system_get_sku_id();
+	CPRINTS("SKU: %u (%s)", sku_id, model_name[get_model()]);
+}
+DECLARE_HOOK(HOOK_INIT, sku_init, HOOK_PRIO_INIT_I2C + 1);
+
+int board_has_side_volume_buttons(void)
+{
+	return get_model() == PAZQUEL360;
+}
+__override int mkbp_support_volume_buttons(void)
+{
+	return board_has_side_volume_buttons();
+}
diff --git a/board/pazquel/board.h b/board/pazquel/board.h
new file mode 100644
index 0000000000..414c8ab7dd
--- /dev/null
+++ b/board/pazquel/board.h
@@ -0,0 +1,104 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Trogdor board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "baseboard.h"
+
+/* Internal SPI flash on NPCX7 */
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */
+
+/* Keyboard */
+#define CONFIG_KEYBOARD_PROTOCOL_MKBP
+#define CONFIG_KEYBOARD_REFRESH_ROW3
+#define CONFIG_PWM_KBLIGHT
+
+/* Battery */
+#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
+#define CONFIG_BATTERY_FUEL_GAUGE
+#define CONFIG_BATTERY_REVIVE_DISCONNECT
+#define CONFIG_BATTERY_LOW_VOLTAGE_PROTECTION
+
+/* BC 1.2 Charger */
+#define CONFIG_BC12_DETECT_PI3USB9201
+
+/* USB */
+#define CONFIG_USB_PD_TCPM_PS8805
+#define CONFIG_USB_PD_TCPM_PS8805_FORCE_DID
+#define CONFIG_USBC_PPC_SN5S330
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+
+/* USB-A */
+#define USB_PORT_COUNT 1
+#define CONFIG_USB_PORT_POWER_DUMB
+
+/* Sensors */
+#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
+/* BMI323 Base accel/gyro */
+#define CONFIG_ACCELGYRO_BMI3XX
+#define CONFIG_ACCELGYRO_BMI3XX_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+#define OPT3001_I2C_ADDR_FLAGS OPT3001_I2C_ADDR1_FLAGS
+
+/* KX022 lid accel */
+#define CONFIG_ACCEL_KX022
+#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
+
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+#define CONFIG_LID_ANGLE_UPDATE
+
+#define CONFIG_TABLET_MODE
+#define CONFIG_TABLET_MODE_SWITCH
+#define CONFIG_GMR_TABLET_MODE
+
+/* GPIO alias */
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_WP_L GPIO_EC_WP_ODL
+#define GPIO_SWITCHCAP_PG GPIO_SWITCHCAP_GPIO_1
+#define GPIO_ACOK_OD GPIO_CHG_ACOK_OD
+/* Da9313 */
+#define DA9313_I2C_ADDR_FLAGS 0x68
+#define DA9313_REG_PVC_CTRL 0x04
+#define DA9313_PVC_CTRL_PVC_MODE BIT(1)
+#define DA9313_PVC_CTRL_PVC_EN BIT(0)
+
+/* Button Config*/
+#define CONFIG_BUTTONS_RUNTIME_CONFIG
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum adc_channel { ADC_VBUS, ADC_AMON_BMON, ADC_PSYS, ADC_CH_COUNT };
+
+/* Motion sensors */
+enum sensor_id {
+	LID_ACCEL = 0,
+	BASE_ACCEL,
+	BASE_GYRO,
+	SENSOR_COUNT,
+};
+
+enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_DISPLIGHT, PWM_CH_COUNT };
+
+enum battery_type {
+	BATTERY_GANFENG,
+	BATTERY_POWTECH_SG20QT1C,
+	BATTERY_TYPE_COUNT,
+};
+/* Reset all TCPCs. */
+void board_reset_pd_mcu(void);
+void board_set_tcpc_power_mode(int port, int mode);
+int board_is_clamshell(void);
+int board_has_side_volume_buttons(void);
+
+#endif /* !defined(__ASSEMBLER__) */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/pazquel/build.mk b/board/pazquel/build.mk
new file mode 100644
index 0000000000..3bc07db568
--- /dev/null
+++ b/board/pazquel/build.mk
@@ -0,0 +1,17 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx7
+CHIP_VARIANT:=npcx7m6fc
+BASEBOARD:=trogdor
+
+board-y+=battery.o
+board-y+=board.o
+board-y+=led.o
+board-y+=usbc_config.o
diff --git a/board/pazquel/ec.tasklist b/board/pazquel/ec.tasklist
new file mode 100644
index 0000000000..228828af3c
--- /dev/null
+++ b/board/pazquel/ec.tasklist
@@ -0,0 +1,23 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/pazquel/gpio.inc b/board/pazquel/gpio.inc
new file mode 100644
index 0000000000..8d9a2827bc
--- /dev/null
+++ b/board/pazquel/gpio.inc
@@ -0,0 +1,187 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+/* USB interrupts */
+GPIO_INT(USB_C0_PD_INT_ODL,    PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-0 TCPC */
+GPIO_INT(USB_C1_PD_INT_ODL,    PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-1 TCPC */
+GPIO_INT(USB_C0_SWCTL_INT_ODL, PIN(0, 3), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-0 PPC */
+GPIO_INT(USB_C1_SWCTL_INT_ODL, PIN(4, 0), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-1 PPC */
+GPIO_INT(USB_C0_BC12_INT_L,    PIN(6, 1), GPIO_INT_FALLING, usb0_evt)  /* Interrupt from port-0 BC1.2 */
+GPIO_INT(USB_C1_BC12_INT_L,    PIN(8, 2), GPIO_INT_FALLING, usb1_evt)  /* Interrupt from port-1 BC1.2 */
+GPIO_INT(USB_A0_OC_ODL,        PIN(D, 1), GPIO_INT_BOTH | GPIO_PULL_UP, usba_oc_interrupt)
+
+/* System interrupts */
+GPIO_INT(CHG_ACOK_OD,       PIN(0, 0), GPIO_INT_BOTH, extpower_interrupt)  /* ACOK */
+GPIO_INT(CCD_MODE_ODL,      PIN(E, 3), GPIO_INT_FALLING, board_connect_c0_sbu)  /* Case Closed Debug Mode */
+GPIO_INT(EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)  /* Power button */
+GPIO_INT(EC_VOLDN_BTN_ODL,  PIN(7, 0), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Down button */
+GPIO_INT(EC_VOLUP_BTN_ODL,  PIN(F, 2), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Up button */
+GPIO_INT(EC_WP_ODL,         PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)  /* Write protection */
+GPIO_INT(LID_OPEN_EC,       PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)  /* Lid open */
+GPIO_INT(AP_RST_L,          PIN(C, 1), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_ap_rst_interrupt)  /* PMIC to signal AP reset */
+GPIO_INT(PS_HOLD,           PIN(A, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, power_signal_interrupt)  /* Indicate when AP triggers reset/shutdown */
+GPIO_INT(AP_SUSPEND,        PIN(5, 7), GPIO_INT_BOTH, power_signal_interrupt)  /* Suspend signal from PMIC */
+GPIO_INT(DEPRECATED_AP_RST_REQ, PIN(C, 2), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V, power_signal_interrupt) /* Deprecated AP initiated reset indicator */
+/*
+ * When switch-cap is off, the POWER_GOOD signal is floating. Need a pull-down
+ * to make it low. Overload the interrupt function chipset_warm_reset_interrupt
+ * for not only signalling power_signal_interrupt but also handling the logic
+ * of WARM_RESET_L which is pulled-up by the same rail of POWER_GOOD.
+ */
+GPIO_INT(POWER_GOOD,        PIN(5, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, chipset_power_good_interrupt)  /* SRC_PP1800_S10A from PMIC */
+GPIO_INT(WARM_RESET_L,      PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_warm_reset_interrupt)  /* AP warm reset */
+GPIO_INT(AP_EC_SPI_CS_L,    PIN(5, 3), GPIO_INT_FALLING | GPIO_PULL_DOWN, shi_cs_event)  /* EC SPI Chip Select */
+
+/* Sensor interrupts */
+GPIO_INT(TABLET_MODE_L,     PIN(C, 6), GPIO_INT_BOTH, gmr_tablet_switch_isr)
+GPIO_INT(ACCEL_GYRO_INT_L,  PIN(A, 0), GPIO_INT_FALLING, bmi3xx_interrupt)  /* Accelerometer/gyro interrupt */
+
+/*
+ * EC_RST_ODL used to be a wake source from PSL mode. However, we disabled
+ * the PSL mode. This GPIO does nothing now. Simply set it an INPUT.
+ */
+GPIO(EC_RST_ODL,            PIN(0, 2), GPIO_INPUT)     /* EC reset */
+GPIO(EC_ENTERING_RW,        PIN(E, 1), GPIO_OUT_LOW)   /* Indicate when EC is entering RW code */
+GPIO(EC_BATT_PRES_ODL,      PIN(E, 5), GPIO_INPUT)     /* Battery Present */
+
+/* PMIC/AP 1.8V */
+GPIO(PMIC_RESIN_L,          PIN(3, 2), GPIO_ODR_HIGH)  /* PMIC reset trigger */
+GPIO(PMIC_KPD_PWR_ODL,      PIN(D, 6), GPIO_ODR_HIGH)  /* PMIC power button */
+GPIO(EC_INT_L,              PIN(A, 2), GPIO_ODR_HIGH)  /* Interrupt line between AP and EC */
+
+/* Power enables */
+GPIO(HIBERNATE_L,           PIN(5, 2), GPIO_OUT_HIGH)  /* EC hibernate */
+GPIO(SWITCHCAP_ON,          PIN(D, 5), GPIO_OUT_LOW)   /* Enable switch cap */
+GPIO(EN_PP3300_A,           PIN(A, 6), GPIO_OUT_LOW)   /* Enable PP3300 */
+GPIO(EN_PP5000_A,           PIN(6, 7), GPIO_OUT_LOW)   /* Enable PP5000 */
+GPIO(EC_BL_DISABLE_L,       PIN(B, 6), GPIO_OUT_LOW)   /* Backlight disable signal from EC */
+
+/* Sensors */
+GPIO(LID_ACCEL_INT_L,       PIN(5, 6), GPIO_INPUT)     /* Lid accel sensor interrupt */
+/* Control the gate for trackpad IRQ. High closes the gate.
+ * This is always set low so that the OS can manage the trackpad. */
+GPIO(TRACKPAD_INT_GATE,     PIN(7, 4), GPIO_OUT_LOW)
+
+/* USB-C */
+GPIO(USB_C0_PD_RST_L,       PIN(F, 1), GPIO_OUT_HIGH)  /* Port-0 TCPC chip reset */
+GPIO(USB_C1_PD_RST_L,       PIN(E, 4), GPIO_OUT_HIGH)  /* Port-1 TCPC chip reset */
+GPIO(DP_MUX_OE_L,           PIN(9, 6), GPIO_ODR_HIGH)  /* DP mux enable, actually Open-Drain */
+GPIO(DP_MUX_SEL,            PIN(4, 5), GPIO_OUT_LOW)   /* DP mux selection: L:C0, H:C1 */
+GPIO(DP_HOT_PLUG_DET,       PIN(9, 5), GPIO_OUT_LOW)   /* DP HPD to AP */
+
+/* USB-A */
+GPIO(EN_USB_A_5V,           PIN(8, 6), GPIO_OUT_LOW)
+GPIO(USB_A_CDP_ILIM_EN_L,   PIN(7, 5), GPIO_OUT_HIGH)  /* H:CDP, L:SDP. Only one USB-A port, always CDP */
+
+/* LEDs */
+GPIO(EC_CHG_LED_Y_C0,       PIN(6, 0), GPIO_OUT_LOW)
+GPIO(EC_CHG_LED_W_C0,       PIN(C, 0), GPIO_OUT_LOW)
+GPIO(EC_CHG_LED_Y_C1,       PIN(C, 3), GPIO_OUT_LOW)
+GPIO(EC_CHG_LED_W_C1,       PIN(C, 4), GPIO_OUT_LOW)
+
+/*
+ * SPI host interface - enable PDs by default. These will be made functional
+ * by the SHI driver when the AP powers up, and restored back to GPIO when
+ * the AP powers down.
+ */
+GPIO(AP_EC_SPI_MOSI,        PIN(4, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(AP_EC_SPI_MISO,        PIN(4, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(AP_EC_SPI_CLK,         PIN(5, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+
+/* PWM */
+GPIO(KB_BL_PWM,             PIN(8, 0), GPIO_INPUT)     /* PWM3 */
+GPIO(EDP_BKLTCTL,           PIN(B, 7), GPIO_INPUT)     /* PWM5 */
+
+/* ADC */
+GPIO(PPVAR_BOOSTIN_SENSE,   PIN(4, 4), GPIO_INPUT)     /* ADC1 */
+GPIO(CHARGER_IADP,          PIN(4, 3), GPIO_INPUT)     /* ADC2 */
+GPIO(CHARGER_PMON,          PIN(4, 2), GPIO_INPUT)     /* ADC3 */
+
+/* I2C */
+GPIO(EC_I2C_POWER_SCL,      PIN(B, 5), GPIO_INPUT)
+GPIO(EC_I2C_POWER_SDA,      PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_PD_SCL,  PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_PD_SDA,  PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_PD_SCL,  PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_PD_SDA,  PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SCL,     PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SDA,     PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,     PIN(B, 3), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SENSOR_SDA,     PIN(B, 2), GPIO_INPUT | GPIO_SEL_1P8V)
+
+/* Board/SKU IDs */
+GPIO(BRD_ID0,               PIN(C, 7), GPIO_INPUT)
+GPIO(BRD_ID1,               PIN(9, 3), GPIO_INPUT)
+GPIO(BRD_ID2,               PIN(6, 3), GPIO_INPUT)
+GPIO(SKU_ID0,               PIN(F, 0), GPIO_INPUT)
+GPIO(SKU_ID1,               PIN(4, 1), GPIO_INPUT)
+GPIO(SKU_ID2,               PIN(D, 4), GPIO_INPUT)
+
+/* Switchcap */
+/*
+ * GPIO0 is configured as PVC_PG. When the chip in power down mode, it outputs
+ * high-Z. Set pull-down to avoid floating.
+ */
+GPIO(SWITCHCAP_GPIO_1,      PIN(E, 2), GPIO_INPUT | GPIO_PULL_DOWN) /* Switchcap GPIO0 */
+
+/* Special straps */
+GPIO(ARM_X86,               PIN(6, 6), GPIO_OUT_LOW)  /* NC, low for power saving */
+
+/* Unused GPIOs, NC. */
+UNUSED(PIN(5, 1))
+UNUSED(PIN(D, 0))
+UNUSED(PIN(F, 3))
+UNUSED(PIN(9, 4))
+UNUSED(PIN(9, 7))
+UNUSED(PIN(A, 7))
+UNUSED(PIN(B, 0))
+UNUSED(PIN(A, 5))
+UNUSED(PIN(3, 5))
+UNUSED(PIN(7, 2))
+UNUSED(PIN(8, 1))
+UNUSED(PIN(3, 7))
+UNUSED(PIN(7, 6))
+UNUSED(PIN(3, 4))
+UNUSED(PIN(C, 5))
+UNUSED(PIN(7, 3))
+UNUSED(PIN(D, 7))
+UNUSED(PIN(A, 3))
+UNUSED(PIN(6, 2))
+UNUSED(PIN(0, 4))
+UNUSED(PIN(8, 3))
+UNUSED(PIN(B, 1))
+UNUSED(PIN(5, 0))
+UNUSED(PIN(D, 3))
+
+/* Alternate functions GPIO definitions */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)            /* UART (GPIO64/65) */
+ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0)             /* I2C0 (GPIOB4/B5) */
+ALTERNATE(PIN_MASK(9, 0x07), 1, MODULE_I2C, 0)             /* I2C1 SDA (GPIO90), I2C2 (GPIO91/92) */
+ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, 0)             /* I2C1 SCL (GPIO87) */
+ALTERNATE(PIN_MASK(3, 0x48), 1, MODULE_I2C, 0)             /* I2C5 (GPIO33/36) */
+ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, GPIO_SEL_1P8V) /* I2C7 (GPIOB2/B3) - 1.8V */
+ALTERNATE(PIN_MASK(4, 0x1C), 0, MODULE_ADC, 0)             /* ADC1 (GPIO44), ADC2 (GPIO43), ADC3 (GPIO42) */
+ALTERNATE(PIN_MASK(4, 0xC0), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SDO (GPIO47), SHI_SDI (GPIO46) */
+ALTERNATE(PIN_MASK(5, 0x28), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SCLK (GPIO55), SHI_CS# (GPIO53) */
+ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)             /* PWM3 (GPIO80) - KB_BL_PWM */
+ALTERNATE(PIN_MASK(B, 0x80), 1, MODULE_PWM, 0)             /* PWM5 (GPIOB7) - EDP_BKLTCTL */
+
+/* Keyboard */
+#define GPIO_KB_INPUT           (GPIO_INPUT | GPIO_PULL_UP)
+#define GPIO_KB_OUTPUT          (GPIO_ODR_HIGH)
+#define GPIO_KB_OUTPUT_COL2     (GPIO_OUT_LOW)
+
+/* Keyboard alternate functions */
+ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)  /* KSO10 (GPIO07), KSO11 (GPIO06), KSO12 (GPIO05) */
+ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)  /* KSO03 (GPIO16), KSO04 (GPIO15), KSO05 (GPIO14), KSO06 (GPIO13), KSO07 (GPIO12), KSO08 (GPIO11), KSO09 (GPIO10) */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)  /* KSO00 (GPIO21), KSO01 (GPIO20) */
+ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)   /* KSI2 (GPIO27), KSI3 (GPIO26), KSI4 (GPIO25), KSI5 (GPIO24), KSI6 (GPIO23), KSI7 (GPIO22) */
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)   /* KSI0 (GPIO31), KSI1 (GPIO30) */
+GPIO(EC_KSO_02_INV,       PIN(1, 7), GPIO_KB_OUTPUT_COL2)              /* KSO02 (GPIO17) */
diff --git a/board/pazquel/led.c b/board/pazquel/led.c
new file mode 100644
index 0000000000..f9e1371a66
--- /dev/null
+++ b/board/pazquel/led.c
@@ -0,0 +1,153 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power and battery LED control.
+ */
+
+#include "battery.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "chipset.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "led_common.h"
+#include "system.h"
+#include "util.h"
+
+#define LED_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS)
+#define BAT_LED_ON 1
+#define BAT_LED_OFF 0
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_BATTERY_LED,
+};
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+enum led_color {
+	LED_OFF = 0,
+	LED_RED,
+	LED_BLUE,
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
+};
+
+static void led_set_color(enum led_color color)
+{
+	gpio_set_level(GPIO_EC_CHG_LED_Y_C1,
+		       (color == LED_RED) ? BAT_LED_ON : BAT_LED_OFF);
+	gpio_set_level(GPIO_EC_CHG_LED_W_C1,
+		       (color == LED_BLUE) ? BAT_LED_ON : BAT_LED_OFF);
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	brightness_range[EC_LED_COLOR_RED] = 1;
+	brightness_range[EC_LED_COLOR_BLUE] = 1;
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (brightness[EC_LED_COLOR_BLUE] != 0)
+		led_set_color(LED_BLUE);
+	else if (brightness[EC_LED_COLOR_RED] != 0)
+		led_set_color(LED_RED);
+	else
+		led_set_color(LED_OFF);
+
+	return EC_SUCCESS;
+}
+
+static void board_led_set_battery(void)
+{
+	static int battery_ticks;
+	enum led_color color = LED_OFF;
+	int period = 0;
+
+	battery_ticks++;
+
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
+		/* Always indicate amber on when charging. */
+		color = LED_RED;
+		break;
+	case LED_PWRS_DISCHARGE:
+		if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
+			/* Discharging in S3: Red 1 sec, off 3 sec */
+			period = (1 + 3) * LED_ONE_SEC;
+			battery_ticks = battery_ticks % period;
+			if (battery_ticks < 1 * LED_ONE_SEC)
+				color = LED_RED;
+			else
+				color = LED_OFF;
+		} else if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
+			/* Discharging in S5: off */
+			color = LED_OFF;
+		} else if (chipset_in_state(CHIPSET_STATE_ON)) {
+			/* Discharging in S0: Blue on */
+			color = LED_BLUE;
+		}
+		break;
+	case LED_PWRS_ERROR:
+		/* Battery error: Red 1 sec, off 1 sec */
+		period = (1 + 1) * LED_ONE_SEC;
+		battery_ticks = battery_ticks % period;
+		if (battery_ticks < 1 * LED_ONE_SEC)
+			color = LED_RED;
+		else
+			color = LED_OFF;
+		break;
+	case LED_PWRS_CHARGE_NEAR_FULL:
+		/* Full Charged: Blue on */
+		color = LED_BLUE;
+		break;
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		color = LED_BLUE;
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		/* Factory mode: Blue 2 sec, Red 2 sec */
+		period = (2 + 2) * LED_ONE_SEC;
+		battery_ticks = battery_ticks % period;
+		if (battery_ticks < 2 * LED_ONE_SEC)
+			color = LED_BLUE;
+		else
+			color = LED_RED;
+		break;
+	default:
+		/* Other states don't alter LED behavior */
+		break;
+	}
+
+	led_set_color(color);
+}
+
+/* Called by hook task every TICK */
+static void led_tick(void)
+{
+	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
+		board_led_set_battery();
+}
+DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
+
+void led_control(enum ec_led_id led_id, enum ec_led_state state)
+{
+	enum led_color color;
+
+	if ((led_id != EC_LED_ID_RECOVERY_HW_REINIT_LED) &&
+	    (led_id != EC_LED_ID_SYSRQ_DEBUG_LED))
+		return;
+
+	if (state == LED_STATE_RESET) {
+		led_auto_control(EC_LED_ID_BATTERY_LED, 1);
+		board_led_set_battery();
+		return;
+	}
+
+	color = state ? LED_BLUE : LED_OFF;
+
+	led_auto_control(EC_LED_ID_BATTERY_LED, 0);
+
+	led_set_color(color);
+}
diff --git a/board/pazquel/usbc_config.c b/board/pazquel/usbc_config.c
new file mode 100644
index 0000000000..28f6b7a1c9
--- /dev/null
+++ b/board/pazquel/usbc_config.c
@@ -0,0 +1,61 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Trogdor family-specific USB-C configuration */
+
+#include "charge_state.h"
+#include "charger.h"
+#include "charger/isl923x_public.h"
+#include "console.h"
+#include "usb_pd.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+};
+
+int charger_profile_override(struct charge_state_data *curr)
+{
+	int usb_mv;
+	int port;
+
+	if (curr->state != ST_CHARGE)
+		return 0;
+
+	/* Lower the max requested voltage to 5V when battery is full. */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
+	    !(curr->batt.flags & BATT_FLAG_BAD_STATUS) &&
+	    !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
+	    (curr->batt.status & STATUS_FULLY_CHARGED))
+		usb_mv = 5000;
+	else
+		usb_mv = PD_MAX_VOLTAGE_MV;
+
+	if (pd_get_max_voltage() != usb_mv) {
+		CPRINTS("VBUS limited to %dmV", usb_mv);
+		for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++)
+			pd_set_external_voltage_limit(port, usb_mv);
+	}
+
+	return 0;
+}
+
+enum ec_status charger_profile_override_get_param(uint32_t param,
+						  uint32_t *value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+enum ec_status charger_profile_override_set_param(uint32_t param,
+						  uint32_t value)
+{
+	return EC_RES_INVALID_PARAM;
+}
diff --git a/board/pazquel/vif_override.xml b/board/pazquel/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/pazquel/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/pdeval-stm32f072/PD_evaluation.md b/board/pdeval-stm32f072/PD_evaluation.md
index 95e31996fc..fd4763a849 100644
--- a/board/pdeval-stm32f072/PD_evaluation.md
+++ b/board/pdeval-stm32f072/PD_evaluation.md
@@ -1,17 +1,17 @@
-USB PD chip evaluation configuration
-====================================
+# USB PD chip evaluation configuration
 
-This board configuration implements a USB Power Delivery TCPM
-in order to evaluate various TCPC chips.
-The code tries to follow the preliminary USB PD interface standard but for TCPC chip implementing proprietary I2C protocol, a new TCPM file can be implemented as explained in the [Updating the code](#Updating-the-code) section below.
+This board configuration implements a USB Power Delivery TCPM in order to
+evaluate various TCPC chips. The code tries to follow the preliminary USB PD
+interface standard but for TCPC chip implementing proprietary I2C protocol, a
+new TCPM file can be implemented as explained in the
+[Updating the code](#Updating-the-code) section below.
 
-Building
---------
+## Building
 
-### ChromiumOS chroot
+### Chromium OS chroot
 
-All the following instructions have been verified in a ChromiumOS chroot.
-You can find how to set one up on the Chromium development wiki:
+All the following instructions have been verified in a ChromiumOS chroot. You
+can find how to set one up on the Chromium development:
 [http://dev.chromium.org/chromium-os/quick-start-guide](http://dev.chromium.org/chromium-os/quick-start-guide)
 
 ### Build the TCPM code
@@ -20,34 +20,52 @@ You can find how to set one up on the Chromium development wiki:
 
 `make BOARD=pdeval-stm32f072`
 
-
-Updating the code
------------------
+## Updating the code
 
 ### TCPC Communication code
 
-Please duplicate [driver/tcpm/tcpci.c](../../driver/tcpm/tcpci.c) into **driver/tcpm/##chip#name##.c**.
-Then update the control logic through I2C there.
+Please duplicate [driver/tcpm/tcpci.c](../../driver/tcpm/tcpci.c) into
+**driver/tcpm/##chip#name##.c**. Then update the control logic through I2C
+there.
 
-In order for your new code to compile, you need to update [driver/build.mk](../../driver/build.mk) with the new file :
-`driver-$(CONFIG_USB_PD_TCPM_##CHIP#NAME##)+=tcpm/##chip#name##.o`
-then document the new `CONFIG_USB_PD_TCPM_` variable in the [include/config.h](../../include/config.h) file and define it in the board configuration in [board/pdeval-stm32f072/board.h](board.h).
+In order for your new code to compile, you need to update
+[driver/build.mk](../../driver/build.mk) with the new file :
+`driver-$(CONFIG_USB_PD_TCPM_##CHIP#NAME##)+=tcpm/##chip#name##.o` then document
+the new `CONFIG_USB_PD_TCPM_` variable in the
+[include/config.h](../../include/config.h) file and define it in the board
+configuration in [board/pdeval-stm32f072/board.h](board.h).
 
 ### Board configuration
 
-In [board/pdeval-stm32f072/board.h](board.h), you can update `CONFIG_USB_PD_PORT_MAX_COUNT` to the actual number of ports on your board.
-You also need to create/delete the corresponding `PD_Cx` tasks in [board/pdeval-stm32f072/ec.tasklist](ec.tasklist).
-
-By default, the firmware is using I2C1 with SCL/SDA on pins PB6 and PB7, running with a 100kHz clock, and tries to talk to TCPCs at i2c slave addresses 0x9c and 0x9e.
-To change the pins or speed, you need to edit `i2c_ports` in [board/pdeval-stm32f072/board.c](board.c), update `I2C_PORT_TCPC` in [board/pdeval-stm32f072/board.h](board.h) with the right controller number, and change the pin mux in [board/pdeval-stm32f072/gpio.inc](gpio.inc). To change TCPC i2c slave addresses, update `TCPC1_I2C_ADDR` and `TCPC2_I2C_ADDR` in [board/pdeval-stm32f072/board.h](board.h).
-
-The I2C bus needs pull-up resistors on SCL/SDA. If your setup doesn't have external pull-ups on those lines, you can activate the chip internal pull-ups (but they are a bit weak for I2C) by editing [board/pdeval-stm32f072/gpio.inc](gpio.inc) and updating the alternate mode configuration flags with `GPIO_PULL_UP` e.g. :
-`ALTERNATE(PIN_MASK(B, 0x00c0), 1, MODULE_I2C,   GPIO_PULL_UP) /* I2C MASTER:PB6/7 */`
-
-An interrupt line, PA1, is configured to be used for the TCPC to get the attention of the TCPM. The GPIO is configured to trigger an interrupt on the falling edge and will call `tcpc_alert()`, which must be implemented in **driver/tcpm/<vendor>.c**, and should determine the cause of the interrupt and take action. The GPIO can be changed in [board/pdeval-stm32f072/gpio.inc](gpio.inc).
-
-Flashing and Running
---------------------
+In [board/pdeval-stm32f072/board.h](board.h), you can update
+`CONFIG_USB_PD_PORT_MAX_COUNT` to the actual number of ports on your board. You
+also need to create/delete the corresponding `PD_Cx` tasks in
+[board/pdeval-stm32f072/ec.tasklist](ec.tasklist).
+
+By default, the firmware is using I2C1 with SCL/SDA on pins PB6 and PB7, running
+with a 100kHz clock, and tries to talk to TCPCs at i2c target addresses 0x9c and
+0x9e. To change the pins or speed, you need to edit `i2c_ports` in
+[board/pdeval-stm32f072/board.c](board.c), update `I2C_PORT_TCPC` in
+[board/pdeval-stm32f072/board.h](board.h) with the right controller number, and
+change the pin mux in [board/pdeval-stm32f072/gpio.inc](gpio.inc). To change
+TCPC i2c target addresses, update `TCPC1_I2C_ADDR` and `TCPC2_I2C_ADDR` in
+[board/pdeval-stm32f072/board.h](board.h).
+
+The I2C bus needs pull-up resistors on SCL/SDA. If your setup doesn't have
+external pull-ups on those lines, you can activate the chip internal pull-ups
+(but they are a bit weak for I2C) by editing
+[board/pdeval-stm32f072/gpio.inc](gpio.inc) and updating the alternate mode
+configuration flags with `GPIO_PULL_UP` e.g. : `ALTERNATE(PIN_MASK(B, 0x00c0),
+1, MODULE_I2C, GPIO_PULL_UP) /* I2C MASTER:PB6/7 */`
+
+An interrupt line, PA1, is configured to be used for the TCPC to get the
+attention of the TCPM. The GPIO is configured to trigger an interrupt on the
+falling edge and will call `tcpc_alert()`, which must be implemented in
+**driver/tcpm/<vendor>.c**, and should determine the cause of the interrupt and
+take action. The GPIO can be changed in
+[board/pdeval-stm32f072/gpio.inc](gpio.inc).
+
+## Flashing and Running
 
 ### Flashing the firmware binary
 
@@ -55,37 +73,46 @@ To flash through JTAG with OpenOCD, you can just run:
 
 `sudo make flash BOARD=pdeval-stm32f072`
 
-Note: you need to do that with your USB mini-B cable is connected to the **USB ST-LINK** plug on the discovery board.
+Note: you need to do that with your USB mini-B cable is connected to the **USB
+ST-LINK** plug on the discovery board.
 
 ### Connecting to the firmware console
 
-Connect a USB cable to the **USB USER** mini-B receptacle on the board.
-`lsusb` should show you a device with the following ID : 18d1:500f
+Connect a USB cable to the **USB USER** mini-B receptacle on the board. `lsusb`
+should show you a device with the following ID : 18d1:500f
 
-You can get a console over USB by issuing the following command on a Linux computer:
+You can get a console over USB by issuing the following command on a Linux
+computer:
 
 `echo '18d1 500f' | sudo tee /sys/bus/usb-serial/drivers/generic/new_id`
 
-Testing
--------
+## Testing
 
-Currently, the TCPM is expecting to have a GPIO to detect VBUS, but to minimize the HW setup with the discovery board the alternative is to fake VBUS detection using either the **USER** button on the discovery board, or the `vbus` console command, both of which toggle the state of VBUS detected. For example, to make get a PD contract with a power adapter, plug in the adapter and then toggle VBUS on. When a PD contract above 6V is made, LED5 on the discovery board will light. To disconnect, toggle VBUS off.
+Currently, the TCPM is expecting to have a GPIO to detect VBUS, but to minimize
+the HW setup with the discovery board the alternative is to fake VBUS detection
+using either the **USER** button on the discovery board, or the `vbus` console
+command, both of which toggle the state of VBUS detected. For example, to make
+get a PD contract with a power adapter, plug in the adapter and then toggle VBUS
+on. When a PD contract above 6V is made, LED5 on the discovery board will light.
+To disconnect, toggle VBUS off.
 
 EC command line commands
 
-- `help`  List all available EC console commands
-- `vbus`  Toggle VBUS on/off
-- `pd <port> state`  Print PD protocol state information
-- `pd <port> swap data`  Request data role swap on port
-- `pd <port> swap power`  Request power role swap on port
-- `i2cscan`  Scan i2c bus for any responsive devices
-- `i2cxfer`  Perform an i2c transaction
-
-On the console, you will the PD state machine transitioning through its states with traces like `C0 st5`.
-You can always the human readable name of the current state by doing `pd 0 state` returning something like :
-`Port C0 CC1, Ena - Role: SNK-UFP State: SNK_DISCOVERY, Flags: 0x0608`
-else the numbering of the state is defined in [include/usb_pd.h](../../include/us_pd.h) by the `PD_STATE_` constants.
-It should be by default :
+-   `help` List all available EC console commands
+-   `vbus` Toggle VBUS on/off
+-   `pd <port> state` Print PD protocol state information
+-   `pd <port> swap data` Request data role swap on port
+-   `pd <port> swap power` Request power role swap on port
+-   `i2cscan` Scan i2c bus for any responsive devices
+-   `i2cxfer` Perform an i2c transaction
+
+On the console, you will the PD state machine transitioning through its states
+with traces like `C0 st5`. You can always the human readable name of the current
+state by doing `pd 0 state` returning something like : `Port C0 CC1, Ena - Role:
+SNK-UFP State: SNK_DISCOVERY, Flags: 0x0608` else the numbering of the state is
+defined in [include/usb_pd.h](../../include/us_pd.h) by the `PD_STATE_`
+constants. It should be by default :
+
 ```
 [0] DISABLED
 [1] SUSPENDED
@@ -125,27 +152,26 @@ It should be by default :
 [35] BIST_TX
 ```
 
-Known Issues
-------------
-
-1. This doc is not finished yet ...
+## Known Issues
 
-2. You might need a ChromeOS chroot ...
+1.  This doc is not finished yet ...
 
-Troubleshooting
----------------
+2.  You might need a ChromeOS chroot ...
 
-1. OpenOCD is not finding the device.
+## Troubleshooting
 
-	1. Check that your USB mini-B cable is connected to the **USB ST-LINK** plug on the discovery board.
-	2. What color is the LD1 LED on the board ?
+1.  OpenOCD is not finding the device.
 
-1. On the I2C bus, SDA/SCL lines are staying always low
+    1.  Check that your USB mini-B cable is connected to the **USB ST-LINK**
+        plug on the discovery board.
+    2.  What color is the LD1 LED on the board ?
 
-	1. You might be missing some pull-up resistors on the bus.
-	1. Check the [Board configuration](#Board-configuration) section if you cannot add external pull-ups.
+1.  On the I2C bus, SDA/SCL lines are staying always low
 
-1. You got black smoke
+    1.  You might be missing some pull-up resistors on the bus.
+    1.  Check the [Board configuration](#Board-configuration) section if you
+        cannot add external pull-ups.
 
-	1. Time to buy a new one.
+1.  You got black smoke
 
+    1.  Time to buy a new one.
diff --git a/board/pdeval-stm32f072/board.c b/board/pdeval-stm32f072/board.c
index 93f3f87082..f170319cc6 100644
--- a/board/pdeval-stm32f072/board.c
+++ b/board/pdeval-stm32f072/board.c
@@ -1,11 +1,11 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 /* STM32F072-discovery board based USB PD evaluation configuration */
 
-#include "common.h"
 #include "anx7447.h"
+#include "common.h"
 #include "ec_version.h"
 #include "gpio.h"
 #include "hooks.h"
@@ -13,7 +13,7 @@
 #include "i2c.h"
 #include "registers.h"
 #include "task.h"
-#include "tcpci.h"
+#include "tcpm/tcpci.h"
 #include "usb_descriptor.h"
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
@@ -27,13 +27,14 @@ void alert_event(enum gpio_signal signal)
 	host_command_pd_send_status(PD_CHARGE_NO_CHANGE);
 }
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 const void *const usb_strings[] = {
-	[USB_STR_DESC]         = usb_string_desc,
-	[USB_STR_VENDOR]       = USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]      = USB_STRING_DESC("PDeval-stm32f072"),
-	[USB_STR_VERSION]      = USB_STRING_DESC(CROS_EC_VERSION32),
+	[USB_STR_DESC] = usb_string_desc,
+	[USB_STR_VENDOR] = USB_STRING_DESC("Google LLC"),
+	[USB_STR_PRODUCT] = USB_STRING_DESC("PDeval-stm32f072"),
+	[USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32),
 	[USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Shell"),
 };
 
@@ -52,9 +53,11 @@ void board_reset_pd_mcu(void)
 }
 
 /* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"tcpc", I2C_PORT_TCPC, 400 /* kHz */, GPIO_I2C0_SCL, GPIO_I2C0_SDA}
-};
+const struct i2c_port_t i2c_ports[] = { { .name = "tcpc",
+					  .port = I2C_PORT_TCPC,
+					  .kbps = 400 /* kHz */,
+					  .scl = GPIO_I2C0_SCL,
+					  .sda = GPIO_I2C0_SDA } };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
 const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
diff --git a/board/pdeval-stm32f072/board.h b/board/pdeval-stm32f072/board.h
index 6da1c7c1f0..6ba7923b8e 100644
--- a/board/pdeval-stm32f072/board.h
+++ b/board/pdeval-stm32f072/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,11 +15,12 @@
 #undef CONFIG_UART_CONSOLE
 #define CONFIG_UART_CONSOLE 2
 
+#define CONFIG_LTO
+
 /* Optional features */
 #define CONFIG_HW_CRC
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
-#define CONFIG_STM_HWTIMER32
+#define CONFIG_I2C_CONTROLLER
 /* USB Power Delivery configuration */
 #define CONFIG_USB_POWER_DELIVERY
 #define CONFIG_USB_PD_TCPMV1
@@ -32,6 +33,7 @@
 #define CONFIG_USB_PD_VBUS_DETECT_TCPC
 #define CONFIG_USB_PD_TCPM_ANX7447
 #define CONFIG_USB_PD_TCPM_MUX
+#define CONFIG_USBC_SS_MUX
 
 #undef CONFIG_USB_PD_INITIAL_DRP_STATE
 #define CONFIG_USB_PD_INITIAL_DRP_STATE PD_DRP_TOGGLE_ON
@@ -40,14 +42,14 @@
 #define CONFIG_USB_PD_PULLUP TYPEC_RP_USB
 
 /* fake board specific type-C power constants */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 650000 /* us */
 
 /* Define typical operating power and max power */
 #define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       60000
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_VOLTAGE_MV     20000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* I2C master port connected to the TCPC */
 #define I2C_PORT_TCPC 0
@@ -58,7 +60,6 @@
 #define CONFIG_USBC_VCONN
 #define CONFIG_USBC_VCONN_SWAP
 /* delay to turn on/off vconn */
-#define PD_VCONN_SWAP_DELAY 5000 /* us */
 
 /* USB Configuration */
 #define CONFIG_USB
@@ -67,15 +68,19 @@
 
 /* USB interface indexes (use define rather than enum to expand them) */
 #define USB_IFACE_CONSOLE 0
-#define USB_IFACE_COUNT   1
+#define USB_IFACE_COUNT 1
 
 /* USB endpoint indexes (use define rather than enum to expand them) */
 #define USB_EP_CONTROL 0
 #define USB_EP_CONSOLE 1
-#define USB_EP_COUNT   2
+#define USB_EP_COUNT 2
 
+/* Remove console commands / features for flash / RAM savings */
 #undef CONFIG_WATCHDOG_HELP
 #undef CONFIG_LID_SWITCH
+#undef CONFIG_CONSOLE_HISTORY
+#undef CONFIG_HIBERNATE
+#undef CONFIG_CMD_CRASH
 
 /*
  * Allow dangerous commands all the time, since we don't have a write protect
diff --git a/board/pdeval-stm32f072/build.mk b/board/pdeval-stm32f072/build.mk
index ef1346d534..2238f8f59a 100644
--- a/board/pdeval-stm32f072/build.mk
+++ b/board/pdeval-stm32f072/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -10,4 +10,4 @@ CHIP:=stm32
 CHIP_FAMILY:=stm32f0
 CHIP_VARIANT:=stm32f07x
 
-board-y=board.o usb_pd_policy.o
+board-y=board.o usb_pd_policy.o usb_pd_pdo.o
diff --git a/board/pdeval-stm32f072/ec.tasklist b/board/pdeval-stm32f072/ec.tasklist
index 5003fc7ba1..e897969a55 100644
--- a/board/pdeval-stm32f072/ec.tasklist
+++ b/board/pdeval-stm32f072/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/pdeval-stm32f072/gpio.inc b/board/pdeval-stm32f072/gpio.inc
index 5409077c34..fb8537ffbe 100644
--- a/board/pdeval-stm32f072/gpio.inc
+++ b/board/pdeval-stm32f072/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/pdeval-stm32f072/openocd-flash.cfg b/board/pdeval-stm32f072/openocd-flash.cfg
index ec32416934..05a697acf8 100644
--- a/board/pdeval-stm32f072/openocd-flash.cfg
+++ b/board/pdeval-stm32f072/openocd-flash.cfg
@@ -1,4 +1,4 @@
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
+# Copyright 2014 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/board/pdeval-stm32f072/usb_pd_pdo.c b/board/pdeval-stm32f072/usb_pd_pdo.c
new file mode 100644
index 0000000000..31d84f9785
--- /dev/null
+++ b/board/pdeval-stm32f072/usb_pd_pdo.c
@@ -0,0 +1,21 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "compile_time_macros.h"
+#include "usb_pd.h"
+#include "usb_pd_pdo.h"
+
+#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP)
+
+const uint32_t pd_src_pdo[] = {
+	PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS),
+};
+const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
+
+const uint32_t pd_snk_pdo[] = {
+	PDO_FIXED(5000, 900, PDO_FIXED_FLAGS),
+	PDO_BATT(5000, 21000, 30000),
+};
+const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
diff --git a/board/pdeval-stm32f072/usb_pd_pdo.h b/board/pdeval-stm32f072/usb_pd_pdo.h
new file mode 100644
index 0000000000..13640a7471
--- /dev/null
+++ b/board/pdeval-stm32f072/usb_pd_pdo.h
@@ -0,0 +1,17 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_BOARD_PDEVAL_STM32F072_USB_PD_PDO_H
+#define __CROS_EC_BOARD_PDEVAL_STM32F072_USB_PD_PDO_H
+
+#include "stdint.h"
+
+extern const uint32_t pd_src_pdo[1];
+extern const int pd_src_pdo_cnt;
+
+extern const uint32_t pd_snk_pdo[2];
+extern const int pd_snk_pdo_cnt;
+
+#endif /* __CROS_EC_BOARD_PDEVAL_STM32F072_USB_PD_PDO_H */
diff --git a/board/pdeval-stm32f072/usb_pd_policy.c b/board/pdeval-stm32f072/usb_pd_policy.c
index 78026c9e7b..eb9a8ef9d5 100644
--- a/board/pdeval-stm32f072/usb_pd_policy.c
+++ b/board/pdeval-stm32f072/usb_pd_policy.c
@@ -1,10 +1,10 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include "common.h"
 #include "anx7447.h"
+#include "common.h"
 #include "console.h"
 #include "gpio.h"
 #include "hooks.h"
@@ -12,34 +12,26 @@
 #include "system.h"
 #include "task.h"
 #include "timer.h"
-#include "util.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
+#include "usb_pd_pdo.h"
+#include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 /* Used to fake VBUS presence since no GPIO is available to read VBUS */
 static int vbus_present;
 
-const uint32_t pd_src_pdo[] = {
-		PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS),
-};
-const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
-
-const uint32_t pd_snk_pdo[] = {
-		PDO_FIXED(5000, 900, PDO_FIXED_FLAGS),
-		PDO_BATT(5000, 21000, 30000),
-};
-const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
-
 #if defined(CONFIG_USB_PD_TCPM_MUX) && defined(CONFIG_USB_PD_TCPM_ANX7447)
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.driver    = &anx7447_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &anx7447_usb_mux_driver,
+				.hpd_update = &anx7447_tcpc_update_hpd_status,
+			},
 	},
 };
 #endif
@@ -48,11 +40,11 @@ const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 int pd_set_power_supply_ready(int port)
 {
 	/* Disable charging */
-	anx7447_board_charging_enable(port, 0);
+	tcpm_set_snk_ctrl(port, 0);
 
 	/* Provide VBUS */
 	gpio_set_level(GPIO_VBUS_PMIC_CTRL, 1);
-	anx7447_set_power_supply_ready(port);
+	tcpm_set_src_ctrl(port, 1);
 
 	/* notify host of power info change */
 
@@ -64,12 +56,12 @@ int pd_set_power_supply_ready(int port)
 void pd_power_supply_reset(int port)
 {
 	/* Disable VBUS */
-	anx7447_power_supply_reset(port);
+	tcpm_set_src_ctrl(port, 0);
 	gpio_set_level(GPIO_VBUS_PMIC_CTRL, 0);
 	CPRINTS("Disable VBUS, port%d", port);
 
 	/* Enable charging */
-	anx7447_board_charging_enable(port, 1);
+	tcpm_set_snk_ctrl(port, 1);
 }
 #else
 int pd_set_power_supply_ready(int port)
@@ -92,8 +84,8 @@ void pd_power_supply_reset(int port)
 void pd_set_input_current_limit(int port, uint32_t max_ma,
 				uint32_t supply_voltage)
 {
-	CPRINTS("USBPD current limit port %d max %d mA %d mV",
-		port, max_ma, supply_voltage);
+	CPRINTS("USBPD current limit port %d max %d mA %d mV", port, max_ma,
+		supply_voltage);
 	/* do some LED coding of the power we can sink */
 	if (max_ma) {
 		if (supply_voltage > 6500)
@@ -109,8 +101,8 @@ void pd_set_input_current_limit(int port, uint32_t max_ma,
 __override void typec_set_input_current_limit(int port, uint32_t max_ma,
 					      uint32_t supply_voltage)
 {
-	CPRINTS("TYPEC current limit port %d max %d mA %d mV",
-		port, max_ma, supply_voltage);
+	CPRINTS("TYPEC current limit port %d max %d mA %d mV", port, max_ma,
+		supply_voltage);
 	gpio_set_level(GPIO_LED_R, !!max_ma);
 }
 
@@ -120,24 +112,21 @@ void button_event(enum gpio_signal signal)
 	CPRINTS("VBUS %d", vbus_present);
 }
 
-static int command_vbus_toggle(int argc, char **argv)
+static int command_vbus_toggle(int argc, const char **argv)
 {
 	vbus_present = !vbus_present;
 	CPRINTS("VBUS %d", vbus_present);
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(vbus, command_vbus_toggle,
-			"",
-			"Toggle VBUS detected");
+DECLARE_CONSOLE_COMMAND(vbus, command_vbus_toggle, "", "Toggle VBUS detected");
 
 int pd_snk_is_vbus_provided(int port)
 {
 	return vbus_present;
 }
 
-__override int pd_check_data_swap(int port,
-				  enum pd_data_role data_role)
+__override int pd_check_data_swap(int port, enum pd_data_role data_role)
 {
 	/* Always allow data swap */
 	return 1;
@@ -155,22 +144,18 @@ int pd_check_vconn_swap(int port)
 }
 #endif
 
-__override void pd_check_pr_role(int port,
-				 enum pd_power_role pr_role,
+__override void pd_check_pr_role(int port, enum pd_power_role pr_role,
 				 int flags)
 {
 }
 
-__override void pd_check_dr_role(int port,
-				 enum pd_data_role dr_role,
-				 int flags)
+__override void pd_check_dr_role(int port, enum pd_data_role dr_role, int flags)
 {
 }
 /* ----------------- Vendor Defined Messages ------------------ */
 const uint32_t vdo_idh = VDO_IDH(1, /* data caps as USB host */
 				 0, /* data caps as USB device */
-				 IDH_PTYPE_PERIPH,
-				 0, /* supports alt modes */
+				 IDH_PTYPE_PERIPH, 0, /* supports alt modes */
 				 0x0000);
 
 const uint32_t vdo_product = VDO_PRODUCT(0x0000, 0x0000);
@@ -194,78 +179,72 @@ __override void svdm_safe_dp_mode(int port)
 {
 	/* make DP interface safe until configure */
 	dp_flags[port] = 0;
-	/* board_set_usb_mux(port, USB_PD_MUX_NONE, pd_get_polarity(port)); */
+	/*
+	 * board_set_usb_mux(port, USB_PD_MUX_NONE,
+	 * polarity_rm_dts(pd_get_polarity(port)));
+	 */
 }
 
 __override int svdm_dp_config(int port, uint32_t *payload)
 {
-	int opos = pd_alt_mode(port, TCPC_TX_SOP, USB_SID_DISPLAYPORT);
+	int opos = pd_alt_mode(port, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT);
 	int pin_mode = pd_dfp_dp_get_pin_mode(port, dp_status[port]);
-#if defined(CONFIG_USB_PD_TCPM_MUX) && defined(CONFIG_USB_PD_TCPM_ANX7447)
-	const struct usb_mux *mux = &usb_muxes[port];
-#endif
-
-#ifdef CONFIG_USB_PD_TCPM_ANX7447
 	mux_state_t mux_state = USB_PD_MUX_NONE;
-	if (pd_get_polarity(port))
-		mux_state |= USB_PD_MUX_POLARITY_INVERTED;
-#endif
 
 	CPRINTS("pin_mode = %d", pin_mode);
 	if (!pin_mode)
 		return 0;
 
-#if defined(CONFIG_USB_PD_TCPM_MUX) && defined(CONFIG_USB_PD_TCPM_ANX7447)
 	switch (pin_mode) {
 	case MODE_DP_PIN_A:
 	case MODE_DP_PIN_C:
 	case MODE_DP_PIN_E:
 		mux_state |= USB_PD_MUX_DP_ENABLED;
-		mux->driver->set(mux, mux_state);
 		break;
 	case MODE_DP_PIN_B:
 	case MODE_DP_PIN_D:
 	case MODE_DP_PIN_F:
 		mux_state |= USB_PD_MUX_DOCK;
-		mux->driver->set(mux, mux_state);
 		break;
 	}
-#endif
+	usb_mux_set(port, mux_state, USB_SWITCH_CONNECT,
+		    polarity_rm_dts(pd_get_polarity(port)));
 
 	/*
 	 * board_set_usb_mux(port, USB_PD_MUX_DP_ENABLED,
-	 * pd_get_polarity(port));
+	 * polarity_rm_dts(pd_get_polarity(port)));
 	 */
-	payload[0] = VDO(USB_SID_DISPLAYPORT, 1,
-			 CMD_DP_CONFIG | VDO_OPOS(opos));
+	payload[0] =
+		VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_CONFIG | VDO_OPOS(opos));
 	payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */
-				1,             /* DPv1.3 signaling */
-				2);            /* UFP connected */
+				1, /* DPv1.3 signaling */
+				2); /* UFP connected */
 	return 2;
 }
 
 __override void svdm_dp_post_config(int port)
 {
-	const struct usb_mux *mux = &usb_muxes[port];
-
 	dp_flags[port] |= DP_FLAGS_DP_ON;
 	if (!(dp_flags[port] & DP_FLAGS_HPD_HI_PENDING))
 		return;
 
-	if (IS_ENABLED(CONFIG_USB_PD_TCPM_ANX7447))
-		anx7447_tcpc_update_hpd_status(mux, 1, 0);
+	usb_mux_hpd_update(port,
+			   USB_PD_MUX_HPD_LVL | USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
 
 __override int svdm_dp_attention(int port, uint32_t *payload)
 {
-#ifdef CONFIG_USB_PD_TCPM_ANX7447
 	int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]);
 	int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]);
-	const struct usb_mux *mux = &usb_muxes[port];
 
+	mux_state_t mux_state =
+		(lvl ? USB_PD_MUX_HPD_LVL : USB_PD_MUX_HPD_LVL_DEASSERTED) |
+		(irq ? USB_PD_MUX_HPD_IRQ : USB_PD_MUX_HPD_IRQ_DEASSERTED);
+
+	/* Note: Usage is deprecated, use usb_mux_hpd_update instead */
 	CPRINTS("Attention: 0x%x", payload[1]);
-	anx7447_tcpc_update_hpd_status(mux, lvl, irq);
-#endif
+	usb_mux_hpd_update(port, mux_state);
+
 	dp_status[port] = payload[1];
 
 	/* ack */
@@ -274,9 +253,7 @@ __override int svdm_dp_attention(int port, uint32_t *payload)
 
 __override void svdm_exit_dp_mode(int port)
 {
-	svdm_safe_dp_mode(port);
-#ifdef CONFIG_USB_PD_TCPM_ANX7447
-	anx7447_tcpc_clear_hpd_status(port);
-#endif
+	usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
+					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
 #endif /* CONFIG_USB_PD_ALT_MODE_DFP */
diff --git a/board/pdeval-stm32f072/vif_override.xml b/board/pdeval-stm32f072/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/pdeval-stm32f072/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/phaser/battery.c b/board/phaser/battery.c
index 2e1f77d552..25a0fbce92 100644
--- a/board/phaser/battery.c
+++ b/board/phaser/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/phaser/board.c b/board/phaser/board.c
index 219f5ad1b1..803cb18dd2 100644
--- a/board/phaser/board.c
+++ b/board/phaser/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,8 @@
 /* Phaser board-specific configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
+#include "battery_smart.h"
+#include "builtin/stdnoreturn.h"
 #include "button.h"
 #include "charge_state.h"
 #include "common.h"
@@ -25,23 +26,24 @@
 #include "power.h"
 #include "power_button.h"
 #include "switch.h"
-#include "task.h"
+#include "system_chip.h"
 #include "tablet_mode.h"
-#include "tcpci.h"
+#include "task.h"
+#include "tcpm/tcpci.h"
 #include "temp_sensor.h"
-#include "thermistor.h"
+#include "temp_sensor/thermistor.h"
 #include "usbc_ppc.h"
 #include "util.h"
-#include "battery_smart.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define USB_PD_PORT_ANX7447	0
-#define USB_PD_PORT_PS8751	1
+#define USB_PD_PORT_ANX7447 0
+#define USB_PD_PORT_PS8751 1
 
 static uint8_t sku_id;
 static bool support_syv_ppc;
+static uint8_t is_psl_hibernate;
 
 /* Check PPC ID and board version to decide which one ppc is used. */
 static bool board_is_support_syv_ppc(void)
@@ -84,31 +86,31 @@ static void ppc_interrupt(enum gpio_signal signal)
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_AMB] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_AMB] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				  ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_CHARGER] = { "TEMP_CHARGER", NPCX_ADC_CH1,
+				      ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 },
 	/* Vbus sensing (1/10 voltage divider). */
-	[ADC_VBUS_C0] = {
-		"VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
-	[ADC_VBUS_C1] = {
-		"VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
+	[ADC_VBUS_C0] = { "VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT * 10,
+			  ADC_READ_MAX + 1, 0 },
+	[ADC_VBUS_C1] = { "VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT * 10,
+			  ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp,
-				 .idx = 0},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
+	[TEMP_SENSOR_BATTERY] = { .name = "Battery",
+				  .type = TEMP_SENSOR_TYPE_BATTERY,
+				  .read = charge_get_battery_temp,
+				  .idx = 0 },
+	[TEMP_SENSOR_AMBIENT] = { .name = "Ambient",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_51k1_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_AMB },
+	[TEMP_SENSOR_CHARGER] = { .name = "Charger",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_13k7_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_CHARGER },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -118,11 +120,9 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrix to rotate lid and base sensor into standard reference frame */
-const mat33_fp_t standard_rot_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
+const mat33_fp_t standard_rot_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				      { 0, FLOAT_TO_FP(-1), 0 },
+				      { 0, 0, FLOAT_TO_FP(1) } };
 
 /* sensor private data */
 static struct stprivate_data g_lis2dh_data;
@@ -168,8 +168,6 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_base_mutex,
 		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
 				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
 		.port = I2C_PORT_SENSOR,
 		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
 		.rot_standard_ref = &standard_rot_ref,
@@ -200,8 +198,6 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_base_mutex,
 		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
 				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
 		.port = I2C_PORT_SENSOR,
 		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
 		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
@@ -215,8 +211,8 @@ unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
 static int board_is_convertible(void)
 {
-	return sku_id == 2 || sku_id == 3 || sku_id == 4 || sku_id == 5 || \
-		sku_id == 255;
+	return sku_id == 2 || sku_id == 3 || sku_id == 4 || sku_id == 5 ||
+	       sku_id == 255;
 }
 
 static void board_update_sensor_config_from_sku(void)
@@ -245,12 +241,103 @@ static void cbi_init(void)
 	board_update_sensor_config_from_sku();
 
 	support_syv_ppc = board_is_support_syv_ppc();
+
+	/* Please correct the SKU ID checking if it is not right */
+	if (sku_id == 1 || sku_id == 2 || sku_id == 3 || sku_id == 4)
+		is_psl_hibernate = 0;
+	else
+		is_psl_hibernate = 1;
 }
 DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1);
 
-#ifndef TEST_BUILD
+static void system_psl_type_sel(int psl_no, uint32_t flags)
+{
+	/* Set PSL input events' type as level or edge trigger */
+	if ((flags & GPIO_INT_F_HIGH) || (flags & GPIO_INT_F_LOW))
+		CLEAR_BIT(NPCX_GLUE_PSL_CTS, psl_no + 4);
+	else if ((flags & GPIO_INT_F_RISING) || (flags & GPIO_INT_F_FALLING))
+		SET_BIT(NPCX_GLUE_PSL_CTS, psl_no + 4);
+
+	/*
+	 * Set PSL input events' polarity is low (high-to-low) active or
+	 * high (low-to-high) active
+	 */
+	if (flags & GPIO_HIB_WAKE_HIGH)
+		SET_BIT(NPCX_DEVALT(ALT_GROUP_D), 2 * psl_no);
+	else
+		CLEAR_BIT(NPCX_DEVALT(ALT_GROUP_D), 2 * psl_no);
+}
+
+int system_config_psl_mode(enum gpio_signal signal)
+{
+	int psl_no;
+	const struct gpio_info *g = gpio_list + signal;
+
+	if (g->port == GPIO_PORT_D && g->mask == MASK_PIN2) /* GPIOD2 */
+		psl_no = 0;
+	else if (g->port == GPIO_PORT_0 && (g->mask & 0x07)) /* GPIO00/01/02 */
+		psl_no = GPIO_MASK_TO_NUM(g->mask) + 1;
+	else
+		return 0;
+
+	system_psl_type_sel(psl_no, g->flags);
+	return 1;
+}
+
+void system_enter_psl_mode(void)
+{
+	/* Configure pins from GPIOs to PSL which rely on VSBY power rail. */
+	gpio_config_module(MODULE_PMU, 1);
+
+	/*
+	 * Only PSL_IN events can pull PSL_OUT to high and reboot ec.
+	 * We should treat it as wake-up pin reset.
+	 */
+	NPCX_BBRAM(BBRM_DATA_INDEX_WAKE) = HIBERNATE_WAKE_PIN;
+
+	/*
+	 * Pull PSL_OUT (GPIO85) to low to cut off ec's VCC power rail by
+	 * setting bit 5 of PDOUT(8).
+	 */
+	SET_BIT(NPCX_PDOUT(GPIO_PORT_8), 5);
+}
+
+/* Hibernate function implemented by PSL (Power Switch Logic) mode. */
+noreturn void __keep __enter_hibernate_in_psl(void)
+{
+	system_enter_psl_mode();
+	/* Spin and wait for PSL cuts power; should never return */
+	while (1)
+		;
+}
+void board_hibernate_late(void)
+{
+	int i;
+
+	/*
+	 * If the SKU cannot use PSL hibernate, immediately return to go the
+	 * non-PSL hibernate flow.
+	 */
+	if (!is_psl_hibernate) {
+		NPCX_KBSINPU = 0x0A;
+		return;
+	}
+
+	for (i = 0; i < hibernate_wake_pins_used; i++) {
+		/* Config PSL pins setting for wake-up inputs */
+		if (!system_config_psl_mode(hibernate_wake_pins[i]))
+			ccprintf("Invalid PSL setting in wake-up pin %d\n", i);
+	}
+
+	/* Clear all pending IRQ otherwise wfi will have no affect */
+	for (i = NPCX_IRQ_0; i < NPCX_IRQ_COUNT; i++)
+		task_clear_pending_irq(i);
+
+	__enter_hibernate_in_psl();
+}
+
 /* This callback disables keyboard when convertibles are fully open */
-void lid_angle_peripheral_enable(int enable)
+__override void lid_angle_peripheral_enable(int enable)
 {
 	/*
 	 * If the lid is in tablet position via other sensors,
@@ -263,7 +350,6 @@ void lid_angle_peripheral_enable(int enable)
 	if (board_is_convertible())
 		keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
 }
-#endif
 
 int board_is_lid_angle_tablet_mode(void)
 {
@@ -271,11 +357,11 @@ int board_is_lid_angle_tablet_mode(void)
 }
 
 /* Battery functions */
-#define SB_OPTIONALMFG_FUNCTION2		0x3e
+#define SB_OPTIONALMFG_FUNCTION2 0x3e
 /* Optional mfg function2 */
-#define SMART_QUICK_CHARGE			(1<<12)
+#define SMART_QUICK_CHARGE (1 << 12)
 /* Quick charge support */
-#define MODE_QUICK_CHARGE_SUPPORT		(1<<4)
+#define MODE_QUICK_CHARGE_SUPPORT (1 << 4)
 
 static void sb_quick_charge_mode(int enable)
 {
@@ -324,15 +410,15 @@ void board_overcurrent_event(int port, int is_overcurrented)
 }
 
 static const struct ppc_config_t ppc_syv682x_port0 = {
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
+	.i2c_port = I2C_PORT_TCPC0,
+	.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+	.drv = &syv682x_drv,
 };
 
 static const struct ppc_config_t ppc_syv682x_port1 = {
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
+	.i2c_port = I2C_PORT_TCPC1,
+	.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+	.drv = &syv682x_drv,
 };
 
 static void board_setup_ppc(void)
@@ -340,12 +426,10 @@ static void board_setup_ppc(void)
 	if (!support_syv_ppc)
 		return;
 
-	memcpy(&ppc_chips[USB_PD_PORT_TCPC_0],
-		&ppc_syv682x_port0,
-		sizeof(struct ppc_config_t));
-	memcpy(&ppc_chips[USB_PD_PORT_TCPC_1],
-		&ppc_syv682x_port1,
-		sizeof(struct ppc_config_t));
+	memcpy(&ppc_chips[USB_PD_PORT_TCPC_0], &ppc_syv682x_port0,
+	       sizeof(struct ppc_config_t));
+	memcpy(&ppc_chips[USB_PD_PORT_TCPC_1], &ppc_syv682x_port1,
+	       sizeof(struct ppc_config_t));
 
 	gpio_set_flags(GPIO_USB_PD_C0_INT_ODL, GPIO_INT_BOTH);
 	gpio_set_flags(GPIO_USB_PD_C1_INT_ODL, GPIO_INT_BOTH);
diff --git a/board/phaser/board.h b/board/phaser/board.h
index e230c98efc..54f3cf3b32 100644
--- a/board/phaser/board.h
+++ b/board/phaser/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,12 +13,27 @@
 #define VARIANT_OCTOPUS_CHARGER_ISL9238
 #include "baseboard.h"
 
+/* b/203442963
+ * It's workaround to reduce keyboard's "Silver Migration".
+ * From keyboard vendor's feedback, there are two factors to cause
+ * "Silver Migration".
+ * 1. A voltage potential between trace.
+ * 2. The presence of an electrolyte , such as moisture.
+ * The reason cause voltage potential between KSIxx trace is EC enter ec
+ * hibernate PSL and turn EC's VCC1 power off. Besides KSI2, the other
+ * KSIxx will be turn off. KSI2 is powered by H1.
+ * To avoid voltage potential is keep KSIxx on. That means not to enter
+ * ec hibernate PSL.
+ */
+#undef CONFIG_HIBERNATE_PSL
+
+#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD
+
 #define CONFIG_VOLUME_BUTTONS
 #define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
 #define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
 
 #define CONFIG_LED_COMMON
-#define CONFIG_LED_POWER_LED
 #define CONFIG_TEMP_SENSOR
 #define CONFIG_THERMISTOR
 #define CONFIG_STEINHART_HART_3V3_13K7_47K_4050B
@@ -29,8 +44,8 @@
 #define CONFIG_CMD_ACCEL_INFO
 
 /* Sensors */
-#define CONFIG_ACCEL_LIS2DE             /* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM        /* Base accel */
+#define CONFIG_ACCEL_LIS2DE /* Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
 /* Sensors without hardware FIFO are in forced mode */
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
 
@@ -45,9 +60,11 @@
 
 /* Additional PPC second source */
 #define CONFIG_USBC_PPC_SYV682X
-#define	CONFIG_USBC_PPC_DEDICATED_INT
-#undef	CONFIG_SYV682X_HV_ILIM
+#define CONFIG_USBC_PPC_DEDICATED_INT
+#undef CONFIG_SYV682X_HV_ILIM
 #define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_5_50
+/* SYV682 isn't connected to CC, so TCPC must provide VCONN */
+#define CONFIG_USBC_PPC_SYV682X_NO_CC
 
 #ifndef __ASSEMBLER__
 
@@ -55,10 +72,10 @@
 #include "registers.h"
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_AMB,		/* ADC0 */
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC1 */
-	ADC_VBUS_C0,			/* ADC9 */
-	ADC_VBUS_C1,			/* ADC4 */
+	ADC_TEMP_SENSOR_AMB, /* ADC0 */
+	ADC_TEMP_SENSOR_CHARGER, /* ADC1 */
+	ADC_VBUS_C0, /* ADC9 */
+	ADC_VBUS_C1, /* ADC4 */
 	ADC_CH_COUNT,
 };
 
@@ -69,18 +86,10 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_COUNT };
 
 /* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
diff --git a/board/phaser/build.mk b/board/phaser/build.mk
index 3d04b75731..998a65a3de 100644
--- a/board/phaser/build.mk
+++ b/board/phaser/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/phaser/ec.tasklist b/board/phaser/ec.tasklist
index d98db145e7..977b8b01be 100644
--- a/board/phaser/ec.tasklist
+++ b/board/phaser/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/phaser/gpio.inc b/board/phaser/gpio.inc
index 639ed914b6..c6d2be7fc6 100644
--- a/board/phaser/gpio.inc
+++ b/board/phaser/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/phaser/led.c b/board/phaser/led.c
index 115832e3b6..16f68b28f9 100644
--- a/board/phaser/led.c
+++ b/board/phaser/led.c
@@ -1,53 +1,57 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Power and battery LED control for Phaser
  */
 
+#include "chipset.h"
 #include "ec_commands.h"
 #include "gpio.h"
 #include "led_common.h"
 #include "led_onoff_states.h"
-#include "chipset.h"
 
 #define LED_ON_LVL 0
 #define LED_OFF_LVL 1
 
-const int led_charge_lvl_1 = 5;
+__override const int led_charge_lvl_1 = 5;
 
-const int led_charge_lvl_2 = 97;
+__override const int led_charge_lvl_2 = 97;
 
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
 
-const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-					{LED_OFF,	   0.5 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 3 * LED_ONE_SEC },
+					       { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-	EC_LED_ID_BATTERY_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED,
+					     EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-void led_set_color_power(enum ec_led_colors color)
+__override void led_set_color_power(enum ec_led_colors color)
 {
 	if (color == EC_LED_COLOR_WHITE)
 		gpio_set_level(GPIO_PWR_LED_WHITE_L, LED_ON_LVL);
@@ -56,7 +60,7 @@ void led_set_color_power(enum ec_led_colors color)
 		gpio_set_level(GPIO_PWR_LED_WHITE_L, LED_OFF_LVL);
 }
 
-void led_set_color_battery(enum ec_led_colors color)
+__override void led_set_color_battery(enum ec_led_colors color)
 {
 	switch (color) {
 	case EC_LED_COLOR_RED:
@@ -109,4 +113,3 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 
 	return EC_SUCCESS;
 }
-
diff --git a/board/phaser/vif_override.xml b/board/phaser/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/phaser/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/pico/battery.c b/board/pico/battery.c
new file mode 100644
index 0000000000..5e1671f5f3
--- /dev/null
+++ b/board/pico/battery.c
@@ -0,0 +1,189 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "battery_fuel_gauge.h"
+#include "gpio.h"
+
+const struct board_batt_params board_battery_info[] = {
+	/* LGC AP18C8K Battery Information */
+	[BATTERY_LGC_AP18C8K] = {
+		.fuel_gauge = {
+			.manuf_name = "LGC KT0030G020",
+			.device_name = "AP18C8K",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.reg_addr = 0x43,
+				.reg_mask = 0x0001,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max		= 13050,
+			.voltage_normal		= 11250,
+			.voltage_min		= 9000,
+			.precharge_current	= 256,
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 75,
+		},
+	},
+	/* Murata AP18C4K Battery Information */
+	[BATTERY_MURATA_AP18C4K] = {
+		.fuel_gauge = {
+			.manuf_name = "Murata KT00304012",
+			.device_name = "AP18C4K",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.reg_addr = 0x0,
+				.reg_mask = 0x2000,
+				.disconnect_val = 0x2000,
+			},
+		},
+		.batt_info = {
+			.voltage_max		= 13200,
+			.voltage_normal		= 11400,
+			.voltage_min		= 9000,
+			.precharge_current	= 256,
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 75,
+		},
+	},
+	/* Panasonic AP19B5K Battery Information */
+	[BATTERY_PANASONIC_AP19B5K_KT00305011] = {
+		.fuel_gauge = {
+			.manuf_name = "PANASONIC KT00305011",
+			.device_name = "AP19B5K",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.reg_addr = 0x0,
+				.reg_mask = 0x4000,
+				.disconnect_val = 0x0,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13200,
+			.voltage_normal		= 11550,
+			.voltage_min		= 9000,
+			.precharge_current	= 256,
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 75,
+		},
+	},
+	/* LGC AP19B8K Battery Information */
+	 [BATTERY_LGC_AP19B8K] = {
+		.fuel_gauge = {
+			.manuf_name = "LGC KT0030G022",
+			.device_name = "AP19B8K",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.reg_addr = 0x43,
+				.reg_mask = 0x0001,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max            = 13050,
+			.voltage_normal         = 11250,
+			.voltage_min            = 9000,
+			.precharge_current      = 256,
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 50,
+			.charging_min_c         = 0,
+			.charging_max_c         = 60,
+			.discharging_min_c      = -20,
+			.discharging_max_c      = 75,
+		},
+	},
+	/* COSMX AP20CBL Battery Information */
+	 [BATTERY_COSMX_AP20CBL] = {
+		.fuel_gauge = {
+			.manuf_name = "COSMX KT0030B002",
+			.device_name = "AP20CBL",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0002,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max            = 13200,
+			.voltage_normal         = 11550,
+			.voltage_min            = 9000,
+			.precharge_current      = 256,
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 50,
+			.charging_min_c         = 0,
+			.charging_max_c         = 60,
+			.discharging_min_c      = -20,
+			.discharging_max_c      = 75,
+		},
+	},
+	/* SMP AP18C7K Battery Information */
+	 [BATTERY_SMP_AP18C7K] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP KT00307010",
+			.device_name = "AP18C7K",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0002,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max            = 13200,
+			.voltage_normal         = 11550,
+			.voltage_min            = 9000,
+			.precharge_current      = 256,
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 45,
+			.charging_min_c         = 0,
+			.charging_max_c         = 60,
+			.discharging_min_c      = -20,
+			.discharging_max_c      = 75,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_LGC_AP18C8K;
+
+enum battery_present battery_hw_present(void)
+{
+	return gpio_get_level(GPIO_EC_BATT_PRES_ODL) ? BP_NO : BP_YES;
+}
diff --git a/board/pico/board.c b/board/pico/board.c
new file mode 100644
index 0000000000..30708c3adc
--- /dev/null
+++ b/board/pico/board.c
@@ -0,0 +1,421 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc.h"
+#include "backlight.h"
+#include "button.h"
+#include "charge_manager.h"
+#include "charge_ramp.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "driver/accel_kionix.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "driver/battery/max17055.h"
+#include "driver/bc12/pi3usb9201.h"
+#include "driver/charger/isl923x.h"
+#include "driver/tcpm/it83xx_pd.h"
+#include "driver/usb_mux/it5205.h"
+#include "ec_commands.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "i2c.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "panic.h"
+#include "power.h"
+#include "power_button.h"
+#include "registers.h"
+#include "spi.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "tcpm/tcpm.h"
+#include "timer.h"
+#include "uart.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd_tcpm.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+#ifndef VARIANT_KUKUI_NO_SENSORS
+/* Motion sensors */
+/* Mutexes */
+static struct mutex g_lid_mutex;
+static struct mutex g_base_mutex;
+
+/* Rotation matrixes */
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
+
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, FLOAT_TO_FP(1), 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
+
+/* sensor private data */
+static struct kionix_accel_data g_kx022_data;
+static struct bmi_drv_data_t g_bmi160_data;
+
+struct motion_sensor_t motion_sensors[] = {
+	[LID_ACCEL] = {
+	 .name = "Lid Accel",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_KX022,
+	 .type = MOTIONSENSE_TYPE_ACCEL,
+	 .location = MOTIONSENSE_LOC_LID,
+	 .drv = &kionix_accel_drv,
+	 .mutex = &g_lid_mutex,
+	 .drv_data = &g_kx022_data,
+	 .port = I2C_PORT_SENSORS,
+	 .i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
+	 .rot_standard_ref = &lid_standard_ref,
+	 .min_frequency = KX022_ACCEL_MIN_FREQ,
+	 .max_frequency = KX022_ACCEL_MAX_FREQ,
+	 .default_range = 2, /* g, enough to calculate lid angle. */
+	 .config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+		 /* Sensor on for lid angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	 },
+	},
+	/*
+	 * Note: bmi160: supports accelerometer and gyro sensor
+	 * Requirement: accelerometer sensor must init before gyro sensor
+	 * DO NOT change the order of the following table.
+	 */
+	[BASE_ACCEL] = {
+	 .name = "Accel",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_BMI160,
+	 .type = MOTIONSENSE_TYPE_ACCEL,
+	 .location = MOTIONSENSE_LOC_BASE,
+	 .drv = &bmi160_drv,
+	 .mutex = &g_base_mutex,
+	 .drv_data = &g_bmi160_data,
+	 .port = I2C_PORT_SENSORS,
+	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+	 .rot_standard_ref = &base_standard_ref,
+	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
+	 .min_frequency = BMI_ACCEL_MIN_FREQ,
+	 .max_frequency = BMI_ACCEL_MAX_FREQ,
+	 .config = {
+		 /* EC use accel for angle detection */
+		 [SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		 },
+		 /* Sensor on for angle detection */
+		 [SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		 },
+	 },
+	},
+	[BASE_GYRO] = {
+	 .name = "Gyro",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_BMI160,
+	 .type = MOTIONSENSE_TYPE_GYRO,
+	 .location = MOTIONSENSE_LOC_BASE,
+	 .drv = &bmi160_drv,
+	 .mutex = &g_base_mutex,
+	 .drv_data = &g_bmi160_data,
+	 .port = I2C_PORT_SENSORS,
+	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+	 .default_range = 1000, /* dps */
+	 .rot_standard_ref = &base_standard_ref,
+	 .min_frequency = BMI_GYRO_MIN_FREQ,
+	 .max_frequency = BMI_GYRO_MAX_FREQ,
+	},
+};
+unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+static bool board_is_convertible(void)
+{
+	int sku = system_get_sku_id();
+
+	return sku == 1 || sku == 2;
+}
+
+int board_sensor_at_360(void)
+{
+	if (board_is_convertible())
+		return !gpio_get_level(GPIO_TABLET_MODE_L);
+
+	return 0;
+}
+#endif /* !VARIANT_KUKUI_NO_SENSORS */
+/*
+ * Map keyboard connector pins to EC GPIO pins for factory test.
+ * Pins mapped to {-1, -1} are skipped.
+ * The connector has 24 pins total, and there is no pin 0.
+ */
+const int keyboard_factory_scan_pins[][2] = {
+	{ -1, -1 },	   { GPIO_KSO_H, 4 }, { GPIO_KSO_H, 0 },
+	{ GPIO_KSO_H, 1 }, { GPIO_KSO_H, 3 }, { GPIO_KSO_H, 2 },
+	{ -1, -1 },	   { -1, -1 },	      { GPIO_KSO_L, 5 },
+	{ GPIO_KSO_L, 6 }, { -1, -1 },	      { GPIO_KSO_L, 3 },
+	{ GPIO_KSO_L, 2 }, { GPIO_KSI, 0 },   { GPIO_KSO_L, 1 },
+	{ GPIO_KSO_L, 4 }, { GPIO_KSI, 3 },   { GPIO_KSI, 2 },
+	{ GPIO_KSO_L, 0 }, { GPIO_KSI, 5 },   { GPIO_KSI, 4 },
+	{ GPIO_KSO_L, 7 }, { GPIO_KSI, 6 },   { GPIO_KSI, 7 },
+	{ GPIO_KSI, 1 },   { -1, -1 },	      { GPIO_KSO_H, 5 },
+	{ -1, -1 },	   { GPIO_KSO_H, 6 }, { -1, -1 },
+	{ -1, -1 },
+};
+
+const int keyboard_factory_scan_pins_used =
+	ARRAY_SIZE(keyboard_factory_scan_pins);
+
+/* Wake-up pins for hibernate */
+const enum gpio_signal hibernate_wake_pins[] = {
+	GPIO_AC_PRESENT,
+	GPIO_LID_OPEN,
+	GPIO_POWER_BUTTON_L,
+};
+const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
+
+/******************************************************************************/
+/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
+const struct adc_t adc_channels[] = {
+	[ADC_BOARD_ID] = { "BOARD_ID", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0,
+			   CHIP_ADC_CH1 },
+	[ADC_EC_SKU_ID] = { "EC_SKU_ID", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0,
+			    CHIP_ADC_CH2 },
+	[ADC_VBUS] = { "VBUS", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0,
+		       CHIP_ADC_CH0 },
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/******************************************************************************/
+/* I2C ports */
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "typec",
+	  .port = IT83XX_I2C_CH_C,
+	  .kbps = 400,
+	  .scl = GPIO_I2C_C_SCL,
+	  .sda = GPIO_I2C_C_SDA },
+	{ .name = "sensor",
+	  .port = IT83XX_I2C_CH_B,
+	  .kbps = 400,
+	  .scl = GPIO_I2C_B_SCL,
+	  .sda = GPIO_I2C_B_SDA },
+	{ .name = "battery",
+	  .port = IT83XX_I2C_CH_A,
+	  .kbps = 100,
+	  .scl = GPIO_I2C_A_SCL,
+	  .sda = GPIO_I2C_A_SDA },
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+#define BC12_I2C_ADDR PI3USB9201_I2C_ADDR_3
+
+/* power signal list.  Must match order of enum power_signal. */
+const struct power_signal_info power_signal_list[] = {
+	{ GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" },
+	{ GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" },
+};
+BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
+
+/******************************************************************************/
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	{
+		.i2c_port = I2C_PORT_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+};
+
+/******************************************************************************/
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_EMBEDDED,
+		/* TCPC is embedded within EC so no i2c config needed */
+		.drv = &it8xxx2_tcpm_drv,
+		/* Alert is active-low, push-pull */
+		.flags = 0,
+	},
+};
+
+static void board_hpd_status(const struct usb_mux *me, mux_state_t mux_state,
+			     bool *ack_required)
+{
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
+	/*
+	 * svdm_dp_attention() did most of the work, we only need to notify
+	 * host here.
+	 */
+	host_set_single_event(EC_HOST_EVENT_USB_MUX);
+}
+
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+				.hpd_update = &board_hpd_status,
+			},
+	},
+};
+
+/* Charger config.  Start i2c address at 1, update during runtime */
+struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+};
+
+static int force_discharge;
+
+int board_set_active_charge_port(int charge_port)
+{
+	CPRINTS("New chg p%d", charge_port);
+
+	/* ignore all request when discharge mode is on */
+	if (force_discharge && charge_port != CHARGE_PORT_NONE)
+		return EC_SUCCESS;
+
+	switch (charge_port) {
+	case CHARGE_PORT_USB_C:
+		/* Don't charge from a source port */
+		if (board_vbus_source_enabled(charge_port))
+			return -1;
+		break;
+	default:
+		/*
+		 * To ensure the fuel gauge (max17055) is always powered
+		 * even when battery is disconnected, keep VBAT rail on but
+		 * set the charging current to minimum.
+		 */
+		charger_set_current(CHARGER_SOLO, 0);
+		break;
+	}
+
+	return EC_SUCCESS;
+}
+
+int board_discharge_on_ac(int enable)
+{
+	int ret, port;
+
+	if (enable) {
+		port = CHARGE_PORT_NONE;
+	} else {
+		/* restore the charge port state */
+		port = charge_manager_get_override();
+		if (port == OVERRIDE_OFF)
+			port = charge_manager_get_active_charge_port();
+	}
+
+	ret = charger_discharge_on_ac(enable);
+	if (ret)
+		return ret;
+
+	force_discharge = enable;
+	return board_set_active_charge_port(port);
+}
+
+#define VBUS_THRESHOLD_MV 4200
+int pd_snk_is_vbus_provided(int port)
+{
+	/* This board has only one port. */
+	if (!port)
+		return adc_read_channel(ADC_VBUS) > VBUS_THRESHOLD_MV ? 1 : 0;
+	else
+		return 0;
+}
+
+void bc12_interrupt(enum gpio_signal signal)
+{
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+
+static void board_init(void)
+{
+	/* If the reset cause is external, pulse PMIC force reset. */
+	if (system_get_reset_flags() == EC_RESET_FLAG_RESET_PIN) {
+		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 0);
+		msleep(100);
+		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 1);
+	}
+
+#ifndef VARIANT_KUKUI_NO_SENSORS
+	/* Enable interrupts from BMI160 sensor. */
+	gpio_enable_interrupt(GPIO_ACCEL_INT_ODL);
+#endif /* VARIANT_KUKUI_NO_SENSORS */
+
+	/* Enable interrupt from PMIC. */
+	gpio_enable_interrupt(GPIO_PMIC_EC_RESETB);
+
+	/* Enable BC12 interrupt */
+	gpio_enable_interrupt(GPIO_BC12_EC_INT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+#ifndef VARIANT_KUKUI_NO_SENSORS
+static void board_motion_init(void)
+{
+	if (!board_is_convertible()) {
+		/* Disable motion sense. */
+		motion_sensor_count = 0;
+		gpio_disable_interrupt(GPIO_ACCEL_INT_ODL);
+		gpio_set_flags(GPIO_ACCEL_INT_ODL, GPIO_INPUT);
+		/* Disable tablet mode. */
+		tablet_set_mode(0, TABLET_TRIGGER_LID);
+		gmr_tablet_switch_disable();
+		gpio_set_flags(GPIO_TABLET_MODE_L, GPIO_INPUT | GPIO_PULL_UP);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, board_motion_init, HOOK_PRIO_DEFAULT + 1);
+#endif /* VARIANT_KUKUI_NO_SENSORS */
+
+/* Vconn control for integrated ITE TCPC */
+void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
+{
+	/* Vconn control is only for port 0 */
+	if (port)
+		return;
+
+	if (cc_pin == USBPD_CC_PIN_1)
+		gpio_set_level(GPIO_EN_USB_C0_CC1_VCONN, !!enabled);
+	else
+		gpio_set_level(GPIO_EN_USB_C0_CC2_VCONN, !!enabled);
+}
+
+/* Called on AP S5 -> S3 transition */
+static void board_chipset_startup(void)
+{
+	gpio_set_level(GPIO_EN_USBA_5V, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S3 -> S5 transition */
+static void board_chipset_shutdown(void)
+{
+	gpio_set_level(GPIO_EN_USBA_5V, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
diff --git a/board/pico/board.h b/board/pico/board.h
new file mode 100644
index 0000000000..1cfed1eba1
--- /dev/null
+++ b/board/pico/board.h
@@ -0,0 +1,156 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Configuration for Kukui */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#define VARIANT_KUKUI_JACUZZI
+#define VARIANT_KUKUI_BATTERY_SMART
+#define VARIANT_KUKUI_CHARGER_ISL9238
+#define VARIANT_KUKUI_EC_IT81202
+
+#ifndef SECTION_IS_RW
+#define VARIANT_KUKUI_NO_SENSORS
+#endif /* SECTION_IS_RW */
+
+#include "baseboard.h"
+
+/* TODO: remove me once we fix IT83XX_ILM_BLOCK_SIZE out of space issue */
+#undef CONFIG_LTO
+
+#undef CONFIG_CHIPSET_POWER_SEQ_VERSION
+#define CONFIG_CHIPSET_POWER_SEQ_VERSION 1
+
+#define CONFIG_BATTERY_HW_PRESENT_CUSTOM
+
+#define CONFIG_CHARGER_PSYS
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 5
+
+#define CONFIG_CHARGER_RUNTIME_CONFIG
+
+#define CONFIG_BC12_DETECT_PI3USB9201
+
+#define CONFIG_EXTPOWER_GPIO
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
+#define CONFIG_EXTPOWER_DEBOUNCE_MS 200
+
+#undef CONFIG_I2C_NACK_RETRY_COUNT
+#define CONFIG_I2C_NACK_RETRY_COUNT 10
+#define CONFIG_SMBUS_PEC
+
+#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP
+#define CONFIG_USB_PD_DISCHARGE_GPIO
+#define CONFIG_USB_PD_TCPC_LOW_POWER
+
+#define CONFIG_USB_MUX_IT5205
+
+/* Motion Sensors */
+#ifndef VARIANT_KUKUI_NO_SENSORS
+#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
+#define CONFIG_ACCEL_KX022 /* Lid accel */
+#define CONFIG_ACCELGYRO_BMI160 /* Base accel */
+#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+#define CONFIG_ALS
+#define CONFIG_CMD_ACCEL_INFO
+
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_UPDATE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+
+#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
+
+#define CONFIG_GMR_TABLET_MODE_CUSTOM
+#endif /* !VARIANT_KUKUI_NO_SENSORS */
+
+/* I2C ports */
+#define I2C_PORT_BC12 IT83XX_I2C_CH_C
+#define I2C_PORT_TCPC0 IT83XX_I2C_CH_C
+#define I2C_PORT_USB_MUX IT83XX_I2C_CH_C
+#define I2C_PORT_CHARGER IT83XX_I2C_CH_A
+#define I2C_PORT_SENSORS IT83XX_I2C_CH_B
+#define I2C_PORT_ACCEL I2C_PORT_SENSORS
+#define I2C_PORT_BATTERY IT83XX_I2C_CH_A
+#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
+
+#define CONFIG_KEYBOARD_PROTOCOL_MKBP
+#define CONFIG_MKBP_EVENT
+#define CONFIG_MKBP_USE_GPIO
+
+#define CONFIG_LED_ONOFF_STATES
+
+#ifndef __ASSEMBLER__
+
+enum adc_channel {
+	/* Real ADC channels begin here */
+	ADC_BOARD_ID = 0,
+	ADC_EC_SKU_ID,
+	ADC_VBUS,
+	ADC_CH_COUNT
+};
+
+/* power signal definitions */
+enum power_signal {
+	AP_IN_S3_L,
+	PMIC_PWR_GOOD,
+
+	/* Number of signals */
+	POWER_SIGNAL_COUNT,
+};
+
+/* Motion sensors */
+enum sensor_id {
+	LID_ACCEL = 0,
+	BASE_ACCEL,
+	BASE_GYRO,
+	SENSOR_COUNT,
+};
+
+enum charge_port {
+	CHARGE_PORT_USB_C,
+};
+
+enum battery_type {
+	BATTERY_LGC_AP18C8K,
+	BATTERY_MURATA_AP18C4K,
+	BATTERY_PANASONIC_AP19B5K_KT00305011,
+	BATTERY_LGC_AP19B8K,
+	BATTERY_COSMX_AP20CBL,
+	BATTERY_SMP_AP18C7K,
+	BATTERY_TYPE_COUNT,
+};
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+/* support factory keyboard test */
+#define CONFIG_KEYBOARD_FACTORY_TEST
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+extern const int keyboard_factory_scan_pins[][2];
+extern const int keyboard_factory_scan_pins_used;
+
+#ifdef SECTION_IS_RO
+/* Interrupt handler for AP jump to BL */
+void emmc_ap_jump_to_bl(enum gpio_signal signal);
+#endif
+
+void bc12_interrupt(enum gpio_signal signal);
+void board_reset_pd_mcu(void);
+int board_get_version(void);
+
+/* returns the i2c port number of charger/battery */
+int board_get_charger_i2c(void);
+int board_get_battery_i2c(void);
+
+/* Motion sensor interrupt */
+void motion_interrupt(enum gpio_signal signal);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/pico/build.mk b/board/pico/build.mk
new file mode 100644
index 0000000000..a1ca27116e
--- /dev/null
+++ b/board/pico/build.mk
@@ -0,0 +1,15 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+#
+# IC is ITE IT81202
+CHIP:=it83xx
+CHIP_FAMILY:=it8xxx2
+CHIP_VARIANT:=it81202bx_1024
+BASEBOARD:=kukui
+
+board-y=battery.o board.o led.o
diff --git a/board/pico/ec.tasklist b/board/pico/ec.tasklist
new file mode 100644
index 0000000000..883033408a
--- /dev/null
+++ b/board/pico/ec.tasklist
@@ -0,0 +1,18 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS_RW(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 1024) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, 1280)
diff --git a/board/pico/gpio.inc b/board/pico/gpio.inc
new file mode 100644
index 0000000000..359e25451e
--- /dev/null
+++ b/board/pico/gpio.inc
@@ -0,0 +1,150 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first.
+ */
+
+/* Interrupts */
+GPIO_INT(POWER_BUTTON_L,    PIN(E, 4), GPIO_INT_BOTH,
+         power_button_interrupt) /* EC_PWR_BTN_ODL */
+GPIO_INT(AP_IN_SLEEP_L,     PIN(F, 2), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V,
+         power_signal_interrupt)
+GPIO_INT(PMIC_EC_RESETB,    PIN(F, 3), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V,
+         power_signal_interrupt)
+GPIO_INT(WARM_RESET_REQ,    PIN(D, 3), GPIO_INT_RISING | GPIO_PULL_DOWN | GPIO_SEL_1P8V,
+         chipset_reset_request_interrupt)
+GPIO_INT_RW(ACCEL_INT_ODL,  PIN(J, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V,
+	 bmi160_interrupt)
+GPIO_INT_RO(BOOTBLOCK_EN_L, PIN(J, 1), GPIO_INT_RISING | GPIO_SEL_1P8V,
+         emmc_ap_jump_to_bl)
+GPIO_INT(SPI0_CS,           PIN(M, 5), GPIO_INT_FALLING,
+         spi_event)        /* SPI slave Chip Select -- AP_SPI_EC_CS_L */
+GPIO_INT(LID_OPEN,          PIN(E, 2), GPIO_INT_BOTH,
+         lid_interrupt)
+GPIO_INT(AC_PRESENT,        PIN(E, 5), GPIO_INT_BOTH,
+         extpower_interrupt) /* ACOK_OD */
+GPIO_INT(BC12_EC_INT_ODL,   PIN(J, 6), GPIO_INT_FALLING,
+         bc12_interrupt)
+GPIO_INT(AP_EC_WATCHDOG_L,  PIN(C, 7), GPIO_INT_FALLING | GPIO_SEL_1P8V,
+         chipset_watchdog_interrupt)
+GPIO_INT(UART1_RX,          PIN(B, 0), GPIO_INT_FALLING,
+         uart_deepsleep_interrupt) /* UART_DEBUG_TX_EC_RX */
+GPIO_INT(TABLET_MODE_L,     PIN(J, 7), GPIO_INT_BOTH,
+	 gmr_tablet_switch_isr)
+/* Unimplemented interrupts */
+GPIO(VOLUME_DOWN_L,         PIN(D, 5), GPIO_INPUT)
+GPIO(VOLUME_UP_L,           PIN(D, 6), GPIO_INPUT)
+GPIO(ALS_RGB_INT_ODL,       PIN(F, 0), GPIO_INPUT)
+GPIO(LID_ACCEL_INT_ODL,     PIN(J, 3), GPIO_INPUT | GPIO_SEL_1P8V)
+
+/* Reset pins */
+GPIO(AP_SYS_RST_L,          PIN(B, 6), GPIO_OUT_LOW)
+/* 1.8V PP or 1.8V OD output with external 10K PU  */
+GPIO(PMIC_WATCHDOG_L,       PIN(H, 0), GPIO_ODR_LOW | GPIO_SEL_1P8V)
+/* OD output with 5VT (there is 5V internal PU on PWRKEY of MT6358) */
+GPIO(PMIC_EN_ODL,           PIN(E, 1), GPIO_ODR_HIGH)
+
+/*
+ * I2C pins should be configured as inputs until I2C module is
+ * initialized. This will avoid driving the lines unintentionally.
+ */
+/* EC programming */
+GPIO(I2C_E_SCL,              PIN(A, 4), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(I2C_E_SDA,              PIN(A, 5), GPIO_INPUT | GPIO_SEL_1P8V)
+/* battery and charger */
+GPIO(I2C_A_SCL,              PIN(B, 3), GPIO_INPUT)
+GPIO(I2C_A_SDA,              PIN(B, 4), GPIO_INPUT)
+/* sensor */
+GPIO(I2C_B_SCL,              PIN(C, 1), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(I2C_B_SDA,              PIN(C, 2), GPIO_INPUT | GPIO_SEL_1P8V)
+/* typec */
+GPIO(I2C_C_SCL,              PIN(F, 6), GPIO_INPUT)
+GPIO(I2C_C_SDA,              PIN(F, 7), GPIO_INPUT)
+
+/* Other input pins */
+/* TODO(WP_L): change to interrupt pin ? */
+GPIO(WP_L,                 PIN(I, 4), GPIO_INPUT | GPIO_SEL_1P8V) /* EC_FLASH_WP_ODL */
+GPIO(CCD_MODE_ODL,         PIN(C, 4), GPIO_INPUT)
+
+/* Other output pins */
+GPIO(EC_BATT_PRES_ODL,     PIN(C, 0), GPIO_INPUT)
+GPIO(EC_BL_EN_OD,          PIN(B, 5), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(EN_USBA_5V,           PIN(B, 7), GPIO_OUT_LOW)
+GPIO(ENTERING_RW,          PIN(C, 5), GPIO_ODR_HIGH)  /* EC_ENTERING_RW_ODL */
+GPIO(EC_INT_L,             PIN(E, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V)  /* EC_AP_INT_ODL */
+GPIO(EC_BOARD_ID_EN_L,     PIN(H, 5), GPIO_ODR_HIGH)  /* EC_BOARD_ID_EN_ODL */
+GPIO(USB_C0_HPD_OD,        PIN(J, 0), GPIO_ODR_LOW)
+GPIO(USB_C0_DISCHARGE,     PIN(H, 3), GPIO_OUT_LOW)
+GPIO(EN_USB_C0_CC1_VCONN,  PIN(H, 1), GPIO_OUT_LOW)
+GPIO(EN_USB_C0_CC2_VCONN,  PIN(H, 2), GPIO_OUT_LOW)
+
+/* LEDs */
+GPIO(LED_BLUE,             PIN(A, 2), GPIO_OUT_HIGH)
+GPIO(LED_GREEN,            PIN(A, 1), GPIO_OUT_HIGH)
+GPIO(LED_ORANGE,           PIN(A, 0), GPIO_OUT_HIGH)
+GPIO(EN_PP1800_S5_L,       PIN(D, 0), GPIO_OUT_LOW)
+
+/* Unimplemented Pins  */
+GPIO(PG_PP5000_A_OD,       PIN(A, 6), GPIO_INPUT)
+GPIO(USB_A0_OC_ODL,        PIN(A, 7), GPIO_INPUT)
+GPIO(EC_PROCHOT_ODL,       PIN(C, 3), GPIO_INPUT)
+GPIO(PMIC_FORCE_RESET_ODL, PIN(C, 6), GPIO_INPUT)
+GPIO(USB_C0_PD_INT_ODL,    PIN(D, 1), GPIO_INPUT) /* no used on this board */
+GPIO(EN_PP5000A_USM,       PIN(D, 7), GPIO_INPUT)
+GPIO(EN_USBC_CHARGE_L,     PIN(F, 1), GPIO_INPUT)
+GPIO(EN_PP5000_USBC,       PIN(H, 4), GPIO_INPUT)
+GPIO(PP1800_H1_PG,         PIN(H, 6), GPIO_INPUT)
+
+/* NC pins, ensure they aren't in floating state. */
+GPIO(NC_GPA3,              PIN(A, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(NC_GPB2,              PIN(B, 2), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(NC_GPD2,              PIN(D, 2), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(NC_GPD4,              PIN(D, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(NC_GPE0,              PIN(E, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(NC_GPE3,              PIN(E, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(NC_GPE7,              PIN(E, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+/*
+ * ADC pins don't have internal pull-down capability,
+ * so we set them as output low.
+ */
+GPIO(NC_GPI5,              PIN(I, 5), GPIO_OUT_LOW)
+GPIO(NC_GPI7,              PIN(I, 7), GPIO_OUT_LOW)
+
+GPIO(NC_GPJ4,              PIN(J, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(NC_GPJ5,              PIN(J, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+/*
+ * GPG3,4,5,7 don't have internal pull-down capability,
+ * so we set them as output low.
+ */
+GPIO(NC_GPG0,              PIN(G, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+/* Don't touch GPG1 and GPG2 */
+GPIO(NC_GPG3,              PIN(G, 3), GPIO_OUT_LOW)
+GPIO(EC_SPI_FLASH_MOSI,    PIN(G, 4), GPIO_OUT_LOW)
+GPIO(EC_SPI_FLASH_MISO,    PIN(G, 5), GPIO_OUT_LOW)
+GPIO(EC_SPI_FLASH_CLK,     PIN(G, 6), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(EC_SPI_FLASH_CS_L,    PIN(G, 7), GPIO_OUT_LOW)
+
+/* Alternate functions GPIO definitions */
+/* Keyboard */
+ALTERNATE(PIN_MASK(KSI,   0xFF), 0, MODULE_KEYBOARD_SCAN, 0) /* KSI0-7 */
+ALTERNATE(PIN_MASK(KSO_H, 0xFF), 0, MODULE_KEYBOARD_SCAN, 0) /* KSO8-15 */
+ALTERNATE(PIN_MASK(KSO_L, 0xFB), 0, MODULE_KEYBOARD_SCAN, 0) /* KSO0-1, 3-7 */
+GPIO(EC_KSO_02_INV, PIN(KSO_L, 2), GPIO_OUT_LOW)	     /* KSO2 inverted */
+/* I2C */
+ALTERNATE(PIN_MASK(B, 0x18), 1, MODULE_I2C, 0) /* I2C A */
+ALTERNATE(PIN_MASK(C, 0x06), 1, MODULE_I2C, GPIO_SEL_1P8V) /* I2C B */
+ALTERNATE(PIN_MASK(F, 0xC0), 1, MODULE_I2C, 0) /* I2C C */
+/* ADC */
+ALTERNATE(PIN_MASK(I, 0x4F), 0, MODULE_ADC, 0)  /* ADC 0,1,2,3,6 */
+/* UART */
+ALTERNATE(PIN_MASK(B, 0x03), 1, MODULE_UART, 0) /* EC to Servo */
+/* EMMC SPI SLAVE M2:CLK, M3:CMD, M6:DATA0 */
+ALTERNATE(PIN_MASK(M, 0x4C), 0, MODULE_SPI_FLASH,  0)
+/* SPI */
+ALTERNATE(PIN_MASK(M, 0x33), 0, MODULE_SPI, 0) /* SPI for communication */
diff --git a/board/pico/led.c b/board/pico/led.c
new file mode 100644
index 0000000000..bbbad7ceb8
--- /dev/null
+++ b/board/pico/led.c
@@ -0,0 +1,85 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power and battery LED control for Jacuzzi
+ */
+#include "common.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+#define LED_ON_LVL 0
+#define LED_OFF_LVL 1
+__override const int led_charge_lvl_1 = 5;
+__override const int led_charge_lvl_2 = 95;
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_AMBER:
+		gpio_set_level(GPIO_LED_ORANGE, LED_ON_LVL);
+		gpio_set_level(GPIO_LED_BLUE, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_GREEN, LED_OFF_LVL);
+		break;
+	case EC_LED_COLOR_BLUE:
+		gpio_set_level(GPIO_LED_BLUE, LED_ON_LVL);
+		gpio_set_level(GPIO_LED_ORANGE, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_GREEN, LED_OFF_LVL);
+		break;
+	case EC_LED_COLOR_GREEN:
+		gpio_set_level(GPIO_LED_GREEN, LED_ON_LVL);
+		gpio_set_level(GPIO_LED_BLUE, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_ORANGE, LED_OFF_LVL);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		gpio_set_level(GPIO_LED_GREEN, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_BLUE, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_ORANGE, LED_OFF_LVL);
+		break;
+	}
+}
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		brightness_range[EC_LED_COLOR_BLUE] = 1;
+		brightness_range[EC_LED_COLOR_GREEN] = 1;
+	}
+}
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(EC_LED_COLOR_AMBER);
+		else if (brightness[EC_LED_COLOR_BLUE] != 0)
+			led_set_color_battery(EC_LED_COLOR_BLUE);
+		else if (brightness[EC_LED_COLOR_GREEN] != 0)
+			led_set_color_battery(EC_LED_COLOR_GREEN);
+		else
+			led_set_color_battery(LED_OFF);
+	}
+	return EC_SUCCESS;
+}
diff --git a/board/pico/vif_override.xml b/board/pico/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/pico/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/pirika/battery.c b/board/pirika/battery.c
new file mode 100644
index 0000000000..f753eba554
--- /dev/null
+++ b/board/pirika/battery.c
@@ -0,0 +1,94 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "charge_state.h"
+#include "common.h"
+
+/*
+ * Battery info for all waddledee battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	/*COSMX  CA14J43 Battery Information */
+	[BATTERY_CA14J43] = {
+		.fuel_gauge = {
+			.manuf_name = "PG01LJ3353",
+			.device_name = "CA14J43",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_mask = 0x6000,
+				.disconnect_val = 0x6000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13200, /* mV */
+			.voltage_normal		= 11550, /* mV */
+			.voltage_min		= 9000, /* mV */
+			.precharge_current	= 256,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 60,
+		},
+	},
+	/*COSMX CA11J58 Battery Information */
+	[BATTERY_CA11J58] = {
+		.fuel_gauge = {
+			.manuf_name = "PG01NL3353",
+			.device_name = "CA11J58",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_mask = 0x6000,
+				.disconnect_val = 0x6000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 8800, /* mV */
+			.voltage_normal		= 7700, /* mV */
+			.voltage_min		= 6000, /* mV */
+			.precharge_current	= 256,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 45,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 60,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_CA14J43;
diff --git a/board/pirika/board.c b/board/pirika/board.c
new file mode 100644
index 0000000000..d1baae03f2
--- /dev/null
+++ b/board/pirika/board.c
@@ -0,0 +1,789 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Waddledee board-specific configuration */
+
+#include "adc_chip.h"
+#include "button.h"
+#include "cbi_fw_config.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "driver/accel_kionix.h"
+#include "driver/accelgyro_lsm6dsm.h"
+#include "driver/bc12/pi3usb9201.h"
+#include "driver/charger/isl923x.h"
+#include "driver/retimer/tusb544.h"
+#include "driver/tcpm/raa489000.h"
+#include "driver/temp_sensor/thermistor.h"
+#include "driver/usb_mux/it5205.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "intc.h"
+#include "keyboard_raw.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "switch.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "tcpm/tcpci.h"
+#include "temp_sensor.h"
+#include "uart.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+
+#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+
+#define INT_RECHECK_US 5000
+
+/* C0 interrupt line shared by BC 1.2 and charger */
+static void check_c0_line(void);
+DECLARE_DEFERRED(check_c0_line);
+
+/* Use default keyboard scan config, because board didn't supply one */
+__override struct keyboard_scan_config keyscan_config = {
+	/*
+	 * CONFIG_KEYBOARD_COL2_INVERTED is defined for passing the column 2
+	 * to H1 which inverts the signal. The signal passing through H1
+	 * adds more delay. Need a larger delay value. Otherwise, pressing
+	 * Refresh key will also trigger T key, which is in the next scanning
+	 * column line. See http://b/156007029.
+	 */
+	.output_settle_us = 80,
+	.debounce_down_us = 9 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x1c, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
+		0xa4, 0xff, 0xf6, 0x55, 0xfa, 0xca  /* full set */
+	},
+};
+
+static const struct ec_response_keybd_config pirika_kb = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+static const struct ec_response_keybd_config pasara_kb = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY | KEYBD_CAP_NUMERIC_KEYPAD,
+};
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	if (get_cbi_fw_config_numeric_pad() == NUMERIC_PAD_ABSENT)
+		return &pirika_kb;
+	else
+		return &pasara_kb;
+}
+
+static void notify_c0_chips(void)
+{
+	schedule_deferred_pd_interrupt(0);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+
+static void check_c0_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		notify_c0_chips();
+		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+	}
+}
+
+static void usb_c0_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c0_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c0_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+}
+
+/* C1 interrupt line shared by BC 1.2, TCPC, and charger */
+static void check_c1_line(void);
+DECLARE_DEFERRED(check_c1_line);
+
+static void notify_c1_chips(void)
+{
+	schedule_deferred_pd_interrupt(1);
+	usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+}
+
+static void check_c1_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips.
+	 */
+	if (!gpio_get_level(GPIO_USB_C1_INT_ODL)) {
+		notify_c1_chips();
+		hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
+	}
+}
+
+static void usb_c1_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c1_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c1_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
+}
+
+static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
+{
+	cprints(CC_USBPD, "C0: CC OVP, SBU OVP, or thermal event");
+	pd_handle_cc_overvoltage(0);
+}
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	[ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH0 },
+	[ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH2 },
+	[ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH3 },
+	[ADC_TEMP_SENSOR_3] = { .name = "TEMP_SENSOR3",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH15 },
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* BC 1.2 chips */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	{
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+		.flags = PI3USB9201_ALWAYS_POWERED,
+	},
+	{
+		.i2c_port = I2C_PORT_SUB_USB_C1,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+		.flags = PI3USB9201_ALWAYS_POWERED,
+	},
+};
+
+int pd_snk_is_vbus_provided(int port)
+{
+	return pd_check_vbus_level(port, VBUS_PRESENT);
+}
+
+/* Charger chips */
+const struct charger_config_t chg_chips[] = {
+	[CHARGER_PRIMARY] = {
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+	[CHARGER_SECONDARY] = {
+		.i2c_port = I2C_PORT_SUB_USB_C1,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+};
+
+/* TCPCs */
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0,
+			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
+		},
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+		.drv = &raa489000_tcpm_drv,
+	},
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_SUB_USB_C1,
+			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
+		},
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+		.drv = &raa489000_tcpm_drv,
+	},
+};
+
+/* USB Retimer */
+enum tusb544_conf { USB_DP = 0, USB_DP_INV, USB, USB_INV, DP, DP_INV };
+
+static int board_tusb544_set(const struct usb_mux *me, mux_state_t mux_state)
+{
+	int rv = EC_SUCCESS;
+	enum tusb544_conf usb_mode = 0;
+	/* USB */
+	if (mux_state & USB_PD_MUX_USB_ENABLED) {
+		/* USB with DP */
+		if (mux_state & USB_PD_MUX_DP_ENABLED) {
+			usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ?
+					   USB_DP_INV :
+					   USB_DP;
+		}
+		/* USB without DP */
+		else {
+			usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ?
+					   USB_INV :
+					   USB;
+		}
+	}
+	/* DP without USB */
+	else if (mux_state & USB_PD_MUX_DP_ENABLED) {
+		usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ? DP_INV :
+									DP;
+	}
+	/* Nothing enabled */
+	else
+		return EC_SUCCESS;
+	/* Write the retimer config byte */
+	if (usb_mode == USB_INV) {
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_GENERAL4, 0x15);
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_DISPLAYPORT_1, 0x33);
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_DISPLAYPORT_2, 0x33);
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_USB3_1_1, 0x22);
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_USB3_1_2, 0x22);
+	} else if (usb_mode == USB) {
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_GENERAL4, 0x11);
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_DISPLAYPORT_1, 0x33);
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_DISPLAYPORT_2, 0x33);
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_USB3_1_1, 0x22);
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_USB3_1_2, 0x22);
+	} else if (usb_mode == USB_DP_INV) {
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_GENERAL4, 0x1F);
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_DISPLAYPORT_1, 0x33);
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_DISPLAYPORT_2, 0x99);
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_USB3_1_1, 0x22);
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_USB3_1_2, 0x22);
+	} else if (usb_mode == USB_DP) {
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_GENERAL4, 0x1B);
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_DISPLAYPORT_1, 0x99);
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_DISPLAYPORT_2, 0x33);
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_USB3_1_1, 0x22);
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_USB3_1_2, 0x22);
+	} else if (usb_mode == DP_INV) {
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_GENERAL4, 0x1E);
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_DISPLAYPORT_1, 0x99);
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_DISPLAYPORT_2, 0x99);
+	} else if (usb_mode == DP) {
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_GENERAL4, 0x1A);
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_DISPLAYPORT_1, 0x99);
+		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				TUSB544_REG_DISPLAYPORT_2, 0x99);
+	}
+
+	return rv;
+}
+
+const struct usb_mux_chain usbc1_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = 1,
+			.i2c_port = I2C_PORT_SUB_USB_C1,
+			.i2c_addr_flags = TUSB544_I2C_ADDR_FLAGS0,
+			.driver = &tusb544_drv,
+			.board_set = &board_tusb544_set,
+		},
+};
+
+/* USB Muxes */
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+			},
+	},
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_SUB_USB_C1,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+			},
+		.next = &usbc1_retimer,
+	},
+};
+
+void board_init(void)
+{
+	int on;
+
+	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_INT_ODL);
+
+	/*
+	 * If interrupt lines are already low, schedule them to be processed
+	 * after inits are completed.
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL))
+		hook_call_deferred(&check_c0_line_data, 0);
+	if (!gpio_get_level(GPIO_USB_C1_INT_ODL))
+		hook_call_deferred(&check_c1_line_data, 0);
+
+	gpio_enable_interrupt(GPIO_USB_C0_CCSBU_OVP_ODL);
+	/* Enable Base Accel interrupt */
+	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
+
+	/* Turn on 5V if the system is on, otherwise turn it off */
+	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
+			      CHIPSET_STATE_SOFT_OFF);
+	board_power_5v_enable(on);
+
+	if (get_cbi_fw_config_numeric_pad() == NUMERIC_PAD_ABSENT) {
+		keyboard_raw_set_cols(KEYBOARD_COLS_NO_KEYPAD);
+	} else {
+		/* Setting scan mask KSO11, KSO12, KSO13 and KSO14 */
+		keyscan_config.actual_key_mask[11] = 0xfe;
+		keyscan_config.actual_key_mask[12] = 0xff;
+		keyscan_config.actual_key_mask[13] = 0xff;
+		keyscan_config.actual_key_mask[14] = 0xff;
+	}
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+void board_hibernate(void)
+{
+	/*
+	 * Put all charger ICs present into low power mode before entering
+	 * z-state.
+	 */
+	raa489000_hibernate(CHARGER_PRIMARY, true);
+	if (board_get_charger_chip_count() > 1)
+		raa489000_hibernate(CHARGER_SECONDARY, true);
+}
+
+__override void board_ocpc_init(struct ocpc_data *ocpc)
+{
+	/* There's no provision to measure Isys */
+	ocpc->chg_flags[CHARGER_SECONDARY] |= OCPC_NO_ISYS_MEAS_CAP;
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * Nothing to do.  TCPC C0 is internal, TCPC C1 reset pin is not
+	 * connected to the EC.
+	 */
+}
+
+__override void board_power_5v_enable(int enable)
+{
+	/*
+	 * Motherboard has a GPIO to turn on the 5V regulator, but the sub-board
+	 * sets it through the charger GPIO.
+	 */
+	gpio_set_level(GPIO_EN_PP5000, !!enable);
+	gpio_set_level(GPIO_EN_USB_A0_VBUS, !!enable);
+	if (isl923x_set_comparator_inversion(1, !!enable))
+		CPRINTS("Failed to %sable sub rails!", enable ? "en" : "dis");
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+	int regval;
+
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
+			if (regval)
+				status = PD_STATUS_TCPC_ALERT_0;
+		}
+	}
+
+	/* Check whether TCPC 1 pulled the shared interrupt line */
+	if (!gpio_get_level(GPIO_USB_C1_INT_ODL)) {
+		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
+			if (regval)
+				status = PD_STATUS_TCPC_ALERT_1;
+		}
+	}
+
+	return status;
+}
+
+int board_is_sourcing_vbus(int port)
+{
+	int regval;
+
+	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
+	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count());
+	int i;
+	int old_port;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	old_port = charge_manager_get_active_charge_port();
+
+	CPRINTS("New chg p%d", port);
+
+	/* Disable all ports. */
+	if (port == CHARGE_PORT_NONE) {
+		for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+			tcpc_write(i, TCPC_REG_COMMAND,
+				   TCPC_REG_COMMAND_SNK_CTRL_LOW);
+			raa489000_enable_asgate(i, false);
+		}
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if port is sourcing VBUS. */
+	if (board_is_sourcing_vbus(port)) {
+		CPRINTS("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * Turn off the other ports sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+		if (port == i)
+			continue;
+
+		if (tcpc_write(i, TCPC_REG_COMMAND,
+			       TCPC_REG_COMMAND_SNK_CTRL_LOW))
+			CPRINTS("p%d: sink path disable failed.", i);
+		raa489000_enable_asgate(i, false);
+	}
+
+	/*
+	 * Stop the charger IC from switching while changing ports.  Otherwise,
+	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
+	 */
+	if (old_port != CHARGE_PORT_NONE)
+		charger_discharge_on_ac(1);
+
+	/* Enable requested charge port. */
+	if (raa489000_enable_asgate(port, true) ||
+	    tcpc_write(port, TCPC_REG_COMMAND,
+		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
+		CPRINTS("p%d: sink path enable failed.", port);
+		charger_discharge_on_ac(0);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	/* Allow the charger IC to begin/continue switching. */
+	charger_discharge_on_ac(0);
+
+	return EC_SUCCESS;
+}
+
+__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+				       int *ki_div, int *kd, int *kd_div)
+{
+	*kp = 1;
+	*kp_div = 20;
+	*ki = 1;
+	*ki_div = 250;
+	*kd = 0;
+	*kd_div = 1;
+}
+
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	if (!board_is_usb_pd_port_present(port))
+		return;
+
+	raa489000_set_output_current(port, rp);
+}
+
+/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_KBLIGHT] = {
+		.channel = 0,
+		.flags = PWM_CONFIG_DSLEEP,
+		.freq_hz = 10000,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+/* Sensor Mutexes */
+static struct mutex g_lid_mutex;
+static struct mutex g_base_mutex;
+
+/* Sensor Data */
+static struct kionix_accel_data g_kx022_data;
+static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
+
+/* Drivers */
+struct motion_sensor_t motion_sensors[] = {
+	[LID_ACCEL] = {
+		.name = "Lid Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_KX022,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &kionix_accel_drv,
+		.mutex = &g_lid_mutex,
+		.drv_data = &g_kx022_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
+		.rot_standard_ref = NULL,
+		.default_range = 2, /* g */
+		/* We only use 2g because its resolution is only 8-bits */
+		.min_frequency = KX022_ACCEL_MIN_FREQ,
+		.max_frequency = KX022_ACCEL_MAX_FREQ,
+		.config = {
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+		},
+	},
+	[BASE_ACCEL] = {
+		.name = "Base Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LSM6DSM,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &lsm6dsm_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
+				MOTIONSENSE_TYPE_ACCEL),
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
+		.rot_standard_ref = NULL,
+		.default_range = 4,  /* g */
+		.min_frequency = LSM6DSM_ODR_MIN_VAL,
+		.max_frequency = LSM6DSM_ODR_MAX_VAL,
+		.config = {
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 13000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+		},
+	},
+	[BASE_GYRO] = {
+		.name = "Base Gyro",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LSM6DSM,
+		.type = MOTIONSENSE_TYPE_GYRO,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &lsm6dsm_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
+				MOTIONSENSE_TYPE_GYRO),
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
+		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
+		.rot_standard_ref = NULL,
+		.min_frequency = LSM6DSM_ODR_MIN_VAL,
+		.max_frequency = LSM6DSM_ODR_MAX_VAL,
+	},
+};
+
+const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+/* Thermistors */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1] = { .name = "Charger",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Vcore",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CHARGER          \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(68), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(90), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(50), \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_charger =
+	THERMAL_CHARGER;
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_VCORE            \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(53), \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_vcore =
+	THERMAL_VCORE;
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_AMBIENT          \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(50), \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_ambient =
+	THERMAL_AMBIENT;
+
+struct ec_thermal_config thermal_params[] = {
+	[TEMP_SENSOR_1] = THERMAL_CHARGER,
+	[TEMP_SENSOR_2] = THERMAL_VCORE,
+	[TEMP_SENSOR_3] = THERMAL_AMBIENT,
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
+
+/* This callback disables keyboard when convertibles are fully open */
+__override void lid_angle_peripheral_enable(int enable)
+{
+	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
+
+	/*
+	 * If the lid is in tablet position via other sensors,
+	 * ignore the lid angle, which might be faulty then
+	 * disable keyboard.
+	 */
+	if (tablet_get_mode())
+		enable = 0;
+
+	if (enable) {
+		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
+	} else {
+		/*
+		 * Ensure that the chipset is off before disabling the keyboard.
+		 * When the chipset is on, the EC keeps the keyboard enabled and
+		 * the AP decides whether to ignore input devices or not.
+		 */
+		if (!chipset_in_s0)
+			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
+	}
+}
+
+__override void board_pulse_entering_rw(void)
+{
+	/*
+	 * On the ITE variants, the EC_ENTERING_RW signal was connected to a pin
+	 * which is active high by default. This cause Cr50 to think that the
+	 * EC has jumped to its RW image even though this may not be the case.
+	 * The pin is changed to GPIO_EC_ENTERING_RW2.
+	 */
+	gpio_set_level(GPIO_EC_ENTERING_RW, 1);
+	gpio_set_level(GPIO_EC_ENTERING_RW2, 1);
+	usleep(MSEC);
+	gpio_set_level(GPIO_EC_ENTERING_RW, 0);
+	gpio_set_level(GPIO_EC_ENTERING_RW2, 0);
+}
diff --git a/board/pirika/board.h b/board/pirika/board.h
new file mode 100644
index 0000000000..c8e2f3eb35
--- /dev/null
+++ b/board/pirika/board.h
@@ -0,0 +1,143 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Waddledee board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* Select Baseboard features */
+#define VARIANT_DEDEDE_EC_IT8320
+#include "baseboard.h"
+
+/* System unlocked in early development */
+#undef CONFIG_SYSTEM_UNLOCKED
+
+#define CONFIG_CMD_TCPC_DUMP
+#define CONFIG_CMD_CHARGER_DUMP
+
+/* Battery */
+#define CONFIG_BATTERY_FUEL_GAUGE
+
+/* BC 1.2 */
+#define CONFIG_BC12_DETECT_PI3USB9201
+
+/* Charger */
+#define CONFIG_CHARGER_RAA489000 /* C0 and C1: Charger */
+#define PD_MAX_VOLTAGE_MV 20000
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#undef CONFIG_CHARGER_SINGLE_CHIP
+#define CONFIG_OCPC
+#define CONFIG_OCPC_DEF_RBATT_MOHMS               \
+	22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \
+	    */
+#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
+#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
+
+#define GPIO_USB_C1_INT_ODL GPIO_SUB_USB_C1_INT_ODL
+
+/* LED */
+#define CONFIG_LED_ONOFF_STATES
+#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
+
+/* PWM */
+#define CONFIG_PWM
+
+/* Sensors */
+#define CONFIG_ACCEL_KX022 /* Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
+#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+/* Sensors without hardware FIFO are in forced mode */
+#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
+
+/* Enable sensor fifo, must also define the _SIZE and _THRES */
+#define CONFIG_ACCEL_FIFO
+/* Power of 2 - Too large of a fifo causes too much timestamp jitter */
+#define CONFIG_ACCEL_FIFO_SIZE 256
+#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
+
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_UPDATE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+
+#define CONFIG_TABLET_MODE
+#define CONFIG_TABLET_MODE_SWITCH
+#define CONFIG_GMR_TABLET_MODE
+
+/* TCPC */
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#define CONFIG_USB_PD_TCPM_RAA489000
+#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+#define CONFIG_USB_PD_VBUS_DETECT_TCPC
+#define CONFIG_USB_PD_DISCHARGE_TCPC
+#define CONFIG_USB_PD_TCPC_LOW_POWER
+#define CONFIG_USB_PD_5V_EN_CUSTOM
+
+/* Thermistors */
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_THERMISTOR
+#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
+#define CONFIG_THROTTLE_AP
+#define CONFIG_CHIPSET_CAN_THROTTLE
+
+/* USB Mux and Retimer */
+#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */
+
+#define CONFIG_USBC_RETIMER_TUSB544 /* C1 Redriver: TUSB544 */
+
+/* Keyboard */
+#define CONFIG_KEYBOARD_VIVALDI
+#define CONFIG_KEYBOARD_REFRESH_ROW3
+#define CONFIG_KEYBOARD_KEYPAD
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum chg_id {
+	CHARGER_PRIMARY,
+	CHARGER_SECONDARY,
+	CHARGER_NUM,
+};
+
+enum pwm_channel {
+	PWM_CH_KBLIGHT,
+	PWM_CH_COUNT,
+};
+
+/* Motion sensors */
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
+
+/* ADC channels */
+enum adc_channel {
+	ADC_VSNS_PP3300_A, /* ADC0 */
+	ADC_TEMP_SENSOR_1, /* ADC2 */
+	ADC_TEMP_SENSOR_2, /* ADC3 */
+	ADC_TEMP_SENSOR_3, /* ADC15 */
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1,
+	TEMP_SENSOR_2,
+	TEMP_SENSOR_3,
+	TEMP_SENSOR_COUNT
+};
+
+/* List of possible batteries */
+enum battery_type {
+	BATTERY_CA14J43,
+	BATTERY_CA11J58,
+	BATTERY_TYPE_COUNT,
+};
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/pirika/build.mk b/board/pirika/build.mk
new file mode 100644
index 0000000000..01b890bf29
--- /dev/null
+++ b/board/pirika/build.mk
@@ -0,0 +1,15 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=it83xx
+CHIP_FAMILY:=it8320
+CHIP_VARIANT:=it8320dx
+BASEBOARD:=dedede
+
+board-y=board.o cbi_ssfc.o led.o usb_pd_policy.o
+board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/pirika/cbi_ssfc.c b/board/pirika/cbi_ssfc.c
new file mode 100644
index 0000000000..81f3ee0dad
--- /dev/null
+++ b/board/pirika/cbi_ssfc.c
@@ -0,0 +1,36 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi_ssfc.h"
+#include "common.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "hooks.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+/* Cache SSFC on init since we don't expect it to change in runtime */
+static union dedede_cbi_ssfc cached_ssfc;
+BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
+
+static void cbi_ssfc_init(void)
+{
+	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
+		/* Default to 0 when CBI isn't populated */
+		cached_ssfc.raw_value = 0;
+
+	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
+}
+DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
+
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
+{
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
+}
+
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
+{
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
+}
diff --git a/board/pirika/cbi_ssfc.h b/board/pirika/cbi_ssfc.h
new file mode 100644
index 0000000000..bf8853a43a
--- /dev/null
+++ b/board/pirika/cbi_ssfc.h
@@ -0,0 +1,59 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _DEDEDE_CBI_SSFC__H_
+#define _DEDEDE_CBI_SSFC__H_
+
+#include "stdint.h"
+
+/****************************************************************************
+ * Dedede CBI Second Source Factory Cache
+ */
+
+/*
+ * Base Sensor (Bits 0-2)
+ */
+enum ec_ssfc_base_sensor {
+	SSFC_SENSOR_BASE_DEFAULT = 0,
+	SSFC_SENSOR_BMI160 = 1,
+	SSFC_SENSOR_ICM426XX = 2,
+	SSFC_SENSOR_LSM6DSM = 3,
+	SSFC_SENSOR_ICM42607 = 4
+};
+
+/*
+ * Lid Sensor (Bits 3-5)
+ */
+enum ec_ssfc_lid_sensor {
+	SSFC_SENSOR_LID_DEFAULT = 0,
+	SSFC_SENSOR_BMA255 = 1,
+	SSFC_SENSOR_KX022 = 2,
+	SSFC_SENSOR_LIS2DWL = 3
+};
+
+union dedede_cbi_ssfc {
+	struct {
+		uint32_t base_sensor : 3;
+		uint32_t lid_sensor : 3;
+		uint32_t reserved_2 : 26;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Get the Base sensor type from SSFC_CONFIG.
+ *
+ * @return the Base sensor board type.
+ */
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
+
+/**
+ * Get the Lid sensor type from SSFC_CONFIG.
+ *
+ * @return the Lid sensor board type.
+ */
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
+
+#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/pirika/ec.tasklist b/board/pirika/ec.tasklist
new file mode 100644
index 0000000000..f7c32f66bf
--- /dev/null
+++ b/board/pirika/ec.tasklist
@@ -0,0 +1,25 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, TRENTA_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, ULTRA_TASK_STACK_SIZE) \
+        TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+        TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE) \
+        TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/pirika/gpio.inc b/board/pirika/gpio.inc
new file mode 100644
index 0000000000..5ec1003a70
--- /dev/null
+++ b/board/pirika/gpio.inc
@@ -0,0 +1,145 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+/* Power State interrupts */
+GPIO_INT(SLP_S4_L,		PIN(I, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,		PIN(H, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(SLP_S0_L,		PIN(E, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,		PIN(G, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID0,	PIN(D, 0), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(RSMRST_PWRGD_L,	PIN(E, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(CPU_C10_GATE_L,	PIN(G, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_DRAM_OD,		PIN(D, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(PG_PP1050_ST_OD,	PIN(L, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID1,	PIN(K, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_VCCIO_EXT_OD,	PIN(D, 7), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(ESPI_RESET_L, 	 PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt)
+
+GPIO_INT(H1_EC_PWR_BTN_ODL,	PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
+#ifdef CONFIG_LOW_POWER_IDLE
+/* Used to wake up the EC from Deep Doze mode when writing to console */
+GPIO_INT(UART1_RX,	 PIN(B, 0), GPIO_INT_BOTH, uart_deepsleep_interrupt)	/* UART_DBG_TX_EC_RX */
+#endif
+
+/* USB-C interrupts */
+GPIO_INT(USB_C0_INT_ODL,	PIN(K, 0), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt) /* BC12 and charger */
+GPIO_INT(SUB_USB_C1_INT_ODL,	PIN(E, 6), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c1_interrupt)
+GPIO_INT(USB_C0_CCSBU_OVP_ODL,	PIN(K, 6), GPIO_INT_FALLING | GPIO_PULL_UP, c0_ccsbu_ovp_interrupt) /* Fault protection */
+
+/* Other interrupts */
+GPIO_INT(LID_OPEN,		PIN(F, 3), GPIO_INT_BOTH, lid_interrupt)
+GPIO_INT(LID_360_L,		PIN(A, 7), GPIO_INT_BOTH, gmr_tablet_switch_isr)
+GPIO_INT(VOLDN_BTN_ODL,		PIN(I, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(VOLUP_BTN_ODL,		PIN(I, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(J, 0), GPIO_INT_FALLING | GPIO_SEL_1P8V, lsm6dsm_interrupt)
+GPIO_INT(EC_WP_OD,		PIN(A, 6), GPIO_INT_BOTH, switch_interrupt)
+
+/* Power sequence GPIOs */
+GPIO(EC_AP_RTCRST,		PIN(K, 2), GPIO_OUT_LOW)
+GPIO(EC_AP_PWR_BTN_ODL,		PIN(B, 6), GPIO_ODR_HIGH)
+GPIO(EC_AP_DPWROK,		PIN(L, 7), GPIO_OUT_LOW)
+GPIO(EC_AP_RSMRST_L,		PIN(H, 0), GPIO_OUT_LOW)
+GPIO(EC_AP_WAKE_ODL,		PIN(D, 5), GPIO_ODR_HIGH)
+GPIO(SYS_RST_ODL,		PIN(D, 1), GPIO_ODR_HIGH)
+GPIO(EC_AP_SYS_PWROK,		PIN(F, 2), GPIO_OUT_LOW)
+GPIO(PG_PP5000_U_OD,		PIN(E, 3), GPIO_INPUT)
+GPIO(EN_PP3300_A,		PIN(C, 5), GPIO_OUT_LOW)
+GPIO(EC_AP_PCH_PWROK_OD,	PIN(D, 6), GPIO_ODR_LOW)
+GPIO(EN_PP5000_U,		PIN(K, 5), GPIO_OUT_LOW)
+/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
+GPIO(EN_VCCST,			PIN(D, 4), GPIO_INPUT)
+GPIO(EN_VCCIO_EXT,		PIN(B, 2), GPIO_OUT_LOW)
+GPIO(EC_PROCHOT_ODL,		PIN(I, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(EC_AP_VCCST_PWRGD_OD,	PIN(E, 5), GPIO_ODR_LOW)
+GPIO(ALL_SYS_PWRGD,		PIN(B, 7), GPIO_OUT_LOW)
+GPIO(EN_SLP_Z,			PIN(K, 3), GPIO_OUT_LOW)
+
+/* Required for icelake chipset code, but implemented through other means for dedede */
+UNIMPLEMENTED(AC_PRESENT)
+UNIMPLEMENTED(PG_EC_DSW_PWROK)
+UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
+
+/* I2C pins - Alternate function below configures I2C module on these pins */
+GPIO(EC_I2C_EEPROM_SCL,		PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SDA,		PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SCL,	PIN(C, 1), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SDA,	PIN(C, 2), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,		PIN(F, 6), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SENSOR_SDA,		PIN(F, 7), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SUB_USB_C1_SCL,	PIN(E, 0), GPIO_INPUT)
+GPIO(EC_I2C_SUB_USB_C1_SDA,	PIN(E, 7), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SCL,		PIN(A, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SDA,		PIN(A, 5), GPIO_INPUT)
+
+/* USB pins */
+GPIO(EC_AP_USB_C0_HPD,		PIN(L, 4), GPIO_OUT_LOW)
+GPIO(EC_AP_USB_C1_HDMI_HPD,	PIN(K, 7), GPIO_OUT_LOW)
+GPIO(EN_USB_A0_VBUS,		PIN(L, 6), GPIO_OUT_LOW) /* Board rev 1, NC board rev 0 */
+
+/* MKBP event synchronization */
+GPIO(EC_AP_MKBP_INT_L,	PIN(L, 5), GPIO_ODR_HIGH)
+
+/* Misc pins which will run to the I/O board */
+
+/* Misc */
+GPIO(EN_BL_OD,			PIN(K, 4), GPIO_ODR_LOW)
+GPIO(EC_ENTERING_RW,		PIN(G, 0), GPIO_OUT_LOW)
+GPIO(EC_ENTERING_RW2,		PIN(C, 7), GPIO_OUT_LOW)
+GPIO(CCD_MODE_ODL,		PIN(H, 5), GPIO_ODR_HIGH)
+GPIO(EC_BATTERY_PRES_ODL,	PIN(I, 4), GPIO_INPUT)
+GPIO(ECH1_PACKET_MODE,		PIN(H, 1), GPIO_OUT_LOW)
+
+/* LED */
+GPIO(LED_R_ODL,                 PIN(A, 1), GPIO_OUT_HIGH)
+GPIO(LED_G_ODL,                 PIN(A, 2), GPIO_OUT_HIGH)
+
+/* NC pins, enable internal pull-down to avoid floating state. */
+GPIO(GPIOA0_NC, PIN(A, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOA3_NC, PIN(A, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOB5_NC, PIN(B, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOC3_NC, PIN(C, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOC4_NC, PIN(C, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOC6_NC, PIN(C, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOF0_NC, PIN(F, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOF1_NC, PIN(F, 1), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOF4_NC, PIN(F, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOF5_NC, PIN(F, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG3_NC, PIN(G, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG4_NC, PIN(G, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG5_NC, PIN(G, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG6_NC, PIN(G, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG7_NC, PIN(G, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOH4_NC, PIN(H, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOH6_NC, PIN(H, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ1_NC, PIN(J, 1), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ3_NC, PIN(J, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ4_NC, PIN(J, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ5_NC, PIN(J, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ6_NC, PIN(J, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOL0_NC, PIN(L, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOL3_NC, PIN(L, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOM6_NC, PIN(M, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+
+/* Alternate functions GPIO definitions */
+/* UART */
+ALTERNATE(PIN_MASK(B, BIT(0) | BIT(1)), 0, MODULE_UART, 0)		/* UART for debug */
+
+/* I2C */
+ALTERNATE(PIN_MASK(B, BIT(3) | BIT(4)), 0, MODULE_I2C, 0)		/* I2C0 */
+ALTERNATE(PIN_MASK(C, BIT(1) | BIT(2)), 0, MODULE_I2C, 0)		/* I2C1 */
+ALTERNATE(PIN_MASK(F, BIT(6) | BIT(7)), 0, MODULE_I2C, GPIO_SEL_1P8V)	/* I2C2 - 1.8V */
+ALTERNATE(PIN_MASK(E, BIT(0) | BIT(7)), 0, MODULE_I2C, 0)		/* I2C4 */
+ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), 0, MODULE_I2C, 0)		/* I2C5 */
+
+/* ADC */
+ALTERNATE(PIN_MASK(L, BIT(2)), 0, MODULE_ADC, 0)		/* ADC15: TEMP_SENSOR_3 */
+ALTERNATE(PIN_MASK(I, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0)	/* ADC0: EC_VSNS_PP3300_A, ADC2: TEMP_SENSOR_1, ADC3: TEMP_SENSOR_2 */
+
diff --git a/board/pirika/led.c b/board/pirika/led.c
new file mode 100644
index 0000000000..916f691dd6
--- /dev/null
+++ b/board/pirika/led.c
@@ -0,0 +1,106 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "chipset.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
+
+__override const int led_charge_lvl_1;
+__override const int led_charge_lvl_2 = 95;
+
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { LED_OFF, 2 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_BATTERY_LED,
+};
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_WHITE:
+		gpio_set_level(GPIO_LED_R_ODL, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_G_ODL, LED_ON_LVL);
+		break;
+	case EC_LED_COLOR_AMBER:
+		gpio_set_level(GPIO_LED_R_ODL, LED_ON_LVL);
+		gpio_set_level(GPIO_LED_G_ODL, LED_OFF_LVL);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		gpio_set_level(GPIO_LED_R_ODL, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_G_ODL, LED_OFF_LVL);
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_battery(EC_LED_COLOR_WHITE);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(EC_LED_COLOR_AMBER);
+		else
+			led_set_color_battery(LED_OFF);
+	}
+	return EC_SUCCESS;
+}
+
+__override enum led_states board_led_get_state(enum led_states desired_state)
+{
+	/* Battery error LED behavior as below:
+	 * S0: Blinking Amber LED, 1s on/ 1s off
+	 * S3/S5: following S3/S5 behavior
+	 * Add function to let battery error LED follow S3/S5 behavior in S3/S5.
+	 */
+
+	if (desired_state == STATE_BATTERY_ERROR) {
+		if (chipset_in_state(CHIPSET_STATE_ON))
+			return desired_state;
+		else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
+			return STATE_DISCHARGE_S3;
+		else
+			return STATE_DISCHARGE_S5;
+	}
+	return desired_state;
+}
diff --git a/board/pirika/usb_pd_policy.c b/board/pirika/usb_pd_policy.c
new file mode 100644
index 0000000000..83c09bb99e
--- /dev/null
+++ b/board/pirika/usb_pd_policy.c
@@ -0,0 +1,61 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "driver/charger/isl923x_public.h"
+#include "driver/tcpm/tcpci.h"
+#include "usb_pd.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+int pd_check_vconn_swap(int port)
+{
+	/* Allow VCONN swaps if the AP is on. */
+	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
+}
+
+void pd_power_supply_reset(int port)
+{
+	/* Disable VBUS */
+	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	if (port >= board_get_usb_pd_port_count())
+		return EC_ERROR_INVAL;
+
+	/* Disable charging. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
+	if (rv)
+		return rv;
+
+	/* Our policy is not to source VBUS when the AP is off. */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	/* Provide Vbus. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
+	if (rv)
+		return rv;
+
+	rv = raa489000_enable_asgate(port, true);
+	if (rv)
+		return rv;
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
diff --git a/board/pirika/vif_override.xml b/board/pirika/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/pirika/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/plankton/board.c b/board/plankton/board.c
index 551642fae0..160192e7ff 100644
--- a/board/plankton/board.c
+++ b/board/plankton/board.c
@@ -1,11 +1,10 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 /* Plankton board configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "common.h"
 #include "console.h"
 #include "gpio.h"
@@ -23,6 +22,7 @@
 void button_event(enum gpio_signal signal);
 void hpd_event(enum gpio_signal signal);
 void vbus_event(enum gpio_signal signal);
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 static volatile uint64_t hpd_prev_ts;
@@ -79,14 +79,12 @@ void hpd_lvl_deferred(void)
 		/* Configure redriver's back side */
 		if (level)
 			sn75dp130_dpcd_init();
-
 	}
 
 	/* Send queued IRQ if the cable is attached */
 	if (hpd_possible_irq && level && dp_mode)
 		pd_send_hpd(0, hpd_irq);
 	hpd_possible_irq = 0;
-
 }
 DECLARE_DEFERRED(hpd_lvl_deferred);
 
@@ -104,8 +102,7 @@ void hpd_event(enum gpio_signal signal)
 	hpd_prev_ts = now.val;
 
 	/* All previous hpd level events need to be re-triggered */
-	hook_call_deferred(&hpd_lvl_deferred_data,
-			   HPD_USTREAM_DEBOUNCE_LVL);
+	hook_call_deferred(&hpd_lvl_deferred_data, HPD_USTREAM_DEBOUNCE_LVL);
 }
 
 /* Debounce time for voltage buttons */
@@ -135,8 +132,7 @@ enum usbc_action {
 	USBC_ACT_COUNT
 };
 
-enum board_src_cap src_cap_mapping[USBC_ACT_COUNT] =
-{
+enum board_src_cap src_cap_mapping[USBC_ACT_COUNT] = {
 	[USBC_ACT_5V_TO_DUT] = SRC_CAP_5V,
 	[USBC_ACT_12V_TO_DUT] = SRC_CAP_12V,
 	[USBC_ACT_20V_TO_DUT] = SRC_CAP_20V,
@@ -156,21 +152,21 @@ static void set_active_cc(int cc)
 	 * disabled then only set the active CC line.
 	 */
 	/* Pull-up on CC2 */
-	gpio_set_flags(GPIO_USBC_CC2_HOST,
-		       ((cc || drp_enable) && host_mode) ?
-		       GPIO_OUT_HIGH : GPIO_INPUT);
+	gpio_set_flags(GPIO_USBC_CC2_HOST, ((cc || drp_enable) && host_mode) ?
+						   GPIO_OUT_HIGH :
+						   GPIO_INPUT);
 	/* Pull-down on CC2 */
 	gpio_set_flags(GPIO_USBC_CC2_DEVICE_ODL,
-		       ((cc || drp_enable) && !host_mode) ?
-		       GPIO_OUT_LOW : GPIO_INPUT);
+		       ((cc || drp_enable) && !host_mode) ? GPIO_OUT_LOW :
+							    GPIO_INPUT);
 	/* Pull-up on CC1 */
-	gpio_set_flags(GPIO_USBC_CC1_HOST,
-		       ((!cc || drp_enable) && host_mode) ?
-		       GPIO_OUT_HIGH : GPIO_INPUT);
+	gpio_set_flags(GPIO_USBC_CC1_HOST, ((!cc || drp_enable) && host_mode) ?
+						   GPIO_OUT_HIGH :
+						   GPIO_INPUT);
 	/* Pull-down on CC1 */
 	gpio_set_flags(GPIO_USBC_CC1_DEVICE_ODL,
-		       ((!cc || drp_enable) && !host_mode) ?
-		       GPIO_OUT_LOW : GPIO_INPUT);
+		       ((!cc || drp_enable) && !host_mode) ? GPIO_OUT_LOW :
+							     GPIO_INPUT);
 }
 
 /**
@@ -222,7 +218,7 @@ static void fake_disconnect_end(void)
 	board_pd_set_host_mode(fake_pd_host_mode);
 
 	/* Restart CC cable detection */
-	hook_call_deferred(&detect_cc_cable_data, 500*MSEC);
+	hook_call_deferred(&detect_cc_cable_data, 500 * MSEC);
 }
 DECLARE_DEFERRED(fake_disconnect_end);
 
@@ -362,10 +358,10 @@ static void set_usbc_action(enum usbc_action act)
 		gpio_set_level(GPIO_CASE_CLOSE_EN, 1);
 		gpio_set_level(GPIO_CASE_CLOSE_DFU_L, 1);
 		break;
-	case  USBC_ACT_DRP_TOGGLE:
+	case USBC_ACT_DRP_TOGGLE:
 		/* Toggle dualrole mode setting. */
-		update_usbc_dual_role(drp_enable ?
-				      PD_DRP_TOGGLE_OFF : PD_DRP_TOGGLE_ON);
+		update_usbc_dual_role(drp_enable ? PD_DRP_TOGGLE_OFF :
+						   PD_DRP_TOGGLE_ON);
 		break;
 	default:
 		break;
@@ -425,8 +421,8 @@ static void button_deferred(void)
 		break;
 	}
 
-	ccprintf("Button %d = %d\n",
-		 button_pressed, gpio_get_level(button_pressed));
+	ccprintf("Button %d = %d\n", button_pressed,
+		 gpio_get_level(button_pressed));
 }
 DECLARE_DEFERRED(button_deferred);
 
@@ -454,15 +450,18 @@ void vbus_event(enum gpio_signal signal)
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* USB PD CC lines sensing. Converted to mV (3300mV/4096). */
-	[ADC_CH_CC1_PD] = {"CC1_PD", 3300, 4096, 0, STM32_AIN(0)},
-	[ADC_CH_CC2_PD] = {"CC2_PD", 3300, 4096, 0, STM32_AIN(4)},
+	[ADC_CH_CC1_PD] = { "CC1_PD", 3300, 4096, 0, STM32_AIN(0) },
+	[ADC_CH_CC2_PD] = { "CC2_PD", 3300, 4096, 0, STM32_AIN(4) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{"master",  I2C_PORT_MASTER, 100,
-		GPIO_MASTER_I2C_SCL, GPIO_MASTER_I2C_SDA},
+	{ .name = "master",
+	  .port = I2C_PORT_MASTER,
+	  .kbps = 100,
+	  .scl = GPIO_MASTER_I2C_SCL,
+	  .sda = GPIO_MASTER_I2C_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -472,12 +471,12 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
  * Pin number for active-high reset from PCA9534 to CMOS pull-down to
  * SN75DP130's RSTN (active-low)
  */
-#define REDRIVER_RST_PIN  0x1
+#define REDRIVER_RST_PIN 0x1
 
 static int sn75dp130_i2c_write(uint8_t index, uint8_t value)
 {
-	return i2c_write8(I2C_PORT_MASTER, SN75DP130_I2C_ADDR_FLAGS,
-			  index, value);
+	return i2c_write8(I2C_PORT_MASTER, SN75DP130_I2C_ADDR_FLAGS, index,
+			  value);
 }
 
 /**
@@ -490,17 +489,15 @@ static int sn75dp130_reset(void)
 {
 	int rv;
 
-	rv = pca9534_config_pin(I2C_PORT_MASTER, 0x20,
-				REDRIVER_RST_PIN, PCA9534_OUTPUT);
+	rv = pca9534_config_pin(I2C_PORT_MASTER, 0x20, REDRIVER_RST_PIN,
+				PCA9534_OUTPUT);
 	/* Assert (its active high) */
-	rv |= pca9534_set_level(I2C_PORT_MASTER, 0x20,
-				REDRIVER_RST_PIN, 1);
+	rv |= pca9534_set_level(I2C_PORT_MASTER, 0x20, REDRIVER_RST_PIN, 1);
 	/* datasheet recommends > 100usec */
 	usleep(200);
 
 	/* De-assert */
-	rv |= pca9534_set_level(I2C_PORT_MASTER, 0x20,
-				REDRIVER_RST_PIN, 0);
+	rv |= pca9534_set_level(I2C_PORT_MASTER, 0x20, REDRIVER_RST_PIN, 0);
 	/* datasheet recommends > 400msec */
 	usleep(450 * MSEC);
 	return rv;
@@ -551,7 +548,7 @@ static int sn75dp130_redriver_init(void)
 	return rv;
 }
 
-static int cmd_usbc_action(int argc, char *argv[])
+static int cmd_usbc_action(int argc, const char *argv[])
 {
 	enum usbc_action act;
 
@@ -596,12 +593,10 @@ int board_in_hub_mode(void)
 	int ret;
 	int level;
 
-	ret = pca9534_config_pin(I2C_PORT_MASTER, 0x20,
-				 6, PCA9534_INPUT);
+	ret = pca9534_config_pin(I2C_PORT_MASTER, 0x20, 6, PCA9534_INPUT);
 	if (ret)
 		return -1;
-	ret = pca9534_get_level(I2C_PORT_MASTER, 0x20,
-				6, &level);
+	ret = pca9534_get_level(I2C_PORT_MASTER, 0x20, 6, &level);
 	if (ret)
 		return -1;
 	return level;
@@ -611,17 +606,14 @@ static int board_usb_hub_reset(void)
 {
 	int ret;
 
-	ret = pca9534_config_pin(I2C_PORT_MASTER, 0x20,
-				 7, PCA9534_OUTPUT);
+	ret = pca9534_config_pin(I2C_PORT_MASTER, 0x20, 7, PCA9534_OUTPUT);
 	if (ret)
 		return ret;
-	ret = pca9534_set_level(I2C_PORT_MASTER, 0x20,
-				7, 0);
+	ret = pca9534_set_level(I2C_PORT_MASTER, 0x20, 7, 0);
 	if (ret)
 		return ret;
 	usleep(100 * MSEC);
-	return pca9534_set_level(I2C_PORT_MASTER, 0x20,
-				 7, 1);
+	return pca9534_set_level(I2C_PORT_MASTER, 0x20, 7, 1);
 }
 
 void board_maybe_reset_usb_hub(void)
@@ -630,12 +622,11 @@ void board_maybe_reset_usb_hub(void)
 		board_usb_hub_reset();
 }
 
-static int cmd_usb_hub_reset(int argc, char *argv[])
+static int cmd_usb_hub_reset(int argc, const char *argv[])
 {
 	return board_usb_hub_reset();
 }
-DECLARE_CONSOLE_COMMAND(hub_reset, cmd_usb_hub_reset,
-			NULL, "Reset USB hub");
+DECLARE_CONSOLE_COMMAND(hub_reset, cmd_usb_hub_reset, NULL, "Reset USB hub");
 
 static void board_usb_hub_reset_no_return(void)
 {
@@ -664,7 +655,7 @@ int board_fake_pd_adc_read(int cc)
 			 * on other CC line. */
 			if (active_cc == cc)
 				return adc_read_channel(cc ? ADC_CH_CC2_PD :
-							ADC_CH_CC1_PD);
+							     ADC_CH_CC1_PD);
 			else
 				return host_mode ? 3000 : 0;
 		}
@@ -750,7 +741,7 @@ static void board_init(void)
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
-static int cmd_fake_disconnect(int argc, char *argv[])
+static int cmd_fake_disconnect(int argc, const char *argv[])
 {
 	int delay_ms, duration_ms;
 	char *e;
@@ -772,8 +763,8 @@ static int cmd_fake_disconnect(int argc, char *argv[])
 	fake_pd_disconnect_duration_us = duration_ms * MSEC;
 	hook_call_deferred(&fake_disconnect_start_data, delay_ms * MSEC);
 
-	ccprintf("Fake disconnect for %d ms starting in %d ms.\n",
-		 duration_ms, delay_ms);
+	ccprintf("Fake disconnect for %d ms starting in %d ms.\n", duration_ms,
+		 delay_ms);
 
 	return EC_SUCCESS;
 }
@@ -787,7 +778,7 @@ static void trigger_dfu_release(void)
 }
 DECLARE_DEFERRED(trigger_dfu_release);
 
-static int cmd_trigger_dfu(int argc, char *argv[])
+static int cmd_trigger_dfu(int argc, const char *argv[])
 {
 	gpio_set_level(GPIO_CASE_CLOSE_DFU_L, 0);
 	ccprintf("Asserting CASE_CLOSE_DFU_L.\n");
diff --git a/board/plankton/board.h b/board/plankton/board.h
index 5e2f5f28a0..a17bd30c3c 100644
--- a/board/plankton/board.h
+++ b/board/plankton/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,6 @@
 #define CONFIG_UART_CONSOLE 2
 
 /* Optional features */
-#define CONFIG_STM_HWTIMER32
 #define CONFIG_USB_POWER_DELIVERY
 #define CONFIG_USB_PD_TCPMV1
 #define CONFIG_USB_PD_ALT_MODE
@@ -34,7 +33,7 @@
 #define CONFIG_ADC
 #define CONFIG_HW_CRC
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_CONTROLLER
 #define CONFIG_INA219
 #define CONFIG_IO_EXPANDER_PCA9534
 #undef CONFIG_WATCHDOG_HELP
@@ -58,7 +57,7 @@
 
 /* Timer selection */
 #define TIM_CLOCK32 2
-#define TIM_ADC     3
+#define TIM_ADC 3
 
 #include "gpio_signal.h"
 
@@ -77,18 +76,18 @@ enum board_src_cap {
 };
 
 /* 3.0A Rp */
-#define PD_SRC_VNC            PD_SRC_3_0_VNC_MV
-#define PD_SNK_RD_THRESHOLD   PD_SRC_3_0_RD_THRESH_MV
+#define PD_SRC_VNC PD_SRC_3_0_VNC_MV
+#define PD_SNK_RD_THRESHOLD PD_SRC_3_0_RD_THRESH_MV
 
 /* delay necessary for the voltage transition on the power supply */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  50000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 50000 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 50000 /* us */
 
 /* Define typical operating power and max power */
 #define PD_OPERATING_POWER_MW 5000
-#define PD_MAX_POWER_MW       60000
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_VOLTAGE_MV     20000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Set USB PD source capability */
 void board_set_source_cap(enum board_src_cap cap);
diff --git a/board/plankton/build.mk b/board/plankton/build.mk
index 89a01e629b..0e597a478f 100644
--- a/board/plankton/build.mk
+++ b/board/plankton/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
+# Copyright 2014 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -11,4 +11,4 @@ CHIP_FAMILY:=stm32f0
 CHIP_VARIANT:=stm32f07x
 
 board-y=board.o
-board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
+board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o usb_pd_pdo.o
diff --git a/board/plankton/ec.tasklist b/board/plankton/ec.tasklist
index 41fc047d6a..5a82344122 100644
--- a/board/plankton/ec.tasklist
+++ b/board/plankton/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/plankton/gpio.inc b/board/plankton/gpio.inc
index 9c618dbaa6..edccec814c 100644
--- a/board/plankton/gpio.inc
+++ b/board/plankton/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
+ * Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/plankton/usb_pd_config.h b/board/plankton/usb_pd_config.h
index fca6484069..47614c3fce 100644
--- a/board/plankton/usb_pd_config.h
+++ b/board/plankton/usb_pd_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -50,7 +50,7 @@ static inline void spi_enable_clock(int port)
 
 #define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
 #define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
-#define TIM_CCR_CS  1
+#define TIM_CCR_CS 1
 #define EXTI_COMP_MASK(p) BIT(21)
 #define IRQ_COMP STM32_IRQ_COMP
 /* triggers packet detection on comparator falling edge */
@@ -92,9 +92,8 @@ static inline void pd_tx_disable(int port, int polarity)
 {
 	/* output low on SPI TX to disable the FET */
 	/* PA6 is SPI1_MISO */
-	STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
-				   & ~(3 << (2*6)))
-				   |  (1 << (2*6));
+	STM32_GPIO_MODER(GPIO_A) =
+		(STM32_GPIO_MODER(GPIO_A) & ~(3 << (2 * 6))) | (1 << (2 * 6));
 	/* put the low level reference in Hi-Z */
 	gpio_set_level(GPIO_USBC_CC1_TX_EN, 0);
 	gpio_set_level(GPIO_USBC_CC2_TX_EN, 0);
@@ -104,11 +103,10 @@ static inline void pd_tx_disable(int port, int polarity)
 static inline void pd_select_polarity(int port, int polarity)
 {
 	/* use the right comparator non inverted input for COMP1 */
-	STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK)
-			| STM32_COMP_CMP1EN
-			| (polarity ?
-			   STM32_COMP_CMP1INSEL_INM4 :
-			   STM32_COMP_CMP1INSEL_INM6);
+	STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK) |
+			 STM32_COMP_CMP1EN |
+			 (polarity ? STM32_COMP_CMP1INSEL_INM4 :
+				     STM32_COMP_CMP1INSEL_INM6);
 	gpio_set_level(GPIO_USBC_POLARITY, polarity);
 }
 
diff --git a/board/plankton/usb_pd_pdo.c b/board/plankton/usb_pd_pdo.c
new file mode 100644
index 0000000000..52dcc11352
--- /dev/null
+++ b/board/plankton/usb_pd_pdo.c
@@ -0,0 +1,45 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "compile_time_macros.h"
+#include "usb_pd.h"
+#include "usb_pd_pdo.h"
+
+#define PDO_FIXED_FLAGS \
+	(PDO_FIXED_DATA_SWAP | PDO_FIXED_UNCONSTRAINED | PDO_FIXED_COMM_CAP)
+
+/* Source PDOs */
+const uint32_t pd_src_pdo[] = {
+	PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS),
+	PDO_FIXED(12000, 3000, PDO_FIXED_FLAGS),
+	PDO_FIXED(20000, 3000, PDO_FIXED_FLAGS),
+};
+
+/* Fake PDOs : we just want our pre-defined voltages */
+const uint32_t pd_snk_pdo[] = {
+	PDO_FIXED(5000, 500, PDO_FIXED_FLAGS),
+	PDO_FIXED(12000, 500, PDO_FIXED_FLAGS),
+	PDO_FIXED(20000, 500, PDO_FIXED_FLAGS),
+};
+const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
+
+static const int pd_src_pdo_cnts[] = {
+	[SRC_CAP_5V] = 1,
+	[SRC_CAP_12V] = 2,
+	[SRC_CAP_20V] = 3,
+};
+
+static int pd_src_pdo_idx;
+
+void board_set_source_cap(enum board_src_cap cap)
+{
+	pd_src_pdo_idx = cap;
+}
+
+int charge_manager_get_source_pdo(const uint32_t **src_pdo, const int port)
+{
+	*src_pdo = pd_src_pdo;
+	return pd_src_pdo_cnts[pd_src_pdo_idx];
+}
diff --git a/board/plankton/usb_pd_pdo.h b/board/plankton/usb_pd_pdo.h
new file mode 100644
index 0000000000..030dab9287
--- /dev/null
+++ b/board/plankton/usb_pd_pdo.h
@@ -0,0 +1,19 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_BOARD_PLANKTON_USB_PD_PDO_H
+#define __CROS_EC_BOARD_PLANKTON_USB_PD_PDO_H
+
+#include "stdint.h"
+
+extern const uint32_t pd_src_pdo[3];
+
+extern const uint32_t pd_snk_pdo[3];
+extern const int pd_snk_pdo_cnt;
+
+void board_set_source_cap(enum board_src_cap cap);
+int charge_manager_get_source_pdo(const uint32_t **src_pdo, const int port);
+
+#endif /* __CROS_EC_BOARD_PLANKTON_USB_PD_PDO_H */
diff --git a/board/plankton/usb_pd_policy.c b/board/plankton/usb_pd_policy.c
index f6701ab65e..622489c744 100644
--- a/board/plankton/usb_pd_policy.c
+++ b/board/plankton/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,60 +7,26 @@
 #include "board.h"
 #include "common.h"
 #include "console.h"
+#include "cros_version.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "registers.h"
 #include "task.h"
 #include "timer.h"
-#include "util.h"
 #include "usb_pd.h"
-#include "version.h"
+#include "usb_pd_pdo.h"
+#include "usb_pd_tcpm.h"
+#include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 /* Acceptable margin between requested VBUS and measured value */
 #define MARGIN_MV 400 /* mV */
 
-#define PDO_FIXED_FLAGS (PDO_FIXED_DATA_SWAP | PDO_FIXED_UNCONSTRAINED |\
-			 PDO_FIXED_COMM_CAP)
-
-/* Source PDOs */
-const uint32_t pd_src_pdo[] = {
-		PDO_FIXED(5000,  3000, PDO_FIXED_FLAGS),
-		PDO_FIXED(12000, 3000, PDO_FIXED_FLAGS),
-		PDO_FIXED(20000, 3000, PDO_FIXED_FLAGS),
-};
-static const int pd_src_pdo_cnts[] = {
-		[SRC_CAP_5V] = 1,
-		[SRC_CAP_12V] = 2,
-		[SRC_CAP_20V] = 3,
-};
-
-static int pd_src_pdo_idx;
-
-/* Fake PDOs : we just want our pre-defined voltages */
-const uint32_t pd_snk_pdo[] = {
-		PDO_FIXED(5000,   500, PDO_FIXED_FLAGS),
-		PDO_FIXED(12000,  500, PDO_FIXED_FLAGS),
-		PDO_FIXED(20000,  500, PDO_FIXED_FLAGS),
-};
-const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
-
 /* Whether alternate mode has been entered or not */
 static int alt_mode;
 
-void board_set_source_cap(enum board_src_cap cap)
-{
-	pd_src_pdo_idx = cap;
-}
-
-int charge_manager_get_source_pdo(const uint32_t **src_pdo, const int port)
-{
-	*src_pdo = pd_src_pdo;
-	return pd_src_pdo_cnts[pd_src_pdo_idx];
-}
-
 void pd_set_input_current_limit(int port, uint32_t max_ma,
 				uint32_t supply_voltage)
 {
@@ -110,22 +76,18 @@ __override int pd_check_power_swap(int port)
 	return 1;
 }
 
-__override int pd_check_data_swap(int port,
-				  enum pd_data_role data_role)
+__override int pd_check_data_swap(int port, enum pd_data_role data_role)
 {
 	/* Always allow data swap */
 	return 1;
 }
 
-__override void pd_check_pr_role(int port,
-				 enum pd_power_role pr_role,
+__override void pd_check_pr_role(int port, enum pd_power_role pr_role,
 				 int flags)
 {
 }
 
-__override void pd_check_dr_role(int port,
-				 enum pd_data_role dr_role,
-				 int flags)
+__override void pd_check_dr_role(int port, enum pd_data_role dr_role, int flags)
 {
 	/* If Plankton is in USB hub mode, always act as UFP */
 	if (board_in_hub_mode() && dr_role == PD_ROLE_DFP &&
@@ -143,8 +105,8 @@ const uint32_t vdo_idh = VDO_IDH(0, /* data caps as USB host */
 const uint32_t vdo_product = VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV);
 
 const uint32_t vdo_ama = VDO_AMA(CONFIG_USB_PD_IDENTITY_HW_VERS,
-				 CONFIG_USB_PD_IDENTITY_SW_VERS,
-				 0, 0, 0, 0, /* SS[TR][12] */
+				 CONFIG_USB_PD_IDENTITY_SW_VERS, 0, 0, 0,
+				 0, /* SS[TR][12] */
 				 0, /* Vconn power */
 				 0, /* Vconn power required */
 				 1, /* Vbus power required */
@@ -172,13 +134,13 @@ static int svdm_response_svids(int port, uint32_t *payload)
 #define MODE_CNT 1
 #define OPOS 1
 
-const uint32_t vdo_dp_mode[MODE_CNT] =  {
-	VDO_MODE_DP(0,		   /* UFP pin cfg supported : none */
+const uint32_t vdo_dp_mode[MODE_CNT] = {
+	VDO_MODE_DP(0, /* UFP pin cfg supported : none */
 		    MODE_DP_PIN_E, /* DFP pin cfg supported */
-		    1,		   /* no usb2.0	signalling in AMode */
-		    CABLE_PLUG,	   /* its a plug */
-		    MODE_DP_V13,   /* DPv1.3 Support, no Gen2 */
-		    MODE_DP_SNK)   /* Its a sink only */
+		    1, /* no usb2.0	signalling in AMode */
+		    CABLE_PLUG, /* its a plug */
+		    MODE_DP_V13, /* DPv1.3 Support, no Gen2 */
+		    MODE_DP_SNK) /* Its a sink only */
 };
 
 static int svdm_response_modes(int port, uint32_t *payload)
@@ -200,13 +162,13 @@ static int dp_status(int port, uint32_t *payload)
 	if (opos != OPOS)
 		return 0; /* nak */
 
-	payload[1] = VDO_DP_STATUS(0,                /* IRQ_HPD */
-				   (hpd == 1),       /* HPD_HI|LOW */
-				   0,		     /* request exit DP */
-				   0,		     /* request exit USB */
-				   0,		     /* MF pref */
+	payload[1] = VDO_DP_STATUS(0, /* IRQ_HPD */
+				   (hpd == 1), /* HPD_HI|LOW */
+				   0, /* request exit DP */
+				   0, /* request exit USB */
+				   0, /* MF pref */
 				   !gpio_get_level(GPIO_USBC_SS_USB_MODE),
-				   0,		     /* power low */
+				   0, /* power low */
 				   0x2);
 	return 2;
 }
@@ -236,7 +198,7 @@ int svdm_enter_mode(int port, uint32_t *payload)
 	return 1;
 }
 
-int pd_alt_mode(int port, enum tcpm_transmit_type type, uint16_t svid)
+int pd_alt_mode(int port, enum tcpci_msg_type type, uint16_t svid)
 {
 	return alt_mode;
 }
diff --git a/board/plankton/vif_override.xml b/board/plankton/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/plankton/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/polyberry/board.c b/board/polyberry/board.c
index 5bb811f82c..52d27e5a37 100644
--- a/board/polyberry/board.c
+++ b/board/polyberry/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,29 +8,31 @@
 #include "dma.h"
 #include "ec_version.h"
 #include "gpio.h"
-#include "gpio_list.h"
 #include "hooks.h"
 #include "registers.h"
 #include "stm32-dma.h"
 #include "task.h"
 #include "update_fw.h"
 #include "usb_descriptor.h"
-#include "util.h"
 #include "usb_dwc_console.h"
 #include "usb_dwc_update.h"
 #include "usb_hw.h"
+#include "util.h"
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
 
 /******************************************************************************
  * Define the strings used in our USB descriptors.
  */
 const void *const usb_strings[] = {
-	[USB_STR_DESC]		= usb_string_desc,
-	[USB_STR_VENDOR]	= USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]	= USB_STRING_DESC("Polyberry"),
-	[USB_STR_SERIALNO]	= USB_STRING_DESC("1234-a"),
-	[USB_STR_VERSION]	= USB_STRING_DESC(CROS_EC_VERSION32),
-	[USB_STR_CONSOLE_NAME]	= USB_STRING_DESC("Polyberry EC Shell"),
-	[USB_STR_UPDATE_NAME]	= USB_STRING_DESC("Firmware update"),
+	[USB_STR_DESC] = usb_string_desc,
+	[USB_STR_VENDOR] = USB_STRING_DESC("Google LLC"),
+	[USB_STR_PRODUCT] = USB_STRING_DESC("Polyberry"),
+	[USB_STR_SERIALNO] = USB_STRING_DESC("1234-a"),
+	[USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32),
+	[USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Polyberry EC Shell"),
+	[USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"),
 };
 
 BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
@@ -47,15 +49,15 @@ struct dwc_usb usb_ctl = {
 	.irq = STM32_IRQ_OTG_HS,
 };
 
-#define GPIO_SET_HS(bank, number)	\
-	(STM32_GPIO_OSPEEDR(GPIO_##bank) |= (0x3 << ((number) * 2)))
+#define GPIO_SET_HS(bank, number) \
+	(STM32_GPIO_OSPEEDR(GPIO_##bank) |= (0x3 << ((number)*2)))
 
 void board_config_post_gpio_init(void)
 {
 	/* We use MCO2 clock passthrough to provide a clock to USB HS */
 	gpio_config_module(MODULE_MCO, 1);
 	/* GPIO PC9 to high speed */
-	GPIO_SET_HS(C,  9);
+	GPIO_SET_HS(C, 9);
 
 	if (usb_ctl.phy_type == USB_PHY_ULPI)
 		gpio_set_level(GPIO_USB_MUX_SEL, 0);
@@ -66,19 +68,19 @@ void board_config_post_gpio_init(void)
 	GPIO_SET_HS(A, 11);
 	GPIO_SET_HS(A, 12);
 
-	GPIO_SET_HS(C,  3);
-	GPIO_SET_HS(C,  2);
-	GPIO_SET_HS(C,  0);
-	GPIO_SET_HS(A,  5);
+	GPIO_SET_HS(C, 3);
+	GPIO_SET_HS(C, 2);
+	GPIO_SET_HS(C, 0);
+	GPIO_SET_HS(A, 5);
 
-	GPIO_SET_HS(B,  5);
+	GPIO_SET_HS(B, 5);
 	GPIO_SET_HS(B, 13);
 	GPIO_SET_HS(B, 12);
-	GPIO_SET_HS(B,  2);
+	GPIO_SET_HS(B, 2);
 	GPIO_SET_HS(B, 10);
-	GPIO_SET_HS(B,  1);
-	GPIO_SET_HS(B,  0);
-	GPIO_SET_HS(A,  3);
+	GPIO_SET_HS(B, 1);
+	GPIO_SET_HS(B, 0);
+	GPIO_SET_HS(A, 3);
 }
 
 static void board_init(void)
diff --git a/board/polyberry/board.h b/board/polyberry/board.h
index 8e55967bf5..1390bb996c 100644
--- a/board/polyberry/board.h
+++ b/board/polyberry/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -44,15 +44,15 @@
 #define DEFAULT_SERIALNO "Uninitialized"
 
 /* USB interface indexes (use define rather than enum to expand them) */
-#define USB_IFACE_CONSOLE	0
-#define USB_IFACE_UPDATE	1
-#define USB_IFACE_COUNT		2
+#define USB_IFACE_CONSOLE 0
+#define USB_IFACE_UPDATE 1
+#define USB_IFACE_COUNT 2
 
 /* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL		0
-#define USB_EP_CONSOLE		1
-#define USB_EP_UPDATE		2
-#define USB_EP_COUNT		3
+#define USB_EP_CONTROL 0
+#define USB_EP_CONSOLE 1
+#define USB_EP_UPDATE 2
+#define USB_EP_COUNT 3
 
 /* This is not actually a Chromium EC so disable some features. */
 #undef CONFIG_WATCHDOG_HELP
@@ -60,7 +60,6 @@
 #undef CONFIG_WATCHDOG
 
 /* Optional features */
-#define CONFIG_STM_HWTIMER32
 
 /*
  * Allow dangerous commands all the time, since we don't have a write protect
diff --git a/board/polyberry/build.mk b/board/polyberry/build.mk
index 6b06f2bb8f..61e4b79d47 100644
--- a/board/polyberry/build.mk
+++ b/board/polyberry/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/polyberry/ec.tasklist b/board/polyberry/ec.tasklist
index c1fb169118..c45a1e89a7 100644
--- a/board/polyberry/ec.tasklist
+++ b/board/polyberry/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/polyberry/gpio.inc b/board/polyberry/gpio.inc
index 536dccc5ff..d862155c4d 100644
--- a/board/polyberry/gpio.inc
+++ b/board/polyberry/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/pompom/battery.c b/board/pompom/battery.c
index 7ce8eec202..2566813651 100644
--- a/board/pompom/battery.c
+++ b/board/pompom/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/pompom/board.c b/board/pompom/board.c
index 041993b01b..9f0b9e484a 100644
--- a/board/pompom/board.c
+++ b/board/pompom/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,37 +9,42 @@
 #include "button.h"
 #include "charge_manager.h"
 #include "charge_state.h"
-#include "extpower.h"
 #include "driver/accel_bma2x2.h"
+#include "driver/accel_lis2dw12.h"
 #include "driver/accelgyro_bmi_common.h"
 #include "driver/ppc/sn5s330.h"
 #include "driver/tcpm/ps8xxx.h"
 #include "driver/tcpm/tcpci.h"
+#include "extpower.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "keyboard_scan.h"
 #include "lid_switch.h"
 #include "pi3usb9201.h"
 #include "power.h"
+#include "power/qcom.h"
 #include "power_button.h"
 #include "pwm.h"
 #include "pwm_chip.h"
-#include "system.h"
 #include "shi_chip.h"
 #include "switch.h"
+#include "system.h"
 #include "tablet_mode.h"
 #include "task.h"
+#include "usbc_ocp.h"
 #include "usbc_ppc.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* Forward declaration */
 static void tcpc_alert_event(enum gpio_signal signal);
 static void usb0_evt(enum gpio_signal signal);
+static void usba_oc_interrupt(enum gpio_signal signal);
 static void ppc_interrupt(enum gpio_signal signal);
 static void board_connect_c0_sbu(enum gpio_signal s);
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /* GPIO Interrupt Handlers */
@@ -60,7 +65,20 @@ static void tcpc_alert_event(enum gpio_signal signal)
 
 static void usb0_evt(enum gpio_signal signal)
 {
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+
+static void usba_oc_deferred(void)
+{
+	/* Use next number after all USB-C ports to indicate the USB-A port */
+	board_overcurrent_event(CONFIG_USB_PD_PORT_MAX_COUNT,
+				!gpio_get_level(GPIO_USB_A0_OC_ODL));
+}
+DECLARE_DEFERRED(usba_oc_deferred);
+
+static void usba_oc_interrupt(enum gpio_signal signal)
+{
+	hook_call_deferred(&usba_oc_deferred_data, 0);
 }
 
 static void ppc_interrupt(enum gpio_signal signal)
@@ -90,7 +108,7 @@ static void board_connect_c0_sbu(enum gpio_signal s)
 }
 
 /* Keyboard scan setting */
-struct keyboard_scan_config keyscan_config = {
+__override struct keyboard_scan_config keyscan_config = {
 	/* Use 80 us, because KSO_02 passes through the H1. */
 	.output_settle_us = 80,
 	/*
@@ -98,10 +116,8 @@ struct keyboard_scan_config keyscan_config = {
 	 * as it uses the new location (KSO_00/KSI_03). And T11 key, which maps
 	 * to KSO_01/KSI_00, is not there.
 	 */
-	.actual_key_mask = {
-		0x1c, 0xfe, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca
-	},
+	.actual_key_mask = { 0x1c, 0xfe, 0xff, 0xff, 0xff, 0xf5, 0xff, 0xa4,
+			     0xff, 0xfe, 0x55, 0xfa, 0xca },
 	/* Other values should be the same as the default configuration. */
 	.debounce_down_us = 9 * MSEC,
 	.debounce_up_us = 30 * MSEC,
@@ -112,14 +128,26 @@ struct keyboard_scan_config keyscan_config = {
 
 /* I2C port map */
 const struct i2c_port_t i2c_ports[] = {
-	{"power",   I2C_PORT_POWER,  100, GPIO_EC_I2C_POWER_SCL,
-					  GPIO_EC_I2C_POWER_SDA},
-	{"tcpc0",   I2C_PORT_TCPC0, 1000, GPIO_EC_I2C_USB_C0_PD_SCL,
-					  GPIO_EC_I2C_USB_C0_PD_SDA},
-	{"eeprom",  I2C_PORT_EEPROM, 400, GPIO_EC_I2C_EEPROM_SCL,
-					  GPIO_EC_I2C_EEPROM_SDA},
-	{"sensor",  I2C_PORT_SENSOR, 400, GPIO_EC_I2C_SENSOR_SCL,
-					  GPIO_EC_I2C_SENSOR_SDA},
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_POWER_SCL,
+	  .sda = GPIO_EC_I2C_POWER_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C0_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C0_PD_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_EEPROM_SCL,
+	  .sda = GPIO_EC_I2C_EEPROM_SDA },
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_SENSOR_SCL,
+	  .sda = GPIO_EC_I2C_SENSOR_SDA },
 };
 
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
@@ -127,54 +155,37 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* Measure VBUS through a 1/10 voltage divider */
-	[ADC_VBUS] = {
-		"VBUS",
-		NPCX_ADC_CH1,
-		ADC_MAX_VOLT * 10,
-		ADC_READ_MAX + 1,
-		0
-	},
+	[ADC_VBUS] = { "VBUS", NPCX_ADC_CH1, ADC_MAX_VOLT * 10,
+		       ADC_READ_MAX + 1, 0 },
 	/*
 	 * Adapter current output or battery charging/discharging current (uV)
 	 * 18x amplification on charger side.
 	 */
-	[ADC_AMON_BMON] = {
-		"AMON_BMON",
-		NPCX_ADC_CH2,
-		ADC_MAX_VOLT * 1000 / 18,
-		ADC_READ_MAX + 1,
-		0
-	},
+	[ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH2, ADC_MAX_VOLT * 1000 / 18,
+			    ADC_READ_MAX + 1, 0 },
 	/*
 	 * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read
 	 * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and
 	 * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we
 	 * only divide by 2 (enough to avoid precision issues).
 	 */
-	[ADC_PSYS] = {
-		"PSYS",
-		NPCX_ADC_CH3,
-		ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1),
-		2,
-		0
-	},
+	[ADC_PSYS] = { "PSYS", NPCX_ADC_CH3,
+		       ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), 2, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct pwm_t pwm_channels[] = {
 	[PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 },
 	/* TODO(waihong): Assign a proper frequency. */
-	[PWM_CH_DISPLIGHT] = { .channel = 5, .flags = 0, .freq = 4800 },
+	[PWM_CH_DISPLIGHT] = { .channel = 5, .flags = 0, .freq = 20000 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
 /* Power Path Controller */
 struct ppc_config_t ppc_chips[] = {
-	{
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
+	{ .i2c_port = I2C_PORT_TCPC0,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
 };
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
@@ -184,7 +195,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = I2C_PORT_TCPC0,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
 		},
 		.drv = &ps8xxx_tcpm_drv,
 	},
@@ -197,11 +208,14 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
  * to AP. But the TCPC chip is also needed to know the HPD status; otherwise,
  * the mux misbehaves.
  */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	},
 };
 
@@ -224,9 +238,21 @@ const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
 /* Initialize board. */
 static void board_init(void)
 {
+	/*
+	 * The rev-2 hardware doesn't have the external pull-up fix for the bug
+	 * b/164256614. It requires rework to stuff the resistor. For people who
+	 * has difficulty to do the rework, this is a workaround, which makes
+	 * the GPIO push-pull, instead of open-drain.
+	 */
+	if (system_get_board_version() == 2)
+		gpio_set_flags(GPIO_HIBERNATE_L, GPIO_OUTPUT);
+
 	/* Enable BC1.2 interrupts */
 	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_L);
 
+	/* Enable USB-A overcurrent interrupt */
+	gpio_enable_interrupt(GPIO_USB_A0_OC_ODL);
+
 	/* Enable interrupt for BMI160 sensor */
 	gpio_enable_interrupt(GPIO_ACCEL_GYRO_INT_L);
 
@@ -242,13 +268,39 @@ static void board_init(void)
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
+void board_hibernate(void)
+{
+	/*
+	 * Sensors are unpowered in hibernate. Apply PD to the
+	 * interrupt lines such that they don't float.
+	 */
+	gpio_set_flags(GPIO_ACCEL_GYRO_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
+	gpio_set_flags(GPIO_LID_ACCEL_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
+
+	/*
+	 * Board rev 2+ has the hardware fix. Don't need the following
+	 * workaround.
+	 */
+	if (system_get_board_version() >= 2)
+		return;
+
+	/*
+	 * Enable the PPC power sink path before EC enters hibernate;
+	 * otherwise, ACOK won't go High and can't wake EC up. Check the
+	 * bug b/170324206 for details.
+	 */
+	ppc_vbus_sink_enable(USB_PD_PORT_C0, 1);
+}
+
 __override uint16_t board_get_ps8xxx_product_id(int port)
 {
-	/* Pompom rev 1+ changes TCPC from PS8751 to PS8805 */
+	/* Pompom rev 2+ changes TCPC from PS8805 to PS8755 */
 	if (system_get_board_version() == 0)
 		return PS8751_PRODUCT_ID;
+	else if (system_get_board_version() == 1)
+		return PS8805_PRODUCT_ID;
 
-	return PS8805_PRODUCT_ID;
+	return PS8755_PRODUCT_ID;
 }
 
 void board_tcpc_init(void)
@@ -269,10 +321,11 @@ void board_tcpc_init(void)
 	 * Initialize HPD to low; after sysjump SOC needs to see
 	 * HPD pulse to enable video path
 	 */
-	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		usb_mux_hpd_update(port, 0, 0);
+	usb_mux_hpd_update(USB_PD_PORT_C0,
+			   USB_PD_MUX_HPD_LVL_DEASSERTED |
+				   USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
 
 /* Called on AP S0 -> S3 transition */
 static void board_chipset_suspend(void)
@@ -350,25 +403,20 @@ void board_overcurrent_event(int port, int is_overcurrented)
 
 int board_set_active_charge_port(int port)
 {
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	int i;
+	int is_real_port = (port == USB_PD_PORT_C0);
 
 	if (!is_real_port && port != CHARGE_PORT_NONE)
 		return EC_ERROR_INVAL;
 
 	if (port == CHARGE_PORT_NONE) {
 		CPRINTS("Disabling all charging port");
-
-		/* Disable all ports. */
-		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-			/*
-			 * Do not return early if one fails otherwise we can
-			 * get into a boot loop assertion failure.
-			 */
-			if (board_vbus_sink_enable(i, 0))
-				CPRINTS("Disabling p%d sink path failed.", i);
-		}
+		/*
+		 * Do not return early if one fails otherwise we can
+		 * get into a boot loop assertion failure.
+		 */
+		if (board_vbus_sink_enable(USB_PD_PORT_C0, 0))
+			CPRINTS("Disabling p%d sink path failed.",
+				USB_PD_PORT_C0);
 
 		return EC_SUCCESS;
 	}
@@ -379,21 +427,8 @@ int board_set_active_charge_port(int port)
 		return EC_ERROR_INVAL;
 	}
 
-
 	CPRINTS("New charge port: p%d", port);
 
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		if (i == port)
-			continue;
-
-		if (board_vbus_sink_enable(i, 0))
-			CPRINTS("p%d: sink path disable failed.", i);
-	}
-
 	/* Enable requested charge port. */
 	if (board_vbus_sink_enable(port, 1)) {
 		CPRINTS("p%d: sink path enable failed.", port);
@@ -403,23 +438,20 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
 {
 	/*
 	 * Ignore lower charge ceiling on PD transition if our battery is
 	 * critical, as we may brownout.
 	 */
-	if (supplier == CHARGE_SUPPLIER_PD &&
-	    charge_ma < 1500 &&
+	if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 &&
 	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
 		CPRINTS("Using max ilim %d", max_ma);
 		charge_ma = max_ma;
 	}
 
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
+	charge_set_input_current_limit(charge_ma, charge_mv);
 }
 
 uint16_t tcpc_get_alert_status(void)
@@ -439,19 +471,16 @@ static struct mutex g_lid_mutex;
 
 static struct bmi_drv_data_t g_bmi160_data;
 static struct accelgyro_saved_data_t g_bma255_data;
+static struct stprivate_data g_lis2dwl_data;
 
 /* Matrix to rotate accelerometer into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0,  0},
-	{ 0,  FLOAT_TO_FP(1),  0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+				       { 0, FLOAT_TO_FP(1), 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
 
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					     { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
@@ -487,7 +516,7 @@ struct motion_sensor_t motion_sensors[] = {
 	 */
 	[BASE_ACCEL] = {
 	 .name = "Base Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3_S5,
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
 	 .chip = MOTIONSENSE_CHIP_BMI160,
 	 .type = MOTIONSENSE_TYPE_ACCEL,
 	 .location = MOTIONSENSE_LOC_BASE,
@@ -512,7 +541,7 @@ struct motion_sensor_t motion_sensors[] = {
 	},
 	[BASE_GYRO] = {
 	 .name = "Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3_S5,
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
 	 .chip = MOTIONSENSE_CHIP_BMI160,
 	 .type = MOTIONSENSE_TYPE_GYRO,
 	 .location = MOTIONSENSE_LOC_BASE,
@@ -529,22 +558,53 @@ struct motion_sensor_t motion_sensors[] = {
 };
 const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
-#ifndef TEST_BUILD
-/* This callback disables keyboard when convertibles are fully open */
-void lid_angle_peripheral_enable(int enable)
+struct motion_sensor_t lis2dwl_lid_accel = {
+	.name = "Lid Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_LIS2DWL,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_LID,
+	.drv = &lis2dw12_drv,
+	.mutex = &g_lid_mutex,
+	.drv_data = &g_lis2dwl_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = LIS2DWL_ADDR0_FLAGS,
+	.rot_standard_ref = &lid_standard_ref,
+	.default_range = 2, /* g */
+	.min_frequency = LIS2DW12_ODR_MIN_VAL,
+	.max_frequency = LIS2DW12_ODR_MAX_VAL,
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 12500 | ROUND_UP_FLAG,
+		},
+		/* Sensor on for lid angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	},
+};
+
+static void board_detect_motionsensor(void)
 {
-	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
+	int val = 0;
 
-	if (enable) {
-		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
-	} else {
-		/*
-		 * Ensure that the chipset is off before disabling the keyboard.
-		 * When the chipset is on, the EC keeps the keyboard enabled and
-		 * the AP decides whether to ignore input devices or not.
-		 */
-		if (!chipset_in_s0)
-			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
+	/*
+	 * BMA253 and LIS2DWL have same target address, so we check the
+	 * LIS2DWL WHO AM I register to check the lid accel type
+	 */
+	i2c_read8(I2C_PORT_SENSOR, LIS2DWL_ADDR0_FLAGS, LIS2DW12_WHO_AM_I_REG,
+		  &val);
+
+	if (val == LIS2DW12_WHO_AM_I) {
+		motion_sensors[LID_ACCEL] = lis2dwl_lid_accel;
+		CPRINTS("Lid Accel: LIS2DWL");
 	}
 }
-#endif
+
+static void board_update_sensor_config_from_sku(void)
+{
+	board_detect_motionsensor();
+}
+DECLARE_HOOK(HOOK_INIT, board_update_sensor_config_from_sku,
+	     HOOK_PRIO_INIT_I2C + 2);
diff --git a/board/pompom/board.h b/board/pompom/board.h
index 11d48a5d40..de7fd92a75 100644
--- a/board/pompom/board.h
+++ b/board/pompom/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,31 +11,29 @@
 #include "baseboard.h"
 #include "board_revs.h"
 
-/* TODO(waihong): Remove the following bringup features */
-#define CONFIG_BRINGUP
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands. */
-#define CONFIG_USB_PD_DEBUG_LEVEL 3
-#define CONFIG_CMD_AP_RESET_LOG
-#define CONFIG_CMD_GPIO_EXTENDED
-#define CONFIG_CMD_POWERINDEBUG
-#define CONFIG_I2C_DEBUG
-
 /* Internal SPI flash on NPCX7 */
-#define CONFIG_FLASH_SIZE (512 * 1024)  /* 512KB internal spi flash */
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */
 
 /* Keyboard */
-#define CONFIG_KEYBOARD_BOARD_CONFIG
+#define CONFIG_KEYBOARD_PROTOCOL_MKBP
+
+#define CONFIG_KEYBOARD_REFRESH_ROW3
 #define CONFIG_PWM_KBLIGHT
 
 /* BC 1.2 Charger */
 #define CONFIG_BC12_DETECT_PI3USB9201
 
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 5
+
 /* USB */
 #define CONFIG_USB_PD_TCPM_MULTI_PS8XXX
 #define CONFIG_USB_PD_TCPM_PS8751
+#define CONFIG_USB_PD_TCPM_PS8755
 #define CONFIG_USB_PD_TCPM_PS8805
 #define CONFIG_USBC_PPC_SN5S330
 #define CONFIG_USB_PD_PORT_MAX_COUNT 1
+#define USB_PD_PORT_C0 0
 
 /* USB-A */
 #define USB_PORT_COUNT 1
@@ -44,13 +42,13 @@
 /* Sensors */
 /* BMI160 Base accel/gyro */
 #define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCEL_INTERRUPTS
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 #define OPT3001_I2C_ADDR_FLAGS OPT3001_I2C_ADDR1_FLAGS
 
 /* BMA253 lid accel */
 #define CONFIG_ACCEL_BMA255
+#define CONFIG_ACCEL_LIS2DWL
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
 
 #define CONFIG_LID_ANGLE
@@ -61,7 +59,7 @@
 #define CONFIG_TABLET_MODE
 #define CONFIG_TABLET_MODE_SWITCH
 #define CONFIG_GMR_TABLET_MODE
-#define GMR_TABLET_MODE_GPIO_L GPIO_LID_360_L
+#define GPIO_TABLET_MODE_L GPIO_LID_360_L
 
 /* GPIO alias */
 #define GPIO_AC_PRESENT GPIO_ACOK_OD
@@ -78,12 +76,7 @@
 #include "gpio_signal.h"
 #include "registers.h"
 
-enum adc_channel {
-	ADC_VBUS,
-	ADC_AMON_BMON,
-	ADC_PSYS,
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_VBUS, ADC_AMON_BMON, ADC_PSYS, ADC_CH_COUNT };
 
 /* Motion sensors */
 enum sensor_id {
@@ -93,25 +86,13 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_DISPLIGHT,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_DISPLIGHT, PWM_CH_COUNT };
 
 enum battery_type {
 	BATTERY_BYD,
 	BATTERY_TYPE_COUNT,
 };
 
-/* Swithcap functions */
-void board_set_switchcap_power(int enable);
-int board_is_switchcap_enabled(void);
-int board_is_switchcap_power_good(void);
-/* Custom function to indicate if sourcing VBUS */
-int board_is_sourcing_vbus(int port);
-/* Enable VBUS sink for a given port */
-int board_vbus_sink_enable(int port, int enable);
 /* Reset all TCPCs. */
 void board_reset_pd_mcu(void);
 void board_set_tcpc_power_mode(int port, int mode);
diff --git a/board/pompom/board_revs.h b/board/pompom/board_revs.h
index 1ac5ee1337..8edc249df0 100644
--- a/board/pompom/board_revs.h
+++ b/board/pompom/board_revs.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,7 +8,7 @@
 
 #define POMPOM_REV0 0
 #define POMPOM_REV1 1
-#define POMPOM_REV_LAST    POMPOM_REV1
+#define POMPOM_REV_LAST POMPOM_REV1
 #define POMPOM_REV_DEFAULT POMPOM_REV1
 
 #if !defined(BOARD_REV)
@@ -19,5 +19,4 @@
 #error "Board revision out of range"
 #endif
 
-
 #endif /* __CROS_EC_BOARD_REVS_H */
diff --git a/board/pompom/build.mk b/board/pompom/build.mk
index a044fa58cb..8d302988f4 100644
--- a/board/pompom/build.mk
+++ b/board/pompom/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -11,4 +11,4 @@ CHIP_FAMILY:=npcx7
 CHIP_VARIANT:=npcx7m6fc
 BASEBOARD:=trogdor
 
-board-y=battery.o board.o led.o
+board-y=battery.o board.o led.o usbc_config.o
diff --git a/board/pompom/ec.tasklist b/board/pompom/ec.tasklist
index 7ec8b46059..9145e6dd84 100644
--- a/board/pompom/ec.tasklist
+++ b/board/pompom/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/pompom/gpio.inc b/board/pompom/gpio.inc
index 70d210b670..3016f8b9d5 100644
--- a/board/pompom/gpio.inc
+++ b/board/pompom/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,23 +8,23 @@
 /* Declare symbolic names for all the GPIOs that we care about.
  * Note: Those with interrupt handlers must be declared first. */
 
-/* USB-C interrupts */
+/* USB interrupts */
 GPIO_INT(USB_C0_PD_INT_ODL,    PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-0 TCPC */
 GPIO_INT(USB_C0_SWCTL_INT_ODL, PIN(0, 3), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-0 PPC */
-GPIO_INT(USB_C0_BC12_INT_L,    PIN(6, 1), GPIO_INT_FALLING, usb0_evt)  /* Interrupt from port-0 BC1.2 */
+GPIO_INT(USB_C0_BC12_INT_L,    PIN(6, 1), GPIO_INT_FALLING | GPIO_PULL_UP, usb0_evt)  /* Interrupt from port-0 BC1.2 */
+GPIO_INT(USB_A0_OC_ODL,        PIN(D, 1), GPIO_INT_BOTH | GPIO_PULL_UP, usba_oc_interrupt)
 
 /* System interrupts */
-GPIO_INT(ACOK_OD,           PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)  /* AC OK? */
+GPIO_INT(ACOK_OD,           PIN(0, 0), GPIO_INT_BOTH, extpower_interrupt)  /* ACOK */
 GPIO_INT(CCD_MODE_ODL,      PIN(E, 3), GPIO_INT_FALLING, board_connect_c0_sbu)  /* Case Closed Debug Mode */
 GPIO_INT(EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)  /* Power button */
 GPIO_INT(EC_VOLDN_BTN_ODL,  PIN(7, 0), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Up button */
 GPIO_INT(EC_VOLUP_BTN_ODL,  PIN(F, 2), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Down button */
 GPIO_INT(EC_WP_ODL,         PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)  /* Write protection */
-GPIO_INT(LID_OPEN_EC,       PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)  /* Lid open? */
+GPIO_INT(LID_OPEN_EC,       PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)  /* Lid open */
 GPIO_INT(AP_RST_L,          PIN(C, 1), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_ap_rst_interrupt)  /* PMIC to signal AP reset */
-GPIO_INT(PS_HOLD,           PIN(A, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V, power_signal_interrupt)  /* Indicate when AP triggers reset/shutdown */
-GPIO_INT(PMIC_FAULT_L,      PIN(A, 3), GPIO_INT_BOTH | GPIO_SEL_1P8V, power_signal_interrupt)  /* Any PMIC fault? */
-GPIO_INT(AP_SUSPEND,        PIN(5, 7), GPIO_INT_BOTH | GPIO_SEL_1P8V, power_signal_interrupt)  /* Suspend signal from PMIC */
+GPIO_INT(PS_HOLD,           PIN(A, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, power_signal_interrupt)  /* Indicate when AP triggers reset/shutdown */
+GPIO_INT(AP_SUSPEND,        PIN(5, 7), GPIO_INT_BOTH, power_signal_interrupt)  /* Suspend signal from PMIC */
 GPIO_INT(DEPRECATED_AP_RST_REQ, PIN(C, 2), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V, power_signal_interrupt) /* Deprecated AP initiated reset indicator */
 /*
  * When switch-cap is off, the POWER_GOOD signal is floating. Need a pull-down
@@ -38,32 +38,25 @@ GPIO_INT(AP_EC_SPI_CS_L,    PIN(5, 3), GPIO_INT_FALLING | GPIO_PULL_DOWN, shi_cs
 
 /* Sensor interrupts */
 GPIO_INT(LID_360_L,         PIN(7, 2), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-GPIO_INT(ACCEL_GYRO_INT_L,  PIN(A, 0), GPIO_INT_FALLING | GPIO_SEL_1P8V, bmi160_interrupt)  /* Accelerometer/gyro interrupt */
+GPIO_INT(ACCEL_GYRO_INT_L,  PIN(A, 0), GPIO_INT_FALLING, bmi160_interrupt)  /* Accelerometer/gyro interrupt */
 
 /*
- * EC_RST_ODL acts as a wake source from PSL hibernate mode. However, it does
- * not need to be an interrupt for normal EC operations. Thus, configure it as
- * GPIO_INT_BOTH with wake on low-to-high edge using GPIO_HIB_WAKE_HIGH so that
- * PSL common code can configure PSL_IN correctly.
- *
- * Use the rising edge to wake EC up. If we chose the falling edge, it would
- * still wake EC up, but EC is in an intermediate state until the signal goes
- * back to high.
+ * EC_RST_ODL acts as a wake source from hibernate mode. However, it does not
+ * need to be an interrupt for normal EC operations. Simply set it an INPUT.
  */
-GPIO(EC_RST_ODL_GPIO02,     PIN(0, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH)  /* Wake source: EC reset */
+GPIO(EC_RST_ODL_GPIO02,     PIN(0, 2), GPIO_INPUT)     /* EC reset */
 GPIO(EC_ENTERING_RW,        PIN(E, 1), GPIO_OUT_LOW)   /* Indicate when EC is entering RW code */
 GPIO(EC_BATT_PRES_ODL,      PIN(E, 5), GPIO_INPUT)     /* Battery Present */
 
 /* PMIC/AP 1.8V */
-GPIO(PM7180_RESIN_D_L,      PIN(3, 2), GPIO_ODR_HIGH | GPIO_SEL_1P8V)  /* PMIC reset trigger */
-GPIO(PMIC_KPD_PWR_ODL,      PIN(D, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V)  /* PMIC power button */
+GPIO(PM7180_RESIN_D_L,      PIN(3, 2), GPIO_ODR_HIGH)  /* PMIC reset trigger */
+GPIO(PMIC_KPD_PWR_ODL,      PIN(D, 6), GPIO_ODR_HIGH)  /* PMIC power button */
 GPIO(EC_INT_L,              PIN(A, 2), GPIO_ODR_HIGH)  /* Interrupt line between AP and EC */
 GPIO(QSIP_ON,               PIN(5, 0), GPIO_OUT_LOW)   /* Not used, for non-switchcap testing */
 
 /* Power enables */
+GPIO(HIBERNATE_L,           PIN(5, 2), GPIO_ODR_HIGH)  /* EC hibernate */
 GPIO(SWITCHCAP_ON,          PIN(D, 5), GPIO_OUT_LOW)   /* Enable switch cap */
-/* TODO(waihong): Remove it. The VBOB switch is for backup. */
-GPIO(VBOB_EN,               PIN(D, 3), GPIO_OUT_LOW)   /* Enable VBOB */
 GPIO(EN_PP3300_A,           PIN(A, 6), GPIO_OUT_LOW)   /* Enable PP3300 */
 GPIO(EN_PP5000_A,           PIN(6, 7), GPIO_OUT_LOW)   /* Enable PP5000 */
 GPIO(EC_BL_DISABLE_L,       PIN(B, 6), GPIO_OUT_LOW)   /* Backlight disable signal from EC */
@@ -76,24 +69,28 @@ GPIO(TRACKPAD_INT_GATE,     PIN(7, 4), GPIO_OUT_LOW)
 
 /* USB-C */
 GPIO(USB_C0_PD_RST_L,       PIN(F, 1), GPIO_OUT_HIGH)  /* Port-0 TCPC chip reset */
-GPIO(DP_MUX_OE_L,           PIN(9, 6), GPIO_OUT_HIGH)  /* DP mux enable */
-GPIO(DP_MUX_SEL,            PIN(4, 5), GPIO_OUT_HIGH)  /* DP mux selection: L:C0, H:C1 */
+GPIO(DP_MUX_OE_L,           PIN(9, 6), GPIO_ODR_HIGH)  /* DP mux enable, actually Open-Drain */
+GPIO(DP_MUX_SEL,            PIN(4, 5), GPIO_OUT_LOW)   /* DP mux selection: L:C0, H:C1 */
 GPIO(DP_HOT_PLUG_DET,       PIN(9, 5), GPIO_OUT_LOW)   /* DP HPD to AP */
-/* TODO(waihong): Remove it from schematic. No use. */
-GPIO(USBC_MUX_CONF0,        PIN(5, 1), GPIO_INPUT)
-GPIO(USB_C0_VBUS_DET_L,     PIN(6, 2), GPIO_INPUT)     /* Deprecated BC1.2 VBUS detection on port-0 */
-
 
 /* USB-A */
 GPIO(EN_USB_A_5V,           PIN(8, 6), GPIO_OUT_LOW)
 GPIO(USB_A_CDP_ILIM_EN,     PIN(7, 5), GPIO_OUT_HIGH)  /* H: CDP, L:SDP. Only one USB-A port, always CDP */
-GPIO(USB_A0_OC_ODL,         PIN(D, 1), GPIO_ODR_HIGH)
 
 /* LEDs */
 GPIO(EC_CHG_LED_Y_C0,       PIN(C, 3), GPIO_OUT_LOW)
 GPIO(EC_CHG_LED_W_C0,       PIN(C, 4), GPIO_OUT_LOW)
 GPIO(EC_PWR_LED_W,          PIN(6, 0), GPIO_OUT_LOW)
 
+/*
+ * SPI host interface - enable PDs by default. These will be made functional
+ * by the SHI driver when the AP powers up, and restored back to GPIO when
+ * the AP powers down.
+ */
+GPIO(AP_EC_SPI_MOSI,        PIN(4, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(AP_EC_SPI_MISO,        PIN(4, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(AP_EC_SPI_CLK,         PIN(5, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+
 /* PWM */
 GPIO(KB_BL_PWM,             PIN(8, 0), GPIO_INPUT)     /* PWM3 */
 GPIO(EDP_BKLTCTL,           PIN(B, 7), GPIO_INPUT)     /* PWM5 */
@@ -128,6 +125,37 @@ GPIO(SKU_ID2,               PIN(D, 4), GPIO_INPUT)
  */
 GPIO(DA9313_GPIO0,          PIN(E, 2), GPIO_INPUT | GPIO_PULL_DOWN) /* Switchcap GPIO0 */
 
+/* Special straps */
+GPIO(ARM_X86,               PIN(6, 6), GPIO_OUT_LOW)  /* NC, low for power saving */
+
+/* Unused GPIOs, NC. */
+UNUSED(PIN(5, 1))
+UNUSED(PIN(D, 0))
+UNUSED(PIN(F, 3))
+UNUSED(PIN(0, 4))
+UNUSED(PIN(C, 0))
+UNUSED(PIN(A, 7))
+UNUSED(PIN(8, 3))
+UNUSED(PIN(8, 1))
+UNUSED(PIN(3, 7))
+UNUSED(PIN(7, 6))
+UNUSED(PIN(3, 4))
+UNUSED(PIN(C, 5))
+UNUSED(PIN(C, 6))
+UNUSED(PIN(A, 3))
+UNUSED(PIN(7, 3))
+UNUSED(PIN(D, 7))
+UNUSED(PIN(A, 5))
+UNUSED(PIN(B, 0))
+UNUSED(PIN(9, 4))
+UNUSED(PIN(B, 1))
+UNUSED(PIN(6, 2))
+UNUSED(PIN(E, 4))
+UNUSED(PIN(F, 5))
+UNUSED(PIN(3, 5))
+UNUSED(PIN(9, 7))
+UNUSED(PIN(D, 3))
+
 /* Alternate functions GPIO definitions */
 ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)            /* UART (GPIO64/65) */
 ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0)             /* I2C0 (GPIOB4/B5) */
@@ -140,10 +168,6 @@ ALTERNATE(PIN_MASK(4, 0xC0), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SDO (GPIO47),
 ALTERNATE(PIN_MASK(5, 0x28), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SCLK (GPIO55), SHI_CS# (GPIO53) */
 ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)             /* PWM3 (GPIO80) - KB_BL_PWM */
 ALTERNATE(PIN_MASK(B, 0x80), 1, MODULE_PWM, 0)             /* PWM5 (GPIOB7) - EDP_BKLTCTL */
-ALTERNATE(PIN_MASK(D, 0x04), 1, MODULE_PMU, 0)             /* PSL_IN1 (GPIOD2) - LID_OPEN_EC */
-ALTERNATE(PIN_MASK(0, 0x01), 1, MODULE_PMU, 0)             /* PSL_IN2 (GPIO00) - ACOK_OD */
-ALTERNATE(PIN_MASK(0, 0x02), 1, MODULE_PMU, 0)             /* PSL_IN3 (GPIO01) - EC_PWR_BTN_ODL */
-ALTERNATE(PIN_MASK(0, 0x04), 1, MODULE_PMU, 0)             /* PSL_IN4 (GPIO02) - EC_RST_ODL */
 
 /* Keyboard */
 #define GPIO_KB_INPUT           (GPIO_INPUT | GPIO_PULL_UP)
diff --git a/board/pompom/led.c b/board/pompom/led.c
index db571a067c..fffd367cc5 100644
--- a/board/pompom/led.c
+++ b/board/pompom/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -31,21 +31,21 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static void led_set_color_battery(enum led_color color)
 {
 	gpio_set_level(GPIO_EC_CHG_LED_Y_C0,
-		(color == LED_AMBER) ? LED_ON_LVL : LED_OFF_LVL);
+		       (color == LED_AMBER) ? LED_ON_LVL : LED_OFF_LVL);
 	gpio_set_level(GPIO_EC_CHG_LED_W_C0,
-		(color == LED_WHITE) ? LED_ON_LVL : LED_OFF_LVL);
+		       (color == LED_WHITE) ? LED_ON_LVL : LED_OFF_LVL);
 }
 
 void led_set_color_power(enum led_color color)
 {
 	gpio_set_level(GPIO_EC_PWR_LED_W,
-		(color == LED_WHITE) ? LED_ON_LVL : LED_OFF_LVL);
+		       (color == LED_WHITE) ? LED_ON_LVL : LED_OFF_LVL);
 }
 
 void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
@@ -82,20 +82,19 @@ static void board_led_set_battery(void)
 	static int battery_ticks;
 	int color = LED_OFF;
 	int period = 0;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
 		/* Always indicate amber on when charging. */
 		color = LED_AMBER;
 		break;
-	case PWR_STATE_DISCHARGE:
+	case LED_PWRS_DISCHARGE:
 		/* Discharging : off */
 		color = LED_OFF;
 		break;
-	case PWR_STATE_ERROR:
+	case LED_PWRS_ERROR:
 		/* Battery error: Amber 1 sec, off 1 sec */
 		period = (1 + 1);
 		battery_ticks = battery_ticks % period;
@@ -104,21 +103,21 @@ static void board_led_set_battery(void)
 		else
 			color = LED_OFF;
 		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
+	case LED_PWRS_CHARGE_NEAR_FULL:
 		/* Full Charged: White on */
 		color = LED_WHITE;
 		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE) {
-			/* Factory mode: White 2 sec, Amber 2 sec */
-			period = (2 + 2);
-			battery_ticks = battery_ticks % period;
-			if (battery_ticks < 2)
-				color = LED_WHITE;
-			else
-				color = LED_AMBER;
-		} else
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		color = LED_WHITE;
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		/* Factory mode: White 2 sec, Amber 2 sec */
+		period = (2 + 2);
+		battery_ticks = battery_ticks % period;
+		if (battery_ticks < 2)
 			color = LED_WHITE;
+		else
+			color = LED_AMBER;
 		break;
 	default:
 		/* Other states don't alter LED behavior */
diff --git a/board/pompom/usbc_config.c b/board/pompom/usbc_config.c
new file mode 100644
index 0000000000..28f6b7a1c9
--- /dev/null
+++ b/board/pompom/usbc_config.c
@@ -0,0 +1,61 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Trogdor family-specific USB-C configuration */
+
+#include "charge_state.h"
+#include "charger.h"
+#include "charger/isl923x_public.h"
+#include "console.h"
+#include "usb_pd.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+};
+
+int charger_profile_override(struct charge_state_data *curr)
+{
+	int usb_mv;
+	int port;
+
+	if (curr->state != ST_CHARGE)
+		return 0;
+
+	/* Lower the max requested voltage to 5V when battery is full. */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
+	    !(curr->batt.flags & BATT_FLAG_BAD_STATUS) &&
+	    !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
+	    (curr->batt.status & STATUS_FULLY_CHARGED))
+		usb_mv = 5000;
+	else
+		usb_mv = PD_MAX_VOLTAGE_MV;
+
+	if (pd_get_max_voltage() != usb_mv) {
+		CPRINTS("VBUS limited to %dmV", usb_mv);
+		for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++)
+			pd_set_external_voltage_limit(port, usb_mv);
+	}
+
+	return 0;
+}
+
+enum ec_status charger_profile_override_get_param(uint32_t param,
+						  uint32_t *value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+enum ec_status charger_profile_override_set_param(uint32_t param,
+						  uint32_t value)
+{
+	return EC_RES_INVALID_PARAM;
+}
diff --git a/board/pompom/vif_override.xml b/board/pompom/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/pompom/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/poppy/base_detect_lux.c b/board/poppy/base_detect_lux.c
index 155243af0e..8b799a3dbd 100644
--- a/board/poppy/base_detect_lux.c
+++ b/board/poppy/base_detect_lux.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,6 @@
 /* Lux base detection code */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "board.h"
 #include "chipset.h"
 #include "common.h"
@@ -21,8 +20,8 @@
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USB, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args)
 
 /* Base detection and debouncing */
 #define BASE_DETECT_DEBOUNCE_US (20 * MSEC)
@@ -45,7 +44,7 @@
 #define BASE_DISCONNECTED_CONNECT_MAX_MV 600
 
 #define BASE_DISCONNECTED_MIN_MV 2800
-#define BASE_DISCONNECTED_MAX_MV (ADC_MAX_VOLT+1)
+#define BASE_DISCONNECTED_MAX_MV (ADC_MAX_VOLT + 1)
 
 /*
  * When base is connected, then gets disconnected:
@@ -94,7 +93,7 @@ int board_is_base_connected(void)
 void board_enable_base_power(int enable)
 {
 	gpio_set_level(GPIO_PPVAR_VAR_BASE,
-		enable && current_base_status == BASE_CONNECTED);
+		       enable && current_base_status == BASE_CONNECTED);
 }
 
 /*
@@ -128,7 +127,7 @@ static void base_detect_change(enum base_status status)
 	 */
 	task_wake(TASK_ID_CHARGER);
 
-	tablet_set_mode(!connected);
+	tablet_set_mode(!connected, TABLET_TRIGGER_BASE);
 }
 
 static void print_base_detect_value(const char *str, int v)
@@ -182,8 +181,7 @@ static void base_detect_deferred(void)
 retry:
 	print_base_detect_value("status unclear", v);
 	/* Unclear base status, schedule again in a while. */
-	hook_call_deferred(&base_detect_deferred_data,
-				   BASE_DETECT_RETRY_US);
+	hook_call_deferred(&base_detect_deferred_data, BASE_DETECT_RETRY_US);
 }
 
 void base_detect_interrupt(enum gpio_signal signal)
@@ -217,21 +215,21 @@ static void base_init(void)
 	hook_call_deferred(&base_detect_deferred_data, BASE_DETECT_DEBOUNCE_US);
 	gpio_enable_interrupt(GPIO_BASE_DET_A);
 }
-DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT+1);
+DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT + 1);
 
-void base_force_state(int state)
+void base_force_state(enum ec_set_base_state_cmd state)
 {
-	if (state == 1) {
+	if (state == EC_SET_BASE_STATE_ATTACH) {
 		gpio_disable_interrupt(GPIO_BASE_DET_A);
 		base_detect_change(BASE_CONNECTED);
 		CPRINTS("BD forced connected");
-	} else if (state == 0) {
+	} else if (state == EC_SET_BASE_STATE_DETACH) {
 		gpio_disable_interrupt(GPIO_BASE_DET_A);
 		base_detect_change(BASE_DISCONNECTED);
 		CPRINTS("BD forced disconnected");
 	} else {
 		hook_call_deferred(&base_detect_deferred_data,
-			BASE_DETECT_DEBOUNCE_US);
+				   BASE_DETECT_DEBOUNCE_US);
 		gpio_enable_interrupt(GPIO_BASE_DET_A);
 		CPRINTS("BD forced reset");
 	}
diff --git a/board/poppy/base_detect_poppy.c b/board/poppy/base_detect_poppy.c
index 358461896e..e6ac6e8da7 100644
--- a/board/poppy/base_detect_poppy.c
+++ b/board/poppy/base_detect_poppy.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,7 +7,6 @@
 
 #include "acpi.h"
 #include "adc.h"
-#include "adc_chip.h"
 #include "board.h"
 #include "chipset.h"
 #include "common.h"
@@ -20,8 +19,8 @@
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USB, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args)
 
 /* Base detection and debouncing */
 #define BASE_DETECT_DEBOUNCE_US (20 * MSEC)
@@ -95,14 +94,13 @@ static void base_detect_change(enum base_status status)
 
 	CPRINTS("Base %sconnected", connected ? "" : "not ");
 	gpio_set_level(GPIO_PP3300_DX_BASE, connected);
-	tablet_set_mode(!connected);
+	tablet_set_mode(!connected, TABLET_TRIGGER_BASE);
 	current_base_status = status;
 
 	if (connected)
 		acpi_dptf_set_profile_num(DPTF_PROFILE_BASE_ATTACHED);
 	else
 		acpi_dptf_set_profile_num(DPTF_PROFILE_BASE_DETACHED);
-
 }
 
 /* Measure detection pin pulse duration (used to wake AP from deep S3). */
@@ -111,8 +109,8 @@ static uint32_t pulse_width;
 
 static void print_base_detect_value(int v, int tmp_pulse_width)
 {
-	CPRINTS("%s = %d (pulse %d)", adc_channels[ADC_BASE_DET].name,
-			v, tmp_pulse_width);
+	CPRINTS("%s = %d (pulse %d)", adc_channels[ADC_BASE_DET].name, v,
+		tmp_pulse_width);
 }
 
 static void base_detect_deferred(void)
@@ -244,15 +242,15 @@ static void base_init(void)
 	if (system_jumped_late() && chipset_in_state(CHIPSET_STATE_ON))
 		base_enable();
 }
-DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT+1);
+DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT + 1);
 
-void base_force_state(int state)
+void base_force_state(enum ec_set_base_state_cmd state)
 {
-	if (state == 1) {
+	if (state == EC_SET_BASE_STATE_ATTACH) {
 		gpio_disable_interrupt(GPIO_BASE_DET_A);
 		base_detect_change(BASE_CONNECTED);
 		CPRINTS("BD forced connected");
-	} else if (state == 0) {
+	} else if (state == EC_SET_BASE_STATE_DETACH) {
 		gpio_disable_interrupt(GPIO_BASE_DET_A);
 		base_detect_change(BASE_DISCONNECTED);
 		CPRINTS("BD forced disconnected");
diff --git a/board/poppy/battery.c b/board/poppy/battery.c
index 3f6c4e273d..5006edf123 100644
--- a/board/poppy/battery.c
+++ b/board/poppy/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -14,14 +14,14 @@
 #include "gpio.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 static enum battery_present batt_pres_prev = BP_NOT_SURE;
 
 /* Shutdown mode parameter to write to manufacturer access register */
-#define SB_SHIP_MODE_REG	SB_MANUFACTURER_ACCESS
-#define SB_SHUTDOWN_DATA	0x0010
-#define SB_REVIVE_DATA		0x23a7
+#define SB_SHIP_MODE_REG SB_MANUFACTURER_ACCESS
+#define SB_SHUTDOWN_DATA 0x0010
+#define SB_REVIVE_DATA 0x23a7
 
 #if defined(BOARD_SORAKA) || defined(BOARD_LUX)
 static const struct battery_info info = {
@@ -86,8 +86,9 @@ static int battery_init(void)
 {
 	int batt_status;
 
-	return battery_status(&batt_status) ? 0 :
-		!!(batt_status & STATUS_INITIALIZED);
+	return battery_status(&batt_status) ?
+		       0 :
+		       !!(batt_status & STATUS_INITIALIZED);
 }
 
 /*
@@ -108,13 +109,13 @@ static int battery_check_disconnect(void)
 	uint8_t data[6];
 
 	/* Check if battery charging + discharging is disabled. */
-	rv = sb_read_mfgacc(PARAM_OPERATION_STATUS,
-			    SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data));
+	rv = sb_read_mfgacc(PARAM_OPERATION_STATUS, SB_ALT_MANUFACTURER_ACCESS,
+			    data, sizeof(data));
 	if (rv)
 		return BATTERY_DISCONNECT_ERROR;
 
-	if ((data[3] & (BATTERY_DISCHARGING_DISABLED |
-			BATTERY_CHARGING_DISABLED)) ==
+	if ((data[3] &
+	     (BATTERY_DISCHARGING_DISABLED | BATTERY_CHARGING_DISABLED)) ==
 	    (BATTERY_DISCHARGING_DISABLED | BATTERY_CHARGING_DISABLED))
 		return BATTERY_DISCONNECTED;
 
@@ -223,4 +224,3 @@ enum battery_present battery_is_present(void)
 	batt_pres_prev = battery_check_present_status();
 	return batt_pres_prev;
 }
-
diff --git a/board/poppy/board.c b/board/poppy/board.c
index e01446b316..a757515aa4 100644
--- a/board/poppy/board.c
+++ b/board/poppy/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,14 +6,13 @@
 /* Poppy board-specific configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "als.h"
 #include "bd99992gw.h"
 #include "board_config.h"
 #include "button.h"
 #include "charge_manager.h"
-#include "charge_state.h"
 #include "charge_ramp.h"
+#include "charge_state.h"
 #include "charger.h"
 #include "chipset.h"
 #include "console.h"
@@ -26,6 +25,7 @@
 #include "driver/tcpm/tcpci.h"
 #include "driver/tcpm/tcpm.h"
 #include "driver/temp_sensor/bd99992gw.h"
+#include "espi.h"
 #include "extpower.h"
 #include "gpio.h"
 #include "hooks.h"
@@ -35,6 +35,7 @@
 #include "math_util.h"
 #include "motion_lid.h"
 #include "motion_sense.h"
+#include "panic.h"
 #include "pi3usb9281.h"
 #include "power.h"
 #include "power_button.h"
@@ -51,15 +52,11 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 #include "util.h"
-#include "espi.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define USB_PD_PORT_ANX74XX	0
-
-/* Minimum input current limit. */
-#define ILIM_MIN_MA 472
+#define USB_PD_PORT_ANX74XX 0
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
@@ -81,9 +78,9 @@ static void vbus_discharge_handler(void)
 {
 	if (system_get_board_version() >= 2) {
 		pd_set_vbus_discharge(0,
-				gpio_get_level(GPIO_USB_C0_VBUS_WAKE_L));
+				      gpio_get_level(GPIO_USB_C0_VBUS_WAKE_L));
 		pd_set_vbus_discharge(1,
-				gpio_get_level(GPIO_USB_C1_VBUS_WAKE_L));
+				      gpio_get_level(GPIO_USB_C1_VBUS_WAKE_L));
 	}
 }
 DECLARE_DEFERRED(vbus_discharge_handler);
@@ -108,12 +105,12 @@ void vbus1_evt(enum gpio_signal signal)
 
 void usb0_evt(enum gpio_signal signal)
 {
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
 }
 
 void usb1_evt(enum gpio_signal signal)
 {
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12, 0);
+	usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
 }
 
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
@@ -132,7 +129,7 @@ static void anx74xx_cable_det_handler(void)
 	 * and if in normal mode, then there is no need to trigger a tcpc reset.
 	 */
 	if (cable_det && !reset_n)
-		task_set_event(TASK_ID_PD_C0, PD_EVENT_TCPC_RESET, 0);
+		task_set_event(TASK_ID_PD_C0, PD_EVENT_TCPC_RESET);
 }
 DECLARE_DEFERRED(anx74xx_cable_det_handler);
 
@@ -143,6 +140,7 @@ void anx74xx_cable_det_interrupt(enum gpio_signal signal)
 }
 #endif
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /* Hibernate wake configuration */
@@ -155,16 +153,17 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* Base detection */
-	[ADC_BASE_DET] = {"BASE_DET", NPCX_ADC_CH0,
-			  ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_BASE_DET] = { "BASE_DET", NPCX_ADC_CH0, ADC_MAX_VOLT,
+			   ADC_READ_MAX + 1, 0 },
 	/* Vbus sensing (10x voltage divider). */
-	[ADC_VBUS] = {"VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
+	[ADC_VBUS] = { "VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT * 10,
+		       ADC_READ_MAX + 1, 0 },
 	/*
 	 * Adapter current output or battery charging/discharging current (uV)
 	 * 18x amplification on charger side.
 	 */
-	[ADC_AMON_BMON] = {"AMON_BMON", NPCX_ADC_CH1, ADC_MAX_VOLT*1000/18,
-			   ADC_READ_MAX+1, 0},
+	[ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH1, ADC_MAX_VOLT * 1000 / 18,
+			    ADC_READ_MAX + 1, 0 },
 #ifdef BOARD_LUX
 	/*
 	 * ISL9238 PSYS output is 1.44 uA/W over 12.4K resistor, to read
@@ -172,19 +171,39 @@ const struct adc_t adc_channels[] = {
 	 * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we
 	 * only divide by 2 (enough to avoid precision issues).
 	 */
-	[ADC_PSYS] = {"PSYS", NPCX_ADC_CH3,
-		      ADC_MAX_VOLT*56250*2/(ADC_READ_MAX+1), 2, 0},
+	[ADC_PSYS] = { "PSYS", NPCX_ADC_CH3,
+		       ADC_MAX_VOLT * 56250 * 2 / (ADC_READ_MAX + 1), 2, 0 },
 #endif
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* I2C port map */
-const struct i2c_port_t i2c_ports[]  = {
-	{"tcpc",      NPCX_I2C_PORT0_0, 400, GPIO_I2C0_0_SCL, GPIO_I2C0_0_SDA},
-	{"als",       NPCX_I2C_PORT0_1, 400, GPIO_I2C0_1_SCL, GPIO_I2C0_1_SDA},
-	{"charger",   NPCX_I2C_PORT1,   100, GPIO_I2C1_SCL,   GPIO_I2C1_SDA},
-	{"pmic",      NPCX_I2C_PORT2,   400, GPIO_I2C2_SCL,   GPIO_I2C2_SDA},
-	{"accelgyro", NPCX_I2C_PORT3,   400, GPIO_I2C3_SCL,   GPIO_I2C3_SDA},
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "tcpc",
+	  .port = NPCX_I2C_PORT0_0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_0_SCL,
+	  .sda = GPIO_I2C0_0_SDA },
+	{ .name = "als",
+	  .port = NPCX_I2C_PORT0_1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_1_SCL,
+	  .sda = GPIO_I2C0_1_SDA },
+	{ .name = "charger",
+	  .port = NPCX_I2C_PORT1,
+	  .kbps = 100,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "pmic",
+	  .port = NPCX_I2C_PORT2,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "accelgyro",
+	  .port = NPCX_I2C_PORT3,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -202,22 +221,28 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = NPCX_I2C_PORT0_0,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
 		},
 		.drv = &ps8xxx_tcpm_drv,
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.driver = &anx74xx_tcpm_usb_mux_driver,
-		.hpd_update = &anx74xx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &anx74xx_tcpm_usb_mux_driver,
+				.hpd_update = &anx74xx_tcpc_update_hpd_status,
+			},
 	},
 	{
-		.usb_port = 1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	}
 };
 
@@ -242,7 +267,6 @@ const struct charger_config_t chg_chips[] = {
 	},
 };
 
-
 /**
  * Power on (or off) a single TCPC.
  * minimum on/off delays are included.
@@ -319,9 +343,10 @@ void board_tcpc_init(void)
 	 * HPD pulse to enable video path
 	 */
 	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		usb_mux_hpd_update(port, 0, 0);
+		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
 
 uint16_t tcpc_get_alert_status(void)
 {
@@ -341,17 +366,17 @@ uint16_t tcpc_get_alert_status(void)
 }
 
 const struct temp_sensor_t temp_sensors[] = {
-	{"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0},
+	{ "Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0 },
 
 	/* These BD99992GW temp sensors are only readable in S0 */
-	{"Ambient", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM0},
-	{"Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM1},
-	{"DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM2},
-	{"eMMC", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM3},
+	{ "Ambient", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM0 },
+	{ "Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM1 },
+	{ "DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM2 },
+	{ "eMMC", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM3 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -367,8 +392,8 @@ static void board_report_pmic_fault(const char *str)
 	uint32_t info;
 
 	/* RESETIRQ1 -- Bit 4: VRFAULT */
-	if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x8, &vrfault)
-	    != EC_SUCCESS)
+	if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x8, &vrfault) !=
+	    EC_SUCCESS)
 		return;
 
 	if (!(vrfault & BIT(4)))
@@ -477,8 +502,7 @@ static void board_pmic_enable_slp_s0_vr_decay(void)
 	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x38, 0x7a);
 }
 
-__override void power_board_handle_host_sleep_event(
-		enum host_sleep_event state)
+__override void power_board_handle_host_sleep_event(enum host_sleep_event state)
 {
 	if (state == HOST_SLEEP_EVENT_S0IX_SUSPEND)
 		board_pmic_enable_slp_s0_vr_decay();
@@ -531,9 +555,9 @@ static void board_init(void)
 		 * force detection on both ports.
 		 */
 		gpio_set_flags(GPIO_USB_C0_VBUS_WAKE_L,
-			GPIO_INPUT | GPIO_PULL_DOWN);
+			       GPIO_INPUT | GPIO_PULL_DOWN);
 		gpio_set_flags(GPIO_USB_C1_VBUS_WAKE_L,
-			GPIO_INPUT | GPIO_PULL_DOWN);
+			       GPIO_INPUT | GPIO_PULL_DOWN);
 
 		vbus0_evt(GPIO_USB_C0_VBUS_WAKE_L);
 		vbus1_evt(GPIO_USB_C1_VBUS_WAKE_L);
@@ -552,10 +576,9 @@ static void board_init(void)
 	 */
 	if (system_get_board_version() >= 5)
 		gpio_set_flags(GPIO_LED_YELLOW_C0_OLD,
-			GPIO_INPUT | GPIO_PULL_UP);
+			       GPIO_INPUT | GPIO_PULL_UP);
 	else
-		gpio_set_flags(GPIO_LED_YELLOW_C0,
-			GPIO_INPUT | GPIO_PULL_UP);
+		gpio_set_flags(GPIO_LED_YELLOW_C0, GPIO_INPUT | GPIO_PULL_UP);
 
 #ifdef BOARD_SORAKA
 	/*
@@ -564,21 +587,25 @@ static void board_init(void)
 	 * for better S0ix/S3 power
 	 */
 	if (system_get_board_version() >= 4) {
-		gpio_set_flags(GPIO_WLAN_PE_RST,
-			GPIO_INPUT | GPIO_PULL_UP);
-		gpio_set_flags(GPIO_PP3300_DX_LTE,
-			GPIO_INPUT | GPIO_PULL_UP);
-		gpio_set_flags(GPIO_LTE_GPS_OFF_L,
-			GPIO_INPUT | GPIO_PULL_UP);
-		gpio_set_flags(GPIO_LTE_BODY_SAR_L,
-			GPIO_INPUT | GPIO_PULL_UP);
-		gpio_set_flags(GPIO_LTE_WAKE_L,
-			GPIO_INPUT | GPIO_PULL_UP);
-		gpio_set_flags(GPIO_LTE_OFF_ODL,
-			GPIO_INPUT | GPIO_PULL_UP);
+		gpio_set_flags(GPIO_WLAN_PE_RST, GPIO_INPUT | GPIO_PULL_UP);
+		gpio_set_flags(GPIO_PP3300_DX_LTE, GPIO_INPUT | GPIO_PULL_UP);
+		gpio_set_flags(GPIO_LTE_GPS_OFF_L, GPIO_INPUT | GPIO_PULL_UP);
+		gpio_set_flags(GPIO_LTE_BODY_SAR_L, GPIO_INPUT | GPIO_PULL_UP);
+		gpio_set_flags(GPIO_LTE_WAKE_L, GPIO_INPUT | GPIO_PULL_UP);
+		gpio_set_flags(GPIO_LTE_OFF_ODL, GPIO_INPUT | GPIO_PULL_UP);
 	}
 #endif
 
+#ifndef BOARD_LUX
+	/*
+	 * see (b/111215677): setting the internal PU/PD of the unused pin
+	 * GPIO10 affects the ball K10 when it is selected to CR_SIN.
+	 * Disabing the WKINEN bit of GPIO10 insteading setting its PU/PD to
+	 * bypass this issue.
+	 */
+	NPCX_WKINEN(MIWU_TABLE_1, MIWU_GROUP_2) &= 0xFE;
+#endif
+
 	/* Enable Gyro interrupts */
 	gpio_enable_interrupt(GPIO_ACCELGYRO3_INT_L);
 
@@ -631,10 +658,12 @@ int board_set_active_charge_port(int charge_port)
 #endif
 		/* Make sure non-charging port is disabled */
 		gpio_set_level(charge_port ? GPIO_USB_C0_CHARGE_L :
-					     GPIO_USB_C1_CHARGE_L, 1);
+					     GPIO_USB_C1_CHARGE_L,
+			       1);
 		/* Enable charging port */
 		gpio_set_level(charge_port ? GPIO_USB_C1_CHARGE_L :
-					     GPIO_USB_C0_CHARGE_L, 0);
+					     GPIO_USB_C0_CHARGE_L,
+			       0);
 	}
 
 	return EC_SUCCESS;
@@ -648,8 +677,8 @@ int board_set_active_charge_port(int charge_port)
  * @param charge_ma     Desired charge limit (mA).
  * @param charge_mv     Negotiated charge voltage (mV).
  */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
 {
 	/* Adjust ILIM according to measurements to eliminate overshoot. */
 	charge_ma = (charge_ma - 500) * 31 / 32 + 472;
@@ -657,7 +686,7 @@ void board_set_charge_limit(int port, int supplier, int charge_ma,
 	if (charge_mv > 5000)
 		charge_ma -= 52;
 
-	charge_set_input_current_limit(MAX(charge_ma, ILIM_MIN_MA), charge_mv);
+	charge_set_input_current_limit(charge_ma, charge_mv);
 }
 
 void board_hibernate(void)
@@ -666,8 +695,7 @@ void board_hibernate(void)
 	uart_flush_output();
 
 	/* Trigger PMIC shutdown. */
-	if (i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS,
-		       0x49, 0x01)) {
+	if (i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x49, 0x01)) {
 		/*
 		 * If we can't tell the PMIC to shutdown, instead reset
 		 * and don't start the AP. Hopefully we'll be able to
@@ -723,31 +751,23 @@ static struct opt3001_drv_data_t g_opt3001_data = {
 };
 
 /* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t mag_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0,  FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t mag_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				      { 0, FLOAT_TO_FP(1), 0 },
+				      { 0, 0, FLOAT_TO_FP(-1) } };
 
 #ifdef BOARD_SORAKA
-const mat33_fp_t lid_standard_ref = {
-	{ 0,  FLOAT_TO_FP(-1),  0},
-	{FLOAT_TO_FP(1),  0,  0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+				      { FLOAT_TO_FP(1), 0, 0 },
+				      { 0, 0, FLOAT_TO_FP(1) } };
 
 /* For rev3 and older */
-const mat33_fp_t lid_standard_ref_old = {
-	{FLOAT_TO_FP(-1),  0,  0},
-	{ 0,  FLOAT_TO_FP(-1),  0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t lid_standard_ref_old = { { FLOAT_TO_FP(-1), 0, 0 },
+					  { 0, FLOAT_TO_FP(-1), 0 },
+					  { 0, 0, FLOAT_TO_FP(1) } };
 #else
-const mat33_fp_t lid_standard_ref = {
-	{FLOAT_TO_FP(-1),  0,  0},
-	{ 0,  FLOAT_TO_FP(-1),  0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				      { 0, FLOAT_TO_FP(-1), 0 },
+				      { 0, 0, FLOAT_TO_FP(1) } };
 #endif
 
 struct motion_sensor_t motion_sensors[] = {
@@ -806,7 +826,10 @@ struct motion_sensor_t motion_sensors[] = {
 	 .default_range = BIT(11), /* 16LSB / uT, fixed */
 	 .rot_standard_ref = &mag_standard_ref,
 	 .min_frequency = BMM150_MAG_MIN_FREQ,
+/* TODO(b/253292373): Remove when clang is fixed. */
+DISABLE_CLANG_WARNING("-Wshift-count-negative")
 	 .max_frequency = BMM150_MAG_MAX_FREQ(SPECIAL),
+ENABLE_CLANG_WARNING("-Wshift-count-negative")
 	},
 	[LID_ALS] = {
 	 .name = "Light",
diff --git a/board/poppy/board.h b/board/poppy/board.h
index 00effffe56..5242c1d3a8 100644
--- a/board/poppy/board.h
+++ b/board/poppy/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,7 +17,6 @@
 /* EC */
 #define CONFIG_ADC
 #define CONFIG_BACKLIGHT_LID
-#define CONFIG_BOARD_VERSION_CUSTOM
 #define CONFIG_BOARD_FORCE_RESET_PIN
 #define CONFIG_BUTTON_TRIGGERED_RECOVERY
 #define CONFIG_DETACHABLE_BASE
@@ -26,16 +25,15 @@
 #define CONFIG_DPTF_MULTI_PROFILE
 #endif
 #define CONFIG_EMULATED_SYSRQ
-#define CONFIG_FLASH_SIZE 0x80000
+#define CONFIG_FLASH_SIZE_BYTES 0x80000
 #define CONFIG_FPU
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_CONTROLLER
 #define CONFIG_LED_COMMON
 #define CONFIG_LID_SWITCH
 #define CONFIG_LOW_POWER_IDLE
 #define CONFIG_LTO
 #define CONFIG_CHIP_PANIC_BACKUP
-#define CONFIG_SOFTWARE_PANIC
 #define CONFIG_SPI_FLASH_REGS
 #define CONFIG_SPI_FLASH_W25X40
 #define CONFIG_VBOOT_HASH
@@ -64,9 +62,10 @@
 #define CONFIG_CHIPSET_SKYLAKE
 #define CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET
 #define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#define CONFIG_HOST_INTERFACE_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
+#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD
 
 /* Battery */
 #define CONFIG_BATTERY_CUT_OFF
@@ -78,7 +77,7 @@
 #ifdef BOARD_LUX
 #define CONFIG_UART_PAD_SWITCH
 
-#define CONFIG_EC_EC_COMM_MASTER
+#define CONFIG_EC_EC_COMM_CLIENT
 #define CONFIG_EC_EC_COMM_BATTERY
 #define CONFIG_CRC8
 #endif
@@ -90,8 +89,8 @@
 #define CONFIG_CHARGER
 #define CONFIG_CHARGER_ISL9238
 #define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT 512
-#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 2
+#define CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT 512
+#define CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT 472
 #define CONFIG_CHARGER_PSYS
 #define CONFIG_CHARGER_SENSE_RESISTOR 10
 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 20
@@ -102,8 +101,8 @@
 #define CONFIG_CMD_CHARGER_ADC_AMON_BMON
 #define CONFIG_HOSTCMD_PD_CONTROL
 #define CONFIG_EXTPOWER_GPIO
-#undef   CONFIG_EXTPOWER_DEBOUNCE_MS
-#define  CONFIG_EXTPOWER_DEBOUNCE_MS 1000
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
+#define CONFIG_EXTPOWER_DEBOUNCE_MS 1000
 #define CONFIG_POWER_BUTTON
 #define CONFIG_POWER_BUTTON_X86
 #define CONFIG_POWER_COMMON
@@ -120,12 +119,11 @@
 #define CONFIG_TEMP_SENSOR_BD99992GW
 #define CONFIG_THERMISTOR_NCP15WB
 
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
+#define CONFIG_MKBP_INPUT_DEVICES
 #define CONFIG_MKBP_EVENT
 #define CONFIG_MKBP_USE_HOST_EVENT
 #define CONFIG_ACCELGYRO_BMI160
 #define CONFIG_MAG_BMI_BMM150
-#define CONFIG_ACCEL_INTERRUPTS
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
 #define CONFIG_ACCELGYRO_SEC_ADDR_FLAGS BMM150_ADDR0_FLAGS
@@ -143,7 +141,7 @@
 #define CONFIG_TABLET_MODE
 #define CONFIG_TABLET_MODE_SWITCH
 
-#undef  CONFIG_UART_TX_BUF_SIZE
+#undef CONFIG_UART_TX_BUF_SIZE
 #define CONFIG_UART_TX_BUF_SIZE 2048
 
 /* USB */
@@ -174,28 +172,28 @@
 #define CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT 2
 
 /* Optional feature to configure npcx chip */
-#define NPCX_UART_MODULE2	1 /* 1:GPIO64/65 as UART */
-#define NPCX_JTAG_MODULE2	0 /* 0:GPIO21/17/16/20 as JTAG */
-#define NPCX_TACH_SEL2		0 /* 0:GPIO40/73 as TACH */
+#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART */
+#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 as JTAG */
+#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 as TACH */
 
 /* I2C ports */
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT0_0
-#define I2C_PORT_TCPC1		NPCX_I2C_PORT0_0
-#define I2C_PORT_ALS		NPCX_I2C_PORT0_1
-#define I2C_PORT_USB_CHARGER_1	NPCX_I2C_PORT0_1
-#define I2C_PORT_USB_CHARGER_0	NPCX_I2C_PORT1
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT1
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT1
-#define I2C_PORT_PMIC		NPCX_I2C_PORT2
-#define I2C_PORT_MP2949		NPCX_I2C_PORT2
-#define I2C_PORT_GYRO		NPCX_I2C_PORT3
-#define I2C_PORT_BARO		NPCX_I2C_PORT3
-#define I2C_PORT_ACCEL		I2C_PORT_GYRO
-#define I2C_PORT_THERMAL	I2C_PORT_PMIC
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0
+#define I2C_PORT_TCPC1 NPCX_I2C_PORT0_0
+#define I2C_PORT_ALS NPCX_I2C_PORT0_1
+#define I2C_PORT_USB_CHARGER_1 NPCX_I2C_PORT0_1
+#define I2C_PORT_USB_CHARGER_0 NPCX_I2C_PORT1
+#define I2C_PORT_CHARGER NPCX_I2C_PORT1
+#define I2C_PORT_BATTERY NPCX_I2C_PORT1
+#define I2C_PORT_PMIC NPCX_I2C_PORT2
+#define I2C_PORT_MP2949 NPCX_I2C_PORT2
+#define I2C_PORT_GYRO NPCX_I2C_PORT3
+#define I2C_PORT_BARO NPCX_I2C_PORT3
+#define I2C_PORT_ACCEL I2C_PORT_GYRO
+#define I2C_PORT_THERMAL I2C_PORT_PMIC
 
 /* I2C addresses */
-#define I2C_ADDR_BD99992_FLAGS	0x30
-#define I2C_ADDR_MP2949_FLAGS	0x20
+#define I2C_ADDR_BD99992_FLAGS 0x30
+#define I2C_ADDR_MP2949_FLAGS 0x20
 
 #ifndef __ASSEMBLER__
 
@@ -203,11 +201,11 @@
 #include "registers.h"
 
 enum temp_sensor_id {
-	TEMP_SENSOR_BATTERY,	/* BD99956GW TSENSE */
-	TEMP_SENSOR_AMBIENT,	/* BD99992GW SYSTHERM0 */
-	TEMP_SENSOR_CHARGER,	/* BD99992GW SYSTHERM1 */
-	TEMP_SENSOR_DRAM,	/* BD99992GW SYSTHERM2 */
-	TEMP_SENSOR_EMMC,	/* BD99992GW SYSTHERM3 */
+	TEMP_SENSOR_BATTERY, /* BD99956GW TSENSE */
+	TEMP_SENSOR_AMBIENT, /* BD99992GW SYSTHERM0 */
+	TEMP_SENSOR_CHARGER, /* BD99992GW SYSTHERM1 */
+	TEMP_SENSOR_DRAM, /* BD99992GW SYSTHERM2 */
+	TEMP_SENSOR_EMMC, /* BD99992GW SYSTHERM3 */
 	TEMP_SENSOR_COUNT
 };
 
@@ -240,17 +238,16 @@ enum adc_channel {
  * delay to turn on the power supply max is ~16ms.
  * delay to turn off the power supply max is about ~180ms.
  */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	250000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* delay to turn on/off vconn */
-#define PD_VCONN_SWAP_DELAY		5000   /* us */
 
 /* Define typical operating power and max power */
-#define PD_OPERATING_POWER_MW		15000
-#define PD_MAX_POWER_MW			45000
-#define PD_MAX_CURRENT_MA		3000
-#define PD_MAX_VOLTAGE_MV		20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 45000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Board specific handlers */
 int board_get_version(void);
diff --git a/board/poppy/build.mk b/board/poppy/build.mk
index df32a7ca8f..36c55d3048 100644
--- a/board/poppy/build.mk
+++ b/board/poppy/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/poppy/ec.tasklist b/board/poppy/ec.tasklist
index 7591137bc9..4ee0b53a32 100644
--- a/board/poppy/ec.tasklist
+++ b/board/poppy/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/poppy/gpio.inc b/board/poppy/gpio.inc
index 940d498a19..63a8d3ce99 100644
--- a/board/poppy/gpio.inc
+++ b/board/poppy/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,14 +13,14 @@ GPIO_INT(USB_C1_PD_INT_ODL,	PIN(C, 5), GPIO_INT_FALLING,			tcpc_alert_event)
 #ifdef CONFIG_POWER_S0IX
 GPIO_INT(PCH_SLP_S0_L,		PIN(7, 5), GPIO_INT_BOTH,			power_signal_interrupt)
 #endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 #ifdef BOARD_LUX
 GPIO_INT(PCH_SLP_S3_L,		PIN(2, 2), GPIO_INT_BOTH,			power_signal_interrupt)
 #else
 GPIO_INT(PCH_SLP_S3_L,		PIN(7, 3), GPIO_INT_BOTH,			power_signal_interrupt)
 #endif
-#endif /* CONFIG_HOSTCMD_ESPI_VW_SLP_S3 */
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#endif /* CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3 */
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 GPIO_INT(PCH_SLP_S4_L,		PIN(8, 6), GPIO_INT_BOTH,			power_signal_interrupt)
 #endif
 GPIO_INT(PCH_SLP_SUS_L,		PIN(6, 2), GPIO_INT_BOTH,			power_signal_interrupt)
@@ -117,7 +117,7 @@ GPIO(PPVAR_VAR_BASE,		PIN(1, 2), GPIO_OUT_LOW)
 #else
 GPIO(PP3300_DX_BASE,		PIN(1, 1), GPIO_OUT_LOW)
 GPIO(TP_EC_GPIO_07,		PIN(0, 7), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(TP_EC_GPIO_10,		PIN(1, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(TP_EC_GPIO_10,		PIN(1, 0), GPIO_INPUT)
 GPIO(TP_EC_GPIO_15,		PIN(1, 5), GPIO_INPUT | GPIO_PULL_UP)
 #endif
 
diff --git a/board/poppy/led.c b/board/poppy/led.c
index 0c2d7f1832..ea82bda490 100644
--- a/board/poppy/led.c
+++ b/board/poppy/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -31,17 +31,18 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static void side_led_set_color(int port, enum led_color color)
 {
 	int yellow_c0 = (system_get_board_version() >= 5) ?
-			GPIO_LED_YELLOW_C0 : GPIO_LED_YELLOW_C0_OLD;
+				GPIO_LED_YELLOW_C0 :
+				GPIO_LED_YELLOW_C0_OLD;
 	gpio_set_level(port ? GPIO_LED_YELLOW_C1 : yellow_c0,
-		(color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
+		       (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
 	gpio_set_level(port ? GPIO_LED_WHITE_C1 : GPIO_LED_WHITE_C0,
-		(color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF);
+		       (color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF);
 }
 
 void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
@@ -92,20 +93,20 @@ static void set_active_port_color(enum led_color color)
 static void board_led_set_battery(void)
 {
 	static int battery_ticks;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
 		/* Always indicate when charging, even in suspend. */
 		set_active_port_color(LED_AMBER);
 		break;
-	case PWR_STATE_DISCHARGE:
+	case LED_PWRS_DISCHARGE:
 		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) {
 			if (charge_get_percent() <= 10)
-				side_led_set_color(0,
-				   (battery_ticks & 0x4) ? LED_WHITE : LED_OFF);
+				side_led_set_color(0, (battery_ticks & 0x4) ?
+							      LED_WHITE :
+							      LED_OFF);
 			else
 				side_led_set_color(0, LED_OFF);
 		}
@@ -113,19 +114,19 @@ static void board_led_set_battery(void)
 		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
 			side_led_set_color(1, LED_OFF);
 		break;
-	case PWR_STATE_ERROR:
-		set_active_port_color((battery_ticks & 0x2) ?
-				LED_WHITE : LED_OFF);
+	case LED_PWRS_ERROR:
+		set_active_port_color((battery_ticks & 0x2) ? LED_WHITE :
+							      LED_OFF);
 		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
+	case LED_PWRS_CHARGE_NEAR_FULL:
 		set_active_port_color(LED_WHITE);
 		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			set_active_port_color((battery_ticks & 0x4) ?
-					LED_AMBER : LED_OFF);
-		else
-			set_active_port_color(LED_WHITE);
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		set_active_port_color(LED_WHITE);
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		set_active_port_color((battery_ticks & 0x4) ? LED_AMBER :
+							      LED_OFF);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
diff --git a/board/poppy/usb_pd_policy.c b/board/poppy/usb_pd_policy.c
index a32b77bbe7..96e13aa73b 100644
--- a/board/poppy/usb_pd_policy.c
+++ b/board/poppy/usb_pd_policy.c
@@ -1,15 +1,15 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "atomic.h"
-#include "extpower.h"
 #include "charge_manager.h"
 #include "common.h"
 #include "console.h"
 #include "driver/tcpm/anx74xx.h"
 #include "driver/tcpm/ps8xxx.h"
+#include "extpower.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "host_command.h"
@@ -17,17 +17,17 @@
 #include "system.h"
 #include "task.h"
 #include "timer.h"
-#include "util.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
+#include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT];
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5,
-							TYPEC_RP_1A5};
+static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5,
+							 TYPEC_RP_1A5 };
 
 int board_vbus_source_enabled(int port)
 {
@@ -48,8 +48,8 @@ static void board_vbus_update_source_current(int port)
 		 * is controlled by GPIO_USB_C0/1_5V_EN. Both of these signals
 		 * can remain outputs.
 		 */
-		gpio_set_level(gpio_3a_en, vbus_rp[port] == TYPEC_RP_3A0 ?
-				1 : 0);
+		gpio_set_level(gpio_3a_en,
+			       vbus_rp[port] == TYPEC_RP_3A0 ? 1 : 0);
 		gpio_set_level(gpio_5v_en, vbus_en[port]);
 	} else {
 		/*
@@ -61,8 +61,8 @@ static void board_vbus_update_source_current(int port)
 		 * 1505 mA.
 		 */
 		int flags = (vbus_rp[port] == TYPEC_RP_1A5 && vbus_en[port]) ?
-			(GPIO_INPUT | GPIO_PULL_UP) :
-			(GPIO_OUTPUT | GPIO_PULL_UP);
+				    (GPIO_INPUT | GPIO_PULL_UP) :
+				    (GPIO_OUTPUT | GPIO_PULL_UP);
 		gpio_set_level(gpio_5v_en, vbus_en[port]);
 		gpio_set_flags(gpio_5v_en, flags);
 	}
@@ -79,8 +79,7 @@ void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
 int pd_set_power_supply_ready(int port)
 {
 	/* Disable charging */
-	gpio_set_level(port ? GPIO_USB_C1_CHARGE_L :
-			      GPIO_USB_C0_CHARGE_L, 1);
+	gpio_set_level(port ? GPIO_USB_C1_CHARGE_L : GPIO_USB_C0_CHARGE_L, 1);
 
 	/* Ensure we advertise the proper available current quota */
 	charge_manager_source_port(port, 1);
@@ -131,15 +130,13 @@ int pd_check_vconn_swap(int port)
 	return gpio_get_level(GPIO_PMIC_SLP_SUS_L);
 }
 
-__override void pd_execute_data_swap(int port,
-				     enum pd_data_role data_role)
+__override void pd_execute_data_swap(int port, enum pd_data_role data_role)
 {
 	/* Only port 0 supports device mode. */
 	if (port != 0)
 		return;
 
-	gpio_set_level(GPIO_USB2_OTG_ID,
-		      (data_role == PD_ROLE_UFP) ? 1 : 0);
+	gpio_set_level(GPIO_USB2_OTG_ID, (data_role == PD_ROLE_UFP) ? 1 : 0);
 	gpio_set_level(GPIO_USB2_OTG_VBUSSENSE,
-		      (data_role == PD_ROLE_UFP) ? 1 : 0);
+		       (data_role == PD_ROLE_UFP) ? 1 : 0);
 }
diff --git a/board/poppy/vif_override.xml b/board/poppy/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/poppy/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/primus/battery.c b/board/primus/battery.c
new file mode 100644
index 0000000000..1b0d74bed3
--- /dev/null
+++ b/board/primus/battery.c
@@ -0,0 +1,211 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "common.h"
+#include "compile_time_macros.h"
+
+/*
+ * Battery info for all Primus battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	[BATTERY_SUNWODA_5B11F21946] = {
+		.fuel_gauge = {
+			.manuf_name = "Sunwoda",
+			.device_name = "LNV-5B11F21946",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0000,
+				.reg_mask = 0x6000,
+				.disconnect_val = 0x6000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13200, /* mV */
+			.voltage_normal		= 11520, /* mV */
+			.voltage_min		= 9000,  /* mV */
+			.precharge_current	= 251,	 /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 60,
+		},
+	},
+
+	[BATTERY_SUNWODA_5B11H56342] = {
+		.fuel_gauge = {
+			.manuf_name = "Sunwoda",
+			.device_name = "LNV-5B11H56342",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0000,
+				.reg_mask = 0x6000,
+				.disconnect_val = 0x6000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13200, /* mV */
+			.voltage_normal		= 11520, /* mV */
+			.voltage_min		= 9000,  /* mV */
+			.precharge_current	= 251,	 /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 60,
+		},
+	},
+
+	[BATTERY_SMP_5B11F21953] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP",
+			.device_name = "LNV-5B11F21953",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0000,
+				.reg_mask = 0x6000,
+				.disconnect_val = 0x6000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13200, /* mV */
+			.voltage_normal		= 11520, /* mV */
+			.voltage_min		= 9000,  /* mV */
+			.precharge_current	= 250,	 /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 60,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 60,
+		},
+	},
+
+	[BATTERY_SMP_5B11H56344] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP",
+			.device_name = "LNV-5B11H56344",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0000,
+				.reg_mask = 0x6000,
+				.disconnect_val = 0x6000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13200, /* mV */
+			.voltage_normal		= 11520, /* mV */
+			.voltage_min		= 9000,  /* mV */
+			.precharge_current	= 250,	 /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 60,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 60,
+		},
+	},
+
+	[BATTERY_CELXPERT_5B11F21941] = {
+		.fuel_gauge = {
+			.manuf_name = "Celxpert",
+			.device_name = "LNV-5B11F21941",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0000,
+				.reg_mask = 0x6000,
+				.disconnect_val = 0x6000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13200, /* mV */
+			.voltage_normal		= 11520, /* mV */
+			.voltage_min		= 9000,  /* mV */
+			.precharge_current	= 487,	 /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 70,
+		},
+	},
+
+	[BATTERY_CELXPERT_5B11H56343] = {
+		.fuel_gauge = {
+			.manuf_name = "Celxpert",
+			.device_name = "LNV-5B11H56343",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0000,
+				.reg_mask = 0x6000,
+				.disconnect_val = 0x6000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13200, /* mV */
+			.voltage_normal		= 11520, /* mV */
+			.voltage_min		= 9000,  /* mV */
+			.precharge_current	= 487,	 /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 70,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SUNWODA_5B11F21946;
diff --git a/board/primus/board.c b/board/primus/board.c
new file mode 100644
index 0000000000..f42e83c509
--- /dev/null
+++ b/board/primus/board.c
@@ -0,0 +1,167 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "button.h"
+#include "charge_manager.h"
+#include "charge_ramp.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "keyboard_8042_sharedlib.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "registers.h"
+#include "switch.h"
+#include "throttle_ap.h"
+#include "usbc_config.h"
+#include "util.h"
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* Console output macros */
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+
+#define KBLIGHT_LED_ON_LVL 100
+#define KBLIGHT_LED_OFF_LVL 0
+
+#define PD_MAX_SUSPEND_CURRENT_MA 3000
+
+/******************************************************************************/
+/* USB-A charging control */
+
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_PP5000_USBA_R,
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
+
+/******************************************************************************/
+
+__override void board_cbi_init(void)
+{
+	config_usb_db_type();
+}
+
+/* Called on AP S3 -> S0 transition */
+static void board_chipset_resume(void)
+{
+	/* Allow keyboard backlight to be enabled */
+	pwm_set_duty(PWM_CH_KBLIGHT, KBLIGHT_LED_ON_LVL);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S0 -> S3 transition */
+static void board_chipset_suspend(void)
+{
+	/* Turn off the keyboard backlight if it's on. */
+	pwm_set_duty(PWM_CH_KBLIGHT, KBLIGHT_LED_OFF_LVL);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
+
+#ifdef CONFIG_CHARGE_RAMP_SW
+
+/*
+ * TODO(b/181508008): tune this threshold
+ */
+
+#define BC12_MIN_VOLTAGE 4400
+
+/**
+ * Return true if VBUS is too low
+ */
+int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
+{
+	int voltage;
+
+	if (charger_get_vbus_voltage(port, &voltage))
+		voltage = 0;
+
+	if (voltage == 0) {
+		CPRINTS("%s: must be disconnected", __func__);
+		return 1;
+	}
+
+	if (voltage < BC12_MIN_VOLTAGE) {
+		CPRINTS("%s: port %d: vbus %d lower than %d", __func__, port,
+			voltage, BC12_MIN_VOLTAGE);
+		return 1;
+	}
+
+	return 0;
+}
+
+#endif /* CONFIG_CHARGE_RAMP_SW */
+
+enum battery_present battery_hw_present(void)
+{
+	enum gpio_signal batt_pres;
+
+	batt_pres = GPIO_EC_BATT_PRES_ODL;
+
+	/* The GPIO is low when the battery is physically present */
+	return gpio_get_level(batt_pres) ? BP_NO : BP_YES;
+}
+
+static void keyboard_init(void)
+{
+	/*
+	 * Set T15(KSI0/KSO11) to Lock key(KSI3/KSO9)
+	 */
+	set_scancode_set2(0, 11, get_scancode_set2(3, 9));
+}
+DECLARE_HOOK(HOOK_INIT, keyboard_init, HOOK_PRIO_DEFAULT);
+
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
+{
+	/*
+	 * Need to set different input current limit depend on system state.
+	 * Guard adapter plug/ un-plug here.
+	 */
+
+	if (((max_ma == PD_MAX_CURRENT_MA) &&
+	     chipset_in_state(CHIPSET_STATE_ANY_OFF)) ||
+	    (max_ma != PD_MAX_CURRENT_MA))
+		charge_ma = charge_ma * 97 / 100;
+	else
+		charge_ma = charge_ma * 93 / 100;
+
+	charge_set_input_current_limit(charge_ma, charge_mv);
+}
+
+static void configure_input_current_limit(void)
+{
+	/*
+	 * If adapter == 3250mA, we need system be charged at 3150mA in S5.
+	 * And system be charged at 3000mA in S0.
+	 */
+	int adapter_current_ma;
+	int adapter_current_mv;
+	/* Get adapter voltage/ current */
+	adapter_current_mv = charge_manager_get_charger_voltage();
+	adapter_current_ma = charge_manager_get_charger_current();
+
+	if ((adapter_current_ma == PD_MAX_CURRENT_MA) &&
+	    chipset_in_or_transitioning_to_state(CHIPSET_STATE_SUSPEND))
+		adapter_current_ma = PD_MAX_SUSPEND_CURRENT_MA;
+	else
+		adapter_current_ma = adapter_current_ma * 97 / 100;
+
+	charge_set_input_current_limit(adapter_current_ma, adapter_current_mv);
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, configure_input_current_limit,
+	     HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN_COMPLETE, configure_input_current_limit,
+	     HOOK_PRIO_DEFAULT);
diff --git a/board/primus/board.h b/board/primus/board.h
new file mode 100644
index 0000000000..3fb8b868c6
--- /dev/null
+++ b/board/primus/board.h
@@ -0,0 +1,230 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Primus board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "compile_time_macros.h"
+
+/* Baseboard features */
+#include "baseboard.h"
+
+/*
+ * This will happen automatically on NPCX9 ES2 and later. Do not remove
+ * until we can confirm all earlier chips are out of service.
+ */
+#define CONFIG_HIBERNATE_PSL_VCC1_RST_WAKEUP
+
+#define CONFIG_MP2964
+
+/* Sensors */
+#undef CONFIG_TABLET_MODE
+#undef CONFIG_TABLET_MODE_SWITCH
+#undef CONFIG_GMR_TABLET_MODE
+
+/* No side buttons */
+#undef CONFIG_MKBP_INPUT_DEVICES
+#undef CONFIG_VOLUME_BUTTONS
+
+/* USB Type A Features */
+#define USB_PORT_COUNT 1
+#define CONFIG_USB_PORT_POWER_DUMB
+
+/* USB Type C and USB PD defines */
+#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
+
+#undef CONFIG_USB_PD_TCPM_NCT38XX
+#define CONFIG_USB_PD_TCPM_RT1715
+#define CONFIG_USBC_RETIMER_INTEL_BB
+
+#define CONFIG_USBC_PPC_SYV682X
+
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
+
+/*
+ * Passive USB-C cables only support up to 60W.
+ */
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 65000
+#define PD_MAX_CURRENT_MA 3250
+#define PD_MAX_VOLTAGE_MV 20000
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
+
+/*
+ * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
+ * signal.
+ */
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
+
+#define GPIO_ID_1_EC_KB_BL_EN GPIO_EC_BATT_PRES_ODL
+
+/* System has back-lit keyboard */
+#define CONFIG_PWM_KBLIGHT
+
+/* Keyboard features */
+#define CONFIG_KEYBOARD_REFRESH_ROW3
+
+/* I2C Bus Configuration */
+
+#define I2C_PORT_USB_C0_TCPC NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1
+#define I2C_PORT_USB_C0_C1_PPC_BC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C0_C1_BC12 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C0_C1_RT NPCX_I2C_PORT3_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_USB_A0_A1_MIX NPCX_I2C_PORT6_1
+#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+
+#define I2C_ADDR_MP2964_FLAGS 0x20
+
+#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x56
+#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x57
+
+/* Enabling Thunderbolt-compatible mode */
+#define CONFIG_USB_PD_TBT_COMPAT_MODE
+
+/* Enabling USB4 mode */
+#define CONFIG_USB_PD_USB4
+
+/* Retimer */
+#define CONFIG_USBC_RETIMER_FW_UPDATE
+
+/* Thermal features */
+#define CONFIG_THERMISTOR
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_TEMP_SENSOR_POWER
+#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
+
+/* LED */
+#undef CONFIG_BATT_HOST_FULL_FACTOR
+#define CONFIG_BATT_HOST_FULL_FACTOR 91
+
+/* Fan features */
+#define CONFIG_CUSTOM_FAN_CONTROL
+#define CONFIG_FANS FAN_CH_COUNT
+#define RPM_DEVIATION 1
+
+/* Charger defines */
+#define CONFIG_CHARGER_BQ25720
+#define CONFIG_CHARGER_BQ25720_VSYS_TH2_CUSTOM
+#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV 70
+#define CONFIG_CHARGE_RAMP_SW
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10
+
+/* PROCHOT defines */
+#define BATT_MAX_CONTINUE_DISCHARGE_WATT 66
+
+/* Prochot assertion/deassertion ratios*/
+#define PROCHOT_ADAPTER_WATT_RATIO 97
+#define PROCHOT_ASSERTION_BATTERY_RATIO 95
+#define PROCHOT_DEASSERTION_BATTERY_RATIO 85
+#define PROCHOT_ASSERTION_PD_RATIO 105
+#define PROCHOT_DEASSERTION_PD_RATIO 100
+#define PROCHOT_DEASSERTION_PD_BATTERY_RATIO 95
+#define PROCHOT_ASSERTION_ADAPTER_RATIO 105
+#define PROCHOT_DEASSERTION_ADAPTER_RATIO 100
+#define PROCHOT_DEASSERTION_ADAPTER_BATT_RATIO 90
+
+/* PS2 defines */
+#define CONFIG_8042_AUX
+#define CONFIG_PS2
+#define CONFIG_CMD_PS2
+#define PRIMUS_PS2_CH NPCX_PS2_CH1
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h" /* needed by registers.h */
+#include "registers.h"
+#include "usbc_config.h"
+
+enum adc_channel {
+	ADC_TEMP_SENSOR_1_DDR_SOC,
+	ADC_TEMP_SENSOR_2_SSD,
+	ADC_TEMP_SENSOR_3_CHARGER,
+	ADC_TEMP_SENSOR_4_MEMORY,
+	ADC_TEMP_SENSOR_5_USBC,
+	ADC_IADPT,
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1_DDR_SOC,
+	TEMP_SENSOR_2_SSD,
+	TEMP_SENSOR_3_CHARGER,
+	TEMP_SENSOR_4_MEMORY,
+	TEMP_SENSOR_5_USBC,
+	TEMP_SENSOR_COUNT
+};
+
+enum sensor_id {
+	LID_ACCEL = 0,
+	BASE_ACCEL,
+	BASE_GYRO,
+	CLEAR_ALS,
+	RGB_ALS,
+	SENSOR_COUNT
+};
+
+enum battery_type {
+	BATTERY_SUNWODA_5B11F21946,
+	BATTERY_SUNWODA_5B11H56342,
+	BATTERY_SMP_5B11F21953,
+	BATTERY_SMP_5B11H56344,
+	BATTERY_CELXPERT_5B11F21941,
+	BATTERY_CELXPERT_5B11H56343,
+	BATTERY_TYPE_COUNT
+};
+
+enum pwm_channel {
+	PWM_CH_LED2_WHITE = 0, /* PWM0 (white charger) */
+	PWM_CH_TKP_A_LED_N, /* PWM1 (LOGO led on A cover) */
+	PWM_CH_LED1_AMBER, /* PWM2 (orange charger) */
+	PWM_CH_KBLIGHT, /* PWM3 */
+	PWM_CH_FAN, /* PWM5 */
+	PWM_CH_LED4, /* PWM7 (power) */
+	PWM_CH_COUNT
+};
+
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT };
+
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT };
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/primus/build.mk b/board/primus/build.mk
new file mode 100644
index 0000000000..409a9dd45e
--- /dev/null
+++ b/board/primus/build.mk
@@ -0,0 +1,28 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Primus board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx9
+CHIP_VARIANT:=npcx9m3f
+BASEBOARD:=brya
+
+board-y=
+board-y+=battery.o
+board-y+=board.o
+board-y+=cbi_ssfc.o
+board-y+=charger.o
+board-y+=fans.o
+board-y+=fw_config.o
+board-y+=i2c.o
+board-y+=keyboard.o
+board-y+=led.o
+board-y+=pwm.o
+board-y+=ps2.o
+board-y+=sensors.o
+board-y+=thermal.o
+board-y+=usbc_config.o
diff --git a/board/primus/cbi_ssfc.c b/board/primus/cbi_ssfc.c
new file mode 100644
index 0000000000..45afa622ab
--- /dev/null
+++ b/board/primus/cbi_ssfc.c
@@ -0,0 +1,30 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi_ssfc.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "cros_board_info.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+/* Cache SSFC on init since we don't expect it to change in runtime */
+static union primus_cbi_ssfc cached_ssfc;
+BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
+
+void board_init_ssfc(void)
+{
+	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
+		/* Default to 0 when CBI isn't populated */
+		cached_ssfc.raw_value = 0;
+
+	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
+}
+
+enum ec_ssfc_trackpoint get_cbi_ssfc_trackpoint(void)
+{
+	return cached_ssfc.trackpoint;
+}
diff --git a/board/primus/cbi_ssfc.h b/board/primus/cbi_ssfc.h
new file mode 100644
index 0000000000..fe4c2fb4e5
--- /dev/null
+++ b/board/primus/cbi_ssfc.h
@@ -0,0 +1,31 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#ifndef _PRIMUS_CBI_SSFC_H_
+#define _PRIMUS_CBI_SSFC_H_
+#include "stdint.h"
+/****************************************************************************
+ * Primus CBI Second Source Factory Cache
+ */
+/*
+ * Trackpoint (Bit 0)
+ */
+enum ec_ssfc_trackpoint {
+	SSFC_SENSOR_TRACKPOINT_ELAN = 0,
+	SSFC_SENSOR_TRACKPOINT_SYNAPTICS = 1,
+};
+union primus_cbi_ssfc {
+	struct {
+		enum ec_ssfc_trackpoint trackpoint : 2;
+		uint32_t reserved_1 : 30;
+	};
+	uint32_t raw_value;
+};
+/**
+ * Get the trackpoint type from SSFC_CONFIG.
+ *
+ * @return the Trackpoint board type.
+ */
+enum ec_ssfc_trackpoint get_cbi_ssfc_trackpoint(void);
+#endif /* _PRIMUS_CBI_SSFC_H_ */
diff --git a/board/primus/charger.c b/board/primus/charger.c
new file mode 100644
index 0000000000..827152e115
--- /dev/null
+++ b/board/primus/charger.c
@@ -0,0 +1,82 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/charger/bq25710.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+#ifndef CONFIG_ZEPHYR
+/* Charger Chip Configuration */
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = BQ25710_SMBUS_ADDR1_FLAGS,
+		.drv = &bq25710_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CHARGER_NUM);
+#endif
+
+int board_set_active_charge_port(int port)
+{
+	int is_valid_port = board_is_usb_pd_port_present(port);
+	int i;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTSUSB("Disabling all charger ports");
+
+		/* Disable all ports. */
+		for (i = 0; i < ppc_cnt; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (ppc_vbus_sink_enable(i, 0))
+				CPRINTSUSB("Disabling C%d as sink failed.", i);
+		}
+
+		return EC_SUCCESS;
+	} else if (!is_valid_port) {
+		return EC_ERROR_INVAL;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (ppc_is_sourcing_vbus(port)) {
+		CPRINTFUSB("Skip enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTSUSB("New charge port: C%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < ppc_cnt; i++) {
+		if (i == port)
+			continue;
+
+		if (ppc_vbus_sink_enable(i, 0))
+			CPRINTSUSB("C%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTSUSB("C%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/board/primus/ec.tasklist b/board/primus/ec.tasklist
new file mode 100644
index 0000000000..3afcca805e
--- /dev/null
+++ b/board/primus/ec.tasklist
@@ -0,0 +1,31 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ *
+ * USB_CHG_Px tasks must be contiguous (see USB_CHG_PORT_TO_TASK_ID(x)).
+ * PD_Cx tasks must be contiguous (see PD_PORT_TO_TASK_ID(x))
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, HOOKS_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, BASEBOARD_CHG_RAMP_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, BASEBOARD_CHARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, BASEBOARD_CHIPSET_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, CONSOLE_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, BASEBOARD_POWERBTN_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, BASEBOARD_PD_INT_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, BASEBOARD_PD_INT_TASK_STACK_SIZE) \
+	TASK_NOTEST(PROCHOT, prochot_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(LOGOLED, logoled_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/primus/fans.c b/board/primus/fans.c
new file mode 100644
index 0000000000..b109fcf5da
--- /dev/null
+++ b/board/primus/fans.c
@@ -0,0 +1,85 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Physical fans. These are logically separate from pwm_channels. */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "fan.h"
+#include "fan_chip.h"
+#include "hooks.h"
+#include "pwm.h"
+
+/* MFT channels. These are logically separate from pwm_channels. */
+const struct mft_t mft_channels[] = {
+	[MFT_CH_0] = {
+		.module = NPCX_MFT_MODULE_1,
+		.clk_src = TCKC_LFCLK,
+		.pwm_id = PWM_CH_FAN,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
+
+static const struct fan_conf fan_conf_0 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
+	.pgood_gpio = -1,
+	.enable_gpio = GPIO_EN_PP5000_FAN,
+};
+
+/*
+ * Set maximum rpm at 4800/ minimum rpm at 1800.
+ */
+static const struct fan_rpm fan_rpm_0 = {
+	.rpm_min = 1800,
+	.rpm_start = 1800,
+	.rpm_max = 4800,
+};
+
+const struct fan_t fans[FAN_CH_COUNT] = {
+	[FAN_CH_0] = {
+		.conf = &fan_conf_0,
+		.rpm = &fan_rpm_0,
+	},
+};
+
+#ifndef CONFIG_FANS
+
+/*
+ * TODO(b/181271666): use static fan speeds until fan and sensors are
+ * tuned. for now, use:
+ *
+ *   AP off:  33%
+ *   AP  on: 100%
+ */
+
+static void fan_slow(void)
+{
+	const int duty_pct = 33;
+
+	ccprints("%s: speed %d%%", __func__, duty_pct);
+
+	pwm_enable(PWM_CH_FAN, 1);
+	pwm_set_duty(PWM_CH_FAN, duty_pct);
+}
+
+static void fan_max(void)
+{
+	const int duty_pct = 100;
+
+	ccprints("%s: speed %d%%", __func__, duty_pct);
+
+	pwm_enable(PWM_CH_FAN, 1);
+	pwm_set_duty(PWM_CH_FAN, duty_pct);
+}
+
+DECLARE_HOOK(HOOK_INIT, fan_slow, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, fan_slow, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, fan_slow, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_RESET, fan_max, HOOK_PRIO_FIRST);
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, fan_max, HOOK_PRIO_DEFAULT);
+
+#endif /* CONFIG_FANS */
diff --git a/board/primus/fw_config.c b/board/primus/fw_config.c
new file mode 100644
index 0000000000..82ba396901
--- /dev/null
+++ b/board/primus/fw_config.c
@@ -0,0 +1,65 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "fw_config.h"
+
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
+
+static union primus_cbi_fw_config fw_config;
+BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
+
+/*
+ * FW_CONFIG defaults for primus if the CBI.FW_CONFIG data is not
+ * initialized.
+ */
+static const union primus_cbi_fw_config fw_config_defaults = {
+	.usb_db = DB_USB3_PS8815,
+	.kb_bl = KEYBOARD_BACKLIGHT_ENABLED,
+};
+
+/****************************************************************************
+ * Primus FW_CONFIG access
+ */
+void board_init_fw_config(void)
+{
+	if (cbi_get_fw_config(&fw_config.raw_value)) {
+		CPRINTS("CBI: Read FW_CONFIG failed, using board defaults");
+		fw_config = fw_config_defaults;
+	}
+
+	if (get_board_id() == 0) {
+		/*
+		 * Early boards have a zero'd out FW_CONFIG, so replace
+		 * it with a sensible default value. If DB_USB_ABSENT2
+		 * was used as an alternate encoding of DB_USB_ABSENT to
+		 * avoid the zero check, then fix it.
+		 */
+		if (fw_config.raw_value == 0) {
+			CPRINTS("CBI: FW_CONFIG is zero, using board defaults");
+			fw_config = fw_config_defaults;
+		} else if (fw_config.usb_db == DB_USB_ABSENT2) {
+			fw_config.usb_db = DB_USB_ABSENT;
+		}
+	}
+}
+
+union primus_cbi_fw_config get_fw_config(void)
+{
+	return fw_config;
+}
+
+enum ec_cfg_mlb_usb ec_cfg_mlb_usb(void)
+{
+	return fw_config.mlb_usb;
+}
+
+enum ec_cfg_usb_db_type ec_cfg_usb_db_type(void)
+{
+	return fw_config.usb_db;
+}
diff --git a/board/primus/fw_config.h b/board/primus/fw_config.h
new file mode 100644
index 0000000000..81fa5481f8
--- /dev/null
+++ b/board/primus/fw_config.h
@@ -0,0 +1,65 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __BOARD_PRIMUS_FW_CONFIG_H_
+#define __BOARD_PRIMUS_FW_CONFIG_H_
+
+#include <stdint.h>
+
+/****************************************************************************
+ * CBI FW_CONFIG layout for Primus board.
+ *
+ * Source of truth is the project/brya/primus/config.star configuration file.
+ */
+
+enum ec_cfg_usb_db_type {
+	DB_USB_ABSENT = 0,
+	DB_USB3_PS8815 = 1,
+	DB_USB_ABSENT2 = 15
+};
+
+enum ec_cfg_keyboard_backlight_type {
+	KEYBOARD_BACKLIGHT_DISABLED = 0,
+	KEYBOARD_BACKLIGHT_ENABLED = 1
+};
+
+enum ec_cfg_mlb_usb { MLB_USB_TBT = 0, MLB_USB_USB4 = 1 };
+
+union primus_cbi_fw_config {
+	struct {
+		enum ec_cfg_usb_db_type usb_db : 4;
+		uint32_t sd_db : 2;
+		uint32_t reserved_0 : 1;
+		enum ec_cfg_keyboard_backlight_type kb_bl : 1;
+		uint32_t audio : 3;
+		uint32_t cellular_db : 2;
+		enum ec_cfg_mlb_usb mlb_usb : 1;
+		uint32_t reserved_1 : 18;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Read the cached FW_CONFIG.  Guaranteed to have valid values.
+ *
+ * @return the FW_CONFIG for the board.
+ */
+union primus_cbi_fw_config get_fw_config(void);
+
+/**
+ * Get MLB USB type from FW_CONFIG.
+ *
+ * @return the MLB USB type.
+ */
+enum ec_cfg_mlb_usb ec_cfg_mlb_usb(void);
+
+/**
+ * Get the USB daughter board type from FW_CONFIG.
+ *
+ * @return the USB daughter board type.
+ */
+enum ec_cfg_usb_db_type ec_cfg_usb_db_type(void);
+
+#endif /* __BOARD_PRIMUS_FW_CONFIG_H_ */
diff --git a/board/primus/gpio.inc b/board/primus/gpio.inc
new file mode 100644
index 0000000000..9928eb0cc5
--- /dev/null
+++ b/board/primus/gpio.inc
@@ -0,0 +1,136 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define MODULE_KB		MODULE_KEYBOARD_SCAN
+
+/* INTERRUPT GPIOs: */
+GPIO_INT(ACOK_OD,                        PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
+GPIO_INT(EC_PROCHOT_IN_L,                PIN(A, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
+GPIO_INT(EC_WP_ODL,                      PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(GSC_EC_PWR_BTN_ODL,             PIN(0, 1), GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW, power_button_interrupt)
+GPIO_INT(LID_OPEN,                       PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
+GPIO_INT(SEQ_EC_ALL_SYS_PG,              PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_DSW_PWROK,               PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_RSMRST_ODL,              PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,                       PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,                      PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SYS_SLP_S0IX_L,                 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(USB_C0_BC12_INT_ODL,            PIN(C, 6), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C0_TCPC_INT_ODL,            PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C0_RT_INT_ODL,              PIN(B, 1), GPIO_INT_FALLING, retimer_interrupt)
+GPIO_INT(USB_C0_PPC_INT_ODL,             PIN(F, 5), GPIO_INT_FALLING, ppc_interrupt)
+/* USB C1 gpio pins are mapped to schematic USB C2 */
+GPIO_INT(USB_C1_TCPC_INT_ODL,            PIN(A, 2), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C1_BC12_INT_ODL,            PIN(0, 2), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C1_PPC_INT_ODL,             PIN(7, 0), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C1_RT_INT_ODL,              PIN(9, 7), GPIO_INT_FALLING, retimer_interrupt)
+
+/* USED GPIOs: */
+GPIO(CCD_MODE_ODL,                   PIN(E, 5), GPIO_INPUT)
+GPIO(CHARGER_VAP_OTG_EN,             PIN(7, 3), GPIO_OUT_LOW)
+GPIO(CPU_C10_GATE_L,                 PIN(6, 7), GPIO_INPUT)
+GPIO(EC_BATT_PRES_ODL,               PIN(E, 1), GPIO_INPUT)
+GPIO(KBD_BL_DTCT_N,                  PIN(A, 3), GPIO_INPUT)
+GPIO(EC_ENTERING_RW,                 PIN(0, 3), GPIO_OUT_LOW)
+GPIO(EC_EN_EDP_BL,                   PIN(D, 3), GPIO_OUT_HIGH)
+GPIO(EC_GSC_PACKET_MODE,             PIN(7, 5), GPIO_OUT_LOW)
+GPIO(EC_I2C_BAT_SCL,                 PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_BAT_SDA,                 PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SCL_R,              PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SDA_R,              PIN(B, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C1_PPC_BC_SCL,    PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C1_PPC_BC_SDA,    PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C1_RT_SCL,        PIN(D, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C1_RT_SDA,        PIN(D, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_TCPC_SCL,         PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_TCPC_SDA,         PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_USB_A0_A1_MIX_SCL,       PIN(E, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_A0_A1_MIX_SDA,       PIN(E, 3), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_TCPC_SCL,         PIN(F, 3), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_TCPC_SDA,         PIN(F, 2), GPIO_INPUT)
+GPIO(EC_PCHHOT_ODL,                  PIN(7, 4), GPIO_INPUT)
+GPIO(EC_PCH_INT_ODL,                 PIN(B, 0), GPIO_ODR_HIGH)
+GPIO(EC_PCH_PWR_BTN_ODL,             PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(EC_PCH_RSMRST_L,                PIN(A, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_RTCRST,                  PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_SYS_PWROK,               PIN(3, 7), GPIO_OUT_LOW)
+GPIO(EC_PCH_WAKE_R_ODL,              PIN(C, 0), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_ODL,                 PIN(5, 7), GPIO_ODR_HIGH)
+GPIO(EN_PP5000_FAN,                  PIN(6, 1), GPIO_OUT_HIGH)
+GPIO(EN_PP5000_USBA_R,               PIN(D, 7), GPIO_OUT_LOW)
+GPIO(EN_S5_RAILS,                    PIN(B, 6), GPIO_OUT_LOW)
+GPIO(IMVP9_VRRDY_OD,                 PIN(9, 5), GPIO_INPUT)
+GPIO(PCH_PWROK,                      PIN(7, 2), GPIO_OUT_LOW)
+GPIO(SYS_RST_ODL,                    PIN(C, 5), GPIO_ODR_HIGH)
+GPIO(USB_C0_RT_RST_ODL,              PIN(A, 7), GPIO_ODR_LOW)
+GPIO(PDEV_STP_N,                     PIN(9, 6), GPIO_ODR_HIGH)
+GPIO(VCCST_PWRGD_OD,                 PIN(A, 4), GPIO_ODR_LOW)
+GPIO(USB_C1_RT_RST_ODL,              PIN(5, 0), GPIO_ODR_LOW)
+GPIO(USB_C0_FRS_EN,                  PIN(8, 3), GPIO_OUT_LOW)
+GPIO(USB_A_LOW_PWR_OD,               PIN(B, 5), GPIO_ODR_LOW)
+GPIO(TBT_PWR_EN,                     PIN(D, 4), GPIO_OUT_LOW)
+GPIO(TP4_RESET,                      PIN(9, 3), GPIO_ODR_LOW)
+GPIO(USB_C1_FRS_EN,                  PIN(9, 4), GPIO_OUT_LOW)
+GPIO(FAN_ID,                         PIN(4, 1), GPIO_INPUT)
+GPIO(USB_C0_OC_ODL,                  PIN(5, 6), GPIO_ODR_HIGH)
+GPIO(USB_C1_OC_ODL,                  PIN(B, 4), GPIO_ODR_HIGH)
+GPIO(EC_PS2_SCL_TPAD,                PIN(6, 2), GPIO_ODR_LOW)
+GPIO(EC_PS2_SDA_TPAD,                PIN(6, 3), GPIO_ODR_LOW)
+
+/* UART alternate functions */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)              /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */
+
+/* I2C alternate functions */
+ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)               /* GPIO33/I2C5_SCL0/CTS_L, GPIO36/RTS_L/I2C5_SDA0 */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)               /* GPIO87/I2C1_SDA0 */
+ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)               /* GPIO92/I2C2_SCL0, GPIO91/I2C2_SDA0, GPIO90/I2C1_SCL0 */
+ALTERNATE(PIN_MASK(B, 0x0c), 0, MODULE_I2C, 0)               /* GPIOB3/I2C7_SCL0/DCD_L, GPIOB2/I2C7_SDA0/DSR_L */
+ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)               /* GPIOD1/I2C3_SCL0, GPIOD0/I2C3_SDA0 */
+ALTERNATE(PIN_MASK(E, 0x18), 0, MODULE_I2C, 0)               /* GPIOE4/I2C6_SCL1/I3C_SCL, GPIOE3/I2C6_SDA1/I3C_SDA */
+ALTERNATE(PIN_MASK(F, 0x0c), 0, MODULE_I2C, 0)               /* GPIOF3/I2C4_SCL1, GPIOF2/I2C4_SDA1 */
+
+/* PWM alternate functions */
+ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0)               /* GPIO40/TA1 */
+ALTERNATE(PIN_MASK(6, 0x01), 0, MODULE_PWM, 0)               /* GPIO60/PWM7 */
+ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)               /* GPIO80/PWM3 */
+ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)               /* GPIOB7/PWM5 */
+ALTERNATE(PIN_MASK(C, 0x1c), 0, MODULE_PWM, 0)               /* GPIOC4/PWM2, GPIOC3/PWM0, GPIOC2/PWM1/I2C6_SCL0 */
+
+/* ADC alternate functions */
+ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0)               /* GPIO34/PS2_DAT2/ADC6 */
+ALTERNATE(PIN_MASK(4, 0x3C), 0, MODULE_ADC, 0)               /* GPIO45/ADC0, GPIO44/ADC1, GPIO43/ADC2, GPIO42/ADC3/RI_L */
+ALTERNATE(PIN_MASK(F, 0x01), 0, MODULE_ADC, 0)               /* GPIOF0/ADC9 */
+
+/* KB alternate functions */
+ALTERNATE(PIN_MASK(0, 0xf0), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO10&P80_CLK/GPIO07, KSO11&P80_DAT/GPIO06, KSO12/GPIO05, KSO13/GPIO04 */
+ALTERNATE(PIN_MASK(1, 0x7f), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO06/GPO13/GP_SEL_L, KSO07/GPO12/JEN_L, KSO03/GPIO16/JTAG_TDO0_SWO, KSO04/GPIO15/XNOR, KSO05/GPIO14, KSO08/GPIO11/CR_SOUT1, KSO09/GPIO10/CR_SIN1 */
+ALTERNATE(PIN_MASK(2, 0xfc), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI2/GPIO27/TRACEDATA1, KSI3/GPIO26/TRACEDATA0, KSI4/GPIO25/TRACECLK/GP_SCLK, KSI5/GPIO24/GP_MISO, KSI6/GPIO23/S_SBUB, KSI7/GPIO22/S_SBUA */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO00/GPIO21/JTAG_TCK_SWCLK, KSO01/GPIO20/JTAG_TMS_SWIO */
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI0/GPIO31/TRACEDATA3/GP_MOSI, KSI1/GPIO30/TRACEDATA2/GP_CS_L */
+ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO14/GPIO82 */
+
+/* PMU alternate functions */
+ALTERNATE(PIN_MASK(0, 0x01), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN2_L&GPI00/GPIO00 */
+ALTERNATE(PIN_MASK(0, 0x02), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW) /* GPIO01/PSL_IN3_L&GPI01 */
+ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN1_L&GPID2/GPIOD2 */
+
+/* Unused Pins */
+UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
+UNUSED(PIN(8, 1))       /* GPIO81/PECI_DATA */
+UNUSED(PIN(3, 2))       /* GPO32/TRIS# */
+UNUSED(PIN(3, 5))       /* GPO35/CR_SOUT4/TEST# */
+UNUSED(PIN(6, 6))       /* GPO66/ARM#_X86 */
+UNUSED(PIN(8, 6))       /* GPIO86/TXD/CR_SOUT2 */
+/* Pre-configured PSL balls:  J8  K6 */
+
+
+/*
+ * The NPCX keyboard driver does not use named GPIOs to access
+ * keyboard scan pins, so we do not list them in *gpio.inc. However, when
+ * KEYBOARD_COL2_INVERTED is defined, this name is required.
+ */
+GPIO(EC_KSO_02_INV,               PIN(1, 7), GPIO_OUT_LOW)
diff --git a/board/primus/i2c.c b/board/primus/i2c.c
new file mode 100644
index 0000000000..02892af19d
--- /dev/null
+++ b/board/primus/i2c.c
@@ -0,0 +1,75 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "i2c.h"
+
+/* I2C port map configuration */
+const struct i2c_port_t i2c_ports[] = {
+	{
+		/* I2C1
+		 * TODO(b/191178381) Need to check the signals with a scope
+		 * before raising to 1MHz.
+		 */
+		.name = "tcpc0",
+		.port = I2C_PORT_USB_C0_TCPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_TCPC_SDA,
+	},
+	{
+		/* I2C2 */
+		.name = "ppc0,1",
+		.port = I2C_PORT_USB_C0_C1_PPC_BC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C1_PPC_BC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C1_PPC_BC_SDA,
+	},
+	{
+		/* I2C3 */
+		.name = "retimer0,2",
+		.port = I2C_PORT_USB_C0_C1_RT,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C1_RT_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C1_RT_SDA,
+	},
+	{
+		/* I2C4
+		 * TODO(b/191178381) Need to check the signals with a scope
+		 * before raising to 1MHz.
+		 */
+		.name = "tcpc1",
+		.port = I2C_PORT_USB_C1_TCPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C1_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C1_TCPC_SDA,
+	},
+	{
+		/* I2C5 */
+		.name = "battery",
+		.port = I2C_PORT_BATTERY,
+		.kbps = 100,
+		.scl = GPIO_EC_I2C_BAT_SCL,
+		.sda = GPIO_EC_I2C_BAT_SDA,
+	},
+	{
+		/* I2C6 */
+		.name = "usb_mix0,1",
+		.port = I2C_PORT_USB_A0_A1_MIX,
+		.kbps = 100,
+		.scl = GPIO_EC_I2C_USB_A0_A1_MIX_SCL,
+		.sda = GPIO_EC_I2C_USB_A0_A1_MIX_SDA,
+	},
+	{
+		/* I2C7 */
+		.name = "eeprom",
+		.port = I2C_PORT_EEPROM,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_MISC_SCL_R,
+		.sda = GPIO_EC_I2C_MISC_SDA_R,
+	},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/board/primus/keyboard.c b/board/primus/keyboard.c
new file mode 100644
index 0000000000..9c9a37e9fc
--- /dev/null
+++ b/board/primus/keyboard.c
@@ -0,0 +1,52 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "ec_commands.h"
+#include "keyboard_scan.h"
+#include "timer.h"
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/* Increase from 50 us, because KSO_02 passes through the H1. */
+	.output_settle_us = 80,
+	/* Other values should be the same as the default configuration. */
+	.debounce_down_us = 9 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x1c, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
+		0xa4, 0xff, 0xfe, 0x55, 0xfb, 0xca  /* full set */
+	},
+};
+
+static const struct ec_response_keybd_config primus_kb = {
+	.num_top_row_keys = 14,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_PREV_TRACK,		/* T8 */
+		TK_PLAY_PAUSE,		/* T9 */
+		TK_NEXT_TRACK,		/* T10 */
+		TK_MICMUTE,		/* T11 */
+		TK_VOL_MUTE,		/* T12 */
+		TK_VOL_DOWN,		/* T13 */
+		TK_VOL_UP,		/* T14 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &primus_kb;
+}
diff --git a/board/primus/led.c b/board/primus/led.c
new file mode 100644
index 0000000000..8d4083558f
--- /dev/null
+++ b/board/primus/led.c
@@ -0,0 +1,236 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Primus specific PWM LED settings. */
+
+#include "battery.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "chipset.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "extpower.h"
+#include "hooks.h"
+#include "led_common.h"
+#include "power.h"
+#include "pwm.h"
+#include "task.h"
+#include "timer.h"
+#include "util.h"
+
+#include <stdint.h>
+#define CPRINTS(format, args...) cprints(CC_LOGOLED, format, ##args)
+
+#define LED_ON_LVL 100
+#define LED_OFF_LVL 0
+#define LED_BAT_S3_OFF_TIME_MS 3000
+#define LED_BAT_S3_TICK_MS 50
+#define LED_BAT_S3_PWM_RESCALE 5
+#define LED_TOTAL_TICKS 6
+#define TICKS_STEP1_BRIGHTER 0
+#define TICKS_STEP2_DIMMER (1000 / LED_BAT_S3_TICK_MS)
+#define TICKS_STEP3_OFF (2 * TICKS_STEP2_DIMMER)
+#define LED_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS)
+#define LED_LOGO_TICK_SEC (LED_ONE_SEC / 4)
+/* Total on/off duration in a period */
+#define PERIOD (LED_LOGO_TICK_SEC * 2)
+#define LED_ON 1
+#define LED_OFF EC_LED_COLOR_COUNT
+#define LED_EVENT_SUSPEND TASK_EVENT_CUSTOM_BIT(0)
+#define LED_EVENT_200MS_TICK TASK_EVENT_CUSTOM_BIT(1)
+
+static int tick;
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+static void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_AMBER:
+		pwm_set_duty(PWM_CH_LED1_AMBER, LED_ON_LVL);
+		pwm_set_duty(PWM_CH_LED2_WHITE, LED_OFF_LVL);
+		break;
+	case EC_LED_COLOR_WHITE:
+		pwm_set_duty(PWM_CH_LED2_WHITE, LED_ON_LVL);
+		pwm_set_duty(PWM_CH_LED1_AMBER, LED_OFF_LVL);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		pwm_set_duty(PWM_CH_LED1_AMBER, LED_OFF_LVL);
+		pwm_set_duty(PWM_CH_LED2_WHITE, LED_OFF_LVL);
+		break;
+	}
+}
+
+static void led_set_battery(void)
+{
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
+		/* Always indicate when charging, even in suspend. */
+		led_set_color_battery(EC_LED_COLOR_AMBER);
+		break;
+	case LED_PWRS_DISCHARGE:
+		led_set_color_battery(LED_OFF);
+		break;
+	case LED_PWRS_CHARGE_NEAR_FULL:
+		led_set_color_battery(EC_LED_COLOR_WHITE);
+		break;
+	default:
+		/* Other states don't alter LED behavior */
+		break;
+	}
+}
+
+void led_set_color_power(int onoff_status)
+{
+	/* primus logo led and power led have same behavior. */
+	if (onoff_status == LED_ON) {
+		pwm_set_duty(PWM_CH_TKP_A_LED_N, LED_ON_LVL);
+		pwm_set_duty(PWM_CH_LED4, LED_ON_LVL);
+	} else {
+		/* LED_OFF and unsupported colors */
+		pwm_set_duty(PWM_CH_TKP_A_LED_N, LED_OFF_LVL);
+		pwm_set_duty(PWM_CH_LED4, LED_OFF_LVL);
+	}
+}
+
+#define AC_DISCONNECTED (-1)
+
+static void led_set_power(void)
+{
+	static int plug_ac_countdown;
+	static int ticks;
+
+	if (plug_ac_countdown > 0) {
+		ticks = (ticks + 1) % PERIOD;
+		plug_ac_countdown--;
+		if (ticks < LED_LOGO_TICK_SEC)
+			led_set_color_power(LED_OFF);
+		else
+			led_set_color_power(LED_ON);
+	} else if (chipset_in_state(CHIPSET_STATE_ON))
+		led_set_color_power(LED_ON);
+	else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		led_set_color_power(LED_OFF);
+
+	/* Check AC_PRESENT */
+	if (!extpower_is_present())
+		plug_ac_countdown = AC_DISCONNECTED;
+	else if (plug_ac_countdown == AC_DISCONNECTED)
+		/* AC power was plugged in (previous state was "disconnected"),
+		 * set plug_ac_countdown for amount of ticks left
+		 */
+		plug_ac_countdown = LED_TOTAL_TICKS;
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		brightness_range[EC_LED_COLOR_RED] = 1;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(EC_LED_COLOR_AMBER);
+		else if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_battery(EC_LED_COLOR_WHITE);
+		else
+			led_set_color_battery(LED_OFF);
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		if (brightness[EC_LED_COLOR_RED] != 0)
+			led_set_color_power(LED_ON);
+		else
+			led_set_color_power(LED_OFF);
+	}
+
+	return EC_SUCCESS;
+}
+
+/* Called by hook task every 200 ms */
+static void led_tick(void)
+{
+	task_set_event(TASK_ID_LOGOLED, LED_EVENT_200MS_TICK);
+}
+DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
+
+static void suspend_led_update(void)
+{
+	while (1) {
+		tick++;
+
+		/* HOOK_CHIPSET_SUSPEND will be called when POWER_S0S0ix,
+		 * if we are not transitioning to suspend, we should break here.
+		 */
+		if (!chipset_in_or_transitioning_to_state(
+			    CHIPSET_STATE_ANY_SUSPEND))
+			break;
+
+		/* 1s gradual on, 1s gradual off, 3s off */
+		if (tick <= TICKS_STEP2_DIMMER) {
+			/* increase 5 duty every 50ms until PWM=100
+			 * enter here 20 times, total duartion is 1sec
+			 * A-cover and power button led are shared same
+			 * behavior.
+			 */
+			pwm_set_duty(PWM_CH_TKP_A_LED_N,
+				     tick * LED_BAT_S3_PWM_RESCALE);
+			pwm_set_duty(PWM_CH_LED4,
+				     tick * LED_BAT_S3_PWM_RESCALE);
+			msleep(LED_BAT_S3_TICK_MS);
+		} else if (tick <= TICKS_STEP3_OFF) {
+			/* decrease 5 duty every 50ms until PWM=0
+			 * enter here 20 times, total duartion is 1sec
+			 * A-cover and power button led are shared same
+			 * behavior.
+			 */
+			pwm_set_duty(PWM_CH_TKP_A_LED_N,
+				     (TICKS_STEP3_OFF - tick) *
+					     LED_BAT_S3_PWM_RESCALE);
+			pwm_set_duty(PWM_CH_LED4,
+				     (TICKS_STEP3_OFF - tick) *
+					     LED_BAT_S3_PWM_RESCALE);
+			msleep(LED_BAT_S3_TICK_MS);
+		} else {
+			tick = TICKS_STEP1_BRIGHTER;
+			msleep(LED_BAT_S3_OFF_TIME_MS);
+		}
+	}
+}
+
+static void suspend_led_init(void)
+{
+	task_set_event(TASK_ID_LOGOLED, LED_EVENT_SUSPEND);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, suspend_led_init, HOOK_PRIO_DEFAULT);
+
+void logoled_task(void *u)
+{
+	uint32_t evt;
+
+	while (1) {
+		evt = task_wait_event(-1);
+
+		if (evt & LED_EVENT_SUSPEND) {
+			tick = TICKS_STEP2_DIMMER;
+			suspend_led_update();
+		}
+
+		if (evt & LED_EVENT_200MS_TICK) {
+			if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+				led_set_power();
+			if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
+				led_set_battery();
+		}
+	}
+}
diff --git a/board/primus/ps2.c b/board/primus/ps2.c
new file mode 100644
index 0000000000..685c036fc2
--- /dev/null
+++ b/board/primus/ps2.c
@@ -0,0 +1,163 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi_ssfc.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "keyboard_8042.h"
+#include "ps2.h"
+#include "ps2_chip.h"
+#include "registers.h"
+#include "time.h"
+
+#include <stddef.h>
+#include <string.h>
+
+#define PS2_TRANSMIT_DELAY_MS 10
+
+static uint8_t queue_data[3];
+static int data_count;
+
+void send_aux_data_to_device(uint8_t data)
+{
+	ps2_transmit_byte(PRIMUS_PS2_CH, data);
+}
+
+static void board_init(void)
+{
+	ps2_enable_channel(PRIMUS_PS2_CH, 1, send_aux_data_to_host_interrupt);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+/*
+ * Goodix touchpad AVDD need to pull low to 0V when poweroff.
+ * Setting PS2 module in GPIO.inc will let AVDD have 0.9V offset.
+ * So we need to enable PS2 module later than PLTRST# to avoid the 0.9V
+ * offset.
+ */
+static void enable_ps2(void)
+{
+	gpio_set_alternate_function(GPIO_PORT_6, BIT(2) | BIT(3),
+				    GPIO_ALT_FUNC_DEFAULT);
+}
+DECLARE_DEFERRED(enable_ps2);
+
+static void disable_ps2(void)
+{
+	gpio_set_flags(GPIO_EC_PS2_SCL_TPAD, GPIO_ODR_LOW);
+	gpio_set_flags(GPIO_EC_PS2_SDA_TPAD, GPIO_ODR_LOW);
+	gpio_set_alternate_function(GPIO_PORT_6, BIT(2) | BIT(3),
+				    GPIO_ALT_FUNC_NONE);
+	/* make sure PLTRST# goes high and re-enable PS2.*/
+	hook_call_deferred(&enable_ps2_data, 2 * SECOND);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESET, disable_ps2, HOOK_PRIO_DEFAULT);
+
+static void ps2_transmit(uint8_t cmd)
+{
+	ps2_transmit_byte(PRIMUS_PS2_CH, cmd);
+	msleep(PS2_TRANSMIT_DELAY_MS);
+}
+
+/* Process the PS2 data at here */
+void get_ps2_data(uint8_t data)
+{
+	/* receive the PS2 data and save in PS2 queue */
+	queue_data[data_count++] = data;
+}
+
+static void send_command_to_trackpoint(uint8_t command1, uint8_t command2)
+{
+	/*
+	 * Send command to trackpoint and wait,
+	 * this will make sure EC get ACK from PS2 device
+	 * and send the next command.
+	 */
+
+	ps2_transmit(TP_COMMAND);
+	ps2_transmit(TP_TOGGLE);
+	ps2_transmit(command1);
+	ps2_transmit(command2);
+}
+
+uint8_t get_trackpoint_id(void)
+{
+	/*
+	 * Three data will be received when asking PS2
+	 * device id.
+	 */
+	ps2_transmit(TP_READ_ID);
+
+	/*
+	 * When EC send TP_READ_ID, trackpoint will return ACK(0xFA),
+	 * and then return device ID. So return the second data.
+	 * Also make sure only return the trackpoint device ID.
+	 */
+	if (queue_data[1] == TP_VARIANT_ELAN ||
+	    queue_data[1] == TP_VARIANT_SYNAPTICS)
+		return queue_data[1];
+	else
+		return 0;
+}
+
+/* Called on AP S0 -> S0ix transition */
+static void ps2_suspend(void)
+{
+	uint8_t trackpoint_id;
+	/*
+	 * When EC send PS2 command to PS2 device,
+	 * PS2 device will return ACK(0xFA).
+	 * EC will send it to host and cause host wake from suspend.
+	 * So disable EC send data to host to avoid it.
+	 *
+	 * In order to receive the PS2 data and also not to wake host,
+	 * use get_ps2_data to process PS2 data.
+	 */
+	ps2_enable_channel(PRIMUS_PS2_CH, 1, get_ps2_data);
+	trackpoint_id = get_trackpoint_id();
+	/*
+	 * Don't need to read any data from PS2 device now,
+	 * so disable it.
+	 */
+	ps2_enable_channel(PRIMUS_PS2_CH, 1, NULL);
+
+	/*
+	 * Send suspend mode to trackpoint
+	 * Those commands was provide by Elan and Synaptics
+	 */
+	if (trackpoint_id == TP_VARIANT_ELAN)
+		send_command_to_trackpoint(TP_TOGGLE_BURST,
+					   TP_TOGGLE_ELAN_SLEEP);
+	else if (trackpoint_id == TP_VARIANT_SYNAPTICS)
+		send_command_to_trackpoint(TP_TOGGLE_SOURCE_TAG,
+					   TP_TOGGLE_SNAPTICS_SLEEP);
+
+	/* Clear the data in queue and the counter */
+	memset(queue_data, 0, ARRAY_SIZE(queue_data));
+	data_count = 0;
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, ps2_suspend, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S0ix -> S0 transition */
+static void ps2_resume(void)
+{
+	uint8_t trackpoint_id;
+
+	ps2_enable_channel(PRIMUS_PS2_CH, 1, get_ps2_data);
+	trackpoint_id = get_trackpoint_id();
+	ps2_enable_channel(PRIMUS_PS2_CH, 1, send_aux_data_to_host_interrupt);
+	/*
+	 * For Synaptics trackpoint, EC need to send command to it again.
+	 * For Elan trackpoint, we just need to touch trackpoint and it wake.
+	 */
+	if (trackpoint_id == TP_VARIANT_SYNAPTICS)
+		send_command_to_trackpoint(TP_TOGGLE_SOURCE_TAG,
+					   TP_TOGGLE_SNAPTICS_SLEEP);
+
+	/* Clear the data in queue and the counter */
+	memset(queue_data, 0, ARRAY_SIZE(queue_data));
+	data_count = 0;
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, ps2_resume, HOOK_PRIO_DEFAULT);
diff --git a/board/primus/ps2.h b/board/primus/ps2.h
new file mode 100644
index 0000000000..a82d6d566a
--- /dev/null
+++ b/board/primus/ps2.h
@@ -0,0 +1,31 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_PRIMUS_PS2_H
+#define __CROS_EC_PRIMUS_PS2_H
+
+/* Primus board-specific PS2 configuration */
+/*
+ * Valid first byte responses to the "Read Secondary ID" (0xE1) command.
+ * 0x01 was the original IBM trackpoint, others implement very limited
+ * subset of trackpoint features.
+ */
+#define TP_READ_ID 0xE1 /* Sent for device identification */
+
+#define TP_COMMAND 0xE2 /* Commands start with this */
+
+/*
+ * Toggling Flag bits
+ */
+#define TP_TOGGLE 0x47 /* Toggle command */
+
+#define TP_VARIANT_ELAN 0x03
+#define TP_VARIANT_SYNAPTICS 0x06
+#define TP_TOGGLE_SOURCE_TAG 0x20
+#define TP_TOGGLE_BURST 0x28
+#define TP_TOGGLE_SNAPTICS_SLEEP 0x10
+#define TP_TOGGLE_ELAN_SLEEP 0x8
+
+#endif /* __CROS_EC_PRIMUS_PS2_H */
diff --git a/board/primus/pwm.c b/board/primus/pwm.c
new file mode 100644
index 0000000000..f2889c2b8e
--- /dev/null
+++ b/board/primus/pwm.c
@@ -0,0 +1,74 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "chipset.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "hooks.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_LED2_WHITE] = {
+		.channel = 0,
+		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+		.freq = 4800,
+	},
+	[PWM_CH_TKP_A_LED_N] = {
+		.channel = 1,
+		.flags = PWM_CONFIG_DSLEEP,
+		.freq = 4800,
+	},
+	[PWM_CH_LED1_AMBER] = {
+		.channel = 2,
+		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+		.freq = 4800,
+	},
+	[PWM_CH_KBLIGHT] = {
+		.channel = 3,
+		.flags = PWM_CONFIG_DSLEEP,
+		/*
+		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
+		 * flicker. Higher frequencies consume similar average power to
+		 * lower PWM frequencies, but higher frequencies record a much
+		 * lower maximum power.
+		 */
+		.freq = 2400,
+	},
+	[PWM_CH_FAN] = {
+		.channel = 5,
+		.flags = PWM_CONFIG_OPEN_DRAIN,
+		.freq = 25000
+	},
+	[PWM_CH_LED4] = {
+		.channel = 7,
+		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+		.freq = 4800,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+static void board_pwm_init(void)
+{
+	/*
+	 * Turn off LOGO/power/battery led
+	 */
+	pwm_enable(PWM_CH_LED1_AMBER, 1);
+	pwm_set_duty(PWM_CH_LED1_AMBER, 0);
+	pwm_enable(PWM_CH_LED2_WHITE, 1);
+	pwm_set_duty(PWM_CH_LED2_WHITE, 0);
+	pwm_enable(PWM_CH_TKP_A_LED_N, 1);
+	pwm_set_duty(PWM_CH_TKP_A_LED_N, 0);
+	pwm_enable(PWM_CH_LED4, 1);
+	pwm_set_duty(PWM_CH_LED4, 0);
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return;
+	pwm_enable(PWM_CH_KBLIGHT, 1);
+	/* TODO(b/190518315)
+	 * Check if need to turn to 100% after with chassis.
+	 */
+	pwm_set_duty(PWM_CH_KBLIGHT, 50);
+}
+DECLARE_HOOK(HOOK_INIT, board_pwm_init, HOOK_PRIO_DEFAULT);
diff --git a/board/primus/sensors.c b/board/primus/sensors.c
new file mode 100644
index 0000000000..67ec6c6310
--- /dev/null
+++ b/board/primus/sensors.c
@@ -0,0 +1,167 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc_chip.h"
+#include "common.h"
+#include "hooks.h"
+#include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
+#include "thermal.h"
+
+/* ADC configuration */
+const struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_1_DDR_SOC] = {
+		.name = "TEMP_DDR_SOC",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_2_SSD] = {
+		.name = "TEMP_SSD",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_3_CHARGER] = {
+		.name = "TEMP_CHARGER",
+		.input_ch = NPCX_ADC_CH6,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_4_MEMORY] = {
+		.name = "TEMP_MEMORY",
+		.input_ch = NPCX_ADC_CH9,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_5_USBC] = {
+		.name = "TEMP_USBC",
+		.input_ch = NPCX_ADC_CH2,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_IADPT] = {
+		.name = "CHARGER_IADPT",
+		.input_ch = NPCX_ADC_CH3,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* Temperature sensor configuration */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1_DDR_SOC] = { .name = "DDR and SOC",
+				    .type = TEMP_SENSOR_TYPE_BOARD,
+				    .read = get_temp_3v3_30k9_47k_4050b,
+				    .idx = ADC_TEMP_SENSOR_1_DDR_SOC },
+	[TEMP_SENSOR_2_SSD] = { .name = "SSD",
+				.type = TEMP_SENSOR_TYPE_BOARD,
+				.read = get_temp_3v3_30k9_47k_4050b,
+				.idx = ADC_TEMP_SENSOR_2_SSD },
+	[TEMP_SENSOR_3_CHARGER] = { .name = "Charger",
+				    .type = TEMP_SENSOR_TYPE_BOARD,
+				    .read = get_temp_3v3_30k9_47k_4050b,
+				    .idx = ADC_TEMP_SENSOR_3_CHARGER },
+	[TEMP_SENSOR_4_MEMORY] = { .name = "MEMORY",
+				   .type = TEMP_SENSOR_TYPE_BOARD,
+				   .read = get_temp_3v3_30k9_47k_4050b,
+				   .idx = ADC_TEMP_SENSOR_4_MEMORY },
+	[TEMP_SENSOR_5_USBC] = { .name = "USBC",
+				 .type = TEMP_SENSOR_TYPE_BOARD,
+				 .read = get_temp_3v3_30k9_47k_4050b,
+				 .idx = ADC_TEMP_SENSOR_5_USBC },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/*
+ * TODO(b/195901486): update for Alder Lake/primus
+ *
+ * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
+ * 130 C.  However, sensor is located next to DDR, so we need to use the lower
+ * DDR temperature limit (85 C)
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(90), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+		}, \
+		.temp_fan_off = C_TO_K(35), \
+		.temp_fan_max = C_TO_K(50), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
+
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_SSD              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(92), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+		}, \
+		.temp_fan_off = C_TO_K(40), \
+		.temp_fan_max = C_TO_K(55), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_ssd = THERMAL_SSD;
+
+/*
+ * TODO(b/195901486): update for Alder Lake/primus
+ *
+ * Inductor limits - used for both charger and PP3300 regulator
+ *
+ * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
+ *
+ * Charger max recommended temperature 100C, max absolute temperature 125C
+ * PP3300 regulator: operating range -40 C to 145 C
+ *
+ * Inductors: limit of 125c
+ * PCB: limit is 80c
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_INDUCTOR         \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(90), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+		}, \
+		.temp_fan_off = C_TO_K(40), \
+		.temp_fan_max = C_TO_K(55), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_inductor =
+	THERMAL_INDUCTOR;
+
+/*
+ * TODO(b/195901486): Thermal table need to be fine tuned.
+ */
+struct ec_thermal_config thermal_params[] = {
+	[TEMP_SENSOR_1_DDR_SOC] = THERMAL_CPU,
+	[TEMP_SENSOR_2_SSD] = THERMAL_SSD,
+	[TEMP_SENSOR_3_CHARGER] = THERMAL_INDUCTOR,
+	[TEMP_SENSOR_4_MEMORY] = THERMAL_INDUCTOR,
+	[TEMP_SENSOR_5_USBC] = THERMAL_INDUCTOR,
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
diff --git a/board/primus/thermal.c b/board/primus/thermal.c
new file mode 100644
index 0000000000..00e2dddf98
--- /dev/null
+++ b/board/primus/thermal.c
@@ -0,0 +1,153 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "fan.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "temp_sensor.h"
+#include "thermal.h"
+#include "util.h"
+/* Console output macros */
+#define CPUTS(outstr) cputs(CC_THERMAL, outstr)
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
+
+struct fan_step {
+	/*
+	 * Sensor 1~4 trigger point, set -1 if we're not using this
+	 * sensor to determine fan speed.
+	 */
+	int8_t on[TEMP_SENSOR_COUNT];
+	/*
+	 * Sensor 1~4 trigger point, set -1 if we're not using this
+	 * sensor to determine fan speed.
+	 */
+	int8_t off[TEMP_SENSOR_COUNT];
+	/* Fan rpm */
+	uint16_t rpm[FAN_CH_COUNT];
+};
+
+static const struct fan_step fan_table[] = {
+	{
+		/* level 0 */
+		.on = { 40, -1, -1, -1, -1 },
+		.off = { 0, -1, -1, -1, -1 },
+		.rpm = { 0 },
+	},
+	{
+		/* level 1 */
+		.on = { 42, -1, -1, -1, -1 },
+		.off = { 40, -1, -1, -1, -1 },
+		.rpm = { 1800 },
+	},
+	{
+		/* level 2 */
+		.on = { 43, -1, -1, -1, -1 },
+		.off = { 42, -1, -1, -1, -1 },
+		.rpm = { 2000 },
+	},
+	{
+		/* level 3 */
+		.on = { 44, -1, -1, -1, -1 },
+		.off = { 43, -1, -1, -1, -1 },
+		.rpm = { 2200 },
+	},
+	{
+		/* level 4 */
+		.on = { 45, -1, -1, -1, -1 },
+		.off = { 44, -1, -1, -1, -1 },
+		.rpm = { 2500 },
+	},
+	{
+		/* level 5 */
+		.on = { 46, -1, -1, -1, -1 },
+		.off = { 45, -1, -1, -1, -1 },
+		.rpm = { 2800 },
+	},
+	{
+		/* level 6 */
+		.on = { 47, -1, -1, -1, -1 },
+		.off = { 46, -1, -1, -1, -1 },
+		.rpm = { 3000 },
+	},
+	{
+		/* level 7 */
+		.on = { 75, -1, -1, -1, -1 },
+		.off = { 72, -1, -1, -1, -1 },
+		.rpm = { 3200 },
+	},
+};
+const int num_fan_levels = ARRAY_SIZE(fan_table);
+
+int fan_table_to_rpm(int fan, int *temp, enum temp_sensor_id temp_sensor)
+{
+	/* current fan level */
+	static int current_level;
+	/* previous fan level */
+	static int prev_current_level;
+
+	/* previous sensor temperature */
+	static int prev_temp[TEMP_SENSOR_COUNT];
+	int i;
+	int new_rpm = 0;
+
+	/*
+	 * Compare the current and previous temperature, we have
+	 * the three paths :
+	 *  1. decreasing path. (check the release point)
+	 *  2. increasing path. (check the trigger point)
+	 *  3. invariant path. (return the current RPM)
+	 */
+	if (temp[temp_sensor] < prev_temp[temp_sensor]) {
+		for (i = current_level; i > 0; i--) {
+			if (temp[temp_sensor] < fan_table[i].off[temp_sensor])
+				current_level = i - 1;
+			else
+				break;
+		}
+	} else if (temp[temp_sensor] > prev_temp[temp_sensor]) {
+		for (i = current_level; i < num_fan_levels; i++) {
+			if (temp[temp_sensor] > fan_table[i].on[temp_sensor])
+				current_level = i + 1;
+			else
+				break;
+		}
+	}
+	if (current_level < 0)
+		current_level = 0;
+
+	if (current_level != prev_current_level) {
+		CPRINTS("temp: %d, prev_temp: %d", temp[temp_sensor],
+			prev_temp[temp_sensor]);
+		CPRINTS("current_level: %d", current_level);
+	}
+
+	prev_temp[temp_sensor] = temp[temp_sensor];
+	prev_current_level = current_level;
+
+	switch (fan) {
+	case FAN_CH_0:
+		new_rpm = fan_table[current_level].rpm[FAN_CH_0];
+		break;
+	default:
+		break;
+	}
+	return new_rpm;
+}
+void board_override_fan_control(int fan, int *temp)
+{
+	if (chipset_in_state(CHIPSET_STATE_ON)) {
+		fan_set_rpm_mode(FAN_CH(fan), 1);
+		fan_set_rpm_target(FAN_CH(fan),
+				   fan_table_to_rpm(FAN_CH(fan), temp,
+						    TEMP_SENSOR_1_DDR_SOC));
+	} else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
+		/* Stop fan when enter S0ix */
+		fan_set_rpm_mode(FAN_CH(fan), 1);
+		fan_set_rpm_target(FAN_CH(fan), 0);
+	}
+}
diff --git a/board/primus/usbc_config.c b/board/primus/usbc_config.c
new file mode 100644
index 0000000000..aca27e9c8e
--- /dev/null
+++ b/board/primus/usbc_config.c
@@ -0,0 +1,291 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/bc12/pi3usb9201_public.h"
+#include "driver/ppc/nx20p348x.h"
+#include "driver/ppc/syv682x_public.h"
+#include "driver/retimer/bb_retimer_public.h"
+#include "driver/tcpm/rt1715.h"
+#include "driver/tcpm/tcpci.h"
+#include "ec_commands.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "system.h"
+#include "task.h"
+#include "task_id.h"
+#include "timer.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+/* USBC TCPC configuration */
+const struct tcpc_config_t tcpc_config[] = {
+	[USBC_PORT_C0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0_TCPC,
+			.addr_flags = RT1715_I2C_ADDR_FLAGS,
+		},
+		.drv = &rt1715_tcpm_drv,
+	},
+	[USBC_PORT_C1] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C1_TCPC,
+			.addr_flags = RT1715_I2C_ADDR_FLAGS,
+		},
+		.drv = &rt1715_tcpm_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
+BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
+
+/* USBC PPC configuration */
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_C1_PPC_BC,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.drv = &syv682x_drv,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C0_C1_PPC_BC,
+		.i2c_addr_flags = SYV682X_ADDR2_FLAGS,
+		.drv = &syv682x_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
+
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/* USBC mux configuration - Alder Lake includes internal mux */
+static const struct usb_mux_chain usbc0_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+static const struct usb_mux_chain usbc1_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+
+const struct usb_mux_chain usb_muxes[] = {
+	[USBC_PORT_C0] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C0_C1_RT,
+			.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc0_tcss_usb_mux,
+	},
+	[USBC_PORT_C1] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C0_C1_RT,
+			.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc1_tcss_usb_mux,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
+
+/* BC1.2 charger detect configuration */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_C1_PPC_BC,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C0_C1_PPC_BC,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_1_FLAGS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
+
+void config_usb_db_type(void)
+{
+	enum ec_cfg_usb_db_type db_type = ec_cfg_usb_db_type();
+
+	/*
+	 * TODO(b/180434685): implement multiple DB types
+	 */
+
+	CPRINTS("Configured USB DB type number is %d", db_type);
+}
+
+__override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
+{
+	enum gpio_signal rst_signal;
+
+	if (me->usb_port == USBC_PORT_C0) {
+		rst_signal = GPIO_USB_C0_RT_RST_ODL;
+	} else if (me->usb_port == USBC_PORT_C1) {
+		rst_signal = GPIO_USB_C1_RT_RST_ODL;
+	} else {
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * We do not have a load switch for the burnside bridge chips,
+	 * so we only need to sequence reset.
+	 */
+
+	if (enable) {
+		/*
+		 * Tpw, minimum time from VCC to RESET_N de-assertion is 100us.
+		 * For boards that don't provide a load switch control, the
+		 * retimer_init() function ensures power is up before calling
+		 * this function.
+		 */
+		gpio_set_level(rst_signal, 1);
+		/*
+		 * Allow 1ms time for the retimer to power up lc_domain
+		 * which powers I2C controller within retimer
+		 */
+		msleep(1);
+
+		/* This will allow power saving on BB retimer */
+		gpio_set_level(GPIO_TBT_PWR_EN, 1);
+	} else {
+		gpio_set_level(rst_signal, 0);
+		msleep(1);
+		gpio_set_level(GPIO_TBT_PWR_EN, 0);
+	}
+	return EC_SUCCESS;
+}
+
+void board_reset_pd_mcu(void)
+{
+	/* Using RT1716, no reset available for TCPC on port 0/ port 2 */
+}
+
+static void board_tcpc_init(void)
+{
+	/* Don't reset TCPCs after initial reset */
+	if (!system_jumped_late()) {
+		board_reset_pd_mcu();
+	}
+
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
+
+	/* Enable BC1.2 interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_0;
+
+	if (gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
+
+int ppc_get_alert_status(int port)
+{
+	if (port == USBC_PORT_C0)
+		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
+	else if (port == USBC_PORT_C1)
+		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
+	return 0;
+}
+
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C1);
+		break;
+	default:
+		break;
+	}
+}
+
+void bc12_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_BC12_INT_ODL:
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+		break;
+	case GPIO_USB_C1_BC12_INT_ODL:
+		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+		break;
+	default:
+		break;
+	}
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C1);
+		break;
+	default:
+		break;
+	}
+}
+
+void retimer_interrupt(enum gpio_signal signal)
+{
+	/*
+	 * TODO(b/179513527): add USB-C support
+	 */
+}
+
+__override bool board_is_dts_port(int port)
+{
+	return port == USBC_PORT_C0;
+}
+
+__override enum tbt_compat_cable_speed board_get_max_tbt_speed(int port)
+{
+	if (ec_cfg_mlb_usb())
+		return TBT_SS_U32_GEN1_GEN2;
+
+	return TBT_SS_TBT_GEN3;
+}
diff --git a/board/primus/usbc_config.h b/board/primus/usbc_config.h
new file mode 100644
index 0000000000..1e087f083c
--- /dev/null
+++ b/board/primus/usbc_config.h
@@ -0,0 +1,17 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Primus board-specific USB-C configuration */
+
+#ifndef __CROS_EC_USBC_CONFIG_H
+#define __CROS_EC_USBC_CONFIG_H
+
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
+
+void config_usb_db_type(void);
+
+#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/primus/vif_override.xml b/board/primus/vif_override.xml
new file mode 100644
index 0000000000..5f9cb6eed1
--- /dev/null
+++ b/board/primus/vif_override.xml
@@ -0,0 +1,117 @@
+<?xml version="1.0" encoding="utf-8"?>
+<vif:VIF xmlns="http://usb.org/VendorInfoFile.xsd">
+  <vif:Product_Revision>2</vif:Product_Revision>
+  <vif:TID>0</vif:TID>
+  <vif:Product>
+    <vif:USB4_Num_Internal_Host_Controllers value="1" />
+    <vif:USB4_Num_PCIe_DN_Bridges value="0" />
+    <vif:USB4RouterList>
+      <vif:Usb4Router>
+        <!--USB4 Router 0-->
+        <vif:USB4_Router_ID value="0" />
+        <vif:USB4_Silicon_VID value="32903">8087</vif:USB4_Silicon_VID>
+        <vif:USB4_Num_Lane_Adapters value="4" />
+        <vif:USB4_Num_USB3_DN_Adapters value="1" />
+        <vif:USB4_Num_DP_IN_Adapters value="1" />
+        <vif:USB4_Num_DP_OUT_Adapters value="0" />
+        <vif:USB4_Num_PCIe_DN_Adapters value="4" />
+        <vif:USB4_TBT3_Not_Supported value="0">TBT3 Compatible</vif:USB4_TBT3_Not_Supported>
+        <vif:USB4_PCIe_Wake_Supported value="true" />
+        <vif:USB4_USB3_Wake_Supported value="false" />
+        <vif:USB4_Num_Unused_Adapters value="0" />
+        <vif:USB4_TBT3_VID value="32903">8087</vif:USB4_TBT3_VID>
+        <vif:USB4_PCIe_Switch_Vendor_ID value="32902">8086</vif:USB4_PCIe_Switch_Vendor_ID>
+        <vif:USB4_PCIe_Switch_Device_ID value="17982">463E</vif:USB4_PCIe_Switch_Device_ID>
+      </vif:Usb4Router>
+    </vif:USB4RouterList>
+  </vif:Product>
+
+  <vif:Component>
+    <vif:USB4_Max_Speed value="1">Gen 3 (40Gb)</vif:USB4_Max_Speed>
+
+    <!--;USB Host-->
+
+    <vif:Host_Speed value="2">USB 3.2 Gen 2x1</vif:Host_Speed>
+    <vif:Host_Contains_Captive_Retimer value="true" />
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:Host_Suspend_Supported value="true" />
+
+    <!--;PD Source-->
+    <!-- will we ever clear USB_Suspend_Supported? -->
+    <vif:USB_Suspend_May_Be_Cleared value="true" />
+
+    <!-- remove FR_Swap_* when we enable CONFIG_USB_PD_FRS -->
+    <!--;Dual Role-->
+    <vif:FR_Swap_Supported_As_Initial_Sink value="true" />
+    <!--;PD Source-->
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="3">3A @ 5V</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!--Source PDO 1-->
+        <vif:Src_PD_OCP_OC_Debounce value="50">50 msec</vif:Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="360">3600 mA</vif:Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+
+    <!-- SOP Discover ID -->
+    <vif:Product_Type_UFP_SOP value="2">PDUSB Peripheral</vif:Product_Type_UFP_SOP>
+    <vif:Product_Type_DFP_SOP value="2">PDUSB Host</vif:Product_Type_DFP_SOP>
+
+    <!-- USB4 Port -->
+    <vif:USB4_Lane_0_Adapter value="1" />
+    <vif:USB4_UFP_Supported value="false" />
+    <vif:USB4_DFP_Supported value="true" />
+    <vif:USB4_USB3_Tunneling_Supported value="true" />
+    <vif:USB4_DP_Tunneling_Supported value="true" />
+    <vif:USB4_CL1_State_Supported value="true" />
+    <vif:USB4_CL2_State_Supported value="true" />
+    <vif:USB4_Num_Retimers value="1" />
+    <vif:USB4_DP_Bit_Rate value="3">HBR3</vif:USB4_DP_Bit_Rate>
+    <vif:USB4_Num_DP_Lanes value="4">4 Lanes</vif:USB4_Num_DP_Lanes>
+
+  </vif:Component>
+
+  <vif:Component>
+    <vif:USB4_Max_Speed value="1">Gen 3 (40Gb)</vif:USB4_Max_Speed>
+
+    <!--;USB Host-->
+    <vif:Host_Speed value="2">USB 3.2 Gen 2x1</vif:Host_Speed>
+    <vif:Host_Contains_Captive_Retimer value="true" />
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:Host_Suspend_Supported value="true" />
+
+    <!--;PD Source-->
+    <!-- will we ever clear USB_Suspend_Supported? -->
+    <vif:USB_Suspend_May_Be_Cleared value="true" />
+
+    <!-- remove FR_Swap_* when we enable CONFIG_USB_PD_FRS -->
+    <!--;Dual Role-->
+    <vif:FR_Swap_Supported_As_Initial_Sink value="true" />
+    <!--;PD Source-->
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="3">3A @ 5V</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!--Source PDO 1-->
+        <vif:Src_PD_OCP_OC_Debounce value="50">50 msec</vif:Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="360">3600 mA</vif:Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+
+    <!-- SOP Discover ID -->
+    <vif:Product_Type_UFP_SOP value="2">PDUSB Peripheral</vif:Product_Type_UFP_SOP>
+    <vif:Product_Type_DFP_SOP value="2">PDUSB Host</vif:Product_Type_DFP_SOP>
+
+   <!-- USB4 Port -->
+    <vif:USB4_Lane_0_Adapter value="1" />
+    <vif:USB4_UFP_Supported value="false" />
+    <vif:USB4_DFP_Supported value="true" />
+    <vif:USB4_USB3_Tunneling_Supported value="true" />
+    <vif:USB4_DP_Tunneling_Supported value="true" />
+    <vif:USB4_CL1_State_Supported value="true" />
+    <vif:USB4_CL2_State_Supported value="true" />
+    <vif:USB4_Num_Retimers value="1" />
+    <vif:USB4_DP_Bit_Rate value="3">HBR3</vif:USB4_DP_Bit_Rate>
+    <vif:USB4_Num_DP_Lanes value="4">4 Lanes</vif:USB4_Num_DP_Lanes>
+
+  </vif:Component>
+</vif:VIF>
diff --git a/board/prism/board.c b/board/prism/board.c
new file mode 100644
index 0000000000..efdc4f5cd1
--- /dev/null
+++ b/board/prism/board.c
@@ -0,0 +1,366 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "clock.h"
+#include "common.h"
+#include "ec_commands.h"
+#include "ec_version.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "hwtimer.h"
+#include "i2c.h"
+#include "printf.h"
+#include "registers.h"
+#include "rgb_keyboard.h"
+#include "rollback.h"
+#include "spi.h"
+#include "system.h"
+#include "task.h"
+#include "timer.h"
+#include "update_fw.h"
+#include "usart-stm32f0.h"
+#include "usart_rx_dma.h"
+#include "usart_tx_dma.h"
+#include "usb_api.h"
+#include "usb_descriptor.h"
+#include "util.h"
+
+#include <stdbool.h>
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+#ifdef SECTION_IS_RW
+#define CROS_EC_SECTION "RW"
+#else
+#define CROS_EC_SECTION "RO"
+#endif
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+/******************************************************************************
+ * Define the strings used in our USB descriptors.
+ */
+const void *const usb_strings[] = {
+	[USB_STR_DESC] = usb_string_desc,
+	[USB_STR_VENDOR] = USB_STRING_DESC("Google LLC"),
+	[USB_STR_PRODUCT] = USB_STRING_DESC("Prism"),
+	[USB_STR_SERIALNO] = 0,
+	[USB_STR_VERSION] =
+		USB_STRING_DESC(CROS_EC_SECTION ":" CROS_EC_VERSION32),
+	[USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"),
+	[USB_STR_HOSTCMD_NAME] = USB_STRING_DESC("Host command"),
+};
+
+BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
+
+/******************************************************************************
+ * Support I2C bridging over USB.
+ */
+
+#ifdef SECTION_IS_RW
+const struct spi_device_t spi_devices[] = {
+	[SPI_RGB0_DEVICE_ID] = { CONFIG_SPI_RGB_PORT, 2, /* 2: Fpclk/8 = 48Mhz/8
+							    = 6Mhz */
+				 GPIO_SPI1_CS1_L },
+	[SPI_RGB1_DEVICE_ID] = { CONFIG_SPI_RGB_PORT, 2, GPIO_SPI1_CS2_L },
+};
+const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
+
+/*
+ * RGB Keyboard config & data
+ */
+BUILD_ASSERT(RGB_GRID0_ROW == RGB_GRID1_ROW);
+
+extern struct rgbkbd_drv is31fl3743b_drv;
+
+static struct rgb_s grid0[RGB_GRID0_COL * RGB_GRID0_ROW];
+static struct rgb_s grid1[RGB_GRID1_COL * RGB_GRID1_ROW];
+
+struct rgbkbd rgbkbds[] = {
+	[0] = {
+		.cfg = &(const struct rgbkbd_cfg) {
+			.drv = &is31fl3743b_drv,
+			.spi = SPI_RGB0_DEVICE_ID,
+			.col_len = RGB_GRID0_COL,
+			.row_len = RGB_GRID0_ROW,
+		},
+		.buf = grid0,
+	},
+	[1] = {
+		.cfg = &(const struct rgbkbd_cfg) {
+			.drv = &is31fl3743b_drv,
+			.spi = SPI_RGB1_DEVICE_ID,
+			.col_len = RGB_GRID1_COL,
+			.row_len = RGB_GRID1_ROW,
+		},
+		.buf = grid1,
+	},
+};
+const uint8_t rgbkbd_count = ARRAY_SIZE(rgbkbds);
+const uint8_t rgbkbd_hsize = RGB_GRID0_COL + RGB_GRID1_COL;
+const uint8_t rgbkbd_vsize = RGB_GRID0_ROW;
+
+enum ec_rgbkbd_type rgbkbd_type = EC_RGBKBD_TYPE_PER_KEY;
+
+#define LED(x, y) RGBKBD_COORD((x), (y))
+#define DELM RGBKBD_DELM
+
+const uint8_t rgbkbd_map[] = {
+	DELM, /* 0: (null) */
+	LED(0, 1),  LED(0, 2),	DELM, /* 1: ~ ` */
+	LED(1, 1),  LED(1, 2),	DELM, /* 2: ! 1 */
+	LED(2, 1),  LED(2, 2),	DELM, /* 3: @ 2 */
+	LED(3, 1),  LED(3, 2),	DELM, /* 4: # 3 */
+	LED(4, 1),  LED(4, 2),	DELM, /* 5: $ 4 */
+	LED(5, 1),  LED(5, 2),	DELM, /* 6: % 5 */
+	LED(6, 1),  LED(6, 2),	DELM, /* 7: ^ 6 */
+	LED(7, 1),  LED(7, 2),	DELM, /* 8: & 7 */
+	LED(8, 1),  LED(8, 2),	DELM, /* 9: * 8 */
+	LED(9, 1),  LED(9, 2),	DELM, /* 10: ( 9 */
+	LED(10, 1), LED(10, 2), DELM, /* 11: ) 0 */
+	LED(11, 1), LED(11, 2), DELM, /* 12: _ - */
+	LED(12, 1), LED(12, 2), DELM, /* 13: + = */
+	DELM, /* 14: (null) */
+	LED(13, 1), LED(13, 2), DELM, /* 15: backspace */
+	LED(0, 3),  LED(15, 2), DELM, /* 16: tab */
+	LED(1, 3),  DELM, /* 17: q */
+	LED(2, 3),  DELM, /* 18: w */
+	LED(3, 3),  DELM, /* 19: e */
+	LED(4, 3),  DELM, /* 20: r */
+	LED(5, 3),  DELM, /* 21: t */
+	LED(6, 3),  DELM, /* 22: y */
+	LED(7, 3),  DELM, /* 23: u */
+	LED(8, 3),  DELM, /* 24: i */
+	LED(9, 3),  DELM, /* 25: o */
+	LED(10, 3), DELM, /* 26: p */
+	LED(11, 3), LED(12, 3), DELM, /* 27: [ { */
+	LED(13, 3), LED(14, 3), DELM, /* 28: ] } */
+	LED(15, 3), LED(16, 3), DELM, /* 29: \ | */
+	LED(0, 4),  LED(1, 4),	DELM, /* 30: caps lock */
+	LED(2, 4),  DELM, /* 31: a */
+	LED(3, 4),  DELM, /* 32: s */
+	LED(4, 4),  DELM, /* 33: d */
+	LED(5, 4),  DELM, /* 34: f */
+	LED(6, 4),  DELM, /* 35: g */
+	LED(7, 4),  DELM, /* 36: h */
+	LED(8, 4),  DELM, /* 37: j */
+	LED(9, 4),  DELM, /* 38: k */
+	LED(10, 4), DELM, /* 39: l */
+	LED(11, 4), LED(12, 4), DELM, /* 40: ; : */
+	LED(13, 4), LED(14, 4), DELM, /* 41: " ' */
+	DELM, /* 42: (null) */
+	LED(15, 4), LED(16, 4), DELM, /* 43: enter */
+	LED(0, 5),  LED(1, 5),	LED(2, 5),  DELM, /* 44: L-shift */
+	DELM, /* 45: (null) */
+	LED(3, 5),  DELM, /* 46: z */
+	LED(4, 5),  DELM, /* 47: x */
+	LED(5, 5),  DELM, /* 48: c */
+	LED(6, 5),  DELM, /* 49: v */
+	LED(7, 5),  DELM, /* 50: b */
+	LED(8, 5),  DELM, /* 51: n */
+	LED(9, 5),  DELM, /* 52: m */
+	LED(10, 5), LED(11, 5), DELM, /* 53: , < */
+	LED(12, 5), LED(13, 5), DELM, /* 54: . > */
+	LED(14, 5), LED(15, 5), DELM, /* 55: / ? */
+	DELM, /* 56: (null) */
+	LED(16, 5), LED(17, 5), LED(18, 5), DELM, /* 57: R-shift */
+	LED(17, 4), LED(18, 4), LED(19, 4), DELM, /* 58: L-ctrl */
+	LED(15, 0), DELM, /* 59: power */
+	LED(17, 2), LED(18, 2), LED(19, 2), DELM, /* 60: L-alt */
+	LED(17, 3), LED(18, 3), LED(19, 3), LED(20, 3),
+	LED(21, 3), LED(16, 2), DELM, /* 61: space */
+	LED(20, 2), DELM, /* 62: R-alt */
+	DELM, /* 63: (null) */
+	LED(21, 2), DELM, /* 64: R-ctrl */
+	DELM, /* 65: (null) */
+	DELM, /* 66: (null) */
+	DELM, /* 67: (null) */
+	DELM, /* 68: (null) */
+	DELM, /* 69: (null) */
+	DELM, /* 70: (null) */
+	DELM, /* 71: (null) */
+	DELM, /* 72: (null) */
+	DELM, /* 73: (null) */
+	DELM, /* 74: (null) */
+	DELM, /* 75: (null) */
+	DELM, /* 76: (null) */
+	DELM, /* 77: (null) */
+	DELM, /* 78: (null) */
+	LED(19, 5), DELM, /* 79: left */
+	DELM, /* 80: (null) */
+	DELM, /* 81: (null) */
+	DELM, /* 82: (null) */
+	LED(20, 4), DELM, /* 83: up */
+	LED(20, 5), DELM, /* 84: down */
+	DELM, /* 85: (null) */
+	DELM, /* 86: (null) */
+	DELM, /* 87: (null) */
+	DELM, /* 88: (null) */
+	LED(21, 5), DELM, /* 89: right */
+	DELM, /* 90: (null) */
+	DELM, /* 91: (null) */
+	DELM, /* 92: (null) */
+	DELM, /* 93: (null) */
+	DELM, /* 94: (null) */
+	DELM, /* 95: (null) */
+	DELM, /* 96: (null) */
+	DELM, /* 97: (null) */
+	DELM, /* 98: (null) */
+	DELM, /* 99: (null) */
+	DELM, /* 100: (null) */
+	DELM, /* 101: (null) */
+	DELM, /* 102: (null) */
+	DELM, /* 103: (null) */
+	DELM, /* 104: (null) */
+	DELM, /* 105: (null) */
+	DELM, /* 106: (null) */
+	DELM, /* 107: (null) */
+	DELM, /* 108: (null) */
+	DELM, /* 109: (null) */
+	LED(0, 0),  DELM, /* 110: esc */
+	LED(1, 0),  DELM, /* T1: previous page */
+	LED(2, 0),  DELM, /* T2: refresh */
+	LED(3, 0),  DELM, /* T3: full screen */
+	LED(4, 0),  DELM, /* T4: windows */
+	LED(5, 0),  DELM, /* T5: screenshot */
+	LED(6, 0),  DELM, /* T6: brightness down */
+	LED(7, 0),  DELM, /* T7: brightness up */
+	LED(8, 0),  DELM, /* T8: KB backlight off */
+	LED(9, 0),  DELM, /* T9: play/pause */
+	LED(10, 0), DELM, /* T10: mute microphone */
+	LED(11, 0), DELM, /* T11: mute speakers */
+	LED(12, 0), DELM, /* T12: volume down */
+	LED(13, 0), DELM, /* T13: volume up */
+	DELM, /* T14: (null) */
+	DELM, /* T15: (null) */
+	DELM, /* 126: (null) */
+	DELM, /* 127: (null) */
+};
+#undef LED
+#undef DELM
+const size_t rgbkbd_map_size = ARRAY_SIZE(rgbkbd_map);
+
+__override void board_kblight_shutdown(void)
+{
+	gpio_set_level(GPIO_RGBKBD_POWER, 0);
+}
+
+__override void board_kblight_init(void)
+{
+	/*
+	 * Keep hardware stand-by always on since it doesn't allow scale and PWM
+	 * registers to be written. We use software stand-by for enable/disable.
+	 */
+	gpio_set_level(GPIO_RGBKBD_SDB_L, 1);
+	gpio_set_level(GPIO_RGBKBD_POWER, 1);
+	msleep(10);
+}
+
+#endif
+
+/******************************************************************************
+ * Initialize board.
+ */
+static int has_keyboard_backlight;
+
+#ifdef SECTION_IS_RW
+static void board_init(void)
+{
+	spi_enable(&spi_devices[SPI_RGB0_DEVICE_ID], 0);
+	spi_enable(&spi_devices[SPI_RGB1_DEVICE_ID], 0);
+
+	/* Set all SPI pins to high speed */
+	/* pins A1, 2, 5, 6, 7 */
+	STM32_GPIO_OSPEEDR(GPIO_A) |= 0x0000fc3c;
+
+	/* Reset SPI1 */
+	STM32_RCC_APB2RSTR |= STM32_RCC_PB2_SPI1;
+	STM32_RCC_APB2RSTR &= ~STM32_RCC_PB2_SPI1;
+	/* Enable clocks to SPI1 module */
+	STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1;
+
+	clock_wait_bus_cycles(BUS_APB, 1);
+	/* Enable SPI for RGB matrix. */
+	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
+	spi_enable(&spi_devices[SPI_RGB0_DEVICE_ID], 1);
+	spi_enable(&spi_devices[SPI_RGB1_DEVICE_ID], 1);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_INIT_SPI - 1);
+#endif /* SECTION_IS_RW */
+
+void board_config_pre_init(void)
+{
+	/* enable SYSCFG clock */
+	STM32_RCC_APB2ENR |= BIT(0);
+
+	/* Remap USART DMA to match the USART driver */
+	/*
+	 * the DMA mapping is :
+	 *  Chan 4 : USART1_TX
+	 *  Chan 5 : USART1_RX
+	 */
+	STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10); /* Remap USART1 RX/TX DMA */
+}
+
+int board_has_keyboard_backlight(void)
+{
+	return has_keyboard_backlight;
+}
+
+/*
+ * Get entropy based on Clock Recovery System, which is enabled on hammer to
+ * synchronize USB SOF with internal oscillator.
+ */
+int board_get_entropy(void *buffer, int len)
+{
+	int i = 0;
+	uint8_t *data = buffer;
+	uint32_t start;
+	/* We expect one SOF per ms, so wait at most 2ms. */
+	const uint32_t timeout = 2 * MSEC;
+
+	for (i = 0; i < len; i++) {
+		STM32_CRS_ICR |= STM32_CRS_ICR_SYNCOKC;
+		start = __hw_clock_source_read();
+		while (!(STM32_CRS_ISR & STM32_CRS_ISR_SYNCOKF)) {
+			if ((__hw_clock_source_read() - start) > timeout)
+				return 0;
+			usleep(500);
+		}
+		/* Pick 8 bits, including FEDIR and 7 LSB of FECAP. */
+		data[i] = STM32_CRS_ISR >> 15;
+	}
+
+	return 1;
+}
+
+/*
+ * Generate a USB serial number from unique chip ID.
+ */
+__override const char *board_read_serial(void)
+{
+	static char str[CONFIG_SERIALNO_LEN];
+
+	if (str[0] == '\0') {
+		uint8_t *id;
+		int pos = 0;
+		int idlen = system_get_chip_unique_id(&id);
+		int i;
+
+		for (i = 0; i < idlen && pos < sizeof(str); i++, pos += 2) {
+			if (snprintf(&str[pos], sizeof(str) - pos, "%02x",
+				     id[i]) < 0)
+				return NULL;
+		}
+	}
+
+	return str;
+}
+
+__override int board_write_serial(const char *serialno)
+{
+	return 0;
+}
diff --git a/board/prism/board.h b/board/prism/board.h
new file mode 100644
index 0000000000..c4bf4de58e
--- /dev/null
+++ b/board/prism/board.h
@@ -0,0 +1,223 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Prism configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* Prism doesn't use WP GPIO, set WP enabled */
+#ifdef SECTION_IS_RO
+#define CONFIG_WP_ALWAYS
+#endif
+
+/* TODO: May define FLASH_PSTATE_LOCKED prior to building MP FW. */
+#undef CONFIG_FLASH_PSTATE_LOCKED
+
+/* USB ID for Prism */
+#define CONFIG_USB_PID 0x5022
+
+/* 48 MHz SYSCLK clock frequency */
+#define CPU_CLOCK 48000000
+
+/* For RGB keyboard control */
+#ifdef SECTION_IS_RW
+#define CONFIG_KEYBOARD_BACKLIGHT
+#define CONFIG_RGB_KEYBOARD
+#define GPIO_RGBKBD_SDB_L GPIO_SDB_L
+#define GPIO_RGBKBD_POWER GPIO_L_POWER
+#define CONFIG_LED_DRIVER_IS31FL3743B
+#define SPI_RGB0_DEVICE_ID 0
+#define SPI_RGB1_DEVICE_ID 1
+#define RGB_GRID0_COL 11
+#define RGB_GRID0_ROW 6
+#define RGB_GRID1_COL 11
+#define RGB_GRID1_ROW 6
+
+/* Enable control of SPI over USB */
+#define CONFIG_SPI_CONTROLLER
+#define CONFIG_STM32_SPI1_CONTROLLER
+/* Enable SPI controller xfer command */
+#define CONFIG_CMD_SPI_XFER
+
+#define CONFIG_SPI_RGB_PORT 0
+
+#define CONFIG_IS31FL3743B_LATE_INIT
+
+#endif /* SECTION_IS_RW */
+
+/*
+ * Flash layout: we redefine the sections offsets and sizes as we want to
+ * include a rollback region, and will use RO/RW regions of different sizes.
+ */
+#undef _IMAGE_SIZE
+#undef CONFIG_ROLLBACK_OFF
+#undef CONFIG_ROLLBACK_SIZE
+#undef CONFIG_FLASH_PSTATE
+#undef CONFIG_FW_PSTATE_SIZE
+#undef CONFIG_FW_PSTATE_OFF
+#undef CONFIG_SHAREDLIB_SIZE
+#undef CONFIG_RO_MEM_OFF
+#undef CONFIG_RO_STORAGE_OFF
+#undef CONFIG_RO_SIZE
+#undef CONFIG_RW_MEM_OFF
+#undef CONFIG_RW_STORAGE_OFF
+#undef CONFIG_RW_SIZE
+#undef CONFIG_EC_PROTECTED_STORAGE_OFF
+#undef CONFIG_EC_PROTECTED_STORAGE_SIZE
+#undef CONFIG_EC_WRITABLE_STORAGE_OFF
+#undef CONFIG_EC_WRITABLE_STORAGE_SIZE
+#undef CONFIG_WP_STORAGE_OFF
+#undef CONFIG_WP_STORAGE_SIZE
+
+#define CONFIG_FLASH_PSTATE
+/* Do not use a dedicated PSTATE bank */
+#undef CONFIG_FLASH_PSTATE_BANK
+
+#define CONFIG_SHAREDLIB_SIZE 0
+
+#define CONFIG_RO_MEM_OFF 0
+#define CONFIG_RO_STORAGE_OFF 0
+#define CONFIG_RO_SIZE (44 * 1024)
+
+/* EC rollback protection block */
+#define CONFIG_ROLLBACK_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
+#define CONFIG_ROLLBACK_SIZE CONFIG_FLASH_BANK_SIZE
+
+#define CONFIG_RW_MEM_OFF (CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE)
+#define CONFIG_RW_STORAGE_OFF 0
+#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE_BYTES - CONFIG_RW_MEM_OFF)
+
+#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF
+#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE
+#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE
+
+#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
+#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
+
+/* The UART console is on USART1 (PA9/PA10) */
+#undef CONFIG_UART_CONSOLE
+#define CONFIG_UART_CONSOLE 1
+
+#undef CONFIG_UART_TX_BUF_SIZE
+/* Has to be power of two */
+#define CONFIG_UART_TX_BUF_SIZE 4096
+
+/* Optional features */
+#define CONFIG_LOW_POWER_IDLE
+#define CONFIG_LTO
+#define CONFIG_FORCE_CONSOLE_RESUME
+#define CONFIG_MATH_UTIL
+
+/* USB Configuration */
+#define CONFIG_USB
+#define CONFIG_STREAM_USB
+#define CONFIG_USB_UPDATE
+
+#undef CONFIG_USB_MAXPOWER_MA
+#define CONFIG_USB_MAXPOWER_MA 100
+
+#define CONFIG_USB_REMOTE_WAKEUP
+#define CONFIG_USB_SUSPEND
+
+#define CONFIG_USB_SERIALNO
+/* Replaced at runtime (board_read_serial) by chip unique-id-based number. */
+#define DEFAULT_SERIALNO "Uninitialized"
+
+/* USB interface indexes (use define rather than enum to expand them) */
+#undef CONFIG_HOSTCMD_EVENTS
+#define USB_IFACE_UPDATE 0
+#define CONFIG_HOST_INTERFACE_USB
+#define USB_IFACE_HOSTCMD 1
+#define USB_IFACE_COUNT 2
+
+/* USB endpoint indexes (use define rather than enum to expand them) */
+#define USB_EP_CONTROL 0
+#define USB_EP_UPDATE 1
+#define USB_EP_HOSTCMD 2
+#define USB_EP_COUNT 3
+
+/* Optional features */
+#define CONFIG_BOARD_PRE_INIT
+#define CONFIG_WATCHDOG_HELP
+
+/* No need to hibernate, remove console commands that are not very useful. */
+#undef CONFIG_HIBERNATE
+#undef CONFIG_CONSOLE_CHANNEL
+#undef CONFIG_CONSOLE_HISTORY
+#undef CONFIG_CMD_GETTIME
+#undef CONFIG_CMD_MD
+#undef CONFIG_CMD_RW
+#undef CONFIG_CMD_SHMEM
+#undef CONFIG_CMD_TIMERINFO
+#undef CONFIG_CMD_WAITMS
+
+#undef CONFIG_LID_SWITCH
+
+#define CONFIG_USB_CONSOLE_READ
+
+#ifdef SECTION_IS_RW
+
+#define CONFIG_CURVE25519
+
+#define CONFIG_USB_PAIRING
+
+#else /* SECTION_IS_RO */
+/* Sign and switch to RW partition on boot. */
+#define CONFIG_RWSIG
+#define CONFIG_RSA
+#endif
+
+#define CONFIG_RSA_KEY_SIZE 3072
+#define CONFIG_RSA_EXPONENT_3
+
+#define CONFIG_SHA256
+#ifdef SECTION_IS_RO
+#define CONFIG_SHA256_UNROLLED
+#endif
+
+#define CONFIG_RWSIG_TYPE_RWSIG
+
+/*
+ * Add rollback protection, and independent RW region protection.
+ */
+#define CONFIG_LIBCRYPTOC
+#define CONFIG_ROLLBACK
+#define CONFIG_ROLLBACK_SECRET_SIZE 32
+#define CONFIG_ROLLBACK_SECRET_LOCAL_ENTROPY_SIZE 32
+#define CONFIG_FLASH_PROTECT_RW
+#ifdef SECTION_IS_RW
+#undef CONFIG_ROLLBACK_UPDATE
+#endif
+
+/* Maximum current to draw. */
+#define MAX_CURRENT_MA 2000
+/* Maximum current/voltage to provide over OTG. */
+#define MAX_OTG_CURRENT_MA 2000
+#define MAX_OTG_VOLTAGE_MV 20000
+
+#ifndef __ASSEMBLER__
+
+/* Timer selection */
+#define TIM_CLOCK32 2
+#define TIM_WATCHDOG 16
+
+#include "gpio_signal.h"
+
+/* USB string indexes */
+enum usb_strings {
+	USB_STR_DESC = 0,
+	USB_STR_VENDOR,
+	USB_STR_PRODUCT,
+	USB_STR_SERIALNO,
+	USB_STR_VERSION,
+	USB_STR_UPDATE_NAME,
+	USB_STR_HOSTCMD_NAME,
+	USB_STR_COUNT
+};
+
+#endif /* !__ASSEMBLER__ */
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/prism/build.mk b/board/prism/build.mk
new file mode 100644
index 0000000000..7e37df6f7a
--- /dev/null
+++ b/board/prism/build.mk
@@ -0,0 +1,13 @@
+# -*- makefile -*-
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CHIP:=stm32
+CHIP_FAMILY:=stm32f0
+CHIP_VARIANT:=stm32f07x
+
+# Build tests that we care about for Prism.
+test-list-y=entropy rsa3 sha256 sha256_unrolled x25519
+
+board-y=board.o
diff --git a/board/prism/dev_key.pem b/board/prism/dev_key.pem
new file mode 100644
index 0000000000..b72c787613
--- /dev/null
+++ b/board/prism/dev_key.pem
@@ -0,0 +1,39 @@
+-----BEGIN RSA PRIVATE KEY-----
+MIIG4gIBAAKCAYEAseZZZlXXDP+KrjqV+XhP0ZgPlU5mX4GCm27yzTqcKiFWLlHZ
+3f8seGG0lKNiL7WvHim8uSEDaPbp2us4uaJ6nTHEpbSGi2QVp90tE3aJG34HyKlg
+jcaE1r/0n6ynG/bf0Xx4O63Plp3Czi3TBYW49vT6+T/Jyfl2JpGQ9KNcD0umafsv
+uaEmdrLGrzjN8w1mFZfwscFkfVDh0cdiFNJ+UkTSpO9/yPapXbo4/lOMwdO9xILF
+cEZV9I7K7lBSvQ5Uep+w0SqNPTh2cGhoeEeDyH+Ce0LA8H7ZwbVnwLe1RswF9Wek
+uzqp9lMSNkkwMtTkumTuJLLGJX9rc0MVQTKgNV8wIzizf5lkCCBCJLf7aRBaeWCJ
+cXjKiavSPOZXDcnqCWqRJT3jN4ibAsU1GQtqLa8pTAi2wkE0fjuvAWK3NYuvpukg
+qNq2LI+BJkF4+dCZoeB1PDNyFNzdOFvkxj2+ImS3DLlPYVng4vHsTK1HRUUpL5Ag
+jjfMhMs4NC7HMOCTAgEDAoIBgHaZkO7j5LNVBx7RuVD63+EQCmOJmZUBAbz0od4n
+EsbA5B7hO+lUyFBBIw3CQXUjyhQb0yYWAkX58Tyc0HvBpxN2gxkjBFztY8U+Hgz5
+sLz+r9sblbPZreR/+GpzGhKklTZS+tJz37m+gd7JN1kD0KSjUft/29v7pBm2YKMX
+krTdGZv8ynvAxE8h2col3qII7rkP9cvWQv416+EvlriMVDbYjG30/9tPG5PRe1Q3
+syvifoMB2PWEOU20h0mK4dNe4d7E96s1Q+RTmTUtyipxUp6d4PIufAjMtM8yfkb0
+/0z81IsWQ0NOhefrMAi8TEcDkbyNSBPqHqbqH2FosFWo2cU3r6TXv2LdvFzc5BA+
+U6c+fXz7BDjv+NT3Bh98whKvTdJYcIgSg6vqzW7ZWJWWllZQtpJnQccIq4sPaL4S
+osFg8jd1kcbjVakCN0wYtfvMa/+WBZNNsZLUHoeIJvO7qnT7VKzhceoKHCJCMxNR
+Ypu5eELxCwebTXiImDqmFsKIawKBwQDpDjff6eatHbjmGV1elTyV5MLi95Tc0T7P
+FZHC1KLXkA/mEuXjAGfoZuLB5a3WmrA8r8fWNZoKV+0RBKIs3at1JFxZn9YiA0Hy
+5qmnYkXjMaY4p5AyO3eJsc2kbsh9r0cy2cb5GdwFDApeoVICoQh+dW9FpvIS+9AF
+0DVc2/Rg//cuXLlCMonF+PZVmDxRNhjBvwvRjxeowiu2ntI4sa83nHMhXI/RfvV4
+xcSng8gSIvabUmunDcPKvqO3rnpHzVECgcEAw2oFcHDAuZ1Xuopb2ghLRK3uLQVy
+BnqLu9QYk3OTe8C3PrNZ80R5MgtnZ0kP8bTZ4uE6MJ3+IMhPUCFqk9euGGdMUlU+
+SUmHie5CZPg4CwD4BUBy6dVdwId7aTxrdBOuGwwhYAhBsJxcfd3eNgiALcCoKsbi
+BLhjJ9Rch2rOsnpNJVwMvFMr6RM33oQrrufe4MBhDa/QD9yDtnDYH/KPO09E6AqU
+sMvBNsjbCC9rSYv+L9QkW8EUhT+wJIcqxUajAoHBAJtez+qb7x4T0JlmPj8OKGPt
+10H6Yz3g1IoOYSyNweUKtUQMmUIARUWZ7IFDyTm8dX3KhTl5EVw6ngtYbB3pHPjC
+6Du/5Bas1qHvG8TsLpd2btBvtXbST7EhM8L0hakfhMyRL1C76ANdXD8WNqxrWv74
+9NkZ9rdSiq6Kzj3n+ECqpMmTJiwhsS6l+Y5lfYt5ZdZ/XTZfZRssHSRp4XshH3po
+TMDoX+D/TlCD2G+tMAwXTxI28m9egocpwnp0UYUziwKBwQCCRq5K9dXRE4/RsZKR
+WtzYc/QeA6FZpwfSjWW3omJSgHopzOaiLaYhXO+aMLVLzeaXQNF1vqlrMDTgFkcN
+OnQQRN2MONQw26+xSYGYpXqyAKVY1aHxOOkrBPzw0vJNYnQSCBZABYEgaD2pPpQk
+BarJKxrHL0FYeuzFOD2vnInMUYjDkrMoN3KbYiU/AsfJ7+nrKutedTVf6FfO9eVq
+obTSNNiasbh13St52zywH5zbsql1OBg9K2MDf8rDBMcuLxcCgcBfM9FWZivdG2tJ
+5REvL0vPAQfcjVi4HUHvnaCuwMYEuF5T2Xf9P8d8ZflfWHaGlkl/qPvE897fns2l
+PZvvhRnr9GlHKt940ZOTI2v+hjlwcHGAAQc+p7BcKeUYLChwhVK/cZ9f6ZCotZNh
+543ecG4KZiJaqBZ/mDRaW7Py0w6lbOAzprrHF3ChvQ6VAllajoWx4CeINRcxX2vP
+bAPZxvt0gwpoHtUAsZo/bKEF0sM5qM/fK43gH5KhJeunq/xHO7E=
+-----END RSA PRIVATE KEY-----
diff --git a/board/prism/ec.tasklist b/board/prism/ec.tasklist
new file mode 100644
index 0000000000..810ef8489b
--- /dev/null
+++ b/board/prism/ec.tasklist
@@ -0,0 +1,14 @@
+/* Copyright 2016 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS_RO(RWSIG,    rwsig_task,   NULL, 1280) \
+	TASK_ALWAYS   (HOOKS,    hook_task,    NULL, 1024) \
+	TASK_ALWAYS_RW(RGBKBD, rgbkbd_task, NULL, 2048) \
+	TASK_ALWAYS   (HOSTCMD, host_command_task, NULL, 1024) \
+	TASK_ALWAYS   (CONSOLE,  console_task, NULL, 1024)
diff --git a/board/prism/gpio.inc b/board/prism/gpio.inc
new file mode 100644
index 0000000000..2b8f2ee9b8
--- /dev/null
+++ b/board/prism/gpio.inc
@@ -0,0 +1,25 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifdef SECTION_IS_RW
+
+GPIO(SDB_L,		PIN(A, 0), GPIO_OUT_LOW)
+GPIO(SPI1_CS1_L,	PIN(A, 1), GPIO_OUT_HIGH)
+GPIO(SPI1_CS2_L,	PIN(A, 2), GPIO_OUT_HIGH)
+GPIO(L_POWER,		PIN(A, 3), GPIO_OUT_LOW)
+
+/* SPI Controller: PA5, 6, 7 */
+ALTERNATE(PIN_MASK(A, 0x00e0), 0, MODULE_SPI_CONTROLLER, GPIO_PULL_UP)
+
+
+#endif /* SECTION_IS_RW */
+
+/* USART1: PA09/PA10 - Servo stm32 console UART */
+ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART, GPIO_PULL_UP)
+
+UNIMPLEMENTED(ENTERING_RW)
+UNIMPLEMENTED(WP_L)
diff --git a/board/puff/board.c b/board/puff/board.c
index c034e06e45..7e5c2ad8e6 100644
--- a/board/puff/board.c
+++ b/board/puff/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,10 +6,9 @@
 /* Puff board-specific configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "button.h"
 #include "charge_manager.h"
-#include "charge_state_v2.h"
+#include "charge_state.h"
 #include "chipset.h"
 #include "common.h"
 #include "core/cortex-m/cpu.h"
@@ -37,8 +36,8 @@
 #include "system.h"
 #include "task.h"
 #include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
 #include "thermal.h"
-#include "thermistor.h"
 #include "uart.h"
 #include "usb_charge.h"
 #include "usb_common.h"
@@ -46,8 +45,8 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void power_monitor(void);
 DECLARE_DEFERRED(power_monitor);
@@ -89,8 +88,8 @@ uint16_t tcpc_get_alert_status(void)
 }
 
 /* Called when the charge manager has switched to a new port. */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
 {
 	/* Blink alert if insufficient power per system_can_boot_ap(). */
 	int insufficient_power =
@@ -106,14 +105,14 @@ static int32_t base_5v_power;
  * Power usage for each port as measured or estimated.
  * Units are milliwatts (5v x ma current)
  */
-#define PWR_BASE_LOAD	(5*1335)
-#define PWR_FRONT_HIGH	(5*1603)
-#define PWR_FRONT_LOW	(5*963)
-#define PWR_REAR	(5*1075)
-#define PWR_HDMI	(5*562)
-#define PWR_C_HIGH	(5*3740)
-#define PWR_C_LOW	(5*2090)
-#define PWR_MAX		(5*10000)
+#define PWR_BASE_LOAD (5 * 1335)
+#define PWR_FRONT_HIGH (5 * 1603)
+#define PWR_FRONT_LOW (5 * 963)
+#define PWR_REAR (5 * 1075)
+#define PWR_HDMI (5 * 562)
+#define PWR_C_HIGH (5 * 3740)
+#define PWR_C_LOW (5 * 2090)
+#define PWR_MAX (5 * 10000)
 
 /*
  * Update the 5V power usage, assuming no throttling,
@@ -186,16 +185,14 @@ static const struct {
 	int current;
 } bj_power[] = {
 	{ /* 0 - 65W (also default) */
-	.voltage = 19000,
-	.current = 3420
-	},
+	  .voltage = 19000,
+	  .current = 3420 },
 	{ /* 1 - 90W */
-	.voltage = 19000,
-	.current = 4740
-	},
+	  .voltage = 19000,
+	  .current = 4740 },
 };
 
-#define ADP_DEBOUNCE_MS		1000  /* Debounce time for BJ plug/unplug */
+#define ADP_DEBOUNCE_MS 1000 /* Debounce time for BJ plug/unplug */
 /* Debounced connection state of the barrel jack */
 static int8_t adp_connected = -1;
 static void adp_connect_deferred(void)
@@ -238,31 +235,29 @@ static void adp_state_init(void)
 	/* Report charge state from the barrel jack. */
 	adp_connect_deferred();
 }
-DECLARE_HOOK(HOOK_INIT, adp_state_init, HOOK_PRIO_CHARGE_MANAGER_INIT + 1);
-
+DECLARE_HOOK(HOOK_INIT, adp_state_init, HOOK_PRIO_INIT_CHARGE_MANAGER + 1);
 
-#include "gpio_list.h" /* Must come after other header files. */
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
 
 /******************************************************************************/
 /* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
+const struct spi_device_t spi_devices[] = {};
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
 /******************************************************************************/
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN]        = { .channel = 5,
-				.flags = PWM_CONFIG_OPEN_DRAIN,
-				.freq = 25000},
-	[PWM_CH_LED_RED]    = { .channel = 0,
-				.flags = PWM_CONFIG_ACTIVE_LOW |
-					 PWM_CONFIG_DSLEEP,
-				.freq = 2000 },
-	[PWM_CH_LED_GREEN]  = { .channel = 2,
-				.flags = PWM_CONFIG_ACTIVE_LOW |
-					 PWM_CONFIG_DSLEEP,
-				.freq = 2000 },
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
+	[PWM_CH_LED_RED] = { .channel = 0,
+			     .flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+			     .freq = 2000 },
+	[PWM_CH_LED_GREEN] = { .channel = 2,
+			       .flags = PWM_CONFIG_ACTIVE_LOW |
+					PWM_CONFIG_DSLEEP,
+			       .freq = 2000 },
 };
 
 /******************************************************************************/
@@ -278,22 +273,44 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.flags = TCPC_FLAGS_RESET_ACTIVE_HIGH,
 	},
 };
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_TCPC_0] = {
-		.usb_port = USB_PD_PORT_TCPC_0,
-		.driver = &anx7447_usb_mux_driver,
-		.hpd_update = &anx7447_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_0,
+			.driver = &anx7447_usb_mux_driver,
+			.hpd_update = &anx7447_tcpc_update_hpd_status,
+		},
 	},
 };
 
 /******************************************************************************/
 /* I2C port map configuration */
 const struct i2c_port_t i2c_ports[] = {
-	{"ina",     I2C_PORT_INA,     400, GPIO_I2C0_SCL, GPIO_I2C0_SDA},
-	{"ppc0",    I2C_PORT_PPC0,    400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"tcpc0",   I2C_PORT_TCPC0,   400, GPIO_I2C3_SCL, GPIO_I2C3_SDA},
-	{"power",   I2C_PORT_POWER,   400, GPIO_I2C5_SCL, GPIO_I2C5_SDA},
-	{"eeprom",  I2C_PORT_EEPROM,  400, GPIO_I2C7_SCL, GPIO_I2C7_SDA},
+	{ .name = "ina",
+	  .port = I2C_PORT_INA,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_SCL,
+	  .sda = GPIO_I2C0_SDA },
+	{ .name = "ppc0",
+	  .port = I2C_PORT_PPC0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 400,
+	  .scl = GPIO_I2C5_SCL,
+	  .sda = GPIO_I2C5_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_I2C7_SCL,
+	  .sda = GPIO_I2C7_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -349,15 +366,14 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
 /******************************************************************************/
 /* Wake up pins */
-const enum gpio_signal hibernate_wake_pins[] = {
-};
+const enum gpio_signal hibernate_wake_pins[] = {};
 const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 
 /******************************************************************************/
 /* Physical fans. These are logically separate from pwm_channels. */
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = -1,
 };
@@ -376,42 +392,52 @@ BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
 /******************************************************************************/
 /* MFT channels. These are logically separate from pwm_channels. */
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN },
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 /******************************************************************************/
 /* Thermal control; drive fan based on temperature sensors. */
-const static struct ec_thermal_config thermal_a = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(68),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(78),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(58),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(41),
-	.temp_fan_max = C_TO_K(72),
-};
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_A                \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(68), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(78), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(58), \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+		.temp_fan_off = C_TO_K(41), \
+		.temp_fan_max = C_TO_K(72), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A;
 
-const static struct ec_thermal_config thermal_b = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(78),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(85),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-};
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_B                \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(78), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(85), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_b = THERMAL_B;
 
 struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_CORE] = thermal_a,
+	[TEMP_SENSOR_CORE] = THERMAL_A,
 };
 BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
 
@@ -480,7 +506,7 @@ static void board_init(void)
 	 * button is not available.
 	 */
 	if (board_version < 2)
-		button_disable_gpio(GPIO_EC_RECOVERY_BTN_ODL);
+		button_disable_gpio(BUTTON_RECOVERY);
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
@@ -498,16 +524,13 @@ static void board_chipset_startup(void)
 	if (ppc_is_sourcing_vbus(0))
 		ppc_vbus_source_enable(0, 1);
 }
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup,
-	     HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
 /******************************************************************************/
 /* USB-C PPC Configuration */
 struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.i2c_port = I2C_PORT_PPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
+	[USB_PD_PORT_TCPC_0] = { .i2c_port = I2C_PORT_PPC0,
+				 .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+				 .drv = &sn5s330_drv },
 };
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
@@ -540,14 +563,12 @@ static void board_tcpc_init(void)
 		/*
 		 * By default configured as output low.
 		 */
-		gpio_set_flags(GPIO_USB_A4_OC_ODL,
-			       GPIO_INPUT | GPIO_INT_BOTH);
+		gpio_set_flags(GPIO_USB_A4_OC_ODL, GPIO_INPUT | GPIO_INT_BOTH);
 		gpio_enable_interrupt(GPIO_USB_A4_OC_ODL);
 	} else {
 		/* Ensure no interrupts from pin */
 		gpio_disable_interrupt(GPIO_USB_A4_OC_ODL);
 	}
-
 }
 /* Make sure this is called after fw_config is initialised */
 DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 2);
@@ -666,8 +687,8 @@ void board_enable_s0_rails(int enable)
 
 unsigned int ec_config_get_bj_power(void)
 {
-	unsigned int bj =
-		(fw_config & EC_CFG_BJ_POWER_MASK) >> EC_CFG_BJ_POWER_L;
+	unsigned int bj = (fw_config & EC_CFG_BJ_POWER_MASK) >>
+			  EC_CFG_BJ_POWER_L;
 	/* Out of range value defaults to 0 */
 	if (bj >= ARRAY_SIZE(bj_power))
 		bj = 0;
@@ -742,23 +763,23 @@ DECLARE_HOOK(HOOK_INIT, setup_thermal, HOOK_PRIO_DEFAULT - 1);
  *
  *  All measurements are in milliwatts.
  */
-#define THROT_TYPE_A		BIT(0)
-#define THROT_TYPE_C		BIT(1)
-#define THROT_PROCHOT		BIT(2)
+#define THROT_TYPE_A BIT(0)
+#define THROT_TYPE_C BIT(1)
+#define THROT_PROCHOT BIT(2)
 
 /*
  * Power gain if front USB A ports are limited.
  */
-#define POWER_GAIN_TYPE_A	3200
+#define POWER_GAIN_TYPE_A 3200
 /*
  * Power gain if Type C port is limited.
  */
-#define POWER_GAIN_TYPE_C	8800
+#define POWER_GAIN_TYPE_C 8800
 /*
  * Power is averaged over 10 ms, with a reading every 2 ms.
  */
-#define POWER_DELAY_MS		2
-#define POWER_READINGS		(10/POWER_DELAY_MS)
+#define POWER_DELAY_MS 2
+#define POWER_READINGS (10 / POWER_DELAY_MS)
 
 static void power_monitor(void)
 {
@@ -773,8 +794,7 @@ static void power_monitor(void)
 	 * If CPU is off or suspended, no need to throttle
 	 * or restrict power.
 	 */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF |
-			     CHIPSET_STATE_SUSPEND)) {
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF | CHIPSET_STATE_SUSPEND)) {
 		/*
 		 * Slow down monitoring, assume no throttling required.
 		 */
@@ -802,7 +822,7 @@ static void power_monitor(void)
 			 */
 			power = (adc_read_channel(ADC_VBUS) *
 				 adc_read_channel(ADC_PPVAR_IMON)) /
-				 1000;
+				1000;
 			/* Init power table */
 			if (history[0] == 0) {
 				for (i = 0; i < POWER_READINGS; i++)
@@ -829,8 +849,7 @@ static void power_monitor(void)
 			 * For barrel-jack supplies, the rating can be
 			 * exceeded briefly, so use the average.
 			 */
-			if (charge_manager_get_supplier() ==
-			    CHARGE_SUPPLIER_PD)
+			if (charge_manager_get_supplier() == CHARGE_SUPPLIER_PD)
 				power = max;
 			else
 				power = total / POWER_READINGS;
@@ -922,8 +941,9 @@ static void power_monitor(void)
 		gpio_set_level(GPIO_EC_PROCHOT_ODL, prochot);
 	}
 	if (diff & THROT_TYPE_C) {
-		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C)
-			? TYPEC_RP_1A5 : TYPEC_RP_3A0;
+		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C) ?
+						TYPEC_RP_1A5 :
+						TYPEC_RP_3A0;
 
 		ppc_set_vbus_source_current_limit(0, rp);
 		tcpm_select_rp_value(0, rp);
diff --git a/board/puff/board.h b/board/puff/board.h
index 57284761fa..59c177c604 100644
--- a/board/puff/board.h
+++ b/board/puff/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,11 +12,11 @@
 #define CONFIG_UART_TX_BUF_SIZE 4096
 
 /* NPCX7 config */
-#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
-#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
+#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */
+#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */
 
 /* Internal SPI flash on NPCX796FC is 512 kB */
-#define CONFIG_FLASH_SIZE (512 * 1024)
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
 #define CONFIG_SPI_FLASH_REGS
 #define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
 
@@ -31,16 +31,16 @@
 /* TODO: (b/143496253) re-enable CEC */
 /* #define CONFIG_CEC */
 #define CONFIG_CRC8
-#define CONFIG_CROS_BOARD_INFO
+#define CONFIG_CBI_EEPROM
 #define CONFIG_EMULATED_SYSRQ
 #undef CONFIG_KEYBOARD_BOOT_KEYS
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
+#define CONFIG_MKBP_INPUT_DEVICES
 #define CONFIG_MKBP_USE_HOST_EVENT
 #undef CONFIG_KEYBOARD_RUNTIME_KEYS
 #undef CONFIG_HIBERNATE
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 #define CONFIG_LED_COMMON
-#undef  CONFIG_LID_SWITCH
+#undef CONFIG_LID_SWITCH
 #define CONFIG_LTO
 #define CONFIG_PWM
 #define CONFIG_VBOOT_EFS2
@@ -49,9 +49,6 @@
 #define CONFIG_VSTORE_SLOT_COUNT 1
 #define CONFIG_SHA256
 
-#define CONFIG_SUPPRESSED_HOST_COMMANDS \
-	EC_CMD_CONSOLE_SNAPSHOT, EC_CMD_CONSOLE_READ, EC_CMD_PD_GET_LOG_ENTRY
-
 /* EC Commands */
 #define CONFIG_CMD_BUTTON
 /* Include CLI command needed to support CCD testing. */
@@ -88,7 +85,7 @@
 #define CONFIG_CPU_PROCHOT_ACTIVE_LOW
 
 /* Dedicated barreljack charger port */
-#undef  CONFIG_DEDICATED_CHARGE_PORT_COUNT
+#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT
 #define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1
 #define DEDICATED_CHARGE_PORT 1
 
@@ -107,21 +104,22 @@
 #define CONFIG_INA3221
 
 /* b/143501304 */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	4000	/* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	2000	/* us */
-#define PD_VCONN_SWAP_DELAY		8000	/* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 4000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 2000 /* us */
+#undef CONFIG_USBC_VCONN_SWAP_DELAY_US
+#define CONFIG_USBC_VCONN_SWAP_DELAY_US 8000 /* us */
 
-#define PD_OPERATING_POWER_MW	CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
-#define PD_MAX_POWER_MW		100000
-#define PD_MAX_CURRENT_MA	5000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
+#define PD_MAX_POWER_MW 100000
+#define PD_MAX_CURRENT_MA 5000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Fan and temp. */
 #define CONFIG_FANS 1
 #undef CONFIG_FAN_INIT_SPEED
 #define CONFIG_FAN_INIT_SPEED 0
 #define CONFIG_TEMP_SENSOR
-#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_ROA_RAILS
+#define CONFIG_TEMP_SENSOR_POWER
 #define CONFIG_THERMISTOR
 #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
 #define CONFIG_THROTTLE_AP
@@ -138,13 +136,12 @@
 #define CONFIG_USB_PD_DECODE_SOP
 #undef CONFIG_USB_CHARGER
 #define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PID		0x5040
+#define CONFIG_USB_PID 0x5040
 #define CONFIG_USB_PD_ALT_MODE
 #define CONFIG_USB_PD_ALT_MODE_DFP
 #define CONFIG_USB_PD_DISCHARGE_PPC
 #define CONFIG_USB_PD_DUAL_ROLE
 #define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT TYPEC_RP_3A0
 #define CONFIG_USB_PD_PORT_MAX_COUNT 1
 #define CONFIG_USB_PD_VBUS_DETECT_PPC
 #define CONFIG_USBC_PPC_SN5S330
@@ -159,7 +156,7 @@
 #define CONFIG_USBC_VCONN
 #define CONFIG_USBC_VCONN_SWAP
 
-#define USB_PD_PORT_TCPC_0	0
+#define USB_PD_PORT_TCPC_0 0
 #define BOARD_TCPC_C0_RESET_HOLD_DELAY ANX74XX_RESET_HOLD_MS
 #define BOARD_TCPC_C0_RESET_POST_DELAY ANX74XX_RESET_HOLD_MS
 
@@ -170,16 +167,19 @@
 
 /* I2C Bus Configuration */
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
-#define I2C_PORT_INA		NPCX_I2C_PORT0_0
-#define I2C_PORT_PPC0		NPCX_I2C_PORT1_0
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT3_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define CONFIG_I2C_CONTROLLER
+#define I2C_PORT_INA NPCX_I2C_PORT0_0
+#define I2C_PORT_PPC0 NPCX_I2C_PORT1_0
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT3_0
+#define I2C_PORT_POWER NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 
 #define PP5000_PGOOD_POWER_SIGNAL_MASK POWER_SIGNAL_MASK(PP5000_A_PGOOD)
 
+/* Include math_util for bitmask_uint64 used in pd_timers */
+#define CONFIG_MATH_UTIL
+
 #ifndef __ASSEMBLER__
 
 #include "gpio_signal.h"
@@ -191,11 +191,11 @@ enum charge_port {
 };
 
 enum adc_channel {
-	ADC_SNS_PP3300,     /* ADC2 */
-	ADC_SNS_PP1050,     /* ADC7 */
-	ADC_VBUS,           /* ADC4 */
-	ADC_PPVAR_IMON,     /* ADC9 */
-	ADC_TEMP_SENSOR_1,  /* ADC0 */
+	ADC_SNS_PP3300, /* ADC2 */
+	ADC_SNS_PP1050, /* ADC7 */
+	ADC_VBUS, /* ADC4 */
+	ADC_PPVAR_IMON, /* ADC9 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
 	/* Number of ADC channels */
 	ADC_CH_COUNT
 };
@@ -220,11 +220,7 @@ enum mft_channel {
 	MFT_CH_COUNT,
 };
 
-enum temp_sensor_id {
-	TEMP_SENSOR_CORE,
-	TEMP_SENSOR_COUNT
-};
-
+enum temp_sensor_id { TEMP_SENSOR_CORE, TEMP_SENSOR_COUNT };
 
 /* Board specific handlers */
 void board_reset_pd_mcu(void);
@@ -238,20 +234,20 @@ void show_critical_error(void);
 /*
  * Barrel-jack power (4 bits).
  */
-#define EC_CFG_BJ_POWER_L		0
-#define EC_CFG_BJ_POWER_H		3
+#define EC_CFG_BJ_POWER_L 0
+#define EC_CFG_BJ_POWER_H 3
 #define EC_CFG_BJ_POWER_MASK GENMASK(EC_CFG_BJ_POWER_H, EC_CFG_BJ_POWER_L)
 /*
  * USB Connector 4 not present (1 bit).
  */
-#define EC_CFG_NO_USB4_L		4
-#define EC_CFG_NO_USB4_H		4
+#define EC_CFG_NO_USB4_L 4
+#define EC_CFG_NO_USB4_H 4
 #define EC_CFG_NO_USB4_MASK GENMASK(EC_CFG_NO_USB4_H, EC_CFG_NO_USB4_L)
 /*
  * Thermal solution config (3 bits).
  */
-#define EC_CFG_THERMAL_L		5
-#define EC_CFG_THERMAL_H		7
+#define EC_CFG_THERMAL_L 5
+#define EC_CFG_THERMAL_H 7
 #define EC_CFG_THERMAL_MASK GENMASK(EC_CFG_THERMAL_H, EC_CFG_THERMAL_L)
 
 unsigned int ec_config_get_bj_power(void);
@@ -261,29 +257,30 @@ unsigned int ec_config_get_thermal_solution(void);
 #endif /* !__ASSEMBLER__ */
 
 /* Pin renaming */
-#define GPIO_WP_L               GPIO_EC_WP_ODL
-#define GPIO_PP5000_A_PG_OD     GPIO_PG_PP5000_A_OD
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
-#define GPIO_RECOVERY_L         GPIO_EC_RECOVERY_BTN_ODL
-#define GPIO_RECOVERY_L_2       GPIO_H1_EC_RECOVERY_BTN_ODL
-#define GPIO_POWER_BUTTON_L	GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_PCH_WAKE_L		GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L	GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_ENTERING_RW	GPIO_EC_ENTERING_RW
-#define GPIO_SYS_RESET_L	GPIO_SYS_RST_ODL
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_PCH_RTCRST		GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_AC_PRESENT		GPIO_BJ_ADP_PRESENT_L
+#define GPIO_WP_L GPIO_EC_WP_ODL
+#define GPIO_PP5000_A_PG_OD GPIO_PG_PP5000_A_OD
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
+#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_ODL
+#define GPIO_RECOVERY_L_2 GPIO_H1_EC_RECOVERY_BTN_ODL
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_EN_ROA_RAILS
+#define GPIO_AC_PRESENT GPIO_BJ_ADP_PRESENT_L
 
 /*
  * There is no RSMRST input, so alias it to the output. This short-circuits
  * common_intel_x86_handle_rsmrst.
  */
-#define GPIO_RSMRST_L_PGOOD	GPIO_PCH_RSMRST_L
+#define GPIO_PG_EC_RSMRST_ODL GPIO_PCH_RSMRST_L
 
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/puff/build.mk b/board/puff/build.mk
index e9968d5710..3edfc84c2f 100644
--- a/board/puff/build.mk
+++ b/board/puff/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/puff/ec.tasklist b/board/puff/ec.tasklist
index ae10417dff..d579f65fd9 100644
--- a/board/puff/ec.tasklist
+++ b/board/puff/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/puff/gpio.inc b/board/puff/gpio.inc
index 7e62488cee..5f7650a682 100644
--- a/board/puff/gpio.inc
+++ b/board/puff/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,12 +25,12 @@ GPIO_INT(PG_VPRIM_CORE_A_OD,   PIN(2, 3), GPIO_INT_BOTH, power_signal_interrupt)
 GPIO_INT(PG_PP1050_A_OD,       PIN(2, 2), GPIO_INT_BOTH, power_signal_interrupt)
 /* EC output, but also interrupt so this can be polled as a power signal */
 GPIO_INT(EC_PCH_RSMRST_L,      PIN(A, 6), GPIO_OUTPUT | GPIO_INT_F_RISING | GPIO_INT_F_FALLING, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(PG_PP2500_DRAM_U_OD,  PIN(2, 0), GPIO_INT_BOTH, power_signal_interrupt)
 GPIO_INT(PG_PP1200_U_OD,       PIN(2, 1), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, slp_s3_interrupt)
 #endif
 GPIO_INT(PG_PP950_VCCIO_OD,    PIN(1, 7), GPIO_INT_BOTH, power_signal_interrupt)
@@ -64,7 +64,7 @@ GPIO_INT(USB_A4_OC_ODL,        PIN(B, 0), GPIO_OUT_LOW | GPIO_INT_BOTH, port_ocp
 GPIO(EC_PCH_PWROK,             PIN(0, 5), GPIO_OUT_LOW)
 GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
 GPIO(EC_PCH_PWR_BTN_ODL,       PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_ODR_HIGH)
+GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_OUT_LOW)
 GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
 GPIO(EC_PROCHOT_IN_OD,         PIN(3, 4), GPIO_INPUT)
 GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
diff --git a/board/puff/led.c b/board/puff/led.c
index ba87f05460..9cca110467 100644
--- a/board/puff/led.c
+++ b/board/puff/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,16 +19,16 @@
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
 
 /*
  * Due to the CSME-Lite processing, upon startup the CPU transitions through
  * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so
  * delay turning off the LED during suspend/shutdown.
  */
-#define LED_CPU_DELAY_MS	(2000 * MSEC)
+#define LED_CPU_DELAY_MS (2000 * MSEC)
 
-const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 enum led_color {
@@ -89,9 +89,9 @@ static int set_color(enum ec_led_id id, enum led_color color, int duty)
 	}
 }
 
-#define LED_PULSE_US		(2 * SECOND)
+#define LED_PULSE_US (2 * SECOND)
 /* 40 msec for nice and smooth transition. */
-#define LED_PULSE_TICK_US	(40 * MSEC)
+#define LED_PULSE_TICK_US (40 * MSEC)
 
 /* When pulsing is enabled, brightness is incremented by <duty_inc> every
  * <interval> usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented
@@ -214,7 +214,7 @@ void show_critical_error(void)
 		set_color(EC_LED_ID_POWER_LED, LED_RED, 100);
 }
 
-static int command_led(int argc, char **argv)
+static int command_led(int argc, const char **argv)
 {
 	enum ec_led_id id = EC_LED_ID_POWER_LED;
 
diff --git a/board/puff/usb_pd_policy.c b/board/puff/usb_pd_policy.c
index f3b9146b0b..e3fc86c8ca 100644
--- a/board/puff/usb_pd_policy.c
+++ b/board/puff/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,16 +12,15 @@
 #include "ec_commands.h"
 #include "gpio.h"
 #include "system.h"
-#include "tcpci.h"
-#include "tcpm.h"
+#include "tcpm/tcpci.h"
+#include "tcpm/tcpm.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
@@ -42,11 +41,6 @@ void pd_power_supply_reset(int port)
 	if (prev_en)
 		pd_set_vbus_discharge(port, 1);
 
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	/* Give back the current quota we are no longer using */
-	charge_manager_source_port(port, 0);
-#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
-
 	/* Notify host of power info change. */
 	pd_send_host_event(PD_EVENT_POWER_CHANGE);
 }
@@ -67,11 +61,6 @@ int pd_set_power_supply_ready(int port)
 	if (rv)
 		return rv;
 
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	/* Ensure we advertise the proper available current quota */
-	charge_manager_source_port(port, 1);
-#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
-
 	/* Notify host of power info change. */
 	pd_send_host_event(PD_EVENT_POWER_CHANGE);
 
diff --git a/board/puff/vif_override.xml b/board/puff/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/puff/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/quackingstick/base_detect.c b/board/quackingstick/base_detect.c
new file mode 100644
index 0000000000..f3045897d6
--- /dev/null
+++ b/board/quackingstick/base_detect.c
@@ -0,0 +1,230 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Coachz base detection code */
+
+#include "adc.h"
+#include "base_state.h"
+#include "board.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "timer.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+
+/* Base detection and debouncing */
+#define BASE_DETECT_EN_DEBOUNCE_US (350 * MSEC)
+#define BASE_DETECT_DIS_DEBOUNCE_US (20 * MSEC)
+
+/*
+ * If the base status is unclear (i.e. not within expected ranges, read
+ * the ADC value again every 500ms.
+ */
+#define BASE_DETECT_RETRY_US (500 * MSEC)
+
+/*
+ * Lid has 604K pull-up, base has 30.1K pull-down, so the
+ * ADC value should be around 30.1/(604+30.1)*3300 = 156
+ *
+ * We add a significant margin on the maximum value, due to noise on the line,
+ * especially when PWM is active. See b/64193554 for details.
+ */
+#define BASE_DETECT_MIN_MV 120
+#define BASE_DETECT_MAX_MV 300
+
+/* Minimum ADC value to indicate base is disconnected for sure */
+#define BASE_DETECT_DISCONNECT_MIN_MV 1500
+
+/*
+ * Base EC pulses detection pin for 500 us to signal out of band USB wake (that
+ * can be used to wake system from deep S3).
+ */
+#define BASE_DETECT_PULSE_MIN_US 400
+#define BASE_DETECT_PULSE_MAX_US 650
+
+static uint64_t base_detect_debounce_time;
+
+static void base_detect_deferred(void);
+DECLARE_DEFERRED(base_detect_deferred);
+
+enum base_status {
+	BASE_UNKNOWN = 0,
+	BASE_DISCONNECTED = 1,
+	BASE_CONNECTED = 2,
+};
+
+static enum base_status current_base_status;
+
+/*
+ * This function is called whenever there is a change in the base detect
+ * status. Actions taken include:
+ * 1. Change in power to base
+ * 2. Indicate mode change to host.
+ * 3. Indicate tablet mode to host. Current assumption is that if base is
+ * disconnected then the system is in tablet mode, else if the base is
+ * connected, then the system is not in tablet mode.
+ */
+static void base_detect_change(enum base_status status)
+{
+	int connected = (status == BASE_CONNECTED);
+
+	if (current_base_status == status)
+		return;
+
+	gpio_set_level(GPIO_EN_BASE, connected);
+	tablet_set_mode(!connected, TABLET_TRIGGER_BASE);
+	base_set_state(connected);
+	current_base_status = status;
+}
+
+/* Measure detection pin pulse duration (used to wake AP from deep S3). */
+static uint64_t pulse_start;
+static uint32_t pulse_width;
+
+static void print_base_detect_value(int v, int tmp_pulse_width)
+{
+	CPRINTS("%s = %d (pulse %d)", adc_channels[ADC_BASE_DET].name, v,
+		tmp_pulse_width);
+}
+
+static void base_detect_deferred(void)
+{
+	uint64_t time_now = get_time().val;
+	int v;
+	uint32_t tmp_pulse_width = pulse_width;
+
+	if (base_detect_debounce_time > time_now) {
+		hook_call_deferred(&base_detect_deferred_data,
+				   base_detect_debounce_time - time_now);
+		return;
+	}
+
+	v = adc_read_channel(ADC_BASE_DET);
+	if (v == ADC_READ_ERROR)
+		return;
+
+	print_base_detect_value(v, tmp_pulse_width);
+
+	if (v >= BASE_DETECT_MIN_MV && v <= BASE_DETECT_MAX_MV) {
+		if (current_base_status != BASE_CONNECTED) {
+			base_detect_change(BASE_CONNECTED);
+		} else if (tmp_pulse_width >= BASE_DETECT_PULSE_MIN_US &&
+			   tmp_pulse_width <= BASE_DETECT_PULSE_MAX_US) {
+			CPRINTS("Sending event to AP");
+			host_set_single_event(EC_HOST_EVENT_KEY_PRESSED);
+		}
+		return;
+	}
+
+	if (v >= BASE_DETECT_DISCONNECT_MIN_MV) {
+		base_detect_change(BASE_DISCONNECTED);
+		return;
+	}
+
+	/* Unclear base status, schedule again in a while. */
+	hook_call_deferred(&base_detect_deferred_data, BASE_DETECT_RETRY_US);
+}
+
+static inline int detect_pin_connected(enum gpio_signal det_pin)
+{
+	return gpio_get_level(det_pin) == 0;
+}
+
+void base_detect_interrupt(enum gpio_signal signal)
+{
+	uint64_t time_now = get_time().val;
+	int debounce_us;
+
+	if (detect_pin_connected(signal))
+		debounce_us = BASE_DETECT_EN_DEBOUNCE_US;
+	else
+		debounce_us = BASE_DETECT_DIS_DEBOUNCE_US;
+
+	if (base_detect_debounce_time <= time_now) {
+		/*
+		 * Detect and measure detection pin pulse, when base is
+		 * connected. Only a single pulse is measured over a debounce
+		 * period. If no pulse, or multiple pulses are detected,
+		 * pulse_width is set to 0.
+		 */
+		if (current_base_status == BASE_CONNECTED &&
+		    !detect_pin_connected(signal)) {
+			pulse_start = time_now;
+		} else {
+			pulse_start = 0;
+		}
+		pulse_width = 0;
+
+		hook_call_deferred(&base_detect_deferred_data, debounce_us);
+	} else {
+		if (current_base_status == BASE_CONNECTED &&
+		    detect_pin_connected(signal) && !pulse_width &&
+		    pulse_start) {
+			/* First pulse within period. */
+			pulse_width = time_now - pulse_start;
+		} else {
+			pulse_start = 0;
+			pulse_width = 0;
+		}
+	}
+
+	base_detect_debounce_time = time_now + debounce_us;
+}
+
+static void base_enable(void)
+{
+	/* Enable base detection interrupt. */
+	base_detect_debounce_time = get_time().val;
+	hook_call_deferred(&base_detect_deferred_data, 0);
+	gpio_enable_interrupt(GPIO_BASE_DET_L);
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, base_enable, HOOK_PRIO_DEFAULT);
+
+static void base_disable(void)
+{
+	/*
+	 * Disable base detection interrupt and disable power to base.
+	 * Set the state UNKNOWN so the next startup will initialize a
+	 * correct state and notify AP.
+	 */
+	gpio_disable_interrupt(GPIO_BASE_DET_L);
+	base_detect_change(BASE_UNKNOWN);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, base_disable, HOOK_PRIO_DEFAULT);
+
+static void base_init(void)
+{
+	/*
+	 * If we jumped to this image and chipset is already in S0, enable
+	 * base.
+	 */
+	if (system_jumped_late() && chipset_in_state(CHIPSET_STATE_ON))
+		base_enable();
+}
+DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT + 1);
+
+void base_force_state(enum ec_set_base_state_cmd state)
+{
+	if (state == EC_SET_BASE_STATE_ATTACH) {
+		gpio_disable_interrupt(GPIO_BASE_DET_L);
+		base_detect_change(BASE_CONNECTED);
+		CPRINTS("BD forced connected");
+	} else if (state == EC_SET_BASE_STATE_DETACH) {
+		gpio_disable_interrupt(GPIO_BASE_DET_L);
+		base_detect_change(BASE_DISCONNECTED);
+		CPRINTS("BD forced disconnected");
+	} else {
+		base_enable();
+		CPRINTS("BD forced reset");
+	}
+}
diff --git a/board/quackingstick/battery.c b/board/quackingstick/battery.c
new file mode 100644
index 0000000000..5376e74dc5
--- /dev/null
+++ b/board/quackingstick/battery.c
@@ -0,0 +1,97 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "common.h"
+#include "util.h"
+
+/*
+ * Battery info for all quackingstick battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+
+const struct board_batt_params board_battery_info[] = {
+	/* COSMX AP21CBI Battery information */
+	[BATTERY_AP21CBI] = {
+		.fuel_gauge = {
+			.manuf_name = "COSMX KT0020B001",
+			.device_name = "AP21CBI",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.reg_addr = 0x0,
+				.reg_mask = 0x8000,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max            = 8800, /* mV */
+			.voltage_normal         = 7700, /* mV */
+			.voltage_min            = 6000, /* mV */
+			.precharge_current      = 256,  /* mA */
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 50,
+			.charging_min_c         = 0,
+			.charging_max_c         = 60,
+			.discharging_min_c      = -20,
+			.discharging_max_c      = 75,
+			.vendor_param_start     = 0x70,
+		},
+	},
+	/* COSMX AP21CBI Battery information */
+	[BATTERY_AP21CBI_VER0] = {
+		.fuel_gauge = {
+			.manuf_name = "AP21CBI",
+			.device_name = "COSMX KT0020B001",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.reg_addr = 0x0,
+				.reg_mask = 0x8000,
+				.disconnect_val = 0x0,
+			}
+		},
+		.batt_info = {
+			.voltage_max            = 8800, /* mV */
+			.voltage_normal         = 7700, /* mV */
+			.voltage_min            = 6000, /* mV */
+			.precharge_current      = 256,  /* mA */
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 50,
+			.charging_min_c         = 0,
+			.charging_max_c         = 60,
+			.discharging_min_c      = -20,
+			.discharging_max_c      = 75,
+			.vendor_param_start     = 0x70,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_AP21CBI;
diff --git a/board/quackingstick/board.c b/board/quackingstick/board.c
new file mode 100644
index 0000000000..2cb1ac37e5
--- /dev/null
+++ b/board/quackingstick/board.c
@@ -0,0 +1,668 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Coachz board-specific configuration */
+
+#include "adc_chip.h"
+#include "button.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "common.h"
+#include "driver/accel_bma2x2.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "driver/accelgyro_icm42607.h"
+#include "driver/accelgyro_icm_common.h"
+#include "driver/ppc/sn5s330.h"
+#include "driver/tcpm/ps8xxx.h"
+#include "driver/tcpm/tcpci.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "lid_switch.h"
+#include "mkbp_input_devices.h"
+#include "peripheral_charger.h"
+#include "pi3usb9201.h"
+#include "power.h"
+#include "power/qcom.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "queue.h"
+#include "shi_chip.h"
+#include "switch.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
+#include "thermal.h"
+#include "usbc_ppc.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+#define KS_DEBOUNCE_US (30 * MSEC) /* Debounce time for kickstand switch */
+
+/* Forward declaration */
+static void tcpc_alert_event(enum gpio_signal signal);
+static void usb0_evt(enum gpio_signal signal);
+static void ppc_interrupt(enum gpio_signal signal);
+static void board_connect_c0_sbu(enum gpio_signal s);
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* GPIO Interrupt Handlers */
+static void tcpc_alert_event(enum gpio_signal signal)
+{
+	int port = -1;
+
+	switch (signal) {
+	case GPIO_USB_C0_PD_INT_ODL:
+		port = 0;
+		break;
+	default:
+		return;
+	}
+
+	schedule_deferred_pd_interrupt(port);
+}
+
+static void usb0_evt(enum gpio_signal signal)
+{
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+
+static void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_SWCTL_INT_ODL:
+		sn5s330_interrupt(0);
+		break;
+	default:
+		break;
+	}
+}
+
+static void board_connect_c0_sbu_deferred(void)
+{
+	/*
+	 * If CCD_MODE_ODL asserts, it means there's a debug accessory connected
+	 * and we should enable the SBU FETs.
+	 */
+	ppc_set_sbu(0, 1);
+}
+DECLARE_DEFERRED(board_connect_c0_sbu_deferred);
+
+static void board_connect_c0_sbu(enum gpio_signal s)
+{
+	hook_call_deferred(&board_connect_c0_sbu_deferred_data, 0);
+}
+
+/* I2C port map */
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_POWER_SCL,
+	  .sda = GPIO_EC_I2C_POWER_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C0_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C0_PD_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_EEPROM_SCL,
+	  .sda = GPIO_EC_I2C_EEPROM_SDA },
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_SENSOR_SCL,
+	  .sda = GPIO_EC_I2C_SENSOR_SDA },
+};
+
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	/* Measure VBUS through a 1/10 voltage divider */
+	[ADC_VBUS] = {
+		"VBUS",
+		NPCX_ADC_CH1,
+		ADC_MAX_VOLT * 10,
+		ADC_READ_MAX + 1,
+		0
+	},
+	/*
+	 * Adapter current output or battery charging/discharging current (uV)
+	 * 18x amplification on charger side.
+	 */
+	[ADC_AMON_BMON] = {
+		"AMON_BMON",
+		NPCX_ADC_CH2,
+		ADC_MAX_VOLT * 1000 / 18,
+		ADC_READ_MAX + 1,
+		0
+	},
+	/*
+	 * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read
+	 * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and
+	 * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we
+	 * only divide by 2 (enough to avoid precision issues).
+	 */
+	[ADC_PSYS] = {
+		"PSYS",
+		NPCX_ADC_CH3,
+		ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1),
+		2,
+		0
+	},
+	/* Base detection */
+	[ADC_BASE_DET] = {
+		"BASE_DET",
+		NPCX_ADC_CH5,
+		ADC_MAX_VOLT,
+		ADC_READ_MAX + 1,
+		0
+	},
+	[ADC_SYSTHERM2] = {
+		"SYSTHERM2",
+		NPCX_ADC_CH6,
+		ADC_MAX_VOLT,
+		ADC_READ_MAX + 1,
+		0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_SYS2] = {
+		.name = "SYSTEMP2",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_SYSTHERM2,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+const struct pwm_t pwm_channels[] = {
+	/* TODO(waihong): Assign a proper frequency. */
+	[PWM_CH_DISPLIGHT] = { .channel = 5, .flags = 0, .freq = 4800 },
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+/* Power Path Controller */
+struct ppc_config_t ppc_chips[] = {
+	{ .i2c_port = I2C_PORT_TCPC0,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
+};
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/* TCPC mux configuration */
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TCPC0,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+	},
+};
+
+/*
+ * Port-0/1 USB mux driver.
+ *
+ * The USB mux is handled by TCPC chip and the HPD update is through a GPIO
+ * to AP. But the TCPC chip is also needed to know the HPD status; otherwise,
+ * the mux misbehaves.
+ */
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
+	},
+};
+
+/* BC1.2 */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	{
+		.i2c_port = I2C_PORT_POWER,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+};
+
+/* Mutexes */
+static struct mutex g_lid_mutex;
+
+static struct bmi_drv_data_t g_bmi160_data;
+static struct icm_drv_data_t g_icm42607_data;
+
+enum lid_accelgyro_type {
+	LID_GYRO_NONE = 0,
+	LID_GYRO_BMI160 = 1,
+	LID_GYRO_ICM42607 = 2,
+};
+
+static enum lid_accelgyro_type lid_accelgyro_config;
+
+/* Matrix to rotate accelerometer into standard reference frame */
+const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+				      { FLOAT_TO_FP(-1), 0, 0 },
+				      { 0, 0, FLOAT_TO_FP(1) } };
+
+struct motion_sensor_t motion_sensors[] = {
+	/*
+	 * Note: bmi160: supports accelerometer and gyro sensor
+	 * Requirement: accelerometer sensor must init before gyro sensor
+	 * DO NOT change the order of the following table.
+	 */
+	[LID_ACCEL] = {
+	 .name = "Lid Accel",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_BMI160,
+	 .type = MOTIONSENSE_TYPE_ACCEL,
+	 .location = MOTIONSENSE_LOC_LID,
+	 .drv = &bmi160_drv,
+	 .mutex = &g_lid_mutex,
+	 .drv_data = &g_bmi160_data,
+	 .port = I2C_PORT_SENSOR,
+	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+	 .rot_standard_ref = &lid_standard_ref,
+	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
+	 .min_frequency = BMI_ACCEL_MIN_FREQ,
+	 .max_frequency = BMI_ACCEL_MAX_FREQ,
+	 .config = {
+		 [SENSOR_CONFIG_EC_S0] = {
+			 .odr = 10000 | ROUND_UP_FLAG,
+		 },
+	 },
+	},
+	[LID_GYRO] = {
+	 .name = "Gyro",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_BMI160,
+	 .type = MOTIONSENSE_TYPE_GYRO,
+	 .location = MOTIONSENSE_LOC_LID,
+	 .drv = &bmi160_drv,
+	 .mutex = &g_lid_mutex,
+	 .drv_data = &g_bmi160_data,
+	 .port = I2C_PORT_SENSOR,
+	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+	 .default_range = 1000, /* dps */
+	 .rot_standard_ref = &lid_standard_ref,
+	 .min_frequency = BMI_GYRO_MIN_FREQ,
+	 .max_frequency = BMI_GYRO_MAX_FREQ,
+	},
+};
+
+struct motion_sensor_t motion_sensors_icm[] = {
+	[LID_ACCEL] = {
+	 .name = "Lid Accel",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_ICM42607,
+	 .type = MOTIONSENSE_TYPE_ACCEL,
+	 .location = MOTIONSENSE_LOC_LID,
+	 .drv = &icm42607_drv,
+	 .mutex = &g_lid_mutex,
+	 .drv_data = &g_icm42607_data,
+	 .port = I2C_PORT_SENSOR,
+	 .i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
+	 .rot_standard_ref = NULL,
+	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
+	 .min_frequency = ICM42607_ACCEL_MIN_FREQ,
+	 .max_frequency = ICM42607_ACCEL_MAX_FREQ,
+	 .config = {
+		 [SENSOR_CONFIG_EC_S0] = {
+			 .odr = 10000 | ROUND_UP_FLAG,
+		 },
+	 },
+	},
+	[LID_GYRO] = {
+	 .name = "Gyro",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_ICM42607,
+	 .type = MOTIONSENSE_TYPE_GYRO,
+	 .location = MOTIONSENSE_LOC_LID,
+	 .drv = &icm42607_drv,
+	 .mutex = &g_lid_mutex,
+	 .drv_data = &g_icm42607_data,
+	 .port = I2C_PORT_SENSOR,
+	 .i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
+	 .default_range = 1000, /* dps */
+	 .rot_standard_ref = NULL,
+	 .min_frequency = ICM42607_GYRO_MIN_FREQ,
+	 .max_frequency = ICM42607_GYRO_MAX_FREQ,
+	},
+};
+
+const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+static void board_detect_motionsensor(void)
+{
+	int val = -1;
+
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return;
+	if (lid_accelgyro_config != LID_GYRO_NONE)
+		return;
+
+	/* Check base accelgyro chip */
+	icm_read8(&motion_sensors_icm[LID_ACCEL], ICM42607_REG_WHO_AM_I, &val);
+	if (val == ICM42607_CHIP_ICM42607P) {
+		motion_sensors[LID_ACCEL] = motion_sensors_icm[LID_ACCEL];
+		motion_sensors[LID_GYRO] = motion_sensors_icm[LID_GYRO];
+		lid_accelgyro_config = LID_GYRO_ICM42607;
+		CPRINTS("LID Accelgyro: ICM42607");
+	} else {
+		lid_accelgyro_config = LID_GYRO_BMI160;
+		CPRINTS("LID Accelgyro: BMI160");
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_detect_motionsensor,
+	     HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_INIT, board_detect_motionsensor, HOOK_PRIO_DEFAULT + 1);
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	if (lid_accelgyro_config == LID_GYRO_ICM42607)
+		icm42607_interrupt(signal);
+	else
+		bmi160_interrupt(signal);
+}
+
+/* Initialize board. */
+static void board_init(void)
+{
+	/*
+	 * The rev-1 hardware use PP1800_SENSORS as the power of the hall IC,
+	 * it cause the LID_OPEN_EC wake EC immediately when EC enter hibernate.
+	 */
+	if (system_get_board_version() <= 1) {
+		hibernate_wake_pins[0] = GPIO_AC_PRESENT;
+		hibernate_wake_pins[1] = GPIO_POWER_BUTTON_L;
+		hibernate_wake_pins[2] = GPIO_EC_RST_ODL;
+		hibernate_wake_pins_used = 3;
+	}
+
+	/* Enable BC1.2 interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_L);
+	gpio_enable_interrupt(GPIO_ACCEL_GYRO_INT_L);
+
+	/*
+	 * The H1 SBU line for CCD are behind PPC chip. The PPC internal FETs
+	 * for SBU may be disconnected after DP alt mode is off. Should enable
+	 * the CCD_MODE_ODL interrupt to make sure the SBU FETs are connected.
+	 */
+	gpio_enable_interrupt(GPIO_CCD_MODE_ODL);
+
+	/* Enable pen input detect interrupt */
+	if (system_get_board_version() >= 2)
+		gpio_enable_interrupt(GPIO_EC_PEN_PDCT_L);
+
+	/* Set the backlight duty cycle to 0. AP will override it later. */
+	pwm_set_duty(PWM_CH_DISPLIGHT, 0);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+void board_tcpc_init(void)
+{
+	/* Only reset TCPC if not sysjump */
+	if (!system_jumped_late()) {
+		/* TODO(crosbug.com/p/61098): How long do we need to wait? */
+		board_reset_pd_mcu();
+	}
+
+	/* Enable PPC interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_SWCTL_INT_ODL);
+
+	/* Enable TCPC interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
+
+	/*
+	 * Initialize HPD to low; after sysjump SOC needs to see
+	 * HPD pulse to enable video path
+	 */
+	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
+		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
+
+enum battery_present battery_is_present(void)
+{
+	static int first_check_done;
+
+	/*
+	 * b/231911921: It's found that the D-FET status is incorrect
+	 * when the battery resume from cut off. The battery needs
+	 * about 2s to ready to discharge so delay 2s before charge
+	 * manager init.
+	 */
+	if (!first_check_done) {
+		if (battery_get_disconnect_state() ==
+		    BATTERY_NOT_DISCONNECTED) {
+			CPRINTS("Delay 2s on the first power on.");
+			sleep(2);
+		}
+		first_check_done = 1;
+	}
+
+	return gpio_get_level(GPIO_BATT_PRES_ODL) ? BP_NO : BP_YES;
+}
+
+void board_hibernate(void)
+{
+	int i;
+
+	/*
+	 * Sensors are unpowered in hibernate. Apply PD to the
+	 * interrupt lines such that they don't float.
+	 */
+	gpio_set_flags(GPIO_ACCEL_GYRO_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
+
+	/*
+	 * Board rev 1+ has the hardware fix. Don't need the following
+	 * workaround.
+	 */
+	if (system_get_board_version() > 1)
+		return;
+
+	/*
+	 * Enable the PPC power sink path before EC enters hibernate;
+	 * otherwise, ACOK won't go High and can't wake EC up. Check the
+	 * bug b/170324206 for details.
+	 */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
+		ppc_vbus_sink_enable(i, 1);
+}
+
+/* Called on AP S0 -> S3 transition */
+static void board_chipset_suspend(void)
+{
+	/*
+	 * Turn off display backlight in S3. AP has its own control. The EC's
+	 * and the AP's will be AND'ed together in hardware.
+	 */
+	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 0);
+	pwm_enable(PWM_CH_DISPLIGHT, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S3 -> S0 transition */
+static void board_chipset_resume(void)
+{
+	/* Turn on display and keyboard backlight in S0. */
+	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 1);
+	if (pwm_get_duty(PWM_CH_DISPLIGHT))
+		pwm_enable(PWM_CH_DISPLIGHT, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
+
+void board_set_switchcap_power(int enable)
+{
+	gpio_set_level(GPIO_SWITCHCAP_ON, enable);
+}
+
+int board_is_switchcap_enabled(void)
+{
+	return gpio_get_level(GPIO_SWITCHCAP_ON);
+}
+
+int board_is_switchcap_power_good(void)
+{
+	return gpio_get_level(GPIO_DA9313_GPIO0);
+}
+
+void board_reset_pd_mcu(void)
+{
+	cprints(CC_USB, "Resetting TCPCs...");
+	cflush();
+
+	gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
+	msleep(PS8XXX_RESET_DELAY_MS);
+	gpio_set_level(GPIO_USB_C0_PD_RST_L, 1);
+}
+
+void board_set_tcpc_power_mode(int port, int mode)
+{
+	/* Ignore the "mode" to turn the chip on.  We can only do a reset. */
+	if (mode)
+		return;
+
+	board_reset_pd_mcu();
+}
+
+int board_vbus_sink_enable(int port, int enable)
+{
+	/* Both ports are controlled by PPC SN5S330 */
+	return ppc_vbus_sink_enable(port, enable);
+}
+
+int board_is_sourcing_vbus(int port)
+{
+	/* Both ports are controlled by PPC SN5S330 */
+	return ppc_is_sourcing_vbus(port);
+}
+
+void board_overcurrent_event(int port, int is_overcurrented)
+{
+	/* TODO(b/120231371): Notify AP */
+	CPRINTS("p%d: overcurrent!", port);
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int i;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTS("Disabling all charging port");
+
+		/* Disable all ports. */
+		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (board_vbus_sink_enable(i, 0))
+				CPRINTS("Disabling p%d sink path failed.", i);
+		}
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (board_is_sourcing_vbus(port)) {
+		CPRINTS("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTS("New charge port: p%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		if (i == port)
+			continue;
+
+		if (board_vbus_sink_enable(i, 0))
+			CPRINTS("p%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (board_vbus_sink_enable(port, 1)) {
+		CPRINTS("p%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
+{
+	/*
+	 * Ignore lower charge ceiling on PD transition if our battery is
+	 * critical, as we may brownout.
+	 */
+	if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 &&
+	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
+		CPRINTS("Using max ilim %d", max_ma);
+		charge_ma = max_ma;
+	}
+
+	charge_set_input_current_limit(charge_ma, charge_mv);
+}
+
+/**
+ * Handle debounced pen input changing state.
+ */
+static void pen_input_deferred(void)
+{
+	bool pen_charge_enable = !gpio_get_level(GPIO_EC_PEN_PDCT_L) &&
+				 !chipset_in_state(CHIPSET_STATE_ANY_OFF);
+
+	gpio_set_level(GPIO_PEN_PWR_EN, pen_charge_enable);
+
+	CPRINTS("Pen charge %sable", pen_charge_enable ? "en" : "dis");
+}
+DECLARE_DEFERRED(pen_input_deferred);
+
+void pen_input_interrupt(enum gpio_signal signal)
+{
+	/* pen input debounce time */
+	hook_call_deferred(&pen_input_deferred_data, (100 * MSEC));
+}
+
+static void pen_charge_check(void)
+{
+	hook_call_deferred(&pen_input_deferred_data, (100 * MSEC));
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, pen_charge_check, HOOK_PRIO_LAST);
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, pen_charge_check, HOOK_PRIO_LAST);
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
+		if (gpio_get_level(GPIO_USB_C0_PD_RST_L))
+			status |= PD_STATUS_TCPC_ALERT_0;
+
+	return status;
+}
diff --git a/board/quackingstick/board.h b/board/quackingstick/board.h
new file mode 100644
index 0000000000..3cc4ab2b12
--- /dev/null
+++ b/board/quackingstick/board.h
@@ -0,0 +1,118 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Coachz board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "baseboard.h"
+
+#define CONFIG_BUTTON_TRIGGERED_RECOVERY
+
+/* Internal SPI flash on NPCX7 */
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */
+
+/* Save some flash space */
+#define CONFIG_LTO
+#define CONFIG_USB_PD_DEBUG_LEVEL 2
+#undef CONFIG_CMD_FLASHINFO
+#undef CONFIG_CMD_MMAPINFO
+#undef CONFIG_CMD_ACCELSPOOF
+#undef CONFIG_CMD_ACCEL_FIFO
+#undef CONFIG_CMD_ACCEL_INFO
+#undef CONFIG_CMD_TASK_RESET
+
+/* Battery */
+#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
+#undef CONFIG_BATTERY_PRESENT_GPIO
+#define CONFIG_BATTERY_PRESENT_CUSTOM
+#define CONFIG_BATTERY_FUEL_GAUGE
+#define CONFIG_BATTERY_VENDOR_PARAM
+
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 5
+
+/* BC 1.2 Charger */
+#define CONFIG_BC12_DETECT_PI3USB9201
+
+/* USB */
+#define CONFIG_USB_PD_TCPM_PS8805
+#define CONFIG_USB_PD_TCPM_PS8805_FORCE_DID
+#define CONFIG_USBC_PPC_SN5S330
+#define CONFIG_USB_PD_PORT_MAX_COUNT 1
+
+/* Lid accel/gyro */
+#define CONFIG_ACCELGYRO_BMI160
+#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
+#define OPT3001_I2C_ADDR_FLAGS OPT3001_I2C_ADDR1_FLAGS
+#define CONFIG_ACCELGYRO_ICM42607
+#define CONFIG_ACCELGYRO_ICM42607_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
+
+#define CONFIG_TABLET_MODE
+#define CONFIG_TABLET_MODE_SWITCH
+#define CONFIG_FRONT_PROXIMITY_SWITCH
+
+#define CONFIG_MKBP_INPUT_DEVICES
+
+#define CONFIG_DETACHABLE_BASE
+#define CONFIG_BASE_ATTACHED_SWITCH
+
+/* GPIO alias */
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_WP_L GPIO_EC_FLASH_WP_ODL
+#define GPIO_PMIC_RESIN_L GPIO_PM845_RESIN_L
+
+/* temp */
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_THERMISTOR
+#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum adc_channel {
+	ADC_VBUS,
+	ADC_AMON_BMON,
+	ADC_PSYS,
+	ADC_BASE_DET,
+	ADC_SYSTHERM2,
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id { TEMP_SENSOR_SYS2, TEMP_SENSOR_COUNT };
+
+/* Motion sensors */
+enum sensor_id {
+	LID_ACCEL = 0,
+	LID_GYRO,
+	SENSOR_COUNT,
+};
+
+enum pwm_channel { PWM_CH_DISPLIGHT = 0, PWM_CH_COUNT };
+
+/* List of possible batteries */
+enum battery_type {
+	BATTERY_AP21CBI,
+	BATTERY_AP21CBI_VER0,
+	BATTERY_TYPE_COUNT,
+};
+
+/* Reset all TCPCs. */
+void board_reset_pd_mcu(void);
+void board_set_tcpc_power_mode(int port, int mode);
+/* Base detection */
+void base_detect_interrupt(enum gpio_signal signal);
+/* motion sensor interrupt */
+void motion_interrupt(enum gpio_signal signal);
+void pen_input_interrupt(enum gpio_signal signal);
+
+#endif /* !defined(__ASSEMBLER__) */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/quackingstick/build.mk b/board/quackingstick/build.mk
new file mode 100644
index 0000000000..363ef59a16
--- /dev/null
+++ b/board/quackingstick/build.mk
@@ -0,0 +1,14 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx7
+CHIP_VARIANT:=npcx7m6fc
+BASEBOARD:=trogdor
+
+board-y=battery.o board.o led.o base_detect.o usbc_config.o
diff --git a/board/quackingstick/ec.tasklist b/board/quackingstick/ec.tasklist
new file mode 100644
index 0000000000..6cc550374d
--- /dev/null
+++ b/board/quackingstick/ec.tasklist
@@ -0,0 +1,19 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE)
diff --git a/board/quackingstick/gpio.inc b/board/quackingstick/gpio.inc
new file mode 100644
index 0000000000..ee3cedf704
--- /dev/null
+++ b/board/quackingstick/gpio.inc
@@ -0,0 +1,193 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+/* USB-C interrupts */
+GPIO_INT(USB_C0_PD_INT_ODL,    PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-0 TCPC */
+GPIO_INT(USB_C0_SWCTL_INT_ODL, PIN(0, 3), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-0 PPC */
+GPIO_INT(USB_C0_BC12_INT_L,    PIN(6, 1), GPIO_INT_FALLING | GPIO_PULL_UP, usb0_evt)  /* Interrupt from port-0 BC1.2 */
+
+/* System interrupts */
+GPIO_INT(ACOK_OD,           PIN(0, 0), GPIO_INT_BOTH, extpower_interrupt)  /* ACOK */
+GPIO_INT(CCD_MODE_ODL,      PIN(E, 3), GPIO_INT_FALLING, board_connect_c0_sbu)  /* Case Closed Debug Mode */
+GPIO_INT(EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)  /* Power button */
+GPIO_INT(EC_VOLDN_BTN_ODL,  PIN(7, 0), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Up button */
+GPIO_INT(EC_VOLUP_BTN_ODL,  PIN(F, 2), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Down button */
+GPIO_INT(EC_FLASH_WP_ODL,   PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)  /* Write protection */
+GPIO_INT(LID_OPEN_EC,       PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)  /* Lid open */
+GPIO_INT(AP_RST_L,          PIN(C, 1), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_ap_rst_interrupt)  /* PMIC to signal AP reset */
+GPIO_INT(PS_HOLD,           PIN(A, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, power_signal_interrupt)  /* Indicate when AP triggers reset/shutdown */
+GPIO_INT(AP_SUSPEND,        PIN(5, 7), GPIO_INT_BOTH, power_signal_interrupt)  /* Suspend signal from PMIC */
+GPIO_INT(DEPRECATED_AP_RST_REQ, PIN(C, 2), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V, power_signal_interrupt) /* Deprecated AP initiated reset indicator */
+
+/*
+ * When switch-cap is off, the POWER_GOOD signal is floating. Need a pull-down
+ * to make it low. Overload the interrupt function chipset_warm_reset_interrupt
+ * for not only signalling power_signal_interrupt but also handling the logic
+ * of WARM_RESET_L which is pulled-up by the same rail of POWER_GOOD.
+ */
+GPIO_INT(POWER_GOOD,        PIN(5, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, chipset_power_good_interrupt)  /* SRC_PP1800_S10A from PMIC */
+GPIO_INT(WARM_RESET_L,      PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_warm_reset_interrupt)  /* AP warm reset */
+GPIO_INT(AP_EC_SPI_CS_L,    PIN(5, 3), GPIO_INT_FALLING | GPIO_PULL_DOWN, shi_cs_event)  /* EC SPI Chip Select */
+GPIO_INT(BASE_DET_L,        PIN(3, 7), GPIO_INT_BOTH, base_detect_interrupt)  /* Detachable base attached? */
+
+/* Sensor interrupts */
+GPIO_INT(ACCEL_GYRO_INT_L,  PIN(A, 0), GPIO_INT_FALLING, motion_interrupt)  /* Accelerometer/gyro interrupt */
+GPIO_INT(EC_PEN_PDCT_L,     PIN(5, 0), GPIO_INT_BOTH, pen_input_interrupt)  /* Pen input detect */
+
+/*
+ * EC_RST_ODL acts as a wake source from hibernate mode. However, it does not
+ * need to be an interrupt for normal EC operations. Simply set it an INPUT.
+ */
+GPIO(EC_RST_ODL,            PIN(0, 2), GPIO_INPUT)     /* EC reset */
+GPIO(EC_ENTERING_RW,        PIN(E, 1), GPIO_OUT_LOW)   /* Indicate when EC is entering RW code */
+GPIO(EC_BATT_PRES_ODL,      PIN(E, 5), GPIO_INPUT)     /* Battery Present */
+
+/* PMIC/AP 1.8V */
+GPIO(PM845_RESIN_L,         PIN(3, 2), GPIO_ODR_HIGH)  /* PMIC reset trigger */
+GPIO(PMIC_KPD_PWR_ODL,      PIN(D, 6), GPIO_ODR_HIGH)  /* PMIC power button */
+GPIO(EC_INT_L,              PIN(A, 2), GPIO_ODR_HIGH)  /* Interrupt line between AP and EC */
+
+/* Power enables */
+GPIO(HIBERNATE_L,           PIN(5, 2), GPIO_ODR_HIGH)  /* EC hibernate */
+GPIO(SWITCHCAP_ON,          PIN(D, 5), GPIO_OUT_LOW)   /* Enable switch cap; will be configured in the board init */
+GPIO(EN_PP3300_A,           PIN(A, 6), GPIO_OUT_LOW)   /* Enable PP3300 */
+GPIO(EN_PP5000_A,           PIN(6, 7), GPIO_OUT_LOW)   /* Enable PP5000 */
+GPIO(EC_BL_DISABLE_L,       PIN(B, 6), GPIO_OUT_LOW)   /* Backlight disable signal from EC */
+
+/* Base detection */
+GPIO(EN_BASE,               PIN(0, 4), GPIO_OUT_LOW)   /* Enable power to detachable base */
+GPIO(PEN_PWR_EN,            PIN(8, 2), GPIO_OUT_LOW)   /* Pen input charge */
+
+/* USB-C */
+GPIO(USB_C0_PD_RST_L,       PIN(F, 1), GPIO_ODR_HIGH)  /* Port-0 TCPC chip reset, actaully Open-Drain */
+GPIO(DP_MUX_OE_L,           PIN(9, 6), GPIO_ODR_HIGH)  /* DP mux enable, actually Open-Drain */
+GPIO(DP_MUX_SEL,            PIN(4, 5), GPIO_OUT_LOW)   /* DP mux selection: L:C0, H:C1 */
+GPIO(DP_HOT_PLUG_DET,       PIN(9, 5), GPIO_OUT_LOW)   /* DP HPD to AP */
+
+/* LEDs */
+GPIO(LED_ORANGE,       PIN(C, 3), GPIO_OUT_LOW)
+GPIO(LED_BLUE,         PIN(C, 4), GPIO_OUT_LOW)
+
+/*
+ * SPI host interface - enable PDs by default. These will be made functional
+ * by the SHI driver when the AP powers up, and restored back to GPIO when
+ * the AP powers down.
+ */
+GPIO(AP_EC_SPI_MOSI,        PIN(4, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(AP_EC_SPI_MISO,        PIN(4, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(AP_EC_SPI_CLK,         PIN(5, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+
+/* PWM */
+GPIO(EDP_BKLTCTL,           PIN(B, 7), GPIO_INPUT)     /* PWM5 */
+
+/* ADC */
+GPIO(PPVAR_BOOSTIN_SENSE,   PIN(4, 4), GPIO_INPUT)     /* ADC1 */
+GPIO(CHARGER_IADP,          PIN(4, 3), GPIO_INPUT)     /* ADC2 */
+GPIO(CHARGER_PMON,          PIN(4, 2), GPIO_INPUT)     /* ADC3 */
+GPIO(SYSTHERM2_CHARGER,     PIN(3, 4), GPIO_INPUT)     /* ADC6 */
+
+/* I2C */
+GPIO(EC_I2C_POWER_SCL,      PIN(B, 5), GPIO_INPUT)
+GPIO(EC_I2C_POWER_SDA,      PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_PD_SCL,  PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_PD_SDA,  PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SCL,     PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SDA,     PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,     PIN(B, 3), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SENSOR_SDA,     PIN(B, 2), GPIO_INPUT | GPIO_SEL_1P8V)
+
+/* Board/SKU IDs */
+GPIO(BRD_ID0,               PIN(C, 7), GPIO_INPUT)
+GPIO(BRD_ID1,               PIN(9, 3), GPIO_INPUT)
+GPIO(BRD_ID2,               PIN(6, 3), GPIO_INPUT)
+GPIO(SKU_ID0,               PIN(F, 0), GPIO_INPUT)
+GPIO(SKU_ID1,               PIN(4, 1), GPIO_INPUT)
+GPIO(SKU_ID2,               PIN(D, 4), GPIO_INPUT)
+
+/* Switchcap */
+/*
+ * GPIO0 is configured as PVC_PG. When the chip in power down mode, it outputs
+ * high-Z. Set pull-down to avoid floating.
+ */
+GPIO(DA9313_GPIO0,          PIN(E, 2), GPIO_INPUT | GPIO_PULL_DOWN) /* Switchcap GPIO0 */
+
+/* Special straps */
+GPIO(ARM_X86,               PIN(6, 6), GPIO_OUT_LOW)  /* NC, low for power saving */
+
+/* Unused GPIOs, NC. Apply PU for power saving */
+UNUSED(PIN(F, 5))
+UNUSED(PIN(4, 0))
+UNUSED(PIN(7, 4))
+UNUSED(PIN(7, 3))
+UNUSED(PIN(D, 7))
+UNUSED(PIN(6, 0))
+UNUSED(PIN(C, 5))
+UNUSED(PIN(3, 0))
+UNUSED(PIN(E, 4))
+UNUSED(PIN(9, 2))
+UNUSED(PIN(9, 1))
+UNUSED(PIN(D, 1))
+UNUSED(PIN(D, 0))
+UNUSED(PIN(5, 1))
+UNUSED(PIN(F, 3))
+UNUSED(PIN(3, 1))
+UNUSED(PIN(2, 7))
+UNUSED(PIN(2, 6))
+UNUSED(PIN(2, 5))
+UNUSED(PIN(2, 4))
+UNUSED(PIN(2, 3))
+UNUSED(PIN(2, 2))
+UNUSED(PIN(2, 1))
+UNUSED(PIN(2, 0))
+UNUSED(PIN(1, 7))
+UNUSED(PIN(1, 6))
+UNUSED(PIN(1, 5))
+UNUSED(PIN(1, 4))
+UNUSED(PIN(1, 3))
+UNUSED(PIN(1, 2))
+UNUSED(PIN(1, 1))
+UNUSED(PIN(1, 0))
+UNUSED(PIN(0, 7))
+UNUSED(PIN(0, 6))
+UNUSED(PIN(0, 5))
+UNUSED(PIN(9, 4))
+UNUSED(PIN(9, 7))
+UNUSED(PIN(A, 7))
+UNUSED(PIN(B, 0))
+UNUSED(PIN(A, 5))
+UNUSED(PIN(3, 5))
+UNUSED(PIN(7, 2))
+UNUSED(PIN(8, 1))
+UNUSED(PIN(7, 6))
+UNUSED(PIN(C, 6))
+UNUSED(PIN(C, 0))
+UNUSED(PIN(A, 3))
+UNUSED(PIN(6, 2))
+UNUSED(PIN(8, 3))
+UNUSED(PIN(B, 1))
+UNUSED(PIN(5, 6))
+UNUSED(PIN(8, 0))
+UNUSED(PIN(D, 3))
+UNUSED(PIN(7, 5))
+UNUSED(PIN(8, 6))
+
+/* Alternate functions GPIO definitions */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)            /* UART (GPIO64/65) */
+ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0)             /* I2C0 (GPIOB4/B5) */
+ALTERNATE(PIN_MASK(9, 0x07), 1, MODULE_I2C, 0)             /* I2C1 SDA (GPIO90), I2C2 (GPIO91/92) */
+ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, 0)             /* I2C1 SCL (GPIO87) */
+ALTERNATE(PIN_MASK(3, 0x48), 1, MODULE_I2C, 0)             /* I2C5 (GPIO33/36) */
+ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, GPIO_SEL_1P8V) /* I2C7 (GPIOB2/B3) - 1.8V */
+ALTERNATE(PIN_MASK(D, 0x03), 1, MODULE_I2C, 0)             /* I2C3 (GPIOD0/D1) */
+ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0)             /* ADC6 (GPIO34) */
+ALTERNATE(PIN_MASK(4, 0x1C), 0, MODULE_ADC, 0)             /* ADC1 (GPIO44), ADC2 (GPIO43), ADC3 (GPIO42) */
+ALTERNATE(PIN_MASK(4, 0xC0), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SDO (GPIO47), SHI_SDI (GPIO46) */
+ALTERNATE(PIN_MASK(5, 0x28), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SCLK (GPIO55), SHI_CS# (GPIO53) */
+ALTERNATE(PIN_MASK(B, 0x80), 1, MODULE_PWM, 0)             /* PWM5 (GPIOB7) - EDP_BKLTCTL */
diff --git a/board/quackingstick/led.c b/board/quackingstick/led.c
new file mode 100644
index 0000000000..b45ea32ec0
--- /dev/null
+++ b/board/quackingstick/led.c
@@ -0,0 +1,159 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power and battery LED control.
+ */
+
+#include "battery.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "chipset.h"
+#include "ec_commands.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "led_common.h"
+#include "system.h"
+#include "util.h"
+
+#define LED_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS)
+/* Battery LED blinks every per 400ms */
+#define LED_HALF_ONE_SEC (500 / HOOK_TICK_INTERVAL_MS)
+
+#define BAT_LED_ON 1
+#define BAT_LED_OFF 0
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_BATTERY_LED,
+};
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+enum led_color {
+	LED_OFF = 0,
+	LED_AMBER,
+	LED_BLUE,
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
+};
+
+static void led_set_color(enum led_color color)
+{
+	gpio_set_level(GPIO_LED_ORANGE,
+		       (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
+	gpio_set_level(GPIO_LED_BLUE,
+		       (color == LED_BLUE) ? BAT_LED_ON : BAT_LED_OFF);
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	brightness_range[EC_LED_COLOR_AMBER] = 1;
+	brightness_range[EC_LED_COLOR_BLUE] = 1;
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (brightness[EC_LED_COLOR_BLUE] != 0)
+		led_set_color(LED_BLUE);
+	else if (brightness[EC_LED_COLOR_AMBER] != 0)
+		led_set_color(LED_AMBER);
+	else
+		led_set_color(LED_OFF);
+
+	return EC_SUCCESS;
+}
+
+static void board_led_set_battery(void)
+{
+	static int battery_ticks;
+	int color = LED_OFF;
+	int period = 0;
+
+	battery_ticks++;
+
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
+		/* Always indicate amber on when charging. */
+		color = LED_AMBER;
+		break;
+	case LED_PWRS_DISCHARGE:
+		if (chipset_in_or_transitioning_to_state(
+			    CHIPSET_STATE_ANY_SUSPEND)) {
+			/* Discharging in S3: Amber 1 sec, off 3 sec */
+			period = (1 + 3) * LED_ONE_SEC;
+			battery_ticks = battery_ticks % period;
+			if (battery_ticks < 1 * LED_ONE_SEC)
+				color = LED_AMBER;
+			else
+				color = LED_OFF;
+		} else if (chipset_in_or_transitioning_to_state(
+				   CHIPSET_STATE_ANY_OFF)) {
+			/* Discharging in S5: off */
+			color = LED_OFF;
+		} else {
+			/* Discharging in S0: Blue on */
+			color = LED_BLUE;
+		}
+		break;
+	case LED_PWRS_ERROR:
+		/* Battery error: Amber on 1 sec, off 1 sec */
+		period = (1 + 1) * LED_ONE_SEC;
+		battery_ticks = battery_ticks % period;
+		if (battery_ticks < 1 * LED_ONE_SEC)
+			color = LED_AMBER;
+		else
+			color = LED_OFF;
+		break;
+	case LED_PWRS_CHARGE_NEAR_FULL:
+		/* Full Charged: Blue on */
+		color = LED_BLUE;
+		break;
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		color = LED_BLUE;
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		/* Factory mode: Blue 2 sec, Amber 2 sec */
+		period = (2 + 2) * LED_ONE_SEC;
+		battery_ticks = battery_ticks % period;
+		if (battery_ticks < 2 * LED_ONE_SEC)
+			color = LED_BLUE;
+		else
+			color = LED_AMBER;
+		break;
+	default:
+		/* Other states don't alter LED behavior */
+		break;
+	}
+
+	led_set_color(color);
+}
+
+/* Called by hook task every TICK */
+static void led_tick(void)
+{
+	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
+		board_led_set_battery();
+}
+DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
+
+void led_control(enum ec_led_id led_id, enum ec_led_state state)
+{
+	enum led_color color;
+
+	if ((led_id != EC_LED_ID_RECOVERY_HW_REINIT_LED) &&
+	    (led_id != EC_LED_ID_SYSRQ_DEBUG_LED))
+		return;
+
+	if (state == LED_STATE_RESET) {
+		led_auto_control(EC_LED_ID_BATTERY_LED, 1);
+		board_led_set_battery();
+		return;
+	}
+
+	color = state ? LED_BLUE : LED_OFF;
+
+	led_auto_control(EC_LED_ID_BATTERY_LED, 0);
+
+	led_set_color(color);
+}
diff --git a/board/quackingstick/usbc_config.c b/board/quackingstick/usbc_config.c
new file mode 100644
index 0000000000..073c394de2
--- /dev/null
+++ b/board/quackingstick/usbc_config.c
@@ -0,0 +1,100 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Trogdor family-specific USB-C configuration */
+
+#include "charge_state.h"
+#include "charger.h"
+#include "charger/isl923x_public.h"
+#include "console.h"
+#include "temp_sensor.h"
+#include "usb_pd.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+};
+
+struct temp_chg_step {
+	int low; /* temp thershold ('C) to lower level*/
+	int high; /* temp thershold ('C) to higher level */
+	int current; /* charging limitation (mA) */
+};
+
+static const struct temp_chg_step temp_chg_table[] = {
+	{ .low = 0, .high = 50, .current = 3000 }, /* Lv0: normal charge */
+	{ .low = 48, .high = 53, .current = 1500 },
+	{ .low = 51, .high = 56, .current = 1000 },
+	{ .low = 54, .high = 100, .current = 800 },
+};
+#define NUM_TEMP_CHG_LEVELS ARRAY_SIZE(temp_chg_table)
+
+int charger_profile_override(struct charge_state_data *curr)
+{
+	static int current_level;
+	int charger_temp, charger_temp_c;
+	int usb_mv;
+	int port;
+
+	if (curr->state != ST_CHARGE)
+		return 0;
+
+	/* charge current control depends on temp if the system is on */
+	if (chipset_in_state(CHIPSET_STATE_ON)) {
+		temp_sensor_read(TEMP_SENSOR_SYS2, &charger_temp);
+		charger_temp_c = K_TO_C(charger_temp);
+
+		if (charger_temp_c <= temp_chg_table[current_level].low)
+			current_level--;
+		else if (charger_temp_c >= temp_chg_table[current_level].high)
+			current_level++;
+
+		if (current_level < 0)
+			current_level = 0;
+
+		if (current_level >= NUM_TEMP_CHG_LEVELS)
+			current_level = NUM_TEMP_CHG_LEVELS - 1;
+
+		curr->requested_current =
+			MIN(curr->requested_current,
+			    temp_chg_table[current_level].current);
+	}
+
+	/* Lower the max requested voltage to 5V when battery is full. */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
+	    !(curr->batt.flags & BATT_FLAG_BAD_STATUS) &&
+	    !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
+	    (curr->batt.status & STATUS_FULLY_CHARGED))
+		usb_mv = 5000;
+	else
+		usb_mv = PD_MAX_VOLTAGE_MV;
+
+	if (pd_get_max_voltage() != usb_mv) {
+		CPRINTS("VBUS limited to %dmV", usb_mv);
+		for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++)
+			pd_set_external_voltage_limit(port, usb_mv);
+	}
+
+	return 0;
+}
+
+enum ec_status charger_profile_override_get_param(uint32_t param,
+						  uint32_t *value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+enum ec_status charger_profile_override_set_param(uint32_t param,
+						  uint32_t value)
+{
+	return EC_RES_INVALID_PARAM;
+}
diff --git a/board/quackingstick/vif_override.xml b/board/quackingstick/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/quackingstick/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/quiche/board.c b/board/quiche/board.c
index 46a19f4b5e..afe177efe8 100644
--- a/board/quiche/board.c
+++ b/board/quiche/board.c
@@ -1,14 +1,103 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Quiche board-specific configuration */
 
+#include "common.h"
+#include "cros_board_info.h"
+#include "driver/ppc/sn5s330.h"
+#include "driver/tcpm/ps8xxx.h"
+#include "driver/tcpm/stm32gx.h"
+#include "driver/tcpm/tcpci.h"
+#include "driver/usb_mux/ps8822.h"
+#include "ec_version.h"
+#include "gpio.h"
 #include "hooks.h"
 #include "switch.h"
+#include "system.h"
+#include "task.h"
+#include "uart.h"
+#include "usb_descriptor.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_dp_ufp.h"
+#include "usb_pe_sm.h"
+#include "usb_prl_sm.h"
+#include "usb_tc_sm.h"
+#include "usbc_ppc.h"
+#include "util.h"
 
-#include "gpio_list.h" /* Must come after other header files. */
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+
+#define QUICHE_PD_DEBUG_LVL 1
+
+#ifdef SECTION_IS_RW
+#define CROS_EC_SECTION "RW"
+#else
+#define CROS_EC_SECTION "RO"
+#endif
+
+#ifdef SECTION_IS_RW
+static int pd_dual_role_init[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	PD_DRP_TOGGLE_ON,
+	PD_DRP_FORCE_SOURCE,
+};
+
+static void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_HOST_USBC_PPC_INT_ODL:
+		sn5s330_interrupt(USB_PD_PORT_HOST);
+		break;
+	case GPIO_USBC_DP_PPC_INT_ODL:
+		sn5s330_interrupt(USB_PD_PORT_DP);
+		break;
+
+	default:
+		break;
+	}
+}
+
+static void tcpc_alert_event(enum gpio_signal s)
+{
+	int port = -1;
+
+	switch (s) {
+	case GPIO_USBC_DP_MUX_ALERT_ODL:
+		port = USB_PD_PORT_DP;
+		break;
+	default:
+		return;
+	}
+	schedule_deferred_pd_interrupt(port);
+}
+
+void hpd_interrupt(enum gpio_signal signal)
+{
+	usb_pd_hpd_edge_event(signal);
+}
+
+static void board_uf_manage_vbus_interrupt(enum gpio_signal signal)
+{
+	baseboard_usb3_check_state();
+}
+
+static void board_pwr_btn_interrupt(enum gpio_signal signal)
+{
+	baseboard_power_button_evt(gpio_get_level(signal));
+}
+
+static void board_usbc_usb3_interrupt(enum gpio_signal signal)
+{
+	baseboard_usbc_usb3_irq();
+}
+#endif /* SECTION_IS_RW */
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
 
 /*
  * Table GPIO signals control both power rails and reset lines to various chips
@@ -16,34 +105,334 @@
  * signals is driven by USB/MST hub power sequencing requirements.
  */
 const struct power_seq board_power_seq[] = {
-	{GPIO_EN_AC_JACK,               1, 20},
-	{GPIO_EN_PP5000_A,              1, 31},
-	{GPIO_EN_PP3300_B,              1, 100},
-	{GPIO_EN_BB,                    1, 30},
-	{GPIO_EN_PP1100_A,              1, 30},
-	{GPIO_EN_PP1050_A,              1, 30},
-	{GPIO_EN_PP1200_A,              1, 20},
-	{GPIO_EN_PP5000_C,              1, 20},
-	{GPIO_EN_PP5000_HSPORT,         1, 31},
-	{GPIO_EN_DP_SINK,               1, 80},
-	{GPIO_MST_RST_L,                1, 20},
-	{GPIO_MST_LP_CTL_L,             1, 41},
-	{GPIO_EC_HUB2_RESET_L,          1, 41},
-	{GPIO_EC_HUB3_RESET_L,          1, 33},
-	{GPIO_DP_SINK_RESET,            1, 100},
-	{GPIO_USBC_DP_PD_RST_L,         1, 100},
-	{GPIO_USBC_UF_RESET_L,          1, 33},
-	{GPIO_DEMUX_DUAL_DP_PD_N,       1, 100},
-	{GPIO_DEMUX_DUAL_DP_RESET_N,    1, 100},
-	{GPIO_DEMUX_DP_HDMI_PD_N,       1, 10},
-	{GPIO_DEMUX_DUAL_DP_MODE,       1, 10},
-	{GPIO_DEMUX_DP_HDMI_MODE,       1, 1},
+	{ GPIO_EN_AC_JACK, 1, 20 },
+	{ GPIO_EC_DFU_MUX_CTRL, 0, 0 },
+	{ GPIO_EN_PP5000_A, 1, 31 },
+	{ GPIO_MST_LP_CTL_L, 1, 0 },
+	{ GPIO_EN_PP3300_B, 1, 1 },
+	{ GPIO_EN_PP1100_A, 1, 100 + 30 },
+	{ GPIO_EN_BB, 1, 30 },
+	{ GPIO_EN_PP1050_A, 1, 30 },
+	{ GPIO_EN_PP1200_A, 1, 20 },
+	{ GPIO_EN_PP5000_C, 1, 20 },
+	{ GPIO_EN_PP5000_HSPORT, 1, 31 },
+	{ GPIO_EN_DP_SINK, 1, 80 },
+	{ GPIO_MST_RST_L, 1, 61 },
+	{ GPIO_EC_HUB2_RESET_L, 1, 41 },
+	{ GPIO_EC_HUB3_RESET_L, 1, 33 },
+	{ GPIO_DP_SINK_RESET, 1, 100 },
+	{ GPIO_USBC_DP_PD_RST_L, 1, 100 },
+	{ GPIO_USBC_UF_RESET_L, 1, 33 },
+	{ GPIO_DEMUX_DUAL_DP_PD_N, 1, 100 },
+	{ GPIO_DEMUX_DUAL_DP_RESET_N, 1, 100 },
+	{ GPIO_DEMUX_DP_HDMI_PD_N, 1, 10 },
+	{ GPIO_DEMUX_DUAL_DP_MODE, 1, 10 },
+	{ GPIO_DEMUX_DP_HDMI_MODE, 1, 5 },
 };
-
 const size_t board_power_seq_count = ARRAY_SIZE(board_power_seq);
 
+/*
+ * Define the strings used in our USB descriptors.
+ */
+const void *const usb_strings[] = {
+	[USB_STR_DESC] = usb_string_desc,
+	[USB_STR_VENDOR] = USB_STRING_DESC("Google LLC"),
+	[USB_STR_PRODUCT] = USB_STRING_DESC("Quiche"),
+	[USB_STR_SERIALNO] = 0,
+	[USB_STR_VERSION] =
+		USB_STRING_DESC(CROS_EC_SECTION ":" CROS_EC_VERSION32),
+	[USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"),
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
+
+#ifndef SECTION_IS_RW
+/* USB-C PPC Configuration */
+struct ppc_config_t ppc_chips[] = {
+	[USB_PD_PORT_HOST] = {
+		.i2c_port = I2C_PORT_I2C1,
+		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	},
+};
+#endif
+
+#ifdef SECTION_IS_RW
+/*
+ * PS8802 set mux board tuning.
+ * Adds in board specific gain and DP lane count configuration
+ */
+static int board_ps8822_mux_set(const struct usb_mux *me, mux_state_t mux_state)
+{
+	int rv = EC_SUCCESS;
+
+	/* DP specific config */
+	if (mux_state & USB_PD_MUX_DP_ENABLED)
+		rv = ps8822_set_dp_rx_eq(me, PS8822_DPEQ_LEVEL_UP_20DB);
+
+	return rv;
+}
+
+/* TCPCs */
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	[USB_PD_PORT_HOST] = {
+		.bus_type = EC_BUS_TYPE_EMBEDDED,
+		.drv = &stm32gx_tcpm_drv,
+	},
+	[USB_PD_PORT_DP] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_I2C1,
+			.addr_flags = PS8XXX_I2C_ADDR2_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+	},
+};
+
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	[USB_PD_PORT_HOST] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_HOST,
+			.i2c_port = I2C_PORT_I2C1,
+			.i2c_addr_flags = PS8822_I2C_ADDR3_FLAG,
+			.driver = &ps8822_usb_mux_driver,
+			.board_set = &board_ps8822_mux_set,
+		},
+	},
+	[USB_PD_PORT_DP] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_DP,
+			.i2c_port = I2C_PORT_I2C1,
+			.i2c_addr_flags = PS8XXX_I2C_ADDR2_FLAGS,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
+	},
+};
+
+/* USB-C PPC Configuration */
+struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	[USB_PD_PORT_HOST] = { .i2c_port = I2C_PORT_I2C1,
+			       .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+			       .drv = &sn5s330_drv },
+	[USB_PD_PORT_DP] = { .i2c_port = I2C_PORT_I2C1,
+			     .i2c_addr_flags = SN5S330_ADDR2_FLAGS,
+			     .drv = &sn5s330_drv },
+	[USB_PD_PORT_USB3] = { .i2c_port = I2C_PORT_I2C3,
+			       .i2c_addr_flags = SN5S330_ADDR1_FLAGS,
+			       .drv = &sn5s330_drv },
+};
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+const struct hpd_to_pd_config_t hpd_config = {
+	.port = USB_PD_PORT_HOST,
+	.signal = GPIO_DDI_MST_IN_HPD,
+};
+
+void board_reset_pd_mcu(void)
+{
+	cprints(CC_SYSTEM, "Resetting TCPCs...");
+	cflush();
+	gpio_set_level(GPIO_USBC_DP_PD_RST_L, 0);
+	gpio_set_level(GPIO_USBC_UF_RESET_L, 0);
+	msleep(PS8805_FW_INIT_DELAY_MS);
+	gpio_set_level(GPIO_USBC_DP_PD_RST_L, 1);
+	gpio_set_level(GPIO_USBC_UF_RESET_L, 1);
+	msleep(PS8805_FW_INIT_DELAY_MS);
+}
+
+void board_enable_usbc_interrupts(void)
+{
+	/* Enable C0 PPC interrupt */
+	gpio_enable_interrupt(GPIO_HOST_USBC_PPC_INT_ODL);
+	/* Enable C1 PPC interrupt */
+	gpio_enable_interrupt(GPIO_USBC_DP_PPC_INT_ODL);
+	/* Enable C0 HPD interrupt */
+	gpio_enable_interrupt(GPIO_DDI_MST_IN_HPD);
+	/* Enable C1 TCPC interrupt */
+	gpio_enable_interrupt(GPIO_USBC_DP_MUX_ALERT_ODL);
+}
+
+void board_disable_usbc_interrupts(void)
+{
+	/* Disable C0 PPC interrupt */
+	gpio_disable_interrupt(GPIO_HOST_USBC_PPC_INT_ODL);
+	/* Disable C1 PPC interrupt */
+	gpio_disable_interrupt(GPIO_USBC_DP_PPC_INT_ODL);
+	/* Disable C0 HPD interrupt */
+	gpio_disable_interrupt(GPIO_DDI_MST_IN_HPD);
+	/* Disable C1 TCPC interrupt */
+	gpio_disable_interrupt(GPIO_USBC_DP_MUX_ALERT_ODL);
+	/* Disable VBUS control interrupt for C2 */
+	gpio_disable_interrupt(GPIO_USBC_UF_MUX_VBUS_EN);
+}
+
+void board_tcpc_init(void)
+{
+	board_reset_pd_mcu();
+
+	/* Enable board usbc interrupts */
+	board_enable_usbc_interrupts();
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 2);
+
+enum pd_dual_role_states board_tc_get_initial_drp_mode(int port)
+{
+	return pd_dual_role_init[port];
+}
+
+__override uint8_t board_get_usb_pd_port_count(void)
+{
+	/*
+	 * CONFIG_USB_PD_PORT_MAX_COUNT must be defined to account for C0, C1,
+	 * and C2, but TCPMv2 only knows about C0 and C1, as C2 is a type-c only
+	 * port that is managed directly by the PS8803 TCPC.
+	 */
+	return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
+}
+
+int ppc_get_alert_status(int port)
+{
+	if (port == USB_PD_PORT_HOST)
+		return gpio_get_level(GPIO_HOST_USBC_PPC_INT_ODL) == 0;
+	else if (port == USB_PD_PORT_DP)
+		return gpio_get_level(GPIO_USBC_DP_PPC_INT_ODL) == 0;
+
+	return 0;
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (!gpio_get_level(GPIO_USBC_DP_MUX_ALERT_ODL) &&
+	    gpio_get_level(GPIO_USBC_DP_PD_RST_L))
+		status |= PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
+
+static void board_usb_pd_dp_ocp_reset(void)
+{
+	gpio_set_level(GPIO_USBC_ALTMODE_OCP_NOTIFY, 1);
+}
+DECLARE_DEFERRED(board_usb_pd_dp_ocp_reset);
+
+void board_overcurrent_event(int port, int is_overcurrented)
+{
+	if (port == USB_PD_PORT_DP) {
+		gpio_set_level(GPIO_USBC_ALTMODE_OCP_NOTIFY, !is_overcurrented);
+		hook_call_deferred(&board_usb_pd_dp_ocp_reset_data,
+				   USB_HUB_OCP_RESET_MSEC);
+	}
+}
+
+int dock_get_mf_preference(void)
+{
+	int rv;
+	uint32_t fw_config;
+	int mf = MF_OFF;
+
+	/*
+	 * MF (multi function) preferece is indicated by bit 0 of the fw_config
+	 * data field. If this data field does not exist, then default to 4 lane
+	 * mode.
+	 */
+	rv = cbi_get_fw_config(&fw_config);
+	if (!rv)
+		mf = CBI_FW_MF_PREFERENCE(fw_config);
+
+	return mf;
+}
+
+static void board_usb_tc_connect(void)
+{
+	int port = TASK_ID_TO_PD_PORT(task_get_current());
+
+	/*
+	 * The EC needs to indicate to the MST hub when the host port is
+	 * attached. GPIO_UFP_PLUG_DET is used for this purpose.
+	 */
+	if (port == USB_PD_PORT_HOST)
+		gpio_set_level(GPIO_UFP_PLUG_DET, 0);
+}
+DECLARE_HOOK(HOOK_USB_PD_CONNECT, board_usb_tc_connect, HOOK_PRIO_DEFAULT);
+
+static void board_usb_tc_disconnect(void)
+{
+	int port = TASK_ID_TO_PD_PORT(task_get_current());
+
+	/* Only the host port disconnect is relevant */
+	if (port == USB_PD_PORT_HOST)
+		gpio_set_level(GPIO_UFP_PLUG_DET, 1);
+}
+DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, board_usb_tc_disconnect,
+	     HOOK_PRIO_DEFAULT);
+
+#endif /* SECTION_IS_RW */
+
 static void board_init(void)
 {
-	/* TODO */
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+static void board_debug_gpio_1_pulse(void)
+{
+	gpio_set_level(GPIO_TRIGGER_1, 0);
+}
+DECLARE_DEFERRED(board_debug_gpio_1_pulse);
+
+static void board_debug_gpio_2_pulse(void)
+{
+	gpio_set_level(GPIO_TRIGGER_2, 0);
+}
+DECLARE_DEFERRED(board_debug_gpio_2_pulse);
+
+void board_debug_gpio(enum debug_gpio trigger, int level, int pulse_usec)
+{
+	switch (trigger) {
+	case TRIGGER_1:
+		gpio_set_level(GPIO_TRIGGER_1, level);
+		if (pulse_usec)
+			hook_call_deferred(&board_debug_gpio_1_pulse_data,
+					   pulse_usec);
+		break;
+	case TRIGGER_2:
+		gpio_set_level(GPIO_TRIGGER_2, level);
+		if (pulse_usec)
+			hook_call_deferred(&board_debug_gpio_2_pulse_data,
+					   pulse_usec);
+		break;
+	default:
+		CPRINTS("bad debug gpio selection");
+		break;
+	}
+}
+
+static int command_dplane(int argc, const char **argv)
+{
+	char *e;
+	int lane;
+
+	if (argc < 2)
+		return EC_ERROR_PARAM_COUNT;
+
+	lane = strtoi(argv[1], &e, 10);
+
+	if ((lane != 2) && (lane != 4))
+		return EC_ERROR_PARAM1;
+
+	/* put MST into reset */
+	gpio_set_level(GPIO_MST_RST_L, 0);
+	msleep(1);
+	/* Set lane control to requested level */
+	gpio_set_level(GPIO_MST_HUB_LANE_SWITCH, lane == 2 ? 1 : 0);
+	msleep(1);
+	/* Take MST out of reset */
+	gpio_set_level(GPIO_MST_RST_L, 1);
+
+	ccprintf("MST lane set:  %s, lane_ctrl = %d\n",
+		 lane == 2 ? "2 lane" : "4 lane",
+		 gpio_get_level(GPIO_MST_HUB_LANE_SWITCH));
+
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(dplane, command_dplane, "<2 | 4>", "MST lane control.");
diff --git a/board/quiche/board.h b/board/quiche/board.h
index 48422e7a50..b1ba0c5eba 100644
--- a/board/quiche/board.h
+++ b/board/quiche/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,19 +12,89 @@
 #include "baseboard.h"
 
 /* Optional features */
+/*
+ * For MP release, CONFIG_SYSTEM_UNLOCKED must be undefined, and
+ * CONFIG_FLASH_PSTATE_LOCKED must be defined in order to enable write protect
+ * using option bytes WRP registers.
+ */
 #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
+#undef CONFIG_FLASH_PSTATE_LOCKED
 
 /* USB Type C and USB PD defines */
+#define USB_PD_PORT_HOST 0
+#define USB_PD_PORT_DP 1
+#define USB_PD_PORT_USB3 2
+
+/*
+ * The host (C0) and display (C1) usbc ports are usb-pd capable. There is
+ * also a type-c only port (C2). C2 must be accounted for in PORT_MAX_COUNT so
+ * the PPC config table is correctly sized and the PPC driver can be used to
+ * control VBUS on/off.
+ */
+#define CONFIG_USB_PD_PORT_MAX_COUNT 3
+#define CONFIG_USB_MUX_PS8822
+
+#define CONFIG_USB_PID 0x5048
+#define CONFIG_USB_BCD_DEV 0x0001 /* v 0.01 */
+#define CONFIG_USB_PD_IDENTITY_HW_VERS 1
+#define CONFIG_USB_PD_IDENTITY_SW_VERS 1
 
-/* USB Type A Features */
+/* I2C port names */
+#define I2C_PORT_I2C1 0
+#define I2C_PORT_I2C2 1
+#define I2C_PORT_I2C3 2
 
-/* BC 1.2 */
+/* Required symbolic I2C port names */
+#define I2C_PORT_MP4245 I2C_PORT_I2C3
+#define I2C_PORT_EEPROM I2C_PORT_I2C3
+#define MP4245_I2C_ADDR_FLAGS MP4245_I2C_ADDR_0_FLAGS
 
+/* Include math_util for bitmask_uint64 used in pd_timers */
+#define CONFIG_MATH_UTIL
 
 #ifndef __ASSEMBLER__
 
 #include "registers.h"
 
+#define GPIO_DP_HPD GPIO_DDI_MST_IN_HPD
+#define GPIO_USBC_UF_ATTACHED_SRC GPIO_USBC_UF_MUX_VBUS_EN
+#define GPIO_BPWR_DET GPIO_TP73
+#define GPIO_USB_HUB_OCP_NOTIFY GPIO_USBC_DATA_OCP_NOTIFY
+#define GPIO_UFP_PLUG_DET GPIO_MST_UFP_PLUG_DET
+#define GPIO_PWR_BUTTON_RED GPIO_EC_STATUS_LED1
+#define GPIO_PWR_BUTTON_GREEN GPIO_EC_STATUS_LED2
+
+#define BUTTON_PRESSED_LEVEL 1
+#define BUTTON_RELEASED_LEVEL 0
+
+#define GPIO_TRIGGER_1 GPIO_EC_STATUS_LED1
+#define GPIO_TRIGGER_2 GPIO_EC_STATUS_LED2
+
+enum debug_gpio {
+	TRIGGER_1 = 0,
+	TRIGGER_2,
+};
+
+/*
+ * Function used to control GPIO signals as a timing marker. This is intended to
+ * be used for development/debugging purposes.
+ *
+ * @param trigger GPIO debug signal selection
+ * @param level desired level of the debug gpio signal
+ * @param pulse_usec pulse width if non-zero
+ */
+void board_debug_gpio(enum debug_gpio trigger, int level, int pulse_usec);
+
+/*
+ * Function called in power on case to enable usbc related interrupts
+ */
+void board_enable_usbc_interrupts(void);
+
+/*
+ * Function called in power off case to disable usbc related interrupts
+ */
+void board_disable_usbc_interrupts(void);
+
 #endif /* !__ASSEMBLER__ */
 
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/quiche/build.mk b/board/quiche/build.mk
index 3c17e2e83b..76a59e502a 100644
--- a/board/quiche/build.mk
+++ b/board/quiche/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -8,7 +8,7 @@
 
 CHIP:=stm32
 CHIP_FAMILY:=stm32g4
-CHIP_VARIANT:=stm32g431xb
+CHIP_VARIANT:=stm32g473xc
 BASEBOARD:=honeybuns
 
 board-y=board.o
diff --git a/board/quiche/dev_key.pem b/board/quiche/dev_key.pem
new file mode 100644
index 0000000000..4897ceb44e
--- /dev/null
+++ b/board/quiche/dev_key.pem
@@ -0,0 +1,39 @@
+-----BEGIN RSA PRIVATE KEY-----
+MIIG4wIBAAKCAYEAyiT9PsD2wW3mhfuxMtihnLDKC+PY9l6j+j405G5Wd3BBtLLl
+2uEoSD8cFQfnVTeFH7wggVf+SMAP3Y2aTnXIfdTX3N0skAdq/kYNUlQAK0xsa3Z7
+bRZ8puvzu+XNqsSS/tvsdYbNE5WC5sXtt7Wkm3mKn7PAti7oQrKbW1beFD0FgdAq
+JoweIdpkuOwDYtFBcF92LWWGziDcEXlc2v5Xj3qvixMLnhy+Ny1Byr2ApVaYZ56H
+JfjHKxbirNj4IrgmhdzfBIKxDf4mGibG0K1aC1io+SixtRV1cS6JRB0D+GS4QIcq
+y9bCMkBeVQLHhSo1UYZqbB7Qef0blQ2sxsXklo8Q5EIQOd6yiXiTelApOWDn3zTi
+uTkUo+99SPDLw/S3sR3uESxt+OYO2Yt6BWe2JSYBhHWB0Xc0PGItq7DUpm2cEWke
+vS91I/lBfqhOxQOvnEx5NM97/RBQMa3jJ5Jv/72X5oU6OcGmaliBJy3Tv0CSiI06
+qgRgWxMym/XA0ui/AgEDAoIBgQCGw1N/K08rnpmup8t3OxZoddwH7TtO6cKm1CNC
+9Dmk9YEjIe6R63AwKhK4r++OJQNqfWsA5VQwgAqTs7w0ToWpOI/ok3MKr5yphAjh
+jVVyMvLyTvzzZFMZ8qJ9Q95x2GH/PUhOWd4NDldEg/PPzm28+7G/zSskH0WBzGeS
+Oeli01kBNXFvCBQWkZh7SAJB4NZK6k7I7lnewJK2UOiR/uUKUcpct10UEyl6Hivc
+flXDjxBFFFoZUITHZJcd5frB0Bh+EiqJ3CnkSIjD4sTnZs/TP8CKhmYriabfBHdH
+j6ffcr5y8VhqDJK/ISSmWQO1c/rSziJLhx/ZrWvWp1FAbRg+kdh+RmV8hYIdEOq8
+PYOiERihd+eHVhtzsc74+cRGxPbaFJ2rpuJt+xk1Zp7IfGyyPWDmvXFKZgX+vo2s
+vJL6q9pPR57uUHL0xsxDrMH3HFxkl1ta5PsiBGXs+zG0EUzNKGtoRTCi176xUWyo
+NG+eWiL9ddeZVBzWeKfJGfwQ53sCgcEA+JE2E5kjvVCasSqERfDfIkSeOKoqWdZ2
+sAvTHibq6+vMBkRubNA0glHcUrMEBblDg3ds2z1A9YvwjwEUq9UFpVH3qfX9vaTX
+lLYFRZjcA3PkCJvFAt5eIlVXp+vgaEo6OcodLjDiqkYKzbMC13k5uM1wsEEwo2vI
+38vhHQlH1PHVTd8pt2Y7mOpDgxOOJLrvwuew7Lj9QSBRZ0EJxqv+1QA4EQ1cPr1H
+hGqggtL0ChLRV7KBHiLz9ggS5vHTEkFNAoHBANAwaSIfTnpAvkMoGy+iQyw0afC0
+7hnwhHKcAzqenT1Mzo3Yt7/zsZE8ywjKPe9C+ZHZyh+W373tCUQRnjpNOpNiVHzi
+ekFxl8kpLhpbB8LTXuRlQmtZjVQPbyuORPGDCzA05GGBN6mnXju+iQEz2WD8f3oY
+Jz5yYl54eAuMsFl5/0yehqBQjRvky5YRna2eNUKBvz+/BgjpZeb0DtLMffcAvrkQ
+FQbAwNvzvagMOEemjLSp9iXjQSNWJAdc86dMOwKBwQCltiQNEMJ+Nbx2HFguoJTB
+gxQlxsbmjvnKsoy+xJydR91ZgvRIis2sNpLhzK1ZJi0CT53nfitOXUsKALhyjgPD
+i/pxTqkpGI+4eVjZEJKs9+1bEoNXPulsOOUanUBFhtF73BN0IJccLrHed1c6UNEl
+3ksgK3XCR9s/3UC+Bi/jS+OJP3Ek7tJl8YJXYl7DJ0qB78tIe1OAwDZE1gaEcqnj
+VXq2COgp04UC8cBXN01cDIuPzFYUF01OsAyZ9oy21jMCgcEAisrwwWo0UYB+13AS
+H8GCHXhGoHieu/Wtob1XfGm+KN3fCTslKqJ2YNMyBdwpSiymYTvcFQ8/0/NbgrZp
+fDN8YkGNqJb8K6EP23DJZudageI/Qu4sR5EI4rT0x7Qt9ldcys3tllYlG8TpfSmw
+q3fmQKhU/BAaKaGW6aWlXQh1kPv/iGmvFYsIvUMyZAu+c77OLFZ/f9SusJuZRKK0
+jIhT+gB/Jgq4rysrPU0pGrLQL8RdzcakGUIrbOQYBOiib4gnAoHAVrvbmZGxyeeA
+oDE2QlXXmd1higPaQe3u+7vmh6itVpJ71n9wmu9xei7IiTOtGDYjHLXa8Qg0y37/
+FVCUiFxhOz05hpnB1ts70tuIWUJbWttMnhZPTpKa1dzZFB6qrlk2o/ONaSfNzpOZ
+FgKxBURFVzNMTlIh7QOZGoOeRg5BkFG5z21g8egYQ/1cY61BhaxJTz93HGKb0jYn
+QnC0WfVF9amWNGwocKATkwjoSVC7rQRsB2FMbY/WCqgE92lXsU9W
+-----END RSA PRIVATE KEY-----
diff --git a/board/quiche/ec.tasklist b/board/quiche/ec.tasklist
index c272906fc7..ffd4a604c9 100644
--- a/board/quiche/ec.tasklist
+++ b/board/quiche/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,5 +8,11 @@
  */
 
 #define CONFIG_TASK_LIST \
+	TASK_ALWAYS_RO(RWSIG,    rwsig_task,   NULL, 1280) \
 	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE)
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS_RW(POWER_BUTTON, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS_RW(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS_RW(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS_RW(PD_INT_C1, pd_interrupt_handler_task, 1, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS_RW(UCPD, ucpd_task, 0, LARGER_TASK_STACK_SIZE)
diff --git a/board/quiche/gpio.inc b/board/quiche/gpio.inc
index e6264c741e..afd18e5bb6 100644
--- a/board/quiche/gpio.inc
+++ b/board/quiche/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,10 +8,19 @@
 /* Declare symbolic names for all the GPIOs that we care about.
  * Note: Those with interrupt handlers must be declared first. */
 
+#ifdef SECTION_IS_RW
+GPIO_INT(HOST_USBC_PPC_INT_ODL,  PIN(D,  9),      GPIO_INT_FALLING | GPIO_PULL_UP, ppc_interrupt)
+GPIO_INT(USBC_DP_MUX_ALERT_ODL,  PIN(B,  1),      GPIO_INT_FALLING | GPIO_PULL_UP, tcpc_alert_event)
+GPIO_INT(USBC_DP_PPC_INT_ODL,    PIN(E,  7),      GPIO_INT_FALLING | GPIO_PULL_UP, ppc_interrupt)
+GPIO_INT(DDI_MST_IN_HPD,         PIN(C,  14),     GPIO_INT_BOTH, hpd_interrupt)
+GPIO_INT(USBC_UF_MUX_VBUS_EN,    PIN(C,  12),     GPIO_INT_BOTH, board_uf_manage_vbus_interrupt)
+GPIO_INT(PWR_BTN,                PIN(A,  0),      GPIO_INT_BOTH, board_pwr_btn_interrupt)
+GPIO_INT(USBC_UF_PPC_INT_ODL,    PIN(B,  5),      GPIO_INT_FALLING | GPIO_PULL_UP, board_usbc_usb3_interrupt)
+#endif
+
 /* Power sequencing signals */
-GPIO(PWR_BTN,                       PIN(A,  0), GPIO_INPUT)
 GPIO(EN_AC_JACK,                    PIN(A,  1), GPIO_OUT_LOW)
-GPIO(EN_BB,                         PIN(A, 10), GPIO_OUT_LOW)
+GPIO(EN_BB,                         PIN(A,  8), GPIO_OUT_LOW)
 GPIO(EN_PP3300_B,                   PIN(B,  2), GPIO_OUT_LOW)
 GPIO(EN_PP5000_A,                   PIN(C,  6), GPIO_OUT_LOW)
 GPIO(EN_PP1200_A,                   PIN(E,  8), GPIO_OUT_LOW)
@@ -23,6 +32,8 @@ GPIO(EN_PP5000_HSPORT,              PIN(D,  0), GPIO_OUT_LOW)
 /* MST Hub signals */
 GPIO(MST_LP_CTL_L,                  PIN(D, 10), GPIO_ODR_LOW)
 GPIO(MST_RST_L,                     PIN(E, 14), GPIO_ODR_LOW)
+GPIO(MST_HUB_LANE_SWITCH,           PIN(C, 15), GPIO_OUT_HIGH)
+GPIO(MST_UFP_PLUG_DET,              PIN(B, 12), GPIO_OUT_HIGH)
 
 /* Display Demux signals */
 GPIO(DEMUX_DUAL_DP_MODE,            PIN(B,  0), GPIO_OUT_LOW)
@@ -39,12 +50,26 @@ GPIO(USBC_UF_RESET_L,               PIN(D,  2), GPIO_ODR_LOW)
 
 /* USB Hubs signals */
 GPIO(EC_HUB2_RESET_L,               PIN(C,  5), GPIO_ODR_LOW)
-GPIO(EC_HUB3_RESET_L,               PIN(C, 10), GPIO_ODR_LOW)
+GPIO(EC_HUB3_RESET_L,               PIN(B, 10), GPIO_ODR_LOW)
+GPIO(USBC_ALTMODE_OCP_NOTIFY,       PIN(F,  0), GPIO_OUT_HIGH)
+GPIO(USBC_DATA_OCP_NOTIFY,          PIN(F,  1), GPIO_OUT_HIGH)
+
+/* USB-A Current limit switches, set default to 1.5A */
+GPIO(TP73,                          PIN(C,  0), GPIO_OUT_LOW)
+GPIO(EC_DFU_MUX_CTRL,               PIN(C,  3), GPIO_OUT_HIGH)
+GPIO(EC_STATUS_LED1,                PIN(C,  1), GPIO_OUT_HIGH)
+GPIO(EC_STATUS_LED2,                PIN(C,  2), GPIO_OUT_HIGH)
+GPIO(USB3_A5_CDP_EN,                PIN(B,  9), GPIO_OUT_LOW)
+GPIO(USB3_A6_CDP_EN,                PIN(C, 13), GPIO_OUT_LOW)
 
 /* Write protect */
 GPIO(EC_FLASH_WP_ODL,               PIN(A,  3), GPIO_ODR_HIGH)
 GPIO(EC_WP_L,                       PIN(E, 11), GPIO_INT_BOTH)
 
+/* UART Bus */
+GPIO(EC_UART_TX,                    PIN(C, 10), GPIO_INT_BOTH)
+GPIO(EC_UART_RX,                    PIN(C, 11), GPIO_INT_BOTH)
+
 /*
  * I2C SCL/SDA pins. These will normally be under control of the peripheral from
  * alt fucntion setting below. But if a port gets wedged, the unwedge code uses
@@ -52,11 +77,12 @@ GPIO(EC_WP_L,                       PIN(E, 11), GPIO_INT_BOTH)
  */
 GPIO(EC_I2C1_SCL,                   PIN(A, 15),  GPIO_ODR_HIGH)
 GPIO(EC_I2C1_SDA,                   PIN(B,  7),  GPIO_ODR_HIGH)
-GPIO(EC_I2C2_SDA,                   PIN(A,  8),  GPIO_ODR_HIGH)
-GPIO(EC_I2C2_SCL,                   PIN(A,  9),  GPIO_ODR_HIGH)
 GPIO(EC_I2C3_SCL,                   PIN(C,  8),  GPIO_ODR_HIGH)
 GPIO(EC_I2C3_SDA,                   PIN(C,  9),  GPIO_ODR_HIGH)
 
+/* misc signals */
+GPIO(BOOT0,                         PIN(B,  8),  GPIO_INPUT)
+
 /* Unimplemented signals since we are not an EC */
 UNIMPLEMENTED(ENTERING_RW)
 
@@ -69,7 +95,6 @@ ALTERNATE(PIN_MASK(C, 0x0C00),  7, MODULE_UART,  GPIO_PULL_UP)
  */
 ALTERNATE(PIN_MASK(B, 0x0080),  4, MODULE_I2C,   GPIO_OPEN_DRAIN)
 ALTERNATE(PIN_MASK(A, 0X8000),  4, MODULE_I2C,   GPIO_OPEN_DRAIN)
-ALTERNATE(PIN_MASK(A, 0x0300),  4, MODULE_I2C,   GPIO_OPEN_DRAIN)
 ALTERNATE(PIN_MASK(C, 0x0300),  8, MODULE_I2C,   GPIO_OPEN_DRAIN)
 /* GPIOA4-7: SPI Signals */
 ALTERNATE(PIN_MASK(A, 0x00F0),  5, MODULE_SPI,   0)
diff --git a/board/rainier/board.c b/board/rainier/board.c
index fa852a5a90..1844688947 100644
--- a/board/rainier/board.c
+++ b/board/rainier/board.c
@@ -1,22 +1,21 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "backlight.h"
 #include "button.h"
-#include "chipset.h"
 #include "charge_manager.h"
 #include "charge_state.h"
+#include "chipset.h"
 #include "common.h"
 #include "console.h"
-#include "ec_commands.h"
 #include "driver/accelgyro_bmi_common.h"
 #include "driver/baro_bmp280.h"
 #include "driver/tcpm/fusb302.h"
 #include "driver/temp_sensor/tmp432.h"
+#include "ec_commands.h"
 #include "extpower.h"
 #include "gpio.h"
 #include "hooks.h"
@@ -31,18 +30,18 @@
 #include "switch.h"
 #include "system.h"
 #include "task.h"
-#include "tcpm.h"
+#include "tcpm/tcpm.h"
 #include "temp_sensor.h"
 #include "temp_sensor_chip.h"
-#include "timer.h"
 #include "thermal.h"
+#include "timer.h"
 #include "usb_charge.h"
 #include "usb_mux.h"
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
@@ -61,40 +60,45 @@ static void warm_reset_request_interrupt(enum gpio_signal signal)
 	chipset_reset(CHIPSET_RESET_AP_REQ);
 }
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /******************************************************************************/
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] = {"BOARD_ID", 16, 4096, 0, STM32_AIN(10)},
+	[ADC_BOARD_ID] = { "BOARD_ID", 16, 4096, 0, STM32_AIN(10) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /******************************************************************************/
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{"tcpc0",   I2C_PORT_TCPC0,     1000, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 1000,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
 /* power signal list.  Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
-	{GPIO_PP1250_S3_PG,    POWER_SIGNAL_ACTIVE_HIGH, "PP1250_S3_PWR_GOOD"},
-	{GPIO_PP900_S0_PG,     POWER_SIGNAL_ACTIVE_HIGH, "PP900_S0_PWR_GOOD"},
-	{GPIO_AP_CORE_PG,      POWER_SIGNAL_ACTIVE_HIGH, "AP_PWR_GOOD"},
-	{GPIO_AP_EC_S3_S0_L,   POWER_SIGNAL_ACTIVE_LOW, "SUSPEND_DEASSERTED"},
+	{ GPIO_PP1250_S3_PG, POWER_SIGNAL_ACTIVE_HIGH, "PP1250_S3_PWR_GOOD" },
+	{ GPIO_PP900_S0_PG, POWER_SIGNAL_ACTIVE_HIGH, "PP900_S0_PWR_GOOD" },
+	{ GPIO_AP_CORE_PG, POWER_SIGNAL_ACTIVE_HIGH, "AP_PWR_GOOD" },
+	{ GPIO_AP_EC_S3_S0_L, POWER_SIGNAL_ACTIVE_LOW, "SUSPEND_DEASSERTED" },
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
 #ifdef CONFIG_TEMP_SENSOR_TMP432
 /* Temperature sensors data; must be in same order as enum temp_sensor_id. */
 const struct temp_sensor_t temp_sensors[] = {
-	{"TMP432_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-		TMP432_IDX_LOCAL, 4},
-	{"TMP432_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-		TMP432_IDX_REMOTE1, 4},
-	{"TMP432_Sensor_2", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-		TMP432_IDX_REMOTE2, 4},
+	{ "TMP432_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
+	  TMP432_IDX_LOCAL, 4 },
+	{ "TMP432_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
+	  TMP432_IDX_REMOTE1, 4 },
+	{ "TMP432_Sensor_2", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
+	  TMP432_IDX_REMOTE2, 4 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -103,9 +107,9 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
  * same order as enum temp_sensor_id. To always ignore any temp, use 0.
  */
 struct ec_thermal_config thermal_params[] = {
-	{{0, 0, 0}, 0, 0}, /* TMP432_Internal */
-	{{0, 0, 0}, 0, 0}, /* TMP432_Sensor_1 */
-	{{0, 0, 0}, 0, 0}, /* TMP432_Sensor_2 */
+	{ { 0, 0, 0 }, 0, 0 }, /* TMP432_Internal */
+	{ { 0, 0, 0 }, 0, 0 }, /* TMP432_Sensor_1 */
+	{ { 0, 0, 0 }, 0, 0 }, /* TMP432_Sensor_2 */
 };
 BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
 #endif
@@ -120,9 +124,8 @@ const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
 /******************************************************************************/
 /* Wake-up pins for hibernate */
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_POWER_BUTTON_L, GPIO_CHARGER_INT_L
-};
+const enum gpio_signal hibernate_wake_pins[] = { GPIO_POWER_BUTTON_L,
+						 GPIO_CHARGER_INT_L };
 const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 
 /******************************************************************************/
@@ -131,17 +134,20 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = I2C_PORT_TCPC0,
-			.addr_flags = FUSB302_I2C_SLAVE_ADDR_FLAGS,
+			.addr_flags = FUSB302_I2C_ADDR_FLAGS,
 		},
 		.drv = &fusb302_tcpm_drv,
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &virtual_usb_mux_driver,
+				.hpd_update = &virtual_hpd_update,
+			},
 	},
 };
 
@@ -168,8 +174,8 @@ int board_set_active_charge_port(int charge_port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			     int max_ma, int charge_mv)
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
 {
 	/*
 	 * NOP because there is no internal power therefore no charging.
@@ -185,13 +191,13 @@ int extpower_is_present(void)
 
 int pd_snk_is_vbus_provided(int port)
 {
-  /* Must be, if we're at a stage where this function is called. */
+	/* Must be, if we're at a stage where this function is called. */
 	return 1;
 }
 
 static void board_spi_enable(void)
 {
-	gpio_config_module(MODULE_SPI_MASTER, 1);
+	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
 
 	/* Enable clocks to SPI2 module */
 	STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
@@ -200,24 +206,22 @@ static void board_spi_enable(void)
 	STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2;
 	STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
 
-	spi_enable(CONFIG_SPI_ACCEL_PORT, 1);
+	spi_enable(&spi_devices[0], 1);
 }
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP,
-	     board_spi_enable,
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_spi_enable,
 	     MOTION_SENSE_HOOK_PRIO - 1);
 
 static void board_spi_disable(void)
 {
-	spi_enable(CONFIG_SPI_ACCEL_PORT, 0);
+	spi_enable(&spi_devices[0], 0);
 
 	/* Disable clocks to SPI2 module */
 	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
 
-	gpio_config_module(MODULE_SPI_MASTER, 0);
+	gpio_config_module(MODULE_SPI_CONTROLLER, 0);
 }
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN,
-		 board_spi_disable,
-		 MOTION_SENSE_HOOK_PRIO + 1);
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_spi_disable,
+	     MOTION_SENSE_HOOK_PRIO + 1);
 
 static void board_init(void)
 {
@@ -250,8 +254,8 @@ void board_config_pre_init(void)
 	 * Ch4: USART1_TX / Ch5: USART1_RX (1000)
 	 * Ch6: SPI2_RX / Ch7: SPI2_TX (0011)
 	 */
-	STM32_DMA_CSELR(STM32_DMAC_CH4) = (8 << 12) | (8 << 16) |
-					  (3 << 20) | (3 << 24);
+	STM32_DMA_CSELR(STM32_DMAC_CH4) = (8 << 12) | (8 << 16) | (3 << 20) |
+					  (3 << 24);
 }
 
 void board_hibernate(void)
@@ -296,16 +300,16 @@ struct {
 	enum rainier_board_version version;
 	int expect_mv;
 } const rainier_boards[] = {
-	{ BOARD_VERSION_REV0, 109 },   /* 51.1K , 2.2K(gru 3.3K) ohm */
-	{ BOARD_VERSION_REV1, 211 },   /* 51.1k , 6.8K ohm */
-	{ BOARD_VERSION_REV2, 319 },   /* 51.1K , 11K ohm */
-	{ BOARD_VERSION_REV3, 427 },   /* 56K   , 17.4K ohm */
-	{ BOARD_VERSION_REV4, 542 },   /* 51.1K , 22K ohm */
-	{ BOARD_VERSION_REV5, 666 },   /* 51.1K , 30K ohm */
-	{ BOARD_VERSION_REV6, 781 },   /* 51.1K , 39.2K ohm */
-	{ BOARD_VERSION_REV7, 900 },   /* 56K   , 56K ohm */
-	{ BOARD_VERSION_REV8, 1023 },  /* 47K   , 61.9K ohm */
-	{ BOARD_VERSION_REV9, 1137 },  /* 47K   , 80.6K ohm */
+	{ BOARD_VERSION_REV0, 109 }, /* 51.1K , 2.2K(gru 3.3K) ohm */
+	{ BOARD_VERSION_REV1, 211 }, /* 51.1k , 6.8K ohm */
+	{ BOARD_VERSION_REV2, 319 }, /* 51.1K , 11K ohm */
+	{ BOARD_VERSION_REV3, 427 }, /* 56K   , 17.4K ohm */
+	{ BOARD_VERSION_REV4, 542 }, /* 51.1K , 22K ohm */
+	{ BOARD_VERSION_REV5, 666 }, /* 51.1K , 30K ohm */
+	{ BOARD_VERSION_REV6, 781 }, /* 51.1K , 39.2K ohm */
+	{ BOARD_VERSION_REV7, 900 }, /* 56K   , 56K ohm */
+	{ BOARD_VERSION_REV8, 1023 }, /* 47K   , 61.9K ohm */
+	{ BOARD_VERSION_REV9, 1137 }, /* 47K   , 80.6K ohm */
 	{ BOARD_VERSION_REV10, 1240 }, /* 56K   , 124K ohm */
 	{ BOARD_VERSION_REV11, 1343 }, /* 51.1K , 150K ohm */
 	{ BOARD_VERSION_REV12, 1457 }, /* 47K   , 200K ohm */
@@ -347,18 +351,15 @@ int board_get_version(void)
 }
 
 /* Motion sensors */
-#ifdef HAS_TASK_MOTIONSENSE
 /* Mutexes */
 static struct mutex g_base_mutex;
 
 static struct bmi_drv_data_t g_bmi160_data;
 
 /* Matrix to rotate accelerometer into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1),  0},
-	{ FLOAT_TO_FP(-1), 0,  0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+				       { FLOAT_TO_FP(-1), 0, 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
 
 static struct bmp280_drv_data_t bmp280_drv_data;
 
@@ -378,7 +379,7 @@ struct motion_sensor_t motion_sensors[] = {
 	 .mutex = &g_base_mutex,
 	 .drv_data = &g_bmi160_data,
 	 .port = CONFIG_SPI_ACCEL_PORT,
-	 .i2c_spi_addr_flags = SLAVE_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
+	 .i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
 	 .rot_standard_ref = &base_standard_ref,
 	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
 	 .min_frequency = BMI_ACCEL_MIN_FREQ,
@@ -401,18 +402,11 @@ struct motion_sensor_t motion_sensors[] = {
 	 .mutex = &g_base_mutex,
 	 .drv_data = &g_bmi160_data,
 	 .port = CONFIG_SPI_ACCEL_PORT,
-	 .i2c_spi_addr_flags = SLAVE_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
+	 .i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
 	 .default_range = 1000, /* dps */
 	 .rot_standard_ref = &base_standard_ref,
 	 .min_frequency = BMI_GYRO_MIN_FREQ,
 	 .max_frequency = BMI_GYRO_MAX_FREQ,
-	 .config = {
-		 /* Enable gyro in S0 */
-		 [SENSOR_CONFIG_EC_S0] = {
-			 .odr = 10000 | ROUND_UP_FLAG,
-			 .ec_rate = 100 * MSEC,
-		 },
-	 },
 	},
 	[LID_BARO] = {
 	 .name = "Baro",
@@ -423,16 +417,15 @@ struct motion_sensor_t motion_sensors[] = {
 	 .drv = &bmp280_drv,
 	 .drv_data = &bmp280_drv_data,
 	 .port = CONFIG_SPI_ACCEL_PORT,
-	 .i2c_spi_addr_flags = SLAVE_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
+	 .i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
 	 .default_range = BIT(18), /*  1bit = 4 Pa, 16bit ~= 2600 hPa */
 	 .min_frequency = BMP280_BARO_MIN_FREQ,
 	 .max_frequency = BMP280_BARO_MAX_FREQ,
 	},
 };
 const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-#endif /* defined(HAS_TASK_MOTIONSENSE) */
 
-int board_allow_i2c_passthru(int port)
+int board_allow_i2c_passthru(const struct i2c_cmd_desc_t *cmd_desc)
 {
 	/*
 	 * Battery port is the only port passthru is allowed on and this board
@@ -440,18 +433,3 @@ int board_allow_i2c_passthru(int port)
 	 */
 	return 0;
 }
-
-int charge_want_shutdown(void)
-{
-	/*
-	 * power/rk3399.c assumes there is internal power. Therefore this stub
-	 * returns false to prevent arbitrary shutdown.
-	 */
-	return 0;
-}
-
-int charge_prevent_power_on(int power_button_pressed)
-{
-	/* Assume there is always sufficient power from charger to power on. */
-	return 0;
-}
diff --git a/board/rainier/board.h b/board/rainier/board.h
index 7ff319e0ea..745ebeaca8 100644
--- a/board/rainier/board.h
+++ b/board/rainier/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,19 +10,18 @@
 
 /* Optional modules */
 #define CONFIG_ADC
-#undef  CONFIG_ADC_WATCHDOG
+#undef CONFIG_ADC_WATCHDOG
 #define CONFIG_CHIPSET_RK3399
 #define CONFIG_CMD_ACCELS
 #define CONFIG_CMD_RTC
 #define CONFIG_HOSTCMD_RTC
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_CONTROLLER
 #define CONFIG_I2C_PASSTHRU_RESTRICTED
 #define CONFIG_LOW_POWER_IDLE
 #define CONFIG_POWER_COMMON
 #define CONFIG_SPI
-#define CONFIG_SPI_MASTER
-#define CONFIG_STM_HWTIMER32
+#define CONFIG_SPI_CONTROLLER
 /* Source RTCCLK from external 32.768kHz source on PC15/OSC32_IN. */
 #define CONFIG_STM32_CLOCK_LSE
 #define CONFIG_SWITCH
@@ -30,11 +29,11 @@
 
 #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands for testing */
 
-#undef  CONFIG_UART_CONSOLE
+#undef CONFIG_UART_CONSOLE
 #define CONFIG_UART_CONSOLE 1
 
 /* Region sizes are no longer a power of 2 so we can't enable MPU */
-#undef  CONFIG_MPU
+#undef CONFIG_MPU
 
 /* Enable a different power-on sequence than the one on gru */
 #undef CONFIG_CHIPSET_POWER_SEQ_VERSION
@@ -42,7 +41,6 @@
 
 /* Optional features */
 #define CONFIG_BOARD_PRE_INIT
-#define CONFIG_BOARD_VERSION_CUSTOM
 #define CONFIG_BUTTON_TRIGGERED_RECOVERY
 #define CONFIG_CHARGER_ILIM_PIN_DISABLED
 #define CONFIG_FORCE_CONSOLE_RESUME
@@ -56,7 +54,6 @@
 #define CONFIG_POWER_BUTTON
 #define CONFIG_POWER_BUTTON_IGNORE_LID
 #define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-#define CONFIG_SOFTWARE_PANIC
 #define CONFIG_VBOOT_HASH
 #define CONFIG_VOLUME_BUTTONS
 
@@ -68,7 +65,6 @@
 
 /* Motion Sensors */
 #define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCEL_INTERRUPTS
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
 #define CONFIG_BARO_BMP280
@@ -106,39 +102,38 @@
 #define CONFIG_USB_PD_COMM_LOCKED
 
 #define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_VOLTAGE_MV     12850
+#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 12850
 
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY 50000  /* us */
-#define PD_VCONN_SWAP_DELAY 5000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 50000 /* us */
 
 /* Timer selection */
-#define TIM_CLOCK32  2
+#define TIM_CLOCK32 2
 #define TIM_WATCHDOG 7
 
 /* 48 MHz SYSCLK clock frequency */
 #define CPU_CLOCK 48000000
 
 /* Optional for testing */
-#undef  CONFIG_PECI
-#undef  CONFIG_PSTORE
+#undef CONFIG_PECI
+#undef CONFIG_PSTORE
 
 #define CONFIG_TASK_PROFILING
 
 #define I2C_PORT_TCPC0 1
 
 /* Enable Accel over SPI */
-#define CONFIG_SPI_ACCEL_PORT    0  /* The first SPI master port (SPI2) */
+#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */
 
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
+#define CONFIG_MKBP_INPUT_DEVICES
 #define CONFIG_MKBP_EVENT
 #define CONFIG_MKBP_USE_GPIO
 /* Define the host events which are allowed to wakeup AP in S3. */
-#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \
-		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC))
+#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK                \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC))
 
 #ifndef __ASSEMBLER__
 
diff --git a/board/rainier/build.mk b/board/rainier/build.mk
index b77a900d56..b95d9dc46e 100644
--- a/board/rainier/build.mk
+++ b/board/rainier/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/rainier/ec.tasklist b/board/rainier/ec.tasklist
index ed574a1d6a..5008495942 100644
--- a/board/rainier/ec.tasklist
+++ b/board/rainier/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/rainier/gpio.inc b/board/rainier/gpio.inc
index 65bbfe1d6f..1cf1080e05 100644
--- a/board/rainier/gpio.inc
+++ b/board/rainier/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -90,4 +90,4 @@ ALTERNATE(PIN_MASK(B, 0x0038), 0, MODULE_SPI,        0)
 /* SPI SLAVE CS: PA15 */
 ALTERNATE(PIN_MASK(A, 0x8000), 0, MODULE_SPI,        0)
 /* SPI MASTER: PD1/3/4 */
-ALTERNATE(PIN_MASK(D, 0x001a), 1, MODULE_SPI_MASTER, 0)
+ALTERNATE(PIN_MASK(D, 0x001a), 1, MODULE_SPI_CONTROLLER, 0)
diff --git a/board/rainier/usb_pd_policy.c b/board/rainier/usb_pd_policy.c
index 6de1dc9271..b6c78d5e95 100644
--- a/board/rainier/usb_pd_policy.c
+++ b/board/rainier/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,13 +13,13 @@
 #include "system.h"
 #include "task.h"
 #include "timer.h"
-#include "util.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
+#include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 static uint8_t vbus_en;
 
diff --git a/board/rainier/vif_override.xml b/board/rainier/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/rainier/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/rammus/battery.c b/board/rammus/battery.c
index 916aac5fd3..9a538cc5e6 100644
--- a/board/rammus/battery.c
+++ b/board/rammus/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -17,8 +17,8 @@
 static enum battery_present batt_pres_prev = BP_NOT_SURE;
 
 /* Shutdown mode parameters to write to manufacturer access register */
-#define SB_SHIP_MODE_REG	SB_MANUFACTURER_ACCESS
-#define SB_SHUTDOWN_DATA	0x0010
+#define SB_SHIP_MODE_REG SB_MANUFACTURER_ACCESS
+#define SB_SHUTDOWN_DATA 0x0010
 
 static const struct battery_info info = {
 	.voltage_max = 13200,
@@ -63,8 +63,9 @@ static int battery_init(void)
 {
 	int batt_status;
 
-	return battery_status(&batt_status) ? 0 :
-		!!(batt_status & STATUS_INITIALIZED);
+	return battery_status(&batt_status) ?
+		       0 :
+		       !!(batt_status & STATUS_INITIALIZED);
 }
 
 /*
@@ -85,13 +86,13 @@ static int battery_check_disconnect(void)
 	uint8_t data[6];
 
 	/* Check if battery charging + discharging is disabled. */
-	rv = sb_read_mfgacc(PARAM_OPERATION_STATUS,
-			    SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data));
+	rv = sb_read_mfgacc(PARAM_OPERATION_STATUS, SB_ALT_MANUFACTURER_ACCESS,
+			    data, sizeof(data));
 	if (rv)
 		return BATTERY_DISCONNECT_ERROR;
 
-	if ((data[3] & (BATTERY_DISCHARGING_DISABLED |
-			BATTERY_CHARGING_DISABLED)) ==
+	if ((data[3] &
+	     (BATTERY_DISCHARGING_DISABLED | BATTERY_CHARGING_DISABLED)) ==
 	    (BATTERY_DISCHARGING_DISABLED | BATTERY_CHARGING_DISABLED))
 		return BATTERY_DISCONNECTED;
 
@@ -127,4 +128,3 @@ enum battery_present battery_is_present(void)
 	batt_pres_prev = batt_pres;
 	return batt_pres;
 }
-
diff --git a/board/rammus/board.c b/board/rammus/board.c
index 06210b2134..86bd039102 100644
--- a/board/rammus/board.c
+++ b/board/rammus/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,25 +6,30 @@
 /* Rammus board-specific configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "anx7447.h"
 #include "bd99992gw.h"
 #include "board_config.h"
 #include "button.h"
+#include "cbi_ssfc.h"
 #include "charge_manager.h"
-#include "charge_state.h"
 #include "charge_ramp.h"
+#include "charge_state.h"
 #include "charger.h"
 #include "chipset.h"
 #include "console.h"
 #include "cros_board_info.h"
-#include "driver/accelgyro_bmi_common.h"
 #include "driver/accel_bma2x2.h"
+#include "driver/accel_kionix.h"
+#include "driver/accel_kx022.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "driver/accelgyro_icm426xx.h"
+#include "driver/accelgyro_icm_common.h"
 #include "driver/charger/isl923x.h"
 #include "driver/tcpm/ps8xxx.h"
 #include "driver/tcpm/tcpci.h"
 #include "driver/tcpm/tcpm.h"
 #include "driver/temp_sensor/bd99992gw.h"
+#include "espi.h"
 #include "extpower.h"
 #include "gpio.h"
 #include "hooks.h"
@@ -35,6 +40,7 @@
 #include "math_util.h"
 #include "motion_lid.h"
 #include "motion_sense.h"
+#include "panic.h"
 #include "pi3usb9281.h"
 #include "power.h"
 #include "power_button.h"
@@ -53,13 +59,12 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 #include "util.h"
-#include "espi.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
-#define USB_PD_PORT_PS8751	1
-#define USB_PD_PORT_ANX7447	0
+#define USB_PD_PORT_PS8751 1
+#define USB_PD_PORT_ANX7447 0
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
@@ -105,14 +110,15 @@ void vbus1_evt(enum gpio_signal signal)
 
 void usb0_evt(enum gpio_signal signal)
 {
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
 }
 
 void usb1_evt(enum gpio_signal signal)
 {
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12, 0);
+	usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
 }
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /* Hibernate wake configuration */
@@ -126,23 +132,44 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* Vbus sensing (10x voltage divider). */
-	[ADC_VBUS] = {"VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
+	[ADC_VBUS] = { "VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT * 10,
+		       ADC_READ_MAX + 1, 0 },
 	/*
 	 * Adapter current output or battery charging/discharging current (uV)
 	 * 18x amplification on charger side.
 	 */
-	[ADC_AMON_BMON] = {"AMON_BMON", NPCX_ADC_CH1, ADC_MAX_VOLT*1000/18,
-			   ADC_READ_MAX+1, 0},
+	[ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH1, ADC_MAX_VOLT * 1000 / 18,
+			    ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* I2C port map */
-const struct i2c_port_t i2c_ports[]  = {
-	{"i2c_0_0", NPCX_I2C_PORT0_0, 400, GPIO_I2C0_0_SCL, GPIO_I2C0_0_SDA},
-	{"i2c_0_1", NPCX_I2C_PORT0_1, 400, GPIO_I2C0_1_SCL, GPIO_I2C0_1_SDA},
-	{"i2c_1",   NPCX_I2C_PORT1,   100, GPIO_I2C1_SCL,   GPIO_I2C1_SDA},
-	{"i2c_2",   NPCX_I2C_PORT2,   400, GPIO_I2C2_SCL,   GPIO_I2C2_SDA},
-	{"i2c_3",   NPCX_I2C_PORT3,   400, GPIO_I2C3_SCL,   GPIO_I2C3_SDA},
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "i2c_0_0",
+	  .port = NPCX_I2C_PORT0_0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_0_SCL,
+	  .sda = GPIO_I2C0_0_SDA },
+	{ .name = "i2c_0_1",
+	  .port = NPCX_I2C_PORT0_1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_1_SCL,
+	  .sda = GPIO_I2C0_1_SDA },
+	{ .name = "i2c_1",
+	  .port = NPCX_I2C_PORT1,
+	  .kbps = 100,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "i2c_2",
+	  .port = NPCX_I2C_PORT2,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "i2c_3",
+	  .port = NPCX_I2C_PORT3,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -161,7 +188,7 @@ struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = I2C_PORT_TCPC1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
 		},
 		.drv = &ps8xxx_tcpm_drv,
 	},
@@ -176,16 +203,20 @@ struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_PS8751] = {
-		.usb_port = USB_PD_PORT_PS8751,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_PS8751,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 	},
 	[USB_PD_PORT_ANX7447] = {
-		.usb_port = USB_PD_PORT_ANX7447,
-		.driver = &anx7447_usb_mux_driver,
-		.hpd_update = &anx7447_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_ANX7447,
+			.driver = &anx7447_usb_mux_driver,
+			.hpd_update = &anx7447_tcpc_update_hpd_status,
+		},
 	}
 };
 
@@ -228,7 +259,7 @@ static void ps8751_i2c_remap(void)
 	uint32_t board_version;
 
 	if (cbi_get_board_version(&board_version) != EC_SUCCESS ||
-		board_version > 1)
+	    board_version > 1)
 		return;
 	/*
 	 * Due to b/118063849, we separate the ps8751 and anx3447 to
@@ -258,9 +289,10 @@ void board_tcpc_init(void)
 	 * HPD pulse to enable video path
 	 */
 	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		usb_mux_hpd_update(port, 0, 0);
+		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
 
 uint16_t tcpc_get_alert_status(void)
 {
@@ -280,17 +312,17 @@ uint16_t tcpc_get_alert_status(void)
 }
 
 const struct temp_sensor_t temp_sensors[] = {
-	{"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0},
+	{ "Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0 },
 
 	/* These BD99992GW temp sensors are only readable in S0 */
-	{"Ambient", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM0},
-	{"Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM1},
-	{"DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM2},
-	{"eMMC", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM3},
+	{ "Ambient", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM0 },
+	{ "Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM1 },
+	{ "DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM2 },
+	{ "eMMC", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM3 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -306,8 +338,8 @@ static void board_report_pmic_fault(const char *str)
 	uint32_t info;
 
 	/* RESETIRQ1 -- Bit 4: VRFAULT */
-	if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x8, &vrfault)
-	    != EC_SUCCESS)
+	if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x8, &vrfault) !=
+	    EC_SUCCESS)
 		return;
 
 	if (!(vrfault & BIT(4)))
@@ -398,8 +430,7 @@ static void board_pmic_enable_slp_s0_vr_decay(void)
 	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x38, 0x7a);
 }
 
-__override void power_board_handle_host_sleep_event(
-		enum host_sleep_event state)
+__override void power_board_handle_host_sleep_event(enum host_sleep_event state)
 {
 	if (state == HOST_SLEEP_EVENT_S0IX_SUSPEND)
 		board_pmic_enable_slp_s0_vr_decay();
@@ -473,7 +504,7 @@ static void usb_charge_mode_init(void)
 	 * inhibit_charging_in_suspend.
 	 */
 	usb_charge_set_mode(0, CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE,
-			USB_DISALLOW_SUSPEND_CHARGE);
+			    USB_DISALLOW_SUSPEND_CHARGE);
 }
 DECLARE_HOOK(HOOK_INIT, usb_charge_mode_init, HOOK_PRIO_DEFAULT + 1);
 
@@ -517,36 +548,17 @@ int board_set_active_charge_port(int charge_port)
 	} else {
 		/* Make sure non-charging port is disabled */
 		gpio_set_level(charge_port ? GPIO_EN_USB_C0_CHARGE_EC_L :
-					     GPIO_EN_USB_C1_CHARGE_EC_L, 1);
+					     GPIO_EN_USB_C1_CHARGE_EC_L,
+			       1);
 		/* Enable charging port */
 		gpio_set_level(charge_port ? GPIO_EN_USB_C1_CHARGE_EC_L :
-					     GPIO_EN_USB_C0_CHARGE_EC_L, 0);
+					     GPIO_EN_USB_C0_CHARGE_EC_L,
+			       0);
 	}
 
 	return EC_SUCCESS;
 }
 
-/**
- * Set the charge limit based upon desired maximum.
- *
- * @param port          Port number.
- * @param supplier      Charge supplier type.
- * @param charge_ma     Desired charge limit (mA).
- * @param charge_mv     Negotiated charge voltage (mV).
- */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	/*
-	 * Limit the input current to 96% negotiated limit,
-	 * to account for the charger chip margin.
-	 */
-	charge_ma = charge_ma * 96 / 100;
-	charge_set_input_current_limit(
-			MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT),
-			charge_mv);
-}
-
 void board_hibernate(void)
 {
 	CPRINTS("Triggering PMIC shutdown.");
@@ -583,21 +595,98 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 static struct bmi_drv_data_t g_bmi160_data;
+static struct icm_drv_data_t g_icm426xx_data;
 
-/* BMA255 private data */
+/* private data */
 static struct accelgyro_saved_data_t g_bma255_data;
+static struct kionix_accel_data g_kx022_data;
 
 /* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0 },
-	{ 0,  FLOAT_TO_FP(-1), 0 },
-	{ 0, 0, FLOAT_TO_FP(-1) }
+const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+				       { 0, FLOAT_TO_FP(-1), 0 },
+				       { 0, 0, FLOAT_TO_FP(-1) } };
+
+const mat33_fp_t base_standard_ref_icm = { { 0, FLOAT_TO_FP(1), 0 },
+					   { FLOAT_TO_FP(1), 0, 0 },
+					   { 0, 0, FLOAT_TO_FP(-1) } };
+
+const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				      { 0, FLOAT_TO_FP(1), 0 },
+				      { 0, 0, FLOAT_TO_FP(-1) } };
+
+struct motion_sensor_t base_accel_icm = {
+	.name = "Base Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.rot_standard_ref = &base_standard_ref_icm,
+	.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
+	.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
+	.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+		/* Sensor on in S3 */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 0,
+		},
+	},
 };
 
-const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0 },
-	{ 0,  FLOAT_TO_FP(1), 0 },
-	{ 0, 0, FLOAT_TO_FP(-1) }
+struct motion_sensor_t base_gyro_icm = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &base_standard_ref_icm,
+	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
+	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
+};
+
+struct motion_sensor_t lid_accel_kx022 = {
+	.name = "Lid Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_KX022,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_LID,
+	.drv = &kionix_accel_drv,
+	.mutex = &g_lid_mutex,
+	.drv_data = &g_kx022_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
+	.rot_standard_ref = &lid_standard_ref,
+	.min_frequency = KX022_ACCEL_MIN_FREQ,
+	.max_frequency = KX022_ACCEL_MAX_FREQ,
+	.default_range = 2, /* g, to support lid angle calculation. */
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 0,
+		},
+		/* Sensor on in S3 */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 0,
+		},
+	},
 };
 
 struct motion_sensor_t motion_sensors[] = {
@@ -676,9 +765,33 @@ struct motion_sensor_t motion_sensors[] = {
 };
 const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
+void motion_interrupt(enum gpio_signal signal)
+{
+	if (get_cbi_ssfc_base_sensor() == SSFC_SENSOR_BASE_ICM426XX)
+		icm426xx_interrupt(signal);
+	else
+		bmi160_interrupt(signal);
+}
+
+static void board_detect_motionsense(void)
+{
+	if (get_cbi_ssfc_lid_sensor() == SSFC_SENSOR_LID_KX022) {
+		motion_sensors[LID_ACCEL] = lid_accel_kx022;
+		ccprints("LID_ACCEL is KX022");
+	} else
+		ccprints("LID_ACCEL is BMA253");
+
+	if (get_cbi_ssfc_base_sensor() == SSFC_SENSOR_BASE_ICM426XX) {
+		motion_sensors[BASE_ACCEL] = base_accel_icm;
+		motion_sensors[BASE_GYRO] = base_gyro_icm;
+		ccprints("BASE_ACCEL is ICM426XX");
+	} else
+		ccprints("BASE_ACCEL is BMI160");
+}
+DECLARE_HOOK(HOOK_INIT, board_detect_motionsense, HOOK_PRIO_DEFAULT);
+
 /* Enable or disable input devices, based on chipset state and tablet mode */
-#ifndef TEST_BUILD
-void lid_angle_peripheral_enable(int enable)
+__override void lid_angle_peripheral_enable(int enable)
 {
 	/* If the lid is in 360 position, ignore the lid angle,
 	 * which might be faulty. Disable keyboard.
@@ -687,7 +800,6 @@ void lid_angle_peripheral_enable(int enable)
 		enable = 0;
 	keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
 }
-#endif
 
 static void board_chipset_reset(void)
 {
diff --git a/board/rammus/board.h b/board/rammus/board.h
index 7a569392a5..bfe8f75e53 100644
--- a/board/rammus/board.h
+++ b/board/rammus/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,20 +8,28 @@
 #ifndef __CROS_EC_BOARD_H
 #define __CROS_EC_BOARD_H
 
+/*
+ * By default, enable all console messages excepted HC, ACPI and event:
+ * The sensor stack is generating a lot of activity.
+ */
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
+#undef CONFIG_HOSTCMD_DEBUG_MODE
+#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
+
 /* EC */
 #define CONFIG_ADC
 #define CONFIG_BACKLIGHT_LID
 #define CONFIG_BOARD_VERSION_CBI
 #define CONFIG_BOARD_FORCE_RESET_PIN
 #define CONFIG_CRC8
-#define CONFIG_CROS_BOARD_INFO
+#define CONFIG_CBI_EEPROM
 #define CONFIG_DPTF
-#define CONFIG_FLASH_SIZE 0x80000
+#define CONFIG_FLASH_SIZE_BYTES 0x80000
 #define CONFIG_FPU
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_CONTROLLER
 #define CONFIG_KEYBOARD_COL2_INVERTED
-#undef  CONFIG_KEYBOARD_VIVALDI
+#undef CONFIG_KEYBOARD_VIVALDI
 #define CONFIG_KEYBOARD_PROTOCOL_8042
 #define CONFIG_LED_COMMON
 #define CONFIG_LID_SWITCH
@@ -30,7 +38,6 @@
 #define CONFIG_CHIP_PANIC_BACKUP
 #define CONFIG_PWM
 #define CONFIG_PWM_KBLIGHT
-#define CONFIG_SOFTWARE_PANIC
 #define CONFIG_SPI_FLASH_REGS
 #define CONFIG_SPI_FLASH_W25X40
 #define CONFIG_VBOOT_HASH
@@ -58,9 +65,9 @@
 #define CONFIG_CHIPSET_SKYLAKE
 #define CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET
 #define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#define CONFIG_HOST_INTERFACE_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 #define CONFIG_HOSTCMD_FLASH_SPI_INFO
 
 /* Battery */
@@ -68,7 +75,8 @@
 #define CONFIG_BATTERY_HW_PRESENT_CUSTOM
 #define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
 #define CONFIG_BATTERY_SMART
-#define CONFIG_BATTERY_LEVEL_NEAR_FULL 94
+#undef CONFIG_BATT_HOST_FULL_FACTOR
+#define CONFIG_BATT_HOST_FULL_FACTOR 94
 
 /* Charger */
 #define CONFIG_CHARGE_MANAGER
@@ -77,16 +85,18 @@
 #define CONFIG_CHARGER
 #define CONFIG_CHARGER_ISL9238
 #define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT 512
-#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 2
+#define CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT 512
+#define CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT 512
 #define CONFIG_CHARGER_PSYS
 #define CONFIG_CHARGER_SENSE_RESISTOR 10
 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 20
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 4 /* charger margin */
 #define CONFIG_CMD_CHARGER_ADC_AMON_BMON
 #define CONFIG_HOSTCMD_PD_CONTROL
 #define CONFIG_EXTPOWER_GPIO
-#undef   CONFIG_EXTPOWER_DEBOUNCE_MS
-#define  CONFIG_EXTPOWER_DEBOUNCE_MS 1000
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
+#define CONFIG_EXTPOWER_DEBOUNCE_MS 1000
 #define CONFIG_POWER_BUTTON
 #define CONFIG_POWER_BUTTON_X86
 #define CONFIG_POWER_COMMON
@@ -113,9 +123,12 @@
 #define CONFIG_ACCELGYRO_BMI160
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+#define CONFIG_ACCELGYRO_ICM426XX
+#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 #define CONFIG_ACCELGYRO_BMI160_INT2_OUTPUT
 #define CONFIG_ACCEL_BMA255
-#define CONFIG_ACCEL_INTERRUPTS
+#define CONFIG_ACCEL_KX022
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
 #define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
@@ -130,13 +143,13 @@
 /* Depends on how fast the AP boots and typical ODRs */
 #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
 
-#undef  CONFIG_UART_TX_BUF_SIZE
+#undef CONFIG_UART_TX_BUF_SIZE
 #define CONFIG_UART_TX_BUF_SIZE 1024
 
 #define CONFIG_TABLET_MODE
 #define CONFIG_TABLET_MODE_SWITCH
 #define CONFIG_GMR_TABLET_MODE
-#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE
+#define GPIO_TABLET_MODE_L GPIO_TABLET_MODE
 
 /* USB */
 #define CONFIG_USB_CHARGER
@@ -171,45 +184,45 @@
 #define CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT 2
 
 /* Optional feature to configure npcx chip */
-#define NPCX_UART_MODULE2	1 /* 1:GPIO64/65 as UART */
-#define NPCX_JTAG_MODULE2	0 /* 0:GPIO21/17/16/20 as JTAG */
-#define NPCX_TACH_SEL2		0 /* 0:GPIO40/73 as TACH */
+#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART */
+#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 as JTAG */
+#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 as TACH */
 
 /* I2C ports */
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT0_0
-#define I2C_PORT_TCPC1		NPCX_I2C_PORT0_1
-#define I2C_PORT_USB_CHARGER_1	NPCX_I2C_PORT0_1
-#define I2C_PORT_USB_CHARGER_0	NPCX_I2C_PORT1
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT1
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT0_0
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT1
-#define I2C_PORT_PMIC		NPCX_I2C_PORT2
-#define I2C_PORT_MP2949		NPCX_I2C_PORT2
-#define I2C_PORT_GYRO		NPCX_I2C_PORT3
-#define I2C_PORT_ACCEL		I2C_PORT_GYRO
-#define I2C_PORT_THERMAL	I2C_PORT_PMIC
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0
+#define I2C_PORT_TCPC1 NPCX_I2C_PORT0_1
+#define I2C_PORT_USB_CHARGER_1 NPCX_I2C_PORT0_1
+#define I2C_PORT_USB_CHARGER_0 NPCX_I2C_PORT1
+#define I2C_PORT_CHARGER NPCX_I2C_PORT1
+#define I2C_PORT_EEPROM NPCX_I2C_PORT0_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT1
+#define I2C_PORT_PMIC NPCX_I2C_PORT2
+#define I2C_PORT_MP2949 NPCX_I2C_PORT2
+#define I2C_PORT_GYRO NPCX_I2C_PORT3
+#define I2C_PORT_ACCEL I2C_PORT_GYRO
+#define I2C_PORT_THERMAL I2C_PORT_PMIC
 
 /* I2C addresses */
-#define I2C_ADDR_BD99992_FLAGS	0x30
-#define I2C_ADDR_MP2949_FLAGS	0x20
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_ADDR_BD99992_FLAGS 0x30
+#define I2C_ADDR_MP2949_FLAGS 0x20
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 
 /* Rename GPIOs */
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_SUS_L	GPIO_SLP_SUS_L_PCH
-#define GPIO_RSMRST_L_PGOOD	GPIO_ROP_EC_RSMRST_L
-#define GPIO_PMIC_DPWROK	GPIO_ROP_DSW_PWROK
-#define GPIO_POWER_BUTTON_L	GPIO_PWR_BTN_ODL
-#define GPIO_VOLUME_DOWN_L	GPIO_VOLDN_BTN
-#define GPIO_VOLUME_UP_L	GPIO_VOLUP_BTN
-#define GPIO_AC_PRESENT		GPIO_ROP_EC_ACOK
-#define GPIO_ENABLE_BACKLIGHT	GPIO_BL_DISABLE_L
-#define GPIO_CPU_PROCHOT	GPIO_PCH_PROCHOT
-#define GPIO_PCH_PWRBTN_L	GPIO_PCH_PWR_BTN_L
-#define GPIO_EC_PLATFORM_RST	GPIO_PLATFORM_RST
-#define GPIO_PMIC_SLP_SUS_L	GPIO_SLP_SUS_L_PMIC
-#define GPIO_USB_C0_5V_EN	GPIO_EN_USB_C0_5V_OUT
-#define GPIO_USB_C1_5V_EN	GPIO_EN_USB_C1_5V_OUT
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_SUS_L GPIO_SLP_SUS_L_PCH
+#define GPIO_PG_EC_RSMRST_ODL GPIO_ROP_EC_RSMRST_L
+#define GPIO_PMIC_DPWROK GPIO_ROP_DSW_PWROK
+#define GPIO_POWER_BUTTON_L GPIO_PWR_BTN_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN
+#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN
+#define GPIO_AC_PRESENT GPIO_ROP_EC_ACOK
+#define GPIO_ENABLE_BACKLIGHT GPIO_BL_DISABLE_L
+#define GPIO_CPU_PROCHOT GPIO_PCH_PROCHOT
+#define GPIO_PCH_PWRBTN_L GPIO_PCH_PWR_BTN_L
+#define GPIO_EC_PLATFORM_RST GPIO_PLATFORM_RST
+#define GPIO_PMIC_SLP_SUS_L GPIO_SLP_SUS_L_PMIC
+#define GPIO_USB_C0_5V_EN GPIO_EN_USB_C0_5V_OUT
+#define GPIO_USB_C1_5V_EN GPIO_EN_USB_C1_5V_OUT
 
 #ifndef __ASSEMBLER__
 
@@ -217,11 +230,11 @@
 #include "registers.h"
 
 enum temp_sensor_id {
-	TEMP_SENSOR_BATTERY,	/* Smart Battery Temperature */
-	TEMP_SENSOR_AMBIENT,	/* BD99992GW SYSTHERM0 */
-	TEMP_SENSOR_CHARGER,	/* BD99992GW SYSTHERM1 */
-	TEMP_SENSOR_DRAM,	/* BD99992GW SYSTHERM2 */
-	TEMP_SENSOR_EMMC,	/* BD99992GW SYSTHERM3 */
+	TEMP_SENSOR_BATTERY, /* Smart Battery Temperature */
+	TEMP_SENSOR_AMBIENT, /* BD99992GW SYSTHERM0 */
+	TEMP_SENSOR_CHARGER, /* BD99992GW SYSTHERM1 */
+	TEMP_SENSOR_DRAM, /* BD99992GW SYSTHERM2 */
+	TEMP_SENSOR_EMMC, /* BD99992GW SYSTHERM3 */
 	TEMP_SENSOR_COUNT
 };
 
@@ -238,11 +251,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum adc_channel {
-	ADC_VBUS,
-	ADC_AMON_BMON,
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_VBUS, ADC_AMON_BMON, ADC_CH_COUNT };
 
 enum pwm_channel {
 	PWM_CH_KBLIGHT,
@@ -255,21 +264,21 @@ enum pwm_channel {
  * delay to turn on the power supply max is ~16ms.
  * delay to turn off the power supply max is about ~180ms.
  */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	250000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* delay to turn on/off vconn */
-#define PD_VCONN_SWAP_DELAY		5000   /* us */
 
 /* Define typical operating power and max power */
-#define PD_OPERATING_POWER_MW		15000
-#define PD_MAX_POWER_MW			45000
-#define PD_MAX_CURRENT_MA		3000
-#define PD_MAX_VOLTAGE_MV		20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 45000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Board specific handlers */
 void board_reset_pd_mcu(void);
 void board_set_tcpc_power_mode(int port, int mode);
+void motion_interrupt(enum gpio_signal signal);
 
 /* Sensors without hardware FIFO are in forced mode */
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
diff --git a/board/rammus/build.mk b/board/rammus/build.mk
index 21f6e4c99e..9bc5e8a822 100644
--- a/board/rammus/build.mk
+++ b/board/rammus/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -9,7 +9,7 @@
 CHIP:=npcx
 CHIP_VARIANT:=npcx5m6g
 
-board-y=board.o
+board-y=board.o cbi_ssfc.o
 board-$(CONFIG_BATTERY_SMART)+=battery.o
 board-$(CONFIG_LED_COMMON)+=led.o
 board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
diff --git a/board/rammus/cbi_ssfc.c b/board/rammus/cbi_ssfc.c
new file mode 100644
index 0000000000..99c303eac5
--- /dev/null
+++ b/board/rammus/cbi_ssfc.c
@@ -0,0 +1,36 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi_ssfc.h"
+#include "common.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "hooks.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+/* Cache SSFC on init since we don't expect it to change in runtime */
+static union rammus_cbi_ssfc cached_ssfc;
+BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
+
+static void cbi_ssfc_init(void)
+{
+	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
+		/* Default to 0 when CBI isn't populated */
+		cached_ssfc.raw_value = 0;
+
+	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
+}
+DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_INIT_I2C + 1);
+
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
+{
+	return cached_ssfc.lid_sensor;
+}
+
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
+{
+	return cached_ssfc.base_sensor;
+}
diff --git a/board/rammus/cbi_ssfc.h b/board/rammus/cbi_ssfc.h
new file mode 100644
index 0000000000..e6351db03f
--- /dev/null
+++ b/board/rammus/cbi_ssfc.h
@@ -0,0 +1,56 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _RAMMUS_CBI_SSFC__H_
+#define _RAMMUS_CBI_SSFC__H_
+
+#include "stdint.h"
+
+/****************************************************************************
+ * Rammus CBI Second Source Factory Cache
+ */
+
+/*
+ * Lid Sensor (Bits 2-0)
+ */
+enum ec_ssfc_lid_sensor {
+	SSFC_SENSOR_LID_DEFAULT = 0,
+	SSFC_SENSOR_LID_BMA255 = 1,
+	SSFC_SENSOR_LID_KX022 = 2
+};
+
+/*
+ * Base Sensor (Bits 5-3)
+ */
+enum ec_ssfc_base_sensor {
+	SSFC_SENSOR_BASE_DEFAULT = 0,
+	SSFC_SENSOR_BASE_BMI160 = 1,
+	SSFC_SENSOR_BASE_ICM426XX = 2,
+};
+
+union rammus_cbi_ssfc {
+	struct {
+		enum ec_ssfc_lid_sensor lid_sensor : 3;
+		enum ec_ssfc_base_sensor base_sensor : 3;
+		uint32_t reserved_2 : 26;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Get the Lid sensor type from SSFC_CONFIG.
+ *
+ * @return the Lid sensor board type.
+ */
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
+
+/**
+ * Get the base sensor type form SSFC_CONFIG.
+ *
+ * @return the base sensor board type.
+ */
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
+
+#endif /* _RAMMUS_CBI_SSFC__H_ */
diff --git a/board/rammus/ec.tasklist b/board/rammus/ec.tasklist
index f708a41386..c2738d28b5 100644
--- a/board/rammus/ec.tasklist
+++ b/board/rammus/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/rammus/gpio.inc b/board/rammus/gpio.inc
index b55fe6b47c..df12930ccd 100644
--- a/board/rammus/gpio.inc
+++ b/board/rammus/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,7 +26,7 @@ GPIO_INT(USB_C0_VBUS_DET_L,  PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP,     vbus0_
 GPIO_INT(USB_C1_VBUS_DET_L,  PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP,     vbus1_evt)
 GPIO_INT(USB_C0_BC12_INT_L,  PIN(D, 3), GPIO_INT_FALLING,                 usb0_evt)
 GPIO_INT(USB_C1_BC12_INT_L,  PIN(3, 3), GPIO_INT_FALLING,                 usb1_evt)
-GPIO_INT(BASE_SIXAXIS_INT_L, PIN(7, 3), GPIO_INT_FALLING | GPIO_SEL_1P8V, bmi160_interrupt)
+GPIO_INT(BASE_SIXAXIS_INT_L, PIN(7, 3), GPIO_INT_FALLING | GPIO_SEL_1P8V, motion_interrupt)
 GPIO_INT(TABLET_MODE,        PIN(C, 6), GPIO_INT_BOTH,                    gmr_tablet_switch_isr)
 
 GPIO(EN_PP3300_TRACKPAD,     PIN(4, 5), GPIO_OUT_LOW)                /* Enable TouchPad */
diff --git a/board/rammus/led.c b/board/rammus/led.c
index a86e11e3a0..d40c39c649 100644
--- a/board/rammus/led.c
+++ b/board/rammus/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -23,9 +23,8 @@
 #define LED_CHARGE_PULSE 10
 #define LED_POWER_PULSE 15
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-	EC_LED_ID_BATTERY_LED};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED,
+					     EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -47,24 +46,20 @@ enum led_power_state {
 };
 
 static const struct {
-	uint8_t led1:1;
-	uint8_t led2:1;
-} led_chg_state_table[] = {
-	[LED_STATE_DISCHARGE] = {LED_OFF, LED_OFF},
-	[LED_STATE_CHARGE] = {LED_OFF, LED_ON},
-	[LED_STATE_FULL] = {LED_ON, LED_OFF},
-	[LED_STATE_ERROR_PHASE0] = {LED_OFF, LED_OFF},
-	[LED_STATE_ERROR_PHASE1] = {LED_OFF, LED_ON}
-};
+	uint8_t led1 : 1;
+	uint8_t led2 : 1;
+} led_chg_state_table[] = { [LED_STATE_DISCHARGE] = { LED_OFF, LED_OFF },
+			    [LED_STATE_CHARGE] = { LED_OFF, LED_ON },
+			    [LED_STATE_FULL] = { LED_ON, LED_OFF },
+			    [LED_STATE_ERROR_PHASE0] = { LED_OFF, LED_OFF },
+			    [LED_STATE_ERROR_PHASE1] = { LED_OFF, LED_ON } };
 
 static const struct {
-	uint8_t led:1;
-} led_pwr_state_table[] = {
-	[LED_STATE_S0] = {LED_ON},
-	[LED_STATE_S3_PHASE0] = {LED_OFF},
-	[LED_STATE_S3_PHASE1] = {LED_ON},
-	[LED_STATE_S5] = {LED_OFF}
-};
+	uint8_t led : 1;
+} led_pwr_state_table[] = { [LED_STATE_S0] = { LED_ON },
+			    [LED_STATE_S3_PHASE0] = { LED_OFF },
+			    [LED_STATE_S3_PHASE1] = { LED_ON },
+			    [LED_STATE_S5] = { LED_OFF } };
 
 void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
 {
@@ -100,7 +95,7 @@ static void rammus_led_set_power(void)
 
 	chipset_state = chipset_in_state(CHIPSET_STATE_HARD_OFF) |
 			(chipset_in_state(CHIPSET_STATE_SOFT_OFF) << 1) |
-			(chipset_in_state(CHIPSET_STATE_SUSPEND)  << 2) |
+			(chipset_in_state(CHIPSET_STATE_SUSPEND) << 2) |
 			(chipset_in_state(CHIPSET_STATE_ON) << 3) |
 			(chipset_in_state(CHIPSET_STATE_STANDBY) << 4);
 
@@ -128,36 +123,37 @@ static void rammus_led_set_power(void)
 
 static void rammus_led_set_battery(void)
 {
-	enum charge_state chg_state = charge_get_state();
+	enum led_pwr_state chg_state = led_pwr_get_state();
 	int charge_percent = charge_get_percent();
 	static unsigned int charge_ticks;
 
 	/* CHIPSET_STATE_OFF */
 	switch (chg_state) {
-	case PWR_STATE_DISCHARGE:
+	case LED_PWRS_DISCHARGE:
 		if ((charge_get_flags() & CHARGE_FLAG_EXTERNAL_POWER) &&
-			charge_percent >= BATTERY_LEVEL_NEAR_FULL)
+		    charge_percent >= CONFIG_BATT_HOST_FULL_FACTOR)
 			config_battery_led(LED_STATE_FULL);
 		else
 			config_battery_led(LED_STATE_DISCHARGE);
 		charge_ticks = 0;
 		break;
-	case PWR_STATE_CHARGE:
+	case LED_PWRS_CHARGE:
 		config_battery_led(LED_STATE_CHARGE);
 		charge_ticks = 0;
 		break;
-	case PWR_STATE_ERROR:
+	case LED_PWRS_ERROR:
 		if ((charge_ticks++ % LED_TOTAL_TICKS) < LED_CHARGE_PULSE)
 			config_battery_led(LED_STATE_ERROR_PHASE0);
 		else
 			config_battery_led(LED_STATE_ERROR_PHASE1);
 		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-	case PWR_STATE_IDLE:
-		if(charge_get_flags() & CHARGE_FLAG_EXTERNAL_POWER)
-			config_battery_led(LED_STATE_FULL);
-		else
-			config_battery_led(LED_STATE_OFF);
+	case LED_PWRS_CHARGE_NEAR_FULL:
+	case LED_PWRS_IDLE:
+		config_battery_led(LED_STATE_DISCHARGE);
+		charge_ticks = 0;
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		config_battery_led(LED_STATE_FULL);
 		charge_ticks = 0;
 		break;
 	default:
diff --git a/board/rammus/usb_pd_policy.c b/board/rammus/usb_pd_policy.c
index 652c9bb259..f048fc5738 100644
--- a/board/rammus/usb_pd_policy.c
+++ b/board/rammus/usb_pd_policy.c
@@ -1,14 +1,14 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "atomic.h"
-#include "extpower.h"
 #include "charge_manager.h"
 #include "common.h"
 #include "console.h"
 #include "driver/tcpm/ps8xxx.h"
+#include "extpower.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "host_command.h"
@@ -16,17 +16,17 @@
 #include "system.h"
 #include "task.h"
 #include "timer.h"
-#include "util.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
+#include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT];
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5,
-							TYPEC_RP_1A5};
+static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5,
+							 TYPEC_RP_1A5 };
 
 int board_vbus_source_enabled(int port)
 {
@@ -53,7 +53,8 @@ int pd_set_power_supply_ready(int port)
 {
 	/* Disable charging */
 	gpio_set_level(port ? GPIO_EN_USB_C1_CHARGE_EC_L :
-			      GPIO_EN_USB_C0_CHARGE_EC_L, 1);
+			      GPIO_EN_USB_C0_CHARGE_EC_L,
+		       1);
 
 	/* Ensure we advertise the proper available current quota */
 	charge_manager_source_port(port, 1);
@@ -103,13 +104,11 @@ int pd_check_vconn_swap(int port)
 	return gpio_get_level(GPIO_SLP_SUS_L_PMIC);
 }
 
-__override void pd_execute_data_swap(int port,
-				     enum pd_data_role data_role)
+__override void pd_execute_data_swap(int port, enum pd_data_role data_role)
 {
 	/* Only port 0 supports device mode. */
 	if (port != 0)
 		return;
 
-	gpio_set_level(GPIO_USB2_ID2,
-		      (data_role == PD_ROLE_UFP) ? 1 : 0);
+	gpio_set_level(GPIO_USB2_ID2, (data_role == PD_ROLE_UFP) ? 1 : 0);
 }
diff --git a/board/rammus/vif_override.xml b/board/rammus/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/rammus/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/redrix/battery.c b/board/redrix/battery.c
new file mode 100644
index 0000000000..c5c144113b
--- /dev/null
+++ b/board/redrix/battery.c
@@ -0,0 +1,66 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "common.h"
+#include "compile_time_macros.h"
+
+/*
+ * Battery info for all Redrix battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	/* DynaPack CosMX Battery Information */
+	[BATTERY_DYNAPACK_COS] = {
+		.fuel_gauge = {
+			.manuf_name = "333-2C-14-A",
+			.ship_mode = {
+				.reg_addr = 0x0,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,	/* mV */
+			.voltage_normal = 7700,
+			.voltage_min = 6000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_DYNAPACK_COS;
diff --git a/board/redrix/board.c b/board/redrix/board.c
new file mode 100644
index 0000000000..84d4520e70
--- /dev/null
+++ b/board/redrix/board.c
@@ -0,0 +1,123 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "button.h"
+#include "charge_ramp.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/accelgyro_lsm6dsm.h"
+#include "driver/als_tcs3400.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "lid_switch.h"
+#include "peripheral_charger.h"
+#include "power.h"
+#include "power_button.h"
+#include "registers.h"
+#include "switch.h"
+#include "tablet_mode.h"
+#include "throttle_ap.h"
+#include "usbc_config.h"
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* Console output macros */
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+
+/* Battery discharging over-current limit is 8A */
+#define BATT_OC_LIMIT -8000
+
+/* PCHG control */
+#ifdef SECTION_IS_RW
+extern struct pchg_drv ctn730_drv;
+
+struct pchg pchgs[] = {
+	[0] = {
+		.cfg = &(const struct pchg_config) {
+			.drv = &ctn730_drv,
+			.i2c_port = I2C_PORT_WLC,
+			.irq_pin = GPIO_PEN_INT_ODL,
+			.full_percent = 96,
+			.block_size = 128,
+			/* A stylus needs about 700ms to complete recovery */
+			.rf_charge_msec = 1000,
+		},
+		.policy = {
+			[PCHG_CHIPSET_STATE_ON] = &pchg_policy_on,
+			[PCHG_CHIPSET_STATE_SUSPEND] = &pchg_policy_suspend,
+		},
+		.events = QUEUE_NULL(PCHG_EVENT_QUEUE_SIZE, enum pchg_event),
+	},
+};
+
+int board_get_pchg_count(void)
+{
+	return ARRAY_SIZE(pchgs);
+}
+#endif
+
+/******************************************************************************/
+/* USB-A charging control */
+
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_PP5000_USBA_R,
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
+
+/******************************************************************************/
+
+/* Called on AP S3 -> S0 transition */
+static void board_chipset_resume(void)
+{
+	/* Allow keyboard backlight to be enabled */
+	gpio_set_level(GPIO_EC_KB_BL_EN, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S0 -> S3 transition */
+static void board_chipset_suspend(void)
+{
+	/* Turn off the keyboard backlight if it's on. */
+	gpio_set_level(GPIO_EC_KB_BL_EN, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
+
+enum battery_present battery_hw_present(void)
+{
+	/* The GPIO is low when the battery is physically present */
+	return gpio_get_level(GPIO_EC_BATT_PRES_ODL) ? BP_NO : BP_YES;
+}
+
+int charger_profile_override(struct charge_state_data *curr)
+{
+	/* Turn off haptic pad LRA if battery discharing current over 8A */
+	if (!(curr->batt.flags & BATT_FLAG_BAD_CURRENT) &&
+	    curr->batt.current < BATT_OC_LIMIT)
+		gpio_set_level(GPIO_LRA_DIS_ODL, 0);
+	else
+		gpio_set_level(GPIO_LRA_DIS_ODL, 1);
+
+	return 0;
+}
+
+enum ec_status charger_profile_override_get_param(uint32_t param,
+						  uint32_t *value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+enum ec_status charger_profile_override_set_param(uint32_t param,
+						  uint32_t value)
+{
+	return EC_RES_INVALID_PARAM;
+}
diff --git a/board/redrix/board.h b/board/redrix/board.h
new file mode 100644
index 0000000000..65f63dc0bb
--- /dev/null
+++ b/board/redrix/board.h
@@ -0,0 +1,267 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Redrix board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "compile_time_macros.h"
+
+/* Baseboard features */
+#include "baseboard.h"
+
+/* Increase tx buffer size. */
+#undef CONFIG_UART_TX_BUF_SIZE
+#define CONFIG_UART_TX_BUF_SIZE 8192
+
+/*
+ * This will happen automatically on NPCX9 ES2 and later. Do not remove
+ * until we can confirm all earlier chips are out of service.
+ */
+#define CONFIG_HIBERNATE_PSL_VCC1_RST_WAKEUP
+
+/* Chipset */
+#define CONFIG_CHIPSET_RESUME_INIT_HOOK
+
+/* Sensors */
+#define CONFIG_ACCEL_BMA255 /* Lid accel */
+#define CONFIG_ACCEL_BMA4XX /* 2nd source Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
+#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_UPDATE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+
+/* TCS3400 ALS */
+#define CONFIG_ALS
+#define ALS_COUNT 1
+#define CONFIG_ALS_TCS3400
+#define CONFIG_ALS_TCS3400_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS)
+
+/* Enable sensor fifo, must also define the _SIZE and _THRES */
+#define CONFIG_ACCEL_FIFO
+/* FIFO size is in power of 2. */
+#define CONFIG_ACCEL_FIFO_SIZE 256
+/* Depends on how fast the AP boots and typical ODRs */
+#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
+
+/* Sensors without hardware FIFO are in forced mode */
+#define CONFIG_ACCEL_FORCE_MODE_MASK (BIT(LID_ACCEL) | BIT(CLEAR_ALS))
+
+/* Sensor console commands */
+#define CONFIG_CMD_ACCELS
+#define CONFIG_CMD_ACCEL_INFO
+
+/* WLC pins */
+#ifdef SECTION_IS_RW
+#define CONFIG_PERIPHERAL_CHARGER
+#define CONFIG_DEVICE_EVENT
+#define CONFIG_CTN730
+#define CONFIG_MKBP_EVENT_WAKEUP_MASK (BIT(EC_MKBP_EVENT_PCHG))
+#endif
+
+/* USB Type A Features */
+#define USB_PORT_COUNT 1
+#define CONFIG_USB_PORT_POWER_DUMB
+
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 6
+
+/* USB Type C and USB PD defines */
+#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
+
+#define CONFIG_IO_EXPANDER
+#define CONFIG_IO_EXPANDER_NCT38XX
+#define CONFIG_IO_EXPANDER_PORT_COUNT 2
+
+#define CONFIG_USB_PD_FRS_PPC
+
+#define CONFIG_USBC_RETIMER_INTEL_BB
+
+#define CONFIG_USBC_PPC_SYV682X
+#define CONFIG_USBC_PPC_NX20P3483
+
+/* TODO: b/193452481 - measure and check these values on redrix */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
+
+/*
+ * Passive USB-C cables only support up to 60W.
+ */
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
+
+/*
+ * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
+ * signal.
+ */
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
+
+#define GPIO_WLC_NRST_CONN GPIO_PEN_RST_L
+
+/* System has back-lit keyboard */
+#define CONFIG_PWM_KBLIGHT
+
+/* I2C Bus Configuration */
+
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+
+#define I2C_PORT_USB_C0_TCPC NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1
+
+#define I2C_PORT_USB_C0_PPC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1
+
+#define I2C_PORT_USB_C0_BC12 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1
+
+#define I2C_PORT_USB_C0_MUX NPCX_I2C_PORT3_0
+#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1
+
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_WLC NPCX_I2C_PORT7_0
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+
+/*
+ * see b/174768555#comment22
+ */
+#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x56
+#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x58
+
+/* Enabling Thunderbolt-compatible mode */
+#define CONFIG_USB_PD_TBT_COMPAT_MODE
+
+/* Enabling USB4 mode */
+#define CONFIG_USB_PD_USB4
+#define CONFIG_USB_PD_DATA_RESET_MSG
+
+/* Retimer */
+#define CONFIG_USBC_RETIMER_FW_UPDATE
+
+/* Thermal features */
+#define CONFIG_THERMISTOR
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_TEMP_SENSOR_POWER
+#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
+
+/* Fan features */
+#define CONFIG_FANS FAN_CH_COUNT
+#define CONFIG_CUSTOM_FAN_CONTROL
+#define RPM_DEVIATION 1
+
+/* Charger defines */
+#define CONFIG_CHARGER_BQ25720
+/*
+ * b/202915015: The IDCHG current limit is set in 512 mA steps.
+ * The value set here is somewhat specific to the battery pack being
+ * currently used. The limit here was set based on the battery's
+ * discharge current limit and what was tested to prevent the AP
+ * rebooting with low charge level batteries.
+ */
+#define CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA 8192
+#define CONFIG_CHARGER_BQ25720_VSYS_TH2_CUSTOM
+#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV 70
+#define CONFIG_CHARGE_RAMP_HW
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10
+#define CONFIG_CHARGER_PROFILE_OVERRIDE
+
+/* Keyboard features */
+#define CONFIG_KEYBOARD_FACTORY_TEST
+#define CONFIG_KEYBOARD_VIVALDI
+#define CONFIG_KEYBOARD_REFRESH_ROW3
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h" /* needed by registers.h */
+#include "registers.h"
+#include "usbc_config.h"
+
+enum adc_channel {
+	ADC_TEMP_SENSOR_1_DDR,
+	ADC_TEMP_SENSOR_2_SOC,
+	ADC_TEMP_SENSOR_3_CHARGER,
+	ADC_TEMP_SENSOR_4_REGULATOR,
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1_DDR,
+	TEMP_SENSOR_2_SOC,
+	TEMP_SENSOR_3_CHARGER,
+	TEMP_SENSOR_4_REGULATOR,
+	TEMP_SENSOR_COUNT
+};
+
+enum sensor_id {
+	LID_ACCEL = 0,
+	BASE_ACCEL,
+	BASE_GYRO,
+	CLEAR_ALS,
+	RGB_ALS,
+	SENSOR_COUNT
+};
+
+enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_C1_NCT38XX, IOEX_PORT_COUNT };
+
+enum battery_type { BATTERY_DYNAPACK_COS, BATTERY_TYPE_COUNT };
+
+enum pwm_channel {
+	PWM_CH_KBLIGHT = 0, /* PWM3 */
+	PWM_CH_FAN, /* PWM5 */
+	PWM_CH_FAN2, /* PWM7 */
+	PWM_CH_COUNT
+};
+
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_1, FAN_CH_COUNT };
+
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_1, MFT_CH_COUNT };
+
+#ifdef CONFIG_KEYBOARD_FACTORY_TEST
+extern const int keyboard_factory_scan_pins[][2];
+extern const int keyboard_factory_scan_pins_used;
+#endif
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/redrix/build.mk b/board/redrix/build.mk
new file mode 100644
index 0000000000..e021ebc4f4
--- /dev/null
+++ b/board/redrix/build.mk
@@ -0,0 +1,27 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Redrix board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx9
+CHIP_VARIANT:=npcx9m3f
+BASEBOARD:=brya
+
+board-y=
+board-y+=battery.o
+board-y+=board.o
+board-y+=cbi_ssfc.o
+board-y+=charger.o
+board-y+=fans.o
+board-y+=fw_config.o
+board-y+=i2c.o
+board-y+=keyboard.o
+board-y+=led.o
+board-y+=pwm.o
+board-y+=sensors.o
+board-y+=thermal.o
+board-y+=usbc_config.o
diff --git a/board/redrix/cbi_ssfc.c b/board/redrix/cbi_ssfc.c
new file mode 100644
index 0000000000..e0e954a7a6
--- /dev/null
+++ b/board/redrix/cbi_ssfc.c
@@ -0,0 +1,30 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi_ssfc.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "cros_board_info.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+/* Cache SSFC on init since we don't expect it to change in runtime */
+static union redrix_cbi_ssfc cached_ssfc;
+BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
+
+void board_init_ssfc(void)
+{
+	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
+		/* Default to 0 when CBI isn't populated */
+		cached_ssfc.raw_value = 0;
+
+	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
+}
+
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
+{
+	return cached_ssfc.lid_sensor;
+}
diff --git a/board/redrix/cbi_ssfc.h b/board/redrix/cbi_ssfc.h
new file mode 100644
index 0000000000..724daa3782
--- /dev/null
+++ b/board/redrix/cbi_ssfc.h
@@ -0,0 +1,39 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _REDRIX_CBI_SSFC_H_
+#define _REDRIX_CBI_SSFC_H_
+
+#include "stdint.h"
+
+/****************************************************************************
+ * Redrix CBI Second Source Factory Cache
+ */
+
+/*
+ * Lid Sensor (Bits 0-1)
+ */
+enum ec_ssfc_lid_sensor {
+	SSFC_SENSOR_LID_DEFAULT = 0,
+	SSFC_SENSOR_LID_BMA253 = 1,
+	SSFC_SENSOR_LID_BMA422 = 2
+};
+
+union redrix_cbi_ssfc {
+	struct {
+		enum ec_ssfc_lid_sensor lid_sensor : 2;
+		uint32_t reserved_1 : 30;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Get the Lid sensor type from SSFC_CONFIG.
+ *
+ * @return the Lid sensor board type.
+ */
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
+
+#endif /* _REDRIX_CBI_SSFC_H_ */
diff --git a/board/redrix/charger.c b/board/redrix/charger.c
new file mode 100644
index 0000000000..827152e115
--- /dev/null
+++ b/board/redrix/charger.c
@@ -0,0 +1,82 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/charger/bq25710.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+#ifndef CONFIG_ZEPHYR
+/* Charger Chip Configuration */
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = BQ25710_SMBUS_ADDR1_FLAGS,
+		.drv = &bq25710_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CHARGER_NUM);
+#endif
+
+int board_set_active_charge_port(int port)
+{
+	int is_valid_port = board_is_usb_pd_port_present(port);
+	int i;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTSUSB("Disabling all charger ports");
+
+		/* Disable all ports. */
+		for (i = 0; i < ppc_cnt; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (ppc_vbus_sink_enable(i, 0))
+				CPRINTSUSB("Disabling C%d as sink failed.", i);
+		}
+
+		return EC_SUCCESS;
+	} else if (!is_valid_port) {
+		return EC_ERROR_INVAL;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (ppc_is_sourcing_vbus(port)) {
+		CPRINTFUSB("Skip enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTSUSB("New charge port: C%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < ppc_cnt; i++) {
+		if (i == port)
+			continue;
+
+		if (ppc_vbus_sink_enable(i, 0))
+			CPRINTSUSB("C%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTSUSB("C%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/board/redrix/ec.tasklist b/board/redrix/ec.tasklist
new file mode 100644
index 0000000000..f755b40858
--- /dev/null
+++ b/board/redrix/ec.tasklist
@@ -0,0 +1,31 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ *
+ * USB_CHG_Px tasks must be contiguous (see USB_CHG_PORT_TO_TASK_ID(x)).
+ * PD_Cx tasks must be contiguous (see PD_PORT_TO_TASK_ID(x))
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, HOOKS_TASK_STACK_SIZE) \
+	TASK_ALWAYS(LED, led_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS_RW(PCHG, pchg_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, BASEBOARD_CHARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, BASEBOARD_CHIPSET_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, CONSOLE_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, BASEBOARD_POWERBTN_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, BASEBOARD_PD_INT_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, BASEBOARD_PD_INT_TASK_STACK_SIZE)
diff --git a/board/redrix/fans.c b/board/redrix/fans.c
new file mode 100644
index 0000000000..905e5b8ad7
--- /dev/null
+++ b/board/redrix/fans.c
@@ -0,0 +1,66 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Physical fans. These are logically separate from pwm_channels. */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "fan.h"
+#include "fan_chip.h"
+#include "hooks.h"
+#include "pwm.h"
+
+/* MFT channels. These are logically separate from pwm_channels. */
+const struct mft_t mft_channels[] = {
+	[MFT_CH_0] = {
+		.module = NPCX_MFT_MODULE_1,
+		.clk_src = TCKC_LFCLK,
+		.pwm_id = PWM_CH_FAN,
+	},
+	[MFT_CH_1] = {
+		.module = NPCX_MFT_MODULE_2,
+		.clk_src = TCKC_LFCLK,
+		.pwm_id = PWM_CH_FAN2,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
+
+static const struct fan_conf fan_conf_0 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
+	.pgood_gpio = -1,
+	.enable_gpio = GPIO_EN_PP5000_FAN,
+};
+
+static const struct fan_conf fan_conf_1 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_1, /* Use MFT id to control fan */
+	.pgood_gpio = -1,
+	.enable_gpio = GPIO_EN_PP5000_FAN2,
+};
+
+static const struct fan_rpm fan_rpm_0 = {
+	.rpm_min = 1900,
+	.rpm_start = 2900,
+	.rpm_max = 7300,
+};
+
+static const struct fan_rpm fan_rpm_1 = {
+	.rpm_min = 1900,
+	.rpm_start = 2900,
+	.rpm_max = 7300,
+};
+
+const struct fan_t fans[FAN_CH_COUNT] = {
+	[FAN_CH_0] = {
+		.conf = &fan_conf_0,
+		.rpm = &fan_rpm_0,
+	},
+	[FAN_CH_1] = {
+		.conf = &fan_conf_1,
+		.rpm = &fan_rpm_1,
+	},
+};
diff --git a/board/redrix/fw_config.c b/board/redrix/fw_config.c
new file mode 100644
index 0000000000..cfbf46291c
--- /dev/null
+++ b/board/redrix/fw_config.c
@@ -0,0 +1,55 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "fw_config.h"
+
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
+
+static union redrix_cbi_fw_config fw_config;
+BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
+
+/*
+ * FW_CONFIG defaults for redrix if the CBI.FW_CONFIG data is not
+ * initialized.
+ */
+static const union redrix_cbi_fw_config fw_config_defaults = {
+	.kb_bl = KEYBOARD_BACKLIGHT_ENABLED,
+};
+
+/****************************************************************************
+ * Redrix FW_CONFIG access
+ */
+void board_init_fw_config(void)
+{
+	if (cbi_get_fw_config(&fw_config.raw_value)) {
+		CPRINTS("CBI: Read FW_CONFIG failed, using board defaults");
+		fw_config = fw_config_defaults;
+	}
+
+	if (get_board_id() == 0) {
+		/*
+		 * Early boards have a zero'd out FW_CONFIG, so replace
+		 * it with a sensible default value.
+		 */
+		if (fw_config.raw_value == 0) {
+			CPRINTS("CBI: FW_CONFIG is zero, using board defaults");
+			fw_config = fw_config_defaults;
+		}
+	}
+}
+
+union redrix_cbi_fw_config get_fw_config(void)
+{
+	return fw_config;
+}
+
+bool ec_cfg_has_eps(void)
+{
+	return (fw_config.eps == EPS_ENABLED);
+}
diff --git a/board/redrix/fw_config.h b/board/redrix/fw_config.h
new file mode 100644
index 0000000000..02157bf23e
--- /dev/null
+++ b/board/redrix/fw_config.h
@@ -0,0 +1,52 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __BOARD_REDRIX_FW_CONFIG_H_
+#define __BOARD_REDRIX_FW_CONFIG_H_
+
+#include <stdint.h>
+
+/****************************************************************************
+ * CBI FW_CONFIG layout for Redrix board.
+ *
+ * Source of truth is the project/brya/redrix/config.star configuration file.
+ */
+
+enum ec_cfg_keyboard_backlight_type {
+	KEYBOARD_BACKLIGHT_DISABLED = 0,
+	KEYBOARD_BACKLIGHT_ENABLED = 1
+};
+
+enum ec_cfg_eps_type { EPS_DISABLED = 0, EPS_ENABLED = 1 };
+
+union redrix_cbi_fw_config {
+	struct {
+		uint32_t sd_db : 2;
+		enum ec_cfg_keyboard_backlight_type kb_bl : 1;
+		uint32_t audio : 3;
+		uint32_t lte_db : 2;
+		uint32_t ufc : 2;
+		enum ec_cfg_eps_type eps : 1;
+		uint32_t reserved_1 : 21;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Read the cached FW_CONFIG.  Guaranteed to have valid values.
+ *
+ * @return the FW_CONFIG for the board.
+ */
+union redrix_cbi_fw_config get_fw_config(void);
+
+/**
+ * Check if the FW_CONFIG has enabled privacy screen.
+ *
+ * @return true if board supports privacy screen, false if the board
+ * doesn't support it.
+ */
+bool ec_cfg_has_eps(void);
+
+#endif /* __BOARD_REDRIX_FW_CONFIG_H_ */
diff --git a/board/redrix/gpio.inc b/board/redrix/gpio.inc
new file mode 100644
index 0000000000..0f39efe33b
--- /dev/null
+++ b/board/redrix/gpio.inc
@@ -0,0 +1,153 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define MODULE_KB		MODULE_KEYBOARD_SCAN
+
+/* INTERRUPT GPIOs: */
+GPIO_INT(ACOK_OD,                        PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
+GPIO_INT(EC_ALS_RGB_INT_R_L,             PIN(D, 4), GPIO_INT_FALLING, tcs3400_interrupt)
+GPIO_INT(EC_IMU_INT_R_L,                 PIN(5, 6), GPIO_SEL_1P8V | GPIO_INT_FALLING, lsm6dsm_interrupt)
+GPIO_INT(EC_PROCHOT_IN_L,                PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
+GPIO_INT(EC_VOLDN_BTN_ODL,               PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(EC_VOLUP_BTN_ODL,               PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(EC_WP_ODL,                      PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(GSC_EC_PWR_BTN_ODL,             PIN(0, 1), GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW, power_button_interrupt)
+GPIO_INT(LID_OPEN,                       PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
+GPIO_INT(SEQ_EC_ALL_SYS_PG,              PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_DSW_PWROK,               PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_RSMRST_ODL,              PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,                       PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,                      PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SYS_SLP_S0IX_L,                 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(TABLET_MODE_L,                  PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
+GPIO_INT(USB_C0_BC12_INT_ODL,            PIN(C, 6), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C0_TCPC_INT_ODL,            PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C0_PPC_INT_ODL,             PIN(6, 2), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C0_RT_INT_ODL,              PIN(B, 1), GPIO_INT_FALLING, retimer_interrupt)
+GPIO_INT(USB_C1_TCPC_INT_ODL,            PIN(A, 2), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C1_BC12_INT_ODL,            PIN(8, 3), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C1_PPC_INT_ODL,             PIN(7, 0), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C1_RT_INT_ODL,              PIN(4, 1), GPIO_INT_FALLING, retimer_interrupt)
+
+/* WLC interrupt. GPIO_PULL_DOWN ensures no IRQ when WLC chip is off. */
+#ifdef SECTION_IS_RW
+GPIO_INT(PEN_INT_ODL, PIN(F, 5), GPIO_INT_RISING | GPIO_PULL_DOWN, pchg_irq)
+#endif
+
+/* USED GPIOs: */
+GPIO(CCD_MODE_ODL,                   PIN(E, 5), GPIO_INPUT)
+GPIO(CHARGER_VAP_OTG_EN,             PIN(9, 6), GPIO_OUT_LOW)
+GPIO(CPU_C10_GATE_L,                 PIN(6, 7), GPIO_INPUT)
+GPIO(EC_BATT_PRES_ODL,               PIN(A, 3), GPIO_INPUT)
+GPIO(EC_ENTERING_RW,                 PIN(0, 3), GPIO_OUT_LOW)
+GPIO(EC_EN_EDP_BL,                   PIN(D, 3), GPIO_OUT_HIGH)
+GPIO(EC_GSC_PACKET_MODE,             PIN(7, 5), GPIO_OUT_LOW)
+GPIO(EC_I2C_BAT_SCL,                 PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_BAT_SDA,                 PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SCL_R,              PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SDA_R,              PIN(B, 2), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,              PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SENSOR_SDA,              PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_USB_C0_PPC_BC_SCL,       PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_PPC_BC_SDA,       PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_RT_SCL,           PIN(D, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_RT_SDA,           PIN(D, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_TCPC_SCL,         PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_TCPC_SDA,         PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_MIX_SCL,          PIN(E, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_MIX_SDA,          PIN(E, 3), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_TCPC_SCL,         PIN(F, 3), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_TCPC_SDA,         PIN(F, 2), GPIO_INPUT)
+GPIO(EC_KB_BL_EN,                    PIN(8, 6), GPIO_OUT_LOW)
+GPIO(EC_PCHHOT_ODL,                  PIN(7, 4), GPIO_INPUT)
+GPIO(EC_PCH_INT_ODL,                 PIN(B, 0), GPIO_ODR_HIGH)
+GPIO(EC_PCH_PWR_BTN_ODL,             PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(EC_PCH_RSMRST_L,                PIN(A, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_RTCRST,                  PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_SYS_PWROK,               PIN(3, 7), GPIO_OUT_LOW)
+GPIO(EC_PCH_WAKE_R_ODL,              PIN(C, 0), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_ODL,                 PIN(6, 3), GPIO_ODR_HIGH)
+GPIO(EN_PP5000_FAN,                  PIN(6, 1), GPIO_OUT_LOW)
+GPIO(EN_PP5000_FAN2,                 PIN(5, 0), GPIO_OUT_LOW)
+GPIO(EN_PP5000_USBA_R,               PIN(D, 7), GPIO_OUT_LOW)
+GPIO(EN_S5_RAILS,                    PIN(B, 6), GPIO_OUT_LOW)
+GPIO(IMVP9_VRRDY_OD,                 PIN(4, 3), GPIO_INPUT)
+GPIO(PCH_PWROK,                      PIN(7, 2), GPIO_OUT_LOW)
+GPIO(SYS_RST_ODL,                    PIN(C, 5), GPIO_ODR_HIGH)
+GPIO(USB_C0_TCPC_RST_ODL,            PIN(A, 7), GPIO_ODR_LOW)
+GPIO(USB_C1_TCPC_RST_ODL,            PIN(A, 0), GPIO_ODR_LOW)
+GPIO(VCCST_PWRGD_OD,                 PIN(A, 4), GPIO_ODR_LOW)
+GPIO(PEN_RST_L,                      PIN(0, 2), GPIO_ODR_HIGH)
+GPIO(LRA_DIS_ODL,                    PIN(0, 4), GPIO_ODR_HIGH)	/* Disable haptic pad LRA */
+
+/* LED */
+GPIO(C0_CHARGE_LED_AMBER_L,          PIN(C, 4), GPIO_OUT_HIGH)	/* Amber C0 port */
+GPIO(C0_CHARGE_LED_WHITE_L,          PIN(C, 3), GPIO_OUT_HIGH)	/* White C0 port */
+GPIO(C1_CHARGE_LED_AMBER_L,          PIN(5, 7), GPIO_OUT_HIGH)	/* Amber C1 port */
+GPIO(C1_CHARGE_LED_WHITE_L,          PIN(9, 4), GPIO_OUT_HIGH)	/* White C1 port */
+GPIO(PWR_LED_WHITE_L,                PIN(C, 2), GPIO_OUT_HIGH)	/* Power LED */
+
+/* UART alternate functions */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)              /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */
+
+/* I2C alternate functions */
+ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)               /* GPIO33/I2C5_SCL0/CTS_L, GPIO36/RTS_L/I2C5_SDA0 */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)               /* GPIO87/I2C1_SDA0 */
+ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)               /* GPIO92/I2C2_SCL0, GPIO91/I2C2_SDA0, GPIO90/I2C1_SCL0 */
+ALTERNATE(PIN_MASK(B, 0x0c), 0, MODULE_I2C, 0)               /* GPIOB3/I2C7_SCL0/DCD_L, GPIOB2/I2C7_SDA0/DSR_L */
+ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, GPIO_SEL_1P8V)   /* GPIOB5/I2C0_SCL0, GPIOB4/I2C0_SDA0 */
+ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)               /* GPIOD1/I2C3_SCL0, GPIOD0/I2C3_SDA0 */
+ALTERNATE(PIN_MASK(E, 0x18), 0, MODULE_I2C, 0)               /* GPIOE4/I2C6_SCL1/I3C_SCL, GPIOE3/I2C6_SDA1/I3C_SDA */
+ALTERNATE(PIN_MASK(F, 0x0c), 0, MODULE_I2C, 0)               /* GPIOF3/I2C4_SCL1, GPIOF2/I2C4_SDA1 */
+
+/* PWM alternate functions */
+ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0)               /* GPIO40/TA1 */
+ALTERNATE(PIN_MASK(7, 0x08), 0, MODULE_PWM, 0)               /* GPIO73/TA2 */
+ALTERNATE(PIN_MASK(6, 0x01), 0, MODULE_PWM, 0)               /* GPIO60/PWM7 */
+ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)               /* GPIO80/PWM3 */
+ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)               /* GPIOB7/PWM5 */
+
+/* ADC alternate functions */
+ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0)               /* GPIO34/PS2_DAT2/ADC6 */
+ALTERNATE(PIN_MASK(4, 0x34), 0, MODULE_ADC, 0)               /* GPIO42/ADC3/RI_L, GPIO45/ADC0, GPIO44/ADC1 */
+ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0)               /* GPIOE1/ADC7 */
+
+/* KB alternate functions */
+ALTERNATE(PIN_MASK(0, 0xe0), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO10&P80_CLK/GPIO07, KSO11&P80_DAT/GPIO06, KSO12/GPIO05 */
+ALTERNATE(PIN_MASK(1, 0x7f), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO06/GPO13/GP_SEL_L, KSO07/GPO12/JEN_L, KSO03/GPIO16/JTAG_TDO0_SWO, KSO04/GPIO15/XNOR, KSO05/GPIO14, KSO08/GPIO11/CR_SOUT1, KSO09/GPIO10/CR_SIN1 */
+ALTERNATE(PIN_MASK(2, 0xfc), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI2/GPIO27/TRACEDATA1, KSI3/GPIO26/TRACEDATA0, KSI4/GPIO25/TRACECLK/GP_SCLK, KSI5/GPIO24/GP_MISO, KSI6/GPIO23/S_SBUB, KSI7/GPIO22/S_SBUA */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO00/GPIO21/JTAG_TCK_SWCLK, KSO01/GPIO20/JTAG_TMS_SWIO */
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI0/GPIO31/TRACEDATA3/GP_MOSI, KSI1/GPIO30/TRACEDATA2/GP_CS_L */
+
+/* PMU alternate functions */
+ALTERNATE(PIN_MASK(0, 0x01), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN2_L&GPI00/GPIO00 */
+ALTERNATE(PIN_MASK(0, 0x02), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW) /* GPIO01/PSL_IN3_L&GPI01 */
+ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN1_L&GPID2/GPIOD2 */
+
+/* Unused Pins */
+UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
+UNUSED(PIN(3, 2))       /* GPO32/TRIS_L */
+UNUSED(PIN(3, 5))       /* GPO35/CR_SOUT4/TEST_L */
+UNUSED(PIN(6, 6))       /* GPO66/ARM_L_x86 */
+UNUSED(PIN(8, 2))       /* KSO14/GPIO82 */
+
+/* Pre-configured PSL balls:  J8  K6 */
+
+/*
+ * The NPCX keyboard driver does not use named GPIOs to access
+ * keyboard scan pins, so we do not list them in *gpio.inc. However, when
+ * KEYBOARD_COL2_INVERTED is defined, this name is required.
+ */
+GPIO(EC_KSO_02_INV,               PIN(1, 7), GPIO_OUT_LOW)
+
+IOEX(USB_C0_OC_ODL,          EXPIN(IOEX_C0_NCT38XX, 0, 4), GPIO_ODR_HIGH)
+IOEX(USB_C0_FRS_EN,          EXPIN(IOEX_C0_NCT38XX, 0, 6), GPIO_OUT_LOW)
+IOEX(USB_C0_RT_RST_ODL,      EXPIN(IOEX_C0_NCT38XX, 0, 7), GPIO_ODR_LOW)
+
+IOEX(USB_C1_OC_ODL,          EXPIN(IOEX_C1_NCT38XX, 0, 4), GPIO_ODR_HIGH)
+IOEX(USB_C1_FRS_EN,          EXPIN(IOEX_C1_NCT38XX, 0, 6), GPIO_OUT_LOW)
+IOEX(USB_C1_RT_RST_ODL,      EXPIN(IOEX_C1_NCT38XX, 0, 7), GPIO_ODR_LOW)
diff --git a/board/redrix/i2c.c b/board/redrix/i2c.c
new file mode 100644
index 0000000000..c1a0c31b40
--- /dev/null
+++ b/board/redrix/i2c.c
@@ -0,0 +1,77 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "i2c.h"
+
+/* I2C port map configuration */
+const struct i2c_port_t i2c_ports[] = {
+	{
+		/* I2C0 */
+		.name = "sensor",
+		.port = I2C_PORT_SENSOR,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_SENSOR_SCL,
+		.sda = GPIO_EC_I2C_SENSOR_SDA,
+	},
+	{
+		/* I2C1 */
+		.name = "tcpc0",
+		.port = I2C_PORT_USB_C0_TCPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_TCPC_SDA,
+	},
+	{
+		/* I2C2 */
+		.name = "ppc0",
+		.port = I2C_PORT_USB_C0_PPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_PPC_BC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_PPC_BC_SDA,
+	},
+	{
+		/* I2C3 */
+		.name = "retimer0",
+		.port = I2C_PORT_USB_C0_MUX,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_RT_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_RT_SDA,
+	},
+	{
+		/* I2C4 C1 TCPC */
+		.name = "tcpc1",
+		.port = I2C_PORT_USB_C1_TCPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C1_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C1_TCPC_SDA,
+	},
+	{
+		/* I2C5 */
+		.name = "battery",
+		.port = I2C_PORT_BATTERY,
+		.kbps = 100,
+		.scl = GPIO_EC_I2C_BAT_SCL,
+		.sda = GPIO_EC_I2C_BAT_SDA,
+	},
+	{
+		/* I2C6 */
+		.name = "ppc1,retimer1",
+		.port = I2C_PORT_USB_C1_PPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C1_MIX_SCL,
+		.sda = GPIO_EC_I2C_USB_C1_MIX_SDA,
+	},
+	{
+		/* I2C7 */
+		.name = "charger,eeprom,wlc",
+		.port = I2C_PORT_EEPROM,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_MISC_SCL_R,
+		.sda = GPIO_EC_I2C_MISC_SDA_R,
+	},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/board/redrix/keyboard.c b/board/redrix/keyboard.c
new file mode 100644
index 0000000000..11cfaaa02d
--- /dev/null
+++ b/board/redrix/keyboard.c
@@ -0,0 +1,93 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "ec_commands.h"
+#include "fw_config.h"
+#include "keyboard_scan.h"
+#include "timer.h"
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/* Increase from 50 us, because KSO_02 passes through the H1. */
+	.output_settle_us = 80,
+	/* Other values should be the same as the default configuration. */
+	.debounce_down_us = 9 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x1c, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
+		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
+	},
+};
+
+static const struct ec_response_keybd_config keybd1 = {
+	.num_top_row_keys = 13,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_KBD_BKLIGHT_TOGGLE,	/* T8 */
+		TK_PLAY_PAUSE,		/* T9 */
+		TK_MICMUTE,		/* T10 */
+		TK_VOL_MUTE,		/* T11 */
+		TK_VOL_DOWN,		/* T12 */
+		TK_VOL_UP,		/* T13 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+static const struct ec_response_keybd_config keybd2 = {
+	.num_top_row_keys = 13,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_PRIVACY_SCRN_TOGGLE,	/* T8 */
+		TK_KBD_BKLIGHT_TOGGLE,	/* T9 */
+		TK_MICMUTE,		/* T10 */
+		TK_VOL_MUTE,		/* T11 */
+		TK_VOL_DOWN,		/* T12 */
+		TK_VOL_UP,		/* T13 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	if (ec_cfg_has_eps() == 0)
+		return &keybd1;
+	else
+		return &keybd2;
+}
+
+#ifdef CONFIG_KEYBOARD_FACTORY_TEST
+/*
+ * Map keyboard connector pins to EC GPIO pins for factory test.
+ * Pins mapped to {-1, -1} are skipped.
+ * The connector has 24 pins total, and there is no pin 0.
+ */
+const int keyboard_factory_scan_pins[][2] = {
+	{ -1, -1 }, { 0, 5 }, { 1, 1 },	  { 1, 0 },   { 0, 6 },
+	{ 0, 7 },   { 1, 4 }, { 1, 3 },	  { 1, 6 },   { 1, 7 },
+	{ 3, 1 },   { 2, 0 }, { 1, 5 },	  { 2, 6 },   { 2, 7 },
+	{ 2, 1 },   { 2, 4 }, { 2, 5 },	  { 1, 2 },   { 2, 3 },
+	{ 2, 2 },   { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 },
+};
+
+const int keyboard_factory_scan_pins_used =
+	ARRAY_SIZE(keyboard_factory_scan_pins);
+#endif
diff --git a/board/redrix/led.c b/board/redrix/led.c
new file mode 100644
index 0000000000..66170766c2
--- /dev/null
+++ b/board/redrix/led.c
@@ -0,0 +1,252 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power and battery LED control for Redrix
+ */
+
+#include "battery.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "chipset.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "host_command.h"
+#include "led_common.h"
+#include "task.h"
+
+#include <stdint.h>
+
+#define BAT_LED_ON 0
+#define BAT_LED_OFF 1
+
+#define POWER_LED_ON 0
+#define POWER_LED_OFF 1
+
+#define LED_TICK_INTERVAL_MS (500 * MSEC)
+#define LED_CYCLE_TIME_MS (2000 * MSEC)
+#define LED_TICKS_PER_CYCLE (LED_CYCLE_TIME_MS / LED_TICK_INTERVAL_MS)
+#define LED_ON_TIME_MS (1000 * MSEC)
+#define LED_ON_TICKS (LED_ON_TIME_MS / LED_TICK_INTERVAL_MS)
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_LEFT_LED,
+					     EC_LED_ID_RIGHT_LED,
+					     EC_LED_ID_POWER_LED };
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+enum led_color {
+	LED_OFF = 0,
+	LED_AMBER,
+	LED_WHITE,
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
+};
+
+enum led_port { LEFT_PORT = 0, RIGHT_PORT };
+
+static void led_set_color_battery(int port, enum led_color color)
+{
+	enum gpio_signal amber_led, white_led;
+
+	amber_led = (port == RIGHT_PORT ? GPIO_C1_CHARGE_LED_AMBER_L :
+					  GPIO_C0_CHARGE_LED_AMBER_L);
+	white_led = (port == RIGHT_PORT ? GPIO_C1_CHARGE_LED_WHITE_L :
+					  GPIO_C0_CHARGE_LED_WHITE_L);
+
+	switch (color) {
+	case LED_WHITE:
+		gpio_set_level(white_led, BAT_LED_ON);
+		gpio_set_level(amber_led, BAT_LED_OFF);
+		break;
+	case LED_AMBER:
+		gpio_set_level(white_led, BAT_LED_OFF);
+		gpio_set_level(amber_led, BAT_LED_ON);
+		break;
+	case LED_OFF:
+		gpio_set_level(white_led, BAT_LED_OFF);
+		gpio_set_level(amber_led, BAT_LED_OFF);
+		break;
+	default:
+		break;
+	}
+}
+
+void led_set_color_power(enum led_color color)
+{
+	switch (color) {
+	case LED_OFF:
+		gpio_set_level(GPIO_PWR_LED_WHITE_L, POWER_LED_OFF);
+		break;
+	case LED_WHITE:
+		gpio_set_level(GPIO_PWR_LED_WHITE_L, POWER_LED_ON);
+		break;
+	default:
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	switch (led_id) {
+	case EC_LED_ID_LEFT_LED:
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		break;
+	case EC_LED_ID_RIGHT_LED:
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		break;
+	case EC_LED_ID_POWER_LED:
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		break;
+	default:
+		break;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	switch (led_id) {
+	case EC_LED_ID_LEFT_LED:
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_battery(LEFT_PORT, LED_WHITE);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(LEFT_PORT, LED_AMBER);
+		else
+			led_set_color_battery(LEFT_PORT, LED_OFF);
+		break;
+	case EC_LED_ID_RIGHT_LED:
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_battery(RIGHT_PORT, LED_WHITE);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(RIGHT_PORT, LED_AMBER);
+		else
+			led_set_color_battery(RIGHT_PORT, LED_OFF);
+		break;
+	case EC_LED_ID_POWER_LED:
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_power(LED_WHITE);
+		else
+			led_set_color_power(LED_OFF);
+		break;
+	default:
+		return EC_ERROR_PARAM1;
+	}
+
+	return EC_SUCCESS;
+}
+
+/*
+ * Set active charge port color to the parameter, turn off all others.
+ * If no port is active (-1), turn off all LEDs.
+ */
+static void set_active_port_color(enum led_color color)
+{
+	int port = charge_manager_get_active_charge_port();
+
+	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
+		led_set_color_battery(RIGHT_PORT,
+				      (port == RIGHT_PORT) ? color : LED_OFF);
+	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
+		led_set_color_battery(LEFT_PORT,
+				      (port == LEFT_PORT) ? color : LED_OFF);
+}
+
+static void led_set_battery(void)
+{
+	static unsigned int battery_ticks;
+
+	battery_ticks++;
+
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
+		/* Always indicate when charging, even in suspend. */
+		set_active_port_color(LED_AMBER);
+		break;
+	case LED_PWRS_DISCHARGE:
+		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
+			if (charge_get_percent() < 10)
+				led_set_color_battery(
+					RIGHT_PORT,
+					(battery_ticks % LED_TICKS_PER_CYCLE <
+					 LED_ON_TICKS) ?
+						LED_AMBER :
+						LED_OFF);
+			else
+				led_set_color_battery(RIGHT_PORT, LED_OFF);
+		}
+
+		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) {
+			if (charge_get_percent() < 10)
+				led_set_color_battery(
+					LEFT_PORT,
+					(battery_ticks % LED_TICKS_PER_CYCLE <
+					 LED_ON_TICKS) ?
+						LED_AMBER :
+						LED_OFF);
+			else
+				led_set_color_battery(LEFT_PORT, LED_OFF);
+		}
+		break;
+	case LED_PWRS_ERROR:
+		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
+			led_set_color_battery(
+				RIGHT_PORT,
+				(battery_ticks & 0x1) ? LED_AMBER : LED_OFF);
+		}
+
+		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) {
+			led_set_color_battery(LEFT_PORT, (battery_ticks & 0x1) ?
+								 LED_AMBER :
+								 LED_OFF);
+		}
+		break;
+	case LED_PWRS_CHARGE_NEAR_FULL:
+		set_active_port_color(LED_WHITE);
+		break;
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		set_active_port_color(LED_WHITE);
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		set_active_port_color(
+			(battery_ticks % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
+				LED_AMBER :
+				LED_OFF);
+		break;
+	default:
+		/* Other states don't alter LED behavior */
+		break;
+	}
+}
+
+static void led_set_power(void)
+{
+	if (chipset_in_state(CHIPSET_STATE_ON))
+		led_set_color_power(LED_WHITE);
+	else
+		led_set_color_power(LED_OFF);
+}
+
+void led_task(void *u)
+{
+	uint32_t start_time;
+	uint32_t task_duration;
+
+	while (1) {
+		start_time = get_time().le.lo;
+
+		if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+			led_set_power();
+
+		led_set_battery();
+
+		/* Compute time for this iteration */
+		task_duration = get_time().le.lo - start_time;
+		/*
+		 * Compute wait time required to for next desired LED tick. If
+		 * the duration exceeds the tick time, then don't sleep.
+		 */
+		if (task_duration < LED_TICK_INTERVAL_MS)
+			usleep(LED_TICK_INTERVAL_MS - task_duration);
+	}
+}
diff --git a/board/redrix/pwm.c b/board/redrix/pwm.c
new file mode 100644
index 0000000000..12f8d7ed9f
--- /dev/null
+++ b/board/redrix/pwm.c
@@ -0,0 +1,35 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "hooks.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_KBLIGHT] = {
+		.channel = 3,
+		.flags = 0,
+		/*
+		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
+		 * flicker. Higher frequencies consume similar average power to
+		 * lower PWM frequencies, but higher frequencies record a much
+		 * lower maximum power.
+		 */
+		.freq = 2400,
+	},
+	[PWM_CH_FAN] = {
+		.channel = 5,
+		.flags = PWM_CONFIG_OPEN_DRAIN,
+		.freq = 25000
+	},
+	[PWM_CH_FAN2] = {
+		.channel = 7,
+		.flags = PWM_CONFIG_OPEN_DRAIN,
+		.freq = 25000
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
diff --git a/board/redrix/sensors.c b/board/redrix/sensors.c
new file mode 100644
index 0000000000..fa7a9ea670
--- /dev/null
+++ b/board/redrix/sensors.c
@@ -0,0 +1,383 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "accelgyro.h"
+#include "adc_chip.h"
+#include "cbi_ssfc.h"
+#include "common.h"
+#include "driver/accel_bma2x2.h"
+#include "driver/accel_bma422.h"
+#include "driver/accelgyro_lsm6dsm.h"
+#include "driver/als_tcs3400_public.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "motion_sense.h"
+#include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
+#include "thermal.h"
+
+/* ADC configuration */
+const struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_1_DDR] = {
+		.name = "TEMP_DDR",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_2_SOC] = {
+		.name = "TEMP_SOC",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_3_CHARGER] = {
+		.name = "TEMP_CHARGER",
+		.input_ch = NPCX_ADC_CH6,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_4_REGULATOR] = {
+		.name = "TEMP_REGULATOR",
+		.input_ch = NPCX_ADC_CH7,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+K_MUTEX_DEFINE(g_lid_accel_mutex);
+K_MUTEX_DEFINE(g_base_accel_mutex);
+static struct accelgyro_saved_data_t g_bma253_data;
+static struct accelgyro_saved_data_t g_bma422_data;
+static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
+
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, FLOAT_TO_FP(1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
+
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, FLOAT_TO_FP(1), 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
+
+/* TCS3400 private data */
+static struct als_drv_data_t g_tcs3400_data = {
+	.als_cal.scale = 1,
+	.als_cal.uscale = 0,
+	.als_cal.offset = 0,
+	.als_cal.channel_scale = {
+		.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kc from VPD */
+		.cover_scale = ALS_CHANNEL_SCALE(0.98),     /* CT */
+	},
+};
+
+/*
+ * TODO: b/184702900 need to calibrate ALS/RGB sensor. At default settings,
+ * shining phone flashlight on sensor pegs all readings at 0xFFFF.
+ */
+static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
+	.calibration.rgb_cal[X] = {
+		.offset = 66, /* 66.47729532 */
+		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0.00222243),
+		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0.51877192),
+		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(-0.28664117),
+		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0.0586877),
+		.scale = {
+			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kr */
+			.cover_scale = ALS_CHANNEL_SCALE(0.61)
+		}
+	},
+	.calibration.rgb_cal[Y] = {
+		.offset = 41, /* 40.95355984 */
+		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(-0.15384715),
+		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0.40454969),
+		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(-0.237452),
+		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0.13102168),
+		.scale = {
+			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kg */
+			.cover_scale = ALS_CHANNEL_SCALE(1.0)
+		},
+	},
+	.calibration.rgb_cal[Z] = {
+		.offset = 5, /* 5.08596128 */
+		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(-0.79005309),
+		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(-0.35553576),
+		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0.13997097),
+		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0.40223911),
+		.scale = {
+			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kb */
+			.cover_scale = ALS_CHANNEL_SCALE(1.6)
+		}
+	},
+	.calibration.irt = FLOAT_TO_FP(0.41),
+	.saturation.again = TCS_DEFAULT_AGAIN,
+	.saturation.atime = TCS_DEFAULT_ATIME,
+};
+
+struct motion_sensor_t motion_sensors[] = {
+	[LID_ACCEL] = {
+		.name = "Lid Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMA255,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &bma2x2_accel_drv,
+		.mutex = &g_lid_accel_mutex,
+		.drv_data = &g_bma253_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
+		.rot_standard_ref = &lid_standard_ref, /* identity matrix */
+		.default_range = 2, /* g */
+		.min_frequency = BMA255_ACCEL_MIN_FREQ,
+		.max_frequency = BMA255_ACCEL_MAX_FREQ,
+		.config = {
+			/* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+			/* Sensor on for lid angle detection */
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+		},
+	},
+
+	[BASE_ACCEL] = {
+		.name = "Base Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LSM6DSM,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &lsm6dsm_drv,
+		.mutex = &g_base_accel_mutex,
+		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
+				MOTIONSENSE_TYPE_ACCEL),
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
+		.rot_standard_ref = &base_standard_ref,
+		.default_range = 4,  /* g */
+		.min_frequency = LSM6DSM_ODR_MIN_VAL,
+		.max_frequency = LSM6DSM_ODR_MAX_VAL,
+		.config = {
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 13000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+		},
+	},
+
+	[BASE_GYRO] = {
+		.name = "Base Gyro",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LSM6DSM,
+		.type = MOTIONSENSE_TYPE_GYRO,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &lsm6dsm_drv,
+		.mutex = &g_base_accel_mutex,
+		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
+				MOTIONSENSE_TYPE_GYRO),
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
+		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = LSM6DSM_ODR_MIN_VAL,
+		.max_frequency = LSM6DSM_ODR_MAX_VAL,
+	},
+
+	[CLEAR_ALS] = {
+		.name = "Clear Light",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_TCS3400,
+		.type = MOTIONSENSE_TYPE_LIGHT,
+		.location = MOTIONSENSE_LOC_CAMERA,
+		.drv = &tcs3400_drv,
+		.drv_data = &g_tcs3400_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = TCS3400_I2C_ADDR_FLAGS,
+		.rot_standard_ref = NULL,
+		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
+		.min_frequency = TCS3400_LIGHT_MIN_FREQ,
+		.max_frequency = TCS3400_LIGHT_MAX_FREQ,
+		.config = {
+			/* Run ALS sensor in S0 */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 1000,
+			},
+		},
+	},
+
+	[RGB_ALS] = {
+		/*
+		 * RGB channels read by CLEAR_ALS and so the i2c port and
+		 * address do not need to be defined for RGB_ALS.
+		 */
+		.name = "RGB Light",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_TCS3400,
+		.type = MOTIONSENSE_TYPE_LIGHT_RGB,
+		.location = MOTIONSENSE_LOC_CAMERA,
+		.drv = &tcs3400_rgb_drv,
+		.drv_data = &g_tcs3400_rgb_data,
+		.rot_standard_ref = NULL,
+		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
+	},
+};
+const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+struct motion_sensor_t bma422_lid_accel = {
+	.name = "Lid Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_BMA422,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_LID,
+	.drv = &bma4_accel_drv,
+	.mutex = &g_lid_accel_mutex,
+	.drv_data = &g_bma422_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = BMA4_I2C_ADDR_PRIMARY,
+	.rot_standard_ref = &lid_standard_ref,
+	.default_range = 2, /* g, enough for laptop. */
+	.min_frequency = BMA4_ACCEL_MIN_FREQ,
+	.max_frequency = BMA4_ACCEL_MAX_FREQ,
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 12500 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+		/* Sensor on in S3 */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 12500 | ROUND_UP_FLAG,
+			.ec_rate = 0,
+		},
+	},
+};
+
+static void board_update_motion_sensor_config(void)
+{
+	if (get_cbi_ssfc_lid_sensor() == SSFC_SENSOR_LID_BMA422)
+		motion_sensors[LID_ACCEL] = bma422_lid_accel;
+}
+
+/* ALS instances when LPC mapping is needed. Each entry directs to a sensor. */
+const struct motion_sensor_t *motion_als_sensors[] = {
+	&motion_sensors[CLEAR_ALS],
+};
+BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
+
+static void board_sensors_init(void)
+{
+	/* Enable interrupt for the TCS3400 color light sensor */
+	gpio_enable_interrupt(GPIO_EC_ALS_RGB_INT_R_L);
+	/* Enable gpio interrupt for base accelgyro sensor */
+	gpio_enable_interrupt(GPIO_EC_IMU_INT_R_L);
+
+	board_update_motion_sensor_config();
+}
+DECLARE_HOOK(HOOK_INIT, board_sensors_init, HOOK_PRIO_INIT_I2C + 1);
+
+/* Temperature sensor configuration */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1_DDR] = { .name = "DDR",
+				.type = TEMP_SENSOR_TYPE_BOARD,
+				.read = get_temp_3v3_30k9_47k_4050b,
+				.idx = ADC_TEMP_SENSOR_1_DDR },
+	[TEMP_SENSOR_2_SOC] = { .name = "SOC",
+				.type = TEMP_SENSOR_TYPE_BOARD,
+				.read = get_temp_3v3_30k9_47k_4050b,
+				.idx = ADC_TEMP_SENSOR_2_SOC },
+	[TEMP_SENSOR_3_CHARGER] = { .name = "Charger",
+				    .type = TEMP_SENSOR_TYPE_BOARD,
+				    .read = get_temp_3v3_30k9_47k_4050b,
+				    .idx = ADC_TEMP_SENSOR_3_CHARGER },
+	[TEMP_SENSOR_4_REGULATOR] = { .name = "Regulator",
+				      .type = TEMP_SENSOR_TYPE_BOARD,
+				      .read = get_temp_3v3_30k9_47k_4050b,
+				      .idx = ADC_TEMP_SENSOR_4_REGULATOR },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_DDR              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_ddr = THERMAL_DDR;
+
+/*
+ * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
+ * 130 C.  However, sensor is located next to SOC, so we need to use the lower
+ * SOC temperature limit (85 C)
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
+
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CHARGER          \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(80), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(85), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_charger =
+	THERMAL_CHARGER;
+
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_REGULATOR        \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(80), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(85), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_regulator =
+	THERMAL_REGULATOR;
+
+/* this should really be "const" */
+struct ec_thermal_config thermal_params[] = {
+	[TEMP_SENSOR_1_DDR] = THERMAL_DDR,
+	[TEMP_SENSOR_2_SOC] = THERMAL_CPU,
+	[TEMP_SENSOR_3_CHARGER] = THERMAL_CHARGER,
+	[TEMP_SENSOR_4_REGULATOR] = THERMAL_REGULATOR,
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
diff --git a/board/redrix/thermal.c b/board/redrix/thermal.c
new file mode 100644
index 0000000000..e192157943
--- /dev/null
+++ b/board/redrix/thermal.c
@@ -0,0 +1,215 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "builtin/assert.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "fan.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "tablet_mode.h"
+#include "temp_sensor.h"
+#include "thermal.h"
+#include "util.h"
+
+/* Console output macros */
+#define CPUTS(outstr) cputs(CC_THERMAL, outstr)
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
+
+struct fan_step {
+	/*
+	 * Sensor 1~4 trigger point, set -1 if we're not using this
+	 * sensor to determine fan speed.
+	 */
+	int8_t on[TEMP_SENSOR_COUNT];
+
+	/*
+	 * Sensor 1~4 trigger point, set -1 if we're not using this
+	 * sensor to determine fan speed.
+	 */
+	int8_t off[TEMP_SENSOR_COUNT];
+
+	/* Fan 1~2 rpm */
+	uint16_t rpm[FAN_CH_COUNT];
+};
+
+static const struct fan_step *fan_step_table;
+
+static const struct fan_step fan_table_clamshell[] = {
+	{
+		/* level 0 */
+		.on = { 53, 53, 0, -1 },
+		.off = { 99, 99, 99, -1 },
+		.rpm = { 0, 0 },
+	},
+	{
+		/* level 1 */
+		.on = { 54, 54, 0, -1 },
+		.off = { 53, 53, 99, -1 },
+		.rpm = { 3900, 4300 },
+	},
+	{
+		/* level 2 */
+		.on = { 55, 55, 0, -1 },
+		.off = { 54, 54, 99, -1 },
+		.rpm = { 4800, 5200 },
+	},
+	{
+		/* level 3 */
+		.on = { 56, 56, 0, -1 },
+		.off = { 54, 55, 99, -1 },
+		.rpm = { 5000, 5500 },
+	},
+	{
+		/* level 4 */
+		.on = { 57, 57, 61, -1 },
+		.off = { 56, 56, 59, -1 },
+		.rpm = { 5200, 5700 },
+	},
+	{
+		/* level 5 */
+		.on = { 58, 58, 63, -1 },
+		.off = { 57, 57, 61, -1 },
+		.rpm = { 5700, 6200 },
+	},
+	{
+		/* level 6 */
+		.on = { 100, 100, 100, -1 },
+		.off = { 58, 58, 63, -1 },
+		.rpm = { 6200, 6400 },
+	},
+};
+
+static const struct fan_step fan_table_tablet[] = {
+	{
+		/* level 0 */
+		.on = { 52, 55, 0, -1 },
+		.off = { 99, 99, 99, -1 },
+		.rpm = { 0, 0 },
+	},
+	{
+		/* level 1 */
+		.on = { 53, 56, 0, -1 },
+		.off = { 52, 55, 99, -1 },
+		.rpm = { 4100, 4200 },
+	},
+	{
+		/* level 2 */
+		.on = { 54, 57, 0, -1 },
+		.off = { 53, 56, 99, -1 },
+		.rpm = { 4500, 4800 },
+	},
+	{
+		/* level 3 */
+		.on = { 55, 58, 0, -1 },
+		.off = { 54, 57, 99, -1 },
+		.rpm = { 4800, 5200 },
+	},
+	{
+		/* level 4 */
+		.on = { 56, 59, 61, -1 },
+		.off = { 55, 58, 59, -1 },
+		.rpm = { 5100, 5400 },
+	},
+	{
+		/* level 5 */
+		.on = { 57, 60, 63, -1 },
+		.off = { 56, 59, 61, -1 },
+		.rpm = { 5500, 5800 },
+	},
+	{
+		/* level 6 */
+		.on = { 100, 100, 100, -1 },
+		.off = { 57, 60, 63, -1 },
+		.rpm = { 6000, 6200 },
+	},
+};
+
+#define NUM_FAN_LEVELS ARRAY_SIZE(fan_table_clamshell)
+
+BUILD_ASSERT(ARRAY_SIZE(fan_table_clamshell) == ARRAY_SIZE(fan_table_tablet));
+
+int fan_table_to_rpm(int fan, int *temp)
+{
+	static int current_level;
+	static int prev_tmp[TEMP_SENSOR_COUNT];
+	int new_rpm = 0;
+	int i;
+
+	if (tablet_get_mode())
+		fan_step_table = fan_table_tablet;
+	else
+		fan_step_table = fan_table_clamshell;
+
+	/*
+	 * Compare the current and previous temperature, we have
+	 * the three paths :
+	 *  1. decreasing path. (check the release point)
+	 *  2. increasing path. (check the trigger point)
+	 *  3. invariant path. (return the current RPM)
+	 */
+	if (temp[TEMP_SENSOR_1_DDR] < prev_tmp[TEMP_SENSOR_1_DDR] ||
+	    temp[TEMP_SENSOR_2_SOC] < prev_tmp[TEMP_SENSOR_2_SOC] ||
+	    temp[TEMP_SENSOR_3_CHARGER] < prev_tmp[TEMP_SENSOR_3_CHARGER]) {
+		for (i = current_level; i > 0; i--) {
+			if (temp[TEMP_SENSOR_1_DDR] <
+				    fan_step_table[i].off[TEMP_SENSOR_1_DDR] &&
+			    temp[TEMP_SENSOR_3_CHARGER] <
+				    fan_step_table[i]
+					    .off[TEMP_SENSOR_3_CHARGER] &&
+			    temp[TEMP_SENSOR_2_SOC] <
+				    fan_step_table[i].off[TEMP_SENSOR_2_SOC])
+				current_level = i - 1;
+			else
+				break;
+		}
+	} else if (temp[TEMP_SENSOR_1_DDR] > prev_tmp[TEMP_SENSOR_1_DDR] ||
+		   temp[TEMP_SENSOR_2_SOC] > prev_tmp[TEMP_SENSOR_2_SOC] ||
+		   temp[TEMP_SENSOR_3_CHARGER] >
+			   prev_tmp[TEMP_SENSOR_3_CHARGER]) {
+		for (i = current_level; i < NUM_FAN_LEVELS; i++) {
+			if ((temp[TEMP_SENSOR_1_DDR] >
+				     fan_step_table[i].on[TEMP_SENSOR_1_DDR] &&
+			     temp[TEMP_SENSOR_3_CHARGER] >
+				     fan_step_table[i]
+					     .on[TEMP_SENSOR_3_CHARGER]) ||
+			    temp[TEMP_SENSOR_2_SOC] >
+				    fan_step_table[i].on[TEMP_SENSOR_2_SOC])
+				current_level = i + 1;
+			else
+				break;
+		}
+	}
+
+	if (current_level < 0)
+		current_level = 0;
+
+	for (i = 0; i < TEMP_SENSOR_COUNT; ++i)
+		prev_tmp[i] = temp[i];
+
+	ASSERT(current_level < NUM_FAN_LEVELS);
+
+	switch (fan) {
+	case FAN_CH_0:
+		new_rpm = fan_step_table[current_level].rpm[FAN_CH_0];
+		break;
+	case FAN_CH_1:
+		new_rpm = fan_step_table[current_level].rpm[FAN_CH_1];
+		break;
+	default:
+		break;
+	}
+
+	return new_rpm;
+}
+
+void board_override_fan_control(int fan, int *tmp)
+{
+	if (chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND)) {
+		fan_set_rpm_mode(FAN_CH(fan), 1);
+		fan_set_rpm_target(FAN_CH(fan), fan_table_to_rpm(fan, tmp));
+	}
+}
diff --git a/board/redrix/usbc_config.c b/board/redrix/usbc_config.c
new file mode 100644
index 0000000000..70e9a7dfd4
--- /dev/null
+++ b/board/redrix/usbc_config.c
@@ -0,0 +1,321 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/bc12/pi3usb9201_public.h"
+#include "driver/ppc/syv682x_public.h"
+#include "driver/retimer/bb_retimer_public.h"
+#include "driver/tcpm/nct38xx.h"
+#include "driver/tcpm/tcpci.h"
+#include "ec_commands.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "ioexpander.h"
+#include "system.h"
+#include "task.h"
+#include "task_id.h"
+#include "timer.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+/* USBC TCPC configuration */
+const struct tcpc_config_t tcpc_config[] = {
+	[USBC_PORT_C0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0_TCPC,
+			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+	},
+	[USBC_PORT_C1] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C1_TCPC,
+			.addr_flags = NCT38XX_I2C_ADDR1_4_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
+BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
+
+/* USBC PPC configuration */
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_PPC,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.frs_en = IOEX_USB_C0_FRS_EN,
+		.drv = &syv682x_drv,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C1_PPC,
+		.i2c_addr_flags = SYV682X_ADDR2_FLAGS,
+		.frs_en = IOEX_USB_C1_FRS_EN,
+		.drv = &syv682x_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
+
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/* USBC mux configuration - Alder Lake includes internal mux */
+static const struct usb_mux_chain usbc0_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+static const struct usb_mux_chain usbc1_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+
+const struct usb_mux_chain usb_muxes[] = {
+	[USBC_PORT_C0] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			/*
+			 * A USB-A adapter plugged into Type-C port
+			 * would increase BBR power consumption, so
+			 * clear USB3_Connection bit in S0ix and
+			 * re-enable in S0
+			 */
+			.flags = USB_MUX_FLAG_CAN_IDLE,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C0_MUX,
+			.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc0_tcss_usb_mux,
+	},
+	[USBC_PORT_C1] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.flags = USB_MUX_FLAG_CAN_IDLE,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C1_MUX,
+			.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc1_tcss_usb_mux,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
+
+/* BC1.2 charger detect configuration */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C1_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_1_FLAGS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
+
+/*
+ * USB C0 and C1 uses burnside bridge chips and have their reset
+ * controlled by their respective TCPC chips acting as GPIO expanders.
+ *
+ * ioex_init() is normally called before we take the TCPCs out of
+ * reset, so we need to start in disabled mode, then explicitly
+ * call ioex_init().
+ */
+
+struct ioexpander_config_t ioex_config[] = {
+	[IOEX_C0_NCT38XX] = {
+		.i2c_host_port = I2C_PORT_USB_C0_TCPC,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
+	},
+	[IOEX_C1_NCT38XX] = {
+		.i2c_host_port = I2C_PORT_USB_C1_TCPC,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR1_4_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT);
+
+__override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
+{
+	enum ioex_signal rst_signal;
+
+	if (me->usb_port == USBC_PORT_C0) {
+		rst_signal = IOEX_USB_C0_RT_RST_ODL;
+	} else if (me->usb_port == USBC_PORT_C1) {
+		rst_signal = IOEX_USB_C1_RT_RST_ODL;
+	} else {
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * We do not have a load switch for the burnside bridge chips,
+	 * so we only need to sequence reset.
+	 */
+
+	if (enable) {
+		/*
+		 * Tpw, minimum time from VCC to RESET_N de-assertion is 100us.
+		 * For boards that don't provide a load switch control, the
+		 * retimer_init() function ensures power is up before calling
+		 * this function.
+		 */
+		ioex_set_level(rst_signal, 1);
+		/*
+		 * Allow 1ms time for the retimer to power up lc_domain
+		 * which powers I2C controller within retimer
+		 */
+		msleep(1);
+	} else {
+		ioex_set_level(rst_signal, 0);
+		msleep(1);
+	}
+	return EC_SUCCESS;
+}
+
+void board_reset_pd_mcu(void)
+{
+	gpio_set_level(GPIO_USB_C0_TCPC_RST_ODL, 0);
+	gpio_set_level(GPIO_USB_C1_TCPC_RST_ODL, 0);
+
+	/*
+	 * delay for power-on to reset-off and min. assertion time
+	 */
+	msleep(NCT38XX_RESET_HOLD_DELAY_MS);
+
+	gpio_set_level(GPIO_USB_C0_TCPC_RST_ODL, 1);
+	gpio_set_level(GPIO_USB_C1_TCPC_RST_ODL, 1);
+
+	nct38xx_reset_notify(USBC_PORT_C0);
+	nct38xx_reset_notify(USBC_PORT_C1);
+
+	/* wait for chips to come up */
+	if (NCT3807_RESET_POST_DELAY_MS != 0)
+		msleep(NCT3807_RESET_POST_DELAY_MS);
+}
+
+static void board_tcpc_init(void)
+{
+	int i;
+
+	/* Don't reset TCPCs after initial reset */
+	if (!system_jumped_late())
+		board_reset_pd_mcu();
+
+	/*
+	 * These IO expander pins are implemented using the
+	 * C0/C1 TCPCs, so they must be set up after the TCPCs has
+	 * been taken out of reset.
+	 */
+	for (i = 0; i < CONFIG_IO_EXPANDER_PORT_COUNT; ++i)
+		ioex_init(i);
+
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
+
+	/* Enable BC1.2 interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_0;
+
+	if (gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
+
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C1);
+		break;
+	default:
+		break;
+	}
+}
+
+void bc12_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_BC12_INT_ODL:
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+		break;
+	case GPIO_USB_C1_BC12_INT_ODL:
+		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+		break;
+	default:
+		break;
+	}
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C1);
+		break;
+	default:
+		break;
+	}
+}
+
+void retimer_interrupt(enum gpio_signal signal)
+{
+	/*
+	 * TODO(b/179513527): add USB-C support
+	 */
+}
+
+__override bool board_is_dts_port(int port)
+{
+	return port == USBC_PORT_C0;
+}
diff --git a/board/redrix/usbc_config.h b/board/redrix/usbc_config.h
new file mode 100644
index 0000000000..248e697572
--- /dev/null
+++ b/board/redrix/usbc_config.h
@@ -0,0 +1,15 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Redrix board-specific USB-C configuration */
+
+#ifndef __CROS_EC_USBC_CONFIG_H
+#define __CROS_EC_USBC_CONFIG_H
+
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
+
+#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/redrix/vif_override.xml b/board/redrix/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/redrix/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/reef/battery.c b/board/reef/battery.c
index 83a3679b26..52ec2a0471 100644
--- a/board/reef/battery.c
+++ b/board/reef/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -20,7 +20,7 @@
 #include "i2c.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 enum battery_type {
 	BATTERY_SONY_CORP,
@@ -135,7 +135,7 @@ const struct battery_info batt_info_smp_cos4870 = {
 	 * unwanted low VSYS_Prochot# assertion can be avoided.
 	 */
 	.voltage_min = 6100,
-	.precharge_current = 256,	/* mA */
+	.precharge_current = 256, /* mA */
 	.start_charging_min_c = 0,
 	.start_charging_max_c = 46,
 	.charging_min_c = 0,
@@ -183,7 +183,7 @@ const struct battery_info batt_info_sonycorp = {
 	 * unwanted low VSYS_Prochot# assertion can be avoided.
 	 */
 	.voltage_min = 6100,
-	.precharge_current = 256,	/* mA */
+	.precharge_current = 256, /* mA */
 	.start_charging_min_c = 0,
 	.start_charging_max_c = 50,
 	.charging_min_c = 0,
@@ -240,7 +240,7 @@ const struct battery_info batt_info_panasoic = {
 	 * unwanted low VSYS_Prochot# assertion can be avoided.
 	 */
 	.voltage_min = 6100,
-	.precharge_current = 256,	/* mA */
+	.precharge_current = 256, /* mA */
 	.start_charging_min_c = 0,
 	.start_charging_max_c = 50,
 	.charging_min_c = 0,
@@ -384,7 +384,7 @@ const struct battery_info batt_info_c22n1626 = {
 	 * unwanted low VSYS_Prochot# assertion can be avoided.
 	 */
 	.voltage_min = 6100,
-	.precharge_current = 256,	/* mA */
+	.precharge_current = 256, /* mA */
 	.start_charging_min_c = 0,
 	.start_charging_max_c = 45,
 	.charging_min_c = 0,
@@ -398,7 +398,7 @@ static int batt_smp_cos4870_init(void)
 	int batt_status;
 
 	return battery_status(&batt_status) ? 0 :
-		batt_status & STATUS_INITIALIZED;
+					      batt_status & STATUS_INITIALIZED;
 }
 
 static int batt_sony_corp_init(void)
@@ -411,8 +411,9 @@ static int batt_sony_corp_init(void)
 	 *      : 0b - Allowed to Discharge
 	 *      : 1b - Not Allowed to Discharge
 	 */
-	return sb_read(SB_MANUFACTURER_ACCESS, &batt_status) ? 0 :
-		!(batt_status & SONY_DISCHARGE_DISABLE_FET_BIT);
+	return sb_read(SB_MANUFACTURER_ACCESS, &batt_status) ?
+		       0 :
+		       !(batt_status & SONY_DISCHARGE_DISABLE_FET_BIT);
 }
 
 static int batt_panasonic_init(void)
@@ -425,8 +426,9 @@ static int batt_panasonic_init(void)
 	 *      : 0b - Not Allowed to Discharge
 	 *      : 1b - Allowed to Discharge
 	 */
-	return sb_read(SB_MANUFACTURER_ACCESS, &batt_status) ? 0 :
-		!!(batt_status & PANASONIC_DISCHARGE_ENABLE_FET_BIT);
+	return sb_read(SB_MANUFACTURER_ACCESS, &batt_status) ?
+		       0 :
+		       !!(batt_status & PANASONIC_DISCHARGE_ENABLE_FET_BIT);
 }
 
 static int batt_c22n1626_init(void)
@@ -439,8 +441,9 @@ static int batt_c22n1626_init(void)
 	 *      : 0b - Not Allowed to Discharge
 	 *      : 1b - Allowed to Discharge
 	 */
-	return sb_read(SB_PACK_STATUS, &batt_status) ? 0 :
-		!!(batt_status & C22N1626_DISCHARGE_ENABLE_FET_BIT);
+	return sb_read(SB_PACK_STATUS, &batt_status) ?
+		       0 :
+		       !!(batt_status & C22N1626_DISCHARGE_ENABLE_FET_BIT);
 }
 
 static const struct ship_mode_info ship_mode_info_smp_cos4870 = {
@@ -461,7 +464,7 @@ static const struct ship_mode_info ship_mode_info_panasonic = {
 	.batt_init = batt_panasonic_init,
 };
 
-static const struct ship_mode_info ship_mode_info_c22n1626= {
+static const struct ship_mode_info ship_mode_info_c22n1626 = {
 	.ship_mode_reg = 0x00,
 	.ship_mode_data = 0x0010,
 	.batt_init = batt_c22n1626_init,
@@ -513,7 +516,8 @@ BUILD_ASSERT(ARRAY_SIZE(info) == BATTERY_TYPE_COUNT);
 static inline const struct board_batt_params *board_get_batt_params(void)
 {
 	return &info[board_battery_type == BATTERY_TYPE_COUNT ?
-			DEFAULT_BATTERY_TYPE : board_battery_type];
+			     DEFAULT_BATTERY_TYPE :
+			     board_battery_type];
 }
 
 enum battery_present battery_hw_present(void)
@@ -540,8 +544,9 @@ static int board_get_battery_type(void)
 
 	/* Initialize fast charging parameters */
 	chg_params = board_get_batt_params()->fast_chg_params;
-	prev_chg_profile_info = &chg_params->chg_profile_info[
-					chg_params->default_temp_range_profile];
+	prev_chg_profile_info =
+		&chg_params->chg_profile_info
+			 [chg_params->default_temp_range_profile];
 
 	return board_battery_type;
 }
@@ -571,11 +576,11 @@ int board_cut_off_battery(void)
 {
 	int rv;
 	const struct ship_mode_info *ship_mode_inf =
-				board_get_batt_params()->ship_mode_inf;
+		board_get_batt_params()->ship_mode_inf;
 
 	/* Ship mode command must be sent twice to take effect */
 	rv = sb_write(ship_mode_inf->ship_mode_reg,
-			ship_mode_inf->ship_mode_data);
+		      ship_mode_inf->ship_mode_data);
 	if (rv != EC_SUCCESS)
 		return rv;
 
@@ -591,7 +596,7 @@ static int charger_should_discharge_on_ac(struct charge_state_data *curr)
 
 	/* Do not discharge on AC if the battery is still waking up */
 	if (!(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
-		!(curr->batt.status & STATUS_FULLY_CHARGED))
+	    !(curr->batt.status & STATUS_FULLY_CHARGED))
 		return 0;
 
 	/*
@@ -608,8 +613,8 @@ static int charger_should_discharge_on_ac(struct charge_state_data *curr)
 	 * and suspend USB charging and DC/DC converter.
 	 */
 	if (!battery_is_cut_off() &&
-		!(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
-		(curr->batt.status & STATUS_FULLY_CHARGED))
+	    !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
+	    (curr->batt.status & STATUS_FULLY_CHARGED))
 		return 1;
 
 	/*
@@ -642,10 +647,10 @@ int charger_profile_override(struct charge_state_data *curr)
 		return 0;
 	}
 
-	return charger_profile_override_common(curr,
-			board_get_batt_params()->fast_chg_params,
-			&prev_chg_profile_info,
-			board_get_batt_params()->batt_info->voltage_max);
+	return charger_profile_override_common(
+		curr, board_get_batt_params()->fast_chg_params,
+		&prev_chg_profile_info,
+		board_get_batt_params()->batt_info->voltage_max);
 }
 
 /*
@@ -671,7 +676,7 @@ enum battery_present battery_is_present(void)
 	 * Battery status will be inactive until it is initialized.
 	 */
 	if (batt_pres == BP_YES && batt_pres_prev != batt_pres &&
-		!battery_is_cut_off()) {
+	    !battery_is_cut_off()) {
 		/* Re-init board battery if battery presence status changes */
 		if (board_get_battery_type() == BATTERY_TYPE_COUNT) {
 			if (bd9995x_get_battery_voltage() >=
diff --git a/board/reef/board.c b/board/reef/board.c
index e6856f3f55..71dadb6507 100644
--- a/board/reef/board.c
+++ b/board/reef/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,6 @@
 /* Reef board-specific configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "button.h"
 #include "charge_manager.h"
 #include "charge_ramp.h"
@@ -14,10 +13,10 @@
 #include "charger.h"
 #include "chipset.h"
 #include "console.h"
-#include "driver/als_opt3001.h"
 #include "driver/accel_kionix.h"
 #include "driver/accel_kx022.h"
 #include "driver/accelgyro_bmi_common.h"
+#include "driver/als_opt3001.h"
 #include "driver/baro_bmp280.h"
 #include "driver/charger/bd9995x.h"
 #include "driver/tcpm/anx74xx.h"
@@ -33,8 +32,9 @@
 #include "lid_angle.h"
 #include "lid_switch.h"
 #include "math_util.h"
-#include "motion_sense.h"
 #include "motion_lid.h"
+#include "motion_sense.h"
+#include "panic.h"
 #include "power.h"
 #include "power_button.h"
 #include "pwm.h"
@@ -45,7 +45,7 @@
 #include "tablet_mode.h"
 #include "task.h"
 #include "temp_sensor.h"
-#include "thermistor.h"
+#include "temp_sensor/thermistor.h"
 #include "timer.h"
 #include "uart.h"
 #include "usb_charge.h"
@@ -54,15 +54,15 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define IN_ALL_SYS_PG	POWER_SIGNAL_MASK(X86_ALL_SYS_PG)
-#define IN_PGOOD_PP3300	POWER_SIGNAL_MASK(X86_PGOOD_PP3300)
-#define IN_PGOOD_PP5000	POWER_SIGNAL_MASK(X86_PGOOD_PP5000)
+#define IN_ALL_SYS_PG POWER_SIGNAL_MASK(X86_ALL_SYS_PG)
+#define IN_PGOOD_PP3300 POWER_SIGNAL_MASK(X86_PGOOD_PP3300)
+#define IN_PGOOD_PP5000 POWER_SIGNAL_MASK(X86_PGOOD_PP5000)
 
-#define USB_PD_PORT_ANX74XX	0
-#define USB_PD_PORT_PS8751	1
+#define USB_PD_PORT_ANX74XX 0
+#define USB_PD_PORT_PS8751 1
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
@@ -98,7 +98,7 @@ static void anx74xx_cable_det_handler(void)
 	 * and if in normal mode, then there is no need to trigger a tcpc reset.
 	 */
 	if (cable_det && !reset_n)
-		task_set_event(TASK_ID_PD_C0, PD_EVENT_TCPC_RESET, 0);
+		task_set_event(TASK_ID_PD_C0, PD_EVENT_TCPC_RESET);
 }
 DECLARE_DEFERRED(anx74xx_cable_det_handler);
 
@@ -117,47 +117,59 @@ void anx74xx_cable_det_interrupt(enum gpio_signal signal)
 static void enable_input_devices(void);
 DECLARE_DEFERRED(enable_input_devices);
 
-#define LID_DEBOUNCE_US    (30 * MSEC)  /* Debounce time for lid switch */
 void tablet_mode_interrupt(enum gpio_signal signal)
 {
 	hook_call_deferred(&enable_input_devices_data, LID_DEBOUNCE_US);
 }
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* Vfs = Vref = 2.816V, 10-bit unsigned reading */
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0
-	},
-	[ADC_TEMP_SENSOR_AMB] = {
-		"AMBIENT", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0
-	},
-	[ADC_BOARD_ID] = {
-		"BRD_ID", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0
-	},
+	[ADC_TEMP_SENSOR_CHARGER] = { "CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				      ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_AMB] = { "AMBIENT", NPCX_ADC_CH1, ADC_MAX_VOLT,
+				  ADC_READ_MAX + 1, 0 },
+	[ADC_BOARD_ID] = { "BRD_ID", NPCX_ADC_CH2, ADC_MAX_VOLT,
+			   ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
 	[PWM_CH_LED_GREEN] = { 2, PWM_CONFIG_DSLEEP, 100 },
-	[PWM_CH_LED_RED] =   { 3, PWM_CONFIG_DSLEEP, 100 },
+	[PWM_CH_LED_RED] = { 3, PWM_CONFIG_DSLEEP, 100 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
-const struct i2c_port_t i2c_ports[]  = {
-	{"tcpc0",     NPCX_I2C_PORT0_0, 400,
-		GPIO_EC_I2C_USB_C0_PD_SCL, GPIO_EC_I2C_USB_C0_PD_SDA},
-	{"tcpc1",     NPCX_I2C_PORT0_1, 400,
-		GPIO_EC_I2C_USB_C1_PD_SCL, GPIO_EC_I2C_USB_C1_PD_SDA},
-	{"accelgyro", I2C_PORT_GYRO,   400,
-		GPIO_EC_I2C_GYRO_SCL,      GPIO_EC_I2C_GYRO_SDA},
-	{"sensors",   NPCX_I2C_PORT2,   400,
-		GPIO_EC_I2C_SENSOR_SCL,    GPIO_EC_I2C_SENSOR_SDA},
-	{"batt",      NPCX_I2C_PORT3,   100,
-		GPIO_EC_I2C_POWER_SCL,     GPIO_EC_I2C_POWER_SDA},
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "tcpc0",
+	  .port = NPCX_I2C_PORT0_0,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_USB_C0_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C0_PD_SDA },
+	{ .name = "tcpc1",
+	  .port = NPCX_I2C_PORT0_1,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_USB_C1_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C1_PD_SDA },
+	{ .name = "accelgyro",
+	  .port = I2C_PORT_GYRO,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_GYRO_SCL,
+	  .sda = GPIO_EC_I2C_GYRO_SDA },
+	{ .name = "sensors",
+	  .port = NPCX_I2C_PORT2,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_SENSOR_SCL,
+	  .sda = GPIO_EC_I2C_SENSOR_SDA },
+	{ .name = "batt",
+	  .port = NPCX_I2C_PORT3,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_POWER_SCL,
+	  .sda = GPIO_EC_I2C_POWER_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -176,7 +188,7 @@ struct i2c_stress_test i2c_stress_tests[] = {
 #ifdef CONFIG_CMD_I2C_STRESS_TEST_TCPC
 	{
 		.port = NPCX_I2C_PORT0_1,
-		.addr_flags = PS8751_I2C_ADDR1_FLAGS,
+		.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
 		.i2c_test = &ps8xxx_i2c_stress_test_dev,
 	},
 #endif
@@ -239,7 +251,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = NPCX_I2C_PORT0_1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
 		},
 		.drv = &ps8xxx_tcpm_drv,
 	},
@@ -285,17 +297,21 @@ static int ps8751_tune_mux(const struct usb_mux *me)
 	return EC_SUCCESS;
 }
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_ANX74XX] = {
-		.usb_port = USB_PD_PORT_ANX74XX,
-		.driver = &anx74xx_tcpm_usb_mux_driver,
-		.hpd_update = &anx74xx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_ANX74XX,
+			.driver = &anx74xx_tcpm_usb_mux_driver,
+			.hpd_update = &anx74xx_tcpc_update_hpd_status,
+		},
 	},
 	[USB_PD_PORT_PS8751] = {
-		.usb_port = USB_PD_PORT_PS8751,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-		.board_init = &ps8751_tune_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_PS8751,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			.board_init = &ps8751_tune_mux,
+		},
 	}
 };
 
@@ -390,27 +406,28 @@ void board_tcpc_init(void)
 	gpio_enable_interrupt(GPIO_USB_C0_CABLE_DET);
 #endif
 	/*
-	* Initialize HPD to low; after sysjump SOC needs to see
-	* HPD pulse to enable video path
-	*/
+	 * Initialize HPD to low; after sysjump SOC needs to see
+	 * HPD pulse to enable video path
+	 */
 	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		usb_mux_hpd_update(port, 0, 0);
+		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp,
-				 .idx = 0},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
+	[TEMP_SENSOR_BATTERY] = { .name = "Battery",
+				  .type = TEMP_SENSOR_TYPE_BATTERY,
+				  .read = charge_get_battery_temp,
+				  .idx = 0 },
+	[TEMP_SENSOR_AMBIENT] = { .name = "Ambient",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_51k1_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_AMB },
+	[TEMP_SENSOR_CHARGER] = { .name = "Charger",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_13k7_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_CHARGER },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -445,7 +462,8 @@ void chipset_pre_init_callback(void)
 
 static void board_set_tablet_mode(void)
 {
-	tablet_set_mode(!gpio_get_level(GPIO_TABLET_MODE_L));
+	tablet_set_mode(!gpio_get_level(GPIO_TABLET_MODE_L),
+			TABLET_TRIGGER_LID);
 }
 
 /* Initialize board. */
@@ -526,8 +544,8 @@ int board_set_active_charge_port(int charge_port)
  * @param charge_ma     Desired charge limit (mA).
  * @param charge_mv     Negotiated charge voltage (mV).
  */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
 {
 	/* Enable charging trigger by BC1.2 detection */
 	int bc12_enable = (supplier == CHARGE_SUPPLIER_BC12_CDP ||
@@ -538,9 +556,7 @@ void board_set_charge_limit(int port, int supplier, int charge_ma,
 	if (bd9995x_bc12_enable_charging(port, bc12_enable))
 		return;
 
-	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-				   CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+	charge_set_input_current_limit(charge_ma, charge_mv);
 }
 
 /**
@@ -571,8 +587,7 @@ static void enable_input_devices(void)
 }
 
 /* Enable or disable input devices, based on chipset state and tablet mode */
-#ifndef TEST_BUILD
-void lid_angle_peripheral_enable(int enable)
+__override void lid_angle_peripheral_enable(int enable)
 {
 	/* If the lid is in 360 position, ignore the lid angle,
 	 * which might be faulty. Disable keyboard.
@@ -581,7 +596,6 @@ void lid_angle_peripheral_enable(int enable)
 		enable = 0;
 	keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
 }
-#endif
 
 /* Called on AP S5 -> S3 transition */
 static void board_chipset_startup(void)
@@ -652,17 +666,17 @@ void board_hibernate_late(void)
 	int i;
 	const uint32_t hibernate_pins[][2] = {
 		/* Turn off LEDs in hibernate */
-		{GPIO_BAT_LED_BLUE, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_BAT_LED_AMBER, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_LID_OPEN, GPIO_INT_RISING | GPIO_PULL_DOWN},
+		{ GPIO_BAT_LED_BLUE, GPIO_INPUT | GPIO_PULL_UP },
+		{ GPIO_BAT_LED_AMBER, GPIO_INPUT | GPIO_PULL_UP },
+		{ GPIO_LID_OPEN, GPIO_INT_RISING | GPIO_PULL_DOWN },
 
 		/*
 		 * BD99956 handles charge input automatically. We'll disable
 		 * charge output in hibernate. Charger will assert ACOK_OD
 		 * when VBUS or VCC are plugged in.
 		 */
-		{GPIO_USB_C0_5V_EN,       GPIO_INPUT  | GPIO_PULL_DOWN},
-		{GPIO_USB_C1_5V_EN,       GPIO_INPUT  | GPIO_PULL_DOWN},
+		{ GPIO_USB_C0_5V_EN, GPIO_INPUT | GPIO_PULL_DOWN },
+		{ GPIO_USB_C1_5V_EN, GPIO_INPUT | GPIO_PULL_DOWN },
 	};
 
 	/* Change GPIOs' state in hibernate for better power consumption */
@@ -689,17 +703,13 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0,  0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+				       { FLOAT_TO_FP(1), 0, 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
 
-const mat33_fp_t mag_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0,  FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t mag_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				      { 0, FLOAT_TO_FP(1), 0 },
+				      { 0, 0, FLOAT_TO_FP(-1) } };
 
 /* sensor private data */
 static struct kionix_accel_data g_kx022_data;
@@ -799,7 +809,10 @@ struct motion_sensor_t motion_sensors[] = {
 	 .default_range = BIT(11), /* 16LSB / uT, fixed */
 	 .rot_standard_ref = &mag_standard_ref,
 	 .min_frequency = BMM150_MAG_MIN_FREQ,
+/* TODO(b/253292373): Remove when clang is fixed. */
+DISABLE_CLANG_WARNING("-Wshift-count-negative")
 	 .max_frequency = BMM150_MAG_MAX_FREQ(SPECIAL),
+ENABLE_CLANG_WARNING("-Wshift-count-negative")
 	},
 	[BASE_BARO] = {
 	 .name = "Base Baro",
@@ -867,8 +880,8 @@ struct {
 	int thresh_mv;
 } const reef_board_versions[] = {
 	/* Vin = 3.3V, R1 = 46.4K, R2 values listed below */
-	{ BOARD_VERSION_1, 328 * 1.03 },  /* 5.11 Kohm */
-	{ BOARD_VERSION_2, 670 * 1.03 },  /* 11.8 Kohm */
+	{ BOARD_VERSION_1, 328 * 1.03 }, /* 5.11 Kohm */
+	{ BOARD_VERSION_2, 670 * 1.03 }, /* 11.8 Kohm */
 	{ BOARD_VERSION_3, 1012 * 1.03 }, /* 20.5 Kohm */
 	{ BOARD_VERSION_4, 1357 * 1.03 }, /* 32.4 Kohm */
 	{ BOARD_VERSION_5, 1690 * 1.03 }, /* 48.7 Kohm */
@@ -913,7 +926,7 @@ int board_get_version(void)
 }
 
 /* Keyboard scan setting */
-struct keyboard_scan_config keyscan_config = {
+__override struct keyboard_scan_config keyscan_config = {
 	/*
 	 * F3 key scan cycle completed but scan input is not
 	 * charging to logic high when EC start scan next
diff --git a/board/reef/board.h b/board/reef/board.h
index 8b38811024..b5bdd574a8 100644
--- a/board/reef/board.h
+++ b/board/reef/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,24 +12,23 @@
  * By default, enable all console messages excepted HC, ACPI and event:
  * The sensor stack is generating a lot of activity.
  */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
 #undef CONFIG_HOSTCMD_DEBUG_MODE
 #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
 
-
 /* EC console commands  */
 #define CONFIG_CMD_ACCELS
 #define CONFIG_CMD_ACCEL_INFO
 #define CONFIG_CMD_BATT_MFG_ACCESS
 #define CONFIG_CMD_CHARGER_ADC_AMON_BMON
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 #define BD9995X_IOUT_GAIN_SELECT \
-		BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V
+	BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V
 
 #define CONFIG_CHARGER_PSYS_READ
 #define BD9995X_PSYS_GAIN_SELECT \
-		BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_02UAW
+	BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_02UAW
 
 #define CONFIG_CMD_I2C_STRESS_TEST
 #define CONFIG_CMD_I2C_STRESS_TEST_ACCEL
@@ -39,7 +38,7 @@
 #define CONFIG_CMD_I2C_STRESS_TEST_TCPC
 
 /* Battery */
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY  "LION"
+#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
 #define CONFIG_BATTERY_CUT_OFF
 #define CONFIG_BATTERY_PRESENT_CUSTOM
 #define CONFIG_BATTERY_SMART
@@ -51,15 +50,19 @@
 #define CONFIG_CHARGER_BD9995X
 #define CONFIG_CHARGER_BD9995X_CHGEN
 #define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT 512
+#define CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT 512
+#define CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT 512
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 5
 #define CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT 1
 #define CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW 18000
 #define CONFIG_CHARGER_MAINTAIN_VBAT
+#undef CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON
 #define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 1
 #define CONFIG_USB_CHARGER
 #define CONFIG_CHARGER_PROFILE_OVERRIDE
 #define CONFIG_CHARGER_PROFILE_OVERRIDE_COMMON
-#undef  CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES
+#undef CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES
 #define CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES 3
 #define CONFIG_CHARGE_MANAGER_EXTERNAL_POWER_LIMIT
 
@@ -86,7 +89,7 @@
 #define CONFIG_USB_PD_PORT_MAX_COUNT 2
 #define CONFIG_USB_PD_VBUS_DETECT_CHARGER
 #define CONFIG_USB_PD_TCPC_LOW_POWER
-#define CONFIG_USB_PD_TCPM_MUX  /* for both PS8751 and ANX3429 */
+#define CONFIG_USB_PD_TCPM_MUX /* for both PS8751 and ANX3429 */
 #define CONFIG_USB_PD_TCPM_ANX3429
 #define CONFIG_USB_PD_TCPM_PS8751
 #define CONFIG_USB_PD_TCPM_TCPCI
@@ -101,7 +104,7 @@
 #define CONFIG_USBC_VCONN_SWAP
 
 /* SoC / PCH */
-#define CONFIG_HOSTCMD_LPC
+#define CONFIG_HOST_INTERFACE_LPC
 #define CONFIG_CHIPSET_APOLLOLAKE
 #define CONFIG_CHIPSET_RESET_HOOK
 #define CONFIG_POWER_BUTTON
@@ -109,18 +112,18 @@
 #define CONFIG_POWER_COMMON
 #define CONFIG_POWER_S0IX
 #define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
+#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD
 
 /* EC */
 #define CONFIG_ADC
-#define CONFIG_BOARD_VERSION_CUSTOM
 #define CONFIG_EXTPOWER_GPIO
-#undef   CONFIG_EXTPOWER_DEBOUNCE_MS
-#define  CONFIG_EXTPOWER_DEBOUNCE_MS 1000
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
+#define CONFIG_EXTPOWER_DEBOUNCE_MS 1000
 #define CONFIG_FPU
 #define CONFIG_HOSTCMD_FLASH_SPI_INFO
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
-#define CONFIG_KEYBOARD_BOARD_CONFIG
+#define CONFIG_I2C_CONTROLLER
+
 #define CONFIG_KEYBOARD_PROTOCOL_8042
 #define CONFIG_KEYBOARD_COL2_INVERTED
 #define CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2
@@ -144,7 +147,7 @@
 #define CONFIG_WIRELESS
 #define CONFIG_WIRELESS_SUSPEND EC_WIRELESS_SWITCH_WLAN_POWER
 #define CONFIG_WLAN_POWER_ACTIVE_LOW
-#define  WIRELESS_GPIO_WLAN_POWER GPIO_WIRELESS_GPIO_WLAN_POWER
+#define WIRELESS_GPIO_WLAN_POWER GPIO_WIRELESS_GPIO_WLAN_POWER
 #define CONFIG_PWR_STATE_DISCHARGE_FULL
 #undef CONFIG_UART_TX_BUF_SIZE
 #define CONFIG_UART_TX_BUF_SIZE 512
@@ -162,9 +165,9 @@
 #undef CONFIG_MOTION_SENSE_SUSPEND_DELAY_US
 #define CONFIG_MOTION_SENSE_SUSPEND_DELAY_US (MSEC * 60)
 
-#define CONFIG_FLASH_SIZE 524288
+#define CONFIG_FLASH_SIZE_BYTES 524288
 #define CONFIG_SPI_FLASH_REGS
-#define CONFIG_SPI_FLASH_W25Q40	/* FIXME: Should be GD25LQ40? */
+#define CONFIG_SPI_FLASH_W25Q40 /* FIXME: Should be GD25LQ40? */
 
 /*
  * Enable 1 slot of secure temporary storage to support
@@ -174,27 +177,26 @@
 #define CONFIG_VSTORE_SLOT_COUNT 1
 
 /* Optional feature - used by nuvoton */
-#define NPCX_UART_MODULE2    1 /* 0:GPIO10/11 1:GPIO64/65 as UART */
-#define NPCX_JTAG_MODULE2    0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/
+#define NPCX_UART_MODULE2 1 /* 0:GPIO10/11 1:GPIO64/65 as UART */
+#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/
 /* FIXME(dhendrix): these pins are just normal GPIOs on Reef. Do we need
  * to change some other setting to put them in GPIO mode? */
-#define NPCX_TACH_SEL2       0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
+#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
 
 /* I2C ports */
-#define I2C_PORT_GYRO			NPCX_I2C_PORT1
-#define I2C_PORT_LID_ACCEL		NPCX_I2C_PORT2
-#define I2C_PORT_ALS			NPCX_I2C_PORT2
-#define I2C_PORT_BARO			NPCX_I2C_PORT2
-#define I2C_PORT_BATTERY		NPCX_I2C_PORT3
-#define I2C_PORT_CHARGER		NPCX_I2C_PORT3
+#define I2C_PORT_GYRO NPCX_I2C_PORT1
+#define I2C_PORT_LID_ACCEL NPCX_I2C_PORT2
+#define I2C_PORT_ALS NPCX_I2C_PORT2
+#define I2C_PORT_BARO NPCX_I2C_PORT2
+#define I2C_PORT_BATTERY NPCX_I2C_PORT3
+#define I2C_PORT_CHARGER NPCX_I2C_PORT3
 /* Accelerometer and Gyroscope are the same device. */
-#define I2C_PORT_ACCEL			I2C_PORT_GYRO
+#define I2C_PORT_ACCEL I2C_PORT_GYRO
 
 /* Sensors */
 #define CONFIG_MKBP_EVENT
 #define CONFIG_MKBP_USE_HOST_EVENT
 #define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCEL_INTERRUPTS
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 #define CONFIG_MAG_BMI_BMM150
@@ -215,7 +217,6 @@
 /* Depends on how fast the AP boots and typical ODRs */
 #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
 
-
 #ifndef __ASSEMBLER__
 
 #include "gpio_signal.h"
@@ -223,9 +224,9 @@
 
 /* ADC signal */
 enum adc_channel {
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC0 */
-	ADC_TEMP_SENSOR_AMB,		/* ADC1 */
-	ADC_BOARD_ID,			/* ADC2 */
+	ADC_TEMP_SENSOR_CHARGER, /* ADC0 */
+	ADC_TEMP_SENSOR_AMB, /* ADC1 */
+	ADC_BOARD_ID, /* ADC2 */
 	ADC_CH_COUNT
 };
 
@@ -286,17 +287,16 @@ enum reef_board_version {
  * delay to turn on the power supply max is ~16ms.
  * delay to turn off the power supply max is about ~180ms.
  */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* delay to turn on/off vconn */
-#define PD_VCONN_SWAP_DELAY 5000 /* us */
 
 /* Define typical operating power and max power */
 #define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       45000
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_VOLTAGE_MV     20000
+#define PD_MAX_POWER_MW 45000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Reset PD MCU */
 void board_reset_pd_mcu(void);
diff --git a/board/reef/build.mk b/board/reef/build.mk
index 728d027803..470e439b13 100644
--- a/board/reef/build.mk
+++ b/board/reef/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/reef/ec.tasklist b/board/reef/ec.tasklist
index eeebc0cc59..bc8668a1db 100644
--- a/board/reef/ec.tasklist
+++ b/board/reef/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/reef/gpio.inc b/board/reef/gpio.inc
index 2b6a5342f4..3f66a9903a 100644
--- a/board/reef/gpio.inc
+++ b/board/reef/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -67,7 +67,8 @@ GPIO(EC_I2C_POWER_SCL,		PIN(D, 1), GPIO_INPUT)
  * Pin 57 (SER_IRQ) defaults to LPC mode, but we also have EC_PCH_KB_INT_ODL
  * (Pin B0) in case it doesn't work (Set CONFIG_KEYBOARD_IRQ_GPIO in this case).
  *
- * See also the NO_LPC_ESPI bit in DEVALT1 and the CONFIG_HOSTCMD_SPS option.
+ * See also the NO_LPC_ESPI bit in DEVALT1 and the
+ * CONFIG_HOST_INTERFACE_SHI option.
  */
 
 GPIO(PCH_SMI_L,			PIN(A, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V)	/* EC_SMI_ODL */
@@ -163,8 +164,8 @@ ALTERNATE(PIN_MASK(0, 0xe0), 0,  MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
 ALTERNATE(PIN_MASK(1, 0x7f), 0,  MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
 GPIO(KBD_KSO2,			 PIN(1, 7), GPIO_KB_OUTPUT_COL2)
 
-ALTERNATE(PIN(4, 4), 6, MODULE_ADC, 0)		/* TEMP_SENSOR_AMB (FIXME: alt function 6?) */
-ALTERNATE(PIN(4, 5), 6, MODULE_ADC, 0)		/* TEMP_SENSOR_CHARGER (FIXME: alt function?) */
+/* GPIO44 for TEMP_SENSOR_AMB and GPIO45 for TEMP_SENSOR_CHARGER */
+ALTERNATE(PIN_MASK(4, 0x30), 0, MODULE_ADC, 0)
 
 ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, 0)	/* GPIO87 for EC_I2C_GYRO_SDA */
 ALTERNATE(PIN_MASK(9, 0x01), 1, MODULE_I2C, 0)	/* GPIO90 for EC_I2C_GYRO_SCL */
diff --git a/board/reef/led.c b/board/reef/led.c
index 807b1c109c..0f9685c15c 100644
--- a/board/reef/led.c
+++ b/board/reef/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -27,8 +27,7 @@
 #define LED_ON_1SEC_TICKS 1
 #define LED_ON_2SECS_TICKS 2
 
-const enum ec_led_id supported_led_ids[] = {
-			EC_LED_ID_BATTERY_LED};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -36,7 +35,7 @@ enum led_color {
 	LED_OFF = 0,
 	LED_BLUE,
 	LED_AMBER,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static int led_set_color_battery(enum led_color color)
@@ -96,43 +95,47 @@ static void led_set_battery(void)
 	static int battery_ticks;
 	static int suspend_ticks;
 
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
 		led_set_color_battery(LED_AMBER);
 		break;
-	case PWR_STATE_DISCHARGE_FULL:
+	case LED_PWRS_DISCHARGE_FULL:
 		if (extpower_is_present()) {
 			led_set_color_battery(LED_BLUE);
 			break;
 		}
-		/* Intentional fall-through */
-	case PWR_STATE_DISCHARGE /* and PWR_STATE_DISCHARGE_FULL */:
+		__fallthrough;
+	case LED_PWRS_DISCHARGE /* and LED_PWRS_DISCHARGE_FULL */:
 		if (chipset_in_state(CHIPSET_STATE_ON)) {
 			led_set_color_battery(LED_BLUE);
 		} else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
 			/* Blink once every four seconds. */
 			led_set_color_battery(
-				(suspend_ticks % LED_TOTAL_4SECS_TICKS)
-				< LED_ON_1SEC_TICKS ? LED_AMBER : LED_OFF);
+				(suspend_ticks % LED_TOTAL_4SECS_TICKS) <
+						LED_ON_1SEC_TICKS ?
+					LED_AMBER :
+					LED_OFF);
 		} else {
 			led_set_color_battery(LED_OFF);
 		}
 		break;
-	case PWR_STATE_ERROR:
-		led_set_color_battery(
-			(battery_ticks % LED_TOTAL_2SECS_TICKS <
-			 LED_ON_1SEC_TICKS) ? LED_AMBER : LED_OFF);
+	case LED_PWRS_ERROR:
+		led_set_color_battery((battery_ticks % LED_TOTAL_2SECS_TICKS <
+				       LED_ON_1SEC_TICKS) ?
+					      LED_AMBER :
+					      LED_OFF);
 		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
+	case LED_PWRS_CHARGE_NEAR_FULL:
 		led_set_color_battery(LED_BLUE);
 		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (charge_get_flags() & CHARGE_FLAG_FORCE_IDLE)
-			led_set_color_battery(
-				(battery_ticks % LED_TOTAL_4SECS_TICKS <
-				 LED_ON_2SECS_TICKS) ? LED_AMBER : LED_BLUE);
-		else
-			led_set_color_battery(LED_BLUE);
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		led_set_color_battery(LED_BLUE);
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		led_set_color_battery((battery_ticks % LED_TOTAL_4SECS_TICKS <
+				       LED_ON_2SECS_TICKS) ?
+					      LED_AMBER :
+					      LED_BLUE);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
diff --git a/board/reef/usb_pd_policy.c b/board/reef/usb_pd_policy.c
index 2d2ef416b2..5990dd9e75 100644
--- a/board/reef/usb_pd_policy.c
+++ b/board/reef/usb_pd_policy.c
@@ -1,16 +1,16 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "atomic.h"
-#include "extpower.h"
 #include "charge_manager.h"
 #include "common.h"
 #include "console.h"
 #include "driver/charger/bd9995x.h"
 #include "driver/tcpm/anx74xx.h"
 #include "driver/tcpm/ps8xxx.h"
+#include "extpower.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "host_command.h"
@@ -18,17 +18,17 @@
 #include "system.h"
 #include "task.h"
 #include "timer.h"
-#include "util.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
+#include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT];
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5,
-							TYPEC_RP_1A5};
+static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5,
+							 TYPEC_RP_1A5 };
 
 int board_vbus_source_enabled(int port)
 {
@@ -39,7 +39,8 @@ static void board_vbus_update_source_current(int port)
 {
 	enum gpio_signal gpio = port ? GPIO_USB_C1_5V_EN : GPIO_USB_C0_5V_EN;
 	int flags = (vbus_rp[port] == TYPEC_RP_1A5 && vbus_en[port]) ?
-		(GPIO_INPUT | GPIO_PULL_UP) : (GPIO_OUTPUT | GPIO_PULL_UP);
+			    (GPIO_INPUT | GPIO_PULL_UP) :
+			    (GPIO_OUTPUT | GPIO_PULL_UP);
 
 	/*
 	 * Driving USB_Cx_5V_EN high, actually put a 16.5k resistance
diff --git a/board/reef/vif_override.xml b/board/reef/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/reef/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/reef_it8320/battery.c b/board/reef_it8320/battery.c
index 1b16a672b2..f03000f3c7 100644
--- a/board/reef_it8320/battery.c
+++ b/board/reef_it8320/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -20,7 +20,7 @@
 #include "i2c.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 enum battery_type {
 	BATTERY_SONY_CORP,
@@ -135,7 +135,7 @@ const struct battery_info batt_info_smp_cos4870 = {
 	 * unwanted low VSYS_Prochot# assertion can be avoided.
 	 */
 	.voltage_min = 6100,
-	.precharge_current = 256,	/* mA */
+	.precharge_current = 256, /* mA */
 	.start_charging_min_c = 0,
 	.start_charging_max_c = 46,
 	.charging_min_c = 0,
@@ -183,7 +183,7 @@ const struct battery_info batt_info_sonycorp = {
 	 * unwanted low VSYS_Prochot# assertion can be avoided.
 	 */
 	.voltage_min = 6100,
-	.precharge_current = 256,	/* mA */
+	.precharge_current = 256, /* mA */
 	.start_charging_min_c = 0,
 	.start_charging_max_c = 50,
 	.charging_min_c = 0,
@@ -240,7 +240,7 @@ const struct battery_info batt_info_panasoic = {
 	 * unwanted low VSYS_Prochot# assertion can be avoided.
 	 */
 	.voltage_min = 6100,
-	.precharge_current = 256,	/* mA */
+	.precharge_current = 256, /* mA */
 	.start_charging_min_c = 0,
 	.start_charging_max_c = 50,
 	.charging_min_c = 0,
@@ -384,7 +384,7 @@ const struct battery_info batt_info_c22n1626 = {
 	 * unwanted low VSYS_Prochot# assertion can be avoided.
 	 */
 	.voltage_min = 6100,
-	.precharge_current = 256,	/* mA */
+	.precharge_current = 256, /* mA */
 	.start_charging_min_c = 0,
 	.start_charging_max_c = 45,
 	.charging_min_c = 0,
@@ -398,7 +398,7 @@ static int batt_smp_cos4870_init(void)
 	int batt_status;
 
 	return battery_status(&batt_status) ? 0 :
-		batt_status & STATUS_INITIALIZED;
+					      batt_status & STATUS_INITIALIZED;
 }
 
 static int batt_sony_corp_init(void)
@@ -411,8 +411,9 @@ static int batt_sony_corp_init(void)
 	 *      : 0b - Allowed to Discharge
 	 *      : 1b - Not Allowed to Discharge
 	 */
-	return sb_read(SB_MANUFACTURER_ACCESS, &batt_status) ? 0 :
-		!(batt_status & SONY_DISCHARGE_DISABLE_FET_BIT);
+	return sb_read(SB_MANUFACTURER_ACCESS, &batt_status) ?
+		       0 :
+		       !(batt_status & SONY_DISCHARGE_DISABLE_FET_BIT);
 }
 
 static int batt_panasonic_init(void)
@@ -425,8 +426,9 @@ static int batt_panasonic_init(void)
 	 *      : 0b - Not Allowed to Discharge
 	 *      : 1b - Allowed to Discharge
 	 */
-	return sb_read(SB_MANUFACTURER_ACCESS, &batt_status) ? 0 :
-		!!(batt_status & PANASONIC_DISCHARGE_ENABLE_FET_BIT);
+	return sb_read(SB_MANUFACTURER_ACCESS, &batt_status) ?
+		       0 :
+		       !!(batt_status & PANASONIC_DISCHARGE_ENABLE_FET_BIT);
 }
 
 static int batt_c22n1626_init(void)
@@ -439,8 +441,9 @@ static int batt_c22n1626_init(void)
 	 *      : 0b - Not Allowed to Discharge
 	 *      : 1b - Allowed to Discharge
 	 */
-	return sb_read(SB_PACK_STATUS, &batt_status) ? 0 :
-		!!(batt_status & C22N1626_DISCHARGE_ENABLE_FET_BIT);
+	return sb_read(SB_PACK_STATUS, &batt_status) ?
+		       0 :
+		       !!(batt_status & C22N1626_DISCHARGE_ENABLE_FET_BIT);
 }
 
 static const struct ship_mode_info ship_mode_info_smp_cos4870 = {
@@ -513,7 +516,8 @@ BUILD_ASSERT(ARRAY_SIZE(info) == BATTERY_TYPE_COUNT);
 static inline const struct board_batt_params *board_get_batt_params(void)
 {
 	return &info[board_battery_type == BATTERY_TYPE_COUNT ?
-			DEFAULT_BATTERY_TYPE : board_battery_type];
+			     DEFAULT_BATTERY_TYPE :
+			     board_battery_type];
 }
 
 enum battery_present battery_hw_present(void)
@@ -540,8 +544,9 @@ static int board_get_battery_type(void)
 
 	/* Initialize fast charging parameters */
 	chg_params = board_get_batt_params()->fast_chg_params;
-	prev_chg_profile_info = &chg_params->chg_profile_info[
-					chg_params->default_temp_range_profile];
+	prev_chg_profile_info =
+		&chg_params->chg_profile_info
+			 [chg_params->default_temp_range_profile];
 
 	return board_battery_type;
 }
@@ -571,11 +576,11 @@ int board_cut_off_battery(void)
 {
 	int rv;
 	const struct ship_mode_info *ship_mode_inf =
-				board_get_batt_params()->ship_mode_inf;
+		board_get_batt_params()->ship_mode_inf;
 
 	/* Ship mode command must be sent twice to take effect */
 	rv = sb_write(ship_mode_inf->ship_mode_reg,
-			ship_mode_inf->ship_mode_data);
+		      ship_mode_inf->ship_mode_data);
 	if (rv != EC_SUCCESS)
 		return rv;
 
@@ -591,7 +596,7 @@ static int charger_should_discharge_on_ac(struct charge_state_data *curr)
 
 	/* Do not discharge on AC if the battery is still waking up */
 	if (!(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
-		!(curr->batt.status & STATUS_FULLY_CHARGED))
+	    !(curr->batt.status & STATUS_FULLY_CHARGED))
 		return 0;
 
 	/*
@@ -608,8 +613,8 @@ static int charger_should_discharge_on_ac(struct charge_state_data *curr)
 	 * and suspend USB charging and DC/DC converter.
 	 */
 	if (!battery_is_cut_off() &&
-		!(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
-		(curr->batt.status & STATUS_FULLY_CHARGED))
+	    !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
+	    (curr->batt.status & STATUS_FULLY_CHARGED))
 		return 1;
 
 	/*
@@ -642,10 +647,10 @@ int charger_profile_override(struct charge_state_data *curr)
 		return 0;
 	}
 
-	return charger_profile_override_common(curr,
-			board_get_batt_params()->fast_chg_params,
-			&prev_chg_profile_info,
-			board_get_batt_params()->batt_info->voltage_max);
+	return charger_profile_override_common(
+		curr, board_get_batt_params()->fast_chg_params,
+		&prev_chg_profile_info,
+		board_get_batt_params()->batt_info->voltage_max);
 }
 
 /*
@@ -671,7 +676,7 @@ enum battery_present battery_is_present(void)
 	 * Battery status will be inactive until it is initialized.
 	 */
 	if (batt_pres == BP_YES && batt_pres_prev != batt_pres &&
-		!battery_is_cut_off()) {
+	    !battery_is_cut_off()) {
 		/* Re-init board battery if battery presence status changes */
 		if (board_get_battery_type() == BATTERY_TYPE_COUNT) {
 			if (bd9995x_get_battery_voltage() >=
diff --git a/board/reef_it8320/board.c b/board/reef_it8320/board.c
index e45174e9e1..5901c1a821 100644
--- a/board/reef_it8320/board.c
+++ b/board/reef_it8320/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,6 @@
 /* reef_it8320 board-specific configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "button.h"
 #include "charge_manager.h"
 #include "charge_ramp.h"
@@ -28,8 +27,9 @@
 #include "lid_angle.h"
 #include "lid_switch.h"
 #include "math_util.h"
-#include "motion_sense.h"
 #include "motion_lid.h"
+#include "motion_sense.h"
+#include "panic.h"
 #include "power.h"
 #include "power_button.h"
 #include "pwm.h"
@@ -40,7 +40,7 @@
 #include "tablet_mode.h"
 #include "task.h"
 #include "temp_sensor.h"
-#include "thermistor.h"
+#include "temp_sensor/thermistor.h"
 #include "timer.h"
 #include "uart.h"
 #include "usb_charge.h"
@@ -49,40 +49,41 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define IN_ALL_SYS_PG	POWER_SIGNAL_MASK(X86_ALL_SYS_PG)
-#define IN_PGOOD_PP3300	POWER_SIGNAL_MASK(X86_PGOOD_PP3300)
-#define IN_PGOOD_PP5000	POWER_SIGNAL_MASK(X86_PGOOD_PP5000)
+#define IN_ALL_SYS_PG POWER_SIGNAL_MASK(X86_ALL_SYS_PG)
+#define IN_PGOOD_PP3300 POWER_SIGNAL_MASK(X86_PGOOD_PP3300)
+#define IN_PGOOD_PP5000 POWER_SIGNAL_MASK(X86_PGOOD_PP5000)
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 const struct adc_t adc_channels[] = {
 	/* Convert to mV (3000mV/1024). */
-	{"CHARGER",     3000, 1024, 0, CHIP_ADC_CH1}, /* GPI1 */
-	{"AMBIENT",     3000, 1024, 0, CHIP_ADC_CH2}, /* GPI2 */
-	{"BRD_ID",      3000, 1024, 0, CHIP_ADC_CH3}, /* GPI3 */
+	{ "CHARGER", 3000, 1024, 0, CHIP_ADC_CH1 }, /* GPI1 */
+	{ "AMBIENT", 3000, 1024, 0, CHIP_ADC_CH2 }, /* GPI2 */
+	{ "BRD_ID", 3000, 1024, 0, CHIP_ADC_CH3 }, /* GPI3 */
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
-const struct i2c_port_t i2c_ports[]  = {
-	{"mux",       IT83XX_I2C_CH_C, 400,
-		GPIO_EC_I2C_C_SCL, GPIO_EC_I2C_C_SDA},
-	{"batt",      IT83XX_I2C_CH_E, 100,
-		GPIO_EC_I2C_E_SCL, GPIO_EC_I2C_E_SDA},
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "mux",
+	  .port = IT83XX_I2C_CH_C,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_C_SCL,
+	  .sda = GPIO_EC_I2C_C_SDA },
+	{ .name = "batt",
+	  .port = IT83XX_I2C_CH_E,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_E_SCL,
+	  .sda = GPIO_EC_I2C_E_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
 const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_EMBEDDED,
-		.drv = &it83xx_tcpm_drv
-	},
-	{
-		.bus_type = EC_BUS_TYPE_EMBEDDED,
-		.drv = &it83xx_tcpm_drv
-	},
+	{ .bus_type = EC_BUS_TYPE_EMBEDDED, .drv = &it83xx_tcpm_drv },
+	{ .bus_type = EC_BUS_TYPE_EMBEDDED, .drv = &it83xx_tcpm_drv },
 };
 
 void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
@@ -112,11 +113,16 @@ const enum gpio_signal hibernate_wake_pins[] = {
 const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 
 static void it83xx_tcpc_update_hpd_status(const struct usb_mux *me,
-					  int hpd_lvl, int hpd_irq)
+					  mux_state_t mux_state,
+					  bool *ack_required)
 {
-	enum gpio_signal gpio =
-		me->usb_port ? GPIO_USB_C1_HPD_1P8_ODL
-			     : GPIO_USB_C0_HPD_1P8_ODL;
+	int hpd_lvl = (mux_state & USB_PD_MUX_HPD_LVL) ? 1 : 0;
+	int hpd_irq = (mux_state & USB_PD_MUX_HPD_IRQ) ? 1 : 0;
+	enum gpio_signal gpio = me->usb_port ? GPIO_USB_C1_HPD_1P8_ODL :
+					       GPIO_USB_C0_HPD_1P8_ODL;
+
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
 
 	hpd_lvl = !hpd_lvl;
 
@@ -128,20 +134,26 @@ static void it83xx_tcpc_update_hpd_status(const struct usb_mux *me,
 	}
 }
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
-		.driver = &pi3usb3x532_usb_mux_driver,
-		.hpd_update = &it83xx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX,
+				.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
+				.driver = &pi3usb3x532_usb_mux_driver,
+				.hpd_update = &it83xx_tcpc_update_hpd_status,
+			},
 	},
 	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = 0x10,
-		.driver = &ps8740_usb_mux_driver,
-		.hpd_update = &it83xx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_USB_MUX,
+				.i2c_addr_flags = 0x10,
+				.driver = &ps8740_usb_mux_driver,
+				.hpd_update = &it83xx_tcpc_update_hpd_status,
+			},
 	},
 };
 
@@ -150,18 +162,18 @@ const int usb_port_enable[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT] = {
 };
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp,
-				 .idx = 0},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
+	[TEMP_SENSOR_BATTERY] = { .name = "Battery",
+				  .type = TEMP_SENSOR_TYPE_BATTERY,
+				  .read = charge_get_battery_temp,
+				  .idx = 0 },
+	[TEMP_SENSOR_AMBIENT] = { .name = "Ambient",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_51k1_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_AMB },
+	[TEMP_SENSOR_CHARGER] = { .name = "Charger",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_13k7_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_CHARGER },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -208,7 +220,7 @@ static void board_set_tablet_mode(void)
 	 * Always report device isn't in tablet mode because
 	 * our id is clamshell and no TABLET_MODE_L pin
 	 */
-	tablet_set_mode(0);
+	tablet_set_mode(0, TABLET_TRIGGER_LID);
 }
 
 /* Initialize board. */
@@ -219,11 +231,12 @@ static void board_init(void)
 	gpio_enable_interrupt(GPIO_CHARGER_INT_L);
 
 	/*
-	* Initialize HPD to low; after sysjump SOC needs to see
-	* HPD pulse to enable video path
-	*/
+	 * Initialize HPD to low; after sysjump SOC needs to see
+	 * HPD pulse to enable video path
+	 */
 	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		usb_mux_hpd_update(port, 0, 0);
+		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_INIT_I2C + 1);
 
@@ -287,8 +300,8 @@ int board_set_active_charge_port(int charge_port)
  * @param charge_ma     Desired charge limit (mA).
  * @param charge_mv     Negotiated charge voltage (mV).
  */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
 {
 	/* Enable charging trigger by BC1.2 detection */
 	int bc12_enable = (supplier == CHARGE_SUPPLIER_BC12_CDP ||
@@ -299,9 +312,7 @@ void board_set_charge_limit(int port, int supplier, int charge_ma,
 	if (bd9995x_bc12_enable_charging(port, bc12_enable))
 		return;
 
-	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-				   CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+	charge_set_input_current_limit(charge_ma, charge_mv);
 }
 
 /**
@@ -380,22 +391,27 @@ void chipset_do_shutdown(void)
 		;
 }
 
+void board_reset_pd_mcu(void)
+{
+	/* do nothing */
+}
+
 void board_hibernate_late(void)
 {
 	int i;
 	const uint32_t hibernate_pins[][2] = {
 		/* Turn off LEDs in hibernate */
-		{GPIO_BAT_LED_BLUE, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_BAT_LED_AMBER, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_LID_OPEN, GPIO_INT_RISING | GPIO_PULL_DOWN},
+		{ GPIO_BAT_LED_BLUE, GPIO_INPUT | GPIO_PULL_UP },
+		{ GPIO_BAT_LED_AMBER, GPIO_INPUT | GPIO_PULL_UP },
+		{ GPIO_LID_OPEN, GPIO_INT_RISING | GPIO_PULL_DOWN },
 
 		/*
 		 * BD99956 handles charge input automatically. We'll disable
 		 * charge output in hibernate. Charger will assert ACOK_OD
 		 * when VBUS or VCC are plugged in.
 		 */
-		{GPIO_USB_C0_5V_EN,       GPIO_INPUT  | GPIO_PULL_DOWN},
-		{GPIO_USB_C1_5V_EN,       GPIO_INPUT  | GPIO_PULL_DOWN},
+		{ GPIO_USB_C0_5V_EN, GPIO_INPUT | GPIO_PULL_DOWN },
+		{ GPIO_USB_C1_5V_EN, GPIO_INPUT | GPIO_PULL_DOWN },
 	};
 
 	/* Change GPIOs' state in hibernate for better power consumption */
@@ -426,8 +442,8 @@ struct {
 	int thresh_mv;
 } const reef_it8320_board_versions[] = {
 	/* Vin = 3.3V, R1 = 46.4K, R2 values listed below */
-	{ BOARD_VERSION_1, 328 * 1.03 },  /* 5.11 Kohm */
-	{ BOARD_VERSION_2, 670 * 1.03 },  /* 11.8 Kohm */
+	{ BOARD_VERSION_1, 328 * 1.03 }, /* 5.11 Kohm */
+	{ BOARD_VERSION_2, 670 * 1.03 }, /* 11.8 Kohm */
 	{ BOARD_VERSION_3, 1012 * 1.03 }, /* 20.5 Kohm */
 	{ BOARD_VERSION_4, 1357 * 1.03 }, /* 32.4 Kohm */
 	{ BOARD_VERSION_5, 1690 * 1.03 }, /* 48.7 Kohm */
@@ -472,7 +488,7 @@ int board_get_version(void)
 }
 
 /* Keyboard scan setting */
-struct keyboard_scan_config keyscan_config = {
+__override struct keyboard_scan_config keyscan_config = {
 	/*
 	 * F3 key scan cycle completed but scan input is not
 	 * charging to logic high when EC start scan next
diff --git a/board/reef_it8320/board.h b/board/reef_it8320/board.h
index fb26e2ff57..87767e5c23 100644
--- a/board/reef_it8320/board.h
+++ b/board/reef_it8320/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,24 +19,24 @@
  * By default, enable all console messages excepted HC, ACPI and event:
  * The sensor stack is generating a lot of activity.
  */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
 #undef CONFIG_HOSTCMD_DEBUG_MODE
 #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
 
 /* EC console commands  */
 #define CONFIG_CMD_BATT_MFG_ACCESS
 #define CONFIG_CMD_CHARGER_ADC_AMON_BMON
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 #define BD9995X_IOUT_GAIN_SELECT \
-		BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V
+	BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V
 
 #define CONFIG_CHARGER_PSYS_READ
 #define BD9995X_PSYS_GAIN_SELECT \
-		BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_02UAW
+	BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_02UAW
 
 /* Battery */
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY  "LION"
+#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
 #define CONFIG_BATTERY_CUT_OFF
 #define CONFIG_BATTERY_PRESENT_CUSTOM
 #define CONFIG_BATTERY_SMART
@@ -48,15 +48,19 @@
 #define CONFIG_CHARGER_BD9995X
 #define CONFIG_CHARGER_BD9995X_CHGEN
 #define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT 512
+#define CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT 512
+#define CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT 512
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 5
 #define CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT 1
 #define CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW 18000
 #define CONFIG_CHARGER_MAINTAIN_VBAT
+#undef CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON
 #define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 1
 #define CONFIG_USB_CHARGER
 #define CONFIG_CHARGER_PROFILE_OVERRIDE
 #define CONFIG_CHARGER_PROFILE_OVERRIDE_COMMON
-#undef  CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES
+#undef CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES
 #define CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES 3
 #define CONFIG_CHARGE_MANAGER_EXTERNAL_POWER_LIMIT
 
@@ -78,7 +82,6 @@
 #define CONFIG_USB_PD_DUAL_ROLE
 #define CONFIG_USB_PD_DISCHARGE_GPIO
 #define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT TYPEC_RP_3A0
 #define CONFIG_USB_PD_PORT_MAX_COUNT 2
 #define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 2
 #define CONFIG_USB_PD_VBUS_DETECT_CHARGER
@@ -89,7 +92,7 @@
 #define CONFIG_USB_PD_TCPMV2
 #define CONFIG_USB_DRP_ACC_TRYSRC
 #define CONFIG_USB_PD_REV30
-#define CONFIG_USB_PID 0x1234            /* Invalid PID for development board */
+#define CONFIG_USB_PID 0x1234 /* Invalid PID for development board */
 #define CONFIG_USB_PD_DECODE_SOP
 #define CONFIG_USB_PD_DEBUG_LEVEL 2
 #define CONFIG_USB_PD_COMM_LOCKED
@@ -99,7 +102,7 @@
 #define CONFIG_USBC_VCONN_SWAP
 
 /* SoC / PCH */
-#define CONFIG_HOSTCMD_LPC
+#define CONFIG_HOST_INTERFACE_LPC
 #define CONFIG_CHIPSET_APOLLOLAKE
 #define CONFIG_CHIPSET_RESET_HOOK
 #define CONFIG_POWER_BUTTON
@@ -107,16 +110,17 @@
 #define CONFIG_POWER_COMMON
 #define CONFIG_POWER_S0IX
 #define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
+#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD
 
 /* EC */
 #define CONFIG_ADC
-#define CONFIG_BOARD_VERSION_CUSTOM
 #define CONFIG_EXTPOWER_GPIO
-#undef  CONFIG_EXTPOWER_DEBOUNCE_MS
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
 #define CONFIG_EXTPOWER_DEBOUNCE_MS 1000
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
-#define CONFIG_KEYBOARD_BOARD_CONFIG
+#define CONFIG_I2C_CONTROLLER
+#define CONFIG_IT83XX_VCC_3P3V
+
 #define CONFIG_KEYBOARD_PROTOCOL_8042
 #define CONFIG_KEYBOARD_COL2_INVERTED
 #define CONFIG_LED_COMMON
@@ -161,15 +165,15 @@
 #include "registers.h"
 
 /* I2C ports */
-#define I2C_PORT_USB_MUX		IT83XX_I2C_CH_C
-#define I2C_PORT_BATTERY		IT83XX_I2C_CH_E
-#define I2C_PORT_CHARGER		IT83XX_I2C_CH_E
+#define I2C_PORT_USB_MUX IT83XX_I2C_CH_C
+#define I2C_PORT_BATTERY IT83XX_I2C_CH_E
+#define I2C_PORT_CHARGER IT83XX_I2C_CH_E
 
 /* ADC signal */
 enum adc_channel {
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC CH1 */
-	ADC_TEMP_SENSOR_AMB,		/* ADC CH2 */
-	ADC_BOARD_ID,			/* ADC CH3 */
+	ADC_TEMP_SENSOR_CHARGER, /* ADC CH1 */
+	ADC_TEMP_SENSOR_AMB, /* ADC CH2 */
+	ADC_BOARD_ID, /* ADC CH3 */
 	ADC_CH_COUNT
 };
 
@@ -199,17 +203,16 @@ enum reef_it8320_board_version {
  * delay to turn on the power supply max is ~16ms.
  * delay to turn off the power supply max is about ~180ms.
  */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* delay to turn on/off vconn */
-#define PD_VCONN_SWAP_DELAY 5000 /* us */
 
 /* Define typical operating power and max power */
 #define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       45000
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_VOLTAGE_MV     20000
+#define PD_MAX_POWER_MW 45000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Reset PD MCU */
 void board_reset_pd_mcu(void);
diff --git a/board/reef_it8320/build.mk b/board/reef_it8320/build.mk
index e5c12f9090..0c2fcec14f 100644
--- a/board/reef_it8320/build.mk
+++ b/board/reef_it8320/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/reef_it8320/ec.tasklist b/board/reef_it8320/ec.tasklist
index fdaf792a17..7faf124d53 100644
--- a/board/reef_it8320/ec.tasklist
+++ b/board/reef_it8320/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/reef_it8320/gpio.inc b/board/reef_it8320/gpio.inc
index 9882065d50..54528d3818 100644
--- a/board/reef_it8320/gpio.inc
+++ b/board/reef_it8320/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,7 +20,7 @@ GPIO_INT(PCH_SLP_S0_L,		PIN(B, 7), GPIO_INT_BOTH, power_signal_interrupt)				/*
 #endif
 GPIO_INT(SUSPWRDNACK,		PIN(E, 1), GPIO_INT_BOTH, power_signal_interrupt)	/* SUSPWRNACK */
 GPIO_INT(LID_OPEN,		PIN(E, 2), GPIO_INT_BOTH, lid_interrupt)		/* LID_OPEN */
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
 GPIO_INT(PCH_PLTRST_L,   	PIN(E, 3), GPIO_INT_BOTH | GPIO_PULL_UP,  lpcrst_interrupt)	/* PLT_RST_L */
 #endif
 GPIO_INT(POWER_BUTTON_L,	PIN(E, 4), GPIO_INT_BOTH, power_button_interrupt)	/* MECH_PWR_BTN_ODL */
diff --git a/board/reef_it8320/led.c b/board/reef_it8320/led.c
index a1ea5964a8..6f250c83e3 100644
--- a/board/reef_it8320/led.c
+++ b/board/reef_it8320/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -27,8 +27,7 @@
 #define LED_ON_1SEC_TICKS 1
 #define LED_ON_2SECS_TICKS 2
 
-const enum ec_led_id supported_led_ids[] = {
-			EC_LED_ID_BATTERY_LED};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -36,7 +35,7 @@ enum led_color {
 	LED_OFF = 0,
 	LED_BLUE,
 	LED_AMBER,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static int led_set_color_battery(enum led_color color)
@@ -97,43 +96,47 @@ static void led_set_battery(void)
 	static int battery_ticks;
 	static int suspend_ticks;
 
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
 		led_set_color_battery(LED_AMBER);
 		break;
-	case PWR_STATE_DISCHARGE_FULL:
+	case LED_PWRS_DISCHARGE_FULL:
 		if (extpower_is_present()) {
 			led_set_color_battery(LED_BLUE);
 			break;
 		}
-		/* Intentional fall-through */
-	case PWR_STATE_DISCHARGE /* and PWR_STATE_DISCHARGE_FULL */:
+		__fallthrough;
+	case LED_PWRS_DISCHARGE /* and LED_PWRS_DISCHARGE_FULL */:
 		if (chipset_in_state(CHIPSET_STATE_ON)) {
 			led_set_color_battery(LED_BLUE);
 		} else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
 			/* Blink once every four seconds. */
 			led_set_color_battery(
-				(suspend_ticks % LED_TOTAL_4SECS_TICKS)
-				< LED_ON_1SEC_TICKS ? LED_AMBER : LED_OFF);
+				(suspend_ticks % LED_TOTAL_4SECS_TICKS) <
+						LED_ON_1SEC_TICKS ?
+					LED_AMBER :
+					LED_OFF);
 		} else {
 			led_set_color_battery(LED_OFF);
 		}
 		break;
-	case PWR_STATE_ERROR:
-		led_set_color_battery(
-			(battery_ticks % LED_TOTAL_2SECS_TICKS <
-			 LED_ON_1SEC_TICKS) ? LED_AMBER : LED_OFF);
+	case LED_PWRS_ERROR:
+		led_set_color_battery((battery_ticks % LED_TOTAL_2SECS_TICKS <
+				       LED_ON_1SEC_TICKS) ?
+					      LED_AMBER :
+					      LED_OFF);
 		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
+	case LED_PWRS_CHARGE_NEAR_FULL:
 		led_set_color_battery(LED_BLUE);
 		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (charge_get_flags() & CHARGE_FLAG_FORCE_IDLE)
-			led_set_color_battery(
-				(battery_ticks % LED_TOTAL_4SECS_TICKS <
-				 LED_ON_2SECS_TICKS) ? LED_AMBER : LED_BLUE);
-		else
-			led_set_color_battery(LED_BLUE);
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		led_set_color_battery(LED_BLUE);
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		led_set_color_battery((battery_ticks % LED_TOTAL_4SECS_TICKS <
+				       LED_ON_2SECS_TICKS) ?
+					      LED_AMBER :
+					      LED_BLUE);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
diff --git a/board/reef_it8320/usb_pd_policy.c b/board/reef_it8320/usb_pd_policy.c
index 87b9c8d42e..bf29197906 100644
--- a/board/reef_it8320/usb_pd_policy.c
+++ b/board/reef_it8320/usb_pd_policy.c
@@ -1,16 +1,16 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "atomic.h"
-#include "extpower.h"
 #include "charge_manager.h"
 #include "common.h"
 #include "console.h"
 #include "driver/charger/bd9995x.h"
 #include "driver/tcpm/anx74xx.h"
 #include "driver/tcpm/ps8xxx.h"
+#include "extpower.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "host_command.h"
@@ -18,17 +18,17 @@
 #include "system.h"
 #include "task.h"
 #include "timer.h"
-#include "util.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
+#include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT];
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5,
-							TYPEC_RP_1A5};
+static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5,
+							 TYPEC_RP_1A5 };
 
 int board_vbus_source_enabled(int port)
 {
@@ -39,7 +39,7 @@ static void board_vbus_update_source_current(int port)
 {
 	enum gpio_signal gpio = port ? GPIO_USB_C1_5V_EN : GPIO_USB_C0_5V_EN;
 	enum gpio_signal gpio_3a_en = port ? GPIO_EN_USB_C1_3A :
-		GPIO_EN_USB_C0_3A;
+					     GPIO_EN_USB_C0_3A;
 
 	gpio_set_level(gpio_3a_en, vbus_rp[port] == TYPEC_RP_3A0 ? 1 : 0);
 	gpio_set_level(gpio, vbus_en[port]);
@@ -58,9 +58,6 @@ int pd_set_power_supply_ready(int port)
 	/* Ensure we're not charging from this port */
 	bd9995x_select_input_port(port, 0);
 
-	/* Ensure we advertise the proper available current quota */
-	charge_manager_source_port(port, 1);
-
 	pd_set_vbus_discharge(port, 0);
 	/* Provide VBUS */
 	vbus_en[port] = 1;
@@ -86,9 +83,6 @@ void pd_power_supply_reset(int port)
 	if (prev_en)
 		pd_set_vbus_discharge(port, 1);
 
-	/* Give back the current quota we are no longer using */
-	charge_manager_source_port(port, 0);
-
 	/* notify host of power info change */
 	pd_send_host_event(PD_EVENT_POWER_CHANGE);
 }
diff --git a/board/reef_it8320/vif_override.xml b/board/reef_it8320/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/reef_it8320/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/reef_mchp/battery.c b/board/reef_mchp/battery.c
index c557533c9d..d4a8aa7546 100644
--- a/board/reef_mchp/battery.c
+++ b/board/reef_mchp/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -18,11 +18,11 @@
 #include "gpio.h"
 #include "hooks.h"
 #include "i2c.h"
-#include "util.h"
 #include "tfdp_chip.h"
+#include "util.h"
 
 #define CPUTS(outstr) cputs(CC_CHARGER, outstr)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 enum battery_type {
 	BATTERY_SONY_CORP,
@@ -137,7 +137,7 @@ const struct battery_info batt_info_smp_cos4870 = {
 	 * unwanted low VSYS_Prochot# assertion can be avoided.
 	 */
 	.voltage_min = 6100,
-	.precharge_current = 256,	/* mA */
+	.precharge_current = 256, /* mA */
 	.start_charging_min_c = 0,
 	.start_charging_max_c = 46,
 	.charging_min_c = 0,
@@ -185,7 +185,7 @@ const struct battery_info batt_info_sonycorp = {
 	 * unwanted low VSYS_Prochot# assertion can be avoided.
 	 */
 	.voltage_min = 6100,
-	.precharge_current = 256,	/* mA */
+	.precharge_current = 256, /* mA */
 	.start_charging_min_c = 0,
 	.start_charging_max_c = 50,
 	.charging_min_c = 0,
@@ -242,7 +242,7 @@ const struct battery_info batt_info_panasoic = {
 	 * unwanted low VSYS_Prochot# assertion can be avoided.
 	 */
 	.voltage_min = 6100,
-	.precharge_current = 256,	/* mA */
+	.precharge_current = 256, /* mA */
 	.start_charging_min_c = 0,
 	.start_charging_max_c = 50,
 	.charging_min_c = 0,
@@ -386,7 +386,7 @@ const struct battery_info batt_info_c22n1626 = {
 	 * unwanted low VSYS_Prochot# assertion can be avoided.
 	 */
 	.voltage_min = 6100,
-	.precharge_current = 256,	/* mA */
+	.precharge_current = 256, /* mA */
 	.start_charging_min_c = 0,
 	.start_charging_max_c = 45,
 	.charging_min_c = 0,
@@ -400,7 +400,7 @@ static int batt_smp_cos4870_init(void)
 	int batt_status;
 
 	return battery_status(&batt_status) ? 0 :
-		batt_status & STATUS_INITIALIZED;
+					      batt_status & STATUS_INITIALIZED;
 }
 
 static int batt_sony_corp_init(void)
@@ -413,8 +413,9 @@ static int batt_sony_corp_init(void)
 	 *      : 0b - Allowed to Discharge
 	 *      : 1b - Not Allowed to Discharge
 	 */
-	return sb_read(SB_MANUFACTURER_ACCESS, &batt_status) ? 0 :
-		!(batt_status & SONY_DISCHARGE_DISABLE_FET_BIT);
+	return sb_read(SB_MANUFACTURER_ACCESS, &batt_status) ?
+		       0 :
+		       !(batt_status & SONY_DISCHARGE_DISABLE_FET_BIT);
 }
 
 static int batt_panasonic_init(void)
@@ -427,8 +428,9 @@ static int batt_panasonic_init(void)
 	 *      : 0b - Not Allowed to Discharge
 	 *      : 1b - Allowed to Discharge
 	 */
-	return sb_read(SB_MANUFACTURER_ACCESS, &batt_status) ? 0 :
-		!!(batt_status & PANASONIC_DISCHARGE_ENABLE_FET_BIT);
+	return sb_read(SB_MANUFACTURER_ACCESS, &batt_status) ?
+		       0 :
+		       !!(batt_status & PANASONIC_DISCHARGE_ENABLE_FET_BIT);
 }
 
 static int batt_c22n1626_init(void)
@@ -441,8 +443,9 @@ static int batt_c22n1626_init(void)
 	 *      : 0b - Not Allowed to Discharge
 	 *      : 1b - Allowed to Discharge
 	 */
-	return sb_read(SB_PACK_STATUS, &batt_status) ? 0 :
-		!!(batt_status & C22N1626_DISCHARGE_ENABLE_FET_BIT);
+	return sb_read(SB_PACK_STATUS, &batt_status) ?
+		       0 :
+		       !!(batt_status & C22N1626_DISCHARGE_ENABLE_FET_BIT);
 }
 
 static const struct ship_mode_info ship_mode_info_smp_cos4870 = {
@@ -515,7 +518,8 @@ BUILD_ASSERT(ARRAY_SIZE(info) == BATTERY_TYPE_COUNT);
 static inline const struct board_batt_params *board_get_batt_params(void)
 {
 	return &info[board_battery_type == BATTERY_TYPE_COUNT ?
-			DEFAULT_BATTERY_TYPE : board_battery_type];
+			     DEFAULT_BATTERY_TYPE :
+			     board_battery_type];
 }
 
 enum battery_present battery_hw_present(void)
@@ -545,8 +549,9 @@ static int board_get_battery_type(void)
 
 	/* Initialize fast charging parameters */
 	chg_params = board_get_batt_params()->fast_chg_params;
-	prev_chg_profile_info = &chg_params->chg_profile_info[
-			chg_params->default_temp_range_profile];
+	prev_chg_profile_info =
+		&chg_params->chg_profile_info
+			 [chg_params->default_temp_range_profile];
 
 	return board_battery_type;
 }
@@ -561,8 +566,7 @@ static int board_get_battery_type(void)
 static void board_init_battery_type(void)
 {
 	if (board_get_battery_type() != BATTERY_TYPE_COUNT)
-		CPRINTS("found batt:%s",
-			info[board_battery_type].manuf_name);
+		CPRINTS("found batt:%s", info[board_battery_type].manuf_name);
 	else
 		CPUTS("battery not found");
 }
@@ -577,16 +581,16 @@ int board_cut_off_battery(void)
 {
 	int rv;
 	const struct ship_mode_info *ship_mode_inf =
-				board_get_batt_params()->ship_mode_inf;
+		board_get_batt_params()->ship_mode_inf;
 
 	/* Ship mode command must be sent twice to take effect */
 	rv = sb_write(ship_mode_inf->ship_mode_reg,
-			ship_mode_inf->ship_mode_data);
+		      ship_mode_inf->ship_mode_data);
 	if (rv != EC_SUCCESS)
 		return rv;
 
 	rv = sb_write(ship_mode_inf->ship_mode_reg,
-			ship_mode_inf->ship_mode_data);
+		      ship_mode_inf->ship_mode_data);
 
 	return rv;
 }
@@ -599,7 +603,7 @@ static int charger_should_discharge_on_ac(struct charge_state_data *curr)
 
 	/* Do not discharge on AC if the battery is still waking up */
 	if (!(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
-			!(curr->batt.status & STATUS_FULLY_CHARGED))
+	    !(curr->batt.status & STATUS_FULLY_CHARGED))
 		return 0;
 
 	/*
@@ -616,8 +620,8 @@ static int charger_should_discharge_on_ac(struct charge_state_data *curr)
 	 * and suspend USB charging and DC/DC converter.
 	 */
 	if (!battery_is_cut_off() &&
-		!(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
-			(curr->batt.status & STATUS_FULLY_CHARGED))
+	    !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
+	    (curr->batt.status & STATUS_FULLY_CHARGED))
 		return 1;
 
 	/*
@@ -650,10 +654,10 @@ int charger_profile_override(struct charge_state_data *curr)
 		return 0;
 	}
 
-	return charger_profile_override_common(curr,
-			board_get_batt_params()->fast_chg_params,
-			&prev_chg_profile_info,
-			board_get_batt_params()->batt_info->voltage_max);
+	return charger_profile_override_common(
+		curr, board_get_batt_params()->fast_chg_params,
+		&prev_chg_profile_info,
+		board_get_batt_params()->batt_info->voltage_max);
 }
 
 /*
@@ -679,7 +683,7 @@ enum battery_present battery_is_present(void)
 	 * Battery status will be inactive until it is initialized.
 	 */
 	if (batt_pres == BP_YES && batt_pres_prev != batt_pres &&
-		!battery_is_cut_off()) {
+	    !battery_is_cut_off()) {
 		/* Re-init board battery if battery presence status changes */
 		if (board_get_battery_type() == BATTERY_TYPE_COUNT) {
 			if (bd9995x_get_battery_voltage() >=
diff --git a/board/reef_mchp/board.c b/board/reef_mchp/board.c
index 621f6c484b..70b75d4b72 100644
--- a/board/reef_mchp/board.c
+++ b/board/reef_mchp/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,6 @@
 /* Reef board-specific configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "als.h"
 #include "button.h"
 #include "charge_manager.h"
@@ -15,10 +14,10 @@
 #include "charger.h"
 #include "chipset.h"
 #include "console.h"
-#include "driver/als_opt3001.h"
 #include "driver/accel_kionix.h"
 #include "driver/accel_kx022.h"
 #include "driver/accelgyro_bmi_common.h"
+#include "driver/als_opt3001.h"
 #include "driver/baro_bmp280.h"
 #include "driver/charger/bd9995x.h"
 #include "driver/tcpm/anx74xx.h"
@@ -33,14 +32,15 @@
 #include "keyboard_scan.h"
 #include "lid_angle.h"
 #include "lid_switch.h"
+#include "lpc_chip.h"
 #include "math_util.h"
-#include "motion_sense.h"
 #include "motion_lid.h"
+#include "motion_sense.h"
+#include "panic.h"
 #include "power.h"
 #include "power_button.h"
 #include "pwm.h"
 #include "pwm_chip.h"
-#include "lpc_chip.h"
 #include "spi.h"
 #include "spi_chip.h"
 #include "switch.h"
@@ -48,8 +48,8 @@
 #include "tablet_mode.h"
 #include "task.h"
 #include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
 #include "tfdp_chip.h"
-#include "thermistor.h"
 #include "timer.h"
 #include "uart.h"
 #include "usb_charge.h"
@@ -58,17 +58,16 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-
 #define CPUTS(outstr) cputs(CC_USBCHARGE, outstr)
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define IN_ALL_SYS_PG	POWER_SIGNAL_MASK(X86_ALL_SYS_PG)
-#define IN_PGOOD_PP3300	POWER_SIGNAL_MASK(X86_PGOOD_PP3300)
-#define IN_PGOOD_PP5000	POWER_SIGNAL_MASK(X86_PGOOD_PP5000)
+#define IN_ALL_SYS_PG POWER_SIGNAL_MASK(X86_ALL_SYS_PG)
+#define IN_PGOOD_PP3300 POWER_SIGNAL_MASK(X86_PGOOD_PP3300)
+#define IN_PGOOD_PP5000 POWER_SIGNAL_MASK(X86_PGOOD_PP5000)
 
-#define USB_PD_PORT_ANX74XX	0
-#define USB_PD_PORT_PS8751	1
+#define USB_PD_PORT_ANX74XX 0
+#define USB_PD_PORT_PS8751 1
 
 #ifdef CONFIG_BOARD_PRE_INIT
 /*
@@ -132,7 +131,7 @@ static void anx74xx_cable_det_handler(void)
 	 * and if in normal mode, then there is no need to trigger a tcpc reset.
 	 */
 	if (cable_det && !reset_n)
-		task_set_event(TASK_ID_PD_C0, PD_EVENT_TCPC_RESET, 0);
+		task_set_event(TASK_ID_PD_C0, PD_EVENT_TCPC_RESET);
 }
 DECLARE_DEFERRED(anx74xx_cable_det_handler);
 /* from firmware-reef-9042.B */
@@ -153,17 +152,17 @@ void anx74xx_cable_det_interrupt(enum gpio_signal signal)
 static void enable_input_devices(void);
 DECLARE_DEFERRED(enable_input_devices);
 
-#define LID_DEBOUNCE_US    (30 * MSEC)  /* Debounce time for lid switch */
 void tablet_mode_interrupt(enum gpio_signal signal)
 {
 	hook_call_deferred(&enable_input_devices_data, LID_DEBOUNCE_US);
 }
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /* SPI devices */
 const struct spi_device_t spi_devices[] = {
-	{ QMSPI0_PORT, 4, GPIO_QMSPI_CS0},
+	{ QMSPI0_PORT, 4, GPIO_QMSPI_CS0 },
 #if defined(CONFIG_SPI_ACCEL_PORT)
 	{ GPSPI0_PORT, 2, GPIO_SPI0_CS0 },
 #endif
@@ -177,15 +176,9 @@ const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
  */
 const struct adc_t adc_channels[] = {
 	/* Vref = 3.000V, 10-bit unsigned reading */
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"CHARGER", 3000, 1024, 0, 0
-	},
-	[ADC_TEMP_SENSOR_AMB] = {
-		"AMBIENT", 3000, 1024, 0, 1
-	},
-	[ADC_BOARD_ID] = {
-		"BRD_ID", 3000, 1024, 0, 2
-	},
+	[ADC_TEMP_SENSOR_CHARGER] = { "CHARGER", 3000, 1024, 0, 0 },
+	[ADC_TEMP_SENSOR_AMB] = { "AMBIENT", 3000, 1024, 0, 1 },
+	[ADC_BOARD_ID] = { "BRD_ID", 3000, 1024, 0, 2 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
@@ -194,7 +187,7 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 const struct pwm_t pwm_channels[] = {
 	/* channel, flags */
 	[PWM_CH_LED_GREEN] = { 4, PWM_CONFIG_DSLEEP },
-	[PWM_CH_LED_RED] =   { 5, PWM_CONFIG_DSLEEP },
+	[PWM_CH_LED_RED] = { 5, PWM_CONFIG_DSLEEP },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 #endif /* #ifdef CONFIG_PWM */
@@ -205,17 +198,32 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
  * Due to added RC of interposer board temporarily reduce
  * 400 to 100 kHz.
  */
-const struct i2c_port_t i2c_ports[]  = {
-	{"tcpc0",     MCHP_I2C_PORT0, 400,
-		GPIO_EC_I2C_USB_C0_PD_SCL, GPIO_EC_I2C_USB_C0_PD_SDA},
-	{"tcpc1",     MCHP_I2C_PORT2, 400,
-		GPIO_EC_I2C_USB_C1_PD_SCL, GPIO_EC_I2C_USB_C1_PD_SDA},
-	{"accelgyro", I2C_PORT_GYRO, 400,
-		GPIO_EC_I2C_GYRO_SCL,      GPIO_EC_I2C_GYRO_SDA},
-	{"sensors",   MCHP_I2C_PORT7, 400,
-		GPIO_EC_I2C_SENSOR_SCL,    GPIO_EC_I2C_SENSOR_SDA},
-	{"batt",      MCHP_I2C_PORT3, 100,
-		GPIO_EC_I2C_POWER_SCL,     GPIO_EC_I2C_POWER_SDA},
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "tcpc0",
+	  .port = MCHP_I2C_PORT0,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_USB_C0_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C0_PD_SDA },
+	{ .name = "tcpc1",
+	  .port = MCHP_I2C_PORT2,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_USB_C1_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C1_PD_SDA },
+	{ .name = "accelgyro",
+	  .port = I2C_PORT_GYRO,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_GYRO_SCL,
+	  .sda = GPIO_EC_I2C_GYRO_SDA },
+	{ .name = "sensors",
+	  .port = MCHP_I2C_PORT7,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_SENSOR_SCL,
+	  .sda = GPIO_EC_I2C_SENSOR_SDA },
+	{ .name = "batt",
+	  .port = MCHP_I2C_PORT3,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_POWER_SCL,
+	  .sda = GPIO_EC_I2C_POWER_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -232,16 +240,6 @@ const uint16_t i2c_port_to_ctrl[I2C_PORT_COUNT] = {
 	(MCHP_I2C_CTRL3 << 8) + MCHP_I2C_PORT7,
 };
 
-/*
- * Used by chip level I2C controller initialization.
- * Board level can specify two unused I2C addresses
- * for each controller. Current chip level disables
- * controller response to address 0(general call).
- */
-const uint32_t i2c_ctrl_slave_addrs[I2C_CONTROLLER_COUNT] = {
-	0, 0, 0, 0,
-};
-
 const struct charger_config_t chg_chips[] = {
 	{
 		.i2c_port = I2C_PORT_CHARGER,
@@ -250,26 +248,6 @@ const struct charger_config_t chg_chips[] = {
 	},
 };
 
-/* Return the two slave addresses the specified
- * controller will respond to when controller
- * is acting as a slave.
- * b[6:0]  = b[7:1] of I2C address 1
- * b[14:8] = b[7:1] of I2C address 2
- * When not using I2C controllers as slaves we can use
- * the same value for all controllers. The address should
- * not be 0x00 as this is the general call address.
- */
-uint16_t board_i2c_slave_addrs(int controller)
-{
-	int i;
-
-	for (i = 0; i < I2C_CONTROLLER_COUNT; i++)
-		if ((i2c_ctrl_slave_addrs[i] & 0xffff) == controller)
-			return (i2c_ctrl_slave_addrs[i] >> 16);
-
-	return 0; /* general call address */
-}
-
 /*
  * default to I2C0 because callers may not check
  * return value if we returned an error code.
@@ -420,19 +398,23 @@ static int ps8751_tune_mux(const struct usb_mux *me)
 /*
  * USB_PD_PORT_ANX74XX and USB_PD_PORT_PS8751 are zero based indices into
  * tcpc_config array. The tcpc_config array contains the actual EC I2C
- * port, device slave address, and a function pointer into the driver code.
+ * port, device address, and a function pointer into the driver code.
  */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_ANX74XX] = {
-		.usb_port = USB_PD_PORT_ANX74XX,
-		.driver = &anx74xx_tcpm_usb_mux_driver,
-		.hpd_update = &anx74xx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_ANX74XX,
+			.driver = &anx74xx_tcpm_usb_mux_driver,
+			.hpd_update = &anx74xx_tcpc_update_hpd_status,
+		},
 	},
 	[USB_PD_PORT_PS8751] = {
-		.usb_port = USB_PD_PORT_PS8751,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-		.board_init = &ps8751_tune_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_PS8751,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			.board_init = &ps8751_tune_mux,
+		},
 	}
 };
 
@@ -540,9 +522,10 @@ void board_tcpc_init(void)
 	 * HPD pulse to enable video path
 	 */
 	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		usb_mux_hpd_update(port, 0, 0);
+		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
 
 /*
  * Data derived from Seinhart-Hart equation in a resistor divider circuit with
@@ -579,8 +562,7 @@ int board_get_charger_temp(int idx, int *temp_ptr)
 	if (mv < 0)
 		return -1;
 
-	*temp_ptr = thermistor_linear_interpolate(mv,
-		&charger_thermistor_info);
+	*temp_ptr = thermistor_linear_interpolate(mv, &charger_thermistor_info);
 	*temp_ptr = C_TO_K(*temp_ptr);
 	return 0;
 }
@@ -620,8 +602,7 @@ int board_get_ambient_temp(int idx, int *temp_ptr)
 	if (mv < 0)
 		return -1;
 
-	*temp_ptr = thermistor_linear_interpolate(mv,
-		&amb_thermistor_info);
+	*temp_ptr = thermistor_linear_interpolate(mv, &amb_thermistor_info);
 	*temp_ptr = C_TO_K(*temp_ptr);
 	return 0;
 }
@@ -632,9 +613,9 @@ int board_get_ambient_temp(int idx, int *temp_ptr)
  * delay from read to taking action
  */
 const struct temp_sensor_t temp_sensors[] = {
-	{"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0},
-	{"Ambient", TEMP_SENSOR_TYPE_BOARD, board_get_ambient_temp, 0},
-	{"Charger", TEMP_SENSOR_TYPE_BOARD, board_get_charger_temp, 1},
+	{ "Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0 },
+	{ "Ambient", TEMP_SENSOR_TYPE_BOARD, board_get_ambient_temp, 0 },
+	{ "Charger", TEMP_SENSOR_TYPE_BOARD, board_get_charger_temp, 1 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -669,7 +650,8 @@ void chipset_pre_init_callback(void)
 
 static void board_set_tablet_mode(void)
 {
-	tablet_set_mode(!gpio_get_level(GPIO_TABLET_MODE_L));
+	tablet_set_mode(!gpio_get_level(GPIO_TABLET_MODE_L),
+			TABLET_TRIGGER_LID);
 }
 
 /* Initialize board. */
@@ -755,8 +737,8 @@ int board_set_active_charge_port(int charge_port)
  * @param charge_ma     Desired charge limit (mA).
  * @param charge_mv     Negotiated charge voltage (mV).
  */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
 {
 	/* Enable charging trigger by BC1.2 detection */
 	int bc12_enable = (supplier == CHARGE_SUPPLIER_BC12_CDP ||
@@ -767,9 +749,7 @@ void board_set_charge_limit(int port, int supplier, int charge_ma,
 	if (bd9995x_bc12_enable_charging(port, bc12_enable))
 		return;
 
-	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-			CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+	charge_set_input_current_limit(charge_ma, charge_mv);
 }
 
 /**
@@ -811,8 +791,7 @@ static void enable_input_devices(void)
 }
 
 /* Enable or disable input devices, based on chipset state and tablet mode */
-#ifndef TEST_BUILD
-void lid_angle_peripheral_enable(int enable)
+__override void lid_angle_peripheral_enable(int enable)
 {
 	/* If the lid is in 360 position, ignore the lid angle,
 	 * which might be faulty. Disable keyboard.
@@ -821,7 +800,6 @@ void lid_angle_peripheral_enable(int enable)
 		enable = 0;
 	keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
 }
-#endif
 
 /* Called on AP S5 -> S3 transition */
 static void board_chipset_startup(void)
@@ -897,17 +875,17 @@ void board_hibernate_late(void)
 	int i;
 	const uint32_t hibernate_pins[][2] = {
 		/* Turn off LEDs in hibernate */
-		{GPIO_BAT_LED_BLUE, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_BAT_LED_AMBER, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_LID_OPEN, GPIO_INT_RISING | GPIO_PULL_DOWN},
+		{ GPIO_BAT_LED_BLUE, GPIO_INPUT | GPIO_PULL_UP },
+		{ GPIO_BAT_LED_AMBER, GPIO_INPUT | GPIO_PULL_UP },
+		{ GPIO_LID_OPEN, GPIO_INT_RISING | GPIO_PULL_DOWN },
 
 		/*
 		 * BD99956 handles charge input automatically. We'll disable
 		 * charge output in hibernate. Charger will assert ACOK_OD
 		 * when VBUS or VCC are plugged in.
 		 */
-		{GPIO_USB_C0_5V_EN,       GPIO_INPUT  | GPIO_PULL_DOWN},
-		{GPIO_USB_C1_5V_EN,       GPIO_INPUT  | GPIO_PULL_DOWN},
+		{ GPIO_USB_C0_5V_EN, GPIO_INPUT | GPIO_PULL_DOWN },
+		{ GPIO_USB_C1_5V_EN, GPIO_INPUT | GPIO_PULL_DOWN },
 	};
 
 	/* Change GPIOs' state in hibernate for better power consumption */
@@ -934,17 +912,13 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0,  0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+				       { FLOAT_TO_FP(1), 0, 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
 
-const mat33_fp_t mag_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0,  FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t mag_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				      { 0, FLOAT_TO_FP(1), 0 },
+				      { 0, 0, FLOAT_TO_FP(-1) } };
 
 /* sensor private data */
 static struct kionix_accel_data g_kx022_data;
@@ -1048,7 +1022,10 @@ struct motion_sensor_t motion_sensors[] = {
 	 .default_range = BIT(11), /* 16LSB / uT, fixed */
 	 .rot_standard_ref = &mag_standard_ref,
 	 .min_frequency = BMM150_MAG_MIN_FREQ,
+/* TODO(b/253292373): Remove when clang is fixed. */
+DISABLE_CLANG_WARNING("-Wshift-count-negative")
 	 .max_frequency = BMM150_MAG_MAX_FREQ(SPECIAL),
+ENABLE_CLANG_WARNING("-Wshift-count-negative")
 	},
 	[BASE_BARO] = {
 	 .name = "Base Baro",
@@ -1120,8 +1097,8 @@ struct {
 	int thresh_mv;
 } const reef_board_versions[] = {
 	/* Vin = 3.3V, R1 = 46.4K, R2 values listed below */
-	{ BOARD_VERSION_1, 328 * 1.03 },  /* 5.11 Kohm */
-	{ BOARD_VERSION_2, 670 * 1.03 },  /* 11.8 Kohm */
+	{ BOARD_VERSION_1, 328 * 1.03 }, /* 5.11 Kohm */
+	{ BOARD_VERSION_2, 670 * 1.03 }, /* 11.8 Kohm */
 	{ BOARD_VERSION_3, 1012 * 1.03 }, /* 20.5 Kohm */
 	{ BOARD_VERSION_4, 1357 * 1.03 }, /* 32.4 Kohm */
 	{ BOARD_VERSION_5, 1690 * 1.03 }, /* 48.7 Kohm */
@@ -1183,7 +1160,7 @@ int board_get_version(void)
 }
 
 /* Keyboard scan setting */
-struct keyboard_scan_config keyscan_config = {
+__override struct keyboard_scan_config keyscan_config = {
 	/*
 	 * F3 key scan cycle completed but scan input is not
 	 * charging to logic high when EC start scan next
diff --git a/board/reef_mchp/board.h b/board/reef_mchp/board.h
index 0e630e15fb..f9db14a01e 100644
--- a/board/reef_mchp/board.h
+++ b/board/reef_mchp/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,24 +12,26 @@
  * By default, enable all console messages excepted HC, ACPI and event:
  * The sensor stack is generating a lot of activity.
  */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
 #undef CONFIG_HOSTCMD_DEBUG_MODE
 #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
 
+/* EC console on UART 0 */
+#define CONFIG_UART_CONSOLE 0
 
 /* EC console commands  */
 #define CONFIG_CMD_ACCELS
 #define CONFIG_CMD_ACCEL_INFO
 #define CONFIG_CMD_BATT_MFG_ACCESS
 #define CONFIG_CMD_CHARGER_ADC_AMON_BMON
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 #define BD9995X_IOUT_GAIN_SELECT \
-		BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V
+	BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V
 
 #define CONFIG_CHARGER_PSYS_READ
 #define BD9995X_PSYS_GAIN_SELECT \
-		BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_02UAW
+	BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_02UAW
 
 #define CONFIG_CMD_I2C_STRESS_TEST
 #define CONFIG_CMD_I2C_STRESS_TEST_ACCEL
@@ -39,7 +41,7 @@
 #define CONFIG_CMD_I2C_STRESS_TEST_TCPC
 
 /* Battery */
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY  "LION"
+#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
 #define CONFIG_BATTERY_CUT_OFF
 #define CONFIG_BATTERY_PRESENT_CUSTOM
 #define CONFIG_BATTERY_SMART
@@ -51,15 +53,19 @@
 #define CONFIG_CHARGER_BD9995X
 #define CONFIG_CHARGER_BD9995X_CHGEN
 #define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT 512
+#define CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT 512
+#define CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT 512
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 5
 #define CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT 1
 #define CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW 18000
 #define CONFIG_CHARGER_MAINTAIN_VBAT
+#undef CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON
 #define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 1
 #define CONFIG_USB_CHARGER
 #define CONFIG_CHARGER_PROFILE_OVERRIDE
 #define CONFIG_CHARGER_PROFILE_OVERRIDE_COMMON
-#undef  CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES
+#undef CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES
 #define CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES 3
 #define CONFIG_CHARGE_MANAGER_EXTERNAL_POWER_LIMIT
 
@@ -86,7 +92,7 @@
 #define CONFIG_USB_PD_PORT_MAX_COUNT 2
 #define CONFIG_USB_PD_VBUS_DETECT_CHARGER
 #define CONFIG_USB_PD_TCPC_LOW_POWER
-#define CONFIG_USB_PD_TCPM_MUX  /* for both PS8751 and ANX3429 */
+#define CONFIG_USB_PD_TCPM_MUX /* for both PS8751 and ANX3429 */
 #define CONFIG_USB_PD_TCPM_ANX3429 /* Silicon on Reef is ANX3429 */
 #define CONFIG_USB_PD_TCPM_PS8751
 #define CONFIG_USB_PD_TCPM_TCPCI
@@ -101,7 +107,7 @@
 #define CONFIG_USBC_VCONN_SWAP
 
 /* SoC / PCH */
-#define CONFIG_HOSTCMD_LPC
+#define CONFIG_HOST_INTERFACE_LPC
 #define CONFIG_CHIPSET_APOLLOLAKE
 #define CONFIG_CHIPSET_RESET_HOOK
 #define CONFIG_POWER_BUTTON
@@ -109,18 +115,18 @@
 #define CONFIG_POWER_COMMON
 #define CONFIG_POWER_S0IX
 #define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
+#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD
 
 /* EC */
 #define CONFIG_ADC
-#define CONFIG_BOARD_VERSION_CUSTOM
 #define CONFIG_EXTPOWER_GPIO
-#undef   CONFIG_EXTPOWER_DEBOUNCE_MS
-#define  CONFIG_EXTPOWER_DEBOUNCE_MS 1000
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
+#define CONFIG_EXTPOWER_DEBOUNCE_MS 1000
 #define CONFIG_FPU
 #define CONFIG_HOSTCMD_FLASH_SPI_INFO
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
-#define CONFIG_KEYBOARD_BOARD_CONFIG
+#define CONFIG_I2C_CONTROLLER
+
 #define CONFIG_KEYBOARD_PROTOCOL_8042
 #define CONFIG_KEYBOARD_COL2_INVERTED
 #define CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2
@@ -142,7 +148,7 @@
 #define CONFIG_WIRELESS
 #define CONFIG_WIRELESS_SUSPEND EC_WIRELESS_SWITCH_WLAN_POWER
 #define CONFIG_WLAN_POWER_ACTIVE_LOW
-#define  WIRELESS_GPIO_WLAN_POWER GPIO_WIRELESS_GPIO_WLAN_POWER
+#define WIRELESS_GPIO_WLAN_POWER GPIO_WIRELESS_GPIO_WLAN_POWER
 #define CONFIG_PWR_STATE_DISCHARGE_FULL
 
 /*
@@ -166,9 +172,9 @@
 #define CONFIG_SPI_FLASH_PORT 0
 #define CONFIG_SPI_FLASH
 
-#define CONFIG_FLASH_SIZE 524288
+#define CONFIG_FLASH_SIZE_BYTES 524288
 #define CONFIG_SPI_FLASH_REGS
-#define CONFIG_SPI_FLASH_W25Q40	/* FIXME: Should be GD25LQ40? */
+#define CONFIG_SPI_FLASH_W25Q40 /* FIXME: Should be GD25LQ40? */
 
 /*
  * Enable 1 slot of secure temporary storage to support
@@ -183,23 +189,22 @@
 #define CONFIG_BOARD_PRE_INIT
 
 /* I2C ports */
-#define I2C_CONTROLLER_COUNT	4
-#define I2C_PORT_COUNT		5
-
-#define I2C_PORT_GYRO			MCHP_I2C_PORT6
-#define I2C_PORT_LID_ACCEL		MCHP_I2C_PORT7
-#define I2C_PORT_ALS			MCHP_I2C_PORT7
-#define I2C_PORT_BARO			MCHP_I2C_PORT7
-#define I2C_PORT_BATTERY		MCHP_I2C_PORT3
-#define I2C_PORT_CHARGER		MCHP_I2C_PORT3
+#define I2C_CONTROLLER_COUNT 4
+#define I2C_PORT_COUNT 5
+
+#define I2C_PORT_GYRO MCHP_I2C_PORT6
+#define I2C_PORT_LID_ACCEL MCHP_I2C_PORT7
+#define I2C_PORT_ALS MCHP_I2C_PORT7
+#define I2C_PORT_BARO MCHP_I2C_PORT7
+#define I2C_PORT_BATTERY MCHP_I2C_PORT3
+#define I2C_PORT_CHARGER MCHP_I2C_PORT3
 /* Accelerometer and Gyroscope are the same device. */
-#define I2C_PORT_ACCEL			I2C_PORT_GYRO
+#define I2C_PORT_ACCEL I2C_PORT_GYRO
 
 /* Sensors */
 #define CONFIG_MKBP_EVENT
 #define CONFIG_MKBP_USE_HOST_EVENT
 #define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCEL_INTERRUPTS
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 #define CONFIG_MAG_BMI_BMM150
@@ -220,7 +225,6 @@
 /* Depends on how fast the AP boots and typical ODRs */
 #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
 
-
 #ifndef __ASSEMBLER__
 
 #include "gpio_signal.h"
@@ -228,9 +232,9 @@
 
 /* ADC signal */
 enum adc_channel {
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC0 */
-	ADC_TEMP_SENSOR_AMB,		/* ADC1 */
-	ADC_BOARD_ID,			/* ADC2 */
+	ADC_TEMP_SENSOR_CHARGER, /* ADC0 */
+	ADC_TEMP_SENSOR_AMB, /* ADC1 */
+	ADC_BOARD_ID, /* ADC2 */
 	ADC_CH_COUNT
 };
 
@@ -269,7 +273,7 @@ enum sensor_id {
 	BASE_GYRO,
 	BASE_MAG,
 	BASE_BARO,
-	LID_ALS,	/* firmware-reef-9042.B doesn't have this */
+	LID_ALS, /* firmware-reef-9042.B doesn't have this */
 	SENSOR_COUNT,
 };
 
@@ -292,17 +296,16 @@ enum reef_board_version {
  * delay to turn on the power supply max is ~16ms.
  * delay to turn off the power supply max is about ~180ms.
  */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* delay to turn on/off vconn */
-#define PD_VCONN_SWAP_DELAY 5000 /* us */
 
 /* Define typical operating power and max power */
 #define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       45000
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_VOLTAGE_MV     20000
+#define PD_MAX_POWER_MW 45000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Reset PD MCU */
 void board_reset_pd_mcu(void);
@@ -315,14 +318,6 @@ void board_print_tcpc_fw_version(int port);
 /* Map I2C port to controller */
 int board_i2c_p2c(int port);
 
-/* Return the two slave addresses the specified
- * controller will respond to when controller
- * is acting as a slave.
- * b[6:0]  = b[7:1] of I2C address 1
- * b[14:8] = b[7:1] of I2C address 2
- */
-uint16_t board_i2c_slave_addrs(int controller);
-
 /* MCHP - firwmare-reef-9042.B does have LID_ALS bit
  * because its using TASK_ALS ?
  */
diff --git a/board/reef_mchp/build.mk b/board/reef_mchp/build.mk
index 303eae4be4..afc530837e 100644
--- a/board/reef_mchp/build.mk
+++ b/board/reef_mchp/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -7,8 +7,8 @@
 #
 
 CHIP:=mchp
-CHIP_FAMILY:=mec17xx
-CHIP_VARIANT:=mec1701h
+CHIP_FAMILY:=mec170x
+CHIP_VARIANT:=mec1701
 CHIP_SPI_SIZE_KB:=512
 
 board-y=board.o led.o
diff --git a/board/reef_mchp/ec.tasklist b/board/reef_mchp/ec.tasklist
index adf63fae62..8611d09301 100644
--- a/board/reef_mchp/ec.tasklist
+++ b/board/reef_mchp/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/reef_mchp/gpio.inc b/board/reef_mchp/gpio.inc
index baaf36330e..9783649e25 100644
--- a/board/reef_mchp/gpio.inc
+++ b/board/reef_mchp/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,6 +8,9 @@
 /* Declare symbolic names for all the GPIOs that we care about.
  * Note: Those with interrupt handlers must be declared first. */
 
+/* include common gpio.inc under chip/mchp/lfw/... */
+#include "chip/mchp/lfw/gpio.inc"
+
 /* MEC1701H GPIO_0105/UART0_RX OK */
 GPIO_INT(UART0_RX, PIN(0105), GPIO_INT_BOTH_DSLEEP | GPIO_PULL_UP, \
 	 uart_deepsleep_interrupt)
@@ -81,7 +84,8 @@ GPIO(EC_I2C_POWER_SCL,		PIN(010), GPIO_INPUT)
  * Pin 57 (SER_IRQ) defaults to LPC mode, but we also have EC_PCH_KB_INT_ODL
  * (Pin B0) in case it doesn't work (Set CONFIG_KEYBOARD_IRQ_GPIO in this case).
  *
- * See also the NO_LPC_ESPI bit in DEVALT1 and the CONFIG_HOSTCMD_SPS option.
+ * See also the NO_LPC_ESPI bit in DEVALT1 and the
+ * CONFIG_HOST_INTERFACE_SHI option.
  */
 
 GPIO(PCH_SMI_L,			PIN(0227), GPIO_ODR_HIGH | GPIO_SEL_1P8V)	/* EC_SMI_ODL */
@@ -167,35 +171,10 @@ GPIO(USB_C1_5V_EN,		PIN(061), GPIO_OUT_LOW | GPIO_PULL_UP)	/* EN_USB_C1_5V_OUT,
 GPIO(BAT_LED_BLUE,		PIN(0153), GPIO_OUT_HIGH)
 GPIO(BAT_LED_AMBER,		PIN(0226), GPIO_OUT_HIGH)
 
-/*
- * MEC1701H
- * GPIO_0055/PWM2/SHD_CS0#/RSMRST#
- * GPIO_0124/GPTP-OUT6/PVT_CS#/KSO11
- * QMSPI controller drives chip select, must be
- * configured to alternative function. See below.
- * Always use the name QMSPI_CS0 for chip select.
- * Actual GPIO could be GPIO_0055 QMSPI shared chip select or
- * GPIO_0124 private chip select.
- */
-GPIO(QMSPI_CS0,	PIN(055),  GPIO_ODR_HIGH)
-
 /*
  * Alternate function pins
  */
 
-/*
- * MEC1701H SHD SPI is connected to QMSPI controller.
- * QMSPI drives chip select. SHD_CS0#(GPIO_0055) must be set
- * to alternate function 2 and GPIO_ODR_HIGH.
- * GPIO_0055 Function 2, Bank 1 bit[13]
- */
-ALTERNATE(PIN_MASK(1, 0x2000), 2, MODULE_SPI_FLASH, GPIO_ODR_HIGH)
-/* SHD_CLK - GPIO_0056 Function 2, Bank 1 bit[14] */
-ALTERNATE(PIN_MASK(1, 0x4000), 2, MODULE_SPI_FLASH, 0)
-/* MOSI(SHD_IO0) - GPIO_0223 Function 2, Bank 4 bit[19] */
-/* MISO(SHD_IO1) - GPIO_0224 Function 2, Bank 4 bit[20] */
-ALTERNATE(PIN_MASK(4, 0x180000), 2, MODULE_SPI_FLASH, 0)
-
 /* MEC1701H LPC all alternate function 1
  *			bank	bit
  * GPIO061 LPCPD#	1	17
@@ -290,13 +269,6 @@ ALTERNATE(PIN_MASK(3, 0x00003001), 1, MODULE_I2C, 0)
 /* reefmchp board note: not PWM in reef or reedmchp boards design?? */
 //ALTERNATE(PIN_MASK(0, 0x00000006), 1, MODULE_PWM, 0)
 
-/*
- * GPIO_0104(UART0_TX) Func1
- * GPIO_0105(UART0_RX) Func1
- * Bank 2 bits[4:5]
- */
-ALTERNATE(PIN_MASK(2, 0x30), 1, MODULE_UART, 0)
-
 /*
  * MCHP TFDP alternate function configuration
  * GPIO 0170 = clock, 0171 = data both function 1
diff --git a/board/reef_mchp/led.c b/board/reef_mchp/led.c
index ca49fe4ed5..ad06133890 100644
--- a/board/reef_mchp/led.c
+++ b/board/reef_mchp/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -27,8 +27,7 @@
 #define LED_ON_1SEC_TICKS 1
 #define LED_ON_2SECS_TICKS 2
 
-const enum ec_led_id supported_led_ids[] = {
-			EC_LED_ID_BATTERY_LED};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -36,7 +35,7 @@ enum led_color {
 	LED_OFF = 0,
 	LED_BLUE,
 	LED_AMBER,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static int led_set_color_battery(enum led_color color)
@@ -97,41 +96,46 @@ static void led_set_battery(void)
 	static int battery_ticks;
 	static int suspend_ticks;
 
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
 		led_set_color_battery(LED_AMBER);
 		break;
-	case PWR_STATE_DISCHARGE_FULL:
+	case LED_PWRS_DISCHARGE_FULL:
 		if (extpower_is_present()) {
 			led_set_color_battery(LED_BLUE);
 			break;
 		}
-		/* Intentional fall-through */
-	case PWR_STATE_DISCHARGE /* and PWR_STATE_DISCHARGE_FULL */:
+		__fallthrough;
+	case LED_PWRS_DISCHARGE /* and LED_PWRS_DISCHARGE_FULL */:
 		if (chipset_in_state(CHIPSET_STATE_ON)) {
 			led_set_color_battery(LED_BLUE);
 		} else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
 			/* Blink once every four seconds. */
 			led_set_color_battery(
-				(suspend_ticks % LED_TOTAL_4SECS_TICKS)
-				< LED_ON_1SEC_TICKS ? LED_AMBER : LED_OFF);
+				(suspend_ticks % LED_TOTAL_4SECS_TICKS) <
+						LED_ON_1SEC_TICKS ?
+					LED_AMBER :
+					LED_OFF);
 		} else {
 			led_set_color_battery(LED_OFF);
 		}
 		break;
-	case PWR_STATE_ERROR:
-		led_set_color_battery(
-			(battery_ticks % LED_TOTAL_2SECS_TICKS <
-			 LED_ON_1SEC_TICKS) ? LED_AMBER : LED_OFF);
+	case LED_PWRS_ERROR:
+		led_set_color_battery((battery_ticks % LED_TOTAL_2SECS_TICKS <
+				       LED_ON_1SEC_TICKS) ?
+					      LED_AMBER :
+					      LED_OFF);
 		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
+	case LED_PWRS_CHARGE_NEAR_FULL:
 		led_set_color_battery(LED_BLUE);
 		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
 		if (charge_get_flags() & CHARGE_FLAG_FORCE_IDLE)
 			led_set_color_battery(
 				(battery_ticks % LED_TOTAL_4SECS_TICKS <
-				 LED_ON_2SECS_TICKS) ? LED_AMBER : LED_BLUE);
+				 LED_ON_2SECS_TICKS) ?
+					LED_AMBER :
+					LED_BLUE);
 		else
 			led_set_color_battery(LED_BLUE);
 		break;
diff --git a/board/reef_mchp/lfw/gpio.inc b/board/reef_mchp/lfw/gpio.inc
deleted file mode 100644
index f4142d3c29..0000000000
--- a/board/reef_mchp/lfw/gpio.inc
+++ /dev/null
@@ -1,43 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Minimal set of GPIOs needed for LFW loader
- */
-
-/*
- * MEC1701H GPIO_0055/PWM2/SHD_CS0#/RSMRST#
- * MEC1701H QMSPI controller drives chip select, must be
- * configured to alternative function. See below.
- * GPIO_SHD_CS0 is used in board level spi_devices[] table
- */
-GPIO(QMSPI_CS0,	PIN(055),  GPIO_ODR_HIGH)
-
-
-/* Alternate functions GPIO definition */
-
-/*
- * UART
- * GPIO_0104(UART0_TX) Func1
- * GPIO_0105(UART0_RX) Func1
- * Bank 2 bits[4:5]
-*/
-ALTERNATE(PIN_MASK(2, 0x30), 1, MODULE_UART, 0)
-
-/* SPI pins */
-/*
- * MEC1701H SHD SPI is connected to QMSPI controller.
- * QMSPI drives chip select. SHD_CS0#(GPIO_0055) must be set
- * to alternate function 2 and GPIO_ODR_HIGH.
- * GPIO_0055 Function 2, Bank 1 bit[13]
- */
-ALTERNATE(PIN_MASK(1, 0x2000), 2, MODULE_SPI_FLASH, GPIO_ODR_HIGH)
-/* SHD_CLK - GPIO_0056 Function 2, Bank 1 bit[14] */
-ALTERNATE(PIN_MASK(1, 0x4000), 2, MODULE_SPI_FLASH, 0)
-/* MOSI(SHD_IO0) - GPIO_0223 Function 2, Bank 4 bit[19] */
-/* MISO(SHD_IO1) - GPIO_0224 Function 2, Bank 4 bit[20] */
-ALTERNATE(PIN_MASK(4, 0x180000), 2, MODULE_SPI_FLASH, 0)
-
-
diff --git a/board/reef_mchp/lfw/vif_override.xml b/board/reef_mchp/lfw/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/reef_mchp/lfw/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/reef_mchp/usb_pd_policy.c b/board/reef_mchp/usb_pd_policy.c
index 90f44f8580..060d53a58a 100644
--- a/board/reef_mchp/usb_pd_policy.c
+++ b/board/reef_mchp/usb_pd_policy.c
@@ -1,36 +1,35 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "atomic.h"
-#include "extpower.h"
 #include "charge_manager.h"
 #include "common.h"
 #include "console.h"
 #include "driver/charger/bd9995x.h"
 #include "driver/tcpm/anx74xx.h"
 #include "driver/tcpm/ps8xxx.h"
+#include "extpower.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "host_command.h"
 #include "registers.h"
 #include "system.h"
 #include "task.h"
+#include "tfdp_chip.h"
 #include "timer.h"
-#include "util.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
+#include "util.h"
 
-#include "tfdp_chip.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT];
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5,
-							TYPEC_RP_1A5};
+static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5,
+							 TYPEC_RP_1A5 };
 
 int board_vbus_source_enabled(int port)
 {
@@ -41,7 +40,8 @@ static void board_vbus_update_source_current(int port)
 {
 	enum gpio_signal gpio = port ? GPIO_USB_C1_5V_EN : GPIO_USB_C0_5V_EN;
 	int flags = (vbus_rp[port] == TYPEC_RP_1A5 && vbus_en[port]) ?
-		(GPIO_INPUT | GPIO_PULL_UP) : (GPIO_OUTPUT | GPIO_PULL_UP);
+			    (GPIO_INPUT | GPIO_PULL_UP) :
+			    (GPIO_OUTPUT | GPIO_PULL_UP);
 
 	/*
 	 * Driving USB_Cx_5V_EN high, actually put a 16.5k resistance
diff --git a/board/reef_mchp/vif_override.xml b/board/reef_mchp/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/reef_mchp/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/samus/battery.c b/board/samus/battery.c
deleted file mode 100644
index bc73cbc1c3..0000000000
--- a/board/samus/battery.c
+++ /dev/null
@@ -1,301 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_smart.h"
-#include "charge_state.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "i2c.h"
-#include "util.h"
-
-static const struct battery_info info = {
-	/*
-	 * Design voltage
-	 *   max    = 8.4V
-	 *   normal = 7.4V
-	 *   min    = 6.0V
-	 */
-	.voltage_max    = 8700,
-	.voltage_normal = 7400,
-	.voltage_min    = 6000,
-
-	/* Pre-charge current: I <= 0.01C */
-	.precharge_current  = 64, /* mA */
-
-	/*
-	 * Operational temperature range
-	 *   0 <= T_charge    <= 50 deg C
-	 * -20 <= T_discharge <= 60 deg C
-	 */
-	.start_charging_min_c = 0,
-	.start_charging_max_c = 50,
-	.charging_min_c       = 0,
-	.charging_max_c       = 50,
-	.discharging_min_c    = -20,
-	.discharging_max_c    = 60,
-};
-
-const struct battery_info *battery_get_info(void)
-{
-	return &info;
-}
-
-#ifdef CONFIG_CHARGER_PROFILE_OVERRIDE
-
-static int fast_charging_allowed = 1;
-
-/*
- * This can override the smart battery's charging profile. To make a change,
- * modify one or more of requested_voltage, requested_current, or state.
- * Leave everything else unchanged.
- *
- * Return the next poll period in usec, or zero to use the default (which is
- * state dependent).
- */
-int charger_profile_override(struct charge_state_data *curr)
-{
-	/* temp in 0.1 deg C */
-	int temp_c;
-	const struct charger_info *info;
-
-	/* keep track of last temperature range for hysteresis */
-	static enum {
-		TEMP_LOW,
-		TEMP_NORMAL,
-		TEMP_HIGH
-	} temp_range = TEMP_NORMAL, prev_temp_range = TEMP_NORMAL;
-
-	/* charging voltage to use at high temp */
-	static int high_temp_charging_voltage;
-
-	/* custom profile phase at normal temp */
-	static int normal_temp_phase;
-
-	/* battery voltage and current and previous voltage and current */
-	int batt_voltage, batt_current;
-	static int prev_batt_voltage, prev_batt_current;
-
-	/*
-	 * Determine temperature range:
-	 * Low: Battery is <15C
-	 * Normal: Battery is 15-45C
-	 * High: Battery is >45C
-	 *
-	 * Add 0.2 degrees of hysteresis.
-	 * If temp reading was bad use last range.
-	 */
-	if (!(curr->batt.flags & BATT_FLAG_BAD_TEMPERATURE)) {
-		temp_c = curr->batt.temperature - 2731;
-		if (temp_c < 149)
-			temp_range = TEMP_LOW;
-		else if (temp_c > 151 && temp_c < 449)
-			temp_range = TEMP_NORMAL;
-		else if (temp_c > 451)
-			temp_range = TEMP_HIGH;
-	}
-
-	/*
-	 * Treat voltage and current as a pair, if either is bad fall back to
-	 * previous reading.
-	 */
-	if (curr->batt.flags &
-	    (BATT_FLAG_BAD_VOLTAGE | BATT_FLAG_BAD_CURRENT)) {
-		batt_voltage = prev_batt_voltage;
-		batt_current = prev_batt_current;
-	} else {
-		batt_voltage = prev_batt_voltage = curr->batt.voltage;
-		batt_current = prev_batt_current = curr->batt.current;
-	}
-
-	/*
-	 * If we are not charging or we aren't using fast charging profiles,
-	 * then do not override desired current and voltage and reset some
-	 * fast charging profile static variables.
-	 */
-	if (curr->state != ST_CHARGE || !fast_charging_allowed) {
-		prev_temp_range = TEMP_NORMAL;
-		normal_temp_phase = 0;
-		return 0;
-	}
-
-	/*
-	 * Okay, impose our custom will:
-	 * Normal temp:
-	 * Phase 0: CC at 9515mA @ 8.3V
-	 *          CV at 8.3V until current drops to 4759mA
-	 * Phase 1: CC at 4759mA @ 8.7V
-	 *          CV at 8.7V
-	 *
-	 * Low temp:
-	 * CC at 2854mA @ 8.7V
-	 * CV at 8.7V
-	 *
-	 * High temp:
-	 * If battery voltage < 8.3V then:
-	 *	CC at 6660mA @ 8.3V
-	 *	CV at 8.3V (when battery is hot we don't go to fully charged)
-	 * else:
-	 *	CV at just above battery voltage which will essentially
-	 *         terminate the charge and allow battery to cool.
-	 * Note that if we ever request a voltage below the present battery
-	 * voltage, then we will stop the BQ switching, which will power off
-	 * the INA and we won't be able to charge again until AC is
-	 * disconnected. see crbug.com/p/35491.
-	 */
-	switch (temp_range) {
-	case TEMP_LOW:
-		curr->requested_current = 2854;
-		curr->requested_voltage = 8700;
-		break;
-	case TEMP_NORMAL:
-		if (normal_temp_phase == 0) {
-			curr->requested_current = 9515;
-			curr->requested_voltage = 8300;
-			if (batt_current <= 4759 && batt_voltage >= 8200)
-				normal_temp_phase = 1;
-		}
-		if (normal_temp_phase == 1) {
-			curr->requested_current = 4759;
-			curr->requested_voltage = 8700;
-		}
-		break;
-	case TEMP_HIGH:
-		/*
-		 * First time TEMP_HIGH is used, get the closest voltage
-		 * just above the battery voltage. If it is above 8.3V, we
-		 * will use that as the target, otherwise we will use 8.3V.
-		 */
-		if (prev_temp_range != TEMP_HIGH) {
-			info = charger_get_info();
-			high_temp_charging_voltage = MAX(8300,
-				charger_closest_voltage(batt_voltage +
-							info->voltage_step));
-		}
-		curr->requested_current = 6660;
-		curr->requested_voltage = high_temp_charging_voltage;
-		break;
-	}
-	prev_temp_range = temp_range;
-
-	return 0;
-}
-
-/* Customs options controllable by host command. */
-#define PARAM_FASTCHARGE (CS_PARAM_CUSTOM_PROFILE_MIN + 0)
-
-enum ec_status charger_profile_override_get_param(uint32_t param,
-						  uint32_t *value)
-{
-	if (param == PARAM_FASTCHARGE) {
-		*value = fast_charging_allowed;
-		return EC_RES_SUCCESS;
-	}
-	return EC_RES_INVALID_PARAM;
-}
-
-enum ec_status charger_profile_override_set_param(uint32_t param,
-						  uint32_t value)
-{
-	if (param == PARAM_FASTCHARGE) {
-		fast_charging_allowed = value;
-		return EC_RES_SUCCESS;
-	}
-	return EC_RES_INVALID_PARAM;
-}
-
-#ifdef CONFIG_CMD_FASTCHARGE
-static int command_fastcharge(int argc, char **argv)
-{
-	if (argc > 1 && !parse_bool(argv[1], &fast_charging_allowed))
-		return EC_ERROR_PARAM1;
-
-	ccprintf("fastcharge %s\n", fast_charging_allowed ? "on" : "off");
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(fastcharge, command_fastcharge,
-			"[on|off]",
-			"Get or set fast charging profile");
-#endif  /* CONFIG_CMD_FASTCHARGE */
-
-#endif	/* CONFIG_CHARGER_PROFILE_OVERRIDE */
-
-#ifdef CONFIG_BATTERY_REVIVE_DISCONNECT
-/*
- * Check if battery is in disconnect state, a state entered by pulling
- * BATT_DISCONN_N low, and clear that state if we have external power plugged
- * and no battery faults are detected. Disconnect state resembles battery
- * shutdown mode, but extra steps must be taken to get the battery out of this
- * mode.
- */
-enum battery_disconnect_state battery_get_disconnect_state(void)
-{
-	uint8_t data[6];
-	int rv;
-	/*
-	 * Take note if we find that the battery isn't in disconnect state,
-	 * and always return NOT_DISCONNECTED without probing the battery.
-	 * This assumes the battery will not go to disconnect state during
-	 * runtime.
-	 */
-	static int not_disconnected;
-
-	if (not_disconnected)
-		return BATTERY_NOT_DISCONNECTED;
-
-	if (extpower_is_present()) {
-		/* Check if battery charging + discharging is disabled. */
-		rv = sb_read_mfgacc(PARAM_OPERATION_STATUS,
-				SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data));
-		if (rv)
-			return BATTERY_DISCONNECT_ERROR;
-		if (~data[3] & (BATTERY_DISCHARGING_DISABLED |
-				BATTERY_CHARGING_DISABLED)) {
-			not_disconnected = 1;
-			return BATTERY_NOT_DISCONNECTED;
-		}
-
-		/*
-		 * Battery is neither charging nor discharging. Verify that
-		 * we didn't enter this state due to a safety fault.
-		 */
-		rv = sb_read_mfgacc(PARAM_SAFETY_STATUS,
-				SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data));
-		if (rv || data[2] || data[3] || data[4] || data[5])
-			return BATTERY_DISCONNECT_ERROR;
-		else
-			/* No safety fault -- clear disconnect state. */
-			return BATTERY_DISCONNECTED;
-	}
-	not_disconnected = 1;
-	return BATTERY_NOT_DISCONNECTED;
-}
-#endif /* CONFIG_BATTERY_REVIVE_DISCONNECT */
-
-#define PARAM_CUT_OFF_LOW  0x10
-#define PARAM_CUT_OFF_HIGH 0x00
-
-int board_cut_off_battery(void)
-{
-	int rv;
-	uint8_t buf[3];
-
-	buf[0] = SB_MANUFACTURER_ACCESS & 0xff;
-	buf[1] = PARAM_CUT_OFF_LOW;
-	buf[2] = PARAM_CUT_OFF_HIGH;
-
-	i2c_lock(I2C_PORT_BATTERY, 1);
-	rv = i2c_xfer_unlocked(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS,
-			       buf, 3, NULL, 0, I2C_XFER_SINGLE);
-	rv |= i2c_xfer_unlocked(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS,
-				buf, 3, NULL, 0, I2C_XFER_SINGLE);
-	i2c_lock(I2C_PORT_BATTERY, 0);
-
-	return rv;
-}
-
diff --git a/board/samus/board.c b/board/samus/board.c
deleted file mode 100644
index 211d000e86..0000000000
--- a/board/samus/board.c
+++ /dev/null
@@ -1,500 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* EC for Samus board configuration */
-
-#include "als.h"
-#include "adc.h"
-#include "adc_chip.h"
-#include "backlight.h"
-#include "battery.h"
-#include "capsense.h"
-#include "charger.h"
-#include "charge_state.h"
-#include "common.h"
-#include "console.h"
-#include "driver/accel_kionix.h"
-#include "driver/accel_kxcj9.h"
-#include "driver/accelgyro_lsm6ds0.h"
-#include "driver/als_isl29035.h"
-#include "driver/charger/bq24773.h"
-#include "driver/temp_sensor/tmp006.h"
-#include "extpower.h"
-#include "fan.h"
-#include "gesture.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "keyboard_scan.h"
-#include "keyboard_8042.h"
-#include "keyboard_8042_sharedlib.h"
-#include "lid_switch.h"
-#include "lightbar.h"
-#include "motion_sense.h"
-#include "motion_lid.h"
-#include "peci.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "temp_sensor_chip.h"
-#include "timer.h"
-#include "thermal.h"
-#include "uart.h"
-#include "util.h"
-
-static void pd_mcu_interrupt(enum gpio_signal signal)
-{
-	/* Exchange status with PD MCU. */
-	host_command_pd_send_status(PD_CHARGE_NO_CHANGE);
-}
-
-#include "gpio_list.h"
-
-/* power signal list.  Must match order of enum power_signal. */
-const struct power_signal_info power_signal_list[] = {
-	{GPIO_PP1050_PGOOD,  POWER_SIGNAL_ACTIVE_HIGH, "PGOOD_PP1050"},
-	{GPIO_PP1200_PGOOD,  POWER_SIGNAL_ACTIVE_HIGH, "PGOOD_PP1200"},
-	{GPIO_PP1800_PGOOD,  POWER_SIGNAL_ACTIVE_HIGH, "PGOOD_PP1800"},
-	{GPIO_VCORE_PGOOD,   POWER_SIGNAL_ACTIVE_HIGH, "PGOOD_VCORE"},
-	{GPIO_PCH_SLP_S0_L,  POWER_SIGNAL_ACTIVE_HIGH, "SLP_S0_DEASSERTED"},
-	{GPIO_PCH_SLP_S3_L,  POWER_SIGNAL_ACTIVE_HIGH, "SLP_S3_DEASSERTED"},
-	{GPIO_PCH_SLP_S5_L,  POWER_SIGNAL_ACTIVE_HIGH, "SLP_S5_DEASSERTED"},
-	{GPIO_PCH_SLP_SUS_L, POWER_SIGNAL_ACTIVE_HIGH, "SLP_SUS_DEASSERTED"},
-	{GPIO_PCH_SUSWARN_L, POWER_SIGNAL_ACTIVE_HIGH, "SUSWARN_DEASSERTED"},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
-const struct adc_t adc_channels[] = {
-	/*
-	 * EC internal temperature is calculated by
-	 * 273 + (295 - 450 * ADC_VALUE / ADC_READ_MAX) / 2
-	 * = -225 * ADC_VALUE / ADC_READ_MAX + 420.5
-	 */
-	{"ECTemp", LM4_ADC_SEQ0, -225, ADC_READ_MAX, 420,
-	 LM4_AIN_NONE, 0x0e /* TS0 | IE0 | END0 */, 0, 0},
-	/*
-	 * TODO(crosbug.com/p/23827): We don't know what to expect here, but
-	 * it's an analog input that's pulled high. We're using it as a battery
-	 * presence indicator for now. We'll return just 0 - ADC_READ_MAX for
-	 * now.
-	 */
-	{"BatteryTemp", LM4_ADC_SEQ2, 1, 1, 0,
-	 LM4_AIN(10), 0x06 /* IE0 | END0 */, LM4_GPIO_B, BIT(4)},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	{4, 0},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* Physical fans. These are logically separate from pwm_channels. */
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = 2,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = -1,
-};
-
-const struct fan_conf fan_conf_1 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = 3,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = -1,
-};
-
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 1000,
-	.rpm_start = 1000,
-	.rpm_max = 6350,
-};
-
-const struct fan_t fans[] = {
-	{ .conf = &fan_conf_0, .rpm = &fan_rpm_0, },
-	{ .conf = &fan_conf_1, .rpm = &fan_rpm_0, },
-};
-BUILD_ASSERT(ARRAY_SIZE(fans) == CONFIG_FANS);
-
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"batt_chg", 0, 100, GPIO_I2C0_SCL, GPIO_I2C0_SDA},
-	{"lightbar", 1, 400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"thermal",  5, 100, GPIO_I2C5_SCL, GPIO_I2C5_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* Charger chips */
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = I2C_ADDR_CHARGER_FLAGS,
-		.drv = &bq2477x_drv,
-	},
-};
-
-#define TEMP_U40_REG_ADDR_FLAGS		(0x40 | I2C_FLAG_BIG_ENDIAN)
-#define TEMP_U41_REG_ADDR_FLAGS		(0x44 | I2C_FLAG_BIG_ENDIAN)
-#define TEMP_U42_REG_ADDR_FLAGS		(0x41 | I2C_FLAG_BIG_ENDIAN)
-#define TEMP_U43_REG_ADDR_FLAGS		(0x45 | I2C_FLAG_BIG_ENDIAN)
-#define TEMP_U115_REG_ADDR_FLAGS	(0x42 | I2C_FLAG_BIG_ENDIAN)
-#define TEMP_U116_REG_ADDR_FLAGS	(0x43 | I2C_FLAG_BIG_ENDIAN)
-
-#define TEMP_U40_ADDR_FLAGS TMP006_ADDR(I2C_PORT_THERMAL,\
-					TEMP_U40_REG_ADDR_FLAGS)
-#define TEMP_U41_ADDR_FLAGS TMP006_ADDR(I2C_PORT_THERMAL,\
-					TEMP_U41_REG_ADDR_FLAGS)
-#define TEMP_U42_ADDR_FLAGS TMP006_ADDR(I2C_PORT_THERMAL,\
-					TEMP_U42_REG_ADDR_FLAGS)
-#define TEMP_U43_ADDR_FLAGS TMP006_ADDR(I2C_PORT_THERMAL,\
-					TEMP_U43_REG_ADDR_FLAGS)
-#define TEMP_U115_ADDR_FLAGS TMP006_ADDR(I2C_PORT_THERMAL,\
-					 TEMP_U115_REG_ADDR_FLAGS)
-#define TEMP_U116_ADDR_FLAGS TMP006_ADDR(I2C_PORT_THERMAL,\
-					 TEMP_U116_REG_ADDR_FLAGS)
-
-const struct tmp006_t tmp006_sensors[TMP006_COUNT] = {
-	{"Charger", TEMP_U40_ADDR_FLAGS},
-	{"CPU", TEMP_U41_ADDR_FLAGS},
-	{"Left C", TEMP_U42_ADDR_FLAGS},
-	{"Right C", TEMP_U43_ADDR_FLAGS},
-	{"Right D", TEMP_U115_ADDR_FLAGS},
-	{"Left D", TEMP_U116_ADDR_FLAGS},
-};
-BUILD_ASSERT(ARRAY_SIZE(tmp006_sensors) == TMP006_COUNT);
-
-/* Temperature sensors data; must be in same order as enum temp_sensor_id. */
-const struct temp_sensor_t temp_sensors[] = {
-	{"PECI", TEMP_SENSOR_TYPE_CPU, peci_temp_sensor_get_val, 0},
-	{"ECInternal", TEMP_SENSOR_TYPE_BOARD, chip_temp_sensor_get_val, 0},
-	{"I2C-Charger-Die", TEMP_SENSOR_TYPE_BOARD, tmp006_get_val, 0},
-	{"I2C-Charger-Object", TEMP_SENSOR_TYPE_CASE, tmp006_get_val, 1},
-	{"I2C-CPU-Die", TEMP_SENSOR_TYPE_BOARD, tmp006_get_val, 2},
-	{"I2C-CPU-Object", TEMP_SENSOR_TYPE_CASE, tmp006_get_val, 3},
-	{"I2C-Left C-Die", TEMP_SENSOR_TYPE_BOARD, tmp006_get_val, 4},
-	{"I2C-Left C-Object", TEMP_SENSOR_TYPE_CASE, tmp006_get_val, 5},
-	{"I2C-Right C-Die", TEMP_SENSOR_TYPE_BOARD, tmp006_get_val, 6},
-	{"I2C-Right C-Object", TEMP_SENSOR_TYPE_CASE, tmp006_get_val, 7},
-	{"I2C-Right D-Die", TEMP_SENSOR_TYPE_BOARD, tmp006_get_val, 8},
-	{"I2C-Right D-Object", TEMP_SENSOR_TYPE_CASE, tmp006_get_val, 9},
-	{"I2C-Left D-Die", TEMP_SENSOR_TYPE_BOARD, tmp006_get_val, 10},
-	{"I2C-Left D-Object", TEMP_SENSOR_TYPE_CASE, tmp006_get_val, 11},
-	{"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/* ALS instances. Must be in same order as enum als_id. */
-struct als_t als[] = {
-	{"ISL", isl29035_init, isl29035_read_lux, 5},
-};
-BUILD_ASSERT(ARRAY_SIZE(als) == ALS_COUNT);
-
-
-/* Thermal limits for each temp sensor. All temps are in degrees K. Must be in
- * same order as enum temp_sensor_id. To always ignore any temp, use 0.
- */
-struct ec_thermal_config thermal_params[] = {
-	/* {Twarn, Thigh, Thalt}, fan_off, fan_max */
-	{{C_TO_K(95), C_TO_K(101), C_TO_K(104)},
-	 {0, 0, 0}, C_TO_K(55), C_TO_K(90)},		/* PECI */
-	{{0, 0, 0}, {0, 0, 0}, 0, 0},			/* EC */
-	{{0, 0, 0}, {0, 0, 0}, C_TO_K(41), C_TO_K(55)},	/* Charger die */
-	{{0, 0, 0}, {0, 0, 0}, 0, 0},
-	{{0, 0, 0}, {0, 0, 0}, C_TO_K(35), C_TO_K(49)},	/* CPU die */
-	{{0, 0, 0}, {0, 0, 0}, 0, 0},
-	{{0, 0, 0}, {0, 0, 0}, 0, 0},			/* Left C die */
-	{{0, 0, 0}, {0, 0, 0}, 0, 0},
-	{{0, 0, 0}, {0, 0, 0}, 0, 0},			/* Right C die */
-	{{0, 0, 0}, {0, 0, 0}, 0, 0},
-	{{0, 0, 0}, {0, 0, 0}, 0, 0},			/* Right D die */
-	{{0, 0, 0}, {0, 0, 0}, 0, 0},
-	{{0, 0, 0}, {0, 0, 0}, C_TO_K(43), C_TO_K(54)},	/* Left D die */
-	{{0, 0, 0}, {0, 0, 0}, 0, 0},
-	{{0, 0, 0}, {0, 0, 0}, 0, 0},			/* Battery */
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-struct keyboard_scan_config keyscan_config = {
-	.output_settle_us = 40,
-	.debounce_down_us = 6 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 1500,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = SECOND,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xf6, 0x55, 0xfa, 0xc8  /* full set */
-	},
-};
-
-/* Initialize board. */
-static void board_init(void)
-{
-	gpio_enable_interrupt(GPIO_PD_MCU_INT);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-#ifdef CONFIG_BATTERY_PRESENT_CUSTOM
-/**
- * Physical check of battery presence.
- */
-enum battery_present battery_is_present(void)
-{
-	/*
-	 * This pin has a pullup, so if it's not completely pegged there's
-	 * something attached. Probably a battery.
-	 */
-	int analog_val = adc_read_channel(ADC_CH_BAT_TEMP);
-	return analog_val < (9 * ADC_READ_MAX / 10) ? BP_YES : BP_NO;
-}
-#endif
-
-static int discharging_on_ac;
-
-/**
- * Discharge battery when on AC power for factory test.
- */
-int board_discharge_on_ac(int enable)
-{
-	int rv = charger_discharge_on_ac(enable);
-
-	if (rv == EC_SUCCESS)
-		discharging_on_ac = enable;
-
-	return rv;
-}
-
-/**
- * Check if we are discharging while connected to AC
- */
-int board_is_discharging_on_ac(void)
-{
-	return discharging_on_ac;
-}
-
-/**
- * Reset PD MCU
- */
-void board_reset_pd_mcu(void)
-{
-	gpio_set_level(GPIO_USB_MCU_RST, 1);
-	usleep(100);
-	gpio_set_level(GPIO_USB_MCU_RST, 0);
-}
-
-void sensor_board_proc_double_tap(void)
-{
-	lightbar_sequence(LIGHTBAR_TAP);
-}
-
-const int usb_port_enable[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT] = {
-	GPIO_USB1_ENABLE,
-	GPIO_USB2_ENABLE,
-};
-
-/* Base Sensor mutex */
-static struct mutex g_base_mutex;
-
-/* Lid Sensor mutex */
-static struct mutex g_lid_mutex;
-
-/* kxcj9 local/private data */
-struct kionix_accel_data g_kxcj9_data;
-
-/* lsm6ds0 local sensor data (per-sensor) */
-struct lsm6ds0_data g_saved_data[2];
-
-/* Four Motion sensors */
-/* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{FLOAT_TO_FP(-1),  0,  0},
-	{ 0, FLOAT_TO_FP(-1),  0},
-	{ 0,  0, FLOAT_TO_FP(-1)}
-};
-
-const mat33_fp_t lid_standard_ref = {
-	{ 0,  FLOAT_TO_FP(1),  0},
-	{FLOAT_TO_FP(-1),  0,  0},
-	{ 0,  0, FLOAT_TO_FP(-1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	/*
-	 * Note: lsm6ds0: supports accelerometer and gyro sensor
-	 * Requirement: accelerometer sensor must init before gyro sensor
-	 * DO NOT change the order of the following table.
-	 */
-	{.name = "Base",
-	 .active_mask = SENSOR_ACTIVE_S0_S3_S5,
-	 .chip = MOTIONSENSE_CHIP_LSM6DS0,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &lsm6ds0_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_saved_data[0],
-	 .port = I2C_PORT_ACCEL,
-	 .i2c_spi_addr_flags = LSM6DS0_ADDR1_FLAGS,
-	 .rot_standard_ref = &base_standard_ref,
-	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	 .min_frequency = LSM6DS0_ACCEL_MIN_FREQ,
-	 .max_frequency = LSM6DS0_ACCEL_MAX_FREQ,
-	 .config = {
-		 /* EC use accel for angle detection */
-		 [SENSOR_CONFIG_EC_S0] = {
-			 .odr = 119000 | ROUND_UP_FLAG,
-			 .ec_rate = 100 * MSEC,
-		 },
-		 /* Used for double tap */
-		 [SENSOR_CONFIG_EC_S3] = {
-			 .odr = TAP_ODR_LSM6DS0 | ROUND_UP_FLAG,
-			 .ec_rate = CONFIG_GESTURE_SAMPLING_INTERVAL_MS * MSEC,
-		 },
-		 [SENSOR_CONFIG_EC_S5] = {
-			 .odr = TAP_ODR_LSM6DS0 | ROUND_UP_FLAG,
-			 .ec_rate = CONFIG_GESTURE_SAMPLING_INTERVAL_MS * MSEC,
-		 },
-	 },
-	},
-
-	{.name = "Lid",
-	 .active_mask = SENSOR_ACTIVE_S0,
-	 .chip = MOTIONSENSE_CHIP_KXCJ9,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &kionix_accel_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_kxcj9_data,
-	 .port = I2C_PORT_ACCEL,
-	 .i2c_spi_addr_flags = KXCJ9_ADDR0_FLAGS,
-	 .rot_standard_ref = &lid_standard_ref,
-	 .default_range = 2,  /* g, to support lid angle calculation. */
-	 .min_frequency = KXCJ9_ACCEL_MIN_FREQ,
-	 .max_frequency = KXCJ9_ACCEL_MAX_FREQ,
-	 .config = {
-		 /* EC use accel for angle detection */
-		 [SENSOR_CONFIG_EC_S0] = {
-			 .odr = 100000 | ROUND_UP_FLAG,
-			 .ec_rate = 100 * MSEC,
-		 },
-	 },
-	},
-
-	{.name = "Base Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3_S5,
-	 .chip = MOTIONSENSE_CHIP_LSM6DS0,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &lsm6ds0_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_saved_data[1],
-	 .port = I2C_PORT_ACCEL,
-	 .i2c_spi_addr_flags = LSM6DS0_ADDR1_FLAGS,
-	 .rot_standard_ref = NULL,
-	 .default_range = 2000,  /* dps, enough for laptop. */
-	 .min_frequency = LSM6DS0_GYRO_MIN_FREQ,
-	 .max_frequency = LSM6DS0_GYRO_MAX_FREQ,
-	},
-
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-#ifdef CONFIG_LOW_POWER_IDLE
-void jtag_interrupt(enum gpio_signal signal)
-{
-	/*
-	 * This interrupt is the first sign someone is trying to use
-	 * the JTAG. Disable slow speed sleep so that the JTAG action
-	 * can take place.
-	 */
-	disable_sleep(SLEEP_MASK_JTAG);
-
-	/*
-	 * Once we get this interrupt, disable it from occurring again
-	 * to avoid repeated interrupts when debugging via JTAG.
-	 */
-	gpio_disable_interrupt(GPIO_JTAG_TCK);
-}
-#endif /* CONFIG_LOW_POWER_IDLE */
-
-
-enum ec_error_list keyboard_scancode_callback(uint16_t *make_code,
-					      int8_t pressed)
-{
-	const uint16_t k = *make_code;
-	static uint8_t s;
-	static const uint16_t a[] = {
-		SCANCODE_UP, SCANCODE_UP, SCANCODE_DOWN, SCANCODE_DOWN,
-		SCANCODE_LEFT, SCANCODE_RIGHT, SCANCODE_LEFT, SCANCODE_RIGHT,
-		SCANCODE_B, SCANCODE_A};
-
-	if (!pressed)
-		return EC_SUCCESS;
-
-	/* Lightbar demo mode: keyboard can fake the battery state */
-	switch (k) {
-	case SCANCODE_UP:
-		demo_battery_level(1);
-		break;
-	case SCANCODE_DOWN:
-		demo_battery_level(-1);
-		break;
-	case SCANCODE_LEFT:
-		demo_is_charging(0);
-		break;
-	case SCANCODE_RIGHT:
-		demo_is_charging(1);
-		break;
-	case SCANCODE_F6:  /* dim */
-		demo_brightness(-1);
-		break;
-	case SCANCODE_F7:  /* bright */
-		demo_brightness(1);
-		break;
-	case SCANCODE_T:
-		demo_tap();
-		break;
-	}
-
-	if (k == a[s])
-		s++;
-	else if (k != a[0])
-		s = 0;
-	else if (s != 2)
-		s = 1;
-
-	if (s == ARRAY_SIZE(a)) {
-		s = 0;
-		lightbar_sequence(LIGHTBAR_KONAMI);
-	}
-	return EC_SUCCESS;
-}
-
-/*
- * Use to define going in to hibernate early if low on battery.
- * HIBERNATE_BATT_PCT specifies the low battery threshold
- * for going into hibernate early, and HIBERNATE_BATT_SEC defines
- * the minimum amount of time to stay in G3 before checking for low
- * battery hibernate.
- */
-#define HIBERNATE_BATT_PCT 10
-#define HIBERNATE_BATT_SEC (3600 * 24)
-
-__override enum critical_shutdown board_system_is_idle(
-		uint64_t last_shutdown_time, uint64_t *target, uint64_t now)
-{
-	if (charge_get_percent() <= HIBERNATE_BATT_PCT) {
-		uint64_t t = last_shutdown_time + HIBERNATE_BATT_SEC * SEC_UL;
-		*target = MIN(*target, t);
-	}
-	return now > *target ?
-			CRITICAL_SHUTDOWN_HIBERNATE : CRITICAL_SHUTDOWN_IGNORE;
-}
diff --git a/board/samus/board.h b/board/samus/board.h
deleted file mode 100644
index 1e3154c2e3..0000000000
--- a/board/samus/board.h
+++ /dev/null
@@ -1,227 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Configuration for Samus mainboard */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Debug features */
-#define CONFIG_CONSOLE_CMDHELP
-#define CONFIG_TASK_PROFILING
-
-#undef HEY_USE_BUILTIN_CLKRUN
-
-/* Optional features */
-#define CONFIG_ACCELGYRO_LSM6DS0
-#define CONFIG_ACCEL_KXCJ9
-#define CONFIG_ACCEL_STD_REF_FRAME_OLD
-#define CONFIG_ALS_ISL29035
-#define CONFIG_BOARD_VERSION_GPIO
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-#undef  CONFIG_BATTERY_CRITICAL_SHUTDOWN_TIMEOUT
-#define CONFIG_BATTERY_CRITICAL_SHUTDOWN_TIMEOUT 60
-#define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_POWER_COMMON
-#define CONFIG_POWER_SHUTDOWN_PAUSE_IN_S5
-#define CONFIG_CHIPSET_CAN_THROTTLE
-#define CONFIG_I2C
-#define CONFIG_I2C_MASTER
-#define CONFIG_KEYBOARD_BOARD_CONFIG
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-#define CONFIG_KEYBOARD_COL2_INVERTED
-#define CONFIG_KEYBOARD_SCANCODE_CALLBACK
-#define CONFIG_LID_ANGLE
-#define CONFIG_LIGHTBAR_POWER_RAILS
-#define CONFIG_LOW_POWER_IDLE
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_X86
-/* Note: not CONFIG_BACKLIGHT_LID. It's handled specially for Samus. */
-#define CONFIG_BACKLIGHT_REQ_GPIO GPIO_PCH_BL_EN
-/* TODO(crosbug.com/p/29467): remove this workaround when possible. */
-#define CONFIG_BATTERY_REQUESTS_NIL_WHEN_DEAD
-#define CONFIG_CHARGER_PROFILE_OVERRIDE
-#define CONFIG_BATTERY_SMART
-#define CONFIG_BATTERY_REVIVE_DISCONNECT
-#define CONFIG_CHARGER
-#define CONFIG_CHARGER_BQ24773
-#define CONFIG_CHARGER_ILIM_PIN_DISABLED
-#define CONFIG_CHARGER_SENSE_RESISTOR 5
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
-#define CONFIG_CHARGER_INPUT_CURRENT 320
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_DISCHARGE_ON_AC_CUSTOM
-#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 1
-#define CONFIG_FANS 2
-#define CONFIG_FAN_UPDATE_PERIOD 10
-#define CONFIG_FPU
-#define CONFIG_GESTURE_DETECTION
-#define CONFIG_GESTURE_SW_DETECTION
-#define CONFIG_GESTURE_SAMPLING_INTERVAL_MS 5
-#undef  CONFIG_HIBERNATE_DELAY_SEC
-#define CONFIG_HIBERNATE_DELAY_SEC (3600 * 24 * 7)
-#define CONFIG_HOSTCMD_PD
-#define CONFIG_HOSTCMD_PD_CHG_CTRL
-#define CONFIG_HOSTCMD_PD_PANIC
-#define CONFIG_PECI_TJMAX 105
-#define CONFIG_PWM
-#define CONFIG_PWM_KBLIGHT
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_TEMP_SENSOR_TMP006
-#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_PP3300_DSW_GATED_EN
-#define CONFIG_THROTTLE_AP
-#define CONFIG_UART_HOST 2
-#define CONFIG_USB_PORT_POWER_SMART
-#define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_CDP
-#define CONFIG_USB_PORT_POWER_SMART_INVERTED
-#define GPIO_USB1_ILIM_SEL GPIO_USB1_ILIM_SEL_L
-#define GPIO_USB2_ILIM_SEL GPIO_USB2_ILIM_SEL_L
-#define CONFIG_VBOOT_HASH
-#define CONFIG_WIRELESS
-#define CONFIG_WIRELESS_SUSPEND \
-	(EC_WIRELESS_SWITCH_WLAN | EC_WIRELESS_SWITCH_WLAN_POWER)
-/* Do we want EC_WIRELESS_SWITCH_WWAN as well? */
-
-#ifndef __ASSEMBLER__
-
-/* I2C ports */
-#define I2C_PORT_BACKLIGHT 0
-#define I2C_PORT_BATTERY 0
-#define I2C_PORT_CHARGER 0
-#define I2C_PORT_PD_MCU 0
-#define I2C_PORT_ALS 1
-#define I2C_PORT_ACCEL 1
-#define I2C_PORT_LIGHTBAR 1
-#define I2C_PORT_THERMAL 5
-
-/* 13x8 keyboard scanner uses an entire GPIO bank for row inputs */
-#define KB_SCAN_ROW_IRQ  LM4_IRQ_GPIOK
-#define KB_SCAN_ROW_GPIO LM4_GPIO_K
-
-/* Host connects to keyboard controller module via LPC */
-#define HOST_KB_BUS_LPC
-
-/* USB ports managed by the EC */
-#define USB_PORT_COUNT 2
-
-#include "gpio_signal.h"
-
-/* x86 signal definitions */
-enum x86_signal {
-	X86_PGOOD_PP1050 = 0,
-	X86_PGOOD_PP1200,
-	X86_PGOOD_PP1800,
-	X86_PGOOD_VCORE,
-
-	X86_SLP_S0_DEASSERTED,
-	X86_SLP_S3_DEASSERTED,
-	X86_SLP_S5_DEASSERTED,
-	X86_SLP_SUS_DEASSERTED,
-	X86_SUSWARN_DEASSERTED,
-
-	/* Number of X86 signals */
-	POWER_SIGNAL_COUNT
-};
-
-enum adc_channel {
-	/* EC internal die temperature in degrees K. */
-	ADC_CH_EC_TEMP = 0,
-	/* BAT_TEMP */
-	ADC_CH_BAT_TEMP,
-
-	ADC_CH_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-
-	/* Number of PWM channels */
-	PWM_CH_COUNT
-};
-
-enum temp_sensor_id {
-	/* CPU die temperature via PECI */
-	TEMP_SENSOR_CPU_PECI,
-	/* EC internal temperature sensor */
-	TEMP_SENSOR_EC_INTERNAL,
-	/* TMP006 U40, die/object temperature near battery charger */
-	TEMP_SENSOR_I2C_U40_DIE,
-	TEMP_SENSOR_I2C_U40_OBJECT,
-	/* TMP006 U41, die/object temperature near CPU */
-	TEMP_SENSOR_I2C_U41_DIE,
-	TEMP_SENSOR_I2C_U41_OBJECT,
-	/* TMP006 U42, die/object temperature left side of C-case */
-	TEMP_SENSOR_I2C_U42_DIE,
-	TEMP_SENSOR_I2C_U42_OBJECT,
-	/* TMP006 U43, die/object temperature right side of C-case */
-	TEMP_SENSOR_I2C_U43_DIE,
-	TEMP_SENSOR_I2C_U43_OBJECT,
-	/* TMP006 U115, die/object temperature right side of D-case */
-	TEMP_SENSOR_I2C_U115_DIE,
-	TEMP_SENSOR_I2C_U115_OBJECT,
-	/* TMP006 U116, die/object temperature left side of D-case */
-	TEMP_SENSOR_I2C_U116_DIE,
-	TEMP_SENSOR_I2C_U116_OBJECT,
-
-	/* Battery temperature sensor */
-	TEMP_SENSOR_BATTERY,
-
-	TEMP_SENSOR_COUNT
-};
-
-enum sensor_id {
-	BASE_ACCEL,
-	LID_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT,
-};
-
-/* The number of TMP006 sensor chips on the board. */
-#define TMP006_COUNT 6
-
-/* Light sensors attached to the EC. */
-enum als_id {
-	ALS_ISL29035 = 0,
-
-	ALS_COUNT,
-};
-
-/* Wireless signals */
-#define WIRELESS_GPIO_WLAN GPIO_WLAN_OFF_L
-#define WIRELESS_GPIO_WLAN_POWER GPIO_PP3300_WLAN_EN
-
-/* Discharge battery when on AC power for factory test. */
-int board_is_discharging_on_ac(void);
-
-/* Reset PD MCU */
-void board_reset_pd_mcu(void);
-
-/* Backboost detected interrupt */
-void bkboost_det_interrupt(enum gpio_signal signal);
-
-/* Interrupt handler for JTAG clock */
-void jtag_interrupt(enum gpio_signal signal);
-
-/* Bit masks for turning on PP5000 rail in G3 */
-#define PP5000_IN_G3_AC       BIT(0)
-#define PP5000_IN_G3_LIGHTBAR BIT(1)
-
-/* Enable/disable PP5000 rail mask in G3 */
-void set_pp5000_in_g3(int mask, int enable);
-
-/* Define for sensor tasks */
-#define CONFIG_GESTURE_SENSOR_DOUBLE_TAP 0
-#define CONFIG_GESTURE_TAP_OUTER_WINDOW_T 200
-#define CONFIG_GESTURE_TAP_INNER_WINDOW_T 30
-#define CONFIG_GESTURE_TAP_MIN_INTERSTICE_T 120
-#define CONFIG_GESTURE_TAP_MAX_INTERSTICE_T 500
-
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/samus/build.mk b/board/samus/build.mk
deleted file mode 100644
index 183605fc62..0000000000
--- a/board/samus/build.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-# -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-# the IC is TI Stellaris LM4
-CHIP:=lm4
-
-# Samus has board-specific chipset code, and the tests don't
-# compile with it. Disable them for now.
-test-list-y=
-
-board-y=battery.o board.o power_sequence.o panel.o extpower.o
diff --git a/board/samus/ec.tasklist b/board/samus/ec.tasklist
deleted file mode 100644
index 345892a64b..0000000000
--- a/board/samus/ec.tasklist
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(ALS, als_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(LIGHTBAR, lightbar_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(EXTPOWER, extpower_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(MOTIONSENSE, motion_sense_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(PDCMD, pd_command_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE)
diff --git a/board/samus/extpower.c b/board/samus/extpower.c
deleted file mode 100644
index c6a7424fca..0000000000
--- a/board/samus/extpower.c
+++ /dev/null
@@ -1,433 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Pure GPIO-based external power detection, buffered to PCH.
- * Drive high in S5-S0 when AC_PRESENT is high, otherwise drive low.
- */
-
-#include "bq24773.h"
-#include "charge_state.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-
-/* Max number of attempts to enable/disable NVDC charger */
-#define CHARGER_MODE_ATTEMPTS 3
-
-/* Backboost has been detected */
-static int bkboost_detected;
-
-/* Charging is disabled */
-static int charge_is_disabled;
-
-/* Extpower task has been initialized */
-static int extpower_task_initialized;
-
-/*
- * Charge circuit occasionally gets wedged and doesn't charge.
- * This variable keeps track of the state of the circuit.
- */
-static enum {
-	CHARGE_CIRCUIT_OK,
-	CHARGE_CIRCUIT_WEDGED,
-} charge_circuit_state = CHARGE_CIRCUIT_OK;
-
-int extpower_is_present(void)
-{
-	return gpio_get_level(GPIO_AC_PRESENT);
-}
-
-static void extpower_buffer_to_pch(void)
-{
-	if (chipset_in_state(CHIPSET_STATE_HARD_OFF)) {
-		/* Drive low in G3 state */
-		gpio_set_level(GPIO_PCH_ACOK, 0);
-	} else {
-		/* Buffer from extpower in S5+ (where 3.3DSW enabled) */
-		gpio_set_level(GPIO_PCH_ACOK, extpower_is_present());
-	}
-}
-DECLARE_HOOK(HOOK_CHIPSET_PRE_INIT, extpower_buffer_to_pch, HOOK_PRIO_DEFAULT);
-
-static void extpower_shutdown(void)
-{
-	/* Drive ACOK buffer to PCH low when shutting down */
-	gpio_set_level(GPIO_PCH_ACOK, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, extpower_shutdown, HOOK_PRIO_DEFAULT);
-
-void extpower_interrupt(enum gpio_signal signal)
-{
-	/* Trigger notification of external power change */
-	extpower_buffer_to_pch();
-
-	/* Wake extpower task only if task has been initialized */
-	if (extpower_task_initialized)
-		task_wake(TASK_ID_EXTPOWER);
-}
-
-static void extpower_init(void)
-{
-	extpower_buffer_to_pch();
-
-	/* Enable interrupts, now that we've initialized */
-	gpio_enable_interrupt(GPIO_AC_PRESENT);
-}
-DECLARE_HOOK(HOOK_INIT, extpower_init, HOOK_PRIO_DEFAULT);
-
-/*
- * Save power in S3/S5/G3 by disabling charging when the battery is
- * full. Restore charging when battery is not full anymore. This saves
- * power because our input AC path is inefficient.
- */
-
-static void check_charging_cutoff(void)
-{
-	/* If battery is full disable charging */
-	if (charge_get_percent() == 100) {
-		charge_is_disabled = 1;
-		host_command_pd_send_status(PD_CHARGE_NONE);
-	}
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, check_charging_cutoff, HOOK_PRIO_DEFAULT);
-
-static void cancel_charging_cutoff(void)
-{
-	/* If charging is disabled, enable it */
-	if (charge_is_disabled) {
-		charge_is_disabled = 0;
-		host_command_pd_send_status(PD_CHARGE_5V);
-	}
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, cancel_charging_cutoff, HOOK_PRIO_DEFAULT);
-
-static void batt_soc_change(void)
-{
-	/* If in S0, leave charging alone */
-	if (chipset_in_state(CHIPSET_STATE_ON)) {
-		host_command_pd_send_status(PD_CHARGE_NO_CHANGE);
-		return;
-	}
-
-	/* Check to disable or enable charging based on batt state of charge */
-	if (!charge_is_disabled && charge_get_percent() == 100) {
-		host_command_pd_send_status(PD_CHARGE_NONE);
-		charge_is_disabled = 1;
-	} else if (charge_is_disabled && charge_get_percent() < 100) {
-		charge_is_disabled = 0;
-		host_command_pd_send_status(PD_CHARGE_5V);
-	} else {
-		/* Leave charging alone, but update battery SOC */
-		host_command_pd_send_status(PD_CHARGE_NO_CHANGE);
-	}
-}
-DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, batt_soc_change, HOOK_PRIO_DEFAULT);
-
-/**
- * Enable/disable NVDC charger to control AC to system and battery.
- */
-static void charger_disable(int disable)
-{
-	int i, rv;
-
-	for (i = 0; i < CHARGER_MODE_ATTEMPTS; i++) {
-		rv = charger_discharge_on_ac(disable);
-		if (rv == EC_SUCCESS)
-			return;
-	}
-
-	CPRINTS("Setting learn mode %d failed!", disable);
-}
-
-static void allow_max_request(void)
-{
-	int prochot_status;
-	if (charge_circuit_state == CHARGE_CIRCUIT_WEDGED) {
-		/* Read PROCHOT status register to clear it */
-		i2c_read8(I2C_PORT_CHARGER, BQ24773_ADDR_FLAGS,
-			  BQ24773_PROCHOT_STATUS, &prochot_status);
-		charge_circuit_state = CHARGE_CIRCUIT_OK;
-	}
-	host_command_pd_send_status(PD_CHARGE_MAX);
-}
-DECLARE_DEFERRED(allow_max_request);
-
-static void allow_min_charging(void)
-{
-	if (!charge_is_disabled && charge_circuit_state == CHARGE_CIRCUIT_OK)
-		host_command_pd_send_status(PD_CHARGE_5V);
-}
-DECLARE_DEFERRED(allow_min_charging);
-
-static void extpower_board_hacks(int extpower, int extpower_prev)
-{
-	/* Cancel deferred attempt to enable max charge request */
-	hook_call_deferred(&allow_max_request_data, -1);
-
-	/*
-	 * When AC is detected, delay briefly before allowing PD
-	 * to negotiate up to the max voltage to give charge circuit
-	 * time to settle down. When AC goes away, disable charging
-	 * for a brief time, allowing charge state machine time to
-	 * see AC has gone away, and then set PD to only allow
-	 * 5V charging for the next time AC is connected.
-	 *
-	 * Use NVDC charger learn mode (charger_disable()) when AC
-	 * is not present to avoid backboosting when AC is plugged in.
-	 *
-	 * When in G3, PP5000 needs to be enabled to accurately sense
-	 * CC voltage when AC is attached. When AC is disconnceted
-	 * it needs to be off to save power.
-	 */
-	if (extpower && !extpower_prev) {
-		/* AC connected */
-		charger_disable(0);
-		hook_call_deferred(&allow_max_request_data, 500*MSEC);
-		set_pp5000_in_g3(PP5000_IN_G3_AC, 1);
-	} else if (extpower && extpower_prev) {
-		/*
-		 * Glitch on AC_PRESENT, attempt to recover from
-		 * backboost
-		 */
-		host_command_pd_send_status(PD_CHARGE_NONE);
-	} else {
-		/* AC disconnected */
-		if (!charge_is_disabled &&
-		    charge_circuit_state == CHARGE_CIRCUIT_OK)
-			host_command_pd_send_status(PD_CHARGE_NONE);
-
-		charger_disable(1);
-
-		hook_call_deferred(&allow_min_charging_data, 100*MSEC);
-		set_pp5000_in_g3(PP5000_IN_G3_AC, 0);
-	}
-	extpower_prev = extpower;
-}
-
-/* Return boostin_voltage or negative if error */
-static int get_boostin_voltage(void)
-{
-	/* Static structs to save stack space */
-	static struct ec_response_usb_pd_power_info pd_power_ret;
-	static struct ec_params_usb_pd_power_info pd_power_args;
-	int ret;
-	int err;
-
-	/* Boost-in voltage is maximum of voltage now on each port */
-	pd_power_args.port = 0;
-	err = pd_host_command(EC_CMD_USB_PD_POWER_INFO, 0,
-			      &pd_power_args,
-			      sizeof(struct ec_params_usb_pd_power_info),
-			      &pd_power_ret,
-			      sizeof(struct ec_response_usb_pd_power_info));
-	if (err < 0)
-		return err;
-	ret = pd_power_ret.meas.voltage_now;
-
-	pd_power_args.port = 1;
-	err = pd_host_command(EC_CMD_USB_PD_POWER_INFO, 0,
-			      &pd_power_args,
-			      sizeof(struct ec_params_usb_pd_power_info),
-			      &pd_power_ret,
-			      sizeof(struct ec_response_usb_pd_power_info));
-	if (err < 0)
-		return err;
-
-	/* Get max of two measuremente */
-	if (pd_power_ret.meas.voltage_now > ret)
-		ret = pd_power_ret.meas.voltage_now;
-
-	return ret;
-}
-
-/*
- * Send command to PD to write a custom persistent log entry indicating that
- * charging was wedged. Returns pd_host_command success status.
- */
-static int log_charge_wedged(void)
-{
-	static struct ec_params_pd_write_log_entry log_args;
-
-	log_args.type = PD_EVENT_MCU_BOARD_CUSTOM;
-	log_args.port = 0;
-
-	return pd_host_command(EC_CMD_PD_WRITE_LOG_ENTRY, 0,
-			       &log_args,
-			       sizeof(struct ec_params_pd_write_log_entry),
-			       NULL, 0);
-}
-
-/* Time interval between checking if charge circuit is wedged */
-#define CHARGE_WEDGE_CHECK_INTERVAL (2*SECOND)
-
-/*
- * Number of iterations through check_charge_wedged() with charging stalled
- * before attempting unwedge.
- */
-#define CHARGE_STALLED_COUNT 5
-/*
- * Number of iterations through check_charge_wedged() with charging stalled
- * after we already just tried unwedging the circuit, before we try again.
- */
-#define CHARGE_STALLED_REPEATEDLY_COUNT 60
-
-/*
- * Minimum number of iterations through check_charge_wedged() between
- * unwedge attempts.
- */
-#define MIN_COUNTS_BETWEEN_UNWEDGES 3
-
-static void check_charge_wedged(void)
-{
-	int rv, prochot_status, batt_discharging_on_ac, boostin_voltage = 0;
-	static int counts_since_wedged;
-	static int charge_stalled_count = CHARGE_STALLED_COUNT;
-	uint8_t *batt_flags = host_get_memmap(EC_MEMMAP_BATT_FLAG);
-
-	if (charge_circuit_state == CHARGE_CIRCUIT_OK) {
-		/* Check PROCHOT warning */
-		rv = i2c_read8(I2C_PORT_CHARGER, BQ24773_ADDR_FLAGS,
-			       BQ24773_PROCHOT_STATUS, &prochot_status);
-		if (rv)
-			prochot_status = 0;
-
-		batt_discharging_on_ac =
-			(*batt_flags & EC_BATT_FLAG_AC_PRESENT) &&
-			(*batt_flags & EC_BATT_FLAG_DISCHARGING);
-
-		/*
-		 * If PROCHOT is set or we are discharging on AC, then we
-		 * need to know boostin_voltage.
-		 */
-		if (prochot_status || batt_discharging_on_ac)
-			boostin_voltage = get_boostin_voltage();
-
-		/*
-		 * If AC is present, and battery is discharging, and
-		 * boostin voltage is above 5V, then we might be wedged.
-		 */
-		if (batt_discharging_on_ac) {
-			if (boostin_voltage > 6000)
-				charge_stalled_count--;
-			else if (boostin_voltage >= 0)
-				charge_stalled_count = CHARGE_STALLED_COUNT;
-			/* If boostin_voltage < 0, don't change stalled count */
-		} else {
-			charge_stalled_count = CHARGE_STALLED_COUNT;
-		}
-
-		/*
-		 * If we were recently wedged, then give ourselves a free pass
-		 * here. This gives an opportunity for reading the PROCHOT
-		 * status to clear it if the error has gone away.
-		 */
-		if (counts_since_wedged < MIN_COUNTS_BETWEEN_UNWEDGES)
-			counts_since_wedged++;
-
-		/*
-		 * If PROCHOT is asserted AND boost_in voltage is above 5V,
-		 * then charge circuit is wedged. If charging has been stalled
-		 * long enough, then also consider the circuit wedged.
-		 *
-		 * To unwedge the charge circuit turn on learn mode and notify
-		 * PD to disable charging on all ports.
-		 * Note: learn mode is critical here because when in this state
-		 * backboosting causes >20V on boostin even after PD disables
-		 * CHARGE_EN lines.
-		 */
-		if ((prochot_status && boostin_voltage > 6000 &&
-			counts_since_wedged >= MIN_COUNTS_BETWEEN_UNWEDGES) ||
-		    charge_stalled_count <= 0) {
-			counts_since_wedged = 0;
-			host_command_pd_send_status(PD_CHARGE_NONE);
-			charger_disable(1);
-			charge_circuit_state = CHARGE_CIRCUIT_WEDGED;
-			log_charge_wedged();
-			CPRINTS("Charge wedged! PROCHOT %02x, Stalled: %d",
-				prochot_status, charge_stalled_count);
-
-			/*
-			 * If this doesn't clear the problem, then start
-			 * the stall counter higher so that we don't retry
-			 * unwedging for a while. Note, if we do start charging
-			 * properly, then stall counter will be set to
-			 * default, so that we will trigger faster the first
-			 * time it stalls out.
-			 */
-			charge_stalled_count = CHARGE_STALLED_REPEATEDLY_COUNT;
-		}
-	} else {
-		/*
-		 * Charge circuit is wedged and we already disabled charging,
-		 * Now start to recover from wedged state by allowing 5V.
-		 */
-		host_command_pd_send_status(PD_CHARGE_5V);
-	}
-}
-
-/**
- * Task to handle external power change
- */
-void extpower_task(void)
-{
-	int extpower = extpower_is_present();
-	int extpower_prev = 0;
-
-	extpower_board_hacks(extpower, extpower_prev);
-	extpower_prev = extpower;
-	extpower_task_initialized = 1;
-
-	/* Enable backboost detection interrupt */
-	gpio_enable_interrupt(GPIO_BKBOOST_DET);
-
-	while (1) {
-		if (task_wait_event(CHARGE_WEDGE_CHECK_INTERVAL) ==
-		    TASK_EVENT_TIMER) {
-			/*
-			 * If we are NOT purposely discharging on AC, then
-			 * periodically check if charge circuit is wedged.
-			 */
-			if (!board_is_discharging_on_ac())
-				check_charge_wedged();
-		} else {
-			/* Must have received power change interrupt */
-			extpower = extpower_is_present();
-
-			/* Various board hacks to run on extpower change */
-			extpower_board_hacks(extpower, extpower_prev);
-			extpower_prev = extpower;
-
-			extpower_handle_update(extpower);
-		}
-	}
-}
-
-void bkboost_det_interrupt(enum gpio_signal signal)
-{
-	/* Backboost has been detected, save it, and disable interrupt */
-	bkboost_detected = 1;
-	gpio_disable_interrupt(GPIO_BKBOOST_DET);
-}
-
-static int command_backboost_det(int argc, char **argv)
-{
-	ccprintf("Backboost detected: %d\n", bkboost_detected);
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(bkboost, command_backboost_det, NULL,
-			"Read backboost detection");
diff --git a/board/samus/gpio.inc b/board/samus/gpio.inc
deleted file mode 100644
index 1b49c58bd0..0000000000
--- a/board/samus/gpio.inc
+++ /dev/null
@@ -1,122 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-GPIO_INT(POWER_BUTTON_L, PIN(A, 2), GPIO_INT_BOTH_DSLEEP,                power_button_interrupt)   /* Power button */
-GPIO_INT(LID_OPEN,       PIN(A, 3), GPIO_INT_BOTH_DSLEEP,                lid_interrupt)            /* Lid switch */
-GPIO_INT(AC_PRESENT,     PIN(H, 3), GPIO_INT_BOTH_DSLEEP,                extpower_interrupt)       /* AC power present */
-GPIO_INT(PCH_SLP_S0_L,   PIN(G, 6), GPIO_INT_BOTH,                       power_signal_interrupt)   /* SLP_S0# signal from PCH */
-GPIO_INT(PCH_SLP_S3_L,   PIN(G, 7), GPIO_INT_BOTH_DSLEEP,                power_signal_interrupt)   /* SLP_S3# signal from PCH */
-GPIO_INT(PCH_SLP_S5_L,   PIN(H, 1), GPIO_INT_BOTH_DSLEEP,                power_signal_interrupt)   /* SLP_S5# signal from PCH */
-GPIO_INT(PCH_SLP_SUS_L,  PIN(G, 3), GPIO_INT_BOTH,                       power_signal_interrupt)   /* SLP_SUS# signal from PCH */
-GPIO_INT(PCH_SUSWARN_L,  PIN(G, 2), GPIO_INT_BOTH,                       power_signal_interrupt)   /* SUSWARN# signal from PCH */
-GPIO_INT(PP1050_PGOOD,   PIN(H, 4), GPIO_INT_BOTH,                       power_signal_interrupt)   /* Power good on 1.05V */
-GPIO_INT(PP1200_PGOOD,   PIN(H, 6), GPIO_INT_BOTH,                       power_signal_interrupt)   /* Power good on 1.2V (DRAM) */
-GPIO_INT(PP1800_PGOOD,   PIN(L, 7), GPIO_INT_BOTH,                       power_signal_interrupt)   /* Power good on 1.8V (DRAM) */
-GPIO_INT(VCORE_PGOOD,    PIN(C, 6), GPIO_INT_BOTH,                       power_signal_interrupt)   /* Power good on core VR */
-GPIO_INT(WP_L,           PIN(A, 4), GPIO_INT_BOTH,                       switch_interrupt)         /* Write protect input */
-GPIO_INT(PCH_BL_EN,      PIN(M, 3), GPIO_INT_RISING,                     backlight_interrupt)      /* PCH backlight input */
-GPIO_INT(JTAG_TCK,       PIN(C, 0), GPIO_DEFAULT,                        jtag_interrupt)           /* JTAG clock input */
-GPIO_INT(UART0_RX,       PIN(A, 0), GPIO_PULL_UP | GPIO_INT_BOTH_DSLEEP, uart_deepsleep_interrupt) /* UART0 RX input */
-GPIO_INT(BKBOOST_DET,    PIN(B, 5), GPIO_INT_RISING,                     bkboost_det_interrupt)    /* Backboost detect */
-
-/* Interrupt signal from PD MCU, external pull-down */
-GPIO_INT(PD_MCU_INT, PIN(J, 5), GPIO_INT_RISING | GPIO_INT_DSLEEP, pd_mcu_interrupt)
-
-/*
- * Combined accelerometer input. This will become an interrupt, once we have
- * support for it.
- */
-GPIO(ACCEL_INT, PIN(F, 7), GPIO_INPUT)
-
-/*
- * Ambient Light Sensor input.  This could become an interrupt once supported.
- */
-GPIO(ALS_INT_L, PIN(N, 0), GPIO_INPUT)
-
-/* Other inputs */
-GPIO(BOARD_VERSION1, PIN(Q, 7), GPIO_INPUT) /* Board version stuffing resistor 1 */
-GPIO(BOARD_VERSION2, PIN(Q, 6), GPIO_INPUT) /* Board version stuffing resistor 2 */
-GPIO(BOARD_VERSION3, PIN(Q, 5), GPIO_INPUT) /* Board version stuffing resistor 3 */
-GPIO(USB1_OC_L,      PIN(E, 7), GPIO_INPUT) /* USB port overcurrent warning */
-GPIO(USB1_STATUS_L,  PIN(E, 6), GPIO_INPUT) /* USB charger port 1 status output */
-GPIO(USB2_OC_L,      PIN(E, 0), GPIO_INPUT) /* USB port overcurrent warning */
-GPIO(USB2_STATUS_L,  PIN(D, 7), GPIO_INPUT) /* USB charger port 2 status output */
-GPIO(PD_IN_RW,       PIN(A, 5), GPIO_INPUT) /* PD is in RW */
-GPIO(PCH_HDA_SDO_L,  PIN(G, 1), GPIO_INPUT) /* HDA_SDO signal to PCH to disable ME */
-
-/* Outputs; all unasserted by default except for reset signals */
-GPIO(CPU_PROCHOT,         PIN(B, 1), GPIO_OUT_LOW)  /* Force CPU to think it's overheated */
-GPIO(PP1200_EN,           PIN(H, 5), GPIO_OUT_LOW)  /* Enable 1.20V supply */
-GPIO(PP3300_DSW_EN,       PIN(F, 6), GPIO_OUT_LOW)  /* Enable 3.3V DSW rail */
-GPIO(PP3300_DSW_GATED_EN, PIN(J, 3), GPIO_OUT_LOW)  /* Enable 3.3V Gated DSW and core VDD */
-GPIO(PP3300_LTE_EN,       PIN(D, 2), GPIO_OUT_LOW)  /* Enable LTE radio */
-GPIO(PP3300_WLAN_EN,      PIN(J, 0), GPIO_OUT_LOW)  /* Enable WiFi power */
-GPIO(PP1050_EN,           PIN(C, 7), GPIO_OUT_LOW)  /* Enable 1.05V regulator */
-GPIO(PP5000_USB_EN,       PIN(C, 5), GPIO_OUT_LOW)  /* Enable USB power */
-GPIO(PP5000_EN,           PIN(H, 7), GPIO_OUT_LOW)  /* Enable 5V supply */
-GPIO(PP1800_EN,           PIN(L, 6), GPIO_OUT_LOW)  /* Enable 1.8V supply */
-GPIO(SYS_PWROK,           PIN(H, 2), GPIO_OUT_LOW)  /* EC thinks everything is up and ready */
-GPIO(WLAN_OFF_L,          PIN(J, 4), GPIO_OUT_LOW)  /* Disable WiFi radio */
-GPIO(USB_MCU_RST,         PIN(B, 0), GPIO_OUT_LOW)  /* USB PD MCU reset */
-GPIO(ENABLE_BACKLIGHT,    PIN(M, 7), GPIO_OUT_LOW)  /* Enable backlight power */
-GPIO(ENABLE_TOUCHPAD,     PIN(N, 1), GPIO_OUT_LOW)  /* Enable touchpad power */
-GPIO(ENTERING_RW,         PIN(D, 3), GPIO_OUT_LOW)  /* Indicate when EC is entering RW code */
-GPIO(LIGHTBAR_RESET_L,    PIN(J, 2), GPIO_ODR_LOW)  /* Reset lightbar controllers */
-GPIO(PCH_DPWROK,          PIN(G, 0), GPIO_OUT_LOW)  /* Indicate when VccDSW is good */
-GPIO(PCH_RSMRST_L,        PIN(C, 4), GPIO_OUT_LOW)  /* Reset PCH resume power plane logic */
-GPIO(PCH_RTCRST_L,        PIN(J, 1), GPIO_ODR_HIGH) /* Reset PCH RTC well */
-GPIO(PCH_WAKE_L,          PIN(F, 0), GPIO_ODR_HIGH) /* Wake signal from EC to PCH */
-GPIO(PCH_NMI_L,           PIN(F, 2), GPIO_ODR_HIGH) /* Non-maskable interrupt pin to PCH */
-GPIO(PCH_PWRBTN_L,        PIN(H, 0), GPIO_ODR_HIGH) /* Power button output to PCH */
-GPIO(PCH_PWROK,           PIN(F, 5), GPIO_OUT_LOW)  /* PWROK / APWROK signals to PCH */
-GPIO(PCH_RCIN_L,          PIN(F, 3), GPIO_ODR_HIGH) /* RCIN# line to PCH (for 8042 emulation) */
-GPIO(PCH_SYS_RST_L,       PIN(F, 1), GPIO_ODR_HIGH) /* Reset PCH resume power plane logic */
-GPIO(PCH_SMI_L,           PIN(F, 4), GPIO_ODR_HIGH) /* System management interrupt to PCH */
-GPIO(TOUCHSCREEN_RESET_L, PIN(N, 7), GPIO_ODR_LOW)  /* Reset touch screen */
-GPIO(PCH_ACOK,            PIN(M, 6), GPIO_OUT_LOW)  /* AC present signal buffered to PCH */
-#ifndef HEY_USE_BUILTIN_CLKRUN
-GPIO(LPC_CLKRUN_L,        PIN(M, 2), GPIO_ODR_HIGH) /* Dunno. Probably important, though. */
-#endif
-GPIO(USB1_CTL1,           PIN(E, 1), GPIO_OUT_LOW)  /* USB charger port 1 CTL1 output */
-GPIO(USB1_CTL2,           PIN(E, 2), GPIO_OUT_HIGH) /* USB charger port 1 CTL2 output */
-GPIO(USB1_CTL3,           PIN(E, 3), GPIO_OUT_LOW)  /* USB charger port 1 CTL3 output */
-GPIO(USB1_ENABLE,         PIN(E, 4), GPIO_OUT_HIGH) /* USB charger port 1 enable */
-GPIO(USB1_ILIM_SEL_L,     PIN(E, 5), GPIO_OUT_HIGH) /* USB charger port 1 ILIM_SEL output */
-GPIO(USB2_CTL1,           PIN(D, 0), GPIO_OUT_LOW)  /* USB charger port 2 CTL1 output */
-GPIO(USB2_CTL2,           PIN(D, 1), GPIO_OUT_HIGH) /* USB charger port 2 CTL2 output */
-GPIO(USB2_CTL3,           PIN(D, 4), GPIO_OUT_LOW)  /* USB charger port 2 CTL3 output */
-GPIO(USB2_ENABLE,         PIN(D, 5), GPIO_OUT_HIGH) /* USB charger port 2 enable */
-GPIO(USB2_ILIM_SEL_L,     PIN(D, 6), GPIO_OUT_HIGH) /* USB charger port 2 ILIM_SEL output */
-
-GPIO(I2C0_SCL,            PIN(B, 2), GPIO_ODR_HIGH) /* I2C port 0 SCL */
-GPIO(I2C0_SDA,            PIN(B, 3), GPIO_ODR_HIGH) /* I2C port 0 SDA */
-GPIO(I2C1_SCL,            PIN(A, 6), GPIO_ODR_HIGH) /* I2C port 1 SCL */
-GPIO(I2C1_SDA,            PIN(A, 7), GPIO_ODR_HIGH) /* I2C port 1 SDA */
-GPIO(I2C5_SCL,            PIN(B, 6), GPIO_ODR_HIGH) /* I2C port 5 SCL */
-GPIO(I2C5_SDA,            PIN(B, 7), GPIO_ODR_HIGH) /* I2C port 5 SDA */
-
-ALTERNATE(PIN_MASK(A, 0x03), 1,  MODULE_UART, 0)               /* UART0 */
-ALTERNATE(PIN_MASK(A, 0x40), 3,  MODULE_I2C,  0)               /* I2C1 SCL */
-ALTERNATE(PIN_MASK(A, 0x80), 3,  MODULE_I2C,  GPIO_OPEN_DRAIN) /* I2C1 SDA */
-ALTERNATE(PIN_MASK(B, 0x04), 3,  MODULE_I2C,  0)               /* I2C0 SCL */
-ALTERNATE(PIN_MASK(B, 0x08), 3,  MODULE_I2C,  GPIO_OPEN_DRAIN) /* I2C0 SDA */
-ALTERNATE(PIN_MASK(B, 0x40), 3,  MODULE_I2C,  0)               /* I2C5 SCL */
-ALTERNATE(PIN_MASK(B, 0x80), 3,  MODULE_I2C,  GPIO_OPEN_DRAIN) /* I2C5 SDA */
-ALTERNATE(PIN_MASK(G, 0x30), 1,  MODULE_UART, 0)               /* UART2 */
-ALTERNATE(PIN_MASK(J, 0x40), 1,  MODULE_PECI, 0)               /* PECI Tx */
-ALTERNATE(PIN_MASK(J, 0x80), 0,  MODULE_PECI, GPIO_ANALOG)     /* PECI Rx */
-ALTERNATE(PIN_MASK(L, 0x3f), 15, MODULE_LPC,  0)               /* LPC */
-ALTERNATE(PIN_MASK(M, 0x33), 15, MODULE_LPC,  0)               /* LPC */
-#ifdef HEY_USE_BUILTIN_CLKRUN
-ALTERNATE(PIN_MASK(M, 0x04), 15, MODULE_LPC,  GPIO_OPEN_DRAIN) /* LPC */
-#endif
-
-ALTERNATE(PIN_MASK(N, 0x3c), 1,  MODULE_PWM,  0) /* FAN0PWM 2&3 */
-ALTERNATE(PIN_MASK(N, 0x40), 1,  MODULE_PWM,  0) /* FAN0PWM4 */
diff --git a/board/samus/panel.c b/board/samus/panel.c
deleted file mode 100644
index b3fe6060aa..0000000000
--- a/board/samus/panel.c
+++ /dev/null
@@ -1,195 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "lid_switch.h"
-#include "timer.h"
-
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-
-#define I2C_ADDR_BACKLIGHT_FLAGS (0x2C | I2C_FLAG_BIG_ENDIAN)
-#define I2C_RETRIES 3
-#define I2C_RETRY_DELAY (5*MSEC)
-
-#define LP8555_REG_COMMAND           0x00
-#define  LP8555_REG_COMMAND_ON       0x01
-#define LP8555_REG_CONFIG            0x10
-#define  LP8555_REG_CONFIG_MODE_MASK 0x03
-#define  LP8555_REG_CONFIG_MODE_PWM  0x00
-#define LP8555_REG_CURRENT           0x11
-#define  LP8555_REG_CURRENT_MAXCURR_5MA   0x00
-#define  LP8555_REG_CURRENT_MAXCURR_10MA  0x01
-#define  LP8555_REG_CURRENT_MAXCURR_15MA  0x02
-#define  LP8555_REG_CURRENT_MAXCURR_20MA  0x03
-#define  LP8555_REG_CURRENT_MAXCURR_23MA  0x04
-#define  LP8555_REG_CURRENT_MAXCURR_25MA  0x05
-#define  LP8555_REG_CURRENT_MAXCURR_30MA  0x06
-#define  LP8555_REG_CURRENT_MAXCURR_50MA  0x07
-#define LP8555_REG_STEP           0x15
-#define  LP8555_REG_STEP_STEP_0MS           (0 << 0)
-#define  LP8555_REG_STEP_STEP_8MS           BIT(0)
-#define  LP8555_REG_STEP_STEP_16MS          (2 << 0)
-#define  LP8555_REG_STEP_STEP_24MS          (3 << 0)
-#define  LP8555_REG_STEP_STEP_28MS          (4 << 0)
-#define  LP8555_REG_STEP_STEP_32MS          (5 << 0)
-#define  LP8555_REG_STEP_STEP_100MS         (6 << 0)
-#define  LP8555_REG_STEP_STEP_200MS         (7 << 0)
-#define  LP8555_REG_STEP_PWM_IN_HYST_NONE   (0 << 3)
-#define  LP8555_REG_STEP_PWM_IN_HYST_1LSB   BIT(3)
-#define  LP8555_REG_STEP_PWM_IN_HYST_2LSB   (2 << 3)
-#define  LP8555_REG_STEP_PWM_IN_HYST_4LSB   (3 << 3)
-#define  LP8555_REG_STEP_PWM_IN_HYST_8LSB   (4 << 3)
-#define  LP8555_REG_STEP_PWM_IN_HYST_16LSB  (5 << 3)
-#define  LP8555_REG_STEP_PWM_IN_HYST_32LSB  (6 << 3)
-#define  LP8555_REG_STEP_PWM_IN_HYST_64LSB  (7 << 3)
-#define  LP8555_REG_STEP_SMOOTH_NONE        (0 << 6)
-#define  LP8555_REG_STEP_SMOOTH_LIGHT       BIT(6)
-#define  LP8555_REG_STEP_SMOOTH_MEDIUM      (2 << 6)
-#define  LP8555_REG_STEP_SMOOTH_HEAVY       (3 << 6)
-
-/* Read from lp8555 with automatic i2c retries */
-static int lp8555_read_with_retry(int reg, int *data)
-{
-	int i, rv;
-
-	for (i = 0; i < I2C_RETRIES; i++) {
-		rv = i2c_read8(I2C_PORT_BACKLIGHT,
-			       I2C_ADDR_BACKLIGHT_FLAGS,
-			       reg, data);
-		if (rv == EC_SUCCESS)
-			return EC_SUCCESS;
-		usleep(I2C_RETRY_DELAY);
-	}
-
-	CPRINTS("Backlight read fail: reg 0x%02x", reg);
-	return rv;
-}
-
-/* Write to lp8555 with automatic i2c retries */
-static int lp8555_write_with_retry(int reg, int data)
-{
-	int i, rv;
-
-	for (i = 0; i < I2C_RETRIES; i++) {
-		rv = i2c_write8(I2C_PORT_BACKLIGHT,
-				I2C_ADDR_BACKLIGHT_FLAGS,
-				reg, data);
-		if (rv == EC_SUCCESS)
-			return EC_SUCCESS;
-		usleep(I2C_RETRY_DELAY);
-	}
-
-	CPRINTS("Backlight write fail: reg 0x%02x data %d", reg, data);
-	return rv;
-}
-
-/**
- * Setup backlight controller and turn it on.
- */
-static void lp8555_enable_pwm_mode(void)
-{
-	int reg;
-	int rv;
-
-	/*
-	 * If not in S0, then PCH backlight enable will not be on, and if
-	 * lid is closed EC backlight enable will not be on. Since these
-	 * two signals are AND'ed together, no point in trying to talk to
-	 * the lp8555 if either one of them is not true.
-	 */
-	if (!chipset_in_state(CHIPSET_STATE_ON) || !lid_is_open())
-		return;
-
-	/* Enable PWM mode. */
-	rv = lp8555_read_with_retry(LP8555_REG_CONFIG, &reg);
-	if (rv != EC_SUCCESS)
-		return;
-	reg &= ~LP8555_REG_CONFIG_MODE_MASK;
-	reg |= LP8555_REG_CONFIG_MODE_PWM;
-	rv = lp8555_write_with_retry(LP8555_REG_CONFIG, reg);
-	if (rv != EC_SUCCESS)
-		return;
-
-	/* Set max LED current to 23mA. */
-	rv = lp8555_write_with_retry(LP8555_REG_CURRENT,
-				     LP8555_REG_CURRENT_MAXCURR_23MA);
-	if (rv != EC_SUCCESS)
-		return;
-
-	/* Set the rate of brightness change. */
-	rv = lp8555_write_with_retry(LP8555_REG_STEP,
-				     LP8555_REG_STEP_STEP_200MS |
-				     LP8555_REG_STEP_PWM_IN_HYST_8LSB |
-				     LP8555_REG_STEP_SMOOTH_HEAVY);
-	if (rv != EC_SUCCESS)
-		return;
-
-	/* Power on. */
-	rv = lp8555_read_with_retry(LP8555_REG_COMMAND, &reg);
-	if (rv != EC_SUCCESS)
-		return;
-	reg |= LP8555_REG_COMMAND_ON;
-	rv = lp8555_write_with_retry(LP8555_REG_COMMAND, reg);
-}
-DECLARE_DEFERRED(lp8555_enable_pwm_mode);
-
-/**
- * Host command to toggle backlight.
- */
-static enum ec_status
-switch_command_enable_backlight(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_switch_enable_backlight *p = args->params;
-
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, p->enabled);
-
-	if (p->enabled)
-		lp8555_enable_pwm_mode();
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_SWITCH_ENABLE_BKLIGHT,
-		     switch_command_enable_backlight,
-		     EC_VER_MASK(0));
-
-void backlight_interrupt(enum gpio_signal signal)
-{
-	/*
-	 * PCH indicates it is turning on backlight so we should
-	 * attempt to put the backlight controller into PWM mode.
-	 */
-	hook_call_deferred(&lp8555_enable_pwm_mode_data, 0);
-}
-
-/**
- * Update backlight state.
- */
-static void update_backlight(void)
-{
-	/*
-	 * Enable backlight if lid is open; this is AND'd with the request from
-	 * the AP in hardware.
-	 */
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, lid_is_open());
-	if (lid_is_open())
-		hook_call_deferred(&lp8555_enable_pwm_mode_data, 0);
-}
-DECLARE_HOOK(HOOK_LID_CHANGE, update_backlight, HOOK_PRIO_DEFAULT);
-
-/**
- * Initialize backlight module.
- */
-static void backlight_init(void)
-{
-	gpio_enable_interrupt(GPIO_PCH_BL_EN);
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, lid_is_open());
-}
-DECLARE_HOOK(HOOK_INIT, backlight_init, HOOK_PRIO_DEFAULT);
diff --git a/board/samus/power_sequence.c b/board/samus/power_sequence.c
deleted file mode 100644
index f6033055c4..0000000000
--- a/board/samus/power_sequence.c
+++ /dev/null
@@ -1,563 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* X86 chipset power control module for Chrome EC */
-
-#include "battery.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "extpower.h"
-#include "i2c.h"
-#include "lb_common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "wireless.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-/* Input state flags */
-#define IN_PGOOD_PP1050           POWER_SIGNAL_MASK(X86_PGOOD_PP1050)
-#define IN_PGOOD_PP1200           POWER_SIGNAL_MASK(X86_PGOOD_PP1200)
-#define IN_PGOOD_PP1800           POWER_SIGNAL_MASK(X86_PGOOD_PP1800)
-#define IN_PGOOD_VCORE            POWER_SIGNAL_MASK(X86_PGOOD_VCORE)
-
-#define IN_PCH_SLP_S0_DEASSERTED  POWER_SIGNAL_MASK(X86_SLP_S0_DEASSERTED)
-#define IN_PCH_SLP_S3_DEASSERTED  POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
-#define IN_PCH_SLP_S5_DEASSERTED  POWER_SIGNAL_MASK(X86_SLP_S5_DEASSERTED)
-#define IN_PCH_SLP_SUS_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_SUS_DEASSERTED)
-
-
-/* All non-core power rails */
-#define IN_PGOOD_ALL_NONCORE (IN_PGOOD_PP1050)
-/* All core power rails */
-#define IN_PGOOD_ALL_CORE    (IN_PGOOD_VCORE)
-/* Rails required for S3 */
-#define IN_PGOOD_S3          (IN_PGOOD_PP1200)
-/* Rails required for S0 */
-#define IN_PGOOD_S0          (IN_PGOOD_ALL_NONCORE)
-/* Rails used to detect if PP5000 is up. 1.8V PGOOD is not
- * a reliable signal to use here with an internal pullup. */
-#define IN_PGOOD_PP5000	     (IN_PGOOD_PP1050 | IN_PGOOD_PP1200)
-
-
-/* All PM_SLP signals from PCH deasserted */
-#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3_DEASSERTED | \
-				  IN_PCH_SLP_S5_DEASSERTED | \
-				  IN_PCH_SLP_SUS_DEASSERTED)
-
-/* All inputs in the right state for S0 */
-#define IN_ALL_S0 (IN_PGOOD_ALL_NONCORE | IN_PGOOD_ALL_CORE | \
-		   IN_ALL_PM_SLP_DEASSERTED)
-
-static int throttle_cpu;      /* Throttle CPU? */
-static uint32_t pp5000_in_g3; /* Turn PP5000 on in G3? */
-
-void chipset_force_shutdown(enum chipset_shutdown_reason reason)
-{
-	CPRINTS("%s(%d)", __func__, reason);
-	report_ap_reset(reason);
-
-	/*
-	 * Force off. This condition will reset once the state machine
-	 * transitions to G3.
-	 */
-	gpio_set_level(GPIO_PCH_DPWROK, 0);
-	gpio_set_level(GPIO_PCH_RSMRST_L, 0);
-}
-
-static void chipset_force_g3(void)
-{
-	CPRINTS("Forcing G3");
-
-	gpio_disable_interrupt(GPIO_VCORE_PGOOD);
-	gpio_set_level(GPIO_PCH_PWROK, 0);
-	gpio_set_level(GPIO_SYS_PWROK, 0);
-	gpio_set_level(GPIO_PP1050_EN, 0);
-	gpio_set_level(GPIO_PP1200_EN, 0);
-	gpio_set_level(GPIO_PP1800_EN, 0);
-	gpio_set_level(GPIO_PP3300_DSW_GATED_EN, 0);
-	gpio_set_level(GPIO_PP5000_USB_EN, 0);
-	/* Disable PP5000 if allowed */
-	if (!pp5000_in_g3)
-		gpio_set_level(GPIO_PP5000_EN, 0);
-	gpio_set_level(GPIO_PCH_RSMRST_L, 0);
-	gpio_set_level(GPIO_PCH_DPWROK, 0);
-	gpio_set_level(GPIO_PP3300_DSW_EN, 0);
-	wireless_set_state(WIRELESS_OFF);
-}
-
-static void chipset_reset_rtc(void)
-{
-	/*
-	 * Assert RTCRST# to the PCH long enough for it to latch the
-	 * assertion and reset the internal RTC backed state.
-	 */
-	CPRINTS("Asserting RTCRST# to PCH");
-	gpio_set_level(GPIO_PCH_RTCRST_L, 0);
-	udelay(100);
-	gpio_set_level(GPIO_PCH_RTCRST_L, 1);
-	udelay(10 * MSEC);
-}
-
-void chipset_reset(enum chipset_reset_reason reason)
-{
-	CPRINTS("%s(%d)", __func__, reason);
-	report_ap_reset(reason);
-
-	/*
-	 * Send a RCIN# pulse to the PCH.  This just causes it to
-	 * assert INIT# to the CPU without dropping power or asserting
-	 * PLTRST# to reset the rest of the system.
-	 */
-
-	/*
-	 * Pulse must be at least 16 PCI clocks long = 500 ns.
-	 */
-	gpio_set_level(GPIO_PCH_RCIN_L, 0);
-	udelay(10);
-	gpio_set_level(GPIO_PCH_RCIN_L, 1);
-}
-
-void chipset_throttle_cpu(int throttle)
-{
-	if (chipset_in_state(CHIPSET_STATE_ON))
-		gpio_set_level(GPIO_CPU_PROCHOT, throttle);
-}
-
-enum power_state power_chipset_init(void)
-{
-	/*
-	 * If we're switching between images without rebooting, see if the x86
-	 * is already powered on; if so, leave it there instead of cycling
-	 * through G3.
-	 */
-	if (system_jumped_to_this_image()) {
-		if ((power_get_signals() & IN_ALL_S0) == IN_ALL_S0) {
-			/* Disable idle task deep sleep when in S0. */
-			disable_sleep(SLEEP_MASK_AP_RUN);
-			CPRINTS("already in S0");
-			return POWER_S0;
-		} else {
-			/* Force all signals to their G3 states */
-			chipset_force_g3();
-		}
-	}
-
-	return POWER_G3;
-}
-
-enum power_state power_handle_state(enum power_state state)
-{
-	struct batt_params batt;
-
-	switch (state) {
-	case POWER_G3:
-		break;
-
-	case POWER_S5:
-
-		while ((power_get_signals() & IN_PCH_SLP_S5_DEASSERTED) == 0) {
-			if (task_wait_event(SECOND*4) == TASK_EVENT_TIMER) {
-				CPRINTS("timeout waiting for S5 exit");
-				/* Put system in G3 and assert RTCRST# */
-				chipset_force_g3();
-				chipset_reset_rtc();
-				/* Try to power back up after RTC reset */
-				return POWER_G3S5;
-			}
-		}
-		return POWER_S5S3; /* Power up to next state */
-		break;
-
-	case POWER_S3:
-		/* Check for state transitions */
-		if (!power_has_signals(IN_PGOOD_S3)) {
-			/* Required rail went away */
-			chipset_force_shutdown(CHIPSET_SHUTDOWN_POWERFAIL);
-			return POWER_S3S5;
-		} else if (gpio_get_level(GPIO_PCH_SLP_S3_L) == 1) {
-			/* Power up to next state */
-			return POWER_S3S0;
-		} else if (gpio_get_level(GPIO_PCH_SLP_S5_L) == 0) {
-			/* Power down to next state */
-			return POWER_S3S5;
-		}
-		break;
-
-	case POWER_S0:
-		if (!power_has_signals(IN_PGOOD_S0)) {
-			/* Required rail went away */
-			chipset_force_shutdown(CHIPSET_SHUTDOWN_POWERFAIL);
-			return POWER_S0S3;
-		} else if (gpio_get_level(GPIO_PCH_SLP_S3_L) == 0) {
-			/* Power down to next state */
-			return POWER_S0S3;
-		}
-		break;
-
-	case POWER_G3S5:
-		/* Return to G3 if battery level is too low */
-		if (charge_want_shutdown() ||
-		    charge_prevent_power_on(0)) {
-			CPRINTS("power-up inhibited");
-			chipset_force_g3();
-			return POWER_G3;
-		}
-
-		/* Enable 3.3V DSW */
-		gpio_set_level(GPIO_PP3300_DSW_EN, 1);
-
-		/*
-		 * Wait 10ms after +3VALW good, since that powers VccDSW and
-		 * VccSUS.
-		 */
-		msleep(10);
-
-		/* Enable PP5000 (5V) rail as 1.05V and 1.2V rails need 5V
-		 * rail to regulate properly. */
-		gpio_set_level(GPIO_PP5000_EN, 1);
-
-		/* Wait for PP1050/PP1200 PGOOD to go LOW to
-		 * indicate that PP5000 is stable */
-		while ((power_get_signals() & IN_PGOOD_PP5000) != 0) {
-			if (task_wait_event(SECOND) == TASK_EVENT_TIMER) {
-				CPRINTS("timeout waiting for PP5000");
-				chipset_force_g3();
-				return POWER_G3;
-			}
-		}
-
-		/*
-		 * TODO(crosbug.com/p/31583): Temporary hack to allow booting
-		 * without battery. If battery is not present here, then delay
-		 * to give time for PD MCU to negotiate to 20V.
-		 */
-		battery_get_params(&batt);
-		if (batt.is_present != BP_YES && !system_is_locked()) {
-			CPRINTS("Attempting boot w/o battery, adding delay");
-			msleep(500);
-		}
-
-		/* Assert DPWROK */
-		gpio_set_level(GPIO_PCH_DPWROK, 1);
-
-		/*
-		 * Wait for SLP_SUS before enabling 1.05V rail.
-		 */
-		if (power_wait_signals(IN_PCH_SLP_SUS_DEASSERTED)) {
-			CPRINTS("timeout waiting for SLP_SUS deassert");
-			chipset_force_g3();
-			return POWER_G3;
-		}
-
-		/* Enable PP1050 rail. */
-		gpio_set_level(GPIO_PP1050_EN, 1);
-
-		/* Wait for 1.05V to come up and CPU to notice */
-		if (power_wait_signals(IN_PGOOD_PP1050)) {
-			CPRINTS("timeout waiting for PP1050");
-			chipset_force_g3();
-			return POWER_G3;
-		}
-
-		/* Add 10ms delay between SUSP_VR and RSMRST */
-		msleep(10);
-
-		/* Deassert RSMRST# */
-		gpio_set_level(GPIO_PCH_RSMRST_L, 1);
-
-		/* Wait 5ms for SUSCLK to stabilize */
-		msleep(5);
-
-		/* Call hook to indicate out of G3 state */
-		hook_notify(HOOK_CHIPSET_PRE_INIT);
-		return POWER_S5;
-
-	case POWER_S5S3:
-		/* Turn on power to RAM */
-		gpio_set_level(GPIO_PP1800_EN, 1);
-		gpio_set_level(GPIO_PP1200_EN, 1);
-		if (power_wait_signals(IN_PGOOD_S3)) {
-			gpio_set_level(GPIO_PP1800_EN, 0);
-			gpio_set_level(GPIO_PP1200_EN, 0);
-			chipset_force_shutdown(CHIPSET_SHUTDOWN_WAIT);
-			return POWER_S5;
-		}
-
-		/*
-		 * Take lightbar out of reset, now that +5VALW is
-		 * available and we won't leak +3VALW through the reset
-		 * line.
-		 */
-		i2c_lock(I2C_PORT_LIGHTBAR, 1);
-		gpio_set_level(GPIO_LIGHTBAR_RESET_L, 1);
-		msleep(1);
-		lb_init(0);
-		msleep(100);
-		i2c_lock(I2C_PORT_LIGHTBAR, 0);
-
-		/*
-		 * Enable touchpad power so it can wake the system from
-		 * suspend.
-		 */
-		gpio_set_level(GPIO_ENABLE_TOUCHPAD, 1);
-
-		/* Turn on USB power rail. */
-		gpio_set_level(GPIO_PP5000_USB_EN, 1);
-
-		/* Call hooks now that rails are up */
-		hook_notify(HOOK_CHIPSET_STARTUP);
-		return POWER_S3;
-
-	case POWER_S3S0:
-		/* Turn on 3.3V DSW gated rail for core regulator */
-		gpio_set_level(GPIO_PP3300_DSW_GATED_EN, 1);
-
-		/* Wait 20ms before allowing VCCST_PGOOD to rise. */
-		msleep(20);
-
-		/* Enable wireless. */
-		wireless_set_state(WIRELESS_ON);
-
-		/* Make sure the touchscreen is on, too. */
-		gpio_set_level(GPIO_TOUCHSCREEN_RESET_L, 1);
-
-		/* Wait for non-core power rails good */
-		if (power_wait_signals(IN_PGOOD_S0)) {
-			gpio_set_level(GPIO_TOUCHSCREEN_RESET_L, 0);
-			wireless_set_state(WIRELESS_OFF);
-			gpio_set_level(GPIO_PP3300_DSW_GATED_EN, 1);
-			chipset_force_shutdown(CHIPSET_SHUTDOWN_WAIT);
-			return POWER_S3;
-		}
-
-		/* Call hooks now that rails are up */
-		hook_notify(HOOK_CHIPSET_RESUME);
-
-		/*
-		 * Disable idle task deep sleep. This means that the low
-		 * power idle task will not go into deep sleep while in S0.
-		 */
-		disable_sleep(SLEEP_MASK_AP_RUN);
-
-		/*
-		 * Throttle CPU if necessary.  This should only be asserted
-		 * when +VCCP is powered (it is by now).
-		 */
-		gpio_set_level(GPIO_CPU_PROCHOT, throttle_cpu);
-
-		/*
-		 * VCORE_PGOOD signal buffer is powered by PP1050_VCCST which
-		 * is gated by SLP_S3 assertion.  Now the signal is valid and
-		 * can be enabled as an interrupt source.
-		 */
-		gpio_enable_interrupt(GPIO_VCORE_PGOOD);
-
-		/* Set PCH_PWROK */
-		gpio_set_level(GPIO_PCH_PWROK, 1);
-
-		/* Wait for VCORE_PGOOD before enabling SYS_PWROK */
-		if (power_wait_signals(IN_PGOOD_VCORE)) {
-			gpio_disable_interrupt(GPIO_VCORE_PGOOD);
-			hook_notify(HOOK_CHIPSET_SUSPEND);
-			enable_sleep(SLEEP_MASK_AP_RUN);
-			gpio_set_level(GPIO_PCH_PWROK, 0);
-			gpio_set_level(GPIO_CPU_PROCHOT, 0);
-			gpio_set_level(GPIO_TOUCHSCREEN_RESET_L, 0);
-			gpio_set_level(GPIO_PP3300_DSW_GATED_EN, 1);
-			wireless_set_state(WIRELESS_OFF);
-			chipset_force_shutdown(CHIPSET_SHUTDOWN_WAIT);
-			return POWER_S3;
-		}
-
-		/*
-		 * Wait a bit for all voltages to be good. PCIe devices need
-		 * 99ms, but mini-PCIe devices only need 1ms. Intel recommends
-		 * at least 5ms between ALL_SYS_PWRGD and SYS_PWROK.
-		 */
-		msleep(5);
-
-		/* Set SYS_PWROK */
-		gpio_set_level(GPIO_SYS_PWROK, 1);
-		return POWER_S0;
-
-	case POWER_S0S3:
-		/* Call hooks before we remove power rails */
-		hook_notify(HOOK_CHIPSET_SUSPEND);
-
-		/* Clear PCH_PWROK */
-		gpio_set_level(GPIO_SYS_PWROK, 0);
-		gpio_set_level(GPIO_PCH_PWROK, 0);
-
-		/* Wait 40ns */
-		udelay(1);
-
-		/* Suspend wireless */
-		wireless_set_state(WIRELESS_SUSPEND);
-
-		/*
-		 * Enable idle task deep sleep. Allow the low power idle task
-		 * to go into deep sleep in S3 or lower.
-		 */
-		enable_sleep(SLEEP_MASK_AP_RUN);
-
-		/* Put touchscreen in reset */
-		gpio_set_level(GPIO_TOUCHSCREEN_RESET_L, 0);
-
-		/*
-		 * Deassert prochot since CPU is off and we're about to drop
-		 * +VCCP.
-		 */
-		gpio_set_level(GPIO_CPU_PROCHOT, 0);
-
-		/* Turn off DSW gated */
-		gpio_set_level(GPIO_PP3300_DSW_GATED_EN, 0);
-
-		/*
-		 * VCORE_PGOOD signal buffer is powered by PP1050_VCCST which
-		 * is gated by SLP_S3 assertion.  The signal is no longer
-		 * valid and should be disabled as an interrupt source.
-		 */
-		gpio_disable_interrupt(GPIO_VCORE_PGOOD);
-		return POWER_S3;
-
-	case POWER_S3S5:
-		/* Call hooks before we remove power rails */
-		hook_notify(HOOK_CHIPSET_SHUTDOWN);
-
-		/* Disable wireless */
-		wireless_set_state(WIRELESS_OFF);
-
-		/* Disable peripheral power */
-		gpio_set_level(GPIO_ENABLE_TOUCHPAD, 0);
-		gpio_set_level(GPIO_PP5000_USB_EN, 0);
-
-		/* Turn off power to RAM */
-		gpio_set_level(GPIO_PP1800_EN, 0);
-		gpio_set_level(GPIO_PP1200_EN, 0);
-
-		/*
-		 * Put touchscreen and lightbar in reset, so we won't
-		 * leak +3VALW through the reset line to chips powered
-		 * by +5VALW.
-		 *
-		 * (Note that we're no longer powering down +5VALW due
-		 * to crosbug.com/p/16600, but to minimize side effects
-		 * of that change we'll still reset these components in
-		 * S5.)
-		 */
-		gpio_set_level(GPIO_TOUCHSCREEN_RESET_L, 0);
-		gpio_set_level(GPIO_LIGHTBAR_RESET_L, 0);
-
-		/* Call hooks after we remove power rails */
-		hook_notify(HOOK_CHIPSET_SHUTDOWN_COMPLETE);
-
-		return power_get_pause_in_s5() ? POWER_S5 : POWER_S5G3;
-
-	case POWER_S5G3:
-		/* Deassert DPWROK */
-		gpio_set_level(GPIO_PCH_DPWROK, 0);
-
-		/* Assert RSMRST# */
-		gpio_set_level(GPIO_PCH_RSMRST_L, 0);
-
-		/* Turn off power rails enabled in S5 */
-		gpio_set_level(GPIO_PP1050_EN, 0);
-
-		/* Check if we can disable PP5000 */
-		if (!pp5000_in_g3)
-			gpio_set_level(GPIO_PP5000_EN, 0);
-
-		/* Disable 3.3V DSW */
-		gpio_set_level(GPIO_PP3300_DSW_EN, 0);
-		return POWER_G3;
-	}
-
-	return state;
-}
-
-/**
- * Set PP5000 rail in G3. The mask represents the reason for
- * turning on/off the PP5000 rail in G3, and enable either
- * enables or disables that mask. If any bit is enabled, then
- * the PP5000 rail will remain on. If all bits are cleared,
- * the rail will turn off.
- *
- * @param mask   Mask to modify
- * @param enable Enable flag
- */
-void set_pp5000_in_g3(int mask, int enable)
-{
-	if (enable)
-		deprecated_atomic_or(&pp5000_in_g3, mask);
-	else
-		deprecated_atomic_clear_bits(&pp5000_in_g3, mask);
-
-	/* if we are in G3 now, then set the rail accordingly */
-	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
-		gpio_set_level(GPIO_PP5000_EN, !!pp5000_in_g3);
-}
-
-#ifdef CONFIG_LIGHTBAR_POWER_RAILS
-/* Returns true if a change was made, NOT the new state */
-int lb_power(int enabled)
-{
-	int ret = 0;
-	int pp5000_en = gpio_get_level(GPIO_PP5000_EN);
-
-	set_pp5000_in_g3(PP5000_IN_G3_LIGHTBAR, enabled);
-
-	/* If the AP is on, we don't change the rails. */
-	if (!chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return ret;
-
-	/* Check if PP5000 rail changed */
-	if (gpio_get_level(GPIO_PP5000_EN) != pp5000_en)
-		ret = 1;
-
-	/*
-	 * When turning on, we have to wait for the rails to come up
-	 * fully before we the lightbar ICs will respond. There's not
-	 * a reliable PGOOD signal for that (I tried), so we just
-	 * have to wait. These delays seem to work.
-	 *
-	 * Note, we should delay even if the PP5000 rail was already
-	 * enabled because we can't be sure it's been enabled long
-	 * enough for lightbar IC to respond.
-	 *
-	 * Also, the lightbar do not expect other i2c traffic while
-	 * being power up. Put a lock on the i2c bus.
-	 * see chrome-os-partner:45223.
-	 */
-	if (enabled) {
-		i2c_lock(I2C_PORT_LIGHTBAR, 1);
-		msleep(10);
-	}
-
-	if (enabled != gpio_get_level(GPIO_LIGHTBAR_RESET_L)) {
-		ret = 1;
-		gpio_set_level(GPIO_LIGHTBAR_RESET_L, enabled);
-		msleep(1);
-	}
-	if (enabled) {
-		lb_init(0);
-		msleep(100);
-		i2c_lock(I2C_PORT_LIGHTBAR, 0);
-	}
-
-	return ret;
-}
-#endif
diff --git a/board/samus_pd/board.c b/board/samus_pd/board.c
deleted file mode 100644
index 0f9c8cfbfe..0000000000
--- a/board/samus_pd/board.c
+++ /dev/null
@@ -1,620 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* samus_pd board configuration */
-
-#include "adc.h"
-#include "adc_chip.h"
-#include "battery.h"
-#include "charge_manager.h"
-#include "charge_ramp.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "pi3usb9281.h"
-#include "power.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "usb_charge.h"
-#include "usb_descriptor.h"
-#include "usb_pd.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-
-/*
- * When battery is high, system may not be pulling full current. Also, when
- * high AND input voltage is below boost bypass, then limit input current
- * limit to HIGH_BATT_LIMIT_CURR_MA to reduce audible ringing.
- */
-#define HIGH_BATT_THRESHOLD 90
-#define HIGH_BATT_LIMIT_BOOST_BYPASS_MV 11000
-#define HIGH_BATT_LIMIT_CURR_MA 2000
-
-/* Chipset power state */
-static enum power_state ps;
-
-/* Battery state of charge */
-static int batt_soc;
-
-/* Default to 5V charging allowed for dead battery case */
-static enum pd_charge_state charge_state = PD_CHARGE_5V;
-
-/* PD MCU status and host event status for host command */
-static int32_t host_event_status_flags;
-static int32_t pd_status_flags;
-
-static struct ec_response_pd_status pd_status;
-
-/* Desired input current limit */
-static int desired_charge_rate_ma = -1;
-
-/* PWM channels. Must be in the exact same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	{STM32_TIM(15), STM32_TIM_CH(2), 0},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-struct mutex pericom_mux_lock;
-struct pi3usb9281_config pi3usb9281_chips[] = {
-	{
-		.i2c_port = I2C_PORT_PERICOM,
-		.mux_gpio = GPIO_USB_C_BC12_SEL,
-		.mux_gpio_level = 0,
-		.mux_lock = &pericom_mux_lock,
-	},
-	{
-		.i2c_port = I2C_PORT_PERICOM,
-		.mux_gpio = GPIO_USB_C_BC12_SEL,
-		.mux_gpio_level = 1,
-		.mux_lock = &pericom_mux_lock,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9281_chips) ==
-	     CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT);
-
-static void pericom_port0_reenable_interrupts(void)
-{
-	CPRINTS("VBUS p0 %d", gpio_get_level(GPIO_USB_C0_VBUS_WAKE));
-	pi3usb9281_enable_interrupts(0);
-}
-DECLARE_DEFERRED(pericom_port0_reenable_interrupts);
-
-static void pericom_port1_reenable_interrupts(void)
-{
-	CPRINTS("VBUS p1 %d", gpio_get_level(GPIO_USB_C1_VBUS_WAKE));
-	pi3usb9281_enable_interrupts(1);
-}
-DECLARE_DEFERRED(pericom_port1_reenable_interrupts);
-
-void vbus0_evt(enum gpio_signal signal)
-{
-	usb_charger_vbus_change(0, gpio_get_level(signal));
-	task_wake(TASK_ID_PD_C0);
-}
-
-void vbus1_evt(enum gpio_signal signal)
-{
-	usb_charger_vbus_change(1, gpio_get_level(signal));
-	task_wake(TASK_ID_PD_C1);
-}
-
-void usb0_evt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
-}
-
-void usb1_evt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12, 0);
-}
-
-static void chipset_s5_to_s3(void)
-{
-	ps = POWER_S3;
-	hook_notify(HOOK_CHIPSET_STARTUP);
-}
-
-static void chipset_s3_to_s0(void)
-{
-	/* Disable deep sleep and restore charge override port */
-	disable_sleep(SLEEP_MASK_AP_RUN);
-	ps = POWER_S0;
-	hook_notify(HOOK_CHIPSET_RESUME);
-}
-
-static void chipset_s3_to_s5(void)
-{
-	ps = POWER_S5;
-	hook_notify(HOOK_CHIPSET_SHUTDOWN);
-	hook_notify(HOOK_CHIPSET_SHUTDOWN_COMPLETE);
-}
-
-static void chipset_s0_to_s3(void)
-{
-	/* Enable deep sleep and store charge override port */
-	enable_sleep(SLEEP_MASK_AP_RUN);
-	ps = POWER_S3;
-	hook_notify(HOOK_CHIPSET_SUSPEND);
-}
-
-static void pch_evt_deferred(void)
-{
-	/* Determine new chipset state, trigger corresponding transition */
-	switch (ps) {
-	case POWER_S5:
-		if (gpio_get_level(GPIO_PCH_SLP_S5_L))
-			chipset_s5_to_s3();
-		if (gpio_get_level(GPIO_PCH_SLP_S3_L))
-			chipset_s3_to_s0();
-		break;
-	case POWER_S3:
-		if (gpio_get_level(GPIO_PCH_SLP_S3_L))
-			chipset_s3_to_s0();
-		else if (!gpio_get_level(GPIO_PCH_SLP_S5_L))
-			chipset_s3_to_s5();
-		break;
-	case POWER_S0:
-		if (!gpio_get_level(GPIO_PCH_SLP_S3_L))
-			chipset_s0_to_s3();
-		if (!gpio_get_level(GPIO_PCH_SLP_S5_L))
-			chipset_s3_to_s5();
-		break;
-	default:
-		break;
-	}
-}
-DECLARE_DEFERRED(pch_evt_deferred);
-
-void pch_evt(enum gpio_signal signal)
-{
-	hook_call_deferred(&pch_evt_deferred_data, 0);
-}
-
-void board_config_pre_init(void)
-{
-	/* enable SYSCFG clock */
-	STM32_RCC_APB2ENR |= BIT(0);
-	/*
-	 * the DMA mapping is :
-	 *  Chan 2 : TIM1_CH1  (C0 RX)
-	 *  Chan 3 : SPI1_TX   (C1 TX)
-	 *  Chan 4 : USART1_TX
-	 *  Chan 5 : USART1_RX
-	 *  Chan 6 : TIM3_CH1  (C1 RX)
-	 *  Chan 7 : SPI2_TX   (C0 TX)
-	 */
-
-	/*
-	 * Remap USART1 RX/TX DMA to match uart driver. Remap SPI2 RX/TX and
-	 * TIM3_CH1 for unique DMA channels.
-	 */
-	STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10) | BIT(24) | BIT(30);
-}
-
-#include "gpio_list.h"
-
-/* Initialize board. */
-static void board_init(void)
-{
-	int slp_s5 = gpio_get_level(GPIO_PCH_SLP_S5_L);
-	int slp_s3 = gpio_get_level(GPIO_PCH_SLP_S3_L);
-
-	/*
-	 * Enable CC lines after all GPIO have been initialized. Note, it is
-	 * important that this is enabled after the CC_ODL lines are set low
-	 * to specify device mode.
-	 */
-	gpio_set_level(GPIO_USB_C_CC_EN, 1);
-
-	/* Enable interrupts on VBUS transitions. */
-	gpio_enable_interrupt(GPIO_USB_C0_VBUS_WAKE);
-	gpio_enable_interrupt(GPIO_USB_C1_VBUS_WAKE);
-
-	/* Enable pericom BC1.2 interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_L);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L);
-
-	/* Determine initial chipset state */
-	if (slp_s5 && slp_s3) {
-		disable_sleep(SLEEP_MASK_AP_RUN);
-		hook_notify(HOOK_CHIPSET_RESUME);
-		ps = POWER_S0;
-	} else if (slp_s5 && !slp_s3) {
-		enable_sleep(SLEEP_MASK_AP_RUN);
-		hook_notify(HOOK_CHIPSET_STARTUP);
-		ps = POWER_S3;
-	} else {
-		enable_sleep(SLEEP_MASK_AP_RUN);
-		hook_notify(HOOK_CHIPSET_SHUTDOWN);
-		hook_notify(HOOK_CHIPSET_SHUTDOWN_COMPLETE);
-		ps = POWER_S5;
-	}
-
-	/* Enable interrupts on PCH state change */
-	gpio_enable_interrupt(GPIO_PCH_SLP_S3_L);
-	gpio_enable_interrupt(GPIO_PCH_SLP_S5_L);
-
-	/* Initialize active charge port to none */
-	pd_status.active_charge_port = CHARGE_PORT_NONE;
-
-	/* Set PD MCU system status bits */
-	if (system_jumped_to_this_image())
-		pd_status_flags |= PD_STATUS_JUMPED_TO_IMAGE;
-	if (system_is_in_rw())
-		pd_status_flags |= PD_STATUS_IN_RW;
-
-#ifdef CONFIG_PWM
-	/* Enable ILIM PWM: initial duty cycle 0% = 500mA limit. */
-	pwm_enable(PWM_CH_ILIM, 1);
-	pwm_set_duty(PWM_CH_ILIM, 0);
-#endif
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	/* USB PD CC lines sensing. Converted to mV (3300mV/4096). */
-	[ADC_C0_CC1_PD] = {"C0_CC1_PD", 3300, 4096, 0, STM32_AIN(0)},
-	[ADC_C1_CC1_PD] = {"C1_CC1_PD", 3300, 4096, 0, STM32_AIN(2)},
-	[ADC_C0_CC2_PD] = {"C0_CC2_PD", 3300, 4096, 0, STM32_AIN(4)},
-	[ADC_C1_CC2_PD] = {"C1_CC2_PD", 3300, 4096, 0, STM32_AIN(5)},
-
-	/* Vbus sensing. Converted to mV, full ADC is equivalent to 25.774V. */
-	[ADC_VBUS] = {"VBUS",  25774, 4096, 0, STM32_AIN(11)},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"master", I2C_PORT_MASTER, 100,
-		GPIO_MASTER_I2C_SCL, GPIO_MASTER_I2C_SDA},
-	{"slave",  I2C_PORT_SLAVE, 100,
-		GPIO_SLAVE_I2C_SCL, GPIO_SLAVE_I2C_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-int board_get_battery_soc(void)
-{
-	return batt_soc;
-}
-
-enum battery_present battery_is_present(void)
-{
-	if (batt_soc >= 0)
-		return BP_YES;
-	return BP_NOT_SURE;
-}
-
-static void pd_send_ec_int(void)
-{
-	gpio_set_level(GPIO_EC_INT, 1);
-
-	/*
-	 * Delay long enough to guarantee EC see's the change. Slowest
-	 * EC clock speed is 250kHz in deep sleep -> 4us, and add 1us
-	 * for buffer.
-	 */
-	usleep(5);
-
-	gpio_set_level(GPIO_EC_INT, 0);
-}
-
-/**
- * Set active charge port -- only one port can be active at a time.
- *
- * @param charge_port   Charge port to enable.
- *
- * Returns EC_SUCCESS if charge port is accepted and made active,
- * EC_ERROR_* otherwise.
- */
-int board_set_active_charge_port(int charge_port)
-{
-	/* charge port is a realy physical port */
-	int is_real_port = (charge_port >= 0 &&
-			    charge_port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	/* check if we are source vbus on that port */
-	if (is_real_port && usb_charger_port_is_sourcing_vbus(charge_port)) {
-		CPRINTS("Skip enable p%d", charge_port);
-		return EC_ERROR_INVAL;
-	}
-
-	CPRINTS("New chg p%d", charge_port);
-
-	/*
-	 * If charging and the active charge port is changed, then disable
-	 * charging to guarantee charge circuit starts up cleanly.
-	 */
-	if (pd_status.active_charge_port != CHARGE_PORT_NONE &&
-	    (charge_port == CHARGE_PORT_NONE ||
-	     charge_port != pd_status.active_charge_port)) {
-		gpio_set_level(GPIO_USB_C0_CHARGE_EN_L, 1);
-		gpio_set_level(GPIO_USB_C1_CHARGE_EN_L, 1);
-		charge_state = PD_CHARGE_NONE;
-		pd_status.active_charge_port = charge_port;
-		CPRINTS("Chg: None");
-		return EC_SUCCESS;
-	}
-
-	/* Save active charge port and enable charging if allowed */
-	pd_status.active_charge_port = charge_port;
-	if (charge_state != PD_CHARGE_NONE) {
-		gpio_set_level(GPIO_USB_C0_CHARGE_EN_L, !(charge_port == 0));
-		gpio_set_level(GPIO_USB_C1_CHARGE_EN_L, !(charge_port == 1));
-	}
-
-	return EC_SUCCESS;
-}
-
-/**
- * Return if max voltage charging is allowed.
- */
-int pd_is_max_request_allowed(void)
-{
-	return charge_state == PD_CHARGE_MAX;
-}
-
-/**
- * Return if board is consuming full amount of input current
- */
-int charge_is_consuming_full_input_current(void)
-{
-	return batt_soc >= 1 && batt_soc < HIGH_BATT_THRESHOLD;
-}
-
-/*
- * Number of VBUS samples to average when computing if VBUS is too low
- * for the ramp stable state.
- */
-#define VBUS_STABLE_SAMPLE_COUNT 4
-
-/* VBUS too low threshold */
-#define VBUS_LOW_THRESHOLD_MV    4600
-
-/**
- * Return if VBUS is sagging too low
- */
-int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
-{
-	static int vbus[VBUS_STABLE_SAMPLE_COUNT];
-	static int vbus_idx, vbus_samples_full;
-	int vbus_sum, i;
-
-	/*
-	 * If we are not allowing charging, it's because the EC saw
-	 * ACOK go low, so we know VBUS is drooping too far.
-	 */
-	if (charge_state == PD_CHARGE_NONE)
-		return 1;
-
-	/* If we are ramping, only look at one reading */
-	if (ramp_state == CHG_RAMP_VBUS_RAMPING) {
-		/* Reset the VBUS array vars used for the stable state */
-		vbus_idx = vbus_samples_full = 0;
-		return adc_read_channel(ADC_VBUS) < VBUS_LOW_THRESHOLD_MV;
-	}
-
-	/* Fill VBUS array with ADC readings */
-	vbus[vbus_idx] = adc_read_channel(ADC_VBUS);
-	vbus_idx = (vbus_idx == VBUS_STABLE_SAMPLE_COUNT-1) ? 0 : vbus_idx + 1;
-	if (vbus_idx == 0)
-		vbus_samples_full = 1;
-
-	/* If VBUS array is not full yet, then return ok */
-	if (!vbus_samples_full)
-		return 0;
-
-	/* All VBUS samples are populated, take average */
-	vbus_sum = 0;
-	for (i = 0; i < VBUS_STABLE_SAMPLE_COUNT; i++)
-		vbus_sum += vbus[i];
-
-	/* Return if average is lower than threshold */
-	return vbus_sum < (VBUS_STABLE_SAMPLE_COUNT * VBUS_LOW_THRESHOLD_MV);
-}
-
-static int board_update_charge_limit(int charge_ma)
-{
-#ifdef CONFIG_PWM
-	int pwm_duty;
-#endif
-	static int actual_charge_rate_ma = -1;
-
-	desired_charge_rate_ma = charge_ma;
-
-	if (batt_soc >= HIGH_BATT_THRESHOLD &&
-	    adc_read_channel(ADC_VBUS) < HIGH_BATT_LIMIT_BOOST_BYPASS_MV)
-		charge_ma = MIN(charge_ma, HIGH_BATT_LIMIT_CURR_MA);
-
-	/* if current hasn't changed, don't do anything */
-	if (charge_ma == actual_charge_rate_ma)
-		return 0;
-
-	actual_charge_rate_ma = charge_ma;
-
-#ifdef CONFIG_PWM
-	pwm_duty = MA_TO_PWM(charge_ma);
-	if (pwm_duty < 0)
-		pwm_duty = 0;
-	else if (pwm_duty > 100)
-		pwm_duty = 100;
-
-	pwm_set_duty(PWM_CH_ILIM, pwm_duty);
-#endif
-
-	pd_status.curr_lim_ma = charge_ma >= 500 ?
-				(charge_ma - 500) * 92 / 100 + 256 : 0;
-
-	CPRINTS("New ilim %d", charge_ma);
-	return 1;
-}
-
-/**
- * Set the charge limit based upon desired maximum.
- *
- * @param port          Port number.
- * @param supplier      Charge supplier type.
- * @param charge_ma     Desired charge limit (mA).
- * @param charge_mv     Negotiated charge voltage (mV).
- */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	/* Update current limit and notify EC if it changed */
-	if (board_update_charge_limit(charge_ma), charge_mv)
-		pd_send_ec_int();
-}
-
-static void board_update_battery_soc(int soc)
-{
-	if (batt_soc != soc) {
-		batt_soc = soc;
-		if (batt_soc >= CONFIG_CHARGE_MANAGER_BAT_PCT_SAFE_MODE_EXIT)
-			charge_manager_leave_safe_mode();
-		board_update_charge_limit(desired_charge_rate_ma);
-		hook_notify(HOOK_BATTERY_SOC_CHANGE);
-	}
-}
-
-/* Send host event up to AP */
-void pd_send_host_event(int mask)
-{
-	/* mask must be set */
-	if (!mask)
-		return;
-
-	deprecated_atomic_or(&(host_event_status_flags), mask);
-	deprecated_atomic_or(&(pd_status_flags), PD_STATUS_HOST_EVENT);
-	pd_send_ec_int();
-}
-
-int battery_is_cut_off(void)
-{
-	return 0;  /* Always return NOT cut off */
-}
-
-/****************************************************************************/
-/* Console commands */
-static int command_ec_int(int argc, char **argv)
-{
-	pd_send_ec_int();
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(ecint, command_ec_int,
-			"",
-			"Toggle EC interrupt line");
-
-static int command_pd_host_event(int argc, char **argv)
-{
-	int event_mask;
-	char *e;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	event_mask = strtoi(argv[1], &e, 10);
-	if (*e)
-		return EC_ERROR_PARAM1;
-
-	pd_send_host_event(event_mask);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(pdevent, command_pd_host_event,
-			"event_mask",
-			"Send PD host event");
-
-/****************************************************************************/
-/* Host commands */
-static enum ec_status ec_status_host_cmd(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_pd_status *p = args->params;
-	struct ec_response_pd_status *r = args->response;
-
-	/* update battery soc */
-	board_update_battery_soc(p->batt_soc);
-
-	if (p->charge_state != charge_state) {
-		switch (p->charge_state) {
-		case PD_CHARGE_NONE:
-			/*
-			 * No current allowed in, set new power request
-			 * so that PD negotiates down to vSafe5V.
-			 */
-			charge_state = p->charge_state;
-			gpio_set_level(GPIO_USB_C0_CHARGE_EN_L, 1);
-			gpio_set_level(GPIO_USB_C1_CHARGE_EN_L, 1);
-			pd_set_new_power_request(
-				pd_status.active_charge_port);
-			/*
-			 * Wake charge ramp task so that it will check
-			 * board_is_vbus_too_low() and stop ramping up.
-			 */
-			task_wake(TASK_ID_CHG_RAMP);
-			CPRINTS("Chg: None");
-			break;
-		case PD_CHARGE_5V:
-			/* Allow current on the active charge port */
-			charge_state = p->charge_state;
-			gpio_set_level(GPIO_USB_C0_CHARGE_EN_L,
-				!(pd_status.active_charge_port == 0));
-			gpio_set_level(GPIO_USB_C1_CHARGE_EN_L,
-				!(pd_status.active_charge_port == 1));
-			CPRINTS("Chg: 5V");
-			break;
-		case PD_CHARGE_MAX:
-			/*
-			 * Allow negotiation above vSafe5V. Should only
-			 * ever get this command when 5V charging is
-			 * already allowed.
-			 */
-			if (charge_state == PD_CHARGE_5V) {
-				charge_state = p->charge_state;
-				pd_set_new_power_request(
-					pd_status.active_charge_port);
-				CPRINTS("Chg: Max");
-			}
-			break;
-		default:
-			break;
-		}
-	}
-
-	*r = pd_status;
-	r->status = pd_status_flags;
-
-	/* Clear host event */
-	deprecated_atomic_clear_bits(&(pd_status_flags), PD_STATUS_HOST_EVENT);
-
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_PD_EXCHANGE_STATUS, ec_status_host_cmd,
-		     EC_VER_MASK(EC_VER_PD_EXCHANGE_STATUS));
-
-static enum ec_status
-host_event_status_host_cmd(struct host_cmd_handler_args *args)
-{
-	struct ec_response_host_event_status *r = args->response;
-
-	/* Clear host event bit to avoid sending more unnecessary events */
-	deprecated_atomic_clear_bits(&(pd_status_flags), PD_STATUS_HOST_EVENT);
-
-	/* Read and clear the host event status to return to AP */
-	r->status = deprecated_atomic_read_clear(&(host_event_status_flags));
-
-	args->response_size = sizeof(*r);
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_PD_HOST_EVENT_STATUS, host_event_status_host_cmd,
-			EC_VER_MASK(0));
diff --git a/board/samus_pd/board.h b/board/samus_pd/board.h
deleted file mode 100644
index 9102d097ce..0000000000
--- a/board/samus_pd/board.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* samus_pd board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* 48 MHz SYSCLK clock frequency */
-#define CPU_CLOCK 48000000
-
-/* the UART console is on USART1 (PA9/PA10) */
-#undef  CONFIG_UART_CONSOLE
-#define CONFIG_UART_CONSOLE 1
-
-/* Optional features */
-#define CONFIG_ADC
-#undef  CONFIG_ADC_WATCHDOG
-#define CONFIG_BATTERY_PRESENT_CUSTOM
-#define CONFIG_BOARD_PRE_INIT
-#define CONFIG_CHARGE_MANAGER
-#define CONFIG_CHARGE_RAMP_SW
-#undef  CONFIG_CMD_ADC
-#undef  CONFIG_CMD_CHARGE_SUPPLIER_INFO
-#undef  CONFIG_CMD_CRASH
-#undef  CONFIG_CMD_HASH
-#undef  CONFIG_CMD_HCDEBUG
-#undef  CONFIG_CMD_I2C_SCAN
-#undef  CONFIG_CMD_I2C_XFER
-/* Minimum ilim = 500 mA */
-#define CONFIG_CHARGER_INPUT_CURRENT PWM_0_MA
-#undef  CONFIG_CMD_GETTIME
-#undef  CONFIG_CMD_IDLE_STATS
-#undef  CONFIG_CMD_MD
-#undef  CONFIG_CMD_RW
-#undef  CONFIG_CMD_SHMEM
-#undef  CONFIG_CMD_TIMERINFO
-#define CONFIG_COMMON_GPIO_SHORTNAMES
-#undef  CONFIG_CONSOLE_CMDHELP
-#undef  CONFIG_CONSOLE_HISTORY
-#undef  CONFIG_DEBUG_ASSERT
-#define CONFIG_FORCE_CONSOLE_RESUME
-#define CONFIG_HIBERNATE_WAKEUP_PINS (STM32_PWR_CSR_EWUP3|STM32_PWR_CSR_EWUP8)
-#define CONFIG_HOSTCMD_ALIGNED
-#undef  CONFIG_HOSTCMD_EVENTS
-#define CONFIG_HW_CRC
-#define CONFIG_I2C
-#define CONFIG_I2C_MASTER
-#define CONFIG_I2C_SLAVE
-#undef  CONFIG_LID_SWITCH
-#define CONFIG_LOW_POWER_IDLE
-#define CONFIG_LTO
-#undef  CONFIG_PWM
-#define CONFIG_STM_HWTIMER32
-#undef  CONFIG_TASK_PROFILING
-#define CONFIG_USB_CHARGER
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV1
-#undef CONFIG_USB_PD_TCPMV1_DEBUG
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_CHECK_MAX_REQUEST_ALLOWED
-#define CONFIG_USB_PD_COMM_LOCKED
-#define CONFIG_USB_PD_CUSTOM_PDO
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_PD_FLASH_ERASE_CHECK
-#define CONFIG_USB_PD_INTERNAL_COMP
-#undef CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_TCPC
-#define CONFIG_USB_PD_TCPM_STUB
-#define CONFIG_USB_PD_VBUS_DETECT_GPIO
-#define CONFIG_BC12_DETECT_PI3USB9281
-#define CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT 2
-#define CONFIG_USBC_SS_MUX_DFP_ONLY
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-#define CONFIG_VBOOT_HASH
-#undef  CONFIG_WATCHDOG_HELP
-
-/* Use PSTATE embedded in the RO image, not in its own erase block */
-#undef  CONFIG_FLASH_PSTATE_BANK
-#undef  CONFIG_FW_PSTATE_SIZE
-#define CONFIG_FW_PSTATE_SIZE 0
-
-/* I2C ports configuration */
-#define I2C_PORT_MASTER 1
-#define I2C_PORT_SLAVE  0
-#define I2C_PORT_EC I2C_PORT_SLAVE
-#define I2C_PORT_PERICOM I2C_PORT_MASTER
-
-/* slave address for host commands */
-#ifdef HAS_TASK_HOSTCMD
-#define CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS CONFIG_USB_PD_I2C_SLAVE_ADDR_FLAGS
-#endif
-
-#ifndef __ASSEMBLER__
-
-/* Timer selection */
-#define TIM_CLOCK32 2
-#define TIM_ADC     3
-
-#include "gpio_signal.h"
-
-/* ADC signal */
-enum adc_channel {
-	ADC_C0_CC1_PD = 0,
-	ADC_C1_CC1_PD,
-	ADC_C0_CC2_PD,
-	ADC_C1_CC2_PD,
-	ADC_VBUS,
-	/* Number of ADC channels */
-	ADC_CH_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_ILIM = 0,
-	/* Number of PWM channels */
-	PWM_CH_COUNT
-};
-
-/* Standard-current Rp */
-#define PD_SRC_VNC           PD_SRC_DEF_VNC_MV
-#define PD_SRC_RD_THRESHOLD  PD_SRC_DEF_RD_THRESH_MV
-
-/*
- * delay to turn on the power supply max is ~16ms.
- * delay to turn off the power supply max is about ~180ms.
- */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
-
-/* delay to turn on/off vconn */
-#define PD_VCONN_SWAP_DELAY 5000 /* us */
-
-/* Define typical operating power and max power */
-#define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       60000
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_VOLTAGE_MV     20000
-
-/* Charge current limit min / max, based on PWM duty cycle */
-#define PWM_0_MA	500
-#define PWM_100_MA	4000
-
-/* Map current in milli-amps to PWM duty cycle percentage */
-#define MA_TO_PWM(curr) (((curr) - PWM_0_MA) * 100 / (PWM_100_MA - PWM_0_MA))
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/samus_pd/build.mk b/board/samus_pd/build.mk
deleted file mode 100644
index 1946fc303c..0000000000
--- a/board/samus_pd/build.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-# -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-# the IC is STmicro STM32F072VBH6
-CHIP:=stm32
-CHIP_FAMILY:=stm32f0
-CHIP_VARIANT:=stm32f07x
-
-# Not enough SRAM: Disable all tests
-test-list-y=
-
-board-y=board.o
-board-$(CONFIG_USB_POWER_DELIVERY)+=usb_mux.o usb_pd_policy.o
diff --git a/board/samus_pd/ec.tasklist b/board/samus_pd/ec.tasklist
deleted file mode 100644
index 297661df0b..0000000000
--- a/board/samus_pd/ec.tasklist
+++ /dev/null
@@ -1,17 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/samus_pd/gpio.inc b/board/samus_pd/gpio.inc
deleted file mode 100644
index a22f15375f..0000000000
--- a/board/samus_pd/gpio.inc
+++ /dev/null
@@ -1,137 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Interrupts */
-GPIO_INT(USB_C0_VBUS_WAKE,       PIN(E, 6),  GPIO_INT_BOTH,    vbus0_evt)
-GPIO_INT(USB_C1_VBUS_WAKE,       PIN(F, 2),  GPIO_INT_BOTH,    vbus1_evt)
-GPIO_INT(USB_C0_BC12_INT_L,      PIN(B, 0),  GPIO_INT_FALLING, usb0_evt)
-GPIO_INT(USB_C1_BC12_INT_L,      PIN(C, 11), GPIO_INT_FALLING, usb1_evt)
-GPIO_INT(PCH_SLP_S0_L,           PIN(C, 14), GPIO_INT_BOTH,    pch_evt)
-GPIO_INT(PCH_SLP_S3_L,           PIN(C, 15), GPIO_INT_BOTH,    pch_evt)
-GPIO_INT(PCH_SLP_S5_L,           PIN(D, 7),  GPIO_INT_BOTH,    pch_evt)
-GPIO_INT(WP_L,                   PIN(D, 2),  GPIO_INT_BOTH,    switch_interrupt)
-
-/* PD RX/TX */
-GPIO(USB_C0_CC1_PD,          PIN(A, 0),  GPIO_ANALOG)
-GPIO(USB_C0_REF,             PIN(A, 1),  GPIO_ANALOG)
-GPIO(USB_C1_CC1_PD,          PIN(A, 2),  GPIO_ANALOG)
-GPIO(USB_C0_CC2_PD,          PIN(A, 4),  GPIO_ANALOG)
-GPIO(USB_C1_CC2_PD,          PIN(A, 5),  GPIO_ANALOG)
-GPIO(USB_C0_REF_PD_ODL,      PIN(A, 6),  GPIO_ODR_LOW)
-
-GPIO(USB_C_CC_EN,            PIN(C, 10), GPIO_OUT_LOW)
-GPIO(USB_C1_CC_TX_EN,        PIN(A, 15), GPIO_OUT_LOW)
-GPIO(USB_C0_CC_TX_EN,        PIN(B, 9),  GPIO_OUT_LOW)
-GPIO(USB_C1_CC1_TX_DATA,     PIN(B, 4),  GPIO_OUT_LOW)
-GPIO(USB_C0_CC1_TX_DATA,     PIN(B, 14), GPIO_OUT_LOW)
-GPIO(USB_C1_CC2_TX_DATA,     PIN(E, 14), GPIO_OUT_LOW)
-GPIO(USB_C0_CC2_TX_DATA,     PIN(D, 3),  GPIO_OUT_LOW)
-
-#if 0
-/* Alternate functions */
-GPIO(USB_C1_TX_CLKOUT,       PIN(B, 1),  GPIO_OUT_LOW)
-GPIO(USB_C0_TX_CLKOUT,       PIN(E, 1),  GPIO_OUT_LOW)
-GPIO(USB_C1_TX_CLKIN,        PIN(B, 3),  GPIO_OUT_LOW)
-GPIO(USB_C0_TX_CLKIN,        PIN(B, 13), GPIO_OUT_LOW)
-#endif
-
-/* Power and muxes control */
-GPIO(PPVAR_BOOSTIN_SENSE,    PIN(C, 1),  GPIO_ANALOG)
-GPIO(PP3300_USB_PD_EN,       PIN(A, 8),  GPIO_OUT_HIGH)
-GPIO(USB_C0_CHARGE_EN_L,     PIN(D, 12), GPIO_OUT_LOW)
-GPIO(USB_C1_CHARGE_EN_L,     PIN(D, 13), GPIO_OUT_LOW)
-GPIO(USB_C0_5V_EN,           PIN(D, 14), GPIO_OUT_LOW)
-GPIO(USB_C1_5V_EN,           PIN(D, 15), GPIO_OUT_LOW)
-GPIO(USB_C0_CC1_VCONN1_EN_L, PIN(D, 8),  GPIO_OUT_HIGH)
-GPIO(USB_C0_CC2_VCONN1_EN_L, PIN(D, 9),  GPIO_OUT_HIGH)
-GPIO(USB_C1_CC1_VCONN1_EN_L, PIN(D, 10), GPIO_OUT_HIGH)
-GPIO(USB_C1_CC2_VCONN1_EN_L, PIN(D, 11), GPIO_OUT_HIGH)
-GPIO(USB_C0_CC_1A5_EN,       PIN(B, 12), GPIO_OUT_LOW)
-GPIO(USB_C1_CC_1A5_EN,       PIN(E, 12), GPIO_OUT_LOW)
-GPIO(ILIM_ADJ_PWM,           PIN(B, 15), GPIO_OUT_LOW)
-
-GPIO(USB_C0_CC1_ODL,         PIN(B, 8),  GPIO_ODR_LOW)
-GPIO(USB_C0_CC2_ODL,         PIN(E, 0),  GPIO_ODR_LOW)
-GPIO(USB_C1_CC1_ODL,         PIN(F, 9),  GPIO_ODR_LOW)
-GPIO(USB_C1_CC2_ODL,         PIN(F, 10), GPIO_ODR_LOW)
-
-GPIO(USB_C_BC12_SEL,         PIN(C, 0),  GPIO_OUT_LOW)
-GPIO(USB_C0_SS1_EN_L,        PIN(E, 2),  GPIO_OUT_HIGH)
-GPIO(USB_C0_SS2_EN_L,        PIN(E, 3),  GPIO_OUT_HIGH)
-GPIO(USB_C1_SS1_EN_L,        PIN(E, 9),  GPIO_OUT_HIGH)
-GPIO(USB_C1_SS2_EN_L,        PIN(E, 10), GPIO_OUT_HIGH)
-GPIO(USB_C0_SS1_DP_MODE,     PIN(E, 4),  GPIO_OUT_HIGH)
-GPIO(USB_C0_SS2_DP_MODE,     PIN(E, 5),  GPIO_OUT_HIGH)
-GPIO(USB_C1_SS1_DP_MODE,     PIN(E, 11), GPIO_OUT_HIGH)
-GPIO(USB_C1_SS2_DP_MODE,     PIN(E, 13), GPIO_OUT_HIGH)
-GPIO(USB_C0_DP_MODE_L,       PIN(E, 8),  GPIO_OUT_HIGH)
-GPIO(USB_C1_DP_MODE_L,       PIN(F, 6),  GPIO_OUT_HIGH)
-GPIO(USB_C0_DP_POLARITY,     PIN(E, 7),  GPIO_OUT_HIGH)
-GPIO(USB_C1_DP_POLARITY,     PIN(F, 3),  GPIO_OUT_HIGH)
-GPIO(USB_C0_DP_HPD,          PIN(F, 0),  GPIO_OUT_LOW)
-GPIO(USB_C1_DP_HPD,          PIN(F, 1),  GPIO_OUT_LOW)
-
-#if 0
-/* Alternate functions */
-GPIO(USB_DM,                 PIN(A, 11), GPIO_ANALOG)
-GPIO(USB_DP,                 PIN(A, 12), GPIO_ANALOG)
-GPIO(UART_TX,                PIN(A, 9),  GPIO_OUT_LOW)
-GPIO(UART_RX,                PIN(A, 10), GPIO_OUT_LOW)
-GPIO(TP64,                   PIN(A, 13), GPIO_ODR_HIGH)
-GPIO(TP71,                   PIN(A, 14), GPIO_ODR_HIGH)
-#endif
-
-/*
- * I2C pins should be configured as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-GPIO(SLAVE_I2C_SCL,          PIN(B, 6),  GPIO_INPUT)
-GPIO(SLAVE_I2C_SDA,          PIN(B, 7),  GPIO_INPUT)
-GPIO(MASTER_I2C_SCL,         PIN(B, 10), GPIO_INPUT)
-GPIO(MASTER_I2C_SDA,         PIN(B, 11), GPIO_INPUT)
-
-/* Case closed debugging. */
-GPIO(EC_INT,                 PIN(B, 2),  GPIO_OUT_LOW)
-GPIO(EC_IN_RW,               PIN(C, 12), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(EC_RST_L,               PIN(C, 13), GPIO_OUT_HIGH)
-GPIO(SPI_FLASH_CS_L,         PIN(D, 0),  GPIO_INPUT)
-GPIO(SPI_FLASH_CSK,          PIN(D, 1),  GPIO_INPUT)
-GPIO(SPI_FLASH_MOSI,         PIN(C, 3),  GPIO_INPUT)
-GPIO(SPI_FLASH_MISO,         PIN(C, 2),  GPIO_INPUT)
-GPIO(EC_JTAG_TCK,            PIN(C, 6),  GPIO_INPUT)
-GPIO(EC_JTAG_TMS,            PIN(C, 7),  GPIO_INPUT)
-GPIO(EC_JTAG_TDO,            PIN(C, 8),  GPIO_INPUT)
-GPIO(EC_JTAG_TDI,            PIN(C, 9),  GPIO_INPUT)
-GPIO(ENTERING_RW,            PIN(B, 5),  GPIO_OUT_LOW)
-GPIO(PD_DISABLE_DEBUG,       PIN(E, 15), GPIO_OUT_HIGH)
-GPIO(PD_DEBUG_EN_L,          PIN(D, 4),  GPIO_INPUT | GPIO_PULL_UP)
-GPIO(PD_SPI_PP3300_EN_L,     PIN(A, 7),  GPIO_OUT_HIGH)
-GPIO(BST_DISABLE,            PIN(A, 3),  GPIO_OUT_LOW)
-
-#if 0
-/* Alternate functions */
-GPIO(EC_UART_TX,             PIN(C, 4),  GPIO_OUT_LOW)
-GPIO(EC_UART_RX,             PIN(C, 5),  GPIO_INPUT)
-GPIO(AP_UART_TX,             PIN(D, 5),  GPIO_OUT_LOW)
-GPIO(AP_UART_RX,             PIN(D, 6),  GPIO_INPUT)
-#endif
-
-ALTERNATE(PIN_MASK(B, 0x0008), 0, MODULE_USB_PD, 0) /* SPI1: SCK(PB3) */
-ALTERNATE(PIN_MASK(B, 0x2000), 0, MODULE_USB_PD, 0) /* SPI2: SCK(PB13) */
-ALTERNATE(PIN_MASK(B, 0x0002), 0, MODULE_USB_PD, 0) /* TIM14_CH1: PB1) */
-ALTERNATE(PIN_MASK(E, 0x0002), 0, MODULE_USB_PD, 0) /* TIM17_CH1: PE1) */
-ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART,   0) /* USART1: PA9/PA10 */
-ALTERNATE(PIN_MASK(D, 0x0060), 0, MODULE_UART,   0) /* USART2: PD5/PD6 */
-ALTERNATE(PIN_MASK(C, 0x0030), 1, MODULE_UART,   0) /* USART3: PC4/PC5 */
-ALTERNATE(PIN_MASK(B, 0x0cc0), 1, MODULE_I2C,    0) /* I2C SLAVE:PB6/7 MASTER:PB10/11 */
-
-#ifdef CONFIG_PWM
-ALTERNATE(PIN_MASK(B, 0x8000), 1, MODULE_PWM,    0) /* ILIM_PWM: PB15 */
-#endif
diff --git a/board/samus_pd/usb_mux.c b/board/samus_pd/usb_mux.c
deleted file mode 100644
index 2213fc41e0..0000000000
--- a/board/samus_pd/usb_mux.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Samus PD-custom USB mux driver. */
-
-#include "common.h"
-#include "gpio.h"
-#include "usb_mux.h"
-#include "util.h"
-
-struct usb_port_mux {
-	enum gpio_signal ss1_en_l;
-	enum gpio_signal ss2_en_l;
-	enum gpio_signal dp_mode_l;
-	enum gpio_signal dp_polarity;
-	enum gpio_signal ss1_dp_mode;
-	enum gpio_signal ss2_dp_mode;
-};
-
-static const struct usb_port_mux mux_gpios[] = {
-	{
-		.ss1_en_l    = GPIO_USB_C0_SS1_EN_L,
-		.ss2_en_l    = GPIO_USB_C0_SS2_EN_L,
-		.dp_mode_l   = GPIO_USB_C0_DP_MODE_L,
-		.dp_polarity = GPIO_USB_C0_DP_POLARITY,
-		.ss1_dp_mode = GPIO_USB_C0_SS1_DP_MODE,
-		.ss2_dp_mode = GPIO_USB_C0_SS2_DP_MODE,
-	},
-	{
-		.ss1_en_l    = GPIO_USB_C1_SS1_EN_L,
-		.ss2_en_l    = GPIO_USB_C1_SS2_EN_L,
-		.dp_mode_l   = GPIO_USB_C1_DP_MODE_L,
-		.dp_polarity = GPIO_USB_C1_DP_POLARITY,
-		.ss1_dp_mode = GPIO_USB_C1_SS1_DP_MODE,
-		.ss2_dp_mode = GPIO_USB_C1_SS2_DP_MODE,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(mux_gpios) == CONFIG_USB_PD_PORT_MAX_COUNT);
-
-
-static int board_init_usb_mux(const struct usb_mux *me)
-{
-	return EC_SUCCESS;
-}
-
-static int board_set_usb_mux(const struct usb_mux *me, mux_state_t mux_state)
-{
-	const struct usb_port_mux *usb_mux = mux_gpios + me->usb_port;
-	int polarity = mux_state & USB_PD_MUX_POLARITY_INVERTED;
-
-	/* reset everything */
-	gpio_set_level(usb_mux->ss1_en_l, 1);
-	gpio_set_level(usb_mux->ss2_en_l, 1);
-	gpio_set_level(usb_mux->dp_mode_l, 1);
-	gpio_set_level(usb_mux->dp_polarity, 1);
-	gpio_set_level(usb_mux->ss1_dp_mode, 1);
-	gpio_set_level(usb_mux->ss2_dp_mode, 1);
-
-	if (!(mux_state & (USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED)))
-		/* everything is already disabled, we can return */
-		return EC_SUCCESS;
-
-	if (mux_state & USB_PD_MUX_USB_ENABLED)
-		/* USB 3.0 uses 2 superspeed lanes */
-		gpio_set_level(polarity ? usb_mux->ss2_dp_mode :
-					  usb_mux->ss1_dp_mode, 0);
-
-	if (mux_state & USB_PD_MUX_DP_ENABLED) {
-		/* DP uses available superspeed lanes (x2 or x4) */
-		gpio_set_level(usb_mux->dp_polarity, polarity);
-		gpio_set_level(usb_mux->dp_mode_l, 0);
-	}
-
-	/* switch on superspeed lanes */
-	gpio_set_level(usb_mux->ss1_en_l, 0);
-	gpio_set_level(usb_mux->ss2_en_l, 0);
-
-	return EC_SUCCESS;
-}
-
-static int board_get_usb_mux(const struct usb_mux *me, mux_state_t *mux_state)
-{
-	const struct usb_port_mux *usb_mux = mux_gpios + me->usb_port;
-
-	*mux_state = 0;
-
-	if (!gpio_get_level(usb_mux->ss1_dp_mode) ||
-	    !gpio_get_level(usb_mux->ss2_dp_mode))
-		*mux_state |= USB_PD_MUX_USB_ENABLED;
-
-	if (!gpio_get_level(usb_mux->dp_mode_l))
-		*mux_state |= USB_PD_MUX_DP_ENABLED;
-
-	if (gpio_get_level(usb_mux->dp_polarity))
-		*mux_state |= USB_PD_MUX_POLARITY_INVERTED;
-
-	return EC_SUCCESS;
-}
-
-const struct usb_mux_driver board_custom_usb_mux_driver = {
-	.init = board_init_usb_mux,
-	.set = board_set_usb_mux,
-	.get = board_get_usb_mux,
-};
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.driver = &board_custom_usb_mux_driver,
-	},
-	{
-		.usb_port = 1,
-		.driver = &board_custom_usb_mux_driver,
-	},
-};
diff --git a/board/samus_pd/usb_pd_config.h b/board/samus_pd/usb_pd_config.h
deleted file mode 100644
index c81b0bf113..0000000000
--- a/board/samus_pd/usb_pd_config.h
+++ /dev/null
@@ -1,278 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "chip/stm32/registers.h"
-#include "gpio.h"
-#include "usb_mux.h"
-
-/* USB Power delivery board configuration */
-
-#ifndef __CROS_EC_USB_PD_CONFIG_H
-#define __CROS_EC_USB_PD_CONFIG_H
-
-/* Timer selection for baseband PD communication */
-#define TIM_CLOCK_PD_TX_C0 17
-#define TIM_CLOCK_PD_RX_C0 1
-#define TIM_CLOCK_PD_TX_C1 14
-#define TIM_CLOCK_PD_RX_C1 3
-
-#define TIM_CLOCK_PD_TX(p) ((p) ? TIM_CLOCK_PD_TX_C1 : TIM_CLOCK_PD_TX_C0)
-#define TIM_CLOCK_PD_RX(p) ((p) ? TIM_CLOCK_PD_RX_C1 : TIM_CLOCK_PD_RX_C0)
-
-/* Timer channel */
-#define TIM_RX_CCR_C0 1
-#define TIM_RX_CCR_C1 1
-#define TIM_TX_CCR_C0 1
-#define TIM_TX_CCR_C1 1
-
-/* RX timer capture/compare register */
-#define TIM_CCR_C0 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C0, TIM_RX_CCR_C0))
-#define TIM_CCR_C1 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C1, TIM_RX_CCR_C1))
-#define TIM_RX_CCR_REG(p) ((p) ? TIM_CCR_C1 : TIM_CCR_C0)
-
-/* TX and RX timer register */
-#define TIM_REG_TX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_TX_C0))
-#define TIM_REG_RX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_RX_C0))
-#define TIM_REG_TX_C1 (STM32_TIM_BASE(TIM_CLOCK_PD_TX_C1))
-#define TIM_REG_RX_C1 (STM32_TIM_BASE(TIM_CLOCK_PD_RX_C1))
-#define TIM_REG_TX(p) ((p) ? TIM_REG_TX_C1 : TIM_REG_TX_C0)
-#define TIM_REG_RX(p) ((p) ? TIM_REG_RX_C1 : TIM_REG_RX_C0)
-
-/* use the hardware accelerator for CRC */
-#define CONFIG_HW_CRC
-
-/* TX uses SPI1 on PB3-4 for port C1, SPI2 on PB 13-14 for port C0 */
-#define SPI_REGS(p) ((p) ? STM32_SPI1_REGS : STM32_SPI2_REGS)
-static inline void spi_enable_clock(int port)
-{
-	if (port == 0)
-		STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
-	else
-		STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1;
-}
-
-/* DMA for transmit uses DMA CH7 for C0 and DMA_CH3 for C1 */
-#define DMAC_SPI_TX(p) ((p) ? STM32_DMAC_CH3 : STM32_DMAC_CH7)
-
-/* RX uses COMP1 and TIM1 CH1 on port C0 and COMP2 and TIM3_CH1 for port C1*/
-#define CMP1OUTSEL STM32_COMP_CMP1OUTSEL_TIM1_IC1
-#define CMP2OUTSEL STM32_COMP_CMP2OUTSEL_TIM3_IC1
-
-#define TIM_TX_CCR_IDX(p) ((p) ? TIM_TX_CCR_C1 : TIM_TX_CCR_C0)
-#define TIM_RX_CCR_IDX(p) ((p) ? TIM_RX_CCR_C1 : TIM_RX_CCR_C0)
-#define TIM_CCR_CS  1
-#define EXTI_COMP_MASK(p) ((p) ? BIT(22) : BIT(21))
-#define IRQ_COMP STM32_IRQ_COMP
-/* triggers packet detection on comparator falling edge */
-#define EXTI_XTSR STM32_EXTI_FTSR
-
-/* DMA for receive uses DMA_CH2 for C0 and DMA_CH6 for C1 */
-#define DMAC_TIM_RX(p) ((p) ? STM32_DMAC_CH6 : STM32_DMAC_CH2)
-
-/* the pins used for communication need to be hi-speed */
-static inline void pd_set_pins_speed(int port)
-{
-	if (port == 0) {
-		/* 40 MHz pin speed on SPI PB13/14 */
-		STM32_GPIO_OSPEEDR(GPIO_B) |= 0x3C000000;
-		/* 40 MHz pin speed on TIM17_CH1 (PE1) */
-		STM32_GPIO_OSPEEDR(GPIO_E) |= 0x0000000C;
-	} else {
-		/* 40 MHz pin speed on SPI PB3/4 */
-		STM32_GPIO_OSPEEDR(GPIO_B) |= 0x000003C0;
-		/* 40 MHz pin speed on TIM14_CH1 (PB1) */
-		STM32_GPIO_OSPEEDR(GPIO_B) |= 0x0000000C;
-	}
-}
-
-/* Reset SPI peripheral used for TX */
-static inline void pd_tx_spi_reset(int port)
-{
-	if (port == 0) {
-		/* Reset SPI2 */
-		STM32_RCC_APB1RSTR |= BIT(14);
-		STM32_RCC_APB1RSTR &= ~BIT(14);
-	} else {
-		/* Reset SPI1 */
-		STM32_RCC_APB2RSTR |= BIT(12);
-		STM32_RCC_APB2RSTR &= ~BIT(12);
-	}
-}
-
-/* Drive the CC line from the TX block */
-static inline void pd_tx_enable(int port, int polarity)
-{
-	if (port == 0) {
-		/* put SPI function on TX pin */
-		if (polarity) /* PD3 is SPI2 MISO */
-			gpio_set_alternate_function(GPIO_D, 0x0008, 1);
-		else /* PB14 is SPI2 MISO */
-			gpio_set_alternate_function(GPIO_B, 0x4000, 0);
-
-		/* set the low level reference */
-		gpio_set_level(GPIO_USB_C0_CC_TX_EN, 1);
-	} else {
-		/* put SPI function on TX pin */
-		if (polarity) /* PE14 is SPI1 MISO */
-			gpio_set_alternate_function(GPIO_E, 0x4000, 1);
-		else /* PB4 is SPI1 MISO */
-			gpio_set_alternate_function(GPIO_B, 0x0010, 0);
-
-		/* set the low level reference */
-		gpio_set_level(GPIO_USB_C1_CC_TX_EN, 1);
-	}
-}
-
-/* Put the TX driver in Hi-Z state */
-static inline void pd_tx_disable(int port, int polarity)
-{
-	if (port == 0) {
-		/* output low on SPI TX to disable the FET */
-		if (polarity) /* PD3 is SPI2 MISO */
-			STM32_GPIO_MODER(GPIO_D) = (STM32_GPIO_MODER(GPIO_D)
-						   & ~(3 << (2*3)))
-						   |  (1 << (2*3));
-		else /* PB14 is SPI2 MISO */
-			STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B)
-						   & ~(3 << (2*14)))
-						   |  (1 << (2*14));
-
-		/* put the low level reference in Hi-Z */
-		gpio_set_level(GPIO_USB_C0_CC_TX_EN, 0);
-	} else {
-		/* output low on SPI TX to disable the FET */
-		if (polarity) /* PE14 is SPI1 MISO */
-			STM32_GPIO_MODER(GPIO_E) = (STM32_GPIO_MODER(GPIO_E)
-						   & ~(3 << (2*14)))
-						   |  (1 << (2*14));
-		else /* PB4 is SPI1 MISO */
-			STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B)
-						   & ~(3 << (2*4)))
-						   |  (1 << (2*4));
-
-		/* put the low level reference in Hi-Z */
-		gpio_set_level(GPIO_USB_C1_CC_TX_EN, 0);
-	}
-}
-
-/* we know the plug polarity, do the right configuration */
-static inline void pd_select_polarity(int port, int polarity)
-{
-	uint32_t val = STM32_COMP_CSR;
-
-	/* Use window mode so that COMP1 and COMP2 share non-inverting input */
-	val |= STM32_COMP_CMP1EN | STM32_COMP_CMP2EN | STM32_COMP_WNDWEN;
-
-	if (port == 0) {
-		/* use the right comparator inverted input for COMP1 */
-		STM32_COMP_CSR = (val & ~STM32_COMP_CMP1INSEL_MASK) |
-				 (polarity ? STM32_COMP_CMP1INSEL_INM4
-					   : STM32_COMP_CMP1INSEL_INM6);
-	} else {
-		/* use the right comparator inverted input for COMP2 */
-		STM32_COMP_CSR = (val & ~STM32_COMP_CMP2INSEL_MASK) |
-				 (polarity ? STM32_COMP_CMP2INSEL_INM5
-					   : STM32_COMP_CMP2INSEL_INM6);
-	}
-}
-
-/* Initialize pins used for TX and put them in Hi-Z */
-static inline void pd_tx_init(void)
-{
-	gpio_config_module(MODULE_USB_PD, 1);
-}
-
-static inline void pd_set_host_mode(int port, int enable)
-{
-	if (port == 0) {
-		if (enable) {
-			/* We never charging in power source mode */
-			gpio_set_level(GPIO_USB_C0_CHARGE_EN_L, 1);
-			/* High-Z is used for host mode. */
-			gpio_set_level(GPIO_USB_C0_CC1_ODL, 1);
-			gpio_set_level(GPIO_USB_C0_CC2_ODL, 1);
-		} else {
-			/* Kill VBUS power supply */
-			gpio_set_level(GPIO_USB_C0_5V_EN, 0);
-			/* Pull low for device mode. */
-			gpio_set_level(GPIO_USB_C0_CC1_ODL, 0);
-			gpio_set_level(GPIO_USB_C0_CC2_ODL, 0);
-			/* Let charge_manager decide to enable the port */
-		}
-	} else {
-		if (enable) {
-			/* We never charging in power source mode */
-			gpio_set_level(GPIO_USB_C1_CHARGE_EN_L, 1);
-			/* High-Z is used for host mode. */
-			gpio_set_level(GPIO_USB_C1_CC1_ODL, 1);
-			gpio_set_level(GPIO_USB_C1_CC2_ODL, 1);
-		} else {
-			/* Kill VBUS power supply */
-			gpio_set_level(GPIO_USB_C1_5V_EN, 0);
-			/* Pull low for device mode. */
-			gpio_set_level(GPIO_USB_C1_CC1_ODL, 0);
-			gpio_set_level(GPIO_USB_C1_CC2_ODL, 0);
-			/* Let charge_manager decide to enable the port */
-		}
-	}
-}
-
-/**
- * Initialize various GPIOs and interfaces to safe state at start of pd_task.
- *
- * These include:
- *   VBUS, charge path based on power role.
- *   Physical layer CC transmit.
- *   VCONNs disabled.
- *
- * @param port        USB-C port number
- * @param power_role  Power role of device
- */
-static inline void pd_config_init(int port, uint8_t power_role)
-{
-	/*
-	 * Set CC pull resistors, and charge_en and vbus_en GPIOs to match
-	 * the initial role.
-	 */
-	pd_set_host_mode(port, power_role);
-
-	/* Initialize TX pins and put them in Hi-Z */
-	pd_tx_init();
-
-	/* Reset mux ... for NONE polarity doesn't matter */
-	usb_mux_set(port, USB_PD_MUX_NONE, USB_SWITCH_DISCONNECT, 0);
-
-	if (port == 0) {
-			gpio_set_level(GPIO_USB_C0_CC1_VCONN1_EN_L, 1);
-			gpio_set_level(GPIO_USB_C0_CC2_VCONN1_EN_L, 1);
-			gpio_set_level(GPIO_USB_C0_DP_HPD, 0);
-	} else {
-			gpio_set_level(GPIO_USB_C1_CC1_VCONN1_EN_L, 1);
-			gpio_set_level(GPIO_USB_C1_CC2_VCONN1_EN_L, 1);
-			gpio_set_level(GPIO_USB_C1_DP_HPD, 0);
-	}
-}
-
-static inline int pd_adc_read(int port, int cc)
-{
-	if (port == 0)
-		return adc_read_channel(cc ? ADC_C0_CC2_PD : ADC_C0_CC1_PD);
-	else
-		return adc_read_channel(cc ? ADC_C1_CC2_PD : ADC_C1_CC1_PD);
-}
-
-static inline void pd_set_vconn(int port, int polarity, int enable)
-{
-	/* Set VCONN on the opposite CC line from the polarity */
-	if (port == 0)
-		gpio_set_level(polarity ? GPIO_USB_C0_CC1_VCONN1_EN_L :
-					  GPIO_USB_C0_CC2_VCONN1_EN_L, !enable);
-	else
-		gpio_set_level(polarity ? GPIO_USB_C1_CC1_VCONN1_EN_L :
-					  GPIO_USB_C1_CC2_VCONN1_EN_L, !enable);
-}
-
-#endif /* __CROS_EC_USB_PD_CONFIG_H */
diff --git a/board/samus_pd/usb_pd_policy.c b/board/samus_pd/usb_pd_policy.c
deleted file mode 100644
index 9eed4f77b5..0000000000
--- a/board/samus_pd/usb_pd_policy.c
+++ /dev/null
@@ -1,152 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "atomic.h"
-#include "charge_manager.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-/* Define typical operating power and max power */
-#define OPERATING_POWER_MW 15000
-#define MAX_POWER_MW       60000
-#define MAX_CURRENT_MA     3000
-
-/*
- * Do not request any voltage within this deadband region, where
- * we're not sure whether or not the boost or the bypass will be on.
- */
-#define INPUT_VOLTAGE_DEADBAND_MIN 9700
-#define INPUT_VOLTAGE_DEADBAND_MAX 11999
-
-#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\
-			 PDO_FIXED_COMM_CAP)
-
-const uint32_t pd_src_pdo[] = {
-		PDO_FIXED(5000,   900, PDO_FIXED_FLAGS),
-};
-const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
-
-const uint32_t pd_snk_pdo[] = {
-		PDO_FIXED(5000, 500, PDO_FIXED_FLAGS),
-		PDO_BATT(4750, 21000, 15000),
-		PDO_VAR(4750, 21000, 3000),
-};
-const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
-
-__override int pd_is_valid_input_voltage(int mv)
-{
-	/* Allow any voltage not in the boost bypass deadband */
-	return  (mv < INPUT_VOLTAGE_DEADBAND_MIN) ||
-		(mv > INPUT_VOLTAGE_DEADBAND_MAX);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	/* provide VBUS */
-	gpio_set_level(port ? GPIO_USB_C1_5V_EN : GPIO_USB_C0_5V_EN, 1);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS; /* we are ready */
-}
-
-void pd_power_supply_reset(int port)
-{
-	/* Kill VBUS */
-	gpio_set_level(port ? GPIO_USB_C1_5V_EN : GPIO_USB_C0_5V_EN, 0);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return gpio_get_level(port ? GPIO_USB_C1_VBUS_WAKE :
-				     GPIO_USB_C0_VBUS_WAKE);
-}
-
-int pd_check_vconn_swap(int port)
-{
-	/* in S5, do not allow vconn swap since pp5000 rail is off */
-	return gpio_get_level(GPIO_PCH_SLP_S5_L);
-}
-
-/* ----------------- Vendor Defined Messages ------------------ */
-#define PORT_TO_HPD(port) ((port) ? GPIO_USB_C1_DP_HPD : GPIO_USB_C0_DP_HPD)
-__override void svdm_dp_post_config(int port)
-{
-	dp_flags[port] |= DP_FLAGS_DP_ON;
-	if (!(dp_flags[port] & DP_FLAGS_HPD_HI_PENDING))
-		return;
-
-	gpio_set_level(PORT_TO_HPD(port), 1);
-}
-
-static void hpd0_irq_deferred(void)
-{
-	gpio_set_level(GPIO_USB_C0_DP_HPD, 1);
-}
-
-static void hpd1_irq_deferred(void)
-{
-	gpio_set_level(GPIO_USB_C1_DP_HPD, 1);
-}
-
-DECLARE_DEFERRED(hpd0_irq_deferred);
-DECLARE_DEFERRED(hpd1_irq_deferred);
-#define PORT_TO_HPD_IRQ_DEFERRED(port) ((port) ?			\
-					&hpd1_irq_deferred_data :	\
-					&hpd0_irq_deferred_data)
-
-__override int svdm_dp_attention(int port, uint32_t *payload)
-{
-	int cur_lvl;
-	int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]);
-	int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]);
-	enum gpio_signal hpd = PORT_TO_HPD(port);
-	cur_lvl = gpio_get_level(hpd);
-
-	dp_status[port] = payload[1];
-
-	/* Its initial DP status message prior to config */
-	if (!(dp_flags[port] & DP_FLAGS_DP_ON)) {
-		if (lvl)
-			dp_flags[port] |= DP_FLAGS_HPD_HI_PENDING;
-		return 1;
-	}
-
-	if (irq & cur_lvl) {
-		gpio_set_level(hpd, 0);
-		hook_call_deferred(PORT_TO_HPD_IRQ_DEFERRED(port),
-				   HPD_DSTREAM_DEBOUNCE_IRQ);
-	} else if (irq & !cur_lvl) {
-		CPRINTF("ERR:HPD:IRQ&LOW\n");
-		return 0; /* nak */
-	} else {
-		gpio_set_level(hpd, lvl);
-	}
-	/* ack */
-	return 1;
-}
-
-__override void svdm_exit_dp_mode(int port)
-{
-	svdm_safe_dp_mode(port);
-	gpio_set_level(PORT_TO_HPD(port), 0);
-}
diff --git a/board/sasuke/battery.c b/board/sasuke/battery.c
new file mode 100644
index 0000000000..c06f88ddfd
--- /dev/null
+++ b/board/sasuke/battery.c
@@ -0,0 +1,171 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "charge_state.h"
+#include "common.h"
+#include "hooks.h"
+#include "usb_pd.h"
+#include "util.h"
+
+#define CHARGING_CURRENT_REDUCE 4000
+/*
+ * Battery info for all sasuke battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ *
+ * Battery FET Status in Manufacture Access : bit15 & bit14
+ *  b'00 - dfet : on / cfet : on
+ *  b'01 - dfet : on / cfet : off
+ *  b'10 - dfet : off / cfet : off
+ *  b'11 - dfet : off / cfet : on
+ *  The value b'10 is disconnect_val, so we can use b'01 for cfet_off_val
+ */
+const struct board_batt_params board_battery_info[] = {
+	/* SDI Battery Information */
+	[BATTERY_SDI] = {
+		.fuel_gauge = {
+			.manuf_name = "SDI",
+			.device_name = "4432D53",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 0,
+				.reg_addr = 0x00,
+				.reg_mask = 0xc000,
+				.disconnect_val = 0x8000,
+				.cfet_mask = 0xc000,
+				.cfet_off_val = 0x2000,
+			}
+		},
+		.batt_info = {
+			.voltage_max            = 8760,
+			.voltage_normal         = 7720, /* mV */
+			.voltage_min            = 6000, /* mV */
+			.precharge_current      = 200,  /* mA */
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 45,
+			.charging_min_c         = 0,
+			.charging_max_c         = 50,
+			.discharging_min_c      = -20,
+			.discharging_max_c      = 70,
+		},
+	},
+	/* SWD(Sunwoda) Battery Information */
+	[BATTERY_SWD] = {
+		.fuel_gauge = {
+			.manuf_name = "SWD",
+			.device_name = "4432W53",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 0,
+				.reg_addr = 0x00,
+				.reg_mask = 0xc000,
+				.disconnect_val = 0x8000,
+				.cfet_mask = 0xc000,
+				.cfet_off_val = 0x2000,
+			}
+		},
+		.batt_info = {
+			.voltage_max            = 8760,
+			.voltage_normal         = 7720, /* mV */
+			.voltage_min            = 6000, /* mV */
+			.precharge_current      = 200,  /* mA */
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 45,
+			.charging_min_c         = 0,
+			.charging_max_c         = 50,
+			.discharging_min_c      = -20,
+			.discharging_max_c      = 70,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SDI;
+
+int charger_profile_override(struct charge_state_data *curr)
+{
+	int current;
+	int voltage;
+
+	current = curr->requested_current;
+	voltage = curr->requested_voltage;
+
+	voltage -= 100;
+	if (current > CHARGING_CURRENT_REDUCE)
+		current -= (current / 10);
+
+	curr->requested_voltage = MIN(curr->requested_voltage, voltage);
+	curr->requested_current = MIN(curr->requested_current, current);
+
+	return 0;
+}
+
+/* Customs options controllable by host command. */
+#define PARAM_FASTCHARGE (CS_PARAM_CUSTOM_PROFILE_MIN + 0)
+
+enum ec_status charger_profile_override_get_param(uint32_t param,
+						  uint32_t *value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+enum ec_status charger_profile_override_set_param(uint32_t param,
+						  uint32_t value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+/* Lower our input voltage to 5V in S0iX when battery is full. */
+#define PD_VOLTAGE_WHEN_FULL 5000
+static void reduce_input_voltage_when_full(void)
+{
+	static int saved_input_voltage = -1;
+	int max_pd_voltage_mv = pd_get_max_voltage();
+	int port;
+
+	if (charge_get_percent() == 100 &&
+	    chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
+		if (max_pd_voltage_mv != PD_VOLTAGE_WHEN_FULL) {
+			saved_input_voltage = max_pd_voltage_mv;
+			max_pd_voltage_mv = PD_VOLTAGE_WHEN_FULL;
+		}
+	} else if (saved_input_voltage != -1) {
+		if (max_pd_voltage_mv == PD_VOLTAGE_WHEN_FULL)
+			max_pd_voltage_mv = saved_input_voltage;
+		saved_input_voltage = -1;
+	}
+
+	if (pd_get_max_voltage() != max_pd_voltage_mv) {
+		for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++)
+			pd_set_external_voltage_limit(port, max_pd_voltage_mv);
+	}
+}
+DECLARE_HOOK(HOOK_SECOND, reduce_input_voltage_when_full, HOOK_PRIO_DEFAULT);
diff --git a/board/sasuke/board.c b/board/sasuke/board.c
new file mode 100644
index 0000000000..502fa60bd5
--- /dev/null
+++ b/board/sasuke/board.c
@@ -0,0 +1,772 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Waddledoo board-specific configuration */
+
+#include "adc_chip.h"
+#include "button.h"
+#include "cbi_fw_config.h"
+#include "cbi_ssfc.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "chipset.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "cros_board_info.h"
+#include "driver/bc12/pi3usb9201.h"
+#include "driver/charger/isl923x.h"
+#include "driver/retimer/nb7v904m.h"
+#include "driver/tcpm/raa489000.h"
+#include "driver/tcpm/tcpci.h"
+#include "driver/temp_sensor/thermistor.h"
+#include "driver/usb_mux/pi3usb3x532.h"
+#include "driver/usb_mux/ps8743.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "keyboard_8042.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "stdbool.h"
+#include "switch.h"
+#include "system.h"
+#include "task.h"
+#include "temp_sensor.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+#define INT_RECHECK_US 5000
+
+/* C0 interrupt line shared by BC 1.2 and charger */
+static void check_c0_line(void);
+DECLARE_DEFERRED(check_c0_line);
+
+static void notify_c0_chips(void)
+{
+	/*
+	 * The interrupt line is shared between the TCPC and BC 1.2 detection
+	 * chip.  Therefore we'll need to check both ICs.
+	 */
+	schedule_deferred_pd_interrupt(0);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+
+static void check_c0_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		notify_c0_chips();
+		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+	}
+}
+
+static void usb_c0_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c0_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c0_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+}
+
+/* C1 interrupt line shared by BC 1.2, TCPC, and charger */
+static void check_c1_line(void);
+DECLARE_DEFERRED(check_c1_line);
+
+static void notify_c1_chips(void)
+{
+	schedule_deferred_pd_interrupt(1);
+	usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+}
+
+static void check_c1_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips.
+	 */
+	if (!gpio_get_level(GPIO_SUB_C1_INT_EN_RAILS_ODL)) {
+		notify_c1_chips();
+		hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
+	}
+}
+
+static void sub_usb_c1_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c1_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c1_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
+}
+static void sub_hdmi_hpd_interrupt(enum gpio_signal s)
+{
+	int hdmi_hpd_odl = gpio_get_level(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL);
+
+	gpio_set_level(GPIO_EC_AP_USB_C1_HDMI_HPD, !hdmi_hpd_odl);
+}
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_1] = {
+		.name = "TEMP_SENSOR1",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_2] = {
+		.name = "TEMP_SENSOR2",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_SUB_ANALOG] = {
+		.name = "SUB_ANALOG",
+		.input_ch = NPCX_ADC_CH2,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_VSNS_PP3300_A] = {
+		.name = "PP3300_A_PGOOD",
+		.input_ch = NPCX_ADC_CH9,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* Thermistors */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Charger",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+static int board_id = -1;
+static int mux_c1 = SSFC_USB_SS_MUX_DEFAULT;
+
+extern const struct usb_mux_chain usbc0_retimer;
+extern const struct usb_mux usbmux_ps8743;
+
+void board_init(void)
+{
+	int on;
+
+	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
+	check_c0_line();
+
+	if (get_cbi_fw_config_db() == DB_1A_HDMI) {
+		/* Disable i2c on HDMI pins */
+		gpio_config_pin(MODULE_I2C, GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL,
+				0);
+		gpio_config_pin(MODULE_I2C, GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL,
+				0);
+
+		/* Set HDMI and sub-rail enables to output */
+		gpio_set_flags(GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL,
+			       chipset_in_state(CHIPSET_STATE_ON) ?
+				       GPIO_ODR_LOW :
+				       GPIO_ODR_HIGH);
+		gpio_set_flags(GPIO_SUB_C1_INT_EN_RAILS_ODL, GPIO_ODR_HIGH);
+
+		/* Select HDMI option */
+		gpio_set_level(GPIO_HDMI_SEL_L, 0);
+
+		/* Enable interrupt for passing through HPD */
+		gpio_enable_interrupt(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL);
+	} else {
+		/* Set SDA as an input */
+		gpio_set_flags(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL, GPIO_INPUT);
+
+		/* Enable C1 interrupts */
+		gpio_enable_interrupt(GPIO_SUB_C1_INT_EN_RAILS_ODL);
+		check_c1_line();
+	}
+
+	/* Turn on 5V if the system is on, otherwise turn it off. */
+	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
+			      CHIPSET_STATE_SOFT_OFF);
+	board_power_5v_enable(on);
+
+	if (board_id == -1) {
+		uint32_t val;
+
+		if (cbi_get_board_version(&val) == EC_SUCCESS) {
+			board_id = val;
+			if (board_id == 2) {
+				nb7v904m_lpm_disable = 1;
+				nb7v904m_set_aux_ch_switch(
+					usbc0_retimer.mux,
+					NB7V904M_AUX_CH_FLIPPED);
+			}
+		}
+	}
+
+	mux_c1 = get_cbi_ssfc_usb_ss_mux();
+
+	if (mux_c1 == SSFC_USB_SS_MUX_PS8743) {
+		usb_muxes[1].mux = &usbmux_ps8743;
+		usb_muxes[1].next = NULL;
+	}
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+/* Enable HDMI any time the SoC is on */
+static void hdmi_enable(void)
+{
+	if (get_cbi_fw_config_db() == DB_1A_HDMI)
+		gpio_set_level(GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, hdmi_enable, HOOK_PRIO_DEFAULT);
+
+static void hdmi_disable(void)
+{
+	if (get_cbi_fw_config_db() == DB_1A_HDMI)
+		gpio_set_level(GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, hdmi_disable, HOOK_PRIO_DEFAULT);
+
+void board_hibernate(void)
+{
+	/*
+	 * Both charger ICs need to be put into their "low power mode" before
+	 * entering the Z-state.
+	 */
+	if (board_get_charger_chip_count() > 1)
+		raa489000_hibernate(1, true);
+	raa489000_hibernate(0, false);
+}
+
+/* USB-A charging control */
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_USB_A0_VBUS,
+};
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * TODO(b:147316511): Here we could issue a digital reset to the IC,
+	 * unsure if we actually want to do that or not yet.
+	 */
+}
+
+static void set_5v_gpio(int level)
+{
+	gpio_set_level(GPIO_EN_PP5000, level);
+}
+
+__override void board_power_5v_enable(int enable)
+{
+	/*
+	 * Port 0 simply has a GPIO to turn on the 5V regulator, however, 5V is
+	 * generated locally on the sub board and we need to set the comparator
+	 * polarity on the sub board charger IC, or send enable signal to HDMI
+	 * DB.
+	 */
+	set_5v_gpio(!!enable);
+
+	if (get_cbi_fw_config_db() == DB_1A_HDMI) {
+		gpio_set_level(GPIO_SUB_C1_INT_EN_RAILS_ODL, !enable);
+	} else {
+		if (isl923x_set_comparator_inversion(1, !!enable))
+			CPRINTS("Failed to %sable sub rails!",
+				enable ? "en" : "dis");
+	}
+}
+
+__override uint8_t board_get_usb_pd_port_count(void)
+{
+	if (get_cbi_fw_config_db() == DB_1A_HDMI)
+		return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
+	else
+		return CONFIG_USB_PD_PORT_MAX_COUNT;
+}
+
+__override uint8_t board_get_charger_chip_count(void)
+{
+	if (get_cbi_fw_config_db() == DB_1A_HDMI)
+		return CHARGER_NUM - 1;
+	else
+		return CHARGER_NUM;
+}
+
+int board_is_sourcing_vbus(int port)
+{
+	int regval;
+
+	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
+	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count());
+	int i;
+	int old_port;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	old_port = charge_manager_get_active_charge_port();
+
+	CPRINTS("New chg p%d", port);
+
+	/* Disable all ports. */
+	if (port == CHARGE_PORT_NONE) {
+		for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+			tcpc_write(i, TCPC_REG_COMMAND,
+				   TCPC_REG_COMMAND_SNK_CTRL_LOW);
+			raa489000_enable_asgate(i, false);
+		}
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if port is sourcing VBUS. */
+	if (board_is_sourcing_vbus(port)) {
+		CPRINTS("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+		if (i == port)
+			continue;
+
+		if (tcpc_write(i, TCPC_REG_COMMAND,
+			       TCPC_REG_COMMAND_SNK_CTRL_LOW))
+			CPRINTS("p%d: sink path disable failed.", i);
+		raa489000_enable_asgate(i, false);
+	}
+
+	/*
+	 * Stop the charger IC from switching while changing ports.  Otherwise,
+	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
+	 */
+	if (old_port != CHARGE_PORT_NONE)
+		charger_discharge_on_ac(1);
+
+	/* Enable requested charge port. */
+	if (raa489000_enable_asgate(port, true) ||
+	    tcpc_write(port, TCPC_REG_COMMAND,
+		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
+		CPRINTS("p%d: sink path enable failed.", port);
+		charger_discharge_on_ac(0);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	/* Allow the charger IC to begin/continue switching. */
+	charger_discharge_on_ac(0);
+
+	return EC_SUCCESS;
+}
+
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	if (port < 0 || port > board_get_usb_pd_port_count())
+		return;
+
+	raa489000_set_output_current(port, rp);
+}
+
+__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+				       int *ki_div, int *kd, int *kd_div)
+{
+	*kp = 1;
+	*kp_div = 20;
+	*ki = 1;
+	*ki_div = 250;
+	*kd = 0;
+	*kd_div = 1;
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	return pd_check_vbus_level(port, VBUS_PRESENT);
+}
+
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+
+	{
+		.i2c_port = I2C_PORT_SUB_USB_C1,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+};
+
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	{
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+		.flags = PI3USB9201_ALWAYS_POWERED,
+	},
+
+	{
+		.i2c_port = I2C_PORT_SUB_USB_C1,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+		.flags = PI3USB9201_ALWAYS_POWERED,
+	},
+};
+
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0,
+			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
+		},
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+		.drv = &raa489000_tcpm_drv,
+	},
+
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_SUB_USB_C1,
+			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
+		},
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+		.drv = &raa489000_tcpm_drv,
+	},
+};
+
+static int board_nb7v904m_mux_set_c0(const struct usb_mux *me,
+				     mux_state_t mux_state);
+static int board_nb7v904m_mux_set(const struct usb_mux *me,
+				  mux_state_t mux_state);
+static int ps8743_tune_mux(const struct usb_mux *me);
+
+const struct usb_mux_chain usbc0_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = 0,
+			.i2c_port = I2C_PORT_USB_C0,
+			.i2c_addr_flags = NB7V904M_I2C_ADDR0,
+			.driver = &nb7v904m_usb_redriver_drv,
+			.board_set = &board_nb7v904m_mux_set_c0,
+		},
+};
+const struct usb_mux_chain usbc1_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = 1,
+			.i2c_port = I2C_PORT_SUB_USB_C1,
+			.i2c_addr_flags = NB7V904M_I2C_ADDR0,
+			.driver = &nb7v904m_usb_redriver_drv,
+			.board_set = &board_nb7v904m_mux_set,
+		},
+};
+
+const struct usb_mux usbmux_ps8743 = {
+	.usb_port = 1,
+	.i2c_port = I2C_PORT_SUB_USB_C1,
+	.i2c_addr_flags = PS8743_I2C_ADDR0_FLAG,
+	.driver = &ps8743_usb_mux_driver,
+	.board_init = &ps8743_tune_mux,
+};
+
+struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
+				.driver = &pi3usb3x532_usb_mux_driver,
+			},
+		.next = &usbc0_retimer,
+	},
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_SUB_USB_C1,
+				.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
+				.driver = &pi3usb3x532_usb_mux_driver,
+			},
+		.next = &usbc1_retimer,
+	}
+};
+/* USB Mux C1 : board_init of PS8743 */
+static int ps8743_tune_mux(const struct usb_mux *me)
+{
+	ps8743_tune_usb_eq(me, PS8743_USB_EQ_TX_3_6_DB,
+			   PS8743_USB_EQ_RX_16_0_DB);
+
+	return EC_SUCCESS;
+}
+
+/* USB Mux C0 */
+static int board_nb7v904m_mux_set_c0(const struct usb_mux *me,
+				     mux_state_t mux_state)
+{
+	int rv = EC_SUCCESS;
+	int flipped = !!(mux_state & USB_PD_MUX_POLARITY_INVERTED);
+
+	if (board_id == -1) {
+		uint32_t val;
+
+		if (cbi_get_board_version(&val) == EC_SUCCESS)
+			board_id = val;
+		if (board_id == 2)
+			nb7v904m_lpm_disable = 1;
+	}
+
+	if (mux_state & USB_PD_MUX_USB_ENABLED) {
+		if (mux_state & USB_PD_MUX_DP_ENABLED) {
+			/* USB with DP */
+			if (flipped) {
+				rv |= nb7v904m_tune_usb_set_eq(
+					me, NB7V904M_CH_A_EQ_10_DB,
+					NB7V904M_CH_B_EQ_0_DB,
+					NB7V904M_CH_C_EQ_2_DB,
+					NB7V904M_CH_D_EQ_2_DB);
+				rv |= nb7v904m_tune_usb_flat_gain(
+					me, NB7V904M_CH_A_GAIN_0_DB,
+					NB7V904M_CH_B_GAIN_1P5_DB,
+					NB7V904M_CH_C_GAIN_0_DB,
+					NB7V904M_CH_D_GAIN_0_DB);
+				rv |= nb7v904m_set_loss_profile_match(
+					me, NB7V904M_LOSS_PROFILE_A,
+					NB7V904M_LOSS_PROFILE_A,
+					NB7V904M_LOSS_PROFILE_C,
+					NB7V904M_LOSS_PROFILE_C);
+			} else {
+				rv |= nb7v904m_tune_usb_set_eq(
+					me, NB7V904M_CH_A_EQ_2_DB,
+					NB7V904M_CH_B_EQ_2_DB,
+					NB7V904M_CH_C_EQ_0_DB,
+					NB7V904M_CH_D_EQ_10_DB);
+				rv |= nb7v904m_tune_usb_flat_gain(
+					me, NB7V904M_CH_A_GAIN_0_DB,
+					NB7V904M_CH_B_GAIN_0_DB,
+					NB7V904M_CH_C_GAIN_1P5_DB,
+					NB7V904M_CH_D_GAIN_0_DB);
+				rv |= nb7v904m_set_loss_profile_match(
+					me, NB7V904M_LOSS_PROFILE_C,
+					NB7V904M_LOSS_PROFILE_C,
+					NB7V904M_LOSS_PROFILE_A,
+					NB7V904M_LOSS_PROFILE_A);
+			}
+		} else {
+			/* USB only */
+			if (board_id == 2)
+				rv |= nb7v904m_set_aux_ch_switch(
+					me, NB7V904M_AUX_CH_FLIPPED);
+
+			rv |= nb7v904m_tune_usb_set_eq(me,
+						       NB7V904M_CH_A_EQ_10_DB,
+						       NB7V904M_CH_B_EQ_0_DB,
+						       NB7V904M_CH_C_EQ_0_DB,
+						       NB7V904M_CH_D_EQ_10_DB);
+			rv |= nb7v904m_tune_usb_flat_gain(
+				me, NB7V904M_CH_A_GAIN_0_DB,
+				NB7V904M_CH_B_GAIN_1P5_DB,
+				NB7V904M_CH_C_GAIN_1P5_DB,
+				NB7V904M_CH_D_GAIN_0_DB);
+			rv |= nb7v904m_set_loss_profile_match(
+				me, NB7V904M_LOSS_PROFILE_A,
+				NB7V904M_LOSS_PROFILE_A,
+				NB7V904M_LOSS_PROFILE_A,
+				NB7V904M_LOSS_PROFILE_A);
+		}
+
+	} else if (mux_state & USB_PD_MUX_DP_ENABLED) {
+		/* 4 lanes DP */
+		rv |= nb7v904m_tune_usb_set_eq(me, NB7V904M_CH_A_EQ_2_DB,
+					       NB7V904M_CH_B_EQ_2_DB,
+					       NB7V904M_CH_C_EQ_2_DB,
+					       NB7V904M_CH_D_EQ_2_DB);
+		rv |= nb7v904m_tune_usb_flat_gain(me, NB7V904M_CH_A_GAIN_0_DB,
+						  NB7V904M_CH_B_GAIN_0_DB,
+						  NB7V904M_CH_C_GAIN_0_DB,
+						  NB7V904M_CH_D_GAIN_0_DB);
+		rv |= nb7v904m_set_loss_profile_match(
+			me, NB7V904M_LOSS_PROFILE_C, NB7V904M_LOSS_PROFILE_C,
+			NB7V904M_LOSS_PROFILE_C, NB7V904M_LOSS_PROFILE_C);
+	}
+
+	return rv;
+}
+
+/* USB Mux */
+static int board_nb7v904m_mux_set(const struct usb_mux *me,
+				  mux_state_t mux_state)
+{
+	int rv = EC_SUCCESS;
+	int flipped = !!(mux_state & USB_PD_MUX_POLARITY_INVERTED);
+
+	if (mux_state & USB_PD_MUX_USB_ENABLED) {
+		/* USB with DP */
+		if (mux_state & USB_PD_MUX_DP_ENABLED) {
+			if (flipped) {
+				rv |= nb7v904m_tune_usb_set_eq(
+					me, NB7V904M_CH_A_EQ_10_DB,
+					NB7V904M_CH_ALL_SKIP_EQ,
+					NB7V904M_CH_ALL_SKIP_EQ,
+					NB7V904M_CH_D_EQ_4_DB);
+				rv |= nb7v904m_tune_usb_flat_gain(
+					me, NB7V904M_CH_ALL_SKIP_GAIN,
+					NB7V904M_CH_B_GAIN_3P5_DB,
+					NB7V904M_CH_C_GAIN_0_DB,
+					NB7V904M_CH_ALL_SKIP_GAIN);
+				rv |= nb7v904m_set_loss_profile_match(
+					me, NB7V904M_LOSS_PROFILE_A,
+					NB7V904M_LOSS_PROFILE_A,
+					NB7V904M_LOSS_PROFILE_D,
+					NB7V904M_LOSS_PROFILE_D);
+			} else {
+				rv |= nb7v904m_tune_usb_set_eq(
+					me, NB7V904M_CH_A_EQ_4_DB,
+					NB7V904M_CH_ALL_SKIP_EQ,
+					NB7V904M_CH_ALL_SKIP_EQ,
+					NB7V904M_CH_D_EQ_10_DB);
+				rv |= nb7v904m_tune_usb_flat_gain(
+					me, NB7V904M_CH_ALL_SKIP_GAIN,
+					NB7V904M_CH_B_GAIN_0_DB,
+					NB7V904M_CH_C_GAIN_3P5_DB,
+					NB7V904M_CH_ALL_SKIP_GAIN);
+				rv |= nb7v904m_set_loss_profile_match(
+					me, NB7V904M_LOSS_PROFILE_D,
+					NB7V904M_LOSS_PROFILE_D,
+					NB7V904M_LOSS_PROFILE_A,
+					NB7V904M_LOSS_PROFILE_A);
+			}
+		} else {
+			/* USB only */
+			rv |= nb7v904m_tune_usb_set_eq(me,
+						       NB7V904M_CH_A_EQ_10_DB,
+						       NB7V904M_CH_ALL_SKIP_EQ,
+						       NB7V904M_CH_ALL_SKIP_EQ,
+						       NB7V904M_CH_D_EQ_10_DB);
+			rv |= nb7v904m_tune_usb_flat_gain(
+				me, NB7V904M_CH_ALL_SKIP_GAIN,
+				NB7V904M_CH_B_GAIN_3P5_DB,
+				NB7V904M_CH_C_GAIN_3P5_DB,
+				NB7V904M_CH_ALL_SKIP_GAIN);
+			rv |= nb7v904m_set_loss_profile_match(
+				me, NB7V904M_LOSS_PROFILE_A,
+				NB7V904M_LOSS_PROFILE_A,
+				NB7V904M_LOSS_PROFILE_A,
+				NB7V904M_LOSS_PROFILE_A);
+		}
+
+	} else if (mux_state & USB_PD_MUX_DP_ENABLED) {
+		/* 4 lanes DP */
+		rv |= nb7v904m_tune_usb_set_eq(me, NB7V904M_CH_A_EQ_4_DB,
+					       NB7V904M_CH_ALL_SKIP_EQ,
+					       NB7V904M_CH_ALL_SKIP_EQ,
+					       NB7V904M_CH_D_EQ_4_DB);
+		rv |= nb7v904m_tune_usb_flat_gain(me, NB7V904M_CH_ALL_SKIP_GAIN,
+						  NB7V904M_CH_B_GAIN_0_DB,
+						  NB7V904M_CH_C_GAIN_0_DB,
+						  NB7V904M_CH_ALL_SKIP_GAIN);
+		rv |= nb7v904m_set_loss_profile_match(
+			me, NB7V904M_LOSS_PROFILE_D, NB7V904M_LOSS_PROFILE_D,
+			NB7V904M_LOSS_PROFILE_D, NB7V904M_LOSS_PROFILE_D);
+	}
+
+	return rv;
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+	int regval;
+
+	/*
+	 * The interrupt line is shared between the TCPC and BC1.2 detector IC.
+	 * Therefore, go out and actually read the alert registers to report the
+	 * alert status.
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
+			/* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */
+			if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0))
+				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
+
+			if (regval)
+				status |= PD_STATUS_TCPC_ALERT_0;
+		}
+	}
+
+	if (board_get_usb_pd_port_count() > 1 &&
+	    !gpio_get_level(GPIO_SUB_C1_INT_EN_RAILS_ODL)) {
+		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
+			/* TCPCI spec Rev 1.0 says to ignore bits 14:12. */
+			if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0))
+				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
+
+			if (regval)
+				status |= PD_STATUS_TCPC_ALERT_1;
+		}
+	}
+
+	return status;
+}
+
+static const struct ec_response_keybd_config keybd1 = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_FORWARD,		/* T2 */
+		TK_REFRESH,		/* T3 */
+		TK_FULLSCREEN,		/* T4 */
+		TK_OVERVIEW,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	/* No function keys, no numeric keypad and no screenlock key */
+};
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	/*
+	 * Future boards should use fw_config if needed.
+	 */
+
+	return &keybd1;
+}
diff --git a/board/sasuke/board.h b/board/sasuke/board.h
new file mode 100644
index 0000000000..f43c287d8b
--- /dev/null
+++ b/board/sasuke/board.h
@@ -0,0 +1,171 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Waddledoo board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#define VARIANT_DEDEDE_EC_NPCX796FC
+#include "baseboard.h"
+#undef GPIO_VOLUME_UP_L
+#undef GPIO_VOLUME_DOWN_L
+#undef CONFIG_VOLUME_BUTTONS
+
+/* EC console commands */
+#define CONFIG_CMD_TCPC_DUMP
+#define CONFIG_CMD_CHARGER_DUMP
+
+/* Battery */
+#define CONFIG_BATTERY_FUEL_GAUGE
+
+/* Charger */
+#define CONFIG_CHARGER_RAA489000
+#define PD_MAX_VOLTAGE_MV 20000
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_OCPC_DEF_RBATT_MOHMS               \
+	22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \
+	    */
+/*
+ * b/147463641: The charger IC seems to overdraw ~4%, therefore we
+ * reduce our target accordingly.
+ */
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 4
+#define CONFIG_OCPC
+#define CONFIG_CHARGER_PROFILE_OVERRIDE
+#define CONFIG_CHARGE_RAMP_HW
+#undef CONFIG_CHARGER_SINGLE_CHIP
+
+#define CONFIG_BATTERY_CHECK_CHARGE_TEMP_LIMITS
+
+/*
+ * GPIO for C1 interrupts, for baseboard use
+ *
+ * Note this line might already have its pull up disabled for HDMI DBs, but
+ * it should be fine to set again before z-state.
+ */
+#define GPIO_USB_C1_INT_ODL GPIO_SUB_C1_INT_EN_RAILS_ODL
+
+/* Keyboard */
+
+/* LED */
+#define CONFIG_LED_COMMON
+#define CONFIG_LED_ONOFF_STATES
+#define GPIO_BAT_LED_RED_L GPIO_LED_R_ODL
+#define GPIO_BAT_LED_GREEN_L GPIO_LED_G_ODL
+#define GPIO_PWR_LED_BLUE_L GPIO_LED_B_ODL
+
+/* PWM */
+#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */
+
+/* Thermistors */
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_THERMISTOR
+#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
+
+/* USB */
+#define CONFIG_BC12_DETECT_PI3USB9201
+#define CONFIG_USBC_RETIMER_NB7V904M
+#define CONFIG_USB_MUX_RUNTIME_CONFIG
+#define CONFIG_USB_MUX_PS8743
+
+/* USB PD */
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#define CONFIG_USB_PD_TCPM_RAA489000
+#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
+#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
+#define CONFIG_USB_PD_COMM_LOCKED
+
+/* USB defines specific to external TCPCs */
+#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+#define CONFIG_USB_PD_VBUS_DETECT_TCPC
+#define CONFIG_USB_PD_DISCHARGE_TCPC
+#define CONFIG_USB_PD_TCPC_LOW_POWER
+
+/* Variant references the TCPCs to determine Vbus sourcing */
+#define CONFIG_USB_PD_5V_EN_CUSTOM
+
+#undef PD_POWER_SUPPLY_TURN_ON_DELAY
+#undef PD_POWER_SUPPLY_TURN_OFF_DELAY
+#undef CONFIG_USBC_VCONN_SWAP_DELAY_US
+/* 20% margin added for these timings */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 13080 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 16080 /* us */
+#undef CONFIG_USBC_VCONN_SWAP_DELAY_US
+#define CONFIG_USBC_VCONN_SWAP_DELAY_US 787 /* us */
+
+/* USB Type A Features */
+#define USB_PORT_COUNT 1
+#undef CONFIG_USB_PORT_POWER_SMART_PORT_COUNT
+#define CONFIG_USB_PORT_POWER_SMART_PORT_COUNT 1
+#define CONFIG_USB_PORT_POWER_SMART
+#define CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY
+#define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_CDP
+#define CONFIG_USB_PORT_POWER_SMART_INVERTED
+#define GPIO_USB1_ILIM_SEL GPIO_EN_USB_A0_5V_SUB
+
+/* I2C configuration */
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
+#define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0
+/* TODO(b:147440290): Need to handle multiple charger ICs */
+#define I2C_PORT_CHARGER I2C_PORT_USB_C0
+
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */
+
+/*
+ * I2C pin names for baseboard
+ *
+ * Note: these lines will be set as i2c on start-up, but this should be
+ * okay since they're ODL.
+ */
+#define GPIO_EC_I2C_SUB_USB_C1_SCL GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL
+#define GPIO_EC_I2C_SUB_USB_C1_SDA GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL
+
+#define CONFIG_MATH_UTIL
+
+/*
+ * There is ccd connection issue on board id = 2.
+ * NB7V904M is needed to be active to resolve this.
+ */
+#define CONFIG_NB7V904M_LPM_OVERRIDE
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum chg_id {
+	CHARGER_PRIMARY,
+	CHARGER_SECONDARY,
+	CHARGER_NUM,
+};
+
+enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT };
+
+enum adc_channel {
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
+	ADC_SUB_ANALOG, /* ADC2 */
+	ADC_VSNS_PP3300_A, /* ADC9 */
+	ADC_CH_COUNT
+};
+
+/* List of possible batteries */
+enum battery_type {
+	BATTERY_SDI,
+	BATTERY_SWD,
+	BATTERY_TYPE_COUNT,
+};
+
+#endif /* !__ASSEMBLER__ */
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/sasuke/build.mk b/board/sasuke/build.mk
new file mode 100644
index 0000000000..1531d1f3ae
--- /dev/null
+++ b/board/sasuke/build.mk
@@ -0,0 +1,14 @@
+# -*- makefile -*-
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx7
+CHIP_VARIANT:=npcx7m7fc
+BASEBOARD:=dedede
+
+board-y=board.o battery.o cbi_ssfc.o led.o usb_pd_policy.o
diff --git a/board/sasuke/cbi_ssfc.c b/board/sasuke/cbi_ssfc.c
new file mode 100644
index 0000000000..4f726ce6a3
--- /dev/null
+++ b/board/sasuke/cbi_ssfc.c
@@ -0,0 +1,41 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi_ssfc.h"
+#include "common.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "hooks.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+/* Cache SSFC on init since we don't expect it to change in runtime */
+static union dedede_cbi_ssfc cached_ssfc;
+BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
+
+static void cbi_ssfc_init(void)
+{
+	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
+		/* Default to 0 when CBI isn't populated */
+		cached_ssfc.raw_value = 0;
+
+	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
+}
+DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
+
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
+{
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
+}
+
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
+{
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
+}
+
+enum ec_ssfc_usb_ss_mux get_cbi_ssfc_usb_ss_mux(void)
+{
+	return (enum ec_ssfc_usb_ss_mux)cached_ssfc.usb_ss_mux;
+}
diff --git a/board/sasuke/cbi_ssfc.h b/board/sasuke/cbi_ssfc.h
new file mode 100644
index 0000000000..7cf6e954a1
--- /dev/null
+++ b/board/sasuke/cbi_ssfc.h
@@ -0,0 +1,76 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _DEDEDE_CBI_SSFC__H_
+#define _DEDEDE_CBI_SSFC__H_
+
+#include "stdint.h"
+
+/****************************************************************************
+ * Dedede CBI Second Source Factory Cache
+ */
+
+/*
+ * Base Sensor (Bits 0-2)
+ */
+enum ec_ssfc_base_sensor {
+	SSFC_SENSOR_BASE_DEFAULT = 0,
+	SSFC_SENSOR_BMI160 = 1,
+	SSFC_SENSOR_ICM426XX = 2,
+	SSFC_SENSOR_LSM6DSM = 3,
+	SSFC_SENSOR_ICM42607 = 4
+};
+
+/*
+ * Lid Sensor (Bits 3-5)
+ */
+enum ec_ssfc_lid_sensor {
+	SSFC_SENSOR_LID_DEFAULT = 0,
+	SSFC_SENSOR_BMA255 = 1,
+	SSFC_SENSOR_KX022 = 2,
+	SSFC_SENSOR_LIS2DWL = 3
+};
+
+/*
+ * USB SuperSpeed Mux (Bits 6-8)
+ */
+enum ec_ssfc_usb_ss_mux {
+	SSFC_USB_SS_MUX_DEFAULT = 0,
+	SSFC_USB_SS_MUX_PS8743 = 1,
+	SSFC_USB_SS_MUX_PI3USBX532 = 2,
+};
+
+union dedede_cbi_ssfc {
+	struct {
+		uint32_t base_sensor : 3;
+		uint32_t lid_sensor : 3;
+		uint32_t usb_ss_mux : 3;
+		uint32_t reserved_2 : 23;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Get the Base sensor type from SSFC_CONFIG.
+ *
+ * @return the Base sensor board type.
+ */
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
+
+/**
+ * Get the Lid sensor type from SSFC_CONFIG.
+ *
+ * @return the Lid sensor board type.
+ */
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
+
+/**
+ * Get the USB SuperSpeed Mux type from SSFC_CONFIG
+ *
+ * @return the USB SuperSpeed Mux type
+ */
+enum ec_ssfc_usb_ss_mux get_cbi_ssfc_usb_ss_mux(void);
+
+#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/sasuke/ec.tasklist b/board/sasuke/ec.tasklist
new file mode 100644
index 0000000000..17d4f989b3
--- /dev/null
+++ b/board/sasuke/ec.tasklist
@@ -0,0 +1,24 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/sasuke/gpio.inc b/board/sasuke/gpio.inc
new file mode 100644
index 0000000000..46069c35eb
--- /dev/null
+++ b/board/sasuke/gpio.inc
@@ -0,0 +1,142 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first.
+ */
+
+/* Power Interrupts */
+GPIO_INT(SLP_S0_L,		 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,		 PIN(A, 5), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(SLP_S4_L,		 PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,		 PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(RSMRST_PWRGD_L,	 PIN(C, 6), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID1,	 PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(CPU_C10_GATE_L,	 PIN(6, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID0,	 PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, power_signal_interrupt)
+GPIO_INT(PG_VCCIO_EXT_OD,	 PIN(B, 0), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(PG_PP5000_U_OD,	 PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_DRAM_OD,		 PIN(E, 4), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(PG_PP1050_ST_OD,	 PIN(4, 2), GPIO_INT_BOTH, power_signal_interrupt)
+
+/* USB-C interrupts */
+GPIO_INT(USB_C0_INT_ODL,	 		PIN(6, 2), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt)
+GPIO_INT(SUB_C1_INT_EN_RAILS_ODL,		PIN(F, 5), GPIO_INT_FALLING | GPIO_PULL_UP, sub_usb_c1_interrupt) /* C1 interrupt OR 5V power en */
+GPIO_INT(EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL,	PIN(9, 1), GPIO_INT_BOTH, sub_hdmi_hpd_interrupt) /* C1 I2C SDA OR HDMI_HPD */
+
+/* Button interrupts */
+GPIO_INT(H1_EC_PWR_BTN_ODL,	 PIN(0, 1), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
+
+/* Other interrupts */
+GPIO_INT(LID_OPEN,		 PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)
+GPIO_INT(EC_WP_OD,		 PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+
+/* I2C Ports */
+GPIO(EC_I2C_EEPROM_SCL,			PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SDA,			PIN(B, 2), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SCL,		PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SDA,		PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,			PIN(B, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(EC_I2C_SENSOR_SDA,			PIN(B, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(EC_I2C_USB_C0_SCL,			PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SDA,			PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_SUB_C1_SCL_HDMI_EN_ODL,	PIN(9, 2), GPIO_INPUT) /* C1 I2C SCL OR HDMI en */
+
+/* Extra Sub-board I/O pins */
+GPIO(EC_SUB_IO_1,  PIN(3, 7), GPIO_OUT_LOW)
+GPIO(EC_SUB_IO_2,  PIN(3, 4), GPIO_OUT_LOW)
+
+/* Misc Enables */
+GPIO(EN_VCCIO_EXT,   PIN(6, 1), GPIO_OUT_LOW)
+/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
+GPIO(EN_VCCST,		PIN(A, 7), GPIO_INPUT)
+GPIO(EN_PP3300_A,	PIN(0, 3), GPIO_OUT_LOW)
+GPIO(EN_PP5000_U,	PIN(A, 4), GPIO_OUT_LOW)
+GPIO(EN_SLP_Z,		PIN(8, 3), GPIO_OUT_LOW)
+GPIO(EN_BL_OD,		PIN(D, 3), GPIO_ODR_LOW)
+GPIO(IMVP9_PE,		PIN(E, 0), GPIO_OUT_LOW)
+GPIO(ECH1_PACKET_MODE,	PIN(7, 5), GPIO_OUT_LOW)
+GPIO(LED_R_ODL,		PIN(C, 4), GPIO_OUT_HIGH)
+GPIO(LED_G_ODL,		PIN(C, 3), GPIO_OUT_HIGH)
+GPIO(LED_B_ODL,		PIN(C, 2), GPIO_OUT_HIGH)
+
+/* Power Sequencing */
+GPIO(EC_AP_PSYS,	     PIN(B, 7), GPIO_OUT_LOW)
+GPIO(EC_AP_RSMRST_L,         PIN(A, 6), GPIO_OUT_LOW)
+GPIO(EC_AP_PWR_BTN_ODL,      PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(EC_AP_RTCRST,           PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_AP_WAKE_ODL,         PIN(7, 4), GPIO_ODR_HIGH)
+GPIO(EC_AP_DPWROK,	     PIN(A, 3), GPIO_OUT_LOW)
+GPIO(EC_AP_PCH_PWROK_OD,     PIN(9, 4), GPIO_ODR_LOW)
+GPIO(EC_AP_VCCST_PWRGD_OD,   PIN(B, 1), GPIO_ODR_LOW)
+GPIO(EC_AP_SYS_PWROK,	     PIN(0, 2), GPIO_OUT_LOW)
+GPIO(EC_AP_MKBP_INT_L,	     PIN(7, 0), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_ODL,	     PIN(F, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(EC_ENTERING_RW,	     PIN(E, 3), GPIO_OUT_LOW)
+GPIO(ALL_SYS_PWRGD,	     PIN(A, 0), GPIO_OUT_LOW)
+GPIO(SYS_RST_ODL,	     PIN(C, 5), GPIO_ODR_HIGH)
+GPIO(CCD_MODE_ODL,	     PIN(E, 5), GPIO_ODR_HIGH)
+
+GPIO(EN_USB_A0_5V_SUB,       PIN(9, 7), GPIO_OUT_LOW) /* Don't limit USB-A charging by default - all ports */
+GPIO(EN_USB_A0_VBUS,         PIN(4, 1), GPIO_OUT_LOW) /* Enable USB-A charging - all ports */
+GPIO(EC_AP_USB_C1_HDMI_HPD,  PIN(9, 6), GPIO_OUT_LOW)
+GPIO(EC_AP_USB_C0_HPD,	     PIN(9, 3), GPIO_OUT_LOW)
+GPIO(HDMI_SEL_L,	     PIN(7, 2), GPIO_OUT_HIGH)
+GPIO(EC_BATTERY_PRES_ODL,    PIN(E, 1), GPIO_INPUT)
+
+/*
+ * Waddledoo doesn't have these physical pins coming to the EC but uses other
+ * logic.
+ */
+UNIMPLEMENTED(AC_PRESENT)
+UNIMPLEMENTED(PG_EC_DSW_PWROK)
+UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
+
+/* Alternate Functions */
+/* ADC */
+ALTERNATE(PIN_MASK(F, BIT(0)), 0, MODULE_ADC, 0) /* ADC9 */
+ALTERNATE(PIN_MASK(4, 0x38), 0, MODULE_ADC, 0)   /* ADC0-2 */
+
+/* Keyboard */
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI0, KSI1 */
+ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI2-7 */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO0, KSO1 */
+ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO3-9 */
+ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO10-13 */
+ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO14 */
+GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW)	/* KSO2 inverted */
+
+/* UART */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)  /* UART1 */
+
+/* I2C */
+ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, 0)   /* I2C7 */
+ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)   /* I2C5 */
+ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)   /* I2C2, I2C1 SCL */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)   /* I2C1 SDA */
+
+/* NC pins, enable internal pull-up to avoid floating state. */
+GPIO(GPIO00_NC, PIN(0, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIO32_NC, PIN(3, 2), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIO35_NC, PIN(3, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIO40_NC, PIN(4, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIO50_NC, PIN(5, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIO56_NC, PIN(5, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIO57_NC, PIN(5, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIO60_NC, PIN(6, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIO63_NC, PIN(6, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIO73_NC, PIN(7, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIO80_NC, PIN(8, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIO81_NC, PIN(8, 1), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIO86_NC, PIN(8, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIO95_NC, PIN(9, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOA2_NC, PIN(A, 2), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOD0_NC, PIN(D, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOD1_NC, PIN(D, 1), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOD6_NC, PIN(D, 6), GPIO_INPUT | GPIO_PULL_DOWN)
diff --git a/board/sasuke/led.c b/board/sasuke/led.c
new file mode 100644
index 0000000000..8ccce58d4c
--- /dev/null
+++ b/board/sasuke/led.c
@@ -0,0 +1,134 @@
+/* Copyright 2018 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power and battery LED control for sasuke
+ */
+
+#include "chipset.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
+
+__override const int led_charge_lvl_1 = 1;
+
+__override const int led_charge_lvl_2 = 100;
+
+/* sasuke : There are 3 leds for AC, Battery and Power */
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     1 * LED_ONE_SEC },
+					   { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_GREEN,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED,
+					    0.5 * LED_ONE_SEC },
+					  { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					 { LED_OFF, 1 * LED_ONE_SEC } },
+	};
+
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_BLUE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_power(enum ec_led_colors color)
+{
+	/* Don't set led if led_auto_control is disabled. */
+	if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) ||
+	    !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
+		return;
+	}
+
+	if (color == EC_LED_COLOR_BLUE) {
+		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_ON_LVL);
+	} else {
+		/* LED_OFF and unsupported colors */
+		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_OFF_LVL);
+	}
+}
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	/* Don't set led if led_auto_control is disabled. */
+	if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) ||
+	    !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
+		return;
+	}
+
+	/* Battery leds must be turn off when blue led is on
+	 * because casta has 3-in-1 led.
+	 */
+	if (!gpio_get_level(GPIO_PWR_LED_BLUE_L)) {
+		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); /*red*/
+		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); /*green*/
+		return;
+	}
+
+	switch (color) {
+	case EC_LED_COLOR_GREEN:
+		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); /*red*/
+		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_ON_LVL); /*green*/
+		break;
+	case EC_LED_COLOR_RED:
+		gpio_set_level(GPIO_BAT_LED_RED_L, LED_ON_LVL); /*red*/
+		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); /*green*/
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); /*red*/
+		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); /*green*/
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_GREEN] = 1;
+		brightness_range[EC_LED_COLOR_RED] = 1;
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		brightness_range[EC_LED_COLOR_BLUE] = 1;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_BAT_LED_GREEN_L,
+			       !brightness[EC_LED_COLOR_GREEN]);
+		gpio_set_level(GPIO_BAT_LED_RED_L,
+			       !brightness[EC_LED_COLOR_RED]);
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		gpio_set_level(GPIO_PWR_LED_BLUE_L,
+			       !brightness[EC_LED_COLOR_BLUE]);
+		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/board/sasuke/usb_pd_policy.c b/board/sasuke/usb_pd_policy.c
new file mode 100644
index 0000000000..23166f7fca
--- /dev/null
+++ b/board/sasuke/usb_pd_policy.c
@@ -0,0 +1,61 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "driver/charger/isl923x_public.h"
+#include "driver/tcpm/tcpci.h"
+#include "usb_pd.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+int pd_check_vconn_swap(int port)
+{
+	/* Allow VCONN swaps if the AP is on. */
+	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
+}
+
+void pd_power_supply_reset(int port)
+{
+	/* Disable VBUS */
+	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	if (port >= board_get_usb_pd_port_count())
+		return EC_ERROR_INVAL;
+
+	/* Disable charging. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
+	if (rv)
+		return rv;
+
+	/* Our policy is not to source VBUS when the AP is off. */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	/* Provide Vbus. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
+	if (rv)
+		return rv;
+
+	rv = raa489000_enable_asgate(port, true);
+	if (rv)
+		return rv;
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
diff --git a/board/sasuke/vif_override.xml b/board/sasuke/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/sasuke/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/sasukette/battery.c b/board/sasukette/battery.c
new file mode 100644
index 0000000000..7a4670816e
--- /dev/null
+++ b/board/sasukette/battery.c
@@ -0,0 +1,177 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery.h"
+#include "battery_fuel_gauge.h"
+#include "battery_smart.h"
+#include "charge_state.h"
+#include "common.h"
+#include "util.h"
+
+#define CHARGING_VOLTAGE_MV_SAFE 8400
+#define CHARGING_CURRENT_MA_SAFE 1500
+
+/*
+ * Battery info for all sasukette battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	/* SDI Battery Information */
+	[BATTERY_SDI] = {
+		.fuel_gauge = {
+			.manuf_name = "SDI",
+			.device_name = "4402D51",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 0,
+				.reg_addr = 0x00,
+				.reg_mask = 0xc000,
+				.disconnect_val = 0x8000,
+				.cfet_mask = 0xc000,
+				.cfet_off_val = 0x2000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 8800,
+			.voltage_normal		= 7700, /* mV */
+			.voltage_min		= 6000, /* mV */
+			.precharge_current	= 200,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 45,
+			.charging_min_c		= 0,
+			.charging_max_c		= 50,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 70,
+		},
+	}
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SDI;
+
+int charger_profile_override(struct charge_state_data *curr)
+{
+	int current;
+	int voltage;
+	/* battery temp in 0.1 deg C */
+	int bat_temp_c;
+	const struct battery_info *batt_info;
+
+	/*
+	 * Keep track of battery temperature range:
+	 *
+	 *     ZONE_0  ZONE_1   ZONE_2  ZONE_3
+	 * ---+------+--------+--------+------+--- Temperature (C)
+	 *    0      5        12       45     50
+	 */
+	enum {
+		TEMP_ZONE_0, /* 0 <= bat_temp_c <= 5 */
+		TEMP_ZONE_1, /* 5 < bat_temp_c <= 12 */
+		TEMP_ZONE_2, /* 12 < bat_temp_c <= 45 */
+		TEMP_ZONE_3, /* 45 < bat_temp_c <= 50 */
+		TEMP_ZONE_COUNT,
+		TEMP_OUT_OF_RANGE = TEMP_ZONE_COUNT
+	} temp_zone;
+
+	/*
+	 * Precharge must be executed when communication is failed on
+	 * dead battery.
+	 */
+	if (!(curr->batt.flags & BATT_FLAG_RESPONSIVE))
+		return 0;
+
+	current = curr->requested_current;
+	voltage = curr->requested_voltage;
+	bat_temp_c = curr->batt.temperature - 2731;
+	batt_info = battery_get_info();
+
+	/*
+	 * If the temperature reading is bad, assume the temperature
+	 * is out of allowable range.
+	 */
+	if ((curr->batt.flags & BATT_FLAG_BAD_TEMPERATURE) ||
+	    (bat_temp_c < 0) || (bat_temp_c > 500))
+		temp_zone = TEMP_OUT_OF_RANGE;
+	else if (bat_temp_c <= 50)
+		temp_zone = TEMP_ZONE_0;
+	else if (bat_temp_c <= 120)
+		temp_zone = TEMP_ZONE_1;
+	else if (bat_temp_c <= 450)
+		temp_zone = TEMP_ZONE_2;
+	else
+		temp_zone = TEMP_ZONE_3;
+
+	switch (temp_zone) {
+	case TEMP_ZONE_0:
+		voltage = CHARGING_VOLTAGE_MV_SAFE;
+		current = CHARGING_CURRENT_MA_SAFE;
+		break;
+
+	case TEMP_ZONE_1:
+		voltage += 100;
+		current = CHARGING_CURRENT_MA_SAFE;
+		break;
+
+	case TEMP_ZONE_2:
+		voltage += 100;
+		break;
+
+	case TEMP_ZONE_3:
+		voltage = CHARGING_VOLTAGE_MV_SAFE;
+		break;
+
+	case TEMP_OUT_OF_RANGE:
+		/* Don't charge if outside of allowable temperature range */
+		current = 0;
+		voltage = 0;
+		curr->batt.flags &= ~BATT_FLAG_WANT_CHARGE;
+		if (curr->state != ST_DISCHARGE)
+			curr->state = ST_IDLE;
+		break;
+	}
+
+	if (voltage > batt_info->voltage_max)
+		voltage = batt_info->voltage_max;
+
+	curr->requested_voltage = voltage;
+	curr->requested_current = MIN(curr->requested_current, current);
+
+	return 0;
+}
+
+enum ec_status charger_profile_override_get_param(uint32_t param,
+						  uint32_t *value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+enum ec_status charger_profile_override_set_param(uint32_t param,
+						  uint32_t value)
+{
+	return EC_RES_INVALID_PARAM;
+}
diff --git a/board/sasukette/board.c b/board/sasukette/board.c
new file mode 100644
index 0000000000..7284d2d3c8
--- /dev/null
+++ b/board/sasukette/board.c
@@ -0,0 +1,350 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Sasukette configuration */
+
+#include "adc_chip.h"
+#include "button.h"
+#include "cbi_fw_config.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "cros_board_info.h"
+#include "driver/bc12/pi3usb9201.h"
+#include "driver/charger/isl923x.h"
+#include "driver/retimer/tusb544.h"
+#include "driver/tcpm/raa489000.h"
+#include "driver/temp_sensor/thermistor.h"
+#include "driver/usb_mux/it5205.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "intc.h"
+#include "keyboard_raw.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "math_util.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "switch.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "tcpm/tcpci.h"
+#include "temp_sensor.h"
+#include "uart.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+
+#define INT_RECHECK_US 5000
+
+/* C0 interrupt line shared by BC 1.2 and charger */
+static void check_c0_line(void);
+DECLARE_DEFERRED(check_c0_line);
+
+static void notify_c0_chips(void)
+{
+	schedule_deferred_pd_interrupt(0);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+
+static void check_c0_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		notify_c0_chips();
+		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+	}
+}
+
+static void usb_c0_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c0_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c0_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+}
+
+static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
+{
+	cprints(CC_USBPD, "C0: CC OVP, SBU OVP, or thermal event");
+	pd_handle_cc_overvoltage(0);
+}
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	[ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH0 },
+	[ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH2 },
+	[ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH3 },
+	[ADC_TEMP_SENSOR_3] = { .name = "TEMP_SENSOR3",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH15 },
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* BC 1.2 chips */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = { {
+	.i2c_port = I2C_PORT_USB_C0,
+	.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	.flags = PI3USB9201_ALWAYS_POWERED,
+} };
+
+int pd_snk_is_vbus_provided(int port)
+{
+	return pd_check_vbus_level(port, VBUS_PRESENT);
+}
+
+/* Charger chips */
+const struct charger_config_t chg_chips[] = { {
+	.i2c_port = I2C_PORT_USB_C0,
+	.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+	.drv = &isl923x_drv,
+} };
+
+/* TCPCs */
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0,
+			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
+		},
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+		.drv = &raa489000_tcpm_drv,
+	}
+};
+
+/* USB Muxes */
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = 0,
+			.i2c_port = I2C_PORT_USB_C0,
+			.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+			.driver = &it5205_usb_mux_driver,
+		},
+} };
+
+static uint32_t board_id;
+
+void board_init(void)
+{
+	int on;
+
+	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
+
+	/*
+	 * If interrupt lines are already low, schedule them to be processed
+	 * after inits are completed.
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL))
+		hook_call_deferred(&check_c0_line_data, 0);
+
+	gpio_enable_interrupt(GPIO_USB_C0_CCSBU_OVP_ODL);
+
+	/* Turn on 5V if the system is on, otherwise turn it off */
+	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
+			      CHIPSET_STATE_SOFT_OFF);
+	board_power_5v_enable(on);
+
+	/* modify AC DC prochot value */
+	isl923x_set_ac_prochot(CHARGER_SOLO, 4096);
+	isl923x_set_dc_prochot(CHARGER_SOLO, 6000);
+
+	cbi_get_board_version(&board_id);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+void board_hibernate(void)
+{
+	/*
+	 * Put all charger ICs present into low power mode before entering
+	 * z-state.
+	 *
+	 * b:186335659: In order to solve the power consumption problem of
+	 * hibernate，HW solution is adopted after board id 3 to solve the
+	 * problem that AC cannot wake up hibernate mode.
+	 */
+	if (board_id > 2)
+		raa489000_hibernate(0, true);
+	else
+		raa489000_hibernate(0, false);
+}
+
+__override void board_pulse_entering_rw(void)
+{
+	/*
+	 * On the ITE variants, the EC_ENTERING_RW signal was connected to a pin
+	 * which is active high by default.  This causes Cr50 to think that the
+	 * EC has jumped to its RW image even though this may not be the case.
+	 * The pin is changed to GPIO_EC_ENTERING_RW2.
+	 */
+	gpio_set_level(GPIO_EC_ENTERING_RW, 1);
+	gpio_set_level(GPIO_EC_ENTERING_RW2, 1);
+	usleep(MSEC);
+	gpio_set_level(GPIO_EC_ENTERING_RW, 0);
+	gpio_set_level(GPIO_EC_ENTERING_RW2, 0);
+}
+
+void board_reset_pd_mcu(void)
+{
+}
+
+__override void board_power_5v_enable(int enable)
+{
+	/*
+	 * Motherboard has a GPIO to turn on the 5V regulator, but the sub-board
+	 * sets it through the charger GPIO.
+	 */
+	gpio_set_level(GPIO_EN_PP5000, !!enable);
+	gpio_set_level(GPIO_EN_USB_A0_VBUS, !!enable);
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+	int regval;
+
+	/*
+	 * The interrupt line is shared between the TCPC and BC1.2 detector IC.
+	 * Therefore, go out and actually read the alert registers to report the
+	 * alert status.
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
+			if (regval)
+				status = PD_STATUS_TCPC_ALERT_0;
+		}
+	}
+
+	return status;
+}
+
+int board_is_sourcing_vbus(int port)
+{
+	int regval;
+
+	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
+	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count());
+	int i;
+	int old_port;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	old_port = charge_manager_get_active_charge_port();
+
+	CPRINTS("New chg p%d", port);
+
+	/* Disable all ports. */
+	if (port == CHARGE_PORT_NONE) {
+		for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+			tcpc_write(i, TCPC_REG_COMMAND,
+				   TCPC_REG_COMMAND_SNK_CTRL_LOW);
+			raa489000_enable_asgate(i, false);
+		}
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if port is sourcing VBUS. */
+	if (board_is_sourcing_vbus(port)) {
+		CPRINTS("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * Turn off the other ports sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+		if (i == port)
+			continue;
+
+		if (tcpc_write(i, TCPC_REG_COMMAND,
+			       TCPC_REG_COMMAND_SNK_CTRL_LOW))
+			CPRINTS("p%d: sink path disable failed.", i);
+		raa489000_enable_asgate(i, false);
+	}
+
+	/*
+	 * Stop the charger IC from switching while changing ports.  Otherwise,
+	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
+	 */
+	if (old_port != CHARGE_PORT_NONE)
+		charger_discharge_on_ac(1);
+
+	/* Enable requested charge port. */
+	if (raa489000_enable_asgate(port, true) ||
+	    tcpc_write(port, TCPC_REG_COMMAND,
+		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
+		CPRINTS("p%d: sink path enable failed.", port);
+		charger_discharge_on_ac(0);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	/* Allow the charger IC to begin/continue switching. */
+	charger_discharge_on_ac(0);
+
+	return EC_SUCCESS;
+}
+
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	if (port < 0 || port > board_get_usb_pd_port_count())
+		return;
+	raa489000_set_output_current(port, rp);
+}
+
+/* Thermistors */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "Cpu",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
diff --git a/board/sasukette/board.h b/board/sasukette/board.h
new file mode 100644
index 0000000000..848be6dffa
--- /dev/null
+++ b/board/sasukette/board.h
@@ -0,0 +1,102 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Sasukette board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* Select Baseboard features */
+#define VARIANT_DEDEDE_EC_IT8320
+#include "baseboard.h"
+#undef GPIO_VOLUME_UP_L
+#undef GPIO_VOLUME_DOWN_L
+#undef CONFIG_VOLUME_BUTTONS
+#undef CONFIG_I2C_DEBUG
+
+/* EC console commands */
+#define CONFIG_CMD_TCPC_DUMP
+#define CONFIG_CMD_CHARGER_DUMP
+
+/* Battery */
+#define CONFIG_BATTERY_FUEL_GAUGE
+#define CONFIG_BATTERY_CHECK_CHARGE_TEMP_LIMITS
+
+/* BC 1.2 */
+#define CONFIG_BC12_DETECT_PI3USB9201
+
+/* Charger */
+#define CONFIG_CHARGER_RAA489000
+#define PD_MAX_VOLTAGE_MV 20000
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SINGLE_CHIP
+#define CONFIG_CHARGER_PROFILE_OVERRIDE
+#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
+#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
+/*
+ * b/147463641: The charger IC seems to overdraw ~4%, therefore we
+ * reduce our target accordingly.
+ */
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 4
+
+/* LED */
+#define CONFIG_LED_COMMON
+#define CONFIG_LED_ONOFF_STATES
+#define GPIO_BAT_LED_RED_L GPIO_LED_R_ODL
+#define GPIO_BAT_LED_GREEN_L GPIO_LED_G_ODL
+#define GPIO_PWR_LED_BLUE_L GPIO_LED_B_ODL
+
+/* TCPC */
+#define CONFIG_USB_PD_PORT_MAX_COUNT 1
+#define CONFIG_USB_PD_TCPM_RAA489000
+
+/* USB defines specific to external TCPCs */
+#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+#define CONFIG_USB_PD_VBUS_DETECT_TCPC
+#define CONFIG_USB_PD_DISCHARGE_TCPC
+#define CONFIG_USB_PD_TCPC_LOW_POWER
+#define CONFIG_USB_PD_5V_EN_CUSTOM
+
+/* Thermistors */
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_THERMISTOR
+#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
+
+/* USB Mux and Retimer */
+#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+/* ADC channels */
+enum adc_channel {
+	ADC_VSNS_PP3300_A, /* ADC0 */
+	ADC_TEMP_SENSOR_1, /* ADC2 */
+	ADC_TEMP_SENSOR_2, /* ADC3 */
+	ADC_TEMP_SENSOR_3, /* ADC15*/
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1,
+	TEMP_SENSOR_2,
+	TEMP_SENSOR_3,
+	TEMP_SENSOR_COUNT
+};
+
+/* List of possible batteries */
+enum battery_type {
+	BATTERY_SDI,
+	BATTERY_TYPE_COUNT,
+};
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/sasukette/build.mk b/board/sasukette/build.mk
new file mode 100644
index 0000000000..01b890bf29
--- /dev/null
+++ b/board/sasukette/build.mk
@@ -0,0 +1,15 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=it83xx
+CHIP_FAMILY:=it8320
+CHIP_VARIANT:=it8320dx
+BASEBOARD:=dedede
+
+board-y=board.o cbi_ssfc.o led.o usb_pd_policy.o
+board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/sasukette/cbi_ssfc.c b/board/sasukette/cbi_ssfc.c
new file mode 100644
index 0000000000..81f3ee0dad
--- /dev/null
+++ b/board/sasukette/cbi_ssfc.c
@@ -0,0 +1,36 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi_ssfc.h"
+#include "common.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "hooks.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+/* Cache SSFC on init since we don't expect it to change in runtime */
+static union dedede_cbi_ssfc cached_ssfc;
+BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
+
+static void cbi_ssfc_init(void)
+{
+	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
+		/* Default to 0 when CBI isn't populated */
+		cached_ssfc.raw_value = 0;
+
+	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
+}
+DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
+
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
+{
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
+}
+
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
+{
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
+}
diff --git a/board/sasukette/cbi_ssfc.h b/board/sasukette/cbi_ssfc.h
new file mode 100644
index 0000000000..bf8853a43a
--- /dev/null
+++ b/board/sasukette/cbi_ssfc.h
@@ -0,0 +1,59 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _DEDEDE_CBI_SSFC__H_
+#define _DEDEDE_CBI_SSFC__H_
+
+#include "stdint.h"
+
+/****************************************************************************
+ * Dedede CBI Second Source Factory Cache
+ */
+
+/*
+ * Base Sensor (Bits 0-2)
+ */
+enum ec_ssfc_base_sensor {
+	SSFC_SENSOR_BASE_DEFAULT = 0,
+	SSFC_SENSOR_BMI160 = 1,
+	SSFC_SENSOR_ICM426XX = 2,
+	SSFC_SENSOR_LSM6DSM = 3,
+	SSFC_SENSOR_ICM42607 = 4
+};
+
+/*
+ * Lid Sensor (Bits 3-5)
+ */
+enum ec_ssfc_lid_sensor {
+	SSFC_SENSOR_LID_DEFAULT = 0,
+	SSFC_SENSOR_BMA255 = 1,
+	SSFC_SENSOR_KX022 = 2,
+	SSFC_SENSOR_LIS2DWL = 3
+};
+
+union dedede_cbi_ssfc {
+	struct {
+		uint32_t base_sensor : 3;
+		uint32_t lid_sensor : 3;
+		uint32_t reserved_2 : 26;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Get the Base sensor type from SSFC_CONFIG.
+ *
+ * @return the Base sensor board type.
+ */
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
+
+/**
+ * Get the Lid sensor type from SSFC_CONFIG.
+ *
+ * @return the Lid sensor board type.
+ */
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
+
+#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/sasukette/ec.tasklist b/board/sasukette/ec.tasklist
new file mode 100644
index 0000000000..d4a6c2cab3
--- /dev/null
+++ b/board/sasukette/ec.tasklist
@@ -0,0 +1,21 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, TRENTA_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, ULTRA_TASK_STACK_SIZE) \
+        TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE)
diff --git a/board/sasukette/gpio.inc b/board/sasukette/gpio.inc
new file mode 100644
index 0000000000..de63737e75
--- /dev/null
+++ b/board/sasukette/gpio.inc
@@ -0,0 +1,139 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+/* Power State interrupts */
+GPIO_INT(SLP_S4_L,		PIN(I, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,		PIN(H, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(SLP_S0_L,		PIN(E, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,		PIN(G, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID0,	PIN(D, 0), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(RSMRST_PWRGD_L,	PIN(E, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(CPU_C10_GATE_L,	PIN(G, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_DRAM_OD,		PIN(D, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(PG_PP1050_ST_OD,	PIN(L, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID1,	PIN(K, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_VCCIO_EXT_OD,	PIN(D, 7), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(ESPI_RESET_L, 	 	PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt)
+
+GPIO_INT(H1_EC_PWR_BTN_ODL,	PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
+#ifdef CONFIG_LOW_POWER_IDLE
+/* Used to wake up the EC from Deep Doze mode when writing to console */
+GPIO_INT(UART1_RX,	 	PIN(B, 0), GPIO_INT_BOTH, uart_deepsleep_interrupt)	/* UART_DBG_TX_EC_RX */
+#endif
+
+/* USB-C interrupts */
+GPIO_INT(USB_C0_INT_ODL,	PIN(K, 0), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt) /* BC12 and charger */
+GPIO_INT(USB_C0_CCSBU_OVP_ODL,	PIN(K, 6), GPIO_INT_FALLING | GPIO_PULL_UP, c0_ccsbu_ovp_interrupt) /* Fault protection */
+
+/* Other interrupts */
+GPIO_INT(LID_OPEN,		PIN(F, 3), GPIO_INT_BOTH, lid_interrupt)
+GPIO_INT(EC_WP_OD,		PIN(A, 6), GPIO_INT_BOTH, switch_interrupt)
+
+/* Power sequence GPIOs */
+GPIO(EC_AP_RTCRST,		PIN(K, 2), GPIO_OUT_LOW)
+GPIO(EC_AP_PWR_BTN_ODL,		PIN(B, 6), GPIO_ODR_HIGH)
+GPIO(EC_AP_DPWROK,		PIN(L, 7), GPIO_OUT_LOW)
+GPIO(EC_AP_RSMRST_L,		PIN(H, 0), GPIO_OUT_LOW)
+GPIO(EC_AP_WAKE_ODL,		PIN(D, 5), GPIO_ODR_HIGH)
+GPIO(SYS_RST_ODL,		PIN(D, 1), GPIO_ODR_HIGH)
+GPIO(EC_AP_SYS_PWROK,		PIN(F, 2), GPIO_OUT_LOW)
+GPIO(PG_PP5000_U_OD,		PIN(E, 3), GPIO_INPUT)
+GPIO(EN_PP3300_A,		PIN(C, 5), GPIO_OUT_LOW)
+GPIO(EC_AP_PCH_PWROK_OD,	PIN(D, 6), GPIO_ODR_LOW)
+GPIO(EN_PP5000_U,		PIN(K, 5), GPIO_OUT_LOW)
+/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
+GPIO(EN_VCCST,			PIN(D, 4), GPIO_INPUT)
+GPIO(EN_VCCIO_EXT,		PIN(B, 2), GPIO_OUT_LOW)
+GPIO(EC_PROCHOT_ODL,		PIN(I, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(EC_AP_VCCST_PWRGD_OD,	PIN(E, 5), GPIO_ODR_LOW)
+GPIO(ALL_SYS_PWRGD,		PIN(B, 7), GPIO_OUT_LOW)
+GPIO(EN_SLP_Z,			PIN(K, 3), GPIO_OUT_LOW)
+
+/* Required for icelake chipset code, but implemented through other means for dedede */
+UNIMPLEMENTED(AC_PRESENT)
+UNIMPLEMENTED(PG_EC_DSW_PWROK)
+UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
+
+/* I2C pins - Alternate function below configures I2C module on these pins */
+GPIO(EC_I2C_EEPROM_SCL,		PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SDA,		PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SCL,	PIN(C, 1), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SDA,	PIN(C, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SCL,		PIN(A, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SDA,		PIN(A, 5), GPIO_INPUT)
+GPIO(EC_AP_USB_C0_HPD,		PIN(L, 4), GPIO_OUT_LOW)
+GPIO(EC_AP_USB_C1_HDMI_HPD,	PIN(K, 7), GPIO_OUT_LOW)
+GPIO(EN_USB_A0_VBUS,		PIN(L, 6), GPIO_OUT_LOW) /* Board rev 1, NC board rev 0 */
+
+/* MKBP event synchronization */
+GPIO(EC_AP_MKBP_INT_L,		PIN(L, 5), GPIO_ODR_HIGH)
+
+
+/* Misc */
+GPIO(EN_BL_OD,			PIN(K, 4), GPIO_ODR_LOW)
+GPIO(EC_ENTERING_RW,		PIN(G, 0), GPIO_OUT_LOW)
+GPIO(EC_ENTERING_RW2,		PIN(C, 7), GPIO_OUT_LOW)
+GPIO(CCD_MODE_ODL,		PIN(H, 5), GPIO_ODR_HIGH)
+GPIO(EC_BATTERY_PRES_ODL,	PIN(I, 4), GPIO_INPUT)
+GPIO(ECH1_PACKET_MODE,		PIN(H, 1), GPIO_OUT_LOW)
+GPIO(LTE_EN, 			PIN(C, 3), GPIO_OUT_LOW)
+GPIO(WWAN_CONFIG, 		PIN(A, 0), GPIO_INPUT |GPIO_PULL_UP)
+
+/* LED */
+GPIO(LED_R_ODL,			PIN(A, 1), GPIO_ODR_HIGH)
+GPIO(LED_G_ODL,			PIN(A, 2), GPIO_ODR_HIGH)
+GPIO(LED_B_ODL,			PIN(A, 3), GPIO_ODR_HIGH)
+
+/* NC pins, enable internal pull-down to avoid floating state. */
+GPIO(GPIOB5_NC, PIN(B, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOC4_NC, PIN(C, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOC6_NC, PIN(C, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOE0_NC, PIN(E, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOE6_NC, PIN(E, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOE7_NC, PIN(E, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOF0_NC, PIN(F, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOF1_NC, PIN(F, 1), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOF4_NC, PIN(F, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOF5_NC, PIN(F, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOF6_NC, PIN(F, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOF7_NC, PIN(F, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG3_NC, PIN(G, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG4_NC, PIN(G, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG5_NC, PIN(G, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG6_NC, PIN(G, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG7_NC, PIN(G, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOH2_NC, PIN(H, 2), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOH4_NC, PIN(H, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOH6_NC, PIN(H, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOI6_NC, PIN(I, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOI7_NC, PIN(I, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ0_NC, PIN(J, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ1_NC, PIN(J, 1), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ3_NC, PIN(J, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ4_NC, PIN(J, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ5_NC, PIN(J, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ6_NC, PIN(J, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOL0_NC, PIN(L, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOL3_NC, PIN(L, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOM6_NC, PIN(M, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+
+/* Alternate functions GPIO definitions */
+/* UART */
+ALTERNATE(PIN_MASK(B, BIT(0) | BIT(1)), 0, MODULE_UART, 0)		/* UART for debug */
+
+/* I2C */
+ALTERNATE(PIN_MASK(B, BIT(3) | BIT(4)), 0, MODULE_I2C, 0)		/* I2C0 EEPROM */
+ALTERNATE(PIN_MASK(C, BIT(1) | BIT(2)), 0, MODULE_I2C, 0)		/* I2C1 BATTERY */
+ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), 0, MODULE_I2C, 0)		/* I2C5 USB_C0 */
+
+/* ADC */
+ALTERNATE(PIN_MASK(L, BIT(2)), 0, MODULE_ADC, 0)    /* ADC15:TEMP_SENSOR3 */
+ALTERNATE(PIN_MASK(I, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0)	/* ADC0: EC_VSNS_PP3300_A, ADC2: TEMP_SENSOR_1, ADC3: TEMP_SENSOR_2 */
diff --git a/board/sasukette/led.c b/board/sasukette/led.c
new file mode 100644
index 0000000000..af6d3635ac
--- /dev/null
+++ b/board/sasukette/led.c
@@ -0,0 +1,135 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power and battery LED control for Sasukette
+ *
+ */
+
+#include "chipset.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
+
+__override const int led_charge_lvl_1 = 1;
+
+__override const int led_charge_lvl_2 = 100;
+
+/* Sasukette : There are 3 leds for AC, Battery and Power */
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     1 * LED_ONE_SEC },
+					   { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED,
+					    0.5 * LED_ONE_SEC },
+					  { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					 { LED_OFF, 1 * LED_ONE_SEC } },
+	};
+
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_BLUE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_power(enum ec_led_colors color)
+{
+	/* Don't set led if led_auto_control is disabled. */
+	if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) ||
+	    !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
+		return;
+	}
+
+	if (color == EC_LED_COLOR_BLUE) {
+		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_ON_LVL);
+	} else {
+		/* LED_OFF and unsupported colors */
+		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_OFF_LVL);
+	}
+}
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	/* Don't set led if led_auto_control is disabled. */
+	if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) ||
+	    !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
+		return;
+	}
+
+	/* Battery leds must be turn off when blue led is on
+	 * because the led is 3-in-1 led.
+	 */
+	if (!gpio_get_level(GPIO_PWR_LED_BLUE_L)) {
+		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); /*red*/
+		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); /*green*/
+		return;
+	}
+
+	switch (color) {
+	case EC_LED_COLOR_GREEN:
+		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); /*red*/
+		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_ON_LVL); /*green*/
+		break;
+	case EC_LED_COLOR_RED:
+		gpio_set_level(GPIO_BAT_LED_RED_L, LED_ON_LVL); /*red*/
+		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); /*green*/
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); /*red*/
+		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); /*green*/
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_GREEN] = 1;
+		brightness_range[EC_LED_COLOR_RED] = 1;
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		brightness_range[EC_LED_COLOR_BLUE] = 1;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_BAT_LED_GREEN_L,
+			       !brightness[EC_LED_COLOR_GREEN]);
+		gpio_set_level(GPIO_BAT_LED_RED_L,
+			       !brightness[EC_LED_COLOR_RED]);
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		gpio_set_level(GPIO_PWR_LED_BLUE_L,
+			       !brightness[EC_LED_COLOR_BLUE]);
+		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/board/sasukette/usb_pd_policy.c b/board/sasukette/usb_pd_policy.c
new file mode 100644
index 0000000000..83c09bb99e
--- /dev/null
+++ b/board/sasukette/usb_pd_policy.c
@@ -0,0 +1,61 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "driver/charger/isl923x_public.h"
+#include "driver/tcpm/tcpci.h"
+#include "usb_pd.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+int pd_check_vconn_swap(int port)
+{
+	/* Allow VCONN swaps if the AP is on. */
+	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
+}
+
+void pd_power_supply_reset(int port)
+{
+	/* Disable VBUS */
+	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	if (port >= board_get_usb_pd_port_count())
+		return EC_ERROR_INVAL;
+
+	/* Disable charging. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
+	if (rv)
+		return rv;
+
+	/* Our policy is not to source VBUS when the AP is off. */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	/* Provide Vbus. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
+	if (rv)
+		return rv;
+
+	rv = raa489000_enable_asgate(port, true);
+	if (rv)
+		return rv;
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
diff --git a/board/sasukette/vif_override.xml b/board/sasukette/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/sasukette/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/scarlet/battery.c b/board/scarlet/battery.c
index 0be4cc93e2..f38e1f7896 100644
--- a/board/scarlet/battery.c
+++ b/board/scarlet/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -32,11 +32,7 @@
 static uint8_t batt_id = 0xff;
 
 /* Do not change the enum values. We directly use strap gpio level to index. */
-enum battery_type {
-	BATTERY_SIMPLO = 0,
-	BATTERY_AETECH,
-	BATTERY_COUNT
-};
+enum battery_type { BATTERY_SIMPLO = 0, BATTERY_AETECH, BATTERY_COUNT };
 
 static const struct battery_info info[] = {
 	[BATTERY_SIMPLO] = {
@@ -192,7 +188,7 @@ int charger_profile_override(struct charge_state_data *curr)
 	else {
 		for (temp_zone = 0; temp_zone < TEMP_ZONE_COUNT; temp_zone++) {
 			if (bat_temp_c <
-				temp_zones[batt_id][temp_zone].temp_max)
+			    temp_zones[batt_id][temp_zone].temp_max)
 				break;
 		}
 	}
@@ -233,9 +229,10 @@ int charger_profile_override(struct charge_state_data *curr)
 		curr->requested_voltage =
 			temp_zones[batt_id][temp_zone].desired_voltage;
 
-		curr->requested_current = (charge_phase) ?
-			CHARGE_PHASE_CHANGED_CURRENT_MA :
-			temp_zones[batt_id][temp_zone].desired_current;
+		curr->requested_current =
+			(charge_phase) ?
+				CHARGE_PHASE_CHANGED_CURRENT_MA :
+				temp_zones[batt_id][temp_zone].desired_current;
 		break;
 	case TEMP_OUT_OF_RANGE:
 		curr->requested_current = curr->requested_voltage = 0;
@@ -246,12 +243,12 @@ int charger_profile_override(struct charge_state_data *curr)
 
 	/*
 	 * When the charger says it's done charging, even if fuel gauge says
-	 * SOC < BATTERY_LEVEL_NEAR_FULL, we'll overwrite SOC with
-	 * BATTERY_LEVEL_NEAR_FULL. So we can ensure both Chrome OS UI
+	 * SOC < CONFIG_BATT_HOST_FULL_FACTOR, we'll overwrite SOC with
+	 * CONFIG_BATT_HOST_FULL_FACTOR. So we can ensure both Chrome OS UI
 	 * and battery LED indicate full charge.
 	 */
 	if (rt946x_is_charge_done()) {
-		curr->batt.state_of_charge = MAX(BATTERY_LEVEL_NEAR_FULL,
+		curr->batt.state_of_charge = MAX(CONFIG_BATT_HOST_FULL_FACTOR,
 						 curr->batt.state_of_charge);
 		/*
 		 * This is a workaround for b:78792296. When AP is off and
@@ -281,8 +278,7 @@ static void board_charge_termination(void)
 			te = 1;
 	}
 }
-DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE,
-	     board_charge_termination,
+DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, board_charge_termination,
 	     HOOK_PRIO_DEFAULT);
 
 /* Customs options controllable by host command. */
diff --git a/board/scarlet/board.c b/board/scarlet/board.c
index ef5dc6f6f1..daa247b385 100644
--- a/board/scarlet/board.c
+++ b/board/scarlet/board.c
@@ -1,30 +1,29 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "backlight.h"
 #include "button.h"
 #include "charge_manager.h"
 #include "charge_state.h"
-#include "charge_state_v2.h"
 #include "charger.h"
 #include "chipset.h"
 #include "common.h"
 #include "console.h"
-#include "ec_commands.h"
 #include "driver/accelgyro_bmi_common.h"
 #include "driver/charger/rt946x.h"
 #include "driver/sync.h"
 #include "driver/tcpm/fusb302.h"
 #include "driver/temp_sensor/tmp432.h"
+#include "ec_commands.h"
 #include "extpower.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "host_command.h"
 #include "i2c.h"
+#include "panic.h"
 #include "power.h"
 #include "power_button.h"
 #include "pwm.h"
@@ -34,18 +33,18 @@
 #include "switch.h"
 #include "system.h"
 #include "task.h"
-#include "tcpm.h"
+#include "tcpm/tcpm.h"
 #include "temp_sensor.h"
 #include "temp_sensor_chip.h"
-#include "timer.h"
 #include "thermal.h"
+#include "timer.h"
 #include "usb_charge.h"
 #include "usb_mux.h"
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
@@ -64,20 +63,29 @@ static void warm_reset_request_interrupt(enum gpio_signal signal)
 	chipset_reset(CHIPSET_RESET_AP_REQ);
 }
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /******************************************************************************/
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] = {"BOARD_ID", 3300, 4096, 0, STM32_AIN(10)},
+	[ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(10) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /******************************************************************************/
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{"charger", I2C_PORT_CHARGER,   400, GPIO_I2C0_SCL, GPIO_I2C0_SDA},
-	{"tcpc0",   I2C_PORT_TCPC0,     1000, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
+	{ .name = "charger",
+	  .port = I2C_PORT_CHARGER,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_SCL,
+	  .sda = GPIO_I2C0_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 1000,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -93,22 +101,22 @@ const struct charger_config_t chg_chips[] = {
 
 /* power signal list.  Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
-	{GPIO_PP1250_S3_PG,    POWER_SIGNAL_ACTIVE_HIGH, "PP1250_S3_PWR_GOOD"},
-	{GPIO_PP900_S0_PG,     POWER_SIGNAL_ACTIVE_HIGH, "PP900_S0_PWR_GOOD"},
-	{GPIO_AP_CORE_PG,      POWER_SIGNAL_ACTIVE_HIGH, "AP_PWR_GOOD"},
-	{GPIO_AP_EC_S3_S0_L,   POWER_SIGNAL_ACTIVE_LOW, "SUSPEND_DEASSERTED"},
+	{ GPIO_PP1250_S3_PG, POWER_SIGNAL_ACTIVE_HIGH, "PP1250_S3_PWR_GOOD" },
+	{ GPIO_PP900_S0_PG, POWER_SIGNAL_ACTIVE_HIGH, "PP900_S0_PWR_GOOD" },
+	{ GPIO_AP_CORE_PG, POWER_SIGNAL_ACTIVE_HIGH, "AP_PWR_GOOD" },
+	{ GPIO_AP_EC_S3_S0_L, POWER_SIGNAL_ACTIVE_LOW, "SUSPEND_DEASSERTED" },
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
 #ifdef CONFIG_TEMP_SENSOR_TMP432
 /* Temperature sensors data; must be in same order as enum temp_sensor_id. */
 const struct temp_sensor_t temp_sensors[] = {
-	{"TMP432_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-		TMP432_IDX_LOCAL, 4},
-	{"TMP432_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-		TMP432_IDX_REMOTE1, 4},
-	{"TMP432_Sensor_2", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-		TMP432_IDX_REMOTE2, 4},
+	{ "TMP432_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
+	  TMP432_IDX_LOCAL, 4 },
+	{ "TMP432_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
+	  TMP432_IDX_REMOTE1, 4 },
+	{ "TMP432_Sensor_2", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
+	  TMP432_IDX_REMOTE2, 4 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -117,9 +125,9 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
  * same order as enum temp_sensor_id. To always ignore any temp, use 0.
  */
 struct ec_thermal_config thermal_params[] = {
-	{{0, 0, 0}, 0, 0}, /* TMP432_Internal */
-	{{0, 0, 0}, 0, 0}, /* TMP432_Sensor_1 */
-	{{0, 0, 0}, 0, 0}, /* TMP432_Sensor_2 */
+	{ { 0, 0, 0 }, 0, 0 }, /* TMP432_Internal */
+	{ { 0, 0, 0 }, 0, 0 }, /* TMP432_Sensor_1 */
+	{ { 0, 0, 0 }, 0, 0 }, /* TMP432_Sensor_2 */
 };
 BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
 #endif
@@ -137,17 +145,20 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = I2C_PORT_TCPC0,
-			.addr_flags = FUSB302_I2C_SLAVE_ADDR_FLAGS,
+			.addr_flags = FUSB302_I2C_ADDR_FLAGS,
 		},
 		.drv = &fusb302_tcpm_drv,
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &virtual_usb_mux_driver,
+				.hpd_update = &virtual_hpd_update,
+			},
 	},
 };
 
@@ -155,11 +166,11 @@ void board_reset_pd_mcu(void)
 {
 }
 
-enum critical_shutdown board_critical_shutdown_check(
-		struct charge_state_data *curr)
+enum critical_shutdown
+board_critical_shutdown_check(struct charge_state_data *curr)
 {
 	if ((curr->batt.flags & BATT_FLAG_BAD_VOLTAGE) ||
-		(curr->batt.voltage <= BAT_LOW_VOLTAGE_THRESH))
+	    (curr->batt.voltage <= BAT_LOW_VOLTAGE_THRESH))
 		return CRITICAL_SHUTDOWN_CUTOFF;
 	else
 		return CRITICAL_SHUTDOWN_IGNORE;
@@ -201,13 +212,6 @@ int board_set_active_charge_port(int charge_port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_set_input_current_limit(MAX(charge_ma,
-			       CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
-
 int extpower_is_present(void)
 {
 	/*
@@ -230,7 +234,7 @@ int pd_snk_is_vbus_provided(int port)
 
 static void board_spi_enable(void)
 {
-	gpio_config_module(MODULE_SPI_MASTER, 1);
+	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
 
 	/* Enable clocks to SPI2 module */
 	STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
@@ -239,23 +243,21 @@ static void board_spi_enable(void)
 	STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2;
 	STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
 
-	spi_enable(CONFIG_SPI_ACCEL_PORT, 1);
+	spi_enable(&spi_devices[0], 1);
 }
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP,
-	     board_spi_enable,
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_spi_enable,
 	     MOTION_SENSE_HOOK_PRIO - 1);
 
 static void board_spi_disable(void)
 {
-	spi_enable(CONFIG_SPI_ACCEL_PORT, 0);
+	spi_enable(&spi_devices[0], 0);
 
 	/* Disable clocks to SPI2 module */
 	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
 
-	gpio_config_module(MODULE_SPI_MASTER, 0);
+	gpio_config_module(MODULE_SPI_CONTROLLER, 0);
 }
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN,
-	     board_spi_disable,
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_spi_disable,
 	     MOTION_SENSE_HOOK_PRIO + 1);
 
 static void board_init(void)
@@ -295,8 +297,8 @@ void board_config_pre_init(void)
 	 * Ch4: USART1_TX / Ch5: USART1_RX (1000)
 	 * Ch6: SPI2_RX / Ch7: SPI2_TX (0011)
 	 */
-	STM32_DMA_CSELR(STM32_DMAC_CH4) = (8 << 12) | (8 << 16) |
-					  (3 << 20) | (3 << 24);
+	STM32_DMA_CSELR(STM32_DMAC_CH4) = (8 << 12) | (8 << 16) | (3 << 20) |
+					  (3 << 24);
 }
 
 enum scarlet_board_version {
@@ -324,16 +326,16 @@ struct {
 	enum scarlet_board_version version;
 	int expect_mv;
 } const scarlet_boards[] = {
-	{ BOARD_VERSION_REV0, 109 },   /* 51.1K , 2.2K(gru 3.3K) ohm */
-	{ BOARD_VERSION_REV1, 211 },   /* 51.1k , 6.8K ohm */
-	{ BOARD_VERSION_REV2, 319 },   /* 51.1K , 11K ohm */
-	{ BOARD_VERSION_REV3, 427 },   /* 56K   , 17.4K ohm */
-	{ BOARD_VERSION_REV4, 542 },   /* 51.1K , 22K ohm */
-	{ BOARD_VERSION_REV5, 666 },   /* 51.1K , 30K ohm */
-	{ BOARD_VERSION_REV6, 781 },   /* 51.1K , 39.2K ohm */
-	{ BOARD_VERSION_REV7, 900 },   /* 56K   , 56K ohm */
-	{ BOARD_VERSION_REV8, 1023 },  /* 47K   , 61.9K ohm */
-	{ BOARD_VERSION_REV9, 1137 },  /* 47K   , 80.6K ohm */
+	{ BOARD_VERSION_REV0, 109 }, /* 51.1K , 2.2K(gru 3.3K) ohm */
+	{ BOARD_VERSION_REV1, 211 }, /* 51.1k , 6.8K ohm */
+	{ BOARD_VERSION_REV2, 319 }, /* 51.1K , 11K ohm */
+	{ BOARD_VERSION_REV3, 427 }, /* 56K   , 17.4K ohm */
+	{ BOARD_VERSION_REV4, 542 }, /* 51.1K , 22K ohm */
+	{ BOARD_VERSION_REV5, 666 }, /* 51.1K , 30K ohm */
+	{ BOARD_VERSION_REV6, 781 }, /* 51.1K , 39.2K ohm */
+	{ BOARD_VERSION_REV7, 900 }, /* 56K   , 56K ohm */
+	{ BOARD_VERSION_REV8, 1023 }, /* 47K   , 61.9K ohm */
+	{ BOARD_VERSION_REV9, 1137 }, /* 47K   , 80.6K ohm */
 	{ BOARD_VERSION_REV10, 1240 }, /* 56K   , 124K ohm */
 	{ BOARD_VERSION_REV11, 1343 }, /* 51.1K , 150K ohm */
 	{ BOARD_VERSION_REV12, 1457 }, /* 47K   , 200K ohm */
@@ -383,18 +385,15 @@ int board_get_version(void)
 }
 
 /* Motion sensors */
-#ifdef HAS_TASK_MOTIONSENSE
 /* Mutexes */
 static struct mutex g_base_mutex;
 
 static struct bmi_drv_data_t g_bmi160_data;
 
 /* Matrix to rotate accelerometer into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0,  0},
-	{ 0,  FLOAT_TO_FP(-1),  0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				       { 0, FLOAT_TO_FP(-1), 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	/*
@@ -412,7 +411,7 @@ struct motion_sensor_t motion_sensors[] = {
 	 .mutex = &g_base_mutex,
 	 .drv_data = &g_bmi160_data,
 	 .port = CONFIG_SPI_ACCEL_PORT,
-	 .i2c_spi_addr_flags = SLAVE_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
+	 .i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
 	 .rot_standard_ref = &base_standard_ref,
 	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
 	 .min_frequency = BMI_ACCEL_MIN_FREQ,
@@ -435,7 +434,7 @@ struct motion_sensor_t motion_sensors[] = {
 	 .mutex = &g_base_mutex,
 	 .drv_data = &g_bmi160_data,
 	 .port = CONFIG_SPI_ACCEL_PORT,
-	 .i2c_spi_addr_flags = SLAVE_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
+	 .i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
 	 .default_range = 1000, /* dps */
 	 .rot_standard_ref = &base_standard_ref,
 	 .min_frequency = BMI_GYRO_MIN_FREQ,
@@ -454,9 +453,8 @@ struct motion_sensor_t motion_sensors[] = {
 	},
 };
 const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-#endif /* defined(HAS_TASK_MOTIONSENSE) */
 
-int board_allow_i2c_passthru(int port)
+int board_allow_i2c_passthru(const struct i2c_cmd_desc_t *cmd_desc)
 {
-	return (port == I2C_PORT_VIRTUAL_BATTERY);
+	return (cmd_desc->port == I2C_PORT_VIRTUAL_BATTERY);
 }
diff --git a/board/scarlet/board.h b/board/scarlet/board.h
index 7e48ffde52..0bd4473389 100644
--- a/board/scarlet/board.h
+++ b/board/scarlet/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,17 +8,22 @@
 #ifndef __CROS_EC_BOARD_H
 #define __CROS_EC_BOARD_H
 
+/* Free up flash space */
+#define CONFIG_DEBUG_ASSERT_BRIEF
+#define CONFIG_LTO
+#define CONFIG_USB_PD_DEBUG_LEVEL 0
+
 /* Optional modules */
 #define CONFIG_ADC
-#undef  CONFIG_ADC_WATCHDOG
+#undef CONFIG_ADC_WATCHDOG
 #define CONFIG_CHIPSET_RK3399
 #define CONFIG_CMD_ACCELS
 #define CONFIG_CMD_RTC
 #define CONFIG_EMULATED_SYSRQ
-#undef  CONFIG_HIBERNATE
+#undef CONFIG_HIBERNATE
 #define CONFIG_HOSTCMD_RTC
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_CONTROLLER
 #define CONFIG_I2C_VIRTUAL_BATTERY
 #define CONFIG_I2C_PASSTHRU_RESTRICTED
 #define CONFIG_LED_COMMON
@@ -26,8 +31,7 @@
 #define CONFIG_LOW_POWER_IDLE_LIMITED
 #define CONFIG_POWER_COMMON
 #define CONFIG_SPI
-#define CONFIG_SPI_MASTER
-#define CONFIG_STM_HWTIMER32
+#define CONFIG_SPI_CONTROLLER
 /* Source RTCCLK from external 32.768kHz source on PC15/OSC32_IN. */
 #define CONFIG_STM32_CLOCK_LSE
 #define CONFIG_SWITCH
@@ -35,7 +39,7 @@
 
 #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands for testing */
 
-#undef  CONFIG_UART_CONSOLE
+#undef CONFIG_UART_CONSOLE
 #define CONFIG_UART_CONSOLE 1
 #define CONFIG_UART_RX_DMA
 
@@ -45,7 +49,6 @@
 
 /* Optional features */
 #define CONFIG_BOARD_PRE_INIT
-#define CONFIG_BOARD_VERSION_CUSTOM
 #define CONFIG_BUTTON_TRIGGERED_RECOVERY
 #define CONFIG_CHARGER_ILIM_PIN_DISABLED
 #define CONFIG_FORCE_CONSOLE_RESUME
@@ -58,18 +61,16 @@
 #undef CONFIG_HOSTCMD_DEBUG_MODE
 #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
 #undef CONFIG_LID_SWITCH
-#undef CONFIG_LTO
 #define CONFIG_POWER_BUTTON
 #define CONFIG_POWER_BUTTON_IGNORE_LID
 #define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-#define CONFIG_SOFTWARE_PANIC
 #define CONFIG_VBOOT_HASH
 #define CONFIG_VOLUME_BUTTONS
 
 #define CONFIG_CHARGER
 #define CONFIG_CHARGER_RT9467
-#define CONFIG_CHARGER_INPUT_CURRENT 512
-#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 2
+#define CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT 512
+#define CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT 512
 #define CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT 2
 #define CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW 15000
 #define CONFIG_CHARGER_PROFILE_OVERRIDE
@@ -84,15 +85,13 @@
 
 /* Motion Sensors */
 #define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCEL_INTERRUPTS
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
 
 /* Camera VSYNC */
 #define CONFIG_SYNC
 #define CONFIG_SYNC_COMMAND
-#define CONFIG_SYNC_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
+#define CONFIG_SYNC_INT_EVENT TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
 
 /* To be able to indicate the device is in tablet mode. */
 #define CONFIG_TABLET_MODE
@@ -130,35 +129,36 @@
 #define CONFIG_BATTERY_REVIVE_DISCONNECT
 #define CONFIG_BATTERY_MAX17055
 
+/* Disable verbose output in EC pd */
+#ifdef SECTION_IS_RO
+#define CONFIG_CMD_PD_SRCCAPS_REDUCED_SIZE
+#endif
+
 /* Battery parameters for max17055 ModelGauge m5 algorithm. */
-#define BATTERY_MAX17055_RSENSE             5     /* m-ohm */
-#define BATTERY_DESIRED_CHARGING_CURRENT    4000  /* mA */
+#define BATTERY_MAX17055_RSENSE 5 /* m-ohm */
+#define BATTERY_DESIRED_CHARGING_CURRENT 4000 /* mA */
 
 #define CONFIG_THROTTLE_AP_ON_BAT_DISCHG_CURRENT
-#define BAT_MAX_DISCHG_CURRENT	5000 /* mA */
-
 #define CONFIG_THROTTLE_AP_ON_BAT_VOLTAGE
-#define BAT_LOW_VOLTAGE_THRESH 3200 /* mV */
 
 #define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_VOLTAGE_MV     12850
+#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 12850
 
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY 50000  /* us */
-#define PD_VCONN_SWAP_DELAY 5000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 50000 /* us */
 
 /* Timer selection */
-#define TIM_CLOCK32  2
+#define TIM_CLOCK32 2
 #define TIM_WATCHDOG 7
 
 /* 48 MHz SYSCLK clock frequency */
 #define CPU_CLOCK 48000000
 
 /* Optional for testing */
-#undef  CONFIG_PECI
-#undef  CONFIG_PSTORE
+#undef CONFIG_PECI
+#undef CONFIG_PSTORE
 
 /* Modules we want to exclude */
 #undef CONFIG_CMD_BATTFAKE
@@ -171,24 +171,24 @@
 
 #define CONFIG_TASK_PROFILING
 
-#define I2C_PORT_CHARGER  0
-#define I2C_PORT_BATTERY  0
+#define I2C_PORT_CHARGER 0
+#define I2C_PORT_BATTERY 0
 #define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
-#define I2C_PORT_TCPC0    1
+#define I2C_PORT_TCPC0 1
 
 /* Route sbs host requests to virtual battery driver */
 #define VIRTUAL_BATTERY_ADDR_FLAGS 0x0B
 
 /* Enable Accel over SPI */
-#define CONFIG_SPI_ACCEL_PORT    0  /* The first SPI master port (SPI2) */
+#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */
 
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
+#define CONFIG_MKBP_INPUT_DEVICES
 #define CONFIG_MKBP_EVENT
 #define CONFIG_MKBP_USE_GPIO
 /* Define the host events which are allowed to wakeup AP in S3. */
-#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \
-		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC))
+#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK                \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC))
 
 #ifndef __ASSEMBLER__
 
diff --git a/board/scarlet/build.mk b/board/scarlet/build.mk
index f2966fea6a..adecf6b4ea 100644
--- a/board/scarlet/build.mk
+++ b/board/scarlet/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/scarlet/ec.tasklist b/board/scarlet/ec.tasklist
index 1548272184..08baec1e86 100644
--- a/board/scarlet/ec.tasklist
+++ b/board/scarlet/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/scarlet/gpio.inc b/board/scarlet/gpio.inc
index bfede671a8..15ce1cb681 100644
--- a/board/scarlet/gpio.inc
+++ b/board/scarlet/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -99,4 +99,4 @@ ALTERNATE(PIN_MASK(B, 0x0038), 0, MODULE_SPI,        0)
 /* SPI SLAVE CS: PA15 */
 ALTERNATE(PIN_MASK(A, 0x8000), 0, MODULE_SPI,        0)
 /* SPI MASTER: PD1/3/4 */
-ALTERNATE(PIN_MASK(D, 0x001a), 1, MODULE_SPI_MASTER, 0)
+ALTERNATE(PIN_MASK(D, 0x001a), 1, MODULE_SPI_CONTROLLER, 0)
diff --git a/board/scarlet/led.c b/board/scarlet/led.c
index d4c758cdcc..cccec4af73 100644
--- a/board/scarlet/led.c
+++ b/board/scarlet/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,6 +8,7 @@
 #include "battery.h"
 #include "charge_state.h"
 #include "chipset.h"
+#include "gpio.h"
 #include "hooks.h"
 #include "led_common.h"
 #include "lid_switch.h"
@@ -27,7 +28,7 @@ enum led_color {
 	LED_RED,
 	LED_AMBER,
 	LED_GREEN,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static int bat_led_set_color(enum led_color color)
@@ -62,35 +63,35 @@ static void scarlet_led_set_battery(void)
 
 	battery_second++;
 
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
 		bat_led_set_color(LED_AMBER);
 		break;
-	case PWR_STATE_DISCHARGE:
+	case LED_PWRS_DISCHARGE:
 		if (charge_get_percent() < 3)
-			bat_led_set_color((battery_second & 1)
-					? LED_OFF : LED_AMBER);
+			bat_led_set_color((battery_second & 1) ? LED_OFF :
+								 LED_AMBER);
 		else if (charge_get_percent() < 10)
-			bat_led_set_color((battery_second & 3)
-					? LED_OFF : LED_AMBER);
-		else if (charge_get_percent() >= BATTERY_LEVEL_NEAR_FULL &&
-		    (chflags & CHARGE_FLAG_EXTERNAL_POWER))
+			bat_led_set_color((battery_second & 3) ? LED_OFF :
+								 LED_AMBER);
+		else if (charge_get_percent() >= CONFIG_BATT_HOST_FULL_FACTOR &&
+			 (chflags & CHARGE_FLAG_EXTERNAL_POWER))
 			bat_led_set_color(LED_GREEN);
 		else
 			bat_led_set_color(LED_OFF);
 		break;
-	case PWR_STATE_ERROR:
+	case LED_PWRS_ERROR:
 		bat_led_set_color(LED_RED);
 		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
+	case LED_PWRS_CHARGE_NEAR_FULL:
 		bat_led_set_color(LED_GREEN);
 		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE. */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			bat_led_set_color(
-				(battery_second & 0x2) ? LED_GREEN : LED_AMBER);
-		else
-			bat_led_set_color(LED_GREEN);
+	case LED_PWRS_IDLE: /* External power connected in IDLE. */
+		bat_led_set_color(LED_GREEN);
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		bat_led_set_color((battery_second & 0x2) ? LED_GREEN :
+							   LED_AMBER);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
@@ -111,10 +112,12 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 	if (led_id == EC_LED_ID_BATTERY_LED) {
 		gpio_set_level(GPIO_BAT_LED_RED,
 			       (brightness[EC_LED_COLOR_RED] != 0) ?
-				BAT_LED_ON : BAT_LED_OFF);
+				       BAT_LED_ON :
+				       BAT_LED_OFF);
 		gpio_set_level(GPIO_BAT_LED_GREEN,
 			       (brightness[EC_LED_COLOR_GREEN] != 0) ?
-				BAT_LED_ON : BAT_LED_OFF);
+				       BAT_LED_ON :
+				       BAT_LED_OFF);
 		return EC_SUCCESS;
 	}
 	return EC_ERROR_UNKNOWN;
diff --git a/board/scarlet/usb_pd_policy.c b/board/scarlet/usb_pd_policy.c
index cba4540ecd..90c7dfb157 100644
--- a/board/scarlet/usb_pd_policy.c
+++ b/board/scarlet/usb_pd_policy.c
@@ -1,11 +1,11 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "atomic.h"
-#include "charger.h"
 #include "charge_manager.h"
+#include "charger.h"
 #include "common.h"
 #include "console.h"
 #include "driver/charger/rt946x.h"
@@ -16,13 +16,13 @@
 #include "system.h"
 #include "task.h"
 #include "timer.h"
-#include "util.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
+#include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 static uint8_t vbus_en;
 
@@ -33,7 +33,6 @@ int board_vbus_source_enabled(int port)
 
 int pd_set_power_supply_ready(int port)
 {
-
 	pd_set_vbus_discharge(port, 0);
 	/* Provide VBUS */
 	vbus_en = 1;
diff --git a/board/scarlet/vif_override.xml b/board/scarlet/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/scarlet/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/scout/board.c b/board/scout/board.c
new file mode 100644
index 0000000000..3d5306fdf0
--- /dev/null
+++ b/board/scout/board.c
@@ -0,0 +1,767 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Puff board-specific configuration */
+
+#include "adc.h"
+#include "button.h"
+#include "chipset.h"
+#include "common.h"
+#include "core/cortex-m/cpu.h"
+#include "cros_board_info.h"
+#include "driver/als_tcs3400.h"
+#include "driver/ina3221.h"
+#include "ec_commands.h"
+#include "extpower.h"
+#include "fan.h"
+#include "fan_chip.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power/cometlake-discrete.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "spi.h"
+#include "switch.h"
+#include "system.h"
+#include "task.h"
+#include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
+#include "thermal.h"
+#include "uart.h"
+#include "usb_common.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+
+/* Sensors */
+
+/* TCS3400 private data */
+static struct als_drv_data_t g_tcs3400_data = {
+	.als_cal.scale = 1,
+	.als_cal.uscale = 0,
+	.als_cal.offset = 0,
+	.als_cal.channel_scale = {
+		.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kc */
+		.cover_scale = ALS_CHANNEL_SCALE(1.0),     /* CT */
+	},
+};
+
+static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
+	/*
+	 * b/202465034: calculate the actual coefficients and scaling factors
+	 */
+	.calibration.rgb_cal[X] = {
+		.offset = 0,
+		.scale = {
+			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kr */
+			.cover_scale = ALS_CHANNEL_SCALE(1.0)
+		},
+		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
+		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
+		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
+		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
+	},
+	.calibration.rgb_cal[Y] = {
+		.offset = 0,
+		.scale = {
+			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kg */
+			.cover_scale = ALS_CHANNEL_SCALE(1.0)
+		},
+		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
+		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
+		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
+		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0.1),
+	},
+	.calibration.rgb_cal[Z] = {
+		.offset = 0,
+		.scale = {
+			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kb */
+			.cover_scale = ALS_CHANNEL_SCALE(1.0)
+		},
+		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
+		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
+		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
+		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
+	},
+	.calibration.irt = INT_TO_FP(1),
+	.saturation.again = TCS_DEFAULT_AGAIN,
+	.saturation.atime = TCS_DEFAULT_ATIME,
+};
+
+struct motion_sensor_t motion_sensors[] = {
+	[CLEAR_ALS] = {
+		.name = "Clear Light",
+		.active_mask = SENSOR_ACTIVE_S0,
+		.chip = MOTIONSENSE_CHIP_TCS3400,
+		.type = MOTIONSENSE_TYPE_LIGHT,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &tcs3400_drv,
+		.drv_data = &g_tcs3400_data,
+		.port = I2C_PORT_SENSORS,
+		.i2c_spi_addr_flags = TCS3400_I2C_ADDR_FLAGS,
+		.rot_standard_ref = NULL,
+		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
+		.min_frequency = TCS3400_LIGHT_MIN_FREQ,
+		.max_frequency = TCS3400_LIGHT_MAX_FREQ,
+		.config = {
+			/* Run ALS sensor in S0 */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 1000,
+			},
+		},
+	},
+	[RGB_ALS] = {
+		.name = "RGB Light",
+		.active_mask = SENSOR_ACTIVE_S0,
+		.chip = MOTIONSENSE_CHIP_TCS3400,
+		.type = MOTIONSENSE_TYPE_LIGHT_RGB,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &tcs3400_rgb_drv,
+		.drv_data = &g_tcs3400_rgb_data,
+		.rot_standard_ref = NULL,
+		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
+	},
+};
+const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+/* ALS instances when LPC mapping is needed. Each entry directs to a sensor. */
+const struct motion_sensor_t *motion_als_sensors[] = {
+	&motion_sensors[CLEAR_ALS],
+};
+BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
+
+static void power_monitor(void);
+DECLARE_DEFERRED(power_monitor);
+
+static uint8_t usbc_overcurrent;
+static int32_t base_5v_power;
+
+/*
+ * Power usage for each port as measured or estimated.
+ * Units are milliwatts (5v x ma current)
+ */
+#define PWR_BASE_LOAD (5 * 1335)
+#define PWR_FRONT_HIGH (5 * 1603)
+#define PWR_FRONT_LOW (5 * 963)
+#define PWR_REAR (5 * 1075)
+#define PWR_HDMI (5 * 562)
+#define PWR_C_HIGH (5 * 3740)
+#define PWR_C_LOW (5 * 2090)
+#define PWR_MAX (5 * 10000)
+
+/*
+ * Update the 5V power usage, assuming no throttling,
+ * and invoke the power monitoring.
+ */
+static void update_5v_usage(void)
+{
+	int front_ports = 0;
+	/*
+	 * Recalculate the 5V load, assuming no throttling.
+	 */
+	base_5v_power = PWR_BASE_LOAD;
+	if (!gpio_get_level(GPIO_USB_A0_OC_ODL)) {
+		front_ports++;
+		base_5v_power += PWR_FRONT_LOW;
+	}
+	if (!gpio_get_level(GPIO_USB_A1_OC_ODL)) {
+		front_ports++;
+		base_5v_power += PWR_FRONT_LOW;
+	}
+	/*
+	 * Only 1 front port can run higher power at a time.
+	 */
+	if (front_ports > 0)
+		base_5v_power += PWR_FRONT_HIGH - PWR_FRONT_LOW;
+	if (!gpio_get_level(GPIO_USB_A2_OC_ODL))
+		base_5v_power += PWR_REAR;
+	if (!gpio_get_level(GPIO_USB_A3_OC_ODL))
+		base_5v_power += PWR_REAR;
+	if (!gpio_get_level(GPIO_HDMI_CONN0_OC_ODL))
+		base_5v_power += PWR_HDMI;
+	if (!gpio_get_level(GPIO_HDMI_CONN1_OC_ODL))
+		base_5v_power += PWR_HDMI;
+	if (usbc_overcurrent)
+		base_5v_power += PWR_C_HIGH;
+	/*
+	 * Invoke the power handler immediately.
+	 */
+	hook_call_deferred(&power_monitor_data, 0);
+}
+DECLARE_DEFERRED(update_5v_usage);
+/*
+ * Start power monitoring after ADCs have been initialised.
+ */
+DECLARE_HOOK(HOOK_INIT, update_5v_usage, HOOK_PRIO_INIT_ADC + 1);
+
+static void port_ocp_interrupt(enum gpio_signal signal)
+{
+	hook_call_deferred(&update_5v_usage_data, 0);
+}
+
+/******************************************************************************/
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/******************************************************************************/
+/* SPI devices */
+const struct spi_device_t spi_devices[] = {};
+const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
+
+/******************************************************************************/
+/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
+	[PWM_CH_LED_RED] = { .channel = 0,
+			     .flags = PWM_CONFIG_DSLEEP,
+			     .freq = 2000 },
+	[PWM_CH_LED_WHITE] = { .channel = 2,
+			       .flags = PWM_CONFIG_DSLEEP,
+			       .freq = 2000 },
+};
+
+/******************************************************************************/
+/* I2C port map configuration */
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "ina",
+	  .port = I2C_PORT_INA,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_SCL,
+	  .sda = GPIO_I2C0_SDA },
+	{ .name = "ppc0",
+	  .port = I2C_PORT_PPC0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "scaler",
+	  .port = I2C_PORT_SCALER,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 400,
+	  .scl = GPIO_I2C5_SCL,
+	  .sda = GPIO_I2C5_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_I2C7_SCL,
+	  .sda = GPIO_I2C7_SDA },
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+const struct adc_t adc_channels[] = {
+	[ADC_SNS_PP3300] = {
+		/*
+		 * 4700/5631 voltage divider: can take the value out of range
+		 * for 32-bit signed integers, so truncate to 470/563 yielding
+		 * <0.1% error and a maximum intermediate value of 1623457792,
+		 * which comfortably fits in int32.
+		 */
+		.name = "SNS_PP3300",
+		.input_ch = NPCX_ADC_CH2,
+		.factor_mul = ADC_MAX_VOLT * 563,
+		.factor_div = (ADC_READ_MAX + 1) * 470,
+	},
+	[ADC_SNS_PP1050] = {
+		.name = "SNS_PP1050",
+		.input_ch = NPCX_ADC_CH7,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+	},
+	[ADC_VBUS] = {  /* 5/39 voltage divider */
+		.name = "VBUS",
+		.input_ch = NPCX_ADC_CH4,
+		.factor_mul = ADC_MAX_VOLT * 39,
+		.factor_div = (ADC_READ_MAX + 1) * 5,
+	},
+	[ADC_PPVAR_IMON] = {  /* 500 mV/A */
+		.name = "PPVAR_IMON",
+		.input_ch = NPCX_ADC_CH9,
+		.factor_mul = ADC_MAX_VOLT * 2, /* Milliamps */
+		.factor_div = ADC_READ_MAX + 1,
+	},
+	[ADC_TEMP_SENSOR_1] = {
+		.name = "TEMP_SENSOR_1",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+	},
+	[ADC_TEMP_SENSOR_2] = {
+		.name = "TEMP_SENSOR_2",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_CORE] = {
+		.name = "Core",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_1,
+	},
+	[TEMP_SENSOR_WIFI] = {
+		.name = "Wifi",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_2,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/******************************************************************************/
+/* Wake up pins */
+const enum gpio_signal hibernate_wake_pins[] = {};
+const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
+
+/******************************************************************************/
+/* Physical fans. These are logically separate from pwm_channels. */
+const struct fan_conf fan_conf_0 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
+	.pgood_gpio = -1,
+	.enable_gpio = -1,
+};
+
+const struct fan_rpm fan_rpm_0 = {
+	.rpm_min = 2400,
+	.rpm_start = 2400,
+	.rpm_max = 5300,
+};
+
+const struct fan_t fans[] = {
+	[FAN_CH_0] = { .conf = &fan_conf_0, .rpm = &fan_rpm_0, },
+};
+BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
+
+/******************************************************************************/
+/* MFT channels. These are logically separate from pwm_channels. */
+const struct mft_t mft_channels[] = {
+	[MFT_CH_0] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN },
+};
+BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
+
+/******************************************************************************/
+/* Thermal control; drive fan based on temperature sensors. */
+static const int temp_fan_off = C_TO_K(35);
+static const int temp_fan_max = C_TO_K(55);
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_A                \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(85), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(90), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(78), \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+		.temp_fan_off = temp_fan_off, \
+		.temp_fan_max = temp_fan_max, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A;
+
+static const struct ec_thermal_config thermal_b = {
+		.temp_host = {
+			[EC_TEMP_THRESH_WARN] = 0,
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(78),
+			[EC_TEMP_THRESH_HALT] = C_TO_K(85),
+		},
+		.temp_host_release = {
+			[EC_TEMP_THRESH_WARN] = 0,
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
+			[EC_TEMP_THRESH_HALT] = 0,
+		},
+	};
+
+struct ec_thermal_config thermal_params[] = {
+	[TEMP_SENSOR_CORE] = THERMAL_A,
+	[TEMP_SENSOR_WIFI] = THERMAL_A,
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
+
+static const struct fan_step_1_1 fan_table0[] = {
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(35),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(41),
+	  .rpm = 2400 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(40),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(44),
+	  .rpm = 2900 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(42),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(46),
+	  .rpm = 3400 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(44),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(48),
+	  .rpm = 3900 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(46),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(50),
+	  .rpm = 4400 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(48),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(52),
+	  .rpm = 4900 },
+	{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(50),
+	  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(55),
+	  .rpm = 5300 },
+};
+#define NUM_FAN_LEVELS ARRAY_SIZE(fan_table0)
+
+static const struct fan_step_1_1 *fan_table = fan_table0;
+
+int fan_percent_to_rpm(int fan, int temp_ratio)
+{
+	return temp_ratio_to_rpm_hysteresis(fan_table, NUM_FAN_LEVELS, fan,
+					    temp_ratio, NULL);
+}
+
+/* Power sensors */
+const struct ina3221_t ina3221[] = {
+	{ I2C_PORT_INA, 0x40, { "PP3300_G", "PP5000_A", "PP3300_WLAN" } },
+	{ I2C_PORT_INA, 0x42, { "PP3300_A", "PP3300_SSD", "PP3300_LAN" } },
+	{ I2C_PORT_INA, 0x43, { NULL, "PP1200_U", "PP2500_DRAM" } }
+};
+const unsigned int ina3221_count = ARRAY_SIZE(ina3221);
+
+static uint16_t board_version;
+static uint32_t sku_id;
+static uint32_t fw_config;
+
+static void cbi_init(void)
+{
+	/*
+	 * Load board info from CBI to control per-device configuration.
+	 *
+	 * If unset it's safe to treat the board as a proto, just C10 gating
+	 * won't be enabled.
+	 */
+	uint32_t val;
+
+	if (cbi_get_board_version(&val) == EC_SUCCESS && val <= UINT16_MAX)
+		board_version = val;
+	if (cbi_get_sku_id(&val) == EC_SUCCESS)
+		sku_id = val;
+	if (cbi_get_fw_config(&val) == EC_SUCCESS)
+		fw_config = val;
+	CPRINTS("Board Version: %d, SKU ID: 0x%08x, F/W config: 0x%08x",
+		board_version, sku_id, fw_config);
+}
+DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1);
+
+static void board_sensors_init(void)
+{
+	/* Enable interrupt for the TCS3400 color light sensor */
+	switch (board_version) {
+	case BOARD_VERSION_PROTO:
+	case BOARD_VERSION_PRE_EVT:
+	case BOARD_VERSION_EVT:
+		/*
+		 * b/203224828: These versions incorrectly use a 1.8V interrupt
+		 * line, which sends a constant interrupt signal and eventually
+		 * triggers a watchdog reset, so we keep it disabled.
+		 */
+		gpio_disable_interrupt(GPIO_EC_RGB_INT_L);
+		CPRINTS("ALS interrupt disabled (detected known-bad hardware)");
+		break;
+
+	case BOARD_VERSION_DVT:
+	case BOARD_VERSION_PVT:
+	default:
+		gpio_enable_interrupt(GPIO_EC_RGB_INT_L);
+		CPRINTS("ALS interrupt enabled");
+		break;
+	}
+}
+/* Ensure board_sensors_init runs after cbi_init. */
+DECLARE_HOOK(HOOK_INIT, board_sensors_init, HOOK_PRIO_INIT_I2C + 2);
+
+static void board_init(void)
+{
+	uint8_t *memmap_batt_flags;
+
+	/* Override some GPIO interrupt priorities.
+	 *
+	 * These interrupts are timing-critical for AP power sequencing, so we
+	 * increase their NVIC priority from the default of 3. This affects
+	 * whole MIWU groups of 8 GPIOs since they share an IRQ.
+	 *
+	 * Latency at the default priority level can be hundreds of
+	 * microseconds while other equal-priority IRQs are serviced, so GPIOs
+	 * requiring faster response must be higher priority.
+	 */
+	/* CPU_C10_GATE_L on GPIO6.7: must be ~instant for ~60us response. */
+	cpu_set_interrupt_priority(NPCX_IRQ_WKINTH_1, 1);
+	/*
+	 * slp_s3_interrupt (GPIOA.5 on WKINTC_0) must respond within 200us
+	 * (tPLT18); less critical than the C10 gate.
+	 */
+	cpu_set_interrupt_priority(NPCX_IRQ_WKINTC_0, 2);
+
+	/* Always claim AC is online, because we don't have a battery. */
+	memmap_batt_flags = host_get_memmap(EC_MEMMAP_BATT_FLAG);
+	*memmap_batt_flags |= EC_BATT_FLAG_AC_PRESENT;
+	/*
+	 * For board version < 2, the directly connected recovery
+	 * button is not available.
+	 */
+	if (board_version < 2)
+		button_disable_gpio(BUTTON_RECOVERY);
+
+	/*
+	 * Early Scout devices does not setup EC_MIC_OE in RO, so it needs
+	 * to be done explicitly instead.
+	 */
+	gpio_set_level(GPIO_EC_MIC_OE, 1);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+/******************************************************************************/
+/* USB-A port control */
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_PP5000_USB_VBUS,
+};
+
+int64_t get_time_dsw_pwrok(void)
+{
+	/* DSW_PWROK is turned on before EC was powered. */
+	return -20 * MSEC;
+}
+
+int extpower_is_present(void)
+{
+	/* genesis: If the EC is running, then there is external power */
+	return 1;
+}
+
+int board_is_c10_gate_enabled(void)
+{
+	/*
+	 * Puff proto drives EN_PP5000_HDMI from EN_S0_RAILS so we cannot gate
+	 * core rails while in S0 because HDMI should remain powered.
+	 * EN_PP5000_HDMI is a separate EC output on all other boards.
+	 */
+	return board_version != 0;
+}
+
+void board_enable_s0_rails(int enable)
+{
+	/* This output isn't connected on protos; safe to set anyway. */
+	gpio_set_level(GPIO_EN_PP5000_HDMI, enable);
+
+	/*
+	 * Toggle scaler power and its downstream USB devices.
+	 */
+	gpio_set_level(GPIO_EC_SCALER_EN, enable);
+	gpio_set_level(GPIO_PWR_CTRL, enable);
+	gpio_set_level(GPIO_EC_MX8M_ONOFF, enable);
+	gpio_set_level(GPIO_EC_CAM_V3P3_EN, enable);
+
+	gpio_set_level(GPIO_EN_LOAD_SWITCH, enable);
+}
+
+/*
+ * TPU is turned on in S0, off in S0ix and lower.
+ */
+static void disable_tpu_power(void)
+{
+	gpio_set_level(GPIO_PP3300_TPU_A_EN, 0);
+	gpio_set_level(GPIO_EC_IMX8_EN, 0);
+}
+
+static void enable_tpu_power(void)
+{
+	gpio_set_level(GPIO_PP3300_TPU_A_EN, 1);
+	gpio_set_level(GPIO_EC_IMX8_EN, 1);
+}
+
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, disable_tpu_power, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, enable_tpu_power, HOOK_PRIO_DEFAULT);
+
+int ec_config_get_usb4_present(void)
+{
+	return !(fw_config & EC_CFG_NO_USB4_MASK);
+}
+
+unsigned int ec_config_get_thermal_solution(void)
+{
+	return (fw_config & EC_CFG_THERMAL_MASK) >> EC_CFG_THERMAL_L;
+}
+
+static void setup_thermal(void)
+{
+	unsigned int table = ec_config_get_thermal_solution();
+	/* Configure Fan */
+	switch (table) {
+	/* Default and table0 use single fan */
+	case 0:
+	default:
+		thermal_params[TEMP_SENSOR_CORE] = thermal_a;
+		thermal_params[TEMP_SENSOR_WIFI] = thermal_a;
+		break;
+	/* Table1 is fanless */
+	case 1:
+		fan_set_count(0);
+		thermal_params[TEMP_SENSOR_CORE] = thermal_b;
+		break;
+	}
+}
+/* fan_set_count should be called before  HOOK_INIT/HOOK_PRIO_DEFAULT */
+DECLARE_HOOK(HOOK_INIT, setup_thermal, HOOK_PRIO_DEFAULT - 1);
+
+/*
+ * Power monitoring and management.
+ *
+ * The overall goal is to gracefully manage the power demand so that
+ * the power budgets are met without letting the system fall into
+ * power deficit (perhaps causing a brownout).
+ *
+ * There are 2 power budgets that need to be managed:
+ *  - overall system power as measured on the main power supply rail.
+ *  - 5V power delivered to the USB and HDMI ports.
+ *
+ * The actual system power demand is calculated from the VBUS voltage and
+ * the input current (read from a shunt), averaged over 5 readings.
+ * The power budget limit is from the charge manager.
+ *
+ * The 5V power cannot be read directly. Instead, we rely on overcurrent
+ * inputs from the USB and HDMI ports to indicate that the port is in use
+ * (and drawing maximum power).
+ *
+ * There are 3 throttles that can be applied (in priority order):
+ *
+ *  - Type A BC1.2 front port restriction (3W)
+ *  - Type C PD (throttle to 1.5A if sourcing)
+ *  - Turn on PROCHOT, which immediately throttles the CPU.
+ *
+ *  The first 2 throttles affect both the system power and the 5V rails.
+ *  The third is a last resort to force an immediate CPU throttle to
+ *  reduce the overall power use.
+ *
+ *  The strategy is to determine what the state of the throttles should be,
+ *  and to then turn throttles off or on as needed to match this.
+ *
+ *  This function runs on demand, or every 2 ms when the CPU is up,
+ *  and continually monitors the power usage, applying the
+ *  throttles when necessary.
+ *
+ *  All measurements are in milliwatts.
+ */
+#define THROT_TYPE_A BIT(0)
+#define THROT_TYPE_C BIT(1)
+#define THROT_PROCHOT BIT(2)
+
+/*
+ * Power gain if front USB A ports are limited.
+ */
+#define POWER_GAIN_TYPE_A 3200
+/*
+ * Power gain if Type C port is limited.
+ */
+#define POWER_GAIN_TYPE_C 8800
+/*
+ * Power is averaged over 10 ms, with a reading every 2 ms.
+ */
+#define POWER_DELAY_MS 2
+#define POWER_READINGS (10 / POWER_DELAY_MS)
+
+static void power_monitor(void)
+{
+	static uint32_t current_state;
+	int32_t delay;
+	uint32_t new_state = 0, diff;
+	int32_t headroom_5v = PWR_MAX - base_5v_power;
+
+	/*
+	 * If CPU is off or suspended, no need to throttle
+	 * or restrict power.
+	 */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF | CHIPSET_STATE_SUSPEND)) {
+		/*
+		 * Slow down monitoring, assume no throttling required.
+		 */
+		delay = 20 * MSEC;
+	} else {
+		delay = POWER_DELAY_MS * MSEC;
+	}
+	/*
+	 * Check the 5v power usage and if necessary,
+	 * adjust the throttles in priority order.
+	 *
+	 * Either throttle may have already been activated by
+	 * the overall power control.
+	 *
+	 * We rely on the overcurrent detection to inform us
+	 * if the port is in use.
+	 *
+	 *  - If type C not already throttled:
+	 *	* If not overcurrent, prefer to limit type C [1].
+	 *	* If in overcurrentuse:
+	 *		- limit type A first [2]
+	 *		- If necessary, limit type C [3].
+	 *  - If type A not throttled, if necessary limit it [2].
+	 */
+	if (headroom_5v < 0) {
+		/*
+		 * Check whether type C is not throttled,
+		 * and is not overcurrent.
+		 */
+		if (!((new_state & THROT_TYPE_C) || usbc_overcurrent)) {
+			/*
+			 * [1] Type C not in overcurrent, throttle it.
+			 */
+			headroom_5v += PWR_C_HIGH - PWR_C_LOW;
+			new_state |= THROT_TYPE_C;
+		}
+		/*
+		 * [2] If type A not already throttled, and power still
+		 * needed, limit type A.
+		 */
+		if (!(new_state & THROT_TYPE_A) && headroom_5v < 0) {
+			headroom_5v += PWR_FRONT_HIGH - PWR_FRONT_LOW;
+			new_state |= THROT_TYPE_A;
+		}
+		/*
+		 * [3] If still under-budget, limit type C.
+		 * No need to check if it is already throttled or not.
+		 */
+		if (headroom_5v < 0)
+			new_state |= THROT_TYPE_C;
+	}
+	/*
+	 * Turn the throttles on or off if they have changed.
+	 */
+	diff = new_state ^ current_state;
+	current_state = new_state;
+	if (diff & THROT_PROCHOT) {
+		int prochot = (new_state & THROT_PROCHOT) ? 0 : 1;
+
+		gpio_set_level(GPIO_EC_PROCHOT_ODL, prochot);
+	}
+	if (diff & THROT_TYPE_A) {
+		int typea_bc = (new_state & THROT_TYPE_A) ? 1 : 0;
+
+		gpio_set_level(GPIO_USB_A_LOW_PWR_OD, typea_bc);
+	}
+	hook_call_deferred(&power_monitor_data, delay);
+}
diff --git a/board/scout/board.h b/board/scout/board.h
new file mode 100644
index 0000000000..33f3cb758f
--- /dev/null
+++ b/board/scout/board.h
@@ -0,0 +1,266 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Puff board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#undef CONFIG_UART_TX_BUF_SIZE
+#define CONFIG_UART_TX_BUF_SIZE 4096
+
+/* NPCX7 config */
+#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */
+#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */
+
+/* Internal SPI flash on NPCX796FC is 512 kB */
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
+#define CONFIG_SPI_FLASH_REGS
+#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
+
+/* EC Defines */
+#define CONFIG_ADC
+#define CONFIG_BOARD_HAS_RTC_RESET
+#define CONFIG_BOARD_VERSION_CBI
+#define CONFIG_DEDICATED_RECOVERY_BUTTON
+#define CONFIG_DEDICATED_RECOVERY_BUTTON_2
+#define CONFIG_BUTTONS_RUNTIME_CONFIG
+#define CONFIG_BOARD_RESET_AFTER_POWER_ON
+/* TODO: (b/143496253) re-enable CEC */
+/* #define CONFIG_CEC */
+#define CONFIG_CRC8
+#define CONFIG_CBI_EEPROM
+#define CONFIG_EMULATED_SYSRQ
+#undef CONFIG_KEYBOARD_BOOT_KEYS
+#define CONFIG_MKBP_INPUT_DEVICES
+#define CONFIG_MKBP_USE_HOST_EVENT
+#undef CONFIG_KEYBOARD_RUNTIME_KEYS
+#undef CONFIG_HIBERNATE
+#define CONFIG_HOST_INTERFACE_ESPI
+#define CONFIG_LED_COMMON
+#undef CONFIG_LID_SWITCH
+#define CONFIG_LTO
+#define CONFIG_PWM
+#define CONFIG_VBOOT_EFS2
+#define CONFIG_VBOOT_HASH
+#define CONFIG_VSTORE
+#define CONFIG_VSTORE_SLOT_COUNT 1
+#define CONFIG_SHA256
+
+/* Sensor */
+#undef CONFIG_MOTION_SENSE_RESUME_DELAY_US
+#define CONFIG_MOTION_SENSE_RESUME_DELAY_US (1000 * MSEC)
+#define CONFIG_CMD_ACCEL_INFO
+/* Enable sensor fifo, must also define the _SIZE and _THRES */
+#define CONFIG_ACCEL_FIFO
+/* FIFO size is in power of 2. */
+#define CONFIG_ACCEL_FIFO_SIZE 256
+/* Depends on how fast the AP boots and typical ODRs */
+#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
+
+/* TCS3400 ALS */
+#define CONFIG_ALS
+#define ALS_COUNT 1
+#define CONFIG_ALS_TCS3400
+#define CONFIG_ALS_TCS3400_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS)
+
+/* Sensors without hardware FIFO are in forced mode */
+#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(CLEAR_ALS)
+
+/* EC Commands */
+#define CONFIG_CMD_BUTTON
+/* Include CLI command needed to support CCD testing. */
+#define CONFIG_CMD_CHARGEN
+#undef CONFIG_CMD_FASTCHARGE
+#undef CONFIG_CMD_KEYBOARD
+#define CONFIG_HOSTCMD_PD_CONTROL
+#undef CONFIG_CMD_PWR_AVG
+#define CONFIG_CMD_PPC_DUMP
+#define CONFIG_CMD_TCPC_DUMP
+#ifdef SECTION_IS_RO
+/* Reduce RO size by removing less-relevant commands. */
+#undef CONFIG_CMD_APTHROTTLE
+#undef CONFIG_CMD_CHARGEN
+#undef CONFIG_CMD_HCDEBUG
+#undef CONFIG_CMD_MMAPINFO
+#endif
+
+#undef CONFIG_CONSOLE_CMDHELP
+
+/* Don't generate host command debug by default */
+#undef CONFIG_HOSTCMD_DEBUG_MODE
+#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
+
+/* Enable AP Reset command for TPM with old firmware version to detect it. */
+#define CONFIG_CMD_AP_RESET_LOG
+#define CONFIG_HOSTCMD_AP_RESET
+
+/* Chipset config */
+#define CONFIG_CHIPSET_COMETLAKE_DISCRETE
+/* check */
+#define CONFIG_CHIPSET_CAN_THROTTLE
+#define CONFIG_CHIPSET_RESET_HOOK
+#define CONFIG_CPU_PROCHOT_ACTIVE_LOW
+
+#define CONFIG_POWER_BUTTON
+#define CONFIG_POWER_BUTTON_IGNORE_LID
+#define CONFIG_POWER_BUTTON_X86
+/* Check: */
+#define CONFIG_POWER_BUTTON_INIT_IDLE
+#define CONFIG_POWER_COMMON
+#define CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD 30
+#define CONFIG_DELAY_DSW_PWROK_TO_PWRBTN
+#define CONFIG_POWER_PP5000_CONTROL
+#define CONFIG_POWER_S0IX
+#define CONFIG_POWER_SLEEP_FAILURE_DETECTION
+#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
+#define CONFIG_INA3221
+
+/* Fan and temp. */
+#define CONFIG_FANS 1
+#undef CONFIG_FAN_INIT_SPEED
+#define CONFIG_FAN_INIT_SPEED 0
+#define CONFIG_FAN_RPM_CUSTOM
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_TEMP_SENSOR_POWER
+#define CONFIG_THERMISTOR
+#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
+#define CONFIG_THROTTLE_AP
+
+#define CONFIG_USB_PD_PORT_MAX_COUNT 0
+
+/* USB Type A Features */
+#define CONFIG_USB_PORT_POWER_DUMB
+/* There are five ports, but power enable is ganged across all of them. */
+#define USB_PORT_COUNT 1
+
+/* I2C Bus Configuration */
+#define CONFIG_I2C
+#define CONFIG_I2C_CONTROLLER
+#define I2C_PORT_INA NPCX_I2C_PORT0_0
+#define I2C_PORT_PPC0 NPCX_I2C_PORT1_0
+#define I2C_PORT_SCALER NPCX_I2C_PORT2_0
+#define I2C_PORT_SENSORS NPCX_I2C_PORT3_0
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT3_0
+#define I2C_PORT_POWER NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+
+#define PP5000_PGOOD_POWER_SIGNAL_MASK POWER_SIGNAL_MASK(PP5000_A_PGOOD)
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum board_version {
+	BOARD_VERSION_PROTO = 1,
+	BOARD_VERSION_PRE_EVT = 2,
+	BOARD_VERSION_EVT = 3,
+	BOARD_VERSION_DVT = 4,
+	BOARD_VERSION_PVT = 5,
+};
+
+enum adc_channel {
+	ADC_SNS_PP3300, /* ADC2 */
+	ADC_SNS_PP1050, /* ADC7 */
+	ADC_VBUS, /* ADC4 */
+	ADC_PPVAR_IMON, /* ADC9 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
+	/* Number of ADC channels */
+	ADC_CH_COUNT
+};
+
+enum pwm_channel {
+	PWM_CH_FAN,
+	PWM_CH_LED_RED,
+	PWM_CH_LED_WHITE,
+	/* Number of PWM channels */
+	PWM_CH_COUNT
+};
+
+enum fan_channel {
+	FAN_CH_0,
+	/* Number of FAN channels */
+	FAN_CH_COUNT
+};
+
+enum mft_channel {
+	MFT_CH_0 = 0,
+	/* Number of MFT channels */
+	MFT_CH_COUNT,
+};
+
+enum temp_sensor_id { TEMP_SENSOR_CORE, TEMP_SENSOR_WIFI, TEMP_SENSOR_COUNT };
+
+enum sensor_id {
+	CLEAR_ALS,
+	RGB_ALS,
+	SENSOR_COUNT,
+};
+
+/* Board specific handlers */
+void board_reset_pd_mcu(void);
+void board_set_tcpc_power_mode(int port, int mode);
+void led_alert(int enable);
+void show_critical_error(void);
+
+/*
+ * firmware config fields
+ */
+/*
+ * Barrel-jack power (4 bits).
+ */
+#define EC_CFG_BJ_POWER_L 0
+#define EC_CFG_BJ_POWER_H 3
+#define EC_CFG_BJ_POWER_MASK GENMASK(EC_CFG_BJ_POWER_H, EC_CFG_BJ_POWER_L)
+/*
+ * USB Connector 4 not present (1 bit).
+ */
+#define EC_CFG_NO_USB4_L 4
+#define EC_CFG_NO_USB4_H 4
+#define EC_CFG_NO_USB4_MASK GENMASK(EC_CFG_NO_USB4_H, EC_CFG_NO_USB4_L)
+/*
+ * Thermal solution config (3 bits).
+ */
+#define EC_CFG_THERMAL_L 5
+#define EC_CFG_THERMAL_H 7
+#define EC_CFG_THERMAL_MASK GENMASK(EC_CFG_THERMAL_H, EC_CFG_THERMAL_L)
+
+int ec_config_get_usb4_present(void);
+unsigned int ec_config_get_thermal_solution(void);
+
+#endif /* !__ASSEMBLER__ */
+
+/* Pin renaming */
+#define GPIO_WP_L GPIO_EC_WP_ODL
+#define GPIO_PP5000_A_PG_OD GPIO_PG_PP5000_A_OD
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
+#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_ODL
+#define GPIO_RECOVERY_L_2 GPIO_H1_EC_RECOVERY_BTN_ODL
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_EN_ROA_RAILS
+#define GPIO_AC_PRESENT GPIO_BJ_ADP_PRESENT_L
+
+/*
+ * There is no RSMRST input, so alias it to the output. This short-circuits
+ * common_intel_x86_handle_rsmrst.
+ */
+#define GPIO_PG_EC_RSMRST_ODL GPIO_PCH_RSMRST_L
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/scout/build.mk b/board/scout/build.mk
new file mode 100644
index 0000000000..7b9d891a0c
--- /dev/null
+++ b/board/scout/build.mk
@@ -0,0 +1,14 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx7
+CHIP_VARIANT:=npcx7m6fc
+
+board-y=board.o
+board-y+=led.o
diff --git a/board/scout/ec.tasklist b/board/scout/ec.tasklist
new file mode 100644
index 0000000000..0c3296d173
--- /dev/null
+++ b/board/scout/ec.tasklist
@@ -0,0 +1,16 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 2048) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/scout/gpio.inc b/board/scout/gpio.inc
new file mode 100644
index 0000000000..8a6b5bb074
--- /dev/null
+++ b/board/scout/gpio.inc
@@ -0,0 +1,172 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Pin names follow the schematic, and are aliased to other names if necessary.
+ * Note: Those with interrupt handlers must be declared first. */
+
+/* Latency on this interrupt is extremely critical, so it comes first to ensure
+ * it gets placed first in gpio_wui_table so gpio_interrupt() needs to do
+ * minimal scanning. */
+GPIO_INT(CPU_C10_GATE_L,       PIN(6, 7), GPIO_INT_BOTH, c10_gate_interrupt)
+
+/* Wake Source interrupts */
+GPIO_INT(EC_WP_ODL,            PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(H1_EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
+
+/* Power sequencing interrupts */
+GPIO_INT(PG_PP5000_A_OD,       PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_PP1800_A_OD,       PIN(3, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_VPRIM_CORE_A_OD,   PIN(2, 3), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_PP1050_A_OD,       PIN(2, 2), GPIO_INT_BOTH, power_signal_interrupt)
+/* EC output, but also interrupt so this can be polled as a power signal */
+GPIO_INT(EC_PCH_RSMRST_L,      PIN(A, 6), GPIO_OUTPUT | GPIO_INT_F_RISING | GPIO_INT_F_FALLING, power_signal_interrupt)
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
+GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
+#endif
+GPIO_INT(PG_PP2500_DRAM_U_OD,  PIN(2, 0), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_PP1200_U_OD,       PIN(2, 1), GPIO_INT_BOTH, power_signal_interrupt)
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, slp_s3_interrupt)
+#endif
+GPIO_INT(PG_PP950_VCCIO_OD,    PIN(1, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(IMVP8_VRRDY_OD,       PIN(1, 6), GPIO_INT_BOTH, power_signal_interrupt)
+/* ALS signals */
+GPIO_INT(EC_RGB_INT_L,         PIN(9, 7), GPIO_INT_FALLING, tcs3400_interrupt)
+/*
+ * Directly connected recovery button (not available on some boards).
+ */
+GPIO_INT(EC_RECOVERY_BTN_ODL,  PIN(F, 1), GPIO_INT_BOTH, button_interrupt)
+/*
+ * Recovery button input from H1.
+ */
+GPIO_INT(H1_EC_RECOVERY_BTN_ODL, PIN(2, 4), GPIO_INT_BOTH, button_interrupt)
+GPIO(BJ_ADP_PRESENT_L,     PIN(8, 2), GPIO_INT_BOTH | GPIO_PULL_UP)
+
+/* Port power control interrupts */
+GPIO_INT(HDMI_CONN0_OC_ODL,    PIN(0, 7), GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(HDMI_CONN1_OC_ODL,    PIN(0, 6), GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(USB_A0_OC_ODL,        PIN(E, 4), GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(USB_A1_OC_ODL,        PIN(A, 2), GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(USB_A2_OC_ODL,        PIN(F, 5), GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(USB_A3_OC_ODL,        PIN(0, 3), GPIO_INT_BOTH, port_ocp_interrupt)
+
+/* PCH/CPU signals */
+GPIO(EC_PCH_PWROK,             PIN(0, 5), GPIO_OUT_LOW)
+GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
+GPIO(EC_PCH_PWR_BTN_ODL,       PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_IN_OD,         PIN(3, 4), GPIO_INPUT)
+GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
+GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
+
+/* i.MX8 soundbar signals */
+GPIO(BOOT_IND_EC,              PIN(E, 2), GPIO_INPUT)
+
+/* TSUM scaler signals */
+GPIO(TSUM_WAKEUP_EC,           PIN(B, 1), GPIO_INPUT)
+
+/* Power control outputs */
+GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
+GPIO(EN_PP3300_INA_H1_EC_ODL,  PIN(5, 7), GPIO_ODR_HIGH)
+GPIO(EN_PP1800_A,              PIN(1, 5), GPIO_OUT_LOW)
+GPIO(VCCST_PG_OD,              PIN(1, 4), GPIO_ODR_LOW)
+GPIO(EN_S0_RAILS,              PIN(1, 1), GPIO_OUT_LOW)
+GPIO(EN_ROA_RAILS,             PIN(A, 3), GPIO_OUT_LOW)
+GPIO(EN_PP950_VCCIO,           PIN(1, 0), GPIO_OUT_LOW)
+GPIO(EC_IMVP8_PE,              PIN(A, 7), GPIO_OUT_LOW)
+GPIO(EN_IMVP8_VR,              PIN(F, 4), GPIO_OUT_LOW)
+GPIO(EC_CAM_V3P3_EN,           PIN(C, 6), GPIO_OUT_LOW)
+GPIO(EC_MX8M_ONOFF,            PIN(9, 3), GPIO_OUT_LOW)
+GPIO(EC_SCALER_EN,             PIN(E, 0), GPIO_OUT_LOW)
+GPIO(EC_IMX8_EN,               PIN(C, 0), GPIO_OUT_LOW)
+GPIO(PP3300_TPU_A_EN,          PIN(B, 0), GPIO_OUT_LOW)
+GPIO(PWR_CTRL,                 PIN(6, 2), GPIO_OUT_LOW)
+GPIO(EN_LOAD_SWITCH,           PIN(4, 2), GPIO_OUT_LOW)
+
+/* Barreljack */
+GPIO(EN_PPVAR_BJ_ADP_L,        PIN(0, 4), GPIO_OUT_LOW)
+
+/* USB type A */
+GPIO(EN_PP5000_USB_VBUS,       PIN(8, 3), GPIO_OUT_LOW)
+GPIO(USB_A_LOW_PWR_OD,         PIN(9, 4), GPIO_ODR_LOW)
+GPIO(USB_A2_STATUS_L,          PIN(6, 1), GPIO_INPUT)
+GPIO(USB_A3_STATUS_L,          PIN(C, 7), GPIO_INPUT)
+
+/* USB type C */
+GPIO(USB_C0_POL_L,             PIN(0, 0), GPIO_INPUT | GPIO_SEL_1P8V) /* USB-C Polarity */
+
+/* Misc. */
+GPIO(M2_SSD_PLN,               PIN(A, 0), GPIO_INPUT)
+GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
+GPIO(CCD_MODE_ODL,             PIN(E, 5), GPIO_ODR_HIGH)
+GPIO(PACKET_MODE_EN,           PIN(7, 5), GPIO_OUT_LOW)
+GPIO(EN_PP_MST_OD,             PIN(9, 6), GPIO_OUT_HIGH)
+GPIO(EC_MIC_OE,                PIN(6, 0), GPIO_OUT_HIGH)
+
+/* HDMI/CEC */
+GPIO(EN_PP5000_HDMI,           PIN(5, 0), GPIO_OUT_LOW)
+GPIO(HDMI_CONN0_CEC_IN,        PIN(4, 0), GPIO_INPUT)
+GPIO(HDMI_CONN1_CEC_OUT,       PIN(9, 5), GPIO_ODR_HIGH)
+GPIO(HDMI_CONN1_CEC_IN,        PIN(D, 3), GPIO_INPUT)
+
+/* I2C pins - Alternate function below configures I2C module on these pins */
+GPIO(I2C0_SCL,                 PIN(B, 5), GPIO_INPUT)                 /* EC_I2C_INA_SCL */
+GPIO(I2C0_SDA,                 PIN(B, 4), GPIO_INPUT)                 /* EC_I2C_INA_SDA */
+GPIO(I2C1_SCL,                 PIN(9, 0), GPIO_INPUT)                 /* EC_I2C_USB_C0_TCPPC_SCL */
+GPIO(I2C1_SDA,                 PIN(8, 7), GPIO_INPUT)                 /* EC_I2C_USB_C0_TCPPC_SDA */
+GPIO(I2C2_SCL,                 PIN(9, 2), GPIO_INPUT)                 /* EC_I2C_DDR_SCALER_SCL */
+GPIO(I2C2_SDA,                 PIN(9, 1), GPIO_INPUT)                 /* EC_I2C_DDR_SCALER_SDA */
+GPIO(I2C3_SCL,                 PIN(D, 1), GPIO_INPUT | GPIO_SEL_1P8V) /* EC_I2C_ALS_SCL */
+GPIO(I2C3_SDA,                 PIN(D, 0), GPIO_INPUT | GPIO_SEL_1P8V) /* EC_I2C_ALS_SDA */
+GPIO(I2C5_SCL,                 PIN(3, 3), GPIO_INPUT)                 /* EC_I2C_IMVP8_SCL */
+GPIO(I2C5_SDA,                 PIN(3, 6), GPIO_INPUT)                 /* EC_I2C_IMVP8_SDA */
+GPIO(I2C7_SCL,                 PIN(B, 3), GPIO_INPUT)                 /* EC_I2C_EEPROM_SCL */
+GPIO(I2C7_SDA,                 PIN(B, 2), GPIO_INPUT)                 /* EC_I2C_EEPROM_SDA */
+
+/* Alternate functions GPIO definitions */
+ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, 0)                  /* I2C0 */
+ALTERNATE(PIN_MASK(9, 0x01), 0, MODULE_I2C, 0)                  /* I2C1 SCL */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)                  /* I2C1 SDA */
+ALTERNATE(PIN_MASK(9, 0x03), 0, MODULE_I2C, 0)                  /* I2C2 */
+ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)                  /* I2C3 */
+ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)                  /* I2C5 */
+ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, 0)                  /* I2C7 */
+
+/* PWM */
+ALTERNATE(PIN_MASK(C, 0x08), 0, MODULE_PWM, 0)                  /* PWM0 - Red Led */
+ALTERNATE(PIN_MASK(C, 0x10), 0, MODULE_PWM, 0)                  /* PWM2 - White Led */
+ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)                  /* PWM5 - Fan 1 */
+ALTERNATE(PIN_MASK(7, 0x08), 0, MODULE_PWM, 0)                  /* TA2 - Fan Tachometer */
+
+/* ADC */
+ALTERNATE(PIN_MASK(4, 0x3A), 0, MODULE_ADC, 0)                  /* ADC0, ADC1, ADC2, ADC4 */
+ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0)                  /* ADC7 */
+ALTERNATE(PIN_MASK(F, 0x01), 0, MODULE_ADC, 0)                  /* ADC9 */
+
+/* UART */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)                 /* UART from EC to Servo */
+
+/* Unused pins */
+UNUSED(PIN(1, 3))						/* EC_GP_SEL1_ODL */
+UNUSED(PIN(8, 0))						/* LED_BLUE_L */
+UNUSED(PIN(C, 2))						/* A12 NC */
+UNUSED(PIN(1, 2))						/* C6  NC */
+UNUSED(PIN(6, 6))						/* H4  NC */
+UNUSED(PIN(8, 1))						/* L6  NC */
+UNUSED(PIN(8, 5))						/* L7  NC */
+UNUSED(PIN(3, 2))						/* E5  NC */
+UNUSED(PIN(D, 6))						/* F6  NC */
+UNUSED(PIN(3, 5))						/* F5  NC */
+UNUSED(PIN(5, 6))						/* M2  NC */
+UNUSED(PIN(D, 2))						/* C11 NC */
+UNUSED(PIN(8, 6))						/* J8  NC */
+UNUSED(PIN(7, 2))						/* H6  NC */
+UNUSED(PIN(F, 2))						/* E11 NC */
+UNUSED(PIN(F, 3))						/* F7  NC */
diff --git a/board/scout/led.c b/board/scout/led.c
new file mode 100644
index 0000000000..ad244ab99e
--- /dev/null
+++ b/board/scout/led.c
@@ -0,0 +1,284 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power LED control for Puff.
+ * Solid green - active power
+ * Green flashing - suspended
+ * Red flashing - alert
+ * Solid red - critical
+ */
+
+#include "chipset.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "led_common.h"
+#include "pwm.h"
+#include "timer.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
+
+/*
+ * Due to the CSME-Lite processing, upon startup the CPU transitions through
+ * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so
+ * delay turning off the LED during suspend/shutdown.
+ */
+#define LED_CPU_DELAY_MS (2000 * MSEC)
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED };
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+enum led_color {
+	LED_OFF = 0,
+	LED_RED,
+	LED_WHITE,
+	LED_AMBER,
+
+	/* Number of colors, not a color itself */
+	LED_COLOR_COUNT
+};
+
+static int set_color_power(enum led_color color, int duty)
+{
+	int white = 0;
+	int red = 0;
+
+	if (duty < 0 || 100 < duty)
+		return EC_ERROR_UNKNOWN;
+
+	switch (color) {
+	case LED_OFF:
+		break;
+	case LED_WHITE:
+		white = 1;
+		break;
+	case LED_RED:
+		red = 1;
+		break;
+	case LED_AMBER:
+		red = 1;
+		white = 1;
+		break;
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+
+	if (red)
+		pwm_set_duty(PWM_CH_LED_RED, duty);
+	else
+		pwm_set_duty(PWM_CH_LED_RED, 0);
+
+	if (white)
+		pwm_set_duty(PWM_CH_LED_WHITE, duty);
+	else
+		pwm_set_duty(PWM_CH_LED_WHITE, 0);
+
+	return EC_SUCCESS;
+}
+
+static int set_color(enum ec_led_id id, enum led_color color, int duty)
+{
+	switch (id) {
+	case EC_LED_ID_POWER_LED:
+		return set_color_power(color, duty);
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+}
+
+#define LED_PULSE_US (2 * SECOND)
+/* 40 msec for nice and smooth transition. */
+#define LED_PULSE_TICK_US (40 * MSEC)
+
+/* When pulsing is enabled, brightness is incremented by <duty_inc> every
+ * <interval> usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented
+ * likewise in LED_PULSE_US usec.
+ */
+static struct {
+	uint32_t interval;
+	int duty_inc;
+	enum led_color color;
+	int duty;
+} led_pulse;
+
+#define CONFIG_TICK(interval, color) \
+	config_tick((interval), 100 / (LED_PULSE_US / (interval)), (color))
+
+static void config_tick(uint32_t interval, int duty_inc, enum led_color color)
+{
+	led_pulse.interval = interval;
+	led_pulse.duty_inc = duty_inc;
+	led_pulse.color = color;
+	led_pulse.duty = 0;
+}
+
+static void pulse_power_led(enum led_color color)
+{
+	set_color(EC_LED_ID_POWER_LED, color, led_pulse.duty);
+	if (led_pulse.duty + led_pulse.duty_inc > 100)
+		led_pulse.duty_inc = led_pulse.duty_inc * -1;
+	else if (led_pulse.duty + led_pulse.duty_inc < 0)
+		led_pulse.duty_inc = led_pulse.duty_inc * -1;
+	led_pulse.duty += led_pulse.duty_inc;
+}
+
+static void led_tick(void);
+DECLARE_DEFERRED(led_tick);
+static void led_tick(void)
+{
+	uint32_t elapsed;
+	uint32_t next = 0;
+	uint32_t start = get_time().le.lo;
+
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		pulse_power_led(led_pulse.color);
+	elapsed = get_time().le.lo - start;
+	next = led_pulse.interval > elapsed ? led_pulse.interval - elapsed : 0;
+	hook_call_deferred(&led_tick_data, next);
+}
+
+static void led_suspend(void)
+{
+	CONFIG_TICK(LED_PULSE_TICK_US, LED_WHITE);
+	led_tick();
+}
+DECLARE_DEFERRED(led_suspend);
+
+static void led_shutdown(void)
+{
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_OFF, 0);
+}
+DECLARE_DEFERRED(led_shutdown);
+
+static void led_shutdown_hook(void)
+{
+	hook_call_deferred(&led_tick_data, -1);
+	hook_call_deferred(&led_suspend_data, -1);
+	hook_call_deferred(&led_shutdown_data, LED_CPU_DELAY_MS);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, led_shutdown_hook, HOOK_PRIO_DEFAULT);
+
+static void led_suspend_hook(void)
+{
+	hook_call_deferred(&led_shutdown_data, -1);
+	hook_call_deferred(&led_suspend_data, LED_CPU_DELAY_MS);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, led_suspend_hook, HOOK_PRIO_DEFAULT);
+
+static void led_resume(void)
+{
+	/* Assume there is no race condition with led_tick, which also
+	 * runs in hook_task.
+	 */
+	hook_call_deferred(&led_tick_data, -1);
+	/*
+	 * Avoid invoking the suspend/shutdown delayed hooks.
+	 */
+	hook_call_deferred(&led_suspend_data, -1);
+	hook_call_deferred(&led_shutdown_data, -1);
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_WHITE, 100);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, led_resume, HOOK_PRIO_DEFAULT);
+
+static void led_init(void)
+{
+	pwm_enable(PWM_CH_LED_RED, 1);
+	pwm_enable(PWM_CH_LED_WHITE, 1);
+
+	if (chipset_in_state(CHIPSET_STATE_ON))
+		led_resume();
+	else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
+		led_suspend();
+	else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		led_shutdown();
+}
+DECLARE_HOOK(HOOK_INIT, led_init, HOOK_PRIO_INIT_PWM + 1);
+
+void board_led_auto_control(void)
+{
+	if (chipset_in_state(CHIPSET_STATE_ON))
+		led_resume();
+	else if (chipset_in_state(CHIPSET_STATE_SUSPEND))
+		led_suspend_hook();
+	else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		led_shutdown_hook();
+}
+
+void led_alert(int enable)
+{
+	if (enable) {
+		/* Overwrite the current signal */
+		config_tick(1 * SECOND, 100, LED_RED);
+		led_tick();
+	} else {
+		/* Restore the previous signal */
+		if (chipset_in_state(CHIPSET_STATE_ON))
+			led_resume();
+		else if (chipset_in_state(CHIPSET_STATE_SUSPEND))
+			led_suspend_hook();
+		else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+			led_shutdown_hook();
+	}
+}
+
+void show_critical_error(void)
+{
+	hook_call_deferred(&led_tick_data, -1);
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_RED, 100);
+}
+
+static int command_led(int argc, const char **argv)
+{
+	enum ec_led_id id = EC_LED_ID_POWER_LED;
+
+	if (argc < 2)
+		return EC_ERROR_PARAM_COUNT;
+
+	if (!strcasecmp(argv[1], "debug")) {
+		led_auto_control(id, !led_auto_control_is_enabled(id));
+		ccprintf("o%s\n", led_auto_control_is_enabled(id) ? "ff" : "n");
+	} else if (!strcasecmp(argv[1], "off")) {
+		set_color(id, LED_OFF, 0);
+	} else if (!strcasecmp(argv[1], "red")) {
+		set_color(id, LED_RED, 100);
+	} else if (!strcasecmp(argv[1], "white")) {
+		set_color(id, LED_WHITE, 100);
+	} else if (!strcasecmp(argv[1], "amber")) {
+		set_color(id, LED_AMBER, 100);
+	} else if (!strcasecmp(argv[1], "alert")) {
+		led_alert(1);
+	} else if (!strcasecmp(argv[1], "crit")) {
+		show_critical_error();
+	} else {
+		return EC_ERROR_PARAM1;
+	}
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(led, command_led,
+			"[debug|red|white|amber|off|alert|crit]",
+			"Turn on/off LED.");
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	brightness_range[EC_LED_COLOR_RED] = 100;
+	brightness_range[EC_LED_COLOR_WHITE] = 100;
+	brightness_range[EC_LED_COLOR_AMBER] = 100;
+}
+
+int led_set_brightness(enum ec_led_id id, const uint8_t *brightness)
+{
+	if (brightness[EC_LED_COLOR_RED])
+		return set_color(id, LED_RED, brightness[EC_LED_COLOR_RED]);
+	else if (brightness[EC_LED_COLOR_WHITE])
+		return set_color(id, LED_WHITE, brightness[EC_LED_COLOR_WHITE]);
+	else if (brightness[EC_LED_COLOR_AMBER])
+		return set_color(id, LED_AMBER, brightness[EC_LED_COLOR_AMBER]);
+	else
+		return set_color(id, LED_OFF, 0);
+}
diff --git a/board/servo_micro/OWNERS b/board/servo_micro/OWNERS
new file mode 100644
index 0000000000..3a4b8d3c05
--- /dev/null
+++ b/board/servo_micro/OWNERS
@@ -0,0 +1,2 @@
+bnemec@google.com
+matthewb@chromium.org
diff --git a/board/servo_micro/board.c b/board/servo_micro/board.c
index 6bbbd85c84..5f8bf1066f 100644
--- a/board/servo_micro/board.c
+++ b/board/servo_micro/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,14 +19,15 @@
 #include "timer.h"
 #include "update_fw.h"
 #include "usart-stm32f0.h"
-#include "usart_tx_dma.h"
 #include "usart_rx_dma.h"
+#include "usart_tx_dma.h"
+#include "usb-stream.h"
 #include "usb_hw.h"
 #include "usb_i2c.h"
 #include "usb_spi.h"
-#include "usb-stream.h"
 #include "util.h"
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 void board_config_pre_init(void)
@@ -45,21 +46,20 @@ void board_config_pre_init(void)
 	 *  i2c : no dma
 	 *  tim16/17: no dma
 	 */
-	STM32_SYSCFG_CFGR1 |= BIT(26);  /* Remap USART3 RX/TX DMA */
+	STM32_SYSCFG_CFGR1 |= BIT(26); /* Remap USART3 RX/TX DMA */
 
 	/* Remap SPI2 to DMA channels 6 and 7 */
 	/* STM32F072 SPI2 defaults to using DMA channels 4 and 5 */
 	/* but cros_ec hardcodes a 6/7 assumption in registers.h */
 	STM32_SYSCFG_CFGR1 |= BIT(24);
-
 }
 
 /******************************************************************************
  * Forward UARTs as a USB serial interface.
  */
 
-#define USB_STREAM_RX_SIZE	32
-#define USB_STREAM_TX_SIZE	64
+#define USB_STREAM_RX_SIZE 32
+#define USB_STREAM_TX_SIZE 64
 
 /******************************************************************************
  * Forward USART2 (EC) as a simple USB serial interface.
@@ -68,33 +68,22 @@ void board_config_pre_init(void)
 static struct usart_config const usart2;
 struct usb_stream_config const usart2_usb;
 
-static struct queue const usart2_to_usb = QUEUE_DIRECT(1024, uint8_t,
-	usart2.producer, usart2_usb.consumer);
-static struct queue const usb_to_usart2 = QUEUE_DIRECT(64, uint8_t,
-	usart2_usb.producer, usart2.consumer);
+static struct queue const usart2_to_usb =
+	QUEUE_DIRECT(1024, uint8_t, usart2.producer, usart2_usb.consumer);
+static struct queue const usb_to_usart2 =
+	QUEUE_DIRECT(64, uint8_t, usart2_usb.producer, usart2.consumer);
 
 static struct usart_rx_dma const usart2_rx_dma =
 	USART_RX_DMA(STM32_DMAC_CH5, 32);
 
 static struct usart_config const usart2 =
-	USART_CONFIG(usart2_hw,
-		usart2_rx_dma.usart_rx,
-		usart_tx_interrupt,
-		115200,
-		0,
-		usart2_to_usb,
-		usb_to_usart2);
-
-USB_STREAM_CONFIG_USART_IFACE(usart2_usb,
-	USB_IFACE_USART2_STREAM,
-	USB_STR_USART2_STREAM_NAME,
-	USB_EP_USART2_STREAM,
-	USB_STREAM_RX_SIZE,
-	USB_STREAM_TX_SIZE,
-	usb_to_usart2,
-	usart2_to_usb,
-	usart2)
+	USART_CONFIG(usart2_hw, usart2_rx_dma.usart_rx, usart_tx_interrupt,
+		     115200, 0, usart2_to_usb, usb_to_usart2);
 
+USB_STREAM_CONFIG_USART_IFACE(usart2_usb, USB_IFACE_USART2_STREAM,
+			      USB_STR_USART2_STREAM_NAME, USB_EP_USART2_STREAM,
+			      USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE,
+			      usb_to_usart2, usart2_to_usb, usart2)
 
 /******************************************************************************
  * Forward USART3 (CPU) as a simple USB serial interface.
@@ -103,33 +92,22 @@ USB_STREAM_CONFIG_USART_IFACE(usart2_usb,
 static struct usart_config const usart3;
 struct usb_stream_config const usart3_usb;
 
-static struct queue const usart3_to_usb = QUEUE_DIRECT(1024, uint8_t,
-	usart3.producer, usart3_usb.consumer);
-static struct queue const usb_to_usart3 = QUEUE_DIRECT(64, uint8_t,
-	usart3_usb.producer, usart3.consumer);
+static struct queue const usart3_to_usb =
+	QUEUE_DIRECT(1024, uint8_t, usart3.producer, usart3_usb.consumer);
+static struct queue const usb_to_usart3 =
+	QUEUE_DIRECT(64, uint8_t, usart3_usb.producer, usart3.consumer);
 
 static struct usart_rx_dma const usart3_rx_dma =
 	USART_RX_DMA(STM32_DMAC_CH3, 32);
 
 static struct usart_config const usart3 =
-	USART_CONFIG(usart3_hw,
-		usart3_rx_dma.usart_rx,
-		usart_tx_interrupt,
-		115200,
-		0,
-		usart3_to_usb,
-		usb_to_usart3);
-
-USB_STREAM_CONFIG_USART_IFACE(usart3_usb,
-	USB_IFACE_USART3_STREAM,
-	USB_STR_USART3_STREAM_NAME,
-	USB_EP_USART3_STREAM,
-	USB_STREAM_RX_SIZE,
-	USB_STREAM_TX_SIZE,
-	usb_to_usart3,
-	usart3_to_usb,
-	usart3)
+	USART_CONFIG(usart3_hw, usart3_rx_dma.usart_rx, usart_tx_interrupt,
+		     115200, 0, usart3_to_usb, usb_to_usart3);
 
+USB_STREAM_CONFIG_USART_IFACE(usart3_usb, USB_IFACE_USART3_STREAM,
+			      USB_STR_USART3_STREAM_NAME, USB_EP_USART3_STREAM,
+			      USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE,
+			      usb_to_usart3, usart3_to_usb, usart3)
 
 /******************************************************************************
  * Forward USART4 (cr50) as a simple USB serial interface.
@@ -139,34 +117,24 @@ USB_STREAM_CONFIG_USART_IFACE(usart3_usb,
 static struct usart_config const usart4;
 struct usb_stream_config const usart4_usb;
 
-static struct queue const usart4_to_usb = QUEUE_DIRECT(64, uint8_t,
-	usart4.producer, usart4_usb.consumer);
-static struct queue const usb_to_usart4 = QUEUE_DIRECT(64, uint8_t,
-	usart4_usb.producer, usart4.consumer);
+static struct queue const usart4_to_usb =
+	QUEUE_DIRECT(1024, uint8_t, usart4.producer, usart4_usb.consumer);
+static struct queue const usb_to_usart4 =
+	QUEUE_DIRECT(64, uint8_t, usart4_usb.producer, usart4.consumer);
 
 static struct usart_config const usart4 =
-	USART_CONFIG(usart4_hw,
-		usart_rx_interrupt,
-		usart_tx_interrupt,
-		115200,
-		0,
-		usart4_to_usb,
-		usb_to_usart4);
-
-USB_STREAM_CONFIG_USART_IFACE(usart4_usb,
-	USB_IFACE_USART4_STREAM,
-	USB_STR_USART4_STREAM_NAME,
-	USB_EP_USART4_STREAM,
-	USB_STREAM_RX_SIZE,
-	USB_STREAM_TX_SIZE,
-	usb_to_usart4,
-	usart4_to_usb,
-	usart4)
+	USART_CONFIG(usart4_hw, usart_rx_interrupt, usart_tx_interrupt, 115200,
+		     0, usart4_to_usb, usb_to_usart4);
+
+USB_STREAM_CONFIG_USART_IFACE(usart4_usb, USB_IFACE_USART4_STREAM,
+			      USB_STR_USART4_STREAM_NAME, USB_EP_USART4_STREAM,
+			      USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE,
+			      usb_to_usart4, usart4_to_usb, usart4)
 
 /******************************************************************************
  * Check parity setting on usarts.
  */
-static int command_uart_parity(int argc, char **argv)
+static int command_uart_parity(int argc, const char **argv)
 {
 	int parity = 0, newparity;
 	struct usart_config const *usart;
@@ -200,14 +168,13 @@ static int command_uart_parity(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(parity, command_uart_parity,
-			"usart[2|3|4] [0|1|2]",
+DECLARE_CONSOLE_COMMAND(parity, command_uart_parity, "usart[2|3|4] [0|1|2]",
 			"Set parity on uart");
 
 /******************************************************************************
  * Set baud rate setting on usarts.
  */
-static int command_uart_baud(int argc, char **argv)
+static int command_uart_baud(int argc, const char **argv)
 {
 	int baud = 0;
 	struct usart_config const *usart;
@@ -233,14 +200,13 @@ static int command_uart_baud(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(baud, command_uart_baud,
-			"usart[2|3|4] rate",
+DECLARE_CONSOLE_COMMAND(baud, command_uart_baud, "usart[2|3|4] rate",
 			"Set baud rate on uart");
 
 /******************************************************************************
  * Hold the usart pins low while disabling it, or return it to normal.
  */
-static int command_hold_usart_low(int argc, char **argv)
+static int command_hold_usart_low(int argc, const char **argv)
 {
 	/* Each bit represents if that port rx is being held low */
 	static int usart_status;
@@ -297,7 +263,7 @@ static int command_hold_usart_low(int argc, char **argv)
 
 	/* Print status for get and set case. */
 	ccprintf("USART status: %s\n",
-			usart_status & usart_mask ? "held low" : "normal");
+		 usart_status & usart_mask ? "held low" : "normal");
 
 	return EC_SUCCESS;
 }
@@ -309,17 +275,18 @@ DECLARE_CONSOLE_COMMAND(hold_usart_low, command_hold_usart_low,
  * Define the strings used in our USB descriptors.
  */
 const void *const usb_strings[] = {
-	[USB_STR_DESC]         = usb_string_desc,
-	[USB_STR_VENDOR]       = USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]      = USB_STRING_DESC("Servo Micro"),
-	[USB_STR_SERIALNO]     = 0,
-	[USB_STR_VERSION]      = USB_STRING_DESC(CROS_EC_VERSION32),
-	[USB_STR_I2C_NAME]     = USB_STRING_DESC("I2C"),
-	[USB_STR_USART4_STREAM_NAME]  = USB_STRING_DESC("UART3"),
+	[USB_STR_DESC] = usb_string_desc,
+	[USB_STR_VENDOR] = USB_STRING_DESC("Google LLC"),
+	[USB_STR_PRODUCT] = USB_STRING_DESC("Servo Micro"),
+	[USB_STR_SERIALNO] = 0,
+	[USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32),
+	[USB_STR_SPI_NAME] = USB_STRING_DESC("SPI"),
+	[USB_STR_I2C_NAME] = USB_STRING_DESC("I2C"),
+	[USB_STR_USART4_STREAM_NAME] = USB_STRING_DESC("UART3"),
 	[USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Servo Shell"),
-	[USB_STR_USART3_STREAM_NAME]  = USB_STRING_DESC("CPU"),
-	[USB_STR_USART2_STREAM_NAME]  = USB_STRING_DESC("EC"),
-	[USB_STR_UPDATE_NAME]  = USB_STRING_DESC("Firmware update"),
+	[USB_STR_USART3_STREAM_NAME] = USB_STRING_DESC("CPU"),
+	[USB_STR_USART2_STREAM_NAME] = USB_STRING_DESC("EC"),
+	[USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"),
 };
 
 BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
@@ -331,11 +298,11 @@ BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
 
 /* SPI devices */
 const struct spi_device_t spi_devices[] = {
-	{ CONFIG_SPI_FLASH_PORT, 1, GPIO_SPI_CS},
+	{ CONFIG_SPI_FLASH_PORT, 1, GPIO_SPI_CS, USB_SPI_ENABLED },
 };
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
-void usb_spi_board_enable(struct usb_spi_config const *config)
+void usb_spi_board_enable(void)
 {
 	/* Configure SPI GPIOs */
 	gpio_config_module(MODULE_SPI_FLASH, 1);
@@ -350,12 +317,12 @@ void usb_spi_board_enable(struct usb_spi_config const *config)
 	STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2;
 	STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
 
-	spi_enable(CONFIG_SPI_FLASH_PORT, 1);
+	spi_enable(&spi_devices[0], 1);
 }
 
-void usb_spi_board_disable(struct usb_spi_config const *config)
+void usb_spi_board_disable(void)
 {
-	spi_enable(CONFIG_SPI_FLASH_PORT, 0);
+	spi_enable(&spi_devices[0], 0);
 
 	/* Disable clocks to SPI2 module */
 	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
@@ -364,20 +331,24 @@ void usb_spi_board_disable(struct usb_spi_config const *config)
 	gpio_config_module(MODULE_SPI_FLASH, 0);
 }
 
-USB_SPI_CONFIG(usb_spi, USB_IFACE_SPI, USB_EP_SPI, 0);
-
 /******************************************************************************
  * Support I2C bridging over USB.
  */
 
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{"master", I2C_PORT_MASTER, 100,
-		GPIO_MASTER_I2C_SCL, GPIO_MASTER_I2C_SDA},
+	{ .name = "master",
+	  .port = I2C_PORT_MASTER,
+	  .kbps = 100,
+	  .scl = GPIO_MASTER_I2C_SCL,
+	  .sda = GPIO_MASTER_I2C_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
-int usb_i2c_board_is_enabled(void) { return 1; }
+int usb_i2c_board_is_enabled(void)
+{
+	return 1;
+}
 
 /* Configure ITE flash support module */
 const struct ite_dfu_config_t ite_dfu_config = {
@@ -407,8 +378,8 @@ static void board_init(void)
 	/* Enable GPIO expander. */
 	gpio_set_level(GPIO_TCA6416_RESET_L, 1);
 
-	/* Structured enpoints */
-	usb_spi_enable(&usb_spi, 1);
+	/* Structured endpoints */
+	usb_spi_enable(1);
 
 	/* Enable UARTs by default. */
 	gpio_set_level(GPIO_UART1_EN_L, 0);
@@ -445,6 +416,6 @@ static void board_jump(void)
 	usart_shutdown(&usart4);
 
 	/* Shutdown other hardware modules and let RW reinitialize them */
-	usb_spi_enable(&usb_spi, 0);
+	usb_spi_enable(0);
 }
 DECLARE_HOOK(HOOK_SYSJUMP, board_jump, HOOK_PRIO_DEFAULT);
diff --git a/board/servo_micro/board.h b/board/servo_micro/board.h
index 50e6910811..109a40409d 100644
--- a/board/servo_micro/board.h
+++ b/board/servo_micro/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -30,12 +30,12 @@
 #undef CONFIG_UART_RX_DMA
 
 /* Optional features */
-#define CONFIG_STM_HWTIMER32
 #define CONFIG_HW_CRC
 #define CONFIG_PVD
-/* See 'Programmable voltage detector characteristics' in the STM32F072x8 Datasheet.
-   PVD Threshold 1 corresponds to a falling voltage threshold of min:2.09V, max:2.27V. */
-#define PVD_THRESHOLD     (1)
+/* See 'Programmable voltage detector characteristics' in the STM32F072x8
+   Datasheet. PVD Threshold 1 corresponds to a falling voltage threshold of
+   min:2.09V, max:2.27V. */
+#define PVD_THRESHOLD (1)
 
 /* USB Configuration */
 #define CONFIG_USB
@@ -50,33 +50,33 @@
 #define DEFAULT_SERIALNO "Uninitialized"
 
 /* USB interface indexes (use define rather than enum to expand them) */
-#define USB_IFACE_USART4_STREAM	0
-#define USB_IFACE_UPDATE	1
-#define USB_IFACE_SPI		2
-#define USB_IFACE_CONSOLE	3
-#define USB_IFACE_I2C		4
-#define USB_IFACE_USART3_STREAM	5
-#define USB_IFACE_USART2_STREAM	6
-#define USB_IFACE_COUNT		7
+#define USB_IFACE_USART4_STREAM 0
+#define USB_IFACE_UPDATE 1
+#define USB_IFACE_SPI 2
+#define USB_IFACE_CONSOLE 3
+#define USB_IFACE_I2C 4
+#define USB_IFACE_USART3_STREAM 5
+#define USB_IFACE_USART2_STREAM 6
+#define USB_IFACE_COUNT 7
 
 /* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL		0
-#define USB_EP_USART4_STREAM	1
-#define USB_EP_UPDATE		2
-#define USB_EP_SPI		3
-#define USB_EP_CONSOLE		4
-#define USB_EP_I2C		5
-#define USB_EP_USART3_STREAM	6
-#define USB_EP_USART2_STREAM	7
-#define USB_EP_COUNT		8
+#define USB_EP_CONTROL 0
+#define USB_EP_USART4_STREAM 1
+#define USB_EP_UPDATE 2
+#define USB_EP_SPI 3
+#define USB_EP_CONSOLE 4
+#define USB_EP_I2C 5
+#define USB_EP_USART3_STREAM 6
+#define USB_EP_USART2_STREAM 7
+#define USB_EP_COUNT 8
 
 /* Enable console recasting of GPIO type. */
 #define CONFIG_CMD_GPIO_EXTENDED
 
 /* Enable control of SPI over USB */
 #define CONFIG_USB_SPI
-#define CONFIG_SPI_MASTER
-#define CONFIG_SPI_FLASH_PORT    0  /* First SPI master port */
+#define CONFIG_SPI_CONTROLLER
+#define CONFIG_SPI_FLASH_PORT 0 /* First SPI controller port */
 
 /* This is not actually an EC so disable some features. */
 #undef CONFIG_WATCHDOG_HELP
@@ -85,16 +85,16 @@
 /* Enable control of I2C over USB */
 #define CONFIG_USB_I2C
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_CONTROLLER
 #define I2C_PORT_MASTER 0
 
 /* See i2c_ite_flash_support.c for more information about these values */
 #define CONFIG_ITE_FLASH_SUPPORT
-#define CONFIG_I2C_XFER_LARGE_READ
+#define CONFIG_I2C_XFER_LARGE_TRANSFER
 #undef CONFIG_USB_I2C_MAX_WRITE_COUNT
 #undef CONFIG_USB_I2C_MAX_READ_COUNT
-#define CONFIG_USB_I2C_MAX_WRITE_COUNT ((1<<9) - 4)
-#define CONFIG_USB_I2C_MAX_READ_COUNT ((1<<9) - 6)
+#define CONFIG_USB_I2C_MAX_WRITE_COUNT ((1 << 9) - 4)
+#define CONFIG_USB_I2C_MAX_READ_COUNT ((1 << 9) - 6)
 
 /*
  * Allow dangerous commands all the time, since we don't have a write protect
@@ -120,6 +120,7 @@ enum usb_strings {
 	USB_STR_PRODUCT,
 	USB_STR_SERIALNO,
 	USB_STR_VERSION,
+	USB_STR_SPI_NAME,
 	USB_STR_I2C_NAME,
 	USB_STR_USART4_STREAM_NAME,
 	USB_STR_CONSOLE_NAME,
diff --git a/board/servo_micro/build.mk b/board/servo_micro/build.mk
index 0e069a31ad..7ac70706fc 100644
--- a/board/servo_micro/build.mk
+++ b/board/servo_micro/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/servo_micro/ccd.md b/board/servo_micro/ccd.md
index acb82adb94..2398e1dd46 100644
--- a/board/servo_micro/ccd.md
+++ b/board/servo_micro/ccd.md
@@ -1,35 +1,36 @@
 <!--
- Copyright 2018 The Chromium OS Authors. All rights reserved.
+ Copyright 2018 The ChromiumOS Authors
  Use of this source code is governed by a BSD-style license that can be
  found in the LICENSE file.
 -->
 
 # Case-Closed Debug in Chromebooks and Servo Micro
 
-The Servo debug/test-automation connector has been required on all
-chromebooks. It has proved essential to performing the required testing to meet
-the six week OS release cycle, for bringing up new systems and qualifying new
-components. In newer form-factors it is becoming hard to fit the Servo connector
-(and related flex) and in some designs the thermal solution stops working when
-the connector is used. The secure Case-Closed Debugging solution provides the
-same capabilities and can take advantage of the Debug Mode detection available
-on the USB-C connector. This application note gives an overview of Case-Closed
-Debug (CCD) but does not address the related security issues.
-
+The Servo debug/test-automation connector has been required on all chromebooks.
+It has proved essential to performing the required testing to meet the six week
+OS release cycle, for bringing up new systems and qualifying new components. In
+newer form-factors it is becoming hard to fit the Servo connector (and related
+flex) and in some designs the thermal solution stops working when the connector
+is used. The secure Case-Closed Debugging solution provides the same
+capabilities and can take advantage of the Debug Mode detection available on the
+USB-C connector. This application note gives an overview of Case-Closed Debug
+(CCD) but does not address the related security issues.
 
 ## Introduction to Case-Closed Debug
 
-Case-Closed Debug provides the same set of features as are available on the Servo connector:
+Case-Closed Debug provides the same set of features as are available on the
+Servo connector:
 
 *   Access to console UART connections to AP, EC and on some systems a third MCU
 *   Ability to reprogram firmware/BIOS SPI flash used by the AP
 *   Ability to reprogram SPI flash used by the EC or use a firmware update mode
     to reprogram the internal flash on the EC (using UART or I2C)
 *   GPIOs for holding the EC (and thus entire system) or AP in reset
-*   Act as master on a debug I2C that is primarily used for power
-    measurements. This bus normally contains INA voltage/current monitors and
-    temperature monitors that will not be populated on final MP systems.
-*   JTAG/SWD could be provided but has not been implemented on any existing system.
+*   Act as master on a debug I2C that is primarily used for power measurements.
+    This bus normally contains INA voltage/current monitors and temperature
+    monitors that will not be populated on final MP systems.
+*   JTAG/SWD could be provided but has not been implemented on any existing
+    system.
 
 When the Servo connector is used these interfaces are presented on well defined
 pins of the board-to-board connector and a flex is used to attach to the
@@ -43,7 +44,6 @@ be used for the debug USB while the main link on the connector continues to be
 available. (The SBU pins are also used by some Alternate Modes, so the connector
 cannot be used for video out at the same time as debugging.)
 
-
 ## Servo Micro: Using CCD with existing boards
 
 The Servo Micro implements the CCD functions in a way that can connect to
@@ -60,8 +60,8 @@ original Servo connector, but on some designs) can be connected to either the
 JTAG pins or the SPI pins. It is capable of providing the SPI flash supply
 voltages.
 
-The schematics for Servo Micro are available [as a
-pdf](servo_micro_sch_20180404.pdf).
+The schematics for Servo Micro are available
+[as a pdf](servo_micro_sch_20180404.pdf).
 
 Servo Micro has a USB micro-B connector and acts as a USB device.
 
@@ -75,8 +75,8 @@ UART connection on CN2.
 
 Schematic sheet 3 shows the I2C GPIO expander and the buffers for JTAG/SWD. The
 buffers adapt to the voltage needed on the DUT that is provided on
-`PPDUT_JTAG_VREF`. In the SWD case the TDI becomes the bidirectional SWDIO but the
-STM32 continues to use a discrete input and output pin. The DUT signal is
+`PPDUT_JTAG_VREF`. In the SWD case the TDI becomes the bidirectional SWDIO but
+the STM32 continues to use a discrete input and output pin. The DUT signal is
 received through U55 and a selection made with U1 to determine if to forward TDO
 from the DUT or the TDI/SWDIO. Because of the shared pins on the STM32 the JTAG
 interface can alternatively be used to connect UART3 to the DUT for a few
@@ -103,26 +103,23 @@ load switches are carefully selected to have reverse blocking (protecting
 against a DUT providing a voltage or both being enabled).
 
 The code for the STM32 in Servo Micro is open source as the
-[`servo_micro`](../../board/servo_micro)
-board in the [Chromium EC
-codebase](https://chromium.googlesource.com/chromiumos/platform/ec/). Essentially
-it is a USB device that provides the standard control endpoint and 7 function
-endpoints defined in
-[`board.h`](board.h).
+[`servo_micro`](../../board/servo_micro) board in the
+[Chromium EC codebase](https://chromium.googlesource.com/chromiumos/platform/ec/).
+Essentially it is a USB device that provides the standard control endpoint and 7
+function endpoints defined in [`board.h`](board.h).
 
 <!-- does not work in emacs/markdown preview but should in gitlies -->
 
-``` c
-    #define USB_EP_USART4_STREAM	1
-    #define USB_EP_UPDATE			2
-    #define USB_EP_SPI			3
-    #define USB_EP_CONSOLE		4
-    #define USB_EP_I2C			5
-    #define USB_EP_USART3_STREAM	6
-    #define USB_EP_USART2_STREAM	7
+```c
+#define USB_EP_USART4_STREAM    1
+#define USB_EP_UPDATE           2
+#define USB_EP_SPI              3
+#define USB_EP_CONSOLE          4
+#define USB_EP_I2C              5
+#define USB_EP_USART3_STREAM    6
+#define USB_EP_USART2_STREAM    7
 ```
 
-
 The USART endpoints use the simple `GOOGLE_SERIAL` vendor class to connect the
 STM32 UARTs. The CONSOLE endpoint also uses `GOOGLE_STREAM` to connect to the
 console of the code running on the STM32. `GOOGLE_STREAM` provides simple byte
@@ -131,32 +128,27 @@ standard Linux `drivers/usb/serial/usb-serial-simple.c`
 
 The SPI endpoint is described in
 [`chip/stm32/usb_spi.h`](../../chip/stm32/usb_spi.h) and provides a simple
-connection to the SPI port. The host support is provided as a [driver in
-flashrom](https://chromium.googlesource.com/chromiumos/third_party/flashrom/+/master/raiden_debug_spi.c).
+connection to the SPI port. The host support is provided as a
+[driver in flashrom](https://chromium.googlesource.com/chromiumos/third_party/flashrom/+/HEAD/raiden_debug_spi.c).
 
 The I2C endpoint is described in [`include/usb_i2c.h`](../../include/usb_i2c.h)
 and provides a simple connection to the I2C bus. The host support is provided in
-the [hdctools servo
-support](https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/master/servo/stm32i2c.py).
+the
+[hdctools servo support](https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/HEAD/servo/stm32i2c.py).
 
 The GPIO endpoint is cryptically described in
-[`chip/stm32/usb_gpio.h`](../../chip/stm32/usb_gpio.h) and provides simple access
-to set/clear and read the GPIO pins. The host support is provided in the
-[hdctools servo
-support](https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/master/servo/stm32gpio.py).
+[`chip/stm32/usb_gpio.h`](../../chip/stm32/usb_gpio.h) and provides simple
+access to set/clear and read the GPIO pins. The host support is provided in the
+[hdctools servo support](https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/HEAD/servo/stm32gpio.py).
 
 The UPDATE endpoint is not part of CCD. It provides a method for updating the
-STM32 without needing the special boot modes. This uses the [Chromium EC update
-over
-USB](../../docs/usb_updater.md)
-method. The STM32 runs the code in
-[`common/usb_update.c`](../../common/usb_update.c).
-The host side code is in
-[`extra/usb_updater/usb_updater2.c`](../../extra/usb_updater/usb_updater2.c)
-and the
-[`extra/usb_updater`](../../extra/usb_updater/)
-directory contains additional scripts.
-
+STM32 without needing the special boot modes. This uses the
+[Chromium EC update over USB](../../docs/usb_updater.md) method. The STM32 runs
+the code in [`common/usb_update.c`](../../common/usb_update.c). The host side
+code is in
+[`extra/usb_updater/usb_updater2.c`](../../extra/usb_updater/usb_updater2.c) and
+the [`extra/usb_updater`](../../extra/usb_updater/) directory contains
+additional scripts.
 
 ## Using CCD on new designs
 
diff --git a/board/servo_micro/ec.tasklist b/board/servo_micro/ec.tasklist
index c1fb169118..c45a1e89a7 100644
--- a/board/servo_micro/ec.tasklist
+++ b/board/servo_micro/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/servo_micro/gpio.inc b/board/servo_micro/gpio.inc
index 10e411c5f2..ad1739f1e6 100644
--- a/board/servo_micro/gpio.inc
+++ b/board/servo_micro/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/servo_v4/OWNERS b/board/servo_v4/OWNERS
new file mode 100644
index 0000000000..150eefc951
--- /dev/null
+++ b/board/servo_v4/OWNERS
@@ -0,0 +1,3 @@
+bnemec@google.com
+matthewb@chromium.org
+waihong@google.com
diff --git a/board/servo_v4/board.c b/board/servo_v4/board.c
index fc6735e19c..6cb6cf5df9 100644
--- a/board/servo_v4/board.c
+++ b/board/servo_v4/board.c
@@ -1,11 +1,10 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 /* Servo V4 configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "common.h"
 #include "console.h"
 #include "ec_version.h"
@@ -24,18 +23,18 @@
 #include "timer.h"
 #include "update_fw.h"
 #include "usart-stm32f0.h"
-#include "usart_tx_dma.h"
 #include "usart_rx_dma.h"
+#include "usart_tx_dma.h"
+#include "usb-stream.h"
 #include "usb_gpio.h"
 #include "usb_i2c.h"
 #include "usb_pd.h"
 #include "usb_pd_config.h"
 #include "usb_spi.h"
-#include "usb-stream.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
 /******************************************************************************
  * GPIO interrupt handlers.
@@ -78,7 +77,7 @@ static volatile int hpd_prev_level;
 
 void hpd_irq_deferred(void)
 {
-	int dp_mode = pd_alt_mode(1, TCPC_TX_SOP, USB_SID_DISPLAYPORT);
+	int dp_mode = pd_alt_mode(1, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT);
 
 	if (dp_mode) {
 		pd_send_hpd(DUT, hpd_irq);
@@ -90,7 +89,7 @@ DECLARE_DEFERRED(hpd_irq_deferred);
 void hpd_lvl_deferred(void)
 {
 	int level = gpio_get_level(GPIO_DP_HPD);
-	int dp_mode = pd_alt_mode(1, TCPC_TX_SOP, USB_SID_DISPLAYPORT);
+	int dp_mode = pd_alt_mode(1, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT);
 
 	if (level != hpd_prev_level) {
 		/* It's a glitch while in deferred or canceled action */
@@ -132,6 +131,7 @@ void hpd_evt(enum gpio_signal signal)
 	hpd_prev_level = level;
 }
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /******************************************************************************
@@ -176,23 +176,22 @@ void board_config_pre_init(void)
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* USB PD CC lines sensing. Converted to mV (3300mV/4096). */
-	[ADC_CHG_CC1_PD] = {"CHG_CC1_PD", 3300, 4096, 0, STM32_AIN(2)},
-	[ADC_CHG_CC2_PD] = {"CHG_CC2_PD", 3300, 4096, 0, STM32_AIN(4)},
-	[ADC_DUT_CC1_PD] = {"DUT_CC1_PD", 3300, 4096, 0, STM32_AIN(0)},
-	[ADC_DUT_CC2_PD] = {"DUT_CC2_PD", 3300, 4096, 0, STM32_AIN(5)},
-	[ADC_SBU1_DET] = {"SBU1_DET", 3300, 4096, 0, STM32_AIN(3)},
-	[ADC_SBU2_DET] = {"SBU2_DET", 3300, 4096, 0, STM32_AIN(7)},
-	[ADC_SUB_C_REF] = {"SUB_C_REF", 3300, 4096, 0, STM32_AIN(1)},
+	[ADC_CHG_CC1_PD] = { "CHG_CC1_PD", 3300, 4096, 0, STM32_AIN(2) },
+	[ADC_CHG_CC2_PD] = { "CHG_CC2_PD", 3300, 4096, 0, STM32_AIN(4) },
+	[ADC_DUT_CC1_PD] = { "DUT_CC1_PD", 3300, 4096, 0, STM32_AIN(0) },
+	[ADC_DUT_CC2_PD] = { "DUT_CC2_PD", 3300, 4096, 0, STM32_AIN(5) },
+	[ADC_SBU1_DET] = { "SBU1_DET", 3300, 4096, 0, STM32_AIN(3) },
+	[ADC_SBU2_DET] = { "SBU2_DET", 3300, 4096, 0, STM32_AIN(7) },
+	[ADC_SUB_C_REF] = { "SUB_C_REF", 3300, 4096, 0, STM32_AIN(1) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
-
 /******************************************************************************
  * Forward UARTs as a USB serial interface.
  */
 
-#define USB_STREAM_RX_SIZE	16
-#define USB_STREAM_TX_SIZE	16
+#define USB_STREAM_RX_SIZE 16
+#define USB_STREAM_TX_SIZE 16
 
 /******************************************************************************
  * Forward USART3 as a simple USB serial interface.
@@ -201,29 +200,19 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 static struct usart_config const usart3;
 struct usb_stream_config const usart3_usb;
 
-static struct queue const usart3_to_usb = QUEUE_DIRECT(64, uint8_t,
-	usart3.producer, usart3_usb.consumer);
-static struct queue const usb_to_usart3 = QUEUE_DIRECT(64, uint8_t,
-	usart3_usb.producer, usart3.consumer);
+static struct queue const usart3_to_usb =
+	QUEUE_DIRECT(64, uint8_t, usart3.producer, usart3_usb.consumer);
+static struct queue const usb_to_usart3 =
+	QUEUE_DIRECT(64, uint8_t, usart3_usb.producer, usart3.consumer);
 
 static struct usart_config const usart3 =
-	USART_CONFIG(usart3_hw,
-		usart_rx_interrupt,
-		usart_tx_interrupt,
-		115200,
-		0,
-		usart3_to_usb,
-		usb_to_usart3);
-
-USB_STREAM_CONFIG(usart3_usb,
-	USB_IFACE_USART3_STREAM,
-	USB_STR_USART3_STREAM_NAME,
-	USB_EP_USART3_STREAM,
-	USB_STREAM_RX_SIZE,
-	USB_STREAM_TX_SIZE,
-	usb_to_usart3,
-	usart3_to_usb)
+	USART_CONFIG(usart3_hw, usart_rx_interrupt, usart_tx_interrupt, 115200,
+		     0, usart3_to_usb, usb_to_usart3);
 
+USB_STREAM_CONFIG(usart3_usb, USB_IFACE_USART3_STREAM,
+		  USB_STR_USART3_STREAM_NAME, USB_EP_USART3_STREAM,
+		  USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE, usb_to_usart3,
+		  usart3_to_usb)
 
 /******************************************************************************
  * Forward USART4 as a simple USB serial interface.
@@ -232,63 +221,73 @@ USB_STREAM_CONFIG(usart3_usb,
 static struct usart_config const usart4;
 struct usb_stream_config const usart4_usb;
 
-static struct queue const usart4_to_usb = QUEUE_DIRECT(64, uint8_t,
-	usart4.producer, usart4_usb.consumer);
-static struct queue const usb_to_usart4 = QUEUE_DIRECT(64, uint8_t,
-	usart4_usb.producer, usart4.consumer);
+static struct queue const usart4_to_usb =
+	QUEUE_DIRECT(64, uint8_t, usart4.producer, usart4_usb.consumer);
+static struct queue const usb_to_usart4 =
+	QUEUE_DIRECT(64, uint8_t, usart4_usb.producer, usart4.consumer);
 
 static struct usart_config const usart4 =
-	USART_CONFIG(usart4_hw,
-		usart_rx_interrupt,
-		usart_tx_interrupt,
-		9600,
-		0,
-		usart4_to_usb,
-		usb_to_usart4);
-
-USB_STREAM_CONFIG(usart4_usb,
-	USB_IFACE_USART4_STREAM,
-	USB_STR_USART4_STREAM_NAME,
-	USB_EP_USART4_STREAM,
-	USB_STREAM_RX_SIZE,
-	USB_STREAM_TX_SIZE,
-	usb_to_usart4,
-	usart4_to_usb)
+	USART_CONFIG(usart4_hw, usart_rx_interrupt, usart_tx_interrupt, 9600, 0,
+		     usart4_to_usb, usb_to_usart4);
+
+USB_STREAM_CONFIG(usart4_usb, USB_IFACE_USART4_STREAM,
+		  USB_STR_USART4_STREAM_NAME, USB_EP_USART4_STREAM,
+		  USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE, usb_to_usart4,
+		  usart4_to_usb)
 
+/*
+ * Define usb interface descriptor for the `EMPTY` usb interface, to satisfy
+ * UEFI and kernel requirements (see b/183857501).
+ */
+const struct usb_interface_descriptor USB_IFACE_DESC(USB_IFACE_EMPTY) = {
+	.bLength = USB_DT_INTERFACE_SIZE,
+	.bDescriptorType = USB_DT_INTERFACE,
+	.bInterfaceNumber = USB_IFACE_EMPTY,
+	.bAlternateSetting = 0,
+	.bNumEndpoints = 0,
+	.bInterfaceClass = USB_CLASS_VENDOR_SPEC,
+	.bInterfaceSubClass = 0,
+	.bInterfaceProtocol = 0,
+	.iInterface = 0,
+};
 
 /******************************************************************************
  * Define the strings used in our USB descriptors.
  */
 
 const void *const usb_strings[] = {
-	[USB_STR_DESC]         = usb_string_desc,
-	[USB_STR_VENDOR]       = USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]      = USB_STRING_DESC("Servo V4"),
-	[USB_STR_SERIALNO]     = USB_STRING_DESC("1234-a"),
-	[USB_STR_VERSION]      = USB_STRING_DESC(CROS_EC_VERSION32),
-	[USB_STR_I2C_NAME]     = USB_STRING_DESC("I2C"),
+	[USB_STR_DESC] = usb_string_desc,
+	[USB_STR_VENDOR] = USB_STRING_DESC("Google LLC"),
+	[USB_STR_PRODUCT] = USB_STRING_DESC("Servo V4"),
+	[USB_STR_SERIALNO] = USB_STRING_DESC("1234-a"),
+	[USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32),
+	[USB_STR_I2C_NAME] = USB_STRING_DESC("I2C"),
 	[USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Servo EC Shell"),
-	[USB_STR_USART3_STREAM_NAME]  = USB_STRING_DESC("DUT UART"),
-	[USB_STR_USART4_STREAM_NAME]  = USB_STRING_DESC("Atmega UART"),
-	[USB_STR_UPDATE_NAME]  = USB_STRING_DESC("Firmware update"),
+	[USB_STR_USART3_STREAM_NAME] = USB_STRING_DESC("DUT UART"),
+	[USB_STR_USART4_STREAM_NAME] = USB_STRING_DESC("Atmega UART"),
+	[USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"),
 };
 
 BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
 
-
-
 /******************************************************************************
  * Support I2C bridging over USB.
  */
 
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{"master", I2C_PORT_MASTER, 100,
-		GPIO_MASTER_I2C_SCL, GPIO_MASTER_I2C_SDA},
+	{ .name = "master",
+	  .port = I2C_PORT_MASTER,
+	  .kbps = 100,
+	  .scl = GPIO_MASTER_I2C_SCL,
+	  .sda = GPIO_MASTER_I2C_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
-int usb_i2c_board_is_enabled(void) { return 1; }
+int usb_i2c_board_is_enabled(void)
+{
+	return 1;
+}
 
 /******************************************************************************
  * Initialize board.
@@ -297,14 +296,13 @@ int usb_i2c_board_is_enabled(void) { return 1; }
 /*
  * Support tca6416 I2C ioexpander.
  */
-#define GPIOX_I2C_ADDR_FLAGS	0x20
-#define GPIOX_IN_PORT_A		0x0
-#define GPIOX_IN_PORT_B		0x1
-#define GPIOX_OUT_PORT_A	0x2
-#define GPIOX_OUT_PORT_B	0x3
-#define GPIOX_DIR_PORT_A	0x6
-#define GPIOX_DIR_PORT_B	0x7
-
+#define GPIOX_I2C_ADDR_FLAGS 0x20
+#define GPIOX_IN_PORT_A 0x0
+#define GPIOX_IN_PORT_B 0x1
+#define GPIOX_OUT_PORT_A 0x2
+#define GPIOX_OUT_PORT_B 0x3
+#define GPIOX_DIR_PORT_A 0x6
+#define GPIOX_DIR_PORT_B 0x7
 
 /* Write a GPIO output on the tca6416 I2C ioexpander. */
 static void write_ioexpander(int bank, int gpio, int val)
@@ -374,15 +372,15 @@ static void init_ioexpander(void)
  * Max observed USB low across sampled systems: 666mV
  * Min observed USB high across sampled systems: 3026mV
  */
-#define GND_MAX_MV	700
-#define USB_HIGH_MV	2500
-#define SBU_DIRECT	0
-#define SBU_FLIP	1
+#define GND_MAX_MV 700
+#define USB_HIGH_MV 2500
+#define SBU_DIRECT 0
+#define SBU_FLIP 1
 
-#define MODE_SBU_DISCONNECT	0
-#define MODE_SBU_CONNECT	1
-#define MODE_SBU_FLIP		2
-#define MODE_SBU_OTHER		3
+#define MODE_SBU_DISCONNECT 0
+#define MODE_SBU_CONNECT 1
+#define MODE_SBU_FLIP 2
+#define MODE_SBU_OTHER 3
 
 static void ccd_measure_sbu(void);
 DECLARE_DEFERRED(ccd_measure_sbu);
@@ -425,12 +423,12 @@ static void ccd_measure_sbu(void)
 		} else {
 			count++;
 		}
-	/*
-	 * If SuzyQ is enabled, we'll poll for a persistent no-signal for
-	 * 500ms. Since USB is differential, we should never see GND/GND
-	 * while the device is connected.
-	 * If disconnected, electrically remove SuzyQ.
-	 */
+		/*
+		 * If SuzyQ is enabled, we'll poll for a persistent no-signal
+		 * for 500ms. Since USB is differential, we should never see
+		 * GND/GND while the device is connected. If disconnected,
+		 * electrically remove SuzyQ.
+		 */
 	} else if ((mux_en) && (sbu1 < GND_MAX_MV) && (sbu2 < GND_MAX_MV)) {
 		/* Check for SBU disconnect if connected. */
 		if (last != MODE_SBU_DISCONNECT) {
diff --git a/board/servo_v4/board.h b/board/servo_v4/board.h
index 8654ad901e..1c7d90eab4 100644
--- a/board/servo_v4/board.h
+++ b/board/servo_v4/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,6 +10,12 @@
 
 #define CONFIG_LTO
 
+/* Free up flash space */
+#ifdef SECTION_IS_RO
+#define CONFIG_DEBUG_ASSERT_BRIEF
+#undef CONFIG_USB_PD_TCPMV1_DEBUG
+#endif
+
 /*
  * Board Versions:
  * Versions are designated by the PCB color and consist of red, blue, and
@@ -17,7 +23,6 @@
  * id from previous versions.
  */
 #define BOARD_VERSION_BLACK 3
-#define CONFIG_BOARD_VERSION_CUSTOM
 
 /* 48 MHz SYSCLK clock frequency */
 #define CPU_CLOCK 48000000
@@ -30,12 +35,12 @@
 #define CONFIG_CMD_USART_INFO
 
 /* Optional features */
-#define CONFIG_STM_HWTIMER32
 #define CONFIG_HW_CRC
 #define CONFIG_PVD
-/* See 'Programmable voltage detector characteristics' in the STM32F072x8 Datasheet.
-   PVD Threshold 1 corresponds to a falling voltage threshold of min:2.09V, max:2.27V. */
-#define PVD_THRESHOLD     (1)
+/* See 'Programmable voltage detector characteristics' in the STM32F072x8
+   Datasheet. PVD Threshold 1 corresponds to a falling voltage threshold of
+   min:2.09V, max:2.27V. */
+#define PVD_THRESHOLD (1)
 
 /* USB Configuration */
 #define CONFIG_USB
@@ -55,23 +60,23 @@
 #define DEFAULT_MAC_ADDR "Uninitialized"
 
 /* USB interface indexes (use define rather than enum to expand them) */
-#define USB_IFACE_CONSOLE	0
-#define USB_IFACE_EMPTY		1
-#define USB_IFACE_I2C		2
-#define USB_IFACE_USART3_STREAM	3
-#define USB_IFACE_USART4_STREAM	4
-#define USB_IFACE_UPDATE	5
-#define USB_IFACE_COUNT		6
+#define USB_IFACE_CONSOLE 0
+#define USB_IFACE_EMPTY 1
+#define USB_IFACE_I2C 2
+#define USB_IFACE_USART3_STREAM 3
+#define USB_IFACE_USART4_STREAM 4
+#define USB_IFACE_UPDATE 5
+#define USB_IFACE_COUNT 6
 
 /* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL		0
-#define USB_EP_CONSOLE		1
-#define USB_EP_EMPTY		2
-#define USB_EP_I2C		3
-#define USB_EP_USART3_STREAM	4
-#define USB_EP_USART4_STREAM	5
-#define USB_EP_UPDATE		6
-#define USB_EP_COUNT		7
+#define USB_EP_CONTROL 0
+#define USB_EP_CONSOLE 1
+#define USB_EP_EMPTY 2
+#define USB_EP_I2C 3
+#define USB_EP_USART3_STREAM 4
+#define USB_EP_USART4_STREAM 5
+#define USB_EP_UPDATE 6
+#define USB_EP_COUNT 7
 
 /* Enable console recasting of GPIO type. */
 #define CONFIG_CMD_GPIO_EXTENDED
@@ -89,22 +94,28 @@
 #undef CONFIG_CMD_ACCELSPOOF
 #undef CONFIG_CMD_FASTCHARGE
 #undef CONFIG_CMD_FLASHINFO
+#undef CONFIG_CMD_FLASH_WP
 #undef CONFIG_CMD_GETTIME
+#undef CONFIG_CMD_I2C_SCAN
+#undef CONFIG_CMD_I2C_XFER
 #undef CONFIG_CMD_MEM
 #undef CONFIG_CMD_SHMEM
 #undef CONFIG_CMD_SYSLOCK
 #undef CONFIG_CMD_TIMERINFO
 #undef CONFIG_CMD_WAITMS
+#undef CONFIG_CMD_USART_INFO
+#undef CONFIG_CMD_CHARGE_SUPPLIER_INFO
+#define CONFIG_CMD_PD_SRCCAPS_REDUCED_SIZE
 
 /* Enable control of I2C over USB */
 #define CONFIG_USB_I2C
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_CONTROLLER
 #define I2C_PORT_MASTER 1
 
 /* PD features */
 #define CONFIG_ADC
-#undef  CONFIG_ADC_WATCHDOG
+#undef CONFIG_ADC_WATCHDOG
 #define CONFIG_BOARD_PRE_INIT
 /*
  * If task profiling is enabled then the rx falling edge detection interrupts
@@ -113,7 +124,7 @@
 #undef CONFIG_TASK_PROFILING
 
 #define CONFIG_CHARGE_MANAGER
-#undef  CONFIG_CHARGE_MANAGER_SAFE_MODE
+#undef CONFIG_CHARGE_MANAGER_SAFE_MODE
 #define CONFIG_USB_POWER_DELIVERY
 #define CONFIG_USB_PD_TCPMV1
 #define CONFIG_CMD_PD
@@ -128,28 +139,29 @@
 #undef CONFIG_USB_PD_PULLUP
 #define CONFIG_USB_PD_PULLUP TYPEC_RP_USB
 #define CONFIG_USB_PD_VBUS_MEASURE_NOT_PRESENT
+#define CONFIG_USB_PD_ONLY_FIXED_PDOS
 
 /* Don't automatically change roles */
 #undef CONFIG_USB_PD_INITIAL_DRP_STATE
 #define CONFIG_USB_PD_INITIAL_DRP_STATE PD_DRP_FORCE_SINK
 
 /* Variable-current Rp no connect and Ra attach macros */
-#define CC_NC(port, cc, sel)  (pd_tcpc_cc_nc(port, cc, sel))
-#define CC_RA(port, cc, sel)  (pd_tcpc_cc_ra(port, cc, sel))
+#define CC_NC(port, cc, sel) (pd_tcpc_cc_nc(port, cc, sel))
+#define CC_RA(port, cc, sel) (pd_tcpc_cc_ra(port, cc, sel))
 
 /*
  * TODO(crosbug.com/p/60792): The delay values are currently just place holders
  * and the delay will need to be relative to the circuitry that allows VBUS to
  * be supplied to the DUT port from the CHG port.
  */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  50000  /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 50000 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 50000 /* us */
 
 /* Define typical operating power and max power */
 #define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       60000
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_VOLTAGE_MV     20000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 /*
  * Define PDO selection logic for SourceCap.
  * On a 45W PD charger, it might provide PDOs with 15V/3A and 20V/2.25A.
@@ -170,8 +182,7 @@
 
 /* Timer selection */
 #define TIM_CLOCK32 2
-#define TIM_ADC     3
-
+#define TIM_ADC 3
 
 #include "gpio_signal.h"
 
@@ -190,7 +201,6 @@ enum usb_strings {
 	USB_STR_COUNT
 };
 
-
 /* ADC signal */
 enum adc_channel {
 	ADC_CHG_CC1_PD,
diff --git a/board/servo_v4/build.mk b/board/servo_v4/build.mk
index 6336bbfab6..05a0684696 100644
--- a/board/servo_v4/build.mk
+++ b/board/servo_v4/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -14,6 +14,6 @@ CHIP_VARIANT:=stm32f07x
 test-list-y=
 
 board-y=board.o
-board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
+board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o usb_pd_pdo.o
 
 all_deps=$(patsubst ro,,$(def_all_deps))
diff --git a/board/servo_v4/ec.tasklist b/board/servo_v4/ec.tasklist
index 2111c6b761..f51780dce4 100644
--- a/board/servo_v4/ec.tasklist
+++ b/board/servo_v4/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/servo_v4/gpio.inc b/board/servo_v4/gpio.inc
index 76b9a06d0f..afc5789636 100644
--- a/board/servo_v4/gpio.inc
+++ b/board/servo_v4/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/servo_v4/usb_pd_config.h b/board/servo_v4/usb_pd_config.h
index b865057618..d47e8e8868 100644
--- a/board/servo_v4/usb_pd_config.h
+++ b/board/servo_v4/usb_pd_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,8 +6,8 @@
 #include "adc.h"
 #include "chip/stm32/registers.h"
 #include "console.h"
-#include "gpio.h"
 #include "ec_commands.h"
+#include "gpio.h"
 #include "usb_pd_tcpm.h"
 
 /* USB Power delivery board configuration */
@@ -56,22 +56,22 @@
 #define CONFIG_HW_CRC
 
 /* Servo v4 CC configuration */
-#define CC_DETACH	BIT(0)   /* Emulate detach: both CC open */
-#define CC_DISABLE_DTS	BIT(1)   /* Apply resistors to single or both CC? */
-#define CC_ALLOW_SRC	BIT(2)   /* Allow charge through by policy? */
-#define CC_ENABLE_DRP	BIT(3)   /* Enable dual-role port */
-#define CC_SNK_WITH_PD	BIT(4)   /* Force enabling PD comm for sink role */
-#define CC_POLARITY	BIT(5)   /* CC polarity */
+#define CC_DETACH BIT(0) /* Emulate detach: both CC open */
+#define CC_DISABLE_DTS BIT(1) /* Apply resistors to single or both CC? */
+#define CC_ALLOW_SRC BIT(2) /* Allow charge through by policy? */
+#define CC_ENABLE_DRP BIT(3) /* Enable dual-role port */
+#define CC_SNK_WITH_PD BIT(4) /* Force enabling PD comm for sink role */
+#define CC_POLARITY BIT(5) /* CC polarity */
 
 /* Servo v4 DP alt-mode configuration */
-#define ALT_DP_ENABLE		BIT(0)   /* Enable DP alt-mode or not */
-#define ALT_DP_PIN_C		BIT(1)   /* Pin assignment C supported */
-#define ALT_DP_PIN_D		BIT(2)   /* Pin assignment D supported */
-#define ALT_DP_PIN_E		BIT(3)   /* Pin assignment E supported */
-#define ALT_DP_MF_PREF		BIT(4)   /* Multi-Function preferred */
-#define ALT_DP_PLUG		BIT(5)   /* Plug or receptacle */
-#define ALT_DP_OVERRIDE_HPD	BIT(6)   /* Override the HPD signal */
-#define ALT_DP_HPD_LVL		BIT(7)   /* HPD level if overridden */
+#define ALT_DP_ENABLE BIT(0) /* Enable DP alt-mode or not */
+#define ALT_DP_PIN_C BIT(1) /* Pin assignment C supported */
+#define ALT_DP_PIN_D BIT(2) /* Pin assignment D supported */
+#define ALT_DP_PIN_E BIT(3) /* Pin assignment E supported */
+#define ALT_DP_MF_PREF BIT(4) /* Multi-Function preferred */
+#define ALT_DP_PLUG BIT(5) /* Plug or receptacle */
+#define ALT_DP_OVERRIDE_HPD BIT(6) /* Override the HPD signal */
+#define ALT_DP_HPD_LVL BIT(7) /* HPD level if overridden */
 
 /* TX uses SPI1 on PB3-4 for CHG port, SPI2 on PB 13-14 for DUT port */
 #define SPI_REGS(p) ((p) ? STM32_SPI2_REGS : STM32_SPI1_REGS)
@@ -94,14 +94,14 @@ static inline void spi_enable_clock(int port)
 
 #define TIM_TX_CCR_IDX(p) ((p) ? TIM_TX_CCR_DUT : TIM_TX_CCR_CHG)
 #define TIM_RX_CCR_IDX(p) ((p) ? TIM_RX_CCR_DUT : TIM_RX_CCR_CHG)
-#define TIM_CCR_CS  1
+#define TIM_CCR_CS 1
 
 /*
  * EXTI line 21 is connected to the CMP1 output,
  * EXTI line 22 is connected to the CMP2 output,
  * CHG uses CMP2, and DUT uses CMP1.
  */
-#define EXTI_COMP_MASK(p) ((p) ? (1<<21) : BIT(22))
+#define EXTI_COMP_MASK(p) ((p) ? (1 << 21) : BIT(22))
 
 #define IRQ_COMP STM32_IRQ_COMP
 /* triggers packet detection on comparator falling edge */
@@ -193,13 +193,25 @@ static inline void pd_select_polarity(int port, int polarity)
 	if (port == 0) {
 		/* CHG use the right comparator inverted input for COMP2 */
 		STM32_COMP_CSR = (val & ~STM32_COMP_CMP2INSEL_MASK) |
-			(polarity ? STM32_COMP_CMP2INSEL_INM4  /* PA4: C0_CC2 */
-				  : STM32_COMP_CMP2INSEL_INM6);/* PA2: C0_CC1 */
+				 (polarity ?
+					  STM32_COMP_CMP2INSEL_INM4 /* PA4:
+								       C0_CC2
+								     */
+					  :
+					  STM32_COMP_CMP2INSEL_INM6); /* PA2:
+									 C0_CC1
+								       */
 	} else {
 		/* DUT use the right comparator inverted input for COMP1 */
 		STM32_COMP_CSR = (val & ~STM32_COMP_CMP1INSEL_MASK) |
-			(polarity ? STM32_COMP_CMP1INSEL_INM5  /* PA5: C1_CC2 */
-			 : STM32_COMP_CMP1INSEL_INM6);/* PA0: C1_CC1 */
+				 (polarity ?
+					  STM32_COMP_CMP1INSEL_INM5 /* PA5:
+								       C1_CC2
+								     */
+					  :
+					  STM32_COMP_CMP1INSEL_INM6); /* PA0:
+									 C1_CC1
+								       */
 	}
 }
 
@@ -279,10 +291,8 @@ static inline void pd_config_init(int port, uint8_t power_role)
 
 	/* Initialize TX pins and put them in Hi-Z */
 	pd_tx_init();
-
 }
 
 int pd_adc_read(int port, int cc);
 
 #endif /* __CROS_EC_USB_PD_CONFIG_H */
-
diff --git a/board/servo_v4/usb_pd_pdo.c b/board/servo_v4/usb_pd_pdo.c
new file mode 100644
index 0000000000..b2eeee8e52
--- /dev/null
+++ b/board/servo_v4/usb_pd_pdo.c
@@ -0,0 +1,56 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "compile_time_macros.h"
+#include "usb_pd.h"
+#include "usb_pd_config.h"
+#include "usb_pd_pdo.h"
+
+#define CHG_PDO_FIXED_FLAGS (PDO_FIXED_DATA_SWAP)
+
+const uint32_t pd_snk_pdo[] = {
+	PDO_FIXED(5000, 500, CHG_PDO_FIXED_FLAGS),
+	PDO_BATT(4750, 21000, 15000),
+	PDO_VAR(4750, 21000, 3000),
+};
+const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
+
+/*
+ * Dynamic PDO that reflects capabilities present on the CHG port. Allow for
+ * multiple entries so that we can offer greater than 5V charging. The 1st
+ * entry will be fixed 5V, but its current value may change based on the CHG
+ * port vbus info. Subsequent entries are used for when offering vbus greater
+ * than 5V.
+ */
+const uint16_t pd_src_voltages_mv[] = {
+	5000, 9000, 10000, 12000, 15000, 20000,
+};
+uint32_t pd_src_chg_pdo[ARRAY_SIZE(pd_src_voltages_mv)];
+uint8_t chg_pdo_cnt;
+
+int active_charge_port = CHARGE_PORT_NONE;
+struct vbus_prop vbus[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+int charge_port_is_active(void)
+{
+	return active_charge_port == CHG && vbus[CHG].mv > 0;
+}
+
+int charge_manager_get_source_pdo(const uint32_t **src_pdo, const int port)
+{
+	int pdo_cnt = 0;
+
+	/*
+	 * If CHG is providing VBUS, then advertise what's available on the CHG
+	 * port, otherwise we provide no power.
+	 */
+	if (charge_port_is_active()) {
+		*src_pdo = pd_src_chg_pdo;
+		pdo_cnt = chg_pdo_cnt;
+	}
+
+	return pdo_cnt;
+}
diff --git a/board/servo_v4/usb_pd_pdo.h b/board/servo_v4/usb_pd_pdo.h
new file mode 100644
index 0000000000..acab299690
--- /dev/null
+++ b/board/servo_v4/usb_pd_pdo.h
@@ -0,0 +1,30 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_BOARD_SERVO_V4_USB_PD_PDO_H
+#define __CROS_EC_BOARD_SERVO_V4_USB_PD_PDO_H
+
+#include "compile_time_macros.h"
+#include "stdint.h"
+
+extern const uint32_t pd_snk_pdo[3];
+extern const int pd_snk_pdo_cnt;
+
+extern const uint16_t pd_src_voltages_mv[6];
+extern uint32_t pd_src_chg_pdo[ARRAY_SIZE(pd_src_voltages_mv)];
+extern uint8_t chg_pdo_cnt;
+
+extern int active_charge_port;
+
+struct vbus_prop {
+	int mv;
+	int ma;
+};
+extern struct vbus_prop vbus[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+int charge_port_is_active(void);
+int charge_manager_get_source_pdo(const uint32_t **src_pdo, const int port);
+
+#endif /* __CROS_EC_BOARD_SERVO_V4_USB_PD_PDO_H */
diff --git a/board/servo_v4/usb_pd_policy.c b/board/servo_v4/usb_pd_policy.c
index b87130fbc8..68eb59ff97 100644
--- a/board/servo_v4/usb_pd_policy.c
+++ b/board/servo_v4/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,66 +18,67 @@
 #include "registers.h"
 #include "system.h"
 #include "task.h"
-#include "tcpm.h"
+#include "tcpm/tcpm.h"
 #include "timer.h"
-#include "util.h"
 #include "usb_common.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
 #include "usb_pd_config.h"
+#include "usb_pd_pdo.h"
 #include "usb_pd_tcpm.h"
+#include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-#define DUT_PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\
-			     PDO_FIXED_COMM_CAP)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
-#define CHG_PDO_FIXED_FLAGS (PDO_FIXED_DATA_SWAP)
+#define DUT_PDO_FIXED_FLAGS \
+	(PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP | PDO_FIXED_COMM_CAP)
 
-#define VBUS_UNCHANGED(curr, pend, new) (curr == new && pend == new)
+#define VBUS_UNCHANGED(curr, pend, new) (curr == new &&pend == new)
 
 /* Macros to config the PD role */
 #define CONF_SET_CLEAR(c, set, clear) ((c | (set)) & ~(clear))
-#define CONF_SRC(c) CONF_SET_CLEAR(c, \
-				CC_DISABLE_DTS | CC_ALLOW_SRC, \
-				CC_ENABLE_DRP | CC_SNK_WITH_PD)
-#define CONF_SNK(c) CONF_SET_CLEAR(c, \
-				CC_DISABLE_DTS, \
-				CC_ALLOW_SRC | CC_ENABLE_DRP | CC_SNK_WITH_PD)
-#define CONF_PDSNK(c) CONF_SET_CLEAR(c, \
-				CC_DISABLE_DTS | CC_SNK_WITH_PD, \
-				CC_ALLOW_SRC | CC_ENABLE_DRP)
-#define CONF_DRP(c) CONF_SET_CLEAR(c, \
-				CC_DISABLE_DTS | CC_ALLOW_SRC | CC_ENABLE_DRP, \
-				CC_SNK_WITH_PD)
-#define CONF_SRCDTS(c) CONF_SET_CLEAR(c, \
-				CC_ALLOW_SRC, \
-				CC_ENABLE_DRP | CC_DISABLE_DTS | CC_SNK_WITH_PD)
-#define CONF_SNKDTS(c) CONF_SET_CLEAR(c, \
-				0, \
-				CC_ALLOW_SRC | CC_ENABLE_DRP | \
-				CC_DISABLE_DTS | CC_SNK_WITH_PD)
-#define CONF_PDSNKDTS(c) CONF_SET_CLEAR(c, \
-				CC_SNK_WITH_PD, \
-				CC_ALLOW_SRC | CC_ENABLE_DRP | CC_DISABLE_DTS)
-#define CONF_DRPDTS(c) CONF_SET_CLEAR(c, \
-				CC_ALLOW_SRC | CC_ENABLE_DRP, \
-				CC_DISABLE_DTS | CC_SNK_WITH_PD)
+#define CONF_SRC(c)                                      \
+	CONF_SET_CLEAR(c, CC_DISABLE_DTS | CC_ALLOW_SRC, \
+		       CC_ENABLE_DRP | CC_SNK_WITH_PD)
+#define CONF_SNK(c)                       \
+	CONF_SET_CLEAR(c, CC_DISABLE_DTS, \
+		       CC_ALLOW_SRC | CC_ENABLE_DRP | CC_SNK_WITH_PD)
+#define CONF_PDSNK(c)                                      \
+	CONF_SET_CLEAR(c, CC_DISABLE_DTS | CC_SNK_WITH_PD, \
+		       CC_ALLOW_SRC | CC_ENABLE_DRP)
+#define CONF_DRP(c)                                                      \
+	CONF_SET_CLEAR(c, CC_DISABLE_DTS | CC_ALLOW_SRC | CC_ENABLE_DRP, \
+		       CC_SNK_WITH_PD)
+#define CONF_SRCDTS(c)                  \
+	CONF_SET_CLEAR(c, CC_ALLOW_SRC, \
+		       CC_ENABLE_DRP | CC_DISABLE_DTS | CC_SNK_WITH_PD)
+#define CONF_SNKDTS(c)                                                 \
+	CONF_SET_CLEAR(c, 0,                                           \
+		       CC_ALLOW_SRC | CC_ENABLE_DRP | CC_DISABLE_DTS | \
+			       CC_SNK_WITH_PD)
+#define CONF_PDSNKDTS(c)                  \
+	CONF_SET_CLEAR(c, CC_SNK_WITH_PD, \
+		       CC_ALLOW_SRC | CC_ENABLE_DRP | CC_DISABLE_DTS)
+#define CONF_DRPDTS(c)                                  \
+	CONF_SET_CLEAR(c, CC_ALLOW_SRC | CC_ENABLE_DRP, \
+		       CC_DISABLE_DTS | CC_SNK_WITH_PD)
+#define CONF_DTSOFF(c) CONF_SET_CLEAR(c, CC_DISABLE_DTS, 0)
+#define CONF_DTSON(c) CONF_SET_CLEAR(c, 0, CC_DISABLE_DTS)
 
 /* Macros to apply Rd/Rp to CC lines */
-#define DUT_ACTIVE_CC_SET(r, flags) \
-	gpio_set_flags(cc_config & CC_POLARITY ? \
-				CONCAT2(GPIO_USB_DUT_CC2_, r) : \
-				CONCAT2(GPIO_USB_DUT_CC1_, r), \
+#define DUT_ACTIVE_CC_SET(r, flags)                            \
+	gpio_set_flags(cc_config &CC_POLARITY ?                \
+			       CONCAT2(GPIO_USB_DUT_CC2_, r) : \
+			       CONCAT2(GPIO_USB_DUT_CC1_, r),  \
 		       flags)
-#define DUT_INACTIVE_CC_SET(r, flags) \
-	gpio_set_flags(cc_config & CC_POLARITY ? \
-				CONCAT2(GPIO_USB_DUT_CC1_, r) : \
-				CONCAT2(GPIO_USB_DUT_CC2_, r), \
+#define DUT_INACTIVE_CC_SET(r, flags)                          \
+	gpio_set_flags(cc_config &CC_POLARITY ?                \
+			       CONCAT2(GPIO_USB_DUT_CC1_, r) : \
+			       CONCAT2(GPIO_USB_DUT_CC2_, r),  \
 		       flags)
-#define DUT_BOTH_CC_SET(r, flags) \
-	do { \
+#define DUT_BOTH_CC_SET(r, flags)                                     \
+	do {                                                          \
 		gpio_set_flags(CONCAT2(GPIO_USB_DUT_CC1_, r), flags); \
 		gpio_set_flags(CONCAT2(GPIO_USB_DUT_CC2_, r), flags); \
 	} while (0)
@@ -88,32 +89,6 @@
 #define DUT_BOTH_CC_PD(r) DUT_BOTH_CC_SET(r, GPIO_OUT_LOW)
 #define DUT_BOTH_CC_OPEN(r) DUT_BOTH_CC_SET(r, GPIO_INPUT)
 
-/*
- * Dynamic PDO that reflects capabilities present on the CHG port. Allow for
- * multiple entries so that we can offer greater than 5V charging. The 1st
- * entry will be fixed 5V, but its current value may change based on the CHG
- * port vbus info. Subsequent entries are used for when offering vbus greater
- * than 5V.
- */
-static const uint16_t pd_src_voltages_mv[] = {
-		5000, 9000, 10000, 12000, 15000, 20000,
-};
-static uint32_t pd_src_chg_pdo[ARRAY_SIZE(pd_src_voltages_mv)];
-static uint8_t chg_pdo_cnt;
-
-const uint32_t pd_snk_pdo[] = {
-		PDO_FIXED(5000, 500, CHG_PDO_FIXED_FLAGS),
-		PDO_BATT(4750, 21000, 15000),
-		PDO_VAR(4750, 21000, 3000),
-};
-const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
-
-struct vbus_prop {
-	int mv;
-	int ma;
-};
-static struct vbus_prop vbus[CONFIG_USB_PD_PORT_MAX_COUNT];
-static int active_charge_port = CHARGE_PORT_NONE;
 static enum charge_supplier active_charge_supplier;
 static uint8_t vbus_rp = TYPEC_RP_RESERVED;
 
@@ -121,15 +96,15 @@ static int cc_config = CC_ALLOW_SRC;
 
 /* Voltage thresholds for no connect in DTS mode */
 static int pd_src_vnc_dts[TYPEC_RP_RESERVED][2] = {
-	{PD_SRC_3_0_VNC_MV, PD_SRC_1_5_VNC_MV},
-	{PD_SRC_1_5_VNC_MV, PD_SRC_DEF_VNC_MV},
-	{PD_SRC_3_0_VNC_MV, PD_SRC_DEF_VNC_MV},
+	{ PD_SRC_3_0_VNC_MV, PD_SRC_1_5_VNC_MV },
+	{ PD_SRC_1_5_VNC_MV, PD_SRC_DEF_VNC_MV },
+	{ PD_SRC_3_0_VNC_MV, PD_SRC_DEF_VNC_MV },
 };
 /* Voltage thresholds for Ra attach in DTS mode */
 static int pd_src_rd_threshold_dts[TYPEC_RP_RESERVED][2] = {
-	{PD_SRC_3_0_RD_THRESH_MV, PD_SRC_1_5_RD_THRESH_MV},
-	{PD_SRC_1_5_RD_THRESH_MV, PD_SRC_DEF_RD_THRESH_MV},
-	{PD_SRC_3_0_RD_THRESH_MV, PD_SRC_DEF_RD_THRESH_MV},
+	{ PD_SRC_3_0_RD_THRESH_MV, PD_SRC_1_5_RD_THRESH_MV },
+	{ PD_SRC_1_5_RD_THRESH_MV, PD_SRC_DEF_RD_THRESH_MV },
+	{ PD_SRC_3_0_RD_THRESH_MV, PD_SRC_DEF_RD_THRESH_MV },
 };
 /* Voltage thresholds for no connect in normal SRC mode */
 static int pd_src_vnc[TYPEC_RP_RESERVED] = {
@@ -160,20 +135,19 @@ static int cc_pull_stored = TYPEC_CC_RD;
 
 static int user_limited_max_mv = 20000;
 
+static uint8_t allow_pr_swap = 1;
+static uint8_t allow_dr_swap = 1;
+
 static uint32_t max_supported_voltage(void)
 {
 	int board_max_mv = board_get_version() >= BOARD_VERSION_BLACK ?
-		PD_MAX_VOLTAGE_MV : MAX_MV_RED_BLUE;
+				   PD_MAX_VOLTAGE_MV :
+				   MAX_MV_RED_BLUE;
 
 	return board_max_mv < user_limited_max_mv ? board_max_mv :
 						    user_limited_max_mv;
 }
 
-static int charge_port_is_active(void)
-{
-	return active_charge_port == CHG && vbus[CHG].mv > 0;
-}
-
 static int is_charge_through_allowed(void)
 {
 	return charge_port_is_active() && cc_config & CC_ALLOW_SRC;
@@ -270,7 +244,7 @@ static void board_manage_dut_port(void)
 static void update_ports(void)
 {
 	int pdo_index, src_index, snk_index, i;
-	uint32_t pdo, max_ma, max_mv;
+	uint32_t pdo, max_ma, max_mv, unused;
 
 	/*
 	 * CHG Vbus has changed states, update PDO that reflects CHG port
@@ -285,6 +259,20 @@ static void update_ports(void)
 			src_index = 0;
 			snk_index = -1;
 
+			/*
+			 * TODO: This code artificially limits PDO
+			 * to entries in pd_src_voltages_mv table
+			 *
+			 * This is artificially overconstrainted.
+			 *
+			 * Allow non-standard PDO objects so long
+			 * as they are valid. See: crrev/c/730877
+			 * for where this started.
+			 *
+			 * This needs to be rearchitected in order
+			 * to support Variable PDO passthrough.
+			 */
+
 			for (i = 0; i < ARRAY_SIZE(pd_src_voltages_mv); ++i) {
 				/* Adhere to board voltage limits */
 				if (pd_src_voltages_mv[i] >
@@ -292,8 +280,8 @@ static void update_ports(void)
 					break;
 
 				/* Find the 'best' PDO <= voltage */
-				pdo_index =
-				pd_find_pdo_index(pd_get_src_cap_cnt(CHG),
+				pdo_index = pd_find_pdo_index(
+					pd_get_src_cap_cnt(CHG),
 					pd_get_src_caps(CHG),
 					pd_src_voltages_mv[i], &pdo);
 				/* Don't duplicate PDOs */
@@ -304,20 +292,54 @@ static void update_ports(void)
 					continue;
 
 				snk_index = pdo_index;
-				pd_extract_pdo_power(pdo, &max_ma, &max_mv);
-				pd_src_chg_pdo[src_index++] =
+				pd_extract_pdo_power(pdo, &max_ma, &max_mv,
+						     &unused);
+				pd_src_chg_pdo[src_index] =
 					PDO_FIXED_VOLT(max_mv) |
-					PDO_FIXED_CURR(max_ma) |
-					DUT_PDO_FIXED_FLAGS |
-					PDO_FIXED_UNCONSTRAINED;
+					PDO_FIXED_CURR(max_ma);
+
+				if (src_index == 0) {
+					/*
+					 * TODO: 1st PDO *should* always be
+					 * vSafe5v PDO. But not always with bad
+					 * DUT. Should re-index and re-map.
+					 *
+					 * TODO: Add variable voltage PDO
+					 * conversion.
+					 */
+					pd_src_chg_pdo[src_index] &=
+						~(DUT_PDO_FIXED_FLAGS |
+						  PDO_FIXED_UNCONSTRAINED);
+
+					/*
+					 * TODO: Keep Unconstrained Power knobs
+					 * exposed and well-defined.
+					 *
+					 * Current method is workaround that
+					 * force-rejects PR_SWAPs in lieu of UP.
+					 *
+					 * Migrate to use config flag such as:
+					 * ((cc_config &
+					 * CC_UNCONSTRAINED_POWER)?
+					 * PDO_FIXED_UNCONSTRAINED:0)
+					 */
+					pd_src_chg_pdo[src_index] |=
+						(DUT_PDO_FIXED_FLAGS |
+						 PDO_FIXED_UNCONSTRAINED);
+				}
+				src_index++;
 			}
 			chg_pdo_cnt = src_index;
 		} else {
 			/* 5V PDO */
 			pd_src_chg_pdo[0] = PDO_FIXED_VOLT(PD_MIN_MV) |
-				PDO_FIXED_CURR(vbus[CHG].ma) |
-				DUT_PDO_FIXED_FLAGS |
-				PDO_FIXED_UNCONSTRAINED;
+					    PDO_FIXED_CURR(vbus[CHG].ma) |
+					    DUT_PDO_FIXED_FLAGS |
+					    PDO_FIXED_UNCONSTRAINED;
+			/*
+			 * TODO: Keep Unconstrained Power knobs
+			 * exposed and well-defined.
+			 */
 
 			chg_pdo_cnt = 1;
 		}
@@ -342,8 +364,8 @@ int board_set_active_charge_port(int charge_port)
 	return 0;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
 {
 	if (port != CHG)
 		return;
@@ -389,8 +411,9 @@ int pd_tcpc_cc_nc(int port, int cc_volt, int cc_sel)
 	if (cc_config & CC_DISABLE_DTS)
 		nc = cc_volt >= pd_src_vnc[rp_index];
 	else
-		nc = cc_volt >= pd_src_vnc_dts[rp_index][
-				cc_config & CC_POLARITY ? !cc_sel : cc_sel];
+		nc = cc_volt >=
+		     pd_src_vnc_dts[rp_index]
+				   [cc_config & CC_POLARITY ? !cc_sel : cc_sel];
 
 	return nc;
 }
@@ -416,19 +439,30 @@ int pd_tcpc_cc_ra(int port, int cc_volt, int cc_sel)
 	if (cc_config & CC_DISABLE_DTS)
 		ra = cc_volt < pd_src_rd_threshold[rp_index];
 	else
-		ra = cc_volt < pd_src_rd_threshold_dts[rp_index][
-				cc_config & CC_POLARITY ? !cc_sel : cc_sel];
+		ra = cc_volt <
+		     pd_src_rd_threshold_dts[rp_index]
+					    [cc_config & CC_POLARITY ? !cc_sel :
+								       cc_sel];
 
 	return ra;
 }
 
+/* DUT CC readings aren't valid if we aren't applying CC pulls */
+bool cc_is_valid(void)
+{
+	if ((cc_config & CC_DETACH) || (cc_pull_stored == TYPEC_CC_OPEN) ||
+	    ((cc_pull_stored == TYPEC_CC_RP) &&
+	     (rp_value_stored == TYPEC_RP_RESERVED)))
+		return false;
+	return true;
+}
+
 int pd_adc_read(int port, int cc)
 {
 	int mv;
-
 	if (port == 0)
 		mv = adc_read_channel(cc ? ADC_CHG_CC2_PD : ADC_CHG_CC1_PD);
-	else if (!(cc_config & CC_DETACH)) {
+	else if (cc_is_valid()) {
 		/*
 		 * In servo v4 hardware logic, both CC lines are wired directly
 		 * to DUT. When servo v4 as a snk, DUT may source Vconn to CC2
@@ -459,7 +493,6 @@ int pd_adc_read(int port, int cc)
 		 */
 		mv = 0;
 	}
-
 	return mv;
 }
 
@@ -568,7 +601,6 @@ int pd_set_rp_rd(int port, int cc_pull, int rp_value)
 			DUT_ACTIVE_CC_PD(RD);
 		else
 			DUT_BOTH_CC_PD(RD);
-
 	}
 
 	rp_value_stored = rp_value;
@@ -594,28 +626,12 @@ int board_select_rp_value(int port, int rp)
 	return EC_SUCCESS;
 }
 
-int charge_manager_get_source_pdo(const uint32_t **src_pdo, const int port)
-{
-	int pdo_cnt = 0;
-
-	/*
-	 * If CHG is providing VBUS, then advertise what's available on the CHG
-	 * port, otherwise we provide no power.
-	 */
-	if (charge_port_is_active()) {
-		*src_pdo =  pd_src_chg_pdo;
-		pdo_cnt = chg_pdo_cnt;
-	}
-
-	return pdo_cnt;
-}
-
 __override void pd_transition_voltage(int idx)
 {
 	timestamp_t deadline;
-	uint32_t ma, mv;
+	uint32_t ma, mv, unused;
 
-	pd_extract_pdo_power(pd_src_chg_pdo[idx - 1], &ma, &mv);
+	pd_extract_pdo_power(pd_src_chg_pdo[idx - 1], &ma, &mv, &unused);
 	/* Is this a transition to a new voltage? */
 	if (charge_port_is_active() && vbus[CHG].mv != mv) {
 		/*
@@ -627,8 +643,7 @@ __override void pd_transition_voltage(int idx)
 		/* Wait for CHG transition */
 		deadline.val = get_time().val + PD_T_PS_TRANSITION;
 		CPRINTS("Waiting for CHG port transition");
-		while (charge_port_is_active() &&
-		       vbus[CHG].mv != mv &&
+		while (charge_port_is_active() && vbus[CHG].mv != mv &&
 		       get_time().val < deadline.val)
 			msleep(10);
 
@@ -688,9 +703,7 @@ void pd_power_supply_reset(int port)
 
 int pd_snk_is_vbus_provided(int port)
 {
-
-	return gpio_get_level(port ? GPIO_USB_DET_PP_DUT :
-				     GPIO_USB_DET_PP_CHG);
+	return gpio_get_level(port ? GPIO_USB_DET_PP_DUT : GPIO_USB_DET_PP_CHG);
 }
 
 __override int pd_check_power_swap(int port)
@@ -707,14 +720,17 @@ __override int pd_check_power_swap(int port)
 	if (port == CHG)
 		return 0;
 
+	if (pd_get_power_role(port) == PD_ROLE_SINK &&
+	    !(cc_config & CC_ALLOW_SRC))
+		return 0;
+
 	if (pd_snk_is_vbus_provided(CHG))
-		return 1;
+		return allow_pr_swap;
 
 	return 0;
 }
 
-__override int pd_check_data_swap(int port,
-				  enum pd_data_role data_role)
+__override int pd_check_data_swap(int port, enum pd_data_role data_role)
 {
 	/*
 	 * Servo should allow data role swaps to let DUT see the USB hub, but
@@ -723,11 +739,10 @@ __override int pd_check_data_swap(int port,
 	if (port == CHG)
 		return 0;
 
-	return 1;
+	return allow_dr_swap;
 }
 
-__override void pd_execute_data_swap(int port,
-				     enum pd_data_role data_role)
+__override void pd_execute_data_swap(int port, enum pd_data_role data_role)
 {
 	/*
 	 * TODO(b/137887386): Turn on the fastboot/DFU path when data swap to
@@ -735,8 +750,7 @@ __override void pd_execute_data_swap(int port,
 	 */
 }
 
-__override void pd_check_pr_role(int port,
-				 enum pd_power_role pr_role,
+__override void pd_check_pr_role(int port, enum pd_power_role pr_role,
 				 int flags)
 {
 	/*
@@ -747,9 +761,7 @@ __override void pd_check_pr_role(int port,
 	 */
 }
 
-__override void pd_check_dr_role(int port,
-				 enum pd_data_role dr_role,
-				 int flags)
+__override void pd_check_dr_role(int port, enum pd_data_role dr_role, int flags)
 {
 	if (port == CHG)
 		return;
@@ -759,15 +771,14 @@ __override void pd_check_dr_role(int port,
 		pd_request_data_swap(port);
 }
 
-
 /* ----------------- Vendor Defined Messages ------------------ */
 /*
  * DP alt-mode config, user configurable.
  * Default is the mode disabled, supporting the C and D pin assignment,
  * multi-function preferred, and a plug.
  */
-static int alt_dp_config = (ALT_DP_PIN_C | ALT_DP_PIN_D | ALT_DP_MF_PREF |
-			    ALT_DP_PLUG);
+static int alt_dp_config =
+	(ALT_DP_PIN_C | ALT_DP_PIN_D | ALT_DP_MF_PREF | ALT_DP_PLUG);
 
 /**
  * Get the pins based on the user config.
@@ -802,8 +813,8 @@ const uint32_t vdo_idh = VDO_IDH(0, /* data caps as USB host */
 const uint32_t vdo_product = VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV);
 
 const uint32_t vdo_ama = VDO_AMA(CONFIG_USB_PD_IDENTITY_HW_VERS,
-				 CONFIG_USB_PD_IDENTITY_SW_VERS,
-				 0, 0, 0, 0, /* SS[TR][12] */
+				 CONFIG_USB_PD_IDENTITY_SW_VERS, 0, 0, 0,
+				 0, /* SS[TR][12] */
 				 0, /* Vconn power */
 				 0, /* Vconn power required */
 				 0, /* Vbus power required */
@@ -841,13 +852,13 @@ uint32_t vdo_dp_mode[MODE_CNT];
 
 static int svdm_response_modes(int port, uint32_t *payload)
 {
-	vdo_dp_mode[0] =
-		VDO_MODE_DP(0,             /* UFP pin cfg supported: none */
-			    alt_dp_config_pins(),  /* DFP pin */
-			    1,             /* no usb2.0 signalling in AMode */
-			    alt_dp_config_cable(), /* plug or receptacle */
-			    MODE_DP_V13,   /* DPv1.3 Support, no Gen2 */
-			    MODE_DP_SNK);  /* Its a sink only */
+	vdo_dp_mode[0] = VDO_MODE_DP(0, /* UFP pin cfg supported: none */
+				     alt_dp_config_pins(), /* DFP pin */
+				     1, /* no usb2.0 signalling in AMode */
+				     alt_dp_config_cable(), /* plug or
+							       receptacle */
+				     MODE_DP_V13, /* DPv1.3 Support, no Gen2 */
+				     MODE_DP_SNK); /* Its a sink only */
 
 	/* CCD uses the SBU lines; don't enable DP when dts-mode enabled */
 	if (!(cc_config & CC_DISABLE_DTS))
@@ -914,17 +925,18 @@ static int dp_status(int port, uint32_t *payload)
 	int hpd = get_hpd_level();
 
 	if (opos != OPOS)
-		return 0;  /* NAK */
-
-	payload[1] = VDO_DP_STATUS(
-		0,                /* IRQ_HPD */
-		hpd,              /* HPD_HI|LOW */
-		0,                /* request exit DP */
-		0,                /* request exit USB */
-		(alt_dp_config & ALT_DP_MF_PREF) != 0,  /* MF pref */
-		is_typec_dp_muxed(),
-		0,                /* power low */
-		hpd ? 0x2 : 0);
+		return 0; /* NAK */
+
+	payload[1] =
+		VDO_DP_STATUS(0, /* IRQ_HPD */
+			      hpd, /* HPD_HI|LOW */
+			      0, /* request exit DP */
+			      0, /* request exit USB */
+			      (alt_dp_config & ALT_DP_MF_PREF) != 0, /* MF
+									pref
+								      */
+			      is_typec_dp_muxed(), 0, /* power low */
+			      hpd ? 0x2 : 0);
 	return 2;
 }
 
@@ -944,15 +956,15 @@ static int svdm_enter_mode(int port, uint32_t *payload)
 	/* SID & mode request is valid */
 	if ((PD_VDO_VID(payload[0]) != USB_SID_DISPLAYPORT) ||
 	    (PD_VDO_OPOS(payload[0]) != OPOS))
-		return 0;  /* NAK */
+		return 0; /* NAK */
 
 	alt_mode = OPOS;
 	return 1;
 }
 
-int pd_alt_mode(int port, enum tcpm_transmit_type type, uint16_t svid)
+int pd_alt_mode(int port, enum tcpci_msg_type type, uint16_t svid)
 {
-	if (type == TCPC_TX_SOP && svid == USB_SID_DISPLAYPORT)
+	if (type == TCPCI_MSG_SOP && svid == USB_SID_DISPLAYPORT)
 		return alt_mode;
 
 	return 0;
@@ -983,7 +995,7 @@ const struct svdm_response svdm_rsp = {
 };
 
 __override int pd_custom_vdm(int port, int cnt, uint32_t *payload,
-		  uint32_t **rpayload)
+			     uint32_t **rpayload)
 {
 	int cmd = PD_VDO_CMD(payload[0]);
 
@@ -995,7 +1007,7 @@ __override int pd_custom_vdm(int port, int cnt, uint32_t *payload,
 	case VDO_CMD_VERSION:
 		/* guarantee last byte of payload is null character */
 		*(payload + cnt - 1) = 0;
-		CPRINTF("ver: %s\n", (char *)(payload+1));
+		CPRINTF("ver: %s\n", (char *)(payload + 1));
 		break;
 	case VDO_CMD_CURRENT:
 		CPRINTF("Current: %dmA\n", payload[1]);
@@ -1017,12 +1029,10 @@ static void print_cc_mode(void)
 		 gpio_get_level(GPIO_DUT_CHG_EN) ? "on" : "off");
 	ccprintf("chg allowed: %s\n", cc_config & CC_ALLOW_SRC ? "on" : "off");
 	ccprintf("drp enabled: %s\n", cc_config & CC_ENABLE_DRP ? "on" : "off");
-	ccprintf("cc polarity: %s\n", cc_config & CC_POLARITY ? "cc2" :
-								"cc1");
+	ccprintf("cc polarity: %s\n", cc_config & CC_POLARITY ? "cc2" : "cc1");
 	ccprintf("pd enabled: %s\n", pd_comm_is_enabled(DUT) ? "on" : "off");
 }
 
-
 static void do_cc(int cc_config_new)
 {
 	int chargeable;
@@ -1031,7 +1041,7 @@ static void do_cc(int cc_config_new)
 	if (cc_config_new != cc_config) {
 		if (!(cc_config & CC_DETACH)) {
 			/* Force detach */
-			pd_power_supply_reset(DUT);
+			gpio_set_level(GPIO_DUT_CHG_EN, 0);
 			/* Always set to 0 here so both CC lines are changed */
 			cc_config &= ~(CC_DISABLE_DTS & CC_ALLOW_SRC);
 
@@ -1092,7 +1102,7 @@ static void do_cc(int cc_config_new)
 	}
 }
 
-static int command_cc(int argc, char **argv)
+static int command_cc(int argc, const char **argv)
 {
 	int cc_config_new = cc_config;
 
@@ -1123,6 +1133,10 @@ static int command_cc(int argc, char **argv)
 			cc_config_new = CONF_PDSNKDTS(cc_config_new);
 		else if (!strcasecmp(argv[1], "drpdts"))
 			cc_config_new = CONF_DRPDTS(cc_config_new);
+		else if (!strcasecmp(argv[1], "dtsoff"))
+			cc_config_new = CONF_DTSOFF(cc_config_new);
+		else if (!strcasecmp(argv[1], "dtson"))
+			cc_config_new = CONF_DTSON(cc_config_new);
 		else
 			return EC_ERROR_PARAM2;
 	}
@@ -1141,7 +1155,7 @@ static int command_cc(int argc, char **argv)
 }
 DECLARE_CONSOLE_COMMAND(cc, command_cc,
 			"[off|on|src|snk|pdsnk|drp|srcdts|snkdts|pdsnkdts|"
-			"drpdts] [cc1|cc2]",
+			"drpdts|dtsoff|dtson] [cc1|cc2]",
 			"Servo_v4 DTS and CHG mode");
 
 static void fake_disconnect_end(void)
@@ -1161,7 +1175,7 @@ static void fake_disconnect_start(void)
 }
 DECLARE_DEFERRED(fake_disconnect_start);
 
-static int cmd_fake_disconnect(int argc, char *argv[])
+static int cmd_fake_disconnect(int argc, const char *argv[])
 {
 	int delay_ms, duration_ms;
 	char *e;
@@ -1183,41 +1197,36 @@ static int cmd_fake_disconnect(int argc, char *argv[])
 	fake_pd_disconnect_duration_us = duration_ms * MSEC;
 	hook_call_deferred(&fake_disconnect_start_data, delay_ms * MSEC);
 
-	ccprintf("Fake disconnect for %d ms starting in %d ms.\n",
-		duration_ms, delay_ms);
+	ccprintf("Fake disconnect for %d ms starting in %d ms.\n", duration_ms,
+		 delay_ms);
 
 	return EC_SUCCESS;
 }
 DECLARE_CONSOLE_COMMAND(fakedisconnect, cmd_fake_disconnect,
 			"<delay_ms> <duration_ms>", NULL);
 
-static int cmd_ada_srccaps(int argc, char *argv[])
+static int cmd_ada_srccaps(int argc, const char *argv[])
 {
 	int i;
-	const uint32_t * const ada_srccaps = pd_get_src_caps(CHG);
+	const uint32_t *const ada_srccaps = pd_get_src_caps(CHG);
 
 	for (i = 0; i < pd_get_src_cap_cnt(CHG); ++i) {
-		uint32_t max_ma, max_mv;
+		uint32_t max_ma, max_mv, unused;
+
+		if (IS_ENABLED(CONFIG_USB_PD_ONLY_FIXED_PDOS) &&
+		    (ada_srccaps[i] & PDO_TYPE_MASK) != PDO_TYPE_FIXED)
+			continue;
 
-		pd_extract_pdo_power(ada_srccaps[i], &max_ma, &max_mv);
+		pd_extract_pdo_power(ada_srccaps[i], &max_ma, &max_mv, &unused);
 		ccprintf("%d: %dmV/%dmA\n", i, max_mv, max_ma);
 	}
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(ada_srccaps, cmd_ada_srccaps,
-			"",
+DECLARE_CONSOLE_COMMAND(ada_srccaps, cmd_ada_srccaps, "",
 			"Print adapter SrcCap");
 
-static void chg_pd_disconnect(void)
-{
-	/* Clear charger PDO on CHG port disconnected. */
-	if (pd_is_disconnected(CHG))
-		pd_set_src_caps(CHG, 0, NULL);
-}
-DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, chg_pd_disconnect, HOOK_PRIO_DEFAULT);
-
-static int cmd_dp_action(int argc, char *argv[])
+static int cmd_dp_action(int argc, const char *argv[])
 {
 	int i;
 	char *e;
@@ -1236,8 +1245,8 @@ static int cmd_dp_action(int argc, char *argv[])
 		alt_dp_config &= ~ALT_DP_ENABLE;
 	} else if (!strcasecmp(argv[1], "pins")) {
 		if (argc >= 3) {
-			alt_dp_config &= ~(ALT_DP_PIN_C | ALT_DP_PIN_D |
-					   ALT_DP_PIN_E);
+			alt_dp_config &=
+				~(ALT_DP_PIN_C | ALT_DP_PIN_D | ALT_DP_PIN_E);
 			for (i = 0; i < 3; i++) {
 				if (!argv[2][i])
 					break;
@@ -1310,10 +1319,10 @@ static int cmd_dp_action(int argc, char *argv[])
 			}
 		}
 		CPRINTS("HPD source: %s",
-			(alt_dp_config & ALT_DP_OVERRIDE_HPD) ? "overridden"
-							      : "external");
+			(alt_dp_config & ALT_DP_OVERRIDE_HPD) ? "overridden" :
+								"external");
 		CPRINTS("HPD level: %d", get_hpd_level());
-	}  else if (!strcasecmp(argv[1], "help")) {
+	} else if (!strcasecmp(argv[1], "help")) {
 		CPRINTS("Usage: usbc_action dp [enable|disable|hpd|mf|pins|"
 			"plug]");
 	}
@@ -1321,7 +1330,7 @@ static int cmd_dp_action(int argc, char *argv[])
 	return EC_SUCCESS;
 }
 
-static int cmd_usbc_action(int argc, char *argv[])
+static int cmd_usbc_action(int argc, const char *argv[])
 {
 	if (argc >= 2 && !strcasecmp(argv[1], "dp"))
 		return cmd_dp_action(argc - 1, &argv[1]);
@@ -1375,6 +1384,27 @@ static int cmd_usbc_action(int argc, char *argv[])
 		 * Drop this message if when we phase out the usbc_role control.
 		 */
 		ccprintf("CHG SRC %dmV\n", user_limited_max_mv);
+	} else if (!strcasecmp(argv[1], "drswap")) {
+		if (argc == 2) {
+			CPRINTF("allow_dr_swap = %d\n", allow_dr_swap);
+			return EC_SUCCESS;
+		}
+
+		if (argc != 3)
+			return EC_ERROR_PARAM2;
+
+		allow_dr_swap = !!atoi(argv[2]);
+
+	} else if (!strcasecmp(argv[1], "prswap")) {
+		if (argc == 2) {
+			CPRINTF("allow_pr_swap = %d\n", allow_pr_swap);
+			return EC_SUCCESS;
+		}
+
+		if (argc != 3)
+			return EC_ERROR_PARAM2;
+
+		allow_pr_swap = !!atoi(argv[2]);
 	} else {
 		return EC_ERROR_PARAM1;
 	}
@@ -1382,5 +1412,6 @@ static int cmd_usbc_action(int argc, char *argv[])
 	return EC_SUCCESS;
 }
 DECLARE_CONSOLE_COMMAND(usbc_action, cmd_usbc_action,
-			"5v|12v|20v|dev|pol0|pol1|drp|dp|chg x(x=voltage)",
+			"5v|12v|20v|dev|pol0|pol1|drp|dp|chg x(x=voltage)|"
+			"drswap [1|0]|prswap [1|0]",
 			"Set Servo v4 type-C port state");
diff --git a/board/servo_v4/vif_override.xml b/board/servo_v4/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/servo_v4/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/servo_v4p1/OWNERS b/board/servo_v4p1/OWNERS
new file mode 100644
index 0000000000..8f4be1ea4d
--- /dev/null
+++ b/board/servo_v4p1/OWNERS
@@ -0,0 +1,3 @@
+bnemec@google.com
+matthewb@chromium.org
+shurst@google.com
diff --git a/board/servo_v4p1/board.c b/board/servo_v4p1/board.c
index 6148358aff..24ffbbe84f 100644
--- a/board/servo_v4p1/board.c
+++ b/board/servo_v4p1/board.c
@@ -1,16 +1,16 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 /* Servo V4p1 configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "ccd_measure_sbu.h"
 #include "chg_control.h"
 #include "common.h"
 #include "console.h"
 #include "dacs.h"
+#include "driver/ioexpander/tca64xxa.h"
 #include "ec_version.h"
 #include "fusb302b.h"
 #include "gpio.h"
@@ -29,15 +29,18 @@
 #include "tusb1064.h"
 #include "update_fw.h"
 #include "usart-stm32f0.h"
-#include "usart_tx_dma.h"
 #include "usart_rx_dma.h"
+#include "usart_tx_dma.h"
+#include "usb-stream.h"
 #include "usb_gpio.h"
 #include "usb_i2c.h"
+#include "usb_mux.h"
 #include "usb_pd.h"
 #include "usb_spi.h"
-#include "usb-stream.h"
 #include "util.h"
 
+#include <driver/gl3590.h>
+
 #ifdef SECTION_IS_RO
 #define CROS_EC_SECTION "RO"
 #else
@@ -63,6 +66,146 @@ static void tca_evt(enum gpio_signal signal)
 	irq_ioexpanders();
 }
 
+/*
+ * Some DUTs are known to be incompatible with servo_v4p1 and USB3.
+ * Due to this USB3 to DUT is forced to be disabled by default.
+ * This command can enable or disable USB3 to DUT manually.
+ * This command is issued during initialization of servod,
+ * automatically enabling USB3 only on DUTs that are known to work
+ * with USB3 servo.
+ * For more information please refer to b/254857085 and b/263573379.
+ */
+static bool usb3_to_dut_enable;
+static int cmd_dut_usb3(int argc, const char *argv[])
+{
+	mux_state_t mux_state;
+
+	if (argc > 2)
+		return EC_ERROR_PARAM_COUNT;
+
+	if (!strcasecmp(argv[1], "enable")) {
+		/*
+		 * Need to set this flag before usb_mux_set to prevent
+		 * calling additional set in board_tusb1064_set.
+		 */
+		usb3_to_dut_enable = true;
+
+		/* Need to reset DUT hub and force re-enumeration. */
+		gpio_set_level(GPIO_DUT_HUB_USB_RESET_L, 0);
+
+		/* Overwrite current Type-C mux state to enable USB3. */
+		mux_state = usb_mux_get(DUT) | USB_PD_MUX_USB_ENABLED;
+
+		usb_mux_set(DUT, mux_state, USB_SWITCH_CONNECT,
+			    polarity_rm_dts(pd_get_polarity(DUT)));
+
+		/* Delay enabling DUT hub to avoid enumeration problems. */
+		usleep(MSEC);
+		gpio_set_level(GPIO_DUT_HUB_USB_RESET_L, 1);
+	} else if (!strcasecmp(argv[1], "disable")) {
+		/*
+		 * Make sure this flag is set to avoid calling additional
+		 * mux set operation in board specific routine.
+		 */
+		usb3_to_dut_enable = true;
+
+		/* No need to reset hub, devices should auto re-enumerate. */
+		mux_state = usb_mux_get(DUT) & ~USB_PD_MUX_USB_ENABLED;
+
+		usb_mux_set(DUT, mux_state, USB_SWITCH_CONNECT,
+			    polarity_rm_dts(pd_get_polarity(DUT)));
+		usb3_to_dut_enable = false;
+	} else if (argc != 1) {
+		ccprintf("Invalid argument: %s\n", argv[1]);
+		return EC_ERROR_INVAL;
+	}
+
+	ccprintf("USB3 to DUT: %s\n",
+		 usb3_to_dut_enable ? "allowed/enabled" : "disabled");
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(dut_usb3, cmd_dut_usb3, "dut_usb3 [enable/disable]>",
+			"Enable or disable USB3 to DUT. Note that after every "
+			"'dut_usb3 enable' USB3 is enabled once and than only "
+			"allowed, not forced. Some other part of servo logic "
+			"(e.g. pd stack) can still enable/disable it.");
+
+/*
+ * TUSB1064 set mux board tuning.
+ * Adds in board specific gain and DP lane count configuration.
+ * Also adds USB3 quirk.
+ */
+static int board_tusb1064_set(const struct usb_mux *me, mux_state_t mux_state)
+{
+	int rv = EC_SUCCESS;
+	bool unused;
+
+	/*
+	 * Apply 10dB gain. Note, this value is selected to match the gain that
+	 * would be set by default if the 2 GPIO gain set pins are left
+	 * floating.
+	 */
+	if (mux_state & USB_PD_MUX_DP_ENABLED) {
+		rv = tusb1064_set_dp_rx_eq(me, TUSB1064_DP_EQ_RX_10_0_DB);
+		/*
+		 * There is no need to perform any of additional
+		 * USB3 workaround related logic if we are using DP, so return.
+		 */
+		return rv;
+	}
+
+	/*
+	 * This function is issued after standard set operation.
+	 * Logic below overwrites any mux set operation issued by e.g.
+	 * pd stack. It prevents using USB3 to DUT on servo, unless
+	 * it is explicitly allowed.
+	 * If user is sure that specific DUT works with USB3 servo_v4p1,
+	 * can skip this logic setting usb3_to_dut_enable flag.
+	 * It can be done via console command usb3_dut [on\off].
+	 */
+	if (!usb3_to_dut_enable) {
+		/*
+		 * In this point servo is already connected to DUT.
+		 * USB3 can be already enabled for short moment.
+		 * Keep DUT hub in reset until MUX is finally set
+		 * (USB3 disabled) to prevent any enumeration issues.
+		 */
+		gpio_set_level(GPIO_DUT_HUB_USB_RESET_L, 0);
+
+		/*
+		 * Overwrite any set operation to disable USB3.
+		 * Note that we can use internal driver call as mux driver
+		 * already locked mutex inside usb_mux_set operation.
+		 * Also note that we can not use usb_mux_set to prevent
+		 * infinite recursion.
+		 */
+		rv = tusb1064_set_mux(me, mux_state & ~USB_PD_MUX_USB_ENABLED,
+				      &unused);
+
+		/* MUX is set, add preventive delay and enable DUT USB hub. */
+		usleep(MSEC);
+		gpio_set_level(GPIO_DUT_HUB_USB_RESET_L, 1);
+	}
+	return rv;
+}
+
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	[CHG] = {
+		/* CHG port connected directly to USB 3.0 hub, no mux */
+	},
+	[DUT] = {
+		/* DUT port with UFP mux */
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = DUT,
+				.i2c_port = I2C_PORT_MASTER,
+				.i2c_addr_flags = TUSB1064_I2C_ADDR10_FLAGS,
+				.driver = &tusb1064_usb_mux_driver,
+				.board_set = &board_tusb1064_set,
+			},
+	}
+};
+
 static volatile uint64_t hpd_prev_ts;
 static volatile int hpd_prev_level;
 
@@ -90,7 +233,7 @@ static volatile int hpd_prev_level;
 
 void hpd_irq_deferred(void)
 {
-	int dp_mode = pd_alt_mode(1, TCPC_TX_SOP, USB_SID_DISPLAYPORT);
+	int dp_mode = pd_alt_mode(1, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT);
 
 	if (dp_mode) {
 		pd_send_hpd(DUT, hpd_irq);
@@ -102,7 +245,7 @@ DECLARE_DEFERRED(hpd_irq_deferred);
 void hpd_lvl_deferred(void)
 {
 	int level = gpio_get_level(GPIO_DP_HPD);
-	int dp_mode = pd_alt_mode(1, TCPC_TX_SOP, USB_SID_DISPLAYPORT);
+	int dp_mode = pd_alt_mode(1, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT);
 
 	if (level != hpd_prev_level) {
 		/* It's a glitch while in deferred or canceled action */
@@ -149,21 +292,35 @@ static void tcpc_evt(enum gpio_signal signal)
 	update_status_fusb302b();
 }
 
+#define HOST_HUB 0
+struct uhub_i2c_iface_t uhub_config[] = {
+	{ I2C_PORT_MASTER, GL3590_I2C_ADDR0 },
+};
+
+static void host_hub_evt(void)
+{
+	gl3590_irq_handler(HOST_HUB);
+}
+DECLARE_DEFERRED(host_hub_evt);
+
 static void hub_evt(enum gpio_signal signal)
 {
-	ccprintf("hub event\n");
+	hook_call_deferred(&host_hub_evt_data, 0);
 }
 
-static void bc12_evt(enum gpio_signal signal)
+static void dut_pwr_evt(enum gpio_signal signal)
 {
-	ccprintf("bc12_evt\n");
+	ccprintf("dut_pwr_evt\n");
 }
 
 /* Enable uservo USB. */
 static void init_uservo_port(void)
 {
 	/* Enable USERVO_POWER_EN */
-	uservo_power_en(1);
+	ec_uservo_power_en(1);
+
+	gl3590_enable_ports(0, GL3590_DFP4, 1);
+
 	/* Connect uservo to host hub */
 	uservo_fastboot_mux_sel(0);
 }
@@ -180,34 +337,13 @@ void ext_hpd_detection_enable(int enable)
 		gpio_disable_interrupt(GPIO_DP_HPD);
 	}
 }
-#else
-void snk_task(void *u)
-{
-	/* DO NOTHING */
-}
-
-void pd_task(void *u)
-{
-	/* DO NOTHING */
-}
-__override uint8_t board_get_usb_pd_port_count(void)
-{
-	return CONFIG_USB_PD_PORT_MAX_COUNT;
-}
-
-void pd_set_suspend(int port, int suspend)
-{
-	/*
-	 * Do nothing. This is only here to make the linker happy for this
-	 * old board on ToT.
-	 */
-}
 #endif /* SECTION_IS_RO */
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
 /******************************************************************************
  * Board pre-init function.
@@ -251,23 +387,22 @@ void board_config_pre_init(void)
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* USB PD CC lines sensing. Converted to mV (3300mV/4096). */
-	[ADC_CHG_CC1_PD] = {"CHG_CC1_PD", 3300, 4096, 0, STM32_AIN(2)},
-	[ADC_CHG_CC2_PD] = {"CHG_CC2_PD", 3300, 4096, 0, STM32_AIN(4)},
-	[ADC_DUT_CC1_PD] = {"DUT_CC1_PD", 3300, 4096, 0, STM32_AIN(0)},
-	[ADC_DUT_CC2_PD] = {"DUT_CC2_PD", 3300, 4096, 0, STM32_AIN(5)},
-	[ADC_SBU1_DET] = {"SBU1_DET", 3300, 4096, 0, STM32_AIN(3)},
-	[ADC_SBU2_DET] = {"SBU2_DET", 3300, 4096, 0, STM32_AIN(7)},
-	[ADC_SUB_C_REF] = {"SUB_C_REF", 3300, 4096, 0, STM32_AIN(1)},
+	[ADC_CHG_CC1_PD] = { "CHG_CC1_PD", 3300, 4096, 0, STM32_AIN(2) },
+	[ADC_CHG_CC2_PD] = { "CHG_CC2_PD", 3300, 4096, 0, STM32_AIN(4) },
+	[ADC_DUT_CC1_PD] = { "DUT_CC1_PD", 3300, 4096, 0, STM32_AIN(0) },
+	[ADC_DUT_CC2_PD] = { "DUT_CC2_PD", 3300, 4096, 0, STM32_AIN(5) },
+	[ADC_SBU1_DET] = { "SBU1_DET", 3300, 4096, 0, STM32_AIN(3) },
+	[ADC_SBU2_DET] = { "SBU2_DET", 3300, 4096, 0, STM32_AIN(7) },
+	[ADC_SUB_C_REF] = { "SUB_C_REF", 3300, 4096, 0, STM32_AIN(1) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
-
 /******************************************************************************
  * Forward UARTs as a USB serial interface.
  */
 
-#define USB_STREAM_RX_SIZE	16
-#define USB_STREAM_TX_SIZE	16
+#define USB_STREAM_RX_SIZE 16
+#define USB_STREAM_TX_SIZE 16
 
 /******************************************************************************
  * Forward USART3 as a simple USB serial interface.
@@ -276,29 +411,19 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 static struct usart_config const usart3;
 struct usb_stream_config const usart3_usb;
 
-static struct queue const usart3_to_usb = QUEUE_DIRECT(64, uint8_t,
-	usart3.producer, usart3_usb.consumer);
-static struct queue const usb_to_usart3 = QUEUE_DIRECT(64, uint8_t,
-	usart3_usb.producer, usart3.consumer);
+static struct queue const usart3_to_usb =
+	QUEUE_DIRECT(64, uint8_t, usart3.producer, usart3_usb.consumer);
+static struct queue const usb_to_usart3 =
+	QUEUE_DIRECT(64, uint8_t, usart3_usb.producer, usart3.consumer);
 
 static struct usart_config const usart3 =
-	USART_CONFIG(usart3_hw,
-		usart_rx_interrupt,
-		usart_tx_interrupt,
-		115200,
-		0,
-		usart3_to_usb,
-		usb_to_usart3);
-
-USB_STREAM_CONFIG(usart3_usb,
-	USB_IFACE_USART3_STREAM,
-	USB_STR_USART3_STREAM_NAME,
-	USB_EP_USART3_STREAM,
-	USB_STREAM_RX_SIZE,
-	USB_STREAM_TX_SIZE,
-	usb_to_usart3,
-	usart3_to_usb)
+	USART_CONFIG(usart3_hw, usart_rx_interrupt, usart_tx_interrupt, 115200,
+		     0, usart3_to_usb, usb_to_usart3);
 
+USB_STREAM_CONFIG(usart3_usb, USB_IFACE_USART3_STREAM,
+		  USB_STR_USART3_STREAM_NAME, USB_EP_USART3_STREAM,
+		  USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE, usb_to_usart3,
+		  usart3_to_usb)
 
 /******************************************************************************
  * Forward USART4 as a simple USB serial interface.
@@ -307,64 +432,73 @@ USB_STREAM_CONFIG(usart3_usb,
 static struct usart_config const usart4;
 struct usb_stream_config const usart4_usb;
 
-static struct queue const usart4_to_usb = QUEUE_DIRECT(64, uint8_t,
-	usart4.producer, usart4_usb.consumer);
-static struct queue const usb_to_usart4 = QUEUE_DIRECT(64, uint8_t,
-	usart4_usb.producer, usart4.consumer);
+static struct queue const usart4_to_usb =
+	QUEUE_DIRECT(64, uint8_t, usart4.producer, usart4_usb.consumer);
+static struct queue const usb_to_usart4 =
+	QUEUE_DIRECT(64, uint8_t, usart4_usb.producer, usart4.consumer);
 
 static struct usart_config const usart4 =
-	USART_CONFIG(usart4_hw,
-		usart_rx_interrupt,
-		usart_tx_interrupt,
-		9600,
-		0,
-		usart4_to_usb,
-		usb_to_usart4);
-
-USB_STREAM_CONFIG(usart4_usb,
-	USB_IFACE_USART4_STREAM,
-	USB_STR_USART4_STREAM_NAME,
-	USB_EP_USART4_STREAM,
-	USB_STREAM_RX_SIZE,
-	USB_STREAM_TX_SIZE,
-	usb_to_usart4,
-	usart4_to_usb)
+	USART_CONFIG(usart4_hw, usart_rx_interrupt, usart_tx_interrupt, 9600, 0,
+		     usart4_to_usb, usb_to_usart4);
+
+USB_STREAM_CONFIG_USART_IFACE(usart4_usb, USB_IFACE_USART4_STREAM,
+			      USB_STR_USART4_STREAM_NAME, USB_EP_USART4_STREAM,
+			      USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE,
+			      usb_to_usart4, usart4_to_usb, usart4)
 
+/*
+ * Define usb interface descriptor for the `EMPTY` usb interface, to satisfy
+ * UEFI and kernel requirements (see b/183857501).
+ */
+const struct usb_interface_descriptor USB_IFACE_DESC(USB_IFACE_EMPTY) = {
+	.bLength = USB_DT_INTERFACE_SIZE,
+	.bDescriptorType = USB_DT_INTERFACE,
+	.bInterfaceNumber = USB_IFACE_EMPTY,
+	.bAlternateSetting = 0,
+	.bNumEndpoints = 0,
+	.bInterfaceClass = USB_CLASS_VENDOR_SPEC,
+	.bInterfaceSubClass = 0,
+	.bInterfaceProtocol = 0,
+	.iInterface = 0,
+};
 
 /******************************************************************************
  * Define the strings used in our USB descriptors.
  */
 
 const void *const usb_strings[] = {
-	[USB_STR_DESC]         = usb_string_desc,
-	[USB_STR_VENDOR]       = USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]      = USB_STRING_DESC("Servo V4p1"),
-	[USB_STR_SERIALNO]     = USB_STRING_DESC("1234-a"),
-	[USB_STR_VERSION]      = USB_STRING_DESC(CROS_EC_VERSION32),
-	[USB_STR_I2C_NAME]     = USB_STRING_DESC("I2C"),
+	[USB_STR_DESC] = usb_string_desc,
+	[USB_STR_VENDOR] = USB_STRING_DESC("Google LLC"),
+	[USB_STR_PRODUCT] = USB_STRING_DESC("Servo V4p1"),
+	[USB_STR_SERIALNO] = USB_STRING_DESC("1234-a"),
+	[USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32),
+	[USB_STR_I2C_NAME] = USB_STRING_DESC("I2C"),
 	[USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Servo EC Shell"),
-	[USB_STR_USART3_STREAM_NAME]  = USB_STRING_DESC("DUT UART"),
-	[USB_STR_USART4_STREAM_NAME]  = USB_STRING_DESC("Atmega UART"),
-	[USB_STR_UPDATE_NAME]  = USB_STRING_DESC("Firmware update"),
+	[USB_STR_USART3_STREAM_NAME] = USB_STRING_DESC("DUT UART"),
+	[USB_STR_USART4_STREAM_NAME] = USB_STRING_DESC("Atmega UART"),
+	[USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"),
 };
 
 BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
 
-
-
 /******************************************************************************
  * Support I2C bridging over USB.
  */
 
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{"master", I2C_PORT_MASTER, 100,
-		GPIO_MASTER_I2C_SCL, GPIO_MASTER_I2C_SDA},
+	{ .name = "master",
+	  .port = I2C_PORT_MASTER,
+	  .kbps = 100,
+	  .scl = GPIO_MASTER_I2C_SCL,
+	  .sda = GPIO_MASTER_I2C_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
-int usb_i2c_board_is_enabled(void) { return 1; }
-
+int usb_i2c_board_is_enabled(void)
+{
+	return 1;
+}
 
 /******************************************************************************
  * Initialize board.
@@ -375,6 +509,36 @@ int board_get_version(void)
 	return board_id_det();
 }
 
+#ifdef SECTION_IS_RO
+/* Forward declaration */
+static void evaluate_input_power_def(void);
+DECLARE_DEFERRED(evaluate_input_power_def);
+
+static void evaluate_input_power_def(void)
+{
+	int state;
+	static int retry = 3;
+
+	/* Wait until host hub INTR# signal is asserted */
+	state = gpio_get_level(GPIO_USBH_I2C_BUSY_INT);
+	if ((state == 0) && retry--) {
+		hook_call_deferred(&evaluate_input_power_def_data, 100 * MSEC);
+		return;
+	}
+
+	if (retry == 0)
+		CPRINTF("Host hub I2C isn't online, expect issues with its "
+			"behaviour\n");
+
+	gpio_enable_interrupt(GPIO_USBH_I2C_BUSY_INT);
+
+	gl3590_init(HOST_HUB);
+
+	init_uservo_port();
+	init_pathsel();
+}
+#endif
+
 static void board_init(void)
 {
 	/* USB to serial queues */
@@ -390,23 +554,33 @@ static void board_init(void)
 	/* Delay DUT hub to avoid brownout. */
 	usleep(MSEC);
 
-	init_ioexpanders();
-	init_dacs();
-	init_tusb1064(1);
 	init_pi3usb9201();
 
 	/* Clear BBRAM, we don't want any PD state carried over on reset. */
 	system_set_bbram(SYSTEM_BBRAM_IDX_PD0, 0);
 	system_set_bbram(SYSTEM_BBRAM_IDX_PD1, 0);
 
-	/* Bring atmel part out of reset */
-	atmel_reset_l(1);
-
 #ifdef SECTION_IS_RO
+	init_ioexpanders();
+	CPRINTS("Board ID is %d", board_id_det());
+
+	init_dacs();
 	init_uservo_port();
 	init_pathsel();
 	init_ina231s();
 	init_fusb302b(1);
+	vbus_dischrg_en(0);
+
+	/* Bring atmel part out of reset */
+	atmel_reset_l(1);
+
+	/*
+	 * Get data about available input power. Defer this check, since we need
+	 * to wait for USB2/USB3 enumeration on host hub as well as I2C
+	 * interface of this hub needs to be initialized. Genesys recommends at
+	 * least 100ms.
+	 */
+	hook_call_deferred(&evaluate_input_power_def_data, 100 * MSEC);
 
 	/* Enable DUT USB2.0 pair. */
 	gpio_set_level(GPIO_FASTBOOT_DUTHUB_MUX_EN_L, 0);
@@ -417,8 +591,7 @@ static void board_init(void)
 
 	gpio_enable_interrupt(GPIO_STM_FAULT_IRQ_L);
 	gpio_enable_interrupt(GPIO_DP_HPD);
-	gpio_enable_interrupt(GPIO_USBH_I2C_BUSY_INT);
-	gpio_enable_interrupt(GPIO_BC12_INT_ODL);
+	gpio_enable_interrupt(GPIO_DUT_PWR_IRQ_ODL);
 
 	/* Disable power to DUT by default */
 	chg_power_select(CHG_POWER_OFF);
@@ -431,6 +604,8 @@ static void board_init(void)
 
 	/* Start SuzyQ detection */
 	start_ccd_meas_sbu_cycle();
+#else /* SECTION_IS_RO */
+	CPRINTS("Board ID is %d", board_id_det());
 #endif /* SECTION_IS_RO */
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
@@ -456,4 +631,16 @@ void tick_event(void)
 	}
 }
 DECLARE_HOOK(HOOK_TICK, tick_event, HOOK_PRIO_DEFAULT);
+
+struct ioexpander_config_t ioex_config[] = {
+	[0] = { .drv = &tca64xxa_ioexpander_drv,
+		.i2c_host_port = TCA6416A_PORT,
+		.i2c_addr_flags = TCA6416A_ADDR,
+		.flags = IOEX_FLAGS_TCA64XXA_FLAG_VER_TCA6416A },
+	[1] = { .drv = &tca64xxa_ioexpander_drv,
+		.i2c_host_port = TCA6424A_PORT,
+		.i2c_addr_flags = TCA6424A_ADDR,
+		.flags = IOEX_FLAGS_TCA64XXA_FLAG_VER_TCA6424A }
+};
+
 #endif /* SECTION_IS_RO */
diff --git a/board/servo_v4p1/board.h b/board/servo_v4p1/board.h
index 471dd93177..4debd67b49 100644
--- a/board/servo_v4p1/board.h
+++ b/board/servo_v4p1/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,6 @@
 /* Use Link-Time Optimizations to try to reduce the firmware code size */
 #define CONFIG_LTO
 
-#define CONFIG_BOARD_VERSION_CUSTOM
-
 /* 48 MHz SYSCLK clock frequency */
 #define CPU_CLOCK 48000000
 
@@ -23,6 +21,14 @@
 #define CHG 0
 #define DUT 1
 
+/*
+ * IO expanders I2C addresses and ports
+ */
+#define TCA6416A_PORT 1
+#define TCA6416A_ADDR 0x21
+#define TCA6424A_PORT 1
+#define TCA6424A_ADDR 0x23
+
 /*
  * Flash layout: we redefine the sections offsets and sizes as we want to
  * include a pstate region, and will use RO/RW regions of different sizes.
@@ -52,31 +58,30 @@
 
 #define CONFIG_RAM_BANK_SIZE CONFIG_RAM_SIZE
 
-
 #define CONFIG_FLASH_PSTATE
 #define CONFIG_FLASH_PSTATE_BANK
 
-#define CONFIG_SHAREDLIB_SIZE   0
+#define CONFIG_SHAREDLIB_SIZE 0
 
-#define CONFIG_RO_MEM_OFF       0
-#define CONFIG_RO_STORAGE_OFF   0
-#define CONFIG_RO_SIZE          (92*1024)
+#define CONFIG_RO_MEM_OFF 0
+#define CONFIG_RO_STORAGE_OFF 0
+#define CONFIG_RO_SIZE (92 * 1024)
 
-#define CONFIG_FW_PSTATE_OFF    (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
-#define CONFIG_FW_PSTATE_SIZE   CONFIG_FLASH_BANK_SIZE
+#define CONFIG_FW_PSTATE_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
+#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE
 
-#define CONFIG_RW_MEM_OFF       (CONFIG_FW_PSTATE_OFF + CONFIG_FW_PSTATE_SIZE)
-#define CONFIG_RW_STORAGE_OFF   0
-#define CONFIG_RW_SIZE          (CONFIG_FLASH_SIZE - \
-				(CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF))
+#define CONFIG_RW_MEM_OFF (CONFIG_FW_PSTATE_OFF + CONFIG_FW_PSTATE_SIZE)
+#define CONFIG_RW_STORAGE_OFF 0
+#define CONFIG_RW_SIZE \
+	(CONFIG_FLASH_SIZE_BYTES - (CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF))
 
-#define CONFIG_EC_PROTECTED_STORAGE_OFF         CONFIG_RO_MEM_OFF
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE        CONFIG_RO_SIZE
-#define CONFIG_EC_WRITABLE_STORAGE_OFF          CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE         CONFIG_RW_SIZE
+#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF
+#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE
+#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE
 
-#define CONFIG_WP_STORAGE_OFF           CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE          CONFIG_EC_PROTECTED_STORAGE_SIZE
+#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
+#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
 
 /* Enable USART1,3,4 and USB streams */
 #define CONFIG_STREAM_USART
@@ -85,8 +90,13 @@
 #define CONFIG_STREAM_USB
 #define CONFIG_CMD_USART_INFO
 
+/* The UART console is on USART1 (PA9/PA10) */
+#undef CONFIG_UART_CONSOLE
+#define CONFIG_UART_CONSOLE 1
+#undef CONFIG_UART_TX_DMA
+#undef CONFIG_UART_RX_DMA
+
 /* Optional features */
-#define CONFIG_STM_HWTIMER32
 #define CONFIG_HW_CRC
 #define CONFIG_PVD
 /*
@@ -94,7 +104,7 @@
  * STM32F072x8 Datasheet. PVD Threshold 1 corresponds to a
  * falling voltage threshold of min:2.09V, max:2.27V.
  */
-#define PVD_THRESHOLD     (1)
+#define PVD_THRESHOLD (1)
 
 /* USB Configuration */
 #define CONFIG_USB
@@ -113,27 +123,35 @@
 #define DEFAULT_MAC_ADDR "Uninitialized"
 
 /* USB interface indexes (use define rather than enum to expand them) */
-#define USB_IFACE_CONSOLE	0
-#define USB_IFACE_EMPTY		1
-#define USB_IFACE_I2C		2
-#define USB_IFACE_USART3_STREAM	3
-#define USB_IFACE_USART4_STREAM	4
-#define USB_IFACE_UPDATE	5
-#define USB_IFACE_COUNT		6
+#define USB_IFACE_CONSOLE 0
+#define USB_IFACE_EMPTY 1
+#define USB_IFACE_I2C 2
+#define USB_IFACE_USART3_STREAM 3
+#define USB_IFACE_USART4_STREAM 4
+#define USB_IFACE_UPDATE 5
+#define USB_IFACE_COUNT 6
 
 /* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL		0
-#define USB_EP_CONSOLE		1
-#define USB_EP_EMPTY		2
-#define USB_EP_I2C		3
-#define USB_EP_USART3_STREAM	4
-#define USB_EP_USART4_STREAM	5
-#define USB_EP_UPDATE		6
-#define USB_EP_COUNT		7
+#define USB_EP_CONTROL 0
+#define USB_EP_CONSOLE 1
+#define USB_EP_EMPTY 2
+#define USB_EP_I2C 3
+#define USB_EP_USART3_STREAM 4
+#define USB_EP_USART4_STREAM 5
+#define USB_EP_UPDATE 6
+#define USB_EP_COUNT 7
 
 /* Enable console recasting of GPIO type. */
 #define CONFIG_CMD_GPIO_EXTENDED
 
+/* Enable I/O expander */
+#ifdef SECTION_IS_RO
+#define CONFIG_IO_EXPANDER
+#define CONFIG_IO_EXPANDER_SUPPORT_GET_PORT
+#define CONFIG_IO_EXPANDER_TCA64XXA
+#define CONFIG_IO_EXPANDER_PORT_COUNT 2
+#endif
+
 /* This is not actually an EC so disable some features. */
 #undef CONFIG_WATCHDOG_HELP
 #undef CONFIG_LID_SWITCH
@@ -157,12 +175,12 @@
 /* Enable control of I2C over USB */
 #define CONFIG_USB_I2C
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_CONTROLLER
 #define I2C_PORT_MASTER 1
 
 /* PD features */
 #define CONFIG_ADC
-#undef  CONFIG_ADC_WATCHDOG
+#undef CONFIG_ADC_WATCHDOG
 #define CONFIG_BOARD_PRE_INIT
 /*
  * If task profiling is enabled then the rx falling edge detection interrupts
@@ -173,9 +191,11 @@
 #define CONFIG_USB_PD_PORT_MAX_COUNT 2
 
 #ifdef SECTION_IS_RO
+#define CONFIG_USB_HUB_GL3590
 #define CONFIG_INA231
 #define CONFIG_CHARGE_MANAGER
-#undef  CONFIG_CHARGE_MANAGER_SAFE_MODE
+#undef CONFIG_CHARGE_MANAGER_SAFE_MODE
+#define CONFIG_USB_MUX_TUSB1064
 #define CONFIG_USB_POWER_DELIVERY
 #define CONFIG_USB_PD_TCPMV1
 #define CONFIG_CMD_PD
@@ -186,32 +206,45 @@
 #define CONFIG_USB_PD_TCPC
 #define CONFIG_USB_PD_TCPM_STUB
 #undef CONFIG_USB_PD_PULLUP
+/* Default pull-up should not be Rp3a0 due to Cr50 */
 #define CONFIG_USB_PD_PULLUP TYPEC_RP_USB
 #define CONFIG_USB_PD_VBUS_MEASURE_NOT_PRESENT
+#define CONFIG_USB_PD_ONLY_FIXED_PDOS
 #define CONFIG_USB_PD_ALT_MODE
+#define CONFIG_USBC_SS_MUX
+#define CONFIG_USBC_SS_MUX_UFP_ONLY
 
 /* Don't automatically change roles */
 #undef CONFIG_USB_PD_INITIAL_DRP_STATE
 #define CONFIG_USB_PD_INITIAL_DRP_STATE PD_DRP_FORCE_SINK
 
 /* Variable-current Rp no connect and Ra attach macros */
-#define CC_NC(port, cc, sel)  (pd_tcpc_cc_nc(port, cc, sel))
-#define CC_RA(port, cc, sel)  (pd_tcpc_cc_ra(port, cc, sel))
+#define CC_NC(port, cc, sel) (pd_tcpc_cc_nc(port, cc, sel))
+#define CC_RA(port, cc, sel) (pd_tcpc_cc_ra(port, cc, sel))
 
 /*
- * TODO(crosbug.com/p/60792): The delay values are currently just place holders
- * and the delay will need to be relative to the circuitry that allows VBUS to
- * be supplied to the DUT port from the CHG port.
+ * These power-supply timing values are now set towards maximum spec limit,
+ * to give the upstream charger the maximum time to respond.
+ *
+ * Currently tuned with the Apple 96W adapter.
+ * TODO: Change to EVENT-based PS_RDY notification (b/214216304)
  */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  50000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY 50000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY (121 * MSEC)
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY (461 * MSEC)
 
 /* Define typical operating power and max power */
 #define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       60000
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_VOLTAGE_MV     20000
+#define PD_MAX_POWER_MW 100000
+#define PD_MAX_CURRENT_MA 5000
+#define PD_MAX_VOLTAGE_MV 20000
+
+/* Add the raw option to the i2c_xfer command */
+#define CONFIG_CMD_I2C_XFER_RAW
+
+/* Enable command for managing host hub */
+#define CONFIG_CMD_GL3590
 #else
+#undef CONFIG_CMD_I2C_XFER
 #undef CONFIG_USB_POWER_DELIVERY
 #endif /* SECTION_IS_RO */
 
@@ -231,8 +264,7 @@
 
 /* Timer selection */
 #define TIM_CLOCK32 2
-#define TIM_ADC     3
-
+#define TIM_ADC 3
 
 #include "gpio_signal.h"
 
@@ -251,7 +283,6 @@ enum usb_strings {
 	USB_STR_COUNT
 };
 
-
 /* ADC signal */
 enum adc_channel {
 	ADC_CHG_CC1_PD,
@@ -265,6 +296,14 @@ enum adc_channel {
 	ADC_CH_COUNT
 };
 
+/* Servo V4.1 Board ID mappings */
+enum servo_board_id {
+	BOARD_ID_UNSET = -1,
+	BOARD_ID_REV0 = 0, /* Proto */
+	BOARD_ID_REV1 = 1, /* EVT */
+	BOARD_ID_REV2 = 2, /* DVT */
+};
+
 /**
  * Compare cc_voltage to disconnect threshold
  *
diff --git a/board/servo_v4p1/build.mk b/board/servo_v4p1/build.mk
index a8d22ccbc3..c1e8db9cd8 100644
--- a/board/servo_v4p1/build.mk
+++ b/board/servo_v4p1/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -14,10 +14,9 @@ CHIP_VARIANT:=stm32f07x
 test-list-y=
 
 # These files are compiled into RO and RW
-board-y=board.o tca6416a.o tca6424a.o
+board-y=board.o
 board-y+=ioexpanders.o
 board-y+=dacs.o
-board-y+=tusb1064.o
 board-y+=pi3usb9201.o
 
 # These files are compiled into RO only
diff --git a/board/servo_v4p1/ccd_measure_sbu.c b/board/servo_v4p1/ccd_measure_sbu.c
index b9c9680cc9..41d53ab597 100644
--- a/board/servo_v4p1/ccd_measure_sbu.c
+++ b/board/servo_v4p1/ccd_measure_sbu.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,8 @@
 #include "ioexpanders.h"
 #include "timer.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
 /*
  * Define voltage thresholds for SBU USB detection.
@@ -20,15 +20,15 @@
  * Max observed USB low across sampled systems: 666mV
  * Min observed USB high across sampled systems: 3026mV
  */
-#define GND_MAX_MV      700
-#define USB_HIGH_MV     2500
-#define SBU_DIRECT      0
-#define SBU_FLIP        1
+#define GND_MAX_MV 700
+#define USB_HIGH_MV 2500
+#define SBU_DIRECT 0
+#define SBU_FLIP 1
 
-#define MODE_SBU_DISCONNECT     0
-#define MODE_SBU_CONNECT        1
-#define MODE_SBU_FLIP           2
-#define MODE_SBU_OTHER          3
+#define MODE_SBU_DISCONNECT 0
+#define MODE_SBU_CONNECT 1
+#define MODE_SBU_FLIP 2
+#define MODE_SBU_OTHER 3
 
 static void ccd_measure_sbu(void);
 DECLARE_DEFERRED(ccd_measure_sbu);
diff --git a/board/servo_v4p1/ccd_measure_sbu.h b/board/servo_v4p1/ccd_measure_sbu.h
index 0dd1ce0de7..8635f892a4 100644
--- a/board/servo_v4p1/ccd_measure_sbu.h
+++ b/board/servo_v4p1/ccd_measure_sbu.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/servo_v4p1/chg_control.c b/board/servo_v4p1/chg_control.c
index cddd8efc69..76f3dc9649 100644
--- a/board/servo_v4p1/chg_control.c
+++ b/board/servo_v4p1/chg_control.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,8 +8,9 @@
 #include "ioexpanders.h"
 #include "registers.h"
 #include "timer.h"
+#include "usb_pd.h"
 
-#define CHG_P5V_POWER  0
+#define CHG_P5V_POWER 0
 #define CHG_VBUS_POWER 1
 
 void chg_reset(void)
@@ -20,7 +21,8 @@ void chg_reset(void)
 	/* Disconnect CHG CC1(Rd) and CC2(Rd) */
 	chg_attach_cc_rds(0);
 
-	msleep(100);
+	/* Give time for CHG to detach, use tErrorRecovery. */
+	msleep(PD_T_ERROR_RECOVERY);
 
 	/* Connect CHG CC1(Rd) and CC2(Rd) to detect charger */
 	chg_attach_cc_rds(1);
@@ -53,9 +55,11 @@ void chg_attach_cc_rds(bool en)
 		 * Configure USB_CHG_CC1_MCU and USB_CHG_CC2_MCU as
 		 * ANALOG input
 		 */
-		STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
-			| (3 << (2*2)) | /* PA2 in ANALOG mode */
-			  (3 << (2*4))); /* PA4 in ANALOG mode */
+		STM32_GPIO_MODER(GPIO_A) =
+			(STM32_GPIO_MODER(GPIO_A) | (3 << (2 * 2)) | /* PA2 in
+									ANALOG
+									mode */
+			 (3 << (2 * 4))); /* PA4 in ANALOG mode */
 	} else {
 		/*
 		 * Configure USB_CHG_CC1_MCU and USB_CHG_CC2_MCU as GPIO and
@@ -69,10 +73,12 @@ void chg_attach_cc_rds(bool en)
 		gpio_set_level(GPIO_USB_CHG_CC2_MCU, 1);
 
 		/* Disable Analog mode and Enable GPO */
-		STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
-			& ~(3 << (2*2) | /* PA2 disable ADC */
-			    3 << (2*4))) /* PA4 disable ADC */
-			|  (1 << (2*2) | /* Set as GPO */
-			    1 << (2*4)); /* Set as GPO */
+		STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) &
+					    ~(3 << (2 * 2) | /* PA2 disable ADC
+							      */
+					      3 << (2 * 4))) /* PA4 disable ADC
+							      */
+					   | (1 << (2 * 2) | /* Set as GPO */
+					      1 << (2 * 4)); /* Set as GPO */
 	}
 }
diff --git a/board/servo_v4p1/chg_control.h b/board/servo_v4p1/chg_control.h
index 8b81708ccc..91e3601ac8 100644
--- a/board/servo_v4p1/chg_control.h
+++ b/board/servo_v4p1/chg_control.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,11 +8,7 @@
 
 #include <stdbool.h>
 
-enum chg_cc_t {
-	CHG_OPEN,
-	CHG_CC1,
-	CHG_CC2
-};
+enum chg_cc_t { CHG_OPEN, CHG_CC1, CHG_CC2 };
 
 enum chg_power_select_t {
 	CHG_POWER_OFF,
diff --git a/board/servo_v4p1/dacs.c b/board/servo_v4p1/dacs.c
index b5c62bb438..355e27684b 100644
--- a/board/servo_v4p1/dacs.c
+++ b/board/servo_v4p1/dacs.c
@@ -1,8 +1,9 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "console.h"
 #include "dacs.h"
 #include "i2c.h"
 #include "ioexpanders.h"
@@ -13,17 +14,17 @@
 #define CC1_DAC_ADDR 0x48
 #define CC2_DAC_ADDR 0x49
 
-#define REG_NOOP    0
-#define REG_DEVID   1
-#define REG_SYNC    2
-#define REG_CONFIG  3
-#define REG_GAIN    4
+#define REG_NOOP 0
+#define REG_DEVID 1
+#define REG_SYNC 2
+#define REG_CONFIG 3
+#define REG_GAIN 4
 #define REG_TRIGGER 5
-#define REG_STATUS  7
-#define REG_DAC     8
+#define REG_STATUS 7
+#define REG_DAC 8
 
-#define DAC1	BIT(0)
-#define DAC2	BIT(1)
+#define DAC1 BIT(0)
+#define DAC2 BIT(1)
 
 static uint8_t dac_enabled;
 
@@ -101,7 +102,8 @@ int write_dac(enum dac_t dac, uint16_t value)
 	return EC_SUCCESS;
 }
 
-static int cmd_cc_dac(int argc, char *argv[])
+#ifdef SECTION_IS_RO
+static int cmd_cc_dac(int argc, const char *argv[])
 {
 	uint8_t dac;
 	uint64_t mv;
@@ -133,6 +135,6 @@ static int cmd_cc_dac(int argc, char *argv[])
 	}
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(cc_dac, cmd_cc_dac,
-			"dac <\"on\"|\"off\"|mv>",
+DECLARE_CONSOLE_COMMAND(cc_dac, cmd_cc_dac, "dac <\"on\"|\"off\"|mv>",
 			"Set Servo v4.1 CC dacs");
+#endif
diff --git a/board/servo_v4p1/dacs.h b/board/servo_v4p1/dacs.h
index bd0ecd67da..4b2028c648 100644
--- a/board/servo_v4p1/dacs.h
+++ b/board/servo_v4p1/dacs.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/servo_v4p1/ec.tasklist b/board/servo_v4p1/ec.tasklist
index 3004799adf..6c9abf1c07 100644
--- a/board/servo_v4p1/ec.tasklist
+++ b/board/servo_v4p1/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,8 +7,8 @@
  * See CONFIG_TASK_LIST in config.h for details.
  */
 #define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS,   hook_task,    NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0,   pd_task,      NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1,   pd_task,      NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C2,   snk_task,     NULL, VENTI_TASK_STACK_SIZE)
+	TASK_ALWAYS(HOOKS,    hook_task,    NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE,  console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS_RO(PD_C0, pd_task,      NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS_RO(PD_C1, pd_task,      NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS_RO(PD_C2, snk_task,     NULL, VENTI_TASK_STACK_SIZE)
diff --git a/board/servo_v4p1/fusb302b.c b/board/servo_v4p1/fusb302b.c
index fabb5b80ad..49959f1d65 100644
--- a/board/servo_v4p1/fusb302b.c
+++ b/board/servo_v4p1/fusb302b.c
@@ -1,17 +1,17 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include "i2c.h"
 #include "fusb302b.h"
 #include "gpio.h"
 #include "hooks.h"
+#include "i2c.h"
 #include "ioexpanders.h"
-#include "util.h"
 #include "task.h"
 #include "time.h"
 #include "usb_pd.h"
+#include "util.h"
 
 static int port;
 static int status0;
@@ -21,12 +21,12 @@ static struct mutex measure_lock;
 
 static int tcpc_write(int reg, int val)
 {
-	return i2c_write8(port, FUSB302_I2C_SLAVE_ADDR_FLAGS, reg, val);
+	return i2c_write8(port, FUSB302_I2C_ADDR_FLAGS, reg, val);
 }
 
 static int tcpc_read(int reg, int *val)
 {
-	return i2c_read8(port, FUSB302_I2C_SLAVE_ADDR_FLAGS, reg, val);
+	return i2c_read8(port, FUSB302_I2C_ADDR_FLAGS, reg, val);
 }
 
 int init_fusb302b(int p)
@@ -72,7 +72,6 @@ int init_fusb302b(int p)
 	if (ret)
 		return ret;
 
-
 	ret = tcpc_read(TCPC_REG_INTERRUPTA, &interrupta);
 	if (ret)
 		return ret;
@@ -159,7 +158,6 @@ int get_cc(int *cc1, int *cc2)
 	else
 		orig_meas_cc2 = 0;
 
-
 	/* Disable CC2 measurement switch, enable CC1 measurement switch */
 	reg &= ~TCPC_REG_SWITCHES0_MEAS_CC2;
 	reg |= TCPC_REG_SWITCHES0_MEAS_CC1;
diff --git a/board/servo_v4p1/fusb302b.h b/board/servo_v4p1/fusb302b.h
index eddc97b7ca..cebf5409f5 100644
--- a/board/servo_v4p1/fusb302b.h
+++ b/board/servo_v4p1/fusb302b.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,183 +12,183 @@
 #define FUSB302_DEVID_302A 0x08
 #define FUSB302_DEVID_302B 0x09
 
-/* I2C slave address varies by part number */
+/* I2C address varies by part number */
 /* FUSB302BUCX / FUSB302BMPX */
-#define FUSB302_I2C_SLAVE_ADDR_FLAGS 0x22
+#define FUSB302_I2C_ADDR_FLAGS 0x22
 /* FUSB302B01MPX */
-#define FUSB302_I2C_SLAVE_ADDR_B01_FLAGS 0x23
+#define FUSB302_I2C_ADDR_B01_FLAGS 0x23
 /* FUSB302B10MPX */
-#define FUSB302_I2C_SLAVE_ADDR_B10_FLAGS 0x24
+#define FUSB302_I2C_ADDR_B10_FLAGS 0x24
 /* FUSB302B11MPX */
-#define FUSB302_I2C_SLAVE_ADDR_B11_FLAGS 0x25
-
-#define TCPC_REG_DEVICE_ID	0x01
-
-#define TCPC_REG_SWITCHES0	0x02
-#define TCPC_REG_SWITCHES0_CC2_PU_EN	(1<<7)
-#define TCPC_REG_SWITCHES0_CC1_PU_EN	(1<<6)
-#define TCPC_REG_SWITCHES0_VCONN_CC2	(1<<5)
-#define TCPC_REG_SWITCHES0_VCONN_CC1	(1<<4)
-#define TCPC_REG_SWITCHES0_MEAS_CC2	(1<<3)
-#define TCPC_REG_SWITCHES0_MEAS_CC1	(1<<2)
-#define TCPC_REG_SWITCHES0_CC2_PD_EN	(1<<1)
-#define TCPC_REG_SWITCHES0_CC1_PD_EN	(1<<0)
-
-#define TCPC_REG_SWITCHES1	0x03
-#define TCPC_REG_SWITCHES1_POWERROLE	(1<<7)
-#define TCPC_REG_SWITCHES1_SPECREV1	(1<<6)
-#define TCPC_REG_SWITCHES1_SPECREV0	(1<<5)
-#define TCPC_REG_SWITCHES1_DATAROLE	(1<<4)
-#define TCPC_REG_SWITCHES1_AUTO_GCRC	(1<<2)
-#define TCPC_REG_SWITCHES1_TXCC2_EN	(1<<1)
-#define TCPC_REG_SWITCHES1_TXCC1_EN	(1<<0)
-
-#define TCPC_REG_MEASURE	0x04
-#define TCPC_REG_MEASURE_MDAC_MASK	0x3F
-#define TCPC_REG_MEASURE_VBUS		(1<<6)
+#define FUSB302_I2C_ADDR_B11_FLAGS 0x25
+
+#define TCPC_REG_DEVICE_ID 0x01
+
+#define TCPC_REG_SWITCHES0 0x02
+#define TCPC_REG_SWITCHES0_CC2_PU_EN (1 << 7)
+#define TCPC_REG_SWITCHES0_CC1_PU_EN (1 << 6)
+#define TCPC_REG_SWITCHES0_VCONN_CC2 (1 << 5)
+#define TCPC_REG_SWITCHES0_VCONN_CC1 (1 << 4)
+#define TCPC_REG_SWITCHES0_MEAS_CC2 (1 << 3)
+#define TCPC_REG_SWITCHES0_MEAS_CC1 (1 << 2)
+#define TCPC_REG_SWITCHES0_CC2_PD_EN (1 << 1)
+#define TCPC_REG_SWITCHES0_CC1_PD_EN (1 << 0)
+
+#define TCPC_REG_SWITCHES1 0x03
+#define TCPC_REG_SWITCHES1_POWERROLE (1 << 7)
+#define TCPC_REG_SWITCHES1_SPECREV1 (1 << 6)
+#define TCPC_REG_SWITCHES1_SPECREV0 (1 << 5)
+#define TCPC_REG_SWITCHES1_DATAROLE (1 << 4)
+#define TCPC_REG_SWITCHES1_AUTO_GCRC (1 << 2)
+#define TCPC_REG_SWITCHES1_TXCC2_EN (1 << 1)
+#define TCPC_REG_SWITCHES1_TXCC1_EN (1 << 0)
+
+#define TCPC_REG_MEASURE 0x04
+#define TCPC_REG_MEASURE_MDAC_MASK 0x3F
+#define TCPC_REG_MEASURE_VBUS (1 << 6)
 /*
  * MDAC reference voltage step size is 42 mV. Round our thresholds to reduce
  * maximum error, which also matches suggested thresholds in datasheet
  * (Table 3. Host Interrupt Summary).
  */
-#define TCPC_REG_MEASURE_MDAC_MV(mv)	(DIV_ROUND_NEAREST((mv), 42) & 0x3f)
-
-#define TCPC_REG_CONTROL0	0x06
-#define TCPC_REG_CONTROL0_TX_FLUSH	(1<<6)
-#define TCPC_REG_CONTROL0_INT_MASK	(1<<5)
-#define TCPC_REG_CONTROL0_HOST_CUR_MASK (3<<2)
-#define TCPC_REG_CONTROL0_HOST_CUR_3A0  (3<<2)
-#define TCPC_REG_CONTROL0_HOST_CUR_1A5  (2<<2)
-#define TCPC_REG_CONTROL0_HOST_CUR_USB  (1<<2)
-#define TCPC_REG_CONTROL0_TX_START	(1<<0)
-
-#define TCPC_REG_CONTROL1	0x07
-#define TCPC_REG_CONTROL1_ENSOP2DB	(1<<6)
-#define TCPC_REG_CONTROL1_ENSOP1DB	(1<<5)
-#define TCPC_REG_CONTROL1_BIST_MODE2	(1<<4)
-#define TCPC_REG_CONTROL1_RX_FLUSH	(1<<2)
-#define TCPC_REG_CONTROL1_ENSOP2	(1<<1)
-#define TCPC_REG_CONTROL1_ENSOP1	(1<<0)
-
-#define TCPC_REG_CONTROL2	0x08
+#define TCPC_REG_MEASURE_MDAC_MV(mv) (DIV_ROUND_NEAREST((mv), 42) & 0x3f)
+
+#define TCPC_REG_CONTROL0 0x06
+#define TCPC_REG_CONTROL0_TX_FLUSH (1 << 6)
+#define TCPC_REG_CONTROL0_INT_MASK (1 << 5)
+#define TCPC_REG_CONTROL0_HOST_CUR_MASK (3 << 2)
+#define TCPC_REG_CONTROL0_HOST_CUR_3A0 (3 << 2)
+#define TCPC_REG_CONTROL0_HOST_CUR_1A5 (2 << 2)
+#define TCPC_REG_CONTROL0_HOST_CUR_USB (1 << 2)
+#define TCPC_REG_CONTROL0_TX_START (1 << 0)
+
+#define TCPC_REG_CONTROL1 0x07
+#define TCPC_REG_CONTROL1_ENSOP2DB (1 << 6)
+#define TCPC_REG_CONTROL1_ENSOP1DB (1 << 5)
+#define TCPC_REG_CONTROL1_BIST_MODE2 (1 << 4)
+#define TCPC_REG_CONTROL1_RX_FLUSH (1 << 2)
+#define TCPC_REG_CONTROL1_ENSOP2 (1 << 1)
+#define TCPC_REG_CONTROL1_ENSOP1 (1 << 0)
+
+#define TCPC_REG_CONTROL2 0x08
 /* two-bit field, valid values below */
-#define TCPC_REG_CONTROL2_MODE_MASK	(0x3<<TCPC_REG_CONTROL2_MODE_POS)
-#define TCPC_REG_CONTROL2_MODE_DFP	(0x3)
-#define TCPC_REG_CONTROL2_MODE_UFP	(0x2)
-#define TCPC_REG_CONTROL2_MODE_DRP	(0x1)
-#define TCPC_REG_CONTROL2_MODE_POS	(1)
-#define TCPC_REG_CONTROL2_TOGGLE	(1<<0)
-
-#define TCPC_REG_CONTROL3	0x09
-#define TCPC_REG_CONTROL3_SEND_HARDRESET	(1<<6)
-#define TCPC_REG_CONTROL3_BIST_TMODE		(1<<5) /* 302B Only */
-#define TCPC_REG_CONTROL3_AUTO_HARDRESET	(1<<4)
-#define TCPC_REG_CONTROL3_AUTO_SOFTRESET	(1<<3)
+#define TCPC_REG_CONTROL2_MODE_MASK (0x3 << TCPC_REG_CONTROL2_MODE_POS)
+#define TCPC_REG_CONTROL2_MODE_DFP (0x3)
+#define TCPC_REG_CONTROL2_MODE_UFP (0x2)
+#define TCPC_REG_CONTROL2_MODE_DRP (0x1)
+#define TCPC_REG_CONTROL2_MODE_POS (1)
+#define TCPC_REG_CONTROL2_TOGGLE (1 << 0)
+
+#define TCPC_REG_CONTROL3 0x09
+#define TCPC_REG_CONTROL3_SEND_HARDRESET (1 << 6)
+#define TCPC_REG_CONTROL3_BIST_TMODE (1 << 5) /* 302B Only */
+#define TCPC_REG_CONTROL3_AUTO_HARDRESET (1 << 4)
+#define TCPC_REG_CONTROL3_AUTO_SOFTRESET (1 << 3)
 /* two-bit field */
-#define TCPC_REG_CONTROL3_N_RETRIES		(1<<1)
-#define TCPC_REG_CONTROL3_N_RETRIES_POS		(1)
-#define TCPC_REG_CONTROL3_N_RETRIES_SIZE	(2)
-#define TCPC_REG_CONTROL3_AUTO_RETRY		(1<<0)
-
-#define TCPC_REG_MASK		0x0A
-#define TCPC_REG_MASK_VBUSOK		(1<<7)
-#define TCPC_REG_MASK_ACTIVITY		(1<<6)
-#define TCPC_REG_MASK_COMP_CHNG		(1<<5)
-#define TCPC_REG_MASK_CRC_CHK		(1<<4)
-#define TCPC_REG_MASK_ALERT		(1<<3)
-#define TCPC_REG_MASK_WAKE		(1<<2)
-#define TCPC_REG_MASK_COLLISION		(1<<1)
-#define TCPC_REG_MASK_BC_LVL		(1<<0)
-
-#define TCPC_REG_POWER		0x0B
-#define TCPC_REG_POWER_PWR		(1<<0)	/* four-bit field */
-#define TCPC_REG_POWER_PWR_LOW		0x1 /* Bandgap + Wake circuitry */
-#define TCPC_REG_POWER_PWR_MEDIUM	0x3 /* LOW + Receiver + Current refs */
-#define TCPC_REG_POWER_PWR_HIGH		0x7 /* MEDIUM + Measure block */
-#define TCPC_REG_POWER_PWR_ALL		0xF /* HIGH + Internal Oscillator */
-
-#define TCPC_REG_RESET		0x0C
-#define TCPC_REG_RESET_PD_RESET		(1<<1)
-#define TCPC_REG_RESET_SW_RESET		(1<<0)
-
-#define TCPC_REG_MASKA		0x0E
-#define TCPC_REG_MASKA_OCP_TEMP		(1<<7)
-#define TCPC_REG_MASKA_TOGDONE		(1<<6)
-#define TCPC_REG_MASKA_SOFTFAIL		(1<<5)
-#define TCPC_REG_MASKA_RETRYFAIL	(1<<4)
-#define TCPC_REG_MASKA_HARDSENT		(1<<3)
-#define TCPC_REG_MASKA_TX_SUCCESS	(1<<2)
-#define TCPC_REG_MASKA_SOFTRESET	(1<<1)
-#define TCPC_REG_MASKA_HARDRESET	(1<<0)
-
-#define TCPC_REG_MASKB		0x0F
-#define TCPC_REG_MASKB_GCRCSENT		(1<<0)
-
-#define TCPC_REG_STATUS0A	0x3C
-#define TCPC_REG_STATUS0A_SOFTFAIL	(1<<5)
-#define TCPC_REG_STATUS0A_RETRYFAIL	(1<<4)
-#define TCPC_REG_STATUS0A_POWER		(1<<2) /* two-bit field */
-#define TCPC_REG_STATUS0A_RX_SOFT_RESET	(1<<1)
-#define TCPC_REG_STATUS0A_RX_HARD_RESEt	(1<<0)
-
-#define TCPC_REG_STATUS1A	0x3D
+#define TCPC_REG_CONTROL3_N_RETRIES (1 << 1)
+#define TCPC_REG_CONTROL3_N_RETRIES_POS (1)
+#define TCPC_REG_CONTROL3_N_RETRIES_SIZE (2)
+#define TCPC_REG_CONTROL3_AUTO_RETRY (1 << 0)
+
+#define TCPC_REG_MASK 0x0A
+#define TCPC_REG_MASK_VBUSOK (1 << 7)
+#define TCPC_REG_MASK_ACTIVITY (1 << 6)
+#define TCPC_REG_MASK_COMP_CHNG (1 << 5)
+#define TCPC_REG_MASK_CRC_CHK (1 << 4)
+#define TCPC_REG_MASK_ALERT (1 << 3)
+#define TCPC_REG_MASK_WAKE (1 << 2)
+#define TCPC_REG_MASK_COLLISION (1 << 1)
+#define TCPC_REG_MASK_BC_LVL (1 << 0)
+
+#define TCPC_REG_POWER 0x0B
+#define TCPC_REG_POWER_PWR (1 << 0) /* four-bit field */
+#define TCPC_REG_POWER_PWR_LOW 0x1 /* Bandgap + Wake circuitry */
+#define TCPC_REG_POWER_PWR_MEDIUM 0x3 /* LOW + Receiver + Current refs */
+#define TCPC_REG_POWER_PWR_HIGH 0x7 /* MEDIUM + Measure block */
+#define TCPC_REG_POWER_PWR_ALL 0xF /* HIGH + Internal Oscillator */
+
+#define TCPC_REG_RESET 0x0C
+#define TCPC_REG_RESET_PD_RESET (1 << 1)
+#define TCPC_REG_RESET_SW_RESET (1 << 0)
+
+#define TCPC_REG_MASKA 0x0E
+#define TCPC_REG_MASKA_OCP_TEMP (1 << 7)
+#define TCPC_REG_MASKA_TOGDONE (1 << 6)
+#define TCPC_REG_MASKA_SOFTFAIL (1 << 5)
+#define TCPC_REG_MASKA_RETRYFAIL (1 << 4)
+#define TCPC_REG_MASKA_HARDSENT (1 << 3)
+#define TCPC_REG_MASKA_TX_SUCCESS (1 << 2)
+#define TCPC_REG_MASKA_SOFTRESET (1 << 1)
+#define TCPC_REG_MASKA_HARDRESET (1 << 0)
+
+#define TCPC_REG_MASKB 0x0F
+#define TCPC_REG_MASKB_GCRCSENT (1 << 0)
+
+#define TCPC_REG_STATUS0A 0x3C
+#define TCPC_REG_STATUS0A_SOFTFAIL (1 << 5)
+#define TCPC_REG_STATUS0A_RETRYFAIL (1 << 4)
+#define TCPC_REG_STATUS0A_POWER (1 << 2) /* two-bit field */
+#define TCPC_REG_STATUS0A_RX_SOFT_RESET (1 << 1)
+#define TCPC_REG_STATUS0A_RX_HARD_RESEt (1 << 0)
+
+#define TCPC_REG_STATUS1A 0x3D
 /* three-bit field, valid values below */
-#define TCPC_REG_STATUS1A_TOGSS		(1<<3)
-#define TCPC_REG_STATUS1A_TOGSS_RUNNING		0x0
-#define TCPC_REG_STATUS1A_TOGSS_SRC1		0x1
-#define TCPC_REG_STATUS1A_TOGSS_SRC2		0x2
-#define TCPC_REG_STATUS1A_TOGSS_SNK1		0x5
-#define TCPC_REG_STATUS1A_TOGSS_SNK2		0x6
-#define TCPC_REG_STATUS1A_TOGSS_AA		0x7
-#define TCPC_REG_STATUS1A_TOGSS_POS		(3)
-#define TCPC_REG_STATUS1A_TOGSS_MASK		(0x7)
-
-#define TCPC_REG_STATUS1A_RXSOP2DB	(1<<2)
-#define TCPC_REG_STATUS1A_RXSOP1DB	(1<<1)
-#define TCPC_REG_STATUS1A_RXSOP		(1<<0)
-
-#define TCPC_REG_INTERRUPTA	0x3E
-#define TCPC_REG_INTERRUPTA_OCP_TEMP	(1<<7)
-#define TCPC_REG_INTERRUPTA_TOGDONE	(1<<6)
-#define TCPC_REG_INTERRUPTA_SOFTFAIL	(1<<5)
-#define TCPC_REG_INTERRUPTA_RETRYFAIL	(1<<4)
-#define TCPC_REG_INTERRUPTA_HARDSENT	(1<<3)
-#define TCPC_REG_INTERRUPTA_TX_SUCCESS	(1<<2)
-#define TCPC_REG_INTERRUPTA_SOFTRESET	(1<<1)
-#define TCPC_REG_INTERRUPTA_HARDRESET	(1<<0)
-
-#define TCPC_REG_INTERRUPTB	0x3F
-#define TCPC_REG_INTERRUPTB_GCRCSENT		(1<<0)
-
-#define TCPC_REG_STATUS0	0x40
-#define TCPC_REG_STATUS0_VBUSOK		(1<<7)
-#define TCPC_REG_STATUS0_ACTIVITY	(1<<6)
-#define TCPC_REG_STATUS0_COMP		(1<<5)
-#define TCPC_REG_STATUS0_CRC_CHK	(1<<4)
-#define TCPC_REG_STATUS0_ALERT		(1<<3)
-#define TCPC_REG_STATUS0_WAKE		(1<<2)
-#define TCPC_REG_STATUS0_BC_LVL1	(1<<1) /* two-bit field */
-#define TCPC_REG_STATUS0_BC_LVL0	(1<<0) /* two-bit field */
-
-#define TCPC_REG_STATUS1	0x41
-#define TCPC_REG_STATUS1_RXSOP2		(1<<7)
-#define TCPC_REG_STATUS1_RXSOP1		(1<<6)
-#define TCPC_REG_STATUS1_RX_EMPTY	(1<<5)
-#define TCPC_REG_STATUS1_RX_FULL	(1<<4)
-#define TCPC_REG_STATUS1_TX_EMPTY	(1<<3)
-#define TCPC_REG_STATUS1_TX_FULL	(1<<2)
-
-#define TCPC_REG_INTERRUPT	0x42
-#define TCPC_REG_INTERRUPT_VBUSOK	(1<<7)
-#define TCPC_REG_INTERRUPT_ACTIVITY	(1<<6)
-#define TCPC_REG_INTERRUPT_COMP_CHNG	(1<<5)
-#define TCPC_REG_INTERRUPT_CRC_CHK	(1<<4)
-#define TCPC_REG_INTERRUPT_ALERT	(1<<3)
-#define TCPC_REG_INTERRUPT_WAKE		(1<<2)
-#define TCPC_REG_INTERRUPT_COLLISION	(1<<1)
-#define TCPC_REG_INTERRUPT_BC_LVL	(1<<0)
-
-#define TCPC_REG_FIFOS		0x43
+#define TCPC_REG_STATUS1A_TOGSS (1 << 3)
+#define TCPC_REG_STATUS1A_TOGSS_RUNNING 0x0
+#define TCPC_REG_STATUS1A_TOGSS_SRC1 0x1
+#define TCPC_REG_STATUS1A_TOGSS_SRC2 0x2
+#define TCPC_REG_STATUS1A_TOGSS_SNK1 0x5
+#define TCPC_REG_STATUS1A_TOGSS_SNK2 0x6
+#define TCPC_REG_STATUS1A_TOGSS_AA 0x7
+#define TCPC_REG_STATUS1A_TOGSS_POS (3)
+#define TCPC_REG_STATUS1A_TOGSS_MASK (0x7)
+
+#define TCPC_REG_STATUS1A_RXSOP2DB (1 << 2)
+#define TCPC_REG_STATUS1A_RXSOP1DB (1 << 1)
+#define TCPC_REG_STATUS1A_RXSOP (1 << 0)
+
+#define TCPC_REG_INTERRUPTA 0x3E
+#define TCPC_REG_INTERRUPTA_OCP_TEMP (1 << 7)
+#define TCPC_REG_INTERRUPTA_TOGDONE (1 << 6)
+#define TCPC_REG_INTERRUPTA_SOFTFAIL (1 << 5)
+#define TCPC_REG_INTERRUPTA_RETRYFAIL (1 << 4)
+#define TCPC_REG_INTERRUPTA_HARDSENT (1 << 3)
+#define TCPC_REG_INTERRUPTA_TX_SUCCESS (1 << 2)
+#define TCPC_REG_INTERRUPTA_SOFTRESET (1 << 1)
+#define TCPC_REG_INTERRUPTA_HARDRESET (1 << 0)
+
+#define TCPC_REG_INTERRUPTB 0x3F
+#define TCPC_REG_INTERRUPTB_GCRCSENT (1 << 0)
+
+#define TCPC_REG_STATUS0 0x40
+#define TCPC_REG_STATUS0_VBUSOK (1 << 7)
+#define TCPC_REG_STATUS0_ACTIVITY (1 << 6)
+#define TCPC_REG_STATUS0_COMP (1 << 5)
+#define TCPC_REG_STATUS0_CRC_CHK (1 << 4)
+#define TCPC_REG_STATUS0_ALERT (1 << 3)
+#define TCPC_REG_STATUS0_WAKE (1 << 2)
+#define TCPC_REG_STATUS0_BC_LVL1 (1 << 1) /* two-bit field */
+#define TCPC_REG_STATUS0_BC_LVL0 (1 << 0) /* two-bit field */
+
+#define TCPC_REG_STATUS1 0x41
+#define TCPC_REG_STATUS1_RXSOP2 (1 << 7)
+#define TCPC_REG_STATUS1_RXSOP1 (1 << 6)
+#define TCPC_REG_STATUS1_RX_EMPTY (1 << 5)
+#define TCPC_REG_STATUS1_RX_FULL (1 << 4)
+#define TCPC_REG_STATUS1_TX_EMPTY (1 << 3)
+#define TCPC_REG_STATUS1_TX_FULL (1 << 2)
+
+#define TCPC_REG_INTERRUPT 0x42
+#define TCPC_REG_INTERRUPT_VBUSOK (1 << 7)
+#define TCPC_REG_INTERRUPT_ACTIVITY (1 << 6)
+#define TCPC_REG_INTERRUPT_COMP_CHNG (1 << 5)
+#define TCPC_REG_INTERRUPT_CRC_CHK (1 << 4)
+#define TCPC_REG_INTERRUPT_ALERT (1 << 3)
+#define TCPC_REG_INTERRUPT_WAKE (1 << 2)
+#define TCPC_REG_INTERRUPT_COLLISION (1 << 1)
+#define TCPC_REG_INTERRUPT_BC_LVL (1 << 0)
+
+#define TCPC_REG_FIFOS 0x43
 
 /* Tokens defined for the FUSB302 TX FIFO */
 enum fusb302_txfifo_tokens {
diff --git a/board/servo_v4p1/gpio.inc b/board/servo_v4p1/gpio.inc
index b42bde495b..fe631aca80 100644
--- a/board/servo_v4p1/gpio.inc
+++ b/board/servo_v4p1/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,7 +12,7 @@ GPIO_INT(STM_FAULT_IRQ_L,	PIN(A, 8),  GPIO_INT_FALLING, tca_evt)
 GPIO_INT(DP_HPD,		PIN(A, 15), GPIO_INT_BOTH, dp_evt)
 GPIO_INT(CHGSRV_TCPC_INT_ODL,	PIN(C, 0),  GPIO_INT_FALLING, tcpc_evt)
 GPIO_INT(USBH_I2C_BUSY_INT,	PIN(C, 9),  GPIO_INT_FALLING, hub_evt)
-GPIO_INT(BC12_INT_ODL,		PIN(F, 1),  GPIO_INT_FALLING, bc12_evt)
+GPIO_INT(DUT_PWR_IRQ_ODL,	PIN(F, 1),  GPIO_INT_FALLING, dut_pwr_evt)
 #endif /* SECTION_IS_RO */
 
 /* Outputs */
@@ -65,6 +65,53 @@ GPIO(USB_DUT_TX_CLKIN,        PIN(B, 13), GPIO_INPUT)
 GPIO(MASTER_I2C_SCL,		PIN(B, 10), GPIO_INPUT)
 GPIO(MASTER_I2C_SDA,		PIN(B, 11), GPIO_INPUT)
 
+/* IOEX */
+#ifdef SECTION_IS_RO
+
+IOEX(SBU_UART_SEL, 		EXPIN(0, 0, 0), GPIO_OUT_LOW)
+IOEX(ATMEL_RESET_L, 		EXPIN(0, 0, 1), GPIO_OUT_LOW)
+IOEX(SBU_FLIP_SEL, 		EXPIN(0, 0, 2), GPIO_OUT_HIGH)
+IOEX(USB3_A0_MUX_SEL, 		EXPIN(0, 0, 3), GPIO_OUT_HIGH)
+IOEX(USB3_A0_MUX_EN_L, 		EXPIN(0, 0, 4), GPIO_OUT_LOW)
+IOEX(USB3_A0_PWR_EN, 		EXPIN(0, 0, 5), GPIO_OUT_LOW)
+IOEX(UART_18_SEL, 		EXPIN(0, 0, 6), GPIO_OUT_LOW)
+IOEX(USERVO_POWER_EN, 		EXPIN(0, 0, 7), GPIO_OUT_LOW)
+IOEX(USERVO_FASTBOOT_MUX_SEL, 	EXPIN(0, 1, 0), GPIO_OUT_LOW)
+IOEX(USB3_A1_PWR_EN, 		EXPIN(0, 1, 1), GPIO_OUT_LOW)
+IOEX(USB3_A1_MUX_SEL, 		EXPIN(0, 1, 2), GPIO_OUT_HIGH)
+IOEX(BOARD_ID_DET0, 		EXPIN(0, 1, 3), GPIO_INPUT)
+IOEX(BOARD_ID_DET1, 		EXPIN(0, 1, 4), GPIO_INPUT)
+IOEX(BOARD_ID_DET2, 		EXPIN(0, 1, 5), GPIO_INPUT)
+IOEX(VBUS_DISCHRG_EN, 		EXPIN(0, 1, 6), GPIO_OUT_LOW)
+IOEX(DONGLE_DET, 		EXPIN(0, 1, 7), GPIO_INPUT)
+
+IOEX(EN_PP5000_ALT_3P3, 	EXPIN(1, 0, 0), GPIO_OUT_LOW)
+IOEX(EN_PP3300_ETH, 		EXPIN(1, 0, 1), GPIO_OUT_HIGH)
+IOEX(EN_PP3300_DP, 		EXPIN(1, 0, 2), GPIO_OUT_HIGH)
+IOEX(FAULT_CLEAR_CC, 		EXPIN(1, 0, 3), GPIO_OUT_LOW)
+IOEX(EN_VOUT_BUF_CC1, 		EXPIN(1, 0, 4), GPIO_OUT_LOW)
+IOEX(EN_VOUT_BUF_CC2, 		EXPIN(1, 0, 5), GPIO_OUT_LOW)
+IOEX(DUT_CHG_EN, 		EXPIN(1, 0, 6), GPIO_OUT_LOW)
+IOEX(HOST_OR_CHG_CTL, 		EXPIN(1, 0, 7), GPIO_OUT_LOW)
+IOEX(USERVO_FAULT_L, 		EXPIN(1, 1, 0), GPIO_INPUT)
+IOEX(USB3_A0_FAULT_L, 		EXPIN(1, 1, 1), GPIO_INPUT)
+IOEX(USB3_A1_FAULT_L, 		EXPIN(1, 1, 2), GPIO_INPUT)
+IOEX(USB_DUTCHG_FLT_ODL, 	EXPIN(1, 1, 3), GPIO_INPUT)
+IOEX(PP3300_DP_FAULT_L, 	EXPIN(1, 1, 4), GPIO_INPUT)
+IOEX(DAC_BUF1_LATCH_FAULT_L, 	EXPIN(1, 1, 5), GPIO_INPUT)
+IOEX(DAC_BUF2_LATCH_FAULT_L, 	EXPIN(1, 1, 6), GPIO_INPUT)
+IOEX(PP5000_SRC_SEL, 		EXPIN(1, 1, 7), GPIO_INPUT)
+IOEX(HOST_CHRG_DET, 		EXPIN(1, 2, 0), GPIO_INPUT)
+IOEX(USBH_PWRDN_L, 		EXPIN(1, 2, 1), GPIO_OUT_HIGH)
+IOEX(ATMEL_SS,			EXPIN(1, 2, 2), GPIO_INPUT)
+IOEX(ATMEL_SCLK,		EXPIN(1, 2, 3), GPIO_INPUT)
+IOEX(ATMEL_MOSI,		EXPIN(1, 2, 4), GPIO_INPUT)
+IOEX(ATMEL_MISO,		EXPIN(1, 2, 5), GPIO_INPUT)
+IOEX(SYS_PWR_IRQ_ODL, 		EXPIN(1, 2, 6), GPIO_INPUT)
+IOEX(TCA_GPIO_DBG_LED_K_ODL, 	EXPIN(1, 2, 7), GPIO_OUT_LOW)
+
+#endif
+
 /* Unimplemented signals since we are not an EC */
 UNIMPLEMENTED(ENTERING_RW)
 UNIMPLEMENTED(WP_L)
diff --git a/board/servo_v4p1/ina231s.c b/board/servo_v4p1/ina231s.c
index 3382686f3f..637a878ef7 100644
--- a/board/servo_v4p1/ina231s.c
+++ b/board/servo_v4p1/ina231s.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,9 +7,9 @@
 #include "ina2xx.h"
 #include "util.h"
 
-#define PP_DUT_IDX	0
-#define PP_CHG_IDX	1
-#define SR_CHG_IDX	2
+#define PP_DUT_IDX 0
+#define PP_CHG_IDX 1
+#define SR_CHG_IDX 2
 
 void init_ina231s(void)
 {
diff --git a/board/servo_v4p1/ina231s.h b/board/servo_v4p1/ina231s.h
index 9c3804e769..6f0828127b 100644
--- a/board/servo_v4p1/ina231s.h
+++ b/board/servo_v4p1/ina231s.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/servo_v4p1/ioexpanders.c b/board/servo_v4p1/ioexpanders.c
index 6617a8d30e..275804de89 100644
--- a/board/servo_v4p1/ioexpanders.c
+++ b/board/servo_v4p1/ioexpanders.c
@@ -1,163 +1,153 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "console.h"
 #include "hooks.h"
 #include "i2c.h"
+#include "ioexpander.h"
 #include "ioexpanders.h"
-#include "tca6416a.h"
-#include "tca6424a.h"
+
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 /******************************************************************************
  * Initialize IOExpanders.
  */
 
+#define PCAL6524HE_PORT TCA6424A_PORT
+#define PCAL6524HE_ADDR TCA6424A_ADDR
+#define PCAL6524HE_DEVICE_ID_ADDR 0x7c
+#define PCAL6524HE_DEVICE_ID_REG 0x46
+#define PCAL6524HE_DEVICE_ID0 0
+#define PCAL6524HE_DEVICE_ID1 0x08
+#define PCAL6524HE_DEVICE_ID2 0x30
+#define PCAL6524HE_INT_MASK_REG_PORT1 0x55
+#define PCAL6524HE_INT_MASK_REG_PORT2 0x56
+
+static enum servo_board_id board_id_val = BOARD_ID_UNSET;
+
+#ifdef SECTION_IS_RO
+
 static int dut_chg_en_state;
+static int bc12_charger;
 
 /* Enable all ioexpander outputs. */
 int init_ioexpanders(void)
 {
-	int ret;
-
-	/*
-	 * Init TCA6416A, PORT 0
-	 * NAME                      | DIR | Initial setting
-	 * -------------------------------------------------
-	 * BIT-0 (SBU_UART_SEL)      | O   | 0
-	 * BIT-1 (ATMEL_RESET_L)     | O   | 0
-	 * BIT-2 (SBU_FLIP_SEL)      | O   | 1
-	 * BIT-3 (USB3_A0_MUX_SEL)   | O   | 0
-	 * BIT-4 (USB3_A0_MUX_EN_L)  | O   | 0
-	 * BIT-5 (USB3_A0_PWR_EN)    | O   | 0
-	 * BIT-6 (UART_18_SEL)       | O   | 0
-	 * BIT-7 (USERVO_POWER_EN)   | O   | 0
-	 */
-	ret = tca6416a_write_byte(1, TCA6416A_OUT_PORT_0, 0x04);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	ret = tca6416a_write_byte(1, TCA6416A_DIR_PORT_0, 0x00);
-	if (ret != EC_SUCCESS)
-		return ret;
+	int fault, irqs;
+	uint8_t dat[3];
 
 	/*
-	 * Init TCA6416A, PORT 1
-	 * NAME                            | DIR | Initial setting
-	 * -------------------------------------------------------
-	 * BIT-0 (USERVO_FASTBOOT_MUX_SEL) | O   | 0
-	 * BIT-1 (USB3_A1_PWR_EN)          | O   | 0
-	 * BIT-2 (USB3_A1_MUX_SEL)         | O   | 0
-	 * BIT-3 (BOARD_ID)                | I   | x
-	 * BIT-4 (BOARD ID)                | I   | x
-	 * BIT-5 (BOARD_ID)                | I   | x
-	 * BIT-6 (CMUX_EN)                 | O   | 1
-	 * BIT-7 (DONGLE_DET)              | I   | x
+	 * Due to shortages of the TI TCA6424 device, the NXP PCAL6524HE
+	 * device has been selected as an alternative IOExpander. The two
+	 * parts are mostly compatible except for some additional initialization
+	 * of the PCAL6524HE.
+	 *
+	 * If the PCAL6524HE device is detected, the interrupt mask register for
+	 * port1 is set to 0 and the port2 is set to 0xbe.
 	 */
-	ret = tca6416a_write_byte(1, TCA6416A_OUT_PORT_1, 0x40);
-	if (ret != EC_SUCCESS)
-		return ret;
 
-	ret = tca6416a_write_byte(1, TCA6416A_DIR_PORT_1, 0xb8);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	/*
-	 * Init TCA6424A, PORT 0
-	 * NAME                      | DIR | Initial setting
-	 * -------------------------------------------------
-	 * BIT-0 (EN_PP5000_ALT_3P3) | O   | 0
-	 * BIT-1 (EN_PP3300_ETH)     | O   | 1
-	 * BIT-2 (EN_PP3300_DP)      | O   | 0
-	 * BIT-3 (FAULT_CLEAR_CC)    | O   | 0
-	 * BIT-4 (EN_VOUT_BUF_CC1)   | O   | 0
-	 * BIT-5 (EN_VOUT_BUF_CC2)   | O   | 0
-	 * BIT-6 (DUT_CHG_EN)        | O   | 0
-	 * BIT-7 (HOST_OR_CHG_CTL    | O   | 0
-	 */
-	ret = tca6424a_write_byte(1, TCA6424A_OUT_PORT_0, 0x02);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	ret = tca6424a_write_byte(1, TCA6424A_DIR_PORT_0, 0x00);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	/*
-	 * Init TCA6424A, PORT 1
-	 * NAME                           | DIR | Initial setting
-	 * ------------------------------------------------------
-	 * BIT-0 (USERVO_FAULT_L)         | I   | x
-	 * BIT-1 (USB3_A0_FAULT_L)        | I   | x
-	 * BIT-2 (USB3_A1_FAULT_L)        | I   | x
-	 * BIT-3 (USB_DUTCHG_FLT_ODL)     | I   | x
-	 * BIT-4 (PP3300_DP_FAULT_L)      | I   | x
-	 * BIT-5 (DAC_BUF1_LATCH_FAULT_L) | I   | x
-	 * BIT-6 (DAC_BUF2_LATCH_FAULT_L) | I   | x
-	 * BIT-7 (PP5000_SRC_SEL)         | I   | x
-	 */
-	ret = tca6424a_write_byte(1, TCA6424A_DIR_PORT_1, 0xff);
-	if (ret != EC_SUCCESS)
-		return ret;
+	/* Attempt to read the device id register of the PCAL6524HE device */
+	i2c_read_block(PCAL6524HE_PORT, PCAL6524HE_DEVICE_ID_ADDR,
+		       PCAL6524HE_DEVICE_ID_REG, dat, 3);
+
+	if (dat[2] == PCAL6524HE_DEVICE_ID2 &&
+	    dat[1] == PCAL6524HE_DEVICE_ID1 &&
+	    dat[0] == PCAL6524HE_DEVICE_ID0) {
+		ccprintf("Detected PCAL6524HE\n");
+		i2c_write8(PCAL6524HE_PORT, PCAL6524HE_ADDR,
+			   PCAL6524HE_INT_MASK_REG_PORT1, 0);
+		i2c_write8(PCAL6524HE_PORT, PCAL6524HE_ADDR,
+			   PCAL6524HE_INT_MASK_REG_PORT2, 0xbe);
+	} else {
+		ccprintf("Detected TCA6424A\n");
+	}
 
-	/*
-	 * Init TCA6424A, PORT 2
-	 * NAME                      | DIR | Initial setting
-	 * ------------------------------------------------
-	 * BIT-0 (VBUS_DISCHRG_EN)   | O   | 0
-	 * BIT-1 (USBH_PWRDN_L)      | O   | 1
-	 * BIT-2 (UNUSED)            | I   | x
-	 * BIT-3 (UNUSED)            | I   | x
-	 * BIT-4 (UNUSED)            | I   | x
-	 * BIT-5 (UNUSED)            | I   | x
-	 * BIT-6 (UNUSED)            | I   | x
-	 * BIT-7 (DBG_LED_K_ODL)     | O   | 0
-	 */
-	ret = tca6424a_write_byte(1, TCA6424A_OUT_PORT_2, 0x02);
-	if (ret != EC_SUCCESS)
-		return ret;
+	/* Clear any faults and other IRQs */
+	fault = read_faults();
+	irqs = read_irqs();
 
-	ret = tca6424a_write_byte(1, TCA6424A_DIR_PORT_2, 0x7c);
-	if (ret != EC_SUCCESS)
-		return ret;
+	if (!(fault & USB_DUTCHG_FLT_ODL)) {
+		CPRINTF("FAULT: Overcurrent on Charger or DUT CC/SBU lines\n");
+	}
 
-	/* Clear any faults */
-	read_faults();
+	if ((!!(irqs & HOST_CHRG_DET) != bc12_charger) &&
+	    (board_id_det() <= BOARD_ID_REV1)) {
+		CPRINTF("BC1.2 charger %s\n",
+			(irqs & HOST_CHRG_DET) ? "plugged" : "unplugged");
+		bc12_charger = !!(irqs & HOST_CHRG_DET);
+	}
 
 	return EC_SUCCESS;
 }
 
 static void ioexpanders_irq(void)
 {
-	int fault;
+	int fault, irqs;
 
 	fault = read_faults();
+	irqs = read_irqs();
 
-	if (!(fault & USERVO_FAULT_L))
-		ccprintf("FAULT: Microservo USB A port load switch\n");
+	if (!(fault & USERVO_FAULT_L)) {
+		ec_uservo_power_en(0);
+		CPRINTF("FAULT: Microservo USB A port load switch\n");
+	}
 
-	if (!(fault & USB3_A0_FAULT_L))
-		ccprintf("FAULT: USB3 A0 port load switch\n");
+	if (!(fault & USB3_A0_FAULT_L)) {
+		ec_usb3_a0_pwr_en(0);
+		CPRINTF("FAULT: USB3 A0 port load switch\n");
+	}
 
-	if (!(fault & USB3_A1_FAULT_L))
-		ccprintf("FAULT: USB3 A1 port load switch\n");
+	if (!(fault & USB3_A1_FAULT_L)) {
+		ec_usb3_a1_pwr_en(0);
+		CPRINTF("FAULT: USB3 A1 port load switch\n");
+	}
 
-	if (!(fault & USB_DUTCHG_FLT_ODL))
-		ccprintf("FAULT: Overcurrent on Charger or DUB CC/SBU lines\n");
+	if (!(fault & USB_DUTCHG_FLT_ODL)) {
+		CPRINTF("FAULT: Overcurrent on Charger or DUT CC/SBU lines\n");
+	}
 
-	if (!(fault & PP3300_DP_FAULT_L))
-		ccprintf("FAULT: Overcurrent on DisplayPort\n");
+	if (!(fault & PP3300_DP_FAULT_L)) {
+		CPRINTF("FAULT: Overcurrent on DisplayPort\n");
+	}
 
 	if (!(fault & DAC_BUF1_LATCH_FAULT_L)) {
-		ccprintf("FAULT: CC1 drive circuitry has exceeded thermal ");
-		ccprintf("limits or exceeded current limits. Power ");
-		ccprintf("off DAC0 to clear the fault\n");
+		CPRINTF("FAULT: CC1 drive circuitry has exceeded thermal "
+			"or current limits. The CC1 DAC has been disabled "
+			"and disconnected.\n");
+
+		en_vout_buf_cc1(0);
 	}
 
-	if (!(fault & DAC_BUF1_LATCH_FAULT_L)) {
-		ccprintf("FAULT: CC2 drive circuitry has exceeded thermal ");
-		ccprintf("limits or exceeded current limits. Power ");
-		ccprintf("off DAC1 to clear the fault\n");
+	if (!(fault & DAC_BUF2_LATCH_FAULT_L)) {
+		CPRINTF("FAULT: CC2 drive circuitry has exceeded thermal "
+			"or current limits. The CC2 DAC has been disabled "
+			"and disconnected.\n");
+
+		en_vout_buf_cc2(0);
+	}
+
+	/*
+	 * In case of both DACs' faults, we should clear them only after
+	 * disabling both DACs.
+	 */
+	if ((fault & (DAC_BUF1_LATCH_FAULT_L | DAC_BUF2_LATCH_FAULT_L)) !=
+	    (DAC_BUF1_LATCH_FAULT_L | DAC_BUF2_LATCH_FAULT_L)) {
+		fault_clear_cc(1);
+		fault_clear_cc(0);
+	}
+
+	if ((!!(irqs & HOST_CHRG_DET) != bc12_charger) &&
+	    (board_id_det() <= BOARD_ID_REV1)) {
+		CPRINTF("BC1.2 charger %s\n",
+			(irqs & HOST_CHRG_DET) ? "plugged" : "unplugged");
+		bc12_charger = !!(irqs & HOST_CHRG_DET);
+	}
+
+	if (!(irqs & SYS_PWR_IRQ_ODL)) {
+		CPRINTF("System full power threshold exceeded\n");
 	}
 }
 DECLARE_DEFERRED(ioexpanders_irq);
@@ -170,115 +160,124 @@ int irq_ioexpanders(void)
 
 inline int sbu_uart_sel(int en)
 {
-	return tca6416a_write_bit(1, TCA6416A_OUT_PORT_0, 0, en);
+	return ioex_set_level(IOEX_SBU_UART_SEL, en);
 }
 
 inline int atmel_reset_l(int en)
 {
-	return tca6416a_write_bit(1, TCA6416A_OUT_PORT_0, 1, en);
+	return ioex_set_level(IOEX_ATMEL_RESET_L, en);
 }
 
 inline int sbu_flip_sel(int en)
 {
-	return tca6416a_write_bit(1, TCA6416A_OUT_PORT_0, 2, en);
+	return ioex_set_level(IOEX_SBU_FLIP_SEL, en);
 }
 
 inline int usb3_a0_mux_sel(int en)
 {
-	return tca6416a_write_bit(1, TCA6416A_OUT_PORT_0, 3, en);
+	return ioex_set_level(IOEX_USB3_A0_MUX_SEL, en);
 }
 
 inline int usb3_a0_mux_en_l(int en)
 {
-	return tca6416a_write_bit(1, TCA6416A_OUT_PORT_0, 4, en);
+	return ioex_set_level(IOEX_USB3_A0_MUX_EN_L, en);
 }
 
-inline int usb3_a0_pwr_en(int en)
+inline int ec_usb3_a0_pwr_en(int en)
 {
-	return tca6416a_write_bit(1, TCA6416A_OUT_PORT_0, 5, en);
+	return ioex_set_level(IOEX_USB3_A0_PWR_EN, en);
 }
 
 inline int uart_18_sel(int en)
 {
-	return tca6416a_write_bit(1, TCA6416A_OUT_PORT_0, 6, en);
+	return ioex_set_level(IOEX_UART_18_SEL, en);
 }
 
-inline int uservo_power_en(int en)
+inline int ec_uservo_power_en(int en)
 {
-	return tca6416a_write_bit(1, TCA6416A_OUT_PORT_0, 7, en);
+	return ioex_set_level(IOEX_USERVO_POWER_EN, en);
 }
 
 inline int uservo_fastboot_mux_sel(enum uservo_fastboot_mux_sel_t sel)
 {
-	return tca6416a_write_bit(1, TCA6416A_OUT_PORT_1, 0, sel);
+	return ioex_set_level(IOEX_USERVO_FASTBOOT_MUX_SEL, (int)sel);
 }
 
-inline int usb3_a1_pwr_en(int en)
+inline int ec_usb3_a1_pwr_en(int en)
 {
-	return tca6416a_write_bit(1, TCA6416A_OUT_PORT_1, 1, en);
+	return ioex_set_level(IOEX_USB3_A1_PWR_EN, en);
 }
 
 inline int usb3_a1_mux_sel(int en)
 {
-	return tca6416a_write_bit(1, TCA6416A_OUT_PORT_1, 2, en);
+	return ioex_set_level(IOEX_USB3_A1_MUX_SEL, en);
 }
 
 inline int board_id_det(void)
 {
-	int id;
+	if (board_id_val == BOARD_ID_UNSET) {
+		int id;
 
-	id = tca6416a_read_byte(1, TCA6416A_IN_PORT_1);
-	if (id < 0)
-		return id;
+		/* Cache board ID at init */
+		if (ioex_get_port(IOEX_GET_INFO(IOEX_BOARD_ID_DET0)->ioex,
+				  IOEX_GET_INFO(IOEX_BOARD_ID_DET0)->port, &id))
+			return id;
 
-	/* Board ID consists of bits 5, 4, and 3 */
-	return (id >> 3) & 0x7;
+		/* Board ID consists of bits 5, 4, and 3 */
+		board_id_val = (id >> BOARD_ID_DET_OFFSET) & BOARD_ID_DET_MASK;
+	}
+
+	return board_id_val;
 }
 
-inline int cmux_en(int en)
+inline int dongle_det(void)
 {
-	return tca6416a_write_bit(1, TCA6416A_OUT_PORT_1, 6, en);
+	int val;
+	ioex_get_level(IOEX_DONGLE_DET, &val);
+	return val;
 }
 
-inline int dongle_det(void)
+inline int get_host_chrg_det(void)
 {
-	return tca6416a_read_bit(1, TCA6416A_IN_PORT_1, 7);
+	int val;
+	ioex_get_level(IOEX_HOST_CHRG_DET, &val);
+	return val;
 }
 
 inline int en_pp5000_alt_3p3(int en)
 {
-	return tca6424a_write_bit(1, TCA6424A_OUT_PORT_0, 0, en);
+	return ioex_set_level(IOEX_EN_PP5000_ALT_3P3, en);
 }
 
 inline int en_pp3300_eth(int en)
 {
-	return tca6424a_write_bit(1, TCA6424A_OUT_PORT_0, 1, en);
+	return ioex_set_level(IOEX_EN_PP3300_ETH, en);
 }
 
 inline int en_pp3300_dp(int en)
 {
-	return tca6424a_write_bit(1, TCA6424A_OUT_PORT_0, 2, en);
+	return ioex_set_level(IOEX_EN_PP3300_DP, en);
 }
 
 inline int fault_clear_cc(int en)
 {
-	return tca6424a_write_bit(1, TCA6424A_OUT_PORT_0, 3, en);
+	return ioex_set_level(IOEX_FAULT_CLEAR_CC, en);
 }
 
 inline int en_vout_buf_cc1(int en)
 {
-	return tca6424a_write_bit(1, TCA6424A_OUT_PORT_0, 4, en);
+	return ioex_set_level(IOEX_EN_VOUT_BUF_CC1, en);
 }
 
 inline int en_vout_buf_cc2(int en)
 {
-	return tca6424a_write_bit(1, TCA6424A_OUT_PORT_0, 5, en);
+	return ioex_set_level(IOEX_EN_VOUT_BUF_CC2, en);
 }
 
 int dut_chg_en(int en)
 {
 	dut_chg_en_state = en;
-	return tca6424a_write_bit(1, TCA6424A_OUT_PORT_0, 6, en);
+	return ioex_set_level(IOEX_DUT_CHG_EN, en);
 }
 
 int get_dut_chg_en(void)
@@ -288,25 +287,70 @@ int get_dut_chg_en(void)
 
 inline int host_or_chg_ctl(int en)
 {
-	return tca6424a_write_bit(1, TCA6424A_OUT_PORT_0, 7, en);
+	return ioex_set_level(IOEX_HOST_OR_CHG_CTL, en);
 }
 
 inline int read_faults(void)
 {
-	return tca6424a_read_byte(1, TCA6424A_IN_PORT_1);
+	int val;
+
+	ioex_get_port(IOEX_GET_INFO(IOEX_USERVO_FAULT_L)->ioex,
+		      IOEX_GET_INFO(IOEX_USERVO_FAULT_L)->port, &val);
+
+	return val;
+}
+
+inline int read_irqs(void)
+{
+	int val;
+
+	ioex_get_port(IOEX_GET_INFO(IOEX_SYS_PWR_IRQ_ODL)->ioex,
+		      IOEX_GET_INFO(IOEX_SYS_PWR_IRQ_ODL)->port, &val);
+
+	return val;
 }
 
 inline int vbus_dischrg_en(int en)
 {
-	return tca6424a_write_bit(1, TCA6424A_OUT_PORT_2, 0, en);
+	return ioex_set_level(IOEX_VBUS_DISCHRG_EN, en);
 }
 
 inline int usbh_pwrdn_l(int en)
 {
-	return tca6424a_write_bit(1, TCA6424A_OUT_PORT_2, 1, en);
+	return ioex_set_level(IOEX_USBH_PWRDN_L, en);
 }
 
 inline int tca_gpio_dbg_led_k_odl(int en)
 {
-	return tca6424a_write_bit(1, TCA6424A_OUT_PORT_2, 7, !en);
+	return ioex_set_level(IOEX_TCA_GPIO_DBG_LED_K_ODL, !en);
+}
+
+#else /* SECTION_IS_RO */
+
+/*
+ * Due to lack of flash in RW section, it is not possible to use IOEX subsystem
+ * in it. Instead, RO section uses IOEX, and RW implements only required
+ * function with raw i2c operation. This function is required by 'version'
+ * console command and should work without any special initialization.
+ */
+inline int board_id_det(void)
+{
+	if (board_id_val == BOARD_ID_UNSET) {
+		int id;
+		int res;
+
+		/* Cache board ID at init */
+		res = i2c_read8(TCA6416A_PORT, TCA6416A_ADDR, BOARD_ID_DET_PORT,
+				&id);
+		if (res != EC_SUCCESS)
+			return res;
+
+		/* Board ID consists of bits 5, 4, and 3 */
+		board_id_val = (id >> BOARD_ID_DET_OFFSET) & BOARD_ID_DET_MASK;
+	}
+
+	/* Board ID consists of bits 5, 4, and 3 */
+	return board_id_val;
 }
+
+#endif /* SECTION_IS_RO */
diff --git a/board/servo_v4p1/ioexpanders.h b/board/servo_v4p1/ioexpanders.h
index d444a6fca3..313fea46a4 100644
--- a/board/servo_v4p1/ioexpanders.h
+++ b/board/servo_v4p1/ioexpanders.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,10 +6,11 @@
 #ifndef __CROS_EC_IOEXPANDERS_H
 #define __CROS_EC_IOEXPANDERS_H
 
-enum uservo_fastboot_mux_sel_t {
-	MUX_SEL_USERVO = 0,
-	MUX_SEL_FASTBOOT = 1
-};
+#define BOARD_ID_DET_MASK 0x7
+#define BOARD_ID_DET_OFFSET 3
+#define BOARD_ID_DET_PORT 1
+
+enum uservo_fastboot_mux_sel_t { MUX_SEL_USERVO = 0, MUX_SEL_FASTBOOT = 1 };
 
 /*
  * Initialize Ioexpanders
@@ -68,13 +69,13 @@ int usb3_a0_mux_sel(int en);
 int usb3_a0_mux_en_l(int en);
 
 /**
- * Controls load switches for 5V to general USB type A
+ * Controls load switches for 5V to general USB type A.
  *
  * @param en	0 - Disable power
  *		1 - Enable power
  * @return EC_SUCCESS or EC_xxx on error
  */
-int usb3_a0_pwr_en(int en);
+int ec_usb3_a0_pwr_en(int en);
 
 /**
  * Controls logic to select 1.8V or 3.3V UART from STM to DUT on SBU lines
@@ -92,7 +93,7 @@ int uart_18_sel(int en);
  *		1 - Enable power
  * @return EC_SUCCESS or EC_xxx on error
  */
-int uservo_power_en(int en);
+int ec_uservo_power_en(int en);
 
 /**
  * USB data path enable from host hub to downstream userv or DUT peripheral
@@ -110,7 +111,7 @@ int uservo_fastboot_mux_sel(enum uservo_fastboot_mux_sel_t sel);
  *		1 - power enabled
  * @return EC_SUCCESS or EC_xxx on error
  */
-int usb3_a1_pwr_en(int en);
+int ec_usb3_a1_pwr_en(int en);
 
 /**
  * USB data path for general USB type A port, second on J2
@@ -128,15 +129,6 @@ int usb3_a1_mux_sel(int en);
  */
 int board_id_det(void);
 
-/**
- * USBC 4:6 redriver enable
- *
- * @param en	0 - TUSB1064 disabled
- *		1 - TUSB1064 enabled
- * @return EC_SUCCESS or EC_xxx on error
- */
-int cmux_en(int en);
-
 /**
  * Reads the TypeA/TypeC DUT cable assembly pigtail
  *
@@ -145,6 +137,14 @@ int cmux_en(int en);
  */
 int dongle_det(void);
 
+/**
+ * Reads state of BC1.2 on host connection
+ *
+ * @return	0 - BC1.2 not present
+ * 		1 - BC1.2 present
+ */
+int get_host_chrg_det(void);
+
 /**
  * Enable signal for supplemental power supply. This supply will support higher
  * wattage servo needs. 10ms after enabling this bit, the server supply should
@@ -233,14 +233,14 @@ int get_dut_chg_en(void);
  */
 int host_or_chg_ctl(int en);
 
-#define USERVO_FAULT_L		BIT(0)
-#define USB3_A0_FAULT_L		BIT(1)
-#define USB3_A1_FAULT_L		BIT(2)
-#define USB_DUTCHG_FLT_ODL	BIT(3)
-#define PP3300_DP_FAULT_L	BIT(4)
-#define DAC_BUF1_LATCH_FAULT_L	BIT(5)
-#define DAC_BUF2_LATCH_FAULT_L	BIT(6)
-#define PP5000_SRC_SEL		BIT(7)
+#define USERVO_FAULT_L BIT(0)
+#define USB3_A0_FAULT_L BIT(1)
+#define USB3_A1_FAULT_L BIT(2)
+#define USB_DUTCHG_FLT_ODL BIT(3)
+#define PP3300_DP_FAULT_L BIT(4)
+#define DAC_BUF1_LATCH_FAULT_L BIT(5)
+#define DAC_BUF2_LATCH_FAULT_L BIT(6)
+#define PP5000_SRC_SEL BIT(7)
 
 /**
  * Read any faults that may have occurred. A fault has occurred if the
@@ -268,6 +268,23 @@ int host_or_chg_ctl(int en);
  */
 int read_faults(void);
 
+#define HOST_CHRG_DET BIT(0)
+#define SYS_PWR_IRQ_ODL BIT(6)
+
+/**
+ * Read irqs which indicate some system event.
+ *
+ * BIT
+ * 0 (HOST_CHRG_DET)   - Change of state of BC1.2 on host connection
+ *                       0 - BC1.2 not present
+ *                       1 - BC1.2 present
+ * 6 (SYS_PWR_IRQ_ODL) - IRQ from system full power INA231 monitor. IRQ can be
+ *                       programmed to trip on wattage threshold.
+ *                       0 - IRQ asserted
+ *                       1 - no IRQ
+ */
+int read_irqs(void);
+
 /**
  * Enables active discharge for USB DUT Charger
  *
diff --git a/board/servo_v4p1/pathsel.c b/board/servo_v4p1/pathsel.c
index 40100ce22a..eba1733e05 100644
--- a/board/servo_v4p1/pathsel.c
+++ b/board/servo_v4p1/pathsel.c
@@ -1,27 +1,44 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "gl3590.h"
 #include "gpio.h"
 #include "ioexpanders.h"
 #include "pathsel.h"
 
+static void hh_usb3_a0_pwr_en(int en)
+{
+	gl3590_enable_ports(0, GL3590_DFP2, en);
+}
+
+static void hh_usb3_a1_pwr_en(int en)
+{
+	gl3590_enable_ports(0, GL3590_DFP1, en);
+}
+
 void init_pathsel(void)
 {
 	/* Connect TypeA port to DUT hub */
 	usb3_a0_to_dut();
 	/* Connect data lines */
 	usb3_a0_mux_en_l(0);
+
 	/* Enable power */
-	usb3_a0_pwr_en(1);
+	ec_usb3_a0_pwr_en(1);
+
+	hh_usb3_a0_pwr_en(1);
 
 	/* Connect TypeA port to DUT hub */
 	usb3_a1_to_dut();
 	/* Connect data lines */
 	gpio_set_level(GPIO_USB3_A1_MUX_EN_L, 0);
+
 	/* Enable power */
-	usb3_a1_pwr_en(1);
+	ec_usb3_a1_pwr_en(1);
+
+	hh_usb3_a1_pwr_en(1);
 }
 
 void usb3_a0_to_dut(void)
@@ -46,14 +63,14 @@ void usb3_a1_to_host(void)
 	usb3_a1_mux_sel(0);
 }
 
-void host_to_dut(void)
+void dut_to_host(void)
 {
 	gpio_set_level(GPIO_FASTBOOT_DUTHUB_MUX_SEL, 0);
+	gpio_set_level(GPIO_FASTBOOT_DUTHUB_MUX_EN_L, 0);
 	uservo_fastboot_mux_sel(MUX_SEL_FASTBOOT);
 }
 
 void uservo_to_host(void)
 {
-	gpio_set_level(GPIO_FASTBOOT_DUTHUB_MUX_SEL, 1);
 	uservo_fastboot_mux_sel(MUX_SEL_USERVO);
 }
diff --git a/board/servo_v4p1/pathsel.h b/board/servo_v4p1/pathsel.h
index d2f71be024..5f228aceb9 100644
--- a/board/servo_v4p1/pathsel.h
+++ b/board/servo_v4p1/pathsel.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -32,9 +32,9 @@ void usb3_a0_to_host(void);
 void usb3_a1_to_host(void);
 
 /**
- * Routes the HOST to the DUT. Used for fastboot
+ * Routes the DUT to the HOST. Used for fastboot
  */
-void host_to_dut(void);
+void dut_to_host(void);
 
 /**
  * Routes the Micro Servo to the Host
diff --git a/board/servo_v4p1/pi3usb9201.c b/board/servo_v4p1/pi3usb9201.c
index 102eaf790d..976c213c49 100644
--- a/board/servo_v4p1/pi3usb9201.c
+++ b/board/servo_v4p1/pi3usb9201.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,7 @@
 #include "i2c.h"
 #include "pi3usb9201.h"
 
-#define PI3USB9201_ADDR	0x5f
+#define PI3USB9201_ADDR 0x5f
 
 inline void init_pi3usb9201(void)
 {
@@ -19,7 +19,7 @@ inline void init_pi3usb9201(void)
 }
 
 inline void write_pi3usb9201(enum pi3usb9201_reg_t reg,
-					enum pi3usb9201_dat_t dat)
+			     enum pi3usb9201_dat_t dat)
 {
 	i2c_write8(1, PI3USB9201_ADDR, reg, dat);
 }
diff --git a/board/servo_v4p1/pi3usb9201.h b/board/servo_v4p1/pi3usb9201.h
index 826db8b871..863fc4129a 100644
--- a/board/servo_v4p1/pi3usb9201.h
+++ b/board/servo_v4p1/pi3usb9201.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,35 +6,29 @@
 #ifndef __CROS_EC_PI3USB9201_H
 #define __CROS_EC_PI3USB9201_H
 
-enum pi3usb9201_reg_t {
-	CTRL_REG1,
-	CTRL_REG2,
-	CLIENT_STATUS,
-	HOST_STATUS
-};
+enum pi3usb9201_reg_t { CTRL_REG1, CTRL_REG2, CLIENT_STATUS, HOST_STATUS };
 
 enum pi3usb9201_dat_t {
-	POWER_DOWN	= 0x0,
-	SDP_HOST_MODE	= 0x2,
-	DCP_HOST_MODE	= 0x4,
-	CDP_HOST_MODE	= 0x6,
-	CLIENT_MODE	= 0x8,
-	USB_PATH_ON	= 0xe
+	POWER_DOWN = 0x0,
+	SDP_HOST_MODE = 0x2,
+	DCP_HOST_MODE = 0x4,
+	CDP_HOST_MODE = 0x6,
+	CLIENT_MODE = 0x8,
+	USB_PATH_ON = 0xe
 };
 
-
 /* Client Status bits */
-#define CS_DCP			BIT(7)
-#define CS_SDP			BIT(6)
-#define CS_CDP			BIT(5)
-#define CS_1A_CHARGER		BIT(3)
-#define CS_2A_CHARGER		BIT(2)
-#define CS_2_4A_CHARGER		BIT(1)
+#define CS_DCP BIT(7)
+#define CS_SDP BIT(6)
+#define CS_CDP BIT(5)
+#define CS_1A_CHARGER BIT(3)
+#define CS_2A_CHARGER BIT(2)
+#define CS_2_4A_CHARGER BIT(1)
 
 /* Host Status bits */
-#define HS_USB_UNPLUGGED	BIT(2)
-#define HS_USB_PLUGGED		BIT(1)
-#define HS_BC1_2		BIT(0)
+#define HS_USB_UNPLUGGED BIT(2)
+#define HS_USB_PLUGGED BIT(1)
+#define HS_BC1_2 BIT(0)
 
 /**
  * Selects Client Mode and client mode detection
diff --git a/board/servo_v4p1/tca6416a.c b/board/servo_v4p1/tca6416a.c
deleted file mode 100644
index d776ad86fe..0000000000
--- a/board/servo_v4p1/tca6416a.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "i2c.h"
-#include "tca6416a.h"
-
-int tca6416a_write_bit(int port, enum tca6416a_bank bank, uint8_t bit, int val)
-{
-	int tmp;
-	int ret;
-
-	/* Read output port register */
-	ret = i2c_read8(port, TCA6416A_ADDR_FLAGS, bank, &tmp);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	if (val)
-		tmp |= BIT(bit);
-	else
-		tmp &= ~BIT(bit);
-
-	/* Write back modified output port register */
-	ret = i2c_write8(port, TCA6416A_ADDR_FLAGS, bank, tmp);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	return EC_SUCCESS;
-}
-
-int tca6416a_write_byte(int port, enum tca6416a_bank bank, uint8_t val)
-{
-	int ret;
-
-	ret = i2c_write8(port, TCA6416A_ADDR_FLAGS, bank, val);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	return EC_SUCCESS;
-}
-
-int tca6416a_read_byte(int port, enum tca6416a_bank bank)
-{
-	int tmp;
-
-	if (i2c_read8(port, TCA6416A_ADDR_FLAGS, bank, &tmp) != EC_SUCCESS)
-		return -1;
-
-	return tmp;
-}
-
-int tca6416a_read_bit(int port, enum tca6416a_bank bank, uint8_t bit)
-{
-	int tmp;
-	int mask = 1 << bit;
-
-	/* Read input port register */
-	if (i2c_read8(port, TCA6416A_ADDR_FLAGS, bank, &tmp) != EC_SUCCESS)
-		return -1;
-
-	return (tmp & mask) >> bit;
-}
diff --git a/board/servo_v4p1/tca6416a.h b/board/servo_v4p1/tca6416a.h
deleted file mode 100644
index 5255059d99..0000000000
--- a/board/servo_v4p1/tca6416a.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_IOEXPANDER_TCA6416A_H
-#define __CROS_EC_IOEXPANDER_TCA6416A_H
-
-#include <stdint.h>
-
-#define TCA6416A_ADDR_FLAGS 0x21
-
-enum tca6416a_bank {
-	TCA6416A_IN_PORT_0  = 0x0,
-	TCA6416A_IN_PORT_1  = 0x1,
-	TCA6416A_OUT_PORT_0 = 0x2,
-	TCA6416A_OUT_PORT_1 = 0x3,
-	TCA6416A_DIR_PORT_0 = 0x6,
-	TCA6416A_DIR_PORT_1 = 0x7,
-};
-
-/*
- * Set a bit in the supplied bank
- *
- * @param port  The I2C port of TCA6416A.
- * @param bank  The bank the bit belongs to.
- * @param bit   The index of the bit to set.
- * @param val   The value to set.
- *
- * @return EC_SUCCESS, or EC_ERROR_* on error.
- */
-int tca6416a_write_bit(int port,
-			enum tca6416a_bank bank, uint8_t bit, int val);
-
-/*
- * Get a bit in the supplied bank
- *
- * @param port  The I2C port of TCA6416A.
- * @param bank  The bank the bit belongs to.
- * @param bit   The index of the bit to get.
- *
- * @return bit value, or -1 on error.
- */
-int tca6416a_read_bit(int port, enum tca6416a_bank bank, uint8_t bit);
-
-/*
- * Write a byt to the supplied bank
- *
- * @param port The I2C port of TCA6416A.
- * @param bank  The bank to write the byte to.
- *
- * @return EC_SUCCESS, or EC_ERROR_* on error.
- */
-int tca6416a_write_byte(int port, enum tca6416a_bank bank, uint8_t val);
-
-/*
- * Read a byte in the supplied bank
- *
- * @param port  The I2C port of TCA6416A.
- * @param bank  The bank to read byte from.
- *
- * @return byte value, or -1 on error.
- */
-int tca6416a_read_byte(int port, enum tca6416a_bank bank);
-
-#endif /* __CROS_EC_IOEXPANDER_TCA6416A_H */
diff --git a/board/servo_v4p1/tca6424a.c b/board/servo_v4p1/tca6424a.c
deleted file mode 100644
index 28c768b046..0000000000
--- a/board/servo_v4p1/tca6424a.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "i2c.h"
-#include "tca6424a.h"
-
-int tca6424a_write_bit(int port, enum tca6424a_bank bank, uint8_t bit, int val)
-{
-	int tmp;
-	int ret;
-
-	/* Read output port register */
-	ret = i2c_read8(port, TCA6424A_ADDR_FLAGS, bank, &tmp);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	if (val)
-		tmp |= BIT(bit);
-	else
-		tmp &= ~BIT(bit);
-
-	/* Write back modified output port register */
-	ret = i2c_write8(port, TCA6424A_ADDR_FLAGS, bank, tmp);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	return EC_SUCCESS;
-}
-
-int tca6424a_write_byte(int port, enum tca6424a_bank bank, uint8_t val)
-{
-	int ret;
-
-	ret = i2c_write8(port, TCA6424A_ADDR_FLAGS, bank, val);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	return EC_SUCCESS;
-}
-
-int tca6424a_read_byte(int port, enum tca6424a_bank bank)
-{
-	int tmp;
-
-	if (i2c_read8(port, TCA6424A_ADDR_FLAGS, bank, &tmp) != EC_SUCCESS)
-		return -1;
-
-	return tmp;
-}
-
-int tca6424a_read_bit(int port, enum tca6424a_bank bank, uint8_t bit)
-{
-	int tmp;
-	int mask = 1 << bit;
-
-	/* Read input port register */
-	if (i2c_read8(port, TCA6424A_ADDR_FLAGS, bank, &tmp) != EC_SUCCESS)
-		return -1;
-
-	return (tmp & mask) >> bit;
-}
diff --git a/board/servo_v4p1/tca6424a.h b/board/servo_v4p1/tca6424a.h
deleted file mode 100644
index 80db7ebdba..0000000000
--- a/board/servo_v4p1/tca6424a.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_IOEXPANDER_TCA6424A_H
-#define __CROS_EC_IOEXPANDER_TCA6424A_H
-
-#include <stdint.h>
-
-#define TCA6424A_ADDR_FLAGS 0x23
-
-enum tca6424a_bank {
-	TCA6424A_IN_PORT_0  = 0x0,
-	TCA6424A_IN_PORT_1  = 0x1,
-	TCA6424A_IN_PORT_2  = 0x2,
-	TCA6424A_OUT_PORT_0 = 0x4,
-	TCA6424A_OUT_PORT_1 = 0x5,
-	TCA6424A_OUT_PORT_2 = 0x6,
-	TCA6424A_DIR_PORT_0 = 0xc,
-	TCA6424A_DIR_PORT_1 = 0xd,
-	TCA6424A_DIR_PORT_2 = 0xe,
-};
-
-/*
- * Set a bit in the supplied bank
- *
- * @param port  The I2C port of TCA6424A.
- * @param bank  The bank the bit belongs to.
- * @param bit   The index of the bit to set.
- * @param val   The value to set.
- *
- * @return EC_SUCCESS, or EC_ERROR_* on error.
- */
-int tca6424a_write_bit(int port,
-			enum tca6424a_bank bank, uint8_t bit, int val);
-
-/*
- * Get a bit in the supplied bank
- *
- * @param port  The I2C port of TCA6424A.
- * @param bank  The bank the bit belongs to.
- * @param bit   The index of the bit to get.
- *
- * @return bit value, or -1 on error.
- */
-int tca6424a_read_bit(int port, enum tca6424a_bank bank, uint8_t bit);
-
-/*
- * Write a byt to the supplied bank
- *
- * @param port The I2C port of TCA6424A.
- * @param bank  The bank to write the byte to.
- *
- * @return EC_SUCCESS, or EC_ERROR_* on error.
- */
-int tca6424a_write_byte(int port, enum tca6424a_bank bank, uint8_t val);
-
-/*
- * Read a byte in the supplied bank
- *
- * @param port  The I2C port of TCA6424A.
- * @param bank  The bank to read byte from.
- *
- * @return byte value, or -1 on error.
- */
-int tca6424a_read_byte(int port, enum tca6424a_bank bank);
-
-#endif /* __CROS_EC_IOEXPANDER_TCA6424A_H */
diff --git a/board/servo_v4p1/tusb1064.c b/board/servo_v4p1/tusb1064.c
deleted file mode 100644
index 30816da11b..0000000000
--- a/board/servo_v4p1/tusb1064.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "i2c.h"
-#include "tusb1064.h"
-#include "ioexpanders.h"
-
-int init_tusb1064(int port)
-{
-	uint8_t val;
-
-	/* Enable the TUSB1064 redriver */
-	cmux_en(1);
-
-	/* Disconnect USB3.1 and DP */
-	val = tusb1064_read_byte(port, TUSB1064_REG_GENERAL);
-	if (val < 0)
-		return EC_ERROR_INVAL;
-
-	val &= ~REG_GENERAL_CTLSEL_2DP_AND_USB3;
-	if (tusb1064_write_byte(port, TUSB1064_REG_GENERAL, val))
-		return EC_ERROR_INVAL;
-
-	return EC_SUCCESS;
-}
-
-int tusb1064_write_byte(int port, uint8_t reg, uint8_t val)
-{
-	return i2c_write8(port, TUSB1064_ADDR_FLAGS, reg, val);
-}
-
-int tusb1064_read_byte(int port, uint8_t reg)
-{
-	int tmp;
-
-	if (i2c_read8(port, TUSB1064_ADDR_FLAGS, reg, &tmp))
-		return -1;
-
-	return tmp;
-}
diff --git a/board/servo_v4p1/tusb1064.h b/board/servo_v4p1/tusb1064.h
deleted file mode 100644
index a6ca77b7b7..0000000000
--- a/board/servo_v4p1/tusb1064.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_TUSB1064_H
-#define __CROS_EC_TUSB1064_H
-
-#include <stdint.h>
-
-#define TUSB1064_ADDR_FLAGS		0x12
-
-#define TUSB1064_REG_GENERAL		0x0a
-#define REG_GENERAL_CTLSEL_DISABLE      0x00
-#define REG_GENERAL_CTLSEL_USB3         0x01
-#define REG_GENERAL_CTLSEL_4DP_LANES    0x02
-#define REG_GENERAL_CTLSEL_2DP_AND_USB3 0x03
-#define REG_GENERAL_FLIPSEL		BIT(2)
-#define REG_GENERAL_DP_ENABLE_CTRL	BIT(3)
-#define REG_GENERAL_EQ_OVERRIDE		BIT(4)
-
-/*
- * Initialize the TUSB1064
- *
- * @param port	The I2C port of TUSB1064
- * @return EC_SUCCESS or EC_ERROR_*
- */
-int init_tusb1064(int port);
-
-/*
- * Write a byte to the TUSB1064
- *
- * @param port	The I2C port of TUSB1064.
- * @param reg	Register to write byte to.
- * @param val	Value to write to TUSB1064.
- *
- * @return EC_SUCCESS, or EC_ERROR_* on error.
- */
-int tusb1064_write_byte(int port, uint8_t reg, uint8_t val);
-
-/*
- * Read a byte from TUSB1064
- *
- * @param port	The I2C port of TUSB1064.
- * @param reg	Register to read byte from.
- *
- * @return	byte value, or -1 on error.
- */
-int tusb1064_read_byte(int port, uint8_t reg);
-
-#endif /* __CROS_EC_TUSB1064_H */
diff --git a/board/servo_v4p1/usb_pd_config.h b/board/servo_v4p1/usb_pd_config.h
index 7946ea5a6e..32ec29341a 100644
--- a/board/servo_v4p1/usb_pd_config.h
+++ b/board/servo_v4p1/usb_pd_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,8 +6,8 @@
 #include "adc.h"
 #include "chip/stm32/registers.h"
 #include "console.h"
-#include "gpio.h"
 #include "ec_commands.h"
+#include "gpio.h"
 #include "usb_pd_tcpm.h"
 
 /* USB Power delivery board configuration */
@@ -15,15 +15,6 @@
 #ifndef __CROS_EC_USB_PD_CONFIG_H
 #define __CROS_EC_USB_PD_CONFIG_H
 
-/* NOTES: Servo V4 and glados equivalents:
- *	Glados		Servo V4
- *	C0		CHG
- *	C1		DUT
- *
- */
-#define CHG 0
-#define DUT 1
-
 /* Timer selection for baseband PD communication */
 #define TIM_CLOCK_PD_TX_CHG 16
 #define TIM_CLOCK_PD_RX_CHG 1
@@ -56,31 +47,33 @@
 #define CONFIG_HW_CRC
 
 /* Servo v4 CC configuration */
-#define CC_DETACH	BIT(0)   /* Emulate detach: both CC open */
-#define CC_DISABLE_DTS	BIT(1)   /* Apply resistors to single or both CC? */
-#define CC_ALLOW_SRC	BIT(2)   /* Allow charge through by policy? */
-#define CC_ENABLE_DRP	BIT(3)   /* Enable dual-role port */
-#define CC_SNK_WITH_PD	BIT(4)   /* Force enabling PD comm for sink role */
-#define CC_POLARITY	BIT(5)   /* CC polarity */
-#define CC_EMCA_SERVO	BIT(6)   /*
-				  * Emulate Electronically Marked Cable Assembly
-				  * (EMCA) servo (or non-EMCA)
-				  */
+#define CC_DETACH BIT(0) /* Emulate detach: both CC open */
+#define CC_DISABLE_DTS BIT(1) /* Apply resistors to single or both CC? */
+#define CC_ALLOW_SRC BIT(2) /* Allow charge through by policy? */
+#define CC_ENABLE_DRP BIT(3) /* Enable dual-role port */
+#define CC_SNK_WITH_PD BIT(4) /* Force enabling PD comm for sink role */
+#define CC_POLARITY BIT(5) /* CC polarity */
+#define CC_EMCA_SERVO                                          \
+	BIT(6) /*                                              \
+		* Emulate Electronically Marked Cable Assembly \
+		* (EMCA) servo (or non-EMCA)                   \
+		*/
+#define CC_FASTBOOT_DFP BIT(7) /* Allow mux uServo->Fastboot on DFP */
 
 /* Servo v4 DP alt-mode configuration */
-#define ALT_DP_ENABLE		BIT(0)   /* Enable DP alt-mode or not */
-#define ALT_DP_PIN_C		BIT(1)   /* Pin assignment C supported */
-#define ALT_DP_PIN_D		BIT(2)   /* Pin assignment D supported */
-#define ALT_DP_MF_PREF		BIT(3)   /* Multi-Function preferred */
-#define ALT_DP_PLUG		BIT(4)   /* Plug or receptacle */
-#define ALT_DP_OVERRIDE_HPD	BIT(5)   /* Override the HPD signal */
-#define ALT_DP_HPD_LVL		BIT(6)   /* HPD level if overridden */
+#define ALT_DP_ENABLE BIT(0) /* Enable DP alt-mode or not */
+#define ALT_DP_PIN_C BIT(1) /* Pin assignment C supported */
+#define ALT_DP_PIN_D BIT(2) /* Pin assignment D supported */
+#define ALT_DP_MF_PREF BIT(3) /* Multi-Function preferred */
+#define ALT_DP_PLUG BIT(4) /* Plug or receptacle */
+#define ALT_DP_OVERRIDE_HPD BIT(5) /* Override the HPD signal */
+#define ALT_DP_HPD_LVL BIT(6) /* HPD level if overridden */
 
 /* TX uses SPI1 on PB3-4 for CHG port, SPI2 on PB 13-14 for DUT port */
 #define SPI_REGS(p) ((p) ? STM32_SPI2_REGS : STM32_SPI1_REGS)
 static inline void spi_enable_clock(int port)
 {
-	if (port == 0)
+	if (port == CHG)
 		STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1;
 	else
 		STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
@@ -97,14 +90,14 @@ static inline void spi_enable_clock(int port)
 
 #define TIM_TX_CCR_IDX(p) ((p) ? TIM_TX_CCR_DUT : TIM_TX_CCR_CHG)
 #define TIM_RX_CCR_IDX(p) ((p) ? TIM_RX_CCR_DUT : TIM_RX_CCR_CHG)
-#define TIM_CCR_CS  1
+#define TIM_CCR_CS 1
 
 /*
  * EXTI line 21 is connected to the CMP1 output,
  * EXTI line 22 is connected to the CMP2 output,
  * CHG uses CMP2, and DUT uses CMP1.
  */
-#define EXTI_COMP_MASK(p) ((p) ? (1<<21) : BIT(22))
+#define EXTI_COMP_MASK(p) ((p) ? (1 << 21) : BIT(22))
 
 #define IRQ_COMP STM32_IRQ_COMP
 /* triggers packet detection on comparator falling edge */
@@ -116,7 +109,7 @@ static inline void spi_enable_clock(int port)
 /* the pins used for communication need to be hi-speed */
 static inline void pd_set_pins_speed(int port)
 {
-	if (port == 0) {
+	if (port == CHG) {
 		/* 40 MHz pin speed on SPI PB3&4,
 		 * (USB_CHG_TX_CLKIN & USB_CHG_CC1_TX_DATA)
 		 */
@@ -138,7 +131,7 @@ static inline void pd_set_pins_speed(int port)
 /* Reset SPI peripheral used for TX */
 static inline void pd_tx_spi_reset(int port)
 {
-	if (port == 0) {
+	if (port == CHG) {
 		/* Reset SPI1 */
 		STM32_RCC_APB2RSTR |= BIT(12);
 		STM32_RCC_APB2RSTR &= ~BIT(12);
@@ -193,16 +186,28 @@ static inline void pd_select_polarity(int port, int polarity)
 	/* Use window mode so that COMP1 and COMP2 share non-inverting input */
 	val |= STM32_COMP_CMP1EN | STM32_COMP_CMP2EN | STM32_COMP_WNDWEN;
 
-	if (port == 0) {
+	if (port == CHG) {
 		/* CHG use the right comparator inverted input for COMP2 */
 		STM32_COMP_CSR = (val & ~STM32_COMP_CMP2INSEL_MASK) |
-			(polarity ? STM32_COMP_CMP2INSEL_INM4  /* PA4: C0_CC2 */
-				  : STM32_COMP_CMP2INSEL_INM6);/* PA2: C0_CC1 */
+				 (polarity ?
+					  STM32_COMP_CMP2INSEL_INM4 /* PA4:
+								       C0_CC2
+								     */
+					  :
+					  STM32_COMP_CMP2INSEL_INM6); /* PA2:
+									 C0_CC1
+								       */
 	} else {
 		/* DUT use the right comparator inverted input for COMP1 */
 		STM32_COMP_CSR = (val & ~STM32_COMP_CMP1INSEL_MASK) |
-			(polarity ? STM32_COMP_CMP1INSEL_INM5  /* PA5: C1_CC2 */
-			 : STM32_COMP_CMP1INSEL_INM6);/* PA0: C1_CC1 */
+				 (polarity ?
+					  STM32_COMP_CMP1INSEL_INM5 /* PA5:
+								       C1_CC2
+								     */
+					  :
+					  STM32_COMP_CMP1INSEL_INM6); /* PA0:
+									 C1_CC1
+								       */
 	}
 }
 
@@ -237,7 +242,7 @@ static inline void pd_set_host_mode(int port, int enable)
 	 * present as a SNK device. If port != DUT (port == 1), then nothing to
 	 * do in this function.
 	 */
-	if (!port)
+	if (port != DUT)
 		return;
 
 	if (enable) {
@@ -282,10 +287,8 @@ static inline void pd_config_init(int port, uint8_t power_role)
 
 	/* Initialize TX pins and put them in Hi-Z */
 	pd_tx_init();
-
 }
 
 int pd_adc_read(int port, int cc);
 
 #endif /* __CROS_EC_USB_PD_CONFIG_H */
-
diff --git a/board/servo_v4p1/usb_pd_policy.c b/board/servo_v4p1/usb_pd_policy.c
index 96af570aae..9ec6ead960 100644
--- a/board/servo_v4p1/usb_pd_policy.c
+++ b/board/servo_v4p1/usb_pd_policy.c
@@ -1,11 +1,11 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "atomic.h"
-#include "chg_control.h"
 #include "charge_manager.h"
+#include "chg_control.h"
 #include "common.h"
 #include "console.h"
 #include "gpio.h"
@@ -13,70 +13,70 @@
 #include "host_command.h"
 #include "i2c.h"
 #include "ioexpanders.h"
+#include "pathsel.h"
 #include "registers.h"
 #include "system.h"
 #include "task.h"
-#include "tcpm.h"
+#include "tcpm/tcpm.h"
 #include "timer.h"
-#include "tusb1064.h"
-#include "util.h"
 #include "usb_common.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
 #include "usb_pd_config.h"
 #include "usb_pd_tcpm.h"
+#include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
-#define DUT_PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\
-			     PDO_FIXED_COMM_CAP)
+#define DUT_PDO_FIXED_FLAGS \
+	(PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP | PDO_FIXED_COMM_CAP)
 
 #define CHG_PDO_FIXED_FLAGS (PDO_FIXED_DATA_SWAP)
 
-#define VBUS_UNCHANGED(curr, pend, new) (curr == new && pend == new)
-
 /* Macros to config the PD role */
 #define CONF_SET_CLEAR(c, set, clear) ((c | (set)) & ~(clear))
-#define CONF_SRC(c) CONF_SET_CLEAR(c, \
-				CC_DISABLE_DTS | CC_ALLOW_SRC, \
-				CC_ENABLE_DRP | CC_SNK_WITH_PD)
-#define CONF_SNK(c) CONF_SET_CLEAR(c, \
-				CC_DISABLE_DTS, \
-				CC_ALLOW_SRC | CC_ENABLE_DRP | CC_SNK_WITH_PD)
-#define CONF_PDSNK(c) CONF_SET_CLEAR(c, \
-				CC_DISABLE_DTS | CC_SNK_WITH_PD, \
-				CC_ALLOW_SRC | CC_ENABLE_DRP)
-#define CONF_DRP(c) CONF_SET_CLEAR(c, \
-				CC_DISABLE_DTS | CC_ALLOW_SRC | CC_ENABLE_DRP, \
-				CC_SNK_WITH_PD)
-#define CONF_SRCDTS(c) CONF_SET_CLEAR(c, \
-				CC_ALLOW_SRC, \
-				CC_ENABLE_DRP | CC_DISABLE_DTS | CC_SNK_WITH_PD)
-#define CONF_SNKDTS(c) CONF_SET_CLEAR(c, \
-				0, \
-				CC_ALLOW_SRC | CC_ENABLE_DRP | \
-				CC_DISABLE_DTS | CC_SNK_WITH_PD)
-#define CONF_PDSNKDTS(c) CONF_SET_CLEAR(c, \
-				CC_SNK_WITH_PD, \
-				CC_ALLOW_SRC | CC_ENABLE_DRP | CC_DISABLE_DTS)
-#define CONF_DRPDTS(c) CONF_SET_CLEAR(c, \
-				CC_ALLOW_SRC | CC_ENABLE_DRP, \
-				CC_DISABLE_DTS | CC_SNK_WITH_PD)
+#define CONF_SRC(c)                                      \
+	CONF_SET_CLEAR(c, CC_DISABLE_DTS | CC_ALLOW_SRC, \
+		       CC_ENABLE_DRP | CC_SNK_WITH_PD)
+#define CONF_SNK(c)                       \
+	CONF_SET_CLEAR(c, CC_DISABLE_DTS, \
+		       CC_ALLOW_SRC | CC_ENABLE_DRP | CC_SNK_WITH_PD)
+#define CONF_PDSNK(c)                                      \
+	CONF_SET_CLEAR(c, CC_DISABLE_DTS | CC_SNK_WITH_PD, \
+		       CC_ALLOW_SRC | CC_ENABLE_DRP)
+#define CONF_DRP(c)                                                      \
+	CONF_SET_CLEAR(c, CC_DISABLE_DTS | CC_ALLOW_SRC | CC_ENABLE_DRP, \
+		       CC_SNK_WITH_PD)
+#define CONF_SRCDTS(c)                  \
+	CONF_SET_CLEAR(c, CC_ALLOW_SRC, \
+		       CC_ENABLE_DRP | CC_DISABLE_DTS | CC_SNK_WITH_PD)
+#define CONF_SNKDTS(c)                                                 \
+	CONF_SET_CLEAR(c, 0,                                           \
+		       CC_ALLOW_SRC | CC_ENABLE_DRP | CC_DISABLE_DTS | \
+			       CC_SNK_WITH_PD)
+#define CONF_PDSNKDTS(c)                  \
+	CONF_SET_CLEAR(c, CC_SNK_WITH_PD, \
+		       CC_ALLOW_SRC | CC_ENABLE_DRP | CC_DISABLE_DTS)
+#define CONF_DRPDTS(c)                                  \
+	CONF_SET_CLEAR(c, CC_ALLOW_SRC | CC_ENABLE_DRP, \
+		       CC_DISABLE_DTS | CC_SNK_WITH_PD)
+#define CONF_DTSOFF(c) CONF_SET_CLEAR(c, CC_DISABLE_DTS, 0)
+#define CONF_DTSON(c) CONF_SET_CLEAR(c, 0, CC_DISABLE_DTS)
 
 /* Macros to apply Rd/Rp to CC lines */
-#define DUT_ACTIVE_CC_SET(r, flags) \
-	gpio_set_flags(cc_config & CC_POLARITY ? \
-				CONCAT2(GPIO_USB_DUT_CC2_, r) : \
-				CONCAT2(GPIO_USB_DUT_CC1_, r), \
+#define DUT_ACTIVE_CC_SET(r, flags)                            \
+	gpio_set_flags(cc_config &CC_POLARITY ?                \
+			       CONCAT2(GPIO_USB_DUT_CC2_, r) : \
+			       CONCAT2(GPIO_USB_DUT_CC1_, r),  \
 		       flags)
-#define DUT_INACTIVE_CC_SET(r, flags) \
-	gpio_set_flags(cc_config & CC_POLARITY ? \
-				CONCAT2(GPIO_USB_DUT_CC1_, r) : \
-				CONCAT2(GPIO_USB_DUT_CC2_, r), \
+#define DUT_INACTIVE_CC_SET(r, flags)                          \
+	gpio_set_flags(cc_config &CC_POLARITY ?                \
+			       CONCAT2(GPIO_USB_DUT_CC1_, r) : \
+			       CONCAT2(GPIO_USB_DUT_CC2_, r),  \
 		       flags)
-#define DUT_BOTH_CC_SET(r, flags) \
-	do { \
+#define DUT_BOTH_CC_SET(r, flags)                                     \
+	do {                                                          \
 		gpio_set_flags(CONCAT2(GPIO_USB_DUT_CC1_, r), flags); \
 		gpio_set_flags(CONCAT2(GPIO_USB_DUT_CC2_, r), flags); \
 	} while (0)
@@ -98,15 +98,15 @@
  * than 5V.
  */
 static const uint16_t pd_src_voltages_mv[] = {
-		5000, 9000, 10000, 12000, 15000, 20000,
+	5000, 9000, 10000, 12000, 15000, 20000,
 };
 static uint32_t pd_src_chg_pdo[ARRAY_SIZE(pd_src_voltages_mv)];
 static uint8_t chg_pdo_cnt;
 
 const uint32_t pd_snk_pdo[] = {
-		PDO_FIXED(5000, 500, CHG_PDO_FIXED_FLAGS),
-		PDO_BATT(4750, 21000, 15000),
-		PDO_VAR(4750, 21000, 3000),
+	PDO_FIXED(5000, 500, CHG_PDO_FIXED_FLAGS),
+	PDO_BATT(4750, 21000, 15000),
+	PDO_VAR(4750, 21000, 3000),
 };
 const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
 
@@ -123,15 +123,15 @@ static int cc_config = CC_ALLOW_SRC | CC_EMCA_SERVO;
 
 /* Voltage thresholds for no connect in DTS mode */
 static int pd_src_vnc_dts[TYPEC_RP_RESERVED][2] = {
-	{PD_SRC_3_0_VNC_MV, PD_SRC_1_5_VNC_MV},
-	{PD_SRC_1_5_VNC_MV, PD_SRC_DEF_VNC_MV},
-	{PD_SRC_3_0_VNC_MV, PD_SRC_DEF_VNC_MV},
+	{ PD_SRC_3_0_VNC_MV, PD_SRC_1_5_VNC_MV },
+	{ PD_SRC_1_5_VNC_MV, PD_SRC_DEF_VNC_MV },
+	{ PD_SRC_3_0_VNC_MV, PD_SRC_DEF_VNC_MV },
 };
 /* Voltage thresholds for Ra attach in DTS mode */
 static int pd_src_rd_threshold_dts[TYPEC_RP_RESERVED][2] = {
-	{PD_SRC_3_0_RD_THRESH_MV, PD_SRC_1_5_RD_THRESH_MV},
-	{PD_SRC_1_5_RD_THRESH_MV, PD_SRC_DEF_RD_THRESH_MV},
-	{PD_SRC_3_0_RD_THRESH_MV, PD_SRC_DEF_RD_THRESH_MV},
+	{ PD_SRC_3_0_RD_THRESH_MV, PD_SRC_1_5_RD_THRESH_MV },
+	{ PD_SRC_1_5_RD_THRESH_MV, PD_SRC_DEF_RD_THRESH_MV },
+	{ PD_SRC_3_0_RD_THRESH_MV, PD_SRC_DEF_RD_THRESH_MV },
 };
 /* Voltage thresholds for no connect in normal SRC mode */
 static int pd_src_vnc[TYPEC_RP_RESERVED] = {
@@ -159,6 +159,9 @@ static int cc_pull_stored = TYPEC_CC_RD;
 
 static int user_limited_max_mv = 20000;
 
+static uint8_t allow_pr_swap = 1;
+static uint8_t allow_dr_swap = 1;
+
 static uint32_t max_supported_voltage(void)
 {
 	return user_limited_max_mv;
@@ -266,7 +269,7 @@ static void board_manage_dut_port(void)
 static void update_ports(void)
 {
 	int pdo_index, src_index, snk_index, i;
-	uint32_t pdo, max_ma, max_mv;
+	uint32_t pdo, max_ma, max_mv, unused;
 
 	/*
 	 * CHG Vbus has changed states, update PDO that reflects CHG port
@@ -281,6 +284,20 @@ static void update_ports(void)
 			src_index = 0;
 			snk_index = -1;
 
+			/*
+			 * TODO: This code artificially limits PDO
+			 * to entries in pd_src_voltages_mv table
+			 *
+			 * This is artificially overconstrainted.
+			 *
+			 * Allow non-standard PDO objects so long
+			 * as they are valid. See: crrev/c/730877
+			 * for where this started.
+			 *
+			 * This needs to be rearchitected in order
+			 * to support Variable PDO passthrough.
+			 */
+
 			for (i = 0; i < ARRAY_SIZE(pd_src_voltages_mv); ++i) {
 				/* Adhere to board voltage limits */
 				if (pd_src_voltages_mv[i] >
@@ -288,8 +305,8 @@ static void update_ports(void)
 					break;
 
 				/* Find the 'best' PDO <= voltage */
-				pdo_index =
-				pd_find_pdo_index(pd_get_src_cap_cnt(CHG),
+				pdo_index = pd_find_pdo_index(
+					pd_get_src_cap_cnt(CHG),
 					pd_get_src_caps(CHG),
 					pd_src_voltages_mv[i], &pdo);
 				/* Don't duplicate PDOs */
@@ -300,20 +317,54 @@ static void update_ports(void)
 					continue;
 
 				snk_index = pdo_index;
-				pd_extract_pdo_power(pdo, &max_ma, &max_mv);
-				pd_src_chg_pdo[src_index++] =
+				pd_extract_pdo_power(pdo, &max_ma, &max_mv,
+						     &unused);
+				pd_src_chg_pdo[src_index] =
 					PDO_FIXED_VOLT(max_mv) |
-					PDO_FIXED_CURR(max_ma) |
-					DUT_PDO_FIXED_FLAGS |
-					PDO_FIXED_UNCONSTRAINED;
+					PDO_FIXED_CURR(max_ma);
+
+				if (src_index == 0) {
+					/*
+					 * TODO: 1st PDO *should* always be
+					 * vSafe5v PDO. But not always with bad
+					 * DUT. Should re-index and re-map.
+					 *
+					 * TODO: Add variable voltage PDO
+					 * conversion.
+					 */
+					pd_src_chg_pdo[src_index] &=
+						~(DUT_PDO_FIXED_FLAGS |
+						  PDO_FIXED_UNCONSTRAINED);
+
+					/*
+					 * TODO: Keep Unconstrained Power knobs
+					 * exposed and well-defined.
+					 *
+					 * Current method is workaround that
+					 * force-rejects PR_SWAPs in lieu of UP.
+					 *
+					 * Migrate to use config flag such as:
+					 * ((cc_config &
+					 * CC_UNCONSTRAINED_POWER)?
+					 * PDO_FIXED_UNCONSTRAINED:0)
+					 */
+					pd_src_chg_pdo[src_index] |=
+						(DUT_PDO_FIXED_FLAGS |
+						 PDO_FIXED_UNCONSTRAINED);
+				}
+				src_index++;
 			}
 			chg_pdo_cnt = src_index;
 		} else {
 			/* 5V PDO */
 			pd_src_chg_pdo[0] = PDO_FIXED_VOLT(PD_MIN_MV) |
-				PDO_FIXED_CURR(vbus[CHG].ma) |
-				DUT_PDO_FIXED_FLAGS |
-				PDO_FIXED_UNCONSTRAINED;
+					    PDO_FIXED_CURR(vbus[CHG].ma) |
+					    DUT_PDO_FIXED_FLAGS |
+					    PDO_FIXED_UNCONSTRAINED;
+			/*
+			 * TODO: Keep Unconstrained Power knobs
+			 * exposed and well-defined.
+			 */
 
 			chg_pdo_cnt = 1;
 		}
@@ -338,8 +389,8 @@ int board_set_active_charge_port(int charge_port)
 	return 0;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
 {
 	if (port != CHG)
 		return;
@@ -385,8 +436,9 @@ int pd_tcpc_cc_nc(int port, int cc_volt, int cc_sel)
 	if (cc_config & CC_DISABLE_DTS)
 		nc = cc_volt >= pd_src_vnc[rp_index];
 	else
-		nc = cc_volt >= pd_src_vnc_dts[rp_index][
-				cc_config & CC_POLARITY ? !cc_sel : cc_sel];
+		nc = cc_volt >=
+		     pd_src_vnc_dts[rp_index]
+				   [cc_config & CC_POLARITY ? !cc_sel : cc_sel];
 
 	return nc;
 }
@@ -412,19 +464,31 @@ int pd_tcpc_cc_ra(int port, int cc_volt, int cc_sel)
 	if (cc_config & CC_DISABLE_DTS)
 		ra = cc_volt < pd_src_rd_threshold[rp_index];
 	else
-		ra = cc_volt < pd_src_rd_threshold_dts[rp_index][
-				cc_config & CC_POLARITY ? !cc_sel : cc_sel];
+		ra = cc_volt <
+		     pd_src_rd_threshold_dts[rp_index]
+					    [cc_config & CC_POLARITY ? !cc_sel :
+								       cc_sel];
 
 	return ra;
 }
 
+/* DUT CC readings aren't valid if we aren't applying CC pulls */
+bool cc_is_valid(void)
+{
+	if ((cc_config & CC_DETACH) || (cc_pull_stored == TYPEC_CC_OPEN) ||
+	    ((cc_pull_stored == TYPEC_CC_RP) &&
+	     (rp_value_stored == TYPEC_RP_RESERVED)))
+		return false;
+	return true;
+}
+
 int pd_adc_read(int port, int cc)
 {
 	int mv = -1;
 
 	if (port == CHG)
 		mv = adc_read_channel(cc ? ADC_CHG_CC2_PD : ADC_CHG_CC1_PD);
-	else if (!(cc_config & CC_DETACH)) {
+	else if (cc_is_valid()) {
 		/*
 		 * In servo v4 hardware logic, both CC lines are wired directly
 		 * to DUT. When servo v4 as a snk, DUT may source Vconn to CC2
@@ -445,13 +509,11 @@ int pd_adc_read(int port, int cc)
 		 *
 		 * This is basically a hack faking "vOpen" from TCPCI spec.
 		 */
-		if ((cc_config & CC_DISABLE_DTS) &&
-		    port == DUT &&
+		if ((cc_config & CC_DISABLE_DTS) && port == DUT &&
 		    cc == ((cc_config & CC_POLARITY) ? 0 : 1)) {
-
-			if ((cc_pull_stored == TYPEC_CC_RD)  ||
-				(cc_pull_stored == TYPEC_CC_RA) ||
-				(cc_pull_stored == TYPEC_CC_RA_RD))
+			if ((cc_pull_stored == TYPEC_CC_RD) ||
+			    (cc_pull_stored == TYPEC_CC_RA) ||
+			    (cc_pull_stored == TYPEC_CC_RA_RD))
 				mv = -1;
 			else if (cc_pull_stored == TYPEC_CC_RP)
 				mv = 3301;
@@ -580,7 +642,7 @@ int pd_set_rp_rd(int port, int cc_pull, int rp_value)
 	if (cc_pull == TYPEC_CC_RP) {
 		rv = board_set_rp(rp_value);
 	} else if ((cc_pull == TYPEC_CC_RD) || (cc_pull == TYPEC_CC_RA_RD) ||
-				(cc_pull == TYPEC_CC_RA)) {
+		   (cc_pull == TYPEC_CC_RA)) {
 		/*
 		 * The DUT port uses a captive cable. It can present Rd on both
 		 * CC1 and CC2. If DTS mode is enabled, then present Rd on both
@@ -659,7 +721,7 @@ int charge_manager_get_source_pdo(const uint32_t **src_pdo, const int port)
 	 * port, otherwise we provide no power.
 	 */
 	if (charge_port_is_active()) {
-		*src_pdo =  pd_src_chg_pdo;
+		*src_pdo = pd_src_chg_pdo;
 		pdo_cnt = chg_pdo_cnt;
 	}
 
@@ -669,9 +731,9 @@ int charge_manager_get_source_pdo(const uint32_t **src_pdo, const int port)
 __override void pd_transition_voltage(int idx)
 {
 	timestamp_t deadline;
-	uint32_t ma, mv;
+	uint32_t ma, mv, unused;
 
-	pd_extract_pdo_power(pd_src_chg_pdo[idx - 1], &ma, &mv);
+	pd_extract_pdo_power(pd_src_chg_pdo[idx - 1], &ma, &mv, &unused);
 	/* Is this a transition to a new voltage? */
 	if (charge_port_is_active() && vbus[CHG].mv != mv) {
 		/*
@@ -683,8 +745,7 @@ __override void pd_transition_voltage(int idx)
 		/* Wait for CHG transition */
 		deadline.val = get_time().val + PD_T_PS_TRANSITION;
 		CPRINTS("Waiting for CHG port transition");
-		while (charge_port_is_active() &&
-		       vbus[CHG].mv != mv &&
+		while (charge_port_is_active() && vbus[CHG].mv != mv &&
 		       get_time().val < deadline.val)
 			msleep(10);
 
@@ -746,8 +807,7 @@ void pd_power_supply_reset(int port)
 
 int pd_snk_is_vbus_provided(int port)
 {
-	return gpio_get_level(port ? GPIO_USB_DET_PP_DUT :
-				     GPIO_USB_DET_PP_CHG);
+	return gpio_get_level(port ? GPIO_USB_DET_PP_DUT : GPIO_USB_DET_PP_CHG);
 }
 
 __override int pd_check_power_swap(int port)
@@ -764,14 +824,17 @@ __override int pd_check_power_swap(int port)
 	if (port == CHG)
 		return 0;
 
+	if (pd_get_power_role(port) == PD_ROLE_SINK &&
+	    !(cc_config & CC_ALLOW_SRC))
+		return 0;
+
 	if (pd_snk_is_vbus_provided(CHG))
-		return 1;
+		return allow_pr_swap;
 
 	return 0;
 }
 
-__override int pd_check_data_swap(int port,
-				  enum pd_data_role data_role)
+__override int pd_check_data_swap(int port, enum pd_data_role data_role)
 {
 	/*
 	 * Servo should allow data role swaps to let DUT see the USB hub, but
@@ -780,20 +843,52 @@ __override int pd_check_data_swap(int port,
 	if (port == CHG)
 		return 0;
 
-	return 1;
+	return allow_dr_swap;
 }
 
-__override void pd_execute_data_swap(int port,
-				     enum pd_data_role data_role)
+__override void pd_execute_data_swap(int port, enum pd_data_role data_role)
 {
-	/*
-	 * TODO(b/137887386): Turn on the fastboot/DFU path when data swap to
-	 * DFP?
-	 */
+	if (port == CHG)
+		return;
+
+	switch (data_role) {
+	case PD_ROLE_DFP:
+		if (cc_config & CC_FASTBOOT_DFP) {
+			dut_to_host();
+		} else {
+			/* Disable USB2 lines from DUT */
+			gpio_set_level(GPIO_FASTBOOT_DUTHUB_MUX_EN_L, 1);
+			uservo_to_host();
+		}
+		break;
+	case PD_ROLE_UFP:
+		/* Ensure that FASTBOOT is disabled */
+		gpio_set_level(GPIO_FASTBOOT_DUTHUB_MUX_SEL, 1);
+
+		/* Enable USB2 lines */
+		gpio_set_level(GPIO_FASTBOOT_DUTHUB_MUX_EN_L, 0);
+
+		/*
+		 * By default, uServo port will be enabled. Only if the user
+		 * explicitly enable CC_FASTBOOT_DFP then uServo is disabled.
+		 */
+		if (!(cc_config & CC_FASTBOOT_DFP))
+			uservo_to_host();
+		break;
+	case PD_ROLE_DISCONNECTED:
+		/* Disable USB2 lines */
+		gpio_set_level(GPIO_FASTBOOT_DUTHUB_MUX_EN_L, 1);
+
+		if (!(cc_config & CC_FASTBOOT_DFP))
+			uservo_to_host();
+		break;
+	default:
+		CPRINTS("C%d: %s: Invalid data_role:%d", port, __func__,
+			data_role);
+	}
 }
 
-__override void pd_check_pr_role(int port,
-				 enum pd_power_role pr_role,
+__override void pd_check_pr_role(int port, enum pd_power_role pr_role,
 				 int flags)
 {
 	/*
@@ -804,9 +899,7 @@ __override void pd_check_pr_role(int port,
 	 */
 }
 
-__override void pd_check_dr_role(int port,
-				 enum pd_data_role dr_role,
-				 int flags)
+__override void pd_check_dr_role(int port, enum pd_data_role dr_role, int flags)
 {
 	if (port == CHG)
 		return;
@@ -816,15 +909,14 @@ __override void pd_check_dr_role(int port,
 		pd_request_data_swap(port);
 }
 
-
 /* ----------------- Vendor Defined Messages ------------------ */
 /*
  * DP alt-mode config, user configurable.
  * Default is the mode disabled, supporting the C and D pin assignment,
  * multi-function preferred, and a plug.
  */
-static int alt_dp_config = (ALT_DP_PIN_C | ALT_DP_PIN_D | ALT_DP_MF_PREF |
-			    ALT_DP_PLUG);
+static int alt_dp_config =
+	(ALT_DP_PIN_C | ALT_DP_PIN_D | ALT_DP_MF_PREF | ALT_DP_PLUG);
 
 /**
  * Get the pins based on the user config.
@@ -857,8 +949,8 @@ const uint32_t vdo_idh = VDO_IDH(0, /* data caps as USB host */
 const uint32_t vdo_product = VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV);
 
 const uint32_t vdo_ama = VDO_AMA(CONFIG_USB_PD_IDENTITY_HW_VERS,
-				 CONFIG_USB_PD_IDENTITY_SW_VERS,
-				 0, 0, 0, 0, /* SS[TR][12] */
+				 CONFIG_USB_PD_IDENTITY_SW_VERS, 0, 0, 0,
+				 0, /* SS[TR][12] */
 				 0, /* Vconn power */
 				 0, /* Vconn power required */
 				 0, /* Vbus power required */
@@ -896,13 +988,13 @@ uint32_t vdo_dp_mode[MODE_CNT];
 
 static int svdm_response_modes(int port, uint32_t *payload)
 {
-	vdo_dp_mode[0] =
-		VDO_MODE_DP(0,             /* UFP pin cfg supported: none */
-			    alt_dp_config_pins(),  /* DFP pin */
-			    1,             /* no usb2.0 signalling in AMode */
-			    alt_dp_config_cable(), /* plug or receptacle */
-			    MODE_DP_V13,   /* DPv1.3 Support, no Gen2 */
-			    MODE_DP_SNK);  /* Its a sink only */
+	vdo_dp_mode[0] = VDO_MODE_DP(0, /* UFP pin cfg supported: none */
+				     alt_dp_config_pins(), /* DFP pin */
+				     1, /* no usb2.0 signalling in AMode */
+				     alt_dp_config_cable(), /* plug or
+							       receptacle */
+				     MODE_DP_V13, /* DPv1.3 Support, no Gen2 */
+				     MODE_DP_SNK); /* Its a sink only */
 
 	/* CCD uses the SBU lines; don't enable DP when dts-mode enabled */
 	if (!(cc_config & CC_DISABLE_DTS))
@@ -915,48 +1007,30 @@ static int svdm_response_modes(int port, uint32_t *payload)
 	return MODE_CNT + 1;
 }
 
-static int is_typec_dp_muxed(void)
-{
-	int value;
-
-	value = tusb1064_read_byte(I2C_PORT_MASTER, TUSB1064_REG_GENERAL);
-	if (value < 0 || value & REG_GENERAL_CTLSEL_4DP_LANES)
-		return 0;
-
-	return 1;
-}
-
 static void set_typec_mux(int pin_cfg)
 {
-	int value;
-
-	value = tusb1064_read_byte(I2C_PORT_MASTER, TUSB1064_REG_GENERAL);
-	if (value < 0)
-		return;
+	mux_state_t mux_mode = USB_PD_MUX_NONE;
 
-	value &= ~(REG_GENERAL_CTLSEL_4DP_LANES | REG_GENERAL_CTLSEL_USB3);
 	switch (pin_cfg) {
-	case 0:
+	case 0: /* return to USB3 only */
+		mux_mode = USB_PD_MUX_USB_ENABLED;
 		CPRINTS("PinCfg:off");
 		break;
-	case MODE_DP_PIN_C:
-		value |= REG_GENERAL_CTLSEL_4DP_LANES;
+	case MODE_DP_PIN_C: /* DisplayPort 4 lanes */
+		mux_mode = USB_PD_MUX_DP_ENABLED;
 		CPRINTS("PinCfg:C");
 		break;
-	case MODE_DP_PIN_D:
-		value |= REG_GENERAL_CTLSEL_2DP_AND_USB3;
+	case MODE_DP_PIN_D: /* DP + USB */
+		mux_mode = USB_PD_MUX_DOCK;
 		CPRINTS("PinCfg:D");
 		break;
 	default:
 		CPRINTS("PinCfg not supported: %d", pin_cfg);
 		return;
 	}
-	if (value && cc_config & CC_POLARITY)
-		value |= REG_GENERAL_FLIPSEL;
-	else
-		value &= ~REG_GENERAL_FLIPSEL;
 
-	tusb1064_write_byte(I2C_PORT_MASTER, TUSB1064_REG_GENERAL, value);
+	usb_mux_set(DUT, mux_mode, USB_SWITCH_CONNECT,
+		    !!(cc_config & CC_POLARITY));
 }
 
 static int get_hpd_level(void)
@@ -971,19 +1045,22 @@ static int dp_status(int port, uint32_t *payload)
 {
 	int opos = PD_VDO_OPOS(payload[0]);
 	int hpd = get_hpd_level();
+	mux_state_t state = usb_mux_get(DUT);
+	int dp_enabled = !!(state & USB_PD_MUX_DP_ENABLED);
 
 	if (opos != OPOS)
-		return 0;  /* NAK */
-
-	payload[1] = VDO_DP_STATUS(
-		0,                /* IRQ_HPD */
-		hpd,              /* HPD_HI|LOW */
-		0,                /* request exit DP */
-		0,                /* request exit USB */
-		(alt_dp_config & ALT_DP_MF_PREF) != 0,  /* MF pref */
-		is_typec_dp_muxed(),
-		0,                /* power low */
-		hpd ? 0x2 : 0);
+		return 0; /* NAK */
+
+	payload[1] =
+		VDO_DP_STATUS(0, /* IRQ_HPD */
+			      hpd, /* HPD_HI|LOW */
+			      0, /* request exit DP */
+			      0, /* request exit USB */
+			      (alt_dp_config & ALT_DP_MF_PREF) != 0, /* MF
+									pref
+								      */
+			      dp_enabled, 0, /* power low */
+			      hpd ? 0x2 : 0);
 
 	return 2;
 }
@@ -1004,15 +1081,15 @@ static int svdm_enter_mode(int port, uint32_t *payload)
 	/* SID & mode request is valid */
 	if ((PD_VDO_VID(payload[0]) != USB_SID_DISPLAYPORT) ||
 	    (PD_VDO_OPOS(payload[0]) != OPOS))
-		return 0;  /* NAK */
+		return 0; /* NAK */
 
 	alt_mode = OPOS;
 	return 1;
 }
 
-int pd_alt_mode(int port, enum tcpm_transmit_type type, uint16_t svid)
+int pd_alt_mode(int port, enum tcpci_msg_type type, uint16_t svid)
 {
-	if (type != TCPC_TX_SOP)
+	if (type != TCPCI_MSG_SOP)
 		return 0;
 
 	if (svid == USB_SID_DISPLAYPORT)
@@ -1046,7 +1123,7 @@ const struct svdm_response svdm_rsp = {
 };
 
 __override int pd_custom_vdm(int port, int cnt, uint32_t *payload,
-		  uint32_t **rpayload)
+			     uint32_t **rpayload)
 {
 	int cmd = PD_VDO_CMD(payload[0]);
 
@@ -1058,7 +1135,7 @@ __override int pd_custom_vdm(int port, int cnt, uint32_t *payload,
 	case VDO_CMD_VERSION:
 		/* guarantee last byte of payload is null character */
 		*(payload + cnt - 1) = 0;
-		CPRINTF("ver: %s\n", (char *)(payload+1));
+		CPRINTF("ver: %s\n", (char *)(payload + 1));
 		break;
 	case VDO_CMD_CURRENT:
 		CPRINTF("Current: %dmA\n", payload[1]);
@@ -1076,18 +1153,15 @@ static void print_cc_mode(void)
 	/* Get current CCD status */
 	ccprintf("cc: %s\n", cc_config & CC_DETACH ? "off" : "on");
 	ccprintf("dts mode: %s\n", cc_config & CC_DISABLE_DTS ? "off" : "on");
-	ccprintf("chg mode: %s\n",
-		 get_dut_chg_en() ? "on" : "off");
+	ccprintf("chg mode: %s\n", get_dut_chg_en() ? "on" : "off");
 	ccprintf("chg allowed: %s\n", cc_config & CC_ALLOW_SRC ? "on" : "off");
 	ccprintf("drp enabled: %s\n", cc_config & CC_ENABLE_DRP ? "on" : "off");
-	ccprintf("cc polarity: %s\n", cc_config & CC_POLARITY ? "cc2" :
-								"cc1");
+	ccprintf("cc polarity: %s\n", cc_config & CC_POLARITY ? "cc2" : "cc1");
 	ccprintf("pd enabled: %s\n", pd_comm_is_enabled(DUT) ? "on" : "off");
-	ccprintf("emca: %s\n", cc_config & CC_EMCA_SERVO ?
-					"emarked" : "non-emarked");
+	ccprintf("emca: %s\n",
+		 cc_config & CC_EMCA_SERVO ? "emarked" : "non-emarked");
 }
 
-
 static void do_cc(int cc_config_new)
 {
 	int chargeable;
@@ -1095,8 +1169,9 @@ static void do_cc(int cc_config_new)
 
 	if (cc_config_new != cc_config) {
 		if (!(cc_config & CC_DETACH)) {
-			/* Force detach */
-			pd_power_supply_reset(DUT);
+			/* Force detach by disabling VBUS */
+			chg_power_select(CHG_POWER_OFF);
+			dut_chg_en(0);
 			/* Always set to 0 here so both CC lines are changed */
 			cc_config &= ~(CC_DISABLE_DTS & CC_ALLOW_SRC);
 
@@ -1157,7 +1232,7 @@ static void do_cc(int cc_config_new)
 	}
 }
 
-static int command_cc(int argc, char **argv)
+static int command_cc(int argc, const char **argv)
 {
 	int cc_config_new = cc_config;
 
@@ -1188,6 +1263,10 @@ static int command_cc(int argc, char **argv)
 			cc_config_new = CONF_PDSNKDTS(cc_config_new);
 		else if (!strcasecmp(argv[1], "drpdts"))
 			cc_config_new = CONF_DRPDTS(cc_config_new);
+		else if (!strcasecmp(argv[1], "dtsoff"))
+			cc_config_new = CONF_DTSOFF(cc_config_new);
+		else if (!strcasecmp(argv[1], "dtson"))
+			cc_config_new = CONF_DTSON(cc_config_new);
 		else if (!strcasecmp(argv[1], "emca"))
 			cc_config_new |= CC_EMCA_SERVO;
 		else if (!strcasecmp(argv[1], "nonemca"))
@@ -1210,7 +1289,7 @@ static int command_cc(int argc, char **argv)
 }
 DECLARE_CONSOLE_COMMAND(cc, command_cc,
 			"[off|on|src|snk|pdsnk|drp|srcdts|snkdts|pdsnkdts|"
-			"drpdts|emca|nonemca] [cc1|cc2]",
+			"drpdts|dtsoff|dtson|emca|nonemca] [cc1|cc2]",
 			"Servo_v4 DTS and CHG mode");
 
 static void fake_disconnect_end(void)
@@ -1230,7 +1309,7 @@ static void fake_disconnect_start(void)
 }
 DECLARE_DEFERRED(fake_disconnect_start);
 
-static int cmd_fake_disconnect(int argc, char *argv[])
+static int cmd_fake_disconnect(int argc, const char *argv[])
 {
 	int delay_ms, duration_ms;
 	char *e;
@@ -1252,41 +1331,37 @@ static int cmd_fake_disconnect(int argc, char *argv[])
 	fake_pd_disconnect_duration_us = duration_ms * MSEC;
 	hook_call_deferred(&fake_disconnect_start_data, delay_ms * MSEC);
 
-	ccprintf("Fake disconnect for %d ms starting in %d ms.\n",
-		duration_ms, delay_ms);
+	ccprintf("Fake disconnect for %d ms starting in %d ms.\n", duration_ms,
+		 delay_ms);
 
 	return EC_SUCCESS;
 }
 DECLARE_CONSOLE_COMMAND(fakedisconnect, cmd_fake_disconnect,
 			"<delay_ms> <duration_ms>", NULL);
 
-static int cmd_ada_srccaps(int argc, char *argv[])
+static int cmd_ada_srccaps(int argc, const char *argv[])
 {
 	int i;
-	const uint32_t * const ada_srccaps = pd_get_src_caps(CHG);
+	const uint32_t *const ada_srccaps = pd_get_src_caps(CHG);
 
 	for (i = 0; i < pd_get_src_cap_cnt(CHG); ++i) {
-		uint32_t max_ma, max_mv;
+		uint32_t max_ma, max_mv, unused;
+
+		if (IS_ENABLED(CONFIG_USB_PD_ONLY_FIXED_PDOS) &&
+		    (ada_srccaps[i] & PDO_TYPE_MASK) != PDO_TYPE_FIXED)
+			continue;
+
+		pd_extract_pdo_power(ada_srccaps[i], &max_ma, &max_mv, &unused);
 
-		pd_extract_pdo_power(ada_srccaps[i], &max_ma, &max_mv);
 		ccprintf("%d: %dmV/%dmA\n", i, max_mv, max_ma);
 	}
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(ada_srccaps, cmd_ada_srccaps,
-			"",
+DECLARE_CONSOLE_COMMAND(ada_srccaps, cmd_ada_srccaps, "",
 			"Print adapter SrcCap");
 
-static void chg_pd_disconnect(void)
-{
-	/* Clear charger PDO on CHG port disconnected. */
-	if (pd_is_disconnected(CHG))
-		pd_set_src_caps(CHG, 0, NULL);
-}
-DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, chg_pd_disconnect, HOOK_PRIO_DEFAULT);
-
-static int cmd_dp_action(int argc, char *argv[])
+static int cmd_dp_action(int argc, const char *argv[])
 {
 	int i;
 	char *e;
@@ -1322,8 +1397,7 @@ static int cmd_dp_action(int argc, char *argv[])
 				}
 			}
 		}
-		CPRINTS("Pins: %s%s",
-			(alt_dp_config & ALT_DP_PIN_C) ? "C" : "",
+		CPRINTS("Pins: %s%s", (alt_dp_config & ALT_DP_PIN_C) ? "C" : "",
 			(alt_dp_config & ALT_DP_PIN_D) ? "D" : "");
 	} else if (!strcasecmp(argv[1], "mf")) {
 		if (argc >= 3) {
@@ -1373,10 +1447,10 @@ static int cmd_dp_action(int argc, char *argv[])
 			}
 		}
 		CPRINTS("HPD source: %s",
-			(alt_dp_config & ALT_DP_OVERRIDE_HPD) ? "overridden"
-							      : "external");
+			(alt_dp_config & ALT_DP_OVERRIDE_HPD) ? "overridden" :
+								"external");
 		CPRINTS("HPD level: %d", get_hpd_level());
-	}  else if (!strcasecmp(argv[1], "help")) {
+	} else if (!strcasecmp(argv[1], "help")) {
 		CPRINTS("Usage: usbc_action dp [enable|disable|hpd|mf|pins|"
 			"plug]");
 	}
@@ -1384,7 +1458,7 @@ static int cmd_dp_action(int argc, char *argv[])
 	return EC_SUCCESS;
 }
 
-static int cmd_usbc_action(int argc, char *argv[])
+static int cmd_usbc_action(int argc, const char *argv[])
 {
 	if (argc >= 2 && !strcasecmp(argv[1], "dp"))
 		return cmd_dp_action(argc - 1, &argv[1]);
@@ -1438,6 +1512,41 @@ static int cmd_usbc_action(int argc, char *argv[])
 		 * Drop this message if when we phase out the usbc_role control.
 		 */
 		ccprintf("CHG SRC %dmV\n", user_limited_max_mv);
+	} else if (!strcasecmp(argv[1], "drswap")) {
+		if (argc == 2) {
+			CPRINTF("allow_dr_swap = %d\n", allow_dr_swap);
+			return EC_SUCCESS;
+		}
+
+		if (argc != 3)
+			return EC_ERROR_PARAM2;
+
+		allow_dr_swap = !!atoi(argv[2]);
+
+	} else if (!strcasecmp(argv[1], "prswap")) {
+		if (argc == 2) {
+			CPRINTF("allow_pr_swap = %d\n", allow_pr_swap);
+			return EC_SUCCESS;
+		}
+
+		if (argc != 3)
+			return EC_ERROR_PARAM2;
+
+		allow_pr_swap = !!atoi(argv[2]);
+	} else if (!strcasecmp(argv[1], "fastboot")) {
+		if (argc == 2) {
+			CPRINTF("fastboot = %d\n",
+				!!(cc_config & CC_FASTBOOT_DFP));
+			return EC_SUCCESS;
+		}
+
+		if (argc != 3)
+			return EC_ERROR_PARAM2;
+
+		if (!!atoi(argv[2]))
+			cc_config |= CC_FASTBOOT_DFP;
+		else
+			cc_config &= ~CC_FASTBOOT_DFP;
 	} else {
 		return EC_ERROR_PARAM1;
 	}
@@ -1445,5 +1554,6 @@ static int cmd_usbc_action(int argc, char *argv[])
 	return EC_SUCCESS;
 }
 DECLARE_CONSOLE_COMMAND(usbc_action, cmd_usbc_action,
-			"5v|12v|20v|dev|pol0|pol1|drp|dp|chg x(x=voltage)",
+			"5v|12v|20v|dev|pol0|pol1|drp|dp|chg x(x=voltage)|"
+			"drswap [1|0]|prswap [1|0]",
 			"Set Servo v4 type-C port state");
diff --git a/board/servo_v4p1/usb_sm.c b/board/servo_v4p1/usb_sm.c
index 94b5e0c08d..4c448b7c9d 100644
--- a/board/servo_v4p1/usb_sm.c
+++ b/board/servo_v4p1/usb_sm.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,8 @@
 #include "util.h"
 
 #ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USB, format, ##args)
 #else /* CONFIG_COMMON_RUNTIME */
 #define CPRINTF(format, args...)
 #define CPRINTS(format, args...)
@@ -22,8 +22,8 @@
 struct internal_ctx {
 	usb_state_ptr last_entered;
 	uint32_t running : 1;
-	uint32_t enter	 : 1;
-	uint32_t exit	 : 1;
+	uint32_t enter : 1;
+	uint32_t exit : 1;
 };
 BUILD_ASSERT(sizeof(struct internal_ctx) ==
 	     member_size(struct sm_ctx, internal));
@@ -64,9 +64,9 @@ static usb_state_ptr shared_parent_state(usb_state_ptr a, usb_state_ptr b)
  * functions.
  */
 static void call_entry_functions(const int port,
-			       struct internal_ctx *const internal,
-			       const usb_state_ptr stop,
-			       const usb_state_ptr current)
+				 struct internal_ctx *const internal,
+				 const usb_state_ptr stop,
+				 const usb_state_ptr current)
 {
 	if (current == stop)
 		return;
@@ -91,7 +91,7 @@ static void call_entry_functions(const int port,
  * during an exit function.
  */
 static void call_exit_functions(const int port, const usb_state_ptr stop,
-			      const usb_state_ptr current)
+				const usb_state_ptr current)
 {
 	if (current == stop)
 		return;
@@ -105,7 +105,7 @@ static void call_exit_functions(const int port, const usb_state_ptr stop,
 void set_state(const int port, struct sm_ctx *const ctx,
 	       const usb_state_ptr new_state)
 {
-	struct internal_ctx * const internal = (void *) ctx->internal;
+	struct internal_ctx *const internal = (void *)ctx->internal;
 	usb_state_ptr last_state;
 	usb_state_ptr shared_parent;
 
@@ -115,8 +115,8 @@ void set_state(const int port, struct sm_ctx *const ctx,
 	 * intended state to transition into.
 	 */
 	if (internal->exit) {
-		CPRINTF("C%d: Ignoring set state to 0x%pP within 0x%pP",
-			port, new_state, ctx->current);
+		CPRINTF("C%d: Ignoring set state to 0x%p within 0x%p", port,
+			new_state, ctx->current);
 		return;
 	}
 
@@ -167,8 +167,8 @@ void set_state(const int port, struct sm_ctx *const ctx,
  * functions.
  */
 static void call_run_functions(const int port,
-			     const struct internal_ctx *const internal,
-			     const usb_state_ptr current)
+			       const struct internal_ctx *const internal,
+			       const usb_state_ptr current)
 {
 	if (!current)
 		return;
@@ -185,7 +185,7 @@ static void call_run_functions(const int port,
 
 void run_state(const int port, struct sm_ctx *const ctx)
 {
-	struct internal_ctx * const internal = (void *) ctx->internal;
+	struct internal_ctx *const internal = (void *)ctx->internal;
 
 	internal->running = true;
 	call_run_functions(port, internal, ctx->current);
diff --git a/board/servo_v4p1/usb_tc_snk_sm.c b/board/servo_v4p1/usb_tc_snk_sm.c
index f9a3966434..d76c2fe24f 100644
--- a/board/servo_v4p1/usb_tc_snk_sm.c
+++ b/board/servo_v4p1/usb_tc_snk_sm.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,15 +14,15 @@
 #include "usb_sm.h"
 #include "usb_tc_sm.h"
 
-#define EVT_TIMEOUT_NEVER  (-1)
-#define EVT_TIMEOUT_5MS    (5 * MSEC)
+#define EVT_TIMEOUT_NEVER (-1)
+#define EVT_TIMEOUT_5MS (5 * MSEC)
 
 /*
  * USB Type-C Sink
  *   See Figure 4-13 in Release 1.4 of USB Type-C Spec.
  */
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 /* Type-C Layer Flags */
 
@@ -36,9 +36,9 @@ enum usb_tc_state {
 static const struct usb_state tc_states[];
 
 /* TypeC Power strings */
-static const char * const pwr2_5_str = "5V/0.5A";
-static const char * const pwr7_5_str = "5V/1.5A";
-static const char * const pwr15_str  = "5V/3A";
+static const char *const pwr2_5_str = "5V/0.5A";
+static const char *const pwr7_5_str = "5V/1.5A";
+static const char *const pwr15_str = "5V/3A";
 
 static struct type_c {
 	/* state machine context */
@@ -101,8 +101,8 @@ static void print_alt_power(void)
 	char const *pwr;
 
 	cc = tc.polarity ? tc.cc2 : tc.cc1;
-	if (cc == TYPEC_CC_VOLT_OPEN ||
-		cc == TYPEC_CC_VOLT_RA || cc == TYPEC_CC_VOLT_RD) {
+	if (cc == TYPEC_CC_VOLT_OPEN || cc == TYPEC_CC_VOLT_RA ||
+	    cc == TYPEC_CC_VOLT_RD) {
 		/* Supply removed or not detected */
 		return;
 	}
@@ -288,4 +288,3 @@ void snk_task(void *u)
 		run_state(0, &tc.ctx);
 	}
 }
-
diff --git a/board/shotzo/board.c b/board/shotzo/board.c
new file mode 100644
index 0000000000..6ae6d8e55c
--- /dev/null
+++ b/board/shotzo/board.c
@@ -0,0 +1,490 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Shotzo board-specific configuration */
+
+#include "adc_chip.h"
+#include "button.h"
+#include "cbi_fw_config.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "cros_board_info.h"
+#include "driver/charger/sm5803.h"
+#include "driver/led/oz554.h"
+#include "driver/tcpm/it83xx_pd.h"
+#include "driver/tcpm/ps8xxx.h"
+#include "driver/temp_sensor/thermistor.h"
+#include "driver/usb_mux/it5205.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "intc.h"
+#include "power.h"
+#include "power_button.h"
+#include "switch.h"
+#include "system.h"
+#include "task.h"
+#include "tcpm/tcpci.h"
+#include "temp_sensor.h"
+#include "uart.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+
+#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+
+#define INT_RECHECK_US 5000
+
+uint32_t board_version;
+
+/* GPIO to enable/disable the USB Type-A port. */
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_USB_A_5V,
+};
+
+/* C0 interrupt line triggered by charger */
+static void check_c0_line(void);
+DECLARE_DEFERRED(check_c0_line);
+
+static void notify_c0_chips(void)
+{
+	sm5803_interrupt(0);
+}
+
+static void check_c0_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		notify_c0_chips();
+		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+	}
+}
+
+static void usb_c0_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c0_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c0_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+}
+
+static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
+{
+	cprints(CC_USBPD, "C0: CC OVP, SBU OVP, or thermal event");
+	pd_handle_cc_overvoltage(0);
+}
+
+/******************************************************************************/
+/*
+ * Barrel jack power supply handling
+ *
+ * EN_PPVAR_BJ_ADP_L must default active to ensure we can power on when the
+ * barrel jack is connected, and the USB-C port can bring the EC up fine in
+ * dead-battery mode. Both the USB-C and barrel jack switches do reverse
+ * protection, so we're safe to turn one on then the other off- but we should
+ * only do that if the system is off since it might still brown out.
+ */
+
+static int barrel_jack_adapter_is_present(void)
+{
+	/* Shotzo barrel jack adapter present pin is active low. */
+	return !gpio_get_level(GPIO_BJ_ADP_PRESENT_L);
+}
+
+/*
+ * Barrel-jack power adapter ratings.
+ */
+
+#define BJ_ADP_RATING_DEFAULT 0 /* BJ power ratings default */
+static const struct {
+	int voltage;
+	int current;
+} bj_power[] = {
+	{ /* 0 - 90W (also default) */
+	  .voltage = 19500,
+	  .current = 4500 },
+};
+
+/* Debounced connection state of the barrel jack */
+static int8_t adp_connected = -1;
+static void adp_connect_deferred(void)
+{
+	struct charge_port_info pi = { 0 };
+	int connected = barrel_jack_adapter_is_present();
+
+	/* Debounce */
+	if (connected == adp_connected)
+		return;
+	if (connected) {
+		unsigned int bj = BJ_ADP_RATING_DEFAULT;
+
+		pi.voltage = bj_power[bj].voltage;
+		pi.current = bj_power[bj].current;
+	}
+	charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED,
+				     DEDICATED_CHARGE_PORT, &pi);
+	adp_connected = connected;
+}
+DECLARE_DEFERRED(adp_connect_deferred);
+
+#define ADP_DEBOUNCE_MS 1000 /* Debounce time for BJ plug/unplug */
+/* IRQ for BJ plug/unplug. It shouldn't be called if BJ is the power source. */
+static void adp_connect_interrupt(enum gpio_signal signal)
+{
+	hook_call_deferred(&adp_connect_deferred_data, ADP_DEBOUNCE_MS * MSEC);
+}
+static void adp_state_init(void)
+{
+	/*
+	 * Initialize all charge suppliers to 0. The charge manager waits until
+	 * all ports have reported in before doing anything.
+	 */
+	for (int i = 0; i < CHARGE_PORT_COUNT; i++) {
+		for (int j = 0; j < CHARGE_SUPPLIER_COUNT; j++)
+			charge_manager_update_charge(j, i, NULL);
+	}
+
+	/* Report charge state from the barrel jack. */
+	adp_connect_deferred();
+}
+DECLARE_HOOK(HOOK_INIT, adp_state_init, HOOK_PRIO_INIT_CHARGE_MANAGER + 1);
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	[ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH0 },
+	[ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH2 },
+	[ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH3 },
+	[ADC_SUB_ANALOG] = { .name = "SUB_ANALOG",
+			     .factor_mul = ADC_MAX_MVOLT,
+			     .factor_div = ADC_READ_MAX + 1,
+			     .shift = 0,
+			     .channel = CHIP_ADC_CH13 },
+	[ADC_TEMP_SENSOR_3] = { .name = "TEMP_SENSOR3",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH15 },
+	[ADC_TEMP_SENSOR_4] = { .name = "TEMP_SENSOR4",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH16 },
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* Charger chips */
+const struct charger_config_t
+	chg_chips[] = { [CHARGER_SOLO] = {
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = SM5803_ADDR_CHARGER_FLAGS,
+				.drv = &sm5803_drv,
+			} };
+
+/* TCPCs */
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { {
+	.bus_type = EC_BUS_TYPE_EMBEDDED,
+	.drv = &it83xx_tcpm_drv,
+} };
+
+/* USB Muxes */
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = 0,
+			.i2c_port = I2C_PORT_USB_C0,
+			.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+			.driver = &it5205_usb_mux_driver,
+		},
+} };
+
+void oz554_board_init(void)
+{
+	int panel_id = 0;
+	int oz554_id;
+
+	oz554_id = gpio_get_level(GPIO_BL_OZ554_ID);
+	panel_id |= gpio_get_level(GPIO_PANEL_ID0) << 0;
+	panel_id |= gpio_get_level(GPIO_PANEL_ID1) << 1;
+	panel_id |= gpio_get_level(GPIO_PANEL_ID2) << 2;
+	panel_id |= gpio_get_level(GPIO_PANEL_ID3) << 3;
+
+	if (oz554_id == 0)
+		CPRINTUSB("OZ554ELN");
+	else if (oz554_id == 1)
+		CPRINTUSB("OZ554ALN");
+	else
+		CPRINTUSB("OZ554A UNKNOWN");
+
+	switch (panel_id) {
+	case 0x00:
+		CPRINTUSB("PANEL M238HAN");
+		oz554_set_config(0, 0xF1);
+		oz554_set_config(1, 0x43);
+		oz554_set_config(2, 0x44);
+		oz554_set_config(5, 0xBF);
+		break;
+	case 0x08:
+		CPRINTUSB("PANEL MV238FHM");
+		oz554_set_config(0, 0xF1);
+		oz554_set_config(1, 0x43);
+		oz554_set_config(2, 0x3C);
+		oz554_set_config(5, 0xD7);
+		break;
+	default:
+		CPRINTUSB("PANEL UNKNOWN");
+		break;
+	}
+}
+
+void board_init(void)
+{
+	int on;
+
+	gpio_enable_interrupt(GPIO_BJ_ADP_PRESENT_L);
+
+	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
+
+	/* Store board version for use in determining charge limits */
+	cbi_get_board_version(&board_version);
+
+	/*
+	 * If interrupt lines are already low, schedule them to be processed
+	 * after inits are completed.
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL))
+		hook_call_deferred(&check_c0_line_data, 0);
+
+	gpio_enable_interrupt(GPIO_USB_C0_CCSBU_OVP_ODL);
+
+	oz554_board_init();
+	gpio_enable_interrupt(GPIO_PANEL_BACKLIGHT_EN);
+
+	/* Charger on the MB will be outputting PROCHOT_ODL and OD CHG_DET */
+	sm5803_configure_gpio0(CHARGER_SOLO, GPIO0_MODE_PROCHOT, 1);
+	sm5803_configure_chg_det_od(CHARGER_SOLO, 1);
+
+	/* Turn on 5V if the system is on, otherwise turn it off */
+	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
+			      CHIPSET_STATE_SOFT_OFF);
+	board_power_5v_enable(on);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+static void board_resume(void)
+{
+	sm5803_disable_low_power_mode(CHARGER_SOLO);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_resume, HOOK_PRIO_DEFAULT);
+
+static void board_suspend(void)
+{
+	sm5803_enable_low_power_mode(CHARGER_SOLO);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_suspend, HOOK_PRIO_DEFAULT);
+
+static void board_shutdown(void)
+{
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_shutdown, HOOK_PRIO_DEFAULT);
+
+__override void board_pulse_entering_rw(void)
+{
+	/*
+	 * On the ITE variants, the EC_ENTERING_RW signal was connected to a pin
+	 * which is active high by default.  This causes Cr50 to think that the
+	 * EC has jumped to its RW image even though this may not be the case.
+	 * The pin is changed to GPIO_EC_ENTERING_RW2.
+	 */
+	gpio_set_level(GPIO_EC_ENTERING_RW, 1);
+	gpio_set_level(GPIO_EC_ENTERING_RW2, 1);
+	usleep(MSEC);
+	gpio_set_level(GPIO_EC_ENTERING_RW, 0);
+	gpio_set_level(GPIO_EC_ENTERING_RW2, 0);
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * Nothing to do.  TCPC C0 is internal.
+	 */
+}
+
+__override void board_power_5v_enable(int enable)
+{
+	/*
+	 * Motherboard has a GPIO to turn on the 5V regulator, but the sub-board
+	 * sets it through the charger GPIO.
+	 */
+	gpio_set_level(GPIO_EN_PP5000, !!enable);
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	/*
+	 * TCPC 0 is embedded in the EC and processes interrupts in the chip
+	 * code (it83xx/intc.c)
+	 */
+	return 0;
+}
+
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
+{
+	if (port == CHARGER_SOLO) {
+		charger_set_input_current_limit(CHARGER_SOLO, max_ma);
+	}
+}
+
+__override int extpower_is_present(void)
+{
+	int port;
+	int rv;
+	bool acok;
+
+	for (port = 0; port < board_get_usb_pd_port_count(); port++) {
+		rv = sm5803_is_acok(port, &acok);
+		if ((rv == EC_SUCCESS) && acok)
+			return 1;
+	}
+
+	if (!gpio_get_level(GPIO_EN_PPVAR_BJ_ADP_L))
+		return 1;
+
+	CPRINTUSB("No external power present.");
+
+	return 0;
+}
+
+int board_set_active_charge_port(int port)
+{
+	CPRINTUSB("Requested charge port change to %d", port);
+
+	/*
+	 * The charge manager may ask us to switch to no charger if we're
+	 * running off USB-C only but upstream doesn't support PD. It requires
+	 * that we accept this switch otherwise it triggers an assert and EC
+	 * reset; it's not possible to boot the AP anyway, but we want to avoid
+	 * resetting the EC so we can continue to do the "low power" LED blink.
+	 */
+	if (port == CHARGE_PORT_NONE)
+		return EC_SUCCESS;
+
+	if (port < 0 || CHARGE_PORT_COUNT <= port)
+		return EC_ERROR_INVAL;
+
+	if (port == charge_manager_get_active_charge_port())
+		return EC_SUCCESS;
+
+	/* Don't charge from a source port */
+	if (board_vbus_source_enabled(port))
+		return EC_ERROR_INVAL;
+
+	if (!chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
+		int bj_active, bj_requested;
+
+		if (charge_manager_get_active_charge_port() != CHARGE_PORT_NONE)
+			/* Change is only permitted while the system is off */
+			return EC_ERROR_INVAL;
+
+		/*
+		 * Current setting is no charge port but the AP is on, so the
+		 * charge manager is out of sync (probably because we're
+		 * reinitializing after sysjump). Reject requests that aren't
+		 * in sync with our outputs.
+		 */
+		bj_active = !gpio_get_level(GPIO_EN_PPVAR_BJ_ADP_L);
+		bj_requested = port == CHARGE_PORT_BARRELJACK;
+		if (bj_active != bj_requested)
+			return EC_ERROR_INVAL;
+	}
+
+	CPRINTUSB("New charger p%d", port);
+
+	switch (port) {
+	case CHARGE_PORT_TYPEC0:
+		sm5803_vbus_sink_enable(CHARGER_SOLO, 1);
+		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 1);
+		break;
+	case CHARGE_PORT_BARRELJACK:
+		/* Make sure BJ adapter is sourcing power */
+		if (!barrel_jack_adapter_is_present())
+			return EC_ERROR_INVAL;
+		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 0);
+		sm5803_vbus_sink_enable(CHARGER_SOLO, 0);
+		break;
+	default:
+		return EC_ERROR_INVAL;
+	}
+
+	return EC_SUCCESS;
+}
+
+/* Vconn control for integrated ITE TCPC */
+void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
+{
+	/* Vconn control is only for port 0 */
+	if (port)
+		return;
+
+	if (cc_pin == USBPD_CC_PIN_1)
+		gpio_set_level(GPIO_EN_USB_C0_CC1_VCONN, !!enabled);
+	else
+		gpio_set_level(GPIO_EN_USB_C0_CC2_VCONN, !!enabled);
+}
+
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	int current;
+
+	if (port < 0 || port > board_get_usb_pd_port_count())
+		return;
+
+	current = (rp == TYPEC_RP_3A0) ? 3000 : 1500;
+
+	charger_set_otg_current_voltage(port, current, 5000);
+}
+
+/* Thermistors */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "Charger",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
+	[TEMP_SENSOR_4] = { .name = "5V regular",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_4 },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
diff --git a/board/shotzo/board.h b/board/shotzo/board.h
new file mode 100644
index 0000000000..c6fcceb045
--- /dev/null
+++ b/board/shotzo/board.h
@@ -0,0 +1,116 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Shotzo board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* Select Baseboard features */
+#define VARIANT_DEDEDE_EC_IT8320
+#include "baseboard.h"
+
+/* Charger */
+#define CONFIG_CHARGER
+#define CONFIG_CHARGER_SM5803 /* C0 and C1: Charger */
+#define PD_MAX_VOLTAGE_MV 15000
+#define CONFIG_USB_PD_VBUS_DETECT_CHARGER
+#define CONFIG_USB_PD_5V_CHARGER_CTRL
+#define CONFIG_CHARGER_OTG
+
+/* TCPC */
+#define CONFIG_USB_PD_PORT_MAX_COUNT 1
+#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0: ITE EC TCPC */
+#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1
+#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+#define CONFIG_USB_PD_TCPC_LOW_POWER
+
+/* Thermistors */
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_THERMISTOR
+#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
+
+/* USB Mux and Retimer */
+#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */
+
+/* USB Type A Features */
+#define USB_PORT_COUNT 1
+#define CONFIG_USB_PORT_POWER_DUMB
+
+/* Buttons */
+#define CONFIG_DEDICATED_RECOVERY_BUTTON
+#define CONFIG_DEDICATED_RECOVERY_BUTTON_2
+#define CONFIG_EMULATED_SYSRQ
+#define CONFIG_POWER_BUTTON_IGNORE_LID
+
+/* Dedicated barreljack charger port */
+#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT
+#define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1
+#define DEDICATED_CHARGE_PORT 1
+
+/* LED backlight controller */
+#define CONFIG_LED_DRIVER_OZ554
+
+/* Unused Features */
+#undef CONFIG_BACKLIGHT_LID
+#undef CONFIG_BATTERY_CUT_OFF
+#undef CONFIG_BATTERY_PRESENT_GPIO
+#undef CONFIG_BATTERY_SMART
+#undef CONFIG_BATTERY_REQUESTS_NIL_WHEN_DEAD
+#undef CONFIG_BATTERY_REVIVE_DISCONNECT
+#undef CONFIG_CMD_KEYBOARD
+#undef CONFIG_HIBERNATE
+#undef CONFIG_KEYBOARD_BOOT_KEYS
+#undef CONFIG_KEYBOARD_RUNTIME_KEYS
+#undef CONFIG_LID_SWITCH
+#undef CONFIG_USB_CHARGER
+#undef CONFIG_VOLUME_BUTTONS
+#undef GPIO_USB_C1_DP_HPD
+
+/* I2C Bus Configuration */
+#define I2C_PORT_BACKLIGHT I2C_PORT_SENSOR
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+/* ADC channels */
+enum adc_channel {
+	ADC_VSNS_PP3300_A, /* ADC0 */
+	ADC_TEMP_SENSOR_1, /* ADC2 */
+	ADC_TEMP_SENSOR_2, /* ADC3 */
+	ADC_SUB_ANALOG, /* ADC13 */
+	ADC_TEMP_SENSOR_3, /* ADC15 */
+	ADC_TEMP_SENSOR_4, /* ADC16 */
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1,
+	TEMP_SENSOR_2,
+	TEMP_SENSOR_3,
+	TEMP_SENSOR_4,
+	TEMP_SENSOR_COUNT
+};
+
+enum charge_port {
+	CHARGE_PORT_TYPEC0,
+	CHARGE_PORT_BARRELJACK,
+};
+
+/* Board specific handlers */
+void led_alert(int enable);
+#define PORT_TO_HPD(port) (GPIO_USB_C0_DP_HPD)
+
+/* Pin renaming */
+#define GPIO_AC_PRESENT GPIO_BJ_ADP_PRESENT_L
+#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_ODL
+#define GPIO_RECOVERY_L_2 GPIO_H1_EC_RECOVERY_BTN_ODL
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/shotzo/build.mk b/board/shotzo/build.mk
new file mode 100644
index 0000000000..07ea50c392
--- /dev/null
+++ b/board/shotzo/build.mk
@@ -0,0 +1,14 @@
+# -*- makefile -*-
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=it83xx
+CHIP_FAMILY:=it8320
+CHIP_VARIANT:=it8320dx
+BASEBOARD:=dedede
+
+board-y=board.o led.o usb_pd_policy.o
diff --git a/board/shotzo/ec.tasklist b/board/shotzo/ec.tasklist
new file mode 100644
index 0000000000..1447f9db15
--- /dev/null
+++ b/board/shotzo/ec.tasklist
@@ -0,0 +1,16 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, ULTRA_TASK_STACK_SIZE) \
+        TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE)
diff --git a/board/shotzo/gpio.inc b/board/shotzo/gpio.inc
new file mode 100644
index 0000000000..4a26d2631a
--- /dev/null
+++ b/board/shotzo/gpio.inc
@@ -0,0 +1,163 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+/* Power State interrupts */
+GPIO_INT(SLP_S4_L,		PIN(I, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,		PIN(H, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(SLP_S0_L,		PIN(E, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,		PIN(G, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID0,	PIN(D, 0), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(RSMRST_PWRGD_L,	PIN(E, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(CPU_C10_GATE_L,	PIN(G, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_DRAM_OD,		PIN(D, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(PG_PP1050_ST_OD,	PIN(L, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID1,	PIN(K, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_VCCIO_EXT_OD,	PIN(D, 7), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(ESPI_RESET_L, 	 PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt)
+
+GPIO_INT(H1_EC_PWR_BTN_ODL,	PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
+#ifdef CONFIG_LOW_POWER_IDLE
+/* Used to wake up the EC from Deep Doze mode when writing to console */
+GPIO_INT(UART1_RX,	 PIN(B, 0), GPIO_INT_BOTH, uart_deepsleep_interrupt)	/* UART_DBG_TX_EC_RX */
+#endif
+
+/* USB-C interrupts */
+GPIO_INT(USB_C0_INT_ODL,	PIN(K, 0), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt) /* charger */
+GPIO_INT(USB_C0_CCSBU_OVP_ODL,	PIN(K, 6), GPIO_INT_FALLING | GPIO_PULL_UP, c0_ccsbu_ovp_interrupt) /* Fault protection */
+
+/* Other interrupts */
+GPIO_INT(EC_WP_OD,		PIN(A, 6), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(BJ_ADP_PRESENT_L,	PIN(J, 1), GPIO_INT_BOTH | GPIO_PULL_UP, adp_connect_interrupt)
+GPIO_INT(PANEL_BACKLIGHT_EN,	PIN(J, 3), GPIO_INT_RISING, oz554_interrupt)
+GPIO_INT(EC_RECOVERY_BTN_ODL,	PIN(F, 1), GPIO_INT_BOTH, button_interrupt)
+GPIO_INT(H1_EC_RECOVERY_BTN_ODL,	PIN(KSI, 5), GPIO_INT_BOTH, button_interrupt)
+
+/* Power sequence GPIOs */
+GPIO(EC_AP_RTCRST,		PIN(K, 2), GPIO_OUT_LOW)
+GPIO(EC_AP_PWR_BTN_ODL,		PIN(B, 6), GPIO_ODR_HIGH)
+GPIO(EC_AP_DPWROK,		PIN(L, 7), GPIO_OUT_LOW)
+GPIO(EC_AP_RSMRST_L,		PIN(H, 0), GPIO_OUT_LOW)
+GPIO(EC_AP_WAKE_ODL,		PIN(D, 5), GPIO_ODR_HIGH)
+GPIO(SYS_RST_ODL,		PIN(D, 1), GPIO_ODR_HIGH)
+GPIO(EC_AP_SYS_PWROK,		PIN(F, 2), GPIO_OUT_LOW)
+GPIO(PG_PP5000_U_OD,		PIN(E, 3), GPIO_INPUT)
+GPIO(EN_PP3300_A,		PIN(C, 5), GPIO_OUT_LOW)
+GPIO(EC_AP_PCH_PWROK_OD,	PIN(D, 6), GPIO_ODR_LOW)
+GPIO(EN_PP5000_U,		PIN(K, 5), GPIO_OUT_LOW)
+/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
+GPIO(EN_VCCST,			PIN(D, 4), GPIO_INPUT)
+GPIO(EN_VCCIO_EXT,		PIN(B, 2), GPIO_OUT_LOW)
+GPIO(EC_PROCHOT_ODL,		PIN(I, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(EC_AP_VCCST_PWRGD_OD,	PIN(E, 5), GPIO_ODR_LOW)
+GPIO(ALL_SYS_PWRGD,		PIN(B, 7), GPIO_OUT_LOW)
+GPIO(EN_SLP_Z,			PIN(K, 3), GPIO_OUT_LOW)
+
+/* Required for icelake chipset code, but implemented through other means for dedede */
+UNIMPLEMENTED(AC_PRESENT)
+UNIMPLEMENTED(PG_EC_DSW_PWROK)
+UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
+
+/* I2C pins - Alternate function below configures I2C module on these pins */
+GPIO(EC_I2C_EEPROM_SCL,		PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SDA,		PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SCL,	PIN(C, 1), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SDA,	PIN(C, 2), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,		PIN(F, 6), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SENSOR_SDA,		PIN(F, 7), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SUB_USB_C1_SCL,	PIN(E, 0), GPIO_INPUT)
+GPIO(EC_I2C_SUB_USB_C1_SDA,	PIN(E, 7), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SCL,		PIN(A, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SDA,		PIN(A, 5), GPIO_INPUT)
+
+/* USB pins */
+GPIO(EN_USB_A_5V,			PIN(L, 6), GPIO_OUT_LOW)
+GPIO(EN_USB_C0_CC1_VCONN,	PIN(H, 4), GPIO_OUT_LOW)
+GPIO(EN_USB_C0_CC2_VCONN,	PIN(H, 6), GPIO_OUT_LOW)
+GPIO(EC_AP_USB_C0_HPD,		PIN(L, 4), GPIO_OUT_LOW)
+GPIO(USB_C0_FRS,		PIN(C, 4), GPIO_OUT_LOW)
+GPIO(HDMI_SEL_L,		PIN(C, 6), GPIO_OUT_HIGH)
+
+/* MKBP event synchronization */
+GPIO(EC_AP_MKBP_INT_L,	PIN(L, 5), GPIO_ODR_HIGH)
+
+/* Misc */
+GPIO(EC_ENTERING_RW,		PIN(G, 0), GPIO_OUT_LOW)
+GPIO(EC_ENTERING_RW2,		PIN(C, 7), GPIO_OUT_LOW)
+GPIO(CCD_MODE_ODL,		PIN(H, 5), GPIO_ODR_HIGH)
+GPIO(ECH1_PACKET_MODE,		PIN(H, 1), GPIO_OUT_LOW)
+GPIO(EN_PPVAR_BJ_ADP_L,		PIN(J, 0), GPIO_OUT_LOW)
+GPIO(EN_VBUS_PWR,		PIN(F, 3), GPIO_OUT_HIGH)
+GPIO(PANEL_ID0,			PIN(K, 4), GPIO_INPUT)
+GPIO(PANEL_ID1,			PIN(J, 4), GPIO_INPUT)
+GPIO(PANEL_ID2,			PIN(J, 5), GPIO_INPUT)
+GPIO(PANEL_ID3,			PIN(J, 6), GPIO_INPUT)
+GPIO(BL_OZ554_ID,		PIN(A, 7), GPIO_INPUT)
+GPIO(EC_CRTL,			PIN(F, 0), GPIO_OUT_LOW)
+GPIO(EC_EDID_WRITE_EN_L,	PIN(B, 5), GPIO_ODR_HIGH)
+
+/* NC pins, enable internal pull-down to avoid floating state. */
+GPIO(GPIOA0_NC, PIN(A, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOA2_NC, PIN(A, 2), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOA3_NC, PIN(A, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOC3_NC, PIN(C, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOE6_NC, PIN(E, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG3_NC, PIN(G, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG4_NC, PIN(G, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG5_NC, PIN(G, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG6_NC, PIN(G, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG7_NC, PIN(G, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOI4_NC, PIN(I, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOI6_NC, PIN(I, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOI7_NC, PIN(I, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOK7_NC, PIN(K, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOM6_NC, PIN(M, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSI0_NC, 	PIN(KSI, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSI1_NC, 	PIN(KSI, 1), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSI2_NC, 	PIN(KSI, 2), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSI3_NC, 	PIN(KSI, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSI4_NC, 	PIN(KSI, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSI6_NC, 	PIN(KSI, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSI7_NC, 	PIN(KSI, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSO0_NC, 	PIN(KSO_L, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSO1_NC, 	PIN(KSO_L, 1), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSO3_NC, 	PIN(KSO_L, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSO4_NC, 	PIN(KSO_L, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSO5_NC, 	PIN(KSO_L, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSO6_NC, 	PIN(KSO_L, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSO7_NC, 	PIN(KSO_L, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSO8_NC, 	PIN(KSO_H, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSO9_NC, 	PIN(KSO_H, 1), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSO10_NC, 	PIN(KSO_H, 2), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSO11_NC, 	PIN(KSO_H, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSO12_NC, 	PIN(KSO_H, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSO13_NC, 	PIN(KSO_H, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSO14_NC, 	PIN(KSO_H, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSO15_NC, 	PIN(KSO_H, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+
+/* LED */
+GPIO(PWR_LED_WHITE_L,	 PIN(A, 1), GPIO_OUT_HIGH)
+
+/* Alternate functions GPIO definitions */
+GPIO(EC_KSO_02_INV, PIN(KSO_L, 2), GPIO_OUT_HIGH)			/* KSO2 inverted */
+
+/* UART */
+ALTERNATE(PIN_MASK(B, BIT(0) | BIT(1)), 0, MODULE_UART, 0)		/* UART for debug */
+
+/* I2C */
+ALTERNATE(PIN_MASK(B, BIT(3) | BIT(4)), 0, MODULE_I2C, 0)		/* I2C0 */
+ALTERNATE(PIN_MASK(C, BIT(1) | BIT(2)), 0, MODULE_I2C, 0)		/* I2C1 */
+ALTERNATE(PIN_MASK(F, BIT(6) | BIT(7)), 0, MODULE_I2C, GPIO_SEL_1P8V)	/* I2C2 - 1.8V */
+ALTERNATE(PIN_MASK(E, BIT(0) | BIT(7)), 0, MODULE_I2C, 0)		/* I2C4 */
+ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), 0, MODULE_I2C, 0)		/* I2C5 */
+
+/* ADC */
+ALTERNATE(PIN_MASK(L, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0)	/* ADC13: EC_SUB_ANALOG, ADC15: TEMP_SENSOR_3, ADC16: TEMP_SENSOR_4 */
+ALTERNATE(PIN_MASK(I, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0)	/* ADC0: EC_VSNS_PP3300_A, ADC2: TEMP_SENSOR_1, ADC3: TEMP_SENSOR_2 */
diff --git a/board/shotzo/led.c b/board/shotzo/led.c
new file mode 100644
index 0000000000..9ca9e7a498
--- /dev/null
+++ b/board/shotzo/led.c
@@ -0,0 +1,242 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Power LED control for Shotzo.
+ * Solid white - active power
+ * 25% duty cycle white, 1s on and 3s off- suspend
+ * Blinking quicky white, 0.5s on and 0.5s off - alert
+ * 2 long 2 short white, long for 1s, short for 0.5s and interval
+ * is 0.5s - critical
+ * Off - shut down
+ */
+
+#include "chipset.h"
+#include "console.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "led_common.h"
+#include "timer.h"
+#include "util.h"
+
+/*
+ * Due to the CSME-Lite processing, upon startup the CPU transitions through
+ * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so
+ * delay turning off the LED during suspend/shutdown.
+ */
+#define LED_CPU_DELAY_MS (2000 * MSEC)
+
+#define POWER_LED_ON 0
+#define POWER_LED_OFF 1
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED };
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+enum led_color {
+	LED_OFF = 0,
+	LED_WHITE,
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
+};
+
+static int led_set_color_power(enum led_color color)
+{
+	switch (color) {
+	case LED_OFF:
+		gpio_set_level(GPIO_PWR_LED_WHITE_L, POWER_LED_OFF);
+		break;
+	case LED_WHITE:
+		gpio_set_level(GPIO_PWR_LED_WHITE_L, POWER_LED_ON);
+		break;
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+	return EC_SUCCESS;
+}
+
+static int led_set_color(enum ec_led_id led_id, enum led_color color)
+{
+	int rv;
+
+	switch (led_id) {
+	case EC_LED_ID_POWER_LED:
+		rv = led_set_color_power(color);
+		break;
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+	return rv;
+}
+
+/* When blinking is enabled, led will blinking according to led_blinking_array.
+ * 1 means led on, 0 means led off, restart from head after reaching the tail.
+ * The interval is LED_BLINKING_MS.
+ */
+#define LED_BLINKING_MS (500 * MSEC)
+static int *led_blinking_array;
+static int led_blinking_count;
+static int led_blinking_index;
+static void led_blinking(void);
+DECLARE_DEFERRED(led_blinking);
+static void led_blinking(void)
+{
+	uint32_t elapsed;
+	uint32_t next = 0;
+	uint32_t start = get_time().le.lo;
+	int signal;
+
+	if (led_blinking_array == NULL)
+		return;
+
+	if (led_blinking_index > (led_blinking_count - 1))
+		led_blinking_index = 0;
+
+	signal = *(led_blinking_array + led_blinking_index);
+
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED)) {
+		switch (signal) {
+		case 0:
+			led_set_color(EC_LED_ID_POWER_LED, LED_OFF);
+			led_blinking_index += 1;
+			break;
+		case 1:
+			led_set_color(EC_LED_ID_POWER_LED, LED_WHITE);
+			led_blinking_index += 1;
+			break;
+		default:
+			led_blinking_index = 0;
+		}
+	}
+
+	elapsed = get_time().le.lo - start;
+	next = elapsed < LED_BLINKING_MS ? LED_BLINKING_MS - elapsed : 0;
+	hook_call_deferred(&led_blinking_data, next);
+}
+
+static int led_suspend_array[] = { 1, 1, 0, 0, 0, 0, 0, 0 };
+const int led_suspend_count = ARRAY_SIZE(led_suspend_array);
+static void led_suspend(void)
+{
+	led_blinking_array = led_suspend_array;
+	led_blinking_count = led_suspend_count;
+	led_blinking_index = 0;
+	led_blinking();
+}
+DECLARE_DEFERRED(led_suspend);
+
+static void led_shutdown(void)
+{
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		led_set_color(EC_LED_ID_POWER_LED, LED_OFF);
+}
+DECLARE_DEFERRED(led_shutdown);
+
+static void led_suspend_hook(void)
+{
+	hook_call_deferred(&led_blinking_data, -1);
+	hook_call_deferred(&led_shutdown_data, -1);
+	hook_call_deferred(&led_suspend_data, LED_CPU_DELAY_MS);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, led_suspend_hook, HOOK_PRIO_DEFAULT);
+
+static void led_shutdown_hook(void)
+{
+	hook_call_deferred(&led_blinking_data, -1);
+	hook_call_deferred(&led_suspend_data, -1);
+	hook_call_deferred(&led_shutdown_data, LED_CPU_DELAY_MS);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, led_shutdown_hook, HOOK_PRIO_DEFAULT);
+
+static void led_resume_hook(void)
+{
+	hook_call_deferred(&led_blinking_data, -1);
+	hook_call_deferred(&led_suspend_data, -1);
+	hook_call_deferred(&led_shutdown_data, -1);
+
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		led_set_color(EC_LED_ID_POWER_LED, LED_WHITE);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, led_resume_hook, HOOK_PRIO_DEFAULT);
+
+static int led_alert_array[] = { 1, 0 };
+const int led_alert_count = ARRAY_SIZE(led_alert_array);
+void led_alert(int enable)
+{
+	if (enable) {
+		/* Overwrite the current signal */
+		hook_call_deferred(&led_blinking_data, -1);
+		led_blinking_array = led_alert_array;
+		led_blinking_count = led_alert_count;
+		led_blinking_index = 0;
+		led_blinking();
+	} else {
+		/* Restore the previous signal */
+		if (chipset_in_state(CHIPSET_STATE_ON))
+			led_resume_hook();
+		else if (chipset_in_state(CHIPSET_STATE_SUSPEND))
+			led_suspend_hook();
+		else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+			led_shutdown_hook();
+	}
+}
+
+static int led_critical_array[] = { 1, 1, 0, 1, 1, 0, 1, 0, 1, 0 };
+const int led_critical_count = ARRAY_SIZE(led_critical_array);
+void show_critical_error(void)
+{
+	hook_call_deferred(&led_blinking_data, -1);
+	led_blinking_array = led_critical_array;
+	led_blinking_count = led_critical_count;
+	led_blinking_index = 0;
+	led_blinking();
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	switch (led_id) {
+	case EC_LED_ID_POWER_LED:
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		break;
+	default:
+		break;
+	}
+}
+
+int led_set_brightness(enum ec_led_id id, const uint8_t *brightness)
+{
+	if (brightness[EC_LED_COLOR_WHITE] != 0)
+		led_set_color(id, LED_WHITE);
+	else
+		led_set_color(id, LED_OFF);
+
+	return EC_SUCCESS;
+}
+
+static int command_led(int argc, const char **argv)
+{
+	enum ec_led_id id = EC_LED_ID_POWER_LED;
+
+	if (argc < 2)
+		return EC_ERROR_PARAM_COUNT;
+
+	if (!strcasecmp(argv[1], "debug")) {
+		led_auto_control(id, !led_auto_control_is_enabled(id));
+		ccprintf("o%s\n", led_auto_control_is_enabled(id) ? "ff" : "n");
+	} else if (!strcasecmp(argv[1], "off")) {
+		led_set_color(id, LED_OFF);
+	} else if (!strcasecmp(argv[1], "white")) {
+		led_set_color(id, LED_WHITE);
+	} else if (!strcasecmp(argv[1], "alert")) {
+		led_alert(1);
+	} else if (!strcasecmp(argv[1], "crit")) {
+		show_critical_error();
+	} else if (!strcasecmp(argv[1], "resume")) {
+		led_resume_hook();
+	} else {
+		return EC_ERROR_PARAM1;
+	}
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(led, command_led, "[debug|white|off|alert|crit|resume]",
+			"Turn on/off LED.");
diff --git a/board/shotzo/usb_pd_policy.c b/board/shotzo/usb_pd_policy.c
new file mode 100644
index 0000000000..8c2b840121
--- /dev/null
+++ b/board/shotzo/usb_pd_policy.c
@@ -0,0 +1,82 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery_smart.h"
+#include "charge_manager.h"
+#include "charger.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "driver/charger/sm5803.h"
+#include "driver/tcpm/tcpci.h"
+#include "usb_pd.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+int pd_check_vconn_swap(int port)
+{
+	/* Allow VCONN swaps if the AP is on */
+	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
+}
+
+void pd_power_supply_reset(int port)
+{
+	int prev_en;
+
+	if (port < 0 || port >= board_get_usb_pd_port_count())
+		return;
+
+	prev_en = charger_is_sourcing_otg_power(port);
+
+	/* Disable Vbus */
+	charger_enable_otg_power(port, 0);
+
+	/* Discharge Vbus if previously enabled */
+	if (prev_en)
+		sm5803_set_vbus_disch(port, 1);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	enum ec_error_list rv;
+
+	/* Disable sinking */
+	rv = sm5803_vbus_sink_enable(port, 0);
+	if (rv)
+		return rv;
+
+	/* Disable Vbus discharge */
+	sm5803_set_vbus_disch(port, 0);
+
+	/* Provide Vbus */
+	charger_enable_otg_power(port, 1);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+__override bool pd_check_vbus_level(int port, enum vbus_level level)
+{
+	return sm5803_check_vbus_level(port, level);
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	return sm5803_is_vbus_present(port);
+}
+
+int board_vbus_source_enabled(int port)
+{
+	/* Ignore non-PD ports (the barrel jack). */
+	if (port >= CONFIG_USB_PD_PORT_MAX_COUNT)
+		return 0;
+	return charger_is_sourcing_otg_power(port);
+}
diff --git a/board/shotzo/vif_override.xml b/board/shotzo/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/shotzo/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/shuboz/analyzestack.yaml b/board/shuboz/analyzestack.yaml
new file mode 100644
index 0000000000..7ff5f39644
--- /dev/null
+++ b/board/shuboz/analyzestack.yaml
@@ -0,0 +1,2 @@
+remove:
+- panic_assert_fail
diff --git a/board/shuboz/battery.c b/board/shuboz/battery.c
new file mode 100644
index 0000000000..f24c50d931
--- /dev/null
+++ b/board/shuboz/battery.c
@@ -0,0 +1,154 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "battery_smart.h"
+#include "charge_state.h"
+#include "common.h"
+#include "hooks.h"
+#include "temp_sensor.h"
+#include "thermal.h"
+#include "util.h"
+
+/*
+ * Battery info for all Zork battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	/* CM1500 50Wh */
+	[BATTERY_CM1500] = {
+		.fuel_gauge = {
+			.manuf_name = "AS3GXXD3KB",
+			.device_name = "C140243",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr = 0x99,
+				.reg_mask = 0x000c,
+				.disconnect_val = 0x000c,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13200, /* mV */
+			.voltage_normal		= 11880, /* mV */
+			.voltage_min		= 9000,  /* mV */
+			.precharge_current	= 256,	 /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 45,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 60,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_CM1500;
+
+static uint16_t current_table[] = {
+	2200,
+	1800,
+	1700,
+	1600,
+};
+#define NUM_CURRENT_LEVELS ARRAY_SIZE(current_table)
+
+#define TEMP_THRESHOLD 54
+static int current_level;
+
+/* Called by hook task every hook second (1 sec) */
+static void current_update(void)
+{
+	int t, temp;
+	int rv;
+	static int Uptime;
+	static int Dntime;
+
+	rv = temp_sensor_read(TEMP_SENSOR_CHARGER, &t);
+	if (rv != EC_SUCCESS)
+		return;
+
+	temp = K_TO_C(t);
+
+	if (temp > TEMP_THRESHOLD) {
+		Dntime = 0;
+		if (Uptime < 5)
+			Uptime++;
+		else {
+			Uptime = 0;
+			current_level++;
+		}
+	} else if (current_level != 0 && temp < TEMP_THRESHOLD) {
+		Uptime = 0;
+		if (Dntime < 5)
+			Dntime++;
+		else {
+			Dntime = 0;
+			current_level--;
+		}
+	} else {
+		Uptime = 0;
+		Dntime = 0;
+	}
+
+	if (current_level < 0)
+		current_level = 0;
+	else if (current_level > NUM_CURRENT_LEVELS)
+		current_level = NUM_CURRENT_LEVELS;
+}
+DECLARE_HOOK(HOOK_SECOND, current_update, HOOK_PRIO_DEFAULT);
+
+int charger_profile_override(struct charge_state_data *curr)
+{
+	/*
+	 * Precharge must be executed when communication is failed on
+	 * dead battery.
+	 */
+	if (!(curr->batt.flags & BATT_FLAG_RESPONSIVE))
+		return 0;
+
+	if (current_level != 0) {
+		if (curr->requested_current > current_table[current_level - 1])
+			curr->requested_current =
+				current_table[current_level - 1];
+	}
+
+	return 0;
+}
+
+enum ec_status charger_profile_override_get_param(uint32_t param,
+						  uint32_t *value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+enum ec_status charger_profile_override_set_param(uint32_t param,
+						  uint32_t value)
+{
+	return EC_RES_INVALID_PARAM;
+}
diff --git a/board/shuboz/board.c b/board/shuboz/board.c
new file mode 100644
index 0000000000..81c0ebe01b
--- /dev/null
+++ b/board/shuboz/board.c
@@ -0,0 +1,629 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery_smart.h"
+#include "button.h"
+#include "cbi_ssfc.h"
+#include "cros_board_info.h"
+#include "driver/accel_kionix.h"
+#include "driver/accel_kx022.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "driver/accelgyro_icm426xx.h"
+#include "driver/accelgyro_icm_common.h"
+#include "driver/bc12/pi3usb9201.h"
+#include "driver/ppc/aoz1380_public.h"
+#include "driver/ppc/nx20p348x.h"
+#include "driver/tcpm/nct38xx.h"
+#include "driver/usb_mux/amd_fp5.h"
+#include "driver/usb_mux/ps8740.h"
+#include "driver/usb_mux/ps8743.h"
+#include "extpower.h"
+#include "fan.h"
+#include "fan_chip.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "ioexpander.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "switch.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "thermal.h"
+#include "usb_charge.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_ppc.h"
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/* This I2C moved. Temporarily detect and support the V0 HW. */
+int I2C_PORT_BATTERY = I2C_PORT_BATTERY_V1;
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* Motion sensors */
+static struct mutex g_lid_mutex;
+static struct mutex g_base_mutex;
+
+/* sensor private data */
+static struct kionix_accel_data g_kx022_data;
+static struct bmi_drv_data_t g_bmi160_data;
+static struct icm_drv_data_t g_icm426xx_data;
+
+/* Matrix to rotate accelrator into standard reference frame */
+static const mat33_fp_t lid_standard_ref = {
+	{ FLOAT_TO_FP(1), 0, 0 },
+	{ 0, FLOAT_TO_FP(-1), 0 },
+	{ 0, 0, FLOAT_TO_FP(-1) },
+};
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+					      { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
+static const mat33_fp_t base_standard_ref_icm = {
+	{ FLOAT_TO_FP(1), 0, 0 },
+	{ 0, FLOAT_TO_FP(-1), 0 },
+	{ 0, 0, FLOAT_TO_FP(-1) },
+};
+
+/* TODO(gcc >= 5.0) Remove the casts to const pointer at rot_standard_ref */
+struct motion_sensor_t icm426xx_base_accel = {
+	.name = "Base Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs. */
+	.rot_standard_ref = &base_standard_ref_icm,
+	.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
+	.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100,
+		},
+	},
+};
+
+struct motion_sensor_t icm426xx_base_gyro = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &base_standard_ref_icm,
+	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
+	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
+};
+
+struct motion_sensor_t motion_sensors[] = {
+	[LID_ACCEL] = {
+	 .name = "Lid Accel",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_KX022,
+	 .type = MOTIONSENSE_TYPE_ACCEL,
+	 .location = MOTIONSENSE_LOC_LID,
+	 .drv = &kionix_accel_drv,
+	 .mutex = &g_lid_mutex,
+	 .drv_data = &g_kx022_data,
+	 .port = I2C_PORT_SENSOR,
+	 .i2c_spi_addr_flags = KX022_ADDR0_FLAGS,
+	 .rot_standard_ref = &lid_standard_ref,
+	 .default_range = 2, /* g, enough for laptop. */
+	 .min_frequency = KX022_ACCEL_MIN_FREQ,
+	 .max_frequency = KX022_ACCEL_MAX_FREQ,
+	 .config = {
+		 /* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100,
+		},
+		 /* Sensor on for lid angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	},
+	},
+
+	[BASE_ACCEL] = {
+	 .name = "Base Accel",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_BMI160,
+	 .type = MOTIONSENSE_TYPE_ACCEL,
+	 .location = MOTIONSENSE_LOC_BASE,
+	 .drv = &bmi160_drv,
+	 .mutex = &g_base_mutex,
+	 .drv_data = &g_bmi160_data,
+	 .port = I2C_PORT_SENSOR,
+	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+	 .default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
+	 .rot_standard_ref = &base_standard_ref,
+	 .min_frequency = BMI_ACCEL_MIN_FREQ,
+	 .max_frequency = BMI_ACCEL_MAX_FREQ,
+	 .config = {
+		 /* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+		/* Sensor on for angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	 },
+	},
+
+	[BASE_GYRO] = {
+	 .name = "Base Gyro",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_BMI160,
+	 .type = MOTIONSENSE_TYPE_GYRO,
+	 .location = MOTIONSENSE_LOC_BASE,
+	 .drv = &bmi160_drv,
+	 .mutex = &g_base_mutex,
+	 .drv_data = &g_bmi160_data,
+	 .port = I2C_PORT_SENSOR,
+	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+	 .default_range = 1000, /* dps */
+	 .rot_standard_ref = &base_standard_ref,
+	 .min_frequency = BMI_GYRO_MIN_FREQ,
+	 .max_frequency = BMI_GYRO_MAX_FREQ,
+	},
+};
+
+unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+static void setup_base_gyro_config(void)
+{
+	if (get_cbi_ssfc_base_sensor() == SSFC_BASE_GYRO_ICM426XX) {
+		motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
+		motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
+		ccprints("BASE GYRO is ICM426XX");
+	} else
+		ccprints("BASE GYRO is BMI160");
+}
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	if (get_cbi_ssfc_base_sensor() == SSFC_BASE_GYRO_ICM426XX)
+		icm426xx_interrupt(signal);
+	else
+		bmi160_interrupt(signal);
+}
+
+/*****************************************************************************
+ * Board suspend / resume
+ */
+
+static void board_chipset_resume(void)
+{
+	ioex_set_level(IOEX_USB_A1_RETIMER_EN, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
+
+static void board_chipset_suspend(void)
+{
+	ioex_set_level(IOEX_USB_A1_RETIMER_EN, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
+
+static int board_ps8743_mux_set(const struct usb_mux *me, mux_state_t mux_state)
+{
+	int res;
+
+	if (mux_state & USB_PD_MUX_DP_ENABLED)
+		/* Enable IN_HPD on the DB */
+		ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 1);
+	else
+		/* Disable IN_HPD on the DB */
+		ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 0);
+
+	res = ps8743_write(me, PS8743_REG_USB_EQ_RX, 0xB0);
+	return res;
+}
+
+/*****************************************************************************
+ * USB-C
+ */
+
+/*
+ * USB C0 port SBU mux use standalone FSUSB42UMX
+ * chip and it need a board specific driver.
+ * Overall, it will use chained mux framework.
+ */
+static int fsusb42umx_set_mux(const struct usb_mux *me, mux_state_t mux_state,
+			      bool *ack_required)
+{
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
+	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
+		ioex_set_level(IOEX_USB_C0_SBU_FLIP, 1);
+	else
+		ioex_set_level(IOEX_USB_C0_SBU_FLIP, 0);
+
+	return EC_SUCCESS;
+}
+
+/*
+ * .init is not necessary here because it has nothing
+ * to do. Primary mux will handle mux state so .get is
+ * not needed as well. usb_mux.c can handle the situation
+ * properly.
+ */
+const struct usb_mux_driver usbc0_sbu_mux_driver = {
+	.set = fsusb42umx_set_mux,
+};
+
+/*
+ * Since FSUSB42UMX is not a i2c device, .i2c_port and
+ * .i2c_addr_flags are not required here.
+ */
+const struct usb_mux_chain usbc0_sbu_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &usbc0_sbu_mux_driver,
+		},
+};
+
+struct usb_mux_chain usbc1_amd_fp5_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.i2c_port = I2C_PORT_USB_AP_MUX,
+			.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
+			.driver = &amd_fp5_usb_mux_driver,
+			.flags = USB_MUX_FLAG_SET_WITHOUT_FLIP,
+		},
+};
+
+struct usb_mux_chain usb_muxes[] = {
+	[USBC_PORT_C0] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.i2c_port = I2C_PORT_USB_AP_MUX,
+			.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
+			.driver = &amd_fp5_usb_mux_driver,
+		},
+		.next = &usbc0_sbu_mux,
+	},
+	[USBC_PORT_C1] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.i2c_port = I2C_PORT_TCPC1,
+			.i2c_addr_flags = PS8743_I2C_ADDR1_FLAG,
+			.driver = &ps8743_usb_mux_driver,
+			.board_set = &board_ps8743_mux_set,
+		},
+		.next = &usbc1_amd_fp5_usb_mux,
+	}
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
+
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C0] = {
+		/* Device does not talk I2C */
+		.drv = &aoz1380_drv
+	},
+
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_TCPC1,
+		.i2c_addr_flags = NX20P3483_ADDR1_FLAGS,
+		.drv = &nx20p348x_drv
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_FAULT_ODL:
+		aoz1380_interrupt(USBC_PORT_C0);
+		break;
+
+	case GPIO_USB_C1_PPC_INT_ODL:
+		/*
+		 * Sensitive only to falling edges; GPIO is configured for both
+		 * because this input may be used for HDMI HPD instead.
+		 */
+		if (!gpio_get_level(signal))
+			nx20p348x_interrupt(USBC_PORT_C1);
+		break;
+
+	default:
+		break;
+	}
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int i;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTSUSB("Disabling all charger ports");
+
+		/* Disable all ports. */
+		for (i = 0; i < ppc_cnt; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (ppc_vbus_sink_enable(i, 0))
+				CPRINTSUSB("Disabling C%d as sink failed.", i);
+		}
+
+		return EC_SUCCESS;
+	} else if (!is_valid_port) {
+		return EC_ERROR_INVAL;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (ppc_is_sourcing_vbus(port)) {
+		CPRINTFUSB("Skip enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTSUSB("New charge port: C%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < ppc_cnt; i++) {
+		if (i == port)
+			continue;
+
+		if (ppc_vbus_sink_enable(i, 0))
+			CPRINTSUSB("C%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTSUSB("C%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+void board_overcurrent_event(int port, int is_overcurrented)
+{
+	switch (port) {
+	case USBC_PORT_C0:
+		ioex_set_level(IOEX_USB_C0_FAULT_ODL, !is_overcurrented);
+		break;
+
+	case USBC_PORT_C1:
+		ioex_set_level(IOEX_USB_C1_FAULT_ODL, !is_overcurrented);
+		break;
+
+	default:
+		break;
+	}
+}
+
+const struct tcpc_config_t tcpc_config[] = {
+	[USBC_PORT_C0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TCPC0,
+			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+	},
+	[USBC_PORT_C1] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TCPC1,
+			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
+BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
+
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_TCPC0,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_TCPC1,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
+
+static void reset_nct38xx_port(int port)
+{
+	enum gpio_signal reset_gpio_l;
+
+	if (port == USBC_PORT_C0)
+		reset_gpio_l = GPIO_USB_C0_TCPC_RST_L;
+	else if (port == USBC_PORT_C1)
+		reset_gpio_l = GPIO_USB_C1_TCPC_RST_L;
+	else
+		/* Invalid port: do nothing */
+		return;
+
+	gpio_set_level(reset_gpio_l, 0);
+	msleep(NCT38XX_RESET_HOLD_DELAY_MS);
+	gpio_set_level(reset_gpio_l, 1);
+	nct38xx_reset_notify(port);
+	if (NCT3807_RESET_POST_DELAY_MS != 0)
+		msleep(NCT3807_RESET_POST_DELAY_MS);
+}
+
+void board_reset_pd_mcu(void)
+{
+	/* Reset TCPC0 */
+	reset_nct38xx_port(USBC_PORT_C0);
+
+	/* Reset TCPC1 */
+	reset_nct38xx_port(USBC_PORT_C1);
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	/*
+	 * Check which port has the ALERT line set and ignore if that TCPC has
+	 * its reset line active.
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL)) {
+		if (gpio_get_level(GPIO_USB_C0_TCPC_RST_L) != 0)
+			status |= PD_STATUS_TCPC_ALERT_0;
+	}
+
+	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL)) {
+		if (gpio_get_level(GPIO_USB_C1_TCPC_RST_L) != 0)
+			status |= PD_STATUS_TCPC_ALERT_1;
+	}
+
+	return status;
+}
+
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	int port = -1;
+
+	switch (signal) {
+	case GPIO_USB_C0_TCPC_INT_ODL:
+		port = 0;
+		break;
+	case GPIO_USB_C1_TCPC_INT_ODL:
+		port = 1;
+		break;
+	default:
+		return;
+	}
+
+	schedule_deferred_pd_interrupt(port);
+}
+
+void bc12_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_BC12_INT_ODL:
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+		break;
+
+	case GPIO_USB_C1_BC12_INT_ODL:
+		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+		break;
+
+	default:
+		break;
+	}
+}
+
+int board_pd_set_frs_enable(int port, int enable)
+{
+	int rv = EC_SUCCESS;
+
+	/* Use the TCPC to enable fast switch when FRS included */
+	if (port == USBC_PORT_C0) {
+		rv = ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN, !!enable);
+	} else {
+		rv = ioex_set_level(IOEX_USB_C1_TCPC_FASTSW_CTL_EN, !!enable);
+	}
+
+	return rv;
+}
+
+static void setup_fw_config(void)
+{
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_PPC_FAULT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
+
+	/* Enable BC 1.2 interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
+
+	/* Enable SBU fault interrupts */
+	ioex_enable_interrupt(IOEX_USB_C0_SBU_FAULT_ODL);
+	ioex_enable_interrupt(IOEX_USB_C1_SBU_FAULT_DB_ODL);
+
+	/* Config Thermal params */
+	thermal_params[0].temp_host[EC_TEMP_THRESH_HIGH] = C_TO_K(72);
+	thermal_params[0].temp_host[EC_TEMP_THRESH_HALT] = C_TO_K(80);
+	thermal_params[0].temp_host_release[EC_TEMP_THRESH_HIGH] = C_TO_K(67);
+	thermal_params[1].temp_host[EC_TEMP_THRESH_HIGH] = C_TO_K(72);
+	thermal_params[1].temp_host[EC_TEMP_THRESH_HALT] = C_TO_K(80);
+	thermal_params[1].temp_host_release[EC_TEMP_THRESH_HIGH] = C_TO_K(67);
+
+	if (ec_config_has_lid_angle_tablet_mode()) {
+		setup_base_gyro_config();
+		/* Enable Gyro interrupts */
+		gpio_enable_interrupt(GPIO_6AXIS_INT_L);
+	} else {
+		motion_sensor_count = 0;
+		/* Device is clamshell only */
+		tablet_set_mode(0, TABLET_TRIGGER_LID);
+		/* Gyro is not present, don't allow line to float */
+		gpio_set_flags(GPIO_6AXIS_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
+	}
+}
+/*
+ * Use HOOK_PRIO_INIT_I2C + 2 to be after ioex_init().
+ */
+DECLARE_HOOK(HOOK_INIT, setup_fw_config, HOOK_PRIO_INIT_I2C + 2);
+
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_KBLIGHT] = {
+		.channel = 3,
+		.flags = PWM_CONFIG_DSLEEP,
+		.freq = 100,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+struct ioexpander_config_t ioex_config[] = {
+	[IOEX_C0_NCT3807] = {
+		.i2c_host_port = I2C_PORT_TCPC0,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+	},
+	[IOEX_C1_NCT3807] = {
+		.i2c_host_port = I2C_PORT_TCPC1,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT);
+
+int usb_port_enable[USBA_PORT_COUNT] = {
+	IOEX_EN_USB_A0_5V,
+	IOEX_EN_USB_A1_5V_DB,
+};
diff --git a/board/shuboz/board.h b/board/shuboz/board.h
new file mode 100644
index 0000000000..64e54fc7a2
--- /dev/null
+++ b/board/shuboz/board.h
@@ -0,0 +1,163 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Trembyle board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#define VARIANT_ZORK_DALBOZ
+
+#include "baseboard.h"
+
+#include <stdbool.h>
+
+#define CONFIG_USBC_PPC_NX20P3483
+#define CONFIG_USB_MUX_PS8740
+#define CONFIG_USB_MUX_PS8743
+#define CONFIG_USB_MUX_RUNTIME_CONFIG
+
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#define CONFIG_USB_PORT_ENABLE_DYNAMIC
+
+#undef PD_MAX_POWER_MW
+#define PD_MAX_POWER_MW 45000
+#undef PD_MAX_CURRENT_MA
+#define PD_MAX_CURRENT_MA 3000
+#undef CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
+#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 40000
+
+#define CONFIG_CHARGER_PROFILE_OVERRIDE
+
+/* USB-A config */
+#define GPIO_USB1_ILIM_SEL IOEX_USB_A0_CHARGE_EN_L
+#define GPIO_USB2_ILIM_SEL IOEX_USB_A1_CHARGE_EN_DB_L
+
+/* Power  LEDs */
+#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
+
+/* Motion sensing drivers */
+#define CONFIG_ACCELGYRO_BMI160
+#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+#define CONFIG_ACCELGYRO_ICM426XX
+#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+#define CONFIG_ACCEL_KX022
+#define CONFIG_CMD_ACCELS
+#define CONFIG_CMD_ACCEL_INFO
+#define CONFIG_TABLET_MODE
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_UPDATE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+
+/*
+ * Jelboz's battery takes several seconds to come back out of its disconnect
+ * state (~4 seconds on the unit I have, so give it a little more for margin).
+ */
+#undef CONFIG_POWER_BUTTON_INIT_TIMEOUT
+#define CONFIG_POWER_BUTTON_INIT_TIMEOUT 5
+
+/* GPIO mapping from board specific name to EC common name. */
+#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL
+#define CONFIG_SCI_GPIO GPIO_EC_FCH_SCI_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_AP_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_EDP_BL_DISABLE
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PCH_PWRBTN_L GPIO_EC_FCH_PWR_BTN_L
+#define GPIO_PCH_RSMRST_L GPIO_EC_FCH_RSMRST_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L
+#define GPIO_PCH_SYS_PWROK GPIO_EC_FCH_PWROK
+#define GPIO_PCH_WAKE_L GPIO_EC_FCH_WAKE_L
+#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL
+#define GPIO_S0_PGOOD GPIO_S0_PWROK_OD
+#define GPIO_S5_PGOOD GPIO_EC_PWROK_OD
+#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L
+#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
+
+#ifndef __ASSEMBLER__
+
+/* This I2C moved. Temporarily detect and support the V0 HW. */
+extern int I2C_PORT_BATTERY;
+
+enum adc_channel { ADC_TEMP_SENSOR_CHARGER, ADC_TEMP_SENSOR_SOC, ADC_CH_COUNT };
+
+enum battery_type {
+	BATTERY_CM1500,
+	BATTERY_TYPE_COUNT,
+};
+
+enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_COUNT };
+
+enum ioex_port { IOEX_C0_NCT3807 = 0, IOEX_C1_NCT3807, IOEX_PORT_COUNT };
+
+#define PORT_TO_HPD(port) ((port == 0) ? GPIO_USB3_C0_DP2_HPD : GPIO_DP1_HPD)
+
+enum temp_sensor_id {
+	TEMP_SENSOR_CHARGER = 0,
+	TEMP_SENSOR_SOC,
+	TEMP_SENSOR_CPU,
+	TEMP_SENSOR_COUNT
+};
+
+enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT };
+
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
+
+/*****************************************************************************
+ * CBI EC FW Configuration
+ */
+/**
+ * SHUBOZ_MB_USBAC
+ *	USB-A0  Speed: 5 Gbps
+ *		Retimer: none
+ *	USB-C0  Speed: 5 Gbps
+ *		Retimer: none
+ *		TCPC: NCT3807
+ *		PPC: AOZ1380
+ *		IOEX: TCPC
+ */
+enum ec_cfg_usb_mb_type {
+	SHUBOZ_MB_USBAC = 0,
+};
+
+/**
+ * SHUBOZ_DB_D_OPT1_USBAC
+ *	USB-A1  Speed: 5 Gbps
+ *		Retimer: TUSB522
+ *	USB-C1  Speed: 5 Gbps
+ *		Retimer: PS8740
+ *		TCPC: NCT3807
+ *		PPC: NX20P3483
+ *		IOEX: TCPC
+ *	HDMI    Exists: no
+ *		Retimer: none
+ *		MST Hub: none
+ */
+enum ec_cfg_usb_db_type {
+	SHUBOZ_DB_D_OPT1_USBAC = 0,
+};
+
+#include "cbi_ec_fw_config.h"
+
+void board_reset_pd_mcu(void);
+
+/* Common definition for the USB PD interrupt handlers. */
+void tcpc_alert_event(enum gpio_signal signal);
+void bc12_interrupt(enum gpio_signal signal);
+void ppc_interrupt(enum gpio_signal signal);
+void motion_interrupt(enum gpio_signal signal);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/shuboz/build.mk b/board/shuboz/build.mk
new file mode 100644
index 0000000000..45c71f962c
--- /dev/null
+++ b/board/shuboz/build.mk
@@ -0,0 +1,15 @@
+# -*- makefile -*-
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx7
+CHIP_VARIANT:=npcx7m7wc
+BASEBOARD:=zork
+
+board-y=board.o led.o
+board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/shuboz/ec.tasklist b/board/shuboz/ec.tasklist
new file mode 100644
index 0000000000..abc796f74f
--- /dev/null
+++ b/board/shuboz/ec.tasklist
@@ -0,0 +1,26 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/shuboz/gpio.inc b/board/shuboz/gpio.inc
new file mode 100644
index 0000000000..c824a80cd4
--- /dev/null
+++ b/board/shuboz/gpio.inc
@@ -0,0 +1,134 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(3, 4), GPIO_INT_FALLING,			tcpc_alert_event)
+GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(F, 1), GPIO_INT_FALLING,			tcpc_alert_event)
+GPIO_INT(USB_C0_PPC_FAULT_ODL,	PIN(6, 3), GPIO_INT_FALLING,			ppc_interrupt)
+/* PPC interrupts trigger on falling edge, but HDMI HPD triggers on rising edge. */
+GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(D, 4), GPIO_INT_BOTH | GPIO_PULL_UP, 	ppc_interrupt)
+GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(9, 3), GPIO_INT_FALLING | GPIO_PULL_UP,	bc12_interrupt)
+GPIO_INT(USB_C1_BC12_INT_ODL, 	PIN(A, 4), GPIO_INT_FALLING | GPIO_PULL_UP,	bc12_interrupt)
+GPIO_INT(SLP_S3_L,		PIN(7, 4), GPIO_INT_BOTH,			power_signal_interrupt)
+GPIO_INT(SLP_S5_L,		PIN(E, 0), GPIO_INT_BOTH,			power_signal_interrupt)
+GPIO_INT(S0_PWROK_OD,		PIN(5, 6), GPIO_INT_BOTH,			power_signal_interrupt)
+GPIO_INT(EC_PWROK_OD,		PIN(3, 7), GPIO_INT_BOTH,			power_signal_interrupt)
+GPIO_INT(EC_PWR_BTN_ODL,	PIN(0, 1), GPIO_INT_BOTH,			power_button_interrupt)
+GPIO_INT(LID_OPEN,		PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	lid_interrupt)
+GPIO_INT(ACOK_OD,		PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	extpower_interrupt)
+GPIO_INT(EC_WP_L,		PIN(5, 0), GPIO_INT_BOTH,			switch_interrupt)
+GPIO_INT(VOLUP_BTN_ODL,		PIN(A, 6), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
+GPIO_INT(VOLDN_BTN_ODL,		PIN(9, 5), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
+GPIO_INT(6AXIS_INT_L,		PIN(A, 0), GPIO_INT_FALLING | GPIO_PULL_UP,	motion_interrupt)
+
+/* GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an interrupt handler. */
+GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH)
+
+GPIO(3AXIS_INT_L,		PIN(9, 6), GPIO_INPUT | GPIO_PULL_DOWN)		/* 3 Axis Accel */
+GPIO(CCD_MODE_ODL,		PIN(C, 6), GPIO_INPUT)				/* Case Closed Debug Mode */
+GPIO(PROCHOT_ODL,		PIN(D, 5), GPIO_ODR_HIGH)			/* PROCHOT to SOC */
+GPIO(EC_BATT_PRES_ODL,		PIN(4, 1), GPIO_INPUT)				/* Battery Present */
+GPIO(EC_AP_INT_ODL,		PIN(A, 3), GPIO_ODR_HIGH)			/* Sensor MKBP event to SOC */
+GPIO(EN_PWR_A,			PIN(B, 7), GPIO_OUT_LOW)			/* Enable Power */
+GPIO(EC_EDP_BL_DISABLE,		PIN(A, 2), GPIO_OUT_HIGH)			/* Enable Backlight */
+GPIO(EC_ENTERING_RW,		PIN(E, 5), GPIO_OUT_LOW)			/* EC Entering RW */
+GPIO(EC_FCH_PWR_BTN_L,		PIN(6, 7), GPIO_OUT_HIGH)			/* Power Button to SOC */
+GPIO(EC_FCH_RSMRST_L,		PIN(A, 1), GPIO_OUT_LOW)			/* RSMRST# to SOC */
+GPIO(EC_FCH_PWROK,		PIN(7, 0), GPIO_OUT_LOW)			/* Power OK to SOC */
+GPIO(EC_FCH_WAKE_L,		PIN(0, 3), GPIO_OUT_HIGH)			/* Wake SOC */
+GPIO(EC_FCH_SCI_ODL,		PIN(7, 6), GPIO_ODR_HIGH)			/* SCI to SOC */
+GPIO(EC_SYS_RST_L,		PIN(C, 7), GPIO_ODR_HIGH)			/* Cold Reset to SOC */
+GPIO(USB_C0_TCPC_RST_L,		PIN(E, 1), GPIO_OUT_HIGH)			/* C0 TCPC Reset */
+GPIO(USB_C1_TCPC_RST_L,		PIN(F, 0), GPIO_OUT_HIGH)			/* C1 TCPC Reset */
+GPIO(USB3_C0_DP2_HPD,		PIN(F, 5), GPIO_OUT_LOW)			/* C0 DP Hotplug Detect */
+GPIO(DP1_HPD,			PIN(F, 4), GPIO_OUT_LOW)			/* C1 DP Hotplug Detect */
+GPIO(EC_H1_PACKET_MODE,		PIN(8, 6), GPIO_OUT_LOW)			/* H1 Packet Mode */
+
+UNIMPLEMENTED(PCH_SMI_L)
+
+GPIO(LED_FULL_L,		PIN(6, 0), GPIO_OUT_HIGH)
+GPIO(LED_CHRG_L,		PIN(C, 0), GPIO_OUT_HIGH)
+
+/*
+ * Dalboz has 2 DB options, with different IO expanders. IOEX_C1_NCT3807 is the
+ * OPT1 DB (USB-C1), IOEX_HDMI_PCAL6408 is the OPT2 DB (HDMI).
+ */
+
+IOEX_INT(USB_C0_SBU_FAULT_ODL,	EXPIN(IOEX_C0_NCT3807, 1, 2), GPIO_INT_FALLING, sbu_fault_interrupt)
+IOEX_INT(USB_C1_SBU_FAULT_DB_ODL, EXPIN(IOEX_C1_NCT3807, 1, 2), GPIO_INT_FALLING, sbu_fault_interrupt)
+
+IOEX(USB_C0_FAULT_ODL,		EXPIN(IOEX_C0_NCT3807, 0, 3), GPIO_ODR_HIGH)	/* C0 Fault to SOC */
+IOEX(USB_C0_TCPC_FASTSW_CTL_EN,	EXPIN(IOEX_C0_NCT3807, 0, 4), GPIO_OUT_LOW)	/* C0 FastSwitch Control */
+IOEX(USB_C1_FAULT_ODL,		EXPIN(IOEX_C0_NCT3807, 1, 0), GPIO_ODR_HIGH)	/* C1 Fault to SOC */
+IOEX(USB_C0_PPC_ILIM_3A_EN,	EXPIN(IOEX_C0_NCT3807, 1, 1), GPIO_OUT_LOW)	/* C0 3A Current Limit Enable */
+IOEX(KB_BL_EN,			EXPIN(IOEX_C0_NCT3807, 1, 3), GPIO_OUT_LOW)	/* KB Backlight Enable */
+IOEX(EN_USB_A0_5V,		EXPIN(IOEX_C0_NCT3807, 1, 5), GPIO_OUT_LOW)	/* A0 5V Source Enable */
+IOEX(USB_A0_CHARGE_EN_L,	EXPIN(IOEX_C0_NCT3807, 1, 6), GPIO_OUT_HIGH)	/* A0 5V High Current Enable */
+IOEX(USB_C0_SBU_FLIP,		EXPIN(IOEX_C0_NCT3807, 1, 7), GPIO_OUT_LOW)	/* C0 SBU Flip */
+
+IOEX(USB_A1_RETIMER_EN,		EXPIN(IOEX_C1_NCT3807, 0, 0), GPIO_OUT_LOW)	/* A1 Retimer Enable */
+IOEX(USB_C1_HPD_IN_DB,		EXPIN(IOEX_C1_NCT3807, 0, 2), GPIO_OUT_LOW)	/* C1 HPD */
+IOEX(USB_C1_TCPC_FASTSW_CTL_EN,	EXPIN(IOEX_C1_NCT3807, 0, 4), GPIO_OUT_LOW)	/* C1 FastSwitch Control */
+IOEX(USB_C1_PPC_EN_L,		EXPIN(IOEX_C1_NCT3807, 1, 3), GPIO_OUT_LOW)	/* C1 PPC Enable */
+IOEX(USB_C1_DATA_EN,		EXPIN(IOEX_C1_NCT3807, 1, 5), GPIO_OUT_HIGH)	/* C1 Retimer Enable */
+IOEX(EN_USB_A1_5V_DB,		EXPIN(IOEX_C1_NCT3807, 1, 6), GPIO_OUT_LOW)	/* A1 5V Source Enable */
+IOEX(USB_A1_CHARGE_EN_DB_L,	EXPIN(IOEX_C1_NCT3807, 1, 7), GPIO_OUT_HIGH)	/* A1 5V High Current Enable */
+
+/*
+ * The NPCX LPC driver configures and controls SCI, so PCH_SCI_ODL [PIN(7, 6)]
+ * is not defined here as GPIO.
+ */
+
+/* I2C pins - these will be reconfigured for alternate function below */
+GPIO(EC_I2C_USB_A0_C0_SCL,	PIN(B, 5), GPIO_INPUT)
+GPIO(EC_I2C_USB_A0_C0_SDA,	PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_A1_C1_SCL,	PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_A1_C1_SDA,	PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_POWER_SCL,		PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_POWER_SDA,		PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_USBC_AP_MUX_SCL,	PIN(D, 1), GPIO_INPUT)
+GPIO(EC_I2C_USBC_AP_MUX_SDA,	PIN(D, 0), GPIO_INPUT)
+GPIO(FCH_SIC,			PIN(F, 3), GPIO_INPUT)
+GPIO(FCH_SID,			PIN(F, 2), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_CBI_SCL,	PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_CBI_SDA,	PIN(3, 6), GPIO_INPUT)
+GPIO(I2C_AUDIO_USB_HUB_SCL,	PIN(E, 4), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(I2C_AUDIO_USB_HUB_SDA,	PIN(E, 3), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_BATT_SCL,		PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_BATT_SDA,		PIN(B, 2), GPIO_INPUT)
+
+ALTERNATE(PIN_MASK(6, BIT(4) | BIT(5)), 0, MODULE_UART, 0) /* Cr50 requires no pullups. */
+
+ALTERNATE(PIN_MASK(B, BIT(4) | BIT(5)), 0, MODULE_I2C, 0)			/* I2C0 */
+ALTERNATE(PIN_MASK(9, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_I2C, 0)		/* I2C1 SCL / I2C2 */
+ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)				/* I2C1 SDA */
+ALTERNATE(PIN_MASK(D, BIT(0) | BIT(1)), 0, MODULE_I2C, 0)			/* I2C3 */
+ALTERNATE(PIN_MASK(F, BIT(2) | BIT(3)), 0, MODULE_I2C, 0)			/* I2C4 */
+ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)			/* I2C5 */
+ALTERNATE(PIN_MASK(E, BIT(3) | BIT(4)), 0, MODULE_I2C, 0)			/* I2C6 */
+ALTERNATE(PIN_MASK(B, BIT(2) | BIT(3)), 0, MODULE_I2C, 0)			/* I2C7 */
+
+ALTERNATE(PIN_MASK(4, BIT(2) | BIT(3)), 0, MODULE_ADC, 0)			/* ADC2, ADC3 Temp Sensors */
+
+ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)				/* PWM3 KB Backlight */
+
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_00-01 */
+ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_02-07 */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_00-01 */
+GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW)					/* KSO_02 inverted */
+ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_03-09 */
+ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_10-12 */
+
+/* Power Switch Logic (PSL) inputs */
+ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)		/* AC_PRESENT, POWER_BUTTON_L, EC_RST_ODL */
+ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)				/* LID_OPEN */
+
+ALTERNATE(PIN_MASK(A, 0xA0), 1,  MODULE_WOV, 0) 				/* I2S_SYNC/I2S_SCLK  GPIOA5/A7 */
+ALTERNATE(PIN_MASK(B, 0x01), 1,  MODULE_WOV, 0) 				/* I2S_SDAT           GPIOB0    */
+ALTERNATE(PIN_MASK(9, 0x90), 1,  MODULE_WOV, 0) 				/* DMIC_CLK/DMIC_IN   GPIO94/97 */
diff --git a/board/shuboz/led.c b/board/shuboz/led.c
new file mode 100644
index 0000000000..dc3361ba5a
--- /dev/null
+++ b/board/shuboz/led.c
@@ -0,0 +1,103 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "chipset.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
+
+__override const int led_charge_lvl_1;
+__override const int led_charge_lvl_2 = 95;
+
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { LED_OFF, 2 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
+
+BUILD_ASSERT(ARRAY_SIZE(led_bat_state_table) == LED_NUM_STATES);
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_BATTERY_LED,
+};
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_WHITE:
+		gpio_set_level(GPIO_LED_FULL_L, LED_ON_LVL);
+		gpio_set_level(GPIO_LED_CHRG_L, LED_OFF_LVL);
+		break;
+	case EC_LED_COLOR_AMBER:
+		gpio_set_level(GPIO_LED_FULL_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_CHRG_L, LED_ON_LVL);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		gpio_set_level(GPIO_LED_FULL_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_CHRG_L, LED_OFF_LVL);
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_battery(EC_LED_COLOR_WHITE);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(EC_LED_COLOR_AMBER);
+		else
+			led_set_color_battery(LED_OFF);
+	}
+
+	return EC_SUCCESS;
+}
+
+__override enum led_states board_led_get_state(enum led_states desired_state)
+{
+	if (desired_state == STATE_BATTERY_ERROR) {
+		if (chipset_in_state(CHIPSET_STATE_ON))
+			return desired_state;
+		else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
+			return STATE_DISCHARGE_S3;
+		else
+			return STATE_DISCHARGE_S5;
+	}
+	return desired_state;
+}
diff --git a/board/shuboz/vif_override.xml b/board/shuboz/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/shuboz/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/spherion/battery.c b/board/spherion/battery.c
new file mode 100644
index 0000000000..b103a58d56
--- /dev/null
+++ b/board/spherion/battery.c
@@ -0,0 +1,112 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "battery_fuel_gauge.h"
+#include "battery_smart.h"
+#include "charge_state.h"
+#include "chipset.h"
+#include "gpio.h"
+#include "temp_sensor.h"
+#include "util.h"
+
+const struct board_batt_params board_battery_info[] = {
+	[BATTERY_C235] = {
+		.fuel_gauge = {
+			.manuf_name = "AS3GWRc3KA",
+			.device_name = "C235-41",
+			.ship_mode = {
+				.reg_addr = 0x0,
+				.reg_data = { 0x10, 0x10 },
+			},
+			.fet = {
+				.reg_addr = 0x99,
+				.reg_mask = 0x0c,
+				.disconnect_val = 0x0c,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 8800,
+			.voltage_normal		= 7700,
+			.voltage_min		= 6000,
+			.precharge_current	= 256,
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 45,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= 0,
+			.discharging_max_c	= 60,
+		},
+	},
+	/* Panasonic AP1505L Battery Information */
+	[BATTERY_PANASONIC_AP15O5L] = {
+		.fuel_gauge = {
+			.manuf_name = "PANASONIC KT00305013",
+			.device_name = "AP15O5L",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.reg_addr = 0x0,
+				.reg_mask = 0x4000,
+				.disconnect_val = 0x0,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13200,
+			.voltage_normal		= 11550, /* mV */
+			.voltage_min		= 9000, /* mV */
+			.precharge_current	= 256,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 75,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_PANASONIC_AP15O5L;
+
+int charger_profile_override(struct charge_state_data *curr)
+{
+	int charger_temp, charger_temp_c;
+	int on;
+
+	/* charge confrol if the system is on, otherwise turn it off */
+	on = chipset_in_state(CHIPSET_STATE_ON);
+	if (!on)
+		return 0;
+
+	/* charge control if outside of allowable temperature range */
+	if (curr->state == ST_CHARGE) {
+		temp_sensor_read(TEMP_SENSOR_CHARGER, &charger_temp);
+		charger_temp_c = K_TO_C(charger_temp);
+		if (charger_temp_c > 52)
+			curr->requested_current =
+				MIN(curr->requested_current, 2200);
+		else if (charger_temp_c > 48)
+			curr->requested_current =
+				MIN(curr->requested_current,
+				    CONFIG_CHARGER_MAX_INPUT_CURRENT);
+	}
+
+	return 0;
+}
+
+enum ec_status charger_profile_override_get_param(uint32_t param,
+						  uint32_t *value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+enum ec_status charger_profile_override_set_param(uint32_t param,
+						  uint32_t value)
+{
+	return EC_RES_INVALID_PARAM;
+}
diff --git a/board/spherion/board.c b/board/spherion/board.c
new file mode 100644
index 0000000000..b6df18b119
--- /dev/null
+++ b/board/spherion/board.c
@@ -0,0 +1,126 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* Spherion board configuration */
+
+#include "adc.h"
+#include "button.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "driver/accel_lis2dw12.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "driver/als_tcs3400.h"
+#include "driver/bc12/mt6360.h"
+#include "driver/bc12/pi3usb9201.h"
+#include "driver/charger/isl923x.h"
+#include "driver/ppc/syv682x.h"
+#include "driver/tcpm/it83xx_pd.h"
+#include "driver/temp_sensor/thermistor.h"
+#include "driver/usb_mux/it5205.h"
+#include "driver/usb_mux/ps8743.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "regulator.h"
+#include "spi.h"
+#include "switch.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "temp_sensor.h"
+#include "timer.h"
+#include "uart.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_ppc.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
+const struct adc_t adc_channels[] = {
+	/* Convert to mV (3000mV/1024). */
+	{ "VBUS_C0", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0, CHIP_ADC_CH0 },
+	{ "BOARD_ID_0", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH1 },
+	{ "BOARD_ID_1", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH2 },
+	/* AMON/BMON gain = 17.97 */
+	{ "CHARGER_AMON_R", ADC_MAX_MVOLT * 1000 / 17.97, ADC_READ_MAX + 1, 0,
+	  CHIP_ADC_CH3 },
+	{ "VBUS_C1", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0, CHIP_ADC_CH5 },
+	{ "CHARGER_PMON", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH6 },
+	{ "TEMP_SENSOR_CHARGER", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0,
+	  CHIP_ADC_CH7 },
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_CHARGER] = { .name = "Charger",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_30k9_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_CHARGER },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/* PWM */
+
+/*
+ * PWM channels. Must be in the exactly same order as in enum pwm_channel.
+ * There total three 16 bits clock prescaler registers for all pwm channels,
+ * so use the same frequency and prescaler register setting is required if
+ * number of pwm channel greater than three.
+ */
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_KBLIGHT] = { .channel = PWM_HW_CH_DCR2,
+			     .flags = 0,
+			     .freq_hz = 10000,
+			     .pcfsr_sel = PWM_PRESCALER_C4 },
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+static void kb_backlight_enable(void)
+{
+	gpio_set_level(GPIO_EC_KB_BL_EN, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, kb_backlight_enable, HOOK_PRIO_DEFAULT);
+
+static void kb_backlight_disable(void)
+{
+	gpio_set_level(GPIO_EC_KB_BL_EN, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, kb_backlight_disable, HOOK_PRIO_DEFAULT);
+
+void board_usb_mux_init(void)
+{
+	if (board_get_sub_board() == SUB_BOARD_TYPEC) {
+		ps8743_tune_usb_eq(usb_muxes[1].mux, PS8743_USB_EQ_TX_12_8_DB,
+				   PS8743_USB_EQ_RX_12_8_DB);
+		ps8743_field_update(usb_muxes[1].mux, PS8743_REG_DCI_CONFIG_2,
+				    PS8743_AUTO_DCI_MODE_MASK,
+				    PS8743_AUTO_DCI_MODE_FORCE_USB);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, board_usb_mux_init, HOOK_PRIO_INIT_I2C + 1);
+
+static void board_suspend(void)
+{
+	gpio_set_level(GPIO_EN_5V_USM, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_suspend, HOOK_PRIO_DEFAULT);
+
+static void board_resume(void)
+{
+	gpio_set_level(GPIO_EN_5V_USM, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_resume, HOOK_PRIO_DEFAULT);
diff --git a/board/spherion/board.h b/board/spherion/board.h
new file mode 100644
index 0000000000..3c20924605
--- /dev/null
+++ b/board/spherion/board.h
@@ -0,0 +1,97 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* Spherion board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "baseboard.h"
+
+/* Chipset config */
+
+/* Optional features */
+#define CONFIG_LTO
+#undef CONFIG_LOW_POWER_S0
+
+/*
+ * TODO: Remove this option once the VBAT no longer keeps high when
+ * system's power isn't presented.
+ */
+#define CONFIG_IT83XX_RESET_PD_CONTRACT_IN_BRAM
+
+/* Temperature sensor */
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_THERMISTOR
+#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
+
+/* LED */
+#define CONFIG_LED_ONOFF_STATES
+
+/* Keyboard features */
+#define CONFIG_KEYBOARD_REFRESH_ROW3
+
+/* Keyboard backliht */
+#define CONFIG_PWM_KBLIGHT
+
+/* Charger*/
+#define CONFIG_CHARGER_MAX_INPUT_CURRENT 3100
+#define CONFIG_CHARGER_PROFILE_OVERRIDE
+
+/* PD / USB-C / PPC */
+#define CONFIG_USB_PD_DEBUG_LEVEL 3
+#define PD_MAX_POWER_MW 65000
+#define PD_MAX_CURRENT_MA CONFIG_CHARGER_MAX_INPUT_CURRENT
+#define PD_MAX_VOLTAGE_MV 20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
+#undef CONFIG_SYV682X_HV_ILIM
+#define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_5_50
+
+/* Optional console commands */
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_SCRATCHPAD
+
+/* Sensor */
+
+/* SPI / Host Command */
+#undef CONFIG_HOSTCMD_DEBUG_MODE
+#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
+
+/* USB-A */
+#define USBA_PORT_COUNT 1
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum battery_type {
+	BATTERY_C235,
+	BATTERY_PANASONIC_AP15O5L,
+	BATTERY_TYPE_COUNT,
+};
+
+enum temp_sensor_id { TEMP_SENSOR_CHARGER, TEMP_SENSOR_COUNT };
+
+enum adc_channel {
+	ADC_VBUS_C0, /* ADC 0 */
+	ADC_BOARD_ID_0, /* ADC 1 */
+	ADC_BOARD_ID_1, /* ADC 2 */
+	ADC_CHARGER_AMON_R, /* ADC 3 */
+	ADC_VBUS_C1, /* ADC 5 */
+	ADC_CHARGER_PMON, /* ADC 6 */
+	ADC_TEMP_SENSOR_CHARGER, /* ADC 7 */
+	/* Number of ADC channels */
+	ADC_CH_COUNT,
+};
+
+enum pwm_channel {
+	PWM_CH_KBLIGHT,
+	PWM_CH_COUNT,
+};
+
+#endif /* !__ASSEMBLER__ */
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/spherion/build.mk b/board/spherion/build.mk
new file mode 100644
index 0000000000..9126acf43f
--- /dev/null
+++ b/board/spherion/build.mk
@@ -0,0 +1,14 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+
+# the IC is ITE IT8xxx2
+CHIP:=it83xx
+CHIP_FAMILY:=it8xxx2
+CHIP_VARIANT:=it81202bx_1024
+BASEBOARD:=asurada
+
+board-y+=battery.o board.o led.o
diff --git a/board/spherion/ec.tasklist b/board/spherion/ec.tasklist
new file mode 100644
index 0000000000..ea717385a0
--- /dev/null
+++ b/board/spherion/ec.tasklist
@@ -0,0 +1,21 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(PDCMD, pd_command_task, NULL, 1024) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 1024) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, 1280) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, 1280) \
+
diff --git a/board/spherion/gpio.inc b/board/spherion/gpio.inc
new file mode 100644
index 0000000000..177ccd07ca
--- /dev/null
+++ b/board/spherion/gpio.inc
@@ -0,0 +1,149 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+/* Wake Source interrupts */
+GPIO_INT(POWER_BUTTON_L,     PIN(E, 4), GPIO_INT_BOTH | GPIO_PULL_UP |
+	 GPIO_HIB_WAKE_HIGH, power_button_interrupt) /* H1_EC_PWR_BTN_ODL */
+GPIO_INT(LID_OPEN,           PIN(E, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,
+         lid_interrupt)
+
+/* Chipset interrupts */
+GPIO_INT(AP_EC_WARM_RST_REQ, PIN(D, 3), GPIO_INT_RISING | GPIO_SEL_1P8V,
+         chipset_reset_request_interrupt)
+
+/* Power sequencing interrupts */
+GPIO_INT(AP_EC_WATCHDOG_L, PIN(C, 7), GPIO_INT_BOTH | GPIO_SEL_1P8V,
+         chipset_watchdog_interrupt)
+GPIO_INT(AP_IN_SLEEP_L, PIN(F, 2),
+         GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V, power_signal_interrupt)
+GPIO_INT(PMIC_EC_PWRGD, PIN(F, 3),
+         GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V, power_signal_interrupt)
+
+/* Sensor Interrupts */
+
+/* USB-C interrupts */
+GPIO_INT(USB_C0_PPC_INT_ODL, PIN(D, 1), GPIO_INT_BOTH, ppc_interrupt)
+GPIO_INT(USB_C0_BC12_INT_ODL,PIN(J, 6), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C1_BC12_INT_L,  PIN(J, 4), GPIO_INT_FALLING, bc12_interrupt)
+
+/* Volume button interrupts */
+GPIO_INT(VOLUME_DOWN_L,      PIN(D, 5), GPIO_INT_BOTH | GPIO_PULL_UP,
+         button_interrupt) /* EC_VOLDN_BTN_ODL */
+GPIO_INT(VOLUME_UP_L,        PIN(D, 6), GPIO_INT_BOTH | GPIO_PULL_UP,
+         button_interrupt) /* EC_VOLUP_BTN_ODL */
+
+/* Other interrupts */
+GPIO_INT(AP_XHCI_INIT_DONE,  PIN(D, 2), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V,
+         usb_a0_interrupt)
+GPIO_INT(AC_PRESENT,         PIN(E, 5), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,
+         extpower_interrupt) /* AC_OK / AC_PRESENT in rev1+ */
+GPIO_INT(UART1_RX,           PIN(B, 0), GPIO_INT_FALLING,
+         uart_deepsleep_interrupt) /* UART_DEBUG_TX_EC_RX */
+GPIO_INT(WP,                 PIN(I, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V,
+         switch_interrupt) /* EC_FLASH_WP_OD */
+GPIO_INT(SPI0_CS,            PIN(M, 5), GPIO_INT_FALLING,
+         spi_event)        /* SPI slave Chip Select -- AP_SPI_EC_CS_L */
+GPIO_INT(X_EC_GPIO2,         PIN(B, 2), GPIO_ODR_HIGH, x_ec_interrupt)
+
+/* Power Sequencing Signals */
+GPIO(EC_PMIC_EN_ODL,         PIN(D, 0), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(EC_PMIC_WATCHDOG_L,     PIN(H, 0), GPIO_ODR_LOW | GPIO_SEL_1P8V)
+GPIO(EN_PP5000_A,            PIN(C, 6), GPIO_OUT_HIGH)
+GPIO(PG_MT6315_PROC_ODL,     PIN(E, 1), GPIO_INPUT)
+GPIO(PG_MT6360_ODL,          PIN(F, 1), GPIO_INPUT)
+GPIO(PG_PP5000_A_ODL,        PIN(A, 6), GPIO_INPUT)
+GPIO(EN_SLP_Z,               PIN(E, 3), GPIO_OUT_LOW)
+GPIO(SYS_RST_ODL,            PIN(B, 6), GPIO_ODR_LOW)
+GPIO(EC_BL_EN_OD,            PIN(B, 5), GPIO_ODR_LOW | GPIO_SEL_1P8V)
+
+/* MKBP event synchronization */
+GPIO(EC_INT_L,               PIN(E, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V) /* EC_AP_INT_ODL */
+
+/* USB and USBC Signals */
+GPIO(DP_AUX_PATH_SEL,        PIN(G, 0), GPIO_OUT_HIGH)
+GPIO(EC_DPBRDG_HPD_ODL,      PIN(J, 0), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(EN_PP5000_USB_A0_VBUS,  PIN(B, 7), GPIO_OUT_LOW)
+GPIO(USB_C0_FRS_EN,          PIN(H, 3), GPIO_OUT_LOW)
+
+/* Misc Signals */
+GPIO(EC_BATT_PRES_ODL,       PIN(C, 0), GPIO_INPUT)
+GPIO(BC12_DET_EN,            PIN(J, 5), GPIO_OUT_LOW) /* EN_USB_C0_BC12_DET */
+GPIO(EN_EC_ID_ODL,           PIN(H, 5), GPIO_ODR_LOW)
+GPIO(ENTERING_RW,            PIN(C, 5), GPIO_OUT_LOW) /* EC_ENTERING_RW */
+GPIO(EC_KB_BL_EN,            PIN(G, 3), GPIO_OUT_LOW) /* Keyboard backlight enable */
+GPIO(EN_5V_USM,              PIN(D, 7), GPIO_OUT_LOW)
+
+/* I2C pins - Alternate function below configures I2C module on these pins */
+GPIO(I2C_A_SCL,              PIN(B, 3), GPIO_INPUT) /* I2C_CHG_BATT_SCL */
+GPIO(I2C_A_SDA,              PIN(B, 4), GPIO_INPUT) /* I2C_CHG_BATT_SDA */
+GPIO(I2C_B_SCL,              PIN(C, 1), GPIO_INPUT | GPIO_SEL_1P8V) /* I2C_SENSOR_SCL */
+GPIO(I2C_B_SDA,              PIN(C, 2), GPIO_INPUT | GPIO_SEL_1P8V) /* I2C_SENSOR_SDA */
+GPIO(I2C_C_SCL,              PIN(F, 6), GPIO_INPUT) /* I2C_USB_C0_SCL */
+GPIO(I2C_C_SDA,              PIN(F, 7), GPIO_INPUT) /* I2C_USB_C0_SCL */
+GPIO(I2C_E_SCL,              PIN(E, 0), GPIO_INPUT) /* I2C_USB_C1_SCL */
+GPIO(I2C_E_SDA,              PIN(E, 7), GPIO_INPUT) /* I2C_USB_C1_SDA */
+
+/* SPI pins - Alternate function below configures SPI module on these pins */
+
+/* NC / TP */
+
+/* Keyboard pins */
+
+/* Subboards HDMI/TYPEC */
+GPIO(EC_X_GPIO1,             PIN(H, 4), GPIO_OUT_LOW)
+GPIO(EC_X_GPIO3,             PIN(J, 1), GPIO_INPUT)
+
+/* Alternate functions GPIO definitions */
+ALTERNATE(PIN_MASK(B, 0x18), 1, MODULE_I2C, 0) /* I2C A */
+ALTERNATE(PIN_MASK(C, 0x06), 1, MODULE_I2C, GPIO_SEL_1P8V) /* I2C B */
+ALTERNATE(PIN_MASK(F, 0xC0), 1, MODULE_I2C, 0) /* I2C C */
+ALTERNATE(PIN_MASK(E, 0x81), 1, MODULE_I2C, 0) /* I2C E */
+
+/* UART */
+ALTERNATE(PIN_MASK(B, 0x03), 1, MODULE_UART, 0) /* EC to Servo */
+
+/* ADC */
+ALTERNATE(PIN_MASK(I, 0xEF), 0, MODULE_ADC, 0) /* ADC 0,1,2,3,5,6,7 */
+
+/* SPI */
+ALTERNATE(PIN_MASK(M, 0x33), 0, MODULE_SPI, 0) /* SPI */
+
+/* Unimplemented Pins  */
+GPIO(SET_VMC_VOLT_AT_1V8,    PIN(D, 4), GPIO_INPUT | GPIO_PULL_DOWN | GPIO_SEL_1P8V)
+GPIO(PACKET_MODE_EN,         PIN(A, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(UNUSED_GPIOA0,          PIN(A, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIOA1,          PIN(A, 1), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIOA2,          PIN(A, 2), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(UNUSED_GPIOF0,          PIN(F, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIOJ2,          PIN(J, 2), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIOJ3,          PIN(J, 3), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIOJ7,          PIN(J, 7), GPIO_INPUT | GPIO_PULL_UP)
+
+/* b/160218054: behavior not defined */
+/* *_ODL pin has external pullup so don't pull it down. */
+GPIO(USB_A0_FAULT_ODL,       PIN(A, 7), GPIO_INPUT)
+GPIO(CHARGER_PROCHOT_ODL,    PIN(C, 3), GPIO_INPUT)
+GPIO(PG_MT6315_GPU_ODL,      PIN(H, 6), GPIO_INPUT)
+GPIO(EN_PP3000_SD_U,         PIN(G, 1), GPIO_INPUT | GPIO_PULL_DOWN | GPIO_SEL_1P8V)
+/* reserved for future use */
+GPIO(CCD_MODE_ODL,           PIN(C, 4), GPIO_INPUT)
+
+/* NC pins, enable internal pull-up/down to avoid floating state. */
+GPIO(NC_GPM2,                PIN(M, 2), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(NC_GPM3,                PIN(M, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(NC_GPM6,                PIN(M, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(SPI_CLK_GPG6,           PIN(G, 6), GPIO_INPUT | GPIO_PULL_UP)
+/*
+ * These 3 pins don't have internal pull-down capability,
+ * so we set them as output low.
+ */
+GPIO(SPI_MOSI_GPG4,          PIN(G, 4), GPIO_OUT_LOW)
+GPIO(SPI_MISO_GPG5,          PIN(G, 5), GPIO_OUT_LOW)
+GPIO(SPI_CS_GPG7,            PIN(G, 7), GPIO_OUT_LOW)
diff --git a/board/spherion/led.c b/board/spherion/led.c
new file mode 100644
index 0000000000..19ade3499e
--- /dev/null
+++ b/board/spherion/led.c
@@ -0,0 +1,88 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery LED control for Spherion
+ */
+
+#include "chipset.h"
+#include "driver/bc12/mt6360.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+
+__override const int led_charge_lvl_1 = 5;
+__override const int led_charge_lvl_2 = 95;
+
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_BATTERY_LED,
+};
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	mt6360_led_set_brightness(MT6360_LED_RGB1, 50);
+	mt6360_led_set_brightness(MT6360_LED_RGB3, 50);
+
+	switch (color) {
+	case EC_LED_COLOR_AMBER:
+		mt6360_led_enable(MT6360_LED_RGB1, 1);
+		mt6360_led_enable(MT6360_LED_RGB3, 0);
+		break;
+	case EC_LED_COLOR_BLUE:
+		mt6360_led_enable(MT6360_LED_RGB1, 0);
+		mt6360_led_enable(MT6360_LED_RGB3, 1);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		mt6360_led_enable(MT6360_LED_RGB1, 0);
+		mt6360_led_enable(MT6360_LED_RGB3, 0);
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_AMBER] =
+			MT6360_LED_BRIGHTNESS_MAX;
+		brightness_range[EC_LED_COLOR_BLUE] = MT6360_LED_BRIGHTNESS_MAX;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(EC_LED_COLOR_AMBER);
+		else if (brightness[EC_LED_COLOR_BLUE] != 0)
+			led_set_color_battery(EC_LED_COLOR_BLUE);
+		else
+			led_set_color_battery(LED_OFF);
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/board/spherion/vif_override.xml b/board/spherion/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/spherion/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/star b/board/star
new file mode 120000
index 0000000000..7f4a914148
--- /dev/null
+++ b/board/star
@@ -0,0 +1 @@
+hammer
\ No newline at end of file
diff --git a/board/stern/battery.c b/board/stern/battery.c
index 50d2bf397c..9edab52867 100644
--- a/board/stern/battery.c
+++ b/board/stern/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/stern/board.c b/board/stern/board.c
index 0a04842e35..39ab395006 100644
--- a/board/stern/board.c
+++ b/board/stern/board.c
@@ -1,10 +1,9 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "backlight.h"
 #include "button.h"
 #include "charge_manager.h"
@@ -31,6 +30,7 @@
 #include "it8801.h"
 #include "keyboard_scan.h"
 #include "lid_switch.h"
+#include "panic.h"
 #include "power.h"
 #include "power_button.h"
 #include "pwm.h"
@@ -40,41 +40,55 @@
 #include "system.h"
 #include "tablet_mode.h"
 #include "task.h"
-#include "tcpm.h"
+#include "tcpm/tcpm.h"
 #include "timer.h"
 #include "usb_charge.h"
 #include "usb_mux.h"
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
 	schedule_deferred_pd_interrupt(0 /* port */);
 }
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /******************************************************************************/
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] =  {"BOARD_ID",  3300, 4096, 0, STM32_AIN(10)},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)},
+	[ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(10) },
+	[ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /******************************************************************************/
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{"typec", 0, 400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"other", 1, 100, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
+	{ .name = "typec",
+	  .port = 0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "other",
+	  .port = 1,
+	  .kbps = 100,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
 const struct i2c_port_t i2c_bitbang_ports[] = {
-	{"battery", 2, 100, GPIO_I2C3_SCL, GPIO_I2C3_SDA, .drv = &bitbang_drv},
+	{ .name = "battery",
+	  .port = 2,
+	  .kbps = 100,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA,
+	  .drv = &bitbang_drv },
 };
 const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
 
@@ -82,13 +96,13 @@ const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
 
 /* power signal list.  Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
+	{ GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" },
+	{ GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" },
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
 /* Keyboard scan setting */
-struct keyboard_scan_config keyscan_config = {
+__override struct keyboard_scan_config keyscan_config = {
 	/*
 	 * TODO(b/133200075): Tune this once we have the final performance
 	 * out of the driver and the i2c bus.
@@ -107,8 +121,8 @@ struct keyboard_scan_config keyscan_config = {
 
 struct ioexpander_config_t ioex_config[CONFIG_IO_EXPANDER_PORT_COUNT] = {
 	[0] = {
-		.i2c_host_port = I2C_PORT_IO_EXPANDER_IT8801,
-		.i2c_slave_addr = IT8801_I2C_ADDR,
+		.i2c_host_port = I2C_PORT_KB_DISCRETE,
+		.i2c_addr_flags = IT8801_I2C_ADDR1,
 		.drv = &it8801_ioexpander_drv,
 	},
 };
@@ -133,15 +147,18 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = I2C_PORT_TCPC0,
-			.addr_flags = FUSB302_I2C_SLAVE_ADDR_FLAGS,
+			.addr_flags = FUSB302_I2C_ADDR_FLAGS,
 		},
 		.drv = &fusb302_tcpm_drv,
 	},
 };
 
-static void board_hpd_status(const struct usb_mux *me,
-			     int hpd_lvl, int hpd_irq)
+static void board_hpd_status(const struct usb_mux *me, mux_state_t mux_state,
+			     bool *ack_required)
 {
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
 	/*
 	 * svdm_dp_attention() did most of the work, we only need to notify
 	 * host here.
@@ -149,13 +166,16 @@ static void board_hpd_status(const struct usb_mux *me,
 	host_set_single_event(EC_HOST_EVENT_USB_MUX);
 }
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+				.hpd_update = &board_hpd_status,
+			},
 	},
 };
 
@@ -201,7 +221,7 @@ int board_set_active_charge_port(int charge_port)
 		if (board_vbus_source_enabled(charge_port))
 			return -1;
 		break;
-	case CHARGE_PORT_NONE:
+	default:
 		/*
 		 * To ensure the fuel gauge (max17055) is always powered
 		 * even when battery is disconnected, keep VBAT rail on but
@@ -209,22 +229,11 @@ int board_set_active_charge_port(int charge_port)
 		 */
 		charger_set_current(CHARGER_SOLO, 0);
 		break;
-	default:
-		panic("Invalid charge port\n");
-		break;
 	}
 
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-			       CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
-
 int board_discharge_on_ac(int enable)
 {
 	int ret, port;
@@ -254,7 +263,7 @@ int pd_snk_is_vbus_provided(int port)
 
 void bc12_interrupt(enum gpio_signal signal)
 {
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
 }
 
 #ifndef VARIANT_KUKUI_NO_SENSORS
@@ -274,13 +283,12 @@ static void board_spi_enable(void)
 	STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
 
 	/* Reinitialize spi peripheral. */
-	spi_enable(CONFIG_SPI_ACCEL_PORT, 1);
+	spi_enable(&spi_devices[0], 1);
 
 	/* Pin mux spi peripheral toward the sensor. */
-	gpio_config_module(MODULE_SPI_MASTER, 1);
+	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
 }
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP,
-	     board_spi_enable,
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_spi_enable,
 	     MOTION_SENSE_HOOK_PRIO - 1);
 
 static void board_spi_disable(void)
@@ -288,14 +296,13 @@ static void board_spi_disable(void)
 	/* Set pins to a state calming the sensor down. */
 	gpio_set_flags(GPIO_EC_SENSOR_SPI_CK, GPIO_OUT_LOW);
 	gpio_set_level(GPIO_EC_SENSOR_SPI_CK, 0);
-	gpio_config_module(MODULE_SPI_MASTER, 0);
+	gpio_config_module(MODULE_SPI_CONTROLLER, 0);
 
 	/* Disable spi peripheral and clocks. */
-	spi_enable(CONFIG_SPI_ACCEL_PORT, 0);
+	spi_enable(&spi_devices[0], 0);
 	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
 }
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN,
-	     board_spi_disable,
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_spi_disable,
 	     MOTION_SENSE_HOOK_PRIO + 1);
 #endif /* !VARIANT_KUKUI_NO_SENSORS */
 
@@ -334,17 +341,13 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Rotation matrixes */
-static const mat33_fp_t base_standard_ref = {
-	{FLOAT_TO_FP(1), 0, 0},
-	{0, FLOAT_TO_FP(-1), 0},
-	{0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, FLOAT_TO_FP(-1), 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
 
-static const mat33_fp_t lid_standard_ref = {
-	{FLOAT_TO_FP(1), 0, 0},
-	{0, FLOAT_TO_FP(1), 0},
-	{0, 0, FLOAT_TO_FP(1) }
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(1), 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
 
 /* sensor private data */
 /* Lid accel private data */
@@ -394,9 +397,10 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_base_mutex,
 		.drv_data = &g_bmi160_data,
 		.port = CONFIG_SPI_ACCEL_PORT,
-		.i2c_spi_addr_flags = SLAVE_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
+		.i2c_spi_addr_flags =
+				ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
 		.rot_standard_ref = &base_standard_ref,
-		.default_range = 2,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
+		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
 		.min_frequency = BMI_ACCEL_MIN_FREQ,
 		.max_frequency = BMI_ACCEL_MAX_FREQ,
 		.config = {
@@ -422,7 +426,8 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_base_mutex,
 		.drv_data = &g_bmi160_data,
 		.port = CONFIG_SPI_ACCEL_PORT,
-		.i2c_spi_addr_flags = SLAVE_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
+		.i2c_spi_addr_flags =
+				ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
 		.default_range = 1000, /* dps */
 		.rot_standard_ref = &base_standard_ref,
 		.min_frequency = BMI_GYRO_MIN_FREQ,
@@ -452,16 +457,3 @@ int board_get_charger_i2c(void)
 	/* TODO(b:138415463): confirm the bus allocation for future builds */
 	return board_get_version() == 1 ? 2 : 1;
 }
-
-/* Enable or disable input devices, based on chipset state and tablet mode */
-#ifndef TEST_BUILD
-void lid_angle_peripheral_enable(int enable)
-{
-	/* If the lid is in 360 position, ignore the lid angle,
-	 * which might be faulty. Disable keyboard.
-	 */
-	if (tablet_get_mode() || chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		enable = 0;
-	keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
-}
-#endif
diff --git a/board/stern/board.h b/board/stern/board.h
index 1ee3d931eb..0cc8194270 100644
--- a/board/stern/board.h
+++ b/board/stern/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,6 +11,7 @@
 #define VARIANT_KUKUI_JACUZZI
 #define VARIANT_KUKUI_BATTERY_SMART
 #define VARIANT_KUKUI_CHARGER_ISL9238
+#define VARIANT_KUKUI_EC_STM32F098
 
 #ifndef SECTION_IS_RW
 #define VARIANT_KUKUI_NO_SENSORS
@@ -18,6 +19,9 @@
 
 #include "baseboard.h"
 
+/* Disable deferred (async) flash protect*/
+#undef CONFIG_FLASH_PROTECT_DEFERRED
+
 #undef CONFIG_CHIPSET_POWER_SEQ_VERSION
 #define CONFIG_CHIPSET_POWER_SEQ_VERSION 1
 
@@ -27,6 +31,8 @@
 #define CONFIG_BATTERY_HW_PRESENT_CUSTOM
 
 #define CONFIG_CHARGER_PSYS
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 5
 
 #define CONFIG_CHARGER_RUNTIME_CONFIG
 
@@ -50,14 +56,12 @@
 #define CONFIG_USB_MUX_IT5205
 
 #define CONFIG_LED_ONOFF_STATES
-#define CONFIG_LED_POWER_LED
 #define CONFIG_LED_COMMON
 
 /* Motion Sensors */
 #ifndef VARIANT_KUKUI_NO_SENSORS
-#define CONFIG_ACCEL_LIS2DWL    /* Lid accel */
+#define CONFIG_ACCEL_LIS2DWL /* Lid accel */
 #define CONFIG_ACCELGYRO_BMI160 /* Base accel */
-#define CONFIG_ACCEL_INTERRUPTS
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 #define CONFIG_CMD_ACCEL_INFO
@@ -72,25 +76,24 @@
 #endif /* VARIANT_KUKUI_NO_SENSORS */
 
 /* I2C ports */
-#define I2C_PORT_BC12               0
-#define I2C_PORT_TCPC0              0
-#define I2C_PORT_USB_MUX            0
-#define I2C_PORT_BATTERY            2
-#define I2C_PORT_CHARGER            board_get_charger_i2c()
-#define I2C_PORT_SENSORS            1
-#define I2C_PORT_IO_EXPANDER_IT8801 1
-#define I2C_PORT_VIRTUAL_BATTERY    I2C_PORT_BATTERY
+#define I2C_PORT_BC12 0
+#define I2C_PORT_TCPC0 0
+#define I2C_PORT_USB_MUX 0
+#define I2C_PORT_BATTERY 2
+#define I2C_PORT_CHARGER board_get_charger_i2c()
+#define I2C_PORT_SENSORS 1
+#define I2C_PORT_KB_DISCRETE 1
+#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
+
+/* IT8801 I2C address */
+#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1
 
 /* Enable Accel over SPI */
-#define CONFIG_SPI_ACCEL_PORT    0  /* The first SPI master port (SPI2) */
+#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */
 
 #define CONFIG_KEYBOARD_PROTOCOL_MKBP
 #define CONFIG_MKBP_EVENT
 #define CONFIG_MKBP_USE_GPIO
-/* Define the MKBP events which are allowed to wakeup AP in S3. */
-#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \
-		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
 
 #ifndef __ASSEMBLER__
 
@@ -138,7 +141,6 @@ void emmc_cmd_interrupt(enum gpio_signal signal);
 void bc12_interrupt(enum gpio_signal signal);
 void board_reset_pd_mcu(void);
 int board_get_version(void);
-int board_is_sourcing_vbus(int port);
 
 /* returns the i2c port number of charger */
 int board_get_charger_i2c(void);
diff --git a/board/stern/build.mk b/board/stern/build.mk
index a6e1c010d7..f583684804 100644
--- a/board/stern/build.mk
+++ b/board/stern/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/stern/ec.tasklist b/board/stern/ec.tasklist
index 36be2e96a4..e77603a8e2 100644
--- a/board/stern/ec.tasklist
+++ b/board/stern/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/stern/gpio.inc b/board/stern/gpio.inc
index 51972ec367..85d080b2e9 100644
--- a/board/stern/gpio.inc
+++ b/board/stern/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -111,5 +111,5 @@ ALTERNATE(PIN_MASK(A, 0x8000), 0, MODULE_SPI,        0)
 /* EMMC SPI SLAVE: PB13/14/15 */
 ALTERNATE(PIN_MASK(B, 0xE000), 0, MODULE_SPI_FLASH,  0)
 /* SENSORS SPI MASTER: PB10, PB12, PC2, PC3 */
-ALTERNATE(PIN_MASK(B, 0x0400), 5, MODULE_SPI_MASTER, 0)
-ALTERNATE(PIN_MASK(C, 0x000C), 1, MODULE_SPI_MASTER, 0)
+ALTERNATE(PIN_MASK(B, 0x0400), 5, MODULE_SPI_CONTROLLER, 0)
+ALTERNATE(PIN_MASK(C, 0x000C), 1, MODULE_SPI_CONTROLLER, 0)
diff --git a/board/stern/led.c b/board/stern/led.c
index ff5f9f2373..7f4ecb6ace 100644
--- a/board/stern/led.c
+++ b/board/stern/led.c
@@ -1,50 +1,57 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Power and battery LED control for Damu
  */
 #include "common.h"
-#include "ioexpander.h"
 #include "driver/ioexpander/it8801.h"
 #include "ec_commands.h"
+#include "ioexpander.h"
 #include "led_common.h"
 #include "led_onoff_states.h"
 
 #define LED_ON_LVL 0
 #define LED_OFF_LVL 1
 
-const int led_charge_lvl_1 = 5;
-const int led_charge_lvl_2 = 95;
+__override const int led_charge_lvl_1 = 5;
+__override const int led_charge_lvl_2 = 95;
 
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
-const struct led_descriptor led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-	EC_LED_ID_BATTERY_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED,
+					     EC_LED_ID_BATTERY_LED };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-void led_set_color_battery(enum ec_led_colors color)
+__override void led_set_color_battery(enum ec_led_colors color)
 {
 	switch (color) {
 	case EC_LED_COLOR_WHITE:
@@ -62,7 +69,7 @@ void led_set_color_battery(enum ec_led_colors color)
 	}
 }
 
-void led_set_color_power(enum ec_led_colors color)
+__override void led_set_color_power(enum ec_led_colors color)
 {
 	switch (color) {
 	case EC_LED_COLOR_WHITE:
diff --git a/board/stern/vif_override.xml b/board/stern/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/stern/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/stm32f446e-eval/board.c b/board/stm32f446e-eval/board.c
index fc796464e2..d8f345f9aa 100644
--- a/board/stm32f446e-eval/board.c
+++ b/board/stm32f446e-eval/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,7 +7,6 @@
 #include "dma.h"
 #include "ec_version.h"
 #include "gpio.h"
-#include "gpio_list.h"
 #include "hooks.h"
 #include "i2c.h"
 #include "registers.h"
@@ -16,16 +15,19 @@
 #include "usb_dwc_console.h"
 #include "usb_hw.h"
 
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
 /******************************************************************************
  * Define the strings used in our USB descriptors.
  */
 const void *const usb_strings[] = {
-	[USB_STR_DESC]		= usb_string_desc,
-	[USB_STR_VENDOR]	= USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]	= USB_STRING_DESC("stm32f446-eval"),
-	[USB_STR_SERIALNO]	= USB_STRING_DESC("1234-a"),
-	[USB_STR_VERSION]	= USB_STRING_DESC(CROS_EC_VERSION32),
-	[USB_STR_CONSOLE_NAME]	= USB_STRING_DESC("EC Shell"),
+	[USB_STR_DESC] = usb_string_desc,
+	[USB_STR_VENDOR] = USB_STRING_DESC("Google LLC"),
+	[USB_STR_PRODUCT] = USB_STRING_DESC("stm32f446-eval"),
+	[USB_STR_SERIALNO] = USB_STRING_DESC("1234-a"),
+	[USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32),
+	[USB_STR_CONSOLE_NAME] = USB_STRING_DESC("EC Shell"),
 };
 
 BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
@@ -43,15 +45,21 @@ struct dwc_usb usb_ctl = {
 
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{"i2c1", I2C_PORT_0, 100,
-		GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"fmpi2c4", FMPI2C_PORT_3, 100,
-		GPIO_FMPI2C_SCL, GPIO_FMPI2C_SDA},
+	{ .name = "i2c1",
+	  .port = I2C_PORT_0,
+	  .kbps = 100,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "fmpi2c4",
+	  .port = FMPI2C_PORT_3,
+	  .kbps = 100,
+	  .scl = GPIO_FMPI2C_SCL,
+	  .sda = GPIO_FMPI2C_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
-#define GPIO_SET_HS(bank, number)	\
-	(STM32_GPIO_OSPEEDR(GPIO_##bank) |= (0x3 << ((number) * 2)))
+#define GPIO_SET_HS(bank, number) \
+	(STM32_GPIO_OSPEEDR(GPIO_##bank) |= (0x3 << ((number)*2)))
 
 void board_config_post_gpio_init(void)
 {
@@ -64,28 +72,27 @@ void board_config_post_gpio_init(void)
 	GPIO_SET_HS(A, 11);
 	GPIO_SET_HS(A, 12);
 
-	GPIO_SET_HS(C,  3);
-	GPIO_SET_HS(C,  2);
-	GPIO_SET_HS(C,  0);
-	GPIO_SET_HS(A,  5);
+	GPIO_SET_HS(C, 3);
+	GPIO_SET_HS(C, 2);
+	GPIO_SET_HS(C, 0);
+	GPIO_SET_HS(A, 5);
 
-	GPIO_SET_HS(B,  5);
+	GPIO_SET_HS(B, 5);
 	GPIO_SET_HS(B, 13);
 	GPIO_SET_HS(B, 12);
-	GPIO_SET_HS(B,  2);
+	GPIO_SET_HS(B, 2);
 	GPIO_SET_HS(B, 10);
-	GPIO_SET_HS(B,  1);
-	GPIO_SET_HS(B,  0);
-	GPIO_SET_HS(A,  3);
+	GPIO_SET_HS(B, 1);
+	GPIO_SET_HS(B, 0);
+	GPIO_SET_HS(A, 3);
 
 	/* Set I2C GPIO to HS */
-	GPIO_SET_HS(B,  6);
-	GPIO_SET_HS(B,  7);
-	GPIO_SET_HS(F,  1);
-	GPIO_SET_HS(F,  0);
-	GPIO_SET_HS(A,  8);
-	GPIO_SET_HS(B,  4);
-	GPIO_SET_HS(C,  6);
-	GPIO_SET_HS(C,  7);
+	GPIO_SET_HS(B, 6);
+	GPIO_SET_HS(B, 7);
+	GPIO_SET_HS(F, 1);
+	GPIO_SET_HS(F, 0);
+	GPIO_SET_HS(A, 8);
+	GPIO_SET_HS(B, 4);
+	GPIO_SET_HS(C, 6);
+	GPIO_SET_HS(C, 7);
 }
-
diff --git a/board/stm32f446e-eval/board.h b/board/stm32f446e-eval/board.h
index fa0b0177ef..667483d81f 100644
--- a/board/stm32f446e-eval/board.h
+++ b/board/stm32f446e-eval/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,7 +27,7 @@
 #define CONFIG_UART_RX_REQ_CH 4
 
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_CONTROLLER
 #define I2C_PORT_0 0
 #define FMPI2C_PORT_3 3
 
@@ -43,12 +43,12 @@
 
 /* USB interface indexes (use define rather than enum to expand them) */
 #define USB_IFACE_CONSOLE 0
-#define USB_IFACE_COUNT   1
+#define USB_IFACE_COUNT 1
 
 /* USB endpoint indexes (use define rather than enum to expand them) */
 #define USB_EP_CONTROL 0
 #define USB_EP_CONSOLE 1
-#define USB_EP_COUNT   2
+#define USB_EP_COUNT 2
 
 /* This is not actually an EC so disable some features. */
 #undef CONFIG_WATCHDOG_HELP
@@ -56,9 +56,8 @@
 #undef CONFIG_WATCHDOG
 
 /* Optional features */
-#define CONFIG_STM_HWTIMER32
 #define CONFIG_DMA_HELP
-#define CONFIG_FLASH
+#define CONFIG_FLASH_CROS
 
 /*
  * Allow dangerous commands all the time, since we don't have a write protect
diff --git a/board/stm32f446e-eval/build.mk b/board/stm32f446e-eval/build.mk
index 6b06f2bb8f..61e4b79d47 100644
--- a/board/stm32f446e-eval/build.mk
+++ b/board/stm32f446e-eval/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/stm32f446e-eval/ec.tasklist b/board/stm32f446e-eval/ec.tasklist
index 2a1ffbf652..6a12f02976 100644
--- a/board/stm32f446e-eval/ec.tasklist
+++ b/board/stm32f446e-eval/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/stm32f446e-eval/gpio.inc b/board/stm32f446e-eval/gpio.inc
index afc8d1e486..8eb7c6090d 100644
--- a/board/stm32f446e-eval/gpio.inc
+++ b/board/stm32f446e-eval/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/stm32l476g-eval/board.c b/board/stm32l476g-eval/board.c
index c7ebc2c6b8..1f22fa9373 100644
--- a/board/stm32l476g-eval/board.c
+++ b/board/stm32l476g-eval/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,8 +6,8 @@
 #include "common.h"
 #include "gpio.h"
 #include "hooks.h"
-#include "registers.h"
 #include "i2c.h"
+#include "registers.h"
 
 #ifdef CTS_MODULE
 /*
@@ -19,6 +19,7 @@ __attribute__((weak)) void cts_irq(enum gpio_signal signal)
 }
 #endif
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 void tick_event(void)
@@ -32,8 +33,12 @@ void tick_event(void)
 DECLARE_HOOK(HOOK_TICK, tick_event, HOOK_PRIO_DEFAULT);
 
 #ifdef CTS_MODULE_I2C
-const struct i2c_port_t i2c_ports[]  = {
-	{"test", STM32_I2C2_PORT, 100, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "test",
+	  .port = STM32_I2C2_PORT,
+	  .kbps = 100,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 #endif
diff --git a/board/stm32l476g-eval/board.h b/board/stm32l476g-eval/board.h
index 4b8033207b..40c7fb0eca 100644
--- a/board/stm32l476g-eval/board.h
+++ b/board/stm32l476g-eval/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,8 +10,8 @@
 
 #ifdef CTS_MODULE
 /* CTS tests are small. We can use smaller size to expedite flash time. */
-#undef  CONFIG_FLASH_SIZE
-#define CONFIG_FLASH_SIZE 0x00040000	/* 256k */
+#undef CONFIG_FLASH_SIZE_BYTES
+#define CONFIG_FLASH_SIZE_BYTES 0x00040000 /* 256k */
 #endif
 
 /* Optional features */
@@ -33,11 +33,10 @@
 #endif
 
 /* Optional features */
-#define CONFIG_STM_HWTIMER32
 
 #ifdef CTS_MODULE_I2C
 #define CONFIG_I2C
-#define CONFIG_I2C_SLAVE
+#define CONFIG_I2C_PERIPHERAL
 #define CONFIG_HOSTCMD_I2C_SLAVE_ADDR 0x3c
 #define I2C_PORT_EC STM32_I2C2_PORT
 #endif
@@ -50,22 +49,22 @@
 
 #ifndef __ASSEMBLER__
 
-#undef CONFIG_FLASH
+#undef CONFIG_FLASH_CROS
 #undef CONFIG_FLASH_PHYSICAL
 
 /* Timer selection */
-#define TIM_CLOCK32	5
+#define TIM_CLOCK32 5
 
 /* External clock speeds (8 MHz) */
 #define STM32_HSE_CLOCK 8000000
 
 /* PLL configuration. Freq = STM32_HSE_CLOCK * n/m/r */
 #undef STM32_PLLM
-#define STM32_PLLM	1
+#define STM32_PLLM 1
 #undef STM32_PLLN
-#define STM32_PLLN	10
+#define STM32_PLLN 10
 #undef STM32_PLLR
-#define STM32_PLLR	2
+#define STM32_PLLR 2
 
 #include "gpio_signal.h"
 
diff --git a/board/stm32l476g-eval/build.mk b/board/stm32l476g-eval/build.mk
index 23c7cd9d38..d453ea9979 100644
--- a/board/stm32l476g-eval/build.mk
+++ b/board/stm32l476g-eval/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/stm32l476g-eval/ec.tasklist b/board/stm32l476g-eval/ec.tasklist
index adfd7c7e92..f580a9d9e5 100644
--- a/board/stm32l476g-eval/ec.tasklist
+++ b/board/stm32l476g-eval/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/stm32l476g-eval/gpio.inc b/board/stm32l476g-eval/gpio.inc
index 9cf5bc0aa4..e84543f8f6 100644
--- a/board/stm32l476g-eval/gpio.inc
+++ b/board/stm32l476g-eval/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/stm32l476g-eval/openocd-flash.cfg b/board/stm32l476g-eval/openocd-flash.cfg
index a347f88b79..2f6a266d93 100644
--- a/board/stm32l476g-eval/openocd-flash.cfg
+++ b/board/stm32l476g-eval/openocd-flash.cfg
@@ -1,4 +1,4 @@
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/board/storo/battery.c b/board/storo/battery.c
new file mode 100644
index 0000000000..5a927ffc26
--- /dev/null
+++ b/board/storo/battery.c
@@ -0,0 +1,99 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "charge_state.h"
+#include "common.h"
+
+/*
+ * Battery info for all Storo battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	/* C21N2018_AS3GXXD3KA Battery Information */
+	[BATTERY_AS3GXXD3KA] = {
+		.fuel_gauge = {
+			.manuf_name = "AS3GXXD3KA",
+			.device_name = "C110160",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr = 0x99,
+				.reg_mask = 0x000C,
+				.disconnect_val = 0x000C,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0004
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 8800,
+			.voltage_normal		= 7890, /* mV */
+			.voltage_min		= 6000, /* mV */
+			.precharge_current	= 256,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 45,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 60,
+		},
+	},
+
+	/* C21N2018_AS3FXXD3KA Battery Information */
+	[BATTERY_AS3FXXD3KA] = {
+		.fuel_gauge = {
+			.manuf_name = "AS3FXXD3KA",
+			.device_name = "C110160",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr = 0x99,
+				.reg_mask = 0x000C,
+				.disconnect_val = 0x000C,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0004
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 8800,
+			.voltage_normal		= 7890, /* mV */
+			.voltage_min		= 6000, /* mV */
+			.precharge_current	= 256,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 45,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 60,
+		},
+	}
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_AS3GXXD3KA;
diff --git a/board/storo/board.c b/board/storo/board.c
new file mode 100644
index 0000000000..d8f1b09ae1
--- /dev/null
+++ b/board/storo/board.c
@@ -0,0 +1,931 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Storo configuration */
+
+#include "adc_chip.h"
+#include "button.h"
+#include "cbi_fw_config.h"
+#include "cbi_ssfc.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "cros_board_info.h"
+#include "driver/accel_bma2x2.h"
+#include "driver/accel_kionix.h"
+#include "driver/accel_lis2dw12.h"
+#include "driver/accelgyro_bmi260.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "driver/accelgyro_icm42607.h"
+#include "driver/accelgyro_icm_common.h"
+#include "driver/bc12/pi3usb9201.h"
+#include "driver/charger/isl923x.h"
+#include "driver/retimer/tusb544.h"
+#include "driver/tcpm/raa489000.h"
+#include "driver/temp_sensor/thermistor.h"
+#include "driver/usb_mux/it5205.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "intc.h"
+#include "keyboard_raw.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "switch.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "tcpm/tcpci.h"
+#include "temp_sensor.h"
+#include "uart.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+#define INT_RECHECK_US 5000
+
+/* C0 interrupt line shared by BC 1.2 and charger */
+static void check_c0_line(void);
+DECLARE_DEFERRED(check_c0_line);
+
+static void notify_c0_chips(void)
+{
+	schedule_deferred_pd_interrupt(0);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+
+static void check_c0_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		notify_c0_chips();
+		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+	}
+}
+
+static void usb_c0_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c0_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c0_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+}
+
+/* C1 interrupt line shared by BC 1.2, TCPC, and charger */
+static void check_c1_line(void);
+DECLARE_DEFERRED(check_c1_line);
+
+static void notify_c1_chips(void)
+{
+	schedule_deferred_pd_interrupt(1);
+	usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+}
+
+static void check_c1_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips.
+	 */
+	if (!gpio_get_level(GPIO_USB_C1_INT_ODL)) {
+		notify_c1_chips();
+		hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
+	}
+}
+
+static void usb_c1_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c1_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c1_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
+}
+
+static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
+{
+	cprints(CC_USBPD, "C0: CC OVP, SBU OVP, or thermal event");
+	pd_handle_cc_overvoltage(0);
+}
+
+static void pen_detect_interrupt(enum gpio_signal s)
+{
+	int pen_detect = !gpio_get_level(GPIO_PEN_DET_ODL);
+
+	gpio_set_level(GPIO_EN_PP3300_PEN, pen_detect);
+}
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	[ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH0 },
+	[ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH2 },
+	[ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH3 },
+	[ADC_TEMP_SENSOR_3] = { .name = "TEMP_SENSOR3",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH15 },
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* BC 1.2 chips */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	{
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+		.flags = PI3USB9201_ALWAYS_POWERED,
+	},
+	{
+		.i2c_port = I2C_PORT_SUB_USB_C1,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+		.flags = PI3USB9201_ALWAYS_POWERED,
+	},
+};
+
+int pd_snk_is_vbus_provided(int port)
+{
+	return pd_check_vbus_level(port, VBUS_PRESENT);
+}
+
+/* Charger chips */
+const struct charger_config_t chg_chips[] = {
+	[CHARGER_PRIMARY] = {
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+	[CHARGER_SECONDARY] = {
+		.i2c_port = I2C_PORT_SUB_USB_C1,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+};
+
+/* TCPCs */
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0,
+			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
+		},
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+		.drv = &raa489000_tcpm_drv,
+	},
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_SUB_USB_C1,
+			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
+		},
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+		.drv = &raa489000_tcpm_drv,
+	},
+};
+
+/* USB Retimer */
+enum tusb544_conf { USB_DP = 0, USB_DP_INV, USB, USB_INV, DP, DP_INV };
+
+/*
+ * Registers we care about of are all the same between NCS8510 and TUSB544,
+ * so we leverage the driver of TUSB544 to control both of them.
+ *
+ * For EQ settings, these two chips are also almost the same, so we have one
+ * set of EQ settings here for both of them as well. When you need to modify
+ * the EQ settings, please make sure that both configurations are correct;
+ * otherwise you need to separate EQ settings then.
+ */
+static int board_tusb544_set(const struct usb_mux *me, mux_state_t mux_state)
+{
+	int rv = EC_SUCCESS;
+	int reg;
+	enum tusb544_conf usb_mode = 0;
+
+	if (mux_state & USB_PD_MUX_USB_ENABLED) {
+		if (mux_state & USB_PD_MUX_DP_ENABLED) {
+			/* USB with DP */
+			usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ?
+					   USB_DP_INV :
+					   USB_DP;
+		} else {
+			/* USB without DP */
+			usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ?
+					   USB_INV :
+					   USB;
+		}
+	} else if (mux_state & USB_PD_MUX_DP_ENABLED) {
+		/* DP without USB */
+		usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ? DP_INV :
+									DP;
+	} else {
+		return EC_SUCCESS;
+	}
+
+	rv = i2c_read8(me->i2c_port, me->i2c_addr_flags, TUSB544_REG_GENERAL6,
+		       &reg);
+	if (rv)
+		return rv;
+
+	reg |= TUSB544_VOD_DCGAIN_OVERRIDE;
+	reg &= ~TUSB544_VOD_DCGAIN_SEL;
+	reg |= (TUSB544_VOD_DCGAIN_SETTING_5 << 2);
+
+	rv = i2c_write8(me->i2c_port, me->i2c_addr_flags, TUSB544_REG_GENERAL6,
+			reg);
+	if (rv)
+		return rv;
+
+	/* Write the retimer config byte */
+	if (usb_mode == USB_INV) {
+		rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				 TUSB544_REG_GENERAL4, 0x15);
+		rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				 TUSB544_REG_USB3_1_1, 0xff);
+		rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				 TUSB544_REG_USB3_1_2, 0xff);
+	} else if (usb_mode == USB) {
+		rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				 TUSB544_REG_GENERAL4, 0x11);
+		rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				 TUSB544_REG_USB3_1_1, 0xff);
+		rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				 TUSB544_REG_USB3_1_2, 0xff);
+	} else if (usb_mode == USB_DP_INV) {
+		rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				 TUSB544_REG_GENERAL4, 0x1F);
+		rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				 TUSB544_REG_USB3_1_1, 0xff);
+		rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				 TUSB544_REG_USB3_1_2, 0xff);
+	} else if (usb_mode == USB_DP) {
+		rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				 TUSB544_REG_GENERAL4, 0x1B);
+		rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				 TUSB544_REG_USB3_1_1, 0xff);
+		rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				 TUSB544_REG_USB3_1_2, 0xff);
+	} else if (usb_mode == DP_INV) {
+		rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				 TUSB544_REG_GENERAL4, 0x1E);
+	} else if (usb_mode == DP) {
+		rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
+				 TUSB544_REG_GENERAL4, 0x1A);
+	}
+
+	rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
+			 TUSB544_REG_DISPLAYPORT_1, 0x66);
+	rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
+			 TUSB544_REG_DISPLAYPORT_2, 0x66);
+	if (rv)
+		return EC_ERROR_UNKNOWN;
+	else
+		return EC_SUCCESS;
+}
+
+/* USB Retimer */
+const struct usb_mux_chain usbc1_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = 1,
+			.i2c_port = I2C_PORT_SUB_USB_C1,
+			.i2c_addr_flags = TUSB544_I2C_ADDR_FLAGS0,
+			.driver = &tusb544_drv,
+			.board_set = &board_tusb544_set,
+		},
+};
+
+/* USB Muxes */
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+			},
+	},
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_SUB_USB_C1,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+			},
+		.next = &usbc1_retimer,
+	},
+};
+
+void board_hibernate(void)
+{
+	/*
+	 * Put all charger ICs present into low power mode before entering
+	 * z-state.
+	 */
+	raa489000_hibernate(CHARGER_PRIMARY, true);
+	if (board_get_charger_chip_count() > 1)
+		raa489000_hibernate(CHARGER_SECONDARY, true);
+}
+
+__override void board_ocpc_init(struct ocpc_data *ocpc)
+{
+	/* There's no provision to measure Isys */
+	ocpc->chg_flags[CHARGER_SECONDARY] |= OCPC_NO_ISYS_MEAS_CAP;
+}
+
+__override void board_pulse_entering_rw(void)
+{
+	/*
+	 * On the ITE variants, the EC_ENTERING_RW signal was connected to a pin
+	 * which is active high by default.  This causes Cr50 to think that the
+	 * EC has jumped to its RW image even though this may not be the case.
+	 * The pin is changed to GPIO_EC_ENTERING_RW2.
+	 */
+	gpio_set_level(GPIO_EC_ENTERING_RW, 1);
+	gpio_set_level(GPIO_EC_ENTERING_RW2, 1);
+	usleep(MSEC);
+	gpio_set_level(GPIO_EC_ENTERING_RW, 0);
+	gpio_set_level(GPIO_EC_ENTERING_RW2, 0);
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * Nothing to do.  TCPC C0 is internal, TCPC C1 reset pin is not
+	 * connected to the EC.
+	 */
+}
+
+__override void board_power_5v_enable(int enable)
+{
+	/*
+	 * Motherboard has a GPIO to turn on the 5V regulator, but the sub-board
+	 * sets it through the charger GPIO.
+	 */
+	gpio_set_level(GPIO_EN_PP5000, !!enable);
+	gpio_set_level(GPIO_EN_USB_A0_VBUS, !!enable);
+	if (isl923x_set_comparator_inversion(1, !!enable))
+		CPRINTS("Failed to %sable sub rails!", enable ? "en" : "dis");
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+	int regval;
+
+	/*
+	 * The interrupt line is shared between the TCPC and BC1.2 detector IC.
+	 * Therefore, go out and actually read the alert registers to report the
+	 * alert status.
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
+			if (regval)
+				status = PD_STATUS_TCPC_ALERT_0;
+		}
+	}
+
+	/* Check whether TCPC 1 pulled the shared interrupt line */
+	if (!gpio_get_level(GPIO_USB_C1_INT_ODL)) {
+		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
+			if (regval)
+				status = PD_STATUS_TCPC_ALERT_1;
+		}
+	}
+
+	return status;
+}
+
+int board_is_sourcing_vbus(int port)
+{
+	int regval;
+
+	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
+	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count());
+	int i;
+	int old_port;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	old_port = charge_manager_get_active_charge_port();
+
+	CPRINTS("New chg p%d", port);
+
+	/* Disable all ports. */
+	if (port == CHARGE_PORT_NONE) {
+		for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+			tcpc_write(i, TCPC_REG_COMMAND,
+				   TCPC_REG_COMMAND_SNK_CTRL_LOW);
+			raa489000_enable_asgate(i, false);
+		}
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if port is sourcing VBUS. */
+	if (board_is_sourcing_vbus(port)) {
+		CPRINTS("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * Turn off the other ports sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+		if (i == port)
+			continue;
+
+		if (tcpc_write(i, TCPC_REG_COMMAND,
+			       TCPC_REG_COMMAND_SNK_CTRL_LOW))
+			CPRINTS("p%d: sink path disable failed.", i);
+		raa489000_enable_asgate(i, false);
+	}
+
+	/*
+	 * Stop the charger IC from switching while changing ports.  Otherwise,
+	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
+	 */
+	if ((old_port != CHARGE_PORT_NONE) && (old_port != port))
+		charger_discharge_on_ac(1);
+
+	/* Enable requested charge port. */
+	if (raa489000_enable_asgate(port, true) ||
+	    tcpc_write(port, TCPC_REG_COMMAND,
+		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
+		CPRINTS("p%d: sink path enable failed.", port);
+		charger_discharge_on_ac(0);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	/* Allow the charger IC to begin/continue switching. */
+	charger_discharge_on_ac(0);
+
+	return EC_SUCCESS;
+}
+
+__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+				       int *ki_div, int *kd, int *kd_div)
+{
+	*kp = 3;
+	*kp_div = 14;
+
+	*ki = 3;
+	*ki_div = 500;
+
+	*kd = 4;
+	*kd_div = 40;
+}
+
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	if (port < 0 || port > board_get_usb_pd_port_count())
+		return;
+
+	raa489000_set_output_current(port, rp);
+}
+
+/* Sensors */
+static struct mutex g_lid_mutex;
+static struct mutex g_base_mutex;
+
+/* Matrices to rotate accelerometers into the standard reference. */
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					     { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
+
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					      { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
+
+static struct accelgyro_saved_data_t g_bma253_data;
+static struct bmi_drv_data_t g_bmi160_data;
+
+struct motion_sensor_t motion_sensors[] = {
+	[LID_ACCEL] = {
+		.name = "Lid Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMA255,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &bma2x2_accel_drv,
+		.mutex = &g_lid_mutex,
+		.drv_data = &g_bma253_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR2_FLAGS,
+		.rot_standard_ref = &lid_standard_ref,
+		.default_range = 2,
+		.min_frequency = BMA255_ACCEL_MIN_FREQ,
+		.max_frequency = BMA255_ACCEL_MAX_FREQ,
+		.config = {
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+		},
+	},
+	[BASE_ACCEL] = {
+		.name = "Base Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMI160,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &bmi160_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = &g_bmi160_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+		.rot_standard_ref = &base_standard_ref,
+		.default_range = 4,
+		.min_frequency = BMI_ACCEL_MIN_FREQ,
+		.max_frequency = BMI_ACCEL_MAX_FREQ,
+		.config = {
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 13000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+		},
+	},
+	[BASE_GYRO] = {
+		.name = "Base Gyro",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMI160,
+		.type = MOTIONSENSE_TYPE_GYRO,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &bmi160_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = &g_bmi160_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+		.default_range = 1000, /* dps */
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = BMI_GYRO_MIN_FREQ,
+		.max_frequency = BMI_GYRO_MAX_FREQ,
+	},
+};
+
+unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+static const mat33_fp_t lid_lis2dwl_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					    { FLOAT_TO_FP(1), 0, 0 },
+					    { 0, 0, FLOAT_TO_FP(-1) } };
+
+/* Lid accel private data */
+static struct stprivate_data g_lis2dwl_data;
+struct motion_sensor_t lis2dwl_lid_accel = {
+
+		.name = "Lid Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LIS2DWL,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &lis2dw12_drv,
+		.mutex = &g_lid_mutex,
+		.drv_data = &g_lis2dwl_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LIS2DWL_ADDR1_FLAGS,
+		.rot_standard_ref = &lid_lis2dwl_ref,
+		.default_range = 2, /* g */
+		.min_frequency = LIS2DW12_ODR_MIN_VAL,
+		.max_frequency = LIS2DW12_ODR_MAX_VAL,
+		.config = {
+			/* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 12500 | ROUND_UP_FLAG,
+			},
+			/* Sensor on for lid angle detection */
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+		},
+};
+
+static const mat33_fp_t lid_KX022_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					  { FLOAT_TO_FP(1), 0, 0 },
+					  { 0, 0, FLOAT_TO_FP(-1) } };
+
+static struct kionix_accel_data g_kx022_data;
+struct motion_sensor_t kx022_lid_accel = {
+	.name = "Lid Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_KX022,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_LID,
+	.drv = &kionix_accel_drv,
+	.mutex = &g_lid_mutex,
+	.drv_data = &g_kx022_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
+	.rot_standard_ref = &lid_KX022_ref,
+	.min_frequency = KX022_ACCEL_MIN_FREQ,
+	.max_frequency = KX022_ACCEL_MAX_FREQ,
+	.default_range = 2, /* g, to support tablet mode */
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	},
+};
+
+static struct icm_drv_data_t g_icm42607_data;
+const mat33_fp_t based_ref_icm42607 = { { FLOAT_TO_FP(1), 0, 0 },
+					{ 0, FLOAT_TO_FP(1), 0 },
+					{ 0, 0, FLOAT_TO_FP(1) } };
+struct motion_sensor_t icm42607_base_accel = {
+	 .name = "Base Accel",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_ICM42607,
+	 .type = MOTIONSENSE_TYPE_ACCEL,
+	 .location = MOTIONSENSE_LOC_BASE,
+	 .drv = &icm42607_drv,
+	 .mutex = &g_base_mutex,
+	 .drv_data = &g_icm42607_data,
+	 .port = I2C_PORT_ACCEL,
+	 .i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
+	 .default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
+	 .rot_standard_ref = &based_ref_icm42607,
+	 .min_frequency = ICM42607_ACCEL_MIN_FREQ,
+	 .max_frequency = ICM42607_ACCEL_MAX_FREQ,
+	 .config = {
+		 /* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	 },
+};
+
+struct motion_sensor_t icm42607_base_gyro = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM42607,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm42607_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm42607_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &based_ref_icm42607,
+	.min_frequency = ICM42607_GYRO_MIN_FREQ,
+	.max_frequency = ICM42607_GYRO_MAX_FREQ,
+};
+
+static struct bmi_drv_data_t g_bmi220_data;
+const mat33_fp_t based_ref_bmi220 = { { 0, FLOAT_TO_FP(1), 0 },
+				      { FLOAT_TO_FP(-1), 0, 0 },
+				      { 0, 0, FLOAT_TO_FP(1) } };
+struct motion_sensor_t bmi220_base_accel = {
+	 .name = "Base Accel",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_BMI220,
+	 .type = MOTIONSENSE_TYPE_ACCEL,
+	 .location = MOTIONSENSE_LOC_BASE,
+	 .drv = &bmi260_drv,
+	 .mutex = &g_base_mutex,
+	 .drv_data = &g_bmi220_data,
+	 .port = I2C_PORT_ACCEL,
+	 .i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
+	 .default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
+	 .rot_standard_ref = &based_ref_bmi220,
+	 .min_frequency = BMI_ACCEL_MIN_FREQ,
+	 .max_frequency = BMI_ACCEL_MAX_FREQ,
+	 .config = {
+		[SENSOR_CONFIG_EC_S0] = {
+				.odr = 13000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+		},
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+	 },
+};
+
+struct motion_sensor_t bmi220_base_gyro = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_BMI220,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &bmi260_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_bmi220_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &based_ref_bmi220,
+	.min_frequency = BMI_GYRO_MIN_FREQ,
+	.max_frequency = BMI_GYRO_MAX_FREQ,
+};
+
+void board_init(void)
+{
+	int on;
+	uint32_t board_id;
+
+	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_INT_ODL);
+
+	/*
+	 * If interrupt lines are already low, schedule them to be processed
+	 * after inits are completed.
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL))
+		hook_call_deferred(&check_c0_line_data, 0);
+	if (!gpio_get_level(GPIO_USB_C1_INT_ODL))
+		hook_call_deferred(&check_c1_line_data, 0);
+
+	gpio_enable_interrupt(GPIO_USB_C0_CCSBU_OVP_ODL);
+	/* Enable Base Accel interrupt */
+	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
+	/* Enable gpio interrupt for pen detect */
+	gpio_enable_interrupt(GPIO_PEN_DET_ODL);
+
+	/* Turn on 5V if the system is on, otherwise turn it off */
+	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
+			      CHIPSET_STATE_SOFT_OFF);
+	board_power_5v_enable(on);
+
+	if (!gpio_get_level(GPIO_PEN_DET_ODL))
+		gpio_set_level(GPIO_EN_PP3300_PEN, 1);
+
+	cbi_get_board_version(&board_id);
+
+	if (board_id > 2) {
+		if (get_cbi_fw_config_tablet_mode()) {
+			if (get_cbi_ssfc_base_sensor() ==
+			    SSFC_SENSOR_ICM42607) {
+				motion_sensors[BASE_ACCEL] =
+					icm42607_base_accel;
+				motion_sensors[BASE_GYRO] = icm42607_base_gyro;
+				CPRINTF("BASE GYRO is ICM42607");
+			} else if (get_cbi_ssfc_base_sensor() ==
+				   SSFC_SENSOR_BMI220) {
+				motion_sensors[BASE_ACCEL] = bmi220_base_accel;
+				motion_sensors[BASE_GYRO] = bmi220_base_gyro;
+				CPRINTF("BASE GYRO is BMI220");
+			} else {
+				CPRINTF("BASE GYRO is BMI160");
+			}
+
+			if (get_cbi_ssfc_lid_sensor() == SSFC_SENSOR_LIS2DWL) {
+				motion_sensors[LID_ACCEL] = lis2dwl_lid_accel;
+				CPRINTF("LID_ACCEL is LIS2DWL");
+			} else if (get_cbi_ssfc_lid_sensor() ==
+				   SSFC_SENSOR_KX022) {
+				motion_sensors[LID_ACCEL] = kx022_lid_accel;
+				CPRINTF("LID_ACCEL is KX022");
+			} else {
+				CPRINTF("LID_ACCEL is BMA253");
+			}
+		} else {
+			motion_sensor_count = 0;
+			gmr_tablet_switch_disable();
+			/*
+			 * Base accel is not stuffed, don't allow
+			 * line to float.
+			 */
+			gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L,
+				       GPIO_INPUT | GPIO_PULL_DOWN);
+		}
+	} else {
+		if (get_cbi_ssfc_base_sensor() == SSFC_SENSOR_ICM42607) {
+			motion_sensors[BASE_ACCEL] = icm42607_base_accel;
+			motion_sensors[BASE_GYRO] = icm42607_base_gyro;
+			CPRINTF("BASE GYRO is ICM42607");
+		} else if (get_cbi_ssfc_base_sensor() == SSFC_SENSOR_BMI220) {
+			motion_sensors[BASE_ACCEL] = bmi220_base_accel;
+			motion_sensors[BASE_GYRO] = bmi220_base_gyro;
+			CPRINTF("BASE GYRO is BMI220");
+		} else {
+			CPRINTF("BASE GYRO is BMI160");
+		}
+
+		if (get_cbi_ssfc_lid_sensor() == SSFC_SENSOR_LIS2DWL) {
+			motion_sensors[LID_ACCEL] = lis2dwl_lid_accel;
+			CPRINTF("LID_ACCEL is LIS2DWL");
+		} else if (get_cbi_ssfc_lid_sensor() == SSFC_SENSOR_KX022) {
+			motion_sensors[LID_ACCEL] = kx022_lid_accel;
+			CPRINTF("LID_ACCEL is KX022");
+		} else {
+			CPRINTF("LID_ACCEL is BMA253");
+		}
+	}
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	switch (get_cbi_ssfc_base_sensor()) {
+	case SSFC_SENSOR_ICM42607:
+		icm42607_interrupt(signal);
+		break;
+	case SSFC_SENSOR_BMI220:
+		bmi260_interrupt(signal);
+		break;
+	case SSFC_SENSOR_BMI160:
+	default:
+		bmi160_interrupt(signal);
+		break;
+	}
+}
+
+/* Thermistors */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "Cpu",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/* This callback disables keyboard when convertibles are fully open */
+__override void lid_angle_peripheral_enable(int enable)
+{
+	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
+
+	/*
+	 * If the lid is in tablet position via other sensors,
+	 * ignore the lid angle, which might be faulty then
+	 * disable keyboard.
+	 */
+	if (tablet_get_mode())
+		enable = 0;
+
+	if (enable) {
+		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
+	} else {
+		/*
+		 * Ensure that the chipset is off before disabling the keyboard.
+		 * When the chipset is on, the EC keeps the keyboard enabled and
+		 * the AP decides whether to ignore input devices or not.
+		 */
+		if (!chipset_in_s0)
+			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
+	}
+}
diff --git a/board/storo/board.h b/board/storo/board.h
new file mode 100644
index 0000000000..930b92f95a
--- /dev/null
+++ b/board/storo/board.h
@@ -0,0 +1,153 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Storo board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* Select Baseboard features */
+#define VARIANT_DEDEDE_EC_IT8320
+#include "baseboard.h"
+
+/* EC console commands */
+#define CONFIG_CMD_TCPC_DUMP
+#define CONFIG_CMD_CHARGER_DUMP
+
+/* Battery */
+#define CONFIG_BATTERY_FUEL_GAUGE
+#define CONFIG_SMBUS_PEC
+
+/* BC 1.2 */
+#define CONFIG_BC12_DETECT_PI3USB9201
+
+/* Charger */
+#define CONFIG_CHARGER_RAA489000
+#define PD_MAX_VOLTAGE_MV 20000
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_OCPC_DEF_RBATT_MOHMS               \
+	22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \
+	    */
+/*
+ * b/147463641: The charger IC seems to overdraw ~4%, therefore we
+ * reduce our target accordingly.
+ */
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 4
+#define CONFIG_OCPC
+#undef CONFIG_CHARGER_SINGLE_CHIP
+#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
+#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
+
+#define GPIO_USB_C1_INT_ODL GPIO_SUB_USB_C1_INT_ODL
+
+/* LED */
+#define CONFIG_LED_ONOFF_STATES
+#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
+
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
+
+/* Sensors */
+#define CONFIG_CMD_ACCELS
+#define CONFIG_CMD_ACCEL_INFO
+#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
+
+#define CONFIG_ACCEL_BMA255 /* Lid accel */
+#define CONFIG_ACCEL_LIS2DWL
+#define CONFIG_ACCEL_KX022
+#define CONFIG_ACCELGYRO_BMI160 /* Base accel */
+#define CONFIG_ACCELGYRO_ICM42607
+#define CONFIG_ACCELGYRO_BMI220
+#define CONFIG_I2C_XFER_LARGE_TRANSFER
+
+/* Lid operates in forced mode, base in FIFO */
+#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
+#define CONFIG_ACCEL_FIFO
+#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */
+#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
+
+#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+#define CONFIG_ACCELGYRO_BMI260_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+#define CONFIG_ACCELGYRO_ICM42607_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_UPDATE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+
+#define CONFIG_TABLET_MODE
+#define CONFIG_TABLET_MODE_SWITCH
+#define CONFIG_GMR_TABLET_MODE
+
+/* TCPC */
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#define CONFIG_USB_PD_TCPM_RAA489000
+
+/* USB defines specific to external TCPCs */
+#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+#define CONFIG_USB_PD_VBUS_DETECT_TCPC
+#define CONFIG_USB_PD_DISCHARGE_TCPC
+#define CONFIG_USB_PD_TCPC_LOW_POWER
+#define CONFIG_USB_PD_5V_EN_CUSTOM
+
+/* Thermistors */
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_THERMISTOR
+#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
+
+/* USB Mux and Retimer */
+#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */
+
+#define CONFIG_USBC_RETIMER_TUSB544 /* C1 Redriver: TUSB544 */
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum chg_id {
+	CHARGER_PRIMARY,
+	CHARGER_SECONDARY,
+	CHARGER_NUM,
+};
+
+/* Motion sensors */
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
+
+/* ADC channels */
+enum adc_channel {
+	ADC_VSNS_PP3300_A, /* ADC0 */
+	ADC_TEMP_SENSOR_1, /* ADC2 */
+	ADC_TEMP_SENSOR_2, /* ADC3 */
+	ADC_TEMP_SENSOR_3, /* ADC15*/
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1,
+	TEMP_SENSOR_2,
+	TEMP_SENSOR_3,
+	TEMP_SENSOR_COUNT
+};
+
+/* List of possible batteries */
+enum battery_type {
+	BATTERY_AS3GXXD3KA,
+	BATTERY_AS3FXXD3KA,
+	BATTERY_TYPE_COUNT,
+};
+
+void motion_interrupt(enum gpio_signal signal);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/storo/build.mk b/board/storo/build.mk
new file mode 100644
index 0000000000..01b890bf29
--- /dev/null
+++ b/board/storo/build.mk
@@ -0,0 +1,15 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=it83xx
+CHIP_FAMILY:=it8320
+CHIP_VARIANT:=it8320dx
+BASEBOARD:=dedede
+
+board-y=board.o cbi_ssfc.o led.o usb_pd_policy.o
+board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/storo/cbi_ssfc.c b/board/storo/cbi_ssfc.c
new file mode 100644
index 0000000000..81f3ee0dad
--- /dev/null
+++ b/board/storo/cbi_ssfc.c
@@ -0,0 +1,36 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi_ssfc.h"
+#include "common.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "hooks.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+/* Cache SSFC on init since we don't expect it to change in runtime */
+static union dedede_cbi_ssfc cached_ssfc;
+BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
+
+static void cbi_ssfc_init(void)
+{
+	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
+		/* Default to 0 when CBI isn't populated */
+		cached_ssfc.raw_value = 0;
+
+	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
+}
+DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
+
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
+{
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
+}
+
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
+{
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
+}
diff --git a/board/storo/cbi_ssfc.h b/board/storo/cbi_ssfc.h
new file mode 100644
index 0000000000..bc6bc92286
--- /dev/null
+++ b/board/storo/cbi_ssfc.h
@@ -0,0 +1,60 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _DEDEDE_CBI_SSFC__H_
+#define _DEDEDE_CBI_SSFC__H_
+
+#include "stdint.h"
+
+/****************************************************************************
+ * Dedede CBI Second Source Factory Cache
+ */
+
+/*
+ * Base Sensor (Bits 0-2)
+ */
+enum ec_ssfc_base_sensor {
+	SSFC_SENSOR_BASE_DEFAULT = 0,
+	SSFC_SENSOR_BMI160 = 1,
+	SSFC_SENSOR_ICM426XX = 2,
+	SSFC_SENSOR_LSM6DSM = 3,
+	SSFC_SENSOR_ICM42607 = 4,
+	SSFC_SENSOR_BMI220 = 5
+};
+
+/*
+ * Lid Sensor (Bits 3-5)
+ */
+enum ec_ssfc_lid_sensor {
+	SSFC_SENSOR_LID_DEFAULT = 0,
+	SSFC_SENSOR_BMA255 = 1,
+	SSFC_SENSOR_KX022 = 2,
+	SSFC_SENSOR_LIS2DWL = 3
+};
+
+union dedede_cbi_ssfc {
+	struct {
+		uint32_t base_sensor : 3;
+		uint32_t lid_sensor : 3;
+		uint32_t reserved_2 : 26;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Get the Base sensor type from SSFC_CONFIG.
+ *
+ * @return the Base sensor board type.
+ */
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
+
+/**
+ * Get the Lid sensor type from SSFC_CONFIG.
+ *
+ * @return the Lid sensor board type.
+ */
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
+
+#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/storo/ec.tasklist b/board/storo/ec.tasklist
new file mode 100644
index 0000000000..8abd36b4be
--- /dev/null
+++ b/board/storo/ec.tasklist
@@ -0,0 +1,25 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, TRENTA_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, ULTRA_TASK_STACK_SIZE) \
+        TASK_ALWAYS(PD_C0, pd_task, NULL, TRENTA_TASK_STACK_SIZE) \
+        TASK_ALWAYS(PD_C1, pd_task, NULL, TRENTA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE) \
+        TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/storo/gpio.inc b/board/storo/gpio.inc
new file mode 100644
index 0000000000..cb07474f52
--- /dev/null
+++ b/board/storo/gpio.inc
@@ -0,0 +1,141 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+/* Power State interrupts */
+GPIO_INT(SLP_S4_L,		PIN(I, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,		PIN(H, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(SLP_S0_L,		PIN(E, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,		PIN(G, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID0,	PIN(D, 0), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(RSMRST_PWRGD_L,	PIN(E, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(CPU_C10_GATE_L,	PIN(G, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_DRAM_OD,		PIN(D, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(PG_PP1050_ST_OD,	PIN(L, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID1,	PIN(K, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_VCCIO_EXT_OD,	PIN(D, 7), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(ESPI_RESET_L, 	 	PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt)
+
+GPIO_INT(H1_EC_PWR_BTN_ODL,	PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
+#ifdef CONFIG_LOW_POWER_IDLE
+/* Used to wake up the EC from Deep Doze mode when writing to console */
+GPIO_INT(UART1_RX,	 	PIN(B, 0), GPIO_INT_BOTH, uart_deepsleep_interrupt)	/* UART_DBG_TX_EC_RX */
+#endif
+
+/* USB-C interrupts */
+GPIO_INT(USB_C0_INT_ODL,	PIN(K, 0), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt) /* BC12 and charger */
+GPIO_INT(SUB_USB_C1_INT_ODL,	PIN(E, 6), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c1_interrupt)
+GPIO_INT(USB_C0_CCSBU_OVP_ODL,	PIN(K, 6), GPIO_INT_FALLING | GPIO_PULL_UP, c0_ccsbu_ovp_interrupt) /* Fault protection */
+
+/* Other interrupts */
+GPIO_INT(LID_OPEN,		PIN(F, 3), GPIO_INT_BOTH, lid_interrupt)
+GPIO_INT(LID_360_L,		PIN(A, 7), GPIO_INT_BOTH, gmr_tablet_switch_isr)
+GPIO_INT(VOLDN_BTN_ODL,		PIN(I, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(VOLUP_BTN_ODL,		PIN(I, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(J, 0), GPIO_INT_FALLING | GPIO_SEL_1P8V, motion_interrupt)
+GPIO_INT(EC_WP_OD,		PIN(A, 6), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(PEN_DET_ODL,		PIN(J, 1), GPIO_INT_BOTH | GPIO_PULL_UP, pen_detect_interrupt)
+
+/* Power sequence GPIOs */
+GPIO(EC_AP_RTCRST,		PIN(K, 2), GPIO_OUT_LOW)
+GPIO(EC_AP_PWR_BTN_ODL,		PIN(B, 6), GPIO_ODR_HIGH)
+GPIO(EC_AP_DPWROK,		PIN(L, 7), GPIO_OUT_LOW)
+GPIO(EC_AP_RSMRST_L,		PIN(H, 0), GPIO_OUT_LOW)
+GPIO(EC_AP_WAKE_ODL,		PIN(D, 5), GPIO_ODR_HIGH)
+GPIO(SYS_RST_ODL,		PIN(D, 1), GPIO_ODR_HIGH)
+GPIO(EC_AP_SYS_PWROK,		PIN(F, 2), GPIO_OUT_LOW)
+GPIO(PG_PP5000_U_OD,		PIN(E, 3), GPIO_INPUT)
+GPIO(EN_PP3300_A,		PIN(C, 5), GPIO_OUT_LOW)
+GPIO(EC_AP_PCH_PWROK_OD,	PIN(D, 6), GPIO_ODR_LOW)
+GPIO(EN_PP5000_U,		PIN(K, 5), GPIO_OUT_LOW)
+/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
+GPIO(EN_VCCST,			PIN(D, 4), GPIO_INPUT)
+GPIO(EN_VCCIO_EXT,		PIN(B, 2), GPIO_OUT_LOW)
+GPIO(EC_PROCHOT_ODL,		PIN(I, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(EC_AP_VCCST_PWRGD_OD,	PIN(E, 5), GPIO_ODR_LOW)
+GPIO(ALL_SYS_PWRGD,		PIN(B, 7), GPIO_OUT_LOW)
+GPIO(EN_SLP_Z,			PIN(K, 3), GPIO_OUT_LOW)
+
+/* Required for icelake chipset code, but implemented through other means for dedede */
+UNIMPLEMENTED(AC_PRESENT)
+UNIMPLEMENTED(PG_EC_DSW_PWROK)
+UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
+
+/* I2C pins - Alternate function below configures I2C module on these pins */
+GPIO(EC_I2C_EEPROM_SCL,		PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SDA,		PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SCL,	PIN(C, 1), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SDA,	PIN(C, 2), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,		PIN(F, 6), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SENSOR_SDA,		PIN(F, 7), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SUB_USB_C1_SCL,	PIN(E, 0), GPIO_INPUT)
+GPIO(EC_I2C_SUB_USB_C1_SDA,	PIN(E, 7), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SCL,		PIN(A, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SDA,		PIN(A, 5), GPIO_INPUT)
+GPIO(EC_AP_USB_C0_HPD,		PIN(L, 4), GPIO_OUT_LOW)
+GPIO(EC_AP_USB_C1_HDMI_HPD,	PIN(K, 7), GPIO_OUT_LOW)
+GPIO(EN_USB_A0_VBUS,		PIN(L, 6), GPIO_OUT_LOW) /* Board rev 1, NC board rev 0 */
+
+/* MKBP event synchronization */
+GPIO(EC_AP_MKBP_INT_L,		PIN(L, 5), GPIO_ODR_HIGH)
+
+
+/* Misc */
+GPIO(EN_BL_OD,			PIN(K, 4), GPIO_ODR_LOW)
+GPIO(EC_ENTERING_RW,		PIN(G, 0), GPIO_OUT_LOW)
+GPIO(EC_ENTERING_RW2,		PIN(C, 7), GPIO_OUT_LOW)
+GPIO(CCD_MODE_ODL,		PIN(H, 5), GPIO_ODR_HIGH)
+GPIO(EC_BATTERY_PRES_ODL,	PIN(I, 4), GPIO_INPUT)
+GPIO(EN_PP3300_PEN,		PIN(B, 5), GPIO_OUT_LOW)
+GPIO(ECH1_PACKET_MODE,		PIN(H, 1), GPIO_OUT_LOW)
+
+/* LED */
+GPIO(LED_COLOR_AMBER,		PIN(A, 1), GPIO_OUT_HIGH)
+GPIO(LED_COLOR_WHITE,		PIN(A, 2), GPIO_OUT_HIGH)
+
+/* NC pins, enable internal pull-down to avoid floating state. */
+GPIO(GPIOA3_NC, PIN(A, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOC3_NC, PIN(C, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOC4_NC, PIN(C, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOC6_NC, PIN(C, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOF0_NC, PIN(F, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOF1_NC, PIN(F, 1), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOF4_NC, PIN(F, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOF5_NC, PIN(F, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG3_NC, PIN(G, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG4_NC, PIN(G, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG5_NC, PIN(G, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG6_NC, PIN(G, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG7_NC, PIN(G, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOH2_NC, PIN(H, 2), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOH4_NC, PIN(H, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOH6_NC, PIN(H, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ3_NC, PIN(J, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ4_NC, PIN(J, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ5_NC, PIN(J, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ6_NC, PIN(J, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOL0_NC, PIN(L, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOL3_NC, PIN(L, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOM6_NC, PIN(M, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+
+/* Alternate functions GPIO definitions */
+/* UART */
+ALTERNATE(PIN_MASK(B, BIT(0) | BIT(1)), 0, MODULE_UART, 0)		/* UART for debug */
+
+/* I2C */
+ALTERNATE(PIN_MASK(B, BIT(3) | BIT(4)), 0, MODULE_I2C, 0)		/* I2C0 EEPROM */
+ALTERNATE(PIN_MASK(C, BIT(1) | BIT(2)), 0, MODULE_I2C, 0)		/* I2C1 BATTERY */
+ALTERNATE(PIN_MASK(F, BIT(6) | BIT(7)), 0, MODULE_I2C, GPIO_SEL_1P8V)	/* I2C2 - 1.8V SENSOR */
+ALTERNATE(PIN_MASK(E, BIT(0) | BIT(7)), 0, MODULE_I2C, 0)		/* I2C4 SUB_USB_C1 */
+ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), 0, MODULE_I2C, 0)		/* I2C5 USB_C0 */
+
+/* ADC */
+ALTERNATE(PIN_MASK(L, BIT(2)), 0, MODULE_ADC, 0)    /* ADC15:TEMP_SENSOR3 */
+ALTERNATE(PIN_MASK(I, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0)	/* ADC0: EC_VSNS_PP3300_A, ADC2: TEMP_SENSOR_1, ADC3: TEMP_SENSOR_2 */
diff --git a/board/storo/led.c b/board/storo/led.c
new file mode 100644
index 0000000000..76bfc05861
--- /dev/null
+++ b/board/storo/led.c
@@ -0,0 +1,108 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power and battery LED control for Storo
+ */
+#include "chipset.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
+
+__override const int led_charge_lvl_1 = 5;
+__override const int led_charge_lvl_2 = 95;
+
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_WHITE,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_BATTERY_LED,
+};
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_WHITE:
+		gpio_set_level(GPIO_LED_COLOR_AMBER, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_COLOR_WHITE, LED_ON_LVL);
+		break;
+	case EC_LED_COLOR_AMBER:
+		gpio_set_level(GPIO_LED_COLOR_AMBER, LED_ON_LVL);
+		gpio_set_level(GPIO_LED_COLOR_WHITE, LED_OFF_LVL);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		gpio_set_level(GPIO_LED_COLOR_AMBER, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_COLOR_WHITE, LED_OFF_LVL);
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_battery(EC_LED_COLOR_WHITE);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(EC_LED_COLOR_AMBER);
+		else
+			led_set_color_battery(LED_OFF);
+	}
+	return EC_SUCCESS;
+}
+
+__override enum led_states board_led_get_state(enum led_states desired_state)
+{
+	/*
+	 * Battery error LED behavior as below:
+	 * S0: Blinking Amber LED, 1s on/ 1s off
+	 * S3/S5: following S3/S5 behavior
+	 * Add function to let battery error LED follow S3/S5 behavior in S3/S5.
+	 */
+
+	if (desired_state == STATE_BATTERY_ERROR) {
+		if (chipset_in_state(CHIPSET_STATE_ON))
+			return desired_state;
+		else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
+			return STATE_DISCHARGE_S3;
+		else
+			return STATE_DISCHARGE_S5;
+	}
+	return desired_state;
+}
diff --git a/board/storo/usb_pd_policy.c b/board/storo/usb_pd_policy.c
new file mode 100644
index 0000000000..83c09bb99e
--- /dev/null
+++ b/board/storo/usb_pd_policy.c
@@ -0,0 +1,61 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "driver/charger/isl923x_public.h"
+#include "driver/tcpm/tcpci.h"
+#include "usb_pd.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+int pd_check_vconn_swap(int port)
+{
+	/* Allow VCONN swaps if the AP is on. */
+	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
+}
+
+void pd_power_supply_reset(int port)
+{
+	/* Disable VBUS */
+	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	if (port >= board_get_usb_pd_port_count())
+		return EC_ERROR_INVAL;
+
+	/* Disable charging. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
+	if (rv)
+		return rv;
+
+	/* Our policy is not to source VBUS when the AP is off. */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	/* Provide Vbus. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
+	if (rv)
+		return rv;
+
+	rv = raa489000_enable_asgate(port, true);
+	if (rv)
+		return rv;
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
diff --git a/board/storo/vif_override.xml b/board/storo/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/storo/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/stryke/battery.c b/board/stryke/battery.c
index 0144c049b5..7690cd420f 100644
--- a/board/stryke/battery.c
+++ b/board/stryke/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/stryke/board.c b/board/stryke/board.c
index afec23450c..c1701e18d7 100644
--- a/board/stryke/board.c
+++ b/board/stryke/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,6 @@
 /* Stryke board-specific configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "button.h"
 #include "common.h"
 #include "cros_board_info.h"
@@ -34,16 +33,16 @@
 #include "system.h"
 #include "task.h"
 #include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
 #include "thermal.h"
-#include "thermistor.h"
 #include "uart.h"
 #include "usb_charge.h"
 #include "usb_pd.h"
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* GPIO to enable/disable the USB Type-A port. */
 const int usb_port_enable[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT] = {
@@ -93,11 +92,11 @@ static void bc12_interrupt(enum gpio_signal signal)
 {
 	switch (signal) {
 	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
 		break;
 
 	case GPIO_USB_C1_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12, 0);
+		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
 		break;
 
 	default:
@@ -105,20 +104,21 @@ static void bc12_interrupt(enum gpio_signal signal)
 	}
 }
 
-#include "gpio_list.h" /* Must come after other header files. */
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
 
 /******************************************************************************/
 /* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
+const struct spi_device_t spi_devices[] = {};
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
 /******************************************************************************/
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT]   = { .channel = 3, .flags = 0, .freq = 10000 },
-	[PWM_CH_FAN] = {.channel = 5, .flags = PWM_CONFIG_OPEN_DRAIN,
-			.freq = 25000},
+	[PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 },
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
@@ -138,22 +138,26 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = I2C_PORT_TCPC1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
 		},
 		.drv = &ps8xxx_tcpm_drv,
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_TCPC_0] = {
-		.usb_port = USB_PD_PORT_TCPC_0,
-		.driver = &anx7447_usb_mux_driver,
-		.hpd_update = &anx7447_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_0,
+			.driver = &anx7447_usb_mux_driver,
+			.hpd_update = &anx7447_tcpc_update_hpd_status,
+		},
 	},
 	[USB_PD_PORT_TCPC_1] = {
-		.usb_port = USB_PD_PORT_TCPC_1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 	}
 };
 
@@ -182,22 +186,18 @@ static struct bmi_drv_data_t g_bmi160_data;
 static struct accelgyro_saved_data_t g_bma255_data;
 
 /* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					      { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
 
 /*
  * TODO(b/124337208): P0 boards don't have this sensor mounted so the rotation
  * matrix can't be tested properly. This needs to be revisited after EVT to make
  * sure the rotaiton matrix for the lid sensor is correct.
  */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+					     { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
@@ -278,7 +278,7 @@ unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
@@ -297,52 +297,56 @@ const struct fan_t fans[FAN_CH_COUNT] = {
 /******************************************************************************/
 /* MFT channels. These are logically separate from pwm_channels. */
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN },
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_2] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_1] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_2] = { "TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Temp1",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Temp2",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_2},
+	[TEMP_SENSOR_1] = { .name = "Temp1",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Temp2",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
-
 /* Stryke Temperature sensors */
 /*
  * TODO(b/124316213): These setting need to be reviewed and set appropriately
  * for Stryke. They matter when the EC is controlling the fan as opposed to DPTF
  * control.
  */
-const static struct ec_thermal_config thermal_a = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(25),
-	.temp_fan_max = C_TO_K(50),
-};
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_A                \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+		.temp_fan_off = C_TO_K(25), \
+		.temp_fan_max = C_TO_K(50), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A;
 
 struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
 
@@ -383,7 +387,6 @@ static void board_gpio_set_pp5000(void)
 	} else if (board_id >= 1) {
 		reset_gpio_flags(GPIO_EN_PP5000_A_V1, GPIO_OUT_LOW);
 	}
-
 }
 
 static void board_init(void)
diff --git a/board/stryke/board.h b/board/stryke/board.h
index 4bc1839787..165cdd53a8 100644
--- a/board/stryke/board.h
+++ b/board/stryke/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,7 @@
 #define CONFIG_LED_COMMON
 #define CONFIG_LOW_POWER_IDLE
 
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 
 #undef CONFIG_UART_TX_BUF_SIZE
 #define CONFIG_UART_TX_BUF_SIZE 4096
@@ -26,7 +26,6 @@
 
 /* Sensors */
 /* BMI160 Base accel/gyro */
-#define CONFIG_ACCEL_INTERRUPTS
 #define CONFIG_ACCELGYRO_BMI160
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
@@ -81,7 +80,8 @@
 #define CONFIG_FANS 1
 #undef CONFIG_FAN_INIT_SPEED
 #define CONFIG_FAN_INIT_SPEED 50
-#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_A_RAILS
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_TEMP_SENSOR_POWER
 #define CONFIG_THERMISTOR
 #define CONFIG_THROTTLE_AP
 #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
@@ -100,15 +100,16 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_AC_PRESENT		GPIO_ACOK_OD
-#define GPIO_RSMRST_L_PGOOD	GPIO_PG_EC_RSMRST_L
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L
+#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
 
 #ifndef __ASSEMBLER__
 
@@ -120,8 +121,8 @@
 extern enum gpio_signal gpio_en_pp5000_a;
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_1,	/* ADC0 */
-	ADC_TEMP_SENSOR_2,	/* ADC1 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
 	ADC_CH_COUNT
 };
 
@@ -132,11 +133,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_FAN,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_FAN, PWM_CH_COUNT };
 
 enum fan_channel {
 	FAN_CH_0 = 0,
@@ -150,11 +147,7 @@ enum mft_channel {
 	MFT_CH_COUNT,
 };
 
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_COUNT
-};
+enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
diff --git a/board/stryke/build.mk b/board/stryke/build.mk
index 733912454f..13153c1526 100644
--- a/board/stryke/build.mk
+++ b/board/stryke/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/stryke/ec.tasklist b/board/stryke/ec.tasklist
index 4a1024a091..829be2b7c8 100644
--- a/board/stryke/ec.tasklist
+++ b/board/stryke/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/stryke/gpio.inc b/board/stryke/gpio.inc
index 8b241b2850..f839d16f84 100644
--- a/board/stryke/gpio.inc
+++ b/board/stryke/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,10 +16,10 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(PG_EC_RSMRST_L,       PIN(E, 2), GPIO_INT_BOTH, intel_x86_rsmrst_signal_interrupt)
diff --git a/board/stryke/led.c b/board/stryke/led.c
index b9ee4a9442..c5667edf2a 100644
--- a/board/stryke/led.c
+++ b/board/stryke/led.c
@@ -1,43 +1,48 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Power and battery LED control for Stryke
  */
 
+#include "chipset.h"
 #include "ec_commands.h"
 #include "gpio.h"
 #include "led_common.h"
 #include "led_onoff_states.h"
-#include "chipset.h"
 
 #define LED_ON_LVL 0
 #define LED_OFF_LVL 1
 
-const int led_charge_lvl_1 = 5;
+__override const int led_charge_lvl_1 = 5;
 
-const int led_charge_lvl_2 = 95;
+__override const int led_charge_lvl_2 = 95;
 
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-void led_set_color_battery(enum ec_led_colors color)
+__override void led_set_color_battery(enum ec_led_colors color)
 {
 	switch (color) {
 	case EC_LED_COLOR_AMBER:
@@ -76,4 +81,3 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 
 	return EC_SUCCESS;
 }
-
diff --git a/board/stryke/vif_override.xml b/board/stryke/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/stryke/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/sweetberry/OWNERS b/board/sweetberry/OWNERS
new file mode 100644
index 0000000000..3a4b8d3c05
--- /dev/null
+++ b/board/sweetberry/OWNERS
@@ -0,0 +1,2 @@
+bnemec@google.com
+matthewb@chromium.org
diff --git a/board/sweetberry/board.c b/board/sweetberry/board.c
index 66b21a81b9..b6b4460e51 100644
--- a/board/sweetberry/board.c
+++ b/board/sweetberry/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,7 +8,6 @@
 #include "dma.h"
 #include "ec_version.h"
 #include "gpio.h"
-#include "gpio_list.h"
 #include "hooks.h"
 #include "i2c.h"
 #include "registers.h"
@@ -24,18 +23,21 @@
 #include "usb_power.h"
 #include "util.h"
 
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
 /******************************************************************************
  * Define the strings used in our USB descriptors.
  */
 const void *const usb_strings[] = {
-	[USB_STR_DESC]		= usb_string_desc,
-	[USB_STR_VENDOR]	= USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]	= USB_STRING_DESC("Sweetberry"),
-	[USB_STR_SERIALNO]	= USB_STRING_DESC("1234-a"),
-	[USB_STR_VERSION]	= USB_STRING_DESC(CROS_EC_VERSION32),
-	[USB_STR_I2C_NAME]	= USB_STRING_DESC("I2C"),
-	[USB_STR_CONSOLE_NAME]	= USB_STRING_DESC("Sweetberry EC Shell"),
-	[USB_STR_UPDATE_NAME]	= USB_STRING_DESC("Firmware update"),
+	[USB_STR_DESC] = usb_string_desc,
+	[USB_STR_VENDOR] = USB_STRING_DESC("Google LLC"),
+	[USB_STR_PRODUCT] = USB_STRING_DESC("Sweetberry"),
+	[USB_STR_SERIALNO] = USB_STRING_DESC("1234-a"),
+	[USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32),
+	[USB_STR_I2C_NAME] = USB_STRING_DESC("I2C"),
+	[USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Sweetberry EC Shell"),
+	[USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"),
 };
 
 BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
@@ -59,28 +61,43 @@ struct dwc_usb usb_ctl = {
 
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{"i2c1", I2C_PORT_0, 400,
-		GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"i2c2", I2C_PORT_1, 400,
-		GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-	{"i2c3", I2C_PORT_2, 400,
-		GPIO_I2C3_SCL, GPIO_I2C3_SDA},
-	{"fmpi2c4", FMPI2C_PORT_3, 900,
-		GPIO_FMPI2C_SCL, GPIO_FMPI2C_SDA},
+	{ .name = "i2c1",
+	  .port = I2C_PORT_0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "i2c2",
+	  .port = I2C_PORT_1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "i2c3",
+	  .port = I2C_PORT_2,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
+	{ .name = "fmpi2c4",
+	  .port = FMPI2C_PORT_3,
+	  .kbps = 900,
+	  .scl = GPIO_FMPI2C_SCL,
+	  .sda = GPIO_FMPI2C_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
-int usb_i2c_board_is_enabled(void) { return 1; }
+int usb_i2c_board_is_enabled(void)
+{
+	return 1;
+}
 
-#define GPIO_SET_HS(bank, number)	\
-	(STM32_GPIO_OSPEEDR(GPIO_##bank) |= (0x3 << ((number) * 2)))
+#define GPIO_SET_HS(bank, number) \
+	(STM32_GPIO_OSPEEDR(GPIO_##bank) |= (0x3 << ((number)*2)))
 
 void board_config_post_gpio_init(void)
 {
 	/* We use MCO2 clock passthrough to provide a clock to USB HS */
 	gpio_config_module(MODULE_MCO, 1);
 	/* GPIO PC9 to high speed */
-	GPIO_SET_HS(C,  9);
+	GPIO_SET_HS(C, 9);
 
 	if (usb_ctl.phy_type == USB_PHY_ULPI)
 		gpio_set_level(GPIO_USB_MUX_SEL, 0);
@@ -91,29 +108,29 @@ void board_config_post_gpio_init(void)
 	GPIO_SET_HS(A, 11);
 	GPIO_SET_HS(A, 12);
 
-	GPIO_SET_HS(C,  3);
-	GPIO_SET_HS(C,  2);
-	GPIO_SET_HS(C,  0);
-	GPIO_SET_HS(A,  5);
+	GPIO_SET_HS(C, 3);
+	GPIO_SET_HS(C, 2);
+	GPIO_SET_HS(C, 0);
+	GPIO_SET_HS(A, 5);
 
-	GPIO_SET_HS(B,  5);
+	GPIO_SET_HS(B, 5);
 	GPIO_SET_HS(B, 13);
 	GPIO_SET_HS(B, 12);
-	GPIO_SET_HS(B,  2);
+	GPIO_SET_HS(B, 2);
 	GPIO_SET_HS(B, 10);
-	GPIO_SET_HS(B,  1);
-	GPIO_SET_HS(B,  0);
-	GPIO_SET_HS(A,  3);
+	GPIO_SET_HS(B, 1);
+	GPIO_SET_HS(B, 0);
+	GPIO_SET_HS(A, 3);
 
 	/* Set I2C GPIO to HS */
-	GPIO_SET_HS(B,  6);
-	GPIO_SET_HS(B,  7);
-	GPIO_SET_HS(F,  1);
-	GPIO_SET_HS(F,  0);
-	GPIO_SET_HS(A,  8);
-	GPIO_SET_HS(B,  4);
-	GPIO_SET_HS(C,  6);
-	GPIO_SET_HS(C,  7);
+	GPIO_SET_HS(B, 6);
+	GPIO_SET_HS(B, 7);
+	GPIO_SET_HS(F, 1);
+	GPIO_SET_HS(F, 0);
+	GPIO_SET_HS(A, 8);
+	GPIO_SET_HS(B, 4);
+	GPIO_SET_HS(C, 6);
+	GPIO_SET_HS(C, 7);
 }
 
 static void board_init(void)
diff --git a/board/sweetberry/board.h b/board/sweetberry/board.h
index 1edea99b9a..4d945f5dc4 100644
--- a/board/sweetberry/board.h
+++ b/board/sweetberry/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -48,28 +48,28 @@
 #define DEFAULT_SERIALNO "Uninitialized"
 
 /* USB interface indexes (use define rather than enum to expand them) */
-#define USB_IFACE_CONSOLE	0
-#define USB_IFACE_UPDATE	1
-#define USB_IFACE_POWER		2
-#define USB_IFACE_I2C		3
-#define USB_IFACE_COUNT		4
+#define USB_IFACE_CONSOLE 0
+#define USB_IFACE_UPDATE 1
+#define USB_IFACE_POWER 2
+#define USB_IFACE_I2C 3
+#define USB_IFACE_COUNT 4
 
 /* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL		0
-#define USB_EP_CONSOLE		1
-#define USB_EP_UPDATE		2
-#define USB_EP_POWER		3
-#define USB_EP_I2C		4
-#define USB_EP_COUNT		5
+#define USB_EP_CONTROL 0
+#define USB_EP_CONSOLE 1
+#define USB_EP_UPDATE 2
+#define USB_EP_POWER 3
+#define USB_EP_I2C 4
+#define USB_EP_COUNT 5
 
 #define CONFIG_USB_I2C
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
-#define I2C_PORT_0	0
-#define I2C_PORT_1	1
-#define I2C_PORT_2	2
-#define FMPI2C_PORT_3	3
-#define I2C_PORT_COUNT	4
+#define CONFIG_I2C_CONTROLLER
+#define I2C_PORT_0 0
+#define I2C_PORT_1 1
+#define I2C_PORT_2 2
+#define FMPI2C_PORT_3 3
+#define I2C_PORT_COUNT 4
 
 /* This is not actually a Chromium EC so disable some features. */
 #undef CONFIG_WATCHDOG_HELP
@@ -77,7 +77,6 @@
 #undef CONFIG_WATCHDOG
 
 /* Optional features */
-#define CONFIG_STM_HWTIMER32
 
 /*
  * Allow dangerous commands all the time, since we don't have a write protect
diff --git a/board/sweetberry/build.mk b/board/sweetberry/build.mk
index 6b06f2bb8f..61e4b79d47 100644
--- a/board/sweetberry/build.mk
+++ b/board/sweetberry/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/sweetberry/ec.tasklist b/board/sweetberry/ec.tasklist
index c1fb169118..c45a1e89a7 100644
--- a/board/sweetberry/ec.tasklist
+++ b/board/sweetberry/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/sweetberry/gpio.inc b/board/sweetberry/gpio.inc
index cfab7fc1f3..28b91d0dec 100644
--- a/board/sweetberry/gpio.inc
+++ b/board/sweetberry/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/taeko/battery.c b/board/taeko/battery.c
new file mode 100644
index 0000000000..24ce4c1bdf
--- /dev/null
+++ b/board/taeko/battery.c
@@ -0,0 +1,159 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery.h"
+#include "battery_fuel_gauge.h"
+#include "battery_smart.h"
+#include "common.h"
+#include "util.h"
+/*
+ * Battery info for all Taeko battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	[BATTERY_SMP_51W] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP",
+			.device_name = "L21M4PG4",
+			.ship_mode = {
+				.reg_addr = 0x34,
+				.reg_data = { 0x0000, 0x1000 },
+			},
+			.fet = {
+				.reg_addr = 0x34,
+				.reg_mask = 0x0100,
+				.disconnect_val = 0x0100,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 8900, /* mV */
+			.voltage_normal		= 7720, /* mV */
+			.voltage_min		= 6000, /* mV */
+			.precharge_current	= 330,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 60,
+		},
+	},
+	[BATTERY_SUNWODA] = {
+		.fuel_gauge = {
+			.manuf_name = "Sunwoda",
+			.device_name = "L21D4PG4",
+			.ship_mode = {
+				.reg_addr = 0x34,
+				.reg_data = { 0x0000, 0x1000 },
+			},
+			.fet = {
+				.reg_addr = 0x34,
+				.reg_mask = 0x0100,
+				.disconnect_val = 0x0100,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 8900, /* mV */
+			.voltage_normal		= 7720, /* mV */
+			.voltage_min		= 6000, /* mV */
+			.precharge_current	= 330,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 60,
+		},
+	},
+	[BATTERY_SMP_71W] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP",
+			.device_name = "L21M4PG5",
+			.ship_mode = {
+				.reg_addr = 0x34,
+				.reg_data = { 0x0000, 0x1000 },
+			},
+			.fet = {
+				.reg_addr = 0x00,
+				.reg_mask = 0x0018,
+				.disconnect_val = 0x0000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 8800, /* mV */
+			.voltage_normal		= 7680, /* mV */
+			.voltage_min		= 6000, /* mV */
+			.precharge_current	= 464,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 60,
+		},
+	},
+	[BATTERY_LGC] = {
+		.fuel_gauge = {
+			.manuf_name = "LGES",
+			.device_name = "L21L4PG5",
+			.ship_mode = {
+				.reg_addr = 0x34,
+				.reg_data = { 0x0000, 0x1000 },
+			},
+			.fet = {
+				.reg_addr = 0x00,
+				.reg_mask = 0x0018,
+				.disconnect_val = 0x0000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 8800, /* mV */
+			.voltage_normal		= 7680, /* mV */
+			.voltage_min		= 6000, /* mV */
+			.precharge_current	= 512,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 60,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SMP_51W;
+
+__override bool board_battery_is_initialized(void)
+{
+	bool batt_initialization_state;
+	int batt_status;
+
+	batt_initialization_state =
+		(battery_status(&batt_status) ?
+			 false :
+			 !!(batt_status & STATUS_INITIALIZED));
+	return batt_initialization_state;
+}
diff --git a/board/taeko/board.c b/board/taeko/board.c
new file mode 100644
index 0000000000..aaf7f215ff
--- /dev/null
+++ b/board/taeko/board.c
@@ -0,0 +1,138 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "button.h"
+#include "charge_manager.h"
+#include "charge_ramp.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/accel_lis2dw12.h"
+#include "driver/accelgyro_lsm6dsm.h"
+#include "driver/accelgyro_lsm6dso.h"
+#include "driver/als_tcs3400.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "keyboard_raw.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "registers.h"
+#include "switch.h"
+#include "tablet_mode.h"
+#include "throttle_ap.h"
+#include "usbc_config.h"
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* Console output macros */
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+
+/******************************************************************************/
+/* USB-A charging control */
+
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_PP5000_USBA_R,
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
+
+/******************************************************************************/
+
+__override void board_cbi_init(void)
+{
+	config_usb_db_type();
+}
+
+void board_init(void)
+{
+	if (!ec_cfg_has_tabletmode()) {
+		/* applies only to clamshell devices */
+		gpio_set_flags(GPIO_VOLUME_DOWN_L, GPIO_INPUT | GPIO_PULL_DOWN);
+		gpio_set_flags(GPIO_VOLUME_UP_L, GPIO_INPUT | GPIO_PULL_DOWN);
+		button_disable_gpio(BUTTON_VOLUME_UP);
+		button_disable_gpio(BUTTON_VOLUME_DOWN);
+	}
+	if (!ec_cfg_has_keyboard_number_pad()) {
+		/* Disable scanning KSO13 and 14 if keypad isn't present. */
+		keyboard_raw_set_cols(KEYBOARD_COLS_NO_KEYPAD);
+	} else {
+		/* Setting scan mask KSO11, KSO12, KSO13 and KSO14 */
+		keyscan_config.actual_key_mask[11] = 0xfe;
+		keyscan_config.actual_key_mask[12] = 0xff;
+		keyscan_config.actual_key_mask[13] = 0xff;
+		keyscan_config.actual_key_mask[14] = 0xff;
+	}
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S3 -> S0 transition */
+static void board_chipset_resume(void)
+{
+	/* Allow keyboard backlight to be enabled */
+	if (ec_cfg_has_keyboard_backlight() == 1) {
+		/* GPIO_EC_KB_BL_EN_L is low active pin */
+		gpio_set_level(GPIO_EC_KB_BL_EN_L, 0);
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S0 -> S3 transition */
+static void board_chipset_suspend(void)
+{
+	/* Turn off the keyboard backlight if it's on. */
+	if (ec_cfg_has_keyboard_backlight() == 1) {
+		/* GPIO_EC_KB_BL_EN_L is low active pin */
+		gpio_set_level(GPIO_EC_KB_BL_EN_L, 1);
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
+
+#ifdef CONFIG_CHARGE_RAMP_SW
+
+/*
+ * TODO: tune this threshold
+ */
+
+#define BC12_MIN_VOLTAGE 4400
+
+/**
+ * Return true if VBUS is too low
+ */
+int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
+{
+	int voltage;
+
+	if (charger_get_vbus_voltage(port, &voltage))
+		voltage = 0;
+
+	if (voltage == 0) {
+		CPRINTS("%s: must be disconnected", __func__);
+		return 1;
+	}
+
+	if (voltage < BC12_MIN_VOLTAGE) {
+		CPRINTS("%s: port %d: vbus %d lower than %d", __func__, port,
+			voltage, BC12_MIN_VOLTAGE);
+		return 1;
+	}
+
+	return 0;
+}
+
+#endif /* CONFIG_CHARGE_RAMP_SW */
+
+enum battery_present battery_hw_present(void)
+{
+	/* The GPIO is low when the battery is physically present */
+	return gpio_get_level(GPIO_EC_BATT_PRES_ODL) ? BP_NO : BP_YES;
+}
diff --git a/board/taeko/board.h b/board/taeko/board.h
new file mode 100644
index 0000000000..d57010a9ff
--- /dev/null
+++ b/board/taeko/board.h
@@ -0,0 +1,261 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Taeko board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "compile_time_macros.h"
+
+/*
+ * Taeko boards are set up for vivaldi
+ */
+#define CONFIG_KEYBOARD_VIVALDI
+#define CONFIG_KEYBOARD_REFRESH_ROW3
+#define CONFIG_KEYBOARD_STRICT_DEBOUNCE
+/* Baseboard features */
+#include "baseboard.h"
+
+/*
+ * This will happen automatically on NPCX9 ES2 and later. Do not remove
+ * until we can confirm all earlier chips are out of service.
+ */
+#define CONFIG_HIBERNATE_PSL_VCC1_RST_WAKEUP
+
+#define CONFIG_MP2964
+
+/* OEM requested 5% charger current margin */
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 5
+
+/* LED */
+#define CONFIG_LED_ONOFF_STATES
+
+/* Sensors */
+#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
+
+/* Button */
+#define CONFIG_BUTTONS_RUNTIME_CONFIG
+
+/* Change Request (b/199529373)
+ * GYRO sensor change from ST LSM6DSOETR3TR to ST LSM6DS3TR-C
+ *	LSM6DSOETR3TR base accel/gyro if board id = 0
+ *	LSM6DS3TR-C Base accel/gyro if board id > 0
+ */
+#define CONFIG_ACCELGYRO_LSM6DSO /* Base accel */
+#define CONFIG_ACCEL_LSM6DSO_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+#define CONFIG_ACCELGYRO_LSM6DSM
+#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+/* Enable sensor fifo, must also define the _SIZE and _THRES */
+#define CONFIG_ACCEL_FIFO
+/* FIFO size is in power of 2. */
+#define CONFIG_ACCEL_FIFO_SIZE 256
+/* Depends on how fast the AP boots and typical ODRs */
+#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
+
+/* Sensors without hardware FIFO are in forced mode */
+#define CONFIG_ACCEL_FORCE_MODE_MASK (BIT(LID_ACCEL))
+
+/* Lid accel */
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_UPDATE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+#define CONFIG_ACCEL_BMA4XX
+#define CONFIG_ACCEL_LIS2DWL
+
+/* Sensor console commands */
+#define CONFIG_CMD_ACCELS
+#define CONFIG_CMD_ACCEL_INFO
+
+/* USB Type A Features */
+#define USB_PORT_COUNT 1
+#define CONFIG_USB_PORT_POWER_DUMB
+
+/* USB Type C and USB PD defines */
+#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
+
+#define CONFIG_IO_EXPANDER
+#define CONFIG_IO_EXPANDER_NCT38XX
+#define CONFIG_IO_EXPANDER_PORT_COUNT 1
+
+#define CONFIG_USB_PD_FRS_PPC
+#define CONFIG_USB_PD_FRS
+#define CONFIG_USB_PD_TCPM_PS8815
+#define CONFIG_USB_PD_TCPM_PS8815_FORCE_DID
+#define CONFIG_USBC_PPC_SYV682X
+#define CONFIG_USBC_PPC_NX20P3483
+#define CONFIG_USBC_NX20P348X_RCP_5VSRC_MASK_ENABLE
+
+/* I2C speed console command */
+#define CONFIG_CMD_I2C_SPEED
+
+/* I2C control host command */
+#define CONFIG_HOSTCMD_I2C_CONTROL
+
+/* TODO: b/177608416 - measure and check these values on brya */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
+
+/*
+ * Passive USB-C cables only support up to 60W.
+ */
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 45000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
+
+/* The lower the input voltage, the higher the power efficiency. */
+#define PD_PREFER_LOW_VOLTAGE
+
+#undef CONFIG_CMD_POWERINDEBUG
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
+
+/*
+ * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
+ * signal.
+ */
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
+
+/* System has back-lit keyboard */
+#define CONFIG_PWM_KBLIGHT
+
+/* I2C Bus Configuration */
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0_TCPC NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1
+#define I2C_PORT_USB_C0_PPC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C0_BC12 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+
+#define I2C_ADDR_MP2964_FLAGS 0x20
+
+/* Thermal features */
+#define CONFIG_THERMISTOR
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_TEMP_SENSOR_POWER
+#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
+
+/* Fan */
+#define CONFIG_FANS FAN_CH_COUNT
+
+/* Charger defines */
+#define CONFIG_CHARGER_BQ25720
+#define CONFIG_CHARGER_BQ25720_VSYS_TH2_CUSTOM
+/* 37h BIT7:2 VSYS_TH2 6.0V */
+#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV 60
+#define CONFIG_CHARGE_RAMP_SW
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10
+/* 30h BIT13:12 Enable PSYS 00b */
+#define CONFIG_CHARGER_BQ25710_PSYS_SENSING
+/* 31h BIT3 = 1 Enable ACOC */
+#define CONFIG_CHARGER_BQ25710_EN_ACOC
+/* 33h BIT15:11 ILIM2 TH 140% */
+#define CONFIG_CHARGER_BQ257X0_ILIM2_VTH_CUSTOM
+#define CONFIG_CHARGER_BQ257X0_ILIM2_VTH \
+	BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH__1P40
+/* 34h BIT0 CONFIG_CHARGER_BQ25710_PP_ACOK */
+#define CONFIG_CHARGER_BQ25710_PP_ACOK
+/* 34h BIT3 and BIT15:10 IDCHG 9728mA, step is 512mA */
+#define CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA 9728
+/* 34h BIT6 CONFIG_CHARGER_BQ25710_PP_COMP */
+#define CONFIG_CHARGER_BQ25710_PP_COMP
+/* 36h UVP 5600mV */
+#define CONFIG_CHARGER_BQ25720_VSYS_UVP_CUSTOM
+#define CONFIG_CHARGER_BQ25720_VSYS_UVP BQ25720_CHARGE_OPTION_4_VSYS_UVP__5P6
+/* 3Eh BIT15:8 VSYS_MIN 6.1V */
+#define CONFIG_CHARGER_BQ25710_VSYS_MIN_VOLTAGE_CUSTOM
+#define CONFIG_CHARGER_BQ25710_VSYS_MIN_VOLTAGE_MV 6100
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h" /* needed by registers.h */
+#include "registers.h"
+#include "usbc_config.h"
+
+enum adc_channel {
+	ADC_TEMP_SENSOR_1_DDR_SOC,
+	ADC_TEMP_SENSOR_2_FAN,
+	ADC_TEMP_SENSOR_3_CHARGER,
+	ADC_TEMP_SENSOR_4_CPUCHOKE,
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1_DDR_SOC,
+	TEMP_SENSOR_2_FAN,
+	TEMP_SENSOR_3_CHARGER,
+	TEMP_SENSOR_4_CPUCHOKE,
+	TEMP_SENSOR_COUNT
+};
+
+enum sensor_id { LID_ACCEL = 0, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
+
+enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_PORT_COUNT };
+
+enum battery_type {
+	BATTERY_SMP_51W,
+	BATTERY_SMP_71W,
+	BATTERY_LGC,
+	BATTERY_SUNWODA,
+	BATTERY_TYPE_COUNT,
+};
+
+enum pwm_channel {
+	PWM_CH_KBLIGHT = 0, /* PWM3 */
+	PWM_CH_FAN, /* PWM5 */
+	PWM_CH_COUNT
+};
+
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT };
+
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT };
+
+void motion_interrupt(enum gpio_signal signal);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/taeko/build.mk b/board/taeko/build.mk
new file mode 100644
index 0000000000..9d193faf4e
--- /dev/null
+++ b/board/taeko/build.mk
@@ -0,0 +1,25 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Taeko board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx9
+CHIP_VARIANT:=npcx9m3f
+BASEBOARD:=brya
+
+board-y=
+board-y+=battery.o
+board-y+=board.o
+board-y+=charger.o
+board-y+=fans.o
+board-y+=fw_config.o
+board-y+=i2c.o
+board-y+=keyboard.o
+board-y+=led.o
+board-y+=pwm.o
+board-y+=sensors.o
+board-y+=usbc_config.o
diff --git a/board/taeko/charger.c b/board/taeko/charger.c
new file mode 100644
index 0000000000..827152e115
--- /dev/null
+++ b/board/taeko/charger.c
@@ -0,0 +1,82 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/charger/bq25710.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+#ifndef CONFIG_ZEPHYR
+/* Charger Chip Configuration */
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = BQ25710_SMBUS_ADDR1_FLAGS,
+		.drv = &bq25710_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CHARGER_NUM);
+#endif
+
+int board_set_active_charge_port(int port)
+{
+	int is_valid_port = board_is_usb_pd_port_present(port);
+	int i;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTSUSB("Disabling all charger ports");
+
+		/* Disable all ports. */
+		for (i = 0; i < ppc_cnt; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (ppc_vbus_sink_enable(i, 0))
+				CPRINTSUSB("Disabling C%d as sink failed.", i);
+		}
+
+		return EC_SUCCESS;
+	} else if (!is_valid_port) {
+		return EC_ERROR_INVAL;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (ppc_is_sourcing_vbus(port)) {
+		CPRINTFUSB("Skip enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTSUSB("New charge port: C%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < ppc_cnt; i++) {
+		if (i == port)
+			continue;
+
+		if (ppc_vbus_sink_enable(i, 0))
+			CPRINTSUSB("C%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTSUSB("C%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/board/taeko/ec.tasklist b/board/taeko/ec.tasklist
new file mode 100644
index 0000000000..29fd0bf4cb
--- /dev/null
+++ b/board/taeko/ec.tasklist
@@ -0,0 +1,30 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ *
+ * USB_CHG_Px tasks must be contiguous (see USB_CHG_PORT_TO_TASK_ID(x)).
+ * PD_Cx tasks must be contiguous (see PD_PORT_TO_TASK_ID(x))
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, HOOKS_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, BASEBOARD_CHG_RAMP_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, BASEBOARD_CHARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, BASEBOARD_CHIPSET_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, CONSOLE_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, BASEBOARD_POWERBTN_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, BASEBOARD_PD_INT_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, BASEBOARD_PD_INT_TASK_STACK_SIZE)
diff --git a/board/taeko/fans.c b/board/taeko/fans.c
new file mode 100644
index 0000000000..ccfec5bc0d
--- /dev/null
+++ b/board/taeko/fans.c
@@ -0,0 +1,88 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Physical fans. These are logically separate from pwm_channels. */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "fan.h"
+#include "fan_chip.h"
+#include "hooks.h"
+#include "pwm.h"
+
+/* MFT channels. These are logically separate from pwm_channels. */
+const struct mft_t mft_channels[] = {
+	[MFT_CH_0] = {
+		.module = NPCX_MFT_MODULE_1,
+		.clk_src = TCKC_LFCLK,
+		.pwm_id = PWM_CH_FAN,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
+
+static const struct fan_conf fan_conf_0 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
+	.pgood_gpio = -1,
+	.enable_gpio = GPIO_EN_PP5000_FAN,
+};
+
+/*
+ * TOOD(b/194774929): need to update for real fan
+ *
+ * Prototype fan spins at about 7200 RPM at 100% PWM.
+ * Set minimum at around 30% PWM.
+ */
+static const struct fan_rpm fan_rpm_0 = {
+	.rpm_min = 2200,
+	.rpm_start = 2200,
+	.rpm_max = 7200,
+};
+
+const struct fan_t fans[FAN_CH_COUNT] = {
+	[FAN_CH_0] = {
+		.conf = &fan_conf_0,
+		.rpm = &fan_rpm_0,
+	},
+};
+
+#ifndef CONFIG_FANS
+
+/*
+ * TODO(b/194774929): use static fan speeds until fan and sensors are
+ * tuned. for now, use:
+ *
+ *   AP off:  33%
+ *   AP  on: 100%
+ */
+
+static void fan_slow(void)
+{
+	const int duty_pct = 33;
+
+	ccprints("%s: speed %d%%", __func__, duty_pct);
+
+	pwm_enable(PWM_CH_FAN, 1);
+	pwm_set_duty(PWM_CH_FAN, duty_pct);
+}
+
+static void fan_max(void)
+{
+	const int duty_pct = 100;
+
+	ccprints("%s: speed %d%%", __func__, duty_pct);
+
+	pwm_enable(PWM_CH_FAN, 1);
+	pwm_set_duty(PWM_CH_FAN, duty_pct);
+}
+
+DECLARE_HOOK(HOOK_INIT, fan_slow, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, fan_slow, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, fan_slow, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_RESET, fan_max, HOOK_PRIO_FIRST);
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, fan_max, HOOK_PRIO_DEFAULT);
+
+#endif /* CONFIG_FANS */
diff --git a/board/taeko/fw_config.c b/board/taeko/fw_config.c
new file mode 100644
index 0000000000..e04386051d
--- /dev/null
+++ b/board/taeko/fw_config.c
@@ -0,0 +1,102 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "fw_config.h"
+#include "gpio.h"
+
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
+
+static union taeko_cbi_fw_config fw_config;
+BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
+
+/*
+ * FW_CONFIG defaults for Taeko if the CBI.FW_CONFIG data is not
+ * initialized.
+ */
+static const union taeko_cbi_fw_config fw_config_defaults = {
+	.usb_db = DB_USB3_PS8815,
+	.kb_bl = KEYBOARD_BACKLIGHT_ENABLED,
+};
+
+/****************************************************************************
+ * Taeko FW_CONFIG access
+ */
+static void determine_storage(void)
+{
+	const bool has_nvme = fw_config.nvme_status == NVME_ENABLED;
+	const bool has_emmc = fw_config.emmc_status == EMMC_ENABLED;
+
+	/*
+	 * If both masks are enabled or disabled, read the EMMC_SKU_DET pin
+	 * (should happen only in the factory).
+	 */
+	if (has_nvme == has_emmc) {
+		/* 0 = eMMC SKU, 1 = NVMe SKU */
+		if (gpio_get_level(GPIO_EMMC_SKU_DET)) {
+			CPRINTS("CBI: Detected NVMe SKU, disabling eMMC");
+			fw_config.emmc_status = EMMC_DISABLED;
+			fw_config.nvme_status = NVME_ENABLED;
+		} else {
+			CPRINTS("CBI: Detected eMMC SKU, disabling NVMe");
+			fw_config.nvme_status = NVME_DISABLED;
+			fw_config.emmc_status = EMMC_ENABLED;
+		}
+	}
+
+	cbi_set_board_info(CBI_TAG_FW_CONFIG, (uint8_t *)&fw_config,
+			   sizeof(fw_config));
+}
+
+void board_init_fw_config(void)
+{
+	if (cbi_get_fw_config(&fw_config.raw_value)) {
+		CPRINTS("CBI: Read FW_CONFIG failed, using board defaults");
+		fw_config = fw_config_defaults;
+	}
+
+	if (get_board_id() == 0) {
+		/*
+		 * Early boards doesn't have correct FW_CONFIG, so replace
+		 * it with a sensible default value.
+		 */
+		CPRINTS("CBI: Using board defaults for early board");
+		if (ec_cfg_has_tabletmode()) {
+			fw_config = fw_config_defaults;
+			fw_config.tabletmode = TABLETMODE_ENABLED;
+		} else
+			fw_config = fw_config_defaults;
+	}
+
+	determine_storage();
+}
+
+union taeko_cbi_fw_config get_fw_config(void)
+{
+	return fw_config;
+}
+
+enum ec_cfg_usb_db_type ec_cfg_usb_db_type(void)
+{
+	return fw_config.usb_db;
+}
+
+bool ec_cfg_has_keyboard_backlight(void)
+{
+	return (fw_config.kb_bl == KEYBOARD_BACKLIGHT_ENABLED);
+}
+
+bool ec_cfg_has_tabletmode(void)
+{
+	return (fw_config.tabletmode == TABLETMODE_ENABLED);
+}
+
+bool ec_cfg_has_keyboard_number_pad(void)
+{
+	return (fw_config.kbnumpad == KEYBOARD_NUMBER_PAD);
+}
diff --git a/board/taeko/fw_config.h b/board/taeko/fw_config.h
new file mode 100644
index 0000000000..5217a72d0a
--- /dev/null
+++ b/board/taeko/fw_config.h
@@ -0,0 +1,101 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __BOARD_TAEKO_FW_CONFIG_H_
+#define __BOARD_TAEKO_FW_CONFIG_H_
+
+#include <stdint.h>
+
+/****************************************************************************
+ * CBI FW_CONFIG layout for Taeko board.
+ *
+ * Source of truth is the project/taeko/taeko/config.star configuration file.
+ */
+
+enum ec_cfg_usb_db_type { DB_USB_ABSENT = 0, DB_USB3_PS8815 = 1 };
+
+enum ec_cfg_keyboard_backlight_type {
+	KEYBOARD_BACKLIGHT_DISABLED = 0,
+	KEYBOARD_BACKLIGHT_ENABLED = 1
+};
+
+enum ec_cfg_tabletmode_type { TABLETMODE_DISABLED = 0, TABLETMODE_ENABLED = 1 };
+
+enum ec_cfg_kbnumpad {
+	KEYBOARD_NUMBER_PAD_ABSENT = 0,
+	KEYBOARD_NUMBER_PAD = 1
+};
+
+enum ec_cfg_nvme_status {
+	NVME_DISABLED = 0,
+	NVME_ENABLED = 1,
+};
+
+enum ec_cfg_emmc_status {
+	EMMC_DISABLED = 0,
+	EMMC_ENABLED = 1,
+};
+
+union taeko_cbi_fw_config {
+	struct {
+		enum ec_cfg_usb_db_type usb_db : 2;
+		uint32_t sd_db : 2;
+		enum ec_cfg_keyboard_backlight_type kb_bl : 1;
+		uint32_t audio : 3;
+		uint32_t reserved_1 : 4;
+		/* b/194515356 - Fw config structure
+		 * b/203630618 - Move tablet mode to bit14
+		 * bit8-9: kb_layout
+		 * bit10-11: wifi_sar_id,
+		 * bit12: nvme
+		 * bit13: emmc
+		 */
+		enum ec_cfg_nvme_status nvme_status : 1;
+		enum ec_cfg_emmc_status emmc_status : 1;
+		enum ec_cfg_tabletmode_type tabletmode : 1;
+		enum ec_cfg_kbnumpad kbnumpad : 1;
+		uint32_t reserved_2 : 16;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Read the cached FW_CONFIG.  Guaranteed to have valid values.
+ *
+ * @return the FW_CONFIG for the board.
+ */
+union taeko_cbi_fw_config get_fw_config(void);
+
+/**
+ * Get the USB daughter board type from FW_CONFIG.
+ *
+ * @return the USB daughter board type.
+ */
+enum ec_cfg_usb_db_type ec_cfg_usb_db_type(void);
+
+/**
+ * Check if the FW_CONFIG has enabled keyboard backlight.
+ *
+ * @return true if board supports keyboard backlight, false if the board
+ * doesn't support it.
+ */
+bool ec_cfg_has_keyboard_backlight(void);
+
+/**
+ * Check if the FW_CONFIG has enabled tablet mode.
+ *
+ * @return true if board supports tablet mode, false if the board
+ * doesn't support it.
+ */
+bool ec_cfg_has_tabletmode(void);
+
+/**
+ * Check if the FW_CONFIG has enable keyboard number pad.
+ *
+ * @return true if board supports keyboard number pad, false if the
+ * keyboard number pad doesn't support it.
+ */
+bool ec_cfg_has_keyboard_number_pad(void);
+#endif /* __BOARD_TAEKO_FW_CONFIG_H_ */
diff --git a/board/taeko/gpio.inc b/board/taeko/gpio.inc
new file mode 100644
index 0000000000..44cb489257
--- /dev/null
+++ b/board/taeko/gpio.inc
@@ -0,0 +1,143 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define MODULE_KB		MODULE_KEYBOARD_SCAN
+
+/* INTERRUPT GPIOs: */
+GPIO_INT(ACOK_OD,                        PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
+GPIO_INT(EC_IMU_INT_R_L,                 PIN(5, 6), GPIO_SEL_1P8V | GPIO_INT_FALLING, lsm6dsm_interrupt)
+GPIO_INT(EC_PROCHOT_IN_L,                PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
+GPIO_INT(EC_VOLDN_BTN_ODL,               PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(EC_VOLUP_BTN_ODL,               PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(EC_WP_ODL,                      PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(GSC_EC_PWR_BTN_ODL,             PIN(0, 1), GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW, power_button_interrupt)
+GPIO_INT(LID_OPEN,                       PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
+GPIO_INT(SEQ_EC_ALL_SYS_PG,              PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_DSW_PWROK,               PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_RSMRST_ODL,              PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,                       PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,                      PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SYS_SLP_S0IX_L,                 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(TABLET_MODE_L,                  PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
+GPIO_INT(USB_C0_BC12_INT_ODL,            PIN(C, 6), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C0_TCPC_INT_ODL,            PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C0_PPC_INT_ODL,             PIN(6, 2), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C1_BC12_INT_ODL,            PIN(5, 0), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C1_TCPC_INT_ODL,            PIN(A, 2), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C1_PPC_INT_ODL,             PIN(F, 5), GPIO_INT_FALLING, ppc_interrupt)
+
+/* USED GPIOs: */
+GPIO(CCD_MODE_ODL,                   PIN(E, 5), GPIO_INPUT)
+GPIO(CHARGER_VAP_OTG_EN,             PIN(7, 3), GPIO_OUT_LOW)
+GPIO(CPU_C10_GATE_L,                 PIN(6, 7), GPIO_INPUT)
+GPIO(EC_ACCEL_INT_R_L,               PIN(8, 1), GPIO_INPUT)
+GPIO(EC_BATT_PRES_ODL,               PIN(A, 3), GPIO_INPUT)
+GPIO(EC_ENTERING_RW,                 PIN(0, 3), GPIO_OUT_LOW)
+GPIO(EC_EN_EDP_BL,                   PIN(D, 3), GPIO_OUT_HIGH)
+GPIO(EC_GSC_PACKET_MODE,             PIN(7, 5), GPIO_OUT_LOW)
+GPIO(EC_I2C_BAT_SCL,                 PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_BAT_SDA,                 PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SCL_R,              PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SDA_R,              PIN(B, 2), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,              PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SENSOR_SDA,              PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_USB_C0_PPC_BC_SCL,       PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_PPC_BC_SDA,       PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_RT_SCL,           PIN(D, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_RT_SDA,           PIN(D, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_TCPC_SCL,         PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_TCPC_SDA,         PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_MIX_SCL,          PIN(E, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_MIX_SDA,          PIN(E, 3), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_TCPC_SCL,         PIN(F, 3), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_TCPC_SDA,         PIN(F, 2), GPIO_INPUT)
+GPIO(EC_KB_BL_EN_L,                  PIN(8, 6), GPIO_OUT_HIGH)
+GPIO(EC_PCHHOT_ODL,                  PIN(7, 4), GPIO_INPUT)
+GPIO(EC_PCH_INT_ODL,                 PIN(B, 0), GPIO_ODR_HIGH)
+GPIO(EC_PCH_PWR_BTN_ODL,             PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(EC_PCH_RSMRST_L,                PIN(A, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_RTCRST,                  PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_SYS_PWROK,               PIN(3, 7), GPIO_OUT_LOW)
+GPIO(EC_PCH_WAKE_R_ODL,              PIN(C, 0), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_ODL,                 PIN(6, 3), GPIO_ODR_HIGH)
+GPIO(EMMC_SKU_DET,                   PIN(7, 0), GPIO_INPUT)
+GPIO(EN_PP5000_FAN,                  PIN(6, 1), GPIO_OUT_LOW)
+GPIO(EN_PP5000_USBA_R,               PIN(D, 7), GPIO_OUT_LOW)
+GPIO(EN_S5_RAILS,                    PIN(B, 6), GPIO_OUT_LOW)
+GPIO(IMVP9_VRRDY_OD,                 PIN(4, 3), GPIO_INPUT)
+GPIO(PCH_PWROK,                      PIN(7, 2), GPIO_OUT_LOW)
+GPIO(SYS_RST_ODL,                    PIN(C, 5), GPIO_ODR_HIGH)
+GPIO(USB_C0_TCPC_RST_ODL,            PIN(A, 7), GPIO_ODR_LOW)
+GPIO(USB_C1_FRS_EN,                  PIN(9, 4), GPIO_OUT_LOW)
+GPIO(USB_C1_RT_INT_ODL,              PIN(A, 0), GPIO_INPUT)
+GPIO(USB_C1_RT_RST_R_ODL,            PIN(0, 2), GPIO_ODR_HIGH)
+GPIO(VCCST_PWRGD_OD,                 PIN(A, 4), GPIO_ODR_LOW)
+
+/* UART alternate functions */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)              /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */
+
+/* I2C alternate functions */
+ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)               /* GPIO33/I2C5_SCL0/CTS_L, GPIO36/RTS_L/I2C5_SDA0 */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)               /* GPIO87/I2C1_SDA0 */
+ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)               /* GPIO92/I2C2_SCL0, GPIO91/I2C2_SDA0, GPIO90/I2C1_SCL0 */
+ALTERNATE(PIN_MASK(B, 0x0c), 0, MODULE_I2C, 0)               /* GPIOB3/I2C7_SCL0/DCD_L, GPIOB2/I2C7_SDA0/DSR_L */
+ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, GPIO_SEL_1P8V)   /* GPIOB5/I2C0_SCL0, GPIOB4/I2C0_SDA0 */
+ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)               /* GPIOD1/I2C3_SCL0, GPIOD0/I2C3_SDA0 */
+ALTERNATE(PIN_MASK(E, 0x18), 0, MODULE_I2C, 0)               /* GPIOE4/I2C6_SCL1/I3C_SCL, GPIOE3/I2C6_SDA1/I3C_SDA */
+ALTERNATE(PIN_MASK(F, 0x0c), 0, MODULE_I2C, 0)               /* GPIOF3/I2C4_SCL1, GPIOF2/I2C4_SDA1 */
+
+/* PWM alternate functions */
+ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0)               /* GPIO40/TA1 */
+ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)               /* GPIO80/PWM3 */
+ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)               /* GPIOB7/PWM5 */
+
+/* ADC alternate functions */
+ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0)               /* GPIO34/PS2_DAT2/ADC6 */
+ALTERNATE(PIN_MASK(4, 0x34), 0, MODULE_ADC, 0)               /* GPIO42/ADC3/RI_L, GPIO45/ADC0, GPIO44/ADC1 */
+ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0)               /* GPIOE1/ADC7 */
+
+/* KB alternate functions */
+ALTERNATE(PIN_MASK(0, 0xf0), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO10&P80_CLK/GPIO07, KSO11&P80_DAT/GPIO06, KSO12/GPIO05, KSO13/GPIO04 */
+ALTERNATE(PIN_MASK(1, 0x7f), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO06/GPO13/GP_SEL_L, KSO07/GPO12/JEN_L, KSO03/GPIO16/JTAG_TDO0_SWO, KSO04/GPIO15/XNOR, KSO05/GPIO14, KSO08/GPIO11/CR_SOUT1, KSO09/GPIO10/CR_SIN1 */
+ALTERNATE(PIN_MASK(2, 0xfc), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI2/GPIO27/TRACEDATA1, KSI3/GPIO26/TRACEDATA0, KSI4/GPIO25/TRACECLK/GP_SCLK, KSI5/GPIO24/GP_MISO, KSI6/GPIO23/S_SBUB, KSI7/GPIO22/S_SBUA */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO00/GPIO21/JTAG_TCK_SWCLK, KSO01/GPIO20/JTAG_TMS_SWIO */
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI0/GPIO31/TRACEDATA3/GP_MOSI, KSI1/GPIO30/TRACEDATA2/GP_CS_L */
+ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO14/GPIO82 */
+
+/* PMU alternate functions */
+ALTERNATE(PIN_MASK(0, 0x01), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN2_L&GPI00/GPIO00 */
+ALTERNATE(PIN_MASK(0, 0x02), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW) /* GPIO01/PSL_IN3_L&GPI01 */
+ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN1_L&GPID2/GPIOD2 */
+
+/* Unused Pins */
+UNUSED(PIN(B, 1))       /* KSO17/GPIOB1/CR_SIN4 */
+UNUSED(PIN(D, 4))       /* GPIOD4/CR_SIN3 */
+UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
+UNUSED(PIN(3, 2))       /* GPO32/TRIS_L */
+UNUSED(PIN(3, 5))       /* GPO35/CR_SOUT4/TEST_L */
+UNUSED(PIN(4, 1))       /* GPIO41/ADC4 */
+UNUSED(PIN(6, 6))       /* GPIO66 */
+UNUSED(PIN(5, 7))       /* GPIO57/SER_IRQ/ESPI_ALERT_L */
+
+/* Pre-configured PSL balls:  J8  K6 */
+
+/*
+ * The NPCX keyboard driver does not use named GPIOs to access
+ * keyboard scan pins, so we do not list them in *gpio.inc. However, when
+ * KEYBOARD_COL2_INVERTED is defined, this name is required.
+ */
+GPIO(EC_KSO_02_INV,               PIN(1, 7), GPIO_OUT_LOW)
+
+/* GPIO02_P2 to PU */
+/* GPIO03_P2 to PU */
+IOEX(USB_C0_OC_ODL,          EXPIN(IOEX_C0_NCT38XX, 0, 4), GPIO_ODR_HIGH)
+IOEX(USB_C0_FRS_EN,          EXPIN(IOEX_C0_NCT38XX, 0, 6), GPIO_OUT_LOW)
+
+/* LED */
+GPIO(LED_1_L,	 PIN(C, 4), GPIO_OUT_HIGH)	/* Battery - Red LED */
+GPIO(LED_2_L,	 PIN(C, 3), GPIO_OUT_HIGH)	/* Battery - Green LED */
+GPIO(LED_3_L,	 PIN(C, 2), GPIO_OUT_HIGH)	/* Power - White LED */
diff --git a/board/taeko/i2c.c b/board/taeko/i2c.c
new file mode 100644
index 0000000000..498df4dd81
--- /dev/null
+++ b/board/taeko/i2c.c
@@ -0,0 +1,70 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "i2c.h"
+
+/* I2C port map configuration */
+const struct i2c_port_t i2c_ports[] = {
+	{
+		/* I2C0 */
+		.name = "sensor",
+		.port = I2C_PORT_SENSOR,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_SENSOR_SCL,
+		.sda = GPIO_EC_I2C_SENSOR_SDA,
+	},
+	{
+		/* I2C1 */
+		.name = "tcpc0",
+		.port = I2C_PORT_USB_C0_TCPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_TCPC_SDA,
+	},
+	{
+		/* I2C2 */
+		.name = "ppc0",
+		.port = I2C_PORT_USB_C0_PPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_PPC_BC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_PPC_BC_SDA,
+	},
+	{
+		/* I2C4 C1 TCPC */
+		.name = "tcpc1",
+		.port = I2C_PORT_USB_C1_TCPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C1_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C1_TCPC_SDA,
+		.flags = I2C_PORT_FLAG_DYNAMIC_SPEED,
+	},
+	{
+		/* I2C5 */
+		.name = "battery",
+		.port = I2C_PORT_BATTERY,
+		.kbps = 100,
+		.scl = GPIO_EC_I2C_BAT_SCL,
+		.sda = GPIO_EC_I2C_BAT_SDA,
+	},
+	{
+		/* I2C6 */
+		.name = "ppc1",
+		.port = I2C_PORT_USB_C1_PPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C1_MIX_SCL,
+		.sda = GPIO_EC_I2C_USB_C1_MIX_SDA,
+	},
+	{
+		/* I2C7 */
+		.name = "eeprom",
+		.port = I2C_PORT_EEPROM,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_MISC_SCL_R,
+		.sda = GPIO_EC_I2C_MISC_SDA_R,
+	},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/board/taeko/keyboard.c b/board/taeko/keyboard.c
new file mode 100644
index 0000000000..4a1b096668
--- /dev/null
+++ b/board/taeko/keyboard.c
@@ -0,0 +1,109 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "ec_commands.h"
+#include "fw_config.h"
+#include "keyboard_scan.h"
+#include "timer.h"
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/* Increase from 50 us, because KSO_02 passes through the H1. */
+	.output_settle_us = 80,
+	/* Other values should be the same as the default configuration. */
+	.debounce_down_us = 30 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x1c, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
+	},
+};
+
+static const struct ec_response_keybd_config taeko_kb = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+static const struct ec_response_keybd_config tarlo_kb = {
+	.num_top_row_keys = 11,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_MICMUTE,             /* T8 */
+		TK_VOL_MUTE,		/* T9 */
+		TK_VOL_DOWN,		/* T10 */
+		TK_VOL_UP,		/* T11 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY | KEYBD_CAP_NUMERIC_KEYPAD,
+};
+
+/*
+ * Row Column info for Top row keys T1 - T15.
+ * Since tarlo keyboard top row keys have some issue when press with search
+ * key together.
+ * Needs to add row and col setting for top row.
+ * Change T8 row, col to (0,1)
+ * Change T9 row, col to (1,5)
+ * Change T10 row, col to (3,5)
+ * Change T11 row, col to (0,9)
+ */
+__override struct key {
+	uint8_t row;
+	uint8_t col;
+} vivaldi_keys[] = {
+	{ .row = 0, .col = 2 }, /* T1 */
+	{ .row = 3, .col = 2 }, /* T2 */
+	{ .row = 2, .col = 2 }, /* T3 */
+	{ .row = 1, .col = 2 }, /* T4 */
+	{ .row = 3, .col = 4 }, /* T5 */
+	{ .row = 2, .col = 4 }, /* T6 */
+	{ .row = 1, .col = 4 }, /* T7 */
+	{ .row = 0, .col = 1 }, /* T8 */
+	{ .row = 1, .col = 5 }, /* T9 */
+	{ .row = 3, .col = 5 }, /* T10 */
+	{ .row = 0, .col = 9 }, /* T11 */
+	{ .row = 2, .col = 9 }, /* T12 */
+	{ .row = 1, .col = 9 }, /* T13 */
+	{ .row = 0, .col = 4 }, /* T14 */
+	{ .row = 0, .col = 11 }, /* T15 */
+};
+BUILD_ASSERT(ARRAY_SIZE(vivaldi_keys) == MAX_TOP_ROW_KEYS);
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	if (ec_cfg_has_keyboard_number_pad())
+		return &tarlo_kb;
+	else {
+		vivaldi_keys[7].row = 2; /* T8 */
+		vivaldi_keys[7].col = 9;
+		vivaldi_keys[8].row = 1; /* T9 */
+		vivaldi_keys[8].col = 9;
+		vivaldi_keys[9].row = 0; /* T10 */
+		vivaldi_keys[9].col = 4;
+		return &taeko_kb;
+	}
+}
diff --git a/board/taeko/led.c b/board/taeko/led.c
new file mode 100644
index 0000000000..1f8637cfe2
--- /dev/null
+++ b/board/taeko/led.c
@@ -0,0 +1,124 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Taeko specific PWM LED settings: there are 2 LEDs on each side of the board,
+ * each one can be controlled separately. The LED colors are white or amber,
+ * and the default behavior is tied to the charging process: both sides are
+ * amber while charging the battery and white when the battery is charged.
+ */
+
+#include "common.h"
+#include "gpio.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
+
+__override const int led_charge_lvl_1 = 5;
+
+__override const int led_charge_lvl_2 = 97;
+
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
+
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    1 * LED_ONE_SEC },
+						  { LED_OFF,
+						    3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_power(enum ec_led_colors color)
+{
+	if (color == EC_LED_COLOR_WHITE)
+		gpio_set_level(GPIO_LED_3_L, LED_ON_LVL);
+	else
+		/* LED_OFF and unsupported colors */
+		gpio_set_level(GPIO_LED_3_L, LED_OFF_LVL);
+}
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_AMBER:
+		gpio_set_level(GPIO_LED_1_L, LED_ON_LVL);
+		gpio_set_level(GPIO_LED_2_L, LED_ON_LVL);
+		break;
+	case EC_LED_COLOR_RED:
+		gpio_set_level(GPIO_LED_1_L, LED_ON_LVL);
+		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
+		break;
+	case EC_LED_COLOR_GREEN:
+		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_2_L, LED_ON_LVL);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_RED] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		brightness_range[EC_LED_COLOR_GREEN] = 1;
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		if (brightness[EC_LED_COLOR_RED] != 0)
+			led_set_color_battery(EC_LED_COLOR_RED);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(EC_LED_COLOR_AMBER);
+		else if (brightness[EC_LED_COLOR_GREEN] != 0)
+			led_set_color_battery(EC_LED_COLOR_GREEN);
+		else
+			led_set_color_battery(LED_OFF);
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_power(EC_LED_COLOR_WHITE);
+		else
+			led_set_color_power(LED_OFF);
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/board/taeko/pwm.c b/board/taeko/pwm.c
new file mode 100644
index 0000000000..521043b859
--- /dev/null
+++ b/board/taeko/pwm.c
@@ -0,0 +1,37 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "hooks.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_KBLIGHT] = {
+		.channel = 3,
+		.flags = 0,
+		/*
+		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
+		 * flicker. Higher frequencies consume similar average power to
+		 * lower PWM frequencies, but higher frequencies record a much
+		 * lower maximum power.
+		 */
+		.freq = 2400,
+	},
+	[PWM_CH_FAN] = {
+		.channel = 5,
+		.flags = PWM_CONFIG_OPEN_DRAIN,
+		.freq = 25000
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+static void board_pwm_init(void)
+{
+	pwm_enable(PWM_CH_KBLIGHT, 1);
+	pwm_set_duty(PWM_CH_KBLIGHT, 50);
+}
+DECLARE_HOOK(HOOK_INIT, board_pwm_init, HOOK_PRIO_DEFAULT);
diff --git a/board/taeko/sensors.c b/board/taeko/sensors.c
new file mode 100644
index 0000000000..ccda469b87
--- /dev/null
+++ b/board/taeko/sensors.c
@@ -0,0 +1,408 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "accelgyro.h"
+#include "adc_chip.h"
+#include "common.h"
+#include "driver/accel_bma422.h"
+#include "driver/accel_bma4xx.h"
+#include "driver/accel_lis2dw12.h"
+#include "driver/accelgyro_lsm6dsm.h"
+#include "driver/accelgyro_lsm6dso.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "motion_sense.h"
+#include "tablet_mode.h"
+#include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
+#include "thermal.h"
+
+#if 0
+#define CPRINTS(format, args...) ccprints(format, ##args)
+#define CPRINTF(format, args...) ccprintf(format, ##args)
+#else
+#define CPRINTS(format, args...)
+#define CPRINTF(format, args...)
+#endif
+
+/* ADC configuration */
+const struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_1_DDR_SOC] = {
+		.name = "TEMP_DDR_SOC",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_2_FAN] = {
+		.name = "TEMP_FAN",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_3_CHARGER] = {
+		.name = "TEMP_CHARGER",
+		.input_ch = NPCX_ADC_CH6,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_4_CPUCHOKE] = {
+		.name = "CPU_CHOKE",
+		.input_ch = NPCX_ADC_CH7,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+K_MUTEX_DEFINE(g_lid_accel_mutex);
+K_MUTEX_DEFINE(g_base_accel_mutex);
+static struct stprivate_data g_lis2dw12_data;
+static struct accelgyro_saved_data_t g_bma422_data;
+static struct lsm6dso_data lsm6dso_data;
+static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
+
+/* The matrix for new DB */
+static const mat33_fp_t lid_ref_for_new_DB = { { FLOAT_TO_FP(-1), 0, 0 },
+					       { 0, FLOAT_TO_FP(1), 0 },
+					       { 0, 0, FLOAT_TO_FP(-1) } };
+/* Matrix to rotate lid and base sensor into standard reference frame */
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					     { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
+
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, FLOAT_TO_FP(1), 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
+
+struct motion_sensor_t bma422_lid_accel = {
+	.name = "Lid Accel - BMA",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_BMA422,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_LID,
+	.drv = &bma4_accel_drv,
+	.mutex = &g_lid_accel_mutex,
+	.drv_data = &g_bma422_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = BMA4_I2C_ADDR_PRIMARY, /* 0x18 */
+	.rot_standard_ref = &lid_standard_ref, /* identity matrix */
+	.default_range = 2, /* g, enough for laptop. */
+	.min_frequency = BMA4_ACCEL_MIN_FREQ,
+	.max_frequency = BMA4_ACCEL_MAX_FREQ,
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 12500 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+		/* Sensor on in S3 */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 12500 | ROUND_UP_FLAG,
+			.ec_rate = 0,
+		},
+	},
+};
+
+struct motion_sensor_t lsm6dsm_base_accel = {
+	.name = "Base Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_LSM6DSM,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &lsm6dsm_drv,
+	.mutex = &g_base_accel_mutex,
+	.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
+			MOTIONSENSE_TYPE_ACCEL),
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
+	.rot_standard_ref = &base_standard_ref,
+	.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
+	.min_frequency = LSM6DSM_ODR_MIN_VAL,
+	.max_frequency = LSM6DSM_ODR_MAX_VAL,
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 13000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+		/* Sensor on for angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+	},
+};
+
+struct motion_sensor_t lsm6dsm_base_gyro = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_LSM6DSM,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &lsm6dsm_drv,
+	.mutex = &g_base_accel_mutex,
+	.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data, MOTIONSENSE_TYPE_GYRO),
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
+	.default_range = 1000 | ROUND_UP_FLAG, /* dps */
+	.rot_standard_ref = &base_standard_ref,
+	.min_frequency = LSM6DSM_ODR_MIN_VAL,
+	.max_frequency = LSM6DSM_ODR_MAX_VAL,
+};
+
+struct motion_sensor_t motion_sensors[] = {
+	[LID_ACCEL] = {
+		.name = "Lid Accel - ST",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LIS2DW12,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &lis2dw12_drv,
+		.mutex = &g_lid_accel_mutex,
+		.drv_data = &g_lis2dw12_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LIS2DW12_ADDR1, /* 0x19 */
+		.rot_standard_ref = &lid_standard_ref, /* identity matrix */
+		.default_range = 2, /* g */
+		.min_frequency = LIS2DW12_ODR_MIN_VAL,
+		.max_frequency = LIS2DW12_ODR_MAX_VAL,
+		.config = {
+			/* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 12500 | ROUND_UP_FLAG,
+			},
+			/* Sensor on for lid angle detection */
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+		},
+	},
+
+	[BASE_ACCEL] = {
+		.name = "Base Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LSM6DSO,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &lsm6dso_drv,
+		.mutex = &g_base_accel_mutex,
+		.drv_data = &lsm6dso_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LSM6DSO_ADDR0_FLAGS,
+		.rot_standard_ref = &base_standard_ref,
+		.default_range = 4,  /* g */
+		.min_frequency = LSM6DSO_ODR_MIN_VAL,
+		.max_frequency = LSM6DSO_ODR_MAX_VAL,
+		.config = {
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 13000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+		},
+	},
+
+	[BASE_GYRO] = {
+		.name = "Base Gyro",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LSM6DSO,
+		.type = MOTIONSENSE_TYPE_GYRO,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &lsm6dso_drv,
+		.mutex = &g_base_accel_mutex,
+		.drv_data = &lsm6dso_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LSM6DSO_ADDR0_FLAGS,
+		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = LSM6DSO_ODR_MIN_VAL,
+		.max_frequency = LSM6DSO_ODR_MAX_VAL,
+	},
+};
+
+unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+static void board_detect_motionsensor(void)
+{
+	int ret;
+	int val;
+
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return;
+
+	/*
+	 * b/194765820 - Dynamic motion sensor count
+	 * All board supports tablet mode if board id > 0
+	 */
+	if (get_board_id() == 0 && !ec_cfg_has_tabletmode())
+		return;
+
+	/* Check lid accel chip */
+	ret = i2c_read8(I2C_PORT_SENSOR, LIS2DW12_ADDR1, LIS2DW12_WHO_AM_I_REG,
+			&val);
+	if (ret == 0 && val == LIS2DW12_WHO_AM_I) {
+		CPRINTS("LID_ACCEL is LIS2DW12");
+		return;
+	}
+
+	ret = i2c_read8(I2C_PORT_SENSOR, BMA4_I2C_ADDR_PRIMARY,
+			BMA4_CHIP_ID_ADDR, &val);
+	if (ret == 0 && val == BMA422_CHIP_ID) {
+		CPRINTS("LID_ACCEL is BMA422");
+		motion_sensors[LID_ACCEL] = bma422_lid_accel;
+		/*
+		 * The driver for BMA422 doesn't have code to support
+		 * INT1. So, it doesn't need to enable interrupt.
+		 * Vendor recommend to configure EC gpio as high-z if
+		 * we don't use INT1. Keep this pin as input w/o enable
+		 * interrupt.
+		 */
+		if (get_board_id() >= 2) {
+			/* Need to change matrix when board ID >= 2 */
+			bma422_lid_accel.rot_standard_ref = &lid_ref_for_new_DB;
+		}
+		return;
+	}
+
+	/* Lid accel is not stuffed, don't allow line to float */
+	gpio_disable_interrupt(GPIO_EC_ACCEL_INT_R_L);
+	gpio_set_flags(GPIO_EC_ACCEL_INT_R_L, GPIO_INPUT | GPIO_PULL_DOWN);
+	CPRINTS("No LID_ACCEL are detected");
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_detect_motionsensor,
+	     HOOK_PRIO_DEFAULT);
+
+static void baseboard_sensors_init(void)
+{
+	CPRINTS("baseboard_sensors_init");
+	/* b/194765820
+	 * Dynamic motion sensor count
+	 * All board supports tablet mode if board id > 0
+	 */
+	if (ec_cfg_has_tabletmode()) {
+		/* Change Request (b/199529373)
+		 * GYRO sensor change from ST LSM6DSOETR3TR to ST LSM6DS3TR-C
+		 *	LSM6DSOETR3TR base accel/gyro if board id = 0
+		 *	LSM6DS3TR-C Base accel/gyro if board id > 0
+		 */
+		if (get_board_id() > 0) {
+			motion_sensors[BASE_ACCEL] = lsm6dsm_base_accel;
+			motion_sensors[BASE_GYRO] = lsm6dsm_base_gyro;
+		}
+
+		if (get_board_id() >= 2) {
+			/* Need to change matrix when board ID >= 2 */
+			motion_sensors[LID_ACCEL].rot_standard_ref =
+				&lid_ref_for_new_DB;
+		}
+
+		/* Enable gpio interrupt for base accelgyro sensor */
+		gpio_enable_interrupt(GPIO_EC_IMU_INT_R_L);
+	} else {
+		CPRINTS("Clamshell");
+		motion_sensor_count = 0;
+		gmr_tablet_switch_disable();
+		gpio_set_flags(GPIO_TABLET_MODE_L, GPIO_INPUT | GPIO_PULL_DOWN);
+		/* Gyro is not present, don't allow line to float */
+		gpio_set_flags(GPIO_EC_IMU_INT_R_L,
+			       GPIO_INPUT | GPIO_PULL_DOWN);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_INIT_I2C + 1);
+
+/* Temperature sensor configuration */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1_DDR_SOC] = { .name = "DDR and SOC",
+				    .type = TEMP_SENSOR_TYPE_BOARD,
+				    .read = get_temp_3v3_30k9_47k_4050b,
+				    .idx = ADC_TEMP_SENSOR_1_DDR_SOC },
+	[TEMP_SENSOR_2_FAN] = { .name = "FAN",
+				.type = TEMP_SENSOR_TYPE_BOARD,
+				.read = get_temp_3v3_30k9_47k_4050b,
+				.idx = ADC_TEMP_SENSOR_2_FAN },
+	[TEMP_SENSOR_3_CHARGER] = { .name = "CHARGER",
+				    .type = TEMP_SENSOR_TYPE_BOARD,
+				    .read = get_temp_3v3_30k9_47k_4050b,
+				    .idx = ADC_TEMP_SENSOR_3_CHARGER },
+	[TEMP_SENSOR_4_CPUCHOKE] = { .name = "CPU CHOKE",
+				     .type = TEMP_SENSOR_TYPE_BOARD,
+				     .read = get_temp_3v3_30k9_47k_4050b,
+				     .idx = ADC_TEMP_SENSOR_4_CPUCHOKE },
+};
+
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/*
+ * TODO(b/201021109): update for Alder Lake/brya
+ *
+ * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
+ * 130 C.  However, sensor is located next to DDR, so we need to use the lower
+ * DDR temperature limit (100 C)
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(90), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(100), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(85), \
+		}, \
+		.temp_fan_off = C_TO_K(35), \
+		.temp_fan_max = C_TO_K(70), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
+
+/*
+ * TODO(b/201021109): update for Alder Lake/brya
+ *
+ * Inductor limits - used for both charger and PP3300 regulator
+ *
+ * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
+ *
+ * Charger max recommended temperature 100C, max absolute temperature 125C
+ * PP3300 regulator: operating range -40 C to 145 C
+ *
+ * Inductors: limit of 125c
+ * PCB: limit is 100c
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_FAN              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(90), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(100), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(85), \
+		}, \
+		.temp_fan_off = C_TO_K(35), \
+		.temp_fan_max = C_TO_K(70), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_fan = THERMAL_FAN;
+
+/* this should really be "const" */
+struct ec_thermal_config thermal_params[] = {
+	[TEMP_SENSOR_1_DDR_SOC] = THERMAL_CPU,
+	[TEMP_SENSOR_2_FAN] = THERMAL_FAN,
+	[TEMP_SENSOR_3_CHARGER] = THERMAL_FAN,
+	[TEMP_SENSOR_4_CPUCHOKE] = THERMAL_FAN,
+};
+
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
diff --git a/board/taeko/usbc_config.c b/board/taeko/usbc_config.c
new file mode 100644
index 0000000000..0c58ca5ff4
--- /dev/null
+++ b/board/taeko/usbc_config.c
@@ -0,0 +1,400 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/bc12/pi3usb9201_public.h"
+#include "driver/ppc/nx20p348x.h"
+#include "driver/ppc/syv682x_public.h"
+#include "driver/retimer/bb_retimer_public.h"
+#include "driver/tcpm/nct38xx.h"
+#include "driver/tcpm/ps8xxx_public.h"
+#include "driver/tcpm/tcpci.h"
+#include "ec_commands.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "ioexpander.h"
+#include "system.h"
+#include "task.h"
+#include "task_id.h"
+#include "timer.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+#if 0
+/* Debug only! */
+#define CPRINTSUSB(format, args...) cprints(CC_USBPD, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBPD, format, ##args)
+#else
+#define CPRINTSUSB(format, args...)
+#define CPRINTFUSB(format, args...)
+#endif
+
+/* USBC TCPC configuration */
+const struct tcpc_config_t tcpc_config[] = {
+	[USBC_PORT_C0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0_TCPC,
+			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+	},
+	[USBC_PORT_C1] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C1_TCPC,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
+			 TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V |
+			 TCPC_FLAGS_CONTROL_VCONN |
+			 TCPC_FLAGS_CONTROL_FRS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
+BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
+
+/* USBC PPC configuration */
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_PPC,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.frs_en = IOEX_USB_C0_FRS_EN,
+		.drv = &syv682x_drv,
+	},
+	[USBC_PORT_C1] = {
+		/* Compatible with Silicon Mitus SM536A0 */
+		.i2c_port = I2C_PORT_USB_C1_PPC,
+		.i2c_addr_flags = NX20P3483_ADDR2_FLAGS,
+		.drv = &nx20p348x_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
+
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/* USBC mux configuration - Alder Lake includes internal mux */
+
+/*
+ * USB3 DB mux configuration - the top level mux still needs to be set
+ * to the virtual_usb_mux_driver so the AP gets notified of mux changes
+ * and updates the TCSS configuration on state changes.
+ */
+static const struct usb_mux_chain usbc1_usb3_db_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
+};
+
+const struct usb_mux_chain usb_muxes[] = {
+	[USBC_PORT_C0] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+	},
+	[USBC_PORT_C1] = {
+		.mux = &(const struct usb_mux) {
+			/* PS8815 DB */
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc1_usb3_db_retimer,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
+
+/* BC1.2 charger detect configuration */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C1_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
+
+/*
+ * USB C0 and C2 uses burnside bridge chips and have their reset
+ * controlled by their respective TCPC chips acting as GPIO expanders.
+ *
+ * ioex_init() is normally called before we take the TCPCs out of
+ * reset, so we need to start in disabled mode, then explicitly
+ * call ioex_init().
+ */
+
+struct ioexpander_config_t ioex_config[] = {
+	[IOEX_C0_NCT38XX] = {
+		.i2c_host_port = I2C_PORT_USB_C0_TCPC,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT);
+
+void config_usb_db_type(void)
+{
+	enum ec_cfg_usb_db_type db_type = ec_cfg_usb_db_type();
+
+	/*
+	 * TODO(b/194515356): implement multiple DB types
+	 */
+	CPRINTS("Configured USB DB type number is %d", db_type);
+}
+
+static void ps8815_reset(void)
+{
+	int val;
+
+	CPRINTS("%s: patching ps8815 registers", __func__);
+
+	if (i2c_read8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_FLAGS, 0x0f,
+		      &val) == EC_SUCCESS)
+		CPRINTS("ps8815: reg 0x0f was %02x", val);
+	else {
+		CPRINTS("delay 10ms to make sure PS8815 is waken from idle");
+		msleep(10);
+	}
+
+	if (i2c_write8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_FLAGS, 0x0f,
+		       0x31) == EC_SUCCESS)
+		CPRINTS("ps8815: reg 0x0f set to 0x31");
+
+	if (i2c_read8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_FLAGS, 0x0f,
+		      &val) == EC_SUCCESS)
+		CPRINTS("ps8815: reg 0x0f now %02x", val);
+}
+
+/**
+ * b/197585292
+ * It's used for early board to check if usb_db is plugged or not.
+ * That's used to avoid TCPC1 initialization abnormal if db isn't
+ * plugged into system.
+ */
+enum usb_db_present {
+	DB_USB_NOT_PRESENT = 0,
+	DB_USB_PRESENT = 1,
+};
+static enum usb_db_present db_usb_hw_pres;
+
+/**
+ * Init hw ps8815 detection and keep it in db_usb_hw_press.
+ * Then, we don't need to keep query ps8815 mcu.
+ */
+static void board_init_ps8815_detection(void)
+{
+	int rv, val;
+
+	CPRINTSUSB("%s", __func__);
+
+	rv = i2c_read8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_FLAGS, 0x00,
+		       &val);
+
+	db_usb_hw_pres = (rv == EC_SUCCESS) ? DB_USB_PRESENT :
+					      DB_USB_NOT_PRESENT;
+
+	if (db_usb_hw_pres == DB_USB_NOT_PRESENT)
+		CPRINTS("DB isn't plugged or something went wrong!");
+}
+
+/**
+ * @return true if ps8815_db is plugged, false if it isn't plugged.
+ */
+static bool board_detect_ps8815_db(void)
+{
+	CPRINTSUSB("%s", __func__);
+
+	/* All dut should plug ps8815 db if board id > 0 */
+	if (get_board_id() > 0)
+		return true;
+
+	if (ec_cfg_usb_db_type() == DB_USB3_PS8815 &&
+	    db_usb_hw_pres == DB_USB_PRESENT)
+		return true;
+
+	CPRINTSUSB("No PS8815 DB");
+	return false;
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * TODO(b/194618663): figure out correct timing
+	 */
+
+	gpio_set_level(GPIO_USB_C0_TCPC_RST_ODL, 0);
+
+	/*
+	 * (b/202489681): Nx20p3483 cannot sink power after reset ec
+	 * To avoid nx20p3483 cannot sink power after reset ec w/ AC
+	 * only in TCPC1 port, EC shouldn't assert GPIO_USB_C1_RT_RST_R_ODL
+	 * if no battery.
+	 */
+	if (battery_hw_present())
+		gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 0);
+
+	/*
+	 * delay for power-on to reset-off and min. assertion time
+	 */
+	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS));
+
+	gpio_set_level(GPIO_USB_C0_TCPC_RST_ODL, 1);
+	gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 1);
+
+	/* wait for chips to come up */
+	msleep(PS8815_FW_INIT_DELAY_MS);
+	ps8815_reset();
+
+	/*
+	 * board_init_ps8815_detection should be called before
+	 * board_get_usb_pd_port_count(). usb_mux_hpd_update can check
+	 * pd port count.
+	 */
+	board_init_ps8815_detection();
+	usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+}
+
+static void board_tcpc_init(void)
+{
+	CPRINTSUSB("%s: board id = %d", __func__, get_board_id());
+
+	/* Don't reset TCPCs after initial reset */
+	if (!system_jumped_late()) {
+		board_reset_pd_mcu();
+
+		/*
+		 * These IO expander pins are implemented using the
+		 * C0/C2 TCPC, so they must be set up after the TCPC has
+		 * been taken out of reset.
+		 */
+		ioex_init(0);
+	}
+
+	CPRINTSUSB("Enable GPIO INT");
+
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
+	if (board_detect_ps8815_db())
+		gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
+	if (board_detect_ps8815_db())
+		gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
+
+	/* Enable BC1.2 interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
+	if (board_detect_ps8815_db())
+		gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_0;
+
+	if (gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
+
+int ppc_get_alert_status(int port)
+{
+	if (port == USBC_PORT_C0)
+		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
+
+	if (port == USBC_PORT_C1)
+		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
+
+	return 0;
+}
+
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C1);
+		break;
+	default:
+		break;
+	}
+}
+
+void bc12_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_BC12_INT_ODL:
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+		break;
+	case GPIO_USB_C1_BC12_INT_ODL:
+		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+		break;
+	default:
+		break;
+	}
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_PPC_INT_ODL:
+		nx20p348x_interrupt(USBC_PORT_C1);
+		break;
+	default:
+		break;
+	}
+}
+
+__override bool board_is_dts_port(int port)
+{
+	return port == USBC_PORT_C0;
+}
+
+__override uint8_t board_get_usb_pd_port_count(void)
+{
+	CPRINTSUSB("%s is called by task_id:%d", __func__, task_get_current());
+
+	if (board_detect_ps8815_db())
+		return CONFIG_USB_PD_PORT_MAX_COUNT;
+
+	return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
+}
diff --git a/board/taeko/usbc_config.h b/board/taeko/usbc_config.h
new file mode 100644
index 0000000000..9a35b4880f
--- /dev/null
+++ b/board/taeko/usbc_config.h
@@ -0,0 +1,17 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Taeko board-specific USB-C configuration */
+
+#ifndef __CROS_EC_USBC_CONFIG_H
+#define __CROS_EC_USBC_CONFIG_H
+
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
+
+void config_usb_db_type(void);
+
+#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/taeko/vif_override.xml b/board/taeko/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/taeko/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/taniks/battery.c b/board/taniks/battery.c
new file mode 100644
index 0000000000..013c27602c
--- /dev/null
+++ b/board/taniks/battery.c
@@ -0,0 +1,132 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery.h"
+#include "battery_fuel_gauge.h"
+#include "battery_smart.h"
+#include "common.h"
+#include "util.h"
+/*
+ * Battery info for all Taniks battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	[BATTERY_SMP_51W] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP",
+			.device_name = "L21M4PG4",
+			.ship_mode = {
+				.reg_addr = 0x34,
+				.reg_data = { 0x0000, 0x1000 },
+			},
+			.fet = {
+				.reg_addr = 0x00,
+				.reg_mask = 0x0018,
+				.disconnect_val = 0x0000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 8900, /* mV */
+			.voltage_normal		= 7680, /* mV */
+			.voltage_min		= 6000, /* mV */
+			.precharge_current	= 464,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 60,
+		},
+	},
+	[BATTERY_SMP_71W] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP",
+			.device_name = "L21M4PG5",
+			.ship_mode = {
+				.reg_addr = 0x34,
+				.reg_data = { 0x0000, 0x1000 },
+			},
+			.fet = {
+				.reg_addr = 0x00,
+				.reg_mask = 0x0018,
+				.disconnect_val = 0x0000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 8800, /* mV */
+			.voltage_normal		= 7680, /* mV */
+			.voltage_min		= 6000, /* mV */
+			.precharge_current	= 464,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 60,
+		},
+	},
+	[BATTERY_LGC] = {
+		.fuel_gauge = {
+			.manuf_name = "LGES",
+			.device_name = "L21L4PG5",
+			.ship_mode = {
+				.reg_addr = 0x34,
+				.reg_data = { 0x0000, 0x1000 },
+			},
+			.fet = {
+				.reg_addr = 0x00,
+				.reg_mask = 0x0018,
+				.disconnect_val = 0x0000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 8800, /* mV */
+			.voltage_normal		= 7680, /* mV */
+			.voltage_min		= 6000, /* mV */
+			.precharge_current	= 512,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 60,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SMP_51W;
+
+__override bool board_battery_is_initialized(void)
+{
+	bool batt_initialization_state;
+	int batt_status;
+
+	batt_initialization_state =
+		(battery_status(&batt_status) ?
+			 false :
+			 !!(batt_status & STATUS_INITIALIZED));
+	return batt_initialization_state;
+}
diff --git a/board/taniks/board.c b/board/taniks/board.c
new file mode 100644
index 0000000000..fdda313c9e
--- /dev/null
+++ b/board/taniks/board.c
@@ -0,0 +1,117 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "button.h"
+#include "charge_manager.h"
+#include "charge_ramp.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/accel_lis2dw12.h"
+#include "driver/accelgyro_lsm6dso.h"
+#include "driver/als_tcs3400.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "keyboard_raw.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "registers.h"
+#include "rgb_keyboard.h"
+#include "switch.h"
+#include "tablet_mode.h"
+#include "throttle_ap.h"
+#include "usbc_config.h"
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* Console output macros */
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+
+/******************************************************************************/
+/* USB-A charging control */
+
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_PP5000_USBA_R,
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
+
+/******************************************************************************/
+
+const struct rgbkbd_init rgbkbd_init_taniks = {
+	.gcc = RGBKBD_MAX_GCC_LEVEL / 2,
+	.scale = { .r = 190, .g = 255, .b = 255 },
+	.color = { .r = 255, .g = 255, .b = 255 },
+};
+
+__override void board_cbi_init(void)
+{
+	config_usb_db_type();
+}
+
+void board_init(void)
+{
+	rgbkbd_register_init_setting(&rgbkbd_init_taniks);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+__override void board_kblight_shutdown(void)
+{
+	gpio_set_level(GPIO_EC_KB_BL_EN_L, 1);
+}
+
+__override void board_kblight_init(void)
+{
+	gpio_set_level(GPIO_RGBKBD_SDB_L, 1);
+	gpio_set_level(GPIO_EC_KB_BL_EN_L, 0);
+	msleep(10);
+}
+
+#ifdef CONFIG_CHARGE_RAMP_SW
+
+/*
+ * TODO: tune this threshold
+ */
+
+#define BC12_MIN_VOLTAGE 4400
+
+/**
+ * Return true if VBUS is too low
+ */
+int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
+{
+	int voltage;
+
+	if (charger_get_vbus_voltage(port, &voltage))
+		voltage = 0;
+
+	if (voltage == 0) {
+		CPRINTS("%s: must be disconnected", __func__);
+		return 1;
+	}
+
+	if (voltage < BC12_MIN_VOLTAGE) {
+		CPRINTS("%s: port %d: vbus %d lower than %d", __func__, port,
+			voltage, BC12_MIN_VOLTAGE);
+		return 1;
+	}
+
+	return 0;
+}
+
+#endif /* CONFIG_CHARGE_RAMP_SW */
+
+enum battery_present battery_hw_present(void)
+{
+	/* The GPIO is low when the battery is physically present */
+	return gpio_get_level(GPIO_EC_BATT_PRES_ODL) ? BP_NO : BP_YES;
+}
diff --git a/board/taniks/board.h b/board/taniks/board.h
new file mode 100644
index 0000000000..1c874d6b83
--- /dev/null
+++ b/board/taniks/board.h
@@ -0,0 +1,303 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Taniks board configuration */
+#define CONFIG_BUTTONS_RUNTIME_CONFIG
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "compile_time_macros.h"
+
+/*
+ * Taniks boards are set up for vivaldi
+ */
+#define CONFIG_KEYBOARD_VIVALDI
+#undef CONFIG_VOLUME_BUTTONS
+#define NPCX_SELECT_KSI_TO_GPIO
+#define CONFIG_KEYBOARD_REFRESH_ROW3
+#define CONFIG_KEYBOARD_SCAN_ADC
+
+/* Baseboard features */
+#include "baseboard.h"
+
+#undef CONFIG_CMD_POWERINDEBUG
+#undef CONFIG_MKBP_INPUT_DEVICES
+#undef CONFIG_TABLET_MODE
+#undef CONFIG_GMR_TABLET_MODE
+#undef CONFIG_TABLET_MODE_SWITCH
+#undef CONFIG_VOLUME_BUTTONS
+
+/*
+ * This will happen automatically on NPCX9 ES2 and later. Do not remove
+ * until we can confirm all earlier chips are out of service.
+ */
+#define CONFIG_HIBERNATE_PSL_VCC1_RST_WAKEUP
+
+/* OEM requested 5% charger margin */
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 5
+
+/* LED */
+#define CONFIG_LED_ONOFF_STATES
+
+/* Sensors */
+#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
+
+/* Change Request (b/211078551)
+ * GYRO sensor change from ST LSM6DSOETR3TR to ST LSM6DS3TR-C
+ *	LSM6DSOETR3TR base accel/gyro if board id = 0
+ *	LSM6DS3TR-C Base accel/gyro if board id > 0
+ */
+#define CONFIG_ACCELGYRO_LSM6DSO /* Base accel */
+#define CONFIG_ACCEL_LSM6DSO_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+#define CONFIG_ACCELGYRO_LSM6DSM
+#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+/* Enable sensor fifo, must also define the _SIZE and _THRES */
+#define CONFIG_ACCEL_FIFO
+/* FIFO size is in power of 2. */
+#define CONFIG_ACCEL_FIFO_SIZE 256
+/* Depends on how fast the AP boots and typical ODRs */
+#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
+
+/* Sensors without hardware FIFO are in forced mode */
+#define CONFIG_ACCEL_FORCE_MODE_MASK (BIT(LID_ACCEL))
+
+/* Lid accel */
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_UPDATE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+#define CONFIG_ACCEL_BMA4XX
+#define CONFIG_ACCEL_LIS2DWL
+
+/* Sensor console commands */
+#define CONFIG_CMD_ACCELS
+#define CONFIG_CMD_ACCEL_INFO
+
+/* USB Type A Features */
+#define USB_PORT_COUNT 1
+#define CONFIG_USB_PORT_POWER_DUMB
+
+#define CONFIG_IO_EXPANDER
+#define CONFIG_IO_EXPANDER_NCT38XX
+#define CONFIG_IO_EXPANDER_PORT_COUNT 1
+
+/* USB Type C and USB PD defines */
+#define CONFIG_USB_PD_TCPM_PS8815
+#define CONFIG_USB_PD_TCPM_PS8815_FORCE_DID
+#define CONFIG_USBC_PPC_SYV682X
+#define CONFIG_USBC_PPC_NX20P3483
+#define CONFIG_USBC_NX20P348X_RCP_5VSRC_MASK_ENABLE
+
+#define CONFIG_USB_PD_FRS_PPC
+#define CONFIG_USB_PD_FRS
+
+/* I2C speed console command */
+#define CONFIG_CMD_I2C_SPEED
+
+/* I2C control host command */
+#define CONFIG_HOSTCMD_I2C_CONTROL
+
+/* TODO: b/177608416 - measure and check these values on brya */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
+
+/*
+ * Passive USB-C cables only support up to 60W.
+ */
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 45000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
+
+/* The lower the input voltage, the higher the power efficiency. */
+#define PD_PREFER_LOW_VOLTAGE
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KSI_00 GPIO_EC_KSI_00
+#define GPIO_KSI_01 GPIO_EC_KSI_01
+#define GPIO_KSI_02 GPIO_EC_KSI_02
+#define GPIO_KSI_03 GPIO_EC_KSI_03
+#define GPIO_KSI_04 GPIO_EC_KSI_04
+#define GPIO_KSI_05 GPIO_EC_KSI_05
+#define GPIO_KSI_06 GPIO_EC_KSI_06
+#define GPIO_KSI_07 GPIO_EC_KSI_07
+#define GPIO_KSO_00 GPIO_EC_KSO_00
+#define GPIO_KSO_01 GPIO_EC_KSO_01
+#define GPIO_KSO_02 GPIO_EC_KSO_02_R
+#define GPIO_KSO_03 GPIO_EC_KSO_03
+#define GPIO_KSO_04 GPIO_EC_KSO_04
+#define GPIO_KSO_05 GPIO_EC_KSO_05
+#define GPIO_KSO_06 GPIO_EC_KSO_06_R
+#define GPIO_KSO_07 GPIO_EC_KSO_07_R
+#define GPIO_KSO_08 GPIO_EC_KSO_08
+#define GPIO_KSO_09 GPIO_EC_KSO_09
+#define GPIO_KSO_10 GPIO_EC_KSO_10
+#define GPIO_KSO_11 GPIO_EC_KSO_11
+#define GPIO_KSO_12 GPIO_EC_KSO_12
+#define GPIO_KSO_13 GPIO_EC_KSO_13
+#define GPIO_KSO_14 GPIO_EC_KSO_14
+#define GPIO_RFR_KEY_L GPIO_EC_RFR_KEY_ODL_R
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+
+/*
+ * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
+ * signal.
+ */
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
+
+/* System has back-lit keyboard */
+#define CONFIG_PWM
+#define CONFIG_KEYBOARD_BACKLIGHT
+
+/* I2C Bus Configuration */
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0_TCPC NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1
+#define I2C_PORT_USB_C0_PPC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C0_BC12 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0
+#define I2C_PORT_KBMCU NPCX_I2C_PORT3_0
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+
+#define I2C_ADDR_MP2964_FLAGS 0x20
+
+/* Thermal features */
+#define CONFIG_THERMISTOR
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_SEQ_EC_DSW_PWROK
+#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
+
+/* Fan */
+#define CONFIG_FANS FAN_CH_COUNT
+
+/* Charger defines */
+#define CONFIG_CHARGER_BQ25720
+#define CONFIG_CHARGER_BQ25720_VSYS_TH2_CUSTOM
+/* 37h BIT7:2 VSYS_TH2 6.0V */
+#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV 60
+#define CONFIG_CHARGE_RAMP_SW
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10
+/* 30h BIT13:12 Enable PSYS 00b */
+#define CONFIG_CHARGER_BQ25710_PSYS_SENSING
+/* 30h BIT7 1.2V enable*/
+#define CONFIG_CHARGER_BQ25710_CMP_REF_1P2
+/* 30h BIT6 external hysteresis */
+#define CONFIG_CHARGER_BQ25710_CMP_POL_EXTERNAL
+/* 31h BIT3 = 1 Enable ACOC */
+#define CONFIG_CHARGER_BQ25710_EN_ACOC
+/* 33h BIT15:11 ILIM2 TH 140% */
+#define CONFIG_CHARGER_BQ257X0_ILIM2_VTH_CUSTOM
+#define CONFIG_CHARGER_BQ257X0_ILIM2_VTH \
+	BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH__1P40
+/* 34h BIT0 CONFIG_CHARGER_BQ25710_PP_ACOK */
+#define CONFIG_CHARGER_BQ25710_PP_ACOK
+/* 34h BIT3 and BIT15:10 IDCHG 9728mA, step is 512mA */
+#define CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA 9728
+/* 34h BIT6 CONFIG_CHARGER_BQ25710_PP_COMP */
+#define CONFIG_CHARGER_BQ25710_PP_COMP
+/* 36h UVP 5600mV */
+#define CONFIG_CHARGER_BQ25720_VSYS_UVP_CUSTOM
+#define CONFIG_CHARGER_BQ25720_VSYS_UVP BQ25720_CHARGE_OPTION_4_VSYS_UVP__5P6
+/* 3Eh BIT15:8 VSYS_MIN 6.1V */
+#define CONFIG_CHARGER_BQ25710_VSYS_MIN_VOLTAGE_CUSTOM
+#define CONFIG_CHARGER_BQ25710_VSYS_MIN_VOLTAGE_MV 6100
+
+/* RGB Keyboard */
+#define GPIO_RGBKBD_SDB_L GPIO_KBMCU_INT_ODL
+
+#define CONFIG_RGB_KEYBOARD
+#define CONFIG_LED_DRIVER_AW20198 /* Awinic AW20198 on I2C */
+
+#define RGB_GRID0_COL 8
+#define RGB_GRID0_ROW 6
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h" /* needed by registers.h */
+#include "registers.h"
+#include "usbc_config.h"
+
+enum adc_channel {
+	ADC_TEMP_SENSOR_1_DDR_SOC,
+	ADC_TEMP_SENSOR_3_CHARGER,
+	ADC_TEMP_SENSOR_4_CPUCHOKE,
+	ADC_KSI_00,
+	ADC_KSI_01,
+	ADC_KSI_02,
+	ADC_KSI_03,
+	ADC_KSI_04,
+	ADC_KSI_05,
+	ADC_KSI_06,
+	ADC_KSI_07,
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1_DDR_SOC,
+	TEMP_SENSOR_3_CHARGER,
+	TEMP_SENSOR_4_CPUCHOKE,
+	TEMP_SENSOR_COUNT
+};
+
+enum sensor_id { LID_ACCEL = 0, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
+
+enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_PORT_COUNT };
+
+enum battery_type {
+	BATTERY_SMP_51W,
+	BATTERY_SMP_71W,
+	BATTERY_LGC,
+	BATTERY_TYPE_COUNT,
+};
+
+enum pwm_channel {
+	PWM_CH_FAN, /* PWM5 */
+	PWM_CH_COUNT
+};
+
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT };
+
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT };
+
+void motion_interrupt(enum gpio_signal signal);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/taniks/build.mk b/board/taniks/build.mk
new file mode 100644
index 0000000000..7d01cfff96
--- /dev/null
+++ b/board/taniks/build.mk
@@ -0,0 +1,25 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Taniks board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx9
+CHIP_VARIANT:=npcx9m3f
+BASEBOARD:=brya
+
+board-y=
+board-y+=battery.o
+board-y+=board.o
+board-y+=charger.o
+board-y+=fans.o
+board-y+=fw_config.o
+board-y+=i2c.o
+board-y+=keyboard.o
+board-y+=led.o
+board-y+=pwm.o
+board-y+=sensors.o
+board-y+=usbc_config.o
diff --git a/board/taniks/charger.c b/board/taniks/charger.c
new file mode 100644
index 0000000000..827152e115
--- /dev/null
+++ b/board/taniks/charger.c
@@ -0,0 +1,82 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/charger/bq25710.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+#ifndef CONFIG_ZEPHYR
+/* Charger Chip Configuration */
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = BQ25710_SMBUS_ADDR1_FLAGS,
+		.drv = &bq25710_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CHARGER_NUM);
+#endif
+
+int board_set_active_charge_port(int port)
+{
+	int is_valid_port = board_is_usb_pd_port_present(port);
+	int i;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTSUSB("Disabling all charger ports");
+
+		/* Disable all ports. */
+		for (i = 0; i < ppc_cnt; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (ppc_vbus_sink_enable(i, 0))
+				CPRINTSUSB("Disabling C%d as sink failed.", i);
+		}
+
+		return EC_SUCCESS;
+	} else if (!is_valid_port) {
+		return EC_ERROR_INVAL;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (ppc_is_sourcing_vbus(port)) {
+		CPRINTFUSB("Skip enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTSUSB("New charge port: C%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < ppc_cnt; i++) {
+		if (i == port)
+			continue;
+
+		if (ppc_vbus_sink_enable(i, 0))
+			CPRINTSUSB("C%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTSUSB("C%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/board/taniks/ec.tasklist b/board/taniks/ec.tasklist
new file mode 100644
index 0000000000..c879d3f77c
--- /dev/null
+++ b/board/taniks/ec.tasklist
@@ -0,0 +1,31 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ *
+ * USB_CHG_Px tasks must be contiguous (see USB_CHG_PORT_TO_TASK_ID(x)).
+ * PD_Cx tasks must be contiguous (see PD_PORT_TO_TASK_ID(x))
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, HOOKS_TASK_STACK_SIZE) \
+	TASK_ALWAYS(RGBKBD, rgbkbd_task, NULL, BASEBOARD_RGBKBD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, BASEBOARD_CHG_RAMP_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, BASEBOARD_CHARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, BASEBOARD_CHIPSET_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, CONSOLE_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, BASEBOARD_POWERBTN_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, BASEBOARD_PD_INT_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, BASEBOARD_PD_INT_TASK_STACK_SIZE)
diff --git a/board/taniks/fans.c b/board/taniks/fans.c
new file mode 100644
index 0000000000..ddb79803d1
--- /dev/null
+++ b/board/taniks/fans.c
@@ -0,0 +1,88 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Physical fans. These are logically separate from pwm_channels. */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "fan.h"
+#include "fan_chip.h"
+#include "hooks.h"
+#include "pwm.h"
+
+/* MFT channels. These are logically separate from pwm_channels. */
+const struct mft_t mft_channels[] = {
+	[MFT_CH_0] = {
+		.module = NPCX_MFT_MODULE_1,
+		.clk_src = TCKC_LFCLK,
+		.pwm_id = PWM_CH_FAN,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
+
+static const struct fan_conf fan_conf_0 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
+	.pgood_gpio = -1,
+	.enable_gpio = GPIO_EN_PP5000_FAN,
+};
+
+/*
+ * TODO(b/211076077): need to update for real fan
+ *
+ * Prototype fan spins at about 7200 RPM at 100% PWM.
+ * Set minimum at around 30% PWM.
+ */
+static const struct fan_rpm fan_rpm_0 = {
+	.rpm_min = 2200,
+	.rpm_start = 2200,
+	.rpm_max = 7200,
+};
+
+const struct fan_t fans[FAN_CH_COUNT] = {
+	[FAN_CH_0] = {
+		.conf = &fan_conf_0,
+		.rpm = &fan_rpm_0,
+	},
+};
+
+#ifndef CONFIG_FANS
+
+/*
+ * TODO(b/211076077): use static fan speeds until fan and sensors are
+ * tuned. for now, use:
+ *
+ *   AP off:  33%
+ *   AP  on: 100%
+ */
+
+static void fan_slow(void)
+{
+	const int duty_pct = 33;
+
+	ccprints("%s: speed %d%%", __func__, duty_pct);
+
+	pwm_enable(PWM_CH_FAN, 1);
+	pwm_set_duty(PWM_CH_FAN, duty_pct);
+}
+
+static void fan_max(void)
+{
+	const int duty_pct = 100;
+
+	ccprints("%s: speed %d%%", __func__, duty_pct);
+
+	pwm_enable(PWM_CH_FAN, 1);
+	pwm_set_duty(PWM_CH_FAN, duty_pct);
+}
+
+DECLARE_HOOK(HOOK_INIT, fan_slow, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, fan_slow, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, fan_slow, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_RESET, fan_max, HOOK_PRIO_FIRST);
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, fan_max, HOOK_PRIO_DEFAULT);
+
+#endif /* CONFIG_FANS */
diff --git a/board/taniks/fw_config.c b/board/taniks/fw_config.c
new file mode 100644
index 0000000000..7d6323c868
--- /dev/null
+++ b/board/taniks/fw_config.c
@@ -0,0 +1,92 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "fw_config.h"
+#include "gpio.h"
+
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
+
+static union taniks_cbi_fw_config fw_config;
+BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
+
+/*
+ * FW_CONFIG defaults for Taniks if the CBI.FW_CONFIG data is not
+ * initialized.
+ */
+static const union taniks_cbi_fw_config fw_config_defaults = {
+	.usb_db = DB_USB3_PS8815,
+	.kb_bl = KEYBOARD_BACKLIGHT_ENABLED,
+};
+
+/****************************************************************************
+ * Taniks FW_CONFIG access
+ */
+static void determine_storage(void)
+{
+	const bool has_nvme = fw_config.nvme_status == NVME_ENABLED;
+	const bool has_emmc = fw_config.emmc_status == EMMC_ENABLED;
+	/*
+	 * If both masks are enabled or disabled, read the EMMC_SKU_DET pin
+	 * (should happen only in the factory).
+	 */
+	if (has_nvme == has_emmc) {
+		/* 0 = eMMC SKU, 1 = NVMe SKU */
+		if (gpio_get_level(GPIO_EMMC_SKU_DET)) {
+			CPRINTS("CBI: Detected NVMe SKU, disabling eMMC");
+			fw_config.emmc_status = EMMC_DISABLED;
+			fw_config.nvme_status = NVME_ENABLED;
+		} else {
+			CPRINTS("CBI: Detected eMMC SKU, disabling NVMe");
+			fw_config.nvme_status = NVME_DISABLED;
+			fw_config.emmc_status = EMMC_ENABLED;
+		}
+	}
+	cbi_set_board_info(CBI_TAG_FW_CONFIG, (uint8_t *)&fw_config,
+			   sizeof(fw_config));
+}
+
+void board_init_fw_config(void)
+{
+	if (cbi_get_fw_config(&fw_config.raw_value)) {
+		CPRINTS("CBI: Read FW_CONFIG failed, using board defaults");
+		fw_config = fw_config_defaults;
+	}
+
+	if (get_board_id() == 0) {
+		/* TODO(b/211076082): Update CBI fw config structure
+		 * Update correct FW_CONFIG.
+		 */
+		CPRINTS("CBI: Using board defaults for early board");
+		if (ec_cfg_has_tabletmode()) {
+			fw_config = fw_config_defaults;
+		}
+	}
+
+	determine_storage();
+}
+
+union taniks_cbi_fw_config get_fw_config(void)
+{
+	return fw_config;
+}
+
+enum ec_cfg_usb_db_type ec_cfg_usb_db_type(void)
+{
+	return fw_config.usb_db;
+}
+
+bool ec_cfg_has_keyboard_backlight(void)
+{
+	return (fw_config.kb_bl == KEYBOARD_BACKLIGHT_ENABLED);
+}
+
+bool ec_cfg_has_tabletmode(void)
+{
+	return (fw_config.tabletmode == TABLETMODE_ENABLED);
+}
diff --git a/board/taniks/fw_config.h b/board/taniks/fw_config.h
new file mode 100644
index 0000000000..05ca552538
--- /dev/null
+++ b/board/taniks/fw_config.h
@@ -0,0 +1,87 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __BOARD_TANIKS_FW_CONFIG_H_
+#define __BOARD_TANIKS_FW_CONFIG_H_
+
+#include <stdint.h>
+
+/****************************************************************************
+ * CBI FW_CONFIG layout for Taniks board.
+ *
+ * Source of truth is the project/taniks/taniks/config.star configuration file.
+ */
+
+enum ec_cfg_usb_db_type { DB_USB_ABSENT = 0, DB_USB3_PS8815 = 1 };
+
+enum ec_cfg_keyboard_backlight_type {
+	KEYBOARD_BACKLIGHT_DISABLED = 0,
+	KEYBOARD_BACKLIGHT_ENABLED = 1
+};
+
+enum ec_cfg_tabletmode_type { TABLETMODE_DISABLED = 0, TABLETMODE_ENABLED = 1 };
+
+enum ec_cfg_nvme_status {
+	NVME_DISABLED = 0,
+	NVME_ENABLED = 1,
+};
+enum ec_cfg_emmc_status {
+	EMMC_DISABLED = 0,
+	EMMC_ENABLED = 1,
+};
+
+union taniks_cbi_fw_config {
+	struct {
+		enum ec_cfg_usb_db_type usb_db : 2;
+		uint32_t sd_db : 2;
+		enum ec_cfg_keyboard_backlight_type kb_bl : 1;
+		uint32_t audio : 3;
+		uint32_t reserved_1 : 4;
+		/* b/211079131 - Fw config structure
+		 * b/211076082 - Move tablet mode to bit14
+		 * bit8-9: kb_layout
+		 * bit10-11: wifi_sar_id,
+		 * bit12: nvme
+		 * bit13: emmc
+		 */
+		enum ec_cfg_nvme_status nvme_status : 1;
+		enum ec_cfg_emmc_status emmc_status : 1;
+		enum ec_cfg_tabletmode_type tabletmode : 1;
+		uint32_t reserved_2 : 17;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Read the cached FW_CONFIG.  Guaranteed to have valid values.
+ *
+ * @return the FW_CONFIG for the board.
+ */
+union taniks_cbi_fw_config get_fw_config(void);
+
+/**
+ * Get the USB daughter board type from FW_CONFIG.
+ *
+ * @return the USB daughter board type.
+ */
+enum ec_cfg_usb_db_type ec_cfg_usb_db_type(void);
+
+/**
+ * Check if the FW_CONFIG has enabled keyboard backlight.
+ *
+ * @return true if board supports keyboard backlight, false if the board
+ * doesn't support it.
+ */
+bool ec_cfg_has_keyboard_backlight(void);
+
+/**
+ * Check if the FW_CONFIG has enabled tablet mode.
+ *
+ * @return true if board supports tablet mode, false if the board
+ * doesn't support it.
+ */
+bool ec_cfg_has_tabletmode(void);
+
+#endif /* __BOARD_TANIKS_FW_CONFIG_H_ */
diff --git a/board/taniks/gpio.inc b/board/taniks/gpio.inc
new file mode 100644
index 0000000000..d2c2bdffb9
--- /dev/null
+++ b/board/taniks/gpio.inc
@@ -0,0 +1,164 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define MODULE_KB		MODULE_KEYBOARD_SCAN
+
+/* INTERRUPT GPIOs: */
+GPIO_INT(ACOK_OD,                        PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
+GPIO_INT(EC_PROCHOT_IN_L,                PIN(2, 4), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
+GPIO_INT(EC_WP_ODL,                      PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(GSC_EC_PWR_BTN_ODL,             PIN(0, 1), GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW, power_button_interrupt)
+GPIO_INT(LID_OPEN,                       PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
+GPIO_INT(SEQ_EC_ALL_SYS_PG,              PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_DSW_PWROK,               PIN(2, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_RSMRST_ODL,              PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,                       PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,                      PIN(2, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SYS_SLP_S0IX_L,                 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(USB_C0_BC12_INT_ODL,            PIN(C, 6), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C0_TCPC_INT_ODL,            PIN(2, 3), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C0_PPC_INT_ODL,             PIN(6, 2), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C1_BC12_INT_ODL,            PIN(5, 0), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C1_TCPC_INT_ODL,            PIN(A, 2), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C1_PPC_INT_ODL,             PIN(F, 5), GPIO_INT_FALLING, ppc_interrupt)
+
+/* Keyboard interrupts */
+#define GPIO_KB_INPUT                    (GPIO_INPUT | GPIO_INT_RISING)
+
+GPIO_INT(EC_KSI_00,                      PIN(4, 4), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
+GPIO_INT(EC_KSI_01,                      PIN(4, 3), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
+GPIO_INT(EC_KSI_02,                      PIN(4, 1), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
+GPIO_INT(EC_KSI_03,                      PIN(3, 7), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
+GPIO_INT(EC_KSI_04,                      PIN(F, 1), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
+GPIO_INT(EC_KSI_05,                      PIN(F, 0), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
+GPIO_INT(EC_KSI_06,                      PIN(E, 0), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
+GPIO_INT(EC_KSI_07,                      PIN(C, 7), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
+GPIO_INT(EC_RFR_KEY_ODL_R,               PIN(8, 3), GPIO_INT_BOTH, keyboard_raw_gpio_interrupt)
+
+/* USED GPIOs: */
+GPIO(CCD_MODE_ODL,                   PIN(E, 5), GPIO_INPUT)
+GPIO(CHARGER_VAP_OTG_EN,             PIN(7, 3), GPIO_OUT_LOW)
+GPIO(CPU_C10_GATE_L,                 PIN(6, 7), GPIO_INPUT)
+GPIO(EC_ACCEL_INT_R_L,               PIN(8, 1), GPIO_INPUT)
+GPIO(EC_BATT_PRES_ODL,               PIN(A, 3), GPIO_INPUT)
+GPIO(EC_ENTERING_RW,                 PIN(0, 3), GPIO_OUT_LOW)
+GPIO(EC_EN_EDP_BL,                   PIN(D, 3), GPIO_OUT_HIGH)
+GPIO(EC_GSC_PACKET_MODE,             PIN(7, 5), GPIO_OUT_LOW)
+GPIO(EC_I2C_BAT_SCL,                 PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_BAT_SDA,                 PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SCL_R,              PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SDA_R,              PIN(B, 2), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,              PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SENSOR_SDA,              PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_USB_C0_PPC_BC_SCL,       PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_PPC_BC_SDA,       PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_KBMCU_SCL,               PIN(D, 1), GPIO_INPUT)
+GPIO(EC_I2C_KBMCU_SDA,               PIN(D, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_TCPC_SCL,         PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_TCPC_SDA,         PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_MIX_SCL,          PIN(E, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_MIX_SDA,          PIN(E, 3), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_TCPC_SCL,         PIN(F, 3), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_TCPC_SDA,         PIN(F, 2), GPIO_INPUT)
+GPIO(EC_KB_BL_EN_L,                  PIN(8, 6), GPIO_OUT_HIGH)
+GPIO(EC_PCHHOT_ODL,                  PIN(7, 4), GPIO_INPUT)
+GPIO(EC_PCH_INT_ODL,                 PIN(B, 0), GPIO_ODR_HIGH)
+GPIO(EC_PCH_PWR_BTN_ODL,             PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(EC_PCH_RSMRST_L,                PIN(A, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_RTCRST,                  PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_SYS_PWROK,               PIN(2, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_WAKE_R_ODL,              PIN(C, 0), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_ODL,                 PIN(6, 3), GPIO_ODR_HIGH)
+GPIO(EN_PP5000_FAN,                  PIN(6, 1), GPIO_OUT_LOW)
+GPIO(EN_PP5000_USBA_R,               PIN(D, 7), GPIO_OUT_LOW)
+GPIO(EN_S5_RAILS,                    PIN(B, 6), GPIO_OUT_LOW)
+GPIO(IMVP9_VRRDY_OD,                 PIN(3, 0), GPIO_INPUT)
+GPIO(PCH_PWROK,                      PIN(7, 2), GPIO_OUT_LOW)
+GPIO(SYS_RST_ODL,                    PIN(C, 5), GPIO_ODR_HIGH)
+GPIO(USB_C0_TCPC_RST_ODL,            PIN(A, 7), GPIO_ODR_LOW)
+GPIO(USB_C1_FRS_EN,                  PIN(9, 4), GPIO_OUT_LOW)
+GPIO(USB_C1_RT_RST_R_ODL,            PIN(0, 2), GPIO_ODR_HIGH)
+GPIO(VCCST_PWRGD_OD,                 PIN(A, 4), GPIO_ODR_LOW)
+GPIO(KBMCU_INT_ODL,                  PIN(7, 0), GPIO_ODR_HIGH)
+GPIO(EMMC_SKU_DET,                   PIN(D, 4), GPIO_INPUT)
+
+/* KB Outputs */
+#define GPIO_KB_OUTPUT               (GPIO_OUT_HIGH)
+
+GPIO(EC_KSO_00,                      PIN(2, 1),  GPIO_KB_OUTPUT)
+GPIO(EC_KSO_01,                      PIN(2, 0),  GPIO_KB_OUTPUT)
+GPIO(EC_KSO_02_R,                    PIN(1, 7),  GPIO_KB_OUTPUT)
+GPIO(EC_KSO_03,                      PIN(1, 6),  GPIO_KB_OUTPUT)
+GPIO(EC_KSO_04,                      PIN(1, 5),  GPIO_KB_OUTPUT)
+GPIO(EC_KSO_05,                      PIN(1, 4),  GPIO_KB_OUTPUT)
+GPIO(EC_KSO_06_R,                    PIN(9, 6),  GPIO_KB_OUTPUT)
+GPIO(EC_KSO_07_R,                    PIN(A, 0),  GPIO_KB_OUTPUT)
+GPIO(EC_KSO_08,                      PIN(1, 1),  GPIO_KB_OUTPUT)
+GPIO(EC_KSO_09,                      PIN(1, 0),  GPIO_KB_OUTPUT)
+GPIO(EC_KSO_10,                      PIN(0, 7),  GPIO_KB_OUTPUT)
+GPIO(EC_KSO_11,                      PIN(0, 6),  GPIO_KB_OUTPUT)
+GPIO(EC_KSO_12,                      PIN(0, 5),  GPIO_KB_OUTPUT)
+GPIO(EC_KSO_13,                      PIN(0, 4),  GPIO_KB_OUTPUT)
+GPIO(EC_KSO_14,                      PIN(8, 2),  GPIO_KB_OUTPUT)
+
+/* UART alternate functions */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)              /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */
+
+/* I2C alternate functions */
+ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)               /* GPIO33/I2C5_SCL0/CTS_L, GPIO36/RTS_L/I2C5_SDA0 */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)               /* GPIO87/I2C1_SDA0 */
+ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)               /* GPIO92/I2C2_SCL0, GPIO91/I2C2_SDA0, GPIO90/I2C1_SCL0 */
+ALTERNATE(PIN_MASK(B, 0x0c), 0, MODULE_I2C, 0)               /* GPIOB3/I2C7_SCL0/DCD_L, GPIOB2/I2C7_SDA0/DSR_L */
+ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, GPIO_SEL_1P8V)   /* GPIOB5/I2C0_SCL0, GPIOB4/I2C0_SDA0 */
+ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)               /* GPIOD1/I2C3_SCL0, GPIOD0/I2C3_SDA0 */
+ALTERNATE(PIN_MASK(E, 0x18), 0, MODULE_I2C, 0)               /* GPIOE4/I2C6_SCL1/I3C_SCL, GPIOE3/I2C6_SDA1/I3C_SDA */
+ALTERNATE(PIN_MASK(F, 0x0c), 0, MODULE_I2C, 0)               /* GPIOF3/I2C4_SCL1, GPIOF2/I2C4_SDA1 */
+
+/* PWM alternate functions */
+ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0)               /* GPIO40/TA1 */
+ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)               /* GPIO80/PWM3 */
+ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)               /* GPIOB7/PWM5 */
+
+/* ADC alternate functions */
+ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0)               /* GPIO34/PS2_DAT2/ADC6 */
+ALTERNATE(PIN_MASK(4, 0x24), 0, MODULE_ADC, 0)               /* GPIO42/ADC3/RI_L, GPIO45/ADC0 */
+ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0)               /* GPIOE1/ADC7 */
+
+/* PMU alternate functions */
+ALTERNATE(PIN_MASK(0, 0x01), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN2_L&GPI00/GPIO00 */
+ALTERNATE(PIN_MASK(0, 0x02), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW) /* GPIO01/PSL_IN3_L&GPI01 */
+ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN1_L&GPID2/GPIOD2 */
+
+/* Unused Pins */
+UNUSED(PIN(B, 1))       /* KSO17/GPIOB1/CR_SIN4 */
+UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
+UNUSED(PIN(3, 2))       /* GPO32/TRIS_L */
+UNUSED(PIN(3, 5))       /* GPO35/CR_SOUT4/TEST_L */
+UNUSED(PIN(6, 6))       /* GPIO66 */
+UNUSED(PIN(5, 7))       /* GPIO57/SER_IRQ/ESPI_ALERT_L */
+UNUSED(PIN(9, 5))       /* GPIO95/SPIP_MISO */
+UNUSED(PIN(5, 6))       /* GPIO56/CLKRUN# */
+UNUSED(PIN(9, 3))       /* GPIO93/TA1/F_DIO2 */
+UNUSED(PIN(9, 7))       /* GPIO97 */
+
+/* Pre-configured PSL balls:  J8  K6 */
+
+/*
+ * The NPCX keyboard driver does not use named GPIOs to access
+ * keyboard scan pins, so we do not list them in *gpio.inc. However, when
+ * KEYBOARD_COL2_INVERTED is defined, this name is required.
+ */
+
+/* GPIO02_P2 to PU */
+/* GPIO03_P2 to PU */
+IOEX(USB_C0_OC_ODL,          EXPIN(IOEX_C0_NCT38XX, 0, 4), GPIO_ODR_HIGH)
+IOEX(USB_C0_FRS_EN,          EXPIN(IOEX_C0_NCT38XX, 0, 6), GPIO_OUT_LOW)
+
+/* LED */
+GPIO(LED_1_L,	 PIN(C, 4), GPIO_OUT_HIGH)	/* Battery - Red LED */
+GPIO(LED_2_L,	 PIN(C, 3), GPIO_OUT_HIGH)	/* Battery - Green LED */
+GPIO(LED_3_L,	 PIN(C, 2), GPIO_OUT_HIGH)	/* Power - White LED */
diff --git a/board/taniks/i2c.c b/board/taniks/i2c.c
new file mode 100644
index 0000000000..28a49b0fae
--- /dev/null
+++ b/board/taniks/i2c.c
@@ -0,0 +1,80 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "i2c.h"
+
+/* I2C port map configuration */
+const struct i2c_port_t i2c_ports[] = {
+	{
+		/* I2C0 */
+		.name = "sensor",
+		.port = I2C_PORT_SENSOR,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_SENSOR_SCL,
+		.sda = GPIO_EC_I2C_SENSOR_SDA,
+	},
+	{
+		/* I2C1 */
+		.name = "tcpc0",
+		.port = I2C_PORT_USB_C0_TCPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_TCPC_SDA,
+	},
+	{
+		/* I2C2 */
+		.name = "ppc0",
+		.port = I2C_PORT_USB_C0_PPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_PPC_BC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_PPC_BC_SDA,
+	},
+	{
+		/* I2C3 */
+		.name = "kbmcu",
+		.port = I2C_PORT_KBMCU,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_KBMCU_SCL,
+		.sda = GPIO_EC_I2C_KBMCU_SDA,
+	},
+	{
+		/* I2C4 C1 TCPC */
+		/* TODO(b/211080526): Change TCPC1's (PS8815) I2C frequency from
+		   400Khz to 1000Khz */
+		.name = "tcpc1",
+		.port = I2C_PORT_USB_C1_TCPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C1_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C1_TCPC_SDA,
+		.flags = I2C_PORT_FLAG_DYNAMIC_SPEED,
+	},
+	{
+		/* I2C5 */
+		.name = "battery",
+		.port = I2C_PORT_BATTERY,
+		.kbps = 100,
+		.scl = GPIO_EC_I2C_BAT_SCL,
+		.sda = GPIO_EC_I2C_BAT_SDA,
+	},
+	{
+		/* I2C6 */
+		.name = "ppc1",
+		.port = I2C_PORT_USB_C1_PPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C1_MIX_SCL,
+		.sda = GPIO_EC_I2C_USB_C1_MIX_SDA,
+	},
+	{
+		/* I2C7 */
+		.name = "eeprom",
+		.port = I2C_PORT_EEPROM,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_MISC_SCL_R,
+		.sda = GPIO_EC_I2C_MISC_SDA_R,
+	},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/board/taniks/keyboard.c b/board/taniks/keyboard.c
new file mode 100644
index 0000000000..069627a168
--- /dev/null
+++ b/board/taniks/keyboard.c
@@ -0,0 +1,125 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "aw20198.h"
+#include "common.h"
+#include "ec_commands.h"
+#include "keyboard_scan.h"
+#include "rgb_keyboard.h"
+#include "timer.h"
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/* Increase from 50 us, because KSO_02 passes through the H1. */
+	.output_settle_us = 80,
+	/* Other values should be the same as the default configuration. */
+	.debounce_down_us = 9 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x1c, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xa4, 0xff, 0xff, 0x55, 0xff, 0xff, 0xff, 0xff,  /* full set */
+	},
+	.ksi_threshold_mv = 250,
+};
+
+static const struct ec_response_keybd_config taniks_kb = {
+	.num_top_row_keys = 11,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_MICMUTE,		/* T8 */
+		TK_VOL_MUTE,		/* T9 */
+		TK_VOL_DOWN,		/* T10 */
+		TK_VOL_UP,		/* T11 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY | KEYBD_CAP_NUMERIC_KEYPAD,
+};
+
+/*
+ * Row Column info for Top row keys T1 - T15.
+ * For taniks keyboard layout(T11 - T14) and
+ * printing(F8 - F11) are different issue.
+ * Move T11 - T14 row and col setting to T8 - T11.
+ * Need define row col to mapping matrix layout.
+ * Change T8 row, col to (0,1)
+ * Change T9 row, col to (1,5)
+ * Change T10 row, col to (3,5)
+ * Change T11 row, col to (0,9)
+ */
+__override const struct key {
+	uint8_t row;
+	uint8_t col;
+} vivaldi_keys[] = {
+	{ .row = 0, .col = 2 }, /* T1 */
+	{ .row = 3, .col = 2 }, /* T2 */
+	{ .row = 2, .col = 2 }, /* T3 */
+	{ .row = 1, .col = 2 }, /* T4 */
+	{ .row = 3, .col = 4 }, /* T5 */
+	{ .row = 2, .col = 4 }, /* T6 */
+	{ .row = 1, .col = 4 }, /* T7 */
+	{ .row = 0, .col = 1 }, /* T8 */
+	{ .row = 1, .col = 5 }, /* T9 */
+	{ .row = 3, .col = 5 }, /* T10 */
+	{ .row = 0, .col = 9 }, /* T11 */
+	{ .row = 2, .col = 9 }, /* T12 */
+	{ .row = 1, .col = 9 }, /* T13 */
+	{ .row = 0, .col = 4 }, /* T14 */
+	{ .row = 0, .col = 11 }, /* T15 */
+};
+BUILD_ASSERT(ARRAY_SIZE(vivaldi_keys) == MAX_TOP_ROW_KEYS);
+
+static struct rgb_s grid0[RGB_GRID0_COL * RGB_GRID0_ROW];
+
+struct rgbkbd rgbkbds[] = {
+	[0] = {
+		.cfg = &(const struct rgbkbd_cfg) {
+			.drv = &aw20198_drv,
+			.i2c = I2C_PORT_KBMCU,
+			.col_len = RGB_GRID0_COL,
+			.row_len = RGB_GRID0_ROW,
+		},
+		.buf = grid0,
+	},
+};
+const uint8_t rgbkbd_count = ARRAY_SIZE(rgbkbds);
+
+const uint8_t rgbkbd_hsize = RGB_GRID0_COL;
+const uint8_t rgbkbd_vsize = RGB_GRID0_ROW;
+
+enum ec_rgbkbd_type rgbkbd_type = EC_RGBKBD_TYPE_FOUR_ZONES_40_LEDS;
+
+#define LED(x, y) RGBKBD_COORD((x), (y))
+#define DELM RGBKBD_DELM
+
+const uint8_t rgbkbd_map[] = {
+	DELM, LED(0, 0), DELM, LED(1, 0), DELM, LED(2, 0), DELM, LED(3, 0),
+	DELM, LED(4, 0), DELM, LED(5, 0), DELM, LED(6, 0), DELM, LED(7, 0),
+	DELM, LED(0, 1), DELM, LED(1, 1), DELM, LED(2, 1), DELM, LED(3, 1),
+	DELM, LED(4, 1), DELM, LED(5, 1), DELM, LED(6, 1), DELM, LED(7, 1),
+	DELM, LED(0, 2), DELM, LED(1, 2), DELM, LED(2, 2), DELM, LED(3, 2),
+	DELM, LED(4, 2), DELM, LED(5, 2), DELM, LED(6, 2), DELM, LED(7, 2),
+	DELM, LED(0, 3), DELM, LED(1, 3), DELM, LED(2, 3), DELM, LED(3, 3),
+	DELM, LED(4, 3), DELM, LED(5, 3), DELM, LED(6, 3), DELM, LED(7, 3),
+	DELM, LED(0, 4), DELM, LED(1, 4), DELM, LED(2, 4), DELM, LED(3, 4),
+	DELM, LED(4, 4), DELM, LED(5, 4), DELM, LED(6, 4), DELM, LED(7, 4),
+	DELM, DELM,
+};
+#undef LED
+#undef DELM
+const size_t rgbkbd_map_size = ARRAY_SIZE(rgbkbd_map);
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &taniks_kb;
+}
diff --git a/board/taniks/led.c b/board/taniks/led.c
new file mode 100644
index 0000000000..b231d55909
--- /dev/null
+++ b/board/taniks/led.c
@@ -0,0 +1,124 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Taniks specific PWM LED settings: there are 2 LEDs on each side of the board,
+ * each one can be controlled separately. The LED colors are white or amber,
+ * and the default behavior is tied to the charging process: both sides are
+ * amber while charging the battery and white when the battery is charged.
+ */
+
+#include "common.h"
+#include "gpio.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
+
+__override const int led_charge_lvl_1 = 5;
+
+__override const int led_charge_lvl_2 = 97;
+
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
+
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    1 * LED_ONE_SEC },
+						  { LED_OFF,
+						    3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_power(enum ec_led_colors color)
+{
+	if (color == EC_LED_COLOR_WHITE)
+		gpio_set_level(GPIO_LED_3_L, LED_ON_LVL);
+	else
+		/* LED_OFF and unsupported colors */
+		gpio_set_level(GPIO_LED_3_L, LED_OFF_LVL);
+}
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_AMBER:
+		gpio_set_level(GPIO_LED_1_L, LED_ON_LVL);
+		gpio_set_level(GPIO_LED_2_L, LED_ON_LVL);
+		break;
+	case EC_LED_COLOR_RED:
+		gpio_set_level(GPIO_LED_1_L, LED_ON_LVL);
+		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
+		break;
+	case EC_LED_COLOR_GREEN:
+		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_2_L, LED_ON_LVL);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_RED] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		brightness_range[EC_LED_COLOR_GREEN] = 1;
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		if (brightness[EC_LED_COLOR_RED] != 0)
+			led_set_color_battery(EC_LED_COLOR_RED);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(EC_LED_COLOR_AMBER);
+		else if (brightness[EC_LED_COLOR_GREEN] != 0)
+			led_set_color_battery(EC_LED_COLOR_GREEN);
+		else
+			led_set_color_battery(LED_OFF);
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_power(EC_LED_COLOR_WHITE);
+		else
+			led_set_color_power(LED_OFF);
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/board/taniks/pwm.c b/board/taniks/pwm.c
new file mode 100644
index 0000000000..62d6c5d8ea
--- /dev/null
+++ b/board/taniks/pwm.c
@@ -0,0 +1,17 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "hooks.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
diff --git a/board/taniks/sensors.c b/board/taniks/sensors.c
new file mode 100644
index 0000000000..54de4ffc56
--- /dev/null
+++ b/board/taniks/sensors.c
@@ -0,0 +1,419 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "accelgyro.h"
+#include "adc_chip.h"
+#include "common.h"
+#include "driver/accel_bma422.h"
+#include "driver/accel_bma4xx.h"
+#include "driver/accel_lis2dw12.h"
+#include "driver/accelgyro_lsm6dsm.h"
+#include "driver/accelgyro_lsm6dso.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "motion_sense.h"
+#include "tablet_mode.h"
+#include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
+#include "thermal.h"
+
+#if 1
+#define CPRINTS(format, args...) ccprints(format, ##args)
+#define CPRINTF(format, args...) ccprintf(format, ##args)
+#else
+#define CPRINTS(format, args...)
+#define CPRINTF(format, args...)
+#endif
+
+/* ADC configuration */
+const struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_1_DDR_SOC] = {
+		.name = "TEMP_DDR_SOC",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_3_CHARGER] = {
+		.name = "TEMP_CHARGER",
+		.input_ch = NPCX_ADC_CH6,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_4_CPUCHOKE] = {
+		.name = "CPU_CHOKE",
+		.input_ch = NPCX_ADC_CH7,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_KSI_00] = {
+		.name = "KSI_00",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_KSI_01] = {
+		.name = "KSI_01",
+		.input_ch = NPCX_ADC_CH2,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_KSI_02] = {
+		.name = "KSI_02",
+		.input_ch = NPCX_ADC_CH4,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_KSI_03] = {
+		.name = "KSI_03",
+		.input_ch = NPCX_ADC_CH5,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_KSI_04] = {
+		.name = "KSI_04",
+		.input_ch = NPCX_ADC_CH8,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_KSI_05] = {
+		.name = "KSI_05",
+		.input_ch = NPCX_ADC_CH9,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_KSI_06] = {
+		.name = "KSI_06",
+		.input_ch = NPCX_ADC_CH10,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_KSI_07] = {
+		.name = "KSI_07",
+		.input_ch = NPCX_ADC_CH11,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+K_MUTEX_DEFINE(g_lid_accel_mutex);
+K_MUTEX_DEFINE(g_base_accel_mutex);
+static struct stprivate_data g_lis2dw12_data;
+static struct accelgyro_saved_data_t g_bma422_data;
+static struct lsm6dso_data lsm6dso_data;
+static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
+
+/* Matrix to rotate lid and base sensor into standard reference frame */
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					     { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
+
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, FLOAT_TO_FP(1), 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
+
+struct motion_sensor_t bma422_lid_accel = {
+	.name = "Lid Accel - BMA",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_BMA422,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_LID,
+	.drv = &bma4_accel_drv,
+	.mutex = &g_lid_accel_mutex,
+	.drv_data = &g_bma422_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = BMA4_I2C_ADDR_PRIMARY, /* 0x18 */
+	.rot_standard_ref = &lid_standard_ref, /* identity matrix */
+	.default_range = 2, /* g, enough for laptop. */
+	.min_frequency = BMA4_ACCEL_MIN_FREQ,
+	.max_frequency = BMA4_ACCEL_MAX_FREQ,
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 12500 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+		/* Sensor on in S3 */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 12500 | ROUND_UP_FLAG,
+			.ec_rate = 0,
+		},
+	},
+};
+
+struct motion_sensor_t lsm6dsm_base_accel = {
+	.name = "Base Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_LSM6DSM,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &lsm6dsm_drv,
+	.mutex = &g_base_accel_mutex,
+	.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
+			MOTIONSENSE_TYPE_ACCEL),
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
+	.rot_standard_ref = &base_standard_ref,
+	.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
+	.min_frequency = LSM6DSM_ODR_MIN_VAL,
+	.max_frequency = LSM6DSM_ODR_MAX_VAL,
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 13000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+		/* Sensor on for angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+	},
+};
+
+struct motion_sensor_t lsm6dsm_base_gyro = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_LSM6DSM,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &lsm6dsm_drv,
+	.mutex = &g_base_accel_mutex,
+	.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data, MOTIONSENSE_TYPE_GYRO),
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
+	.default_range = 1000 | ROUND_UP_FLAG, /* dps */
+	.rot_standard_ref = &base_standard_ref,
+	.min_frequency = LSM6DSM_ODR_MIN_VAL,
+	.max_frequency = LSM6DSM_ODR_MAX_VAL,
+};
+
+struct motion_sensor_t motion_sensors[] = {
+	[LID_ACCEL] = {
+		.name = "Lid Accel - ST",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LIS2DW12,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &lis2dw12_drv,
+		.mutex = &g_lid_accel_mutex,
+		.drv_data = &g_lis2dw12_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LIS2DW12_ADDR1, /* 0x19 */
+		.rot_standard_ref = &lid_standard_ref, /* identity matrix */
+		.default_range = 2, /* g */
+		.min_frequency = LIS2DW12_ODR_MIN_VAL,
+		.max_frequency = LIS2DW12_ODR_MAX_VAL,
+		.config = {
+			/* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 12500 | ROUND_UP_FLAG,
+			},
+			/* Sensor on for lid angle detection */
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+		},
+	},
+
+	[BASE_ACCEL] = {
+		.name = "Base Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LSM6DSO,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &lsm6dso_drv,
+		.mutex = &g_base_accel_mutex,
+		.drv_data = &lsm6dso_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LSM6DSO_ADDR0_FLAGS,
+		.rot_standard_ref = &base_standard_ref,
+		.default_range = 4,  /* g */
+		.min_frequency = LSM6DSO_ODR_MIN_VAL,
+		.max_frequency = LSM6DSO_ODR_MAX_VAL,
+		.config = {
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 13000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+		},
+	},
+
+	[BASE_GYRO] = {
+		.name = "Base Gyro",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_LSM6DSO,
+		.type = MOTIONSENSE_TYPE_GYRO,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &lsm6dso_drv,
+		.mutex = &g_base_accel_mutex,
+		.drv_data = &lsm6dso_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = LSM6DSO_ADDR0_FLAGS,
+		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = LSM6DSO_ODR_MIN_VAL,
+		.max_frequency = LSM6DSO_ODR_MAX_VAL,
+	},
+
+};
+
+#ifdef CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
+unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+#else
+const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+#endif
+
+static void board_detect_motionsensor(void)
+{
+	int ret;
+	int val;
+
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return;
+
+	/*
+	 * b/194765820 - Dynamic motion sensor count
+	 * All board supports tablet mode if board id > 0
+	 */
+	if (get_board_id() == 0 && !ec_cfg_has_tabletmode())
+		return;
+
+	/* Check lid accel chip */
+	ret = i2c_read8(I2C_PORT_SENSOR, LIS2DW12_ADDR1, LIS2DW12_WHO_AM_I_REG,
+			&val);
+	if (ret == 0 && val == LIS2DW12_WHO_AM_I) {
+		CPRINTS("LID_ACCEL is LIS2DW12");
+		return;
+	}
+
+	ret = i2c_read8(I2C_PORT_SENSOR, BMA4_I2C_ADDR_PRIMARY,
+			BMA4_CHIP_ID_ADDR, &val);
+	if (ret == 0 && val == BMA422_CHIP_ID) {
+		CPRINTS("LID_ACCEL is BMA422");
+		motion_sensors[LID_ACCEL] = bma422_lid_accel;
+		/*
+		 * The driver for BMA422 doesn't have code to support
+		 * INT1. So, it doesn't need to enable interrupt.
+		 * Vendor recommend to configure EC gpio as high-z if
+		 * we don't use INT1. Keep this pin as input w/o enable
+		 * interrupt.
+		 */
+		return;
+	}
+
+	/* Lid accel is not stuffed, don't allow line to float */
+	gpio_disable_interrupt(GPIO_EC_ACCEL_INT_R_L);
+	gpio_set_flags(GPIO_EC_ACCEL_INT_R_L, GPIO_INPUT | GPIO_PULL_DOWN);
+	CPRINTS("No LID_ACCEL are detected");
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_detect_motionsensor,
+	     HOOK_PRIO_DEFAULT);
+
+static void baseboard_sensors_init(void)
+{
+	CPRINTS("baseboard_sensors_init");
+
+	CPRINTS("Clamshell");
+}
+DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_INIT_I2C + 1);
+
+/* Temperature sensor configuration */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1_DDR_SOC] = { .name = "DDR and SOC",
+				    .type = TEMP_SENSOR_TYPE_BOARD,
+				    .read = get_temp_3v3_30k9_47k_4050b,
+				    .idx = ADC_TEMP_SENSOR_1_DDR_SOC },
+	[TEMP_SENSOR_3_CHARGER] = { .name = "CHARGER",
+				    .type = TEMP_SENSOR_TYPE_BOARD,
+				    .read = get_temp_3v3_30k9_47k_4050b,
+				    .idx = ADC_TEMP_SENSOR_3_CHARGER },
+	[TEMP_SENSOR_4_CPUCHOKE] = { .name = "CPU CHOKE",
+				     .type = TEMP_SENSOR_TYPE_BOARD,
+				     .read = get_temp_3v3_30k9_47k_4050b,
+				     .idx = ADC_TEMP_SENSOR_4_CPUCHOKE },
+};
+
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/*
+ * TODO(b/201021109): update for Alder Lake/brya
+ *
+ * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
+ * 130 C.  However, sensor is located next to DDR, so we need to use the lower
+ * DDR temperature limit (100 C)
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(90), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(100), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(85), \
+		}, \
+		.temp_fan_off = C_TO_K(35), \
+		.temp_fan_max = C_TO_K(70), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
+
+/*
+ * TODO(b/201021109): update for Alder Lake/brya
+ *
+ * Inductor limits - used for both charger and PP3300 regulator
+ *
+ * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
+ *
+ * Charger max recommended temperature 100C, max absolute temperature 125C
+ * PP3300 regulator: operating range -40 C to 145 C
+ *
+ * Inductors: limit of 125c
+ * PCB: limit is 100c
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_FAN              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(90), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(100), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(85), \
+		}, \
+		.temp_fan_off = C_TO_K(35), \
+		.temp_fan_max = C_TO_K(70), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_fan = THERMAL_FAN;
+
+/* this should really be "const" */
+struct ec_thermal_config thermal_params[] = {
+	[TEMP_SENSOR_1_DDR_SOC] = THERMAL_CPU,
+	[TEMP_SENSOR_3_CHARGER] = THERMAL_FAN,
+	[TEMP_SENSOR_4_CPUCHOKE] = THERMAL_FAN,
+};
+
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
diff --git a/board/taniks/usbc_config.c b/board/taniks/usbc_config.c
new file mode 100644
index 0000000000..0c58ca5ff4
--- /dev/null
+++ b/board/taniks/usbc_config.c
@@ -0,0 +1,400 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/bc12/pi3usb9201_public.h"
+#include "driver/ppc/nx20p348x.h"
+#include "driver/ppc/syv682x_public.h"
+#include "driver/retimer/bb_retimer_public.h"
+#include "driver/tcpm/nct38xx.h"
+#include "driver/tcpm/ps8xxx_public.h"
+#include "driver/tcpm/tcpci.h"
+#include "ec_commands.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "ioexpander.h"
+#include "system.h"
+#include "task.h"
+#include "task_id.h"
+#include "timer.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+#if 0
+/* Debug only! */
+#define CPRINTSUSB(format, args...) cprints(CC_USBPD, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBPD, format, ##args)
+#else
+#define CPRINTSUSB(format, args...)
+#define CPRINTFUSB(format, args...)
+#endif
+
+/* USBC TCPC configuration */
+const struct tcpc_config_t tcpc_config[] = {
+	[USBC_PORT_C0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0_TCPC,
+			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+	},
+	[USBC_PORT_C1] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C1_TCPC,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
+			 TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V |
+			 TCPC_FLAGS_CONTROL_VCONN |
+			 TCPC_FLAGS_CONTROL_FRS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
+BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
+
+/* USBC PPC configuration */
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_PPC,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.frs_en = IOEX_USB_C0_FRS_EN,
+		.drv = &syv682x_drv,
+	},
+	[USBC_PORT_C1] = {
+		/* Compatible with Silicon Mitus SM536A0 */
+		.i2c_port = I2C_PORT_USB_C1_PPC,
+		.i2c_addr_flags = NX20P3483_ADDR2_FLAGS,
+		.drv = &nx20p348x_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
+
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/* USBC mux configuration - Alder Lake includes internal mux */
+
+/*
+ * USB3 DB mux configuration - the top level mux still needs to be set
+ * to the virtual_usb_mux_driver so the AP gets notified of mux changes
+ * and updates the TCSS configuration on state changes.
+ */
+static const struct usb_mux_chain usbc1_usb3_db_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
+};
+
+const struct usb_mux_chain usb_muxes[] = {
+	[USBC_PORT_C0] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+	},
+	[USBC_PORT_C1] = {
+		.mux = &(const struct usb_mux) {
+			/* PS8815 DB */
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc1_usb3_db_retimer,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
+
+/* BC1.2 charger detect configuration */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C1_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
+
+/*
+ * USB C0 and C2 uses burnside bridge chips and have their reset
+ * controlled by their respective TCPC chips acting as GPIO expanders.
+ *
+ * ioex_init() is normally called before we take the TCPCs out of
+ * reset, so we need to start in disabled mode, then explicitly
+ * call ioex_init().
+ */
+
+struct ioexpander_config_t ioex_config[] = {
+	[IOEX_C0_NCT38XX] = {
+		.i2c_host_port = I2C_PORT_USB_C0_TCPC,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT);
+
+void config_usb_db_type(void)
+{
+	enum ec_cfg_usb_db_type db_type = ec_cfg_usb_db_type();
+
+	/*
+	 * TODO(b/194515356): implement multiple DB types
+	 */
+	CPRINTS("Configured USB DB type number is %d", db_type);
+}
+
+static void ps8815_reset(void)
+{
+	int val;
+
+	CPRINTS("%s: patching ps8815 registers", __func__);
+
+	if (i2c_read8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_FLAGS, 0x0f,
+		      &val) == EC_SUCCESS)
+		CPRINTS("ps8815: reg 0x0f was %02x", val);
+	else {
+		CPRINTS("delay 10ms to make sure PS8815 is waken from idle");
+		msleep(10);
+	}
+
+	if (i2c_write8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_FLAGS, 0x0f,
+		       0x31) == EC_SUCCESS)
+		CPRINTS("ps8815: reg 0x0f set to 0x31");
+
+	if (i2c_read8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_FLAGS, 0x0f,
+		      &val) == EC_SUCCESS)
+		CPRINTS("ps8815: reg 0x0f now %02x", val);
+}
+
+/**
+ * b/197585292
+ * It's used for early board to check if usb_db is plugged or not.
+ * That's used to avoid TCPC1 initialization abnormal if db isn't
+ * plugged into system.
+ */
+enum usb_db_present {
+	DB_USB_NOT_PRESENT = 0,
+	DB_USB_PRESENT = 1,
+};
+static enum usb_db_present db_usb_hw_pres;
+
+/**
+ * Init hw ps8815 detection and keep it in db_usb_hw_press.
+ * Then, we don't need to keep query ps8815 mcu.
+ */
+static void board_init_ps8815_detection(void)
+{
+	int rv, val;
+
+	CPRINTSUSB("%s", __func__);
+
+	rv = i2c_read8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_FLAGS, 0x00,
+		       &val);
+
+	db_usb_hw_pres = (rv == EC_SUCCESS) ? DB_USB_PRESENT :
+					      DB_USB_NOT_PRESENT;
+
+	if (db_usb_hw_pres == DB_USB_NOT_PRESENT)
+		CPRINTS("DB isn't plugged or something went wrong!");
+}
+
+/**
+ * @return true if ps8815_db is plugged, false if it isn't plugged.
+ */
+static bool board_detect_ps8815_db(void)
+{
+	CPRINTSUSB("%s", __func__);
+
+	/* All dut should plug ps8815 db if board id > 0 */
+	if (get_board_id() > 0)
+		return true;
+
+	if (ec_cfg_usb_db_type() == DB_USB3_PS8815 &&
+	    db_usb_hw_pres == DB_USB_PRESENT)
+		return true;
+
+	CPRINTSUSB("No PS8815 DB");
+	return false;
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * TODO(b/194618663): figure out correct timing
+	 */
+
+	gpio_set_level(GPIO_USB_C0_TCPC_RST_ODL, 0);
+
+	/*
+	 * (b/202489681): Nx20p3483 cannot sink power after reset ec
+	 * To avoid nx20p3483 cannot sink power after reset ec w/ AC
+	 * only in TCPC1 port, EC shouldn't assert GPIO_USB_C1_RT_RST_R_ODL
+	 * if no battery.
+	 */
+	if (battery_hw_present())
+		gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 0);
+
+	/*
+	 * delay for power-on to reset-off and min. assertion time
+	 */
+	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS));
+
+	gpio_set_level(GPIO_USB_C0_TCPC_RST_ODL, 1);
+	gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 1);
+
+	/* wait for chips to come up */
+	msleep(PS8815_FW_INIT_DELAY_MS);
+	ps8815_reset();
+
+	/*
+	 * board_init_ps8815_detection should be called before
+	 * board_get_usb_pd_port_count(). usb_mux_hpd_update can check
+	 * pd port count.
+	 */
+	board_init_ps8815_detection();
+	usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+}
+
+static void board_tcpc_init(void)
+{
+	CPRINTSUSB("%s: board id = %d", __func__, get_board_id());
+
+	/* Don't reset TCPCs after initial reset */
+	if (!system_jumped_late()) {
+		board_reset_pd_mcu();
+
+		/*
+		 * These IO expander pins are implemented using the
+		 * C0/C2 TCPC, so they must be set up after the TCPC has
+		 * been taken out of reset.
+		 */
+		ioex_init(0);
+	}
+
+	CPRINTSUSB("Enable GPIO INT");
+
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
+	if (board_detect_ps8815_db())
+		gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
+	if (board_detect_ps8815_db())
+		gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
+
+	/* Enable BC1.2 interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
+	if (board_detect_ps8815_db())
+		gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_0;
+
+	if (gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
+
+int ppc_get_alert_status(int port)
+{
+	if (port == USBC_PORT_C0)
+		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
+
+	if (port == USBC_PORT_C1)
+		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
+
+	return 0;
+}
+
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C1);
+		break;
+	default:
+		break;
+	}
+}
+
+void bc12_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_BC12_INT_ODL:
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+		break;
+	case GPIO_USB_C1_BC12_INT_ODL:
+		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+		break;
+	default:
+		break;
+	}
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_PPC_INT_ODL:
+		nx20p348x_interrupt(USBC_PORT_C1);
+		break;
+	default:
+		break;
+	}
+}
+
+__override bool board_is_dts_port(int port)
+{
+	return port == USBC_PORT_C0;
+}
+
+__override uint8_t board_get_usb_pd_port_count(void)
+{
+	CPRINTSUSB("%s is called by task_id:%d", __func__, task_get_current());
+
+	if (board_detect_ps8815_db())
+		return CONFIG_USB_PD_PORT_MAX_COUNT;
+
+	return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
+}
diff --git a/board/taniks/usbc_config.h b/board/taniks/usbc_config.h
new file mode 100644
index 0000000000..c9b8a8d71c
--- /dev/null
+++ b/board/taniks/usbc_config.h
@@ -0,0 +1,17 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Taniks board-specific USB-C configuration */
+
+#ifndef __CROS_EC_USBC_CONFIG_H
+#define __CROS_EC_USBC_CONFIG_H
+
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
+
+void config_usb_db_type(void);
+
+#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/taniks/vif_override.xml b/board/taniks/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/taniks/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/taranza/board.c b/board/taranza/board.c
new file mode 100644
index 0000000000..5cd32395a3
--- /dev/null
+++ b/board/taranza/board.c
@@ -0,0 +1,388 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Taranza board-specific configuration */
+
+#include "adc_chip.h"
+#include "board.h"
+#include "button.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "driver/ppc/syv682x_public.h"
+#include "driver/tcpm/it83xx_pd.h"
+#include "driver/temp_sensor/thermistor.h"
+#include "driver/usb_mux/it5205.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "intc.h"
+#include "power.h"
+#include "power_button.h"
+#include "switch.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "tcpm/tcpci.h"
+#include "temp_sensor.h"
+#include "uart.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_ppc.h"
+
+#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	[ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH0 },
+	[ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH2 },
+	[ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH3 },
+	[ADC_VBUS] = { .name = "VBUS", /* 113/1113 voltage divider */
+		       .factor_mul = ADC_MAX_MVOLT * 1113,
+		       .factor_div = (ADC_READ_MAX + 1) * 113,
+		       .shift = 0,
+		       .channel = CHIP_ADC_CH4 },
+	[ADC_TEMP_SENSOR_3] = { .name = "TEMP_SENSOR3",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH13 },
+	[ADC_PPVAR_PWR_IN_IMON] = { .name = "ADC_PPVAR_PWR_IN_IMON",
+				    .factor_mul = ADC_MAX_MVOLT,
+				    .factor_div = ADC_READ_MAX + 1,
+				    .shift = 0,
+				    .channel = CHIP_ADC_CH15 },
+	[ADC_SNS_PPVAR_PWR_IN] = { .name = "ADC_SNS_PPVAR_PWR_IN",
+				   .factor_mul = ADC_MAX_MVOLT,
+				   .factor_div = ADC_READ_MAX + 1,
+				   .shift = 0,
+				   .channel = CHIP_ADC_CH16 },
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* TCPCs */
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_EMBEDDED,
+		.drv = &it83xx_tcpm_drv,
+	},
+};
+
+/* PPCs */
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.frs_en = GPIO_EC_USB_C0_FRS_EN,
+		.drv = &syv682x_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
+
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/* USB Muxes */
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+			},
+	},
+};
+
+/* USB-A ports */
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_USB_A0_VBUS, GPIO_EN_USB_A1_VBUS, GPIO_EN_USB_A2_VBUS,
+	GPIO_EN_USB_A3_VBUS, GPIO_EN_USB_A4_VBUS,
+};
+
+/* Thermistors */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "SoC power",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+void board_init(void)
+{
+	gpio_enable_interrupt(GPIO_BJ_ADP_PRESENT);
+
+	/* Enable PPC interrupt */
+	gpio_enable_interrupt(GPIO_USB_C0_FAULT_L);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * Nothing to do.  TCPC C0 is internal.
+	 */
+}
+
+__override void board_power_5v_enable(int enable)
+{
+	/*
+	 * Nothing to do. 5V should always be enabled while in Z1 or above.
+	 */
+}
+
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
+{
+	int insufficient_power =
+		(charge_ma * charge_mv) <
+		(CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON * 1000);
+	/* TODO(b/259467280) blink LED on error */
+	(void)insufficient_power;
+}
+
+int board_vbus_source_enabled(int port)
+{
+	if (port != CHARGE_PORT_TYPEC0)
+		return 0;
+
+	return ppc_is_sourcing_vbus(port);
+}
+
+/* Vconn control for integrated ITE TCPC */
+void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
+{
+	/*
+	 * We ignore the cc_pin and PPC vconn because polarity and PPC vconn
+	 * should already be set correctly in the PPC driver via the pd
+	 * state machine.
+	 */
+}
+
+/******************************************************************************/
+/*
+ * Since taranza has no battery, it must source all of its power from either
+ * USB-C or the barrel jack (preferred). Fizz operates in continuous safe
+ * mode (charge_manager_leave_safe_mode() will never be called), which
+ * modifies port selection as follows:
+ *
+ * - Dual-role / dedicated capability of the port partner is ignored.
+ * - Charge ceiling on PD voltage transition is ignored.
+ * - CHARGE_PORT_NONE will never be selected.
+ */
+
+/* List of BJ adapters */
+enum bj_adapter {
+	BJ_NONE,
+	BJ_65W_19V,
+};
+
+/* Barrel-jack power adapter ratings. */
+static const struct charge_port_info bj_adapters[] = {
+	[BJ_NONE] = { .current = 0, .voltage = 0 },
+	[BJ_65W_19V] = { .current = 3420, .voltage = 19000 },
+};
+#define BJ_ADP_RATING_DEFAULT BJ_65W_19V /* BJ power ratings default */
+#define ADP_DEBOUNCE_MS 1000 /* Debounce time for BJ plug/unplug */
+
+/* Debounced connection state of the barrel jack */
+static int8_t bj_adp_connected = -1;
+static void adp_connect_deferred(void)
+{
+	const struct charge_port_info *pi;
+	int connected = gpio_get_level(GPIO_BJ_ADP_PRESENT);
+
+	/* Debounce */
+	if (connected == bj_adp_connected)
+		return;
+
+	if (connected) {
+		pi = &bj_adapters[BJ_ADP_RATING_DEFAULT];
+	} else {
+		/* No barrel-jack, zero out this power supply */
+		pi = &bj_adapters[BJ_NONE];
+	}
+	/* This will result in a call to board_set_active_charge_port */
+	charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED,
+				     DEDICATED_CHARGE_PORT, pi);
+	bj_adp_connected = connected;
+}
+DECLARE_DEFERRED(adp_connect_deferred);
+
+/* IRQ for BJ plug/unplug. It shouldn't be called if BJ is the power source. */
+void adp_connect_interrupt(enum gpio_signal signal)
+{
+	hook_call_deferred(&adp_connect_deferred_data, ADP_DEBOUNCE_MS * MSEC);
+}
+
+int board_set_active_charge_port(int port)
+{
+	const int active_port = charge_manager_get_active_charge_port();
+
+	CPRINTUSB("Requested charge port change to %d", port);
+
+	if (port < 0 || CHARGE_PORT_COUNT <= port)
+		return EC_ERROR_INVAL;
+
+	if (port == active_port)
+		return EC_SUCCESS;
+
+	/* Don't sink from a source port */
+	if (board_vbus_source_enabled(port))
+		return EC_ERROR_INVAL;
+
+	if (!chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
+		int bj_requested;
+
+		if (charge_manager_get_active_charge_port() != CHARGE_PORT_NONE)
+			/* Change is only permitted while the system is off */
+			return EC_ERROR_INVAL;
+
+		/*
+		 * Current setting is no charge port but the AP is on, so the
+		 * charge manager is out of sync (probably because we're
+		 * reinitializing after sysjump). Reject requests that aren't
+		 * in sync with our outputs.
+		 */
+		bj_requested = port == CHARGE_PORT_BARRELJACK;
+		if (bj_adp_connected != bj_requested)
+			return EC_ERROR_INVAL;
+	}
+
+	CPRINTUSB("New charger p%d", port);
+
+	switch (port) {
+	case CHARGE_PORT_TYPEC0:
+		ppc_vbus_sink_enable(USBC_PORT_C0, 1);
+		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_OD, 0);
+		break;
+	case CHARGE_PORT_BARRELJACK:
+		/* Make sure BJ adapter is sourcing power */
+		if (!gpio_get_level(GPIO_BJ_ADP_PRESENT))
+			return EC_ERROR_INVAL;
+		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_OD, 1);
+		ppc_vbus_sink_enable(USBC_PORT_C0, 1);
+		break;
+	default:
+		return EC_ERROR_INVAL;
+	}
+
+	return EC_SUCCESS;
+}
+
+static void board_charge_manager_init(void)
+{
+	enum charge_port port;
+
+	/*
+	 * Initialize all charge suppliers to 0. The charge manager waits until
+	 * all ports have reported in before doing anything.
+	 */
+	for (int i = 0; i < CHARGE_PORT_COUNT; i++) {
+		for (int j = 0; j < CHARGE_SUPPLIER_COUNT; j++)
+			charge_manager_update_charge(j, i, NULL);
+	}
+
+	port = gpio_get_level(GPIO_BJ_ADP_PRESENT) ? CHARGE_PORT_BARRELJACK :
+						     CHARGE_PORT_TYPEC0;
+	CPRINTUSB("Power source is p%d (%s)", port,
+		  port == CHARGE_PORT_TYPEC0 ? "USB-C" : "BJ");
+
+	/* Initialize the power source supplier */
+	switch (port) {
+	case CHARGE_PORT_TYPEC0:
+		typec_set_input_current_limit(port, 3000, 5000);
+		break;
+	case CHARGE_PORT_BARRELJACK:
+		charge_manager_update_charge(
+			CHARGE_SUPPLIER_DEDICATED, DEDICATED_CHARGE_PORT,
+			&bj_adapters[BJ_ADP_RATING_DEFAULT]);
+		break;
+	}
+
+	/* Report charge state from the barrel jack. */
+	adp_connect_deferred();
+}
+DECLARE_HOOK(HOOK_INIT, board_charge_manager_init,
+	     HOOK_PRIO_INIT_CHARGE_MANAGER + 1);
+
+__override int extpower_is_present(void)
+{
+	/*
+	 * There's no battery, so running this method implies we have power.
+	 */
+	return 1;
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	if (signal == GPIO_USB_C0_FAULT_L)
+		syv682x_interrupt(USBC_PORT_C0);
+}
+
+/* I2C Ports */
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_EEPROM_SCL,
+	  .sda = GPIO_EC_I2C_EEPROM_SDA },
+
+	{ .name = "hdmi2_edid",
+	  .port = I2C_PORT_HDMI2_EDID,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_HDMI2_EDID_SCL,
+	  .sda = GPIO_EC_I2C_HDMI2_EDID_SDA },
+
+	{ .name = "usbc0",
+	  .port = I2C_PORT_USB_C0,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C0_SCL,
+	  .sda = GPIO_EC_I2C_USB_C0_SDA },
+
+	{ .name = "hdmi2_src_ddc",
+	  .port = I2C_PORT_HDMI2_SRC_DDC,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_HDMI2_SRC_DDC_SCL,
+	  .sda = GPIO_EC_I2C_HDMI2_SRC_DDC_SDA },
+
+	{ .name = "hdmi1_edid",
+	  .port = I2C_PORT_HDMI1_EDID,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_HDMI1_EDID_SCL,
+	  .sda = GPIO_EC_I2C_HDMI1_EDID_SDA },
+
+	{ .name = "hdmi1_src_ddc",
+	  .port = I2C_PORT_HDMI1_SRC_DDC,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_HDMI1_SRC_DDC_SCL,
+	  .sda = GPIO_EC_I2C_HDMI1_SRC_DDC_SDA },
+};
+
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
diff --git a/board/taranza/board.h b/board/taranza/board.h
new file mode 100644
index 0000000000..8dc03d5a23
--- /dev/null
+++ b/board/taranza/board.h
@@ -0,0 +1,153 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Taranza board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* Select Baseboard features */
+#define VARIANT_DEDEDE_EC_IT8320
+#include "baseboard.h"
+
+/* System unlocked in early development */
+#define CONFIG_SYSTEM_UNLOCKED
+
+#define CONFIG_CMD_CHARGER_DUMP
+
+/* I2C Bus Configuration */
+#define I2C_PORT_HDMI2_EDID IT83XX_I2C_CH_B
+#undef I2C_PORT_USB_C0
+#define I2C_PORT_USB_C0 IT83XX_I2C_CH_C
+#define I2C_PORT_HDMI2_SRC_DDC IT83XX_I2C_CH_D
+#define I2C_PORT_HDMI1_EDID IT83XX_I2C_CH_E
+#define I2C_PORT_HDMI1_SRC_DDC IT83XX_I2C_CH_F
+
+/* Power */
+#undef CONFIG_CHARGER
+#undef CONFIG_CHARGER_DISCHARGE_ON_AC
+#undef CONFIG_USB_PD_VBUS_MEASURE_CHARGER
+#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 16000
+#define PD_MAX_VOLTAGE_MV 20000
+#undef PD_MAX_CURRENT_MA
+#define PD_MAX_CURRENT_MA 3250
+#undef PD_MAX_POWER_MW
+#define PD_MAX_POWER_MW 65000
+#define CONFIG_USB_PD_VBUS_DETECT_GPIO
+
+/* Override macro for C0 only */
+#define PORT_TO_HPD(port) (GPIO_USB_C0_DP_HPD)
+
+/* Power: Dedicated barreljack charger port */
+#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT
+#define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1
+#define DEDICATED_CHARGE_PORT 1
+
+/* USB Type-C */
+#undef CONFIG_USB_CHARGER
+#undef CONFIG_USB_MUX_PI3USB31532
+
+/* TCPC */
+#define CONFIG_USB_PD_PORT_MAX_COUNT 1
+#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0: ITE EC TCPC */
+#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1
+
+/* PPC */
+#define CONFIG_USB_PD_DISCHARGE_PPC
+#define CONFIG_USB_PD_VBUS_DETECT_PPC
+#define CONFIG_USBC_PPC
+#define CONFIG_USBC_PPC_SYV682X
+
+/* USB Mux and Retimer */
+#define CONFIG_USB_MUX_IT5205 /* C0: ITE Mux */
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */
+
+/* USB Type A Features */
+#define CONFIG_USB_PORT_POWER_DUMB
+#define USB_PORT_COUNT 5 /* Type A ports */
+
+/* No battery */
+#undef CONFIG_BATTERY_CUT_OFF
+#undef CONFIG_BATTERY_PRESENT_GPIO
+#undef CONFIG_BATTERY_REQUESTS_NIL_WHEN_DEAD
+#undef CONFIG_BATTERY_REVIVE_DISCONNECT
+#undef CONFIG_BATTERY_SMART
+
+/* Thermistors */
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_THERMISTOR
+#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
+
+/* Buttons */
+#define CONFIG_DEDICATED_RECOVERY_BUTTON
+#define CONFIG_DEDICATED_RECOVERY_BUTTON_2
+#define CONFIG_DEDICATED_RECOVERY_BUTTON_FLAGS BUTTON_FLAG_ACTIVE_HIGH
+#define CONFIG_POWER_BUTTON
+#define CONFIG_POWER_BUTTON_IGNORE_LID
+#define CONFIG_POWER_BUTTON_X86
+#define CONFIG_EMULATED_SYSRQ
+
+/* No Keyboard */
+#undef CONFIG_KEYBOARD_COL2_INVERTED
+#undef CONFIG_KEYBOARD_PROTOCOL_8042
+#undef CONFIG_CMD_KEYBOARD
+#undef CONFIG_KEYBOARD_BOOT_KEYS
+#undef CONFIG_KEYBOARD_RUNTIME_KEYS
+
+/* No backlight */
+#undef CONFIG_BACKLIGHT_LID
+#undef GPIO_ENABLE_BACKLIGHT
+
+/* Unused features - Misc */
+#undef CONFIG_HIBERNATE
+#undef CONFIG_VOLUME_BUTTONS
+#undef CONFIG_LID_SWITCH
+#undef CONFIG_TABLET_MODE
+#undef CONFIG_TABLET_MODE_SWITCH
+#undef CONFIG_GMR_TABLET_MODE
+#undef GPIO_TABLET_MODE_L
+
+/* Unused GPIOs */
+#undef GPIO_USB_C1_DP_HPD
+
+/* Pin renaming */
+#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_OD
+#define GPIO_RECOVERY_L_2 GPIO_H1_EC_RECOVERY_BTN_ODL
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum charge_port {
+	CHARGE_PORT_TYPEC0,
+	CHARGE_PORT_BARRELJACK,
+};
+
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_COUNT };
+
+/* ADC channels */
+enum adc_channel {
+	ADC_VSNS_PP3300_A, /* ADC0 */
+	ADC_TEMP_SENSOR_1, /* ADC2 */
+	ADC_TEMP_SENSOR_2, /* ADC3 */
+	ADC_VBUS, /* ADC4 */
+	ADC_TEMP_SENSOR_3, /* ADC13 */
+	ADC_PPVAR_PWR_IN_IMON, /* ADC15 */
+	ADC_SNS_PPVAR_PWR_IN, /* ADC16 */
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1,
+	TEMP_SENSOR_2,
+	TEMP_SENSOR_3,
+	TEMP_SENSOR_COUNT
+};
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/taranza/build.mk b/board/taranza/build.mk
new file mode 100644
index 0000000000..9bbf403060
--- /dev/null
+++ b/board/taranza/build.mk
@@ -0,0 +1,15 @@
+# -*- makefile -*-
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=it83xx
+CHIP_FAMILY:=it8320
+CHIP_VARIANT:=it8320dx
+BASEBOARD:=dedede
+BOARD:=taranza
+
+board-y=board.o led.o usb_pd_policy.o
diff --git a/board/taranza/ec.tasklist b/board/taranza/ec.tasklist
new file mode 100644
index 0000000000..4aad682d14
--- /dev/null
+++ b/board/taranza/ec.tasklist
@@ -0,0 +1,16 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE)
diff --git a/board/taranza/gpio.inc b/board/taranza/gpio.inc
new file mode 100644
index 0000000000..6ec6b94646
--- /dev/null
+++ b/board/taranza/gpio.inc
@@ -0,0 +1,175 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+/* Power State interrupts */
+GPIO_INT(SLP_S4_L, PIN(I, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L, PIN(H, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(SLP_S0_L, PIN(E, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L, PIN(G, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID0, PIN(D, 0), GPIO_INT_BOTH | GPIO_SEL_1P8V,
+	 power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID1, PIN(K, 1), GPIO_INT_BOTH | GPIO_SEL_1P8V,
+	 power_signal_interrupt)
+GPIO_INT(RSMRST_PWRGD_L, PIN(E, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(CPU_C10_GATE_L, PIN(G, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_DRAM_OD, PIN(D, 3), GPIO_INT_BOTH,
+	 baseboard_all_sys_pgood_interrupt)
+GPIO_INT(PG_PP1050_ST_OD, PIN(L, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(EC_VSNS_PP3300_S5, PIN(I, 0), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_VCCIO_EXT_OD, PIN(D, 7), GPIO_INT_BOTH,
+	 baseboard_all_sys_pgood_interrupt)
+GPIO_INT(ESPI_RESET_L, PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V,
+	 espi_reset_pin_asserted_interrupt)
+
+GPIO_INT(H1_EC_PWR_BTN_ODL, PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP,
+	 power_button_interrupt)
+#ifdef CONFIG_LOW_POWER_IDLE
+/* Used to wake up the EC from Deep Doze mode when writing to console */
+GPIO_INT(UART1_RX, PIN(B, 0), GPIO_INT_BOTH,
+	 uart_deepsleep_interrupt) /* UART_DBG_TX_EC_RX
+				    */
+#endif
+
+/* Other interrupts */
+GPIO_INT(EC_WP_OD, PIN(A, 6), GPIO_INT_BOTH, switch_interrupt)
+/* Directly connected recovery button */
+GPIO_INT(EC_RECOVERY_BTN_OD, PIN(K, 7), GPIO_INT_BOTH, button_interrupt)
+/* Recovery button input from H1 */
+GPIO_INT(H1_EC_RECOVERY_BTN_ODL, PIN(K, 4), GPIO_INT_BOTH, button_interrupt)
+GPIO_INT(BJ_ADP_PRESENT, PIN(A, 7), GPIO_INT_BOTH, adp_connect_interrupt)
+GPIO_INT(USB_C0_FAULT_L, PIN(K, 0), GPIO_INT_FALLING, ppc_interrupt)
+
+/* Power sequence GPIOs */
+GPIO(EC_AP_PSYS, PIN(J, 2), GPIO_OUT_LOW)
+GPIO(EC_AP_RTCRST, PIN(K, 2), GPIO_OUT_LOW)
+GPIO(EC_AP_PWR_BTN_ODL, PIN(B, 6), GPIO_ODR_HIGH)
+GPIO(EC_AP_DPWROK, PIN(L, 7), GPIO_OUT_LOW)
+GPIO(EC_AP_RSMRST_L, PIN(H, 0), GPIO_OUT_LOW)
+GPIO(EC_AP_WAKE_ODL, PIN(D, 5), GPIO_ODR_HIGH)
+GPIO(SYS_RST_ODL, PIN(D, 1), GPIO_ODR_HIGH)
+GPIO(EC_AP_SYS_PWROK, PIN(F, 2), GPIO_OUT_LOW)
+GPIO(PG_PP5000_U_OD, PIN(J, 0), GPIO_INPUT)
+GPIO(EN_PP5000_U, PIN(K, 5), GPIO_OUT_HIGH)
+GPIO(PG_PP3300_A, PIN(B, 5), GPIO_INPUT)
+GPIO(EN_PP3300_A, PIN(C, 5), GPIO_OUT_LOW)
+GPIO(EC_AP_PCH_PWROK_OD, PIN(D, 6), GPIO_ODR_LOW)
+/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
+GPIO(EN_VCCST, PIN(D, 4), GPIO_INPUT)
+GPIO(EN_VCCIO_EXT, PIN(B, 2), GPIO_OUT_LOW)
+GPIO(EC_PROCHOT_ODL, PIN(I, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(EC_AP_VCCST_PWRGD_OD, PIN(E, 5), GPIO_ODR_LOW)
+GPIO(ALL_SYS_PWRGD, PIN(B, 7), GPIO_OUT_LOW)
+GPIO(EN_PPVAR_BJ_ADP_OD, PIN(E, 3), GPIO_ODR_HIGH)
+GPIO(ACK_PPVAR_BJ_ADP_ODL, PIN(A, 0), GPIO_INPUT)
+
+/* Required for icelake chipset code, but implemented through other means for
+ * dedede */
+UNIMPLEMENTED(AC_PRESENT)
+UNIMPLEMENTED(PG_EC_DSW_PWROK)
+UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
+
+/* Required for dedede baseboard but not used in taranza */
+UNIMPLEMENTED(USB_C0_INT_ODL)
+UNIMPLEMENTED(EN_SLP_Z)
+UNIMPLEMENTED(EC_BATTERY_PRES_ODL)
+
+/* I2C pins - Alternate function below configures I2C module on these pins */
+GPIO(EC_I2C_EEPROM_SCL, PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SDA, PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SCL, PIN(F, 6), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SDA, PIN(F, 7), GPIO_INPUT)
+GPIO(EC_I2C_HDMI1_EDID_SCL, PIN(E, 0), GPIO_INPUT)
+GPIO(EC_I2C_HDMI1_EDID_SDA, PIN(E, 7), GPIO_INPUT)
+GPIO(EC_I2C_HDMI2_EDID_SCL, PIN(C, 1), GPIO_INPUT)
+GPIO(EC_I2C_HDMI2_EDID_SDA, PIN(C, 2), GPIO_INPUT)
+GPIO(EC_I2C_HDMI1_SRC_DDC_SCL, PIN(A, 4), GPIO_INPUT)
+GPIO(EC_I2C_HDMI1_SRC_DDC_SDA, PIN(A, 5), GPIO_INPUT)
+GPIO(EC_I2C_HDMI2_SRC_DDC_SCL, PIN(H, 1), GPIO_INPUT)
+GPIO(EC_I2C_HDMI2_SRC_DDC_SDA, PIN(H, 2), GPIO_INPUT)
+
+/* USB pins */
+GPIO(EC_AP_USB_C0_HPD, PIN(L, 4), GPIO_OUT_LOW)
+GPIO(EN_USB_A0_VBUS, PIN(L, 6), GPIO_OUT_LOW)
+GPIO(EN_USB_A1_VBUS, PIN(C, 6), GPIO_OUT_LOW)
+GPIO(EN_USB_A2_VBUS, PIN(C, 4), GPIO_OUT_LOW)
+GPIO(EN_USB_A3_VBUS, PIN(J, 5), GPIO_OUT_LOW)
+GPIO(EN_USB_A4_VBUS, PIN(J, 4), GPIO_OUT_LOW)
+GPIO(EC_USB_C0_FRS_EN, PIN(K, 6), GPIO_OUT_LOW)
+GPIO(USB_C0_SBU_MUX_FAULT, PIN(I, 7), GPIO_INPUT)
+
+/* MKBP event synchronization */
+/* TODO(b/257833880) Check whether this pin is needed */
+GPIO(EC_AP_MKBP_INT_L, PIN(L, 5), GPIO_ODR_HIGH)
+
+/* HDMI */
+GPIO(HDMI1_CEC, PIN(F, 0), GPIO_OUT_LOW)
+GPIO(HDMI2_CEC_IN, PIN(J, 3), GPIO_INPUT)
+GPIO(HDMI2_CEC, PIN(F, 1), GPIO_OUT_LOW)
+GPIO(HDMI1_SRC_HPD, PIN(F, 3), GPIO_INPUT)
+GPIO(HDMI2_SRC_HPD, PIN(KSO_L, 3), GPIO_INPUT)
+GPIO(EC_HDMI1_SRC_HPD_OUT, PIN(I, 6), GPIO_OUT_LOW)
+GPIO(EC_HDMI2_SRC_HPD_OUT, PIN(KSO_L, 4), GPIO_OUT_LOW)
+GPIO(HDMI1_EDID_SEL, PIN(J, 1), GPIO_OUT_LOW)
+GPIO(HDMI2_EDID_SEL, PIN(KSO_L, 5), GPIO_OUT_LOW)
+GPIO(EDID_BTN_ODL, PIN(C, 3), GPIO_INPUT)
+GPIO(EC_EN_PP5000_HDMI1, PIN(KSO_L, 6), GPIO_OUT_LOW)
+GPIO(EC_EN_PP5000_HDMI2, PIN(KSO_L, 7), GPIO_OUT_LOW)
+
+/* Misc */
+GPIO(EC_ENTERING_RW, PIN(C, 7), GPIO_OUT_LOW)
+GPIO(CCD_MODE_ODL, PIN(H, 5), GPIO_ODR_HIGH)
+GPIO(ECH1_PACKET_MODE, PIN(C, 0), GPIO_OUT_LOW)
+GPIO(EN_RS232_X, PIN(E, 6), GPIO_OUT_LOW)
+GPIO(UART0_RX, PIN(B, 1), GPIO_OUT_LOW) /* UART_EC_TX_DBG_RX */
+
+/* LED */
+GPIO(LED_W_ODL, PIN(A, 2), GPIO_OUT_HIGH)
+
+/* NC pins, enable internal pull-down to avoid floating state. */
+GPIO(GPIOG0_NC, PIN(G, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG3_NC, PIN(G, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG4_NC, PIN(G, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG5_NC, PIN(G, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG6_NC, PIN(G, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOG7_NC, PIN(G, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOH4_NC, PIN(H, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOH6_NC, PIN(H, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOI4_NC, PIN(I, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOJ6_NC, PIN(J, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOK3_NC, PIN(K, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOM6_NC, PIN(M, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOA1_NC, PIN(A, 1), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOA3_NC, PIN(A, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+
+/* Alternate functions GPIO definitions */
+/* UART */
+ALTERNATE(PIN_MASK(B, BIT(0) | BIT(1)), 0, MODULE_UART, 0) /* UART for debug */
+
+/* I2C */
+ALTERNATE(PIN_MASK(B, BIT(3) | BIT(4)), 0, MODULE_I2C, 0) /* I2C0 - EEPROM */
+ALTERNATE(PIN_MASK(C, BIT(1) | BIT(2)), 0, MODULE_I2C, 0) /* I2C1 - HDMI2_EDID
+							   */
+ALTERNATE(PIN_MASK(F, BIT(6) | BIT(7)), 0, MODULE_I2C, 0) /* I2C2 - USB_C0 */
+ALTERNATE(PIN_MASK(E, BIT(0) | BIT(7)), 0, MODULE_I2C, 0) /* I2C4 - HDMI1_EDID
+							   */
+ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), 0, MODULE_I2C, 0) /* I2C5 -
+							     HDMI1_SRC_DDC */
+ALTERNATE(PIN_MASK(H, BIT(1) | BIT(2)), 0, MODULE_I2C, 0) /* I2C3 -
+							     HDMI2_SRC_DDC */
+
+/* ADC */
+/* ADC2: TEMP_SENSOR_1, ADC3: TEMP_SENSOR_2, ADC4: VBUS */
+ALTERNATE(PIN_MASK(I, BIT(2) | BIT(3) | BIT(4)), 0, MODULE_ADC, 0)
+/*
+ * ADC13: TEMP_SENSOR_3
+ * ADC15: ANALOG_PPVAR_PWR_IN_IMON
+ * ADC16: SNS_PPVAR_PWR_IN
+ */
+ALTERNATE(PIN_MASK(L, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0)
diff --git a/board/taranza/led.c b/board/taranza/led.c
new file mode 100644
index 0000000000..e37e36d6fa
--- /dev/null
+++ b/board/taranza/led.c
@@ -0,0 +1,70 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Taranza specific LED settings. */
+
+#include "chipset.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "led_common.h"
+
+#define LED_ON_LVL 0
+#define LED_OFF_LVL 1
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_POWER_LED,
+};
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+enum led_color {
+	LED_OFF = 0,
+	LED_GREEN,
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
+};
+
+static int led_set_color_power(enum led_color color)
+{
+	switch (color) {
+	case LED_GREEN:
+		gpio_set_level(GPIO_LED_W_ODL, LED_ON_LVL);
+		break;
+	case LED_OFF:
+		gpio_set_level(GPIO_LED_W_ODL, LED_OFF_LVL);
+		break;
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+	return EC_SUCCESS;
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	brightness_range[EC_LED_COLOR_GREEN] = 1;
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (brightness[EC_LED_COLOR_GREEN] != 0)
+		led_set_color_power(LED_GREEN);
+	else
+		led_set_color_power(LED_OFF);
+
+	return EC_SUCCESS;
+}
+
+/* Called by hook task every TICK */
+static void led_tick(void)
+{
+	if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		return;
+
+	if (chipset_in_state(CHIPSET_STATE_ON))
+		led_set_color_power(LED_GREEN);
+	else
+		led_set_color_power(LED_OFF);
+}
+DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
diff --git a/board/taranza/usb_pd_policy.c b/board/taranza/usb_pd_policy.c
new file mode 100644
index 0000000000..58bc80170f
--- /dev/null
+++ b/board/taranza/usb_pd_policy.c
@@ -0,0 +1,72 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "charger.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "gpio.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+int pd_check_vconn_swap(int port)
+{
+	/* Allow VCONN swaps if the AP is on */
+	return gpio_get_level(GPIO_EN_PP5000_U);
+}
+
+void pd_power_supply_reset(int port)
+{
+	int prev_en;
+
+	if (port < 0 || port >= board_get_usb_pd_port_count())
+		return;
+
+	prev_en = ppc_is_sourcing_vbus(port);
+
+	/* Disable VBUS source */
+	ppc_vbus_source_enable(port, 0);
+
+	/* Enable discharge if we were previously sourcing 5V */
+	if (prev_en)
+		pd_set_vbus_discharge(port, 1);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	/* Disable charging */
+	rv = ppc_vbus_sink_enable(port, 0);
+	if (rv)
+		return rv;
+
+	pd_set_vbus_discharge(port, 0);
+
+	/* Enable VBUS source */
+	rv = ppc_vbus_source_enable(port, 1);
+	if (rv)
+		return rv;
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+__override int pd_snk_is_vbus_provided(int port)
+{
+	if (port != CHARGE_PORT_TYPEC0)
+		return 0;
+
+	return ppc_is_vbus_present(port);
+}
diff --git a/board/taranza/vif_override.xml b/board/taranza/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/taranza/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/terrador/battery.c b/board/terrador/battery.c
index d129ede528..caaf3d6d55 100644
--- a/board/terrador/battery.c
+++ b/board/terrador/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/terrador/board.c b/board/terrador/board.c
index 22a9b36eaa..a7356f53f5 100644
--- a/board/terrador/board.c
+++ b/board/terrador/board.c
@@ -1,23 +1,22 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Volteer board-specific configuration */
-#include "bb_retimer.h"
-#include "button.h"
-#include "common.h"
 #include "accelgyro.h"
+#include "button.h"
 #include "cbi_ec_fw_config.h"
+#include "common.h"
 #include "driver/accel_bma2x2.h"
 #include "driver/accelgyro_bmi260.h"
-#include "driver/bc12/pi3usb9201.h"
 #include "driver/als_tcs3400.h"
+#include "driver/bc12/pi3usb9201.h"
 #include "driver/ppc/syv682x.h"
+#include "driver/retimer/bb_retimer_public.h"
+#include "driver/sync.h"
 #include "driver/tcpm/tcpci.h"
 #include "driver/tcpm/tusb422.h"
-#include "driver/retimer/bb_retimer.h"
-#include "driver/sync.h"
 #include "extpower.h"
 #include "fan.h"
 #include "fan_chip.h"
@@ -31,8 +30,8 @@
 #include "pwm_chip.h"
 #include "switch.h"
 #include "system.h"
-#include "task.h"
 #include "tablet_mode.h"
+#include "task.h"
 #include "throttle_ap.h"
 #include "uart.h"
 #include "usb_mux.h"
@@ -42,12 +41,13 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#include "gpio_list.h" /* Must come after other header files. */
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 /* Keyboard scan setting */
-struct keyboard_scan_config keyscan_config = {
+__override struct keyboard_scan_config keyscan_config = {
 	/* Increase from 50 us, because KSO_02 passes through the H1. */
 	.output_settle_us = 80,
 	/* Other values should be the same as the default configuration. */
@@ -72,7 +72,6 @@ union volteer_cbi_fw_config fw_config_defaults = {
 
 static void board_init(void)
 {
-
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
@@ -171,17 +170,22 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
  * 130 C.  However, sensor is located next to DDR, so we need to use the lower
  * DDR temperature limit (85 C)
  */
-const static struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(35),
-	.temp_fan_max = C_TO_K(50),
-};
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+		}, \
+		.temp_fan_off = C_TO_K(35), \
+		.temp_fan_max = C_TO_K(50), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 
 /*
  * Inductor limits - used for both charger and PP3300 regulator
@@ -194,24 +198,29 @@ const static struct ec_thermal_config thermal_cpu = {
  * Inductors: limit of 125c
  * PCB: limit is 80c
  */
-const static struct ec_thermal_config thermal_inductor = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(55),
-};
-
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_INDUCTOR         \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+		}, \
+		.temp_fan_off = C_TO_K(40), \
+		.temp_fan_max = C_TO_K(55), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_inductor =
+	THERMAL_INDUCTOR;
 
 struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_CHARGER]			= thermal_inductor,
-	[TEMP_SENSOR_2_PP3300_REGULATOR]	= thermal_inductor,
-	[TEMP_SENSOR_3_DDR_SOC]			= thermal_cpu,
-	[TEMP_SENSOR_4_FAN]			= thermal_cpu,
+	[TEMP_SENSOR_1_CHARGER] = THERMAL_INDUCTOR,
+	[TEMP_SENSOR_2_PP3300_REGULATOR] = THERMAL_INDUCTOR,
+	[TEMP_SENSOR_3_DDR_SOC] = THERMAL_CPU,
+	[TEMP_SENSOR_4_FAN] = THERMAL_CPU,
 };
 BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
 
@@ -235,11 +244,15 @@ void board_reset_pd_mcu(void)
 }
 
 /* USBC mux configuration - Tiger Lake includes internal mux */
-struct usb_mux usbc0_usb4_mb_retimer = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &bb_usb_retimer,
-	.i2c_port = I2C_PORT_USB_0_MIX,
-	.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
+struct usb_mux_chain usbc0_usb4_mb_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_0_MIX,
+			.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
+		},
 };
 /*****************************************************************************
  * USB-C MUX/Retimer dynamic configuration.
@@ -248,7 +261,7 @@ static void setup_mux(void)
 {
 	CPRINTS("C0 supports bb-retimer");
 	/* USB-C port 0 have a retimer */
-	usb_muxes[USBC_PORT_C0].next_mux = &usbc0_usb4_mb_retimer;
+	usb_muxes[USBC_PORT_C0].next = &usbc0_usb4_mb_retimer;
 }
 
 __override void board_cbi_init(void)
@@ -260,7 +273,6 @@ __override void board_cbi_init(void)
 	/* Reassign USB_C0_RT_RST_ODL */
 	bb_controls[USBC_PORT_C0].usb_ls_en_gpio = GPIO_USB_C0_LS_EN;
 	bb_controls[USBC_PORT_C0].retimer_rst_gpio = GPIO_USB_C0_RT_RST_ODL;
-
 }
 
 /******************************************************************************/
@@ -290,6 +302,7 @@ void ppc_interrupt(enum gpio_signal signal)
 		break;
 	case GPIO_USB_C1_PPC_INT_ODL:
 		syv682x_interrupt(USBC_PORT_C1);
+		break;
 	default:
 		break;
 	}
@@ -319,7 +332,6 @@ struct tcpc_config_t tcpc_config[] = {
 			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
 		},
 		.drv = &tusb422_tcpm_drv,
-		.usb23 = USBC_PORT_0_USB2_NUM | (USBC_PORT_0_USB3_NUM << 4),
 	},
 	[USBC_PORT_C1] = {
 		.bus_type = EC_BUS_TYPE_I2C,
@@ -328,7 +340,6 @@ struct tcpc_config_t tcpc_config[] = {
 			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
 		},
 		.drv = &tusb422_tcpm_drv,
-		.usb23 = USBC_PORT_1_USB2_NUM | (USBC_PORT_1_USB3_NUM << 4),
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
@@ -336,23 +347,31 @@ BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
 
 /******************************************************************************/
 /* USBC mux configuration - Tiger Lake includes internal mux */
-struct usb_mux usbc1_usb4_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &bb_usb_retimer,
-	.i2c_port = I2C_PORT_USB_1_MIX,
-	.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
+struct usb_mux_chain usbc1_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
-struct usb_mux usb_muxes[] = {
+struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 	},
 	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc1_usb4_db_retimer,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_1_MIX,
+			.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc1_tcss_usb_mux,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
@@ -412,3 +431,10 @@ int ppc_get_alert_status(int port)
 	else
 		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
 }
+
+/******************************************************************************/
+/* USB-A charging control */
+
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_PP5000_USBA,
+};
diff --git a/board/terrador/board.h b/board/terrador/board.h
index 16c72663de..5f3e5171a8 100644
--- a/board/terrador/board.h
+++ b/board/terrador/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,6 +11,40 @@
 /* Baseboard features */
 #include "baseboard.h"
 
+/* Free flash space */
+#define CONFIG_USB_PD_DEBUG_LEVEL 0
+#undef CONFIG_CONSOLE_CMDHELP
+#undef CONFIG_CMD_BATTFAKE
+#undef CONFIG_CMD_HASH
+#undef CONFIG_CMD_I2C_SCAN
+#define CONFIG_DEBUG_ASSERT_BRIEF
+#undef CONFIG_CONSOLE_HISTORY
+#undef CONFIG_ACCEL_SPOOF_MODE
+#undef CONFIG_USB_PD_TCPMV1_DEBUG
+#undef CONFIG_CMD_SYSLOCK
+#undef CONFIG_CMD_APTHROTTLE
+#undef CONFIG_CMD_TIMERINFO
+#undef CONFIG_CMD_MD
+#undef CONFIG_CMD_I2C_SCAN
+#undef CONFIG_CMD_I2C_XFER
+#undef CONFIG_CMD_AP_RESET_LOG
+#undef CONFIG_CMD_ADC
+#undef CONFIG_CMD_CHARGE_SUPPLIER_INFO
+#undef CONFIG_CMD_CHARGER_DUMP
+#undef CONFIG_CMD_IDLE_STATS
+#undef CONFIG_CMD_MFALLOW
+#undef CONFIG_CMD_MMAPINFO
+#undef CONFIG_CMD_SLEEPMASK
+#undef CONFIG_CMD_SLEEPMASK_SET
+#undef CONFIG_CMD_USB_PD_CABLE
+#undef CONFIG_CMD_FLASHINFO
+#undef CONFIG_CMD_FLASH_WP
+#undef CONFIG_CMD_GETTIME
+#undef CONFIG_CMD_TEMP_SENSOR
+#undef CONFIG_CMD_POWERINDEBUG
+#undef CONFIG_CMD_POWER_AVG
+#undef CONFIG_CMD_REGULATOR
+
 /* Optional features */
 #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
 
@@ -21,6 +55,9 @@
 #undef CONFIG_UART_TX_BUF_SIZE
 #define CONFIG_UART_TX_BUF_SIZE 4096
 
+/* Chipset features */
+#define CONFIG_POWER_PP5000_CONTROL
+
 /* LED defines */
 #define CONFIG_LED_PWM
 /* Although there are 2 LEDs, they are both controlled by the same lines. */
@@ -39,59 +76,48 @@
 
 /* TCS3400 ALS */
 #define CONFIG_ALS
-#define ALS_COUNT		1
+#define ALS_COUNT 1
 #define CONFIG_ALS_TCS3400
 #define CONFIG_ALS_TCS3400_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS)
 
 /* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
-	(BIT(LID_ACCEL) | BIT(CLEAR_ALS))
+#define CONFIG_ACCEL_FORCE_MODE_MASK (BIT(LID_ACCEL) | BIT(CLEAR_ALS))
 
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE		BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID		LID_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
 
 /* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
 
-/*
- * USB-C port's USB2 & USB3 mapping from schematics
- * USB2 numbering on PCH - 1 to n
- * USB3 numbering on AP - 0 to n (PMC's USB3 numbering for MUX
- * configuration is - 1 to n hence add +1)
- */
-#define USBC_PORT_0_USB2_NUM	9
-#define USBC_PORT_0_USB3_NUM	1
-#define USBC_PORT_1_USB2_NUM	4
-#define USBC_PORT_1_USB3_NUM	2
-
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
 
 /*
  * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
  * cables only support up to 60W.
  */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Enabling Thunderbolt-compatible mode */
 #define CONFIG_USB_PD_TBT_COMPAT_MODE
 
 /* Enabling USB4 mode */
 #define CONFIG_USB_PD_USB4
-#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR	0x40
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x40
+#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x40
+#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x40
 
 /* USB Type A Features */
+#define USB_PORT_COUNT 1
+#define CONFIG_USB_PORT_POWER_DUMB
 
 /* USBC PPC*/
-#define CONFIG_USBC_PPC_SYV682X		/* USBC port C0/C1 */
+#define CONFIG_USBC_PPC_SYV682X /* USBC port C0/C1 */
 
 /* BC 1.2 */
 
@@ -101,8 +127,8 @@
 #undef CONFIG_FANS
 
 /* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 
 /*
  * Macros for GPIO signals used in common code that don't match the
@@ -110,48 +136,45 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_DSW_PWROK		GPIO_EC_PCH_DSW_PWROK
-#define GPIO_PG_EC_DSW_PWROK		GPIO_DSW_PWROK
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD		GPIO_PG_EC_RSMRST_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
-#define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE_L
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_LID_OPEN GPIO_EC_LID_OPEN
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK
+#define GPIO_PG_EC_DSW_PWROK GPIO_DSW_PWROK
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
 
 /* I2C Bus Configuration */
 #define CONFIG_I2C
-#define I2C_PORT_ACCEL		I2C_PORT_SENSOR
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_0_MIX	NPCX_I2C_PORT3_0
-#define I2C_PORT_USB_1_MIX	NPCX_I2C_PORT4_1
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_0_MIX NPCX_I2C_PORT3_0
+#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT4_1
+#define I2C_PORT_POWER NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
 
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-#define CONFIG_I2C_MASTER
+#define I2C_PORT_BATTERY I2C_PORT_POWER
+#define I2C_PORT_CHARGER I2C_PORT_EEPROM
 
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+#define CONFIG_I2C_CONTROLLER
 
 #ifndef __ASSEMBLER__
 
@@ -181,11 +204,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 void board_reset_pd_mcu(void);
 
diff --git a/board/terrador/build.mk b/board/terrador/build.mk
index b78172d3cf..824bac888e 100644
--- a/board/terrador/build.mk
+++ b/board/terrador/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/terrador/ec.tasklist b/board/terrador/ec.tasklist
index 292de51cdb..c29125d517 100644
--- a/board/terrador/ec.tasklist
+++ b/board/terrador/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,6 +16,7 @@
 	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
 	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
 	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
 	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
 	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
 	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
diff --git a/board/terrador/gpio.inc b/board/terrador/gpio.inc
index b95ce51dc3..6d3c4cb720 100644
--- a/board/terrador/gpio.inc
+++ b/board/terrador/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,7 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
@@ -77,6 +77,8 @@ GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
 GPIO(EC_PCH_INT_ODL,           PIN(B, 0), GPIO_ODR_HIGH)
 
 /* USB and USBC Signals */
+GPIO(EN_PP5000_USBA,		PIN(C, 6), GPIO_OUT_LOW)	/* Enable USB-A charging - all ports */
+GPIO(USB_A_LOW_PWR_OD,		PIN(6, 6), GPIO_ODR_LOW)	/* Don't limit USB-A charging by default - all ports */
 
 /*
  * USB_C1 moved from GPIO32 to GPIO83 on boards with board ID >=1.
@@ -165,3 +167,6 @@ ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)  /* GPIO00 =
                                                                        GPIO01 = H1_EC_PWR_BTN_ODL
                                                                        GPIO02 = EC_RST_ODL */
 
+/* Temperature sensors */
+ALTERNATE(PIN_MASK(4, BIT(2) | BIT(4) | BIT(5)), 0, MODULE_ADC, 0) /* TEMP_SENSOR1,2,4 */
+ALTERNATE(PIN_MASK(F, BIT(1)), 0, MODULE_ADC, 0) /* TEMP_SENSOR3 */
diff --git a/board/terrador/led.c b/board/terrador/led.c
index f792eb6e3f..ce2d497ea7 100644
--- a/board/terrador/led.c
+++ b/board/terrador/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -18,17 +18,17 @@ const enum ec_led_id supported_led_ids[] = {
 };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-struct pwm_led led_color_map[] = {
-				/* Green, Red, Blue */
-	[EC_LED_COLOR_GREEN] =  {    100,   0,    0 },
-	[EC_LED_COLOR_RED] =    {      0, 100,    0 },
-	[EC_LED_COLOR_BLUE] =   {      0,   0,  100 },
+struct pwm_led_color_map led_color_map[] = {
+	/* Green, Red, Blue */
+	[EC_LED_COLOR_GREEN] = { 100, 0, 0 },
+	[EC_LED_COLOR_RED] = { 0, 100, 0 },
+	[EC_LED_COLOR_BLUE] = { 0, 0, 100 },
 	/* The green LED seems to be brighter than the others, so turn down
 	 * green from its natural level for these secondary colors.
 	 */
-	[EC_LED_COLOR_YELLOW] = {     70, 100,    0 },
-	[EC_LED_COLOR_WHITE] =  {     70, 100,  100 },
-	[EC_LED_COLOR_AMBER] =  {     20, 100,    0 },
+	[EC_LED_COLOR_YELLOW] = { 70, 100, 0 },
+	[EC_LED_COLOR_WHITE] = { 70, 100, 100 },
+	[EC_LED_COLOR_AMBER] = { 20, 100, 0 },
 };
 
 struct pwm_led pwm_leds[] = {
diff --git a/board/terrador/sensors.c b/board/terrador/sensors.c
index 9e34812131..086f323b2e 100644
--- a/board/terrador/sensors.c
+++ b/board/terrador/sensors.c
@@ -1,21 +1,22 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Volteer family-specific sensor configuration */
-#include "common.h"
 #include "accelgyro.h"
+#include "common.h"
 #include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi_common.h"
 #include "driver/accelgyro_bmi260.h"
+#include "driver/accelgyro_bmi_common.h"
 #include "driver/als_tcs3400.h"
 #include "driver/sync.h"
-#include "keyboard_scan.h"
+#include "gpio.h"
 #include "hooks.h"
 #include "i2c.h"
-#include "task.h"
+#include "keyboard_scan.h"
 #include "tablet_mode.h"
+#include "task.h"
 #include "util.h"
 
 /******************************************************************************/
@@ -84,17 +85,13 @@ static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
 };
 
 /* Rotation matrix for the lid accelerometer */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+				       { FLOAT_TO_FP(-1), 0, 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
@@ -224,22 +221,3 @@ static void baseboard_sensors_init(void)
 	gpio_enable_interrupt(GPIO_EC_IMU_INT_L);
 }
 DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_DEFAULT);
-
-#ifndef TEST_BUILD
-void lid_angle_peripheral_enable(int enable)
-{
-	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
-
-	if (enable) {
-		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
-	} else {
-		/*
-		 * Ensure that the chipset is off before disabling the keyboard.
-		 * When the chipset is on, the EC keeps the keyboard enabled and
-		 * the AP decides whether to ignore input devices or not.
-		 */
-		if (!chipset_in_s0)
-			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
-	}
-}
-#endif
diff --git a/board/terrador/vif_override.xml b/board/terrador/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/terrador/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/tglrvp_ish/board.c b/board/tglrvp_ish/board.c
index a0584410b3..5a8cbb45a9 100644
--- a/board/tglrvp_ish/board.c
+++ b/board/tglrvp_ish/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,15 +15,17 @@
 #include "power.h"
 #include "task.h"
 
-#include "gpio_list.h" /* has to be included last */
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
 
 /* I2C port map */
+#ifdef BOARD_ADL_ISH_LITE
+const struct i2c_port_t i2c_ports[] = {};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+#elif defined(BOARD_TGLRVP_ISH)
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 1000
-	},
+	{ .name = "sensor", .port = I2C_PORT_SENSOR, .kbps = 1000 },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -60,6 +62,7 @@ struct motion_sensor_t motion_sensors[] = {
 	},
 };
 const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+#endif /* BOARD_TGLRVP_ISH */
 
 int chipset_in_state(int state_mask)
 {
diff --git a/board/tglrvp_ish/board.h b/board/tglrvp_ish/board.h
index a9a3d4d544..e285014e5e 100644
--- a/board/tglrvp_ish/board.h
+++ b/board/tglrvp_ish/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,12 +8,6 @@
 #ifndef __CROS_EC_BOARD_H
 #define __CROS_EC_BOARD_H
 
-/*
- * Allow dangerous commands.
- * TODO: Don't use this on production systems.
- */
-#define CONFIG_SYSTEM_UNLOCKED
-
 /*
  * By default, enable all console messages except HC, ACPI and event
  * The sensor stack is generating a lot of activity.
@@ -22,29 +16,32 @@
 #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
 
 /* ISH specific */
-#undef  CONFIG_DEBUG_ASSERT
+#undef CONFIG_DEBUG_ASSERT
 #define CONFIG_CLOCK_CRYSTAL
 #define CONFIG_ISH_UART_0
+
 /* EC */
-#define CONFIG_FLASH_SIZE 0x80000
+#define CONFIG_FLASH_SIZE_BYTES 0x80000
 #define CONFIG_FPU
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
-
-#define CONFIG_ACCELGYRO_LSM6DSM	/* For LSM6DS3 */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(BASE_ACCEL)
+#define CONFIG_I2C_CONTROLLER
 
 /* Host command over HECI */
-#define CONFIG_HOSTCMD_HECI
+#define CONFIG_HOST_INTERFACE_HECI
+
+#ifdef BOARD_TGLRVP_ISH
+#define CONFIG_ACCELGYRO_LSM6DSM /* For LSM6DS3 */
+#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(BASE_ACCEL)
 
 /* I2C ports */
 #define I2C_PORT_SENSOR ISH_I2C1
-#define CONFIG_CMD_I2C_XFER
 
 /* EC Console Commands */
 #define CONFIG_CMD_ACCELS
 #define CONFIG_CMD_ACCEL_INFO
 #define CONFIG_CMD_TIMERINFO
+#define CONFIG_CMD_I2C_XFER
+#endif /* BOARD_TGLRVP_ISH */
 
 /* Undefined features */
 #undef CONFIG_CMD_HASH
@@ -55,7 +52,7 @@
 #undef CONFIG_CMD_SHMEM
 #undef CONFIG_EXTPOWER
 #undef CONFIG_KEYBOARD_KSO_BASE
-#undef CONFIG_FLASH
+#undef CONFIG_FLASH_CROS
 #undef CONFIG_FMAP
 #undef CONFIG_LID_SWITCH
 #undef CONFIG_SWITCH
@@ -81,9 +78,12 @@
 
 #define CONFIG_ISH_IPAPG
 
-#define CONFIG_ISH_D0I2_MIN_USEC	(15*MSEC)
-#define CONFIG_ISH_D0I3_MIN_USEC	(50*MSEC)
-
+#define CONFIG_ISH_D0I2_MIN_USEC (15 * MSEC)
+#ifdef BOARD_ADL_ISH_LITE
+#define CONFIG_ISH_D0I3_MIN_USEC (3000 * MSEC)
+#else
+#define CONFIG_ISH_D0I3_MIN_USEC (50 * MSEC)
+#endif
 #define CONFIG_ISH_NEW_PM
 
 #ifndef __ASSEMBLER__
@@ -92,10 +92,7 @@
 #include "registers.h"
 
 /* Motion sensors */
-enum sensor_id {
-	BASE_ACCEL,
-	SENSOR_COUNT
-};
+enum sensor_id { BASE_ACCEL, SENSOR_COUNT };
 
 #endif /* !__ASSEMBLER__ */
 
diff --git a/board/tglrvp_ish/build.mk b/board/tglrvp_ish/build.mk
index 74ec3c865f..4a84a1f475 100644
--- a/board/tglrvp_ish/build.mk
+++ b/board/tglrvp_ish/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/tglrvp_ish/ec.tasklist b/board/tglrvp_ish/ec.tasklist
index a4db486e9a..aa98f37479 100644
--- a/board/tglrvp_ish/ec.tasklist
+++ b/board/tglrvp_ish/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,6 +7,14 @@
  * See CONFIG_TASK_LIST in config.h for details.
  */
 
+#ifdef BOARD_ADL_ISH_LITE
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, HUGE_TASK_STACK_SIZE, 0) \
+	TASK_NOTEST(CHIPSET, board_idle_task, NULL, IDLE_TASK_STACK_SIZE, 0) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE, 0) \
+	TASK_ALWAYS(HECI_RX, heci_rx_task, NULL, HUGE_TASK_STACK_SIZE, 0) \
+	TASK_ALWAYS(IPC_MNG, ipc_mng_task, NULL, LARGER_TASK_STACK_SIZE, 0)
+#else
 #define CONFIG_TASK_LIST \
 	TASK_ALWAYS(HOOKS, hook_task, NULL, HUGE_TASK_STACK_SIZE, 0) \
 	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, LARGER_TASK_STACK_SIZE, 0) \
@@ -15,3 +23,4 @@
 	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE, 0) \
 	TASK_ALWAYS(HECI_RX, heci_rx_task, NULL, HUGE_TASK_STACK_SIZE, 0) \
 	TASK_ALWAYS(IPC_MNG, ipc_mng_task, NULL, LARGER_TASK_STACK_SIZE, 0)
+#endif
diff --git a/board/tglrvp_ish/gpio.inc b/board/tglrvp_ish/gpio.inc
index 286309e388..8b25af63cb 100644
--- a/board/tglrvp_ish/gpio.inc
+++ b/board/tglrvp_ish/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/tglrvpu_ite/board.c b/board/tglrvpu_ite/board.c
deleted file mode 100644
index 5698761c6a..0000000000
--- a/board/tglrvpu_ite/board.c
+++ /dev/null
@@ -1,206 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel TGL-U-RVP-ITE board-specific configuration */
-
-#include "bb_retimer.h"
-#include "button.h"
-#include "charger.h"
-#include "driver/charger/isl9241.h"
-#include "extpower.h"
-#include "i2c.h"
-#include "icelake.h"
-#include "intc.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "uart.h"
-
-#include "gpio_list.h"
-
-#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ## args)
-
-/* Mutex for shared NVM access */
-static struct mutex bb_nvm_mutex;
-
-/* TCPC gpios */
-const struct tcpc_gpio_config_t tcpc_gpios[] = {
-	[TYPE_C_PORT_0] = {
-		.vbus = {
-			.pin = GPIO_USB_C0_VBUS_INT,
-			.pin_pol = 1,
-		},
-		.src = {
-			.pin = GPIO_USB_C0_SRC_EN,
-			.pin_pol = 1,
-		},
-		.snk = {
-			.pin = GPIO_USB_C0_SNK_EN_L,
-			.pin_pol = 0,
-		},
-		.vconn = {
-			.cc1_pin = GPIO_USB_C0_CC1_VCONN_EN,
-			.cc2_pin = GPIO_USB_C0_CC2_VCONN_EN,
-			.pin_pol = 1,
-		},
-		.src_ilim = {
-			.pin = GPIO_USB_C0_SRC_HI_ILIM,
-			.pin_pol = 1,
-		},
-	},
-	[TYPE_C_PORT_1] = {
-		.vbus = {
-			.pin = GPIO_USB_C1_VBUS_INT,
-			.pin_pol = 1,
-		},
-		.src = {
-			.pin = GPIO_USB_C1_SRC_EN,
-			.pin_pol = 1,
-		},
-		.snk = {
-			.pin = GPIO_USB_C1_SNK_EN_L,
-			.pin_pol = 0,
-		},
-		.vconn = {
-			.cc1_pin = GPIO_USB_C1_CC1_VCONN_EN,
-			.cc2_pin = GPIO_USB_C1_CC2_VCONN_EN,
-			.pin_pol = 1,
-		},
-		.src_ilim = {
-			.pin = GPIO_USB_C1_SRC_HI_ILIM,
-			.pin_pol = 1,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_gpios) == CONFIG_USB_PD_PORT_MAX_COUNT);
-
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	/* Flash EC */
-	[I2C_CHAN_FLASH] = {
-		.name = "chan-A",
-		.port = IT83XX_I2C_CH_A,
-		.kbps = 100,
-		.scl = GPIO_I2C_A_SCL,
-		.sda = GPIO_I2C_A_SDA,
-	},
-	/*
-	 * Port-80 Display, Charger, Battery, IO-expanders, EEPROM,
-	 * IMVP9, AUX-rail, power-monitor.
-	 */
-	[I2C_CHAN_BATT_CHG] = {
-		.name = "batt_chg",
-		.port = IT83XX_I2C_CH_B,
-		.kbps = 100,
-		.scl = GPIO_I2C_B_SCL,
-		.sda = GPIO_I2C_B_SDA,
-	},
-	/* Retimers, PDs */
-	[I2C_CHAN_RETIMER] = {
-		.name = "retimer",
-		.port = IT83XX_I2C_CH_E,
-		.kbps = 100,
-		.scl = GPIO_I2C_E_SCL,
-		.sda = GPIO_I2C_E_SDA,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(i2c_ports) == I2C_CHAN_COUNT);
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* Charger Chips */
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = ISL9241_ADDR_FLAGS,
-		.drv = &isl9241_drv,
-	},
-};
-
-/******************************************************************************/
-/* PWROK signal configuration */
-/*
- * On TGLRVP the ALL_SYS_PWRGD, VCCST_PWRGD, PCH_PWROK, and SYS_PWROK
- * signals are handled by the board. No EC control needed.
- */
-const struct intel_x86_pwrok_signal pwrok_signal_assert_list[] = {};
-const int pwrok_signal_assert_count = ARRAY_SIZE(pwrok_signal_assert_list);
-
-const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[] = {};
-const int pwrok_signal_deassert_count = ARRAY_SIZE(pwrok_signal_assert_list);
-
-/*
- * Returns board information (board id[7:0] and Fab id[15:8]) on success
- * -1 on error.
- */
-int board_get_version(void)
-{
-	int port0, port1;
-	int fab_id, board_id, bom_id;
-
-	if (ioexpander_read_intelrvp_version(&port0, &port1))
-		return -1;
-	/*
-	 * Port0: bit 0   - BOM ID(2)
-	 *        bit 2:1 - FAB ID(1:0) + 1
-	 * Port1: bit 7:6 - BOM ID(1:0)
-	 *        bit 5:0 - BOARD ID(5:0)
-	 */
-	bom_id = ((port1 & 0xC0) >> 6) | ((port0 & 0x01) << 2);
-	fab_id = ((port0 & 0x06) >> 1) + 1;
-	board_id = port1 & 0x3F;
-
-	CPRINTS("BID:0x%x, FID:0x%x, BOM:0x%x", board_id, fab_id, bom_id);
-
-	return board_id | (fab_id << 8);
-}
-
-__override void bb_retimer_power_handle(const struct usb_mux *me, int on_off)
-{
-	const struct bb_usb_control *control = &bb_controls[me->usb_port];
-
-	/*
-	 * LSx based F/W updating is a POR, however to avoid the rework on
-	 * RVP retain the FORCE_PWR GPIO with EC.
-	 */
-	enum gpio_signal force_power_gpio = me->usb_port ?
-		GPIO_USB_C1_RETIMER_FORCE_PWR : GPIO_USB_C0_RETIMER_FORCE_PWR;
-
-	/* handle retimer's power domain */
-	if (on_off) {
-		/*
-		 * BB retimer NVM can be shared between multiple ports, hence
-		 * lock enabling the retimer until the current retimer request
-		 * is complete.
-		 */
-		mutex_lock(&bb_nvm_mutex);
-
-		gpio_set_level(control->usb_ls_en_gpio, 1);
-		/*
-		 * Tpw, minimum time from VCC to RESET_N de-assertion is 100us.
-		 * For boards that don't provide a load switch control, the
-		 * retimer_init() function ensures power is up before calling
-		 * this function.
-		 */
-		msleep(1);
-		gpio_set_level(control->retimer_rst_gpio, 1);
-		msleep(10);
-		gpio_set_level(force_power_gpio, 1);
-
-		/* Allow 20ms time for the retimer to be initialized. */
-		msleep(20);
-
-		mutex_unlock(&bb_nvm_mutex);
-	} else {
-		gpio_set_level(force_power_gpio, 0);
-		msleep(1);
-		gpio_set_level(control->retimer_rst_gpio, 0);
-		msleep(1);
-		gpio_set_level(control->usb_ls_en_gpio, 0);
-	}
-}
diff --git a/board/tglrvpu_ite/board.h b/board/tglrvpu_ite/board.h
deleted file mode 100644
index 222295c7cd..0000000000
--- a/board/tglrvpu_ite/board.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel TGL-U-RVP-ITE board-specific configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* USB MUX */
-#define CONFIG_USB_MUX_VIRTUAL
-
-#define CONFIG_USBC_VCONN
-
-/* FAN configs */
-#define CONFIG_FANS 1
-#define BOARD_FAN_MIN_RPM 3000
-#define BOARD_FAN_MAX_RPM 10000
-
-/* Temperature sensor */
-#define CONFIG_TEMP_SENSOR
-
-/* Support early firmware selection */
-#define CONFIG_VBOOT_EFS2
-#define GPIO_PACKET_MODE_EN		GPIO_ME_G3_TO_ME_EC
-
-#include "baseboard.h"
-
-#define CONFIG_CHIPSET_TIGERLAKE
-#define GPIO_PG_EC_RSMRST_ODL		GPIO_RSMRST_L_PGOOD
-#define GPIO_PCH_DSW_PWROK		GPIO_EC_PCH_DSW_PWROK
-#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_ALL_SYS_PWRGD
-
-/* Charger */
-#define CONFIG_CHARGER_ISL9241
-
-/* DC Jack charge ports */
-#undef  CONFIG_DEDICATED_CHARGE_PORT_COUNT
-#define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1
-
-/* USB ports */
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define DEDICATED_CHARGE_PORT 2
-
-/* USB-C port's USB2 & USB3 port numbers */
-#if defined(BOARD_TGLRVPU_ITE) || defined(BOARD_TGLRVPU_ITE_TCPMV1)
-	#define TYPE_C_PORT_0_USB2_NUM	6
-	#define TYPE_C_PORT_1_USB2_NUM	7
-
-	#define TYPE_C_PORT_0_USB3_NUM	3
-	#define TYPE_C_PORT_1_USB3_NUM	4
-#else /* BOARD_TGLRVPY_ITE */
-	#define TYPE_C_PORT_0_USB2_NUM	6
-	#define TYPE_C_PORT_1_USB2_NUM	5
-
-	#define TYPE_C_PORT_0_USB3_NUM	3
-	#define TYPE_C_PORT_1_USB3_NUM	2
-#endif /* BOARD_TGLRVPU_ITE */
-
-
-/* Config BB retimer */
-#define CONFIG_USBC_RETIMER_INTEL_BB
-
-/* Thermal configs */
-
-/* I2C ports */
-#define CONFIG_IT83XX_SMCLK2_ON_GPC7
-
-#define I2C_PORT_CHARGER	IT83XX_I2C_CH_B
-#define I2C_PORT_BATTERY	IT83XX_I2C_CH_B
-#define I2C_PORT_PCA9555_BOARD_ID_GPIO	IT83XX_I2C_CH_B
-#define I2C_PORT_PORT80		IT83XX_I2C_CH_B
-#define I2C_PORT0_BB_RETIMER	IT83XX_I2C_CH_E
-#define I2C_PORT1_BB_RETIMER	IT83XX_I2C_CH_E
-
-#define I2C_ADDR_PCA9555_BOARD_ID_GPIO	0x22
-#define PORT80_I2C_ADDR			MAX695X_I2C_ADDR1_FLAGS
-#if defined(BOARD_TGLRVPU_ITE) || defined(BOARD_TGLRVPU_ITE_TCPMV1)
-	#define I2C_PORT0_BB_RETIMER_ADDR	0x42
-	#define I2C_PORT1_BB_RETIMER_ADDR	0x43
-#else /* BOARD_TGLRVPY_ITE */
-	#define I2C_PORT0_BB_RETIMER_ADDR	0x42
-	#define I2C_PORT1_BB_RETIMER_ADDR	0x41
-#endif /* BOARD_TGLRVPU_ITE */
-
-/* Enabling SOP* communication */
-#define CONFIG_USB_PD_DECODE_SOP
-
-/* Enabling Thunderbolt-compatible mode */
-#define CONFIG_USB_PD_TBT_COMPAT_MODE
-
-/* Enabling USB4 mode */
-#define CONFIG_USB_PD_USB4
-
-#ifndef __ASSEMBLER__
-
-enum tglrvp_charge_ports {
-	TYPE_C_PORT_0,
-	TYPE_C_PORT_1,
-};
-
-enum tglrvp_i2c_channel {
-	I2C_CHAN_FLASH,
-	I2C_CHAN_BATT_CHG,
-	I2C_CHAN_RETIMER,
-	I2C_CHAN_COUNT,
-};
-
-/* Define max power */
-#define PD_MAX_POWER_MW        60000
-
-int board_get_version(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/tglrvpu_ite/build.mk b/board/tglrvpu_ite/build.mk
deleted file mode 100644
index 57c49d3569..0000000000
--- a/board/tglrvpu_ite/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Intel TGL-U-RVP-ITE board-specific configuration
-#
-
-#it8320
-CHIP:=it83xx
-CHIP_FAMILY:=it8320
-CHIP_VARIANT:=it8320dx
-BASEBOARD:=intelrvp
-
-board-y=board.o
diff --git a/board/tglrvpu_ite/ec.tasklist b/board/tglrvpu_ite/ec.tasklist
deleted file mode 100644
index 4e65a446e4..0000000000
--- a/board/tglrvpu_ite/ec.tasklist
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Intel TGL-U-RVP-ITE board-specific configuration.
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/tglrvpu_ite/gpio.inc b/board/tglrvpu_ite/gpio.inc
deleted file mode 100644
index e0bce1ddd8..0000000000
--- a/board/tglrvpu_ite/gpio.inc
+++ /dev/null
@@ -1,209 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel TGL-U-RVP-ITE board-specific configuration */
-
-/*
- * Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first.
- */
-
-/* Power sequencing interrupts */
-GPIO_INT(PG_EC_DSW_PWROK,	PIN(C, 0), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_SUS_L,		PIN(C, 3), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(ALL_SYS_PWRGD,		PIN(F, 0), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(RSMRST_L_PGOOD,	PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PCH_SLP_S0_L,		PIN(G, 6), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(PCH_SLP_S3_L,		PIN(F, 2), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-GPIO_INT(PCH_SLP_S4_L,		PIN(F, 3), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-
-/* Button interrupts */
-GPIO_INT(VOLUME_UP_L,	PIN(D, 5), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(VOLUME_DOWN_L,	PIN(D, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(LID_OPEN,	PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP, lid_interrupt)
-GPIO_INT(POWER_BUTTON_L,PIN(E, 4), GPIO_INT_BOTH, power_button_interrupt)
-
-GPIO_INT(AC_PRESENT,	PIN(A, 7), GPIO_INT_BOTH, extpower_interrupt)
-
-GPIO_INT(UART1_RX,	PIN(B, 0), GPIO_INT_FALLING, uart_deepsleep_interrupt)	/* UART1 RX input */
-
-GPIO_INT(WP_L,		PIN(I, 4), GPIO_INT_BOTH, switch_interrupt)		/* EC_WP_ODL */
-
-#ifdef CONFIG_HOSTCMD_ESPI
-/* enable 1.8v input of EC's espi_reset pin, and then this pin takes effect. */
-GPIO_INT(ESPI_RESET_L,	PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt) /* eSPI_reset# */
-#endif
-
-GPIO_INT(TABLET_MODE_L,	PIN(K, 1), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-
-/* DC Jack presence coming from +VADP_OUT */
-GPIO_INT(DC_JACK_PRESENT,	PIN(J, 2), GPIO_INT_BOTH, board_dc_jack_interrupt)
-
-/* Type-C interrupts */
-#if defined(BOARD_TGLRVPU_ITE) || defined(BOARD_TGLRVPU_ITE_TCPMV1)
-GPIO_INT(USB_C0_VBUS_INT,	PIN(L, 5), GPIO_INT_BOTH, tcpc_alert_event)
-GPIO_INT(USB_C1_VBUS_INT,	PIN(D, 4), GPIO_INT_BOTH, tcpc_alert_event)
-#else /* BOARD_TGLRVPY_ITE */
-GPIO_INT(USB_C0_VBUS_INT,	PIN(D, 4), GPIO_INT_BOTH, tcpc_alert_event)
-GPIO_INT(USB_C1_VBUS_INT,	PIN(L, 5), GPIO_INT_BOTH, tcpc_alert_event)
-#endif /* BOARD_TGLRVPU_ITE */
-
-/* Power sequencing GPIOs */
-GPIO(CPU_PROCHOT,	PIN(B, 2), GPIO_INPUT)
-GPIO(SYS_RESET_L,	PIN(B, 6), GPIO_ODR_HIGH)
-GPIO(PCH_RSMRST_L,	PIN(C, 6), GPIO_OUT_LOW)
-GPIO(PCH_PWRBTN_L,	PIN(D, 0), GPIO_ODR_HIGH)
-GPIO(EC_SPI_OE_N,	PIN(I, 2), GPIO_OUT_LOW)
-/*
- * PCH_SYS_PWROK is an input, driven by the Silego chip. The common x86
- * power sequencing expects that PCH_SYS_PWROK is an output and will drive
- * this signal if GPIO_PCH_SYS_PWROK is configured. Map this pin as no-connect
- * so that state can be monitored using the console.
- */
-GPIO(NC_PCH_SYS_PWROK,	PIN(K, 4), GPIO_INPUT)
-GPIO(EN_PP5000,		PIN(L, 4), GPIO_OUT_LOW)
-GPIO(EN_PP3300_A,	PIN(K, 2), GPIO_OUT_LOW)
-GPIO(EC_PCH_DSW_PWROK,	PIN(L, 6), GPIO_OUT_LOW)
-
-/* Host communication GPIOs */
-GPIO(PCH_WAKE_L,	PIN(J, 0), GPIO_ODR_HIGH)
-#ifndef CONFIG_HOSTCMD_ESPI
-GPIO(PCH_PLTRST_L,	PIN(E, 3), GPIO_INPUT | GPIO_PULL_UP)
-#endif
-
-/* Battery present */
-GPIO(EC_BATT_PRES_L,	PIN(K, 0), GPIO_INPUT)
-
-/* Type-C GPIOs */
-#if defined(BOARD_TGLRVPU_ITE) || defined(BOARD_TGLRVPU_ITE_TCPMV1)
-GPIO(USB_C0_SRC_EN,	PIN(L, 1), GPIO_OUT_LOW)
-GPIO(USB_C0_SNK_EN_L,	PIN(H, 6), GPIO_ODR_LOW)
-GPIO(USB_C0_SRC_HI_ILIM, PIN(M, 6), GPIO_OUT_LOW)
-GPIO(USB_C0_HPD,	PIN(E, 6), GPIO_INPUT)
-GPIO(USB_C0_FRS_EN,	PIN(L, 7), GPIO_INPUT)
-
-GPIO(USB_C1_SRC_EN,	PIN(G, 1), GPIO_OUT_LOW)
-GPIO(USB_C1_SNK_EN_L,	PIN(I, 5), GPIO_ODR_LOW)
-GPIO(USB_C1_SRC_HI_ILIM, PIN(A, 0), GPIO_OUT_LOW)
-GPIO(USB_C1_HPD,	PIN(D, 3), GPIO_INPUT)
-GPIO(USB_C1_FRS_EN,	PIN(K, 5), GPIO_INPUT)
-
-/* Retimer GPIOs */
-GPIO(USB_C0_LS_EN,		PIN(J, 1), GPIO_OUT_LOW)
-GPIO(USB_C0_RETIMER_RST,	PIN(J, 5), GPIO_OUT_LOW)
-GPIO(USB_C0_RETIMER_FORCE_PWR,	PIN(J, 3), GPIO_OUT_LOW)
-
-GPIO(USB_C1_LS_EN,		PIN(C, 4), GPIO_OUT_LOW)
-GPIO(USB_C1_RETIMER_RST,	PIN(J, 4), GPIO_OUT_LOW)
-GPIO(USB_C1_RETIMER_FORCE_PWR,	PIN(H, 5), GPIO_OUT_LOW)
-#else /* BOARD_TGLRVPY_ITE */
-GPIO(USB_C0_SRC_EN,	PIN(G, 1), GPIO_OUT_LOW)
-GPIO(USB_C0_SNK_EN_L,	PIN(I, 5), GPIO_ODR_LOW | GPIO_PULL_DOWN)
-GPIO(USB_C0_SRC_HI_ILIM, PIN(A, 0), GPIO_OUT_LOW)
-GPIO(USB_C0_HPD,	PIN(D, 3), GPIO_INPUT)
-GPIO(USB_C0_FRS_EN,	PIN(K, 5), GPIO_INPUT)
-
-GPIO(USB_C1_SRC_EN,	PIN(L, 1), GPIO_OUT_LOW)
-GPIO(USB_C1_SNK_EN_L,	PIN(H, 6), GPIO_ODR_LOW | GPIO_PULL_DOWN)
-GPIO(USB_C1_SRC_HI_ILIM, PIN(M, 6), GPIO_OUT_LOW)
-GPIO(USB_C1_HPD,	PIN(E, 6), GPIO_INPUT)
-GPIO(USB_C1_FRS_EN,	PIN(L, 7), GPIO_INPUT)
-
-/* Retimer GPIOs */
-GPIO(USB_C0_LS_EN,		PIN(C, 4), GPIO_OUT_LOW)
-GPIO(USB_C0_RETIMER_RST,	PIN(J, 4), GPIO_OUT_LOW)
-GPIO(USB_C0_RETIMER_FORCE_PWR,	PIN(H, 5), GPIO_OUT_LOW)
-
-GPIO(USB_C1_LS_EN,		PIN(J, 1), GPIO_OUT_LOW)
-GPIO(USB_C1_RETIMER_RST,	PIN(J, 5), GPIO_OUT_LOW)
-GPIO(USB_C1_RETIMER_FORCE_PWR,	PIN(J, 3), GPIO_OUT_LOW)
-#endif /* BOARD_TGLRVPU_ITE */
-
-/* Type-C BC1.2 GPIOs */
-GPIO(USB_C0_BC12_CHG_DET_L,	PIN(A, 1), GPIO_INPUT)
-GPIO(USB_C0_BC12_VBUS_ON_ODL,	PIN(H, 4), GPIO_ODR_HIGH)
-
-GPIO(USB_C1_BC12_CHG_DET_L,	PIN(B, 7), GPIO_INPUT)
-GPIO(USB_C1_BC12_VBUS_ON_ODL,	PIN(J, 6), GPIO_ODR_HIGH)
-
-/* VCONN enable pins */
-GPIO(USB_C0_CC1_VCONN_EN,	PIN(D, 1), GPIO_OUT_LOW)
-GPIO(USB_C0_CC2_VCONN_EN,	PIN(G, 2), GPIO_OUT_LOW)
-GPIO(USB_C1_CC1_VCONN_EN,	PIN(E, 5), GPIO_OUT_LOW)
-GPIO(USB_C1_CC2_VCONN_EN,	PIN(I, 0), GPIO_OUT_LOW)
-
-/* USB-A GPIOs */
-GPIO(USB_A_5V_EN,	PIN(K, 3), GPIO_INPUT)
-
-/* LED */
-GPIO(BAT_LED_GREEN_L,	PIN(A, 6), GPIO_OUT_HIGH)	/* LED_2_L */
-GPIO(AC_LED_GREEN_L,	PIN(A, 3), GPIO_OUT_HIGH)	/* LED_1_L */
-
-/* FAN control pins */
-GPIO(FAN_POWER_EN,	PIN(K, 6), GPIO_OUT_LOW)
-
-/* H1 pins */
-GPIO(CCD_MODE_ODL,	PIN(B, 5), GPIO_INPUT)
-GPIO(ENTERING_RW,	PIN(C, 5), GPIO_OUT_LOW)
-/* ME_GE_TO_ME_EC pin is re-purposed for H1 Packet Mode indication */
-GPIO(ME_G3_TO_ME_EC,	PIN(H, 3), GPIO_OUT_LOW)
-
-/* Used with Discrete TBT and or with PD on RVP */
-GPIO(NC_TBT_C0_RESET_N,		PIN(KSO_H, 7), GPIO_INPUT)
-GPIO(NC_TBT_C1_RESET_N,		PIN(K, 7), GPIO_INPUT)
-GPIO(NC_USB_C0_RETIMER_ALRT,	PIN(I, 7), GPIO_INPUT)
-GPIO(NC_USB_C1_RETIMER_ALRT,	PIN(G, 0), GPIO_INPUT)
-
-/* Used if Base EC is present */
-GPIO(NC_EC_BASE_DET,		PIN(I, 3), GPIO_INPUT)
-
-#ifndef CONFIG_HOSTCMD_ESPI
-GPIO_INT(ESPI_RESET_L,	PIN(D, 2), GPIO_INPUT)
-#endif
-
-/* Unused pins */
-GPIO(NC_SUSWARN,		PIN(E, 1), GPIO_INPUT)
-GPIO(NC_BATT_DISABLE,		PIN(H, 0), GPIO_INPUT)
-GPIO(NC_SMC_ONOFF_N,		PIN(L, 3), GPIO_INPUT) /* Power button interrupt without H1 */
-
-/*
- * I2C pins should be configure as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-GPIO(I2C_A_SCL,	PIN(B, 3), GPIO_INPUT)
-GPIO(I2C_A_SDA,	PIN(B, 4), GPIO_INPUT)
-GPIO(I2C_B_SCL,	PIN(C, 1), GPIO_INPUT)
-GPIO(I2C_B_SDA,	PIN(C, 2), GPIO_INPUT)
-GPIO(I2C_C_SCL,	PIN(C, 7), GPIO_INPUT)
-GPIO(I2C_C_SDA,	PIN(F, 7), GPIO_INPUT)
-GPIO(I2C_E_SCL,	PIN(E, 0), GPIO_INPUT)
-GPIO(I2C_E_SDA,	PIN(E, 7), GPIO_INPUT)
-GPIO(I2C_F_SCL,	PIN(A, 4), GPIO_INPUT)
-GPIO(I2C_F_SDA,	PIN(A, 5), GPIO_INPUT)
-
-/* Alternate pins for I2C */
-ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C F SCL/SDA A4/A5 */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(4)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C A SCL/SDA B3/B4 */
-ALTERNATE(PIN_MASK(C, BIT(1) | BIT(2)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C B SCL/SDA C1/C2 */
-ALTERNATE(PIN_MASK(E, BIT(0) | BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C E SCL/SDA E0/E7 */
-ALTERNATE(PIN_MASK(C, BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C C SCL C7 */
-ALTERNATE(PIN_MASK(F, BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C C SDA F7 */
-
-/* Alternate pins for UART */
-ALTERNATE(PIN_MASK(B, BIT(0) | BIT(1)), GPIO_ALT_FUNC_DEFAULT, MODULE_UART, GPIO_PULL_UP) /* UART1 B0/B1 */
-
-/* Alternate pins for ADC */
-ALTERNATE(PIN_MASK(I, BIT(1) | BIT(6)), GPIO_ALT_FUNC_DEFAULT, MODULE_ADC, GPIO_FLAG_NONE)	/* ADC 1,6 -> I1,I6 */
-ALTERNATE(PIN_MASK(L, BIT(0) | BIT(2)), GPIO_ALT_FUNC_DEFAULT, MODULE_ADC, GPIO_FLAG_NONE)	/* ADC 13,15 -> L0,L2 */
-
-/* Alternate pins for FAN */
-ALTERNATE(PIN_MASK(A, BIT(2)), GPIO_ALT_FUNC_DEFAULT, MODULE_PWM, GPIO_FLAG_NONE)	/* PWM2 A2 */
-ALTERNATE(PIN_MASK(D, BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_PWM, GPIO_FLAG_NONE)	/* TACH1A D7 */
diff --git a/board/tglrvpu_ite_tcpmv1 b/board/tglrvpu_ite_tcpmv1
deleted file mode 120000
index 05edd4d22f..0000000000
--- a/board/tglrvpu_ite_tcpmv1
+++ /dev/null
@@ -1 +0,0 @@
-tglrvpu_ite
\ No newline at end of file
diff --git a/board/tglrvpy_ite b/board/tglrvpy_ite
deleted file mode 120000
index 05edd4d22f..0000000000
--- a/board/tglrvpy_ite
+++ /dev/null
@@ -1 +0,0 @@
-tglrvpu_ite
\ No newline at end of file
diff --git a/board/tglrvpy_ite_tcpmv1 b/board/tglrvpy_ite_tcpmv1
deleted file mode 120000
index 560115c8ab..0000000000
--- a/board/tglrvpy_ite_tcpmv1
+++ /dev/null
@@ -1 +0,0 @@
-tglrvpy_ite
\ No newline at end of file
diff --git a/board/tigertail/board.c b/board/tigertail/board.c
index 8963c7e80a..73ba1ecc73 100644
--- a/board/tigertail/board.c
+++ b/board/tigertail/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,6 @@
 /* Tigertail board configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "common.h"
 #include "console.h"
 #include "ec_version.h"
@@ -20,24 +19,23 @@
 #include "timer.h"
 #include "update_fw.h"
 #include "usart-stm32f0.h"
-#include "usart_tx_dma.h"
 #include "usart_rx_dma.h"
-#include "usb_i2c.h"
+#include "usart_tx_dma.h"
 #include "usb-stream.h"
+#include "usb_i2c.h"
 #include "util.h"
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 /******************************************************************************
  * Forward UARTs as a USB serial interface.
  */
 
-#define USB_STREAM_RX_SIZE	16
-#define USB_STREAM_TX_SIZE	16
+#define USB_STREAM_RX_SIZE 16
+#define USB_STREAM_TX_SIZE 16
 
 /******************************************************************************
  * Forward USART1 as a simple USB serial interface.
@@ -45,43 +43,33 @@
 static struct usart_config const usart1;
 struct usb_stream_config const usart1_usb;
 
-static struct queue const usart1_to_usb = QUEUE_DIRECT(64, uint8_t,
-	usart1.producer, usart1_usb.consumer);
-static struct queue const usb_to_usart1 = QUEUE_DIRECT(64, uint8_t,
-	usart1_usb.producer, usart1.consumer);
+static struct queue const usart1_to_usb =
+	QUEUE_DIRECT(64, uint8_t, usart1.producer, usart1_usb.consumer);
+static struct queue const usb_to_usart1 =
+	QUEUE_DIRECT(64, uint8_t, usart1_usb.producer, usart1.consumer);
 
 static struct usart_config const usart1 =
-	USART_CONFIG(usart1_hw,
-		usart_rx_interrupt,
-		usart_tx_interrupt,
-		115200,
-		0,
-		usart1_to_usb,
-		usb_to_usart1);
-
-USB_STREAM_CONFIG(usart1_usb,
-	USB_IFACE_USART1_STREAM,
-	USB_STR_USART1_STREAM_NAME,
-	USB_EP_USART1_STREAM,
-	USB_STREAM_RX_SIZE,
-	USB_STREAM_TX_SIZE,
-	usb_to_usart1,
-	usart1_to_usb)
+	USART_CONFIG(usart1_hw, usart_rx_interrupt, usart_tx_interrupt, 115200,
+		     0, usart1_to_usb, usb_to_usart1);
 
+USB_STREAM_CONFIG(usart1_usb, USB_IFACE_USART1_STREAM,
+		  USB_STR_USART1_STREAM_NAME, USB_EP_USART1_STREAM,
+		  USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE, usb_to_usart1,
+		  usart1_to_usb)
 
 /******************************************************************************
  * Define the strings used in our USB descriptors.
  */
 const void *const usb_strings[] = {
-	[USB_STR_DESC]         = usb_string_desc,
-	[USB_STR_VENDOR]       = USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]      = USB_STRING_DESC("Tigertail"),
-	[USB_STR_SERIALNO]     = 0,
-	[USB_STR_VERSION]      = USB_STRING_DESC(CROS_EC_VERSION32),
-	[USB_STR_I2C_NAME]     = USB_STRING_DESC("I2C"),
-	[USB_STR_USART1_STREAM_NAME]  = USB_STRING_DESC("DUT UART"),
+	[USB_STR_DESC] = usb_string_desc,
+	[USB_STR_VENDOR] = USB_STRING_DESC("Google LLC"),
+	[USB_STR_PRODUCT] = USB_STRING_DESC("Tigertail"),
+	[USB_STR_SERIALNO] = 0,
+	[USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32),
+	[USB_STR_I2C_NAME] = USB_STRING_DESC("I2C"),
+	[USB_STR_USART1_STREAM_NAME] = USB_STRING_DESC("DUT UART"),
 	[USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Tigertail Console"),
-	[USB_STR_UPDATE_NAME]  = USB_STRING_DESC("Firmware update"),
+	[USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"),
 };
 
 BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
@@ -91,25 +79,29 @@ BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
  */
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_SBU1] = {"SBU1", 3300, 4096, 0, STM32_AIN(6)},
-	[ADC_SBU2] = {"SBU2", 3300, 4096, 0, STM32_AIN(7)},
+	[ADC_SBU1] = { "SBU1", 3300, 4096, 0, STM32_AIN(6) },
+	[ADC_SBU2] = { "SBU2", 3300, 4096, 0, STM32_AIN(7) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
-
-
 /******************************************************************************
  * Support I2C bridging over USB.
  */
 
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{"master", I2C_PORT_MASTER, 100,
-		GPIO_MASTER_I2C_SCL, GPIO_MASTER_I2C_SDA},
+	{ .name = "master",
+	  .port = I2C_PORT_MASTER,
+	  .kbps = 100,
+	  .scl = GPIO_MASTER_I2C_SCL,
+	  .sda = GPIO_MASTER_I2C_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
-int usb_i2c_board_is_enabled(void) { return 1; }
+int usb_i2c_board_is_enabled(void)
+{
+	return 1;
+}
 
 /******************************************************************************
  * Console commands.
@@ -134,7 +126,7 @@ static void set_uart_gpios(int state)
 {
 	int uart = GPIO_INPUT;
 	int dir = 0;
-	int voltage = 1;  /* 1: 1.8v, 0: 3.3v */
+	int voltage = 1; /* 1: 1.8v, 0: 3.3v */
 	int enabled = 0;
 
 	gpio_set_level(GPIO_ST_UART_LVL_DIS, 1);
@@ -283,7 +275,7 @@ void set_uart_state(int state)
  */
 void uart_sbu_tick(void)
 {
-	static int debounce;  /* = 0 */
+	static int debounce; /* = 0 */
 
 	if (uart_detect != UART_DETECT_AUTO)
 		return;
@@ -320,7 +312,7 @@ void uart_sbu_tick(void)
 }
 DECLARE_HOOK(HOOK_TICK, uart_sbu_tick, HOOK_PRIO_DEFAULT);
 
-static int command_uart(int argc, char **argv)
+static int command_uart(int argc, const char **argv)
 {
 	const char *uart_state_str = "off";
 	const char *uart_detect_str = "manual";
@@ -345,15 +337,15 @@ static int command_uart(int argc, char **argv)
 	uart_state_str = uart_state_names[uart_state];
 	if (uart_detect == UART_DETECT_AUTO)
 		uart_detect_str = "auto";
-	ccprintf("UART mux is: %s, setting: %s\n",
-		uart_state_str, uart_detect_str);
+	ccprintf("UART mux is: %s, setting: %s\n", uart_state_str,
+		 uart_detect_str);
 
 	return EC_SUCCESS;
 }
 DECLARE_CONSOLE_COMMAND(uart, command_uart,
-	"[off|on18|on33|flip18|flip33|auto]",
-	"Set the sbu uart state\n"
-	"WARNING: 3.3v may damage 1.8v devices.\n");
+			"[off|on18|on33|flip18|flip33|auto]",
+			"Set the sbu uart state\n"
+			"WARNING: 3.3v may damage 1.8v devices.\n");
 
 static void set_led_a(int r, int g, int b)
 {
@@ -418,7 +410,6 @@ void set_mux_state(int state)
 		set_led_b(1, 0, 0);
 }
 
-
 /* On button press, toggle between mux A, B, off. */
 static int button_ready = 1;
 void button_interrupt_deferred(void)
@@ -457,7 +448,7 @@ void button_interrupt(enum gpio_signal signal)
 	hook_call_deferred(&button_interrupt_deferred_data, 0);
 }
 
-static int command_mux(int argc, char **argv)
+static int command_mux(int argc, const char **argv)
 {
 	char *mux_state_str = "off";
 
@@ -480,9 +471,8 @@ static int command_mux(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(mux, command_mux,
-	"[off|A|B]",
-	"Get/set the mux and enable state of the TYPE-C mux");
+DECLARE_CONSOLE_COMMAND(mux, command_mux, "[off|A|B]",
+			"Get/set the mux and enable state of the TYPE-C mux");
 
 /******************************************************************************
  * Initialize board.
diff --git a/board/tigertail/board.h b/board/tigertail/board.h
index 63019e717f..26e6af5985 100644
--- a/board/tigertail/board.h
+++ b/board/tigertail/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,7 +24,6 @@
 #undef CONFIG_UART_RX_DMA
 
 /* Optional features */
-#define CONFIG_STM_HWTIMER32
 #define CONFIG_HW_CRC
 
 /* USB Configuration */
@@ -40,19 +39,19 @@
 #define DEFAULT_SERIALNO "Uninitialized"
 
 /* USB interface indexes (use define rather than enum to expand them) */
-#define USB_IFACE_CONSOLE	0
-#define USB_IFACE_UPDATE	1
-#define USB_IFACE_USART1_STREAM	2
-#define USB_IFACE_I2C		3
-#define USB_IFACE_COUNT		4
+#define USB_IFACE_CONSOLE 0
+#define USB_IFACE_UPDATE 1
+#define USB_IFACE_USART1_STREAM 2
+#define USB_IFACE_I2C 3
+#define USB_IFACE_COUNT 4
 
 /* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL		0
-#define USB_EP_CONSOLE		1
-#define USB_EP_UPDATE		2
-#define USB_EP_USART1_STREAM	3
-#define USB_EP_I2C		4
-#define USB_EP_COUNT		5
+#define USB_EP_CONTROL 0
+#define USB_EP_CONSOLE 1
+#define USB_EP_UPDATE 2
+#define USB_EP_USART1_STREAM 3
+#define USB_EP_I2C 4
+#define USB_EP_COUNT 5
 
 /* Enable console recasting of GPIO type. */
 #define CONFIG_CMD_GPIO_EXTENDED
@@ -64,7 +63,7 @@
 /* Enable control of I2C over USB */
 #define CONFIG_USB_I2C
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_CONTROLLER
 #define I2C_PORT_MASTER 0
 #define CONFIG_INA231
 
@@ -77,14 +76,11 @@
  */
 #define CONFIG_SYSTEM_UNLOCKED
 
-
 #ifndef __ASSEMBLER__
 
 /* Timer selection */
 #define TIM_CLOCK32 2
-#define TIM_ADC     3
-
-
+#define TIM_ADC 3
 
 #include "gpio_signal.h"
 
diff --git a/board/tigertail/build.mk b/board/tigertail/build.mk
index 9e7fae1c07..7766dd5e6b 100644
--- a/board/tigertail/build.mk
+++ b/board/tigertail/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/tigertail/ec.tasklist b/board/tigertail/ec.tasklist
index afdb5dedc7..c254025ebc 100644
--- a/board/tigertail/ec.tasklist
+++ b/board/tigertail/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/tigertail/gpio.inc b/board/tigertail/gpio.inc
index 107d3b2a2e..41c96cba46 100644
--- a/board/tigertail/gpio.inc
+++ b/board/tigertail/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/todor/battery.c b/board/todor/battery.c
deleted file mode 100644
index d129ede528..0000000000
--- a/board/todor/battery.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Volteer battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* LGC\011 L17L3PB0 Battery Information */
-	/*
-	 * Battery info provided by ODM on b/143477210, comment #11
-	 */
-	[BATTERY_LGC011] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= TARGET_WITH_MARGIN(13200, 5),
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 75,
-		},
-	},
-	/* LGC AP18C8K Battery Information */
-	 [BATTERY_LGC_AP18C8K] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC KT0030G020",
-			.device_name = "AP18C8K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x43,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max            = 13050,
-			.voltage_normal         = 11250,
-			.voltage_min            = 9000,
-			.precharge_current      = 256,
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 50,
-			.charging_min_c         = 0,
-			.charging_max_c         = 60,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 75,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_LGC011;
diff --git a/board/todor/board.c b/board/todor/board.c
deleted file mode 100644
index 6f189a7c33..0000000000
--- a/board/todor/board.c
+++ /dev/null
@@ -1,440 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer board-specific configuration */
-#include "bb_retimer.h"
-#include "button.h"
-#include "common.h"
-#include "accelgyro.h"
-#include "cbi_ec_fw_config.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi260.h"
-#include "driver/als_tcs3400.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/ppc/syv682x.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/tusb422.h"
-#include "driver/retimer/bb_retimer.h"
-#include "driver/sync.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "tablet_mode.h"
-#include "throttle_ap.h"
-#include "uart.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tbt.h"
-#include "usb_pd_tcpm.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-/* Keyboard scan setting */
-struct keyboard_scan_config keyscan_config = {
-	/* Increase from 50 us, because KSO_02 passes through the H1. */
-	.output_settle_us = 80,
-	/* Other values should be the same as the default configuration. */
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-/******************************************************************************/
-/*
- * FW_CONFIG defaults for Todor if the CBI data is not initialized.
- */
-union volteer_cbi_fw_config fw_config_defaults = {
-	.usb_db = DB_USB3_PASSIVE,
-};
-
-static void board_init(void)
-{
-
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-__override enum tbt_compat_cable_speed board_get_max_tbt_speed(int port)
-{
-	/* Routing length exceeds 205mm prior to connection to re-timer */
-	if (port == USBC_PORT_C1)
-		return TBT_SS_U32_GEN1_GEN2;
-
-	/*
-	 * Thunderbolt-compatible mode not supported
-	 *
-	 * TODO (b/147726366): All the USB-C ports need to support same speed.
-	 * Need to fix once USB-C feature set is known for Volteer.
-	 */
-	return TBT_SS_RES_0;
-}
-
-__override bool board_is_tbt_usb4_port(int port)
-{
-	/*
-	 * On Proto-1 only Port 1 supports TBT & USB4
-	 *
-	 * TODO (b/147732807): All the USB-C ports need to support same
-	 * features. Need to fix once USB-C feature set is known for Volteer.
-	 */
-	return port == USBC_PORT_C1;
-}
-
-/******************************************************************************/
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C0_SENSOR_SCL,
-		.sda = GPIO_EC_I2C0_SENSOR_SDA,
-	},
-	{
-		.name = "usb_c0",
-		.port = I2C_PORT_USB_C0,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C1_USB_C0_SCL,
-		.sda = GPIO_EC_I2C1_USB_C0_SDA,
-	},
-	{
-		.name = "usb_c1",
-		.port = I2C_PORT_USB_C1,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C2_USB_C1_SCL,
-		.sda = GPIO_EC_I2C2_USB_C1_SDA,
-	},
-	{
-		.name = "usb_0_mix",
-		.port = I2C_PORT_USB_0_MIX,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C3_USB_0_MIX_SCL,
-		.sda = GPIO_EC_I2C3_USB_0_MIX_SDA,
-	},
-	{
-		.name = "usb_1_mix",
-		.port = I2C_PORT_USB_1_MIX,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C4_USB_1_MIX_SCL,
-		.sda = GPIO_EC_I2C4_USB_1_MIX_SDA,
-	},
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C5_POWER_SCL,
-		.sda = GPIO_EC_I2C5_POWER_SDA,
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C7_EEPROM_SCL,
-		.sda = GPIO_EC_I2C7_EEPROM_SDA,
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/******************************************************************************/
-/* PWM configuration */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED1_BLUE] = {
-		.channel = 2,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 2400,
-	},
-	[PWM_CH_LED2_GREEN] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 2400,
-	},
-	[PWM_CH_LED3_RED] = {
-		.channel = 1,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 2400,
-	},
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = 0,
-		/*
-		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
-		 * flicker. Higher frequencies consume similar average power to
-		 * lower PWM frequencies, but higher frequencies record a much
-		 * lower maximum power.
-		 */
-		.freq = 2400,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/******************************************************************************/
-/* EC thermal management configuration */
-
-/*
- * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
- * 130 C.  However, sensor is located next to DDR, so we need to use the lower
- * DDR temperature limit (85 C)
- */
-const static struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(35),
-	.temp_fan_max = C_TO_K(50),
-};
-
-/*
- * Inductor limits - used for both charger and PP3300 regulator
- *
- * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
- *
- * Charger max recommended temperature 100C, max absolute temperature 125C
- * PP3300 regulator: operating range -40 C to 145 C
- *
- * Inductors: limit of 125c
- * PCB: limit is 80c
- */
-const static struct ec_thermal_config thermal_inductor = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(55),
-};
-
-
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_CHARGER]			= thermal_inductor,
-	[TEMP_SENSOR_2_PP3300_REGULATOR]	= thermal_inductor,
-	[TEMP_SENSOR_3_DDR_SOC]			= thermal_cpu,
-	[TEMP_SENSOR_4_FAN]			= thermal_cpu,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-/******************************************************************************/
-
-static void kb_backlight_enable(void)
-{
-	gpio_set_level(GPIO_EC_KB_BL_EN, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, kb_backlight_enable, HOOK_PRIO_DEFAULT);
-
-static void kb_backlight_disable(void)
-{
-	gpio_set_level(GPIO_EC_KB_BL_EN, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, kb_backlight_disable, HOOK_PRIO_DEFAULT);
-
-void board_reset_pd_mcu(void)
-{
-	/* TODO(b/159025015): Terrador: check USB PD reset operation */
-}
-
-/* USBC mux configuration - Tiger Lake includes internal mux */
-struct usb_mux usbc0_usb4_mb_retimer = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &bb_usb_retimer,
-	.i2c_port = I2C_PORT_USB_0_MIX,
-	.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
-};
-/*****************************************************************************
- * USB-C MUX/Retimer dynamic configuration.
- */
-static void setup_mux(void)
-{
-	CPRINTS("C0 supports bb-retimer");
-	/* USB-C port 0 have a retimer */
-	usb_muxes[USBC_PORT_C0].next_mux = &usbc0_usb4_mb_retimer;
-}
-
-__override void board_cbi_init(void)
-{
-	/*
-	 * TODO(b/159025015): Terrador: check FW_CONFIG fields for USB DB type
-	 */
-	setup_mux();
-	/* Reassign USB_C0_RT_RST_ODL */
-	bb_controls[USBC_PORT_C0].usb_ls_en_gpio = GPIO_USB_C0_LS_EN;
-	bb_controls[USBC_PORT_C0].retimer_rst_gpio = GPIO_USB_C0_RT_RST_ODL;
-
-}
-
-/******************************************************************************/
-/* USBC PPC configuration */
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/******************************************************************************/
-/* PPC support routines */
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C0);
-		break;
-	case GPIO_USB_C1_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C1);
-	default:
-		break;
-	}
-}
-
-/******************************************************************************/
-/* BC1.2 charger detect configuration */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC TCPC configuration */
-struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
-		},
-		.drv = &tusb422_tcpm_drv,
-		.usb23 = USBC_PORT_0_USB2_NUM | (USBC_PORT_0_USB3_NUM << 4),
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C1,
-			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
-		},
-		.drv = &tusb422_tcpm_drv,
-		.usb23 = USBC_PORT_1_USB2_NUM | (USBC_PORT_1_USB3_NUM << 4),
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC mux configuration - Tiger Lake includes internal mux */
-struct usb_mux usbc1_usb4_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &bb_usb_retimer,
-	.i2c_port = I2C_PORT_USB_1_MIX,
-	.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
-};
-struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc1_usb4_db_retimer,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-struct bb_usb_control bb_controls[] = {
-	[USBC_PORT_C0] = {
-		/* USB-C port 0 doesn't have a retimer */
-	},
-	[USBC_PORT_C1] = {
-		.usb_ls_en_gpio = GPIO_USB_C1_LS_EN,
-		.retimer_rst_gpio = GPIO_USB_C1_RT_RST_ODL,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(bb_controls) == USBC_PORT_COUNT);
-
-static void board_tcpc_init(void)
-{
-	/* Don't reset TCPCs after initial reset */
-	if (!system_jumped_late())
-		board_reset_pd_mcu();
-
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
-
-	/* Enable BC1.2 interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
-
-/******************************************************************************/
-/* TCPC support routines */
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	/*
-	 * Check which port has the ALERT line set
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_0;
-	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (port == USBC_PORT_C0)
-		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
-	else
-		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
-}
diff --git a/board/todor/board.h b/board/todor/board.h
deleted file mode 100644
index 011fd8e359..0000000000
--- a/board/todor/board.h
+++ /dev/null
@@ -1,193 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Baseboard features */
-#include "baseboard.h"
-
-/* Optional features */
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
-
-#define CONFIG_VBOOT_EFS2
-
-#define CONFIG_POWER_BUTTON
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* LED defines */
-#define CONFIG_LED_PWM
-/* Although there are 2 LEDs, they are both controlled by the same lines. */
-#define CONFIG_LED_PWM_COUNT 1
-
-/* Keyboard features */
-
-/* Sensors */
-/* BMA253 accelerometer in base */
-#define CONFIG_ACCEL_BMA255
-
-/* BMI260 accel/gyro in base */
-#define CONFIG_ACCELGYRO_BMI260
-#define CONFIG_ACCELGYRO_BMI260_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-/* TCS3400 ALS */
-#define CONFIG_ALS
-#define ALS_COUNT		1
-#define CONFIG_ALS_TCS3400
-#define CONFIG_ALS_TCS3400_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS)
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
-	(BIT(LID_ACCEL) | BIT(CLEAR_ALS))
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE		BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID		LID_ACCEL
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
-
-/*
- * USB-C port's USB2 & USB3 mapping from schematics
- * USB2 numbering on PCH - 1 to n
- * USB3 numbering on AP - 0 to n (PMC's USB3 numbering for MUX
- * configuration is - 1 to n hence add +1)
- */
-#define USBC_PORT_0_USB2_NUM	9
-#define USBC_PORT_0_USB3_NUM	1
-#define USBC_PORT_1_USB2_NUM	4
-#define USBC_PORT_1_USB3_NUM	2
-
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
-
-/*
- * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
- * cables only support up to 60W.
- */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
-
-/* Enabling Thunderbolt-compatible mode */
-#define CONFIG_USB_PD_TBT_COMPAT_MODE
-
-/* Enabling USB4 mode */
-#define CONFIG_USB_PD_USB4
-#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR	0x40
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x40
-
-/* USB Type A Features */
-
-/* USBC PPC*/
-#define CONFIG_USBC_PPC_SYV682X		/* USBC port C0/C1 */
-
-/* BC 1.2 */
-
-/* Volume Button feature */
-
-/* Fan features */
-#undef CONFIG_FANS
-
-/* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_UART2_EC_RX
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PG_EC_DSW_PWROK		GPIO_DSW_PWROK
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD		GPIO_PG_EC_RSMRST_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
-#define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE_L
-
-/* I2C Bus Configuration */
-#define CONFIG_I2C
-#define I2C_PORT_ACCEL		I2C_PORT_SENSOR
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_0_MIX	NPCX_I2C_PORT3_0
-#define I2C_PORT_USB_1_MIX	NPCX_I2C_PORT4_1
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-#define CONFIG_I2C_MASTER
-
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum battery_type {
-	BATTERY_LGC011,
-	BATTERY_LGC_AP18C8K,
-	BATTERY_TYPE_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_LED1_BLUE = 0,
-	PWM_CH_LED2_GREEN,
-	PWM_CH_LED3_RED,
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	CLEAR_ALS,
-	RGB_ALS,
-	SENSOR_COUNT,
-};
-
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
-
-void board_reset_pd_mcu(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/todor/build.mk b/board/todor/build.mk
deleted file mode 100644
index b78172d3cf..0000000000
--- a/board/todor/build.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
-BASEBOARD:=volteer
-
-board-y=board.o
-board-y+=battery.o
-board-y+=led.o
-board-y+=sensors.o
diff --git a/board/todor/ec.tasklist b/board/todor/ec.tasklist
deleted file mode 100644
index 292de51cdb..0000000000
--- a/board/todor/ec.tasklist
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/todor/gpio.inc b/board/todor/gpio.inc
deleted file mode 100644
index 0ccb99815e..0000000000
--- a/board/todor/gpio.inc
+++ /dev/null
@@ -1,167 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(EC_LID_OPEN,          PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(EC_WP_L,              PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(H1_EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
-GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_RSMRST_ODL,     PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(DSW_PWROK,            PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4),  GPIO_INT_BOTH, power_signal_interrupt)
-
-/* Sensor Interrupts */
-GPIO_INT(EC_IMU_INT_L,         PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, bmi260_interrupt)
-GPIO_INT(EC_ALS_RGB_INT_L,     PIN(D, 4), GPIO_INT_FALLING, tcs3400_interrupt)
-GPIO_INT(TABLET_MODE_L,        PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(E, 0), GPIO_INT_BOTH, tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(A, 2), GPIO_INT_BOTH, tcpc_alert_event)
-
-GPIO_INT(USB_C0_PPC_INT_ODL,	PIN(6, 2), GPIO_INT_BOTH, ppc_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(F, 5), GPIO_INT_BOTH, ppc_interrupt)
-
-GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(E, 4), GPIO_INT_BOTH, bc12_interrupt)
-GPIO_INT(USB_C1_MIX_INT_ODL,	PIN(0, 3), GPIO_INT_BOTH, bc12_interrupt)
-
-/* HDMI interrupts */
-
-/* Volume button interrupts */
-GPIO_INT(EC_VOLDN_BTN_ODL,		PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL,		PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-
-/* Power Sequencing Signals */
-GPIO(EN_PP3300_A,              PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_PPVAR_VCCIN,           PIN(4, 3), GPIO_OUT_LOW) /* Enables VCCIN IMPV9 */
-/* The EC does not buffer this signal on Volteer. */
-UNIMPLEMENTED(PCH_DSW_PWROK)
-
-/* Other wake sources */
-/*
- * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an
- * interrupt handler because it is automatically handled by the PSL.
- *
- * We need to lock the setting so this gpio can't be reconfigured to overdrive
- * the real reset signal. (This is the PSL input pin not the real reset pin).
- */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH |
-					   GPIO_HIB_WAKE_HIGH |
-					   GPIO_LOCKED)
-
-/* AP/PCH Signals */
-GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
-GPIO(EC_PCH_RSMRST_ODL,        PIN(A, 6), GPIO_ODR_LOW) /* TODO - b/140950085 - implement TGL sequencing requirement */
-GPIO(EC_PCH_PWR_BTN_ODL,       PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
-GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
-GPIO_INT(EC_PROCHOT_IN_L,      PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
-GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
-
-GPIO(EC_PCH_INT_ODL,           PIN(B, 0), GPIO_ODR_HIGH)
-
-/* USB and USBC Signals */
-
-/*
- * USB_C1 moved from GPIO32 to GPIO83 on boards with board ID >=1.
- * GPIO83/EN_PP1800_A is DNS on board ID 0 and GPIO32 is N/C on board ID >=1
- * so it's safe to define GPIOs compatible with both designs.
- * TODO (b/149858568): remove board ID=0 support.
- */
-GPIO(USB_C0_RT_RST_ODL,			PIN(6, 1), GPIO_ODR_LOW) /* USB_C0 Reset */
-GPIO(USB_C1_RT_RST_ODL,			PIN(8, 3), GPIO_ODR_LOW) /* USB_C1 Reset */
-GPIO(USB_C0_OC_ODL,			PIN(B, 1), GPIO_ODR_HIGH)
-GPIO(USB_C1_OC_ODL,			PIN(5, 0), GPIO_ODR_HIGH)
-GPIO(USB_C0_FRS_EN,			PIN(6, 0), GPIO_OUT_LOW)
-GPIO(USB_C1_FRS_EN,			PIN(9, 4), GPIO_OUT_LOW)
-
-/* Don't have a load switch for retimer */
-UNIMPLEMENTED(USB_C0_LS_EN)
-UNIMPLEMENTED(USB_C1_LS_EN)
-
-/* Misc Signals */
-GPIO(UART2_EC_RX,		PIN(7, 5), GPIO_OUT_LOW)	/* H1 Packet Mode */
-GPIO(EC_KB_BL_EN,		PIN(8, 6), GPIO_OUT_LOW)	/* Keyboard backlight enable*/
-GPIO(CCD_MODE_ODL,		PIN(E, 5), GPIO_INPUT)		/* Case Closed Debug Mode */
-
-/*
- * eDP backlight - both PCH and EC have enable pins that must be high
- * for the backlight to turn on. Default state is high, and can be turned
- * off during sleep states.
- */
-GPIO(EC_EDP_BL_EN,             PIN(D, 3), GPIO_OUT_HIGH)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(EC_I2C0_SENSOR_SCL,       PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C0_SENSOR_SDA,       PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C1_USB_C0_SCL,       PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C1_USB_C0_SDA,       PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SCL,       PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SDA,       PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C3_USB_0_MIX_SCL,    PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C3_USB_0_MIX_SDA,    PIN(D, 0), GPIO_INPUT)
-GPIO(EC_I2C4_USB_1_MIX_SCL,    PIN(F, 3), GPIO_INPUT)
-GPIO(EC_I2C4_USB_1_MIX_SDA,    PIN(F, 2), GPIO_INPUT)
-GPIO(EC_I2C5_POWER_SCL,        PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C5_POWER_SDA,        PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_SCL,       PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_SDA,       PIN(B, 2), GPIO_INPUT)
-
-/* Battery signals */
-GPIO(EC_BATT_PRES_ODL, 		PIN(E, 1), GPIO_INPUT)
-
-/* Physical HPD pins are not needed on EC as these are configured by PMC */
-GPIO(USB_C0_DP_HPD,		PIN(B, 7), GPIO_INPUT)
-GPIO(USB_C1_DP_HPD,		PIN(7, 0), GPIO_INPUT)
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, BIT(5) | BIT(4)), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V)) /* I2C0 */
-ALTERNATE(PIN_MASK(9, BIT(0) | BIT(2) | BIT(1)), 0, MODULE_I2C, 0)                   /* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)                                     /* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, BIT(1) | BIT(0)), 0, MODULE_I2C, 0)                            /* I2C3 */
-ALTERNATE(PIN_MASK(F, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)                            /* I2C4 */
-ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)                            /* I2C5 */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)                            /* I2C7 */
-
-/* This selects between an LED module on the motherboard and one on the daughter
- * board, to be controlled by LED_{1,2,3}_L. PWM allows driving both modules at
- * the same time. */
-ALTERNATE(PIN_MASK(C, BIT(2) | BIT(3) | BIT(4)), 0, MODULE_PWM, 0)                   /* LED_{3,2,1}_L */
-
-/* Keyboard pins */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_00-01 */
-GPIO(EC_KSO_02_INV, PIN(1, 7),                        GPIO_OUT_LOW)  /* KSO_02 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_14 */
-ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)                     /* EC_KB_BL_PWM */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, BIT(5) | BIT(4)), 0, MODULE_UART, 0)                           /* UART from EC to Servo */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)                    /* GPIOD2 = EC_LID_OPEN */
-ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)  /* GPIO00 = ACOK_OD,
-                                                                       GPIO01 = H1_EC_PWR_BTN_ODL
-                                                                       GPIO02 = EC_RST_ODL */
-
diff --git a/board/todor/led.c b/board/todor/led.c
deleted file mode 100644
index c4053f0f10..0000000000
--- a/board/todor/led.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Volteer
- */
-
-#include "common.h"
-#include "ec_commands.h"
-#include "led_common.h"
-#include "led_pwm.h"
-#include "pwm.h"
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-struct pwm_led led_color_map[] = {
-				/* Red, Green, Blue */
-	[EC_LED_COLOR_RED] =    {  100,   0,     0 },
-	[EC_LED_COLOR_GREEN] =  {    0, 100,     0 },
-	[EC_LED_COLOR_BLUE] =   {    0,   0,   100 },
-	/* The green LED seems to be brighter than the others, so turn down
-	 * green from its natural level for these secondary colors.
-	 */
-	[EC_LED_COLOR_YELLOW] = {  100,  70,     0 },
-	[EC_LED_COLOR_WHITE] =  {  100,  70,   100 },
-	[EC_LED_COLOR_AMBER] =  {  100,  20,     0 },
-};
-
-struct pwm_led pwm_leds[] = {
-	/* 2 RGB diffusers controlled by 1 set of 3 channels. */
-	[PWM_LED0] = {
-		.ch0 = PWM_CH_LED3_RED,
-		.ch1 = PWM_CH_LED2_GREEN,
-		.ch2 = PWM_CH_LED1_BLUE,
-		.enable = &pwm_enable,
-		.set_duty = &pwm_set_duty,
-	},
-};
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_RED] = 255;
-	brightness_range[EC_LED_COLOR_GREEN] = 255;
-	brightness_range[EC_LED_COLOR_BLUE] = 255;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	enum pwm_led_id pwm_id;
-
-	/* Convert ec_led_id to pwm_led_id. */
-	if (led_id == EC_LED_ID_POWER_LED)
-		pwm_id = PWM_LED0;
-	else
-		return EC_ERROR_UNKNOWN;
-
-	if (brightness[EC_LED_COLOR_RED])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_RED);
-	else if (brightness[EC_LED_COLOR_GREEN])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_GREEN);
-	else if (brightness[EC_LED_COLOR_BLUE])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_BLUE);
-	else if (brightness[EC_LED_COLOR_YELLOW])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_YELLOW);
-	else if (brightness[EC_LED_COLOR_WHITE])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_WHITE);
-	else if (brightness[EC_LED_COLOR_AMBER])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_AMBER);
-	else
-		/* Otherwise, the "color" is "off". */
-		set_pwm_led_color(pwm_id, -1);
-
-	return EC_SUCCESS;
-}
diff --git a/board/todor/sensors.c b/board/todor/sensors.c
deleted file mode 100644
index 9e34812131..0000000000
--- a/board/todor/sensors.c
+++ /dev/null
@@ -1,245 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer family-specific sensor configuration */
-#include "common.h"
-#include "accelgyro.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_bmi260.h"
-#include "driver/als_tcs3400.h"
-#include "driver/sync.h"
-#include "keyboard_scan.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "task.h"
-#include "tablet_mode.h"
-#include "util.h"
-
-/******************************************************************************/
-/* Sensors */
-static struct mutex g_lid_accel_mutex;
-static struct mutex g_base_mutex;
-
-/* BMA253 private data */
-static struct accelgyro_saved_data_t g_bma253_data;
-
-/* BMI260 private data */
-static struct bmi_drv_data_t g_bmi260_data;
-
-/* TCS3400 private data */
-static struct als_drv_data_t g_tcs3400_data = {
-	.als_cal.scale = 1,
-	.als_cal.uscale = 0,
-	.als_cal.offset = 0,
-	.als_cal.channel_scale = {
-		.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kc from VPD */
-		.cover_scale = ALS_CHANNEL_SCALE(1.0),     /* CT */
-	},
-};
-
-/*
- * TODO: b/146166425 need to calibrate ALS/RGB sensor. At default settings,
- * shining phone flashlight on sensor pegs all readings at 0xFFFF.
- */
-static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
-	.calibration.rgb_cal[X] = {
-		.offset = 0,
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kr */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		}
-	},
-	.calibration.rgb_cal[Y] = {
-		.offset = 0,
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kg */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		},
-	},
-	.calibration.rgb_cal[Z] = {
-		.offset = 0,
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kb */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		}
-	},
-	.calibration.irt = INT_TO_FP(1),
-	.saturation.again = TCS_DEFAULT_AGAIN,
-	.saturation.atime = TCS_DEFAULT_ATIME,
-};
-
-/* Rotation matrix for the lid accelerometer */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_lid_accel_mutex,
-		.drv_data = &g_bma253_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.default_range = 2, /* g, to support tablet mode */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI260,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi260_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi260_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.default_range = 4, /* g */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI260,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi260_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi260_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-	[CLEAR_ALS] = {
-		.name = "Clear Light",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_TCS3400,
-		.type = MOTIONSENSE_TYPE_LIGHT,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &tcs3400_drv,
-		.drv_data = &g_tcs3400_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = TCS3400_I2C_ADDR_FLAGS,
-		.rot_standard_ref = NULL,
-		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
-		.min_frequency = TCS3400_LIGHT_MIN_FREQ,
-		.max_frequency = TCS3400_LIGHT_MAX_FREQ,
-		.config = {
-			/* Run ALS sensor in S0 */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 1000,
-			},
-		},
-	},
-
-	[RGB_ALS] = {
-		/*
-		 * RGB channels read by CLEAR_ALS and so the i2c port and
-		 * address do not need to be defined for RGB_ALS.
-		 */
-		.name = "RGB Light",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_TCS3400,
-		.type = MOTIONSENSE_TYPE_LIGHT_RGB,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &tcs3400_rgb_drv,
-		.drv_data = &g_tcs3400_rgb_data,
-		.rot_standard_ref = NULL,
-		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
-	},
-};
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/* ALS instances when LPC mapping is needed. Each entry directs to a sensor. */
-const struct motion_sensor_t *motion_als_sensors[] = {
-	&motion_sensors[CLEAR_ALS],
-};
-BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
-
-static void baseboard_sensors_init(void)
-{
-	/* Note - BMA253 interrupt unused by EC */
-
-	/* Enable interrupt for the TCS3400 color light sensor */
-	gpio_enable_interrupt(GPIO_EC_ALS_RGB_INT_L);
-	/* Enable interrupt for the BMI260 accel/gyro sensor */
-	gpio_enable_interrupt(GPIO_EC_IMU_INT_L);
-}
-DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_DEFAULT);
-
-#ifndef TEST_BUILD
-void lid_angle_peripheral_enable(int enable)
-{
-	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
-
-	if (enable) {
-		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
-	} else {
-		/*
-		 * Ensure that the chipset is off before disabling the keyboard.
-		 * When the chipset is on, the EC keeps the keyboard enabled and
-		 * the AP decides whether to ignore input devices or not.
-		 */
-		if (!chipset_in_s0)
-			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
-	}
-}
-#endif
diff --git a/board/tomato b/board/tomato
new file mode 120000
index 0000000000..e96f559c72
--- /dev/null
+++ b/board/tomato
@@ -0,0 +1 @@
+cherry
\ No newline at end of file
diff --git a/board/treeya/battery.c b/board/treeya/battery.c
index a98a38d3e9..8dce09612b 100644
--- a/board/treeya/battery.c
+++ b/board/treeya/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/treeya/board.c b/board/treeya/board.c
index c796bf43a0..35fbd3dde3 100644
--- a/board/treeya/board.c
+++ b/board/treeya/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,38 +10,61 @@
 #include "driver/accelgyro_bmi_common.h"
 #include "driver/accelgyro_lsm6dsm.h"
 #include "extpower.h"
+#include "gpio.h"
 #include "i2c.h"
 #include "lid_switch.h"
 #include "power.h"
 #include "power_button.h"
 #include "pwm.h"
-#include "system.h"
 #include "switch.h"
+#include "system.h"
+#include "system_chip.h"
 #include "tablet_mode.h"
 #include "task.h"
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
+static uint8_t is_psl_hibernate;
+
 const enum gpio_signal hibernate_wake_pins[] = {
 	GPIO_LID_OPEN,
 	GPIO_AC_PRESENT,
 	GPIO_POWER_BUTTON_L,
 	GPIO_EC_RST_ODL,
 };
-const int hibernate_wake_pins_used =  ARRAY_SIZE(hibernate_wake_pins);
+const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 
 /* I2C port map. */
 const struct i2c_port_t i2c_ports[] = {
-	{"power",   I2C_PORT_POWER,   100, GPIO_I2C0_SCL, GPIO_I2C0_SDA},
-	{"tcpc0",   I2C_PORT_TCPC0,   400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"tcpc1",   I2C_PORT_TCPC1,   400, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-	{"thermal", I2C_PORT_THERMAL_AP, 400, GPIO_I2C3_SCL, GPIO_I2C3_SDA},
-	{"sensor",  I2C_PORT_SENSOR,  400, GPIO_I2C7_SCL, GPIO_I2C7_SDA},
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_I2C0_SCL,
+	  .sda = GPIO_I2C0_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "tcpc1",
+	  .port = I2C_PORT_TCPC1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "thermal",
+	  .port = I2C_PORT_THERMAL_AP,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_I2C7_SCL,
+	  .sda = GPIO_I2C7_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
-#ifdef HAS_TASK_MOTIONSENSE
-
 /* Motion sensors */
 static struct mutex g_lid_mutex_1;
 static struct mutex g_base_mutex_1;
@@ -51,19 +74,15 @@ static struct stprivate_data g_lis2dwl_data;
 /* Base accel private data */
 static struct lsm6dsm_data g_lsm6dsm_data = LSM6DSM_DATA;
 
-
 /* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t lsm6dsm_base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lsm6dsm_base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+						      { 0, FLOAT_TO_FP(-1), 0 },
+						      { 0, 0,
+							FLOAT_TO_FP(1) } };
 
-static const mat33_fp_t treeya_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t treeya_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+						{ FLOAT_TO_FP(1), 0, 0 },
+						{ 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t lid_accel_1 = {
 	.name = "Lid Accel",
@@ -102,8 +121,6 @@ struct motion_sensor_t base_accel_1 = {
 	.mutex = &g_base_mutex_1,
 	.drv_data = LSM6DSM_ST_DATA(g_lsm6dsm_data,
 			MOTIONSENSE_TYPE_ACCEL),
-	.int_signal = GPIO_6AXIS_INT_L,
-	.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
 	.port = I2C_PORT_ACCEL,
 	.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
 	.rot_standard_ref = &lsm6dsm_base_standard_ref,
@@ -132,10 +149,7 @@ struct motion_sensor_t base_gyro_1 = {
 	.location = MOTIONSENSE_LOC_BASE,
 	.drv = &lsm6dsm_drv,
 	.mutex = &g_base_mutex_1,
-	.drv_data = LSM6DSM_ST_DATA(g_lsm6dsm_data,
-			MOTIONSENSE_TYPE_GYRO),
-	.int_signal = GPIO_6AXIS_INT_L,
-	.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
+	.drv_data = LSM6DSM_ST_DATA(g_lsm6dsm_data, MOTIONSENSE_TYPE_GYRO),
 	.port = I2C_PORT_ACCEL,
 	.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
 	.default_range = 1000 | ROUND_UP_FLAG, /* dps */
@@ -146,10 +160,14 @@ struct motion_sensor_t base_gyro_1 = {
 
 static int board_use_st_sensor(void)
 {
-	/* sku_id 0xa8-0xa9 use ST sensors */
+	/* sku_id 0xa8-0xa9, 0xbe, 0xbf use ST sensors */
 	uint32_t sku_id = system_get_sku_id();
 
-	return sku_id == 0xa8 || sku_id == 0xa9;
+	if (sku_id == 0xa8 || sku_id == 0xa9 || sku_id == 0xbe ||
+	    sku_id == 0xbf)
+		return 1;
+	else
+		return 0;
 }
 
 /* treeya board will use two sets of lid/base sensor, we need update
@@ -157,16 +175,20 @@ static int board_use_st_sensor(void)
  */
 void board_update_sensor_config_from_sku(void)
 {
+	uint32_t sku_id = system_get_sku_id();
+
 	if (board_is_convertible()) {
 		/* sku_id a8-a9 use ST sensors */
 		if (board_use_st_sensor()) {
 			motion_sensors[LID_ACCEL] = lid_accel_1;
 			motion_sensors[BASE_ACCEL] = base_accel_1;
 			motion_sensors[BASE_GYRO] = base_gyro_1;
-		} else{
+		} else {
 			/*Need to change matrix for treeya*/
-			motion_sensors[BASE_ACCEL].rot_standard_ref = &treeya_standard_ref;
-			motion_sensors[BASE_GYRO].rot_standard_ref = &treeya_standard_ref;
+			motion_sensors[BASE_ACCEL].rot_standard_ref =
+				&treeya_standard_ref;
+			motion_sensors[BASE_GYRO].rot_standard_ref =
+				&treeya_standard_ref;
 		}
 
 		/* Enable Gyro interrupts */
@@ -174,10 +196,16 @@ void board_update_sensor_config_from_sku(void)
 	} else {
 		motion_sensor_count = 0;
 		/* Device is clamshell only */
-		tablet_set_mode(0);
+		tablet_set_mode(0, TABLET_TRIGGER_LID);
 		/* Gyro is not present, don't allow line to float */
-		gpio_set_flags(GPIO_6AXIS_INT_L,
-			       GPIO_INPUT | GPIO_PULL_DOWN);
+		gpio_set_flags(GPIO_6AXIS_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
+	}
+
+	if (sku_id == 160 || sku_id == 168 || sku_id == 169 || sku_id == 190 ||
+	    sku_id == 191) {
+		is_psl_hibernate = 0;
+	} else {
+		is_psl_hibernate = 1;
 	}
 }
 
@@ -190,4 +218,89 @@ void board_bmi160_lsm6dsm_interrupt(enum gpio_signal signal)
 		bmi160_interrupt(signal);
 }
 
-#endif
+static void system_psl_type_sel(int psl_no, uint32_t flags)
+{
+	/* Set PSL input events' type as level or edge trigger */
+	if ((flags & GPIO_INT_F_HIGH) || (flags & GPIO_INT_F_LOW))
+		CLEAR_BIT(NPCX_GLUE_PSL_CTS, psl_no + 4);
+	else if ((flags & GPIO_INT_F_RISING) || (flags & GPIO_INT_F_FALLING))
+		SET_BIT(NPCX_GLUE_PSL_CTS, psl_no + 4);
+
+	/*
+	 * Set PSL input events' polarity is low (high-to-low) active or
+	 * high (low-to-high) active
+	 */
+	if (flags & GPIO_HIB_WAKE_HIGH)
+		SET_BIT(NPCX_DEVALT(ALT_GROUP_D), 2 * psl_no);
+	else
+		CLEAR_BIT(NPCX_DEVALT(ALT_GROUP_D), 2 * psl_no);
+}
+
+int system_config_psl_mode(enum gpio_signal signal)
+{
+	int psl_no;
+	const struct gpio_info *g = gpio_list + signal;
+
+	if (g->port == GPIO_PORT_D && g->mask == MASK_PIN2) /* GPIOD2 */
+		psl_no = 0;
+	else if (g->port == GPIO_PORT_0 && (g->mask & 0x07)) /* GPIO00/01/02 */
+		psl_no = GPIO_MASK_TO_NUM(g->mask) + 1;
+	else
+		return 0;
+
+	system_psl_type_sel(psl_no, g->flags);
+	return 1;
+}
+
+void system_enter_psl_mode(void)
+{
+	/* Configure pins from GPIOs to PSL which rely on VSBY power rail. */
+	gpio_config_module(MODULE_PMU, 1);
+
+	/*
+	 * Only PSL_IN events can pull PSL_OUT to high and reboot ec.
+	 * We should treat it as wake-up pin reset.
+	 */
+	NPCX_BBRAM(BBRM_DATA_INDEX_WAKE) = HIBERNATE_WAKE_PIN;
+
+	/*
+	 * Pull PSL_OUT (GPIO85) to low to cut off ec's VCC power rail by
+	 * setting bit 5 of PDOUT(8).
+	 */
+	SET_BIT(NPCX_PDOUT(GPIO_PORT_8), 5);
+}
+
+/* Hibernate function implemented by PSL (Power Switch Logic) mode. */
+noreturn void __keep __enter_hibernate_in_psl(void)
+{
+	system_enter_psl_mode();
+	/* Spin and wait for PSL cuts power; should never return */
+	while (1)
+		;
+}
+
+void board_hibernate_late(void)
+{
+	int i;
+
+	/*
+	 * If the SKU cannot use PSL hibernate, immediately return to go the
+	 * non-PSL hibernate flow.
+	 */
+	if (!is_psl_hibernate) {
+		NPCX_KBSINPU = 0x0A;
+		return;
+	}
+
+	for (i = 0; i < hibernate_wake_pins_used; i++) {
+		/* Config PSL pins setting for wake-up inputs */
+		if (!system_config_psl_mode(hibernate_wake_pins[i]))
+			ccprintf("Invalid PSL setting in wake-up pin %d\n", i);
+	}
+
+	/* Clear all pending IRQ otherwise wfi will have no affect */
+	for (i = NPCX_IRQ_0; i < NPCX_IRQ_COUNT; i++)
+		task_clear_pending_irq(i);
+
+	__enter_hibernate_in_psl();
+}
diff --git a/board/treeya/board.h b/board/treeya/board.h
index 4bda4cb64c..75c093cd71 100644
--- a/board/treeya/board.h
+++ b/board/treeya/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,18 +12,31 @@
 
 #include "baseboard.h"
 
+/* b/203442963
+ * It's workaround to reduce keyboard's "Silver Migration".
+ * From keyboard vendor's feedback, there are two factors to cause
+ * "Silver Migration".
+ * 1. A voltage potential between trace.
+ * 2. The presence of an electrolyte , such as moisture.
+ * The reason cause voltage potential between KSIxx trace is EC enter ec
+ * hibernate PSL and turn EC's VCC1 power off. Besides KSI2, the other
+ * KSIxx will be turn off. KSI2 is powered by H1.
+ * To avoid voltage potential is keep KSIxx on. That means not to enter
+ * ec hibernate PSL.
+ */
+#undef CONFIG_HIBERNATE_PSL
+
 /*
  * By default, enable all console messages excepted HC, ACPI and event:
  * The sensor stack is generating a lot of activity.
  */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
 #undef CONFIG_HOSTCMD_DEBUG_MODE
 #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
 
 /* Power and battery LEDs */
 #define CONFIG_LED_COMMON
 #define CONFIG_CMD_LEDTEST
-#define CONFIG_LED_POWER_LED
 
 #define CONFIG_LED_ONOFF_STATES
 
@@ -37,7 +50,6 @@
 #define CONFIG_ACCELGYRO_BMI160
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCEL_INTERRUPTS
 #define CONFIG_ACCEL_KX022
 #define CONFIG_CMD_ACCELS
 #define CONFIG_CMD_ACCEL_INFO
@@ -49,7 +61,7 @@
 /*
  * Slew rate on the PP1800_SENSOR load switch requires a short delay on startup.
  */
-#undef  CONFIG_MOTION_SENSE_RESUME_DELAY_US
+#undef CONFIG_MOTION_SENSE_RESUME_DELAY_US
 #define CONFIG_MOTION_SENSE_RESUME_DELAY_US (10 * MSEC)
 
 /* Second set of sensor drivers */
@@ -60,7 +72,6 @@
 
 #ifndef __ASSEMBLER__
 
-
 enum battery_type {
 	BATTERY_SMP,
 	BATTERY_LGC,
diff --git a/board/treeya/build.mk b/board/treeya/build.mk
index 250abe6712..618554c11f 100644
--- a/board/treeya/build.mk
+++ b/board/treeya/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/treeya/ec.tasklist b/board/treeya/ec.tasklist
index fb6e2f75a1..7c9bfc2aff 100644
--- a/board/treeya/ec.tasklist
+++ b/board/treeya/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/treeya/gpio.inc b/board/treeya/gpio.inc
index 70e2e1b29c..f0de3fc62c 100644
--- a/board/treeya/gpio.inc
+++ b/board/treeya/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/treeya/led.c b/board/treeya/led.c
index 837d7a6723..60bcc33b16 100644
--- a/board/treeya/led.c
+++ b/board/treeya/led.c
@@ -1,51 +1,54 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "common.h"
-#include "led_onoff_states.h"
-#include "led_common.h"
 #include "gpio.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
-const int led_charge_lvl_1 = 5;
+__override const int led_charge_lvl_1 = 5;
 
-const int led_charge_lvl_2 = 97;
+__override const int led_charge_lvl_2 = 97;
 
-struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,  2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
 
-const struct led_descriptor
-			led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-				{LED_OFF,          0.5 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 3 * LED_ONE_SEC },
+					       { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-void led_set_color_power(enum ec_led_colors color)
+__override void led_set_color_power(enum ec_led_colors color)
 {
 	if (color == EC_LED_COLOR_WHITE)
 		gpio_set_level(GPIO_POWER_LED_3_L, LED_ON_LVL);
@@ -54,7 +57,7 @@ void led_set_color_power(enum ec_led_colors color)
 		gpio_set_level(GPIO_POWER_LED_3_L, LED_OFF_LVL);
 }
 
-void led_set_color_battery(enum ec_led_colors color)
+__override void led_set_color_battery(enum ec_led_colors color)
 {
 	switch (color) {
 	case EC_LED_COLOR_RED:
diff --git a/board/treeya/vif_override.xml b/board/treeya/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/treeya/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/trembyle/battery.c b/board/trembyle/battery.c
index 33e4e9ce5d..22724f11b4 100644
--- a/board/trembyle/battery.c
+++ b/board/trembyle/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/trembyle/board.c b/board/trembyle/board.c
index bcf1cc926c..c75f3fc732 100644
--- a/board/trembyle/board.c
+++ b/board/trembyle/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,13 +6,12 @@
 /* Trembyle board configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "button.h"
-#include "charger.h"
 #include "cbi_ec_fw_config.h"
-#include "driver/accelgyro_bmi_common.h"
+#include "charger.h"
 #include "driver/accel_kionix.h"
 #include "driver/accel_kx022.h"
+#include "driver/accelgyro_bmi_common.h"
 #include "driver/retimer/pi3dpx1207.h"
 #include "driver/retimer/pi3hdx1204.h"
 #include "driver/retimer/ps8811.h"
@@ -31,17 +30,16 @@
 #include "switch.h"
 #include "system.h"
 #include "task.h"
-#include "thermistor.h"
 #include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
 #include "usb_charge.h"
 #include "usb_mux.h"
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#ifdef HAS_TASK_MOTIONSENSE
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* Motion sensors */
 static struct mutex g_lid_mutex;
@@ -92,7 +90,7 @@ struct motion_sensor_t motion_sensors[] = {
 	 .drv_data = &g_bmi160_data,
 	 .port = I2C_PORT_SENSOR,
 	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 2, /* g, enough for laptop */
+	 .default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
 	 .rot_standard_ref = NULL,
 	 .min_frequency = BMI_ACCEL_MIN_FREQ,
 	 .max_frequency = BMI_ACCEL_MAX_FREQ,
@@ -129,8 +127,6 @@ struct motion_sensor_t motion_sensors[] = {
 
 unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
-#endif /* HAS_TASK_MOTIONSENSE */
-
 const struct power_signal_info power_signal_list[] = {
 	[X86_SLP_S3_N] = {
 		.gpio = GPIO_PCH_SLP_S3_L,
@@ -187,7 +183,7 @@ const int usb_port_enable[USBA_PORT_COUNT] = {
 const struct pi3hdx1204_tuning pi3hdx1204_tuning = {
 	.eq_ch0_ch1_offset = PI3HDX1204_EQ_DB710,
 	.eq_ch2_ch3_offset = PI3HDX1204_EQ_DB710,
-	.vod_offset = PI3HDX1204_VOD_115_ALL_CHANNELS,
+	.vod_offset = PI3HDX1204_VOD_130_ALL_CHANNELS,
 	.de_offset = PI3HDX1204_DE_DB_MINUS5,
 };
 
@@ -210,8 +206,8 @@ static void board_chipset_resume(void)
 		int val;
 
 		rv = i2c_read8(I2C_PORT_USBA0,
-				PS8811_I2C_ADDR_FLAGS + PS8811_REG_PAGE1,
-				PS8811_REG1_USB_BEQ_LEVEL, &val);
+			       PS8811_I2C_ADDR_FLAGS3 + PS8811_REG_PAGE1,
+			       PS8811_REG1_USB_BEQ_LEVEL, &val);
 		if (!rv)
 			break;
 	}
@@ -223,10 +219,12 @@ static void board_chipset_resume(void)
 	/* USB-A1 needs to increase gain to get over MB/DB connector */
 	for (retry = 0; retry < PS8811_ACCESS_RETRIES; ++retry) {
 		rv = i2c_write8(I2C_PORT_USBA1,
-				PS8811_I2C_ADDR_FLAGS + PS8811_REG_PAGE1,
+				PS8811_I2C_ADDR_FLAGS3 + PS8811_REG_PAGE1,
 				PS8811_REG1_USB_BEQ_LEVEL,
-				PS8811_BEQ_I2C_LEVEL_UP_13DB |
-				PS8811_BEQ_PIN_LEVEL_UP_18DB);
+				(PS8811_BEQ_I2C_LEVEL_UP_13DB
+				 << PS8811_BEQ_I2C_LEVEL_UP_SHIFT) |
+					(PS8811_BEQ_PIN_LEVEL_UP_18DB
+					 << PS8811_BEQ_PIN_LEVEL_UP_SHIFT));
 		if (!rv)
 			break;
 	}
@@ -236,9 +234,7 @@ static void board_chipset_resume(void)
 	}
 
 	if (ec_config_has_hdmi_retimer_pi3hdx1204()) {
-		pi3hdx1204_enable(I2C_PORT_TCPC1,
-				  PI3HDX1204_I2C_ADDR_FLAGS,
-				  1);
+		pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS, 1);
 	}
 }
 DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
@@ -249,9 +245,7 @@ static void board_chipset_suspend(void)
 	ioex_set_level(IOEX_USB_A1_RETIMER_EN, 0);
 
 	if (ec_config_has_hdmi_retimer_pi3hdx1204()) {
-		pi3hdx1204_enable(I2C_PORT_TCPC1,
-				  PI3HDX1204_I2C_ADDR_FLAGS,
-				  0);
+		pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS, 0);
 	}
 }
 DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
@@ -259,6 +253,10 @@ DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
 /*****************************************************************************
  * USB-C MUX/Retimer dynamic configuration
  */
+
+/* Place holder for second mux in USBC1 chain */
+struct usb_mux_chain usbc1_mux1;
+
 static void setup_mux(void)
 {
 	if (ec_config_has_usbc1_retimer_ps8802()) {
@@ -268,12 +266,10 @@ static void setup_mux(void)
 		 * Replace usb_muxes[USBC_PORT_C1] with the PS8802
 		 * table entry.
 		 */
-		memcpy(&usb_muxes[USBC_PORT_C1],
-		       &usbc1_ps8802,
-		       sizeof(struct usb_mux));
+		usb_muxes[USBC_PORT_C1].mux = &usbc1_ps8802;
 
 		/* Set the AMD FP5 as the secondary MUX */
-		usb_muxes[USBC_PORT_C1].next_mux = &usbc1_amd_fp5_usb_mux;
+		usbc1_mux1.mux = &usbc1_amd_fp5_usb_mux;
 
 		/* Don't have the AMD FP5 flip */
 		usbc1_amd_fp5_usb_mux.flags = USB_MUX_FLAG_SET_WITHOUT_FLIP;
@@ -285,12 +281,10 @@ static void setup_mux(void)
 		 * Replace usb_muxes[USBC_PORT_C1] with the AMD FP5
 		 * table entry.
 		 */
-		memcpy(&usb_muxes[USBC_PORT_C1],
-		       &usbc1_amd_fp5_usb_mux,
-		       sizeof(struct usb_mux));
+		usb_muxes[USBC_PORT_C1].mux = &usbc1_amd_fp5_usb_mux;
 
 		/* Set the PS8818 as the secondary MUX */
-		usb_muxes[USBC_PORT_C1].next_mux = &usbc1_ps8818;
+		usbc1_mux1.mux = &usbc1_ps8818;
 	}
 }
 
@@ -304,23 +298,29 @@ const struct pi3dpx1207_usb_control pi3dpx1207_controls[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(pi3dpx1207_controls) == USBC_PORT_COUNT);
 
-const struct usb_mux usbc0_pi3dpx1207_usb_retimer = {
-	.usb_port = USBC_PORT_C0,
-	.i2c_port = I2C_PORT_TCPC0,
-	.i2c_addr_flags = PI3DPX1207_I2C_ADDR_FLAGS,
-	.driver = &pi3dpx1207_usb_retimer,
+const struct usb_mux_chain usbc0_pi3dpx1207_usb_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.i2c_port = I2C_PORT_TCPC0,
+			.i2c_addr_flags = PI3DPX1207_I2C_ADDR_FLAGS,
+			.driver = &pi3dpx1207_usb_retimer,
+		},
 };
 
-struct usb_mux usb_muxes[] = {
+struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.i2c_port = I2C_PORT_USB_AP_MUX,
-		.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
-		.driver = &amd_fp5_usb_mux_driver,
-		.next_mux = &usbc0_pi3dpx1207_usb_retimer,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.i2c_port = I2C_PORT_USB_AP_MUX,
+			.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
+			.driver = &amd_fp5_usb_mux_driver,
+		},
+		.next = &usbc0_pi3dpx1207_usb_retimer,
 	},
 	[USBC_PORT_C1] = {
 		/* Filled in dynamically at startup */
+		.next = &usbc1_mux1,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
@@ -364,7 +364,7 @@ DECLARE_HOOK(HOOK_INIT, setup_fw_config, HOOK_PRIO_INIT_I2C + 2);
 /* Physical fans. These are logically separate from pwm_channels. */
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = -1,
 };
@@ -452,29 +452,40 @@ const struct temp_sensor_t temp_sensors[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
-const static struct ec_thermal_config thermal_thermistor = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(90),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(92),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
-	},
-	.temp_fan_off = C_TO_K(25),
-	.temp_fan_max = C_TO_K(58),
-};
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_THERMISTOR       \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(90), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(92), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(80), \
+		}, \
+		.temp_fan_off = C_TO_K(25), \
+		.temp_fan_max = C_TO_K(58), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_thermistor =
+	THERMAL_THERMISTOR;
 
-const static struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(90),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(92),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
-	},
-	.temp_fan_off = C_TO_K(25),
-	.temp_fan_max = C_TO_K(58),
-};
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(90), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(92), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(80), \
+		}, \
+		.temp_fan_off = C_TO_K(25), \
+		.temp_fan_max = C_TO_K(58), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 
 struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
 
diff --git a/board/trembyle/board.h b/board/trembyle/board.h
index 7a28379233..c04e963d1e 100644
--- a/board/trembyle/board.h
+++ b/board/trembyle/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,17 +10,16 @@
 
 #define VARIANT_ZORK_TREMBYLE
 
-#include <stdbool.h>
 #include "baseboard.h"
 
+#include <stdbool.h>
+
 #define CONFIG_USBC_RETIMER_PI3DPX1207
-#define CONFIG_MKBP_USE_GPIO
 
 /* Motion sensing drivers */
 #define CONFIG_ACCELGYRO_BMI160
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCEL_INTERRUPTS
 #define CONFIG_ACCEL_KX022
 #define CONFIG_CMD_ACCELS
 #define CONFIG_CMD_ACCEL_INFO
@@ -31,36 +30,32 @@
 #define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
 
 /* GPIO mapping from board specific name to EC common name. */
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_EC_BATT_PRES_ODL
-#define CONFIG_SCI_GPIO			GPIO_EC_FCH_SCI_ODL
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_AP_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT_L		GPIO_EC_EDP_BL_DISABLE
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_FCH_PWR_BTN_L
-#define GPIO_PCH_RSMRST_L		GPIO_EC_FCH_RSMRST_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S5_L		GPIO_SLP_S5_L
-#define GPIO_PCH_SYS_PWROK		GPIO_EC_FCH_PWROK
-#define GPIO_PCH_WAKE_L			GPIO_EC_FCH_WAKE_L
-#define GPIO_POWER_BUTTON_L		GPIO_EC_PWR_BTN_ODL
-#define GPIO_S0_PGOOD			GPIO_S0_PWROK_OD
-#define GPIO_S5_PGOOD			GPIO_EC_PWROK_OD
-#define GPIO_SYS_RESET_L		GPIO_EC_SYS_RST_L
-#define GPIO_VOLUME_DOWN_L		GPIO_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
+#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL
+#define CONFIG_SCI_GPIO GPIO_EC_FCH_SCI_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_AP_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_EDP_BL_DISABLE
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PCH_PWRBTN_L GPIO_EC_FCH_PWR_BTN_L
+#define GPIO_PCH_RSMRST_L GPIO_EC_FCH_RSMRST_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L
+#define GPIO_PCH_SYS_PWROK GPIO_EC_FCH_PWROK
+#define GPIO_PCH_WAKE_L GPIO_EC_FCH_WAKE_L
+#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL
+#define GPIO_S0_PGOOD GPIO_S0_PWROK_OD
+#define GPIO_S5_PGOOD GPIO_EC_PWROK_OD
+#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L
+#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
 
 #ifndef __ASSEMBLER__
 
-enum adc_channel {
-	ADC_TEMP_SENSOR_CHARGER,
-	ADC_TEMP_SENSOR_SOC,
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_TEMP_SENSOR_CHARGER, ADC_TEMP_SENSOR_SOC, ADC_CH_COUNT };
 
 enum battery_type {
 	BATTERY_AP18F4M,
@@ -73,11 +68,7 @@ enum mft_channel {
 	MFT_CH_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_FAN,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_FAN, PWM_CH_COUNT };
 
 enum temp_sensor_id {
 	TEMP_SENSOR_CHARGER = 0,
@@ -86,16 +77,11 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum usba_port {
-	USBA_PORT_A0 = 0,
-	USBA_PORT_A1,
-	USBA_PORT_COUNT
-};
+enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT };
 
 /*****************************************************************************
  * CBI EC FW Configuration
  */
-#include "cbi_ec_fw_config.h"
 
 /**
  * TREMBYLE_MB_USBAC
@@ -154,62 +140,53 @@ enum ec_cfg_usb_db_type {
 	TREMBYLE_DB_T_OPT3_USBAC_HDMI_MSTHUB = 2,
 };
 
+#include "cbi_ec_fw_config.h"
 
-#define HAS_USBC1_RETIMER_PS8802 \
-			(BIT(TREMBYLE_DB_T_OPT2_USBAC) | \
-			 BIT(TREMBYLE_DB_T_OPT3_USBAC_HDMI_MSTHUB))
+#define HAS_USBC1_RETIMER_PS8802         \
+	(BIT(TREMBYLE_DB_T_OPT2_USBAC) | \
+	 BIT(TREMBYLE_DB_T_OPT3_USBAC_HDMI_MSTHUB))
 
 static inline bool ec_config_has_usbc1_retimer_ps8802(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_USBC1_RETIMER_PS8802);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_USBC1_RETIMER_PS8802);
 }
 
-#define HAS_USBC1_RETIMER_PS8818 \
-			(BIT(TREMBYLE_DB_T_OPT1_USBAC_HMDI))
+#define HAS_USBC1_RETIMER_PS8818 (BIT(TREMBYLE_DB_T_OPT1_USBAC_HMDI))
 
 static inline bool ec_config_has_usbc1_retimer_ps8818(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_USBC1_RETIMER_PS8818);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_USBC1_RETIMER_PS8818);
 }
 
-#define HAS_HDMI_RETIMER_PI3HDX1204 \
-			(BIT(TREMBYLE_DB_T_OPT1_USBAC_HMDI))
+#define HAS_HDMI_RETIMER_PI3HDX1204 (BIT(TREMBYLE_DB_T_OPT1_USBAC_HMDI))
 
 static inline bool ec_config_has_hdmi_retimer_pi3hdx1204(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_HDMI_RETIMER_PI3HDX1204);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_HDMI_RETIMER_PI3HDX1204);
 }
 
-#define HAS_MST_HUB_RTD2141B \
-			(BIT(TREMBYLE_DB_T_OPT3_USBAC_HDMI_MSTHUB))
+#define HAS_MST_HUB_RTD2141B (BIT(TREMBYLE_DB_T_OPT3_USBAC_HDMI_MSTHUB))
 
 static inline bool ec_config_has_mst_hub_rtd2141b(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_MST_HUB_RTD2141B);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_MST_HUB_RTD2141B);
 }
 
-#define HAS_HDMI_CONN_HPD \
-			(BIT(TREMBYLE_DB_T_OPT1_USBAC_HMDI))
+#define HAS_HDMI_CONN_HPD (BIT(TREMBYLE_DB_T_OPT1_USBAC_HMDI))
 
 static inline bool ec_config_has_hdmi_conn_hpd(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_HDMI_CONN_HPD);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_HDMI_CONN_HPD);
 }
 
-#define PORT_TO_HPD(port) ((port == 0) \
-	? GPIO_USB_C0_HPD \
-	: (ec_config_has_usbc1_retimer_ps8802()) \
-		? GPIO_DP1_HPD \
-		: GPIO_DP2_HPD)
+#define PORT_TO_HPD(port)                                           \
+	((port == 0)				? GPIO_USB_C0_HPD : \
+	 (ec_config_has_usbc1_retimer_ps8802()) ? GPIO_DP1_HPD :    \
+						  GPIO_DP2_HPD)
 
-extern const struct usb_mux usbc0_pi3dpx1207_usb_retimer;
-extern const struct usb_mux usbc1_ps8802;
+extern const struct usb_mux_chain usbc0_pi3dpx1207_usb_retimer;
 extern const struct usb_mux usbc1_ps8818;
+extern struct usb_mux usbc1_ps8802;
 extern struct usb_mux usbc1_amd_fp5_usb_mux;
 
 void hdmi_hpd_interrupt(enum ioex_signal signal);
diff --git a/board/trembyle/build.mk b/board/trembyle/build.mk
index 4ca0cbd96f..cd58c2b91b 100644
--- a/board/trembyle/build.mk
+++ b/board/trembyle/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/trembyle/ec.tasklist b/board/trembyle/ec.tasklist
index 41b83cf4f3..4bb60ed55d 100644
--- a/board/trembyle/ec.tasklist
+++ b/board/trembyle/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/trembyle/gpio.inc b/board/trembyle/gpio.inc
index 6cc3e6fe09..7c49eef74e 100644
--- a/board/trembyle/gpio.inc
+++ b/board/trembyle/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/trembyle/led.c b/board/trembyle/led.c
index ea8e445166..ec4e93dca5 100644
--- a/board/trembyle/led.c
+++ b/board/trembyle/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,32 +8,41 @@
 #include "led_common.h"
 #include "led_onoff_states.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
-const int led_charge_lvl_1;
-const int led_charge_lvl_2 = 100;
+__override const int led_charge_lvl_1;
+__override const int led_charge_lvl_2 = 100;
 
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]       = {{EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC},
-					{EC_LED_COLOR_RED,  2 * LED_ONE_SEC} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_RED,  LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_RED,  1 * LED_ONE_SEC},
-					{LED_OFF,           3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,           LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC},
-					{EC_LED_COLOR_RED,  2 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} },
-};
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_BLUE,
+					     2 * LED_ONE_SEC },
+					   { EC_LED_COLOR_RED,
+					     2 * LED_ONE_SEC } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_BLUE,
+					    2 * LED_ONE_SEC },
+					  { EC_LED_COLOR_RED,
+					    2 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+	};
 BUILD_ASSERT(ARRAY_SIZE(led_bat_state_table) == LED_NUM_STATES);
 
 const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-void led_set_color_battery(enum ec_led_colors color)
+__override void led_set_color_battery(enum ec_led_colors color)
 {
 	switch (color) {
 	case EC_LED_COLOR_BLUE:
diff --git a/board/trembyle/vif_override.xml b/board/trembyle/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/trembyle/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/trogdor/battery.c b/board/trogdor/battery.c
index 0548a6e6d0..cffda632bc 100644
--- a/board/trogdor/battery.c
+++ b/board/trogdor/battery.c
@@ -1,45 +1,68 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Battery pack vendor provided charging profile
  */
 
-#include "battery.h"
-#include "battery_smart.h"
+#include "battery_fuel_gauge.h"
+#include "common.h"
+#include "util.h"
 
-/* Shutdown mode parameter to write to manufacturer access register */
-#define SB_SHIP_MODE_REG	SB_MANUFACTURER_ACCESS
-#define SB_SHUTDOWN_DATA	0x0010
+/*
+ * Battery info for all trogdor battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
 
-/* Battery info */
-static const struct battery_info info = {
-	.voltage_max = 8800,
-	.voltage_normal = 7700,
-	.voltage_min = 6000,
-	.precharge_current = 256, /* mA */
-	.start_charging_min_c = 0,
-	.start_charging_max_c = 50,
-	.charging_min_c = 0,
-	.charging_max_c = 60,
-	.discharging_min_c = -20,
-	.discharging_max_c = 75,
+const struct board_batt_params board_battery_info[] = {
+	/* AP16L5J */
+	[BATTERY_AP16L5J] = {
+		.fuel_gauge = {
+			.manuf_name = "PANASONIC",
+			.device_name = "AP16L5J",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.mfgacc_support = 0,
+				.reg_addr = 0x0,
+				.reg_mask = 0x4000,
+				.disconnect_val = 0x0,
+			}
+		},
+		.batt_info = {
+			.voltage_max            = 8800,
+			.voltage_normal         = 7700, /* mV */
+			.voltage_min            = 6000, /* mV */
+			.precharge_current      = 256,  /* mA */
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 50,
+			.charging_min_c         = 0,
+			.charging_max_c         = 60,
+			.discharging_min_c      = -20,
+			.discharging_max_c      = 75,
+		},
+	},
 };
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
 
-const struct battery_info *battery_get_info(void)
-{
-	return &info;
-}
-
-int board_cut_off_battery(void)
-{
-	int rv;
-
-	/* Ship mode command must be sent twice to take effect */
-	rv = sb_write(SB_SHIP_MODE_REG, SB_SHUTDOWN_DATA);
-
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	return sb_write(SB_SHIP_MODE_REG, SB_SHUTDOWN_DATA);
-}
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_AP16L5J;
diff --git a/board/trogdor/board.c b/board/trogdor/board.c
index b39e100b56..ed3d32b757 100644
--- a/board/trogdor/board.c
+++ b/board/trogdor/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,114 +7,41 @@
 
 #include "adc_chip.h"
 #include "button.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "extpower.h"
+#include "driver/accel_bma2x2.h"
 #include "driver/accelgyro_bmi_common.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
+#include "extpower.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "keyboard_scan.h"
 #include "lid_switch.h"
-#if BOARD_REV >= TROGDOR_REV1
-#include "pi3usb9201.h"
-#else
-#include "pi3usb9281.h"
-#endif /* BOARD_REV */
 #include "power.h"
 #include "power_button.h"
 #include "pwm.h"
 #include "pwm_chip.h"
-#include "system.h"
 #include "shi_chip.h"
 #include "switch.h"
+#include "system.h"
+#include "tablet_mode.h"
 #include "task.h"
+#include "usbc_config.h"
 #include "usbc_ppc.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-/* Forward declaration */
-static void tcpc_alert_event(enum gpio_signal signal);
-static void usb0_evt(enum gpio_signal signal);
-static void usb1_evt(enum gpio_signal signal);
-static void ppc_interrupt(enum gpio_signal signal);
-static void board_connect_c0_sbu(enum gpio_signal s);
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
-/* GPIO Interrupt Handlers */
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_PD_INT_ODL:
-		port = 0;
-		break;
-	case GPIO_USB_C1_PD_INT_ODL:
-		port = 1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-static void usb0_evt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
-}
-
-static void usb1_evt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12, 0);
-}
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_SWCTL_INT_ODL:
-		sn5s330_interrupt(0);
-		break;
-	case GPIO_USB_C1_SWCTL_INT_ODL:
-		sn5s330_interrupt(1);
-		break;
-	default:
-		break;
-	}
-}
-
-static void board_connect_c0_sbu_deferred(void)
-{
-	/*
-	 * If CCD_MODE_ODL asserts, it means there's a debug accessory connected
-	 * and we should enable the SBU FETs.
-	 */
-	ppc_set_sbu(0, 1);
-}
-DECLARE_DEFERRED(board_connect_c0_sbu_deferred);
-
-static void board_connect_c0_sbu(enum gpio_signal s)
-{
-	hook_call_deferred(&board_connect_c0_sbu_deferred_data, 0);
-}
-
 /* Keyboard scan setting */
-struct keyboard_scan_config keyscan_config = {
+__override struct keyboard_scan_config keyscan_config = {
 	/* Use 80 us, because KSO_02 passes through the H1. */
 	.output_settle_us = 80,
 	/*
 	 * Unmask 0x08 in [0] (KSO_00/KSI_03, the new location of Search key);
 	 * as it still uses the legacy location (KSO_01/KSI_00).
 	 */
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca
-	},
+	.actual_key_mask = { 0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, 0xa4,
+			     0xff, 0xfe, 0x55, 0xfa, 0xca },
 	/* Other values should be the same as the default configuration. */
 	.debounce_down_us = 9 * MSEC,
 	.debounce_up_us = 30 * MSEC,
@@ -125,16 +52,31 @@ struct keyboard_scan_config keyscan_config = {
 
 /* I2C port map */
 const struct i2c_port_t i2c_ports[] = {
-	{"power",   I2C_PORT_POWER,  100, GPIO_EC_I2C_POWER_SCL,
-					  GPIO_EC_I2C_POWER_SDA},
-	{"tcpc0",   I2C_PORT_TCPC0, 1000, GPIO_EC_I2C_USB_C0_PD_SCL,
-					  GPIO_EC_I2C_USB_C0_PD_SDA},
-	{"tcpc1",   I2C_PORT_TCPC1, 1000, GPIO_EC_I2C_USB_C1_PD_SCL,
-					  GPIO_EC_I2C_USB_C1_PD_SDA},
-	{"eeprom",  I2C_PORT_EEPROM, 400, GPIO_EC_I2C_EEPROM_SCL,
-					  GPIO_EC_I2C_EEPROM_SDA},
-	{"sensor",  I2C_PORT_SENSOR, 400, GPIO_EC_I2C_SENSOR_SCL,
-					  GPIO_EC_I2C_SENSOR_SDA},
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_POWER_SCL,
+	  .sda = GPIO_EC_I2C_POWER_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C0_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C0_PD_SDA },
+	{ .name = "tcpc1",
+	  .port = I2C_PORT_TCPC1,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C1_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C1_PD_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_EEPROM_SCL,
+	  .sda = GPIO_EC_I2C_EEPROM_SDA },
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_SENSOR_SCL,
+	  .sda = GPIO_EC_I2C_SENSOR_SDA },
 };
 
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
@@ -142,37 +84,22 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* Measure VBUS through a 1/10 voltage divider */
-	[ADC_VBUS] = {
-		"VBUS",
-		NPCX_ADC_CH1,
-		ADC_MAX_VOLT * 10,
-		ADC_READ_MAX + 1,
-		0
-	},
+	[ADC_VBUS] = { "VBUS", NPCX_ADC_CH1, ADC_MAX_VOLT * 10,
+		       ADC_READ_MAX + 1, 0 },
 	/*
 	 * Adapter current output or battery charging/discharging current (uV)
 	 * 18x amplification on charger side.
 	 */
-	[ADC_AMON_BMON] = {
-		"AMON_BMON",
-		NPCX_ADC_CH2,
-		ADC_MAX_VOLT * 1000 / 18,
-		ADC_READ_MAX + 1,
-		0
-	},
+	[ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH2, ADC_MAX_VOLT * 1000 / 18,
+			    ADC_READ_MAX + 1, 0 },
 	/*
 	 * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read
 	 * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and
 	 * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we
 	 * only divide by 2 (enough to avoid precision issues).
 	 */
-	[ADC_PSYS] = {
-		"PSYS",
-		NPCX_ADC_CH3,
-		ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1),
-		2,
-		0
-	},
+	[ADC_PSYS] = { "PSYS", NPCX_ADC_CH3,
+		       ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), 2, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
@@ -183,136 +110,17 @@ const struct pwm_t pwm_channels[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
-/* Power Path Controller */
-struct ppc_config_t ppc_chips[] = {
-	{
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	{
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-};
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/* TCPC mux configuration */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-
-/*
- * Port-0/1 USB mux driver.
- *
- * The USB mux is handled by TCPC chip and the HPD update is through a GPIO
- * to AP. But the TCPC chip is also needed to know the HPD status; otherwise,
- * the mux misbehaves.
- */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	},
-	{
-		.usb_port = 1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	}
-};
-
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_USB_A_5V,
-};
-
-/* BC1.2 */
-#if BOARD_REV >= TROGDOR_REV1
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_POWER,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	{
-		.i2c_port = I2C_PORT_EEPROM,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-#else
-struct pi3usb9281_config pi3usb9281_chips[] = {
-	{
-		.i2c_port = I2C_PORT_POWER,
-	},
-	{
-		.i2c_port = I2C_PORT_EEPROM,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9281_chips) ==
-	     CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT);
-#endif /* BOARD_REV */
-
 /* Initialize board. */
 static void board_init(void)
 {
-	/* Enable BC1.2 interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_L);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L);
-
 	/* Enable interrupt for BMI160 sensor */
 	gpio_enable_interrupt(GPIO_ACCEL_GYRO_INT_L);
 
-	/*
-	 * The H1 SBU line for CCD are behind PPC chip. The PPC internal FETs
-	 * for SBU may be disconnected after DP alt mode is off. Should enable
-	 * the CCD_MODE_ODL interrupt to make sure the SBU FETs are connected.
-	 */
-	gpio_enable_interrupt(GPIO_CCD_MODE_ODL);
-
 	/* Set the backlight duty cycle to 0. AP will override it later. */
 	pwm_set_duty(PWM_CH_DISPLIGHT, 0);
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
-void board_tcpc_init(void)
-{
-	/* Only reset TCPC if not sysjump */
-	if (!system_jumped_late()) {
-		/* TODO(crosbug.com/p/61098): How long do we need to wait? */
-		board_reset_pd_mcu();
-	}
-
-	/* Enable PPC interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_SWCTL_INT_ODL);
-
-	/* Enable TCPC interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL);
-
-	/*
-	 * Initialize HPD to low; after sysjump SOC needs to see
-	 * HPD pulse to enable video path
-	 */
-	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		usb_mux_hpd_update(port, 0, 0);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
-
 /* Called on AP S0 -> S3 transition */
 static void board_chipset_suspend(void)
 {
@@ -335,162 +143,49 @@ static void board_chipset_resume(void)
 }
 DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
 
-void board_set_switchcap_power(int enable)
-{
-	gpio_set_level(GPIO_SWITCHCAP_ON, enable);
-}
-
-int board_is_switchcap_enabled(void)
-{
-	return gpio_get_level(GPIO_SWITCHCAP_ON);
-}
-
-int board_is_switchcap_power_good(void)
-{
-	return gpio_get_level(GPIO_DA9313_GPIO0);
-}
-
-void board_reset_pd_mcu(void)
-{
-	cprints(CC_USB, "Resetting TCPCs...");
-	cflush();
-
-	gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
-	gpio_set_level(GPIO_USB_C1_PD_RST_ODL, 0);
-	msleep(PS8XXX_RESET_DELAY_MS);
-	gpio_set_level(GPIO_USB_C0_PD_RST_L, 1);
-	gpio_set_level(GPIO_USB_C1_PD_RST_ODL, 1);
-	msleep(PS8805_FW_INIT_DELAY_MS);
-}
-
-void board_set_tcpc_power_mode(int port, int mode)
-{
-	/* Ignore the "mode" to turn the chip on.  We can only do a reset. */
-	if (mode)
-		return;
-
-	board_reset_pd_mcu();
-}
-
-int board_vbus_sink_enable(int port, int enable)
-{
-	/* Both ports are controlled by PPC SN5S330 */
-	return ppc_vbus_sink_enable(port, enable);
-}
-
-int board_is_sourcing_vbus(int port)
-{
-	/* Both ports are controlled by PPC SN5S330 */
-	return ppc_is_sourcing_vbus(port);
-}
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* TODO(b/120231371): Notify AP */
-	CPRINTS("p%d: overcurrent!", port);
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	int i;
-
-	if (!is_real_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	if (port == CHARGE_PORT_NONE) {
-		CPRINTS("Disabling all charging port");
-
-		/* Disable all ports. */
-		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-			/*
-			 * Do not return early if one fails otherwise we can
-			 * get into a boot loop assertion failure.
-			 */
-			if (board_vbus_sink_enable(i, 0))
-				CPRINTS("Disabling p%d sink path failed.", i);
-		}
-
-		return EC_SUCCESS;
-	}
-
-	/* Check if the port is sourcing VBUS. */
-	if (board_is_sourcing_vbus(port)) {
-		CPRINTS("Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-
-	CPRINTS("New charge port: p%d", port);
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		if (i == port)
-			continue;
-
-		if (board_vbus_sink_enable(i, 0))
-			CPRINTS("p%d: sink path disable failed.", i);
-	}
-
-	/* Enable requested charge port. */
-	if (board_vbus_sink_enable(port, 1)) {
-		CPRINTS("p%d: sink path enable failed.", port);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	/*
-	 * Ignore lower charge ceiling on PD transition if our battery is
-	 * critical, as we may brownout.
-	 */
-	if (supplier == CHARGE_SUPPLIER_PD &&
-	    charge_ma < 1500 &&
-	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
-		CPRINTS("Using max ilim %d", max_ma);
-		charge_ma = max_ma;
-	}
-
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
-		if (gpio_get_level(GPIO_USB_C0_PD_RST_L))
-			status |= PD_STATUS_TCPC_ALERT_0;
-	if (!gpio_get_level(GPIO_USB_C1_PD_INT_ODL))
-		if (gpio_get_level(GPIO_USB_C1_PD_RST_ODL))
-			status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
 /* Mutexes */
 static struct mutex g_base_mutex;
+static struct mutex g_lid_mutex;
 
 static struct bmi_drv_data_t g_bmi160_data;
+static struct accelgyro_saved_data_t g_bma255_data;
 
 /* Matrix to rotate accelerometer into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0,  0},
-	{ 0,  FLOAT_TO_FP(-1),  0},
-	{ 0,  0, FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+				       { 0, FLOAT_TO_FP(-1), 0 },
+				       { 0, 0, FLOAT_TO_FP(-1) } };
+
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					     { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t motion_sensors[] = {
+	[LID_ACCEL] = {
+	 .name = "Lid Accel",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_BMA255,
+	 .type = MOTIONSENSE_TYPE_ACCEL,
+	 .location = MOTIONSENSE_LOC_LID,
+	 .drv = &bma2x2_accel_drv,
+	 .mutex = &g_lid_mutex,
+	 .drv_data = &g_bma255_data,
+	 .port = I2C_PORT_SENSOR,
+	 .i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
+	 .rot_standard_ref = &lid_standard_ref,
+	 .default_range = 2, /* g, to support lid angle calculation. */
+	 .min_frequency = BMA255_ACCEL_MIN_FREQ,
+	 .max_frequency = BMA255_ACCEL_MAX_FREQ,
+	 .config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+		/* Sensor on for lid angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	 },
+	},
 	/*
 	 * Note: bmi160: supports accelerometer and gyro sensor
 	 * Requirement: accelerometer sensor must init before gyro sensor
@@ -498,7 +193,7 @@ struct motion_sensor_t motion_sensors[] = {
 	 */
 	[BASE_ACCEL] = {
 	 .name = "Base Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3_S5,
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
 	 .chip = MOTIONSENSE_CHIP_BMI160,
 	 .type = MOTIONSENSE_TYPE_ACCEL,
 	 .location = MOTIONSENSE_LOC_BASE,
@@ -515,11 +210,15 @@ struct motion_sensor_t motion_sensors[] = {
 		 [SENSOR_CONFIG_EC_S0] = {
 			 .odr = 10000 | ROUND_UP_FLAG,
 		 },
+		 /* Sensor on for lid angle detection */
+		 [SENSOR_CONFIG_EC_S3] = {
+			 .odr = 10000 | ROUND_UP_FLAG,
+		 },
 	 },
 	},
 	[BASE_GYRO] = {
 	 .name = "Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3_S5,
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
 	 .chip = MOTIONSENSE_CHIP_BMI160,
 	 .type = MOTIONSENSE_TYPE_GYRO,
 	 .location = MOTIONSENSE_LOC_BASE,
diff --git a/board/trogdor/board.h b/board/trogdor/board.h
index e593207f29..2c8e67d26b 100644
--- a/board/trogdor/board.h
+++ b/board/trogdor/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,32 +10,29 @@
 
 #include "baseboard.h"
 
-/* Board revision */
-#include "board_revs.h"
-
 /* TODO(waihong): Remove the following bringup features */
 #define CONFIG_BRINGUP
 #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands. */
 #define CONFIG_USB_PD_DEBUG_LEVEL 3
-#define CONFIG_CMD_AP_RESET_LOG
 #define CONFIG_CMD_GPIO_EXTENDED
 #define CONFIG_CMD_POWERINDEBUG
 #define CONFIG_I2C_DEBUG
 
 /* Internal SPI flash on NPCX7 */
-#define CONFIG_FLASH_SIZE (1024 * 1024)  /* 1MB internal spi flash */
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */
 
 /* Keyboard */
-#define CONFIG_KEYBOARD_BOARD_CONFIG
+#define CONFIG_KEYBOARD_PROTOCOL_MKBP
+
 #define CONFIG_PWM_KBLIGHT
 
+/* Battery */
+#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
+#define CONFIG_BATTERY_REVIVE_DISCONNECT
+#define CONFIG_BATTERY_FUEL_GAUGE
+
 /* BC 1.2 Charger */
-#if BOARD_REV >= TROGDOR_REV1
 #define CONFIG_BC12_DETECT_PI3USB9201
-#else
-#define CONFIG_BC12_DETECT_PI3USB9281
-#define CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT 2
-#endif /* BOARD_REV */
 
 /* USB */
 #define CONFIG_USB_PD_TCPM_PS8805
@@ -47,49 +44,54 @@
 #define CONFIG_USB_PORT_POWER_DUMB
 
 /* Sensors */
+/* BMI160 Base accel/gyro */
 #define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCEL_INTERRUPTS
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 #define OPT3001_I2C_ADDR_FLAGS OPT3001_I2C_ADDR1_FLAGS
 
+/* BMA253 lid accel */
+#define CONFIG_ACCEL_BMA255
+#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
+
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+#define CONFIG_LID_ANGLE_UPDATE
+
+#define CONFIG_TABLET_MODE
+#define CONFIG_TABLET_MODE_SWITCH
+#define CONFIG_GMR_TABLET_MODE
+
 /* GPIO alias */
 #define GPIO_AC_PRESENT GPIO_ACOK_OD
 #define GPIO_WP_L GPIO_EC_WP_ODL
+#define GPIO_SWITCHCAP_PG GPIO_SWITCHCAP_GPIO_1
+#define GPIO_ACOK_OD GPIO_CHG_ACOK_OD
 
 #ifndef __ASSEMBLER__
 
 #include "gpio_signal.h"
 #include "registers.h"
 
-enum adc_channel {
-	ADC_VBUS,
-	ADC_AMON_BMON,
-	ADC_PSYS,
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_VBUS, ADC_AMON_BMON, ADC_PSYS, ADC_CH_COUNT };
 
 /* Motion sensors */
 enum sensor_id {
-	BASE_ACCEL = 0,
+	LID_ACCEL = 0,
+	BASE_ACCEL,
 	BASE_GYRO,
 	SENSOR_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_DISPLIGHT,
-	PWM_CH_COUNT
+enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_DISPLIGHT, PWM_CH_COUNT };
+
+/* List of possible batteries */
+enum battery_type {
+	BATTERY_AP16L5J,
+	BATTERY_TYPE_COUNT,
 };
 
-/* Swithcap functions */
-void board_set_switchcap_power(int enable);
-int board_is_switchcap_enabled(void);
-int board_is_switchcap_power_good(void);
-/* Custom function to indicate if sourcing VBUS */
-int board_is_sourcing_vbus(int port);
-/* Enable VBUS sink for a given port */
-int board_vbus_sink_enable(int port, int enable);
 /* Reset all TCPCs. */
 void board_reset_pd_mcu(void);
 void board_set_tcpc_power_mode(int port, int mode);
diff --git a/board/trogdor/board_revs.h b/board/trogdor/board_revs.h
deleted file mode 100644
index 9d3273f813..0000000000
--- a/board/trogdor/board_revs.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_BOARD_REVS_H
-#define __CROS_EC_BOARD_REVS_H
-
-#define TROGDOR_REV0 0
-#define TROGDOR_REV1 1
-#define TROGDOR_REV_LAST    TROGDOR_REV1
-
-#define TROGDOR_REV_DEFAULT TROGDOR_REV0
-
-#if !defined(BOARD_REV)
-#define BOARD_REV TROGDOR_REV_DEFAULT
-#endif
-
-#if BOARD_REV < TROGDOR_REV0 || BOARD_REV > TROGDOR_REV_LAST
-#error "Board revision out of range"
-#endif
-
-#endif /* __CROS_EC_BOARD_REVS_H */
diff --git a/board/trogdor/build.mk b/board/trogdor/build.mk
index c0a0e78c12..becaf09262 100644
--- a/board/trogdor/build.mk
+++ b/board/trogdor/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -8,7 +8,12 @@
 
 CHIP:=npcx
 CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m7wb
+CHIP_VARIANT:=npcx7m6fc
 BASEBOARD:=trogdor
 
-board-y=battery.o board.o led.o
+board-y+=battery.o
+board-y+=board.o
+board-y+=hibernate.o
+board-y+=led.o
+board-y+=switchcap.o
+board-y+=usbc_config.o
diff --git a/board/trogdor/ec.tasklist b/board/trogdor/ec.tasklist
index eb14fab204..97b5046f7f 100644
--- a/board/trogdor/ec.tasklist
+++ b/board/trogdor/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/trogdor/gpio.inc b/board/trogdor/gpio.inc
index e8b560f9a6..63d6e84963 100644
--- a/board/trogdor/gpio.inc
+++ b/board/trogdor/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,26 +8,25 @@
 /* Declare symbolic names for all the GPIOs that we care about.
  * Note: Those with interrupt handlers must be declared first. */
 
-/* USB-C interrupts */
+/* USB interrupts */
 GPIO_INT(USB_C0_PD_INT_ODL,    PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-0 TCPC */
 GPIO_INT(USB_C1_PD_INT_ODL,    PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-1 TCPC */
 GPIO_INT(USB_C0_SWCTL_INT_ODL, PIN(0, 3), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-0 PPC */
 GPIO_INT(USB_C1_SWCTL_INT_ODL, PIN(4, 0), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-1 PPC */
-GPIO_INT(USB_C0_BC12_INT_L,    PIN(6, 1), GPIO_INT_FALLING, usb0_evt)  /* Interrupt from port-0 BC1.2 */
-GPIO_INT(USB_C1_BC12_INT_L,    PIN(8, 2), GPIO_INT_FALLING, usb1_evt)  /* Interrupt from port-1 BC1.2 */
+GPIO_INT(USB_C0_BC12_INT_L,    PIN(6, 1), GPIO_INT_FALLING | GPIO_PULL_UP, usb0_evt)  /* Interrupt from port-0 BC1.2 */
+GPIO_INT(USB_C1_BC12_INT_L,    PIN(8, 2), GPIO_INT_FALLING | GPIO_PULL_UP, usb1_evt)  /* Interrupt from port-1 BC1.2 */
+GPIO_INT(USB_A0_OC_ODL,        PIN(D, 1), GPIO_INT_BOTH | GPIO_PULL_UP, usba_oc_interrupt)
 
 /* System interrupts */
-GPIO_INT(ACOK_OD,           PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)  /* AC OK? */
-GPIO_INT(CCD_MODE_ODL,      PIN(E, 3), GPIO_INT_FALLING, board_connect_c0_sbu)  /* Case Closed Debug Mode */
+GPIO_INT(CHG_ACOK_OD,       PIN(0, 0), GPIO_INT_BOTH, extpower_interrupt)  /* ACOK */
 GPIO_INT(EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)  /* Power button */
 GPIO_INT(EC_VOLDN_BTN_ODL,  PIN(7, 0), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Up button */
 GPIO_INT(EC_VOLUP_BTN_ODL,  PIN(F, 2), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Down button */
 GPIO_INT(EC_WP_ODL,         PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)  /* Write protection */
-GPIO_INT(LID_OPEN_EC,       PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)  /* Lid open? */
+GPIO_INT(LID_OPEN_EC,       PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)  /* Lid open */
 GPIO_INT(AP_RST_L,          PIN(C, 1), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_ap_rst_interrupt)  /* PMIC to signal AP reset */
-GPIO_INT(PS_HOLD,           PIN(A, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V, power_signal_interrupt)  /* Indicate when AP triggers reset/shutdown */
-GPIO_INT(PMIC_FAULT_L,      PIN(A, 3), GPIO_INT_BOTH | GPIO_SEL_1P8V, power_signal_interrupt)  /* Any PMIC fault? */
-GPIO_INT(AP_SUSPEND,        PIN(5, 7), GPIO_INT_BOTH | GPIO_SEL_1P8V, power_signal_interrupt)  /* Suspend signal from PMIC */
+GPIO_INT(PS_HOLD,           PIN(A, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, power_signal_interrupt)  /* Indicate when AP triggers reset/shutdown */
+GPIO_INT(AP_SUSPEND,        PIN(5, 7), GPIO_INT_BOTH, power_signal_interrupt)  /* Suspend signal from PMIC */
 GPIO_INT(DEPRECATED_AP_RST_REQ, PIN(C, 2), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V, power_signal_interrupt) /* Deprecated AP initiated reset indicator */
 /*
  * When switch-cap is off, the POWER_GOOD signal is floating. Need a pull-down
@@ -40,32 +39,26 @@ GPIO_INT(WARM_RESET_L,      PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_wa
 GPIO_INT(AP_EC_SPI_CS_L,    PIN(5, 3), GPIO_INT_FALLING | GPIO_PULL_DOWN, shi_cs_event)  /* EC SPI Chip Select */
 
 /* Sensor interrupts */
-GPIO_INT(ACCEL_GYRO_INT_L,  PIN(A, 0), GPIO_INT_FALLING | GPIO_SEL_1P8V, bmi160_interrupt)  /* Accelerometer/gyro interrupt */
+GPIO_INT(TABLET_MODE_L,     PIN(C, 6), GPIO_INT_BOTH, gmr_tablet_switch_isr)
+GPIO_INT(ACCEL_GYRO_INT_L,  PIN(A, 0), GPIO_INT_FALLING, bmi160_interrupt)  /* Accelerometer/gyro interrupt */
 
 /*
- * EC_RST_ODL acts as a wake source from PSL hibernate mode. However, it does
- * not need to be an interrupt for normal EC operations. Thus, configure it as
- * GPIO_INT_BOTH with wake on low-to-high edge using GPIO_HIB_WAKE_HIGH so that
- * PSL common code can configure PSL_IN correctly.
- *
- * Use the rising edge to wake EC up. If we chose the falling edge, it would
- * still wake EC up, but EC is in an intermediate state until the signal goes
- * back to high.
+ * EC_RST_ODL used to be a wake source from PSL mode. However, we disabled
+ * the PSL mode. This GPIO does nothing now. Simply set it an INPUT.
  */
-GPIO(EC_RST_ODL,            PIN(0, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH)  /* Wake source: EC reset */
+GPIO(EC_RST_ODL,            PIN(0, 2), GPIO_INPUT)     /* EC reset */
 GPIO(EC_ENTERING_RW,        PIN(E, 1), GPIO_OUT_LOW)   /* Indicate when EC is entering RW code */
+GPIO(CCD_MODE_ODL,          PIN(E, 3), GPIO_INPUT)     /* Case Closed Debug Mode */
 GPIO(EC_BATT_PRES_ODL,      PIN(E, 5), GPIO_INPUT)     /* Battery Present */
 
 /* PMIC/AP 1.8V */
-GPIO(PMIC_RESIN_L,          PIN(3, 2), GPIO_ODR_HIGH | GPIO_SEL_1P8V)  /* PMIC reset trigger */
-GPIO(PMIC_KPD_PWR_ODL,      PIN(D, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V)  /* PMIC power button */
+GPIO(PMIC_RESIN_L,          PIN(3, 2), GPIO_ODR_HIGH)  /* PMIC reset trigger */
+GPIO(PMIC_KPD_PWR_ODL,      PIN(D, 6), GPIO_ODR_HIGH)  /* PMIC power button */
 GPIO(EC_INT_L,              PIN(A, 2), GPIO_ODR_HIGH)  /* Interrupt line between AP and EC */
-GPIO(QSIP_ON,               PIN(5, 0), GPIO_OUT_LOW)   /* Not used, for non-switchcap testing */
 
 /* Power enables */
+GPIO(HIBERNATE_L,           PIN(5, 2), GPIO_ODR_HIGH)  /* EC hibernate */
 GPIO(SWITCHCAP_ON,          PIN(D, 5), GPIO_OUT_LOW)   /* Enable switch cap */
-/* TODO(waihong): Remove it. The VBOB switch is for backup. */
-GPIO(VBOB_EN,               PIN(D, 3), GPIO_OUT_LOW)   /* Enable VBOB */
 GPIO(EN_PP3300_A,           PIN(A, 6), GPIO_OUT_LOW)   /* Enable PP3300 */
 GPIO(EN_PP5000_A,           PIN(6, 7), GPIO_OUT_LOW)   /* Enable PP5000 */
 GPIO(EC_BL_DISABLE_L,       PIN(B, 6), GPIO_OUT_LOW)   /* Backlight disable signal from EC */
@@ -78,26 +71,29 @@ GPIO(TRACKPAD_INT_GATE,     PIN(7, 4), GPIO_OUT_LOW)
 
 /* USB-C */
 GPIO(USB_C0_PD_RST_L,       PIN(F, 1), GPIO_OUT_HIGH)  /* Port-0 TCPC chip reset */
-GPIO(USB_C1_PD_RST_ODL,     PIN(E, 4), GPIO_ODR_HIGH)  /* Port-1 TCPC chip reset */
-GPIO(DP_MUX_OE_L,           PIN(9, 6), GPIO_OUT_HIGH)  /* DP mux enable */
-GPIO(DP_MUX_SEL,            PIN(4, 5), GPIO_OUT_HIGH)  /* DP mux selection: L:C0, H:C1 */
+GPIO(USB_C1_PD_RST_L,       PIN(E, 4), GPIO_OUT_HIGH)  /* Port-1 TCPC chip reset */
+GPIO(DP_MUX_OE_L,           PIN(9, 6), GPIO_ODR_HIGH)  /* DP mux enable, actually Open-Drain */
+GPIO(DP_MUX_SEL,            PIN(4, 5), GPIO_OUT_LOW)   /* DP mux selection: L:C0, H:C1 */
 GPIO(DP_HOT_PLUG_DET,       PIN(9, 5), GPIO_OUT_LOW)   /* DP HPD to AP */
-/* TODO(waihong): Remove it from schematic. No use. */
-GPIO(USBC_MUX_CONF0,        PIN(5, 1), GPIO_INPUT)
-GPIO(USB_C0_VBUS_DET_L,     PIN(6, 2), GPIO_INPUT)     /* Deprecated BC1.2 VBUS detection on port-0 */
-GPIO(USB_C1_VBUS_DET_L,     PIN(8, 3), GPIO_INPUT)     /* Deprecated BC1.2 VBUS detection on port-1 */
 
 /* USB-A */
 GPIO(EN_USB_A_5V,           PIN(8, 6), GPIO_OUT_LOW)
 GPIO(USB_A_CDP_ILIM_EN_L,   PIN(7, 5), GPIO_OUT_HIGH)  /* H:CDP, L:SDP. Only one USB-A port, always CDP */
-GPIO(USB_A0_OC_ODL,         PIN(D, 1), GPIO_ODR_HIGH)
 
 /* LEDs */
-GPIO(EC_CHG_LED_Y_C0,       PIN(C, 3), GPIO_OUT_LOW)
-GPIO(EC_CHG_LED_W_C0,       PIN(C, 4), GPIO_OUT_LOW)
-/* TODO(waihong): NC in the schematic. The C1 subboard doesn't have any LED. */
-GPIO(EC_CHG_LED_Y_C1,       PIN(6, 0), GPIO_OUT_LOW)
-GPIO(EC_CHG_LED_W_C1,       PIN(C, 0), GPIO_OUT_LOW)
+GPIO(EC_CHG_LED_Y_C0,       PIN(6, 0), GPIO_OUT_LOW)
+GPIO(EC_CHG_LED_W_C0,       PIN(C, 0), GPIO_OUT_LOW)
+GPIO(EC_CHG_LED_Y_C1,       PIN(C, 3), GPIO_OUT_LOW)
+GPIO(EC_CHG_LED_W_C1,       PIN(C, 4), GPIO_OUT_LOW)
+
+/*
+ * SPI host interface - enable PDs by default. These will be made functional
+ * by the SHI driver when the AP powers up, and restored back to GPIO when
+ * the AP powers down.
+ */
+GPIO(AP_EC_SPI_MOSI,        PIN(4, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(AP_EC_SPI_MISO,        PIN(4, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(AP_EC_SPI_CLK,         PIN(5, 5), GPIO_INPUT | GPIO_PULL_DOWN)
 
 /* PWM */
 GPIO(KB_BL_PWM,             PIN(8, 0), GPIO_INPUT)     /* PWM3 */
@@ -133,7 +129,36 @@ GPIO(SKU_ID2,               PIN(D, 4), GPIO_INPUT)
  * GPIO0 is configured as PVC_PG. When the chip in power down mode, it outputs
  * high-Z. Set pull-down to avoid floating.
  */
-GPIO(DA9313_GPIO0,          PIN(E, 2), GPIO_INPUT | GPIO_PULL_DOWN) /* Switchcap GPIO0 */
+GPIO(SWITCHCAP_GPIO_1,      PIN(E, 2), GPIO_INPUT | GPIO_PULL_DOWN) /* Switchcap GPIO0 */
+
+/* Special straps */
+GPIO(ARM_X86,               PIN(6, 6), GPIO_OUT_LOW)  /* NC, low for power saving */
+
+/* Unused GPIOs, NC. */
+UNUSED(PIN(5, 1))
+UNUSED(PIN(D, 0))
+UNUSED(PIN(F, 3))
+UNUSED(PIN(9, 4))
+UNUSED(PIN(9, 7))
+UNUSED(PIN(A, 7))
+UNUSED(PIN(B, 0))
+UNUSED(PIN(A, 5))
+UNUSED(PIN(3, 5))
+UNUSED(PIN(7, 2))
+UNUSED(PIN(8, 1))
+UNUSED(PIN(3, 7))
+UNUSED(PIN(7, 6))
+UNUSED(PIN(3, 4))
+UNUSED(PIN(C, 5))
+UNUSED(PIN(7, 3))
+UNUSED(PIN(D, 7))
+UNUSED(PIN(A, 3))
+UNUSED(PIN(6, 2))
+UNUSED(PIN(0, 4))
+UNUSED(PIN(8, 3))
+UNUSED(PIN(B, 1))
+UNUSED(PIN(5, 0))
+UNUSED(PIN(D, 3))
 
 /* Alternate functions GPIO definitions */
 ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)            /* UART (GPIO64/65) */
@@ -147,10 +172,6 @@ ALTERNATE(PIN_MASK(4, 0xC0), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SDO (GPIO47),
 ALTERNATE(PIN_MASK(5, 0x28), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SCLK (GPIO55), SHI_CS# (GPIO53) */
 ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)             /* PWM3 (GPIO80) - KB_BL_PWM */
 ALTERNATE(PIN_MASK(B, 0x80), 1, MODULE_PWM, 0)             /* PWM5 (GPIOB7) - EDP_BKLTCTL */
-ALTERNATE(PIN_MASK(D, 0x04), 1, MODULE_PMU, 0)             /* PSL_IN1 (GPIOD2) - LID_OPEN_EC */
-ALTERNATE(PIN_MASK(0, 0x01), 1, MODULE_PMU, 0)             /* PSL_IN2 (GPIO00) - ACOK_OD */
-ALTERNATE(PIN_MASK(0, 0x02), 1, MODULE_PMU, 0)             /* PSL_IN3 (GPIO01) - EC_PWR_BTN_ODL */
-ALTERNATE(PIN_MASK(0, 0x04), 1, MODULE_PMU, 0)             /* PSL_IN4 (GPIO02) - EC_RST_ODL */
 
 /* Keyboard */
 #define GPIO_KB_INPUT           (GPIO_INPUT | GPIO_PULL_UP)
diff --git a/board/trogdor/hibernate.c b/board/trogdor/hibernate.c
new file mode 100644
index 0000000000..9b64e85053
--- /dev/null
+++ b/board/trogdor/hibernate.c
@@ -0,0 +1,16 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "gpio.h"
+
+void board_hibernate(void)
+{
+	/*
+	 * Sensors are unpowered in hibernate. Apply PD to the
+	 * interrupt lines such that they don't float.
+	 */
+	gpio_set_flags(GPIO_ACCEL_GYRO_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
+	gpio_set_flags(GPIO_LID_ACCEL_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
+}
diff --git a/board/trogdor/led.c b/board/trogdor/led.c
index 3af5776e12..1fdab30f5a 100644
--- a/board/trogdor/led.c
+++ b/board/trogdor/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -31,15 +31,15 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static void side_led_set_color(int port, enum led_color color)
 {
 	gpio_set_level(port ? GPIO_EC_CHG_LED_Y_C1 : GPIO_EC_CHG_LED_Y_C0,
-		(color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
+		       (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
 	gpio_set_level(port ? GPIO_EC_CHG_LED_W_C1 : GPIO_EC_CHG_LED_W_C0,
-		(color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF);
+		       (color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF);
 }
 
 void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
@@ -90,20 +90,20 @@ static void set_active_port_color(enum led_color color)
 static void board_led_set_battery(void)
 {
 	static int battery_ticks;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
 		/* Always indicate when charging, even in suspend. */
 		set_active_port_color(LED_AMBER);
 		break;
-	case PWR_STATE_DISCHARGE:
+	case LED_PWRS_DISCHARGE:
 		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
 			if (charge_get_percent() <= 10)
-				side_led_set_color(0,
-				   (battery_ticks & 0x4) ? LED_WHITE : LED_OFF);
+				side_led_set_color(0, (battery_ticks & 0x4) ?
+							      LED_WHITE :
+							      LED_OFF);
 			else
 				side_led_set_color(0, LED_OFF);
 		}
@@ -111,19 +111,19 @@ static void board_led_set_battery(void)
 		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
 			side_led_set_color(1, LED_OFF);
 		break;
-	case PWR_STATE_ERROR:
-		set_active_port_color((battery_ticks & 0x2) ?
-				LED_WHITE : LED_OFF);
+	case LED_PWRS_ERROR:
+		set_active_port_color((battery_ticks & 0x2) ? LED_WHITE :
+							      LED_OFF);
 		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
+	case LED_PWRS_CHARGE_NEAR_FULL:
 		set_active_port_color(LED_WHITE);
 		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			set_active_port_color((battery_ticks & 0x4) ?
-					LED_AMBER : LED_OFF);
-		else
-			set_active_port_color(LED_WHITE);
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		set_active_port_color(LED_WHITE);
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		set_active_port_color((battery_ticks & 0x4) ? LED_AMBER :
+							      LED_OFF);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
diff --git a/board/trogdor/switchcap.c b/board/trogdor/switchcap.c
new file mode 100644
index 0000000000..5173e27f75
--- /dev/null
+++ b/board/trogdor/switchcap.c
@@ -0,0 +1,22 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "gpio.h"
+#include "power/qcom.h"
+
+void board_set_switchcap_power(int enable)
+{
+	gpio_set_level(GPIO_SWITCHCAP_ON, enable);
+}
+
+int board_is_switchcap_enabled(void)
+{
+	return gpio_get_level(GPIO_SWITCHCAP_ON);
+}
+
+int board_is_switchcap_power_good(void)
+{
+	return gpio_get_level(GPIO_SWITCHCAP_PG);
+}
diff --git a/board/trogdor/usbc_config.c b/board/trogdor/usbc_config.c
new file mode 100644
index 0000000000..270c6c0d8f
--- /dev/null
+++ b/board/trogdor/usbc_config.c
@@ -0,0 +1,365 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Trogdor board-specific USB-C configuration */
+
+#include "bc12/pi3usb9201_public.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "charger/isl923x_public.h"
+#include "common.h"
+#include "config.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "ppc/sn5s330_public.h"
+#include "system.h"
+#include "tcpm/ps8xxx_public.h"
+#include "tcpm/tcpci.h"
+#include "timer.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usbc_config.h"
+#include "usbc_ocp.h"
+#include "usbc_ppc.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+};
+
+int charger_profile_override(struct charge_state_data *curr)
+{
+	int usb_mv;
+	int port;
+
+	if (curr->state != ST_CHARGE)
+		return 0;
+
+	/* Lower the max requested voltage to 5V when battery is full. */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
+	    !(curr->batt.flags & BATT_FLAG_BAD_STATUS) &&
+	    !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
+	    (curr->batt.status & STATUS_FULLY_CHARGED))
+		usb_mv = 5000;
+	else
+		usb_mv = PD_MAX_VOLTAGE_MV;
+
+	if (pd_get_max_voltage() != usb_mv) {
+		CPRINTS("VBUS limited to %dmV", usb_mv);
+		for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++)
+			pd_set_external_voltage_limit(port, usb_mv);
+	}
+
+	return 0;
+}
+
+enum ec_status charger_profile_override_get_param(uint32_t param,
+						  uint32_t *value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+enum ec_status charger_profile_override_set_param(uint32_t param,
+						  uint32_t value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+/* GPIO Interrupt Handlers */
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	int port = -1;
+
+	switch (signal) {
+	case GPIO_USB_C0_PD_INT_ODL:
+		port = 0;
+		break;
+	case GPIO_USB_C1_PD_INT_ODL:
+		port = 1;
+		break;
+	default:
+		return;
+	}
+
+	schedule_deferred_pd_interrupt(port);
+}
+
+void usb0_evt(enum gpio_signal signal)
+{
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+
+void usb1_evt(enum gpio_signal signal)
+{
+	usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+}
+
+static void usba_oc_deferred(void)
+{
+	/* Use next number after all USB-C ports to indicate the USB-A port */
+	board_overcurrent_event(CONFIG_USB_PD_PORT_MAX_COUNT,
+				!gpio_get_level(GPIO_USB_A0_OC_ODL));
+}
+DECLARE_DEFERRED(usba_oc_deferred);
+
+void usba_oc_interrupt(enum gpio_signal signal)
+{
+	hook_call_deferred(&usba_oc_deferred_data, 0);
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_SWCTL_INT_ODL:
+		sn5s330_interrupt(0);
+		break;
+	case GPIO_USB_C1_SWCTL_INT_ODL:
+		sn5s330_interrupt(1);
+		break;
+	default:
+		break;
+	}
+}
+
+/* Power Path Controller */
+struct ppc_config_t ppc_chips[] = {
+	{ .i2c_port = I2C_PORT_TCPC0,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
+	{ .i2c_port = I2C_PORT_TCPC1,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
+};
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/* TCPC mux configuration */
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TCPC0,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+	},
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TCPC1,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+	},
+};
+
+/*
+ * Port-0/1 USB mux driver.
+ *
+ * The USB mux is handled by TCPC chip and the HPD update is through a GPIO
+ * to AP. But the TCPC chip is also needed to know the HPD status; otherwise,
+ * the mux misbehaves.
+ */
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
+	},
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
+	}
+};
+
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_USB_A_5V,
+};
+
+/* BC1.2 */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	{
+		.i2c_port = I2C_PORT_POWER,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+	{
+		.i2c_port = I2C_PORT_EEPROM,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+};
+
+/* Initialize board USC-C things */
+static void board_init_usbc(void)
+{
+	/* Enable BC1.2 interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_L);
+	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L);
+
+	/* Enable USB-A overcurrent interrupt */
+	gpio_enable_interrupt(GPIO_USB_A0_OC_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_init_usbc, HOOK_PRIO_DEFAULT);
+
+void board_tcpc_init(void)
+{
+	/* Only reset TCPC if not sysjump */
+	if (!system_jumped_late()) {
+		/* TODO(crosbug.com/p/61098): How long do we need to wait? */
+		board_reset_pd_mcu();
+	}
+
+	/* Enable PPC interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_SWCTL_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_SWCTL_INT_ODL);
+
+	/* Enable TCPC interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL);
+
+	/*
+	 * Initialize HPD to low; after sysjump SOC needs to see
+	 * HPD pulse to enable video path
+	 */
+	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
+		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
+
+void board_reset_pd_mcu(void)
+{
+	cprints(CC_USB, "Resetting TCPCs...");
+	cflush();
+
+	gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
+	gpio_set_level(GPIO_USB_C1_PD_RST_L, 0);
+	msleep(PS8XXX_RESET_DELAY_MS);
+	gpio_set_level(GPIO_USB_C0_PD_RST_L, 1);
+	gpio_set_level(GPIO_USB_C1_PD_RST_L, 1);
+	msleep(PS8805_FW_INIT_DELAY_MS);
+}
+
+void board_set_tcpc_power_mode(int port, int mode)
+{
+	/* Ignore the "mode" to turn the chip on.  We can only do a reset. */
+	if (mode)
+		return;
+
+	board_reset_pd_mcu();
+}
+
+int board_vbus_sink_enable(int port, int enable)
+{
+	/* Both ports are controlled by PPC SN5S330 */
+	return ppc_vbus_sink_enable(port, enable);
+}
+
+int board_is_sourcing_vbus(int port)
+{
+	/* Both ports are controlled by PPC SN5S330 */
+	return ppc_is_sourcing_vbus(port);
+}
+
+void board_overcurrent_event(int port, int is_overcurrented)
+{
+	/* TODO(b/120231371): Notify AP */
+	CPRINTS("p%d: overcurrent!", port);
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int i;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTS("Disabling all charging port");
+
+		/* Disable all ports. */
+		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (board_vbus_sink_enable(i, 0))
+				CPRINTS("Disabling p%d sink path failed.", i);
+		}
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (board_is_sourcing_vbus(port)) {
+		CPRINTS("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTS("New charge port: p%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		if (i == port)
+			continue;
+
+		if (board_vbus_sink_enable(i, 0))
+			CPRINTS("p%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (board_vbus_sink_enable(port, 1)) {
+		CPRINTS("p%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
+{
+	/*
+	 * Ignore lower charge ceiling on PD transition if our battery is
+	 * critical, as we may brownout.
+	 */
+	if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 &&
+	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
+		CPRINTS("Using max ilim %d", max_ma);
+		charge_ma = max_ma;
+	}
+
+	charge_set_input_current_limit(charge_ma, charge_mv);
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
+		if (gpio_get_level(GPIO_USB_C0_PD_RST_L))
+			status |= PD_STATUS_TCPC_ALERT_0;
+	if (!gpio_get_level(GPIO_USB_C1_PD_INT_ODL))
+		if (gpio_get_level(GPIO_USB_C1_PD_RST_L))
+			status |= PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
diff --git a/board/trogdor/usbc_config.h b/board/trogdor/usbc_config.h
new file mode 100644
index 0000000000..c9b676fc61
--- /dev/null
+++ b/board/trogdor/usbc_config.h
@@ -0,0 +1,19 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Trogdor board-specific USB-C configuration */
+
+#ifndef __CROS_EC_USBC_CONFIG_H
+#define __CROS_EC_USBC_CONFIG_H
+
+#include "gpio.h"
+
+void tcpc_alert_event(enum gpio_signal signal);
+void usb0_evt(enum gpio_signal signal);
+void usb1_evt(enum gpio_signal signal);
+void usba_oc_interrupt(enum gpio_signal signal);
+void ppc_interrupt(enum gpio_signal signal);
+
+#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/trogdor/vif_override.xml b/board/trogdor/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/trogdor/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/trondo/battery.c b/board/trondo/battery.c
deleted file mode 100644
index 9b356a8efd..0000000000
--- a/board/trondo/battery.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Volteer battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* LGC\011 L17L3PB0 Battery Information */
-	/*
-	 * Battery info provided by ODM on b/143477210, comment #11
-	 */
-	[BATTERY_LGC011] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= TARGET_WITH_MARGIN(13200, 5),
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 75,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_LGC011;
diff --git a/board/trondo/board.c b/board/trondo/board.c
deleted file mode 100644
index 58c74283e4..0000000000
--- a/board/trondo/board.c
+++ /dev/null
@@ -1,453 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer board-specific configuration */
-#include "bb_retimer.h"
-#include "button.h"
-#include "common.h"
-#include "accelgyro.h"
-#include "cbi_ec_fw_config.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi260.h"
-#include "driver/als_tcs3400.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/ppc/syv682x.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/tusb422.h"
-#include "driver/retimer/bb_retimer.h"
-#include "driver/sync.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "tablet_mode.h"
-#include "throttle_ap.h"
-#include "uart.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tbt.h"
-#include "usb_pd_tcpm.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-/* Keyboard scan setting */
-struct keyboard_scan_config keyscan_config = {
-	/* Increase from 50 us, because KSO_02 passes through the H1. */
-	.output_settle_us = 80,
-	/* Other values should be the same as the default configuration. */
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-/******************************************************************************/
-/*
- * FW_CONFIG defaults for Trondo if the CBI data is not initialized.
- */
-union volteer_cbi_fw_config fw_config_defaults = {
-	.usb_db = DB_USB3_PASSIVE,
-};
-
-static void board_init(void)
-{
-	/* Illuminate motherboard and daughter board LEDs equally to start. */
-	pwm_enable(PWM_CH_LED4_SIDESEL, 1);
-	pwm_set_duty(PWM_CH_LED4_SIDESEL, 50);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-__override enum tbt_compat_cable_speed board_get_max_tbt_speed(int port)
-{
-	/* Routing length exceeds 205mm prior to connection to re-timer */
-	if (port == USBC_PORT_C1)
-		return TBT_SS_U32_GEN1_GEN2;
-
-	/*
-	 * Thunderbolt-compatible mode not supported
-	 *
-	 * TODO (b/147726366): All the USB-C ports need to support same speed.
-	 * Need to fix once USB-C feature set is known for Volteer.
-	 */
-	return TBT_SS_RES_0;
-}
-
-__override bool board_is_tbt_usb4_port(int port)
-{
-	/*
-	 * On Proto-1 only Port 1 supports TBT & USB4
-	 *
-	 * TODO (b/147732807): All the USB-C ports need to support same
-	 * features. Need to fix once USB-C feature set is known for Volteer.
-	 */
-	return port == USBC_PORT_C1;
-}
-
-/******************************************************************************/
-/* Physical fans. These are logically separate from pwm_channels. */
-
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = GPIO_EN_PP5000_FAN,
-};
-
-/*
- * Fan specs from datasheet:
- * Max speed 5900 rpm (+/- 7%), minimum duty cycle 30%.
- * Minimum speed not specified by RPM. Set minimum RPM to max speed (with
- * margin) x 30%.
- *    5900 x 1.07 x 0.30 = 1894, round up to 1900
- */
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 1900,
-	.rpm_start = 1900,
-	.rpm_max = 5900,
-};
-
-const struct fan_t fans[FAN_CH_COUNT] = {
-	[FAN_CH_0] = {
-		.conf = &fan_conf_0,
-		.rpm = &fan_rpm_0,
-	},
-};
-
-/******************************************************************************/
-/* EC thermal management configuration */
-
-/*
- * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
- * 130 C.  However, sensor is located next to DDR, so we need to use the lower
- * DDR temperature limit (85 C)
- */
-const static struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(35),
-	.temp_fan_max = C_TO_K(50),
-};
-
-/*
- * Inductor limits - used for both charger and PP3300 regulator
- *
- * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
- *
- * Charger max recommended temperature 100C, max absolute temperature 125C
- * PP3300 regulator: operating range -40 C to 145 C
- *
- * Inductors: limit of 125c
- * PCB: limit is 80c
- */
-const static struct ec_thermal_config thermal_inductor = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(55),
-};
-
-
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_CHARGER]			= thermal_inductor,
-	[TEMP_SENSOR_2_PP3300_REGULATOR]	= thermal_inductor,
-	[TEMP_SENSOR_3_DDR_SOC]			= thermal_cpu,
-	[TEMP_SENSOR_4_FAN]			= thermal_cpu,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-/******************************************************************************/
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {
-		.module = NPCX_MFT_MODULE_1,
-		.clk_src = TCKC_LFCLK,
-		.pwm_id = PWM_CH_FAN,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-/******************************************************************************/
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C0_SENSOR_SCL,
-		.sda = GPIO_EC_I2C0_SENSOR_SDA,
-	},
-	{
-		.name = "usb_c0",
-		.port = I2C_PORT_USB_C0,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C1_USB_C0_SCL,
-		.sda = GPIO_EC_I2C1_USB_C0_SDA,
-	},
-	{
-		.name = "usb_c1",
-		.port = I2C_PORT_USB_C1,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C2_USB_C1_SCL,
-		.sda = GPIO_EC_I2C2_USB_C1_SDA,
-	},
-	{
-		.name = "usb_1_mix",
-		.port = I2C_PORT_USB_1_MIX,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C3_USB_1_MIX_SCL,
-		.sda = GPIO_EC_I2C3_USB_1_MIX_SDA,
-	},
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C5_POWER_SCL,
-		.sda = GPIO_EC_I2C5_POWER_SDA,
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C7_EEPROM_SCL,
-		.sda = GPIO_EC_I2C7_EEPROM_SDA,
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/******************************************************************************/
-/* PWM configuration */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED1_BLUE] = {
-		.channel = 2,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 2400,
-	},
-	[PWM_CH_LED2_GREEN] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 2400,
-	},
-	[PWM_CH_LED3_RED] = {
-		.channel = 1,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 2400,
-	},
-	[PWM_CH_LED4_SIDESEL] = {
-		.channel = 7,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		/* Run at a higher frequency than the color PWM signals to avoid
-		 * timing-based color shifts.
-		 */
-		.freq = 4800,
-	},
-	[PWM_CH_FAN] = {
-		.channel = 5,
-		.flags = PWM_CONFIG_OPEN_DRAIN,
-		.freq = 25000
-	},
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = 0,
-		/*
-		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
-		 * flicker. Higher frequencies consume similar average power to
-		 * lower PWM frequencies, but higher frequencies record a much
-		 * lower maximum power.
-		 */
-		.freq = 2400,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-void board_reset_pd_mcu(void)
-{
-	/* TODO(b/159025023): Trondo: check USB PD reset operation */
-}
-
-__override void board_cbi_init(void)
-{
-	/* TODO(b/159025023): Trondo: check FW_CONFIG fields for USB DB type */
-}
-
-/******************************************************************************/
-/* USBC PPC configuration */
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/******************************************************************************/
-/* PPC support routines */
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		sn5s330_interrupt(USBC_PORT_C0);
-		break;
-	case GPIO_USB_C1_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C1);
-	default:
-		break;
-	}
-}
-
-/******************************************************************************/
-/* BC1.2 charger detect configuration */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC TCPC configuration */
-struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
-		},
-		.drv = &tusb422_tcpm_drv,
-		.usb23 = USBC_PORT_0_USB2_NUM | (USBC_PORT_0_USB3_NUM << 4),
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C1,
-			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
-		},
-		.drv = &tusb422_tcpm_drv,
-		.usb23 = USBC_PORT_1_USB2_NUM | (USBC_PORT_1_USB3_NUM << 4),
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC mux configuration - Tiger Lake includes internal mux */
-struct usb_mux usbc1_usb4_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &bb_usb_retimer,
-	.i2c_port = I2C_PORT_USB_1_MIX,
-	.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
-};
-struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc1_usb4_db_retimer,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-struct bb_usb_control bb_controls[] = {
-	[USBC_PORT_C0] = {
-		/* USB-C port 0 doesn't have a retimer */
-	},
-	[USBC_PORT_C1] = {
-		.usb_ls_en_gpio = GPIO_USB_C1_LS_EN,
-		.retimer_rst_gpio = GPIO_USB_C1_RT_RST_ODL,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(bb_controls) == USBC_PORT_COUNT);
-
-static void board_tcpc_init(void)
-{
-	/* Don't reset TCPCs after initial reset */
-	if (!system_jumped_late())
-		board_reset_pd_mcu();
-
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
-
-	/* Enable BC1.2 interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
-
-/******************************************************************************/
-/* TCPC support routines */
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	/*
-	 * Check which port has the ALERT line set
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_0;
-	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (port == USBC_PORT_C0)
-		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
-	else
-		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
-}
-
diff --git a/board/trondo/board.h b/board/trondo/board.h
deleted file mode 100644
index c81bc1a5db..0000000000
--- a/board/trondo/board.h
+++ /dev/null
@@ -1,189 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Baseboard features */
-#include "baseboard.h"
-
-/* Optional features */
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
-
-#define CONFIG_POWER_BUTTON
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* LED defines */
-#define CONFIG_LED_PWM
-/* Although there are 2 LEDs, they are both controlled by the same lines. */
-#define CONFIG_LED_PWM_COUNT 1
-
-/* Keyboard features */
-
-/* Sensors */
-/* BMA253 accelerometer in base */
-#define CONFIG_ACCEL_BMA255
-
-/* BMI260 accel/gyro in base */
-#define CONFIG_ACCELGYRO_BMI260
-#define CONFIG_ACCELGYRO_BMI260_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-/* TCS3400 ALS */
-#define CONFIG_ALS
-#define ALS_COUNT		1
-#define CONFIG_ALS_TCS3400
-#define CONFIG_ALS_TCS3400_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS)
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
-	(BIT(LID_ACCEL) | BIT(CLEAR_ALS))
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
-
-/*
- * USB-C port's USB2 & USB3 mapping from schematics
- * USB2 numbering on PCH - 1 to n
- * USB3 numbering on AP - 0 to n (PMC's USB3 numbering for MUX
- * configuration is - 1 to n hence add +1)
- */
-#define USBC_PORT_0_USB2_NUM	9
-#define USBC_PORT_0_USB3_NUM	1
-#define USBC_PORT_1_USB2_NUM	4
-#define USBC_PORT_1_USB3_NUM	2
-
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
-
-/*
- * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
- * cables only support up to 60W.
- */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
-
-/* Enabling Thunderbolt-compatible mode */
-#define CONFIG_USB_PD_TBT_COMPAT_MODE
-
-/* Enabling USB4 mode */
-#define CONFIG_USB_PD_USB4
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x40
-
-/* USB Type A Features */
-
-/* USBC PPC*/
-#define CONFIG_USBC_PPC_SN5S330		/* USBC port C0 */
-#define CONFIG_USBC_PPC_SYV682X		/* USBC port C1 */
-
-/* BC 1.2 */
-
-/* Volume Button feature */
-/*
- * TODO (b/149858568): remove CONFIG_BUTTONS_RUNTIME_CONFIG once board ID=0
- * support is stripped.
- */
-#define CONFIG_BUTTONS_RUNTIME_CONFIG
-
-/* Fan features */
-
-/* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PG_EC_DSW_PWROK		GPIO_DSW_PWROK
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD		GPIO_PG_EC_RSMRST_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
-#define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE_L
-
-/* I2C Bus Configuration */
-#define CONFIG_I2C
-#define I2C_PORT_ACCEL		I2C_PORT_SENSOR
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_1_MIX	NPCX_I2C_PORT3_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-#define CONFIG_I2C_MASTER
-
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum battery_type {
-	BATTERY_LGC011,
-	BATTERY_TYPE_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_LED1_BLUE = 0,
-	PWM_CH_LED2_GREEN,
-	PWM_CH_LED3_RED,
-	PWM_CH_LED4_SIDESEL,
-	PWM_CH_FAN,
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	CLEAR_ALS,
-	RGB_ALS,
-	SENSOR_COUNT,
-};
-
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
-
-void board_reset_pd_mcu(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/trondo/build.mk b/board/trondo/build.mk
deleted file mode 100644
index b78172d3cf..0000000000
--- a/board/trondo/build.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
-BASEBOARD:=volteer
-
-board-y=board.o
-board-y+=battery.o
-board-y+=led.o
-board-y+=sensors.o
diff --git a/board/trondo/ec.tasklist b/board/trondo/ec.tasklist
deleted file mode 100644
index 292de51cdb..0000000000
--- a/board/trondo/ec.tasklist
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/trondo/gpio.inc b/board/trondo/gpio.inc
deleted file mode 100644
index 4ea6194140..0000000000
--- a/board/trondo/gpio.inc
+++ /dev/null
@@ -1,171 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(EC_LID_OPEN,          PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(EC_WP_L,              PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(H1_EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
-GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_RSMRST_ODL,     PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(DSW_PWROK,            PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4),  GPIO_INT_BOTH, power_signal_interrupt)
-
-/* Sensor Interrupts */
-GPIO_INT(EC_IMU_INT_L,         PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, bmi260_interrupt)
-GPIO_INT(EC_ALS_RGB_INT_L,     PIN(D, 4), GPIO_INT_FALLING, tcs3400_interrupt)
-GPIO_INT(TABLET_MODE_L,        PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(E, 0), GPIO_INT_BOTH, tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(A, 2), GPIO_INT_BOTH, tcpc_alert_event)
-
-GPIO_INT(USB_C0_PPC_INT_ODL,	PIN(6, 2), GPIO_INT_BOTH, ppc_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(F, 5), GPIO_INT_BOTH, ppc_interrupt)
-
-GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(E, 4), GPIO_INT_BOTH, bc12_interrupt)
-GPIO_INT(USB_C1_MIX_INT_ODL,	PIN(0, 3), GPIO_INT_BOTH, bc12_interrupt)
-
-/* HDMI interrupts */
-
-/* Volume button interrupts */
-GPIO_INT(EC_VOLDN_BTN_ODL,		PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-/*
- * EC_VOLUP_BTN_ODL moved from GPIO75 to GPIO97 on boards with board ID >=1.
- * GPIO97/EN_PP1050_BYPASS is DNS on board ID 0, and GPIO75 will be used once
- * EFS support is added.
- * TODO (b/149858568): remove board ID=0 support.
- */
-GPIO_INT(EC_VOLUP_BTN_ODL_BOARDID_0,	PIN(7, 5), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL,		PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-
-/* Power Sequencing Signals */
-GPIO(EN_PP3300_A,              PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_PPVAR_VCCIN,           PIN(4, 3), GPIO_OUT_LOW) /* Enables VCCIN IMPV9 */
-/* The EC does not buffer this signal on Volteer. */
-UNIMPLEMENTED(PCH_DSW_PWROK)
-
-/* Other wake sources */
-/*
- * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an
- * interrupt handler because it is automatically handled by the PSL.
- *
- * We need to lock the setting so this gpio can't be reconfigured to overdrive
- * the real reset signal. (This is the PSL input pin not the real reset pin).
- */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH |
-					   GPIO_HIB_WAKE_HIGH |
-					   GPIO_LOCKED)
-
-/* AP/PCH Signals */
-GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
-GPIO(EC_PCH_RSMRST_ODL,        PIN(A, 6), GPIO_ODR_LOW) /* TODO - b/140950085 - implement TGL sequencing requirement */
-GPIO(EC_PCH_PWR_BTN_ODL,       PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
-GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
-GPIO_INT(EC_PROCHOT_IN_L,      PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
-GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
-
-GPIO(EC_PCH_INT_ODL,           PIN(B, 0), GPIO_ODR_HIGH)
-
-/* USB and USBC Signals */
-
-/*
- * USB_C1 moved from GPIO32 to GPIO83 on boards with board ID >=1.
- * GPIO83/EN_PP1800_A is DNS on board ID 0 and GPIO32 is N/C on board ID >=1
- * so it's safe to define GPIOs compatible with both designs.
- * TODO (b/149858568): remove board ID=0 support.
- */
-GPIO(USB_C1_RT_RST_ODL_BOARDID_0,	PIN(3, 2), GPIO_ODR_LOW) /* USB_C1 Reset on boards without board ID */
-GPIO(USB_C1_RT_RST_ODL,			PIN(8, 3), GPIO_ODR_LOW) /* USB_C1 Reset on boards board ID >=1 */
-GPIO(USB_C0_OC_ODL,			PIN(B, 1), GPIO_ODR_HIGH)
-GPIO(USB_C1_OC_ODL,			PIN(5, 0), GPIO_ODR_HIGH)
-
-/* Don't have a load switch for retimer */
-UNIMPLEMENTED(USB_C1_LS_EN)
-
-/* Misc Signals */
-
-/*
- * eDP backlight - both PCH and EC have enable pins that must be high
- * for the backlight to turn on. Default state is high, and can be turned
- * off during sleep states.
- */
-GPIO(EC_EDP_BL_EN,             PIN(D, 3), GPIO_OUT_HIGH)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(EC_I2C0_SENSOR_SCL,       PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C0_SENSOR_SDA,       PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C1_USB_C0_SCL,       PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C1_USB_C0_SDA,       PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SCL,       PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SDA,       PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C3_USB_1_MIX_SCL,    PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C3_USB_1_MIX_SDA,    PIN(D, 0), GPIO_INPUT)
-GPIO(EC_I2C5_POWER_SCL,        PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C5_POWER_SDA,        PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_SCL,       PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_SDA,       PIN(B, 2), GPIO_INPUT)
-
-/* Battery signals */
-GPIO(EC_BATT_PRES_ODL, 		PIN(E, 1), GPIO_INPUT)
-
-/* Physical HPD pins are not needed on EC as these are configured by PMC */
-GPIO(USB_C0_DP_HPD,		PIN(F, 3), GPIO_INPUT)
-GPIO(USB_C1_DP_HPD,		PIN(7, 0), GPIO_INPUT)
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, BIT(5) | BIT(4)), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V)) /* I2C0 */
-ALTERNATE(PIN_MASK(9, BIT(0) | BIT(2) | BIT(1)), 0, MODULE_I2C, 0)                   /* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)                                     /* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, BIT(1) | BIT(0)), 0, MODULE_I2C, 0)                            /* I2C3 */
-ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)                            /* I2C5 */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)                            /* I2C7 */
-
-/* This selects between an LED module on the motherboard and one on the daughter
- * board, to be controlled by LED_{1,2,3}_L. PWM allows driving both modules at
- * the same time. */
-ALTERNATE(PIN_MASK(6, BIT(0)), 0, MODULE_PWM, 0)                                     /* LED_SIDESEL_4_L */
-ALTERNATE(PIN_MASK(C, BIT(2) | BIT(3) | BIT(4)), 0, MODULE_PWM, 0)                   /* LED_{3,2,1}_L */
-
-/* Fan signals */
-GPIO(EN_PP5000_FAN,            PIN(6, 1), GPIO_OUT_LOW)
-ALTERNATE(PIN_MASK(B, BIT(7)), 0, MODULE_PWM, 0)	/* FAN_PWM */
-ALTERNATE(PIN_MASK(4, BIT(0)), 0, MODULE_PWM, 0)	/* FAN_SPEED_TACH */
-
-/* Keyboard pins */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_00-01 */
-GPIO(EC_KSO_02_INV, PIN(1, 7),                        GPIO_OUT_LOW)  /* KSO_02 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_14 */
-ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)                     /* EC_KB_BL_PWM */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, BIT(5) | BIT(4)), 0, MODULE_UART, 0)                           /* UART from EC to Servo */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)                    /* GPIOD2 = EC_LID_OPEN */
-ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)  /* GPIO00 = ACOK_OD,
-                                                                       GPIO01 = H1_EC_PWR_BTN_ODL
-                                                                       GPIO02 = EC_RST_ODL */
-
diff --git a/board/trondo/led.c b/board/trondo/led.c
deleted file mode 100644
index 735df935d2..0000000000
--- a/board/trondo/led.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Volteer
- */
-
-#include "charge_manager.h"
-#include "common.h"
-#include "ec_commands.h"
-#include "hooks.h"
-#include "led_common.h"
-#include "led_pwm.h"
-#include "pwm.h"
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-struct pwm_led led_color_map[] = {
-				/* Red, Green, Blue */
-	[EC_LED_COLOR_RED] =    {  100,   0,     0 },
-	[EC_LED_COLOR_GREEN] =  {    0, 100,     0 },
-	[EC_LED_COLOR_BLUE] =   {    0,   0,   100 },
-	/* The green LED seems to be brighter than the others, so turn down
-	 * green from its natural level for these secondary colors.
-	 */
-	[EC_LED_COLOR_YELLOW] = {  100,  70,     0 },
-	[EC_LED_COLOR_WHITE] =  {  100,  70,   100 },
-	[EC_LED_COLOR_AMBER] =  {  100,  20,     0 },
-};
-
-struct pwm_led pwm_leds[] = {
-	/* 2 RGB diffusers controlled by 1 set of 3 channels. */
-	[PWM_LED0] = {
-		.ch0 = PWM_CH_LED3_RED,
-		.ch1 = PWM_CH_LED2_GREEN,
-		.ch2 = PWM_CH_LED1_BLUE,
-		.enable = &pwm_enable,
-		.set_duty = &pwm_set_duty,
-	},
-};
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_RED] = 255;
-	brightness_range[EC_LED_COLOR_GREEN] = 255;
-	brightness_range[EC_LED_COLOR_BLUE] = 255;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	enum pwm_led_id pwm_id;
-
-	/* Convert ec_led_id to pwm_led_id. */
-	if (led_id == EC_LED_ID_POWER_LED)
-		pwm_id = PWM_LED0;
-	else
-		return EC_ERROR_UNKNOWN;
-
-	if (brightness[EC_LED_COLOR_RED])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_RED);
-	else if (brightness[EC_LED_COLOR_GREEN])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_GREEN);
-	else if (brightness[EC_LED_COLOR_BLUE])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_BLUE);
-	else if (brightness[EC_LED_COLOR_YELLOW])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_YELLOW);
-	else if (brightness[EC_LED_COLOR_WHITE])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_WHITE);
-	else if (brightness[EC_LED_COLOR_AMBER])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_AMBER);
-	else
-		/* Otherwise, the "color" is "off". */
-		set_pwm_led_color(pwm_id, -1);
-
-	return EC_SUCCESS;
-}
-
-/* Illuminates the LED on the side of the active charging port. If not charging,
- * illuminates both LEDs.
- */
-static void led_set_charge_port_tick(void)
-{
-	int port;
-	int side_select_duty;
-
-	port = charge_manager_get_active_charge_port();
-	switch (port) {
-	case 0:
-		side_select_duty = 100;
-		break;
-	case 1:
-		side_select_duty = 0;
-		break;
-	default:
-		side_select_duty = 50;
-	}
-
-	pwm_set_duty(PWM_CH_LED4_SIDESEL, side_select_duty);
-}
-DECLARE_HOOK(HOOK_TICK, led_set_charge_port_tick, HOOK_PRIO_DEFAULT);
diff --git a/board/trondo/sensors.c b/board/trondo/sensors.c
deleted file mode 100644
index e9169abaae..0000000000
--- a/board/trondo/sensors.c
+++ /dev/null
@@ -1,229 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer family-specific sensor configuration */
-#include "common.h"
-#include "accelgyro.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_bmi260.h"
-#include "driver/als_tcs3400.h"
-#include "driver/sync.h"
-#include "keyboard_scan.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "task.h"
-#include "util.h"
-
-/******************************************************************************/
-/* Sensors */
-static struct mutex g_lid_accel_mutex;
-static struct mutex g_base_mutex;
-
-/* BMA253 private data */
-static struct accelgyro_saved_data_t g_bma253_data;
-
-/* BMI260 private data */
-static struct bmi_drv_data_t g_bmi260_data;
-
-/* TCS3400 private data */
-static struct als_drv_data_t g_tcs3400_data = {
-	.als_cal.scale = 1,
-	.als_cal.uscale = 0,
-	.als_cal.offset = 0,
-	.als_cal.channel_scale = {
-		.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kc from VPD */
-		.cover_scale = ALS_CHANNEL_SCALE(1.0),     /* CT */
-	},
-};
-
-/*
- * TODO: b/146166425 need to calibrate ALS/RGB sensor. At default settings,
- * shining phone flashlight on sensor pegs all readings at 0xFFFF.
- */
-static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
-	.calibration.rgb_cal[X] = {
-		.offset = 0,
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kr */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		}
-	},
-	.calibration.rgb_cal[Y] = {
-		.offset = 0,
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kg */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		},
-	},
-	.calibration.rgb_cal[Z] = {
-		.offset = 0,
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kb */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		}
-	},
-	.calibration.irt = INT_TO_FP(1),
-	.saturation.again = TCS_DEFAULT_AGAIN,
-	.saturation.atime = TCS_DEFAULT_ATIME,
-};
-
-/* Rotation matrix for the lid accelerometer */
-/* TODO: b/146144170 - the accelerometer is on the motherboard for proto1
- * for testing. Once the sensor moves to the lid, the rotation matrix needs
- * to be updated for correct behavior.
- */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_lid_accel_mutex,
-		.drv_data = &g_bma253_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.default_range = 2, /* g, to support tablet mode */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI260,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi260_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi260_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.default_range = 4, /* g */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI260,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi260_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi260_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-	[CLEAR_ALS] = {
-		.name = "Clear Light",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_TCS3400,
-		.type = MOTIONSENSE_TYPE_LIGHT,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &tcs3400_drv,
-		.drv_data = &g_tcs3400_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = TCS3400_I2C_ADDR_FLAGS,
-		.rot_standard_ref = NULL,
-		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
-		.min_frequency = TCS3400_LIGHT_MIN_FREQ,
-		.max_frequency = TCS3400_LIGHT_MAX_FREQ,
-		.config = {
-			/* Run ALS sensor in S0 */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 1000,
-			},
-		},
-	},
-
-	[RGB_ALS] = {
-		/*
-		 * RGB channels read by CLEAR_ALS and so the i2c port and
-		 * address do not need to be defined for RGB_ALS.
-		 */
-		.name = "RGB Light",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_TCS3400,
-		.type = MOTIONSENSE_TYPE_LIGHT_RGB,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &tcs3400_rgb_drv,
-		.drv_data = &g_tcs3400_rgb_data,
-		.rot_standard_ref = NULL,
-		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
-	},
-};
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/* ALS instances when LPC mapping is needed. Each entry directs to a sensor. */
-const struct motion_sensor_t *motion_als_sensors[] = {
-	&motion_sensors[CLEAR_ALS],
-};
-BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
-
-static void baseboard_sensors_init(void)
-{
-	/* Note - BMA253 interrupt unused by EC */
-
-	/* Enable interrupt for the TCS3400 color light sensor */
-	gpio_enable_interrupt(GPIO_EC_ALS_RGB_INT_L);
-	/* Enable interrupt for the BMI260 accel/gyro sensor */
-	gpio_enable_interrupt(GPIO_EC_IMU_INT_L);
-}
-DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_DEFAULT);
diff --git a/board/twinkie/board.c b/board/twinkie/board.c
index b50307397a..ffc3746432 100644
--- a/board/twinkie/board.c
+++ b/board/twinkie/board.c
@@ -1,11 +1,10 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 /* Twinkie dongle configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "common.h"
 #include "console.h"
 #include "ec_version.h"
@@ -28,6 +27,7 @@ void vbus_event(enum gpio_signal signal)
 	ccprintf("INA!\n");
 }
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /* Initialize board. */
@@ -37,7 +37,7 @@ void board_config_pre_init(void)
 	STM32_RCC_APB2ENR |= BIT(0);
 	/* Remap USART DMA to match the USART driver and TIM2 DMA */
 	STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10) /* Remap USART1 RX/TX DMA */
-			   |  BIT(29);/* Remap TIM2 DMA */
+			      | BIT(29); /* Remap TIM2 DMA */
 	/* 40 MHz pin speed on UART PA9/PA10 */
 	STM32_GPIO_OSPEEDR(GPIO_A) |= 0x003C0000;
 	/* 40 MHz pin speed on TX clock out PB9 */
@@ -60,20 +60,24 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* USB PD CC lines sensing. Converted to mV (3300mV/4096). */
-	[ADC_CH_CC1_PD] = {"CC1_PD", 3300, 4096, 0, STM32_AIN(1)},
-	[ADC_CH_CC2_PD] = {"CC2_PD", 3300, 4096, 0, STM32_AIN(3)},
+	[ADC_CH_CC1_PD] = { "CC1_PD", 3300, 4096, 0, STM32_AIN(1) },
+	[ADC_CH_CC2_PD] = { "CC2_PD", 3300, 4096, 0, STM32_AIN(3) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{"master", I2C_PORT_MASTER, 100, GPIO_I2C_SCL, GPIO_I2C_SDA},
+	{ .name = "master",
+	  .port = I2C_PORT_MASTER,
+	  .kbps = 100,
+	  .scl = GPIO_I2C_SCL,
+	  .sda = GPIO_I2C_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
-const void * const usb_strings[] = {
+const void *const usb_strings[] = {
 	[USB_STR_DESC] = usb_string_desc,
-	[USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."),
+	[USB_STR_VENDOR] = USB_STRING_DESC("Google LLC"),
 	[USB_STR_PRODUCT] = USB_STRING_DESC("Twinkie"),
 	[USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32),
 	[USB_STR_SNIFFER] = USB_STRING_DESC("USB-PD Sniffer"),
diff --git a/board/twinkie/board.h b/board/twinkie/board.h
index b5756fda34..808053d146 100644
--- a/board/twinkie/board.h
+++ b/board/twinkie/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -42,7 +42,7 @@
 #define CONFIG_ADC
 #define CONFIG_BOARD_PRE_INIT
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_CONTROLLER
 #define CONFIG_INA231
 #undef CONFIG_WATCHDOG_HELP
 #undef CONFIG_LID_SWITCH
@@ -54,7 +54,7 @@
 /* USB configuration */
 #define CONFIG_USB_PID 0x500A
 /* By default, enable all console messages excepted USB */
-#define CC_DEFAULT     (CC_ALL & ~CC_MASK(CC_USB))
+#define CC_DEFAULT (CC_ALL & ~CC_MASK(CC_USB))
 
 /*
  * Allow dangerous commands all the time, since we don't have a write protect
@@ -79,9 +79,8 @@ void trace_packets(void);
 void set_trace_mode(int mode);
 
 /* Timer selection */
-#define TIM_CLOCK_MSB  3
-#define TIM_CLOCK_LSB 15
-#define TIM_ADC       16
+#define TIM_CLOCK32 2
+#define TIM_ADC 16
 
 #include "gpio_signal.h"
 
@@ -106,28 +105,28 @@ enum usb_strings {
 };
 
 /* Standard-current Rp */
-#define PD_SRC_VNC           PD_SRC_DEF_VNC_MV
-#define PD_SRC_RD_THRESHOLD  PD_SRC_DEF_RD_THRESH_MV
+#define PD_SRC_VNC PD_SRC_DEF_VNC_MV
+#define PD_SRC_RD_THRESHOLD PD_SRC_DEF_RD_THRESH_MV
 
 /* delay necessary for the voltage transition on the power supply */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  50000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 50000 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 50000 /* us */
 
 /* Define typical operating power and max power */
 #define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       60000
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_VOLTAGE_MV     20000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 #endif /* !__ASSEMBLER__ */
 
 /* USB interface indexes (use define rather than enum to expand them) */
 #define USB_IFACE_CONSOLE 0
-#define USB_IFACE_VENDOR  1
+#define USB_IFACE_VENDOR 1
 
 /* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL   0
-#define USB_EP_CONSOLE   1
+#define USB_EP_CONTROL 0
+#define USB_EP_CONSOLE 1
 
 /*
  * Endpoint 2 is missing because the console used to use two bidirectional
@@ -137,13 +136,13 @@ enum usb_strings {
  */
 
 #ifdef HAS_TASK_SNIFFER
-#define USB_EP_SNIFFER   3
-#define USB_EP_COUNT     4
-#define USB_IFACE_COUNT  2
+#define USB_EP_SNIFFER 3
+#define USB_EP_COUNT 4
+#define USB_IFACE_COUNT 2
 #else
-#define USB_EP_COUNT     2
+#define USB_EP_COUNT 2
 /* No IFACE_VENDOR for the sniffer */
-#define USB_IFACE_COUNT  1
+#define USB_IFACE_COUNT 1
 #endif
 
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/twinkie/build.mk b/board/twinkie/build.mk
index 6fc2067d8f..f710000486 100644
--- a/board/twinkie/build.mk
+++ b/board/twinkie/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
+# Copyright 2014 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -10,5 +10,5 @@ CHIP:=stm32
 CHIP_FAMILY:=stm32f0
 CHIP_VARIANT:=stm32f07x
 
-board-y=board.o usb_pd_policy.o injector.o simpletrace.o
+board-y=board.o usb_pd_policy.o injector.o simpletrace.o usb_pd_pdo.o
 board-$(HAS_TASK_SNIFFER)+=sniffer.o
diff --git a/board/twinkie/ec.tasklist b/board/twinkie/ec.tasklist
index 600df47c60..0dcfd38308 100644
--- a/board/twinkie/ec.tasklist
+++ b/board/twinkie/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/twinkie/gpio.inc b/board/twinkie/gpio.inc
index 551cb73748..45b34de766 100644
--- a/board/twinkie/gpio.inc
+++ b/board/twinkie/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
+ * Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/twinkie/injector.c b/board/twinkie/injector.c
index cae1d3557f..7688b68128 100644
--- a/board/twinkie/injector.c
+++ b/board/twinkie/injector.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -48,26 +48,31 @@ static const struct res_cfg {
 		uint32_t flags;
 	} cfgs[2];
 } res_cfg[] = {
-	[INJ_RES_NONE]  = {"NONE"},
-	[INJ_RES_RA]    = {"RA", {{GPIO_CC1_RA, GPIO_ODR_LOW},
-				  {GPIO_CC2_RA, GPIO_ODR_LOW} } },
-	[INJ_RES_RD]    = {"RD", {{GPIO_CC1_RD, GPIO_ODR_LOW},
-				  {GPIO_CC2_RD, GPIO_ODR_LOW} } },
-	[INJ_RES_RPUSB] = {"RPUSB", {{GPIO_CC1_RPUSB, GPIO_OUT_HIGH},
-				     {GPIO_CC2_RPUSB, GPIO_OUT_HIGH} } },
-	[INJ_RES_RP1A5] = {"RP1A5", {{GPIO_CC1_RP1A5, GPIO_OUT_HIGH},
-				     {GPIO_CC2_RP1A5, GPIO_OUT_HIGH} } },
-	[INJ_RES_RP3A0] = {"RP3A0", {{GPIO_CC1_RP3A0, GPIO_OUT_HIGH},
-				     {GPIO_CC2_RP3A0, GPIO_OUT_HIGH} } },
+	[INJ_RES_NONE] = { "NONE" },
+	[INJ_RES_RA] = { "RA",
+			 { { GPIO_CC1_RA, GPIO_ODR_LOW },
+			   { GPIO_CC2_RA, GPIO_ODR_LOW } } },
+	[INJ_RES_RD] = { "RD",
+			 { { GPIO_CC1_RD, GPIO_ODR_LOW },
+			   { GPIO_CC2_RD, GPIO_ODR_LOW } } },
+	[INJ_RES_RPUSB] = { "RPUSB",
+			    { { GPIO_CC1_RPUSB, GPIO_OUT_HIGH },
+			      { GPIO_CC2_RPUSB, GPIO_OUT_HIGH } } },
+	[INJ_RES_RP1A5] = { "RP1A5",
+			    { { GPIO_CC1_RP1A5, GPIO_OUT_HIGH },
+			      { GPIO_CC2_RP1A5, GPIO_OUT_HIGH } } },
+	[INJ_RES_RP3A0] = { "RP3A0",
+			    { { GPIO_CC1_RP3A0, GPIO_OUT_HIGH },
+			      { GPIO_CC2_RP3A0, GPIO_OUT_HIGH } } },
 };
 
-#define CC_RA(cc)  (cc < PD_SRC_RD_THRESHOLD)
+#define CC_RA(cc) (cc < PD_SRC_RD_THRESHOLD)
 #define CC_RD(cc) ((cc > PD_SRC_RD_THRESHOLD) && (cc < PD_SRC_VNC))
 #define GET_POLARITY(cc1, cc2) (CC_RD(cc2) || CC_RA(cc1))
 
 #ifdef HAS_TASK_SNIFFER
 /* we don't have the default DMA handlers */
-void dma_event_interrupt_channel_3(void)
+static void dma_event_interrupt_channel_3(void)
 {
 	if (STM32_DMA1_REGS->isr & STM32_DMA_ISR_TCIF(STM32_DMAC_CH3)) {
 		dma_clear_isr(STM32_DMAC_CH3);
@@ -103,8 +108,8 @@ static inline void enable_tracing_ifneeded(int flag)
 		pd_rx_enable_monitoring(0);
 }
 
-static int send_message(int polarity, uint16_t header,
-			uint8_t cnt, const uint32_t *data)
+static int send_message(int polarity, uint16_t header, uint8_t cnt,
+			const uint32_t *data)
 {
 	int bit_len;
 
@@ -215,7 +220,7 @@ static void fsm_wait(uint32_t w)
 	uint32_t timeout_ms = INJ_ARG0(w);
 	uint32_t min_edges = INJ_ARG12(w);
 
-	wait_packet(inj_polarity,  min_edges, timeout_ms * 1000);
+	wait_packet(inj_polarity, min_edges, timeout_ms * 1000);
 #endif
 }
 
@@ -224,7 +229,7 @@ static void fsm_expect(uint32_t w)
 	uint32_t timeout_ms = INJ_ARG0(w);
 	uint8_t cmd = INJ_ARG2(w);
 
-	expect_packet(inj_polarity,  cmd, timeout_ms * 1000);
+	expect_packet(inj_polarity, cmd, timeout_ms * 1000);
 }
 static void fsm_get(uint32_t w)
 {
@@ -242,11 +247,11 @@ static void fsm_get(uint32_t w)
 		break;
 	case INJ_GET_VBUS:
 		*store_ptr = (ina2xx_get_voltage(0) & 0xffff) |
-			 ((ina2xx_get_current(0) & 0xffff) << 16);
+			     ((ina2xx_get_current(0) & 0xffff) << 16);
 		break;
 	case INJ_GET_VCONN:
 		*store_ptr = (ina2xx_get_voltage(1) & 0xffff) |
-			 ((ina2xx_get_current(1) & 0xffff) << 16);
+			     ((ina2xx_get_current(1) & 0xffff) << 16);
 		break;
 	case INJ_GET_POLARITY:
 		*store_ptr = inj_polarity;
@@ -336,9 +341,9 @@ static int fsm_run(int index)
 
 /* ------ Console commands ------ */
 
-static int hex8tou32(char *str, uint32_t *val)
+static int hex8tou32(const char *str, uint32_t *val)
 {
-	char *ptr = str;
+	const char *ptr = str;
 	uint32_t tmp = 0;
 
 	while (*ptr) {
@@ -358,7 +363,7 @@ static int hex8tou32(char *str, uint32_t *val)
 	return EC_SUCCESS;
 }
 
-static int cmd_fsm(int argc, char **argv)
+static int cmd_fsm(int argc, const char **argv)
 {
 	int index;
 	char *e;
@@ -375,8 +380,7 @@ static int cmd_fsm(int argc, char **argv)
 	return EC_SUCCESS;
 }
 
-
-static int cmd_send(int argc, char **argv)
+static int cmd_send(int argc, const char **argv)
 {
 	int pol, cnt, i;
 	uint16_t header;
@@ -396,7 +400,7 @@ static int cmd_send(int argc, char **argv)
 		return EC_ERROR_PARAM3;
 
 	for (i = 0; i < cnt; i++)
-		if (hex8tou32(argv[i+2], data + i))
+		if (hex8tou32(argv[i + 2], data + i))
 			return EC_ERROR_INVAL;
 
 	bit_len = send_message(pol, header, cnt, data);
@@ -405,15 +409,15 @@ static int cmd_send(int argc, char **argv)
 	return EC_SUCCESS;
 }
 
-static int cmd_cc_level(int argc, char **argv)
+static int cmd_cc_level(int argc, const char **argv)
 {
-	ccprintf("CC1 = %d mV ; CC2 = %d mV\n",
-		pd_adc_read(0, 0), pd_adc_read(0, 1));
+	ccprintf("CC1 = %d mV ; CC2 = %d mV\n", pd_adc_read(0, 0),
+		 pd_adc_read(0, 1));
 
 	return EC_SUCCESS;
 }
 
-static int cmd_resistor(int argc, char **argv)
+static int cmd_resistor(int argc, const char **argv)
 {
 	int p, r;
 
@@ -435,7 +439,7 @@ static int cmd_resistor(int argc, char **argv)
 	return EC_SUCCESS;
 }
 
-static int cmd_tx_clock(int argc, char **argv)
+static int cmd_tx_clock(int argc, const char **argv)
 {
 	int freq;
 	char *e;
@@ -452,7 +456,7 @@ static int cmd_tx_clock(int argc, char **argv)
 	return EC_SUCCESS;
 }
 
-static int cmd_rx_threshold(int argc, char **argv)
+static int cmd_rx_threshold(int argc, const char **argv)
 {
 	int mv;
 	char *e;
@@ -471,7 +475,7 @@ static int cmd_rx_threshold(int argc, char **argv)
 	return EC_SUCCESS;
 }
 
-static int cmd_ina_dump(int argc, char **argv, int index)
+static int cmd_ina_dump(int argc, const char **argv, int index)
 {
 	if (index == 1) { /* VCONN INA is off by default, switch it on */
 		ina2xx_write(index, INA2XX_REG_CONFIG, 0x4123);
@@ -483,7 +487,7 @@ static int cmd_ina_dump(int argc, char **argv, int index)
 	}
 
 	ccprintf("%s = %d mV ; %d mA\n", index == 0 ? "VBUS" : "VCONN",
-		ina2xx_get_voltage(index), ina2xx_get_current(index));
+		 ina2xx_get_voltage(index), ina2xx_get_current(index));
 
 	if (index == 1) /* power off VCONN INA */
 		ina2xx_write(index, INA2XX_REG_CONFIG, 0);
@@ -491,7 +495,7 @@ static int cmd_ina_dump(int argc, char **argv, int index)
 	return EC_SUCCESS;
 }
 
-static int cmd_bufwr(int argc, char **argv)
+static int cmd_bufwr(int argc, const char **argv)
 {
 	int idx, cnt, i;
 	char *e;
@@ -505,13 +509,13 @@ static int cmd_bufwr(int argc, char **argv)
 		return EC_ERROR_PARAM2;
 
 	for (i = 0; i < cnt; i++)
-		if (hex8tou32(argv[i+1], inj_cmds + idx + i))
+		if (hex8tou32(argv[i + 1], inj_cmds + idx + i))
 			return EC_ERROR_INVAL;
 
 	return EC_SUCCESS;
 }
 
-static int cmd_bufrd(int argc, char **argv)
+static int cmd_bufrd(int argc, const char **argv)
 {
 	int idx, i;
 	int cnt = 1;
@@ -537,7 +541,7 @@ static int cmd_bufrd(int argc, char **argv)
 	return EC_SUCCESS;
 }
 
-static int cmd_sink(int argc, char **argv)
+static int cmd_sink(int argc, const char **argv)
 {
 	/*
 	 * Jump to the RW section which should contain a firmware acting
@@ -548,18 +552,16 @@ static int cmd_sink(int argc, char **argv)
 	return EC_SUCCESS;
 }
 
-static int cmd_trace(int argc, char **argv)
+static int cmd_trace(int argc, const char **argv)
 {
 	if (argc < 1)
 		return EC_ERROR_PARAM_COUNT;
 
-	if (!strcasecmp(argv[0], "on") ||
-	    !strcasecmp(argv[0], "1"))
+	if (!strcasecmp(argv[0], "on") || !strcasecmp(argv[0], "1"))
 		set_trace_mode(TRACE_MODE_ON);
 	else if (!strcasecmp(argv[0], "raw"))
 		set_trace_mode(TRACE_MODE_RAW);
-	else if (!strcasecmp(argv[0], "off") ||
-		 !strcasecmp(argv[0], "0"))
+	else if (!strcasecmp(argv[0], "off") || !strcasecmp(argv[0], "0"))
 		set_trace_mode(TRACE_MODE_OFF);
 	else
 		return EC_ERROR_PARAM2;
@@ -567,7 +569,7 @@ static int cmd_trace(int argc, char **argv)
 	return EC_SUCCESS;
 }
 
-static int command_tw(int argc, char **argv)
+static int command_tw(int argc, const char **argv)
 {
 	if (!strcasecmp(argv[1], "send"))
 		return cmd_send(argc - 2, argv + 2);
diff --git a/board/twinkie/injector.h b/board/twinkie/injector.h
index 4a33f8ecf0..ed39522969 100644
--- a/board/twinkie/injector.h
+++ b/board/twinkie/injector.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,50 +21,50 @@
 
 /* Macros to extract values from FSM command words */
 #define INJ_CMD(w) ((w) >> 28)
-#define INJ_ARG(w) ((w) & 0x0FFFFFFF)
-#define INJ_ARG0(w) ((w) & 0x0000FFFF)
+#define INJ_ARG(w) ((w)&0x0FFFFFFF)
+#define INJ_ARG0(w) ((w)&0x0000FFFF)
 #define INJ_ARG1(w) (((w) >> 16) & 0xFF)
 #define INJ_ARG2(w) (((w) >> 24) & 0xF)
 #define INJ_ARG12(w) (((w) >> 16) & 0xFFF)
 
 enum inj_cmd {
-	INJ_CMD_END   = 0x0, /* stop the FSM */
-	INJ_CMD_SEND  = 0x1, /* Send message on CCx */
-			     /* arg0: header arg1/2:payload index/count  */
-	INJ_CMD_WAVE  = 0x2, /* Send arbitrary waveform */
-			     /* stored at index arg1 of len arg0 */
-	INJ_CMD_HRST  = 0x3, /* Send Hard Reset on CCx */
-	INJ_CMD_WAIT  = 0x4, /* Wait for arg12 edges if arg12 != 0 */
-			     /* and timeout after arg0 ms */
-	INJ_CMD_GET   = 0x5, /* Get parameter arg1 (INJ_GET_x) at index arg0 */
-	INJ_CMD_SET   = 0x6, /* Set parameter arg1 (INJ_SET_x) with arg0 */
-	INJ_CMD_JUMP  = 0x8, /* Jump to index (as arg0) */
+	INJ_CMD_END = 0x0, /* stop the FSM */
+	INJ_CMD_SEND = 0x1, /* Send message on CCx */
+	/* arg0: header arg1/2:payload index/count  */
+	INJ_CMD_WAVE = 0x2, /* Send arbitrary waveform */
+	/* stored at index arg1 of len arg0 */
+	INJ_CMD_HRST = 0x3, /* Send Hard Reset on CCx */
+	INJ_CMD_WAIT = 0x4, /* Wait for arg12 edges if arg12 != 0 */
+	/* and timeout after arg0 ms */
+	INJ_CMD_GET = 0x5, /* Get parameter arg1 (INJ_GET_x) at index arg0 */
+	INJ_CMD_SET = 0x6, /* Set parameter arg1 (INJ_SET_x) with arg0 */
+	INJ_CMD_JUMP = 0x8, /* Jump to index (as arg0) */
 	INJ_CMD_EXPCT = 0xC, /* Expect a packet with command arg2 */
-			     /* and timeout after arg0 ms */
-	INJ_CMD_NOP   = 0xF, /* No-Operation */
+	/* and timeout after arg0 ms */
+	INJ_CMD_NOP = 0xF, /* No-Operation */
 };
 
 enum inj_set {
-	INJ_SET_RESISTOR1  = 0, /* CC1 resistor as arg0 (INJ_RES_x) */
-	INJ_SET_RESISTOR2  = 1, /* CC2 resistor as arg0 (INJ_RES_x) */
-	INJ_SET_RECORD     = 2, /* Recording on/off */
-	INJ_SET_TX_SPEED   = 3, /* TX frequency is arg0 kHz */
-	INJ_SET_RX_THRESH  = 4, /* RX voltage threshold is arg0 mV */
-	INJ_SET_POLARITY   = 5, /* Polarity for other operations (INJ_POL_CC) */
-	INJ_SET_TRACE      = 6, /* Text packet trace on/raw/off */
+	INJ_SET_RESISTOR1 = 0, /* CC1 resistor as arg0 (INJ_RES_x) */
+	INJ_SET_RESISTOR2 = 1, /* CC2 resistor as arg0 (INJ_RES_x) */
+	INJ_SET_RECORD = 2, /* Recording on/off */
+	INJ_SET_TX_SPEED = 3, /* TX frequency is arg0 kHz */
+	INJ_SET_RX_THRESH = 4, /* RX voltage threshold is arg0 mV */
+	INJ_SET_POLARITY = 5, /* Polarity for other operations (INJ_POL_CC) */
+	INJ_SET_TRACE = 6, /* Text packet trace on/raw/off */
 };
 
 enum inj_get {
-	INJ_GET_CC       = 0,  /* CC1/CC2 voltages in mV */
-	INJ_GET_VBUS     = 1,  /* VBUS voltage in mV and current in mA */
-	INJ_GET_VCONN    = 2, /* VCONN voltage in mV and current in mA */
+	INJ_GET_CC = 0, /* CC1/CC2 voltages in mV */
+	INJ_GET_VBUS = 1, /* VBUS voltage in mV and current in mA */
+	INJ_GET_VCONN = 2, /* VCONN voltage in mV and current in mA */
 	INJ_GET_POLARITY = 3, /* Current polarity (INJ_POL_CC) */
 };
 
 enum inj_res {
-	INJ_RES_NONE  = 0,
-	INJ_RES_RA    = 1,
-	INJ_RES_RD    = 2,
+	INJ_RES_NONE = 0,
+	INJ_RES_RA = 1,
+	INJ_RES_RD = 2,
 	INJ_RES_RPUSB = 3,
 	INJ_RES_RP1A5 = 4,
 	INJ_RES_RP3A0 = 5,
@@ -79,7 +79,7 @@ enum inj_pol {
 enum trace_mode {
 	TRACE_MODE_OFF = 0,
 	TRACE_MODE_RAW = 1,
-	TRACE_MODE_ON  = 2,
+	TRACE_MODE_ON = 2,
 };
 
 /* Number of words in the FSM command/data buffer  */
diff --git a/board/twinkie/simpletrace.c b/board/twinkie/simpletrace.c
index f68a09adcf..fdc4cbfbb2 100644
--- a/board/twinkie/simpletrace.c
+++ b/board/twinkie/simpletrace.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,6 +11,7 @@
 #include "hooks.h"
 #include "hwtimer.h"
 #include "injector.h"
+#include "printf.h"
 #include "registers.h"
 #include "system.h"
 #include "task.h"
@@ -25,61 +26,57 @@ int trace_mode;
 /* The FSM is waiting for the following command (0 == None) */
 uint8_t expected_cmd;
 
-static const char * const ctrl_msg_name[] = {
-	[0]                      = "RSVD-C0",
-	[PD_CTRL_GOOD_CRC]       = "GOODCRC",
-	[PD_CTRL_GOTO_MIN]       = "GOTOMIN",
-	[PD_CTRL_ACCEPT]         = "ACCEPT",
-	[PD_CTRL_REJECT]         = "REJECT",
-	[PD_CTRL_PING]           = "PING",
-	[PD_CTRL_PS_RDY]         = "PSRDY",
+static const char *const ctrl_msg_name[] = {
+	[0] = "RSVD-C0",
+	[PD_CTRL_GOOD_CRC] = "GOODCRC",
+	[PD_CTRL_GOTO_MIN] = "GOTOMIN",
+	[PD_CTRL_ACCEPT] = "ACCEPT",
+	[PD_CTRL_REJECT] = "REJECT",
+	[PD_CTRL_PING] = "PING",
+	[PD_CTRL_PS_RDY] = "PSRDY",
 	[PD_CTRL_GET_SOURCE_CAP] = "GSRCCAP",
-	[PD_CTRL_GET_SINK_CAP]   = "GSNKCAP",
-	[PD_CTRL_DR_SWAP]        = "DRSWAP",
-	[PD_CTRL_PR_SWAP]        = "PRSWAP",
-	[PD_CTRL_VCONN_SWAP]     = "VCONNSW",
-	[PD_CTRL_WAIT]           = "WAIT",
-	[PD_CTRL_SOFT_RESET]     = "SFT-RST",
-	[14]                     = "RSVD-C14",
-	[15]                     = "RSVD-C15",
+	[PD_CTRL_GET_SINK_CAP] = "GSNKCAP",
+	[PD_CTRL_DR_SWAP] = "DRSWAP",
+	[PD_CTRL_PR_SWAP] = "PRSWAP",
+	[PD_CTRL_VCONN_SWAP] = "VCONNSW",
+	[PD_CTRL_WAIT] = "WAIT",
+	[PD_CTRL_SOFT_RESET] = "SFT-RST",
+	[14] = "RSVD-C14",
+	[15] = "RSVD-C15",
 };
 
-static const char * const data_msg_name[] = {
-	[0]                      = "RSVD-D0",
-	[PD_DATA_SOURCE_CAP]     = "SRCCAP",
-	[PD_DATA_REQUEST]        = "REQUEST",
-	[PD_DATA_BIST]           = "BIST",
-	[PD_DATA_SINK_CAP]       = "SNKCAP",
+static const char *const data_msg_name[] = {
+	[0] = "RSVD-D0",
+	[PD_DATA_SOURCE_CAP] = "SRCCAP",
+	[PD_DATA_REQUEST] = "REQUEST",
+	[PD_DATA_BIST] = "BIST",
+	[PD_DATA_SINK_CAP] = "SNKCAP",
 	/* 5-14 Reserved */
-	[PD_DATA_VENDOR_DEF]     = "VDM",
+	[PD_DATA_VENDOR_DEF] = "VDM",
 };
 
-static const char * const svdm_cmd_name[] = {
-	[CMD_DISCOVER_IDENT]     = "DISCID",
-	[CMD_DISCOVER_SVID]	 = "DISCSVID",
-	[CMD_DISCOVER_MODES]	 = "DISCMODE",
-	[CMD_ENTER_MODE]	 = "ENTER",
-	[CMD_EXIT_MODE]		 = "EXIT",
-	[CMD_ATTENTION]		 = "ATTN",
-	[CMD_DP_STATUS]          = "DPSTAT",
-	[CMD_DP_CONFIG]          = "DPCFG",
+static const char *const svdm_cmd_name[] = {
+	[CMD_DISCOVER_IDENT] = "DISCID",   [CMD_DISCOVER_SVID] = "DISCSVID",
+	[CMD_DISCOVER_MODES] = "DISCMODE", [CMD_ENTER_MODE] = "ENTER",
+	[CMD_EXIT_MODE] = "EXIT",	   [CMD_ATTENTION] = "ATTN",
+	[CMD_DP_STATUS] = "DPSTAT",	   [CMD_DP_CONFIG] = "DPCFG",
 };
 
-static const char * const svdm_cmdt_name[] = {
-	[CMDT_INIT]     = "INI",
-	[CMDT_RSP_ACK]  = "ACK",
-	[CMDT_RSP_NAK]  = "NAK",
+static const char *const svdm_cmdt_name[] = {
+	[CMDT_INIT] = "INI",
+	[CMDT_RSP_ACK] = "ACK",
+	[CMDT_RSP_NAK] = "NAK",
 	[CMDT_RSP_BUSY] = "BSY",
 };
 
 static void print_pdo(uint32_t word)
 {
 	if ((word & PDO_TYPE_MASK) == PDO_TYPE_BATTERY)
-		ccprintf(" %dmV/%dmW", ((word>>10)&0x3ff)*50,
-			 (word&0x3ff)*250);
+		ccprintf(" %dmV/%dmW", ((word >> 10) & 0x3ff) * 50,
+			 (word & 0x3ff) * 250);
 	else
-		ccprintf(" %dmV/%dmA", ((word>>10)&0x3ff)*50,
-			 (word&0x3ff)*10);
+		ccprintf(" %dmV/%dmA", ((word >> 10) & 0x3ff) * 50,
+			 (word & 0x3ff) * 10);
 }
 
 static void print_rdo(uint32_t word)
@@ -109,9 +106,11 @@ static void print_packet(int head, uint32_t *payload)
 	int id = PD_HEADER_ID(head);
 	const char *name;
 	const char *prole;
+	char ts_str[PRINTF_TIMESTAMP_BUF_SIZE];
 
 	if (trace_mode == TRACE_MODE_RAW) {
-		ccprintf("%pT[%04x]", PRINTF_TIMESTAMP_NOW, head);
+		snprintf_timestamp_now(ts_str, sizeof(ts_str));
+		ccprintf("%s[%04x]", ts_str, head);
 		for (i = 0; i < cnt; i++)
 			ccprintf(" %08x", payload[i]);
 		ccputs("\n");
@@ -119,8 +118,8 @@ static void print_packet(int head, uint32_t *payload)
 	}
 	name = cnt ? data_msg_name[typ] : ctrl_msg_name[typ];
 	prole = head & (PD_ROLE_SOURCE << 8) ? "SRC" : "SNK";
-	ccprintf("%pT %s/%d [%04x]%s",
-		 PRINTF_TIMESTAMP_NOW, prole, id, head, name);
+	snprintf_timestamp_now(ts_str, sizeof(ts_str));
+	ccprintf("%s %s/%d [%04x]%s", ts_str, prole, id, head, name);
 	if (!cnt) { /* Control message : we are done */
 		ccputs("\n");
 		return;
@@ -144,27 +143,32 @@ static void print_packet(int head, uint32_t *payload)
 			break;
 		default:
 			ccprintf(" %08x", payload[i]);
-	}
+		}
 	ccputs("\n");
 }
 
 static void print_error(enum pd_rx_errors err)
 {
+	char ts_str[PRINTF_TIMESTAMP_BUF_SIZE];
+
+	snprintf_timestamp_now(ts_str, sizeof(ts_str));
+
 	if (err == PD_RX_ERR_INVAL)
-		ccprintf("%pT TMOUT\n", PRINTF_TIMESTAMP_NOW);
+		ccprintf("%s TMOUT\n", ts_str);
 	else if (err == PD_RX_ERR_HARD_RESET)
-		ccprintf("%pT HARD-RST\n", PRINTF_TIMESTAMP_NOW);
+		ccprintf("%s HARD-RST\n", ts_str);
 	else if (err == PD_RX_ERR_UNSUPPORTED_SOP)
-		ccprintf("%pT SOP*\n", PRINTF_TIMESTAMP_NOW);
+		ccprintf("%s SOP*\n", ts_str);
 	else
 		ccprintf("ERR %d\n", err);
 }
 
+#ifdef HAS_TASK_SNIFFER
 /* keep track of RX edge timing in order to trigger receive */
 static timestamp_t rx_edge_ts[2][PD_RX_TRANSITION_COUNT];
 static int rx_edge_ts_idx[2];
 
-void rx_event(void)
+static void rx_event(void)
 {
 	int pending, i;
 	int next_idx;
@@ -175,19 +179,20 @@ void rx_event(void)
 		if (pending & (1 << (21 + i))) {
 			rx_edge_ts[i][rx_edge_ts_idx[i]].val = get_time().val;
 			next_idx = (rx_edge_ts_idx[i] ==
-					PD_RX_TRANSITION_COUNT - 1) ?
-						0 : rx_edge_ts_idx[i] + 1;
+				    PD_RX_TRANSITION_COUNT - 1) ?
+					   0 :
+					   rx_edge_ts_idx[i] + 1;
 
 			/*
 			 * If we have seen enough edges in a certain amount of
 			 * time, then trigger RX start.
 			 */
 			if ((rx_edge_ts[i][rx_edge_ts_idx[i]].val -
-			     rx_edge_ts[i][next_idx].val)
-			     < PD_RX_TRANSITION_WINDOW) {
+			     rx_edge_ts[i][next_idx].val) <
+			    PD_RX_TRANSITION_WINDOW) {
 				/* acquire the message only on the active CC */
-				STM32_COMP_CSR &= ~(i ? STM32_COMP_CMP1EN
-						      : STM32_COMP_CMP2EN);
+				STM32_COMP_CSR &= ~(i ? STM32_COMP_CMP1EN :
+							STM32_COMP_CMP2EN);
 				/* start sampling */
 				pd_rx_start(0);
 				/*
@@ -197,7 +202,7 @@ void rx_event(void)
 				pd_rx_disable_monitoring(0);
 				/* trigger the analysis in the task */
 #ifdef HAS_TASK_SNIFFER
-				task_set_event(TASK_ID_SNIFFER, 1 << i, 0);
+				task_set_event(TASK_ID_SNIFFER, 1 << i);
 #endif
 				/* start reception only one CC line */
 				break;
@@ -209,7 +214,6 @@ void rx_event(void)
 		}
 	}
 }
-#ifdef HAS_TASK_SNIFFER
 DECLARE_IRQ(STM32_IRQ_COMP, rx_event, 1);
 #endif
 
diff --git a/board/twinkie/sniffer.c b/board/twinkie/sniffer.c
index 6eb2e0824e..501608717d 100644
--- a/board/twinkie/sniffer.c
+++ b/board/twinkie/sniffer.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,8 +9,9 @@
 #include "console.h"
 #include "dma.h"
 #include "gpio.h"
-#include "hwtimer.h"
 #include "hooks.h"
+#include "hwtimer.h"
+#include "ina2xx.h"
 #include "injector.h"
 #include "link_defs.h"
 #include "registers.h"
@@ -19,7 +20,6 @@
 #include "usb_descriptor.h"
 #include "usb_hw.h"
 #include "util.h"
-#include "ina2xx.h"
 
 /* Size of one USB packet buffer */
 #define EP_BUF_SIZE 64
@@ -105,11 +105,11 @@ static void ep_tx(void)
 		btable_ep[USB_EP_SNIFFER].tx_addr = usb_sram_addr(ep_buf[b]);
 	}
 	/* re-enable data transmission if we have available data */
-	btable_ep[USB_EP_SNIFFER].tx_count = (free_usb & (1<<b)) ? 0
-								 : EP_BUF_SIZE;
+	btable_ep[USB_EP_SNIFFER].tx_count =
+		(free_usb & (1 << b)) ? 0 : EP_BUF_SIZE;
 	STM32_TOGGLE_EP(USB_EP_SNIFFER, EP_TX_MASK, EP_TX_VALID, 0);
 	/* wake up the processing */
-	task_set_event(TASK_ID_SNIFFER, USB_EVENT, 0);
+	task_set_event(TASK_ID_SNIFFER, USB_EVENT);
 }
 
 static void ep_event(enum usb_ep_event evt)
@@ -127,7 +127,6 @@ static void ep_event(enum usb_ep_event evt)
 }
 USB_DECLARE_EP(USB_EP_SNIFFER, ep_tx, ep_tx, ep_event);
 
-
 /* --- RX operation using comparator linked to timer --- */
 /* RX on CC1 is using COMP1 triggering TIM1 CH1 */
 #define TIM_RX1 1
@@ -144,13 +143,13 @@ USB_DECLARE_EP(USB_EP_SNIFFER, ep_tx, ep_tx, ep_event);
 static const struct dma_option dma_tim_cc1 = {
 	DMAC_TIM_RX1, (void *)&STM32_TIM_CCRx(TIM_RX1, TIM_RX1_CCR_IDX),
 	STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
-	STM32_DMA_CCR_CIRC | STM32_DMA_CCR_TCIE | STM32_DMA_CCR_HTIE
+		STM32_DMA_CCR_CIRC | STM32_DMA_CCR_TCIE | STM32_DMA_CCR_HTIE
 };
 
 static const struct dma_option dma_tim_cc2 = {
 	DMAC_TIM_RX2, (void *)&STM32_TIM_CCRx(TIM_RX2, TIM_RX2_CCR_IDX),
 	STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
-	STM32_DMA_CCR_CIRC | STM32_DMA_CCR_TCIE | STM32_DMA_CCR_HTIE
+		STM32_DMA_CCR_CIRC | STM32_DMA_CCR_TCIE | STM32_DMA_CCR_HTIE
 };
 
 /* sequence number for sample buffers */
@@ -161,7 +160,7 @@ static uint32_t oflow;
 #define SNIFFER_CHANNEL_CC1 0
 #define SNIFFER_CHANNEL_CC2 1
 
-#define get_channel(b)   (((b) >> 12) & 0x1)
+#define get_channel(b) (((b) >> 12) & 0x1)
 
 void tim_rx1_handler(uint32_t stat)
 {
@@ -171,8 +170,7 @@ void tim_rx1_handler(uint32_t stat)
 	uint32_t next = idx ? 0x0001 : 0x0100;
 
 	sample_tstamp[idx] = __hw_clock_source_read();
-	sample_seq[idx] = ((seq++ << 3) & 0x0ff8) |
-			(SNIFFER_CHANNEL_CC1<<12);
+	sample_seq[idx] = ((seq++ << 3) & 0x0ff8) | (SNIFFER_CHANNEL_CC1 << 12);
 	if (filled_dma & next) {
 		oflow++;
 		sample_seq[idx] |= 0x8000;
@@ -193,8 +191,7 @@ void tim_rx2_handler(uint32_t stat)
 
 	idx += 2;
 	sample_tstamp[idx] = __hw_clock_source_read();
-	sample_seq[idx] = ((seq++ << 3) & 0x0ff8) |
-			(SNIFFER_CHANNEL_CC2<<12);
+	sample_seq[idx] = ((seq++ << 3) & 0x0ff8) | (SNIFFER_CHANNEL_CC2 << 12);
 	if (filled_dma & next) {
 		oflow++;
 		sample_seq[idx] |= 0x8000;
@@ -206,19 +203,19 @@ void tim_rx2_handler(uint32_t stat)
 	led_set_activity(1);
 }
 
-void tim_dma_handler(void)
+static void tim_dma_handler(void)
 {
 	stm32_dma_regs_t *dma = STM32_DMA1_REGS;
-	uint32_t stat = dma->isr & (STM32_DMA_ISR_HTIF(DMAC_TIM_RX1)
-				  | STM32_DMA_ISR_TCIF(DMAC_TIM_RX1)
-				  | STM32_DMA_ISR_HTIF(DMAC_TIM_RX2)
-				  | STM32_DMA_ISR_TCIF(DMAC_TIM_RX2));
+	uint32_t stat = dma->isr & (STM32_DMA_ISR_HTIF(DMAC_TIM_RX1) |
+				    STM32_DMA_ISR_TCIF(DMAC_TIM_RX1) |
+				    STM32_DMA_ISR_HTIF(DMAC_TIM_RX2) |
+				    STM32_DMA_ISR_TCIF(DMAC_TIM_RX2));
 	if (stat & STM32_DMA_ISR_ALL(DMAC_TIM_RX2))
 		tim_rx2_handler(stat);
 	else
 		tim_rx1_handler(stat);
 	/* time to process the samples */
-	task_set_event(TASK_ID_SNIFFER, USB_EVENT, 0);
+	task_set_event(TASK_ID_SNIFFER, USB_EVENT);
 }
 DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_4_7, tim_dma_handler, 1);
 
@@ -251,30 +248,26 @@ static void rx_timer_init(int tim_id, timer_ctlr_t *tim, int ch_idx, int up_idx)
 	tim->sr = 0;
 }
 
-
-
 void sniffer_init(void)
 {
 	/* remap TIM1 CH1/2/3 to DMA channel 6 */
 	STM32_SYSCFG_CFGR1 |= BIT(28);
 
 	/* TIM1 CH1 for CC1 RX */
-	rx_timer_init(TIM_RX1, (void *)STM32_TIM_BASE(TIM_RX1),
-		      TIM_RX1_CCR_IDX, 2);
+	rx_timer_init(TIM_RX1, (void *)STM32_TIM_BASE(TIM_RX1), TIM_RX1_CCR_IDX,
+		      2);
 	/* TIM3 CH4 for CC2 RX */
-	rx_timer_init(TIM_RX2, (void *)STM32_TIM_BASE(TIM_RX2),
-		      TIM_RX2_CCR_IDX, 2);
+	rx_timer_init(TIM_RX2, (void *)STM32_TIM_BASE(TIM_RX2), TIM_RX2_CCR_IDX,
+		      2);
 
 	/* turn on COMP/SYSCFG */
 	STM32_RCC_APB2ENR |= BIT(0);
-	STM32_COMP_CSR = STM32_COMP_CMP1EN | STM32_COMP_CMP1MODE_HSPEED |
-			 STM32_COMP_CMP1INSEL_VREF12 |
-			 STM32_COMP_CMP1OUTSEL_TIM1_IC1 |
-			 STM32_COMP_CMP1HYST_HI |
-			 STM32_COMP_CMP2EN | STM32_COMP_CMP2MODE_HSPEED |
-			 STM32_COMP_CMP2INSEL_VREF12 |
-			 STM32_COMP_CMP2OUTSEL_TIM2_IC4 |
-			 STM32_COMP_CMP2HYST_HI;
+	STM32_COMP_CSR =
+		STM32_COMP_CMP1EN | STM32_COMP_CMP1MODE_HSPEED |
+		STM32_COMP_CMP1INSEL_VREF12 | STM32_COMP_CMP1OUTSEL_TIM1_IC1 |
+		STM32_COMP_CMP1HYST_HI | STM32_COMP_CMP2EN |
+		STM32_COMP_CMP2MODE_HSPEED | STM32_COMP_CMP2INSEL_VREF12 |
+		STM32_COMP_CMP2OUTSEL_TIM2_IC4 | STM32_COMP_CMP2HYST_HI;
 
 	/* start sampling the edges on the CC lines using the RX timers */
 	dma_start_rx(&dma_tim_cc1, RX_COUNT, samples[0]);
@@ -311,15 +304,14 @@ void sniffer_task(void)
 			ep_buf[u][0] = sample_seq[d >> 3] | (d & 7);
 			ep_buf[u][1] = sample_tstamp[d >> 3];
 
-			memcpy_to_usbram(
-					((void *)usb_sram_addr(ep_buf[u]
-						+ (EP_PACKET_HEADER_SIZE>>1))),
-					samples[d >> 4]+off,
-					EP_PAYLOAD_SIZE);
-			deprecated_atomic_clear_bits((uint32_t *)&free_usb,
-						     1 << u);
+			memcpy_to_usbram(((void *)usb_sram_addr(
+						 ep_buf[u] +
+						 (EP_PACKET_HEADER_SIZE >> 1))),
+					 samples[d >> 4] + off,
+					 EP_PAYLOAD_SIZE);
+			atomic_clear_bits((atomic_t *)&free_usb, 1 << u);
 			u = !u;
-			deprecated_atomic_clear_bits(&filled_dma, 1 << d);
+			atomic_clear_bits((atomic_t *)&filled_dma, 1 << d);
 		}
 		led_reset_record();
 
@@ -333,8 +325,8 @@ void sniffer_task(void)
 
 int wait_packet(int pol, uint32_t min_edges, uint32_t timeout_us)
 {
-	stm32_dma_chan_t *chan = dma_get_channel(pol ? DMAC_TIM_RX2
-						     : DMAC_TIM_RX1);
+	stm32_dma_chan_t *chan =
+		dma_get_channel(pol ? DMAC_TIM_RX2 : DMAC_TIM_RX1);
 	uint32_t t0 = __hw_clock_source_read();
 	uint32_t c0 = chan->cndtr;
 	uint32_t t_gap = t0;
@@ -356,7 +348,7 @@ int wait_packet(int pol, uint32_t min_edges, uint32_t timeout_us)
 				total_edges += nb;
 			} else {
 				if ((t - t_gap) > 20 &&
-				    (total_edges - (t - t0)/256) >= min_edges)
+				    (total_edges - (t - t0) / 256) >= min_edges)
 					/* real gap after the packet */
 					break;
 			}
@@ -393,11 +385,10 @@ static void sniffer_sysjump(void)
 }
 DECLARE_HOOK(HOOK_SYSJUMP, sniffer_sysjump, HOOK_PRIO_DEFAULT);
 
-static int command_sniffer(int argc, char **argv)
+static int command_sniffer(int argc, const char **argv)
 {
 	ccprintf("Seq number:%d Overflows: %d\n", seq, oflow);
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(sniffer, command_sniffer,
-			"[]", "Buffering status");
+DECLARE_CONSOLE_COMMAND(sniffer, command_sniffer, "[]", "Buffering status");
diff --git a/board/twinkie/usb_pd_config.h b/board/twinkie/usb_pd_config.h
index 1c20a9df77..062c174d8a 100644
--- a/board/twinkie/usb_pd_config.h
+++ b/board/twinkie/usb_pd_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -50,7 +50,7 @@ static inline void spi_enable_clock(int port)
 #define DMAC_TIM_RX(p) STM32_DMAC_CH2
 #define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
 #define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
-#define TIM_CCR_CS  1
+#define TIM_CCR_CS 1
 #define EXTI_COMP_MASK(p) (BIT(21) | BIT(22))
 #define IRQ_COMP STM32_IRQ_COMP
 /* triggers packet detection on comparator falling edge */
@@ -102,11 +102,11 @@ static inline void pd_tx_enable(int port, int polarity)
 static inline void pd_tx_disable(int port, int polarity)
 {
 	/* TX_DATA on PB4 is an output low GPIO to disable the FET */
-	STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B) & ~(3 << (2*4)))
-							     |  (1 << (2*4));
+	STM32_GPIO_MODER(GPIO_B) =
+		(STM32_GPIO_MODER(GPIO_B) & ~(3 << (2 * 4))) | (1 << (2 * 4));
 	/* TX_DATA on PA6 is an output low GPIO to disable the FET */
-	STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) & ~(3 << (2*6)))
-							     |  (1 << (2*6));
+	STM32_GPIO_MODER(GPIO_A) =
+		(STM32_GPIO_MODER(GPIO_A) & ~(3 << (2 * 6))) | (1 << (2 * 6));
 	/*
 	 * Tri-state the low side after the high side
 	 * to ensure we are not going above Vnc
@@ -119,11 +119,12 @@ static inline void pd_tx_disable(int port, int polarity)
 static inline void pd_select_polarity(int port, int polarity)
 {
 	/* use the right comparator */
-	STM32_COMP_CSR = (STM32_COMP_CSR
-		& ~(STM32_COMP_CMP1INSEL_MASK | STM32_COMP_CMP2INSEL_MASK
-		  |STM32_COMP_CMP1EN | STM32_COMP_CMP2EN))
-		| STM32_COMP_CMP1INSEL_INM4 | STM32_COMP_CMP2INSEL_INM4
-		| (polarity ? STM32_COMP_CMP2EN : STM32_COMP_CMP1EN);
+	STM32_COMP_CSR =
+		(STM32_COMP_CSR &
+		 ~(STM32_COMP_CMP1INSEL_MASK | STM32_COMP_CMP2INSEL_MASK |
+		   STM32_COMP_CMP1EN | STM32_COMP_CMP2EN)) |
+		STM32_COMP_CMP1INSEL_INM4 | STM32_COMP_CMP2INSEL_INM4 |
+		(polarity ? STM32_COMP_CMP2EN : STM32_COMP_CMP1EN);
 }
 
 /* Initialize pins used for clocking */
diff --git a/board/twinkie/usb_pd_pdo.c b/board/twinkie/usb_pd_pdo.c
new file mode 100644
index 0000000000..fbc0624f80
--- /dev/null
+++ b/board/twinkie/usb_pd_pdo.c
@@ -0,0 +1,24 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "compile_time_macros.h"
+#include "usb_pd.h"
+#include "usb_pd_pdo.h"
+
+#define PDO_FIXED_FLAGS (PDO_FIXED_UNCONSTRAINED | PDO_FIXED_DATA_SWAP)
+
+const uint32_t pd_src_pdo[] = {
+	PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS),
+	PDO_FIXED(12000, 3000, PDO_FIXED_FLAGS),
+	PDO_FIXED(20000, 3000, PDO_FIXED_FLAGS),
+};
+const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
+
+const uint32_t pd_snk_pdo[] = {
+	PDO_FIXED(5000, 500, PDO_FIXED_FLAGS),
+	PDO_BATT(4750, 21000, 15000),
+	PDO_VAR(4750, 21000, 3000),
+};
+const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
diff --git a/board/twinkie/usb_pd_pdo.h b/board/twinkie/usb_pd_pdo.h
new file mode 100644
index 0000000000..0badd0f7bf
--- /dev/null
+++ b/board/twinkie/usb_pd_pdo.h
@@ -0,0 +1,17 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_BOARD_TWINKIE_USB_PD_PDO_H
+#define __CROS_EC_BOARD_TWINKIE_USB_PD_PDO_H
+
+#include "stdint.h"
+
+extern const uint32_t pd_src_pdo[3];
+extern const int pd_src_pdo_cnt;
+
+extern const uint32_t pd_snk_pdo[3];
+extern const int pd_snk_pdo_cnt;
+
+#endif /* __CROS_EC_BOARD_TWINKIE_USB_PD_PDO_H */
diff --git a/board/twinkie/usb_pd_policy.c b/board/twinkie/usb_pd_policy.c
index 62ecd6e0db..c3434cd0d5 100644
--- a/board/twinkie/usb_pd_policy.c
+++ b/board/twinkie/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,27 +11,12 @@
 #include "registers.h"
 #include "task.h"
 #include "timer.h"
-#include "util.h"
 #include "usb_pd.h"
+#include "usb_pd_pdo.h"
+#include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-#define PDO_FIXED_FLAGS (PDO_FIXED_UNCONSTRAINED | PDO_FIXED_DATA_SWAP)
-
-const uint32_t pd_src_pdo[] = {
-		PDO_FIXED(5000,  3000, PDO_FIXED_FLAGS),
-		PDO_FIXED(12000, 3000, PDO_FIXED_FLAGS),
-		PDO_FIXED(20000, 3000, PDO_FIXED_FLAGS),
-};
-const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
-
-const uint32_t pd_snk_pdo[] = {
-		PDO_FIXED(5000, 500, PDO_FIXED_FLAGS),
-		PDO_BATT(4750, 21000, 15000),
-		PDO_VAR(4750, 21000, 3000),
-};
-const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 void pd_set_input_current_limit(int port, uint32_t max_ma,
 				uint32_t supply_voltage)
@@ -65,27 +50,23 @@ __override int pd_check_power_swap(int port)
 	return 0;
 }
 
-__override int pd_check_data_swap(int port,
-				  enum pd_data_role data_role)
+__override int pd_check_data_swap(int port, enum pd_data_role data_role)
 {
 	/* Always allow data swap */
 	return 1;
 }
 
-__override void pd_check_pr_role(int port,
-				 enum pd_power_role pr_role,
+__override void pd_check_pr_role(int port, enum pd_power_role pr_role,
 				 int flags)
 {
 }
 
-__override void pd_check_dr_role(int port,
-				 enum pd_data_role dr_role,
-				 int flags)
+__override void pd_check_dr_role(int port, enum pd_data_role dr_role, int flags)
 {
 }
 
 __override int pd_custom_vdm(int port, int cnt, uint32_t *payload,
-		  uint32_t **rpayload)
+			     uint32_t **rpayload)
 {
 	return 0;
 }
diff --git a/board/twinkie/vif_override.xml b/board/twinkie/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/twinkie/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/vell/battery.c b/board/vell/battery.c
new file mode 100644
index 0000000000..0ffb7fb015
--- /dev/null
+++ b/board/vell/battery.c
@@ -0,0 +1,99 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "cbi.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "gpio.h"
+/*
+ * Battery info for all Vell battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	/* Simplo Coslight Battery Information */
+	[BATTERY_SIMPLO_COS] = {
+		.fuel_gauge = {
+			.manuf_name = "333-1C-DA-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8800,	/* mV */
+			.voltage_normal = 7600,
+			.voltage_min = 6000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = 0,
+			.discharging_max_c = 60,
+		},
+	},
+	/* 916Q2303H Simplo CosMX Battery Information */
+	[BATTERY_SIMPLO_COS2] = {
+		.fuel_gauge = {
+			.manuf_name = "133-1C-39-A",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x0006,
+			},
+		},
+		.batt_info = {
+			.voltage_max = 8860,	/* mV */
+			.voltage_normal = 7720,
+			.voltage_min = 6000,
+			.precharge_current = 256,	/* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 51,
+			.discharging_min_c = -10,
+			.discharging_max_c = 60,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SIMPLO_COS2;
+
+enum battery_present battery_hw_present(void)
+{
+	/* The GPIO is low when the battery is physically present */
+	return gpio_get_level(GPIO_EC_BATT_PRES_ODL) ? BP_NO : BP_YES;
+}
diff --git a/board/vell/board.c b/board/vell/board.c
new file mode 100644
index 0000000000..a475684a66
--- /dev/null
+++ b/board/vell/board.c
@@ -0,0 +1,66 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "button.h"
+#include "charge_ramp.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/als_tcs3400.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "lid_switch.h"
+#include "panic.h"
+#include "power.h"
+#include "power/intel_x86.h"
+#include "power_button.h"
+#include "registers.h"
+#include "switch.h"
+#include "throttle_ap.h"
+#include "usbc_config.h"
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* Console output macros */
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+
+static void board_chipset_startup(void)
+{
+	/* Allow keyboard backlight to be enabled */
+
+	gpio_set_level(GPIO_EC_KB_BL_EN, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
+
+static void board_chipset_shutdown(void)
+{
+	/* Turn off the keyboard backlight if it's on. */
+
+	gpio_set_level(GPIO_EC_KB_BL_EN, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
+
+static void set_board_id_5_gpios(void)
+{
+	if (get_board_id() < 6) {
+		power_signal_list[X86_ALL_SYS_PGOOD].gpio =
+			GPIO_ID_5_SEQ_EC_ALL_SYS_PG;
+	}
+}
+DECLARE_HOOK(HOOK_INIT, set_board_id_5_gpios, HOOK_PRIO_POST_FIRST);
+
+__override int intel_x86_get_pg_ec_all_sys_pwrgd(void)
+{
+	if (get_board_id() < 6)
+		return gpio_get_level(GPIO_ID_5_SEQ_EC_ALL_SYS_PG);
+
+	return gpio_get_level(GPIO_PG_EC_ALL_SYS_PWRGD);
+}
diff --git a/board/vell/board.h b/board/vell/board.h
new file mode 100644
index 0000000000..ca4d055b9b
--- /dev/null
+++ b/board/vell/board.h
@@ -0,0 +1,247 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Vell board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "compile_time_macros.h"
+
+/* Baseboard features */
+#include "baseboard.h"
+
+/*
+ * This will happen automatically on NPCX9 ES2 and later. Do not remove
+ * until we can confirm all earlier chips are out of service.
+ */
+#define CONFIG_HIBERNATE_PSL_VCC1_RST_WAKEUP
+
+/* No side buttons */
+#undef CONFIG_MKBP_INPUT_DEVICES
+#undef CONFIG_VOLUME_BUTTONS
+
+/* Sensors */
+#undef CONFIG_TABLET_MODE
+#undef CONFIG_TABLET_MODE_SWITCH
+#undef CONFIG_GMR_TABLET_MODE
+
+/* TCS3400 ALS */
+#define CONFIG_ALS
+#define ALS_COUNT 1
+#define CONFIG_ALS_TCS3400
+#define CONFIG_ALS_TCS3400_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS)
+
+/* Enable sensor fifo, must also define the _SIZE and _THRES */
+#define CONFIG_ACCEL_FIFO
+/* FIFO size is in power of 2. */
+#define CONFIG_ACCEL_FIFO_SIZE 256
+/* Depends on how fast the AP boots and typical ODRs */
+#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
+
+/* Sensors without hardware FIFO are in forced mode */
+#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(CLEAR_ALS)
+
+/* USB Type C and USB PD defines */
+#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
+
+#define CONFIG_IO_EXPANDER
+#define CONFIG_IO_EXPANDER_NCT38XX
+#define CONFIG_IO_EXPANDER_PORT_COUNT 4
+
+#define CONFIG_USB_PD_FRS_PPC
+
+#define CONFIG_USBC_RETIMER_INTEL_BB
+
+#define CONFIG_USBC_PPC_SYV682X
+
+#undef CONFIG_SYV682X_HV_ILIM
+#define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_5_50
+
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 4
+
+/* TODO: b/177608416 - measure and check these values on brya */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
+
+/* USB Type C and USB PD defines */
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_CURRENT_MA 5000
+#define PD_MAX_VOLTAGE_MV 20000
+/* Max Power = 100 W */
+#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
+
+/*
+ * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
+ * signal.
+ */
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
+#define GPIO_RIGHT_LED_AMBER_L GPIO_LED_1_L
+#define GPIO_RIGHT_LED_WHITE_L GPIO_LED_2_L
+#define GPIO_LEFT_LED_AMBER_L GPIO_LED_3_L
+#define GPIO_LEFT_LED_WHITE_L GPIO_LED_4_L
+
+/* System has back-lit keyboard */
+#define CONFIG_PWM_KBLIGHT
+
+/* I2C Bus Configuration */
+
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+
+#define I2C_PORT_USB_C0_C1_TCPC NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C2_C3_TCPC NPCX_I2C_PORT4_1
+
+#define I2C_PORT_USB_C0_C1_PPC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C2_C3_PPC NPCX_I2C_PORT6_1
+
+#define I2C_PORT_USB_C0_C1_BC12 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C2_C3_BC12 NPCX_I2C_PORT6_1
+
+#define I2C_PORT_USB_C0_C1_MUX NPCX_I2C_PORT3_0
+#define I2C_PORT_USB_C2_C3_MUX NPCX_I2C_PORT3_0
+
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+
+/*
+ * see b/174768555#comment22
+ */
+#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x56
+#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x57
+#define USBC_PORT_C2_BB_RETIMER_I2C_ADDR 0x58
+#define USBC_PORT_C3_BB_RETIMER_I2C_ADDR 0x59
+
+/* Enabling Thunderbolt-compatible mode */
+#define CONFIG_USB_PD_TBT_COMPAT_MODE
+
+/* Enabling USB4 mode */
+#define CONFIG_USB_PD_USB4
+#define CONFIG_USB_PD_DATA_RESET_MSG
+
+/* Retimer */
+#define CONFIG_USBC_RETIMER_FW_UPDATE
+
+/* Thermal features */
+#define CONFIG_THERMISTOR
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_TEMP_SENSOR_POWER
+#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
+
+/* Fan features */
+#define CONFIG_FANS FAN_CH_COUNT
+#define CONFIG_FAN_BYPASS_SLOW_RESPONSE
+#define CONFIG_CUSTOM_FAN_CONTROL
+#define RPM_DEVIATION 1
+
+/* Charger defines */
+#define CONFIG_CHARGER_ISL9241
+#define CONFIG_CHARGE_RAMP_SW
+#define CONFIG_CHARGER_SENSE_RESISTOR 5
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+
+/* Keyboard features */
+#define CONFIG_KEYBOARD_FACTORY_TEST
+#define CONFIG_KEYBOARD_REFRESH_ROW3
+
+#undef CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE
+#define CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE 3
+
+/*
+ * Older boards have a different ADC assignment.
+ */
+
+#define CONFIG_ADC_CHANNELS_RUNTIME_CONFIG
+#define CONFIG_POWER_SIGNAL_RUNTIME_CONFIG
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h" /* needed by registers.h */
+#include "registers.h"
+#include "usbc_config.h"
+
+enum adc_channel {
+	ADC_TEMP_SENSOR_1_SOC,
+	ADC_TEMP_SENSOR_2_CHARGER,
+	ADC_TEMP_SENSOR_3_WWAN,
+	ADC_TEMP_SENSOR_4_DDR,
+	ADC_TEMP_SENSOR_5_REGULATOR,
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1_SOC,
+	TEMP_SENSOR_2_CHARGER,
+	TEMP_SENSOR_3_WWAN,
+	TEMP_SENSOR_4_DDR,
+	TEMP_SENSOR_5_REGULATOR,
+	TEMP_SENSOR_COUNT
+};
+
+enum sensor_id { CLEAR_ALS = 0, RGB_ALS, SENSOR_COUNT };
+
+enum ioex_port {
+	IOEX_C0_NCT38XX = 0,
+	IOEX_C1_NCT38XX,
+	IOEX_C2_NCT38XX,
+	IOEX_C3_NCT38XX,
+	IOEX_PORT_COUNT
+};
+
+enum battery_type {
+	BATTERY_SIMPLO_COS,
+	BATTERY_SIMPLO_COS2,
+	BATTERY_TYPE_COUNT
+};
+
+enum pwm_channel {
+	PWM_CH_KBLIGHT = 0, /* PWM3 */
+	PWM_CH_FAN, /* PWM5 */
+	PWM_CH_COUNT
+};
+
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT };
+
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT };
+
+#ifdef CONFIG_KEYBOARD_FACTORY_TEST
+extern const int keyboard_factory_scan_pins[][2];
+extern const int keyboard_factory_scan_pins_used;
+#endif
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/vell/build.mk b/board/vell/build.mk
new file mode 100644
index 0000000000..cad0da2a4e
--- /dev/null
+++ b/board/vell/build.mk
@@ -0,0 +1,26 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Brya board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx9
+CHIP_VARIANT:=npcx9m3f
+BASEBOARD:=brya
+
+board-y=
+board-y+=battery.o
+board-y+=board.o
+board-y+=charger.o
+board-y+=fans.o
+board-y+=fw_config.o
+board-y+=i2c.o
+board-y+=keyboard.o
+board-y+=led.o
+board-y+=pwm.o
+board-y+=sensors.o
+board-y+=thermal.o
+board-y+=usbc_config.o
diff --git a/board/vell/charger.c b/board/vell/charger.c
new file mode 100644
index 0000000000..59d8812993
--- /dev/null
+++ b/board/vell/charger.c
@@ -0,0 +1,94 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/charger/isl9241.h"
+#include "hooks.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/* Charger Chip Configuration */
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = ISL9241_ADDR_FLAGS,
+		.drv = &isl9241_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CHARGER_NUM);
+
+int board_set_active_charge_port(int port)
+{
+	int is_valid_port = board_is_usb_pd_port_present(port);
+	int i;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTSUSB("Disabling all charger ports");
+
+		/* Disable all ports. */
+		for (i = 0; i < ppc_cnt; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (ppc_vbus_sink_enable(i, 0))
+				CPRINTSUSB("Disabling C%d as sink failed.", i);
+		}
+
+		return EC_SUCCESS;
+	} else if (!is_valid_port) {
+		return EC_ERROR_INVAL;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (ppc_is_sourcing_vbus(port)) {
+		CPRINTFUSB("Skip enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTSUSB("New charge port: C%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < ppc_cnt; i++) {
+		if (i == port)
+			continue;
+
+		if (ppc_vbus_sink_enable(i, 0))
+			CPRINTSUSB("C%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTSUSB("C%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+static void set_ac_prochot(void)
+{
+	isl9241_set_ac_prochot(CHARGER_SOLO, PD_MAX_CURRENT_MA);
+}
+DECLARE_HOOK(HOOK_INIT, set_ac_prochot, HOOK_PRIO_DEFAULT);
+
+/* Set the DCPROCHOT base on battery over discharging current 10.5A */
+static void set_dc_prochot(void)
+{
+	isl9241_set_dc_prochot(CHARGER_SOLO, 10500);
+}
+DECLARE_HOOK(HOOK_INIT, set_dc_prochot, HOOK_PRIO_DEFAULT);
diff --git a/board/vell/ec.tasklist b/board/vell/ec.tasklist
new file mode 100644
index 0000000000..0bae104a07
--- /dev/null
+++ b/board/vell/ec.tasklist
@@ -0,0 +1,35 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ *
+ * USB_CHG_Px tasks must be contiguous (see USB_CHG_PORT_TO_TASK_ID(x)).
+ * PD_Cx tasks must be contiguous (see PD_PORT_TO_TASK_ID(x))
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, HOOKS_TASK_STACK_SIZE) \
+	TASK_ALWAYS(LED, led_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, BASEBOARD_CHG_RAMP_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P2, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P3, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, BASEBOARD_CHARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, BASEBOARD_CHIPSET_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, CONSOLE_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, BASEBOARD_POWERBTN_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C2, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C3, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_shared_alert_task, (BIT(1) | BIT(0)), BASEBOARD_PD_INT_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_shared_alert_task, (BIT(3) | BIT(2)), BASEBOARD_PD_INT_TASK_STACK_SIZE)
diff --git a/board/vell/fans.c b/board/vell/fans.c
new file mode 100644
index 0000000000..050dc0cfa4
--- /dev/null
+++ b/board/vell/fans.c
@@ -0,0 +1,44 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Physical fans. These are logically separate from pwm_channels. */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "fan.h"
+#include "fan_chip.h"
+#include "hooks.h"
+#include "pwm.h"
+
+/* MFT channels. These are logically separate from pwm_channels. */
+const struct mft_t mft_channels[] = {
+	[MFT_CH_0] = {
+		.module = NPCX_MFT_MODULE_1,
+		.clk_src = TCKC_LFCLK,
+		.pwm_id = PWM_CH_FAN,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
+
+static const struct fan_conf fan_conf_0 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
+	.pgood_gpio = -1,
+	.enable_gpio = GPIO_EN_PP5000_FAN,
+};
+
+static const struct fan_rpm fan_rpm_0 = {
+	.rpm_min = 2500,
+	.rpm_start = 2500,
+	.rpm_max = 6800,
+};
+
+const struct fan_t fans[FAN_CH_COUNT] = {
+	[FAN_CH_0] = {
+		.conf = &fan_conf_0,
+		.rpm = &fan_rpm_0,
+	},
+};
diff --git a/board/vell/fw_config.c b/board/vell/fw_config.c
new file mode 100644
index 0000000000..137c5c9f9a
--- /dev/null
+++ b/board/vell/fw_config.c
@@ -0,0 +1,33 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "fw_config.h"
+
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
+
+static union vell_cbi_fw_config fw_config;
+BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
+
+/*
+ * FW_CONFIG defaults for vell if the CBI.FW_CONFIG data is not
+ * initialized.
+ */
+static const union vell_cbi_fw_config fw_config_defaults = {};
+
+/****************************************************************************
+ * Vell FW_CONFIG access
+ */
+void board_init_fw_config(void)
+{
+	if (cbi_get_fw_config(&fw_config.raw_value)) {
+		CPRINTS("CBI: Read FW_CONFIG failed, using board defaults");
+		fw_config = fw_config_defaults;
+	}
+}
diff --git a/board/vell/fw_config.h b/board/vell/fw_config.h
new file mode 100644
index 0000000000..324057a8e9
--- /dev/null
+++ b/board/vell/fw_config.h
@@ -0,0 +1,27 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __BOARD_VELL_FW_CONFIG_H_
+#define __BOARD_VELL_FW_CONFIG_H_
+
+#include <stdint.h>
+
+/****************************************************************************
+ * CBI FW_CONFIG layout for Vell board.
+ *
+ * Source of truth is the project/brya/vell/config.star configuration file.
+ */
+union vell_cbi_fw_config {
+	struct {
+		uint32_t lte_db : 1;
+		uint32_t kb_color : 1;
+		uint32_t storage_nand : 1;
+		uint32_t wifi_sar_id : 2;
+		uint32_t reserved_1 : 27;
+	};
+	uint32_t raw_value;
+};
+
+#endif /* __BOARD_VELL_FW_CONFIG_H_ */
diff --git a/board/vell/gpio.inc b/board/vell/gpio.inc
new file mode 100644
index 0000000000..0bd8065ab4
--- /dev/null
+++ b/board/vell/gpio.inc
@@ -0,0 +1,164 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define MODULE_KB		MODULE_KEYBOARD_SCAN
+
+/* INTERRUPT GPIOs: */
+GPIO_INT(ACOK_OD,                        PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
+GPIO_INT(EC_ALS_RGB_INT_R_L,             PIN(D, 4), GPIO_INT_FALLING, tcs3400_interrupt)
+GPIO_INT(EC_PROCHOT_IN_L,                PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
+GPIO_INT(EC_WP_ODL,                      PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(GSC_EC_PWR_BTN_ODL,             PIN(0, 1), GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW, power_button_interrupt)
+GPIO_INT(LID_OPEN,                       PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
+GPIO_INT(SEQ_EC_ALL_SYS_PG,              PIN(9, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_DSW_PWROK,               PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_RSMRST_ODL,              PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,                       PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,                      PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SYS_SLP_S0IX_L,                 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(USB_C0_BC12_INT_ODL,            PIN(C, 6), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C0_C1_TCPC_INT_ODL,         PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C0_PPC_INT_ODL,             PIN(6, 2), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C0_RT_INT_ODL,              PIN(B, 1), GPIO_INT_FALLING, retimer_interrupt)
+GPIO_INT(USB_C1_BC12_INT_ODL,            PIN(5, 0), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C1_PPC_INT_ODL,             PIN(9, 5), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C1_RT_INT_ODL,              PIN(A, 0), GPIO_INT_FALLING, retimer_interrupt)
+GPIO_INT(USB_C2_BC12_INT_ODL,            PIN(8, 3), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C2_C3_TCPC_INT_ODL,         PIN(A, 2), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C2_PPC_INT_ODL,             PIN(7, 0), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C2_RT_INT_ODL,              PIN(9, 4), GPIO_INT_FALLING, retimer_interrupt)
+GPIO_INT(USB_C3_BC12_INT_ODL,            PIN(5, 6), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C3_PPC_INT_ODL,             PIN(8, 1), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C3_RT_INT_ODL,              PIN(9, 3), GPIO_INT_FALLING, retimer_interrupt)
+
+/* USED GPIOs: */
+GPIO(CCD_MODE_ODL,                   PIN(E, 5), GPIO_INPUT)
+GPIO(CHARGER_VAP_OTG_EN,             PIN(7, 3), GPIO_OUT_LOW)
+GPIO(CPU_C10_GATE_L,                 PIN(6, 7), GPIO_INPUT)
+GPIO(EC_BATT_PRES_ODL,               PIN(A, 3), GPIO_INPUT)
+GPIO(EC_ENTERING_RW,                 PIN(0, 3), GPIO_OUT_LOW)
+GPIO(EC_EN_EDP_BL,                   PIN(D, 3), GPIO_OUT_HIGH)
+GPIO(EC_GSC_PACKET_MODE,             PIN(7, 5), GPIO_OUT_LOW)
+GPIO(EC_I2C_BAT_SCL,                 PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_BAT_SDA,                 PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SCL_R,              PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SDA_R,              PIN(B, 2), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,              PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SENSOR_SDA,              PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_USB_C0_C1_PPC_BC_SCL,    PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C1_PPC_BC_SDA,    PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_RT_SCL,              PIN(D, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_RT_SDA,              PIN(D, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C1_TCPC_SCL,      PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C1_TCPC_SDA,      PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_USB_C2_C3_PPC_BC_RT_SCL, PIN(E, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C2_C3_PPC_BC_RT_SDA, PIN(E, 3), GPIO_INPUT)
+GPIO(EC_I2C_USB_C2_C3_TCPC_SCL,      PIN(F, 3), GPIO_INPUT)
+GPIO(EC_I2C_USB_C2_C3_TCPC_SDA,      PIN(F, 2), GPIO_INPUT)
+GPIO(EC_KB_BL_EN,                    PIN(8, 0), GPIO_OUT_LOW)
+GPIO(EC_PCHHOT_ODL,                  PIN(7, 4), GPIO_INPUT)
+GPIO(EC_PCH_INT_ODL,                 PIN(B, 0), GPIO_ODR_HIGH)
+GPIO(EC_PCH_PWR_BTN_ODL,             PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(EC_PCH_RSMRST_L,                PIN(A, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_RTCRST,                  PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_SYS_PWROK,               PIN(3, 7), GPIO_OUT_LOW)
+GPIO(EC_PCH_WAKE_R_ODL,              PIN(C, 0), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_ODL,                 PIN(6, 3), GPIO_ODR_HIGH)
+GPIO(EN_PP5000_FAN,                  PIN(6, 1), GPIO_OUT_HIGH)
+GPIO(EN_S5_RAILS,                    PIN(B, 6), GPIO_OUT_LOW)
+GPIO(IMVP9_VRRDY_OD,                 PIN(4, 3), GPIO_INPUT)
+GPIO(PCH_PWROK,                      PIN(7, 2), GPIO_OUT_LOW)
+GPIO(ID_5_SEQ_EC_ALL_SYS_PG,         PIN(D, 7), GPIO_INPUT)
+GPIO(SYS_RST_ODL,                    PIN(C, 5), GPIO_ODR_HIGH)
+GPIO(USB_C0_C1_TCPC_RST_ODL,         PIN(A, 7), GPIO_ODR_LOW)
+GPIO(USB_C2_C3_TCPC_RST_ODL,         PIN(9, 6), GPIO_ODR_LOW)
+GPIO(VCCST_PWRGD_OD,                 PIN(A, 4), GPIO_ODR_LOW)
+
+/* LED */
+GPIO(LED_1_L,                        PIN(C, 4), GPIO_OUT_LOW)
+GPIO(LED_2_L,                        PIN(C, 3), GPIO_OUT_LOW)
+GPIO(LED_3_L,                        PIN(C, 2), GPIO_OUT_LOW)
+GPIO(LED_4_L,                        PIN(6, 0), GPIO_OUT_LOW)
+
+/* UART alternate functions */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)              /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */
+
+/* I2C alternate functions */
+ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)               /* GPIO33/I2C5_SCL0/CTS_L, GPIO36/RTS_L/I2C5_SDA0 */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)               /* GPIO87/I2C1_SDA0 */
+ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)               /* GPIO92/I2C2_SCL0, GPIO91/I2C2_SDA0, GPIO90/I2C1_SCL0 */
+ALTERNATE(PIN_MASK(B, 0x0c), 0, MODULE_I2C, 0)               /* GPIOB3/I2C7_SCL0/DCD_L, GPIOB2/I2C7_SDA0/DSR_L */
+ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, GPIO_SEL_1P8V)   /* GPIOB5/I2C0_SCL0, GPIOB4/I2C0_SDA0 */
+ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)               /* GPIOD1/I2C3_SCL0, GPIOD0/I2C3_SDA0 */
+ALTERNATE(PIN_MASK(E, 0x18), 0, MODULE_I2C, 0)               /* GPIOE4/I2C6_SCL1/I3C_SCL, GPIOE3/I2C6_SDA1/I3C_SDA */
+ALTERNATE(PIN_MASK(F, 0x0c), 0, MODULE_I2C, 0)               /* GPIOF3/I2C4_SCL1, GPIOF2/I2C4_SDA1 */
+
+/* PWM alternate functions */
+ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0)               /* GPIO40/TA1 */
+ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)               /* GPIOB7/PWM5 */
+
+/* ADC alternate functions */
+ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0)               /* GPIO34/PS2_DAT2/ADC6 */
+ALTERNATE(PIN_MASK(4, 0x36), 0, MODULE_ADC, 0)               /* GPIO42/ADC3/RI_L, GPIO45/ADC0, GPIO44/ADC1, GPIO41/ADC4*/
+ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0)               /* GPIOE1/ADC7 */
+
+/* KB alternate functions */
+ALTERNATE(PIN_MASK(0, 0xf0), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO10&P80_CLK/GPIO07, KSO11&P80_DAT/GPIO06, KSO12/GPIO05, KSO13/GPIO04 */
+ALTERNATE(PIN_MASK(1, 0x7f), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO06/GPO13/GP_SEL_L, KSO07/GPO12/JEN_L, KSO03/GPIO16/JTAG_TDO0_SWO, KSO04/GPIO15/XNOR, KSO05/GPIO14, KSO08/GPIO11/CR_SOUT1, KSO09/GPIO10/CR_SIN1 */
+ALTERNATE(PIN_MASK(2, 0xfc), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI2/GPIO27/TRACEDATA1, KSI3/GPIO26/TRACEDATA0, KSI4/GPIO25/TRACECLK/GP_SCLK, KSI5/GPIO24/GP_MISO, KSI6/GPIO23/S_SBUB, KSI7/GPIO22/S_SBUA */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO00/GPIO21/JTAG_TCK_SWCLK, KSO01/GPIO20/JTAG_TMS_SWIO */
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI0/GPIO31/TRACEDATA3/GP_MOSI, KSI1/GPIO30/TRACEDATA2/GP_CS_L */
+ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO14/GPIO82 */
+
+/* PMU alternate functions */
+ALTERNATE(PIN_MASK(0, 0x01), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN2_L&GPI00/GPIO00 */
+ALTERNATE(PIN_MASK(0, 0x02), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW) /* GPIO01/PSL_IN3_L&GPI01 */
+ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN1_L&GPID2/GPIOD2 */
+
+/* Unused Pins */
+UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
+UNUSED(PIN(3, 2))       /* GPO32/TRIS_L */
+UNUSED(PIN(3, 5))       /* GPO35/CR_SOUT4/TEST_L */
+UNUSED(PIN(6, 6))       /* GPIO66 */
+UNUSED(PIN(5, 7))       /* GPIO57/SER_IRQ/ESPI_ALERT_L */
+UNUSED(PIN(F, 4))       /* GPIOF4/I2C5_SDA1 */
+UNUSED(PIN(F, 5))       /* GPIOF5/I2C5_SCL1 */
+UNUSED(PIN(8, 6))       /* GPO86/TXD/CR_SOUT2 */
+
+/* Pre-configured PSL balls:  J8  K6 */
+
+/*
+ * The NPCX keyboard driver does not use named GPIOs to access
+ * keyboard scan pins, so we do not list them in *gpio.inc. However, when
+ * KEYBOARD_COL2_INVERTED is defined, this name is required.
+ */
+GPIO(EC_KSO_02_INV,               PIN(1, 7), GPIO_OUT_LOW)
+
+/* IO expander configuration */
+/* GPIO02_P1 to PU */
+/* GPIO03_P1 to PU */
+IOEX(USB_C0_OC_ODL,          EXPIN(IOEX_C0_NCT38XX, 0, 4), GPIO_ODR_HIGH)
+IOEX(USB_C0_FRS_EN,          EXPIN(IOEX_C0_NCT38XX, 0, 6), GPIO_OUT_LOW)
+IOEX(USB_C0_RT_RST_ODL,      EXPIN(IOEX_C0_NCT38XX, 0, 7), GPIO_ODR_LOW)
+
+IOEX(USB_C1_RT_RST_ODL,      EXPIN(IOEX_C1_NCT38XX, 0, 2), GPIO_ODR_LOW)
+/* GPIO03_P2 to PU */
+IOEX(USB_C1_OC_ODL,          EXPIN(IOEX_C1_NCT38XX, 0, 4), GPIO_ODR_HIGH)
+IOEX(USB_C1_FRS_EN,          EXPIN(IOEX_C1_NCT38XX, 0, 6), GPIO_OUT_LOW)
+/* GPIO07_P2 to PU */
+
+/* GPIO02_P1 to PU */
+/* GPIO03_P1 to PU */
+IOEX(USB_C2_OC_ODL,          EXPIN(IOEX_C2_NCT38XX, 0, 4), GPIO_ODR_HIGH)
+IOEX(USB_C2_FRS_EN,          EXPIN(IOEX_C2_NCT38XX, 0, 6), GPIO_OUT_LOW)
+IOEX(USB_C2_RT_RST_ODL,      EXPIN(IOEX_C2_NCT38XX, 0, 7), GPIO_ODR_LOW)
+
+IOEX(USB_C3_RT_RST_ODL,      EXPIN(IOEX_C3_NCT38XX, 0, 2), GPIO_ODR_LOW)
+/* GPIO03_P2 to PU */
+IOEX(USB_C3_OC_ODL,          EXPIN(IOEX_C3_NCT38XX, 0, 4), GPIO_ODR_HIGH)
+IOEX(USB_C3_FRS_EN,          EXPIN(IOEX_C3_NCT38XX, 0, 6), GPIO_OUT_LOW)
+/* GPIO07_P2 to PU */
diff --git a/board/vell/i2c.c b/board/vell/i2c.c
new file mode 100644
index 0000000000..822de9a0d1
--- /dev/null
+++ b/board/vell/i2c.c
@@ -0,0 +1,78 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "hooks.h"
+#include "i2c.h"
+
+/* I2C port map configuration */
+const struct i2c_port_t i2c_ports[] = {
+	{
+		/* I2C0 */
+		.name = "sensor",
+		.port = I2C_PORT_SENSOR,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_SENSOR_SCL,
+		.sda = GPIO_EC_I2C_SENSOR_SDA,
+	},
+	{
+		/* I2C1 */
+		.name = "tcpc0,1",
+		.port = I2C_PORT_USB_C0_C1_TCPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C1_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C1_TCPC_SDA,
+	},
+	{
+		/* I2C2 */
+		.name = "ppc0,1",
+		.port = I2C_PORT_USB_C0_C1_PPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C1_PPC_BC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C1_PPC_BC_SDA,
+	},
+	{
+		/* I2C3 */
+		.name = "retimer0,1,2,3",
+		.port = I2C_PORT_USB_C0_C1_MUX,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_RT_SCL,
+		.sda = GPIO_EC_I2C_USB_RT_SDA,
+	},
+	{
+		/* I2C4 */
+		.name = "tcpc2,3",
+		.port = I2C_PORT_USB_C2_C3_TCPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C2_C3_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C2_C3_TCPC_SDA,
+	},
+	{
+		/* I2C5 */
+		.name = "battery",
+		.port = I2C_PORT_BATTERY,
+		.kbps = 100,
+		.scl = GPIO_EC_I2C_BAT_SCL,
+		.sda = GPIO_EC_I2C_BAT_SDA,
+	},
+	{
+		/* I2C6 */
+		.name = "ppc2,3",
+		.port = I2C_PORT_USB_C2_C3_PPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C2_C3_PPC_BC_RT_SCL,
+		.sda = GPIO_EC_I2C_USB_C2_C3_PPC_BC_RT_SDA,
+	},
+	{
+		/* I2C7 */
+		.name = "eeprom",
+		.port = I2C_PORT_EEPROM,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_MISC_SCL_R,
+		.sda = GPIO_EC_I2C_MISC_SDA_R,
+	},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/board/vell/keyboard.c b/board/vell/keyboard.c
new file mode 100644
index 0000000000..f541f51e3b
--- /dev/null
+++ b/board/vell/keyboard.c
@@ -0,0 +1,69 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "ec_commands.h"
+#include "keyboard_scan.h"
+#include "timer.h"
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/* Increase from 50 us, because KSO_02 passes through the H1. */
+	.output_settle_us = 80,
+	/* Other values should be the same as the default configuration. */
+	.debounce_down_us = 9 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x1c, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
+		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
+	},
+};
+
+static const struct ec_response_keybd_config keybd1 = {
+	.num_top_row_keys = 13,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_KBD_BKLIGHT_TOGGLE,	/* T8 */
+		TK_PLAY_PAUSE,		/* T9 */
+		TK_MICMUTE,		/* T10 */
+		TK_VOL_MUTE,		/* T11 */
+		TK_VOL_DOWN,		/* T12 */
+		TK_VOL_UP,		/* T13 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &keybd1;
+}
+
+#ifdef CONFIG_KEYBOARD_FACTORY_TEST
+/*
+ * Map keyboard connector pins to EC GPIO pins for factory test.
+ * Pins mapped to {-1, -1} are skipped.
+ * The connector has 24 pins total, and there is no pin 0.
+ */
+const int keyboard_factory_scan_pins[][2] = {
+	{ -1, -1 }, { 0, 5 }, { 1, 1 },	  { 1, 0 },   { 0, 6 },
+	{ 0, 7 },   { 1, 4 }, { 1, 3 },	  { 1, 6 },   { 1, 7 },
+	{ 3, 1 },   { 2, 0 }, { 1, 5 },	  { 2, 6 },   { 2, 7 },
+	{ 2, 1 },   { 2, 4 }, { 2, 5 },	  { 1, 2 },   { 2, 3 },
+	{ 2, 2 },   { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 },
+};
+
+const int keyboard_factory_scan_pins_used =
+	ARRAY_SIZE(keyboard_factory_scan_pins);
+#endif
diff --git a/board/vell/led.c b/board/vell/led.c
new file mode 100644
index 0000000000..186a211744
--- /dev/null
+++ b/board/vell/led.c
@@ -0,0 +1,242 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power and battery LED control for Vell
+ */
+
+#include "battery.h"
+#include "cbi.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "led_common.h"
+#include "task.h"
+#include "util.h"
+
+#include <stdint.h>
+
+#define BATT_LOW_BCT 10
+
+#define LED_TICK_INTERVAL_MS (500 * MSEC)
+#define LED_CYCLE_TIME_MS (2000 * MSEC)
+#define LED_TICKS_PER_CYCLE (LED_CYCLE_TIME_MS / LED_TICK_INTERVAL_MS)
+#define LED_ON_TIME_MS (1000 * MSEC)
+#define LED_ON_TICKS (LED_ON_TIME_MS / LED_TICK_INTERVAL_MS)
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_LEFT_LED,
+					     EC_LED_ID_RIGHT_LED };
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+enum led_color {
+	LED_OFF = 0,
+	LED_AMBER,
+	LED_WHITE,
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
+};
+
+enum led_port { RIGHT_PORT = 0, LEFT_PORT };
+
+uint8_t bat_led_on;
+uint8_t bat_led_off;
+
+static void led_init(void)
+{
+	if (get_board_id() < 2) {
+		bat_led_on = 0;
+		bat_led_off = 1;
+	} else {
+		bat_led_on = 1;
+		bat_led_off = 0;
+	}
+}
+DECLARE_HOOK(HOOK_INIT, led_init, HOOK_PRIO_DEFAULT);
+
+static void led_set_color_battery(int port, enum led_color color)
+{
+	enum gpio_signal amber_led, white_led;
+
+	amber_led = (port == RIGHT_PORT ? GPIO_RIGHT_LED_AMBER_L :
+					  GPIO_LEFT_LED_AMBER_L);
+	white_led = (port == RIGHT_PORT ? GPIO_RIGHT_LED_WHITE_L :
+					  GPIO_LEFT_LED_WHITE_L);
+
+	switch (color) {
+	case LED_WHITE:
+		gpio_set_level(white_led, bat_led_on);
+		gpio_set_level(amber_led, bat_led_off);
+		break;
+	case LED_AMBER:
+		gpio_set_level(white_led, bat_led_off);
+		gpio_set_level(amber_led, bat_led_on);
+		break;
+	case LED_OFF:
+		gpio_set_level(white_led, bat_led_off);
+		gpio_set_level(amber_led, bat_led_off);
+		break;
+	default:
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	memset(brightness_range, '\0',
+	       sizeof(*brightness_range) * EC_LED_COLOR_COUNT);
+	switch (led_id) {
+	case EC_LED_ID_LEFT_LED:
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		break;
+	case EC_LED_ID_RIGHT_LED:
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		break;
+	default:
+		break;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	switch (led_id) {
+	case EC_LED_ID_LEFT_LED:
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_battery(LEFT_PORT, LED_WHITE);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(LEFT_PORT, LED_AMBER);
+		else
+			led_set_color_battery(LEFT_PORT, LED_OFF);
+		break;
+	case EC_LED_ID_RIGHT_LED:
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_battery(RIGHT_PORT, LED_WHITE);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(RIGHT_PORT, LED_AMBER);
+		else
+			led_set_color_battery(RIGHT_PORT, LED_OFF);
+		break;
+	default:
+		return EC_ERROR_PARAM1;
+	}
+
+	return EC_SUCCESS;
+}
+
+/*
+ * Set active charge port color to the parameter, turn off all others.
+ * If no port is active (-1), turn off all LEDs.
+ */
+static void set_active_port_color(enum led_color color)
+{
+	int usbc_port = charge_manager_get_active_charge_port();
+	int port = 0;
+
+	if ((usbc_port == USBC_PORT_C0) || (usbc_port == USBC_PORT_C1))
+		port = RIGHT_PORT;
+	else if ((usbc_port == USBC_PORT_C2) || (usbc_port == USBC_PORT_C3))
+		port = LEFT_PORT;
+
+	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
+		led_set_color_battery(RIGHT_PORT,
+				      (port == RIGHT_PORT) ? color : LED_OFF);
+	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
+		led_set_color_battery(LEFT_PORT,
+				      (port == LEFT_PORT) ? color : LED_OFF);
+}
+
+static void led_set_battery(void)
+{
+	static unsigned int battery_ticks;
+
+	battery_ticks++;
+
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
+		/* Always indicate when charging, even in suspend. */
+		set_active_port_color(LED_AMBER);
+		break;
+	case LED_PWRS_DISCHARGE:
+		/*
+		 * Blinking amber LEDs slowly if battery is lower 10
+		 * percentage.
+		 */
+		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
+			if (charge_get_percent() < BATT_LOW_BCT)
+				led_set_color_battery(
+					RIGHT_PORT,
+					(battery_ticks % LED_TICKS_PER_CYCLE <
+					 LED_ON_TICKS) ?
+						LED_AMBER :
+						LED_OFF);
+			else
+				led_set_color_battery(RIGHT_PORT, LED_OFF);
+		}
+
+		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) {
+			if (charge_get_percent() < BATT_LOW_BCT)
+				led_set_color_battery(
+					LEFT_PORT,
+					(battery_ticks % LED_TICKS_PER_CYCLE <
+					 LED_ON_TICKS) ?
+						LED_AMBER :
+						LED_OFF);
+			else
+				led_set_color_battery(LEFT_PORT, LED_OFF);
+		}
+		break;
+	case LED_PWRS_ERROR:
+		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
+			led_set_color_battery(
+				RIGHT_PORT,
+				(battery_ticks & 0x1) ? LED_AMBER : LED_OFF);
+		}
+
+		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) {
+			led_set_color_battery(LEFT_PORT, (battery_ticks & 0x1) ?
+								 LED_AMBER :
+								 LED_OFF);
+		}
+		break;
+	case LED_PWRS_CHARGE_NEAR_FULL:
+		set_active_port_color(LED_WHITE);
+		break;
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		set_active_port_color(LED_WHITE);
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		set_active_port_color(
+			(battery_ticks % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
+				LED_AMBER :
+				LED_OFF);
+		break;
+	default:
+		/* Other states don't alter LED behavior */
+		break;
+	}
+}
+
+void led_task(void *u)
+{
+	uint32_t start_time;
+	uint32_t task_duration;
+
+	while (1) {
+		start_time = get_time().le.lo;
+
+		led_set_battery();
+
+		/* Compute time for this iteration */
+		task_duration = get_time().le.lo - start_time;
+		/*
+		 * Compute wait time required to for next desired LED tick. If
+		 * the duration exceeds the tick time, then don't sleep.
+		 */
+		if (task_duration < LED_TICK_INTERVAL_MS)
+			usleep(LED_TICK_INTERVAL_MS - task_duration);
+	}
+}
diff --git a/board/vell/pwm.c b/board/vell/pwm.c
new file mode 100644
index 0000000000..fc81baf455
--- /dev/null
+++ b/board/vell/pwm.c
@@ -0,0 +1,40 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "hooks.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_KBLIGHT] = {
+		.channel = 3,
+		.flags = 0,
+		/*
+		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
+		 * flicker. Higher frequencies consume similar average power to
+		 * lower PWM frequencies, but higher frequencies record a much
+		 * lower maximum power.
+		 */
+		.freq = 2400,
+	},
+	[PWM_CH_FAN] = {
+		.channel = 5,
+		.flags = PWM_CONFIG_OPEN_DRAIN,
+		.freq = 25000,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+static void board_pwm_init(void)
+{
+	/*
+	 * Turn on all the LED at 50%.
+	 */
+	pwm_enable(PWM_CH_KBLIGHT, 1);
+	pwm_set_duty(PWM_CH_KBLIGHT, 50);
+}
+DECLARE_HOOK(HOOK_INIT, board_pwm_init, HOOK_PRIO_DEFAULT);
diff --git a/board/vell/sensors.c b/board/vell/sensors.c
new file mode 100644
index 0000000000..e57598ccbf
--- /dev/null
+++ b/board/vell/sensors.c
@@ -0,0 +1,297 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "accelgyro.h"
+#include "adc.h"
+#include "common.h"
+#include "driver/als_tcs3400_public.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "motion_sense.h"
+#include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
+#include "thermal.h"
+
+/* ADC configuration */
+struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_1_SOC] = {
+		.name = "TEMP_SOC",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_2_CHARGER] = {
+		.name = "TEMP_CHARGER",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_3_WWAN] = {
+		.name = "TEMP_WWAN",
+		.input_ch = NPCX_ADC_CH6,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_4_DDR] = {
+		.name = "TEMP_DDR",
+		.input_ch = NPCX_ADC_CH7,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_5_REGULATOR] = {
+		.name = "TEMP_REGULATOR",
+		.input_ch = NPCX_ADC_CH4,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* TCS3400 private data */
+static struct als_drv_data_t g_tcs3400_data = {
+	.als_cal.scale = 1,
+	.als_cal.uscale = 0,
+	.als_cal.offset = 0,
+	.als_cal.channel_scale = {
+		.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kc from VPD */
+		.cover_scale = ALS_CHANNEL_SCALE(0.23),     /* CT */
+	},
+};
+
+/*
+ * TODO: b/184702900 need to calibrate ALS/RGB sensor. At default settings,
+ * shining phone flashlight on sensor pegs all readings at 0xFFFF.
+ */
+static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
+	.calibration.rgb_cal[X] = {
+		.offset = 448, /* 447.5509362 */
+		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(-0.45511034),
+		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(-0.21956361),
+		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0.32628044),
+		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0.3610898),
+		.scale = {
+			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kr */
+			.cover_scale = ALS_CHANNEL_SCALE(0.08)
+		}
+	},
+	.calibration.rgb_cal[Y] = {
+		.offset = 436, /* 435.9025807*/
+		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(-0.50765776),
+		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(-0.34142269),
+		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0.55352908),
+		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0.35923454),
+		.scale = {
+			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kg */
+			.cover_scale = ALS_CHANNEL_SCALE(1.0)
+		},
+	},
+	.calibration.rgb_cal[Z] = {
+		.offset = 287, /* 286.51472391*/
+		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(-0.11635731),
+		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(-0.76700456),
+		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(1.36663521),
+		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0.18494607),
+		.scale = {
+			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kb */
+			.cover_scale = ALS_CHANNEL_SCALE(0.54)
+		}
+	},
+	.calibration.irt = FLOAT_TO_FP(0.06),
+	.saturation.again = TCS_DEFAULT_AGAIN,
+	.saturation.atime = TCS_DEFAULT_ATIME,
+};
+
+struct motion_sensor_t motion_sensors[] = {
+	[CLEAR_ALS] = {
+		.name = "Clear Light",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_TCS3400,
+		.type = MOTIONSENSE_TYPE_LIGHT,
+		.location = MOTIONSENSE_LOC_CAMERA,
+		.drv = &tcs3400_drv,
+		.drv_data = &g_tcs3400_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = TCS3400_I2C_ADDR_FLAGS,
+		.rot_standard_ref = NULL,
+		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
+		.min_frequency = TCS3400_LIGHT_MIN_FREQ,
+		.max_frequency = TCS3400_LIGHT_MAX_FREQ,
+		.config = {
+			/* Run ALS sensor in S0 */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 1000,
+			},
+		},
+	},
+
+	[RGB_ALS] = {
+		/*
+		 * RGB channels read by CLEAR_ALS and so the i2c port and
+		 * address do not need to be defined for RGB_ALS.
+		 */
+		.name = "RGB Light",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_TCS3400,
+		.type = MOTIONSENSE_TYPE_LIGHT_RGB,
+		.location = MOTIONSENSE_LOC_CAMERA,
+		.drv = &tcs3400_rgb_drv,
+		.drv_data = &g_tcs3400_rgb_data,
+		.rot_standard_ref = NULL,
+		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
+	},
+};
+const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+/* ALS instances when LPC mapping is needed. Each entry directs to a sensor. */
+const struct motion_sensor_t *motion_als_sensors[] = {
+	&motion_sensors[CLEAR_ALS],
+};
+BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
+
+static void baseboard_sensors_init(void)
+{
+	/* Enable interrupt for the TCS3400 color light sensor */
+	gpio_enable_interrupt(GPIO_EC_ALS_RGB_INT_R_L);
+}
+DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_INIT_I2C + 1);
+
+/* Temperature sensor configuration */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1_SOC] = {
+		.name = "SOC",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_1_SOC,
+	},
+	[TEMP_SENSOR_2_CHARGER] = {
+		.name = "Charger",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_2_CHARGER,
+	},
+	[TEMP_SENSOR_3_WWAN] = {
+		.name = "WWAN",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_3_WWAN,
+	},
+	[TEMP_SENSOR_4_DDR] = {
+		.name = "DDR",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_4_DDR,
+	},
+	[TEMP_SENSOR_5_REGULATOR] = {
+		.name = "Regulator",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_5_REGULATOR,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/*
+ * TODO(b/203839956): update for Alder Lake/vell
+ *
+ * Alder Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
+ * 130 C.  However, sensor is located next to DDR, so we need to use the lower
+ * DDR temperature limit (85 C)
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(90), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(95), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(85), \
+		}, \
+	}
+
+/*
+ * TODO(b/203839956): update for Alder Lake/vell
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CHARGER          \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(90), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(95), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(85), \
+		}, \
+	}
+
+/*
+ * TODO(b/203839956): update for vell WWAN module
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_WWAN             \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+		}, \
+	}
+
+/*
+ * TODO(b/203839956): update for Alder Lake/vell
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+
+#define THERMAL_DDR              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(80), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(85), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
+		}, \
+	}
+
+/*
+ * TODO(b/203839956): update for Alder Lake/vell
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+
+#define THERMAL_REGULATOR        \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(80), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(85), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
+		}, \
+	}
+
+struct ec_thermal_config thermal_params[] = {
+	[TEMP_SENSOR_1_SOC] = THERMAL_CPU,
+	[TEMP_SENSOR_2_CHARGER] = THERMAL_CHARGER,
+	[TEMP_SENSOR_3_WWAN] = THERMAL_WWAN,
+	[TEMP_SENSOR_4_DDR] = THERMAL_DDR,
+	[TEMP_SENSOR_5_REGULATOR] = THERMAL_REGULATOR,
+};
diff --git a/board/vell/thermal.c b/board/vell/thermal.c
new file mode 100644
index 0000000000..045bcb92fa
--- /dev/null
+++ b/board/vell/thermal.c
@@ -0,0 +1,134 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "fan.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "temp_sensor.h"
+#include "thermal.h"
+#include "util.h"
+
+/* Console output macros */
+#define CPUTS(outstr) cputs(CC_THERMAL, outstr)
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
+
+struct fan_step {
+	/*
+	 * Sensor 1~5 trigger point, set -1 if we're not using this
+	 * sensor to determine fan speed.
+	 */
+	int8_t on[TEMP_SENSOR_COUNT];
+
+	/*
+	 * Sensor 1~5 trigger point, set -1 if we're not using this
+	 * sensor to determine fan speed.
+	 */
+	int8_t off[TEMP_SENSOR_COUNT];
+
+	/* Fan 1~2 rpm */
+	uint16_t rpm[FAN_CH_COUNT];
+};
+
+static const struct fan_step fan_table[] = {
+	{
+		/* level 0 */
+		.on = { 47, 62, 48, 50, -1 },
+		.off = { 99, 99, 99, 99, -1 },
+		.rpm = { 0 },
+	},
+	{
+		/* level 1 */
+		.on = { 49, 62, 50, 52, -1 },
+		.off = { 46, 99, 47, 49, -1 },
+		.rpm = { 3100 },
+	},
+	{
+		/* level 2 */
+		.on = { 51, 62, 53, 54, -1 },
+		.off = { 48, 99, 49, 51, -1 },
+		.rpm = { 3750 },
+	},
+	{
+		/* level 3 */
+		.on = { 100, 100, 100, 100, -1 },
+		.off = { 50, 60, 51, 52, -1 },
+		.rpm = { 5100 },
+	},
+};
+
+#define NUM_FAN_LEVELS ARRAY_SIZE(fan_table)
+
+static int fan_table_to_rpm(int fan, int *temp)
+{
+	static int current_level;
+	static int prev_tmp[TEMP_SENSOR_COUNT];
+	int i;
+
+	/*
+	 * Compare the current and previous temperature, we have
+	 * the three paths :
+	 *  1. decreasing path. (check the release point)
+	 *  2. increasing path. (check the trigger point)
+	 *  3. invariant path. (return the current RPM)
+	 */
+	if (temp[TEMP_SENSOR_1_SOC] < prev_tmp[TEMP_SENSOR_1_SOC] ||
+	    temp[TEMP_SENSOR_2_CHARGER] < prev_tmp[TEMP_SENSOR_2_CHARGER] ||
+	    temp[TEMP_SENSOR_3_WWAN] < prev_tmp[TEMP_SENSOR_3_WWAN] ||
+	    temp[TEMP_SENSOR_4_DDR] < prev_tmp[TEMP_SENSOR_4_DDR]) {
+		for (i = current_level; i > 0; i--) {
+			if (temp[TEMP_SENSOR_1_SOC] <
+				    fan_table[i].off[TEMP_SENSOR_1_SOC] &&
+			    temp[TEMP_SENSOR_2_CHARGER] <
+				    fan_table[i].off[TEMP_SENSOR_2_CHARGER] &&
+			    temp[TEMP_SENSOR_3_WWAN] <
+				    fan_table[i].off[TEMP_SENSOR_3_WWAN] &&
+			    temp[TEMP_SENSOR_4_DDR] <
+				    fan_table[i].off[TEMP_SENSOR_4_DDR])
+				current_level = i - 1;
+			else
+				break;
+		}
+	} else if (temp[TEMP_SENSOR_1_SOC] > prev_tmp[TEMP_SENSOR_1_SOC] ||
+		   temp[TEMP_SENSOR_2_CHARGER] >
+			   prev_tmp[TEMP_SENSOR_2_CHARGER] ||
+		   temp[TEMP_SENSOR_3_WWAN] > prev_tmp[TEMP_SENSOR_3_WWAN] ||
+		   temp[TEMP_SENSOR_4_DDR] > prev_tmp[TEMP_SENSOR_4_DDR]) {
+		for (i = current_level; i < NUM_FAN_LEVELS; i++) {
+			if (temp[TEMP_SENSOR_1_SOC] >
+				    fan_table[i].on[TEMP_SENSOR_1_SOC] ||
+			    (temp[TEMP_SENSOR_2_CHARGER] >
+				     fan_table[i].on[TEMP_SENSOR_2_CHARGER] &&
+			     temp[TEMP_SENSOR_3_WWAN] >
+				     fan_table[i].on[TEMP_SENSOR_3_WWAN]) ||
+			    temp[TEMP_SENSOR_4_DDR] >
+				    fan_table[i].on[TEMP_SENSOR_4_DDR])
+				current_level = i + 1;
+			else
+				break;
+		}
+	}
+
+	if (current_level < 0)
+		current_level = 0;
+
+	if (current_level >= NUM_FAN_LEVELS)
+		current_level = NUM_FAN_LEVELS - 1;
+
+	for (i = 0; i < TEMP_SENSOR_COUNT; ++i)
+		prev_tmp[i] = temp[i];
+
+	return fan_table[current_level].rpm[FAN_CH_0];
+}
+
+void board_override_fan_control(int fan, int *tmp)
+{
+	if (chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND)) {
+		fan_set_rpm_mode(FAN_CH(fan), 1);
+		fan_set_rpm_target(FAN_CH(fan), fan_table_to_rpm(fan, tmp));
+	}
+}
diff --git a/board/vell/usbc_config.c b/board/vell/usbc_config.c
new file mode 100644
index 0000000000..4290c40936
--- /dev/null
+++ b/board/vell/usbc_config.c
@@ -0,0 +1,481 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi.h"
+#include "charge_ramp.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/bc12/pi3usb9201_public.h"
+#include "driver/ppc/nx20p348x.h"
+#include "driver/ppc/syv682x_public.h"
+#include "driver/retimer/bb_retimer_public.h"
+#include "driver/tcpm/nct38xx.h"
+#include "driver/tcpm/tcpci.h"
+#include "ec_commands.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "ioexpander.h"
+#include "system.h"
+#include "task.h"
+#include "task_id.h"
+#include "timer.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+/* USBC TCPC configuration */
+const struct tcpc_config_t tcpc_config[] = {
+	[USBC_PORT_C0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0_C1_TCPC,
+			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+	},
+	[USBC_PORT_C1] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0_C1_TCPC,
+			.addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+	},
+	[USBC_PORT_C2] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C2_C3_TCPC,
+			.addr_flags = NCT38XX_I2C_ADDR1_4_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+	},
+	[USBC_PORT_C3] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C2_C3_TCPC,
+			.addr_flags = NCT38XX_I2C_ADDR2_4_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
+BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
+
+/* USBC PPC configuration */
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_C1_PPC,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.frs_en = IOEX_USB_C0_FRS_EN,
+		.drv = &syv682x_drv,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C0_C1_PPC,
+		.i2c_addr_flags = SYV682X_ADDR1_FLAGS,
+		.frs_en = IOEX_USB_C1_FRS_EN,
+		.drv = &syv682x_drv,
+	},
+	[USBC_PORT_C2] = {
+		.i2c_port = I2C_PORT_USB_C2_C3_PPC,
+		.i2c_addr_flags = SYV682X_ADDR2_FLAGS,
+		.frs_en = IOEX_USB_C2_FRS_EN,
+		.drv = &syv682x_drv,
+	},
+	[USBC_PORT_C3] = {
+		.i2c_port = I2C_PORT_USB_C2_C3_PPC,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.frs_en = IOEX_USB_C3_FRS_EN,
+		.drv = &syv682x_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
+
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+struct ppc_config_t ppc_chips_old_c3 = {
+	.i2c_port = I2C_PORT_USB_C2_C3_PPC,
+	.i2c_addr_flags = SYV682X_ADDR3_FLAGS,
+	.frs_en = IOEX_USB_C3_FRS_EN,
+	.drv = &syv682x_drv,
+};
+
+/* USBC mux configuration - Alder Lake includes internal mux */
+static const struct usb_mux_chain usbc0_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+static const struct usb_mux_chain usbc1_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+static const struct usb_mux_chain usbc2_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C2,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+static const struct usb_mux_chain usbc3_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C3,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+
+const struct usb_mux_chain usb_muxes[] = {
+	[USBC_PORT_C0] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C0_C1_MUX,
+			.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc0_tcss_usb_mux,
+	},
+	[USBC_PORT_C1] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C0_C1_MUX,
+			.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc1_tcss_usb_mux,
+	},
+	[USBC_PORT_C2] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C2,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C2_C3_MUX,
+			.i2c_addr_flags = USBC_PORT_C2_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc2_tcss_usb_mux,
+	},
+	[USBC_PORT_C3] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C3,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C2_C3_MUX,
+			.i2c_addr_flags = USBC_PORT_C3_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc3_tcss_usb_mux,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
+
+/* BC1.2 charger detect configuration */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_C1_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C0_C1_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_2_FLAGS,
+	},
+	[USBC_PORT_C2] = {
+		.i2c_port = I2C_PORT_USB_C2_C3_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_1_FLAGS,
+	},
+	[USBC_PORT_C3] = {
+		.i2c_port = I2C_PORT_USB_C2_C3_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_0_FLAGS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
+
+/*
+ * USB C0 and C2 uses burnside bridge chips and have their reset
+ * controlled by their respective TCPC chips acting as GPIO expanders.
+ *
+ * ioex_init() is normally called before we take the TCPCs out of
+ * reset, so we need to start in disabled mode, then explicitly
+ * call ioex_init().
+ */
+
+struct ioexpander_config_t ioex_config[] = {
+	[IOEX_C0_NCT38XX] = {
+		.i2c_host_port = I2C_PORT_USB_C0_C1_TCPC,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
+	},
+	[IOEX_C1_NCT38XX] = {
+		.i2c_host_port = I2C_PORT_USB_C0_C1_TCPC,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
+	},
+	[IOEX_C2_NCT38XX] = {
+		.i2c_host_port = I2C_PORT_USB_C2_C3_TCPC,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR1_4_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
+	},
+	[IOEX_C3_NCT38XX] = {
+		.i2c_host_port = I2C_PORT_USB_C2_C3_TCPC,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR2_4_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT);
+
+#ifdef CONFIG_CHARGE_RAMP_SW
+
+/*
+ * TODO(b/181508008): tune this threshold
+ */
+
+#define BC12_MIN_VOLTAGE 4400
+
+/**
+ * Return true if VBUS is too low
+ */
+int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
+{
+	int voltage;
+
+	if (charger_get_vbus_voltage(port, &voltage))
+		voltage = 0;
+
+	if (voltage == 0) {
+		CPRINTS("%s: must be disconnected", __func__);
+		return 1;
+	}
+
+	if (voltage < BC12_MIN_VOLTAGE) {
+		CPRINTS("%s: port %d: vbus %d lower than %d", __func__, port,
+			voltage, BC12_MIN_VOLTAGE);
+		return 1;
+	}
+
+	return 0;
+}
+
+#endif /* CONFIG_CHARGE_RAMP_SW */
+
+__override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
+{
+	enum ioex_signal rst_signal;
+
+	if (me->usb_port == USBC_PORT_C0)
+		rst_signal = IOEX_USB_C0_RT_RST_ODL;
+	else if (me->usb_port == USBC_PORT_C1)
+		rst_signal = IOEX_USB_C1_RT_RST_ODL;
+	else if (me->usb_port == USBC_PORT_C2)
+		rst_signal = IOEX_USB_C2_RT_RST_ODL;
+	else if (me->usb_port == USBC_PORT_C3)
+		rst_signal = IOEX_USB_C3_RT_RST_ODL;
+	else
+		return EC_ERROR_INVAL;
+
+	/*
+	 * We do not have a load switch for the burnside bridge chips,
+	 * so we only need to sequence reset.
+	 */
+
+	if (enable) {
+		/*
+		 * Tpw, minimum time from VCC to RESET_N de-assertion is 100us.
+		 * For boards that don't provide a load switch control, the
+		 * retimer_init() function ensures power is up before calling
+		 * this function.
+		 */
+		ioex_set_level(rst_signal, 1);
+		/*
+		 * Allow 1ms time for the retimer to power up lc_domain
+		 * which powers I2C controller within retimer
+		 */
+		msleep(1);
+	} else {
+		ioex_set_level(rst_signal, 0);
+		msleep(1);
+	}
+	return EC_SUCCESS;
+}
+
+void board_reset_pd_mcu(void)
+{
+	gpio_set_level(GPIO_USB_C0_C1_TCPC_RST_ODL, 0);
+	gpio_set_level(GPIO_USB_C2_C3_TCPC_RST_ODL, 0);
+
+	/*
+	 * delay for power-on to reset-off and min. assertion time
+	 */
+	msleep(NCT38XX_RESET_HOLD_DELAY_MS);
+
+	gpio_set_level(GPIO_USB_C0_C1_TCPC_RST_ODL, 1);
+	gpio_set_level(GPIO_USB_C2_C3_TCPC_RST_ODL, 1);
+
+	nct38xx_reset_notify(USBC_PORT_C0);
+	nct38xx_reset_notify(USBC_PORT_C1);
+	nct38xx_reset_notify(USBC_PORT_C2);
+	nct38xx_reset_notify(USBC_PORT_C3);
+
+	/* wait for chips to come up */
+	if (NCT3808_RESET_POST_DELAY_MS != 0)
+		msleep(NCT3808_RESET_POST_DELAY_MS);
+}
+
+static void board_tcpc_init(void)
+{
+	int i;
+
+	/* Don't reset TCPCs after initial reset */
+	if (!system_jumped_late())
+		board_reset_pd_mcu();
+
+	/*
+	 * These IO expander pins are implemented using the
+	 * C0/C1/C2/C3 TCPCs, so they must be set up after the TCPC
+	 * has been taken out of reset.
+	 */
+	for (i = 0; i < CONFIG_IO_EXPANDER_PORT_COUNT; ++i)
+		ioex_init(i);
+
+	if (get_board_id() < 2)
+		ppc_chips[USBC_PORT_C3] = ppc_chips_old_c3;
+
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C2_PPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C3_PPC_INT_ODL);
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_C1_TCPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C2_C3_TCPC_INT_ODL);
+
+	/* Enable BC1.2 interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C2_BC12_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C3_BC12_INT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (gpio_get_level(GPIO_USB_C0_C1_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_0 | PD_STATUS_TCPC_ALERT_1;
+
+	if (gpio_get_level(GPIO_USB_C2_C3_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_2 | PD_STATUS_TCPC_ALERT_3;
+
+	return status;
+}
+
+int ppc_get_alert_status(int port)
+{
+	if (port == USBC_PORT_C0)
+		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
+	else if (port == USBC_PORT_C1)
+		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
+	else if (port == USBC_PORT_C2)
+		return gpio_get_level(GPIO_USB_C2_PPC_INT_ODL) == 0;
+	else if (port == USBC_PORT_C3)
+		return gpio_get_level(GPIO_USB_C3_PPC_INT_ODL) == 0;
+	return 0;
+}
+
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_C1_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C2_C3_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C2);
+		break;
+	default:
+		break;
+	}
+}
+
+void bc12_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_BC12_INT_ODL:
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+		break;
+	case GPIO_USB_C1_BC12_INT_ODL:
+		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+		break;
+	case GPIO_USB_C2_BC12_INT_ODL:
+		usb_charger_task_set_event(2, USB_CHG_EVENT_BC12);
+		break;
+	case GPIO_USB_C3_BC12_INT_ODL:
+		usb_charger_task_set_event(3, USB_CHG_EVENT_BC12);
+		break;
+	default:
+		break;
+	}
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C1);
+		break;
+	case GPIO_USB_C2_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C2);
+		break;
+	case GPIO_USB_C3_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C3);
+		break;
+	default:
+		break;
+	}
+}
+
+void retimer_interrupt(enum gpio_signal signal)
+{
+	/*
+	 * TODO(b/179513527): add USB-C support
+	 */
+}
+
+__override bool board_is_dts_port(int port)
+{
+	return port == USBC_PORT_C0;
+}
diff --git a/board/vell/usbc_config.h b/board/vell/usbc_config.h
new file mode 100644
index 0000000000..694b316ee8
--- /dev/null
+++ b/board/vell/usbc_config.h
@@ -0,0 +1,21 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Vell board-specific USB-C configuration */
+
+#ifndef __CROS_EC_USBC_CONFIG_H
+#define __CROS_EC_USBC_CONFIG_H
+
+#define CONFIG_USB_PD_PORT_MAX_COUNT 4
+
+enum usbc_port {
+	USBC_PORT_C0 = 0,
+	USBC_PORT_C1,
+	USBC_PORT_C2,
+	USBC_PORT_C3,
+	USBC_PORT_COUNT
+};
+
+#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/vell/vif_override.xml b/board/vell/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/vell/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/vilboz/battery.c b/board/vilboz/battery.c
index c9bbf70a86..a119ce38e8 100644
--- a/board/vilboz/battery.c
+++ b/board/vilboz/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -6,7 +6,11 @@
  */
 
 #include "battery_fuel_gauge.h"
+#include "battery_smart.h"
+#include "charge_state.h"
 #include "common.h"
+#include "temp_sensor.h"
+#include "thermal.h"
 #include "util.h"
 
 /*
@@ -125,6 +129,37 @@ const struct board_batt_params board_battery_info[] = {
 		},
 	},
 
+	/* SMP L20M3PG3 47W
+	 * Gauge IC: Renesas RAJ240047
+	 */
+	[BATTERY_SMP_3] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP",
+			.device_name = "L20M3PG3",
+			.ship_mode = {
+				.reg_addr = 0x34,
+				.reg_data = { 0x0000, 0x1000 },
+			},
+			.fet = {
+				.reg_addr = 0x0,
+				.reg_mask = 0x0010,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max            = 13200, /* mV */
+			.voltage_normal         = 11520, /* mV */
+			.voltage_min            = 9000,  /* mV */
+			.precharge_current      = 256,   /* mA */
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 50,
+			.charging_min_c         = 0,
+			.charging_max_c         = 60,
+			.discharging_min_c      = -20,
+			.discharging_max_c      = 70,
+		},
+	},
+
 	/* LGC  L19L3PG1 */
 	[BATTERY_LGC] = {
 		.fuel_gauge = {
@@ -344,3 +379,79 @@ const struct board_batt_params board_battery_info[] = {
 BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
 
 const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SMP;
+
+struct chg_curr_step {
+	int on;
+	int off;
+	int curr_ma;
+};
+
+static const struct chg_curr_step chg_curr_table[] = {
+	{ .on = 0, .off = 35, .curr_ma = 2800 },
+	{ .on = 36, .off = 35, .curr_ma = 1500 },
+	{ .on = 39, .off = 38, .curr_ma = 1000 },
+};
+
+/* All charge current tables must have the same number of levels */
+#define NUM_CHG_CURRENT_LEVELS ARRAY_SIZE(chg_curr_table)
+
+int charger_profile_override(struct charge_state_data *curr)
+{
+	int rv;
+	int chg_temp_c;
+	int current;
+	int thermal_sensor0;
+	static int current_level;
+	static int prev_tmp;
+
+	/*
+	 * Precharge must be executed when communication is failed on
+	 * dead battery.
+	 */
+	if (!(curr->batt.flags & BATT_FLAG_RESPONSIVE))
+		return 0;
+
+	current = curr->requested_current;
+
+	rv = temp_sensor_read(TEMP_SENSOR_CHARGER, &thermal_sensor0);
+	chg_temp_c = K_TO_C(thermal_sensor0);
+
+	if (rv != EC_SUCCESS)
+		return 0;
+
+	if (chipset_in_state(CHIPSET_STATE_ON)) {
+		if (chg_temp_c < prev_tmp) {
+			if (chg_temp_c <= chg_curr_table[current_level].off)
+				current_level = current_level - 1;
+		} else if (chg_temp_c > prev_tmp) {
+			if (chg_temp_c >= chg_curr_table[current_level + 1].on)
+				current_level = current_level + 1;
+		}
+		/*
+		 * Prevent level always minus 0 or over table steps.
+		 */
+		if (current_level < 0)
+			current_level = 0;
+		else if (current_level >= NUM_CHG_CURRENT_LEVELS)
+			current_level = NUM_CHG_CURRENT_LEVELS - 1;
+
+		prev_tmp = chg_temp_c;
+		current = chg_curr_table[current_level].curr_ma;
+
+		curr->requested_current = MIN(curr->requested_current, current);
+	}
+
+	return 0;
+}
+
+enum ec_status charger_profile_override_get_param(uint32_t param,
+						  uint32_t *value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+enum ec_status charger_profile_override_set_param(uint32_t param,
+						  uint32_t value)
+{
+	return EC_RES_INVALID_PARAM;
+}
diff --git a/board/vilboz/board.c b/board/vilboz/board.c
index 33cff6b0db..d759865fc7 100644
--- a/board/vilboz/board.c
+++ b/board/vilboz/board.c
@@ -1,16 +1,17 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "battery_smart.h"
 #include "button.h"
+#include "charge_state.h"
 #include "cros_board_info.h"
 #include "driver/accel_lis2dw12.h"
 #include "driver/accelgyro_lsm6dsm.h"
 #include "driver/bc12/pi3usb9201.h"
 #include "driver/ioexpander/pcal6408.h"
-#include "driver/ppc/aoz1380.h"
+#include "driver/ppc/aoz1380_public.h"
 #include "driver/tcpm/nct38xx.h"
 #include "driver/usb_mux/amd_fp5.h"
 #include "extpower.h"
@@ -28,12 +29,12 @@
 #include "tablet_mode.h"
 #include "task.h"
 #include "usb_charge.h"
-#include "usb_pd_tcpm.h"
 #include "usb_mux.h"
+#include "usb_pd_tcpm.h"
 #include "usbc_ppc.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* This I2C moved. Temporarily detect and support the V0 HW. */
 int I2C_PORT_BATTERY = I2C_PORT_BATTERY_V1;
@@ -43,10 +44,9 @@ void hdmi_hpd_interrupt(enum gpio_signal signal)
 	gpio_set_level(GPIO_DP1_HPD, gpio_get_level(signal));
 }
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
-#ifdef HAS_TASK_MOTIONSENSE
-
 /* Motion sensors */
 static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
@@ -56,17 +56,13 @@ static struct stprivate_data g_lis2dwl_data;
 static struct lsm6dsm_data g_lsm6dsm_data = LSM6DSM_DATA;
 
 /* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, FLOAT_TO_FP(-1), 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
 
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
 /* TODO(gcc >= 5.0) Remove the casts to const pointer at rot_standard_ref */
 struct motion_sensor_t motion_sensors[] = {
@@ -107,11 +103,9 @@ struct motion_sensor_t motion_sensors[] = {
 	 .mutex = &g_base_mutex,
 	 .drv_data = LSM6DSM_ST_DATA(g_lsm6dsm_data,
 			MOTIONSENSE_TYPE_ACCEL),
-	 .int_signal = GPIO_6AXIS_INT_L,
-	 .flags = MOTIONSENSE_FLAG_INT_SIGNAL,
 	 .port = I2C_PORT_SENSOR,
 	 .i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-	 .default_range = 4, /* g, enough for laptop */
+	 .default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
 	 .rot_standard_ref = &base_standard_ref,
 	 .min_frequency = LSM6DSM_ODR_MIN_VAL,
 	 .max_frequency = LSM6DSM_ODR_MAX_VAL,
@@ -139,8 +133,6 @@ struct motion_sensor_t motion_sensors[] = {
 	 .mutex = &g_base_mutex,
 	 .drv_data = LSM6DSM_ST_DATA(g_lsm6dsm_data,
 			MOTIONSENSE_TYPE_GYRO),
-	.int_signal = GPIO_6AXIS_INT_L,
-	.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
 	 .port = I2C_PORT_SENSOR,
 	 .i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
 	 .default_range = 1000 | ROUND_UP_FLAG, /* dps */
@@ -152,15 +144,17 @@ struct motion_sensor_t motion_sensors[] = {
 
 unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
-#endif /* HAS_TASK_MOTIONSENSE */
-
 /*
  * USB C0 port SBU mux use standalone FSUSB42UMX
  * chip and it need a board specific driver.
  * Overall, it will use chained mux framework.
  */
-static int fsusb42umx_set_mux(const struct usb_mux *me, mux_state_t mux_state)
+static int fsusb42umx_set_mux(const struct usb_mux *me, mux_state_t mux_state,
+			      bool *ack_required)
 {
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
 	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
 		ioex_set_level(IOEX_USB_C0_SBU_FLIP, 1);
 	else
@@ -183,18 +177,23 @@ const struct usb_mux_driver usbc0_sbu_mux_driver = {
  * Since FSUSB42UMX is not a i2c device, .i2c_port and
  * .i2c_addr_flags are not required here.
  */
-const struct usb_mux usbc0_sbu_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &usbc0_sbu_mux_driver,
+const struct usb_mux_chain usbc0_sbu_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &usbc0_sbu_mux_driver,
+		},
 };
 
-const struct usb_mux usb_muxes[] = {
+const struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.i2c_port = I2C_PORT_USB_AP_MUX,
-		.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
-		.driver = &amd_fp5_usb_mux_driver,
-		.next_mux = &usbc0_sbu_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.i2c_port = I2C_PORT_USB_AP_MUX,
+			.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
+			.driver = &amd_fp5_usb_mux_driver,
+		},
+		.next = &usbc0_sbu_mux,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
@@ -222,8 +221,7 @@ void ppc_interrupt(enum gpio_signal signal)
 
 int board_set_active_charge_port(int port)
 {
-	int is_valid_port = (port >= 0 &&
-			     port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	int i;
 
 	if (port == CHARGE_PORT_NONE) {
@@ -244,7 +242,6 @@ int board_set_active_charge_port(int port)
 		return EC_ERROR_INVAL;
 	}
 
-
 	/* Check if the port is sourcing VBUS. */
 	if (ppc_is_sourcing_vbus(port)) {
 		CPRINTFUSB("Skip enable C%d", port);
@@ -308,23 +305,28 @@ const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
 
-static void reset_pd_port(int port, enum gpio_signal reset_gpio_l,
-			  int hold_delay, int finish_delay)
+static void reset_nct38xx_port(int port)
 {
+	enum gpio_signal reset_gpio_l;
+
+	if (port == USBC_PORT_C0)
+		reset_gpio_l = GPIO_USB_C0_TCPC_RST_L;
+	else
+		/* Invalid port: do nothing */
+		return;
+
 	gpio_set_level(reset_gpio_l, 0);
-	msleep(hold_delay);
+	msleep(NCT38XX_RESET_HOLD_DELAY_MS);
 	gpio_set_level(reset_gpio_l, 1);
-	if (finish_delay)
-		msleep(finish_delay);
+	nct38xx_reset_notify(port);
+	if (NCT3807_RESET_POST_DELAY_MS != 0)
+		msleep(NCT3807_RESET_POST_DELAY_MS);
 }
 
 void board_reset_pd_mcu(void)
 {
 	/* Reset TCPC0 */
-	reset_pd_port(USBC_PORT_C0, GPIO_USB_C0_TCPC_RST_L,
-		      NCT38XX_RESET_HOLD_DELAY_MS,
-		      NCT38XX_RESET_POST_DELAY_MS);
-
+	reset_nct38xx_port(USBC_PORT_C0);
 }
 
 uint16_t tcpc_get_alert_status(void)
@@ -364,8 +366,7 @@ int board_pd_set_frs_enable(int port, int enable)
 
 	/* Use the TCPC to enable fast switch when FRS included */
 	if (port == USBC_PORT_C0) {
-		rv = ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN,
-				    !!enable);
+		rv = ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN, !!enable);
 	}
 
 	return rv;
@@ -375,7 +376,7 @@ void bc12_interrupt(enum gpio_signal signal)
 {
 	switch (signal) {
 	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
 		break;
 
 	default:
@@ -406,34 +407,87 @@ static void setup_fw_config(void)
 	} else {
 		motion_sensor_count = 0;
 		/* Device is clamshell only */
-		tablet_set_mode(0);
+		tablet_set_mode(0, TABLET_TRIGGER_LID);
 		/* Gyro is not present, don't allow line to float */
 		gpio_set_flags(GPIO_6AXIS_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
 	}
 }
 DECLARE_HOOK(HOOK_INIT, setup_fw_config, HOOK_PRIO_INIT_I2C + 2);
 
-static void wwan_lte_startup(void)
+static void lte_usb3_mux_init(void)
+{
+	/*
+	 * the USB_C1 port might be used for the LTE modem if it is not used
+	 * for type-C, we need to keep the superspeed mux in USB 3 position.
+	 */
+	if (ec_config_lte_present() == LTE_PRESENT) {
+		const struct usb_mux usb_c1 = {
+			.usb_port = 1 /* USBC_PORT_C1 */,
+			.i2c_port = I2C_PORT_USB_AP_MUX,
+			.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
+			.driver = &amd_fp5_usb_mux_driver,
+		};
+		bool unused;
+		/*
+		 * Note: Direct mux driver calls are deprecated.  Calls
+		 * should go through the usb_mux APIs instead.
+		 */
+		/* steer the mux to connect the USB 3 superspeed pairs */
+		usb_c1.driver->set(&usb_c1, USB_PD_MUX_USB_ENABLED, &unused);
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, lte_usb3_mux_init, HOOK_PRIO_DEFAULT);
+
+static void lte_function_resume(void)
+{
+	gpio_set_level(GPIO_LTE_FCPO, 1);
+}
+DECLARE_DEFERRED(lte_function_resume);
+
+static void lte_power_resume(void)
 {
-	/* Turn on WWAN LTE function as we go into S0 from S5. */
 	gpio_set_level(GPIO_LTE_EN, 1);
 	gpio_set_level(GPIO_LTE_W_DISABLE_L, 1);
 }
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, wwan_lte_startup, HOOK_PRIO_DEFAULT + 1);
+DECLARE_DEFERRED(lte_power_resume);
 
-static void wwan_lte_shutdown(void)
+static void lte_power_suspend(void)
 {
-	/* Turn off WWAN LTE function as we go back to S5. */
 	gpio_set_level(GPIO_LTE_EN, 0);
 	gpio_set_level(GPIO_LTE_W_DISABLE_L, 0);
 }
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, wwan_lte_shutdown, HOOK_PRIO_DEFAULT + 1);
+DECLARE_DEFERRED(lte_power_suspend);
 
+static void lte_function_suspend(void)
+{
+	gpio_set_level(GPIO_LTE_FCPO, 0);
+	hook_call_deferred(&lte_power_suspend_data, 100 * MSEC);
+}
+DECLARE_DEFERRED(lte_function_suspend);
+
+static void wwan_lte_resume_hook(void)
+{
+	/* Turn on WWAN LTE function as we go into S0 from S3/S5. */
+	hook_call_deferred(&lte_function_suspend_data, -1);
+	hook_call_deferred(&lte_power_suspend_data, -1);
+	lte_power_resume();
+	hook_call_deferred(&lte_function_resume_data, 10 * MSEC);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, wwan_lte_resume_hook, HOOK_PRIO_DEFAULT);
+
+static void wwan_lte_suspend_hook(void)
+{
+	/* Turn off WWAN LTE function as we go into S3/S5 from S0. */
+	hook_call_deferred(&lte_power_resume_data, -1);
+	hook_call_deferred(&lte_function_resume_data, -1);
+	hook_call_deferred(&lte_function_suspend_data, 20 * MSEC);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, wwan_lte_suspend_hook, HOOK_PRIO_DEFAULT);
 const struct pwm_t pwm_channels[] = {
 	[PWM_CH_KBLIGHT] = {
 		.channel = 3,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq = 100,
+		.flags = 0,
+		.freq = 15000,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
@@ -441,7 +495,7 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 struct ioexpander_config_t ioex_config[] = {
 	[IOEX_C0_NCT3807] = {
 		.i2c_host_port = I2C_PORT_TCPC0,
-		.i2c_slave_addr = NCT38XX_I2C_ADDR1_1_FLAGS,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
 		.drv = &nct38xx_ioexpander_drv,
 	},
 };
diff --git a/board/vilboz/board.h b/board/vilboz/board.h
index ff8fa06ae3..5bda55b8d3 100644
--- a/board/vilboz/board.h
+++ b/board/vilboz/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,10 +10,9 @@
 
 #define VARIANT_ZORK_DALBOZ
 
-#include <stdbool.h>
 #include "baseboard.h"
 
-#define CONFIG_MKBP_USE_GPIO
+#include <stdbool.h>
 
 #define CONFIG_USB_PD_PORT_MAX_COUNT 1
 
@@ -21,15 +20,15 @@
 #define GPIO_USB1_ILIM_SEL GPIO_USB_A0_CHARGE_EN_L
 #define GPIO_USB2_ILIM_SEL GPIO_USB_A1_CHARGE_EN_DB_L
 
-/* Power  LEDs */
-#define CONFIG_LED_POWER_LED
+#define CONFIG_CHARGER_PROFILE_OVERRIDE
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 5
 
 /* Motion sensing drivers */
 #define CONFIG_ACCELGYRO_LSM6DSM
 #define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 #define CONFIG_ACCEL_LIS2DWL
-#define CONFIG_ACCEL_INTERRUPTS
 #define CONFIG_CMD_ACCELS
 #define CONFIG_CMD_ACCEL_INFO
 #define CONFIG_TABLET_MODE
@@ -38,47 +37,49 @@
 #define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
 #define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
 
-
+/*
+ * Vilboz's battery takes ~3 seconds to come back out of its disconnect state,
+ * so give it a little more for margin.
+ */
+#undef CONFIG_POWER_BUTTON_INIT_TIMEOUT
+#define CONFIG_POWER_BUTTON_INIT_TIMEOUT 4
 
 /* GPIO mapping from board specific name to EC common name. */
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_EC_BATT_PRES_ODL
-#define CONFIG_SCI_GPIO			GPIO_EC_FCH_SCI_ODL
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_AP_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT_L		GPIO_EC_EDP_BL_DISABLE
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_FCH_PWR_BTN_L
-#define GPIO_PCH_RSMRST_L		GPIO_EC_FCH_RSMRST_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S5_L		GPIO_SLP_S5_L
-#define GPIO_PCH_SYS_PWROK		GPIO_EC_FCH_PWROK
-#define GPIO_PCH_WAKE_L			GPIO_EC_FCH_WAKE_L
-#define GPIO_POWER_BUTTON_L		GPIO_EC_PWR_BTN_ODL
-#define GPIO_S0_PGOOD			GPIO_S0_PWROK_OD
-#define GPIO_S5_PGOOD			GPIO_EC_PWROK_OD
-#define GPIO_SYS_RESET_L		GPIO_EC_SYS_RST_L
-#define GPIO_VOLUME_DOWN_L		GPIO_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
+#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL
+#define CONFIG_SCI_GPIO GPIO_EC_FCH_SCI_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_AP_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_EDP_BL_DISABLE
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PCH_PWRBTN_L GPIO_EC_FCH_PWR_BTN_L
+#define GPIO_PCH_RSMRST_L GPIO_EC_FCH_RSMRST_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L
+#define GPIO_PCH_SYS_PWROK GPIO_EC_FCH_PWROK
+#define GPIO_PCH_WAKE_L GPIO_EC_FCH_WAKE_L
+#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL
+#define GPIO_S0_PGOOD GPIO_S0_PWROK_OD
+#define GPIO_S5_PGOOD GPIO_EC_PWROK_OD
+#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L
+#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
 
 #ifndef __ASSEMBLER__
 
 /* This I2C moved. Temporarily detect and support the V0 HW. */
 extern int I2C_PORT_BATTERY;
 
-enum adc_channel {
-	ADC_TEMP_SENSOR_CHARGER,
-	ADC_TEMP_SENSOR_SOC,
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_TEMP_SENSOR_CHARGER, ADC_TEMP_SENSOR_SOC, ADC_CH_COUNT };
 
 enum battery_type {
 	BATTERY_SMP,
 	BATTERY_SMP_1,
 	BATTERY_SMP_2,
+	BATTERY_SMP_3,
 	BATTERY_LGC,
 	BATTERY_LGC_1,
 	BATTERY_LGC_2,
@@ -89,19 +90,11 @@ enum battery_type {
 	BATTERY_TYPE_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_COUNT };
 
-enum ioex_port {
-	IOEX_C0_NCT3807 = 0,
-	IOEX_PORT_COUNT
-};
+enum ioex_port { IOEX_C0_NCT3807 = 0, IOEX_PORT_COUNT };
 
-#define PORT_TO_HPD(port) ((port == 0) \
-	? GPIO_USB3_C0_DP2_HPD \
-	: GPIO_DP1_HPD)
+#define PORT_TO_HPD(port) ((port == 0) ? GPIO_USB3_C0_DP2_HPD : GPIO_DP1_HPD)
 
 enum temp_sensor_id {
 	TEMP_SENSOR_CHARGER = 0,
@@ -110,24 +103,16 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum usba_port {
-	USBA_PORT_A0 = 0,
-	USBA_PORT_A1,
-	USBA_PORT_COUNT
-};
+enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT };
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_COUNT };
 
 /*****************************************************************************
  * CBI EC FW Configuration
  */
-#include "cbi_ec_fw_config.h"
 
 /**
- * DALBOZ_MB_USBAC
+ * VILBOZ_MB_USBAC
  *	USB-A0  Speed: 5 Gbps
  *		Retimer: none
  *	USB-C0  Speed: 5 Gbps
@@ -137,62 +122,22 @@ enum usbc_port {
  *		IOEX: TCPC
  */
 enum ec_cfg_usb_mb_type {
-	DALBOZ_MB_USBAC = 0,
+	VILBOZ_MB_USBAC = 0,
 };
 
 /**
- * DALBOZ_DB_D_OPT1_USBAC
+ * VILBOZ_DB_D_OPT1_USBA_HDMI
  *	USB-A1  Speed: 5 Gbps
- *		Retimer: TUSB522
- *	USB-C1  Speed: 5 Gbps
- *		Retimer: PS8740
- *		TCPC: NCT3807
- *		PPC: NX20P3483
- *		IOEX: TCPC
- *	HDMI    Exists: no
- *		Retimer: none
- *		MST Hub: none
- *
- * DALBOZ_DB_D_OPT2_USBA_HDMI
- *	USB-A1  Speed: 5 Gbps
- *		Retimer: TUSB522
- *	USB-C1  none
- *		IOEX: PCAL6408
- *	HDMI    Exists: yes
- *		Retimer: PI3HDX1204
+ *		Retimer: None
+ *	HDMI    Retimer: PS8203
  *		MST Hub: none
+ *	P-Sensor SX9324
  */
 enum ec_cfg_usb_db_type {
-	DALBOZ_DB_D_OPT1_USBAC = 0,
-	DALBOZ_DB_D_OPT2_USBA_HDMI = 1,
+	VILBOZ_DB_D_OPT1_USBA_HDMI = 0,
 };
 
-#define HAS_USBC1 \
-			(BIT(DALBOZ_DB_D_OPT1_USBAC))
-
-static inline bool ec_config_has_usbc1(void)
-{
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_USBC1);
-}
-
-#define HAS_USBC1_RETIMER_PS8740 \
-			(BIT(DALBOZ_DB_D_OPT1_USBAC))
-
-static inline bool ec_config_has_usbc1_retimer_ps8740(void)
-{
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_USBC1_RETIMER_PS8740);
-}
-
-#define HAS_HDMI_RETIMER_PI3HDX1204 \
-			(BIT(DALBOZ_DB_D_OPT2_USBA_HDMI))
-
-static inline bool ec_config_has_hdmi_retimer_pi3hdx1204(void)
-{
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_HDMI_RETIMER_PI3HDX1204);
-}
+#include "cbi_ec_fw_config.h"
 
 void board_reset_pd_mcu(void);
 
diff --git a/board/vilboz/build.mk b/board/vilboz/build.mk
index 1c0cbc4f63..45c71f962c 100644
--- a/board/vilboz/build.mk
+++ b/board/vilboz/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/vilboz/ec.tasklist b/board/vilboz/ec.tasklist
index 08801d1786..864ca42492 100644
--- a/board/vilboz/ec.tasklist
+++ b/board/vilboz/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/vilboz/gpio.inc b/board/vilboz/gpio.inc
index 79ea48848f..6897f16890 100644
--- a/board/vilboz/gpio.inc
+++ b/board/vilboz/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -54,8 +54,9 @@ GPIO(LED_CHRG_L,		PIN(C, 0), GPIO_OUT_HIGH)
 GPIO(LED3_PWM,			PIN(C, 3), GPIO_OUT_HIGH)
 
 /* LTE control */
-GPIO(LTE_EN,            PIN(6, 2), GPIO_OUT_LOW)           /* WWAN LET Fuction enable */
-GPIO(LTE_W_DISABLE_L,   PIN(4, 0), GPIO_OUT_LOW)           /* WWAN LET flight mode */
+GPIO(LTE_EN,            PIN(6, 2), GPIO_OUT_LOW)           /* WWAN LTE Function enable */
+GPIO(LTE_W_DISABLE_L,   PIN(4, 0), GPIO_OUT_LOW)           /* WWAN LTE flight mode */
+GPIO(LTE_FCPO,          PIN(7, 3), GPIO_OUT_LOW)           /* WWAN LTE Full Card Power ON OFF */
 
 /*
  * Vilboz has only 1 HDMI DB option
diff --git a/board/vilboz/led.c b/board/vilboz/led.c
index 5b8d650936..fa28eb5f40 100644
--- a/board/vilboz/led.c
+++ b/board/vilboz/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,46 +8,53 @@
 #include "led_common.h"
 #include "led_onoff_states.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
-const int led_charge_lvl_1 = 5;
-const int led_charge_lvl_2 = 97;
+__override const int led_charge_lvl_1 = 5;
+__override const int led_charge_lvl_2 = 97;
 
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]       = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,  1 * LED_ONE_SEC},
-					{LED_OFF, 1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,  2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
 
 BUILD_ASSERT(ARRAY_SIZE(led_bat_state_table) == LED_NUM_STATES);
 
-const struct led_descriptor
-			led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-				{LED_OFF,          0.5 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 3 * LED_ONE_SEC },
+					       { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    3 * LED_ONE_SEC },
+						  { LED_OFF,
+						    0.5 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
 BUILD_ASSERT(ARRAY_SIZE(led_pwr_state_table) == PWR_LED_NUM_STATES);
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-void led_set_color_power(enum ec_led_colors color)
+__override void led_set_color_power(enum ec_led_colors color)
 {
 	if (color == EC_LED_COLOR_WHITE)
 		gpio_set_level(GPIO_LED3_PWM, LED_ON_LVL);
@@ -56,7 +63,7 @@ void led_set_color_power(enum ec_led_colors color)
 		gpio_set_level(GPIO_LED3_PWM, LED_OFF_LVL);
 }
 
-void led_set_color_battery(enum ec_led_colors color)
+__override void led_set_color_battery(enum ec_led_colors color)
 {
 	switch (color) {
 	case EC_LED_COLOR_GREEN:
diff --git a/board/vilboz/vif_override.xml b/board/vilboz/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/vilboz/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/voema/battery.c b/board/voema/battery.c
new file mode 100644
index 0000000000..dcd45d31fd
--- /dev/null
+++ b/board/voema/battery.c
@@ -0,0 +1,96 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "common.h"
+#include "util.h"
+
+/*
+ * Battery info for all Volteer battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	/* LGC\011 L17L3PB0 Battery Information */
+	/*
+	 * Battery info provided by ODM on b/143477210, comment #11
+	 */
+	[BATTERY_LGC011] = {
+		.fuel_gauge = {
+			.manuf_name = "LGC",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x10, 0x10 },
+			},
+			.fet = {
+				.reg_addr = 0x0,
+				.reg_mask = 0x6000,
+				.disconnect_val = 0x6000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= TARGET_WITH_MARGIN(13200, 5),
+			.voltage_normal		= 11550, /* mV */
+			.voltage_min		= 9000, /* mV */
+			.precharge_current	= 256,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 45,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= 0,
+			.discharging_max_c	= 75,
+		},
+	},
+	/* Panasonic AP1505L Battery Information */
+	[BATTERY_PANASONIC_AP15O5L] = {
+		.fuel_gauge = {
+			.manuf_name = "PANASONIC KT00305013",
+			.device_name = "AP15O5L",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.reg_addr = 0x0,
+				.reg_mask = 0x4000,
+				.disconnect_val = 0x0,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13200,
+			.voltage_normal		= 11550, /* mV */
+			.voltage_min		= 9000, /* mV */
+			.precharge_current	= 256,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 75,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_PANASONIC_AP15O5L;
diff --git a/board/voema/board.c b/board/voema/board.c
new file mode 100644
index 0000000000..beedb0d1b9
--- /dev/null
+++ b/board/voema/board.c
@@ -0,0 +1,449 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Volteer board-specific configuration */
+#include "accelgyro.h"
+#include "button.h"
+#include "cbi_ec_fw_config.h"
+#include "common.h"
+#include "driver/accel_bma2x2.h"
+#include "driver/accelgyro_bmi260.h"
+#include "driver/als_tcs3400.h"
+#include "driver/bc12/pi3usb9201.h"
+#include "driver/ppc/syv682x.h"
+#include "driver/sync.h"
+#include "driver/tcpm/ps8xxx.h"
+#include "driver/tcpm/rt1715.h"
+#include "driver/tcpm/tcpci.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "keyboard_raw.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "switch.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "throttle_ap.h"
+#include "uart.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tbt.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/* Increase from 50 us, because KSO_02 passes through the H1. */
+	.output_settle_us = 80,
+	/* Other values should be the same as the default configuration. */
+	.debounce_down_us = 9 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
+		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
+	},
+};
+
+static const struct ec_response_keybd_config voema_kb = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &voema_kb;
+}
+
+/*
+ * We have total 30 pins for keyboard connecter {-1, -1} mean
+ * the N/A pin that don't consider it and reserve index 0 area
+ * that we don't have pin 0.
+ */
+const int keyboard_factory_scan_pins[][2] = {
+	{ -1, -1 }, { 0, 5 },	{ 1, 1 }, { 1, 0 },   { 0, 6 },	  { 0, 7 },
+	{ -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 },   { -1, -1 }, { 1, 6 },
+	{ 1, 7 },   { 3, 1 },	{ 2, 0 }, { 1, 5 },   { 2, 6 },	  { 2, 7 },
+	{ 2, 1 },   { 2, 4 },	{ 2, 5 }, { 1, 2 },   { 2, 3 },	  { 2, 2 },
+	{ 3, 0 },   { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 },	  { -1, -1 },
+	{ -1, -1 },
+};
+const int keyboard_factory_scan_pins_used =
+	ARRAY_SIZE(keyboard_factory_scan_pins);
+
+/******************************************************************************/
+/*
+ * FW_CONFIG defaults for Volteer if the CBI data is not initialized.
+ */
+union volteer_cbi_fw_config fw_config_defaults = {
+	.usb_db = DB_USB3_ACTIVE,
+};
+
+static void board_init(void)
+{
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+/******************************************************************************/
+/* EC thermal management configuration */
+
+/*
+ * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
+ * 130 C.  However, sensor is located next to DDR, so we need to use the lower
+ * DDR temperature limit (85 C)
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
+
+/*
+ * Inductor limits - used for both charger and PP3300 regulator
+ *
+ * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
+ *
+ * Charger max recommended temperature 100C, max absolute temperature 125C
+ * PP3300 regulator: operating range -40 C to 145 C
+ *
+ * Inductors: limit of 125c
+ * PCB: limit is 80c
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_INDUCTOR         \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_inductor =
+	THERMAL_INDUCTOR;
+
+struct ec_thermal_config thermal_params[] = {
+	[TEMP_SENSOR_1_CHARGER] = THERMAL_INDUCTOR,
+	[TEMP_SENSOR_2_PP3300_REGULATOR] = THERMAL_INDUCTOR,
+	[TEMP_SENSOR_3_DDR_SOC] = THERMAL_CPU,
+	[TEMP_SENSOR_4_FAN] = THERMAL_CPU,
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
+
+/******************************************************************************/
+/* I2C port map configuration */
+const struct i2c_port_t i2c_ports[] = {
+	{
+		.name = "sensor",
+		.port = I2C_PORT_SENSOR,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C0_SENSOR_SCL,
+		.sda = GPIO_EC_I2C0_SENSOR_SDA,
+	},
+	{
+		.name = "usb_c0",
+		.port = I2C_PORT_USB_C0,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C1_USB_C0_SCL,
+		.sda = GPIO_EC_I2C1_USB_C0_SDA,
+	},
+	{
+		.name = "usb_c1",
+		.port = I2C_PORT_USB_C1,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C2_USB_C1_SCL,
+		.sda = GPIO_EC_I2C2_USB_C1_SDA,
+	},
+	{
+		.name = "power",
+		.port = I2C_PORT_POWER,
+		.kbps = 100,
+		.scl = GPIO_EC_I2C5_BATTERY_SCL,
+		.sda = GPIO_EC_I2C5_BATTERY_SDA,
+	},
+	{
+		.name = "eeprom",
+		.port = I2C_PORT_EEPROM,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C7_EEPROM_PWR_SCL_R,
+		.sda = GPIO_EC_I2C7_EEPROM_PWR_SDA_R,
+	},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+/******************************************************************************/
+/* PWM configuration */
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_KBLIGHT] = {
+		.channel = 3,
+		.flags = 0,
+		/*
+		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
+		 * flicker. Higher frequencies consume similar average power to
+		 * lower PWM frequencies, but higher frequencies record a much
+		 * lower maximum power.
+		 */
+		.freq = 2400,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+/******************************************************************************/
+/* USB-A charging control */
+
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_PP5000_USBA,
+};
+
+static void ps8815_reset(void)
+{
+	int val;
+
+	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 0);
+	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS));
+	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 1);
+	msleep(PS8815_FW_INIT_DELAY_MS);
+
+	/*
+	 * b/144397088
+	 * ps8815 firmware 0x01 needs special configuration
+	 */
+
+	CPRINTS("%s: patching ps8815 registers", __func__);
+
+	if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) ==
+	    EC_SUCCESS)
+		CPRINTS("ps8815: reg 0x0f was %02x", val);
+
+	if (i2c_write8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f,
+		       0x31) == EC_SUCCESS)
+		CPRINTS("ps8815: reg 0x0f set to 0x31");
+
+	if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) ==
+	    EC_SUCCESS)
+		CPRINTS("ps8815: reg 0x0f now %02x", val);
+}
+
+void board_reset_pd_mcu(void)
+{
+	/* No reset available for TCPC on port 0 */
+	/* Daughterboard specific reset for port 1 */
+	ps8815_reset();
+	usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+}
+
+__override void board_cbi_init(void)
+{
+	if ((!IS_ENABLED(TEST_BUILD) && !ec_cfg_has_numeric_pad()) ||
+	    get_board_id() <= 2)
+		keyboard_raw_set_cols(KEYBOARD_COLS_NO_KEYPAD);
+}
+
+/******************************************************************************/
+/* USBC PPC configuration */
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.frs_en = GPIO_USB_C0_FRS_EN,
+		.drv = &syv682x_drv,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C1,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.frs_en = GPIO_USB_C1_FRS_EN,
+		.drv = &syv682x_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/******************************************************************************/
+/* PPC support routines */
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C1);
+		break;
+	default:
+		break;
+	}
+}
+
+/******************************************************************************/
+/* BC1.2 charger detect configuration */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C1,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
+
+/******************************************************************************/
+/* USBC TCPC configuration */
+const struct tcpc_config_t tcpc_config[] = {
+	[USBC_PORT_C0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0,
+			.addr_flags = RT1715_I2C_ADDR_FLAGS,
+		},
+		.drv = &rt1715_tcpm_drv,
+	},
+	[USBC_PORT_C1] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C1,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V,
+		.drv = &ps8xxx_tcpm_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
+BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
+
+/*
+ * USB3 DB mux configuration - the top level mux still needs to be set to the
+ * virtual_usb_mux_driver so the AP gets notified of mux changes and updates
+ * the TCSS configuration on state changes.
+ */
+static const struct usb_mux_chain usbc1_usb3_db_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
+	.next = NULL,
+};
+
+/******************************************************************************/
+/* USBC mux configuration - Tiger Lake includes internal mux */
+const struct usb_mux_chain usb_muxes[] = {
+	[USBC_PORT_C0] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+	},
+	[USBC_PORT_C1] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc1_usb3_db_retimer,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
+
+static void board_tcpc_init(void)
+{
+	/* Don't reset TCPCs after initial reset */
+	if (!system_jumped_late())
+		board_reset_pd_mcu();
+
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
+
+	/* Enable BC1.2 interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
+
+/******************************************************************************/
+/* TCPC support routines */
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	/*
+	 * Check which port has the ALERT line set
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL))
+		status |= PD_STATUS_TCPC_ALERT_0;
+	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL))
+		status |= PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
+
+int ppc_get_alert_status(int port)
+{
+	if (port == USBC_PORT_C0)
+		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
+	else
+		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
+}
+
+static void kb_backlight_enable(void)
+{
+	gpio_set_level(GPIO_EC_KB_BL_EN, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, kb_backlight_enable, HOOK_PRIO_DEFAULT);
+
+static void kb_backlight_disable(void)
+{
+	gpio_set_level(GPIO_EC_KB_BL_EN, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, kb_backlight_disable, HOOK_PRIO_DEFAULT);
diff --git a/board/voema/board.h b/board/voema/board.h
new file mode 100644
index 0000000000..f10192b0b6
--- /dev/null
+++ b/board/voema/board.h
@@ -0,0 +1,182 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Volteer board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* Baseboard features */
+#include "baseboard.h"
+
+/*
+ * The RAM and flash size combination on the the NPCX797FC does not leave
+ * any unused flash space that can be used to store the .init_rom section.
+ */
+#undef CONFIG_CHIP_INIT_ROM_REGION
+
+#define CONFIG_VBOOT_EFS2
+
+#define CONFIG_POWER_BUTTON
+
+#undef CONFIG_UART_TX_BUF_SIZE
+#define CONFIG_UART_TX_BUF_SIZE 4096
+
+/* Chipset features */
+#define CONFIG_POWER_PP5000_CONTROL
+
+/* LED defines */
+#define CONFIG_LED_ONOFF_STATES
+
+/* Keyboard features */
+#define CONFIG_KEYBOARD_FACTORY_TEST
+#define CONFIG_KEYBOARD_VIVALDI
+#define CONFIG_KEYBOARD_REFRESH_ROW3
+
+/* Sensors */
+/* BMA253 accelerometer in base */
+#define CONFIG_ACCEL_BMA255
+#define CONFIG_ACCELGYRO_ICM426XX
+#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+#define CONFIG_ACCEL_KX022
+
+/* TCS3400 ALS */
+#define CONFIG_ALS
+#define ALS_COUNT 1
+#define CONFIG_ALS_TCS3400
+#define CONFIG_ALS_TCS3400_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS)
+
+/* Sensors without hardware FIFO are in forced mode */
+#define CONFIG_ACCEL_FORCE_MODE_MASK (board_accel_force_mode_mask())
+
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_UPDATE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+
+/* USB Type C and USB PD defines */
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+
+/* TODO: b/144165680 - measure and check these values on Volteer */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+
+/*
+ * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
+ * cables only support up to 60W.
+ */
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 65000
+#define PD_MAX_CURRENT_MA 3250
+#define PD_MAX_VOLTAGE_MV 20000
+
+/* Enabling Thunderbolt-compatible mode */
+#define CONFIG_USB_PD_TBT_COMPAT_MODE
+
+/* USB Type A Features */
+#define USB_PORT_COUNT 1
+#define CONFIG_USB_PORT_POWER_DUMB
+
+/* USBC PPC*/
+#undef CONFIG_SYV682X_HV_ILIM
+#define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_5_50
+#define CONFIG_USBC_PPC_SYV682X /* USBC port C0/C1 */
+#define CONFIG_USB_PD_FRS_PPC
+#undef CONFIG_USB_PD_TCPC_RUNTIME_CONFIG
+#undef CONFIG_USB_PD_TCPM_TUSB422
+#undef CONFIG_USB_MUX_RUNTIME_CONFIG
+
+/* BC 1.2 */
+
+/* Volume Button feature */
+
+/* Fan features */
+#undef CONFIG_FANS
+
+/* charger defines */
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+
+/* Retimer */
+#undef CONFIG_USBC_RETIMER_INTEL_BB
+#undef CONFIG_USBC_RETIMER_INTEL_BB_RUNTIME_CONFIG
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_LID_OPEN GPIO_EC_LID_OPEN
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
+
+/* I2C Bus Configuration */
+#define CONFIG_I2C
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT3_0
+#define I2C_PORT_POWER NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+
+#define I2C_PORT_BATTERY I2C_PORT_POWER
+#define I2C_PORT_CHARGER I2C_PORT_EEPROM
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+#define CONFIG_I2C_CONTROLLER
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum battery_type {
+	BATTERY_LGC011,
+	BATTERY_PANASONIC_AP15O5L,
+	BATTERY_TYPE_COUNT,
+};
+
+enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_COUNT };
+
+enum sensor_id {
+	LID_ACCEL = 0,
+	BASE_ACCEL,
+	BASE_GYRO,
+	CLEAR_ALS,
+	RGB_ALS,
+	SENSOR_COUNT,
+};
+
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
+
+void board_reset_pd_mcu(void);
+void motion_interrupt(enum gpio_signal signal);
+int board_accel_force_mode_mask(void);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/voema/build.mk b/board/voema/build.mk
new file mode 100644
index 0000000000..7d375fe291
--- /dev/null
+++ b/board/voema/build.mk
@@ -0,0 +1,18 @@
+# -*- makefile -*-
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx7
+CHIP_VARIANT:=npcx7m7fc
+
+BASEBOARD:=volteer
+
+board-y=board.o
+board-y+=battery.o
+board-y+=led.o
+board-y+=sensors.o
diff --git a/board/voema/ec.tasklist b/board/voema/ec.tasklist
new file mode 100644
index 0000000000..c29125d517
--- /dev/null
+++ b/board/voema/ec.tasklist
@@ -0,0 +1,27 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/voema/gpio.inc b/board/voema/gpio.inc
new file mode 100644
index 0000000000..e1a931094c
--- /dev/null
+++ b/board/voema/gpio.inc
@@ -0,0 +1,180 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+/* Wake Source interrupts */
+GPIO_INT(EC_LID_OPEN,          PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
+GPIO_INT(EC_WP_L,              PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(H1_EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
+GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
+
+/* Power sequencing interrupts */
+GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
+#endif
+GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_EC_RSMRST_ODL,     PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_EC_DSW_PWROK,      PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
+
+/* Sensor Interrupts */
+GPIO_INT(EC_ALS_RGB_INT_L,     PIN(D, 4), GPIO_INT_FALLING, tcs3400_interrupt)
+GPIO_INT(EC_MB_ACCEL_INT_L,    PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, motion_interrupt)
+GPIO_INT(TABLET_MODE_L,        PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
+
+/*
+ * Base / Lid g-sensor interrupt unused on Voema, configure as regular input
+ * for power saving.
+ */
+GPIO(EC_ACCEL_INT,		PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
+
+/* USB-C interrupts */
+GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(E, 0), GPIO_INT_BOTH, tcpc_alert_event)
+GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(A, 2), GPIO_INT_BOTH, tcpc_alert_event)
+
+GPIO_INT(USB_C0_PPC_INT_ODL,	PIN(6, 2), GPIO_INT_BOTH, ppc_interrupt)
+GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(F, 5), GPIO_INT_BOTH, ppc_interrupt)
+
+GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(E, 4), GPIO_INT_BOTH, bc12_interrupt)
+GPIO_INT(USB_C1_MIX_INT_ODL,	PIN(0, 3), GPIO_INT_BOTH, bc12_interrupt)
+
+/* HDMI interrupts */
+
+/* Volume button interrupts */
+GPIO_INT(EC_VOLDN_BTN_ODL,		PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(EC_VOLUP_BTN_ODL,		PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+
+/* Power Sequencing Signals */
+GPIO(EN_PP3300_A,              PIN(A, 3), GPIO_OUT_LOW)
+GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
+GPIO(EN_PPVAR_VCCIN,           PIN(4, 3), GPIO_OUT_LOW) /* Enables VCCIN IMPV9 */
+GPIO(EC_PCH_DSW_PWROK,         PIN(C, 0), GPIO_OUT_LOW)
+
+/* Other wake sources */
+/*
+ * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an
+ * interrupt handler because it is automatically handled by the PSL.
+ *
+ * We need to lock the setting so this gpio can't be reconfigured to overdrive
+ * the real reset signal. (This is the PSL input pin not the real reset pin).
+ */
+GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH |
+					   GPIO_HIB_WAKE_HIGH |
+					   GPIO_LOCKED)
+
+/* AP/PCH Signals */
+GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
+GPIO(EC_PCH_RSMRST_ODL,        PIN(A, 6), GPIO_ODR_LOW) /* TODO - b/140950085 - implement TGL sequencing requirement */
+GPIO(EC_PCH_PWR_BTN_ODL,       PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
+GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
+GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
+GPIO_INT(EC_PROCHOT_IN_L,      PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
+GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
+
+GPIO(EC_PCH_INT_ODL,           PIN(B, 0), GPIO_ODR_HIGH)
+
+/* USB and USBC Signals */
+GPIO(EN_PP5000_USBA,		PIN(C, 6), GPIO_OUT_LOW)	/* Enable USB-A charging - all ports */
+GPIO(USB_A_LOW_PWR_OD,		PIN(6, 6), GPIO_ODR_LOW)	/* Don't limit USB-A charging by default - all ports */
+GPIO(USB_C1_RT_RST_ODL,		PIN(8, 3), GPIO_ODR_LOW)
+GPIO(USB_C0_OC_ODL,		PIN(B, 1), GPIO_ODR_HIGH)
+GPIO(USB_C1_OC_ODL,		PIN(5, 0), GPIO_ODR_HIGH)
+GPIO(USB_C0_FRS_EN,		PIN(6, 0), GPIO_OUT_LOW)
+GPIO(USB_C1_FRS_EN,		PIN(9, 4), GPIO_OUT_LOW)
+
+/* Don't have a load switch for retimer */
+UNIMPLEMENTED(USB_C1_LS_EN)
+
+/* Misc Signals */
+GPIO(EC_H1_PACKET_MODE,		PIN(7, 5), GPIO_OUT_LOW)	/* H1 Packet Mode */
+/*
+ * Despite their names, M2_SSD_PLN and M2_SSD_PLA are active-low, and M2_SSD_PLN
+ * is open-drain.
+ * TODO(b/138954381): Change these names when they change on the schematic.
+ */
+GPIO(M2_SSD_PLN,		PIN(A, 0), GPIO_ODR_HIGH)	/* SSD power-loss notification */
+GPIO(M2_SSD_PLA,		PIN(7, 0), GPIO_INPUT)		/* SSD power-loss acknowledgment */
+GPIO(CCD_MODE_ODL,		PIN(E, 5), GPIO_INPUT)		/* Case Closed Debug Mode */
+GPIO(EC_KB_BL_EN,		PIN(8, 6), GPIO_OUT_LOW)
+
+/* Unused signals */
+GPIO(UNUSED_GPIO72,		PIN(7, 2), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIO41,		PIN(4, 1), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIOF2,		PIN(F, 2), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIOF3,		PIN(F, 3), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIO96,		PIN(9, 6), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIO34,		PIN(3, 4), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIO57,		PIN(5, 7), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIOC2,		PIN(C, 2), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIO61,		PIN(6, 1), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIOB7,		PIN(B, 7), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIO40,		PIN(4, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIOD1,		PIN(D, 1), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIOD0,		PIN(D, 0), GPIO_INPUT | GPIO_PULL_UP)
+
+/*
+ * eDP backlight - both PCH and EC have enable pins that must be high
+ * for the backlight to turn on. Default state is high, and can be turned
+ * off during sleep states.
+ */
+GPIO(EC_EDP_BL_EN,             PIN(D, 3), GPIO_OUT_HIGH)
+
+/* I2C pins - Alternate function below configures I2C module on these pins */
+GPIO(EC_I2C0_SENSOR_SCL,       PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C0_SENSOR_SDA,       PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C1_USB_C0_SCL,       PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C1_USB_C0_SDA,       PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C2_USB_C1_SCL,       PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C2_USB_C1_SDA,       PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C5_BATTERY_SCL,      PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C5_BATTERY_SDA,      PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C7_EEPROM_PWR_SCL_R, PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C7_EEPROM_PWR_SDA_R, PIN(B, 2), GPIO_INPUT)
+
+/* Battery signals */
+GPIO(EC_BATT_PRES_ODL, 		PIN(E, 1), GPIO_INPUT)
+
+ /* LED */
+GPIO(LED_1_L,                  PIN(C, 4), GPIO_OUT_HIGH)        /* Blue */
+GPIO(LED_2_L,                  PIN(C, 3), GPIO_OUT_HIGH)        /* Amber */
+
+/* Alternate functions GPIO definitions */
+ALTERNATE(PIN_MASK(B, BIT(5) | BIT(4)), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V)) /* I2C0 */
+ALTERNATE(PIN_MASK(9, BIT(0) | BIT(2) | BIT(1)), 0, MODULE_I2C, 0)                   /* I2C1 SCL / I2C2 */
+ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)                                     /* I2C1 SDA */
+ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)                            /* I2C5 */
+ALTERNATE(PIN_MASK(B, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)                            /* I2C7 */
+
+/* Keyboard pins */
+#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_00-01 */
+ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_02-07 */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_00-01 */
+GPIO(EC_KSO_02_INV, PIN(1, 7),                        GPIO_OUT_LOW)  /* KSO_02 */
+ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_03-09 */
+ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_10-13 */
+ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_14 */
+ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)                     /* EC_KB_BL_PWM */
+
+/* UART */
+ALTERNATE(PIN_MASK(6, BIT(5) | BIT(4)), 0, MODULE_UART, 0)                           /* UART from EC to Servo */
+
+/* Power Switch Logic (PSL) inputs */
+ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)                    /* GPIOD2 = EC_LID_OPEN */
+ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)  /* GPIO00 = ACOK_OD,
+                                                                       GPIO01 = H1_EC_PWR_BTN_ODL
+                                                                       GPIO02 = EC_RST_ODL */
+
+/* Temperature sensors */
+ALTERNATE(PIN_MASK(4, BIT(2) | BIT(4) | BIT(5)), 0, MODULE_ADC, 0) /* TEMP_SENSOR1,2,4 */
+ALTERNATE(PIN_MASK(F, BIT(1)), 0, MODULE_ADC, 0) /* TEMP_SENSOR3 */
+
diff --git a/board/voema/led.c b/board/voema/led.c
new file mode 100644
index 0000000000..a41f549faf
--- /dev/null
+++ b/board/voema/led.c
@@ -0,0 +1,85 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power and battery LED control for voema
+ */
+
+#include "chipset.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+
+#define LED_ON_LVL 0
+#define LED_OFF_LVL 1
+
+__override const int led_charge_lvl_1 = 5;
+
+__override const int led_charge_lvl_2 = 95;
+
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_AMBER:
+		gpio_set_level(GPIO_LED_2_L, LED_ON_LVL);
+		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
+		break;
+	case EC_LED_COLOR_BLUE:
+		gpio_set_level(GPIO_LED_1_L, LED_ON_LVL);
+		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		brightness_range[EC_LED_COLOR_BLUE] = 1;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(EC_LED_COLOR_AMBER);
+		else if (brightness[EC_LED_COLOR_BLUE] != 0)
+			led_set_color_battery(EC_LED_COLOR_BLUE);
+		else
+			led_set_color_battery(LED_OFF);
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/board/voema/sensors.c b/board/voema/sensors.c
new file mode 100644
index 0000000000..bcb8f9ee36
--- /dev/null
+++ b/board/voema/sensors.c
@@ -0,0 +1,311 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Volteer family-specific sensor configuration */
+#include "accelgyro.h"
+#include "cbi_ssfc.h"
+#include "common.h"
+#include "driver/accel_bma2x2.h"
+#include "driver/accel_kionix.h"
+#include "driver/accelgyro_icm426xx.h"
+#include "driver/accelgyro_icm_common.h"
+#include "driver/als_tcs3400.h"
+#include "driver/sync.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "keyboard_scan.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "util.h"
+
+/******************************************************************************/
+/* Sensors */
+static struct mutex g_lid_accel_mutex;
+static struct mutex g_base_mutex;
+
+/* BMA253 private data */
+static struct accelgyro_saved_data_t g_bma253_base_data;
+static struct accelgyro_saved_data_t g_bma253_lid_data;
+
+static struct icm_drv_data_t g_icm426xx_data;
+
+static struct kionix_accel_data g_kx022_lid_data;
+
+/* TCS3400 private data */
+static struct als_drv_data_t g_tcs3400_data = {
+	.als_cal.scale = 1,
+	.als_cal.uscale = 0,
+	.als_cal.offset = 0,
+	.als_cal.channel_scale = {
+		.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kc from VPD */
+		.cover_scale = ALS_CHANNEL_SCALE(1.0),     /* CT */
+	},
+};
+
+/*
+ * TODO: b/146166425 need to calibrate ALS/RGB sensor. At default settings,
+ * shining phone flashlight on sensor pegs all readings at 0xFFFF.
+ */
+static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
+	.calibration.rgb_cal[X] = {
+		.offset = 0,
+		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
+		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
+		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
+		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
+		.scale = {
+			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kr */
+			.cover_scale = ALS_CHANNEL_SCALE(1.0)
+		}
+	},
+	.calibration.rgb_cal[Y] = {
+		.offset = 0,
+		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
+		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
+		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
+		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
+		.scale = {
+			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kg */
+			.cover_scale = ALS_CHANNEL_SCALE(1.0)
+		},
+	},
+	.calibration.rgb_cal[Z] = {
+		.offset = 0,
+		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
+		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
+		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
+		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
+		.scale = {
+			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kb */
+			.cover_scale = ALS_CHANNEL_SCALE(1.0)
+		}
+	},
+	.calibration.irt = INT_TO_FP(1),
+	.saturation.again = TCS_DEFAULT_AGAIN,
+	.saturation.atime = TCS_DEFAULT_ATIME,
+};
+
+/* Rotation matrix for the lid accelerometer */
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
+
+const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+				       { FLOAT_TO_FP(-1), 0, 0 },
+				       { 0, 0, FLOAT_TO_FP(-1) } };
+
+const mat33_fp_t base_icm_ref = { { FLOAT_TO_FP(1), 0, 0 },
+				  { 0, FLOAT_TO_FP(-1), 0 },
+				  { 0, 0, FLOAT_TO_FP(-1) } };
+
+struct motion_sensor_t kx022_lid_accel = {
+	.name = "Lid Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_KX022,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_LID,
+	.drv = &kionix_accel_drv,
+	.mutex = &g_lid_accel_mutex,
+	.drv_data = &g_kx022_lid_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = KX022_ADDR0_FLAGS,
+	.rot_standard_ref = &lid_standard_ref,
+	.min_frequency = KX022_ACCEL_MIN_FREQ,
+	.max_frequency = KX022_ACCEL_MAX_FREQ,
+	.default_range = 2, /* g, to support tablet mode */
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	},
+};
+
+struct motion_sensor_t motion_sensors[] = {
+	[LID_ACCEL] = {
+		.name = "Lid Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMA255,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &bma2x2_accel_drv,
+		.mutex = &g_lid_accel_mutex,
+		.drv_data = &g_bma253_lid_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
+		.rot_standard_ref = &lid_standard_ref,
+		.min_frequency = BMA255_ACCEL_MIN_FREQ,
+		.max_frequency = BMA255_ACCEL_MAX_FREQ,
+		.default_range = 2, /* g, to support tablet mode */
+		.config = {
+			/* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+			/* Sensor on in S3 */
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+		},
+	},
+	[BASE_ACCEL] = {
+		.name = "Base Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMA255,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &bma2x2_accel_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = &g_bma253_base_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR2_FLAGS,
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = BMA255_ACCEL_MIN_FREQ,
+		.max_frequency = BMA255_ACCEL_MAX_FREQ,
+		.default_range = 4, /* g */
+		.config = {
+			/* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+			/* Sensor on in S3 */
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+		},
+	},
+	[CLEAR_ALS] = {
+		.name = "Clear Light",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_TCS3400,
+		.type = MOTIONSENSE_TYPE_LIGHT,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &tcs3400_drv,
+		.drv_data = &g_tcs3400_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = TCS3400_I2C_ADDR_FLAGS,
+		.rot_standard_ref = NULL,
+		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
+		.min_frequency = TCS3400_LIGHT_MIN_FREQ,
+		.max_frequency = TCS3400_LIGHT_MAX_FREQ,
+		.config = {
+			/* Run ALS sensor in S0 */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 1000,
+			},
+		},
+	},
+
+	[RGB_ALS] = {
+		/*
+		 * RGB channels read by CLEAR_ALS and so the i2c port and
+		 * address do not need to be defined for RGB_ALS.
+		 */
+		.name = "RGB Light",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_TCS3400,
+		.type = MOTIONSENSE_TYPE_LIGHT_RGB,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &tcs3400_rgb_drv,
+		.drv_data = &g_tcs3400_rgb_data,
+		.rot_standard_ref = NULL,
+		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
+	},
+};
+unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+struct motion_sensor_t icm_base_accel = {
+		.name = "Base Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_ICM426XX,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &icm426xx_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = &g_icm426xx_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+		.rot_standard_ref = &base_icm_ref,
+		.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
+		.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
+		.default_range = 4, /* g */
+		.config = {
+			/* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+			/* Sensor on in S3 */
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+		},
+};
+
+struct motion_sensor_t icm_base_gyro = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &base_icm_ref,
+	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
+	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
+};
+
+/* ALS instances when LPC mapping is needed. Each entry directs to a sensor. */
+const struct motion_sensor_t *motion_als_sensors[] = {
+	&motion_sensors[CLEAR_ALS],
+};
+BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
+
+static void baseboard_sensors_init(void)
+{
+	/* Enable interrupt for the TCS3400 color light sensor */
+	gpio_enable_interrupt(GPIO_EC_ALS_RGB_INT_L);
+
+	/*
+	 * TODO: If a SSFC for the base sensor is added, add the check
+	 * here.
+	 */
+	if (get_cbi_ssfc_base_sensor() == SSFC_SENSOR_BASE_ICM426XX) {
+		gpio_enable_interrupt(GPIO_EC_MB_ACCEL_INT_L);
+		motion_sensors[BASE_ACCEL] = icm_base_accel;
+		motion_sensors[BASE_GYRO] = icm_base_gyro;
+		ccprints("BASE ACCEL/GYRO is ICM426XX");
+	} else
+		ccprints("BASE_ACCEL is BMA253");
+
+	if (get_cbi_ssfc_lid_sensor() == SSFC_SENSOR_LID_KX022) {
+		motion_sensors[LID_ACCEL] = kx022_lid_accel;
+		ccprints("LID_ACCEL is KX022");
+	} else
+		ccprints("LID_ACCEL is BMA253");
+}
+DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_DEFAULT);
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	icm426xx_interrupt(signal);
+}
+
+int board_accel_force_mode_mask(void)
+{
+	if (system_get_board_version() <= 2)
+		return (BIT(LID_ACCEL) | BIT(CLEAR_ALS) | BIT(BASE_ACCEL));
+	else
+		return (BIT(LID_ACCEL) | BIT(CLEAR_ALS));
+}
diff --git a/board/voema/vif_override.xml b/board/voema/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/voema/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/volet/battery.c b/board/volet/battery.c
new file mode 100644
index 0000000000..89769e8364
--- /dev/null
+++ b/board/volet/battery.c
@@ -0,0 +1,125 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "common.h"
+#include "util.h"
+
+/*
+ * Battery info for all Volteer battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	/* AP19B8M */
+	[BATTERY_AP19B8M] = {
+		.fuel_gauge = {
+			.manuf_name = "LGC KT0030G024",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.reg_addr = 0x43,
+				.reg_mask = 0x0001,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0002,
+				.cfet_off_val = 0x0000,
+			}
+		},
+		.batt_info = {
+			.voltage_max          = 13350,
+			.voltage_normal       = 11610,
+			.voltage_min          = 9000,
+			.precharge_current    = 256,
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 50,
+			.charging_min_c       = 0,
+			.charging_max_c       = 60,
+			.discharging_min_c    = -20,
+			.discharging_max_c    = 75,
+		},
+	},
+	/* LGC AP18C8K Battery Information */
+	 [BATTERY_LGC_AP18C8K] = {
+		.fuel_gauge = {
+			.manuf_name = "LGC KT0030G020",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.reg_addr = 0x43,
+				.reg_mask = 0x0001,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0002,
+				.cfet_off_val = 0x0000,
+			},
+		},
+		.batt_info = {
+			.voltage_max            = 13050,
+			.voltage_normal         = 11250,
+			.voltage_min            = 9000,
+			.precharge_current      = 256,
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 50,
+			.charging_min_c         = 0,
+			.charging_max_c         = 60,
+			.discharging_min_c      = -20,
+			.discharging_max_c      = 75,
+		},
+	},
+	/* COSMX AP20CBL Battery Information */
+	 [BATTERY_COSMX_AP20CBL] = {
+		.fuel_gauge = {
+			.manuf_name = "COSMX KT0030B002",
+			.device_name = "AP20CBL",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x2000,
+				.disconnect_val = 0x2000,
+			},
+		},
+		.batt_info = {
+			.voltage_max            = 13200,
+			.voltage_normal         = 11550,
+			.voltage_min            = 9000,
+			.precharge_current      = 256,
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 50,
+			.charging_min_c         = 0,
+			.charging_max_c         = 60,
+			.discharging_min_c      = -20,
+			.discharging_max_c      = 75,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_AP19B8M;
diff --git a/board/volet/board.c b/board/volet/board.c
new file mode 100644
index 0000000000..222fdde37e
--- /dev/null
+++ b/board/volet/board.c
@@ -0,0 +1,509 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Volteer board-specific configuration */
+#include "accelgyro.h"
+#include "button.h"
+#include "cbi_ec_fw_config.h"
+#include "common.h"
+#include "driver/accel_bma2x2.h"
+#include "driver/accelgyro_bmi160.h"
+#include "driver/als_tcs3400.h"
+#include "driver/bc12/pi3usb9201.h"
+#include "driver/ppc/syv682x.h"
+#include "driver/sync.h"
+#include "driver/tcpm/ps8xxx.h"
+#include "driver/tcpm/rt1715.h"
+#include "driver/tcpm/tcpci.h"
+#include "extpower.h"
+#include "fan.h"
+#include "fan_chip.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "keyboard_raw.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "switch.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "throttle_ap.h"
+#include "uart.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tbt.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
+
+static const struct ec_response_keybd_config volet_kb = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+static const struct ec_response_keybd_config volet_kb_num = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY | KEYBD_CAP_NUMERIC_KEYPAD,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	if (!ec_cfg_has_numeric_pad())
+		return &volet_kb;
+	else
+		return &volet_kb_num;
+}
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/* Increase from 50 us, because KSO_02 passes through the H1. */
+	.output_settle_us = 80,
+	/* Other values should be the same as the default configuration. */
+	.debounce_down_us = 9 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x1c, 0xfe, 0xff, 0xff, 0xff, 0xf5, 0xff,
+		0xa4, 0xff, 0xfe, 0x55, 0xfe, 0xff, 0xff,
+		0xff, /* full set */
+	},
+};
+
+/*
+ * We have total 30 pins for keyboard connecter {-1, -1} mean
+ * the N/A pin that don't consider it and reserve index 0 area
+ * that we don't have pin 0.
+ */
+const int keyboard_factory_scan_pins[][2] = {
+	{ -1, -1 }, { 0, 5 },	{ 1, 1 }, { 1, 0 },   { 0, 6 },	  { 0, 7 },
+	{ -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 },   { -1, -1 }, { 1, 6 },
+	{ 1, 7 },   { 3, 1 },	{ 2, 0 }, { 1, 5 },   { 2, 6 },	  { 2, 7 },
+	{ 2, 1 },   { 2, 4 },	{ 2, 5 }, { 1, 2 },   { 2, 3 },	  { 2, 2 },
+	{ 3, 0 },   { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 },	  { -1, -1 },
+	{ -1, -1 },
+};
+const int keyboard_factory_scan_pins_used =
+	ARRAY_SIZE(keyboard_factory_scan_pins);
+
+__override uint32_t board_override_feature_flags0(uint32_t flags0)
+{
+	/*
+	 * Remove keyboard backlight feature for devices that don't support it.
+	 */
+	if (!ec_cfg_has_keyboard_backlight())
+		return (flags0 & ~EC_FEATURE_MASK_0(EC_FEATURE_PWM_KEYB));
+	else
+		return flags0;
+}
+
+/******************************************************************************/
+/*
+ * FW_CONFIG defaults for Voxel if the CBI data is not initialized.
+ */
+union volteer_cbi_fw_config fw_config_defaults = {
+	.usb_db = DB_USB4_GEN3,
+};
+
+/******************************************************************************/
+/* Physical fans. These are logically separate from pwm_channels. */
+
+const struct fan_conf fan_conf_0 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
+	.pgood_gpio = -1,
+	.enable_gpio = GPIO_EN_PP5000_FAN,
+};
+
+/*
+ * Fan specs from datasheet:
+ * Max speed 5900 rpm (+/- 7%), minimum duty cycle 30%.
+ * Minimum speed not specified by RPM. Set minimum RPM to max speed (with
+ * margin) x 30%.
+ *    5900 x 1.07 x 0.30 = 1894, round up to 1900
+ * reference that temperature and fan settings
+ * are derived from data in b/167523658#39
+ */
+const struct fan_rpm fan_rpm_0 = {
+	.rpm_min = 2100,
+	.rpm_start = 2100,
+	.rpm_max = 5800,
+};
+
+const struct fan_t fans[FAN_CH_COUNT] = {
+	[FAN_CH_0] = {
+		.conf = &fan_conf_0,
+		.rpm = &fan_rpm_0,
+	},
+};
+
+/******************************************************************************/
+/* EC thermal management configuration */
+
+/*
+ * Reference that temperature and fan settings
+ * are derived from data in b/167523658#39
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(85), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(68), \
+		}, \
+		.temp_fan_off = C_TO_K(25), \
+		.temp_fan_max = C_TO_K(90), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
+
+struct ec_thermal_config thermal_params[] = {
+	[TEMP_SENSOR_1_CHARGER] = THERMAL_CPU,
+	[TEMP_SENSOR_2_PP3300_REGULATOR] = THERMAL_CPU,
+	[TEMP_SENSOR_3_DDR_SOC] = THERMAL_CPU,
+	[TEMP_SENSOR_4_FAN] = THERMAL_CPU,
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
+
+/******************************************************************************/
+/* MFT channels. These are logically separate from pwm_channels. */
+const struct mft_t mft_channels[] = {
+	[MFT_CH_0] = {
+		.module = NPCX_MFT_MODULE_1,
+		.clk_src = TCKC_LFCLK,
+		.pwm_id = PWM_CH_FAN,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
+
+/******************************************************************************/
+/* I2C port map configuration */
+const struct i2c_port_t i2c_ports[] = {
+	{
+		.name = "sensor",
+		.port = I2C_PORT_SENSOR,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C0_SENSOR_SCL,
+		.sda = GPIO_EC_I2C0_SENSOR_SDA,
+	},
+	{
+		.name = "usb_c0",
+		.port = I2C_PORT_USB_C0,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C1_USB_C0_SCL,
+		.sda = GPIO_EC_I2C1_USB_C0_SDA,
+	},
+	{
+		.name = "usb_c1",
+		.port = I2C_PORT_USB_C1,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C2_USB_C1_SCL,
+		.sda = GPIO_EC_I2C2_USB_C1_SDA,
+	},
+	{
+		.name = "power",
+		.port = I2C_PORT_POWER,
+		.kbps = 100,
+		.scl = GPIO_EC_I2C5_POWER_SCL,
+		.sda = GPIO_EC_I2C5_POWER_SDA,
+	},
+	{
+		.name = "eeprom",
+		.port = I2C_PORT_EEPROM,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C7_EEPROM_SCL,
+		.sda = GPIO_EC_I2C7_EEPROM_SDA,
+	},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+/******************************************************************************/
+/* PWM configuration */
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_FAN] = {
+		.channel = 5,
+		.flags = PWM_CONFIG_OPEN_DRAIN,
+		.freq = 25000
+	},
+	[PWM_CH_KBLIGHT] = {
+		.channel = 3,
+		.flags = 0,
+		/*
+		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
+		 * flicker. Higher frequencies consume similar average power to
+		 * lower PWM frequencies, but higher frequencies record a much
+		 * lower maximum power.
+		 */
+		.freq = 2400,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+static void kb_backlight_enable(void)
+{
+	if (ec_cfg_has_keyboard_backlight())
+		gpio_set_level(GPIO_EC_KB_BL_EN, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, kb_backlight_enable, HOOK_PRIO_DEFAULT);
+
+static void kb_backlight_disable(void)
+{
+	if (ec_cfg_has_keyboard_backlight())
+		gpio_set_level(GPIO_EC_KB_BL_EN, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, kb_backlight_disable, HOOK_PRIO_DEFAULT);
+
+static void ps8815_reset(void)
+{
+	int val;
+
+	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 0);
+	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS));
+	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 1);
+	msleep(PS8815_FW_INIT_DELAY_MS);
+
+	/*
+	 * b/144397088
+	 * ps8815 firmware 0x01 needs special configuration
+	 */
+
+	CPRINTS("%s: patching ps8815 registers", __func__);
+
+	if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) ==
+	    EC_SUCCESS)
+		CPRINTS("ps8815: reg 0x0f was %02x", val);
+
+	if (i2c_write8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f,
+		       0x31) == EC_SUCCESS)
+		CPRINTS("ps8815: reg 0x0f set to 0x31");
+
+	if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) ==
+	    EC_SUCCESS)
+		CPRINTS("ps8815: reg 0x0f now %02x", val);
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * Only the Burnside Bridge retimers provide a reset pin, but this is
+	 * already handled by the bb_retimer.c driver.
+	 */
+	ps8815_reset();
+	usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+}
+
+/******************************************************************************/
+/* USB-A charging control */
+
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_PP5000_USBA,
+};
+
+/******************************************************************************/
+/* USBC PPC configuration */
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.drv = &syv682x_drv,
+		.frs_en = GPIO_USB_C0_FRS_EN,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C1,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.drv = &syv682x_drv,
+		.frs_en = GPIO_USB_C1_FRS_EN,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/******************************************************************************/
+/* PPC support routines */
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C1);
+		break;
+	default:
+		break;
+	}
+}
+
+__override void board_cbi_init(void)
+{
+	if ((!IS_ENABLED(TEST_BUILD) && !ec_cfg_has_numeric_pad())) {
+		keyboard_raw_set_cols(KEYBOARD_COLS_NO_KEYPAD);
+		/* Search key is moved back to col=1,row=0 */
+		keyscan_config.actual_key_mask[0] = 0x14;
+		keyscan_config.actual_key_mask[1] = 0xff;
+		keyscan_config.actual_key_mask[11] = 0xfa;
+		keyscan_config.actual_key_mask[12] = 0xca;
+	}
+}
+
+/******************************************************************************/
+/* BC1.2 charger detect configuration */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C1,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
+
+/******************************************************************************/
+/* USBC TCPC configuration */
+const struct  tcpc_config_t tcpc_config[] = {
+	[USBC_PORT_C0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0,
+			.addr_flags = RT1715_I2C_ADDR_FLAGS,
+		},
+		.drv = &rt1715_tcpm_drv,
+	},
+	[USBC_PORT_C1] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C1,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V,
+		.drv = &ps8xxx_tcpm_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
+BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
+
+/*
+ * USB3 DB mux configuration - the top level mux still needs to be set to the
+ * virtual_usb_mux_driver so the AP gets notified of mux changes and updates
+ * the TCSS configuration on state changes.
+ */
+static const struct usb_mux_chain usbc1_usb3_db_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
+	.next = NULL,
+};
+
+/******************************************************************************/
+/* USBC mux configuration - Tiger Lake includes internal mux */
+const struct usb_mux_chain usb_muxes[] = {
+	[USBC_PORT_C0] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+	},
+	[USBC_PORT_C1] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc1_usb3_db_retimer,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
+
+static void board_tcpc_init(void)
+{
+	/* Don't reset TCPCs after initial reset */
+	if (!system_jumped_late())
+		board_reset_pd_mcu();
+
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
+
+	/* Enable BC1.2 interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
+
+/******************************************************************************/
+/* TCPC support routines */
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	/*
+	 * Check which port has the ALERT line set
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL))
+		status |= PD_STATUS_TCPC_ALERT_0;
+	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL))
+		status |= PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
+
+int ppc_get_alert_status(int port)
+{
+	if (port == USBC_PORT_C0)
+		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
+	else
+		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
+}
diff --git a/board/volet/board.h b/board/volet/board.h
new file mode 100644
index 0000000000..c616b1cbe1
--- /dev/null
+++ b/board/volet/board.h
@@ -0,0 +1,187 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Volteer board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* Baseboard features */
+#include "baseboard.h"
+
+/* Optional features */
+#undef NPCX7_PWM1_SEL
+#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */
+
+/*
+ * The RAM and flash size combination on the the NPCX797FC does not leave
+ * any unused flash space that can be used to store the .init_rom section.
+ */
+#undef CONFIG_CHIP_INIT_ROM_REGION
+
+#define CONFIG_VBOOT_EFS2
+
+#define CONFIG_POWER_BUTTON
+
+#undef CONFIG_UART_TX_BUF_SIZE
+#define CONFIG_UART_TX_BUF_SIZE 4096
+
+/* Chipset features */
+#define CONFIG_POWER_PP5000_CONTROL
+#define CONFIG_CPU_PROCHOT_GATE_ON_C10
+
+/* LED defines */
+#define CONFIG_LED_ONOFF_STATES
+
+/* Keyboard features */
+#define CONFIG_KEYBOARD_FACTORY_TEST
+#define CONFIG_KEYBOARD_REFRESH_ROW3
+
+/* Keyboard backliht */
+#define CONFIG_PWM
+#define CONFIG_PWM_KBLIGHT
+
+/* Sensors */
+#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
+/* BMI160 Base accel/gyro */
+#define CONFIG_ACCELGYRO_BMI160
+#define CONFIG_ACCELGYRO_ICM426XX /* Base accel second source*/
+#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+/* Lid operates in forced mode, base in FIFO */
+#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
+
+/* BMA253 Lid accel */
+#define CONFIG_ACCEL_KX022 /* Lid accel */
+#define CONFIG_ACCEL_BMA255
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_UPDATE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+
+/* USB Type C and USB PD defines */
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+
+/*
+ * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
+ * cables only support up to 60W.
+ */
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
+
+#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
+#ifdef BOARD_VOXEL_ECMODEENTRY
+#undef CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
+#endif
+
+/* Enabling Thunderbolt-compatible mode */
+#define CONFIG_USB_PD_TBT_COMPAT_MODE
+
+/* USB Type A Features */
+#define USB_PORT_COUNT 1
+#define CONFIG_USB_PORT_POWER_DUMB
+
+/* USBC PPC*/
+#define CONFIG_USBC_PPC_SYV682X /* USBC port C0/C1 */
+#define CONFIG_USB_PD_FRS_PPC
+#undef CONFIG_USB_PD_TCPC_RUNTIME_CONFIG
+#undef CONFIG_USB_PD_TCPM_TUSB422
+#undef CONFIG_USB_MUX_RUNTIME_CONFIG
+
+/* BC 1.2 */
+
+/* Volume Button feature */
+
+/* Fan features */
+
+/* charger defines */
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+
+/* Retimer */
+#undef CONFIG_USBC_RETIMER_INTEL_BB
+#undef CONFIG_USBC_RETIMER_INTEL_BB_RUNTIME_CONFIG
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_LID_OPEN GPIO_EC_LID_OPEN
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
+
+/* I2C Bus Configuration */
+#define CONFIG_I2C
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0
+#define I2C_PORT_POWER NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+
+#define I2C_PORT_BATTERY I2C_PORT_POWER
+#define I2C_PORT_CHARGER I2C_PORT_EEPROM
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+#define CONFIG_I2C_CONTROLLER
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum battery_type {
+	BATTERY_AP19B8M,
+	BATTERY_LGC_AP18C8K,
+	BATTERY_COSMX_AP20CBL,
+	BATTERY_TYPE_COUNT,
+};
+
+enum pwm_channel { PWM_CH_FAN, PWM_CH_KBLIGHT, PWM_CH_COUNT };
+
+enum sensor_id {
+	LID_ACCEL = 0,
+	BASE_ACCEL,
+	BASE_GYRO,
+	SENSOR_COUNT,
+};
+
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
+
+void board_reset_pd_mcu(void);
+
+void motion_interrupt(enum gpio_signal signal);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/volet/build.mk b/board/volet/build.mk
new file mode 100644
index 0000000000..18397fdec3
--- /dev/null
+++ b/board/volet/build.mk
@@ -0,0 +1,17 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx7
+CHIP_VARIANT:=npcx7m7fc
+BASEBOARD:=volteer
+
+board-y=board.o
+board-y+=battery.o
+board-y+=led.o
+board-y+=sensors.o
diff --git a/board/volet/ec.tasklist b/board/volet/ec.tasklist
new file mode 100644
index 0000000000..07a91894ed
--- /dev/null
+++ b/board/volet/ec.tasklist
@@ -0,0 +1,27 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/volet/gpio.inc b/board/volet/gpio.inc
new file mode 100644
index 0000000000..079c731785
--- /dev/null
+++ b/board/volet/gpio.inc
@@ -0,0 +1,184 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+/* Wake Source interrupts */
+GPIO_INT(EC_LID_OPEN,          PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
+GPIO_INT(EC_WP_L,              PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(H1_EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
+GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
+
+/* Power sequencing interrupts */
+GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
+#endif
+GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_EC_RSMRST_ODL,     PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_EC_DSW_PWROK,      PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4),  GPIO_INT_BOTH, power_signal_interrupt)
+
+/* Sensor Interrupts */
+GPIO_INT(EC_IMU_INT_L,         PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, motion_interrupt)
+GPIO(EC_ALS_RGB_INT_L,         PIN(D, 4), GPIO_INPUT | GPIO_PULL_UP)	/* unused */
+GPIO_INT(TABLET_MODE_L,        PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
+/*
+ * Lid g-sensor interrupt unused on Voxel, configure as regular input for
+ * power saving.
+ */
+GPIO(EC_ACCEL_INT,		PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
+
+/* USB-C interrupts */
+GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(E, 0), GPIO_INT_BOTH, tcpc_alert_event)
+GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(A, 2), GPIO_INT_BOTH, tcpc_alert_event)
+
+GPIO_INT(USB_C0_PPC_INT_ODL,	PIN(6, 2), GPIO_INT_BOTH, ppc_interrupt)
+GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(F, 5), GPIO_INT_BOTH, ppc_interrupt)
+
+GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(E, 4), GPIO_INT_BOTH, bc12_interrupt)
+GPIO_INT(USB_C1_MIX_INT_ODL,	PIN(0, 3), GPIO_INT_BOTH, bc12_interrupt)
+
+/* HDMI interrupts */
+
+/* Volume button interrupts */
+GPIO_INT(EC_VOLDN_BTN_ODL,		PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(EC_VOLUP_BTN_ODL,		PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+
+/* Power Sequencing Signals */
+GPIO(EN_PP3300_A,              PIN(A, 3), GPIO_OUT_LOW)
+GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
+GPIO(EN_PPVAR_VCCIN,           PIN(4, 3), GPIO_OUT_LOW) /* Enables VCCIN IMPV9 */
+GPIO(EC_PCH_DSW_PWROK,         PIN(C, 0), GPIO_OUT_LOW)
+
+/* Other wake sources */
+/*
+ * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an
+ * interrupt handler because it is automatically handled by the PSL.
+ *
+ * We need to lock the setting so this gpio can't be reconfigured to overdrive
+ * the real reset signal. (This is the PSL input pin not the real reset pin).
+ */
+GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH |
+					   GPIO_HIB_WAKE_HIGH |
+					   GPIO_LOCKED)
+
+/* AP/PCH Signals */
+GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
+GPIO(EC_PCH_RSMRST_ODL,        PIN(A, 6), GPIO_ODR_LOW) /* TODO - b/140950085 - implement TGL sequencing requirement */
+GPIO(EC_PCH_PWR_BTN_ODL,       PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
+GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
+GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
+GPIO_INT(EC_PROCHOT_IN_L,      PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
+GPIO_INT(CPU_C10_GATE_L,       PIN(6, 7), GPIO_INT_RISING, throttle_ap_c10_input_interrupt)
+GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
+
+GPIO(EC_PCH_INT_ODL,           PIN(B, 0), GPIO_ODR_HIGH)
+
+/* USB and USBC Signals */
+GPIO(EN_PP5000_USBA,		PIN(3, 5), GPIO_OUT_LOW)	/* Enable USB-A charging - all ports */
+GPIO(USB_A_LOW_PWR_OD,		PIN(6, 6), GPIO_ODR_LOW)	/* Don't limit USB-A charging by default - all ports */
+
+/*
+ * USB_C1 moved from GPIO32 to GPIO83 on boards with board ID >=1.
+ * GPIO83/EN_PP1800_A is DNS on board ID 0 and GPIO32 is N/C on board ID >=1
+ * so it's safe to define GPIOs compatible with both designs.
+ * TODO (b/149858568): remove board ID=0 support.
+ */
+GPIO(USB_C0_RT_RST_ODL,			PIN(4, 1), GPIO_ODR_LOW)
+GPIO(USB_C1_RT_RST_ODL,			PIN(8, 3), GPIO_ODR_LOW) /* USB_C1 Reset on boards board ID >=1 */
+GPIO(USB_C0_OC_ODL,			PIN(B, 1), GPIO_ODR_HIGH)
+GPIO(USB_C1_OC_ODL,			PIN(5, 0), GPIO_ODR_HIGH)
+GPIO(USB_C0_RT_INT_ODL,			PIN(C, 6), GPIO_INPUT)
+GPIO(USB_C1_RT_INT_ODL,			PIN(9, 6), GPIO_INPUT)
+GPIO(USB_C0_FRS_EN,			PIN(C, 2), GPIO_OUT_LOW)
+GPIO(USB_C1_FRS_EN,			PIN(9, 4), GPIO_OUT_LOW)
+
+/* Don't have a load switch for retimer */
+UNIMPLEMENTED(USB_C0_LS_EN)
+UNIMPLEMENTED(USB_C1_LS_EN)
+
+/* Misc Signals */
+GPIO(EC_H1_PACKET_MODE,		PIN(7, 5), GPIO_OUT_LOW)	/* H1 Packet Mode */
+GPIO(LED_1_L,                  PIN(C, 4), GPIO_OUT_HIGH)        /* Blue */
+GPIO(LED_2_L,                  PIN(C, 3), GPIO_OUT_HIGH)        /* Yellow */
+GPIO(EC_KB_BL_EN,		PIN(8, 6), GPIO_OUT_LOW)	/* Keyboard backlight enable*/
+
+GPIO(M2_SSD_PLN,        PIN(A, 0), GPIO_ODR_HIGH)	/* SSD power-loss notification */
+GPIO(M2_SSD_PLA,        PIN(7, 0), GPIO_INPUT)		/* SSD power-loss acknowledgment */
+GPIO(CCD_MODE_ODL,      PIN(E, 5), GPIO_INPUT)		/* Case Closed Debug Mode */
+GPIO(EC_SLP_S0IX,       PIN(7, 2), GPIO_INPUT | GPIO_PULL_UP)
+
+/* Unused signals */
+GPIO(UNUSED_GPIO34,     PIN(3, 4), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIO60,     PIN(6, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIOA7,     PIN(A, 7), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIOD0,     PIN(D, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIOD1,     PIN(D, 1), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIOF2,     PIN(F, 2), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(UNUSED_GPIOF3,     PIN(F, 3), GPIO_INPUT | GPIO_PULL_UP)
+
+/*
+ * eDP backlight - both PCH and EC have enable pins that must be high
+ * for the backlight to turn on. Default state is high, and can be turned
+ * off during sleep states.
+ */
+GPIO(EC_EDP_BL_EN,             PIN(D, 3), GPIO_OUT_HIGH)
+
+/* I2C pins - Alternate function below configures I2C module on these pins */
+GPIO(EC_I2C0_SENSOR_SCL,       PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C0_SENSOR_SDA,       PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C1_USB_C0_SCL,       PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C1_USB_C0_SDA,       PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C2_USB_C1_SCL,       PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C2_USB_C1_SDA,       PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C5_POWER_SCL,        PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C5_POWER_SDA,        PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C7_EEPROM_SCL,       PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C7_EEPROM_SDA,       PIN(B, 2), GPIO_INPUT)
+
+/* Battery signals */
+GPIO(EC_BATT_PRES_ODL, 		PIN(E, 1), GPIO_INPUT)
+
+/* Alternate functions GPIO definitions */
+ALTERNATE(PIN_MASK(B, BIT(5) | BIT(4)), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V)) /* I2C0 */
+ALTERNATE(PIN_MASK(9, BIT(0) | BIT(2) | BIT(1)), 0, MODULE_I2C, 0)                   /* I2C1 SCL / I2C2 */
+ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)                                     /* I2C1 SDA */
+ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)                            /* I2C5 */
+ALTERNATE(PIN_MASK(B, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)                            /* I2C7 */
+
+/* Fan signals */
+GPIO(EN_PP5000_FAN,            PIN(6, 1), GPIO_OUT_LOW)
+ALTERNATE(PIN_MASK(B, BIT(7)), 0, MODULE_PWM, 0)	/* FAN_PWM */
+ALTERNATE(PIN_MASK(4, BIT(0)), 0, MODULE_PWM, 0)	/* FAN_SPEED_TACH */
+
+/* Keyboard pins */
+#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_00-01 */
+ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_02-07 */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_00-01 */
+GPIO(EC_KSO_02_INV, PIN(1, 7),                        GPIO_OUT_LOW)  /* KSO_02 */
+ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_03-09 */
+ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_10-13 */
+ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_14 */
+ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)                     /* EC_KB_BL_PWM */
+
+/* UART */
+ALTERNATE(PIN_MASK(6, BIT(5) | BIT(4)), 0, MODULE_UART, 0)                           /* UART from EC to Servo */
+
+/* Power Switch Logic (PSL) inputs */
+ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)                    /* GPIOD2 = EC_LID_OPEN */
+ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)  /* GPIO00 = ACOK_OD,
+                                                                       GPIO01 = H1_EC_PWR_BTN_ODL
+                                                                       GPIO02 = EC_RST_ODL */
+
+/* Temperature sensors */
+ALTERNATE(PIN_MASK(4, BIT(2) | BIT(4) | BIT(5)), 0, MODULE_ADC, 0) /* TEMP_SENSOR1,2,4 */
+ALTERNATE(PIN_MASK(F, BIT(1)), 0, MODULE_ADC, 0) /* TEMP_SENSOR3 */
diff --git a/board/volet/led.c b/board/volet/led.c
new file mode 100644
index 0000000000..2458e882e3
--- /dev/null
+++ b/board/volet/led.c
@@ -0,0 +1,84 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power and battery LED control for Volteer
+ */
+
+#include "chipset.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+
+#define LED_ON_LVL 0
+#define LED_OFF_LVL 1
+
+__override const int led_charge_lvl_1 = 5;
+
+__override const int led_charge_lvl_2 = 95;
+
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_AMBER:
+		gpio_set_level(GPIO_LED_2_L, LED_ON_LVL);
+		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
+		break;
+	case EC_LED_COLOR_BLUE:
+		gpio_set_level(GPIO_LED_1_L, LED_ON_LVL);
+		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		brightness_range[EC_LED_COLOR_BLUE] = 1;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		if (brightness[EC_LED_COLOR_BLUE] != 0)
+			led_set_color_battery(EC_LED_COLOR_BLUE);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(EC_LED_COLOR_AMBER);
+		else
+			led_set_color_battery(LED_OFF);
+	}
+	return EC_SUCCESS;
+}
diff --git a/board/volet/sensors.c b/board/volet/sensors.c
new file mode 100644
index 0000000000..932b39f43e
--- /dev/null
+++ b/board/volet/sensors.c
@@ -0,0 +1,241 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Volteer family-specific sensor configuration */
+#include "accelgyro.h"
+#include "cbi_ec_fw_config.h"
+#include "cbi_ssfc.h"
+#include "common.h"
+#include "driver/accel_bma2x2.h"
+#include "driver/accel_kionix.h"
+#include "driver/accelgyro_bmi160.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "driver/accelgyro_icm426xx.h"
+#include "driver/accelgyro_icm_common.h"
+#include "driver/als_tcs3400.h"
+#include "driver/sync.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "keyboard_scan.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ##args)
+/******************************************************************************/
+/* Sensors */
+static struct mutex g_lid_accel_mutex;
+static struct mutex g_base_mutex;
+
+/* BMA253 private data */
+static struct accelgyro_saved_data_t g_bma253_data;
+static struct kionix_accel_data g_kx022_data;
+
+/* BMI160 private data */
+static struct bmi_drv_data_t g_bmi160_data;
+static struct icm_drv_data_t g_icm426xx_data;
+
+/* Rotation matrix for the lid accelerometer */
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
+
+const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+				       { FLOAT_TO_FP(-1), 0, 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
+
+static const mat33_fp_t base_icm_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					 { 0, FLOAT_TO_FP(1), 0 },
+					 { 0, 0, FLOAT_TO_FP(1) } };
+
+struct motion_sensor_t kx022_lid_accel = {
+	.name = "Lid Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_KX022,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_LID,
+	.drv = &kionix_accel_drv,
+	.mutex = &g_lid_accel_mutex,
+	.drv_data = &g_kx022_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = KX022_ADDR0_FLAGS,
+	.rot_standard_ref = &lid_standard_ref,
+	.min_frequency = KX022_ACCEL_MIN_FREQ,
+	.max_frequency = KX022_ACCEL_MAX_FREQ,
+	.default_range = 2, /* g, to support tablet mode */
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	},
+};
+
+struct motion_sensor_t icm426xx_base_accel = {
+	.name = "Base Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
+	.rot_standard_ref = &base_icm_ref,
+	.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
+	.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+	},
+};
+
+struct motion_sensor_t icm426xx_base_gyro = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &base_icm_ref,
+	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
+	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
+};
+
+struct motion_sensor_t motion_sensors[] = {
+	[LID_ACCEL] = {
+		.name = "Lid Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMA255,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &bma2x2_accel_drv,
+		.mutex = &g_lid_accel_mutex,
+		.drv_data = &g_bma253_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
+		.rot_standard_ref = &lid_standard_ref,
+		.min_frequency = BMA255_ACCEL_MIN_FREQ,
+		.max_frequency = BMA255_ACCEL_MAX_FREQ,
+		.default_range = 2, /* g, to support tablet mode */
+		.config = {
+			/* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+			/* Sensor on in S3 */
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+		},
+	},
+	[BASE_ACCEL] = {
+		.name = "Base Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMI160,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &bmi160_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = &g_bmi160_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = BMI_ACCEL_MIN_FREQ,
+		.max_frequency = BMI_ACCEL_MAX_FREQ,
+		.default_range = 4, /* g */
+		.config = {
+			/* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+			/* Sensor on in S3 */
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+		},
+	},
+
+	[BASE_GYRO] = {
+		.name = "Base Gyro",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMI160,
+		.type = MOTIONSENSE_TYPE_GYRO,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &bmi160_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = &g_bmi160_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+		.default_range = 1000, /* dps */
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = BMI_GYRO_MIN_FREQ,
+		.max_frequency = BMI_GYRO_MAX_FREQ,
+	},
+};
+unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+static void board_sensors_init(void)
+{
+	if (ec_cfg_has_tabletmode()) {
+		if (get_cbi_ssfc_base_sensor() == SSFC_SENSOR_BASE_ICM426XX) {
+			motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
+			motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
+			ccprints("BASE GYRO is ICM426XX");
+		} else
+			ccprints("BASE GYRO is BMI160");
+
+		if (get_cbi_ssfc_lid_sensor() == SSFC_SENSOR_LID_KX022) {
+			motion_sensors[LID_ACCEL] = kx022_lid_accel;
+			ccprints("LID_ACCEL is KX022");
+		} else
+			ccprints("LID_ACCEL is BMA253");
+
+		motion_sensor_count = ARRAY_SIZE(motion_sensors);
+		/* Enable interrupt for the accel/gyro sensor */
+		gpio_enable_interrupt(GPIO_EC_IMU_INT_L);
+	} else {
+		motion_sensor_count = 0;
+		gmr_tablet_switch_disable();
+		/* Base accel is not stuffed, don't allow line to float */
+		gpio_set_flags(GPIO_EC_IMU_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, board_sensors_init, HOOK_PRIO_DEFAULT);
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	switch (get_cbi_ssfc_base_sensor()) {
+	case SSFC_SENSOR_BASE_ICM426XX:
+		icm426xx_interrupt(signal);
+		break;
+	case SSFC_SENSOR_BASE_BMI160:
+	default:
+		bmi160_interrupt(signal);
+		break;
+	}
+}
diff --git a/board/volet/vif_override.xml b/board/volet/vif_override.xml
new file mode 100644
index 0000000000..56d132401e
--- /dev/null
+++ b/board/volet/vif_override.xml
@@ -0,0 +1,158 @@
+<?xml version="1.0" encoding="utf-8"?>
+<vif:VIF xmlns="http://usb.org/VendorInfoFile.xsd">
+  <vif:Model_Part_Number>Voxel</Model_Part_Number>
+  <vif:Product_Revision>0</Product_Revision>
+  <vif:TID>0</TID>
+  <vif:Product>
+    <!-- Information about TGL USB4 provided by Intel. See b/172963736 -->
+    <vif:USB4_Num_Internal_Host_Controllers value="1" />
+    <vif:USB4_Num_PCIe_DN_Bridges value="0" />
+    <vif:USB4RouterList>
+      <vif:Usb4Router>
+        <vif:USB4_Router_ID value="1" />
+        <vif:USB4_Silicon_VID value="32903">8087</USB4_Silicon_VID>
+        <vif:USB4_Num_Lane_Adapters value="4" />
+        <vif:USB4_Num_USB3_DN_Adapters value="1" />
+        <vif:USB4_Num_DP_IN_Adapters value="1" />
+        <vif:USB4_Num_DP_OUT_Adapters value="0" />
+        <vif:USB4_Num_PCIe_DN_Adapters value="4" />
+        <vif:USB4_TBT3_Not_Supported value="0">TBT3 Compatible</USB4_TBT3_Not_Supported>
+        <vif:USB4_PCIe_Wake_Supported value="true" />
+        <vif:USB4_USB3_Wake_Supported value="false" />
+        <vif:USB4_Num_Unused_Adapters value="0" />
+        <vif:USB4_TBT3_VID value="32903">8087</USB4_TBT3_VID>
+        <vif:USB4_PCIe_Switch_Vendor_ID value="32902">8086</USB4_PCIe_Switch_Vendor_ID>
+        <vif:USB4_PCIe_Switch_Device_ID value="39451">9A1B</USB4_PCIe_Switch_Device_ID>
+      </vif:Usb4Router>
+      <vif:Usb4Router>
+        <vif:USB4_Router_ID value="0" />
+        <vif:USB4_Silicon_VID value="32903">8087</USB4_Silicon_VID>
+        <vif:USB4_Num_Lane_Adapters value="2" />
+        <vif:USB4_Num_USB3_DN_Adapters value="1" />
+        <vif:USB4_Num_DP_IN_Adapters value="0" />
+        <vif:USB4_Num_DP_OUT_Adapters value="0" />
+        <vif:USB4_Num_PCIe_DN_Adapters value="0" />
+        <vif:USB4_TBT3_Not_Supported value="1">Not TBT3-Compatible</USB4_TBT3_Not_Supported>
+        <vif:USB4_PCIe_Wake_Supported value="false" />
+        <vif:USB4_USB3_Wake_Supported value="false" />
+        <vif:USB4_Num_Unused_Adapters value="0" />
+      </vif:Usb4Router>
+    </vif:USB4RouterList>
+  </vif:Product>
+  <vif:Component>
+    <vif:USB4_Max_Speed value="1">Gen 3 (40Gb)</USB4_Max_Speed>
+    <vif:USB4_DFP_Supported value="true" />
+    <vif:USB4_UFP_Supported value="false" />
+    <vif:USB4_USB3_Tunneling_Supported value="true" />
+    <vif:USB4_DP_Tunneling_Supported value="true" />
+    <vif:USB4_PCIe_Tunneling_Supported value="true" />
+    <vif:USB4_TBT3_Compatibility_Supported value="true" />
+    <vif:USB4_CL1_State_Supported value="true" />
+    <vif:USB4_CL2_State_Supported value="true" />
+    <vif:USB4_Num_Retimers value="1" />
+    <vif:USB4_DP_Bit_Rate value="3">HBR3</USB4_DP_Bit_Rate>
+    <vif:USB4_Num_DP_Lanes value="4">4 Lanes</USB4_Num_DP_Lanes>
+    <vif:USB4_Lane_0_Adapter value="1" />
+    <vif:Host_Supports_USB_Data value="true" />
+    <vif:Host_Speed value="2">USB 3.2 Gen 2x1</Host_Speed>
+    <vif:Host_Contains_Captive_Retimer value="true" />
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:Host_Suspend_Supported value="true" />
+    <vif:Is_DFP_On_Hub value="false" />
+    <vif:USB_Suspend_May_Be_Cleared value="true" />
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="3">3A @ 5V</FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <vif:FR_Swap_Supported_As_Initial_Sink value="true" />
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!-- Add in missing fields for SrcPdo0, derived from SYV682B datasheet. -->
+        <vif:Src_PD_OCP_OC_Debounce value="50">50 msec</Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="360">3600 mA</Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+    <vif:Data_Capable_As_USB_Host_SOP value="true" />
+    <vif:Data_Capable_As_USB_Device_SOP value="false" />
+    <!-- TODO(b/173028252): Figure out the appropriate Discover Identity ACK for
+         Volteer and update the EC and VIF accordingly. -->
+    <vif:Product_Type_UFP_SOP value="3">PSD</Product_Type_UFP_SOP>
+    <vif:Product_Type_DFP_SOP value="4">Alternate Mode Controller (AMC)</Product_Type_DFP_SOP>
+    <vif:DFP_VDO_Port_Number value="0" />
+    <vif:Modal_Operation_Supported_SOP value="true" />
+    <vif:USB_VID_SOP value="6353">18D1</USB_VID_SOP>
+    <vif:bcdDevice_SOP value="0">0000</bcdDevice_SOP>
+    <vif:SVID_Fixed_SOP value="true" />
+    <vif:Num_SVIDs_Min_SOP value="1" />
+    <vif:Num_SVIDs_Max_SOP value="1" />
+    <vif:SOPSVIDList>
+      <vif:SOPSVID>
+        <vif:SVID_SOP value="32903">8087</SVID_SOP>
+        <vif:SVID_Modes_Fixed_SOP value="true" />
+        <vif:SVID_Num_Modes_Min_SOP value="1" />
+        <vif:SVID_Num_Modes_Max_SOP value="1" />
+        <vif:SOPSVIDModeList>
+          <vif:SOPSVIDMode>
+            <vif:SVID_Mode_Enter_SOP value="true" />
+            <vif:SVID_Mode_Recog_Value_SOP value="0">00000000</SVID_Mode_Recog_Value_SOP>
+          </vif:SOPSVIDMode>
+        </vif:SOPSVIDModeList>
+      </vif:SOPSVID>
+    </vif:SOPSVIDList>
+  </vif:Component>
+  <vif:Component>
+    <vif:USB4_Max_Speed value="1">Gen 3 (40Gb)</USB4_Max_Speed>
+    <vif:USB4_DFP_Supported value="true" />
+    <vif:USB4_UFP_Supported value="false" />
+    <vif:USB4_USB3_Tunneling_Supported value="true" />
+    <vif:USB4_DP_Tunneling_Supported value="true" />
+    <vif:USB4_PCIe_Tunneling_Supported value="true" />
+    <vif:USB4_TBT3_Compatibility_Supported value="true" />
+    <vif:USB4_CL1_State_Supported value="true" />
+    <vif:USB4_CL2_State_Supported value="true" />
+    <vif:USB4_Num_Retimers value="1" />
+    <vif:USB4_DP_Bit_Rate value="3">HBR3</USB4_DP_Bit_Rate>
+    <vif:USB4_Num_DP_Lanes value="4">4 Lanes</USB4_Num_DP_Lanes>
+    <vif:USB4_Lane_0_Adapter value="1" />
+    <vif:Host_Supports_USB_Data value="true" />
+    <vif:Host_Speed value="2">USB 3.2 Gen 2x1</Host_Speed>
+    <vif:Host_Contains_Captive_Retimer value="true" />
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:Host_Suspend_Supported value="true" />
+    <vif:Is_DFP_On_Hub value="false" />
+    <vif:USB_Suspend_May_Be_Cleared value="true" />
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="3">3A @ 5V</FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <vif:FR_Swap_Supported_As_Initial_Sink value="true" />
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!-- Add in missing fields for SrcPdo0, derived from SYV682B datasheet. -->
+        <vif:Src_PD_OCP_OC_Debounce value="50">50 msec</Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="360">3600 mA</Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+    <vif:Data_Capable_As_USB_Host_SOP value="true" />
+    <vif:Data_Capable_As_USB_Device_SOP value="false" />
+    <!-- TODO(b/173028252): Figure out the appropriate Discover Identity ACK for
+         Volteer and update the EC and VIF accordingly. -->
+    <vif:Product_Type_UFP_SOP value="3">PSD</Product_Type_UFP_SOP>
+    <vif:Product_Type_DFP_SOP value="4">Alternate Mode Controller (AMC)</Product_Type_DFP_SOP>
+    <vif:DFP_VDO_Port_Number value="1" />
+    <vif:Modal_Operation_Supported_SOP value="true" />
+    <vif:USB_VID_SOP value="6353">18D1</USB_VID_SOP>
+    <vif:bcdDevice_SOP value="0">0000</bcdDevice_SOP>
+    <vif:SVID_Fixed_SOP value="true" />
+    <vif:Num_SVIDs_Min_SOP value="1" />
+    <vif:Num_SVIDs_Max_SOP value="1" />
+    <vif:SOPSVIDList>
+      <vif:SOPSVID>
+        <vif:SVID_SOP value="32903">8087</SVID_SOP>
+        <vif:SVID_Modes_Fixed_SOP value="true" />
+        <vif:SVID_Num_Modes_Min_SOP value="1" />
+        <vif:SVID_Num_Modes_Max_SOP value="1" />
+        <vif:SOPSVIDModeList>
+          <vif:SOPSVIDMode>
+            <vif:SVID_Mode_Enter_SOP value="true" />
+            <vif:SVID_Mode_Recog_Value_SOP value="0">00000000</SVID_Mode_Recog_Value_SOP>
+          </vif:SOPSVIDMode>
+        </vif:SOPSVIDModeList>
+      </vif:SOPSVID>
+    </vif:SOPSVIDList>
+  </vif:Component>
+</vif:VIF>
diff --git a/board/volmar/battery.c b/board/volmar/battery.c
new file mode 100644
index 0000000000..852ed4b137
--- /dev/null
+++ b/board/volmar/battery.c
@@ -0,0 +1,238 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery.h"
+#include "battery_fuel_gauge.h"
+#include "cbi.h"
+#include "charge_ramp.h"
+#include "charge_state.h"
+#include "charger_profile_override.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "gpio.h"
+/*
+ * Battery info for all Volmar battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	/* COSMX AP20CBL Battery Information */
+	[BATTERY_COSMX_AP20CBL] = {
+		.fuel_gauge = {
+			.manuf_name = "COSMX KT0030B002",
+			.device_name = "AP20CBL",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x2000,
+				.disconnect_val = 0x2000,
+				.cfet_mask = 0x4000,
+				.cfet_off_val = 0x4000,
+			},
+		},
+		.batt_info = {
+			.voltage_max            = 13200,
+			.voltage_normal         = 11550,
+			.voltage_min            = 9000,
+			.precharge_current      = 256,
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 50,
+			.charging_min_c         = 0,
+			.charging_max_c         = 60,
+			.discharging_min_c      = -20,
+			.discharging_max_c      = 75,
+		},
+	},
+	/* COSMX AP20CBL Battery Information (new firmware ver) */
+	[BATTERY_COSMX_AP20CBL_004] = {
+		.fuel_gauge = {
+			.manuf_name = "COSMX KT0030B004",
+			.device_name = "AP20CBL",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x2000,
+				.disconnect_val = 0x2000,
+				.cfet_mask = 0x4000,
+				.cfet_off_val = 0x4000,
+			},
+		},
+		.batt_info = {
+			.voltage_max            = 13200,
+			.voltage_normal         = 11550,
+			.voltage_min            = 9000,
+			.precharge_current      = 256,
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 50,
+			.charging_min_c         = 0,
+			.charging_max_c         = 60,
+			.discharging_min_c      = -20,
+			.discharging_max_c      = 75,
+		},
+	},
+	/* LGC AP18C8K Battery Information */
+	[BATTERY_LGC_AP18C8K] = {
+		.fuel_gauge = {
+			.manuf_name = "LGC KT0030G020",
+			.device_name = "AP18C8K",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.reg_addr = 0x43,
+				.reg_mask = 0x0001,
+				.disconnect_val = 0x0,
+			},
+		},
+		.batt_info = {
+			.voltage_max            = 13050,
+			.voltage_normal         = 11250,
+			.voltage_min            = 9000,
+			.precharge_current      = 256,
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 50,
+			.charging_min_c         = 0,
+			.charging_max_c         = 60,
+			.discharging_min_c      = -20,
+			.discharging_max_c      = 75,
+		},
+	},
+	/* LGC AP19B8M Battery Information */
+	[BATTERY_AP19B8M] = {
+		.fuel_gauge = {
+			.manuf_name = "LGC KT0030G024",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.reg_addr = 0x43,
+				.reg_mask = 0x0001,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0002,
+				.cfet_off_val = 0x0000,
+			}
+		},
+		.batt_info = {
+			.voltage_max          = 13350,
+			.voltage_normal       = 11610,
+			.voltage_min          = 9000,
+			.precharge_current    = 256,
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 50,
+			.charging_min_c       = 0,
+			.charging_max_c       = 60,
+			.discharging_min_c    = -20,
+			.discharging_max_c    = 75,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_COSMX_AP20CBL;
+
+enum battery_present battery_hw_present(void)
+{
+	/* The GPIO is low when the battery is physically present */
+	return gpio_get_level(GPIO_EC_BATT_PRES_ODL) ? BP_NO : BP_YES;
+}
+
+static int charger_should_discharge_on_ac(struct charge_state_data *curr)
+{
+	/* can not discharge on AC without battery */
+	if (curr->batt.is_present != BP_YES)
+		return 0;
+
+	/* Do not discharge when battery disconnect */
+	if (battery_get_disconnect_state() != BATTERY_NOT_DISCONNECTED)
+		return 0;
+
+	/* Do not discharge on AC if the battery is still waking up */
+	if ((curr->batt.flags & BATT_FLAG_BAD_STATUS) ||
+	    (!(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
+	     !(curr->batt.status & STATUS_FULLY_CHARGED)))
+		return 0;
+
+	/*
+	 * In heavy load (>3A being withdrawn from VSYS) the DCDC of the
+	 * charger operates on hybrid mode. This causes a slight voltage
+	 * ripple on VSYS that falls in the audible noise frequency (single
+	 * digit kHz range). This small ripple generates audible noise in
+	 * the output ceramic capacitors (caps on VSYS and any input of
+	 * DCDC under VSYS).
+	 *
+	 * To overcome this issue, force battery discharging when battery
+	 * full, So the battery MOS of NVDC charger will turn on always,
+	 * it make the Vsys same as Vbat and the noise has been improved.
+	 */
+	if (!battery_is_cut_off() &&
+	    !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
+	    (curr->batt.status & STATUS_FULLY_CHARGED))
+		return 1;
+
+	return 0;
+}
+
+/*
+ * This can override the smart battery's charging profile. To make a change,
+ * modify one or more of requested_voltage, requested_current, or state.
+ * Leave everything else unchanged.
+ *
+ * Return the next poll period in usec, or zero to use the default (which is
+ * state dependent).
+ */
+int charger_profile_override(struct charge_state_data *curr)
+{
+	int disch_on_ac = charger_should_discharge_on_ac(curr);
+
+	charger_discharge_on_ac(disch_on_ac);
+
+	if (disch_on_ac) {
+		curr->state = ST_DISCHARGE;
+		return 0;
+	}
+
+	return 0;
+}
+
+enum ec_status charger_profile_override_get_param(uint32_t param,
+						  uint32_t *value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+enum ec_status charger_profile_override_set_param(uint32_t param,
+						  uint32_t value)
+{
+	return EC_RES_INVALID_PARAM;
+}
diff --git a/board/volmar/board.c b/board/volmar/board.c
new file mode 100644
index 0000000000..e87a43a030
--- /dev/null
+++ b/board/volmar/board.c
@@ -0,0 +1,73 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "button.h"
+#include "charge_ramp.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "registers.h"
+#include "switch.h"
+#include "throttle_ap.h"
+#include "usbc_config.h"
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* Console output macros */
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+
+__override void board_cbi_init(void)
+{
+	config_usb_db_type();
+}
+
+/* Called on AP S3 -> S0 transition */
+static void board_chipset_resume(void)
+{
+	/* Allow keyboard backlight to be enabled */
+
+	gpio_set_level(GPIO_EC_KB_BL_EN_L, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S0 -> S3 transition */
+static void board_chipset_suspend(void)
+{
+	/* Turn off the keyboard backlight if it's on. */
+
+	gpio_set_level(GPIO_EC_KB_BL_EN_L, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
+
+/* keyboard factory test */
+#ifdef CONFIG_KEYBOARD_FACTORY_TEST
+/*
+ * We have total 30 pins for keyboard connecter {-1, -1} mean
+ * the N/A pin that don't consider it and reserve index 0 area
+ * that we don't have pin 0.
+ */
+const int keyboard_factory_scan_pins[][2] = {
+	{ -1, -1 }, { 0, 5 },	{ 1, 1 }, { 1, 0 },   { 0, 6 },	  { 0, 7 },
+	{ -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 },   { -1, -1 }, { 1, 6 },
+	{ 1, 7 },   { 3, 1 },	{ 2, 0 }, { 1, 5 },   { 2, 6 },	  { 2, 7 },
+	{ 2, 1 },   { 2, 4 },	{ 2, 5 }, { 1, 2 },   { 2, 3 },	  { 2, 2 },
+	{ 3, 0 },   { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 },	  { -1, -1 },
+	{ -1, -1 },
+};
+
+const int keyboard_factory_scan_pins_used =
+	ARRAY_SIZE(keyboard_factory_scan_pins);
+#endif
diff --git a/board/volmar/board.h b/board/volmar/board.h
new file mode 100644
index 0000000000..12561dc314
--- /dev/null
+++ b/board/volmar/board.h
@@ -0,0 +1,196 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Volmar board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "compile_time_macros.h"
+
+/* Baseboard features */
+#include "baseboard.h"
+
+/*
+ * This will happen automatically on NPCX9 ES2 and later. Do not remove
+ * until we can confirm all earlier chips are out of service.
+ */
+#define CONFIG_HIBERNATE_PSL_VCC1_RST_WAKEUP
+
+#define CONFIG_MP2964
+
+/* Tablet mode is not supported */
+#undef CONFIG_TABLET_MODE
+#undef CONFIG_TABLET_MODE_SWITCH
+#undef CONFIG_LID_ANGLE
+
+/* LED */
+#define CONFIG_LED_ONOFF_STATES
+
+/* USB Type A Features */
+#define USB_PORT_COUNT 1
+#define CONFIG_USB_PORT_POWER_DUMB
+
+/* USB Type C and USB PD defines */
+#undef CONFIG_USB_PD_TCPM_NCT38XX
+#define CONFIG_USB_PD_TCPM_RT1715 /* C0 */
+#define CONFIG_USB_PD_TCPM_PS8815 /* C1 */
+#define CONFIG_USB_PD_TCPM_PS8815_FORCE_DID
+
+/* Retimer */
+#undef CONFIG_USBC_RETIMER_INTEL_BB
+
+/* I2C speed console command */
+#define CONFIG_CMD_I2C_SPEED
+
+/* I2C control host command */
+#define CONFIG_HOSTCMD_I2C_CONTROL
+
+#define CONFIG_USBC_PPC_SYV682X
+
+/* TODO: b/177608416 - measure and check these values on brya */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
+
+/*
+ * Passive USB-C cables only support up to 60W.
+ */
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
+
+#define CONFIG_CHARGER_PROFILE_OVERRIDE
+#define CONFIG_PWR_STATE_DISCHARGE_FULL
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
+
+/*
+ * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
+ * signal.
+ */
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
+
+/* System has back-lit keyboard */
+#define CONFIG_PWM_KBLIGHT
+
+/* I2C Bus Configuration */
+
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+
+#define I2C_PORT_USB_C0_C2_TCPC NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1
+
+#define I2C_PORT_USB_C0_C2_PPC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1
+
+#define I2C_PORT_USB_C0_C2_BC12 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1
+
+#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1
+
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+
+#define I2C_ADDR_MP2964_FLAGS 0x20
+
+/* Thermal features */
+#define CONFIG_THERMISTOR
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_TEMP_SENSOR_POWER
+#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
+
+#define CONFIG_FANS FAN_CH_COUNT
+
+/* Charger defines */
+#define CONFIG_CHARGER_ISL9241
+#define CONFIG_CHARGE_RAMP_SW
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+
+#undef CONFIG_POWER_BUTTON_INIT_TIMEOUT
+#define CONFIG_POWER_BUTTON_INIT_TIMEOUT 2
+
+/* Keyboard */
+#define CONFIG_KEYBOARD_REFRESH_ROW3
+#define CONFIG_KEYBOARD_FACTORY_TEST
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h" /* needed by registers.h */
+#include "registers.h"
+#include "usbc_config.h"
+
+enum adc_channel {
+	ADC_TEMP_SENSOR_1_DDR_SOC,
+	ADC_TEMP_SENSOR_2_FAN,
+	ADC_TEMP_SENSOR_3_CHARGER,
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1_DDR_SOC,
+	TEMP_SENSOR_2_FAN,
+	TEMP_SENSOR_3_CHARGER,
+	TEMP_SENSOR_COUNT
+};
+
+enum battery_type {
+	BATTERY_COSMX_AP20CBL,
+	BATTERY_COSMX_AP20CBL_004,
+	BATTERY_LGC_AP18C8K,
+	BATTERY_AP19B8M,
+	BATTERY_TYPE_COUNT
+};
+
+enum pwm_channel {
+	PWM_CH_KBLIGHT = 0, /* PWM3 */
+	PWM_CH_FAN, /* PWM5 */
+	PWM_CH_COUNT
+};
+
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT };
+
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT };
+
+#ifdef CONFIG_KEYBOARD_FACTORY_TEST
+extern const int keyboard_factory_scan_pins[][2];
+extern const int keyboard_factory_scan_pins_used;
+#endif
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/volmar/build.mk b/board/volmar/build.mk
new file mode 100644
index 0000000000..ed25f9c9aa
--- /dev/null
+++ b/board/volmar/build.mk
@@ -0,0 +1,25 @@
+# -*- makefile -*-
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Volmar board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx9
+CHIP_VARIANT:=npcx9m3f
+BASEBOARD:=brya
+
+board-y=
+board-y+=battery.o
+board-y+=board.o
+board-y+=charger.o
+board-y+=fans.o
+board-y+=fw_config.o
+board-y+=i2c.o
+board-y+=keyboard.o
+board-y+=led.o
+board-y+=pwm.o
+board-y+=sensors.o
+board-y+=usbc_config.o
diff --git a/board/volmar/charger.c b/board/volmar/charger.c
new file mode 100644
index 0000000000..76e2712181
--- /dev/null
+++ b/board/volmar/charger.c
@@ -0,0 +1,80 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/charger/isl9241.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/* Charger Chip Configuration */
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = ISL9241_ADDR_FLAGS,
+		.drv = &isl9241_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CHARGER_NUM);
+
+int board_set_active_charge_port(int port)
+{
+	int is_valid_port = board_is_usb_pd_port_present(port);
+	int i;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTSUSB("Disabling all charger ports");
+
+		/* Disable all ports. */
+		for (i = 0; i < ppc_cnt; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (ppc_vbus_sink_enable(i, 0))
+				CPRINTSUSB("Disabling C%d as sink failed.", i);
+		}
+
+		return EC_SUCCESS;
+	} else if (!is_valid_port) {
+		return EC_ERROR_INVAL;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (ppc_is_sourcing_vbus(port)) {
+		CPRINTFUSB("Skip enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTSUSB("New charge port: C%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < ppc_cnt; i++) {
+		if (i == port)
+			continue;
+
+		if (ppc_vbus_sink_enable(i, 0))
+			CPRINTSUSB("C%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTSUSB("C%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/board/volmar/ec.tasklist b/board/volmar/ec.tasklist
new file mode 100644
index 0000000000..70b64bc757
--- /dev/null
+++ b/board/volmar/ec.tasklist
@@ -0,0 +1,29 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ *
+ * USB_CHG_Px tasks must be contiguous (see USB_CHG_PORT_TO_TASK_ID(x)).
+ * PD_Cx tasks must be contiguous (see PD_PORT_TO_TASK_ID(x))
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, HOOKS_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, BASEBOARD_CHG_RAMP_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, BASEBOARD_CHARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, BASEBOARD_CHIPSET_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, CONSOLE_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, BASEBOARD_POWERBTN_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_shared_alert_task, (BIT(2) | BIT(0)), BASEBOARD_PD_INT_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, BASEBOARD_PD_INT_TASK_STACK_SIZE)
diff --git a/board/volmar/fans.c b/board/volmar/fans.c
new file mode 100644
index 0000000000..6b87f9cba3
--- /dev/null
+++ b/board/volmar/fans.c
@@ -0,0 +1,89 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Physical fans. These are logically separate from pwm_channels. */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "fan.h"
+#include "fan_chip.h"
+#include "hooks.h"
+#include "pwm.h"
+
+/* MFT channels. These are logically separate from pwm_channels. */
+const struct mft_t mft_channels[] = {
+	[MFT_CH_0] = {
+		.module = NPCX_MFT_MODULE_1,
+		.clk_src = TCKC_LFCLK,
+		.pwm_id = PWM_CH_FAN,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
+
+static const struct fan_conf fan_conf_0 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
+	.pgood_gpio = -1,
+	.enable_gpio = GPIO_EN_PP5000_FAN,
+};
+
+/*
+ * TOOD(b/181271666): thermistor placement and calibration
+ *
+ * Prototype fan spins at about 4200 RPM at 100% PWM, this
+ * is specific to board ID 2 and might also apears in later
+ * boards as well.
+ */
+static const struct fan_rpm fan_rpm_0 = {
+	.rpm_min = 3000,
+	.rpm_start = 3000,
+	.rpm_max = 6000,
+};
+
+const struct fan_t fans[FAN_CH_COUNT] = {
+	[FAN_CH_0] = {
+		.conf = &fan_conf_0,
+		.rpm = &fan_rpm_0,
+	},
+};
+
+#ifndef CONFIG_FANS
+
+/*
+ * TODO(b/181271666): use static fan speeds until fan and sensors are
+ * tuned. for now, use:
+ *
+ *   AP off:  33%
+ *   AP  on: 100%
+ */
+
+static void fan_slow(void)
+{
+	const int duty_pct = 33;
+
+	ccprints("%s: speed %d%%", __func__, duty_pct);
+
+	pwm_enable(PWM_CH_FAN, 1);
+	pwm_set_duty(PWM_CH_FAN, duty_pct);
+}
+
+static void fan_max(void)
+{
+	const int duty_pct = 100;
+
+	ccprints("%s: speed %d%%", __func__, duty_pct);
+
+	pwm_enable(PWM_CH_FAN, 1);
+	pwm_set_duty(PWM_CH_FAN, duty_pct);
+}
+
+DECLARE_HOOK(HOOK_INIT, fan_slow, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, fan_slow, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, fan_slow, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_RESET, fan_max, HOOK_PRIO_FIRST);
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, fan_max, HOOK_PRIO_DEFAULT);
+
+#endif /* CONFIG_FANS */
diff --git a/board/volmar/fw_config.c b/board/volmar/fw_config.c
new file mode 100644
index 0000000000..5c62ed17b8
--- /dev/null
+++ b/board/volmar/fw_config.c
@@ -0,0 +1,61 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "fw_config.h"
+
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
+
+static union volmar_cbi_fw_config fw_config;
+BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
+
+/*
+ * FW_CONFIG defaults for volmar if the CBI.FW_CONFIG data is not
+ * initialized.
+ */
+static const union volmar_cbi_fw_config fw_config_defaults = {
+	.usb_db = DB_USB3_PS8815,
+	.kb_bl = KEYBOARD_BACKLIGHT_ENABLED,
+};
+
+/****************************************************************************
+ * Volmar FW_CONFIG access
+ */
+void board_init_fw_config(void)
+{
+	if (cbi_get_fw_config(&fw_config.raw_value)) {
+		CPRINTS("CBI: Read FW_CONFIG failed, using board defaults");
+		fw_config = fw_config_defaults;
+	}
+
+	if (get_board_id() == 0) {
+		/*
+		 * Early boards have a zero'd out FW_CONFIG, so replace
+		 * it with a sensible default value. If DB_USB_ABSENT2
+		 * was used as an alternate encoding of DB_USB_ABSENT to
+		 * avoid the zero check, then fix it.
+		 */
+		if (fw_config.raw_value == 0) {
+			CPRINTS("CBI: FW_CONFIG is zero, using board defaults");
+			fw_config = fw_config_defaults;
+		} else if (fw_config.usb_db == DB_USB_ABSENT2) {
+			fw_config.usb_db = DB_USB_ABSENT;
+		}
+	}
+}
+
+union volmar_cbi_fw_config get_fw_config(void)
+{
+	return fw_config;
+}
+
+enum ec_cfg_usb_db_type ec_cfg_usb_db_type(void)
+{
+	return fw_config.usb_db;
+}
diff --git a/board/volmar/fw_config.h b/board/volmar/fw_config.h
new file mode 100644
index 0000000000..4dddec9273
--- /dev/null
+++ b/board/volmar/fw_config.h
@@ -0,0 +1,54 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __BOARD_VOLMAR_FW_CONFIG_H_
+#define __BOARD_VOLMAR_FW_CONFIG_H_
+
+#include <stdint.h>
+
+/****************************************************************************
+ * CBI FW_CONFIG layout for Volmar board.
+ *
+ * Source of truth is the project/brya/volmar/config.star configuration file.
+ */
+
+enum ec_cfg_usb_db_type {
+	DB_USB_ABSENT = 0,
+	DB_USB3_PS8815 = 1,
+	DB_USB_ABSENT2 = 15
+};
+
+enum ec_cfg_keyboard_backlight_type {
+	KEYBOARD_BACKLIGHT_DISABLED = 0,
+	KEYBOARD_BACKLIGHT_ENABLED = 1
+};
+
+union volmar_cbi_fw_config {
+	struct {
+		enum ec_cfg_usb_db_type usb_db : 4;
+		enum ec_cfg_keyboard_backlight_type kb_bl : 1;
+		uint32_t audio : 3;
+		uint32_t boot_nvme_mask : 1;
+		uint32_t boot_emmc_mask : 1;
+		uint32_t reserved_1 : 22;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Read the cached FW_CONFIG.  Guaranteed to have valid values.
+ *
+ * @return the FW_CONFIG for the board.
+ */
+union volmar_cbi_fw_config get_fw_config(void);
+
+/**
+ * Get the USB daughter board type from FW_CONFIG.
+ *
+ * @return the USB daughter board type.
+ */
+enum ec_cfg_usb_db_type ec_cfg_usb_db_type(void);
+
+#endif /* __BOARD_VOLMAR_FW_CONFIG_H_ */
diff --git a/board/volmar/gpio.inc b/board/volmar/gpio.inc
new file mode 100644
index 0000000000..b1d4e8c3dc
--- /dev/null
+++ b/board/volmar/gpio.inc
@@ -0,0 +1,141 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define MODULE_KB		MODULE_KEYBOARD_SCAN
+
+/* INTERRUPT GPIOs: */
+GPIO_INT(ACOK_OD,                        PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
+GPIO_INT(EC_PROCHOT_IN_L,                PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
+GPIO_INT(EC_VOLDN_BTN_ODL,               PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(EC_VOLUP_BTN_ODL,               PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(EC_WP_ODL,                      PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(GSC_EC_PWR_BTN_ODL,             PIN(0, 1), GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW, power_button_interrupt)
+GPIO_INT(LID_OPEN,                       PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
+GPIO_INT(SEQ_EC_ALL_SYS_PG,              PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_DSW_PWROK,               PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_RSMRST_ODL,              PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,                       PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,                      PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SYS_SLP_S0IX_L,                 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(USB_C0_BC12_INT_ODL,            PIN(C, 6), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C0_C2_TCPC_INT_ODL,         PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C0_PPC_INT_ODL,             PIN(6, 2), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C1_BC12_INT_ODL,            PIN(5, 0), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C1_PPC_INT_ODL,             PIN(F, 5), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C1_TCPC_INT_ODL,            PIN(A, 2), GPIO_INT_FALLING, tcpc_alert_event)
+
+/* USED GPIOs: */
+GPIO(CCD_MODE_ODL,                   PIN(E, 5), GPIO_INPUT)
+GPIO(CHARGER_VAP_OTG_EN,             PIN(7, 3), GPIO_OUT_LOW)
+GPIO(CPU_C10_GATE_L,                 PIN(6, 7), GPIO_INPUT)
+GPIO(EC_BATT_PRES_ODL,               PIN(A, 3), GPIO_INPUT)
+GPIO(EC_ENTERING_RW,                 PIN(0, 3), GPIO_OUT_LOW)
+GPIO(EC_EN_EDP_BL,                   PIN(D, 3), GPIO_OUT_HIGH)
+GPIO(EC_GSC_PACKET_MODE,             PIN(7, 5), GPIO_OUT_LOW)
+GPIO(EC_I2C_BAT_SCL,                 PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_BAT_SDA,                 PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SCL_R,              PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SDA_R,              PIN(B, 2), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,              PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SENSOR_SDA,              PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_USB_C0_C2_PPC_BC_SCL,    PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_PPC_BC_SDA,    PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_TCPC_SCL,      PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_TCPC_SDA,      PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_MIX_SCL,          PIN(E, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_MIX_SDA,          PIN(E, 3), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_TCPC_SCL,         PIN(F, 3), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_TCPC_SDA,         PIN(F, 2), GPIO_INPUT)
+GPIO(EC_KB_BL_EN_L,                  PIN(8, 6), GPIO_OUT_HIGH)
+GPIO(EC_PCHHOT_ODL,                  PIN(7, 4), GPIO_INPUT)
+GPIO(EC_PCH_INT_ODL,                 PIN(B, 0), GPIO_ODR_HIGH)
+GPIO(EC_PCH_PWR_BTN_ODL,             PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(EC_PCH_RSMRST_L,                PIN(A, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_RTCRST,                  PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_SYS_PWROK,               PIN(3, 7), GPIO_OUT_LOW)
+GPIO(EC_PCH_WAKE_R_ODL,              PIN(C, 0), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_ODL,                 PIN(6, 3), GPIO_ODR_HIGH)
+GPIO(EN_PP5000_FAN,                  PIN(6, 1), GPIO_OUT_HIGH)
+GPIO(EN_PP5000_USBA_R,               PIN(D, 7), GPIO_OUT_LOW)
+GPIO(EN_S5_RAILS,                    PIN(B, 6), GPIO_OUT_LOW)
+GPIO(IMVP9_VRRDY_OD,                 PIN(4, 3), GPIO_INPUT)
+GPIO(PCH_PWROK,                      PIN(7, 2), GPIO_OUT_LOW)
+GPIO(SYS_RST_ODL,                    PIN(C, 5), GPIO_ODR_HIGH)
+GPIO(USB_C0_C2_TCPC_RST_ODL,         PIN(A, 7), GPIO_ODR_LOW)
+GPIO(USB_C1_FRS_EN,                  PIN(9, 4), GPIO_OUT_LOW)
+GPIO(USB_C1_RST_ODL,                 PIN(9, 6), GPIO_ODR_LOW)
+GPIO(USB_C1_RT_INT_ODL,              PIN(A, 0), GPIO_INPUT)
+GPIO(USB_C1_RT_RST_R_ODL,            PIN(0, 2), GPIO_ODR_LOW)
+GPIO(VCCST_PWRGD_OD,                 PIN(A, 4), GPIO_ODR_LOW)
+GPIO(LED_1_L,                        PIN(C, 4), GPIO_OUT_HIGH)
+GPIO(LED_2_L,                        PIN(C, 3), GPIO_OUT_HIGH)
+
+/* UART alternate functions */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)              /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */
+
+/* I2C alternate functions */
+ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)               /* GPIO33/I2C5_SCL0/CTS_L, GPIO36/RTS_L/I2C5_SDA0 */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)               /* GPIO87/I2C1_SDA0 */
+ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)               /* GPIO92/I2C2_SCL0, GPIO91/I2C2_SDA0, GPIO90/I2C1_SCL0 */
+ALTERNATE(PIN_MASK(B, 0x0c), 0, MODULE_I2C, 0)               /* GPIOB3/I2C7_SCL0/DCD_L, GPIOB2/I2C7_SDA0/DSR_L */
+ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, GPIO_SEL_1P8V)   /* GPIOB5/I2C0_SCL0, GPIOB4/I2C0_SDA0 */
+ALTERNATE(PIN_MASK(E, 0x18), 0, MODULE_I2C, 0)               /* GPIOE4/I2C6_SCL1/I3C_SCL, GPIOE3/I2C6_SDA1/I3C_SDA */
+ALTERNATE(PIN_MASK(F, 0x0c), 0, MODULE_I2C, 0)               /* GPIOF3/I2C4_SCL1, GPIOF2/I2C4_SDA1 */
+
+/* PWM alternate functions */
+ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0)               /* GPIO40/TA1 */
+ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)               /* GPIO80/PWM3 */
+ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)               /* GPIOB7/PWM5 */
+
+/* ADC alternate functions */
+ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0)               /* GPIO34/PS2_DAT2/ADC6 */
+ALTERNATE(PIN_MASK(4, 0x34), 0, MODULE_ADC, 0)               /* GPIO42/ADC3/RI_L, GPIO45/ADC0, GPIO44/ADC1 */
+
+/* KB alternate functions */
+ALTERNATE(PIN_MASK(0, 0xf0), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO10&P80_CLK/GPIO07, KSO11&P80_DAT/GPIO06, KSO12/GPIO05, KSO13/GPIO04 */
+ALTERNATE(PIN_MASK(1, 0x7f), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO06/GPO13/GP_SEL_L, KSO07/GPO12/JEN_L, KSO03/GPIO16/JTAG_TDO0_SWO, KSO04/GPIO15/XNOR, KSO05/GPIO14, KSO08/GPIO11/CR_SOUT1, KSO09/GPIO10/CR_SIN1 */
+ALTERNATE(PIN_MASK(2, 0xfc), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI2/GPIO27/TRACEDATA1, KSI3/GPIO26/TRACEDATA0, KSI4/GPIO25/TRACECLK/GP_SCLK, KSI5/GPIO24/GP_MISO, KSI6/GPIO23/S_SBUB, KSI7/GPIO22/S_SBUA */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO00/GPIO21/JTAG_TCK_SWCLK, KSO01/GPIO20/JTAG_TMS_SWIO */
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI0/GPIO31/TRACEDATA3/GP_MOSI, KSI1/GPIO30/TRACEDATA2/GP_CS_L */
+ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO14/GPIO82 */
+
+/* PMU alternate functions */
+ALTERNATE(PIN_MASK(0, 0x01), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN2_L&GPI00/GPIO00 */
+ALTERNATE(PIN_MASK(0, 0x02), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW) /* GPIO01/PSL_IN3_L&GPI01 */
+ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN1_L&GPID2/GPIOD2 */
+
+/* Unused Pins */
+UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
+UNUSED(PIN(3, 2))       /* GPO32/TRIS_L */
+UNUSED(PIN(3, 4))       /* GPIO34 */
+UNUSED(PIN(3, 5))       /* GPO35/CR_SOUT4/TEST_L */
+UNUSED(PIN(6, 6))       /* GPIO66 */
+UNUSED(PIN(5, 7))       /* GPIO57/SER_IRQ/ESPI_ALERT_L */
+UNUSED(PIN(8, 3))       /* GPIO83 */
+UNUSED(PIN(7, 0))       /* GPIO70 */
+UNUSED(PIN(4, 1))       /* GPIO41 */
+UNUSED(PIN(8, 1))       /* GPIO81 */
+UNUSED(PIN(5, 6))       /* GPIO56 */
+UNUSED(PIN(B, 1))       /* GPIOB1 */
+UNUSED(PIN(D, 0))       /* GPIOD0/I2C3_SDA0 */
+UNUSED(PIN(D, 1))       /* GPIOD1/I2C3_SCL0 */
+UNUSED(PIN(9, 5))       /* GPIO95 */
+
+/* Pre-configured PSL balls:  J8  K6 */
+
+/*
+ * The NPCX keyboard driver does not use named GPIOs to access
+ * keyboard scan pins, so we do not list them in *gpio.inc. However, when
+ * KEYBOARD_COL2_INVERTED is defined, this name is required.
+ */
+GPIO(EC_KSO_02_INV,               PIN(1, 7), GPIO_OUT_LOW)
+
+GPIO(USB_C0_OC_ODL,     PIN(D, 4), GPIO_ODR_HIGH)
+GPIO(USB_C0_FRS_EN,     PIN(6, 0), GPIO_OUT_LOW)
+GPIO(USB_C0_RT_RST_ODL, PIN(C, 2), GPIO_ODR_LOW)
+
+GPIO(USB_C1_OC_ODL,     PIN(E, 1), GPIO_ODR_HIGH)
diff --git a/board/volmar/i2c.c b/board/volmar/i2c.c
new file mode 100644
index 0000000000..29dd2904c1
--- /dev/null
+++ b/board/volmar/i2c.c
@@ -0,0 +1,73 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "hooks.h"
+#include "i2c.h"
+
+#define BOARD_ID_FAST_PLUS_CAPABLE 2
+
+/* I2C port map configuration */
+const struct i2c_port_t i2c_ports[] = {
+	{
+		/* I2C0 */
+		.name = "sensor",
+		.port = I2C_PORT_SENSOR,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_SENSOR_SCL,
+		.sda = GPIO_EC_I2C_SENSOR_SDA,
+	},
+	{
+		/* I2C1 */
+		.name = "tcpc0,2",
+		.port = I2C_PORT_USB_C0_C2_TCPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C2_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C2_TCPC_SDA,
+	},
+	{
+		/* I2C2 */
+		.name = "ppc0,2",
+		.port = I2C_PORT_USB_C0_C2_PPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C2_PPC_BC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C2_PPC_BC_SDA,
+	},
+	{
+		/* I2C4 C1 TCPC */
+		.name = "tcpc1",
+		.port = I2C_PORT_USB_C1_TCPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C1_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C1_TCPC_SDA,
+		.flags = I2C_PORT_FLAG_DYNAMIC_SPEED,
+	},
+	{
+		/* I2C5 */
+		.name = "battery",
+		.port = I2C_PORT_BATTERY,
+		.kbps = 100,
+		.scl = GPIO_EC_I2C_BAT_SCL,
+		.sda = GPIO_EC_I2C_BAT_SDA,
+	},
+	{
+		/* I2C6 */
+		.name = "ppc1",
+		.port = I2C_PORT_USB_C1_PPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C1_MIX_SCL,
+		.sda = GPIO_EC_I2C_USB_C1_MIX_SDA,
+	},
+	{
+		/* I2C7 */
+		.name = "eeprom",
+		.port = I2C_PORT_EEPROM,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_MISC_SCL_R,
+		.sda = GPIO_EC_I2C_MISC_SDA_R,
+	},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/board/volmar/keyboard.c b/board/volmar/keyboard.c
new file mode 100644
index 0000000000..16857b53c9
--- /dev/null
+++ b/board/volmar/keyboard.c
@@ -0,0 +1,47 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "ec_commands.h"
+#include "keyboard_scan.h"
+#include "timer.h"
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/* Increase from 50 us, because KSO_02 passes through the H1. */
+	.output_settle_us = 80,
+	/* Other values should be the same as the default configuration. */
+	.debounce_down_us = 9 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
+		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
+	},
+};
+
+static const struct ec_response_keybd_config volmar_kb = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &volmar_kb;
+}
diff --git a/board/volmar/led.c b/board/volmar/led.c
new file mode 100644
index 0000000000..11b1cced9e
--- /dev/null
+++ b/board/volmar/led.c
@@ -0,0 +1,87 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ * Power and battery LED control for volmar
+ */
+
+#include "chipset.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+
+#define LED_ON_LVL 0
+#define LED_OFF_LVL 1
+
+#define GPIO_LED_BLUE_L GPIO_LED_1_L
+#define GPIO_LED_AMBER_L GPIO_LED_2_L
+
+__override const int led_charge_lvl_1 = 5;
+
+__override const int led_charge_lvl_2 = 95;
+
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_AMBER:
+		gpio_set_level(GPIO_LED_AMBER_L, LED_ON_LVL);
+		gpio_set_level(GPIO_LED_BLUE_L, LED_OFF_LVL);
+		break;
+	case EC_LED_COLOR_BLUE:
+		gpio_set_level(GPIO_LED_BLUE_L, LED_ON_LVL);
+		gpio_set_level(GPIO_LED_AMBER_L, LED_OFF_LVL);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		gpio_set_level(GPIO_LED_BLUE_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_AMBER_L, LED_OFF_LVL);
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		brightness_range[EC_LED_COLOR_BLUE] = 1;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(EC_LED_COLOR_AMBER);
+		else if (brightness[EC_LED_COLOR_BLUE] != 0)
+			led_set_color_battery(EC_LED_COLOR_BLUE);
+		else
+			led_set_color_battery(LED_OFF);
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/board/volmar/pwm.c b/board/volmar/pwm.c
new file mode 100644
index 0000000000..33622559a1
--- /dev/null
+++ b/board/volmar/pwm.c
@@ -0,0 +1,40 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "hooks.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_KBLIGHT] = {
+		.channel = 3,
+		.flags = 0,
+		/*
+		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
+		 * flicker. Higher frequencies consume similar average power to
+		 * lower PWM frequencies, but higher frequencies record a much
+		 * lower maximum power.
+		 */
+		.freq = 2400,
+	},
+	[PWM_CH_FAN] = {
+		.channel = 5,
+		.flags = PWM_CONFIG_OPEN_DRAIN,
+		.freq = 25000
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+static void board_pwm_init(void)
+{
+	/*
+	 * Turn on the fan at 50%.
+	 */
+	pwm_enable(PWM_CH_KBLIGHT, 1);
+	pwm_set_duty(PWM_CH_KBLIGHT, 50);
+}
+DECLARE_HOOK(HOOK_INIT, board_pwm_init, HOOK_PRIO_DEFAULT);
diff --git a/board/volmar/sensors.c b/board/volmar/sensors.c
new file mode 100644
index 0000000000..1a0a5f8398
--- /dev/null
+++ b/board/volmar/sensors.c
@@ -0,0 +1,152 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc.h"
+#include "common.h"
+#include "hooks.h"
+#include "motion_sense.h"
+#include "temp_sensor.h"
+#include "temp_sensor/thermistor.h"
+#include "thermal.h"
+
+/* ADC configuration */
+const struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_1_DDR_SOC] = {
+		.name = "TEMP_DDR_SOC",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_2_FAN] = {
+		.name = "TEMP_FAN",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_3_CHARGER] = {
+		.name = "TEMP_CHARGER",
+		.input_ch = NPCX_ADC_CH6,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* Temperature sensor configuration */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1_DDR_SOC] = {
+		.name = "DDR and SOC",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_1_DDR_SOC,
+	},
+	[TEMP_SENSOR_2_FAN] = {
+		.name = "FAN",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_2_FAN,
+	},
+	[TEMP_SENSOR_3_CHARGER] = {
+		.name = "CHARGER",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = ADC_TEMP_SENSOR_3_CHARGER,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/*
+ * TODO(b/180681346): update for Alder Lake/brya
+ *
+ * Alder Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
+ * 130 C.  However, sensor is located next to DDR, so we need to use the lower
+ * DDR temperature limit (85 C)
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(85), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
+		}, \
+		.temp_fan_off = C_TO_K(30), \
+		.temp_fan_max = C_TO_K(84), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
+
+/*
+ * TODO(b/180681346): update for Alder Lake/brya
+ *
+ * Inductor limits - used for both charger and PP3300 regulator
+ *
+ * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
+ *
+ * Charger max recommended temperature 100C, max absolute temperature 125C
+ * PP3300 regulator: operating range -40 C to 145 C
+ *
+ * Inductors: limit of 125c
+ * PCB: limit is 85c
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_FAN              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = 0, \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = 0, \
+		}, \
+		.temp_fan_off = 0, \
+		.temp_fan_max = 0, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_fan = THERMAL_FAN;
+
+/*
+ * Inductor limits - used for both charger and PP3300 regulator
+ *
+ * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
+ *
+ * Charger max recommended temperature 125C, max absolute temperature 150C
+ * PP3300 regulator: operating range -40 C to 125 C
+ *
+ * Inductors: limit of 125c
+ * PCB: limit is 85c
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CHARGER          \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = 0, \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = 0, \
+		}, \
+		.temp_fan_off = 0, \
+		.temp_fan_max = 0, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_charger =
+	THERMAL_CHARGER;
+
+/* this should really be "const" */
+struct ec_thermal_config thermal_params[] = {
+	[TEMP_SENSOR_1_DDR_SOC] = THERMAL_CPU,
+	[TEMP_SENSOR_2_FAN] = THERMAL_FAN,
+	[TEMP_SENSOR_3_CHARGER] = THERMAL_CHARGER,
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
diff --git a/board/volmar/usbc_config.c b/board/volmar/usbc_config.c
new file mode 100644
index 0000000000..8357dfa690
--- /dev/null
+++ b/board/volmar/usbc_config.c
@@ -0,0 +1,312 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi.h"
+#include "charge_ramp.h"
+#include "charger.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/bc12/pi3usb9201_public.h"
+#include "driver/ppc/syv682x_public.h"
+#include "driver/tcpm/ps8xxx_public.h"
+#include "driver/tcpm/rt1715.h"
+#include "driver/tcpm/tcpci.h"
+#include "ec_commands.h"
+#include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "ioexpander.h"
+#include "system.h"
+#include "task.h"
+#include "task_id.h"
+#include "timer.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+/* USBC TCPC configuration */
+const struct tcpc_config_t tcpc_config[] = {
+	[USBC_PORT_C0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0_C2_TCPC,
+			.addr_flags = RT1715_I2C_ADDR_FLAGS,
+		},
+		.drv = &rt1715_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
+			 TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V,
+	},
+	[USBC_PORT_C1] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C1_TCPC,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
+			 TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
+BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
+
+/******************************************************************************/
+/* USB-A charging control */
+
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_PP5000_USBA_R,
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
+
+/******************************************************************************/
+
+/* USBC PPC configuration */
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_C2_PPC,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.drv = &syv682x_drv,
+	},
+	[USBC_PORT_C1] = {
+		/* Compatible with Silicon Mitus SM536A0 */
+		.i2c_port = I2C_PORT_USB_C1_PPC,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.drv = &syv682x_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
+
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/*
+ * USB3 DB mux configuration - the top level mux still needs to be set
+ * to the virtual_usb_mux_driver so the AP gets notified of mux changes
+ * and updates the TCSS configuration on state changes.
+ */
+static const struct usb_mux_chain usbc1_usb3_db_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
+};
+
+const struct usb_mux_chain usb_muxes[] = {
+	[USBC_PORT_C0] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+	},
+	[USBC_PORT_C1] = {
+		.mux = &(const struct usb_mux) {
+			/* PS8815 DB */
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc1_usb3_db_retimer,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
+
+/* BC1.2 charger detect configuration */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_C2_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C1_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
+
+#ifdef CONFIG_CHARGE_RAMP_SW
+
+/*
+ * TODO(b/181508008): tune this threshold
+ */
+
+#define BC12_MIN_VOLTAGE 4400
+
+/**
+ * Return true if VBUS is too low
+ */
+int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
+{
+	int voltage;
+
+	if (charger_get_vbus_voltage(port, &voltage))
+		voltage = 0;
+
+	if (voltage == 0) {
+		CPRINTS("%s: must be disconnected", __func__);
+		return 1;
+	}
+
+	if (voltage < BC12_MIN_VOLTAGE) {
+		CPRINTS("%s: port %d: vbus %d lower than %d", __func__, port,
+			voltage, BC12_MIN_VOLTAGE);
+		return 1;
+	}
+
+	return 0;
+}
+
+#endif /* CONFIG_CHARGE_RAMP_SW */
+
+void config_usb_db_type(void)
+{
+	enum ec_cfg_usb_db_type db_type = ec_cfg_usb_db_type();
+
+	/*
+	 * TODO(b/180434685): implement multiple DB types
+	 */
+
+	CPRINTS("Configured USB DB type number is %d", db_type);
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * TODO(b/179648104): figure out correct timing
+	 */
+
+	gpio_set_level(GPIO_USB_C0_RT_RST_ODL, 0);
+	gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 0);
+
+	/*
+	 * delay for power-on to reset-off and min. assertion time
+	 */
+
+	msleep(20);
+
+	gpio_set_level(GPIO_USB_C0_RT_RST_ODL, 1);
+	gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 1);
+
+	/* wait for chips to come up */
+
+	msleep(50);
+}
+
+static void board_tcpc_init(void)
+{
+	/* Don't reset TCPCs after initial reset */
+	if (!system_jumped_late())
+		board_reset_pd_mcu();
+
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_C2_TCPC_INT_ODL);
+
+	/* Enable BC1.2 interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
+
+	if (ec_cfg_usb_db_type() != DB_USB_ABSENT) {
+		gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
+		gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
+		gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (gpio_get_level(GPIO_USB_C0_C2_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_0 | PD_STATUS_TCPC_ALERT_2;
+
+	if ((ec_cfg_usb_db_type() != DB_USB_ABSENT) &&
+	    gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
+
+int ppc_get_alert_status(int port)
+{
+	if (port == USBC_PORT_C0)
+		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
+	else if ((port == USBC_PORT_C1) &&
+		 (ec_cfg_usb_db_type() != DB_USB_ABSENT))
+		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
+	return 0;
+}
+
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_C2_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_TCPC_INT_ODL:
+		if (ec_cfg_usb_db_type() == DB_USB_ABSENT)
+			break;
+		schedule_deferred_pd_interrupt(USBC_PORT_C1);
+		break;
+	default:
+		break;
+	}
+}
+
+void bc12_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_BC12_INT_ODL:
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+		break;
+	case GPIO_USB_C1_BC12_INT_ODL:
+		if (ec_cfg_usb_db_type() == DB_USB_ABSENT)
+			break;
+		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+		break;
+	default:
+		break;
+	}
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_PPC_INT_ODL:
+		switch (ec_cfg_usb_db_type()) {
+		case DB_USB_ABSENT:
+		case DB_USB_ABSENT2:
+			break;
+		case DB_USB3_PS8815:
+			syv682x_interrupt(USBC_PORT_C1);
+			break;
+		}
+		break;
+	default:
+		break;
+	}
+}
+
+__override bool board_is_dts_port(int port)
+{
+	return port == USBC_PORT_C0;
+}
diff --git a/board/volmar/usbc_config.h b/board/volmar/usbc_config.h
new file mode 100644
index 0000000000..0722d00d6b
--- /dev/null
+++ b/board/volmar/usbc_config.h
@@ -0,0 +1,17 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Volmar board-specific USB-C configuration */
+
+#ifndef __CROS_EC_USBC_CONFIG_H
+#define __CROS_EC_USBC_CONFIG_H
+
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
+
+void config_usb_db_type(void);
+
+#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/volmar/vif_override.xml b/board/volmar/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/volmar/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/volteer/battery.c b/board/volteer/battery.c
index 1c24e1ec24..31cb7faaf9 100644
--- a/board/volteer/battery.c
+++ b/board/volteer/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/volteer/board.c b/board/volteer/board.c
index b8314d8a01..f8363ea4d7 100644
--- a/board/volteer/board.c
+++ b/board/volteer/board.c
@@ -1,32 +1,24 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Volteer board-specific configuration */
-#include "bb_retimer.h"
-#include "button.h"
-#include "common.h"
 #include "accelgyro.h"
+#include "button.h"
 #include "cbi_ec_fw_config.h"
+#include "common.h"
 #include "driver/accel_bma2x2.h"
 #include "driver/accelgyro_bmi260.h"
 #include "driver/als_tcs3400.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/ppc/syv682x.h"
-#include "driver/retimer/bb_retimer.h"
+#include "driver/retimer/bb_retimer_public.h"
 #include "driver/sync.h"
 #include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/rt1715.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/tusb422.h"
 #include "extpower.h"
 #include "fan.h"
 #include "fan_chip.h"
 #include "gpio.h"
 #include "hooks.h"
-#include "keyboard_raw.h"
 #include "keyboard_scan.h"
 #include "lid_switch.h"
 #include "power.h"
@@ -35,23 +27,25 @@
 #include "pwm_chip.h"
 #include "switch.h"
 #include "system.h"
-#include "task.h"
 #include "tablet_mode.h"
+#include "task.h"
 #include "throttle_ap.h"
+#include "timer.h"
 #include "uart.h"
-#include "usb_mux.h"
 #include "usb_pd.h"
 #include "usb_pd_tbt.h"
 #include "usb_pd_tcpm.h"
-#include "usbc_ppc.h"
 #include "util.h"
 
-#include "gpio_list.h" /* Must come after other header files. */
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+/* Disable debug messages to save flash space */
+#define CPRINTS(format, args...)
 
+/******************************************************************************/
 /* Keyboard scan setting */
-struct keyboard_scan_config keyscan_config = {
+__override struct keyboard_scan_config keyscan_config = {
 	/* Increase from 50 us, because KSO_02 passes through the H1. */
 	.output_settle_us = 80,
 	/* Other values should be the same as the default configuration. */
@@ -66,69 +60,12 @@ struct keyboard_scan_config keyscan_config = {
 	},
 };
 
-/******************************************************************************/
-/*
- * FW_CONFIG defaults for Volteer if the CBI data is not initialized.
- */
-union volteer_cbi_fw_config fw_config_defaults = {
-	.usb_db = DB_USB4_GEN2,
-};
-
-static void board_init(void)
-{
-	/* Illuminate motherboard and daughter board LEDs equally to start. */
-	pwm_enable(PWM_CH_LED4_SIDESEL, 1);
-	pwm_set_duty(PWM_CH_LED4_SIDESEL, 50);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-__override enum tbt_compat_cable_speed board_get_max_tbt_speed(int port)
-{
-	enum ec_cfg_usb_db_type usb_db = ec_cfg_usb_db_type();
-
-	if (port == USBC_PORT_C1) {
-		if (usb_db == DB_USB4_GEN2) {
-			/*
-			 * Older boards violate 205mm trace length prior
-			 * to connection to the re-timer and only support up
-			 * to GEN2 speeds.
-			 */
-			return TBT_SS_U32_GEN1_GEN2;
-		} else if (usb_db == DB_USB4_GEN3) {
-			return TBT_SS_TBT_GEN3;
-		}
-	}
-
-	/*
-	 * Thunderbolt-compatible mode not supported
-	 *
-	 * TODO (b/147726366): All the USB-C ports need to support same speed.
-	 * Need to fix once USB-C feature set is known for Volteer.
-	 */
-	return TBT_SS_RES_0;
-}
-
-__override bool board_is_tbt_usb4_port(int port)
-{
-	enum ec_cfg_usb_db_type usb_db = ec_cfg_usb_db_type();
-
-	/*
-	 * Volteer reference design only supports TBT & USB4 on port 1
-	 * if the USB4 DB is present.
-	 *
-	 * TODO (b/147732807): All the USB-C ports need to support same
-	 * features. Need to fix once USB-C feature set is known for Volteer.
-	 */
-	return ((port == USBC_PORT_C1)
-		&& ((usb_db == DB_USB4_GEN2) || (usb_db == DB_USB4_GEN3)));
-}
-
 /******************************************************************************/
 /* Physical fans. These are logically separate from pwm_channels. */
 
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
@@ -161,17 +98,22 @@ const struct fan_t fans[FAN_CH_COUNT] = {
  * 130 C.  However, sensor is located next to DDR, so we need to use the lower
  * DDR temperature limit (85 C)
  */
-const static struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(35),
-	.temp_fan_max = C_TO_K(50),
-};
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+		}, \
+		.temp_fan_off = C_TO_K(35), \
+		.temp_fan_max = C_TO_K(50), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 
 /*
  * Inductor limits - used for both charger and PP3300 regulator
@@ -184,24 +126,29 @@ const static struct ec_thermal_config thermal_cpu = {
  * Inductors: limit of 125c
  * PCB: limit is 80c
  */
-const static struct ec_thermal_config thermal_inductor = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(55),
-};
-
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_INDUCTOR         \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+		}, \
+		.temp_fan_off = C_TO_K(40), \
+		.temp_fan_max = C_TO_K(55), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_inductor =
+	THERMAL_INDUCTOR;
 
 struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_CHARGER]			= thermal_inductor,
-	[TEMP_SENSOR_2_PP3300_REGULATOR]	= thermal_inductor,
-	[TEMP_SENSOR_3_DDR_SOC]			= thermal_cpu,
-	[TEMP_SENSOR_4_FAN]			= thermal_cpu,
+	[TEMP_SENSOR_1_CHARGER] = THERMAL_INDUCTOR,
+	[TEMP_SENSOR_2_PP3300_REGULATOR] = THERMAL_INDUCTOR,
+	[TEMP_SENSOR_3_DDR_SOC] = THERMAL_CPU,
+	[TEMP_SENSOR_4_FAN] = THERMAL_CPU,
 };
 BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
 
@@ -310,341 +257,3 @@ const struct pwm_t pwm_channels[] = {
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/******************************************************************************/
-/* Volteer specific USB daughter-board configuration */
-
-/* USBC TCPC configuration for USB3 daughter board */
-static const struct tcpc_config_t tcpc_config_p1_usb3 = {
-	.bus_type = EC_BUS_TYPE_I2C,
-	.i2c_info = {
-		.port = I2C_PORT_USB_C1,
-		.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-	},
-	.flags = TCPC_FLAGS_TCPCI_REV2_0 | TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V,
-	.drv = &ps8xxx_tcpm_drv,
-	.usb23 = USBC_PORT_1_USB2_NUM | (USBC_PORT_1_USB3_NUM << 4),
-};
-
-/*
- * USB3 DB mux configuration - the top level mux still needs to be set to the
- * virtual_usb_mux_driver so the AP gets notified of mux changes and updates
- * the TCSS configuration on state changes.
- */
-static const struct usb_mux usbc1_usb3_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	.next_mux = NULL,
-};
-
-static const struct usb_mux mux_config_p1_usb3_active = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-	.next_mux = &usbc1_usb3_db_retimer,
-};
-
-static const struct usb_mux mux_config_p1_usb3_passive = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-
-/******************************************************************************/
-/* USB-A charging control */
-
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_PP5000_USBA,
-};
-
-static enum gpio_signal ps8xxx_rst_odl = GPIO_USB_C1_RT_RST_ODL;
-
-static void ps8815_reset(void)
-{
-	int val;
-
-	gpio_set_level(ps8xxx_rst_odl, 0);
-	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS,
-			   PS8815_PWR_H_RST_H_DELAY_MS));
-	gpio_set_level(ps8xxx_rst_odl, 1);
-	msleep(PS8815_FW_INIT_DELAY_MS);
-
-	/*
-	 * b/144397088
-	 * ps8815 firmware 0x01 needs special configuration
-	 */
-
-	CPRINTS("%s: patching ps8815 registers", __func__);
-
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
-		CPRINTS("ps8815: reg 0x0f was %02x", val);
-
-	if (i2c_write8(I2C_PORT_USB_C1,
-		       PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) == EC_SUCCESS)
-		CPRINTS("ps8815: reg 0x0f set to 0x31");
-
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
-		CPRINTS("ps8815: reg 0x0f now %02x", val);
-}
-
-void board_reset_pd_mcu(void)
-{
-	enum ec_cfg_usb_db_type usb_db = ec_cfg_usb_db_type();
-
-	/* No reset available for TCPC on port 0 */
-	/* Daughterboard specific reset for port 1 */
-	if (usb_db == DB_USB3_ACTIVE) {
-		ps8815_reset();
-		usb_mux_hpd_update(USBC_PORT_C1, 0, 0);
-	}
-}
-
-/*
- * Set up support for the USB3 daughterboard:
- *   Parade PS8815 TCPC (integrated retimer)
- *   Diodes PI3USB9201 BC 1.2 chip (same as USB4 board)
- *   Silergy SYV682A PPC (same as USB4 board)
- *   Virtual mux with stacked retimer
- */
-static void config_db_usb3_active(void)
-{
-	tcpc_config[USBC_PORT_C1] = tcpc_config_p1_usb3;
-	usb_muxes[USBC_PORT_C1] = mux_config_p1_usb3_active;
-}
-
-/*
- * Set up support for the passive USB3 daughterboard:
- *   TUSB422 TCPC (already the default)
- *   PI3USB9201 BC 1.2 chip (already the default)
- *   Silergy SYV682A PPC (already the default)
- *   Virtual mux without stacked retimer
- */
-
-static void config_db_usb3_passive(void)
-{
-	usb_muxes[USBC_PORT_C1] = mux_config_p1_usb3_passive;
-}
-
-static void config_port_discrete_tcpc(int port)
-{
-	/*
-	 * Support 2 Pin-to-Pin compatible parts: TUSB422 and RT1715, for
-	 * simplicity allow either and decide at runtime which we are using.
-	 * Default to TUSB422, and switch to RT1715 if it is on the I2C bus and
-	 * the VID matches.
-	 */
-
-	int regval;
-
-	if (i2c_read16(port ? I2C_PORT_USB_C1 : I2C_PORT_USB_C0,
-		       RT1715_I2C_ADDR_FLAGS, TCPC_REG_VENDOR_ID,
-		       &regval) == EC_SUCCESS) {
-		if (regval == RT1715_VENDOR_ID) {
-			CPRINTS("C%d: RT1715 detected", port);
-			tcpc_config[port].i2c_info.addr_flags =
-				RT1715_I2C_ADDR_FLAGS;
-			tcpc_config[port].drv = &rt1715_tcpm_drv;
-			return;
-		}
-	}
-	CPRINTS("C%d: Default to TUSB422", port);
-}
-
-static const char *db_type_prefix = "USB DB type: ";
-__override void board_cbi_init(void)
-{
-	enum ec_cfg_usb_db_type usb_db = ec_cfg_usb_db_type();
-
-	/* Reconfigure Volteer GPIOs based on the board ID */
-	if (get_board_id() == 0) {
-		CPRINTS("Configuring GPIOs for board ID 0");
-		CPRINTS("VOLUME_UP button disabled");
-
-		/* Reassign USB_C1_RT_RST_ODL */
-		bb_controls[USBC_PORT_C1].retimer_rst_gpio =
-			GPIO_USB_C1_RT_RST_ODL_BOARDID_0;
-		ps8xxx_rst_odl = GPIO_USB_C1_RT_RST_ODL_BOARDID_0;
-	}
-	config_port_discrete_tcpc(0);
-	switch (usb_db) {
-	case DB_USB_ABSENT:
-		CPRINTS("%sNone", db_type_prefix);
-		break;
-	case DB_USB4_GEN2:
-		config_port_discrete_tcpc(1);
-		CPRINTS("%sUSB4 Gen1/2", db_type_prefix);
-		break;
-	case DB_USB4_GEN3:
-		config_port_discrete_tcpc(1);
-		CPRINTS("%sUSB4 Gen3", db_type_prefix);
-		break;
-	case DB_USB3_ACTIVE:
-		config_db_usb3_active();
-		CPRINTS("%sUSB3 Active", db_type_prefix);
-		break;
-	case DB_USB3_PASSIVE:
-		config_db_usb3_passive();
-		config_port_discrete_tcpc(1);
-		CPRINTS("%sUSB3 Passive", db_type_prefix);
-		break;
-	default:
-		CPRINTS("%sID %d not supported", db_type_prefix, usb_db);
-	}
-
-	if ((!IS_ENABLED(TEST_BUILD) && !ec_cfg_has_numeric_pad()) ||
-	    get_board_id() <= 2)
-		keyboard_raw_set_cols(KEYBOARD_COLS_NO_KEYPAD);
-}
-
-/******************************************************************************/
-/* USBC PPC configuration */
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/******************************************************************************/
-/* PPC support routines */
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		sn5s330_interrupt(USBC_PORT_C0);
-		break;
-	case GPIO_USB_C1_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C1);
-	default:
-		break;
-	}
-}
-
-/******************************************************************************/
-/* BC1.2 charger detect configuration */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC TCPC configuration */
-struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
-		},
-		.drv = &tusb422_tcpm_drv,
-		.usb23 = USBC_PORT_0_USB2_NUM | (USBC_PORT_0_USB3_NUM << 4),
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C1,
-			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
-		},
-		.drv = &tusb422_tcpm_drv,
-		.usb23 = USBC_PORT_1_USB2_NUM | (USBC_PORT_1_USB3_NUM << 4),
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC mux configuration - Tiger Lake includes internal mux */
-struct usb_mux usbc1_usb4_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &bb_usb_retimer,
-	.i2c_port = I2C_PORT_USB_1_MIX,
-	.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
-};
-struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc1_usb4_db_retimer,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-struct bb_usb_control bb_controls[] = {
-	[USBC_PORT_C0] = {
-		/* USB-C port 0 doesn't have a retimer */
-	},
-	[USBC_PORT_C1] = {
-		.usb_ls_en_gpio = GPIO_USB_C1_LS_EN,
-		.retimer_rst_gpio = GPIO_USB_C1_RT_RST_ODL,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(bb_controls) == USBC_PORT_COUNT);
-
-static void board_tcpc_init(void)
-{
-	/* Don't reset TCPCs after initial reset */
-	if (!system_jumped_late())
-		board_reset_pd_mcu();
-
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
-
-	/* Enable BC1.2 interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
-
-/******************************************************************************/
-/* TCPC support routines */
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	/*
-	 * Check which port has the ALERT line set
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_0;
-	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (port == USBC_PORT_C0)
-		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
-	else
-		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
-}
diff --git a/board/volteer/board.h b/board/volteer/board.h
index 4aa02f6d6b..557327a765 100644
--- a/board/volteer/board.h
+++ b/board/volteer/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,17 +11,10 @@
 /* Baseboard features */
 #include "baseboard.h"
 
-#ifdef BOARD_VOLTEER_TCPMV1
-/* Disable TCPMv2 configuration options */
-#undef CONFIG_USB_PD_TCPMV2
-
-/* Enable the required TCPMv1 options */
-#define CONFIG_USB_PD_TCPMV1
-
+#ifdef BOARD_VOLTEER_NPCX797FC
 /*
- * Because the TPCMv1 stack has considerably smaller flash footprint, disable
- * the CONFIG_CHIP_INIT_ROM_REGION for testing of the init_rom API and the
- * BMI260 driver.
+ * The RAM and flash size combination on the the NPCX797FC does not leave
+ * any unused flash space that can be used to store the .init_rom section.
  */
 #undef CONFIG_CHIP_INIT_ROM_REGION
 #endif
@@ -29,6 +22,9 @@
 /* Optional features */
 #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
 
+/* Remove PRL state names to free flash space */
+#define CONFIG_USB_PD_DEBUG_LEVEL 0
+
 #define CONFIG_VBOOT_EFS2
 
 #define CONFIG_POWER_BUTTON
@@ -38,6 +34,7 @@
 
 /* Chipset features */
 #define CONFIG_POWER_PP5000_CONTROL
+#define CONFIG_CPU_PROCHOT_GATE_ON_C10
 
 /* LED defines */
 #define CONFIG_LED_PWM
@@ -57,62 +54,52 @@
 
 /* TCS3400 ALS */
 #define CONFIG_ALS
-#define ALS_COUNT		1
+#define ALS_COUNT 1
 #define CONFIG_ALS_TCS3400
 #define CONFIG_ALS_TCS3400_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS)
 
 /* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
-	(BIT(LID_ACCEL) | BIT(CLEAR_ALS))
+#define CONFIG_ACCEL_FORCE_MODE_MASK (BIT(LID_ACCEL) | BIT(CLEAR_ALS))
 
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE		BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID		LID_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
 
 /* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
-
-/*
- * USB-C port's USB2 & USB3 mapping from schematics
- * USB2 numbering on PCH - 1 to n
- * USB3 numbering on AP - 0 to n (PMC's USB3 numbering for MUX
- * configuration is - 1 to n hence add +1)
- */
-#define USBC_PORT_0_USB2_NUM	9
-#define USBC_PORT_0_USB3_NUM	1
-#define USBC_PORT_1_USB2_NUM	4
-#define USBC_PORT_1_USB3_NUM	2
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
 
 /* TODO: b/144165680 - measure and check these values on Volteer */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
-
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
 /*
  * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
  * cables only support up to 60W.
  */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Enabling Thunderbolt-compatible mode */
 #define CONFIG_USB_PD_TBT_COMPAT_MODE
 
 /* Enabling USB4 mode */
 #define CONFIG_USB_PD_USB4
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x40
+#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x40
 
 /* USB Type A Features */
-#define USB_PORT_COUNT			1
+#define USB_PORT_COUNT 1
 #define CONFIG_USB_PORT_POWER_DUMB
 
 /* USBC PPC*/
-#define CONFIG_USBC_PPC_SN5S330		/* USBC port C0 */
-#define CONFIG_USBC_PPC_SYV682X		/* USBC port C1 */
+#define CONFIG_USBC_PPC_SN5S330 /* USBC port C0 */
+#define CONFIG_USBC_PPC_SYV682X /* USBC port C1 */
+#define CONFIG_USB_PD_FRS_PPC
+
+/* Disable PPC logging to reduce EC image size */
+#undef CONFIG_USBC_PPC_LOGGING
 
 /* BC 1.2 */
 
@@ -121,8 +108,8 @@
 /* Fan features */
 
 /* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 
 /*
  * Macros for GPIO signals used in common code that don't match the
@@ -130,51 +117,97 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_DSW_PWROK		GPIO_EC_PCH_DSW_PWROK
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD		GPIO_PG_EC_RSMRST_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
-#define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE_L
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_LID_OPEN GPIO_EC_LID_OPEN
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
 
 /* I2C Bus Configuration */
 #define CONFIG_I2C
-#define I2C_PORT_ACCEL		I2C_PORT_SENSOR
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_1_MIX	NPCX_I2C_PORT3_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-#define CONFIG_I2C_MASTER
-
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT3_0
+#define I2C_PORT_POWER NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+
+#define I2C_PORT_BATTERY I2C_PORT_POWER
+#define I2C_PORT_CHARGER I2C_PORT_EEPROM
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+#define CONFIG_I2C_CONTROLLER
+
+#define CONFIG_DEBUG_ASSERT_BRIEF
+
+/* Disable console commands to help save space */
+#undef CONFIG_CMD_ADC
+#undef CONFIG_CMD_APTHROTTLE
+#undef CONFIG_CMD_BATTFAKE
+#undef CONFIG_CMD_BUTTON
+#undef CONFIG_CMD_CBI
+#undef CONFIG_CMD_CHARGER
+#undef CONFIG_CMD_CHARGE_SUPPLIER_INFO
+#undef CONFIG_CMD_CRASH
+#undef CONFIG_CMD_DEVICE_EVENT
+#undef CONFIG_CMD_FLASH_WP
+#undef CONFIG_CMD_HASH
+#undef CONFIG_CMD_I2C_XFER
+#undef CONFIG_CMD_IDLE_STATS
+#undef CONFIG_CMD_INA
+#undef CONFIG_CMD_MFALLOW
+#undef CONFIG_CMD_MMAPINFO
+#undef CONFIG_CMD_POWERINDEBUG
+#undef CONFIG_CMD_PWR_AVG
+#undef CONFIG_CMD_REGULATOR
+#undef CONFIG_CMD_USB_PD_CABLE
+#undef CONFIG_CONSOLE_CMDHELP
+#undef CONFIG_CONSOLE_HISTORY
+
+/* Free flash space */
+#undef CONFIG_ACCEL_SPOOF_MODE
+#undef CONFIG_CMD_SYSLOCK
+#undef CONFIG_CMD_TIMERINFO
+#undef CONFIG_CMD_MD
+#undef CONFIG_CMD_I2C_SCAN
+#undef CONFIG_CMD_AP_RESET_LOG
+#undef CONFIG_CMD_CHARGER_DUMP
+#undef CONFIG_CMD_SLEEPMASK_SET
+#undef CONFIG_CONSOLE_VERBOSE
+#undef CONFIG_CMD_TYPEC
+#undef CONFIG_CMD_FASTCHARGE
+#undef CONFIG_CMD_KEYBOARD
+#undef CONFIG_CMD_MEM
+#undef CONFIG_CMD_PD
+#undef CONFIG_CMD_PECI
+#undef CONFIG_CMD_RETIMER
+#undef CONFIG_CMD_RW
+
+/* Disable volume button in ectool */
+#undef CONFIG_HOSTCMD_BUTTON
 
 #ifndef __ASSEMBLER__
 
 #include "gpio_signal.h"
 #include "registers.h"
+#include "usbc_config.h"
 
 enum battery_type {
 	BATTERY_LGC011,
@@ -200,12 +233,6 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
-
 void board_reset_pd_mcu(void);
 
 #endif /* !__ASSEMBLER__ */
diff --git a/board/volteer/build.mk b/board/volteer/build.mk
index bcf93c58cb..fc7828e29b 100644
--- a/board/volteer/build.mk
+++ b/board/volteer/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -8,10 +8,18 @@
 
 CHIP:=npcx
 CHIP_FAMILY:=npcx7
+# A limited Volteer boards are reworked with NPCX797FC variant. Set the
+# modify the variant type to match.
+ifeq ($(BOARD),volteer_npcx797fc)
+CHIP_VARIANT:=npcx7m7fc
+else
 CHIP_VARIANT:=npcx7m6fc
+endif
 BASEBOARD:=volteer
 
 board-y=board.o
 board-y+=battery.o
+board-y+=cbi.o
 board-y+=led.o
 board-y+=sensors.o
+board-y+=usbc_config.o
diff --git a/board/volteer/cbi.c b/board/volteer/cbi.c
new file mode 100644
index 0000000000..c2bc656bb5
--- /dev/null
+++ b/board/volteer/cbi.c
@@ -0,0 +1,27 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Features common to ECOS and Zephyr */
+#include "cbi.h"
+#include "cbi_ec_fw_config.h"
+#include "common.h"
+#include "keyboard_raw.h"
+#include "usbc_config.h"
+
+/******************************************************************************/
+/*
+ * FW_CONFIG defaults for Volteer if the CBI data is not initialized.
+ */
+union volteer_cbi_fw_config fw_config_defaults = {
+	.usb_db = DB_USB4_GEN2,
+};
+
+__override void board_cbi_init(void)
+{
+	config_usb3_db_type();
+	if ((!IS_ENABLED(TEST_BUILD) && !ec_cfg_has_numeric_pad()) ||
+	    get_board_id() <= 2)
+		keyboard_raw_set_cols(KEYBOARD_COLS_NO_KEYPAD);
+}
diff --git a/board/volteer/ec.tasklist b/board/volteer/ec.tasklist
index ec9e64e850..0492fcc3c0 100644
--- a/board/volteer/ec.tasklist
+++ b/board/volteer/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,6 +16,7 @@
 	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
 	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
 	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
 	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
 	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
 	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
diff --git a/board/volteer/gpio.inc b/board/volteer/gpio.inc
index 183f20c890..04982595fe 100644
--- a/board/volteer/gpio.inc
+++ b/board/volteer/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,7 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
@@ -77,6 +77,7 @@ GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
 GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
 GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
 GPIO_INT(EC_PROCHOT_IN_L,      PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
+GPIO_INT(CPU_C10_GATE_L,       PIN(6, 7), GPIO_INT_RISING, throttle_ap_c10_input_interrupt)
 GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
 
 GPIO(EC_PCH_INT_ODL,           PIN(B, 0), GPIO_ODR_HIGH)
@@ -84,19 +85,12 @@ GPIO(EC_PCH_INT_ODL,           PIN(B, 0), GPIO_ODR_HIGH)
 /* USB and USBC Signals */
 GPIO(EN_PP5000_USBA,		PIN(C, 6), GPIO_OUT_LOW)	/* Enable USB-A charging - all ports */
 GPIO(USB_A_LOW_PWR_OD,		PIN(6, 6), GPIO_ODR_LOW)	/* Don't limit USB-A charging by default - all ports */
-
-/*
- * USB_C1 moved from GPIO32 to GPIO83 on boards with board ID >=1.
- * GPIO83/EN_PP1800_A is DNS on board ID 0 and GPIO32 is N/C on board ID >=1
- * so it's safe to define GPIOs compatible with both designs.
- * TODO (b/149858568): remove board ID=0 support.
- */
-GPIO(USB_C1_RT_RST_ODL_BOARDID_0,	PIN(3, 2), GPIO_ODR_LOW) /* USB_C1 Reset on boards without board ID */
-GPIO(USB_C1_RT_RST_ODL,			PIN(8, 3), GPIO_ODR_LOW) /* USB_C1 Reset on boards board ID >=1 */
-GPIO(USB_C0_OC_ODL,			PIN(B, 1), GPIO_ODR_HIGH)
-GPIO(USB_C1_OC_ODL,			PIN(5, 0), GPIO_ODR_HIGH)
+GPIO(USB_C1_RT_RST_ODL,		PIN(8, 3), GPIO_ODR_LOW)
+GPIO(USB_C0_OC_ODL,		PIN(B, 1), GPIO_ODR_HIGH)
+GPIO(USB_C1_OC_ODL,		PIN(5, 0), GPIO_ODR_HIGH)
 /* There is currently no need to service this interrupt. */
-GPIO(USB_C1_RT_INT_ODL,			PIN(F, 3), GPIO_INPUT)
+GPIO(USB_C1_RT_INT_ODL,		PIN(F, 3), GPIO_INPUT)
+GPIO(USB_C1_FRS_EN, 		PIN(9, 4), GPIO_OUT_LOW)
 
 /* Don't have a load switch for retimer */
 UNIMPLEMENTED(USB_C1_LS_EN)
@@ -114,10 +108,16 @@ GPIO(CCD_MODE_ODL,		PIN(E, 5), GPIO_INPUT)		/* Case Closed Debug Mode */
 GPIO(EC_SLP_S0IX,		PIN(7, 2), GPIO_INPUT | GPIO_PULL_UP)
 
 /* Unused signals */
+GPIO(CHARGER_INT_L,		PIN(7, 3), GPIO_INPUT)		/* Interrupt not used from ISL9241, on board pull-up */
+GPIO(EC_GP_SEL0_ODL,		PIN(B, 6), GPIO_OUT_LOW) 	/* Cannot be configured as input, drive output low, don't rely on the default setting of PxDOUT register */
+GPIO(EN_PP5000_USB_AG,		PIN(A, 7), GPIO_INPUT | GPIO_PULL_UP) /* Unconnected power sequencing signal */
 GPIO(UNUSED_GPIO41,		PIN(4, 1), GPIO_INPUT | GPIO_PULL_UP)
 GPIO(UNUSED_GPIOF2,		PIN(F, 2), GPIO_INPUT | GPIO_PULL_UP)
 GPIO(UNUSED_GPIO96,		PIN(9, 6), GPIO_INPUT | GPIO_PULL_UP)
 GPIO(UNUSED_GPIO34,		PIN(3, 4), GPIO_INPUT | GPIO_PULL_UP)
+/* Only connected to test points */
+GPIO(EC_KB_BL_EN,		PIN(8, 6), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(EC_ESPI_ALERT_L,		PIN(5, 7), GPIO_INPUT | GPIO_PULL_UP)
 
 /*
  * eDP backlight - both PCH and EC have enable pins that must be high
@@ -182,3 +182,6 @@ ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)  /* GPIO00 =
                                                                        GPIO01 = H1_EC_PWR_BTN_ODL
                                                                        GPIO02 = EC_RST_ODL */
 
+/* Temperature sensors */
+ALTERNATE(PIN_MASK(4, BIT(2) | BIT(4) | BIT(5)), 0, MODULE_ADC, 0) /* TEMP_SENSOR1,2,4 */
+ALTERNATE(PIN_MASK(F, BIT(1)), 0, MODULE_ADC, 0) /* TEMP_SENSOR3 */
diff --git a/board/volteer/led.c b/board/volteer/led.c
index 4486bcb912..adc8f7b4a6 100644
--- a/board/volteer/led.c
+++ b/board/volteer/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -18,17 +18,17 @@ const enum ec_led_id supported_led_ids[] = {
 };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-struct pwm_led led_color_map[] = {
-				/* Red, Green, Blue */
-	[EC_LED_COLOR_RED] =    {  100,   0,     0 },
-	[EC_LED_COLOR_GREEN] =  {    0, 100,     0 },
-	[EC_LED_COLOR_BLUE] =   {    0,   0,   100 },
+struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = {
+	/* Red, Green, Blue */
+	[EC_LED_COLOR_RED] = { 100, 0, 0 },
+	[EC_LED_COLOR_GREEN] = { 0, 100, 0 },
+	[EC_LED_COLOR_BLUE] = { 0, 0, 100 },
 	/* The green LED seems to be brighter than the others, so turn down
 	 * green from its natural level for these secondary colors.
 	 */
-	[EC_LED_COLOR_YELLOW] = {  100,  70,     0 },
-	[EC_LED_COLOR_WHITE] =  {  100,  70,   100 },
-	[EC_LED_COLOR_AMBER] =  {  100,  20,     0 },
+	[EC_LED_COLOR_YELLOW] = { 100, 70, 0 },
+	[EC_LED_COLOR_WHITE] = { 100, 70, 100 },
+	[EC_LED_COLOR_AMBER] = { 100, 20, 0 },
 };
 
 struct pwm_led pwm_leds[] = {
@@ -102,3 +102,11 @@ static void led_set_charge_port_tick(void)
 		pwm_set_duty(PWM_CH_LED4_SIDESEL, side_select_duty);
 }
 DECLARE_HOOK(HOOK_TICK, led_set_charge_port_tick, HOOK_PRIO_DEFAULT);
+
+static void board_led_init(void)
+{
+	/* Illuminate motherboard and daughter board LEDs equally to start. */
+	pwm_enable(PWM_CH_LED4_SIDESEL, 1);
+	pwm_set_duty(PWM_CH_LED4_SIDESEL, 50);
+}
+DECLARE_HOOK(HOOK_INIT, board_led_init, HOOK_PRIO_DEFAULT);
diff --git a/board/volteer/sensors.c b/board/volteer/sensors.c
index 9e34812131..61068c28f1 100644
--- a/board/volteer/sensors.c
+++ b/board/volteer/sensors.c
@@ -1,27 +1,27 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Volteer family-specific sensor configuration */
-#include "common.h"
 #include "accelgyro.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_bmi260.h"
-#include "driver/als_tcs3400.h"
-#include "driver/sync.h"
-#include "keyboard_scan.h"
+#include "common.h"
+#include "driver/accel_bma2x2_public.h"
+#include "driver/accelgyro_bmi260_public.h"
+#include "driver/accelgyro_bmi_common_public.h"
+#include "driver/als_tcs3400_public.h"
+#include "gpio.h"
 #include "hooks.h"
 #include "i2c.h"
-#include "task.h"
+#include "keyboard_scan.h"
 #include "tablet_mode.h"
+#include "task.h"
 #include "util.h"
 
 /******************************************************************************/
 /* Sensors */
-static struct mutex g_lid_accel_mutex;
-static struct mutex g_base_mutex;
+K_MUTEX_DEFINE(g_lid_accel_mutex);
+K_MUTEX_DEFINE(g_base_mutex);
 
 /* BMA253 private data */
 static struct accelgyro_saved_data_t g_bma253_data;
@@ -84,17 +84,13 @@ static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
 };
 
 /* Rotation matrix for the lid accelerometer */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+				       { FLOAT_TO_FP(-1), 0, 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
@@ -224,22 +220,3 @@ static void baseboard_sensors_init(void)
 	gpio_enable_interrupt(GPIO_EC_IMU_INT_L);
 }
 DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_DEFAULT);
-
-#ifndef TEST_BUILD
-void lid_angle_peripheral_enable(int enable)
-{
-	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
-
-	if (enable) {
-		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
-	} else {
-		/*
-		 * Ensure that the chipset is off before disabling the keyboard.
-		 * When the chipset is on, the EC keeps the keyboard enabled and
-		 * the AP decides whether to ignore input devices or not.
-		 */
-		if (!chipset_in_s0)
-			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
-	}
-}
-#endif
diff --git a/board/volteer/usbc_config.c b/board/volteer/usbc_config.c
new file mode 100644
index 0000000000..e95143cd39
--- /dev/null
+++ b/board/volteer/usbc_config.c
@@ -0,0 +1,409 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Volteer family-specific USB-C configuration */
+#include "cbi_ec_fw_config.h"
+#include "common.h"
+#include "driver/bc12/pi3usb9201_public.h"
+#include "driver/ppc/sn5s330_public.h"
+#include "driver/ppc/syv682x_public.h"
+#include "driver/retimer/bb_retimer_public.h"
+#include "driver/tcpm/ps8xxx_public.h"
+#include "driver/tcpm/rt1715_public.h"
+#include "driver/tcpm/tcpci.h"
+#include "driver/tcpm/tusb422_public.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "system.h"
+#include "timer.h"
+#include "usb_mux.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+/* Disable debug messages to save flash space */
+#define CPRINTS(format, args...)
+
+/* USBC TCPC configuration for USB3 daughter board */
+static const struct tcpc_config_t tcpc_config_p1_usb3 = {
+	.bus_type = EC_BUS_TYPE_I2C,
+	.i2c_info = {
+		.port = I2C_PORT_USB_C1,
+		.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+	},
+	.flags = TCPC_FLAGS_TCPCI_REV2_0 | TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V,
+	.drv = &ps8xxx_tcpm_drv,
+};
+
+/*
+ * USB3 DB mux configuration - the top level mux still needs to be set to the
+ * virtual_usb_mux_driver so the AP gets notified of mux changes and updates
+ * the TCSS configuration on state changes.
+ */
+static const struct usb_mux_chain usbc1_usb3_db_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
+	.next = NULL,
+};
+
+static const struct usb_mux_chain mux_config_p1_usb3_active = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+	.next = &usbc1_usb3_db_retimer,
+};
+
+static const struct usb_mux_chain mux_config_p1_usb3_passive = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		}
+};
+
+/*
+ * Set up support for the USB3 daughterboard:
+ *   Parade PS8815 TCPC (integrated retimer)
+ *   Diodes PI3USB9201 BC 1.2 chip (same as USB4 board)
+ *   Silergy SYV682A PPC (same as USB4 board)
+ *   Virtual mux with stacked retimer
+ */
+static void config_db_usb3_active(void)
+{
+	tcpc_config[USBC_PORT_C1] = tcpc_config_p1_usb3;
+	usb_muxes[USBC_PORT_C1] = mux_config_p1_usb3_active;
+}
+
+/*
+ * Set up support for the passive USB3 daughterboard:
+ *   TUSB422 TCPC (already the default)
+ *   PI3USB9201 BC 1.2 chip (already the default)
+ *   Silergy SYV682A PPC (already the default)
+ *   Virtual mux without stacked retimer
+ */
+
+static void config_db_usb3_passive(void)
+{
+	usb_muxes[USBC_PORT_C1] = mux_config_p1_usb3_passive;
+}
+
+static void config_port_discrete_tcpc(int port)
+{
+	/*
+	 * Support 2 Pin-to-Pin compatible parts: TUSB422 and RT1715, for
+	 * simplicity allow either and decide at runtime which we are using.
+	 * Default to TUSB422, and switch to RT1715 if it is on the I2C bus and
+	 * the VID matches.
+	 */
+
+	int regval;
+
+	if (i2c_read16(port ? I2C_PORT_USB_C1 : I2C_PORT_USB_C0,
+		       RT1715_I2C_ADDR_FLAGS, TCPC_REG_VENDOR_ID,
+		       &regval) == EC_SUCCESS) {
+		if (regval == RT1715_VENDOR_ID) {
+			CPRINTS("C%d: RT1715 detected", port);
+			tcpc_config[port].i2c_info.addr_flags =
+				RT1715_I2C_ADDR_FLAGS;
+			tcpc_config[port].drv = &rt1715_tcpm_drv;
+			return;
+		}
+	}
+	CPRINTS("C%d: Default to TUSB422", port);
+}
+
+void config_usb3_db_type(void)
+{
+	enum ec_cfg_usb_db_type usb_db = ec_cfg_usb_db_type();
+
+	config_port_discrete_tcpc(0);
+	switch (usb_db) {
+	case DB_USB_ABSENT:
+		CPRINTS("USB DB Type: None");
+		break;
+	case DB_USB4_GEN2:
+		config_port_discrete_tcpc(1);
+		CPRINTS("USB DB Type: USB4 Gen1/2");
+		break;
+	case DB_USB4_GEN3:
+		config_port_discrete_tcpc(1);
+		CPRINTS("USB DB Type: USB4 Gen3");
+		break;
+	case DB_USB3_ACTIVE:
+		config_db_usb3_active();
+		CPRINTS("USB DB Type: USB3 Active");
+		break;
+	case DB_USB3_PASSIVE:
+		config_db_usb3_passive();
+		config_port_discrete_tcpc(1);
+		CPRINTS("USB DB Type: USB3 Passive");
+		break;
+	default:
+		CPRINTS("USB DB Type: ID %d not supported", usb_db);
+	}
+}
+
+/******************************************************************************/
+/* USBC PPC configuration */
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+		.drv = &sn5s330_drv,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C1,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.frs_en = GPIO_USB_C1_FRS_EN,
+		.drv = &syv682x_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/******************************************************************************/
+/* PPC support routines */
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		sn5s330_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C1);
+		break;
+	default:
+		break;
+	}
+}
+
+/******************************************************************************/
+/* USBC TCPC configuration */
+struct tcpc_config_t tcpc_config[] = {
+	[USBC_PORT_C0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0,
+			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
+		},
+		.drv = &tusb422_tcpm_drv,
+	},
+	[USBC_PORT_C1] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C1,
+			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
+		},
+		.drv = &tusb422_tcpm_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
+BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
+
+/******************************************************************************/
+/* USB-A charging control */
+
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_PP5000_USBA,
+};
+
+/******************************************************************************/
+/* USBC mux configuration - Tiger Lake includes internal mux */
+struct usb_mux_chain usbc1_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		}
+};
+
+struct usb_mux_chain usb_muxes[] = {
+	[USBC_PORT_C0] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+	},
+	[USBC_PORT_C1] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_1_MIX,
+			.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc1_tcss_usb_mux,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
+
+struct bb_usb_control bb_controls[] = {
+	[USBC_PORT_C0] = {
+		/* USB-C port 0 doesn't have a retimer */
+	},
+	[USBC_PORT_C1] = {
+		.usb_ls_en_gpio = GPIO_USB_C1_LS_EN,
+		.retimer_rst_gpio = GPIO_USB_C1_RT_RST_ODL,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(bb_controls) == USBC_PORT_COUNT);
+
+__override enum tbt_compat_cable_speed board_get_max_tbt_speed(int port)
+{
+	enum ec_cfg_usb_db_type usb_db = ec_cfg_usb_db_type();
+
+	if (port == USBC_PORT_C1) {
+		if (usb_db == DB_USB4_GEN2) {
+			/*
+			 * Older boards violate 205mm trace length prior
+			 * to connection to the re-timer and only support up
+			 * to GEN2 speeds.
+			 */
+			return TBT_SS_U32_GEN1_GEN2;
+		} else if (usb_db == DB_USB4_GEN3) {
+			return TBT_SS_TBT_GEN3;
+		}
+	}
+
+	/*
+	 * Thunderbolt-compatible mode not supported
+	 *
+	 * TODO (b/147726366): All the USB-C ports need to support same speed.
+	 * Need to fix once USB-C feature set is known for Volteer.
+	 */
+	return TBT_SS_RES_0;
+}
+
+__override bool board_is_tbt_usb4_port(int port)
+{
+	enum ec_cfg_usb_db_type usb_db = ec_cfg_usb_db_type();
+
+	/*
+	 * Volteer reference design only supports TBT & USB4 on port 1
+	 * if the USB4 DB is present.
+	 *
+	 * TODO (b/147732807): All the USB-C ports need to support same
+	 * features. Need to fix once USB-C feature set is known for Volteer.
+	 */
+	return ((port == USBC_PORT_C1) &&
+		((usb_db == DB_USB4_GEN2) || (usb_db == DB_USB4_GEN3)));
+}
+
+static void ps8815_reset(void)
+{
+	int val;
+
+	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 0);
+	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS));
+	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 1);
+	msleep(PS8815_FW_INIT_DELAY_MS);
+
+	/*
+	 * b/144397088
+	 * ps8815 firmware 0x01 needs special configuration
+	 */
+
+	CPRINTS("%s: patching ps8815 registers", __func__);
+
+	if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) ==
+	    EC_SUCCESS)
+		CPRINTS("ps8815: reg 0x0f was %02x", val);
+
+	if (i2c_write8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f,
+		       0x31) == EC_SUCCESS)
+		CPRINTS("ps8815: reg 0x0f set to 0x31");
+
+	if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) ==
+	    EC_SUCCESS)
+		CPRINTS("ps8815: reg 0x0f now %02x", val);
+}
+
+void board_reset_pd_mcu(void)
+{
+	enum ec_cfg_usb_db_type usb_db = ec_cfg_usb_db_type();
+
+	/* No reset available for TCPC on port 0 */
+	/* Daughterboard specific reset for port 1 */
+	if (usb_db == DB_USB3_ACTIVE) {
+		ps8815_reset();
+		usb_mux_hpd_update(USBC_PORT_C1,
+				   USB_PD_MUX_HPD_LVL_DEASSERTED |
+					   USB_PD_MUX_HPD_IRQ_DEASSERTED);
+	}
+}
+
+static void board_tcpc_init(void)
+{
+	/* Don't reset TCPCs after initial reset */
+	if (!system_jumped_late())
+		board_reset_pd_mcu();
+
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
+
+#ifndef CONFIG_ZEPHYR
+	/* Enable BC1.2 interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
+#endif /* !CONFIG_ZEPHYR */
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
+
+#ifndef CONFIG_ZEPHYR
+/******************************************************************************/
+/* BC1.2 charger detect configuration */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C1,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
+#endif /* !CONFIG_ZEPHYR */
+
+/******************************************************************************/
+/* TCPC support routines */
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	/*
+	 * Check which port has the ALERT line set
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL))
+		status |= PD_STATUS_TCPC_ALERT_0;
+	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL))
+		status |= PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
+
+/******************************************************************************/
+
+int ppc_get_alert_status(int port)
+{
+	if (port == USBC_PORT_C0)
+		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
+	else
+		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
+}
diff --git a/board/volteer/usbc_config.h b/board/volteer/usbc_config.h
new file mode 100644
index 0000000000..7428d0c436
--- /dev/null
+++ b/board/volteer/usbc_config.h
@@ -0,0 +1,16 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* volteer board-specific USB-C configuration */
+
+#ifndef __CROS_EC_USBC_CONFIG_H
+#define __CROS_EC_USBC_CONFIG_H
+
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
+
+/* Configure the USB3 daughterboard type */
+void config_usb3_db_type(void);
+
+#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/volteer/vif_override.xml b/board/volteer/vif_override.xml
new file mode 100644
index 0000000000..771f0fe076
--- /dev/null
+++ b/board/volteer/vif_override.xml
@@ -0,0 +1,114 @@
+<?xml version="1.0" encoding="utf-8"?>
+<vif:VIF xmlns="http://usb.org/VendorInfoFile.xsd">
+  <vif:Model_Part_Number>Volteer RT1715</vif:Model_Part_Number>
+  <vif:Product_Revision>0</vif:Product_Revision>
+  <vif:TID>0</vif:TID>
+  <vif:Product>
+    <!-- Information about TGL USB4 provided by Intel. See b/172963736 -->
+    <vif:USB4_Num_Internal_Host_Controllers value="1" />
+    <vif:USB4_Num_PCIe_DN_Bridges value="0" />
+    <vif:USB4RouterList>
+      <vif:Usb4Router>
+        <vif:USB4_Router_ID value="1" />
+        <vif:USB4_Silicon_VID value="32903">8087</vif:USB4_Silicon_VID>
+        <vif:USB4_Num_Lane_Adapters value="4" />
+        <vif:USB4_Num_USB3_DN_Adapters value="1" />
+        <vif:USB4_Num_DP_IN_Adapters value="1" />
+        <vif:USB4_Num_DP_OUT_Adapters value="0" />
+        <vif:USB4_Num_PCIe_DN_Adapters value="4" />
+        <vif:USB4_TBT3_Not_Supported value="0">TBT3 Compatible</vif:USB4_TBT3_Not_Supported>
+        <vif:USB4_PCIe_Wake_Supported value="true" />
+        <vif:USB4_USB3_Wake_Supported value="false" />
+        <vif:USB4_Num_Unused_Adapters value="0" />
+        <vif:USB4_TBT3_VID value="32903">8087</vif:USB4_TBT3_VID>
+        <vif:USB4_PCIe_Switch_Vendor_ID value="32902">8086</vif:USB4_PCIe_Switch_Vendor_ID>
+        <vif:USB4_PCIe_Switch_Device_ID value="39451">9A1B</vif:USB4_PCIe_Switch_Device_ID>
+      </vif:Usb4Router>
+      <vif:Usb4Router>
+        <vif:USB4_Router_ID value="0" />
+        <vif:USB4_Silicon_VID value="32903">8087</vif:USB4_Silicon_VID>
+        <vif:USB4_Num_Lane_Adapters value="2" />
+        <vif:USB4_Num_USB3_DN_Adapters value="1" />
+        <vif:USB4_Num_DP_IN_Adapters value="0" />
+        <vif:USB4_Num_DP_OUT_Adapters value="0" />
+        <vif:USB4_Num_PCIe_DN_Adapters value="0" />
+        <vif:USB4_TBT3_Not_Supported value="1">Not TBT3-Compatible</vif:USB4_TBT3_Not_Supported>
+        <vif:USB4_PCIe_Wake_Supported value="false" />
+        <vif:USB4_USB3_Wake_Supported value="false" />
+        <vif:USB4_Num_Unused_Adapters value="0" />
+      </vif:Usb4Router>
+    </vif:USB4RouterList>
+  </vif:Product>
+  <vif:Component>
+    <!-- Port 0 is USB3-only. -->
+    <vif:USB4_Supported value="false">NO</vif:USB4_Supported>
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!-- Add in missing fields for SrcPdo0, derived from SYV682B datasheet. -->
+        <vif:Src_PD_OCP_OC_Debounce value="50">50 msec</vif:Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="360">3600 mA</vif:Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+    <vif:DFP_VDO_Port_Number value="0" />
+    <vif:Modal_Operation_Supported_SOP value="false" />
+  </vif:Component>
+  <vif:Component>
+    <vif:USB4_Max_Speed value="1">Gen 3 (40Gb)</vif:USB4_Max_Speed>
+    <vif:USB4_DFP_Supported value="true" />
+    <vif:USB4_UFP_Supported value="false" />
+    <vif:USB4_USB3_Tunneling_Supported value="true" />
+    <vif:USB4_DP_Tunneling_Supported value="true" />
+    <vif:USB4_PCIe_Tunneling_Supported value="true" />
+    <vif:USB4_TBT3_Compatibility_Supported value="true" />
+    <vif:USB4_CL1_State_Supported value="true" />
+    <vif:USB4_CL2_State_Supported value="true" />
+    <vif:USB4_Num_Retimers value="1" />
+    <vif:USB4_DP_Bit_Rate value="3">HBR3</vif:USB4_DP_Bit_Rate>
+    <vif:USB4_Num_DP_Lanes value="4">4 Lanes</vif:USB4_Num_DP_Lanes>
+    <vif:USB4_Lane_0_Adapter value="1" />
+    <vif:Host_Supports_USB_Data value="true" />
+    <vif:Host_Speed value="2">USB 3.2 Gen 2x1</vif:Host_Speed>
+    <vif:Host_Contains_Captive_Retimer value="true" />
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:Host_Suspend_Supported value="true" />
+    <vif:Is_DFP_On_Hub value="false" />
+    <vif:USB_Suspend_May_Be_Cleared value="true" />
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="3">3A @ 5V</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <vif:FR_Swap_Supported_As_Initial_Sink value="true" />
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!-- Add in missing fields for SrcPdo0, derived from SYV682B datasheet. -->
+        <vif:Src_PD_OCP_OC_Debounce value="50">50 msec</vif:Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="360">3600 mA</vif:Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+    <vif:Data_Capable_As_USB_Host_SOP value="true" />
+    <vif:Data_Capable_As_USB_Device_SOP value="false" />
+    <!-- TODO(b/173028252): Figure out the appropriate Discover Identity ACK for
+         Volteer and update the EC and VIF accordingly. -->
+    <vif:Product_Type_UFP_SOP value="3">PSD</vif:Product_Type_UFP_SOP>
+    <vif:Product_Type_DFP_SOP value="4">Alternate Mode Controller (AMC)</vif:Product_Type_DFP_SOP>
+    <vif:DFP_VDO_Port_Number value="1" />
+    <vif:Modal_Operation_Supported_SOP value="true" />
+    <vif:USB_VID_SOP value="6353">18D1</vif:USB_VID_SOP>
+    <vif:bcdDevice_SOP value="0">0000</vif:bcdDevice_SOP>
+    <vif:SVID_Fixed_SOP value="true" />
+    <vif:Num_SVIDs_Min_SOP value="1" />
+    <vif:Num_SVIDs_Max_SOP value="1" />
+    <vif:SOPSVIDList>
+      <vif:SOPSVID>
+        <vif:SVID_SOP value="32903">8087</vif:SVID_SOP>
+        <vif:SVID_Modes_Fixed_SOP value="true" />
+        <vif:SVID_Num_Modes_Min_SOP value="1" />
+        <vif:SVID_Num_Modes_Max_SOP value="1" />
+        <vif:SOPSVIDModeList>
+          <vif:SOPSVIDMode>
+            <vif:SVID_Mode_Enter_SOP value="true" />
+            <vif:SVID_Mode_Recog_Value_SOP value="0">00000000</vif:SVID_Mode_Recog_Value_SOP>
+          </vif:SOPSVIDMode>
+        </vif:SOPSVIDModeList>
+      </vif:SOPSVID>
+    </vif:SOPSVIDList>
+  </vif:Component>
+</vif:VIF>
diff --git a/board/volteer_ish/board.c b/board/volteer_ish/board.c
index 76c127056b..59b63c2a28 100644
--- a/board/volteer_ish/board.c
+++ b/board/volteer_ish/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,8 +6,8 @@
 /* Volteer ISH board-specific configuration */
 
 #include "console.h"
-#include "driver/accelgyro_bmi_common.h"
 #include "driver/accel_bma2x2.h"
+#include "driver/accelgyro_bmi_common.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "host_command.h"
@@ -16,15 +16,12 @@
 #include "power.h"
 #include "task.h"
 
-#include "gpio_list.h" /* has to be included last */
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
 
 /* I2C port map */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 1000
-	},
+	{ .name = "sensor", .port = I2C_PORT_SENSOR, .kbps = 1000 },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
diff --git a/board/volteer_ish/board.h b/board/volteer_ish/board.h
index b290d70b19..6f7d3bd1b7 100644
--- a/board/volteer_ish/board.h
+++ b/board/volteer_ish/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,26 +22,24 @@
 #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
 
 /* ISH specific */
-#undef  CONFIG_DEBUG_ASSERT
+#undef CONFIG_DEBUG_ASSERT
 #define CONFIG_CLOCK_CRYSTAL
 #define CONFIG_ISH_UART_0
 /* EC */
-#define CONFIG_FLASH_SIZE 0x80000
+#define CONFIG_FLASH_SIZE_BYTES 0x80000
 #define CONFIG_FPU
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_CONTROLLER
 
 /* BMA253 Lid accel */
 #define CONFIG_ACCEL_BMA255
 
 /* Host command over HECI */
-#define CONFIG_HOSTCMD_HECI
+#define CONFIG_HOST_INTERFACE_HECI
 
 #define CONFIG_MKBP_EVENT
 #define CONFIG_MKBP_USE_HECI
 
-#define CONFIG_ACCEL_INTERRUPTS
-
 /* Enable sensor fifo, must also define the _SIZE and _THRES */
 #define CONFIG_ACCEL_FIFO
 /* FIFO size is in power of 2. */
@@ -70,7 +68,7 @@
 #undef CONFIG_CMD_SHMEM
 #undef CONFIG_EXTPOWER
 #undef CONFIG_KEYBOARD_KSO_BASE
-#undef CONFIG_FLASH
+#undef CONFIG_FLASH_CROS
 #undef CONFIG_FMAP
 #undef CONFIG_LID_SWITCH
 #undef CONFIG_SWITCH
@@ -88,10 +86,7 @@
 #include "registers.h"
 
 /* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, SENSOR_COUNT };
 
 #endif /* !__ASSEMBLER__ */
 
diff --git a/board/volteer_ish/build.mk b/board/volteer_ish/build.mk
index 74ec3c865f..4a84a1f475 100644
--- a/board/volteer_ish/build.mk
+++ b/board/volteer_ish/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/volteer_ish/ec.tasklist b/board/volteer_ish/ec.tasklist
index a4db486e9a..de7d256324 100644
--- a/board/volteer_ish/ec.tasklist
+++ b/board/volteer_ish/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/volteer_ish/gpio.inc b/board/volteer_ish/gpio.inc
index 286309e388..8b25af63cb 100644
--- a/board/volteer_ish/gpio.inc
+++ b/board/volteer_ish/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/volteer_tcpmv1 b/board/volteer_npcx797fc
similarity index 100%
rename from board/volteer_tcpmv1
rename to board/volteer_npcx797fc
diff --git a/board/voxel/battery.c b/board/voxel/battery.c
index 4d314150e2..887ba27344 100644
--- a/board/voxel/battery.c
+++ b/board/voxel/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -44,6 +44,8 @@ const struct board_batt_params board_battery_info[] = {
 				.reg_addr = 0x43,
 				.reg_mask = 0x0001,
 				.disconnect_val = 0x0,
+				.cfet_mask = 0x0002,
+				.cfet_off_val = 0x0000,
 			}
 		},
 		.batt_info = {
@@ -59,37 +61,65 @@ const struct board_batt_params board_battery_info[] = {
 			.discharging_max_c    = 75,
 		},
 	},
-	/* LGC\011 L17L3PB0 Battery Information */
-	/*
-	 * Battery info provided by ODM on b/143477210, comment #11
-	 */
-	[BATTERY_LGC011] = {
+	/* LGC AP18C8K Battery Information */
+	 [BATTERY_LGC_AP18C8K] = {
 		.fuel_gauge = {
-			.manuf_name = "LGC",
+			.manuf_name = "LGC KT0030G020",
 			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x10, 0x10 },
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.reg_addr = 0x43,
+				.reg_mask = 0x0001,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0002,
+				.cfet_off_val = 0x0000,
+			},
+		},
+		.batt_info = {
+			.voltage_max            = 13050,
+			.voltage_normal         = 11250,
+			.voltage_min            = 9000,
+			.precharge_current      = 256,
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 50,
+			.charging_min_c         = 0,
+			.charging_max_c         = 60,
+			.discharging_min_c      = -20,
+			.discharging_max_c      = 75,
+		},
+	},
+	/* COSMX AP20CBL Battery Information */
+	 [BATTERY_COSMX_AP20CBL] = {
+		.fuel_gauge = {
+			.manuf_name = "COSMX KT0030B002",
+			.device_name = "AP20CBL",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
 			},
 			.fet = {
+				.mfgacc_support = 1,
 				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			}
+				.reg_mask = 0x2000,
+				.disconnect_val = 0x2000,
+			},
 		},
 		.batt_info = {
-			.voltage_max		= TARGET_WITH_MARGIN(13200, 5),
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 75,
+			.voltage_max            = 13200,
+			.voltage_normal         = 11550,
+			.voltage_min            = 9000,
+			.precharge_current      = 256,
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 50,
+			.charging_min_c         = 0,
+			.charging_max_c         = 60,
+			.discharging_min_c      = -20,
+			.discharging_max_c      = 75,
 		},
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
 
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_LGC011;
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_AP19B8M;
diff --git a/board/voxel/board.c b/board/voxel/board.c
index 6f6b1824fb..9faef2db6b 100644
--- a/board/voxel/board.c
+++ b/board/voxel/board.c
@@ -1,24 +1,23 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Volteer board-specific configuration */
-#include "bb_retimer.h"
-#include "button.h"
-#include "common.h"
 #include "accelgyro.h"
+#include "button.h"
 #include "cbi_ec_fw_config.h"
+#include "common.h"
 #include "driver/accel_bma2x2.h"
 #include "driver/accelgyro_bmi160.h"
 #include "driver/als_tcs3400.h"
 #include "driver/bc12/pi3usb9201.h"
 #include "driver/ppc/syv682x.h"
+#include "driver/retimer/bb_retimer_public.h"
+#include "driver/sync.h"
+#include "driver/tcpm/rt1715.h"
 #include "driver/tcpm/tcpci.h"
 #include "driver/tcpm/tusb422.h"
-#include "driver/tcpm/rt1715.h"
-#include "driver/retimer/bb_retimer.h"
-#include "driver/sync.h"
 #include "extpower.h"
 #include "fan.h"
 #include "fan_chip.h"
@@ -32,8 +31,8 @@
 #include "pwm_chip.h"
 #include "switch.h"
 #include "system.h"
-#include "task.h"
 #include "tablet_mode.h"
+#include "task.h"
 #include "throttle_ap.h"
 #include "uart.h"
 #include "usb_mux.h"
@@ -43,12 +42,56 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#include "gpio_list.h" /* Must come after other header files. */
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
+
+static const struct ec_response_keybd_config zbu_new_kb = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,
+		TK_REFRESH,
+		TK_FULLSCREEN,
+		TK_OVERVIEW,
+		TK_SNAPSHOT,
+		TK_BRIGHTNESS_DOWN,
+		TK_BRIGHTNESS_UP,
+		TK_VOL_MUTE,
+		TK_VOL_DOWN,
+		TK_VOL_UP,
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+static const struct ec_response_keybd_config zbu_old_kb = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_FORWARD,		/* T2 */
+		TK_REFRESH,		/* T3 */
+		TK_FULLSCREEN,		/* T4 */
+		TK_OVERVIEW,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	if (get_board_id() > 2)
+		return &zbu_new_kb;
+	else
+		return &zbu_old_kb;
+}
 
 /* Keyboard scan setting */
-struct keyboard_scan_config keyscan_config = {
+__override struct keyboard_scan_config keyscan_config = {
 	/* Increase from 50 us, because KSO_02 passes through the H1. */
 	.output_settle_us = 80,
 	/* Other values should be the same as the default configuration. */
@@ -63,6 +106,33 @@ struct keyboard_scan_config keyscan_config = {
 	},
 };
 
+/*
+ * We have total 30 pins for keyboard connecter {-1, -1} mean
+ * the N/A pin that don't consider it and reserve index 0 area
+ * that we don't have pin 0.
+ */
+const int keyboard_factory_scan_pins[][2] = {
+	{ -1, -1 }, { 0, 5 },	{ 1, 1 }, { 1, 0 },   { 0, 6 },	  { 0, 7 },
+	{ -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 },   { -1, -1 }, { 1, 6 },
+	{ 1, 7 },   { 3, 1 },	{ 2, 0 }, { 1, 5 },   { 2, 6 },	  { 2, 7 },
+	{ 2, 1 },   { 2, 4 },	{ 2, 5 }, { 1, 2 },   { 2, 3 },	  { 2, 2 },
+	{ 3, 0 },   { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 },	  { -1, -1 },
+	{ -1, -1 },
+};
+const int keyboard_factory_scan_pins_used =
+	ARRAY_SIZE(keyboard_factory_scan_pins);
+
+__override uint32_t board_override_feature_flags0(uint32_t flags0)
+{
+	/*
+	 * Remove keyboard backlight feature for devices that don't support it.
+	 */
+	if (!ec_cfg_has_keyboard_backlight())
+		return (flags0 & ~EC_FEATURE_MASK_0(EC_FEATURE_PWM_KEYB));
+	else
+		return flags0;
+}
+
 /******************************************************************************/
 /*
  * FW_CONFIG defaults for Voxel if the CBI data is not initialized.
@@ -76,7 +146,7 @@ union volteer_cbi_fw_config fw_config_defaults = {
 
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
@@ -87,11 +157,13 @@ const struct fan_conf fan_conf_0 = {
  * Minimum speed not specified by RPM. Set minimum RPM to max speed (with
  * margin) x 30%.
  *    5900 x 1.07 x 0.30 = 1894, round up to 1900
+ * reference that temperature and fan settings
+ * are derived from data in b/167523658#39
  */
 const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 1900,
-	.rpm_start = 1900,
-	.rpm_max = 5900,
+	.rpm_min = 2100,
+	.rpm_start = 2100,
+	.rpm_max = 5800,
 };
 
 const struct fan_t fans[FAN_CH_COUNT] = {
@@ -105,51 +177,31 @@ const struct fan_t fans[FAN_CH_COUNT] = {
 /* EC thermal management configuration */
 
 /*
- * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
- * 130 C.  However, sensor is located next to DDR, so we need to use the lower
- * DDR temperature limit (85 C)
+ * Reference that temperature and fan settings
+ * are derived from data in b/167523658#39
  */
-const static struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(35),
-	.temp_fan_max = C_TO_K(50),
-};
-
 /*
- * Inductor limits - used for both charger and PP3300 regulator
- *
- * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
- *
- * Charger max recommended temperature 100C, max absolute temperature 125C
- * PP3300 regulator: operating range -40 C to 145 C
- *
- * Inductors: limit of 125c
- * PCB: limit is 80c
+ * TODO(b/202062363): Remove when clang is fixed.
  */
-const static struct ec_thermal_config thermal_inductor = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(55),
-};
-
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(85), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(68), \
+		}, \
+		.temp_fan_off = C_TO_K(25), \
+		.temp_fan_max = C_TO_K(90), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 
 struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_CHARGER]			= thermal_inductor,
-	[TEMP_SENSOR_2_PP3300_REGULATOR]	= thermal_inductor,
-	[TEMP_SENSOR_3_DDR_SOC]			= thermal_cpu,
-	[TEMP_SENSOR_4_FAN]			= thermal_cpu,
+	[TEMP_SENSOR_1_CHARGER] = THERMAL_CPU,
+	[TEMP_SENSOR_2_PP3300_REGULATOR] = THERMAL_CPU,
+	[TEMP_SENSOR_3_DDR_SOC] = THERMAL_CPU,
+	[TEMP_SENSOR_4_FAN] = THERMAL_CPU,
 };
 BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
 
@@ -243,13 +295,15 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
 static void kb_backlight_enable(void)
 {
-	gpio_set_level(GPIO_EC_KB_BL_EN, 1);
+	if (ec_cfg_has_keyboard_backlight())
+		gpio_set_level(GPIO_EC_KB_BL_EN, 1);
 }
 DECLARE_HOOK(HOOK_CHIPSET_RESUME, kb_backlight_enable, HOOK_PRIO_DEFAULT);
 
 static void kb_backlight_disable(void)
 {
-	gpio_set_level(GPIO_EC_KB_BL_EN, 0);
+	if (ec_cfg_has_keyboard_backlight())
+		gpio_set_level(GPIO_EC_KB_BL_EN, 0);
 }
 DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, kb_backlight_disable, HOOK_PRIO_DEFAULT);
 
@@ -260,12 +314,12 @@ static void setup_board_tcpc(void)
 
 	if (board_id == 0) {
 		/* config typec C0 prot TUSB422 TCPC */
-		tcpc_config[USBC_PORT_C0].i2c_info.addr_flags
-			= TUSB422_I2C_ADDR_FLAGS;
+		tcpc_config[USBC_PORT_C0].i2c_info.addr_flags =
+			TUSB422_I2C_ADDR_FLAGS;
 		tcpc_config[USBC_PORT_C0].drv = &tusb422_tcpm_drv;
 		/* config typec C1 prot TUSB422 TCPC */
-		tcpc_config[USBC_PORT_C1].i2c_info.addr_flags
-			= TUSB422_I2C_ADDR_FLAGS;
+		tcpc_config[USBC_PORT_C1].i2c_info.addr_flags =
+			TUSB422_I2C_ADDR_FLAGS;
 		tcpc_config[USBC_PORT_C1].drv = &tusb422_tcpm_drv;
 	}
 }
@@ -278,11 +332,6 @@ void board_reset_pd_mcu(void)
 	 */
 }
 
-__override void board_cbi_init(void)
-{
-	setup_board_tcpc();
-}
-
 /******************************************************************************/
 /* USB-A charging control */
 
@@ -297,11 +346,13 @@ struct ppc_config_t ppc_chips[] = {
 		.i2c_port = I2C_PORT_USB_C0,
 		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
 		.drv = &syv682x_drv,
+		.frs_en = GPIO_USB_C0_FRS_EN,
 	},
 	[USBC_PORT_C1] = {
 		.i2c_port = I2C_PORT_USB_C1,
 		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
 		.drv = &syv682x_drv,
+		.frs_en = GPIO_USB_C1_FRS_EN,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
@@ -317,11 +368,29 @@ void ppc_interrupt(enum gpio_signal signal)
 		break;
 	case GPIO_USB_C1_PPC_INT_ODL:
 		syv682x_interrupt(USBC_PORT_C1);
+		break;
 	default:
 		break;
 	}
 }
 
+/* Disable FRS on boards with the SYV682A. FRS only works on the SYV682B. */
+void setup_board_ppc(void)
+{
+	uint8_t board_id = get_board_id();
+
+	if (board_id < 2) {
+		ppc_chips[USBC_PORT_C0].frs_en = 0;
+		ppc_chips[USBC_PORT_C1].frs_en = 0;
+	}
+}
+
+__override void board_cbi_init(void)
+{
+	setup_board_tcpc();
+	setup_board_ppc();
+}
+
 /******************************************************************************/
 /* BC1.2 charger detect configuration */
 const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
@@ -346,7 +415,6 @@ struct tcpc_config_t tcpc_config[] = {
 			.addr_flags = RT1715_I2C_ADDR_FLAGS,
 		},
 		.drv = &rt1715_tcpm_drv,
-		.usb23 = USBC_PORT_0_USB2_NUM | (USBC_PORT_0_USB3_NUM << 4),
 	},
 	[USBC_PORT_C1] = {
 		.bus_type = EC_BUS_TYPE_I2C,
@@ -355,7 +423,6 @@ struct tcpc_config_t tcpc_config[] = {
 			.addr_flags = RT1715_I2C_ADDR_FLAGS,
 		},
 		.drv = &rt1715_tcpm_drv,
-		.usb23 = USBC_PORT_1_USB2_NUM | (USBC_PORT_1_USB3_NUM << 4),
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
@@ -363,30 +430,43 @@ BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
 
 /******************************************************************************/
 /* USBC mux configuration - Tiger Lake includes internal mux */
-struct usb_mux usbc0_usb4_db_retimer = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &bb_usb_retimer,
-	.i2c_port = I2C_PORT_USB_0_MIX,
-	.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
+struct usb_mux_chain usbc0_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
-struct usb_mux usbc1_usb4_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &bb_usb_retimer,
-	.i2c_port = I2C_PORT_USB_1_MIX,
-	.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
+struct usb_mux_chain usbc1_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
-struct usb_mux usb_muxes[] = {
+
+struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc0_usb4_db_retimer,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_0_MIX,
+			.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc0_tcss_usb_mux,
 	},
 	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc1_usb4_db_retimer,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_1_MIX,
+			.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc1_tcss_usb_mux,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
diff --git a/board/voxel/board.h b/board/voxel/board.h
index 9f81e1da5b..1b866a5749 100644
--- a/board/voxel/board.h
+++ b/board/voxel/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,7 +13,7 @@
 
 /* Optional features */
 #undef NPCX7_PWM1_SEL
-#define NPCX7_PWM1_SEL    0    /* GPIO C2 is not used as PWM1. */
+#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */
 
 /*
  * The RAM and flash size combination on the the NPCX797FC does not leave
@@ -21,8 +21,6 @@
  */
 #undef CONFIG_CHIP_INIT_ROM_REGION
 
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
-
 #define CONFIG_VBOOT_EFS2
 
 #define CONFIG_POWER_BUTTON
@@ -32,66 +30,79 @@
 
 /* Chipset features */
 #define CONFIG_POWER_PP5000_CONTROL
+#define CONFIG_CPU_PROCHOT_GATE_ON_C10
 
 /* LED defines */
 #define CONFIG_LED_ONOFF_STATES
 
 /* Keyboard features */
+#define CONFIG_KEYBOARD_FACTORY_TEST
+#define CONFIG_KEYBOARD_REFRESH_ROW3
+
+/* Keyboard backliht */
+#define CONFIG_PWM
+#define CONFIG_PWM_KBLIGHT
 
 /* Sensors */
+#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
 /* BMI160 Base accel/gyro */
 #define CONFIG_ACCELGYRO_BMI160
+#define CONFIG_ACCELGYRO_ICM426XX /* Base accel second source*/
+#define CONFIG_ACCELGYRO_ICM42607 /* Base accel second source*/
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+#define CONFIG_ACCELGYRO_ICM42607_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+/* Lid operates in forced mode, base in FIFO */
+#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
 
 /* BMA253 Lid accel */
+#define CONFIG_ACCEL_KX022 /* Lid accel */
 #define CONFIG_ACCEL_BMA255
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE	BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID	LID_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
 
 /* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
 
-/*
- * USB-C port's USB2 & USB3 mapping from schematics
- * USB2 numbering on PCH - 1 to n
- * USB3 numbering on AP - 0 to n (PMC's USB3 numbering for MUX
- * configuration is - 1 to n hence add +1)
- */
-#define USBC_PORT_0_USB2_NUM	9
-#define USBC_PORT_0_USB3_NUM	1
-#define USBC_PORT_1_USB2_NUM	4
-#define USBC_PORT_1_USB3_NUM	2
-
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
 
 /*
  * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
  * cables only support up to 60W.
  */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 45000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
+
+#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
+#ifdef BOARD_VOXEL_ECMODEENTRY
+#undef CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
+#endif
 
 /* Enabling Thunderbolt-compatible mode */
 #define CONFIG_USB_PD_TBT_COMPAT_MODE
 
 /* Enabling USB4 mode */
 #define CONFIG_USB_PD_USB4
-#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR	0x40
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x41
+#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x40
+#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x41
+#define CONFIG_USB_PD_DATA_RESET_MSG
 
 /* USB Type A Features */
-#define USB_PORT_COUNT			1
+#define USB_PORT_COUNT 1
 #define CONFIG_USB_PORT_POWER_DUMB
 
 /* USBC PPC*/
-#define CONFIG_USBC_PPC_SYV682X		/* USBC port C0/C1 */
+#define CONFIG_USBC_PPC_SYV682X /* USBC port C0/C1 */
+#define CONFIG_USB_PD_FRS_PPC
 
 /* BC 1.2 */
 
@@ -103,8 +114,8 @@
 /* Fan features */
 
 /* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 
 /*
  * Macros for GPIO signals used in common code that don't match the
@@ -112,47 +123,44 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_DSW_PWROK		GPIO_EC_PCH_DSW_PWROK
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD		GPIO_PG_EC_RSMRST_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
-#define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE_L
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_LID_OPEN GPIO_EC_LID_OPEN
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
 
 /* I2C Bus Configuration */
 #define CONFIG_I2C
-#define I2C_PORT_ACCEL		I2C_PORT_SENSOR
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_0_MIX	NPCX_I2C_PORT3_0
-#define I2C_PORT_USB_1_MIX	NPCX_I2C_PORT4_1
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_0_MIX NPCX_I2C_PORT3_0
+#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT4_1
+#define I2C_PORT_POWER NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
 
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-#define CONFIG_I2C_MASTER
+#define I2C_PORT_BATTERY I2C_PORT_POWER
+#define I2C_PORT_CHARGER I2C_PORT_EEPROM
 
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+#define CONFIG_I2C_CONTROLLER
 
 #ifndef __ASSEMBLER__
 
@@ -161,15 +169,12 @@
 
 enum battery_type {
 	BATTERY_AP19B8M,
-	BATTERY_LGC011,
+	BATTERY_LGC_AP18C8K,
+	BATTERY_COSMX_AP20CBL,
 	BATTERY_TYPE_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_FAN,
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_FAN, PWM_CH_KBLIGHT, PWM_CH_COUNT };
 
 enum sensor_id {
 	LID_ACCEL = 0,
@@ -178,14 +183,12 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 void board_reset_pd_mcu(void);
 
+void motion_interrupt(enum gpio_signal signal);
+
 #endif /* !__ASSEMBLER__ */
 
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/voxel/build.mk b/board/voxel/build.mk
index 838d6a16ce..c994631759 100644
--- a/board/voxel/build.mk
+++ b/board/voxel/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/voxel/ec.tasklist b/board/voxel/ec.tasklist
index 292de51cdb..ebcf47c499 100644
--- a/board/voxel/ec.tasklist
+++ b/board/voxel/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,7 +15,8 @@
 	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
 	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
 	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
 	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
 	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
 	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
diff --git a/board/voxel/gpio.inc b/board/voxel/gpio.inc
index 3d8c61dceb..171288a639 100644
--- a/board/voxel/gpio.inc
+++ b/board/voxel/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,7 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
@@ -25,7 +25,7 @@ GPIO_INT(PG_EC_DSW_PWROK,      PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
 GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4),  GPIO_INT_BOTH, power_signal_interrupt)
 
 /* Sensor Interrupts */
-GPIO_INT(EC_IMU_INT_L,         PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, bmi160_interrupt)
+GPIO_INT(EC_IMU_INT_L,         PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, motion_interrupt)
 GPIO(EC_ALS_RGB_INT_L,         PIN(D, 4), GPIO_INPUT | GPIO_PULL_UP)	/* unused */
 GPIO_INT(TABLET_MODE_L,        PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
 /*
@@ -77,10 +77,10 @@ GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
 GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
 GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
 GPIO_INT(EC_PROCHOT_IN_L,      PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
+GPIO_INT(CPU_C10_GATE_L,       PIN(6, 7), GPIO_INT_RISING, throttle_ap_c10_input_interrupt)
 GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
 
 GPIO(EC_PCH_INT_ODL,           PIN(B, 0), GPIO_ODR_HIGH)
-GPIO(CPU_C10_GATE_L,           PIN(6, 7), GPIO_INPUT)
 
 /* USB and USBC Signals */
 GPIO(EN_PP5000_USBA,		PIN(3, 5), GPIO_OUT_LOW)	/* Enable USB-A charging - all ports */
@@ -181,3 +181,6 @@ ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)  /* GPIO00 =
                                                                        GPIO01 = H1_EC_PWR_BTN_ODL
                                                                        GPIO02 = EC_RST_ODL */
 
+/* Temperature sensors */
+ALTERNATE(PIN_MASK(4, BIT(2) | BIT(4) | BIT(5)), 0, MODULE_ADC, 0) /* TEMP_SENSOR1,2,4 */
+ALTERNATE(PIN_MASK(F, BIT(1)), 0, MODULE_ADC, 0) /* TEMP_SENSOR3 */
diff --git a/board/voxel/led.c b/board/voxel/led.c
index 8ad3e9c1f8..acd00f8941 100644
--- a/board/voxel/led.c
+++ b/board/voxel/led.c
@@ -1,44 +1,50 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Power and battery LED control for Volteer
  */
 
+#include "chipset.h"
 #include "ec_commands.h"
 #include "gpio.h"
 #include "led_common.h"
 #include "led_onoff_states.h"
-#include "chipset.h"
 
 #define LED_ON_LVL 0
 #define LED_OFF_LVL 1
 
-const int led_charge_lvl_1 = 5;
+__override const int led_charge_lvl_1 = 5;
 
-const int led_charge_lvl_2 = 95;
+__override const int led_charge_lvl_2 = 95;
 
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-void led_set_color_battery(enum ec_led_colors color)
+__override void led_set_color_battery(enum ec_led_colors color)
 {
 	switch (color) {
 	case EC_LED_COLOR_AMBER:
diff --git a/board/voxel/sensors.c b/board/voxel/sensors.c
index fab1fac66b..81e6b13b57 100644
--- a/board/voxel/sensors.c
+++ b/board/voxel/sensors.c
@@ -1,24 +1,31 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Volteer family-specific sensor configuration */
-#include "common.h"
 #include "accelgyro.h"
+#include "cbi_ec_fw_config.h"
+#include "cbi_ssfc.h"
+#include "common.h"
 #include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi_common.h"
+#include "driver/accel_kionix.h"
 #include "driver/accelgyro_bmi160.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "driver/accelgyro_icm42607.h"
+#include "driver/accelgyro_icm426xx.h"
+#include "driver/accelgyro_icm_common.h"
 #include "driver/als_tcs3400.h"
 #include "driver/sync.h"
-#include "keyboard_scan.h"
+#include "gpio.h"
 #include "hooks.h"
 #include "i2c.h"
-#include "task.h"
+#include "keyboard_scan.h"
 #include "tablet_mode.h"
+#include "task.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ##args)
 /******************************************************************************/
 /* Sensors */
 static struct mutex g_lid_accel_mutex;
@@ -26,21 +33,142 @@ static struct mutex g_base_mutex;
 
 /* BMA253 private data */
 static struct accelgyro_saved_data_t g_bma253_data;
+static struct kionix_accel_data g_kx022_data;
 
 /* BMI160 private data */
 static struct bmi_drv_data_t g_bmi160_data;
+static struct icm_drv_data_t g_icm426xx_data;
 
 /* Rotation matrix for the lid accelerometer */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
+
+const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+				       { FLOAT_TO_FP(-1), 0, 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
+
+static const mat33_fp_t base_icm_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					 { 0, FLOAT_TO_FP(1), 0 },
+					 { 0, 0, FLOAT_TO_FP(1) } };
+
+struct motion_sensor_t kx022_lid_accel = {
+	.name = "Lid Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_KX022,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_LID,
+	.drv = &kionix_accel_drv,
+	.mutex = &g_lid_accel_mutex,
+	.drv_data = &g_kx022_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = KX022_ADDR0_FLAGS,
+	.rot_standard_ref = &lid_standard_ref,
+	.min_frequency = KX022_ACCEL_MIN_FREQ,
+	.max_frequency = KX022_ACCEL_MAX_FREQ,
+	.default_range = 2, /* g, to support tablet mode */
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	},
+};
+
+struct motion_sensor_t icm426xx_base_accel = {
+	.name = "Base Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
+	.rot_standard_ref = &base_icm_ref,
+	.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
+	.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+	},
+};
+
+struct motion_sensor_t icm426xx_base_gyro = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &base_icm_ref,
+	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
+	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
+};
+
+struct motion_sensor_t icm42607_base_accel = {
+	.name = "Base Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM42607,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm42607_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
+	.default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
+	.rot_standard_ref = &base_icm_ref,
+	.min_frequency = ICM42607_ACCEL_MIN_FREQ,
+	.max_frequency = ICM42607_ACCEL_MAX_FREQ,
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+	},
 };
 
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
+struct motion_sensor_t icm42607_base_gyro = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM42607,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm42607_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &base_icm_ref,
+	.min_frequency = ICM42607_GYRO_MIN_FREQ,
+	.max_frequency = ICM42607_GYRO_MAX_FREQ,
 };
 
 struct motion_sensor_t motion_sensors[] = {
@@ -118,32 +246,54 @@ struct motion_sensor_t motion_sensors[] = {
 };
 unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
+static enum ec_ssfc_base_sensor base_gyro_config = SSFC_SENSOR_BASE_DEFAULT;
+
 static void board_sensors_init(void)
 {
-	/* Note - BMA253 interrupt unused by EC */
+	base_gyro_config = get_cbi_ssfc_base_sensor();
+
+	if (ec_cfg_has_tabletmode()) {
+		if (base_gyro_config == SSFC_SENSOR_BASE_ICM426XX) {
+			motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
+			motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
+			ccprints("BASE GYRO is ICM426XX");
+		} else if (base_gyro_config == SSFC_SENSOR_BASE_ICM42607) {
+			motion_sensors[BASE_ACCEL] = icm42607_base_accel;
+			motion_sensors[BASE_GYRO] = icm42607_base_gyro;
+			ccprints("BASE GYRO is ICM42607");
+		} else
+			ccprints("BASE GYRO is BMI160");
 
-	/* Enable interrupt for the BMI160 accel/gyro sensor */
-	gpio_enable_interrupt(GPIO_EC_IMU_INT_L);
+		if (get_cbi_ssfc_lid_sensor() == SSFC_SENSOR_LID_KX022) {
+			motion_sensors[LID_ACCEL] = kx022_lid_accel;
+			ccprints("LID_ACCEL is KX022");
+		} else
+			ccprints("LID_ACCEL is BMA253");
 
-	CPRINTS("Motion Sensor Count = %d", motion_sensor_count);
+		motion_sensor_count = ARRAY_SIZE(motion_sensors);
+		/* Enable interrupt for the accel/gyro sensor */
+		gpio_enable_interrupt(GPIO_EC_IMU_INT_L);
+	} else {
+		motion_sensor_count = 0;
+		gmr_tablet_switch_disable();
+		/* Base accel is not stuffed, don't allow line to float */
+		gpio_set_flags(GPIO_EC_IMU_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
+	}
 }
 DECLARE_HOOK(HOOK_INIT, board_sensors_init, HOOK_PRIO_DEFAULT);
 
-#ifndef TEST_BUILD
-void lid_angle_peripheral_enable(int enable)
+void motion_interrupt(enum gpio_signal signal)
 {
-	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
-
-	if (enable) {
-		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
-	} else {
-		/*
-		 * Ensure that the chipset is off before disabling the keyboard.
-		 * When the chipset is on, the EC keeps the keyboard enabled and
-		 * the AP decides whether to ignore input devices or not.
-		 */
-		if (!chipset_in_s0)
-			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
+	switch (base_gyro_config) {
+	case SSFC_SENSOR_BASE_ICM426XX:
+		icm426xx_interrupt(signal);
+		break;
+	case SSFC_SENSOR_BASE_ICM42607:
+		icm42607_interrupt(signal);
+		break;
+	case SSFC_SENSOR_BASE_BMI160:
+	default:
+		bmi160_interrupt(signal);
+		break;
 	}
 }
-#endif
diff --git a/board/voxel/vif_override.xml b/board/voxel/vif_override.xml
new file mode 100644
index 0000000000..3875c2851f
--- /dev/null
+++ b/board/voxel/vif_override.xml
@@ -0,0 +1,158 @@
+<?xml version="1.0" encoding="utf-8"?>
+<vif:VIF xmlns="http://usb.org/VendorInfoFile.xsd">
+  <vif:Model_Part_Number>Voxel</vif:Model_Part_Number>
+  <vif:Product_Revision>0</vif:Product_Revision>
+  <vif:TID>0</vif:TID>
+  <vif:Product>
+    <!-- Information about TGL USB4 provided by Intel. See b/172963736 -->
+    <vif:USB4_Num_Internal_Host_Controllers value="1" />
+    <vif:USB4_Num_PCIe_DN_Bridges value="0" />
+    <vif:USB4RouterList>
+      <vif:Usb4Router>
+        <vif:USB4_Router_ID value="1" />
+        <vif:USB4_Silicon_VID value="32903">8087</vif:USB4_Silicon_VID>
+        <vif:USB4_Num_Lane_Adapters value="4" />
+        <vif:USB4_Num_USB3_DN_Adapters value="1" />
+        <vif:USB4_Num_DP_IN_Adapters value="1" />
+        <vif:USB4_Num_DP_OUT_Adapters value="0" />
+        <vif:USB4_Num_PCIe_DN_Adapters value="4" />
+        <vif:USB4_TBT3_Not_Supported value="0">TBT3 Compatible</vif:USB4_TBT3_Not_Supported>
+        <vif:USB4_PCIe_Wake_Supported value="true" />
+        <vif:USB4_USB3_Wake_Supported value="false" />
+        <vif:USB4_Num_Unused_Adapters value="0" />
+        <vif:USB4_TBT3_VID value="32903">8087</vif:USB4_TBT3_VID>
+        <vif:USB4_PCIe_Switch_Vendor_ID value="32902">8086</vif:USB4_PCIe_Switch_Vendor_ID>
+        <vif:USB4_PCIe_Switch_Device_ID value="39451">9A1B</vif:USB4_PCIe_Switch_Device_ID>
+      </vif:Usb4Router>
+      <vif:Usb4Router>
+        <vif:USB4_Router_ID value="0" />
+        <vif:USB4_Silicon_VID value="32903">8087</vif:USB4_Silicon_VID>
+        <vif:USB4_Num_Lane_Adapters value="2" />
+        <vif:USB4_Num_USB3_DN_Adapters value="1" />
+        <vif:USB4_Num_DP_IN_Adapters value="0" />
+        <vif:USB4_Num_DP_OUT_Adapters value="0" />
+        <vif:USB4_Num_PCIe_DN_Adapters value="0" />
+        <vif:USB4_TBT3_Not_Supported value="1">Not TBT3-Compatible</vif:USB4_TBT3_Not_Supported>
+        <vif:USB4_PCIe_Wake_Supported value="false" />
+        <vif:USB4_USB3_Wake_Supported value="false" />
+        <vif:USB4_Num_Unused_Adapters value="0" />
+      </vif:Usb4Router>
+    </vif:USB4RouterList>
+  </vif:Product>
+  <vif:Component>
+    <vif:USB4_Max_Speed value="1">Gen 3 (40Gb)</vif:USB4_Max_Speed>
+    <vif:USB4_DFP_Supported value="true" />
+    <vif:USB4_UFP_Supported value="false" />
+    <vif:USB4_USB3_Tunneling_Supported value="true" />
+    <vif:USB4_DP_Tunneling_Supported value="true" />
+    <vif:USB4_PCIe_Tunneling_Supported value="true" />
+    <vif:USB4_TBT3_Compatibility_Supported value="true" />
+    <vif:USB4_CL1_State_Supported value="true" />
+    <vif:USB4_CL2_State_Supported value="true" />
+    <vif:USB4_Num_Retimers value="1" />
+    <vif:USB4_DP_Bit_Rate value="3">HBR3</vif:USB4_DP_Bit_Rate>
+    <vif:USB4_Num_DP_Lanes value="4">4 Lanes</vif:USB4_Num_DP_Lanes>
+    <vif:USB4_Lane_0_Adapter value="1" />
+    <vif:Host_Supports_USB_Data value="true" />
+    <vif:Host_Speed value="2">USB 3.2 Gen 2x1</vif:Host_Speed>
+    <vif:Host_Contains_Captive_Retimer value="true" />
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:Host_Suspend_Supported value="true" />
+    <vif:Is_DFP_On_Hub value="false" />
+    <vif:USB_Suspend_May_Be_Cleared value="true" />
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="3">3A @ 5V</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <vif:FR_Swap_Supported_As_Initial_Sink value="true" />
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!-- Add in missing fields for SrcPdo0, derived from SYV682B datasheet. -->
+        <vif:Src_PD_OCP_OC_Debounce value="50">50 msec</vif:Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="360">3600 mA</vif:Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+    <vif:Data_Capable_As_USB_Host_SOP value="true" />
+    <vif:Data_Capable_As_USB_Device_SOP value="false" />
+    <!-- TODO(b/173028252): Figure out the appropriate Discover Identity ACK for
+         Volteer and update the EC and VIF accordingly. -->
+    <vif:Product_Type_UFP_SOP value="3">PSD</vif:Product_Type_UFP_SOP>
+    <vif:Product_Type_DFP_SOP value="4">Alternate Mode Controller (AMC)</vif:Product_Type_DFP_SOP>
+    <vif:DFP_VDO_Port_Number value="0" />
+    <vif:Modal_Operation_Supported_SOP value="true" />
+    <vif:USB_VID_SOP value="6353">18D1</vif:USB_VID_SOP>
+    <vif:bcdDevice_SOP value="0">0000</vif:bcdDevice_SOP>
+    <vif:SVID_Fixed_SOP value="true" />
+    <vif:Num_SVIDs_Min_SOP value="1" />
+    <vif:Num_SVIDs_Max_SOP value="1" />
+    <vif:SOPSVIDList>
+      <vif:SOPSVID>
+        <vif:SVID_SOP value="32903">8087</vif:SVID_SOP>
+        <vif:SVID_Modes_Fixed_SOP value="true" />
+        <vif:SVID_Num_Modes_Min_SOP value="1" />
+        <vif:SVID_Num_Modes_Max_SOP value="1" />
+        <vif:SOPSVIDModeList>
+          <vif:SOPSVIDMode>
+            <vif:SVID_Mode_Enter_SOP value="true" />
+            <vif:SVID_Mode_Recog_Value_SOP value="0">00000000</vif:SVID_Mode_Recog_Value_SOP>
+          </vif:SOPSVIDMode>
+        </vif:SOPSVIDModeList>
+      </vif:SOPSVID>
+    </vif:SOPSVIDList>
+  </vif:Component>
+  <vif:Component>
+    <vif:USB4_Max_Speed value="1">Gen 3 (40Gb)</vif:USB4_Max_Speed>
+    <vif:USB4_DFP_Supported value="true" />
+    <vif:USB4_UFP_Supported value="false" />
+    <vif:USB4_USB3_Tunneling_Supported value="true" />
+    <vif:USB4_DP_Tunneling_Supported value="true" />
+    <vif:USB4_PCIe_Tunneling_Supported value="true" />
+    <vif:USB4_TBT3_Compatibility_Supported value="true" />
+    <vif:USB4_CL1_State_Supported value="true" />
+    <vif:USB4_CL2_State_Supported value="true" />
+    <vif:USB4_Num_Retimers value="1" />
+    <vif:USB4_DP_Bit_Rate value="3">HBR3</vif:USB4_DP_Bit_Rate>
+    <vif:USB4_Num_DP_Lanes value="4">4 Lanes</vif:USB4_Num_DP_Lanes>
+    <vif:USB4_Lane_0_Adapter value="1" />
+    <vif:Host_Supports_USB_Data value="true" />
+    <vif:Host_Speed value="2">USB 3.2 Gen 2x1</vif:Host_Speed>
+    <vif:Host_Contains_Captive_Retimer value="true" />
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:Host_Suspend_Supported value="true" />
+    <vif:Is_DFP_On_Hub value="false" />
+    <vif:USB_Suspend_May_Be_Cleared value="true" />
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="3">3A @ 5V</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <vif:FR_Swap_Supported_As_Initial_Sink value="true" />
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!-- Add in missing fields for SrcPdo0, derived from SYV682B datasheet. -->
+        <vif:Src_PD_OCP_OC_Debounce value="50">50 msec</vif:Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="360">3600 mA</vif:Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+    <vif:Data_Capable_As_USB_Host_SOP value="true" />
+    <vif:Data_Capable_As_USB_Device_SOP value="false" />
+    <!-- TODO(b/173028252): Figure out the appropriate Discover Identity ACK for
+         Volteer and update the EC and VIF accordingly. -->
+    <vif:Product_Type_UFP_SOP value="3">PSD</vif:Product_Type_UFP_SOP>
+    <vif:Product_Type_DFP_SOP value="4">Alternate Mode Controller (AMC)</vif:Product_Type_DFP_SOP>
+    <vif:DFP_VDO_Port_Number value="1" />
+    <vif:Modal_Operation_Supported_SOP value="true" />
+    <vif:USB_VID_SOP value="6353">18D1</vif:USB_VID_SOP>
+    <vif:bcdDevice_SOP value="0">0000</vif:bcdDevice_SOP>
+    <vif:SVID_Fixed_SOP value="true" />
+    <vif:Num_SVIDs_Min_SOP value="1" />
+    <vif:Num_SVIDs_Max_SOP value="1" />
+    <vif:SOPSVIDList>
+      <vif:SOPSVID>
+        <vif:SVID_SOP value="32903">8087</vif:SVID_SOP>
+        <vif:SVID_Modes_Fixed_SOP value="true" />
+        <vif:SVID_Num_Modes_Min_SOP value="1" />
+        <vif:SVID_Num_Modes_Max_SOP value="1" />
+        <vif:SOPSVIDModeList>
+          <vif:SOPSVIDMode>
+            <vif:SVID_Mode_Enter_SOP value="true" />
+            <vif:SVID_Mode_Recog_Value_SOP value="0">00000000</vif:SVID_Mode_Recog_Value_SOP>
+          </vif:SOPSVIDMode>
+        </vif:SOPSVIDModeList>
+      </vif:SOPSVID>
+    </vif:SOPSVIDList>
+  </vif:Component>
+</vif:VIF>
diff --git a/board/voxel_ecmodeentry b/board/voxel_ecmodeentry
new file mode 120000
index 0000000000..082df00bc3
--- /dev/null
+++ b/board/voxel_ecmodeentry
@@ -0,0 +1 @@
+voxel
\ No newline at end of file
diff --git a/board/waddledee/battery.c b/board/waddledee/battery.c
index 6b77248624..37b2dd2e3d 100644
--- a/board/waddledee/battery.c
+++ b/board/waddledee/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -279,6 +279,8 @@ const struct board_batt_params board_battery_info[] = {
 				.reg_addr = 0x43,
 				.reg_mask = 0x0001,
 				.disconnect_val = 0x0,
+				.cfet_mask = 0x0002,
+				.cfet_off_val = 0x0,
 			},
 		},
 		.batt_info = {
diff --git a/board/waddledee/board.c b/board/waddledee/board.c
index b85ce0cd97..229573eb42 100644
--- a/board/waddledee/board.c
+++ b/board/waddledee/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,16 +8,16 @@
 #include "adc_chip.h"
 #include "button.h"
 #include "charge_manager.h"
-#include "charge_state_v2.h"
+#include "charge_state.h"
 #include "charger.h"
 #include "driver/accel_kionix.h"
 #include "driver/accelgyro_lsm6dsm.h"
 #include "driver/bc12/pi3usb9201.h"
 #include "driver/charger/sm5803.h"
 #include "driver/retimer/tusb544.h"
-#include "driver/temp_sensor/thermistor.h"
 #include "driver/tcpm/anx7447.h"
 #include "driver/tcpm/it83xx_pd.h"
+#include "driver/temp_sensor/thermistor.h"
 #include "driver/usb_mux/it5205.h"
 #include "gpio.h"
 #include "hooks.h"
@@ -32,7 +32,7 @@
 #include "system.h"
 #include "tablet_mode.h"
 #include "task.h"
-#include "tcpci.h"
+#include "tcpm/tcpci.h"
 #include "temp_sensor.h"
 #include "uart.h"
 #include "usb_charge.h"
@@ -40,7 +40,7 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
 
 #define INT_RECHECK_US 5000
 
@@ -53,7 +53,7 @@ DECLARE_DEFERRED(check_c0_line);
 
 static void notify_c0_chips(void)
 {
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
 	sm5803_interrupt(0);
 }
 
@@ -88,7 +88,7 @@ DECLARE_DEFERRED(check_c1_line);
 static void notify_c1_chips(void)
 {
 	schedule_deferred_pd_interrupt(1);
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12, 0);
+	usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
 	sm5803_interrupt(1);
 }
 
@@ -127,34 +127,26 @@ static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH0
-	},
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH2
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH3
-	},
-	[ADC_SUB_ANALOG] = {
-		.name = "SUB_ANALOG",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH13
-	},
+	[ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH0 },
+	[ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH2 },
+	[ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH3 },
+	[ADC_SUB_ANALOG] = { .name = "SUB_ANALOG",
+			     .factor_mul = ADC_MAX_MVOLT,
+			     .factor_div = ADC_READ_MAX + 1,
+			     .shift = 0,
+			     .channel = CHIP_ADC_CH13 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
@@ -204,27 +196,36 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 };
 
 /* USB Retimer */
-const struct usb_mux usbc1_retimer = {
-	.usb_port = 1,
-	.i2c_port = I2C_PORT_SUB_USB_C1,
-	.i2c_addr_flags = TUSB544_I2C_ADDR_FLAGS0,
-	.driver = &tusb544_drv,
+const struct usb_mux_chain usbc1_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = 1,
+			.i2c_port = I2C_PORT_SUB_USB_C1,
+			.i2c_addr_flags = TUSB544_I2C_ADDR_FLAGS0,
+			.driver = &tusb544_drv,
+		},
 };
 
 /* USB Muxes */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+			},
 	},
 	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = AN7447_TCPC0_I2C_ADDR_FLAGS,
-		.driver = &anx7447_usb_mux_driver,
-		.next_mux = &usbc1_retimer,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_SUB_USB_C1,
+				.i2c_addr_flags = AN7447_TCPC0_I2C_ADDR_FLAGS,
+				.driver = &anx7447_usb_mux_driver,
+			},
+		.next = &usbc1_retimer,
 	},
 };
 
@@ -239,7 +240,6 @@ void board_init(void)
 		c1_int_line = GPIO_USB_C1_INT_V1_ODL;
 	}
 
-
 	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
 	gpio_enable_interrupt(c1_int_line);
 
@@ -247,10 +247,8 @@ void board_init(void)
 	 * If interrupt lines are already low, schedule them to be processed
 	 * after inits are completed.
 	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL))
-		hook_call_deferred(&check_c0_line_data, 0);
-	if (!gpio_get_level(c1_int_line))
-		hook_call_deferred(&check_c1_line_data, 0);
+	check_c0_line();
+	check_c1_line();
 
 	gpio_enable_interrupt(GPIO_USB_C0_CCSBU_OVP_ODL);
 	/* Enable Base Accel interrupt */
@@ -264,7 +262,8 @@ void board_init(void)
 	sm5803_configure_gpio0(CHARGER_SECONDARY, GPIO0_MODE_OUTPUT, 0);
 
 	/* Turn on 5V if the system is on, otherwise turn it off */
-	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND);
+	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
+			      CHIPSET_STATE_SOFT_OFF);
 	board_power_5v_enable(on);
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
@@ -343,18 +342,6 @@ uint16_t tcpc_get_alert_status(void)
 	return status;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
-			    int charge_mv)
-{
-	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
-
-	/*
-	 * TODO(b/151955431): Characterize the input current limit in case a
-	 * scaling needs to be applied here
-	 */
-	charge_set_input_current_limit(icl, charge_mv);
-}
-
 int board_set_active_charge_port(int port)
 {
 	int is_valid_port = (port >= 0 && port < board_get_usb_pd_port_count());
@@ -404,9 +391,8 @@ void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
 		gpio_set_level(GPIO_EN_USB_C0_CC2_VCONN, !!enabled);
 }
 
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
+__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+				       int *ki_div, int *kd, int *kd_div)
 {
 	*kp = 3;
 	*kp_div = 14;
@@ -464,7 +450,7 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Sensor Data */
-static struct kionix_accel_data  g_kx022_data;
+static struct kionix_accel_data g_kx022_data;
 static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
 
 /* Drivers */
@@ -504,8 +490,6 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_base_mutex,
 		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
 				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
 		.port = I2C_PORT_SENSOR,
 		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
 		.rot_standard_ref = NULL,
@@ -533,8 +517,6 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_base_mutex,
 		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
 				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
 		.port = I2C_PORT_SENSOR,
 		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
 		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
@@ -548,20 +530,19 @@ const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
 /* Thermistors */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
-#ifndef TEST_BUILD
 /* This callback disables keyboard when convertibles are fully open */
-void lid_angle_peripheral_enable(int enable)
+__override void lid_angle_peripheral_enable(int enable)
 {
 	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
 
@@ -585,4 +566,3 @@ void lid_angle_peripheral_enable(int enable)
 			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
 	}
 }
-#endif
diff --git a/board/waddledee/board.h b/board/waddledee/board.h
index 5540fdcbe7..1ac3fc76da 100644
--- a/board/waddledee/board.h
+++ b/board/waddledee/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,13 +24,16 @@
 #define CONFIG_BC12_DETECT_PI3USB9201
 
 /* Charger */
-#define CONFIG_CHARGER_SM5803		/* C0 and C1: Charger */
+#define CONFIG_CHARGER_SM5803 /* C0 and C1: Charger */
+#define PD_MAX_VOLTAGE_MV 15000
 #define CONFIG_USB_PD_VBUS_DETECT_CHARGER
 #define CONFIG_USB_PD_5V_CHARGER_CTRL
 #define CONFIG_CHARGER_OTG
-#undef  CONFIG_CHARGER_SINGLE_CHIP
+#undef CONFIG_CHARGER_SINGLE_CHIP
 #define CONFIG_OCPC
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr */
+#define CONFIG_OCPC_DEF_RBATT_MOHMS               \
+	21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr \
+	    */
 
 /*
  * GPIO for C1 interrupts, for baseboard use
@@ -47,12 +50,13 @@
 #define CONFIG_PWM
 
 /* Sensors */
-#define CONFIG_ACCEL_KX022		/* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM	/* Base accel */
+#define CONFIG_ACCEL_KX022 /* Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
+#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 /* Sensors without hardware FIFO are in forced mode */
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
 
-#define CONFIG_ACCEL_INTERRUPTS
 /* Enable sensor fifo, must also define the _SIZE and _THRES */
 #define CONFIG_ACCEL_FIFO
 /* Power of 2 - Too large of a fifo causes too much timestamp jitter */
@@ -70,21 +74,20 @@
 
 /* TCPC */
 #define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP	/* C0: ITE EC TCPC */
-#define CONFIG_USB_PD_TCPM_ANX7447	/* C1: ANX TCPC + Mux */
+#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0: ITE EC TCPC */
+#define CONFIG_USB_PD_TCPM_ANX7447 /* C1: ANX TCPC + Mux */
 #define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1
 
 /* Thermistors */
 #define CONFIG_TEMP_SENSOR
 #define CONFIG_THERMISTOR
 #define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_PP3300_A
 
 /* USB Mux and Retimer */
-#define CONFIG_USB_MUX_IT5205			/* C1: ITE Mux */
-#define I2C_PORT_USB_MUX I2C_PORT_USB_C0	/* Required for ITE Mux */
+#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */
 
-#define CONFIG_USBC_RETIMER_TUSB544		/* C1 Redriver: TUSB544 */
+#define CONFIG_USBC_RETIMER_TUSB544 /* C1 Redriver: TUSB544 */
 
 #ifndef __ASSEMBLER__
 
@@ -106,27 +109,18 @@ enum pwm_channel {
 };
 
 /* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
 /* ADC channels */
 enum adc_channel {
-	ADC_VSNS_PP3300_A,     /* ADC0 */
-	ADC_TEMP_SENSOR_1,     /* ADC2 */
-	ADC_TEMP_SENSOR_2,     /* ADC3 */
-	ADC_SUB_ANALOG,        /* ADC13 */
+	ADC_VSNS_PP3300_A, /* ADC0 */
+	ADC_TEMP_SENSOR_1, /* ADC2 */
+	ADC_TEMP_SENSOR_2, /* ADC3 */
+	ADC_SUB_ANALOG, /* ADC13 */
 	ADC_CH_COUNT
 };
 
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_COUNT
-};
+enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
@@ -143,8 +137,6 @@ enum battery_type {
 	BATTERY_TYPE_COUNT,
 };
 
-int board_is_sourcing_vbus(int port);
-
 #endif /* !__ASSEMBLER__ */
 
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/waddledee/build.mk b/board/waddledee/build.mk
index 00e4e0bb5d..9b862c7624 100644
--- a/board/waddledee/build.mk
+++ b/board/waddledee/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -11,5 +11,5 @@ CHIP_FAMILY:=it8320
 CHIP_VARIANT:=it8320dx
 BASEBOARD:=dedede
 
-board-y=board.o led.o usb_pd_policy.o
+board-y=board.o cbi_ssfc.o led.o usb_pd_policy.o
 board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/waddledee/cbi_ssfc.c b/board/waddledee/cbi_ssfc.c
new file mode 100644
index 0000000000..81f3ee0dad
--- /dev/null
+++ b/board/waddledee/cbi_ssfc.c
@@ -0,0 +1,36 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi_ssfc.h"
+#include "common.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "hooks.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+/* Cache SSFC on init since we don't expect it to change in runtime */
+static union dedede_cbi_ssfc cached_ssfc;
+BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
+
+static void cbi_ssfc_init(void)
+{
+	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
+		/* Default to 0 when CBI isn't populated */
+		cached_ssfc.raw_value = 0;
+
+	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
+}
+DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
+
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
+{
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
+}
+
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
+{
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
+}
diff --git a/board/waddledee/cbi_ssfc.h b/board/waddledee/cbi_ssfc.h
new file mode 100644
index 0000000000..bf8853a43a
--- /dev/null
+++ b/board/waddledee/cbi_ssfc.h
@@ -0,0 +1,59 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _DEDEDE_CBI_SSFC__H_
+#define _DEDEDE_CBI_SSFC__H_
+
+#include "stdint.h"
+
+/****************************************************************************
+ * Dedede CBI Second Source Factory Cache
+ */
+
+/*
+ * Base Sensor (Bits 0-2)
+ */
+enum ec_ssfc_base_sensor {
+	SSFC_SENSOR_BASE_DEFAULT = 0,
+	SSFC_SENSOR_BMI160 = 1,
+	SSFC_SENSOR_ICM426XX = 2,
+	SSFC_SENSOR_LSM6DSM = 3,
+	SSFC_SENSOR_ICM42607 = 4
+};
+
+/*
+ * Lid Sensor (Bits 3-5)
+ */
+enum ec_ssfc_lid_sensor {
+	SSFC_SENSOR_LID_DEFAULT = 0,
+	SSFC_SENSOR_BMA255 = 1,
+	SSFC_SENSOR_KX022 = 2,
+	SSFC_SENSOR_LIS2DWL = 3
+};
+
+union dedede_cbi_ssfc {
+	struct {
+		uint32_t base_sensor : 3;
+		uint32_t lid_sensor : 3;
+		uint32_t reserved_2 : 26;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Get the Base sensor type from SSFC_CONFIG.
+ *
+ * @return the Base sensor board type.
+ */
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
+
+/**
+ * Get the Lid sensor type from SSFC_CONFIG.
+ *
+ * @return the Lid sensor board type.
+ */
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
+
+#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/waddledee/ec.tasklist b/board/waddledee/ec.tasklist
index 75181a4531..c3c360febb 100644
--- a/board/waddledee/ec.tasklist
+++ b/board/waddledee/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,13 +12,13 @@
 	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
 	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
 	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, TRENTA_TASK_STACK_SIZE) \
 	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
 	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
 	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, ULTRA_TASK_STACK_SIZE) \
         TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
         TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
         TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/waddledee/gpio.inc b/board/waddledee/gpio.inc
index 3ce80593a7..b0c8d8cd03 100644
--- a/board/waddledee/gpio.inc
+++ b/board/waddledee/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -37,8 +37,8 @@ GPIO_INT(USB_C0_CCSBU_OVP_ODL,	PIN(K, 6), GPIO_INT_FALLING | GPIO_PULL_UP, c0_cc
 /* Other interrupts */
 GPIO_INT(LID_OPEN,		PIN(F, 3), GPIO_INT_BOTH, lid_interrupt)
 GPIO_INT(LID_360_L,		PIN(A, 7), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-GPIO_INT(VOLDN_BTN_ODL,		PIN(I, 6), GPIO_INT_BOTH, button_interrupt)
-GPIO_INT(VOLUP_BTN_ODL,		PIN(I, 7), GPIO_INT_BOTH, button_interrupt)
+GPIO_INT(VOLDN_BTN_ODL,		PIN(I, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(VOLUP_BTN_ODL,		PIN(I, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
 GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(J, 0), GPIO_INT_FALLING | GPIO_SEL_1P8V, lsm6dsm_interrupt)
 GPIO_INT(EC_WP_OD,		PIN(A, 6), GPIO_INT_BOTH, switch_interrupt)
 
@@ -100,7 +100,7 @@ GPIO(EC_SUB_IO_2_2, PIN(L, 2), GPIO_INPUT)
 /* Misc */
 GPIO(EN_BL_OD,			PIN(K, 4), GPIO_ODR_LOW)
 GPIO(EC_ENTERING_RW,		PIN(G, 0), GPIO_OUT_LOW)
-GPIO(CCD_MODE_ODL,		PIN(H, 5), GPIO_INPUT)
+GPIO(CCD_MODE_ODL,		PIN(H, 5), GPIO_ODR_HIGH)
 GPIO(EC_BATTERY_PRES_ODL,	PIN(I, 4), GPIO_INPUT)
 GPIO(PEN_DET_ODL,		PIN(J, 1), GPIO_INPUT | GPIO_PULL_UP)
 GPIO(EN_KB_BL,			PIN(J, 3), GPIO_OUT_LOW) /* Currently unused */
diff --git a/board/waddledee/led.c b/board/waddledee/led.c
index b19e594fbd..1a2bc16898 100644
--- a/board/waddledee/led.c
+++ b/board/waddledee/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,14 +19,14 @@ const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 /*
  * Board has one physical LED with red, green, and blue
  */
-struct pwm_led led_color_map[EC_LED_COLOR_COUNT] = {
-				/* Red, Green, Blue */
-	[EC_LED_COLOR_RED]    = { 100,   0,   0 },
-	[EC_LED_COLOR_GREEN]  = {   0, 100,   0 },
-	[EC_LED_COLOR_BLUE]   = {   0,   0, 100 },
-	[EC_LED_COLOR_YELLOW] = {  50,  50,   0 },
-	[EC_LED_COLOR_WHITE]  = {  50,  50,  50 },
-	[EC_LED_COLOR_AMBER]  = {  70,  30,   0 },
+struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = {
+	/* Red, Green, Blue */
+	[EC_LED_COLOR_RED] = { 100, 0, 0 },
+	[EC_LED_COLOR_GREEN] = { 0, 100, 0 },
+	[EC_LED_COLOR_BLUE] = { 0, 0, 100 },
+	[EC_LED_COLOR_YELLOW] = { 50, 50, 0 },
+	[EC_LED_COLOR_WHITE] = { 50, 50, 50 },
+	[EC_LED_COLOR_AMBER] = { 70, 30, 0 },
 };
 
 /* One logical LED with red, green, and blue channels. */
diff --git a/board/waddledee/usb_pd_policy.c b/board/waddledee/usb_pd_policy.c
index 9d53f20047..2433b25431 100644
--- a/board/waddledee/usb_pd_policy.c
+++ b/board/waddledee/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,8 +13,8 @@
 #include "driver/tcpm/tcpci.h"
 #include "usb_pd.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
@@ -38,11 +38,6 @@ void pd_power_supply_reset(int port)
 	if (prev_en)
 		sm5803_set_vbus_disch(port, 1);
 
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	/* Give back the current quota we are no longer using */
-	charge_manager_source_port(port, 0);
-#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
-
 	/* Notify host of power info change. */
 	pd_send_host_event(PD_EVENT_POWER_CHANGE);
 }
@@ -62,11 +57,6 @@ int pd_set_power_supply_ready(int port)
 	/* Provide Vbus */
 	charger_enable_otg_power(port, 1);
 
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	/* Ensure we advertise the proper available current quota */
-	charge_manager_source_port(port, 1);
-#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
-
 	/* Notify host of power info change. */
 	pd_send_host_event(PD_EVENT_POWER_CHANGE);
 
@@ -75,18 +65,7 @@ int pd_set_power_supply_ready(int port)
 
 __override bool pd_check_vbus_level(int port, enum vbus_level level)
 {
-	int vbus_voltage;
-
-	/* If we're unable to speak to the charger, best to guess false */
-	if (charger_get_vbus_voltage(port, &vbus_voltage))
-		return false;
-
-	if (level == VBUS_SAFE0V)
-		return vbus_voltage < PD_V_SAFE0V_MAX;
-	else if (level == VBUS_PRESENT)
-		return vbus_voltage > PD_V_SAFE5V_MIN;
-	else
-		return vbus_voltage < PD_V_SINK_DISCONNECT_MAX;
+	return sm5803_check_vbus_level(port, level);
 }
 
 int pd_snk_is_vbus_provided(int port)
diff --git a/board/waddledee/vif_override.xml b/board/waddledee/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/waddledee/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/waddledoo/battery.c b/board/waddledoo/battery.c
index 64af3b4302..29eac40158 100644
--- a/board/waddledoo/battery.c
+++ b/board/waddledoo/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/waddledoo/board.c b/board/waddledoo/board.c
index fb5c51a0a6..80234defdf 100644
--- a/board/waddledoo/board.c
+++ b/board/waddledoo/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,7 +9,7 @@
 #include "button.h"
 #include "cbi_fw_config.h"
 #include "charge_manager.h"
-#include "charge_state_v2.h"
+#include "charge_state.h"
 #include "charger.h"
 #include "chipset.h"
 #include "common.h"
@@ -42,34 +42,81 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-static void tcpc_alert_event(enum gpio_signal s)
-{
-	int port = (s == GPIO_USB_C0_INT_ODL) ? 0 : 1;
+#define INT_RECHECK_US 5000
 
-	schedule_deferred_pd_interrupt(port);
-}
+/* C0 interrupt line shared by BC 1.2 and charger */
+static void check_c0_line(void);
+DECLARE_DEFERRED(check_c0_line);
 
-static void usb_c0_interrupt(enum gpio_signal s)
+static void notify_c0_chips(void)
 {
 	/*
 	 * The interrupt line is shared between the TCPC and BC 1.2 detection
 	 * chip.  Therefore we'll need to check both ICs.
 	 */
-	tcpc_alert_event(s);
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
+	schedule_deferred_pd_interrupt(0);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
 }
 
-static void sub_usb_c1_interrupt(enum gpio_signal s)
+static void check_c0_line(void)
 {
 	/*
-	 * The interrupt line is shared between the TCPC and BC 1.2 detection
-	 * chip.  Therefore we'll need to check both ICs.
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		notify_c0_chips();
+		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+	}
+}
+
+static void usb_c0_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c0_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c0_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+}
+
+/* C1 interrupt line shared by BC 1.2, TCPC, and charger */
+static void check_c1_line(void);
+DECLARE_DEFERRED(check_c1_line);
+
+static void notify_c1_chips(void)
+{
+	schedule_deferred_pd_interrupt(1);
+	usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+}
+
+static void check_c1_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips.
 	 */
-	tcpc_alert_event(s);
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12, 0);
+	if (!gpio_get_level(GPIO_SUB_C1_INT_EN_RAILS_ODL)) {
+		notify_c1_chips();
+		hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
+	}
+}
+
+static void sub_usb_c1_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c1_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c1_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
 }
 
 static void sub_hdmi_hpd_interrupt(enum gpio_signal s)
@@ -79,6 +126,7 @@ static void sub_hdmi_hpd_interrupt(enum gpio_signal s)
 	gpio_set_level(GPIO_EC_AP_USB_C1_HDMI_HPD, !hdmi_hpd_odl);
 }
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /* ADC channels */
@@ -118,20 +166,23 @@ void board_init(void)
 {
 	int on;
 
+	/* Enable C0 interrupt and check if it needs processing */
 	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
+	check_c0_line();
 
 	if (get_cbi_fw_config_db() == DB_1A_HDMI) {
 		/* Disable i2c on HDMI pins */
-		gpio_config_pin(MODULE_I2C,
-				GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL, 0);
-		gpio_config_pin(MODULE_I2C,
-				GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL, 0);
+		gpio_config_pin(MODULE_I2C, GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL,
+				0);
+		gpio_config_pin(MODULE_I2C, GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL,
+				0);
 
 		/* Set HDMI and sub-rail enables to output */
 		gpio_set_flags(GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL,
 			       chipset_in_state(CHIPSET_STATE_ON) ?
-						GPIO_ODR_LOW : GPIO_ODR_HIGH);
-		gpio_set_flags(GPIO_SUB_C1_INT_EN_RAILS_ODL,   GPIO_ODR_HIGH);
+				       GPIO_ODR_LOW :
+				       GPIO_ODR_HIGH);
+		gpio_set_flags(GPIO_SUB_C1_INT_EN_RAILS_ODL, GPIO_ODR_HIGH);
 
 		/* Select HDMI option */
 		gpio_set_level(GPIO_HDMI_SEL_L, 0);
@@ -140,17 +191,18 @@ void board_init(void)
 		gpio_enable_interrupt(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL);
 	} else {
 		/* Set SDA as an input */
-		gpio_set_flags(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL,
-			       GPIO_INPUT);
+		gpio_set_flags(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL, GPIO_INPUT);
 
-		/* Enable C1 interrupts */
+		/* Enable C1 interrupt and check if it needs processing */
 		gpio_enable_interrupt(GPIO_SUB_C1_INT_EN_RAILS_ODL);
+		check_c1_line();
 	}
 	/* Enable gpio interrupt for base accelgyro sensor */
 	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
 
 	/* Turn on 5V if the system is on, otherwise turn it off. */
-	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND);
+	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
+			      CHIPSET_STATE_SOFT_OFF);
 	board_power_5v_enable(on);
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
@@ -177,8 +229,8 @@ void board_hibernate(void)
 	 * entering the Z-state.
 	 */
 	if (board_get_charger_chip_count() > 1)
-		raa489000_hibernate(1);
-	raa489000_hibernate(0);
+		raa489000_hibernate(1, true);
+	raa489000_hibernate(0, true);
 }
 
 void board_reset_pd_mcu(void)
@@ -189,38 +241,43 @@ void board_reset_pd_mcu(void)
 	 */
 }
 
+#ifdef BOARD_WADDLEDOO
 static void reconfigure_5v_gpio(void)
 {
 	/*
-	 * b/147257497: On early boards, GPIO_EN_PP5000 was swapped with
-	 * GPIO_VOLUP_BTN_ODL. Therefore, we'll actually need to set that GPIO
-	 * instead for those boards.  Note that this breaks the volume up button
-	 * functionality.
+	 * b/147257497: On early waddledoo boards, GPIO_EN_PP5000 was swapped
+	 * with GPIO_VOLUP_BTN_ODL. Therefore, we'll actually need to set that
+	 * GPIO instead for those boards.  Note that this breaks the volume up
+	 * button functionality.
 	 */
 	if (system_get_board_version() < 0) {
 		CPRINTS("old board - remapping 5V en");
 		gpio_set_flags(GPIO_VOLUP_BTN_ODL, GPIO_OUT_LOW);
 	}
 }
-DECLARE_HOOK(HOOK_INIT, reconfigure_5v_gpio, HOOK_PRIO_INIT_I2C+1);
+DECLARE_HOOK(HOOK_INIT, reconfigure_5v_gpio, HOOK_PRIO_INIT_I2C + 1);
+#endif /* BOARD_WADDLEDOO */
 
 static void set_5v_gpio(int level)
 {
 	int version;
-	enum gpio_signal gpio;
+	enum gpio_signal gpio = GPIO_EN_PP5000;
 
 	/*
-	 * b/147257497: On early boards, GPIO_EN_PP5000 was swapped with
-	 * GPIO_VOLUP_BTN_ODL. Therefore, we'll actually need to set that GPIO
-	 * instead for those boards.  Note that this breaks the volume up button
-	 * functionality.
+	 * b/147257497: On early waddledoo boards, GPIO_EN_PP5000 was swapped
+	 * with GPIO_VOLUP_BTN_ODL. Therefore, we'll actually need to set that
+	 * GPIO instead for those boards.  Note that this breaks the volume up
+	 * button functionality.
 	 */
-	version = system_get_board_version();
+	if (IS_ENABLED(BOARD_WADDLEDOO)) {
+		version = system_get_board_version();
 
-	/*
-	 * If the CBI EEPROM wasn't formatted, assume it's a very early board.
-	 */
-	gpio = version < 0 ? GPIO_VOLUP_BTN_ODL : GPIO_EN_PP5000;
+		/*
+		 * If the CBI EEPROM wasn't formatted, assume it's a very early
+		 * board.
+		 */
+		gpio = version < 0 ? GPIO_VOLUP_BTN_ODL : GPIO_EN_PP5000;
+	}
 
 	gpio_set_level(gpio, level);
 }
@@ -239,10 +296,9 @@ __override void board_power_5v_enable(int enable)
 		gpio_set_level(GPIO_SUB_C1_INT_EN_RAILS_ODL, !enable);
 	} else {
 		if (isl923x_set_comparator_inversion(1, !!enable))
-			CPRINTS("Failed to %sable sub rails!", enable ?
-								"en" : "dis");
+			CPRINTS("Failed to %sable sub rails!",
+				enable ? "en" : "dis");
 	}
-
 }
 
 __override uint8_t board_get_usb_pd_port_count(void)
@@ -267,13 +323,11 @@ int board_is_sourcing_vbus(int port)
 
 	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
 	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
-
 }
 
 int board_set_active_charge_port(int port)
 {
-	int is_real_port = (port >= 0 &&
-			    port < board_get_usb_pd_port_count());
+	int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count());
 	int i;
 	int old_port;
 
@@ -286,9 +340,11 @@ int board_set_active_charge_port(int port)
 
 	/* Disable all ports. */
 	if (port == CHARGE_PORT_NONE) {
-		for (i = 0; i < board_get_usb_pd_port_count(); i++)
+		for (i = 0; i < board_get_usb_pd_port_count(); i++) {
 			tcpc_write(i, TCPC_REG_COMMAND,
 				   TCPC_REG_COMMAND_SNK_CTRL_LOW);
+			raa489000_enable_asgate(i, false);
+		}
 
 		return EC_SUCCESS;
 	}
@@ -310,6 +366,7 @@ int board_set_active_charge_port(int port)
 		if (tcpc_write(i, TCPC_REG_COMMAND,
 			       TCPC_REG_COMMAND_SNK_CTRL_LOW))
 			CPRINTS("p%d: sink path disable failed.", i);
+		raa489000_enable_asgate(i, false);
 	}
 
 	/*
@@ -320,7 +377,8 @@ int board_set_active_charge_port(int port)
 		charger_discharge_on_ac(1);
 
 	/* Enable requested charge port. */
-	if (tcpc_write(port, TCPC_REG_COMMAND,
+	if (raa489000_enable_asgate(port, true) ||
+	    tcpc_write(port, TCPC_REG_COMMAND,
 		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
 		CPRINTS("p%d: sink path enable failed.", port);
 		charger_discharge_on_ac(0);
@@ -333,16 +391,12 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
 {
-	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
+	if (port < 0 || port > board_get_usb_pd_port_count())
+		return;
 
-	/*
-	 * TODO(b:147463641): Characterize the input current limit in case that
-	 * a scaling needs to be applied here.
-	 */
-	charge_set_input_current_limit(icl, charge_mv);
+	raa489000_set_output_current(port, rp);
 }
 
 /* Sensors */
@@ -350,17 +404,13 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrices to rotate accelerometers into the standard reference. */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					     { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
 
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					      { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
 
 static struct accelgyro_saved_data_t g_bma253_data;
 static struct bmi_drv_data_t g_bmi160_data;
@@ -436,29 +486,15 @@ struct motion_sensor_t motion_sensors[] = {
 
 const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
+__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+				       int *ki_div, int *kd, int *kd_div)
 {
-	/*
-	 * Early boards need different constants due to a change in charger IC
-	 * silicon revision.
-	 */
-	if (system_get_board_version() >= 0) {
-		*kp = 1;
-		*kp_div = 128;
-		*ki = 1;
-		*ki_div = 1024;
-		*kd = 0;
-		*kd_div = 1;
-	} else {
-		*kp = 1;
-		*kp_div = 4;
-		*ki = 1;
-		*ki_div = 15;
-		*kd = 1;
-		*kd_div = 10;
-	}
+	*kp = 1;
+	*kp_div = 20;
+	*ki = 1;
+	*ki_div = 250;
+	*kd = 0;
+	*kd_div = 1;
 }
 
 int pd_snk_is_vbus_provided(int port)
@@ -538,25 +574,34 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usbc1_retimer = {
-	.usb_port = 1,
-	.i2c_port = I2C_PORT_SUB_USB_C1,
-	.i2c_addr_flags = NB7V904M_I2C_ADDR0,
-	.driver = &nb7v904m_usb_redriver_drv,
+const struct usb_mux_chain usbc1_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = 1,
+			.i2c_port = I2C_PORT_SUB_USB_C1,
+			.i2c_addr_flags = NB7V904M_I2C_ADDR0,
+			.driver = &nb7v904m_usb_redriver_drv,
+		},
 };
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
-		.driver = &pi3usb3x532_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
+				.driver = &pi3usb3x532_usb_mux_driver,
+			},
 	},
 	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
-		.driver = &pi3usb3x532_usb_mux_driver,
-		.next_mux = &usbc1_retimer,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_SUB_USB_C1,
+				.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
+				.driver = &pi3usb3x532_usb_mux_driver,
+			},
+		.next = &usbc1_retimer,
 	}
 };
 
@@ -582,7 +627,7 @@ uint16_t tcpc_get_alert_status(void)
 	}
 
 	if (board_get_usb_pd_port_count() > 1 &&
-				!gpio_get_level(GPIO_SUB_C1_INT_EN_RAILS_ODL)) {
+	    !gpio_get_level(GPIO_SUB_C1_INT_EN_RAILS_ODL)) {
 		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
 			/* TCPCI spec Rev 1.0 says to ignore bits 14:12. */
 			if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0))
@@ -596,9 +641,8 @@ uint16_t tcpc_get_alert_status(void)
 	return status;
 }
 
-#ifndef TEST_BUILD
 /* This callback disables keyboard when convertibles are fully open */
-void lid_angle_peripheral_enable(int enable)
+__override void lid_angle_peripheral_enable(int enable)
 {
 	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
 
@@ -622,4 +666,3 @@ void lid_angle_peripheral_enable(int enable)
 			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
 	}
 }
-#endif
diff --git a/board/waddledoo/board.h b/board/waddledoo/board.h
index 3f788e0392..a53507ecad 100644
--- a/board/waddledoo/board.h
+++ b/board/waddledoo/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,20 +17,42 @@
  */
 #define CONFIG_SYSTEM_UNLOCKED
 
+/* Save some flash space */
+#undef CONFIG_ACCEL_SPOOF_MODE
+#define CONFIG_CHIP_INIT_ROM_REGION
+#undef CONFIG_CONSOLE_CMDHELP
+#undef CONFIG_CONSOLE_HISTORY
+#define CONFIG_DEBUG_ASSERT_BRIEF
+#define CONFIG_USB_PD_DEBUG_LEVEL 0
+
+/* EC console commands */
+#define CONFIG_CMD_CHARGER_DUMP
+
+/* Remove default commands to free flash space */
+#undef CONFIG_CMD_ACCELSPOOF
+#undef CONFIG_CMD_BATTFAKE
+
 /* Battery */
 #define CONFIG_BATTERY_FUEL_GAUGE
 
 /* Charger */
 #define CONFIG_CHARGER_RAA489000
+#define PD_MAX_VOLTAGE_MV 20000
 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 #define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */
+#define CONFIG_OCPC_DEF_RBATT_MOHMS               \
+	22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \
+	    */
+/*
+ * b/147463641: The charger IC seems to overdraw ~4%, therefore we
+ * reduce our target accordingly.
+ */
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 4
 #define CONFIG_OCPC
-#undef  CONFIG_CHARGER_SINGLE_CHIP
-
-/* EC console commands */
-#define CONFIG_CMD_TCPC_DUMP
-#define CONFIG_CMD_CHARGER_DUMP
+#undef CONFIG_CHARGER_SINGLE_CHIP
+#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
+#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
 
 /*
  * GPIO for C1 interrupts, for baseboard use
@@ -57,7 +79,7 @@
 
 /* PWM */
 #define CONFIG_PWM
-#define NPCX7_PWM1_SEL    1  /* GPIO C2 is used as PWM1. */
+#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */
 
 /* USB */
 #define CONFIG_BC12_DETECT_PI3USB9201
@@ -76,17 +98,26 @@
 /* Variant references the TCPCs to determine Vbus sourcing */
 #define CONFIG_USB_PD_5V_EN_CUSTOM
 
+#undef PD_POWER_SUPPLY_TURN_ON_DELAY
+#undef PD_POWER_SUPPLY_TURN_OFF_DELAY
+#undef CONFIG_USBC_VCONN_SWAP_DELAY_US
+/* 20% margin added for these timings */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 13080 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 16080 /* us */
+#undef CONFIG_USBC_VCONN_SWAP_DELAY_US
+#define CONFIG_USBC_VCONN_SWAP_DELAY_US 787 /* us */
+
 /* I2C configuration */
-#define I2C_PORT_EEPROM     NPCX_I2C_PORT7_0
-#define I2C_PORT_BATTERY    NPCX_I2C_PORT5_0
-#define I2C_PORT_SENSOR     NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0     NPCX_I2C_PORT1_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
 #define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_MUX    I2C_PORT_USB_C0
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0
 /* TODO(b:147440290): Need to handle multiple charger ICs */
-#define I2C_PORT_CHARGER    I2C_PORT_USB_C0
+#define I2C_PORT_CHARGER I2C_PORT_USB_C0
 
-#define I2C_PORT_ACCEL      I2C_PORT_SENSOR
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
 
 #define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */
 
@@ -103,16 +134,15 @@
 #define CONFIG_CMD_ACCELS
 #define CONFIG_CMD_ACCEL_INFO
 
-#define CONFIG_ACCEL_BMA255		/* Lid accel */
-#define CONFIG_ACCELGYRO_BMI160		/* Base accel */
+#define CONFIG_ACCEL_BMA255 /* Lid accel */
+#define CONFIG_ACCELGYRO_BMI160 /* Base accel */
 
 /* Lid operates in forced mode, base in FIFO */
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
 #define CONFIG_ACCEL_FIFO
-#define CONFIG_ACCEL_FIFO_SIZE 256	/* Must be a power of 2 */
+#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */
 #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
 
-#define CONFIG_ACCEL_INTERRUPTS
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 
@@ -125,9 +155,6 @@
 #define CONFIG_TABLET_MODE_SWITCH
 #define CONFIG_GMR_TABLET_MODE
 
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_GPIO
-
 #ifndef __ASSEMBLER__
 
 #include "gpio_signal.h"
@@ -140,19 +167,14 @@ enum chg_id {
 };
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_1,     /* ADC0 */
-	ADC_TEMP_SENSOR_2,     /* ADC1 */
-	ADC_SUB_ANALOG,	       /* ADC2 */
-	ADC_VSNS_PP3300_A,     /* ADC9 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
+	ADC_SUB_ANALOG, /* ADC2 */
+	ADC_VSNS_PP3300_A, /* ADC9 */
 	ADC_CH_COUNT
 };
 
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
 enum pwm_channel {
 	PWM_CH_KBLIGHT,
@@ -167,7 +189,5 @@ enum battery_type {
 	BATTERY_TYPE_COUNT,
 };
 
-int board_is_sourcing_vbus(int port);
-
 #endif /* !__ASSEMBLER__ */
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/waddledoo/build.mk b/board/waddledoo/build.mk
index 3cbadc55d7..6f205ebcf4 100644
--- a/board/waddledoo/build.mk
+++ b/board/waddledoo/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -11,4 +11,4 @@ CHIP_FAMILY:=npcx7
 CHIP_VARIANT:=npcx7m6fc
 BASEBOARD:=dedede
 
-board-y=board.o battery.o led.o usb_pd_policy.o
+board-y=board.o battery.o cbi_ssfc.o led.o usb_pd_policy.o
diff --git a/board/waddledoo/cbi_ssfc.c b/board/waddledoo/cbi_ssfc.c
new file mode 100644
index 0000000000..81f3ee0dad
--- /dev/null
+++ b/board/waddledoo/cbi_ssfc.c
@@ -0,0 +1,36 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi_ssfc.h"
+#include "common.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "hooks.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+/* Cache SSFC on init since we don't expect it to change in runtime */
+static union dedede_cbi_ssfc cached_ssfc;
+BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
+
+static void cbi_ssfc_init(void)
+{
+	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
+		/* Default to 0 when CBI isn't populated */
+		cached_ssfc.raw_value = 0;
+
+	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
+}
+DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
+
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
+{
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
+}
+
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
+{
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
+}
diff --git a/board/waddledoo/cbi_ssfc.h b/board/waddledoo/cbi_ssfc.h
new file mode 100644
index 0000000000..bf8853a43a
--- /dev/null
+++ b/board/waddledoo/cbi_ssfc.h
@@ -0,0 +1,59 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _DEDEDE_CBI_SSFC__H_
+#define _DEDEDE_CBI_SSFC__H_
+
+#include "stdint.h"
+
+/****************************************************************************
+ * Dedede CBI Second Source Factory Cache
+ */
+
+/*
+ * Base Sensor (Bits 0-2)
+ */
+enum ec_ssfc_base_sensor {
+	SSFC_SENSOR_BASE_DEFAULT = 0,
+	SSFC_SENSOR_BMI160 = 1,
+	SSFC_SENSOR_ICM426XX = 2,
+	SSFC_SENSOR_LSM6DSM = 3,
+	SSFC_SENSOR_ICM42607 = 4
+};
+
+/*
+ * Lid Sensor (Bits 3-5)
+ */
+enum ec_ssfc_lid_sensor {
+	SSFC_SENSOR_LID_DEFAULT = 0,
+	SSFC_SENSOR_BMA255 = 1,
+	SSFC_SENSOR_KX022 = 2,
+	SSFC_SENSOR_LIS2DWL = 3
+};
+
+union dedede_cbi_ssfc {
+	struct {
+		uint32_t base_sensor : 3;
+		uint32_t lid_sensor : 3;
+		uint32_t reserved_2 : 26;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Get the Base sensor type from SSFC_CONFIG.
+ *
+ * @return the Base sensor board type.
+ */
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
+
+/**
+ * Get the Lid sensor type from SSFC_CONFIG.
+ *
+ * @return the Lid sensor board type.
+ */
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
+
+#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/waddledoo/ec.tasklist b/board/waddledoo/ec.tasklist
index 0aba1fabeb..ba5855412d 100644
--- a/board/waddledoo/ec.tasklist
+++ b/board/waddledoo/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/waddledoo/gpio.inc b/board/waddledoo/gpio.inc
index e6bc32af1e..6b55d890b2 100644
--- a/board/waddledoo/gpio.inc
+++ b/board/waddledoo/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -83,7 +83,7 @@ GPIO(EC_PROCHOT_ODL,	     PIN(F, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
 GPIO(EC_ENTERING_RW,	     PIN(E, 3), GPIO_OUT_LOW)
 GPIO(ALL_SYS_PWRGD,	     PIN(A, 0), GPIO_OUT_LOW)
 GPIO(SYS_RST_ODL,	     PIN(C, 5), GPIO_ODR_HIGH)
-GPIO(CCD_MODE_ODL,	     PIN(E, 5), GPIO_INPUT)
+GPIO(CCD_MODE_ODL,	     PIN(E, 5), GPIO_ODR_HIGH)
 
 GPIO(USB_C0_RST_ODL,	     PIN(9, 7), GPIO_OUT_HIGH) /* currently unused */
 GPIO(EC_AP_USB_C1_HDMI_HPD,  PIN(9, 6), GPIO_OUT_LOW)
diff --git a/board/waddledoo/led.c b/board/waddledoo/led.c
index ca9a05bd84..4315e0b87d 100644
--- a/board/waddledoo/led.c
+++ b/board/waddledoo/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,14 +19,11 @@ const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
  * We only have a white and an amber LED, so setting any other colour results in
  * both LEDs being off.
  */
-struct pwm_led led_color_map[EC_LED_COLOR_COUNT] = {
-				/* Amber, White */
-	[EC_LED_COLOR_RED]    = {   0,   0 },
-	[EC_LED_COLOR_GREEN]  = {   0,   0 },
-	[EC_LED_COLOR_BLUE]   = {   0,   0 },
-	[EC_LED_COLOR_YELLOW] = {   0,   0 },
-	[EC_LED_COLOR_WHITE]  = {   0, 100 },
-	[EC_LED_COLOR_AMBER]  = {  100,  0 },
+struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = {
+	/* Amber, White */
+	[EC_LED_COLOR_RED] = { 0, 0 },	   [EC_LED_COLOR_GREEN] = { 0, 0 },
+	[EC_LED_COLOR_BLUE] = { 0, 0 },	   [EC_LED_COLOR_YELLOW] = { 0, 0 },
+	[EC_LED_COLOR_WHITE] = { 0, 100 }, [EC_LED_COLOR_AMBER] = { 100, 0 },
 };
 
 /* One logical LED with amber and white channels. */
diff --git a/board/waddledoo/usb_pd_policy.c b/board/waddledoo/usb_pd_policy.c
index 905e049937..23166f7fca 100644
--- a/board/waddledoo/usb_pd_policy.c
+++ b/board/waddledoo/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,11 +7,12 @@
 #include "chipset.h"
 #include "common.h"
 #include "console.h"
+#include "driver/charger/isl923x_public.h"
 #include "driver/tcpm/tcpci.h"
 #include "usb_pd.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
@@ -24,11 +25,6 @@ void pd_power_supply_reset(int port)
 	/* Disable VBUS */
 	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
 
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	/* Give back the current quota we are no longer using */
-	charge_manager_source_port(port, 0);
-#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
-
 	/* Notify host of power info change. */
 	pd_send_host_event(PD_EVENT_POWER_CHANGE);
 }
@@ -54,10 +50,9 @@ int pd_set_power_supply_ready(int port)
 	if (rv)
 		return rv;
 
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	/* Ensure we advertise the proper available current quota */
-	charge_manager_source_port(port, 1);
-#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
+	rv = raa489000_enable_asgate(port, true);
+	if (rv)
+		return rv;
 
 	/* Notify host of power info change. */
 	pd_send_host_event(PD_EVENT_POWER_CHANGE);
diff --git a/board/waddledoo/vif_override.xml b/board/waddledoo/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/waddledoo/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/waddledoo2/battery.c b/board/waddledoo2/battery.c
new file mode 100644
index 0000000000..3696d4e38c
--- /dev/null
+++ b/board/waddledoo2/battery.c
@@ -0,0 +1,128 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+#include "battery.h"
+#include "battery_fuel_gauge.h"
+#include "common.h"
+#include "gpio.h"
+#include "util.h"
+
+/*
+ * Battery info for Waddledoo2 battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+		/* LGC AP18C8K Battery Information */
+	 [BATTERY_LGC_AP18C8K] = {
+		.fuel_gauge = {
+			.manuf_name = "LGC KT0030G020",
+			.device_name = "AP18C8K",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.reg_addr = 0x43,
+				.reg_mask = 0x0001,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0002,
+				.cfet_off_val = 0x0000,
+			},
+		},
+		.batt_info = {
+			.voltage_max            = 13050,
+			.voltage_normal         = 11250,
+			.voltage_min            = 9000,
+			.precharge_current      = 256,
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 50,
+			.charging_min_c         = 0,
+			.charging_max_c         = 60,
+			.discharging_min_c      = -20,
+			.discharging_max_c      = 75,
+		},
+	},
+	/* Murata AP18C4K Battery Information */
+	[BATTERY_MURATA_AP18C4K] = {
+		.fuel_gauge = {
+			.manuf_name = "Murata KT00304012",
+			.device_name = "AP18C4K",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.reg_addr = 0x0,
+				.reg_mask = 0x2000,
+				.disconnect_val = 0x2000,
+				.cfet_mask = 0x4000,
+				.cfet_off_val = 0x4000,
+			},
+		},
+		.batt_info = {
+			.voltage_max		= 13200,
+			.voltage_normal		= 11400,
+			.voltage_min		= 9000,
+			.precharge_current	= 256,
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 75,
+		},
+	},
+	/* AP19B8M */
+	[BATTERY_AP19B8M] = {
+		.fuel_gauge = {
+			.manuf_name = "LGC KT0030G024",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.reg_addr = 0x43,
+				.reg_mask = 0x0001,
+				.disconnect_val = 0x0,
+				.cfet_mask = 0x0002,
+				.cfet_off_val = 0x0000,
+			}
+		},
+		.batt_info = {
+			.voltage_max          = 13350,
+			.voltage_normal       = 11610,
+			.voltage_min          = 9000,
+			.precharge_current    = 256,
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 50,
+			.charging_min_c       = 0,
+			.charging_max_c       = 60,
+			.discharging_min_c    = -20,
+			.discharging_max_c    = 75,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_LGC_AP18C8K;
diff --git a/board/waddledoo2/board.c b/board/waddledoo2/board.c
new file mode 100644
index 0000000000..8a7a2b461d
--- /dev/null
+++ b/board/waddledoo2/board.c
@@ -0,0 +1,843 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Waddledoo2 board-specific configuration */
+
+#include "adc.h"
+#include "button.h"
+#include "cbi_fw_config.h"
+#include "cbi_ssfc.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "chipset.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "driver/accel_bma2x2.h"
+#include "driver/accel_kionix.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "driver/accelgyro_icm426xx.h"
+#include "driver/accelgyro_icm_common.h"
+#include "driver/bc12/pi3usb9201.h"
+#include "driver/charger/isl923x.h"
+#include "driver/retimer/ps8802.h"
+#include "driver/tcpm/raa489000.h"
+#include "driver/tcpm/tcpci.h"
+#include "driver/temp_sensor/thermistor.h"
+#include "driver/usb_mux/pi3usb3x532.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "keyboard_config.h"
+#include "keyboard_raw.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "motion_sense.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "stdbool.h"
+#include "switch.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "temp_sensor.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+#define INT_RECHECK_US 5000
+
+#define ADC_VOL_UP_MASK BIT(0)
+#define ADC_VOL_DOWN_MASK BIT(1)
+
+static uint8_t new_adc_key_state;
+
+static void ps8762_chaddr_deferred(void);
+DECLARE_DEFERRED(ps8762_chaddr_deferred);
+
+/******************************************************************************/
+/* USB-A Configuration */
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_USB_A0_VBUS,
+	GPIO_EN_USB_A1_VBUS,
+};
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/*
+	 * F3 key scan cycle completed but scan input is not
+	 * charging to logic high when EC start scan next
+	 * column for "T" key, so we set .output_settle_us
+	 * to 80us from 50us.
+	 */
+	.output_settle_us = 80,
+	.debounce_down_us = 9 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x1c, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
+		0xa4, 0xff, 0xfe, 0x55, 0xfe, 0xff, 0xff, 0xff,  /* full set */
+	},
+};
+
+static const struct ec_response_keybd_config waddledoo2_keybd = {
+	/* Default Chromeos keyboard config */
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_FORWARD,		/* T2 */
+		TK_REFRESH,		/* T3 */
+		TK_FULLSCREEN,		/* T4 */
+		TK_OVERVIEW,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	/* No function keys, no numeric keypad, has screenlock key */
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &waddledoo2_keybd;
+}
+
+/* C0 interrupt line shared by BC 1.2 and charger */
+static void check_c0_line(void);
+DECLARE_DEFERRED(check_c0_line);
+
+static void notify_c0_chips(void)
+{
+	/*
+	 * The interrupt line is shared between the TCPC and BC 1.2 detection
+	 * chip.  Therefore we'll need to check both ICs.
+	 */
+	schedule_deferred_pd_interrupt(0);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+
+static void check_c0_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		notify_c0_chips();
+		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+	}
+}
+
+static void usb_c0_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c0_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c0_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+}
+
+/* C1 interrupt line shared by BC 1.2, TCPC, and charger */
+static void check_c1_line(void);
+DECLARE_DEFERRED(check_c1_line);
+
+static void notify_c1_chips(void)
+{
+	schedule_deferred_pd_interrupt(1);
+	usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+}
+
+static void check_c1_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips.
+	 */
+	if (!gpio_get_level(GPIO_SUB_USB_C1_INT_ODL)) {
+		notify_c1_chips();
+		hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
+	}
+}
+
+static void sub_usb_c1_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c1_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c1_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
+}
+
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_1] = {
+		.name = "TEMP_SENSOR1",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_2] = {
+		.name = "TEMP_SENSOR2",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_SUB_ANALOG] = {
+		.name = "SUB_ANALOG",
+		.input_ch = NPCX_ADC_CH2,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_VSNS_PP3300_A] = {
+		.name = "PP3300_A_PGOOD",
+		.input_ch = NPCX_ADC_CH9,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* Thermistors */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_A                \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(85), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A;
+
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_B                \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(73), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(85), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = 0, \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_b = THERMAL_B;
+
+struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
+
+static void setup_thermal(void)
+{
+	thermal_params[TEMP_SENSOR_1] = thermal_a;
+	thermal_params[TEMP_SENSOR_2] = thermal_b;
+}
+
+void board_hibernate(void)
+{
+	/*
+	 * Both charger ICs need to be put into their "low power mode" before
+	 * entering the Z-state.
+	 */
+	raa489000_hibernate(1, true);
+	raa489000_hibernate(0, true);
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * TODO(b:147316511): Here we could issue a digital reset to the IC,
+	 * unsure if we actually want to do that or not yet.
+	 */
+}
+
+static void ps8762_chaddr_deferred(void)
+{
+	/* Switch PS8762 I2C Address to 0x50*/
+	if (ps8802_chg_i2c_addr(I2C_PORT_SUB_USB_C1) == EC_SUCCESS)
+		CPRINTS("Switch PS8762 address to 0x50 success");
+	else
+		CPRINTS("Switch PS8762 address to 0x50 failed");
+}
+
+__override void board_power_5v_enable(int enable)
+{
+	/*
+	 * Port 0 simply has a GPIO to turn on the 5V regulator, however, 5V is
+	 * generated locally on the sub board and we need to set the comparator
+	 * polarity on the sub board charger IC.
+	 */
+	gpio_set_level(GPIO_EN_PP5000, !!enable);
+	if (isl923x_set_comparator_inversion(1, !!enable))
+		CPRINTS("Failed to %sable sub rails!", enable ? "en" : "dis");
+
+	if (!enable)
+		return;
+	/*
+	 * Port C1 the PP3300_USB_C1  assert, delay 15ms
+	 * colud be accessed PS8762 by I2C.
+	 */
+	hook_call_deferred(&ps8762_chaddr_deferred_data, 15 * MSEC);
+}
+
+int board_is_sourcing_vbus(int port)
+{
+	int regval;
+
+	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
+	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int i;
+	int old_port;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	old_port = charge_manager_get_active_charge_port();
+
+	CPRINTS("New chg p%d", port);
+
+	/* Disable all ports. */
+	if (port == CHARGE_PORT_NONE) {
+		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
+			tcpc_write(i, TCPC_REG_COMMAND,
+				   TCPC_REG_COMMAND_SNK_CTRL_LOW);
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if port is sourcing VBUS. */
+	if (board_is_sourcing_vbus(port)) {
+		CPRINTS("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		if (i == port)
+			continue;
+
+		if (tcpc_write(i, TCPC_REG_COMMAND,
+			       TCPC_REG_COMMAND_SNK_CTRL_LOW))
+			CPRINTS("p%d: sink path disable failed.", i);
+	}
+
+	/*
+	 * Stop the charger IC from switching while changing ports.  Otherwise,
+	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
+	 */
+	if (old_port != CHARGE_PORT_NONE)
+		charger_discharge_on_ac(1);
+
+	/* Enable requested charge port. */
+	if (tcpc_write(port, TCPC_REG_COMMAND,
+		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
+		CPRINTS("p%d: sink path enable failed.", port);
+		charger_discharge_on_ac(0);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	/* Allow the charger IC to begin/continue switching. */
+	charger_discharge_on_ac(0);
+
+	return EC_SUCCESS;
+}
+
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	if (port < 0 || port > board_get_usb_pd_port_count())
+		return;
+
+	raa489000_set_output_current(port, rp);
+}
+
+/* Sensors */
+static struct mutex g_lid_mutex;
+static struct mutex g_base_mutex;
+
+/* Matrices to rotate accelerometers into the standard reference. */
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
+
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					      { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
+
+/* BMA253 private data */
+static struct accelgyro_saved_data_t g_bma253_data;
+
+/* BMI160 private data */
+static struct bmi_drv_data_t g_bmi160_data;
+
+static const mat33_fp_t base_icm_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					 { 0, FLOAT_TO_FP(1), 0 },
+					 { 0, 0, FLOAT_TO_FP(-1) } };
+
+/* ICM426 private data */
+static struct icm_drv_data_t g_icm426xx_data;
+/* KX022 private data */
+static struct kionix_accel_data g_kx022_data;
+
+struct motion_sensor_t kx022_lid_accel = {
+	.name = "Lid Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_KX022,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_LID,
+	.drv = &kionix_accel_drv,
+	.mutex = &g_lid_mutex,
+	.drv_data = &g_kx022_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = KX022_ADDR0_FLAGS,
+	.rot_standard_ref = &lid_standard_ref,
+	.min_frequency = KX022_ACCEL_MIN_FREQ,
+	.max_frequency = KX022_ACCEL_MAX_FREQ,
+	.default_range = 2, /* g, to support tablet mode */
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	},
+};
+
+struct motion_sensor_t icm426xx_base_accel = {
+	.name = "Base Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
+	.rot_standard_ref = &base_icm_ref,
+	.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
+	.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 13000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+	},
+};
+
+struct motion_sensor_t icm426xx_base_gyro = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &base_icm_ref,
+	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
+	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
+};
+
+struct motion_sensor_t motion_sensors[] = {
+	[LID_ACCEL] = {
+		.name = "Lid Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMA255,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &bma2x2_accel_drv,
+		.mutex = &g_lid_mutex,
+		.drv_data = &g_bma253_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
+		.rot_standard_ref = &lid_standard_ref,
+		.default_range = 2,
+		.min_frequency = BMA255_ACCEL_MIN_FREQ,
+		.max_frequency = BMA255_ACCEL_MAX_FREQ,
+		.config = {
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+		},
+	},
+	[BASE_ACCEL] = {
+		.name = "Base Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMI160,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &bmi160_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = &g_bmi160_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+		.rot_standard_ref = &base_standard_ref,
+		.default_range = 4,
+		.min_frequency = BMI_ACCEL_MIN_FREQ,
+		.max_frequency = BMI_ACCEL_MAX_FREQ,
+		.config = {
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 13000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+		},
+	},
+	[BASE_GYRO] = {
+		.name = "Base Gyro",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMI160,
+		.type = MOTIONSENSE_TYPE_GYRO,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &bmi160_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = &g_bmi160_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+		.default_range = 1000, /* dps */
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = BMI_GYRO_MIN_FREQ,
+		.max_frequency = BMI_GYRO_MAX_FREQ,
+	},
+};
+
+unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+void board_init(void)
+{
+	int on;
+
+	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
+	gpio_enable_interrupt(GPIO_SUB_USB_C1_INT_ODL);
+	check_c0_line();
+	check_c1_line();
+
+	/* Enable gpio interrupt for base accelgyro sensor */
+	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
+	if (get_cbi_fw_config_tablet_mode()) {
+		if (get_cbi_ssfc_base_sensor() == SSFC_SENSOR_ICM426XX) {
+			motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
+			motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
+			cprints(CC_SYSTEM, "BASE GYRO is ICM426XX");
+		} else
+			cprints(CC_SYSTEM, "BASE GYRO is BMI160");
+
+		if (get_cbi_ssfc_lid_sensor() == SSFC_SENSOR_KX022) {
+			motion_sensors[LID_ACCEL] = kx022_lid_accel;
+			cprints(CC_SYSTEM, "LID_ACCEL is KX022");
+		} else
+			cprints(CC_SYSTEM, "LID_ACCEL is BMA253");
+
+		motion_sensor_count = ARRAY_SIZE(motion_sensors);
+		/* Enable gpio interrupt for base accelgyro sensor */
+		gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
+	} else {
+		motion_sensor_count = 0;
+		gmr_tablet_switch_disable();
+		/* Base accel is not stuffed, don't allow line to float */
+		gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L,
+			       GPIO_INPUT | GPIO_PULL_DOWN);
+	}
+
+	/* Turn on 5V if the system is on, otherwise turn it off. */
+	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
+			      CHIPSET_STATE_SOFT_OFF);
+	board_power_5v_enable(on);
+
+	/* Initialize THERMAL */
+	setup_thermal();
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	switch (get_cbi_ssfc_base_sensor()) {
+	case SSFC_SENSOR_ICM426XX:
+		icm426xx_interrupt(signal);
+		break;
+	case SSFC_SENSOR_BMI160:
+	default:
+		bmi160_interrupt(signal);
+		break;
+	}
+}
+
+__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+				       int *ki_div, int *kd, int *kd_div)
+{
+	*kp = 1;
+	*kp_div = 20;
+	*ki = 1;
+	*ki_div = 250;
+	*kd = 0;
+	*kd_div = 1;
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	return pd_check_vbus_level(port, VBUS_PRESENT);
+}
+
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+
+	{
+		.i2c_port = I2C_PORT_SUB_USB_C1,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+};
+const unsigned int chg_cnt = ARRAY_SIZE(chg_chips);
+
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	{
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+		.flags = PI3USB9201_ALWAYS_POWERED,
+	},
+
+	{
+		.i2c_port = I2C_PORT_SUB_USB_C1,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+		.flags = PI3USB9201_ALWAYS_POWERED,
+	},
+};
+
+/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_KBLIGHT] = {
+		.channel = 3,
+		.flags = PWM_CONFIG_DSLEEP,
+		.freq = 10000,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0,
+			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
+		},
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+		.drv = &raa489000_tcpm_drv,
+	},
+
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_SUB_USB_C1,
+			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
+		},
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+		.drv = &raa489000_tcpm_drv,
+	},
+};
+
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
+				.driver = &pi3usb3x532_usb_mux_driver,
+			},
+	},
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_SUB_USB_C1,
+				.i2c_addr_flags = PS8802_I2C_ADDR_FLAGS_CUSTOM,
+				.driver = &ps8802_usb_mux_driver,
+			},
+	}
+};
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+	int regval;
+
+	/*
+	 * The interrupt line is shared between the TCPC and BC1.2 detector IC.
+	 * Therefore, go out and actually read the alert registers to report the
+	 * alert status.
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
+		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
+			/* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */
+			if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0))
+				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
+
+			if (regval)
+				status |= PD_STATUS_TCPC_ALERT_0;
+		}
+	}
+
+	if (!gpio_get_level(GPIO_SUB_USB_C1_INT_ODL)) {
+		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
+			/* TCPCI spec Rev 1.0 says to ignore bits 14:12. */
+			if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0))
+				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
+
+			if (regval)
+				status |= PD_STATUS_TCPC_ALERT_1;
+		}
+	}
+
+	return status;
+}
+
+int adc_to_physical_value(enum gpio_signal gpio)
+{
+	if (gpio == GPIO_VOLUME_UP_L)
+		return !!(new_adc_key_state & ADC_VOL_UP_MASK);
+	else if (gpio == GPIO_VOLUME_DOWN_L)
+		return !!(new_adc_key_state & ADC_VOL_DOWN_MASK);
+
+	CPRINTS("Not a volume up or down key");
+	return 0;
+}
+
+int button_is_adc_detected(enum gpio_signal gpio)
+{
+	return (gpio == GPIO_VOLUME_DOWN_L) || (gpio == GPIO_VOLUME_UP_L);
+}
+
+static void adc_vol_key_press_check(void)
+{
+	int volt = adc_read_channel(ADC_SUB_ANALOG);
+	static uint8_t old_adc_key_state;
+	uint8_t adc_key_state_change;
+
+	if (volt > 2400 && volt < 2490) {
+		/* volume-up is pressed */
+		new_adc_key_state = ADC_VOL_UP_MASK;
+	} else if (volt > 2600 && volt < 2690) {
+		/* volume-down is pressed */
+		new_adc_key_state = ADC_VOL_DOWN_MASK;
+	} else if (volt < 2290) {
+		/* both volumn-up and volume-down are pressed */
+		new_adc_key_state = ADC_VOL_UP_MASK | ADC_VOL_DOWN_MASK;
+	} else if (volt > 2700) {
+		/* both volumn-up and volume-down are released */
+		new_adc_key_state = 0;
+	}
+	if (new_adc_key_state != old_adc_key_state) {
+		adc_key_state_change = old_adc_key_state ^ new_adc_key_state;
+		if (adc_key_state_change & ADC_VOL_UP_MASK)
+			button_interrupt(GPIO_VOLUME_UP_L);
+		if (adc_key_state_change & ADC_VOL_DOWN_MASK)
+			button_interrupt(GPIO_VOLUME_DOWN_L);
+
+		old_adc_key_state = new_adc_key_state;
+	}
+}
+DECLARE_HOOK(HOOK_TICK, adc_vol_key_press_check, HOOK_PRIO_DEFAULT);
+
+/* This callback disables keyboard when convertibles are fully open */
+__override void lid_angle_peripheral_enable(int enable)
+{
+	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
+
+	/*
+	 * If the lid is in tablet position via other sensors,
+	 * ignore the lid angle, which might be faulty then
+	 * disable keyboard.
+	 */
+	if (tablet_get_mode())
+		enable = 0;
+
+	if (enable) {
+		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
+	} else {
+		/*
+		 * Ensure that the chipset is off before disabling the keyboard.
+		 * When the chipset is on, the EC keeps the keyboard enabled and
+		 * the AP decides whether to ignore input devices or not.
+		 */
+		if (!chipset_in_s0)
+			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
+	}
+}
diff --git a/board/waddledoo2/board.h b/board/waddledoo2/board.h
new file mode 100644
index 0000000000..428a4cc3fc
--- /dev/null
+++ b/board/waddledoo2/board.h
@@ -0,0 +1,181 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Waddledoo2 board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#define VARIANT_KEEBY_EC_NPCX797FC
+#include "baseboard.h"
+
+/*
+ * The RAM and flash size combination on the the NPCX797FC does not leave
+ * any unused flash space that can be used to store the .init_rom section.
+ */
+#undef CONFIG_CHIP_INIT_ROM_REGION
+
+/* Battery */
+#define CONFIG_BATTERY_FUEL_GAUGE
+
+/* Charger */
+#define CONFIG_CHARGER_RAA489000
+#define PD_MAX_VOLTAGE_MV 20000
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_OCPC_DEF_RBATT_MOHMS               \
+	22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \
+	    */
+/*
+ * b/147463641: The charger IC seems to overdraw ~4%, therefore we
+ * reduce our target accordingly.
+ */
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 4
+#define CONFIG_OCPC
+#undef CONFIG_CHARGER_SINGLE_CHIP
+#undef CONFIG_CMD_CHARGER_DUMP
+#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
+#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
+
+/* GPIO for C1 interrupts, for baseboard use */
+#define GPIO_USB_C1_INT_ODL GPIO_SUB_USB_C1_INT_ODL
+
+/* Keyboard */
+
+#define CONFIG_KEYBOARD_KEYPAD
+#define CONFIG_PWM_KBLIGHT
+
+/* LED defines */
+#define CONFIG_LED_ONOFF_STATES
+
+/* PWM */
+#define CONFIG_PWM
+#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */
+
+/* Temp sensor */
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_THROTTLE_AP
+#define CONFIG_THERMISTOR_NCP15WB
+#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
+
+/* USB */
+#define CONFIG_BC12_DETECT_PI3USB9201
+#define CONFIG_USBC_RETIMER_PS8802
+
+/* Common USB-A defines */
+#define USB_PORT_COUNT 2
+#define CONFIG_USB_PORT_POWER_SMART
+#define CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY
+#define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_CDP
+#define CONFIG_USB_PORT_POWER_SMART_INVERTED
+#define GPIO_USB1_ILIM_SEL GPIO_USB_A0_CHARGE_EN_L
+#define GPIO_USB2_ILIM_SEL GPIO_USB_A1_CHARGE_EN_L
+
+/******************************************************************************/
+
+/* USB PD */
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#define CONFIG_USB_PD_TCPM_RAA489000
+
+/* USB defines specific to external TCPCs */
+#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+#define CONFIG_USB_PD_VBUS_DETECT_TCPC
+#define CONFIG_USB_PD_DISCHARGE_TCPC
+#define CONFIG_USB_PD_TCPC_LOW_POWER
+
+/* Variant references the TCPCs to determine Vbus sourcing */
+#define CONFIG_USB_PD_5V_EN_CUSTOM
+
+/* I2C configuration */
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
+#define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0
+/* TODO(b:147440290): Need to handle multiple charger ICs */
+#define I2C_PORT_CHARGER I2C_PORT_USB_C0
+
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */
+
+/* Sensors */
+#define CONFIG_CMD_ACCELS
+#define CONFIG_CMD_ACCEL_INFO
+#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
+
+#define CONFIG_ACCEL_BMA255 /* Lid accel */
+#define CONFIG_ACCELGYRO_BMI160 /* Base accel */
+#define CONFIG_ACCEL_KX022 /* Lid accel */
+#define CONFIG_ACCELGYRO_ICM426XX /* Base accel second source*/
+
+/* Lid operates in forced mode, base in FIFO */
+#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
+#define CONFIG_ACCEL_FIFO
+#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */
+#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
+
+#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_UPDATE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+
+#define CONFIG_TABLET_MODE
+#define CONFIG_TABLET_MODE_SWITCH
+#define CONFIG_GMR_TABLET_MODE
+
+/* Volume Button feature */
+#define CONFIG_ADC_BUTTONS
+#define CONFIG_VOLUME_BUTTONS
+#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum chg_id {
+	CHARGER_PRIMARY,
+	CHARGER_SECONDARY,
+	CHARGER_NUM,
+};
+
+enum adc_channel {
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
+	ADC_SUB_ANALOG, /* ADC2 */
+	ADC_VSNS_PP3300_A, /* ADC9 */
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT };
+
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
+
+enum pwm_channel {
+	PWM_CH_KBLIGHT,
+	PWM_CH_COUNT,
+};
+
+enum battery_type {
+	BATTERY_AP19B8M,
+	BATTERY_LGC_AP18C8K,
+	BATTERY_MURATA_AP18C4K,
+	BATTERY_TYPE_COUNT,
+};
+
+int board_is_sourcing_vbus(int port);
+void motion_interrupt(enum gpio_signal signal);
+#endif /* !__ASSEMBLER__ */
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/waddledoo2/build.mk b/board/waddledoo2/build.mk
new file mode 100644
index 0000000000..eb422dae93
--- /dev/null
+++ b/board/waddledoo2/build.mk
@@ -0,0 +1,14 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx7
+CHIP_VARIANT:=npcx7m7fc
+BASEBOARD:=keeby
+
+board-y=board.o battery.o cbi_ssfc.o led.o usb_pd_policy.o
diff --git a/board/waddledoo2/cbi_ssfc.c b/board/waddledoo2/cbi_ssfc.c
new file mode 100644
index 0000000000..81f3ee0dad
--- /dev/null
+++ b/board/waddledoo2/cbi_ssfc.c
@@ -0,0 +1,36 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi_ssfc.h"
+#include "common.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "hooks.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+/* Cache SSFC on init since we don't expect it to change in runtime */
+static union dedede_cbi_ssfc cached_ssfc;
+BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
+
+static void cbi_ssfc_init(void)
+{
+	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
+		/* Default to 0 when CBI isn't populated */
+		cached_ssfc.raw_value = 0;
+
+	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
+}
+DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
+
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
+{
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
+}
+
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
+{
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
+}
diff --git a/board/waddledoo2/cbi_ssfc.h b/board/waddledoo2/cbi_ssfc.h
new file mode 100644
index 0000000000..bf8853a43a
--- /dev/null
+++ b/board/waddledoo2/cbi_ssfc.h
@@ -0,0 +1,59 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _DEDEDE_CBI_SSFC__H_
+#define _DEDEDE_CBI_SSFC__H_
+
+#include "stdint.h"
+
+/****************************************************************************
+ * Dedede CBI Second Source Factory Cache
+ */
+
+/*
+ * Base Sensor (Bits 0-2)
+ */
+enum ec_ssfc_base_sensor {
+	SSFC_SENSOR_BASE_DEFAULT = 0,
+	SSFC_SENSOR_BMI160 = 1,
+	SSFC_SENSOR_ICM426XX = 2,
+	SSFC_SENSOR_LSM6DSM = 3,
+	SSFC_SENSOR_ICM42607 = 4
+};
+
+/*
+ * Lid Sensor (Bits 3-5)
+ */
+enum ec_ssfc_lid_sensor {
+	SSFC_SENSOR_LID_DEFAULT = 0,
+	SSFC_SENSOR_BMA255 = 1,
+	SSFC_SENSOR_KX022 = 2,
+	SSFC_SENSOR_LIS2DWL = 3
+};
+
+union dedede_cbi_ssfc {
+	struct {
+		uint32_t base_sensor : 3;
+		uint32_t lid_sensor : 3;
+		uint32_t reserved_2 : 26;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Get the Base sensor type from SSFC_CONFIG.
+ *
+ * @return the Base sensor board type.
+ */
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
+
+/**
+ * Get the Lid sensor type from SSFC_CONFIG.
+ *
+ * @return the Lid sensor board type.
+ */
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
+
+#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/waddledoo2/ec.tasklist b/board/waddledoo2/ec.tasklist
new file mode 100644
index 0000000000..29666dd959
--- /dev/null
+++ b/board/waddledoo2/ec.tasklist
@@ -0,0 +1,25 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/waddledoo2/gpio.inc b/board/waddledoo2/gpio.inc
new file mode 100644
index 0000000000..f2a95f9762
--- /dev/null
+++ b/board/waddledoo2/gpio.inc
@@ -0,0 +1,145 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first.
+ */
+
+/* Power Interrupts */
+GPIO_INT(SLP_S0_L,		 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,		 PIN(A, 5), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(SLP_S4_L,		 PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,		 PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(RSMRST_PWRGD_L,	 PIN(C, 6), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID1,	 PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(CPU_C10_GATE_L,	 PIN(6, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(VCCIN_AUX_VID0,	 PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, power_signal_interrupt)
+GPIO_INT(PG_VCCIO_EXT_OD,	 PIN(B, 0), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(PG_PP5000_U_OD,	 PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_DRAM_OD,		 PIN(E, 4), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
+GPIO_INT(PG_PP1050_ST_OD,	 PIN(4, 2), GPIO_INT_BOTH, power_signal_interrupt)
+
+/* USB-C interrupts */
+GPIO_INT(USB_C0_INT_ODL,	 PIN(6, 2), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt)
+GPIO_INT(SUB_USB_C1_INT_ODL,	 PIN(F, 5), GPIO_INT_FALLING | GPIO_PULL_UP, sub_usb_c1_interrupt)
+
+/* Button interrupts */
+GPIO_INT(EC_PWR_BTN_ODL,	 PIN(0, 1), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
+
+/* Other interrupts */
+GPIO_INT(LID_OPEN,		 PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)
+GPIO_INT(EC_WP_OD,		 PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(BASE_SIXAXIS_INT_L,	 PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, motion_interrupt)
+GPIO_INT(LID_360_L,		 PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
+
+/* I2C Ports */
+GPIO(EC_I2C_EEPROM_SCL,	      PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SDA,	      PIN(B, 2), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SCL,      PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SDA,      PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,	      PIN(B, 5), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SDA,	      PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SCL,	      PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SDA,	      PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_SUB_USB_C1_SCL,   PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_SUB_USB_C1_SDA,   PIN(9, 1), GPIO_INPUT)
+
+/* Extra Sub-board I/O pins */
+
+GPIO(EC_SUB_IO_2,  PIN(3, 4), GPIO_OUT_LOW)
+
+/* Misc Enables */
+GPIO(EN_VCCIO_EXT,   PIN(6, 1), GPIO_OUT_LOW)
+/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
+GPIO(EN_VCCST,		PIN(A, 7), GPIO_INPUT)
+GPIO(EN_PP3300_PEN,	PIN(6, 3), GPIO_OUT_LOW)
+GPIO(EN_PP3300_A,	PIN(0, 3), GPIO_OUT_LOW)
+GPIO(EN_PP5000_U,	PIN(A, 4), GPIO_OUT_LOW)
+GPIO(EN_SLP_Z,		PIN(8, 3), GPIO_OUT_LOW)
+GPIO(EN_KB_BL,		PIN(6, 0), GPIO_OUT_LOW)
+GPIO(EN_BL_OD,		PIN(D, 3), GPIO_ODR_LOW)
+GPIO(EC_CBI_WP,		PIN(E, 5), GPIO_OUT_LOW)
+
+/* LED */
+GPIO(LED_B_ODL,                  PIN(C, 2), GPIO_OUT_HIGH)        /* PWM_CH_LED2_BLUE */
+GPIO(LED_G_ODL,                  PIN(C, 3), GPIO_OUT_HIGH)        /* PWM_CH_LED1_GREEN */
+GPIO(LED_R_ODL,                  PIN(C, 4), GPIO_OUT_HIGH)        /* PWM_CH_LED2_ORANGE */
+
+/* Power Sequencing */
+GPIO(EC_AP_PSYS,	     PIN(B, 7), GPIO_OUT_LOW)
+GPIO(EC_AP_RSMRST_L,         PIN(A, 6), GPIO_OUT_LOW)
+GPIO(EC_AP_PWR_BTN_ODL,      PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(EC_AP_RTCRST,           PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_AP_WAKE_ODL,         PIN(7, 4), GPIO_ODR_HIGH)
+GPIO(EC_AP_DPWROK,	     PIN(A, 3), GPIO_OUT_LOW)
+GPIO(EC_AP_PCH_PWROK_OD,     PIN(9, 4), GPIO_ODR_LOW)
+GPIO(EC_AP_VCCST_PWRGD_OD,   PIN(B, 1), GPIO_ODR_LOW)
+GPIO(EC_AP_SYS_PWROK,	     PIN(0, 2), GPIO_OUT_LOW)
+GPIO(EC_AP_MKBP_INT_L,	     PIN(7, 0), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_ODL,	     PIN(F, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(EC_ENTERING_RW,	     PIN(E, 3), GPIO_OUT_LOW)
+GPIO(ALL_SYS_PWRGD,	     PIN(A, 0), GPIO_OUT_LOW)
+GPIO(SYS_RST_ODL,	     PIN(C, 5), GPIO_ODR_HIGH)
+
+/* USB pins */
+GPIO(EC_AP_USB_C1_HDMI_HPD,  PIN(9, 6), GPIO_OUT_LOW)
+GPIO(EC_AP_USB_C0_HPD,	     PIN(9, 3), GPIO_OUT_LOW)
+GPIO(HDMI_SEL_L,	     PIN(7, 2), GPIO_OUT_HIGH)
+GPIO(EC_BATTERY_PRES_ODL,    PIN(E, 1), GPIO_INPUT)
+GPIO(USB_A0_CHARGE_EN_L, PIN(3, 7), GPIO_OUT_HIGH)	/* Enable A0 1.5A Charging */
+GPIO(USB_A1_CHARGE_EN_L, PIN(F, 3), GPIO_OUT_HIGH)	/* Enable A1 1.5A Charging */
+GPIO(EN_USB_A0_VBUS,	 PIN(4, 1), GPIO_OUT_LOW)		/* Enable A1 5V Charging */
+GPIO(EN_USB_A1_VBUS,	 PIN(F, 2), GPIO_OUT_LOW)		/* Enable A1 5V Charging */
+/*
+ * Waddledoo2 doesn't have these physical pins coming to the EC but uses other
+ * logic.
+ */
+UNIMPLEMENTED(AC_PRESENT)
+UNIMPLEMENTED(PG_EC_DSW_PWROK)
+UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
+UNIMPLEMENTED(VOLDN_BTN_ODL)
+UNIMPLEMENTED(VOLUP_BTN_ODL)
+
+/* Alternate Functions */
+/* ADC */
+ALTERNATE(PIN_MASK(F, BIT(0)), 0, MODULE_ADC, 0) /* ADC9 */
+ALTERNATE(PIN_MASK(4, 0x38), 0, MODULE_ADC, 0)   /* ADC0-2 */
+
+/* Keyboard */
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI0, KSI1 */
+ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI2-7 */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO0, KSO1 */
+ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO3-9 */
+ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO10-13 */
+ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO14 */
+GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW)	/* KSO2 inverted */
+
+/* PWM */
+ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0) /* PWM3 */
+
+/* UART */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)  /* UART1 */
+
+/* I2C */
+ALTERNATE(PIN_MASK(B, 0x3C), 0, MODULE_I2C, 0)   /* I2C7,I2C0 */
+ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)   /* I2C5 */
+ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)   /* I2C2, I2C1 SCL */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)   /* I2C1 SDA */
+
+/* NC pins, enable internal pull-up to avoid floating state. */
+GPIO(GPIO32_NC, PIN(3, 2), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO35_NC, PIN(3, 5), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO57_NC, PIN(5, 7), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO81_NC, PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO86_NC, PIN(8, 6), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOD0_NC, PIN(D, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOD1_NC, PIN(D, 1), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOD6_NC, PIN(D, 6), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIOE0_NC, PIN(E, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(GPIO40_NC, PIN(4, 0), GPIO_INPUT | GPIO_PULL_UP)
diff --git a/board/waddledoo2/led.c b/board/waddledoo2/led.c
new file mode 100644
index 0000000000..9ef613e483
--- /dev/null
+++ b/board/waddledoo2/led.c
@@ -0,0 +1,84 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power and battery LED control for waddledoo2
+ */
+
+#include "chipset.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+
+#define LED_ON_LVL 0
+#define LED_OFF_LVL 1
+
+__override const int led_charge_lvl_1 = 5;
+
+__override const int led_charge_lvl_2 = 95;
+
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_AMBER:
+		gpio_set_level(GPIO_LED_R_ODL, LED_ON_LVL);
+		gpio_set_level(GPIO_LED_B_ODL, LED_OFF_LVL);
+		break;
+	case EC_LED_COLOR_BLUE:
+		gpio_set_level(GPIO_LED_R_ODL, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_B_ODL, LED_ON_LVL);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		gpio_set_level(GPIO_LED_R_ODL, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_B_ODL, LED_OFF_LVL);
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		brightness_range[EC_LED_COLOR_BLUE] = 1;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		if (brightness[EC_LED_COLOR_BLUE] != 0)
+			led_set_color_battery(EC_LED_COLOR_BLUE);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(EC_LED_COLOR_AMBER);
+		else
+			led_set_color_battery(LED_OFF);
+	}
+	return EC_SUCCESS;
+}
diff --git a/board/waddledoo2/usb_pd_policy.c b/board/waddledoo2/usb_pd_policy.c
new file mode 100644
index 0000000000..3410726e87
--- /dev/null
+++ b/board/waddledoo2/usb_pd_policy.c
@@ -0,0 +1,56 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "driver/tcpm/tcpci.h"
+#include "usb_pd.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+int pd_check_vconn_swap(int port)
+{
+	/* Allow VCONN swaps if the AP is on. */
+	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
+}
+
+void pd_power_supply_reset(int port)
+{
+	/* Disable VBUS */
+	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	if (port >= CONFIG_USB_PD_PORT_MAX_COUNT)
+		return EC_ERROR_INVAL;
+
+	/* Disable charging. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
+	if (rv)
+		return rv;
+
+	/* Our policy is not to source VBUS when the AP is off. */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	/* Provide Vbus. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
+	if (rv)
+		return rv;
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
diff --git a/board/waddledoo2/vif_override.xml b/board/waddledoo2/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/waddledoo2/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/wheelie/battery.c b/board/wheelie/battery.c
index c9770124cd..bc2c5bec4d 100644
--- a/board/wheelie/battery.c
+++ b/board/wheelie/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -277,6 +277,8 @@ const struct board_batt_params board_battery_info[] = {
 				.reg_addr = 0x43,
 				.reg_mask = 0x0001,
 				.disconnect_val = 0x0,
+				.cfet_mask = 0x0002,
+				.cfet_off_val = 0x0,
 			},
 		},
 		.batt_info = {
diff --git a/board/wheelie/board.c b/board/wheelie/board.c
index ab1cb03942..f2acbb4efa 100644
--- a/board/wheelie/board.c
+++ b/board/wheelie/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,17 +8,17 @@
 #include "adc_chip.h"
 #include "button.h"
 #include "charge_manager.h"
-#include "charge_state_v2.h"
+#include "charge_state.h"
 #include "charger.h"
 #include "driver/accel_lis2dh.h"
 #include "driver/accelgyro_lsm6dsm.h"
 #include "driver/bc12/pi3usb9201.h"
 #include "driver/charger/sm5803.h"
-#include "driver/sync.h"
 #include "driver/retimer/tusb544.h"
-#include "driver/temp_sensor/thermistor.h"
+#include "driver/sync.h"
 #include "driver/tcpm/anx7447.h"
 #include "driver/tcpm/it83xx_pd.h"
+#include "driver/temp_sensor/thermistor.h"
 #include "driver/usb_mux/it5205.h"
 #include "gpio.h"
 #include "hooks.h"
@@ -32,7 +32,7 @@
 #include "switch.h"
 #include "tablet_mode.h"
 #include "task.h"
-#include "tcpci.h"
+#include "tcpm/tcpci.h"
 #include "temp_sensor.h"
 #include "uart.h"
 #include "usb_charge.h"
@@ -40,12 +40,12 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
 
 /* C0 interrupt line shared by BC 1.2 and charger */
 static void usb_c0_interrupt(enum gpio_signal s)
 {
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
 	sm5803_interrupt(0);
 }
 
@@ -53,7 +53,7 @@ static void usb_c0_interrupt(enum gpio_signal s)
 static void usb_c1_interrupt(enum gpio_signal s)
 {
 	schedule_deferred_pd_interrupt(1);
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12, 0);
+	usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
 	sm5803_interrupt(1);
 }
 
@@ -68,34 +68,26 @@ static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH0
-	},
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH2
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH3
-	},
-	[ADC_SUB_ANALOG] = {
-		.name = "SUB_ANALOG",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH13
-	},
+	[ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH0 },
+	[ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH2 },
+	[ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH3 },
+	[ADC_SUB_ANALOG] = { .name = "SUB_ANALOG",
+			     .factor_mul = ADC_MAX_MVOLT,
+			     .factor_div = ADC_READ_MAX + 1,
+			     .shift = 0,
+			     .channel = CHIP_ADC_CH13 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
@@ -143,27 +135,36 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 };
 
 /* USB Retimer */
-const struct usb_mux usbc1_retimer = {
-	.usb_port = 1,
-	.i2c_port = I2C_PORT_SUB_USB_C1,
-	.i2c_addr_flags = TUSB544_I2C_ADDR_FLAGS0,
-	.driver = &tusb544_drv,
+const struct usb_mux_chain usbc1_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = 1,
+			.i2c_port = I2C_PORT_SUB_USB_C1,
+			.i2c_addr_flags = TUSB544_I2C_ADDR_FLAGS0,
+			.driver = &tusb544_drv,
+		},
 };
 
 /* USB Muxes */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+			},
 	},
 	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = AN7447_TCPC0_I2C_ADDR_FLAGS,
-		.driver = &anx7447_usb_mux_driver,
-		.next_mux = &usbc1_retimer,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_SUB_USB_C1,
+				.i2c_addr_flags = AN7447_TCPC0_I2C_ADDR_FLAGS,
+				.driver = &anx7447_usb_mux_driver,
+			},
+		.next = &usbc1_retimer,
 	},
 };
 
@@ -228,18 +229,6 @@ uint16_t tcpc_get_alert_status(void)
 	return status;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
-			    int charge_mv)
-{
-	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
-
-	/*
-	 * TODO(b/151955431): Characterize the input current limit in case a
-	 * scaling needs to be applied here
-	 */
-	charge_set_input_current_limit(icl, charge_mv);
-}
-
 int board_set_active_charge_port(int port)
 {
 	int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
@@ -394,8 +383,6 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_base_mutex,
 		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
 				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
 		.port = I2C_PORT_SENSOR,
 		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
 		.rot_standard_ref = NULL,
@@ -423,8 +410,6 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_base_mutex,
 		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
 				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
 		.port = I2C_PORT_SENSOR,
 		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
 		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
@@ -449,20 +434,19 @@ const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
 /* Thermistors */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
-#ifndef TEST_BUILD
 /* This callback disables keyboard when convertibles are fully open */
-void lid_angle_peripheral_enable(int enable)
+__override void lid_angle_peripheral_enable(int enable)
 {
 	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
 
@@ -486,4 +470,3 @@ void lid_angle_peripheral_enable(int enable)
 			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
 	}
 }
-#endif
diff --git a/board/wheelie/board.h b/board/wheelie/board.h
index 7c680545c0..c53f22b512 100644
--- a/board/wheelie/board.h
+++ b/board/wheelie/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,12 +22,13 @@
 #define CONFIG_BC12_DETECT_PI3USB9201
 
 /* Charger */
-#define CONFIG_CHARGER_SM5803		/* C0 and C1: Charger */
-#define CONFIG_FPU			/* For charger calculations */
+#define CONFIG_CHARGER_SM5803 /* C0 and C1: Charger */
+#define PD_MAX_VOLTAGE_MV 15000
+#define CONFIG_FPU /* For charger calculations */
 #define CONFIG_USB_PD_VBUS_DETECT_CHARGER
 #define CONFIG_USB_PD_5V_CHARGER_CTRL
 #define CONFIG_CHARGER_OTG
-#undef  CONFIG_CHARGER_SINGLE_CHIP
+#undef CONFIG_CHARGER_SINGLE_CHIP
 
 /* LED */
 #define CONFIG_LED_PWM
@@ -37,13 +38,14 @@
 #define CONFIG_PWM
 
 /* Sensors */
-#define CONFIG_ACCEL_LIS2DE		/* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM	/* Base accel */
-#define CONFIG_SYNC			/* Camera VSYNC */
+#define CONFIG_ACCEL_LIS2DE /* Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
+#define CONFIG_SYNC /* Camera VSYNC */
+#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 /* Sensors without hardware FIFO are in forced mode */
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
 
-#define CONFIG_ACCEL_INTERRUPTS
 /* Enable sensor fifo, must also define the _SIZE and _THRES */
 #define CONFIG_ACCEL_FIFO
 /* Power of 2 - Too large of a fifo causes too much timestamp jitter */
@@ -55,8 +57,7 @@
 #define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
 #define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
 
-#define CONFIG_SYNC_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
+#define CONFIG_SYNC_INT_EVENT TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
 
 #define CONFIG_TABLET_MODE
 #define CONFIG_TABLET_MODE_SWITCH
@@ -64,21 +65,20 @@
 
 /* TCPC */
 #define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP	/* C0: ITE EC TCPC */
-#define CONFIG_USB_PD_TCPM_ANX7447	/* C1: ANX TCPC + Mux */
+#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0: ITE EC TCPC */
+#define CONFIG_USB_PD_TCPM_ANX7447 /* C1: ANX TCPC + Mux */
 #define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1
 
 /* Thermistors */
 #define CONFIG_TEMP_SENSOR
 #define CONFIG_THERMISTOR
 #define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_PP3300_A
 
 /* USB Mux and Retimer */
-#define CONFIG_USB_MUX_IT5205			/* C1: ITE Mux */
-#define I2C_PORT_USB_MUX I2C_PORT_USB_C0	/* Required for ITE Mux */
+#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */
 
-#define CONFIG_USBC_RETIMER_TUSB544		/* C1 Redriver: TUSB544 */
+#define CONFIG_USBC_RETIMER_TUSB544 /* C1 Redriver: TUSB544 */
 
 #ifndef __ASSEMBLER__
 
@@ -100,28 +100,18 @@ enum pwm_channel {
 };
 
 /* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	VSYNC,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, VSYNC, SENSOR_COUNT };
 
 /* ADC channels */
 enum adc_channel {
-	ADC_VSNS_PP3300_A,     /* ADC0 */
-	ADC_TEMP_SENSOR_1,     /* ADC2 */
-	ADC_TEMP_SENSOR_2,     /* ADC3 */
-	ADC_SUB_ANALOG,        /* ADC13 */
+	ADC_VSNS_PP3300_A, /* ADC0 */
+	ADC_TEMP_SENSOR_1, /* ADC2 */
+	ADC_TEMP_SENSOR_2, /* ADC3 */
+	ADC_SUB_ANALOG, /* ADC13 */
 	ADC_CH_COUNT
 };
 
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_COUNT
-};
+enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
@@ -138,8 +128,6 @@ enum battery_type {
 	BATTERY_TYPE_COUNT,
 };
 
-int board_is_sourcing_vbus(int port);
-
 #endif /* !__ASSEMBLER__ */
 
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/wheelie/build.mk b/board/wheelie/build.mk
index 00e4e0bb5d..9b862c7624 100644
--- a/board/wheelie/build.mk
+++ b/board/wheelie/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -11,5 +11,5 @@ CHIP_FAMILY:=it8320
 CHIP_VARIANT:=it8320dx
 BASEBOARD:=dedede
 
-board-y=board.o led.o usb_pd_policy.o
+board-y=board.o cbi_ssfc.o led.o usb_pd_policy.o
 board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/wheelie/cbi_ssfc.c b/board/wheelie/cbi_ssfc.c
new file mode 100644
index 0000000000..81f3ee0dad
--- /dev/null
+++ b/board/wheelie/cbi_ssfc.c
@@ -0,0 +1,36 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi_ssfc.h"
+#include "common.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "hooks.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+/* Cache SSFC on init since we don't expect it to change in runtime */
+static union dedede_cbi_ssfc cached_ssfc;
+BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
+
+static void cbi_ssfc_init(void)
+{
+	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
+		/* Default to 0 when CBI isn't populated */
+		cached_ssfc.raw_value = 0;
+
+	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
+}
+DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
+
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
+{
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
+}
+
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
+{
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
+}
diff --git a/board/wheelie/cbi_ssfc.h b/board/wheelie/cbi_ssfc.h
new file mode 100644
index 0000000000..bf8853a43a
--- /dev/null
+++ b/board/wheelie/cbi_ssfc.h
@@ -0,0 +1,59 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _DEDEDE_CBI_SSFC__H_
+#define _DEDEDE_CBI_SSFC__H_
+
+#include "stdint.h"
+
+/****************************************************************************
+ * Dedede CBI Second Source Factory Cache
+ */
+
+/*
+ * Base Sensor (Bits 0-2)
+ */
+enum ec_ssfc_base_sensor {
+	SSFC_SENSOR_BASE_DEFAULT = 0,
+	SSFC_SENSOR_BMI160 = 1,
+	SSFC_SENSOR_ICM426XX = 2,
+	SSFC_SENSOR_LSM6DSM = 3,
+	SSFC_SENSOR_ICM42607 = 4
+};
+
+/*
+ * Lid Sensor (Bits 3-5)
+ */
+enum ec_ssfc_lid_sensor {
+	SSFC_SENSOR_LID_DEFAULT = 0,
+	SSFC_SENSOR_BMA255 = 1,
+	SSFC_SENSOR_KX022 = 2,
+	SSFC_SENSOR_LIS2DWL = 3
+};
+
+union dedede_cbi_ssfc {
+	struct {
+		uint32_t base_sensor : 3;
+		uint32_t lid_sensor : 3;
+		uint32_t reserved_2 : 26;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Get the Base sensor type from SSFC_CONFIG.
+ *
+ * @return the Base sensor board type.
+ */
+enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
+
+/**
+ * Get the Lid sensor type from SSFC_CONFIG.
+ *
+ * @return the Lid sensor board type.
+ */
+enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
+
+#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/wheelie/ec.tasklist b/board/wheelie/ec.tasklist
index 75181a4531..701c1fa099 100644
--- a/board/wheelie/ec.tasklist
+++ b/board/wheelie/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/wheelie/gpio.inc b/board/wheelie/gpio.inc
index ba47baaa86..eb96828e07 100644
--- a/board/wheelie/gpio.inc
+++ b/board/wheelie/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -100,7 +100,7 @@ GPIO(EC_SUB_IO_2_2, PIN(L, 2), GPIO_INPUT)
 /* Misc */
 GPIO(EN_BL_OD,			PIN(K, 4), GPIO_OUT_LOW)
 GPIO(EC_ENTERING_RW,		PIN(G, 0), GPIO_OUT_LOW)
-GPIO(CCD_MODE_ODL,		PIN(H, 5), GPIO_INPUT)
+GPIO(CCD_MODE_ODL,		PIN(H, 5), GPIO_ODR_HIGH)
 GPIO(EC_BATTERY_PRES_ODL,	PIN(I, 4), GPIO_INPUT)
 GPIO(PEN_DET_ODL,		PIN(J, 1), GPIO_INPUT | GPIO_PULL_UP)
 GPIO(EN_KB_BL,			PIN(J, 3), GPIO_OUT_LOW) /* Currently unused */
diff --git a/board/wheelie/led.c b/board/wheelie/led.c
index 8c65f54568..59518dbe6c 100644
--- a/board/wheelie/led.c
+++ b/board/wheelie/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,14 +19,14 @@ const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 /*
  * Board has one physical LED with red, green, and blue
  */
-struct pwm_led led_color_map[EC_LED_COLOR_COUNT] = {
-				/* Red, Green, Blue */
-	[EC_LED_COLOR_RED]    = { 100,   0,   0 },
-	[EC_LED_COLOR_GREEN]  = {   0, 100,   0 },
-	[EC_LED_COLOR_BLUE]   = {   0,   0, 100 },
-	[EC_LED_COLOR_YELLOW] = {  50,  50,   0 },
-	[EC_LED_COLOR_WHITE]  = {  50,  50,  50 },
-	[EC_LED_COLOR_AMBER]  = {  70,  30,   0 },
+struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = {
+	/* Red, Green, Blue */
+	[EC_LED_COLOR_RED] = { 100, 0, 0 },
+	[EC_LED_COLOR_GREEN] = { 0, 100, 0 },
+	[EC_LED_COLOR_BLUE] = { 0, 0, 100 },
+	[EC_LED_COLOR_YELLOW] = { 50, 50, 0 },
+	[EC_LED_COLOR_WHITE] = { 50, 50, 50 },
+	[EC_LED_COLOR_AMBER] = { 70, 30, 0 },
 };
 
 /* One logical LED with red, green, and blue channels. */
diff --git a/board/wheelie/usb_pd_policy.c b/board/wheelie/usb_pd_policy.c
index 1611af23e0..3c7564fa12 100644
--- a/board/wheelie/usb_pd_policy.c
+++ b/board/wheelie/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,8 +13,8 @@
 #include "driver/tcpm/tcpci.h"
 #include "usb_pd.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
@@ -39,11 +39,6 @@ void pd_power_supply_reset(int port)
 	if (prev_en)
 		sm5803_set_vbus_disch(port, 1);
 
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	/* Give back the current quota we are no longer using */
-	charge_manager_source_port(port, 0);
-#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
-
 	/* Notify host of power info change. */
 	pd_send_host_event(PD_EVENT_POWER_CHANGE);
 }
@@ -63,11 +58,6 @@ int pd_set_power_supply_ready(int port)
 	/* Provide Vbus */
 	chg_chips[port].drv->enable_otg_power(port, 1);
 
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	/* Ensure we advertise the proper available current quota */
-	charge_manager_source_port(port, 1);
-#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
-
 	/* Notify host of power info change. */
 	pd_send_host_event(PD_EVENT_POWER_CHANGE);
 
diff --git a/board/wheelie/vif_override.xml b/board/wheelie/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/wheelie/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/willow/battery.c b/board/willow/battery.c
index cc97838f48..a79785aaf8 100644
--- a/board/willow/battery.c
+++ b/board/willow/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/willow/board.c b/board/willow/board.c
index 17ccb305e0..7ba0cfb8cc 100644
--- a/board/willow/board.c
+++ b/board/willow/board.c
@@ -1,10 +1,9 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "backlight.h"
 #include "button.h"
 #include "charge_manager.h"
@@ -31,48 +30,62 @@
 #include "it8801.h"
 #include "keyboard_scan.h"
 #include "lid_switch.h"
+#include "panic.h"
 #include "power.h"
 #include "power_button.h"
 #include "registers.h"
 #include "spi.h"
 #include "system.h"
-#include "tablet_mode.h"
 #include "task.h"
-#include "tcpm.h"
+#include "tcpm/tcpm.h"
 #include "timer.h"
 #include "usb_charge.h"
 #include "usb_mux.h"
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
 	schedule_deferred_pd_interrupt(0 /* port */);
 }
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /******************************************************************************/
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] =  {"BOARD_ID",  3300, 4096, 0, STM32_AIN(10)},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)},
+	[ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(10) },
+	[ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /******************************************************************************/
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{"typec", 0, 400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"other", 1, 400, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
+	{ .name = "typec",
+	  .port = 0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "other",
+	  .port = 1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
 const struct i2c_port_t i2c_bitbang_ports[] = {
-	{"battery", 2, 100, GPIO_I2C3_SCL, GPIO_I2C3_SDA, .drv = &bitbang_drv},
+	{ .name = "battery",
+	  .port = 2,
+	  .kbps = 100,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA,
+	  .drv = &bitbang_drv },
 };
 const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
 
@@ -80,13 +93,13 @@ const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
 
 /* power signal list.  Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
+	{ GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" },
+	{ GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" },
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
 /* Keyboard scan setting */
-struct keyboard_scan_config keyscan_config = {
+__override struct keyboard_scan_config keyscan_config = {
 	/*
 	 * TODO(b/133200075): Tune this once we have the final performance
 	 * out of the driver and the i2c bus.
@@ -105,8 +118,8 @@ struct keyboard_scan_config keyscan_config = {
 
 struct ioexpander_config_t ioex_config[CONFIG_IO_EXPANDER_PORT_COUNT] = {
 	[0] = {
-		.i2c_host_port = I2C_PORT_IO_EXPANDER_IT8801,
-		.i2c_slave_addr = IT8801_I2C_ADDR,
+		.i2c_host_port = I2C_PORT_KB_DISCRETE,
+		.i2c_addr_flags = IT8801_I2C_ADDR1,
 		.drv = &it8801_ioexpander_drv,
 	},
 };
@@ -131,15 +144,18 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = I2C_PORT_TCPC0,
-			.addr_flags = FUSB302_I2C_SLAVE_ADDR_FLAGS,
+			.addr_flags = FUSB302_I2C_ADDR_FLAGS,
 		},
 		.drv = &fusb302_tcpm_drv,
 	},
 };
 
-static void board_hpd_status(const struct usb_mux *me,
-			     int hpd_lvl, int hpd_irq)
+static void board_hpd_status(const struct usb_mux *me, mux_state_t mux_state,
+			     bool *ack_required)
 {
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
 	/*
 	 * svdm_dp_attention() did most of the work, we only need to notify
 	 * host here.
@@ -147,13 +163,16 @@ static void board_hpd_status(const struct usb_mux *me,
 	host_set_single_event(EC_HOST_EVENT_USB_MUX);
 }
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+				.hpd_update = &board_hpd_status,
+			},
 	},
 };
 
@@ -200,7 +219,7 @@ int board_set_active_charge_port(int charge_port)
 		if (board_vbus_source_enabled(charge_port))
 			return -1;
 		break;
-	case CHARGE_PORT_NONE:
+	default:
 		/*
 		 * To ensure the fuel gauge (max17055) is always powered
 		 * even when battery is disconnected, keep VBAT rail on but
@@ -208,22 +227,11 @@ int board_set_active_charge_port(int charge_port)
 		 */
 		charger_set_current(CHARGER_SOLO, 0);
 		break;
-	default:
-		panic("Invalid charge port\n");
-		break;
 	}
 
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-			       CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
-
 int board_discharge_on_ac(int enable)
 {
 	int ret, port;
@@ -253,7 +261,7 @@ int pd_snk_is_vbus_provided(int port)
 
 void bc12_interrupt(enum gpio_signal signal)
 {
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
 }
 
 #ifndef VARIANT_KUKUI_NO_SENSORS
@@ -273,13 +281,12 @@ static void board_spi_enable(void)
 	STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
 
 	/* Reinitialize spi peripheral. */
-	spi_enable(CONFIG_SPI_ACCEL_PORT, 1);
+	spi_enable(&spi_devices[0], 1);
 
 	/* Pin mux spi peripheral toward the sensor. */
-	gpio_config_module(MODULE_SPI_MASTER, 1);
+	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
 }
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP,
-	     board_spi_enable,
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_spi_enable,
 	     MOTION_SENSE_HOOK_PRIO - 1);
 
 static void board_spi_disable(void)
@@ -287,14 +294,13 @@ static void board_spi_disable(void)
 	/* Set pins to a state calming the sensor down. */
 	gpio_set_flags(GPIO_EC_SENSOR_SPI_CK, GPIO_OUT_LOW);
 	gpio_set_level(GPIO_EC_SENSOR_SPI_CK, 0);
-	gpio_config_module(MODULE_SPI_MASTER, 0);
+	gpio_config_module(MODULE_SPI_CONTROLLER, 0);
 
 	/* Disable spi peripheral and clocks. */
-	spi_enable(CONFIG_SPI_ACCEL_PORT, 0);
+	spi_enable(&spi_devices[0], 0);
 	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
 }
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN,
-	     board_spi_disable,
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_spi_disable,
 	     MOTION_SENSE_HOOK_PRIO + 1);
 #endif /* !VARIANT_KUKUI_NO_SENSORS */
 
@@ -333,11 +339,9 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Rotation matrixes */
-static const mat33_fp_t base_standard_ref = {
-	{FLOAT_TO_FP(1), 0, 0},
-	{0, FLOAT_TO_FP(1), 0},
-	{0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, FLOAT_TO_FP(1), 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
 
 /* sensor private data */
 static struct kionix_accel_data g_kx022_data;
@@ -356,7 +360,7 @@ struct motion_sensor_t motion_sensors[] = {
 	 .port = I2C_PORT_SENSORS,
 	 .i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
 	 .rot_standard_ref = NULL, /* Identity matrix. */
-	 .default_range = 2, /* g, to meet CDD 7.3.1/C-1-4 reqs */
+	 .default_range = 2, /* g, enough to calculate lid angle. */
 	 .config = {
 		/* EC use accel for angle detection */
 		[SENSOR_CONFIG_EC_S0] = {
@@ -383,9 +387,9 @@ struct motion_sensor_t motion_sensors[] = {
 	 .mutex = &g_base_mutex,
 	 .drv_data = &g_bmi160_data,
 	 .port = CONFIG_SPI_ACCEL_PORT,
-	 .i2c_spi_addr_flags = SLAVE_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
+	 .i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
 	 .rot_standard_ref = &base_standard_ref,
-	 .default_range = 2,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
+	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
 	 .min_frequency = BMI_ACCEL_MIN_FREQ,
 	 .max_frequency = BMI_ACCEL_MAX_FREQ,
 	 .config = {
@@ -411,7 +415,7 @@ struct motion_sensor_t motion_sensors[] = {
 	 .mutex = &g_base_mutex,
 	 .drv_data = &g_bmi160_data,
 	 .port = CONFIG_SPI_ACCEL_PORT,
-	 .i2c_spi_addr_flags = SLAVE_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
+	 .i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
 	 .default_range = 1000, /* dps */
 	 .rot_standard_ref = &base_standard_ref,
 	 .min_frequency = BMI_GYRO_MIN_FREQ,
diff --git a/board/willow/board.h b/board/willow/board.h
index 7d70a98ca6..1772022395 100644
--- a/board/willow/board.h
+++ b/board/willow/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,6 +11,7 @@
 #define VARIANT_KUKUI_JACUZZI
 #define VARIANT_KUKUI_BATTERY_SMART
 #define VARIANT_KUKUI_CHARGER_ISL9238
+#define VARIANT_KUKUI_EC_STM32F098
 
 #ifndef SECTION_IS_RW
 #define VARIANT_KUKUI_NO_SENSORS
@@ -18,6 +19,9 @@
 
 #include "baseboard.h"
 
+/* Disable deferred (async) flash protect*/
+#undef CONFIG_FLASH_PROTECT_DEFERRED
+
 #undef CONFIG_CHIPSET_POWER_SEQ_VERSION
 #define CONFIG_CHIPSET_POWER_SEQ_VERSION 1
 
@@ -26,6 +30,8 @@
 #define CONFIG_BATTERY_HW_PRESENT_CUSTOM
 
 #define CONFIG_CHARGER_PSYS
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 5
 
 #define CONFIG_CHARGER_RUNTIME_CONFIG
 
@@ -49,15 +55,15 @@
 
 /* Motion Sensors */
 #ifndef VARIANT_KUKUI_NO_SENSORS
-#define CONFIG_ACCEL_KX022	/* Lid accel */
+#define CONFIG_ACCEL_KX022 /* Lid accel */
 #define CONFIG_ACCELGYRO_BMI160 /* Base accel */
-#define CONFIG_ACCEL_INTERRUPTS
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 #define CONFIG_ALS
 #define CONFIG_CMD_ACCEL_INFO
 
 #define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_UPDATE
 #define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
 #define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
 
@@ -66,28 +72,32 @@
 #endif /* VARIANT_KUKUI_NO_SENSORS */
 
 /* I2C ports */
-#define I2C_PORT_BC12               0
-#define I2C_PORT_TCPC0              0
-#define I2C_PORT_USB_MUX            0
-#define I2C_PORT_CHARGER            board_get_charger_i2c()
-#define I2C_PORT_SENSORS            1
-#define I2C_PORT_IO_EXPANDER_IT8801 1
-#define I2C_PORT_VIRTUAL_BATTERY    I2C_PORT_BATTERY
-#define I2C_PORT_BATTERY            2
+#define I2C_PORT_BC12 0
+#define I2C_PORT_TCPC0 0
+#define I2C_PORT_USB_MUX 0
+#define I2C_PORT_CHARGER board_get_charger_i2c()
+#define I2C_PORT_SENSORS 1
+#define I2C_PORT_KB_DISCRETE 1
+#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
+#define I2C_PORT_BATTERY 2
+
+/* IT8801 I2C address */
+#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1
 
 /* Enable Accel over SPI */
-#define CONFIG_SPI_ACCEL_PORT    0  /* The first SPI master port (SPI2) */
+#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */
 
 #define CONFIG_KEYBOARD_PROTOCOL_MKBP
 #define CONFIG_MKBP_EVENT
 #define CONFIG_MKBP_USE_GPIO
-/* Define the MKBP events which are allowed to wakeup AP in S3. */
-#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \
-		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
 
 #define CONFIG_LED_ONOFF_STATES
 
+#undef CONFIG_GMR_TABLET_MODE
+#undef GPIO_TABLET_MODE_L
+#undef CONFIG_TABLET_MODE
+#undef CONFIG_TABLET_MODE_SWITCH
+
 #ifndef __ASSEMBLER__
 
 enum adc_channel {
@@ -141,7 +151,6 @@ void emmc_cmd_interrupt(enum gpio_signal signal);
 void bc12_interrupt(enum gpio_signal signal);
 void board_reset_pd_mcu(void);
 int board_get_version(void);
-int board_is_sourcing_vbus(int port);
 
 /* returns the i2c port number of charger/battery */
 int board_get_charger_i2c(void);
diff --git a/board/willow/build.mk b/board/willow/build.mk
index a6e1c010d7..f583684804 100644
--- a/board/willow/build.mk
+++ b/board/willow/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/willow/ec.tasklist b/board/willow/ec.tasklist
index c1330b86f8..fb131b8eb4 100644
--- a/board/willow/ec.tasklist
+++ b/board/willow/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/willow/gpio.inc b/board/willow/gpio.inc
index 1c5db485c8..684e1997c9 100644
--- a/board/willow/gpio.inc
+++ b/board/willow/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -37,11 +37,10 @@ GPIO_INT(IT8801_SMB_INT,    PIN(A, 8),  GPIO_INT_FALLING | GPIO_PULL_UP,
          io_expander_it8801_interrupt) /* KB_INT_ODL */
 GPIO_INT(AP_EC_WATCHDOG_L,  PIN(D, 2),  GPIO_INT_FALLING,
          chipset_watchdog_interrupt)
-GPIO_INT(TABLET_MODE_L,     PIN(B, 11), GPIO_INT_BOTH,
-         gmr_tablet_switch_isr)
 
 /* Unimplemented interrupts */
 GPIO(ALS_RGB_INT_ODL,      PIN(C, 10), GPIO_INPUT)
+GPIO(TABLET_MODE_L,        PIN(B, 11), GPIO_INPUT)
 
 /* Reset pins */
 GPIO(AP_SYS_RST_L,         PIN(C, 11), GPIO_OUT_LOW)
@@ -117,5 +116,5 @@ ALTERNATE(PIN_MASK(A, 0x8000), 0, MODULE_SPI,        0)
 /* EMMC SPI SLAVE: PB13/14/15 */
 ALTERNATE(PIN_MASK(B, 0xE000), 0, MODULE_SPI_FLASH,  0)
 /* SENSORS SPI MASTER: PB10, PB12, PC2, PC3 */
-ALTERNATE(PIN_MASK(B, 0x0400), 5, MODULE_SPI_MASTER, 0)
-ALTERNATE(PIN_MASK(C, 0x000C), 1, MODULE_SPI_MASTER, 0)
+ALTERNATE(PIN_MASK(B, 0x0400), 5, MODULE_SPI_CONTROLLER, 0)
+ALTERNATE(PIN_MASK(C, 0x000C), 1, MODULE_SPI_CONTROLLER, 0)
diff --git a/board/willow/led.c b/board/willow/led.c
index e5b204f934..6e177f15d6 100644
--- a/board/willow/led.c
+++ b/board/willow/led.c
@@ -1,37 +1,43 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Power and battery LED control for Willow
  */
 #include "common.h"
-#include "ioexpander.h"
 #include "driver/ioexpander/it8801.h"
 #include "ec_commands.h"
+#include "ioexpander.h"
 #include "led_common.h"
 #include "led_onoff_states.h"
 #define LED_ON_LVL 0
 #define LED_OFF_LVL 1
-const int led_charge_lvl_1 = 5;
-const int led_charge_lvl_2 = 95;
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
+__override const int led_charge_lvl_1 = 5;
+__override const int led_charge_lvl_2 = 95;
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-void led_set_color_battery(enum ec_led_colors color)
+__override void led_set_color_battery(enum ec_led_colors color)
 {
 	switch (color) {
 	case EC_LED_COLOR_AMBER:
@@ -77,4 +83,4 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 			led_set_color_battery(LED_OFF);
 	}
 	return EC_SUCCESS;
-}
\ No newline at end of file
+}
diff --git a/board/willow/vif_override.xml b/board/willow/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/willow/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/woomax/battery.c b/board/woomax/battery.c
index bd46c51cc7..0bed2f03f5 100644
--- a/board/woomax/battery.c
+++ b/board/woomax/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/woomax/board.c b/board/woomax/board.c
index 2a88f43bf4..cf47c10c70 100644
--- a/board/woomax/board.c
+++ b/board/woomax/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,15 +6,20 @@
 /* Trembyle board configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "button.h"
 #include "cbi_ec_fw_config.h"
-#include "driver/accelgyro_bmi_common.h"
+#include "cbi_ssfc.h"
+#include "cros_board_info.h"
 #include "driver/accel_kionix.h"
 #include "driver/accel_kx022.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "driver/accelgyro_icm426xx.h"
+#include "driver/accelgyro_icm_common.h"
 #include "driver/retimer/pi3dpx1207.h"
 #include "driver/retimer/pi3hdx1204.h"
+#include "driver/retimer/ps8802.h"
 #include "driver/retimer/ps8811.h"
+#include "driver/retimer/ps8818_public.h"
 #include "driver/temp_sensor/sb_tsi.h"
 #include "driver/usb_mux/amd_fp5.h"
 #include "extpower.h"
@@ -33,16 +38,15 @@
 #include "tablet_mode.h"
 #include "task.h"
 #include "temp_sensor.h"
-#include "thermistor.h"
+#include "temp_sensor/thermistor.h"
 #include "usb_charge.h"
 #include "usb_mux.h"
 
+/* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#ifdef HAS_TASK_MOTIONSENSE
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* Motion sensors */
 static struct mutex g_lid_mutex;
@@ -51,6 +55,7 @@ static struct mutex g_base_mutex;
 /* sensor private data */
 static struct kionix_accel_data g_kx022_data;
 static struct bmi_drv_data_t g_bmi160_data;
+static struct icm_drv_data_t g_icm426xx_data;
 
 /* Rotation matrix for the lid accelerometer */
 static const mat33_fp_t lid_standard_ref = {
@@ -60,12 +65,63 @@ static const mat33_fp_t lid_standard_ref = {
 };
 
 static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)},
+	{ 0, FLOAT_TO_FP(-1), 0 },
+	{ FLOAT_TO_FP(-1), 0, 0 },
+	{ 0, 0, FLOAT_TO_FP(-1) },
+};
+
+static const mat33_fp_t base_standard_ref_icm = {
+	{ FLOAT_TO_FP(1), 0, 0 },
+	{ 0, FLOAT_TO_FP(-1), 0 },
+	{ 0, 0, FLOAT_TO_FP(-1) },
 };
 
 /* TODO(gcc >= 5.0) Remove the casts to const pointer at rot_standard_ref */
+struct motion_sensor_t icm426xx_base_accel = {
+	.name = "Base Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs. */
+	.rot_standard_ref = &base_standard_ref_icm,
+	.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
+	.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100,
+		},
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	},
+};
+
+struct motion_sensor_t icm426xx_base_gyro = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &base_standard_ref_icm,
+	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
+	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
+};
+
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
 	 .name = "Lid Accel",
@@ -106,7 +162,7 @@ struct motion_sensor_t motion_sensors[] = {
 	 .drv_data = &g_bmi160_data,
 	 .port = I2C_PORT_SENSOR,
 	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 2, /* g, enough for laptop */
+	 .default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
 	 .rot_standard_ref = &base_standard_ref,
 	 .min_frequency = BMI_ACCEL_MIN_FREQ,
 	 .max_frequency = BMI_ACCEL_MAX_FREQ,
@@ -135,7 +191,7 @@ struct motion_sensor_t motion_sensors[] = {
 	 .port = I2C_PORT_SENSOR,
 	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
 	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = NULL,
+	 .rot_standard_ref = &base_standard_ref,
 	 .min_frequency = BMI_GYRO_MIN_FREQ,
 	 .max_frequency = BMI_GYRO_MAX_FREQ,
 	},
@@ -143,7 +199,23 @@ struct motion_sensor_t motion_sensors[] = {
 
 unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
-#endif /* HAS_TASK_MOTIONSENSE */
+static void setup_base_gyro_config(void)
+{
+	if (get_cbi_ssfc_base_sensor() == SSFC_BASE_GYRO_ICM426XX) {
+		motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
+		motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
+		ccprints("BASE GYRO is ICM426XX");
+	} else
+		ccprints("BASE GYRO is BMI160");
+}
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	if (get_cbi_ssfc_base_sensor() == SSFC_BASE_GYRO_ICM426XX)
+		icm426xx_interrupt(signal);
+	else
+		bmi160_interrupt(signal);
+}
 
 const struct power_signal_info power_signal_list[] = {
 	[X86_SLP_S3_N] = {
@@ -200,7 +272,7 @@ const int usb_port_enable[USBA_PORT_COUNT] = {
 const struct pi3hdx1204_tuning pi3hdx1204_tuning = {
 	.eq_ch0_ch1_offset = PI3HDX1204_EQ_DB710,
 	.eq_ch2_ch3_offset = PI3HDX1204_EQ_DB710,
-	.vod_offset = PI3HDX1204_VOD_115_ALL_CHANNELS,
+	.vod_offset = PI3HDX1204_VOD_130_ALL_CHANNELS,
 	.de_offset = PI3HDX1204_DE_DB_MINUS5,
 };
 
@@ -223,8 +295,8 @@ static void board_chipset_resume(void)
 		int val;
 
 		rv = i2c_read8(I2C_PORT_USBA0,
-				PS8811_I2C_ADDR_FLAGS + PS8811_REG_PAGE1,
-				PS8811_REG1_USB_BEQ_LEVEL, &val);
+			       PS8811_I2C_ADDR_FLAGS3 + PS8811_REG_PAGE1,
+			       PS8811_REG1_USB_BEQ_LEVEL, &val);
 		if (!rv)
 			break;
 	}
@@ -236,8 +308,7 @@ static void board_chipset_resume(void)
 	if (ec_config_has_hdmi_retimer_pi3hdx1204()) {
 		ioex_set_level(IOEX_HDMI_POWER_EN_DB, 1);
 		msleep(PI3HDX1204_POWER_ON_DELAY_MS);
-		pi3hdx1204_enable(I2C_PORT_TCPC1,
-				  PI3HDX1204_I2C_ADDR_FLAGS,
+		pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS,
 				  hpd);
 	}
 }
@@ -248,9 +319,7 @@ static void board_chipset_suspend(void)
 	ioex_set_level(IOEX_USB_A0_RETIMER_EN, 0);
 
 	if (ec_config_has_hdmi_retimer_pi3hdx1204()) {
-		pi3hdx1204_enable(I2C_PORT_TCPC1,
-				  PI3HDX1204_I2C_ADDR_FLAGS,
-				  0);
+		pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS, 0);
 		ioex_set_level(IOEX_HDMI_POWER_EN_DB, 0);
 	}
 
@@ -261,6 +330,136 @@ DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
 /*****************************************************************************
  * USB-C MUX/Retimer dynamic configuration
  */
+static int woomax_ps8818_mux_set(const struct usb_mux *me,
+				 mux_state_t mux_state)
+{
+	int rv = EC_SUCCESS;
+
+	/* USB specific config */
+	if (mux_state & USB_PD_MUX_USB_ENABLED) {
+		/* Boost the USB gain */
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_APTX1EQ_10G_LEVEL,
+					      PS8818_EQ_LEVEL_UP_MASK,
+					      PS8818_EQ_LEVEL_UP_18DB);
+		if (rv)
+			return rv;
+
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_APTX2EQ_10G_LEVEL,
+					      PS8818_EQ_LEVEL_UP_MASK,
+					      PS8818_EQ_LEVEL_UP_18DB);
+		if (rv)
+			return rv;
+
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_APTX1EQ_5G_LEVEL,
+					      PS8818_EQ_LEVEL_UP_MASK,
+					      PS8818_EQ_LEVEL_UP_19DB);
+		if (rv)
+			return rv;
+
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_APTX2EQ_5G_LEVEL,
+					      PS8818_EQ_LEVEL_UP_MASK,
+					      PS8818_EQ_LEVEL_UP_19DB);
+		if (rv)
+			return rv;
+	}
+
+	/* DP specific config */
+	if (mux_state & USB_PD_MUX_DP_ENABLED) {
+		/* Boost the DP gain */
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_DPEQ_LEVEL,
+					      PS8818_DPEQ_LEVEL_UP_MASK,
+					      PS8818_DPEQ_LEVEL_UP_19DB);
+		if (rv)
+			return rv;
+
+		/* Enable IN_HPD on the DB */
+		gpio_or_ioex_set_level(board_usbc1_retimer_inhpd, 1);
+	} else {
+		gpio_or_ioex_set_level(board_usbc1_retimer_inhpd, 0);
+	}
+
+	if (!(mux_state & USB_PD_MUX_POLARITY_INVERTED)) {
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_CRX1EQ_10G_LEVEL,
+					      PS8818_EQ_LEVEL_UP_MASK,
+					      PS8818_EQ_LEVEL_UP_19DB);
+		rv |= ps8818_i2c_write(me, PS8818_REG_PAGE1,
+				       PS8818_REG1_APRX1_DE_LEVEL, 0x02);
+	}
+
+	/* set the RX input termination */
+	rv |= ps8818_i2c_field_update8(me, PS8818_REG_PAGE1, PS8818_REG1_RX_PHY,
+				       PS8818_RX_INPUT_TERM_MASK,
+				       PS8818_RX_INPUT_TERM_85_OHM);
+	/* set register 0x40 ICP1 for 1G PD loop */
+	rv |= ps8818_i2c_write(me, PS8818_REG_PAGE1, 0x40, 0x84);
+
+	return rv;
+}
+
+static int woomax_ps8802_mux_set(const struct usb_mux *me,
+				 mux_state_t mux_state)
+{
+	int rv = EC_SUCCESS;
+
+	/* Make sure the PS8802 is awake */
+	rv = ps8802_i2c_wake(me);
+	if (rv)
+		return rv;
+
+	/* USB specific config */
+	if (mux_state & USB_PD_MUX_USB_ENABLED) {
+		/* Boost the USB gain */
+		rv = ps8802_i2c_field_update16(me, PS8802_REG_PAGE2,
+					       PS8802_REG2_USB_SSEQ_LEVEL,
+					       PS8802_USBEQ_LEVEL_UP_MASK,
+					       PS8802_USBEQ_LEVEL_UP_19DB);
+		if (rv)
+			return rv;
+	}
+
+	/* DP specific config */
+	if (mux_state & USB_PD_MUX_DP_ENABLED) {
+		/*Boost the DP gain */
+		rv = ps8802_i2c_field_update16(me, PS8802_REG_PAGE2,
+					       PS8802_REG2_DPEQ_LEVEL,
+					       PS8802_DPEQ_LEVEL_UP_MASK,
+					       PS8802_DPEQ_LEVEL_UP_19DB);
+		if (rv)
+			return rv;
+
+		/* Enable IN_HPD on the DB */
+		gpio_or_ioex_set_level(board_usbc1_retimer_inhpd, 1);
+	} else {
+		/* Disable IN_HPD on the DB */
+		gpio_or_ioex_set_level(board_usbc1_retimer_inhpd, 0);
+	}
+
+	/* Set extra swing level tuning at 800mV/P0 */
+	rv = ps8802_i2c_field_update8(me, PS8802_REG_PAGE1,
+				      PS8802_800MV_LEVEL_TUNING,
+				      PS8802_EXTRA_SWING_LEVEL_P0_MASK,
+				      PS8802_EXTRA_SWING_LEVEL_P0_UP_1);
+
+	return rv;
+}
+
+const struct usb_mux usbc1_woomax_ps8818 = {
+	.usb_port = USBC_PORT_C1,
+	.i2c_port = I2C_PORT_TCPC1,
+	.i2c_addr_flags = PS8818_I2C_ADDR0_FLAGS,
+	.driver = &ps8818_usb_retimer_driver,
+	.board_set = &woomax_ps8818_mux_set,
+};
+
+/* Place holder for second mux in USBC1 chain */
+struct usb_mux_chain usbc1_mux1;
+
 static void setup_mux(void)
 {
 	if (ec_config_has_usbc1_retimer_ps8802()) {
@@ -272,12 +471,11 @@ static void setup_mux(void)
 		 * Replace usb_muxes[USBC_PORT_C1] with the PS8802
 		 * table entry.
 		 */
-		memcpy(&usb_muxes[USBC_PORT_C1],
-		       &usbc1_ps8802,
-		       sizeof(struct usb_mux));
+		usb_muxes[USBC_PORT_C1].mux = &usbc1_ps8802;
 
 		/* Set the AMD FP5 as the secondary MUX */
-		usb_muxes[USBC_PORT_C1].next_mux = &usbc1_amd_fp5_usb_mux;
+		usbc1_mux1.mux = &usbc1_amd_fp5_usb_mux;
+		usbc1_ps8802.board_set = &woomax_ps8802_mux_set;
 
 		/* Don't have the AMD FP5 flip */
 		usbc1_amd_fp5_usb_mux.flags = USB_MUX_FLAG_SET_WITHOUT_FLIP;
@@ -291,13 +489,228 @@ static void setup_mux(void)
 		 * Replace usb_muxes[USBC_PORT_C1] with the AMD FP5
 		 * table entry.
 		 */
-		memcpy(&usb_muxes[USBC_PORT_C1],
-		       &usbc1_amd_fp5_usb_mux,
-		       sizeof(struct usb_mux));
+		usb_muxes[USBC_PORT_C1].mux = &usbc1_amd_fp5_usb_mux;
 
 		/* Set the PS8818 as the secondary MUX */
-		usb_muxes[USBC_PORT_C1].next_mux = &usbc1_ps8818;
+		usbc1_mux1.mux = &usbc1_woomax_ps8818;
+	}
+}
+
+enum pi3dpx1207_usb_conf { USB_DP = 0, USB_DP_INV, USB, USB_INV, DP, DP_INV };
+
+static uint8_t pi3dpx1207_picasso_eq[] = {
+	/*usb_dp*/
+	0x13,
+	0x11,
+	0x20,
+	0x62,
+	0x06,
+	0x5B,
+	0x5B,
+	0x07,
+	0x03,
+	0x40,
+	0xFC,
+	0x42,
+	0x71,
+	/*usb_dp_inv */
+	0x13,
+	0x11,
+	0x20,
+	0x72,
+	0x06,
+	0x03,
+	0x07,
+	0x5B,
+	0x5B,
+	0x23,
+	0xFC,
+	0x42,
+	0x71,
+	/*usb*/
+	0x13,
+	0x11,
+	0x20,
+	0x42,
+	0x00,
+	0x03,
+	0x07,
+	0x07,
+	0x03,
+	0x00,
+	0x42,
+	0x42,
+	0x71,
+	/*usb_inv*/
+	0x13,
+	0x11,
+	0x20,
+	0x52,
+	0x00,
+	0x03,
+	0x07,
+	0x07,
+	0x03,
+	0x02,
+	0x42,
+	0x42,
+	0x71,
+	/*dp*/
+	0x13,
+	0x11,
+	0x20,
+	0x22,
+	0x06,
+	0x5B,
+	0x5B,
+	0x5B,
+	0x5B,
+	0x60,
+	0xFC,
+	0xFC,
+	0x71,
+	/*dp_inv*/
+	0x13,
+	0x11,
+	0x20,
+	0x32,
+	0x06,
+	0x5B,
+	0x5B,
+	0x5B,
+	0x5B,
+	0x63,
+	0xFC,
+	0xFC,
+	0x71,
+};
+static uint8_t pi3dpx1207_dali_eq[] = {
+	/*usb_dp*/
+	0x13,
+	0x11,
+	0x20,
+	0x62,
+	0x06,
+	0x5B,
+	0x5B,
+	0x07,
+	0x07,
+	0x40,
+	0xFC,
+	0x42,
+	0x71,
+	/*usb_dp_inv*/
+	0x13,
+	0x11,
+	0x20,
+	0x72,
+	0x06,
+	0x07,
+	0x07,
+	0x5B,
+	0x5B,
+	0x23,
+	0xFC,
+	0x42,
+	0x71,
+	/*usb*/
+	0x13,
+	0x11,
+	0x20,
+	0x42,
+	0x00,
+	0x07,
+	0x07,
+	0x07,
+	0x07,
+	0x00,
+	0x42,
+	0x42,
+	0x71,
+	/*usb_inv*/
+	0x13,
+	0x11,
+	0x20,
+	0x52,
+	0x00,
+	0x07,
+	0x07,
+	0x07,
+	0x07,
+	0x02,
+	0x42,
+	0x42,
+	0x71,
+	/*dp*/
+	0x13,
+	0x11,
+	0x20,
+	0x22,
+	0x06,
+	0x5B,
+	0x5B,
+	0x5B,
+	0x5B,
+	0x60,
+	0xFC,
+	0xFC,
+	0x71,
+	/*dp_inv*/
+	0x13,
+	0x11,
+	0x20,
+	0x32,
+	0x06,
+	0x5B,
+	0x5B,
+	0x5B,
+	0x5B,
+	0x63,
+	0xFC,
+	0xFC,
+	0x71,
+};
+
+static int board_pi3dpx1207_mux_set(const struct usb_mux *me,
+				    mux_state_t mux_state)
+{
+	int rv = EC_SUCCESS;
+	enum pi3dpx1207_usb_conf usb_mode = 0;
+
+	/* USB */
+	if (mux_state & USB_PD_MUX_USB_ENABLED) {
+		/* USB with DP */
+		if (mux_state & USB_PD_MUX_DP_ENABLED) {
+			usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ?
+					   USB_DP_INV :
+					   USB_DP;
+		}
+		/* USB without DP */
+		else {
+			usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ?
+					   USB_INV :
+					   USB;
+		}
 	}
+	/* DP without USB */
+	else if (mux_state & USB_PD_MUX_DP_ENABLED) {
+		usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ? DP_INV :
+									DP;
+	}
+	/* Nothing enabled */
+	else
+		return EC_SUCCESS;
+
+	/* Write the retimer config byte */
+	if (ec_config_has_usbc1_retimer_ps8802())
+		rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags,
+			      &pi3dpx1207_dali_eq[usb_mode * 13], 13, NULL, 0);
+	else
+		rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags,
+			      &pi3dpx1207_picasso_eq[usb_mode * 13], 13, NULL,
+			      0);
+
+	return rv;
 }
 
 const struct pi3dpx1207_usb_control pi3dpx1207_controls[] = {
@@ -310,23 +723,30 @@ const struct pi3dpx1207_usb_control pi3dpx1207_controls[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(pi3dpx1207_controls) == USBC_PORT_COUNT);
 
-const struct usb_mux usbc0_pi3dpx1207_usb_retimer = {
-	.usb_port = USBC_PORT_C0,
-	.i2c_port = I2C_PORT_TCPC0,
-	.i2c_addr_flags = PI3DPX1207_I2C_ADDR_FLAGS,
-	.driver = &pi3dpx1207_usb_retimer,
+const struct usb_mux_chain usbc0_pi3dpx1207_usb_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.i2c_port = I2C_PORT_TCPC0,
+			.i2c_addr_flags = PI3DPX1207_I2C_ADDR_FLAGS,
+			.driver = &pi3dpx1207_usb_retimer,
+			.board_set = &board_pi3dpx1207_mux_set,
+		},
 };
 
-struct usb_mux usb_muxes[] = {
+struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.i2c_port = I2C_PORT_USB_AP_MUX,
-		.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
-		.driver = &amd_fp5_usb_mux_driver,
-		.next_mux = &usbc0_pi3dpx1207_usb_retimer,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.i2c_port = I2C_PORT_USB_AP_MUX,
+			.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
+			.driver = &amd_fp5_usb_mux_driver,
+		},
+		.next = &usbc0_pi3dpx1207_usb_retimer,
 	},
 	[USBC_PORT_C1] = {
 		/* Filled in dynamically at startup */
+		.next = &usbc1_mux1,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
@@ -336,9 +756,14 @@ BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
  */
 
 int board_usbc1_retimer_inhpd = IOEX_USB_C1_HPD_IN_DB;
-
+static uint32_t board_ver;
 static void setup_fw_config(void)
 {
+	cbi_get_board_version(&board_ver);
+
+	if (board_ver >= 2)
+		board_usbc1_retimer_inhpd = GPIO_USB_C1_HPD_IN_DB;
+
 	/* Enable Gyro interrupts */
 	gpio_enable_interrupt(GPIO_6AXIS_INT_L);
 
@@ -346,6 +771,7 @@ static void setup_fw_config(void)
 	if (ec_config_has_hdmi_retimer_pi3hdx1204())
 		gpio_enable_interrupt(GPIO_DP1_HPD_EC_IN);
 
+	setup_base_gyro_config();
 	setup_mux();
 }
 /* Use HOOK_PRIO_INIT_I2C + 2 to be after ioex_init(). */
@@ -358,14 +784,14 @@ DECLARE_HOOK(HOOK_INIT, setup_fw_config, HOOK_PRIO_INIT_I2C + 2);
 /* Physical fans. These are logically separate from pwm_channels. */
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = -1,
 };
 const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 3000,
-	.rpm_start = 3000,
-	.rpm_max = 4900,
+	.rpm_min = 1100,
+	.rpm_start = 1100,
+	.rpm_max = 5120,
 };
 const struct fan_t fans[] = {
 	[FAN_CH_0] = {
@@ -446,29 +872,36 @@ const struct temp_sensor_t temp_sensors[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
-const static struct ec_thermal_config thermal_thermistor = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(90),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(92),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
-	},
-	.temp_fan_off = C_TO_K(25),
-	.temp_fan_max = C_TO_K(58),
-};
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_THERMISTOR       \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(95), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(100), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(90), \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_thermistor =
+	THERMAL_THERMISTOR;
 
-const static struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(90),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(92),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
-	},
-	.temp_fan_off = C_TO_K(25),
-	.temp_fan_max = C_TO_K(58),
-};
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(95), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(100), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(90), \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 
 struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
 
@@ -497,8 +930,8 @@ static const struct ec_response_keybd_config woomax_kb = {
 	.capabilities = KEYBD_CAP_SCRNLOCK_KEY | KEYBD_CAP_NUMERIC_KEYPAD,
 };
 
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	return &woomax_kb;
 }
@@ -517,10 +950,9 @@ static void hdmi_hpd_handler(void)
 {
 	int hpd = gpio_get_level(GPIO_DP1_HPD_EC_IN);
 
-	pi3hdx1204_enable(I2C_PORT_TCPC1,
-			  PI3HDX1204_I2C_ADDR_FLAGS,
-			  chipset_in_or_transitioning_to_state(CHIPSET_STATE_ON)
-			  && hpd);
+	pi3hdx1204_enable(
+		I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS,
+		chipset_in_or_transitioning_to_state(CHIPSET_STATE_ON) && hpd);
 }
 DECLARE_DEFERRED(hdmi_hpd_handler);
 
@@ -530,3 +962,19 @@ void hdmi_hpd_interrupt(enum gpio_signal signal)
 	hook_call_deferred(&hdmi_hpd_handler_data, (2 * MSEC));
 }
 
+int board_usbc_port_to_hpd_gpio_or_ioex(int port)
+{
+	/* USB-C0 always uses USB_C0_HPD */
+	if (port == 0)
+		return GPIO_USB_C0_HPD;
+	/*
+	 * USB-C1 OPT3 DB use IOEX_USB_C1_HPD_IN_DB for board version 1
+	 * USB-C1 OPT3 DB use GPIO_USB_C1_HPD_IN_DB for board version 2
+	 */
+	else if (ec_config_has_mst_hub_rtd2141b())
+		return (board_ver >= 2) ? GPIO_USB_C1_HPD_IN_DB :
+					  IOEX_USB_C1_HPD_IN_DB;
+
+	/* USB-C1 OPT1 DB use DP2_HPD. */
+	return GPIO_DP2_HPD;
+}
diff --git a/board/woomax/board.h b/board/woomax/board.h
index 1c28c4c90d..3723d9d485 100644
--- a/board/woomax/board.h
+++ b/board/woomax/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,21 +10,21 @@
 
 #define VARIANT_ZORK_TREMBYLE
 
-#include <stdbool.h>
 #include "baseboard.h"
 
+#include <stdbool.h>
+
 #undef CONFIG_USB_PORT_POWER_SMART_PORT_COUNT
 #define CONFIG_USB_PORT_POWER_SMART_PORT_COUNT 1
 #define CONFIG_USBC_RETIMER_PI3DPX1207
-#define CONFIG_MKBP_USE_GPIO
-
-#define CONFIG_LED_POWER_LED
 
 /* Motion sensing drivers */
 #define CONFIG_ACCELGYRO_BMI160
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCEL_INTERRUPTS
+#define CONFIG_ACCELGYRO_ICM426XX
+#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 #define CONFIG_ACCEL_KX022
 #define CONFIG_CMD_ACCELS
 #define CONFIG_CMD_ACCEL_INFO
@@ -36,41 +36,47 @@
 #define CONFIG_GMR_TABLET_MODE
 
 /* Keyboard */
+#define CONFIG_KEYBOARD_VIVALDI
 #define CONFIG_KEYBOARD_REFRESH_ROW3
 #define CONFIG_KEYBOARD_KEYPAD
 
+/*
+ * Woomax's battery takes several seconds to come back out of its disconnect
+ * state (~4 seconds on the unit I have, so give it a little more for margin).
+ */
+#undef CONFIG_POWER_BUTTON_INIT_TIMEOUT
+#define CONFIG_POWER_BUTTON_INIT_TIMEOUT 5
+
+/* Thermal */
+#define CONFIG_CUSTOM_FAN_CONTROL
+
 /* GPIO mapping from board specific name to EC common name. */
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_EC_BATT_PRES_ODL
-#define CONFIG_SCI_GPIO			GPIO_EC_FCH_SCI_ODL
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_AP_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT_L		GPIO_EC_EDP_BL_DISABLE
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_FCH_PWR_BTN_L
-#define GPIO_PCH_RSMRST_L		GPIO_EC_FCH_RSMRST_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S5_L		GPIO_SLP_S5_L
-#define GPIO_PCH_SYS_PWROK		GPIO_EC_FCH_PWROK
-#define GPIO_PCH_WAKE_L			GPIO_EC_FCH_WAKE_L
-#define GPIO_POWER_BUTTON_L		GPIO_EC_PWR_BTN_ODL
-#define GPIO_S0_PGOOD			GPIO_S0_PWROK_OD
-#define GPIO_S5_PGOOD			GPIO_EC_PWROK_OD
-#define GPIO_SYS_RESET_L		GPIO_EC_SYS_RST_L
-#define GPIO_VOLUME_DOWN_L		GPIO_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE_L
+#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL
+#define CONFIG_SCI_GPIO GPIO_EC_FCH_SCI_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_AP_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_EDP_BL_DISABLE
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PCH_PWRBTN_L GPIO_EC_FCH_PWR_BTN_L
+#define GPIO_PCH_RSMRST_L GPIO_EC_FCH_RSMRST_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L
+#define GPIO_PCH_SYS_PWROK GPIO_EC_FCH_PWROK
+#define GPIO_PCH_WAKE_L GPIO_EC_FCH_WAKE_L
+#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL
+#define GPIO_S0_PGOOD GPIO_S0_PWROK_OD
+#define GPIO_S5_PGOOD GPIO_EC_PWROK_OD
+#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L
+#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
 
 #ifndef __ASSEMBLER__
 
-enum adc_channel {
-	ADC_TEMP_SENSOR_CHARGER,
-	ADC_TEMP_SENSOR_SOC,
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_TEMP_SENSOR_CHARGER, ADC_TEMP_SENSOR_SOC, ADC_CH_COUNT };
 
 enum battery_type {
 	BATTERY_C536,
@@ -83,11 +89,7 @@ enum mft_channel {
 	MFT_CH_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_FAN,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_FAN, PWM_CH_COUNT };
 
 enum temp_sensor_id {
 	TEMP_SENSOR_CHARGER = 0,
@@ -96,15 +98,11 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum usba_port {
-	USBA_PORT_A0 = 0,
-	USBA_PORT_COUNT
-};
+enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_COUNT };
 
 /*****************************************************************************
  * CBI EC FW Configuration
  */
-#include "cbi_ec_fw_config.h"
 
 /**
  * WOOMAX_MB_USBAC
@@ -146,60 +144,56 @@ enum ec_cfg_usb_db_type {
 	WOOMAX_DB_T_OPT3_USBAC_HDMI_MSTHUB = 1,
 };
 
-#define HAS_USBC1_RETIMER_PS8802 \
-			 (BIT(WOOMAX_DB_T_OPT3_USBAC_HDMI_MSTHUB))
+#include "cbi_ec_fw_config.h"
+
+#define HAS_USBC1_RETIMER_PS8802 (BIT(WOOMAX_DB_T_OPT3_USBAC_HDMI_MSTHUB))
 
 static inline bool ec_config_has_usbc1_retimer_ps8802(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_USBC1_RETIMER_PS8802);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_USBC1_RETIMER_PS8802);
 }
 
-#define HAS_USBC1_RETIMER_PS8818 \
-			(BIT(WOOMAX_DB_T_OPT1_USBAC_HMDI))
+#define HAS_USBC1_RETIMER_PS8818 (BIT(WOOMAX_DB_T_OPT1_USBAC_HMDI))
 
 static inline bool ec_config_has_usbc1_retimer_ps8818(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_USBC1_RETIMER_PS8818);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_USBC1_RETIMER_PS8818);
 }
 
-#define HAS_HDMI_RETIMER_PI3HDX1204 \
-			(BIT(WOOMAX_DB_T_OPT1_USBAC_HMDI))
+#define HAS_HDMI_RETIMER_PI3HDX1204 (BIT(WOOMAX_DB_T_OPT1_USBAC_HMDI))
 
 static inline bool ec_config_has_hdmi_retimer_pi3hdx1204(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_HDMI_RETIMER_PI3HDX1204);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_HDMI_RETIMER_PI3HDX1204);
 }
 
-#define HAS_MST_HUB_RTD2141B \
-			(BIT(WOOMAX_DB_T_OPT3_USBAC_HDMI_MSTHUB))
+#define HAS_MST_HUB_RTD2141B (BIT(WOOMAX_DB_T_OPT3_USBAC_HDMI_MSTHUB))
 
 static inline bool ec_config_has_mst_hub_rtd2141b(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_MST_HUB_RTD2141B);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_MST_HUB_RTD2141B);
 }
 
-/*
+/**
+ * @warning Callers must use gpio_or_ioex_set_level to handle the return result
+ * since either type of signal can be returned.
+ *
  * USB-C0 always uses USB_C0_HPD (= DP3_HPD).
  * USB-C1 OPT1 DB uses DP2_HPD.
  * USB-C1 OPT3 DB uses DP1_HPD via RTD2141B MST hub to drive AP
  *    HPD, EC drives MST hub HPD input from USB-PD messages.
+ *
+ * @return GPIO (gpio_signal) or IOEX (ioex_signal)
  */
+int board_usbc_port_to_hpd_gpio_or_ioex(int port);
+#define PORT_TO_HPD(port) board_usbc_port_to_hpd_gpio_or_ioex(port)
 
-#define PORT_TO_HPD(port) ((port == 0) \
-	? GPIO_USB_C0_HPD \
-	: (ec_config_has_mst_hub_rtd2141b()) \
-		? IOEX_USB_C1_HPD_IN_DB \
-		: GPIO_DP2_HPD)
-
-extern const struct usb_mux usbc0_pi3dpx1207_usb_retimer;
-extern const struct usb_mux usbc1_ps8802;
+extern const struct usb_mux_chain usbc0_pi3dpx1207_usb_retimer;
 extern const struct usb_mux usbc1_ps8818;
+extern struct usb_mux usbc1_ps8802;
 extern struct usb_mux usbc1_amd_fp5_usb_mux;
 void hdmi_hpd_interrupt(enum gpio_signal signal);
+void motion_interrupt(enum gpio_signal signal);
 
 #endif /* !__ASSEMBLER__ */
 
diff --git a/board/woomax/build.mk b/board/woomax/build.mk
index 1c0cbc4f63..61be1882bf 100644
--- a/board/woomax/build.mk
+++ b/board/woomax/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -11,5 +11,5 @@ CHIP_FAMILY:=npcx7
 CHIP_VARIANT:=npcx7m7wc
 BASEBOARD:=zork
 
-board-y=board.o led.o
+board-y=board.o led.o thermal.o
 board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/woomax/ec.tasklist b/board/woomax/ec.tasklist
index d9c1606eb2..abc796f74f 100644
--- a/board/woomax/ec.tasklist
+++ b/board/woomax/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/woomax/gpio.inc b/board/woomax/gpio.inc
index 6654b88570..f085134b2e 100644
--- a/board/woomax/gpio.inc
+++ b/board/woomax/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,7 +24,7 @@ GPIO_INT(ACOK_OD,		PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	extpower_inter
 GPIO_INT(EC_WP_L,		PIN(5, 0), GPIO_INT_BOTH,			switch_interrupt)
 GPIO_INT(VOLDN_BTN_ODL,		PIN(A, 6), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
 GPIO_INT(VOLUP_BTN_ODL,		PIN(9, 5), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-GPIO_INT(6AXIS_INT_L,		PIN(A, 0), GPIO_INT_FALLING | GPIO_PULL_UP,	bmi160_interrupt)
+GPIO_INT(6AXIS_INT_L,		PIN(A, 0), GPIO_INT_FALLING | GPIO_PULL_UP,	motion_interrupt)
 GPIO_INT(TABLET_MODE_L,		PIN(4, 4), GPIO_INT_BOTH,			gmr_tablet_switch_isr)
 GPIO_INT(DP1_HPD_EC_IN,		PIN(7, 5), GPIO_INT_BOTH,			hdmi_hpd_interrupt)
 
@@ -53,6 +53,7 @@ GPIO(EC_DP1_HPD,		PIN(F, 4), GPIO_OUT_LOW)			/* C1 DP Hotplug Detect */
 GPIO(DP2_HPD,			PIN(C, 1), GPIO_OUT_LOW)			/* C1 DP Hotplug Detect */
 GPIO(EC_H1_PACKET_MODE,		PIN(8, 6), GPIO_OUT_LOW)			/* H1 Packet Mode */
 GPIO(EN_PWR_TOUCHPAD_PS2,	PIN(C, 2), GPIO_INPUT)				/* Touchpad Power */
+GPIO(USB_C1_HPD_IN_DB,		PIN(B, 1), GPIO_OUT_LOW)			/* C1 HPD for board version 2 */
 
 UNIMPLEMENTED(NO_HPD)
 UNIMPLEMENTED(PCH_SMI_L)
@@ -75,7 +76,7 @@ IOEX(USB_C0_DATA_EN,		EXPIN(USBC_PORT_C0, 1, 4), GPIO_OUT_LOW)	/* C0 Data Enable
 IOEX(EN_USB_A0_5V,		EXPIN(USBC_PORT_C0, 1, 5), GPIO_OUT_LOW)	/* A0 5V Source Enable */
 IOEX(USB_A0_CHARGE_EN_L,	EXPIN(USBC_PORT_C0, 1, 6), GPIO_OUT_HIGH)	/* A0 5V High Current Enable */
 
-IOEX(USB_C1_HPD_IN_DB,		EXPIN(USBC_PORT_C1, 0, 2), GPIO_OUT_LOW)	/* C1 HPD */
+IOEX(USB_C1_HPD_IN_DB,		EXPIN(USBC_PORT_C1, 0, 2), GPIO_OUT_LOW)	/* C1 HPD for board version 1*/
 IOEX(HDMI_POWER_EN_DB,		EXPIN(USBC_PORT_C1, 0, 3), GPIO_OUT_LOW)	/* HDMI retimer power enable */
 IOEX(USB_C1_TCPC_FASTSW_CTL_EN,	EXPIN(USBC_PORT_C1, 0, 4), GPIO_OUT_LOW)	/* C1 FastSwitch Control */
 IOEX(USB_C1_MUX_RST_DB,		EXPIN(USBC_PORT_C1, 1, 1), GPIO_OUT_LOW)	/* C1 Mux Reset */
diff --git a/board/woomax/led.c b/board/woomax/led.c
index 6aa6c74f94..9ecd0e8110 100644
--- a/board/woomax/led.c
+++ b/board/woomax/led.c
@@ -1,44 +1,53 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "chipset.h"
 #include "ec_commands.h"
 #include "gpio.h"
 #include "led_common.h"
 #include "led_onoff_states.h"
-#include "chipset.h"
 
 #define LED_ON_LVL 0
 #define LED_OFF_LVL 1
 
-const int led_charge_lvl_1 = 5;
-
-const int led_charge_lvl_2 = 95;
+__override const int led_charge_lvl_1 = 5;
 
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+__override const int led_charge_lvl_2 = 95;
 
-const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	     3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	     3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    1 * LED_ONE_SEC },
+						  { LED_OFF,
+						    3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
 const enum ec_led_id supported_led_ids[] = {
 	EC_LED_ID_BATTERY_LED,
@@ -47,7 +56,7 @@ const enum ec_led_id supported_led_ids[] = {
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-void led_set_color_battery(enum ec_led_colors color)
+__override void led_set_color_battery(enum ec_led_colors color)
 {
 	switch (color) {
 	case EC_LED_COLOR_AMBER:
@@ -65,7 +74,7 @@ void led_set_color_battery(enum ec_led_colors color)
 	}
 }
 
-void led_set_color_power(enum ec_led_colors color)
+__override void led_set_color_power(enum ec_led_colors color)
 {
 	if (color == EC_LED_COLOR_WHITE)
 		gpio_set_level(GPIO_LED_3_L, LED_ON_LVL);
@@ -102,4 +111,3 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 
 	return EC_SUCCESS;
 }
-
diff --git a/board/woomax/thermal.c b/board/woomax/thermal.c
new file mode 100644
index 0000000000..a2ab52cc74
--- /dev/null
+++ b/board/woomax/thermal.c
@@ -0,0 +1,137 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "extpower.h"
+#include "fan.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "temp_sensor.h"
+#include "thermal.h"
+#include "util.h"
+
+/* Console output macros */
+#define CPUTS(outstr) cputs(CC_THERMAL, outstr)
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
+
+struct fan_step {
+	/*
+	 * Sensor 1~3 trigger point, set -1 if we're not using this
+	 * sensor to determine fan speed.
+	 */
+	int8_t on[TEMP_SENSOR_COUNT];
+
+	/*
+	 * Sensor 1~3 trigger point, set -1 if we're not using this
+	 * sensor to determine fan speed.
+	 */
+	int8_t off[TEMP_SENSOR_COUNT];
+
+	/* Fan rpm */
+	uint16_t rpm;
+};
+
+static const struct fan_step fan_step_table[] = {
+	{
+		/* level 0 */
+		.on = { -1, -1, 36 },
+		.off = { -1, -1, 99 },
+		.rpm = 0,
+	},
+	{
+		/* level 1 */
+		.on = { -1, -1, 40 },
+		.off = { -1, -1, 32 },
+		.rpm = 2244,
+	},
+	{
+		/* level 2 */
+		.on = { -1, -1, 45 },
+		.off = { -1, -1, 35 },
+		.rpm = 2580,
+	},
+	{
+		/* level 3 */
+		.on = { -1, -1, 50 },
+		.off = { -1, -1, 40 },
+		.rpm = 2824,
+	},
+	{
+		/* level 4 */
+		.on = { -1, -1, 55 },
+		.off = { -1, -1, 45 },
+		.rpm = 3120,
+	},
+	{
+		/* level 5 */
+		.on = { -1, -1, 60 },
+		.off = { -1, -1, 50 },
+		.rpm = 3321,
+	},
+	{
+		/* level 6 */
+		.on = { -1, -1, 70 },
+		.off = { -1, -1, 55 },
+		.rpm = 3780,
+	},
+	{
+		/* level 7 */
+		.on = { -1, -1, 80 },
+		.off = { -1, -1, 60 },
+		.rpm = 4330,
+	},
+	{
+		/* level 8 */
+		.on = { -1, -1, 99 },
+		.off = { -1, -1, 74 },
+		.rpm = 4915,
+	},
+};
+
+#define NUM_FAN_LEVELS ARRAY_SIZE(fan_step_table)
+
+int fan_table_to_rpm(int fan, int *temp)
+{
+	static int current_level;
+	static int prev_tmp[TEMP_SENSOR_COUNT];
+	int i;
+
+	/*
+	 * Comopare the current and previous temperature, we have
+	 * the three path:
+	 * 1. decreasing path. (check the release point)
+	 * 2. increasing path. (check the trigger point)
+	 * 3. invariant path. (return the current RPM)
+	 */
+	if (temp[TEMP_SENSOR_CPU] < prev_tmp[TEMP_SENSOR_CPU]) {
+		if (temp[TEMP_SENSOR_CPU] <
+		    fan_step_table[current_level].off[TEMP_SENSOR_CPU])
+			current_level = current_level - 1;
+	} else if (temp[TEMP_SENSOR_CPU] > prev_tmp[TEMP_SENSOR_CPU]) {
+		if (temp[TEMP_SENSOR_CPU] >
+		    fan_step_table[current_level].on[TEMP_SENSOR_CPU])
+			current_level = current_level + 1;
+	}
+
+	if (current_level < 0)
+		current_level = 0;
+	else if (current_level > NUM_FAN_LEVELS)
+		current_level = NUM_FAN_LEVELS;
+
+	for (i = 0; i < TEMP_SENSOR_COUNT; i++)
+		prev_tmp[i] = temp[i];
+
+	return fan_step_table[current_level].rpm;
+}
+
+void board_override_fan_control(int fan, int *tmp)
+{
+	if (chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND)) {
+		fan_set_rpm_mode(FAN_CH(fan), 1);
+		fan_set_rpm_target(FAN_CH(fan), fan_table_to_rpm(fan, tmp));
+	}
+}
diff --git a/board/woomax/vif_override.xml b/board/woomax/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/woomax/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/wormdingler/base_detect.c b/board/wormdingler/base_detect.c
new file mode 100644
index 0000000000..dca23b4d2e
--- /dev/null
+++ b/board/wormdingler/base_detect.c
@@ -0,0 +1,232 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Wormdingler base detection code */
+
+#include "adc.h"
+#include "base_state.h"
+#include "board.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "timer.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+
+/* Make sure POGO VBUS starts later then PP3300_HUB when power on  */
+#define BASE_DETECT_EN_LATER_US (600 * MSEC)
+
+/* Base detection and debouncing */
+#define BASE_DETECT_EN_DEBOUNCE_US (350 * MSEC)
+#define BASE_DETECT_DIS_DEBOUNCE_US (20 * MSEC)
+
+/*
+ * If the base status is unclear (i.e. not within expected ranges, read
+ * the ADC value again every 500ms.
+ */
+#define BASE_DETECT_RETRY_US (500 * MSEC)
+
+/*
+ * Lid has 604K pull-up, base has 30.1K pull-down, so the
+ * ADC value should be around 30.1/(604+30.1)*3300 = 156
+ *
+ * We add a significant margin on the maximum value, due to noise on the line,
+ * especially when PWM is active. See b/64193554 for details.
+ */
+#define BASE_DETECT_MIN_MV 120
+#define BASE_DETECT_MAX_MV 300
+
+/* Minimum ADC value to indicate base is disconnected for sure */
+#define BASE_DETECT_DISCONNECT_MIN_MV 1500
+
+/*
+ * Base EC pulses detection pin for 500 us to signal out of band USB wake (that
+ * can be used to wake system from deep S3).
+ */
+#define BASE_DETECT_PULSE_MIN_US 400
+#define BASE_DETECT_PULSE_MAX_US 650
+
+static uint64_t base_detect_debounce_time;
+
+static void base_detect_deferred(void);
+DECLARE_DEFERRED(base_detect_deferred);
+
+enum base_status {
+	BASE_UNKNOWN = 0,
+	BASE_DISCONNECTED = 1,
+	BASE_CONNECTED = 2,
+};
+
+static enum base_status current_base_status;
+
+/*
+ * This function is called whenever there is a change in the base detect
+ * status. Actions taken include:
+ * 1. Change in power to base
+ * 2. Indicate mode change to host.
+ * 3. Indicate tablet mode to host. Current assumption is that if base is
+ * disconnected then the system is in tablet mode, else if the base is
+ * connected, then the system is not in tablet mode.
+ */
+static void base_detect_change(enum base_status status)
+{
+	int connected = (status == BASE_CONNECTED);
+
+	if (current_base_status == status)
+		return;
+
+	gpio_set_level(GPIO_EN_BASE, connected);
+	base_set_state(connected);
+	current_base_status = status;
+}
+
+/* Measure detection pin pulse duration (used to wake AP from deep S3). */
+static uint64_t pulse_start;
+static uint32_t pulse_width;
+
+static void print_base_detect_value(int v, int tmp_pulse_width)
+{
+	CPRINTS("%s = %d (pulse %d)", adc_channels[ADC_BASE_DET].name, v,
+		tmp_pulse_width);
+}
+
+static void base_detect_deferred(void)
+{
+	uint64_t time_now = get_time().val;
+	int v;
+	uint32_t tmp_pulse_width = pulse_width;
+
+	if (base_detect_debounce_time > time_now) {
+		hook_call_deferred(&base_detect_deferred_data,
+				   base_detect_debounce_time - time_now);
+		return;
+	}
+
+	v = adc_read_channel(ADC_BASE_DET);
+	if (v == ADC_READ_ERROR)
+		return;
+
+	print_base_detect_value(v, tmp_pulse_width);
+
+	if (v >= BASE_DETECT_MIN_MV && v <= BASE_DETECT_MAX_MV) {
+		if (current_base_status != BASE_CONNECTED) {
+			base_detect_change(BASE_CONNECTED);
+		} else if (tmp_pulse_width >= BASE_DETECT_PULSE_MIN_US &&
+			   tmp_pulse_width <= BASE_DETECT_PULSE_MAX_US) {
+			CPRINTS("Sending event to AP");
+			host_set_single_event(EC_HOST_EVENT_KEY_PRESSED);
+		}
+		return;
+	}
+
+	if (v >= BASE_DETECT_DISCONNECT_MIN_MV) {
+		base_detect_change(BASE_DISCONNECTED);
+		return;
+	}
+
+	/* Unclear base status, schedule again in a while. */
+	hook_call_deferred(&base_detect_deferred_data, BASE_DETECT_RETRY_US);
+}
+
+static inline int detect_pin_connected(enum gpio_signal det_pin)
+{
+	return gpio_get_level(det_pin) == 0;
+}
+
+void base_detect_interrupt(enum gpio_signal signal)
+{
+	uint64_t time_now = get_time().val;
+	int debounce_us;
+
+	if (detect_pin_connected(signal))
+		debounce_us = BASE_DETECT_EN_DEBOUNCE_US;
+	else
+		debounce_us = BASE_DETECT_DIS_DEBOUNCE_US;
+
+	if (base_detect_debounce_time <= time_now) {
+		/*
+		 * Detect and measure detection pin pulse, when base is
+		 * connected. Only a single pulse is measured over a debounce
+		 * period. If no pulse, or multiple pulses are detected,
+		 * pulse_width is set to 0.
+		 */
+		if (current_base_status == BASE_CONNECTED &&
+		    !detect_pin_connected(signal)) {
+			pulse_start = time_now;
+		} else {
+			pulse_start = 0;
+		}
+		pulse_width = 0;
+
+		hook_call_deferred(&base_detect_deferred_data, debounce_us);
+	} else {
+		if (current_base_status == BASE_CONNECTED &&
+		    detect_pin_connected(signal) && !pulse_width &&
+		    pulse_start) {
+			/* First pulse within period. */
+			pulse_width = time_now - pulse_start;
+		} else {
+			pulse_start = 0;
+			pulse_width = 0;
+		}
+	}
+
+	base_detect_debounce_time = time_now + debounce_us;
+}
+
+static void base_enable(void)
+{
+	/* Enable base detection interrupt. */
+	base_detect_debounce_time = get_time().val;
+	hook_call_deferred(&base_detect_deferred_data, BASE_DETECT_EN_LATER_US);
+	gpio_enable_interrupt(GPIO_BASE_DET_L);
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, base_enable, HOOK_PRIO_DEFAULT);
+
+static void base_disable(void)
+{
+	/*
+	 * Disable base detection interrupt and disable power to base.
+	 * Set the state UNKNOWN so the next startup will initialize a
+	 * correct state and notify AP.
+	 */
+	gpio_disable_interrupt(GPIO_BASE_DET_L);
+	base_detect_change(BASE_UNKNOWN);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, base_disable, HOOK_PRIO_DEFAULT);
+
+static void base_init(void)
+{
+	/*
+	 * If we jumped to this image and chipset is already in S0, enable
+	 * base.
+	 */
+	if (system_jumped_late() && chipset_in_state(CHIPSET_STATE_ON))
+		base_enable();
+}
+DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT + 1);
+
+void base_force_state(enum ec_set_base_state_cmd state)
+{
+	if (state == EC_SET_BASE_STATE_ATTACH) {
+		gpio_disable_interrupt(GPIO_BASE_DET_L);
+		base_detect_change(BASE_CONNECTED);
+		CPRINTS("BD forced connected");
+	} else if (state == EC_SET_BASE_STATE_DETACH) {
+		gpio_disable_interrupt(GPIO_BASE_DET_L);
+		base_detect_change(BASE_DISCONNECTED);
+		CPRINTS("BD forced disconnected");
+	} else {
+		base_enable();
+		CPRINTS("BD forced reset");
+	}
+}
diff --git a/board/wormdingler/battery.c b/board/wormdingler/battery.c
new file mode 100644
index 0000000000..001cd0474b
--- /dev/null
+++ b/board/wormdingler/battery.c
@@ -0,0 +1,99 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "common.h"
+#include "util.h"
+
+/*
+ * Battery info for all wormdingler battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+
+const struct board_batt_params board_battery_info[] = {
+	/* Sunwoda L21D2PG2 */
+	[BATTERY_L21D2PG2] = {
+		.fuel_gauge = {
+			.manuf_name = "Sunwoda",
+			.device_name = "L21D2PG2",
+			.ship_mode = {
+				.reg_addr = 0x34,
+				.reg_data = { 0x0000, 0x1000 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x34,
+				.reg_mask = 0x0100,
+				.disconnect_val = 0x0,
+			}
+		},
+		.batt_info = {
+			.voltage_max            = 8860, /* mV */
+			.voltage_normal         = 7700, /* mV */
+			.voltage_min            = 6000, /* mV */
+			.precharge_current      = 200,  /* mA */
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 50,
+			.charging_min_c         = 0,
+			.charging_max_c         = 63,
+			.discharging_min_c      = -20,
+			.discharging_max_c      = 63,
+			.vendor_param_start     = 0x70,
+		},
+	},
+	/* BYD L21B2PG2 */
+	[BATTERY_L21B2PG2] = {
+		.fuel_gauge = {
+			.manuf_name = "BYD",
+			.device_name = "L21B2PG2",
+			.ship_mode = {
+				.reg_addr = 0x34,
+				.reg_data = { 0x0000, 0x1000 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x34,
+				.reg_mask = 0x0100,
+				.disconnect_val = 0x0,
+			}
+		},
+		.batt_info = {
+			.voltage_max            = 8860, /* mV */
+			.voltage_normal         = 7700, /* mV */
+			.voltage_min            = 6000, /* mV */
+			.precharge_current      = 256,  /* mA */
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 50,
+			.charging_min_c         = 0,
+			.charging_max_c         = 60,
+			.discharging_min_c      = -20,
+			.discharging_max_c      = 60,
+			.vendor_param_start     = 0x70,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_L21D2PG2;
diff --git a/board/wormdingler/board.c b/board/wormdingler/board.c
new file mode 100644
index 0000000000..4c02398e6c
--- /dev/null
+++ b/board/wormdingler/board.c
@@ -0,0 +1,661 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Wormdingler board-specific configuration */
+
+#include "adc_chip.h"
+#include "button.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "common.h"
+#include "driver/accel_bma2x2.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "driver/accelgyro_icm42607.h"
+#include "driver/accelgyro_icm_common.h"
+#include "driver/ln9310.h"
+#include "driver/ppc/sn5s330.h"
+#include "driver/tcpm/ps8xxx.h"
+#include "driver/tcpm/tcpci.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "keyboard_mkbp.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "peripheral_charger.h"
+#include "pi3usb9201.h"
+#include "power.h"
+#include "power/qcom.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "queue.h"
+#include "shi_chip.h"
+#include "switch.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "task.h"
+#include "usbc_ppc.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+#define KS_DEBOUNCE_US (30 * MSEC) /* Debounce time for kickstand switch */
+
+/* Forward declaration */
+static void tcpc_alert_event(enum gpio_signal signal);
+static void usb0_evt(enum gpio_signal signal);
+static void usb1_evt(enum gpio_signal signal);
+static void ppc_interrupt(enum gpio_signal signal);
+static void board_connect_c0_sbu(enum gpio_signal s);
+static void switchcap_interrupt(enum gpio_signal signal);
+
+#include "gpio_list.h"
+
+/* GPIO Interrupt Handlers */
+static void tcpc_alert_event(enum gpio_signal signal)
+{
+	int port = -1;
+
+	switch (signal) {
+	case GPIO_USB_C0_PD_INT_ODL:
+		port = 0;
+		break;
+	case GPIO_USB_C1_PD_INT_ODL:
+		port = 1;
+		break;
+	default:
+		return;
+	}
+
+	schedule_deferred_pd_interrupt(port);
+}
+
+static void usb0_evt(enum gpio_signal signal)
+{
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+
+static void usb1_evt(enum gpio_signal signal)
+{
+	usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+}
+
+static void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_SWCTL_INT_ODL:
+		sn5s330_interrupt(0);
+		break;
+	case GPIO_USB_C1_SWCTL_INT_ODL:
+		sn5s330_interrupt(1);
+		break;
+	default:
+		break;
+	}
+}
+
+static void board_connect_c0_sbu_deferred(void)
+{
+	/*
+	 * If CCD_MODE_ODL asserts, it means there's a debug accessory connected
+	 * and we should enable the SBU FETs.
+	 */
+	ppc_set_sbu(0, 1);
+}
+DECLARE_DEFERRED(board_connect_c0_sbu_deferred);
+
+static void board_connect_c0_sbu(enum gpio_signal s)
+{
+	hook_call_deferred(&board_connect_c0_sbu_deferred_data, 0);
+}
+
+static void switchcap_interrupt(enum gpio_signal signal)
+{
+	ln9310_interrupt(signal);
+}
+
+/* I2C port map */
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_POWER_SCL,
+	  .sda = GPIO_EC_I2C_POWER_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C0_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C0_PD_SDA },
+	{ .name = "tcpc1",
+	  .port = I2C_PORT_TCPC1,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C1_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C1_PD_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_EEPROM_SCL,
+	  .sda = GPIO_EC_I2C_EEPROM_SDA },
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_SENSOR_SCL,
+	  .sda = GPIO_EC_I2C_SENSOR_SDA },
+};
+
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	/* Measure VBUS through a 1/10 voltage divider */
+	[ADC_VBUS] = { "VBUS", NPCX_ADC_CH1, ADC_MAX_VOLT * 10,
+		       ADC_READ_MAX + 1, 0 },
+	/*
+	 * Adapter current output or battery charging/discharging current (uV)
+	 * 18x amplification on charger side.
+	 */
+	[ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH2, ADC_MAX_VOLT * 1000 / 18,
+			    ADC_READ_MAX + 1, 0 },
+	/*
+	 * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read
+	 * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and
+	 * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we
+	 * only divide by 2 (enough to avoid precision issues).
+	 */
+	[ADC_PSYS] = { "PSYS", NPCX_ADC_CH3,
+		       ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), 2, 0 },
+	/* Base detection */
+	[ADC_BASE_DET] = { "BASE_DET", NPCX_ADC_CH5, ADC_MAX_VOLT,
+			   ADC_READ_MAX + 1, 0 },
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+const struct pwm_t pwm_channels[] = {
+	/* TODO(waihong): Assign a proper frequency. */
+	[PWM_CH_DISPLIGHT] = { .channel = 5, .flags = 0, .freq = 4800 },
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+/* LN9310 switchcap */
+const struct ln9310_config_t ln9310_config = {
+	.i2c_port = I2C_PORT_POWER,
+	.i2c_addr_flags = LN9310_I2C_ADDR_0_FLAGS,
+};
+
+/* Power Path Controller */
+struct ppc_config_t ppc_chips[] = {
+	{ .i2c_port = I2C_PORT_TCPC0,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
+	{ .i2c_port = I2C_PORT_TCPC1,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
+};
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/* TCPC mux configuration */
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TCPC0,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+	},
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TCPC1,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+	},
+};
+
+/*
+ * Port-0/1 USB mux driver.
+ *
+ * The USB mux is handled by TCPC chip and the HPD update is through a GPIO
+ * to AP. But the TCPC chip is also needed to know the HPD status; otherwise,
+ * the mux misbehaves.
+ */
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
+	},
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
+	}
+};
+
+/* BC1.2 */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	{
+		.i2c_port = I2C_PORT_POWER,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+	{
+		.i2c_port = I2C_PORT_EEPROM,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+};
+
+/* Mutexes */
+static struct mutex g_lid_mutex;
+
+static struct bmi_drv_data_t g_bmi160_data;
+static struct icm_drv_data_t g_icm42607_data;
+
+enum lid_accelgyro_type {
+	LID_GYRO_NONE = 0,
+	LID_GYRO_BMI160 = 1,
+	LID_GYRO_ICM42607 = 2,
+};
+
+static enum lid_accelgyro_type lid_accelgyro_config;
+
+/* Matrix to rotate accelerometer into standard reference frame */
+const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+				      { 0, FLOAT_TO_FP(1), 0 },
+				      { 0, 0, FLOAT_TO_FP(1) } };
+
+const mat33_fp_t lid_standard_ref_icm42607 = { { 0, FLOAT_TO_FP(-1), 0 },
+					       { FLOAT_TO_FP(1), 0, 0 },
+					       { 0, 0, FLOAT_TO_FP(1) } };
+
+struct motion_sensor_t icm42607_lid_accel = {
+	.name = "Lid Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM42607,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_LID,
+	.drv = &icm42607_drv,
+	.mutex = &g_lid_mutex,
+	.drv_data = &g_icm42607_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
+	.rot_standard_ref = &lid_standard_ref_icm42607,
+	.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
+	.min_frequency = ICM42607_ACCEL_MIN_FREQ,
+	.max_frequency = ICM42607_ACCEL_MAX_FREQ,
+	.config = {
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	},
+};
+
+struct motion_sensor_t icm42607_lid_gyro = {
+	.name = "Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM42607,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_LID,
+	.drv = &icm42607_drv,
+	.mutex = &g_lid_mutex,
+	.drv_data = &g_icm42607_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &lid_standard_ref_icm42607,
+	.min_frequency = ICM42607_GYRO_MIN_FREQ,
+	.max_frequency = ICM42607_GYRO_MAX_FREQ,
+};
+
+struct motion_sensor_t motion_sensors[] = {
+	/*
+	 * Note: bmi160: supports accelerometer and gyro sensor
+	 * Requirement: accelerometer sensor must init before gyro sensor
+	 * DO NOT change the order of the following table.
+	 */
+	[LID_ACCEL] = {
+	 .name = "Lid Accel",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_BMI160,
+	 .type = MOTIONSENSE_TYPE_ACCEL,
+	 .location = MOTIONSENSE_LOC_LID,
+	 .drv = &bmi160_drv,
+	 .mutex = &g_lid_mutex,
+	 .drv_data = &g_bmi160_data,
+	 .port = I2C_PORT_SENSOR,
+	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+	 .rot_standard_ref = &lid_standard_ref,
+	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
+	 .min_frequency = BMI_ACCEL_MIN_FREQ,
+	 .max_frequency = BMI_ACCEL_MAX_FREQ,
+	 .config = {
+		 [SENSOR_CONFIG_EC_S0] = {
+			 .odr = 10000 | ROUND_UP_FLAG,
+		 },
+	 },
+	},
+	[LID_GYRO] = {
+	 .name = "Gyro",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_BMI160,
+	 .type = MOTIONSENSE_TYPE_GYRO,
+	 .location = MOTIONSENSE_LOC_LID,
+	 .drv = &bmi160_drv,
+	 .mutex = &g_lid_mutex,
+	 .drv_data = &g_bmi160_data,
+	 .port = I2C_PORT_SENSOR,
+	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
+	 .default_range = 1000, /* dps */
+	 .rot_standard_ref = &lid_standard_ref,
+	 .min_frequency = BMI_GYRO_MIN_FREQ,
+	 .max_frequency = BMI_GYRO_MAX_FREQ,
+	},
+};
+const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+static void board_detect_motionsensor(void)
+{
+	int val = -1;
+
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return;
+	if (lid_accelgyro_config != LID_GYRO_NONE)
+		return;
+
+	/* Check base accelgyro chip */
+	icm_read8(&icm42607_lid_accel, ICM42607_REG_WHO_AM_I, &val);
+	if (val == ICM42607_CHIP_ICM42607P) {
+		motion_sensors[LID_ACCEL] = icm42607_lid_accel;
+		motion_sensors[LID_GYRO] = icm42607_lid_gyro;
+		lid_accelgyro_config = LID_GYRO_ICM42607;
+		CPRINTS("LID Accelgyro: ICM42607");
+	} else {
+		lid_accelgyro_config = LID_GYRO_BMI160;
+		CPRINTS("LID Accelgyro: BMI160");
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_detect_motionsensor,
+	     HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_INIT, board_detect_motionsensor, HOOK_PRIO_DEFAULT + 1);
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	switch (lid_accelgyro_config) {
+	case LID_GYRO_ICM42607:
+		icm42607_interrupt(signal);
+		break;
+	case LID_GYRO_BMI160:
+	default:
+		bmi160_interrupt(signal);
+		break;
+	}
+}
+
+enum battery_cell_type board_get_battery_cell_type(void)
+{
+	return BATTERY_CELL_TYPE_2S;
+}
+
+static void board_switchcap_init(void)
+{
+	CPRINTS("Use switchcap: LN9310");
+
+	/* Configure and enable interrupt for LN9310 */
+	gpio_set_flags(GPIO_SWITCHCAP_PG_INT_L, GPIO_INT_FALLING);
+	gpio_enable_interrupt(GPIO_SWITCHCAP_PG_INT_L);
+
+	/* Only configure the switchcap if not sysjump */
+	if (!system_jumped_late())
+		ln9310_init();
+}
+
+/* Initialize board. */
+static void board_init(void)
+{
+	/* Enable BC1.2 interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_L);
+	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L);
+	gpio_enable_interrupt(GPIO_ACCEL_GYRO_INT_L);
+
+	/*
+	 * The H1 SBU line for CCD are behind PPC chip. The PPC internal FETs
+	 * for SBU may be disconnected after DP alt mode is off. Should enable
+	 * the CCD_MODE_ODL interrupt to make sure the SBU FETs are connected.
+	 */
+	gpio_enable_interrupt(GPIO_CCD_MODE_ODL);
+
+	/* Set the backlight duty cycle to 0. AP will override it later. */
+	pwm_set_duty(PWM_CH_DISPLIGHT, 0);
+
+	board_switchcap_init();
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+__overridable uint16_t board_get_ps8xxx_product_id(int port)
+{
+	if (check_ps8755_chip(port))
+		return PS8755_PRODUCT_ID;
+
+	return PS8805_PRODUCT_ID;
+}
+
+void board_tcpc_init(void)
+{
+	/* Only reset TCPC if not sysjump */
+	if (!system_jumped_late()) {
+		/* TODO(crosbug.com/p/61098): How long do we need to wait? */
+		board_reset_pd_mcu();
+	}
+
+	/* Enable PPC interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_SWCTL_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_SWCTL_INT_ODL);
+
+	/* Enable TCPC interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL);
+
+	/*
+	 * Initialize HPD to low; after sysjump SOC needs to see
+	 * HPD pulse to enable video path
+	 */
+	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
+		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
+
+void board_hibernate(void)
+{
+	int i;
+
+	/*
+	 * Sensors are unpowered in hibernate. Apply PD to the
+	 * interrupt lines such that they don't float.
+	 */
+	gpio_set_flags(GPIO_ACCEL_GYRO_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
+
+	/*
+	 * Board rev 1+ has the hardware fix. Don't need the following
+	 * workaround.
+	 */
+	if (system_get_board_version() >= 1)
+		return;
+
+	/*
+	 * Enable the PPC power sink path before EC enters hibernate;
+	 * otherwise, ACOK won't go High and can't wake EC up. Check the
+	 * bug b/170324206 for details.
+	 */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
+		ppc_vbus_sink_enable(i, 1);
+}
+
+/* Called on AP S0 -> S3 transition */
+static void board_chipset_suspend(void)
+{
+	/*
+	 * Turn off display backlight in S3. AP has its own control. The EC's
+	 * and the AP's will be AND'ed together in hardware.
+	 */
+	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 0);
+	pwm_enable(PWM_CH_DISPLIGHT, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S3 -> S0 transition */
+static void board_chipset_resume(void)
+{
+	/* Turn on display and keyboard backlight in S0. */
+	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 1);
+	if (pwm_get_duty(PWM_CH_DISPLIGHT))
+		pwm_enable(PWM_CH_DISPLIGHT, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
+
+void board_set_switchcap_power(int enable)
+{
+	gpio_set_level(GPIO_SWITCHCAP_ON_L, !enable);
+	ln9310_software_enable(enable);
+}
+
+int board_is_switchcap_enabled(void)
+{
+	return !gpio_get_level(GPIO_SWITCHCAP_ON_L);
+}
+
+int board_is_switchcap_power_good(void)
+{
+	return ln9310_power_good();
+}
+
+void board_reset_pd_mcu(void)
+{
+	cprints(CC_USB, "Resetting TCPCs...");
+	cflush();
+
+	gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
+	gpio_set_level(GPIO_USB_C1_PD_RST_L, 0);
+	msleep(PS8XXX_RESET_DELAY_MS);
+	gpio_set_level(GPIO_USB_C0_PD_RST_L, 1);
+	gpio_set_level(GPIO_USB_C1_PD_RST_L, 1);
+}
+
+void board_set_tcpc_power_mode(int port, int mode)
+{
+	/* Ignore the "mode" to turn the chip on.  We can only do a reset. */
+	if (mode)
+		return;
+
+	board_reset_pd_mcu();
+}
+
+int board_vbus_sink_enable(int port, int enable)
+{
+	/* Both ports are controlled by PPC SN5S330 */
+	return ppc_vbus_sink_enable(port, enable);
+}
+
+int board_is_sourcing_vbus(int port)
+{
+	/* Both ports are controlled by PPC SN5S330 */
+	return ppc_is_sourcing_vbus(port);
+}
+
+void board_overcurrent_event(int port, int is_overcurrented)
+{
+	/* TODO(b/120231371): Notify AP */
+	CPRINTS("p%d: overcurrent!", port);
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int i;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTS("Disabling all charging port");
+
+		/* Disable all ports. */
+		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (board_vbus_sink_enable(i, 0))
+				CPRINTS("Disabling p%d sink path failed.", i);
+		}
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (board_is_sourcing_vbus(port)) {
+		CPRINTS("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTS("New charge port: p%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		if (i == port)
+			continue;
+
+		if (board_vbus_sink_enable(i, 0))
+			CPRINTS("p%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (board_vbus_sink_enable(port, 1)) {
+		CPRINTS("p%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
+{
+	/*
+	 * Ignore lower charge ceiling on PD transition if our battery is
+	 * critical, as we may brownout.
+	 */
+	if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 &&
+	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
+		CPRINTS("Using max ilim %d", max_ma);
+		charge_ma = max_ma;
+	}
+
+	charge_set_input_current_limit(charge_ma, charge_mv);
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
+		if (gpio_get_level(GPIO_USB_C0_PD_RST_L))
+			status |= PD_STATUS_TCPC_ALERT_0;
+	if (!gpio_get_level(GPIO_USB_C1_PD_INT_ODL))
+		if (gpio_get_level(GPIO_USB_C1_PD_RST_L))
+			status |= PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
diff --git a/board/wormdingler/board.h b/board/wormdingler/board.h
new file mode 100644
index 0000000000..595e16eac8
--- /dev/null
+++ b/board/wormdingler/board.h
@@ -0,0 +1,105 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Wormdingler board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "baseboard.h"
+
+#define CONFIG_BUTTON_TRIGGERED_RECOVERY
+
+/* Internal SPI flash on NPCX7 */
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */
+
+/* Switchcap */
+#define CONFIG_LN9310
+
+/* Battery */
+#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
+#define CONFIG_BATTERY_REVIVE_DISCONNECT
+#define CONFIG_BATTERY_FUEL_GAUGE
+#define CONFIG_BATTERY_VENDOR_PARAM
+
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 5
+
+/* Enable PD3.0 */
+#define CONFIG_USB_PD_REV30
+
+/* BC 1.2 Charger */
+#define CONFIG_BC12_DETECT_PI3USB9201
+
+/* USB */
+#define CONFIG_USB_PD_TCPM_MULTI_PS8XXX
+#define CONFIG_USB_PD_TCPM_PS8755
+#define CONFIG_USB_PD_TCPM_PS8805
+#define CONFIG_USB_PD_TCPM_PS8805_FORCE_DID
+#define CONFIG_USBC_PPC_SN5S330
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+
+/* Lid accel/gyro */
+#define CONFIG_ACCELGYRO_BMI160
+#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
+#define OPT3001_I2C_ADDR_FLAGS OPT3001_I2C_ADDR1_FLAGS
+#define CONFIG_ACCELGYRO_ICM42607
+#define CONFIG_ACCELGYRO_ICM42607_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
+
+#define CONFIG_FRONT_PROXIMITY_SWITCH
+
+#define CONFIG_DETACHABLE_BASE
+#define CONFIG_BASE_ATTACHED_SWITCH
+
+/* GPIO alias */
+#define GPIO_AC_PRESENT GPIO_CHG_ACOK_OD
+#define GPIO_WP_L GPIO_EC_FLASH_WP_ODL
+#define GPIO_PMIC_RESIN_L GPIO_PM845_RESIN_L
+#define GPIO_SWITCHCAP_PG_INT_L GPIO_LN9310_INT
+
+#define CONFIG_MKBP_INPUT_DEVICES
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum adc_channel {
+	ADC_VBUS,
+	ADC_AMON_BMON,
+	ADC_PSYS,
+	ADC_BASE_DET,
+	ADC_CH_COUNT
+};
+
+/* Motion sensors */
+enum sensor_id {
+	LID_ACCEL = 0,
+	LID_GYRO,
+	SENSOR_COUNT,
+};
+
+enum pwm_channel { PWM_CH_DISPLIGHT = 0, PWM_CH_COUNT };
+
+/* List of possible batteries */
+enum battery_type {
+	BATTERY_L21D2PG2,
+	BATTERY_L21B2PG2,
+	BATTERY_TYPE_COUNT,
+};
+
+/* Reset all TCPCs. */
+void board_reset_pd_mcu(void);
+void board_set_tcpc_power_mode(int port, int mode);
+/* Base detection */
+void base_detect_interrupt(enum gpio_signal signal);
+
+void motion_interrupt(enum gpio_signal signal);
+
+#endif /* !defined(__ASSEMBLER__) */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/wormdingler/build.mk b/board/wormdingler/build.mk
new file mode 100644
index 0000000000..363ef59a16
--- /dev/null
+++ b/board/wormdingler/build.mk
@@ -0,0 +1,14 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx7
+CHIP_VARIANT:=npcx7m6fc
+BASEBOARD:=trogdor
+
+board-y=battery.o board.o led.o base_detect.o usbc_config.o
diff --git a/board/wormdingler/ec.tasklist b/board/wormdingler/ec.tasklist
new file mode 100644
index 0000000000..8fc8115afc
--- /dev/null
+++ b/board/wormdingler/ec.tasklist
@@ -0,0 +1,22 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/wormdingler/gpio.inc b/board/wormdingler/gpio.inc
new file mode 100644
index 0000000000..37e71977ac
--- /dev/null
+++ b/board/wormdingler/gpio.inc
@@ -0,0 +1,196 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+/* USB-C interrupts */
+GPIO_INT(USB_C0_PD_INT_ODL,    PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-0 TCPC */
+GPIO_INT(USB_C1_PD_INT_ODL,    PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-1 TCPC */
+GPIO_INT(USB_C0_SWCTL_INT_ODL, PIN(0, 3), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-0 PPC */
+GPIO_INT(USB_C1_SWCTL_INT_ODL, PIN(4, 0), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-1 PPC */
+GPIO_INT(USB_C0_BC12_INT_L,    PIN(6, 1), GPIO_INT_FALLING | GPIO_PULL_UP, usb0_evt)  /* Interrupt from port-0 BC1.2 */
+GPIO_INT(USB_C1_BC12_INT_L,    PIN(8, 2), GPIO_INT_FALLING | GPIO_PULL_UP, usb1_evt)  /* Interrupt from port-1 BC1.2 */
+
+/* System interrupts */
+GPIO_INT(CHG_ACOK_OD,       PIN(0, 0), GPIO_INT_BOTH, extpower_interrupt)  /* ACOK */
+GPIO_INT(CCD_MODE_ODL,      PIN(E, 3), GPIO_INT_FALLING, board_connect_c0_sbu)  /* Case Closed Debug Mode */
+GPIO_INT(EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)  /* Power button */
+GPIO_INT(EC_VOLDN_BTN_ODL,  PIN(7, 0), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Down button */
+GPIO_INT(EC_VOLUP_BTN_ODL,  PIN(F, 2), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Up button */
+GPIO_INT(EC_FLASH_WP_ODL,   PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)  /* Write protection */
+GPIO_INT(LID_OPEN_EC,       PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)  /* Lid open */
+GPIO_INT(AP_RST_L,          PIN(C, 1), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_ap_rst_interrupt)  /* PMIC to signal AP reset */
+GPIO_INT(PS_HOLD,           PIN(A, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, power_signal_interrupt)  /* Indicate when AP triggers reset/shutdown */
+GPIO_INT(AP_SUSPEND,        PIN(5, 7), GPIO_INT_BOTH, power_signal_interrupt)  /* Suspend signal from PMIC */
+GPIO_INT(DEPRECATED_AP_RST_REQ, PIN(C, 2), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V, power_signal_interrupt) /* Deprecated AP initiated reset indicator */
+
+/*
+ * When switch-cap is off, the POWER_GOOD signal is floating. Need a pull-down
+ * to make it low. Overload the interrupt function chipset_warm_reset_interrupt
+ * for not only signalling power_signal_interrupt but also handling the logic
+ * of WARM_RESET_L which is pulled-up by the same rail of POWER_GOOD.
+ */
+GPIO_INT(POWER_GOOD,        PIN(5, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, chipset_power_good_interrupt)  /* SRC_PP1800_S10A from PMIC */
+GPIO_INT(WARM_RESET_L,      PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_warm_reset_interrupt)  /* AP warm reset */
+GPIO_INT(AP_EC_SPI_CS_L,    PIN(5, 3), GPIO_INT_FALLING | GPIO_PULL_DOWN, shi_cs_event)  /* EC SPI Chip Select */
+
+GPIO_INT(BASE_DET_L,        PIN(3, 7), GPIO_INT_BOTH, base_detect_interrupt)  /* Detachable base attached? */
+
+/* Sensor interrupts */
+GPIO_INT(ACCEL_GYRO_INT_L,  PIN(A, 0), GPIO_INT_FALLING, motion_interrupt)  /* Accelerometer/gyro interrupt */
+
+/* Switchcap, for LN9310, it is the interrupt line of LN9310. */
+GPIO_INT(LN9310_INT,      PIN(E, 2), GPIO_INT_FALLING, switchcap_interrupt)
+
+/*
+ * EC_RST_ODL acts as a wake source from hibernate mode. However, it does not
+ * need to be an interrupt for normal EC operations. Simply set it an INPUT.
+ */
+GPIO(EC_RST_ODL,            PIN(0, 2), GPIO_INPUT)     /* EC reset */
+GPIO(EC_ENTERING_RW,        PIN(E, 1), GPIO_OUT_LOW)   /* Indicate when EC is entering RW code */
+GPIO(EC_BATT_PRES_ODL,      PIN(E, 5), GPIO_INPUT)     /* Battery Present */
+
+/* PMIC/AP 1.8V */
+GPIO(PM845_RESIN_L,         PIN(3, 2), GPIO_ODR_HIGH)  /* PMIC reset trigger */
+GPIO(PMIC_KPD_PWR_ODL,      PIN(D, 6), GPIO_ODR_HIGH)  /* PMIC power button */
+GPIO(EC_INT_L,              PIN(A, 2), GPIO_ODR_HIGH)  /* Interrupt line between AP and EC */
+GPIO(QSIP_ON,               PIN(5, 0), GPIO_OUT_LOW)   /* Not used, for non-switchcap testing */
+
+/* Power enables */
+GPIO(HIBERNATE_L,           PIN(5, 2), GPIO_ODR_HIGH)  /* EC hibernate */
+GPIO(SWITCHCAP_ON_L,        PIN(D, 5), GPIO_ODR_HIGH)  /* Enable switch cap */
+GPIO(EN_PP3300_A,           PIN(A, 6), GPIO_OUT_LOW)   /* Enable PP3300 */
+GPIO(EN_PP5000_A,           PIN(6, 7), GPIO_OUT_LOW)   /* Enable PP5000 */
+GPIO(EC_BL_DISABLE_L,       PIN(B, 6), GPIO_OUT_LOW)   /* Backlight disable signal from EC */
+
+/* Base detection */
+GPIO(EN_BASE,               PIN(0, 4), GPIO_OUT_LOW)   /* Enable power to detachable base */
+
+/* POGO */
+GPIO(POGO_VBUS_PRESENT,     PIN(6, 2), GPIO_INPUT)    /* POGO PIN */
+
+/* USB-C */
+GPIO(USB_C0_PD_RST_L,       PIN(F, 1), GPIO_ODR_HIGH)  /* Port-0 TCPC chip reset, actaully Open-Drain */
+GPIO(USB_C1_PD_RST_L,       PIN(E, 4), GPIO_ODR_HIGH)  /* Port-1 TCPC chip reset, actually Open-Drain */
+GPIO(DP_MUX_OE_L,           PIN(9, 6), GPIO_ODR_HIGH)  /* DP mux enable, actually Open-Drain */
+GPIO(DP_MUX_SEL,            PIN(4, 5), GPIO_OUT_LOW)   /* DP mux selection: L:C0, H:C1 */
+GPIO(DP_HOT_PLUG_DET,       PIN(9, 5), GPIO_OUT_LOW)   /* DP HPD to AP */
+
+/* LEDs */
+GPIO(EC_CHG_LED_R_C0,       PIN(C, 3), GPIO_OUT_LOW)
+GPIO(EC_CHG_LED_G_C0,       PIN(C, 4), GPIO_OUT_LOW)
+
+/*
+ * SPI host interface - enable PDs by default. These will be made functional
+ * by the SHI driver when the AP powers up, and restored back to GPIO when
+ * the AP powers down.
+ */
+GPIO(AP_EC_SPI_MOSI,        PIN(4, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(AP_EC_SPI_MISO,        PIN(4, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(AP_EC_SPI_CLK,         PIN(5, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+
+/* PWM */
+GPIO(EDP_BKLTCTL,           PIN(B, 7), GPIO_INPUT)     /* PWM5 */
+GPIO(WCAM_EC_VSYNC,         PIN(C, 0), GPIO_INPUT)     /* PWM6 */
+GPIO(FCAM_EC_VSYNC,         PIN(6, 0), GPIO_INPUT)     /* PWM7 */
+
+/* ADC */
+GPIO(PPVAR_BOOSTIN_SENSE,   PIN(4, 4), GPIO_INPUT)     /* ADC1 */
+GPIO(CHARGER_IADP,          PIN(4, 3), GPIO_INPUT)     /* ADC2 */
+GPIO(CHARGER_PMON,          PIN(4, 2), GPIO_INPUT)     /* ADC3 */
+
+/* I2C */
+GPIO(EC_I2C_POWER_SCL,      PIN(B, 5), GPIO_INPUT)
+GPIO(EC_I2C_POWER_SDA,      PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_PD_SCL,  PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_PD_SDA,  PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_PD_SCL,  PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_PD_SDA,  PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SCL,     PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SDA,     PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,     PIN(B, 3), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SENSOR_SDA,     PIN(B, 2), GPIO_INPUT | GPIO_SEL_1P8V)
+
+/* Board/SKU IDs */
+GPIO(BRD_ID0,               PIN(C, 7), GPIO_INPUT)
+GPIO(BRD_ID1,               PIN(9, 3), GPIO_INPUT)
+GPIO(BRD_ID2,               PIN(6, 3), GPIO_INPUT)
+GPIO(SKU_ID0,               PIN(F, 0), GPIO_INPUT)
+GPIO(SKU_ID1,               PIN(4, 1), GPIO_INPUT)
+GPIO(SKU_ID2,               PIN(D, 4), GPIO_INPUT)
+
+/* Special straps */
+GPIO(ARM_X86,               PIN(6, 6), GPIO_OUT_LOW)  /* NC, low for power saving */
+
+/* Unused GPIOs, NC. Apply PU for power saving */
+UNUSED(PIN(5, 1))
+UNUSED(PIN(F, 3))
+UNUSED(PIN(3, 1))
+UNUSED(PIN(3, 0))
+UNUSED(PIN(2, 7))
+UNUSED(PIN(2, 6))
+UNUSED(PIN(2, 5))
+UNUSED(PIN(2, 4))
+UNUSED(PIN(2, 3))
+UNUSED(PIN(2, 2))
+UNUSED(PIN(2, 1))
+UNUSED(PIN(2, 0))
+UNUSED(PIN(1, 7))
+UNUSED(PIN(1, 6))
+UNUSED(PIN(1, 5))
+UNUSED(PIN(1, 4))
+UNUSED(PIN(1, 3))
+UNUSED(PIN(1, 2))
+UNUSED(PIN(1, 1))
+UNUSED(PIN(1, 0))
+UNUSED(PIN(0, 7))
+UNUSED(PIN(0, 6))
+UNUSED(PIN(0, 5))
+UNUSED(PIN(9, 4))
+UNUSED(PIN(9, 7))
+UNUSED(PIN(A, 7))
+UNUSED(PIN(B, 0))
+UNUSED(PIN(A, 5))
+UNUSED(PIN(3, 5))
+UNUSED(PIN(7, 2))
+UNUSED(PIN(8, 1))
+UNUSED(PIN(7, 6))
+UNUSED(PIN(3, 4))
+UNUSED(PIN(C, 5))
+UNUSED(PIN(C, 6))
+UNUSED(PIN(A, 3))
+UNUSED(PIN(8, 3))
+UNUSED(PIN(B, 1))
+UNUSED(PIN(5, 6))
+UNUSED(PIN(8, 0))
+UNUSED(PIN(D, 0))
+UNUSED(PIN(D, 1))
+UNUSED(PIN(D, 3))
+UNUSED(PIN(7, 5))
+UNUSED(PIN(8, 6))
+UNUSED(PIN(7, 3))
+UNUSED(PIN(7, 4))
+UNUSED(PIN(D, 7))
+UNUSED(PIN(8, 5))
+
+/* Alternate functions GPIO definitions */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)            /* UART (GPIO64/65) */
+ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0)             /* I2C0 (GPIOB4/B5) */
+ALTERNATE(PIN_MASK(9, 0x07), 1, MODULE_I2C, 0)             /* I2C1 SDA (GPIO90), I2C2 (GPIO91/92) */
+ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, 0)             /* I2C1 SCL (GPIO87) */
+ALTERNATE(PIN_MASK(3, 0x48), 1, MODULE_I2C, 0)             /* I2C5 (GPIO33/36) */
+ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, GPIO_SEL_1P8V) /* I2C7 (GPIOB2/B3) - 1.8V */
+ALTERNATE(PIN_MASK(4, 0x1C), 0, MODULE_ADC, 0)             /* ADC1 (GPIO44), ADC2 (GPIO43), ADC3 (GPIO42) */
+ALTERNATE(PIN_MASK(4, 0xC0), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SDO (GPIO47), SHI_SDI (GPIO46) */
+ALTERNATE(PIN_MASK(5, 0x28), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SCLK (GPIO55), SHI_CS# (GPIO53) */
+ALTERNATE(PIN_MASK(B, 0x80), 1, MODULE_PWM, 0)             /* PWM5 (GPIOB7) - EDP_BKLTCTL */
+/* TODO(Camera?) should have a poper config for this, PWM or not */
+ALTERNATE(PIN_MASK(C, 0x01), 1, MODULE_PWM, 0)             /* PWM6 (GPIOC0) - WCAM_EC_VSYNC */
+ALTERNATE(PIN_MASK(6, 0x01), 1, MODULE_PWM, 0)             /* PWM7 (GPIO60) - FCAM_EC_VSYNC */
+
+
diff --git a/board/wormdingler/led.c b/board/wormdingler/led.c
new file mode 100644
index 0000000000..0b6f177b5a
--- /dev/null
+++ b/board/wormdingler/led.c
@@ -0,0 +1,163 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power and battery LED control.
+ */
+
+#include "battery.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "chipset.h"
+#include "ec_commands.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "led_common.h"
+#include "system.h"
+#include "util.h"
+
+#define LED_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS)
+/* Battery LED blinks every per 400ms */
+#define LED_HALF_ONE_SEC (500 / HOOK_TICK_INTERVAL_MS)
+
+#define BAT_LED_ON 1
+#define BAT_LED_OFF 0
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_BATTERY_LED,
+};
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+enum led_color {
+	LED_OFF = 0,
+	LED_RED,
+	LED_GREEN,
+	LED_AMBER,
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
+};
+
+static void led_set_color(enum led_color color)
+{
+	gpio_set_level(GPIO_EC_CHG_LED_R_C0,
+		       (color == LED_RED) ? BAT_LED_ON : BAT_LED_OFF);
+	gpio_set_level(GPIO_EC_CHG_LED_G_C0,
+		       (color == LED_GREEN) ? BAT_LED_ON : BAT_LED_OFF);
+	if (color == LED_AMBER) {
+		gpio_set_level(GPIO_EC_CHG_LED_R_C0, BAT_LED_ON);
+		gpio_set_level(GPIO_EC_CHG_LED_G_C0, BAT_LED_ON);
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	brightness_range[EC_LED_COLOR_RED] = 1;
+	brightness_range[EC_LED_COLOR_GREEN] = 1;
+	brightness_range[EC_LED_COLOR_AMBER] = 1;
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (brightness[EC_LED_COLOR_RED] != 0)
+		led_set_color(LED_RED);
+	else if (brightness[EC_LED_COLOR_GREEN] != 0)
+		led_set_color(LED_GREEN);
+	else if (brightness[EC_LED_COLOR_AMBER] != 0)
+		led_set_color(LED_AMBER);
+	else
+		led_set_color(LED_OFF);
+
+	return EC_SUCCESS;
+}
+
+static void board_led_set_battery(void)
+{
+	static int battery_ticks;
+	int color = LED_OFF;
+	int period = 0;
+	int percent = DIV_ROUND_NEAREST(charge_get_display_charge(), 10);
+
+	battery_ticks++;
+
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
+	case LED_PWRS_CHARGE_NEAR_FULL:
+		if (chipset_in_state(CHIPSET_STATE_ON |
+				     CHIPSET_STATE_ANY_SUSPEND |
+				     CHIPSET_STATE_ANY_OFF)) {
+			if (percent <= BATTERY_LEVEL_CRITICAL) {
+				/* battery capa <= 5%, Red */
+				color = LED_RED;
+			} else if (percent > BATTERY_LEVEL_CRITICAL &&
+				   percent < CONFIG_BATT_HOST_FULL_FACTOR) {
+				/* 5% < battery capa < 97%, Orange */
+				color = LED_AMBER;
+			} else {
+				/* battery capa >= 97%, Green */
+				color = LED_GREEN;
+			}
+		}
+		break;
+	case LED_PWRS_DISCHARGE:
+		/* Always indicate off on when discharging */
+		color = LED_OFF;
+		break;
+	case LED_PWRS_ERROR:
+		/* Battery error, Red on 1sec off 1sec */
+		period = (1 + 1) * LED_ONE_SEC;
+		battery_ticks = battery_ticks % period;
+		if (battery_ticks < 1 * LED_ONE_SEC)
+			color = LED_RED;
+		else
+			color = LED_OFF;
+		break;
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		color = LED_RED;
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		/* Factory mode, Red 2 sec, green 2 sec */
+		period = (2 + 2) * LED_ONE_SEC;
+		battery_ticks = battery_ticks % period;
+		if (battery_ticks < 2 * LED_ONE_SEC)
+			color = LED_RED;
+		else
+			color = LED_GREEN;
+		break;
+	default:
+		/* Other states don't alter LED behavior */
+		break;
+	}
+
+	led_set_color(color);
+}
+
+/* Called by hook task every TICK */
+static void led_tick(void)
+{
+	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
+		board_led_set_battery();
+}
+DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
+
+void led_control(enum ec_led_id led_id, enum ec_led_state state)
+{
+	enum led_color color;
+
+	if ((led_id != EC_LED_ID_RECOVERY_HW_REINIT_LED) &&
+	    (led_id != EC_LED_ID_SYSRQ_DEBUG_LED))
+		return;
+
+	if (state == LED_STATE_RESET) {
+		led_auto_control(EC_LED_ID_BATTERY_LED, 1);
+		board_led_set_battery();
+		return;
+	}
+
+	color = state ? LED_RED : LED_OFF;
+
+	led_auto_control(EC_LED_ID_BATTERY_LED, 0);
+
+	led_set_color(color);
+}
diff --git a/board/wormdingler/usbc_config.c b/board/wormdingler/usbc_config.c
new file mode 100644
index 0000000000..28f6b7a1c9
--- /dev/null
+++ b/board/wormdingler/usbc_config.c
@@ -0,0 +1,61 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Trogdor family-specific USB-C configuration */
+
+#include "charge_state.h"
+#include "charger.h"
+#include "charger/isl923x_public.h"
+#include "console.h"
+#include "usb_pd.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+};
+
+int charger_profile_override(struct charge_state_data *curr)
+{
+	int usb_mv;
+	int port;
+
+	if (curr->state != ST_CHARGE)
+		return 0;
+
+	/* Lower the max requested voltage to 5V when battery is full. */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
+	    !(curr->batt.flags & BATT_FLAG_BAD_STATUS) &&
+	    !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
+	    (curr->batt.status & STATUS_FULLY_CHARGED))
+		usb_mv = 5000;
+	else
+		usb_mv = PD_MAX_VOLTAGE_MV;
+
+	if (pd_get_max_voltage() != usb_mv) {
+		CPRINTS("VBUS limited to %dmV", usb_mv);
+		for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++)
+			pd_set_external_voltage_limit(port, usb_mv);
+	}
+
+	return 0;
+}
+
+enum ec_status charger_profile_override_get_param(uint32_t param,
+						  uint32_t *value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+enum ec_status charger_profile_override_set_param(uint32_t param,
+						  uint32_t value)
+{
+	return EC_RES_INVALID_PARAM;
+}
diff --git a/board/wormdingler/vif_override.xml b/board/wormdingler/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/wormdingler/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/yorp/battery.c b/board/yorp/battery.c
index 1d8ec33d3d..d391942ab3 100644
--- a/board/yorp/battery.c
+++ b/board/yorp/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/yorp/board.c b/board/yorp/board.c
index 1d4597311a..475ced087c 100644
--- a/board/yorp/board.c
+++ b/board/yorp/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,6 @@
 /* Yorp board-specific configuration */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "battery.h"
 #include "charge_manager.h"
 #include "charge_state.h"
@@ -32,17 +31,17 @@
 #include "switch.h"
 #include "system.h"
 #include "tablet_mode.h"
-#include "tcpci.h"
+#include "tcpm/tcpci.h"
 #include "temp_sensor.h"
-#include "thermistor.h"
+#include "temp_sensor/thermistor.h"
 #include "usb_mux.h"
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 static void ppc_interrupt(enum gpio_signal signal)
 {
@@ -65,26 +64,26 @@ static void ppc_interrupt(enum gpio_signal signal)
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_AMB] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_AMB] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				  ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_CHARGER] = { "TEMP_CHARGER", NPCX_ADC_CH1,
+				      ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp,
-				 .idx = 0},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
+	[TEMP_SENSOR_BATTERY] = { .name = "Battery",
+				  .type = TEMP_SENSOR_TYPE_BATTERY,
+				  .read = charge_get_battery_temp,
+				  .idx = 0 },
+	[TEMP_SENSOR_AMBIENT] = { .name = "Ambient",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_51k1_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_AMB },
+	[TEMP_SENSOR_CHARGER] = { .name = "Charger",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_13k7_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_CHARGER },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -94,11 +93,9 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0,  0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+				       { FLOAT_TO_FP(1), 0, 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
 
 /* sensor private data */
 static struct kionix_accel_data g_kx022_data;
@@ -143,8 +140,6 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_base_mutex,
 		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
 				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
 		.port = I2C_PORT_SENSOR,
 		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
 		.rot_standard_ref = &base_standard_ref,
@@ -175,8 +170,6 @@ struct motion_sensor_t motion_sensors[] = {
 		.mutex = &g_base_mutex,
 		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
 				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
 		.port = I2C_PORT_SENSOR,
 		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
 		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
@@ -196,14 +189,14 @@ static void board_init(void)
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
-void board_hibernate_late(void) {
-
+void board_hibernate_late(void)
+{
 	int i;
 
 	const uint32_t hibernate_pins[][2] = {
 		/* Turn off LEDs before going to hibernate */
-		{GPIO_BAT_LED_BLUE_L, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_BAT_LED_ORANGE_L, GPIO_INPUT | GPIO_PULL_UP},
+		{ GPIO_BAT_LED_BLUE_L, GPIO_INPUT | GPIO_PULL_UP },
+		{ GPIO_BAT_LED_ORANGE_L, GPIO_INPUT | GPIO_PULL_UP },
 	};
 
 	for (i = 0; i < ARRAY_SIZE(hibernate_pins); ++i)
@@ -211,25 +204,6 @@ void board_hibernate_late(void) {
 }
 
 #ifndef TEST_BUILD
-/* This callback disables keyboard when convertibles are fully open */
-void lid_angle_peripheral_enable(int enable)
-{
-	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
-
-	if (enable) {
-		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
-	} else {
-		/*
-		 * Ensure that the chipset is off before disabling the keyboard.
-		 * When the chipset is on, the EC keeps the keyboard enabled and
-		 * the AP decides whether to ignore input devices or not.
-		 */
-		if (!chipset_in_s0)
-			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
-	}
-}
-
-
 static void post_old_board_warning(void)
 {
 	uint32_t board_id = 0;
@@ -244,7 +218,7 @@ static void post_old_board_warning(void)
 	 * warning.
 	 */
 	CPRINTS("\n\n\n ***** BOARD ID 0 is not officially supported!!! *****"
-			"\n\n\n");
+		"\n\n\n");
 }
 DECLARE_HOOK(HOOK_INIT, post_old_board_warning, HOOK_PRIO_INIT_I2C + 1);
 #endif
diff --git a/board/yorp/board.h b/board/yorp/board.h
index 01f701184a..8ffb6d2781 100644
--- a/board/yorp/board.h
+++ b/board/yorp/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,6 +13,8 @@
 #define VARIANT_OCTOPUS_CHARGER_ISL9238
 #include "baseboard.h"
 
+#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD
+
 /* EC console commands  */
 #define CONFIG_CMD_ACCELS
 #define CONFIG_CMD_ACCEL_INFO
@@ -24,8 +26,8 @@
 #define CONFIG_USB_PD_VBUS_MEASURE_NOT_PRESENT
 
 /* Sensors */
-#define CONFIG_ACCEL_KX022		/* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM	/* Base accel */
+#define CONFIG_ACCEL_KX022 /* Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
 /* Sensors without hardware FIFO are in forced mode */
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
 
@@ -48,8 +50,8 @@
 #include "registers.h"
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_AMB,		/* ADC0 */
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC1 */
+	ADC_TEMP_SENSOR_AMB, /* ADC0 */
+	ADC_TEMP_SENSOR_CHARGER, /* ADC1 */
 	ADC_CH_COUNT
 };
 
@@ -60,18 +62,10 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_COUNT };
 
 /* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
diff --git a/board/yorp/build.mk b/board/yorp/build.mk
index 3d04b75731..998a65a3de 100644
--- a/board/yorp/build.mk
+++ b/board/yorp/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/yorp/ec.tasklist b/board/yorp/ec.tasklist
index d98db145e7..977b8b01be 100644
--- a/board/yorp/ec.tasklist
+++ b/board/yorp/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/yorp/gpio.inc b/board/yorp/gpio.inc
index 9edd6107c6..b3dbf60ab8 100644
--- a/board/yorp/gpio.inc
+++ b/board/yorp/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/yorp/led.c b/board/yorp/led.c
index e5dd48327b..f8b9898046 100644
--- a/board/yorp/led.c
+++ b/board/yorp/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,34 +10,44 @@
 #include "led_common.h"
 #include "led_onoff_states.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
-const int led_charge_lvl_1 = 0;
+__override const int led_charge_lvl_1;
 
-const int led_charge_lvl_2 = 100;
+__override const int led_charge_lvl_2 = 100;
 
 /* Yorp: Note there is only LED for charge / power */
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]       = {{EC_LED_COLOR_BLUE,  2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_BLUE,  2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-};
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_BLUE,
+					     2 * LED_ONE_SEC },
+					   { EC_LED_COLOR_AMBER,
+					     2 * LED_ONE_SEC } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_BLUE,
+					    2 * LED_ONE_SEC },
+					  { EC_LED_COLOR_AMBER,
+					    2 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+	};
 BUILD_ASSERT(ARRAY_SIZE(led_bat_state_table) == LED_NUM_STATES);
 
 const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-void led_set_color_battery(enum ec_led_colors color)
+__override void led_set_color_battery(enum ec_led_colors color)
 {
 	switch (color) {
 	case EC_LED_COLOR_BLUE:
@@ -72,4 +82,3 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 
 	return EC_SUCCESS;
 }
-
diff --git a/board/yorp/vif_override.xml b/board/yorp/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/yorp/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/board/zinger/board.c b/board/zinger/board.c
index 74da1ca9eb..41d91ab438 100644
--- a/board/zinger/board.c
+++ b/board/zinger/board.c
@@ -1,10 +1,11 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 /* Tiny charger configuration */
 
 #include "common.h"
+#include "cros_version.h"
 #include "debug_printf.h"
 #include "ec_commands.h"
 #include "registers.h"
@@ -15,19 +16,16 @@
 #include "task.h"
 #include "usb_pd.h"
 #include "util.h"
-#include "version.h"
 
 /* Large 768-Byte buffer for RSA computation : could be re-use afterwards... */
 static uint32_t rsa_workbuf[3 * RSANUMWORDS];
 
-extern void pd_rx_handler(void);
-
 /* RW firmware reset vector */
-static uint32_t * const rw_rst =
-	(uint32_t *)(CONFIG_PROGRAM_MEMORY_BASE+CONFIG_RW_MEM_OFF+4);
+static uint32_t *const rw_rst =
+	(uint32_t *)(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RW_MEM_OFF + 4);
 
 /* External interrupt EXTINT7 for external comparator on PA7 */
-void pd_rx_interrupt(void)
+static void pd_rx_interrupt(void)
 {
 	/* trigger reception handling */
 	pd_rx_handler();
@@ -40,7 +38,7 @@ static void jump_to_rw(void)
 
 	debug_printf("Jump to RW\n");
 	/* Disable interrupts */
-	asm volatile("cpsid i");
+	interrupt_disable();
 	/* Call RW firmware reset vector */
 	jump_rw_rst();
 }
@@ -59,8 +57,8 @@ static int check_rw_valid(void *rw_hash)
 		return 0;
 
 	good = rsa_verify((const struct rsa_public_key *)CONFIG_RO_PUBKEY_ADDR,
-			  (const uint8_t *)CONFIG_RW_SIG_ADDR,
-			  rw_hash, rsa_workbuf);
+			  (const uint8_t *)CONFIG_RW_SIG_ADDR, rw_hash,
+			  rsa_workbuf);
 	if (!good) {
 		debug_printf("RSA FAILED\n");
 		pd_log_event(PD_EVENT_ACC_RW_FAIL, 0, 0, NULL);
@@ -77,8 +75,7 @@ int main(void)
 	void *rw_hash;
 
 	hardware_init();
-	debug_printf("%s started\n",
-		is_ro_mode() ? "RO" : "RW");
+	debug_printf("%s started\n", is_ro_mode() ? "RO" : "RW");
 
 	/* the RO partition protection is not enabled : do it */
 	if (!flash_physical_is_permanently_protected())
diff --git a/board/zinger/board.h b/board/zinger/board.h
index 30abce115a..1ca83354bc 100644
--- a/board/zinger/board.h
+++ b/board/zinger/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -37,11 +37,11 @@
 #undef CONFIG_DEBUG_ASSERT
 #undef CONFIG_DEBUG_EXCEPTIONS
 #undef CONFIG_DEBUG_STACK_OVERFLOW
-#undef CONFIG_FLASH
+#undef CONFIG_FLASH_CROS
 #undef CONFIG_FLASH_PHYSICAL
 #undef CONFIG_FMAP
 /* Not using pstate but keep some space for the public key */
-#undef  CONFIG_FW_PSTATE_SIZE
+#undef CONFIG_FW_PSTATE_SIZE
 #define CONFIG_FW_PSTATE_SIZE 544
 #define CONFIG_HIBERNATE
 #define CONFIG_HIBERNATE_WAKEUP_PINS STM32_PWR_CSR_EWUP1
@@ -59,7 +59,7 @@
 #undef CONFIG_USB_PD_DUAL_ROLE
 #undef CONFIG_USB_PD_INTERNAL_COMP
 #define CONFIG_USB_PD_LOGGING
-#undef  CONFIG_EVENT_LOG_SIZE
+#undef CONFIG_EVENT_LOG_SIZE
 #define CONFIG_EVENT_LOG_SIZE 256
 #define CONFIG_USB_PD_LOW_POWER_IDLE_WHEN_CONNECTED
 #define CONFIG_USB_PD_PORT_MAX_COUNT 1
@@ -73,8 +73,8 @@
 #undef CONFIG_WATCHDOG_PERIOD_MS
 #define CONFIG_WATCHDOG_PERIOD_MS 2300
 
-/* debug printf flash footprinf is about 1400 bytes */
-#define CONFIG_DEBUG_PRINTF
+/* debug printf flash footprint is about 1400 bytes */
+#undef CONFIG_DEBUG_PRINTF
 #define UARTN CONFIG_UART_CONSOLE
 #define UARTN_BASE STM32_USART_BASE(CONFIG_UART_CONSOLE)
 
@@ -90,9 +90,9 @@
 #ifndef __ASSEMBLER__
 
 #include "common.h"
+#include "gpio_signal.h"
 
 /* No GPIO abstraction layer */
-enum gpio_signal;
 
 enum adc_channel {
 	ADC_CH_CC1_PD = 1,
@@ -105,10 +105,11 @@ enum adc_channel {
 #define ADC_CH_CC2_PD ADC_CH_CC1_PD
 
 /* 3.0A Rp */
-#define PD_SRC_VNC (PD_SRC_3_0_VNC_MV * 4096 / 3300/* 12-bit ADC, 3.3V range */)
+#define PD_SRC_VNC \
+	(PD_SRC_3_0_VNC_MV * 4096 / 3300 /* 12-bit ADC, 3.3V range */)
 
 /* delay necessary for the voltage transition on the power supply */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  50000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 50000 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 50000 /* us */
 
 /* Initialize all useful registers */
diff --git a/board/zinger/build.mk b/board/zinger/build.mk
index 566cf34ce0..da1878efe9 100644
--- a/board/zinger/build.mk
+++ b/board/zinger/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
+# Copyright 2014 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -10,4 +10,4 @@ CHIP:=stm32
 CHIP_FAMILY:=stm32f0
 CHIP_VARIANT:=stm32f03x
 
-board-y=board.o hardware.o runtime.o usb_pd_policy.o
+board-y=board.o hardware.o runtime.o usb_pd_policy.o usb_pd_pdo.o
diff --git a/board/zinger/ec.irqlist b/board/zinger/ec.irqlist
index 690fa950fc..186c0f6338 100644
--- a/board/zinger/ec.irqlist
+++ b/board/zinger/ec.irqlist
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/zinger/ec.tasklist b/board/zinger/ec.tasklist
index 091eb90a22..89d9ffab76 100644
--- a/board/zinger/ec.tasklist
+++ b/board/zinger/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/zinger/gpio.inc b/board/zinger/gpio.inc
new file mode 100644
index 0000000000..65e3066695
--- /dev/null
+++ b/board/zinger/gpio.inc
@@ -0,0 +1,8 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Stub file only */
\ No newline at end of file
diff --git a/board/zinger/hardware.c b/board/zinger/hardware.c
index ceeac38d38..0ad5b7ff94 100644
--- a/board/zinger/hardware.c
+++ b/board/zinger/hardware.c
@@ -1,11 +1,10 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 /* Hardware initialization and common functions */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "common.h"
 #include "cpu.h"
 #include "registers.h"
@@ -40,16 +39,16 @@ static void power_init(void)
 	/* enable TIM2, TIM3, TIM14, PWR */
 	STM32_RCC_APB1ENR = 0x10000103;
 	/* enable DMA, SRAM, CRC, GPA, GPB, GPF */
-	STM32_RCC_AHBENR  = 0x460045;
+	STM32_RCC_AHBENR = 0x460045;
 }
 
 /* GPIO setting helpers */
-#define OUT(n) (1 << ((n) * 2))
-#define AF(n) (2 << ((n) * 2))
-#define ANALOG(n) (3 << ((n) * 2))
+#define OUT(n) (1 << ((n)*2))
+#define AF(n) (2 << ((n)*2))
+#define ANALOG(n) (3 << ((n)*2))
 #define HIGH(n) (1 << (n))
 #define ODR(n) (1 << (n))
-#define HISPEED(n) (3 << ((n) * 2))
+#define HISPEED(n) (3 << ((n)*2))
 #define AFx(n, x) (x << (((n) % 8) * 4))
 
 static void pins_init(void)
@@ -84,9 +83,9 @@ static void pins_init(void)
 	STM32_GPIO_AFRH(GPIO_A) = AFx(9, 1) | AFx(10, 1);
 	STM32_GPIO_OTYPER(GPIO_A) = ODR(4);
 	STM32_GPIO_OSPEEDR(GPIO_A) = HISPEED(5) | HISPEED(6) | HISPEED(7);
-	STM32_GPIO_MODER(GPIO_A) = OUT(0) | ANALOG(1) | ANALOG(2) | ANALOG(3)
-				 | OUT(4) | AF(5) /*| AF(6)*/ | AF(7) | AF(9)
-				 | AF(10) | OUT(13) | OUT(14);
+	STM32_GPIO_MODER(GPIO_A) = OUT(0) | ANALOG(1) | ANALOG(2) | ANALOG(3) |
+				   OUT(4) | AF(5) /*| AF(6)*/ | AF(7) | AF(9) |
+				   AF(10) | OUT(13) | OUT(14);
 	/* set PF0 / PF1 as output */
 	STM32_GPIO_ODR(GPIO_F) = 0;
 	STM32_GPIO_MODER(GPIO_F) = OUT(0) | OUT(1);
@@ -108,7 +107,8 @@ static void adc_init(void)
 			;
 	}
 	/* Single conversion, right aligned, 12-bit */
-	STM32_ADC_CFGR1 = BIT(12); /* BIT(15) => AUTOOFF */;
+	STM32_ADC_CFGR1 = BIT(12); /* BIT(15) => AUTOOFF */
+	;
 	/* clock is ADCCLK (ADEN must be off when writing this reg) */
 	STM32_ADC_CFGR2 = 0;
 	/* Sampling time : 71.5 ADC clock cycles, about 5us */
@@ -133,8 +133,8 @@ static void uart_init(void)
 	STM32_USART_BRR(UARTN_BASE) =
 		DIV_ROUND_NEAREST(CPU_CLOCK, CONFIG_UART_BAUD_RATE);
 	/* UART enabled, 8 Data bits, oversampling x16, no parity */
-	STM32_USART_CR1(UARTN_BASE) =
-		STM32_USART_CR1_UE | STM32_USART_CR1_TE | STM32_USART_CR1_RE;
+	STM32_USART_CR1(UARTN_BASE) = STM32_USART_CR1_UE | STM32_USART_CR1_TE |
+				      STM32_USART_CR1_RE;
 	/* 1 stop bit, no fancy stuff */
 	STM32_USART_CR2(UARTN_BASE) = 0x0000;
 	/* DMA disabled, special modes disabled, error interrupt disabled */
@@ -201,7 +201,7 @@ static int watchdog_ain_id, watchdog_ain_high, watchdog_ain_low;
 static int adc_enable_last_watchdog(void)
 {
 	return adc_enable_watchdog(watchdog_ain_id, watchdog_ain_high,
-			    watchdog_ain_low);
+				   watchdog_ain_low);
 }
 
 static inline int adc_watchdog_enabled(void)
@@ -249,8 +249,7 @@ int adc_enable_watchdog(int ch, int high, int low)
 	/* Clear flags */
 	STM32_ADC_ISR = 0x8e;
 	/* Set Watchdog enable bit on a single channel / continuous mode */
-	STM32_ADC_CFGR1 = (ch << 26) | BIT(23) | BIT(22)
-			|  BIT(13) | BIT(12);
+	STM32_ADC_CFGR1 = (ch << 26) | BIT(23) | BIT(22) | BIT(13) | BIT(12);
 	/* Enable watchdog interrupt */
 	STM32_ADC_IER = BIT(7);
 	/* Start continuous conversion */
@@ -290,25 +289,26 @@ int adc_disable_watchdog(void)
 	(FLASH_TIMEOUT_US * (CPU_CLOCK / SECOND) / CYCLE_PER_FLASH_LOOP)
 
 /* Flash unlocking keys */
-#define KEY1    0x45670123
-#define KEY2    0xCDEF89AB
+#define KEY1 0x45670123
+#define KEY2 0xCDEF89AB
 
 /* Lock bits for FLASH_CR register */
-#define PG       BIT(0)
-#define PER      BIT(1)
-#define OPTPG    BIT(4)
-#define OPTER    BIT(5)
-#define STRT     BIT(6)
-#define CR_LOCK  BIT(7)
-#define OPTWRE   BIT(9)
-
-int flash_physical_write(int offset, int size, const char *data)
+#define PG BIT(0)
+#define PER BIT(1)
+#define OPTPG BIT(4)
+#define OPTER BIT(5)
+#define STRT BIT(6)
+#define CR_LOCK BIT(7)
+#define OPTWRE BIT(9)
+
+int crec_flash_physical_write(int offset, int size, const char *data)
 {
 	uint16_t *address = (uint16_t *)(CONFIG_PROGRAM_MEMORY_BASE + offset);
 	int res = EC_SUCCESS;
 	int i;
 
-	if ((uint32_t)address > CONFIG_PROGRAM_MEMORY_BASE + CONFIG_FLASH_SIZE)
+	if ((uint32_t)address >
+	    CONFIG_PROGRAM_MEMORY_BASE + CONFIG_FLASH_SIZE_BYTES)
 		return EC_ERROR_INVAL;
 
 	/* unlock CR if needed */
@@ -353,7 +353,7 @@ int flash_physical_write(int offset, int size, const char *data)
 	return res;
 }
 
-int flash_physical_erase(int offset, int size)
+int crec_flash_physical_erase(int offset, int size)
 {
 	int res = EC_SUCCESS;
 
@@ -369,14 +369,13 @@ int flash_physical_erase(int offset, int size)
 	STM32_FLASH_CR |= PER;
 
 	for (; size > 0; size -= CONFIG_FLASH_ERASE_SIZE,
-	     offset += CONFIG_FLASH_ERASE_SIZE) {
+			 offset += CONFIG_FLASH_ERASE_SIZE) {
 		int i;
 		/* select page to erase */
 		STM32_FLASH_AR = CONFIG_PROGRAM_MEMORY_BASE + offset;
 		/* set STRT bit : start erase */
 		STM32_FLASH_CR |= STRT;
 
-
 		/* Wait for erase to complete */
 		for (i = 0; (STM32_FLASH_SR & 1) && (i < FLASH_TIMEOUT_LOOP);
 		     i++)
@@ -434,7 +433,6 @@ static void unlock_erase_optb(void)
 	STM32_FLASH_CR = OPTWRE;
 }
 
-
 static void write_optb(int byte, uint8_t value)
 {
 	volatile int16_t *hword = (uint16_t *)(STM32_OPTB_BASE + byte);
@@ -464,7 +462,7 @@ void flash_physical_permanent_protect(void)
 	/* Set RDP to level 1 to prevent disabling the protection */
 	write_optb(0, 0x11);
 	/* Reset by using OBL_LAUNCH to take changes into account */
-	asm volatile("cpsid i");
+	interrupt_disable();
 	STM32_FLASH_CR |= FLASH_CR_OBL_LAUNCH;
 	/* Spin and wait for reboot; should never return */
 	while (1)
@@ -475,6 +473,6 @@ int flash_physical_is_permanently_protected(void)
 {
 	/* if RDP is still at level 0, the flash protection is not in place */
 	return (STM32_FLASH_OBR & STM32_FLASH_OBR_RDP_MASK) &&
-		/* the low 16KB (RO partition) are write-protected */
-		!(STM32_FLASH_WRPR & 0xF);
+	       /* the low 16KB (RO partition) are write-protected */
+	       !(STM32_FLASH_WRPR & 0xF);
 }
diff --git a/board/zinger/runtime.c b/board/zinger/runtime.c
index da1a11a7ee..25d09d797c 100644
--- a/board/zinger/runtime.c
+++ b/board/zinger/runtime.c
@@ -1,9 +1,10 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 /* tiny substitute of the runtime layer */
 
+#include "atomic.h"
 #include "chip/stm32/clock-f.h"
 #include "clock.h"
 #include "common.h"
@@ -16,7 +17,7 @@
 #include "util.h"
 
 volatile uint32_t last_event;
-uint32_t sleep_mask;
+atomic_t sleep_mask;
 
 /* High word of the 64-bit timestamp counter  */
 static volatile uint32_t clksrc_high;
@@ -35,9 +36,9 @@ void force_time(timestamp_t ts)
 	STM32_TIM32_CNT(2) = ts.le.lo;
 }
 
-void udelay(unsigned us)
+void udelay(unsigned int us)
 {
-	unsigned t0 = STM32_TIM32_CNT(2);
+	unsigned int t0 = STM32_TIM32_CNT(2);
 	while ((STM32_TIM32_CNT(2) - t0) < us)
 		;
 }
@@ -67,14 +68,12 @@ void interrupt_enable(void)
 	asm("cpsie i");
 }
 
-uint32_t task_set_event(task_id_t tskid, uint32_t event, int wait)
+void task_set_event(task_id_t tskid, uint32_t event)
 {
 	last_event = event;
-
-	return 0;
 }
 
-void tim2_interrupt(void)
+static void tim2_interrupt(void)
 {
 	uint32_t stat = STM32_TIM_SR(2);
 
@@ -107,7 +106,7 @@ static void zinger_config_hispeed_clock(void)
 	STM32_RCC_CR |= BIT(24);
 	/* Wait for PLL to be ready */
 	while (!(STM32_RCC_CR & BIT(25)))
-			;
+		;
 
 	/* switch SYSCLK to PLL */
 	STM32_RCC_CFGR = 0x00288002;
@@ -136,7 +135,7 @@ void runtime_init(void)
  * SET_RTC_MATCH_DELAY: max time to set RTC match alarm. if we set the alarm
  * in the past, it will never wake up and cause a watchdog.
  */
-#define STOP_MODE_LATENCY 300   /* us */
+#define STOP_MODE_LATENCY 300 /* us */
 #define SET_RTC_MATCH_DELAY 200 /* us */
 #define MAX_LATENCY (STOP_MODE_LATENCY + SET_RTC_MATCH_DELAY)
 
@@ -148,7 +147,7 @@ uint32_t task_wait_event(int timeout_us)
 
 	t1.val = get_time().val + timeout_us;
 
-	asm volatile("cpsid i");
+	interrupt_disable();
 	/* the event already happened */
 	if (last_event || !timeout_us) {
 		evt = last_event;
@@ -162,10 +161,10 @@ uint32_t task_wait_event(int timeout_us)
 	while (1) {
 		/* set timeout on timer */
 		if (timeout_us < 0) {
-			asm volatile ("wfi");
+			asm volatile("wfi");
 		} else if (timeout_us <= MAX_LATENCY ||
-			  t1.le.lo - timeout_us > t1.le.lo + MAX_LATENCY ||
-			  !DEEP_SLEEP_ALLOWED) {
+			   t1.le.lo - timeout_us > t1.le.lo + MAX_LATENCY ||
+			   !DEEP_SLEEP_ALLOWED) {
 			STM32_TIM32_CCR1(2) = STM32_TIM32_CNT(2) + timeout_us;
 			STM32_TIM_DIER(2) = 3; /*  match interrupt and UIE */
 
@@ -178,8 +177,8 @@ uint32_t task_wait_event(int timeout_us)
 			/* set deep sleep bit */
 			CPU_SCB_SYSCTRL |= 0x4;
 
-			set_rtc_alarm(0, timeout_us - STOP_MODE_LATENCY,
-				      &rtc0, 0);
+			set_rtc_alarm(0, timeout_us - STOP_MODE_LATENCY, &rtc0,
+				      0);
 
 			asm volatile("wfi");
 
@@ -195,7 +194,7 @@ uint32_t task_wait_event(int timeout_us)
 
 		asm volatile("cpsie i ; isb");
 		/* note: interrupt that woke us up will run here */
-		asm volatile("cpsid i");
+		interrupt_disable();
 
 		t0 = get_time();
 		/* check for timeout if timeout was set */
@@ -229,16 +228,15 @@ uint32_t task_wait_event_mask(uint32_t event_mask, int timeout_us)
 
 	/* Restore any pending events not in the event_mask */
 	if (evt & ~event_mask)
-		task_set_event(0, evt & ~event_mask, 0);
+		task_set_event(0, evt & ~event_mask);
 
 	return evt & event_mask;
 }
 
-noreturn
-void __keep cpu_reset(void)
+noreturn void __keep cpu_reset(void)
 {
 	/* Disable interrupts */
-	asm volatile("cpsid i");
+	interrupt_disable();
 	/* reboot the CPU */
 	CPU_NVIC_APINT = 0x05fa0004;
 	/* Spin and wait for reboot; should never return */
@@ -258,17 +256,18 @@ void system_reset(int flags)
 void exception_panic(void) __attribute__((naked));
 void exception_panic(void)
 {
-#ifdef CONFIG_DEBUG_PRINTF
 	asm volatile(
+#ifdef CONFIG_DEBUG_PRINTF
 		"mov r0, %0\n"
 		/* TODO: Should this be SP_process instead of SP_main? */
 		"mov r3, sp\n"
 		"ldr r1, [r3, #6*4]\n" /* retrieve exception PC */
 		"ldr r2, [r3, #5*4]\n" /* retrieve exception LR */
 		"bl debug_printf\n"
-	: : "r"("PANIC PC=%08x LR=%08x\n\n"));
 #endif
-	cpu_reset();
+		"bl cpu_reset\n"
+		:
+		: "r"("PANIC PC=%08x LR=%08x\n\n"));
 }
 
 void panic_reboot(void)
@@ -287,7 +286,9 @@ enum ec_image system_get_image_copy(void)
 
 /* --- stubs --- */
 void __hw_timer_enable_clock(int n, int enable)
-{ /* Done in hardware init */ }
+{ /* Done in hardware init */
+}
 
-void usleep(unsigned us)
-{ /* Used only as a workaround */ }
+void usleep(unsigned int us)
+{ /* Used only as a workaround */
+}
diff --git a/board/zinger/usb_pd_config.h b/board/zinger/usb_pd_config.h
index d0797b3d80..c3d86e2c2b 100644
--- a/board/zinger/usb_pd_config.h
+++ b/board/zinger/usb_pd_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,7 +10,7 @@
 
 /* Timer selection for baseband PD communication */
 #define TIM_CLOCK_PD_TX_C0 14
-#define TIM_CLOCK_PD_RX_C0  3
+#define TIM_CLOCK_PD_RX_C0 3
 
 #define TIM_CLOCK_PD_TX(p) TIM_CLOCK_PD_TX_C0
 #define TIM_CLOCK_PD_RX(p) TIM_CLOCK_PD_RX_C0
@@ -46,7 +46,7 @@ static inline void spi_enable_clock(int port)
 #define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
 #define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
 /* connect TIM3 CH1 to TIM3_CH2 input */
-#define TIM_CCR_CS  2
+#define TIM_CCR_CS 2
 #define EXTI_COMP_MASK(p) BIT(7)
 #define IRQ_COMP STM32_IRQ_EXTI4_15
 /* the RX is inverted, triggers on rising edge */
@@ -72,7 +72,7 @@ static inline void pd_tx_spi_reset(int port)
 static inline void pd_tx_enable(int port, int polarity)
 {
 	/* Drive SPI MISO on PA6 by putting it in AF mode  */
-	STM32_GPIO_MODER(GPIO_A) |= 0x2 << (2*6);
+	STM32_GPIO_MODER(GPIO_A) |= 0x2 << (2 * 6);
 	/* Drive TX GND on PA4 */
 	STM32_GPIO_BSRR(GPIO_A) = 1 << (4 + 16 /* Reset */);
 }
@@ -83,7 +83,7 @@ static inline void pd_tx_disable(int port, int polarity)
 	/* Put TX GND (PA4) in Hi-Z state */
 	STM32_GPIO_BSRR(GPIO_A) = BIT(4) /* Set */;
 	/* Put SPI MISO (PA6) in Hi-Z by putting it in input mode  */
-	STM32_GPIO_MODER(GPIO_A) &= ~(0x3 << (2*6));
+	STM32_GPIO_MODER(GPIO_A) &= ~(0x3 << (2 * 6));
 }
 
 /* we know the plug polarity, do the right configuration */
@@ -98,7 +98,9 @@ static inline void pd_tx_init(void)
 	/* Already done in hardware_init() */
 }
 
-static inline void pd_config_init(int port, uint8_t power_role) {}
+static inline void pd_config_init(int port, uint8_t power_role)
+{
+}
 
 static inline int pd_adc_read(int port, int cc)
 {
diff --git a/board/zinger/usb_pd_pdo.c b/board/zinger/usb_pd_pdo.c
new file mode 100644
index 0000000000..36be87bd78
--- /dev/null
+++ b/board/zinger/usb_pd_pdo.c
@@ -0,0 +1,17 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "compile_time_macros.h"
+#include "usb_pd.h"
+#include "usb_pd_pdo.h"
+
+/* Power Delivery Objects */
+const uint32_t pd_src_pdo[] = {
+	[PDO_IDX_5V] = PDO_FIXED(5000, RATED_CURRENT, PDO_FIXED_FLAGS),
+	[PDO_IDX_12V] = PDO_FIXED(12000, RATED_CURRENT, PDO_FIXED_FLAGS),
+	[PDO_IDX_20V] = PDO_FIXED(20000, RATED_CURRENT, PDO_FIXED_FLAGS),
+};
+const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
+BUILD_ASSERT(ARRAY_SIZE(pd_src_pdo) == PDO_IDX_COUNT);
diff --git a/board/zinger/usb_pd_pdo.h b/board/zinger/usb_pd_pdo.h
new file mode 100644
index 0000000000..45f6668077
--- /dev/null
+++ b/board/zinger/usb_pd_pdo.h
@@ -0,0 +1,30 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_BOARD_ZINGER_USB_PD_PDO_H
+#define __CROS_EC_BOARD_ZINGER_USB_PD_PDO_H
+
+/* Max current */
+#if defined(BOARD_ZINGER)
+#define RATED_CURRENT 3000
+#elif defined(BOARD_MINIMUFFIN)
+#define RATED_CURRENT 2250
+#endif
+
+/* Voltage indexes for the PDOs */
+enum volt_idx {
+	PDO_IDX_5V = 0,
+	PDO_IDX_12V = 1,
+	PDO_IDX_20V = 2,
+
+	PDO_IDX_COUNT
+};
+
+#define PDO_FIXED_FLAGS (PDO_FIXED_UNCONSTRAINED | PDO_FIXED_DATA_SWAP)
+
+extern const uint32_t pd_src_pdo[3];
+extern const int pd_src_pdo_cnt;
+
+#endif /* __CROS_EC_BOARD_ZINGER_USB_PD_PDO_H */
diff --git a/board/zinger/usb_pd_policy.c b/board/zinger/usb_pd_policy.c
index f47789e063..157fda5ab4 100644
--- a/board/zinger/usb_pd_policy.c
+++ b/board/zinger/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,25 +9,27 @@
 #include "debug_printf.h"
 #include "ec_commands.h"
 #include "hooks.h"
+#include "printf.h"
 #include "registers.h"
 #include "system.h"
 #include "task.h"
 #include "timer.h"
-#include "util.h"
 #include "usb_pd.h"
+#include "usb_pd_pdo.h"
+#include "util.h"
 
 /* ------------------------- Power supply control ------------------------ */
 
 /* GPIO level setting helpers through BSRR register */
-#define GPIO_SET(n)   (1 << (n))
+#define GPIO_SET(n) (1 << (n))
 #define GPIO_RESET(n) (1 << ((n) + 16))
 
 /* Output voltage selection */
 enum volt {
-	VO_5V  = GPIO_RESET(13) | GPIO_RESET(14),
-	VO_12V = GPIO_SET(13)   | GPIO_RESET(14),
+	VO_5V = GPIO_RESET(13) | GPIO_RESET(14),
+	VO_12V = GPIO_SET(13) | GPIO_RESET(14),
 	VO_13V = GPIO_RESET(13) | GPIO_SET(14),
-	VO_20V = GPIO_SET(13)   | GPIO_SET(14),
+	VO_20V = GPIO_SET(13) | GPIO_SET(14),
 };
 
 static inline void set_output_voltage(enum volt v)
@@ -72,33 +74,27 @@ static timestamp_t fault_deadline;
 /* ADC in 12-bit mode */
 #define ADC_SCALE BIT(12)
 /* ADC power supply : VDDA = 3.3V */
-#define VDDA_MV   3300
+#define VDDA_MV 3300
 /* Current sense resistor : 5 milliOhm */
-#define R_SENSE   5
+#define R_SENSE 5
 /* VBUS voltage is measured through 10k / 100k voltage divider = /11 */
-#define VOLT_DIV  ((10+100)/10)
+#define VOLT_DIV ((10 + 100) / 10)
 /* The current sensing op-amp has a x100 gain */
 #define CURR_GAIN 100
 /* convert VBUS voltage in raw ADC value */
-#define VBUS_MV(mv) ((mv)*ADC_SCALE/VOLT_DIV/VDDA_MV)
+#define VBUS_MV(mv) ((mv)*ADC_SCALE / VOLT_DIV / VDDA_MV)
 /* convert VBUS current in raw ADC value */
-#define VBUS_MA(ma) ((ma)*ADC_SCALE*R_SENSE/1000*CURR_GAIN/VDDA_MV)
+#define VBUS_MA(ma) ((ma)*ADC_SCALE * R_SENSE / 1000 * CURR_GAIN / VDDA_MV)
 /* convert raw ADC value to mA */
-#define ADC_TO_CURR_MA(vbus) ((vbus)*1000/(ADC_SCALE*R_SENSE)*VDDA_MV/CURR_GAIN)
+#define ADC_TO_CURR_MA(vbus) \
+	((vbus)*1000 / (ADC_SCALE * R_SENSE) * VDDA_MV / CURR_GAIN)
 /* convert raw ADC value to mV */
-#define ADC_TO_VOLT_MV(vbus) ((vbus)*VOLT_DIV*VDDA_MV/ADC_SCALE)
-
-/* Max current */
-#if defined(BOARD_ZINGER)
-#define RATED_CURRENT 3000
-#elif defined(BOARD_MINIMUFFIN)
-#define RATED_CURRENT 2250
-#endif
+#define ADC_TO_VOLT_MV(vbus) ((vbus)*VOLT_DIV * VDDA_MV / ADC_SCALE)
 
 /* Max current : 20% over rated current */
-#define MAX_CURRENT VBUS_MA(RATED_CURRENT * 6/5)
+#define MAX_CURRENT VBUS_MA(RATED_CURRENT * 6 / 5)
 /* Fast short circuit protection : 50% over rated current */
-#define MAX_CURRENT_FAST VBUS_MA(RATED_CURRENT * 3/2)
+#define MAX_CURRENT_FAST VBUS_MA(RATED_CURRENT * 3 / 2)
 /* reset over-current after 1 second */
 #define OCP_TIMEOUT SECOND
 
@@ -106,19 +102,19 @@ static timestamp_t fault_deadline;
 #define SINK_IDLE_CURRENT VBUS_MA(500 /* mA */)
 
 /* Under-voltage limit is 0.8x Vnom */
-#define UVP_MV(mv)  VBUS_MV((mv) * 8 / 10)
+#define UVP_MV(mv) VBUS_MV((mv)*8 / 10)
 /* Over-voltage limit is 1.2x Vnom */
-#define OVP_MV(mv)  VBUS_MV((mv) * 12 / 10)
+#define OVP_MV(mv) VBUS_MV((mv)*12 / 10)
 /* Over-voltage recovery threshold is 1.1x Vnom */
-#define OVP_REC_MV(mv)  VBUS_MV((mv) * 11 / 10)
+#define OVP_REC_MV(mv) VBUS_MV((mv)*11 / 10)
 
 /* Maximum discharging delay */
-#define DISCHARGE_TIMEOUT (275*MSEC)
+#define DISCHARGE_TIMEOUT (275 * MSEC)
 /* Voltage overshoot below the OVP threshold for discharging to avoid OVP */
 #define DISCHARGE_OVERSHOOT_MV VBUS_MV(200)
 
 /* Time to wait after last RX edge interrupt before allowing deep sleep */
-#define PD_RX_SLEEP_TIMEOUT (100*MSEC)
+#define PD_RX_SLEEP_TIMEOUT (100 * MSEC)
 
 /* ----- output voltage discharging ----- */
 
@@ -154,39 +150,18 @@ static void discharge_voltage(int target_volt)
 
 /* ----------------------- USB Power delivery policy ---------------------- */
 
-#define PDO_FIXED_FLAGS (PDO_FIXED_UNCONSTRAINED | PDO_FIXED_DATA_SWAP)
-
-/* Voltage indexes for the PDOs */
-enum volt_idx {
-	PDO_IDX_5V  = 0,
-	PDO_IDX_12V = 1,
-	PDO_IDX_20V = 2,
-
-	PDO_IDX_COUNT
-};
-
-/* Power Delivery Objects */
-const uint32_t pd_src_pdo[] = {
-	[PDO_IDX_5V]  = PDO_FIXED(5000,  RATED_CURRENT, PDO_FIXED_FLAGS),
-	[PDO_IDX_12V] = PDO_FIXED(12000, RATED_CURRENT, PDO_FIXED_FLAGS),
-	[PDO_IDX_20V] = PDO_FIXED(20000, RATED_CURRENT, PDO_FIXED_FLAGS),
-};
-const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
-BUILD_ASSERT(ARRAY_SIZE(pd_src_pdo) == PDO_IDX_COUNT);
-
 /* PDO voltages (should match the table above) */
 static const struct {
 	enum volt select; /* GPIO configuration to select the voltage */
-	int       uvp;    /* under-voltage limit in mV */
-	int       ovp;    /* over-voltage limit in mV */
-	int       ovp_rec;/* over-voltage recovery threshold in mV */
+	int uvp; /* under-voltage limit in mV */
+	int ovp; /* over-voltage limit in mV */
+	int ovp_rec; /* over-voltage recovery threshold in mV */
 } voltages[ARRAY_SIZE(pd_src_pdo)] = {
-	[PDO_IDX_5V]  = {VO_5V,  UVP_MV(5000),  OVP_MV(5000),
-						OVP_REC_MV(5000)},
-	[PDO_IDX_12V] = {VO_12V, UVP_MV(12000), OVP_MV(12000),
-						OVP_REC_MV(12000)},
-	[PDO_IDX_20V] = {VO_20V, UVP_MV(20000), OVP_MV(20000),
-						OVP_REC_MV(20000)},
+	[PDO_IDX_5V] = { VO_5V, UVP_MV(5000), OVP_MV(5000), OVP_REC_MV(5000) },
+	[PDO_IDX_12V] = { VO_12V, UVP_MV(12000), OVP_MV(12000),
+			  OVP_REC_MV(12000) },
+	[PDO_IDX_20V] = { VO_20V, UVP_MV(20000), OVP_MV(20000),
+			  OVP_REC_MV(20000) },
 };
 
 /* current and previous selected PDO entry */
@@ -225,8 +200,8 @@ void pd_transition_voltage(int idx)
 			/* Make sure discharging is disabled */
 			discharge_disable();
 			/* Enable over-current monitoring */
-			adc_enable_watchdog(ADC_CH_A_SENSE,
-					    MAX_CURRENT_FAST, 0);
+			adc_enable_watchdog(ADC_CH_A_SENSE, MAX_CURRENT_FAST,
+					    0);
 		}
 	}
 	set_output_voltage(voltages[volt_idx].select);
@@ -267,28 +242,22 @@ void pd_power_supply_reset(int port)
 	}
 }
 
-int pd_check_data_swap(int port,
-		       enum pd_data_role data_role)
+int pd_check_data_swap(int port, enum pd_data_role data_role)
 {
 	/* Allow data swap if we are a DFP, otherwise don't allow */
 	return (data_role == PD_ROLE_DFP) ? 1 : 0;
 }
 
-void pd_execute_data_swap(int port,
-			  enum pd_data_role data_role)
+void pd_execute_data_swap(int port, enum pd_data_role data_role)
 {
 	/* Do nothing */
 }
 
-void pd_check_pr_role(int port,
-		      enum pd_power_role pr_role,
-		      int flags)
+void pd_check_pr_role(int port, enum pd_power_role pr_role, int flags)
 {
 }
 
-void pd_check_dr_role(int port,
-		      enum pd_data_role dr_role,
-		      int flags)
+void pd_check_dr_role(int port, enum pd_data_role dr_role, int flags)
 {
 	/* If DFP, try to switch to UFP */
 	if ((flags & PD_FLAGS_PARTNER_DR_DATA) && dr_role == PD_ROLE_DFP)
@@ -315,7 +284,7 @@ int pd_board_checks(void)
 			__enter_hibernate(0, 0);
 		}
 	} else {
-		hib_to.val = get_time().val + 60*SECOND;
+		hib_to.val = get_time().val + 60 * SECOND;
 		hib_to_ready = 1;
 	}
 #endif
@@ -345,8 +314,8 @@ int pd_board_checks(void)
 		/* trigger the slow OCP iff all 4 samples are above the max */
 		if (count == 3) {
 			debug_printf("OCP %d mA\n",
-			  vbus_amp * VDDA_MV / CURR_GAIN * 1000
-				   / R_SENSE / ADC_SCALE);
+				     vbus_amp * VDDA_MV / CURR_GAIN * 1000 /
+					     R_SENSE / ADC_SCALE);
 			pd_log_event(PD_EVENT_PS_FAULT, 0, PS_FAULT_OCP, NULL);
 			fault = FAULT_OCP;
 			/* reset over-current after 1 second */
@@ -375,8 +344,7 @@ int pd_board_checks(void)
 	if ((output_is_enabled() && (vbus_volt > voltages[ovp_idx].ovp)) ||
 	    (fault && (vbus_volt > voltages[ovp_idx].ovp_rec))) {
 		if (!fault) {
-			debug_printf("OVP %d mV\n",
-				     ADC_TO_VOLT_MV(vbus_volt));
+			debug_printf("OVP %d mV\n", ADC_TO_VOLT_MV(vbus_volt));
 			pd_log_event(PD_EVENT_PS_FAULT, 0, PS_FAULT_OVP, NULL);
 		}
 		fault = FAULT_OVP;
@@ -387,7 +355,7 @@ int pd_board_checks(void)
 
 	/* the discharge did not work properly */
 	if (discharge_is_enabled() &&
-		(get_time().val > discharge_deadline.val)) {
+	    (get_time().val > discharge_deadline.val)) {
 		/* ensure we always finish a 2-step discharge */
 		volt_idx = discharge_volt_idx;
 		set_output_voltage(voltages[volt_idx].select);
@@ -395,8 +363,7 @@ int pd_board_checks(void)
 		discharge_disable();
 		/* enable over-current monitoring */
 		adc_enable_watchdog(ADC_CH_A_SENSE, MAX_CURRENT_FAST, 0);
-		debug_printf("Disch FAIL %d mV\n",
-			     ADC_TO_VOLT_MV(vbus_volt));
+		debug_printf("Disch FAIL %d mV\n", ADC_TO_VOLT_MV(vbus_volt));
 		pd_log_event(PD_EVENT_PS_FAULT, 0, PS_FAULT_DISCH, NULL);
 		fault = FAULT_DISCHARGE;
 		/* reset it after 1 second */
@@ -416,10 +383,9 @@ int pd_board_checks(void)
 	}
 
 	return EC_SUCCESS;
-
 }
 
-void pd_adc_interrupt(void)
+static void pd_adc_interrupt(void)
 {
 	/* Clear flags */
 	STM32_ADC_ISR = 0x8e;
@@ -433,10 +399,10 @@ void pd_adc_interrupt(void)
 		} else { /* discharge complete */
 			discharge_disable();
 			/* enable over-current monitoring */
-			adc_enable_watchdog(ADC_CH_A_SENSE,
-					    MAX_CURRENT_FAST, 0);
+			adc_enable_watchdog(ADC_CH_A_SENSE, MAX_CURRENT_FAST,
+					    0);
 		}
-	} else {/* Over-current detection */
+	} else { /* Over-current detection */
 		/* cut the power output */
 		pd_power_supply_reset(0);
 		/* record a special fault */
@@ -479,9 +445,7 @@ static int svdm_response_svids(int port, uint32_t *payload)
 #define MODE_CNT 1
 #define OPOS 1
 
-const uint32_t vdo_dp_mode[MODE_CNT] =  {
-	VDO_MODE_GOOGLE(MODE_GOOGLE_FU)
-};
+const uint32_t vdo_dp_mode[MODE_CNT] = { VDO_MODE_GOOGLE(MODE_GOOGLE_FU) };
 
 static int svdm_response_modes(int port, uint32_t *payload)
 {
@@ -525,16 +489,17 @@ const struct svdm_response svdm_rsp = {
 };
 
 __override int pd_custom_vdm(int port, int cnt, uint32_t *payload,
-		  uint32_t **rpayload)
+			     uint32_t **rpayload)
 {
 	int cmd = PD_VDO_CMD(payload[0]);
 	int rsize;
+	char ts_str[PRINTF_TIMESTAMP_BUF_SIZE];
 
 	if (PD_VDO_VID(payload[0]) != USB_VID_GOOGLE || !gfu_mode)
 		return 0;
 
-	debug_printf("%pT] VDM/%d [%d] %08x\n",
-		     PRINTF_TIMESTAMP_NOW, cnt, cmd, payload[0]);
+	snprintf_timestamp_now(ts_str, sizeof(ts_str));
+	debug_printf("%s] VDM/%d [%d] %08x\n", ts_str, cnt, cmd, payload[0]);
 	*rpayload = payload;
 
 	rsize = pd_custom_flash_vdm(port, cnt, payload);
diff --git a/board/zinger/vif_override.xml b/board/zinger/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/zinger/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->
diff --git a/builtin/assert.h b/builtin/assert.h
index e58a450fa8..71a275bf23 100644
--- a/builtin/assert.h
+++ b/builtin/assert.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,33 +21,62 @@ extern "C" {
 #ifdef CONFIG_DEBUG_ASSERT_REBOOTS
 
 #ifdef CONFIG_DEBUG_ASSERT_BRIEF
-extern noreturn void panic_assert_fail(const char *fname, int linenum);
+#if defined(__cplusplus) && !defined(__clang__)
+[[noreturn]]
+#else
+noreturn
+#endif
+void panic_assert_fail(const char *fname, int linenum);
 #define ASSERT(cond)                                           \
 	do {                                                   \
 		if (!(cond))                                   \
 			panic_assert_fail(__FILE__, __LINE__); \
 	} while (0)
+
+#else /* !CONFIG_DEBUG_ASSERT_BRIEF */
+
+#if defined(__cplusplus) && !defined(__clang__)
+[[noreturn]]
 #else
-extern noreturn void panic_assert_fail(const char *msg, const char *func,
-			      const char *fname, int linenum);
+noreturn
+#endif
+void panic_assert_fail(const char *msg, const char *func,
+				const char *fname, int linenum);
 #define ASSERT(cond)                                                 \
 	do {                                                         \
 		if (!(cond))                                         \
 			panic_assert_fail(#cond, __func__, __FILE__, \
 					  __LINE__);                 \
 	} while (0)
-#endif
+#endif /* CONFIG_DEBUG_ASSERT_BRIEF */
+
+#else /* !CONFIG_DEBUG_ASSERT_REBOOTS */
+
+#if defined(__arm__)
+#define ARCH_SOFTWARE_BREAKPOINT __asm("bkpt")
+#elif defined(__nds32__)
+#define ARCH_SOFTWARE_BREAKPOINT __asm("break 0")
+#elif defined(__riscv)
+#define ARCH_SOFTWARE_BREAKPOINT __asm("ebreak")
+#elif defined(VIF_BUILD)
+/* The genvif utility compiles usb_pd_policy.c and needs an empty definition. */
+#define ARCH_SOFTWARE_BREAKPOINT
 #else
-#define ASSERT(cond)                     \
-	do {                             \
-		if (!(cond))             \
-			__asm("bkpt");   \
-		__builtin_unreachable(); \
-	} while (0)
+#error "CONFIG_DEBUG_ASSERT_REBOOTS must be defined on this architecture"
 #endif
-#else
+
+#define ASSERT(cond)                              \
+	do {                                      \
+		if (!(cond)) {                    \
+			ARCH_SOFTWARE_BREAKPOINT; \
+			__builtin_unreachable();  \
+		}                                 \
+	} while (0)
+#endif /* CONFIG_DEBUG_ASSERT_REBOOTS */
+
+#else /* !CONFIG_DEBUG_ASSERT */
 #define ASSERT(cond)
-#endif
+#endif /* CONFIG_DEBUG_ASSERT */
 
 /* This collides with cstdlib, so exclude it where cstdlib is supported. */
 #ifndef assert
diff --git a/builtin/build.mk b/builtin/build.mk
new file mode 100644
index 0000000000..6613bfec05
--- /dev/null
+++ b/builtin/build.mk
@@ -0,0 +1,6 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Build for EC's standard library implementation.
+builtin-y=stdlib.o
diff --git a/builtin/ctype.h b/builtin/ctype.h
new file mode 100644
index 0000000000..8844adca67
--- /dev/null
+++ b/builtin/ctype.h
@@ -0,0 +1,16 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_CTYPE_H__
+#define __CROS_EC_CTYPE_H__
+
+int isdigit(int c);
+int isspace(int c);
+int isalpha(int c);
+int isupper(int c);
+int isprint(int c);
+int tolower(int c);
+
+#endif /* __CROS_EC_CTYPE_H__ */
diff --git a/builtin/endian.h b/builtin/endian.h
index 8a50cb4815..0220836dca 100644
--- a/builtin/endian.h
+++ b/builtin/endian.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,7 +17,7 @@ extern "C" {
  * host byte order. Note that the code currently does not require functions
  * for converting little endian integers.
  */
-#if (__BYTE_ORDER__  == __ORDER_LITTLE_ENDIAN__)
+#if (__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__)
 
 static inline uint16_t be16toh(uint16_t in)
 {
@@ -36,10 +36,14 @@ static inline uint64_t be64toh(uint64_t in)
 #define htobe32 be32toh
 #define htobe64 be64toh
 
-#endif  /* __BYTE_ORDER__  == __ORDER_LITTLE_ENDIAN__ */
+#define htole16(x) (uint16_t)(x)
+#define htole32(x) (uint32_t)(x)
+#define htole64(x) (uint64_t)(x)
+
+#endif /* __BYTE_ORDER__  == __ORDER_LITTLE_ENDIAN__ */
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif  /* __EC_BUILTIN_ENDIAN_H */
+#endif /* __EC_BUILTIN_ENDIAN_H */
diff --git a/builtin/inttypes.h b/builtin/inttypes.h
index c442fbe499..eed80407ce 100644
--- a/builtin/inttypes.h
+++ b/builtin/inttypes.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,6 +6,8 @@
 #ifndef __CROS_EC_INTTYPES_H__
 #define __CROS_EC_INTTYPES_H__
 
+#include <stdint.h>
+
 #define PRIx64 "llx"
 #define PRId64 "lld"
 
diff --git a/builtin/limits.h b/builtin/limits.h
index 5cbfa3e6d1..0e185614ae 100644
--- a/builtin/limits.h
+++ b/builtin/limits.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,6 +6,8 @@
 #ifndef __CROS_EC_LIMITS_H_
 #define __CROS_EC_LIMITS_H_
 
+#define CHAR_BIT 8
+
 #define ULONG_MAX 0xffffffffu
 
 #endif /* __CROS_EC_LIMITS_H_ */
diff --git a/builtin/math.h b/builtin/math.h
new file mode 100644
index 0000000000..aa07a0286d
--- /dev/null
+++ b/builtin/math.h
@@ -0,0 +1,23 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_MATH_H__
+#define __CROS_EC_MATH_H__
+
+#include "fpu.h"
+
+#include <stdbool.h>
+
+static inline bool isnan(float a)
+{
+	return __builtin_isnan(a);
+}
+
+static inline bool isinf(float a)
+{
+	return __builtin_isinf(a);
+}
+
+#endif /* __CROS_EC_MATH_H__ */
diff --git a/builtin/stdarg.h b/builtin/stdarg.h
index 66ab940b16..5bf0aa8aa2 100644
--- a/builtin/stdarg.h
+++ b/builtin/stdarg.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,10 +13,10 @@
  */
 
 #ifdef __GNUC__
-#define va_start(v, l)		__builtin_va_start(v, l)
-#define va_end(v)		__builtin_va_end(v)
-#define va_arg(v, l)		__builtin_va_arg(v, l)
-typedef __builtin_va_list	va_list;
+#define va_start(v, l) __builtin_va_start(v, l)
+#define va_end(v) __builtin_va_end(v)
+#define va_arg(v, l) __builtin_va_arg(v, l)
+typedef __builtin_va_list va_list;
 #else
 #include_next <stdarg.h>
 #endif
diff --git a/builtin/stdbool.h b/builtin/stdbool.h
index 6e0f92dfc0..72d4927484 100644
--- a/builtin/stdbool.h
+++ b/builtin/stdbool.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,8 +6,8 @@
 #ifndef __CROS_EC_STDBOOL_H__
 #define __CROS_EC_STDBOOL_H__
 
-#define bool    _Bool
-#define true    1
-#define false   0
+#define bool _Bool
+#define true 1
+#define false 0
 
 #endif /* __CROS_EC_STDBOOL_H__ */
diff --git a/builtin/stddef.h b/builtin/stddef.h
index 69fb1982c7..9e69ba55ad 100644
--- a/builtin/stddef.h
+++ b/builtin/stddef.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,12 +11,6 @@
 #endif
 
 typedef __SIZE_TYPE__ size_t;
-/* There is a GCC macro for a size_t type, but not for a ssize_t type.
- * The following construct convinces GCC to make __SIZE_TYPE__ signed.
- */
-#define unsigned signed
-typedef __SIZE_TYPE__ ssize_t;
-#undef unsigned
 
 #ifndef NULL
 #define NULL ((void *)0)
@@ -36,7 +30,7 @@ typedef __WCHAR_TYPE__ wchar_t;
  * check for safety.
  */
 #ifndef offsetof
-#define offsetof(TYPE, MEMBER) __builtin_offsetof (TYPE, MEMBER)
+#define offsetof(TYPE, MEMBER) __builtin_offsetof(TYPE, MEMBER)
 #endif
 
 #endif /* __CROS_EC_STDDEF_H__ */
diff --git a/builtin/stdint.h b/builtin/stdint.h
index dedc9de475..5a107e1730 100644
--- a/builtin/stdint.h
+++ b/builtin/stdint.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,43 +6,43 @@
 #ifndef __CROS_EC_STDINT_H__
 #define __CROS_EC_STDINT_H__
 
-typedef unsigned char      uint8_t;
-typedef signed char        int8_t;
+typedef unsigned char uint8_t;
+typedef signed char int8_t;
 
-typedef unsigned short     uint16_t;
-typedef signed short       int16_t;
+typedef unsigned short uint16_t;
+typedef signed short int16_t;
 
-typedef unsigned int       uint32_t;
-typedef signed int         int32_t;
+typedef unsigned int uint32_t;
+typedef signed int int32_t;
 
 typedef unsigned long long uint64_t;
-typedef signed long long   int64_t;
+typedef signed long long int64_t;
 
-typedef unsigned int       uintptr_t;
-typedef int                intptr_t;
+typedef unsigned int uintptr_t;
+typedef int intptr_t;
 
 /* uint_leastX_t represents the smallest type available with at least X bits.
  * uint_fastX_t represents the fastest type available with at least X bits.
  */
-typedef uint8_t            uint_least8_t;
-typedef uint16_t           uint_least16_t;
-typedef uint32_t           uint_least32_t;
-typedef uint64_t           uint_least64_t;
-
-typedef int8_t             int_least8_t;
-typedef int16_t            int_least16_t;
-typedef int32_t            int_least32_t;
-typedef int64_t            int_least64_t;
-
-typedef uint8_t            uint_fast8_t;
-typedef uint16_t           uint_fast16_t;
-typedef uint32_t           uint_fast32_t;
-typedef uint64_t           uint_fast64_t;
-
-typedef int8_t             int_fast8_t;
-typedef int16_t            int_fast16_t;
-typedef int32_t            int_fast32_t;
-typedef int64_t            int_fast64_t;
+typedef uint8_t uint_least8_t;
+typedef uint16_t uint_least16_t;
+typedef uint32_t uint_least32_t;
+typedef uint64_t uint_least64_t;
+
+typedef int8_t int_least8_t;
+typedef int16_t int_least16_t;
+typedef int32_t int_least32_t;
+typedef int64_t int_least64_t;
+
+typedef uint8_t uint_fast8_t;
+typedef uint16_t uint_fast16_t;
+typedef uint32_t uint_fast32_t;
+typedef uint64_t uint_fast64_t;
+
+typedef int8_t int_fast8_t;
+typedef int16_t int_fast16_t;
+typedef int32_t int_fast32_t;
+typedef int64_t int_fast64_t;
 
 #ifndef UINT8_MAX
 #define UINT8_MAX (255U)
@@ -67,12 +67,15 @@ typedef int64_t            int_fast64_t;
 #ifndef INT32_MAX
 #define INT32_MAX (2147483647U)
 #endif
+#ifndef INT32_MIN
+#define INT32_MIN (-2147483648)
+#endif
 
 #ifndef UINT64_C
-#define UINT64_C(c)	c ## ULL
+#define UINT64_C(c) c##ULL
 #endif
 #ifndef INT64_C
-#define INT64_C(c)	c ## LL
+#define INT64_C(c) c##LL
 #endif
 
 #ifndef UINT64_MAX
@@ -81,5 +84,8 @@ typedef int64_t            int_fast64_t;
 #ifndef INT64_MAX
 #define INT64_MAX INT64_C(9223372036854775807)
 #endif
+#ifndef INT64_MIN
+#define INT64_MIN (INT64_C(-9223372036854775807) - 1)
+#endif
 
 #endif /* __CROS_EC_STDINT_H__ */
diff --git a/builtin/stdio.h b/builtin/stdio.h
new file mode 100644
index 0000000000..bd75c01f53
--- /dev/null
+++ b/builtin/stdio.h
@@ -0,0 +1,61 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_STDIO_H__
+#define __CROS_EC_STDIO_H__
+
+#include "common.h"
+
+#include <stdarg.h>
+#include <stddef.h>
+
+/**
+ * Print formatted outut to a string.
+ *
+ * Guarantees null-termination if size!=0.
+ *
+ * @param str           Destination string
+ * @param size          Size of destination in bytes
+ * @param format        Format string
+ * @return EC_SUCCESS, or EC_ERROR_OVERFLOW if the output was truncated.
+ */
+__attribute__((__format__(__printf__, 3, 4)))
+__warn_unused_result __stdlib_compat int
+crec_snprintf(char *str, size_t size, const char *format, ...);
+
+/**
+ * Print formatted output to a string.
+ *
+ * Guarantees null-termination if size!=0.
+ *
+ * @param str           Destination string
+ * @param size          Size of destination in bytes
+ * @param format        Format string
+ * @param args          Parameters
+ * @return The string length written to str, or a negative value on error.
+ *         The negative values can be -EC_ERROR_INVAL or -EC_ERROR_OVERFLOW.
+ */
+__warn_unused_result __stdlib_compat int
+crec_vsnprintf(char *str, size_t size, const char *format, va_list args);
+
+/*
+ * Create weak aliases to the crec_* printf functions. This lets us call the
+ * crec_* printf functions in tests that link the C standard library.
+ */
+
+/**
+ * Alias to crec_snprintf.
+ */
+__attribute__((__format__(__printf__, 3, 4)))
+__warn_unused_result __stdlib_compat int
+snprintf(char *str, size_t size, const char *format, ...);
+
+/**
+ * Alias to crec_vsnprintf.
+ */
+__warn_unused_result __stdlib_compat int
+vsnprintf(char *str, size_t size, const char *format, va_list args);
+
+#endif /* __CROS_EC_STDIO_H__ */
diff --git a/builtin/stdlib.c b/builtin/stdlib.c
new file mode 100644
index 0000000000..0d654f0395
--- /dev/null
+++ b/builtin/stdlib.c
@@ -0,0 +1,465 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Standard library utility functions for Chrome EC */
+
+#include "common.h"
+#include "console.h"
+#include "printf.h"
+#include "util.h"
+
+#include <stdio.h>
+
+/*
+ * The following macros are defined in stdlib.h in the C standard library, which
+ * conflict with the definitions in this file.
+ */
+#undef isspace
+#undef isdigit
+#undef isalpha
+#undef isupper
+#undef isprint
+#undef tolower
+
+/* Context for snprintf() */
+struct snprintf_context {
+	char *str;
+	int size;
+};
+
+/**
+ * Add a character to the string context.
+ *
+ * @param context	Context receiving character
+ * @param c		Character to add
+ * @return 0 if character added, 1 if character dropped because no space.
+ */
+static int snprintf_addchar(void *context, int c)
+{
+	struct snprintf_context *ctx = (struct snprintf_context *)context;
+
+	if (!ctx->size)
+		return 1;
+
+	*(ctx->str++) = c;
+	ctx->size--;
+	return 0;
+}
+
+int crec_vsnprintf(char *str, size_t size, const char *format, va_list args)
+{
+	struct snprintf_context ctx;
+	int rv;
+
+	if (!str || !format || size <= 0)
+		return -EC_ERROR_INVAL;
+
+	ctx.str = str;
+	ctx.size = size - 1; /* Reserve space for terminating '\0' */
+
+	rv = vfnprintf(snprintf_addchar, &ctx, format, args);
+
+	/* Terminate string */
+	*ctx.str = '\0';
+
+	return (rv == EC_SUCCESS) ? (ctx.str - str) : -rv;
+}
+#ifndef CONFIG_ZEPHYR
+int vsnprintf(char *str, size_t size, const char *format, va_list args)
+	__attribute__((weak, alias("crec_vsnprintf")));
+#endif /* CONFIG_ZEPHYR */
+
+int crec_snprintf(char *str, size_t size, const char *format, ...)
+{
+	va_list args;
+	int rv;
+
+	va_start(args, format);
+	rv = crec_vsnprintf(str, size, format, args);
+	va_end(args);
+
+	return rv;
+}
+#ifndef CONFIG_ZEPHYR
+int snprintf(char *str, size_t size, const char *format, ...)
+	__attribute__((weak, alias("crec_snprintf")));
+#endif /* CONFIG_ZEPHYR */
+
+/*
+ * TODO(b/237712836): Zephyr's libc should provide strcasecmp. For now we'll
+ * use the EC implementation.
+ */
+__stdlib_compat int strcasecmp(const char *s1, const char *s2)
+{
+	int diff;
+
+	do {
+		diff = tolower(*s1) - tolower(*s2);
+		if (diff)
+			return diff;
+	} while (*(s1++) && *(s2++));
+	return 0;
+}
+
+/*
+ * TODO(b/237712836): Remove this conditional once strcasecmp is added to
+ * Zephyr's libc.
+ */
+#ifndef CONFIG_ZEPHYR
+__stdlib_compat size_t strlen(const char *s)
+{
+	int len = 0;
+
+	while (*s++)
+		len++;
+
+	return len;
+}
+
+__stdlib_compat size_t strnlen(const char *s, size_t maxlen)
+{
+	size_t len = 0;
+
+	while (len < maxlen && *s) {
+		s++;
+		len++;
+	}
+	return len;
+}
+
+__stdlib_compat size_t strcspn(const char *s, const char *reject)
+{
+	size_t i;
+	size_t reject_len = strlen(reject);
+
+	for (i = 0; s[i] != 0; i++)
+		for (size_t j = 0; j < reject_len; j++)
+			if (s[i] == reject[j])
+				return i;
+	return i;
+}
+
+__stdlib_compat int isspace(int c)
+{
+	return c == ' ' || c == '\t' || c == '\r' || c == '\n';
+}
+
+__stdlib_compat int isdigit(int c)
+{
+	return c >= '0' && c <= '9';
+}
+
+__stdlib_compat int isalpha(int c)
+{
+	return (c >= 'A' && c <= 'Z') || (c >= 'a' && c <= 'z');
+}
+
+__stdlib_compat int isupper(int c)
+{
+	return c >= 'A' && c <= 'Z';
+}
+
+__stdlib_compat int isprint(int c)
+{
+	return c >= ' ' && c <= '~';
+}
+
+__stdlib_compat int tolower(int c)
+{
+	return c >= 'A' && c <= 'Z' ? c + 'a' - 'A' : c;
+}
+
+__stdlib_compat int strncasecmp(const char *s1, const char *s2, size_t size)
+{
+	int diff;
+
+	if (!size)
+		return 0;
+
+	do {
+		diff = tolower(*s1) - tolower(*s2);
+		if (diff)
+			return diff;
+	} while (*(s1++) && *(s2++) && --size);
+	return 0;
+}
+
+__stdlib_compat char *strstr(const char *s1, const char *s2)
+{
+	const char *p, *q, *r;
+	size_t len1 = strlen(s1);
+	size_t len2 = strlen(s2);
+
+	if (len1 == 0 || len2 == 0 || len1 < len2)
+		return NULL;
+
+	r = s1 + len1 - len2 + 1;
+	for (; s1 < r; s1++) {
+		if (*s1 == *s2) {
+			p = s1 + 1;
+			q = s2 + 1;
+			for (; q < s2 + len2;) {
+				if (*p++ != *q++)
+					break;
+			}
+			if (*q == '\0')
+				return (char *)s1;
+		}
+	}
+	return NULL;
+}
+
+__stdlib_compat unsigned long long int strtoull(const char *nptr, char **endptr,
+						int base)
+{
+	uint64_t result = 0;
+	int c = '\0';
+
+	while ((c = *nptr++) && isspace(c))
+		;
+
+	if (c == '+') {
+		c = *nptr++;
+	} else if (c == '-') {
+		if (endptr)
+			*endptr = (char *)nptr - 1;
+		return result;
+	}
+
+	base = find_base(base, &c, &nptr);
+
+	while (c) {
+		if (c >= '0' && c < '0' + MIN(base, 10))
+			result = result * base + (c - '0');
+		else if (c >= 'A' && c < 'A' + base - 10)
+			result = result * base + (c - 'A' + 10);
+		else if (c >= 'a' && c < 'a' + base - 10)
+			result = result * base + (c - 'a' + 10);
+		else
+			break;
+
+		c = *nptr++;
+	}
+
+	if (endptr)
+		*endptr = (char *)nptr - 1;
+	return result;
+}
+BUILD_ASSERT(sizeof(unsigned long long int) == sizeof(uint64_t));
+
+__stdlib_compat int atoi(const char *nptr)
+{
+	int result = 0;
+	int neg = 0;
+	char c = '\0';
+
+	while ((c = *nptr++) && isspace(c))
+		;
+
+	if (c == '-') {
+		neg = 1;
+		c = *nptr++;
+	}
+
+	while (isdigit(c)) {
+		result = result * 10 + (c - '0');
+		c = *nptr++;
+	}
+
+	return neg ? -result : result;
+}
+
+__keep __stdlib_compat int memcmp(const void *s1, const void *s2, size_t len)
+{
+	const char *sa = s1;
+	const char *sb = s2;
+	int diff = 0;
+
+	while (len-- > 0) {
+		diff = *(sa++) - *(sb++);
+		if (diff)
+			return diff;
+	}
+
+	return 0;
+}
+
+#if !(__has_feature(address_sanitizer) || __has_feature(memory_sanitizer))
+__keep __stdlib_compat void *memcpy(void *dest, const void *src, size_t len)
+{
+	char *d = (char *)dest;
+	const char *s = (const char *)src;
+	uint32_t *dw;
+	const uint32_t *sw;
+	char *head;
+	char *const tail = (char *)dest + len;
+	/* Set 'body' to the last word boundary */
+	uint32_t *const body = (uint32_t *)((uintptr_t)tail & ~3);
+
+	if (((uintptr_t)dest & 3) != ((uintptr_t)src & 3)) {
+		/* Misaligned. no body, no tail. */
+		head = tail;
+	} else {
+		/* Aligned */
+		if ((uintptr_t)tail < (((uintptr_t)d + 3) & ~3))
+			/* len is shorter than the first word boundary */
+			head = tail;
+		else
+			/* Set 'head' to the first word boundary */
+			head = (char *)(((uintptr_t)d + 3) & ~3);
+	}
+
+	/* Copy head */
+	while (d < head)
+		*(d++) = *(s++);
+
+	/* Copy body */
+	dw = (uint32_t *)d;
+	sw = (uint32_t *)s;
+	while (dw < body)
+		*(dw++) = *(sw++);
+
+	/* Copy tail */
+	d = (char *)dw;
+	s = (const char *)sw;
+	while (d < tail)
+		*(d++) = *(s++);
+
+	return dest;
+}
+#endif /* address_sanitizer || memory_sanitizer */
+
+#if !(__has_feature(address_sanitizer) || __has_feature(memory_sanitizer))
+__keep __stdlib_compat __visible void *memset(void *dest, int c, size_t len)
+{
+	char *d = (char *)dest;
+	uint32_t cccc;
+	uint32_t *dw;
+	char *head;
+	char *const tail = (char *)dest + len;
+	/* Set 'body' to the last word boundary */
+	uint32_t *const body = (uint32_t *)((uintptr_t)tail & ~3);
+
+	c &= 0xff; /* Clear upper bits before ORing below */
+	cccc = c | (c << 8) | (c << 16) | (c << 24);
+
+	if ((uintptr_t)tail < (((uintptr_t)d + 3) & ~3))
+		/* len is shorter than the first word boundary */
+		head = tail;
+	else
+		/* Set 'head' to the first word boundary */
+		head = (char *)(((uintptr_t)d + 3) & ~3);
+
+	/* Copy head */
+	while (d < head)
+		*(d++) = c;
+
+	/* Copy body */
+	dw = (uint32_t *)d;
+	while (dw < body)
+		*(dw++) = cccc;
+
+	/* Copy tail */
+	d = (char *)dw;
+	while (d < tail)
+		*(d++) = c;
+
+	return dest;
+}
+#endif /* address_sanitizer || memory_sanitizer */
+
+#if !(__has_feature(address_sanitizer) || __has_feature(memory_sanitizer))
+__keep __stdlib_compat void *memmove(void *dest, const void *src, size_t len)
+{
+	if ((uintptr_t)dest <= (uintptr_t)src ||
+	    (uintptr_t)dest >= (uintptr_t)src + len) {
+		/* Start of destination doesn't overlap source, so just use
+		 * memcpy().
+		 */
+		return memcpy(dest, src, len);
+	} else {
+		/* Need to copy from tail because there is overlap. */
+		char *d = (char *)dest + len;
+		const char *s = (const char *)src + len;
+		uint32_t *dw;
+		const uint32_t *sw;
+		char *head;
+		char *const tail = (char *)dest;
+		/* Set 'body' to the last word boundary */
+		uint32_t *const body = (uint32_t *)(((uintptr_t)tail + 3) & ~3);
+
+		if (((uintptr_t)dest & 3) != ((uintptr_t)src & 3)) {
+			/* Misaligned. no body, no tail. */
+			head = tail;
+		} else {
+			/* Aligned */
+			if ((uintptr_t)tail > ((uintptr_t)d & ~3))
+				/* Shorter than the first word boundary */
+				head = tail;
+			else
+				/* Set 'head' to the first word boundary */
+				head = (char *)((uintptr_t)d & ~3);
+		}
+
+		/* Copy head */
+		while (d > head)
+			*(--d) = *(--s);
+
+		/* Copy body */
+		dw = (uint32_t *)d;
+		sw = (uint32_t *)s;
+		while (dw > body)
+			*(--dw) = *(--sw);
+
+		/* Copy tail */
+		d = (char *)dw;
+		s = (const char *)sw;
+		while (d > tail)
+			*(--d) = *(--s);
+
+		return dest;
+	}
+}
+#endif /* address_sanitizer || memory_sanitizer */
+
+__stdlib_compat void *memchr(const void *buffer, int c, size_t n)
+{
+	char *current = (char *)buffer;
+	char *end = current + n;
+
+	while (current != end) {
+		if (*current == c)
+			return current;
+		current++;
+	}
+	return NULL;
+}
+
+__stdlib_compat char *strncpy(char *dest, const char *src, size_t n)
+{
+	char *d = dest;
+
+	while (n && *src) {
+		*d++ = *src++;
+		n--;
+	}
+	if (n)
+		*d = '\0';
+	return dest;
+}
+
+__stdlib_compat int strncmp(const char *s1, const char *s2, size_t n)
+{
+	while (n--) {
+		if (*s1 != *s2)
+			return *s1 - *s2;
+		if (!*s1)
+			break;
+		s1++;
+		s2++;
+	}
+	return 0;
+}
+#endif /* !CONFIG_ZEPHYR */
diff --git a/builtin/stdlib.h b/builtin/stdlib.h
new file mode 100644
index 0000000000..fcce72ee8d
--- /dev/null
+++ b/builtin/stdlib.h
@@ -0,0 +1,11 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_STDLIB_H__
+#define __CROS_EC_STDLIB_H__
+
+int atoi(const char *nptr);
+
+#endif /* __CROS_EC_STDLIB_H__ */
diff --git a/builtin/stdnoreturn.h b/builtin/stdnoreturn.h
index 659d3c540f..078a0d6698 100644
--- a/builtin/stdnoreturn.h
+++ b/builtin/stdnoreturn.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,7 +9,8 @@
 /*
  * Only defined for C: https://en.cppreference.com/w/c/language/_Noreturn
  *
- * C++ uses [[noreturn]]: https://en.cppreference.com/w/cpp/language/attributes/noreturn
+ * C++ uses [[noreturn]]:
+ * https://en.cppreference.com/w/cpp/language/attributes/noreturn
  */
 #ifndef __cplusplus
 #ifndef noreturn
diff --git a/builtin/string.h b/builtin/string.h
index 8c9a71bd75..742d75a478 100644
--- a/builtin/string.h
+++ b/builtin/string.h
@@ -1,12 +1,10 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-/* This header is only needed for CR50 compatibility */
-
-#ifndef __CROS_EC_STRINGS_H__
-#define __CROS_EC_STRINGS_H__
+#ifndef __CROS_EC_STRING_H__
+#define __CROS_EC_STRING_H__
 
 #include <stddef.h>
 
@@ -20,12 +18,28 @@ void *memmove(void *dest, const void *src, size_t n);
 void *memset(void *dest, int c, size_t len);
 void *memchr(const void *buffer, int c, size_t n);
 
+size_t strlen(const char *s);
 size_t strnlen(const char *s, size_t maxlen);
 char *strncpy(char *dest, const char *src, size_t n);
 int strncmp(const char *s1, const char *s2, size_t n);
 
+/**
+ * Calculates the length of the initial segment of s which consists
+ * entirely of bytes not in reject.
+ */
+size_t strcspn(const char *s, const char *reject);
+
+/**
+ * Find the first occurrence of the substring <s2> in the string <s1>
+ *
+ * @param s1	String where <s2> is searched.
+ * @param s2	Substring to be located in <s1>
+ * @return	Pointer to the located substring or NULL if not found.
+ */
+char *strstr(const char *s1, const char *s2);
+
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* __CROS_EC_STRINGS_H__ */
+#endif /* __CROS_EC_STRING_H__ */
diff --git a/builtin/strings.h b/builtin/strings.h
new file mode 100644
index 0000000000..cbcc858c36
--- /dev/null
+++ b/builtin/strings.h
@@ -0,0 +1,14 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_STRINGS_H__
+#define __CROS_EC_STRINGS_H__
+
+#include <stddef.h>
+
+int strcasecmp(const char *s1, const char *s2);
+int strncasecmp(const char *s1, const char *s2, size_t size);
+
+#endif /* __CROS_EC_STRINGS_H__ */
diff --git a/builtin/sys/time.h b/builtin/sys/time.h
new file mode 100644
index 0000000000..537ca6ceb0
--- /dev/null
+++ b/builtin/sys/time.h
@@ -0,0 +1,24 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_SYS_TIME_H__
+#define __CROS_EC_SYS_TIME_H__
+
+#include <sys/types.h>
+
+/**
+ * Partial implementation of <sys/time.h> header:
+ * https://pubs.opengroup.org/onlinepubs/9699919799/basedefs/sys_time.h.html
+ */
+
+typedef int64_t time_t;
+typedef int32_t suseconds_t;
+
+struct timeval {
+	time_t tv_sec; /* seconds */
+	suseconds_t tv_usec; /* microseconds */
+};
+
+#endif /* __CROS_EC_SYS_TIME_H__ */
diff --git a/builtin/sys/types.h b/builtin/sys/types.h
new file mode 100644
index 0000000000..01fc1a7749
--- /dev/null
+++ b/builtin/sys/types.h
@@ -0,0 +1,19 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_SYS_TYPES_H__
+#define __CROS_EC_SYS_TYPES_H__
+
+/* Data type for POSIX style clock() implementation */
+typedef long clock_t;
+
+/* There is a GCC macro for a size_t type, but not for a ssize_t type.
+ * The following construct convinces GCC to make __SIZE_TYPE__ signed.
+ */
+#define unsigned signed
+typedef __SIZE_TYPE__ ssize_t;
+#undef unsigned
+
+#endif /* __CROS_EC_SYS_TYPES_H__ */
diff --git a/builtin/time.h b/builtin/time.h
index a069ae18c9..36b07b4721 100644
--- a/builtin/time.h
+++ b/builtin/time.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/host/adc_chip.h b/chip/host/adc_chip.h
new file mode 100644
index 0000000000..cd55e1b5fb
--- /dev/null
+++ b/chip/host/adc_chip.h
@@ -0,0 +1,16 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Host-specific ADC module for Chrome EC */
+
+#ifndef __CROS_EC_ADC_CHIP_H
+#define __CROS_EC_ADC_CHIP_H
+
+/* Place-holder data structure to define ADC channels. */
+struct adc_t {
+	int unused;
+};
+
+#endif /* __CROS_EC_ADC_CHIP_H */
diff --git a/chip/host/build.mk b/chip/host/build.mk
index 8d2d69f3c3..b4a75cf3c6 100644
--- a/chip/host/build.mk
+++ b/chip/host/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
+# Copyright 2013 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -9,9 +9,9 @@
 CORE:=host
 
 chip-y=system.o gpio.o uart.o persistence.o flash.o lpc.o reboot.o \
-	clock.o spi_master.o trng.o
+	clock.o spi_controller.o trng.o
 
-ifndef CONFIG_KEYBOARD_NOT_RAW
+ifndef CONFIG_KEYBOARD_DISCRETE
 chip-$(HAS_TASK_KEYSCAN)+=keyboard_raw.o
 endif
 chip-$(CONFIG_USB_PD_TCPC)+=usb_pd_phy.o
diff --git a/chip/host/clock.c b/chip/host/clock.c
index 2c3c48661e..29fb0dfa5a 100644
--- a/chip/host/clock.c
+++ b/chip/host/clock.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -6,8 +6,13 @@
  */
 
 #include "clock.h"
+#include "common.h"
 
 int clock_get_freq(void)
 {
 	return 16000000;
 }
+
+test_mockable void clock_enable_module(enum module_id module, int enable)
+{
+}
diff --git a/chip/host/config_chip.h b/chip/host/config_chip.h
index 195744c556..323fb83d33 100644
--- a/chip/host/config_chip.h
+++ b/chip/host/config_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,21 +10,21 @@
 
 /* Memory mapping */
 #if !defined(TEST_NVMEM) && !defined(TEST_CR50_FUZZ)
-#define CONFIG_FLASH_SIZE 0x00020000
+#define CONFIG_FLASH_SIZE_BYTES 0x00020000
 #define CONFIG_FLASH_BANK_SIZE 0x1000
 #else
-#define CONFIG_FLASH_SIZE (512 * 1024)
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
 #define CONFIG_FLASH_BANK_SIZE 0x800
 #endif
 
-extern char __host_flash[CONFIG_FLASH_SIZE];
+extern char __host_flash[CONFIG_FLASH_SIZE_BYTES];
 
 #define CONFIG_PROGRAM_MEMORY_BASE ((uintptr_t)__host_flash)
-#define CONFIG_FLASH_ERASE_SIZE 0x0010	     /* erase bank size */
-#define CONFIG_FLASH_WRITE_SIZE 0x0002	     /* minimum write size */
+#define CONFIG_FLASH_ERASE_SIZE 0x0010 /* erase bank size */
+#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */
 #define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0080 /* ideal write size */
-#define CONFIG_RAM_BASE 0x0		     /* Not supported */
-#define CONFIG_RAM_SIZE                0x0 /* Not supported */
+#define CONFIG_RAM_BASE 0x0 /* Not supported */
+#define CONFIG_RAM_SIZE 0x0 /* Not supported */
 
 #define CONFIG_FPU
 
@@ -43,7 +43,7 @@ extern char __host_flash[CONFIG_FLASH_SIZE];
 
 /* Interval between HOOK_TICK notifications */
 #define HOOK_TICK_INTERVAL_MS 250
-#define HOOK_TICK_INTERVAL    (HOOK_TICK_INTERVAL_MS * MSEC)
+#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC)
 
 /* Do NOT use common panic code (designed to output information on the UART) */
 #undef CONFIG_COMMON_PANIC_OUTPUT
diff --git a/chip/host/flash.c b/chip/host/flash.c
index 9f79298d60..03a5fc777b 100644
--- a/chip/host/flash.c
+++ b/chip/host/flash.c
@@ -1,20 +1,21 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Flash module for emulator */
 
-#include <stdio.h>
-
+#include "builtin/assert.h"
 #include "common.h"
 #include "config_chip.h"
 #include "flash.h"
 #include "persistence.h"
 #include "util.h"
 
+#include <stdio.h>
+
 /* This needs to be aligned to the erase bank size for NVCTR. */
-__aligned(CONFIG_FLASH_ERASE_SIZE) char __host_flash[CONFIG_FLASH_SIZE];
+__aligned(CONFIG_FLASH_ERASE_SIZE) char __host_flash[CONFIG_FLASH_SIZE_BYTES];
 uint8_t __host_flash_protect[PHYSICAL_BANKS];
 
 /* Override this function to make flash erase/write operation fail */
@@ -26,8 +27,7 @@ test_mockable int flash_pre_op(void)
 static int flash_check_protect(int offset, int size)
 {
 	int first_bank = offset / CONFIG_FLASH_BANK_SIZE;
-	int last_bank = DIV_ROUND_UP(offset + size,
-				     CONFIG_FLASH_BANK_SIZE);
+	int last_bank = DIV_ROUND_UP(offset + size, CONFIG_FLASH_BANK_SIZE);
 	int bank;
 
 	for (bank = first_bank; bank < last_bank; ++bank)
@@ -52,6 +52,7 @@ static void flash_set_persistent(void)
 static void flash_get_persistent(void)
 {
 	FILE *f = get_persistent_storage("flash", "rb");
+	int sz;
 
 	if (f == NULL) {
 		fprintf(stderr,
@@ -60,12 +61,13 @@ static void flash_get_persistent(void)
 		return;
 	}
 
-	fread(__host_flash, sizeof(__host_flash), 1, f);
+	sz = fread(__host_flash, sizeof(__host_flash), 1, f);
+	ASSERT(sz == 1);
 
 	release_persistent_storage(f);
 }
 
-int flash_physical_write(int offset, int size, const char *data)
+int crec_flash_physical_write(int offset, int size, const char *data)
 {
 	ASSERT((size & (CONFIG_FLASH_WRITE_SIZE - 1)) == 0);
 
@@ -81,7 +83,7 @@ int flash_physical_write(int offset, int size, const char *data)
 	return EC_SUCCESS;
 }
 
-int flash_physical_erase(int offset, int size)
+int crec_flash_physical_erase(int offset, int size)
 {
 	ASSERT((size & (CONFIG_FLASH_ERASE_SIZE - 1)) == 0);
 
@@ -97,12 +99,12 @@ int flash_physical_erase(int offset, int size)
 	return EC_SUCCESS;
 }
 
-int flash_physical_get_protect(int bank)
+int crec_flash_physical_get_protect(int bank)
 {
 	return __host_flash_protect[bank];
 }
 
-uint32_t flash_physical_get_protect_flags(void)
+uint32_t crec_flash_physical_get_protect_flags(void)
 {
 	int i;
 	uint32_t flags = EC_FLASH_PROTECT_ALL_NOW;
@@ -114,20 +116,19 @@ uint32_t flash_physical_get_protect_flags(void)
 	return flags;
 }
 
-int flash_physical_protect_now(int all)
+int crec_flash_physical_protect_now(int all)
 {
 	memset(__host_flash_protect, 1, all ? PHYSICAL_BANKS : WP_BANK_COUNT);
 	return EC_SUCCESS;
 }
 
-uint32_t flash_physical_get_valid_flags(void)
+uint32_t crec_flash_physical_get_valid_flags(void)
 {
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-	       EC_FLASH_PROTECT_RO_NOW |
+	return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW |
 	       EC_FLASH_PROTECT_ALL_NOW;
 }
 
-uint32_t flash_physical_get_writable_flags(uint32_t cur_flags)
+uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
 {
 	uint32_t ret = 0;
 
@@ -146,13 +147,13 @@ uint32_t flash_physical_get_writable_flags(uint32_t cur_flags)
 	return ret;
 }
 
-int flash_pre_init(void)
+int crec_flash_pre_init(void)
 {
 	uint32_t prot_flags;
 
 	flash_get_persistent();
 
-	prot_flags = flash_get_protect();
+	prot_flags = crec_flash_get_protect();
 
 	if (prot_flags & EC_FLASH_PROTECT_GPIO_ASSERTED) {
 		/*
@@ -161,13 +162,14 @@ int flash_pre_init(void)
 		 */
 		if ((prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT) &&
 		    !(prot_flags & EC_FLASH_PROTECT_RO_NOW)) {
-			int rv = flash_set_protect(EC_FLASH_PROTECT_RO_NOW,
-						   EC_FLASH_PROTECT_RO_NOW);
+			int rv =
+				crec_flash_set_protect(EC_FLASH_PROTECT_RO_NOW,
+						       EC_FLASH_PROTECT_RO_NOW);
 			if (rv)
 				return rv;
 
 			/* Re-read flags */
-			prot_flags = flash_get_protect();
+			prot_flags = crec_flash_get_protect();
 		}
 	}
 
diff --git a/chip/host/gpio.c b/chip/host/gpio.c
index 3c15205ad5..d80d93dcf7 100644
--- a/chip/host/gpio.c
+++ b/chip/host/gpio.c
@@ -1,12 +1,10 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* GPIO module for emulator */
 
-#include "console.h"
-
 #include "common.h"
 #include "console.h"
 #include "gpio.h"
@@ -19,8 +17,8 @@ static int gpio_interrupt_enabled[GPIO_COUNT];
 /* Create a dictionary of names for debug console print */
 #define GPIO_INT(name, pin, flags, signal) #name,
 #define GPIO(name, pin, flags) #name,
-const char * gpio_names[GPIO_COUNT] = {
-	#include "gpio.wrap"
+const char *gpio_names[GPIO_COUNT] = {
+#include "gpio.wrap"
 };
 #undef GPIO
 #undef GPIO_INT
@@ -92,7 +90,7 @@ test_mockable void gpio_set_flags_by_mask(uint32_t port, uint32_t mask,
 }
 
 test_mockable void gpio_set_alternate_function(uint32_t port, uint32_t mask,
-						enum gpio_alternate_func func)
+					       enum gpio_alternate_func func)
 {
 	/* Nothing */
 }
diff --git a/chip/host/host_test.h b/chip/host/host_test.h
index e2bf5448c3..39516f751e 100644
--- a/chip/host/host_test.h
+++ b/chip/host/host_test.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,4 +14,4 @@
 /* Get emulator executable name */
 const char *__get_prog_name(void);
 
-#endif  /* __CROS_EC_HOST_TEST_H */
+#endif /* __CROS_EC_HOST_TEST_H */
diff --git a/chip/host/i2c.c b/chip/host/i2c.c
index 8e6f086b4f..3fddbbbac5 100644
--- a/chip/host/i2c.c
+++ b/chip/host/i2c.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -15,7 +15,7 @@
 
 struct i2c_dev {
 	int port;
-	uint16_t slave_addr_flags;
+	uint16_t addr_flags;
 	int valid;
 };
 
@@ -29,7 +29,7 @@ static void detach_init(void)
 }
 DECLARE_HOOK(HOOK_INIT, detach_init, HOOK_PRIO_FIRST);
 
-int test_detach_i2c(const int port, const uint16_t slave_addr_flags)
+int test_detach_i2c(const int port, const uint16_t addr_flags)
 {
 	int i;
 
@@ -41,20 +41,19 @@ int test_detach_i2c(const int port, const uint16_t slave_addr_flags)
 		return EC_ERROR_OVERFLOW;
 
 	detached_devs[i].port = port;
-	detached_devs[i].slave_addr_flags = slave_addr_flags;
+	detached_devs[i].addr_flags = addr_flags;
 	detached_devs[i].valid = 1;
 
 	return EC_SUCCESS;
 }
 
-int test_attach_i2c(const int port, const uint16_t slave_addr_flags)
+int test_attach_i2c(const int port, const uint16_t addr_flags)
 {
 	int i;
 
 	for (i = 0; i < MAX_DETACHED_DEV_COUNT; ++i)
-		if (detached_devs[i].valid &&
-		    detached_devs[i].port == port &&
-		    detached_devs[i].slave_addr_flags == slave_addr_flags)
+		if (detached_devs[i].valid && detached_devs[i].port == port &&
+		    detached_devs[i].addr_flags == addr_flags)
 			break;
 
 	if (i == MAX_DETACHED_DEV_COUNT)
@@ -64,32 +63,28 @@ int test_attach_i2c(const int port, const uint16_t slave_addr_flags)
 	return EC_SUCCESS;
 }
 
-static int test_check_detached(const int port,
-			       const uint16_t slave_addr_flags)
+static int test_check_detached(const int port, const uint16_t addr_flags)
 {
 	int i;
 
 	for (i = 0; i < MAX_DETACHED_DEV_COUNT; ++i)
-		if (detached_devs[i].valid &&
-		    detached_devs[i].port == port &&
-		    detached_devs[i].slave_addr_flags == slave_addr_flags)
+		if (detached_devs[i].valid && detached_devs[i].port == port &&
+		    detached_devs[i].addr_flags == addr_flags)
 			return 1;
 	return 0;
 }
 
-int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags,
-		  const uint8_t *out, int out_size,
-		  uint8_t *in, int in_size, int flags)
+int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out,
+		  int out_size, uint8_t *in, int in_size, int flags)
 {
 	const struct test_i2c_xfer *p;
 	int rv;
 
-	if (test_check_detached(port, slave_addr_flags))
+	if (test_check_detached(port, addr_flags))
 		return EC_ERROR_UNKNOWN;
 	for (p = __test_i2c_xfer; p < __test_i2c_xfer_end; ++p) {
-		rv = p->routine(port, slave_addr_flags,
-				out, out_size,
-				in, in_size, flags);
+		rv = p->routine(port, addr_flags, out, out_size, in, in_size,
+				flags);
 		if (rv != EC_ERROR_INVAL)
 			return rv;
 	}
diff --git a/chip/host/keyboard_raw.c b/chip/host/keyboard_raw.c
index 3e1f755f7f..47b9a7dda0 100644
--- a/chip/host/keyboard_raw.c
+++ b/chip/host/keyboard_raw.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/host/lpc.c b/chip/host/lpc.c
index dd64be9275..78619c5b75 100644
--- a/chip/host/lpc.c
+++ b/chip/host/lpc.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/host/persistence.c b/chip/host/persistence.c
index 90856b3bdf..369f58034b 100644
--- a/chip/host/persistence.c
+++ b/chip/host/persistence.c
@@ -1,15 +1,49 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Persistence module for emulator */
 
-#include <linux/limits.h>
-#include <unistd.h>
+/* This provides storage that can be opened, closed and reopened by the
+ * current process at will, whose naming even remains stable across multiple
+ * invocations of the same executable, while providing a unique name for
+ * each executable (as determined by path) that uses these routines.
+ *
+ * Useful when semi-permanent storage is required even with many
+ * similar processes running in parallel (e.g. in a highly parallel
+ * test suite run.
+ *
+ * mkstemp and friends don't provide these properties which is why we have
+ * this homegrown implementation of something similar-yet-different.
+ */
+
+#include "builtin/assert.h"
+#include "util.h"
+
 #include <stdio.h>
 #include <string.h>
 
+#include <linux/limits.h>
+#include <unistd.h>
+
+/* The longest path in a chroot seems to be about 280 characters (as of
+ * April 2021) so define a cut-off instead of just hoping for the best:
+ * If we were to run into a path that is nearly PATH_MAX bytes long,
+ * file names could end up being reused inadvertedly because the various
+ * snprintf calls would cut off the trailing characters, so the "tag" (and
+ * maybe more) is gone even though it only exists for differentiation.
+ *
+ * Instead bail out if we encounter a path (to an executable using these
+ * routines) that is longer than we expect.
+ *
+ * Round up for some spare room because why not?
+ */
+static const int max_len = 300;
+
+/* This must be at least the size of the prefix added in get_storage_path */
+static const int max_prefix_len = 25;
+
 static void get_storage_path(char *out)
 {
 	char buf[PATH_MAX];
@@ -19,6 +53,8 @@ static void get_storage_path(char *out)
 	sz = readlink("/proc/self/exe", buf, PATH_MAX - 1);
 	buf[sz] = '\0';
 
+	ASSERT(sz <= max_len);
+
 	/* replace / by underscores in the path to get the shared memory name */
 	current = strchr(buf, '/');
 	while (current) {
@@ -26,21 +62,32 @@ static void get_storage_path(char *out)
 		current = strchr(current, '/');
 	}
 
-	snprintf(out, PATH_MAX - 1, "/dev/shm/EC_persist_%s", buf);
+	sz = snprintf(out, PATH_MAX - 1, "/dev/shm/EC_persist_%.*s", max_len,
+		      buf);
+	ASSERT(sz > 0);
+
 	out[PATH_MAX - 1] = '\0';
+
+	ASSERT(sz <= max_len + max_prefix_len);
 }
 
 FILE *get_persistent_storage(const char *tag, const char *mode)
 {
 	char buf[PATH_MAX];
 	char path[PATH_MAX];
+	int sz;
+
+	/* There's no longer tag in use right now, and there shouldn't be. */
+	ASSERT(strlen(tag) < 32);
 
 	/*
 	 * The persistent storage with tag 'foo' for test 'bar' would
 	 * be named 'bar_persist_foo'
 	 */
 	get_storage_path(buf);
-	snprintf(path, PATH_MAX - 1, "%s_%s", buf, tag);
+	sz = snprintf(path, PATH_MAX - 1, "%.*s_%32s", max_len + max_prefix_len,
+		      buf, tag);
+	ASSERT(sz > 0);
 	path[PATH_MAX - 1] = '\0';
 
 	return fopen(path, mode);
@@ -55,9 +102,15 @@ void remove_persistent_storage(const char *tag)
 {
 	char buf[PATH_MAX];
 	char path[PATH_MAX];
+	int sz;
+
+	/* There's no longer tag in use right now, and there shouldn't be. */
+	ASSERT(strlen(tag) < 32);
 
 	get_storage_path(buf);
-	snprintf(path, PATH_MAX - 1, "%s_%s", buf, tag);
+	sz = snprintf(path, PATH_MAX - 1, "%.*s_%32s", max_len + max_prefix_len,
+		      buf, tag);
+	ASSERT(sz > 0);
 	path[PATH_MAX - 1] = '\0';
 
 	unlink(path);
diff --git a/chip/host/persistence.h b/chip/host/persistence.h
index a473f8dfb0..479788815f 100644
--- a/chip/host/persistence.h
+++ b/chip/host/persistence.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/host/reboot.c b/chip/host/reboot.c
index e932c5f11a..59e15ee81d 100644
--- a/chip/host/reboot.c
+++ b/chip/host/reboot.c
@@ -1,18 +1,19 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Emulator self-reboot procedure */
 
-#include <string.h>
-#include <unistd.h>
-
 #include "console.h"
 #include "host_test.h"
 #include "reboot.h"
 #include "test_util.h"
 
+#include <string.h>
+
+#include <unistd.h>
+
 #ifdef TEST_FUZZ
 /* reboot breaks fuzzing, let's just not do it. */
 void emulator_reboot(void)
@@ -20,10 +21,9 @@ void emulator_reboot(void)
 	ccprints("Emulator would reboot here. Fuzzing: doing nothing.");
 }
 #else /* !TEST_FUZZ */
-noreturn
-void emulator_reboot(void)
+noreturn void emulator_reboot(void)
 {
-	char *argv[] = {strdup(__get_prog_name()), NULL};
+	char *argv[] = { strdup(__get_prog_name()), NULL };
 	emulator_flush();
 	execv(__get_prog_name(), argv);
 	while (1)
diff --git a/chip/host/reboot.h b/chip/host/reboot.h
index 1c1201f451..e382db0adf 100644
--- a/chip/host/reboot.h
+++ b/chip/host/reboot.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,9 +10,10 @@
 
 #include <stdnoreturn.h>
 
-#ifndef TEST_FUZZ
+#if !(defined(TEST_FUZZ) || defined(CONFIG_ZTEST))
 noreturn
 #endif
-void emulator_reboot(void);
+	void
+	emulator_reboot(void);
 
-#endif
+#endif /* __CROS_EC_REBOOT_H */
diff --git a/chip/host/registers.h b/chip/host/registers.h
index 7347ce04d3..3c75686b40 100644
--- a/chip/host/registers.h
+++ b/chip/host/registers.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/host/spi_controller.c b/chip/host/spi_controller.c
new file mode 100644
index 0000000000..ae6e2c9346
--- /dev/null
+++ b/chip/host/spi_controller.c
@@ -0,0 +1,41 @@
+/* Copyright 2019 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Mock SPI Controller driver for unit test.
+ */
+
+#include "common.h"
+#include "gpio.h"
+#include "spi.h"
+
+#include <stdint.h>
+
+test_mockable int spi_enable(const struct spi_device_t *spi_device, int enable)
+{
+	return EC_SUCCESS;
+}
+
+test_mockable int spi_transaction(const struct spi_device_t *spi_device,
+				  const uint8_t *txdata, int txlen,
+				  uint8_t *rxdata, int rxlen)
+{
+	return EC_SUCCESS;
+}
+
+test_mockable int spi_transaction_async(const struct spi_device_t *spi_device,
+					const uint8_t *txdata, int txlen,
+					uint8_t *rxdata, int rxlen)
+{
+	return EC_SUCCESS;
+}
+
+test_mockable int spi_transaction_flush(const struct spi_device_t *spi_device)
+{
+	return EC_SUCCESS;
+}
+
+test_mockable int spi_transaction_wait(const struct spi_device_t *spi_device)
+{
+	return EC_SUCCESS;
+}
diff --git a/chip/host/spi_master.c b/chip/host/spi_master.c
deleted file mode 100644
index 1900e7b7a8..0000000000
--- a/chip/host/spi_master.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Mock Master SPI driver for unit test.
- */
-
-#include <stdint.h>
-
-#include "common.h"
-#include "gpio.h"
-
-#include "spi.h"
-
-test_mockable int spi_enable(int port, int enable)
-{
-	return EC_SUCCESS;
-}
-
-test_mockable int spi_transaction(const struct spi_device_t *spi_device,
-				  const uint8_t *txdata, int txlen,
-				  uint8_t *rxdata, int rxlen)
-{
-	return EC_SUCCESS;
-}
-
-test_mockable int spi_transaction_async(const struct spi_device_t *spi_device,
-					const uint8_t *txdata, int txlen,
-					uint8_t *rxdata, int rxlen)
-{
-	return EC_SUCCESS;
-}
-
-test_mockable int spi_transaction_flush(const struct spi_device_t *spi_device)
-{
-	return EC_SUCCESS;
-}
-
-test_mockable int spi_transaction_wait(const struct spi_device_t *spi_device)
-{
-	return EC_SUCCESS;
-}
diff --git a/chip/host/system.c b/chip/host/system.c
index 66d3442467..ae650e3f9f 100644
--- a/chip/host/system.c
+++ b/chip/host/system.c
@@ -1,10 +1,11 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* System module for emulator */
 
+#include "builtin/assert.h"
 #include "common.h"
 #include "ec_commands.h"
 #include "host_test.h"
@@ -43,15 +44,12 @@ static void ramdata_get_persistent(void)
 {
 	FILE *f = get_persistent_storage("ramdata", "rb");
 
-	if (f == NULL) {
-		fprintf(stderr,
-			"No RAM data found. Initializing to 0x00.\n");
+	if ((f == NULL) || (fread(__ram_data, RAM_DATA_SIZE, 1, f) != 1)) {
+		fprintf(stderr, "No RAM data found. Initializing to 0x00.\n");
 		memset(__ram_data, 0, RAM_DATA_SIZE);
 		return;
 	}
 
-	fread(__ram_data, RAM_DATA_SIZE, 1, f);
-
 	release_persistent_storage(f);
 
 	/*
@@ -76,9 +74,8 @@ static uint32_t get_image_copy(void)
 	FILE *f = get_persistent_storage("image_copy", "rb");
 	uint32_t ret;
 
-	if (f == NULL)
+	if ((f == NULL) || (fread(&ret, sizeof(ret), 1, f) != 1))
 		return EC_IMAGE_UNKNOWN;
-	fread(&ret, sizeof(ret), 1, f);
 	release_persistent_storage(f);
 	remove_persistent_storage("image_copy");
 
@@ -100,9 +97,8 @@ static uint32_t load_reset_flags(void)
 	FILE *f = get_persistent_storage("reset_flags", "rb");
 	uint32_t ret;
 
-	if (f == NULL)
+	if ((f == NULL) || (fread(&ret, sizeof(ret), 1, f) != 1))
 		return EC_RESET_FLAG_POWER_ON;
-	fread(&ret, sizeof(ret), 1, f);
 	release_persistent_storage(f);
 	remove_persistent_storage("reset_flags");
 
@@ -123,9 +119,8 @@ static int load_time(timestamp_t *t)
 {
 	FILE *f = get_persistent_storage("time", "rb");
 
-	if (f == NULL)
+	if ((f == NULL) || (fread(t, sizeof(*t), 1, f) != 1))
 		return 0;
-	fread(t, sizeof(*t), 1, f);
 	release_persistent_storage(f);
 	remove_persistent_storage("time");
 
@@ -134,14 +129,14 @@ static int load_time(timestamp_t *t)
 
 test_mockable struct panic_data *panic_get_data(void)
 {
-	return (struct panic_data *)
-		(__ram_data + RAM_DATA_SIZE - sizeof(struct panic_data));
+	return (struct panic_data *)(__ram_data + RAM_DATA_SIZE -
+				     sizeof(struct panic_data));
 }
 
-test_mockable uintptr_t get_panic_data_start()
+test_mockable uintptr_t get_panic_data_start(void)
 {
-	return (uintptr_t)
-		(__ram_data + RAM_DATA_SIZE - sizeof(struct panic_data));
+	return (uintptr_t)(__ram_data + RAM_DATA_SIZE -
+			   sizeof(struct panic_data));
 }
 
 test_mockable void system_reset(int flags)
@@ -224,28 +219,27 @@ int system_set_scratchpad(uint32_t value)
 {
 	FILE *f = get_persistent_storage("scratchpad", "w");
 
-	fprintf(f, "%lu", value);
+	fprintf(f, "%u", value);
 	release_persistent_storage(f);
 
 	return EC_SUCCESS;
 }
 
-uint32_t system_get_scratchpad(void)
+int system_get_scratchpad(uint32_t *value)
 {
 	FILE *f = get_persistent_storage("scratchpad", "r");
-	uint32_t value;
 	int success;
 
 	if (f == NULL)
-		return 0;
+		return EC_ERROR_UNKNOWN;
 
-	success = fscanf(f, "%u", &value);
+	success = fscanf(f, "%u", value);
 	release_persistent_storage(f);
 
 	if (success)
-		return value;
+		return EC_SUCCESS;
 	else
-		return 0;
+		return EC_ERROR_UNKNOWN;
 }
 
 static void __jump_resetvec(void)
@@ -286,3 +280,10 @@ void system_pre_init(void)
 	*(uintptr_t *)(__host_flash + CONFIG_RW_MEM_OFF + 4) =
 		(uintptr_t)__rw_jump_resetvec;
 }
+
+test_mockable enum ec_error_list
+get_ap_reset_stats(struct ap_reset_log_entry *reset_log_entries,
+		   size_t num_reset_log_entries, uint32_t *resets_since_ec_boot)
+{
+	return EC_ERROR_INVAL;
+}
diff --git a/chip/host/trng.c b/chip/host/trng.c
index 8407aa6ea1..f67dd6c4db 100644
--- a/chip/host/trng.c
+++ b/chip/host/trng.c
@@ -1,5 +1,5 @@
 
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -14,27 +14,32 @@
 #error "This fake trng driver must not be used in non-test builds."
 #endif
 
+#include "common.h"
+
 #include <stdint.h>
 #include <stdlib.h> /* Only valid for host */
 
-#include "common.h"
-
 static unsigned int seed;
 
-test_mockable void init_trng(void)
+test_mockable void trng_init(void)
 {
 	seed = 0;
 	srand(seed);
 }
 
-test_mockable void exit_trng(void)
+test_mockable void trng_exit(void)
+{
+}
+
+test_mockable uint32_t trng_rand(void)
 {
+	return (uint32_t)rand_r(&seed);
 }
 
-test_mockable void rand_bytes(void *buffer, size_t len)
+test_mockable void trng_rand_bytes(void *buffer, size_t len)
 {
 	uint8_t *b, *end;
 
-	for (b = buffer, end = b+len; b != end; b++)
+	for (b = buffer, end = b + len; b != end; b++)
 		*b = (uint8_t)rand_r(&seed);
 }
diff --git a/chip/host/uart.c b/chip/host/uart.c
index 578924612f..71e8345196 100644
--- a/chip/host/uart.c
+++ b/chip/host/uart.c
@@ -1,16 +1,11 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* UART driver for emulator */
 
-#include <pthread.h>
-#include <signal.h>
-#include <stdio.h>
-#include <termio.h>
-#include <unistd.h>
-
+#include "builtin/assert.h"
 #include "common.h"
 #include "queue.h"
 #include "task.h"
@@ -18,6 +13,13 @@
 #include "uart.h"
 #include "util.h"
 
+#include <signal.h>
+#include <stdio.h>
+
+#include <pthread.h>
+#include <termio.h>
+#include <unistd.h>
+
 static int stopped = 1;
 static int init_done;
 
@@ -55,7 +57,6 @@ static void test_capture_char(char c)
 	capture_buf[capture_size++] = c;
 }
 
-
 const char *test_get_captured_console(void)
 {
 	return (const char *)capture_buf;
@@ -190,6 +191,6 @@ void uart_init(void)
 	pthread_mutex_unlock(&mutex);
 #endif
 
-	stopped = 1;  /* Not transmitting yet */
+	stopped = 1; /* Not transmitting yet */
 	init_done = 1;
 }
diff --git a/chip/host/usb_pd_phy.c b/chip/host/usb_pd_phy.c
index ba81b986ad..aa5f022f3e 100644
--- a/chip/host/usb_pd_phy.c
+++ b/chip/host/usb_pd_phy.c
@@ -1,8 +1,9 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
 #include "crc.h"
@@ -37,9 +38,9 @@ static struct pd_physical {
 	int verified_idx;
 } pd_phy[CONFIG_USB_PD_PORT_MAX_COUNT];
 
-static const uint16_t enc4b5b[] = {
-	0x1E, 0x09, 0x14, 0x15, 0x0A, 0x0B, 0x0E, 0x0F, 0x12, 0x13, 0x16,
-	0x17, 0x1A, 0x1B, 0x1C, 0x1D};
+static const uint16_t enc4b5b[] = { 0x1E, 0x09, 0x14, 0x15, 0x0A, 0x0B,
+				    0x0E, 0x0F, 0x12, 0x13, 0x16, 0x17,
+				    0x1A, 0x1B, 0x1C, 0x1D };
 
 /* Test utilities */
 static void pd_test_reset_phy(int port)
@@ -216,7 +217,6 @@ int pd_test_tx_msg_verify_crc(int port)
 	return pd_test_tx_msg_verify_word(port, crc32_result());
 }
 
-
 /* Mock functions */
 
 void pd_init_dequeue(int port)
diff --git a/chip/ish/aontaskfw/ipapg.S b/chip/ish/aontaskfw/ipapg.S
index f0d3f8c554..305b9a0fb6 100755
--- a/chip/ish/aontaskfw/ipapg.S
+++ b/chip/ish/aontaskfw/ipapg.S
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/ish/aontaskfw/ish_aon_defs.h b/chip/ish/aontaskfw/ish_aon_defs.h
index 3cc3a491c0..0b3990100a 100644
--- a/chip/ish/aontaskfw/ish_aon_defs.h
+++ b/chip/ish/aontaskfw/ish_aon_defs.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/ish/aontaskfw/ish_aon_share.h b/chip/ish/aontaskfw/ish_aon_share.h
index 20b36ec2b2..b986150b73 100644
--- a/chip/ish/aontaskfw/ish_aon_share.h
+++ b/chip/ish/aontaskfw/ish_aon_share.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,13 +11,12 @@
 #include "power_mgt.h"
 
 /* magic ID for valid aontask image check */
-#define AON_MAGIC_ID			        0x544E4F41  /*"AONT"*/
+#define AON_MAGIC_ID 0x544E4F41 /*"AONT"*/
 
 /* aontask error code  */
-#define AON_SUCCESS				0
-#define AON_ERROR_NOT_SUPPORT_POWER_MODE	1
-#define AON_ERROR_DMA_FAILED			2
-
+#define AON_SUCCESS 0
+#define AON_ERROR_NOT_SUPPORT_POWER_MODE 1
+#define AON_ERROR_DMA_FAILED 2
 
 /* shared data structure between main FW and aontask */
 struct ish_aon_share {
diff --git a/chip/ish/aontaskfw/ish_aontask.c b/chip/ish/aontaskfw/ish_aontask.c
index ab9d02abbf..6f2d9c9f2d 100644
--- a/chip/ish/aontaskfw/ish_aontask.c
+++ b/chip/ish/aontaskfw/ish_aontask.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -45,8 +45,8 @@
 
 #include "common.h"
 #include "ia_structs.h"
-#include "ish_aon_share.h"
 #include "ish_aon_defs.h"
+#include "ish_aon_share.h"
 #include "ish_dma.h"
 #include "power_mgt.h"
 
@@ -64,9 +64,9 @@
  * AON_IDT_ENTRY_VEC_FIRST ~  AON_IDT_ENTRY_VEC_LAST
  */
 #ifdef CONFIG_ISH_NEW_PM
-#define AON_IDT_ENTRY_VEC_LAST		ISH_PMU_WAKEUP_VEC
+#define AON_IDT_ENTRY_VEC_LAST ISH_PMU_WAKEUP_VEC
 #else
-#define AON_IDT_ENTRY_VEC_FIRST		ISH_PMU_WAKEUP_VEC
+#define AON_IDT_ENTRY_VEC_FIRST ISH_PMU_WAKEUP_VEC
 #endif
 
 #ifdef CONFIG_ISH_PM_RESET_PREP
@@ -76,21 +76,71 @@
  * (if CONFIG_ISH_PM_RESET_PREP defined)
  */
 #ifdef CONFIG_ISH_NEW_PM
-#define AON_IDT_ENTRY_VEC_FIRST		ISH_RESET_PREP_VEC
+#define AON_IDT_ENTRY_VEC_FIRST ISH_RESET_PREP_VEC
 #else
-#define AON_IDT_ENTRY_VEC_LAST		ISH_RESET_PREP_VEC
+#define AON_IDT_ENTRY_VEC_LAST ISH_RESET_PREP_VEC
 #endif
 #else
 /* only need handle single PMU wakeup interrupt */
 #ifdef CONFIG_ISH_NEW_PM
-#define AON_IDT_ENTRY_VEC_FIRST		ISH_PMU_WAKEUP_VEC
+#define AON_IDT_ENTRY_VEC_FIRST ISH_PMU_WAKEUP_VEC
 #else
-#define AON_IDT_ENTRY_VEC_LAST		ISH_PMU_WAKEUP_VEC
+#define AON_IDT_ENTRY_VEC_LAST ISH_PMU_WAKEUP_VEC
 #endif
 #endif
 
 static void handle_reset(enum ish_pm_state pm_state);
 
+#if defined(CHIP_VARIANT_ISH5P4)
+static void sb_upstream_write_raw_base(uint32_t addr, uint32_t attr,
+				       uint32_t data, uint32_t sairs,
+				       uint8_t addr48, uint16_t addr_hi)
+{
+	uint32_t eflags;
+	uint32_t addr_hi_32;
+
+	addr_hi_32 = addr_hi | (1 << 31);
+
+	eflags = interrupt_lock();
+
+	PMU_VNN_REQ = (1 << VNN_ID_SIDEBAND);
+	while (!(PMU_VNN_REQ_ACK & PMU_VNN_REQ_ACK_STATUS))
+		continue;
+
+	if (dma_poll(SBEP_REG_UP_MSG_STATUS_ADDR, 0, UP_STATUS_BUSY_MASK) ==
+	    DMA_RC_OK) {
+		SBEP_REG_UP_MSG_REQ_ADDR_LOW = addr;
+
+		if (addr48) {
+			SBEP_REG_UP_MSG_REQ_ADDR_HIGH = addr_hi_32;
+		} else {
+			SBEP_REG_UP_MSG_REQ_ADDR_HIGH = 0;
+		}
+
+		SBEP_REG_UP_MSG_REQ_ATTR = attr;
+		SBEP_REG_UP_MSG_REQ_DATA = data;
+		SBEP_REG_UP_MSG_REQ_EH = sairs;
+		SBEP_REG_UP_MSG_COMMAND = SBEP_CMD_WRITE;
+
+		dma_poll(SBEP_REG_UP_MSG_STATUS_ADDR, 0, UP_STATUS_BUSY_MASK);
+		dma_poll(SBEP_REG_UP_MSG_STATUS_ADDR, UP_STATUS_MSG_SENT_MASK,
+			 UP_STATUS_MSG_SENT_MASK);
+		SBEP_REG_UP_MSG_STATUS = UP_STATUS_MSG_SENT_CLR;
+	}
+
+	PMU_VNN_REQ = (1 << VNN_ID_SIDEBAND);
+	interrupt_unlock(eflags);
+}
+
+static void sb_upstream_write_raw(uint32_t addr, uint32_t attr, uint32_t data,
+				  uint32_t sairs)
+{
+	addr = addr & 0x0000FFFF;
+
+	sb_upstream_write_raw_base(addr, attr, data, sairs, 0, 0);
+}
+#endif
+
 /* ISR for PMU wakeup interrupt */
 static void pmu_wakeup_isr(void)
 {
@@ -101,7 +151,7 @@ static void pmu_wakeup_isr(void)
 	IOAPIC_EOI_REG = ISH_PMU_WAKEUP_VEC;
 	LAPIC_EOI_REG = 0x0;
 
-	__asm__ volatile ("iret;");
+	__asm__ volatile("iret;");
 
 	__builtin_unreachable();
 }
@@ -157,14 +207,15 @@ static void reset_prep_isr(void)
  *                     ---------------------------
  */
 
-static struct idt_entry aon_idt[AON_IDT_ENTRY_VEC_LAST -
-				AON_IDT_ENTRY_VEC_FIRST + 1];
+static struct idt_entry
+	aon_idt[AON_IDT_ENTRY_VEC_LAST - AON_IDT_ENTRY_VEC_FIRST + 1];
 
 static struct idt_header aon_idt_hdr = {
 
 	.limit = (sizeof(struct idt_entry) * (AON_IDT_ENTRY_VEC_LAST + 1)) - 1,
 	.entries = (struct idt_entry *)((uint32_t)&aon_idt -
-			(sizeof(struct idt_entry) * AON_IDT_ENTRY_VEC_FIRST))
+					(sizeof(struct idt_entry) *
+					 AON_IDT_ENTRY_VEC_FIRST))
 };
 
 /**
@@ -245,13 +296,9 @@ static ldt_entry aon_ldt[2] = {
 	 * limit: 0xFFFFFFFF
 	 * flag: 0x9B, Present = 1, DPL = 0, code segment
 	 */
-	{
-		.dword_lo = GEN_GDT_DESC_LO(0x0, 0xFFFFFFFF,
-				GDT_DESC_CODE_FLAGS),
+	{ .dword_lo = GEN_GDT_DESC_LO(0x0, 0xFFFFFFFF, GDT_DESC_CODE_FLAGS),
 
-		.dword_up = GEN_GDT_DESC_UP(0x0, 0xFFFFFFFF,
-				GDT_DESC_CODE_FLAGS)
-	},
+	  .dword_up = GEN_GDT_DESC_UP(0x0, 0xFFFFFFFF, GDT_DESC_CODE_FLAGS) },
 
 	/**
 	 * entry 1 for data segment
@@ -259,16 +306,11 @@ static ldt_entry aon_ldt[2] = {
 	 * limit: 0xFFFFFFFF
 	 * flag: 0x93, Present = 1, DPL = 0, data segment
 	 */
-	{
-		.dword_lo = GEN_GDT_DESC_LO(0x0, 0xFFFFFFFF,
-				GDT_DESC_DATA_FLAGS),
+	{ .dword_lo = GEN_GDT_DESC_LO(0x0, 0xFFFFFFFF, GDT_DESC_DATA_FLAGS),
 
-		.dword_up = GEN_GDT_DESC_UP(0x0, 0xFFFFFFFF,
-				GDT_DESC_DATA_FLAGS)
-	}
+	  .dword_up = GEN_GDT_DESC_UP(0x0, 0xFFFFFFFF, GDT_DESC_DATA_FLAGS) }
 };
 
-
 /* shared data structure between main FW and aon task */
 struct ish_aon_share aon_share = {
 	.magic_id = AON_MAGIC_ID,
@@ -282,15 +324,14 @@ struct ish_aon_share aon_share = {
 /* snowball structure */
 #if defined(CHIP_FAMILY_ISH3)
 /* on ISH3, reused ISH2PMC IPC message registers */
-#define SNOWBALL_BASE	IPC_ISH2PMC_MSG_BASE
+#define SNOWBALL_BASE IPC_ISH2PMC_MSG_BASE
 #else
 /* from ISH4, used reserved rom part of AON memory */
-#define SNOWBALL_BASE	(CONFIG_AON_PERSISTENT_BASE + 256)
+#define SNOWBALL_BASE (CONFIG_AON_PERSISTENT_BASE + 256)
 #endif
 
 struct snowball_struct *snowball = (void *)SNOWBALL_BASE;
 
-
 /* In IMR DDR, ISH FW image has a manifest header */
 #define ISH_FW_IMAGE_MANIFEST_HEADER_SIZE (0x1000)
 
@@ -324,30 +365,24 @@ static int store_main_fw(void)
 	uint64_t imr_fw_rw_addr;
 
 	imr_fw_addr = (((uint64_t)snowball->uma_base_hi << 32) +
-		       snowball->uma_base_lo +
-		       snowball->fw_offset +
+		       snowball->uma_base_lo + snowball->fw_offset +
 		       ISH_FW_IMAGE_MANIFEST_HEADER_SIZE);
 
-	imr_fw_rw_addr = (imr_fw_addr
-			  + aon_share.main_fw_rw_addr
-			  - CONFIG_RAM_BASE);
+	imr_fw_rw_addr =
+		(imr_fw_addr + aon_share.main_fw_rw_addr - CONFIG_RAM_BASE);
 
 	/* disable BCG (Block Clock Gating) for DMA, DMA can be accessed now */
 	disable_dma_bcg();
 
 	/* store main FW's read and write data region to IMR/UMA DDR */
-	ret = ish_dma_copy(
-		PAGING_CHAN,
-		imr_fw_rw_addr,
-		aon_share.main_fw_rw_addr,
-		aon_share.main_fw_rw_size,
-		SRAM_TO_UMA);
+	ret = ish_dma_copy(PAGING_CHAN, imr_fw_rw_addr,
+			   aon_share.main_fw_rw_addr, aon_share.main_fw_rw_size,
+			   SRAM_TO_UMA);
 
 	/* enable BCG for DMA, DMA can't be accessed now */
 	enable_dma_bcg();
 
 	if (ret != DMA_RC_OK) {
-
 		aon_share.last_error = AON_ERROR_DMA_FAILED;
 		aon_share.error_count++;
 
@@ -365,31 +400,24 @@ static int restore_main_fw(void)
 	uint64_t imr_fw_rw_addr;
 
 	imr_fw_addr = (((uint64_t)snowball->uma_base_hi << 32) +
-		       snowball->uma_base_lo +
-		       snowball->fw_offset +
+		       snowball->uma_base_lo + snowball->fw_offset +
 		       ISH_FW_IMAGE_MANIFEST_HEADER_SIZE);
 
-	imr_fw_ro_addr = (imr_fw_addr
-			  + aon_share.main_fw_ro_addr
-			  - CONFIG_RAM_BASE);
+	imr_fw_ro_addr =
+		(imr_fw_addr + aon_share.main_fw_ro_addr - CONFIG_RAM_BASE);
 
-	imr_fw_rw_addr = (imr_fw_addr
-			  + aon_share.main_fw_rw_addr
-			  - CONFIG_RAM_BASE);
+	imr_fw_rw_addr =
+		(imr_fw_addr + aon_share.main_fw_rw_addr - CONFIG_RAM_BASE);
 
 	/* disable BCG (Block Clock Gating) for DMA, DMA can be accessed now */
 	disable_dma_bcg();
 
 	/* restore main FW's read only code and data region from IMR/UMA DDR */
-	ret = ish_dma_copy(
-		PAGING_CHAN,
-		aon_share.main_fw_ro_addr,
-		imr_fw_ro_addr,
-		aon_share.main_fw_ro_size,
-		UMA_TO_SRAM);
+	ret = ish_dma_copy(PAGING_CHAN, aon_share.main_fw_ro_addr,
+			   imr_fw_ro_addr, aon_share.main_fw_ro_size,
+			   UMA_TO_SRAM);
 
 	if (ret != DMA_RC_OK) {
-
 		aon_share.last_error = AON_ERROR_DMA_FAILED;
 		aon_share.error_count++;
 
@@ -400,19 +428,14 @@ static int restore_main_fw(void)
 	}
 
 	/* restore main FW's read and write data region from IMR/UMA DDR */
-	ret = ish_dma_copy(
-			PAGING_CHAN,
-			aon_share.main_fw_rw_addr,
-			imr_fw_rw_addr,
-			aon_share.main_fw_rw_size,
-			UMA_TO_SRAM
-			);
+	ret = ish_dma_copy(PAGING_CHAN, aon_share.main_fw_rw_addr,
+			   imr_fw_rw_addr, aon_share.main_fw_rw_size,
+			   UMA_TO_SRAM);
 
 	/* enable BCG for DMA, DMA can't be accessed now */
 	enable_dma_bcg();
 
 	if (ret != DMA_RC_OK) {
-
 		aon_share.last_error = AON_ERROR_DMA_FAILED;
 		aon_share.error_count++;
 
@@ -424,10 +447,10 @@ static int restore_main_fw(void)
 
 #if defined(CHIP_FAMILY_ISH3)
 /* on ISH3, the last SRAM bank is reserved for AON use */
-#define SRAM_POWER_OFF_BANKS	(CONFIG_RAM_BANKS - 1)
+#define SRAM_POWER_OFF_BANKS (CONFIG_RAM_BANKS - 1)
 #elif defined(CHIP_FAMILY_ISH4) || defined(CHIP_FAMILY_ISH5)
 /* ISH4 and ISH5 have separate AON memory, can power off entire main SRAM */
-#define SRAM_POWER_OFF_BANKS	CONFIG_RAM_BANKS
+#define SRAM_POWER_OFF_BANKS CONFIG_RAM_BANKS
 #else
 #error "CHIP_FAMILY_ISH(3|4|5) must be defined"
 #endif
@@ -436,33 +459,33 @@ static int restore_main_fw(void)
  * check SRAM bank i power gated status in PMU_SRAM_PG_EN register
  * 1: power gated 0: not power gated
  */
-#define BANK_PG_STATUS(i)	(PMU_SRAM_PG_EN & (0x1 << (i)))
+#define BANK_PG_STATUS(i) (PMU_SRAM_PG_EN & (0x1 << (i)))
 
 /* enable power gate of a SRAM bank */
-#define BANK_PG_ENABLE(i)	(PMU_SRAM_PG_EN |= (0x1 << (i)))
+#define BANK_PG_ENABLE(i) (PMU_SRAM_PG_EN |= (0x1 << (i)))
 
 /* disable power gate of a SRAM bank */
-#define BANK_PG_DISABLE(i)	(PMU_SRAM_PG_EN &= ~(0x1 << (i)))
+#define BANK_PG_DISABLE(i) (PMU_SRAM_PG_EN &= ~(0x1 << (i)))
 
 /**
  * check SRAM bank i disabled status in ISH_SRAM_CTRL_CSFGR register
  * 1: disabled 0: enabled
  */
-#define BANK_DISABLE_STATUS(i)	(ISH_SRAM_CTRL_CSFGR & (0x1 << ((i) + 4)))
+#define BANK_DISABLE_STATUS(i) (ISH_SRAM_CTRL_CSFGR & (0x1 << ((i) + 4)))
 
 /* enable a SRAM bank in ISH_SRAM_CTRL_CSFGR register */
-#define BANK_ENABLE(i)		(ISH_SRAM_CTRL_CSFGR &= ~(0x1 << ((i) + 4)))
+#define BANK_ENABLE(i) (ISH_SRAM_CTRL_CSFGR &= ~(0x1 << ((i) + 4)))
 
 /* disable a SRAM bank in ISH_SRAM_CTRL_CSFGR register */
-#define BANK_DISABLE(i)		(ISH_SRAM_CTRL_CSFGR |= (0x1 << ((i) + 4)))
+#define BANK_DISABLE(i) (ISH_SRAM_CTRL_CSFGR |= (0x1 << ((i) + 4)))
 
 /* SRAM needs time to warm up after power on */
-#define SRAM_WARM_UP_DELAY_CNT		10
+#define SRAM_WARM_UP_DELAY_CNT 10
 
 /* SRAM needs time to enter retention mode */
-#define CYCLES_PER_US                  100
-#define SRAM_RETENTION_US_DELAY	       5
-#define SRAM_RETENTION_CYCLES_DELAY    (SRAM_RETENTION_US_DELAY * CYCLES_PER_US)
+#define CYCLES_PER_US 100
+#define SRAM_RETENTION_US_DELAY 5
+#define SRAM_RETENTION_CYCLES_DELAY (SRAM_RETENTION_US_DELAY * CYCLES_PER_US)
 
 static void sram_power(int on)
 {
@@ -485,10 +508,9 @@ static void sram_power(int on)
 		erase_cfg = (((bank_size - 4) >> 2) << 2) | 0x1;
 
 	for (i = 0; i < SRAM_POWER_OFF_BANKS; i++) {
-
-		if (on && (BANK_PG_STATUS(i) || (!IS_ENABLED(CONFIG_ISH_NEW_PM)
-						&& BANK_DISABLE_STATUS(i)))) {
-
+		if (on &&
+		    (BANK_PG_STATUS(i) || (!IS_ENABLED(CONFIG_ISH_NEW_PM) &&
+					   BANK_DISABLE_STATUS(i)))) {
 			/* power on and enable a bank */
 			BANK_PG_DISABLE(i);
 
@@ -519,13 +541,12 @@ static void sram_power(int on)
 		 * booting ISH
 		 */
 		ISH_SRAM_CTRL_INTR = 0xFFFFFFFF;
-
 	}
 }
 
 #define RTC_TICKS_IN_SECOND 32768
 
-static  __maybe_unused uint64_t get_rtc(void)
+static __maybe_unused uint64_t get_rtc(void)
 {
 	uint32_t lower;
 	uint32_t upper;
@@ -645,8 +666,7 @@ static void handle_d0i2(void)
 	}
 
 	/* set main SRAM into retention mode*/
-	PMU_LDO_CTRL = PMU_LDO_ENABLE_BIT
-		| PMU_LDO_RETENTION_BIT;
+	PMU_LDO_CTRL = PMU_LDO_ENABLE_BIT | PMU_LDO_RETENTION_BIT;
 
 	/* delay some cycles before halt */
 	delay(SRAM_RETENTION_CYCLES_DELAY);
@@ -670,6 +690,10 @@ static void handle_d0i2(void)
 
 	clear_vnnred_aoncg();
 
+	if (IS_ENABLED(CONFIG_ISH_NEW_PM) &&
+	    (PMU_RST_PREP & PMU_RST_PREP_AVAIL))
+		handle_reset(ISH_PM_STATE_RESET_PREP);
+
 	/* set main SRAM intto normal mode */
 	PMU_LDO_CTRL = PMU_LDO_ENABLE_BIT;
 
@@ -696,6 +720,13 @@ static void handle_d0i3(void)
 		aon_share.pg_exit = 0;
 	}
 
+#if defined(CHIP_VARIANT_ISH5P4)
+	/* Set PMC LTR to 2ms before DMA copy */
+	if (IS_ENABLED(CONFIG_ISH_NEW_PM))
+		sb_upstream_write_raw(0, LTR_CMD_ATTR, LTR_CMD_DATA_2MS,
+				      SBEP_PMC_SAIRS_VAL);
+#endif
+
 	/* store main FW 's context to IMR DDR from main SRAM */
 	ret = store_main_fw();
 
@@ -706,6 +737,13 @@ static void handle_d0i3(void)
 	/* power off main SRAM */
 	sram_power(0);
 
+#if defined(CHIP_VARIANT_ISH5P4)
+	/* Set LTR to a large number after DMA copy done */
+	if (IS_ENABLED(CONFIG_ISH_NEW_PM))
+		sb_upstream_write_raw(0, LTR_CMD_ATTR, LTR_CMD_DATA_INFINITE,
+				      SBEP_PMC_SAIRS_VAL);
+#endif
+
 	set_vnnred_aoncg();
 
 	if (IS_ENABLED(CONFIG_ISH_IPAPG) && is_ipapg_allowed()) {
@@ -725,6 +763,10 @@ static void handle_d0i3(void)
 
 	clear_vnnred_aoncg();
 
+	if (IS_ENABLED(CONFIG_ISH_NEW_PM) &&
+	    (PMU_RST_PREP & PMU_RST_PREP_AVAIL))
+		handle_reset(ISH_PM_STATE_RESET_PREP);
+
 	/* power on main SRAM */
 	sram_power(1);
 
@@ -734,6 +776,13 @@ static void handle_d0i3(void)
 					aon_share.uma_msb);
 	}
 
+#if defined(CHIP_VARIANT_ISH5P4)
+	/* Set PMC LTR to 2ms before DMA copy */
+	if (IS_ENABLED(CONFIG_ISH_NEW_PM))
+		sb_upstream_write_raw(0, LTR_CMD_ATTR, LTR_CMD_DATA_2MS,
+				      SBEP_PMC_SAIRS_VAL);
+#endif
+
 	/* restore main FW 's context to main SRAM from IMR DDR */
 	ret = restore_main_fw();
 
@@ -782,7 +831,7 @@ static void handle_reset(enum ish_pm_state pm_state)
 		 * ISH ipc host driver will set DMA_ENABLED_MASK bit when it
 		 * is loaded and starts, and clear this bit when it is removed.
 		 *
-		 * see: https://github.com/torvalds/linux/blob/master/drivers/
+		 * see: https://github.com/torvalds/linux/blob/HEAD/drivers/
 		 *      hid/intel-ish-hid/ipc/ipc.c
 		 *
 		 * we have two kinds of reset situations need to handle here:
@@ -801,8 +850,8 @@ static void handle_reset(enum ish_pm_state pm_state)
 		 * Sx for long time.
 		 *
 		 */
-		if (IPC_ISH_RMP2 & DMA_ENABLED_MASK) {
-
+		if (IS_ENABLED(CONFIG_ISH_NEW_PM) ||
+		    (IPC_ISH_RMP2 & DMA_ENABLED_MASK)) {
 			/* clear ISH2HOST doorbell register */
 			*IPC_ISH2HOST_DOORBELL_ADDR = 0;
 
@@ -827,7 +876,6 @@ static void handle_reset(enum ish_pm_state pm_state)
 
 		ish_mia_halt();
 	}
-
 }
 
 static void handle_unknown_state(void)
@@ -840,22 +888,21 @@ static void handle_unknown_state(void)
 
 void ish_aon_main(void)
 {
-
 	/* set PMU wakeup interrupt gate using LDT code segment selector(0x4) */
 	if (IS_ENABLED(CONFIG_ISH_NEW_PM)) {
-		aon_idt[AON_IDT_ENTRY_VEC_LAST -
-			AON_IDT_ENTRY_VEC_FIRST].dword_lo =
+		aon_idt[AON_IDT_ENTRY_VEC_LAST - AON_IDT_ENTRY_VEC_FIRST]
+			.dword_lo =
 			GEN_IDT_DESC_LO(&pmu_wakeup_isr, 0x4, IDT_DESC_FLAGS);
 
-		aon_idt[AON_IDT_ENTRY_VEC_LAST -
-			AON_IDT_ENTRY_VEC_FIRST].dword_up =
+		aon_idt[AON_IDT_ENTRY_VEC_LAST - AON_IDT_ENTRY_VEC_FIRST]
+			.dword_up =
 			GEN_IDT_DESC_UP(&pmu_wakeup_isr, 0x4, IDT_DESC_FLAGS);
 	} else {
-		aon_idt[0].dword_lo = GEN_IDT_DESC_LO(&pmu_wakeup_isr, 0x4,
-			IDT_DESC_FLAGS);
+		aon_idt[0].dword_lo =
+			GEN_IDT_DESC_LO(&pmu_wakeup_isr, 0x4, IDT_DESC_FLAGS);
 
-		aon_idt[0].dword_up = GEN_IDT_DESC_UP(&pmu_wakeup_isr, 0x4,
-			IDT_DESC_FLAGS);
+		aon_idt[0].dword_up =
+			GEN_IDT_DESC_UP(&pmu_wakeup_isr, 0x4, IDT_DESC_FLAGS);
 	}
 
 	if (IS_ENABLED(CONFIG_ISH_PM_RESET_PREP)) {
@@ -864,39 +911,34 @@ void ish_aon_main(void)
 		 * selector(0x4)
 		 */
 		if (IS_ENABLED(CONFIG_ISH_NEW_PM)) {
-			aon_idt[0].dword_lo = GEN_IDT_DESC_LO(&reset_prep_isr,
-				0x4, IDT_DESC_FLAGS);
+			aon_idt[0].dword_lo = GEN_IDT_DESC_LO(
+				&reset_prep_isr, 0x4, IDT_DESC_FLAGS);
 
-			aon_idt[0].dword_up = GEN_IDT_DESC_UP(&reset_prep_isr,
-				0x4, IDT_DESC_FLAGS);
+			aon_idt[0].dword_up = GEN_IDT_DESC_UP(
+				&reset_prep_isr, 0x4, IDT_DESC_FLAGS);
 		} else {
-			aon_idt[AON_IDT_ENTRY_VEC_LAST -
-				AON_IDT_ENTRY_VEC_FIRST].dword_lo =
-				GEN_IDT_DESC_LO(&reset_prep_isr, 0x4,
-				IDT_DESC_FLAGS);
-
-			aon_idt[AON_IDT_ENTRY_VEC_LAST -
-				AON_IDT_ENTRY_VEC_FIRST].dword_up =
-				GEN_IDT_DESC_UP(&reset_prep_isr, 0x4,
-				IDT_DESC_FLAGS);
+			aon_idt[AON_IDT_ENTRY_VEC_LAST - AON_IDT_ENTRY_VEC_FIRST]
+				.dword_lo = GEN_IDT_DESC_LO(
+				&reset_prep_isr, 0x4, IDT_DESC_FLAGS);
+
+			aon_idt[AON_IDT_ENTRY_VEC_LAST - AON_IDT_ENTRY_VEC_FIRST]
+				.dword_up = GEN_IDT_DESC_UP(
+				&reset_prep_isr, 0x4, IDT_DESC_FLAGS);
 		}
 	}
 
 	while (1) {
-
 		/**
 		 *  will start to run from here when switched to aontask from
 		 *  the second time
 		 */
 
 		/* save main FW's IDT and load aontask's IDT */
-		__asm__ volatile (
-				"sidtl %0;\n"
-				"lidtl %1;\n"
-				:
-				: "m" (aon_share.main_fw_idt_hdr),
-				  "m" (aon_idt_hdr)
-				);
+		__asm__ volatile("sidtl %0;\n"
+				 "lidtl %1;\n"
+				 :
+				 : "m"(aon_share.main_fw_idt_hdr),
+				   "m"(aon_idt_hdr));
 
 		aon_share.last_error = AON_SUCCESS;
 
@@ -927,11 +969,9 @@ void ish_aon_main(void)
 		}
 
 		/* restore main FW's IDT and switch back to main FW */
-		__asm__ volatile(
-				"lidtl %0;\n"
-				:
-				: "m" (aon_share.main_fw_idt_hdr)
-				);
+		__asm__ volatile("lidtl %0;\n"
+				 :
+				 : "m"(aon_share.main_fw_idt_hdr));
 
 		if (IS_ENABLED(CONFIG_ISH_IPAPG) && aon_share.pg_exit) {
 			mainfw_gdt.entries[tr / sizeof(struct gdt_entry)]
@@ -939,6 +979,6 @@ void ish_aon_main(void)
 			pg_exit_restore_ctx();
 		}
 
-		__asm__ volatile ("iret;");
+		__asm__ volatile("iret;");
 	}
 }
diff --git a/chip/ish/aontaskfw/ish_aontask.lds.S b/chip/ish/aontaskfw/ish_aontask.lds.S
index ca5f54f705..306beef5e9 100644
--- a/chip/ish/aontaskfw/ish_aontask.lds.S
+++ b/chip/ish/aontaskfw/ish_aontask.lds.S
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/ish/build.mk b/chip/ish/build.mk
index 9f220abd21..3777f9f4ce 100644
--- a/chip/ish/build.mk
+++ b/chip/ish/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -20,8 +20,8 @@ endif
 chip-y+=clock.o gpio.o system.o hwtimer.o uart.o flash.o ish_persistent_data.o
 chip-$(CONFIG_I2C)+=i2c.o
 chip-$(CONFIG_WATCHDOG)+=watchdog.o
-chip-$(CONFIG_HOSTCMD_HECI)+=host_command_heci.o
-chip-$(CONFIG_HOSTCMD_HECI)+=heci.o system_state_subsys.o ipc_heci.o
+chip-$(CONFIG_HOST_INTERFACE_HECI)+=host_command_heci.o
+chip-$(CONFIG_HOST_INTERFACE_HECI)+=heci.o system_state_subsys.o ipc_heci.o
 chip-$(CONFIG_HID_HECI)+=hid_subsys.o
 chip-$(CONFIG_HID_HECI)+=heci.o system_state_subsys.o ipc_heci.o
 chip-$(CONFIG_DMA_PAGING)+=dma.o
diff --git a/chip/ish/clock.c b/chip/ish/clock.c
index ac818f5733..133711edf7 100644
--- a/chip/ish/clock.c
+++ b/chip/ish/clock.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,13 +7,12 @@
 
 #include "clock.h"
 #include "common.h"
-#include "util.h"
 #include "power_mgt.h"
+#include "util.h"
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
-
+#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args)
 
 void clock_init(void)
 {
@@ -30,3 +29,7 @@ void clock_refresh_console_in_use(void)
 	 */
 	ish_pm_refresh_console_in_use();
 }
+
+test_mockable void clock_enable_module(enum module_id module, int enable)
+{
+}
diff --git a/chip/ish/config_chip.h b/chip/ish/config_chip.h
index 4c884d00cc..b76c302f4e 100644
--- a/chip/ish/config_chip.h
+++ b/chip/ish/config_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,18 +15,18 @@
 #endif
 
 /* Number of IRQ vectors on the ISH */
-#define CONFIG_IRQ_COUNT	(VEC_TO_IRQ(255) + 1)
+#define CONFIG_IRQ_COUNT (VEC_TO_IRQ(255) + 1)
 
 /* Use a bigger console output buffer */
 #undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE	2048
+#define CONFIG_UART_TX_BUF_SIZE 2048
 
 /* Interval between HOOK_TICK notifications */
-#define HOOK_TICK_INTERVAL_MS	250
-#define HOOK_TICK_INTERVAL	(HOOK_TICK_INTERVAL_MS * MSEC)
+#define HOOK_TICK_INTERVAL_MS 250
+#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC)
 
 /* Maximum number of deferrable functions */
-#define DEFERRABLE_MAX_COUNT	8
+#define DEFERRABLE_MAX_COUNT 8
 
 /* this macro causes 'pause' and reduces loop counts inside loop. */
 #define CPU_RELAX() asm volatile("rep; nop" ::: "memory")
@@ -36,49 +36,48 @@
 /*****************************************************************************/
 
 #ifdef CHIP_VARIANT_ISH5P4
-#define CONFIG_RAM_BASE		0xFF200000
+#define CONFIG_RAM_BASE 0xFF200000
 #else
-#define CONFIG_RAM_BASE		0xFF000000
+#define CONFIG_RAM_BASE 0xFF000000
 #endif
-#define CONFIG_RAM_SIZE		0x000A0000
+#define CONFIG_RAM_SIZE 0x000A0000
 #ifdef CHIP_VARIANT_ISH5P4
-#define CONFIG_RAM_BANK_SIZE	0x00010000
+#define CONFIG_RAM_BANK_SIZE 0x00010000
 #else
-#define CONFIG_RAM_BANK_SIZE	0x00008000
+#define CONFIG_RAM_BANK_SIZE 0x00008000
 #endif
 
 #if defined(CHIP_FAMILY_ISH3)
 /* On ISH3, there is no separate AON memory; use last 4KB of SRAM */
-#define CONFIG_AON_RAM_BASE		0xFF09F000
-#define CONFIG_AON_RAM_SIZE		0x00001000
+#define CONFIG_AON_RAM_BASE 0xFF09F000
+#define CONFIG_AON_RAM_SIZE 0x00001000
 #elif defined(CHIP_FAMILY_ISH4)
-#define CONFIG_AON_RAM_BASE		0xFF800000
-#define CONFIG_AON_RAM_SIZE		0x00001000
+#define CONFIG_AON_RAM_BASE 0xFF800000
+#define CONFIG_AON_RAM_SIZE 0x00001000
 #elif defined(CHIP_FAMILY_ISH5)
-#define CONFIG_AON_RAM_BASE		0xFF800000
-#define CONFIG_AON_RAM_SIZE		0x00002000
+#define CONFIG_AON_RAM_BASE 0xFF800000
+#define CONFIG_AON_RAM_SIZE 0x00002000
 #else
 #error "CHIP_FAMILY_ISH(3|4|5) must be defined"
 #endif
 
 /* The end of the AON memory is reserved for read-only use */
-#define CONFIG_AON_PERSISTENT_SIZE	0x180
-#define CONFIG_AON_PERSISTENT_BASE	(CONFIG_AON_RAM_BASE	\
-					 + CONFIG_AON_RAM_SIZE	\
-					 - CONFIG_AON_PERSISTENT_SIZE)
+#define CONFIG_AON_PERSISTENT_SIZE 0x180
+#define CONFIG_AON_PERSISTENT_BASE \
+	(CONFIG_AON_RAM_BASE + CONFIG_AON_RAM_SIZE - CONFIG_AON_PERSISTENT_SIZE)
 
 /* Store persistent panic data in AON memory. */
-#define CONFIG_PANIC_DATA_BASE		(&(ish_persistent_data.panic_data))
+#define CONFIG_PANIC_DATA_BASE (&(ish_persistent_data.panic_data))
 
 /* System stack size */
-#define CONFIG_STACK_SIZE		1024
+#define CONFIG_STACK_SIZE 1024
 
 /* non-standard task stack sizes */
-#define IDLE_TASK_STACK_SIZE		640
-#define LARGER_TASK_STACK_SIZE		1024
-#define HUGE_TASK_STACK_SIZE		2048
+#define IDLE_TASK_STACK_SIZE 640
+#define LARGER_TASK_STACK_SIZE 1024
+#define HUGE_TASK_STACK_SIZE 2048
 /* Default task stack size */
-#define TASK_STACK_SIZE			640
+#define TASK_STACK_SIZE 640
 
 /****************************************************************************/
 /* Define our flash layout. */
@@ -87,13 +86,13 @@
  */
 
 /* Protect bank size 4K bytes */
-#define CONFIG_FLASH_BANK_SIZE		0x00001000
+#define CONFIG_FLASH_BANK_SIZE 0x00001000
 /* Sector erase size 4K bytes */
-#define CONFIG_FLASH_ERASE_SIZE		0x00000000
+#define CONFIG_FLASH_ERASE_SIZE 0x00000000
 /* Minimum write size */
-#define CONFIG_FLASH_WRITE_SIZE		0x00000000
+#define CONFIG_FLASH_WRITE_SIZE 0x00000000
 /* Program memory base address */
-#define CONFIG_PROGRAM_MEMORY_BASE	0x00100000
+#define CONFIG_PROGRAM_MEMORY_BASE 0x00100000
 
 #include "config_flash_layout.h"
 
@@ -101,16 +100,16 @@
 /*                        Watchdog Timer Configuration                       */
 /*****************************************************************************/
 #if defined(CHIP_FAMILY_ISH3) || defined(CHIP_FAMILY_ISH5)
-#define WDT_CLOCK_HZ		(120000000) /* 120 MHz */
+#define WDT_CLOCK_HZ (120000000) /* 120 MHz */
 #elif defined(CHIP_FAMILY_ISH4)
-#define WDT_CLOCK_HZ		(100000000) /* 100 MHz */
+#define WDT_CLOCK_HZ (100000000) /* 100 MHz */
 #else
 #error "CHIP_FAMILY_ISH(3|4|5) must be defined"
 #endif
 
 /* Provide WDT vec number to Minute-IA core implementation */
 #undef CONFIG_MIA_WDT_VEC
-#define CONFIG_MIA_WDT_VEC	ISH_WDT_VEC
+#define CONFIG_MIA_WDT_VEC ISH_WDT_VEC
 
 /****************************************************************************/
 /* Customize the build */
@@ -133,4 +132,4 @@
 #define CONFIG_ISH_CLEAR_FABRIC_ERRORS
 #endif
 
-#endif  /* __CROS_EC_CONFIG_CHIP_H */
+#endif /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/chip/ish/config_flash_layout.h b/chip/ish/config_flash_layout.h
index 0430baf3eb..4e4b7ad90b 100644
--- a/chip/ish/config_flash_layout.h
+++ b/chip/ish/config_flash_layout.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,14 +8,14 @@
 
 /* Mem-mapped, No external SPI for ISH */
 #undef CONFIG_EXTERNAL_STORAGE
-#define  CONFIG_MAPPED_STORAGE
-#undef  CONFIG_FLASH_PSTATE
+#define CONFIG_MAPPED_STORAGE
+#undef CONFIG_FLASH_PSTATE
 #undef CONFIG_SPI_FLASH
 
 #ifdef CHIP_VARIANT_ISH5P4
-#define CONFIG_ISH_BOOT_START		0xFF200000
+#define CONFIG_ISH_BOOT_START 0xFF200000
 #else
-#define CONFIG_ISH_BOOT_START		0xFF000000
+#define CONFIG_ISH_BOOT_START 0xFF000000
 #endif
 
 /*****************************************************************************/
@@ -24,40 +24,37 @@
  * turn off SPI and flash, making these unnecessary.
  */
 
-#define CONFIG_MAPPED_STORAGE_BASE	0x0
+#define CONFIG_MAPPED_STORAGE_BASE 0x0
 
-#define CONFIG_EC_PROTECTED_STORAGE_OFF  (CONFIG_FLASH_SIZE - 0x20000)
+#define CONFIG_EC_PROTECTED_STORAGE_OFF (CONFIG_FLASH_SIZE_BYTES - 0x20000)
 #define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x20000
-#define CONFIG_EC_WRITABLE_STORAGE_OFF   (CONFIG_FLASH_SIZE - 0x40000)
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE  0x20000
+#define CONFIG_EC_WRITABLE_STORAGE_OFF (CONFIG_FLASH_SIZE_BYTES - 0x40000)
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x20000
 
 /* Unused for ISH - loader is external to ISH FW */
-#define CONFIG_LOADER_MEM_OFF		0
-#define CONFIG_LOADER_SIZE		0xC00
-
+#define CONFIG_LOADER_MEM_OFF 0
+#define CONFIG_LOADER_SIZE 0xC00
 
 /* RO/RW images - not relevant for ISH
  */
-#define CONFIG_RO_MEM_OFF		(CONFIG_LOADER_MEM_OFF + \
-					CONFIG_LOADER_SIZE)
-#define CONFIG_RO_SIZE			(97 * 1024)
-#define CONFIG_RW_MEM_OFF		CONFIG_RO_MEM_OFF
-#define CONFIG_RW_SIZE			CONFIG_RO_SIZE
+#define CONFIG_RO_MEM_OFF (CONFIG_LOADER_MEM_OFF + CONFIG_LOADER_SIZE)
+#define CONFIG_RO_SIZE (97 * 1024)
+#define CONFIG_RW_MEM_OFF CONFIG_RO_MEM_OFF
+#define CONFIG_RW_SIZE CONFIG_RO_SIZE
 
 /*****************************************************************************/
 
 /* Not relevant for ISH */
-#define CONFIG_BOOT_HEADER_STORAGE_OFF	0
-#define CONFIG_BOOT_HEADER_STORAGE_SIZE	0x240
+#define CONFIG_BOOT_HEADER_STORAGE_OFF 0
+#define CONFIG_BOOT_HEADER_STORAGE_SIZE 0x240
 
-#define CONFIG_LOADER_STORAGE_OFF	(CONFIG_BOOT_HEADER_STORAGE_OFF + \
-					CONFIG_BOOT_HEADER_STORAGE_SIZE)
+#define CONFIG_LOADER_STORAGE_OFF \
+	(CONFIG_BOOT_HEADER_STORAGE_OFF + CONFIG_BOOT_HEADER_STORAGE_SIZE)
 
 /* RO image immediately follows the loader image */
-#define CONFIG_RO_STORAGE_OFF		(CONFIG_LOADER_STORAGE_OFF + \
-					CONFIG_LOADER_SIZE)
+#define CONFIG_RO_STORAGE_OFF (CONFIG_LOADER_STORAGE_OFF + CONFIG_LOADER_SIZE)
 
 /* RW image starts at the beginning of SPI */
-#define CONFIG_RW_STORAGE_OFF		0
+#define CONFIG_RW_STORAGE_OFF 0
 
 #endif /* __CROS_EC_CONFIG_FLASH_LAYOUT_H */
diff --git a/chip/ish/dma.c b/chip/ish/dma.c
index b9744fd234..eae6a850f1 100644
--- a/chip/ish/dma.c
+++ b/chip/ish/dma.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,34 +7,12 @@
 
 #include "common.h"
 #include "console.h"
-#include "registers.h"
 #include "ish_dma.h"
+#include "registers.h"
 #include "util.h"
 
 static int dma_init_called; /* If ish_dma_init is called */
 
-static int dma_poll(uint32_t addr, uint32_t expected, uint32_t mask)
-{
-	int retval = -1;
-	uint32_t counter = 0;
-
-	/*
-	 * The timeout is approximately 2.2 seconds according to
-	 * value of UINT32_MAX, 120MHZ ISH clock frequency and
-	 * instruction count which is around 4.
-	 */
-	while (counter < (UINT32_MAX / 64)) {
-		/* test condition */
-		if ((REG32(addr) & mask) == expected) {
-			retval = DMA_RC_OK;
-			break;
-		}
-		counter++;
-	}
-
-	return retval;
-}
-
 void ish_dma_ocp_timeout_disable(void)
 {
 	if (!IS_ENABLED(CONFIG_ISH_NEW_PM)) {
@@ -44,24 +22,6 @@ void ish_dma_ocp_timeout_disable(void)
 	}
 }
 
-static inline uint32_t interrupt_lock(void)
-{
-	uint32_t eflags = 0;
-	__asm__ volatile("pushfl;" /* save eflag value */
-			 "popl  %0;"
-			 "cli;"
-			 : "=r"(eflags)); /* shut off interrupts */
-	return eflags;
-}
-
-static inline void interrupt_unlock(uint32_t eflags)
-{
-	__asm__ volatile("pushl  %0;" /* restore elfag values */
-			 "popfl;"
-			 :
-			 : "r"(eflags));
-}
-
 void dma_configure_psize(void)
 {
 	/* Give chan0 512 bytes for high performance, and chan1 128 bytes. */
@@ -112,8 +72,8 @@ int ish_dma_copy(uint32_t chan, uint32_t dst, uint32_t src, uint32_t length,
 	mode |= NON_SNOOP;
 	MISC_DMA_CTL_REG(chan) = mode; /* Set transfer direction */
 
-	DMA_CFG_REG = DMA_ENABLE;  /* Enable DMA module */
-	DMA_LLP(chan_reg) = 0;     /* Linked lists are not used */
+	DMA_CFG_REG = DMA_ENABLE; /* Enable DMA module */
+	DMA_LLP(chan_reg) = 0; /* Linked lists are not used */
 	DMA_CTL_LOW(chan_reg) =
 		0 /* Set transfer parameters */ |
 		(DMA_CTL_TT_FC_M2M_DMAC << DMA_CTL_TT_FC_SHIFT) |
@@ -126,24 +86,27 @@ int ish_dma_copy(uint32_t chan, uint32_t dst, uint32_t src, uint32_t length,
 
 	interrupt_unlock(eflags);
 	while (length) {
-		chunk = (length > DMA_MAX_BLOCK_SIZE) ? DMA_MAX_BLOCK_SIZE
-						      : length;
+		chunk = (length > DMA_MAX_BLOCK_SIZE) ? DMA_MAX_BLOCK_SIZE :
+							length;
 
 		if (rc != DMA_RC_OK)
 			break;
 
 		eflags = interrupt_lock();
 		MISC_CHID_CFG_REG = chan; /* Set channel to configure */
-		DMA_CTL_HIGH(chan_reg) =
-			chunk;		 /* Set number of bytes to transfer */
+		DMA_CTL_HIGH(chan_reg) = chunk; /* Set number of bytes to
+						   transfer */
 		DMA_DAR(chan_reg) = dst; /* Destination address */
 		DMA_SAR(chan_reg) = src; /* Source address */
 		DMA_EN_REG = DMA_CH_EN_BIT(chan) |
-			     DMA_CH_EN_WE_BIT(chan); /* Enable the channel */
+			     DMA_CH_EN_WE_BIT(chan); /* Enable
+							the
+							channel
+						      */
 		interrupt_unlock(eflags);
 
-		rc = ish_wait_for_dma_done(
-			chan); /* Wait for trans completion */
+		rc = ish_wait_for_dma_done(chan); /* Wait for trans completion
+						   */
 
 		dst += chunk;
 		src += chunk;
diff --git a/chip/ish/flash.c b/chip/ish/flash.c
index 8ef4d1a73c..c9c4a132d9 100644
--- a/chip/ish/flash.c
+++ b/chip/ish/flash.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,13 +6,12 @@
 #include "common.h"
 #include "flash.h"
 
-
 /**
  * Initialize the module.
  *
  * Applies at-boot protection settings if necessary.
  */
-int flash_pre_init(void)
+int crec_flash_pre_init(void)
 {
 	return EC_SUCCESS;
 }
diff --git a/chip/ish/gpio.c b/chip/ish/gpio.c
index 6c7a27e1e7..287e7a375b 100644
--- a/chip/ish/gpio.c
+++ b/chip/ish/gpio.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,7 +24,7 @@ test_mockable int gpio_get_level(enum gpio_signal signal)
 	if (g->port == UNIMPLEMENTED_GPIO_BANK)
 		return 0;
 
-	return  !!(ISH_GPIO_GPLR & g->mask);
+	return !!(ISH_GPIO_GPLR & g->mask);
 }
 
 void gpio_set_level(enum gpio_signal signal, int value)
@@ -55,8 +55,8 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
 	}
 
 	/* ISH 3 can't support both rising and falling edge */
-	if (IS_ENABLED(CHIP_FAMILY_ISH3) &&
-	    (flags & GPIO_INT_F_RISING) && (flags & GPIO_INT_F_FALLING)) {
+	if (IS_ENABLED(CHIP_FAMILY_ISH3) && (flags & GPIO_INT_F_RISING) &&
+	    (flags & GPIO_INT_F_FALLING)) {
 		ccprintf("\n\nISH 2/3 does not support both rising & falling "
 			 "edge for %d 0x%02x\n\n",
 			 port, mask);
@@ -65,7 +65,7 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
 	/* GPSR/GPCR Output high/low */
 	if (flags & GPIO_HIGH) /* Output high */
 		ISH_GPIO_GPSR |= mask;
-	else if (flags & GPIO_LOW)  /* output low */
+	else if (flags & GPIO_LOW) /* output low */
 		ISH_GPIO_GPCR |= mask;
 
 	/* GPDR pin direction 1 = output, 0 = input*/
@@ -123,7 +123,6 @@ void gpio_pre_init(void)
 	const struct gpio_info *g = gpio_list;
 
 	for (i = 0; i < GPIO_COUNT; i++, g++) {
-
 		flags = g->flags;
 
 		if (flags & GPIO_DEFAULT)
diff --git a/chip/ish/hbm.h b/chip/ish/hbm.h
index edfb587d21..17c7853b1d 100644
--- a/chip/ish/hbm.h
+++ b/chip/ish/hbm.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,70 +6,69 @@
 #ifndef __HBM_H
 #define __HBM_H
 
-#include <stdint.h>
-#include <stddef.h>
-
 #include "heci_client.h"
 
-#define HBM_MAJOR_VERSION			1
+#include <stddef.h>
+#include <stdint.h>
+
+#define HBM_MAJOR_VERSION 1
 #ifdef HECI_ENABLE_DMA
-#define HBM_MINOR_VERSION			2
+#define HBM_MINOR_VERSION 2
 #else
-#define HBM_MINOR_VERSION			0
+#define HBM_MINOR_VERSION 0
 #endif
 
 #define __packed __attribute__((packed))
 
-#define HECI_MSG_REPONSE_FLAG			0x80
+#define HECI_MSG_REPONSE_FLAG 0x80
 
 enum HECI_BUS_MSG {
 	/* requests */
-	HECI_BUS_MSG_VERSION_REQ		= 1,
-	HECI_BUS_MSG_HOST_STOP_REQ		= 2,
-	HECI_BUS_MSG_ME_STOP_REQ		= 3,
-	HECI_BUS_MSG_HOST_ENUM_REQ		= 4,
-	HECI_BUS_MSG_HOST_CLIENT_PROP_REQ	= 5,
-	HECI_BUS_MSG_CLIENT_CONNECT_REQ		= 6,
-	HECI_BUS_MSG_CLIENT_DISCONNECT_REQ	= 7,
-	HECI_BUS_MSG_FLOW_CONTROL		= 8,
-	HECI_BUS_MSG_RESET_REQ			= 9,
-	HECI_BUS_MSG_ADD_CLIENT_REQ		= 0x0A,
-	HECI_BUS_MSG_DMA_REQ			= 0x10,
-	HECI_BUS_MSG_DMA_ALLOC_NOTIFY		= 0x11,
-	HECI_BUS_MSG_DMA_XFER_REQ		= 0x12,
+	HECI_BUS_MSG_VERSION_REQ = 1,
+	HECI_BUS_MSG_HOST_STOP_REQ = 2,
+	HECI_BUS_MSG_ME_STOP_REQ = 3,
+	HECI_BUS_MSG_HOST_ENUM_REQ = 4,
+	HECI_BUS_MSG_HOST_CLIENT_PROP_REQ = 5,
+	HECI_BUS_MSG_CLIENT_CONNECT_REQ = 6,
+	HECI_BUS_MSG_CLIENT_DISCONNECT_REQ = 7,
+	HECI_BUS_MSG_FLOW_CONTROL = 8,
+	HECI_BUS_MSG_RESET_REQ = 9,
+	HECI_BUS_MSG_ADD_CLIENT_REQ = 0x0A,
+	HECI_BUS_MSG_DMA_REQ = 0x10,
+	HECI_BUS_MSG_DMA_ALLOC_NOTIFY = 0x11,
+	HECI_BUS_MSG_DMA_XFER_REQ = 0x12,
 
 	/* responses */
-	HECI_BUS_MSG_VERSION_RESP		=
+	HECI_BUS_MSG_VERSION_RESP =
 		(HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_VERSION_REQ),
-	HECI_BUS_MSG_HOST_STOP_RESP		=
+	HECI_BUS_MSG_HOST_STOP_RESP =
 		(HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_HOST_STOP_REQ),
-	HECI_BUS_MSG_HOST_ENUM_RESP		=
+	HECI_BUS_MSG_HOST_ENUM_RESP =
 		(HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_HOST_ENUM_REQ),
-	HECI_BUS_MSG_HOST_CLIENT_PROP_RESP	=
+	HECI_BUS_MSG_HOST_CLIENT_PROP_RESP =
 		(HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_HOST_CLIENT_PROP_REQ),
-	HECI_BUS_MSG_CLIENT_CONNECT_RESP	=
+	HECI_BUS_MSG_CLIENT_CONNECT_RESP =
 		(HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_CLIENT_CONNECT_REQ),
-	HECI_BUS_MSG_CLIENT_DISCONNECT_RESP	= 
+	HECI_BUS_MSG_CLIENT_DISCONNECT_RESP =
 		(HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_CLIENT_DISCONNECT_REQ),
-	HECI_BUS_MSG_RESET_RESP			=
+	HECI_BUS_MSG_RESET_RESP =
 		(HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_RESET_REQ),
-	HECI_BUS_MSG_ADD_CLIENT_RESP		=
+	HECI_BUS_MSG_ADD_CLIENT_RESP =
 		(HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_ADD_CLIENT_REQ),
-	HECI_BUS_MSG_DMA_RESP			=
-		(HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_DMA_REQ),
-	HECI_BUS_MSG_DMA_ALLOC_RESP		=
+	HECI_BUS_MSG_DMA_RESP = (HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_DMA_REQ),
+	HECI_BUS_MSG_DMA_ALLOC_RESP =
 		(HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_DMA_ALLOC_NOTIFY),
-	HECI_BUS_MSG_DMA_XFER_RESP		=
+	HECI_BUS_MSG_DMA_XFER_RESP =
 		(HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_DMA_XFER_REQ)
 };
 
 enum {
-	HECI_CONNECT_STATUS_SUCCESS           = 0,
-	HECI_CONNECT_STATUS_CLIENT_NOT_FOUND  = 1,
-	HECI_CONNECT_STATUS_ALREADY_EXISTS    = 2,
-	HECI_CONNECT_STATUS_REJECTED          = 3,
+	HECI_CONNECT_STATUS_SUCCESS = 0,
+	HECI_CONNECT_STATUS_CLIENT_NOT_FOUND = 1,
+	HECI_CONNECT_STATUS_ALREADY_EXISTS = 2,
+	HECI_CONNECT_STATUS_REJECTED = 3,
 	HECI_CONNECT_STATUS_INVALID_PARAMETER = 4,
-	HECI_CONNECT_STATUS_INACTIVE_CLIENT   = 5,
+	HECI_CONNECT_STATUS_INACTIVE_CLIENT = 5,
 };
 
 struct hbm_version {
@@ -101,14 +100,14 @@ struct hbm_client_prop_req {
 	uint8_t reserved[2];
 } __packed;
 
-#define CLIENT_DMA_ENABLE	0x80
+#define CLIENT_DMA_ENABLE 0x80
 
 struct hbm_client_properties {
 	struct heci_guid protocol_name; /* heci client protocol ID */
-	uint8_t protocol_version;	/* protocol version */
+	uint8_t protocol_version; /* protocol version */
 	/* max connection from host to client. currently only 1 is allowed */
 	uint8_t max_number_of_connections;
-	uint8_t fixed_address;	/* not yet supported */
+	uint8_t fixed_address; /* not yet supported */
 	uint8_t single_recv_buf; /* not yet supported */
 	uint32_t max_msg_length; /* max payload size */
 	/* not yet supported. [7] enable/disable, [6:0] dma length */
@@ -168,13 +167,13 @@ struct hbm_host_stop_res {
 struct hbm_h2i {
 	uint8_t cmd;
 	union {
-		struct hbm_version_req			ver_req;
-		struct hbm_enum_req			enum_req;
-		struct hbm_client_prop_req		client_prop_req;
-		struct hbm_client_connect_req		client_connect_req;
-		struct hbm_flow_control			flow_ctrl;
-		struct hbm_client_disconnect_req	client_disconnect_req;
-		struct hbm_host_stop_req		host_stop_req;
+		struct hbm_version_req ver_req;
+		struct hbm_enum_req enum_req;
+		struct hbm_client_prop_req client_prop_req;
+		struct hbm_client_connect_req client_connect_req;
+		struct hbm_flow_control flow_ctrl;
+		struct hbm_client_disconnect_req client_disconnect_req;
+		struct hbm_host_stop_req host_stop_req;
 	} data;
 } __packed;
 
@@ -182,13 +181,13 @@ struct hbm_h2i {
 struct hbm_i2h {
 	uint8_t cmd;
 	union {
-		struct hbm_version_res			ver_res;
-		struct hbm_enum_res			enum_res;
-		struct hbm_client_prop_res		client_prop_res;
-		struct hbm_client_connect_res		client_connect_res;
-		struct hbm_flow_control			flow_ctrl;
-		struct hbm_client_disconnect_res	client_disconnect_res;
-		struct hbm_host_stop_res		host_stop_res;
+		struct hbm_version_res ver_res;
+		struct hbm_enum_res enum_res;
+		struct hbm_client_prop_res client_prop_res;
+		struct hbm_client_connect_res client_connect_res;
+		struct hbm_flow_control flow_ctrl;
+		struct hbm_client_disconnect_res client_disconnect_res;
+		struct hbm_host_stop_res host_stop_res;
 	} data;
 } __packed;
 
diff --git a/chip/ish/heci.c b/chip/ish/heci.c
index 309a17c0a1..6f99a486e7 100644
--- a/chip/ish/heci.c
+++ b/chip/ish/heci.c
@@ -1,9 +1,10 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "atomic.h"
+#include "builtin/assert.h"
 #include "compile_time_macros.h"
 #include "console.h"
 #include "hbm.h"
@@ -15,19 +16,19 @@
 #include "util.h"
 
 #define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_LPC, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_LPC, format, ##args)
 
 struct heci_header {
 	uint8_t fw_addr;
 	uint8_t host_addr;
 	uint16_t length; /* [8:0] length, [14:9] reserved, [15] msg_complete */
 } __packed;
-#define HECI_MSG_CMPL_SHIFT		15
-#define HECI_MSG_LENGTH_MASK		0x01FF
-#define HECI_MSG_LENGTH(length)		((length) & HECI_MSG_LENGTH_MASK)
+#define HECI_MSG_CMPL_SHIFT 15
+#define HECI_MSG_LENGTH_MASK 0x01FF
+#define HECI_MSG_LENGTH(length) ((length)&HECI_MSG_LENGTH_MASK)
 #define HECI_MSG_IS_COMPLETED(length) \
-				(!!((length) & (0x01 << HECI_MSG_CMPL_SHIFT)))
+	(!!((length) & (0x01 << HECI_MSG_CMPL_SHIFT)))
 
 BUILD_ASSERT(HECI_IPC_PAYLOAD_SIZE ==
 	     (IPC_MAX_PAYLOAD_SIZE - sizeof(struct heci_header)));
@@ -38,26 +39,26 @@ struct heci_msg {
 } __packed;
 
 /* HECI addresses */
-#define HECI_HBM_ADDRESS		0	/* HECI Bus Message */
-#define HECI_DYN_CLIENT_ADDR_START	0x20	/* Dynamic client start addr */
+#define HECI_HBM_ADDRESS 0 /* HECI Bus Message */
+#define HECI_DYN_CLIENT_ADDR_START 0x20 /* Dynamic client start addr */
 
 /* A fw client has the same value for both handle and fw address */
-#define TO_FW_ADDR(handle)		((uintptr_t)(handle))
-#define TO_HECI_HANDLE(fw_addr)		((heci_handle_t)(uintptr_t)(fw_addr))
+#define TO_FW_ADDR(handle) ((uintptr_t)(handle))
+#define TO_HECI_HANDLE(fw_addr) ((heci_handle_t)(uintptr_t)(fw_addr))
 /* convert client fw address to client context index */
-#define TO_CLIENT_CTX_IDX(fw_addr)	((fw_addr) - HECI_DYN_CLIENT_ADDR_START)
+#define TO_CLIENT_CTX_IDX(fw_addr) ((fw_addr)-HECI_DYN_CLIENT_ADDR_START)
 
 /* should be less than HECI_INVALID_HANDLE - 1 */
 BUILD_ASSERT(HECI_MAX_NUM_OF_CLIENTS < 0x0FE);
 
 struct heci_client_connect {
-	uint8_t is_connected;	/* client is connected to host */
-	uint8_t host_addr;	/* connected host address */
+	uint8_t is_connected; /* client is connected to host */
+	uint8_t host_addr; /* connected host address */
 
 	/* receiving message */
 	uint8_t ignore_rx_msg;
-	uint8_t	rx_msg[HECI_MAX_MSG_SIZE];
-	size_t  rx_msg_length;
+	uint8_t rx_msg[HECI_MAX_MSG_SIZE];
+	size_t rx_msg_length;
 
 	uint32_t flow_ctrl_creds; /* flow control */
 	struct mutex lock; /* protects against 2 writers */
@@ -67,7 +68,7 @@ struct heci_client_connect {
 
 struct heci_client_context {
 	const struct heci_client *client;
-	void *data;	/* client specific data */
+	void *data; /* client specific data */
 
 	struct heci_client_connect connect; /* connection context */
 	struct ss_subsys_device ss_device; /* system state receiver device */
@@ -82,7 +83,7 @@ struct heci_bus_context {
 
 /* declare heci bus */
 struct heci_bus_context heci_bus_ctx = {
-		.ipc_handle = IPC_INVALID_HANDLE,
+	.ipc_handle = IPC_INVALID_HANDLE,
 };
 
 static inline struct heci_client_context *
@@ -118,11 +119,14 @@ static inline int heci_is_valid_handle(const heci_handle_t handle)
 
 /* find heci device that contains this system state device in it */
 #define ss_device_to_heci_client_context(ss_dev) \
-	((struct heci_client_context *)((void *)(ss_dev) - \
-	(void *)(&(((struct heci_client_context *)0)->ss_device))))
-#define client_context_to_handle(cli_ctx) \
-	((heci_handle_t)((uint32_t)((cli_ctx) - &heci_bus_ctx.client_ctxs[0]) \
-	/ sizeof(heci_bus_ctx.client_ctxs[0]) + 1))
+	((struct heci_client_context             \
+		  *)((void *)(ss_dev) -          \
+		     (void *)(&(                 \
+			     ((struct heci_client_context *)0)->ss_device))))
+#define client_context_to_handle(cli_ctx)                                       \
+	((heci_handle_t)((uint32_t)((cli_ctx) - &heci_bus_ctx.client_ctxs[0]) / \
+				 sizeof(heci_bus_ctx.client_ctxs[0]) +          \
+			 1))
 
 /*
  * each heci device registered as system state device which gets
@@ -132,7 +136,7 @@ static inline int heci_is_valid_handle(const heci_handle_t handle)
 static int heci_client_suspend(struct ss_subsys_device *ss_device)
 {
 	struct heci_client_context *cli_ctx =
-			ss_device_to_heci_client_context(ss_device);
+		ss_device_to_heci_client_context(ss_device);
 	heci_handle_t handle = client_context_to_handle(cli_ctx);
 
 	if (cli_ctx->client->cbs->suspend)
@@ -144,7 +148,7 @@ static int heci_client_suspend(struct ss_subsys_device *ss_device)
 static int heci_client_resume(struct ss_subsys_device *ss_device)
 {
 	struct heci_client_context *cli_ctx =
-			ss_device_to_heci_client_context(ss_device);
+		ss_device_to_heci_client_context(ss_device);
 	heci_handle_t handle = client_context_to_handle(cli_ctx);
 
 	if (cli_ctx->client->cbs->resume)
@@ -239,8 +243,8 @@ static int heci_send_heci_msg_timestamp(struct heci_msg *msg,
 				      timestamp);
 
 	if (written != length) {
-		CPRINTF("%s error : len = %d err = %d\n", __func__,
-			(int)length, written);
+		CPRINTF("%s error : len = %d err = %d\n", __func__, (int)length,
+			written);
 		return -EC_ERROR_UNKNOWN;
 	}
 
@@ -381,7 +385,6 @@ int heci_send_msg(const heci_handle_t handle, uint8_t *buf,
 	return heci_send_msg_timestamp(handle, buf, buf_size, NULL);
 }
 
-
 int heci_send_msgs(const heci_handle_t handle,
 		   const struct heci_msg_list *msg_list)
 {
@@ -453,8 +456,8 @@ int heci_send_msgs(const heci_handle_t handle,
 
 			/* no leftovers, send the last msg here */
 			if (msg_sent == total_size) {
-				msg.hdr.length |=
-					(uint16_t)1 << HECI_MSG_CMPL_SHIFT;
+				msg.hdr.length |= (uint16_t)1
+						  << HECI_MSG_CMPL_SHIFT;
 			}
 
 			heci_send_heci_msg(&msg);
@@ -488,7 +491,6 @@ int heci_send_msgs(const heci_handle_t handle,
 	mutex_unlock(&connect->lock);
 
 	return total_size;
-
 }
 
 /* For now, we only support fixed client payload size < IPC payload size */
@@ -535,9 +537,9 @@ static int handle_version_req(struct hbm_version_req *ver_req)
 	return EC_SUCCESS;
 }
 
-#define BITS_PER_BYTE			8
+#define BITS_PER_BYTE 8
 /* get number of bits for one element of "valid_addresses" array */
-#define	BITS_PER_ELEMENT \
+#define BITS_PER_ELEMENT \
 	(sizeof(((struct hbm_enum_res *)0)->valid_addresses[0]) * BITS_PER_BYTE)
 
 static int handle_enum_req(struct hbm_enum_req *enum_req)
@@ -604,11 +606,11 @@ static int handle_client_prop_req(struct hbm_client_prop_req *client_prop_req)
 		client_prop->protocol_name = client->protocol_id;
 		client_prop->protocol_version = client->protocol_ver;
 		client_prop->max_number_of_connections =
-						client->max_n_of_connections;
+			client->max_n_of_connections;
 		client_prop->max_msg_length = client->max_msg_size;
 		client_prop->dma_hdr_len = client->dma_header_length;
-		client_prop->dma_hdr_len |= client->dma_enabled ?
-					    CLIENT_DMA_ENABLE : 0;
+		client_prop->dma_hdr_len |=
+			client->dma_enabled ? CLIENT_DMA_ENABLE : 0;
 	}
 
 	heci_send_heci_msg(&heci_msg);
@@ -642,8 +644,8 @@ static int heci_send_flow_control(uint8_t fw_addr)
 	return EC_SUCCESS;
 }
 
-static int handle_client_connect_req(
-			struct hbm_client_connect_req *client_connect_req)
+static int
+handle_client_connect_req(struct hbm_client_connect_req *client_connect_req)
 {
 	struct hbm_client_connect_res *client_connect_res;
 	struct heci_msg heci_msg;
@@ -663,7 +665,7 @@ static int handle_client_connect_req(
 	client_connect_res->host_addr = client_connect_req->host_addr;
 	if (!heci_is_valid_client_addr(client_connect_req->fw_addr)) {
 		client_connect_res->status =
-					HECI_CONNECT_STATUS_CLIENT_NOT_FOUND;
+			HECI_CONNECT_STATUS_CLIENT_NOT_FOUND;
 	} else if (!client_connect_req->host_addr) {
 		client_connect_res->status =
 			HECI_CONNECT_STATUS_INVALID_PARAMETER;
@@ -671,7 +673,7 @@ static int handle_client_connect_req(
 		connect = heci_get_client_connect(client_connect_req->fw_addr);
 		if (connect->is_connected) {
 			client_connect_res->status =
-					HECI_CONNECT_STATUS_ALREADY_EXISTS;
+				HECI_CONNECT_STATUS_ALREADY_EXISTS;
 		} else {
 			connect->is_connected = 1;
 			connect->host_addr = client_connect_req->host_addr;
@@ -706,7 +708,7 @@ static int handle_flow_control_cmd(struct hbm_flow_control *flow_ctrl)
 	mutex_unlock(&connect->cred_lock);
 
 	if (waiting_task)
-		task_set_event(waiting_task, TASK_EVENT_IPC_READY, 0);
+		task_set_event(waiting_task, TASK_EVENT_IPC_READY);
 
 	return EC_SUCCESS;
 }
@@ -729,8 +731,7 @@ static void heci_handle_client_msg(struct heci_msg *msg, size_t length)
 	connect = &cli_ctx->connect;
 
 	payload_size = HECI_MSG_LENGTH(msg->hdr.length);
-	if (connect->is_connected &&
-	    msg->hdr.host_addr == connect->host_addr) {
+	if (connect->is_connected && msg->hdr.host_addr == connect->host_addr) {
 		if (!connect->ignore_rx_msg &&
 		    connect->rx_msg_length + payload_size > HECI_MAX_MSG_SIZE) {
 			connect->ignore_rx_msg = 1; /* too big. discard */
@@ -760,7 +761,7 @@ static void heci_handle_client_msg(struct heci_msg *msg, size_t length)
 }
 
 static int handle_client_disconnect_req(
-			struct hbm_client_disconnect_req *client_disconnect_req)
+	struct hbm_client_disconnect_req *client_disconnect_req)
 {
 	struct hbm_client_disconnect_res *client_disconnect_res;
 	struct heci_msg heci_msg;
@@ -772,8 +773,9 @@ static int handle_client_disconnect_req(
 
 	CPRINTS("Got HECI disconnect request");
 
-	heci_build_hbm_header(&heci_msg.hdr, sizeof(i2h->cmd) +
-					     sizeof(*client_disconnect_res));
+	heci_build_hbm_header(&heci_msg.hdr,
+			      sizeof(i2h->cmd) +
+				      sizeof(*client_disconnect_res));
 
 	i2h = (struct hbm_i2h *)heci_msg.payload;
 	i2h->cmd = HECI_BUS_MSG_CLIENT_DISCONNECT_RESP;
@@ -789,7 +791,7 @@ static int handle_client_disconnect_req(
 	if (!heci_is_valid_client_addr(fw_addr) ||
 	    !heci_is_client_connected(fw_addr)) {
 		client_disconnect_res->status =
-					HECI_CONNECT_STATUS_CLIENT_NOT_FOUND;
+			HECI_CONNECT_STATUS_CLIENT_NOT_FOUND;
 	} else {
 		connect = heci_get_client_connect(fw_addr);
 		if (connect->host_addr != host_addr) {
@@ -891,8 +893,8 @@ static int is_hbm_validity(struct hbm_h2i *h2i, size_t length)
 	}
 
 	if (valid_msg_len != length) {
-		CPRINTF("invalid cmd(%d) valid : %d, cur : %zd\n",
-			h2i->cmd, valid_msg_len, length);
+		CPRINTF("invalid cmd(%d) valid : %d, cur : %zd\n", h2i->cmd,
+			valid_msg_len, length);
 		/* TODO: invalid cmd. not sure to reply with error ? */
 		return 0;
 	}
@@ -922,7 +924,7 @@ static void heci_handle_hbm(struct hbm_h2i *h2i, size_t length)
 
 	case HECI_BUS_MSG_CLIENT_CONNECT_REQ:
 		handle_client_connect_req(
-					(struct hbm_client_connect_req *)data);
+			(struct hbm_client_connect_req *)data);
 		break;
 
 	case HECI_BUS_MSG_FLOW_CONTROL:
@@ -931,7 +933,7 @@ static void heci_handle_hbm(struct hbm_h2i *h2i, size_t length)
 
 	case HECI_BUS_MSG_CLIENT_DISCONNECT_REQ:
 		handle_client_disconnect_req(
-				(struct hbm_client_disconnect_req *)data);
+			(struct hbm_client_disconnect_req *)data);
 		break;
 
 	case HECI_BUS_MSG_HOST_STOP_REQ:
@@ -991,7 +993,7 @@ static void heci_handle_heci_msg(struct heci_msg *heci_msg, size_t msg_length)
 }
 
 /* event flag for HECI msg */
-#define EVENT_FLAG_BIT_HECI_MSG			TASK_EVENT_CUSTOM_BIT(0)
+#define EVENT_FLAG_BIT_HECI_MSG TASK_EVENT_CUSTOM_BIT(0)
 
 void heci_rx_task(void)
 {
@@ -1017,8 +1019,9 @@ void heci_rx_task(void)
 			continue;
 		}
 
-		if (HECI_MSG_LENGTH(heci_msg.hdr.length) + sizeof(heci_msg.hdr)
-		    == msg_len)
+		if (HECI_MSG_LENGTH(heci_msg.hdr.length) +
+			    sizeof(heci_msg.hdr) ==
+		    msg_len)
 			heci_handle_heci_msg(&heci_msg, msg_len);
 		else
 			CPRINTS("msg len mismatch.. discard..");
diff --git a/chip/ish/heci_client.h b/chip/ish/heci_client.h
index 9dca4bff90..2ba9ea01db 100644
--- a/chip/ish/heci_client.h
+++ b/chip/ish/heci_client.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,26 +6,26 @@
 #ifndef __HECI_CLIENT_H
 #define __HECI_CLIENT_H
 
-#include <stdint.h>
-#include <stddef.h>
-
 #include "hooks.h"
 
-#define HECI_MAX_NUM_OF_CLIENTS			2
+#include <stddef.h>
+#include <stdint.h>
+
+#define HECI_MAX_NUM_OF_CLIENTS 2
 
-#define HECI_MAX_MSG_SIZE			4960
-#define HECI_IPC_PAYLOAD_SIZE   (IPC_MAX_PAYLOAD_SIZE - 4)
-#define HECI_MAX_MSGS				3
+#define HECI_MAX_MSG_SIZE 4960
+#define HECI_IPC_PAYLOAD_SIZE (IPC_MAX_PAYLOAD_SIZE - 4)
+#define HECI_MAX_MSGS 3
 
 enum HECI_ERR {
-	HECI_ERR_TOO_MANY_MSG_ITEMS		= EC_ERROR_INTERNAL_FIRST + 0,
-	HECI_ERR_NO_CRED_FROM_CLIENT_IN_HOST	= EC_ERROR_INTERNAL_FIRST + 1,
-	HECI_ERR_CLIENT_IS_NOT_CONNECTED	= EC_ERROR_INTERNAL_FIRST + 2,
+	HECI_ERR_TOO_MANY_MSG_ITEMS = EC_ERROR_INTERNAL_FIRST + 0,
+	HECI_ERR_NO_CRED_FROM_CLIENT_IN_HOST = EC_ERROR_INTERNAL_FIRST + 1,
+	HECI_ERR_CLIENT_IS_NOT_CONNECTED = EC_ERROR_INTERNAL_FIRST + 2,
 };
 
-typedef void *					heci_handle_t;
+typedef void *heci_handle_t;
 
-#define HECI_INVALID_HANDLE			NULL
+#define HECI_INVALID_HANDLE NULL
 
 struct heci_guid {
 	uint32_t data1;
@@ -57,8 +57,8 @@ struct heci_client {
 	uint32_t max_msg_size;
 	uint8_t protocol_ver;
 	uint8_t max_n_of_connections;
-	uint8_t dma_header_length :7;
-	uint8_t dma_enabled :1;
+	uint8_t dma_header_length : 7;
+	uint8_t dma_enabled : 1;
 
 	const struct heci_client_callbacks *cbs;
 };
@@ -91,7 +91,7 @@ void *heci_get_client_data(const heci_handle_t handle);
 int heci_send_msg(const heci_handle_t handle, uint8_t *buf,
 		  const size_t buf_size);
 int heci_send_msg_timestamp(const heci_handle_t handle, uint8_t *buf,
-		  const size_t buf_size, uint32_t *timestamp);
+			    const size_t buf_size, uint32_t *timestamp);
 /*
  * send client msgs(using list of buffer&size).
  * heci_msg_item with size == 0 is not acceptable.
@@ -102,11 +102,11 @@ int heci_send_msgs(const heci_handle_t handle,
 int heci_send_fixed_client_msg(const uint8_t fw_addr, uint8_t *buf,
 			       const size_t buf_size);
 
-#define HECI_CLIENT_ENTRY(heci_client) \
-	void _heci_entry_##heci_client(void) \
-	{ \
+#define HECI_CLIENT_ENTRY(heci_client)                \
+	void _heci_entry_##heci_client(void)          \
+	{                                             \
 		heci_register_client(&(heci_client)); \
-	} \
+	}                                             \
 	DECLARE_HOOK(HOOK_INIT, _heci_entry_##heci_client, HOOK_PRIO_LAST - 1)
 
 #endif /* __HECI_CLIENT_H */
diff --git a/chip/ish/hid_device.h b/chip/ish/hid_device.h
index 0a32e305af..07d8a77673 100644
--- a/chip/ish/hid_device.h
+++ b/chip/ish/hid_device.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,20 +6,20 @@
 #ifndef __HID_DEVICE_H
 #define __HID_DEVICE_H
 
-#include <stdint.h>
-#include <stddef.h>
-
 #include "hooks.h"
 
-#define HID_SUBSYS_MAX_PAYLOAD_SIZE			4954
+#include <stddef.h>
+#include <stdint.h>
+
+#define HID_SUBSYS_MAX_PAYLOAD_SIZE 4954
 
 enum HID_SUBSYS_ERR {
-	HID_SUBSYS_ERR_NOT_READY		= EC_ERROR_INTERNAL_FIRST + 0,
-	HID_SUBSYS_ERR_TOO_MANY_HID_DEVICES	= EC_ERROR_INTERNAL_FIRST + 1,
+	HID_SUBSYS_ERR_NOT_READY = EC_ERROR_INTERNAL_FIRST + 0,
+	HID_SUBSYS_ERR_TOO_MANY_HID_DEVICES = EC_ERROR_INTERNAL_FIRST + 1,
 };
 
-typedef void *					hid_handle_t;
-#define HID_INVALID_HANDLE			NULL
+typedef void *hid_handle_t;
+#define HID_INVALID_HANDLE NULL
 
 struct hid_callbacks {
 	/*
@@ -73,11 +73,11 @@ int hid_subsys_set_device_data(const hid_handle_t handle, void *data);
 /* retrieve HID device specific data */
 void *hid_subsys_get_device_data(const hid_handle_t handle);
 
-#define HID_DEVICE_ENTRY(hid_dev) \
-	void _hid_dev_entry_##hid_dev(void) \
-	{ \
+#define HID_DEVICE_ENTRY(hid_dev)                       \
+	void _hid_dev_entry_##hid_dev(void)             \
+	{                                               \
 		hid_subsys_register_device(&(hid_dev)); \
-	} \
+	}                                               \
 	DECLARE_HOOK(HOOK_INIT, _hid_dev_entry_##hid_dev, HOOK_PRIO_LAST - 2)
 
 #endif /* __HID_DEVICE_H */
diff --git a/chip/ish/hid_subsys.c b/chip/ish/hid_subsys.c
index bd3f331fdc..555af9046a 100644
--- a/chip/ish/hid_subsys.c
+++ b/chip/ish/hid_subsys.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,8 @@
 
 #ifdef HID_SUBSYS_DEBUG
 #define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_LPC, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_LPC, format, ##args)
 #else
 #define CPUTS(outstr)
 #define CPRINTS(format, args...)
@@ -21,10 +21,15 @@
 
 #define __packed __attribute__((packed))
 
-#define HECI_CLIENT_HID_GUID { 0x33AECD58, 0xB679, 0x4E54,\
-			 { 0x9B, 0xD9, 0xA0, 0x4D, 0x34, 0xF0, 0xC2, 0x26 } }
+#define HECI_CLIENT_HID_GUID                                           \
+	{                                                              \
+		0x33AECD58, 0xB679, 0x4E54,                            \
+		{                                                      \
+			0x9B, 0xD9, 0xA0, 0x4D, 0x34, 0xF0, 0xC2, 0x26 \
+		}                                                      \
+	}
 
-#define HID_SUBSYS_MAX_HID_DEVICES			3
+#define HID_SUBSYS_MAX_HID_DEVICES 3
 
 /*
  * the following enum values and data structures with __packed are used for
@@ -55,13 +60,13 @@ struct hid_device_info {
 	uint16_t vid;
 } __packed;
 
-struct hid_enum_payload	{
+struct hid_enum_payload {
 	uint8_t num_of_hid_devices;
 	struct hid_device_info dev_info[0];
 } __packed;
 
-#define COMMAND_MASK			0x7F
-#define RESPONSE_FLAG			0x80
+#define COMMAND_MASK 0x7F
+#define RESPONSE_FLAG 0x80
 struct hid_msg_hdr {
 	uint8_t command; /* bit 7 is used to indicate "response" */
 	uint8_t device_id;
@@ -94,8 +99,8 @@ static struct hid_subsystem hid_subsys_ctx = {
 	.heci_handle = HECI_INVALID_HANDLE,
 };
 
-#define handle_to_dev_id(_handle)	((uintptr_t)(_handle))
-#define dev_id_to_handle(_dev_id)	((hid_handle_t)(uintptr_t)(_dev_id))
+#define handle_to_dev_id(_handle) ((uintptr_t)(_handle))
+#define dev_id_to_handle(_dev_id) ((hid_handle_t)(uintptr_t)(_dev_id))
 
 static inline hid_handle_t device_index_to_handle(int device_index)
 {
@@ -108,8 +113,8 @@ static inline int is_valid_handle(hid_handle_t handle)
 	       (uintptr_t)handle <= hid_subsys_ctx.num_of_hid_devices;
 }
 
-static inline
-struct hid_subsys_hid_device *handle_to_hid_device(hid_handle_t handle)
+static inline struct hid_subsys_hid_device *
+handle_to_hid_device(hid_handle_t handle)
 {
 	if (!is_valid_handle(handle))
 		return NULL;
@@ -117,7 +122,6 @@ struct hid_subsys_hid_device *handle_to_hid_device(hid_handle_t handle)
 	return &hid_subsys_ctx.hid_devices[(uintptr_t)handle - 1];
 }
 
-
 hid_handle_t hid_subsys_register_device(const struct hid_device *dev_info)
 {
 	struct hid_subsys_hid_device *hid_device;
@@ -156,7 +160,7 @@ int hid_subsys_send_input_report(const hid_handle_t handle, uint8_t *buf,
 				 const size_t buf_size)
 {
 	struct hid_subsys_hid_device *hid_device;
-	struct hid_msg_hdr hid_msg_hdr = {0};
+	struct hid_msg_hdr hid_msg_hdr = { 0 };
 	struct heci_msg_item msg_item[2];
 	struct heci_msg_list msg_list;
 
@@ -253,7 +257,7 @@ static int handle_hid_device_msg(struct hid_msg *hid_msg)
 	 * re-use hid_msg from host for reply.
 	 */
 	switch (hid_msg->hdr.command & COMMAND_MASK) {
-	case  HID_GET_HID_DESCRIPTOR:
+	case HID_GET_HID_DESCRIPTOR:
 		if (cbs->get_hid_descriptor)
 			ret = cbs->get_hid_descriptor(handle, payload,
 						      buf_size);
@@ -277,10 +281,8 @@ static int handle_hid_device_msg(struct hid_msg *hid_msg)
 
 	case HID_SET_FEATURE_REPORT:
 		if (cbs->set_feature_report) {
-			ret = cbs->set_feature_report(handle,
-						      payload[0],
-						      payload,
-						      payload_size);
+			ret = cbs->set_feature_report(handle, payload[0],
+						      payload, payload_size);
 			/*
 			 * if no error, reply only with the report id.
 			 * re-use the first byte of payload
@@ -293,8 +295,8 @@ static int handle_hid_device_msg(struct hid_msg *hid_msg)
 		break;
 	case HID_GET_INPUT_REPORT:
 		if (cbs->get_input_report)
-			ret = cbs->get_input_report(handle, payload[0],
-						    payload, buf_size);
+			ret = cbs->get_input_report(handle, payload[0], payload,
+						    buf_size);
 
 		break;
 
@@ -331,21 +333,21 @@ static int handle_hid_subsys_msg(struct hid_msg *hid_msg)
 	struct hid_enum_payload *enum_payload;
 
 	switch (hid_msg->hdr.command & COMMAND_MASK) {
-	case  HID_DM_ENUM_DEVICES:
+	case HID_DM_ENUM_DEVICES:
 		enum_payload = (struct hid_enum_payload *)hid_msg->payload;
 
 		for (i = 0; i < hid_subsys_ctx.num_of_hid_devices; i++) {
 			enum_payload->dev_info[i] =
-					hid_subsys_ctx.hid_devices[i].info;
+				hid_subsys_ctx.hid_devices[i].info;
 		}
 
 		enum_payload->num_of_hid_devices =
-					hid_subsys_ctx.num_of_hid_devices;
+			hid_subsys_ctx.num_of_hid_devices;
 
 		/* reply payload size */
 		size = sizeof(enum_payload->num_of_hid_devices);
 		size += enum_payload->num_of_hid_devices *
-					sizeof(enum_payload->dev_info[0]);
+			sizeof(enum_payload->dev_info[0]);
 
 		break;
 
@@ -408,7 +410,7 @@ static int hid_subsys_resume(const heci_handle_t heci_handle)
 	for (i = 0; i < hid_subsys_ctx.num_of_hid_devices; i++) {
 		if (hid_subsys_ctx.hid_devices[i].cbs->resume)
 			ret |= hid_subsys_ctx.hid_devices[i].cbs->resume(
-					device_index_to_handle(i));
+				device_index_to_handle(i));
 	}
 
 	return ret;
@@ -422,7 +424,7 @@ static int hid_subsys_suspend(const heci_handle_t heci_handle)
 	for (i = hid_subsys_ctx.num_of_hid_devices - 1; i >= 0; i--) {
 		if (hid_subsys_ctx.hid_devices[i].cbs->suspend)
 			ret |= hid_subsys_ctx.hid_devices[i].cbs->suspend(
-					device_index_to_handle(i));
+				device_index_to_handle(i));
 	}
 
 	return ret;
diff --git a/chip/ish/host_command_heci.c b/chip/ish/host_command_heci.c
index 2fcab44b8b..fe82f94bda 100644
--- a/chip/ish/host_command_heci.c
+++ b/chip/ish/host_command_heci.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,11 +13,16 @@
 #include "util.h"
 
 #define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_LPC, format, ## args)
-
-#define HECI_CLIENT_CROS_EC_ISH_GUID { 0x7b7154d0, 0x56f4, 0x4bdc,\
-			 { 0xb0, 0xd8, 0x9e, 0x7c, 0xda, 0xe0, 0xd6, 0xa0 } }
+#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_LPC, format, ##args)
+
+#define HECI_CLIENT_CROS_EC_ISH_GUID                                   \
+	{                                                              \
+		0x7b7154d0, 0x56f4, 0x4bdc,                            \
+		{                                                      \
+			0xb0, 0xd8, 0x9e, 0x7c, 0xda, 0xe0, 0xd6, 0xa0 \
+		}                                                      \
+	}
 
 /* Handle for all heci cros_ec interactions */
 static heci_handle_t heci_cros_ec_handle = HECI_INVALID_HANDLE;
@@ -33,13 +38,25 @@ static heci_handle_t heci_cros_ec_handle = HECI_INVALID_HANDLE;
 struct cros_ec_ishtp_msg_hdr {
 	uint8_t channel;
 	uint8_t status;
-	uint8_t id;	/* Pairs up request and responses */
+	uint8_t id; /* Pairs up request and responses */
 	uint8_t reserved;
 } __ec_align4;
 
 #define CROS_EC_ISHTP_MSG_HDR_SIZE sizeof(struct cros_ec_ishtp_msg_hdr)
+
+/*
+ * Increase response_buffer size
+ * some host command response messages use bigger space; so increase
+ * the buffer size on par with EC, which is 256 bytes in total.
+ * The size has to meet
+ * HECI_CROS_EC_RESPONSE_BUF_SIZE >= CROS_EC_ISHTP_MSG_HDR_SIZE + 256.
+ * Here 260 bytes is chosen.
+ */
+#define HECI_CROS_EC_RESPONSE_BUF_SIZE 260
 #define HECI_CROS_EC_RESPONSE_MAX \
-	(HECI_IPC_PAYLOAD_SIZE - CROS_EC_ISHTP_MSG_HDR_SIZE)
+	(HECI_CROS_EC_RESPONSE_BUF_SIZE - CROS_EC_ISHTP_MSG_HDR_SIZE)
+BUILD_ASSERT(HECI_CROS_EC_RESPONSE_BUF_SIZE >=
+	     CROS_EC_ISHTP_MSG_HDR_SIZE + 256);
 
 struct cros_ec_ishtp_msg {
 	struct cros_ec_ishtp_msg_hdr hdr;
@@ -51,7 +68,7 @@ enum heci_cros_ec_channel {
 	CROS_MKBP_EVENT = 2, /* initiated from EC */
 };
 
-static uint8_t response_buffer[IPC_MAX_PAYLOAD_SIZE] __aligned(4);
+static uint8_t response_buffer[HECI_CROS_EC_RESPONSE_BUF_SIZE] __aligned(4);
 static struct host_packet heci_packet;
 
 int heci_send_mkbp_event(uint32_t *timestamp)
@@ -88,10 +105,11 @@ static void heci_send_hostcmd_response(struct host_packet *pkt)
 }
 
 static void cros_ec_ishtp_subsys_new_msg_received(const heci_handle_t handle,
-					uint8_t *msg, const size_t msg_size)
+						  uint8_t *msg,
+						  const size_t msg_size)
 {
-	struct cros_ec_ishtp_msg *in = (void *) msg;
-	struct cros_ec_ishtp_msg *out = (void *) response_buffer;
+	struct cros_ec_ishtp_msg *in = (void *)msg;
+	struct cros_ec_ishtp_msg *out = (void *)response_buffer;
 
 	if (in->hdr.channel != CROS_EC_COMMAND) {
 		CPRINTS("Unknown HECI packet 0x%02x", in->hdr.channel);
@@ -113,7 +131,8 @@ static void cros_ec_ishtp_subsys_new_msg_received(const heci_handle_t handle,
 	heci_packet.response_size = 0;
 
 	heci_packet.driver_result = EC_RES_SUCCESS;
-	host_packet_receive(&heci_packet);
+	if (IS_ENABLED(HAS_TASK_HOSTCMD))
+		host_packet_receive(&heci_packet);
 }
 
 /*
@@ -137,10 +156,10 @@ static enum ec_status heci_get_protocol_info(struct host_cmd_handler_args *args)
 
 	args->response_size = sizeof(*r);
 
-	return EC_SUCCESS;
+	return EC_RES_SUCCESS;
 }
 DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, heci_get_protocol_info,
-EC_VER_MASK(0));
+		     EC_VER_MASK(0));
 
 static int cros_ec_ishtp_subsys_initialize(const heci_handle_t heci_handle)
 {
diff --git a/chip/ish/hpet.h b/chip/ish/hpet.h
index 06738fafb1..7438f42949 100644
--- a/chip/ish/hpet.h
+++ b/chip/ish/hpet.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,61 +10,58 @@
 
 /* ISH HPET config and timer registers */
 
-#define TIMER0_CONF_CAP_REG		0x100
-#define TIMER0_COMP_VAL_REG		0x108
-
+#define TIMER0_CONF_CAP_REG 0x100
+#define TIMER0_COMP_VAL_REG 0x108
 
 /* HPET_GENERAL_CONFIG settings  */
-#define HPET_GENERAL_CONFIG		REG32(ISH_HPET_BASE + 0x10)
-#define HPET_ENABLE_CNF		BIT(0)
-#define HPET_LEGACY_RT_CNF	BIT(1)
+#define HPET_GENERAL_CONFIG REG32(ISH_HPET_BASE + 0x10)
+#define HPET_ENABLE_CNF BIT(0)
+#define HPET_LEGACY_RT_CNF BIT(1)
 
 /* Interrupt status acknowledge register */
-#define HPET_INTR_CLEAR		REG32(ISH_HPET_BASE + 0x20)
+#define HPET_INTR_CLEAR REG32(ISH_HPET_BASE + 0x20)
 
 /* Main counter register. 64-bit */
-#define HPET_MAIN_COUNTER_64	REG64(ISH_HPET_BASE + 0xF0)
-#define HPET_MAIN_COUNTER_64_LO	REG32(ISH_HPET_BASE + 0xF0)
-#define HPET_MAIN_COUNTER_64_HI	REG32(ISH_HPET_BASE + 0xF4)
+#define HPET_MAIN_COUNTER_64 REG64(ISH_HPET_BASE + 0xF0)
+#define HPET_MAIN_COUNTER_64_LO REG32(ISH_HPET_BASE + 0xF0)
+#define HPET_MAIN_COUNTER_64_HI REG32(ISH_HPET_BASE + 0xF4)
 
 /* HPET Timer 0/1/2 configuration*/
-#define HPET_TIMER_CONF_CAP(x)	REG32(ISH_HPET_BASE + 0x100 + ((x) * 0x20))
-#define HPET_Tn_INT_TYPE_CNF		BIT(1)
-#define HPET_Tn_INT_ENB_CNF		BIT(2)
-#define HPET_Tn_TYPE_CNF		BIT(3)
-#define HPET_Tn_VAL_SET_CNF		BIT(6)
-#define HPET_Tn_32MODE_CNF		BIT(8)
-#define HPET_Tn_INT_ROUTE_CNF_SHIFT	0x9
-#define HPET_Tn_INT_ROUTE_CNF_MASK	(0x1f << 9)
+#define HPET_TIMER_CONF_CAP(x) REG32(ISH_HPET_BASE + 0x100 + ((x)*0x20))
+#define HPET_Tn_INT_TYPE_CNF BIT(1)
+#define HPET_Tn_INT_ENB_CNF BIT(2)
+#define HPET_Tn_TYPE_CNF BIT(3)
+#define HPET_Tn_VAL_SET_CNF BIT(6)
+#define HPET_Tn_32MODE_CNF BIT(8)
+#define HPET_Tn_INT_ROUTE_CNF_SHIFT 0x9
+#define HPET_Tn_INT_ROUTE_CNF_MASK (0x1f << 9)
 
 /*
  * HPET Timer 0/1/2 comparator values. 1/2 are always 32-bit. 0 can be
  * configured as 64-bit.
  */
-#define HPET_TIMER_COMP(x)	REG32(ISH_HPET_BASE + 0x108 + ((x) * 0x20))
-#define HPET_TIMER0_COMP_64	REG64(ISH_HPET_BASE + 0x108)
+#define HPET_TIMER_COMP(x) REG32(ISH_HPET_BASE + 0x108 + ((x)*0x20))
+#define HPET_TIMER0_COMP_64 REG64(ISH_HPET_BASE + 0x108)
 
 /* ISH 4/5: Special status register
  * Use this register to see HPET timer are settled after a write.
  */
-#define HPET_CTRL_STATUS		REG32(ISH_HPET_BASE + 0x160)
-#define HPET_INT_STATUS_SETTLING	BIT(1)
-#define HPET_MAIN_COUNTER_SETTLING	(BIT(2) | BIT(3))
-#define HPET_T0_CAP_SETTLING		BIT(4)
-#define HPET_T1_CAP_SETTLING		BIT(5)
-#define HPET_T0_CMP_SETTLING		(BIT(7) | BIT(8))
-#define HPET_T1_CMP_SETTLING		BIT(9)
-#define HPET_MAIN_COUNTER_VALID		BIT(13)
-#define HPET_T1_SETTLING		(HPET_T1_CAP_SETTLING | \
-					 HPET_T1_CMP_SETTLING)
-#define HPET_T0_SETTLING		(HPET_T0_CAP_SETTLING | \
-					 HPET_T0_CMP_SETTLING)
-#define HPET_ANY_SETTLING		(BIT(12) - 1)
+#define HPET_CTRL_STATUS REG32(ISH_HPET_BASE + 0x160)
+#define HPET_INT_STATUS_SETTLING BIT(1)
+#define HPET_MAIN_COUNTER_SETTLING (BIT(2) | BIT(3))
+#define HPET_T0_CAP_SETTLING BIT(4)
+#define HPET_T1_CAP_SETTLING BIT(5)
+#define HPET_T0_CMP_SETTLING (BIT(7) | BIT(8))
+#define HPET_T1_CMP_SETTLING BIT(9)
+#define HPET_MAIN_COUNTER_VALID BIT(13)
+#define HPET_T1_SETTLING (HPET_T1_CAP_SETTLING | HPET_T1_CMP_SETTLING)
+#define HPET_T0_SETTLING (HPET_T0_CAP_SETTLING | HPET_T0_CMP_SETTLING)
+#define HPET_ANY_SETTLING (BIT(12) - 1)
 
 #if defined(CHIP_FAMILY_ISH3)
-#define ISH_HPET_CLK_FREQ		12000000	/* 12 MHz clock */
+#define ISH_HPET_CLK_FREQ 12000000 /* 12 MHz clock */
 #elif defined(CHIP_FAMILY_ISH4) || defined(CHIP_FAMILY_ISH5)
-#define ISH_HPET_CLK_FREQ		32768		/* 32.768 KHz clock */
+#define ISH_HPET_CLK_FREQ 32768 /* 32.768 KHz clock */
 #endif
 
 #endif /* __CROS_EC_HPET_H */
diff --git a/chip/ish/hwtimer.c b/chip/ish/hwtimer.c
index 1259dae7f4..40c3de67a8 100644
--- a/chip/ish/hwtimer.c
+++ b/chip/ish/hwtimer.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,14 +8,14 @@
 #include "console.h"
 #include "hpet.h"
 #include "hwtimer.h"
-#include "timer.h"
 #include "registers.h"
 #include "task.h"
+#include "timer.h"
 #include "util.h"
 
 #define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ##args)
 
 static uint32_t last_deadline;
 
@@ -37,7 +37,7 @@ static uint32_t last_deadline;
 /* Scaling helper methods for different ISH chip variants */
 #ifdef CHIP_FAMILY_ISH3
 #define CLOCK_FACTOR 12
-BUILD_ASSERT(CLOCK_FACTOR * SECOND == ISH_HPET_CLK_FREQ);
+BUILD_ASSERT(CLOCK_FACTOR *SECOND == ISH_HPET_CLK_FREQ);
 
 static inline uint64_t scale_us2ticks(uint64_t us)
 {
@@ -239,8 +239,7 @@ int __hw_clock_source_init64(uint64_t start_t)
 
 	/* Timer 1 - IRQ routing */
 	timer1_config &= ~HPET_Tn_INT_ROUTE_CNF_MASK;
-	timer1_config |= (ISH_HPET_TIMER1_IRQ <<
-			  HPET_Tn_INT_ROUTE_CNF_SHIFT);
+	timer1_config |= (ISH_HPET_TIMER1_IRQ << HPET_Tn_INT_ROUTE_CNF_SHIFT);
 
 	/* Level triggered interrupt */
 	timer1_config |= HPET_Tn_INT_TYPE_CNF;
diff --git a/chip/ish/i2c.c b/chip/ish/i2c.c
index 3978011033..1da65b0b15 100644
--- a/chip/ish/i2c.c
+++ b/chip/ish/i2c.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,78 +6,66 @@
 /* I2C port module for ISH */
 
 #include "common.h"
-#include "console.h"
 #include "config_chip.h"
+#include "console.h"
 #include "gpio.h"
 #include "hooks.h"
+#include "hwtimer.h"
 #include "i2c.h"
-#include "registers.h"
 #include "ish_i2c.h"
+#include "registers.h"
 #include "task.h"
 #include "timer.h"
-#include "hwtimer.h"
 #include "util.h"
 
 #define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args)
 
 /*25MHz, 50MHz, 100MHz, 120MHz, 40MHz, 20MHz, 37MHz*/
-static uint16_t default_hcnt_scl_100[] = {
-	4000, 4420, 4920, 4400, 4000, 4000, 4300
-};
+static uint16_t default_hcnt_scl_100[] = { 4000, 4420, 4920, 4400,
+					   4000, 4000, 4300 };
 
-static uint16_t default_lcnt_scl_100[] = {
-	4720, 5180, 4990, 5333, 4700, 5200, 4950
-};
+static uint16_t default_lcnt_scl_100[] = { 4720, 5180, 4990, 5333,
+					   4700, 5200, 4950 };
 
-static uint16_t default_hcnt_scl_400[] = {
-	600, 820, 1120, 800, 600, 600, 450
-};
+static uint16_t default_hcnt_scl_400[] = { 600, 820, 1120, 800, 600, 600, 450 };
 
-static uint16_t default_lcnt_scl_400[] = {
-	1320, 1380, 1300, 1550, 1300, 1200, 1250
-};
+static uint16_t default_lcnt_scl_400[] = { 1320, 1380, 1300, 1550,
+					   1300, 1200, 1250 };
 
-static uint16_t default_hcnt_scl_1000[] = {
-	260, 260, 260, 305, 260, 260, 260
-};
+static uint16_t default_hcnt_scl_1000[] = { 260, 260, 260, 305, 260, 260, 260 };
 
-static uint16_t default_lcnt_scl_1000[] = {
-	500, 500, 500, 525, 500, 500, 500
-};
+static uint16_t default_lcnt_scl_1000[] = { 500, 500, 500, 525, 500, 500, 500 };
 
 static uint16_t default_hcnt_scl_hs[] = { 160, 300, 160, 166, 175, 150, 162 };
 static uint16_t default_lcnt_scl_hs[] = { 320, 340, 320, 325, 325, 300, 297 };
 
-
 #ifdef CHIP_VARIANT_ISH5P4
 /* Change to I2C_FREQ_100 in real silicon platform */
-static uint8_t bus_freq[ISH_I2C_PORT_COUNT] = {
-	I2C_FREQ_100, I2C_FREQ_100, I2C_FREQ_100
-};
+static uint8_t bus_freq[ISH_I2C_PORT_COUNT] = { I2C_FREQ_100, I2C_FREQ_100,
+						I2C_FREQ_100 };
 #else
-static uint8_t bus_freq[ISH_I2C_PORT_COUNT] = {
-	I2C_FREQ_120, I2C_FREQ_120, I2C_FREQ_120
-};
+static uint8_t bus_freq[ISH_I2C_PORT_COUNT] = { I2C_FREQ_120, I2C_FREQ_120,
+						I2C_FREQ_120 };
 #endif
 
 static struct i2c_context i2c_ctxs[ISH_I2C_PORT_COUNT] = {
 	{
 		.bus = 0,
-		.base = (uint32_t *) ISH_I2C0_BASE,
+		.base = (uint32_t *)ISH_I2C0_BASE,
 		.speed = I2C_SPEED_400KHZ,
 		.int_pin = ISH_I2C0_IRQ,
 	},
 	{
 		.bus = 1,
-		.base = (uint32_t *) ISH_I2C1_BASE,
+		.base = (uint32_t *)ISH_I2C1_BASE,
 		.speed = I2C_SPEED_400KHZ,
 		.int_pin = ISH_I2C1_IRQ,
 	},
 	{
 		.bus = 2,
-		.base = (uint32_t *) ISH_I2C2_BASE,
+		.base = (uint32_t *)ISH_I2C2_BASE,
 		.speed = I2C_SPEED_400KHZ,
 		.int_pin = ISH_I2C2_IRQ,
 	},
@@ -104,22 +92,20 @@ static struct i2c_bus_info board_config[ISH_I2C_PORT_COUNT] = {
 		.fast_speed.sda_hold = DEFAULT_SDA_HOLD_FAST,
 		.fast_plus_speed.sda_hold = DEFAULT_SDA_HOLD_FAST_PLUS,
 		.high_speed.sda_hold = DEFAULT_SDA_HOLD_HIGH,
-	 },
+	},
 };
 
-static inline void i2c_mmio_write(uint32_t *base, uint8_t offset,
-				  uint32_t data)
+static inline void i2c_mmio_write(uint32_t *base, uint8_t offset, uint32_t data)
 {
-	REG32((uint32_t) ((uint8_t *)base + offset)) = data;
+	REG32((uint32_t)((uint8_t *)base + offset)) = data;
 }
 
 static inline uint32_t i2c_mmio_read(uint32_t *base, uint8_t offset)
 {
-	return REG32((uint32_t) ((uint8_t *)base + offset));
+	return REG32((uint32_t)((uint8_t *)base + offset));
 }
 
-static inline uint8_t i2c_read_byte(uint32_t *addr, uint8_t reg,
-					  uint8_t offset)
+static inline uint8_t i2c_read_byte(uint32_t *addr, uint8_t reg, uint8_t offset)
 {
 	uint32_t ret = i2c_mmio_read(addr, reg) >> offset;
 
@@ -129,7 +115,6 @@ static inline uint8_t i2c_read_byte(uint32_t *addr, uint8_t reg,
 static void i2c_intr_switch(uint32_t *base, int mode)
 {
 	switch (mode) {
-
 	case ENABLE_WRITE_INT:
 		i2c_mmio_write(base, IC_INTR_MASK, IC_INTR_WRITE_MASK_VAL);
 		break;
@@ -157,8 +142,8 @@ static void i2c_intr_switch(uint32_t *base, int mode)
 	}
 }
 
-static void i2c_init_transaction(struct i2c_context *ctx,
-				 uint16_t slave_addr, uint8_t flags)
+static void i2c_init_transaction(struct i2c_context *ctx, uint16_t addr,
+				 uint8_t flags)
 {
 	uint32_t con_value;
 	uint32_t *base = ctx->base;
@@ -169,64 +154,64 @@ static void i2c_init_transaction(struct i2c_context *ctx,
 	i2c_intr_switch(base, DISABLE_INT);
 
 	i2c_mmio_write(base, IC_ENABLE, IC_ENABLE_DISABLE);
-	i2c_mmio_write(base, IC_TAR, (slave_addr << IC_TAR_OFFSET) |
-			TAR_SPECIAL_VAL | IC_10BITADDR_MASTER_VAL);
+	i2c_mmio_write(base, IC_TAR,
+		       (addr << IC_TAR_OFFSET) | TAR_SPECIAL_VAL |
+			       IC_10BITADDR_MASTER_VAL);
 
 	/* set Clock SCL Count */
 	switch (ctx->speed) {
-
 	case I2C_SPEED_100KHZ:
 		i2c_mmio_write(base, IC_SS_SCL_HCNT,
-				NS_2_COUNTERS(bus_info->std_speed.hcnt,
+			       NS_2_COUNTERS(bus_info->std_speed.hcnt,
 					     clk_in_val));
 		i2c_mmio_write(base, IC_SS_SCL_LCNT,
-				NS_2_COUNTERS(bus_info->std_speed.lcnt,
+			       NS_2_COUNTERS(bus_info->std_speed.lcnt,
 					     clk_in_val));
 		i2c_mmio_write(base, IC_SDA_HOLD,
-				NS_2_COUNTERS(bus_info->std_speed.sda_hold,
+			       NS_2_COUNTERS(bus_info->std_speed.sda_hold,
 					     clk_in_val));
 		break;
 
 	case I2C_SPEED_400KHZ:
 		i2c_mmio_write(base, IC_FS_SCL_HCNT,
-				NS_2_COUNTERS(bus_info->fast_speed.hcnt,
+			       NS_2_COUNTERS(bus_info->fast_speed.hcnt,
 					     clk_in_val));
 		i2c_mmio_write(base, IC_FS_SCL_LCNT,
-				NS_2_COUNTERS(bus_info->fast_speed.lcnt,
+			       NS_2_COUNTERS(bus_info->fast_speed.lcnt,
 					     clk_in_val));
 		i2c_mmio_write(base, IC_SDA_HOLD,
-				NS_2_COUNTERS(bus_info->fast_speed.sda_hold,
+			       NS_2_COUNTERS(bus_info->fast_speed.sda_hold,
 					     clk_in_val));
 		break;
 
 	case I2C_SPEED_1MHZ:
 		i2c_mmio_write(base, IC_FS_SCL_HCNT,
-				NS_2_COUNTERS(bus_info->fast_plus_speed.hcnt,
+			       NS_2_COUNTERS(bus_info->fast_plus_speed.hcnt,
 					     clk_in_val));
 		i2c_mmio_write(base, IC_FS_SCL_LCNT,
-				NS_2_COUNTERS(bus_info->fast_plus_speed.lcnt,
+			       NS_2_COUNTERS(bus_info->fast_plus_speed.lcnt,
 					     clk_in_val));
 		i2c_mmio_write(base, IC_SDA_HOLD,
-				NS_2_COUNTERS(bus_info->fast_plus_speed.sda_hold,
+			       NS_2_COUNTERS(bus_info->fast_plus_speed.sda_hold,
 					     clk_in_val));
 		break;
 
 	case I2C_SPEED_3M4HZ:
 		i2c_mmio_write(base, IC_HS_SCL_HCNT,
-				NS_2_COUNTERS(bus_info->high_speed.hcnt,
+			       NS_2_COUNTERS(bus_info->high_speed.hcnt,
 					     clk_in_val));
 		i2c_mmio_write(base, IC_HS_SCL_LCNT,
-				NS_2_COUNTERS(bus_info->high_speed.lcnt,
+			       NS_2_COUNTERS(bus_info->high_speed.lcnt,
 					     clk_in_val));
 		i2c_mmio_write(base, IC_SDA_HOLD,
-				NS_2_COUNTERS(bus_info->high_speed.sda_hold,
+			       NS_2_COUNTERS(bus_info->high_speed.sda_hold,
 					     clk_in_val));
 
 		i2c_mmio_write(base, IC_FS_SCL_HCNT,
-				NS_2_COUNTERS(bus_info->fast_speed.hcnt,
+			       NS_2_COUNTERS(bus_info->fast_speed.hcnt,
 					     clk_in_val));
 		i2c_mmio_write(base, IC_FS_SCL_LCNT,
-				NS_2_COUNTERS(bus_info->fast_speed.lcnt,
+			       NS_2_COUNTERS(bus_info->fast_speed.lcnt,
 					     clk_in_val));
 		break;
 
@@ -248,15 +233,13 @@ static void i2c_init_transaction(struct i2c_context *ctx,
 	i2c_mmio_write(base, IC_ENABLE, IC_ENABLE_ENABLE);
 }
 
-static void i2c_write_buffer(uint32_t *base, uint8_t len,
-			     const uint8_t *buffer, ssize_t *cur_index,
-			     ssize_t total_len)
+static void i2c_write_buffer(uint32_t *base, uint8_t len, const uint8_t *buffer,
+			     ssize_t *cur_index, ssize_t total_len)
 {
 	int i;
 	uint16_t out;
 
 	for (i = 0; i < len; i++) {
-
 		++(*cur_index);
 		out = (buffer[i] << DATA_CMD_DAT_OFFSET) | DATA_CMD_WRITE_VAL;
 
@@ -270,7 +253,7 @@ static void i2c_write_buffer(uint32_t *base, uint8_t len,
 }
 
 static void i2c_write_read_commands(uint32_t *base, uint8_t len, int more_data,
-					unsigned restart_flag)
+				    unsigned int restart_flag)
 {
 	/* this routine just set RX FIFO's control bit(s),
 	 * READ command or RESTART */
@@ -293,16 +276,15 @@ static void i2c_write_read_commands(uint32_t *base, uint8_t len, int more_data,
 	}
 }
 
-int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags,
-		  const uint8_t *out, int out_size,
-		  uint8_t *in, int in_size, int flags)
+int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out,
+		  int out_size, uint8_t *in, int in_size, int flags)
 {
 	int i;
 	ssize_t total_len;
 	uint64_t expire_ts;
 	struct i2c_context *ctx;
 	ssize_t curr_index = 0;
-	uint16_t addr = I2C_GET_ADDR(slave_addr_flags);
+	uint16_t addr = I2C_STRIP_FLAGS(addr_flags);
 	int begin_indx;
 	uint8_t repeat_start = 0;
 
@@ -333,8 +315,8 @@ int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags,
 
 	/* Write W data */
 	if (out_size)
-		i2c_write_buffer(ctx->base, out_size, out,
-				&curr_index, total_len);
+		i2c_write_buffer(ctx->base, out_size, out, &curr_index,
+				 total_len);
 
 	/* Wait here until Tx is completed so that FIFO becomes empty.
 	 * This is optimized for smaller Tx data size.
@@ -344,10 +326,8 @@ int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags,
 	 * */
 	expire_ts = __hw_clock_source_read() + I2C_TX_FLUSH_TIMEOUT_USEC;
 	if (in_size > (ISH_I2C_FIFO_SIZE - out_size)) {
-
 		while ((i2c_mmio_read(ctx->base, IC_STATUS) &
 			BIT(IC_STATUS_TFE)) == 0) {
-
 			if (__hw_clock_source_read() >= expire_ts) {
 				ctx->error_flag = 1;
 				break;
@@ -358,7 +338,7 @@ int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags,
 
 	begin_indx = 0;
 	while (in_size) {
-		int rd_size;  /* read size for on i2c transaction */
+		int rd_size; /* read size for on i2c transaction */
 
 		/*
 		 * check if in_size > ISH_I2C_FIFO_SIZE, then try to read
@@ -383,11 +363,11 @@ int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags,
 		 * set R commands bit, start to read
 		 */
 		i2c_write_read_commands(ctx->base, rd_size, in_size,
-				(begin_indx == 0) && (repeat_start != 0));
-
+					(begin_indx == 0) &&
+						(repeat_start != 0));
 
-		/* need timeout in case no ACK from slave */
-		task_wait_event_mask(TASK_EVENT_I2C_IDLE, 2*MSEC);
+		/* need timeout in case no ACK from peripheral */
+		task_wait_event_mask(TASK_EVENT_I2C_IDLE, 2 * MSEC);
 
 		if (ctx->interrupts & M_TX_ABRT) {
 			ctx->error_flag = 1;
@@ -396,8 +376,7 @@ int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags,
 
 		/* read data */
 		for (i = begin_indx; i < begin_indx + rd_size; i++)
-			in[i] = i2c_read_byte(ctx->base,
-					IC_DATA_CMD, 0);
+			in[i] = i2c_read_byte(ctx->base, IC_DATA_CMD, 0);
 
 		begin_indx += rd_size;
 	} /* while (in_size) */
@@ -411,7 +390,6 @@ int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags,
 	while ((i2c_mmio_read(ctx->base, IC_STATUS) &
 		(BIT(IC_STATUS_MASTER_ACTIVITY) | BIT(IC_STATUS_TFE))) !=
 	       BIT(IC_STATUS_TFE)) {
-
 		if (__hw_clock_source_read() >= expire_ts) {
 			ctx->error_flag = 1;
 			break;
@@ -432,12 +410,12 @@ static void i2c_interrupt_handler(struct i2c_context *ctx)
 	uint32_t raw_intr;
 
 	if (IS_ENABLED(INTR_DEBUG))
-		raw_intr = 0x0000FFFF & i2c_mmio_read(ctx->base,
-						      IC_RAW_INTR_STAT);
+		raw_intr = 0x0000FFFF &
+			   i2c_mmio_read(ctx->base, IC_RAW_INTR_STAT);
 
 	/* check interrupts */
 	ctx->interrupts = i2c_mmio_read(ctx->base, IC_INTR_STAT);
-	ctx->reason = (uint16_t) i2c_mmio_read(ctx->base, IC_TX_ABRT_SOURCE);
+	ctx->reason = (uint16_t)i2c_mmio_read(ctx->base, IC_TX_ABRT_SOURCE);
 
 	if (IS_ENABLED(INTR_DEBUG))
 		CPRINTS("INTR_STAT = 0x%04x, TX_ABORT_SRC = 0x%04x, "
@@ -446,7 +424,7 @@ static void i2c_interrupt_handler(struct i2c_context *ctx)
 
 	/* disable interrupts */
 	i2c_intr_switch(ctx->base, DISABLE_INT);
-	task_set_event(ctx->wait_task_id, TASK_EVENT_I2C_IDLE, 0);
+	task_set_event(ctx->wait_task_id, TASK_EVENT_I2C_IDLE);
 }
 
 static void i2c_isr_bus0(void)
@@ -467,9 +445,8 @@ static void i2c_isr_bus2(void)
 }
 DECLARE_IRQ(ISH_I2C2_IRQ, i2c_isr_bus2);
 
-static void  i2c_config_speed(struct i2c_context *ctx, int kbps)
+static void i2c_config_speed(struct i2c_context *ctx, int kbps)
 {
-
 	if (kbps > 1000)
 		ctx->speed = I2C_SPEED_3M4HZ;
 	else if (kbps > 400)
@@ -478,7 +455,6 @@ static void  i2c_config_speed(struct i2c_context *ctx, int kbps)
 		ctx->speed = I2C_SPEED_400KHZ;
 	else
 		ctx->speed = I2C_SPEED_100KHZ;
-
 }
 
 static void i2c_init_hardware(struct i2c_context *ctx)
@@ -486,8 +462,8 @@ static void i2c_init_hardware(struct i2c_context *ctx)
 	static const uint8_t speed_val_arr[] = {
 		[I2C_SPEED_100KHZ] = STD_SPEED_VAL,
 		[I2C_SPEED_400KHZ] = FAST_SPEED_VAL,
-		[I2C_SPEED_1MHZ]   = FAST_SPEED_VAL,
-		[I2C_SPEED_3M4HZ]  = HIGH_SPEED_VAL,
+		[I2C_SPEED_1MHZ] = FAST_SPEED_VAL,
+		[I2C_SPEED_3M4HZ] = HIGH_SPEED_VAL,
 	};
 
 	uint32_t *base = ctx->base;
@@ -495,19 +471,20 @@ static void i2c_init_hardware(struct i2c_context *ctx)
 	/* disable interrupts */
 	i2c_intr_switch(base, DISABLE_INT);
 	i2c_mmio_write(base, IC_ENABLE, IC_ENABLE_DISABLE);
-	i2c_mmio_write(base, IC_CON, (MASTER_MODE_VAL
-				| speed_val_arr[ctx->speed]
-				| IC_RESTART_EN_VAL
-				| IC_SLAVE_DISABLE_VAL));
+	i2c_mmio_write(base, IC_CON,
+		       (MASTER_MODE_VAL | speed_val_arr[ctx->speed] |
+			IC_RESTART_EN_VAL | IC_SLAVE_DISABLE_VAL));
 
 	i2c_mmio_write(base, IC_FS_SPKLEN, spkln[bus_freq[ctx->bus]]);
 	i2c_mmio_write(base, IC_HS_SPKLEN, spkln[bus_freq[ctx->bus]]);
 
 	/* get RX_FIFO and TX_FIFO depth */
-	ctx->max_rx_depth = i2c_read_byte(base, IC_COMP_PARAM_1,
-					RX_BUFFER_DEPTH_OFFSET) + 1;
-	ctx->max_tx_depth = i2c_read_byte(base, IC_COMP_PARAM_1,
-					TX_BUFFER_DEPTH_OFFSET) + 1;
+	ctx->max_rx_depth =
+		i2c_read_byte(base, IC_COMP_PARAM_1, RX_BUFFER_DEPTH_OFFSET) +
+		1;
+	ctx->max_tx_depth =
+		i2c_read_byte(base, IC_COMP_PARAM_1, TX_BUFFER_DEPTH_OFFSET) +
+		1;
 }
 
 static void i2c_initial_board_config(struct i2c_context *ctx)
diff --git a/chip/ish/ipc_heci.c b/chip/ish/ipc_heci.c
index 5271aa3a91..8ce0a258e1 100644
--- a/chip/ish/ipc_heci.c
+++ b/chip/ish/ipc_heci.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,19 +23,20 @@
  *  - Doorbell Clear Status Register (DB CSR)
  */
 
-#include "registers.h"
+#include "builtin/assert.h"
 #include "console.h"
-#include "task.h"
-#include "util.h"
+#include "hooks.h"
+#include "hwtimer.h"
 #include "ipc_heci.h"
 #include "ish_fwst.h"
 #include "queue.h"
-#include "hooks.h"
-#include "hwtimer.h"
+#include "registers.h"
+#include "task.h"
+#include "util.h"
 
 #define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_LPC, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_LPC, format, ##args)
 
 /*
  * comminucation protocol is defined in Linux Documentation
@@ -44,57 +45,55 @@
 
 /* MNG commands */
 /* The ipc_mng_task manages IPC link. It should be the highest priority */
-#define MNG_RX_CMPL_ENABLE              0
-#define MNG_RX_CMPL_DISABLE             1
-#define MNG_RX_CMPL_INDICATION          2
-#define MNG_RESET_NOTIFY                3
-#define MNG_RESET_NOTIFY_ACK            4
-#define MNG_SYNC_FW_CLOCK               5
-#define MNG_ILLEGAL_CMD                 0xFF
+#define MNG_RX_CMPL_ENABLE 0
+#define MNG_RX_CMPL_DISABLE 1
+#define MNG_RX_CMPL_INDICATION 2
+#define MNG_RESET_NOTIFY 3
+#define MNG_RESET_NOTIFY_ACK 4
+#define MNG_SYNC_FW_CLOCK 5
+#define MNG_ILLEGAL_CMD 0xFF
 
 /* Doorbell */
-#define IPC_DB_MSG_LENGTH_FIELD		0x3FF
-#define IPC_DB_MSG_LENGTH_SHIFT		0
+#define IPC_DB_MSG_LENGTH_FIELD 0x3FF
+#define IPC_DB_MSG_LENGTH_SHIFT 0
 #define IPC_DB_MSG_LENGTH_MASK \
-	  (IPC_DB_MSG_LENGTH_FIELD << IPC_DB_MSG_LENGTH_SHIFT)
+	(IPC_DB_MSG_LENGTH_FIELD << IPC_DB_MSG_LENGTH_SHIFT)
 
-#define IPC_DB_PROTOCOL_FIELD		0x0F
-#define IPC_DB_PROTOCOL_SHIFT		10
+#define IPC_DB_PROTOCOL_FIELD 0x0F
+#define IPC_DB_PROTOCOL_SHIFT 10
 #define IPC_DB_PROTOCOL_MASK (IPC_DB_PROTOCOL_FIELD << IPC_DB_PROTOCOL_SHIFT)
 
-#define IPC_DB_CMD_FIELD		0x0F
-#define IPC_DB_CMD_SHIFT		16
-#define IPC_DB_CMD_MASK			(IPC_DB_CMD_FIELD << IPC_DB_CMD_SHIFT)
+#define IPC_DB_CMD_FIELD 0x0F
+#define IPC_DB_CMD_SHIFT 16
+#define IPC_DB_CMD_MASK (IPC_DB_CMD_FIELD << IPC_DB_CMD_SHIFT)
 
-#define IPC_DB_BUSY_SHIFT		31
-#define IPC_DB_BUSY_MASK		BIT(IPC_DB_BUSY_SHIFT)
+#define IPC_DB_BUSY_SHIFT 31
+#define IPC_DB_BUSY_MASK BIT(IPC_DB_BUSY_SHIFT)
 
 #define IPC_DB_MSG_LENGTH(drbl) \
-	  (((drbl) & IPC_DB_MSG_LENGTH_MASK) >> IPC_DB_MSG_LENGTH_SHIFT)
+	(((drbl)&IPC_DB_MSG_LENGTH_MASK) >> IPC_DB_MSG_LENGTH_SHIFT)
 #define IPC_DB_PROTOCOL(drbl) \
-	  (((drbl) & IPC_DB_PROTOCOL_MASK) >> IPC_DB_PROTOCOL_SHIFT)
-#define IPC_DB_CMD(drbl) \
-	  (((drbl) & IPC_DB_CMD_MASK) >> IPC_DB_CMD_SHIFT)
-#define IPC_DB_BUSY(drbl)		(!!((drbl) & IPC_DB_BUSY_MASK))
+	(((drbl)&IPC_DB_PROTOCOL_MASK) >> IPC_DB_PROTOCOL_SHIFT)
+#define IPC_DB_CMD(drbl) (((drbl)&IPC_DB_CMD_MASK) >> IPC_DB_CMD_SHIFT)
+#define IPC_DB_BUSY(drbl) (!!((drbl)&IPC_DB_BUSY_MASK))
 
-#define IPC_BUILD_DB(length, proto, cmd, busy) \
+#define IPC_BUILD_DB(length, proto, cmd, busy)                         \
 	(((busy) << IPC_DB_BUSY_SHIFT) | ((cmd) << IPC_DB_CMD_SHIFT) | \
-	((proto) << IPC_DB_PROTOCOL_SHIFT) | \
-		((length) << IPC_DB_MSG_LENGTH_SHIFT))
+	 ((proto) << IPC_DB_PROTOCOL_SHIFT) |                          \
+	 ((length) << IPC_DB_MSG_LENGTH_SHIFT))
 
 #define IPC_BUILD_MNG_DB(cmd, length) \
 	IPC_BUILD_DB(length, IPC_PROTOCOL_MNG, cmd, 1)
 
-#define IPC_BUILD_HECI_DB(length) \
-	IPC_BUILD_DB(length, IPC_PROTOCOL_HECI, 0, 1)
+#define IPC_BUILD_HECI_DB(length) IPC_BUILD_DB(length, IPC_PROTOCOL_HECI, 0, 1)
 
-#define IPC_MSG_MAX_SIZE		0x80
-#define IPC_HOST_MSG_QUEUE_SIZE		8
-#define IPC_PMC_MSG_QUEUE_SIZE		2
+#define IPC_MSG_MAX_SIZE 0x80
+#define IPC_HOST_MSG_QUEUE_SIZE 8
+#define IPC_PMC_MSG_QUEUE_SIZE 2
 
-#define IPC_HANDLE_PEER_ID_SHIFT	4
-#define IPC_HANDLE_PROTOCOL_SHIFT	0
-#define IPC_HANDLE_PROTOCOL_MASK	0x0F
+#define IPC_HANDLE_PEER_ID_SHIFT 4
+#define IPC_HANDLE_PROTOCOL_SHIFT 0
+#define IPC_HANDLE_PROTOCOL_MASK 0x0F
 #define IPC_BUILD_HANDLE(peer_id, protocol) \
 	((ipc_handle_t)(((peer_id) << IPC_HANDLE_PEER_ID_SHIFT) | (protocol)))
 #define IPC_BUILD_MNG_HANDLE(peer_id) \
@@ -103,10 +102,10 @@
 #define IPC_HANDLE_PEER_ID(handle) \
 	((uint32_t)(handle) >> IPC_HANDLE_PEER_ID_SHIFT)
 #define IPC_HANDLE_PROTOCOL(handle) \
-	((uint32_t)(handle) & IPC_HANDLE_PROTOCOL_MASK)
-#define IPC_IS_VALID_HANDLE(handle) \
+	((uint32_t)(handle)&IPC_HANDLE_PROTOCOL_MASK)
+#define IPC_IS_VALID_HANDLE(handle)                      \
 	(IPC_HANDLE_PEER_ID(handle) < IPC_PEERS_COUNT && \
-	    IPC_HANDLE_PROTOCOL(handle) < IPC_PROTOCOL_COUNT)
+	 IPC_HANDLE_PROTOCOL(handle) < IPC_PROTOCOL_COUNT)
 
 struct ipc_msg {
 	uint32_t drbl;
@@ -191,21 +190,20 @@ static inline void ipc_disable_pimr_db_interrupt(const struct ipc_if_ctx *ctx)
 	IPC_PIMR &= ~ctx->pimr_2ish_bit;
 }
 
-static inline void ipc_enable_pimr_clearing_interrupt(
-						const struct ipc_if_ctx *ctx)
+static inline void
+ipc_enable_pimr_clearing_interrupt(const struct ipc_if_ctx *ctx)
 {
 	IPC_PIMR |= ctx->pimr_2host_clearing_bit;
 }
 
-static inline void ipc_disable_pimr_clearing_interrupt(
-						const struct ipc_if_ctx *ctx)
+static inline void
+ipc_disable_pimr_clearing_interrupt(const struct ipc_if_ctx *ctx)
 {
 	IPC_PIMR &= ~ctx->pimr_2host_clearing_bit;
 }
 
 static void write_payload_and_ring_drbl(const struct ipc_if_ctx *ctx,
-					uint32_t drbl,
-					const uint8_t *payload,
+					uint32_t drbl, const uint8_t *payload,
 					size_t payload_size)
 {
 	memcpy((void *)(ctx->out_msg_reg), payload, payload_size);
@@ -280,7 +278,7 @@ static int ipc_send_reset_notify(const ipc_handle_t handle)
 
 static int ipc_send_cmpl_indication(struct ipc_if_ctx *ctx)
 {
-	struct ipc_msg msg;
+	struct ipc_msg msg = { 0 };
 
 	msg.drbl = IPC_BUILD_MNG_DB(MNG_RX_CMPL_INDICATION, 0);
 	ipc_write_raw(ctx, msg.drbl, msg.payload, IPC_DB_MSG_LENGTH(msg.drbl));
@@ -289,8 +287,8 @@ static int ipc_send_cmpl_indication(struct ipc_if_ctx *ctx)
 }
 
 static int ipc_get_protocol_data(const struct ipc_if_ctx *ctx,
-				 const uint32_t protocol,
-				 uint8_t *buf, const size_t buf_size)
+				 const uint32_t protocol, uint8_t *buf,
+				 const size_t buf_size)
 {
 	int len = 0, payload_size;
 	uint8_t *src = NULL, *dest = NULL;
@@ -325,9 +323,8 @@ static int ipc_get_protocol_data(const struct ipc_if_ctx *ctx,
 	}
 
 	if (IS_ENABLED(IPC_HECI_DEBUG))
-		CPRINTF("ipc p=%d, db=0x%0x, payload_size=%d\n",
-			protocol, drbl_val,
-			IPC_DB_MSG_LENGTH(drbl_val));
+		CPRINTF("ipc p=%d, db=0x%0x, payload_size=%d\n", protocol,
+			drbl_val, IPC_DB_MSG_LENGTH(drbl_val));
 
 	switch (protocol) {
 	case IPC_PROTOCOL_HECI:
@@ -340,7 +337,7 @@ static int ipc_get_protocol_data(const struct ipc_if_ctx *ctx,
 		msg->drbl = drbl_val;
 		dest = msg->payload;
 		break;
-	default :
+	default:
 		break;
 	}
 
@@ -377,7 +374,7 @@ static void handle_msg_recv_interrupt(const uint32_t peer_id)
 	if (!invalid_msg) {
 		/* send event to task */
 		task_set_event(ctx->msg_events[protocol].task_id,
-			       ctx->msg_events[protocol].event, 0);
+			       ctx->msg_events[protocol].event);
 	} else {
 		CPRINTS("discard msg (%d) : %d", protocol, invalid_msg);
 
@@ -544,13 +541,11 @@ int ipc_write_timestamp(const ipc_handle_t handle, const void *buf,
 }
 
 ipc_handle_t ipc_open(const enum ipc_peer_id peer_id,
-		      const enum ipc_protocol protocol,
-		      const uint32_t event)
+		      const enum ipc_protocol protocol, const uint32_t event)
 {
 	struct ipc_if_ctx *ctx;
 
-	if (protocol >= IPC_PROTOCOL_COUNT ||
-	    peer_id >= IPC_PEERS_COUNT)
+	if (protocol >= IPC_PROTOCOL_COUNT || peer_id >= IPC_PEERS_COUNT)
 		return IPC_INVALID_HANDLE;
 
 	ctx = ipc_get_if_ctx(peer_id);
@@ -564,9 +559,9 @@ ipc_handle_t ipc_open(const enum ipc_peer_id peer_id,
 	ctx->msg_events[protocol].enabled = 1;
 	ctx->msg_events[protocol].event = event;
 
-	 /* For HECI protocol, set HECI UP status when IPC link is ready */
-	if (peer_id == IPC_PEER_ID_HOST &&
-	    protocol == IPC_PROTOCOL_HECI && ish_fwst_is_ilup_set())
+	/* For HECI protocol, set HECI UP status when IPC link is ready */
+	if (peer_id == IPC_PEER_ID_HOST && protocol == IPC_PROTOCOL_HECI &&
+	    ish_fwst_is_ilup_set())
 		ish_fwst_set_hup();
 
 	if (ctx->initialized == 0) {
@@ -686,7 +681,7 @@ int ipc_read(const ipc_handle_t handle, void *buf, const size_t buf_size,
 }
 
 /* event flag for MNG msg */
-#define EVENT_FLAG_BIT_MNG_MSG			TASK_EVENT_CUSTOM_BIT(0)
+#define EVENT_FLAG_BIT_MNG_MSG TASK_EVENT_CUSTOM_BIT(0)
 
 /*
  * This task handles MNG messages
diff --git a/chip/ish/ipc_heci.h b/chip/ish/ipc_heci.h
index 183e6a2c6b..96b08f9c4a 100644
--- a/chip/ish/ipc_heci.h
+++ b/chip/ish/ipc_heci.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,17 +7,19 @@
 #ifndef __IPC_HECI_H
 #define __IPC_HECI_H
 
+#include <stddef.h>
+
 enum IPC_ERR {
-	IPC_ERR_IPC_IS_NOT_READY	= EC_ERROR_INTERNAL_FIRST + 0,
-	IPC_ERR_TOO_SMALL_BUFFER	= EC_ERROR_INTERNAL_FIRST + 1,
-	IPC_ERR_TX_QUEUE_FULL		= EC_ERROR_INTERNAL_FIRST + 2,
-	IPC_ERR_INVALID_TASK		= EC_ERROR_INTERNAL_FIRST + 3,
-	IPC_ERR_MSG_NOT_AVAILABLE	= EC_ERROR_INTERNAL_FIRST + 4,
-	IPC_ERR_INVALID_MSG		= EC_ERROR_INTERNAL_FIRST + 5,
+	IPC_ERR_IPC_IS_NOT_READY = EC_ERROR_INTERNAL_FIRST + 0,
+	IPC_ERR_TOO_SMALL_BUFFER = EC_ERROR_INTERNAL_FIRST + 1,
+	IPC_ERR_TX_QUEUE_FULL = EC_ERROR_INTERNAL_FIRST + 2,
+	IPC_ERR_INVALID_TASK = EC_ERROR_INTERNAL_FIRST + 3,
+	IPC_ERR_MSG_NOT_AVAILABLE = EC_ERROR_INTERNAL_FIRST + 4,
+	IPC_ERR_INVALID_MSG = EC_ERROR_INTERNAL_FIRST + 5,
 };
 
 enum ipc_peer_id {
-	IPC_PEER_ID_HOST	= 0, /* x64 host */
+	IPC_PEER_ID_HOST = 0, /* x64 host */
 #if 0 /* other peers are not implemented yet */
 	IPC_PEER_ID_PMC		= 1, /* Power Management Controller */
 	IPC_PEER_ID_CSME	= 2, /* Converged Security Management Engine */
@@ -33,11 +35,11 @@ enum ipc_peer_id {
 BUILD_ASSERT(IPC_PEERS_COUNT <= 0x0F);
 
 enum ipc_protocol {
-	IPC_PROTOCOL_BOOT = 0,	/* Not supported */
-	IPC_PROTOCOL_HECI,	/* Host Embedded Controller Interface */
-	IPC_PROTOCOL_MCTP,	/* not supported */
-	IPC_PROTOCOL_MNG,	/* Management protocol */
-	IPC_PROTOCOL_ECP,	/* EC Protocol. not supported */
+	IPC_PROTOCOL_BOOT = 0, /* Not supported */
+	IPC_PROTOCOL_HECI, /* Host Embedded Controller Interface */
+	IPC_PROTOCOL_MCTP, /* not supported */
+	IPC_PROTOCOL_MNG, /* Management protocol */
+	IPC_PROTOCOL_ECP, /* EC Protocol. not supported */
 	IPC_PROTOCOL_COUNT
 };
 /*
@@ -46,10 +48,10 @@ enum ipc_protocol {
  */
 BUILD_ASSERT(IPC_PROTOCOL_COUNT <= 0x0F);
 
-typedef void *				ipc_handle_t;
+typedef void *ipc_handle_t;
 
-#define IPC_MAX_PAYLOAD_SIZE		128
-#define IPC_INVALID_HANDLE		NULL
+#define IPC_MAX_PAYLOAD_SIZE 128
+#define IPC_INVALID_HANDLE NULL
 
 /*
  * Open ipc channel
@@ -61,8 +63,7 @@ typedef void *				ipc_handle_t;
  * @return		ipc handle or IPC_INVALID_HANDLE if there's error
  */
 ipc_handle_t ipc_open(const enum ipc_peer_id peer_id,
-		      const enum ipc_protocol protocol,
-		      const uint32_t event);
+		      const enum ipc_protocol protocol, const uint32_t event);
 void ipc_close(const ipc_handle_t handle);
 
 /*
@@ -74,10 +75,10 @@ void ipc_close(const ipc_handle_t handle);
  *			if > 0, wait for the specified microsecond duration time
  */
 int ipc_read(const ipc_handle_t handle, void *buf, const size_t buf_size,
-             int timeout_us);
+	     int timeout_us);
 
 /* Write message to ipc channel. */
 int ipc_write_timestamp(const ipc_handle_t handle, const void *buf,
-	      const size_t buf_size, uint32_t *timestamp);
+			const size_t buf_size, uint32_t *timestamp);
 
 #endif /* __IPC_HECI_H */
diff --git a/chip/ish/ish_dma.h b/chip/ish/ish_dma.h
index 2c76c7d319..89d6cb7342 100644
--- a/chip/ish/ish_dma.h
+++ b/chip/ish/ish_dma.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,6 +27,47 @@
 
 #define PAGE_SIZE 4096
 
+static inline uint32_t interrupt_lock(void)
+{
+	uint32_t eflags = 0;
+
+	__asm__ volatile("pushfl;" /* save eflag value */
+			 "popl  %0;"
+			 "cli;"
+			 : "=r"(eflags)); /* shut off interrupts */
+	return eflags;
+}
+
+static inline void interrupt_unlock(uint32_t eflags)
+{
+	__asm__ volatile("pushl  %0;" /* restore elfag values */
+			 "popfl;"
+			 :
+			 : "r"(eflags));
+}
+
+static inline int dma_poll(uint32_t addr, uint32_t expected, uint32_t mask)
+{
+	int retval = -1;
+	uint32_t counter = 0;
+
+	/*
+	 * The timeout is approximately 2.2 seconds according to
+	 * value of UINT32_MAX, 120MHZ ISH clock frequency and
+	 * instruction count which is around 4.
+	 */
+	while (counter < (UINT32_MAX / 64)) {
+		/* test condition */
+		if ((REG32(addr) & mask) == expected) {
+			retval = DMA_RC_OK;
+			break;
+		}
+		counter++;
+	}
+
+	return retval;
+}
+
 /**
  * SRAM: ISH local static ram
  * UMA: Protected system DRAM region dedicated for ISH
diff --git a/chip/ish/ish_fwst.h b/chip/ish/ish_fwst.h
index c114db3241..999546ca34 100644
--- a/chip/ish/ish_fwst.h
+++ b/chip/ish/ish_fwst.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,84 +17,84 @@
  * IPC link is up(ready)
  * IPC can be used by other protocols
  */
-#define IPC_ISH_FWSTS_ILUP_FIELD		0x01
-#define IPC_ISH_FWSTS_ILUP_SHIFT		0
-#define IPC_ISH_FWSTS_ILUP_MASK	\
-	  (IPC_ISH_FWSTS_ILUP_FIELD << IPC_ISH_FWSTS_ILUP_SHIFT)
+#define IPC_ISH_FWSTS_ILUP_FIELD 0x01
+#define IPC_ISH_FWSTS_ILUP_SHIFT 0
+#define IPC_ISH_FWSTS_ILUP_MASK \
+	(IPC_ISH_FWSTS_ILUP_FIELD << IPC_ISH_FWSTS_ILUP_SHIFT)
 
 /*
  * HECI layer is up(ready)
  */
-#define IPC_ISH_FWSTS_HUP_FIELD			0x01
-#define IPC_ISH_FWSTS_HUP_SHIFT			1
+#define IPC_ISH_FWSTS_HUP_FIELD 0x01
+#define IPC_ISH_FWSTS_HUP_SHIFT 1
 #define IPC_ISH_FWSTS_HUP_MASK \
-	  (IPC_ISH_FWSTS_HUP_FIELD << IPC_ISH_FWSTS_HUP_SHIFT)
+	(IPC_ISH_FWSTS_HUP_FIELD << IPC_ISH_FWSTS_HUP_SHIFT)
 
 /*
  * ISH FW reason reason
  */
-#define IPC_ISH_FWSTS_FAIL_REASON_FIELD		0x0F
-#define IPC_ISH_FWSTS_FAIL_REASON_SHIFT		2
+#define IPC_ISH_FWSTS_FAIL_REASON_FIELD 0x0F
+#define IPC_ISH_FWSTS_FAIL_REASON_SHIFT 2
 #define IPC_ISH_FWSTS_FAIL_REASON_MASK \
-	  (IPC_ISH_FWSTS_FAIL_REASON_FIELD << IPC_ISH_FWSTS_FAIL_REASON_SHIFT)
+	(IPC_ISH_FWSTS_FAIL_REASON_FIELD << IPC_ISH_FWSTS_FAIL_REASON_SHIFT)
 
 /*
  * ISH FW reset ID
  */
-#define IPC_ISH_FWSTS_RESET_ID_FIELD		0x0F
-#define IPC_ISH_FWSTS_RESET_ID_SHIFT		8
+#define IPC_ISH_FWSTS_RESET_ID_FIELD 0x0F
+#define IPC_ISH_FWSTS_RESET_ID_SHIFT 8
 #define IPC_ISH_FWSTS_RESET_ID_MASK \
-	  (IPC_ISH_FWSTS_RESET_ID_FIELD << IPC_ISH_FWSTS_RESET_ID_SHIFT)
+	(IPC_ISH_FWSTS_RESET_ID_FIELD << IPC_ISH_FWSTS_RESET_ID_SHIFT)
 
 /*
  * ISH FW status type
  */
 enum {
-	FWSTS_AFTER_RESET               = 0,
-	FWSTS_WAIT_FOR_HOST             = 4,
-	FWSTS_START_KERNEL_DMA          = 5,
-	FWSTS_FW_IS_RUNNING             = 7,
-	FWSTS_SENSOR_APP_LOADED         = 8,
-	FWSTS_SENSOR_APP_RUNNING        = 15
+	FWSTS_AFTER_RESET = 0,
+	FWSTS_WAIT_FOR_HOST = 4,
+	FWSTS_START_KERNEL_DMA = 5,
+	FWSTS_FW_IS_RUNNING = 7,
+	FWSTS_SENSOR_APP_LOADED = 8,
+	FWSTS_SENSOR_APP_RUNNING = 15
 };
 
 /*
  * General ISH FW status
  */
-#define IPC_ISH_FWSTS_FW_STATUS_FIELD		0x0F
-#define IPC_ISH_FWSTS_FW_STATUS_SHIFT		12
+#define IPC_ISH_FWSTS_FW_STATUS_FIELD 0x0F
+#define IPC_ISH_FWSTS_FW_STATUS_SHIFT 12
 #define IPC_ISH_FWSTS_FW_STATUS_MASK \
-	  (IPC_ISH_FWSTS_FW_STATUS_FIELD << IPC_ISH_FWSTS_FW_STATUS_SHIFT)
+	(IPC_ISH_FWSTS_FW_STATUS_FIELD << IPC_ISH_FWSTS_FW_STATUS_SHIFT)
 
-#define IPC_ISH_FWSTS_DMA0_IN_USE_FIELD		0x01
-#define IPC_ISH_FWSTS_DMA0_IN_USE_SHIFT		16
+#define IPC_ISH_FWSTS_DMA0_IN_USE_FIELD 0x01
+#define IPC_ISH_FWSTS_DMA0_IN_USE_SHIFT 16
 #define IPC_ISH_FWSTS_DMA0_IN_USE_MASK \
-	  (IPC_ISH_FWSTS_DMA0_IN_USE_FIELD << IPC_ISH_FWSTS_DMA0_IN_USE_SHIFT)
+	(IPC_ISH_FWSTS_DMA0_IN_USE_FIELD << IPC_ISH_FWSTS_DMA0_IN_USE_SHIFT)
 
-#define IPC_ISH_FWSTS_DMA1_IN_USE_FIELD		0x01
-#define IPC_ISH_FWSTS_DMA1_IN_USE_SHIFT		17
+#define IPC_ISH_FWSTS_DMA1_IN_USE_FIELD 0x01
+#define IPC_ISH_FWSTS_DMA1_IN_USE_SHIFT 17
 #define IPC_ISH_FWSTS_DMA1_IN_USE_MASK \
-	  (IPC_ISH_FWSTS_DMA1_IN_USE_FIELD << IPC_ISH_FWSTS_DMA1_IN_USE_SHIFT)
+	(IPC_ISH_FWSTS_DMA1_IN_USE_FIELD << IPC_ISH_FWSTS_DMA1_IN_USE_SHIFT)
 
-#define IPC_ISH_FWSTS_DMA2_IN_USE_FIELD		0x01
-#define IPC_ISH_FWSTS_DMA2_IN_USE_SHIFT		18
+#define IPC_ISH_FWSTS_DMA2_IN_USE_FIELD 0x01
+#define IPC_ISH_FWSTS_DMA2_IN_USE_SHIFT 18
 #define IPC_ISH_FWSTS_DMA2_IN_USE_MASK \
-	  (IPC_ISH_FWSTS_DMA2_IN_USE_FIELD << IPC_ISH_FWSTS_DMA2_IN_USE_SHIFT)
+	(IPC_ISH_FWSTS_DMA2_IN_USE_FIELD << IPC_ISH_FWSTS_DMA2_IN_USE_SHIFT)
 
-#define IPC_ISH_FWSTS_DMA3_IN_USE_FIELD		0x01
-#define IPC_ISH_FWSTS_DMA3_IN_USE_SHIFT		19
+#define IPC_ISH_FWSTS_DMA3_IN_USE_FIELD 0x01
+#define IPC_ISH_FWSTS_DMA3_IN_USE_SHIFT 19
 #define IPC_ISH_FWSTS_DMA3_IN_USE_MASK \
-	  (IPC_ISH_FWSTS_DMA3_IN_USE_FIELD << IPC_ISH_FWSTS_DMA3_IN_USE_SHIFT)
+	(IPC_ISH_FWSTS_DMA3_IN_USE_FIELD << IPC_ISH_FWSTS_DMA3_IN_USE_SHIFT)
 
-#define IPC_ISH_FWSTS_POWER_STATE_FIELD		0x0F
-#define IPC_ISH_FWSTS_POWER_STATE_SHIFT		20
+#define IPC_ISH_FWSTS_POWER_STATE_FIELD 0x0F
+#define IPC_ISH_FWSTS_POWER_STATE_SHIFT 20
 #define IPC_ISH_FWSTS_POWER_STATE_MASK \
-	  (IPC_ISH_FWSTS_POWER_STATE_FIELD << IPC_ISH_FWSTS_POWER_STATE_SHIFT)
+	(IPC_ISH_FWSTS_POWER_STATE_FIELD << IPC_ISH_FWSTS_POWER_STATE_SHIFT)
 
-#define IPC_ISH_FWSTS_AON_CHECK_FIELD		0x07
-#define IPC_ISH_FWSTS_AON_CHECK_SHIFT		24
+#define IPC_ISH_FWSTS_AON_CHECK_FIELD 0x07
+#define IPC_ISH_FWSTS_AON_CHECK_SHIFT 24
 #define IPC_ISH_FWSTS_AON_CHECK_MASK \
-	  (IPC_ISH_FWSTS_AON_CHECK_FIELD << IPC_ISH_FWSTS_AON_CHECK_SHIFT)
+	(IPC_ISH_FWSTS_AON_CHECK_FIELD << IPC_ISH_FWSTS_AON_CHECK_SHIFT)
 
 /* get ISH FW status register */
 static inline uint32_t ish_fwst_get(void)
@@ -105,7 +105,7 @@ static inline uint32_t ish_fwst_get(void)
 /* set IPC link up */
 static inline void ish_fwst_set_ilup(void)
 {
-	IPC_ISH_FWSTS |= (1<<IPC_ISH_FWSTS_ILUP_SHIFT);
+	IPC_ISH_FWSTS |= (1 << IPC_ISH_FWSTS_ILUP_SHIFT);
 }
 
 /* clear IPC link up */
@@ -123,7 +123,7 @@ static inline int ish_fwst_is_ilup_set(void)
 /* set HECI up */
 static inline void ish_fwst_set_hup(void)
 {
-	IPC_ISH_FWSTS |= (1<<IPC_ISH_FWSTS_HUP_SHIFT);
+	IPC_ISH_FWSTS |= (1 << IPC_ISH_FWSTS_HUP_SHIFT);
 }
 
 /* clear HECI up */
@@ -144,14 +144,14 @@ static inline void ish_fwst_set_fail_reason(uint32_t val)
 	uint32_t fwst = IPC_ISH_FWSTS;
 
 	IPC_ISH_FWSTS = (fwst & ~IPC_ISH_FWSTS_FAIL_REASON_MASK) |
-		(val << IPC_ISH_FWSTS_FAIL_REASON_SHIFT);
+			(val << IPC_ISH_FWSTS_FAIL_REASON_SHIFT);
 }
 
 /* get fw failure reason */
 static inline uint32_t ish_fwst_get_fail_reason(void)
 {
-	return (IPC_ISH_FWSTS & IPC_ISH_FWSTS_FAIL_REASON_MASK)
-		>> IPC_ISH_FWSTS_FAIL_REASON_SHIFT;
+	return (IPC_ISH_FWSTS & IPC_ISH_FWSTS_FAIL_REASON_MASK) >>
+	       IPC_ISH_FWSTS_FAIL_REASON_SHIFT;
 }
 
 /* set reset id */
@@ -160,14 +160,14 @@ static inline void ish_fwst_set_reset_id(uint32_t val)
 	uint32_t fwst = IPC_ISH_FWSTS;
 
 	IPC_ISH_FWSTS = (fwst & ~IPC_ISH_FWSTS_RESET_ID_MASK) |
-		(val << IPC_ISH_FWSTS_RESET_ID_SHIFT);
+			(val << IPC_ISH_FWSTS_RESET_ID_SHIFT);
 }
 
 /* get reset id */
 static inline uint32_t ish_fwst_get_reset_id(void)
 {
-	return (IPC_ISH_FWSTS & IPC_ISH_FWSTS_RESET_ID_MASK)
-		>> IPC_ISH_FWSTS_RESET_ID_SHIFT;
+	return (IPC_ISH_FWSTS & IPC_ISH_FWSTS_RESET_ID_MASK) >>
+	       IPC_ISH_FWSTS_RESET_ID_SHIFT;
 }
 
 /* set general fw status */
@@ -176,14 +176,14 @@ static inline void ish_fwst_set_fw_status(uint32_t val)
 	uint32_t fwst = IPC_ISH_FWSTS;
 
 	IPC_ISH_FWSTS = (fwst & ~IPC_ISH_FWSTS_FW_STATUS_MASK) |
-		(val << IPC_ISH_FWSTS_FW_STATUS_SHIFT);
+			(val << IPC_ISH_FWSTS_FW_STATUS_SHIFT);
 }
 
 /* get general fw status */
 static inline uint32_t ish_fwst_get_fw_status(void)
 {
-	return (IPC_ISH_FWSTS & IPC_ISH_FWSTS_FW_STATUS_MASK)
-		>> IPC_ISH_FWSTS_FW_STATUS_SHIFT;
+	return (IPC_ISH_FWSTS & IPC_ISH_FWSTS_FW_STATUS_MASK) >>
+	       IPC_ISH_FWSTS_FW_STATUS_SHIFT;
 }
 
 #endif /* __ISH_FWST_H */
diff --git a/chip/ish/ish_i2c.h b/chip/ish/ish_i2c.h
index 5b30de775c..7aa2977178 100644
--- a/chip/ish/ish_i2c.h
+++ b/chip/ish/ish_i2c.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,25 +6,25 @@
 #ifndef __CROS_EC_ISH_I2C_H
 #define __CROS_EC_ISH_I2C_H
 
-#include <stdint.h>
 #include "task.h"
 
-#define I2C_TSC_TIMEOUT			2000000
-#define I2C_CALIB_ADDRESS		0x3
-#define I2C_INTERRUPT_TIMEOUT		(TICKFREQ / 20)
-#define NS_IN_SEC			1000
-#define DEFAULT_SDA_HOLD		240
-#define DEFAULT_SDA_HOLD_STD		2400
-#define DEFAULT_SDA_HOLD_FAST		600
-#define DEFAULT_SDA_HOLD_FAST_PLUS	300
-#define DEFAULT_SDA_HOLD_HIGH		140
-#define NS_2_COUNTERS(ns, clk)		((ns * clk)/NS_IN_SEC)
-#define COUNTERS_2_NS(counters, clk)	(counters * (NANOSECONDS_IN_SEC / \
-					(clk * HZ_IN_MEGAHZ)))
-#define I2C_TX_FLUSH_TIMEOUT_USEC	200
+#include <stdint.h>
 
-#define ISH_I2C_FIFO_SIZE 64
+#define I2C_TSC_TIMEOUT 2000000
+#define I2C_CALIB_ADDRESS 0x3
+#define I2C_INTERRUPT_TIMEOUT (TICKFREQ / 20)
+#define NS_IN_SEC 1000
+#define DEFAULT_SDA_HOLD 240
+#define DEFAULT_SDA_HOLD_STD 2400
+#define DEFAULT_SDA_HOLD_FAST 600
+#define DEFAULT_SDA_HOLD_FAST_PLUS 300
+#define DEFAULT_SDA_HOLD_HIGH 140
+#define NS_2_COUNTERS(ns, clk) ((ns * clk) / NS_IN_SEC)
+#define COUNTERS_2_NS(counters, clk) \
+	(counters * (NANOSECONDS_IN_SEC / (clk * HZ_IN_MEGAHZ)))
+#define I2C_TX_FLUSH_TIMEOUT_USEC 200
 
+#define ISH_I2C_FIFO_SIZE 64
 
 enum {
 	/* freq mode values */
@@ -38,29 +38,18 @@ enum {
 };
 
 const unsigned int clk_in[] = {
-	[I2C_FREQ_25] = 25,
-	[I2C_FREQ_50] = 50,
-	[I2C_FREQ_100] = 100,
-	[I2C_FREQ_120] = 120,
-	[I2C_FREQ_40] = 40,
-	[I2C_FREQ_20] = 20,
+	[I2C_FREQ_25] = 25,   [I2C_FREQ_50] = 50, [I2C_FREQ_100] = 100,
+	[I2C_FREQ_120] = 120, [I2C_FREQ_40] = 40, [I2C_FREQ_20] = 20,
 	[I2C_FREQ_37] = 37,
 };
 
 const uint8_t spkln[] = {
-	[I2C_FREQ_25] = 2,
-	[I2C_FREQ_50] = 3,
-	[I2C_FREQ_100] = 5,
-	[I2C_FREQ_120] = 6,
-	[I2C_FREQ_40] = 2,
-	[I2C_FREQ_20] = 1,
+	[I2C_FREQ_25] = 2,  [I2C_FREQ_50] = 3, [I2C_FREQ_100] = 5,
+	[I2C_FREQ_120] = 6, [I2C_FREQ_40] = 2, [I2C_FREQ_20] = 1,
 	[I2C_FREQ_37] = 2,
 };
 
-enum {
-	I2C_READ,
-	I2C_WRITE
-};
+enum { I2C_READ, I2C_WRITE };
 
 enum {
 	/* REGISTERS */
@@ -125,7 +114,7 @@ enum {
 	IC_10BITADDR_MASTER = 0,
 	/* IC_TAR WRITE VALUES */
 	IC_10BITADDR_MASTER_VAL =
-	    (IC_10BITADDR_MASTER << IC_10BITADDR_MASTER_OFFSET),
+		(IC_10BITADDR_MASTER << IC_10BITADDR_MASTER_OFFSET),
 	TAR_SPECIAL_VAL = (TAR_SPECIAL << SPECIAL_OFFSET),
 	/* IC_DATA_CMD OFFSETS */
 	DATA_CMD_DAT_OFFSET = 0,
@@ -180,13 +169,13 @@ struct i2c_bus_info {
 	struct i2c_bus_data fast_speed;
 	struct i2c_bus_data fast_plus_speed;
 	struct i2c_bus_data high_speed;
-} __attribute__ ((__packed__));
+} __attribute__((__packed__));
 
 enum i2c_speed {
-	I2C_SPEED_100KHZ,	/* 100kHz */
-	I2C_SPEED_400KHZ,	/* 400kHz */
-	I2C_SPEED_1MHZ,		/*   1MHz */
-	I2C_SPEED_3M4HZ,	/* 3.4MHz */
+	I2C_SPEED_100KHZ, /* 100kHz */
+	I2C_SPEED_400KHZ, /* 400kHz */
+	I2C_SPEED_1MHZ, /*   1MHz */
+	I2C_SPEED_3M4HZ, /* 3.4MHz */
 };
 
 struct i2c_context {
diff --git a/chip/ish/ish_persistent_data.c b/chip/ish/ish_persistent_data.c
index 003f781d5f..ed909d6f7b 100644
--- a/chip/ish/ish_persistent_data.c
+++ b/chip/ish/ish_persistent_data.c
@@ -1,14 +1,14 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "common.h"
-#include "ec_commands.h"
 #include "config.h"
+#include "ec_commands.h"
 #include "hooks.h"
-#include "system.h"
 #include "ish_persistent_data.h"
+#include "system.h"
 
 #define PERSISTENT_DATA_MAGIC 0x49534864 /* "ISHd" */
 
@@ -16,7 +16,7 @@ struct ish_persistent_data ish_persistent_data = {
 	.magic = PERSISTENT_DATA_MAGIC,
 	.reset_flags = EC_RESET_FLAG_POWER_ON,
 	.watchdog_counter = 0,
-	.panic_data = {0},
+	.panic_data = { 0 },
 };
 
 /*
@@ -40,8 +40,7 @@ void ish_persistent_data_init(void)
 {
 	if (ish_persistent_data_aon.magic == PERSISTENT_DATA_MAGIC) {
 		/* Stored data is valid, load a copy */
-		memcpy(&ish_persistent_data,
-		       &ish_persistent_data_aon,
+		memcpy(&ish_persistent_data, &ish_persistent_data_aon,
 		       sizeof(struct ish_persistent_data));
 
 		/* Invalidate stored data, in case commit fails to happen */
@@ -54,7 +53,6 @@ void ish_persistent_data_init(void)
 
 void ish_persistent_data_commit(void)
 {
-	memcpy(&ish_persistent_data_aon,
-	       &ish_persistent_data,
+	memcpy(&ish_persistent_data_aon, &ish_persistent_data,
 	       sizeof(struct ish_persistent_data));
 }
diff --git a/chip/ish/ish_persistent_data.h b/chip/ish/ish_persistent_data.h
index 0fd973e1bb..60aa6b94ae 100644
--- a/chip/ish/ish_persistent_data.h
+++ b/chip/ish/ish_persistent_data.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/ish/power_mgt.c b/chip/ish/power_mgt.c
index 6664b589a8..de9022b55a 100644
--- a/chip/ish/power_mgt.c
+++ b/chip/ish/power_mgt.c
@@ -1,10 +1,8 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <stdnoreturn.h>
-
 #include "aontaskfw/ish_aon_share.h"
 #include "console.h"
 #include "hwtimer.h"
@@ -17,6 +15,8 @@
 #include "util.h"
 #include "watchdog.h"
 
+#include <stdnoreturn.h>
+
 #define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
 #define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 #define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
@@ -52,7 +52,7 @@ static void pg_exit_restore_hw(void)
  * fixed amount of time to keep the console in use flag true after boot in
  * order to give a permanent window in which the low speed clock is not used.
  */
-#define CONSOLE_IN_USE_ON_BOOT_TIME (15*SECOND)
+#define CONSOLE_IN_USE_ON_BOOT_TIME (15 * SECOND)
 
 /* power management internal context data structure */
 struct pm_context {
@@ -172,20 +172,20 @@ static void init_aon_task(void)
 	 * limit: 0x67
 	 * Present = 1, DPL = 0
 	 */
-	desc_lo = GEN_GDT_DESC_LO((uint32_t)&main_tss,
-			GDT_DESC_TSS_LIMIT, GDT_DESC_TSS_FLAGS);
-	desc_up = GEN_GDT_DESC_UP((uint32_t)&main_tss,
-			GDT_DESC_TSS_LIMIT, GDT_DESC_TSS_FLAGS);
+	desc_lo = GEN_GDT_DESC_LO((uint32_t)&main_tss, GDT_DESC_TSS_LIMIT,
+				  GDT_DESC_TSS_FLAGS);
+	desc_up = GEN_GDT_DESC_UP((uint32_t)&main_tss, GDT_DESC_TSS_LIMIT,
+				  GDT_DESC_TSS_FLAGS);
 	add_gdt_entry(desc_lo, desc_up);
 
 	/* set GDT entry 4 for TSS descriptor of aontask
 	 * limit: 0x67
 	 * Present = 1, DPL = 0, Accessed = 1
 	 */
-	desc_lo = GEN_GDT_DESC_LO((uint32_t)aon_tss,
-			GDT_DESC_TSS_LIMIT, GDT_DESC_TSS_FLAGS);
-	desc_up = GEN_GDT_DESC_UP((uint32_t)aon_tss,
-			GDT_DESC_TSS_LIMIT, GDT_DESC_TSS_FLAGS);
+	desc_lo = GEN_GDT_DESC_LO((uint32_t)aon_tss, GDT_DESC_TSS_LIMIT,
+				  GDT_DESC_TSS_FLAGS);
+	desc_up = GEN_GDT_DESC_UP((uint32_t)aon_tss, GDT_DESC_TSS_LIMIT,
+				  GDT_DESC_TSS_FLAGS);
 	pm_ctx.aon_tss_selector[1] = add_gdt_entry(desc_lo, desc_up);
 
 	/* set GDT entry 5 for LDT descriptor of aontask
@@ -205,12 +205,12 @@ static void init_aon_task(void)
 			 "pop %eax;");
 
 	aon_share->main_fw_ro_addr = (uint32_t)&__aon_ro_start;
-	aon_share->main_fw_ro_size = (uint32_t)&__aon_ro_end -
-				     (uint32_t)&__aon_ro_start;
+	aon_share->main_fw_ro_size =
+		(uint32_t)&__aon_ro_end - (uint32_t)&__aon_ro_start;
 
 	aon_share->main_fw_rw_addr = (uint32_t)&__aon_rw_start;
-	aon_share->main_fw_rw_size = (uint32_t)&__aon_rw_end -
-				     (uint32_t)&__aon_rw_start;
+	aon_share->main_fw_rw_size =
+		(uint32_t)&__aon_rw_end - (uint32_t)&__aon_rw_start;
 
 	aon_share->uma_msb = IPC_UMA_RANGE_LOWER_1;
 
@@ -258,8 +258,7 @@ static void switch_to_aontask(void)
 	interrupt_enable();
 }
 
-noreturn
-static void handle_reset_in_aontask(enum ish_pm_state pm_state)
+noreturn static void handle_reset_in_aontask(enum ish_pm_state pm_state)
 {
 	pm_ctx.aon_share->pm_state = pm_state;
 
@@ -318,10 +317,8 @@ static uint32_t convert_both_edge_gpio_to_single_edge(void)
 	 * interrupt trigger mode enabled pins.
 	 */
 	for (i = 0; i < 32; i++) {
-		if (ISH_GPIO_GIMR & BIT(i) &&
-		    ISH_GPIO_GRER & BIT(i) &&
+		if (ISH_GPIO_GIMR & BIT(i) && ISH_GPIO_GRER & BIT(i) &&
 		    ISH_GPIO_GFER & BIT(i)) {
-
 			/* Record the pin so we can restore it later */
 			both_edge_pins |= BIT(i);
 
@@ -513,7 +510,6 @@ static int d0ix_decide(timestamp_t cur_time, uint32_t idle_us)
 	int pm_state = ISH_PM_STATE_D0I0;
 
 	if (DEEP_SLEEP_ALLOWED) {
-
 		/* check if the console use has expired. */
 		if (sleep_mask & SLEEP_MASK_CONSOLE) {
 			if (cur_time.val > pm_ctx.console_expire_time.val) {
@@ -525,8 +521,7 @@ static int d0ix_decide(timestamp_t cur_time, uint32_t idle_us)
 		}
 
 		if (IS_ENABLED(CONFIG_ISH_PM_D0I3) &&
-		    idle_us >= CONFIG_ISH_D0I3_MIN_USEC &&
-		    pm_ctx.aon_valid)
+		    idle_us >= CONFIG_ISH_D0I3_MIN_USEC && pm_ctx.aon_valid)
 			pm_state = ISH_PM_STATE_D0I3;
 
 		else if (IS_ENABLED(CONFIG_ISH_PM_D0I2) &&
@@ -617,18 +612,41 @@ void ish_pm_init(void)
 	/* clear reset history register in CCU */
 	CCU_RST_HST = CCU_RST_HST;
 
+#if defined(CHIP_VARIANT_ISH5P4)
+	if (IS_ENABLED(CONFIG_ISH_NEW_PM))
+		PMU_D3_STATUS_1 = 0xffffffff;
+#endif
+
 	/* disable TCG and disable BCG */
-	CCU_TCG_EN = 0;
+	CCU_TCG_ENABLE = 0;
+	CCU_BCG_ENABLE = 0;
+
+	/* Disable power gate of CACHE and ROM */
+	PMU_RF_ROM_PWR_CTRL = 0;
+
 	reset_bcg();
 
 	if (IS_ENABLED(CONFIG_ISH_PM_AONTASK))
 		init_aon_task();
 
-	/* unmask all wake up events */
+	if (IS_ENABLED(CONFIG_ISH_NEW_PM)) {
+		PMU_GPIO_WAKE_MASK0 = 0;
+		PMU_GPIO_WAKE_MASK1 = 0;
+	}
+
+	/* Unmask all wake up events in event1 */
 	PMU_MASK_EVENT = ~PMU_MASK_EVENT_BIT_ALL;
+	/* Mask events in event2 */
+	PMU_MASK_EVENT2 = PMU_MASK2_ALL_EVENTS;
+
+#if defined(CHIP_VARIANT_ISH5P4)
+	SBEP_REG_CLK_GATE_ENABLE =
+		(SB_CLK_GATE_EN_LOCAL_CLK_GATE | SB_CLK_GATE_EN_TRUNK_CLK_GATE);
+#endif
 
 	if (IS_ENABLED(CONFIG_ISH_NEW_PM)) {
-		PMU_ISH_FABRIC_CNT = (PMU_ISH_FABRIC_CNT & 0xffff0000) | FABRIC_IDLE_COUNT;
+		PMU_ISH_FABRIC_CNT = (PMU_ISH_FABRIC_CNT & 0xffff0000) |
+				     FABRIC_IDLE_COUNT;
 		PMU_PGCB_CLKGATE_CTRL = TRUNK_CLKGATE_COUNT;
 	}
 
@@ -647,15 +665,22 @@ void ish_pm_init(void)
 		    (PMU_D3_STATUS & PMU_BME_BIT_SET))
 			PMU_D3_STATUS = PMU_D3_STATUS;
 
+#if defined(CHIP_VARIANT_ISH5P4)
+		if (IS_ENABLED(CONFIG_ISH_NEW_PM)) {
+			/* Mask all function1 */
+			PMU_REG_MASK_D3_RISE = 0x2;
+			PMU_REG_MASK_D3_FALL = 0x2;
+			PMU_REG_MASK_BME_RISE = 0x2;
+			PMU_REG_MASK_BME_FALL = 0x2;
+		}
+#endif
 		enable_d3bme_irqs();
 	}
 }
 
-noreturn
-void ish_pm_reset(enum ish_pm_state pm_state)
+noreturn void ish_pm_reset(enum ish_pm_state pm_state)
 {
-	if (IS_ENABLED(CONFIG_ISH_PM_AONTASK) &&
-	    pm_ctx.aon_valid) {
+	if (IS_ENABLED(CONFIG_ISH_PM_AONTASK) && pm_ctx.aon_valid) {
 		handle_reset_in_aontask(pm_state);
 	} else {
 		ish_mia_reset();
@@ -674,8 +699,8 @@ void __idle(void)
 	 * time in order to give a fixed window on boot
 	 */
 	disable_sleep(SLEEP_MASK_CONSOLE);
-	pm_ctx.console_expire_time.val = get_time().val +
-					 CONSOLE_IN_USE_ON_BOOT_TIME;
+	pm_ctx.console_expire_time.val =
+		get_time().val + CONSOLE_IN_USE_ON_BOOT_TIME;
 
 	while (1) {
 		t0 = get_time();
@@ -709,7 +734,7 @@ static void print_stats(const char *name, const struct pm_stat *stat)
 /**
  * Print low power idle statistics
  */
-static int command_idle_stats(int argc, char **argv)
+static int command_idle_stats(int argc, const char **argv)
 {
 	struct ish_aon_share *aon_share = pm_ctx.aon_share;
 
@@ -737,13 +762,11 @@ static int command_idle_stats(int argc, char **argv)
 DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, "",
 			"Print power management statistics");
 
-
 /**
  * main FW only need handle PMU wakeup interrupt for D0i1 state, aontask will
  * handle PMU wakeup interrupt for other low power states
  */
-__maybe_unused
-static void pmu_wakeup_isr(void)
+__maybe_unused static void pmu_wakeup_isr(void)
 {
 	/* at current nothing need to do */
 }
@@ -758,8 +781,7 @@ DECLARE_IRQ(ISH_PMU_WAKEUP_IRQ, pmu_wakeup_isr);
  *
  */
 
-__maybe_unused noreturn
-static void reset_prep_isr(void)
+__maybe_unused noreturn static void reset_prep_isr(void)
 {
 	/* mask reset prep avail interrupt */
 	PMU_RST_PREP = PMU_RST_PREP_INT_MASK;
@@ -779,8 +801,7 @@ static void reset_prep_isr(void)
 DECLARE_IRQ(ISH_RESET_PREP_IRQ, reset_prep_isr);
 #endif
 
-__maybe_unused
-static void handle_d3(uint32_t irq_vec)
+__maybe_unused static void handle_d3(uint32_t irq_vec)
 {
 	PMU_D3_STATUS = PMU_D3_STATUS;
 
@@ -834,5 +855,5 @@ void ish_pm_refresh_console_in_use(void)
 	/* Set console in use expire time. */
 	pm_ctx.console_expire_time = get_time();
 	pm_ctx.console_expire_time.val +=
-				pm_ctx.console_in_use_timeout_sec * SECOND;
+		pm_ctx.console_in_use_timeout_sec * SECOND;
 }
diff --git a/chip/ish/power_mgt.h b/chip/ish/power_mgt.h
index a1fd5aabb6..a7a702018f 100644
--- a/chip/ish/power_mgt.h
+++ b/chip/ish/power_mgt.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,19 +6,19 @@
 #ifndef __CROS_EC_POWER_MGT_H
 #define __CROS_EC_POWER_MGT_H
 
-#include <stdnoreturn.h>
-
 #include "common.h"
 #include "registers.h"
 
+#include <stdnoreturn.h>
+
 extern void uart_port_restore(void);
 extern void uart_to_idle(void);
 extern void clear_fabric_error(void);
 extern void i2c_port_restore(void);
 extern void lapic_restore(void);
 
-#define FABRIC_IDLE_COUNT	50
-#define TRUNK_CLKGATE_COUNT	0xf
+#define FABRIC_IDLE_COUNT 50
+#define TRUNK_CLKGATE_COUNT 0xf
 
 /* power states for ISH */
 enum ish_pm_state {
@@ -58,8 +58,7 @@ static inline void ish_mia_halt(void)
 }
 
 /* reset ISH mintue-ia cpu core  */
-noreturn
-static inline void ish_mia_reset(void)
+noreturn static inline void ish_mia_reset(void)
 {
 	/**
 	 * ISH HW looks at the rising edge of this bit to
diff --git a/chip/ish/registers.h b/chip/ish/registers.h
index 258abe33ef..7fe5d2c5ab 100644
--- a/chip/ish/registers.h
+++ b/chip/ish/registers.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,99 +19,100 @@
  * ISH3.0 has 3 controllers. Locking must occur by-controller (not by-port).
  */
 enum ish_i2c_port {
-	ISH_I2C0   = 0,      /* Controller 0 */
-	ISH_I2C1   = 1,      /* Controller 1 */
-	ISH_I2C2   = 2,      /* Controller 2 */
+	ISH_I2C0 = 0, /* Controller 0 */
+	ISH_I2C1 = 1, /* Controller 1 */
+	ISH_I2C2 = 2, /* Controller 2 */
 	I2C_PORT_COUNT,
 };
 
 #endif
 
-#define ISH_I2C_PORT_COUNT	I2C_PORT_COUNT
+#define ISH_I2C_PORT_COUNT I2C_PORT_COUNT
 
 /* In ISH, the devices are mapped to pre-defined addresses in the 32-bit
  * linear address space.
  */
 #ifdef CHIP_VARIANT_ISH5P4
-#define ISH_I2C0_BASE     0x00000000
-#define ISH_I2C1_BASE     0x00002000
-#define ISH_I2C2_BASE     0x00004000
-#define ISH_UART_BASE     0x08100000
-#define ISH_GPIO_BASE     0x00100000
-#define ISH_PMU_BASE      0x04200000
-#define ISH_OCP_BASE      0xFFFFFFFF
-#define ISH_MISC_BASE     0x04400000
-#define ISH_DMA_BASE      0x10100000
-#define ISH_CCU_BASE      0x04300000
-#define ISH_IPC_BASE      0x04100000
-#define ISH_WDT_BASE      0x04900000
-#define ISH_IOAPIC_BASE   0xFEC00000
-#define ISH_HPET_BASE     0x04700000
-#define ISH_LAPIC_BASE    0xFEE00000
+#define ISH_I2C0_BASE 0x00000000
+#define ISH_I2C1_BASE 0x00002000
+#define ISH_I2C2_BASE 0x00004000
+#define ISH_UART_BASE 0x08100000
+#define ISH_GPIO_BASE 0x00100000
+#define ISH_PMU_BASE 0x04200000
+#define ISH_OCP_BASE 0xFFFFFFFF
+#define ISH_MISC_BASE 0x04400000
+#define ISH_DMA_BASE 0x10100000
+#define ISH_CCU_BASE 0x04300000
+#define ISH_IPC_BASE 0x04100000
+#define ISH_WDT_BASE 0x04900000
+#define ISH_IOAPIC_BASE 0xFEC00000
+#define ISH_HPET_BASE 0x04700000
+#define ISH_LAPIC_BASE 0xFEE00000
+#define ISH_SBEP_BASE 0x04500000
 #else
-#define ISH_I2C0_BASE     0x00100000
-#define ISH_I2C1_BASE     0x00102000
-#define ISH_I2C2_BASE     0x00105000
-#define ISH_UART_BASE     0x00103000
-#define ISH_GPIO_BASE     0x001F0000
-#define ISH_PMU_BASE      0x00800000
-#define ISH_OCP_BASE      0x00700000
-#define ISH_MISC_BASE     0x00C00000
-#define ISH_DMA_BASE      0x00400000
-#define ISH_CCU_BASE      0x00900000
-#define ISH_IPC_BASE      0x00B00000
-#define ISH_WDT_BASE      0xFDE00000
-#define ISH_IOAPIC_BASE   0xFEC00000
-#define ISH_HPET_BASE     0xFED00000
-#define ISH_LAPIC_BASE    0xFEE00000
+#define ISH_I2C0_BASE 0x00100000
+#define ISH_I2C1_BASE 0x00102000
+#define ISH_I2C2_BASE 0x00105000
+#define ISH_UART_BASE 0x00103000
+#define ISH_GPIO_BASE 0x001F0000
+#define ISH_PMU_BASE 0x00800000
+#define ISH_OCP_BASE 0x00700000
+#define ISH_MISC_BASE 0x00C00000
+#define ISH_DMA_BASE 0x00400000
+#define ISH_CCU_BASE 0x00900000
+#define ISH_IPC_BASE 0x00B00000
+#define ISH_WDT_BASE 0xFDE00000
+#define ISH_IOAPIC_BASE 0xFEC00000
+#define ISH_HPET_BASE 0xFED00000
+#define ISH_LAPIC_BASE 0xFEE00000
 #endif
 
 /* HW interrupt pins mapped to IOAPIC, from I/O sources */
 #ifdef CHIP_VARIANT_ISH5P4
-#define ISH_I2C0_IRQ               15
-#define ISH_I2C1_IRQ               16
-#define ISH_FABRIC_IRQ             12
-#define ISH_I2C2_IRQ               17
-#define ISH_WDT_IRQ                26
-#define ISH_GPIO_IRQ               13
-#define ISH_HPET_TIMER1_IRQ        14
-#define ISH_IPC_HOST2ISH_IRQ       0
-#define ISH_PMU_WAKEUP_IRQ         10
-#define ISH_D3_RISE_IRQ            9
-#define ISH_D3_FALL_IRQ            9
-#define ISH_BME_RISE_IRQ           9
-#define ISH_BME_FALL_IRQ           9
-#define ISH_IPC_ISH2HOST_CLR_IRQ   0
-#define ISH_UART0_IRQ              23
-#define ISH_UART1_IRQ              24
-#define ISH_RESET_PREP_IRQ         6
+#define ISH_I2C0_IRQ 15
+#define ISH_I2C1_IRQ 16
+#define ISH_FABRIC_IRQ 12
+#define ISH_I2C2_IRQ 17
+#define ISH_WDT_IRQ 26
+#define ISH_GPIO_IRQ 13
+#define ISH_HPET_TIMER1_IRQ 14
+#define ISH_IPC_HOST2ISH_IRQ 0
+#define ISH_PMU_WAKEUP_IRQ 10
+#define ISH_D3_RISE_IRQ 9
+#define ISH_D3_FALL_IRQ 9
+#define ISH_BME_RISE_IRQ 9
+#define ISH_BME_FALL_IRQ 9
+#define ISH_IPC_ISH2HOST_CLR_IRQ 0
+#define ISH_UART0_IRQ 23
+#define ISH_UART1_IRQ 24
+#define ISH_RESET_PREP_IRQ 6
 #else
-#define ISH_I2C0_IRQ               0
-#define ISH_I2C1_IRQ               1
-#define ISH_FABRIC_IRQ             5
-#define ISH_I2C2_IRQ               40
-#define ISH_WDT_IRQ                6
-#define ISH_GPIO_IRQ               7
-#define ISH_HPET_TIMER1_IRQ        8
-#define ISH_IPC_HOST2ISH_IRQ       12
-#define ISH_PMU_WAKEUP_IRQ         18
-#define ISH_D3_RISE_IRQ            19
-#define ISH_D3_FALL_IRQ            29
-#define ISH_BME_RISE_IRQ           50
-#define ISH_BME_FALL_IRQ           51
-#define ISH_IPC_ISH2HOST_CLR_IRQ   24
-#define ISH_UART0_IRQ              34
-#define ISH_UART1_IRQ              35
-#define ISH_RESET_PREP_IRQ         62
+#define ISH_I2C0_IRQ 0
+#define ISH_I2C1_IRQ 1
+#define ISH_FABRIC_IRQ 5
+#define ISH_I2C2_IRQ 40
+#define ISH_WDT_IRQ 6
+#define ISH_GPIO_IRQ 7
+#define ISH_HPET_TIMER1_IRQ 8
+#define ISH_IPC_HOST2ISH_IRQ 12
+#define ISH_PMU_WAKEUP_IRQ 18
+#define ISH_D3_RISE_IRQ 19
+#define ISH_D3_FALL_IRQ 29
+#define ISH_BME_RISE_IRQ 50
+#define ISH_BME_FALL_IRQ 51
+#define ISH_IPC_ISH2HOST_CLR_IRQ 24
+#define ISH_UART0_IRQ 34
+#define ISH_UART1_IRQ 35
+#define ISH_RESET_PREP_IRQ 62
 #endif
 
 /* Interrupt vectors 0-31 are architecture reserved.
  * Vectors 32-255 are user-defined.
  */
-#define USER_VEC_START   32
+#define USER_VEC_START 32
 /* Map IRQs to vectors after offset 10 for certain APIC interrupts */
-#define IRQ_TO_VEC(irq)  ((irq) + USER_VEC_START + 10)
-#define VEC_TO_IRQ(vec)  ((vec) - USER_VEC_START - 10)
+#define IRQ_TO_VEC(irq) ((irq) + USER_VEC_START + 10)
+#define VEC_TO_IRQ(vec) ((vec)-USER_VEC_START - 10)
 
 /* ISH GPIO Registers */
 #define ISH_GPIO_GCCR REG32(ISH_GPIO_BASE + 0x000) /* Direction lock */
@@ -128,320 +129,400 @@ enum ish_i2c_port {
 #define ISH_GPIO_GWSR REG32(ISH_GPIO_BASE + 0x118) /* Wake Source */
 #define ISH_GPIO_GSEC REG32(ISH_GPIO_BASE + 0x130) /* Secure Input */
 
+#if defined(CHIP_VARIANT_ISH5P4)
+/* Side Band End Point registers */
+#define SBEP_REG_CLK_GATE_ENABLE REG32(ISH_SBEP_BASE + 0x006C)
+#define SB_CLK_GATE_EN_LOCAL_CLK_GATE BIT(0)
+#define SB_CLK_GATE_EN_TRUNK_CLK_GATE BIT(1)
+#endif
+
+#define SBEP_REG_UP_MSG_STATUS_ADDR (ISH_SBEP_BASE + 0x0040)
+#define SBEP_REG_UP_MSG_STATUS REG32(ISH_SBEP_BASE + 0x0040)
+#define SBEP_REG_UP_MSG_COMMAND REG32(ISH_SBEP_BASE + 0x0044)
+#define SBEP_REG_UP_MSG_REQ_ADDR_LOW REG32(ISH_SBEP_BASE + 0x0048)
+#define SBEP_REG_UP_MSG_REQ_ADDR_HIGH REG32(ISH_SBEP_BASE + 0x004C)
+#define SBEP_REG_UP_MSG_REQ_DATA REG32(ISH_SBEP_BASE + 0x0050)
+#define SBEP_REG_UP_MSG_REQ_ATTR REG32(ISH_SBEP_BASE + 0x0054)
+#define SBEP_REG_UP_MSG_REQ_EH REG32(ISH_SBEP_BASE + 0x0058)
+
+#define UP_STATUS_BUSY_MASK 0x01
+#define UP_STATUS_MSG_SENT_MASK 0x02
+#define UP_STATUS_MSG_SENT_CLR 0x02
+
+#define SBEP_CMD_ACTION 0x1
+#define SBEP_CMD_TYPE_WRITE 0x0
+#define SBEP_CMD_TYPE_READ 0x1
+#define SBEP_CMD_POSTED 0x1
+#define SBEP_CMD_NON_POSTED 0x0
+#define SBEP_CMD_INT_ENABLED 0x1
+#define SBEP_CMD_ACTION_OFF 0
+#define SBEP_CMD_TYPE_OFF 1
+#define SBEP_CMD_POSTED_OFF 2
+#define SBEP_CMD_INT_OFF 3
+
+#define SBEP_CMD_WRITE                                \
+	((SBEP_CMD_ACTION << SBEP_CMD_ACTION_OFF) |   \
+	 (SBEP_CMD_TYPE_WRITE << SBEP_CMD_TYPE_OFF) | \
+	 (SBEP_CMD_POSTED << SBEP_CMD_POSTED_OFF) |   \
+	 (SBEP_CMD_INT_ENABLED << SBEP_CMD_INT_OFF))
+
+#define SBEP_ATTR_LTR_OPCODE 0x43
+#define SBEP_ATTR_PMC_DEST_ID 0xCC
+#define SBEP_ATTR_DEST_ID_OFF 0
+#define SBEP_ATTR_OPCODE_OFF 8
+#define SBEP_ATTR_WRITE_ALL_BYTES 0xF
+#define SBEP_ATTR_BYTE_ENABLE_OFF 16
+#define LTR_CMD_ATTR                                        \
+	((SBEP_ATTR_PMC_DEST_ID << SBEP_ATTR_DEST_ID_OFF) | \
+	 (SBEP_ATTR_LTR_OPCODE << SBEP_ATTR_OPCODE_OFF) |   \
+	 (SBEP_ATTR_WRITE_ALL_BYTES << SBEP_ATTR_BYTE_ENABLE_OFF))
+#define LTR_CMD_DATA_2MS 0x90029002
+#define LTR_CMD_DATA_INFINITE 0
+
+#define SBEP_SAIRS_ROOT_SPACE_PMC 0
+
+#define SBEP_SAIRS_EH_PRESENT 1
+#define SBEP_SAIRS_ROOT_SPACE_OFF 16
+#define SBEP_SAIRS_EH_PRESENT_OFF 31
+
+#define SBEP_PMC_SAIRS_VAL                                          \
+	((SBEP_SAIRS_ROOT_SPACE_PMC << SBEP_SAIRS_ROOT_SPACE_OFF) | \
+	 (SBEP_SAIRS_EH_PRESENT << SBEP_SAIRS_EH_PRESENT_OFF))
+
 /* APIC interrupt vectors */
-#define ISH_TS_VECTOR              0x20  /* Task switch vector */
-#define LAPIC_LVT_ERROR_VECTOR     0x21  /* Clears IOAPIC/LAPIC sync errors */
-#define SOFTIRQ_VECTOR             0x22  /* Handles software generated IRQs */
-#define LAPIC_SPURIOUS_INT_VECTOR  0xff
+#define ISH_TS_VECTOR 0x20 /* Task switch vector */
+#define LAPIC_LVT_ERROR_VECTOR 0x21 /* Clears IOAPIC/LAPIC sync errors */
+#define SOFTIRQ_VECTOR 0x22 /* Handles software generated IRQs */
+#define LAPIC_SPURIOUS_INT_VECTOR 0xff
 
 /* Interrupt to vector mapping. To be programmed into IOAPIC */
-#define ISH_I2C0_VEC               IRQ_TO_VEC(ISH_I2C0_IRQ)
-#define ISH_I2C1_VEC               IRQ_TO_VEC(ISH_I2C1_IRQ)
-#define ISH_I2C2_VEC               IRQ_TO_VEC(ISH_I2C2_IRQ)
-#define ISH_WDT_VEC                IRQ_TO_VEC(ISH_WDT_IRQ)
-#define ISH_GPIO_VEC               IRQ_TO_VEC(ISH_GPIO_IRQ)
-#define ISH_HPET_TIMER1_VEC        IRQ_TO_VEC(ISH_HPET_TIMER1_IRQ)
-#define ISH_IPC_ISH2HOST_CLR_VEC   IRQ_TO_VEC(ISH_IPC_ISH2HOST_CLR_IRQ)
-#define ISH_UART0_VEC              IRQ_TO_VEC(ISH_UART0_IRQ)
-#define ISH_UART1_VEC              IRQ_TO_VEC(ISH_UART1_IRQ)
-#define ISH_IPC_VEC                IRQ_TO_VEC(ISH_IPC_HOST2ISH_IRQ)
-#define ISH_RESET_PREP_VEC         IRQ_TO_VEC(ISH_RESET_PREP_IRQ)
-#define ISH_PMU_WAKEUP_VEC         IRQ_TO_VEC(ISH_PMU_WAKEUP_IRQ)
-#define ISH_D3_RISE_VEC            IRQ_TO_VEC(ISH_D3_RISE_IRQ)
-#define ISH_D3_FALL_VEC            IRQ_TO_VEC(ISH_D3_FALL_IRQ)
-#define ISH_BME_RISE_VEC           IRQ_TO_VEC(ISH_BME_RISE_IRQ)
-#define ISH_BME_FALL_VEC           IRQ_TO_VEC(ISH_BME_FALL_IRQ)
-#define ISH_FABRIC_VEC             IRQ_TO_VEC(ISH_FABRIC_IRQ)
-
-#define ISH_DEBUG_UART			UART_PORT_0
-#define ISH_DEBUG_UART_IRQ		ISH_UART0_IRQ
-#define ISH_DEBUG_UART_VEC		ISH_UART0_VEC
+#define ISH_I2C0_VEC IRQ_TO_VEC(ISH_I2C0_IRQ)
+#define ISH_I2C1_VEC IRQ_TO_VEC(ISH_I2C1_IRQ)
+#define ISH_I2C2_VEC IRQ_TO_VEC(ISH_I2C2_IRQ)
+#define ISH_WDT_VEC IRQ_TO_VEC(ISH_WDT_IRQ)
+#define ISH_GPIO_VEC IRQ_TO_VEC(ISH_GPIO_IRQ)
+#define ISH_HPET_TIMER1_VEC IRQ_TO_VEC(ISH_HPET_TIMER1_IRQ)
+#define ISH_IPC_ISH2HOST_CLR_VEC IRQ_TO_VEC(ISH_IPC_ISH2HOST_CLR_IRQ)
+#define ISH_UART0_VEC IRQ_TO_VEC(ISH_UART0_IRQ)
+#define ISH_UART1_VEC IRQ_TO_VEC(ISH_UART1_IRQ)
+#define ISH_IPC_VEC IRQ_TO_VEC(ISH_IPC_HOST2ISH_IRQ)
+#define ISH_RESET_PREP_VEC IRQ_TO_VEC(ISH_RESET_PREP_IRQ)
+#define ISH_PMU_WAKEUP_VEC IRQ_TO_VEC(ISH_PMU_WAKEUP_IRQ)
+#define ISH_D3_RISE_VEC IRQ_TO_VEC(ISH_D3_RISE_IRQ)
+#define ISH_D3_FALL_VEC IRQ_TO_VEC(ISH_D3_FALL_IRQ)
+#define ISH_BME_RISE_VEC IRQ_TO_VEC(ISH_BME_RISE_IRQ)
+#define ISH_BME_FALL_VEC IRQ_TO_VEC(ISH_BME_FALL_IRQ)
+#define ISH_FABRIC_VEC IRQ_TO_VEC(ISH_FABRIC_IRQ)
+
+#define ISH_DEBUG_UART UART_PORT_0
+#define ISH_DEBUG_UART_IRQ ISH_UART0_IRQ
+#define ISH_DEBUG_UART_VEC ISH_UART0_VEC
 
 /* IPC_Registers */
-#define IPC_PISR			REG32(ISH_IPC_BASE + 0x0)
-#define IPC_PISR_HOST2ISH_BIT		BIT(0)
-
-#define IPC_PIMR			REG32(ISH_IPC_BASE + 0x4)
-#define IPC_PIMR_HOST2ISH_BIT		BIT(0)
-#define IPC_PIMR_ISH2HOST_CLR_BIT	BIT(11)
-#define IPC_PIMR_CSME_CSR_BIT		BIT(23)
-#define IPC_ISH2HOST_MSG_BASE		REG8_ADDR(ISH_IPC_BASE + 0x60)
-#define IPC_ISH_FWSTS			REG32(ISH_IPC_BASE + 0x34)
-#define IPC_HOST2ISH_DOORBELL_ADDR	REG32_ADDR(ISH_IPC_BASE + 0x48)
-#define IPC_HOST2ISH_MSG_BASE		REG8_ADDR(ISH_IPC_BASE + 0xE0)
-#define IPC_ISH2HOST_DOORBELL_ADDR	REG32_ADDR(ISH_IPC_BASE + 0x54)
-#define IPC_ISH2PMC_DOORBELL		REG32(ISH_IPC_BASE + 0x58)
-#define IPC_ISH2PMC_MSG_BASE		(ISH_IPC_BASE + 0x260)
-#define IPC_ISH_RMP0			REG32(ISH_IPC_BASE + 0x360)
-#define IPC_ISH_RMP1			REG32(ISH_IPC_BASE + 0x364)
-#define IPC_ISH_RMP2			REG32(ISH_IPC_BASE + 0x368)
-#define DMA_ENABLED_MASK		BIT(0)
-#define IPC_BUSY_CLEAR			REG32(ISH_IPC_BASE + 0x378)
-#define IPC_DB_CLR_STS_ISH2HOST_BIT	BIT(0)
-
-#define IPC_UMA_RANGE_LOWER_0		REG32(ISH_IPC_BASE + 0x380)
-#define IPC_UMA_RANGE_LOWER_1		REG32(ISH_IPC_BASE + 0x384)
-#define IPC_UMA_RANGE_UPPER_0		REG32(ISH_IPC_BASE + 0x388)
-#define IPC_UMA_RANGE_UPPER_1		REG32(ISH_IPC_BASE + 0x38C)
+#define IPC_PISR REG32(ISH_IPC_BASE + 0x0)
+#define IPC_PISR_HOST2ISH_BIT BIT(0)
+
+#define IPC_PIMR REG32(ISH_IPC_BASE + 0x4)
+#define IPC_PIMR_HOST2ISH_BIT BIT(0)
+#define IPC_PIMR_ISH2HOST_CLR_BIT BIT(11)
+#define IPC_PIMR_CSME_CSR_BIT BIT(23)
+#define IPC_ISH2HOST_MSG_BASE REG8_ADDR(ISH_IPC_BASE + 0x60)
+#define IPC_ISH_FWSTS REG32(ISH_IPC_BASE + 0x34)
+#define IPC_HOST2ISH_DOORBELL_ADDR REG32_ADDR(ISH_IPC_BASE + 0x48)
+#define IPC_HOST2ISH_MSG_BASE REG8_ADDR(ISH_IPC_BASE + 0xE0)
+#define IPC_ISH2HOST_DOORBELL_ADDR REG32_ADDR(ISH_IPC_BASE + 0x54)
+#define IPC_ISH2PMC_DOORBELL REG32(ISH_IPC_BASE + 0x58)
+#define IPC_ISH2PMC_MSG_BASE (ISH_IPC_BASE + 0x260)
+#define IPC_ISH_RMP0 REG32(ISH_IPC_BASE + 0x360)
+#define IPC_ISH_RMP1 REG32(ISH_IPC_BASE + 0x364)
+#define IPC_ISH_RMP2 REG32(ISH_IPC_BASE + 0x368)
+#define DMA_ENABLED_MASK BIT(0)
+#define IPC_BUSY_CLEAR REG32(ISH_IPC_BASE + 0x378)
+#define IPC_DB_CLR_STS_ISH2HOST_BIT BIT(0)
+
+#define IPC_UMA_RANGE_LOWER_0 REG32(ISH_IPC_BASE + 0x380)
+#define IPC_UMA_RANGE_LOWER_1 REG32(ISH_IPC_BASE + 0x384)
+#define IPC_UMA_RANGE_UPPER_0 REG32(ISH_IPC_BASE + 0x388)
+#define IPC_UMA_RANGE_UPPER_1 REG32(ISH_IPC_BASE + 0x38C)
 
 /* PMU Registers */
-#define PMU_SRAM_PG_EN			REG32(ISH_PMU_BASE + 0x0)
+#define PMU_SRAM_PG_EN REG32(ISH_PMU_BASE + 0x0)
 #ifndef CHIP_VARIANT_ISH5P4
-#define PMU_D3_STATUS			REG32(ISH_PMU_BASE + 0x4)
-#define PMU_D3_BIT_SET			BIT(0)
-#define PMU_D3_BIT_RISING_EDGE_STATUS	BIT(1)
-#define PMU_D3_BIT_FALLING_EDGE_STATUS	BIT(2)
-#define PMU_D3_BIT_RISING_EDGE_MASK	BIT(3)
-#define PMU_D3_BIT_FALLING_EDGE_MASK	BIT(4)
-#define PMU_BME_BIT_SET		BIT(5)
-#define PMU_BME_BIT_RISING_EDGE_STATUS	BIT(6)
+#define PMU_D3_STATUS REG32(ISH_PMU_BASE + 0x4)
+#define PMU_D3_BIT_SET BIT(0)
+#define PMU_D3_BIT_RISING_EDGE_STATUS BIT(1)
+#define PMU_D3_BIT_FALLING_EDGE_STATUS BIT(2)
+#define PMU_D3_BIT_RISING_EDGE_MASK BIT(3)
+#define PMU_D3_BIT_FALLING_EDGE_MASK BIT(4)
+#define PMU_BME_BIT_SET BIT(5)
+#define PMU_BME_BIT_RISING_EDGE_STATUS BIT(6)
 #define PMU_BME_BIT_FALLING_EDGE_STATUS BIT(7)
-#define PMU_BME_BIT_RISING_EDGE_MASK	BIT(8)
-#define PMU_BME_BIT_FALLING_EDGE_MASK	BIT(9)
+#define PMU_BME_BIT_RISING_EDGE_MASK BIT(8)
+#define PMU_BME_BIT_FALLING_EDGE_MASK BIT(9)
 #else
-#define PMU_STATUS_REG_ADDR		(ISH_PMU_BASE + 0xF00)
-#define PMU_SCRATCHPAD0_REG_ADDR	(ISH_PMU_BASE + 0xF04)
-#define PMU_SCRATCHPAD1_REG_ADDR	(ISH_PMU_BASE + 0xF08)
-#define PMU_PG_EN_REG_ADDR		(ISH_PMU_BASE + 0xF10)
-#define PMU_PMC_HOST_RST_CTL		REG32(ISH_PMU_BASE + 0xF20)
-#define PMU_SW_PG_REQ			REG32(ISH_PMU_BASE + 0xF14)
-#define PMU_PMC_PG_WAKE			REG32(ISH_PMU_BASE + 0xF18)
-#define PMU_INTERNAL_PCE		REG32(ISH_PMU_BASE + 0xF30)
-#define PMU_D3_STATUS			REG32(ISH_PMU_BASE + 0x100)
-#define PMU_HOST_RST_B			BIT(0)
-#define PMU_PCE_SHADOW_MASK		0x1F
-#define PMU_PCE_PG_ALLOWED		BIT(4)
-#define PMU_PCE_CHANGE_MASK		BIT(9)
-#define PMU_PCE_CHANGE_DETECTED		BIT(8)
-#define PMU_PCE_PMCRE			BIT(0)
-#define PMU_SW_PG_REQ_B_VAL		BIT(0)
-#define PMU_SW_PG_REQ_B_RISE		BIT(1)
-#define PMU_SW_PG_REQ_B_FALL		BIT(2)
-#define PMU_PMC_PG_WAKE_VAL		BIT(0)
-#define PMU_PMC_PG_WAKE_RISE		BIT(1)
-#define PMU_PMC_PG_WAKE_FALL		BIT(2)
-#define PMU_PCE_PG_ALLOWED		BIT(4)
-#define PMU_D0I3_ENABLE_MASK		BIT(23)
-#define PMU_D3_BIT_SET			BIT(16)
-#define PMU_D3_BIT_RISING_EDGE_STATUS	BIT(17)
-#define PMU_D3_BIT_FALLING_EDGE_STATUS	BIT(18)
-#define PMU_D3_BIT_RISING_EDGE_MASK	BIT(19)
-#define PMU_D3_BIT_FALLING_EDGE_MASK	BIT(20)
-#define PMU_BME_BIT_SET			BIT(24)
-#define PMU_BME_BIT_RISING_EDGE_STATUS	BIT(25)
-#define PMU_BME_BIT_FALLING_EDGE_STATUS	BIT(26)
-#define PMU_BME_BIT_RISING_EDGE_MASK	BIT(27)
-#define PMU_BME_BIT_FALLING_EDGE_MASK	BIT(28)
+#define PMU_STATUS_REG_ADDR (ISH_PMU_BASE + 0xF00)
+#define PMU_SCRATCHPAD0_REG_ADDR (ISH_PMU_BASE + 0xF04)
+#define PMU_SCRATCHPAD1_REG_ADDR (ISH_PMU_BASE + 0xF08)
+#define PMU_PG_EN_REG_ADDR (ISH_PMU_BASE + 0xF10)
+#define PMU_PMC_HOST_RST_CTL REG32(ISH_PMU_BASE + 0xF20)
+#define PMU_SW_PG_REQ REG32(ISH_PMU_BASE + 0xF14)
+#define PMU_PMC_PG_WAKE REG32(ISH_PMU_BASE + 0xF18)
+#define PMU_INTERNAL_PCE REG32(ISH_PMU_BASE + 0xF30)
+#define PMU_D3_STATUS REG32(ISH_PMU_BASE + 0x100)
+#define PMU_D3_STATUS_1 REG32(ISH_PMU_BASE + 0x104)
+#define PMU_HOST_RST_B BIT(0)
+#define PMU_PCE_SHADOW_MASK 0x1F
+#define PMU_PCE_PG_ALLOWED BIT(4)
+#define PMU_PCE_CHANGE_MASK BIT(9)
+#define PMU_PCE_CHANGE_DETECTED BIT(8)
+#define PMU_PCE_PMCRE BIT(0)
+#define PMU_SW_PG_REQ_B_VAL BIT(0)
+#define PMU_SW_PG_REQ_B_RISE BIT(1)
+#define PMU_SW_PG_REQ_B_FALL BIT(2)
+#define PMU_PMC_PG_WAKE_VAL BIT(0)
+#define PMU_PMC_PG_WAKE_RISE BIT(1)
+#define PMU_PMC_PG_WAKE_FALL BIT(2)
+#define PMU_PCE_PG_ALLOWED BIT(4)
+#define PMU_D0I3_ENABLE_MASK BIT(23)
+#define PMU_D3_BIT_SET BIT(16)
+#define PMU_D3_BIT_RISING_EDGE_STATUS BIT(17)
+#define PMU_D3_BIT_FALLING_EDGE_STATUS BIT(18)
+#define PMU_D3_BIT_RISING_EDGE_MASK BIT(19)
+#define PMU_D3_BIT_FALLING_EDGE_MASK BIT(20)
+#define PMU_BME_BIT_SET BIT(24)
+#define PMU_BME_BIT_RISING_EDGE_STATUS BIT(25)
+#define PMU_BME_BIT_FALLING_EDGE_STATUS BIT(26)
+#define PMU_BME_BIT_RISING_EDGE_MASK BIT(27)
+#define PMU_BME_BIT_FALLING_EDGE_MASK BIT(28)
+#define PMU_REG_MASK_D3_RISE REG32(ISH_PMU_BASE + 0x200)
+#define PMU_REG_MASK_D3_FALL REG32(ISH_PMU_BASE + 0x208)
+#define PMU_REG_MASK_BME_RISE REG32(ISH_PMU_BASE + 0x220)
+#define PMU_REG_MASK_BME_FALL REG32(ISH_PMU_BASE + 0x228)
 #endif
 
-#define PMU_ISH_FABRIC_CNT		REG32(ISH_PMU_BASE + 0x18)
+#define PMU_GPIO_WAKE_MASK0 REG32(ISH_PMU_BASE + 0x250)
+#define PMU_GPIO_WAKE_MASK1 REG32(ISH_PMU_BASE + 0x254)
+
+#define PMU_ISH_FABRIC_CNT REG32(ISH_PMU_BASE + 0x18)
 
-#define PMU_PGCB_CLKGATE_CTRL		REG32(ISH_PMU_BASE + 0x54)
+#define PMU_PGCB_CLKGATE_CTRL REG32(ISH_PMU_BASE + 0x54)
 
-#define PMU_VNN_REQ			REG32(ISH_PMU_BASE + 0x3c)
-#define VNN_REQ_IPC_HOST_WRITE		BIT(3) /* Power for IPC host write */
+#define PMU_VNN_REQ REG32(ISH_PMU_BASE + 0x3c)
+#define VNN_REQ_IPC_HOST_WRITE BIT(3) /* Power for IPC host write */
 
-#define PMU_VNN_REQ_ACK		REG32(ISH_PMU_BASE + 0x40)
-#define PMU_VNN_REQ_ACK_STATUS		BIT(0) /* VNN req and ack status */
+#define PMU_VNN_REQ_ACK REG32(ISH_PMU_BASE + 0x40)
+#define PMU_VNN_REQ_ACK_STATUS BIT(0) /* VNN req and ack status */
 
-#define PMU_VNNAON_RED			REG32(ISH_PMU_BASE + 0x58)
+#define PMU_VNNAON_RED REG32(ISH_PMU_BASE + 0x58)
 
-#define PMU_RST_PREP			REG32(ISH_PMU_BASE + 0x5c)
-#define PMU_RST_PREP_GET		BIT(0)
-#define PMU_RST_PREP_AVAIL		BIT(1)
-#define PMU_RST_PREP_INT_MASK		BIT(31)
+#define PMU_RST_PREP REG32(ISH_PMU_BASE + 0x5c)
+#define PMU_RST_PREP_GET BIT(0)
+#define PMU_RST_PREP_AVAIL BIT(1)
+#define PMU_RST_PREP_INT_MASK BIT(31)
 
-#define VNN_ID_DMA0             4
-#define VNN_ID_DMA(chan)        (VNN_ID_DMA0 + chan)
+#define VNN_ID_DMA0 4
+#define VNN_ID_DMA(chan) (VNN_ID_DMA0 + chan)
+#define VNN_ID_SIDEBAND 21
 
 /* OCP registers */
-#define OCP_IOSF2OCP_BRIDGE      (ISH_OCP_BASE + 0x9400)
-#define OCP_AGENT_CONTROL        REG32(OCP_IOSF2OCP_BRIDGE + 0x20)
-#define OCP_RESPONSE_TO_DISABLE  0xFFFFF8FF
+#define OCP_IOSF2OCP_BRIDGE (ISH_OCP_BASE + 0x9400)
+#define OCP_AGENT_CONTROL REG32(OCP_IOSF2OCP_BRIDGE + 0x20)
+#define OCP_RESPONSE_TO_DISABLE 0xFFFFF8FF
 
 /* MISC registers */
-#define MISC_REG_BASE            ISH_MISC_BASE
-#define DMA_REG_BASE             ISH_DMA_BASE
+#define MISC_REG_BASE ISH_MISC_BASE
+#define DMA_REG_BASE ISH_DMA_BASE
 #ifndef CHIP_VARIANT_ISH5P4
-#define MISC_CHID_CFG_REG        REG32(MISC_REG_BASE + 0x40)
-#define MISC_DMA_CTL_REG(ch)     REG32(MISC_REG_BASE + (4 * (ch)))
-#define MISC_SRC_FILLIN_DMA(ch)  REG32(MISC_REG_BASE + 0x20 + (4 * (ch)))
-#define MISC_DST_FILLIN_DMA(ch)  REG32(MISC_REG_BASE + 0x80 + (4 * (ch)))
-#define MISC_ISH_ECC_ERR_SRESP   REG32(MISC_REG_BASE + 0x94)
+#define MISC_CHID_CFG_REG REG32(MISC_REG_BASE + 0x40)
+#define MISC_DMA_CTL_REG(ch) REG32(MISC_REG_BASE + (4 * (ch)))
+#define MISC_SRC_FILLIN_DMA(ch) REG32(MISC_REG_BASE + 0x20 + (4 * (ch)))
+#define MISC_DST_FILLIN_DMA(ch) REG32(MISC_REG_BASE + 0x80 + (4 * (ch)))
+#define MISC_ISH_ECC_ERR_SRESP REG32(MISC_REG_BASE + 0x94)
 #else
-#define DMA_MISC_OFFSET          0x1000
-#define DMA_MISC_BASE            (DMA_REG_BASE + DMA_MISC_OFFSET)
-#define MISC_CHID_CFG_REG        REG32(DMA_MISC_BASE + 0x400)
-#define MISC_DMA_CTL_REG(ch)     REG32(DMA_MISC_BASE + (4 * (ch)))
-#define MISC_SRC_FILLIN_DMA(ch)  REG32(DMA_MISC_BASE + 0x100 + (4 * (ch)))
-#define MISC_DST_FILLIN_DMA(ch)  REG32(DMA_MISC_BASE + 0x200 + (4 * (ch)))
-#define MISC_ISH_ECC_ERR_SRESP   REG32(DMA_MISC_BASE + 0x404)
+#define DMA_MISC_OFFSET 0x1000
+#define DMA_MISC_BASE (DMA_REG_BASE + DMA_MISC_OFFSET)
+#define MISC_CHID_CFG_REG REG32(DMA_MISC_BASE + 0x400)
+#define MISC_DMA_CTL_REG(ch) REG32(DMA_MISC_BASE + (4 * (ch)))
+#define MISC_SRC_FILLIN_DMA(ch) REG32(DMA_MISC_BASE + 0x100 + (4 * (ch)))
+#define MISC_DST_FILLIN_DMA(ch) REG32(DMA_MISC_BASE + 0x200 + (4 * (ch)))
+#define MISC_ISH_ECC_ERR_SRESP REG32(DMA_MISC_BASE + 0x404)
 #endif
-#define MISC_ISH_RTC_COUNTER0	REG32(ISH_MISC_BASE + 0x70)
-#define MISC_ISH_RTC_COUNTER1	REG32(ISH_MISC_BASE + 0x74)
+#define MISC_ISH_RTC_COUNTER0 REG32(ISH_MISC_BASE + 0x70)
+#define MISC_ISH_RTC_COUNTER1 REG32(ISH_MISC_BASE + 0x74)
 
 /* DMA registers */
-#define DMA_CH_REGS_SIZE              0x58
-#define DMA_CLR_BLOCK_REG             REG32(DMA_REG_BASE + 0x340)
-#define DMA_CLR_ERR_REG               REG32(DMA_REG_BASE + 0x358)
-#define DMA_EN_REG_ADDR               (DMA_REG_BASE + 0x3A0)
-#define DMA_EN_REG                    REG32(DMA_EN_REG_ADDR)
-#define DMA_CFG_REG                   REG32(DMA_REG_BASE + 0x398)
-#define DMA_PSIZE_01                  REG32(DMA_REG_BASE + 0x400)
-#define DMA_PSIZE_CHAN0_SIZE          512
-#define DMA_PSIZE_CHAN0_OFFSET        0
-#define DMA_PSIZE_CHAN1_SIZE          128
-#define DMA_PSIZE_CHAN1_OFFSET        13
-#define DMA_PSIZE_UPDATE	      BIT(26)
-#define DMA_MAX_CHANNEL               4
-#define DMA_SAR(chan)                 REG32(chan + 0x000)
-#define DMA_DAR(chan)                 REG32(chan + 0x008)
-#define DMA_LLP(chan)                 REG32(chan + 0x010)
-#define DMA_CTL_LOW(chan)             REG32(chan + 0x018)
-#define DMA_CTL_HIGH(chan)            REG32(chan + 0x018 + 0x4)
-#define DMA_CTL_INT_ENABLE	      BIT(0)
-#define DMA_CTL_DST_TR_WIDTH_SHIFT    1
-#define DMA_CTL_SRC_TR_WIDTH_SHIFT    4
-#define DMA_CTL_DINC_SHIFT            7
-#define DMA_CTL_SINC_SHIFT            9
-#define DMA_CTL_ADDR_INC              0
-#define DMA_CTL_DEST_MSIZE_SHIFT      11
-#define DMA_CTL_SRC_MSIZE_SHIFT       14
-#define DMA_CTL_TT_FC_SHIFT           20
-#define DMA_CTL_TT_FC_M2M_DMAC        0
-#define DMA_ENABLE		      BIT(0)
-#define DMA_CH_EN_BIT(n)	      BIT(n)
-#define DMA_CH_EN_WE_BIT(n)	      BIT(8 + (n))
-#define DMA_MAX_BLOCK_SIZE	      (4096)
-#define SRC_TR_WIDTH                  2
-#define SRC_BURST_SIZE                3
-#define DEST_TR_WIDTH                 2
-#define DEST_BURST_SIZE               3
-
-#define PMU_MASK_EVENT			REG32(ISH_PMU_BASE + 0x10)
-#define PMU_MASK_EVENT_BIT_GPIO(pin)	BIT(pin)
-#define PMU_MASK_EVENT_BIT_HPET	BIT(16)
-#define PMU_MASK_EVENT_BIT_IPC		BIT(17)
-#define PMU_MASK_EVENT_BIT_D3		BIT(18)
-#define PMU_MASK_EVENT_BIT_DMA		BIT(19)
-#define PMU_MASK_EVENT_BIT_I2C0	BIT(20)
-#define PMU_MASK_EVENT_BIT_I2C1	BIT(21)
-#define PMU_MASK_EVENT_BIT_SPI		BIT(22)
-#define PMU_MASK_EVENT_BIT_UART	BIT(23)
-#define PMU_MASK_EVENT_BIT_ALL		(0xffffffff)
-
-#define PMU_RF_ROM_PWR_CTRL		REG32(ISH_PMU_BASE + 0x30)
-
-#define PMU_LDO_CTRL			REG32(ISH_PMU_BASE + 0x44)
-#define PMU_LDO_ENABLE_BIT		BIT(0)
-#define PMU_LDO_RETENTION_BIT		BIT(1)
-#define PMU_LDO_CALIBRATION_BIT	BIT(2)
-#define PMU_LDO_READY_BIT		BIT(3)
+#define DMA_CH_REGS_SIZE 0x58
+#define DMA_CLR_BLOCK_REG REG32(DMA_REG_BASE + 0x340)
+#define DMA_CLR_ERR_REG REG32(DMA_REG_BASE + 0x358)
+#define DMA_EN_REG_ADDR (DMA_REG_BASE + 0x3A0)
+#define DMA_EN_REG REG32(DMA_EN_REG_ADDR)
+#define DMA_CFG_REG REG32(DMA_REG_BASE + 0x398)
+#define DMA_PSIZE_01 REG32(DMA_REG_BASE + 0x400)
+#define DMA_PSIZE_CHAN0_SIZE 512
+#define DMA_PSIZE_CHAN0_OFFSET 0
+#define DMA_PSIZE_CHAN1_SIZE 128
+#define DMA_PSIZE_CHAN1_OFFSET 13
+#define DMA_PSIZE_UPDATE BIT(26)
+#define DMA_MAX_CHANNEL 4
+#define DMA_SAR(chan) REG32(chan + 0x000)
+#define DMA_DAR(chan) REG32(chan + 0x008)
+#define DMA_LLP(chan) REG32(chan + 0x010)
+#define DMA_CTL_LOW(chan) REG32(chan + 0x018)
+#define DMA_CTL_HIGH(chan) REG32(chan + 0x018 + 0x4)
+#define DMA_CTL_INT_ENABLE BIT(0)
+#define DMA_CTL_DST_TR_WIDTH_SHIFT 1
+#define DMA_CTL_SRC_TR_WIDTH_SHIFT 4
+#define DMA_CTL_DINC_SHIFT 7
+#define DMA_CTL_SINC_SHIFT 9
+#define DMA_CTL_ADDR_INC 0
+#define DMA_CTL_DEST_MSIZE_SHIFT 11
+#define DMA_CTL_SRC_MSIZE_SHIFT 14
+#define DMA_CTL_TT_FC_SHIFT 20
+#define DMA_CTL_TT_FC_M2M_DMAC 0
+#define DMA_ENABLE BIT(0)
+#define DMA_CH_EN_BIT(n) BIT(n)
+#define DMA_CH_EN_WE_BIT(n) BIT(8 + (n))
+#define DMA_MAX_BLOCK_SIZE (4096)
+#define SRC_TR_WIDTH 2
+#define SRC_BURST_SIZE 3
+#define DEST_TR_WIDTH 2
+#define DEST_BURST_SIZE 3
+
+#define PMU_MASK_EVENT REG32(ISH_PMU_BASE + 0x10)
+#define PMU_MASK_EVENT2 REG32(ISH_PMU_BASE + 0x4C)
+#define PMU_MASK_EVENT_BIT_GPIO(pin) BIT(pin)
+#define PMU_MASK_EVENT_BIT_HPET BIT(16)
+#define PMU_MASK_EVENT_BIT_IPC BIT(17)
+#define PMU_MASK_EVENT_BIT_D3 BIT(18)
+#define PMU_MASK_EVENT_BIT_DMA BIT(19)
+#define PMU_MASK_EVENT_BIT_I2C0 BIT(20)
+#define PMU_MASK_EVENT_BIT_I2C1 BIT(21)
+#define PMU_MASK_EVENT_BIT_SPI BIT(22)
+#define PMU_MASK_EVENT_BIT_UART BIT(23)
+#define PMU_MASK_EVENT_BIT_ALL (0xffffffff)
+#define PMU_MASK_EVENT2_SRAM_ERASE1 BIT(3)
+#define PMU_MASK_EVENT2_SRAM_ERASE0 BIT(4)
+#define PMU_MASK_EVENT2_ISOL_ACK_RISE BIT(14)
+#define PMU_MASK_EVENT2_ISOL_ACK_FALL BIT(15)
+#define PMU_MASK_EVENT2_HOST_RST_RISE BIT(16)
+#define PMU_MASK_EVENT2_HOST_RST_FALL BIT(17)
+#define PMU_MASK2_ALL_EVENTS                                             \
+	(PMU_MASK_EVENT2_SRAM_ERASE0 | PMU_MASK_EVENT2_SRAM_ERASE1 |     \
+	 PMU_MASK_EVENT2_ISOL_ACK_RISE | PMU_MASK_EVENT2_ISOL_ACK_FALL | \
+	 PMU_MASK_EVENT2_HOST_RST_RISE | PMU_MASK_EVENT2_HOST_RST_FALL)
+
+#define PMU_RF_ROM_PWR_CTRL REG32(ISH_PMU_BASE + 0x30)
+
+#define PMU_LDO_CTRL REG32(ISH_PMU_BASE + 0x44)
+#define PMU_LDO_ENABLE_BIT BIT(0)
+#define PMU_LDO_RETENTION_BIT BIT(1)
+#define PMU_LDO_CALIBRATION_BIT BIT(2)
+#define PMU_LDO_READY_BIT BIT(3)
 
 /* CCU Registers */
-#define CCU_TCG_EN		REG32(ISH_CCU_BASE + 0x0)
-#define CCU_BCG_EN		REG32(ISH_CCU_BASE + 0x4)
+#define CCU_TCG_EN REG32(ISH_CCU_BASE + 0x0)
+#define CCU_BCG_EN REG32(ISH_CCU_BASE + 0x4)
 #ifndef CHIP_VARIANT_ISH5P4
-#define CCU_WDT_CD		REG32(ISH_CCU_BASE + 0x8)
-#define CCU_RST_HST		REG32(ISH_CCU_BASE + 0x34) /* Reset history */
-#define CCU_TCG_ENABLE		REG32(ISH_CCU_BASE + 0x38)
-#define CCU_BCG_ENABLE		REG32(ISH_CCU_BASE + 0x3c)
+#define CCU_WDT_CD REG32(ISH_CCU_BASE + 0x8)
+#define CCU_RST_HST REG32(ISH_CCU_BASE + 0x34) /* Reset history */
+#define CCU_TCG_ENABLE REG32(ISH_CCU_BASE + 0x38)
+#define CCU_BCG_ENABLE REG32(ISH_CCU_BASE + 0x3c)
 #else
-#define CCU_WDT_CD		REG32(ISH_CCU_BASE + 0x7c)
-#define CCU_RST_HST		REG32(ISH_CCU_BASE + 0x3c) /* Reset history */
-#define CCU_TCG_ENABLE		REG32(ISH_CCU_BASE + 0x40)
-#define CCU_BCG_ENABLE		REG32(ISH_CCU_BASE + 0x44)
+#define CCU_WDT_CD REG32(ISH_CCU_BASE + 0x7c)
+#define CCU_RST_HST REG32(ISH_CCU_BASE + 0x3c) /* Reset history */
+#define CCU_TCG_ENABLE REG32(ISH_CCU_BASE + 0x40)
+#define CCU_BCG_ENABLE REG32(ISH_CCU_BASE + 0x44)
 #endif
-#define CCU_BCG_MIA		REG32(ISH_CCU_BASE + 0x4)
-#define CCU_BCG_UART		REG32(ISH_CCU_BASE + 0x8)
-#define CCU_BCG_I2C		REG32(ISH_CCU_BASE + 0xc)
-#define CCU_BCG_SPI		REG32(ISH_CCU_BASE + 0x10)
-#define CCU_BCG_GPIO		REG32(ISH_CCU_BASE + 0x14)
-#define CCU_BCG_DMA		REG32(ISH_CCU_BASE + 0x28)
-#define CCU_AONCG_EN		REG32(ISH_CCU_BASE + 0xdc)
-#define CCU_BCG_BIT_MIA	BIT(0)
-#define CCU_BCG_BIT_DMA	BIT(1)
-#define CCU_BCG_BIT_I2C0	BIT(2)
-#define CCU_BCG_BIT_I2C1	BIT(3)
-#define CCU_BCG_BIT_SPI	BIT(4)
-#define CCU_BCG_BIT_SRAM	BIT(5)
-#define CCU_BCG_BIT_HPET	BIT(6)
-#define CCU_BCG_BIT_UART	BIT(7)
-#define CCU_BCG_BIT_GPIO	BIT(8)
-#define CCU_BCG_BIT_I2C2	BIT(9)
-#define CCU_BCG_BIT_SPI2	BIT(10)
-#define CCU_BCG_BIT_ALL	(0x7ff)
+#define CCU_BCG_MIA REG32(ISH_CCU_BASE + 0x4)
+#define CCU_BCG_UART REG32(ISH_CCU_BASE + 0x8)
+#define CCU_BCG_I2C REG32(ISH_CCU_BASE + 0xc)
+#define CCU_BCG_SPI REG32(ISH_CCU_BASE + 0x10)
+#define CCU_BCG_GPIO REG32(ISH_CCU_BASE + 0x14)
+#define CCU_BCG_DMA REG32(ISH_CCU_BASE + 0x28)
+#define CCU_AONCG_EN REG32(ISH_CCU_BASE + 0xdc)
+#define CCU_BCG_BIT_MIA BIT(0)
+#define CCU_BCG_BIT_DMA BIT(1)
+#define CCU_BCG_BIT_I2C0 BIT(2)
+#define CCU_BCG_BIT_I2C1 BIT(3)
+#define CCU_BCG_BIT_SPI BIT(4)
+#define CCU_BCG_BIT_SRAM BIT(5)
+#define CCU_BCG_BIT_HPET BIT(6)
+#define CCU_BCG_BIT_UART BIT(7)
+#define CCU_BCG_BIT_GPIO BIT(8)
+#define CCU_BCG_BIT_I2C2 BIT(9)
+#define CCU_BCG_BIT_SPI2 BIT(10)
+#define CCU_BCG_BIT_ALL (0x7ff)
 
 /* Bitmasks for CCU_RST_HST */
-#define CCU_SW_RST	BIT(0)  /* Used to indicate SW reset */
-#define CCU_WDT_RST	BIT(1)  /* Used to indicate WDT reset */
-#define CCU_MIASS_RST	BIT(2)  /* Used to indicate UIA shutdown reset */
-#define CCU_SRECC_RST	BIT(3)  /* Used to indicate SRAM ECC reset */
+#define CCU_SW_RST BIT(0) /* Used to indicate SW reset */
+#define CCU_WDT_RST BIT(1) /* Used to indicate WDT reset */
+#define CCU_MIASS_RST BIT(2) /* Used to indicate UIA shutdown reset */
+#define CCU_SRECC_RST BIT(3) /* Used to indicate SRAM ECC reset */
 
 /* Fabric Agent Status register */
-#define FABRIC_AGENT_STATUS		REG32(ISH_OCP_BASE + 0x7828)
+#define FABRIC_AGENT_STATUS REG32(ISH_OCP_BASE + 0x7828)
 #define FABRIC_INBAND_ERR_SECONDARY_BIT BIT(29)
-#define FABRIC_INBAND_ERR_PRIMARY_BIT	BIT(28)
-#define FABRIC_M_ERR_BIT		BIT(24)
-#define FABRIC_MIA_STATUS_BIT_ERR	(FABRIC_INBAND_ERR_SECONDARY_BIT | \
-					 FABRIC_INBAND_ERR_PRIMARY_BIT | \
-					 FABRIC_M_ERR_BIT)
+#define FABRIC_INBAND_ERR_PRIMARY_BIT BIT(28)
+#define FABRIC_M_ERR_BIT BIT(24)
+#define FABRIC_MIA_STATUS_BIT_ERR                                          \
+	(FABRIC_INBAND_ERR_SECONDARY_BIT | FABRIC_INBAND_ERR_PRIMARY_BIT | \
+	 FABRIC_M_ERR_BIT)
 
 /* CSME Registers */
 #ifdef CHIP_VARIANT_ISH5P4
-#define SEC_OFFSET			0x10000
+#define SEC_OFFSET 0x10000
 #else
-#define SEC_OFFSET			0x0
+#define SEC_OFFSET 0x0
 #endif
-#define ISH_RST_REG			REG32(ISH_IPC_BASE + SEC_OFFSET + 0x44)
-#define IPC_PIMR_CIM_SEC		(ISH_IPC_BASE + SEC_OFFSET + 0x10)
+#define ISH_RST_REG REG32(ISH_IPC_BASE + SEC_OFFSET + 0x44)
+#define IPC_PIMR_CIM_SEC (ISH_IPC_BASE + SEC_OFFSET + 0x10)
 
 /* IOAPIC registers */
-#define IOAPIC_IDX			REG32(ISH_IOAPIC_BASE + 0x0)
-#define IOAPIC_WDW			REG32(ISH_IOAPIC_BASE + 0x10)
+#define IOAPIC_IDX REG32(ISH_IOAPIC_BASE + 0x0)
+#define IOAPIC_WDW REG32(ISH_IOAPIC_BASE + 0x10)
 /* Bare address needed for assembler (ISH_IOAPIC_BASE + 0x40) */
-#define IOAPIC_EOI_REG_ADDR		0xFEC00040
-#define IOAPIC_EOI_REG			REG32(IOAPIC_EOI_REG_ADDR)
-
-#define IOAPIC_VERSION			(0x1)
-#define IOAPIC_IOREDTBL			(0x10)
-#define IOAPIC_REDTBL_DELMOD_FIXED	(0x00000000)
-#define IOAPIC_REDTBL_DESTMOD_PHYS	(0x00000000)
-#define IOAPIC_REDTBL_INTPOL_HIGH	(0x00000000)
-#define IOAPIC_REDTBL_INTPOL_LOW	(0x00002000)
-#define IOAPIC_REDTBL_IRR		(0x00004000)
-#define IOAPIC_REDTBL_TRIGGER_EDGE	(0x00000000)
-#define IOAPIC_REDTBL_TRIGGER_LEVEL	(0x00008000)
-#define IOAPIC_REDTBL_MASK		(0x00010000)
+#define IOAPIC_EOI_REG_ADDR 0xFEC00040
+#define IOAPIC_EOI_REG REG32(IOAPIC_EOI_REG_ADDR)
+
+#define IOAPIC_VERSION (0x1)
+#define IOAPIC_IOREDTBL (0x10)
+#define IOAPIC_REDTBL_DELMOD_FIXED (0x00000000)
+#define IOAPIC_REDTBL_DESTMOD_PHYS (0x00000000)
+#define IOAPIC_REDTBL_INTPOL_HIGH (0x00000000)
+#define IOAPIC_REDTBL_INTPOL_LOW (0x00002000)
+#define IOAPIC_REDTBL_IRR (0x00004000)
+#define IOAPIC_REDTBL_TRIGGER_EDGE (0x00000000)
+#define IOAPIC_REDTBL_TRIGGER_LEVEL (0x00008000)
+#define IOAPIC_REDTBL_MASK (0x00010000)
 
 /* WDT (Watchdog Timer) Registers */
-#define WDT_CONTROL			REG32(ISH_WDT_BASE + 0x0)
-#define WDT_RELOAD			REG32(ISH_WDT_BASE + 0x4)
-#define WDT_VALUES			REG32(ISH_WDT_BASE + 0x8)
-#define WDT_CONTROL_ENABLE_BIT		BIT(17)
+#define WDT_CONTROL REG32(ISH_WDT_BASE + 0x0)
+#define WDT_RELOAD REG32(ISH_WDT_BASE + 0x4)
+#define WDT_VALUES REG32(ISH_WDT_BASE + 0x8)
+#define WDT_CONTROL_ENABLE_BIT BIT(17)
 
 /* LAPIC registers */
 /* Bare address needed for assembler (ISH_LAPIC_BASE + 0xB0) */
-#define LAPIC_EOI_REG_ADDR		0xFEE000B0
-#define LAPIC_EOI_REG			REG32(LAPIC_EOI_REG_ADDR)
-#define LAPIC_ISR_REG			REG32(ISH_LAPIC_BASE + 0x100)
-#define LAPIC_ISR_LAST_REG		REG32(ISH_LAPIC_BASE + 0x170)
-#define LAPIC_IRR_REG			REG32(ISH_LAPIC_BASE + 0x200)
-#define LAPIC_ESR_REG			REG32(ISH_LAPIC_BASE + 0x280)
-#define LAPIC_ERR_RECV_ILLEGAL		BIT(6)
-#define LAPIC_ICR_REG			REG32(ISH_LAPIC_BASE + 0x300)
+#define LAPIC_EOI_REG_ADDR 0xFEE000B0
+#define LAPIC_EOI_REG REG32(LAPIC_EOI_REG_ADDR)
+#define LAPIC_ISR_REG REG32(ISH_LAPIC_BASE + 0x100)
+#define LAPIC_ISR_LAST_REG REG32(ISH_LAPIC_BASE + 0x170)
+#define LAPIC_IRR_REG REG32(ISH_LAPIC_BASE + 0x200)
+#define LAPIC_ESR_REG REG32(ISH_LAPIC_BASE + 0x280)
+#define LAPIC_ERR_RECV_ILLEGAL BIT(6)
+#define LAPIC_ICR_REG REG32(ISH_LAPIC_BASE + 0x300)
 
 /* SRAM control registers */
 #ifndef CHIP_VARIANT_ISH5P4
-#define ISH_SRAM_CTRL_BASE		0x00500000
+#define ISH_SRAM_CTRL_BASE 0x00500000
 #else
-#define ISH_SRAM_CTRL_BASE		0x10500000
+#define ISH_SRAM_CTRL_BASE 0x10500000
 #endif
-#define ISH_SRAM_CTRL_CSFGR		REG32(ISH_SRAM_CTRL_BASE + 0x00)
-#define ISH_SRAM_CTRL_INTR		REG32(ISH_SRAM_CTRL_BASE + 0x04)
-#define ISH_SRAM_CTRL_INTR_MASK	REG32(ISH_SRAM_CTRL_BASE + 0x08)
-#define ISH_SRAM_CTRL_ERASE_CTRL	REG32(ISH_SRAM_CTRL_BASE + 0x0c)
-#define ISH_SRAM_CTRL_ERASE_ADDR	REG32(ISH_SRAM_CTRL_BASE + 0x10)
-#define ISH_SRAM_CTRL_BANK_STATUS	REG32(ISH_SRAM_CTRL_BASE + 0x2c)
+#define ISH_SRAM_CTRL_CSFGR REG32(ISH_SRAM_CTRL_BASE + 0x00)
+#define ISH_SRAM_CTRL_INTR REG32(ISH_SRAM_CTRL_BASE + 0x04)
+#define ISH_SRAM_CTRL_INTR_MASK REG32(ISH_SRAM_CTRL_BASE + 0x08)
+#define ISH_SRAM_CTRL_ERASE_CTRL REG32(ISH_SRAM_CTRL_BASE + 0x0c)
+#define ISH_SRAM_CTRL_ERASE_ADDR REG32(ISH_SRAM_CTRL_BASE + 0x10)
+#define ISH_SRAM_CTRL_BANK_STATUS REG32(ISH_SRAM_CTRL_BASE + 0x2c)
 
 #endif /* __CROS_EC_REGISTERS_H */
diff --git a/chip/ish/system.c b/chip/ish/system.c
index 1e6fe87800..22af124cd9 100644
--- a/chip/ish/system.c
+++ b/chip/ish/system.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,8 +23,8 @@
 #include "util.h"
 
 #define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 int system_is_reboot_warm(void)
 {
@@ -57,8 +57,7 @@ uint32_t chip_read_reset_flags(void)
  * Used when the watchdog timer exceeds max retries and we want to
  * disable ISH completely.
  */
-noreturn
-static void system_halt(void)
+noreturn static void system_halt(void)
 {
 	cflush();
 
@@ -66,9 +65,8 @@ static void system_halt(void)
 		disable_all_interrupts();
 		WDT_CONTROL = 0;
 		CCU_TCG_EN = 1;
-		__asm__ volatile (
-			"cli\n"
-			"hlt\n");
+		__asm__ volatile("cli\n"
+				 "hlt\n");
 	}
 }
 
@@ -90,8 +88,8 @@ void system_reset(int flags)
 	if (flags & SYSTEM_RESET_AP_WATCHDOG) {
 		save_flags |= EC_RESET_FLAG_WATCHDOG;
 		ish_persistent_data.watchdog_counter += 1;
-		if (ish_persistent_data.watchdog_counter
-		    >= CONFIG_WATCHDOG_MAX_RETRIES) {
+		if (ish_persistent_data.watchdog_counter >=
+		    CONFIG_WATCHDOG_MAX_RETRIES) {
 			CPRINTS("Halting ISH due to max watchdog resets");
 			system_halt();
 		}
@@ -147,9 +145,9 @@ int system_set_scratchpad(uint32_t value)
 	return EC_SUCCESS;
 }
 
-uint32_t system_get_scratchpad(void)
+int system_get_scratchpad(uint32_t *unused)
 {
-	return 0;
+	return EC_ERROR_UNIMPLEMENTED;
 }
 
 void system_hibernate(uint32_t seconds, uint32_t microseconds)
@@ -175,19 +173,13 @@ void system_set_image_copy(enum ec_image copy)
 {
 }
 
-#define HBW_FABRIC_BASE		0x10000000
-#define PER0_FABRIC_BASE	0x04000000
-#define AGENT_STS		0x28
-#define ERROR_LOG		0x58
+#define HBW_FABRIC_BASE 0x10000000
+#define PER0_FABRIC_BASE 0x04000000
+#define AGENT_STS 0x28
+#define ERROR_LOG 0x58
 
-static uint16_t hbw_ia_offset[] = {
-	0x1000,
-	0x3400,
-	0x3800,
-	0x5000,
-	0x5800,
-	0x6000
-};
+static uint16_t hbw_ia_offset[] = { 0x1000, 0x3400, 0x3800,
+				    0x5000, 0x5800, 0x6000 };
 
 static inline void clear_register(uint32_t reg)
 {
diff --git a/chip/ish/system_state.h b/chip/ish/system_state.h
index 20de1aaf4b..bcffcf49ee 100644
--- a/chip/ish/system_state.h
+++ b/chip/ish/system_state.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,7 @@
 #ifndef __SYSTEM_STATE_H
 #define __SYSTEM_STATE_H
 
-#define HECI_FIXED_SYSTEM_STATE_ADDR				13
+#define HECI_FIXED_SYSTEM_STATE_ADDR 13
 
 struct ss_subsys_device;
 
diff --git a/chip/ish/system_state_subsys.c b/chip/ish/system_state_subsys.c
index 36b79c747a..76053dcded 100644
--- a/chip/ish/system_state_subsys.c
+++ b/chip/ish/system_state_subsys.c
@@ -1,33 +1,32 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "console.h"
 #include "heci_client.h"
 #include "registers.h"
 #include "system_state.h"
-#include "console.h"
 
 #ifdef SS_SUBSYSTEM_DEBUG
 #define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_LPC, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_LPC, format, ##args)
 #else
 #define CPUTS(outstr)
 #define CPRINTS(format, args...)
 #define CPRINTF(format, args...)
 #endif
 
-
 /* the following "define"s and structures are from host driver
  * and they are slightly modified for look&feel purpose.
  */
-#define SYSTEM_STATE_SUBSCRIBE		0x1
-#define SYSTEM_STATE_STATUS		0x2
-#define SYSTEM_STATE_QUERY_SUBSCRIBERS	0x3
-#define SYSTEM_STATE_STATE_CHANGE_REQ	0x4
+#define SYSTEM_STATE_SUBSCRIBE 0x1
+#define SYSTEM_STATE_STATUS 0x2
+#define SYSTEM_STATE_QUERY_SUBSCRIBERS 0x3
+#define SYSTEM_STATE_STATE_CHANGE_REQ 0x4
 
-#define SUSPEND_STATE_BIT		BIT(1) /* suspend/resume */
+#define SUSPEND_STATE_BIT BIT(1) /* suspend/resume */
 
 /* Cached state of ISH's requested power rails when AP suspends */
 static uint32_t cached_vnn_request;
@@ -67,7 +66,7 @@ struct ss_state_change_req {
  * "struct ss_subsys_device" in it and calls ss_subsys_register_client() like
  * HECI client.
  */
-#define MAX_SS_CLIENTS				HECI_MAX_NUM_OF_CLIENTS
+#define MAX_SS_CLIENTS HECI_MAX_NUM_OF_CLIENTS
 
 struct ss_subsystem_context {
 	uint32_t registered_state;
@@ -103,7 +102,7 @@ static int ss_subsys_suspend(void)
 	for (i = ss_subsys_ctx.num_of_ss_client - 1; i >= 0; i--) {
 		if (ss_subsys_ctx.clients[i]->cbs->suspend)
 			ss_subsys_ctx.clients[i]->cbs->suspend(
-						ss_subsys_ctx.clients[i]);
+				ss_subsys_ctx.clients[i]);
 	}
 
 	/*
@@ -126,8 +125,7 @@ static int ss_subsys_resume(void)
 	/*
 	 * Restore VNN power request from before suspend.
 	 */
-	if (IS_ENABLED(CHIP_FAMILY_ISH5) &&
-	    cached_vnn_request) {
+	if (IS_ENABLED(CHIP_FAMILY_ISH5) && cached_vnn_request) {
 		/* Request all cached power rails that are not already on. */
 		PMU_VNN_REQ = cached_vnn_request & ~PMU_VNN_REQ;
 		/* Wait for power request to get acknowledged */
@@ -138,7 +136,7 @@ static int ss_subsys_resume(void)
 	for (i = 0; i < ss_subsys_ctx.num_of_ss_client; i++) {
 		if (ss_subsys_ctx.clients[i]->cbs->resume)
 			ss_subsys_ctx.clients[i]->cbs->resume(
-						ss_subsys_ctx.clients[i]);
+				ss_subsys_ctx.clients[i]);
 	}
 
 	return EC_SUCCESS;
diff --git a/chip/ish/uart.c b/chip/ish/uart.c
index b0f21cdf5f..0ff03da89a 100644
--- a/chip/ish/uart.c
+++ b/chip/ish/uart.c
@@ -1,36 +1,29 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* UART module for ISH */
+#include "atomic.h"
 #include "common.h"
-#include "math_util.h"
 #include "console.h"
-#include "uart_defs.h"
-#include "atomic.h"
-#include "task.h"
+#include "interrupts.h"
+#include "math_util.h"
 #include "registers.h"
+#include "system.h"
+#include "task.h"
 #include "uart.h"
 #include "uart_defs.h"
-#include "interrupts.h"
-#include "system.h"
 
 #define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_LPC, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_LPC, format, ##args)
 
 static const uint32_t baud_conf[][BAUD_TABLE_MAX] = {
-	{B9600, 9600},
-	{B57600, 57600},
-	{B115200, 115200},
-	{B921600, 921600},
-	{B2000000, 2000000},
-	{B3000000, 3000000},
-	{B3250000, 3250000},
-	{B3500000, 3500000},
-	{B4000000, 4000000},
-	{B19200, 19200},
+	{ B9600, 9600 },       { B57600, 57600 },     { B115200, 115200 },
+	{ B921600, 921600 },   { B2000000, 2000000 }, { B3000000, 3000000 },
+	{ B3250000, 3250000 }, { B3500000, 3500000 }, { B4000000, 4000000 },
+	{ B19200, 19200 },
 };
 
 static struct uart_ctx uart_ctx[UART_DEVICES] = {
@@ -122,7 +115,7 @@ int uart_read_char(void)
 	return RBR(ISH_DEBUG_UART);
 }
 
-void uart_ec_interrupt(void)
+static void uart_ec_interrupt(void)
 {
 	/* Read input FIFO until empty, then fill output FIFO */
 	uart_process_input();
@@ -146,7 +139,7 @@ static int uart_return_baud_rate_by_id(int baud_rate_id)
 
 static void uart_hw_init(enum UART_PORT id)
 {
-	uint32_t divisor;	/* baud rate divisor */
+	uint32_t divisor; /* baud rate divisor */
 	uint8_t mcr = 0;
 	uint8_t fcr = 0;
 	struct uart_ctx *ctx = &uart_ctx[id];
@@ -156,7 +149,8 @@ static void uart_hw_init(enum UART_PORT id)
 	divisor = (ctx->input_freq / ctx->baud_rate) >> 4;
 	if (IS_ENABLED(CONFIG_ISH_DW_UART)) {
 		/* calculate the fractional part */
-		fraction = ceil_for(ctx->input_freq, ctx->baud_rate) - (divisor << 4);
+		fraction = ceil_for(ctx->input_freq, ctx->baud_rate) -
+			   (divisor << 4);
 	} else {
 		MUL(ctx->id) = (divisor * ctx->baud_rate);
 		DIV(ctx->id) = (ctx->input_freq / 16);
@@ -189,8 +183,7 @@ static void uart_hw_init(enum UART_PORT id)
 		fcr = FCR_FIFO_SIZE_64 | FCR_ITL_FIFO_64_BYTES_1;
 
 	/* configure FIFOs */
-	FCR(ctx->id) = (fcr | FCR_FIFO_ENABLE
-			| FCR_RESET_RX | FCR_RESET_TX);
+	FCR(ctx->id) = (fcr | FCR_FIFO_ENABLE | FCR_RESET_RX | FCR_RESET_TX);
 
 	if (!IS_ENABLED(CONFIG_ISH_DW_UART))
 		/* enable UART unit */
@@ -229,8 +222,8 @@ static void uart_stop_hw(enum UART_PORT id)
 
 	if (!IS_ENABLED(CONFIG_ISH_DW_UART)) {
 		/* Manually clearing the fifo from possible noise.
-	 	 * Entering D0i3 when fifo is not cleared may result in a hang.
-	 	 */
+		 * Entering D0i3 when fifo is not cleared may result in a hang.
+		 */
 		fifo_len = (FOR(id) & FOR_OCCUPANCY_MASK) >> FOR_OCCUPANCY_OFFS;
 
 		for (i = 0; i < fifo_len; i++)
@@ -264,7 +257,7 @@ static int uart_client_init(enum UART_PORT id, uint32_t baud_rate_id, int flags)
 
 	uart_ctx[id].client_flags = flags;
 
-	deprecated_atomic_and(&uart_ctx[id].uart_state, ~UART_STATE_CG);
+	atomic_and(&uart_ctx[id].uart_state, ~UART_STATE_CG);
 	uart_hw_init(id);
 
 	return EC_SUCCESS;
@@ -280,10 +273,10 @@ static void uart_drv_init(void)
 
 	if (!IS_ENABLED(CONFIG_ISH_DW_UART))
 		/* Enable HSU global interrupts (DMA/U0/U1) and set PMEN bit
-	 	 * to allow PMU to clock gate ISH
-	 	 */
-		HSU_REG_GIEN = (GIEN_DMA_EN | GIEN_UART0_EN
-				| GIEN_UART1_EN | GIEN_PWR_MGMT);
+		 * to allow PMU to clock gate ISH
+		 */
+		HSU_REG_GIEN = (GIEN_DMA_EN | GIEN_UART0_EN | GIEN_UART1_EN |
+				GIEN_PWR_MGMT);
 
 	task_enable_irq(ISH_DEBUG_UART_IRQ);
 }
diff --git a/chip/ish/uart_defs.h b/chip/ish/uart_defs.h
index b573ef7710..581a702d31 100644
--- a/chip/ish/uart_defs.h
+++ b/chip/ish/uart_defs.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,353 +8,342 @@
 #ifndef __CROS_EC_UART_DEFS_H_
 #define __CROS_EC_UART_DEFS_H_
 
-#include <stdint.h>
+#include "atomic.h"
+
 #include <stddef.h>
+#include <stdint.h>
 
-#define UART_ERROR		-1
-#define UART_BUSY		-2
+#define UART_ERROR -1
+#define UART_BUSY -2
 #ifdef CHIP_VARIANT_ISH5P4
-#define UART0_OFFS		(0x00)
-#define UART1_OFFS		(0x2000)
-#define UART2_OFFS		(0x4000)
+#define UART0_OFFS (0x00)
+#define UART1_OFFS (0x2000)
+#define UART2_OFFS (0x4000)
 #else
-#define UART0_OFFS		(0x80)
-#define UART1_OFFS		(0x100)
-#define UART2_OFFS		(0x180)
+#define UART0_OFFS (0x80)
+#define UART1_OFFS (0x100)
+#define UART2_OFFS (0x180)
 #endif
 
-#define HSU_BASE		ISH_UART_BASE
-#define UART0_BASE		(ISH_UART_BASE + UART0_OFFS)
-#define UART1_BASE		(ISH_UART_BASE + UART1_OFFS)
-#define UART2_BASE		(ISH_UART_BASE + UART2_OFFS)
+#define HSU_BASE ISH_UART_BASE
+#define UART0_BASE (ISH_UART_BASE + UART0_OFFS)
+#define UART1_BASE (ISH_UART_BASE + UART1_OFFS)
+#define UART2_BASE (ISH_UART_BASE + UART2_OFFS)
 
-#define UART_REG(size, name, n)					\
-	REG##size(uart_ctx[n].base +					\
+#define UART_REG(size, name, n)      \
+	REG##size(uart_ctx[n].base + \
 		  UART_OFFSET_##name * uart_ctx[n].addr_interval)
 
 /* Register accesses */
-#define LSR(n)			UART_REG(8, LSR, n)
-#define THR(n)			UART_REG(8, THR, n)
-#define RBR(n)			UART_REG(8, RBR, n)
-#define DLL(n)			UART_REG(8, DLL, n)
-#define DLH(n)			UART_REG(8, DLH, n)
-#define IER(n)			UART_REG(8, IER, n)
-#define IIR(n)			UART_REG(8, IIR, n)
-#define FCR(n)			UART_REG(8, FCR, n)
-#define LCR(n)			UART_REG(8, LCR, n)
-#define MCR(n)			UART_REG(8, MCR, n)
-#define MSR(n)			UART_REG(8, MSR, n)
-#define DLF(n)			UART_REG(8, DLF, n)
-#define FOR(n)			UART_REG(32, FOR, n)
-#define ABR(n)			UART_REG(32, ABR, n)
-#define PS(n)			UART_REG(32, PS, n)
-#define MUL(n)			UART_REG(32, MUL, n)
-#define DIV(n)			UART_REG(32, DIV, n)
+#define LSR(n) UART_REG(8, LSR, n)
+#define THR(n) UART_REG(8, THR, n)
+#define RBR(n) UART_REG(8, RBR, n)
+#define DLL(n) UART_REG(8, DLL, n)
+#define DLH(n) UART_REG(8, DLH, n)
+#define IER(n) UART_REG(8, IER, n)
+#define IIR(n) UART_REG(8, IIR, n)
+#define FCR(n) UART_REG(8, FCR, n)
+#define LCR(n) UART_REG(8, LCR, n)
+#define MCR(n) UART_REG(8, MCR, n)
+#define MSR(n) UART_REG(8, MSR, n)
+#define DLF(n) UART_REG(8, DLF, n)
+#define FOR(n) UART_REG(32, FOR, n)
+#define ABR(n) UART_REG(32, ABR, n)
+#define PS(n) UART_REG(32, PS, n)
+#define MUL(n) UART_REG(32, MUL, n)
+#define DIV(n) UART_REG(32, DIV, n)
 
 #ifdef CONFIG_ISH_DW_UART
 /*
  * RBR: Receive Buffer register     (BLAB bit = 0)
  */
-#define UART_OFFSET_RBR		(0x00)
+#define UART_OFFSET_RBR (0x00)
 
 /*
  * THR: Transmit Holding register   (BLAB bit = 0)
  */
-#define UART_OFFSET_THR		(0x00)
+#define UART_OFFSET_THR (0x00)
 
 /*
  * DLL: Divisor Latch Reg. low byte  (BLAB bit = 1)
  * baud rate = (serial clock freq) / (16 * divisor)
  */
-#define UART_OFFSET_DLL		(0x00)
+#define UART_OFFSET_DLL (0x00)
 
 /*
  * DLH: Divisor Latch Reg. high byte (BLAB bit = 1)
  */
-#define UART_OFFSET_DLH		(0x04)
+#define UART_OFFSET_DLH (0x04)
 
 /*
  * IER: Interrupt Enable register   (BLAB bit = 0)
  */
-#define UART_OFFSET_IER		(0x04)
+#define UART_OFFSET_IER (0x04)
 
-#define IER_RECV		(0x01)  /* Receive Data Available */
-#define IER_TDRQ		(0x02)  /* Transmit Holding Register Empty */
-#define IER_LINE_STAT		(0x04)  /* Receiver Line Status */
-#define IER_MODEM		(0x08)  /* Modem Status */
-#define IER_PTIME		(0x80)  /* Programmable THRE Interrupt Mode Enable */
+#define IER_RECV (0x01) /* Receive Data Available */
+#define IER_TDRQ (0x02) /* Transmit Holding Register Empty */
+#define IER_LINE_STAT (0x04) /* Receiver Line Status */
+#define IER_MODEM (0x08) /* Modem Status */
+#define IER_PTIME (0x80) /* Programmable THRE Interrupt Mode Enable */
 
 /*
  * IIR: Interrupt ID register
  */
-#define UART_OFFSET_IIR		(0x08)
-
-#define IIR_MODEM		(0x00)  /* Prio: 4 */
-#define IIR_NO_INTR		(0x01)
-#define IIR_THRE		(0x02)  /* Prio: 3 */
-#define IIR_RECV_DATA		(0x04)  /* Prio: 2 */
-#define IIR_LINE_STAT		(0x06)  /* Prio: 1 */
-#define IIR_BUSY		(0x07)  /* Prio: 5 */
-#define IIR_TIME_OUT		(0x0C)  /* Prio: 2 */
-#define IIR_SOURCE		(0x0F)
+#define UART_OFFSET_IIR (0x08)
 
+#define IIR_MODEM (0x00) /* Prio: 4 */
+#define IIR_NO_INTR (0x01)
+#define IIR_THRE (0x02) /* Prio: 3 */
+#define IIR_RECV_DATA (0x04) /* Prio: 2 */
+#define IIR_LINE_STAT (0x06) /* Prio: 1 */
+#define IIR_BUSY (0x07) /* Prio: 5 */
+#define IIR_TIME_OUT (0x0C) /* Prio: 2 */
+#define IIR_SOURCE (0x0F)
 
 /*
  * FCR: FIFO Control register (FIFO_MODE != NONE)
  */
-#define UART_OFFSET_FCR		(0x08)
+#define UART_OFFSET_FCR (0x08)
 
-#define FIFO_SIZE		64
-#define FCR_FIFO_ENABLE		(0x01)
-#define FCR_RESET_RX		(0x02)
-#define FCR_RESET_TX		(0x04)
-#define FCR_DMA_MODE		(0x08)
+#define FIFO_SIZE 64
+#define FCR_FIFO_ENABLE (0x01)
+#define FCR_RESET_RX (0x02)
+#define FCR_RESET_TX (0x04)
+#define FCR_DMA_MODE (0x08)
 
 /*
  * LCR: Line Control register
  */
-#define UART_OFFSET_LCR		(0x0c)
+#define UART_OFFSET_LCR (0x0c)
 
-#define LCR_5BIT_CHR		(0x00)
-#define LCR_6BIT_CHR		(0x01)
-#define LCR_7BIT_CHR		(0x02)
-#define LCR_8BIT_CHR		(0x03)
-#define LCR_BIT_CHR_MASK	(0x03)
+#define LCR_5BIT_CHR (0x00)
+#define LCR_6BIT_CHR (0x01)
+#define LCR_7BIT_CHR (0x02)
+#define LCR_8BIT_CHR (0x03)
+#define LCR_BIT_CHR_MASK (0x03)
 
-#define LCR_STOP		BIT(2)  /* 0: 1 stop bit, 1: 1.5/2 */
-#define LCR_PEN			BIT(3)  /* Parity Enable */
-#define LCR_EPS			BIT(4)  /* Even Parity Select */
-#define LCR_SP			BIT(5)  /* Stick Parity */
-#define LCR_BC			BIT(6)  /* Break Control */
-#define LCR_DLAB		BIT(7)  /* Divisor Latch Access */
+#define LCR_STOP BIT(2) /* 0: 1 stop bit, 1: 1.5/2 */
+#define LCR_PEN BIT(3) /* Parity Enable */
+#define LCR_EPS BIT(4) /* Even Parity Select */
+#define LCR_SP BIT(5) /* Stick Parity */
+#define LCR_BC BIT(6) /* Break Control */
+#define LCR_DLAB BIT(7) /* Divisor Latch Access */
 
 /*
  * MCR: Modem Control register
  */
-#define UART_OFFSET_MCR		(0x10)
-#define MCR_DTR			(0x1)     /* Data terminal ready */
-#define MCR_RTS			(0x2)     /* Request to send */
-#define MCR_LOOP		(0x10)    /* LoopBack bit*/
+#define UART_OFFSET_MCR (0x10)
+#define MCR_DTR (0x1) /* Data terminal ready */
+#define MCR_RTS (0x2) /* Request to send */
+#define MCR_LOOP (0x10) /* LoopBack bit*/
 
-#define MCR_INTR_ENABLE		(0x08)    /* User-designated OUT2 */
-#define MCR_AUTO_FLOW_EN	(0x20)
+#define MCR_INTR_ENABLE (0x08) /* User-designated OUT2 */
+#define MCR_AUTO_FLOW_EN (0x20)
 
 /*
  * LSR: Line Status register
  */
-#define UART_OFFSET_LSR		(0x14)
+#define UART_OFFSET_LSR (0x14)
 
-#define LSR_DR			(0x01)         /* Data Ready */
-#define LSR_OE			(0x02)         /* Overrun error */
-#define LSR_PE			(0x04)         /* Parity error */
-#define LSR_FE			(0x08)         /* Framing error */
-#define LSR_BI			(0x10)         /* Breaking interrupt */
-#define LSR_TDRQ		(0x20)       /* Transmit Holding Register Empty */
-#define LSR_TEMT		(0x40)       /* Transmitter empty */
+#define LSR_DR (0x01) /* Data Ready */
+#define LSR_OE (0x02) /* Overrun error */
+#define LSR_PE (0x04) /* Parity error */
+#define LSR_FE (0x08) /* Framing error */
+#define LSR_BI (0x10) /* Breaking interrupt */
+#define LSR_TDRQ (0x20) /* Transmit Holding Register Empty */
+#define LSR_TEMT (0x40) /* Transmitter empty */
 
 /*
  * MSR: Modem Status register
  */
-#define UART_OFFSET_MSR		(0x18)
+#define UART_OFFSET_MSR (0x18)
 
-#define MSR_CTS			BIT(4) /* Clear To Send signal */
+#define MSR_CTS BIT(4) /* Clear To Send signal */
 
 /*
  * TFL: Transmit FIFO Level
  */
-#define UART_OFFSET_TFL		(0x80)
+#define UART_OFFSET_TFL (0x80)
 
 /*
  * RFL: Receive FIFO Level
  */
-#define UART_OFFSET_RFL		(0x84)
+#define UART_OFFSET_RFL (0x84)
 #else
 /* RBR: Receive Buffer register     (BLAB bit = 0)  */
-#define UART_OFFSET_RBR	(0)
+#define UART_OFFSET_RBR (0)
 /* THR: Transmit Holding register   (BLAB bit = 0)  */
-#define UART_OFFSET_THR	(0)
+#define UART_OFFSET_THR (0)
 /* IER: Interrupt Enable register   (BLAB bit = 0)  */
-#define UART_OFFSET_IER	(1)
+#define UART_OFFSET_IER (1)
 
 /* FCR: FIFO Control register */
-#define UART_OFFSET_FCR	(2)
-#define FCR_FIFO_ENABLE	BIT(0)
-#define FCR_RESET_RX		BIT(1)
-#define FCR_RESET_TX		BIT(2)
+#define UART_OFFSET_FCR (2)
+#define FCR_FIFO_ENABLE BIT(0)
+#define FCR_RESET_RX BIT(1)
+#define FCR_RESET_TX BIT(2)
 
 /* LCR: Line Control register */
-#define UART_OFFSET_LCR	(3)
-#define LCR_DLAB		(0x80)
-#define LCR_5BIT_CHR		(0x00)
-#define LCR_6BIT_CHR		(0x01)
-#define LCR_7BIT_CHR		(0x02)
-#define LCR_8BIT_CHR		(0x03)
-#define LCR_BIT_CHR_MASK	(0x03)
-#define LCR_SB			(0x40)	/* Set Break */
+#define UART_OFFSET_LCR (3)
+#define LCR_DLAB (0x80)
+#define LCR_5BIT_CHR (0x00)
+#define LCR_6BIT_CHR (0x01)
+#define LCR_7BIT_CHR (0x02)
+#define LCR_8BIT_CHR (0x03)
+#define LCR_BIT_CHR_MASK (0x03)
+#define LCR_SB (0x40) /* Set Break */
 
 /* MCR: Modem Control register */
-#define UART_OFFSET_MCR	(4)
-#define MCR_DTR		BIT(0)
-#define MCR_RTS		BIT(1)
-#define MCR_LOO		BIT(4)
-#define MCR_INTR_ENABLE	BIT(3)
-#define MCR_AUTO_FLOW_EN	BIT(5)
+#define UART_OFFSET_MCR (4)
+#define MCR_DTR BIT(0)
+#define MCR_RTS BIT(1)
+#define MCR_LOO BIT(4)
+#define MCR_INTR_ENABLE BIT(3)
+#define MCR_AUTO_FLOW_EN BIT(5)
 
 /* LSR: Line Status register */
-#define UART_OFFSET_LSR	(5)
-#define LSR_DR			BIT(0)	/* Data Ready */
-#define LSR_OE			BIT(1)	/* Overrun error */
-#define LSR_PE			BIT(2)	/* Parity error */
-#define LSR_FE			BIT(3)	/* Framing error */
-#define LSR_BI			BIT(4)	/* Breaking interrupt */
-#define LSR_THR_EMPTY		BIT(5)	/* Non FIFO mode: Transmit holding
-					 * register empty
-					 */
-#define LSR_TDRQ		BIT(5)	/* FIFO mode: Transmit Data request */
-#define LSR_TEMT		BIT(6)	/* Transmitter empty */
+#define UART_OFFSET_LSR (5)
+#define LSR_DR BIT(0) /* Data Ready */
+#define LSR_OE BIT(1) /* Overrun error */
+#define LSR_PE BIT(2) /* Parity error */
+#define LSR_FE BIT(3) /* Framing error */
+#define LSR_BI BIT(4) /* Breaking interrupt */
+#define LSR_THR_EMPTY                             \
+	BIT(5) /* Non FIFO mode: Transmit holding \
+		* register empty                  \
+		*/
+#define LSR_TDRQ BIT(5) /* FIFO mode: Transmit Data request */
+#define LSR_TEMT BIT(6) /* Transmitter empty */
 
 #define FCR_ITL_FIFO_64_BYTES_56 (BIT(6) | BIT(7))
 
-#define IER_RECV		BIT(0)
-#define IER_TDRQ		BIT(1)
-#define IER_LINE_STAT		BIT(2)
+#define IER_RECV BIT(0)
+#define IER_TDRQ BIT(1)
+#define IER_LINE_STAT BIT(2)
 
-#define UART_OFFSET_IIR	(2)
+#define UART_OFFSET_IIR (2)
 /* MSR: Modem Status register */
-#define UART_OFFSET_MSR	(6)
+#define UART_OFFSET_MSR (6)
 
 /* DLL: Divisor Latch Reg. low byte  (BLAB bit = 1) */
-#define UART_OFFSET_DLL	(0)
+#define UART_OFFSET_DLL (0)
 
 /* DLH: Divisor Latch Reg. high byte (BLAB bit = 1) */
-#define UART_OFFSET_DLH	(1)
+#define UART_OFFSET_DLH (1)
 #endif
 
 /*
  * DLF: Divisor Latch Fraction Register
  */
-#define UART_OFFSET_DLF		(0xC0)
+#define UART_OFFSET_DLF (0xC0)
 
 /* FOR: Fifo O Register (ISH only) */
-#define UART_OFFSET_FOR	(0x20)
-#define FOR_OCCUPANCY_OFFS	0
-#define FOR_OCCUPANCY_MASK	0x7F
+#define UART_OFFSET_FOR (0x20)
+#define FOR_OCCUPANCY_OFFS 0
+#define FOR_OCCUPANCY_MASK 0x7F
 
 /* ABR: Auto-Baud Control Register (ISH only) */
-#define UART_OFFSET_ABR	(0x24)
-#define ABR_UUE		BIT(4)
+#define UART_OFFSET_ABR (0x24)
+#define ABR_UUE BIT(4)
 
 /* Pre-Scalar Register (ISH only) */
-#define UART_OFFSET_PS		(0x30)
+#define UART_OFFSET_PS (0x30)
 
 /* DDS registers (ISH only) */
-#define UART_OFFSET_MUL	(0x34)
-#define UART_OFFSET_DIV	(0x38)
+#define UART_OFFSET_MUL (0x34)
+#define UART_OFFSET_DIV (0x38)
 
-#define FCR_FIFO_SIZE_16	(0x00)
-#define FCR_FIFO_SIZE_64	(0x20)
-#define FCR_ITL_FIFO_64_BYTES_1	(0x00)
+#define FCR_FIFO_SIZE_16 (0x00)
+#define FCR_FIFO_SIZE_64 (0x20)
+#define FCR_ITL_FIFO_64_BYTES_1 (0x00)
 
 /* tx empty trigger(TET) */
-#define FCR_TET_EMPTY		(0x00)
-#define FCR_TET_2CHAR		(0x10)
-#define FCR_TET_QTR_FULL	(0x20)
-#define FCR_TET_HALF_FULL	(0x30)
+#define FCR_TET_EMPTY (0x00)
+#define FCR_TET_2CHAR (0x10)
+#define FCR_TET_QTR_FULL (0x20)
+#define FCR_TET_HALF_FULL (0x30)
 
 /* receive trigger(RT) */
-#define FCR_RT_1CHAR		(0x00)
-#define FCR_RT_QTR_FULL		(0x40)
-#define FCR_RT_HALF_FULL	(0x80)
-#define FCR_RT_2LESS_FULL	(0xc0)
+#define FCR_RT_1CHAR (0x00)
+#define FCR_RT_QTR_FULL (0x40)
+#define FCR_RT_HALF_FULL (0x80)
+#define FCR_RT_2LESS_FULL (0xc0)
 
 /* G_IEN: Global Interrupt Enable  (ISH only) */
-#define HSU_REG_GIEN		REG32(HSU_BASE + 0x0)
-#define HSU_REG_GIST		REG32(HSU_BASE + 0x4)
-
-#define GIEN_PWR_MGMT		BIT(24)
-#define GIEN_DMA_EN		BIT(5)
-#define GIEN_UART2_EN		BIT(2)
-#define GIEN_UART1_EN		BIT(1)
-#define GIEN_UART0_EN		BIT(0)
-#define GIST_DMA_EN		BIT(5)
-#define GIST_UART2_EN		BIT(2)
-#define GIST_UART1_EN		BIT(1)
-#define GIST_UART0_EN		BIT(0)
-#define GIST_UARTx_EN		(GIST_UART0_EN|GIST_UART1_EN|GIST_UART2_EN)
+#define HSU_REG_GIEN REG32(HSU_BASE + 0x0)
+#define HSU_REG_GIST REG32(HSU_BASE + 0x4)
+
+#define GIEN_PWR_MGMT BIT(24)
+#define GIEN_DMA_EN BIT(5)
+#define GIEN_UART2_EN BIT(2)
+#define GIEN_UART1_EN BIT(1)
+#define GIEN_UART0_EN BIT(0)
+#define GIST_DMA_EN BIT(5)
+#define GIST_UART2_EN BIT(2)
+#define GIST_UART1_EN BIT(1)
+#define GIST_UART0_EN BIT(0)
+#define GIST_UARTx_EN (GIST_UART0_EN | GIST_UART1_EN | GIST_UART2_EN)
 
 /* UART config flag, send to sc_io_control if the current UART line has HW
  * flow control lines connected.
  */
-#define UART_CONFIG_HW_FLOW_CONTROL		BIT(0)
+#define UART_CONFIG_HW_FLOW_CONTROL BIT(0)
 
 /* UART config flag for sc_io_control.  If defined a sc_io_event_rx_msg is
  * raised only when the rx buffer is completely full. Otherwise, the event
  * is raised after a timeout is received on the UART line,
  * and all data received until now is provided.
  */
-#define UART_CONFIG_DELIVER_FULL_RX_BUF	BIT(1)
+#define UART_CONFIG_DELIVER_FULL_RX_BUF BIT(1)
 
 /* UART config flag for sc_io_control.  If defined a sc_io_event_rx_buf_depleted
  * is raised when all rx buffers that were added are full. Otherwise, no
  * event is raised.
  */
-#define UART_CONFIG_ANNOUNCE_DEPLETED_BUF	BIT(2)
-
-#define UART_INT_DEVICES		3
-#define UART_EXT_DEVICES		8
-#define UART_DEVICES			UART_INT_DEVICES
-#define UART_ISH_ADDR_INTERVAL		1
-
-#define B9600				0x0000d
-#define B57600				0x00000018
-#define B115200			0x00000011
-#define B921600			0x00000012
-#define B2000000			0x00000013
-#define B3000000			0x00000014
-#define B3250000			0x00000015
-#define B3500000			0x00000016
-#define B4000000			0x00000017
-#define B19200				0x0000e
-#define B38400				0x0000f
+#define UART_CONFIG_ANNOUNCE_DEPLETED_BUF BIT(2)
+
+#define UART_INT_DEVICES 3
+#define UART_EXT_DEVICES 8
+#define UART_DEVICES UART_INT_DEVICES
+#define UART_ISH_ADDR_INTERVAL 1
+
+#define B9600 0x0000d
+#define B57600 0x00000018
+#define B115200 0x00000011
+#define B921600 0x00000012
+#define B2000000 0x00000013
+#define B3000000 0x00000014
+#define B3250000 0x00000015
+#define B3500000 0x00000016
+#define B4000000 0x00000017
+#define B19200 0x0000e
+#define B38400 0x0000f
 
 /* KHZ, MHZ */
-#define KHZ(x)				((x) * 1000)
-#define MHZ(x)				(KHZ(x) * 1000)
+#define KHZ(x) ((x)*1000)
+#define MHZ(x) (KHZ(x) * 1000)
 #if defined(CHIP_VARIANT_ISH5P4)
 /* Change to 100MHZ in real silicon platform */
-#define UART_ISH_INPUT_FREQ		MHZ(100)
+#define UART_ISH_INPUT_FREQ MHZ(100)
 #elif defined(CHIP_FAMILY_ISH3) || defined(CHIP_FAMILY_ISH5)
-#define UART_ISH_INPUT_FREQ		MHZ(120)
+#define UART_ISH_INPUT_FREQ MHZ(120)
 #elif defined(CHIP_FAMILY_ISH4)
-#define UART_ISH_INPUT_FREQ		MHZ(100)
+#define UART_ISH_INPUT_FREQ MHZ(100)
 #endif
-#define UART_DEFAULT_BAUD_RATE		115200
-#define UART_STATE_CG			BIT(UART_OP_CG)
+#define UART_DEFAULT_BAUD_RATE 115200
+#define UART_STATE_CG BIT(UART_OP_CG)
 
-enum UART_PORT {
-	UART_PORT_0,
-	UART_PORT_1,
-	UART_PORT_MAX
-};
+enum UART_PORT { UART_PORT_0, UART_PORT_1, UART_PORT_MAX };
 
-enum UART_OP {
-	UART_OP_READ,
-	UART_OP_WRITE,
-	UART_OP_CG,
-	UART_OP_MAX
-};
+enum UART_OP { UART_OP_READ, UART_OP_WRITE, UART_OP_CG, UART_OP_MAX };
 
-enum {
-	BAUD_IDX,
-	BAUD_SPEED,
-	BAUD_TABLE_MAX
-};
+enum { BAUD_IDX, BAUD_SPEED, BAUD_TABLE_MAX };
 
 struct uart_ctx {
 	uint32_t id;
 	uint32_t base;
 	uint32_t addr_interval;
-	uint32_t uart_state;
+	atomic_t uart_state;
 	uint32_t is_open;
 	uint32_t baud_rate;
 	uint32_t input_freq;
diff --git a/chip/ish/util/pack_ec.py b/chip/ish/util/pack_ec.py
index f1ce28539e..13a2afafd9 100755
--- a/chip/ish/util/pack_ec.py
+++ b/chip/ish/util/pack_ec.py
@@ -1,7 +1,7 @@
 #!/usr/bin/env python3
 # -*- coding: utf-8 -*-"
 
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -20,89 +20,109 @@
 import argparse
 import struct
 
+
 MANIFEST_ENTRY_SIZE = 0x80
 HEADER_SIZE = 0x1000
 PAGE_SIZE = 0x1000
 
+
 def parseargs():
-  parser = argparse.ArgumentParser()
-  parser.add_argument("-k", "--kernel",
-                      help="EC kernel binary to pack, \
-                      usually ec.RW.bin or ec.RW.flat.",
-                      required=True)
-  parser.add_argument("--kernel-size", type=int,
-                      help="Size of EC kernel image",
-                      required=True)
-  parser.add_argument("-a", "--aon",
-                      help="EC aontask binary to pack, \
-                      usually ish_aontask.bin.",
-                      required=False)
-  parser.add_argument("--aon-size", type=int,
-                      help="Size of EC aontask image",
-                      required=False)
-  parser.add_argument("-o", "--output",
-                      help="Output flash binary file")
-
-  return parser.parse_args()
+    parser = argparse.ArgumentParser()
+    parser.add_argument(
+        "-k",
+        "--kernel",
+        help="EC kernel binary to pack, usually ec.RW.bin or ec.RW.flat.",
+        required=True,
+    )
+    parser.add_argument(
+        "--kernel-size", type=int, help="Size of EC kernel image", required=True
+    )
+    parser.add_argument(
+        "-a",
+        "--aon",
+        help="EC aontask binary to pack, usually ish_aontask.bin.",
+        required=False,
+    )
+    parser.add_argument(
+        "--aon-size", type=int, help="Size of EC aontask image", required=False
+    )
+    parser.add_argument("-o", "--output", help="Output flash binary file")
+
+    return parser.parse_args()
+
 
 def gen_manifest(ext_id, comp_app_name, code_offset, module_size):
-  """Returns a binary blob that represents a manifest entry"""
-  m = bytearray(MANIFEST_ENTRY_SIZE)
+    """Returns a binary blob that represents a manifest entry"""
+    m = bytearray(MANIFEST_ENTRY_SIZE)
 
-  # 4 bytes of ASCII encode ID (little endian)
-  struct.pack_into('<4s', m, 0, ext_id)
-  # 8 bytes of ASCII encode ID (little endian)
-  struct.pack_into('<8s', m, 32, comp_app_name)
-  # 4 bytes of code offset (little endian)
-  struct.pack_into('<I', m, 96, code_offset)
-  # 2 bytes of module in page size increments (little endian)
-  struct.pack_into('<H', m, 100, module_size)
+    # 4 bytes of ASCII encode ID (little endian)
+    struct.pack_into("<4s", m, 0, ext_id)
+    # 8 bytes of ASCII encode ID (little endian)
+    struct.pack_into("<8s", m, 32, comp_app_name)
+    # 4 bytes of code offset (little endian)
+    struct.pack_into("<I", m, 96, code_offset)
+    # 2 bytes of module in page size increments (little endian)
+    struct.pack_into("<H", m, 100, module_size)
+
+    return m
 
-  return m
 
 def roundup_page(size):
-  """Returns roundup-ed page size from size of bytes"""
-  return int(size / PAGE_SIZE) + (size % PAGE_SIZE > 0)
+    """Returns roundup-ed page size from size of bytes"""
+    return int(size / PAGE_SIZE) + (size % PAGE_SIZE > 0)
+
 
 def main():
-  args = parseargs()
-  print("    Packing EC image file for ISH")
-
-  with open(args.output, 'wb') as f:
-    print("      kernel binary size:", args.kernel_size)
-    kern_rdup_pg_size = roundup_page(args.kernel_size)
-    # Add manifest for main ISH binary
-    f.write(gen_manifest(b'ISHM', b'ISH_KERN', HEADER_SIZE, kern_rdup_pg_size))
-
-    if args.aon is not None:
-      print("      AON binary size:   ", args.aon_size)
-      aon_rdup_pg_size = roundup_page(args.aon_size)
-      # Add manifest for aontask binary
-      f.write(gen_manifest(b'ISHM', b'AON_TASK',
-                           (HEADER_SIZE + kern_rdup_pg_size * PAGE_SIZE -
-                            MANIFEST_ENTRY_SIZE), aon_rdup_pg_size))
-
-    # Add manifest that signals end of manifests
-    f.write(gen_manifest(b'ISHE', b'', 0, 0))
-
-    # Pad the remaining HEADER with 0s
-    if args.aon is not None:
-      f.write(b'\x00' * (HEADER_SIZE - (MANIFEST_ENTRY_SIZE * 3)))
-    else:
-      f.write(b'\x00' * (HEADER_SIZE - (MANIFEST_ENTRY_SIZE * 2)))
-
-    # Append original kernel image
-    with open(args.kernel, 'rb') as in_file:
-      f.write(in_file.read())
-    # Filling padings due to size round up as pages
-    f.write(b'\x00' * (kern_rdup_pg_size * PAGE_SIZE - args.kernel_size))
-
-    if args.aon is not None:
-      # Append original aon image
-      with open(args.aon, 'rb') as in_file:
-        f.write(in_file.read())
-      # Filling padings due to size round up as pages
-      f.write(b'\x00' * (aon_rdup_pg_size * PAGE_SIZE - args.aon_size))
-
-if __name__ == '__main__':
-  main()
+    args = parseargs()
+    print("    Packing EC image file for ISH")
+
+    with open(args.output, "wb") as f:
+        print("      kernel binary size:", args.kernel_size)
+        kern_rdup_pg_size = roundup_page(args.kernel_size)
+        # Add manifest for main ISH binary
+        f.write(
+            gen_manifest(b"ISHM", b"ISH_KERN", HEADER_SIZE, kern_rdup_pg_size)
+        )
+
+        if args.aon is not None:
+            print("      AON binary size:   ", args.aon_size)
+            aon_rdup_pg_size = roundup_page(args.aon_size)
+            # Add manifest for aontask binary
+            f.write(
+                gen_manifest(
+                    b"ISHM",
+                    b"AON_TASK",
+                    (
+                        HEADER_SIZE
+                        + kern_rdup_pg_size * PAGE_SIZE
+                        - MANIFEST_ENTRY_SIZE
+                    ),
+                    aon_rdup_pg_size,
+                )
+            )
+
+        # Add manifest that signals end of manifests
+        f.write(gen_manifest(b"ISHE", b"", 0, 0))
+
+        # Pad the remaining HEADER with 0s
+        if args.aon is not None:
+            f.write(b"\x00" * (HEADER_SIZE - (MANIFEST_ENTRY_SIZE * 3)))
+        else:
+            f.write(b"\x00" * (HEADER_SIZE - (MANIFEST_ENTRY_SIZE * 2)))
+
+        # Append original kernel image
+        with open(args.kernel, "rb") as in_file:
+            f.write(in_file.read())
+        # Filling padings due to size round up as pages
+        f.write(b"\x00" * (kern_rdup_pg_size * PAGE_SIZE - args.kernel_size))
+
+        if args.aon is not None:
+            # Append original aon image
+            with open(args.aon, "rb") as in_file:
+                f.write(in_file.read())
+            # Filling padings due to size round up as pages
+            f.write(b"\x00" * (aon_rdup_pg_size * PAGE_SIZE - args.aon_size))
+
+
+if __name__ == "__main__":
+    main()
diff --git a/chip/ish/watchdog.c b/chip/ish/watchdog.c
index bf78f49312..8f0ea5ddf1 100644
--- a/chip/ish/watchdog.c
+++ b/chip/ish/watchdog.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -23,14 +23,14 @@
 #include "ec_commands.h"
 #include "hooks.h"
 #include "ish_persistent_data.h"
-#include "task.h"
 #include "registers.h"
 #include "system.h"
+#include "task.h"
 #include "watchdog.h"
 
 /* Units are hundreds of milliseconds */
-#define WDT_T1_PERIOD		(100) /* 10 seconds */
-#define WDT_T2_PERIOD		(10)  /* 1 second */
+#define WDT_T1_PERIOD (100) /* 10 seconds */
+#define WDT_T2_PERIOD (10) /* 1 second */
 
 int watchdog_init(void)
 {
@@ -45,9 +45,8 @@ int watchdog_init(void)
 	CCU_WDT_CD = WDT_CLOCK_HZ / 10; /* 10 Hz => 100 ms period */
 
 	/* Enable the watchdog timer and set initial T1/T2 values */
-	WDT_CONTROL = WDT_CONTROL_ENABLE_BIT
-		| (WDT_T2_PERIOD << 8)
-		| WDT_T1_PERIOD;
+	WDT_CONTROL = WDT_CONTROL_ENABLE_BIT | (WDT_T2_PERIOD << 8) |
+		      WDT_T1_PERIOD;
 
 	task_enable_irq(ISH_WDT_IRQ);
 
diff --git a/chip/it83xx/adc.c b/chip/it83xx/adc.c
index f8a113beab..7b08a8beb1 100644
--- a/chip/it83xx/adc.c
+++ b/chip/it83xx/adc.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,10 +6,9 @@
 /* IT83xx ADC module for Chrome EC */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "clock.h"
-#include "console.h"
 #include "common.h"
+#include "console.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "registers.h"
@@ -18,7 +17,7 @@
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 /* Global variables */
 static struct mutex adc_lock;
@@ -27,42 +26,42 @@ static volatile task_id_t task_waiting;
 
 /* Data structure of ADC channel control registers. */
 const struct adc_ctrl_t adc_ctrl_regs[] = {
-	{&IT83XX_ADC_VCH0CTL, &IT83XX_ADC_VCH0DATM, &IT83XX_ADC_VCH0DATL},
-	{&IT83XX_ADC_VCH1CTL, &IT83XX_ADC_VCH1DATM, &IT83XX_ADC_VCH1DATL},
-	{&IT83XX_ADC_VCH2CTL, &IT83XX_ADC_VCH2DATM, &IT83XX_ADC_VCH2DATL},
-	{&IT83XX_ADC_VCH3CTL, &IT83XX_ADC_VCH3DATM, &IT83XX_ADC_VCH3DATL},
-	{&IT83XX_ADC_VCH4CTL, &IT83XX_ADC_VCH4DATM, &IT83XX_ADC_VCH4DATL},
-	{&IT83XX_ADC_VCH5CTL, &IT83XX_ADC_VCH5DATM, &IT83XX_ADC_VCH5DATL},
-	{&IT83XX_ADC_VCH6CTL, &IT83XX_ADC_VCH6DATM, &IT83XX_ADC_VCH6DATL},
-	{&IT83XX_ADC_VCH7CTL, &IT83XX_ADC_VCH7DATM, &IT83XX_ADC_VCH7DATL},
-	{&IT83XX_ADC_VCH13CTL, &IT83XX_ADC_VCH13DATM, &IT83XX_ADC_VCH13DATL},
-	{&IT83XX_ADC_VCH14CTL, &IT83XX_ADC_VCH14DATM, &IT83XX_ADC_VCH14DATL},
-	{&IT83XX_ADC_VCH15CTL, &IT83XX_ADC_VCH15DATM, &IT83XX_ADC_VCH15DATL},
-	{&IT83XX_ADC_VCH16CTL, &IT83XX_ADC_VCH16DATM, &IT83XX_ADC_VCH16DATL},
+	{ &IT83XX_ADC_VCH0CTL, &IT83XX_ADC_VCH0DATM, &IT83XX_ADC_VCH0DATL },
+	{ &IT83XX_ADC_VCH1CTL, &IT83XX_ADC_VCH1DATM, &IT83XX_ADC_VCH1DATL },
+	{ &IT83XX_ADC_VCH2CTL, &IT83XX_ADC_VCH2DATM, &IT83XX_ADC_VCH2DATL },
+	{ &IT83XX_ADC_VCH3CTL, &IT83XX_ADC_VCH3DATM, &IT83XX_ADC_VCH3DATL },
+	{ &IT83XX_ADC_VCH4CTL, &IT83XX_ADC_VCH4DATM, &IT83XX_ADC_VCH4DATL },
+	{ &IT83XX_ADC_VCH5CTL, &IT83XX_ADC_VCH5DATM, &IT83XX_ADC_VCH5DATL },
+	{ &IT83XX_ADC_VCH6CTL, &IT83XX_ADC_VCH6DATM, &IT83XX_ADC_VCH6DATL },
+	{ &IT83XX_ADC_VCH7CTL, &IT83XX_ADC_VCH7DATM, &IT83XX_ADC_VCH7DATL },
+	{ &IT83XX_ADC_VCH13CTL, &IT83XX_ADC_VCH13DATM, &IT83XX_ADC_VCH13DATL },
+	{ &IT83XX_ADC_VCH14CTL, &IT83XX_ADC_VCH14DATM, &IT83XX_ADC_VCH14DATL },
+	{ &IT83XX_ADC_VCH15CTL, &IT83XX_ADC_VCH15DATM, &IT83XX_ADC_VCH15DATL },
+	{ &IT83XX_ADC_VCH16CTL, &IT83XX_ADC_VCH16DATM, &IT83XX_ADC_VCH16DATL },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_ctrl_regs) == CHIP_ADC_COUNT);
 
 #ifdef CONFIG_ADC_VOLTAGE_COMPARATOR
-#define VCMP_ADC_CH_MASK_H           BIT(3)
-#define VCMP_ADC_CH_MASK_L           0x7
+#define VCMP_ADC_CH_MASK_H BIT(3)
+#define VCMP_ADC_CH_MASK_L 0x7
 /* 10-bits resolution */
-#define VCMP_RESOLUTION              BIT(10)
-#define VCMP_MAX_MVOLT               3000
+#define VCMP_RESOLUTION BIT(10)
+#define VCMP_MAX_MVOLT 3000
 
 /* Data structure of voltage comparator control registers. */
 const struct vcmp_ctrl_t vcmp_ctrl_regs[] = {
-	{&IT83XX_ADC_VCMP0CTL, &IT83XX_ADC_VCMP0CSELM, &IT83XX_ADC_CMP0THRDATM,
-		&IT83XX_ADC_CMP0THRDATL},
-	{&IT83XX_ADC_VCMP1CTL, &IT83XX_ADC_VCMP1CSELM, &IT83XX_ADC_CMP1THRDATM,
-		&IT83XX_ADC_CMP1THRDATL},
-	{&IT83XX_ADC_VCMP2CTL, &IT83XX_ADC_VCMP2CSELM, &IT83XX_ADC_CMP2THRDATM,
-		&IT83XX_ADC_CMP2THRDATL},
-	{&IT83XX_ADC_VCMP3CTL, &IT83XX_ADC_VCMP3CSELM, &IT83XX_ADC_CMP3THRDATM,
-		&IT83XX_ADC_CMP3THRDATL},
-	{&IT83XX_ADC_VCMP4CTL, &IT83XX_ADC_VCMP4CSELM, &IT83XX_ADC_CMP4THRDATM,
-		&IT83XX_ADC_CMP4THRDATL},
-	{&IT83XX_ADC_VCMP5CTL, &IT83XX_ADC_VCMP5CSELM, &IT83XX_ADC_CMP5THRDATM,
-		&IT83XX_ADC_CMP5THRDATL},
+	{ &IT83XX_ADC_VCMP0CTL, &IT83XX_ADC_VCMP0CSELM, &IT83XX_ADC_CMP0THRDATM,
+	  &IT83XX_ADC_CMP0THRDATL },
+	{ &IT83XX_ADC_VCMP1CTL, &IT83XX_ADC_VCMP1CSELM, &IT83XX_ADC_CMP1THRDATM,
+	  &IT83XX_ADC_CMP1THRDATL },
+	{ &IT83XX_ADC_VCMP2CTL, &IT83XX_ADC_VCMP2CSELM, &IT83XX_ADC_CMP2THRDATM,
+	  &IT83XX_ADC_CMP2THRDATL },
+	{ &IT83XX_ADC_VCMP3CTL, &IT83XX_ADC_VCMP3CSELM, &IT83XX_ADC_CMP3THRDATM,
+	  &IT83XX_ADC_CMP3THRDATL },
+	{ &IT83XX_ADC_VCMP4CTL, &IT83XX_ADC_VCMP4CSELM, &IT83XX_ADC_CMP4THRDATM,
+	  &IT83XX_ADC_CMP4THRDATL },
+	{ &IT83XX_ADC_VCMP5CTL, &IT83XX_ADC_VCMP5CSELM, &IT83XX_ADC_CMP5THRDATM,
+	  &IT83XX_ADC_CMP5THRDATL },
 };
 BUILD_ASSERT(ARRAY_SIZE(vcmp_ctrl_regs) == CHIP_VCMP_COUNT);
 #endif
@@ -121,8 +120,8 @@ static void adc_disable_channel(int ch)
 static int adc_data_valid(enum chip_adc_channel adc_ch)
 {
 	return (adc_ch <= CHIP_ADC_CH7) ?
-		(IT83XX_ADC_ADCDVSTS & BIT(adc_ch)) :
-		(IT83XX_ADC_ADCDVSTS2 & (1 << (adc_ch - CHIP_ADC_CH13)));
+		       (IT83XX_ADC_ADCDVSTS & BIT(adc_ch)) :
+		       (IT83XX_ADC_ADCDVSTS2 & (1 << (adc_ch - CHIP_ADC_CH13)));
 }
 
 int adc_read_channel(enum adc_channel ch)
@@ -145,33 +144,39 @@ int adc_read_channel(enum adc_channel ch)
 	/* Wait for interrupt */
 	events = task_wait_event_mask(TASK_EVENT_ADC_DONE, ADC_TIMEOUT_US);
 	task_waiting = TASK_ID_INVALID;
-
-	if (events & TASK_EVENT_ADC_DONE) {
-		/* data valid of adc channel[x] */
-		if (adc_data_valid(adc_ch)) {
-			/* read adc raw data msb and lsb */
-			adc_raw_data = (*adc_ctrl_regs[adc_ch].adc_datm << 8) +
-				*adc_ctrl_regs[adc_ch].adc_datl;
-
-			/* W/C data valid flag */
-			if (adc_ch <= CHIP_ADC_CH7)
-				IT83XX_ADC_ADCDVSTS = BIT(adc_ch);
-			else
-				IT83XX_ADC_ADCDVSTS2 =
-					(1 << (adc_ch - CHIP_ADC_CH13));
-
-			mv = adc_raw_data * adc_channels[ch].factor_mul /
-				adc_channels[ch].factor_div +
-				adc_channels[ch].shift;
-			valid = 1;
-		}
+	/*
+	 * Ensure EC won't post the adc done event which is set after getting
+	 * events (events |= __wait_evt() in task_wait_event_mask()) to next
+	 * adc read.
+	 * NOTE: clear TASK_EVENT_ADC_DONE event must happen after setting
+	 * task_waiting to invalid. So TASK_EVENT_ADC_DONE would not set until
+	 * next read.
+	 */
+	atomic_clear_bits(task_get_event_bitmap(task_get_current()),
+			  TASK_EVENT_ADC_DONE);
+
+	/* data valid of adc channel[x] */
+	if (adc_data_valid(adc_ch)) {
+		/* read adc raw data msb and lsb */
+		adc_raw_data = (*adc_ctrl_regs[adc_ch].adc_datm << 8) +
+			       *adc_ctrl_regs[adc_ch].adc_datl;
+
+		/* W/C data valid flag */
+		if (adc_ch <= CHIP_ADC_CH7)
+			IT83XX_ADC_ADCDVSTS = BIT(adc_ch);
+		else
+			IT83XX_ADC_ADCDVSTS2 = (1 << (adc_ch - CHIP_ADC_CH13));
+
+		mv = (uint64_t)adc_raw_data * adc_channels[ch].factor_mul /
+			     adc_channels[ch].factor_div +
+		     adc_channels[ch].shift;
+		valid = 1;
 	}
 
 	if (!valid) {
 		CPRINTS("ADC failed to read!!! (regs=%x, %x, ch=%d, evt=%x)",
-			IT83XX_ADC_ADCDVSTS,
-			IT83XX_ADC_ADCDVSTS2,
-			adc_ch, events);
+			IT83XX_ADC_ADCDVSTS, IT83XX_ADC_ADCDVSTS2, adc_ch,
+			events);
 	}
 
 	adc_disable_channel(adc_ch);
@@ -202,7 +207,7 @@ void adc_interrupt(void)
 	task_disable_irq(IT83XX_IRQ_ADC);
 	/* Wake up the task which was waiting for the interrupt */
 	if (task_waiting != TASK_ID_INVALID)
-		task_set_event(task_waiting, TASK_EVENT_ADC_DONE, 0);
+		task_set_event(task_waiting, TASK_EVENT_ADC_DONE);
 }
 
 #ifdef CONFIG_ADC_VOLTAGE_COMPARATOR
@@ -287,8 +292,8 @@ static void voltage_comparator_init(void)
 		 */
 
 		/* Select which ADC channel output voltage into comparator */
-		*vcmp_ctrl_regs[idx].vcmp_ctrl |=
-			vcmp_list[idx].adc_ch & VCMP_ADC_CH_MASK_L;
+		*vcmp_ctrl_regs[idx].vcmp_ctrl |= vcmp_list[idx].adc_ch &
+						  VCMP_ADC_CH_MASK_L;
 		if (vcmp_list[idx].adc_ch & VCMP_ADC_CH_MASK_H)
 			*vcmp_ctrl_regs[idx].vcmp_adc_chm |= ADC_VCMP_VCMPCSELM;
 
@@ -350,6 +355,11 @@ static void adc_init(void)
 	IT83XX_ADC_ADCSTS &= ~BIT(7);
 	IT83XX_ADC_ADCCFG &= ~BIT(5);
 	IT83XX_ADC_ADCCTL = 1;
+	/*
+	 * Enable this bit, and data of VCHxDATL/VCHxDATM will be
+	 * kept until data valid is cleared.
+	 */
+	IT83XX_ADC_ADCGCR |= IT83XX_ADC_DBKEN;
 
 	task_waiting = TASK_ID_INVALID;
 	/* disable adc interrupt */
diff --git a/chip/it83xx/adc_chip.h b/chip/it83xx/adc_chip.h
index 23cc68fb34..3804a684e5 100644
--- a/chip/it83xx/adc_chip.h
+++ b/chip/it83xx/adc_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,6 +10,8 @@
 
 #include "common.h"
 
+#include <stdint.h>
+
 /*
  * Maximum time we allow for an ADC conversion.
  * NOTE:
@@ -59,13 +61,13 @@ enum vcmp_scan_period {
 	VCMP_SCAN_PERIOD_400US = 0x30,
 	VCMP_SCAN_PERIOD_600US = 0x40,
 	VCMP_SCAN_PERIOD_800US = 0x50,
-	VCMP_SCAN_PERIOD_1MS   = 0x60,
+	VCMP_SCAN_PERIOD_1MS = 0x60,
 	VCMP_SCAN_PERIOD_1_5MS = 0x70,
-	VCMP_SCAN_PERIOD_2MS   = 0x80,
+	VCMP_SCAN_PERIOD_2MS = 0x80,
 	VCMP_SCAN_PERIOD_2_5MS = 0x90,
-	VCMP_SCAN_PERIOD_3MS   = 0xA0,
-	VCMP_SCAN_PERIOD_4MS   = 0xB0,
-	VCMP_SCAN_PERIOD_5MS   = 0xC0,
+	VCMP_SCAN_PERIOD_3MS = 0xA0,
+	VCMP_SCAN_PERIOD_4MS = 0xB0,
+	VCMP_SCAN_PERIOD_5MS = 0xC0,
 };
 
 /* Data structure to define ADC channel control registers. */
@@ -93,8 +95,8 @@ struct vcmp_ctrl_t {
 };
 
 /* supported flags (member "flag" in struct vcmp_t) for voltage comparator */
-#define GREATER_THRESHOLD         BIT(0)
-#define LESS_EQUAL_THRESHOLD      BIT(1)
+#define GREATER_THRESHOLD BIT(0)
+#define LESS_EQUAL_THRESHOLD BIT(1)
 
 /* Data structure for board to define voltage comparator list. */
 struct vcmp_t {
@@ -121,12 +123,6 @@ struct vcmp_t {
 	enum chip_adc_channel adc_ch;
 };
 
-/*
- * Boards must provide this list of ADC channel definitions. This must match
- * the enum adc_channel list provided by the board.
- */
-extern const struct adc_t adc_channels[];
-
 #ifdef CONFIG_ADC_VOLTAGE_COMPARATOR
 /*
  * Boards must provide this list of voltage comparator definitions.
diff --git a/chip/it83xx/build.mk b/chip/it83xx/build.mk
index eb4473f4a9..c23bc33a6e 100644
--- a/chip/it83xx/build.mk
+++ b/chip/it83xx/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
+# Copyright 2013 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -29,12 +29,13 @@ chip-$(CONFIG_PWM)+=pwm.o
 chip-$(CONFIG_ADC)+=adc.o
 chip-$(CONFIG_DAC)+=dac.o
 chip-$(CONFIG_HOSTCMD_X86)+=lpc.o ec2i.o
-chip-$(CONFIG_HOSTCMD_ESPI)+=espi.o
-chip-$(CONFIG_SPI_MASTER)+=spi_master.o
+chip-$(CONFIG_HOST_INTERFACE_ESPI)+=espi.o
+chip-$(CONFIG_SPI_CONTROLLER)+=spi_controller.o
 chip-$(CONFIG_SPI)+=spi.o
 chip-$(CONFIG_PECI)+=peci.o
-ifndef CONFIG_KEYBOARD_NOT_RAW
+chip-$(CONFIG_CEC_BITBANG)+=cec_bitbang.o
+ifndef CONFIG_KEYBOARD_DISCRETE
 chip-$(HAS_TASK_KEYSCAN)+=keyboard_raw.o
 endif
-chip-$(CONFIG_I2C_MASTER)+=i2c.o
-chip-$(CONFIG_I2C_SLAVE)+=i2c_slave.o
+chip-$(CONFIG_I2C_CONTROLLER)+=i2c.o
+chip-$(CONFIG_I2C_PERIPHERAL)+=i2c_peripheral.o
diff --git a/chip/it83xx/cec_bitbang.c b/chip/it83xx/cec_bitbang.c
new file mode 100644
index 0000000000..25d01b3b19
--- /dev/null
+++ b/chip/it83xx/cec_bitbang.c
@@ -0,0 +1,140 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cec.h"
+#include "cec_bitbang_chip.h"
+#include "console.h"
+#include "driver/cec/bitbang.h"
+#include "gpio.h"
+#include "hwtimer_chip.h"
+#include "task.h"
+#include "timer.h"
+#include "util.h"
+
+#ifdef CONFIG_CEC_DEBUG
+#define CPRINTF(format, args...) cprintf(CC_CEC, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CEC, format, ##args)
+#else
+#define CPRINTF(...)
+#define CPRINTS(...)
+#endif
+
+/* Timestamp when the most recent interrupt occurred */
+static timestamp_t interrupt_time;
+
+/* Timestamp when the second most recent interrupt occurred */
+static timestamp_t prev_interrupt_time;
+
+/* Flag set when a transfer is initiated from the AP */
+static bool transfer_initiated;
+
+/*
+ * ITE doesn't have a capture timer, so we use a countdown timer for timeout
+ * events combined with a GPIO interrupt for capture events.
+ */
+void cec_tmr_cap_start(enum cec_cap_edge edge, int timeout)
+{
+	switch (edge) {
+	case CEC_CAP_EDGE_NONE:
+		gpio_disable_interrupt(CEC_GPIO_IN);
+		break;
+	case CEC_CAP_EDGE_FALLING:
+		gpio_set_flags(CEC_GPIO_IN, GPIO_INT_FALLING);
+		gpio_enable_interrupt(CEC_GPIO_IN);
+		break;
+	case CEC_CAP_EDGE_RISING:
+		gpio_set_flags(CEC_GPIO_IN, GPIO_INT_RISING);
+		gpio_enable_interrupt(CEC_GPIO_IN);
+		break;
+	}
+
+	if (timeout > 0) {
+		/*
+		 * Take into account the delay from when the interrupt occurs to
+		 * when we actually get here.
+		 */
+		int delay =
+			CEC_US_TO_TICKS(get_time().val - interrupt_time.val);
+		int timer_count = timeout - delay;
+
+		/*
+		 * Handle the case where the delay is greater than the timeout.
+		 * This should never actually happen for typical delay and
+		 * timeout values.
+		 */
+		if (timer_count < 0) {
+			timer_count = 0;
+			CPRINTS("CEC WARNING: timer_count < 0");
+		}
+
+		/* Start the timer and enable the timer interrupt */
+		ext_timer_ms(CEC_EXT_TIMER, CEC_CLOCK_SOURCE, 1, 1, timer_count,
+			     0, 1);
+	} else {
+		ext_timer_stop(CEC_EXT_TIMER, 1);
+	}
+}
+
+void cec_tmr_cap_stop(void)
+{
+	gpio_disable_interrupt(CEC_GPIO_IN);
+	ext_timer_stop(CEC_EXT_TIMER, 1);
+}
+
+int cec_tmr_cap_get(void)
+{
+	return CEC_US_TO_TICKS(interrupt_time.val - prev_interrupt_time.val);
+}
+
+__override void cec_update_interrupt_time(void)
+{
+	prev_interrupt_time = interrupt_time;
+	interrupt_time = get_time();
+}
+
+void cec_ext_timer_interrupt(void)
+{
+	if (transfer_initiated) {
+		transfer_initiated = false;
+		cec_event_tx();
+	} else {
+		cec_update_interrupt_time();
+		cec_event_timeout();
+	}
+}
+
+void cec_gpio_interrupt(enum gpio_signal signal)
+{
+	cec_update_interrupt_time();
+	cec_event_cap();
+}
+
+void cec_trigger_send(void)
+{
+	/* Elevate to interrupt context */
+	transfer_initiated = true;
+	task_trigger_irq(et_ctrl_regs[CEC_EXT_TIMER].irq);
+}
+
+void cec_enable_timer(void)
+{
+	/*
+	 * Nothing to do. Interrupts will be enabled as needed by
+	 * cec_tmr_cap_start().
+	 */
+}
+
+void cec_disable_timer(void)
+{
+	cec_tmr_cap_stop();
+
+	interrupt_time.val = 0;
+	prev_interrupt_time.val = 0;
+}
+
+void cec_init_timer(void)
+{
+	ext_timer_ms(CEC_EXT_TIMER, CEC_CLOCK_SOURCE, 0, 0, 0, 1, 0);
+}
diff --git a/chip/it83xx/cec_bitbang_chip.h b/chip/it83xx/cec_bitbang_chip.h
new file mode 100644
index 0000000000..daca59c921
--- /dev/null
+++ b/chip/it83xx/cec_bitbang_chip.h
@@ -0,0 +1,21 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_CEC_CHIP_H
+#define __CROS_EC_CEC_CHIP_H
+
+#include "hwtimer_chip.h"
+
+#define CEC_CLOCK_SOURCE EXT_PSR_32P768K_HZ
+#define CEC_CLOCK_FREQ_HZ 32768
+
+/* Time in us to timer clock ticks */
+#define CEC_US_TO_TICKS(t) ((t)*CEC_CLOCK_FREQ_HZ / 1000000)
+#ifdef CONFIG_CEC_DEBUG
+/* Timer clock ticks to us */
+#define CEC_TICKS_TO_US(ticks) (1000000 * (ticks) / CEC_CLOCK_FREQ_HZ)
+#endif
+
+#endif /* __CROS_EC_CEC_CHIP_H */
diff --git a/chip/it83xx/clock.c b/chip/it83xx/clock.c
index d38197379a..bd6ae01281 100644
--- a/chip/it83xx/clock.c
+++ b/chip/it83xx/clock.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,6 +9,7 @@
 #include "clock.h"
 #include "common.h"
 #include "console.h"
+#include "gpio.h"
 #include "hwtimer.h"
 #include "hwtimer_chip.h"
 #include "intc.h"
@@ -23,11 +24,11 @@
 
 /* Console output macros. */
 #define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args)
 
 #ifdef CONFIG_LOW_POWER_IDLE
 #define SLEEP_SET_HTIMER_DELAY_USEC 250
-#define SLEEP_FTIMER_SKIP_USEC      (HOOK_TICK_INTERVAL * 2)
+#define SLEEP_FTIMER_SKIP_USEC (HOOK_TICK_INTERVAL * 2)
 
 static timestamp_t sleep_mode_t0;
 static timestamp_t sleep_mode_t1;
@@ -39,13 +40,13 @@ static uint32_t ec_sleep;
  * Fixed amount of time to keep the console in use flag true after boot in
  * order to give a permanent window in which the heavy sleep mode is not used.
  */
-#define CONSOLE_IN_USE_ON_BOOT_TIME (15*SECOND)
+#define CONSOLE_IN_USE_ON_BOOT_TIME (15 * SECOND)
 static int console_in_use_timeout_sec = 5;
 static timestamp_t console_expire_time;
 
 /* clock source is 32.768KHz */
-#define TIMER_32P768K_CNT_TO_US(cnt) ((uint64_t)(cnt) * 1000000 / 32768)
-#define TIMER_CNT_8M_32P768K(cnt)    (((cnt) / (8000000 / 32768)) + 1)
+#define TIMER_32P768K_CNT_TO_US(cnt) ((uint64_t)(cnt)*1000000 / 32768)
+#define TIMER_CNT_8M_32P768K(cnt) (((cnt) / (8000000 / 32768)) + 1)
 #endif /*CONFIG_LOW_POWER_IDLE */
 
 static int freq;
@@ -65,10 +66,11 @@ static void clock_module_disable(void)
 	IT83XX_GCTRL_MCCR &= ~BIT(7);
 	clock_disable_peripheral((CGC_OFFSET_EGPC | CGC_OFFSET_CIR), 0, 0);
 	clock_disable_peripheral((CGC_OFFSET_SMBA | CGC_OFFSET_SMBB |
-		CGC_OFFSET_SMBC | CGC_OFFSET_SMBD | CGC_OFFSET_SMBE |
-		CGC_OFFSET_SMBF), 0, 0);
-	clock_disable_peripheral((CGC_OFFSET_SSPI | CGC_OFFSET_PECI |
-		CGC_OFFSET_USB), 0, 0);
+				  CGC_OFFSET_SMBC | CGC_OFFSET_SMBD |
+				  CGC_OFFSET_SMBE | CGC_OFFSET_SMBF),
+				 0, 0);
+	clock_disable_peripheral(
+		(CGC_OFFSET_SSPI | CGC_OFFSET_PECI | CGC_OFFSET_USB), 0, 0);
 }
 
 enum pll_freq_idx {
@@ -77,19 +79,11 @@ enum pll_freq_idx {
 	PLL_96_MHZ = 4,
 };
 
-static const uint8_t pll_to_idx[8] = {
-	0,
-	0,
-	PLL_24_MHZ,
-	0,
-	PLL_48_MHZ,
-	0,
-	0,
-	PLL_96_MHZ
-};
+static const uint8_t pll_to_idx[8] = { 0,	   0, PLL_24_MHZ, 0,
+				       PLL_48_MHZ, 0, 0,	  PLL_96_MHZ };
 
 struct clock_pll_t {
-	int     pll_freq;
+	int pll_freq;
 	uint8_t pll_setting;
 	uint8_t div_fnd;
 	uint8_t div_uart;
@@ -113,17 +107,17 @@ const struct clock_pll_t clock_pll_ctrl[] = {
 	 * SSPI:  48MHz(24MHz if PLL=24MHz)
 	 */
 	/* PLL:24MHz, MCU:24MHz, Fnd(e-flash):24MHz */
-	[PLL_24_MHZ] = {24000000, 2, 0, 0, 0, 0, 0, 2, 0, 0, 0x2},
+	[PLL_24_MHZ] = { 24000000, 2, 0, 0, 0, 0, 0, 2, 0, 0, 0x2 },
 #ifdef CONFIG_IT83XX_FLASH_CLOCK_48MHZ
 	/* PLL:48MHz, MCU:48MHz, Fnd:48MHz */
-	[PLL_48_MHZ] = {48000000, 4, 0, 1, 0, 1, 0, 6, 1, 0, 0x5},
+	[PLL_48_MHZ] = { 48000000, 4, 0, 1, 0, 1, 0, 6, 1, 0, 0x5 },
 	/* PLL:96MHz, MCU:96MHz, Fnd:48MHz */
-	[PLL_96_MHZ] = {96000000, 7, 1, 3, 1, 3, 1, 6, 3, 1, 0xb},
+	[PLL_96_MHZ] = { 96000000, 7, 1, 3, 1, 3, 1, 6, 3, 1, 0xb },
 #else
 	/* PLL:48MHz, MCU:48MHz, Fnd:24MHz */
-	[PLL_48_MHZ] = {48000000, 4, 1, 1, 0, 1, 0, 2, 1, 0, 0x5},
+	[PLL_48_MHZ] = { 48000000, 4, 1, 1, 0, 1, 0, 2, 1, 0, 0x5 },
 	/* PLL:96MHz, MCU:96MHz, Fnd:32MHz */
-	[PLL_96_MHZ] = {96000000, 7, 2, 3, 1, 3, 1, 4, 3, 1, 0xb},
+	[PLL_96_MHZ] = { 96000000, 7, 2, 3, 1, 3, 1, 4, 3, 1, 0xb },
 #endif
 };
 
@@ -134,9 +128,15 @@ static uint8_t pll_setting;
 
 void __ram_code clock_ec_pll_ctrl(enum ec_pll_ctrl mode)
 {
+	volatile uint8_t _pll_ctrl __unused;
+
 	IT83XX_ECPM_PLLCTRL = mode;
-	/* for deep doze / sleep mode */
-	IT83XX_ECPM_PLLCTRL = mode;
+	/*
+	 * for deep doze / sleep mode
+	 * This load operation will ensure PLL setting is taken into
+	 * control register before wait for interrupt instruction.
+	 */
+	_pll_ctrl = IT83XX_ECPM_PLLCTRL;
 
 #ifdef IT83XX_CHIP_FLASH_NO_DEEP_POWER_DOWN
 	/*
@@ -189,18 +189,18 @@ void __ram_code clock_pll_changed(void)
 	clock_ec_pll_ctrl(EC_PLL_SLEEP);
 	if (IS_ENABLED(CHIP_CORE_NDS32)) {
 		/* Global interrupt enable */
-		asm volatile ("setgie.e");
+		asm volatile("setgie.e");
 		/* EC sleep */
 		asm("standby wake_grant");
 		/* Global interrupt disable */
-		asm volatile ("setgie.d");
+		asm volatile("setgie.d");
 	} else if (IS_ENABLED(CHIP_CORE_RISCV)) {
 		/* Global interrupt enable */
-		asm volatile ("csrsi mstatus, 0x8");
+		asm volatile("csrsi mstatus, 0x8");
 		/* EC sleep */
 		asm("wfi");
 		/* Global interrupt disable */
-		asm volatile ("csrci mstatus, 0x8");
+		asm volatile("csrci mstatus, 0x8");
 	}
 	/* New FND clock frequency */
 	IT83XX_ECPM_SCDCR0 = (pll_div_fnd << 4);
@@ -213,20 +213,20 @@ static void clock_set_pll(enum pll_freq_idx idx)
 {
 	int pll;
 
-	pll_div_fnd  = clock_pll_ctrl[idx].div_fnd;
-	pll_div_ec   = clock_pll_ctrl[idx].div_ec;
+	pll_div_fnd = clock_pll_ctrl[idx].div_fnd;
+	pll_div_ec = clock_pll_ctrl[idx].div_ec;
 	pll_div_jtag = clock_pll_ctrl[idx].div_jtag;
-	pll_setting  = clock_pll_ctrl[idx].pll_setting;
+	pll_setting = clock_pll_ctrl[idx].pll_setting;
 
 	/* Update PLL settings or not */
 	if (((IT83XX_ECPM_PLLFREQR & 0xf) != pll_setting) ||
-		((IT83XX_ECPM_SCDCR0 & 0xf0) != (pll_div_fnd << 4)) ||
-		((IT83XX_ECPM_SCDCR3 & 0xf) != pll_div_ec)) {
+	    ((IT83XX_ECPM_SCDCR0 & 0xf0) != (pll_div_fnd << 4)) ||
+	    ((IT83XX_ECPM_SCDCR3 & 0xf) != pll_div_ec)) {
 		/* Enable hw timer to wakeup EC from the sleep mode */
-		ext_timer_ms(LOW_POWER_EXT_TIMER, EXT_PSR_32P768K_HZ,
-				1, 1, 5, 1, 0);
+		ext_timer_ms(LOW_POWER_EXT_TIMER, EXT_PSR_32P768K_HZ, 1, 1, 5,
+			     1, 0);
 		task_clear_pending_irq(et_ctrl_regs[LOW_POWER_EXT_TIMER].irq);
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 		/*
 		 * Workaround for (b:70537592):
 		 * We have to set chip select pin as input mode in order to
@@ -243,7 +243,7 @@ static void clock_set_pll(enum pll_freq_idx idx)
 #endif
 		/* Update PLL settings. */
 		clock_pll_changed();
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 #ifdef IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED
 		/* Enable eSPI pad after changing PLL sequence. */
 		espi_enable_pad(1);
@@ -257,13 +257,13 @@ static void clock_set_pll(enum pll_freq_idx idx)
 	pll = pll_to_idx[IT83XX_ECPM_PLLFREQR & 0xf];
 	/* USB and UART */
 	IT83XX_ECPM_SCDCR1 = (clock_pll_ctrl[pll].div_usb << 4) |
-				clock_pll_ctrl[pll].div_uart;
+			     clock_pll_ctrl[pll].div_uart;
 	/* SSPI and SMB */
 	IT83XX_ECPM_SCDCR2 = (clock_pll_ctrl[pll].div_sspi << 4) |
-				clock_pll_ctrl[pll].div_smb;
+			     clock_pll_ctrl[pll].div_smb;
 	/* USBPD and PWM */
 	IT83XX_ECPM_SCDCR4 = (clock_pll_ctrl[pll].div_usbpd << 4) |
-				clock_pll_ctrl[pll].div_pwm;
+			     clock_pll_ctrl[pll].div_pwm;
 	/* Current PLL frequency  */
 	freq = clock_pll_ctrl[pll].pll_freq;
 }
@@ -277,8 +277,7 @@ void clock_init(void)
 		/* Interrupt Vector Table Base Address, in 64k Byte unit */
 		IT83XX_GCTRL_IVTBAR = (CONFIG_RW_MEM_OFF >> 16) & 0xFF;
 
-#if (PLL_CLOCK == 24000000)     || \
-	(PLL_CLOCK == 48000000) || \
+#if (PLL_CLOCK == 24000000) || (PLL_CLOCK == 48000000) || \
 	(PLL_CLOCK == 96000000)
 	/* Set PLL frequency */
 	clock_set_pll(PLL_CLOCK / 24000000);
@@ -295,13 +294,17 @@ void clock_init(void)
 	 */
 	IT83XX_GCTRL_RSTS = (IT83XX_GCTRL_RSTS & 0x3F) + 0x40;
 
-#if defined(IT83XX_ESPI_RESET_MODULE_BY_FW) && defined(CONFIG_HOSTCMD_ESPI)
+#if defined(IT83XX_ESPI_RESET_MODULE_BY_FW) && \
+	defined(CONFIG_HOST_INTERFACE_ESPI)
 	/*
 	 * Because we don't support eSPI HW reset function (b/111480168) on DX
 	 * version, so we have to reset eSPI configurations during init to
 	 * ensure Host and EC are synchronized (especially for the field of
 	 * I/O mode)
+	 * Since bit4 of VWCTRL2 register is enabled, the below reset routine
+	 * will be able to reset pltrst# signal.
 	 */
+	IT83XX_ESPI_VWCTRL2 |= ESPI_PLTRST_ESPI_RESET;
 	if (!system_jumped_to_this_image())
 		espi_fw_reset_module();
 #endif
@@ -337,8 +340,8 @@ int clock_get_freq(void)
  */
 void clock_enable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode)
 {
-	volatile uint8_t *reg = (volatile uint8_t *)
-			(IT83XX_ECPM_BASE + (offset >> 8));
+	volatile uint8_t *reg =
+		(volatile uint8_t *)(IT83XX_ECPM_BASE + (offset >> 8));
 	uint8_t reg_mask = offset & 0xff;
 
 	/*
@@ -360,8 +363,8 @@ void clock_enable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode)
  */
 void clock_disable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode)
 {
-	volatile uint8_t *reg = (volatile uint8_t *)
-			(IT83XX_ECPM_BASE + (offset >> 8));
+	volatile uint8_t *reg =
+		(volatile uint8_t *)(IT83XX_ECPM_BASE + (offset >> 8));
 	uint8_t reg_mask = offset & 0xff;
 	uint8_t tmp_mask = 0;
 
@@ -380,7 +383,7 @@ void clock_refresh_console_in_use(void)
 }
 
 static void clock_event_timer_clock_change(enum ext_timer_clock_source clock,
-					uint32_t count)
+					   uint32_t count)
 {
 	IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) &= ~BIT(0);
 	IT83XX_ETWD_ETXPSR(EVENT_EXT_TIMER) = clock;
@@ -412,19 +415,19 @@ static int clock_allow_low_power_idle(void)
 
 	/* If timer interrupt status is set, don't go to sleep mode. */
 	if (*et_ctrl_regs[EVENT_EXT_TIMER].isr &
-		et_ctrl_regs[EVENT_EXT_TIMER].mask)
+	    et_ctrl_regs[EVENT_EXT_TIMER].mask)
 		return 0;
 
-	/*
-	 * If timer is less than 250us to expire, then we don't go to sleep
-	 * mode.
-	 */
+		/*
+		 * If timer is less than 250us to expire, then we don't go to
+		 * sleep mode.
+		 */
 #ifdef IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES
 	if (EVENT_TIMER_COUNT_TO_US(ext_observation_reg_read(EVENT_EXT_TIMER)) <
 #else
 	if (EVENT_TIMER_COUNT_TO_US(IT83XX_ETWD_ETXCNTOR(EVENT_EXT_TIMER)) <
 #endif
-		SLEEP_SET_HTIMER_DELAY_USEC)
+	    SLEEP_SET_HTIMER_DELAY_USEC)
 		return 0;
 
 	/*
@@ -434,7 +437,7 @@ static int clock_allow_low_power_idle(void)
 	 */
 	sleep_mode_t0 = get_time();
 	if ((sleep_mode_t0.le.lo > (0xffffffff - SLEEP_FTIMER_SKIP_USEC)) ||
-		(sleep_mode_t0.le.lo < SLEEP_FTIMER_SKIP_USEC))
+	    (sleep_mode_t0.le.lo < SLEEP_FTIMER_SKIP_USEC))
 		return 0;
 
 	/* If we are waked up by console, then keep awake at least 5s. */
@@ -449,7 +452,7 @@ int clock_ec_wake_from_sleep(void)
 	return ec_sleep;
 }
 
-void clock_cpu_standby(void)
+void __ram_code clock_cpu_standby(void)
 {
 	/* standby instruction */
 	if (IS_ENABLED(CHIP_CORE_NDS32)) {
@@ -533,7 +536,7 @@ void __enter_hibernate(uint32_t seconds, uint32_t microseconds)
 	/* EC sleep */
 	ec_sleep = 1;
 #if defined(IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED) && \
-defined(CONFIG_HOSTCMD_ESPI)
+	defined(CONFIG_HOST_INTERFACE_ESPI)
 	/* Disable eSPI pad. */
 	espi_enable_pad(0);
 #endif
@@ -546,14 +549,20 @@ defined(CONFIG_HOSTCMD_ESPI)
 	__builtin_unreachable();
 }
 
+/* use data type int here not bool to get better instruction number. */
+static volatile int wait_interrupt_fired;
 void clock_sleep_mode_wakeup_isr(void)
 {
 	uint32_t st_us, c;
 
+	/* Clear flag on each interrupt. */
+	if (IS_ENABLED(CHIP_CORE_RISCV))
+		wait_interrupt_fired = 0;
+
 	/* trigger a reboot if wake up EC from sleep mode (system hibernate) */
 	if (clock_ec_wake_from_sleep()) {
 #if defined(IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED) && \
-defined(CONFIG_HOSTCMD_ESPI)
+	defined(CONFIG_HOST_INTERFACE_ESPI)
 		/*
 		 * Enable eSPI pad.
 		 * We will not need to enable eSPI pad here if Dx is able to
@@ -571,9 +580,9 @@ defined(CONFIG_HOSTCMD_ESPI)
 
 	if (IT83XX_ECPM_PLLCTRL == EC_PLL_DEEP_DOZE) {
 		clock_ec_pll_ctrl(EC_PLL_DOZE);
-
 		/* update free running timer */
-		c = 0xffffffff - IT83XX_ETWD_ETXCNTOR(LOW_POWER_EXT_TIMER);
+		c = LOW_POWER_TIMER_MASK -
+		    IT83XX_ETWD_ETXCNTOR(LOW_POWER_EXT_TIMER);
 		st_us = TIMER_32P768K_CNT_TO_US(c);
 		sleep_mode_t1.val = sleep_mode_t0.val + st_us;
 		__hw_clock_source_set(sleep_mode_t1.le.lo);
@@ -595,15 +604,12 @@ defined(CONFIG_HOSTCMD_ESPI)
 	}
 }
 
-/**
- * Low power idle task. Executed when no tasks are ready to be scheduled.
- */
-void __idle(void)
+void __keep __idle_init(void)
 {
 	console_expire_time.val = get_time().val + CONSOLE_IN_USE_ON_BOOT_TIME;
 	/* init hw timer and clock source is 32.768 KHz */
-	ext_timer_ms(LOW_POWER_EXT_TIMER, EXT_PSR_32P768K_HZ, 1, 0,
-		0xffffffff, 1, 1);
+	ext_timer_ms(LOW_POWER_EXT_TIMER, EXT_PSR_32P768K_HZ, 1, 0, 0xffffffff,
+		     1, 1);
 
 	/*
 	 * Print when the idle task starts.  This is the lowest priority task,
@@ -611,10 +617,28 @@ void __idle(void)
 	 * their task inits and have gone to sleep.
 	 */
 	CPRINTS("low power idle task started");
+}
+
+/**
+ * Low power idle task. Executed when no tasks are ready to be scheduled.
+ */
+void __ram_code __idle(void)
+{
+	/*
+	 * There is not enough space from ram code section to cache entire idle
+	 * function, hence pull initialization function out of the section.
+	 */
+	__idle_init();
 
 	while (1) {
 		/* Disable interrupts */
 		interrupt_disable();
+#ifdef CONFIG_IT83XX_I2C_CMD_QUEUE
+		if (i2c_idle_not_allowed()) {
+			interrupt_enable();
+			continue;
+		}
+#endif
 		/* Check if the EC can enter deep doze mode or not */
 		if (DEEP_SLEEP_ALLOWED && clock_allow_low_power_idle()) {
 			/* reset low power mode hw timer */
@@ -636,8 +660,21 @@ void __idle(void)
 			clock_ec_pll_ctrl(EC_PLL_DOZE);
 			idle_doze_cnt++;
 		}
+		/* Set flag before entering low power mode. */
+		if (IS_ENABLED(CHIP_CORE_RISCV))
+			wait_interrupt_fired = 1;
 		clock_cpu_standby();
 		interrupt_enable();
+		/*
+		 * Sometimes wfi instruction may fail due to CPU's MTIP@mip
+		 * register is non-zero.
+		 * If the wait_interrupt_fired flag is true at this point,
+		 * it means that EC waked-up by the above issue not an
+		 * interrupt. Hence we loop running wfi instruction here until
+		 * wfi success.
+		 */
+		while (IS_ENABLED(CHIP_CORE_RISCV) && wait_interrupt_fired)
+			clock_cpu_standby();
 	}
 }
 #endif /* CONFIG_LOW_POWER_IDLE */
@@ -647,7 +684,7 @@ void __idle(void)
 /**
  * Print low power idle statistics
  */
-static int command_idle_stats(int argc, char **argv)
+static int command_idle_stats(int argc, const char **argv)
 {
 	timestamp_t ts = get_time();
 
@@ -655,13 +692,16 @@ static int command_idle_stats(int argc, char **argv)
 	ccprintf("Num idle calls that sleep:           %d\n", idle_sleep_cnt);
 
 	ccprintf("Total Time spent in sleep(sec):      %.6lld(s)\n",
-						total_idle_sleep_time_us);
+		 total_idle_sleep_time_us);
 	ccprintf("Total time on:                       %.6llds\n\n", ts.val);
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats,
-			"",
+DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, "",
 			"Print last idle stats");
 
 #endif /* CONFIG_CMD_IDLE_STATS */
 #endif /* CONFIG_LOW_POWER_IDLE */
+
+test_mockable void clock_enable_module(enum module_id module, int enable)
+{
+}
diff --git a/chip/it83xx/config_chip.h b/chip/it83xx/config_chip.h
index 2cc683ba20..537069972f 100644
--- a/chip/it83xx/config_chip.h
+++ b/chip/it83xx/config_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,7 @@
 #ifndef __CROS_EC_CONFIG_CHIP_H
 #define __CROS_EC_CONFIG_CHIP_H
 
-#if defined(CHIP_FAMILY_IT8320)    /* N8 core */
+#if defined(CHIP_FAMILY_IT8320) /* N8 core */
 #include "config_chip_it8320.h"
 #elif defined(CHIP_FAMILY_IT8XXX2) /* RISCV core */
 #include "config_chip_it8xxx2.h"
@@ -19,7 +19,7 @@
 
 /* Interval between HOOK_TICK notifications */
 #define HOOK_TICK_INTERVAL_MS 500
-#define HOOK_TICK_INTERVAL    (HOOK_TICK_INTERVAL_MS * MSEC)
+#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC)
 
 /* Default PLL frequency. */
 #define PLL_CLOCK 48000000
@@ -35,34 +35,34 @@
 #define I2C_ENHANCED_PORT_COUNT 3
 
 /* System stack size */
-#define CONFIG_STACK_SIZE           1024
+#define CONFIG_STACK_SIZE 1024
 
 /* non-standard task stack sizes */
-#define SMALLER_TASK_STACK_SIZE     (384 + CHIP_EXTRA_STACK_SPACE)
-#define IDLE_TASK_STACK_SIZE        (512 + CHIP_EXTRA_STACK_SPACE)
-#define LARGER_TASK_STACK_SIZE      (768 + CHIP_EXTRA_STACK_SPACE)
-#define VENTI_TASK_STACK_SIZE       (896 + CHIP_EXTRA_STACK_SPACE)
-#define ULTRA_TASK_STACK_SIZE       (1056 + CHIP_EXTRA_STACK_SPACE)
-#define TRENTA_TASK_STACK_SIZE      (1184 + CHIP_EXTRA_STACK_SPACE)
+#define SMALLER_TASK_STACK_SIZE (384 + CHIP_EXTRA_STACK_SPACE)
+#define IDLE_TASK_STACK_SIZE (512 + CHIP_EXTRA_STACK_SPACE)
+#define LARGER_TASK_STACK_SIZE (768 + CHIP_EXTRA_STACK_SPACE)
+#define VENTI_TASK_STACK_SIZE (896 + CHIP_EXTRA_STACK_SPACE)
+#define ULTRA_TASK_STACK_SIZE (1056 + CHIP_EXTRA_STACK_SPACE)
+#define TRENTA_TASK_STACK_SIZE (1184 + CHIP_EXTRA_STACK_SPACE)
 
 /* Default task stack size */
-#define TASK_STACK_SIZE             (512 + CHIP_EXTRA_STACK_SPACE)
+#define TASK_STACK_SIZE (512 + CHIP_EXTRA_STACK_SPACE)
 
 #ifdef IT83XX_CHIP_FLASH_IS_KGD
-#define CONFIG_FLASH_BANK_SIZE      0x00001000  /* protect bank size */
-#define CONFIG_FLASH_ERASE_SIZE     0x00001000  /* erase bank size */
+#define CONFIG_FLASH_BANK_SIZE 0x00001000 /* protect bank size */
+#define CONFIG_FLASH_ERASE_SIZE 0x00001000 /* erase bank size */
 #else
-#define CONFIG_FLASH_BANK_SIZE      0x00000800  /* protect bank size */
-#define CONFIG_FLASH_ERASE_SIZE     0x00000400  /* erase bank size */
+#define CONFIG_FLASH_BANK_SIZE 0x00000800 /* protect bank size */
+#define CONFIG_FLASH_ERASE_SIZE 0x00000400 /* erase bank size */
 #endif
-#define CONFIG_FLASH_WRITE_SIZE     0x00000004  /* minimum write size */
+#define CONFIG_FLASH_WRITE_SIZE 0x00000004 /* minimum write size */
 
 /*
  * This is the block size of the ILM on the it83xx chip.
  * The ILM for static code cache, CPU fetch instruction from
  * ILM(ILM -> CPU)instead of flash(flash -> IMMU -> CPU) if enabled.
  */
-#define IT83XX_ILM_BLOCK_SIZE       0x00001000
+#define IT83XX_ILM_BLOCK_SIZE 0x00001000
 
 #ifdef IT83XX_CHIP_FLASH_IS_KGD
 /*
@@ -101,9 +101,9 @@
  * IT8xxx2 series support mapping LPC/eSPI I/O cycle 800h ~ 9FFh
  * to 0x80081800 ~ 0x800819FF of DLM1.
  */
-#define CONFIG_H2RAM_BASE               (CHIP_H2RAM_BASE)
-#define CONFIG_H2RAM_SIZE               0x00001000
-#define CONFIG_H2RAM_HOST_LPC_IO_BASE   0x800
+#define CONFIG_H2RAM_BASE (CHIP_H2RAM_BASE)
+#define CONFIG_H2RAM_SIZE 0x00001000
+#define CONFIG_H2RAM_HOST_LPC_IO_BASE 0x800
 
 /****************************************************************************/
 /* Customize the build */
@@ -121,4 +121,6 @@
 #define GPIO_PIN(port, index) GPIO_##port, BIT(index)
 #define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m)
 
-#endif  /* __CROS_EC_CONFIG_CHIP_H */
+#define __RAM_CODE_SECTION_NAME ".ram_code"
+
+#endif /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/chip/it83xx/config_chip_it8320.h b/chip/it83xx/config_chip_it8320.h
index 6163ef8fb9..0e5c48c96a 100644
--- a/chip/it83xx/config_chip_it8320.h
+++ b/chip/it83xx/config_chip_it8320.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,19 +12,19 @@
 /* N8 core */
 #define CHIP_CORE_NDS32
 /* The base address of EC interrupt controller registers. */
-#define CHIP_EC_INTC_BASE           0x00F01100
+#define CHIP_EC_INTC_BASE 0x00F01100
 
 /****************************************************************************/
 /* Memory mapping */
 
-#define CHIP_H2RAM_BASE             0x0008D000 /* 0x0008D000~0x0008DFFF */
-#define CHIP_RAMCODE_BASE           0x0008E000 /* 0x0008E000~0x0008EFFF */
-#define CHIP_EXTRA_STACK_SPACE      0
+#define CHIP_H2RAM_BASE 0x0008D000 /* 0x0008D000~0x0008DFFF */
+#define CHIP_RAMCODE_BASE 0x0008E000 /* 0x0008E000~0x0008EFFF */
+#define CHIP_EXTRA_STACK_SPACE 0
 
-#define CONFIG_RAM_BASE             0x00080000
-#define CONFIG_RAM_SIZE             0x0000C000
+#define CONFIG_RAM_BASE 0x00080000
+#define CONFIG_RAM_SIZE 0x0000C000
 
-#define CONFIG_PROGRAM_MEMORY_BASE  0x00000000
+#define CONFIG_PROGRAM_MEMORY_BASE 0x00000000
 
 /****************************************************************************/
 /* Chip IT8320 is used with IT83XX TCPM driver */
@@ -36,7 +36,7 @@
  * doesn't support a write-protect pin, and if we make the write-protection
  * permanent, it can't be undone easily enough to support RMA.
  */
-#define CONFIG_FLASH_SIZE  0x00040000
+#define CONFIG_FLASH_SIZE_BYTES 0x00040000
 /* For IT8320BX, we have to reload cc parameters after ec softreset. */
 #define IT83XX_USBPD_CC_PARAMETER_RELOAD
 /*
@@ -45,7 +45,7 @@
  */
 #define IT83XX_USBPD_CC_VOLTAGE_DETECTOR_INDEPENDENT
 /* Chip IT8320BX actually has TCPC physical port count */
-#define IT83XX_USBPD_PHY_PORT_COUNT    2
+#define IT83XX_USBPD_PHY_PORT_COUNT 2
 /* For IT8320BX, we have to write 0xff to clear pending bit.*/
 #define IT83XX_ESPI_VWCTRL1_WRITE_FF_CLEAR
 /* For IT8320BX, we have to read observation register of external timer two
@@ -53,15 +53,18 @@
  */
 #define IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES
 #elif defined(CHIP_VARIANT_IT8320DX)
-#define CONFIG_FLASH_SIZE  0x00080000
+#define CONFIG_FLASH_SIZE_BYTES 0x00080000
 #define CONFIG_IT83XX_FLASH_CLOCK_48MHZ
 /*
  * Disable eSPI pad, then PLL change
  * (include EC clock frequency) is succeed even CS# is low.
  */
 #define IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED
-/* The slave frequency is adjustable (bit[2-0] at register IT83XX_ESPI_GCAC1) */
-#define IT83XX_ESPI_SLAVE_MAX_FREQ_CONFIGURABLE
+/*
+ * The peripheral frequency is adjustable
+ * (bit[2-0] at register IT83XX_ESPI_GCAC1)
+ */
+#define IT83XX_ESPI_PERIPHERAL_MAX_FREQ_CONFIGURABLE
 /*
  * TODO(b/111480168): eSPI HW reset can't be used because the DMA address
  * gets set incorrectly resulting in a memory access exception.
@@ -93,9 +96,9 @@
 /* Chip Dx transmit status bit of PD register is different from Bx. */
 #define IT83XX_PD_TX_ERROR_STATUS_BIT5
 /* Chip IT8320DX actually has TCPC physical port count */
-#define IT83XX_USBPD_PHY_PORT_COUNT    2
+#define IT83XX_USBPD_PHY_PORT_COUNT 2
 #else
 #error "Unsupported chip variant!"
 #endif
 
-#endif  /* __CROS_EC_CONFIG_CHIP_IT8320_H */
+#endif /* __CROS_EC_CONFIG_CHIP_IT8320_H */
diff --git a/chip/it83xx/config_chip_it8xxx2.h b/chip/it83xx/config_chip_it8xxx2.h
index fd7d4e94dd..cbbbd0bd55 100644
--- a/chip/it83xx/config_chip_it8xxx2.h
+++ b/chip/it83xx/config_chip_it8xxx2.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,6 +6,8 @@
 #ifndef __CROS_EC_CONFIG_CHIP_IT8XXX2_H
 #define __CROS_EC_CONFIG_CHIP_IT8XXX2_H
 
+#define __RAM_CODE_ILM0_SECTION_NAME ".ram_code_ilm0"
+
 /* CPU core BFD configuration */
 #include "core/riscv-rv32i/config_core.h"
 
@@ -13,7 +15,7 @@
 #define CHIP_CORE_RISCV
 #define CHIP_ILM_DLM_ORDER
 /* The base address of EC interrupt controller registers. */
-#define CHIP_EC_INTC_BASE           0x00F03F00
+#define CHIP_EC_INTC_BASE 0x00F03F00
 #define CONFIG_IT83XX_FLASH_CLOCK_48MHZ
 /*
  * ILM/DLM size register.
@@ -25,11 +27,11 @@
 /****************************************************************************/
 /* Memory mapping */
 
-#define CHIP_ILM_BASE               0x80000000
-#define CHIP_EXTRA_STACK_SPACE      128
+#define CHIP_ILM_BASE 0x80000000
+#define CHIP_EXTRA_STACK_SPACE 128
 /* We reserve 12KB space for ramcode, h2ram, and immu sections. */
-#define CHIP_RAM_SPACE_RESERVED     0x3000
-#define CONFIG_PROGRAM_MEMORY_BASE  (CHIP_ILM_BASE)
+#define CHIP_RAM_SPACE_RESERVED 0x3000
+#define CONFIG_PROGRAM_MEMORY_BASE (CHIP_ILM_BASE)
 
 /****************************************************************************/
 /* Chip IT83202 is used with IT8XXX2 TCPM driver */
@@ -37,9 +39,9 @@
 
 #if defined(CHIP_VARIANT_IT83202BX)
 /* TODO(b/133460224): enable properly chip config option. */
-#define CONFIG_FLASH_SIZE           0x00080000
-#define CONFIG_RAM_BASE             0x80080000
-#define CONFIG_RAM_SIZE             0x00010000
+#define CONFIG_FLASH_SIZE_BYTES 0x00080000
+#define CONFIG_RAM_BASE 0x80080000
+#define CONFIG_RAM_SIZE 0x00010000
 
 /* Embedded flash is KGD */
 #define IT83XX_CHIP_FLASH_IS_KGD
@@ -57,8 +59,11 @@
  * (include EC clock frequency) is succeed even CS# is low.
  */
 #define IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED
-/* The slave frequency is adjustable (bit[2-0] at register IT83XX_ESPI_GCAC1) */
-#define IT83XX_ESPI_SLAVE_MAX_FREQ_CONFIGURABLE
+/*
+ * The peripheral frequency is adjustable
+ * (bit[2-0] at register IT83XX_ESPI_GCAC1)
+ */
+#define IT83XX_ESPI_PERIPHERAL_MAX_FREQ_CONFIGURABLE
 /* Watchdog reset supports hardware reset. */
 #define IT83XX_ETWD_HW_RESET_SUPPORT
 /*
@@ -75,17 +80,34 @@
 /* Enable detect type-c plug in and out interrupt. */
 #define IT83XX_INTC_PLUG_IN_OUT_SUPPORT
 /* Chip IT83202BX actually has TCPC physical port count. */
-#define IT83XX_USBPD_PHY_PORT_COUNT    3
-#elif defined(CHIP_VARIANT_IT81302AX_1024) \
-|| defined(CHIP_VARIANT_IT81202AX_1024)
-#define CONFIG_FLASH_SIZE           0x00100000
-#define CONFIG_RAM_BASE             0x80100000
-#define CONFIG_RAM_SIZE             0x0000f000
+#define IT83XX_USBPD_PHY_PORT_COUNT 3
+#elif defined(CHIP_VARIANT_IT81302AX_1024) ||   \
+	defined(CHIP_VARIANT_IT81202AX_1024) || \
+	defined(CHIP_VARIANT_IT81302BX_1024) || \
+	defined(CHIP_VARIANT_IT81302BX_512) ||  \
+	defined(CHIP_VARIANT_IT81202BX_1024)
 
-/* Embedded flash is KGD */
-#define IT83XX_CHIP_FLASH_IS_KGD
+/*
+ * Workaround mul instruction bug, see:
+ * https://www.ite.com.tw/uploads/product_download/it81202-bx-chip-errata.pdf
+ */
+#undef CONFIG_RISCV_EXTENSION_M
+#define CONFIG_IT8XXX2_MUL_WORKAROUND
+
+#if defined(CHIP_VARIANT_IT81302BX_512)
+#define CONFIG_FLASH_SIZE_BYTES 0x00080000
+#define CONFIG_RAM_BASE 0x80080000
+#else
+#define CONFIG_FLASH_SIZE_BYTES 0x00100000
+#define CONFIG_RAM_BASE 0x80100000
 /* Set ILM (instruction local memory) size up to 1M bytes */
 #define IT83XX_CHIP_FLASH_SIZE_1MB
+#endif
+
+#define CONFIG_RAM_SIZE 0x0000f000
+
+/* Embedded flash is KGD */
+#define IT83XX_CHIP_FLASH_IS_KGD
 /* chip id is 3 bytes */
 #define IT83XX_CHIP_ID_3BYTES
 /*
@@ -98,8 +120,11 @@
  * (include EC clock frequency) is succeed even CS# is low.
  */
 #define IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED
-/* The slave frequency is adjustable (bit[2-0] at register IT83XX_ESPI_GCAC1) */
-#define IT83XX_ESPI_SLAVE_MAX_FREQ_CONFIGURABLE
+/*
+ * The peripheral frequency is adjustable
+ * (bit[2-0] at register IT83XX_ESPI_GCAC1)
+ */
+#define IT83XX_ESPI_PERIPHERAL_MAX_FREQ_CONFIGURABLE
 /* Watchdog reset supports hardware reset. */
 #define IT83XX_ETWD_HW_RESET_SUPPORT
 /*
@@ -107,7 +132,7 @@
  * Please refer to gpio_1p8v_sel[] for 1.8v GPIOs.
  */
 #define IT83XX_GPIO_1P8V_PIN_EXTENDED
-#ifdef CHIP_VARIANT_IT81202AX_1024
+#if defined(CHIP_VARIANT_IT81202AX_1024) || defined(CHIP_VARIANT_IT81202BX_1024)
 /* Pins of group K and L are set as internal pull-down at initialization. */
 #define IT83XX_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN
 #endif
@@ -123,19 +148,31 @@
 #define IT83XX_INTC_PLUG_IN_OUT_SUPPORT
 /* Wake up CPU from low power mode even if interrupts are disabled */
 #define IT83XX_RISCV_WAKEUP_CPU_WITHOUT_INT_ENABLED
-/* Auto reset rx fifo while CS# deasserted. */
-#define IT83XX_SPI_AUTO_RESET_RX_FIFO
-/* CPU accesses FIFO to reach rx valid data length. */
-#define IT83XX_SPI_RX_VALID_INT
 /* Individual setting CC1 and CC2 resistance. */
 #define IT83XX_USBPD_CC1_CC2_RESISTANCE_SEPARATE
 /* Chip actually has TCPC physical port count. */
-#define IT83XX_USBPD_PHY_PORT_COUNT    2
+#define IT83XX_USBPD_PHY_PORT_COUNT 2
 #else
 #error "Unsupported chip variant!"
 #endif
 
-#define CHIP_H2RAM_BASE   (CONFIG_RAM_BASE + 0x1000) /* base+1000h~base+1FFF */
-#define CHIP_RAMCODE_BASE (CONFIG_RAM_BASE + 0x2000) /* base+2000h~base+2FFF */
+#define CHIP_RAMCODE_ILM0 (CONFIG_RAM_BASE + 0) /* base+0000h~base+0FFF */
+#define CHIP_H2RAM_BASE (CONFIG_RAM_BASE + 0x1000) /* base+1000h~base+1FFF */
+#define CHIP_RAMCODE_BASE                                  \
+	(CONFIG_RAM_BASE + 0x2000) /* base+2000h~base+2FFF \
+				    */
+
+#ifdef BASEBOARD_KUKUI
+/*
+ * Reserved 0x80000~0xfffff 512kb on flash for saving EC logs (8kb space is
+ * enough to save the logs). This configuration reduces EC FW binary size to
+ * 512kb. With this config, we still have 4x kb space on RO and 6x kb space on
+ * RW.
+ */
+#define CHIP_FLASH_PRESERVE_LOGS_BASE 0x80000
+#define CHIP_FLASH_PRESERVE_LOGS_SIZE 0x2000
+#undef CONFIG_FLASH_SIZE_BYTES
+#define CONFIG_FLASH_SIZE_BYTES CHIP_FLASH_PRESERVE_LOGS_BASE
+#endif
 
-#endif  /* __CROS_EC_CONFIG_CHIP_IT8XXX2_H */
+#endif /* __CROS_EC_CONFIG_CHIP_IT8XXX2_H */
diff --git a/chip/it83xx/dac.c b/chip/it83xx/dac.c
index 695d1cbc68..2e563f7557 100644
--- a/chip/it83xx/dac.c
+++ b/chip/it83xx/dac.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -44,7 +44,7 @@ static void dac_init(void)
 }
 DECLARE_HOOK(HOOK_INIT, dac_init, HOOK_PRIO_INIT_DAC);
 
-static int command_dac(int argc, char **argv)
+static int command_dac(int argc, const char **argv)
 {
 	char *e;
 	int ch, mv, rv;
@@ -85,6 +85,5 @@ static int command_dac(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(dac, command_dac,
-			"[ch2-5] [0-3300mV]",
+DECLARE_CONSOLE_COMMAND(dac, command_dac, "[ch2-5] [0-3300mV]",
 			"Enable or disable(0mV) DAC output voltage.");
diff --git a/chip/it83xx/dac_chip.h b/chip/it83xx/dac_chip.h
index fa50769c85..07e44e2e79 100644
--- a/chip/it83xx/dac_chip.h
+++ b/chip/it83xx/dac_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -55,4 +55,3 @@ void dac_set_output_voltage(enum chip_dac_channel ch, int mv);
 int dac_get_output_voltage(enum chip_dac_channel ch);
 
 #endif /* __CROS_EC_DAC_CHIP_H */
-
diff --git a/chip/it83xx/ec2i.c b/chip/it83xx/ec2i.c
index be02a8f813..52f96b95d7 100644
--- a/chip/it83xx/ec2i.c
+++ b/chip/it83xx/ec2i.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,11 +16,11 @@
 
 static const struct ec2i_t keyboard_settings[] = {
 	/* Select logical device 06h(keyboard) */
-	{HOST_INDEX_LDN, LDN_KBC_KEYBOARD},
+	{ HOST_INDEX_LDN, LDN_KBC_KEYBOARD },
 	/* Set IRQ=01h for logical device */
-	{HOST_INDEX_IRQNUMX, 0x01},
-	/* Configure IRQTP for KBC. */
-#ifdef CONFIG_HOSTCMD_ESPI
+	{ HOST_INDEX_IRQNUMX, 0x01 },
+/* Configure IRQTP for KBC. */
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	/*
 	 * Interrupt request type select (IRQTP) for KBC.
 	 * bit 1, 0: IRQ request is buffered and applied to SERIRQ
@@ -39,55 +39,55 @@ static const struct ec2i_t keyboard_settings[] = {
 	 * Additionally, this interrupt is configured as edge-triggered on the
 	 * host side. So, match the trigger mode on the EC side as well.
 	 */
-	{HOST_INDEX_IRQTP, 0x02},
+	{ HOST_INDEX_IRQTP, 0x02 },
 #endif
 	/* Enable logical device */
-	{HOST_INDEX_LDA, 0x01},
+	{ HOST_INDEX_LDA, 0x01 },
 };
 
 #ifdef CONFIG_IT83XX_ENABLE_MOUSE_DEVICE
 static const struct ec2i_t mouse_settings[] = {
 	/* Select logical device 05h(mouse) */
-	{HOST_INDEX_LDN, LDN_KBC_MOUSE},
+	{ HOST_INDEX_LDN, LDN_KBC_MOUSE },
 	/* Set IRQ=0Ch for logical device */
-	{HOST_INDEX_IRQNUMX, 0x0C},
+	{ HOST_INDEX_IRQNUMX, 0x0C },
 	/* Enable logical device */
-	{HOST_INDEX_LDA, 0x01},
+	{ HOST_INDEX_LDA, 0x01 },
 };
 #endif
 
 static const struct ec2i_t pm1_settings[] = {
 	/* Select logical device 11h(PM1 ACPI) */
-	{HOST_INDEX_LDN, LDN_PMC1},
+	{ HOST_INDEX_LDN, LDN_PMC1 },
 	/* Set IRQ=00h for logical device */
-	{HOST_INDEX_IRQNUMX, 0x00},
+	{ HOST_INDEX_IRQNUMX, 0x00 },
 	/* Enable logical device */
-	{HOST_INDEX_LDA, 0x01},
+	{ HOST_INDEX_LDA, 0x01 },
 };
 
 static const struct ec2i_t pm2_settings[] = {
 	/* Select logical device 12h(PM2) */
-	{HOST_INDEX_LDN, LDN_PMC2},
+	{ HOST_INDEX_LDN, LDN_PMC2 },
 	/* I/O Port Base Address 200h/204h */
-	{HOST_INDEX_IOBAD0_MSB, 0x02},
-	{HOST_INDEX_IOBAD0_LSB, 0x00},
-	{HOST_INDEX_IOBAD1_MSB, 0x02},
-	{HOST_INDEX_IOBAD1_LSB, 0x04},
+	{ HOST_INDEX_IOBAD0_MSB, 0x02 },
+	{ HOST_INDEX_IOBAD0_LSB, 0x00 },
+	{ HOST_INDEX_IOBAD1_MSB, 0x02 },
+	{ HOST_INDEX_IOBAD1_LSB, 0x04 },
 	/* Set IRQ=00h for logical device */
-	{HOST_INDEX_IRQNUMX, 0x00},
+	{ HOST_INDEX_IRQNUMX, 0x00 },
 	/* Enable logical device */
-	{HOST_INDEX_LDA, 0x01},
+	{ HOST_INDEX_LDA, 0x01 },
 };
 
 static const struct ec2i_t smfi_settings[] = {
 	/* Select logical device 0Fh(SMFI) */
-	{HOST_INDEX_LDN, LDN_SMFI},
+	{ HOST_INDEX_LDN, LDN_SMFI },
 	/* H2RAM LPC I/O cycle Dxxx */
-	{HOST_INDEX_DSLDC6, 0x00},
+	{ HOST_INDEX_DSLDC6, 0x00 },
 	/* Enable H2RAM LPC I/O cycle */
-	{HOST_INDEX_DSLDC7, 0x01},
+	{ HOST_INDEX_DSLDC7, 0x01 },
 	/* Enable logical device */
-	{HOST_INDEX_LDA, 0x01},
+	{ HOST_INDEX_LDA, 0x01 },
 };
 
 /*
@@ -96,16 +96,16 @@ static const struct ec2i_t smfi_settings[] = {
  */
 static const struct ec2i_t pm3_settings[] = {
 	/* Select logical device 17h(PM3) */
-	{HOST_INDEX_LDN, LDN_PMC3},
+	{ HOST_INDEX_LDN, LDN_PMC3 },
 	/* I/O Port Base Address 80h */
-	{HOST_INDEX_IOBAD0_MSB, 0x00},
-	{HOST_INDEX_IOBAD0_LSB, 0x80},
-	{HOST_INDEX_IOBAD1_MSB, 0x00},
-	{HOST_INDEX_IOBAD1_LSB, 0x00},
+	{ HOST_INDEX_IOBAD0_MSB, 0x00 },
+	{ HOST_INDEX_IOBAD0_LSB, 0x80 },
+	{ HOST_INDEX_IOBAD1_MSB, 0x00 },
+	{ HOST_INDEX_IOBAD1_LSB, 0x00 },
 	/* Set IRQ=00h for logical device */
-	{HOST_INDEX_IRQNUMX, 0x00},
+	{ HOST_INDEX_IRQNUMX, 0x00 },
 	/* Enable logical device */
-	{HOST_INDEX_LDA, 0x01},
+	{ HOST_INDEX_LDA, 0x01 },
 };
 
 /*
@@ -115,28 +115,28 @@ static const struct ec2i_t pm3_settings[] = {
  */
 static const struct ec2i_t rtct_settings[] = {
 	/* Select logical device 10h(RTCT) */
-	{HOST_INDEX_LDN, LDN_RTCT},
+	{ HOST_INDEX_LDN, LDN_RTCT },
 	/* P80L Begin Index */
-	{HOST_INDEX_DSLDC4, P80L_P80LB},
+	{ HOST_INDEX_DSLDC4, P80L_P80LB },
 	/* P80L End Index */
-	{HOST_INDEX_DSLDC5, P80L_P80LE},
+	{ HOST_INDEX_DSLDC5, P80L_P80LE },
 	/* P80L Current Index */
-	{HOST_INDEX_DSLDC6, P80L_P80LC},
+	{ HOST_INDEX_DSLDC6, P80L_P80LC },
 };
 
 #ifdef CONFIG_UART_HOST
 static const struct ec2i_t uart2_settings[] = {
 	/* Select logical device 2h(UART2) */
-	{HOST_INDEX_LDN, LDN_UART2},
+	{ HOST_INDEX_LDN, LDN_UART2 },
 	/*
 	 * I/O port base address is 2F8h.
 	 * Host can use LPC I/O port 0x2F8 ~ 0x2FF to access UART2.
 	 * See specification 7.24.4 for more detial.
 	 */
-	{HOST_INDEX_IOBAD0_MSB, 0x02},
-	{HOST_INDEX_IOBAD0_LSB, 0xF8},
+	{ HOST_INDEX_IOBAD0_MSB, 0x02 },
+	{ HOST_INDEX_IOBAD0_LSB, 0xF8 },
 	/* IRQ number is 3 */
-	{HOST_INDEX_IRQNUMX, 0x03},
+	{ HOST_INDEX_IRQNUMX, 0x03 },
 	/*
 	 * Interrupt Request Type Select
 	 * bit1, 0: IRQ request is buffered and applied to SERIRQ.
@@ -144,9 +144,9 @@ static const struct ec2i_t uart2_settings[] = {
 	 * bit0, 0: Edge triggered mode.
 	 *       1: Level triggered mode.
 	 */
-	{HOST_INDEX_IRQTP, 0x02},
+	{ HOST_INDEX_IRQTP, 0x02 },
 	/* Enable logical device */
-	{HOST_INDEX_LDA, 0x01},
+	{ HOST_INDEX_LDA, 0x01 },
 };
 #endif
 
@@ -163,7 +163,7 @@ enum ec2i_status_mask {
 	EC2I_STATUS_CRIB = BIT(1),
 	/* 1: EC write-access is still processing with IHD register. */
 	EC2I_STATUS_CWIB = BIT(2),
-	EC2I_STATUS_ALL  = (EC2I_STATUS_CRIB | EC2I_STATUS_CWIB),
+	EC2I_STATUS_ALL = (EC2I_STATUS_CRIB | EC2I_STATUS_CWIB),
 };
 
 static int ec2i_wait_status_bit_cleared(enum ec2i_status_mask mask)
@@ -288,8 +288,7 @@ static void pnpcfg_configure(const struct ec2i_t *settings, size_t entries)
 	}
 }
 
-#define PNPCFG(_s)						\
-	pnpcfg_configure(_s##_settings, ARRAY_SIZE(_s##_settings))
+#define PNPCFG(_s) pnpcfg_configure(_s##_settings, ARRAY_SIZE(_s##_settings))
 
 static void pnpcfg_init(void)
 {
diff --git a/chip/it83xx/ec2i_chip.h b/chip/it83xx/ec2i_chip.h
index c8069f4ff5..73eeaa31f7 100644
--- a/chip/it83xx/ec2i_chip.h
+++ b/chip/it83xx/ec2i_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,9 +8,9 @@
 #ifndef __CROS_EC_EC2I_CHIP_H
 #define __CROS_EC_EC2I_CHIP_H
 
-#define P80L_P80LB               0
-#define P80L_P80LE               0x3F
-#define P80L_P80LC               0
+#define P80L_P80LB 0
+#define P80L_P80LE 0x3F
+#define P80L_P80LC 0
 #define P80L_BRAM_BANK1_SIZE_MASK 0x3F
 
 /* Index list of the host interface registers of PNPCFG */
diff --git a/chip/it83xx/espi.c b/chip/it83xx/espi.c
index c731a7ad7e..f59f3728bf 100644
--- a/chip/it83xx/espi.c
+++ b/chip/it83xx/espi.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,161 +7,131 @@
 
 #include "console.h"
 #include "espi.h"
+#include "gpio.h"
 #include "hooks.h"
 #include "port80.h"
 #include "power.h"
 #include "registers.h"
 #include "system.h"
+#include "system_boot_time.h"
 #include "task.h"
 #include "uart.h"
 #include "util.h"
 
 /* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args)
 
 struct vw_channel_t {
-	uint8_t  index;         /* VW index of signal */
-	uint8_t  level_mask;    /* level bit of signal */
-	uint8_t  valid_mask;    /* valid bit of signal */
+	uint8_t index; /* VW index of signal */
+	uint8_t level_mask; /* level bit of signal */
+	uint8_t valid_mask; /* valid bit of signal */
 };
 
-/* VW settings after the master enables the VW channel. */
+/* VW settings after the controller enables the VW channel. */
 static const struct vw_channel_t en_vw_setting[] = {
-	/* EC sends SUS_ACK# = 1 VW to PCH. That does not apply to GLK SoC. */
+/* EC sends SUS_ACK# = 1 VW to PCH. That does not apply to GLK SoC. */
 #ifndef CONFIG_CHIPSET_GEMINILAKE
-	{ESPI_SYSTEM_EVENT_VW_IDX_40,
-		VW_LEVEL_FIELD(0),
-		VW_VALID_FIELD(VW_IDX_40_SUS_ACK)},
+	{ ESPI_SYSTEM_EVENT_VW_IDX_40, VW_LEVEL_FIELD(0),
+	  VW_VALID_FIELD(VW_IDX_40_SUS_ACK) },
 #endif
 };
 
-/* VW settings after the master enables the OOB channel. */
+/* VW settings after the controller enables the OOB channel. */
 static const struct vw_channel_t en_oob_setting[] = {
-	{ESPI_SYSTEM_EVENT_VW_IDX_4,
-		VW_LEVEL_FIELD(0),
-		VW_VALID_FIELD(VW_IDX_4_OOB_RST_ACK)},
+	{ ESPI_SYSTEM_EVENT_VW_IDX_4, VW_LEVEL_FIELD(0),
+	  VW_VALID_FIELD(VW_IDX_4_OOB_RST_ACK) },
 };
 
-/* VW settings after the master enables the flash channel. */
+/* VW settings after the controller enables the flash channel. */
 static const struct vw_channel_t en_flash_setting[] = {
-	{ESPI_SYSTEM_EVENT_VW_IDX_5,
-		VW_LEVEL_FIELD(VW_IDX_5_BTLD_STATUS_DONE),
-		VW_VALID_FIELD(VW_IDX_5_BTLD_STATUS_DONE)},
+	{ ESPI_SYSTEM_EVENT_VW_IDX_5, VW_LEVEL_FIELD(VW_IDX_5_BTLD_STATUS_DONE),
+	  VW_VALID_FIELD(VW_IDX_5_BTLD_STATUS_DONE) },
 };
 
 /* VW settings at host startup */
 static const struct vw_channel_t vw_host_startup_setting[] = {
-	{ESPI_SYSTEM_EVENT_VW_IDX_6,
-		VW_LEVEL_FIELD(VW_IDX_6_SCI | VW_IDX_6_SMI |
-				VW_IDX_6_RCIN | VW_IDX_6_HOST_RST_ACK),
-		VW_VALID_FIELD(VW_IDX_6_SCI | VW_IDX_6_SMI |
-				VW_IDX_6_RCIN | VW_IDX_6_HOST_RST_ACK)},
+	{ ESPI_SYSTEM_EVENT_VW_IDX_6,
+	  VW_LEVEL_FIELD(VW_IDX_6_SCI | VW_IDX_6_SMI | VW_IDX_6_RCIN |
+			 VW_IDX_6_HOST_RST_ACK),
+	  VW_VALID_FIELD(VW_IDX_6_SCI | VW_IDX_6_SMI | VW_IDX_6_RCIN |
+			 VW_IDX_6_HOST_RST_ACK) },
 };
 
 #define VW_CHAN(name, idx, level, valid) \
-	[(name - VW_SIGNAL_START)] = {idx, level, valid}
+	[(name - VW_SIGNAL_START)] = { idx, level, valid }
 
 /* VW signals used in eSPI (NOTE: must match order of enum espi_vw_signal). */
 static const struct vw_channel_t vw_channel_list[] = {
-	/* index 02h: master to slave. */
-	VW_CHAN(VW_SLP_S3_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_2,
+	/* index 02h: controller to peripheral. */
+	VW_CHAN(VW_SLP_S3_L, ESPI_SYSTEM_EVENT_VW_IDX_2,
 		VW_LEVEL_FIELD(VW_IDX_2_SLP_S3),
 		VW_VALID_FIELD(VW_IDX_2_SLP_S3)),
-	VW_CHAN(VW_SLP_S4_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_2,
+	VW_CHAN(VW_SLP_S4_L, ESPI_SYSTEM_EVENT_VW_IDX_2,
 		VW_LEVEL_FIELD(VW_IDX_2_SLP_S4),
 		VW_VALID_FIELD(VW_IDX_2_SLP_S4)),
-	VW_CHAN(VW_SLP_S5_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_2,
+	VW_CHAN(VW_SLP_S5_L, ESPI_SYSTEM_EVENT_VW_IDX_2,
 		VW_LEVEL_FIELD(VW_IDX_2_SLP_S5),
 		VW_VALID_FIELD(VW_IDX_2_SLP_S5)),
-	/* index 03h: master to slave. */
-	VW_CHAN(VW_SUS_STAT_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_3,
+	/* index 03h: controller to peripheral. */
+	VW_CHAN(VW_SUS_STAT_L, ESPI_SYSTEM_EVENT_VW_IDX_3,
 		VW_LEVEL_FIELD(VW_IDX_3_SUS_STAT),
 		VW_VALID_FIELD(VW_IDX_3_SUS_STAT)),
-	VW_CHAN(VW_PLTRST_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_3,
+	VW_CHAN(VW_PLTRST_L, ESPI_SYSTEM_EVENT_VW_IDX_3,
 		VW_LEVEL_FIELD(VW_IDX_3_PLTRST),
 		VW_VALID_FIELD(VW_IDX_3_PLTRST)),
-	VW_CHAN(VW_OOB_RST_WARN,
-		ESPI_SYSTEM_EVENT_VW_IDX_3,
+	VW_CHAN(VW_OOB_RST_WARN, ESPI_SYSTEM_EVENT_VW_IDX_3,
 		VW_LEVEL_FIELD(VW_IDX_3_OOB_RST_WARN),
 		VW_VALID_FIELD(VW_IDX_3_OOB_RST_WARN)),
-	/* index 04h: slave to master. */
-	VW_CHAN(VW_OOB_RST_ACK,
-		ESPI_SYSTEM_EVENT_VW_IDX_4,
+	/* index 04h: peripheral to controller. */
+	VW_CHAN(VW_OOB_RST_ACK, ESPI_SYSTEM_EVENT_VW_IDX_4,
 		VW_LEVEL_FIELD(VW_IDX_4_OOB_RST_ACK),
 		VW_VALID_FIELD(VW_IDX_4_OOB_RST_ACK)),
-	VW_CHAN(VW_WAKE_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_4,
-		VW_LEVEL_FIELD(VW_IDX_4_WAKE),
-		VW_VALID_FIELD(VW_IDX_4_WAKE)),
-	VW_CHAN(VW_PME_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_4,
-		VW_LEVEL_FIELD(VW_IDX_4_PME),
-		VW_VALID_FIELD(VW_IDX_4_PME)),
-	/* index 05h: slave to master. */
-	VW_CHAN(VW_ERROR_FATAL,
-		ESPI_SYSTEM_EVENT_VW_IDX_5,
-		VW_LEVEL_FIELD(VW_IDX_5_FATAL),
-		VW_VALID_FIELD(VW_IDX_5_FATAL)),
-	VW_CHAN(VW_ERROR_NON_FATAL,
-		ESPI_SYSTEM_EVENT_VW_IDX_5,
+	VW_CHAN(VW_WAKE_L, ESPI_SYSTEM_EVENT_VW_IDX_4,
+		VW_LEVEL_FIELD(VW_IDX_4_WAKE), VW_VALID_FIELD(VW_IDX_4_WAKE)),
+	VW_CHAN(VW_PME_L, ESPI_SYSTEM_EVENT_VW_IDX_4,
+		VW_LEVEL_FIELD(VW_IDX_4_PME), VW_VALID_FIELD(VW_IDX_4_PME)),
+	/* index 05h: peripheral to controller. */
+	VW_CHAN(VW_ERROR_FATAL, ESPI_SYSTEM_EVENT_VW_IDX_5,
+		VW_LEVEL_FIELD(VW_IDX_5_FATAL), VW_VALID_FIELD(VW_IDX_5_FATAL)),
+	VW_CHAN(VW_ERROR_NON_FATAL, ESPI_SYSTEM_EVENT_VW_IDX_5,
 		VW_LEVEL_FIELD(VW_IDX_5_NON_FATAL),
 		VW_VALID_FIELD(VW_IDX_5_NON_FATAL)),
-	VW_CHAN(VW_SLAVE_BTLD_STATUS_DONE,
-		ESPI_SYSTEM_EVENT_VW_IDX_5,
+	VW_CHAN(VW_PERIPHERAL_BTLD_STATUS_DONE, ESPI_SYSTEM_EVENT_VW_IDX_5,
 		VW_LEVEL_FIELD(VW_IDX_5_BTLD_STATUS_DONE),
 		VW_VALID_FIELD(VW_IDX_5_BTLD_STATUS_DONE)),
-	/* index 06h: slave to master. */
-	VW_CHAN(VW_SCI_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_6,
-		VW_LEVEL_FIELD(VW_IDX_6_SCI),
-		VW_VALID_FIELD(VW_IDX_6_SCI)),
-	VW_CHAN(VW_SMI_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_6,
-		VW_LEVEL_FIELD(VW_IDX_6_SMI),
-		VW_VALID_FIELD(VW_IDX_6_SMI)),
-	VW_CHAN(VW_RCIN_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_6,
-		VW_LEVEL_FIELD(VW_IDX_6_RCIN),
-		VW_VALID_FIELD(VW_IDX_6_RCIN)),
-	VW_CHAN(VW_HOST_RST_ACK,
-		ESPI_SYSTEM_EVENT_VW_IDX_6,
+	/* index 06h: peripheral to controller. */
+	VW_CHAN(VW_SCI_L, ESPI_SYSTEM_EVENT_VW_IDX_6,
+		VW_LEVEL_FIELD(VW_IDX_6_SCI), VW_VALID_FIELD(VW_IDX_6_SCI)),
+	VW_CHAN(VW_SMI_L, ESPI_SYSTEM_EVENT_VW_IDX_6,
+		VW_LEVEL_FIELD(VW_IDX_6_SMI), VW_VALID_FIELD(VW_IDX_6_SMI)),
+	VW_CHAN(VW_RCIN_L, ESPI_SYSTEM_EVENT_VW_IDX_6,
+		VW_LEVEL_FIELD(VW_IDX_6_RCIN), VW_VALID_FIELD(VW_IDX_6_RCIN)),
+	VW_CHAN(VW_HOST_RST_ACK, ESPI_SYSTEM_EVENT_VW_IDX_6,
 		VW_LEVEL_FIELD(VW_IDX_6_HOST_RST_ACK),
 		VW_VALID_FIELD(VW_IDX_6_HOST_RST_ACK)),
-	/* index 07h: master to slave. */
-	VW_CHAN(VW_HOST_RST_WARN,
-		ESPI_SYSTEM_EVENT_VW_IDX_7,
+	/* index 07h: controller to peripheral. */
+	VW_CHAN(VW_HOST_RST_WARN, ESPI_SYSTEM_EVENT_VW_IDX_7,
 		VW_LEVEL_FIELD(VW_IDX_7_HOST_RST_WARN),
 		VW_VALID_FIELD(VW_IDX_7_HOST_RST_WARN)),
-	/* index 40h: slave to master. */
-	VW_CHAN(VW_SUS_ACK,
-		ESPI_SYSTEM_EVENT_VW_IDX_40,
+	/* index 40h: peripheral to controller. */
+	VW_CHAN(VW_SUS_ACK, ESPI_SYSTEM_EVENT_VW_IDX_40,
 		VW_LEVEL_FIELD(VW_IDX_40_SUS_ACK),
 		VW_VALID_FIELD(VW_IDX_40_SUS_ACK)),
-	/* index 41h: master to slave. */
-	VW_CHAN(VW_SUS_WARN_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_41,
+	/* index 41h: controller to peripheral. */
+	VW_CHAN(VW_SUS_WARN_L, ESPI_SYSTEM_EVENT_VW_IDX_41,
 		VW_LEVEL_FIELD(VW_IDX_41_SUS_WARN),
 		VW_VALID_FIELD(VW_IDX_41_SUS_WARN)),
-	VW_CHAN(VW_SUS_PWRDN_ACK_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_41,
+	VW_CHAN(VW_SUS_PWRDN_ACK_L, ESPI_SYSTEM_EVENT_VW_IDX_41,
 		VW_LEVEL_FIELD(VW_IDX_41_SUS_PWRDN_ACK),
 		VW_VALID_FIELD(VW_IDX_41_SUS_PWRDN_ACK)),
-	VW_CHAN(VW_SLP_A_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_41,
+	VW_CHAN(VW_SLP_A_L, ESPI_SYSTEM_EVENT_VW_IDX_41,
 		VW_LEVEL_FIELD(VW_IDX_41_SLP_A),
 		VW_VALID_FIELD(VW_IDX_41_SLP_A)),
-	/* index 42h: master to slave. */
-	VW_CHAN(VW_SLP_LAN,
-		ESPI_SYSTEM_EVENT_VW_IDX_42,
+	/* index 42h: controller to peripheral. */
+	VW_CHAN(VW_SLP_LAN, ESPI_SYSTEM_EVENT_VW_IDX_42,
 		VW_LEVEL_FIELD(VW_IDX_42_SLP_LAN),
 		VW_VALID_FIELD(VW_IDX_42_SLP_LAN)),
-	VW_CHAN(VW_SLP_WLAN,
-		ESPI_SYSTEM_EVENT_VW_IDX_42,
+	VW_CHAN(VW_SLP_WLAN, ESPI_SYSTEM_EVENT_VW_IDX_42,
 		VW_LEVEL_FIELD(VW_IDX_42_SLP_WLAN),
 		VW_VALID_FIELD(VW_IDX_42_SLP_WLAN)),
 };
@@ -220,11 +190,11 @@ int espi_vw_get_wire(enum espi_vw_signal signal)
 
 	/* Not valid */
 	if (!(IT83XX_ESPI_VWIDX(vw_channel_list[i].index) &
-		vw_channel_list[i].valid_mask))
+	      vw_channel_list[i].valid_mask))
 		return 0;
 
 	return !!(IT83XX_ESPI_VWIDX(vw_channel_list[i].index) &
-		vw_channel_list[i].level_mask);
+		  vw_channel_list[i].level_mask);
 }
 
 /**
@@ -264,7 +234,7 @@ int espi_vw_disable_wire_int(enum espi_vw_signal signal)
 
 /* Configure virtual wire outputs */
 static void espi_configure_vw(const struct vw_channel_t *settings,
-						size_t entries)
+			      size_t entries)
 {
 	size_t i;
 
@@ -276,13 +246,13 @@ static void espi_configure_vw(const struct vw_channel_t *settings,
 static void espi_vw_host_startup(void)
 {
 	espi_configure_vw(vw_host_startup_setting,
-				ARRAY_SIZE(vw_host_startup_setting));
+			  ARRAY_SIZE(vw_host_startup_setting));
 }
 
 static void espi_vw_no_isr(uint8_t flag_changed, uint8_t vw_evt)
 {
 	CPRINTS("espi VW interrupt event is ignored! (bit%d at VWCTRL1)",
-								vw_evt);
+		vw_evt);
 }
 
 #ifndef CONFIG_CHIPSET_GEMINILAKE
@@ -297,13 +267,14 @@ static void espi_vw_idx7_isr(uint8_t flag_changed, uint8_t vw_evt)
 {
 	if (flag_changed & VW_LEVEL_FIELD(VW_IDX_7_HOST_RST_WARN))
 		espi_vw_set_wire(VW_HOST_RST_ACK,
-			espi_vw_get_wire(VW_HOST_RST_WARN));
+				 espi_vw_get_wire(VW_HOST_RST_WARN));
 }
 
 #ifdef CONFIG_CHIPSET_RESET_HOOK
 static void espi_chipset_reset(void)
 {
 	hook_notify(HOOK_CHIPSET_RESET);
+	update_ap_boot_time(ESPIRST);
 }
 DECLARE_DEFERRED(espi_chipset_reset);
 #endif
@@ -315,12 +286,14 @@ static void espi_vw_idx3_isr(uint8_t flag_changed, uint8_t vw_evt)
 
 		if (pltrst) {
 			espi_vw_host_startup();
+			update_ap_boot_time(PLTRST_HIGH);
 		} else {
 #ifdef CONFIG_CHIPSET_RESET_HOOK
 			hook_call_deferred(&espi_chipset_reset_data, MSEC);
 #endif
 			/* Store port 80 reset event */
 			port_80_write(PORT_80_EVENT_RESET);
+			update_ap_boot_time(PLTRST_LOW);
 		}
 
 		CPRINTS("VW PLTRST_L %sasserted", pltrst ? "de" : "");
@@ -328,7 +301,7 @@ static void espi_vw_idx3_isr(uint8_t flag_changed, uint8_t vw_evt)
 
 	if (flag_changed & VW_LEVEL_FIELD(VW_IDX_3_OOB_RST_WARN))
 		espi_vw_set_wire(VW_OOB_RST_ACK,
-			espi_vw_get_wire(VW_OOB_RST_WARN));
+				 espi_vw_get_wire(VW_OOB_RST_WARN));
 }
 
 static void espi_vw_idx2_isr(uint8_t flag_changed, uint8_t vw_evt)
@@ -352,25 +325,25 @@ struct vw_interrupt_t {
  */
 #ifdef CONFIG_CHIPSET_GEMINILAKE
 static const struct vw_interrupt_t vw_isr_list[] = {
-	[0] = {espi_vw_idx2_isr,  ESPI_SYSTEM_EVENT_VW_IDX_2},
-	[1] = {espi_vw_idx3_isr,  ESPI_SYSTEM_EVENT_VW_IDX_3},
-	[2] = {espi_vw_idx7_isr,  ESPI_SYSTEM_EVENT_VW_IDX_7},
-	[3] = {espi_vw_no_isr,    ESPI_SYSTEM_EVENT_VW_IDX_41},
-	[4] = {espi_vw_no_isr,    ESPI_SYSTEM_EVENT_VW_IDX_42},
-	[5] = {espi_vw_no_isr,    ESPI_SYSTEM_EVENT_VW_IDX_43},
-	[6] = {espi_vw_no_isr,    ESPI_SYSTEM_EVENT_VW_IDX_44},
-	[7] = {espi_vw_no_isr,    ESPI_SYSTEM_EVENT_VW_IDX_47},
+	[0] = { espi_vw_idx2_isr, ESPI_SYSTEM_EVENT_VW_IDX_2 },
+	[1] = { espi_vw_idx3_isr, ESPI_SYSTEM_EVENT_VW_IDX_3 },
+	[2] = { espi_vw_idx7_isr, ESPI_SYSTEM_EVENT_VW_IDX_7 },
+	[3] = { espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_41 },
+	[4] = { espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_42 },
+	[5] = { espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_43 },
+	[6] = { espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_44 },
+	[7] = { espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_47 },
 };
 #else
 static const struct vw_interrupt_t vw_isr_list[] = {
-	[0] = {espi_vw_idx2_isr,  ESPI_SYSTEM_EVENT_VW_IDX_2},
-	[1] = {espi_vw_idx3_isr,  ESPI_SYSTEM_EVENT_VW_IDX_3},
-	[2] = {espi_vw_idx7_isr,  ESPI_SYSTEM_EVENT_VW_IDX_7},
-	[3] = {espi_vw_idx41_isr, ESPI_SYSTEM_EVENT_VW_IDX_41},
-	[4] = {espi_vw_no_isr,    ESPI_SYSTEM_EVENT_VW_IDX_42},
-	[5] = {espi_vw_no_isr,    ESPI_SYSTEM_EVENT_VW_IDX_43},
-	[6] = {espi_vw_no_isr,    ESPI_SYSTEM_EVENT_VW_IDX_44},
-	[7] = {espi_vw_no_isr,    ESPI_SYSTEM_EVENT_VW_IDX_47},
+	[0] = { espi_vw_idx2_isr, ESPI_SYSTEM_EVENT_VW_IDX_2 },
+	[1] = { espi_vw_idx3_isr, ESPI_SYSTEM_EVENT_VW_IDX_3 },
+	[2] = { espi_vw_idx7_isr, ESPI_SYSTEM_EVENT_VW_IDX_7 },
+	[3] = { espi_vw_idx41_isr, ESPI_SYSTEM_EVENT_VW_IDX_41 },
+	[4] = { espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_42 },
+	[5] = { espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_43 },
+	[6] = { espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_44 },
+	[7] = { espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_47 },
 };
 #endif
 
@@ -438,6 +411,12 @@ void espi_reset_pin_asserted_interrupt(enum gpio_signal signal)
 {
 #ifdef IT83XX_ESPI_RESET_MODULE_BY_FW
 	espi_fw_reset_module();
+	/*
+	 * bit[7], enable P80L function.
+	 * bit[6], accept port 80h cycle.
+	 * bit[1-0], 10b: I2EC is read-only.
+	 */
+	IT83XX_GCTRL_SPCTRL1 |= 0xC2;
 #endif
 	/* reset vw_index_flag when espi_reset# asserted. */
 	espi_reset_vw_index_flags();
@@ -483,39 +462,39 @@ static void espi_enable_reset(void)
 
 #endif
 	IT83XX_GPIO_GCR = (IT83XX_GPIO_GCR & ~0x6) |
-		(config << IT83XX_GPIO_GCR_LPC_RST_POS);
+			  (config << IT83XX_GPIO_GCR_LPC_RST_POS);
 
 	/* enable interrupt of EC's espi_reset pin */
 	gpio_clear_pending_interrupt(GPIO_ESPI_RESET_L);
 	gpio_enable_interrupt(GPIO_ESPI_RESET_L);
 }
 
-/* Interrupt event of master enables the VW channel. */
+/* Interrupt event of controller enables the VW channel. */
 static void espi_vw_en_asserted(uint8_t evt)
 {
 	/*
-	 * Configure slave to master virtual wire outputs after receiving
-	 * the event of master enables the VW channel.
+	 * Configure peripheral to controller virtual wire outputs after
+	 * receiving the event of controller enables the VW channel.
 	 */
 	espi_configure_vw(en_vw_setting, ARRAY_SIZE(en_vw_setting));
 }
 
-/* Interrupt event of master enables the OOB channel. */
+/* Interrupt event of controller enables the OOB channel. */
 static void espi_oob_en_asserted(uint8_t evt)
 {
 	/*
-	 * Configure slave to master virtual wire outputs after receiving
-	 * the event of master enables the OOB channel.
+	 * Configure peripheral to controller virtual wire outputs after
+	 * receiving the event of controller enables the OOB channel.
 	 */
 	espi_configure_vw(en_oob_setting, ARRAY_SIZE(en_oob_setting));
 }
 
-/* Interrupt event of master enables the flash channel. */
+/* Interrupt event of controller enables the flash channel. */
 static void espi_flash_en_asserted(uint8_t evt)
 {
 	/*
-	 * Configure slave to master virtual wire outputs after receiving
-	 * the event of master enables the flash channel.
+	 * Configure peripheral to controller virtual wire outputs after
+	 * receiving the event of controller enables the flash channel.
 	 */
 	espi_configure_vw(en_flash_setting, ARRAY_SIZE(en_flash_setting));
 }
@@ -530,14 +509,10 @@ static void espi_no_isr(uint8_t evt)
  * IT83XX_ESPI_ESGCTRL0 register.
  */
 static void (*espi_isr[])(uint8_t evt) = {
-	[0] = espi_no_isr,
-	[1] = espi_vw_en_asserted,
-	[2] = espi_oob_en_asserted,
-	[3] = espi_flash_en_asserted,
-	[4] = espi_no_isr,
-	[5] = espi_no_isr,
-	[6] = espi_no_isr,
-	[7] = espi_no_isr,
+	[0] = espi_no_isr,	    [1] = espi_vw_en_asserted,
+	[2] = espi_oob_en_asserted, [3] = espi_flash_en_asserted,
+	[4] = espi_no_isr,	    [5] = espi_no_isr,
+	[6] = espi_no_isr,	    [7] = espi_no_isr,
 };
 
 void espi_interrupt(void)
@@ -554,8 +529,8 @@ void espi_interrupt(void)
 			espi_isr[i](i);
 	}
 	/*
-	 * bit7: the slave has received a peripheral posted/completion.
-	 * This bit indicates the slave has received a packet from eSPI
+	 * bit7: the peripheral has received a peripheral posted/completion.
+	 * This bit indicates the peripheral has received a packet from eSPI
 	 * peripheral channel. We can check cycle type (bit[3-0] at ESPCTRL0)
 	 * and make corresponding modification if needed.
 	 */
@@ -584,14 +559,14 @@ void espi_enable_pad(int enable)
 void espi_init(void)
 {
 	/*
-	 * bit[2-0], the maximum frequency of operation supported by slave:
+	 * bit[2-0], the maximum frequency of operation supported by peripheral:
 	 * 000b: 20MHz
 	 * 001b: 25MHz
 	 * 010b: 33MHz
 	 * 011b: 50MHz
 	 * 100b: 66MHz
 	 */
-#ifdef IT83XX_ESPI_SLAVE_MAX_FREQ_CONFIGURABLE
+#ifdef IT83XX_ESPI_PERIPHERAL_MAX_FREQ_CONFIGURABLE
 	IT83XX_ESPI_GCAC1 = (IT83XX_ESPI_GCAC1 & ~0x7) | BIT(2);
 #endif
 	/* reset vw_index_flag at initialization */
diff --git a/chip/it83xx/fan.c b/chip/it83xx/fan.c
index adb3985025..b8b805453e 100644
--- a/chip/it83xx/fan.c
+++ b/chip/it83xx/fan.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,12 +18,12 @@
 #include "task.h"
 #include "util.h"
 
-#define TACH_EC_FREQ                8000000
-#define FAN_CTRL_BASED_MS           10
-#define FAN_CTRL_INTERVAL_MAX_MS    60
+#define TACH_EC_FREQ 8000000
+#define FAN_CTRL_BASED_MS 10
+#define FAN_CTRL_INTERVAL_MAX_MS 60
 
 /* The sampling rate (fs) is FreqEC / 128 */
-#define TACH_DATA_VALID_TIMEOUT_MS  (0xFFFF * 128 / (TACH_EC_FREQ / 1000))
+#define TACH_DATA_VALID_TIMEOUT_MS (0xFFFF * 128 / (TACH_EC_FREQ / 1000))
 
 /*
  * Fan Speed (RPM) = 60 / (1/fs sec * {FnTMRR, FnTLRR} * P)
@@ -37,25 +37,25 @@
 #define TACH1_TO_RPM(pulse, raw) (raw * 120 / (pulse * 2))
 
 enum fan_output_s {
-	FAN_DUTY_I  = 0x01,
-	FAN_DUTY_R  = 0x02,
+	FAN_DUTY_I = 0x01,
+	FAN_DUTY_R = 0x02,
 	FAN_DUTY_OV = 0x03,
 	FAN_DUTY_DONE = 0x04,
 };
 
 struct fan_info {
-	unsigned int    flags;
-	int             fan_mode;
-	int             fan_p;
-	int             rpm_target;
-	int             rpm_actual;
-	int             tach_valid_ms;
-	int             rpm_re;
-	int             fan_ms;
-	int             fan_ms_idx;
-	int             startup_duty;
+	unsigned int flags;
+	int fan_mode;
+	int fan_p;
+	int rpm_target;
+	int rpm_actual;
+	int tach_valid_ms;
+	int rpm_re;
+	int fan_ms;
+	int fan_ms_idx;
+	int startup_duty;
 	enum fan_status fan_sts;
-	int             enabled;
+	int enabled;
 };
 static struct fan_info fan_info_data[TACH_CH_COUNT];
 
@@ -72,7 +72,8 @@ static void fan_set_interval(int ch)
 	tach_ch = tach_bind(ch);
 
 	diff = ABS(fan_info_data[tach_ch].rpm_target -
-		fan_info_data[tach_ch].rpm_actual) / 100;
+		   fan_info_data[tach_ch].rpm_actual) /
+	       100;
 
 	fan_ms = FAN_CTRL_INTERVAL_MAX_MS;
 
@@ -122,7 +123,7 @@ void fan_set_enabled(int ch, int enabled)
 		disable_sleep(SLEEP_MASK_FAN);
 		/* enable timer interrupt for fan control */
 		ext_timer_start(FAN_CTRL_EXT_TIMER, 1);
-	/* disable */
+		/* disable */
 	} else {
 		fan_set_duty(ch, 0);
 
@@ -245,9 +246,8 @@ enum fan_status fan_get_status(int ch)
 int fan_is_stalled(int ch)
 {
 	/* Must be enabled with non-zero target to stall */
-	if (!fan_get_enabled(ch) ||
-		fan_get_rpm_target(ch) == 0 ||
-		!fan_get_duty(ch))
+	if (!fan_get_enabled(ch) || fan_get_rpm_target(ch) == 0 ||
+	    !fan_get_duty(ch))
 		return 0;
 
 	/* Check for stall condition */
@@ -273,8 +273,7 @@ static void fan_ctrl(int ch)
 	tach_ch = tach_bind(ch);
 
 	fan_info_data[tach_ch].fan_ms_idx += FAN_CTRL_BASED_MS;
-	if (fan_info_data[tach_ch].fan_ms_idx >
-		fan_info_data[tach_ch].fan_ms) {
+	if (fan_info_data[tach_ch].fan_ms_idx > fan_info_data[tach_ch].fan_ms) {
 		fan_info_data[tach_ch].fan_ms_idx = 0x00;
 		adjust = 1;
 	}
@@ -411,7 +410,7 @@ static void proc_tach(int ch)
 	} else {
 		fan_info_data[tach_ch].tach_valid_ms += FAN_CTRL_BASED_MS;
 		if (fan_info_data[tach_ch].tach_valid_ms >
-			TACH_DATA_VALID_TIMEOUT_MS)
+		    TACH_DATA_VALID_TIMEOUT_MS)
 			fan_info_data[tach_ch].rpm_actual = 0;
 	}
 }
@@ -436,14 +435,12 @@ static void fan_init(void)
 	enum tach_ch_sel tach_ch;
 
 	for (ch = 0; ch < fan_get_count(); ch++) {
-
 		rpm_re = fan_tach[pwm_channels[FAN_CH(ch)].channel].rpm_re;
 		fan_p = fan_tach[pwm_channels[FAN_CH(ch)].channel].fan_p;
 		s_duty = fan_tach[pwm_channels[FAN_CH(ch)].channel].s_duty;
 		tach_ch = tach_bind(FAN_CH(ch));
 
 		if (tach_ch < TACH_CH_COUNT) {
-
 			if (tach_ch == TACH_CH_TACH0B) {
 				/* GPJ2 will select TACH0B as its alt. */
 				IT83XX_GPIO_GRC5 |= 0x01;
@@ -473,6 +470,6 @@ static void fan_init(void)
 
 	/* init external timer for fan control */
 	ext_timer_ms(FAN_CTRL_EXT_TIMER, EXT_PSR_32P768K_HZ, 0, 0,
-			FAN_CTRL_BASED_MS, 1, 0);
+		     FAN_CTRL_BASED_MS, 1, 0);
 }
 DECLARE_HOOK(HOOK_INIT, fan_init, HOOK_PRIO_INIT_FAN);
diff --git a/chip/it83xx/flash.c b/chip/it83xx/flash.c
index c0e062bce4..fa8ab65292 100644
--- a/chip/it83xx/flash.c
+++ b/chip/it83xx/flash.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,53 +9,53 @@
 #include "flash_chip.h"
 #include "host_command.h"
 #include "intc.h"
-#include "system.h"
-#include "util.h"
-#include "watchdog.h"
 #include "registers.h"
-#include "task.h"
 #include "shared_mem.h"
+#include "system.h"
+#include "task.h"
 #include "uart.h"
+#include "util.h"
+#include "watchdog.h"
 
-#define FLASH_DMA_START ((uint32_t) &__flash_dma_start)
+#define FLASH_DMA_START ((uint32_t)&__flash_dma_start)
 #define FLASH_DMA_CODE __attribute__((section(".flash_direct_map")))
+#define FLASH_ILM0_ADDR ((uint32_t)&__ilm0_ram_code)
 
 /* erase size of sector is 1KB or 4KB */
 #define FLASH_SECTOR_ERASE_SIZE CONFIG_FLASH_ERASE_SIZE
 
 #ifdef IT83XX_CHIP_FLASH_IS_KGD
 /* page program command  */
-#define FLASH_CMD_PAGE_WRITE    0x2
+#define FLASH_CMD_PAGE_WRITE 0x2
 /* ector erase command (erase size is 4KB) */
-#define FLASH_CMD_SECTOR_ERASE  0x20
+#define FLASH_CMD_SECTOR_ERASE 0x20
 /* command for flash write */
-#define FLASH_CMD_WRITE         FLASH_CMD_PAGE_WRITE
+#define FLASH_CMD_WRITE FLASH_CMD_PAGE_WRITE
 #else
 /* Auto address increment programming */
-#define FLASH_CMD_AAI_WORD      0xAD
+#define FLASH_CMD_AAI_WORD 0xAD
 /* Flash sector erase (1K bytes) command */
-#define FLASH_CMD_SECTOR_ERASE  0xD7
+#define FLASH_CMD_SECTOR_ERASE 0xD7
 /* command for flash write */
-#define FLASH_CMD_WRITE         FLASH_CMD_AAI_WORD
+#define FLASH_CMD_WRITE FLASH_CMD_AAI_WORD
 #endif
 /* Write status register */
-#define FLASH_CMD_WRSR         0x01
+#define FLASH_CMD_WRSR 0x01
 /* Write disable */
-#define FLASH_CMD_WRDI         0x04
+#define FLASH_CMD_WRDI 0x04
 /* Write enable */
-#define FLASH_CMD_WREN         0x06
+#define FLASH_CMD_WREN 0x06
 /* Read status register */
-#define FLASH_CMD_RS           0x05
+#define FLASH_CMD_RS 0x05
 
-#define FLASH_TEXT_START ((uint32_t) &__flash_text_start)
+#if (CONFIG_FLASH_SIZE_BYTES == 0x80000) && defined(CHIP_CORE_NDS32)
+#define FLASH_TEXT_START ((uint32_t)&__flash_text_start)
+/* Apply workaround of the issue (b:111808417) */
+#define IMMU_CACHE_TAG_INVALID
 /* The default tag index of immu. */
 #define IMMU_TAG_INDEX_BY_DEFAULT 0x7E000
 /* immu cache size is 8K bytes. */
-#define IMMU_SIZE                 0x2000
-
-#if (CONFIG_FLASH_SIZE == 0x80000) && defined(CHIP_CORE_NDS32)
-/* Apply workaround of the issue (b:111808417) */
-#define IMMU_CACHE_TAG_INVALID
+#define IMMU_SIZE 0x2000
 #endif
 
 static int stuck_locked;
@@ -88,18 +88,18 @@ enum flash_status_mask {
 };
 
 enum dlm_address_view {
-	SCAR0_ILM0_DLM13   = 0x8D000, /* DLM ~ 0x8DFFF H2RAM map LPC I/O */
-	SCAR1_ILM1_DLM11   = 0x8B000, /* DLM ~ 0x8BFFF ram 44K ~ 48K */
-	SCAR2_ILM2_DLM14   = 0x8E000, /* DLM ~ 0x8EFFF RO/RW flash code DMA */
-	SCAR3_ILM3_DLM6    = 0x86000, /* DLM ~ 0x86FFF ram 24K ~ 28K */
-	SCAR4_ILM4_DLM7    = 0x87000, /* DLM ~ 0x87FFF ram 28K ~ 32K */
-	SCAR5_ILM5_DLM8    = 0x88000, /* DLM ~ 0x88FFF ram 32K ~ 36K */
-	SCAR6_ILM6_DLM9    = 0x89000, /* DLM ~ 0x89FFF ram 36K ~ 40K */
-	SCAR7_ILM7_DLM10   = 0x8A000, /* DLM ~ 0x8AFFF ram 40K ~ 44K */
-	SCAR8_ILM8_DLM4    = 0x84000, /* DLM ~ 0x84FFF ram 16K ~ 20K */
-	SCAR9_ILM9_DLM5    = 0x85000, /* DLM ~ 0x85FFF ram 20K ~ 24K */
-	SCAR10_ILM10_DLM2  = 0x82000, /* DLM ~ 0x82FFF ram 8K ~ 12K */
-	SCAR11_ILM11_DLM3  = 0x83000, /* DLM ~ 0x83FFF ram 12K ~ 16K */
+	SCAR0_ILM0_DLM13 = 0x8D000, /* DLM ~ 0x8DFFF H2RAM map LPC I/O */
+	SCAR1_ILM1_DLM11 = 0x8B000, /* DLM ~ 0x8BFFF ram 44K ~ 48K */
+	SCAR2_ILM2_DLM14 = 0x8E000, /* DLM ~ 0x8EFFF RO/RW flash code DMA */
+	SCAR3_ILM3_DLM6 = 0x86000, /* DLM ~ 0x86FFF ram 24K ~ 28K */
+	SCAR4_ILM4_DLM7 = 0x87000, /* DLM ~ 0x87FFF ram 28K ~ 32K */
+	SCAR5_ILM5_DLM8 = 0x88000, /* DLM ~ 0x88FFF ram 32K ~ 36K */
+	SCAR6_ILM6_DLM9 = 0x89000, /* DLM ~ 0x89FFF ram 36K ~ 40K */
+	SCAR7_ILM7_DLM10 = 0x8A000, /* DLM ~ 0x8AFFF ram 40K ~ 44K */
+	SCAR8_ILM8_DLM4 = 0x84000, /* DLM ~ 0x84FFF ram 16K ~ 20K */
+	SCAR9_ILM9_DLM5 = 0x85000, /* DLM ~ 0x85FFF ram 20K ~ 24K */
+	SCAR10_ILM10_DLM2 = 0x82000, /* DLM ~ 0x82FFF ram 8K ~ 12K */
+	SCAR11_ILM11_DLM3 = 0x83000, /* DLM ~ 0x83FFF ram 12K ~ 16K */
 	SCAR12_ILM12_DLM12 = 0x8C000, /* DLM ~ 0x8CFFF immu cache */
 };
 
@@ -177,8 +177,8 @@ void FLASH_DMA_CODE dma_flash_write_dat(uint8_t wdata)
 	IT83XX_SMFI_ECINDDR = wdata;
 }
 
-void FLASH_DMA_CODE dma_flash_transaction(int wlen, uint8_t *wbuf,
-					int rlen, uint8_t *rbuf, int cmd_end)
+void FLASH_DMA_CODE dma_flash_transaction(int wlen, uint8_t *wbuf, int rlen,
+					  uint8_t *rbuf, int cmd_end)
 {
 	int i;
 
@@ -197,10 +197,10 @@ void FLASH_DMA_CODE dma_flash_transaction(int wlen, uint8_t *wbuf,
 }
 
 void FLASH_DMA_CODE dma_flash_cmd_read_status(enum flash_status_mask mask,
-						enum flash_status_mask target)
+					      enum flash_status_mask target)
 {
 	uint8_t status[1];
-	uint8_t cmd_rs[] = {FLASH_CMD_RS};
+	uint8_t cmd_rs[] = { FLASH_CMD_RS };
 
 	/*
 	 * We prefer no timeout here. We can always get the status
@@ -220,7 +220,7 @@ void FLASH_DMA_CODE dma_flash_cmd_read_status(enum flash_status_mask mask,
 
 void FLASH_DMA_CODE dma_flash_cmd_write_enable(void)
 {
-	uint8_t cmd_we[] = {FLASH_CMD_WREN};
+	uint8_t cmd_we[] = { FLASH_CMD_WREN };
 
 	/* enter EC-indirect follow mode */
 	dma_flash_follow_mode();
@@ -234,7 +234,7 @@ void FLASH_DMA_CODE dma_flash_cmd_write_enable(void)
 
 void FLASH_DMA_CODE dma_flash_cmd_write_disable(void)
 {
-	uint8_t cmd_wd[] = {FLASH_CMD_WRDI};
+	uint8_t cmd_wd[] = { FLASH_CMD_WRDI };
 
 	/* enter EC-indirect follow mode */
 	dma_flash_follow_mode();
@@ -248,8 +248,8 @@ void FLASH_DMA_CODE dma_flash_cmd_write_disable(void)
 
 void FLASH_DMA_CODE dma_flash_cmd_erase(int addr, int cmd)
 {
-	uint8_t cmd_erase[] = {cmd, ((addr >> 16) & 0xFF),
-				((addr >> 8) & 0xFF), (addr & 0xFF)};
+	uint8_t cmd_erase[] = { cmd, ((addr >> 16) & 0xFF),
+				((addr >> 8) & 0xFF), (addr & 0xFF) };
 
 	/* enter EC-indirect follow mode */
 	dma_flash_follow_mode();
@@ -264,8 +264,8 @@ void FLASH_DMA_CODE dma_flash_cmd_erase(int addr, int cmd)
 void FLASH_DMA_CODE dma_flash_cmd_write(int addr, int wlen, uint8_t *wbuf)
 {
 	int i;
-	uint8_t flash_write[] = {FLASH_CMD_WRITE, ((addr >> 16) & 0xFF),
-				((addr >> 8) & 0xFF), (addr & 0xFF)};
+	uint8_t flash_write[] = { FLASH_CMD_WRITE, ((addr >> 16) & 0xFF),
+				  ((addr >> 8) & 0xFF), (addr & 0xFF) };
 
 	/* enter EC-indirect follow mode */
 	dma_flash_follow_mode();
@@ -281,12 +281,12 @@ void FLASH_DMA_CODE dma_flash_cmd_write(int addr, int wlen, uint8_t *wbuf)
 		 * chunk worth of data.
 		 */
 		if (!(++addr % CONFIG_FLASH_WRITE_IDEAL_SIZE)) {
-			uint8_t w_en[] = {FLASH_CMD_WREN};
+			uint8_t w_en[] = { FLASH_CMD_WREN };
 
 			dma_flash_fsce_high();
 			/* make sure busy bit cleared. */
 			dma_flash_cmd_read_status(FLASH_SR_BUSY,
-							FLASH_SR_NO_BUSY);
+						  FLASH_SR_NO_BUSY);
 			/* send write enable command */
 			dma_flash_transaction(sizeof(w_en), w_en, 0, NULL, 1);
 			/* make sure busy bit cleared and write enabled. */
@@ -296,7 +296,7 @@ void FLASH_DMA_CODE dma_flash_cmd_write(int addr, int wlen, uint8_t *wbuf)
 			flash_write[2] = (addr >> 8) & 0xff;
 			flash_write[3] = addr & 0xff;
 			dma_flash_transaction(sizeof(flash_write), flash_write,
-				0, NULL, 0);
+					      0, NULL, 0);
 		}
 	}
 	dma_flash_fsce_high();
@@ -340,7 +340,7 @@ int FLASH_DMA_CODE dma_flash_verify(int addr, int size, const char *data)
 			if (flash[i] != 0xFF)
 				return EC_ERROR_UNKNOWN;
 		}
-	/* verify for write */
+		/* verify for write */
 	} else {
 		for (i = 0; i < size; i++) {
 			if (flash[i] != wbuf[i])
@@ -370,7 +370,7 @@ static enum flash_wp_status flash_check_wp(void)
 	enum flash_wp_status wp_status;
 	int all_bank_count, bank;
 
-	all_bank_count = CONFIG_FLASH_SIZE / CONFIG_FLASH_BANK_SIZE;
+	all_bank_count = CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE;
 
 	for (bank = 0; bank < all_bank_count; bank++) {
 		if (!(IT83XX_GCTRL_EWPR0PFEC(FWP_REG(bank)) & FWP_MASK(bank)))
@@ -395,8 +395,7 @@ static enum flash_wp_status flash_check_wp(void)
  * @param start_bank    Start bank to protect
  * @param bank_count    Number of banks to protect
  */
-static void flash_protect_banks(int start_bank,
-				int bank_count,
+static void flash_protect_banks(int start_bank, int bank_count,
 				enum flash_wp_interface wp_if)
 {
 	int bank;
@@ -411,7 +410,7 @@ static void flash_protect_banks(int start_bank,
 	}
 }
 
-int FLASH_DMA_CODE flash_physical_read(int offset, int size, char *data)
+int FLASH_DMA_CODE crec_flash_physical_read(int offset, int size, char *data)
 {
 	int i;
 
@@ -432,7 +431,8 @@ int FLASH_DMA_CODE flash_physical_read(int offset, int size, char *data)
  * @param size          Number of bytes to write.
  * @param data          Data to write to flash.  Must be 32-bit aligned.
  */
-int FLASH_DMA_CODE flash_physical_write(int offset, int size, const char *data)
+int FLASH_DMA_CODE crec_flash_physical_write(int offset, int size,
+					     const char *data)
 {
 	int ret = EC_ERROR_UNKNOWN;
 
@@ -452,7 +452,11 @@ int FLASH_DMA_CODE flash_physical_write(int offset, int size, const char *data)
 	interrupt_disable();
 
 	dma_flash_write(offset, size, data);
+#ifdef IMMU_CACHE_TAG_INVALID
 	dma_reset_immu((offset + size) >= IMMU_TAG_INDEX_BY_DEFAULT);
+#else
+	dma_reset_immu(0);
+#endif
 	/*
 	 * Internal flash of N8 or RISC-V core is ILM(Instruction Local Memory)
 	 * mapped, but RISC-V's ILM base address is 0x80000000.
@@ -475,7 +479,7 @@ int FLASH_DMA_CODE flash_physical_write(int offset, int size, const char *data)
  * @param offset        Flash offset to erase.
  * @param size          Number of bytes to erase.
  */
-int FLASH_DMA_CODE flash_physical_erase(int offset, int size)
+int FLASH_DMA_CODE crec_flash_physical_erase(int offset, int size)
 {
 	int v_size = size, v_addr = offset, ret = EC_ERROR_UNKNOWN;
 
@@ -496,8 +500,29 @@ int FLASH_DMA_CODE flash_physical_erase(int offset, int size)
 	for (; size > 0; size -= FLASH_SECTOR_ERASE_SIZE) {
 		dma_flash_erase(offset, FLASH_CMD_SECTOR_ERASE);
 		offset += FLASH_SECTOR_ERASE_SIZE;
+		/*
+		 * If requested erase size is too large at one time on KGD
+		 * flash, we need to reload watchdog to prevent the reset.
+		 */
+		if (IS_ENABLED(IT83XX_CHIP_FLASH_IS_KGD) && (size > 0x10000))
+			watchdog_reload();
+			/*
+			 * EC still need to handle AP's EC_CMD_GET_COMMS_STATUS
+			 * command during erasing.
+			 */
+#ifdef IT83XX_IRQ_SPI_PERIPHERAL
+		if (IS_ENABLED(CONFIG_SPI) && IS_ENABLED(HAS_TASK_HOSTCMD) &&
+		    IS_ENABLED(CONFIG_HOST_COMMAND_STATUS)) {
+			if (IT83XX_SPI_RX_VLISR & IT83XX_SPI_RVLI)
+				task_trigger_irq(IT83XX_IRQ_SPI_PERIPHERAL);
+		}
+#endif
 	}
+#ifdef IMMU_CACHE_TAG_INVALID
 	dma_reset_immu((v_addr + v_size) >= IMMU_TAG_INDEX_BY_DEFAULT);
+#else
+	dma_reset_immu(0);
+#endif
 	/* get the ILM address of a flash offset. */
 	v_addr |= CONFIG_MAPPED_STORAGE_BASE;
 	ret = dma_flash_verify(v_addr, v_size, NULL);
@@ -513,7 +538,7 @@ int FLASH_DMA_CODE flash_physical_erase(int offset, int size)
  * @param bank    Bank index to check.
  * @return        non-zero if bank is protected until reboot.
  */
-int flash_physical_get_protect(int bank)
+int crec_flash_physical_get_protect(int bank)
 {
 	return IT83XX_GCTRL_EWPR0PFEC(FWP_REG(bank)) & FWP_MASK(bank);
 }
@@ -524,21 +549,20 @@ int flash_physical_get_protect(int bank)
  * @param all      Protect all (=1) or just read-only and pstate (=0).
  * @return         non-zero if error.
  */
-int flash_physical_protect_now(int all)
+int crec_flash_physical_protect_now(int all)
 {
 	if (all) {
 		/* Protect the entire flash */
-		flash_protect_banks(0,
-			CONFIG_FLASH_SIZE / CONFIG_FLASH_BANK_SIZE,
+		flash_protect_banks(
+			0, CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE,
 			FLASH_WP_EC);
 		all_protected = 1;
 	} else {
 		/* Protect the read-only section and persistent state */
-		flash_protect_banks(WP_BANK_OFFSET,
-			WP_BANK_COUNT, FLASH_WP_EC);
+		flash_protect_banks(WP_BANK_OFFSET, WP_BANK_COUNT, FLASH_WP_EC);
 #ifdef PSTATE_BANK
-		flash_protect_banks(PSTATE_BANK,
-			PSTATE_BANK_COUNT, FLASH_WP_EC);
+		flash_protect_banks(PSTATE_BANK, PSTATE_BANK_COUNT,
+				    FLASH_WP_EC);
 #endif
 	}
 
@@ -558,7 +582,7 @@ int flash_physical_protect_now(int all)
  *
  * Uses the EC_FLASH_PROTECT_* flags from ec_commands.h
  */
-uint32_t flash_physical_get_protect_flags(void)
+uint32_t crec_flash_physical_get_protect_flags(void)
 {
 	uint32_t flags = 0;
 
@@ -583,10 +607,9 @@ uint32_t flash_physical_get_protect_flags(void)
  *
  * @return   A combination of EC_FLASH_PROTECT_* flags from ec_commands.h
  */
-uint32_t flash_physical_get_valid_flags(void)
+uint32_t crec_flash_physical_get_valid_flags(void)
 {
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-	       EC_FLASH_PROTECT_RO_NOW |
+	return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW |
 	       EC_FLASH_PROTECT_ALL_NOW;
 }
 
@@ -596,7 +619,7 @@ uint32_t flash_physical_get_valid_flags(void)
  * @param    cur_flags The current flash protect flags.
  * @return   A combination of EC_FLASH_PROTECT_* flags from ec_commands.h
  */
-uint32_t flash_physical_get_writable_flags(uint32_t cur_flags)
+uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
 {
 	uint32_t ret = 0;
 
@@ -615,9 +638,38 @@ uint32_t flash_physical_get_writable_flags(uint32_t cur_flags)
 	return ret;
 }
 
-static void flash_code_static_dma(void)
+static void flash_enable_second_ilm(void)
 {
+#ifdef CHIP_CORE_RISCV
+	/* Make sure no interrupt while enable static cache */
+	interrupt_disable();
+
+	/* Invalid ILM0 */
+	IT83XX_GCTRL_RVILMCR0 &= ~ILMCR_ILM0_ENABLE;
+	IT83XX_SMFI_SCAR0H = BIT(3);
+	/* copy code to ram */
+	memcpy((void *)CHIP_RAMCODE_ILM0, (const void *)FLASH_ILM0_ADDR,
+	       IT83XX_ILM_BLOCK_SIZE);
+	/*
+	 * Set the logic memory address(flash code of RO/RW) in flash
+	 * by programming the register SCAR0x bit19-bit0.
+	 */
+	IT83XX_SMFI_SCAR0L = FLASH_ILM0_ADDR & GENMASK(7, 0);
+	IT83XX_SMFI_SCAR0M = (FLASH_ILM0_ADDR >> 8) & GENMASK(7, 0);
+	IT83XX_SMFI_SCAR0H = (FLASH_ILM0_ADDR >> 16) & GENMASK(2, 0);
+	if (FLASH_ILM0_ADDR & BIT(19))
+		IT83XX_SMFI_SCAR0H |= BIT(7);
+	else
+		IT83XX_SMFI_SCAR0H &= ~BIT(7);
+	/* Enable ILM 0 */
+	IT83XX_GCTRL_RVILMCR0 |= ILMCR_ILM0_ENABLE;
+
+	interrupt_enable();
+#endif
+}
 
+static void flash_code_static_dma(void)
+{
 	/* Make sure no interrupt while enable static DMA */
 	interrupt_disable();
 
@@ -630,7 +682,7 @@ static void flash_code_static_dma(void)
 	if (IS_ENABLED(CHIP_CORE_NDS32))
 		IT83XX_GCTRL_MCCR2 |= IT83XX_DLM14_ENABLE;
 	memcpy((void *)CHIP_RAMCODE_BASE, (const void *)FLASH_DMA_START,
-		IT83XX_ILM_BLOCK_SIZE);
+	       IT83XX_ILM_BLOCK_SIZE);
 	if (IS_ENABLED(CHIP_CORE_RISCV))
 		IT83XX_GCTRL_RVILMCR0 |= ILMCR_ILM2_ENABLE;
 	/* Disable DLM 56k~60k region and be the ram code section */
@@ -669,7 +721,7 @@ static void flash_code_static_dma(void)
  *
  * Applies at-boot protection settings if necessary.
  */
-int flash_pre_init(void)
+int crec_flash_pre_init(void)
 {
 	int32_t reset_flags, prot_flags, unwanted_prot_flags;
 
@@ -678,11 +730,16 @@ int flash_pre_init(void)
 	if (IS_ENABLED(IT83XX_CHIP_FLASH_IS_KGD))
 		IT83XX_SMFI_FLHCTRL6R |= IT83XX_SMFI_MASK_ECINDPP;
 	flash_code_static_dma();
+	/*
+	 * Enable second ilm (ILM0 of it8xxx2 series), so we can pull more code
+	 * (4kB) into static cache to save latency of fetching code from flash.
+	 */
+	flash_enable_second_ilm();
 
 	reset_flags = system_get_reset_flags();
-	prot_flags = flash_get_protect();
+	prot_flags = crec_flash_get_protect();
 	unwanted_prot_flags = EC_FLASH_PROTECT_ALL_NOW |
-		EC_FLASH_PROTECT_ERROR_INCONSISTENT;
+			      EC_FLASH_PROTECT_ERROR_INCONSISTENT;
 
 	/*
 	 * If we have already jumped between images, an earlier image could
@@ -693,12 +750,12 @@ int flash_pre_init(void)
 
 	if (prot_flags & EC_FLASH_PROTECT_GPIO_ASSERTED) {
 		/* Protect the entire flash of host interface */
-		flash_protect_banks(0,
-			CONFIG_FLASH_SIZE / CONFIG_FLASH_BANK_SIZE,
+		flash_protect_banks(
+			0, CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE,
 			FLASH_WP_HOST);
 		/* Protect the entire flash of DBGR interface */
-		flash_protect_banks(0,
-			CONFIG_FLASH_SIZE / CONFIG_FLASH_BANK_SIZE,
+		flash_protect_banks(
+			0, CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE,
 			FLASH_WP_DBGR);
 		/*
 		 * Write protect is asserted.  If we want RO flash protected,
@@ -706,13 +763,14 @@ int flash_pre_init(void)
 		 */
 		if ((prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT) &&
 		    !(prot_flags & EC_FLASH_PROTECT_RO_NOW)) {
-			int rv = flash_set_protect(EC_FLASH_PROTECT_RO_NOW,
-						   EC_FLASH_PROTECT_RO_NOW);
+			int rv =
+				crec_flash_set_protect(EC_FLASH_PROTECT_RO_NOW,
+						       EC_FLASH_PROTECT_RO_NOW);
 			if (rv)
 				return rv;
 
 			/* Re-read flags */
-			prot_flags = flash_get_protect();
+			prot_flags = crec_flash_get_protect();
 		}
 	} else {
 		/* Don't want RO flash protected */
diff --git a/chip/it83xx/flash_chip.h b/chip/it83xx/flash_chip.h
index 4a604ed7f7..c1cb44bdf2 100644
--- a/chip/it83xx/flash_chip.h
+++ b/chip/it83xx/flash_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,6 +13,9 @@
  */
 extern const char __flash_dma_start;
 
+/* This symbol is the begin address of the __ilm0_ram_code section. */
+extern const char __ilm0_ram_code;
+
 /* This symbol is the begin address of the text section. */
 extern const char __flash_text_start;
 
diff --git a/chip/it83xx/gpio.c b/chip/it83xx/gpio.c
index 3dd6d16268..2b1b8283be 100644
--- a/chip/it83xx/gpio.c
+++ b/chip/it83xx/gpio.c
@@ -1,10 +1,11 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* GPIO module for Chrome EC */
 
+#include "builtin/assert.h"
 #include "clock.h"
 #include "common.h"
 #include "gpio.h"
@@ -19,6 +20,23 @@
 #include "timer.h"
 #include "util.h"
 
+/* Data structure to define KSI/KSO GPIO mode control registers. */
+struct kbs_gpio_ctrl_t {
+	/* GPIO mode control register. */
+	volatile uint8_t *gpio_mode;
+	/* GPIO output enable register. */
+	volatile uint8_t *gpio_out;
+};
+
+static const struct kbs_gpio_ctrl_t kbs_gpio_ctrl_regs[] = {
+	/* KSI pins 7:0 */
+	{ &IT83XX_KBS_KSIGCTRL, &IT83XX_KBS_KSIGOEN },
+	/* KSO pins 15:8 */
+	{ &IT83XX_KBS_KSOHGCTRL, &IT83XX_KBS_KSOHGOEN },
+	/* KSO pins 7:0 */
+	{ &IT83XX_KBS_KSOLGCTRL, &IT83XX_KBS_KSOLGOEN },
+};
+
 /**
  * Convert wake-up controller (WUC) group to the corresponding wake-up edge
  * sense register (WUESR). Return pointer to the register.
@@ -34,8 +52,8 @@ static volatile uint8_t *wuesr(uint8_t grp)
 	 * the address increases by fours.
 	 */
 	return (grp <= 4) ?
-			(volatile uint8_t *)(IT83XX_WUC_WUESR1 + grp-1) :
-			(volatile uint8_t *)(IT83XX_WUC_WUESR5 + 4*(grp-5));
+		       (volatile uint8_t *)(IT83XX_WUC_WUESR1 + grp - 1) :
+		       (volatile uint8_t *)(IT83XX_WUC_WUESR5 + 4 * (grp - 5));
 }
 
 /**
@@ -53,8 +71,8 @@ static volatile uint8_t *wuemr(uint8_t grp)
 	 * the address increases by fours.
 	 */
 	return (grp <= 4) ?
-			(volatile uint8_t *)(IT83XX_WUC_WUEMR1 + grp-1) :
-			(volatile uint8_t *)(IT83XX_WUC_WUEMR5 + 4*(grp-5));
+		       (volatile uint8_t *)(IT83XX_WUC_WUEMR1 + grp - 1) :
+		       (volatile uint8_t *)(IT83XX_WUC_WUEMR5 + 4 * (grp - 5));
 }
 
 /**
@@ -73,8 +91,8 @@ static volatile uint8_t *wubemr(uint8_t grp)
 	 * the address increases by fours.
 	 */
 	return (grp <= 4) ?
-			(volatile uint8_t *)(IT83XX_WUC_WUBEMR1 + grp-1) :
-			(volatile uint8_t *)(IT83XX_WUC_WUBEMR5 + 4*(grp-5));
+		       (volatile uint8_t *)(IT83XX_WUC_WUBEMR1 + grp - 1) :
+		       (volatile uint8_t *)(IT83XX_WUC_WUBEMR5 + 4 * (grp - 5));
 }
 #endif
 
@@ -95,140 +113,140 @@ static const struct {
 	uint8_t wuc_mask;
 } gpio_irqs[] = {
 	/*     irq           gpio_port,gpio_mask,wuc_group,wuc_mask */
-	[IT83XX_IRQ_WKO20] =    {GPIO_D, BIT(0),        2, BIT(0)},
-	[IT83XX_IRQ_WKO21] =    {GPIO_D, BIT(1),        2, BIT(1)},
-	[IT83XX_IRQ_WKO22] =    {GPIO_C, BIT(4),        2, BIT(2)},
-	[IT83XX_IRQ_WKO23] =    {GPIO_C, BIT(6),        2, BIT(3)},
-	[IT83XX_IRQ_WKO24] =    {GPIO_D, BIT(2),        2, BIT(4)},
+	[IT83XX_IRQ_WKO20] = { GPIO_D, BIT(0), 2, BIT(0) },
+	[IT83XX_IRQ_WKO21] = { GPIO_D, BIT(1), 2, BIT(1) },
+	[IT83XX_IRQ_WKO22] = { GPIO_C, BIT(4), 2, BIT(2) },
+	[IT83XX_IRQ_WKO23] = { GPIO_C, BIT(6), 2, BIT(3) },
+	[IT83XX_IRQ_WKO24] = { GPIO_D, BIT(2), 2, BIT(4) },
 #ifdef IT83XX_GPIO_INT_FLEXIBLE
-	[IT83XX_IRQ_WKO40] =    {GPIO_E, BIT(5),        4, BIT(0)},
-	[IT83XX_IRQ_WKO45] =    {GPIO_E, BIT(6),        4, BIT(5)},
-	[IT83XX_IRQ_WKO46] =    {GPIO_E, BIT(7),        4, BIT(6)},
+	[IT83XX_IRQ_WKO40] = { GPIO_E, BIT(5), 4, BIT(0) },
+	[IT83XX_IRQ_WKO45] = { GPIO_E, BIT(6), 4, BIT(5) },
+	[IT83XX_IRQ_WKO46] = { GPIO_E, BIT(7), 4, BIT(6) },
 #endif
-	[IT83XX_IRQ_WKO50] =    {GPIO_K, BIT(0),        5, BIT(0)},
-	[IT83XX_IRQ_WKO51] =    {GPIO_K, BIT(1),        5, BIT(1)},
-	[IT83XX_IRQ_WKO52] =    {GPIO_K, BIT(2),        5, BIT(2)},
-	[IT83XX_IRQ_WKO53] =    {GPIO_K, BIT(3),        5, BIT(3)},
-	[IT83XX_IRQ_WKO54] =    {GPIO_K, BIT(4),        5, BIT(4)},
-	[IT83XX_IRQ_WKO55] =    {GPIO_K, BIT(5),        5, BIT(5)},
-	[IT83XX_IRQ_WKO56] =    {GPIO_K, BIT(6),        5, BIT(6)},
-	[IT83XX_IRQ_WKO57] =    {GPIO_K, BIT(7),        5, BIT(7)},
-	[IT83XX_IRQ_WKO60] =    {GPIO_H, BIT(0),        6, BIT(0)},
-	[IT83XX_IRQ_WKO61] =    {GPIO_H, BIT(1),        6, BIT(1)},
-	[IT83XX_IRQ_WKO62] =    {GPIO_H, BIT(2),        6, BIT(2)},
-	[IT83XX_IRQ_WKO63] =    {GPIO_H, BIT(3),        6, BIT(3)},
-	[IT83XX_IRQ_WKO64] =    {GPIO_F, BIT(4),        6, BIT(4)},
-	[IT83XX_IRQ_WKO65] =    {GPIO_F, BIT(5),        6, BIT(5)},
-	[IT83XX_IRQ_WKO65] =    {GPIO_F, BIT(6),        6, BIT(6)},
-	[IT83XX_IRQ_WKO67] =    {GPIO_F, BIT(7),        6, BIT(7)},
-	[IT83XX_IRQ_WKO70] =    {GPIO_E, BIT(0),        7, BIT(0)},
-	[IT83XX_IRQ_WKO71] =    {GPIO_E, BIT(1),        7, BIT(1)},
-	[IT83XX_IRQ_WKO72] =    {GPIO_E, BIT(2),        7, BIT(2)},
-	[IT83XX_IRQ_WKO73] =    {GPIO_E, BIT(3),        7, BIT(3)},
-	[IT83XX_IRQ_WKO74] =    {GPIO_I, BIT(4),        7, BIT(4)},
-	[IT83XX_IRQ_WKO75] =    {GPIO_I, BIT(5),        7, BIT(5)},
-	[IT83XX_IRQ_WKO76] =    {GPIO_I, BIT(6),        7, BIT(6)},
-	[IT83XX_IRQ_WKO77] =    {GPIO_I, BIT(7),        7, BIT(7)},
-	[IT83XX_IRQ_WKO80] =    {GPIO_A, BIT(3),        8, BIT(0)},
-	[IT83XX_IRQ_WKO81] =    {GPIO_A, BIT(4),        8, BIT(1)},
-	[IT83XX_IRQ_WKO82] =    {GPIO_A, BIT(5),        8, BIT(2)},
-	[IT83XX_IRQ_WKO83] =    {GPIO_A, BIT(6),        8, BIT(3)},
-	[IT83XX_IRQ_WKO84] =    {GPIO_B, BIT(2),        8, BIT(4)},
-	[IT83XX_IRQ_WKO85] =    {GPIO_C, BIT(0),        8, BIT(5)},
-	[IT83XX_IRQ_WKO86] =    {GPIO_C, BIT(7),        8, BIT(6)},
-	[IT83XX_IRQ_WKO87] =    {GPIO_D, BIT(7),        8, BIT(7)},
-	[IT83XX_IRQ_WKO88] =    {GPIO_H, BIT(4),        9, BIT(0)},
-	[IT83XX_IRQ_WKO89] =    {GPIO_H, BIT(5),        9, BIT(1)},
-	[IT83XX_IRQ_WKO90] =    {GPIO_H, BIT(6),        9, BIT(2)},
-	[IT83XX_IRQ_WKO91] =    {GPIO_A, BIT(0),        9, BIT(3)},
-	[IT83XX_IRQ_WKO92] =    {GPIO_A, BIT(1),        9, BIT(4)},
-	[IT83XX_IRQ_WKO93] =    {GPIO_A, BIT(2),        9, BIT(5)},
-	[IT83XX_IRQ_WKO94] =    {GPIO_B, BIT(4),        9, BIT(6)},
-	[IT83XX_IRQ_WKO95] =    {GPIO_C, BIT(2),        9, BIT(7)},
-	[IT83XX_IRQ_WKO96] =    {GPIO_F, BIT(0),        10, BIT(0)},
-	[IT83XX_IRQ_WKO97] =    {GPIO_F, BIT(1),        10, BIT(1)},
-	[IT83XX_IRQ_WKO98] =    {GPIO_F, BIT(2),        10, BIT(2)},
-	[IT83XX_IRQ_WKO99] =    {GPIO_F, BIT(3),        10, BIT(3)},
-	[IT83XX_IRQ_WKO100] =   {GPIO_A, BIT(7),        10, BIT(4)},
-	[IT83XX_IRQ_WKO101] =   {GPIO_B, BIT(0),        10, BIT(5)},
-	[IT83XX_IRQ_WKO102] =   {GPIO_B, BIT(1),        10, BIT(6)},
-	[IT83XX_IRQ_WKO103] =   {GPIO_B, BIT(3),        10, BIT(7)},
-	[IT83XX_IRQ_WKO104] =   {GPIO_B, BIT(5),        11, BIT(0)},
-	[IT83XX_IRQ_WKO105] =   {GPIO_B, BIT(6),        11, BIT(1)},
-	[IT83XX_IRQ_WKO106] =   {GPIO_B, BIT(7),        11, BIT(2)},
-	[IT83XX_IRQ_WKO107] =   {GPIO_C, BIT(1),        11, BIT(3)},
-	[IT83XX_IRQ_WKO108] =   {GPIO_C, BIT(3),        11, BIT(4)},
-	[IT83XX_IRQ_WKO109] =   {GPIO_C, BIT(5),        11, BIT(5)},
-	[IT83XX_IRQ_WKO110] =   {GPIO_D, BIT(3),        11, BIT(6)},
-	[IT83XX_IRQ_WKO111] =   {GPIO_D, BIT(4),        11, BIT(7)},
-	[IT83XX_IRQ_WKO112] =   {GPIO_D, BIT(5),        12, BIT(0)},
-	[IT83XX_IRQ_WKO113] =   {GPIO_D, BIT(6),        12, BIT(1)},
-	[IT83XX_IRQ_WKO114] =   {GPIO_E, BIT(4),        12, BIT(2)},
-	[IT83XX_IRQ_WKO115] =   {GPIO_G, BIT(0),        12, BIT(3)},
-	[IT83XX_IRQ_WKO116] =   {GPIO_G, BIT(1),        12, BIT(4)},
-	[IT83XX_IRQ_WKO117] =   {GPIO_G, BIT(2),        12, BIT(5)},
-	[IT83XX_IRQ_WKO118] =   {GPIO_G, BIT(6),        12, BIT(6)},
-	[IT83XX_IRQ_WKO119] =   {GPIO_I, BIT(0),        12, BIT(7)},
-	[IT83XX_IRQ_WKO120] =   {GPIO_I, BIT(1),        13, BIT(0)},
-	[IT83XX_IRQ_WKO121] =   {GPIO_I, BIT(2),        13, BIT(1)},
-	[IT83XX_IRQ_WKO122] =   {GPIO_I, BIT(3),        13, BIT(2)},
+	[IT83XX_IRQ_WKO50] = { GPIO_K, BIT(0), 5, BIT(0) },
+	[IT83XX_IRQ_WKO51] = { GPIO_K, BIT(1), 5, BIT(1) },
+	[IT83XX_IRQ_WKO52] = { GPIO_K, BIT(2), 5, BIT(2) },
+	[IT83XX_IRQ_WKO53] = { GPIO_K, BIT(3), 5, BIT(3) },
+	[IT83XX_IRQ_WKO54] = { GPIO_K, BIT(4), 5, BIT(4) },
+	[IT83XX_IRQ_WKO55] = { GPIO_K, BIT(5), 5, BIT(5) },
+	[IT83XX_IRQ_WKO56] = { GPIO_K, BIT(6), 5, BIT(6) },
+	[IT83XX_IRQ_WKO57] = { GPIO_K, BIT(7), 5, BIT(7) },
+	[IT83XX_IRQ_WKO60] = { GPIO_H, BIT(0), 6, BIT(0) },
+	[IT83XX_IRQ_WKO61] = { GPIO_H, BIT(1), 6, BIT(1) },
+	[IT83XX_IRQ_WKO62] = { GPIO_H, BIT(2), 6, BIT(2) },
+	[IT83XX_IRQ_WKO63] = { GPIO_H, BIT(3), 6, BIT(3) },
+	[IT83XX_IRQ_WKO64] = { GPIO_F, BIT(4), 6, BIT(4) },
+	[IT83XX_IRQ_WKO65] = { GPIO_F, BIT(5), 6, BIT(5) },
+	[IT83XX_IRQ_WKO65] = { GPIO_F, BIT(6), 6, BIT(6) },
+	[IT83XX_IRQ_WKO67] = { GPIO_F, BIT(7), 6, BIT(7) },
+	[IT83XX_IRQ_WKO70] = { GPIO_E, BIT(0), 7, BIT(0) },
+	[IT83XX_IRQ_WKO71] = { GPIO_E, BIT(1), 7, BIT(1) },
+	[IT83XX_IRQ_WKO72] = { GPIO_E, BIT(2), 7, BIT(2) },
+	[IT83XX_IRQ_WKO73] = { GPIO_E, BIT(3), 7, BIT(3) },
+	[IT83XX_IRQ_WKO74] = { GPIO_I, BIT(4), 7, BIT(4) },
+	[IT83XX_IRQ_WKO75] = { GPIO_I, BIT(5), 7, BIT(5) },
+	[IT83XX_IRQ_WKO76] = { GPIO_I, BIT(6), 7, BIT(6) },
+	[IT83XX_IRQ_WKO77] = { GPIO_I, BIT(7), 7, BIT(7) },
+	[IT83XX_IRQ_WKO80] = { GPIO_A, BIT(3), 8, BIT(0) },
+	[IT83XX_IRQ_WKO81] = { GPIO_A, BIT(4), 8, BIT(1) },
+	[IT83XX_IRQ_WKO82] = { GPIO_A, BIT(5), 8, BIT(2) },
+	[IT83XX_IRQ_WKO83] = { GPIO_A, BIT(6), 8, BIT(3) },
+	[IT83XX_IRQ_WKO84] = { GPIO_B, BIT(2), 8, BIT(4) },
+	[IT83XX_IRQ_WKO85] = { GPIO_C, BIT(0), 8, BIT(5) },
+	[IT83XX_IRQ_WKO86] = { GPIO_C, BIT(7), 8, BIT(6) },
+	[IT83XX_IRQ_WKO87] = { GPIO_D, BIT(7), 8, BIT(7) },
+	[IT83XX_IRQ_WKO88] = { GPIO_H, BIT(4), 9, BIT(0) },
+	[IT83XX_IRQ_WKO89] = { GPIO_H, BIT(5), 9, BIT(1) },
+	[IT83XX_IRQ_WKO90] = { GPIO_H, BIT(6), 9, BIT(2) },
+	[IT83XX_IRQ_WKO91] = { GPIO_A, BIT(0), 9, BIT(3) },
+	[IT83XX_IRQ_WKO92] = { GPIO_A, BIT(1), 9, BIT(4) },
+	[IT83XX_IRQ_WKO93] = { GPIO_A, BIT(2), 9, BIT(5) },
+	[IT83XX_IRQ_WKO94] = { GPIO_B, BIT(4), 9, BIT(6) },
+	[IT83XX_IRQ_WKO95] = { GPIO_C, BIT(2), 9, BIT(7) },
+	[IT83XX_IRQ_WKO96] = { GPIO_F, BIT(0), 10, BIT(0) },
+	[IT83XX_IRQ_WKO97] = { GPIO_F, BIT(1), 10, BIT(1) },
+	[IT83XX_IRQ_WKO98] = { GPIO_F, BIT(2), 10, BIT(2) },
+	[IT83XX_IRQ_WKO99] = { GPIO_F, BIT(3), 10, BIT(3) },
+	[IT83XX_IRQ_WKO100] = { GPIO_A, BIT(7), 10, BIT(4) },
+	[IT83XX_IRQ_WKO101] = { GPIO_B, BIT(0), 10, BIT(5) },
+	[IT83XX_IRQ_WKO102] = { GPIO_B, BIT(1), 10, BIT(6) },
+	[IT83XX_IRQ_WKO103] = { GPIO_B, BIT(3), 10, BIT(7) },
+	[IT83XX_IRQ_WKO104] = { GPIO_B, BIT(5), 11, BIT(0) },
+	[IT83XX_IRQ_WKO105] = { GPIO_B, BIT(6), 11, BIT(1) },
+	[IT83XX_IRQ_WKO106] = { GPIO_B, BIT(7), 11, BIT(2) },
+	[IT83XX_IRQ_WKO107] = { GPIO_C, BIT(1), 11, BIT(3) },
+	[IT83XX_IRQ_WKO108] = { GPIO_C, BIT(3), 11, BIT(4) },
+	[IT83XX_IRQ_WKO109] = { GPIO_C, BIT(5), 11, BIT(5) },
+	[IT83XX_IRQ_WKO110] = { GPIO_D, BIT(3), 11, BIT(6) },
+	[IT83XX_IRQ_WKO111] = { GPIO_D, BIT(4), 11, BIT(7) },
+	[IT83XX_IRQ_WKO112] = { GPIO_D, BIT(5), 12, BIT(0) },
+	[IT83XX_IRQ_WKO113] = { GPIO_D, BIT(6), 12, BIT(1) },
+	[IT83XX_IRQ_WKO114] = { GPIO_E, BIT(4), 12, BIT(2) },
+	[IT83XX_IRQ_WKO115] = { GPIO_G, BIT(0), 12, BIT(3) },
+	[IT83XX_IRQ_WKO116] = { GPIO_G, BIT(1), 12, BIT(4) },
+	[IT83XX_IRQ_WKO117] = { GPIO_G, BIT(2), 12, BIT(5) },
+	[IT83XX_IRQ_WKO118] = { GPIO_G, BIT(6), 12, BIT(6) },
+	[IT83XX_IRQ_WKO119] = { GPIO_I, BIT(0), 12, BIT(7) },
+	[IT83XX_IRQ_WKO120] = { GPIO_I, BIT(1), 13, BIT(0) },
+	[IT83XX_IRQ_WKO121] = { GPIO_I, BIT(2), 13, BIT(1) },
+	[IT83XX_IRQ_WKO122] = { GPIO_I, BIT(3), 13, BIT(2) },
 #ifdef IT83XX_GPIO_INT_FLEXIBLE
-	[IT83XX_IRQ_WKO123] =   {GPIO_G, BIT(3),        13, BIT(3)},
-	[IT83XX_IRQ_WKO124] =   {GPIO_G, BIT(4),        13, BIT(4)},
-	[IT83XX_IRQ_WKO125] =   {GPIO_G, BIT(5),        13, BIT(5)},
-	[IT83XX_IRQ_WKO126] =   {GPIO_G, BIT(7),        13, BIT(6)},
+	[IT83XX_IRQ_WKO123] = { GPIO_G, BIT(3), 13, BIT(3) },
+	[IT83XX_IRQ_WKO124] = { GPIO_G, BIT(4), 13, BIT(4) },
+	[IT83XX_IRQ_WKO125] = { GPIO_G, BIT(5), 13, BIT(5) },
+	[IT83XX_IRQ_WKO126] = { GPIO_G, BIT(7), 13, BIT(6) },
 #endif
-	[IT83XX_IRQ_WKO128] =   {GPIO_J, BIT(0),        14, BIT(0)},
-	[IT83XX_IRQ_WKO129] =   {GPIO_J, BIT(1),        14, BIT(1)},
-	[IT83XX_IRQ_WKO130] =   {GPIO_J, BIT(2),        14, BIT(2)},
-	[IT83XX_IRQ_WKO131] =   {GPIO_J, BIT(3),        14, BIT(3)},
-	[IT83XX_IRQ_WKO132] =   {GPIO_J, BIT(4),        14, BIT(4)},
-	[IT83XX_IRQ_WKO133] =   {GPIO_J, BIT(5),        14, BIT(5)},
-	[IT83XX_IRQ_WKO134] =   {GPIO_J, BIT(6),        14, BIT(6)},
-	[IT83XX_IRQ_WKO135] =   {GPIO_J, BIT(7),        14, BIT(7)},
-	[IT83XX_IRQ_WKO136] =   {GPIO_L, BIT(0),        15, BIT(0)},
-	[IT83XX_IRQ_WKO137] =   {GPIO_L, BIT(1),        15, BIT(1)},
-	[IT83XX_IRQ_WKO138] =   {GPIO_L, BIT(2),        15, BIT(2)},
-	[IT83XX_IRQ_WKO139] =   {GPIO_L, BIT(3),        15, BIT(3)},
-	[IT83XX_IRQ_WKO140] =   {GPIO_L, BIT(4),        15, BIT(4)},
-	[IT83XX_IRQ_WKO141] =   {GPIO_L, BIT(5),        15, BIT(5)},
-	[IT83XX_IRQ_WKO142] =   {GPIO_L, BIT(6),        15, BIT(6)},
-	[IT83XX_IRQ_WKO143] =   {GPIO_L, BIT(7),        15, BIT(7)},
+	[IT83XX_IRQ_WKO128] = { GPIO_J, BIT(0), 14, BIT(0) },
+	[IT83XX_IRQ_WKO129] = { GPIO_J, BIT(1), 14, BIT(1) },
+	[IT83XX_IRQ_WKO130] = { GPIO_J, BIT(2), 14, BIT(2) },
+	[IT83XX_IRQ_WKO131] = { GPIO_J, BIT(3), 14, BIT(3) },
+	[IT83XX_IRQ_WKO132] = { GPIO_J, BIT(4), 14, BIT(4) },
+	[IT83XX_IRQ_WKO133] = { GPIO_J, BIT(5), 14, BIT(5) },
+	[IT83XX_IRQ_WKO134] = { GPIO_J, BIT(6), 14, BIT(6) },
+	[IT83XX_IRQ_WKO135] = { GPIO_J, BIT(7), 14, BIT(7) },
+	[IT83XX_IRQ_WKO136] = { GPIO_L, BIT(0), 15, BIT(0) },
+	[IT83XX_IRQ_WKO137] = { GPIO_L, BIT(1), 15, BIT(1) },
+	[IT83XX_IRQ_WKO138] = { GPIO_L, BIT(2), 15, BIT(2) },
+	[IT83XX_IRQ_WKO139] = { GPIO_L, BIT(3), 15, BIT(3) },
+	[IT83XX_IRQ_WKO140] = { GPIO_L, BIT(4), 15, BIT(4) },
+	[IT83XX_IRQ_WKO141] = { GPIO_L, BIT(5), 15, BIT(5) },
+	[IT83XX_IRQ_WKO142] = { GPIO_L, BIT(6), 15, BIT(6) },
+	[IT83XX_IRQ_WKO143] = { GPIO_L, BIT(7), 15, BIT(7) },
 #ifdef IT83XX_GPIO_INT_FLEXIBLE
-	[IT83XX_IRQ_WKO144] =   {GPIO_M, BIT(0),        16, BIT(0)},
-	[IT83XX_IRQ_WKO145] =   {GPIO_M, BIT(1),        16, BIT(1)},
-	[IT83XX_IRQ_WKO146] =   {GPIO_M, BIT(2),        16, BIT(2)},
-	[IT83XX_IRQ_WKO147] =   {GPIO_M, BIT(3),        16, BIT(3)},
-	[IT83XX_IRQ_WKO148] =   {GPIO_M, BIT(4),        16, BIT(4)},
-	[IT83XX_IRQ_WKO149] =   {GPIO_M, BIT(5),        16, BIT(5)},
-	[IT83XX_IRQ_WKO150] =   {GPIO_M, BIT(6),        16, BIT(6)},
+	[IT83XX_IRQ_WKO144] = { GPIO_M, BIT(0), 16, BIT(0) },
+	[IT83XX_IRQ_WKO145] = { GPIO_M, BIT(1), 16, BIT(1) },
+	[IT83XX_IRQ_WKO146] = { GPIO_M, BIT(2), 16, BIT(2) },
+	[IT83XX_IRQ_WKO147] = { GPIO_M, BIT(3), 16, BIT(3) },
+	[IT83XX_IRQ_WKO148] = { GPIO_M, BIT(4), 16, BIT(4) },
+	[IT83XX_IRQ_WKO149] = { GPIO_M, BIT(5), 16, BIT(5) },
+	[IT83XX_IRQ_WKO150] = { GPIO_M, BIT(6), 16, BIT(6) },
 #endif
 #if defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2)
-	[IT83XX_IRQ_GPO0]   =   {GPIO_O, BIT(0),        19, BIT(0)},
-	[IT83XX_IRQ_GPO1]   =   {GPIO_O, BIT(1),        19, BIT(1)},
-	[IT83XX_IRQ_GPO2]   =   {GPIO_O, BIT(2),        19, BIT(2)},
-	[IT83XX_IRQ_GPO3]   =   {GPIO_O, BIT(3),        19, BIT(3)},
-	[IT83XX_IRQ_GPP0]   =   {GPIO_P, BIT(0),        20, BIT(0)},
-	[IT83XX_IRQ_GPP1]   =   {GPIO_P, BIT(1),        20, BIT(1)},
-	[IT83XX_IRQ_GPP2]   =   {GPIO_P, BIT(2),        20, BIT(2)},
-	[IT83XX_IRQ_GPP3]   =   {GPIO_P, BIT(3),        20, BIT(3)},
-	[IT83XX_IRQ_GPP4]   =   {GPIO_P, BIT(4),        20, BIT(4)},
-	[IT83XX_IRQ_GPP5]   =   {GPIO_P, BIT(5),        20, BIT(5)},
-	[IT83XX_IRQ_GPP6]   =   {GPIO_P, BIT(6),        20, BIT(6)},
-	[IT83XX_IRQ_GPQ0]   =   {GPIO_Q, BIT(0),        21, BIT(0)},
-	[IT83XX_IRQ_GPQ1]   =   {GPIO_Q, BIT(1),        21, BIT(1)},
-	[IT83XX_IRQ_GPQ2]   =   {GPIO_Q, BIT(2),        21, BIT(2)},
-	[IT83XX_IRQ_GPQ3]   =   {GPIO_Q, BIT(3),        21, BIT(3)},
-	[IT83XX_IRQ_GPQ4]   =   {GPIO_Q, BIT(4),        21, BIT(4)},
-	[IT83XX_IRQ_GPQ5]   =   {GPIO_Q, BIT(5),        21, BIT(5)},
-	[IT83XX_IRQ_GPR0]   =   {GPIO_R, BIT(0),        22, BIT(0)},
-	[IT83XX_IRQ_GPR1]   =   {GPIO_R, BIT(1),        22, BIT(1)},
-	[IT83XX_IRQ_GPR2]   =   {GPIO_R, BIT(2),        22, BIT(2)},
-	[IT83XX_IRQ_GPR3]   =   {GPIO_R, BIT(3),        22, BIT(3)},
-	[IT83XX_IRQ_GPR4]   =   {GPIO_R, BIT(4),        22, BIT(4)},
-	[IT83XX_IRQ_GPR5]   =   {GPIO_R, BIT(5),        22, BIT(5)},
+	[IT83XX_IRQ_GPO0] = { GPIO_O, BIT(0), 19, BIT(0) },
+	[IT83XX_IRQ_GPO1] = { GPIO_O, BIT(1), 19, BIT(1) },
+	[IT83XX_IRQ_GPO2] = { GPIO_O, BIT(2), 19, BIT(2) },
+	[IT83XX_IRQ_GPO3] = { GPIO_O, BIT(3), 19, BIT(3) },
+	[IT83XX_IRQ_GPP0] = { GPIO_P, BIT(0), 20, BIT(0) },
+	[IT83XX_IRQ_GPP1] = { GPIO_P, BIT(1), 20, BIT(1) },
+	[IT83XX_IRQ_GPP2] = { GPIO_P, BIT(2), 20, BIT(2) },
+	[IT83XX_IRQ_GPP3] = { GPIO_P, BIT(3), 20, BIT(3) },
+	[IT83XX_IRQ_GPP4] = { GPIO_P, BIT(4), 20, BIT(4) },
+	[IT83XX_IRQ_GPP5] = { GPIO_P, BIT(5), 20, BIT(5) },
+	[IT83XX_IRQ_GPP6] = { GPIO_P, BIT(6), 20, BIT(6) },
+	[IT83XX_IRQ_GPQ0] = { GPIO_Q, BIT(0), 21, BIT(0) },
+	[IT83XX_IRQ_GPQ1] = { GPIO_Q, BIT(1), 21, BIT(1) },
+	[IT83XX_IRQ_GPQ2] = { GPIO_Q, BIT(2), 21, BIT(2) },
+	[IT83XX_IRQ_GPQ3] = { GPIO_Q, BIT(3), 21, BIT(3) },
+	[IT83XX_IRQ_GPQ4] = { GPIO_Q, BIT(4), 21, BIT(4) },
+	[IT83XX_IRQ_GPQ5] = { GPIO_Q, BIT(5), 21, BIT(5) },
+	[IT83XX_IRQ_GPR0] = { GPIO_R, BIT(0), 22, BIT(0) },
+	[IT83XX_IRQ_GPR1] = { GPIO_R, BIT(1), 22, BIT(1) },
+	[IT83XX_IRQ_GPR2] = { GPIO_R, BIT(2), 22, BIT(2) },
+	[IT83XX_IRQ_GPR3] = { GPIO_R, BIT(3), 22, BIT(3) },
+	[IT83XX_IRQ_GPR4] = { GPIO_R, BIT(4), 22, BIT(4) },
+	[IT83XX_IRQ_GPR5] = { GPIO_R, BIT(5), 22, BIT(5) },
 #endif
-	[IT83XX_IRQ_COUNT]  =   {     0,      0,         0,      0},
+	[IT83XX_IRQ_COUNT] = { 0, 0, 0, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(gpio_irqs) == IT83XX_IRQ_COUNT + 1);
 
@@ -246,7 +264,7 @@ static int gpio_to_irq(uint8_t port, uint8_t mask)
 
 	for (i = 0; i < IT83XX_IRQ_COUNT; i++) {
 		if (gpio_irqs[i].gpio_port == port &&
-				gpio_irqs[i].gpio_mask == mask)
+		    gpio_irqs[i].gpio_mask == mask)
 			return i;
 	}
 
@@ -260,133 +278,133 @@ struct gpio_1p8v_t {
 
 static const struct gpio_1p8v_t gpio_1p8v_sel[GPIO_PORT_COUNT][8] = {
 #ifdef IT83XX_GPIO_1P8V_PIN_EXTENDED
-	[GPIO_A] = { [4] = {&IT83XX_GPIO_GRC24, BIT(0)},
-		     [5] = {&IT83XX_GPIO_GRC24, BIT(1)},
-		     [6] = {&IT83XX_GPIO_GRC24, BIT(5)},
-		     [7] = {&IT83XX_GPIO_GRC24, BIT(6)} },
-	[GPIO_B] = { [3] = {&IT83XX_GPIO_GRC22, BIT(1)},
-		     [4] = {&IT83XX_GPIO_GRC22, BIT(0)},
-		     [5] = {&IT83XX_GPIO_GRC19, BIT(7)},
-		     [6] = {&IT83XX_GPIO_GRC19, BIT(6)},
-		     [7] = {&IT83XX_GPIO_GRC24, BIT(4)} },
-	[GPIO_C] = { [0] = {&IT83XX_GPIO_GRC22, BIT(7)},
-		     [1] = {&IT83XX_GPIO_GRC19, BIT(5)},
-		     [2] = {&IT83XX_GPIO_GRC19, BIT(4)},
-		     [4] = {&IT83XX_GPIO_GRC24, BIT(2)},
-		     [6] = {&IT83XX_GPIO_GRC24, BIT(3)},
-		     [7] = {&IT83XX_GPIO_GRC19, BIT(3)} },
-	[GPIO_D] = { [0] = {&IT83XX_GPIO_GRC19, BIT(2)},
-		     [1] = {&IT83XX_GPIO_GRC19, BIT(1)},
-		     [2] = {&IT83XX_GPIO_GRC19, BIT(0)},
-		     [3] = {&IT83XX_GPIO_GRC20, BIT(7)},
-		     [4] = {&IT83XX_GPIO_GRC20, BIT(6)},
-		     [5] = {&IT83XX_GPIO_GRC22, BIT(4)},
-		     [6] = {&IT83XX_GPIO_GRC22, BIT(5)},
-		     [7] = {&IT83XX_GPIO_GRC22, BIT(6)} },
-	[GPIO_E] = { [0] = {&IT83XX_GPIO_GRC20, BIT(5)},
-		     [1] = {&IT83XX_GPIO_GCR28, BIT(6)},
-		     [2] = {&IT83XX_GPIO_GCR28, BIT(7)},
-		     [4] = {&IT83XX_GPIO_GRC22, BIT(2)},
-		     [5] = {&IT83XX_GPIO_GRC22, BIT(3)},
-		     [6] = {&IT83XX_GPIO_GRC20, BIT(4)},
-		     [7] = {&IT83XX_GPIO_GRC20, BIT(3)} },
-	[GPIO_F] = { [0] = {&IT83XX_GPIO_GCR28, BIT(4)},
-		     [1] = {&IT83XX_GPIO_GCR28, BIT(5)},
-		     [2] = {&IT83XX_GPIO_GRC20, BIT(2)},
-		     [3] = {&IT83XX_GPIO_GRC20, BIT(1)},
-		     [4] = {&IT83XX_GPIO_GRC20, BIT(0)},
-		     [5] = {&IT83XX_GPIO_GRC21, BIT(7)},
-		     [6] = {&IT83XX_GPIO_GRC21, BIT(6)},
-		     [7] = {&IT83XX_GPIO_GRC21, BIT(5)} },
-	[GPIO_G] = { [0] = {&IT83XX_GPIO_GCR28, BIT(2)},
-		     [1] = {&IT83XX_GPIO_GRC21, BIT(4)},
-		     [2] = {&IT83XX_GPIO_GCR28, BIT(3)},
-		     [6] = {&IT83XX_GPIO_GRC21, BIT(3)} },
-	[GPIO_H] = { [0] = {&IT83XX_GPIO_GRC21, BIT(2)},
-		     [1] = {&IT83XX_GPIO_GRC21, BIT(1)},
-		     [2] = {&IT83XX_GPIO_GRC21, BIT(0)},
-		     [5] = {&IT83XX_GPIO_GCR27, BIT(7)},
-		     [6] = {&IT83XX_GPIO_GCR28, BIT(0)} },
-	[GPIO_I] = { [0] = {&IT83XX_GPIO_GCR27, BIT(3)},
-		     [1] = {&IT83XX_GPIO_GRC23, BIT(4)},
-		     [2] = {&IT83XX_GPIO_GRC23, BIT(5)},
-		     [3] = {&IT83XX_GPIO_GRC23, BIT(6)},
-		     [4] = {&IT83XX_GPIO_GRC23, BIT(7)},
-		     [5] = {&IT83XX_GPIO_GCR27, BIT(4)},
-		     [6] = {&IT83XX_GPIO_GCR27, BIT(5)},
-		     [7] = {&IT83XX_GPIO_GCR27, BIT(6)} },
-	[GPIO_J] = { [0] = {&IT83XX_GPIO_GRC23, BIT(0)},
-		     [1] = {&IT83XX_GPIO_GRC23, BIT(1)},
-		     [2] = {&IT83XX_GPIO_GRC23, BIT(2)},
-		     [3] = {&IT83XX_GPIO_GRC23, BIT(3)},
-		     [4] = {&IT83XX_GPIO_GCR27, BIT(0)},
-		     [5] = {&IT83XX_GPIO_GCR27, BIT(1)},
-		     [6] = {&IT83XX_GPIO_GCR27, BIT(2)},
-		     [7] = {&IT83XX_GPIO_GCR33, BIT(2)} },
-	[GPIO_K] = { [0] = {&IT83XX_GPIO_GCR26, BIT(0)},
-		     [1] = {&IT83XX_GPIO_GCR26, BIT(1)},
-		     [2] = {&IT83XX_GPIO_GCR26, BIT(2)},
-		     [3] = {&IT83XX_GPIO_GCR26, BIT(3)},
-		     [4] = {&IT83XX_GPIO_GCR26, BIT(4)},
-		     [5] = {&IT83XX_GPIO_GCR26, BIT(5)},
-		     [6] = {&IT83XX_GPIO_GCR26, BIT(6)},
-		     [7] = {&IT83XX_GPIO_GCR26, BIT(7)} },
-	[GPIO_L] = { [0] = {&IT83XX_GPIO_GCR25, BIT(0)},
-		     [1] = {&IT83XX_GPIO_GCR25, BIT(1)},
-		     [2] = {&IT83XX_GPIO_GCR25, BIT(2)},
-		     [3] = {&IT83XX_GPIO_GCR25, BIT(3)},
-		     [4] = {&IT83XX_GPIO_GCR25, BIT(4)},
-		     [5] = {&IT83XX_GPIO_GCR25, BIT(5)},
-		     [6] = {&IT83XX_GPIO_GCR25, BIT(6)},
-		     [7] = {&IT83XX_GPIO_GCR25, BIT(7)} },
+	[GPIO_A] = { [4] = { &IT83XX_GPIO_GRC24, BIT(0) },
+		     [5] = { &IT83XX_GPIO_GRC24, BIT(1) },
+		     [6] = { &IT83XX_GPIO_GRC24, BIT(5) },
+		     [7] = { &IT83XX_GPIO_GRC24, BIT(6) } },
+	[GPIO_B] = { [3] = { &IT83XX_GPIO_GRC22, BIT(1) },
+		     [4] = { &IT83XX_GPIO_GRC22, BIT(0) },
+		     [5] = { &IT83XX_GPIO_GRC19, BIT(7) },
+		     [6] = { &IT83XX_GPIO_GRC19, BIT(6) },
+		     [7] = { &IT83XX_GPIO_GRC24, BIT(4) } },
+	[GPIO_C] = { [0] = { &IT83XX_GPIO_GRC22, BIT(7) },
+		     [1] = { &IT83XX_GPIO_GRC19, BIT(5) },
+		     [2] = { &IT83XX_GPIO_GRC19, BIT(4) },
+		     [4] = { &IT83XX_GPIO_GRC24, BIT(2) },
+		     [6] = { &IT83XX_GPIO_GRC24, BIT(3) },
+		     [7] = { &IT83XX_GPIO_GRC19, BIT(3) } },
+	[GPIO_D] = { [0] = { &IT83XX_GPIO_GRC19, BIT(2) },
+		     [1] = { &IT83XX_GPIO_GRC19, BIT(1) },
+		     [2] = { &IT83XX_GPIO_GRC19, BIT(0) },
+		     [3] = { &IT83XX_GPIO_GRC20, BIT(7) },
+		     [4] = { &IT83XX_GPIO_GRC20, BIT(6) },
+		     [5] = { &IT83XX_GPIO_GRC22, BIT(4) },
+		     [6] = { &IT83XX_GPIO_GRC22, BIT(5) },
+		     [7] = { &IT83XX_GPIO_GRC22, BIT(6) } },
+	[GPIO_E] = { [0] = { &IT83XX_GPIO_GRC20, BIT(5) },
+		     [1] = { &IT83XX_GPIO_GCR28, BIT(6) },
+		     [2] = { &IT83XX_GPIO_GCR28, BIT(7) },
+		     [4] = { &IT83XX_GPIO_GRC22, BIT(2) },
+		     [5] = { &IT83XX_GPIO_GRC22, BIT(3) },
+		     [6] = { &IT83XX_GPIO_GRC20, BIT(4) },
+		     [7] = { &IT83XX_GPIO_GRC20, BIT(3) } },
+	[GPIO_F] = { [0] = { &IT83XX_GPIO_GCR28, BIT(4) },
+		     [1] = { &IT83XX_GPIO_GCR28, BIT(5) },
+		     [2] = { &IT83XX_GPIO_GRC20, BIT(2) },
+		     [3] = { &IT83XX_GPIO_GRC20, BIT(1) },
+		     [4] = { &IT83XX_GPIO_GRC20, BIT(0) },
+		     [5] = { &IT83XX_GPIO_GRC21, BIT(7) },
+		     [6] = { &IT83XX_GPIO_GRC21, BIT(6) },
+		     [7] = { &IT83XX_GPIO_GRC21, BIT(5) } },
+	[GPIO_G] = { [0] = { &IT83XX_GPIO_GCR28, BIT(2) },
+		     [1] = { &IT83XX_GPIO_GRC21, BIT(4) },
+		     [2] = { &IT83XX_GPIO_GCR28, BIT(3) },
+		     [6] = { &IT83XX_GPIO_GRC21, BIT(3) } },
+	[GPIO_H] = { [0] = { &IT83XX_GPIO_GRC21, BIT(2) },
+		     [1] = { &IT83XX_GPIO_GRC21, BIT(1) },
+		     [2] = { &IT83XX_GPIO_GRC21, BIT(0) },
+		     [5] = { &IT83XX_GPIO_GCR27, BIT(7) },
+		     [6] = { &IT83XX_GPIO_GCR28, BIT(0) } },
+	[GPIO_I] = { [0] = { &IT83XX_GPIO_GCR27, BIT(3) },
+		     [1] = { &IT83XX_GPIO_GRC23, BIT(4) },
+		     [2] = { &IT83XX_GPIO_GRC23, BIT(5) },
+		     [3] = { &IT83XX_GPIO_GRC23, BIT(6) },
+		     [4] = { &IT83XX_GPIO_GRC23, BIT(7) },
+		     [5] = { &IT83XX_GPIO_GCR27, BIT(4) },
+		     [6] = { &IT83XX_GPIO_GCR27, BIT(5) },
+		     [7] = { &IT83XX_GPIO_GCR27, BIT(6) } },
+	[GPIO_J] = { [0] = { &IT83XX_GPIO_GRC23, BIT(0) },
+		     [1] = { &IT83XX_GPIO_GRC23, BIT(1) },
+		     [2] = { &IT83XX_GPIO_GRC23, BIT(2) },
+		     [3] = { &IT83XX_GPIO_GRC23, BIT(3) },
+		     [4] = { &IT83XX_GPIO_GCR27, BIT(0) },
+		     [5] = { &IT83XX_GPIO_GCR27, BIT(1) },
+		     [6] = { &IT83XX_GPIO_GCR27, BIT(2) },
+		     [7] = { &IT83XX_GPIO_GCR33, BIT(2) } },
+	[GPIO_K] = { [0] = { &IT83XX_GPIO_GCR26, BIT(0) },
+		     [1] = { &IT83XX_GPIO_GCR26, BIT(1) },
+		     [2] = { &IT83XX_GPIO_GCR26, BIT(2) },
+		     [3] = { &IT83XX_GPIO_GCR26, BIT(3) },
+		     [4] = { &IT83XX_GPIO_GCR26, BIT(4) },
+		     [5] = { &IT83XX_GPIO_GCR26, BIT(5) },
+		     [6] = { &IT83XX_GPIO_GCR26, BIT(6) },
+		     [7] = { &IT83XX_GPIO_GCR26, BIT(7) } },
+	[GPIO_L] = { [0] = { &IT83XX_GPIO_GCR25, BIT(0) },
+		     [1] = { &IT83XX_GPIO_GCR25, BIT(1) },
+		     [2] = { &IT83XX_GPIO_GCR25, BIT(2) },
+		     [3] = { &IT83XX_GPIO_GCR25, BIT(3) },
+		     [4] = { &IT83XX_GPIO_GCR25, BIT(4) },
+		     [5] = { &IT83XX_GPIO_GCR25, BIT(5) },
+		     [6] = { &IT83XX_GPIO_GCR25, BIT(6) },
+		     [7] = { &IT83XX_GPIO_GCR25, BIT(7) } },
 #if defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2)
-	[GPIO_O] = { [0] = {&IT83XX_GPIO_GCR31, BIT(0)},
-		     [1] = {&IT83XX_GPIO_GCR31, BIT(1)},
-		     [2] = {&IT83XX_GPIO_GCR31, BIT(2)},
-		     [3] = {&IT83XX_GPIO_GCR31, BIT(3)} },
-	[GPIO_P] = { [0] = {&IT83XX_GPIO_GCR32, BIT(0)},
-		     [1] = {&IT83XX_GPIO_GCR32, BIT(1)},
-		     [2] = {&IT83XX_GPIO_GCR32, BIT(2)},
-		     [3] = {&IT83XX_GPIO_GCR32, BIT(3)},
-		     [4] = {&IT83XX_GPIO_GCR32, BIT(4)},
-		     [5] = {&IT83XX_GPIO_GCR32, BIT(5)},
-		     [6] = {&IT83XX_GPIO_GCR32, BIT(6)} },
+	[GPIO_O] = { [0] = { &IT83XX_GPIO_GCR31, BIT(0) },
+		     [1] = { &IT83XX_GPIO_GCR31, BIT(1) },
+		     [2] = { &IT83XX_GPIO_GCR31, BIT(2) },
+		     [3] = { &IT83XX_GPIO_GCR31, BIT(3) } },
+	[GPIO_P] = { [0] = { &IT83XX_GPIO_GCR32, BIT(0) },
+		     [1] = { &IT83XX_GPIO_GCR32, BIT(1) },
+		     [2] = { &IT83XX_GPIO_GCR32, BIT(2) },
+		     [3] = { &IT83XX_GPIO_GCR32, BIT(3) },
+		     [4] = { &IT83XX_GPIO_GCR32, BIT(4) },
+		     [5] = { &IT83XX_GPIO_GCR32, BIT(5) },
+		     [6] = { &IT83XX_GPIO_GCR32, BIT(6) } },
 #endif
 #else
-	[GPIO_A] = { [4] = {&IT83XX_GPIO_GRC24, BIT(0)},
-		     [5] = {&IT83XX_GPIO_GRC24, BIT(1)} },
-	[GPIO_B] = { [3] = {&IT83XX_GPIO_GRC22, BIT(1)},
-		     [4] = {&IT83XX_GPIO_GRC22, BIT(0)},
-		     [5] = {&IT83XX_GPIO_GRC19, BIT(7)},
-		     [6] = {&IT83XX_GPIO_GRC19, BIT(6)} },
-	[GPIO_C] = { [1] = {&IT83XX_GPIO_GRC19, BIT(5)},
-		     [2] = {&IT83XX_GPIO_GRC19, BIT(4)},
-		     [7] = {&IT83XX_GPIO_GRC19, BIT(3)} },
-	[GPIO_D] = { [0] = {&IT83XX_GPIO_GRC19, BIT(2)},
-		     [1] = {&IT83XX_GPIO_GRC19, BIT(1)},
-		     [2] = {&IT83XX_GPIO_GRC19, BIT(0)},
-		     [3] = {&IT83XX_GPIO_GRC20, BIT(7)},
-		     [4] = {&IT83XX_GPIO_GRC20, BIT(6)} },
-	[GPIO_E] = { [0] = {&IT83XX_GPIO_GRC20, BIT(5)},
-		     [6] = {&IT83XX_GPIO_GRC20, BIT(4)},
-		     [7] = {&IT83XX_GPIO_GRC20, BIT(3)} },
-	[GPIO_F] = { [2] = {&IT83XX_GPIO_GRC20, BIT(2)},
-		     [3] = {&IT83XX_GPIO_GRC20, BIT(1)},
-		     [4] = {&IT83XX_GPIO_GRC20, BIT(0)},
-		     [5] = {&IT83XX_GPIO_GRC21, BIT(7)},
-		     [6] = {&IT83XX_GPIO_GRC21, BIT(6)},
-		     [7] = {&IT83XX_GPIO_GRC21, BIT(5)} },
-	[GPIO_H] = { [0] = {&IT83XX_GPIO_GRC21, BIT(2)},
-		     [1] = {&IT83XX_GPIO_GRC21, BIT(1)},
-		     [2] = {&IT83XX_GPIO_GRC21, BIT(0)} },
-	[GPIO_I] = { [1] = {&IT83XX_GPIO_GRC23, BIT(4)},
-		     [2] = {&IT83XX_GPIO_GRC23, BIT(5)},
-		     [3] = {&IT83XX_GPIO_GRC23, BIT(6)},
-		     [4] = {&IT83XX_GPIO_GRC23, BIT(7)} },
-	[GPIO_J] = { [0] = {&IT83XX_GPIO_GRC23, BIT(0)},
-		     [1] = {&IT83XX_GPIO_GRC23, BIT(1)},
-		     [2] = {&IT83XX_GPIO_GRC23, BIT(2)},
-		     [3] = {&IT83XX_GPIO_GRC23, BIT(3)} },
+	[GPIO_A] = { [4] = { &IT83XX_GPIO_GRC24, BIT(0) },
+		     [5] = { &IT83XX_GPIO_GRC24, BIT(1) } },
+	[GPIO_B] = { [3] = { &IT83XX_GPIO_GRC22, BIT(1) },
+		     [4] = { &IT83XX_GPIO_GRC22, BIT(0) },
+		     [5] = { &IT83XX_GPIO_GRC19, BIT(7) },
+		     [6] = { &IT83XX_GPIO_GRC19, BIT(6) } },
+	[GPIO_C] = { [1] = { &IT83XX_GPIO_GRC19, BIT(5) },
+		     [2] = { &IT83XX_GPIO_GRC19, BIT(4) },
+		     [7] = { &IT83XX_GPIO_GRC19, BIT(3) } },
+	[GPIO_D] = { [0] = { &IT83XX_GPIO_GRC19, BIT(2) },
+		     [1] = { &IT83XX_GPIO_GRC19, BIT(1) },
+		     [2] = { &IT83XX_GPIO_GRC19, BIT(0) },
+		     [3] = { &IT83XX_GPIO_GRC20, BIT(7) },
+		     [4] = { &IT83XX_GPIO_GRC20, BIT(6) } },
+	[GPIO_E] = { [0] = { &IT83XX_GPIO_GRC20, BIT(5) },
+		     [6] = { &IT83XX_GPIO_GRC20, BIT(4) },
+		     [7] = { &IT83XX_GPIO_GRC20, BIT(3) } },
+	[GPIO_F] = { [2] = { &IT83XX_GPIO_GRC20, BIT(2) },
+		     [3] = { &IT83XX_GPIO_GRC20, BIT(1) },
+		     [4] = { &IT83XX_GPIO_GRC20, BIT(0) },
+		     [5] = { &IT83XX_GPIO_GRC21, BIT(7) },
+		     [6] = { &IT83XX_GPIO_GRC21, BIT(6) },
+		     [7] = { &IT83XX_GPIO_GRC21, BIT(5) } },
+	[GPIO_H] = { [0] = { &IT83XX_GPIO_GRC21, BIT(2) },
+		     [1] = { &IT83XX_GPIO_GRC21, BIT(1) },
+		     [2] = { &IT83XX_GPIO_GRC21, BIT(0) } },
+	[GPIO_I] = { [1] = { &IT83XX_GPIO_GRC23, BIT(4) },
+		     [2] = { &IT83XX_GPIO_GRC23, BIT(5) },
+		     [3] = { &IT83XX_GPIO_GRC23, BIT(6) },
+		     [4] = { &IT83XX_GPIO_GRC23, BIT(7) } },
+	[GPIO_J] = { [0] = { &IT83XX_GPIO_GRC23, BIT(0) },
+		     [1] = { &IT83XX_GPIO_GRC23, BIT(1) },
+		     [2] = { &IT83XX_GPIO_GRC23, BIT(2) },
+		     [3] = { &IT83XX_GPIO_GRC23, BIT(3) } },
 #endif
 };
 
@@ -405,26 +423,45 @@ static void gpio_1p8v_3p3v_sel_by_pin(uint8_t port, uint8_t pin, int sel_1p8v)
 }
 
 static inline void it83xx_set_alt_func(uint32_t port, uint32_t pin,
-				enum gpio_alternate_func func)
+				       enum gpio_alternate_func func)
 {
 	/*
 	 * If func is not ALT_FUNC_NONE, set for alternate function.
 	 * Otherwise, turn the pin into an input as it's default.
 	 */
 	if (func != GPIO_ALT_FUNC_NONE)
-		IT83XX_GPIO_CTRL(port, pin) &= ~(GPCR_PORT_PIN_MODE_OUTPUT |
-			GPCR_PORT_PIN_MODE_INPUT);
+		IT83XX_GPIO_CTRL(port, pin) &=
+			~(GPCR_PORT_PIN_MODE_OUTPUT | GPCR_PORT_PIN_MODE_INPUT);
 	else
-		IT83XX_GPIO_CTRL(port, pin) =
-			(IT83XX_GPIO_CTRL(port, pin) | GPCR_PORT_PIN_MODE_INPUT)
-			& ~GPCR_PORT_PIN_MODE_OUTPUT;
+		IT83XX_GPIO_CTRL(port, pin) = (IT83XX_GPIO_CTRL(port, pin) |
+					       GPCR_PORT_PIN_MODE_INPUT) &
+					      ~GPCR_PORT_PIN_MODE_OUTPUT;
 }
 
 void gpio_set_alternate_function(uint32_t port, uint32_t mask,
-				enum gpio_alternate_func func)
+				 enum gpio_alternate_func func)
 {
 	uint32_t pin = 0;
 
+	/* Alternate function configuration for KSI/KSO pins */
+	if (port > GPIO_PORT_COUNT) {
+		port -= GPIO_KSI;
+		/*
+		 * If func is non-negative, set for keyboard scan function.
+		 * Otherwise, turn the pin into a GPIO input.
+		 */
+		if (func >= GPIO_ALT_FUNC_DEFAULT) {
+			/* KBS mode */
+			*kbs_gpio_ctrl_regs[port].gpio_mode &= ~mask;
+		} else {
+			/* input */
+			*kbs_gpio_ctrl_regs[port].gpio_out &= ~mask;
+			/* GPIO mode */
+			*kbs_gpio_ctrl_regs[port].gpio_mode |= mask;
+		}
+		return;
+	}
+
 	/* For each bit high in the mask, set that pin to use alt. func. */
 	while (mask > 0) {
 		if (mask & 1)
@@ -437,7 +474,9 @@ void gpio_set_alternate_function(uint32_t port, uint32_t mask,
 test_mockable int gpio_get_level(enum gpio_signal signal)
 {
 	return (IT83XX_GPIO_DATA_MIRROR(gpio_list[signal].port) &
-			gpio_list[signal].mask) ? 1 : 0;
+		gpio_list[signal].mask) ?
+		       1 :
+		       0;
 }
 
 void gpio_set_level(enum gpio_signal signal, int value)
@@ -447,22 +486,53 @@ void gpio_set_level(enum gpio_signal signal, int value)
 
 	if (value)
 		IT83XX_GPIO_DATA(gpio_list[signal].port) |=
-				 gpio_list[signal].mask;
+			gpio_list[signal].mask;
 	else
 		IT83XX_GPIO_DATA(gpio_list[signal].port) &=
-				~gpio_list[signal].mask;
+			~gpio_list[signal].mask;
 	/* restore interrupts */
 	set_int_mask(int_mask);
 }
 
 void gpio_kbs_pin_gpio_mode(uint32_t port, uint32_t mask, uint32_t flags)
 {
-	if (port == GPIO_KSO_H)
-		IT83XX_KBS_KSOHGCTRL |= mask;
-	else if (port == GPIO_KSO_L)
-		IT83XX_KBS_KSOLGCTRL |= mask;
-	else if (port == GPIO_KSI)
-		IT83XX_KBS_KSIGCTRL |= mask;
+	uint32_t idx = port - GPIO_KSI;
+
+	/* Set GPIO mode */
+	*kbs_gpio_ctrl_regs[idx].gpio_mode |= mask;
+
+	/* Set input or output */
+	if (flags & GPIO_OUTPUT) {
+		/*
+		 * Select open drain first, so that we don't glitch the signal
+		 * when changing the line to an output.
+		 */
+		if (flags & GPIO_OPEN_DRAIN)
+			/*
+			 * it83xx: need external pullup for output data high
+			 * it8xxx2: this pin is always internal pullup
+			 */
+			IT83XX_GPIO_GPOT(port) |= mask;
+		else
+			/*
+			 * it8xxx2: this pin is not internal pullup
+			 */
+			IT83XX_GPIO_GPOT(port) &= ~mask;
+
+		/* Set level before change to output. */
+		if (flags & GPIO_HIGH)
+			IT83XX_GPIO_DATA(port) |= mask;
+		else if (flags & GPIO_LOW)
+			IT83XX_GPIO_DATA(port) &= ~mask;
+		*kbs_gpio_ctrl_regs[idx].gpio_out |= mask;
+	} else {
+		*kbs_gpio_ctrl_regs[idx].gpio_out &= ~mask;
+		if (flags & GPIO_PULL_UP)
+			IT83XX_GPIO_GPOT(port) |= mask;
+		else
+			/* No internal pullup and pulldown */
+			IT83XX_GPIO_GPOT(port) &= ~mask;
+	}
 }
 
 #ifndef IT83XX_GPIO_INT_FLEXIBLE
@@ -495,8 +565,8 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
 	uint32_t pin = 0;
 	uint32_t mask_copy = mask;
 
+	/* Set GPIO mode for KSI/KSO pins */
 	if (port > GPIO_PORT_COUNT) {
-		/* set up GPIO of KSO/KSI pins (support input only). */
 		gpio_kbs_pin_gpio_mode(port, mask, flags);
 		return;
 	}
@@ -524,26 +594,26 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
 			/* Set input or output. */
 			if (flags & GPIO_OUTPUT)
 				IT83XX_GPIO_CTRL(port, pin) =
-				(IT83XX_GPIO_CTRL(port, pin) |
-				 GPCR_PORT_PIN_MODE_OUTPUT) &
-				~GPCR_PORT_PIN_MODE_INPUT;
+					(IT83XX_GPIO_CTRL(port, pin) |
+					 GPCR_PORT_PIN_MODE_OUTPUT) &
+					~GPCR_PORT_PIN_MODE_INPUT;
 			else
 				IT83XX_GPIO_CTRL(port, pin) =
-				(IT83XX_GPIO_CTRL(port, pin) |
-				 GPCR_PORT_PIN_MODE_INPUT) &
-				~GPCR_PORT_PIN_MODE_OUTPUT;
+					(IT83XX_GPIO_CTRL(port, pin) |
+					 GPCR_PORT_PIN_MODE_INPUT) &
+					~GPCR_PORT_PIN_MODE_OUTPUT;
 
 			/* Handle pullup / pulldown */
 			if (flags & GPIO_PULL_UP) {
 				IT83XX_GPIO_CTRL(port, pin) =
-				(IT83XX_GPIO_CTRL(port, pin) |
-				 GPCR_PORT_PIN_MODE_PULLUP) &
-				~GPCR_PORT_PIN_MODE_PULLDOWN;
+					(IT83XX_GPIO_CTRL(port, pin) |
+					 GPCR_PORT_PIN_MODE_PULLUP) &
+					~GPCR_PORT_PIN_MODE_PULLDOWN;
 			} else if (flags & GPIO_PULL_DOWN) {
 				IT83XX_GPIO_CTRL(port, pin) =
-				(IT83XX_GPIO_CTRL(port, pin) |
-				 GPCR_PORT_PIN_MODE_PULLDOWN) &
-				~GPCR_PORT_PIN_MODE_PULLUP;
+					(IT83XX_GPIO_CTRL(port, pin) |
+					 GPCR_PORT_PIN_MODE_PULLDOWN) &
+					~GPCR_PORT_PIN_MODE_PULLUP;
 			} else {
 				/* No pull up/down */
 				IT83XX_GPIO_CTRL(port, pin) &=
@@ -553,7 +623,7 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
 
 			/* To select 1.8v or 3.3v support. */
 			gpio_1p8v_3p3v_sel_by_pin(port, pin,
-						(flags & GPIO_SEL_1P8V));
+						  (flags & GPIO_SEL_1P8V));
 		}
 
 		pin++;
@@ -667,6 +737,24 @@ void gpio_pre_init(void)
 
 	IT83XX_GPIO_GCR = 0x06;
 
+#if !defined(CONFIG_IT83XX_VCC_1P8V) && !defined(CONFIG_IT83XX_VCC_3P3V)
+#error Please select voltage level of VCC for EC.
+#endif
+
+#if defined(CONFIG_IT83XX_VCC_1P8V) && defined(CONFIG_IT83XX_VCC_3P3V)
+#error Must select only one voltage level of VCC for EC.
+#endif
+	/* The power level of GPM6 follows VCC */
+	IT83XX_GPIO_GCR29 |= BIT(0);
+
+	/* The power level (VCC) of GPM0~6 is 1.8V */
+	if (IS_ENABLED(CONFIG_IT83XX_VCC_1P8V))
+		IT83XX_GPIO_GCR30 |= BIT(4);
+
+	/* The power level (VCC) of GPM0~6 is 3.3V */
+	if (IS_ENABLED(CONFIG_IT83XX_VCC_3P3V))
+		IT83XX_GPIO_GCR30 &= ~BIT(4);
+
 #if IT83XX_USBPD_PHY_PORT_COUNT < CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT
 #error "ITE pd active port count should be less than physical port count !"
 #endif
@@ -719,10 +807,12 @@ void gpio_pre_init(void)
 	 */
 	if (IS_ENABLED(IT83XX_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN)) {
 		for (i = 0; i < 8; i++) {
-			IT83XX_GPIO_CTRL(GPIO_K, i) = (GPCR_PORT_PIN_MODE_INPUT
-				| GPCR_PORT_PIN_MODE_PULLDOWN);
-			IT83XX_GPIO_CTRL(GPIO_L, i) = (GPCR_PORT_PIN_MODE_INPUT
-				| GPCR_PORT_PIN_MODE_PULLDOWN);
+			IT83XX_GPIO_CTRL(GPIO_K, i) =
+				(GPCR_PORT_PIN_MODE_INPUT |
+				 GPCR_PORT_PIN_MODE_PULLDOWN);
+			IT83XX_GPIO_CTRL(GPIO_L, i) =
+				(GPCR_PORT_PIN_MODE_INPUT |
+				 GPCR_PORT_PIN_MODE_PULLDOWN);
 		}
 	}
 
@@ -786,7 +876,10 @@ static void __gpio_irq(void)
 	/* Determine interrupt number. */
 	int irq = intc_get_ec_int();
 
-#ifdef HAS_TASK_KEYSCAN
+	/* assert failure if interrupt number is zero */
+	ASSERT(irq);
+
+#if defined(HAS_TASK_KEYSCAN) && !defined(CONFIG_KEYBOARD_DISCRETE)
 	if (irq == IT83XX_IRQ_WKINTC) {
 		keyboard_raw_interrupt();
 		return;
diff --git a/chip/it83xx/hwtimer.c b/chip/it83xx/hwtimer.c
index 291751a1cb..13c28ca57e 100644
--- a/chip/it83xx/hwtimer.c
+++ b/chip/it83xx/hwtimer.c
@@ -1,12 +1,12 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Hardware timers driver */
 
-#include "cpu.h"
 #include "common.h"
+#include "cpu.h"
 #include "hooks.h"
 #include "hwtimer.h"
 #include "hwtimer_chip.h"
@@ -55,18 +55,18 @@
 #define MS_TO_COUNT(hz, ms) ((hz) * (ms) / 1000)
 
 const struct ext_timer_ctrl_t et_ctrl_regs[] = {
-	{&IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x08,
-		IT83XX_IRQ_EXT_TIMER3},
-	{&IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x10,
-		IT83XX_IRQ_EXT_TIMER4},
-	{&IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x20,
-		IT83XX_IRQ_EXT_TIMER5},
-	{&IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x40,
-		IT83XX_IRQ_EXT_TIMER6},
-	{&IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x80,
-		IT83XX_IRQ_EXT_TIMER7},
-	{&IT83XX_INTC_IELMR10, &IT83XX_INTC_IPOLR10, &IT83XX_INTC_ISR10, 0x01,
-		IT83XX_IRQ_EXT_TMR8},
+	{ &IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x08,
+	  IT83XX_IRQ_EXT_TIMER3 },
+	{ &IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x10,
+	  IT83XX_IRQ_EXT_TIMER4 },
+	{ &IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x20,
+	  IT83XX_IRQ_EXT_TIMER5 },
+	{ &IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x40,
+	  IT83XX_IRQ_EXT_TIMER6 },
+	{ &IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x80,
+	  IT83XX_IRQ_EXT_TIMER7 },
+	{ &IT83XX_INTC_IELMR10, &IT83XX_INTC_IPOLR10, &IT83XX_INTC_ISR10, 0x01,
+	  IT83XX_IRQ_EXT_TMR8 },
 };
 BUILD_ASSERT(ARRAY_SIZE(et_ctrl_regs) == EXT_TIMER_COUNT);
 
@@ -128,7 +128,8 @@ void __hw_clock_event_set(uint32_t deadline)
 	wait = deadline - __hw_clock_source_read();
 	IT83XX_ETWD_ETXCNTLR(EVENT_EXT_TIMER) =
 		wait < EVENT_TIMER_COUNT_TO_US(0xffffffff) ?
-		EVENT_TIMER_US_TO_COUNT(wait) : 0xffffffff;
+			EVENT_TIMER_US_TO_COUNT(wait) :
+			0xffffffff;
 	/* enable and re-start timer */
 	IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) |= 0x03;
 	task_enable_irq(et_ctrl_regs[EVENT_EXT_TIMER].irq);
@@ -206,6 +207,13 @@ static void __hw_clock_source_irq(void)
 	}
 #endif
 
+#ifdef CONFIG_CEC_BITBANG
+	if (irq == et_ctrl_regs[CEC_EXT_TIMER].irq) {
+		cec_ext_timer_interrupt();
+		return;
+	}
+#endif
+
 	/* Interrupt of free running timer TIMER_H. */
 	if (irq == et_ctrl_regs[FREE_EXT_TIMER_H].irq) {
 		free_run_timer_overflow();
@@ -225,7 +233,7 @@ DECLARE_IRQ(CPU_INT_GROUP_3, __hw_clock_source_irq, 1);
 
 #ifdef IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES
 /* Number of CPU cycles in 125 us */
-#define CYCLES_125NS (125*(PLL_CLOCK/SECOND) / 1000)
+#define CYCLES_125NS (125 * (PLL_CLOCK / SECOND) / 1000)
 uint32_t __ram_code ext_observation_reg_read(enum ext_timer_sel ext_timer)
 {
 	uint32_t prev_mask = read_clear_int_mask();
@@ -245,8 +253,8 @@ uint32_t __ram_code ext_observation_reg_read(enum ext_timer_sel ext_timer)
 		/* read for the second time */
 		"lwi %0,[%1]\n\t"
 		: "=&r"(val)
-		: "r"((uintptr_t) &IT83XX_ETWD_ETXCNTOR(ext_timer)),
-			"i"(CYCLES_125NS));
+		: "r"((uintptr_t)&IT83XX_ETWD_ETXCNTOR(ext_timer)),
+		  "i"(CYCLES_125NS));
 	/* restore interrupts */
 	set_int_mask(prev_mask);
 
@@ -275,10 +283,8 @@ void ext_timer_stop(enum ext_timer_sel ext_timer, int dis_irq)
 }
 
 static void ext_timer_ctrl(enum ext_timer_sel ext_timer,
-		enum ext_timer_clock_source ext_timer_clock,
-		int start,
-		int with_int,
-		int32_t count)
+			   enum ext_timer_clock_source ext_timer_clock,
+			   int start, int with_int, int32_t count)
 {
 	uint8_t intc_mask;
 
@@ -307,12 +313,8 @@ static void ext_timer_ctrl(enum ext_timer_sel ext_timer,
 }
 
 int ext_timer_ms(enum ext_timer_sel ext_timer,
-		enum ext_timer_clock_source ext_timer_clock,
-		int start,
-		int with_int,
-		int32_t ms,
-		int first_time_enable,
-		int raw)
+		 enum ext_timer_clock_source ext_timer_clock, int start,
+		 int with_int, int32_t ms, int first_time_enable, int raw)
 {
 	uint32_t count;
 
diff --git a/chip/it83xx/hwtimer_chip.h b/chip/it83xx/hwtimer_chip.h
index ef53c4e871..756f669c4d 100644
--- a/chip/it83xx/hwtimer_chip.h
+++ b/chip/it83xx/hwtimer_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,25 +8,51 @@
 #ifndef __CROS_EC_HWTIMER_CHIP_H
 #define __CROS_EC_HWTIMER_CHIP_H
 
-#define TIMER_COUNT_1US_SHIFT      3
+#define TIMER_COUNT_1US_SHIFT 3
 
 /* Microseconds to event timer counter setting register */
-#define EVENT_TIMER_US_TO_COUNT(us)  ((us) << TIMER_COUNT_1US_SHIFT)
+#define EVENT_TIMER_US_TO_COUNT(us) ((us) << TIMER_COUNT_1US_SHIFT)
 /* Event timer counter observation value to microseconds */
 #define EVENT_TIMER_COUNT_TO_US(cnt) ((cnt) >> TIMER_COUNT_1US_SHIFT)
 
-#define FREE_EXT_TIMER_L     EXT_TIMER_3
-#define FREE_EXT_TIMER_H     EXT_TIMER_4
-#define FAN_CTRL_EXT_TIMER   EXT_TIMER_5
-#define EVENT_EXT_TIMER      EXT_TIMER_6
-#define WDT_EXT_TIMER        EXT_TIMER_7
-#define LOW_POWER_EXT_TIMER  EXT_TIMER_8
+#define FREE_EXT_TIMER_L EXT_TIMER_3
+#define FREE_EXT_TIMER_H EXT_TIMER_4
+
+/*
+ * We only have one free timer, so use it for either fans or CEC. Since ITE also
+ * has a CEC peripheral, devices without a fan can have up to two CEC ports, and
+ * devices with a fan up to one.
+ */
+#if defined(CONFIG_FANS) && defined(CONFIG_CEC_BITBANG)
+#error "Can't enable both CONFIG_FANS and CONFIG_CEC_BITBANG"
+#endif
+#if defined(CONFIG_FANS)
+#define FAN_CTRL_EXT_TIMER EXT_TIMER_5
+#elif defined(CONFIG_CEC_BITBANG)
+#define CEC_EXT_TIMER EXT_TIMER_5
+#endif
+
+#define EVENT_EXT_TIMER EXT_TIMER_6
+/*
+ * The low power timer is used to continue system time when EC goes into low
+ * power in idle task. Timer 7 is 24bit timer and configured at 32.768khz.
+ * The configuration is enough for continuing system time, because periodic
+ * tick event (interval is 500ms on it8xxx2) will wake EC up.
+ *
+ * IMPORTANT:
+ * If you change low power timer to a non-24bit timer, you also have to change
+ * mask of observation register in clock_sleep_mode_wakeup_isr() or EC will get
+ * wrong system time after resume.
+ */
+#define LOW_POWER_EXT_TIMER EXT_TIMER_7
+#define LOW_POWER_TIMER_MASK (BIT(24) - 1)
+#define WDT_EXT_TIMER EXT_TIMER_8
 
 enum ext_timer_clock_source {
 	EXT_PSR_32P768K_HZ = 0,
-	EXT_PSR_1P024K_HZ  = 1,
-	EXT_PSR_32_HZ      = 2,
-	EXT_PSR_8M_HZ      = 3
+	EXT_PSR_1P024K_HZ = 1,
+	EXT_PSR_32_HZ = 2,
+	EXT_PSR_8M_HZ = 3
 };
 
 /*
@@ -63,6 +89,7 @@ uint32_t __ram_code ext_observation_reg_read(enum ext_timer_sel ext_timer);
 void ext_timer_start(enum ext_timer_sel ext_timer, int en_irq);
 void ext_timer_stop(enum ext_timer_sel ext_timer, int dis_irq);
 void fan_ext_timer_interrupt(void);
+void cec_ext_timer_interrupt(void);
 void update_exc_start_time(void);
 
 /**
@@ -71,11 +98,7 @@ void update_exc_start_time(void);
  * @param raw	(!=0) timer count equal to param "ms" no conversion.
  */
 int ext_timer_ms(enum ext_timer_sel ext_timer,
-		enum ext_timer_clock_source ext_timer_clock,
-		int start,
-		int et_int,
-		int32_t ms,
-		int first_time_enable,
-		int raw);
+		 enum ext_timer_clock_source ext_timer_clock, int start,
+		 int et_int, int32_t ms, int first_time_enable, int raw);
 
 #endif /* __CROS_EC_HWTIMER_CHIP_H */
diff --git a/chip/it83xx/i2c.c b/chip/it83xx/i2c.c
index 91863eb308..701f2a9576 100644
--- a/chip/it83xx/i2c.c
+++ b/chip/it83xx/i2c.c
@@ -1,10 +1,11 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* I2C module for Chrome EC */
 
+#include "builtin/assert.h"
 #include "clock.h"
 #include "common.h"
 #include "console.h"
@@ -16,11 +17,53 @@
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
 
 /* Default maximum time we allow for an I2C transfer */
 #define I2C_TIMEOUT_DEFAULT_US (100 * MSEC)
 
+#ifdef CONFIG_IT83XX_I2C_CMD_QUEUE
+
+#ifdef CHIP_CORE_NDS32
+#error "Remapping DLM base is required on it8320 series"
+#endif
+
+/* It is allowed to configure the size up to 2K bytes. */
+#define I2C_CQ_MODE_MAX_PAYLOAD_SIZE 128
+/* reserved 5 bytes for ID and CMD_x */
+#define I2C_CQ_MODE_TX_MAX_PAYLOAD_SIZE (I2C_CQ_MODE_MAX_PAYLOAD_SIZE - 5)
+uint8_t i2c_cq_mode_tx_dlm[I2C_ENHANCED_PORT_COUNT]
+			  [I2C_CQ_MODE_MAX_PAYLOAD_SIZE] __aligned(4);
+uint8_t i2c_cq_mode_rx_dlm[I2C_ENHANCED_PORT_COUNT]
+			  [I2C_CQ_MODE_MAX_PAYLOAD_SIZE] __aligned(4);
+
+/* Repeat Start */
+#define I2C_CQ_CMD_L_RS BIT(7)
+/*
+ * R/W (Read/ Write) decides the I2C read or write direction
+ * 1: read, 0: write
+ */
+#define I2C_CQ_CMD_L_RW BIT(6)
+/* P (STOP) is the I2C STOP condition */
+#define I2C_CQ_CMD_L_P BIT(5)
+/* E (End) is this device end flag */
+#define I2C_CQ_CMD_L_E BIT(4)
+/* LA (Last ACK) is Last ACK in master receiver */
+#define I2C_CQ_CMD_L_LA BIT(3)
+/* bit[2:0] are number of transfer out or receive data which depends on R/W. */
+#define I2C_CQ_CMD_L_NUM_BIT_2_0 GENMASK(2, 0)
+
+struct i2c_cq_packet {
+	uint8_t id;
+	uint8_t cmd_l;
+	uint8_t cmd_h;
+	uint8_t wdata[0];
+};
+
+/* Preventing CPU going into idle mode during command queue I2C transaction. */
+static uint32_t i2c_idle_disabled;
+#endif /* CONFIG_IT83XX_I2C_CMD_QUEUE */
+
 enum enhanced_i2c_transfer_direct {
 	TX_DIRECT,
 	RX_DIRECT,
@@ -44,8 +87,8 @@ enum i2c_host_status {
 	/* Byte done status */
 	HOSTA_BDS = 0x80,
 	/* Error bit is set */
-	HOSTA_ANY_ERROR = (HOSTA_DVER | HOSTA_BSER |
-				HOSTA_FAIL | HOSTA_NACK | HOSTA_TMOE),
+	HOSTA_ANY_ERROR = (HOSTA_DVER | HOSTA_BSER | HOSTA_FAIL | HOSTA_NACK |
+			   HOSTA_TMOE),
 	/* W/C for next byte */
 	HOSTA_NEXT_BYTE = HOSTA_BDS,
 	/* W/C host status register */
@@ -94,10 +137,12 @@ enum enhanced_i2c_ctl {
 	E_RX_MODE = 0x80,
 	/* State reset and hardware reset */
 	E_STS_AND_HW_RST = (E_STS_RST | E_HW_RST),
-	/* Generate start condition and transmit slave address */
+	/* Generate start condition and transmit peripheral address */
 	E_START_ID = (E_INT_EN | E_MODE_SEL | E_ACK | E_START | E_HW_RST),
 	/* Generate stop condition */
 	E_FINISH = (E_INT_EN | E_MODE_SEL | E_ACK | E_STOP | E_HW_RST),
+	/* start with command queue mode */
+	E_START_CQ = (E_INT_EN | E_MODE_SEL | E_ACK | E_START),
 };
 
 enum i2c_reset_cause {
@@ -111,10 +156,10 @@ struct i2c_ch_freq {
 };
 
 static const struct i2c_ch_freq i2c_freq_select[] = {
-	{ 50,   1},
-	{ 100,  2},
-	{ 400,  3},
-	{ 1000, 4},
+	{ 50, 1 },
+	{ 100, 2 },
+	{ 400, 3 },
+	{ 1000, 4 },
 };
 
 struct i2c_pin {
@@ -129,37 +174,30 @@ struct i2c_pin {
 };
 
 static const struct i2c_pin i2c_pin_regs[] = {
-	{ &IT83XX_GPIO_GPCRB3, &IT83XX_GPIO_GPCRB4,
-		&IT83XX_GPIO_GPDRB, &IT83XX_GPIO_GPDRB,
-		&IT83XX_GPIO_GPDMRB, &IT83XX_GPIO_GPDMRB,
-		0x08, 0x10},
-	{ &IT83XX_GPIO_GPCRC1, &IT83XX_GPIO_GPCRC2,
-		&IT83XX_GPIO_GPDRC, &IT83XX_GPIO_GPDRC,
-		&IT83XX_GPIO_GPDMRC, &IT83XX_GPIO_GPDMRC,
-		0x02, 0x04},
+	{ &IT83XX_GPIO_GPCRB3, &IT83XX_GPIO_GPCRB4, &IT83XX_GPIO_GPDRB,
+	  &IT83XX_GPIO_GPDRB, &IT83XX_GPIO_GPDMRB, &IT83XX_GPIO_GPDMRB, 0x08,
+	  0x10 },
+	{ &IT83XX_GPIO_GPCRC1, &IT83XX_GPIO_GPCRC2, &IT83XX_GPIO_GPDRC,
+	  &IT83XX_GPIO_GPDRC, &IT83XX_GPIO_GPDMRC, &IT83XX_GPIO_GPDMRC, 0x02,
+	  0x04 },
 #ifdef CONFIG_IT83XX_SMCLK2_ON_GPC7
-	{ &IT83XX_GPIO_GPCRC7, &IT83XX_GPIO_GPCRF7,
-		&IT83XX_GPIO_GPDRC, &IT83XX_GPIO_GPDRF,
-		&IT83XX_GPIO_GPDMRC, &IT83XX_GPIO_GPDMRF,
-		0x80, 0x80},
+	{ &IT83XX_GPIO_GPCRC7, &IT83XX_GPIO_GPCRF7, &IT83XX_GPIO_GPDRC,
+	  &IT83XX_GPIO_GPDRF, &IT83XX_GPIO_GPDMRC, &IT83XX_GPIO_GPDMRF, 0x80,
+	  0x80 },
 #else
-	{ &IT83XX_GPIO_GPCRF6, &IT83XX_GPIO_GPCRF7,
-		&IT83XX_GPIO_GPDRF, &IT83XX_GPIO_GPDRF,
-		&IT83XX_GPIO_GPDMRF, &IT83XX_GPIO_GPDMRF,
-		0x40, 0x80},
+	{ &IT83XX_GPIO_GPCRF6, &IT83XX_GPIO_GPCRF7, &IT83XX_GPIO_GPDRF,
+	  &IT83XX_GPIO_GPDRF, &IT83XX_GPIO_GPDMRF, &IT83XX_GPIO_GPDMRF, 0x40,
+	  0x80 },
 #endif
-	{ &IT83XX_GPIO_GPCRH1, &IT83XX_GPIO_GPCRH2,
-		&IT83XX_GPIO_GPDRH, &IT83XX_GPIO_GPDRH,
-		&IT83XX_GPIO_GPDMRH, &IT83XX_GPIO_GPDMRH,
-		0x02, 0x04},
-	{ &IT83XX_GPIO_GPCRE0, &IT83XX_GPIO_GPCRE7,
-		&IT83XX_GPIO_GPDRE, &IT83XX_GPIO_GPDRE,
-		&IT83XX_GPIO_GPDMRE, &IT83XX_GPIO_GPDMRE,
-		0x01, 0x80},
-	{ &IT83XX_GPIO_GPCRA4, &IT83XX_GPIO_GPCRA5,
-		&IT83XX_GPIO_GPDRA, &IT83XX_GPIO_GPDRA,
-		&IT83XX_GPIO_GPDMRA, &IT83XX_GPIO_GPDMRA,
-		0x10, 0x20},
+	{ &IT83XX_GPIO_GPCRH1, &IT83XX_GPIO_GPCRH2, &IT83XX_GPIO_GPDRH,
+	  &IT83XX_GPIO_GPDRH, &IT83XX_GPIO_GPDMRH, &IT83XX_GPIO_GPDMRH, 0x02,
+	  0x04 },
+	{ &IT83XX_GPIO_GPCRE0, &IT83XX_GPIO_GPCRE7, &IT83XX_GPIO_GPDRE,
+	  &IT83XX_GPIO_GPDRE, &IT83XX_GPIO_GPDMRE, &IT83XX_GPIO_GPDMRE, 0x01,
+	  0x80 },
+	{ &IT83XX_GPIO_GPCRA4, &IT83XX_GPIO_GPCRA5, &IT83XX_GPIO_GPDRA,
+	  &IT83XX_GPIO_GPDRA, &IT83XX_GPIO_GPDMRA, &IT83XX_GPIO_GPDMRA, 0x10,
+	  0x20 },
 };
 
 struct i2c_ctrl_t {
@@ -169,12 +207,12 @@ struct i2c_ctrl_t {
 };
 
 const struct i2c_ctrl_t i2c_ctrl_regs[] = {
-	{IT83XX_IRQ_SMB_A, CGC_OFFSET_SMBA, -1},
-	{IT83XX_IRQ_SMB_B, CGC_OFFSET_SMBB, -1},
-	{IT83XX_IRQ_SMB_C, CGC_OFFSET_SMBC, -1},
-	{IT83XX_IRQ_SMB_D, CGC_OFFSET_SMBD, 3},
-	{IT83XX_IRQ_SMB_E, CGC_OFFSET_SMBE, 0},
-	{IT83XX_IRQ_SMB_F, CGC_OFFSET_SMBF, 1},
+	{ IT83XX_IRQ_SMB_A, CGC_OFFSET_SMBA, -1 },
+	{ IT83XX_IRQ_SMB_B, CGC_OFFSET_SMBB, -1 },
+	{ IT83XX_IRQ_SMB_C, CGC_OFFSET_SMBC, -1 },
+	{ IT83XX_IRQ_SMB_D, CGC_OFFSET_SMBD, 3 },
+	{ IT83XX_IRQ_SMB_E, CGC_OFFSET_SMBE, 0 },
+	{ IT83XX_IRQ_SMB_F, CGC_OFFSET_SMBF, 1 },
 };
 
 enum i2c_ch_status {
@@ -186,17 +224,17 @@ enum i2c_ch_status {
 
 /* I2C port state data */
 struct i2c_port_data {
-	const uint8_t *out;  /* Output data pointer */
-	int out_size;        /* Output data to transfer, in bytes */
-	uint8_t *in;         /* Input data pointer */
-	int in_size;         /* Input data to transfer, in bytes */
-	int flags;           /* Flags (I2C_XFER_*) */
-	int widx;            /* Index into output data */
-	int ridx;            /* Index into input data */
-	int err;             /* Error code, if any */
-	uint8_t addr_8bit;   /* address of device */
+	const uint8_t *out; /* Output data pointer */
+	int out_size; /* Output data to transfer, in bytes */
+	uint8_t *in; /* Input data pointer */
+	int in_size; /* Input data to transfer, in bytes */
+	int flags; /* Flags (I2C_XFER_*) */
+	int widx; /* Index into output data */
+	int ridx; /* Index into input data */
+	int err; /* Error code, if any */
+	uint8_t addr_8bit; /* address of device */
 	uint32_t timeout_us; /* Transaction timeout, or 0 to use default */
-	uint8_t freq;        /* Frequency setting */
+	uint8_t freq; /* Frequency setting */
 
 	enum i2c_ch_status i2ccs;
 	/* Task waiting on port, or TASK_ID_INVALID if none. */
@@ -284,9 +322,9 @@ static void i2c_pio_trans_data(int p, enum enhanced_i2c_transfer_direct direct,
 	p_ch = i2c_ch_reg_shift(p);
 
 	if (first_byte) {
-		/* First byte must be slave address. */
-		IT83XX_I2C_DTR(p_ch) =
-			data | (direct == RX_DIRECT ? BIT(0) : 0);
+		/* First byte must be peripheral address. */
+		IT83XX_I2C_DTR(p_ch) = data |
+				       (direct == RX_DIRECT ? BIT(0) : 0);
 		/* start or repeat start signal. */
 		IT83XX_I2C_CTR(p_ch) = E_START_ID;
 	} else {
@@ -299,12 +337,12 @@ static void i2c_pio_trans_data(int p, enum enhanced_i2c_transfer_direct direct,
 			 * Last byte should be NACK in the end of read cycle
 			 */
 			if (((pd->ridx + 1) == pd->in_size) &&
-				(pd->flags & I2C_XFER_STOP))
+			    (pd->flags & I2C_XFER_STOP))
 				nack = 1;
 		}
 		/* Set hardware reset to start next transmission */
-		IT83XX_I2C_CTR(p_ch) =
-			E_INT_EN | E_MODE_SEL | E_HW_RST | (nack ? 0 : E_ACK);
+		IT83XX_I2C_CTR(p_ch) = E_INT_EN | E_MODE_SEL | E_HW_RST |
+				       (nack ? 0 : E_ACK);
 	}
 }
 
@@ -317,7 +355,7 @@ static int i2c_tran_write(int p)
 		IT83XX_SMB_HOCTL2(p) = 0x13;
 		/*
 		 * bit0, Direction of the host transfer.
-		 * bit[1:7}, Address of the targeted slave.
+		 * bit[1:7}, Address of the targeted peripheral.
 		 */
 		IT83XX_SMB_TRASLA(p) = pd->addr_8bit;
 		/* Send first byte */
@@ -377,7 +415,7 @@ static int i2c_tran_read(int p)
 		IT83XX_SMB_HOCTL2(p) = 0x13;
 		/*
 		 * bit0, Direction of the host transfer.
-		 * bit[1:7}, Address of the targeted slave.
+		 * bit[1:7}, Address of the targeted peripheral.
 		 */
 		IT83XX_SMB_TRASLA(p) = pd->addr_8bit | 0x01;
 		/* clear start flag */
@@ -395,7 +433,7 @@ static int i2c_tran_read(int p)
 			IT83XX_SMB_HOCTL(p) = 0x5D;
 	} else {
 		if ((pd->i2ccs == I2C_CH_REPEAT_START) ||
-			(pd->i2ccs == I2C_CH_WAIT_READ)) {
+		    (pd->i2ccs == I2C_CH_WAIT_READ)) {
 			if (pd->i2ccs == I2C_CH_REPEAT_START) {
 				/* write to read */
 				i2c_w2r_change_direction(p);
@@ -488,8 +526,8 @@ static int enhanced_i2c_tran_write(int p)
 				/* Write to read protocol */
 				pd->i2ccs = I2C_CH_REPEAT_START;
 				/* Repeat Start */
-				i2c_pio_trans_data(p, RX_DIRECT,
-						   pd->addr_8bit, 1);
+				i2c_pio_trans_data(p, RX_DIRECT, pd->addr_8bit,
+						   1);
 			} else {
 				if (pd->flags & I2C_XFER_STOP) {
 					IT83XX_I2C_CTR(p_ch) = E_FINISH;
@@ -538,8 +576,8 @@ static int enhanced_i2c_tran_read(int p)
 				/* Write to read */
 				pd->i2ccs = I2C_CH_WAIT_READ;
 				/* Send ID */
-				i2c_pio_trans_data(p, RX_DIRECT,
-						   pd->addr_8bit, 1);
+				i2c_pio_trans_data(p, RX_DIRECT, pd->addr_8bit,
+						   1);
 				task_enable_irq(i2c_ctrl_regs[p].irq);
 			}
 		} else {
@@ -578,7 +616,7 @@ static int enhanced_i2c_error(int p)
 
 	if (i2c_str & E_HOSTA_ANY_ERROR) {
 		pd->err = i2c_str & E_HOSTA_ANY_ERROR;
-	/* device does not respond ACK */
+		/* device does not respond ACK */
 	} else if ((i2c_str & E_HOSTA_BDS_AND_ACK) == E_HOSTA_BDS) {
 		if (IT83XX_I2C_CTR(p_ch) & E_ACK)
 			pd->err = E_HOSTA_ACK;
@@ -587,11 +625,199 @@ static int enhanced_i2c_error(int p)
 	return pd->err;
 }
 
-static int i2c_transaction(int p)
+#ifdef CONFIG_IT83XX_I2C_CMD_QUEUE
+static void enhanced_i2c_set_cmd_addr_regs(int p)
+{
+	int dlm_index = p - I2C_STANDARD_PORT_COUNT;
+	int p_ch = i2c_ch_reg_shift(p);
+	uint32_t dlm_base;
+
+	/* set "Address Register" to store the I2C data */
+	dlm_base = (uint32_t)&i2c_cq_mode_rx_dlm[dlm_index] & 0xffffff;
+	IT83XX_I2C_RAMH2A(p_ch) = (dlm_base >> 16) & 0xff;
+	IT83XX_I2C_RAMHA(p_ch) = (dlm_base >> 8) & 0xff;
+	IT83XX_I2C_RAMLA(p_ch) = dlm_base & 0xff;
+
+	/* Set "Command Address Register" to get commands */
+	dlm_base = (uint32_t)&i2c_cq_mode_tx_dlm[dlm_index] & 0xffffff;
+	IT83XX_I2C_CMD_ADDH2(p_ch) = (dlm_base >> 16) & 0xff;
+	IT83XX_I2C_CMD_ADDH(p_ch) = (dlm_base >> 8) & 0xff;
+	IT83XX_I2C_CMD_ADDL(p_ch) = dlm_base & 0xff;
+}
+
+static void i2c_enable_idle(int port)
+{
+	i2c_idle_disabled &= ~BIT(port);
+}
+
+static void i2c_disable_idle(int port)
+{
+	i2c_idle_disabled |= BIT(port);
+}
+
+uint32_t i2c_idle_not_allowed(void)
+{
+	return i2c_idle_disabled;
+}
+
+static int command_i2c_idle_mask(int argc, const char **argv)
+{
+	ccprintf("i2c idle mask: %08x\n", i2c_idle_disabled);
+
+	return EC_SUCCESS;
+}
+DECLARE_SAFE_CONSOLE_COMMAND(i2cidlemask, command_i2c_idle_mask, NULL,
+			     "Display i2c idle mask");
+
+static void enhanced_i2c_cq_write(int p)
+{
+	struct i2c_port_data *pd = pdata + p;
+	struct i2c_cq_packet *i2c_cq_pckt;
+	uint8_t num_bit_2_0 = (pd->out_size - 1) & I2C_CQ_CMD_L_NUM_BIT_2_0;
+	uint8_t num_bit_10_3 = ((pd->out_size - 1) >> 3) & 0xff;
+	int dlm_index = p - I2C_STANDARD_PORT_COUNT;
+
+	i2c_cq_pckt = (struct i2c_cq_packet *)&i2c_cq_mode_tx_dlm[dlm_index];
+	/* Set commands in RAM. */
+	i2c_cq_pckt->id = pd->addr_8bit;
+	i2c_cq_pckt->cmd_l = I2C_CQ_CMD_L_P | I2C_CQ_CMD_L_E | num_bit_2_0;
+	i2c_cq_pckt->cmd_h = num_bit_10_3;
+	for (int i = 0; i < pd->out_size; i++)
+		i2c_cq_pckt->wdata[i] = pd->out[i];
+}
+
+static void enhanced_i2c_cq_read(int p)
+{
+	struct i2c_port_data *pd = pdata + p;
+	struct i2c_cq_packet *i2c_cq_pckt;
+	uint8_t num_bit_2_0 = (pd->in_size - 1) & I2C_CQ_CMD_L_NUM_BIT_2_0;
+	uint8_t num_bit_10_3 = ((pd->in_size - 1) >> 3) & 0xff;
+	int dlm_index = p - I2C_STANDARD_PORT_COUNT;
+
+	i2c_cq_pckt = (struct i2c_cq_packet *)&i2c_cq_mode_tx_dlm[dlm_index];
+	/* Set commands in RAM. */
+	i2c_cq_pckt->id = pd->addr_8bit;
+	i2c_cq_pckt->cmd_l = I2C_CQ_CMD_L_RW | I2C_CQ_CMD_L_P | I2C_CQ_CMD_L_E |
+			     num_bit_2_0;
+	i2c_cq_pckt->cmd_h = num_bit_10_3;
+}
+
+static void enhanced_i2c_cq_write_to_read(int p)
+{
+	struct i2c_port_data *pd = pdata + p;
+	struct i2c_cq_packet *i2c_cq_pckt;
+	uint8_t num_bit_2_0 = (pd->out_size - 1) & I2C_CQ_CMD_L_NUM_BIT_2_0;
+	uint8_t num_bit_10_3 = ((pd->out_size - 1) >> 3) & 0xff;
+	int dlm_index = p - I2C_STANDARD_PORT_COUNT;
+	int i;
+
+	i2c_cq_pckt = (struct i2c_cq_packet *)&i2c_cq_mode_tx_dlm[dlm_index];
+	/* Set commands in RAM. (command byte for write) */
+	i2c_cq_pckt->id = pd->addr_8bit;
+	i2c_cq_pckt->cmd_l = num_bit_2_0;
+	i2c_cq_pckt->cmd_h = num_bit_10_3;
+	for (i = 0; i < pd->out_size; i++)
+		i2c_cq_pckt->wdata[i] = pd->out[i];
+	/* Set commands in RAM. (command byte for read) */
+	num_bit_2_0 = (pd->in_size - 1) & I2C_CQ_CMD_L_NUM_BIT_2_0;
+	num_bit_10_3 = ((pd->in_size - 1) >> 3) & 0xff;
+	i2c_cq_pckt->wdata[i++] = I2C_CQ_CMD_L_RS | I2C_CQ_CMD_L_RW |
+				  I2C_CQ_CMD_L_P | I2C_CQ_CMD_L_E | num_bit_2_0;
+	i2c_cq_pckt->wdata[i] = num_bit_10_3;
+}
+
+static int enhanced_i2c_cmd_queue_trans(int p)
+{
+	struct i2c_port_data *pd = pdata + p;
+	int p_ch = i2c_ch_reg_shift(p);
+	int dlm_index = p - I2C_STANDARD_PORT_COUNT;
+
+	/* ISR of command queue mode */
+	if (in_interrupt_context()) {
+		/* device 1 finish IRQ */
+		if (IT83XX_I2C_FST(p_ch) & IT83XX_I2C_FST_DEV1_IRQ) {
+			/* get data if this is a read transaction */
+			for (int i = 0; i < pd->in_size; i++)
+				pd->in[i] = i2c_cq_mode_rx_dlm[dlm_index][i];
+		} else {
+			/* device 1 error have occurred. eg. nack, timeout... */
+			if (IT83XX_I2C_NST(p_ch) & IT83XX_I2C_NST_ID_NACK)
+				pd->err = E_HOSTA_ACK;
+			else
+				pd->err = IT83XX_I2C_STR(p_ch) &
+					  E_HOSTA_ANY_ERROR;
+		}
+		/* reset bus */
+		IT83XX_I2C_CTR(p_ch) = E_STS_AND_HW_RST;
+		IT83XX_I2C_CTR1(p_ch) = 0;
+
+		return 0;
+	}
+
+	if ((pd->out_size > I2C_CQ_MODE_TX_MAX_PAYLOAD_SIZE) ||
+	    (pd->in_size > I2C_CQ_MODE_MAX_PAYLOAD_SIZE)) {
+		pd->err = EC_ERROR_INVAL;
+		return 0;
+	}
+
+	/* State reset and hardware reset */
+	IT83XX_I2C_CTR(p_ch) = E_STS_AND_HW_RST;
+	/* Set "PSR" registers to decide the i2c speed. */
+	IT83XX_I2C_PSR(p_ch) = pdata[p].freq;
+	IT83XX_I2C_HSPR(p_ch) = pdata[p].freq;
+	/* Set time out register. port D, E, or F clock/data low timeout. */
+	IT83XX_I2C_TOR(p_ch) = I2C_CLK_LOW_TIMEOUT;
+
+	/* i2c write to read */
+	if (pd->out_size && pd->in_size)
+		enhanced_i2c_cq_write_to_read(p);
+	/* i2c write */
+	else if (pd->out_size)
+		enhanced_i2c_cq_write(p);
+	/* i2c read */
+	else if (pd->in_size)
+		enhanced_i2c_cq_read(p);
+
+	/* enable i2c module with command queue mode */
+	IT83XX_I2C_CTR1(p_ch) = IT83XX_I2C_MDL_EN | IT83XX_I2C_COMQ_EN;
+	/* one shot on device 1 */
+	IT83XX_I2C_MODE_SEL(p_ch) = 0;
+	IT83XX_I2C_CTR2(p_ch) = 1;
+	/* start */
+	i2c_disable_idle(p);
+	IT83XX_I2C_CTR(p_ch) = E_START_CQ;
+
+	return 0;
+}
+#endif /* CONFIG_IT83XX_I2C_CMD_QUEUE */
+
+static int enhanced_i2c_pio_trans(int p)
 {
 	struct i2c_port_data *pd = pdata + p;
 	int p_ch;
 
+	/* no error */
+	if (!(enhanced_i2c_error(p))) {
+		/* i2c write */
+		if (pd->out_size)
+			return enhanced_i2c_tran_write(p);
+		/* i2c read */
+		else if (pd->in_size)
+			return enhanced_i2c_tran_read(p);
+	}
+
+	p_ch = i2c_ch_reg_shift(p);
+	IT83XX_I2C_CTR(p_ch) = E_STS_AND_HW_RST;
+	IT83XX_I2C_CTR1(p_ch) = 0;
+
+	return 0;
+}
+
+static int i2c_transaction(int p)
+{
+	struct i2c_port_data *pd = pdata + p;
+	int ret;
+
 	if (p < I2C_STANDARD_PORT_COUNT) {
 		/* any error */
 		if (IT83XX_SMB_HOSTA(p) & HOSTA_ANY_ERROR) {
@@ -612,18 +838,13 @@ static int i2c_transaction(int p)
 		/* disable the SMBus host interface */
 		IT83XX_SMB_HOCTL2(p) = 0x00;
 	} else {
-		/* no error */
-		if (!(enhanced_i2c_error(p))) {
-			/* i2c write */
-			if (pd->out_size)
-				return enhanced_i2c_tran_write(p);
-			/* i2c read */
-			else if (pd->in_size)
-				return enhanced_i2c_tran_read(p);
-		}
-		p_ch = i2c_ch_reg_shift(p);
-		IT83XX_I2C_CTR(p_ch) = E_STS_AND_HW_RST;
-		IT83XX_I2C_CTR1(p_ch) = 0;
+#ifdef CONFIG_IT83XX_I2C_CMD_QUEUE
+		if (pd->flags == I2C_XFER_SINGLE)
+			ret = enhanced_i2c_cmd_queue_trans(p);
+		else
+#endif
+			ret = enhanced_i2c_pio_trans(p);
+		return ret;
 	}
 	/* done doing work */
 	return 0;
@@ -641,9 +862,8 @@ int i2c_is_busy(int port)
 	return (IT83XX_I2C_STR(p_ch) & E_HOSTA_BB);
 }
 
-int chip_i2c_xfer(int port, uint16_t slave_addr_flags,
-		  const uint8_t *out, int out_size,
-		  uint8_t *in, int in_size, int flags)
+int chip_i2c_xfer(int port, uint16_t addr_flags, const uint8_t *out,
+		  int out_size, uint8_t *in, int in_size, int flags)
 {
 	struct i2c_port_data *pd = pdata + port;
 	uint32_t events = 0;
@@ -651,10 +871,15 @@ int chip_i2c_xfer(int port, uint16_t slave_addr_flags,
 	if (out_size == 0 && in_size == 0)
 		return EC_SUCCESS;
 
-	if (pd->i2ccs) {
-		if ((flags & I2C_XFER_SINGLE) == I2C_XFER_SINGLE)
-			flags &= ~I2C_XFER_START;
-	}
+	/*
+	 * Make the below i2c transaction work:
+	 * - i2c_xfer with I2C_XFER_START flag
+	 * - i2c_xfer with I2C_XFER_START flag
+	 * - xxx
+	 * - i2c_xfer with I2C_XFER_STOP flag
+	 */
+	if (pd->i2ccs)
+		flags &= ~I2C_XFER_START;
 
 	/* Copy data to port struct */
 	pd->out = out;
@@ -665,12 +890,12 @@ int chip_i2c_xfer(int port, uint16_t slave_addr_flags,
 	pd->widx = 0;
 	pd->ridx = 0;
 	pd->err = 0;
-	pd->addr_8bit = I2C_GET_ADDR(slave_addr_flags) << 1;
+	pd->addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1;
 
 	/* Make sure we're in a good state to start */
-	if ((flags & I2C_XFER_START) && (i2c_is_busy(port)
-		|| (i2c_get_line_levels(port) != I2C_LINE_IDLE))) {
-
+	if ((flags & I2C_XFER_START) &&
+	    (i2c_is_busy(port) ||
+	     (i2c_get_line_levels(port) != I2C_LINE_IDLE))) {
 		/* Attempt to unwedge the port. */
 		pd->err = i2c_unwedge(port);
 
@@ -708,6 +933,10 @@ int chip_i2c_xfer(int port, uint16_t slave_addr_flags,
 	if (pd->err)
 		pd->i2ccs = I2C_CH_NORMAL;
 
+#ifdef CONFIG_IT83XX_I2C_CMD_QUEUE
+	i2c_enable_idle(port);
+#endif
+
 	return pd->err;
 }
 
@@ -717,7 +946,7 @@ int i2c_raw_get_scl(int port)
 
 	if (get_scl_from_i2c_port(port, &g) == EC_SUCCESS)
 		return !!(*i2c_pin_regs[port].mirror_clk &
-			i2c_pin_regs[port].clk_mask);
+			  i2c_pin_regs[port].clk_mask);
 
 	/* If no SCL pin defined for this port, then return 1 to appear idle */
 	return 1;
@@ -729,7 +958,7 @@ int i2c_raw_get_sda(int port)
 
 	if (get_sda_from_i2c_port(port, &g) == EC_SUCCESS)
 		return !!(*i2c_pin_regs[port].mirror_data &
-			i2c_pin_regs[port].data_mask);
+			  i2c_pin_regs[port].data_mask);
 
 	/* If no SDA pin defined for this port, then return 1 to appear idle */
 	return 1;
@@ -769,7 +998,7 @@ void i2c_interrupt(int port)
 	/* If done doing work, wake up the task waiting for the transfer */
 	if (!i2c_transaction(port)) {
 		task_disable_irq(i2c_ctrl_regs[port].irq);
-		task_set_event(id, TASK_EVENT_I2C_IDLE, 0);
+		task_set_event(id, TASK_EVENT_I2C_IDLE);
 	}
 }
 
@@ -782,8 +1011,8 @@ static void i2c_standard_port_timing_regs_400khz(int port)
 	/* Port clock frequency depends on setting of timing registers. */
 	IT83XX_SMB_SCLKTS(port) = 0;
 	/* Suggested setting of timing registers of 400kHz. */
-	IT83XX_SMB_4P7USL = 0x5;
-	IT83XX_SMB_4P0USL = 0x1;
+	IT83XX_SMB_4P7USL = 0x6;
+	IT83XX_SMB_4P0USL = 0;
 	IT83XX_SMB_300NS = 0x1;
 	IT83XX_SMB_250NS = 0x2;
 	IT83XX_SMB_45P3USL = 0x6a;
@@ -805,7 +1034,7 @@ static void i2c_standard_port_set_frequency(int port, int freq_khz)
 		for (int f = ARRAY_SIZE(i2c_freq_select) - 1; f >= 0; f--) {
 			if (freq_khz >= i2c_freq_select[f].kbps) {
 				IT83XX_SMB_SCLKTS(port) =
-						i2c_freq_select[f].freq_set;
+					i2c_freq_select[f].freq_set;
 				break;
 			}
 		}
@@ -907,10 +1136,10 @@ void i2c_init(void)
 			p_ch = i2c_ch_reg_shift(p);
 			switch (p) {
 			case IT83XX_I2C_CH_D:
-				#ifndef CONFIG_UART_HOST
+#ifndef CONFIG_UART_HOST
 				/* Enable SMBus D channel */
 				IT83XX_GPIO_GRC2 |= 0x20;
-				#endif
+#endif
 				break;
 			case IT83XX_I2C_CH_E:
 				/* Enable SMBus E channel */
@@ -928,6 +1157,10 @@ void i2c_init(void)
 			IT83XX_I2C_CTR(p_ch) = E_STS_AND_HW_RST;
 			/* bit1, Module enable */
 			IT83XX_I2C_CTR1(p_ch) = 0;
+#ifdef CONFIG_IT83XX_I2C_CMD_QUEUE
+			/* set command address registers */
+			enhanced_i2c_set_cmd_addr_regs(p);
+#endif
 		}
 		pdata[i].task_waiting = TASK_ID_INVALID;
 	}
diff --git a/chip/it83xx/i2c_peripheral.c b/chip/it83xx/i2c_peripheral.c
new file mode 100644
index 0000000000..dfb139514f
--- /dev/null
+++ b/chip/it83xx/i2c_peripheral.c
@@ -0,0 +1,356 @@
+/* Copyright 2019 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* I2C module for Chrome EC */
+#include "clock.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "i2c_peripheral.h"
+#include "printf.h"
+#include "registers.h"
+#include "task.h"
+
+#include <stddef.h>
+#include <string.h>
+
+/* Console output macros */
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
+
+/* The size must be a power of 2 */
+#define I2C_MAX_BUFFER_SIZE 0x100
+#define I2C_SIZE_MASK (I2C_MAX_BUFFER_SIZE - 1)
+
+#define I2C_READ_MAXFIFO_DATA 16
+#define I2C_ENHANCED_CH_INTERVAL 0x80
+
+/* Store controller to peripheral data of channel D, E, F by DMA */
+static uint8_t in_data[I2C_ENHANCED_PORT_COUNT][I2C_MAX_BUFFER_SIZE]
+	__attribute__((section(".h2ram.pool.i2cslv")));
+/* Store peripheral to controller data of channel D, E, F by DMA */
+static uint8_t out_data[I2C_ENHANCED_PORT_COUNT][I2C_MAX_BUFFER_SIZE]
+	__attribute__((section(".h2ram.pool.i2cslv")));
+/* Store read and write data of channel A by FIFO mode */
+static uint8_t pbuffer[I2C_MAX_BUFFER_SIZE];
+
+static uint32_t w_index;
+static uint32_t r_index;
+static int wr_done[I2C_ENHANCED_PORT_COUNT];
+
+void buffer_index_reset(void)
+{
+	/* Reset write buffer index */
+	w_index = 0;
+	/* Reset read buffer index */
+	r_index = 0;
+}
+
+/* Data structure to define I2C peripheral control configuration. */
+struct i2c_periph_ctrl_t {
+	int irq; /* peripheral irq */
+	/* offset from base 0x00F03500 register; -1 means unused. */
+	int offset;
+	enum clock_gate_offsets clock_gate;
+	int dma_index;
+};
+
+/* I2C peripheral control */
+const struct i2c_periph_ctrl_t i2c_periph_ctrl[] = {
+	[IT83XX_I2C_CH_A] = { .irq = IT83XX_IRQ_SMB_A,
+			      .offset = -1,
+			      .clock_gate = CGC_OFFSET_SMBA,
+			      .dma_index = -1 },
+	[IT83XX_I2C_CH_D] = { .irq = IT83XX_IRQ_SMB_D,
+			      .offset = 0x180,
+			      .clock_gate = CGC_OFFSET_SMBD,
+			      .dma_index = 0 },
+	[IT83XX_I2C_CH_E] = { .irq = IT83XX_IRQ_SMB_E,
+			      .offset = 0x0,
+			      .clock_gate = CGC_OFFSET_SMBE,
+			      .dma_index = 1 },
+	[IT83XX_I2C_CH_F] = { .irq = IT83XX_IRQ_SMB_F,
+			      .offset = 0x80,
+			      .clock_gate = CGC_OFFSET_SMBF,
+			      .dma_index = 2 },
+};
+
+void i2c_peripheral_read_write_data(int port)
+{
+	int periph_status, i;
+
+	/* I2C peripheral channel A FIFO mode */
+	if (port < I2C_STANDARD_PORT_COUNT) {
+		int count;
+
+		periph_status = IT83XX_SMB_SLSTA;
+
+		/* bit0-4 : FIFO byte count */
+		count = IT83XX_SMB_SFFSTA & 0x1F;
+
+		/* Peripheral data register is waiting for read or write. */
+		if (periph_status & IT83XX_SMB_SDS) {
+			/* Controller to read data */
+			if (periph_status & IT83XX_SMB_RCS) {
+				for (i = 0; i < I2C_READ_MAXFIFO_DATA; i++)
+					/* Return buffer data to controller */
+					IT83XX_SMB_SLDA =
+						pbuffer[(i + r_index) &
+							I2C_SIZE_MASK];
+
+				/* Index to next 16 bytes of read buffer */
+				r_index += I2C_READ_MAXFIFO_DATA;
+			}
+			/* Controller to write data */
+			else {
+				/* FIFO Full */
+				if (IT83XX_SMB_SFFSTA & IT83XX_SMB_SFFFULL) {
+					for (i = 0; i < count; i++)
+						/* Get data from controller to
+						 * buffer */
+						pbuffer[(w_index + i) &
+							I2C_SIZE_MASK] =
+							IT83XX_SMB_SLDA;
+				}
+
+				/* Index to next byte of write buffer */
+				w_index += count;
+			}
+		}
+		/* Stop condition, indicate stop condition detected. */
+		if (periph_status & IT83XX_SMB_SPDS) {
+			/* Read data less 16 bytes status */
+			if (periph_status & IT83XX_SMB_RCS) {
+				/* Disable FIFO mode to clear left count */
+				IT83XX_SMB_SFFCTL &= ~IT83XX_SMB_SAFE;
+
+				/* Peripheral A FIFO Enable */
+				IT83XX_SMB_SFFCTL |= IT83XX_SMB_SAFE;
+			}
+			/* Controller to write data */
+			else {
+				for (i = 0; i < count; i++)
+					/* Get data from controller to buffer */
+					pbuffer[(i + w_index) & I2C_SIZE_MASK] =
+						IT83XX_SMB_SLDA;
+			}
+
+			/* Reset read and write buffer index */
+			buffer_index_reset();
+		}
+		/* Peripheral time status, timeout status occurs. */
+		if (periph_status & IT83XX_SMB_STS) {
+			/* Reset read and write buffer index */
+			buffer_index_reset();
+		}
+
+		/* Write clear the peripheral status */
+		IT83XX_SMB_SLSTA = periph_status;
+	}
+	/* Enhanced I2C peripheral channel D, E, F DMA mode */
+	else {
+		int ch, idx;
+
+		/* Get enhanced i2c channel */
+		ch = i2c_periph_ctrl[port].offset / I2C_ENHANCED_CH_INTERVAL;
+
+		idx = i2c_periph_ctrl[port].dma_index;
+
+		/* Interrupt pending */
+		if (IT83XX_I2C_STR(ch) & IT83XX_I2C_INTPEND) {
+			periph_status = IT83XX_I2C_IRQ_ST(ch);
+
+			/* Controller to read data */
+			if (periph_status & IT83XX_I2C_IDR_CLR) {
+				/*
+				 * TODO(b:129360157): Return buffer data by
+				 * "out_data" array.
+				 * Ex: Write data to buffer from 0x00 to 0xFF
+				 */
+				for (i = 0; i < I2C_MAX_BUFFER_SIZE; i++)
+					out_data[idx][i] = i;
+			}
+			/* Controller to write data */
+			if (periph_status & IT83XX_I2C_IDW_CLR) {
+				/* Controller to write data finish flag */
+				wr_done[idx] = 1;
+			}
+			/* Peripheral finish */
+			if (periph_status & IT83XX_I2C_P_CLR) {
+				if (wr_done[idx]) {
+					char str_buf[hex_str_buf_size(
+						I2C_MAX_BUFFER_SIZE)];
+					/*
+					 * TODO(b:129360157): Handle controller
+					 * write data by "in_data" array.
+					 */
+					snprintf_hex_buffer(
+						str_buf, sizeof(str_buf),
+						HEX_BUF(in_data[idx],
+							I2C_MAX_BUFFER_SIZE));
+					CPRINTS("WData: %s", str_buf);
+					wr_done[idx] = 0;
+				}
+			}
+
+			/* Write clear the peripheral status */
+			IT83XX_I2C_IRQ_ST(ch) = periph_status;
+		}
+
+		/* Hardware reset */
+		IT83XX_I2C_CTR(ch) |= IT83XX_I2C_HALT;
+	}
+}
+
+void i2c_periph_interrupt(int port)
+{
+	/* Peripheral to read and write fifo data */
+	i2c_peripheral_read_write_data(port);
+
+	/* Clear the interrupt status */
+	task_clear_pending_irq(i2c_periph_ctrl[port].irq);
+}
+
+void i2c_peripheral_enable(int port, uint8_t periph_addr)
+{
+	clock_enable_peripheral(i2c_periph_ctrl[port].clock_gate, 0, 0);
+
+	/* I2C peripheral channel A FIFO mode */
+	if (port < I2C_STANDARD_PORT_COUNT) {
+		/* This field defines the SMCLK0/1/2 clock/data low timeout. */
+		IT83XX_SMB_25MS = I2C_CLK_LOW_TIMEOUT;
+
+		/* bit0 : Peripheral A FIFO Enable */
+		IT83XX_SMB_SFFCTL |= IT83XX_SMB_SAFE;
+
+		/*
+		 * bit1 : Peripheral interrupt enable.
+		 * bit2 : SMCLK/SMDAT will be released if timeout.
+		 * bit3 : Peripheral detect STOP condition interrupt enable.
+		 */
+		IT83XX_SMB_SICR = 0x0E;
+
+		/* Peripheral address 1 */
+		IT83XX_SMB_RESLADR = periph_addr;
+
+		/* Write clear all peripheral status */
+		IT83XX_SMB_SLSTA = 0xE7;
+
+		/* bit5 : Enable the SMBus peripheral device */
+		IT83XX_SMB_HOCTL2(port) |= IT83XX_SMB_SLVEN;
+	}
+	/* Enhanced I2C peripheral channel D, E, F DMA mode */
+	else {
+		int ch, idx;
+		uint32_t in_data_addr, out_data_addr;
+
+		/* Get enhanced i2c channel */
+		ch = i2c_periph_ctrl[port].offset / I2C_ENHANCED_CH_INTERVAL;
+
+		idx = i2c_periph_ctrl[port].dma_index;
+
+		switch (port) {
+		case IT83XX_I2C_CH_D:
+			/* Enable I2C D channel */
+			IT83XX_GPIO_GRC2 |= (1 << 5);
+			break;
+		case IT83XX_I2C_CH_E:
+			/* Enable I2C E channel */
+			IT83XX_GCTRL_PMER1 |= (1 << 0);
+			break;
+		case IT83XX_I2C_CH_F:
+			/* Enable I2C F channel */
+			IT83XX_GCTRL_PMER1 |= (1 << 1);
+			break;
+		}
+
+		/* Software reset */
+		IT83XX_I2C_DHTR(ch) |= (1 << 7);
+		IT83XX_I2C_DHTR(ch) &= ~(1 << 7);
+
+		/* This field defines the SMCLK3/4/5 clock/data low timeout. */
+		IT83XX_I2C_TOR(ch) = I2C_CLK_LOW_TIMEOUT;
+
+		/* Bit stretching */
+		IT83XX_I2C_TOS(ch) |= IT83XX_I2C_CLK_STR;
+
+		/* Peripheral address(8-bit)*/
+		IT83XX_I2C_IDR(ch) = periph_addr << 1;
+
+		/* I2C interrupt enable and set acknowledge */
+		IT83XX_I2C_CTR(ch) = IT83XX_I2C_HALT | IT83XX_I2C_INTEN |
+				     IT83XX_I2C_ACK;
+
+		/*
+		 * bit3 : Peripheral ID write flag
+		 * bit2 : Peripheral ID read flag
+		 * bit1 : Peripheral received data flag
+		 * bit0 : Peripheral finish
+		 */
+		IT83XX_I2C_IRQ_ST(ch) = 0xFF;
+
+		/* Clear read and write data buffer of DMA */
+		memset(in_data[idx], 0, I2C_MAX_BUFFER_SIZE);
+		memset(out_data[idx], 0, I2C_MAX_BUFFER_SIZE);
+
+		if (IS_ENABLED(CHIP_ILM_DLM_ORDER)) {
+			in_data_addr = (uint32_t)in_data[idx] & 0xffffff;
+			out_data_addr = (uint32_t)out_data[idx] & 0xffffff;
+		} else {
+			in_data_addr = (uint32_t)in_data[idx] & 0xfff;
+			out_data_addr = (uint32_t)out_data[idx] & 0xfff;
+		}
+
+		/* DMA write target address register */
+		IT83XX_I2C_RAMHA(ch) = in_data_addr >> 8;
+		IT83XX_I2C_RAMLA(ch) = in_data_addr;
+
+		if (IS_ENABLED(CHIP_ILM_DLM_ORDER)) {
+			/*
+			 * DMA write target address register
+			 * for high order byte
+			 */
+			IT83XX_I2C_RAMH2A(ch) = in_data_addr >> 16;
+			/*
+			 * DMA read target address register
+			 * for high order byte
+			 */
+			IT83XX_I2C_CMD_ADDH2(ch) = out_data_addr >> 16;
+			IT83XX_I2C_CMD_ADDH(ch) = out_data_addr >> 8;
+			IT83XX_I2C_CMD_ADDL(ch) = out_data_addr;
+		} else {
+			/* DMA read target address register */
+			IT83XX_I2C_RAMHA2(ch) = out_data_addr >> 8;
+			IT83XX_I2C_RAMLA2(ch) = out_data_addr;
+		}
+
+		/* I2C module enable and command queue mode */
+		IT83XX_I2C_CTR1(ch) = IT83XX_I2C_COMQ_EN | IT83XX_I2C_MDL_EN;
+	}
+}
+
+static void i2c_peripheral_init(void)
+{
+	int i, p;
+
+	/* DLM 52k~56k size select enable */
+	IT83XX_GCTRL_MCCR2 |= (1 << 4);
+
+	/* Enable I2C Peripheral function */
+	for (i = 0; i < i2c_periphs_used; i++) {
+		/* I2c peripheral port mapping. */
+		p = i2c_periph_ports[i].port;
+
+		/* To enable peripheral ch[x] */
+		i2c_peripheral_enable(p, i2c_periph_ports[i].addr);
+
+		/* Clear the interrupt status */
+		task_clear_pending_irq(i2c_periph_ctrl[p].irq);
+
+		/* enable i2c interrupt */
+		task_enable_irq(i2c_periph_ctrl[p].irq);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, i2c_peripheral_init, HOOK_PRIO_POST_I2C);
diff --git a/chip/it83xx/i2c_slave.c b/chip/it83xx/i2c_slave.c
deleted file mode 100644
index adfa794d77..0000000000
--- a/chip/it83xx/i2c_slave.c
+++ /dev/null
@@ -1,345 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* I2C module for Chrome EC */
-
-#include "clock.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c_slave.h"
-#include "registers.h"
-#include <stddef.h>
-#include <string.h>
-#include "task.h"
-
-/* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-
-/* The size must be a power of 2 */
-#define I2C_MAX_BUFFER_SIZE 0x100
-#define I2C_SIZE_MASK (I2C_MAX_BUFFER_SIZE - 1)
-
-#define I2C_READ_MAXFIFO_DATA 16
-#define I2C_ENHANCED_CH_INTERVAL 0x80
-
-/* Store master to slave data of channel D, E, F by DMA */
-static uint8_t in_data[I2C_ENHANCED_PORT_COUNT][I2C_MAX_BUFFER_SIZE]
-			__attribute__((section(".h2ram.pool.i2cslv")));
-/* Store slave to master data of channel D, E, F by DMA */
-static uint8_t out_data[I2C_ENHANCED_PORT_COUNT][I2C_MAX_BUFFER_SIZE]
-			__attribute__((section(".h2ram.pool.i2cslv")));
-/* Store read and write data of channel A by FIFO mode */
-static uint8_t pbuffer[I2C_MAX_BUFFER_SIZE];
-
-static uint32_t w_index;
-static uint32_t r_index;
-static int wr_done[I2C_ENHANCED_PORT_COUNT];
-
-void buffer_index_reset(void)
-{
-	/* Reset write buffer index */
-	w_index = 0;
-	/* Reset read buffer index */
-	r_index = 0;
-}
-
-/* Data structure to define I2C slave control configuration. */
-struct i2c_slv_ctrl_t {
-	int irq;              /* slave irq */
-	/* offset from base 0x00F03500 register; -1 means unused. */
-	int offset;
-	enum clock_gate_offsets clock_gate;
-	int dma_index;
-};
-
-/* I2C slave control */
-const struct i2c_slv_ctrl_t i2c_slv_ctrl[] = {
-	[IT83XX_I2C_CH_A] = {.irq = IT83XX_IRQ_SMB_A, .offset = -1,
-		.clock_gate = CGC_OFFSET_SMBA, .dma_index = -1},
-	[IT83XX_I2C_CH_D] = {.irq = IT83XX_IRQ_SMB_D, .offset = 0x180,
-		.clock_gate = CGC_OFFSET_SMBD, .dma_index = 0},
-	[IT83XX_I2C_CH_E] = {.irq = IT83XX_IRQ_SMB_E, .offset = 0x0,
-		.clock_gate = CGC_OFFSET_SMBE, .dma_index = 1},
-	[IT83XX_I2C_CH_F] = {.irq = IT83XX_IRQ_SMB_F, .offset = 0x80,
-		.clock_gate = CGC_OFFSET_SMBF, .dma_index = 2},
-};
-
-void i2c_slave_read_write_data(int port)
-{
-	int slv_status, i;
-
-	/* I2C slave channel A FIFO mode */
-	if (port < I2C_STANDARD_PORT_COUNT) {
-		int count;
-
-		slv_status = IT83XX_SMB_SLSTA;
-
-		/* bit0-4 : FIFO byte count */
-		count = IT83XX_SMB_SFFSTA & 0x1F;
-
-		/* Slave data register is waiting for read or write. */
-		if (slv_status & IT83XX_SMB_SDS) {
-			/* Master to read data */
-			if (slv_status & IT83XX_SMB_RCS) {
-				for (i = 0; i < I2C_READ_MAXFIFO_DATA; i++)
-					/* Return buffer data to master */
-					IT83XX_SMB_SLDA =
-					pbuffer[(i + r_index) & I2C_SIZE_MASK];
-
-				/* Index to next 16 bytes of read buffer */
-				r_index += I2C_READ_MAXFIFO_DATA;
-			}
-			/* Master to write data */
-			else {
-				/* FIFO Full */
-				if (IT83XX_SMB_SFFSTA & IT83XX_SMB_SFFFULL) {
-					for (i = 0; i < count; i++)
-				/* Get data from master to buffer */
-						pbuffer[(w_index + i) &
-					I2C_SIZE_MASK] = IT83XX_SMB_SLDA;
-				}
-
-				/* Index to next byte of write buffer */
-				w_index += count;
-			}
-		}
-		/* Stop condition, indicate stop condition detected. */
-		if (slv_status & IT83XX_SMB_SPDS) {
-			/* Read data less 16 bytes status */
-			if (slv_status & IT83XX_SMB_RCS) {
-				/* Disable FIFO mode to clear left count */
-				IT83XX_SMB_SFFCTL &= ~IT83XX_SMB_SAFE;
-
-				/* Slave A FIFO Enable */
-				IT83XX_SMB_SFFCTL |= IT83XX_SMB_SAFE;
-			}
-			/* Master to write data */
-			else {
-				for (i = 0; i < count; i++)
-					/* Get data from master to buffer */
-					pbuffer[(i + w_index) &
-					I2C_SIZE_MASK] = IT83XX_SMB_SLDA;
-			}
-
-			/* Reset read and write buffer index */
-			buffer_index_reset();
-		}
-		/* Slave time status, timeout status occurs. */
-		if (slv_status & IT83XX_SMB_STS) {
-			/* Reset read and write buffer index */
-			buffer_index_reset();
-		}
-
-		/* Write clear the slave status */
-		IT83XX_SMB_SLSTA = slv_status;
-	}
-	/* Enhanced I2C slave channel D, E, F DMA mode */
-	else {
-		int ch, idx;
-
-		/* Get enhanced i2c channel */
-		ch = i2c_slv_ctrl[port].offset / I2C_ENHANCED_CH_INTERVAL;
-
-		idx = i2c_slv_ctrl[port].dma_index;
-
-		/* Interrupt pending */
-		if (IT83XX_I2C_STR(ch) & IT83XX_I2C_INTPEND) {
-
-			slv_status = IT83XX_I2C_IRQ_ST(ch);
-
-			/* Master to read data */
-			if (slv_status & IT83XX_I2C_IDR_CLR) {
-			/*
-			 * TODO(b:129360157): Return buffer data by
-			 * "out_data" array.
-			 * Ex: Write data to buffer from 0x00 to 0xFF
-			 */
-				for (i = 0; i < I2C_MAX_BUFFER_SIZE; i++)
-					out_data[idx][i] = i;
-			}
-			/* Master to write data */
-			if (slv_status & IT83XX_I2C_IDW_CLR) {
-				/* Master to write data finish flag */
-				wr_done[idx] = 1;
-			}
-			/* Slave finish */
-			if (slv_status & IT83XX_I2C_P_CLR) {
-				if (wr_done[idx]) {
-			/*
-			 * TODO(b:129360157): Handle master write
-			 * data by "in_data" array.
-			 */
-					CPRINTS("WData: %ph",
-						HEX_BUF(in_data[idx],
-							I2C_MAX_BUFFER_SIZE));
-					wr_done[idx] = 0;
-				}
-			}
-
-			/* Write clear the slave status */
-			IT83XX_I2C_IRQ_ST(ch) = slv_status;
-		}
-
-		/* Hardware reset */
-		IT83XX_I2C_CTR(ch) |= IT83XX_I2C_HALT;
-	}
-}
-
-void i2c_slv_interrupt(int port)
-{
-	/* Slave to read and write fifo data */
-	i2c_slave_read_write_data(port);
-
-	/* Clear the interrupt status */
-	task_clear_pending_irq(i2c_slv_ctrl[port].irq);
-}
-
-void i2c_slave_enable(int port, uint8_t slv_addr)
-{
-
-	clock_enable_peripheral(i2c_slv_ctrl[port].clock_gate, 0, 0);
-
-	/* I2C slave channel A FIFO mode */
-	if (port < I2C_STANDARD_PORT_COUNT) {
-
-		/* This field defines the SMCLK0/1/2 clock/data low timeout. */
-		IT83XX_SMB_25MS = I2C_CLK_LOW_TIMEOUT;
-
-		/* bit0 : Slave A FIFO Enable */
-		IT83XX_SMB_SFFCTL |= IT83XX_SMB_SAFE;
-
-		/*
-		 * bit1 : Slave interrupt enable.
-		 * bit2 : SMCLK/SMDAT will be released if timeout.
-		 * bit3 : Slave detect STOP condition interrupt enable.
-		 */
-		IT83XX_SMB_SICR = 0x0E;
-
-		/* Slave address 1 */
-		IT83XX_SMB_RESLADR = slv_addr;
-
-		/* Write clear all slave status */
-		IT83XX_SMB_SLSTA = 0xE7;
-
-		/* bit5 : Enable the SMBus slave device */
-		IT83XX_SMB_HOCTL2(port) |= IT83XX_SMB_SLVEN;
-	}
-	/* Enhanced I2C slave channel D, E, F DMA mode */
-	else {
-		int ch, idx;
-		uint32_t in_data_addr, out_data_addr;
-
-		/* Get enhanced i2c channel */
-		ch = i2c_slv_ctrl[port].offset / I2C_ENHANCED_CH_INTERVAL;
-
-		idx = i2c_slv_ctrl[port].dma_index;
-
-		switch (port) {
-		case IT83XX_I2C_CH_D:
-			/* Enable I2C D channel */
-			IT83XX_GPIO_GRC2 |= (1 << 5);
-			break;
-		case IT83XX_I2C_CH_E:
-			/* Enable I2C E channel */
-			IT83XX_GCTRL_PMER1 |= (1 << 0);
-			break;
-		case IT83XX_I2C_CH_F:
-			/* Enable I2C F channel */
-			IT83XX_GCTRL_PMER1 |= (1 << 1);
-			break;
-		}
-
-		/* Software reset */
-		IT83XX_I2C_DHTR(ch) |= (1 << 7);
-		IT83XX_I2C_DHTR(ch) &= ~(1 << 7);
-
-		/* This field defines the SMCLK3/4/5 clock/data low timeout. */
-		IT83XX_I2C_TOR(ch) = I2C_CLK_LOW_TIMEOUT;
-
-		/* Bit stretching */
-		IT83XX_I2C_TOS(ch) |= IT83XX_I2C_CLK_STR;
-
-		/* Slave address(8-bit)*/
-		IT83XX_I2C_IDR(ch) = slv_addr << 1;
-
-		/* I2C interrupt enable and set acknowledge */
-		IT83XX_I2C_CTR(ch) = IT83XX_I2C_HALT |
-			IT83XX_I2C_INTEN | IT83XX_I2C_ACK;
-
-		/*
-		 * bit3 : Slave ID write flag
-		 * bit2 : Slave ID read flag
-		 * bit1 : Slave received data flag
-		 * bit0 : Slave finish
-		 */
-		IT83XX_I2C_IRQ_ST(ch) = 0xFF;
-
-		/* Clear read and write data buffer of DMA */
-		memset(in_data[idx], 0, I2C_MAX_BUFFER_SIZE);
-		memset(out_data[idx], 0, I2C_MAX_BUFFER_SIZE);
-
-		if (IS_ENABLED(CHIP_ILM_DLM_ORDER)) {
-			in_data_addr = (uint32_t)in_data[idx] & 0xffffff;
-			out_data_addr = (uint32_t)out_data[idx] & 0xffffff;
-		} else {
-			in_data_addr = (uint32_t)in_data[idx] & 0xfff;
-			out_data_addr = (uint32_t)out_data[idx] & 0xfff;
-		}
-
-		/* DMA write target address register */
-		IT83XX_I2C_RAMHA(ch) = in_data_addr >> 8;
-		IT83XX_I2C_RAMLA(ch) = in_data_addr;
-
-		if (IS_ENABLED(CHIP_ILM_DLM_ORDER)) {
-			/*
-			 * DMA write target address register
-			 * for high order byte
-			 */
-			IT83XX_I2C_RAMH2A(ch) = in_data_addr >> 16;
-			/*
-			 * DMA read target address register
-			 * for high order byte
-			 */
-			IT83XX_I2C_CMD_ADDH2(ch) = out_data_addr >> 16;
-			IT83XX_I2C_CMD_ADDH(ch) = out_data_addr >> 8;
-			IT83XX_I2C_CMD_ADDL(ch) = out_data_addr;
-		} else {
-			/* DMA read target address register */
-			IT83XX_I2C_RAMHA2(ch) = out_data_addr >> 8;
-			IT83XX_I2C_RAMLA2(ch) = out_data_addr;
-		}
-
-		/* I2C module enable and command queue mode */
-		IT83XX_I2C_CTR1(ch) = IT83XX_I2C_COMQ_EN |
-			IT83XX_I2C_MDL_EN;
-	}
-}
-
-static void i2c_slave_init(void)
-{
-	int  i, p;
-
-	/* DLM 52k~56k size select enable */
-	IT83XX_GCTRL_MCCR2 |= (1 << 4);
-
-	/* Enable I2C Slave function */
-	for (i = 0; i < i2c_slvs_used; i++) {
-
-		/* I2c slave port mapping. */
-		p = i2c_slv_ports[i].port;
-
-		/* To enable slave ch[x] */
-		i2c_slave_enable(p, i2c_slv_ports[i].slave_adr);
-
-		/* Clear the interrupt status */
-		task_clear_pending_irq(i2c_slv_ctrl[p].irq);
-
-		/* enable i2c interrupt */
-		task_enable_irq(i2c_slv_ctrl[p].irq);
-	}
-}
-DECLARE_HOOK(HOOK_INIT, i2c_slave_init, HOOK_PRIO_INIT_I2C + 1);
diff --git a/chip/it83xx/intc.c b/chip/it83xx/intc.c
index 2a6e3688d9..89e5d70a01 100644
--- a/chip/it83xx/intc.c
+++ b/chip/it83xx/intc.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,98 +6,20 @@
 #include "common.h"
 #include "intc.h"
 #include "it83xx_pd.h"
+#include "ite_pd_intc.h"
 #include "kmsc_chip.h"
 #include "registers.h"
 #include "task.h"
-#include "tcpm.h"
+#include "tcpm/tcpm.h"
 #include "usb_pd.h"
 
-#if defined(CONFIG_USB_PD_TCPM_ITE_ON_CHIP)
-static void chip_pd_irq(enum usbpd_port port)
-{
-	task_clear_pending_irq(usbpd_ctrl_regs[port].irq);
-
-	/* check status */
-	if (IS_ENABLED(IT83XX_INTC_FAST_SWAP_SUPPORT) &&
-		IS_ENABLED(CONFIG_USB_PD_FRS_TCPC) &&
-		IS_ENABLED(CONFIG_USB_PD_REV30)) {
-		/*
-		 * FRS detection must handle first, because we need to short
-		 * the interrupt -> board_frs_handler latency-critical time.
-		 */
-		if (USBPD_IS_FAST_SWAP_DETECT(port)) {
-			/* clear detect FRS signal (cc to GND) status */
-			USBPD_CLEAR_FRS_DETECT_STATUS(port);
-			if (board_frs_handler)
-				board_frs_handler(port);
-			/* inform TCPMv2 to change state */
-			pd_got_frs_signal(port);
-		}
-	}
-
-	if (USBPD_IS_HARD_RESET_DETECT(port)) {
-		/* clear interrupt */
-		IT83XX_USBPD_ISR(port) = USBPD_REG_MASK_HARD_RESET_DETECT;
-		USBPD_SW_RESET(port);
-		task_set_event(PD_PORT_TO_TASK_ID(port),
-			PD_EVENT_RX_HARD_RESET, 0);
-	}
-
-	if (USBPD_IS_RX_DONE(port)) {
-		tcpm_enqueue_message(port);
-		/* clear RX done interrupt */
-		IT83XX_USBPD_ISR(port) = USBPD_REG_MASK_MSG_RX_DONE;
-	}
-
-	if (USBPD_IS_TX_DONE(port)) {
-#ifdef CONFIG_USB_PD_TCPM_DRIVER_IT8XXX2
-		it83xx_clear_tx_error_status(port);
-		/* check TX status, clear by TX_DONE status too */
-		if (USBPD_IS_TX_ERR(port))
-			it83xx_get_tx_error_status(port);
-#endif
-		/* clear TX done interrupt */
-		IT83XX_USBPD_ISR(port) = USBPD_REG_MASK_MSG_TX_DONE;
-		task_set_event(PD_PORT_TO_TASK_ID(port),
-			TASK_EVENT_PHY_TX_DONE, 0);
-	}
-
-	if (IS_ENABLED(IT83XX_INTC_PLUG_IN_OUT_SUPPORT)) {
-		if (USBPD_IS_PLUG_IN_OUT_DETECT(port)) {
-			if (USBPD_IS_PLUG_IN(port))
-				/*
-				 * When tcpc detect type-c plug in:
-				 * 1)If we are sink, disable detect interrupt,
-				 * messages on cc line won't trigger interrupt.
-				 * 2)If we are source, then set plug out
-				 * detection.
-				 */
-				switch_plug_out_type(port);
-			else
-				/*
-				 * When tcpc detect type-c plug out:
-				 * switch to detect plug in.
-				 */
-				IT83XX_USBPD_TCDCR(port) &=
-					~USBPD_REG_PLUG_OUT_SELECT;
-
-			/* clear type-c device plug in/out detect interrupt */
-			IT83XX_USBPD_TCDCR(port) |=
-				USBPD_REG_PLUG_IN_OUT_DETECT_STAT;
-			task_set_event(PD_PORT_TO_TASK_ID(port),
-				PD_EVENT_CC, 0);
-		}
-	}
-}
-#endif
-
 int __ram_code intc_get_ec_int(void)
 {
 	extern volatile int ec_int;
 	return ec_int;
 }
 
-void intc_cpu_int_group_5(void)
+static void intc_cpu_int_group_5(void)
 {
 	/* Determine interrupt number. */
 	int intc_group_5 = intc_get_ec_int();
@@ -118,7 +40,7 @@ void intc_cpu_int_group_5(void)
 }
 DECLARE_IRQ(CPU_INT_GROUP_5, intc_cpu_int_group_5, 2);
 
-void intc_cpu_int_group_4(void)
+static void intc_cpu_int_group_4(void)
 {
 	/* Determine interrupt number. */
 	int intc_group_4 = intc_get_ec_int();
@@ -151,7 +73,7 @@ void intc_cpu_int_group_4(void)
 }
 DECLARE_IRQ(CPU_INT_GROUP_4, intc_cpu_int_group_4, 2);
 
-void intc_cpu_int_group_12(void)
+static void intc_cpu_int_group_12(void)
 {
 	/* Determine interrupt number. */
 	int intc_group_12 = intc_get_ec_int();
@@ -162,7 +84,7 @@ void intc_cpu_int_group_12(void)
 		peci_interrupt();
 		break;
 #endif
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	case IT83XX_IRQ_ESPI:
 		espi_interrupt();
 		break;
@@ -186,8 +108,8 @@ void intc_cpu_int_group_12(void)
 #endif
 #endif
 #ifdef CONFIG_SPI
-	case IT83XX_IRQ_SPI_SLAVE:
-		spi_slv_int_handler();
+	case IT83XX_IRQ_SPI_PERIPHERAL:
+		spi_peripheral_int_handler();
 		break;
 #endif
 	default:
@@ -196,7 +118,7 @@ void intc_cpu_int_group_12(void)
 }
 DECLARE_IRQ(CPU_INT_GROUP_12, intc_cpu_int_group_12, 2);
 
-void intc_cpu_int_group_7(void)
+static void intc_cpu_int_group_7(void)
 {
 	/* Determine interrupt number. */
 	int intc_group_7 = intc_get_ec_int();
@@ -218,17 +140,17 @@ void intc_cpu_int_group_7(void)
 }
 DECLARE_IRQ(CPU_INT_GROUP_7, intc_cpu_int_group_7, 2);
 
-void intc_cpu_int_group_6(void)
+static void intc_cpu_int_group_6(void)
 {
 	/* Determine interrupt number. */
 	int intc_group_6 = intc_get_ec_int();
 
 	switch (intc_group_6) {
-#if defined(CONFIG_I2C_MASTER) || defined(CONFIG_I2C_SLAVE)
+#if defined(CONFIG_I2C_CONTROLLER) || defined(CONFIG_I2C_PERIPHERAL)
 	case IT83XX_IRQ_SMB_A:
-#ifdef CONFIG_I2C_SLAVE
+#ifdef CONFIG_I2C_PERIPHERAL
 		if (IT83XX_SMB_SFFCTL & IT83XX_SMB_SAFE)
-			i2c_slv_interrupt(IT83XX_I2C_CH_A);
+			i2c_periph_interrupt(IT83XX_I2C_CH_A);
 		else
 #endif
 			i2c_interrupt(IT83XX_I2C_CH_A);
@@ -243,27 +165,27 @@ void intc_cpu_int_group_6(void)
 		break;
 
 	case IT83XX_IRQ_SMB_D:
-#ifdef CONFIG_I2C_SLAVE
+#ifdef CONFIG_I2C_PERIPHERAL
 		if (!(IT83XX_I2C_CTR(3) & IT83XX_I2C_MODE))
-			i2c_slv_interrupt(IT83XX_I2C_CH_D);
+			i2c_periph_interrupt(IT83XX_I2C_CH_D);
 		else
 #endif
 			i2c_interrupt(IT83XX_I2C_CH_D);
 		break;
 
 	case IT83XX_IRQ_SMB_E:
-#ifdef CONFIG_I2C_SLAVE
+#ifdef CONFIG_I2C_PERIPHERAL
 		if (!(IT83XX_I2C_CTR(0) & IT83XX_I2C_MODE))
-			i2c_slv_interrupt(IT83XX_I2C_CH_E);
+			i2c_periph_interrupt(IT83XX_I2C_CH_E);
 		else
 #endif
 			i2c_interrupt(IT83XX_I2C_CH_E);
 		break;
 
 	case IT83XX_IRQ_SMB_F:
-#ifdef CONFIG_I2C_SLAVE
+#ifdef CONFIG_I2C_PERIPHERAL
 		if (!(IT83XX_I2C_CTR(1) & IT83XX_I2C_MODE))
-			i2c_slv_interrupt(IT83XX_I2C_CH_F);
+			i2c_periph_interrupt(IT83XX_I2C_CH_F);
 		else
 #endif
 			i2c_interrupt(IT83XX_I2C_CH_F);
diff --git a/chip/it83xx/intc.h b/chip/it83xx/intc.h
index bd6d947453..43adb3784d 100644
--- a/chip/it83xx/intc.h
+++ b/chip/it83xx/intc.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,7 +15,7 @@
 static inline void data_serialization_barrier(void)
 {
 	if (IS_ENABLED(CHIP_CORE_NDS32))
-		asm volatile ("dsb");
+		asm volatile("dsb");
 }
 
 int intc_get_ec_int(void);
@@ -31,8 +31,8 @@ void adc_interrupt(void);
 void voltage_comparator_interrupt(void);
 #endif
 void i2c_interrupt(int port);
-#ifdef CONFIG_I2C_SLAVE
-void i2c_slv_interrupt(int port);
+#ifdef CONFIG_I2C_PERIPHERAL
+void i2c_periph_interrupt(int port);
 #endif
 void clock_sleep_mode_wakeup_isr(void);
 int clock_ec_wake_from_sleep(void);
@@ -44,10 +44,14 @@ void espi_vw_interrupt(void);
 void espi_enable_pad(int enable);
 void espi_init(void);
 void clock_cpu_standby(void);
-void spi_slv_int_handler(void);
+void spi_emmc_cmd0_isr(uint32_t *cmd0_payload);
+void spi_peripheral_int_handler(void);
 #if defined(CONFIG_HOSTCMD_X86) && defined(HAS_TASK_KEYPROTO)
 void lpc_kbc_ibf_interrupt(void);
 void lpc_kbc_obe_interrupt(void);
 #endif
+#ifdef CONFIG_IT83XX_I2C_CMD_QUEUE
+uint32_t i2c_idle_not_allowed(void);
+#endif
 
 #endif /* __CROS_EC_INTC_H */
diff --git a/chip/it83xx/irq.c b/chip/it83xx/irq.c
index 275c6e0e36..21e8070f06 100644
--- a/chip/it83xx/irq.c
+++ b/chip/it83xx/irq.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,56 +10,59 @@
 #include "registers.h"
 #include "util.h"
 
-#define IRQ_GROUP(n, cpu_ints...) \
-	{(uint32_t)&CONCAT2(IT83XX_INTC_ISR, n) - IT83XX_INTC_BASE, \
-	 (uint32_t)&CONCAT2(IT83XX_INTC_IER, n) - IT83XX_INTC_BASE, \
-	 ##cpu_ints}
+#define IRQ_GROUP(n, cpu_ints...)                                            \
+	{                                                                    \
+		(uint32_t) & CONCAT2(IT83XX_INTC_ISR, n) - IT83XX_INTC_BASE, \
+			(uint32_t)&CONCAT2(IT83XX_INTC_IER, n) -             \
+				IT83XX_INTC_BASE,                            \
+			##cpu_ints                                           \
+	}
 
 static const struct {
 	uint8_t isr_off;
 	uint8_t ier_off;
 	uint8_t cpu_int[8];
 } irq_groups[] = {
-	IRQ_GROUP(0,  {-1,  2,  5,  4,  6,  2,  2,  4}),
-	IRQ_GROUP(1,  { 7,  6,  6,  5,  2,  2,  2,  8}),
-	IRQ_GROUP(2,  { 6,  2,  8,  8,  8,  2, 12, 12}),
-	IRQ_GROUP(3,  { 5,  4,  4,  4, 11, 11,  3,  2}),
-	IRQ_GROUP(4,  {11, 11, 11, 11,  8,  9,  9,  9}),
-	IRQ_GROUP(5,  { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(6,  { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(7,  {10, 10,  3, 12,  3,  3,  3,  3}),
-	IRQ_GROUP(8,  { 4,  4,  4,  4,  4,  4, -1, 12}),
-	IRQ_GROUP(9,  { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(10, { 3,  6, 12, 12,  5,  2,  2,  2}),
-	IRQ_GROUP(11, { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(12, { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(13, { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(14, { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(15, { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(16, { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(17, { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(18, { 2,  2,  2,  2, -1,  4,  4,  7}),
-	IRQ_GROUP(19, { 6,  6, 12,  3,  3,  3,  3,  3}),
-	IRQ_GROUP(20, {12, 12, 12, 12, 12, 12, 12, -1}),
+	IRQ_GROUP(0, { -1, 2, 5, 4, 6, 2, 2, 4 }),
+	IRQ_GROUP(1, { 7, 6, 6, 5, 2, 2, 2, 8 }),
+	IRQ_GROUP(2, { 6, 2, 8, 8, 8, 2, 12, 12 }),
+	IRQ_GROUP(3, { 5, 4, 4, 4, 11, 11, 3, 2 }),
+	IRQ_GROUP(4, { 11, 11, 11, 11, 8, 9, 9, 9 }),
+	IRQ_GROUP(5, { 2, 2, 2, 2, 2, 2, 2, 2 }),
+	IRQ_GROUP(6, { 2, 2, 2, 2, 2, 2, 2, 2 }),
+	IRQ_GROUP(7, { 10, 10, 3, 12, 3, 3, 3, 3 }),
+	IRQ_GROUP(8, { 4, 4, 4, 4, 4, 4, -1, 12 }),
+	IRQ_GROUP(9, { 2, 2, 2, 2, 2, 2, 2, 2 }),
+	IRQ_GROUP(10, { 3, 6, 12, 12, 5, 2, 2, 2 }),
+	IRQ_GROUP(11, { 2, 2, 2, 2, 2, 2, 2, 2 }),
+	IRQ_GROUP(12, { 2, 2, 2, 2, 2, 2, 2, 2 }),
+	IRQ_GROUP(13, { 2, 2, 2, 2, 2, 2, 2, 2 }),
+	IRQ_GROUP(14, { 2, 2, 2, 2, 2, 2, 2, 2 }),
+	IRQ_GROUP(15, { 2, 2, 2, 2, 2, 2, 2, 2 }),
+	IRQ_GROUP(16, { 2, 2, 2, 2, 2, 2, 2, 2 }),
+	IRQ_GROUP(17, { 2, 2, 2, 2, 2, 2, 2, 2 }),
+	IRQ_GROUP(18, { 2, 2, 2, 2, -1, 4, 4, 7 }),
+	IRQ_GROUP(19, { 6, 6, 12, 3, 3, 3, 3, 3 }),
+	IRQ_GROUP(20, { 12, 12, 12, 12, 12, 12, 12, -1 }),
 #if defined(IT83XX_INTC_GROUP_21_22_SUPPORT)
-	IRQ_GROUP(21, { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(22, { 2,  2, -1, -1, -1, -1, -1, -1}),
+	IRQ_GROUP(21, { 2, 2, 2, 2, 2, 2, 2, 2 }),
+	IRQ_GROUP(22, { 2, 2, -1, -1, -1, -1, -1, -1 }),
 #elif defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2)
-	IRQ_GROUP(21, {-1, -1, 12, 12, 12, 12, 12, 12}),
-	IRQ_GROUP(22, { 2,  2,  2,  2,  2,  2,  2,  2}),
+	IRQ_GROUP(21, { -1, -1, 12, 12, 12, 12, 12, 12 }),
+	IRQ_GROUP(22, { 2, 2, 2, 2, 2, 2, 2, 2 }),
 #else
-	IRQ_GROUP(21, {-1, -1, -1, -1, -1, -1, -1, -1}),
-	IRQ_GROUP(22, {-1, -1, -1, -1, -1, -1, -1, -1}),
+	IRQ_GROUP(21, { -1, -1, -1, -1, -1, -1, -1, -1 }),
+	IRQ_GROUP(22, { -1, -1, -1, -1, -1, -1, -1, -1 }),
 #endif
-	IRQ_GROUP(23, { 2,  2, -1, -1, -1, -1, -1,  2}),
-	IRQ_GROUP(24, { 2,  2,  2,  2,  2,  2, -1,  2}),
-	IRQ_GROUP(25, { 2,  2,  2,  2, -1, -1, -1, -1}),
-	IRQ_GROUP(26, { 2,  2,  2,  2,  2,  2,  2, -1}),
-	IRQ_GROUP(27, { 2,  2,  2,  2,  2,  2, -1, -1}),
-	IRQ_GROUP(28, { 2,  2,  2,  2,  2,  2, -1, -1}),
+	IRQ_GROUP(23, { 2, 2, -1, -1, -1, -1, -1, 2 }),
+	IRQ_GROUP(24, { 2, 2, 2, 2, 2, 2, -1, 2 }),
+	IRQ_GROUP(25, { 2, 2, 2, 2, -1, -1, -1, -1 }),
+	IRQ_GROUP(26, { 2, 2, 2, 2, 2, 2, 2, -1 }),
+	IRQ_GROUP(27, { 2, 2, 2, 2, 2, 2, -1, -1 }),
+	IRQ_GROUP(28, { 2, 2, 2, 2, 2, 2, -1, -1 }),
 };
 
-#if defined(CHIP_FAMILY_IT8320)    /* N8 core */
+#if defined(CHIP_FAMILY_IT8320) /* N8 core */
 /* Number of CPU hardware interrupts (HW0 ~ HW15) */
 int cpu_int_entry_number;
 #endif
@@ -68,7 +71,7 @@ int chip_get_ec_int(void)
 {
 	extern volatile int ec_int;
 
-#if defined(CHIP_FAMILY_IT8320)    /* N8 core */
+#if defined(CHIP_FAMILY_IT8320) /* N8 core */
 	int i;
 
 	for (i = 0; i < IT83XX_IRQ_COUNT; i++) {
@@ -85,7 +88,14 @@ int chip_get_ec_int(void)
 	/* Determine interrupt number */
 	ec_int -= 16;
 #else /* defined(CHIP_FAMILY_IT8XXX2) RISCV core */
-	ec_int = IT83XX_INTC_AIVCT - 0x10;
+	/* wait until two equal interrupt values are read */
+	do {
+		ec_int = IT83XX_INTC_AIVCT;
+	} while (ec_int != IT83XX_INTC_AIVCT);
+	ec_int -= 0x10;
+	/* Unsupported EC INT number. */
+	if (chip_get_intc_group(ec_int) >= 16)
+		return -1;
 #endif
 	return ec_int;
 }
@@ -100,7 +110,11 @@ void chip_enable_irq(int irq)
 	int group = irq / 8;
 	int bit = irq % 8;
 
-	IT83XX_INTC_REG(irq_groups[group].ier_off) |= BIT(bit);
+	/* SOC's interrupts share CPU machine-mode external interrupt */
+	if (IS_ENABLED(CHIP_CORE_RISCV))
+		IT83XX_INTC_REG(irq_groups[group].ier_off) |= BIT(bit);
+
+	/* SOC's interrupts use CPU HW interrupt 2 ~ 15 */
 	if (IS_ENABLED(CHIP_CORE_NDS32))
 		IT83XX_INTC_REG(IT83XX_INTC_EXT_IER_OFF(group)) |= BIT(bit);
 }
@@ -110,9 +124,29 @@ void chip_disable_irq(int irq)
 	int group = irq / 8;
 	int bit = irq % 8;
 
-	IT83XX_INTC_REG(irq_groups[group].ier_off) &= ~BIT(bit);
-	if (IS_ENABLED(CHIP_CORE_NDS32))
+	/* SOC's interrupts share CPU machine-mode external interrupt */
+	if (IS_ENABLED(CHIP_CORE_RISCV)) {
+		volatile uint8_t _ier __unused;
+
+		IT83XX_INTC_REG(irq_groups[group].ier_off) &= ~BIT(bit);
+		/*
+		 * This load operation will guarantee the above modification of
+		 * EC's register can be seen by any following instructions.
+		 */
+		_ier = IT83XX_INTC_REG(irq_groups[group].ier_off);
+	}
+
+	/* SOC's interrupts use CPU HW interrupt 2 ~ 15 */
+	if (IS_ENABLED(CHIP_CORE_NDS32)) {
+		volatile uint8_t _ext_ier __unused;
+
 		IT83XX_INTC_REG(IT83XX_INTC_EXT_IER_OFF(group)) &= ~BIT(bit);
+		/*
+		 * This load operation will guarantee the above modification of
+		 * EC's register can be seen by any following instructions.
+		 */
+		_ext_ier = IT83XX_INTC_REG(IT83XX_INTC_EXT_IER_OFF(group));
+	}
 }
 
 void chip_clear_pending_irq(int irq)
diff --git a/chip/it83xx/it83xx_fpu.S b/chip/it83xx/it83xx_fpu.S
index 5265eb7253..a75145c835 100644
--- a/chip/it83xx/it83xx_fpu.S
+++ b/chip/it83xx/it83xx_fpu.S
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/it83xx/keyboard_raw.c b/chip/it83xx/keyboard_raw.c
index 5f44670576..9123a6e5e8 100644
--- a/chip/it83xx/keyboard_raw.c
+++ b/chip/it83xx/keyboard_raw.c
@@ -1,20 +1,24 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "common.h"
+#include "irq_chip.h"
 #include "keyboard_raw.h"
 #include "keyboard_scan.h"
 #include "registers.h"
 #include "task.h"
-#include "irq_chip.h"
+
+#define KSOH_PIN_MASK (((1 << (KEYBOARD_COLS_MAX - 8)) - 1) & 0xff)
 
 /*
  * Initialize the raw keyboard interface.
  */
 void keyboard_raw_init(void)
 {
+	uint32_t int_mask;
+
 	/* Ensure top-level interrupt is disabled */
 	keyboard_raw_enable_interrupt(0);
 
@@ -40,8 +44,17 @@ void keyboard_raw_init(void)
 	IT83XX_KBS_KSOL = 0x00;
 #endif
 
-	/* KSO[15:8] pins low. */
-	IT83XX_KBS_KSOH1 = 0x00;
+	/* critical section with interrupts off */
+	int_mask = read_clear_int_mask();
+	/*
+	 * KSO[COLS_MAX:8] pins low.
+	 * NOTE: KSO[15:8] pins can part be enabled for keyboard function and
+	 *       rest be configured as GPIO output mode. In this case that we
+	 *       disable the ISR in critical section to avoid race condition.
+	 */
+	IT83XX_KBS_KSOH1 &= ~KSOH_PIN_MASK;
+	/* restore interrupts */
+	set_int_mask(int_mask);
 
 	/* KSI[0-7] falling-edge triggered is selected */
 	IT83XX_WUC_WUEMR3 = 0xFF;
@@ -71,6 +84,7 @@ void keyboard_raw_task_start(void)
 test_mockable void keyboard_raw_drive_column(int col)
 {
 	int mask;
+	uint32_t int_mask;
 
 	/* Tri-state all outputs */
 	if (col == KEYBOARD_COLUMN_NONE)
@@ -87,7 +101,19 @@ test_mockable void keyboard_raw_drive_column(int col)
 	mask ^= BIT(2);
 #endif
 	IT83XX_KBS_KSOL = mask & 0xff;
-	IT83XX_KBS_KSOH1 = (mask >> 8) & 0xff;
+
+	/* critical section with interrupts off */
+	int_mask = read_clear_int_mask();
+	/*
+	 * Because IT83XX_KBS_KSOH1 register is shared by keyboard scan
+	 * out and GPIO output mode, so we don't drive all KSOH pins
+	 * here (this depends on how many keyboard matrix output pin
+	 * we are using).
+	 */
+	IT83XX_KBS_KSOH1 = (IT83XX_KBS_KSOH1 & ~KSOH_PIN_MASK) |
+			   ((mask >> 8) & KSOH_PIN_MASK);
+	/* restore interrupts */
+	set_int_mask(int_mask);
 }
 
 /*
@@ -125,3 +151,8 @@ void keyboard_raw_interrupt(void)
 	/* Wake the scan task */
 	task_wake(TASK_ID_KEYSCAN);
 }
+
+int keyboard_raw_is_input_low(int port, int id)
+{
+	return !(IT83XX_GPIO_DATA_MIRROR(port) & BIT(id));
+}
diff --git a/chip/it83xx/kmsc_chip.h b/chip/it83xx/kmsc_chip.h
index cf4169a1c4..84f781c0a6 100644
--- a/chip/it83xx/kmsc_chip.h
+++ b/chip/it83xx/kmsc_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/it83xx/lpc.c b/chip/it83xx/lpc.c
index ae66181430..03606c6085 100644
--- a/chip/it83xx/lpc.c
+++ b/chip/it83xx/lpc.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -30,7 +30,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args)
 
 /* LPC PM channels */
 enum lpc_pm_ch {
@@ -48,25 +48,25 @@ enum pm_ctrl_mask {
 	PM_CTRL_OBEIE = 0x02,
 };
 
-#define LPC_ACPI_CMD      LPC_PM1   /* ACPI commands 62h/66h port */
-#define LPC_HOST_CMD      LPC_PM2   /* Host commands 200h/204h port */
-#define LPC_HOST_PORT_80H LPC_PM3   /* Host 80h port */
+#define LPC_ACPI_CMD LPC_PM1 /* ACPI commands 62h/66h port */
+#define LPC_HOST_CMD LPC_PM2 /* Host commands 200h/204h port */
+#define LPC_HOST_PORT_80H LPC_PM3 /* Host 80h port */
 
 static uint8_t acpi_ec_memmap[EC_MEMMAP_SIZE]
-			__attribute__((section(".h2ram.pool.acpiec")));
+	__attribute__((section(".h2ram.pool.acpiec")));
 static uint8_t host_cmd_memmap[256]
-			__attribute__((section(".h2ram.pool.hostcmd")));
+	__attribute__((section(".h2ram.pool.hostcmd")));
 
 static struct host_packet lpc_packet;
 static struct host_cmd_handler_args host_cmd_args;
-static uint8_t host_cmd_flags;   /* Flags from host command */
+static uint8_t host_cmd_flags; /* Flags from host command */
 
 /* Params must be 32-bit aligned */
 static uint8_t params_copy[EC_LPC_HOST_PACKET_SIZE] __aligned(4);
 static int init_done;
 static int p80l_index;
 
-static struct ec_lpc_host_args * const lpc_host_args =
+static struct ec_lpc_host_args *const lpc_host_args =
 	(struct ec_lpc_host_args *)host_cmd_memmap;
 
 static void pm_set_ctrl(enum lpc_pm_ch ch, enum pm_ctrl_mask ctrl, int set)
@@ -136,9 +136,9 @@ static void keyboard_irq_assert(void)
  */
 static void lpc_generate_smi(void)
 {
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	espi_vw_set_wire(VW_SMI_L, 0);
-	udelay(65);
+	udelay(CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US);
 	espi_vw_set_wire(VW_SMI_L, 1);
 #else
 	gpio_set_level(GPIO_PCH_SMI_L, 0);
@@ -149,9 +149,9 @@ static void lpc_generate_smi(void)
 
 static void lpc_generate_sci(void)
 {
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	espi_vw_set_wire(VW_SCI_L, 0);
-	udelay(65);
+	udelay(CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US);
 	espi_vw_set_wire(VW_SCI_L, 1);
 #else
 	gpio_set_level(GPIO_PCH_SCI_L, 0);
@@ -195,15 +195,13 @@ static void lpc_send_response(struct host_cmd_handler_args *args)
 	}
 
 	/* New-style response */
-	lpc_host_args->flags =
-		(host_cmd_flags & ~EC_HOST_ARGS_FLAG_FROM_HOST) |
-		EC_HOST_ARGS_FLAG_TO_HOST;
+	lpc_host_args->flags = (host_cmd_flags & ~EC_HOST_ARGS_FLAG_FROM_HOST) |
+			       EC_HOST_ARGS_FLAG_TO_HOST;
 
 	lpc_host_args->data_size = size;
 
 	csum = args->command + lpc_host_args->flags +
-		lpc_host_args->command_version +
-		lpc_host_args->data_size;
+	       lpc_host_args->command_version + lpc_host_args->data_size;
 
 	for (i = 0, out = (uint8_t *)args->response; i < size; i++, out++)
 		csum += *out;
@@ -251,7 +249,7 @@ void lpc_update_host_event_status(void)
 
 	/* Copy host events to mapped memory */
 	*(host_event_t *)host_get_memmap(EC_MEMMAP_HOST_EVENTS) =
-				lpc_get_host_events();
+		lpc_get_host_events();
 
 	task_enable_irq(IT83XX_IRQ_PMC_IN);
 
@@ -377,7 +375,7 @@ void lpc_clear_acpi_status_mask(uint8_t mask)
 	pm_set_status(LPC_ACPI_CMD, mask, 0);
 }
 
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
 int lpc_get_pltrst_asserted(void)
 {
 	return !gpio_get_level(GPIO_PCH_PLTRST_L);
@@ -390,7 +388,7 @@ void lpc_kbc_ibf_interrupt(void)
 {
 	if (lpc_keyboard_input_pending()) {
 		keyboard_host_write(IT83XX_KBC_KBHIDIR,
-			(IT83XX_KBC_KBHISR & 0x08) ? 1 : 0);
+				    (IT83XX_KBC_KBHISR & 0x08) ? 1 : 0);
 		/* bit7, write-1 clear IBF */
 		IT83XX_KBC_KBHICR |= BIT(7);
 		IT83XX_KBC_KBHICR &= ~BIT(7);
@@ -565,7 +563,7 @@ static void lpc_init(void)
 {
 	enum ec2i_message ec2i_r;
 
-	/* SPI slave interface is disabled */
+	/* SPI peripheral interface is disabled */
 	IT83XX_GCTRL_SSCR = 0;
 	/*
 	 * DLM 52k~56k size select enable.
@@ -688,7 +686,7 @@ static void lpc_init(void)
 	 */
 	IT83XX_GCTRL_SPCTRL1 |= 0xC2;
 
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
 	gpio_enable_interrupt(GPIO_PCH_PLTRST_L);
 #endif
 
@@ -711,7 +709,7 @@ static void lpc_init(void)
 	task_clear_pending_irq(IT83XX_IRQ_PMC3_IN);
 	task_enable_irq(IT83XX_IRQ_PMC3_IN);
 
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	espi_init();
 #endif
 	/* Sufficiently initialized */
@@ -726,15 +724,14 @@ static void lpc_init(void)
  */
 DECLARE_HOOK(HOOK_INIT, lpc_init, HOOK_PRIO_INIT_LPC);
 
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
 void lpcrst_interrupt(enum gpio_signal signal)
 {
 	if (lpc_get_pltrst_asserted())
 		/* Store port 80 reset event */
 		port_80_write(PORT_80_EVENT_RESET);
 
-	CPRINTS("LPC RESET# %sasserted",
-		lpc_get_pltrst_asserted() ? "" : "de");
+	CPRINTS("LPC RESET# %sasserted", lpc_get_pltrst_asserted() ? "" : "de");
 }
 #endif
 
@@ -765,6 +762,5 @@ static enum ec_status lpc_get_protocol_info(struct host_cmd_handler_args *args)
 
 	return EC_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO,
-		lpc_get_protocol_info,
-		EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, lpc_get_protocol_info,
+		     EC_VER_MASK(0));
diff --git a/chip/it83xx/peci.c b/chip/it83xx/peci.c
index 07336eaaf6..ee94f2baac 100644
--- a/chip/it83xx/peci.c
+++ b/chip/it83xx/peci.c
@@ -1,35 +1,34 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* PECI interface for Chrome EC */
 
+#include "builtin/assert.h"
 #include "clock.h"
 #include "hooks.h"
 #include "peci.h"
 #include "registers.h"
-#include "util.h"
-#include "timer.h"
 #include "task.h"
+#include "timer.h"
+#include "util.h"
 
 enum peci_status {
-	PECI_STATUS_NO_ERR        = 0x00,
-	PECI_STATUS_HOBY          = 0x01,
-	PECI_STATUS_FINISH        = 0x02,
-	PECI_STATUS_RD_FCS_ERR    = 0x04,
-	PECI_STATUS_WR_FCS_ERR    = 0x08,
-	PECI_STATUS_EXTERR        = 0x20,
-	PECI_STATUS_BUSERR        = 0x40,
-	PECI_STATUS_RCV_ERRCODE   = 0x80,
-	PECI_STATUS_ERR_NEED_RST  = (PECI_STATUS_BUSERR | PECI_STATUS_EXTERR),
-	PECI_STATUS_ANY_ERR       = (PECI_STATUS_RCV_ERRCODE |
-					PECI_STATUS_BUSERR |
-					PECI_STATUS_EXTERR |
-					PECI_STATUS_WR_FCS_ERR |
-					PECI_STATUS_RD_FCS_ERR),
-	PECI_STATUS_ANY_BIT       = 0xFE,
-	PECI_STATUS_TIMEOUT       = 0xFF,
+	PECI_STATUS_NO_ERR = 0x00,
+	PECI_STATUS_HOBY = 0x01,
+	PECI_STATUS_FINISH = 0x02,
+	PECI_STATUS_RD_FCS_ERR = 0x04,
+	PECI_STATUS_WR_FCS_ERR = 0x08,
+	PECI_STATUS_EXTERR = 0x20,
+	PECI_STATUS_BUSERR = 0x40,
+	PECI_STATUS_RCV_ERRCODE = 0x80,
+	PECI_STATUS_ERR_NEED_RST = (PECI_STATUS_BUSERR | PECI_STATUS_EXTERR),
+	PECI_STATUS_ANY_ERR = (PECI_STATUS_RCV_ERRCODE | PECI_STATUS_BUSERR |
+			       PECI_STATUS_EXTERR | PECI_STATUS_WR_FCS_ERR |
+			       PECI_STATUS_RD_FCS_ERR),
+	PECI_STATUS_ANY_BIT = 0xFE,
+	PECI_STATUS_TIMEOUT = 0xFF,
 };
 
 static task_id_t peci_current_task;
@@ -106,10 +105,9 @@ int peci_transaction(struct peci_data *peci)
 		IT83XX_PECI_HOWRLR = 0x00;
 	} else {
 		if ((peci->cmd_code == PECI_CMD_WR_PKG_CFG) ||
-			(peci->cmd_code == PECI_CMD_WR_IAMSR) ||
-			(peci->cmd_code == PECI_CMD_WR_PCI_CFG) ||
-			(peci->cmd_code == PECI_CMD_WR_PCI_CFG_LOCAL)) {
-
+		    (peci->cmd_code == PECI_CMD_WR_IAMSR) ||
+		    (peci->cmd_code == PECI_CMD_WR_PCI_CFG) ||
+		    (peci->cmd_code == PECI_CMD_WR_PCI_CFG_LOCAL)) {
 			/* write length include Cmd Code + AW FCS */
 			IT83XX_PECI_HOWRLR = peci->w_len + 2;
 
@@ -157,17 +155,14 @@ int peci_transaction(struct peci_data *peci)
 	peci_current_task = TASK_ID_INVALID;
 
 	if (index < peci->timeout_us) {
-
 		status = IT83XX_PECI_HOSTAR;
 
 		/* any error */
 		if (IT83XX_PECI_HOSTAR & PECI_STATUS_ANY_ERR) {
-
 			if (IT83XX_PECI_HOSTAR & PECI_STATUS_ERR_NEED_RST)
 				peci_reset();
 
 		} else if (IT83XX_PECI_HOSTAR & PECI_STATUS_FINISH) {
-
 			/* The read data field of the PECI protocol. */
 			for (index = 0x00; index < peci->r_len; index++)
 				peci->r_buf[index] = IT83XX_PECI_HORDDR;
diff --git a/chip/it83xx/pwm.c b/chip/it83xx/pwm.c
index 6328c69b46..3d0d4eaeb6 100644
--- a/chip/it83xx/pwm.c
+++ b/chip/it83xx/pwm.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,35 +8,35 @@
 #include "clock.h"
 #include "gpio.h"
 #include "hooks.h"
+#include "math_util.h"
 #include "pwm.h"
 #include "pwm_chip.h"
 #include "registers.h"
 #include "util.h"
-#include "math_util.h"
 
 #define PWM_CTRX_MIN 100
-#define PWM_EC_FREQ  8000000
+#define PWM_EC_FREQ 8000000
 
 const struct pwm_ctrl_t pwm_ctrl_regs[] = {
-	{ &IT83XX_PWM_DCR0, &IT83XX_PWM_PCSSGL, &IT83XX_GPIO_GPCRA0},
-	{ &IT83XX_PWM_DCR1, &IT83XX_PWM_PCSSGL, &IT83XX_GPIO_GPCRA1},
-	{ &IT83XX_PWM_DCR2, &IT83XX_PWM_PCSSGL, &IT83XX_GPIO_GPCRA2},
-	{ &IT83XX_PWM_DCR3, &IT83XX_PWM_PCSSGL, &IT83XX_GPIO_GPCRA3},
-	{ &IT83XX_PWM_DCR4, &IT83XX_PWM_PCSSGH, &IT83XX_GPIO_GPCRA4},
-	{ &IT83XX_PWM_DCR5, &IT83XX_PWM_PCSSGH, &IT83XX_GPIO_GPCRA5},
-	{ &IT83XX_PWM_DCR6, &IT83XX_PWM_PCSSGH, &IT83XX_GPIO_GPCRA6},
-	{ &IT83XX_PWM_DCR7, &IT83XX_PWM_PCSSGH, &IT83XX_GPIO_GPCRA7},
+	{ &IT83XX_PWM_DCR0, &IT83XX_PWM_PCSSGL, &IT83XX_GPIO_GPCRA0 },
+	{ &IT83XX_PWM_DCR1, &IT83XX_PWM_PCSSGL, &IT83XX_GPIO_GPCRA1 },
+	{ &IT83XX_PWM_DCR2, &IT83XX_PWM_PCSSGL, &IT83XX_GPIO_GPCRA2 },
+	{ &IT83XX_PWM_DCR3, &IT83XX_PWM_PCSSGL, &IT83XX_GPIO_GPCRA3 },
+	{ &IT83XX_PWM_DCR4, &IT83XX_PWM_PCSSGH, &IT83XX_GPIO_GPCRA4 },
+	{ &IT83XX_PWM_DCR5, &IT83XX_PWM_PCSSGH, &IT83XX_GPIO_GPCRA5 },
+	{ &IT83XX_PWM_DCR6, &IT83XX_PWM_PCSSGH, &IT83XX_GPIO_GPCRA6 },
+	{ &IT83XX_PWM_DCR7, &IT83XX_PWM_PCSSGH, &IT83XX_GPIO_GPCRA7 },
 };
 
 const struct pwm_ctrl_t2 pwm_clock_ctrl_regs[] = {
 	{ &IT83XX_PWM_CTR, &IT83XX_PWM_C0CPRS, &IT83XX_PWM_C0CPRS,
-		&IT83XX_PWM_PCFSR, 0x01},
+	  &IT83XX_PWM_PCFSR, 0x01 },
 	{ &IT83XX_PWM_CTR1, &IT83XX_PWM_C4CPRS, &IT83XX_PWM_C4MCPRS,
-		&IT83XX_PWM_PCFSR, 0x02},
+	  &IT83XX_PWM_PCFSR, 0x02 },
 	{ &IT83XX_PWM_CTR2, &IT83XX_PWM_C6CPRS, &IT83XX_PWM_C6MCPRS,
-		&IT83XX_PWM_PCFSR, 0x04},
+	  &IT83XX_PWM_PCFSR, 0x04 },
 	{ &IT83XX_PWM_CTR3, &IT83XX_PWM_C7CPRS, &IT83XX_PWM_C7MCPRS,
-		&IT83XX_PWM_PCFSR, 0x08},
+	  &IT83XX_PWM_PCFSR, 0x08 },
 };
 
 static int pwm_get_cycle_time(enum pwm_channel ch)
@@ -67,18 +67,19 @@ static int pwm_get_cycle_time(enum pwm_channel ch)
 void pwm_enable(enum pwm_channel ch, int enabled)
 {
 	/* pwm channel mapping */
-	ch = pwm_channels[ch].channel;
+	int pwm_reg_index = pwm_channels[ch].channel;
 
 	/*
 	 * enabled : pin to PWM function.
 	 * disabled : pin to GPIO input function.
 	 */
 	if (enabled)
-		*pwm_ctrl_regs[ch].pwm_pin = 0x00;
+		*pwm_ctrl_regs[pwm_reg_index].pwm_pin = 0x00;
 	else
-		*pwm_ctrl_regs[ch].pwm_pin = 0x80 |
-			((pwm_channels[ch].flags & PWM_CONFIG_ACTIVE_LOW) ?
-			4 : 2);
+		*pwm_ctrl_regs[pwm_reg_index].pwm_pin =
+			0x80 |
+			((pwm_channels[ch].flags & PWM_CONFIG_ACTIVE_LOW) ? 4 :
+									    2);
 }
 
 int pwm_get_enabled(enum pwm_channel ch)
@@ -88,7 +89,9 @@ int pwm_get_enabled(enum pwm_channel ch)
 
 	/* pin is PWM function and PWMs clock counter was enabled */
 	return ((*pwm_ctrl_regs[ch].pwm_pin & ~0x04) == 0x00 &&
-		IT83XX_PWM_ZTIER & 0x02) ? 1 : 0;
+		IT83XX_PWM_ZTIER & 0x02) ?
+		       1 :
+		       0;
 }
 
 void pwm_set_duty(enum pwm_channel ch, int percent)
@@ -202,7 +205,8 @@ static int pwm_ch_freq(enum pwm_channel ch)
 	int actual_freq = -1, targe_freq, deviation;
 	int pcfsr, ctr, pcfsr_sel, pcs_shift, pcs_mask;
 	int pwm_clk_src = (pwm_channels[ch].flags & PWM_CONFIG_DSLEEP) ?
-							32768 : PWM_EC_FREQ;
+				  32768 :
+				  PWM_EC_FREQ;
 
 	targe_freq = pwm_channels[ch].freq_hz;
 	deviation = (targe_freq / 100) + 1;
@@ -251,8 +255,8 @@ static int pwm_ch_freq(enum pwm_channel ch)
 		*pwm_ctrl_regs[ch].pwm_clock_source |= pcs_mask;
 
 		*pwm_clock_ctrl_regs[pcfsr_sel].pwm_cpr_lsb = pcfsr & 0xFF;
-		*pwm_clock_ctrl_regs[pcfsr_sel].pwm_cpr_msb =
-			(pcfsr >> 8) & 0xFF;
+		*pwm_clock_ctrl_regs[pcfsr_sel].pwm_cpr_msb = (pcfsr >> 8) &
+							      0xFF;
 	}
 
 	return actual_freq;
diff --git a/chip/it83xx/pwm_chip.h b/chip/it83xx/pwm_chip.h
index 4e8aba1c62..03435d03f6 100644
--- a/chip/it83xx/pwm_chip.h
+++ b/chip/it83xx/pwm_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h
index 7f70724864..ade0b97289 100644
--- a/chip/it83xx/registers.h
+++ b/chip/it83xx/registers.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,775 +11,776 @@
 #include "common.h"
 #include "compile_time_macros.h"
 
-#define __ram_code __attribute__((section(".ram_code")))
+#define __ram_code __attribute__((section(__RAM_CODE_SECTION_NAME)))
 
 /* IRQ numbers */
 /* Group 0 */
-#define IT83XX_IRQ_WKO20           1
-#define IT83XX_IRQ_KBC_OUT         2
-#define IT83XX_IRQ_PMC_OUT         3
-#define IT83XX_IRQ_SMB_D           4
-#define IT83XX_IRQ_WKINTAD         5
-#define IT83XX_IRQ_WKO23           6
-#define IT83XX_IRQ_PWM             7
+#define IT83XX_IRQ_WKO20 1
+#define IT83XX_IRQ_KBC_OUT 2
+#define IT83XX_IRQ_PMC_OUT 3
+#define IT83XX_IRQ_SMB_D 4
+#define IT83XX_IRQ_WKINTAD 5
+#define IT83XX_IRQ_WKO23 6
+#define IT83XX_IRQ_PWM 7
 /* Group 1 */
-#define IT83XX_IRQ_ADC             8
-#define IT83XX_IRQ_SMB_A           9
-#define IT83XX_IRQ_SMB_B          10
-#define IT83XX_IRQ_KB_MATRIX      11
-#define IT83XX_IRQ_WKO26          12
-#define IT83XX_IRQ_WKINTC         13
-#define IT83XX_IRQ_WKO25          14
-#define IT83XX_IRQ_CIR            15
+#define IT83XX_IRQ_ADC 8
+#define IT83XX_IRQ_SMB_A 9
+#define IT83XX_IRQ_SMB_B 10
+#define IT83XX_IRQ_KB_MATRIX 11
+#define IT83XX_IRQ_WKO26 12
+#define IT83XX_IRQ_WKINTC 13
+#define IT83XX_IRQ_WKO25 14
+#define IT83XX_IRQ_CIR 15
 /* Group 2 */
-#define IT83XX_IRQ_SMB_C          16
-#define IT83XX_IRQ_WKO24          17
-#define IT83XX_IRQ_PS2_2          18
-#define IT83XX_IRQ_PS2_1          19
-#define IT83XX_IRQ_PS2_0          20
-#define IT83XX_IRQ_WKO22          21
-#define IT83XX_IRQ_SMFI           22
-#define IT83XX_IRQ_USB            23
+#define IT83XX_IRQ_SMB_C 16
+#define IT83XX_IRQ_WKO24 17
+#define IT83XX_IRQ_PS2_2 18
+#define IT83XX_IRQ_PS2_1 19
+#define IT83XX_IRQ_PS2_0 20
+#define IT83XX_IRQ_WKO22 21
+#define IT83XX_IRQ_SMFI 22
+#define IT83XX_IRQ_USB 23
 /* Group 3 */
-#define IT83XX_IRQ_KBC_IN         24
-#define IT83XX_IRQ_PMC_IN         25
-#define IT83XX_IRQ_PMC2_OUT       26
-#define IT83XX_IRQ_PMC2_IN        27
-#define IT83XX_IRQ_GINT           28
-#define IT83XX_IRQ_EGPC           29
-#define IT83XX_IRQ_EXT_TIMER1     30
-#define IT83XX_IRQ_WKO21          31
+#define IT83XX_IRQ_KBC_IN 24
+#define IT83XX_IRQ_PMC_IN 25
+#define IT83XX_IRQ_PMC2_OUT 26
+#define IT83XX_IRQ_PMC2_IN 27
+#define IT83XX_IRQ_GINT 28
+#define IT83XX_IRQ_EGPC 29
+#define IT83XX_IRQ_EXT_TIMER1 30
+#define IT83XX_IRQ_WKO21 31
 /* Group 4 */
-#define IT83XX_IRQ_GPINT0         32
-#define IT83XX_IRQ_GPINT1         33
-#define IT83XX_IRQ_GPINT2         34
-#define IT83XX_IRQ_GPINT3         35
-#define IT83XX_IRQ_CIR_GPINT      36
-#define IT83XX_IRQ_SSPI           37
-#define IT83XX_IRQ_UART1          38
-#define IT83XX_IRQ_UART2          39
+#define IT83XX_IRQ_GPINT0 32
+#define IT83XX_IRQ_GPINT1 33
+#define IT83XX_IRQ_GPINT2 34
+#define IT83XX_IRQ_GPINT3 35
+#define IT83XX_IRQ_CIR_GPINT 36
+#define IT83XX_IRQ_SSPI 37
+#define IT83XX_IRQ_UART1 38
+#define IT83XX_IRQ_UART2 39
 /* Group 5 */
-#define IT83XX_IRQ_WKO50          40
-#define IT83XX_IRQ_WKO51          41
-#define IT83XX_IRQ_WKO52          42
-#define IT83XX_IRQ_WKO53          43
-#define IT83XX_IRQ_WKO54          44
-#define IT83XX_IRQ_WKO55          45
-#define IT83XX_IRQ_WKO56          46
-#define IT83XX_IRQ_WKO57          47
+#define IT83XX_IRQ_WKO50 40
+#define IT83XX_IRQ_WKO51 41
+#define IT83XX_IRQ_WKO52 42
+#define IT83XX_IRQ_WKO53 43
+#define IT83XX_IRQ_WKO54 44
+#define IT83XX_IRQ_WKO55 45
+#define IT83XX_IRQ_WKO56 46
+#define IT83XX_IRQ_WKO57 47
 /* Group 6 */
-#define IT83XX_IRQ_WKO60          48
-#define IT83XX_IRQ_WKO61          49
-#define IT83XX_IRQ_WKO62          50
-#define IT83XX_IRQ_WKO63          51
-#define IT83XX_IRQ_WKO64          52
-#define IT83XX_IRQ_WKO65          53
-#define IT83XX_IRQ_WKO66          54
-#define IT83XX_IRQ_WKO67          55
+#define IT83XX_IRQ_WKO60 48
+#define IT83XX_IRQ_WKO61 49
+#define IT83XX_IRQ_WKO62 50
+#define IT83XX_IRQ_WKO63 51
+#define IT83XX_IRQ_WKO64 52
+#define IT83XX_IRQ_WKO65 53
+#define IT83XX_IRQ_WKO66 54
+#define IT83XX_IRQ_WKO67 55
 /* Group 7 */
-#define IT83XX_IRQ_RTCT_ALARM1    56
-#define IT83XX_IRQ_RTCT_ALARM2    57
-#define IT83XX_IRQ_EXT_TIMER2     58
-#define IT83XX_IRQ_DEFERRED_SPI   59
-#define IT83XX_IRQ_TMR_A0         60
-#define IT83XX_IRQ_TMR_A1         61
-#define IT83XX_IRQ_TMR_B0         62
-#define IT83XX_IRQ_TMR_B1         63
+#define IT83XX_IRQ_RTCT_ALARM1 56
+#define IT83XX_IRQ_RTCT_ALARM2 57
+#define IT83XX_IRQ_EXT_TIMER2 58
+#define IT83XX_IRQ_DEFERRED_SPI 59
+#define IT83XX_IRQ_TMR_A0 60
+#define IT83XX_IRQ_TMR_A1 61
+#define IT83XX_IRQ_TMR_B0 62
+#define IT83XX_IRQ_TMR_B1 63
 /* Group 8 */
-#define IT83XX_IRQ_PMC2EX_OUT     64
-#define IT83XX_IRQ_PMC2EX_IN      65
-#define IT83XX_IRQ_PMC3_OUT       66
-#define IT83XX_IRQ_PMC3_IN        67
-#define IT83XX_IRQ_PMC4_OUT       68
-#define IT83XX_IRQ_PMC4_IN        69
-#define IT83XX_IRQ_I2BRAM         71
+#define IT83XX_IRQ_PMC2EX_OUT 64
+#define IT83XX_IRQ_PMC2EX_IN 65
+#define IT83XX_IRQ_PMC3_OUT 66
+#define IT83XX_IRQ_PMC3_IN 67
+#define IT83XX_IRQ_PMC4_OUT 68
+#define IT83XX_IRQ_PMC4_IN 69
+#define IT83XX_IRQ_I2BRAM 71
 /* Group 9 */
-#define IT83XX_IRQ_WKO70          72
-#define IT83XX_IRQ_WKO71          73
-#define IT83XX_IRQ_WKO72          74
-#define IT83XX_IRQ_WKO73          75
-#define IT83XX_IRQ_WKO74          76
-#define IT83XX_IRQ_WKO75          77
-#define IT83XX_IRQ_WKO76          78
-#define IT83XX_IRQ_WKO77          79
+#define IT83XX_IRQ_WKO70 72
+#define IT83XX_IRQ_WKO71 73
+#define IT83XX_IRQ_WKO72 74
+#define IT83XX_IRQ_WKO73 75
+#define IT83XX_IRQ_WKO74 76
+#define IT83XX_IRQ_WKO75 77
+#define IT83XX_IRQ_WKO76 78
+#define IT83XX_IRQ_WKO77 79
 /* Group 10 */
-#define IT83XX_IRQ_EXT_TMR8       80
+#define IT83XX_IRQ_EXT_TMR8 80
 #define IT83XX_IRQ_SMB_CLOCK_HELD 81
-#define IT83XX_IRQ_CEC            82
-#define IT83XX_IRQ_H2RAM_LPC      83
-#define IT83XX_IRQ_HW_KB_SCAN     84
-#define IT83XX_IRQ_WKO88          85
-#define IT83XX_IRQ_WKO89          86
-#define IT83XX_IRQ_WKO90          87
+#define IT83XX_IRQ_CEC 82
+#define IT83XX_IRQ_H2RAM_LPC 83
+#define IT83XX_IRQ_HW_KB_SCAN 84
+#define IT83XX_IRQ_WKO88 85
+#define IT83XX_IRQ_WKO89 86
+#define IT83XX_IRQ_WKO90 87
 /* Group 11 */
-#define IT83XX_IRQ_WKO80          88
-#define IT83XX_IRQ_WKO81          89
-#define IT83XX_IRQ_WKO82          90
-#define IT83XX_IRQ_WKO83          91
-#define IT83XX_IRQ_WKO84          92
-#define IT83XX_IRQ_WKO85          93
-#define IT83XX_IRQ_WKO86          94
-#define IT83XX_IRQ_WKO87          95
+#define IT83XX_IRQ_WKO80 88
+#define IT83XX_IRQ_WKO81 89
+#define IT83XX_IRQ_WKO82 90
+#define IT83XX_IRQ_WKO83 91
+#define IT83XX_IRQ_WKO84 92
+#define IT83XX_IRQ_WKO85 93
+#define IT83XX_IRQ_WKO86 94
+#define IT83XX_IRQ_WKO87 95
 /* Group 12 */
-#define IT83XX_IRQ_WKO91          96
-#define IT83XX_IRQ_WKO92          97
-#define IT83XX_IRQ_WKO93          98
-#define IT83XX_IRQ_WKO94          99
-#define IT83XX_IRQ_WKO95          100
-#define IT83XX_IRQ_WKO96          101
-#define IT83XX_IRQ_WKO97          102
-#define IT83XX_IRQ_WKO98          103
+#define IT83XX_IRQ_WKO91 96
+#define IT83XX_IRQ_WKO92 97
+#define IT83XX_IRQ_WKO93 98
+#define IT83XX_IRQ_WKO94 99
+#define IT83XX_IRQ_WKO95 100
+#define IT83XX_IRQ_WKO96 101
+#define IT83XX_IRQ_WKO97 102
+#define IT83XX_IRQ_WKO98 103
 /* Group 13 */
-#define IT83XX_IRQ_WKO99          104
-#define IT83XX_IRQ_WKO100         105
-#define IT83XX_IRQ_WKO101         106
-#define IT83XX_IRQ_WKO102         107
-#define IT83XX_IRQ_WKO103         108
-#define IT83XX_IRQ_WKO104         109
-#define IT83XX_IRQ_WKO105         110
-#define IT83XX_IRQ_WKO106         111
+#define IT83XX_IRQ_WKO99 104
+#define IT83XX_IRQ_WKO100 105
+#define IT83XX_IRQ_WKO101 106
+#define IT83XX_IRQ_WKO102 107
+#define IT83XX_IRQ_WKO103 108
+#define IT83XX_IRQ_WKO104 109
+#define IT83XX_IRQ_WKO105 110
+#define IT83XX_IRQ_WKO106 111
 /* Group 14 */
-#define IT83XX_IRQ_WKO107         112
-#define IT83XX_IRQ_WKO108         113
-#define IT83XX_IRQ_WKO109         114
-#define IT83XX_IRQ_WKO110         115
-#define IT83XX_IRQ_WKO111         116
-#define IT83XX_IRQ_WKO112         117
-#define IT83XX_IRQ_WKO113         118
-#define IT83XX_IRQ_WKO114         119
+#define IT83XX_IRQ_WKO107 112
+#define IT83XX_IRQ_WKO108 113
+#define IT83XX_IRQ_WKO109 114
+#define IT83XX_IRQ_WKO110 115
+#define IT83XX_IRQ_WKO111 116
+#define IT83XX_IRQ_WKO112 117
+#define IT83XX_IRQ_WKO113 118
+#define IT83XX_IRQ_WKO114 119
 /* Group 15 */
-#define IT83XX_IRQ_WKO115         120
-#define IT83XX_IRQ_WKO116         121
-#define IT83XX_IRQ_WKO117         122
-#define IT83XX_IRQ_WKO118         123
-#define IT83XX_IRQ_WKO119         124
-#define IT83XX_IRQ_WKO120         125
-#define IT83XX_IRQ_WKO121         126
-#define IT83XX_IRQ_WKO122         127
+#define IT83XX_IRQ_WKO115 120
+#define IT83XX_IRQ_WKO116 121
+#define IT83XX_IRQ_WKO117 122
+#define IT83XX_IRQ_WKO118 123
+#define IT83XX_IRQ_WKO119 124
+#define IT83XX_IRQ_WKO120 125
+#define IT83XX_IRQ_WKO121 126
+#define IT83XX_IRQ_WKO122 127
 /* Group 16 */
-#define IT83XX_IRQ_WKO128         128
-#define IT83XX_IRQ_WKO129         129
-#define IT83XX_IRQ_WKO130         130
-#define IT83XX_IRQ_WKO131         131
-#define IT83XX_IRQ_WKO132         132
-#define IT83XX_IRQ_WKO133         133
-#define IT83XX_IRQ_WKO134         134
-#define IT83XX_IRQ_WKO135         135
+#define IT83XX_IRQ_WKO128 128
+#define IT83XX_IRQ_WKO129 129
+#define IT83XX_IRQ_WKO130 130
+#define IT83XX_IRQ_WKO131 131
+#define IT83XX_IRQ_WKO132 132
+#define IT83XX_IRQ_WKO133 133
+#define IT83XX_IRQ_WKO134 134
+#define IT83XX_IRQ_WKO135 135
 /* Group 17 */
-#define IT83XX_IRQ_WKO136         136
-#define IT83XX_IRQ_WKO137         137
-#define IT83XX_IRQ_WKO138         138
-#define IT83XX_IRQ_WKO139         139
-#define IT83XX_IRQ_WKO140         140
-#define IT83XX_IRQ_WKO141         141
-#define IT83XX_IRQ_WKO142         142
-#define IT83XX_IRQ_WKO143         143
+#define IT83XX_IRQ_WKO136 136
+#define IT83XX_IRQ_WKO137 137
+#define IT83XX_IRQ_WKO138 138
+#define IT83XX_IRQ_WKO139 139
+#define IT83XX_IRQ_WKO140 140
+#define IT83XX_IRQ_WKO141 141
+#define IT83XX_IRQ_WKO142 142
+#define IT83XX_IRQ_WKO143 143
 /* Group 18 */
-#define IT83XX_IRQ_WKO123         144
-#define IT83XX_IRQ_WKO124         145
-#define IT83XX_IRQ_WKO125         146
-#define IT83XX_IRQ_WKO126         147
-#define IT83XX_IRQ_PMC5_OUT       149
-#define IT83XX_IRQ_PMC5_IN        150
-#define IT83XX_IRQ_V_COMP         151
+#define IT83XX_IRQ_WKO123 144
+#define IT83XX_IRQ_WKO124 145
+#define IT83XX_IRQ_WKO125 146
+#define IT83XX_IRQ_WKO126 147
+#define IT83XX_IRQ_PMC5_OUT 149
+#define IT83XX_IRQ_PMC5_IN 150
+#define IT83XX_IRQ_V_COMP 151
 /* Group 19 */
-#define IT83XX_IRQ_SMB_E          152
-#define IT83XX_IRQ_SMB_F          153
-#define IT83XX_IRQ_OSC_DMA        154
-#define IT83XX_IRQ_EXT_TIMER3     155
-#define IT83XX_IRQ_EXT_TIMER4     156
-#define IT83XX_IRQ_EXT_TIMER5     157
-#define IT83XX_IRQ_EXT_TIMER6     158
-#define IT83XX_IRQ_EXT_TIMER7     159
+#define IT83XX_IRQ_SMB_E 152
+#define IT83XX_IRQ_SMB_F 153
+#define IT83XX_IRQ_OSC_DMA 154
+#define IT83XX_IRQ_EXT_TIMER3 155
+#define IT83XX_IRQ_EXT_TIMER4 156
+#define IT83XX_IRQ_EXT_TIMER5 157
+#define IT83XX_IRQ_EXT_TIMER6 158
+#define IT83XX_IRQ_EXT_TIMER7 159
 /* Group 20 */
-#define IT83XX_IRQ_PECI           160
-#define IT83XX_IRQ_SOFTWARE       161
-#define IT83XX_IRQ_ESPI           162
-#define IT83XX_IRQ_ESPI_VW        163
-#define IT83XX_IRQ_PCH_P80        164
-#define IT83XX_IRQ_USBPD0         165
-#define IT83XX_IRQ_USBPD1         166
+#define IT83XX_IRQ_PECI 160
+#define IT83XX_IRQ_SOFTWARE 161
+#define IT83XX_IRQ_ESPI 162
+#define IT83XX_IRQ_ESPI_VW 163
+#define IT83XX_IRQ_PCH_P80 164
+#define IT83XX_IRQ_USBPD0 165
+#define IT83XX_IRQ_USBPD1 166
 /* Group 21 */
 #if defined(CHIP_FAMILY_IT8320)
-#define IT83XX_IRQ_WKO40          168
-#define IT83XX_IRQ_WKO45          169
-#define IT83XX_IRQ_WKO46          170
-#define IT83XX_IRQ_WKO144         171
-#define IT83XX_IRQ_WKO145         172
-#define IT83XX_IRQ_WKO146         173
-#define IT83XX_IRQ_WKO147         174
-#define IT83XX_IRQ_WKO148         175
+#define IT83XX_IRQ_WKO40 168
+#define IT83XX_IRQ_WKO45 169
+#define IT83XX_IRQ_WKO46 170
+#define IT83XX_IRQ_WKO144 171
+#define IT83XX_IRQ_WKO145 172
+#define IT83XX_IRQ_WKO146 173
+#define IT83XX_IRQ_WKO147 174
+#define IT83XX_IRQ_WKO148 175
 /* Group 22 */
-#define IT83XX_IRQ_WKO149         176
-#define IT83XX_IRQ_WKO150         177
+#define IT83XX_IRQ_WKO149 176
+#define IT83XX_IRQ_WKO150 177
 
-#define IT83XX_IRQ_COUNT          178
+#define IT83XX_IRQ_COUNT 178
 #elif defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2)
 /* Group 21 */
-#define IT83XX_IRQ_AUDIO_IF       170
-#define IT83XX_IRQ_SPI_SLAVE      171
-#define IT83XX_IRQ_DSP_ENGINE     172
-#define IT83XX_IRQ_NN_ENGINE      173
-#define IT83XX_IRQ_USBPD2         174
-#define IT83XX_IRQ_CRYPTO         175
+#define IT83XX_IRQ_AUDIO_IF 170
+#define IT83XX_IRQ_SPI_PERIPHERAL 171
+#define IT83XX_IRQ_DSP_ENGINE 172
+#define IT83XX_IRQ_NN_ENGINE 173
+#define IT83XX_IRQ_USBPD2 174
+#define IT83XX_IRQ_CRYPTO 175
 /* Group 22 */
-#define IT83XX_IRQ_WKO40          176
-#define IT83XX_IRQ_WKO45          177
-#define IT83XX_IRQ_WKO46          178
-#define IT83XX_IRQ_WKO144         179
-#define IT83XX_IRQ_WKO145         180
-#define IT83XX_IRQ_WKO146         181
-#define IT83XX_IRQ_WKO147         182
-#define IT83XX_IRQ_WKO148         183
+#define IT83XX_IRQ_WKO40 176
+#define IT83XX_IRQ_WKO45 177
+#define IT83XX_IRQ_WKO46 178
+#define IT83XX_IRQ_WKO144 179
+#define IT83XX_IRQ_WKO145 180
+#define IT83XX_IRQ_WKO146 181
+#define IT83XX_IRQ_WKO147 182
+#define IT83XX_IRQ_WKO148 183
 /* Group 23 */
-#define IT83XX_IRQ_WKO149         184
-#define IT83XX_IRQ_WKO150         185
-#define IT83XX_IRQ_SSPI1          191
+#define IT83XX_IRQ_WKO149 184
+#define IT83XX_IRQ_WKO150 185
+#define IT83XX_IRQ_SSPI1 191
 /* Group 24 */
-#define IT83XX_IRQ_XLPIN0         192
-#define IT83XX_IRQ_XLPIN1         193
-#define IT83XX_IRQ_XLPIN2         194
-#define IT83XX_IRQ_XLPIN3         195
-#define IT83XX_IRQ_XLPIN4         196
-#define IT83XX_IRQ_XLPIN5         197
-#define IT83XX_IRQ_WEEK_ALARM     199
+#define IT83XX_IRQ_XLPIN0 192
+#define IT83XX_IRQ_XLPIN1 193
+#define IT83XX_IRQ_XLPIN2 194
+#define IT83XX_IRQ_XLPIN3 195
+#define IT83XX_IRQ_XLPIN4 196
+#define IT83XX_IRQ_XLPIN5 197
+#define IT83XX_IRQ_WEEK_ALARM 199
 /* Group 25 */
-#define IT83XX_IRQ_GPO0           200
-#define IT83XX_IRQ_GPO1           201
-#define IT83XX_IRQ_GPO2           202
-#define IT83XX_IRQ_GPO3           203
+#define IT83XX_IRQ_GPO0 200
+#define IT83XX_IRQ_GPO1 201
+#define IT83XX_IRQ_GPO2 202
+#define IT83XX_IRQ_GPO3 203
 /* Group 26 */
-#define IT83XX_IRQ_GPP0           208
-#define IT83XX_IRQ_GPP1           209
-#define IT83XX_IRQ_GPP2           210
-#define IT83XX_IRQ_GPP3           211
-#define IT83XX_IRQ_GPP4           212
-#define IT83XX_IRQ_GPP5           213
-#define IT83XX_IRQ_GPP6           214
+#define IT83XX_IRQ_GPP0 208
+#define IT83XX_IRQ_GPP1 209
+#define IT83XX_IRQ_GPP2 210
+#define IT83XX_IRQ_GPP3 211
+#define IT83XX_IRQ_GPP4 212
+#define IT83XX_IRQ_GPP5 213
+#define IT83XX_IRQ_GPP6 214
 /* Group 27 */
-#define IT83XX_IRQ_GPQ0           216
-#define IT83XX_IRQ_GPQ1           217
-#define IT83XX_IRQ_GPQ2           218
-#define IT83XX_IRQ_GPQ3           219
-#define IT83XX_IRQ_GPQ4           220
-#define IT83XX_IRQ_GPQ5           221
+#define IT83XX_IRQ_GPQ0 216
+#define IT83XX_IRQ_GPQ1 217
+#define IT83XX_IRQ_GPQ2 218
+#define IT83XX_IRQ_GPQ3 219
+#define IT83XX_IRQ_GPQ4 220
+#define IT83XX_IRQ_GPQ5 221
 /* Group 28 */
-#define IT83XX_IRQ_GPR0           224
-#define IT83XX_IRQ_GPR1           225
-#define IT83XX_IRQ_GPR2           226
-#define IT83XX_IRQ_GPR3           227
-#define IT83XX_IRQ_GPR4           228
-#define IT83XX_IRQ_GPR5           229
-
-#define IT83XX_IRQ_COUNT          230
+#define IT83XX_IRQ_GPR0 224
+#define IT83XX_IRQ_GPR1 225
+#define IT83XX_IRQ_GPR2 226
+#define IT83XX_IRQ_GPR3 227
+#define IT83XX_IRQ_GPR4 228
+#define IT83XX_IRQ_GPR5 229
+
+#define IT83XX_IRQ_COUNT 230
 #endif /* !defined(CHIP_FAMILY_IT8320) */
 
 /* IRQ dispatching to CPU INT vectors */
-#define IT83XX_CPU_INT_IRQ_1       2
-#define IT83XX_CPU_INT_IRQ_2       5
-#define IT83XX_CPU_INT_IRQ_3       4
-#define IT83XX_CPU_INT_IRQ_4       6
-#define IT83XX_CPU_INT_IRQ_5       2
-#define IT83XX_CPU_INT_IRQ_6       2
-#define IT83XX_CPU_INT_IRQ_7       4
-#define IT83XX_CPU_INT_IRQ_8       7
-#define IT83XX_CPU_INT_IRQ_9       6
-#define IT83XX_CPU_INT_IRQ_10      6
-#define IT83XX_CPU_INT_IRQ_11      5
-#define IT83XX_CPU_INT_IRQ_12      2
-#define IT83XX_CPU_INT_IRQ_13      2
-#define IT83XX_CPU_INT_IRQ_14      2
-#define IT83XX_CPU_INT_IRQ_15      8
-#define IT83XX_CPU_INT_IRQ_16      6
-#define IT83XX_CPU_INT_IRQ_17      2
-#define IT83XX_CPU_INT_IRQ_18      8
-#define IT83XX_CPU_INT_IRQ_19      8
-#define IT83XX_CPU_INT_IRQ_20      8
-#define IT83XX_CPU_INT_IRQ_21      2
-#define IT83XX_CPU_INT_IRQ_22     12
-#define IT83XX_CPU_INT_IRQ_23     12
-#define IT83XX_CPU_INT_IRQ_24      5
-#define IT83XX_CPU_INT_IRQ_25      4
-#define IT83XX_CPU_INT_IRQ_26      4
-#define IT83XX_CPU_INT_IRQ_27      4
-#define IT83XX_CPU_INT_IRQ_28     11
-#define IT83XX_CPU_INT_IRQ_29     11
-#define IT83XX_CPU_INT_IRQ_30      3
-#define IT83XX_CPU_INT_IRQ_31      2
-#define IT83XX_CPU_INT_IRQ_32     11
-#define IT83XX_CPU_INT_IRQ_33     11
-#define IT83XX_CPU_INT_IRQ_34     11
-#define IT83XX_CPU_INT_IRQ_35     11
-#define IT83XX_CPU_INT_IRQ_36      8
-#define IT83XX_CPU_INT_IRQ_37      9
-#define IT83XX_CPU_INT_IRQ_38      9
-#define IT83XX_CPU_INT_IRQ_39      9
-#define IT83XX_CPU_INT_IRQ_40      2
-#define IT83XX_CPU_INT_IRQ_41      2
-#define IT83XX_CPU_INT_IRQ_42      2
-#define IT83XX_CPU_INT_IRQ_43      2
-#define IT83XX_CPU_INT_IRQ_44      2
-#define IT83XX_CPU_INT_IRQ_45      2
-#define IT83XX_CPU_INT_IRQ_46      2
-#define IT83XX_CPU_INT_IRQ_47      2
-#define IT83XX_CPU_INT_IRQ_48      2
-#define IT83XX_CPU_INT_IRQ_49      2
-#define IT83XX_CPU_INT_IRQ_50      2
-#define IT83XX_CPU_INT_IRQ_51      2
-#define IT83XX_CPU_INT_IRQ_52      2
-#define IT83XX_CPU_INT_IRQ_53      2
-#define IT83XX_CPU_INT_IRQ_54      2
-#define IT83XX_CPU_INT_IRQ_55      2
-#define IT83XX_CPU_INT_IRQ_56     10
-#define IT83XX_CPU_INT_IRQ_57     10
-#define IT83XX_CPU_INT_IRQ_58      3
-#define IT83XX_CPU_INT_IRQ_59     12
-#define IT83XX_CPU_INT_IRQ_60      3
-#define IT83XX_CPU_INT_IRQ_61      3
-#define IT83XX_CPU_INT_IRQ_62      3
-#define IT83XX_CPU_INT_IRQ_63      3
-#define IT83XX_CPU_INT_IRQ_64      4
-#define IT83XX_CPU_INT_IRQ_65      4
-#define IT83XX_CPU_INT_IRQ_66      4
-#define IT83XX_CPU_INT_IRQ_67      4
-#define IT83XX_CPU_INT_IRQ_68      4
-#define IT83XX_CPU_INT_IRQ_69      4
-#define IT83XX_CPU_INT_IRQ_71     12
-#define IT83XX_CPU_INT_IRQ_72      2
-#define IT83XX_CPU_INT_IRQ_73      2
-#define IT83XX_CPU_INT_IRQ_74      2
-#define IT83XX_CPU_INT_IRQ_75      2
-#define IT83XX_CPU_INT_IRQ_76      2
-#define IT83XX_CPU_INT_IRQ_77      2
-#define IT83XX_CPU_INT_IRQ_78      2
-#define IT83XX_CPU_INT_IRQ_79      2
-#define IT83XX_CPU_INT_IRQ_80      3
-#define IT83XX_CPU_INT_IRQ_81      6
-#define IT83XX_CPU_INT_IRQ_82     12
-#define IT83XX_CPU_INT_IRQ_83     12
-#define IT83XX_CPU_INT_IRQ_84      5
-#define IT83XX_CPU_INT_IRQ_85      2
-#define IT83XX_CPU_INT_IRQ_86      2
-#define IT83XX_CPU_INT_IRQ_87      2
-#define IT83XX_CPU_INT_IRQ_88      2
-#define IT83XX_CPU_INT_IRQ_89      2
-#define IT83XX_CPU_INT_IRQ_90      2
-#define IT83XX_CPU_INT_IRQ_91      2
-#define IT83XX_CPU_INT_IRQ_92      2
-#define IT83XX_CPU_INT_IRQ_93      2
-#define IT83XX_CPU_INT_IRQ_94      2
-#define IT83XX_CPU_INT_IRQ_95      2
-#define IT83XX_CPU_INT_IRQ_96      2
-#define IT83XX_CPU_INT_IRQ_97      2
-#define IT83XX_CPU_INT_IRQ_98      2
-#define IT83XX_CPU_INT_IRQ_99      2
-#define IT83XX_CPU_INT_IRQ_100     2
-#define IT83XX_CPU_INT_IRQ_101     2
-#define IT83XX_CPU_INT_IRQ_102     2
-#define IT83XX_CPU_INT_IRQ_103     2
-#define IT83XX_CPU_INT_IRQ_104     2
-#define IT83XX_CPU_INT_IRQ_105     2
-#define IT83XX_CPU_INT_IRQ_106     2
-#define IT83XX_CPU_INT_IRQ_107     2
-#define IT83XX_CPU_INT_IRQ_108     2
-#define IT83XX_CPU_INT_IRQ_109     2
-#define IT83XX_CPU_INT_IRQ_110     2
-#define IT83XX_CPU_INT_IRQ_111     2
-#define IT83XX_CPU_INT_IRQ_112     2
-#define IT83XX_CPU_INT_IRQ_113     2
-#define IT83XX_CPU_INT_IRQ_114     2
-#define IT83XX_CPU_INT_IRQ_115     2
-#define IT83XX_CPU_INT_IRQ_116     2
-#define IT83XX_CPU_INT_IRQ_117     2
-#define IT83XX_CPU_INT_IRQ_118     2
-#define IT83XX_CPU_INT_IRQ_119     2
-#define IT83XX_CPU_INT_IRQ_120     2
-#define IT83XX_CPU_INT_IRQ_121     2
-#define IT83XX_CPU_INT_IRQ_122     2
-#define IT83XX_CPU_INT_IRQ_123     2
-#define IT83XX_CPU_INT_IRQ_124     2
-#define IT83XX_CPU_INT_IRQ_125     2
-#define IT83XX_CPU_INT_IRQ_126     2
-#define IT83XX_CPU_INT_IRQ_127     2
-#define IT83XX_CPU_INT_IRQ_128     2
-#define IT83XX_CPU_INT_IRQ_129     2
-#define IT83XX_CPU_INT_IRQ_130     2
-#define IT83XX_CPU_INT_IRQ_131     2
-#define IT83XX_CPU_INT_IRQ_132     2
-#define IT83XX_CPU_INT_IRQ_133     2
-#define IT83XX_CPU_INT_IRQ_134     2
-#define IT83XX_CPU_INT_IRQ_135     2
-#define IT83XX_CPU_INT_IRQ_136     2
-#define IT83XX_CPU_INT_IRQ_137     2
-#define IT83XX_CPU_INT_IRQ_138     2
-#define IT83XX_CPU_INT_IRQ_139     2
-#define IT83XX_CPU_INT_IRQ_140     2
-#define IT83XX_CPU_INT_IRQ_141     2
-#define IT83XX_CPU_INT_IRQ_142     2
-#define IT83XX_CPU_INT_IRQ_143     2
-#define IT83XX_CPU_INT_IRQ_144     2
-#define IT83XX_CPU_INT_IRQ_145     2
-#define IT83XX_CPU_INT_IRQ_146     2
-#define IT83XX_CPU_INT_IRQ_147     2
-#define IT83XX_CPU_INT_IRQ_149     4
-#define IT83XX_CPU_INT_IRQ_150     4
-#define IT83XX_CPU_INT_IRQ_151     7
-#define IT83XX_CPU_INT_IRQ_152     6
-#define IT83XX_CPU_INT_IRQ_153     6
-#define IT83XX_CPU_INT_IRQ_154    12
-#define IT83XX_CPU_INT_IRQ_155     3
-#define IT83XX_CPU_INT_IRQ_156     3
-#define IT83XX_CPU_INT_IRQ_157     3
-#define IT83XX_CPU_INT_IRQ_158     3
-#define IT83XX_CPU_INT_IRQ_159     3
-#define IT83XX_CPU_INT_IRQ_160    12
-#define IT83XX_CPU_INT_IRQ_161    12
-#define IT83XX_CPU_INT_IRQ_162    12
-#define IT83XX_CPU_INT_IRQ_163    12
-#define IT83XX_CPU_INT_IRQ_164    12
-#define IT83XX_CPU_INT_IRQ_165    12
-#define IT83XX_CPU_INT_IRQ_166    12
-#define IT83XX_CPU_INT_IRQ_167    12
-#define IT83XX_CPU_INT_IRQ_168     2
-#define IT83XX_CPU_INT_IRQ_169     2
+#define IT83XX_CPU_INT_IRQ_1 2
+#define IT83XX_CPU_INT_IRQ_2 5
+#define IT83XX_CPU_INT_IRQ_3 4
+#define IT83XX_CPU_INT_IRQ_4 6
+#define IT83XX_CPU_INT_IRQ_5 2
+#define IT83XX_CPU_INT_IRQ_6 2
+#define IT83XX_CPU_INT_IRQ_7 4
+#define IT83XX_CPU_INT_IRQ_8 7
+#define IT83XX_CPU_INT_IRQ_9 6
+#define IT83XX_CPU_INT_IRQ_10 6
+#define IT83XX_CPU_INT_IRQ_11 5
+#define IT83XX_CPU_INT_IRQ_12 2
+#define IT83XX_CPU_INT_IRQ_13 2
+#define IT83XX_CPU_INT_IRQ_14 2
+#define IT83XX_CPU_INT_IRQ_15 8
+#define IT83XX_CPU_INT_IRQ_16 6
+#define IT83XX_CPU_INT_IRQ_17 2
+#define IT83XX_CPU_INT_IRQ_18 8
+#define IT83XX_CPU_INT_IRQ_19 8
+#define IT83XX_CPU_INT_IRQ_20 8
+#define IT83XX_CPU_INT_IRQ_21 2
+#define IT83XX_CPU_INT_IRQ_22 12
+#define IT83XX_CPU_INT_IRQ_23 12
+#define IT83XX_CPU_INT_IRQ_24 5
+#define IT83XX_CPU_INT_IRQ_25 4
+#define IT83XX_CPU_INT_IRQ_26 4
+#define IT83XX_CPU_INT_IRQ_27 4
+#define IT83XX_CPU_INT_IRQ_28 11
+#define IT83XX_CPU_INT_IRQ_29 11
+#define IT83XX_CPU_INT_IRQ_30 3
+#define IT83XX_CPU_INT_IRQ_31 2
+#define IT83XX_CPU_INT_IRQ_32 11
+#define IT83XX_CPU_INT_IRQ_33 11
+#define IT83XX_CPU_INT_IRQ_34 11
+#define IT83XX_CPU_INT_IRQ_35 11
+#define IT83XX_CPU_INT_IRQ_36 8
+#define IT83XX_CPU_INT_IRQ_37 9
+#define IT83XX_CPU_INT_IRQ_38 9
+#define IT83XX_CPU_INT_IRQ_39 9
+#define IT83XX_CPU_INT_IRQ_40 2
+#define IT83XX_CPU_INT_IRQ_41 2
+#define IT83XX_CPU_INT_IRQ_42 2
+#define IT83XX_CPU_INT_IRQ_43 2
+#define IT83XX_CPU_INT_IRQ_44 2
+#define IT83XX_CPU_INT_IRQ_45 2
+#define IT83XX_CPU_INT_IRQ_46 2
+#define IT83XX_CPU_INT_IRQ_47 2
+#define IT83XX_CPU_INT_IRQ_48 2
+#define IT83XX_CPU_INT_IRQ_49 2
+#define IT83XX_CPU_INT_IRQ_50 2
+#define IT83XX_CPU_INT_IRQ_51 2
+#define IT83XX_CPU_INT_IRQ_52 2
+#define IT83XX_CPU_INT_IRQ_53 2
+#define IT83XX_CPU_INT_IRQ_54 2
+#define IT83XX_CPU_INT_IRQ_55 2
+#define IT83XX_CPU_INT_IRQ_56 10
+#define IT83XX_CPU_INT_IRQ_57 10
+#define IT83XX_CPU_INT_IRQ_58 3
+#define IT83XX_CPU_INT_IRQ_59 12
+#define IT83XX_CPU_INT_IRQ_60 3
+#define IT83XX_CPU_INT_IRQ_61 3
+#define IT83XX_CPU_INT_IRQ_62 3
+#define IT83XX_CPU_INT_IRQ_63 3
+#define IT83XX_CPU_INT_IRQ_64 4
+#define IT83XX_CPU_INT_IRQ_65 4
+#define IT83XX_CPU_INT_IRQ_66 4
+#define IT83XX_CPU_INT_IRQ_67 4
+#define IT83XX_CPU_INT_IRQ_68 4
+#define IT83XX_CPU_INT_IRQ_69 4
+#define IT83XX_CPU_INT_IRQ_71 12
+#define IT83XX_CPU_INT_IRQ_72 2
+#define IT83XX_CPU_INT_IRQ_73 2
+#define IT83XX_CPU_INT_IRQ_74 2
+#define IT83XX_CPU_INT_IRQ_75 2
+#define IT83XX_CPU_INT_IRQ_76 2
+#define IT83XX_CPU_INT_IRQ_77 2
+#define IT83XX_CPU_INT_IRQ_78 2
+#define IT83XX_CPU_INT_IRQ_79 2
+#define IT83XX_CPU_INT_IRQ_80 3
+#define IT83XX_CPU_INT_IRQ_81 6
+#define IT83XX_CPU_INT_IRQ_82 12
+#define IT83XX_CPU_INT_IRQ_83 12
+#define IT83XX_CPU_INT_IRQ_84 5
+#define IT83XX_CPU_INT_IRQ_85 2
+#define IT83XX_CPU_INT_IRQ_86 2
+#define IT83XX_CPU_INT_IRQ_87 2
+#define IT83XX_CPU_INT_IRQ_88 2
+#define IT83XX_CPU_INT_IRQ_89 2
+#define IT83XX_CPU_INT_IRQ_90 2
+#define IT83XX_CPU_INT_IRQ_91 2
+#define IT83XX_CPU_INT_IRQ_92 2
+#define IT83XX_CPU_INT_IRQ_93 2
+#define IT83XX_CPU_INT_IRQ_94 2
+#define IT83XX_CPU_INT_IRQ_95 2
+#define IT83XX_CPU_INT_IRQ_96 2
+#define IT83XX_CPU_INT_IRQ_97 2
+#define IT83XX_CPU_INT_IRQ_98 2
+#define IT83XX_CPU_INT_IRQ_99 2
+#define IT83XX_CPU_INT_IRQ_100 2
+#define IT83XX_CPU_INT_IRQ_101 2
+#define IT83XX_CPU_INT_IRQ_102 2
+#define IT83XX_CPU_INT_IRQ_103 2
+#define IT83XX_CPU_INT_IRQ_104 2
+#define IT83XX_CPU_INT_IRQ_105 2
+#define IT83XX_CPU_INT_IRQ_106 2
+#define IT83XX_CPU_INT_IRQ_107 2
+#define IT83XX_CPU_INT_IRQ_108 2
+#define IT83XX_CPU_INT_IRQ_109 2
+#define IT83XX_CPU_INT_IRQ_110 2
+#define IT83XX_CPU_INT_IRQ_111 2
+#define IT83XX_CPU_INT_IRQ_112 2
+#define IT83XX_CPU_INT_IRQ_113 2
+#define IT83XX_CPU_INT_IRQ_114 2
+#define IT83XX_CPU_INT_IRQ_115 2
+#define IT83XX_CPU_INT_IRQ_116 2
+#define IT83XX_CPU_INT_IRQ_117 2
+#define IT83XX_CPU_INT_IRQ_118 2
+#define IT83XX_CPU_INT_IRQ_119 2
+#define IT83XX_CPU_INT_IRQ_120 2
+#define IT83XX_CPU_INT_IRQ_121 2
+#define IT83XX_CPU_INT_IRQ_122 2
+#define IT83XX_CPU_INT_IRQ_123 2
+#define IT83XX_CPU_INT_IRQ_124 2
+#define IT83XX_CPU_INT_IRQ_125 2
+#define IT83XX_CPU_INT_IRQ_126 2
+#define IT83XX_CPU_INT_IRQ_127 2
+#define IT83XX_CPU_INT_IRQ_128 2
+#define IT83XX_CPU_INT_IRQ_129 2
+#define IT83XX_CPU_INT_IRQ_130 2
+#define IT83XX_CPU_INT_IRQ_131 2
+#define IT83XX_CPU_INT_IRQ_132 2
+#define IT83XX_CPU_INT_IRQ_133 2
+#define IT83XX_CPU_INT_IRQ_134 2
+#define IT83XX_CPU_INT_IRQ_135 2
+#define IT83XX_CPU_INT_IRQ_136 2
+#define IT83XX_CPU_INT_IRQ_137 2
+#define IT83XX_CPU_INT_IRQ_138 2
+#define IT83XX_CPU_INT_IRQ_139 2
+#define IT83XX_CPU_INT_IRQ_140 2
+#define IT83XX_CPU_INT_IRQ_141 2
+#define IT83XX_CPU_INT_IRQ_142 2
+#define IT83XX_CPU_INT_IRQ_143 2
+#define IT83XX_CPU_INT_IRQ_144 2
+#define IT83XX_CPU_INT_IRQ_145 2
+#define IT83XX_CPU_INT_IRQ_146 2
+#define IT83XX_CPU_INT_IRQ_147 2
+#define IT83XX_CPU_INT_IRQ_149 4
+#define IT83XX_CPU_INT_IRQ_150 4
+#define IT83XX_CPU_INT_IRQ_151 7
+#define IT83XX_CPU_INT_IRQ_152 6
+#define IT83XX_CPU_INT_IRQ_153 6
+#define IT83XX_CPU_INT_IRQ_154 12
+#define IT83XX_CPU_INT_IRQ_155 3
+#define IT83XX_CPU_INT_IRQ_156 3
+#define IT83XX_CPU_INT_IRQ_157 3
+#define IT83XX_CPU_INT_IRQ_158 3
+#define IT83XX_CPU_INT_IRQ_159 3
+#define IT83XX_CPU_INT_IRQ_160 12
+#define IT83XX_CPU_INT_IRQ_161 12
+#define IT83XX_CPU_INT_IRQ_162 12
+#define IT83XX_CPU_INT_IRQ_163 12
+#define IT83XX_CPU_INT_IRQ_164 12
+#define IT83XX_CPU_INT_IRQ_165 12
+#define IT83XX_CPU_INT_IRQ_166 12
+#define IT83XX_CPU_INT_IRQ_167 12
+#define IT83XX_CPU_INT_IRQ_168 2
+#define IT83XX_CPU_INT_IRQ_169 2
 #if defined(CHIP_FAMILY_IT8320)
-#define IT83XX_CPU_INT_IRQ_170     2
-#define IT83XX_CPU_INT_IRQ_171     2
-#define IT83XX_CPU_INT_IRQ_172     2
-#define IT83XX_CPU_INT_IRQ_173     2
-#define IT83XX_CPU_INT_IRQ_174     2
-#define IT83XX_CPU_INT_IRQ_175     2
+#define IT83XX_CPU_INT_IRQ_170 2
+#define IT83XX_CPU_INT_IRQ_171 2
+#define IT83XX_CPU_INT_IRQ_172 2
+#define IT83XX_CPU_INT_IRQ_173 2
+#define IT83XX_CPU_INT_IRQ_174 2
+#define IT83XX_CPU_INT_IRQ_175 2
 #elif defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2)
-#define IT83XX_CPU_INT_IRQ_170    12
-#define IT83XX_CPU_INT_IRQ_171    12
-#define IT83XX_CPU_INT_IRQ_172    12
-#define IT83XX_CPU_INT_IRQ_173    12
-#define IT83XX_CPU_INT_IRQ_174    12
-#define IT83XX_CPU_INT_IRQ_175    12
+#define IT83XX_CPU_INT_IRQ_170 12
+#define IT83XX_CPU_INT_IRQ_171 12
+#define IT83XX_CPU_INT_IRQ_172 12
+#define IT83XX_CPU_INT_IRQ_173 12
+#define IT83XX_CPU_INT_IRQ_174 12
+#define IT83XX_CPU_INT_IRQ_175 12
 #endif
-#define IT83XX_CPU_INT_IRQ_176     2
-#define IT83XX_CPU_INT_IRQ_177     2
-#define IT83XX_CPU_INT_IRQ_178     2
-#define IT83XX_CPU_INT_IRQ_179     2
-#define IT83XX_CPU_INT_IRQ_180     2
-#define IT83XX_CPU_INT_IRQ_181     2
-#define IT83XX_CPU_INT_IRQ_182     2
-#define IT83XX_CPU_INT_IRQ_183     2
-#define IT83XX_CPU_INT_IRQ_184     2
-#define IT83XX_CPU_INT_IRQ_185     2
-#define IT83XX_CPU_INT_IRQ_191     2
-#define IT83XX_CPU_INT_IRQ_192     2
-#define IT83XX_CPU_INT_IRQ_193     2
-#define IT83XX_CPU_INT_IRQ_194     2
-#define IT83XX_CPU_INT_IRQ_195     2
-#define IT83XX_CPU_INT_IRQ_196     2
-#define IT83XX_CPU_INT_IRQ_197     2
-#define IT83XX_CPU_INT_IRQ_199     2
-#define IT83XX_CPU_INT_IRQ_200     2
-#define IT83XX_CPU_INT_IRQ_201     2
-#define IT83XX_CPU_INT_IRQ_202     2
-#define IT83XX_CPU_INT_IRQ_203     2
-#define IT83XX_CPU_INT_IRQ_208     2
-#define IT83XX_CPU_INT_IRQ_209     2
-#define IT83XX_CPU_INT_IRQ_210     2
-#define IT83XX_CPU_INT_IRQ_211     2
-#define IT83XX_CPU_INT_IRQ_212     2
-#define IT83XX_CPU_INT_IRQ_213     2
-#define IT83XX_CPU_INT_IRQ_214     2
-#define IT83XX_CPU_INT_IRQ_216     2
-#define IT83XX_CPU_INT_IRQ_217     2
-#define IT83XX_CPU_INT_IRQ_218     2
-#define IT83XX_CPU_INT_IRQ_219     2
-#define IT83XX_CPU_INT_IRQ_220     2
-#define IT83XX_CPU_INT_IRQ_221     2
-#define IT83XX_CPU_INT_IRQ_224     2
-#define IT83XX_CPU_INT_IRQ_225     2
-#define IT83XX_CPU_INT_IRQ_226     2
-#define IT83XX_CPU_INT_IRQ_227     2
-#define IT83XX_CPU_INT_IRQ_228     2
-#define IT83XX_CPU_INT_IRQ_229     2
+#define IT83XX_CPU_INT_IRQ_176 2
+#define IT83XX_CPU_INT_IRQ_177 2
+#define IT83XX_CPU_INT_IRQ_178 2
+#define IT83XX_CPU_INT_IRQ_179 2
+#define IT83XX_CPU_INT_IRQ_180 2
+#define IT83XX_CPU_INT_IRQ_181 2
+#define IT83XX_CPU_INT_IRQ_182 2
+#define IT83XX_CPU_INT_IRQ_183 2
+#define IT83XX_CPU_INT_IRQ_184 2
+#define IT83XX_CPU_INT_IRQ_185 2
+#define IT83XX_CPU_INT_IRQ_191 2
+#define IT83XX_CPU_INT_IRQ_192 2
+#define IT83XX_CPU_INT_IRQ_193 2
+#define IT83XX_CPU_INT_IRQ_194 2
+#define IT83XX_CPU_INT_IRQ_195 2
+#define IT83XX_CPU_INT_IRQ_196 2
+#define IT83XX_CPU_INT_IRQ_197 2
+#define IT83XX_CPU_INT_IRQ_199 2
+#define IT83XX_CPU_INT_IRQ_200 2
+#define IT83XX_CPU_INT_IRQ_201 2
+#define IT83XX_CPU_INT_IRQ_202 2
+#define IT83XX_CPU_INT_IRQ_203 2
+#define IT83XX_CPU_INT_IRQ_208 2
+#define IT83XX_CPU_INT_IRQ_209 2
+#define IT83XX_CPU_INT_IRQ_210 2
+#define IT83XX_CPU_INT_IRQ_211 2
+#define IT83XX_CPU_INT_IRQ_212 2
+#define IT83XX_CPU_INT_IRQ_213 2
+#define IT83XX_CPU_INT_IRQ_214 2
+#define IT83XX_CPU_INT_IRQ_216 2
+#define IT83XX_CPU_INT_IRQ_217 2
+#define IT83XX_CPU_INT_IRQ_218 2
+#define IT83XX_CPU_INT_IRQ_219 2
+#define IT83XX_CPU_INT_IRQ_220 2
+#define IT83XX_CPU_INT_IRQ_221 2
+#define IT83XX_CPU_INT_IRQ_224 2
+#define IT83XX_CPU_INT_IRQ_225 2
+#define IT83XX_CPU_INT_IRQ_226 2
+#define IT83XX_CPU_INT_IRQ_227 2
+#define IT83XX_CPU_INT_IRQ_228 2
+#define IT83XX_CPU_INT_IRQ_229 2
 
 /* "Fake" IRQ to declare in readable fashion all WKO IRQ routed to INT#2 */
-#define CPU_INT_2_ALL_GPIOS      255
-#define IT83XX_CPU_INT_IRQ_255     2
+#define CPU_INT_2_ALL_GPIOS 255
+#define IT83XX_CPU_INT_IRQ_255 2
 
-#define CPU_INT_GROUP_5          254
-#define IT83XX_CPU_INT_IRQ_254     5
+#define CPU_INT_GROUP_5 254
+#define IT83XX_CPU_INT_IRQ_254 5
 
-#define CPU_INT_GROUP_4          252
-#define IT83XX_CPU_INT_IRQ_252     4
+#define CPU_INT_GROUP_4 252
+#define IT83XX_CPU_INT_IRQ_252 4
 
-#define CPU_INT_GROUP_12         253
-#define IT83XX_CPU_INT_IRQ_253    12
+#define CPU_INT_GROUP_12 253
+#define IT83XX_CPU_INT_IRQ_253 12
 
-#define CPU_INT_GROUP_3          251
-#define IT83XX_CPU_INT_IRQ_251     3
+#define CPU_INT_GROUP_3 251
+#define IT83XX_CPU_INT_IRQ_251 3
 
-#define CPU_INT_GROUP_6          250
-#define IT83XX_CPU_INT_IRQ_250     6
+#define CPU_INT_GROUP_6 250
+#define IT83XX_CPU_INT_IRQ_250 6
 
-#define CPU_INT_GROUP_9          249
-#define IT83XX_CPU_INT_IRQ_249     9
+#define CPU_INT_GROUP_9 249
+#define IT83XX_CPU_INT_IRQ_249 9
 
-#define CPU_INT_GROUP_7          248
-#define IT83XX_CPU_INT_IRQ_248     7
+#define CPU_INT_GROUP_7 248
+#define IT83XX_CPU_INT_IRQ_248 7
 
 #define CPU_INT(irq) CONCAT2(IT83XX_CPU_INT_IRQ_, irq)
 
 /* --- INTC --- */
-#define IT83XX_INTC_BASE    CHIP_EC_INTC_BASE
-
-#define IT83XX_INTC_REG(n)  REG8(IT83XX_INTC_BASE+(n))
-
-#define IT83XX_INTC_AIVCT   REG8(IT83XX_INTC_BASE+0x10)
-
-#define IT83XX_INTC_IER0    REG8(IT83XX_INTC_BASE+0x04)
-#define IT83XX_INTC_IER1    REG8(IT83XX_INTC_BASE+0x05)
-#define IT83XX_INTC_IER2    REG8(IT83XX_INTC_BASE+0x06)
-#define IT83XX_INTC_IER3    REG8(IT83XX_INTC_BASE+0x07)
-#define IT83XX_INTC_IER4    REG8(IT83XX_INTC_BASE+0x15)
-#define IT83XX_INTC_IER5    REG8(IT83XX_INTC_BASE+0x19)
-#define IT83XX_INTC_IER6    REG8(IT83XX_INTC_BASE+0x1d)
-#define IT83XX_INTC_IER7    REG8(IT83XX_INTC_BASE+0x21)
-#define IT83XX_INTC_IER8    REG8(IT83XX_INTC_BASE+0x25)
-#define IT83XX_INTC_IER9    REG8(IT83XX_INTC_BASE+0x29)
-#define IT83XX_INTC_IER10   REG8(IT83XX_INTC_BASE+0x2d)
-#define IT83XX_INTC_IER11   REG8(IT83XX_INTC_BASE+0x31)
-#define IT83XX_INTC_IER12   REG8(IT83XX_INTC_BASE+0x35)
-#define IT83XX_INTC_IER13   REG8(IT83XX_INTC_BASE+0x39)
-#define IT83XX_INTC_IER14   REG8(IT83XX_INTC_BASE+0x3d)
-#define IT83XX_INTC_IER15   REG8(IT83XX_INTC_BASE+0x41)
-#define IT83XX_INTC_IER16   REG8(IT83XX_INTC_BASE+0x45)
-#define IT83XX_INTC_IER17   REG8(IT83XX_INTC_BASE+0x49)
-#define IT83XX_INTC_IER18   REG8(IT83XX_INTC_BASE+0x4d)
-#define IT83XX_INTC_IER19   REG8(IT83XX_INTC_BASE+0x51)
-#define IT83XX_INTC_IER20   REG8(IT83XX_INTC_BASE+0x55)
-#define IT83XX_INTC_IER21   REG8(IT83XX_INTC_BASE+0x59)
-#define IT83XX_INTC_IER22   REG8(IT83XX_INTC_BASE+0x5d)
-#define IT83XX_INTC_IER23   REG8(IT83XX_INTC_BASE+0x91)
-#define IT83XX_INTC_IER24   REG8(IT83XX_INTC_BASE+0x95)
-#define IT83XX_INTC_IER25   REG8(IT83XX_INTC_BASE+0x99)
-#define IT83XX_INTC_IER26   REG8(IT83XX_INTC_BASE+0x9d)
-#define IT83XX_INTC_IER27   REG8(IT83XX_INTC_BASE+0xa1)
-#define IT83XX_INTC_IER28   REG8(IT83XX_INTC_BASE+0xa5)
-
-#define IT83XX_INTC_ISR0    REG8(IT83XX_INTC_BASE+0x00)
-#define IT83XX_INTC_ISR1    REG8(IT83XX_INTC_BASE+0x01)
-#define IT83XX_INTC_ISR2    REG8(IT83XX_INTC_BASE+0x02)
-#define IT83XX_INTC_ISR3    REG8(IT83XX_INTC_BASE+0x03)
-#define IT83XX_INTC_ISR4    REG8(IT83XX_INTC_BASE+0x14)
-#define IT83XX_INTC_ISR5    REG8(IT83XX_INTC_BASE+0x18)
-#define IT83XX_INTC_ISR6    REG8(IT83XX_INTC_BASE+0x1c)
-#define IT83XX_INTC_ISR7    REG8(IT83XX_INTC_BASE+0x20)
-#define IT83XX_INTC_ISR8    REG8(IT83XX_INTC_BASE+0x24)
-#define IT83XX_INTC_ISR9    REG8(IT83XX_INTC_BASE+0x28)
-#define IT83XX_INTC_ISR10   REG8(IT83XX_INTC_BASE+0x2c)
-#define IT83XX_INTC_ISR11   REG8(IT83XX_INTC_BASE+0x30)
-#define IT83XX_INTC_ISR12   REG8(IT83XX_INTC_BASE+0x34)
-#define IT83XX_INTC_ISR13   REG8(IT83XX_INTC_BASE+0x38)
-#define IT83XX_INTC_ISR14   REG8(IT83XX_INTC_BASE+0x3c)
-#define IT83XX_INTC_ISR15   REG8(IT83XX_INTC_BASE+0x40)
-#define IT83XX_INTC_ISR16   REG8(IT83XX_INTC_BASE+0x44)
-#define IT83XX_INTC_ISR17   REG8(IT83XX_INTC_BASE+0x48)
-#define IT83XX_INTC_ISR18   REG8(IT83XX_INTC_BASE+0x4c)
-#define IT83XX_INTC_ISR19   REG8(IT83XX_INTC_BASE+0x50)
-#define IT83XX_INTC_ISR20   REG8(IT83XX_INTC_BASE+0x54)
-#define IT83XX_INTC_ISR21   REG8(IT83XX_INTC_BASE+0x58)
-#define IT83XX_INTC_ISR22   REG8(IT83XX_INTC_BASE+0x5c)
-#define IT83XX_INTC_ISR23   REG8(IT83XX_INTC_BASE+0x90)
-#define IT83XX_INTC_ISR24   REG8(IT83XX_INTC_BASE+0x94)
-#define IT83XX_INTC_ISR25   REG8(IT83XX_INTC_BASE+0x98)
-#define IT83XX_INTC_ISR26   REG8(IT83XX_INTC_BASE+0x9c)
-#define IT83XX_INTC_ISR27   REG8(IT83XX_INTC_BASE+0xa0)
-#define IT83XX_INTC_ISR28   REG8(IT83XX_INTC_BASE+0xa4)
-
-#define IT83XX_INTC_IELMR10 REG8(IT83XX_INTC_BASE+0x2E)
-#define IT83XX_INTC_IPOLR10 REG8(IT83XX_INTC_BASE+0x2F)
-#define IT83XX_INTC_IELMR19 REG8(IT83XX_INTC_BASE+0x52)
-#define IT83XX_INTC_IPOLR19 REG8(IT83XX_INTC_BASE+0x53)
+#define IT83XX_INTC_BASE CHIP_EC_INTC_BASE
+
+#define IT83XX_INTC_REG(n) REG8(IT83XX_INTC_BASE + (n))
+
+#define IT83XX_INTC_AIVCT REG8(IT83XX_INTC_BASE + 0x10)
+
+#define IT83XX_INTC_IER0 REG8(IT83XX_INTC_BASE + 0x04)
+#define IT83XX_INTC_IER1 REG8(IT83XX_INTC_BASE + 0x05)
+#define IT83XX_INTC_IER2 REG8(IT83XX_INTC_BASE + 0x06)
+#define IT83XX_INTC_IER3 REG8(IT83XX_INTC_BASE + 0x07)
+#define IT83XX_INTC_IER4 REG8(IT83XX_INTC_BASE + 0x15)
+#define IT83XX_INTC_IER5 REG8(IT83XX_INTC_BASE + 0x19)
+#define IT83XX_INTC_IER6 REG8(IT83XX_INTC_BASE + 0x1d)
+#define IT83XX_INTC_IER7 REG8(IT83XX_INTC_BASE + 0x21)
+#define IT83XX_INTC_IER8 REG8(IT83XX_INTC_BASE + 0x25)
+#define IT83XX_INTC_IER9 REG8(IT83XX_INTC_BASE + 0x29)
+#define IT83XX_INTC_IER10 REG8(IT83XX_INTC_BASE + 0x2d)
+#define IT83XX_INTC_IER11 REG8(IT83XX_INTC_BASE + 0x31)
+#define IT83XX_INTC_IER12 REG8(IT83XX_INTC_BASE + 0x35)
+#define IT83XX_INTC_IER13 REG8(IT83XX_INTC_BASE + 0x39)
+#define IT83XX_INTC_IER14 REG8(IT83XX_INTC_BASE + 0x3d)
+#define IT83XX_INTC_IER15 REG8(IT83XX_INTC_BASE + 0x41)
+#define IT83XX_INTC_IER16 REG8(IT83XX_INTC_BASE + 0x45)
+#define IT83XX_INTC_IER17 REG8(IT83XX_INTC_BASE + 0x49)
+#define IT83XX_INTC_IER18 REG8(IT83XX_INTC_BASE + 0x4d)
+#define IT83XX_INTC_IER19 REG8(IT83XX_INTC_BASE + 0x51)
+#define IT83XX_INTC_IER20 REG8(IT83XX_INTC_BASE + 0x55)
+#define IT83XX_INTC_IER21 REG8(IT83XX_INTC_BASE + 0x59)
+#define IT83XX_INTC_IER22 REG8(IT83XX_INTC_BASE + 0x5d)
+#define IT83XX_INTC_IER23 REG8(IT83XX_INTC_BASE + 0x91)
+#define IT83XX_INTC_IER24 REG8(IT83XX_INTC_BASE + 0x95)
+#define IT83XX_INTC_IER25 REG8(IT83XX_INTC_BASE + 0x99)
+#define IT83XX_INTC_IER26 REG8(IT83XX_INTC_BASE + 0x9d)
+#define IT83XX_INTC_IER27 REG8(IT83XX_INTC_BASE + 0xa1)
+#define IT83XX_INTC_IER28 REG8(IT83XX_INTC_BASE + 0xa5)
+
+#define IT83XX_INTC_ISR0 REG8(IT83XX_INTC_BASE + 0x00)
+#define IT83XX_INTC_ISR1 REG8(IT83XX_INTC_BASE + 0x01)
+#define IT83XX_INTC_ISR2 REG8(IT83XX_INTC_BASE + 0x02)
+#define IT83XX_INTC_ISR3 REG8(IT83XX_INTC_BASE + 0x03)
+#define IT83XX_INTC_ISR4 REG8(IT83XX_INTC_BASE + 0x14)
+#define IT83XX_INTC_ISR5 REG8(IT83XX_INTC_BASE + 0x18)
+#define IT83XX_INTC_ISR6 REG8(IT83XX_INTC_BASE + 0x1c)
+#define IT83XX_INTC_ISR7 REG8(IT83XX_INTC_BASE + 0x20)
+#define IT83XX_INTC_ISR8 REG8(IT83XX_INTC_BASE + 0x24)
+#define IT83XX_INTC_ISR9 REG8(IT83XX_INTC_BASE + 0x28)
+#define IT83XX_INTC_ISR10 REG8(IT83XX_INTC_BASE + 0x2c)
+#define IT83XX_INTC_ISR11 REG8(IT83XX_INTC_BASE + 0x30)
+#define IT83XX_INTC_ISR12 REG8(IT83XX_INTC_BASE + 0x34)
+#define IT83XX_INTC_ISR13 REG8(IT83XX_INTC_BASE + 0x38)
+#define IT83XX_INTC_ISR14 REG8(IT83XX_INTC_BASE + 0x3c)
+#define IT83XX_INTC_ISR15 REG8(IT83XX_INTC_BASE + 0x40)
+#define IT83XX_INTC_ISR16 REG8(IT83XX_INTC_BASE + 0x44)
+#define IT83XX_INTC_ISR17 REG8(IT83XX_INTC_BASE + 0x48)
+#define IT83XX_INTC_ISR18 REG8(IT83XX_INTC_BASE + 0x4c)
+#define IT83XX_INTC_ISR19 REG8(IT83XX_INTC_BASE + 0x50)
+#define IT83XX_INTC_ISR20 REG8(IT83XX_INTC_BASE + 0x54)
+#define IT83XX_INTC_ISR21 REG8(IT83XX_INTC_BASE + 0x58)
+#define IT83XX_INTC_ISR22 REG8(IT83XX_INTC_BASE + 0x5c)
+#define IT83XX_INTC_ISR23 REG8(IT83XX_INTC_BASE + 0x90)
+#define IT83XX_INTC_ISR24 REG8(IT83XX_INTC_BASE + 0x94)
+#define IT83XX_INTC_ISR25 REG8(IT83XX_INTC_BASE + 0x98)
+#define IT83XX_INTC_ISR26 REG8(IT83XX_INTC_BASE + 0x9c)
+#define IT83XX_INTC_ISR27 REG8(IT83XX_INTC_BASE + 0xa0)
+#define IT83XX_INTC_ISR28 REG8(IT83XX_INTC_BASE + 0xa4)
+
+#define IT83XX_INTC_IELMR10 REG8(IT83XX_INTC_BASE + 0x2E)
+#define IT83XX_INTC_IPOLR10 REG8(IT83XX_INTC_BASE + 0x2F)
+#define IT83XX_INTC_IELMR19 REG8(IT83XX_INTC_BASE + 0x52)
+#define IT83XX_INTC_IPOLR19 REG8(IT83XX_INTC_BASE + 0x53)
 
 #define IT83XX_INTC_EXT_IER_OFF(n) (0x60 + (n))
-#define IT83XX_INTC_IVCT(i)     REG8(IT83XX_INTC_BASE+0x80+(i))
+#define IT83XX_INTC_IVCT(i) REG8(IT83XX_INTC_BASE + 0x80 + (i))
 
 /* --- EC Access to the Host Controlled Modules (EC2I Bridge) --- */
-#define IT83XX_EC2I_BASE  0x00F01200
+#define IT83XX_EC2I_BASE 0x00F01200
 
-#define IT83XX_EC2I_IHIOA       REG8(IT83XX_EC2I_BASE+0x00)
-#define IT83XX_EC2I_IHD         REG8(IT83XX_EC2I_BASE+0x01)
-#define IT83XX_EC2I_LSIOHA      REG8(IT83XX_EC2I_BASE+0x02)
-#define IT83XX_EC2I_SIOLV       REG8(IT83XX_EC2I_BASE+0x03)
-#define IT83XX_EC2I_IBMAE       REG8(IT83XX_EC2I_BASE+0x04)
-#define IT83XX_EC2I_IBCTL       REG8(IT83XX_EC2I_BASE+0x05)
+#define IT83XX_EC2I_IHIOA REG8(IT83XX_EC2I_BASE + 0x00)
+#define IT83XX_EC2I_IHD REG8(IT83XX_EC2I_BASE + 0x01)
+#define IT83XX_EC2I_LSIOHA REG8(IT83XX_EC2I_BASE + 0x02)
+#define IT83XX_EC2I_SIOLV REG8(IT83XX_EC2I_BASE + 0x03)
+#define IT83XX_EC2I_IBMAE REG8(IT83XX_EC2I_BASE + 0x04)
+#define IT83XX_EC2I_IBCTL REG8(IT83XX_EC2I_BASE + 0x05)
 
 /* --- System Wake-UP Control (SWUC) --- */
-#define IT83XX_SWUC_BASE  0x00F01400
-#define IT83XX_SWUC_SWCTL1      REG8(IT83XX_SWUC_BASE+0x00)
+#define IT83XX_SWUC_BASE 0x00F01400
+#define IT83XX_SWUC_SWCTL1 REG8(IT83XX_SWUC_BASE + 0x00)
 
 /* --- Wake-Up Control (WUC) --- */
-#define IT83XX_WUC_BASE   0x00F01B00
+#define IT83XX_WUC_BASE 0x00F01B00
 
-#define IT83XX_WUC_WUEMR1 (IT83XX_WUC_BASE+0x00)
-#define IT83XX_WUC_WUEMR5 (IT83XX_WUC_BASE+0x0c)
-#define IT83XX_WUC_WUESR1 (IT83XX_WUC_BASE+0x04)
-#define IT83XX_WUC_WUESR5 (IT83XX_WUC_BASE+0x0d)
-#define IT83XX_WUC_WUBEMR1 (IT83XX_WUC_BASE+0x3c)
-#define IT83XX_WUC_WUBEMR5 (IT83XX_WUC_BASE+0x0f)
+#define IT83XX_WUC_WUEMR1 (IT83XX_WUC_BASE + 0x00)
+#define IT83XX_WUC_WUEMR5 (IT83XX_WUC_BASE + 0x0c)
+#define IT83XX_WUC_WUESR1 (IT83XX_WUC_BASE + 0x04)
+#define IT83XX_WUC_WUESR5 (IT83XX_WUC_BASE + 0x0d)
+#define IT83XX_WUC_WUBEMR1 (IT83XX_WUC_BASE + 0x3c)
+#define IT83XX_WUC_WUBEMR5 (IT83XX_WUC_BASE + 0x0f)
 
-#define IT83XX_WUC_WUESR10    REG8(IT83XX_WUC_BASE+0x21)
-#define IT83XX_WUC_WUESR11    REG8(IT83XX_WUC_BASE+0x25)
+#define IT83XX_WUC_WUESR10 REG8(IT83XX_WUC_BASE + 0x21)
+#define IT83XX_WUC_WUESR11 REG8(IT83XX_WUC_BASE + 0x25)
 
-#define IT83XX_WUC_WUEMR3     REG8(IT83XX_WUC_BASE+0x02)
-#define IT83XX_WUC_WUESR3     REG8(IT83XX_WUC_BASE+0x06)
-#define IT83XX_WUC_WUENR3     REG8(IT83XX_WUC_BASE+0x0A)
+#define IT83XX_WUC_WUEMR3 REG8(IT83XX_WUC_BASE + 0x02)
+#define IT83XX_WUC_WUESR3 REG8(IT83XX_WUC_BASE + 0x06)
+#define IT83XX_WUC_WUENR3 REG8(IT83XX_WUC_BASE + 0x0A)
 
-#define IT83XX_WUC_WUEMR4     REG8(IT83XX_WUC_BASE+0x03)
-#define IT83XX_WUC_WUESR4     REG8(IT83XX_WUC_BASE+0x07)
-#define IT83XX_WUC_WUENR4     REG8(IT83XX_WUC_BASE+0x0B)
+#define IT83XX_WUC_WUEMR4 REG8(IT83XX_WUC_BASE + 0x03)
+#define IT83XX_WUC_WUESR4 REG8(IT83XX_WUC_BASE + 0x07)
+#define IT83XX_WUC_WUENR4 REG8(IT83XX_WUC_BASE + 0x0B)
 
 /* --- UART --- */
 #define IT83XX_UART0_BASE 0x00F02700
 #define IT83XX_UART1_BASE 0x00F02800
 
-#define IT83XX_UART_BASE(n)        CONCAT3(IT83XX_UART, n, _BASE)
+#define IT83XX_UART_BASE(n) CONCAT3(IT83XX_UART, n, _BASE)
 #define IT83XX_UART_REG(n, offset) REG8(IT83XX_UART_BASE(n) + (offset))
 
-#define IT83XX_UART_DLL(n)         IT83XX_UART_REG(n, 0x00)
-#define IT83XX_UART_DLM(n)         IT83XX_UART_REG(n, 0x01)
-#define IT83XX_UART_RBR(n)         IT83XX_UART_REG(n, 0x00)
-#define IT83XX_UART_THR(n)         IT83XX_UART_REG(n, 0x00)
-#define IT83XX_UART_IER(n)         IT83XX_UART_REG(n, 0x01)
-#define IT83XX_UART_IIR(n)         IT83XX_UART_REG(n, 0x02)
-#define IT83XX_UART_FCR(n)         IT83XX_UART_REG(n, 0x02)
-#define IT83XX_UART_LCR(n)         IT83XX_UART_REG(n, 0x03)
-#define IT83XX_UART_MCR(n)         IT83XX_UART_REG(n, 0x04)
-#define IT83XX_UART_LSR(n)         IT83XX_UART_REG(n, 0x05)
-#define IT83XX_UART_MSR(n)         IT83XX_UART_REG(n, 0x06)
-#define IT83XX_UART_SCR(n)         IT83XX_UART_REG(n, 0x07)
-#define IT83XX_UART_ECSMPR(n)      IT83XX_UART_REG(n, 0x08)
-#define IT83XX_UART_CSSR(n)        IT83XX_UART_REG(n, 0x09)
+#define IT83XX_UART_DLL(n) IT83XX_UART_REG(n, 0x00)
+#define IT83XX_UART_DLM(n) IT83XX_UART_REG(n, 0x01)
+#define IT83XX_UART_RBR(n) IT83XX_UART_REG(n, 0x00)
+#define IT83XX_UART_THR(n) IT83XX_UART_REG(n, 0x00)
+#define IT83XX_UART_IER(n) IT83XX_UART_REG(n, 0x01)
+#define IT83XX_UART_IIR(n) IT83XX_UART_REG(n, 0x02)
+#define IT83XX_UART_FCR(n) IT83XX_UART_REG(n, 0x02)
+#define IT83XX_UART_LCR(n) IT83XX_UART_REG(n, 0x03)
+#define IT83XX_UART_MCR(n) IT83XX_UART_REG(n, 0x04)
+#define IT83XX_UART_LSR(n) IT83XX_UART_REG(n, 0x05)
+#define IT83XX_UART_MSR(n) IT83XX_UART_REG(n, 0x06)
+#define IT83XX_UART_SCR(n) IT83XX_UART_REG(n, 0x07)
+#define IT83XX_UART_ECSMPR(n) IT83XX_UART_REG(n, 0x08)
+#define IT83XX_UART_CSSR(n) IT83XX_UART_REG(n, 0x09)
 
 /* --- GPIO --- */
 
-#define IT83XX_GPIO_BASE  0x00F01600
+#define IT83XX_GPIO_BASE 0x00F01600
 #define IT83XX_GPIO2_BASE 0x00F03E00
 
-#define IT83XX_GPIO_GCR         REG8(IT83XX_GPIO_BASE+0x00)
-#define IT83XX_GPIO_GCR_LPC_RST_B7      0x1
-#define IT83XX_GPIO_GCR_LPC_RST_D2      0x2
+#define IT83XX_GPIO_GCR REG8(IT83XX_GPIO_BASE + 0x00)
+#define IT83XX_GPIO_GCR_LPC_RST_B7 0x1
+#define IT83XX_GPIO_GCR_LPC_RST_D2 0x2
 #define IT83XX_GPIO_GCR_LPC_RST_DISABLE 0x3
-#define IT83XX_GPIO_GCR_LPC_RST_POS     1
-
-#define IT83XX_GPIO_GPDRA       REG8(IT83XX_GPIO_BASE+0x01)
-#define IT83XX_GPIO_GPDRB       REG8(IT83XX_GPIO_BASE+0x02)
-#define IT83XX_GPIO_GPDRC       REG8(IT83XX_GPIO_BASE+0x03)
-#define IT83XX_GPIO_GPDRE       REG8(IT83XX_GPIO_BASE+0x05)
-#define IT83XX_GPIO_GPDRF       REG8(IT83XX_GPIO_BASE+0x06)
-#define IT83XX_GPIO_GPDRH       REG8(IT83XX_GPIO_BASE+0x08)
-
-#define IT83XX_GPIO_GPCRA0      REG8(IT83XX_GPIO_BASE+0x10)
-#define IT83XX_GPIO_GPCRA1      REG8(IT83XX_GPIO_BASE+0x11)
-#define IT83XX_GPIO_GPCRA2      REG8(IT83XX_GPIO_BASE+0x12)
-#define IT83XX_GPIO_GPCRA3      REG8(IT83XX_GPIO_BASE+0x13)
-#define IT83XX_GPIO_GPCRA4      REG8(IT83XX_GPIO_BASE+0x14)
-#define IT83XX_GPIO_GPCRA5      REG8(IT83XX_GPIO_BASE+0x15)
-#define IT83XX_GPIO_GPCRA6      REG8(IT83XX_GPIO_BASE+0x16)
-#define IT83XX_GPIO_GPCRA7      REG8(IT83XX_GPIO_BASE+0x17)
-
-#define IT83XX_GPIO_GPCRB0      REG8(IT83XX_GPIO_BASE+0x18)
-#define IT83XX_GPIO_GPCRB1      REG8(IT83XX_GPIO_BASE+0x19)
-#define IT83XX_GPIO_GPCRB2      REG8(IT83XX_GPIO_BASE+0x1A)
-#define IT83XX_GPIO_GPCRB3      REG8(IT83XX_GPIO_BASE+0x1B)
-#define IT83XX_GPIO_GPCRB4      REG8(IT83XX_GPIO_BASE+0x1C)
-#define IT83XX_GPIO_GPCRB5      REG8(IT83XX_GPIO_BASE+0x1D)
-#define IT83XX_GPIO_GPCRB6      REG8(IT83XX_GPIO_BASE+0x1E)
-#define IT83XX_GPIO_GPCRB7      REG8(IT83XX_GPIO_BASE+0x1F)
-
-#define IT83XX_GPIO_GPCRC0      REG8(IT83XX_GPIO_BASE+0x20)
-#define IT83XX_GPIO_GPCRC1      REG8(IT83XX_GPIO_BASE+0x21)
-#define IT83XX_GPIO_GPCRC2      REG8(IT83XX_GPIO_BASE+0x22)
-#define IT83XX_GPIO_GPCRC3      REG8(IT83XX_GPIO_BASE+0x23)
-#define IT83XX_GPIO_GPCRC4      REG8(IT83XX_GPIO_BASE+0x24)
-#define IT83XX_GPIO_GPCRC5      REG8(IT83XX_GPIO_BASE+0x25)
-#define IT83XX_GPIO_GPCRC6      REG8(IT83XX_GPIO_BASE+0x26)
-#define IT83XX_GPIO_GPCRC7      REG8(IT83XX_GPIO_BASE+0x27)
-
-#define IT83XX_GPIO_GPCRE0      REG8(IT83XX_GPIO_BASE+0x30)
-#define IT83XX_GPIO_GPCRE1      REG8(IT83XX_GPIO_BASE+0x31)
-#define IT83XX_GPIO_GPCRE2      REG8(IT83XX_GPIO_BASE+0x32)
-#define IT83XX_GPIO_GPCRE3      REG8(IT83XX_GPIO_BASE+0x33)
-#define IT83XX_GPIO_GPCRE4      REG8(IT83XX_GPIO_BASE+0x34)
-#define IT83XX_GPIO_GPCRE5      REG8(IT83XX_GPIO_BASE+0x35)
-#define IT83XX_GPIO_GPCRE6      REG8(IT83XX_GPIO_BASE+0x36)
-#define IT83XX_GPIO_GPCRE7      REG8(IT83XX_GPIO_BASE+0x37)
-
-#define IT83XX_GPIO_GPCRF0      REG8(IT83XX_GPIO_BASE+0x38)
-#define IT83XX_GPIO_GPCRF1      REG8(IT83XX_GPIO_BASE+0x39)
-#define IT83XX_GPIO_GPCRF2      REG8(IT83XX_GPIO_BASE+0x3A)
-#define IT83XX_GPIO_GPCRF3      REG8(IT83XX_GPIO_BASE+0x3B)
-#define IT83XX_GPIO_GPCRF4      REG8(IT83XX_GPIO_BASE+0x3C)
-#define IT83XX_GPIO_GPCRF5      REG8(IT83XX_GPIO_BASE+0x3D)
-#define IT83XX_GPIO_GPCRF6      REG8(IT83XX_GPIO_BASE+0x3E)
-#define IT83XX_GPIO_GPCRF7      REG8(IT83XX_GPIO_BASE+0x3F)
-
-#define IT83XX_GPIO_GPCRH0      REG8(IT83XX_GPIO_BASE+0x48)
-#define IT83XX_GPIO_GPCRH1      REG8(IT83XX_GPIO_BASE+0x49)
-#define IT83XX_GPIO_GPCRH2      REG8(IT83XX_GPIO_BASE+0x4A)
-#define IT83XX_GPIO_GPCRH3      REG8(IT83XX_GPIO_BASE+0x4B)
-#define IT83XX_GPIO_GPCRH4      REG8(IT83XX_GPIO_BASE+0x4C)
-#define IT83XX_GPIO_GPCRH5      REG8(IT83XX_GPIO_BASE+0x4D)
-#define IT83XX_GPIO_GPCRH6      REG8(IT83XX_GPIO_BASE+0x4E)
-#define IT83XX_GPIO_GPCRH7      REG8(IT83XX_GPIO_BASE+0x4F)
-
-#define IT83XX_GPIO_GPCRI0      REG8(IT83XX_GPIO_BASE+0x50)
-#define IT83XX_GPIO_GPCRI1      REG8(IT83XX_GPIO_BASE+0x51)
-#define IT83XX_GPIO_GPCRI2      REG8(IT83XX_GPIO_BASE+0x52)
-#define IT83XX_GPIO_GPCRI3      REG8(IT83XX_GPIO_BASE+0x53)
-#define IT83XX_GPIO_GPCRI4      REG8(IT83XX_GPIO_BASE+0x54)
-#define IT83XX_GPIO_GPCRI5      REG8(IT83XX_GPIO_BASE+0x55)
-#define IT83XX_GPIO_GPCRI6      REG8(IT83XX_GPIO_BASE+0x56)
-#define IT83XX_GPIO_GPCRI7      REG8(IT83XX_GPIO_BASE+0x57)
-
-#define IT83XX_GPIO_GPCRM5      REG8(IT83XX_GPIO_BASE+0xA5)
-
-#define IT83XX_GPIO_GPDMRA      REG8(IT83XX_GPIO_BASE+0x61)
-#define IT83XX_GPIO_GPDMRB      REG8(IT83XX_GPIO_BASE+0x62)
-#define IT83XX_GPIO_GPDMRC      REG8(IT83XX_GPIO_BASE+0x63)
-#define IT83XX_GPIO_GPDMRE      REG8(IT83XX_GPIO_BASE+0x65)
-#define IT83XX_GPIO_GPDMRF      REG8(IT83XX_GPIO_BASE+0x66)
-#define IT83XX_GPIO_GPDMRH      REG8(IT83XX_GPIO_BASE+0x68)
-
-#define IT83XX_GPIO_GPCRL0      REG8(IT83XX_GPIO_BASE+0x98)
-#define IT83XX_GPIO_GPCRL1      REG8(IT83XX_GPIO_BASE+0x99)
-#define IT83XX_GPIO_GPCRL2      REG8(IT83XX_GPIO_BASE+0x9A)
-#define IT83XX_GPIO_GPCRL3      REG8(IT83XX_GPIO_BASE+0x9B)
-#define IT83XX_GPIO_GPCRP0      REG8(IT83XX_GPIO2_BASE+0x18)
-#define IT83XX_GPIO_GPCRP1      REG8(IT83XX_GPIO2_BASE+0x19)
-
-#define IT83XX_GPIO_GRC1        REG8(IT83XX_GPIO_BASE+0xF0)
-#define IT83XX_GPIO_GRC2        REG8(IT83XX_GPIO_BASE+0xF1)
-#define IT83XX_GPIO_GRC3        REG8(IT83XX_GPIO_BASE+0xF2)
-#define IT83XX_GPIO_GRC4        REG8(IT83XX_GPIO_BASE+0xF3)
-#define IT83XX_GPIO_GRC5        REG8(IT83XX_GPIO_BASE+0xF4)
-#define IT83XX_GPIO_GRC6        REG8(IT83XX_GPIO_BASE+0xF5)
-#define IT83XX_GPIO_GRC7        REG8(IT83XX_GPIO_BASE+0xF6)
-#define IT83XX_GPIO_GRC8        REG8(IT83XX_GPIO_BASE+0xF7)
-#define IT83XX_GPIO_GRC19       REG8(IT83XX_GPIO_BASE+0xE4)
-#define IT83XX_GPIO_GRC20       REG8(IT83XX_GPIO_BASE+0xE5)
-#define IT83XX_GPIO_GRC21       REG8(IT83XX_GPIO_BASE+0xE6)
-#define IT83XX_GPIO_GRC22       REG8(IT83XX_GPIO_BASE+0xE7)
-#define IT83XX_GPIO_GRC23       REG8(IT83XX_GPIO_BASE+0xE8)
-#define IT83XX_GPIO_GRC24       REG8(IT83XX_GPIO_BASE+0xE9)
-#define IT83XX_GPIO_GCR25       REG8(IT83XX_GPIO_BASE+0xD1)
-#define IT83XX_GPIO_GCR26       REG8(IT83XX_GPIO_BASE+0xD2)
-#define IT83XX_GPIO_GCR27       REG8(IT83XX_GPIO_BASE+0xD3)
-#define IT83XX_GPIO_GCR28       REG8(IT83XX_GPIO_BASE+0xD4)
-#define IT83XX_GPIO_GCR30       REG8(IT83XX_GPIO_BASE+0xED)
-#define IT83XX_GPIO_GCR31       REG8(IT83XX_GPIO_BASE+0xD5)
-#define IT83XX_GPIO_GCR32       REG8(IT83XX_GPIO_BASE+0xD6)
-#define IT83XX_GPIO_GCR33       REG8(IT83XX_GPIO_BASE+0xD7)
-
-#define IT83XX_VBATPC_BGPOPSCR  REG8(IT83XX_GPIO2_BASE+0xF0)
-#define IT83XX_VBATPC_XLPIER    REG8(IT83XX_GPIO2_BASE+0xF5)
+#define IT83XX_GPIO_GCR_LPC_RST_POS 1
+
+#define IT83XX_GPIO_GPDRA REG8(IT83XX_GPIO_BASE + 0x01)
+#define IT83XX_GPIO_GPDRB REG8(IT83XX_GPIO_BASE + 0x02)
+#define IT83XX_GPIO_GPDRC REG8(IT83XX_GPIO_BASE + 0x03)
+#define IT83XX_GPIO_GPDRE REG8(IT83XX_GPIO_BASE + 0x05)
+#define IT83XX_GPIO_GPDRF REG8(IT83XX_GPIO_BASE + 0x06)
+#define IT83XX_GPIO_GPDRH REG8(IT83XX_GPIO_BASE + 0x08)
+
+#define IT83XX_GPIO_GPCRA0 REG8(IT83XX_GPIO_BASE + 0x10)
+#define IT83XX_GPIO_GPCRA1 REG8(IT83XX_GPIO_BASE + 0x11)
+#define IT83XX_GPIO_GPCRA2 REG8(IT83XX_GPIO_BASE + 0x12)
+#define IT83XX_GPIO_GPCRA3 REG8(IT83XX_GPIO_BASE + 0x13)
+#define IT83XX_GPIO_GPCRA4 REG8(IT83XX_GPIO_BASE + 0x14)
+#define IT83XX_GPIO_GPCRA5 REG8(IT83XX_GPIO_BASE + 0x15)
+#define IT83XX_GPIO_GPCRA6 REG8(IT83XX_GPIO_BASE + 0x16)
+#define IT83XX_GPIO_GPCRA7 REG8(IT83XX_GPIO_BASE + 0x17)
+
+#define IT83XX_GPIO_GPCRB0 REG8(IT83XX_GPIO_BASE + 0x18)
+#define IT83XX_GPIO_GPCRB1 REG8(IT83XX_GPIO_BASE + 0x19)
+#define IT83XX_GPIO_GPCRB2 REG8(IT83XX_GPIO_BASE + 0x1A)
+#define IT83XX_GPIO_GPCRB3 REG8(IT83XX_GPIO_BASE + 0x1B)
+#define IT83XX_GPIO_GPCRB4 REG8(IT83XX_GPIO_BASE + 0x1C)
+#define IT83XX_GPIO_GPCRB5 REG8(IT83XX_GPIO_BASE + 0x1D)
+#define IT83XX_GPIO_GPCRB6 REG8(IT83XX_GPIO_BASE + 0x1E)
+#define IT83XX_GPIO_GPCRB7 REG8(IT83XX_GPIO_BASE + 0x1F)
+
+#define IT83XX_GPIO_GPCRC0 REG8(IT83XX_GPIO_BASE + 0x20)
+#define IT83XX_GPIO_GPCRC1 REG8(IT83XX_GPIO_BASE + 0x21)
+#define IT83XX_GPIO_GPCRC2 REG8(IT83XX_GPIO_BASE + 0x22)
+#define IT83XX_GPIO_GPCRC3 REG8(IT83XX_GPIO_BASE + 0x23)
+#define IT83XX_GPIO_GPCRC4 REG8(IT83XX_GPIO_BASE + 0x24)
+#define IT83XX_GPIO_GPCRC5 REG8(IT83XX_GPIO_BASE + 0x25)
+#define IT83XX_GPIO_GPCRC6 REG8(IT83XX_GPIO_BASE + 0x26)
+#define IT83XX_GPIO_GPCRC7 REG8(IT83XX_GPIO_BASE + 0x27)
+
+#define IT83XX_GPIO_GPCRE0 REG8(IT83XX_GPIO_BASE + 0x30)
+#define IT83XX_GPIO_GPCRE1 REG8(IT83XX_GPIO_BASE + 0x31)
+#define IT83XX_GPIO_GPCRE2 REG8(IT83XX_GPIO_BASE + 0x32)
+#define IT83XX_GPIO_GPCRE3 REG8(IT83XX_GPIO_BASE + 0x33)
+#define IT83XX_GPIO_GPCRE4 REG8(IT83XX_GPIO_BASE + 0x34)
+#define IT83XX_GPIO_GPCRE5 REG8(IT83XX_GPIO_BASE + 0x35)
+#define IT83XX_GPIO_GPCRE6 REG8(IT83XX_GPIO_BASE + 0x36)
+#define IT83XX_GPIO_GPCRE7 REG8(IT83XX_GPIO_BASE + 0x37)
+
+#define IT83XX_GPIO_GPCRF0 REG8(IT83XX_GPIO_BASE + 0x38)
+#define IT83XX_GPIO_GPCRF1 REG8(IT83XX_GPIO_BASE + 0x39)
+#define IT83XX_GPIO_GPCRF2 REG8(IT83XX_GPIO_BASE + 0x3A)
+#define IT83XX_GPIO_GPCRF3 REG8(IT83XX_GPIO_BASE + 0x3B)
+#define IT83XX_GPIO_GPCRF4 REG8(IT83XX_GPIO_BASE + 0x3C)
+#define IT83XX_GPIO_GPCRF5 REG8(IT83XX_GPIO_BASE + 0x3D)
+#define IT83XX_GPIO_GPCRF6 REG8(IT83XX_GPIO_BASE + 0x3E)
+#define IT83XX_GPIO_GPCRF7 REG8(IT83XX_GPIO_BASE + 0x3F)
+
+#define IT83XX_GPIO_GPCRH0 REG8(IT83XX_GPIO_BASE + 0x48)
+#define IT83XX_GPIO_GPCRH1 REG8(IT83XX_GPIO_BASE + 0x49)
+#define IT83XX_GPIO_GPCRH2 REG8(IT83XX_GPIO_BASE + 0x4A)
+#define IT83XX_GPIO_GPCRH3 REG8(IT83XX_GPIO_BASE + 0x4B)
+#define IT83XX_GPIO_GPCRH4 REG8(IT83XX_GPIO_BASE + 0x4C)
+#define IT83XX_GPIO_GPCRH5 REG8(IT83XX_GPIO_BASE + 0x4D)
+#define IT83XX_GPIO_GPCRH6 REG8(IT83XX_GPIO_BASE + 0x4E)
+#define IT83XX_GPIO_GPCRH7 REG8(IT83XX_GPIO_BASE + 0x4F)
+
+#define IT83XX_GPIO_GPCRI0 REG8(IT83XX_GPIO_BASE + 0x50)
+#define IT83XX_GPIO_GPCRI1 REG8(IT83XX_GPIO_BASE + 0x51)
+#define IT83XX_GPIO_GPCRI2 REG8(IT83XX_GPIO_BASE + 0x52)
+#define IT83XX_GPIO_GPCRI3 REG8(IT83XX_GPIO_BASE + 0x53)
+#define IT83XX_GPIO_GPCRI4 REG8(IT83XX_GPIO_BASE + 0x54)
+#define IT83XX_GPIO_GPCRI5 REG8(IT83XX_GPIO_BASE + 0x55)
+#define IT83XX_GPIO_GPCRI6 REG8(IT83XX_GPIO_BASE + 0x56)
+#define IT83XX_GPIO_GPCRI7 REG8(IT83XX_GPIO_BASE + 0x57)
+
+#define IT83XX_GPIO_GPCRM5 REG8(IT83XX_GPIO_BASE + 0xA5)
+
+#define IT83XX_GPIO_GPDMRA REG8(IT83XX_GPIO_BASE + 0x61)
+#define IT83XX_GPIO_GPDMRB REG8(IT83XX_GPIO_BASE + 0x62)
+#define IT83XX_GPIO_GPDMRC REG8(IT83XX_GPIO_BASE + 0x63)
+#define IT83XX_GPIO_GPDMRE REG8(IT83XX_GPIO_BASE + 0x65)
+#define IT83XX_GPIO_GPDMRF REG8(IT83XX_GPIO_BASE + 0x66)
+#define IT83XX_GPIO_GPDMRH REG8(IT83XX_GPIO_BASE + 0x68)
+
+#define IT83XX_GPIO_GPCRL0 REG8(IT83XX_GPIO_BASE + 0x98)
+#define IT83XX_GPIO_GPCRL1 REG8(IT83XX_GPIO_BASE + 0x99)
+#define IT83XX_GPIO_GPCRL2 REG8(IT83XX_GPIO_BASE + 0x9A)
+#define IT83XX_GPIO_GPCRL3 REG8(IT83XX_GPIO_BASE + 0x9B)
+#define IT83XX_GPIO_GPCRP0 REG8(IT83XX_GPIO2_BASE + 0x18)
+#define IT83XX_GPIO_GPCRP1 REG8(IT83XX_GPIO2_BASE + 0x19)
+
+#define IT83XX_GPIO_GRC1 REG8(IT83XX_GPIO_BASE + 0xF0)
+#define IT83XX_GPIO_GRC2 REG8(IT83XX_GPIO_BASE + 0xF1)
+#define IT83XX_GPIO_GRC3 REG8(IT83XX_GPIO_BASE + 0xF2)
+#define IT83XX_GPIO_GRC4 REG8(IT83XX_GPIO_BASE + 0xF3)
+#define IT83XX_GPIO_GRC5 REG8(IT83XX_GPIO_BASE + 0xF4)
+#define IT83XX_GPIO_GRC6 REG8(IT83XX_GPIO_BASE + 0xF5)
+#define IT83XX_GPIO_GRC7 REG8(IT83XX_GPIO_BASE + 0xF6)
+#define IT83XX_GPIO_GRC8 REG8(IT83XX_GPIO_BASE + 0xF7)
+#define IT83XX_GPIO_GRC19 REG8(IT83XX_GPIO_BASE + 0xE4)
+#define IT83XX_GPIO_GRC20 REG8(IT83XX_GPIO_BASE + 0xE5)
+#define IT83XX_GPIO_GRC21 REG8(IT83XX_GPIO_BASE + 0xE6)
+#define IT83XX_GPIO_GRC22 REG8(IT83XX_GPIO_BASE + 0xE7)
+#define IT83XX_GPIO_GRC23 REG8(IT83XX_GPIO_BASE + 0xE8)
+#define IT83XX_GPIO_GRC24 REG8(IT83XX_GPIO_BASE + 0xE9)
+#define IT83XX_GPIO_GCR25 REG8(IT83XX_GPIO_BASE + 0xD1)
+#define IT83XX_GPIO_GCR26 REG8(IT83XX_GPIO_BASE + 0xD2)
+#define IT83XX_GPIO_GCR27 REG8(IT83XX_GPIO_BASE + 0xD3)
+#define IT83XX_GPIO_GCR28 REG8(IT83XX_GPIO_BASE + 0xD4)
+#define IT83XX_GPIO_GCR29 REG8(IT83XX_GPIO_BASE + 0xEE)
+#define IT83XX_GPIO_GCR30 REG8(IT83XX_GPIO_BASE + 0xED)
+#define IT83XX_GPIO_GCR31 REG8(IT83XX_GPIO_BASE + 0xD5)
+#define IT83XX_GPIO_GCR32 REG8(IT83XX_GPIO_BASE + 0xD6)
+#define IT83XX_GPIO_GCR33 REG8(IT83XX_GPIO_BASE + 0xD7)
+
+#define IT83XX_VBATPC_BGPOPSCR REG8(IT83XX_GPIO2_BASE + 0xF0)
+#define IT83XX_VBATPC_XLPIER REG8(IT83XX_GPIO2_BASE + 0xF5)
 
 enum {
 	/* GPIO group index */
@@ -804,7 +805,16 @@ enum {
 #endif
 	GPIO_PORT_COUNT,
 
-	/* NOTE: Support GPIO input only if KSO/KSI pins are used as GPIO. */
+	/*
+	 * NOTE: support flags when KSI/KSO are configured as GPIO
+	 * 1) it8320bx:
+	 * output: GPIO_OUTPUT, GPIO_OPEN_DRAIN, GPIO_HIGH, GPIO_LOW
+	 * input: GPIO_INPUT
+	 * 2) it8320dx, it8xxx1, and it8xxx2:
+	 * output: GPIO_OUTPUT, GPIO_OPEN_DRAIN(always internal pullup),
+	 *         GPIO_HIGH, GPIO_LOW
+	 * input: GPIO_INPUT, GPIO_PULL_UP
+	 */
 	/* KSI[7-0]  GPIO data mirror register. */
 	GPIO_KSI,
 	/* KSO[15-8] GPIO data mirror register. */
@@ -816,11 +826,11 @@ enum {
 };
 
 struct gpio_reg_t {
-	/* GPIO port data register (bit mapping to pin) */
+	/* GPIO and KSI/KSO port data register (bit mapping to pin) */
 	uint32_t reg_gpdr;
-	/* GPIO port data mirror register (bit mapping to pin) */
+	/* GPIO and KSI/KSO port data mirror register (bit mapping to pin) */
 	uint32_t reg_gpdmr;
-	/* GPIO port output type register (bit mapping to pin) */
+	/* GPIO and KSI/KSO port output type register (bit mapping to pin) */
 	uint32_t reg_gpotr;
 	/* GPIO port control register (byte mapping to pin) */
 	uint32_t reg_gpcr;
@@ -829,70 +839,67 @@ struct gpio_reg_t {
 /* GPIO group index convert to GPIO data/output type/ctrl group address */
 static const struct gpio_reg_t gpio_group_to_reg[] = {
 	/*               GPDR(set),  GPDMR(get), GPOTR,      GPCR      */
-	[GPIO_A]     = { 0x00F01601, 0x00F01661, 0x00F01671, 0x00F01610 },
-	[GPIO_B]     = { 0x00F01602, 0x00F01662, 0x00F01672, 0x00F01618 },
-	[GPIO_C]     = { 0x00F01603, 0x00F01663, 0x00F01673, 0x00F01620 },
-	[GPIO_D]     = { 0x00F01604, 0x00F01664, 0x00F01674, 0x00F01628 },
-	[GPIO_E]     = { 0x00F01605, 0x00F01665, 0x00F01675, 0x00F01630 },
-	[GPIO_F]     = { 0x00F01606, 0x00F01666, 0x00F01676, 0x00F01638 },
-	[GPIO_G]     = { 0x00F01607, 0x00F01667, 0x00F01677, 0x00F01640 },
-	[GPIO_H]     = { 0x00F01608, 0x00F01668, 0x00F01678, 0x00F01648 },
-	[GPIO_I]     = { 0x00F01609, 0x00F01669, 0x00F01679, 0x00F01650 },
-	[GPIO_J]     = { 0x00F0160A, 0x00F0166A, 0x00F0167A, 0x00F01658 },
-	[GPIO_K]     = { 0x00F0160B, 0x00F0166B, 0x00F0167B, 0x00F01690 },
-	[GPIO_L]     = { 0x00F0160C, 0x00F0166C, 0x00F0167C, 0x00F01698 },
-	[GPIO_M]     = { 0x00F0160D, 0x00F0166D, 0x00F0167D, 0x00F016a0 },
+	[GPIO_A] = { 0x00F01601, 0x00F01661, 0x00F01671, 0x00F01610 },
+	[GPIO_B] = { 0x00F01602, 0x00F01662, 0x00F01672, 0x00F01618 },
+	[GPIO_C] = { 0x00F01603, 0x00F01663, 0x00F01673, 0x00F01620 },
+	[GPIO_D] = { 0x00F01604, 0x00F01664, 0x00F01674, 0x00F01628 },
+	[GPIO_E] = { 0x00F01605, 0x00F01665, 0x00F01675, 0x00F01630 },
+	[GPIO_F] = { 0x00F01606, 0x00F01666, 0x00F01676, 0x00F01638 },
+	[GPIO_G] = { 0x00F01607, 0x00F01667, 0x00F01677, 0x00F01640 },
+	[GPIO_H] = { 0x00F01608, 0x00F01668, 0x00F01678, 0x00F01648 },
+	[GPIO_I] = { 0x00F01609, 0x00F01669, 0x00F01679, 0x00F01650 },
+	[GPIO_J] = { 0x00F0160A, 0x00F0166A, 0x00F0167A, 0x00F01658 },
+	[GPIO_K] = { 0x00F0160B, 0x00F0166B, 0x00F0167B, 0x00F01690 },
+	[GPIO_L] = { 0x00F0160C, 0x00F0166C, 0x00F0167C, 0x00F01698 },
+	[GPIO_M] = { 0x00F0160D, 0x00F0166D, 0x00F0167D, 0x00F016a0 },
 #if defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2)
-	[GPIO_O]     = { 0x00F03E01, 0x00F03E61, 0x00F03E71, 0x00F03E10 },
-	[GPIO_P]     = { 0x00F03E02, 0x00F03E62, 0x00F03E72, 0x00F03E18 },
-	[GPIO_Q]     = { 0x00F03E03, 0x00F03E63, 0x00F03E73, 0x00F03E20 },
-	[GPIO_R]     = { 0x00F03E04, 0x00F03E64, 0x00F03E74, 0x00F03E28 },
+	[GPIO_O] = { 0x00F03E01, 0x00F03E61, 0x00F03E71, 0x00F03E10 },
+	[GPIO_P] = { 0x00F03E02, 0x00F03E62, 0x00F03E72, 0x00F03E18 },
+	[GPIO_Q] = { 0x00F03E03, 0x00F03E63, 0x00F03E73, 0x00F03E20 },
+	[GPIO_R] = { 0x00F03E04, 0x00F03E64, 0x00F03E74, 0x00F03E28 },
 #endif
-	[GPIO_KSI]   = { 0x00F01D09, 0x00F01D09,         -1,         -1 },
-	[GPIO_KSO_H] = { 0x00F01D0C, 0x00F01D0C,         -1,         -1 },
-	[GPIO_KSO_L] = { 0x00F01D0F, 0x00F01D0F,         -1,         -1 },
+	[GPIO_KSI] = { 0x00F01D08, 0x00F01D09, 0x00F01D26, 0xFFFFFFFF },
+	[GPIO_KSO_H] = { 0x00F01D01, 0x00F01D0C, 0x00F01D27, 0xFFFFFFFF },
+	[GPIO_KSO_L] = { 0x00F01D00, 0x00F01D0F, 0x00F01D28, 0xFFFFFFFF },
 };
 BUILD_ASSERT(ARRAY_SIZE(gpio_group_to_reg) == (COUNT));
 
 #define UNIMPLEMENTED_GPIO_BANK GPIO_A
 
-#define IT83XX_GPIO_DATA(port)                 \
-	REG8(gpio_group_to_reg[port].reg_gpdr)
-#define IT83XX_GPIO_DATA_MIRROR(port)          \
-	REG8(gpio_group_to_reg[port].reg_gpdmr)
-#define IT83XX_GPIO_GPOT(port)                 \
-	REG8(gpio_group_to_reg[port].reg_gpotr)
-#define IT83XX_GPIO_CTRL(port, pin_offset)     \
+#define IT83XX_GPIO_DATA(port) REG8(gpio_group_to_reg[port].reg_gpdr)
+#define IT83XX_GPIO_DATA_MIRROR(port) REG8(gpio_group_to_reg[port].reg_gpdmr)
+#define IT83XX_GPIO_GPOT(port) REG8(gpio_group_to_reg[port].reg_gpotr)
+#define IT83XX_GPIO_CTRL(port, pin_offset) \
 	REG8(gpio_group_to_reg[port].reg_gpcr + pin_offset)
-#define GPCR_PORT_PIN_MODE_INPUT          BIT(7)
-#define GPCR_PORT_PIN_MODE_OUTPUT         BIT(6)
-#define GPCR_PORT_PIN_MODE_PULLUP         BIT(2)
-#define GPCR_PORT_PIN_MODE_PULLDOWN       BIT(1)
+#define GPCR_PORT_PIN_MODE_INPUT BIT(7)
+#define GPCR_PORT_PIN_MODE_OUTPUT BIT(6)
+#define GPCR_PORT_PIN_MODE_PULLUP BIT(2)
+#define GPCR_PORT_PIN_MODE_PULLDOWN BIT(1)
 
 /* --- Clock and Power Management (ECPM) --- */
 
-#define IT83XX_ECPM_BASE  0x00F01E00
+#define IT83XX_ECPM_BASE 0x00F01E00
 
 #define IT83XX_ECPM_CGCTRL1R_OFF 0x01
 #define IT83XX_ECPM_CGCTRL2R_OFF 0x02
 #define IT83XX_ECPM_CGCTRL3R_OFF 0x05
 #define IT83XX_ECPM_CGCTRL4R_OFF 0x09
 
-#define IT83XX_ECPM_PLLCTRL	REG8(IT83XX_ECPM_BASE+0x03)
+#define IT83XX_ECPM_PLLCTRL REG8(IT83XX_ECPM_BASE + 0x03)
 enum ec_pll_ctrl {
 	EC_PLL_DOZE = 0,
 	EC_PLL_SLEEP = 1,
 	EC_PLL_DEEP_DOZE = 3,
 };
 
-#define IT83XX_ECPM_AUTOCG	REG8(IT83XX_ECPM_BASE+0x04)
-#define IT83XX_ECPM_PLLFREQR	REG8(IT83XX_ECPM_BASE+0x06)
-#define IT83XX_ECPM_PLLCSS	REG8(IT83XX_ECPM_BASE+0x08)
-#define IT83XX_ECPM_SCDCR0	REG8(IT83XX_ECPM_BASE+0x0c)
-#define IT83XX_ECPM_SCDCR1	REG8(IT83XX_ECPM_BASE+0x0d)
-#define IT83XX_ECPM_SCDCR2	REG8(IT83XX_ECPM_BASE+0x0e)
-#define IT83XX_ECPM_SCDCR3	REG8(IT83XX_ECPM_BASE+0x0f)
-#define IT83XX_ECPM_SCDCR4	REG8(IT83XX_ECPM_BASE+0x10)
+#define IT83XX_ECPM_AUTOCG REG8(IT83XX_ECPM_BASE + 0x04)
+#define IT83XX_ECPM_PLLFREQR REG8(IT83XX_ECPM_BASE + 0x06)
+#define IT83XX_ECPM_PLLCSS REG8(IT83XX_ECPM_BASE + 0x08)
+#define IT83XX_ECPM_SCDCR0 REG8(IT83XX_ECPM_BASE + 0x0c)
+#define IT83XX_ECPM_SCDCR1 REG8(IT83XX_ECPM_BASE + 0x0d)
+#define IT83XX_ECPM_SCDCR2 REG8(IT83XX_ECPM_BASE + 0x0e)
+#define IT83XX_ECPM_SCDCR3 REG8(IT83XX_ECPM_BASE + 0x0f)
+#define IT83XX_ECPM_SCDCR4 REG8(IT83XX_ECPM_BASE + 0x10)
 
 /*
  * The clock gate offsets combine the register offset from ECPM_BASE and the
@@ -900,514 +907,528 @@ enum ec_pll_ctrl {
  * clock_enable_peripheral() and clock_disable_peripheral()
  */
 enum clock_gate_offsets {
-	CGC_OFFSET_EGPC  = ((IT83XX_ECPM_CGCTRL2R_OFF << 8) | 0x40),
-	CGC_OFFSET_CIR   = ((IT83XX_ECPM_CGCTRL2R_OFF << 8) | 0x20),
-	CGC_OFFSET_SWUC  = ((IT83XX_ECPM_CGCTRL2R_OFF << 8) | 0x10),
-	CGC_OFFSET_USB   = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x20),
-	CGC_OFFSET_PECI  = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x08),
-	CGC_OFFSET_UART  = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x04),
-	CGC_OFFSET_SSPI  = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x02),
-	CGC_OFFSET_DBGR  = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x01),
-	CGC_OFFSET_SMBF  = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x80),
-	CGC_OFFSET_SMBE  = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x40),
-	CGC_OFFSET_SMBD  = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x20),
-	CGC_OFFSET_SMBC  = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x10),
-	CGC_OFFSET_SMBB  = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x08),
-	CGC_OFFSET_SMBA  = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x04),
-	CGC_OFFSET_SMB   = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x02),
-	CGC_OFFSET_CEC   = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x01)
+	CGC_OFFSET_EGPC = ((IT83XX_ECPM_CGCTRL2R_OFF << 8) | 0x40),
+	CGC_OFFSET_CIR = ((IT83XX_ECPM_CGCTRL2R_OFF << 8) | 0x20),
+	CGC_OFFSET_SWUC = ((IT83XX_ECPM_CGCTRL2R_OFF << 8) | 0x10),
+	CGC_OFFSET_USB = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x20),
+	CGC_OFFSET_PECI = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x08),
+	CGC_OFFSET_UART = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x04),
+	CGC_OFFSET_SSPI = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x02),
+	CGC_OFFSET_DBGR = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x01),
+	CGC_OFFSET_SMBF = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x80),
+	CGC_OFFSET_SMBE = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x40),
+	CGC_OFFSET_SMBD = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x20),
+	CGC_OFFSET_SMBC = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x10),
+	CGC_OFFSET_SMBB = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x08),
+	CGC_OFFSET_SMBA = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x04),
+	CGC_OFFSET_SMB = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x02),
+	CGC_OFFSET_CEC = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x01)
 };
 
 /* --- Timer (TMR) --- */
-#define IT83XX_TMR_BASE         0x00F02900
-
-#define IT83XX_TMR_PRSC         REG8(IT83XX_TMR_BASE+0x00)
-#define IT83XX_TMR_GCSMS        REG8(IT83XX_TMR_BASE+0x01)
-#define IT83XX_TMR_CTR_A0       REG8(IT83XX_TMR_BASE+0x02)
-#define IT83XX_TMR_CTR_A1       REG8(IT83XX_TMR_BASE+0x03)
-#define IT83XX_TMR_CTR_B0       REG8(IT83XX_TMR_BASE+0x04)
-#define IT83XX_TMR_CTR_B1       REG8(IT83XX_TMR_BASE+0x05)
-#define IT83XX_TMR_DCR_A0       REG8(IT83XX_TMR_BASE+0x06)
-#define IT83XX_TMR_DCR_A1       REG8(IT83XX_TMR_BASE+0x07)
-#define IT83XX_TMR_DCR_B0       REG8(IT83XX_TMR_BASE+0x08)
-#define IT83XX_TMR_DCR_B1       REG8(IT83XX_TMR_BASE+0x09)
-#define IT83XX_TMR_CCGSR        REG8(IT83XX_TMR_BASE+0x0A)
-#define IT83XX_TMR_TMRCE        REG8(IT83XX_TMR_BASE+0x0B)
-#define IT83XX_TMR_TMRIE        REG8(IT83XX_TMR_BASE+0x0C)
+#define IT83XX_TMR_BASE 0x00F02900
+
+#define IT83XX_TMR_PRSC REG8(IT83XX_TMR_BASE + 0x00)
+#define IT83XX_TMR_GCSMS REG8(IT83XX_TMR_BASE + 0x01)
+#define IT83XX_TMR_CTR_A0 REG8(IT83XX_TMR_BASE + 0x02)
+#define IT83XX_TMR_CTR_A1 REG8(IT83XX_TMR_BASE + 0x03)
+#define IT83XX_TMR_CTR_B0 REG8(IT83XX_TMR_BASE + 0x04)
+#define IT83XX_TMR_CTR_B1 REG8(IT83XX_TMR_BASE + 0x05)
+#define IT83XX_TMR_DCR_A0 REG8(IT83XX_TMR_BASE + 0x06)
+#define IT83XX_TMR_DCR_A1 REG8(IT83XX_TMR_BASE + 0x07)
+#define IT83XX_TMR_DCR_B0 REG8(IT83XX_TMR_BASE + 0x08)
+#define IT83XX_TMR_DCR_B1 REG8(IT83XX_TMR_BASE + 0x09)
+#define IT83XX_TMR_CCGSR REG8(IT83XX_TMR_BASE + 0x0A)
+#define IT83XX_TMR_TMRCE REG8(IT83XX_TMR_BASE + 0x0B)
+#define IT83XX_TMR_TMRIE REG8(IT83XX_TMR_BASE + 0x0C)
 
 /* --- External Timer and Watchdog (ETWD) --- */
-#define IT83XX_ETWD_BASE  0x00F01F00
-
-#define IT83XX_ETWD_ETWCFG        REG8(IT83XX_ETWD_BASE+0x01)
-#define IT83XX_ETWD_ET1PSR        REG8(IT83XX_ETWD_BASE+0x02)
-#define IT83XX_ETWD_ET1CNTLHR     REG8(IT83XX_ETWD_BASE+0x03)
-#define IT83XX_ETWD_ET1CNTLLR     REG8(IT83XX_ETWD_BASE+0x04)
-#define IT83XX_ETWD_ETWCTRL       REG8(IT83XX_ETWD_BASE+0x05)
-#define IT83XX_ETWD_EWDCNTLLR     REG8(IT83XX_ETWD_BASE+0x06)
-#define IT83XX_ETWD_EWDKEYR       REG8(IT83XX_ETWD_BASE+0x07)
-#define IT83XX_ETWD_EWDCNTLHR     REG8(IT83XX_ETWD_BASE+0x09)
-#define IT83XX_ETWD_ETXCTRL(n)    REG8(IT83XX_ETWD_BASE + 0x10 + (n << 3))
-#define IT83XX_ETWD_ETXPSR(n)     REG8(IT83XX_ETWD_BASE + 0x11 + (n << 3))
-#define IT83XX_ETWD_ETXCNTLR(n)   REG32(IT83XX_ETWD_BASE + 0x14 + (n << 3))
-#define IT83XX_ETWD_ETXCNTOR(n)   REG32(IT83XX_ETWD_BASE + 0x48 + (n << 2))
+#define IT83XX_ETWD_BASE 0x00F01F00
+
+#define IT83XX_ETWD_ETWCFG REG8(IT83XX_ETWD_BASE + 0x01)
+#define IT83XX_ETWD_ET1PSR REG8(IT83XX_ETWD_BASE + 0x02)
+#define IT83XX_ETWD_ET1CNTLHR REG8(IT83XX_ETWD_BASE + 0x03)
+#define IT83XX_ETWD_ET1CNTLLR REG8(IT83XX_ETWD_BASE + 0x04)
+#define IT83XX_ETWD_ETWCTRL REG8(IT83XX_ETWD_BASE + 0x05)
+#define IT83XX_ETWD_EWDCNTLLR REG8(IT83XX_ETWD_BASE + 0x06)
+#define IT83XX_ETWD_EWDKEYR REG8(IT83XX_ETWD_BASE + 0x07)
+#define IT83XX_ETWD_EWDCNTLHR REG8(IT83XX_ETWD_BASE + 0x09)
+#define IT83XX_ETWD_ETXCTRL(n) REG8(IT83XX_ETWD_BASE + 0x10 + (n << 3))
+#define IT83XX_ETWD_ETXPSR(n) REG8(IT83XX_ETWD_BASE + 0x11 + (n << 3))
+#define IT83XX_ETWD_ETXCNTLR(n) REG32(IT83XX_ETWD_BASE + 0x14 + (n << 3))
+#define IT83XX_ETWD_ETXCNTOR(n) REG32(IT83XX_ETWD_BASE + 0x48 + (n << 2))
 
 /* --- General Control (GCTRL) --- */
 #define IT83XX_GCTRL_BASE 0x00F02000
 
 #ifdef IT83XX_CHIP_ID_3BYTES
-#define IT83XX_GCTRL_CHIPID1      REG8(IT83XX_GCTRL_BASE+0x85)
-#define IT83XX_GCTRL_CHIPID2      REG8(IT83XX_GCTRL_BASE+0x86)
-#define IT83XX_GCTRL_CHIPID3      REG8(IT83XX_GCTRL_BASE+0x87)
+#define IT83XX_GCTRL_CHIPID1 REG8(IT83XX_GCTRL_BASE + 0x85)
+#define IT83XX_GCTRL_CHIPID2 REG8(IT83XX_GCTRL_BASE + 0x86)
+#define IT83XX_GCTRL_CHIPID3 REG8(IT83XX_GCTRL_BASE + 0x87)
 #else
-#define IT83XX_GCTRL_CHIPID1      REG8(IT83XX_GCTRL_BASE+0x00)
-#define IT83XX_GCTRL_CHIPID2      REG8(IT83XX_GCTRL_BASE+0x01)
+#define IT83XX_GCTRL_CHIPID1 REG8(IT83XX_GCTRL_BASE + 0x00)
+#define IT83XX_GCTRL_CHIPID2 REG8(IT83XX_GCTRL_BASE + 0x01)
 #endif
-#define IT83XX_GCTRL_CHIPVER      REG8(IT83XX_GCTRL_BASE+0x02)
-#define IT83XX_GCTRL_DBGROS       REG8(IT83XX_GCTRL_BASE+0x03)
-#define IT83XX_SMB_DBGR           BIT(0)
-#define IT83XX_GCTRL_WNCKR        REG8(IT83XX_GCTRL_BASE+0x0B)
-#define IT83XX_GCTRL_RSTS         REG8(IT83XX_GCTRL_BASE+0x06)
-#define IT83XX_GCTRL_BADRSEL      REG8(IT83XX_GCTRL_BASE+0x0A)
-#define IT83XX_GCTRL_SPCTRL1      REG8(IT83XX_GCTRL_BASE+0x0D)
-#define IT83XX_GCTRL_RSTDMMC      REG8(IT83XX_GCTRL_BASE+0x10)
-#define IT83XX_GCTRL_RSTC4        REG8(IT83XX_GCTRL_BASE+0x11)
-#define IT83XX_GCTRL_SPCTRL4      REG8(IT83XX_GCTRL_BASE+0x1C)
-#define IT83XX_GCTRL_MCCR3        REG8(IT83XX_GCTRL_BASE+0x20)
-#define IT83XX_GCTRL_SPISLVPFE    BIT(6)
-#define IT83XX_GCTRL_RSTC5        REG8(IT83XX_GCTRL_BASE+0x21)
-#define IT83XX_GCTRL_MCCR         REG8(IT83XX_GCTRL_BASE+0x30)
-#define IT83XX_GCTRL_PMER1        REG8(IT83XX_GCTRL_BASE+0x32)
-#define IT83XX_GCTRL_PMER2        REG8(IT83XX_GCTRL_BASE+0x33)
-#define IT83XX_GCTRL_EPLR         REG8(IT83XX_GCTRL_BASE+0x37)
-#define IT83XX_GCTRL_IVTBAR       REG8(IT83XX_GCTRL_BASE+0x41)
-#define IT83XX_GCTRL_MCCR2        REG8(IT83XX_GCTRL_BASE+0x44)
-#define IT83XX_DLM14_ENABLE       BIT(5)
-#define IT83XX_GCTRL_SSCR         REG8(IT83XX_GCTRL_BASE+0x4A)
-#define IT83XX_GCTRL_ETWDUARTCR   REG8(IT83XX_GCTRL_BASE+0x4B)
-#define IT83XX_GCTRL_WMCR         REG8(IT83XX_GCTRL_BASE+0x4C)
-#define IT83XX_GCTRL_H2ROFSR      REG8(IT83XX_GCTRL_BASE+0x53)
+#define IT83XX_GCTRL_CHIPVER REG8(IT83XX_GCTRL_BASE + 0x02)
+#define IT83XX_GCTRL_DBGROS REG8(IT83XX_GCTRL_BASE + 0x03)
+#define IT83XX_SMB_DBGR BIT(0)
+#define IT83XX_GCTRL_WNCKR REG8(IT83XX_GCTRL_BASE + 0x0B)
+#define IT83XX_GCTRL_RSTS REG8(IT83XX_GCTRL_BASE + 0x06)
+#define IT83XX_GCTRL_BADRSEL REG8(IT83XX_GCTRL_BASE + 0x0A)
+#define IT83XX_GCTRL_SPCTRL1 REG8(IT83XX_GCTRL_BASE + 0x0D)
+#define IT83XX_GCTRL_RSTDMMC REG8(IT83XX_GCTRL_BASE + 0x10)
+#define IT83XX_GCTRL_RSTC4 REG8(IT83XX_GCTRL_BASE + 0x11)
+#define IT83XX_GCTRL_SPCTRL4 REG8(IT83XX_GCTRL_BASE + 0x1C)
+#define IT83XX_GCTRL_MCCR3 REG8(IT83XX_GCTRL_BASE + 0x20)
+#define IT83XX_GCTRL_SPISLVPFE BIT(6)
+#define IT83XX_GCTRL_RSTC5 REG8(IT83XX_GCTRL_BASE + 0x21)
+#define IT83XX_GCTRL_MCCR REG8(IT83XX_GCTRL_BASE + 0x30)
+#define IT83XX_GCTRL_PMER1 REG8(IT83XX_GCTRL_BASE + 0x32)
+#define IT83XX_GCTRL_PMER2 REG8(IT83XX_GCTRL_BASE + 0x33)
+#define IT83XX_GCTRL_EPLR REG8(IT83XX_GCTRL_BASE + 0x37)
+#define IT83XX_GCTRL_IVTBAR REG8(IT83XX_GCTRL_BASE + 0x41)
+#define IT83XX_GCTRL_MCCR2 REG8(IT83XX_GCTRL_BASE + 0x44)
+#define IT83XX_GCTRL_PIN_MUX0 REG8(IT83XX_GCTRL_BASE + 0x46)
+#define IT83XX_DLM14_ENABLE BIT(5)
+#define IT83XX_GCTRL_SSCR REG8(IT83XX_GCTRL_BASE + 0x4A)
+#define IT83XX_GCTRL_ETWDUARTCR REG8(IT83XX_GCTRL_BASE + 0x4B)
+#define IT83XX_GCTRL_WMCR REG8(IT83XX_GCTRL_BASE + 0x4C)
+#define IT83XX_GCTRL_H2ROFSR REG8(IT83XX_GCTRL_BASE + 0x53)
 /* bit[0] = 0 or 1 : disable or enable ETWD hardware reset */
-#define ETWD_HW_RST_EN            BIT(0)
-#define IT83XX_GCTRL_RVILMCR0     REG8(IT83XX_GCTRL_BASE+0x5D)
-#define ILMCR_ILM2_ENABLE         BIT(2)
-#define IT83XX_GCTRL_EWPR0PFH(i)  REG8(IT83XX_GCTRL_BASE+0x60+i)
-#define IT83XX_GCTRL_EWPR0PFD(i)  REG8(IT83XX_GCTRL_BASE+0xA0+i)
-#define IT83XX_GCTRL_EWPR0PFEC(i) REG8(IT83XX_GCTRL_BASE+0xC0+i)
+#define ETWD_HW_RST_EN BIT(0)
+#define IT83XX_GCTRL_RVILMCR0 REG8(IT83XX_GCTRL_BASE + 0x5D)
+#define ILMCR_ILM0_ENABLE BIT(0)
+#define ILMCR_ILM2_ENABLE BIT(2)
+#define IT83XX_GCTRL_EWPR0PFH(i) REG8(IT83XX_GCTRL_BASE + 0x60 + i)
+#define IT83XX_GCTRL_EWPR0PFD(i) REG8(IT83XX_GCTRL_BASE + 0xA0 + i)
+#define IT83XX_GCTRL_EWPR0PFEC(i) REG8(IT83XX_GCTRL_BASE + 0xC0 + i)
 
 /* --- Pulse Width Modulation (PWM) --- */
-#define IT83XX_PWM_BASE   0x00F01800
-
-#define IT83XX_PWM_C0CPRS       REG8(IT83XX_PWM_BASE+0x00)
-#define IT83XX_PWM_CTR          REG8(IT83XX_PWM_BASE+0x01)
-#define IT83XX_PWM_DCR0         REG8(IT83XX_PWM_BASE+0x02)
-#define IT83XX_PWM_DCR1         REG8(IT83XX_PWM_BASE+0x03)
-#define IT83XX_PWM_DCR2         REG8(IT83XX_PWM_BASE+0x04)
-#define IT83XX_PWM_DCR3         REG8(IT83XX_PWM_BASE+0x05)
-#define IT83XX_PWM_DCR4         REG8(IT83XX_PWM_BASE+0x06)
-#define IT83XX_PWM_DCR5         REG8(IT83XX_PWM_BASE+0x07)
-#define IT83XX_PWM_DCR6         REG8(IT83XX_PWM_BASE+0x08)
-#define IT83XX_PWM_DCR7         REG8(IT83XX_PWM_BASE+0x09)
-#define IT83XX_PWM_PWMPOL       REG8(IT83XX_PWM_BASE+0x0A)
-#define IT83XX_PWM_PCFSR        REG8(IT83XX_PWM_BASE+0x0B)
-#define IT83XX_PWM_PCSSGL       REG8(IT83XX_PWM_BASE+0x0C)
-#define IT83XX_PWM_PCSSGH       REG8(IT83XX_PWM_BASE+0x0D)
-#define IT83XX_PWM_CR256PCSSG   REG8(IT83XX_PWM_BASE+0x0E)
-#define IT83XX_PWM_PCSGR        REG8(IT83XX_PWM_BASE+0x0F)
-#define IT83XX_PWM_CTR1M        REG8(IT83XX_PWM_BASE+0x10)
-#define IT83XX_PWM_F1TLRR       REG8(IT83XX_PWM_BASE+0x1E)
-#define IT83XX_PWM_F1TMRR       REG8(IT83XX_PWM_BASE+0x1F)
-#define IT83XX_PWM_F2TLRR       REG8(IT83XX_PWM_BASE+0x20)
-#define IT83XX_PWM_F2TMRR       REG8(IT83XX_PWM_BASE+0x21)
-#define IT83XX_PWM_ZINTSCR      REG8(IT83XX_PWM_BASE+0x22)
-#define IT83XX_PWM_ZTIER        REG8(IT83XX_PWM_BASE+0x23)
-#define IT83XX_PWM_TSWCTLR      REG8(IT83XX_PWM_BASE+0x24)
-#define IT83XX_PWM_C4CPRS       REG8(IT83XX_PWM_BASE+0x27)
-#define IT83XX_PWM_C4MCPRS      REG8(IT83XX_PWM_BASE+0x28)
-#define IT83XX_PWM_C6CPRS       REG8(IT83XX_PWM_BASE+0x2B)
-#define IT83XX_PWM_C6MCPRS      REG8(IT83XX_PWM_BASE+0x2C)
-#define IT83XX_PWM_C7CPRS       REG8(IT83XX_PWM_BASE+0x2D)
-#define IT83XX_PWM_C7MCPRS      REG8(IT83XX_PWM_BASE+0x2E)
-#define IT83XX_PWM_CLK6MSEL     REG8(IT83XX_PWM_BASE+0x40)
-#define IT83XX_PWM_CTR1         REG8(IT83XX_PWM_BASE+0x41)
-#define IT83XX_PWM_CTR2         REG8(IT83XX_PWM_BASE+0x42)
-#define IT83XX_PWM_CTR3         REG8(IT83XX_PWM_BASE+0x43)
-#define IT83XX_PWM_PWM5TOCTRL   REG8(IT83XX_PWM_BASE+0x44)
-#define IT83XX_PWM_CFLRR        REG8(IT83XX_PWM_BASE+0x45)
-#define IT83XX_PWM_CFMRR        REG8(IT83XX_PWM_BASE+0x46)
-#define IT83XX_PWM_CFINTCTRL    REG8(IT83XX_PWM_BASE+0x47)
-#define IT83XX_PWM_TSWCTRL      REG8(IT83XX_PWM_BASE+0x48)
-#define IT83XX_PWM_PWMODENR     REG8(IT83XX_PWM_BASE+0x49)
+#define IT83XX_PWM_BASE 0x00F01800
+
+#define IT83XX_PWM_C0CPRS REG8(IT83XX_PWM_BASE + 0x00)
+#define IT83XX_PWM_CTR REG8(IT83XX_PWM_BASE + 0x01)
+#define IT83XX_PWM_DCR0 REG8(IT83XX_PWM_BASE + 0x02)
+#define IT83XX_PWM_DCR1 REG8(IT83XX_PWM_BASE + 0x03)
+#define IT83XX_PWM_DCR2 REG8(IT83XX_PWM_BASE + 0x04)
+#define IT83XX_PWM_DCR3 REG8(IT83XX_PWM_BASE + 0x05)
+#define IT83XX_PWM_DCR4 REG8(IT83XX_PWM_BASE + 0x06)
+#define IT83XX_PWM_DCR5 REG8(IT83XX_PWM_BASE + 0x07)
+#define IT83XX_PWM_DCR6 REG8(IT83XX_PWM_BASE + 0x08)
+#define IT83XX_PWM_DCR7 REG8(IT83XX_PWM_BASE + 0x09)
+#define IT83XX_PWM_PWMPOL REG8(IT83XX_PWM_BASE + 0x0A)
+#define IT83XX_PWM_PCFSR REG8(IT83XX_PWM_BASE + 0x0B)
+#define IT83XX_PWM_PCSSGL REG8(IT83XX_PWM_BASE + 0x0C)
+#define IT83XX_PWM_PCSSGH REG8(IT83XX_PWM_BASE + 0x0D)
+#define IT83XX_PWM_CR256PCSSG REG8(IT83XX_PWM_BASE + 0x0E)
+#define IT83XX_PWM_PCSGR REG8(IT83XX_PWM_BASE + 0x0F)
+#define IT83XX_PWM_CTR1M REG8(IT83XX_PWM_BASE + 0x10)
+#define IT83XX_PWM_F1TLRR REG8(IT83XX_PWM_BASE + 0x1E)
+#define IT83XX_PWM_F1TMRR REG8(IT83XX_PWM_BASE + 0x1F)
+#define IT83XX_PWM_F2TLRR REG8(IT83XX_PWM_BASE + 0x20)
+#define IT83XX_PWM_F2TMRR REG8(IT83XX_PWM_BASE + 0x21)
+#define IT83XX_PWM_ZINTSCR REG8(IT83XX_PWM_BASE + 0x22)
+#define IT83XX_PWM_ZTIER REG8(IT83XX_PWM_BASE + 0x23)
+#define IT83XX_PWM_TSWCTLR REG8(IT83XX_PWM_BASE + 0x24)
+#define IT83XX_PWM_C4CPRS REG8(IT83XX_PWM_BASE + 0x27)
+#define IT83XX_PWM_C4MCPRS REG8(IT83XX_PWM_BASE + 0x28)
+#define IT83XX_PWM_C6CPRS REG8(IT83XX_PWM_BASE + 0x2B)
+#define IT83XX_PWM_C6MCPRS REG8(IT83XX_PWM_BASE + 0x2C)
+#define IT83XX_PWM_C7CPRS REG8(IT83XX_PWM_BASE + 0x2D)
+#define IT83XX_PWM_C7MCPRS REG8(IT83XX_PWM_BASE + 0x2E)
+#define IT83XX_PWM_CLK6MSEL REG8(IT83XX_PWM_BASE + 0x40)
+#define IT83XX_PWM_CTR1 REG8(IT83XX_PWM_BASE + 0x41)
+#define IT83XX_PWM_CTR2 REG8(IT83XX_PWM_BASE + 0x42)
+#define IT83XX_PWM_CTR3 REG8(IT83XX_PWM_BASE + 0x43)
+#define IT83XX_PWM_PWM5TOCTRL REG8(IT83XX_PWM_BASE + 0x44)
+#define IT83XX_PWM_CFLRR REG8(IT83XX_PWM_BASE + 0x45)
+#define IT83XX_PWM_CFMRR REG8(IT83XX_PWM_BASE + 0x46)
+#define IT83XX_PWM_CFINTCTRL REG8(IT83XX_PWM_BASE + 0x47)
+#define IT83XX_PWM_TSWCTRL REG8(IT83XX_PWM_BASE + 0x48)
+#define IT83XX_PWM_PWMODENR REG8(IT83XX_PWM_BASE + 0x49)
 
 /* Analog to Digital Converter (ADC) */
-#define IT83XX_ADC_BASE   0x00F01900
-
-#define IT83XX_ADC_ADCSTS       REG8(IT83XX_ADC_BASE+0x00)
-#define IT83XX_ADC_ADCCFG       REG8(IT83XX_ADC_BASE+0x01)
-#define IT83XX_ADC_ADCCTL       REG8(IT83XX_ADC_BASE+0x02)
-#define IT83XX_ADC_ADCGCR       REG8(IT83XX_ADC_BASE+0x03)
-#define IT83XX_ADC_VCH0CTL      REG8(IT83XX_ADC_BASE+0x04)
-#define IT83XX_ADC_KDCTL        REG8(IT83XX_ADC_BASE+0x05)
-#define IT83XX_ADC_AHCE             BIT(7)
-#define IT83XX_ADC_VCH1CTL      REG8(IT83XX_ADC_BASE+0x06)
-#define IT83XX_ADC_VCH1DATL     REG8(IT83XX_ADC_BASE+0x07)
-#define IT83XX_ADC_VCH1DATM     REG8(IT83XX_ADC_BASE+0x08)
-#define IT83XX_ADC_VCH2CTL      REG8(IT83XX_ADC_BASE+0x09)
-#define IT83XX_ADC_VCH2DATL     REG8(IT83XX_ADC_BASE+0x0A)
-#define IT83XX_ADC_VCH2DATM     REG8(IT83XX_ADC_BASE+0x0B)
-#define IT83XX_ADC_VCH3CTL      REG8(IT83XX_ADC_BASE+0x0C)
-#define IT83XX_ADC_VCH3DATL     REG8(IT83XX_ADC_BASE+0x0D)
-#define IT83XX_ADC_VCH3DATM     REG8(IT83XX_ADC_BASE+0x0E)
-#define IT83XX_ADC_VHSCDBL      REG8(IT83XX_ADC_BASE+0x14)
-#define IT83XX_ADC_VHSCDBM      REG8(IT83XX_ADC_BASE+0x15)
-#define IT83XX_ADC_VCH0DATL     REG8(IT83XX_ADC_BASE+0x18)
-#define IT83XX_ADC_VCH0DATM     REG8(IT83XX_ADC_BASE+0x19)
-#define IT83XX_ADC_VHSGCDBL     REG8(IT83XX_ADC_BASE+0x1C)
-#define IT83XX_ADC_VHSGCDBM     REG8(IT83XX_ADC_BASE+0x1D)
-#define IT83XX_ADC_ADCSAR       REG8(IT83XX_ADC_BASE+0x32)
-#define IT83XX_ADC_VCMPSCP      REG8(IT83XX_ADC_BASE+0x37)
-#define IT83XX_ADC_VCH4CTL      REG8(IT83XX_ADC_BASE+0x38)
-#define IT83XX_ADC_VCH4DATM     REG8(IT83XX_ADC_BASE+0x39)
-#define IT83XX_ADC_VCH4DATL     REG8(IT83XX_ADC_BASE+0x3A)
-#define IT83XX_ADC_VCH5CTL      REG8(IT83XX_ADC_BASE+0x3B)
-#define IT83XX_ADC_VCH5DATM     REG8(IT83XX_ADC_BASE+0x3C)
-#define IT83XX_ADC_VCH5DATL     REG8(IT83XX_ADC_BASE+0x3D)
-#define IT83XX_ADC_VCH6CTL      REG8(IT83XX_ADC_BASE+0x3E)
-#define IT83XX_ADC_VCH6DATM     REG8(IT83XX_ADC_BASE+0x3F)
-#define IT83XX_ADC_VCH6DATL     REG8(IT83XX_ADC_BASE+0x40)
-#define IT83XX_ADC_VCH7CTL      REG8(IT83XX_ADC_BASE+0x41)
-#define IT83XX_ADC_VCH7DATM     REG8(IT83XX_ADC_BASE+0x42)
-#define IT83XX_ADC_VCH7DATL     REG8(IT83XX_ADC_BASE+0x43)
-#define IT83XX_ADC_ADCDVSTS     REG8(IT83XX_ADC_BASE+0x44)
-#define IT83XX_ADC_VCMPSTS      REG8(IT83XX_ADC_BASE+0x45)
-#define IT83XX_ADC_VCMP0CTL     REG8(IT83XX_ADC_BASE+0x46)
-#define ADC_VCMP_CMPEN              BIT(7)
-#define ADC_VCMP_CMPINTEN           BIT(6)
-#define ADC_VCMP_GREATER_THRESHOLD  BIT(5)
-#define ADC_VCMP_EDGE_TRIGGER       BIT(4)
-#define ADC_VCMP_GPIO_ACTIVE_LOW    BIT(3)
-#define IT83XX_ADC_CMP0THRDATM  REG8(IT83XX_ADC_BASE+0x47)
-#define IT83XX_ADC_CMP0THRDATL  REG8(IT83XX_ADC_BASE+0x48)
-#define IT83XX_ADC_VCMP1CTL     REG8(IT83XX_ADC_BASE+0x49)
-#define IT83XX_ADC_CMP1THRDATM  REG8(IT83XX_ADC_BASE+0x4A)
-#define IT83XX_ADC_CMP1THRDATL  REG8(IT83XX_ADC_BASE+0x4B)
-#define IT83XX_ADC_VCMP2CTL     REG8(IT83XX_ADC_BASE+0x4C)
-#define IT83XX_ADC_CMP2THRDATM  REG8(IT83XX_ADC_BASE+0x4D)
-#define IT83XX_ADC_CMP2THRDATL  REG8(IT83XX_ADC_BASE+0x4E)
-#define IT83XX_ADC_VCH13CTL     REG8(IT83XX_ADC_BASE+0x60)
-#define IT83XX_ADC_VCH13DATM    REG8(IT83XX_ADC_BASE+0x61)
-#define IT83XX_ADC_VCH13DATL    REG8(IT83XX_ADC_BASE+0x62)
-#define IT83XX_ADC_VCH14CTL     REG8(IT83XX_ADC_BASE+0x63)
-#define IT83XX_ADC_VCH14DATM    REG8(IT83XX_ADC_BASE+0x64)
-#define IT83XX_ADC_VCH14DATL    REG8(IT83XX_ADC_BASE+0x65)
-#define IT83XX_ADC_VCH15CTL     REG8(IT83XX_ADC_BASE+0x66)
-#define IT83XX_ADC_VCH15DATM    REG8(IT83XX_ADC_BASE+0x67)
-#define IT83XX_ADC_VCH15DATL    REG8(IT83XX_ADC_BASE+0x68)
-#define IT83XX_ADC_VCH16CTL     REG8(IT83XX_ADC_BASE+0x69)
-#define IT83XX_ADC_VCH16DATM    REG8(IT83XX_ADC_BASE+0x6A)
-#define IT83XX_ADC_VCH16DATL    REG8(IT83XX_ADC_BASE+0x6B)
-#define IT83XX_ADC_ADCDVSTS2    REG8(IT83XX_ADC_BASE+0x6C)
-#define IT83XX_ADC_VCMPSTS2     REG8(IT83XX_ADC_BASE+0x6D)
-#define IT83XX_ADC_VCMP3CTL     REG8(IT83XX_ADC_BASE+0x6E)
-#define IT83XX_ADC_CMP3THRDATM  REG8(IT83XX_ADC_BASE+0x6F)
-#define IT83XX_ADC_CMP3THRDATL  REG8(IT83XX_ADC_BASE+0x70)
-#define IT83XX_ADC_VCMP4CTL     REG8(IT83XX_ADC_BASE+0x71)
-#define IT83XX_ADC_CMP4THRDATM  REG8(IT83XX_ADC_BASE+0x72)
-#define IT83XX_ADC_CMP4THRDATL  REG8(IT83XX_ADC_BASE+0x73)
-#define IT83XX_ADC_VCMP5CTL     REG8(IT83XX_ADC_BASE+0x74)
-#define IT83XX_ADC_CMP5THRDATM  REG8(IT83XX_ADC_BASE+0x75)
-#define IT83XX_ADC_CMP5THRDATL  REG8(IT83XX_ADC_BASE+0x76)
-#define IT83XX_ADC_VCMP0CSELM   REG8(IT83XX_ADC_BASE+0x77)
-#define ADC_VCMP_VCMPCSELM          BIT(0)
-#define IT83XX_ADC_VCMP1CSELM   REG8(IT83XX_ADC_BASE+0x78)
-#define IT83XX_ADC_VCMP2CSELM   REG8(IT83XX_ADC_BASE+0x79)
-#define IT83XX_ADC_VCMP3CSELM   REG8(IT83XX_ADC_BASE+0x7A)
-#define IT83XX_ADC_VCMP4CSELM   REG8(IT83XX_ADC_BASE+0x7B)
-#define IT83XX_ADC_VCMP5CSELM   REG8(IT83XX_ADC_BASE+0x7C)
+#define IT83XX_ADC_BASE 0x00F01900
+
+#define IT83XX_ADC_ADCSTS REG8(IT83XX_ADC_BASE + 0x00)
+#define IT83XX_ADC_ADCCFG REG8(IT83XX_ADC_BASE + 0x01)
+#define IT83XX_ADC_ADCCTL REG8(IT83XX_ADC_BASE + 0x02)
+#define IT83XX_ADC_ADCGCR REG8(IT83XX_ADC_BASE + 0x03)
+#define IT83XX_ADC_DBKEN BIT(7) /* ADC data buffer keep enable. */
+#define IT83XX_ADC_VCH0CTL REG8(IT83XX_ADC_BASE + 0x04)
+#define IT83XX_ADC_KDCTL REG8(IT83XX_ADC_BASE + 0x05)
+#define IT83XX_ADC_AHCE BIT(7)
+#define IT83XX_ADC_VCH1CTL REG8(IT83XX_ADC_BASE + 0x06)
+#define IT83XX_ADC_VCH1DATL REG8(IT83XX_ADC_BASE + 0x07)
+#define IT83XX_ADC_VCH1DATM REG8(IT83XX_ADC_BASE + 0x08)
+#define IT83XX_ADC_VCH2CTL REG8(IT83XX_ADC_BASE + 0x09)
+#define IT83XX_ADC_VCH2DATL REG8(IT83XX_ADC_BASE + 0x0A)
+#define IT83XX_ADC_VCH2DATM REG8(IT83XX_ADC_BASE + 0x0B)
+#define IT83XX_ADC_VCH3CTL REG8(IT83XX_ADC_BASE + 0x0C)
+#define IT83XX_ADC_VCH3DATL REG8(IT83XX_ADC_BASE + 0x0D)
+#define IT83XX_ADC_VCH3DATM REG8(IT83XX_ADC_BASE + 0x0E)
+#define IT83XX_ADC_VHSCDBL REG8(IT83XX_ADC_BASE + 0x14)
+#define IT83XX_ADC_VHSCDBM REG8(IT83XX_ADC_BASE + 0x15)
+#define IT83XX_ADC_VCH0DATL REG8(IT83XX_ADC_BASE + 0x18)
+#define IT83XX_ADC_VCH0DATM REG8(IT83XX_ADC_BASE + 0x19)
+#define IT83XX_ADC_VHSGCDBL REG8(IT83XX_ADC_BASE + 0x1C)
+#define IT83XX_ADC_VHSGCDBM REG8(IT83XX_ADC_BASE + 0x1D)
+#define IT83XX_ADC_ADCSAR REG8(IT83XX_ADC_BASE + 0x32)
+#define IT83XX_ADC_VCMPSCP REG8(IT83XX_ADC_BASE + 0x37)
+#define IT83XX_ADC_VCH4CTL REG8(IT83XX_ADC_BASE + 0x38)
+#define IT83XX_ADC_VCH4DATM REG8(IT83XX_ADC_BASE + 0x39)
+#define IT83XX_ADC_VCH4DATL REG8(IT83XX_ADC_BASE + 0x3A)
+#define IT83XX_ADC_VCH5CTL REG8(IT83XX_ADC_BASE + 0x3B)
+#define IT83XX_ADC_VCH5DATM REG8(IT83XX_ADC_BASE + 0x3C)
+#define IT83XX_ADC_VCH5DATL REG8(IT83XX_ADC_BASE + 0x3D)
+#define IT83XX_ADC_VCH6CTL REG8(IT83XX_ADC_BASE + 0x3E)
+#define IT83XX_ADC_VCH6DATM REG8(IT83XX_ADC_BASE + 0x3F)
+#define IT83XX_ADC_VCH6DATL REG8(IT83XX_ADC_BASE + 0x40)
+#define IT83XX_ADC_VCH7CTL REG8(IT83XX_ADC_BASE + 0x41)
+#define IT83XX_ADC_VCH7DATM REG8(IT83XX_ADC_BASE + 0x42)
+#define IT83XX_ADC_VCH7DATL REG8(IT83XX_ADC_BASE + 0x43)
+#define IT83XX_ADC_ADCDVSTS REG8(IT83XX_ADC_BASE + 0x44)
+#define IT83XX_ADC_VCMPSTS REG8(IT83XX_ADC_BASE + 0x45)
+#define IT83XX_ADC_VCMP0CTL REG8(IT83XX_ADC_BASE + 0x46)
+#define ADC_VCMP_CMPEN BIT(7)
+#define ADC_VCMP_CMPINTEN BIT(6)
+#define ADC_VCMP_GREATER_THRESHOLD BIT(5)
+#define ADC_VCMP_EDGE_TRIGGER BIT(4)
+#define ADC_VCMP_GPIO_ACTIVE_LOW BIT(3)
+#define IT83XX_ADC_CMP0THRDATM REG8(IT83XX_ADC_BASE + 0x47)
+#define IT83XX_ADC_CMP0THRDATL REG8(IT83XX_ADC_BASE + 0x48)
+#define IT83XX_ADC_VCMP1CTL REG8(IT83XX_ADC_BASE + 0x49)
+#define IT83XX_ADC_CMP1THRDATM REG8(IT83XX_ADC_BASE + 0x4A)
+#define IT83XX_ADC_CMP1THRDATL REG8(IT83XX_ADC_BASE + 0x4B)
+#define IT83XX_ADC_VCMP2CTL REG8(IT83XX_ADC_BASE + 0x4C)
+#define IT83XX_ADC_CMP2THRDATM REG8(IT83XX_ADC_BASE + 0x4D)
+#define IT83XX_ADC_CMP2THRDATL REG8(IT83XX_ADC_BASE + 0x4E)
+#define IT83XX_ADC_VCH13CTL REG8(IT83XX_ADC_BASE + 0x60)
+#define IT83XX_ADC_VCH13DATM REG8(IT83XX_ADC_BASE + 0x61)
+#define IT83XX_ADC_VCH13DATL REG8(IT83XX_ADC_BASE + 0x62)
+#define IT83XX_ADC_VCH14CTL REG8(IT83XX_ADC_BASE + 0x63)
+#define IT83XX_ADC_VCH14DATM REG8(IT83XX_ADC_BASE + 0x64)
+#define IT83XX_ADC_VCH14DATL REG8(IT83XX_ADC_BASE + 0x65)
+#define IT83XX_ADC_VCH15CTL REG8(IT83XX_ADC_BASE + 0x66)
+#define IT83XX_ADC_VCH15DATM REG8(IT83XX_ADC_BASE + 0x67)
+#define IT83XX_ADC_VCH15DATL REG8(IT83XX_ADC_BASE + 0x68)
+#define IT83XX_ADC_VCH16CTL REG8(IT83XX_ADC_BASE + 0x69)
+#define IT83XX_ADC_VCH16DATM REG8(IT83XX_ADC_BASE + 0x6A)
+#define IT83XX_ADC_VCH16DATL REG8(IT83XX_ADC_BASE + 0x6B)
+#define IT83XX_ADC_ADCDVSTS2 REG8(IT83XX_ADC_BASE + 0x6C)
+#define IT83XX_ADC_VCMPSTS2 REG8(IT83XX_ADC_BASE + 0x6D)
+#define IT83XX_ADC_VCMP3CTL REG8(IT83XX_ADC_BASE + 0x6E)
+#define IT83XX_ADC_CMP3THRDATM REG8(IT83XX_ADC_BASE + 0x6F)
+#define IT83XX_ADC_CMP3THRDATL REG8(IT83XX_ADC_BASE + 0x70)
+#define IT83XX_ADC_VCMP4CTL REG8(IT83XX_ADC_BASE + 0x71)
+#define IT83XX_ADC_CMP4THRDATM REG8(IT83XX_ADC_BASE + 0x72)
+#define IT83XX_ADC_CMP4THRDATL REG8(IT83XX_ADC_BASE + 0x73)
+#define IT83XX_ADC_VCMP5CTL REG8(IT83XX_ADC_BASE + 0x74)
+#define IT83XX_ADC_CMP5THRDATM REG8(IT83XX_ADC_BASE + 0x75)
+#define IT83XX_ADC_CMP5THRDATL REG8(IT83XX_ADC_BASE + 0x76)
+#define IT83XX_ADC_VCMP0CSELM REG8(IT83XX_ADC_BASE + 0x77)
+#define ADC_VCMP_VCMPCSELM BIT(0)
+#define IT83XX_ADC_VCMP1CSELM REG8(IT83XX_ADC_BASE + 0x78)
+#define IT83XX_ADC_VCMP2CSELM REG8(IT83XX_ADC_BASE + 0x79)
+#define IT83XX_ADC_VCMP3CSELM REG8(IT83XX_ADC_BASE + 0x7A)
+#define IT83XX_ADC_VCMP4CSELM REG8(IT83XX_ADC_BASE + 0x7B)
+#define IT83XX_ADC_VCMP5CSELM REG8(IT83XX_ADC_BASE + 0x7C)
 
 /* Digital to Analog Converter (DAC) */
-#define IT83XX_DAC_BASE   0x00F01A00
+#define IT83XX_DAC_BASE 0x00F01A00
 
-#define IT83XX_DAC_DACPDREG     REG8(IT83XX_DAC_BASE+0x01)
-#define IT83XX_DAC_POWDN(ch)    BIT(ch)
-#define IT83XX_DAC_DACDAT(ch)   REG8(IT83XX_DAC_BASE+0x02+ch)
+#define IT83XX_DAC_DACPDREG REG8(IT83XX_DAC_BASE + 0x01)
+#define IT83XX_DAC_POWDN(ch) BIT(ch)
+#define IT83XX_DAC_DACDAT(ch) REG8(IT83XX_DAC_BASE + 0x02 + ch)
 
 /* Keyboard Controller (KBC) */
-#define IT83XX_KBC_BASE   0x00F01300
+#define IT83XX_KBC_BASE 0x00F01300
 
-#define IT83XX_KBC_KBHICR       REG8(IT83XX_KBC_BASE+0x00)
-#define IT83XX_KBC_KBIRQR       REG8(IT83XX_KBC_BASE+0x02)
-#define IT83XX_KBC_KBHISR       REG8(IT83XX_KBC_BASE+0x04)
-#define IT83XX_KBC_KBHIKDOR     REG8(IT83XX_KBC_BASE+0x06)
-#define IT83XX_KBC_KBHIMDOR     REG8(IT83XX_KBC_BASE+0x08)
-#define IT83XX_KBC_KBHIDIR      REG8(IT83XX_KBC_BASE+0x0A)
+#define IT83XX_KBC_KBHICR REG8(IT83XX_KBC_BASE + 0x00)
+#define IT83XX_KBC_KBIRQR REG8(IT83XX_KBC_BASE + 0x02)
+#define IT83XX_KBC_KBHISR REG8(IT83XX_KBC_BASE + 0x04)
+#define IT83XX_KBC_KBHIKDOR REG8(IT83XX_KBC_BASE + 0x06)
+#define IT83XX_KBC_KBHIMDOR REG8(IT83XX_KBC_BASE + 0x08)
+#define IT83XX_KBC_KBHIDIR REG8(IT83XX_KBC_BASE + 0x0A)
 
 /* Power Management Channel (PMC) */
-#define IT83XX_PMC_BASE   0x00F01500
-
-#define IT83XX_PMC_PM1STS       REG8(IT83XX_PMC_BASE+0x00)
-#define IT83XX_PMC_PM1DO        REG8(IT83XX_PMC_BASE+0x01)
-#define IT83XX_PMC_PM1DOSCI     REG8(IT83XX_PMC_BASE+0x02)
-#define IT83XX_PMC_PM1DOSMI     REG8(IT83XX_PMC_BASE+0x03)
-#define IT83XX_PMC_PM1DI        REG8(IT83XX_PMC_BASE+0x04)
-#define IT83XX_PMC_PM1DISCI     REG8(IT83XX_PMC_BASE+0x05)
-#define IT83XX_PMC_PM1CTL       REG8(IT83XX_PMC_BASE+0x06)
-#define IT83XX_PMC_PM1IC        REG8(IT83XX_PMC_BASE+0x07)
-#define IT83XX_PMC_PM1IE        REG8(IT83XX_PMC_BASE+0x08)
-#define IT83XX_PMC_PM2STS       REG8(IT83XX_PMC_BASE+0x10)
-#define IT83XX_PMC_PM2DO        REG8(IT83XX_PMC_BASE+0x11)
-#define IT83XX_PMC_PM2DOSCI     REG8(IT83XX_PMC_BASE+0x12)
-#define IT83XX_PMC_PM2DOSMI     REG8(IT83XX_PMC_BASE+0x13)
-#define IT83XX_PMC_PM2DI        REG8(IT83XX_PMC_BASE+0x14)
-#define IT83XX_PMC_PM2DISCI     REG8(IT83XX_PMC_BASE+0x15)
-#define IT83XX_PMC_PM2CTL       REG8(IT83XX_PMC_BASE+0x16)
-#define IT83XX_PMC_PM2IC        REG8(IT83XX_PMC_BASE+0x17)
-#define IT83XX_PMC_PM2IE        REG8(IT83XX_PMC_BASE+0x18)
-#define IT83XX_PMC_PM3STS       REG8(IT83XX_PMC_BASE+0x20)
-#define IT83XX_PMC_PM3DO        REG8(IT83XX_PMC_BASE+0x21)
-#define IT83XX_PMC_PM3DI        REG8(IT83XX_PMC_BASE+0x22)
-#define IT83XX_PMC_PM3CTL       REG8(IT83XX_PMC_BASE+0x23)
-#define IT83XX_PMC_PM3IC        REG8(IT83XX_PMC_BASE+0x24)
-#define IT83XX_PMC_PM3IE        REG8(IT83XX_PMC_BASE+0x25)
-#define IT83XX_PMC_PM4STS       REG8(IT83XX_PMC_BASE+0x30)
-#define IT83XX_PMC_PM4DO        REG8(IT83XX_PMC_BASE+0x31)
-#define IT83XX_PMC_PM4DI        REG8(IT83XX_PMC_BASE+0x32)
-#define IT83XX_PMC_PM4CTL       REG8(IT83XX_PMC_BASE+0x33)
-#define IT83XX_PMC_PM4IC        REG8(IT83XX_PMC_BASE+0x34)
-#define IT83XX_PMC_PM4IE        REG8(IT83XX_PMC_BASE+0x35)
-#define IT83XX_PMC_PM5STS       REG8(IT83XX_PMC_BASE+0x40)
-#define IT83XX_PMC_PM5DO        REG8(IT83XX_PMC_BASE+0x41)
-#define IT83XX_PMC_PM5DI        REG8(IT83XX_PMC_BASE+0x42)
-#define IT83XX_PMC_PM5CTL       REG8(IT83XX_PMC_BASE+0x43)
-#define IT83XX_PMC_PM5IC        REG8(IT83XX_PMC_BASE+0x44)
-#define IT83XX_PMC_PM5IE        REG8(IT83XX_PMC_BASE+0x45)
-#define IT83XX_PMC_MBXCTRL      REG8(IT83XX_PMC_BASE+0x19)
-#define IT83XX_PMC_MBXEC_00     REG8(IT83XX_PMC_BASE+0xF0)
-#define IT83XX_PMC_MBXEC_01     REG8(IT83XX_PMC_BASE+0xF1)
-#define IT83XX_PMC_MBXEC_02     REG8(IT83XX_PMC_BASE+0xF2)
-#define IT83XX_PMC_MBXEC_03     REG8(IT83XX_PMC_BASE+0xF3)
-#define IT83XX_PMC_MBXEC_04     REG8(IT83XX_PMC_BASE+0xF4)
-#define IT83XX_PMC_MBXEC_05     REG8(IT83XX_PMC_BASE+0xF5)
-#define IT83XX_PMC_MBXEC_06     REG8(IT83XX_PMC_BASE+0xF6)
-#define IT83XX_PMC_MBXEC_07     REG8(IT83XX_PMC_BASE+0xF7)
-#define IT83XX_PMC_MBXEC_08     REG8(IT83XX_PMC_BASE+0xF8)
-#define IT83XX_PMC_MBXEC_09     REG8(IT83XX_PMC_BASE+0xF9)
-#define IT83XX_PMC_MBXEC_10     REG8(IT83XX_PMC_BASE+0xFA)
-#define IT83XX_PMC_MBXEC_11     REG8(IT83XX_PMC_BASE+0xFB)
-#define IT83XX_PMC_MBXEC_12     REG8(IT83XX_PMC_BASE+0xFC)
-#define IT83XX_PMC_MBXEC_13     REG8(IT83XX_PMC_BASE+0xFD)
-#define IT83XX_PMC_MBXEC_14     REG8(IT83XX_PMC_BASE+0xFE)
-#define IT83XX_PMC_MBXEC_15     REG8(IT83XX_PMC_BASE+0xFF)
-#define IT83XX_PMC_PMSTS(ch)    REG8(IT83XX_PMC_BASE + 0x00 + (ch << 4))
-#define IT83XX_PMC_PMDO(ch)     REG8(IT83XX_PMC_BASE + 0x01 + (ch << 4))
-#define IT83XX_PMC_PMDI(ch)     \
-REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 2 : 4) + (ch << 4))
-#define IT83XX_PMC_PMCTL(ch)     \
-REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 3 : 6) + (ch << 4))
-#define IT83XX_PMC_PMIE(ch)     \
-REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 5 : 8) + (ch << 4))
+#define IT83XX_PMC_BASE 0x00F01500
+
+#define IT83XX_PMC_PM1STS REG8(IT83XX_PMC_BASE + 0x00)
+#define IT83XX_PMC_PM1DO REG8(IT83XX_PMC_BASE + 0x01)
+#define IT83XX_PMC_PM1DOSCI REG8(IT83XX_PMC_BASE + 0x02)
+#define IT83XX_PMC_PM1DOSMI REG8(IT83XX_PMC_BASE + 0x03)
+#define IT83XX_PMC_PM1DI REG8(IT83XX_PMC_BASE + 0x04)
+#define IT83XX_PMC_PM1DISCI REG8(IT83XX_PMC_BASE + 0x05)
+#define IT83XX_PMC_PM1CTL REG8(IT83XX_PMC_BASE + 0x06)
+#define IT83XX_PMC_PM1IC REG8(IT83XX_PMC_BASE + 0x07)
+#define IT83XX_PMC_PM1IE REG8(IT83XX_PMC_BASE + 0x08)
+#define IT83XX_PMC_PM2STS REG8(IT83XX_PMC_BASE + 0x10)
+#define IT83XX_PMC_PM2DO REG8(IT83XX_PMC_BASE + 0x11)
+#define IT83XX_PMC_PM2DOSCI REG8(IT83XX_PMC_BASE + 0x12)
+#define IT83XX_PMC_PM2DOSMI REG8(IT83XX_PMC_BASE + 0x13)
+#define IT83XX_PMC_PM2DI REG8(IT83XX_PMC_BASE + 0x14)
+#define IT83XX_PMC_PM2DISCI REG8(IT83XX_PMC_BASE + 0x15)
+#define IT83XX_PMC_PM2CTL REG8(IT83XX_PMC_BASE + 0x16)
+#define IT83XX_PMC_PM2IC REG8(IT83XX_PMC_BASE + 0x17)
+#define IT83XX_PMC_PM2IE REG8(IT83XX_PMC_BASE + 0x18)
+#define IT83XX_PMC_PM3STS REG8(IT83XX_PMC_BASE + 0x20)
+#define IT83XX_PMC_PM3DO REG8(IT83XX_PMC_BASE + 0x21)
+#define IT83XX_PMC_PM3DI REG8(IT83XX_PMC_BASE + 0x22)
+#define IT83XX_PMC_PM3CTL REG8(IT83XX_PMC_BASE + 0x23)
+#define IT83XX_PMC_PM3IC REG8(IT83XX_PMC_BASE + 0x24)
+#define IT83XX_PMC_PM3IE REG8(IT83XX_PMC_BASE + 0x25)
+#define IT83XX_PMC_PM4STS REG8(IT83XX_PMC_BASE + 0x30)
+#define IT83XX_PMC_PM4DO REG8(IT83XX_PMC_BASE + 0x31)
+#define IT83XX_PMC_PM4DI REG8(IT83XX_PMC_BASE + 0x32)
+#define IT83XX_PMC_PM4CTL REG8(IT83XX_PMC_BASE + 0x33)
+#define IT83XX_PMC_PM4IC REG8(IT83XX_PMC_BASE + 0x34)
+#define IT83XX_PMC_PM4IE REG8(IT83XX_PMC_BASE + 0x35)
+#define IT83XX_PMC_PM5STS REG8(IT83XX_PMC_BASE + 0x40)
+#define IT83XX_PMC_PM5DO REG8(IT83XX_PMC_BASE + 0x41)
+#define IT83XX_PMC_PM5DI REG8(IT83XX_PMC_BASE + 0x42)
+#define IT83XX_PMC_PM5CTL REG8(IT83XX_PMC_BASE + 0x43)
+#define IT83XX_PMC_PM5IC REG8(IT83XX_PMC_BASE + 0x44)
+#define IT83XX_PMC_PM5IE REG8(IT83XX_PMC_BASE + 0x45)
+#define IT83XX_PMC_MBXCTRL REG8(IT83XX_PMC_BASE + 0x19)
+#define IT83XX_PMC_MBXEC_00 REG8(IT83XX_PMC_BASE + 0xF0)
+#define IT83XX_PMC_MBXEC_01 REG8(IT83XX_PMC_BASE + 0xF1)
+#define IT83XX_PMC_MBXEC_02 REG8(IT83XX_PMC_BASE + 0xF2)
+#define IT83XX_PMC_MBXEC_03 REG8(IT83XX_PMC_BASE + 0xF3)
+#define IT83XX_PMC_MBXEC_04 REG8(IT83XX_PMC_BASE + 0xF4)
+#define IT83XX_PMC_MBXEC_05 REG8(IT83XX_PMC_BASE + 0xF5)
+#define IT83XX_PMC_MBXEC_06 REG8(IT83XX_PMC_BASE + 0xF6)
+#define IT83XX_PMC_MBXEC_07 REG8(IT83XX_PMC_BASE + 0xF7)
+#define IT83XX_PMC_MBXEC_08 REG8(IT83XX_PMC_BASE + 0xF8)
+#define IT83XX_PMC_MBXEC_09 REG8(IT83XX_PMC_BASE + 0xF9)
+#define IT83XX_PMC_MBXEC_10 REG8(IT83XX_PMC_BASE + 0xFA)
+#define IT83XX_PMC_MBXEC_11 REG8(IT83XX_PMC_BASE + 0xFB)
+#define IT83XX_PMC_MBXEC_12 REG8(IT83XX_PMC_BASE + 0xFC)
+#define IT83XX_PMC_MBXEC_13 REG8(IT83XX_PMC_BASE + 0xFD)
+#define IT83XX_PMC_MBXEC_14 REG8(IT83XX_PMC_BASE + 0xFE)
+#define IT83XX_PMC_MBXEC_15 REG8(IT83XX_PMC_BASE + 0xFF)
+#define IT83XX_PMC_PMSTS(ch) REG8(IT83XX_PMC_BASE + 0x00 + (ch << 4))
+#define IT83XX_PMC_PMDO(ch) REG8(IT83XX_PMC_BASE + 0x01 + (ch << 4))
+#define IT83XX_PMC_PMDI(ch) \
+	REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 2 : 4) + (ch << 4))
+#define IT83XX_PMC_PMCTL(ch) \
+	REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 3 : 6) + (ch << 4))
+#define IT83XX_PMC_PMIE(ch) \
+	REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 5 : 8) + (ch << 4))
 
 /* Keyboard Matrix Scan control (KBS) */
-#define IT83XX_KBS_BASE   0x00F01D00
-
-#define IT83XX_KBS_KSOL         REG8(IT83XX_KBS_BASE+0x00)
-#define IT83XX_KBS_KSOH1        REG8(IT83XX_KBS_BASE+0x01)
-#define IT83XX_KBS_KSOCTRL      REG8(IT83XX_KBS_BASE+0x02)
-#define IT83XX_KBS_KSOH2        REG8(IT83XX_KBS_BASE+0x03)
-#define IT83XX_KBS_KSI          REG8(IT83XX_KBS_BASE+0x04)
-#define IT83XX_KBS_KSICTRL      REG8(IT83XX_KBS_BASE+0x05)
-#define IT83XX_KBS_KSIGCTRL     REG8(IT83XX_KBS_BASE+0x06)
-#define IT83XX_KBS_KSIGOEN      REG8(IT83XX_KBS_BASE+0x07)
-#define IT83XX_KBS_KSIGDAT      REG8(IT83XX_KBS_BASE+0x08)
-#define IT83XX_KBS_KSIGDMRR     REG8(IT83XX_KBS_BASE+0x09)
-#define IT83XX_KBS_KSOHGCTRL    REG8(IT83XX_KBS_BASE+0x0A)
-#define IT83XX_KBS_KSOHGOEN     REG8(IT83XX_KBS_BASE+0x0B)
-#define IT83XX_KBS_KSOHGDMRR    REG8(IT83XX_KBS_BASE+0x0C)
-#define IT83XX_KBS_KSOLGCTRL    REG8(IT83XX_KBS_BASE+0x0D)
-#define IT83XX_KBS_KSOLGOEN     REG8(IT83XX_KBS_BASE+0x0E)
-#define IT83XX_KBS_KSOLGDMRR    REG8(IT83XX_KBS_BASE+0x0F)
-#define IT83XX_KBS_KSO0LSDR     REG8(IT83XX_KBS_BASE+0x10)
-#define IT83XX_KBS_KSO1LSDR     REG8(IT83XX_KBS_BASE+0x11)
-#define IT83XX_KBS_KSO2LSDR     REG8(IT83XX_KBS_BASE+0x12)
-#define IT83XX_KBS_KSO3LSDR     REG8(IT83XX_KBS_BASE+0x13)
-#define IT83XX_KBS_KSO4LSDR     REG8(IT83XX_KBS_BASE+0x14)
-#define IT83XX_KBS_KSO5LSDR     REG8(IT83XX_KBS_BASE+0x15)
-#define IT83XX_KBS_KSO6LSDR     REG8(IT83XX_KBS_BASE+0x16)
-#define IT83XX_KBS_KSO7LSDR     REG8(IT83XX_KBS_BASE+0x17)
-#define IT83XX_KBS_KSO8LSDR     REG8(IT83XX_KBS_BASE+0x18)
-#define IT83XX_KBS_KSO9LSDR     REG8(IT83XX_KBS_BASE+0x19)
-#define IT83XX_KBS_KSO10LSDR    REG8(IT83XX_KBS_BASE+0x1A)
-#define IT83XX_KBS_KSO11LSDR    REG8(IT83XX_KBS_BASE+0x1B)
-#define IT83XX_KBS_KSO12LSDR    REG8(IT83XX_KBS_BASE+0x1C)
-#define IT83XX_KBS_KSO13LSDR    REG8(IT83XX_KBS_BASE+0x1D)
-#define IT83XX_KBS_KSO14LSDR    REG8(IT83XX_KBS_BASE+0x1E)
-#define IT83XX_KBS_KSO15LSDR    REG8(IT83XX_KBS_BASE+0x1F)
-#define IT83XX_KBS_KSO16LSDR    REG8(IT83XX_KBS_BASE+0x20)
-#define IT83XX_KBS_KSO17LSDR    REG8(IT83XX_KBS_BASE+0x21)
-#define IT83XX_KBS_SDC1R        REG8(IT83XX_KBS_BASE+0x22)
-#define IT83XX_KBS_SDC2R        REG8(IT83XX_KBS_BASE+0x23)
-#define IT83XX_KBS_SDC3R        REG8(IT83XX_KBS_BASE+0x24)
-#define IT83XX_KBS_SDSR         REG8(IT83XX_KBS_BASE+0x25)
+#define IT83XX_KBS_BASE 0x00F01D00
+
+#define IT83XX_KBS_KSOL REG8(IT83XX_KBS_BASE + 0x00)
+#define IT83XX_KBS_KSOH1 REG8(IT83XX_KBS_BASE + 0x01)
+#define IT83XX_KBS_KSOCTRL REG8(IT83XX_KBS_BASE + 0x02)
+#define IT83XX_KBS_KSOH2 REG8(IT83XX_KBS_BASE + 0x03)
+#define IT83XX_KBS_KSI REG8(IT83XX_KBS_BASE + 0x04)
+#define IT83XX_KBS_KSICTRL REG8(IT83XX_KBS_BASE + 0x05)
+#define IT83XX_KBS_KSIGCTRL REG8(IT83XX_KBS_BASE + 0x06)
+#define IT83XX_KBS_KSIGOEN REG8(IT83XX_KBS_BASE + 0x07)
+#define IT83XX_KBS_KSIGDAT REG8(IT83XX_KBS_BASE + 0x08)
+#define IT83XX_KBS_KSIGDMRR REG8(IT83XX_KBS_BASE + 0x09)
+#define IT83XX_KBS_KSOHGCTRL REG8(IT83XX_KBS_BASE + 0x0A)
+#define IT83XX_KBS_KSOHGOEN REG8(IT83XX_KBS_BASE + 0x0B)
+#define IT83XX_KBS_KSOHGDMRR REG8(IT83XX_KBS_BASE + 0x0C)
+#define IT83XX_KBS_KSOLGCTRL REG8(IT83XX_KBS_BASE + 0x0D)
+#define IT83XX_KBS_KSOLGOEN REG8(IT83XX_KBS_BASE + 0x0E)
+#define IT83XX_KBS_KSOLGDMRR REG8(IT83XX_KBS_BASE + 0x0F)
+#define IT83XX_KBS_KSO0LSDR REG8(IT83XX_KBS_BASE + 0x10)
+#define IT83XX_KBS_KSO1LSDR REG8(IT83XX_KBS_BASE + 0x11)
+#define IT83XX_KBS_KSO2LSDR REG8(IT83XX_KBS_BASE + 0x12)
+#define IT83XX_KBS_KSO3LSDR REG8(IT83XX_KBS_BASE + 0x13)
+#define IT83XX_KBS_KSO4LSDR REG8(IT83XX_KBS_BASE + 0x14)
+#define IT83XX_KBS_KSO5LSDR REG8(IT83XX_KBS_BASE + 0x15)
+#define IT83XX_KBS_KSO6LSDR REG8(IT83XX_KBS_BASE + 0x16)
+#define IT83XX_KBS_KSO7LSDR REG8(IT83XX_KBS_BASE + 0x17)
+#define IT83XX_KBS_KSO8LSDR REG8(IT83XX_KBS_BASE + 0x18)
+#define IT83XX_KBS_KSO9LSDR REG8(IT83XX_KBS_BASE + 0x19)
+#define IT83XX_KBS_KSO10LSDR REG8(IT83XX_KBS_BASE + 0x1A)
+#define IT83XX_KBS_KSO11LSDR REG8(IT83XX_KBS_BASE + 0x1B)
+#define IT83XX_KBS_KSO12LSDR REG8(IT83XX_KBS_BASE + 0x1C)
+#define IT83XX_KBS_KSO13LSDR REG8(IT83XX_KBS_BASE + 0x1D)
+#define IT83XX_KBS_KSO14LSDR REG8(IT83XX_KBS_BASE + 0x1E)
+#define IT83XX_KBS_KSO15LSDR REG8(IT83XX_KBS_BASE + 0x1F)
+#define IT83XX_KBS_KSO16LSDR REG8(IT83XX_KBS_BASE + 0x20)
+#define IT83XX_KBS_KSO17LSDR REG8(IT83XX_KBS_BASE + 0x21)
+#define IT83XX_KBS_SDC1R REG8(IT83XX_KBS_BASE + 0x22)
+#define IT83XX_KBS_SDC2R REG8(IT83XX_KBS_BASE + 0x23)
+#define IT83XX_KBS_SDC3R REG8(IT83XX_KBS_BASE + 0x24)
+#define IT83XX_KBS_SDSR REG8(IT83XX_KBS_BASE + 0x25)
+#define IT83XX_KBS_KSIGPODR REG8(IT83XX_KBS_BASE + 0x26)
+#define IT83XX_KBS_KSOHGPODR REG8(IT83XX_KBS_BASE + 0x27)
+#define IT83XX_KBS_KSOLGPODR REG8(IT83XX_KBS_BASE + 0x28)
 
 /* Shared Memory Flash Interface Bridge (SMFI) */
-#define IT83XX_SMFI_BASE  0x00F01000
-
-#define IT83XX_SMFI_SMECCS      REG8(IT83XX_SMFI_BASE+0x20)
-#define IT83XX_SMFI_MASK_HOSTWA 	BIT(5)
-#define IT83XX_SMFI_HRAMWC      REG8(IT83XX_SMFI_BASE+0x5A)
-#define IT83XX_SMFI_HRAMW0BA    REG8(IT83XX_SMFI_BASE+0x5B)
-#define IT83XX_SMFI_HRAMW1BA    REG8(IT83XX_SMFI_BASE+0x5C)
-#define IT83XX_SMFI_HRAMW0AAS   REG8(IT83XX_SMFI_BASE+0x5D)
-#define IT83XX_SMFI_HRAMW1AAS   REG8(IT83XX_SMFI_BASE+0x5E)
-#define IT83XX_SMFI_HRAMW2BA    REG8(IT83XX_SMFI_BASE+0x76)
-#define IT83XX_SMFI_HRAMW3BA    REG8(IT83XX_SMFI_BASE+0x77)
-#define IT83XX_SMFI_HRAMW2AAS   REG8(IT83XX_SMFI_BASE+0x78)
-#define IT83XX_SMFI_HRAMW3AAS   REG8(IT83XX_SMFI_BASE+0x79)
-#define IT83XX_SMFI_H2RAMECSIE  REG8(IT83XX_SMFI_BASE+0x7A)
-#define IT83XX_SMFI_H2RAMECSA   REG8(IT83XX_SMFI_BASE+0x7B)
-#define IT83XX_SMFI_H2RAMHSS    REG8(IT83XX_SMFI_BASE+0x7C)
-#define IT83XX_SMFI_ECINDAR0    REG8(IT83XX_SMFI_BASE+0x3B)
-#define IT83XX_SMFI_ECINDAR1    REG8(IT83XX_SMFI_BASE+0x3C)
-#define IT83XX_SMFI_ECINDAR2    REG8(IT83XX_SMFI_BASE+0x3D)
-#define IT83XX_SMFI_ECINDAR3    REG8(IT83XX_SMFI_BASE+0x3E)
+#define IT83XX_SMFI_BASE 0x00F01000
+
+#define IT83XX_SMFI_SMECCS REG8(IT83XX_SMFI_BASE + 0x20)
+#define IT83XX_SMFI_MASK_HOSTWA BIT(5)
+#define IT83XX_SMFI_HRAMWC REG8(IT83XX_SMFI_BASE + 0x5A)
+#define IT83XX_SMFI_HRAMW0BA REG8(IT83XX_SMFI_BASE + 0x5B)
+#define IT83XX_SMFI_HRAMW1BA REG8(IT83XX_SMFI_BASE + 0x5C)
+#define IT83XX_SMFI_HRAMW0AAS REG8(IT83XX_SMFI_BASE + 0x5D)
+#define IT83XX_SMFI_HRAMW1AAS REG8(IT83XX_SMFI_BASE + 0x5E)
+#define IT83XX_SMFI_HRAMW2BA REG8(IT83XX_SMFI_BASE + 0x76)
+#define IT83XX_SMFI_HRAMW3BA REG8(IT83XX_SMFI_BASE + 0x77)
+#define IT83XX_SMFI_HRAMW2AAS REG8(IT83XX_SMFI_BASE + 0x78)
+#define IT83XX_SMFI_HRAMW3AAS REG8(IT83XX_SMFI_BASE + 0x79)
+#define IT83XX_SMFI_H2RAMECSIE REG8(IT83XX_SMFI_BASE + 0x7A)
+#define IT83XX_SMFI_H2RAMECSA REG8(IT83XX_SMFI_BASE + 0x7B)
+#define IT83XX_SMFI_H2RAMHSS REG8(IT83XX_SMFI_BASE + 0x7C)
+#define IT83XX_SMFI_ECINDAR0 REG8(IT83XX_SMFI_BASE + 0x3B)
+#define IT83XX_SMFI_ECINDAR1 REG8(IT83XX_SMFI_BASE + 0x3C)
+#define IT83XX_SMFI_ECINDAR2 REG8(IT83XX_SMFI_BASE + 0x3D)
+#define IT83XX_SMFI_ECINDAR3 REG8(IT83XX_SMFI_BASE + 0x3E)
 #define EC_INDIRECT_READ_INTERNAL_FLASH BIT(6)
-#define IT83XX_SMFI_ECINDDR     REG8(IT83XX_SMFI_BASE+0x3F)
-#define IT83XX_SMFI_SCAR2L      REG8(IT83XX_SMFI_BASE+0x46)
-#define IT83XX_SMFI_SCAR2M      REG8(IT83XX_SMFI_BASE+0x47)
-#define IT83XX_SMFI_SCAR2H      REG8(IT83XX_SMFI_BASE+0x48)
-#define IT83XX_SMFI_FLHCTRL3R   REG8(IT83XX_SMFI_BASE+0x63)
-#define IT83XX_SMFI_STCDMACR    REG8(IT83XX_SMFI_BASE+0x80)
-#define IT83XX_SMFI_FLHCTRL6R   REG8(IT83XX_SMFI_BASE+0xA2)
+#define IT83XX_SMFI_ECINDDR REG8(IT83XX_SMFI_BASE + 0x3F)
+#define IT83XX_SMFI_SCAR0L REG8(IT83XX_SMFI_BASE + 0x40)
+#define IT83XX_SMFI_SCAR0M REG8(IT83XX_SMFI_BASE + 0x41)
+#define IT83XX_SMFI_SCAR0H REG8(IT83XX_SMFI_BASE + 0x42)
+#define IT83XX_SMFI_SCAR2L REG8(IT83XX_SMFI_BASE + 0x46)
+#define IT83XX_SMFI_SCAR2M REG8(IT83XX_SMFI_BASE + 0x47)
+#define IT83XX_SMFI_SCAR2H REG8(IT83XX_SMFI_BASE + 0x48)
+#define IT83XX_SMFI_FLHCTRL3R REG8(IT83XX_SMFI_BASE + 0x63)
+#define IT83XX_SMFI_STCDMACR REG8(IT83XX_SMFI_BASE + 0x80)
+#define IT83XX_SMFI_FLHCTRL6R REG8(IT83XX_SMFI_BASE + 0xA2)
 /* Enable EC-indirect page program command */
 #define IT83XX_SMFI_MASK_ECINDPP BIT(3)
 
 /* Serial Peripheral Interface (SSPI) */
-#define IT83XX_SSPI_BASE  0x00F02600
+#define IT83XX_SSPI_BASE 0x00F02600
 
-#define IT83XX_SSPI_SPIDATA     REG8(IT83XX_SSPI_BASE+0x00)
-#define IT83XX_SSPI_SPICTRL1    REG8(IT83XX_SSPI_BASE+0x01)
-#define IT83XX_SSPI_SPICTRL2    REG8(IT83XX_SSPI_BASE+0x02)
-#define IT83XX_SSPI_SPISTS      REG8(IT83XX_SSPI_BASE+0x03)
-#define IT83XX_SSPI_SPICTRL3    REG8(IT83XX_SSPI_BASE+0x04)
+#define IT83XX_SSPI_SPIDATA REG8(IT83XX_SSPI_BASE + 0x00)
+#define IT83XX_SSPI_SPICTRL1 REG8(IT83XX_SSPI_BASE + 0x01)
+#define IT83XX_SSPI_SPICTRL2 REG8(IT83XX_SSPI_BASE + 0x02)
+#define IT83XX_SSPI_SPISTS REG8(IT83XX_SSPI_BASE + 0x03)
+#define IT83XX_SSPI_SPICTRL3 REG8(IT83XX_SSPI_BASE + 0x04)
 
 /* Serial Peripheral Interface (SPI) */
-#define IT83XX_SPI_BASE  0x00F03A00
-
-#define IT83XX_SPI_SPISGCR      REG8(IT83XX_SPI_BASE+0x00)
-#define IT83XX_SPI_SPISCEN         BIT(0)
-#define IT83XX_SPI_TXRXFAR      REG8(IT83XX_SPI_BASE+0x01)
-#define IT83XX_SPI_CPURXF2A        BIT(4)
-#define IT83XX_SPI_CPURXF1A        BIT(3)
-#define IT83XX_SPI_CPUTFA          BIT(1)
-#define IT83XX_SPI_TXFCR        REG8(IT83XX_SPI_BASE+0x02)
-#define IT83XX_SPI_TXFCMR          BIT(2)
-#define IT83XX_SPI_TXFR            BIT(1)
-#define IT83XX_SPI_TXFS            BIT(0)
-#define IT83XX_SPI_GCR2         REG8(IT83XX_SPI_BASE+0x03)
-#define IT83XX_SPI_RXF2OC          BIT(4)
-#define IT83XX_SPI_RXF1OC          BIT(3)
-#define IT83XX_SPI_RXFAR           BIT(0)
-#define IT83XX_SPI_IMR          REG8(IT83XX_SPI_BASE+0x04)
-#define IT83XX_SPI_RX_REACH        BIT(5)
-#define IT83XX_SPI_EDIM            BIT(2)
-#define IT83XX_SPI_ISR          REG8(IT83XX_SPI_BASE+0x05)
-#define IT83XX_SPI_ENDDETECTINT    BIT(2)
-#define IT83XX_SPI_RXFSR        REG8(IT83XX_SPI_BASE+0x07)
-#define IT83XX_SPI_RXFFSM          (BIT(4) | BIT(3))
-#define IT83XX_SPI_RXF2FS          BIT(2)
-#define IT83XX_SPI_RXF1FS          BIT(1)
+#define IT83XX_SPI_BASE 0x00F03A00
+
+#define IT83XX_SPI_SPISGCR REG8(IT83XX_SPI_BASE + 0x00)
+#define IT83XX_SPI_SPISCEN BIT(0)
+#define IT83XX_SPI_TXRXFAR REG8(IT83XX_SPI_BASE + 0x01)
+#define IT83XX_SPI_CPURXF2A BIT(4)
+#define IT83XX_SPI_CPURXF1A BIT(3)
+#define IT83XX_SPI_CPUTFA BIT(1)
+#define IT83XX_SPI_TXFCR REG8(IT83XX_SPI_BASE + 0x02)
+#define IT83XX_SPI_TXFCMR BIT(2)
+#define IT83XX_SPI_TXFR BIT(1)
+#define IT83XX_SPI_TXFS BIT(0)
+#define IT83XX_SPI_GCR2 REG8(IT83XX_SPI_BASE + 0x03)
+#define IT83XX_SPI_RXF2OC BIT(4)
+#define IT83XX_SPI_RXF1OC BIT(3)
+#define IT83XX_SPI_RXFAR BIT(0)
+#define IT83XX_SPI_IMR REG8(IT83XX_SPI_BASE + 0x04)
+#define IT83XX_SPI_RX_FIFO_FULL BIT(7)
+#define IT83XX_SPI_RX_REACH BIT(5)
+#define IT83XX_SPI_EDIM BIT(2)
+#define IT83XX_SPI_ISR REG8(IT83XX_SPI_BASE + 0x05)
+#define IT83XX_SPI_TXFSR REG8(IT83XX_SPI_BASE + 0x06)
+#define IT83XX_SPI_ENDDETECTINT BIT(2)
+#define IT83XX_SPI_RXFSR REG8(IT83XX_SPI_BASE + 0x07)
+#define IT83XX_SPI_RXFFSM (BIT(4) | BIT(3))
+#define IT83XX_SPI_RXF2FS BIT(2)
+#define IT83XX_SPI_RXF1FS BIT(1)
 #ifdef CHIP_VARIANT_IT83202BX
-#define IT83XX_SPI_SPISRDR      REG8(IT83XX_SPI_BASE+0x08)
+#define IT83XX_SPI_SPISRDR REG8(IT83XX_SPI_BASE + 0x08)
 #else
-#define IT83XX_SPI_SPISRDR      REG8(IT83XX_SPI_BASE+0x0b)
+#define IT83XX_SPI_SPISRDR REG8(IT83XX_SPI_BASE + 0x0b)
 #endif
-#define IT83XX_SPI_CPUWTFDB0    REG32(IT83XX_SPI_BASE+0x08)
-#define IT83XX_SPI_FCR          REG8(IT83XX_SPI_BASE+0x09)
-#define IT83XX_SPI_SPISRTXF        BIT(2)
-#define IT83XX_SPI_RXFR            BIT(1)
-#define IT83XX_SPI_RXFCMR          BIT(0)
-#define IT83XX_SPI_RXFRDRB0     REG32(IT83XX_SPI_BASE+0x0C)
-#define IT83XX_SPI_FTCB0R       REG8(IT83XX_SPI_BASE+0x18)
-#define IT83XX_SPI_FTCB1R       REG8(IT83XX_SPI_BASE+0x19)
-#define IT83XX_SPI_TCCB0        REG8(IT83XX_SPI_BASE+0x1A)
-#define IT83XX_SPI_TCCB1        REG8(IT83XX_SPI_BASE+0x1B)
-#define IT83XX_SPI_HPR2         REG8(IT83XX_SPI_BASE+0x1E)
-#define IT83XX_SPI_RX_VLISMR    REG8(IT83XX_SPI_BASE+0x26)
-#define IT83XX_SPI_RVLIM           BIT(0)
-#define IT83XX_SPI_RX_VLISR     REG8(IT83XX_SPI_BASE+0x27)
-#define IT83XX_SPI_RVLI            BIT(0)
+#define IT83XX_SPI_CPUWTFDB0 REG32(IT83XX_SPI_BASE + 0x08)
+#define IT83XX_SPI_FCR REG8(IT83XX_SPI_BASE + 0x09)
+#define IT83XX_SPI_SPISRTXF BIT(2)
+#define IT83XX_SPI_RXFR BIT(1)
+#define IT83XX_SPI_RXFCMR BIT(0)
+#define IT83XX_SPI_RXFRDRB0 REG32(IT83XX_SPI_BASE + 0x0C)
+#define IT83XX_SPI_FTCB0R REG8(IT83XX_SPI_BASE + 0x18)
+#define IT83XX_SPI_FTCB1R REG8(IT83XX_SPI_BASE + 0x19)
+#define IT83XX_SPI_TCCB0 REG8(IT83XX_SPI_BASE + 0x1A)
+#define IT83XX_SPI_TCCB1 REG8(IT83XX_SPI_BASE + 0x1B)
+#define IT83XX_SPI_HPR2 REG8(IT83XX_SPI_BASE + 0x1E)
+#define IT83XX_SPI_EMMCBMR REG8(IT83XX_SPI_BASE + 0x21)
+#define IT83XX_SPI_EMMCABM BIT(1) /* eMMC Alternative Boot Mode */
+#define IT83XX_SPI_RX_VLISMR REG8(IT83XX_SPI_BASE + 0x26)
+#define IT83XX_SPI_RVLIM BIT(0)
+#define IT83XX_SPI_RX_VLISR REG8(IT83XX_SPI_BASE + 0x27)
+#define IT83XX_SPI_RVLI BIT(0)
 
 /* Platform Environment Control Interface (PECI) */
-#define IT83XX_PECI_BASE  0x00F02C00
-
-#define IT83XX_PECI_HOSTAR      REG8(IT83XX_PECI_BASE+0x00)
-#define IT83XX_PECI_HOCTLR      REG8(IT83XX_PECI_BASE+0x01)
-#define IT83XX_PECI_HOCMDR      REG8(IT83XX_PECI_BASE+0x02)
-#define IT83XX_PECI_HOTRADDR    REG8(IT83XX_PECI_BASE+0x03)
-#define IT83XX_PECI_HOWRLR      REG8(IT83XX_PECI_BASE+0x04)
-#define IT83XX_PECI_HORDLR      REG8(IT83XX_PECI_BASE+0x05)
-#define IT83XX_PECI_HOWRDR      REG8(IT83XX_PECI_BASE+0x06)
-#define IT83XX_PECI_HORDDR      REG8(IT83XX_PECI_BASE+0x07)
-#define IT83XX_PECI_HOCTL2R     REG8(IT83XX_PECI_BASE+0x08)
-#define IT83XX_PECI_RWFCSV      REG8(IT83XX_PECI_BASE+0x09)
-#define IT83XX_PECI_RRFCSV      REG8(IT83XX_PECI_BASE+0x0A)
-#define IT83XX_PECI_WFCSV       REG8(IT83XX_PECI_BASE+0x0B)
-#define IT83XX_PECI_RFCSV       REG8(IT83XX_PECI_BASE+0x0C)
-#define IT83XX_PECI_AWFCSV      REG8(IT83XX_PECI_BASE+0x0D)
-#define IT83XX_PECI_PADCTLR     REG8(IT83XX_PECI_BASE+0x0E)
+#define IT83XX_PECI_BASE 0x00F02C00
+
+#define IT83XX_PECI_HOSTAR REG8(IT83XX_PECI_BASE + 0x00)
+#define IT83XX_PECI_HOCTLR REG8(IT83XX_PECI_BASE + 0x01)
+#define IT83XX_PECI_HOCMDR REG8(IT83XX_PECI_BASE + 0x02)
+#define IT83XX_PECI_HOTRADDR REG8(IT83XX_PECI_BASE + 0x03)
+#define IT83XX_PECI_HOWRLR REG8(IT83XX_PECI_BASE + 0x04)
+#define IT83XX_PECI_HORDLR REG8(IT83XX_PECI_BASE + 0x05)
+#define IT83XX_PECI_HOWRDR REG8(IT83XX_PECI_BASE + 0x06)
+#define IT83XX_PECI_HORDDR REG8(IT83XX_PECI_BASE + 0x07)
+#define IT83XX_PECI_HOCTL2R REG8(IT83XX_PECI_BASE + 0x08)
+#define IT83XX_PECI_RWFCSV REG8(IT83XX_PECI_BASE + 0x09)
+#define IT83XX_PECI_RRFCSV REG8(IT83XX_PECI_BASE + 0x0A)
+#define IT83XX_PECI_WFCSV REG8(IT83XX_PECI_BASE + 0x0B)
+#define IT83XX_PECI_RFCSV REG8(IT83XX_PECI_BASE + 0x0C)
+#define IT83XX_PECI_AWFCSV REG8(IT83XX_PECI_BASE + 0x0D)
+#define IT83XX_PECI_PADCTLR REG8(IT83XX_PECI_BASE + 0x0E)
 
 /*
  * The count number of the counter for 25 ms register.
  * The 25 ms register is calculated by (count number *1.024 kHz).
  */
-#define I2C_CLK_LOW_TIMEOUT  255 /* ~=249 ms */
+#define I2C_CLK_LOW_TIMEOUT 255 /* ~=249 ms */
 
 /* SMBus/I2C Interface (SMB/I2C) */
-#define IT83XX_SMB_BASE   0x00F01C00
-
-#define IT83XX_SMB_4P7USL       REG8(IT83XX_SMB_BASE+0x00)
-#define IT83XX_SMB_4P0USL       REG8(IT83XX_SMB_BASE+0x01)
-#define IT83XX_SMB_300NS        REG8(IT83XX_SMB_BASE+0x02)
-#define IT83XX_SMB_250NS        REG8(IT83XX_SMB_BASE+0x03)
-#define IT83XX_SMB_25MS         REG8(IT83XX_SMB_BASE+0x04)
-#define IT83XX_SMB_45P3USL      REG8(IT83XX_SMB_BASE+0x05)
-#define IT83XX_SMB_45P3USH      REG8(IT83XX_SMB_BASE+0x06)
-#define IT83XX_SMB_4P7A4P0H     REG8(IT83XX_SMB_BASE+0x07)
-#define IT83XX_SMB_SLVISELR     REG8(IT83XX_SMB_BASE+0x08)
-#define IT83XX_SMB_SCLKTS(ch)   REG8(IT83XX_SMB_BASE+0x09+ch)
-#define IT83XX_SMB_CHSEF        REG8(IT83XX_SMB_BASE+0x11)
-#define IT83XX_SMB_CHSAB        REG8(IT83XX_SMB_BASE+0x20)
-#define IT83XX_SMB_CHSCD        REG8(IT83XX_SMB_BASE+0x21)
-#define IT83XX_SMB_HOSTA(ch)    REG8(IT83XX_SMB_BASE+0x40+(ch << 6))
-#define IT83XX_SMB_HOCTL(ch)    REG8(IT83XX_SMB_BASE+0x41+(ch << 6))
-#define IT83XX_SMB_HOCMD(ch)    REG8(IT83XX_SMB_BASE+0x42+(ch << 6))
-#define IT83XX_SMB_TRASLA(ch)   REG8(IT83XX_SMB_BASE+0x43+(ch << 6))
-#define IT83XX_SMB_D0REG(ch)    REG8(IT83XX_SMB_BASE+0x44+(ch << 6))
-#define IT83XX_SMB_D1REG(ch)    REG8(IT83XX_SMB_BASE+0x45+(ch << 6))
-#define IT83XX_SMB_HOBDB(ch)    REG8(IT83XX_SMB_BASE+0x46+(ch << 6))
-#define IT83XX_SMB_PECERC(ch)   REG8(IT83XX_SMB_BASE+0x47+(ch << 6))
-#define IT83XX_SMB_SMBPCTL(ch)  REG8(IT83XX_SMB_BASE+0x4A+(ch << 6))
-#define IT83XX_SMB_HOCTL2(ch)   REG8(IT83XX_SMB_BASE+0x50+(ch << 6))
-#define IT83XX_SMB_SLVEN        (1 << 5)
-#define IT83XX_SMB_RESLADR      REG8(IT83XX_SMB_BASE+0x48)
-#define IT83XX_SMB_SLDA         REG8(IT83XX_SMB_BASE+0x49)
-#define IT83XX_SMB_SLSTA        REG8(IT83XX_SMB_BASE+0x4B)
-#define IT83XX_SMB_SPDS         (1 << 5)
-#define IT83XX_SMB_RCS          (1 << 3)
-#define IT83XX_SMB_STS          (1 << 2)
-#define IT83XX_SMB_SDS          (1 << 1)
-#define IT83XX_SMB_SICR         REG8(IT83XX_SMB_BASE+0x4C)
-#define IT83XX_SMB_RESLADR2     REG8(IT83XX_SMB_BASE+0x51)
-#define IT83XX_SMB_ENADDR2      (1 << 7)
-#define IT83XX_SMB_SFFCTL       REG8(IT83XX_SMB_BASE+0x55)
-#define IT83XX_SMB_SAFE         (1 << 0)
-#define IT83XX_SMB_SFFSTA       REG8(IT83XX_SMB_BASE+0x56)
-#define IT83XX_SMB_SFFFULL      (1 << 6)
+#define IT83XX_SMB_BASE 0x00F01C00
+
+#define IT83XX_SMB_4P7USL REG8(IT83XX_SMB_BASE + 0x00)
+#define IT83XX_SMB_4P0USL REG8(IT83XX_SMB_BASE + 0x01)
+#define IT83XX_SMB_300NS REG8(IT83XX_SMB_BASE + 0x02)
+#define IT83XX_SMB_250NS REG8(IT83XX_SMB_BASE + 0x03)
+#define IT83XX_SMB_25MS REG8(IT83XX_SMB_BASE + 0x04)
+#define IT83XX_SMB_45P3USL REG8(IT83XX_SMB_BASE + 0x05)
+#define IT83XX_SMB_45P3USH REG8(IT83XX_SMB_BASE + 0x06)
+#define IT83XX_SMB_4P7A4P0H REG8(IT83XX_SMB_BASE + 0x07)
+#define IT83XX_SMB_SLVISELR REG8(IT83XX_SMB_BASE + 0x08)
+#define IT83XX_SMB_SCLKTS(ch) REG8(IT83XX_SMB_BASE + 0x09 + ch)
+#define IT83XX_SMB_CHSEF REG8(IT83XX_SMB_BASE + 0x11)
+#define IT83XX_SMB_CHSAB REG8(IT83XX_SMB_BASE + 0x20)
+#define IT83XX_SMB_CHSCD REG8(IT83XX_SMB_BASE + 0x21)
+#define IT83XX_SMB_HOSTA(ch) REG8(IT83XX_SMB_BASE + 0x40 + (ch << 6))
+#define IT83XX_SMB_HOCTL(ch) REG8(IT83XX_SMB_BASE + 0x41 + (ch << 6))
+#define IT83XX_SMB_HOCMD(ch) REG8(IT83XX_SMB_BASE + 0x42 + (ch << 6))
+#define IT83XX_SMB_TRASLA(ch) REG8(IT83XX_SMB_BASE + 0x43 + (ch << 6))
+#define IT83XX_SMB_D0REG(ch) REG8(IT83XX_SMB_BASE + 0x44 + (ch << 6))
+#define IT83XX_SMB_D1REG(ch) REG8(IT83XX_SMB_BASE + 0x45 + (ch << 6))
+#define IT83XX_SMB_HOBDB(ch) REG8(IT83XX_SMB_BASE + 0x46 + (ch << 6))
+#define IT83XX_SMB_PECERC(ch) REG8(IT83XX_SMB_BASE + 0x47 + (ch << 6))
+#define IT83XX_SMB_SMBPCTL(ch) REG8(IT83XX_SMB_BASE + 0x4A + (ch << 6))
+#define IT83XX_SMB_HOCTL2(ch) REG8(IT83XX_SMB_BASE + 0x50 + (ch << 6))
+#define IT83XX_SMB_SLVEN (1 << 5)
+#define IT83XX_SMB_RESLADR REG8(IT83XX_SMB_BASE + 0x48)
+#define IT83XX_SMB_SLDA REG8(IT83XX_SMB_BASE + 0x49)
+#define IT83XX_SMB_SLSTA REG8(IT83XX_SMB_BASE + 0x4B)
+#define IT83XX_SMB_SPDS (1 << 5)
+#define IT83XX_SMB_RCS (1 << 3)
+#define IT83XX_SMB_STS (1 << 2)
+#define IT83XX_SMB_SDS (1 << 1)
+#define IT83XX_SMB_SICR REG8(IT83XX_SMB_BASE + 0x4C)
+#define IT83XX_SMB_RESLADR2 REG8(IT83XX_SMB_BASE + 0x51)
+#define IT83XX_SMB_ENADDR2 (1 << 7)
+#define IT83XX_SMB_SFFCTL REG8(IT83XX_SMB_BASE + 0x55)
+#define IT83XX_SMB_HSAPE BIT(1)
+#define IT83XX_SMB_SAFE (1 << 0)
+#define IT83XX_SMB_SFFSTA REG8(IT83XX_SMB_BASE + 0x56)
+#define IT83XX_SMB_SFFFULL (1 << 6)
 
 /* BRAM */
-#define IT83XX_BRAM_BASE  0x00F02200
+#define IT83XX_BRAM_BASE 0x00F02200
 
 /* offset 0 ~ 0x7f */
-#define IT83XX_BRAM_BANK0(i)    REG8(IT83XX_BRAM_BASE + i)
+#define IT83XX_BRAM_BANK0(i) REG8(IT83XX_BRAM_BASE + i)
 /* Battery backed RAM indices. */
 enum bram_indices {
 	/* reset flags uses 4 bytes */
@@ -1417,187 +1438,232 @@ enum bram_indices {
 	BRAM_IDX_RESET_FLAGS3 = 3,
 
 	/* PD state data for CONFIG_USB_PD_DUAL_ROLE uses 1 byte per port */
-	BRAM_IDX_PD0 =           4,
-	BRAM_IDX_PD1 =           5,
-	BRAM_IDX_PD2 =           6,
+	BRAM_IDX_PD0 = 4,
+	BRAM_IDX_PD1 = 5,
+	BRAM_IDX_PD2 = 6,
 
 	/* index 7 is reserved */
 
-	BRAM_IDX_SCRATCHPAD0  = 8,
-	BRAM_IDX_SCRATCHPAD1  = 9,
-	BRAM_IDX_SCRATCHPAD2  = 0xa,
-	BRAM_IDX_SCRATCHPAD3  = 0xb,
-	/* index 0xc ~ 0xf are reserved */
+	BRAM_IDX_SCRATCHPAD0 = 8,
+	BRAM_IDX_SCRATCHPAD1 = 9,
+	BRAM_IDX_SCRATCHPAD2 = 0xa,
+	BRAM_IDX_SCRATCHPAD3 = 0xb,
 
-	/* NVCONTEXT uses 16 bytes */
-	BRAM_IDX_NVCONTEXT     = 0x10,
-	BRAM_IDX_NVCONTEXT_END = 0x1F,
+	/* EC logs status */
+	BRAM_IDX_EC_LOG_STATUS = 0xc,
 
-	/* offset 0x20 ~ 0x7b are reserved for future use. */
+/* offset 0x0d ~ 0x1f are reserved for future use. */
+#if defined(CONFIG_HOST_INTERFACE_LPC) || defined(CONFIG_HOST_INTERFACE_ESPI)
+	/*
+	 * offset 0x20 ~ 0x7b are reserved for future use.
+	 * (apply to x86 platform)
+	 */
 
 	/* This field is used to indicate BRAM is valid or not. */
-	BRAM_IDX_VALID_FLAGS0  = 0x7c,
-	BRAM_IDX_VALID_FLAGS1  = 0x7d,
-	BRAM_IDX_VALID_FLAGS2  = 0x7e,
-	BRAM_IDX_VALID_FLAGS3  = 0x7f
-	/* offset 0x7f is the end of BRAM bank 0. */
+	BRAM_IDX_VALID_FLAGS0 = 0x7c,
+	BRAM_IDX_VALID_FLAGS1 = 0x7d,
+	BRAM_IDX_VALID_FLAGS2 = 0x7e,
+	BRAM_IDX_VALID_FLAGS3 = 0x7f
+/* offset 0x7f is the end of BRAM bank 0. */
+#else
+
+	/* panic data uses 144 bytes (offset 0x20 ~ 0xaf) */
+	BRAM_PANIC_DATA_START = 0x20,
+	BRAM_PANIC_DATA_END = 0xaf,
+
+	/* This field is used to indicate BRAM is valid or not. */
+	BRAM_IDX_VALID_FLAGS0 = 0xbc,
+	BRAM_IDX_VALID_FLAGS1 = 0xbd,
+	BRAM_IDX_VALID_FLAGS2 = 0xbe,
+	BRAM_IDX_VALID_FLAGS3 = 0xbf
+/* offset 0xbf is the end of BRAM bank 1. */
+#endif
 };
-#define BRAM_RESET_FLAGS0       IT83XX_BRAM_BANK0(BRAM_IDX_RESET_FLAGS0)
-#define BRAM_RESET_FLAGS1       IT83XX_BRAM_BANK0(BRAM_IDX_RESET_FLAGS1)
-#define BRAM_RESET_FLAGS2       IT83XX_BRAM_BANK0(BRAM_IDX_RESET_FLAGS2)
-#define BRAM_RESET_FLAGS3       IT83XX_BRAM_BANK0(BRAM_IDX_RESET_FLAGS3)
+#define BRAM_RESET_FLAGS0 IT83XX_BRAM_BANK0(BRAM_IDX_RESET_FLAGS0)
+#define BRAM_RESET_FLAGS1 IT83XX_BRAM_BANK0(BRAM_IDX_RESET_FLAGS1)
+#define BRAM_RESET_FLAGS2 IT83XX_BRAM_BANK0(BRAM_IDX_RESET_FLAGS2)
+#define BRAM_RESET_FLAGS3 IT83XX_BRAM_BANK0(BRAM_IDX_RESET_FLAGS3)
 
-#define BRAM_SCRATCHPAD0        IT83XX_BRAM_BANK0(BRAM_IDX_SCRATCHPAD0)
-#define BRAM_SCRATCHPAD1        IT83XX_BRAM_BANK0(BRAM_IDX_SCRATCHPAD1)
-#define BRAM_SCRATCHPAD2        IT83XX_BRAM_BANK0(BRAM_IDX_SCRATCHPAD2)
-#define BRAM_SCRATCHPAD3        IT83XX_BRAM_BANK0(BRAM_IDX_SCRATCHPAD3)
+#define BRAM_SCRATCHPAD0 IT83XX_BRAM_BANK0(BRAM_IDX_SCRATCHPAD0)
+#define BRAM_SCRATCHPAD1 IT83XX_BRAM_BANK0(BRAM_IDX_SCRATCHPAD1)
+#define BRAM_SCRATCHPAD2 IT83XX_BRAM_BANK0(BRAM_IDX_SCRATCHPAD2)
+#define BRAM_SCRATCHPAD3 IT83XX_BRAM_BANK0(BRAM_IDX_SCRATCHPAD3)
 
-#define BRAM_VALID_FLAGS0       IT83XX_BRAM_BANK0(BRAM_IDX_VALID_FLAGS0)
-#define BRAM_VALID_FLAGS1       IT83XX_BRAM_BANK0(BRAM_IDX_VALID_FLAGS1)
-#define BRAM_VALID_FLAGS2       IT83XX_BRAM_BANK0(BRAM_IDX_VALID_FLAGS2)
-#define BRAM_VALID_FLAGS3       IT83XX_BRAM_BANK0(BRAM_IDX_VALID_FLAGS3)
+#define BRAM_EC_LOG_STATUS IT83XX_BRAM_BANK0(BRAM_IDX_EC_LOG_STATUS)
+enum bram_ec_logs_status { EC_LOG_SAVED_IN_FLASH = 1, EC_LOG_SAVED_IN_MEMORY };
 
-#define IT83XX_BRAM_BANK1(i)    REG8(IT83XX_BRAM_BASE + 0x80 + i)
+#define BRAM_VALID_FLAGS0 IT83XX_BRAM_BANK0(BRAM_IDX_VALID_FLAGS0)
+#define BRAM_VALID_FLAGS1 IT83XX_BRAM_BANK0(BRAM_IDX_VALID_FLAGS1)
+#define BRAM_VALID_FLAGS2 IT83XX_BRAM_BANK0(BRAM_IDX_VALID_FLAGS2)
+#define BRAM_VALID_FLAGS3 IT83XX_BRAM_BANK0(BRAM_IDX_VALID_FLAGS3)
+
+/*
+ * These 128 bytes are use to latch port 80h data on x86 platform.
+ * And they will be used to save panic data if the GPG1 reset mechanism
+ * is enabled.
+ */
+#if defined(CONFIG_HOST_INTERFACE_LPC) || defined(CONFIG_HOST_INTERFACE_ESPI)
+/* offset 0x80 ~ 0xbf */
+#define IT83XX_BRAM_BANK1(i) REG8(IT83XX_BRAM_BASE + 0x80 + i)
+#else
+/* Length of bram panic data */
+#define BRAM_PANIC_LEN (BRAM_PANIC_DATA_END - BRAM_PANIC_DATA_START + 1)
+#endif
 
 /*
  * Enhanced SMBus/I2C Interface
  * Ch_D: 0x00F03680 , Ch_E: 0x00F03500 , Ch_F: 0x00F03580
  * Ch_D: ch = 0x03  , Ch_E: ch = 0x00  , Ch_F: ch = 0x01
  */
-#define IT83XX_I2C_BASE   0x00F03500
-
-#define IT83XX_I2C_DRR(ch)           REG8(IT83XX_I2C_BASE+0x00+(ch << 7))
-#define IT83XX_I2C_PSR(ch)           REG8(IT83XX_I2C_BASE+0x01+(ch << 7))
-#define IT83XX_I2C_HSPR(ch)          REG8(IT83XX_I2C_BASE+0x02+(ch << 7))
-#define IT83XX_I2C_STR(ch)           REG8(IT83XX_I2C_BASE+0x03+(ch << 7))
-#define IT83XX_I2C_BB                (1 << 5)
-#define IT83XX_I2C_TIME_OUT          (1 << 3)
-#define IT83XX_I2C_RW                (1 << 2)
-#define IT83XX_I2C_INTPEND           (1 << 1)
-#define IT83XX_I2C_DHTR(ch)          REG8(IT83XX_I2C_BASE+0x04+(ch << 7))
-#define IT83XX_I2C_TOR(ch)           REG8(IT83XX_I2C_BASE+0x05+(ch << 7))
-#define IT83XX_I2C_DTR(ch)           REG8(IT83XX_I2C_BASE+0x08+(ch << 7))
-#define IT83XX_I2C_CTR(ch)           REG8(IT83XX_I2C_BASE+0x09+(ch << 7))
-#define IT83XX_I2C_INTEN             (1 << 6)
-#define IT83XX_I2C_MODE              (1 << 5)
-#define IT83XX_I2C_STARST            (1 << 4)
-#define IT83XX_I2C_ACK               (1 << 3)
-#define IT83XX_I2C_HALT              (1 << 0)
-#define IT83XX_I2C_CTR1(ch)          REG8(IT83XX_I2C_BASE+0x0A+(ch << 7))
-#define IT83XX_I2C_COMQ_EN           (1 << 7)
-#define IT83XX_I2C_MDL_EN            (1 << 1)
-#define IT83XX_I2C_BYTE_CNT_L(ch)    REG8(IT83XX_I2C_BASE+0x0C+(ch << 7))
-#define IT83XX_I2C_IRQ_ST(ch)        REG8(IT83XX_I2C_BASE+0x0D+(ch << 7))
-#define IT83XX_I2C_IDW_CLR           (1 << 3)
-#define IT83XX_I2C_IDR_CLR           (1 << 2)
-#define IT83XX_I2C_SLVDATAFLG        (1 << 1)
-#define IT83XX_I2C_P_CLR             (1 << 0)
-#define IT83XX_I2C_IDR(ch)           REG8(IT83XX_I2C_BASE+0x06+(ch << 7))
-#define IT83XX_I2C_TOS(ch)           REG8(IT83XX_I2C_BASE+0x07+(ch << 7))
-#define IT83XX_I2C_CLK_STR           (1 << 7)
-#define IT83XX_I2C_IDR2(ch)          REG8(IT83XX_I2C_BASE+0x1F+(ch << 7))
-#define IT83XX_I2C_RAMHA(ch)         REG8(IT83XX_I2C_BASE+0x23+(ch << 7))
-#define IT83XX_I2C_RAMLA(ch)         REG8(IT83XX_I2C_BASE+0x24+(ch << 7))
-#define IT83XX_I2C_RAMHA2(ch)        REG8(IT83XX_I2C_BASE+0x2B+(ch << 7))
-#define IT83XX_I2C_RAMLA2(ch)        REG8(IT83XX_I2C_BASE+0x2C+(ch << 7))
-#define IT83XX_I2C_CMD_ADDH(ch)      REG8(IT83XX_I2C_BASE+0x25+(ch << 7))
-#define IT83XX_I2C_CMD_ADDL(ch)      REG8(IT83XX_I2C_BASE+0x26+(ch << 7))
-#define IT83XX_I2C_RAMH2A(ch)        REG8(IT83XX_I2C_BASE+0x50+(ch << 7))
-#define IT83XX_I2C_CMD_ADDH2(ch)     REG8(IT83XX_I2C_BASE+0x52+(ch << 7))
+#define IT83XX_I2C_BASE 0x00F03500
+
+#define IT83XX_I2C_DRR(ch) REG8(IT83XX_I2C_BASE + 0x00 + (ch << 7))
+#define IT83XX_I2C_PSR(ch) REG8(IT83XX_I2C_BASE + 0x01 + (ch << 7))
+#define IT83XX_I2C_HSPR(ch) REG8(IT83XX_I2C_BASE + 0x02 + (ch << 7))
+#define IT83XX_I2C_STR(ch) REG8(IT83XX_I2C_BASE + 0x03 + (ch << 7))
+#define IT83XX_I2C_BB (1 << 5)
+#define IT83XX_I2C_TIME_OUT (1 << 3)
+#define IT83XX_I2C_RW (1 << 2)
+#define IT83XX_I2C_INTPEND (1 << 1)
+#define IT83XX_I2C_DHTR(ch) REG8(IT83XX_I2C_BASE + 0x04 + (ch << 7))
+#define IT83XX_I2C_TOR(ch) REG8(IT83XX_I2C_BASE + 0x05 + (ch << 7))
+#define IT83XX_I2C_DTR(ch) REG8(IT83XX_I2C_BASE + 0x08 + (ch << 7))
+#define IT83XX_I2C_CTR(ch) REG8(IT83XX_I2C_BASE + 0x09 + (ch << 7))
+#define IT83XX_I2C_INTEN (1 << 6)
+#define IT83XX_I2C_MODE (1 << 5)
+#define IT83XX_I2C_STARST (1 << 4)
+#define IT83XX_I2C_ACK (1 << 3)
+#define IT83XX_I2C_HALT (1 << 0)
+#define IT83XX_I2C_CTR1(ch) REG8(IT83XX_I2C_BASE + 0x0A + (ch << 7))
+#define IT83XX_I2C_COMQ_EN (1 << 7)
+#define IT83XX_I2C_MDL_EN (1 << 1)
+#define IT83XX_I2C_BYTE_CNT_L(ch) REG8(IT83XX_I2C_BASE + 0x0C + (ch << 7))
+#define IT83XX_I2C_IRQ_ST(ch) REG8(IT83XX_I2C_BASE + 0x0D + (ch << 7))
+#define IT83XX_I2C_IDW_CLR (1 << 3)
+#define IT83XX_I2C_IDR_CLR (1 << 2)
+#define IT83XX_I2C_SLVDATAFLG (1 << 1)
+#define IT83XX_I2C_P_CLR (1 << 0)
+#define IT83XX_I2C_IDR(ch) REG8(IT83XX_I2C_BASE + 0x06 + (ch << 7))
+#define IT83XX_I2C_TOS(ch) REG8(IT83XX_I2C_BASE + 0x07 + (ch << 7))
+#define IT83XX_I2C_CLK_STR (1 << 7)
+#define IT83XX_I2C_STR2(ch) REG8(IT83XX_I2C_BASE + 0x12 + (ch << 7))
+#define IT83XX_I2C_NST(ch) REG8(IT83XX_I2C_BASE + 0x13 + (ch << 7))
+#define IT83XX_I2C_NST_CNS BIT(7)
+#define IT83XX_I2C_NST_ID_NACK BIT(3)
+#define IT83XX_I2C_TO_ARB_ST(ch) REG8(IT83XX_I2C_BASE + 0x18 + (ch << 7))
+#define IT83XX_I2C_ERR_ST(ch) REG8(IT83XX_I2C_BASE + 0x19 + (ch << 7))
+#define IT83XX_I2C_ERR_ST_DEV1_EIRQ BIT(0)
+#define IT83XX_I2C_FST(ch) REG8(IT83XX_I2C_BASE + 0x1b + (ch << 7))
+#define IT83XX_I2C_FST_DEV1_IRQ BIT(4)
+#define IT83XX_I2C_EM(ch) REG8(IT83XX_I2C_BASE + 0x1c + (ch << 7))
+#define IT83XX_I2C_EM_DEV1_IRQ BIT(4)
+#define IT83XX_I2C_MODE_SEL(ch) REG8(IT83XX_I2C_BASE + 0x1d + (ch << 7))
+#define IT83XX_I2C_IDR2(ch) REG8(IT83XX_I2C_BASE + 0x1F + (ch << 7))
+#define IT83XX_I2C_CTR2(ch) REG8(IT83XX_I2C_BASE + 0x20 + (ch << 7))
+#define IT83XX_I2C_RAMHA(ch) REG8(IT83XX_I2C_BASE + 0x23 + (ch << 7))
+#define IT83XX_I2C_RAMLA(ch) REG8(IT83XX_I2C_BASE + 0x24 + (ch << 7))
+#define IT83XX_I2C_RAMHA2(ch) REG8(IT83XX_I2C_BASE + 0x2B + (ch << 7))
+#define IT83XX_I2C_RAMLA2(ch) REG8(IT83XX_I2C_BASE + 0x2C + (ch << 7))
+#define IT83XX_I2C_CMD_ADDH(ch) REG8(IT83XX_I2C_BASE + 0x25 + (ch << 7))
+#define IT83XX_I2C_CMD_ADDL(ch) REG8(IT83XX_I2C_BASE + 0x26 + (ch << 7))
+#define IT83XX_I2C_RAMH2A(ch) REG8(IT83XX_I2C_BASE + 0x50 + (ch << 7))
+#define IT83XX_I2C_CMD_ADDH2(ch) REG8(IT83XX_I2C_BASE + 0x52 + (ch << 7))
 
 enum i2c_channels {
-	IT83XX_I2C_CH_A,  /* GPIO.B3/B4 */
-	IT83XX_I2C_CH_B,  /* GPIO.C1/C2 */
-	IT83XX_I2C_CH_C,  /* GPIO.F6/F7 or GPIO.C7/F7 */
-	IT83XX_I2C_CH_D,  /* GPIO.H1/H2 */
-	IT83XX_I2C_CH_E,  /* GPIO.E0/E7 */
-	IT83XX_I2C_CH_F,  /* GPIO.A4/A5 (for util/iteflash) */
+	IT83XX_I2C_CH_A, /* GPIO.B3/B4 */
+	IT83XX_I2C_CH_B, /* GPIO.C1/C2 */
+	IT83XX_I2C_CH_C, /* GPIO.F6/F7 or GPIO.C7/F7 */
+	IT83XX_I2C_CH_D, /* GPIO.H1/H2 */
+	IT83XX_I2C_CH_E, /* GPIO.E0/E7 */
+	IT83XX_I2C_CH_F, /* GPIO.A4/A5 (for util/iteflash) */
 	IT83XX_I2C_PORT_COUNT,
 };
 
 #define USB_VID_ITE 0x048d
 
-#define IT83XX_ESPI_BASE  0x00F03100
+#define IT83XX_ESPI_BASE 0x00F03100
 
-#define IT83XX_ESPI_GCAC1      REG8(IT83XX_ESPI_BASE+0x05)
-#define IT83XX_ESPI_ESPCTRL0   REG8(IT83XX_ESPI_BASE+0x90)
-#define IT83XX_ESPI_ESGCTRL0   REG8(IT83XX_ESPI_BASE+0xA0)
-#define IT83XX_ESPI_ESGCTRL1   REG8(IT83XX_ESPI_BASE+0xA1)
-#define IT83XX_ESPI_ESGCTRL2   REG8(IT83XX_ESPI_BASE+0xA2)
+#define IT83XX_ESPI_GCAC1 REG8(IT83XX_ESPI_BASE + 0x05)
+#define IT83XX_ESPI_ESPCTRL0 REG8(IT83XX_ESPI_BASE + 0x90)
+#define IT83XX_ESPI_ESGCTRL0 REG8(IT83XX_ESPI_BASE + 0xA0)
+#define IT83XX_ESPI_ESGCTRL1 REG8(IT83XX_ESPI_BASE + 0xA1)
+#define IT83XX_ESPI_ESGCTRL2 REG8(IT83XX_ESPI_BASE + 0xA2)
 
 /* eSPI VW */
-#define IT83XX_ESPI_VW_BASE  0x00F03200
-#define IT83XX_ESPI_VWIDX(i)   REG8(IT83XX_ESPI_VW_BASE+(i))
+#define IT83XX_ESPI_VW_BASE 0x00F03200
+#define IT83XX_ESPI_VWIDX(i) REG8(IT83XX_ESPI_VW_BASE + (i))
 
-#define VW_LEVEL_FIELD(f)          ((f) << 0)
-#define VW_VALID_FIELD(f)          ((f) << 4)
+#define VW_LEVEL_FIELD(f) ((f) << 0)
+#define VW_VALID_FIELD(f) ((f) << 4)
 
 #define ESPI_SYSTEM_EVENT_VW_IDX_2 0x2
-#define VW_IDX_2_SLP_S3            BIT(0)
-#define VW_IDX_2_SLP_S4            BIT(1)
-#define VW_IDX_2_SLP_S5            BIT(2)
+#define VW_IDX_2_SLP_S3 BIT(0)
+#define VW_IDX_2_SLP_S4 BIT(1)
+#define VW_IDX_2_SLP_S5 BIT(2)
 
 #define ESPI_SYSTEM_EVENT_VW_IDX_3 0x3
-#define VW_IDX_3_SUS_STAT          BIT(0)
-#define VW_IDX_3_PLTRST            BIT(1)
-#define VW_IDX_3_OOB_RST_WARN      BIT(2)
+#define VW_IDX_3_SUS_STAT BIT(0)
+#define VW_IDX_3_PLTRST BIT(1)
+#define VW_IDX_3_OOB_RST_WARN BIT(2)
 
 #define ESPI_SYSTEM_EVENT_VW_IDX_4 0x4
-#define VW_IDX_4_OOB_RST_ACK       BIT(0)
-#define VW_IDX_4_WAKE              BIT(2)
-#define VW_IDX_4_PME               BIT(3)
+#define VW_IDX_4_OOB_RST_ACK BIT(0)
+#define VW_IDX_4_WAKE BIT(2)
+#define VW_IDX_4_PME BIT(3)
 
 #define ESPI_SYSTEM_EVENT_VW_IDX_5 0x5
-#define VW_IDX_5_SLAVE_BTLD_DONE   BIT(0)
-#define VW_IDX_5_FATAL             BIT(1)
-#define VW_IDX_5_NON_FATAL         BIT(2)
+#define VW_IDX_5_SLAVE_BTLD_DONE BIT(0)
+#define VW_IDX_5_FATAL BIT(1)
+#define VW_IDX_5_NON_FATAL BIT(2)
 #define VW_IDX_5_SLAVE_BTLD_STATUS BIT(3)
-#define VW_IDX_5_BTLD_STATUS_DONE  (VW_IDX_5_SLAVE_BTLD_DONE | \
-					VW_IDX_5_SLAVE_BTLD_STATUS)
+#define VW_IDX_5_BTLD_STATUS_DONE \
+	(VW_IDX_5_SLAVE_BTLD_DONE | VW_IDX_5_SLAVE_BTLD_STATUS)
 
 #define ESPI_SYSTEM_EVENT_VW_IDX_6 0x6
-#define VW_IDX_6_SCI               BIT(0)
-#define VW_IDX_6_SMI               BIT(1)
-#define VW_IDX_6_RCIN              BIT(2)
-#define VW_IDX_6_HOST_RST_ACK      BIT(3)
+#define VW_IDX_6_SCI BIT(0)
+#define VW_IDX_6_SMI BIT(1)
+#define VW_IDX_6_RCIN BIT(2)
+#define VW_IDX_6_HOST_RST_ACK BIT(3)
 
 #define ESPI_SYSTEM_EVENT_VW_IDX_7 0x7
-#define VW_IDX_7_HOST_RST_WARN     BIT(0)
+#define VW_IDX_7_HOST_RST_WARN BIT(0)
 
 #define ESPI_SYSTEM_EVENT_VW_IDX_40 0x40
-#define VW_IDX_40_SUS_ACK           BIT(0)
+#define VW_IDX_40_SUS_ACK BIT(0)
 
 #define ESPI_SYSTEM_EVENT_VW_IDX_41 0x41
-#define VW_IDX_41_SUS_WARN          BIT(0)
-#define VW_IDX_41_SUS_PWRDN_ACK     BIT(1)
-#define VW_IDX_41_SLP_A             BIT(3)
+#define VW_IDX_41_SUS_WARN BIT(0)
+#define VW_IDX_41_SUS_PWRDN_ACK BIT(1)
+#define VW_IDX_41_SLP_A BIT(3)
 
 #define ESPI_SYSTEM_EVENT_VW_IDX_42 0x42
-#define VW_IDX_42_SLP_LAN           BIT(0)
-#define VW_IDX_42_SLP_WLAN          BIT(1)
+#define VW_IDX_42_SLP_LAN BIT(0)
+#define VW_IDX_42_SLP_WLAN BIT(1)
 
 #define ESPI_SYSTEM_EVENT_VW_IDX_43 0x43
 #define ESPI_SYSTEM_EVENT_VW_IDX_44 0x44
 #define ESPI_SYSTEM_EVENT_VW_IDX_47 0x47
 
-#define IT83XX_ESPI_VWCTRL0    REG8(IT83XX_ESPI_VW_BASE+0x90)
+#define IT83XX_ESPI_VWCTRL0 REG8(IT83XX_ESPI_VW_BASE + 0x90)
 #define ESPI_INTERRUPT_EVENT_PUT_PC BIT(7)
 
-#define IT83XX_ESPI_VWCTRL1    REG8(IT83XX_ESPI_VW_BASE+0x91)
-#define IT83XX_ESPI_VWCTRL2    REG8(IT83XX_ESPI_VW_BASE+0x92)
-#define IT83XX_ESPI_VWCTRL3    REG8(IT83XX_ESPI_VW_BASE+0x93)
+#define IT83XX_ESPI_VWCTRL1 REG8(IT83XX_ESPI_VW_BASE + 0x91)
+#define IT83XX_ESPI_VWCTRL2 REG8(IT83XX_ESPI_VW_BASE + 0x92)
+#define IT83XX_ESPI_VWCTRL3 REG8(IT83XX_ESPI_VW_BASE + 0x93)
+/* 1b: Refers to espi_reset# for pltrst */
+#define ESPI_PLTRST_ESPI_RESET BIT(4)
 
 /* eSPI Queue 0 */
-#define IT83XX_ESPI_QUEUE_BASE  0x00F03300
+#define IT83XX_ESPI_QUEUE_BASE 0x00F03300
 /* PUT_PC data byte 0 - 63 */
-#define IT83XX_ESPI_QUEUE_PUT_PC(i)  REG8(IT83XX_ESPI_QUEUE_BASE+(i))
+#define IT83XX_ESPI_QUEUE_PUT_PC(i) REG8(IT83XX_ESPI_QUEUE_BASE + (i))
 /* PUT_OOB data byte 0 - 79 */
-#define IT83XX_ESPI_QUEUE_PUT_OOB(i) REG8(IT83XX_ESPI_QUEUE_BASE+0x80+(i))
+#define IT83XX_ESPI_QUEUE_PUT_OOB(i) REG8(IT83XX_ESPI_QUEUE_BASE + 0x80 + (i))
 
 /* USB Controller */
-#define IT83XX_USB_BASE   0x00F02F00
+#define IT83XX_USB_BASE 0x00F02F00
 
-#define IT83XX_USB_P0MCR  REG8(IT83XX_USB_BASE+0xE4)
+#define IT83XX_USB_P0MCR REG8(IT83XX_USB_BASE + 0xE4)
 #define USB_DP_DM_PULL_DOWN_EN BIT(4)
 
 /* Wake pin definitions, defined at board-level */
@@ -1611,11 +1677,11 @@ extern int hibernate_wake_pins_used;
 
 /* --- MISC (not implemented yet) --- */
 
-#define IT83XX_PS2_BASE   0x00F01700
+#define IT83XX_PS2_BASE 0x00F01700
 #define IT83XX_EGPIO_BASE 0x00F02100
-#define IT83XX_CIR_BASE   0x00F02300
-#define IT83XX_DBGR_BASE  0x00F02500
-#define IT83XX_OW_BASE    0x00F02A00
-#define IT83XX_CEC_BASE   0x00F02E00
+#define IT83XX_CIR_BASE 0x00F02300
+#define IT83XX_DBGR_BASE 0x00F02500
+#define IT83XX_OW_BASE 0x00F02A00
+#define IT83XX_CEC_BASE 0x00F02E00
 
 #endif /* __CROS_EC_REGISTERS_H */
diff --git a/chip/it83xx/spi.c b/chip/it83xx/spi.c
index 1fb77f9c3b..c172e9fca9 100644
--- a/chip/it83xx/spi.c
+++ b/chip/it83xx/spi.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -12,6 +12,7 @@
 #include "gpio.h"
 #include "hooks.h"
 #include "host_command.h"
+#include "intc.h"
 #include "registers.h"
 #include "spi.h"
 #include "system.h"
@@ -19,8 +20,8 @@
 #include "util.h"
 
 /* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SPI, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SPI, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SPI, format, ##args)
 
 #define SPI_RX_MAX_FIFO_SIZE 256
 #define SPI_TX_MAX_FIFO_SIZE 256
@@ -30,8 +31,8 @@
 
 /* Max data size for a version 3 request/response packet. */
 #define SPI_MAX_REQUEST_SIZE SPI_RX_MAX_FIFO_SIZE
-#define SPI_MAX_RESPONSE_SIZE (SPI_TX_MAX_FIFO_SIZE - \
-	EC_SPI_PREAMBLE_LENGTH - EC_SPI_PAST_END_LENGTH)
+#define SPI_MAX_RESPONSE_SIZE \
+	(SPI_TX_MAX_FIFO_SIZE - EC_SPI_PREAMBLE_LENGTH - EC_SPI_PAST_END_LENGTH)
 
 static const uint8_t out_preamble[EC_SPI_PREAMBLE_LENGTH] = {
 	EC_SPI_PROCESSING,
@@ -48,7 +49,7 @@ static uint8_t out_msg[SPI_TX_MAX_FIFO_SIZE] __aligned(4);
 /* Parameters used by host protocols */
 static struct host_packet spi_packet;
 
-enum spi_slave_state_machine {
+enum spi_peripheral_state_machine {
 	/* Ready to receive next request */
 	SPI_STATE_READY_TO_RECV,
 	/* Receiving request */
@@ -59,21 +60,21 @@ enum spi_slave_state_machine {
 	SPI_STATE_RX_BAD,
 
 	SPI_STATE_COUNT,
-} spi_slv_state;
+} spi_peripheral_state;
 
 static const int spi_response_state[] = {
-	[SPI_STATE_READY_TO_RECV] = EC_SPI_OLD_READY,
-	[SPI_STATE_RECEIVING]     = EC_SPI_RECEIVING,
-	[SPI_STATE_PROCESSING]    = EC_SPI_PROCESSING,
-	[SPI_STATE_RX_BAD]        = EC_SPI_RX_BAD_DATA,
+	[SPI_STATE_READY_TO_RECV] = EC_SPI_RX_READY,
+	[SPI_STATE_RECEIVING] = EC_SPI_RECEIVING,
+	[SPI_STATE_PROCESSING] = EC_SPI_PROCESSING,
+	[SPI_STATE_RX_BAD] = EC_SPI_RX_BAD_DATA,
 };
 BUILD_ASSERT(ARRAY_SIZE(spi_response_state) == SPI_STATE_COUNT);
 
 static void spi_set_state(int state)
 {
-	/* SPI slave state machine */
-	spi_slv_state = state;
-	/* Response spi slave state */
+	/* SPI peripheral state machine */
+	spi_peripheral_state = state;
+	/* Response spi peripheral state */
 	IT83XX_SPI_SPISRDR = spi_response_state[state];
 }
 
@@ -117,12 +118,12 @@ static void spi_response_host_data(uint8_t *out_msg_addr, int tx_size)
 
 	/*
 	 * After writing data to Tx FIFO is finished, this bit will
-	 * be to indicate the SPI slave controller.
+	 * be to indicate the SPI peripheral.
 	 */
 	IT83XX_SPI_TXFCR = IT83XX_SPI_TXFS;
 	/* End Tx FIFO access */
 	IT83XX_SPI_TXRXFAR = 0;
-	/* SPI slave read Tx FIFO */
+	/* SPI peripheral read Tx FIFO */
 	IT83XX_SPI_FCR = IT83XX_SPI_SPISRTXF;
 }
 
@@ -137,18 +138,18 @@ static void spi_send_response_packet(struct host_packet *pkt)
 {
 	int i, tx_size;
 
-	if (spi_slv_state != SPI_STATE_PROCESSING) {
+	if (spi_peripheral_state != SPI_STATE_PROCESSING) {
 		CPRINTS("The request data is not processing.");
 		return;
 	}
 
 	/* Append our past-end byte, which we reserved space for. */
 	for (i = 0; i < EC_SPI_PAST_END_LENGTH; i++)
-		((uint8_t *)pkt->response)[pkt->response_size + i]
-			= EC_SPI_PAST_END;
+		((uint8_t *)pkt->response)[pkt->response_size + i] =
+			EC_SPI_PAST_END;
 
 	tx_size = pkt->response_size + EC_SPI_PREAMBLE_LENGTH +
-			EC_SPI_PAST_END_LENGTH;
+		  EC_SPI_PAST_END_LENGTH;
 
 	/* Transmit the reply */
 	spi_response_host_data(out_msg, tx_size);
@@ -169,7 +170,7 @@ static void spi_host_request_data(uint8_t *in_msg_addr, int count)
 	 */
 
 	for (i = 0; i < count; i += 4)
-		/* Get data from master to buffer */
+		/* Get data from controller to buffer */
 		*(uint32_t *)(in_msg_addr + i) = IT83XX_SPI_RXFRDRB0;
 }
 
@@ -193,7 +194,7 @@ static void spi_parse_header(void)
 
 		/* Store request data from Rx FIFO to in_msg buffer */
 		spi_host_request_data(in_msg + sizeof(*r),
-			pkt_size - sizeof(*r));
+				      pkt_size - sizeof(*r));
 
 		/* Set up parameters for host request */
 		spi_packet.send_response = spi_send_response_packet;
@@ -233,8 +234,24 @@ void spi_event(enum gpio_signal signal)
 	}
 }
 
-void spi_slv_int_handler(void)
+void spi_peripheral_int_handler(void)
 {
+	if (IS_ENABLED(CONFIG_BOOTBLOCK) &&
+	    (IT83XX_SPI_ISR & IT83XX_SPI_RX_FIFO_FULL) &&
+	    (IT83XX_SPI_EMMCBMR & IT83XX_SPI_EMMCABM)) {
+		spi_host_request_data(in_msg, 128);
+		/* End CPU access RX FIFO */
+		IT83XX_SPI_TXRXFAR = 0;
+		/* Write to clear interrupt status */
+		IT83XX_SPI_ISR = 0xff;
+		/*
+		 * Handle eMMC CMD0:
+		 * GO_IDLE_STATE, GO_PRE_IDLE_STATE, and BOOT_INITIATION
+		 */
+		spi_emmc_cmd0_isr((uint32_t *)in_msg);
+		return;
+	}
+
 	/*
 	 * The status of SPI end detection interrupt bit is set, it
 	 * means that host command parse has been completed and AP
@@ -242,12 +259,6 @@ void spi_slv_int_handler(void)
 	 * EC responded data, then AP ended the transaction.
 	 */
 	if (IT83XX_SPI_ISR & IT83XX_SPI_ENDDETECTINT) {
-		/* Reset fifo and prepare to receive next transaction */
-		if (!IS_ENABLED(IT83XX_SPI_AUTO_RESET_RX_FIFO))
-			reset_rx_fifo();
-		/* Enable Rx byte reach interrupt */
-		if (!IS_ENABLED(IT83XX_SPI_RX_VALID_INT))
-			IT83XX_SPI_IMR &= ~IT83XX_SPI_RX_REACH;
 		/* Ready to receive */
 		spi_set_state(SPI_STATE_READY_TO_RECV);
 		/*
@@ -255,50 +266,50 @@ void spi_slv_int_handler(void)
 		 * sleep bit of SPI in S3 or lower.
 		 */
 		enable_sleep(SLEEP_MASK_SPI);
-		/* CS# is deasserted, so write clear all slave status */
+		/* CS# is deasserted, so write clear all peripheral status */
 		IT83XX_SPI_ISR = 0xff;
 	}
-
-	if (IS_ENABLED(IT83XX_SPI_RX_VALID_INT)) {
-		/*
-		 * The status of Rx valid length interrupt bit is set that
-		 * indicates reached target count(IT83XX_SPI_FTCB1R,
-		 * IT83XX_SPI_FTCB0R) and the length field of the host
-		 * requested data.
-		 */
-		if (IT83XX_SPI_RX_VLISR & IT83XX_SPI_RVLI) {
-			/* write clear slave status */
-			IT83XX_SPI_RX_VLISR = IT83XX_SPI_RVLI;
-			/* Parse header for version of spi-protocol */
-			spi_parse_header();
-		}
-	} else {
-		/*
-		 * The status of Rx byte reach interrupt bit is set,
-		 * start to parse transaction.
-		 * There is a limitation that Rx FIFO starts dropping
-		 * data when the CPU access the the FIFO. So we will
-		 * wait the data until Rx byte reach then to parse.
-		 * The Rx FIFO to reach is mock data generated by
-		 * generate clock that is not the bytes sent from
-		 * the host.
-		 */
-		if (IT83XX_SPI_ISR & IT83XX_SPI_RX_REACH) {
-			/* Disable Rx byte reach interrupt */
-			IT83XX_SPI_IMR |= IT83XX_SPI_RX_REACH;
-			/* write clear slave status */
-			IT83XX_SPI_ISR = IT83XX_SPI_RX_REACH;
-			/* Parse header for version of spi-protocol */
-			spi_parse_header();
-		}
+	/*
+	 * The status of Rx valid length interrupt bit is set that
+	 * indicates reached target count(IT83XX_SPI_FTCB1R,
+	 * IT83XX_SPI_FTCB0R) and the length field of the host
+	 * requested data.
+	 */
+	if (IT83XX_SPI_RX_VLISR & IT83XX_SPI_RVLI) {
+		/* write clear peripheral status */
+		IT83XX_SPI_RX_VLISR = IT83XX_SPI_RVLI;
+		/* Parse header for version of spi-protocol */
+		spi_parse_header();
 	}
 
 	/* Clear the interrupt status */
-	task_clear_pending_irq(IT83XX_IRQ_SPI_SLAVE);
+	task_clear_pending_irq(IT83XX_IRQ_SPI_PERIPHERAL);
 }
 
 static void spi_init(void)
 {
+	/* Set FIFO data target count */
+	struct ec_host_request cmd_head;
+
+	/*
+	 * Target count means the size of host request.
+	 * And plus extra 4 bytes because the CPU accesses FIFO base on
+	 * word. If host requested data length is one byte, we need to
+	 * align the data length to 4 bytes.
+	 */
+	int target_count = sizeof(cmd_head) + 4;
+	/* Offset of data_len member of host request. */
+	int offset = (char *)&cmd_head.data_len - (char *)&cmd_head;
+
+	IT83XX_SPI_FTCB1R = (target_count >> 8) & 0xff;
+	IT83XX_SPI_FTCB0R = target_count & 0xff;
+	/*
+	 * The register setting can capture the length field of host
+	 * request.
+	 */
+	IT83XX_SPI_TCCB1 = (offset >> 8) & 0xff;
+	IT83XX_SPI_TCCB0 = offset & 0xff;
+
 	/* Set SPI pins to alternate function */
 	gpio_config_module(MODULE_SPI, 1);
 	/*
@@ -308,43 +319,16 @@ static void spi_init(void)
 	IT83XX_GCTRL_MCCR3 |= IT83XX_GCTRL_SPISLVPFE;
 	/* Set unused blocked byte */
 	IT83XX_SPI_HPR2 = 0x00;
-	/* Set FIFO data target count */
-	if (IS_ENABLED(IT83XX_SPI_RX_VALID_INT)) {
-		struct ec_host_request cmd_head;
-		/*
-		 * Target count means the size of host request.
-		 * And plus extra 4 bytes because the CPU accesses FIFO base on
-		 * word. If host requested data length is one byte, we need to
-		 * align the data length to 4 bytes.
-		 */
-		int target_count = sizeof(cmd_head) + 4;
-		/* Offset of data_len member of host request. */
-		int offset = (char *)&cmd_head.data_len - (char *)&cmd_head;
-
-		IT83XX_SPI_FTCB1R = (target_count >> 8) & 0xff;
-		IT83XX_SPI_FTCB0R = target_count & 0xff;
-		/*
-		 * The register setting can capture the length field of host
-		 * request.
-		 */
-		IT83XX_SPI_TCCB1 = (offset >> 8) & 0xff;
-		IT83XX_SPI_TCCB0 = offset & 0xff;
-	} else {
-		IT83XX_SPI_FTCB1R = (SPI_RX_MAX_FIFO_SIZE >> 8) & 0xff;
-		IT83XX_SPI_FTCB0R = SPI_RX_MAX_FIFO_SIZE & 0xff;
-	}
 	/* Rx valid length interrupt enabled */
-	if (IS_ENABLED(IT83XX_SPI_RX_VALID_INT))
-		IT83XX_SPI_RX_VLISMR &= ~IT83XX_SPI_RVLIM;
+	IT83XX_SPI_RX_VLISMR &= ~IT83XX_SPI_RVLIM;
 	/*
 	 * General control register2
 	 * bit4 : Rx FIFO2 will not be overwrited once it's full.
 	 * bit3 : Rx FIFO1 will not be overwrited once it's full.
 	 * bit0 : Rx FIFO1/FIFO2 will reset after each CS_N goes high.
 	 */
-	if (IS_ENABLED(IT83XX_SPI_AUTO_RESET_RX_FIFO))
-		IT83XX_SPI_GCR2 = IT83XX_SPI_RXF2OC | IT83XX_SPI_RXF1OC
-					| IT83XX_SPI_RXFAR;
+	IT83XX_SPI_GCR2 = IT83XX_SPI_RXF2OC | IT83XX_SPI_RXF1OC |
+			  IT83XX_SPI_RXFAR;
 	/*
 	 * Interrupt mask register (0b:Enable, 1b:Mask)
 	 * bit5 : Rx byte reach interrupt mask
@@ -353,25 +337,22 @@ static void spi_init(void)
 	IT83XX_SPI_IMR &= ~IT83XX_SPI_EDIM;
 	/* Reset fifo and prepare to for next transaction */
 	reset_rx_fifo();
-	/* Enable Rx byte reach interrupt */
-	if (!IS_ENABLED(IT83XX_SPI_RX_VALID_INT))
-		IT83XX_SPI_IMR &= ~IT83XX_SPI_RX_REACH;
 	/* Ready to receive */
 	spi_set_state(SPI_STATE_READY_TO_RECV);
 	/* Interrupt status register(write one to clear) */
 	IT83XX_SPI_ISR = 0xff;
-	/* SPI slave controller enable (after settings are ready) */
+	/* SPI peripheral enable (after settings are ready) */
 	IT83XX_SPI_SPISGCR = IT83XX_SPI_SPISCEN;
-	/* Enable SPI slave interrupt */
-	task_clear_pending_irq(IT83XX_IRQ_SPI_SLAVE);
-	task_enable_irq(IT83XX_IRQ_SPI_SLAVE);
+	/* Enable SPI peripheral interrupt */
+	task_clear_pending_irq(IT83XX_IRQ_SPI_PERIPHERAL);
+	task_enable_irq(IT83XX_IRQ_SPI_PERIPHERAL);
 	/* Enable SPI chip select pin interrupt */
 	gpio_clear_pending_interrupt(GPIO_SPI0_CS);
 	gpio_enable_interrupt(GPIO_SPI0_CS);
 }
 DECLARE_HOOK(HOOK_INIT, spi_init, HOOK_PRIO_INIT_SPI);
 
-/* reset slave SPI module */
+/* reset peripheral SPI module */
 static void spi_reset(void)
 {
 	/*
@@ -382,8 +363,25 @@ static void spi_reset(void)
 }
 DECLARE_HOOK(HOOK_SYSJUMP, spi_reset, HOOK_PRIO_DEFAULT);
 
+#if defined(SECTION_IS_RO) && defined(CONFIG_BOOTBLOCK)
+/* AP has booted */
+void emmc_ap_jump_to_bl(enum gpio_signal signal)
+{
+	/* Transmission completed. Set SPI pin mux to AP communication mode */
+	IT83XX_GCTRL_PIN_MUX0 &= ~BIT(7);
+	/* Reset and re-initialize SPI module to communication mode */
+	spi_reset();
+	spi_init();
+	/* Disable interrupt of detection of AP's BOOTBLOCK_EN_L */
+	gpio_disable_interrupt(GPIO_BOOTBLOCK_EN_L);
+	enable_sleep(SLEEP_MASK_EMMC);
+
+	CPRINTS("eMMC emulation disabled. AP Jumped to BL");
+}
+#endif
+
 /* Get protocol information */
-enum ec_status spi_get_protocol_info(struct host_cmd_handler_args *args)
+static enum ec_status _spi_get_protocol_info(struct host_cmd_handler_args *args)
 {
 	struct ec_response_get_protocol_info *r = args->response;
 
@@ -397,6 +395,10 @@ enum ec_status spi_get_protocol_info(struct host_cmd_handler_args *args)
 
 	return EC_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO,
-		spi_get_protocol_info,
-		EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, _spi_get_protocol_info,
+		     EC_VER_MASK(0));
+
+enum ec_status spi_get_protocol_info(struct host_cmd_handler_args *args)
+{
+	return _spi_get_protocol_info(args);
+}
diff --git a/chip/it83xx/spi_controller.c b/chip/it83xx/spi_controller.c
new file mode 100644
index 0000000000..aaab27e138
--- /dev/null
+++ b/chip/it83xx/spi_controller.c
@@ -0,0 +1,173 @@
+/* Copyright 2015 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* SPI module for Chrome EC */
+
+#include "clock.h"
+#include "console.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "registers.h"
+#include "spi.h"
+#include "task.h"
+#include "timer.h"
+#include "util.h"
+
+/* Console output macros */
+#define CPUTS(outstr) cputs(CC_SPI, outstr)
+#define CPRINTS(format, args...) cprints(CC_SPI, format, ##args)
+
+enum sspi_clk_sel {
+	sspi_clk_24mhz = 0,
+	sspi_clk_12mhz,
+	sspi_clk_8mhz,
+	sspi_clk_6mhz,
+	sspi_clk_4p8mhz,
+	sspi_clk_4mhz,
+	sspi_clk_3p428mhz,
+	sspi_clk_3mhz,
+};
+
+enum sspi_ch_sel {
+	SSPI_CH_CS0 = 0,
+	SSPI_CH_CS1,
+};
+
+static void sspi_frequency(enum sspi_clk_sel freq)
+{
+	/*
+	 * bit[6:5]
+	 * Bit 6:Clock Polarity (CLPOL)
+	 * 0: SSCK is low in the idle mode.
+	 * 1: SSCK is high in the idle mode.
+	 * Bit 5:Clock Phase (CLPHS)
+	 * 0: Latch data on the first SSCK edge.
+	 * 1: Latch data on the second SSCK edge.
+	 *
+	 * bit[4:2]
+	 * 000b: 1/2 clk_sspi
+	 * 001b: 1/4 clk_sspi
+	 * 010b: 1/6 clk_sspi
+	 * 011b: 1/8 clk_sspi
+	 * 100b: 1/10 clk_sspi
+	 * 101b: 1/12 clk_sspi
+	 * 110b: 1/14 clk_sspi
+	 * 111b: 1/16 clk_sspi
+	 *
+	 * SSCK frequency is [freq] MHz and mode 3.
+	 * note, clk_sspi need equal to 48MHz above.
+	 */
+	IT83XX_SSPI_SPICTRL1 |= (0x60 | (freq << 2));
+}
+
+static void sspi_transmission_end(void)
+{
+	/* Write 1 to end the SPI transmission. */
+	IT83XX_SSPI_SPISTS = 0x20;
+
+	/* Short delay for "Transfer End Flag" */
+	IT83XX_GCTRL_WNCKR = 0;
+
+	/* Write 1 to clear this bit and terminate data transmission. */
+	IT83XX_SSPI_SPISTS = 0x02;
+}
+
+/* We assume only one SPI port in the chip, one SPI device */
+int spi_enable(const struct spi_device_t *spi_device, int enable)
+{
+	int port = spi_device->port;
+
+	if (enable) {
+		/*
+		 * bit[5:4]
+		 * 00b: SPI channel 0 and channel 1 are disabled.
+		 * 10b: SSCK/SMOSI/SMISO/SSCE1# are enabled.
+		 * 01b: SSCK/SMOSI/SMISO/SSCE0# are enabled.
+		 * 11b: SSCK/SMOSI/SMISO/SSCE1#/SSCE0# are enabled.
+		 */
+		if (port == SSPI_CH_CS1)
+			IT83XX_GPIO_GRC1 |= 0x20;
+		else
+			IT83XX_GPIO_GRC1 |= 0x10;
+
+		gpio_config_module(MODULE_SPI_CONTROLLER, 1);
+	} else {
+		if (port == SSPI_CH_CS1)
+			IT83XX_GPIO_GRC1 &= ~0x20;
+		else
+			IT83XX_GPIO_GRC1 &= ~0x10;
+
+		gpio_config_module(MODULE_SPI_CONTROLLER, 0);
+	}
+
+	return EC_SUCCESS;
+}
+
+int spi_transaction(const struct spi_device_t *spi_device,
+		    const uint8_t *txdata, int txlen, uint8_t *rxdata,
+		    int rxlen)
+{
+	int idx;
+	uint8_t port = spi_device->port;
+	static struct mutex spi_mutex;
+
+	mutex_lock(&spi_mutex);
+	/* bit[0]: Write cycle */
+	IT83XX_SSPI_SPICTRL2 &= ~0x04;
+	for (idx = 0x00; idx < txlen; idx++) {
+		IT83XX_SSPI_SPIDATA = txdata[idx];
+		if (port == SSPI_CH_CS1)
+			/* Write 1 to start the data transmission of CS1 */
+			IT83XX_SSPI_SPISTS |= 0x08;
+		else
+			/* Write 1 to start the data transmission of CS0 */
+			IT83XX_SSPI_SPISTS |= 0x10;
+	}
+
+	/* bit[1]: Read cycle */
+	IT83XX_SSPI_SPICTRL2 |= 0x04;
+	for (idx = 0x00; idx < rxlen; idx++) {
+		if (port == SSPI_CH_CS1)
+			/* Write 1 to start the data transmission of CS1 */
+			IT83XX_SSPI_SPISTS |= 0x08;
+		else
+			/* Write 1 to start the data transmission of CS0 */
+			IT83XX_SSPI_SPISTS |= 0x10;
+		rxdata[idx] = IT83XX_SSPI_SPIDATA;
+	}
+
+	sspi_transmission_end();
+	mutex_unlock(&spi_mutex);
+
+	return EC_SUCCESS;
+}
+
+static void sspi_init(void)
+{
+	int i;
+
+	clock_enable_peripheral(CGC_OFFSET_SSPI, 0, 0);
+	sspi_frequency(sspi_clk_8mhz);
+
+	/*
+	 * bit[5:3] Byte Width (BYTEWIDTH)
+	 * 000b: 8-bit transmission
+	 * 001b: 1-bit transmission
+	 * 010b: 2-bit transmission
+	 * 011b: 3-bit transmission
+	 * 100b: 4-bit transmission
+	 * 101b: 5-bit transmission
+	 * 110b: 6-bit transmission
+	 * 111b: 7-bit transmission
+	 *
+	 * bit[1] Blocking selection
+	 */
+	IT83XX_SSPI_SPICTRL2 |= 0x02;
+
+	for (i = 0; i < spi_devices_used; i++)
+		/* Disabling spi module */
+		spi_enable(&spi_devices[i], 0);
+}
+DECLARE_HOOK(HOOK_INIT, sspi_init, HOOK_PRIO_INIT_SPI);
diff --git a/chip/it83xx/spi_master.c b/chip/it83xx/spi_master.c
deleted file mode 100644
index 23cea9d2ab..0000000000
--- a/chip/it83xx/spi_master.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* SPI module for Chrome EC */
-
-#include "clock.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "spi.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_SPI, outstr)
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
-
-enum sspi_clk_sel {
-	sspi_clk_24mhz = 0,
-	sspi_clk_12mhz,
-	sspi_clk_8mhz,
-	sspi_clk_6mhz,
-	sspi_clk_4p8mhz,
-	sspi_clk_4mhz,
-	sspi_clk_3p428mhz,
-	sspi_clk_3mhz,
-};
-
-enum sspi_ch_sel {
-	SSPI_CH_CS0 = 0,
-	SSPI_CH_CS1,
-};
-
-static void sspi_frequency(enum sspi_clk_sel freq)
-{
-	/*
-	 * bit[6:5]
-	 * Bit 6:Clock Polarity (CLPOL)
-	 * 0: SSCK is low in the idle mode.
-	 * 1: SSCK is high in the idle mode.
-	 * Bit 5:Clock Phase (CLPHS)
-	 * 0: Latch data on the first SSCK edge.
-	 * 1: Latch data on the second SSCK edge.
-	 *
-	 * bit[4:2]
-	 * 000b: 1/2 clk_sspi
-	 * 001b: 1/4 clk_sspi
-	 * 010b: 1/6 clk_sspi
-	 * 011b: 1/8 clk_sspi
-	 * 100b: 1/10 clk_sspi
-	 * 101b: 1/12 clk_sspi
-	 * 110b: 1/14 clk_sspi
-	 * 111b: 1/16 clk_sspi
-	 *
-	 * SSCK frequency is [freq] MHz and mode 3.
-	 * note, clk_sspi need equal to 48MHz above.
-	 */
-	IT83XX_SSPI_SPICTRL1 |= (0x60 | (freq << 2));
-}
-
-static void sspi_transmission_end(void)
-{
-	/* Write 1 to end the SPI transmission. */
-	IT83XX_SSPI_SPISTS = 0x20;
-
-	/* Short delay for "Transfer End Flag" */
-	IT83XX_GCTRL_WNCKR = 0;
-
-	/* Write 1 to clear this bit and terminate data transmission. */
-	IT83XX_SSPI_SPISTS = 0x02;
-}
-
-/* We assume only one SPI port in the chip, one SPI device */
-int spi_enable(int port, int enable)
-{
-	if (enable) {
-		/*
-		 * bit[5:4]
-		 * 00b: SPI channel 0 and channel 1 are disabled.
-		 * 10b: SSCK/SMOSI/SMISO/SSCE1# are enabled.
-		 * 01b: SSCK/SMOSI/SMISO/SSCE0# are enabled.
-		 * 11b: SSCK/SMOSI/SMISO/SSCE1#/SSCE0# are enabled.
-		 */
-		if (port == SSPI_CH_CS1)
-			IT83XX_GPIO_GRC1 |= 0x20;
-		else
-			IT83XX_GPIO_GRC1 |= 0x10;
-
-		gpio_config_module(MODULE_SPI_MASTER, 1);
-	} else {
-		if (port == SSPI_CH_CS1)
-			IT83XX_GPIO_GRC1 &= ~0x20;
-		else
-			IT83XX_GPIO_GRC1 &= ~0x10;
-
-		gpio_config_module(MODULE_SPI_MASTER, 0);
-	}
-
-	return EC_SUCCESS;
-}
-
-int spi_transaction(const struct spi_device_t *spi_device,
-		const uint8_t *txdata, int txlen,
-		uint8_t *rxdata, int rxlen)
-{
-	int idx;
-	uint8_t port = spi_device->port;
-	static struct mutex spi_mutex;
-
-	mutex_lock(&spi_mutex);
-	/* bit[0]: Write cycle */
-	IT83XX_SSPI_SPICTRL2 &= ~0x04;
-	for (idx = 0x00; idx < txlen; idx++) {
-		IT83XX_SSPI_SPIDATA = txdata[idx];
-		if (port == SSPI_CH_CS1)
-			/* Write 1 to start the data transmission of CS1 */
-			IT83XX_SSPI_SPISTS |= 0x08;
-		else
-			/* Write 1 to start the data transmission of CS0 */
-			IT83XX_SSPI_SPISTS |= 0x10;
-	}
-
-	/* bit[1]: Read cycle */
-	IT83XX_SSPI_SPICTRL2 |= 0x04;
-	for (idx = 0x00; idx < rxlen; idx++) {
-		if (port == SSPI_CH_CS1)
-			/* Write 1 to start the data transmission of CS1 */
-			IT83XX_SSPI_SPISTS |= 0x08;
-		else
-			/* Write 1 to start the data transmission of CS0 */
-			IT83XX_SSPI_SPISTS |= 0x10;
-		rxdata[idx] = IT83XX_SSPI_SPIDATA;
-	}
-
-	sspi_transmission_end();
-	mutex_unlock(&spi_mutex);
-
-	return EC_SUCCESS;
-}
-
-static void sspi_init(void)
-{
-	int i;
-
-	clock_enable_peripheral(CGC_OFFSET_SSPI, 0, 0);
-	sspi_frequency(sspi_clk_8mhz);
-
-	/*
-	 * bit[5:3] Byte Width (BYTEWIDTH)
-	 * 000b: 8-bit transmission
-	 * 001b: 1-bit transmission
-	 * 010b: 2-bit transmission
-	 * 011b: 3-bit transmission
-	 * 100b: 4-bit transmission
-	 * 101b: 5-bit transmission
-	 * 110b: 6-bit transmission
-	 * 111b: 7-bit transmission
-	 *
-	 * bit[1] Blocking selection
-	 */
-	IT83XX_SSPI_SPICTRL2 |= 0x02;
-
-	for (i = 0; i < spi_devices_used; i++)
-		/* Disabling spi module */
-		spi_enable(spi_devices[i].port, 0);
-}
-DECLARE_HOOK(HOOK_INIT, sspi_init, HOOK_PRIO_INIT_SPI);
diff --git a/chip/it83xx/system.c b/chip/it83xx/system.c
index 960ef7b622..09c5678cd4 100644
--- a/chip/it83xx/system.c
+++ b/chip/it83xx/system.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,16 +7,18 @@
 
 #include "console.h"
 #include "cpu.h"
+#include "cros_version.h"
 #include "ec2i_chip.h"
 #include "flash.h"
 #include "hooks.h"
 #include "host_command.h"
 #include "intc.h"
+#include "link_defs.h"
+#include "panic.h"
 #include "registers.h"
 #include "system.h"
 #include "task.h"
 #include "util.h"
-#include "version.h"
 #include "watchdog.h"
 
 void system_hibernate(uint32_t seconds, uint32_t microseconds)
@@ -43,12 +45,48 @@ static int delayed_clear_reset_flags;
 static void clear_reset_flags(void)
 {
 	if (IS_ENABLED(CONFIG_BOARD_RESET_AFTER_POWER_ON) &&
-			delayed_clear_reset_flags) {
+	    delayed_clear_reset_flags) {
 		chip_save_reset_flags(0);
 	}
 }
 DECLARE_HOOK(HOOK_INIT, clear_reset_flags, HOOK_PRIO_LAST);
 
+#if !defined(CONFIG_HOST_INTERFACE_LPC) && !defined(CONFIG_HOST_INTERFACE_ESPI)
+static void system_save_panic_data_to_bram(void)
+{
+	uint8_t *ptr = (uint8_t *)PANIC_DATA_PTR;
+
+	for (int i = 0; i < CONFIG_PANIC_DATA_SIZE; i++)
+		IT83XX_BRAM_BANK0(i + BRAM_PANIC_DATA_START) = ptr[i];
+}
+
+static void system_restore_panic_data_from_bram(void)
+{
+	uint8_t *ptr = (uint8_t *)PANIC_DATA_PTR;
+
+	for (int i = 0; i < CONFIG_PANIC_DATA_SIZE; i++)
+		ptr[i] = IT83XX_BRAM_BANK0(i + BRAM_PANIC_DATA_START);
+}
+BUILD_ASSERT(BRAM_PANIC_LEN >= CONFIG_PANIC_DATA_SIZE);
+#else
+static void system_save_panic_data_to_bram(void)
+{
+}
+static void system_restore_panic_data_from_bram(void)
+{
+}
+#endif
+
+static void system_reset_ec_by_gpg1(void)
+{
+	system_save_panic_data_to_bram();
+	/* Set GPG1 as output high and wait until EC reset. */
+	IT83XX_GPIO_CTRL(GPIO_G, 1) = GPCR_PORT_PIN_MODE_OUTPUT;
+	IT83XX_GPIO_DATA(GPIO_G) |= BIT(1);
+	while (1)
+		;
+}
+
 static void check_reset_cause(void)
 {
 	uint32_t flags;
@@ -65,6 +103,18 @@ static void check_reset_cause(void)
 	/* Determine if watchdog reset or power on reset. */
 	if (raw_reset_cause & 0x02) {
 		flags |= EC_RESET_FLAG_WATCHDOG;
+		if (IS_ENABLED(CONFIG_IT83XX_HARD_RESET_BY_GPG1)) {
+			/*
+			 * Save watchdog reset flag to BRAM so we can restore
+			 * the flag on next reboot.
+			 */
+			chip_save_reset_flags(EC_RESET_FLAG_WATCHDOG);
+			/*
+			 * Assert GPG1 to reset EC and then EC_RST_ODL will be
+			 * toggled.
+			 */
+			system_reset_ec_by_gpg1();
+		}
 	} else if (raw_reset_cause & 0x01) {
 		flags |= EC_RESET_FLAG_POWER_ON;
 	} else {
@@ -87,7 +137,7 @@ static void check_reset_cause(void)
 	 * we know this is the first reset.
 	 */
 	if (IS_ENABLED(CONFIG_BOARD_RESET_AFTER_POWER_ON) &&
-			(flags & EC_RESET_FLAG_POWER_ON)) {
+	    (flags & EC_RESET_FLAG_POWER_ON)) {
 		if (flags & EC_RESET_FLAG_INITIAL_PWR) {
 			/* Second boot, clear the flag immediately */
 			chip_save_reset_flags(0);
@@ -101,7 +151,7 @@ static void check_reset_cause(void)
 			 * fine because we will have the correct flag anyway.
 			 */
 			chip_save_reset_flags(chip_read_reset_flags() |
-						EC_RESET_FLAG_INITIAL_PWR);
+					      EC_RESET_FLAG_INITIAL_PWR);
 
 			/*
 			 * Schedule chip_save_reset_flags(0) later.
@@ -118,10 +168,14 @@ static void check_reset_cause(void)
 
 	/* Clear PD contract recorded in bram if this is a power-on reset. */
 	if (IS_ENABLED(CONFIG_IT83XX_RESET_PD_CONTRACT_IN_BRAM) &&
-	   (flags == (EC_RESET_FLAG_POWER_ON | EC_RESET_FLAG_RESET_PIN))) {
+	    (flags == (EC_RESET_FLAG_POWER_ON | EC_RESET_FLAG_RESET_PIN))) {
 		for (int i = 0; i < MAX_SYSTEM_BBRAM_IDX_PD_PORTS; i++)
 			system_set_bbram((SYSTEM_BBRAM_IDX_PD0 + i), 0);
 	}
+
+	if ((IS_ENABLED(CONFIG_IT83XX_HARD_RESET_BY_GPG1)) &&
+	    (flags & ~(EC_RESET_FLAG_POWER_ON | EC_RESET_FLAG_RESET_PIN)))
+		system_restore_panic_data_from_bram();
 }
 
 static void system_reset_cause_is_unknown(void)
@@ -134,7 +188,7 @@ static void system_reset_cause_is_unknown(void)
 		 * eg: Andes core (jral5: LP=PC+2, jal: LP=PC+4)
 		 */
 		ccprintf("===Unknown reset! jump from %x or %x===\n",
-				ec_reset_lp - 4, ec_reset_lp - 2);
+			 ec_reset_lp - 4, ec_reset_lp - 2);
 }
 DECLARE_HOOK(HOOK_INIT, system_reset_cause_is_unknown, HOOK_PRIO_FIRST);
 
@@ -161,6 +215,9 @@ int system_is_reboot_warm(void)
 
 void chip_pre_init(void)
 {
+	/* bit1=0: disable pre-defined command */
+	IT83XX_SMB_SFFCTL &= ~IT83XX_SMB_HSAPE;
+
 	/* bit0, EC received the special waveform from iteflash */
 	if (IT83XX_GCTRL_DBGROS & IT83XX_SMB_DBGR) {
 		/*
@@ -187,7 +244,7 @@ void chip_pre_init(void)
 		IT83XX_GCTRL_WMCR |= BIT(7);
 }
 
-#define BRAM_VALID_MAGIC        0x4252414D  /* "BRAM" */
+#define BRAM_VALID_MAGIC 0x4252414D /* "BRAM" */
 #define BRAM_VALID_MAGIC_FIELD0 (BRAM_VALID_MAGIC & 0xff)
 #define BRAM_VALID_MAGIC_FIELD1 ((BRAM_VALID_MAGIC >> 8) & 0xff)
 #define BRAM_VALID_MAGIC_FIELD2 ((BRAM_VALID_MAGIC >> 16) & 0xff)
@@ -212,12 +269,21 @@ void chip_bram_valid(void)
 		BRAM_VALID_FLAGS2 = BRAM_VALID_MAGIC_FIELD2;
 		BRAM_VALID_FLAGS3 = BRAM_VALID_MAGIC_FIELD3;
 	}
+
+#if defined(CONFIG_PRESERVE_LOGS) && defined(CONFIG_IT83XX_HARD_RESET_BY_GPG1)
+	if (BRAM_EC_LOG_STATUS == EC_LOG_SAVED_IN_FLASH) {
+		/* Restore EC logs from flash. */
+		memcpy((void *)__preserved_logs_start,
+		       (const void *)CHIP_FLASH_PRESERVE_LOGS_BASE,
+		       (uintptr_t)__preserved_logs_size);
+	}
+	BRAM_EC_LOG_STATUS = 0;
+#endif
 }
 
 void system_pre_init(void)
 {
 	/* No initialization required */
-
 }
 
 uint32_t chip_read_reset_flags(void)
@@ -248,6 +314,16 @@ void system_reset(int flags)
 		cflush();
 	}
 
+#if defined(CONFIG_PRESERVE_LOGS) && defined(CONFIG_IT83XX_HARD_RESET_BY_GPG1)
+	/* Saving EC logs into flash before reset. */
+	crec_flash_physical_erase(CHIP_FLASH_PRESERVE_LOGS_BASE,
+				  CHIP_FLASH_PRESERVE_LOGS_SIZE);
+	crec_flash_physical_write(CHIP_FLASH_PRESERVE_LOGS_BASE,
+				  (uintptr_t)__preserved_logs_size,
+				  __preserved_logs_start);
+	BRAM_EC_LOG_STATUS = EC_LOG_SAVED_IN_FLASH;
+#endif
+
 	/* Disable interrupts to avoid task swaps during reboot. */
 	interrupt_disable();
 
@@ -276,6 +352,10 @@ void system_reset(int flags)
 	if (flags & SYSTEM_RESET_HARD)
 		IT83XX_GCTRL_ETWDUARTCR |= ETWD_HW_RST_EN;
 #endif
+	/* Set GPG1 as output high and wait until EC reset. */
+	if (IS_ENABLED(CONFIG_IT83XX_HARD_RESET_BY_GPG1))
+		system_reset_ec_by_gpg1();
+
 	/*
 	 * Writing invalid key to watchdog module triggers a soft or hardware
 	 * reset. It depends on the setting of bit0 at ETWDUARTCR register.
@@ -298,23 +378,18 @@ int system_set_scratchpad(uint32_t value)
 	return EC_SUCCESS;
 }
 
-uint32_t system_get_scratchpad(void)
+int system_get_scratchpad(uint32_t *value)
 {
-	uint32_t value = 0;
-
-	value |= BRAM_SCRATCHPAD3 << 24;
-	value |= BRAM_SCRATCHPAD2 << 16;
-	value |= BRAM_SCRATCHPAD1 << 8;
-	value |= BRAM_SCRATCHPAD0;
-
-	return value;
+	*value = (BRAM_SCRATCHPAD3 << 24) | (BRAM_SCRATCHPAD2 << 16) |
+		 (BRAM_SCRATCHPAD1 << 8) | (BRAM_SCRATCHPAD0);
+	return EC_SUCCESS;
 }
 
 static uint32_t system_get_chip_id(void)
 {
 #ifdef IT83XX_CHIP_ID_3BYTES
 	return (IT83XX_GCTRL_CHIPID1 << 16) | (IT83XX_GCTRL_CHIPID2 << 8) |
-		IT83XX_GCTRL_CHIPID3;
+	       IT83XX_GCTRL_CHIPID3;
 #else
 	return (IT83XX_GCTRL_CHIPID1 << 8) | IT83XX_GCTRL_CHIPID2;
 #endif
@@ -340,7 +415,7 @@ const char *system_get_chip_vendor(void)
 
 const char *system_get_chip_name(void)
 {
-	static char buf[8] = {'i', 't'};
+	static char buf[8] = { 'i', 't' };
 	int num = (IS_ENABLED(IT83XX_CHIP_ID_3BYTES) ? 4 : 3);
 	uint32_t chip_id = system_get_chip_id();
 
@@ -363,10 +438,6 @@ const char *system_get_chip_revision(void)
 
 static int bram_idx_lookup(enum system_bbram_idx idx)
 {
-	if (idx >= SYSTEM_BBRAM_IDX_VBNVBLOCK0 &&
-	    idx <= SYSTEM_BBRAM_IDX_VBNVBLOCK15)
-		return BRAM_IDX_NVCONTEXT +
-		       idx - SYSTEM_BBRAM_IDX_VBNVBLOCK0;
 	if (idx == SYSTEM_BBRAM_IDX_PD0)
 		return BRAM_IDX_PD0;
 	if (idx == SYSTEM_BBRAM_IDX_PD1)
@@ -398,9 +469,6 @@ int system_set_bbram(enum system_bbram_idx idx, uint8_t value)
 	return EC_SUCCESS;
 }
 
-#define BRAM_NVCONTEXT_SIZE (BRAM_IDX_NVCONTEXT_END - BRAM_IDX_NVCONTEXT + 1)
-BUILD_ASSERT(EC_VBNV_BLOCK_SIZE <= BRAM_NVCONTEXT_SIZE);
-
 uintptr_t system_get_fw_reset_vector(uintptr_t base)
 {
 	/*
diff --git a/chip/it83xx/uart.c b/chip/it83xx/uart.c
index d0b645e68c..6635c5966e 100644
--- a/chip/it83xx/uart.c
+++ b/chip/it83xx/uart.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,7 +17,7 @@
 #include "util.h"
 
 /* Traces on UART1 */
-#define UART_PORT      0
+#define UART_PORT 0
 #define UART_PORT_HOST 1
 
 static int init_done;
diff --git a/chip/it83xx/watchdog.c b/chip/it83xx/watchdog.c
index f0e200c4ac..b67987d899 100644
--- a/chip/it83xx/watchdog.c
+++ b/chip/it83xx/watchdog.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,9 +24,9 @@ static int wdt_warning_fired;
  */
 
 /* Magic value to tickle the watchdog register. */
-#define ITE83XX_WATCHDOG_MAGIC_WORD  0x5C
+#define ITE83XX_WATCHDOG_MAGIC_WORD 0x5C
 /* Start to print warning message. */
-#define ITE83XX_WATCHDOG_WARNING_MS  CONFIG_AUX_TIMER_PERIOD_MS
+#define ITE83XX_WATCHDOG_WARNING_MS CONFIG_AUX_TIMER_PERIOD_MS
 /* The interval to print warning message at critical period. */
 #define ITE83XX_WATCHDOG_CRITICAL_MS 30
 
@@ -38,14 +38,27 @@ static void watchdog_set_warning_timer(int32_t ms, int init)
 
 void watchdog_warning_irq(void)
 {
-#ifdef CONFIG_SOFTWARE_PANIC
-	struct panic_data * const pdata_ptr = get_panic_data_write();
-
+	/*
+	 * Why we directly use the PANIC_DATA_PTR:
+	 *
+	 * We don't get the panic data pointer from get_panic_data_write()
+	 * because this interrupt fires on a warning and we don't want to
+	 * initialize a panic with only a warning. We also don't use
+	 * panic_get_data() because that function returns a NULL pointer if
+	 * panic data was never prior initialized.
+	 *
+	 * Why we fill ipc/mepc here in the watchdog bark/warning interrupt:
+	 *
+	 * In ITE, a full watchdog bite results in an EC reset that bypasses all
+	 * exception handlers. We save the program counter now (during a
+	 * warning) before a full watchdog bite occurs so it is accessible after
+	 * the bite.
+	 */
+	struct panic_data *const pdata_ptr = PANIC_DATA_PTR;
 #if defined(CHIP_CORE_NDS32)
 	pdata_ptr->nds_n8.ipc = get_ipc();
 #elif defined(CHIP_CORE_RISCV)
 	pdata_ptr->riscv.mepc = get_mepc();
-#endif
 #endif
 	/* clear interrupt status */
 	task_clear_pending_irq(et_ctrl_regs[WDT_EXT_TIMER].irq);
@@ -64,10 +77,10 @@ void watchdog_warning_irq(void)
 	 * LP = PC+4 after a jump and link instruction (jal).
 	 */
 	panic_printf("Pre-WDT warning! IPC:%08x LP:%08x TASK_ID:%d\n",
-		get_ipc(), ilp, task_get_current());
+		     get_ipc(), ilp, task_get_current());
 #elif defined(CHIP_CORE_RISCV)
 	panic_printf("Pre-WDT warning! MEPC:%08x RA:%08x TASK_ID:%d\n",
-		get_mepc(), ira, task_get_current());
+		     get_mepc(), ira, task_get_current());
 #endif
 
 	if (!wdt_warning_fired++)
@@ -93,6 +106,7 @@ void watchdog_reload(void)
 	}
 }
 DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_SYSJUMP, watchdog_reload, HOOK_PRIO_LAST);
 
 int watchdog_init(void)
 {
diff --git a/chip/lm4/adc.c b/chip/lm4/adc.c
deleted file mode 100644
index c06ce35df3..0000000000
--- a/chip/lm4/adc.c
+++ /dev/null
@@ -1,274 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* LM4-specific ADC module for Chrome EC */
-
-#include "adc.h"
-#include "adc_chip.h"
-#include "atomic.h"
-#include "clock.h"
-#include "console.h"
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Maximum time we allow for an ADC conversion */
-#define ADC_TIMEOUT_US SECOND
-
-static volatile task_id_t task_waiting_on_ss[LM4_ADC_SEQ_COUNT];
-
-static void configure_gpio(void)
-{
-	int i, port, mask;
-
-	/* Use analog function for AIN */
-	for (i = 0; i < ADC_CH_COUNT; ++i) {
-		if (adc_channels[i].gpio_mask) {
-			mask = adc_channels[i].gpio_mask;
-			port = adc_channels[i].gpio_port;
-			LM4_GPIO_DEN(port) &= ~mask;
-			LM4_GPIO_AMSEL(port) |= mask;
-		}
-	}
-}
-
-/**
- * Flush an ADC sequencer and initiate a read.
- *
- * @param seq		Sequencer to read
- * @return Raw ADC value.
- */
-static int flush_and_read(enum lm4_adc_sequencer seq)
-{
-	/*
-	 * This is currently simple because we can dedicate a sequencer to each
-	 * ADC channel.  If we have enough channels that's no longer possible,
-	 * this code will need to become more complex.  For example, we could:
-	 *
-	 * 1) Read them all using a timer interrupt, and then return the most
-	 * recent value?  This is lowest-latency for the caller, but won't
-	 * return accurate data if read frequently.
-	 *
-	 * 2) Reserve SS3 for reading a single value, and configure it on each
-	 * read?  Needs mutex if we could have multiple callers; doesn't matter
-	 * if just used for debugging.
-	 *
-	 * 3) Both?
-	 */
-	volatile uint32_t scratch  __attribute__((unused));
-	int event;
-
-	/* Empty the FIFO of any previous results */
-	while (!(LM4_ADC_SSFSTAT(seq) & 0x100))
-		scratch = LM4_ADC_SSFIFO(seq);
-
-	/*
-	 * This assumes we don't have multiple tasks accessing the same
-	 * sequencer. Add mutex lock if needed.
-	 */
-	task_waiting_on_ss[seq] = task_get_current();
-
-	/* Clear the interrupt status */
-	LM4_ADC_ADCISC |= 0x01 << seq;
-
-	/* Enable interrupt */
-	LM4_ADC_ADCIM |= 0x01 << seq;
-
-	/* Initiate sample sequence */
-	LM4_ADC_ADCPSSI |= 0x01 << seq;
-
-	/* Wait for interrupt */
-	event = task_wait_event_mask(TASK_EVENT_ADC_DONE, ADC_TIMEOUT_US);
-
-	/* Disable interrupt */
-	LM4_ADC_ADCIM &= ~(0x01 << seq);
-
-	task_waiting_on_ss[seq] = TASK_ID_INVALID;
-
-	if (!(event & TASK_EVENT_ADC_DONE))
-		return ADC_READ_ERROR;
-
-	/* Read the FIFO and convert to temperature */
-	return LM4_ADC_SSFIFO(seq);
-}
-
-/**
- * Configure an ADC sequencer to be dedicated for an ADC input.
- *
- * @param seq		Sequencer to configure
- * @param ain_id	ADC input to use
- * @param ssctl		Value for sampler sequencer control register
- *
- */
-static void adc_configure(const struct adc_t *adc)
-{
-	const enum lm4_adc_sequencer seq = adc->sequencer;
-
-	/* Configure sample sequencer */
-	LM4_ADC_ADCACTSS &= ~(0x01 << seq);
-
-	/* Trigger sequencer by processor request */
-	LM4_ADC_ADCEMUX = (LM4_ADC_ADCEMUX & ~(0xf << (seq * 4))) | 0x00;
-
-	/* Sample internal temp sensor */
-	if (adc->channel == LM4_AIN_NONE) {
-		LM4_ADC_SSMUX(seq) = 0x00;
-		LM4_ADC_SSEMUX(seq) = 0x00;
-	} else {
-		LM4_ADC_SSMUX(seq) = adc->channel & 0xf;
-		LM4_ADC_SSEMUX(seq) = adc->channel >> 4;
-	}
-	LM4_ADC_SSCTL(seq) = adc->flag;
-
-	/* Enable sample sequencer */
-	LM4_ADC_ADCACTSS |= 0x01 << seq;
-}
-
-int adc_read_channel(enum adc_channel ch)
-{
-	const struct adc_t *adc = adc_channels + ch;
-	static uint32_t ch_busy_mask;
-	static struct mutex adc_clock;
-	int rv;
-
-	/*
-	 * TODO(crbug.com/314121): Generalize ADC reads such that any task can
-	 * trigger a read of any channel.
-	 */
-
-	/*
-	 * Enable ADC clock and set a bit in ch_busy_mask to signify that this
-	 * channel is busy. Note, this function may be called from multiple
-	 * tasks, but each channel may be read by only one task. If assert
-	 * fails, then it means multiple tasks are trying to read same channel.
-	 */
-	mutex_lock(&adc_clock);
-	ASSERT(!(ch_busy_mask & (1UL << ch)));
-	clock_enable_peripheral(CGC_OFFSET_ADC, 0x1,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-	ch_busy_mask |= (1UL << ch);
-	mutex_unlock(&adc_clock);
-
-	rv = flush_and_read(adc->sequencer);
-
-	/*
-	 * If no ADC channels are busy, then disable ADC clock to conserve
-	 * power.
-	 */
-	mutex_lock(&adc_clock);
-	ch_busy_mask &= ~(1UL << ch);
-	if (!ch_busy_mask)
-		clock_disable_peripheral(CGC_OFFSET_ADC, 0x1,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-	mutex_unlock(&adc_clock);
-
-	if (rv == ADC_READ_ERROR)
-		return ADC_READ_ERROR;
-
-	return rv * adc->factor_mul / adc->factor_div + adc->shift;
-}
-
-/*****************************************************************************/
-/* Interrupt handlers */
-
-/**
- * Handle an interrupt on the specified sample sequencer.
- */
-static void handle_interrupt(int ss)
-{
-	int id = task_waiting_on_ss[ss];
-
-	/* Clear the interrupt status */
-	LM4_ADC_ADCISC = (0x1 << ss);
-
-	/* Wake up the task which was waiting on the interrupt, if any */
-	if (id != TASK_ID_INVALID)
-		task_set_event(id, TASK_EVENT_ADC_DONE, 0);
-}
-
-void ss0_interrupt(void) { handle_interrupt(0); }
-void ss1_interrupt(void) { handle_interrupt(1); }
-void ss2_interrupt(void) { handle_interrupt(2); }
-void ss3_interrupt(void) { handle_interrupt(3); }
-
-DECLARE_IRQ(LM4_IRQ_ADC0_SS0, ss0_interrupt, 2);
-DECLARE_IRQ(LM4_IRQ_ADC0_SS1, ss1_interrupt, 2);
-DECLARE_IRQ(LM4_IRQ_ADC0_SS2, ss2_interrupt, 2);
-DECLARE_IRQ(LM4_IRQ_ADC0_SS3, ss3_interrupt, 2);
-
-/*****************************************************************************/
-/* Console commands */
-
-#ifdef CONFIG_CMD_ECTEMP
-static int command_ectemp(int argc, char **argv)
-{
-	int t = adc_read_channel(ADC_CH_EC_TEMP);
-	ccprintf("EC temperature is %d K = %d C\n", t, K_TO_C(t));
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(ectemp, command_ectemp,
-			NULL,
-			"Print EC temperature");
-#endif
-
-/*****************************************************************************/
-/* Initialization */
-
-static void adc_init(void)
-{
-	int i;
-
-	/* Configure GPIOs */
-	configure_gpio();
-
-	/*
-	 * Temporarily enable the PLL when turning on the clock to the ADC
-	 * module, to work around chip errata (10.4).  No need to notify
-	 * other modules; the PLL isn't enabled long enough to matter.
-	 */
-	clock_enable_pll(1, 0);
-
-	/* Enable ADC0 module in run and sleep modes. */
-	clock_enable_peripheral(CGC_OFFSET_ADC, 0x1,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-
-	/*
-	 * Use external voltage references (VREFA+, VREFA-) instead of
-	 * VDDA and GNDA.
-	 */
-	LM4_ADC_ADCCTL = 0x01;
-
-	/* Use internal oscillator */
-	LM4_ADC_ADCCC = 0x1;
-
-	/* Disable the PLL now that the ADC is using the internal oscillator */
-	clock_enable_pll(0, 0);
-
-	/* No tasks waiting yet */
-	for (i = 0; i < LM4_ADC_SEQ_COUNT; i++)
-		task_waiting_on_ss[i] = TASK_ID_INVALID;
-
-	/* Enable IRQs */
-	task_enable_irq(LM4_IRQ_ADC0_SS0);
-	task_enable_irq(LM4_IRQ_ADC0_SS1);
-	task_enable_irq(LM4_IRQ_ADC0_SS2);
-	task_enable_irq(LM4_IRQ_ADC0_SS3);
-
-	/* 2**6 = 64x oversampling */
-	LM4_ADC_ADCSAC = 6;
-
-	/* Initialize ADC sequencer */
-	for (i = 0; i < ADC_CH_COUNT; ++i)
-		adc_configure(adc_channels + i);
-
-	/* Disable ADC0 module until it is needed to conserve power. */
-	clock_disable_peripheral(CGC_OFFSET_ADC, 0x1,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-}
-DECLARE_HOOK(HOOK_INIT, adc_init, HOOK_PRIO_INIT_ADC);
diff --git a/chip/lm4/adc_chip.h b/chip/lm4/adc_chip.h
deleted file mode 100644
index b43bec2da3..0000000000
--- a/chip/lm4/adc_chip.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* LM4-specific ADC module for Chrome EC */
-
-#ifndef __CROS_EC_ADC_CHIP_H
-#define __CROS_EC_ADC_CHIP_H
-
-enum lm4_adc_sequencer {
-	LM4_ADC_SEQ0 = 0,
-	LM4_ADC_SEQ1,
-	LM4_ADC_SEQ2,
-	LM4_ADC_SEQ3,
-	LM4_ADC_SEQ_COUNT
-};
-
-/* Data structure to define ADC channels. */
-struct adc_t {
-	const char *name;
-	enum lm4_adc_sequencer sequencer;
-	int factor_mul;
-	int factor_div;
-	int shift;
-	int channel;
-	int flag;
-	uint32_t gpio_port;
-	uint8_t gpio_mask;
-};
-
-/*
- * Boards must provide this list of ADC channel definitions.  This must match
- * the enum adc_channel list provided by the board.
- */
-extern const struct adc_t adc_channels[];
-
-/* Minimum and maximum values returned by raw ADC read. */
-#define ADC_READ_MIN 0
-#define ADC_READ_MAX 4095
-
-/* Just plain id mapping for code readability */
-#define LM4_AIN(x) (x)
-
-/* Mock value for "channel" in adc_t if we don't have an external channel. */
-#define LM4_AIN_NONE (-1)
-
-#endif /* __CROS_EC_ADC_CHIP_H */
diff --git a/chip/lm4/build.mk b/chip/lm4/build.mk
deleted file mode 100644
index 26419d3a04..0000000000
--- a/chip/lm4/build.mk
+++ /dev/null
@@ -1,31 +0,0 @@
-# -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# LM4 chip specific files build
-#
-
-# LM4 SoC has a Cortex-M4F ARM core
-CORE:=cortex-m
-# Allow the full Cortex-M4 instruction set
-CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
-
-# Required chip modules
-chip-y=clock.o gpio.o hwtimer.o system.o uart.o
-
-# Optional chip modules
-chip-$(CONFIG_ADC)+=adc.o chip_temp_sensor.o
-chip-$(CONFIG_EEPROM)+=eeprom.o
-chip-$(CONFIG_FANS)+=fan.o
-chip-$(CONFIG_FLASH_PHYSICAL)+=flash.o
-chip-$(CONFIG_I2C)+=i2c.o
-chip-$(CONFIG_HOSTCMD_LPC)+=lpc.o
-chip-$(CONFIG_PECI)+=peci.o
-# pwm functions are implemented with the fan functions
-chip-$(CONFIG_PWM)+=pwm.o fan.o
-chip-$(CONFIG_SPI)+=spi.o
-chip-$(CONFIG_WATCHDOG)+=watchdog.o
-ifndef CONFIG_KEYBOARD_NOT_RAW
-chip-$(HAS_TASK_KEYSCAN)+=keyboard_raw.o
-endif
diff --git a/chip/lm4/chip_temp_sensor.c b/chip/lm4/chip_temp_sensor.c
deleted file mode 100644
index eb1bc4d133..0000000000
--- a/chip/lm4/chip_temp_sensor.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Temperature sensor module for Chrome EC */
-
-#include "adc.h"
-#include "adc_chip.h"
-#include "common.h"
-#include "hooks.h"
-
-/* Initialize temperature reading to a valid value (27 C) */
-static int last_val = C_TO_K(27);
-
-static void chip_temp_sensor_poll(void)
-{
-	last_val = adc_read_channel(ADC_CH_EC_TEMP);
-}
-DECLARE_HOOK(HOOK_SECOND, chip_temp_sensor_poll, HOOK_PRIO_TEMP_SENSOR);
-
-int chip_temp_sensor_get_val(int idx, int *temp_ptr)
-{
-	if (last_val == ADC_READ_ERROR)
-		return EC_ERROR_UNKNOWN;
-
-	*temp_ptr = last_val;
-
-	return EC_SUCCESS;
-}
diff --git a/chip/lm4/clock.c b/chip/lm4/clock.c
deleted file mode 100644
index 39800c9034..0000000000
--- a/chip/lm4/clock.c
+++ /dev/null
@@ -1,754 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks and power management settings */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "uart.h"
-#include "util.h"
-#include "watchdog.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
-
-#define PLL_CLOCK 66666667  /* System clock = 200MHz PLL/3 = 66.667MHz */
-
-#ifdef CONFIG_LOW_POWER_USE_LFIOSC
-/*
- * Length of time for the processor to wake up from deep sleep. Actual
- * measurement gives anywhere up to 780us, depending on the mode it is coming
- * out of. The datasheet gives a maximum of 846us, for coming out of deep
- * sleep in our worst case deep sleep mode.
- */
-#define DEEP_SLEEP_RECOVER_TIME_USEC 850
-#else
-/*
- * Length of time for the processor to wake up from deep sleep. Datasheet
- * maximum is 145us, but in practice have seen as much as 336us.
- */
-#define DEEP_SLEEP_RECOVER_TIME_USEC 400
-#endif
-
-/* Low power idle statistics */
-#ifdef CONFIG_LOW_POWER_IDLE
-static int idle_sleep_cnt;
-static int idle_dsleep_cnt;
-static uint64_t idle_dsleep_time_us;
-static int dsleep_recovery_margin_us = 1000000;
-
-/*
- * Fixed amount of time to keep the console in use flag true after boot in
- * order to give a permanent window in which the low speed clock is not used.
- */
-#define CONSOLE_IN_USE_ON_BOOT_TIME (15*SECOND)
-
-static int console_in_use_timeout_sec = 60;
-static timestamp_t console_expire_time;
-#endif
-
-static int freq;
-
-/**
- * Disable the PLL; run off internal oscillator.
- */
-static void disable_pll(void)
-{
-	/* Switch to 16MHz internal oscillator and power down the PLL */
-	LM4_SYSTEM_RCC = LM4_SYSTEM_RCC_SYSDIV(0) |
-		LM4_SYSTEM_RCC_BYPASS |
-		LM4_SYSTEM_RCC_PWRDN |
-		LM4_SYSTEM_RCC_OSCSRC(1) |
-		LM4_SYSTEM_RCC_MOSCDIS;
-
-#ifdef CONFIG_LOW_POWER_IDLE
-	/*
-	 * If using the low power idle, then set the ACG bit, which specifies
-	 * that the sleep and deep sleep modes are using their own clock gating
-	 * registers SCGC and DCGS respectively instead of using the run mode
-	 * clock gating registers RCGC.
-	 */
-	LM4_SYSTEM_RCC |= LM4_SYSTEM_RCC_ACG;
-#endif
-
-	LM4_SYSTEM_RCC2 &= ~LM4_SYSTEM_RCC2_USERCC2;
-
-	freq = INTERNAL_CLOCK;
-}
-
-/**
- * Enable the PLL to run at full clock speed.
- */
-static void enable_pll(void)
-{
-	/* Disable the PLL so we can reconfigure it */
-	disable_pll();
-
-	/*
-	 * Enable the PLL (PWRDN is no longer set) and set divider.  PLL is
-	 * still bypassed, since it hasn't locked yet.
-	 */
-	LM4_SYSTEM_RCC = LM4_SYSTEM_RCC_SYSDIV(2) |
-		LM4_SYSTEM_RCC_USESYSDIV |
-		LM4_SYSTEM_RCC_BYPASS |
-		LM4_SYSTEM_RCC_OSCSRC(1) |
-		LM4_SYSTEM_RCC_MOSCDIS;
-
-#ifdef CONFIG_LOW_POWER_IDLE
-	/*
-	 * If using the low power idle, then set the ACG bit, which specifies
-	 * that the sleep and deep sleep modes are using their own clock gating
-	 * registers SCGC and DCGS respectively instead of using the run mode
-	 * clock gating registers RCGC.
-	 */
-	LM4_SYSTEM_RCC |= LM4_SYSTEM_RCC_ACG;
-#endif
-
-	/* Wait for the PLL to lock */
-	clock_wait_cycles(1024);
-	while (!(LM4_SYSTEM_PLLSTAT & 1))
-		;
-
-	/* Remove bypass on PLL */
-	LM4_SYSTEM_RCC &= ~LM4_SYSTEM_RCC_BYPASS;
-	freq = PLL_CLOCK;
-}
-
-void clock_enable_pll(int enable, int notify)
-{
-	if (enable)
-		enable_pll();
-	else
-		disable_pll();
-
-	/* Notify modules of frequency change */
-	if (notify)
-		hook_notify(HOOK_FREQ_CHANGE);
-}
-
-void clock_wait_cycles(uint32_t cycles)
-{
-	asm volatile("1: subs %0, #1\n"
-		     "   bne 1b\n" : "+r"(cycles));
-}
-
-int clock_get_freq(void)
-{
-	return freq;
-}
-
-void clock_init(void)
-{
-#ifdef BOARD_BDS
-	/*
-	 * Perform an auto calibration of the internal oscillator using the
-	 * 32.768KHz hibernate clock, unless we've already done so.  This is
-	 * only necessary on A2 silicon as on BDS; A3 silicon is all
-	 * factory-trimmed.
-	 */
-	if ((LM4_SYSTEM_PIOSCSTAT & 0x300) != 0x100) {
-		/* Start calibration */
-		LM4_SYSTEM_PIOSCCAL = 0x80000000;
-		LM4_SYSTEM_PIOSCCAL = 0x80000200;
-		/* Wait for result */
-		clock_wait_cycles(16);
-		while (!(LM4_SYSTEM_PIOSCSTAT & 0x300))
-			;
-	}
-#else
-	/*
-	 * Only BDS has an external crystal; other boards don't have one, and
-	 * can disable main oscillator control to reduce power consumption.
-	 */
-	LM4_SYSTEM_MOSCCTL = 0x04;
-#endif
-
-	/* Make sure PLL is disabled */
-	disable_pll();
-}
-
-void clock_enable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode)
-{
-	if (mode & CGC_MODE_RUN)
-		*(LM4_SYSTEM_RCGC_BASE + offset) |= mask;
-
-	if (mode & CGC_MODE_SLEEP)
-		*(LM4_SYSTEM_SCGC_BASE + offset) |= mask;
-
-	if (mode & CGC_MODE_DSLEEP)
-		*(LM4_SYSTEM_DCGC_BASE + offset) |= mask;
-
-	/* Wait for clock change to take affect. */
-	clock_wait_cycles(3);
-}
-
-void clock_disable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode)
-{
-	if (mode & CGC_MODE_RUN)
-		*(LM4_SYSTEM_RCGC_BASE + offset) &= ~mask;
-
-	if (mode & CGC_MODE_SLEEP)
-		*(LM4_SYSTEM_SCGC_BASE + offset) &= ~mask;
-
-	if (mode & CGC_MODE_DSLEEP)
-		*(LM4_SYSTEM_DCGC_BASE + offset) &= ~mask;
-}
-
-/*
- * The low power idle task does not support using the EEPROM,
- * because it is dangerous to go to deep sleep while EEPROM
- * transaction is in progress. To fix, LM4_EEPROM_EEDONE, should
- * be checked before going in to deep sleep.
- */
-#if defined(CONFIG_LOW_POWER_IDLE) && defined(CONFIG_EEPROM)
-#error "Low power idle mode does not support use of EEPROM"
-#endif
-
-#ifdef CONFIG_LOW_POWER_IDLE
-
-void clock_refresh_console_in_use(void)
-{
-	disable_sleep(SLEEP_MASK_CONSOLE);
-
-	/* Set console in use expire time. */
-	console_expire_time = get_time();
-	console_expire_time.val += console_in_use_timeout_sec * SECOND;
-
-}
-
-/* Low power idle task.  Executed when no tasks are ready to be scheduled. */
-void __idle(void)
-{
-	timestamp_t t0, t1, rtc_t0, rtc_t1;
-	int next_delay = 0;
-	int time_for_dsleep, margin_us;
-	int use_low_speed_clock;
-
-	/* Enable the hibernate IRQ used to wake up from deep sleep */
-	system_enable_hib_interrupt();
-
-	/* Set SRAM and flash power management to 'low power' in deep sleep. */
-	LM4_SYSTEM_DSLPPWRCFG = 0x23;
-
-	/* Enable JTAG interrupt which will notify us when JTAG is in use. */
-	gpio_enable_interrupt(GPIO_JTAG_TCK);
-
-	/*
-	 * Initialize console in use to true and specify the console expire
-	 * time in order to give a fixed window on boot in which the low speed
-	 * clock will not be used in idle.
-	 */
-	disable_sleep(SLEEP_MASK_CONSOLE);
-	console_expire_time.val = get_time().val + CONSOLE_IN_USE_ON_BOOT_TIME;
-
-	/*
-	 * Print when the idle task starts.  This is the lowest priority task,
-	 * so this only starts once all other tasks have gotten a chance to do
-	 * their task inits and have gone to sleep.
-	 */
-	CPRINTS("low power idle task started");
-
-	while (1) {
-		/*
-		 * Disable interrupts before going to deep sleep in order to
-		 * calculate the appropriate time to wake up. Note: the wfi
-		 * instruction waits until an interrupt is pending, so it
-		 * will still wake up even with interrupts disabled.
-		 */
-		interrupt_disable();
-
-		t0 = get_time();
-		next_delay = __hw_clock_event_get() - t0.le.lo;
-
-		/* Do we have enough time before next event to deep sleep. */
-		time_for_dsleep = next_delay > (DEEP_SLEEP_RECOVER_TIME_USEC +
-						HIB_SET_RTC_MATCH_DELAY_USEC);
-
-		if (DEEP_SLEEP_ALLOWED && time_for_dsleep) {
-			/* Deep-sleep in STOP mode. */
-			idle_dsleep_cnt++;
-
-			/* Check if the console use has expired. */
-			if ((sleep_mask & SLEEP_MASK_CONSOLE) &&
-					t0.val > console_expire_time.val) {
-				/* Enable low speed deep sleep. */
-				enable_sleep(SLEEP_MASK_CONSOLE);
-
-				/*
-				 * Wait one clock before checking if low speed
-				 * deep sleep is allowed to give time for
-				 * sleep mask to update.
-				 */
-				clock_wait_cycles(1);
-
-				if (LOW_SPEED_DEEP_SLEEP_ALLOWED)
-					CPRINTS("Disabling console in "
-						"deep sleep");
-			}
-
-			/*
-			 * Determine if we should use a lower clock speed or
-			 * keep the same (16MHz) clock in deep sleep. Use the
-			 * lower speed only if the sleep mask specifies that low
-			 * speed sleep is allowed, the console UART TX is not
-			 * busy, and the console UART buffer is empty.
-			 */
-			use_low_speed_clock = LOW_SPEED_DEEP_SLEEP_ALLOWED &&
-				!uart_tx_in_progress() && uart_buffer_empty();
-
-#ifdef CONFIG_LOW_POWER_USE_LFIOSC
-			/* Set the deep sleep clock register. Use either the
-			 *  normal PIOSC (16MHz) or the LFIOSC (32kHz). */
-			LM4_SYSTEM_DSLPCLKCFG = use_low_speed_clock ?
-					0x32 : 0x10;
-#else
-			/*
-			 * Set the deep sleep clock register. Use either the
-			 * PIOSC with no divider (16MHz) or the PIOSC with
-			 * a /64 divider (250kHz).
-			 */
-			LM4_SYSTEM_DSLPCLKCFG = use_low_speed_clock ?
-					0x1f800010 : 0x10;
-#endif
-
-			/*
-			 * If using low speed clock, disable console.
-			 * This will also convert the console RX pin to a GPIO
-			 * and set an edge interrupt to wake us from deep sleep
-			 * if any action occurs on console.
-			 */
-			if (use_low_speed_clock)
-				uart_enter_dsleep();
-
-			/* Set deep sleep bit. */
-			CPU_SCB_SYSCTRL |= 0x4;
-
-			/* Record real time before sleeping. */
-			rtc_t0 = system_get_rtc();
-
-			/*
-			 * Set RTC interrupt in time to wake up before
-			 * next event.
-			 */
-			system_set_rtc_alarm(0, next_delay -
-						DEEP_SLEEP_RECOVER_TIME_USEC);
-
-			/* Wait for interrupt: goes into deep sleep. */
-			asm("wfi");
-
-			/* Clear deep sleep bit. */
-			CPU_SCB_SYSCTRL &= ~0x4;
-
-			/* Disable and clear RTC interrupt. */
-			system_reset_rtc_alarm();
-
-			/* Fast forward timer according to RTC counter. */
-			rtc_t1 = system_get_rtc();
-			t1.val = t0.val + (rtc_t1.val - rtc_t0.val);
-			force_time(t1);
-
-			/* If using low speed clock, re-enable the console. */
-			if (use_low_speed_clock)
-				uart_exit_dsleep();
-
-			/* Record time spent in deep sleep. */
-			idle_dsleep_time_us += (rtc_t1.val - rtc_t0.val);
-
-			/* Calculate how close we were to missing deadline */
-			margin_us = next_delay - (int)(rtc_t1.val - rtc_t0.val);
-			if (margin_us < 0)
-				CPRINTS("overslept by %dus", -margin_us);
-
-			/* Record the closest to missing a deadline. */
-			if (margin_us < dsleep_recovery_margin_us)
-				dsleep_recovery_margin_us = margin_us;
-		} else {
-			idle_sleep_cnt++;
-
-			/* Normal idle : only CPU clock stopped. */
-			asm("wfi");
-		}
-		interrupt_enable();
-	}
-}
-#endif /* CONFIG_LOW_POWER_IDLE */
-
-/*****************************************************************************/
-/* Console commands */
-
-#ifdef CONFIG_CMD_SLEEP
-/**
- * Measure baseline for power consumption.
- *
- * Levels :
- *   0 : CPU running in tight loop
- *   1 : CPU running in tight loop but peripherals gated
- *   2 : CPU in sleep mode
- *   3 : CPU in sleep mode and peripherals gated
- *   4 : CPU in deep sleep mode
- *   5 : CPU in deep sleep mode and peripherals gated
- *
- * Clocks :
- *   0 : No change
- *   1 : 16MHz
- *   2 : 1 MHz
- *   3 : 30kHz
- *
- * SRAM Power Management:
- *   0 : Active
- *   1 : Standby
- *   3 : Low Power
- *
- * Flash Power Management:
- *   0 : Active
- *   2 : Low Power
- */
-static int command_sleep(int argc, char **argv)
-{
-	int level = 0;
-	int clock = 0;
-	int sram_pm = 0;
-	int flash_pm = 0;
-	uint32_t uartibrd = 0;
-	uint32_t uartfbrd = 0;
-
-	if (argc >= 2)
-		level = strtoi(argv[1], NULL, 10);
-	if (argc >= 3)
-		clock = strtoi(argv[2], NULL, 10);
-	if (argc >= 4)
-		sram_pm = strtoi(argv[3], NULL, 10);
-	if (argc >= 5)
-		flash_pm = strtoi(argv[4], NULL, 10);
-
-#ifdef BOARD_BDS
-	/* Remove LED current sink. */
-	gpio_set_level(GPIO_DEBUG_LED, 0);
-#endif
-
-	ccprintf("Sleep : level %d, clock %d, sram pm %d, flash_pm %d...\n",
-			level, clock, sram_pm, flash_pm);
-	cflush();
-
-	/* Set clock speed. */
-	if (clock) {
-		/* Use ROM code function to set the clock */
-		void **func_table = (void **)*(uint32_t *)0x01000044;
-		void (*rom_clock_set)(uint32_t rcc) = func_table[23];
-
-		/* Disable interrupts. */
-		asm volatile("cpsid i");
-
-		switch (clock) {
-		case 1: /* 16MHz IOSC */
-			uartibrd = 17;
-			uartfbrd = 23;
-			rom_clock_set(0x00000d51);
-			break;
-		case 2: /* 1MHz IOSC */
-			uartibrd = 1;
-			uartfbrd = 5;
-			rom_clock_set(0x07C00d51);
-			break;
-		case 3: /* 30 kHz */
-			uartibrd = 0;
-			uartfbrd = 0;
-			rom_clock_set(0x00000d71);
-			break;
-		}
-
-		/*
-		 * TODO(crosbug.com/p/23795): move this to the UART module;
-		 * ugly to have UARTisms here.  Also note this only fixes
-		 * UART0, not UART1.  Should just be able to trigger
-		 * HOOK_FREQ_CHANGE and have that take care of it.
-		 */
-		if (uartfbrd) {
-			/* Disable the port via UARTCTL and add HSE. */
-			LM4_UART_CTL(0) = 0x0320;
-			/* Set the baud rate divisor. */
-			LM4_UART_IBRD(0) = uartibrd;
-			LM4_UART_FBRD(0) = uartfbrd;
-			/* Poke UARTLCRH to make the new divisor take effect. */
-			LM4_UART_LCRH(0) = LM4_UART_LCRH(0);
-			/* Enable the port. */
-			LM4_UART_CTL(0) |= 0x0001;
-		}
-		asm volatile("cpsie i");
-	}
-
-	if (uartfbrd) {
-		ccprintf("We are still alive. RCC=%08x\n", LM4_SYSTEM_RCC);
-		cflush();
-	}
-
-	/* Enable interrupts. */
-	asm volatile("cpsid i");
-
-	/* gate peripheral clocks */
-	if (level & 1) {
-		clock_disable_peripheral(CGC_OFFSET_WD,     0xffffffff,
-				CGC_MODE_ALL);
-		clock_disable_peripheral(CGC_OFFSET_TIMER,  0xffffffff,
-				CGC_MODE_ALL);
-		clock_disable_peripheral(CGC_OFFSET_GPIO,   0xffffffff,
-				CGC_MODE_ALL);
-		clock_disable_peripheral(CGC_OFFSET_DMA,    0xffffffff,
-				CGC_MODE_ALL);
-		clock_disable_peripheral(CGC_OFFSET_HIB,    0xffffffff,
-				CGC_MODE_ALL);
-		clock_disable_peripheral(CGC_OFFSET_UART,   0xffffffff,
-				CGC_MODE_ALL);
-		clock_disable_peripheral(CGC_OFFSET_SSI,    0xffffffff,
-				CGC_MODE_ALL);
-		clock_disable_peripheral(CGC_OFFSET_I2C,    0xffffffff,
-				CGC_MODE_ALL);
-		clock_disable_peripheral(CGC_OFFSET_ADC,    0xffffffff,
-				CGC_MODE_ALL);
-		clock_disable_peripheral(CGC_OFFSET_LPC,    0xffffffff,
-				CGC_MODE_ALL);
-		clock_disable_peripheral(CGC_OFFSET_PECI,   0xffffffff,
-				CGC_MODE_ALL);
-		clock_disable_peripheral(CGC_OFFSET_FAN,    0xffffffff,
-				CGC_MODE_ALL);
-		clock_disable_peripheral(CGC_OFFSET_EEPROM, 0xffffffff,
-				CGC_MODE_ALL);
-		clock_disable_peripheral(CGC_OFFSET_WTIMER, 0xffffffff,
-				CGC_MODE_ALL);
-	}
-
-	/* Set deep sleep bit. */
-	if (level >= 4)
-		CPU_SCB_SYSCTRL |= 0x4;
-
-	/* Set SRAM and flash PM for sleep and deep sleep. */
-	LM4_SYSTEM_SLPPWRCFG = (flash_pm << 4) | sram_pm;
-	LM4_SYSTEM_DSLPPWRCFG = (flash_pm << 4) | sram_pm;
-
-	/* Go to low power mode (forever ...) */
-	if (level > 1)
-		while (1) {
-			asm("wfi");
-			watchdog_reload();
-		}
-	else
-		while (1)
-			watchdog_reload();
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(sleep, command_sleep,
-			"[level [clock] [sram pm] [flash pm]]",
-			"Drop into sleep");
-#endif /* CONFIG_CMD_SLEEP */
-
-#ifdef CONFIG_CMD_PLL
-
-static int command_pll(int argc, char **argv)
-{
-	int v;
-
-	/* Toggle the PLL */
-	if (argc > 1) {
-		if (parse_bool(argv[1], &v)) {
-			clock_enable_pll(v, 1);
-		} else {
-			/* Disable PLL and set extra divider */
-			char *e;
-			v = strtoi(argv[1], &e, 10);
-			if (*e)
-				return EC_ERROR_PARAM1;
-
-			LM4_SYSTEM_RCC = LM4_SYSTEM_RCC_SYSDIV(v - 1) |
-				LM4_SYSTEM_RCC_BYPASS |
-				LM4_SYSTEM_RCC_PWRDN |
-				LM4_SYSTEM_RCC_OSCSRC(1) |
-				LM4_SYSTEM_RCC_MOSCDIS;
-
-			freq = INTERNAL_CLOCK / v;
-
-			/* Notify modules of frequency change */
-			hook_notify(HOOK_FREQ_CHANGE);
-		}
-	}
-
-	/* Print current PLL state */
-	ccprintf("RCC:     0x%08x\n", LM4_SYSTEM_RCC);
-	ccprintf("RCC2:    0x%08x\n", LM4_SYSTEM_RCC2);
-	ccprintf("PLLSTAT: 0x%08x\n", LM4_SYSTEM_PLLSTAT);
-	ccprintf("Clock:   %d Hz\n", clock_get_freq());
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(pll, command_pll,
-			"[ on | off | <div> ]",
-			"Get/set PLL state");
-
-#endif /* CONFIG_CMD_PLL */
-
-#ifdef CONFIG_CMD_CLOCKGATES
-/**
- * Print all clock gating registers
- */
-static int command_clock_gating(int argc, char **argv)
-{
-	ccprintf("         Run       , Sleep     , Deep Sleep\n");
-
-	ccprintf("WD:      0x%08x, ",
-				*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_WD));
-	ccprintf("0x%08x, ",	*(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_WD));
-	ccprintf("0x%08x\n",	*(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_WD));
-
-	ccprintf("TIMER:   0x%08x, ",
-				*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_TIMER));
-	ccprintf("0x%08x, ",	*(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_TIMER));
-	ccprintf("0x%08x\n",	*(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_TIMER));
-
-	ccprintf("GPIO:    0x%08x, ",
-				*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_GPIO));
-	ccprintf("0x%08x, ",	*(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_GPIO));
-	ccprintf("0x%08x\n",	*(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_GPIO));
-
-	ccprintf("DMA:     0x%08x, ",
-				*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_DMA));
-	ccprintf("0x%08x, ",	*(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_DMA));
-	ccprintf("0x%08x\n",	*(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_DMA));
-
-	ccprintf("HIB:     0x%08x, ",
-				*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_HIB));
-	ccprintf("0x%08x, ",	*(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_HIB));
-	ccprintf("0x%08x\n",	*(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_HIB));
-
-	ccprintf("UART:    0x%08x, ",
-				*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_UART));
-	ccprintf("0x%08x, ",	*(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_UART));
-	ccprintf("0x%08x\n",	*(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_UART));
-
-	ccprintf("SSI:     0x%08x, ",
-				*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_SSI));
-	ccprintf("0x%08x, ",	*(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_SSI));
-	ccprintf("0x%08x\n",	*(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_SSI));
-
-	ccprintf("I2C:     0x%08x, ",
-				*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_I2C));
-	ccprintf("0x%08x, ",	*(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_I2C));
-	ccprintf("0x%08x\n",	*(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_I2C));
-
-	ccprintf("ADC:     0x%08x, ",
-				*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_ADC));
-	ccprintf("0x%08x, ",	*(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_ADC));
-	ccprintf("0x%08x\n",	*(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_ADC));
-
-	ccprintf("LPC:     0x%08x, ",
-				*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_LPC));
-	ccprintf("0x%08x, ",	*(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_LPC));
-	ccprintf("0x%08x\n",	*(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_LPC));
-
-	ccprintf("PECI:    0x%08x, ",
-				*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_PECI));
-	ccprintf("0x%08x, ",	*(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_PECI));
-	ccprintf("0x%08x\n",	*(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_PECI));
-
-	ccprintf("FAN:     0x%08x, ",
-				*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_FAN));
-	ccprintf("0x%08x, ",	*(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_FAN));
-	ccprintf("0x%08x\n",	*(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_FAN));
-
-	ccprintf("EEPROM:  0x%08x, ",
-				*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_EEPROM));
-	ccprintf("0x%08x, ",	*(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_EEPROM));
-	ccprintf("0x%08x\n",	*(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_EEPROM));
-
-	ccprintf("WTIMER:  0x%08x, ",
-				*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_WTIMER));
-	ccprintf("0x%08x, ",	*(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_WTIMER));
-	ccprintf("0x%08x\n",	*(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_WTIMER));
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(clockgates, command_clock_gating,
-			"",
-			"Get state of the clock gating controls regs");
-#endif /* CONFIG_CMD_CLOCKGATES */
-
-#ifdef CONFIG_LOW_POWER_IDLE
-/**
- * Print low power idle statistics
- */
-static int command_idle_stats(int argc, char **argv)
-{
-	timestamp_t ts = get_time();
-
-	ccprintf("Num idle calls that sleep:           %d\n", idle_sleep_cnt);
-	ccprintf("Num idle calls that deep-sleep:      %d\n", idle_dsleep_cnt);
-	ccprintf("Time spent in deep-sleep:            %.6llds\n",
-			idle_dsleep_time_us);
-	ccprintf("Total time on:                       %.6llds\n", ts.val);
-	ccprintf("Deep-sleep closest to wake deadline: %dus\n",
-			dsleep_recovery_margin_us);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats,
-			"",
-			"Print last idle stats");
-
-/**
- * Configure deep sleep clock settings.
- */
-static int command_dsleep(int argc, char **argv)
-{
-	int v;
-
-	if (argc > 1) {
-		if (parse_bool(argv[1], &v)) {
-			/*
-			 * Force deep sleep not to use low speed clock or
-			 * allow it to use the low speed clock.
-			 */
-			if (v)
-				disable_sleep(SLEEP_MASK_FORCE_NO_LOW_SPEED);
-			else
-				enable_sleep(SLEEP_MASK_FORCE_NO_LOW_SPEED);
-		} else {
-			/* Set console in use timeout. */
-			char *e;
-			v = strtoi(argv[1], &e, 10);
-			if (*e)
-				return EC_ERROR_PARAM1;
-
-			console_in_use_timeout_sec = v;
-
-			/* Refresh console in use to use new timeout. */
-			clock_refresh_console_in_use();
-		}
-	}
-
-	ccprintf("Sleep mask: %08x\n", sleep_mask);
-	ccprintf("Console in use timeout:   %d sec\n",
-			console_in_use_timeout_sec);
-	ccprintf("DSLPCLKCFG register:      0x%08x\n", LM4_SYSTEM_DSLPCLKCFG);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(dsleep, command_dsleep,
-			"[ on | off | <timeout> sec]",
-			"Deep sleep clock settings:\nUse 'on' to force deep "
-			"sleep not to use low speed clock.\nUse 'off' to "
-			"allow deep sleep to auto-select using the low speed "
-			"clock.\n"
-			"Give a timeout value for the console in use timeout.\n"
-			"See also 'sleepmask'.");
-#endif /* CONFIG_LOW_POWER_IDLE */
-
diff --git a/chip/lm4/config_chip.h b/chip/lm4/config_chip.h
deleted file mode 100644
index 8abe059e5b..0000000000
--- a/chip/lm4/config_chip.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_CHIP_H
-#define __CROS_EC_CONFIG_CHIP_H
-
-/* CPU core BFD configuration */
-#include "core/cortex-m/config_core.h"
-
-/* 16.000 MHz internal oscillator frequency (PIOSC) */
-#define INTERNAL_CLOCK 16000000
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT 132
-
-/* Use a bigger console output buffer */
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 8192
-
-/* Interval between HOOK_TICK notifications */
-#define HOOK_TICK_INTERVAL_MS 250
-#define HOOK_TICK_INTERVAL    (HOOK_TICK_INTERVAL_MS * MSEC)
-
-/* Number of I2C ports */
-#define I2C_PORT_COUNT 6
-
-/*
- * Time it takes to set the RTC match register. This value is conservatively
- * set based on measurements around 200us.
- */
-#define HIB_SET_RTC_MATCH_DELAY_USEC 300
-
-/****************************************************************************/
-/* Memory mapping */
-
-#define CONFIG_RAM_BASE             0x20000000
-#define CONFIG_RAM_SIZE             0x00008000
-
-/* System stack size */
-#define CONFIG_STACK_SIZE           4096
-
-/* non-standard task stack sizes */
-#define IDLE_TASK_STACK_SIZE        512
-#define LARGER_TASK_STACK_SIZE      768
-#define SMALLER_TASK_STACK_SIZE     384
-
-/* Default task stack size */
-#define TASK_STACK_SIZE             512
-
-#define CONFIG_PROGRAM_MEMORY_BASE  0x00000000
-#define CONFIG_FLASH_BANK_SIZE      0x00000800  /* protect bank size */
-#define CONFIG_FLASH_ERASE_SIZE     0x00000400  /* erase bank size */
-#define CONFIG_FLASH_WRITE_SIZE     0x00000004  /* minimum write size */
-
-/* Ideal flash write size fills the 32-entry flash write buffer */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE (32 * 4)
-
-/* This is the physical size of the flash on the chip. We'll reserve one bank
- * in order to emulate per-bank write-protection UNTIL REBOOT. The hardware
- * doesn't support a write-protect pin, and if we make the write-protection
- * permanent, it can't be undone easily enough to support RMA. */
-#define CONFIG_FLASH_SIZE  0x00040000
-
-/****************************************************************************/
-/* Define our flash layout. */
-
-/* Memory-mapped internal flash */
-#define CONFIG_INTERNAL_STORAGE
-#define CONFIG_MAPPED_STORAGE
-
-/* Program is run directly from storage */
-#define CONFIG_MAPPED_STORAGE_BASE CONFIG_PROGRAM_MEMORY_BASE
-
-/* Compute the rest of the flash params from these */
-#include "config_std_internal_flash.h"
-
-/****************************************************************************/
-/* Lock the boot configuration to prevent brickage. */
-
-/*
- * No GPIO trigger for ROM bootloader.
- * Keep JTAG debugging enabled.
- * Use 0xA442 flash write key.
- * Lock it this way.
- */
-#define CONFIG_BOOTCFG_VALUE 0x7ffffffe
-
-/****************************************************************************/
-/* Customize the build */
-
-/* Optional features present on this chip */
-#define CONFIG_ADC
-#define CONFIG_HOSTCMD_ALIGNED
-#define CONFIG_HOSTCMD_LPC
-#define CONFIG_PECI
-#define CONFIG_RTC
-#define CONFIG_SWITCH
-#define CONFIG_MPU
-
-/* Chip needs to do custom pre-init */
-#define CONFIG_CHIP_PRE_INIT
-
-#define GPIO_PIN(port, index) GPIO_##port, BIT(index)
-#define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m)
-
-#endif  /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/chip/lm4/eeprom.c b/chip/lm4/eeprom.c
deleted file mode 100644
index 97fd3bdc24..0000000000
--- a/chip/lm4/eeprom.c
+++ /dev/null
@@ -1,268 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* EEPROM module for Chrome EC */
-
-#include "clock.h"
-#include "console.h"
-#include "eeprom.h"
-#include "registers.h"
-#include "timer.h"
-#include "util.h"
-#include "watchdog.h"
-
-/* Size of EEPROM block in bytes */
-#define EEPROM_BLOCK_SIZE 64
-
-/* Count of EEPROM blocks */
-static int block_count;
-
-/*
- * Wait for the current EEPROM operation to finish; all operations but write
- * should normally finish in 4 system clocks, but worst case is up to
- * 1800ms if the EEPROM needs to do an internal page erase/copy.  We must
- * spin-wait for this delay, because EEPROM operations will fail if the chip
- * drops to sleep mode.
- */
-static int wait_for_done(void)
-{
-	int j;
-
-	for (j = 0; j < 20; j++) {  /* 20 * 100 ms = 2000 ms */
-		uint64_t tstop = get_time().val + 100 * MSEC;
-		while (get_time().val < tstop) {
-			if (!(LM4_EEPROM_EEDONE & 0x01))
-				return EC_SUCCESS;
-		}
-		watchdog_reload();
-	}
-
-	return EC_ERROR_UNKNOWN;
-}
-
-
-int eeprom_get_block_count(void)
-{
-	return block_count;
-}
-
-
-int eeprom_get_block_size(void)
-{
-	return EEPROM_BLOCK_SIZE;
-}
-
-
-int eeprom_read(int block, int offset, int size, char *data)
-{
-	uint32_t *d = (uint32_t *)data;
-	int rv;
-
-	if (block < 0 || block >= block_count ||
-	    offset < 0 || offset > EEPROM_BLOCK_SIZE || offset & 3 ||
-	    size < 0 || offset + size > EEPROM_BLOCK_SIZE || size & 3)
-		return EC_ERROR_UNKNOWN;
-
-	rv = wait_for_done();
-	if (rv)
-		return rv;
-
-	LM4_EEPROM_EEBLOCK = block;
-	if (LM4_EEPROM_EEBLOCK != block)
-		return EC_ERROR_UNKNOWN;  /* Error setting block */
-
-	LM4_EEPROM_EEOFFSET = offset >> 2;
-
-	for (; size; size -= sizeof(uint32_t))
-		*(d++) = LM4_EEPROM_EERDWRINC;
-
-	return EC_SUCCESS;
-}
-
-
-int eeprom_write(int block, int offset, int size, const char *data)
-{
-	uint32_t *d = (uint32_t *)data;
-	int rv;
-
-	if (block < 0 || block >= block_count ||
-	    offset < 0 || offset > EEPROM_BLOCK_SIZE || offset & 3 ||
-	    size < 0 || offset + size > EEPROM_BLOCK_SIZE || size & 3)
-		return EC_ERROR_UNKNOWN;
-
-	rv = wait_for_done();
-	if (rv)
-		return rv;
-
-	LM4_EEPROM_EEBLOCK = block;
-	if (LM4_EEPROM_EEBLOCK != block)
-		return EC_ERROR_UNKNOWN;  /* Error setting block */
-
-	LM4_EEPROM_EEOFFSET = offset >> 2;
-
-	/* Write 32 bits at a time; wait for each write to complete */
-	for (; size; size -= sizeof(uint32_t)) {
-		LM4_EEPROM_EERDWRINC = *(d++);
-
-		rv = wait_for_done();
-		if (rv)
-			return rv;
-
-		if (LM4_EEPROM_EEDONE & 0x10) {
-			/* Failed due to write protect */
-			return EC_ERROR_ACCESS_DENIED;
-		} else if (LM4_EEPROM_EEDONE & 0x100) {
-			/* Failed due to program voltage level */
-			return EC_ERROR_UNKNOWN;
-		}
-	}
-
-	return EC_SUCCESS;
-}
-
-
-int eeprom_hide(int block)
-{
-	/* Block 0 can't be hidden */
-	if (block <= 0 || block >= block_count)
-		return EC_ERROR_UNKNOWN;
-
-	LM4_EEPROM_EEHIDE |= 1 << block;
-	return EC_SUCCESS;
-}
-
-
-/*****************************************************************************/
-/* Console commands */
-
-static int command_eeprom_info(int argc, char **argv)
-{
-	ccprintf("%d blocks @ %d bytes, hide=0x%08x\n",
-		 eeprom_get_block_count(), eeprom_get_block_size(),
-		 LM4_EEPROM_EEHIDE);
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(eeinfo, command_eeprom_info,
-			NULL,
-			"Print EEPROM info");
-
-
-static int command_eeprom_read(int argc, char **argv)
-{
-	int block = 0;
-	int offset = 0;
-	char *e;
-	int rv;
-	uint32_t d;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	block = strtoi(argv[1], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM1;
-
-	if (argc > 2) {
-		offset = strtoi(argv[2], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM2;
-	}
-
-	rv = eeprom_read(block, offset, sizeof(d), (char *)&d);
-	if (rv == EC_SUCCESS)
-		ccprintf("%d:%d = 0x%08x\n", block, offset, d);
-	return rv;
-}
-DECLARE_CONSOLE_COMMAND(eeread, command_eeprom_read,
-			"block [offset]",
-			"Read a word of EEPROM");
-
-
-static int command_eeprom_write(int argc, char **argv)
-{
-	int block = 0;
-	int offset = 0;
-	char *e;
-	uint32_t d;
-
-	if (argc < 4)
-		return EC_ERROR_PARAM_COUNT;
-
-	block = strtoi(argv[1], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM1;
-	offset = strtoi(argv[2], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM2;
-	d = strtoi(argv[3], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM3;
-
-	ccprintf("Writing 0x%08x to %d:%d...\n", d, block, offset);
-	return eeprom_write(block, offset, sizeof(d), (char *)&d);
-}
-DECLARE_CONSOLE_COMMAND(eewrite, command_eeprom_write,
-			"block offset value",
-			"Write a word of EEPROM");
-
-
-#ifdef CONSOLE_COMMAND_EEHIDE
-static int command_eeprom_hide(int argc, char **argv)
-{
-	int block = 0;
-	char *e;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	block = strtoi(argv[1], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM1;
-
-	ccprintf("Hiding block %d\n", block);
-	return eeprom_hide(block);
-}
-DECLARE_CONSOLE_COMMAND(eehide, command_eeprom_hide,
-			"block",
-			"Hide a block of EEPROM");
-#endif
-
-
-/*****************************************************************************/
-/* Initialization */
-
-
-int eeprom_init(void)
-{
-	/* Enable the EEPROM module in run and sleep modes. */
-	clock_enable_peripheral(CGC_OFFSET_EEPROM, 0x1,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-
-	/* Wait for internal EEPROM init to finish */
-	wait_for_done();
-
-	/* Store block count */
-	block_count = LM4_EEPROM_EESIZE >> 16;
-
-	/*
-	 * Handle resetting the EEPROM module to clear state from a previous
-	 * error condition.
-	 */
-	if (LM4_EEPROM_EESUPP & 0xc0) {
-		LM4_SYSTEM_SREEPROM = 1;
-		clock_wait_cycles(200);
-		LM4_SYSTEM_SREEPROM = 0;
-
-		/* Wait again for internal init to finish */
-		clock_wait_cycles(6);
-		wait_for_done();
-
-		/* Fail if error condition didn't clear */
-		if (LM4_EEPROM_EESUPP & 0xc0)
-			return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
diff --git a/chip/lm4/fan.c b/chip/lm4/fan.c
deleted file mode 100644
index b09323a37b..0000000000
--- a/chip/lm4/fan.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* LM4 fan control module. */
-
-#include "clock.h"
-#include "fan.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "util.h"
-
-/* Maximum RPM for fan controller */
-#define MAX_RPM 0x1fff
-
-/* Maximum PWM for PWM controller */
-#define MAX_PWM 0x1ff
-
-/*
- * Scaling factor for requested/actual RPM for CPU fan.  We need this because
- * the fan controller on Blizzard filters tach pulses that are less than 64
- * 15625Hz ticks apart, which works out to ~7000rpm on an unscaled fan.  By
- * telling the controller we actually have twice as many edges per revolution,
- * the controller can handle fans that actually go twice as fast.  See
- * crosbug.com/p/7718.
- */
-#define RPM_SCALE 2
-
-
-void fan_set_enabled(int ch, int enabled)
-{
-	if (enabled)
-		LM4_FAN_FANCTL |= BIT(ch);
-	else
-		LM4_FAN_FANCTL &= ~BIT(ch);
-}
-
-int fan_get_enabled(int ch)
-{
-	return (LM4_FAN_FANCTL & BIT(ch)) ? 1 : 0;
-}
-
-void fan_set_duty(int ch, int percent)
-{
-	int duty;
-
-	if (percent < 0)
-		percent = 0;
-	else if (percent > 100)
-		percent = 100;
-
-	duty = (MAX_PWM * percent + 50) / 100;
-
-	/* Always enable the channel */
-	fan_set_enabled(ch, 1);
-
-	/* Set the duty cycle */
-	LM4_FAN_FANCMD(ch) = duty << 16;
-}
-
-int fan_get_duty(int ch)
-{
-	return ((LM4_FAN_FANCMD(ch) >> 16) * 100 + MAX_PWM / 2) / MAX_PWM;
-}
-
-int fan_get_rpm_mode(int ch)
-{
-	return (LM4_FAN_FANCH(ch) & 0x0001) ? 0 : 1;
-}
-
-void fan_set_rpm_mode(int ch, int rpm_mode)
-{
-	int was_enabled = fan_get_enabled(ch);
-	int was_rpm = fan_get_rpm_mode(ch);
-
-	if (!was_rpm && rpm_mode) {
-		/* Enable RPM control */
-		fan_set_enabled(ch, 0);
-		LM4_FAN_FANCH(ch) &= ~0x0001;
-		fan_set_enabled(ch, was_enabled);
-	} else if (was_rpm && !rpm_mode) {
-		/* Disable RPM mode */
-		fan_set_enabled(ch, 0);
-		LM4_FAN_FANCH(ch) |= 0x0001;
-		fan_set_enabled(ch, was_enabled);
-	}
-}
-
-int fan_get_rpm_actual(int ch)
-{
-	return (LM4_FAN_FANCST(ch) & MAX_RPM) * RPM_SCALE;
-}
-
-int fan_get_rpm_target(int ch)
-{
-	return (LM4_FAN_FANCMD(ch) & MAX_RPM) * RPM_SCALE;
-}
-
-test_mockable void fan_set_rpm_target(int ch, int rpm)
-{
-	/* Apply fan scaling */
-	if (rpm > 0)
-		rpm /= RPM_SCALE;
-
-	/* Treat out-of-range requests as requests for maximum fan speed */
-	if (rpm < 0 || rpm > MAX_RPM)
-		rpm = MAX_RPM;
-
-	LM4_FAN_FANCMD(ch) = rpm;
-}
-
-/* The LM4 status is the original definition of enum fan_status */
-enum fan_status fan_get_status(int ch)
-{
-	return (LM4_FAN_FANSTS >> (2 * ch)) & 0x03;
-}
-
-/**
- * Return non-zero if fan is enabled but stalled.
- */
-int fan_is_stalled(int ch)
-{
-	/* Must be enabled with non-zero target to stall */
-	if (!fan_get_enabled(ch) || fan_get_rpm_target(ch) == 0)
-		return 0;
-
-	/* Check for stall condition */
-	return fan_get_status(ch) == FAN_STATUS_STOPPED;
-}
-
-void fan_channel_setup(int ch, unsigned int flags)
-{
-	uint32_t init;
-
-	if (flags & FAN_USE_RPM_MODE)
-		/*
-		 * Configure automatic/feedback mode:
-		 * 0x8000 = bit 15     = auto-restart
-		 * 0x0000 = bit 14     = slow acceleration
-		 * 0x0000 = bits 13:11 = no hysteresis
-		 * 0x0000 = bits 10:8  = start period (2<<0) edges
-		 * 0x0000 = bits 7:6   = no fast start
-		 * 0x0020 = bits 5:4   = average 4 edges when
-		 *                       calculating RPM
-		 * 0x000c = bits 3:2   = 8 pulses per revolution
-		 *                       (see note at top of file)
-		 * 0x0000 = bit 0      = automatic control
-		 */
-		init = 0x802c;
-	else
-		/*
-		 * Configure drive-only mode:
-		 * 0x0000 = bit 15     = no auto-restart
-		 * 0x0000 = bit 14     = slow acceleration
-		 * 0x0000 = bits 13:11 = no hysteresis
-		 * 0x0000 = bits 10:8  = start period (2<<0) edges
-		 * 0x0000 = bits 7:6   = no fast start
-		 * 0x0000 = bits 5:4   = no RPM averaging
-		 * 0x0000 = bits 3:2   = 1 pulses per revolution
-		 * 0x0001 = bit 0      = manual control
-		 */
-		init = 0x0001;
-
-	if (flags & FAN_USE_FAST_START)
-		/*
-		 * Configure fast-start mode
-		 * 0x0000 = bits 10:8  = start period (2<<0) edges
-		 * 0x0040 = bits 7:6   = fast start at 50% duty
-		 */
-		init |= 0x0040;
-
-	LM4_FAN_FANCH(ch) = init;
-}
-
-static void fan_init(void)
-{
-
-#ifdef CONFIG_FAN_DSLEEP
-	/* Enable the fan module and delay a few clocks */
-	clock_enable_peripheral(CGC_OFFSET_FAN, 0x1, CGC_MODE_ALL);
-#else
-	/* Enable the fan module and delay a few clocks */
-	clock_enable_peripheral(CGC_OFFSET_FAN, 0x1,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-#endif
-	/* Disable all fans */
-	LM4_FAN_FANCTL = 0;
-}
-/* Init before PWM */
-DECLARE_HOOK(HOOK_INIT, fan_init, HOOK_PRIO_INIT_FAN);
diff --git a/chip/lm4/flash.c b/chip/lm4/flash.c
deleted file mode 100644
index 4f7e905e21..0000000000
--- a/chip/lm4/flash.c
+++ /dev/null
@@ -1,293 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Flash memory module for Chrome EC */
-
-#include "flash.h"
-#include "registers.h"
-#include "switch.h"
-#include "system.h"
-#include "timer.h"
-#include "util.h"
-#include "watchdog.h"
-
-#define FLASH_FWB_WORDS 32
-#define FLASH_FWB_BYTES (FLASH_FWB_WORDS * 4)
-
-#define BANK_SHIFT 5 /* bank registers have 32bits each, 2^32 */
-#define BANK_MASK (BIT(BANK_SHIFT) - 1) /* 5 bits */
-#define F_BANK(b) ((b) >> BANK_SHIFT)
-#define F_BIT(b) (1 << ((b) & BANK_MASK))
-
-/* Flash timeouts.  These are 2x the spec sheet max. */
-#define ERASE_TIMEOUT_MS 200
-#define WRITE_TIMEOUT_US 300
-
-int stuck_locked;  /* Is physical flash stuck protected? */
-int all_protected; /* Has all-flash protection been requested? */
-
-/**
- * Protect flash banks until reboot.
- *
- * @param start_bank    Start bank to protect
- * @param bank_count    Number of banks to protect
- */
-static void protect_banks(int start_bank, int bank_count)
-{
-	int bank;
-	for (bank = start_bank; bank < start_bank + bank_count; bank++)
-		LM4_FLASH_FMPPE[F_BANK(bank)] &= ~F_BIT(bank);
-}
-
-/**
- * Perform a write-buffer operation.  Buffer (FWB) and address (FMA) must be
- * pre-loaded.
- *
- * @return EC_SUCCESS, or nonzero if error.
- */
-static int write_buffer(void)
-{
-	int t;
-
-	if (all_protected)
-		return EC_ERROR_ACCESS_DENIED;
-
-	if (!LM4_FLASH_FWBVAL)
-		return EC_SUCCESS;  /* Nothing to do */
-
-	/* Clear previous error status */
-	LM4_FLASH_FCMISC = LM4_FLASH_FCRIS;
-
-	/* Start write operation at page boundary */
-	LM4_FLASH_FMC2 = 0xa4420001;
-
-	/*
-	 * Reload the watchdog timer, so that writing a large amount of flash
-	 * doesn't cause a watchdog reset.
-	 */
-	watchdog_reload();
-
-	/* Wait for write to complete */
-	for (t = 0; LM4_FLASH_FMC2 & 0x01; t += 10) {
-		if (t > WRITE_TIMEOUT_US)
-			return EC_ERROR_TIMEOUT;
-		udelay(10);
-	}
-
-	/* Check for error conditions - program failed, erase needed,
-	 * voltage error. */
-	if (LM4_FLASH_FCRIS & 0x2e01)
-		return EC_ERROR_UNKNOWN;
-
-	return EC_SUCCESS;
-}
-
-/*****************************************************************************/
-/* Physical layer APIs */
-
-int flash_physical_write(int offset, int size, const char *data)
-{
-	const uint32_t *data32 = (const uint32_t *)data;
-	int rv;
-	int i;
-
-	if (all_protected)
-		return EC_ERROR_ACCESS_DENIED;
-
-	/* Fail if offset, size, and data aren't at least word-aligned */
-	if ((offset | size | (uint32_t)(uintptr_t)data) & 3)
-		return EC_ERROR_INVAL;
-
-	/* Get initial write buffer index and page */
-	LM4_FLASH_FMA = offset & ~(FLASH_FWB_BYTES - 1);
-	i = (offset >> 2) & (FLASH_FWB_WORDS - 1);
-
-	/* Copy words into buffer */
-	for (; size > 0; size -= 4) {
-		LM4_FLASH_FWB[i++] = *data32++;
-		if (i == FLASH_FWB_WORDS) {
-			rv = write_buffer();
-			if (rv != EC_SUCCESS)
-				return rv;
-
-			/* Advance to next page */
-			i = 0;
-			LM4_FLASH_FMA += FLASH_FWB_BYTES;
-		}
-	}
-
-	/* Handle final partial page, if any */
-	if (i > 0)
-		return write_buffer();
-
-	return EC_SUCCESS;
-}
-
-int flash_physical_erase(int offset, int size)
-{
-	if (all_protected)
-		return EC_ERROR_ACCESS_DENIED;
-
-	LM4_FLASH_FCMISC = LM4_FLASH_FCRIS;  /* Clear previous error status */
-
-	for (; size > 0; size -= CONFIG_FLASH_ERASE_SIZE,
-		     offset += CONFIG_FLASH_ERASE_SIZE) {
-		int t;
-
-		/* Do nothing if already erased */
-		if (flash_is_erased(offset, CONFIG_FLASH_ERASE_SIZE))
-			continue;
-
-		LM4_FLASH_FMA = offset;
-
-		/*
-		 * Reload the watchdog timer, so that erasing many flash pages
-		 * doesn't cause a watchdog reset.  May not need this now that
-		 * we're using msleep() below.
-		 */
-		watchdog_reload();
-
-		/* Start erase */
-		LM4_FLASH_FMC = 0xa4420002;
-
-		/* Wait for erase to complete */
-		for (t = 0; LM4_FLASH_FMC & 0x02; t++) {
-			if (t > ERASE_TIMEOUT_MS)
-				return EC_ERROR_TIMEOUT;
-			msleep(1);
-		}
-
-		/* Check for error conditions - erase failed, voltage error,
-		 * protection error */
-		if (LM4_FLASH_FCRIS & 0x0a01)
-			return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-int flash_physical_get_protect(int bank)
-{
-	return (LM4_FLASH_FMPPE[F_BANK(bank)] & F_BIT(bank)) ? 0 : 1;
-}
-
-uint32_t flash_physical_get_protect_flags(void)
-{
-	uint32_t flags = 0;
-
-	/* Read all-protected state from our shadow copy */
-	if (all_protected)
-		flags |= EC_FLASH_PROTECT_ALL_NOW;
-
-	/* Check if blocks were stuck locked at pre-init */
-	if (stuck_locked)
-		flags |= EC_FLASH_PROTECT_ERROR_STUCK;
-
-	return flags;
-}
-
-int flash_physical_protect_now(int all)
-{
-	if (all) {
-		/* Protect the entire flash */
-		all_protected = 1;
-		protect_banks(0, CONFIG_FLASH_SIZE /
-			      CONFIG_FLASH_BANK_SIZE);
-	} else
-		/* Protect the WP region (read-only section and pstate) */
-		protect_banks(WP_BANK_OFFSET, WP_BANK_COUNT);
-
-	return EC_SUCCESS;
-}
-
-uint32_t flash_physical_get_valid_flags(void)
-{
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-	       EC_FLASH_PROTECT_RO_NOW |
-	       EC_FLASH_PROTECT_ALL_NOW;
-}
-
-uint32_t flash_physical_get_writable_flags(uint32_t cur_flags)
-{
-	uint32_t ret = 0;
-
-	/* If RO protection isn't enabled, its at-boot state can be changed. */
-	if (!(cur_flags & EC_FLASH_PROTECT_RO_NOW))
-		ret |= EC_FLASH_PROTECT_RO_AT_BOOT;
-
-	/*
-	 * If entire flash isn't protected at this boot, it can be enabled if
-	 * the WP GPIO is asserted.
-	 */
-	if (!(cur_flags & EC_FLASH_PROTECT_ALL_NOW) &&
-	    (cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED))
-		ret |= EC_FLASH_PROTECT_ALL_NOW;
-
-	return ret;
-}
-
-
-/*****************************************************************************/
-/* High-level APIs */
-
-int flash_pre_init(void)
-{
-	uint32_t reset_flags = system_get_reset_flags();
-	uint32_t prot_flags = flash_get_protect();
-	uint32_t unwanted_prot_flags = EC_FLASH_PROTECT_ALL_NOW |
-		EC_FLASH_PROTECT_ERROR_INCONSISTENT;
-
-	/*
-	 * If we have already jumped between images, an earlier image could
-	 * have applied write protection.  Nothing additional needs to be done.
-	 */
-	if (reset_flags & EC_RESET_FLAG_SYSJUMP)
-		return EC_SUCCESS;
-
-	if (prot_flags & EC_FLASH_PROTECT_GPIO_ASSERTED) {
-		/*
-		 * Write protect is asserted.  If we want RO flash protected,
-		 * protect it now.
-		 */
-		if ((prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT) &&
-		    !(prot_flags & EC_FLASH_PROTECT_RO_NOW)) {
-			int rv = flash_set_protect(EC_FLASH_PROTECT_RO_NOW,
-						   EC_FLASH_PROTECT_RO_NOW);
-			if (rv)
-				return rv;
-
-			/* Re-read flags */
-			prot_flags = flash_get_protect();
-		}
-
-		/* Update all-now flag if all flash is protected */
-		if (prot_flags & EC_FLASH_PROTECT_ALL_NOW)
-			all_protected = 1;
-
-	} else {
-		/* Don't want RO flash protected */
-		unwanted_prot_flags |= EC_FLASH_PROTECT_RO_NOW;
-	}
-
-	/* If there are no unwanted flags, done */
-	if (!(prot_flags & unwanted_prot_flags))
-		return EC_SUCCESS;
-
-	/*
-	 * If the last reboot was a power-on reset, it should have cleared
-	 * write-protect.  If it didn't, then the flash write protect registers
-	 * have been permanently committed and we can't fix that.
-	 */
-	if (reset_flags & EC_RESET_FLAG_POWER_ON) {
-		stuck_locked = 1;
-		return EC_ERROR_ACCESS_DENIED;
-	}
-
-	/* Otherwise, do a hard boot to clear the flash protection registers */
-	system_reset(SYSTEM_RESET_HARD | SYSTEM_RESET_PRESERVE_FLAGS);
-
-	/* That doesn't return, so if we're still here that's an error */
-	return EC_ERROR_UNKNOWN;
-}
diff --git a/chip/lm4/gpio.c b/chip/lm4/gpio.c
deleted file mode 100644
index 65d6548f90..0000000000
--- a/chip/lm4/gpio.c
+++ /dev/null
@@ -1,385 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GPIO module for Chrome EC */
-
-#include "clock.h"
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "switch.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* 0-terminated list of GPIO base addresses */
-static const uint32_t gpio_bases[] = {
-	LM4_GPIO_A, LM4_GPIO_B, LM4_GPIO_C, LM4_GPIO_D,
-	LM4_GPIO_E, LM4_GPIO_F, LM4_GPIO_G, LM4_GPIO_H,
-	LM4_GPIO_J, LM4_GPIO_K, LM4_GPIO_L, LM4_GPIO_M,
-	LM4_GPIO_N, LM4_GPIO_P, LM4_GPIO_Q, 0
-};
-
-/**
- * Find the index of a GPIO port base address
- *
- * This is used by the clock gating registers.
- *
- * @param port_base	Base address to find (LM4_GPIO_[A-Q])
- *
- * @return The index, or -1 if no match.
- */
-static int find_gpio_port_index(uint32_t port_base)
-{
-	int i;
-	for (i = 0; gpio_bases[i]; i++) {
-		if (gpio_bases[i] == port_base)
-			return i;
-	}
-	return -1;
-}
-
-void gpio_set_alternate_function(uint32_t port, uint32_t mask,
-				enum gpio_alternate_func func)
-{
-	int port_index = find_gpio_port_index(port);
-	int cgmask;
-
-	/* Ignore (do nothing for) invalid port values */
-	if (port_index < 0)
-		return;
-
-	/* Enable the GPIO port in run and sleep. */
-	cgmask = 1 << port_index;
-	clock_enable_peripheral(CGC_OFFSET_GPIO, cgmask,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-
-	if (func != GPIO_ALT_FUNC_NONE) {
-		int pctlmask = 0;
-		int i;
-		/* Expand mask from bits to nibbles */
-		for (i = 0; i < 8; i++) {
-			if (mask & BIT(i))
-				pctlmask |= 1 << (4 * i);
-		}
-
-		LM4_GPIO_PCTL(port) =
-			(LM4_GPIO_PCTL(port) & ~(pctlmask * 0xf)) |
-			(pctlmask * func);
-		LM4_GPIO_AFSEL(port) |= mask;
-	} else {
-		LM4_GPIO_AFSEL(port) &= ~mask;
-	}
-}
-
-test_mockable int gpio_get_level(enum gpio_signal signal)
-{
-	return LM4_GPIO_DATA(gpio_list[signal].port,
-			     gpio_list[signal].mask) ? 1 : 0;
-}
-
-void gpio_set_level(enum gpio_signal signal, int value)
-{
-	/*
-	 * Ok to write 0xff because LM4_GPIO_DATA bit-masks only the bit
-	 * we care about.
-	 */
-	LM4_GPIO_DATA(gpio_list[signal].port,
-		      gpio_list[signal].mask) = (value ? 0xff : 0);
-}
-
-void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
-{
-	/*
-	 * Select open drain first, so that we don't glitch the signal
-	 * when changing the line to an output.
-	 */
-	if (flags & GPIO_OPEN_DRAIN)
-		LM4_GPIO_ODR(port) |= mask;
-	else
-		LM4_GPIO_ODR(port) &= ~mask;
-
-	if (flags & GPIO_OUTPUT)
-		LM4_GPIO_DIR(port) |= mask;
-	else
-		LM4_GPIO_DIR(port) &= ~mask;
-
-	/* Handle pullup / pulldown */
-	if (flags & GPIO_PULL_UP) {
-		LM4_GPIO_PUR(port) |= mask;
-	} else if (flags & GPIO_PULL_DOWN) {
-		LM4_GPIO_PDR(port) |= mask;
-	} else {
-		/* No pull up/down */
-		LM4_GPIO_PUR(port) &= ~mask;
-		LM4_GPIO_PDR(port) &= ~mask;
-	}
-
-	/* Set up interrupt type */
-	if (flags & (GPIO_INT_F_LOW | GPIO_INT_F_HIGH))
-		LM4_GPIO_IS(port) |= mask;
-	else
-		LM4_GPIO_IS(port) &= ~mask;
-
-	if (flags & (GPIO_INT_F_RISING | GPIO_INT_F_HIGH))
-		LM4_GPIO_IEV(port) |= mask;
-	else
-		LM4_GPIO_IEV(port) &= ~mask;
-
-	/* Handle interrupting on both edges */
-	if ((flags & GPIO_INT_F_RISING) &&
-	    (flags & GPIO_INT_F_FALLING))
-		LM4_GPIO_IBE(port) |= mask;
-	else
-		LM4_GPIO_IBE(port) &= ~mask;
-
-	if (flags & GPIO_ANALOG)
-		LM4_GPIO_DEN(port) &= ~mask;
-	else
-		LM4_GPIO_DEN(port) |= mask;
-
-	/* Set level */
-	if (flags & GPIO_HIGH)
-		LM4_GPIO_DATA(port, mask) = 0xff;
-	else if (flags & GPIO_LOW)
-		LM4_GPIO_DATA(port, mask) = 0;
-}
-
-int gpio_enable_interrupt(enum gpio_signal signal)
-{
-	const struct gpio_info *g = gpio_list + signal;
-	/* Fail if no interrupt handler */
-	if (signal >= GPIO_IH_COUNT)
-		return EC_ERROR_UNKNOWN;
-
-	LM4_GPIO_IM(g->port) |= g->mask;
-	return EC_SUCCESS;
-}
-
-int gpio_disable_interrupt(enum gpio_signal signal)
-{
-	const struct gpio_info *g = gpio_list + signal;
-
-	/* Fail if no interrupt handler */
-	if (signal >= GPIO_IH_COUNT)
-		return EC_ERROR_UNKNOWN;
-
-	LM4_GPIO_IM(g->port) &= ~g->mask;
-	return EC_SUCCESS;
-}
-
-int gpio_clear_pending_interrupt(enum gpio_signal signal)
-{
-	const struct gpio_info *g = gpio_list + signal;
-
-	/* Fail if no interrupt handler */
-	if (signal >= GPIO_IH_COUNT)
-		return EC_ERROR_INVAL;
-
-	LM4_GPIO_ICR(g->port) |= g->mask;
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_LOW_POWER_IDLE
-/**
- * Convert GPIO port to a mask that can be used to set the
- * clock gate control register for GPIOs.
- */
-static int gpio_port_to_clock_gate_mask(uint32_t gpio_port)
-{
-	int index = find_gpio_port_index(gpio_port);
-
-	return index >= 0 ? BIT(index) : 0;
-}
-#endif
-
-void gpio_pre_init(void)
-{
-	const struct gpio_info *g = gpio_list;
-	int is_warm = 0;
-	int i;
-
-	if (LM4_SYSTEM_RCGCGPIO == 0x7fff) {
-		/* This is a warm reboot */
-		is_warm = 1;
-	} else {
-		/*
-		 * Enable clocks to all the GPIO blocks since we use all of
-		 * them as GPIOs in run and sleep modes.
-		 */
-		clock_enable_peripheral(CGC_OFFSET_GPIO, 0x7fff,
-				CGC_MODE_RUN | CGC_MODE_SLEEP);
-	}
-
-	/*
-	 * Disable GPIO commit control for PD7 and PF0, since we don't use the
-	 * NMI pin function.
-	 */
-	LM4_GPIO_LOCK(LM4_GPIO_D) = LM4_GPIO_LOCK_UNLOCK;
-	LM4_GPIO_CR(LM4_GPIO_D) |= 0x80;
-	LM4_GPIO_LOCK(LM4_GPIO_D) = 0;
-	LM4_GPIO_LOCK(LM4_GPIO_F) = LM4_GPIO_LOCK_UNLOCK;
-	LM4_GPIO_CR(LM4_GPIO_F) |= 0x01;
-	LM4_GPIO_LOCK(LM4_GPIO_F) = 0;
-
-	/* Clear SSI0 alternate function on PA2:5 */
-	LM4_GPIO_AFSEL(LM4_GPIO_A) &= ~0x3c;
-
-	/* Mask all GPIO interrupts */
-	for (i = 0; gpio_bases[i]; i++)
-		LM4_GPIO_IM(gpio_bases[i]) = 0;
-
-	/* Set all GPIOs to defaults */
-	for (i = 0; i < GPIO_COUNT; i++, g++) {
-		int flags = g->flags;
-
-		if (flags & GPIO_DEFAULT)
-			continue;
-
-#ifdef CONFIG_LOW_POWER_IDLE
-		/*
-		 * Enable board specific GPIO ports to interrupt deep sleep by
-		 * providing a clock to that port in deep sleep mode.
-		 */
-		if (flags & GPIO_INT_DSLEEP) {
-			clock_enable_peripheral(CGC_OFFSET_GPIO,
-				gpio_port_to_clock_gate_mask(g->port),
-				CGC_MODE_ALL);
-		}
-#endif
-
-		/*
-		 * If this is a warm reboot, don't set the output levels or
-		 * we'll shut off the main chipset.
-		 */
-		if (is_warm)
-			flags &= ~(GPIO_LOW | GPIO_HIGH);
-
-		/* Set up GPIO based on flags */
-		gpio_set_flags_by_mask(g->port, g->mask, flags);
-
-		/* Use as GPIO, not alternate function */
-		gpio_set_alternate_function(g->port, g->mask,
-					GPIO_ALT_FUNC_NONE);
-	}
-
-#ifdef CONFIG_LOW_POWER_IDLE
-	/*
-	 * Enable KB scan row to interrupt deep sleep by providing a clock
-	 * signal to that port in deep sleep mode.
-	 */
-	clock_enable_peripheral(CGC_OFFSET_GPIO,
-				gpio_port_to_clock_gate_mask(KB_SCAN_ROW_GPIO),
-				CGC_MODE_ALL);
-#endif
-}
-
-/* List of GPIO IRQs to enable. Don't automatically enable interrupts for
- * the keyboard input GPIO bank - that's handled separately. Of course the
- * bank is different for different systems. */
-static const uint8_t gpio_irqs[] = {
-	LM4_IRQ_GPIOA, LM4_IRQ_GPIOB, LM4_IRQ_GPIOC, LM4_IRQ_GPIOD,
-	LM4_IRQ_GPIOE, LM4_IRQ_GPIOF, LM4_IRQ_GPIOG, LM4_IRQ_GPIOH,
-	LM4_IRQ_GPIOJ,
-#if defined(KB_SCAN_ROW_IRQ) && (KB_SCAN_ROW_IRQ != LM4_IRQ_GPIOK)
-	LM4_IRQ_GPIOK,
-#endif
-	LM4_IRQ_GPIOL, LM4_IRQ_GPIOM,
-#if defined(KB_SCAN_ROW_IRQ) && (KB_SCAN_ROW_IRQ != LM4_IRQ_GPION)
-	LM4_IRQ_GPION,
-#endif
-	LM4_IRQ_GPIOP, LM4_IRQ_GPIOQ
-};
-
-static void gpio_init(void)
-{
-	int i;
-
-	/* Enable IRQs now that pins are set up */
-	for (i = 0; i < ARRAY_SIZE(gpio_irqs); i++)
-		task_enable_irq(gpio_irqs[i]);
-}
-DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
-
-/*****************************************************************************/
-/* Interrupt handlers */
-
-/**
- * Handle a GPIO interrupt.
- *
- * @param port		GPIO port (LM4_GPIO_*)
- * @param mis		Masked interrupt status value for that port
- */
-static void gpio_interrupt(int port, uint32_t mis)
-{
-	int i = 0;
-	const struct gpio_info *g = gpio_list;
-
-	for (i = 0; i < GPIO_IH_COUNT && mis; i++, g++) {
-		if (port == g->port && (mis & g->mask)) {
-			gpio_irq_handlers[i](i);
-			mis &= ~g->mask;
-		}
-	}
-}
-
-/**
- * Handlers for each GPIO port.  These read and clear the interrupt bits for
- * the port, then call the master handler above.
- */
-#define GPIO_IRQ_FUNC(irqfunc, gpiobase)		\
-	void irqfunc(void)				\
-	{						\
-		uint32_t mis = LM4_GPIO_MIS(gpiobase);	\
-		LM4_GPIO_ICR(gpiobase) = mis;		\
-		gpio_interrupt(gpiobase, mis);		\
-	}
-
-GPIO_IRQ_FUNC(__gpio_a_interrupt, LM4_GPIO_A);
-GPIO_IRQ_FUNC(__gpio_b_interrupt, LM4_GPIO_B);
-GPIO_IRQ_FUNC(__gpio_c_interrupt, LM4_GPIO_C);
-GPIO_IRQ_FUNC(__gpio_d_interrupt, LM4_GPIO_D);
-GPIO_IRQ_FUNC(__gpio_e_interrupt, LM4_GPIO_E);
-GPIO_IRQ_FUNC(__gpio_f_interrupt, LM4_GPIO_F);
-GPIO_IRQ_FUNC(__gpio_g_interrupt, LM4_GPIO_G);
-GPIO_IRQ_FUNC(__gpio_h_interrupt, LM4_GPIO_H);
-GPIO_IRQ_FUNC(__gpio_j_interrupt, LM4_GPIO_J);
-#if defined(KB_SCAN_ROW_GPIO) && (KB_SCAN_ROW_GPIO != LM4_GPIO_K)
-GPIO_IRQ_FUNC(__gpio_k_interrupt, LM4_GPIO_K);
-#endif
-GPIO_IRQ_FUNC(__gpio_l_interrupt, LM4_GPIO_L);
-GPIO_IRQ_FUNC(__gpio_m_interrupt, LM4_GPIO_M);
-#if defined(KB_SCAN_ROW_GPIO) && (KB_SCAN_ROW_GPIO != LM4_GPIO_N)
-GPIO_IRQ_FUNC(__gpio_n_interrupt, LM4_GPIO_N);
-#endif
-GPIO_IRQ_FUNC(__gpio_p_interrupt, LM4_GPIO_P);
-GPIO_IRQ_FUNC(__gpio_q_interrupt, LM4_GPIO_Q);
-
-#undef GPIO_IRQ_FUNC
-
-/*
- * Declare IRQs.  Nesting this macro inside the GPIO_IRQ_FUNC macro works
- * poorly because DECLARE_IRQ() stringizes its inputs.
- */
-DECLARE_IRQ(LM4_IRQ_GPIOA, __gpio_a_interrupt, 1);
-DECLARE_IRQ(LM4_IRQ_GPIOB, __gpio_b_interrupt, 1);
-DECLARE_IRQ(LM4_IRQ_GPIOC, __gpio_c_interrupt, 1);
-DECLARE_IRQ(LM4_IRQ_GPIOD, __gpio_d_interrupt, 1);
-DECLARE_IRQ(LM4_IRQ_GPIOE, __gpio_e_interrupt, 1);
-DECLARE_IRQ(LM4_IRQ_GPIOF, __gpio_f_interrupt, 1);
-DECLARE_IRQ(LM4_IRQ_GPIOG, __gpio_g_interrupt, 1);
-DECLARE_IRQ(LM4_IRQ_GPIOH, __gpio_h_interrupt, 1);
-DECLARE_IRQ(LM4_IRQ_GPIOJ, __gpio_j_interrupt, 1);
-#if defined(KB_SCAN_ROW_GPIO) && (KB_SCAN_ROW_GPIO != LM4_GPIO_K)
-DECLARE_IRQ(LM4_IRQ_GPIOK, __gpio_k_interrupt, 1);
-#endif
-DECLARE_IRQ(LM4_IRQ_GPIOL, __gpio_l_interrupt, 1);
-DECLARE_IRQ(LM4_IRQ_GPIOM, __gpio_m_interrupt, 1);
-#if defined(KB_SCAN_ROW_GPIO) && (KB_SCAN_ROW_GPIO != LM4_GPIO_N)
-DECLARE_IRQ(LM4_IRQ_GPION, __gpio_n_interrupt, 1);
-#endif
-DECLARE_IRQ(LM4_IRQ_GPIOP, __gpio_p_interrupt, 1);
-DECLARE_IRQ(LM4_IRQ_GPIOQ, __gpio_q_interrupt, 1);
diff --git a/chip/lm4/hwtimer.c b/chip/lm4/hwtimer.c
deleted file mode 100644
index 44e1c2fb27..0000000000
--- a/chip/lm4/hwtimer.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Hardware timers driver */
-
-#include "clock.h"
-#include "common.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-
-void __hw_clock_event_set(uint32_t deadline)
-{
-	/* set the match on the deadline */
-	LM4_TIMER_TAMATCHR(6) = 0xffffffff - deadline;
-	/* Set the match interrupt */
-	LM4_TIMER_IMR(6) |= 0x10;
-}
-
-uint32_t __hw_clock_event_get(void)
-{
-	return 0xffffffff - LM4_TIMER_TAMATCHR(6);
-}
-
-void __hw_clock_event_clear(void)
-{
-	/* Disable the match interrupt */
-	LM4_TIMER_IMR(6) &= ~0x10;
-}
-
-uint32_t __hw_clock_source_read(void)
-{
-	return 0xffffffff - LM4_TIMER_TAV(6);
-}
-
-void __hw_clock_source_set(uint32_t ts)
-{
-	LM4_TIMER_TAV(6) = 0xffffffff - ts;
-}
-
-void __hw_clock_source_irq(void)
-{
-	uint32_t status = LM4_TIMER_RIS(6);
-
-	/* Clear interrupt */
-	LM4_TIMER_ICR(6) = status;
-
-	/*
-	 * Find expired timers and set the new timer deadline; check the IRQ
-	 * status to determine if the free-running counter overflowed.
-	 */
-	process_timers(status & 0x01);
-}
-DECLARE_IRQ(LM4_IRQ_TIMERW0A, __hw_clock_source_irq, 1);
-
-static void update_prescaler(void)
-{
-	/*
-	 * Set the prescaler to increment every microsecond.  This takes
-	 * effect immediately, because the TAILD bit in TAMR is clear.
-	 */
-	LM4_TIMER_TAPR(6) = clock_get_freq() / SECOND;
-}
-DECLARE_HOOK(HOOK_FREQ_CHANGE, update_prescaler, HOOK_PRIO_DEFAULT);
-
-int __hw_clock_source_init(uint32_t start_t)
-{
-	/*
-	 * Use WTIMER0 (timer 6) configured as a free running counter with 1 us
-	 * period.
-	 */
-
-	/* Enable WTIMER0 clock in run and sleep modes. */
-	clock_enable_peripheral(CGC_OFFSET_WTIMER, 0x1,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-
-	/* Ensure timer is disabled : TAEN = TBEN = 0 */
-	LM4_TIMER_CTL(6) &= ~0x101;
-	/* Set overflow interrupt */
-	LM4_TIMER_IMR(6) = 0x1;
-	/* 32-bit timer mode */
-	LM4_TIMER_CFG(6) = 4;
-
-	/* Set initial prescaler */
-	update_prescaler();
-
-	/* Periodic mode, counting down */
-	LM4_TIMER_TAMR(6) = 0x22;
-	/* Use the full 32-bits of the timer */
-	LM4_TIMER_TAILR(6) = 0xffffffff;
-	/* Starts counting in timer A */
-	LM4_TIMER_CTL(6) |= 0x1;
-
-	/*
-	 * Override the count with the start value now that counting has
-	 * started.
-	 */
-	__hw_clock_source_set(start_t);
-
-	/* Enable interrupt */
-	task_enable_irq(LM4_IRQ_TIMERW0A);
-
-	return LM4_IRQ_TIMERW0A;
-}
diff --git a/chip/lm4/i2c.c b/chip/lm4/i2c.c
deleted file mode 100644
index 0608b433bc..0000000000
--- a/chip/lm4/i2c.c
+++ /dev/null
@@ -1,411 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* I2C port module for Chrome EC */
-
-#include "atomic.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-
-/* Flags for writes to MCS */
-#define LM4_I2C_MCS_RUN   BIT(0)
-#define LM4_I2C_MCS_START BIT(1)
-#define LM4_I2C_MCS_STOP  BIT(2)
-#define LM4_I2C_MCS_ACK   BIT(3)
-#define LM4_I2C_MCS_HS    BIT(4)
-#define LM4_I2C_MCS_QCMD  BIT(5)
-
-/* Flags for reads from MCS */
-#define LM4_I2C_MCS_BUSY   BIT(0)
-#define LM4_I2C_MCS_ERROR  BIT(1)
-#define LM4_I2C_MCS_ADRACK BIT(2)
-#define LM4_I2C_MCS_DATACK BIT(3)
-#define LM4_I2C_MCS_ARBLST BIT(4)
-#define LM4_I2C_MCS_IDLE   BIT(5)
-#define LM4_I2C_MCS_BUSBSY BIT(6)
-#define LM4_I2C_MCS_CLKTO  BIT(7)
-
-/*
- * Minimum delay between resetting the port or sending a stop condition, and
- * when the port can be expected to be back in an idle state (and the slave
- * has had long enough to see the start/stop condition edges).
- *
- * 500 us = 50 clocks at 100 KHz bus speed.  This has been experimentally
- * determined to be enough.
- */
-#define I2C_IDLE_US 500
-
-/* IRQ for each port */
-static const uint32_t i2c_irqs[] = {LM4_IRQ_I2C0, LM4_IRQ_I2C1, LM4_IRQ_I2C2,
-				    LM4_IRQ_I2C3, LM4_IRQ_I2C4, LM4_IRQ_I2C5};
-BUILD_ASSERT(ARRAY_SIZE(i2c_irqs) == I2C_PORT_COUNT);
-
-/* I2C port state data */
-struct i2c_port_data {
-	const uint8_t *out;	/* Output data pointer */
-	int out_size;		/* Output data to transfer, in bytes */
-	uint8_t *in;		/* Input data pointer */
-	int in_size;		/* Input data to transfer, in bytes */
-	int flags;		/* Flags (I2C_XFER_*) */
-	int idx;		/* Index into input/output data */
-	int err;		/* Error code, if any */
-	uint32_t timeout_us;	/* Transaction timeout, or 0 to use default */
-
-	/* Task waiting on port, or TASK_ID_INVALID if none. */
-	volatile int task_waiting;
-};
-static struct i2c_port_data pdata[I2C_PORT_COUNT];
-
-int i2c_is_busy(int port)
-{
-	return LM4_I2C_MCS(port) & LM4_I2C_MCS_BUSBSY;
-}
-
-/**
- * I2C transfer engine.
- *
- * @return Zero when done with transfer (ready to wake task).
- *
- * MCS sequence on multi-byte write:
- *     0x3 0x1 0x1 ... 0x1 0x5
- * Single byte write:
- *     0x7
- *
- * MCS receive sequence on multi-byte read:
- *     0xb 0x9 0x9 ... 0x9 0x5
- * Single byte read:
- *     0x7
- */
-int i2c_do_work(int port)
-{
-	struct i2c_port_data *pd = pdata + port;
-	uint32_t reg_mcs = LM4_I2C_MCS_RUN;
-
-	if (pd->flags & I2C_XFER_START) {
-		/* Set start bit on first byte */
-		reg_mcs |= LM4_I2C_MCS_START;
-		pd->flags &= ~I2C_XFER_START;
-	} else if (LM4_I2C_MCS(port) & (LM4_I2C_MCS_CLKTO | LM4_I2C_MCS_ARBLST |
-					LM4_I2C_MCS_ERROR)) {
-		/*
-		 * Error after starting; abort transfer.  Ignore errors at
-		 * start because arbitration and timeout errors are taken care
-		 * of in chip_i2c_xfer(), and slave ack failures will
-		 * automatically clear once we send a start condition.
-		 */
-		pd->err = EC_ERROR_UNKNOWN;
-		return 0;
-	}
-
-	if (pd->out_size) {
-		/* Send next byte of output */
-		LM4_I2C_MDR(port) = *(pd->out++);
-		pd->idx++;
-
-		/* Handle starting to send last byte */
-		if (pd->idx == pd->out_size) {
-
-			/* Done with output after this */
-			pd->out_size = 0;
-			pd->idx = 0;
-
-			/* Resend start bit when changing direction */
-			pd->flags |= I2C_XFER_START;
-
-			/*
-			 * Send stop bit after last byte if the stop flag is
-			 * on, and caller doesn't expect to receive data.
-			 */
-			if ((pd->flags & I2C_XFER_STOP) && pd->in_size == 0)
-				reg_mcs |= LM4_I2C_MCS_STOP;
-		}
-
-		LM4_I2C_MCS(port) = reg_mcs;
-		return 1;
-
-	} else if (pd->in_size) {
-		if (pd->idx) {
-			/* Copy the byte we just read */
-			*(pd->in++) = LM4_I2C_MDR(port) & 0xff;
-		} else {
-			/* Starting receive; switch to receive address */
-			LM4_I2C_MSA(port) |= 0x01;
-		}
-
-		if (pd->idx < pd->in_size) {
-			/* More data to read */
-			pd->idx++;
-
-			/* ACK all bytes except the last one */
-			if ((pd->flags & I2C_XFER_STOP) &&
-			    pd->idx == pd->in_size)
-				reg_mcs |= LM4_I2C_MCS_STOP;
-			else
-				reg_mcs |= LM4_I2C_MCS_ACK;
-
-			LM4_I2C_MCS(port) = reg_mcs;
-			return 1;
-		}
-	}
-
-	/* If we're still here, done with transfer */
-	return 0;
-}
-
-int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags,
-		  const uint8_t *out, int out_size,
-		  uint8_t *in, int in_size, int flags)
-{
-	struct i2c_port_data *pd = pdata + port;
-	uint32_t reg_mcs = LM4_I2C_MCS(port);
-	int events = 0;
-
-	if (out_size == 0 && in_size == 0)
-		return EC_SUCCESS;
-
-	/* Copy data to port struct */
-	pd->out = out;
-	pd->out_size = out_size;
-	pd->in = in;
-	pd->in_size = in_size;
-	pd->flags = flags;
-	pd->idx = 0;
-	pd->err = 0;
-
-	/* Make sure we're in a good state to start */
-	if ((flags & I2C_XFER_START) &&
-	    ((reg_mcs & (LM4_I2C_MCS_CLKTO | LM4_I2C_MCS_ARBLST)) ||
-			    (i2c_get_line_levels(port) != I2C_LINE_IDLE))) {
-		uint32_t tpr = LM4_I2C_MTPR(port);
-
-		CPRINTS("I2C%d Addr:%02X bad status 0x%02x, SCL=%d, SDA=%d",
-			port,
-			I2C_GET_ADDR(slave_addr_flags),
-			reg_mcs,
-			i2c_get_line_levels(port) & I2C_LINE_SCL_HIGH,
-			i2c_get_line_levels(port) & I2C_LINE_SDA_HIGH);
-
-		/* Attempt to unwedge the port. */
-		i2c_unwedge(port);
-
-		/* Clock timeout or arbitration lost.  Reset port to clear. */
-		deprecated_atomic_or(LM4_SYSTEM_SRI2C_ADDR, BIT(port));
-		clock_wait_cycles(3);
-		deprecated_atomic_clear_bits(LM4_SYSTEM_SRI2C_ADDR, BIT(port));
-		clock_wait_cycles(3);
-
-		/* Restore settings */
-		LM4_I2C_MCR(port) = 0x10;
-		LM4_I2C_MTPR(port) = tpr;
-
-		/*
-		 * We don't know what edges the slave saw, so sleep long enough
-		 * that the slave will see the new start condition below.
-		 */
-		usleep(I2C_IDLE_US);
-	}
-
-	/* Set slave address for transmit */
-	LM4_I2C_MSA(port) = (I2C_GET_ADDR(slave_addr_flags) << 1) & 0xff;
-
-	/* Enable interrupts */
-	pd->task_waiting = task_get_current();
-	LM4_I2C_MICR(port) = 0x03;
-	LM4_I2C_MIMR(port) = 0x03;
-
-	/* Kick the port interrupt handler to start the transfer */
-	task_trigger_irq(i2c_irqs[port]);
-
-	/* Wait for transfer complete or timeout */
-	events = task_wait_event_mask(TASK_EVENT_I2C_IDLE, pd->timeout_us);
-
-	/* Disable interrupts */
-	LM4_I2C_MIMR(port) = 0x00;
-	pd->task_waiting = TASK_ID_INVALID;
-
-	/* Handle timeout */
-	if (events & TASK_EVENT_TIMER)
-		pd->err = EC_ERROR_TIMEOUT;
-
-	if (pd->err) {
-		/* Force port back idle */
-		LM4_I2C_MCS(port) = LM4_I2C_MCS_STOP;
-		usleep(I2C_IDLE_US);
-	}
-
-	return pd->err;
-}
-
-int i2c_raw_get_scl(int port)
-{
-	enum gpio_signal g;
-	int ret;
-
-	/* If no SCL pin defined for this port, then return 1 to appear idle. */
-	if (get_scl_from_i2c_port(port, &g) != EC_SUCCESS)
-		return 1;
-
-	/* If we are driving the pin low, it must be low. */
-	if (gpio_get_level(g) == 0)
-		return 0;
-
-	/*
-	 * Otherwise, we need to toggle it to an input to read the true pin
-	 * state.
-	 */
-	gpio_set_flags(g, GPIO_INPUT);
-	ret = gpio_get_level(g);
-	gpio_set_flags(g, GPIO_ODR_HIGH);
-
-	return ret;
-}
-
-int i2c_raw_get_sda(int port)
-{
-	enum gpio_signal g;
-	int ret;
-
-	/* If no SDA pin defined for this port, then return 1 to appear idle. */
-	if (get_sda_from_i2c_port(port, &g) != EC_SUCCESS)
-		return 1;
-
-	/* If we are driving the pin low, it must be low. */
-	if (gpio_get_level(g) == 0)
-		return 0;
-
-	/*
-	 * Otherwise, we need to toggle it to an input to read the true pin
-	 * state.
-	 */
-	gpio_set_flags(g, GPIO_INPUT);
-	ret = gpio_get_level(g);
-	gpio_set_flags(g, GPIO_ODR_HIGH);
-
-	return ret;
-}
-
-int i2c_get_line_levels(int port)
-{
-	/* Conveniently, MBMON bit BIT(1) is SDA and BIT(0) is SCL. */
-	return LM4_I2C_MBMON(port) & 0x03;
-}
-
-void i2c_set_timeout(int port, uint32_t timeout)
-{
-	pdata[port].timeout_us = timeout ? timeout : I2C_TIMEOUT_DEFAULT_US;
-}
-
-/*****************************************************************************/
-/* Hooks */
-
-static void i2c_freq_changed(void)
-{
-	int freq = clock_get_freq();
-	int i;
-
-	for (i = 0; i < i2c_ports_used; i++) {
-		/*
-		 * From datasheet:
-		 *     SCL_PRD = 2 * (1 + TPR) * (SCL_LP + SCL_HP) * CLK_PRD
-		 *
-		 * so:
-		 *     TPR = SCL_PRD / (2 * (SCL_LP + SCL_HP) * CLK_PRD) - 1
-		 *
-		 * converting from period to frequency:
-		 *     TPR = CLK_FREQ / (SCL_FREQ * 2 * (SCL_LP + SCL_HP)) - 1
-		 */
-		const int d = 2 * (6 + 4) * (i2c_ports[i].kbps * 1000);
-
-		/* Round TPR up, so desired kbps is an upper bound */
-		const int tpr = (freq + d - 1) / d - 1;
-
-#ifdef PRINT_I2C_SPEEDS
-		const int f = freq / (2 * (1 + tpr) * (6 + 4));
-		CPRINTS("I2C%d clk=%d tpr=%d freq=%d",
-			i2c_ports[i].port, freq, tpr, f);
-#endif
-
-		LM4_I2C_MTPR(i2c_ports[i].port) = tpr;
-	}
-}
-DECLARE_HOOK(HOOK_FREQ_CHANGE, i2c_freq_changed, HOOK_PRIO_DEFAULT);
-
-void i2c_init(void)
-{
-	uint32_t mask = 0;
-	int i;
-
-	/* Enable I2C modules in run and sleep modes. */
-	for (i = 0; i < i2c_ports_used; i++)
-		mask |= 1 << i2c_ports[i].port;
-
-	clock_enable_peripheral(CGC_OFFSET_I2C, mask,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-
-	/* Configure GPIOs */
-	gpio_config_module(MODULE_I2C, 1);
-
-	/* Initialize ports as master, with interrupts enabled */
-	for (i = 0; i < i2c_ports_used; i++)
-		LM4_I2C_MCR(i2c_ports[i].port) = 0x10;
-
-	/* Set initial clock frequency */
-	i2c_freq_changed();
-
-	/* Enable IRQs; no tasks are waiting on ports */
-	for (i = 0; i < I2C_PORT_COUNT; i++) {
-		pdata[i].task_waiting = TASK_ID_INVALID;
-		task_enable_irq(i2c_irqs[i]);
-
-		/* Use default timeout */
-		i2c_set_timeout(i, 0);
-	}
-}
-
-/**
- * Handle an interrupt on the specified port.
- *
- * @param port		I2C port generating interrupt
- */
-static void handle_interrupt(int port)
-{
-	int id = pdata[port].task_waiting;
-
-	/* Clear the interrupt status */
-	LM4_I2C_MICR(port) = LM4_I2C_MMIS(port);
-
-	/* If no task is waiting, just return */
-	if (id == TASK_ID_INVALID)
-		return;
-
-	/* If done doing work, wake up the task waiting for the transfer */
-	if (!i2c_do_work(port))
-		task_set_event(id, TASK_EVENT_I2C_IDLE, 0);
-}
-
-void i2c0_interrupt(void) { handle_interrupt(0); }
-void i2c1_interrupt(void) { handle_interrupt(1); }
-void i2c2_interrupt(void) { handle_interrupt(2); }
-void i2c3_interrupt(void) { handle_interrupt(3); }
-void i2c4_interrupt(void) { handle_interrupt(4); }
-void i2c5_interrupt(void) { handle_interrupt(5); }
-
-DECLARE_IRQ(LM4_IRQ_I2C0, i2c0_interrupt, 2);
-DECLARE_IRQ(LM4_IRQ_I2C1, i2c1_interrupt, 2);
-DECLARE_IRQ(LM4_IRQ_I2C2, i2c2_interrupt, 2);
-DECLARE_IRQ(LM4_IRQ_I2C3, i2c3_interrupt, 2);
-DECLARE_IRQ(LM4_IRQ_I2C4, i2c4_interrupt, 2);
-DECLARE_IRQ(LM4_IRQ_I2C5, i2c5_interrupt, 2);
diff --git a/chip/lm4/keyboard_raw.c b/chip/lm4/keyboard_raw.c
deleted file mode 100644
index 81af0efdde..0000000000
--- a/chip/lm4/keyboard_raw.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Functions needed by keyboard scanner module for Chrome EC */
-
-#include "common.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "registers.h"
-#include "task.h"
-
-void keyboard_raw_init(void)
-{
-	/* Ensure top-level interrupt is disabled */
-	keyboard_raw_enable_interrupt(0);
-
-	/*
-	 * Set column outputs as open-drain; we either pull them low or let
-	 * them float high.
-	 */
-	LM4_GPIO_AFSEL(LM4_GPIO_P) = 0;  /* KSO[7:0] */
-	LM4_GPIO_AFSEL(LM4_GPIO_Q) &= ~0x1f;  /* KSO[12:8] */
-	LM4_GPIO_DEN(LM4_GPIO_P) = 0xff;
-	LM4_GPIO_DEN(LM4_GPIO_Q) |= 0x1f;
-	LM4_GPIO_DIR(LM4_GPIO_P) = 0xff;
-	LM4_GPIO_DIR(LM4_GPIO_Q) |= 0x1f;
-	LM4_GPIO_ODR(LM4_GPIO_P) = 0xff;
-	LM4_GPIO_ODR(LM4_GPIO_Q) |= 0x1f;
-
-#ifdef CONFIG_KEYBOARD_COL2_INVERTED
-	/*
-	 * When column 2 is inverted, the Silego has a pulldown instead of a
-	 * pullup.  So drive it push-pull instead of open-drain.
-	 */
-	LM4_GPIO_ODR(LM4_GPIO_P) &= ~BIT(2);
-#endif
-
-	/* Set row inputs with pull-up */
-	LM4_GPIO_AFSEL(KB_SCAN_ROW_GPIO) &= 0xff;
-	LM4_GPIO_DEN(KB_SCAN_ROW_GPIO) |= 0xff;
-	LM4_GPIO_DIR(KB_SCAN_ROW_GPIO) = 0;
-	LM4_GPIO_PUR(KB_SCAN_ROW_GPIO) = 0xff;
-
-	/* Edge-sensitive on both edges. */
-	LM4_GPIO_IS(KB_SCAN_ROW_GPIO) = 0;
-	LM4_GPIO_IBE(KB_SCAN_ROW_GPIO) = 0xff;
-
-	/*
-	 * Enable interrupts for the inputs.  The top-level interrupt is still
-	 * masked off, so this won't trigger interrupts yet.
-	 */
-	LM4_GPIO_IM(KB_SCAN_ROW_GPIO) = 0xff;
-}
-
-void keyboard_raw_task_start(void)
-{
-	task_enable_irq(KB_SCAN_ROW_IRQ);
-}
-
-test_mockable void keyboard_raw_drive_column(int col)
-{
-	int mask;
-
-	if (col == KEYBOARD_COLUMN_NONE)
-		mask = 0x1fff;			/* Tri-state all outputs */
-	else if (col == KEYBOARD_COLUMN_ALL)
-		mask = 0;			/* Assert all outputs */
-	else
-		mask = 0x1fff ^ BIT(col);	/* Assert a single output */
-
-#ifdef CONFIG_KEYBOARD_COL2_INVERTED
-	/* Invert column 2 output */
-	mask ^= BIT(2);
-#endif
-
-	LM4_GPIO_DATA(LM4_GPIO_P, 0xff) = mask & 0xff;
-	LM4_GPIO_DATA(LM4_GPIO_Q, 0x1f) = (mask >> 8) & 0x1f;
-}
-
-test_mockable int keyboard_raw_read_rows(void)
-{
-	/* Bits are active-low, so invert returned levels */
-	return LM4_GPIO_DATA(KB_SCAN_ROW_GPIO, 0xff) ^ 0xff;
-}
-
-void keyboard_raw_enable_interrupt(int enable)
-{
-	if (enable) {
-		/*
-		 * Clear pending interrupts before enabling them, because the
-		 * raw interrupt status may have been tripped by keyboard
-		 * scanning or, if a key is already pressed, by driving all the
-		 * outputs.
-		 *
-		 * We won't lose keyboard events because the scanning task will
-		 * explicitly check the raw row state before waiting for an
-		 * interrupt.  If a key is pressed, the task won't wait.
-		 */
-		LM4_GPIO_ICR(KB_SCAN_ROW_GPIO) = 0xff;
-		LM4_GPIO_IM(KB_SCAN_ROW_GPIO) = 0xff;
-	} else {
-		LM4_GPIO_IM(KB_SCAN_ROW_GPIO) = 0;
-	}
-}
-
-/**
- * Interrupt handler for the entire GPIO bank of keyboard rows.
- */
-void keyboard_raw_interrupt(void)
-{
-	/* Clear all pending keyboard interrupts */
-	LM4_GPIO_ICR(KB_SCAN_ROW_GPIO) = 0xff;
-
-	/* Wake the scan task */
-	task_wake(TASK_ID_KEYSCAN);
-}
-DECLARE_IRQ(KB_SCAN_ROW_IRQ, keyboard_raw_interrupt, 3);
diff --git a/chip/lm4/lpc.c b/chip/lm4/lpc.c
deleted file mode 100644
index 5b146ba32a..0000000000
--- a/chip/lm4/lpc.c
+++ /dev/null
@@ -1,834 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* LPC module for Chrome EC */
-
-#include "acpi.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "keyboard_protocol.h"
-#include "lpc.h"
-#include "port80.h"
-#include "pwm.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "uart.h"
-#include "util.h"
-
-/* LPC channels */
-#define LPC_CH_ACPI     0  /* ACPI commands */
-#define LPC_CH_PORT80   1  /* Port 80 debug output */
-#define LPC_CH_CMD_DATA 2  /* Data for host commands (args/params/response) */
-#define LPC_CH_KEYBOARD 3  /* 8042 keyboard emulation */
-#define LPC_CH_CMD      4  /* Host commands */
-#define LPC_CH_MEMMAP   5  /* Memory-mapped data */
-#define LPC_CH_COMX     7  /* UART emulation */
-/* LPC pool offsets */
-#define LPC_POOL_OFFS_ACPI       0  /* ACPI commands - 0=in, 1=out */
-#define LPC_POOL_OFFS_PORT80     4  /* Port 80 - 4=in, 5=out */
-#define LPC_POOL_OFFS_COMX       8  /* UART emulation range - 8-15 */
-#define LPC_POOL_OFFS_KEYBOARD  16  /* Keyboard - 16=in, 17=out */
-#define LPC_POOL_OFFS_CMD       20  /* Host commands - 20=in, 21=out */
-#define LPC_POOL_OFFS_CMD_DATA 512  /* Data range for host commands - 512-767 */
-#define LPC_POOL_OFFS_MEMMAP   768  /* Memory-mapped data - 768-1023 */
-/* LPC pool data pointers */
-#define LPC_POOL_ACPI     (LM4_LPC_LPCPOOL + LPC_POOL_OFFS_ACPI)
-#define LPC_POOL_PORT80   (LM4_LPC_LPCPOOL + LPC_POOL_OFFS_PORT80)
-#define LPC_POOL_COMX     (LM4_LPC_LPCPOOL + LPC_POOL_OFFS_COMX)
-#define LPC_POOL_KEYBOARD (LM4_LPC_LPCPOOL + LPC_POOL_OFFS_KEYBOARD)
-#define LPC_POOL_CMD      (LM4_LPC_LPCPOOL + LPC_POOL_OFFS_CMD)
-#define LPC_POOL_CMD_DATA (LM4_LPC_LPCPOOL + LPC_POOL_OFFS_CMD_DATA)
-#define LPC_POOL_MEMMAP   (LM4_LPC_LPCPOOL + LPC_POOL_OFFS_MEMMAP)
-/* LPC COMx I/O address (in x86 I/O address space) */
-#define LPC_COMX_ADDR 0x3f8  /* COM1 */
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-
-static struct host_packet lpc_packet;
-static struct host_cmd_handler_args host_cmd_args;
-static uint8_t host_cmd_flags;   /* Flags from host command */
-
-/* Params must be 32-bit aligned */
-static uint8_t params_copy[EC_LPC_HOST_PACKET_SIZE] __aligned(4);
-static int init_done;
-
-static uint8_t * const cmd_params = (uint8_t *)LPC_POOL_CMD_DATA +
-	EC_LPC_ADDR_HOST_PARAM - EC_LPC_ADDR_HOST_ARGS;
-static struct ec_lpc_host_args * const lpc_host_args =
-	(struct ec_lpc_host_args *)LPC_POOL_CMD_DATA;
-
-static void wait_irq_sent(void)
-{
-	/*
-	 * A hard-coded delay here isn't very elegant, but it's the best we can
-	 * manage (and it's a short delay, so it's not that horrible).  We need
-	 * this because SIRQRIS isn't cleared in continuous mode, and the EC
-	 * has trouble sending more than 1 frame in quiet mode.  Waiting 4 us =
-	 * 2 SERIRQ frames ensures the IRQ has been sent out.
-	 */
-	udelay(4);
-}
-
-#ifdef CONFIG_KEYBOARD_IRQ_GPIO
-static void keyboard_irq_assert(void)
-{
-	/*
-	 * Enforce signal-high for long enough for the signal to be pulled high
-	 * by the external pullup resistor.  This ensures the host will see the
-	 * following falling edge, regardless of the line state before this
-	 * function call.
-	 */
-	uint64_t tstop = get_time().val + MSEC;
-	gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 1);
-	udelay(4);
-	/* Generate a falling edge */
-	gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 0);
-	/* Wait for host senses the interrupt and gets the char. */
-	do {
-		if (get_time().val > tstop)
-			break;
-	} while (lpc_keyboard_has_char());
-	/* Set signal high, now that we've generated the edge */
-	gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 1);
-}
-#else
-static void wait_send_serirq(uint32_t lpcirqctl)
-{
-	LM4_LPC_LPCIRQCTL = lpcirqctl;
-	wait_irq_sent();
-}
-
-/**
- * Manually generate an IRQ to host (edge-trigger).
- *
- * @param irq_num	IRQ number to generate.  Pass 0 to set the AH
- *			(active high) bit.
- *
- * For SERIRQ quite mode, we need to set LM4_LPC_LPCIRQCTL twice.
- * The first one is to assert IRQ (pull low), and then the second one is
- * to de-assert it. This generates a pulse (high-low-high) for an IRQ.
- */
-static void lpc_manual_irq(int irq_num)
-{
-	uint32_t common_bits =
-	    0x00000004 |  /* PULSE */
-	    0x00000002 |  /* ONCHG - for quiet mode */
-	    0x00000001;   /* SND - send immediately */
-
-	/* Send out the IRQ first. */
-	wait_send_serirq((1 << (irq_num + 16)) | common_bits);
-
-	/* Generate a all-high frame to simulate a rising edge. */
-	wait_send_serirq(common_bits);
-}
-
-static inline void keyboard_irq_assert(void)
-{
-	/* Use serirq method. */
-	lpc_manual_irq(1);  /* IRQ#1 */
-}
-#endif
-
-/**
- * Generate SMI pulse to the host chipset via GPIO.
- *
- * If the x86 is in S0, SMI# is sampled at 33MHz, so minimum pulse length is
- * 60ns.  If the x86 is in S3, SMI# is sampled at 32.768KHz, so we need pulse
- * length >61us.  Both are short enough and events are infrequent, so just
- * delay for 65us.
- */
-static void lpc_generate_smi(void)
-{
-	host_event_t smi;
-
-	/* Enforce signal-high for long enough to debounce high */
-	gpio_set_level(GPIO_PCH_SMI_L, 1);
-	udelay(65);
-	/* Generate a falling edge */
-	gpio_set_level(GPIO_PCH_SMI_L, 0);
-	udelay(65);
-	/* Set signal high, now that we've generated the edge */
-	gpio_set_level(GPIO_PCH_SMI_L, 1);
-
-	smi = lpc_get_host_events_by_type(LPC_HOST_EVENT_SMI);
-	if (smi)
-		HOST_EVENT_CPRINTS("smi", smi);
-}
-
-/**
- * Generate SCI pulse to the host chipset via LPC0SCI.
- */
-static void lpc_generate_sci(void)
-{
-	host_event_t sci;
-
-#ifdef CONFIG_SCI_GPIO
-	/* Enforce signal-high for long enough to debounce high */
-	gpio_set_level(CONFIG_SCI_GPIO, 1);
-	udelay(65);
-	/* Generate a falling edge */
-	gpio_set_level(CONFIG_SCI_GPIO, 0);
-	udelay(65);
-	/* Set signal high, now that we've generated the edge */
-	gpio_set_level(CONFIG_SCI_GPIO, 1);
-#else
-	LM4_LPC_LPCCTL |= LM4_LPC_SCI_START;
-#endif
-
-	sci = lpc_get_host_events_by_type(LPC_HOST_EVENT_SCI);
-	if (sci)
-		HOST_EVENT_CPRINTS("sci", sci);
-}
-
-/**
- * Update the level-sensitive wake signal to the AP.
- *
- * @param wake_events	Currently asserted wake events
- */
-static void lpc_update_wake(uint64_t wake_events)
-{
-	/*
-	 * Mask off power button event, since the AP gets that through a
-	 * separate dedicated GPIO.
-	 */
-	wake_events &= ~EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON);
-
-	/* Signal is asserted low when wake events is non-zero */
-	gpio_set_level(GPIO_PCH_WAKE_L, !wake_events);
-}
-
-uint8_t *lpc_get_memmap_range(void)
-{
-	return (uint8_t *)LPC_POOL_MEMMAP;
-}
-
-static void lpc_send_response(struct host_cmd_handler_args *args)
-{
-	uint8_t *out;
-	int size = args->response_size;
-	int csum;
-	int i;
-
-	/* Ignore in-progress on LPC since interface is synchronous anyway */
-	if (args->result == EC_RES_IN_PROGRESS)
-		return;
-
-	/* Handle negative size */
-	if (size < 0) {
-		args->result = EC_RES_INVALID_RESPONSE;
-		size = 0;
-	}
-
-	/* New-style response */
-	lpc_host_args->flags =
-		(host_cmd_flags & ~EC_HOST_ARGS_FLAG_FROM_HOST) |
-		EC_HOST_ARGS_FLAG_TO_HOST;
-
-	lpc_host_args->data_size = size;
-
-	csum = args->command + lpc_host_args->flags +
-		lpc_host_args->command_version +
-		lpc_host_args->data_size;
-
-	for (i = 0, out = (uint8_t *)args->response; i < size; i++, out++)
-		csum += *out;
-
-	lpc_host_args->checksum = (uint8_t)csum;
-
-	/* Fail if response doesn't fit in the param buffer */
-	if (size > EC_PROTO2_MAX_PARAM_SIZE)
-		args->result = EC_RES_INVALID_RESPONSE;
-
-	/* Write result to the data byte.  This sets the TOH status bit. */
-	LPC_POOL_CMD[1] = args->result;
-
-	/* Clear the busy bit, so the host knows the EC is done. */
-	task_disable_irq(LM4_IRQ_LPC);
-	LM4_LPC_ST(LPC_CH_CMD) &= ~LM4_LPC_ST_BUSY;
-	task_enable_irq(LM4_IRQ_LPC);
-}
-
-static void lpc_send_response_packet(struct host_packet *pkt)
-{
-	/* Ignore in-progress on LPC since interface is synchronous anyway */
-	if (pkt->driver_result == EC_RES_IN_PROGRESS)
-		return;
-
-	/* Write result to the data byte.  This sets the TOH status bit. */
-	LPC_POOL_CMD[1] = pkt->driver_result;
-
-	/* Clear the busy bit, so the host knows the EC is done. */
-	task_disable_irq(LM4_IRQ_LPC);
-	LM4_LPC_ST(LPC_CH_CMD) &= ~LM4_LPC_ST_BUSY;
-	task_enable_irq(LM4_IRQ_LPC);
-}
-
-int lpc_keyboard_has_char(void)
-{
-	return (LM4_LPC_ST(LPC_CH_KEYBOARD) & LM4_LPC_ST_TOH) ? 1 : 0;
-}
-
-/* Return true if the FRMH is set */
-int lpc_keyboard_input_pending(void)
-{
-	return (LM4_LPC_ST(LPC_CH_KEYBOARD) & LM4_LPC_ST_FRMH) ? 1 : 0;
-}
-
-/* Put a char to host buffer and send IRQ if specified. */
-void lpc_keyboard_put_char(uint8_t chr, int send_irq)
-{
-	LPC_POOL_KEYBOARD[1] = chr;
-	if (send_irq)
-		keyboard_irq_assert();
-}
-
-void lpc_keyboard_clear_buffer(void)
-{
-	/* Make sure the previous TOH and IRQ has been sent out. */
-	wait_irq_sent();
-
-	LM4_LPC_ST(LPC_CH_KEYBOARD) &= ~LM4_LPC_ST_TOH;
-
-	/* Ensure there is no TOH set in this period. */
-	wait_irq_sent();
-}
-
-void lpc_keyboard_resume_irq(void)
-{
-	if (lpc_keyboard_has_char())
-		keyboard_irq_assert();
-}
-
-#ifdef CONFIG_UART_HOST
-
-int lpc_comx_has_char(void)
-{
-	return LM4_LPC_ST(LPC_CH_COMX) & LM4_LPC_ST_FRMH;
-}
-
-int lpc_comx_get_char(void)
-{
-	return LPC_POOL_COMX[0];
-}
-
-void lpc_comx_put_char(int c)
-{
-	LPC_POOL_COMX[1] = c;
-
-	/*
-	 * We could in theory manually trigger an IRQ, like we do for the 8042
-	 * keyboard interface, but neither the kernel nor BIOS seems to require
-	 * this.
-	 */
-}
-
-#endif /* CONFIG_UART_HOST */
-
-/**
- * Update the host event status.
- *
- * Sends a pulse if masked event status becomes non-zero:
- *   - SMI pulse via EC_SMI_L GPIO
- *   - SCI pulse via LPC0SCI
- */
-void lpc_update_host_event_status(void)
-{
-	int need_sci = 0;
-	int need_smi = 0;
-
-	if (!init_done)
-		return;
-
-	/* Disable LPC interrupt while updating status register */
-	task_disable_irq(LM4_IRQ_LPC);
-
-	if (lpc_get_host_events_by_type(LPC_HOST_EVENT_SMI)) {
-		/* Only generate SMI for first event */
-		if (!(LM4_LPC_ST(LPC_CH_ACPI) & LM4_LPC_ST_SMI))
-			need_smi = 1;
-		LM4_LPC_ST(LPC_CH_ACPI) |= LM4_LPC_ST_SMI;
-	} else
-		LM4_LPC_ST(LPC_CH_ACPI) &= ~LM4_LPC_ST_SMI;
-
-	if (lpc_get_host_events_by_type(LPC_HOST_EVENT_SCI)) {
-		/* Generate SCI for every event */
-		need_sci = 1;
-		LM4_LPC_ST(LPC_CH_ACPI) |= LM4_LPC_ST_SCI;
-	} else
-		LM4_LPC_ST(LPC_CH_ACPI) &= ~LM4_LPC_ST_SCI;
-
-	/* Copy host events to mapped memory */
-	*(host_event_t *)host_get_memmap(EC_MEMMAP_HOST_EVENTS) =
-				lpc_get_host_events();
-
-	task_enable_irq(LM4_IRQ_LPC);
-
-	/* Process the wake events. */
-	lpc_update_wake(lpc_get_host_events_by_type(LPC_HOST_EVENT_WAKE));
-
-	/* Send pulse on SMI signal if needed */
-	if (need_smi)
-		lpc_generate_smi();
-
-	/* ACPI 5.0-12.6.1: Generate SCI for SCI_EVT=1. */
-	if (need_sci)
-		lpc_generate_sci();
-}
-
-void lpc_set_acpi_status_mask(uint8_t mask)
-{
-	uint32_t set_mask = 0;
-	if (mask & EC_LPC_STATUS_BURST_MODE)
-		set_mask |= LM4_LPC_ST_BURST;
-
-	LM4_LPC_ST(LPC_CH_ACPI) |= set_mask;
-}
-
-void lpc_clear_acpi_status_mask(uint8_t mask)
-{
-	uint32_t clear_mask = 0;
-	if (mask & EC_LPC_STATUS_BURST_MODE)
-		clear_mask |= LM4_LPC_ST_BURST;
-
-	LM4_LPC_ST(LPC_CH_ACPI) &= ~clear_mask;
-}
-
-int lpc_get_pltrst_asserted(void)
-{
-	return (LM4_LPC_LPCSTS & BIT(10)) ? 1 : 0;
-}
-
-/**
- * Handle write to ACPI I/O port
- *
- * @param is_cmd	Is write command (is_cmd=1) or data (is_cmd=0)
- */
-static void handle_acpi_write(int is_cmd)
-{
-	uint8_t value, result;
-
-	/* Set the busy bit */
-	LM4_LPC_ST(LPC_CH_ACPI) |= LM4_LPC_ST_BUSY;
-
-	/* Read command/data; this clears the FRMH status bit. */
-	value = LPC_POOL_ACPI[0];
-
-	/* Handle whatever this was. */
-	if (acpi_ap_to_ec(is_cmd, value, &result))
-		LPC_POOL_ACPI[1] = result;
-
-	/* Clear the busy bit */
-	LM4_LPC_ST(LPC_CH_ACPI) &= ~LM4_LPC_ST_BUSY;
-
-	/*
-	 * ACPI 5.0-12.6.1: Generate SCI for Input Buffer Empty / Output Buffer
-	 * Full condition on the kernel channel.
-	 */
-	lpc_generate_sci();
-}
-
-/**
- * Handle write to host command I/O ports.
- *
- * @param is_cmd	Is write command (1) or data (0)?
- */
-static void handle_host_write(int is_cmd)
-{
-	/* Ignore data writes or overlapping commands from host */
-	uint32_t is_overlapping = LM4_LPC_ST(LPC_CH_CMD) & LM4_LPC_ST_BUSY;
-	if (!is_cmd || is_overlapping) {
-		if (is_overlapping)
-			CPRINTS("LPC Ignoring overlapping HC");
-		LM4_LPC_ST(LPC_CH_CMD) &= ~LM4_LPC_ST_FRMH;
-		return;
-	}
-
-	/* Set the busy bit */
-	LM4_LPC_ST(LPC_CH_CMD) |= LM4_LPC_ST_BUSY;
-
-	/*
-	 * Read the command byte.  This clears the FRMH bit in
-	 * the status byte.
-	 */
-	host_cmd_args.command = LPC_POOL_CMD[0];
-
-	host_cmd_args.result = EC_RES_SUCCESS;
-	host_cmd_args.send_response = lpc_send_response;
-	host_cmd_flags = lpc_host_args->flags;
-
-	/* See if we have an old or new style command */
-	if (host_cmd_args.command == EC_COMMAND_PROTOCOL_3) {
-		lpc_packet.send_response = lpc_send_response_packet;
-
-		lpc_packet.request = (const void *)LPC_POOL_CMD_DATA;
-		lpc_packet.request_temp = params_copy;
-		lpc_packet.request_max = sizeof(params_copy);
-		/* Don't know the request size so pass in the entire buffer */
-		lpc_packet.request_size = EC_LPC_HOST_PACKET_SIZE;
-
-		lpc_packet.response = (void *)LPC_POOL_CMD_DATA;
-		lpc_packet.response_max = EC_LPC_HOST_PACKET_SIZE;
-		lpc_packet.response_size = 0;
-
-		lpc_packet.driver_result = EC_RES_SUCCESS;
-		host_packet_receive(&lpc_packet);
-		return;
-
-	} else if (host_cmd_flags & EC_HOST_ARGS_FLAG_FROM_HOST) {
-		/* Version 2 (link) style command */
-		int size = lpc_host_args->data_size;
-		int csum, i;
-
-		host_cmd_args.version = lpc_host_args->command_version;
-		host_cmd_args.params = params_copy;
-		host_cmd_args.params_size = size;
-		host_cmd_args.response = cmd_params;
-		host_cmd_args.response_max = EC_PROTO2_MAX_PARAM_SIZE;
-		host_cmd_args.response_size = 0;
-
-		/* Verify params size */
-		if (size > EC_PROTO2_MAX_PARAM_SIZE) {
-			host_cmd_args.result = EC_RES_INVALID_PARAM;
-		} else {
-			const uint8_t *src = cmd_params;
-			uint8_t *copy = params_copy;
-
-			/*
-			 * Verify checksum and copy params out of LPC space.
-			 * This ensures the data acted on by the host command
-			 * handler can't be changed by host writes after the
-			 * checksum is verified.
-			 */
-			csum = host_cmd_args.command +
-				host_cmd_flags +
-				host_cmd_args.version +
-				host_cmd_args.params_size;
-
-			for (i = 0; i < size; i++) {
-				csum += *src;
-				*(copy++) = *(src++);
-			}
-
-			if ((uint8_t)csum != lpc_host_args->checksum)
-				host_cmd_args.result = EC_RES_INVALID_CHECKSUM;
-		}
-	} else {
-		/* Old style command, now unsupported */
-		host_cmd_args.result = EC_RES_INVALID_COMMAND;
-	}
-
-	/* Hand off to host command handler */
-	host_command_received(&host_cmd_args);
-}
-
-#ifdef CONFIG_CHIPSET_RESET_HOOK
-static void lpc_chipset_reset(void)
-{
-	hook_notify(HOOK_CHIPSET_RESET);
-}
-DECLARE_DEFERRED(lpc_chipset_reset);
-#endif
-
-/**
- * LPC interrupt handler
- */
-void lpc_interrupt(void)
-{
-	uint32_t mis = LM4_LPC_LPCMIS;
-	uint32_t st;
-
-	/* Clear the interrupt bits we're handling */
-	LM4_LPC_LPCIC = mis;
-
-#ifdef HAS_TASK_HOSTCMD
-	/* Handle ACPI command and data writes */
-	st = LM4_LPC_ST(LPC_CH_ACPI);
-	if (st & LM4_LPC_ST_FRMH)
-		handle_acpi_write(st & LM4_LPC_ST_CMD);
-
-	/* Handle user command writes */
-	st = LM4_LPC_ST(LPC_CH_CMD);
-	if (st & LM4_LPC_ST_FRMH)
-		handle_host_write(st & LM4_LPC_ST_CMD);
-#endif
-
-	/*
-	 * Handle port 80 writes (CH0MIS1).  Due to crosbug.com/p/12349 the
-	 * interrupt status (mis & LM4_LPC_INT_MASK(LPC_CH_PORT80, 2))
-	 * apparently gets lost on back-to-back writes to port 80, so check the
-	 * FRMH bit in the channel status register to see if a write is
-	 * pending.  Loop to handle bursts of back-to-back writes.
-	 */
-	while (LM4_LPC_ST(LPC_CH_PORT80) & LM4_LPC_ST_FRMH)
-		port_80_write(LPC_POOL_PORT80[0]);
-
-#ifdef HAS_TASK_KEYPROTO
-	/* Handle keyboard interface writes */
-	st = LM4_LPC_ST(LPC_CH_KEYBOARD);
-	if (st & LM4_LPC_ST_FRMH)
-		keyboard_host_write(LPC_POOL_KEYBOARD[0], st & LM4_LPC_ST_CMD);
-
-	if (mis & LM4_LPC_INT_MASK(LPC_CH_KEYBOARD, 1)) {
-		/* Host read data; wake up task to send remaining bytes */
-		task_wake(TASK_ID_KEYPROTO);
-	}
-#endif
-
-#ifdef CONFIG_UART_HOST
-	/* Handle COMx */
-	if (lpc_comx_has_char()) {
-		/* Copy a character to the UART if there's space */
-		if (uart_comx_putc_ok())
-			uart_comx_putc(lpc_comx_get_char());
-	}
-#endif
-
-	/* Debugging: print changes to LPC0RESET */
-	if (mis & BIT(31)) {
-		if (LM4_LPC_LPCSTS & BIT(10)) {
-			int i;
-
-			/* Store port 80 reset event */
-			port_80_write(PORT_80_EVENT_RESET);
-
-			/*
-			 * Workaround for crosbug.com/p/12349; clear all FRMH
-			 * bits so host writes will trigger interrupts.
-			 */
-			for (i = 0; i < 8; i++)
-				LM4_LPC_ST(i) &= ~LM4_LPC_ST_FRMH;
-
-#ifdef CONFIG_CHIPSET_RESET_HOOK
-			/* Notify HOOK_CHIPSET_RESET */
-			hook_call_deferred(&lpc_chipset_reset_data, MSEC);
-#endif
-		}
-
-		CPRINTS("LPC RESET# %sasserted",
-			lpc_get_pltrst_asserted() ? "" : "de");
-	}
-}
-DECLARE_IRQ(LM4_IRQ_LPC, lpc_interrupt, 2);
-
-/* Enable LPC ACPI-EC interrupts */
-void lpc_enable_acpi_interrupts(void)
-{
-	LM4_LPC_LPCIM |= LM4_LPC_INT_MASK(LPC_CH_ACPI, 6);
-}
-
-/* Disable LPC ACPI-EC interrupts */
-void lpc_disable_acpi_interrupts(void)
-{
-	LM4_LPC_LPCIM &= ~(LM4_LPC_INT_MASK(LPC_CH_ACPI, 6));
-}
-
-static void lpc_init(void)
-{
-	/* Enable LPC clock in run and sleep modes. */
-	clock_enable_peripheral(CGC_OFFSET_LPC, 0x1,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-
-	LM4_LPC_LPCIM = 0;
-	LM4_LPC_LPCCTL = 0;
-	LM4_LPC_LPCIRQCTL = 0;
-
-	/* Configure GPIOs */
-	gpio_config_module(MODULE_LPC, 1);
-
-	/*
-	 * Set LPC channel 0 to I/O address 0x62 (data) / 0x66 (command),
-	 * single endpoint, offset 0 for host command/writes and 1 for EC
-	 * data writes, pool bytes 0(data)/1(cmd)
-	 */
-	LM4_LPC_ADR(LPC_CH_ACPI) = EC_LPC_ADDR_ACPI_DATA;
-	LM4_LPC_CTL(LPC_CH_ACPI) = (LPC_POOL_OFFS_ACPI << (5 - 1));
-	LM4_LPC_ST(LPC_CH_ACPI) = 0;
-	/* Unmask interrupt for host command and data writes */
-	LM4_LPC_LPCIM |= LM4_LPC_INT_MASK(LPC_CH_ACPI, 6);
-
-	/*
-	 * Set LPC channel 1 to I/O address 0x80 (data), single endpoint,
-	 * pool bytes 4(data)/5(cmd).
-	 */
-	LM4_LPC_ADR(LPC_CH_PORT80) = 0x80;
-	LM4_LPC_CTL(LPC_CH_PORT80) = (LPC_POOL_OFFS_PORT80 << (5 - 1));
-	/* Unmask interrupt for host data writes */
-	LM4_LPC_LPCIM |= LM4_LPC_INT_MASK(LPC_CH_PORT80, 2);
-
-	/*
-	 * Set LPC channel 2 to I/O address 0x880, range endpoint,
-	 * arbitration disabled, pool bytes 512-639.  To access this from
-	 * x86, use the following command to set GEN_LPC2:
-	 *
-	 *   pci_write32 0 0x1f 0 0x88 0x007c0801
-	 */
-	LM4_LPC_ADR(LPC_CH_CMD_DATA) = EC_LPC_ADDR_HOST_ARGS;
-	LM4_LPC_CTL(LPC_CH_CMD_DATA) = 0x8019 |
-		(LPC_POOL_OFFS_CMD_DATA << (5 - 1));
-
-	/*
-	 * Set LPC channel 3 to I/O address 0x60 (data) / 0x64 (command),
-	 * single endpoint, offset 0 for host command/writes and 1 for EC
-	 * data writes, pool bytes 0(data)/1(cmd)
-	 */
-	LM4_LPC_ADR(LPC_CH_KEYBOARD) = 0x60;
-	LM4_LPC_CTL(LPC_CH_KEYBOARD) = (BIT(24)/* IRQSEL1 */) |
-		(0 << 18/* IRQEN1 */) | (LPC_POOL_OFFS_KEYBOARD << (5 - 1));
-	LM4_LPC_ST(LPC_CH_KEYBOARD) = 0;
-	/* Unmask interrupt for host command/data writes and data reads */
-	LM4_LPC_LPCIM |= LM4_LPC_INT_MASK(LPC_CH_KEYBOARD, 7);
-
-	/*
-	 * Set LPC channel 4 to I/O address 0x200 (data) / 0x204 (command),
-	 * single endpoint, offset 0 for host command/writes and 1 for EC
-	 * data writes, pool bytes 0(data)/1(cmd)
-	 */
-	LM4_LPC_ADR(LPC_CH_CMD) = EC_LPC_ADDR_HOST_DATA;
-	LM4_LPC_CTL(LPC_CH_CMD) = (LPC_POOL_OFFS_CMD << (5 - 1));
-	/*
-	 * Initialize status bits to 0.  We never set the ACPI burst status bit,
-	 * so this guarantees that at least one status bit will always be 0.
-	 * This is used by comm_lpc.c to detect that the EC is present on the
-	 * LPC bus.  See crosbug.com/p/10963.
-	 */
-	LM4_LPC_ST(LPC_CH_CMD) = 0;
-	/* Unmask interrupt for host command writes */
-	LM4_LPC_LPCIM |= LM4_LPC_INT_MASK(LPC_CH_CMD, 4);
-
-	/*
-	 * Set LPC channel 5 to I/O address 0x900, range endpoint,
-	 * arbitration enabled, pool bytes 768-1023.  To access this from
-	 * x86, use the following command to set GEN_LPC3:
-	 *
-	 *   pci_write32 0 0x1f 0 0x8c 0x007c0901
-	 */
-	LM4_LPC_ADR(LPC_CH_MEMMAP) = EC_LPC_ADDR_MEMMAP;
-	LM4_LPC_CTL(LPC_CH_MEMMAP) = 0x0019 | (LPC_POOL_OFFS_MEMMAP << (5 - 1));
-
-#ifdef CONFIG_UART_HOST
-	/*
-	 * Set LPC channel 7 to COM port I/O address.  Note that channel 7
-	 * ignores the TYPE bit and is always an 8-byte range.
-	 */
-	LM4_LPC_ADR(LPC_CH_COMX) = LPC_COMX_ADDR;
-	/*
-	 * In theory we could configure IRQSELs and set IRQEN2/CX, and then the
-	 * host could enable IRQs on its own.  So far that hasn't been
-	 * necessary, and due to the issues with IRQs (see wait_irq_sent()
-	 * above) it might not work anyway.
-	 */
-	LM4_LPC_CTL(LPC_CH_COMX) = 0x0004 | (LPC_POOL_OFFS_COMX << (5 - 1));
-	/* Enable COMx emulation for reads and writes. */
-	LM4_LPC_LPCDMACX = 0x00310000;
-	/*
-	 * Unmask interrupt for host data writes.  We don't need interrupts for
-	 * reads, because there's no flow control in that direction; LPC is
-	 * much faster than the UART, and the UART doesn't have anywhere
-	 * sensible to buffer input anyway.
-	 */
-	LM4_LPC_LPCIM |= LM4_LPC_INT_MASK(LPC_CH_COMX, 2);
-#endif /* CONFIG_UART_HOST */
-
-	/*
-	 * Unmask LPC bus reset interrupt.  This lets us monitor the PCH
-	 * PLTRST# signal for debugging.
-	 */
-	LM4_LPC_LPCIM |= BIT(31);
-
-	/* Enable LPC channels */
-	LM4_LPC_LPCCTL = LM4_LPC_SCI_CLK_1 |
-		BIT(LPC_CH_ACPI) |
-		BIT(LPC_CH_PORT80) |
-		BIT(LPC_CH_CMD_DATA) |
-		BIT(LPC_CH_KEYBOARD) |
-		BIT(LPC_CH_CMD) |
-		BIT(LPC_CH_MEMMAP);
-
-#ifdef CONFIG_UART_HOST
-	LM4_LPC_LPCCTL |= 1 << LPC_CH_COMX;
-#endif
-
-	/*
-	 * Ensure the EC (slave) has control of the memory-mapped I/O space.
-	 * Once the EC has won arbitration for the memory-mapped space, it will
-	 * keep control of it until it writes the last byte in the space.
-	 * (That never happens; we can't use the last byte in the space because
-	 * ACPI can't see it anyway.)
-	 */
-	while (!(LM4_LPC_ST(LPC_CH_MEMMAP) & 0x10)) {
-		/* Clear HW1ST */
-		LM4_LPC_ST(LPC_CH_MEMMAP) &= ~0x40;
-		/* Do a slave write; this should cause SW1ST to be set */
-		*LPC_POOL_MEMMAP = *LPC_POOL_MEMMAP;
-	}
-
-	/* Initialize host args and memory map to all zero */
-	memset(lpc_host_args, 0, sizeof(*lpc_host_args));
-	memset(lpc_get_memmap_range(), 0, EC_MEMMAP_SIZE);
-
-	/* We support LPC args and version 3 protocol */
-	*(lpc_get_memmap_range() + EC_MEMMAP_HOST_CMD_FLAGS) =
-		EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED |
-		EC_HOST_CMD_FLAG_VERSION_3;
-
-	/* Enable LPC interrupt */
-	task_enable_irq(LM4_IRQ_LPC);
-
-#ifdef CONFIG_UART_HOST
-	/* Enable COMx UART */
-	uart_comx_enable();
-#endif
-
-	/* Sufficiently initialized */
-	init_done = 1;
-
-	/* Update host events now that we can copy them to memmap */
-	lpc_update_host_event_status();
-}
-/*
- * Set prio to higher than default; this way LPC memory mapped data is ready
- * before other inits try to initialize their memmap data.
- */
-DECLARE_HOOK(HOOK_INIT, lpc_init, HOOK_PRIO_INIT_LPC);
-
-static void lpc_tick(void)
-{
-	/*
-	 * Make sure pending LPC interrupts have been processed.
-	 * This works around a LM4 bug where host writes sometimes
-	 * don't trigger interrupts.  See crosbug.com/p/13965.
-	 */
-	task_trigger_irq(LM4_IRQ_LPC);
-}
-DECLARE_HOOK(HOOK_TICK, lpc_tick, HOOK_PRIO_DEFAULT);
-
-/**
- * Get protocol information
- */
-static enum ec_status lpc_get_protocol_info(struct host_cmd_handler_args *args)
-{
-	struct ec_response_get_protocol_info *r = args->response;
-
-	memset(r, 0, sizeof(*r));
-	r->protocol_versions = BIT(2) | BIT(3);
-	r->max_request_packet_size = EC_LPC_HOST_PACKET_SIZE;
-	r->max_response_packet_size = EC_LPC_HOST_PACKET_SIZE;
-	r->flags = 0;
-
-	args->response_size = sizeof(*r);
-
-	return EC_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO,
-		     lpc_get_protocol_info,
-		     EC_VER_MASK(0));
diff --git a/chip/lm4/peci.c b/chip/lm4/peci.c
deleted file mode 100644
index b3b54a64bc..0000000000
--- a/chip/lm4/peci.c
+++ /dev/null
@@ -1,152 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* PECI interface for Chrome EC */
-
-#include "chipset.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "peci.h"
-#include "registers.h"
-#include "temp_sensor.h"
-#include "util.h"
-
-/* Initial PECI baud rate */
-#define PECI_BAUD_RATE 100000
-
-/* Polling interval for PECI, in ms */
-#define PECI_POLL_INTERVAL_MS 250
-
-/*
- * Internal and external path delays, in ns.  The external delay is a
- * best-guess measurement, but we're fairly tolerant of a bad guess because
- * PECI_BAUD_RATE is slow compared to PECI's actual maximum baud rate.
- */
-#define PECI_TD_FET_NS 60
-#define PECI_TD_INT_NS 80
-
-/* Number of controller retries. Should be between 0 and 7. */
-#define PECI_RETRY_COUNT 4
-
-/* Timing negotiation error bypass. 1 = on. 0 = off. */
-#define PECI_ERROR_BYPASS 1
-
-#define TEMP_AVG_LENGTH 4  /* Should be power of 2 */
-static int temp_vals[TEMP_AVG_LENGTH];
-static int temp_idx;
-
-int peci_get_cpu_temp(void)
-{
-	int v = LM4_PECI_M0D0 & 0xffff;
-
-	if (v >= 0x8000 && v <= 0x8fff)
-		return -1;
-
-	return v >> 6;
-}
-
-int peci_temp_sensor_get_val(int idx, int *temp_ptr)
-{
-	int sum = 0;
-	int success_cnt = 0;
-	int i;
-
-	if (!chipset_in_state(CHIPSET_STATE_ON))
-		return EC_ERROR_NOT_POWERED;
-
-	for (i = 0; i < TEMP_AVG_LENGTH; ++i) {
-		if (temp_vals[i] >= 0) {
-			success_cnt++;
-			sum += temp_vals[i];
-		}
-	}
-
-	/*
-	 * Require at least two valid samples. When the AP transitions into S0,
-	 * it is possible, depending on the timing of the PECI sample, to read
-	 * an invalid temperature. This is very rare, but when it does happen
-	 * the temperature returned is CONFIG_PECI_TJMAX. Requiring two valid
-	 * samples here assures us that one bad maximum temperature reading
-	 * when entering S0 won't cause us to trigger an over temperature.
-	 */
-	if (success_cnt < 2)
-		return EC_ERROR_UNKNOWN;
-
-	*temp_ptr = sum / success_cnt;
-	return EC_SUCCESS;
-}
-
-static void peci_temp_sensor_poll(void)
-{
-	temp_vals[temp_idx] = peci_get_cpu_temp();
-	temp_idx = (temp_idx + 1) & (TEMP_AVG_LENGTH - 1);
-}
-DECLARE_HOOK(HOOK_TICK, peci_temp_sensor_poll, HOOK_PRIO_TEMP_SENSOR);
-
-static void peci_freq_changed(void)
-{
-	int freq = clock_get_freq();
-	int baud;
-
-	/* Disable polling while reconfiguring */
-	LM4_PECI_CTL = 0;
-
-	/*
-	 * Calculate baud setting from desired rate, compensating for internal
-	 * and external delays.
-	 */
-	baud = freq / (4 * PECI_BAUD_RATE) - 2;
-	baud -= (freq / 1000000) * (PECI_TD_FET_NS + PECI_TD_INT_NS) / 1000;
-
-	/* Set baud rate and polling rate */
-	LM4_PECI_DIV = (baud << 16) |
-		(PECI_POLL_INTERVAL_MS * (freq / 1000 / 4096));
-
-	/* Set up temperature monitoring to report in degrees K */
-	LM4_PECI_CTL = ((CONFIG_PECI_TJMAX + 273) << 22) | 0x0001 |
-		       (PECI_RETRY_COUNT << 12) |
-		       (PECI_ERROR_BYPASS << 11);
-}
-DECLARE_HOOK(HOOK_FREQ_CHANGE, peci_freq_changed, HOOK_PRIO_DEFAULT);
-
-static void peci_init(void)
-{
-	int i;
-
-	/* Enable the PECI module in run and sleep modes. */
-	clock_enable_peripheral(CGC_OFFSET_PECI, 0x1,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-
-	/* Configure GPIOs */
-	gpio_config_module(MODULE_PECI, 1);
-
-	/* Set initial clock frequency */
-	peci_freq_changed();
-
-	/* Initialize temperature reading buffer to a valid value. */
-	for (i = 0; i < TEMP_AVG_LENGTH; ++i)
-		temp_vals[i] = 300; /* 27 C */
-}
-DECLARE_HOOK(HOOK_INIT, peci_init, HOOK_PRIO_DEFAULT);
-
-/*****************************************************************************/
-/* Console commands */
-
-static int command_peci_temp(int argc, char **argv)
-{
-	int t = peci_get_cpu_temp();
-	if (t == -1) {
-		ccprintf("PECI error 0x%04x\n", LM4_PECI_M0D0 & 0xffff);
-		return EC_ERROR_UNKNOWN;
-	}
-	ccprintf("CPU temp = %d K = %d C\n", t, K_TO_C(t));
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(pecitemp, command_peci_temp,
-			NULL,
-			"Print CPU temperature");
diff --git a/chip/lm4/pwm.c b/chip/lm4/pwm.c
deleted file mode 100644
index 38ce61714d..0000000000
--- a/chip/lm4/pwm.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* PWM control module for LM4.
- *
- * On this chip, the PWM logic is implemented by the hardware FAN modules.
- */
-
-#include "clock.h"
-#include "fan.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "util.h"
-
-void pwm_enable(enum pwm_channel ch, int enabled)
-{
-	fan_set_enabled(pwm_channels[ch].channel, enabled);
-}
-
-int pwm_get_enabled(enum pwm_channel ch)
-{
-	return fan_get_enabled(pwm_channels[ch].channel);
-}
-
-void pwm_set_duty(enum pwm_channel ch, int percent)
-{
-	if (percent < 0)
-		percent = 0;
-	else if (percent > 100)
-		percent = 100;
-
-	/* Assume the fan control is active high and invert it ourselves */
-	if (pwm_channels[ch].flags & PWM_CONFIG_ACTIVE_LOW)
-		percent = 100 - percent;
-
-	/* Always enable the channel */
-	pwm_enable(ch, 1);
-
-	/* Set the duty cycle */
-	fan_set_duty(pwm_channels[ch].channel, percent);
-}
-
-int pwm_get_duty(enum pwm_channel ch)
-{
-	int percent = fan_get_duty(pwm_channels[ch].channel);
-
-	if (pwm_channels[ch].flags & PWM_CONFIG_ACTIVE_LOW)
-		percent = 100 - percent;
-
-	return percent;
-}
-
-static void pwm_init(void)
-{
-	int i;
-
-	for (i = 0; i < PWM_CH_COUNT; ++i)
-		fan_channel_setup(pwm_channels[i].channel,
-				       (pwm_channels[i].flags &
-					PWM_CONFIG_HAS_RPM_MODE)
-				       ? FAN_USE_RPM_MODE : 0);
-}
-
-/* The chip-specific fan module initializes before this. */
-DECLARE_HOOK(HOOK_INIT, pwm_init, HOOK_PRIO_INIT_PWM);
diff --git a/chip/lm4/pwm_chip.h b/chip/lm4/pwm_chip.h
deleted file mode 100644
index ada5785495..0000000000
--- a/chip/lm4/pwm_chip.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* LM4-specific PWM module for Chrome EC */
-
-#ifndef __CROS_EC_PWM_CHIP_H
-#define __CROS_EC_PWM_CHIP_H
-
-/* Data structure to define PWM channels. */
-struct pwm_t {
-	/* PWM channel ID */
-	int channel;
-	/* PWM channel flags. See include/pwm.h */
-	uint32_t flags;
-};
-
-extern const struct pwm_t pwm_channels[];
-
-#endif /* __CROS_EC_PWM_CHIP_H */
diff --git a/chip/lm4/registers.h b/chip/lm4/registers.h
deleted file mode 100644
index 0c59da19f6..0000000000
--- a/chip/lm4/registers.h
+++ /dev/null
@@ -1,600 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Register map for LM4x processor
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#define __CROS_EC_REGISTERS_H
-
-#include "common.h"
-
-#define LM4_UART_CH0_BASE      0x4000c000
-#define LM4_UART_CH1_BASE      0x4000d000
-#define LM4_UART_CH_SEP        0x00001000
-static inline int lm4_uart_addr(int ch, int offset)
-{
-	return offset + LM4_UART_CH0_BASE + LM4_UART_CH_SEP * ch;
-}
-#define LM4UARTREG(ch, offset) REG32(lm4_uart_addr(ch, offset))
-#define LM4_UART_DR(ch)        LM4UARTREG(ch, 0x000)
-#define LM4_UART_FR(ch)        LM4UARTREG(ch, 0x018)
-#define LM4_UART_IBRD(ch)      LM4UARTREG(ch, 0x024)
-#define LM4_UART_FBRD(ch)      LM4UARTREG(ch, 0x028)
-#define LM4_UART_LCRH(ch)      LM4UARTREG(ch, 0x02c)
-#define LM4_UART_CTL(ch)       LM4UARTREG(ch, 0x030)
-#define LM4_UART_IFLS(ch)      LM4UARTREG(ch, 0x034)
-#define LM4_UART_IM(ch)        LM4UARTREG(ch, 0x038)
-#define LM4_UART_ICR(ch)       LM4UARTREG(ch, 0x044)
-#define LM4_UART_DMACTL(ch)    LM4UARTREG(ch, 0x048)
-#define LM4_UART_CC(ch)        LM4UARTREG(ch, 0xfc8)
-
-#define LM4_SSI_BASE           0x40008000
-#define LM4_SSI_CH_SEP         0x40001000
-static inline int lm4_spi_addr(int ch, int offset)
-{
-	return offset + LM4_SSI_BASE + LM4_SSI_CH_SEP * ch;
-}
-#define LM4SSIREG(ch, offset)  REG32(lm4_spi_addr(ch, offset))
-#define LM4_SSI_CR0(ch)        LM4SSIREG(ch, 0x000)
-#define LM4_SSI_CR1(ch)        LM4SSIREG(ch, 0x004)
-#define LM4_SSI_DR(ch)         LM4SSIREG(ch, 0x008)
-#define LM4_SSI_SR(ch)         LM4SSIREG(ch, 0x00c)
-#define LM4_SSI_SR_TFE         BIT(0)  /* Transmit FIFO empty */
-#define LM4_SSI_SR_TNF         BIT(1)  /* Transmit FIFO not full */
-#define LM4_SSI_SR_RNE         BIT(2)  /* Receive FIFO not empty */
-#define LM4_SSI_SR_RFF         BIT(3)  /* Receive FIFO full */
-#define LM4_SSI_SR_BSY         BIT(4)  /* Busy */
-#define LM4_SSI_CPSR(ch)       LM4SSIREG(ch, 0x010)
-#define LM4_SSI_IM(ch)         LM4SSIREG(ch, 0x014)
-#define LM4_SSI_RIS(ch)        LM4SSIREG(ch, 0x018)
-#define LM4_SSI_MIS(ch)        LM4SSIREG(ch, 0x01c)
-#define LM4_SSI_ICR(ch)        LM4SSIREG(ch, 0x020)
-#define LM4_SSI_DMACTL(ch)     LM4SSIREG(ch, 0x024)
-#define LM4_SSI_CC(ch)         LM4SSIREG(ch, 0xfc8)
-
-#define LM4_ADC_ADCACTSS       REG32(0x40038000)
-#define LM4_ADC_ADCRIS         REG32(0x40038004)
-#define LM4_ADC_ADCIM          REG32(0x40038008)
-#define LM4_ADC_ADCISC         REG32(0x4003800c)
-#define LM4_ADC_ADCOSTAT       REG32(0x40038010)
-#define LM4_ADC_ADCEMUX        REG32(0x40038014)
-#define LM4_ADC_ADCUSTAT       REG32(0x40038018)
-#define LM4_ADC_ADCSSPRI       REG32(0x40038020)
-#define LM4_ADC_ADCSPC         REG32(0x40038024)
-#define LM4_ADC_ADCPSSI        REG32(0x40038028)
-#define LM4_ADC_ADCSAC         REG32(0x40038030)
-#define LM4_ADC_ADCCTL         REG32(0x40038038)
-#define LM4_ADC_ADCCC          REG32(0x40038fc8)
-#define LM4_ADC_SS0_BASE       0x40038040
-#define LM4_ADC_SS1_BASE       0x40038060
-#define LM4_ADC_SS2_BASE       0x40038080
-#define LM4_ADC_SS3_BASE       0x400380a0
-#define LM4_ADC_SS_SEP         0x00000020
-static inline int lm4_adc_addr(int ss, int offset)
-{
-	return offset + LM4_ADC_SS0_BASE + LM4_ADC_SS_SEP * ss;
-}
-#define LM4ADCREG(ss, offset)  REG32(lm4_adc_addr(ss, offset))
-#define LM4_ADC_SSMUX(ss)      LM4ADCREG(ss, 0x000)
-#define LM4_ADC_SSCTL(ss)      LM4ADCREG(ss, 0x004)
-#define LM4_ADC_SSFIFO(ss)     LM4ADCREG(ss, 0x008)
-#define LM4_ADC_SSFSTAT(ss)    LM4ADCREG(ss, 0x00c)
-#define LM4_ADC_SSOP(ss)       LM4ADCREG(ss, 0x010)
-#define LM4_ADC_SSEMUX(ss)     LM4ADCREG(ss, 0x018)
-
-#define LM4_LPC_LPCCTL         REG32(0x40080000)
-#define LM4_LPC_SCI_START      BIT(9)  /* Start a pulse on LPC0SCI signal */
-#define LM4_LPC_SCI_CLK_1      (0 << 10) /* SCI asserted for 1 clock period */
-#define LM4_LPC_SCI_CLK_2      (1 << 10) /* SCI asserted for 2 clock periods */
-#define LM4_LPC_SCI_CLK_4      (2 << 10) /* SCI asserted for 4 clock periods */
-#define LM4_LPC_SCI_CLK_8      (3 << 10) /* SCI asserted for 8 clock periods */
-#define LM4_LPC_LPCSTS         REG32(0x40080004)
-#define LM4_LPC_LPCIRQCTL      REG32(0x40080008)
-#define LM4_LPC_LPCIRQST       REG32(0x4008000c)
-#define LM4_LPC_LPCIM          REG32(0x40080100)
-#define LM4_LPC_LPCRIS         REG32(0x40080104)
-#define LM4_LPC_LPCMIS         REG32(0x40080108)
-#define LM4_LPC_LPCIC          REG32(0x4008010c)
-#define LM4_LPC_INT_MASK(ch, bits) ((bits) << (4 * (ch)))
-#define LM4_LPC_LPCDMACX       REG32(0x40080120)
-#define LM4_LPC_CH0_BASE       0x40080010
-#define LM4_LPC_CH1_BASE       0x40080020
-#define LM4_LPC_CH2_BASE       0x40080030
-#define LM4_LPC_CH3_BASE       0x40080040
-#define LM4_LPC_CH4_BASE       0x40080050
-#define LM4_LPC_CH5_BASE       0x40080060
-#define LM4_LPC_CH6_BASE       0x40080070
-#define LM4_LPC_CH7_BASE       0x40080080
-#define LM4_LPC_CH_SEP         0x00000010
-static inline int lm4_lpc_addr(int ch, int offset)
-{
-	return offset + LM4_LPC_CH0_BASE + LM4_LPC_CH_SEP * ch;
-}
-#define LM4LPCREG(ch, offset)  REG32(lm4_lpc_addr(ch, offset))
-#define LM4_LPC_CTL(ch)        LM4LPCREG(ch, 0x000)
-#define LM4_LPC_ST(ch)         LM4LPCREG(ch, 0x004)
-#define LM4_LPC_ST_TOH         BIT(0)  /* TO Host bit */
-#define LM4_LPC_ST_FRMH        BIT(1)  /* FRoM Host bit */
-#define LM4_LPC_ST_CMD         BIT(3)  /* Last from-host byte was command */
-#define LM4_LPC_ST_BURST       BIT(8)
-#define LM4_LPC_ST_SCI         BIT(9)
-#define LM4_LPC_ST_SMI         BIT(10)
-#define LM4_LPC_ST_BUSY        BIT(12)
-#define LM4_LPC_ADR(ch)        LM4LPCREG(ch, 0x008)
-#define LM4_LPC_POOL_BYTES     1024   /* Size of LPCPOOL in bytes */
-#define LM4_LPC_LPCPOOL        ((volatile unsigned char *)0x40080400)
-
-#define LM4_FAN_FANSTS         REG32(0x40084000)
-#define LM4_FAN_FANCTL         REG32(0x40084004)
-#define LM4_FAN_CH0_BASE       0x40084010
-#define LM4_FAN_CH1_BASE       0x40084020
-#define LM4_FAN_CH2_BASE       0x40084030
-#define LM4_FAN_CH3_BASE       0x40084040
-#define LM4_FAN_CH4_BASE       0x40084050
-#define LM4_FAN_CH5_BASE       0x40084060
-#define LM4_FAN_CH_SEP         0x00000010
-static inline int lm4_fan_addr(int ch, int offset)
-{
-	return offset + LM4_FAN_CH0_BASE + LM4_FAN_CH_SEP * ch;
-}
-#define LM4FANREG(ch, offset)  REG32(lm4_fan_addr(ch, offset))
-#define LM4_FAN_FANCH(ch)      LM4FANREG(ch, 0x000)
-#define LM4_FAN_FANCMD(ch)     LM4FANREG(ch, 0x004)
-#define LM4_FAN_FANCST(ch)     LM4FANREG(ch, 0x008)
-
-#define LM4_EEPROM_EESIZE      REG32(0x400af000)
-#define LM4_EEPROM_EEBLOCK     REG32(0x400af004)
-#define LM4_EEPROM_EEOFFSET    REG32(0x400af008)
-#define LM4_EEPROM_EERDWR      REG32(0x400af010)
-#define LM4_EEPROM_EERDWRINC   REG32(0x400af014)
-#define LM4_EEPROM_EEDONE      REG32(0x400af018)
-#define LM4_EEPROM_EESUPP      REG32(0x400af01c)
-#define LM4_EEPROM_EEUNLOCK    REG32(0x400af020)
-#define LM4_EEPROM_EEPROT      REG32(0x400af030)
-#define LM4_EEPROM_EEPASS0     REG32(0x400af034)
-#define LM4_EEPROM_EEPASS1     REG32(0x400af038)
-#define LM4_EEPROM_EEPASS2     REG32(0x400af03c)
-#define LM4_EEPROM_EEINT       REG32(0x400af040)
-#define LM4_EEPROM_EEHIDE      REG32(0x400af050)
-
-#define LM4_PECI_CTL           REG32(0x400b0000)
-#define LM4_PECI_DIV           REG32(0x400b0004)
-#define LM4_PECI_CMP           REG32(0x400b0008)
-#define LM4_PECI_M0D0C         REG32(0x400b0010)
-#define LM4_PECI_M0D1C         REG32(0x400b0014)
-#define LM4_PECI_M1D0C         REG32(0x400b0018)
-#define LM4_PECI_M1D1C         REG32(0x400b001c)
-#define LM4_PECI_M0D0          REG32(0x400b0040)
-#define LM4_PECI_M0D1          REG32(0x400b0044)
-#define LM4_PECI_M1D0          REG32(0x400b0048)
-#define LM4_PECI_M1D1          REG32(0x400b004c)
-#define LM4_PECI_IM            REG32(0x400b0080)
-#define LM4_PECI_RIS           REG32(0x400b0084)
-#define LM4_PECI_MIS           REG32(0x400b0088)
-#define LM4_PECI_IC            REG32(0x400b008c)
-#define LM4_PECI_ACADDR        REG32(0x400b0100)
-#define LM4_PECI_ACARG         REG32(0x400b0104)
-#define LM4_PECI_ACRDWR0       REG32(0x400b0108)
-#define LM4_PECI_ACRDWR1       REG32(0x400b010c)
-#define LM4_PECI_ACCMD         REG32(0x400b0110)
-#define LM4_PECI_ACCODE        REG32(0x400b0114)
-
-
-#define LM4_HIBERNATE_HIBRTCC  REG32(0x400fc000)
-#define LM4_HIBERNATE_HIBRTCM0 REG32(0x400fc004)
-#define LM4_HIBERNATE_HIBRTCLD REG32(0x400fc00c)
-#define LM4_HIBERNATE_HIBCTL   REG32(0x400fc010)
-#define LM4_HIBCTL_WRC         BIT(31)
-#define LM4_HIBCTL_CLK32EN     BIT(6)
-#define LM4_HIBCTL_PINWEN      BIT(4)
-#define LM4_HIBCTL_RTCWEN      BIT(3)
-#define LM4_HIBCTL_HIBREQ      BIT(1)
-#define LM4_HIBCTL_RTCEN       BIT(0)
-#define LM4_HIBERNATE_HIBIM    REG32(0x400fc014)
-#define LM4_HIBERNATE_HIBRIS   REG32(0x400fc018)
-#define LM4_HIBERNATE_HIBMIS   REG32(0x400fc01c)
-#define LM4_HIBERNATE_HIBIC    REG32(0x400fc020)
-#define LM4_HIBERNATE_HIBRTCT  REG32(0x400fc024)
-#define LM4_HIBERNATE_HIBRTCSS REG32(0x400fc028)
-#define LM4_HIBERNATE_HIBDATA_ENTRIES 16  /* Number of entries in HIBDATA[] */
-#define LM4_HIBERNATE_HIBDATA  ((volatile uint32_t *)0x400fc030)
-
-#define LM4_FLASH_FMA          REG32(0x400fd000)
-#define LM4_FLASH_FMD          REG32(0x400fd004)
-#define LM4_FLASH_FMC          REG32(0x400fd008)
-#define LM4_FLASH_FCRIS        REG32(0x400fd00c)
-#define LM4_FLASH_FCMISC       REG32(0x400fd014)
-#define LM4_FLASH_FMC2         REG32(0x400fd020)
-#define LM4_FLASH_FWBVAL       REG32(0x400fd030)
-/* FWB size is 32 words = 128 bytes */
-#define LM4_FLASH_FWB          ((volatile uint32_t*)0x400fd100)
-#define LM4_FLASH_FSIZE        REG32(0x400fdfc0)
-#define LM4_FLASH_FMPRE0       REG32(0x400fe200)
-#define LM4_FLASH_FMPRE1       REG32(0x400fe204)
-#define LM4_FLASH_FMPRE2       REG32(0x400fe208)
-#define LM4_FLASH_FMPRE3       REG32(0x400fe20c)
-#define LM4_FLASH_FMPPE        ((volatile uint32_t*)0x400fe400)
-#define LM4_FLASH_FMPPE0       REG32(0x400fe400)
-#define LM4_FLASH_FMPPE1       REG32(0x400fe404)
-#define LM4_FLASH_FMPPE2       REG32(0x400fe408)
-#define LM4_FLASH_FMPPE3       REG32(0x400fe40c)
-
-#define LM4_SYSTEM_DID0        REG32(0x400fe000)
-#define LM4_SYSTEM_DID1        REG32(0x400fe004)
-#define LM4_SYSTEM_PBORCTL     REG32(0x400fe030)
-#define LM4_SYSTEM_RIS         REG32(0x400fe050)
-#define LM4_SYSTEM_MISC        REG32(0x400fe058)
-#define LM4_SYSTEM_RESC        REG32(0x400fe05c)
-#define LM4_SYSTEM_RCC         REG32(0x400fe060)
-#define LM4_SYSTEM_RCC_ACG        BIT(27)
-#define LM4_SYSTEM_RCC_SYSDIV(x)  (((x) & 0xf) << 23)
-#define LM4_SYSTEM_RCC_USESYSDIV  BIT(22)
-#define LM4_SYSTEM_RCC_PWRDN      BIT(13)
-#define LM4_SYSTEM_RCC_BYPASS     BIT(11)
-#define LM4_SYSTEM_RCC_XTAL(x)    (((x) & 0x1f) << 6)
-#define LM4_SYSTEM_RCC_OSCSRC(x)  (((x) & 0x3) << 4)
-#define LM4_SYSTEM_RCC_IOSCDIS    BIT(1)
-#define LM4_SYSTEM_RCC_MOSCDIS    BIT(0)
-#define LM4_SYSTEM_RCC2        REG32(0x400fe070)
-#define LM4_SYSTEM_RCC2_USERCC2     BIT(31)
-#define LM4_SYSTEM_RCC2_DIV400      BIT(30)
-#define LM4_SYSTEM_RCC2_SYSDIV2(x)  (((x) & 0x3f) << 23)
-#define LM4_SYSTEM_RCC2_SYSDIV2LSB  BIT(22)
-#define LM4_SYSTEM_RCC2_PWRDN2      BIT(13)
-#define LM4_SYSTEM_RCC2_BYPASS2     BIT(11)
-#define LM4_SYSTEM_RCC2_OSCSRC2(x)  (((x) & 0x7) << 4)
-#define LM4_SYSTEM_MOSCCTL     REG32(0x400fe07c)
-#define LM4_SYSTEM_DSLPCLKCFG  REG32(0x400fe144)
-#define LM4_SYSTEM_PIOSCCAL    REG32(0x400fe150)
-#define LM4_SYSTEM_PIOSCSTAT   REG32(0x400fe154)
-#define LM4_SYSTEM_PLLSTAT     REG32(0x400fe168)
-#define LM4_SYSTEM_SLPPWRCFG   REG32(0x400fe188)
-#define LM4_SYSTEM_DSLPPWRCFG  REG32(0x400fe18c)
-#define LM4_SYSTEM_LDOSPCTL    REG32(0x400fe1b4)
-#define LM4_SYSTEM_LDOSPCAL    REG32(0x400fe1b8)
-#define LM4_SYSTEM_LDODPCTL    REG32(0x400fe1bc)
-#define LM4_SYSTEM_LDODPCAL    REG32(0x400fe1c0)
-#define LM4_SYSTEM_SPDMST      REG32(0x400fe1cc)
-#define LM4_SYSTEM_BOOTCFG     REG32(0x400fe1d0)
-#define LM4_SYSTEM_BOOTCFG_MASK 0x7fff00ec /* Reserved bits of BOOTCFG reg */
-/* Note: USER_REG3 is used to hold pre-programming process data and should not
- * be modified by EC code.  See crosbug.com/p/8889. */
-#define LM4_SYSTEM_USER_REG3   REG32(0x400fe1ec)
-#define LM4_SYSTEM_SRI2C       REG32(0x400fe520)
-#define LM4_SYSTEM_SREEPROM    REG32(0x400fe558)
-
-#define LM4_SYSTEM_SRI2C_ADDR  ((uint32_t *)0x400fe520)
-
-#define LM4_SYSTEM_RCGC_BASE   ((volatile uint32_t *)0x400fe600)
-#define LM4_SYSTEM_RCGCGPIO    REG32(0x400fe608)
-#define LM4_SYSTEM_SCGC_BASE   ((volatile uint32_t *)0x400fe700)
-#define LM4_SYSTEM_DCGC_BASE   ((volatile uint32_t *)0x400fe800)
-
-/*
- * Offsets from CGC_BASE registers for each peripheral.
- * Note: these are in units of 32-bit words offset from
- * the base address.
- */
-enum clock_gate_offsets {
-	CGC_OFFSET_WD =        0,
-	CGC_OFFSET_TIMER =     1,
-	CGC_OFFSET_GPIO =      2,
-	CGC_OFFSET_DMA =       3,
-	CGC_OFFSET_HIB =       5,
-	CGC_OFFSET_UART =      6,
-	CGC_OFFSET_SSI =       7,
-	CGC_OFFSET_I2C =       8,
-	CGC_OFFSET_ADC =       14,
-	CGC_OFFSET_LPC =       18,
-	CGC_OFFSET_PECI =      20,
-	CGC_OFFSET_FAN =       21,
-	CGC_OFFSET_EEPROM =    22,
-	CGC_OFFSET_WTIMER =    23,
-};
-
-#define LM4_SYSTEM_PREEPROM    REG32(0x400fea58)
-
-#define LM4_DMA_DMACFG         REG32(0x400ff004)
-#define LM4_DMA_DMACTLBASE     REG32(0x400ff008)
-#define LM4_DMA_DMACHMAP0      REG32(0x400ff510)
-#define LM4_DMA_DMACHMAP1      REG32(0x400ff514)
-#define LM4_DMA_DMACHMAP2      REG32(0x400ff518)
-#define LM4_DMA_DMACHMAP3      REG32(0x400ff51c)
-
-/* IRQ numbers */
-#define LM4_IRQ_GPIOA            0
-#define LM4_IRQ_GPIOB            1
-#define LM4_IRQ_GPIOC            2
-#define LM4_IRQ_GPIOD            3
-#define LM4_IRQ_GPIOE            4
-#define LM4_IRQ_UART0            5
-#define LM4_IRQ_UART1            6
-#define LM4_IRQ_SSI0             7
-#define LM4_IRQ_I2C0             8
-/* 9 - 13 reserved */
-#define LM4_IRQ_ADC0_SS0        14
-#define LM4_IRQ_ADC0_SS1        15
-#define LM4_IRQ_ADC0_SS2        16
-#define LM4_IRQ_ADC0_SS3        17
-#define LM4_IRQ_WATCHDOG        18
-#define LM4_IRQ_TIMER0A         19
-#define LM4_IRQ_TIMER0B         20
-#define LM4_IRQ_TIMER1A         21
-#define LM4_IRQ_TIMER1B         22
-#define LM4_IRQ_TIMER2A         23
-#define LM4_IRQ_TIMER2B         24
-#define LM4_IRQ_ACMP0           25
-#define LM4_IRQ_ACMP1           26
-#define LM4_IRQ_ACMP2           27
-#define LM4_IRQ_SYSCTRL         28
-#define LM4_IRQ_EEPROM          29
-#define LM4_IRQ_GPIOF           30
-#define LM4_IRQ_GPIOG           31
-#define LM4_IRQ_GPIOH           32
-#define LM4_IRQ_UART2           33
-#define LM4_IRQ_SSI1            34
-#define LM4_IRQ_TIMER3A         35
-#define LM4_IRQ_TIMER3B         36
-#define LM4_IRQ_I2C1            37
-/* 38 - 42 reserved */
-#define LM4_IRQ_HIBERNATE       43
-/* 44 - 45 reserved */
-#define LM4_IRQ_UDMA_SOFTWARE   46
-#define LM4_IRQ_UDMA_ERROR      47
-#define LM4_IRQ_ADC1_SS0        48
-#define LM4_IRQ_ADC1_SS1        49
-#define LM4_IRQ_ADC1_SS2        50
-#define LM4_IRQ_ADC1_SS3        51
-/* 52 - 53 reserved */
-#define LM4_IRQ_GPIOJ           54
-#define LM4_IRQ_GPIOK           55
-#define LM4_IRQ_GPIOL           56
-#define LM4_IRQ_SSI2            57
-#define LM4_IRQ_SSI3            58
-#define LM4_IRQ_UART3           59
-#define LM4_IRQ_UART4           60
-#define LM4_IRQ_UART5           61
-#define LM4_IRQ_UART6           62
-#define LM4_IRQ_UART7           63
-/* 64 - 67 reserved */
-#define LM4_IRQ_I2C2            68
-#define LM4_IRQ_I2C3            69
-#define LM4_IRQ_TIMER4A         70
-#define LM4_IRQ_TIMER4B         71
-/* 72 - 91 reserved */
-#define LM4_IRQ_TIMER5A         92
-#define LM4_IRQ_TIMER5B         93
-#define LM4_IRQ_TIMERW0A        94
-#define LM4_IRQ_TIMERW0B        95
-#define LM4_IRQ_TIMERW1A        96
-#define LM4_IRQ_TIMERW1B        97
-#define LM4_IRQ_TIMERW2A        98
-#define LM4_IRQ_TIMERW2B        99
-#define LM4_IRQ_TIMERW3A       100
-#define LM4_IRQ_TIMERW3B       101
-#define LM4_IRQ_TIMERW4A       102
-#define LM4_IRQ_TIMERW4B       103
-#define LM4_IRQ_TIMERW5A       104
-#define LM4_IRQ_TIMERW5B       105
-#define LM4_IRQ_SYS_EXCEPTION  106
-#define LM4_IRQ_SYS_PECI       107
-#define LM4_IRQ_LPC            108
-#define LM4_IRQ_I2C4           109
-#define LM4_IRQ_I2C5           110
-#define LM4_IRQ_GPIOM          111
-#define LM4_IRQ_GPION          112
-/* 113 reserved */
-#define LM4_IRQ_FAN            114
-/* 115 reserved */
-#define LM4_IRQ_GPIOP          116
-#define LM4_IRQ_GPIOP1         117
-#define LM4_IRQ_GPIOP2         118
-#define LM4_IRQ_GPIOP3         119
-#define LM4_IRQ_GPIOP4         120
-#define LM4_IRQ_GPIOP5         121
-#define LM4_IRQ_GPIOP6         122
-#define LM4_IRQ_GPIOP7         123
-#define LM4_IRQ_GPIOQ          124
-#define LM4_IRQ_GPIOQ1         125
-#define LM4_IRQ_GPIOQ2         126
-#define LM4_IRQ_GPIOQ3         127
-#define LM4_IRQ_GPIOQ4         128
-#define LM4_IRQ_GPIOQ5         129
-#define LM4_IRQ_GPIOQ6         130
-#define LM4_IRQ_GPIOQ7         131
-/* 132 - 138 reserved */
-
-/* GPIO */
-#define LM4_GPIO_PORTA_BASE         0x40004000
-#define LM4_GPIO_PORTB_BASE         0x40005000
-#define LM4_GPIO_PORTC_BASE         0x40006000
-#define LM4_GPIO_PORTD_BASE         0x40007000
-#define LM4_GPIO_PORTE_BASE         0x40024000
-#define LM4_GPIO_PORTF_BASE         0x40025000
-#define LM4_GPIO_PORTG_BASE         0x40026000
-#define LM4_GPIO_PORTH_BASE         0x40027000
-#define LM4_GPIO_PORTJ_BASE         0x4003d000
-#define LM4_GPIO_PORTK_BASE         0x40061000
-#define LM4_GPIO_PORTL_BASE         0x40062000
-#define LM4_GPIO_PORTM_BASE         0x40063000
-#define LM4_GPIO_PORTN_BASE         0x40064000
-#define LM4_GPIO_PORTP_BASE         0x40065000
-#define LM4_GPIO_PORTQ_BASE         0x40066000
-#define LM4_GPIO_PORTA_AHB_BASE     0x40058000
-#define LM4_GPIO_PORTB_AHB_BASE     0x40059000
-#define LM4_GPIO_PORTC_AHB_BASE     0x4005a000
-#define LM4_GPIO_PORTD_AHB_BASE     0x4005b000
-#define LM4_GPIO_PORTE_AHB_BASE     0x4005c000
-#define LM4_GPIO_PORTF_AHB_BASE     0x4005d000
-#define LM4_GPIO_PORTG_AHB_BASE     0x4005e000
-#define LM4_GPIO_PORTH_AHB_BASE     0x4005f000
-#define LM4_GPIO_PORTJ_AHB_BASE     0x40060000
-/* Ports for passing to LM4GPIOREG(); abstracted from base addresses above so
- * that we can switch to/from AHB. */
-#define LM4_GPIO_A LM4_GPIO_PORTA_BASE
-#define LM4_GPIO_B LM4_GPIO_PORTB_BASE
-#define LM4_GPIO_C LM4_GPIO_PORTC_BASE
-#define LM4_GPIO_D LM4_GPIO_PORTD_BASE
-#define LM4_GPIO_E LM4_GPIO_PORTE_BASE
-#define LM4_GPIO_F LM4_GPIO_PORTF_BASE
-#define LM4_GPIO_G LM4_GPIO_PORTG_BASE
-#define LM4_GPIO_H LM4_GPIO_PORTH_BASE
-#define LM4_GPIO_J LM4_GPIO_PORTJ_BASE
-#define LM4_GPIO_K LM4_GPIO_PORTK_BASE
-#define LM4_GPIO_L LM4_GPIO_PORTL_BASE
-#define LM4_GPIO_M LM4_GPIO_PORTM_BASE
-#define LM4_GPIO_N LM4_GPIO_PORTN_BASE
-#define LM4_GPIO_P LM4_GPIO_PORTP_BASE
-#define LM4_GPIO_Q LM4_GPIO_PORTQ_BASE
-#define LM4GPIOREG(port, offset)      REG32((port) + (offset))
-#define LM4_GPIO_DATA(port, mask)     LM4GPIOREG(port, ((mask) << 2))
-#define LM4_GPIO_DIR(port)            LM4GPIOREG(port, 0x400)
-#define LM4_GPIO_IS(port)             LM4GPIOREG(port, 0x404)
-#define LM4_GPIO_IBE(port)            LM4GPIOREG(port, 0x408)
-#define LM4_GPIO_IEV(port)            LM4GPIOREG(port, 0x40c)
-#define LM4_GPIO_IM(port)             LM4GPIOREG(port, 0x410)
-#define LM4_GPIO_RIS(port)            LM4GPIOREG(port, 0x414)
-#define LM4_GPIO_MIS(port)            LM4GPIOREG(port, 0x418)
-#define LM4_GPIO_ICR(port)            LM4GPIOREG(port, 0x41c)
-#define LM4_GPIO_AFSEL(port)          LM4GPIOREG(port, 0x420)
-#define LM4_GPIO_DR2R(port)           LM4GPIOREG(port, 0x500)
-#define LM4_GPIO_DR4R(port)           LM4GPIOREG(port, 0x504)
-#define LM4_GPIO_DR8R(port)           LM4GPIOREG(port, 0x508)
-#define LM4_GPIO_ODR(port)            LM4GPIOREG(port, 0x50c)
-#define LM4_GPIO_PUR(port)            LM4GPIOREG(port, 0x510)
-#define LM4_GPIO_PDR(port)            LM4GPIOREG(port, 0x514)
-#define LM4_GPIO_SLR(port)            LM4GPIOREG(port, 0x518)
-#define LM4_GPIO_DEN(port)            LM4GPIOREG(port, 0x51c)
-#define LM4_GPIO_LOCK(port)           LM4GPIOREG(port, 0x520)
-#define LM4_GPIO_CR(port)             LM4GPIOREG(port, 0x524)
-#define LM4_GPIO_AMSEL(port)          LM4GPIOREG(port, 0x528)
-#define LM4_GPIO_PCTL(port)           LM4GPIOREG(port, 0x52c)
-
-/* Chip-independent aliases for port base addresses */
-#define GPIO_A LM4_GPIO_A
-#define GPIO_B LM4_GPIO_B
-#define GPIO_C LM4_GPIO_C
-#define GPIO_D LM4_GPIO_D
-#define GPIO_E LM4_GPIO_E
-#define GPIO_F LM4_GPIO_F
-#define GPIO_G LM4_GPIO_G
-#define GPIO_H LM4_GPIO_H
-#define GPIO_J LM4_GPIO_J
-#define GPIO_K LM4_GPIO_K
-#define GPIO_L LM4_GPIO_L
-#define GPIO_M LM4_GPIO_M
-#define GPIO_N LM4_GPIO_N
-#define GPIO_P LM4_GPIO_P
-#define GPIO_Q LM4_GPIO_Q
-
-#define UNIMPLEMENTED_GPIO_BANK GPIO_A
-
-/* Value to write to LM4_GPIO_LOCK to unlock writes */
-#define LM4_GPIO_LOCK_UNLOCK          0x4c4f434b
-
-/* I2C */
-#define LM4_I2C0_BASE                 0x40020000
-#define LM4_I2C1_BASE                 0x40021000
-#define LM4_I2C2_BASE                 0x40022000
-#define LM4_I2C3_BASE                 0x40023000
-#define LM4_I2C4_BASE                 0x400c0000
-#define LM4_I2C5_BASE                 0x400c1000
-#define LM4_I2C_BASESEP               0x00001000
-/* I2C base address by port.  Compiles to a constant in gcc if port
-   and offset are constant. */
-static inline int lm4_i2c_addr(int port, int offset)
-{
-	return offset + (port < 4 ?
-			 LM4_I2C0_BASE + LM4_I2C_BASESEP * port :
-			 LM4_I2C4_BASE + LM4_I2C_BASESEP * (port - 4));
-}
-#define LM4I2CREG(port, offset)       REG32(lm4_i2c_addr(port, offset))
-#define LM4_I2C_MSA(port)             LM4I2CREG(port, 0x000)
-#define LM4_I2C_MCS(port)             LM4I2CREG(port, 0x004)
-#define LM4_I2C_MDR(port)             LM4I2CREG(port, 0x008)
-#define LM4_I2C_MTPR(port)            LM4I2CREG(port, 0x00c)
-#define LM4_I2C_MIMR(port)            LM4I2CREG(port, 0x010)
-#define LM4_I2C_MRIS(port)            LM4I2CREG(port, 0x014)
-#define LM4_I2C_MMIS(port)            LM4I2CREG(port, 0x018)
-#define LM4_I2C_MICR(port)            LM4I2CREG(port, 0x01c)
-#define LM4_I2C_MCR(port)             LM4I2CREG(port, 0x020)
-#define LM4_I2C_MCLKOCNT(port)        LM4I2CREG(port, 0x024)
-#define LM4_I2C_MBMON(port)           LM4I2CREG(port, 0x02c)
-
-
-/* Timers */
-/* Timers 0-5 are 16/32 bit */
-#define LM4_TIMER0_BASE                 0x40030000
-#define LM4_TIMER1_BASE                 0x40031000
-#define LM4_TIMER2_BASE                 0x40032000
-#define LM4_TIMER3_BASE                 0x40033000
-#define LM4_TIMER4_BASE                 0x40034000
-#define LM4_TIMER5_BASE                 0x40035000
-/* Timers 6-11 are 32/64 bit */
-#define LM4_TIMERW0_BASE                0x40036000
-#define LM4_TIMERW1_BASE                0x40037000
-#define LM4_TIMERW2_BASE                0x4004c000
-#define LM4_TIMERW3_BASE                0x4004d000
-#define LM4_TIMERW4_BASE                0x4004e000
-#define LM4_TIMERW5_BASE                0x4004f000
-#define LM4_TIMER_SEP                   0x00001000
-static inline int lm4_timer_addr(int timer, int offset)
-{
-	if (timer < 8)
-		return offset + LM4_TIMER0_BASE + LM4_TIMER_SEP * timer;
-	else
-		return offset + LM4_TIMERW2_BASE + LM4_TIMER_SEP * (timer - 8);
-}
-#define LM4TIMERREG(timer, offset)      REG32(lm4_timer_addr(timer, offset))
-#define LM4_TIMER_CFG(tmr)              LM4TIMERREG(tmr, 0x00)
-#define LM4_TIMER_TAMR(tmr)             LM4TIMERREG(tmr, 0x04)
-#define LM4_TIMER_TBMR(tmr)             LM4TIMERREG(tmr, 0x08)
-#define LM4_TIMER_CTL(tmr)              LM4TIMERREG(tmr, 0x0c)
-#define LM4_TIMER_SYNC(tmr)             LM4TIMERREG(tmr, 0x10)
-#define LM4_TIMER_IMR(tmr)              LM4TIMERREG(tmr, 0x18)
-#define LM4_TIMER_RIS(tmr)              LM4TIMERREG(tmr, 0x1c)
-#define LM4_TIMER_MIS(tmr)              LM4TIMERREG(tmr, 0x20)
-#define LM4_TIMER_ICR(tmr)              LM4TIMERREG(tmr, 0x24)
-#define LM4_TIMER_TAILR(tmr)            LM4TIMERREG(tmr, 0x28)
-#define LM4_TIMER_TBILR(tmr)            LM4TIMERREG(tmr, 0x2c)
-#define LM4_TIMER_TAMATCHR(tmr)         LM4TIMERREG(tmr, 0x30)
-#define LM4_TIMER_TBMATCHR(tmr)         LM4TIMERREG(tmr, 0x34)
-#define LM4_TIMER_TAPR(tmr)             LM4TIMERREG(tmr, 0x38)
-#define LM4_TIMER_TBPR(tmr)             LM4TIMERREG(tmr, 0x3c)
-#define LM4_TIMER_TAPMR(tmr)            LM4TIMERREG(tmr, 0x40)
-#define LM4_TIMER_TBPMR(tmr)            LM4TIMERREG(tmr, 0x44)
-#define LM4_TIMER_TAR(tmr)              LM4TIMERREG(tmr, 0x48)
-#define LM4_TIMER_TBR(tmr)              LM4TIMERREG(tmr, 0x4c)
-#define LM4_TIMER_TAV(tmr)              LM4TIMERREG(tmr, 0x50)
-#define LM4_TIMER_TBV(tmr)              LM4TIMERREG(tmr, 0x54)
-#define LM4_TIMER_RTCPD(tmr)            LM4TIMERREG(tmr, 0x58)
-#define LM4_TIMER_TAPS(tmr)             LM4TIMERREG(tmr, 0x5c)
-#define LM4_TIMER_TBPS(tmr)             LM4TIMERREG(tmr, 0x60)
-#define LM4_TIMER_TAPV(tmr)             LM4TIMERREG(tmr, 0x64)
-#define LM4_TIMER_TBPV(tmr)             LM4TIMERREG(tmr, 0x68)
-
-#define LM4_SYSTICK_CTRL                REG32(0xe000e010)
-#define LM4_SYSTICK_RELOAD              REG32(0xe000e014)
-#define LM4_SYSTICK_CURRENT             REG32(0xe000e018)
-
-/* Watchdogs */
-#define LM4_WATCHDOG0_BASE              0x40000000
-#define LM4_WATCHDOG1_BASE              0x40001000
-static inline int lm4_watchdog_addr(int num, int offset)
-{
-	return offset + (num ? LM4_WATCHDOG1_BASE : LM4_WATCHDOG0_BASE);
-}
-#define LM4WDTREG(num, offset)		REG32(lm4_watchdog_addr(num, offset))
-#define LM4_WATCHDOG_LOAD(n)            LM4WDTREG(n, 0x000)
-#define LM4_WATCHDOG_VALUE(n)           LM4WDTREG(n, 0x004)
-#define LM4_WATCHDOG_CTL(n)             LM4WDTREG(n, 0x008)
-#define LM4_WATCHDOG_ICR(n)             LM4WDTREG(n, 0x00c)
-#define LM4_WATCHDOG_RIS(n)             LM4WDTREG(n, 0x010)
-#define LM4_WATCHDOG_TEST(n)            LM4WDTREG(n, 0x418)
-#define LM4_WATCHDOG_LOCK(n)            LM4WDTREG(n, 0xc00)
-
-#define LM4_TEST_MODE_ENABLED		REG32(0x400fdff0)
-
-#endif /* __CROS_EC_REGISTERS_H */
diff --git a/chip/lm4/spi.c b/chip/lm4/spi.c
deleted file mode 100644
index be988b78a0..0000000000
--- a/chip/lm4/spi.c
+++ /dev/null
@@ -1,190 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* SPI module for Chrome EC */
-
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "spi.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_SPI, outstr)
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
-
-
-int spi_enable(int port, int enable)
-{
-	int i;
-
-	if (enable) {
-		gpio_config_module(MODULE_SPI, 1);
-		for (i = 0; i < spi_devices_used; i++) {
-			if (spi_devices[i].port != port)
-				continue;
-			/*
-			 * Don't use the SSI0 frame output.
-			 * CS# is a GPIO so we can keep it low during an entire
-			 * transaction.
-			*/
-			gpio_set_flags(spi_device[i]->gpio_cs, GPIO_OUTPUT);
-			gpio_set_level(spi_device[i]->gpio_cs, 1);
-		}
-
-		/* Enable SSI port */
-		LM4_SSI_CR1(0) |= 0x02;
-	} else {
-		/* Disable SSI port */
-		LM4_SSI_CR1(0) &= ~0x02;
-
-		for (i = 0; i < spi_devices_used; i++) {
-			if (spi_devices[i].port != port)
-				continue;
-			/* Make sure CS# is deselected */
-			gpio_set_level(spi_device[i]->gpio_cs, 1);
-			gpio_set_flags(spi_device->gpio_cs[i], GPIO_ODR_HIGH);
-		}
-
-		gpio_config_module(MODULE_SPI, 0);
-	}
-
-	return EC_SUCCESS;
-}
-
-
-int spi_transaction(const struct spi_device_t *spi_device,
-		    const uint8_t *txdata, int txlen,
-		    uint8_t *rxdata, int rxlen)
-{
-	int totallen = txlen + rxlen;
-	int txcount = 0, rxcount = 0;
-	static struct mutex spi_mutex;
-	volatile uint32_t unused  __attribute__((unused));
-
-	mutex_lock(&spi_mutex);
-	/* Empty the receive FIFO */
-	while (LM4_SSI_SR(0) & LM4_SSI_SR_RNE)
-		unused = LM4_SSI_DR(0);
-
-	/* Start transaction.  Need to do this explicitly because the LM4
-	 * SSI controller pulses its frame select every byte, and the EEPROM
-	 * wants the chip select held low during the entire transaction. */
-	gpio_set_level(spi_device->gpio_cs, 0);
-
-	while (rxcount < totallen) {
-		/* Handle received bytes if any.  We just checked rxcount <
-		 * totallen, so we don't need to worry about overflowing the
-		 * receive buffer. */
-		if (LM4_SSI_SR(0) & LM4_SSI_SR_RNE) {
-			if (rxcount < txlen) {
-				/* Throw away bytes received while we were
-				   transmitting */
-				unused = LM4_SSI_DR(0);
-			} else
-				*(rxdata++) = LM4_SSI_DR(0);
-			rxcount++;
-		}
-
-		/* Transmit another byte if needed */
-		if ((LM4_SSI_SR(0) & LM4_SSI_SR_TNF) && txcount < totallen) {
-			if (txcount < txlen)
-				LM4_SSI_DR(0) = *(txdata++);
-			else {
-				/* Clock out unused byte so we can clock in the
-				 * response byte */
-				LM4_SSI_DR(0) = 0;
-			}
-			txcount++;
-		}
-	}
-
-	/* End transaction */
-	gpio_set_level(spi_device->gpio_cs, 1);
-	mutex_unlock(&spi_mutex);
-
-	return EC_SUCCESS;
-}
-
-/*****************************************************************************/
-/* Hooks */
-
-static int spi_init(void)
-{
-	/* Enable the SPI module in run and sleep modes */
-	clock_enable_peripheral(CGC_OFFSET_SSI, 0x1,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-
-	LM4_SSI_CR1(0) = 0;       /* Disable SSI */
-	LM4_SSI_CR0(0) = 0x0007;  /* SCR=0, SPH=0, SPO=0, FRF=SPI, 8-bit */
-
-	/* Use PIOSC for clock.  This limits us to 8MHz (PIOSC/2), but is
-	 * simpler to configure and we don't need to worry about clock
-	 * frequency changing when the PLL is disabled.  If we really start
-	 * using this, might be worth using the system clock and handling
-	 * frequency change (like we do with PECI) so we can go faster. */
-	LM4_SSI_CC(0) = 1;
-	/* SSICLK = PIOSC / (CPSDVSR * (1 + SCR)
-	 *        = 16 MHz / (2 * (1 + 0))
-	 *        = 8 MHz */
-	LM4_SSI_CPSR(0) = 2;
-
-	/* Ensure the SPI port is disabled.  This keeps us from interfering
-	 * with the main chipset when we're not explicitly using the SPI
-	 * bus. */
-	spi_enable(CONFIG_SPI_FLASH_PORT, 0);
-
-	return EC_SUCCESS;
-}
-DECLARE_HOOK(HOOK_INIT, spi_init, HOOK_PRIO_INIT_SPI);
-
-/*****************************************************************************/
-/* Console commands */
-
-static int printrx(const char *desc, const uint8_t *txdata, int txlen,
-		   int rxlen)
-{
-	uint8_t rxdata[32];
-	int rv;
-	int i;
-
-	rv = spi_transaction(SPI_FLASH_DEVICE, txdata, txlen, rxdata, rxlen);
-	if (rv)
-		return rv;
-
-	ccprintf("%-12s:", desc);
-	for (i = 0; i < rxlen; i++)
-		ccprintf(" 0x%02x", rxdata[i]);
-	ccputs("\n");
-	return EC_SUCCESS;
-}
-
-
-static int command_spirom(int argc, char **argv)
-{
-	uint8_t txmandev[] = {0x90, 0x00, 0x00, 0x00};
-	uint8_t txjedec[] = {0x9f};
-	uint8_t txunique[] = {0x4b, 0x00, 0x00, 0x00, 0x00};
-	uint8_t txsr1[] = {0x05};
-	uint8_t txsr2[] = {0x35};
-
-	spi_enable(CONFIG_SPI_FLASH_PORT, 1);
-
-	printrx("Man/Dev ID", txmandev, sizeof(txmandev), 2);
-	printrx("JEDEC ID", txjedec, sizeof(txjedec), 3);
-	printrx("Unique ID", txunique, sizeof(txunique), 8);
-	printrx("Status reg 1", txsr1, sizeof(txsr1), 1);
-	printrx("Status reg 2", txsr2, sizeof(txsr2), 1);
-
-	spi_enable(CONFIG_SPI_FLASH_PORT, 0);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(spirom, command_spirom,
-			NULL,
-			"Test reading SPI EEPROM");
diff --git a/chip/lm4/system.c b/chip/lm4/system.c
deleted file mode 100644
index 75e7d556ec..0000000000
--- a/chip/lm4/system.c
+++ /dev/null
@@ -1,767 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* System module for Chrome EC : LM4 hardware specific implementation */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "host_command.h"
-#include "panic.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Indices for hibernate data registers */
-enum hibdata_index {
-	HIBDATA_INDEX_SCRATCHPAD,           /* General-purpose scratchpad */
-	HIBDATA_INDEX_WAKE,                 /* Wake reasons for hibernate */
-	HIBDATA_INDEX_SAVED_RESET_FLAGS,    /* Saved reset flags */
-#ifdef CONFIG_SOFTWARE_PANIC
-	HIBDATA_INDEX_SAVED_PANIC_REASON,   /* Saved panic reason */
-	HIBDATA_INDEX_SAVED_PANIC_INFO,     /* Saved panic data */
-	HIBDATA_INDEX_SAVED_PANIC_EXCEPTION /* Saved panic exception code */
-#endif
-};
-
-/* Flags for HIBDATA_INDEX_WAKE */
-#define HIBDATA_WAKE_RTC        BIT(0)  /* RTC alarm */
-#define HIBDATA_WAKE_HARD_RESET BIT(1)  /* Hard reset via short RTC alarm */
-#define HIBDATA_WAKE_PIN        BIT(2)  /* Wake pin */
-
-/*
- * Time to hibernate to trigger a power-on reset.  50 ms is sufficient for the
- * EC itself, but we need a longer delay to ensure the rest of the components
- * on the same power rail are reset and 5VALW has dropped.
- */
-#define HIB_RESET_USEC 1000000
-
-/*
- * Convert between microseconds and the hibernation module RTC subsecond
- * register which has 15-bit resolution. Divide down both numerator and
- * denominator to avoid integer overflow while keeping the math accurate.
- */
-#define HIB_RTC_USEC_TO_SUBSEC(us) ((us) * (32768/64) / (1000000/64))
-#define HIB_RTC_SUBSEC_TO_USEC(ss) ((ss) * (1000000/64) / (32768/64))
-
-/**
- * Wait for a write to commit to a hibernate register.
- *
- * @return EC_SUCCESS if successful, non-zero if error.
- */
-static int wait_for_hibctl_wc(void)
-{
-	int i;
-
-	/* Wait for write-capable */
-	for (i = 0; i < 1000000; i++) {
-		if (LM4_HIBERNATE_HIBCTL & LM4_HIBCTL_WRC)
-			return EC_SUCCESS;
-	}
-	return EC_ERROR_TIMEOUT;
-}
-
-/**
- * Read hibernate register at specified index.
- *
- * @return The value of the register or 0 if invalid index.
- */
-static uint32_t hibdata_read(enum hibdata_index index)
-{
-	if (index < 0 || index >= LM4_HIBERNATE_HIBDATA_ENTRIES)
-		return 0;
-
-	return LM4_HIBERNATE_HIBDATA[index];
-}
-
-/**
- * Write hibernate register at specified index.
- *
- * @return nonzero if error.
- */
-static int hibdata_write(enum hibdata_index index, uint32_t value)
-{
-	int rv;
-
-	if (index < 0 || index >= LM4_HIBERNATE_HIBDATA_ENTRIES)
-		return EC_ERROR_INVAL;
-
-	/* Wait for ok-to-write */
-	rv = wait_for_hibctl_wc();
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	/* Write register */
-	LM4_HIBERNATE_HIBDATA[index] = value;
-
-	/* Wait for write-complete */
-	return wait_for_hibctl_wc();
-}
-
-uint32_t chip_read_reset_flags(void)
-{
-	return hibdata_read(HIBDATA_INDEX_SAVED_RESET_FLAGS);
-}
-
-void chip_save_reset_flags(uint32_t flags)
-{
-	hibdata_write(HIBDATA_INDEX_SAVED_RESET_FLAGS, flags);
-}
-
-static void check_reset_cause(void)
-{
-	uint32_t hib_status = LM4_HIBERNATE_HIBRIS;
-	uint32_t raw_reset_cause = LM4_SYSTEM_RESC;
-	uint32_t hib_wake_flags = hibdata_read(HIBDATA_INDEX_WAKE);
-	uint32_t flags = 0;
-
-	/* Clear the reset causes now that we've read them */
-	LM4_SYSTEM_RESC = 0;
-	wait_for_hibctl_wc();
-	LM4_HIBERNATE_HIBIC = hib_status;
-	hibdata_write(HIBDATA_INDEX_WAKE, 0);
-
-	if (raw_reset_cause & 0x02) {
-		/*
-		 * Full power-on reset of chip.  This resets the flash
-		 * protection registers to their permanently-stored values.
-		 * Note that this is also triggered by hibernation, because
-		 * that de-powers the chip.
-		 */
-		flags |= EC_RESET_FLAG_POWER_ON;
-	} else if (!flags && (raw_reset_cause & 0x01)) {
-		/*
-		 * LM4 signals the reset pin in RESC for all power-on resets,
-		 * even though the external pin wasn't asserted.  Make setting
-		 * this flag mutually-exclusive with power on flag, so we can
-		 * use it to indicate a keyboard-triggered reset.
-		 */
-		flags |= EC_RESET_FLAG_RESET_PIN;
-	}
-
-	if (raw_reset_cause & 0x04)
-		flags |= EC_RESET_FLAG_BROWNOUT;
-
-	if (raw_reset_cause & 0x10)
-		flags |= EC_RESET_FLAG_SOFT;
-
-	if (raw_reset_cause & 0x28) {
-		/* Watchdog timer 0 or 1 */
-		flags |= EC_RESET_FLAG_WATCHDOG;
-	}
-
-	/* Handle other raw reset causes */
-	if (raw_reset_cause && !flags)
-		flags |= EC_RESET_FLAG_OTHER;
-
-
-	if ((hib_status & 0x09) &&
-	    (hib_wake_flags & HIBDATA_WAKE_HARD_RESET)) {
-		/* Hibernation caused by software-triggered hard reset */
-		flags |= EC_RESET_FLAG_HARD;
-
-		/* Consume the hibernate reasons so we don't see them below */
-		hib_status &= ~0x09;
-	}
-
-	if ((hib_status & 0x01) && (hib_wake_flags & HIBDATA_WAKE_RTC))
-		flags |= EC_RESET_FLAG_RTC_ALARM;
-
-	if ((hib_status & 0x08) && (hib_wake_flags & HIBDATA_WAKE_PIN))
-		flags |= EC_RESET_FLAG_WAKE_PIN;
-
-	if (hib_status & 0x04)
-		flags |= EC_RESET_FLAG_LOW_BATTERY;
-
-	/* Restore then clear saved reset flags */
-	flags |= chip_read_reset_flags();
-	chip_save_reset_flags(0);
-
-	system_set_reset_flags(flags);
-}
-
-/*
- * A3 and earlier chip stepping has a problem accessing flash during shutdown.
- * To work around that, we jump to RAM before hibernating.  This function must
- * live in RAM.  It must be called with interrupts disabled, cannot call other
- * functions, and can't be declared static (or else the compiler optimizes it
- * into the main hibernate function.
- */
-void  __attribute__((noinline)) __attribute__((section(".iram.text")))
-__enter_hibernate(int hibctl)
-{
-	LM4_HIBERNATE_HIBCTL = hibctl;
-	while (1)
-		;
-}
-
-/**
- * Read the real-time clock.
- *
- * @param ss_ptr       Destination for sub-seconds value, if not null.
- *
- * @return the real-time clock seconds value.
- */
-uint32_t system_get_rtc_sec_subsec(uint32_t *ss_ptr)
-{
-	uint32_t rtc, rtc2;
-	uint32_t rtcss, rtcss2;
-
-	/*
-	 * The hibernate module isn't synchronized, so need to read repeatedly
-	 * to guarantee a valid read.
-	 */
-	do {
-		rtc = LM4_HIBERNATE_HIBRTCC;
-		rtcss = LM4_HIBERNATE_HIBRTCSS & 0x7fff;
-		rtcss2 = LM4_HIBERNATE_HIBRTCSS & 0x7fff;
-		rtc2 = LM4_HIBERNATE_HIBRTCC;
-	} while (rtc != rtc2 || rtcss != rtcss2);
-
-	if (ss_ptr)
-		*ss_ptr = rtcss;
-
-	return rtc;
-}
-
-timestamp_t system_get_rtc(void)
-{
-	uint32_t rtc, rtc_ss;
-	timestamp_t time;
-
-	rtc = system_get_rtc_sec_subsec(&rtc_ss);
-
-	time.val = ((uint64_t)rtc) * SECOND + HIB_RTC_SUBSEC_TO_USEC(rtc_ss);
-	return time;
-}
-
-/**
- * Set the real-time clock.
- *
- * @param seconds	New clock value.
- */
-void system_set_rtc(uint32_t seconds)
-{
-	wait_for_hibctl_wc();
-	LM4_HIBERNATE_HIBRTCLD = seconds;
-	wait_for_hibctl_wc();
-}
-
-/**
- * Set the hibernate RTC match time at a given time from now
- *
- * @param seconds      Number of seconds from now for RTC match
- * @param microseconds Number of microseconds from now for RTC match
- */
-static void set_hibernate_rtc_match_time(uint32_t seconds,
-					uint32_t microseconds)
-{
-	uint32_t rtc, rtcss;
-
-	/*
-	 * Make sure that the requested delay is not less then the
-	 * amount of time it takes to set the RTC match registers,
-	 * otherwise, the match event could be missed.
-	 */
-	if (seconds == 0 && microseconds < HIB_SET_RTC_MATCH_DELAY_USEC)
-		microseconds = HIB_SET_RTC_MATCH_DELAY_USEC;
-
-	/* Calculate the wake match */
-	rtc = system_get_rtc_sec_subsec(&rtcss) + seconds;
-	rtcss += HIB_RTC_USEC_TO_SUBSEC(microseconds);
-	if (rtcss > 0x7fff) {
-		rtc += rtcss >> 15;
-		rtcss &= 0x7fff;
-	}
-
-	/* Set RTC alarm match */
-	wait_for_hibctl_wc();
-	LM4_HIBERNATE_HIBRTCM0 = rtc;
-	wait_for_hibctl_wc();
-	LM4_HIBERNATE_HIBRTCSS = rtcss << 16;
-	wait_for_hibctl_wc();
-}
-
-/**
- * Use hibernate module to set up an RTC interrupt at a given
- * time from now
- *
- * @param seconds      Number of seconds before RTC interrupt
- * @param microseconds Number of microseconds before RTC interrupt
- */
-void system_set_rtc_alarm(uint32_t seconds, uint32_t microseconds)
-{
-	/* Clear pending interrupt */
-	wait_for_hibctl_wc();
-	LM4_HIBERNATE_HIBIC = LM4_HIBERNATE_HIBRIS;
-
-	/* Set match time */
-	set_hibernate_rtc_match_time(seconds, microseconds);
-
-	/* Enable RTC interrupt on match */
-	wait_for_hibctl_wc();
-	LM4_HIBERNATE_HIBIM = 1;
-
-	/*
-	 * Wait for the write to commit.  This ensures that the RTC interrupt
-	 * actually gets enabled.  This is important if we're about to switch
-	 * the system to the 30 kHz oscillator, which might prevent the write
-	 * from committing.
-	 */
-	wait_for_hibctl_wc();
-}
-
-/**
- * Disable and clear the RTC interrupt.
- */
-void system_reset_rtc_alarm(void)
-{
-	/* Disable hibernate interrupts */
-	wait_for_hibctl_wc();
-	LM4_HIBERNATE_HIBIM = 0;
-
-	/* Clear interrupts */
-	wait_for_hibctl_wc();
-	LM4_HIBERNATE_HIBIC = LM4_HIBERNATE_HIBRIS;
-}
-
-/**
- * Hibernate module interrupt
- */
-void __hibernate_irq(void)
-{
-	system_reset_rtc_alarm();
-}
-DECLARE_IRQ(LM4_IRQ_HIBERNATE, __hibernate_irq, 1);
-
-/**
- * Enable hibernate interrupt
- */
-void system_enable_hib_interrupt(void)
-{
-	task_enable_irq(LM4_IRQ_HIBERNATE);
-}
-
-/**
- * Internal hibernate function.
- *
- * @param seconds      Number of seconds to sleep before RTC alarm
- * @param microseconds Number of microseconds to sleep before RTC alarm
- * @param flags        Additional hibernate wake flags
- */
-static void hibernate(uint32_t seconds, uint32_t microseconds, uint32_t flags)
-{
-	uint32_t hibctl;
-
-	/* Set up wake reasons and hibernate flags */
-	hibctl = LM4_HIBERNATE_HIBCTL | LM4_HIBCTL_PINWEN;
-
-	if (flags & HIBDATA_WAKE_PIN)
-		hibctl |= LM4_HIBCTL_PINWEN;
-	else
-		hibctl &= ~LM4_HIBCTL_PINWEN;
-
-	if (seconds || microseconds) {
-		hibctl |= LM4_HIBCTL_RTCWEN;
-		flags |= HIBDATA_WAKE_RTC;
-
-		set_hibernate_rtc_match_time(seconds, microseconds);
-
-		/* Enable RTC interrupt on match */
-		wait_for_hibctl_wc();
-		LM4_HIBERNATE_HIBIM = 1;
-	} else {
-		hibctl &= ~LM4_HIBCTL_RTCWEN;
-	}
-	wait_for_hibctl_wc();
-	LM4_HIBERNATE_HIBCTL = hibctl;
-
-	/* Clear pending interrupt */
-	wait_for_hibctl_wc();
-	LM4_HIBERNATE_HIBIC = LM4_HIBERNATE_HIBRIS;
-
-	/* Store hibernate flags */
-	hibdata_write(HIBDATA_INDEX_WAKE, flags);
-
-	__enter_hibernate(hibctl | LM4_HIBCTL_HIBREQ);
-}
-
-void system_hibernate(uint32_t seconds, uint32_t microseconds)
-{
-	/* Flush console before hibernating */
-	cflush();
-	hibernate(seconds, microseconds, HIBDATA_WAKE_PIN);
-}
-
-void chip_pre_init(void)
-{
-	/* Enable clocks to GPIO block C in run and sleep modes. */
-	clock_enable_peripheral(CGC_OFFSET_GPIO, 0x0004, CGC_MODE_ALL);
-
-	/*
-	 * Ensure PC0:3 are set to JTAG function.  They should be set this way
-	 * on a cold boot, but on a warm reboot a previous misbehaving image
-	 * could have set them differently.
-	 */
-	if (((LM4_GPIO_PCTL(LM4_GPIO_C) & 0x0000ffff) == 0x00001111) &&
-	    ((LM4_GPIO_AFSEL(LM4_GPIO_C) & 0x0f) == 0x0f) &&
-	    ((LM4_GPIO_DEN(LM4_GPIO_C) & 0x0f) == 0x0f) &&
-	    ((LM4_GPIO_PUR(LM4_GPIO_C) & 0x0f) == 0x0f))
-		return;  /* Already properly configured */
-
-	/* Unlock commit register for JTAG pins */
-	LM4_GPIO_LOCK(LM4_GPIO_C) = LM4_GPIO_LOCK_UNLOCK;
-	LM4_GPIO_CR(LM4_GPIO_C) |= 0x0f;
-
-	/* Reset JTAG pins */
-	LM4_GPIO_PCTL(LM4_GPIO_C) =
-		(LM4_GPIO_PCTL(LM4_GPIO_C) & 0xffff0000) | 0x00001111;
-	LM4_GPIO_AFSEL(LM4_GPIO_C) |= 0x0f;
-	LM4_GPIO_DEN(LM4_GPIO_C) |= 0x0f;
-	LM4_GPIO_PUR(LM4_GPIO_C) |= 0x0f;
-
-	/* Set interrupt on either edge of the JTAG signals */
-	LM4_GPIO_IS(LM4_GPIO_C) &= ~0x0f;
-	LM4_GPIO_IBE(LM4_GPIO_C) |= 0x0f;
-
-	/* Re-lock commit register */
-	LM4_GPIO_CR(LM4_GPIO_C) &= ~0x0f;
-	LM4_GPIO_LOCK(LM4_GPIO_C) = 0;
-}
-
-void system_pre_init(void)
-{
-	uint32_t hibctl;
-#ifdef CONFIG_SOFTWARE_PANIC
-	uint32_t reason, info;
-	uint8_t exception;
-#endif
-
-	/*
-	 * Enable clocks to the hibernation module in run, sleep,
-	 * and deep sleep modes.
-	 */
-	clock_enable_peripheral(CGC_OFFSET_HIB, 0x1, CGC_MODE_ALL);
-
-	/*
-	 * Enable the hibernation oscillator, if it's not already enabled.
-	 * This should only need setting if the EC completely lost power (for
-	 * example, the battery was pulled).
-	 */
-	if (!(LM4_HIBERNATE_HIBCTL & LM4_HIBCTL_CLK32EN)) {
-		int i;
-
-		/* Enable clock to hibernate module */
-		wait_for_hibctl_wc();
-		LM4_HIBERNATE_HIBCTL |= LM4_HIBCTL_CLK32EN;
-
-		/* Wait for write-complete */
-		for (i = 0; i < 1000000; i++) {
-			if (LM4_HIBERNATE_HIBRIS & 0x10)
-				break;
-		}
-
-		/* Enable and reset RTC */
-		wait_for_hibctl_wc();
-		LM4_HIBERNATE_HIBCTL |= LM4_HIBCTL_RTCEN;
-		system_set_rtc(0);
-
-		/* Clear all hibernate data entries */
-		for (i = 0; i < LM4_HIBERNATE_HIBDATA_ENTRIES; i++)
-			hibdata_write(i, 0);
-	}
-
-	/*
-	 * Set wake reasons to RTC match and WAKE pin by default.
-	 * Before going in to hibernate, these may change.
-	 */
-	hibctl = LM4_HIBERNATE_HIBCTL;
-	hibctl |= LM4_HIBCTL_RTCWEN;
-	hibctl |= LM4_HIBCTL_PINWEN;
-	wait_for_hibctl_wc();
-	LM4_HIBERNATE_HIBCTL = hibctl;
-
-	/*
-	 * Initialize registers after reset to work around LM4 chip errata
-	 * (still present in A3 chip stepping).
-	 */
-	wait_for_hibctl_wc();
-	LM4_HIBERNATE_HIBRTCT = 0x7fff;
-	wait_for_hibctl_wc();
-	LM4_HIBERNATE_HIBIM = 0;
-
-	check_reset_cause();
-
-#ifdef CONFIG_SOFTWARE_PANIC
-	/* Restore then clear saved panic reason */
-	reason = hibdata_read(HIBDATA_INDEX_SAVED_PANIC_REASON);
-	info = hibdata_read(HIBDATA_INDEX_SAVED_PANIC_INFO);
-	exception = hibdata_read(HIBDATA_INDEX_SAVED_PANIC_EXCEPTION);
-	if (reason || info || exception) {
-		panic_set_reason(reason, info, exception);
-		hibdata_write(HIBDATA_INDEX_SAVED_PANIC_REASON, 0);
-		hibdata_write(HIBDATA_INDEX_SAVED_PANIC_INFO, 0);
-		hibdata_write(HIBDATA_INDEX_SAVED_PANIC_EXCEPTION, 0);
-	}
-#endif
-
-	/* Initialize bootcfg if needed */
-	if (LM4_SYSTEM_BOOTCFG != CONFIG_BOOTCFG_VALUE) {
-		/* read-modify-write */
-		LM4_FLASH_FMD = (LM4_SYSTEM_BOOTCFG_MASK & LM4_SYSTEM_BOOTCFG)
-			| (~LM4_SYSTEM_BOOTCFG_MASK & CONFIG_BOOTCFG_VALUE);
-		LM4_FLASH_FMA = 0x75100000;
-		LM4_FLASH_FMC = 0xa4420008;  /* WRKEY | COMT */
-		while (LM4_FLASH_FMC & 0x08)
-			;
-	}
-
-	/* Brown-outs should trigger a reset */
-	LM4_SYSTEM_PBORCTL |= 0x02;
-}
-
-void system_reset(int flags)
-{
-	uint32_t save_flags = 0;
-
-	/* Disable interrupts to avoid task swaps during reboot */
-	interrupt_disable();
-
-	/* Save current reset reasons if necessary */
-	if (flags & SYSTEM_RESET_PRESERVE_FLAGS)
-		save_flags = system_get_reset_flags() | EC_RESET_FLAG_PRESERVED;
-
-	if (flags & SYSTEM_RESET_LEAVE_AP_OFF)
-		save_flags |= EC_RESET_FLAG_AP_OFF;
-
-	chip_save_reset_flags(save_flags);
-
-	if (flags & SYSTEM_RESET_HARD) {
-#ifdef CONFIG_SOFTWARE_PANIC
-		uint32_t reason, info;
-		uint8_t exception;
-
-		/* Panic data will be wiped by hard reset, so save it */
-		panic_get_reason(&reason, &info, &exception);
-		hibdata_write(HIBDATA_INDEX_SAVED_PANIC_REASON, reason);
-		hibdata_write(HIBDATA_INDEX_SAVED_PANIC_INFO, info);
-		hibdata_write(HIBDATA_INDEX_SAVED_PANIC_EXCEPTION, exception);
-#endif
-
-		/*
-		 * Bounce through hibernate to trigger a hard reboot.  Do
-		 * not wake on wake pin, since we need the full duration.
-		 */
-		hibernate(0, HIB_RESET_USEC, HIBDATA_WAKE_HARD_RESET);
-	} else
-		CPU_NVIC_APINT = 0x05fa0004;
-
-	/* Spin and wait for reboot; should never return */
-	while (1)
-		;
-}
-
-int system_set_scratchpad(uint32_t value)
-{
-	return hibdata_write(HIBDATA_INDEX_SCRATCHPAD, value);
-}
-
-uint32_t system_get_scratchpad(void)
-{
-	return hibdata_read(HIBDATA_INDEX_SCRATCHPAD);
-}
-
-const char *system_get_chip_vendor(void)
-{
-	return "ti";
-}
-
-static char to_hex(int x)
-{
-	if (x >= 0 && x <= 9)
-		return '0' + x;
-	return 'a' + x - 10;
-}
-
-const char *system_get_chip_id_string(void)
-{
-	static char str[15] = "Unknown-";
-	char *p = str + 8;
-	uint32_t did = LM4_SYSTEM_DID1 >> 16;
-
-	if (*p)
-		return (const char *)str;
-
-	*p = to_hex(did >> 12);
-	*(p + 1) = to_hex((did >> 8) & 0xf);
-	*(p + 2) = to_hex((did >> 4) & 0xf);
-	*(p + 3) = to_hex(did & 0xf);
-	*(p + 4) = '\0';
-
-	return (const char *)str;
-}
-
-const char *system_get_raw_chip_name(void)
-{
-	switch ((LM4_SYSTEM_DID1 & 0xffff0000) >> 16) {
-	case 0x10de:
-		return "tm4e1g31h6zrb";
-	case 0x10e2:
-		return "lm4fsxhh5bb";
-	case 0x10e3:
-		return "lm4fs232h5bb";
-	case 0x10e4:
-		return "lm4fs99h5bb";
-	case 0x10e6:
-		return "lm4fs1ah5bb";
-	case 0x10ea:
-		return "lm4fs1gh5bb";
-	default:
-		return system_get_chip_id_string();
-	}
-}
-
-const char *system_get_chip_name(void)
-{
-	const char *postfix = "-tm"; /* test mode */
-	static char str[20];
-	const char *raw_chip_name = system_get_raw_chip_name();
-	char *p = str;
-
-	if (LM4_TEST_MODE_ENABLED) {
-		/* Debug mode is enabled. Postfix chip name. */
-		while (*raw_chip_name)
-			*(p++) = *(raw_chip_name++);
-		while (*postfix)
-			*(p++) = *(postfix++);
-		*p = '\0';
-		return (const char *)str;
-	} else {
-		return raw_chip_name;
-	}
-}
-
-int system_get_bbram(enum system_bbram_idx idx, uint8_t *value)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-int system_set_bbram(enum system_bbram_idx idx, uint8_t value)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-const char *system_get_chip_revision(void)
-{
-	static char rev[3];
-
-	/* Extract the major[15:8] and minor[7:0] revisions. */
-	rev[0] = 'A' + ((LM4_SYSTEM_DID0 >> 8) & 0xff);
-	rev[1] = '0' + (LM4_SYSTEM_DID0 & 0xff);
-	rev[2] = 0;
-
-	return rev;
-}
-
-/*****************************************************************************/
-/* Console commands */
-void print_system_rtc(enum console_channel ch)
-{
-	uint32_t rtc;
-	uint32_t rtcss;
-
-	rtc = system_get_rtc_sec_subsec(&rtcss);
-	cprintf(ch, "RTC: 0x%08x.%04x (%d.%06d s)\n",
-		 rtc, rtcss, rtc, HIB_RTC_SUBSEC_TO_USEC(rtcss));
-}
-
-#ifdef CONFIG_CMD_RTC
-static int command_system_rtc(int argc, char **argv)
-{
-	if (argc == 3 && !strcasecmp(argv[1], "set")) {
-		char *e;
-		uint32_t t = strtoi(argv[2], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM2;
-
-		system_set_rtc(t);
-	} else if (argc > 1) {
-		return EC_ERROR_INVAL;
-	}
-
-	print_system_rtc(CC_COMMAND);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(rtc, command_system_rtc,
-			"[set <seconds>]",
-			"Get/set real-time clock");
-
-#ifdef CONFIG_CMD_RTC_ALARM
-/**
- * Test the RTC alarm by setting an interrupt on RTC match.
- */
-static int command_rtc_alarm_test(int argc, char **argv)
-{
-	int s = 1, us = 0;
-	char *e;
-
-	ccprintf("Setting RTC alarm\n");
-	system_enable_hib_interrupt();
-
-	if (argc > 1) {
-		s = strtoi(argv[1], &e, 10);
-		if (*e)
-			return EC_ERROR_PARAM1;
-
-	}
-	if (argc > 2) {
-		us = strtoi(argv[2], &e, 10);
-		if (*e)
-			return EC_ERROR_PARAM2;
-
-	}
-
-	system_set_rtc_alarm(s, us);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(rtc_alarm, command_rtc_alarm_test,
-			"[seconds [microseconds]]",
-			"Test alarm");
-#endif /* CONFIG_CMD_RTC_ALARM */
-#endif /* CONFIG_CMD_RTC */
-
-/*****************************************************************************/
-/* Host commands */
-
-#ifdef CONFIG_HOSTCMD_RTC
-static enum ec_status system_rtc_get_value(struct host_cmd_handler_args *args)
-{
-	struct ec_response_rtc *r = args->response;
-
-	r->time = system_get_rtc_sec_subsec(NULL);
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_VALUE,
-		     system_rtc_get_value,
-		     EC_VER_MASK(0));
-
-static enum ec_status system_rtc_set_value(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_rtc *p = args->params;
-
-	system_set_rtc(p->time);
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_VALUE,
-		     system_rtc_set_value,
-		     EC_VER_MASK(0));
-#endif /* CONFIG_HOSTCMD_RTC */
diff --git a/chip/lm4/uart.c b/chip/lm4/uart.c
deleted file mode 100644
index 7ccea9eb75..0000000000
--- a/chip/lm4/uart.c
+++ /dev/null
@@ -1,352 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* UART module for Chrome EC */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "lpc.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "uart.h"
-#include "util.h"
-
-#ifdef CONFIG_UART_HOST
-#define IRQ_UART_HOST CONCAT2(LM4_IRQ_UART, CONFIG_UART_HOST)
-#endif
-
-static int init_done;
-
-int uart_init_done(void)
-{
-	return init_done;
-}
-
-void uart_tx_start(void)
-{
-	/* If interrupt is already enabled, nothing to do */
-	if (LM4_UART_IM(0) & 0x20)
-		return;
-
-	/* Do not allow deep sleep while transmit in progress */
-	disable_sleep(SLEEP_MASK_UART);
-
-	/*
-	 * Re-enable the transmit interrupt, then forcibly trigger the
-	 * interrupt.  This works around a hardware problem with the
-	 * UART where the FIFO only triggers the interrupt when its
-	 * threshold is _crossed_, not just met.
-	 */
-	LM4_UART_IM(0) |= 0x20;
-	task_trigger_irq(LM4_IRQ_UART0);
-}
-
-void uart_tx_stop(void)
-{
-	LM4_UART_IM(0) &= ~0x20;
-
-	/* Re-allow deep sleep */
-	enable_sleep(SLEEP_MASK_UART);
-}
-
-void uart_tx_flush(void)
-{
-	/* Wait for transmit FIFO empty */
-	while (!(LM4_UART_FR(0) & 0x80))
-		;
-}
-
-int uart_tx_ready(void)
-{
-	return !(LM4_UART_FR(0) & 0x20);
-}
-
-int uart_tx_in_progress(void)
-{
-	/* Transmit is in progress if the TX busy bit is set. */
-	return LM4_UART_FR(0) & 0x08;
-}
-
-int uart_rx_available(void)
-{
-	return !(LM4_UART_FR(0) & 0x10);
-}
-
-void uart_write_char(char c)
-{
-	/* Wait for space in transmit FIFO. */
-	while (!uart_tx_ready())
-		;
-
-	LM4_UART_DR(0) = c;
-}
-
-int uart_read_char(void)
-{
-	return LM4_UART_DR(0);
-}
-
-static void uart_clear_rx_fifo(int channel)
-{
-	int scratch __attribute__ ((unused));
-	while (!(LM4_UART_FR(channel) & 0x10))
-		scratch = LM4_UART_DR(channel);
-}
-
-/**
- * Interrupt handler for UART0
- */
-void uart_ec_interrupt(void)
-{
-	/* Clear transmit and receive interrupt status */
-	LM4_UART_ICR(0) = 0x70;
-
-
-	/* Read input FIFO until empty, then fill output FIFO */
-	uart_process_input();
-	uart_process_output();
-}
-DECLARE_IRQ(LM4_IRQ_UART0, uart_ec_interrupt, 1);
-
-#ifdef CONFIG_UART_HOST
-
-/**
- * Interrupt handler for Host UART
- */
-void uart_host_interrupt(void)
-{
-	/* Clear transmit and receive interrupt status */
-	LM4_UART_ICR(CONFIG_UART_HOST) = 0x70;
-
-#ifdef CONFIG_HOSTCMD_LPC
-	/*
-	 * If we have space in our FIFO and a character is pending in LPC,
-	 * handle that character.
-	 */
-	if (!(LM4_UART_FR(CONFIG_UART_HOST) & 0x20) && lpc_comx_has_char()) {
-		/* Copy the next byte then disable transmit interrupt */
-		LM4_UART_DR(CONFIG_UART_HOST) = lpc_comx_get_char();
-		LM4_UART_IM(CONFIG_UART_HOST) &= ~0x20;
-	}
-
-	/*
-	 * Handle received character.  There is no flow control on input;
-	 * received characters are blindly forwarded to LPC.  This is ok
-	 * because LPC is much faster than UART, and we don't have flow control
-	 * on the UART receive-side either.
-	 */
-	if (!(LM4_UART_FR(CONFIG_UART_HOST) & 0x10))
-		lpc_comx_put_char(LM4_UART_DR(CONFIG_UART_HOST));
-#endif
-}
-/* Must be same prio as LPC interrupt handler so they don't preempt */
-DECLARE_IRQ(IRQ_UART_HOST, uart_host_interrupt, 2);
-
-#endif /* CONFIG_UART_HOST */
-
-static void uart_config(int port)
-{
-	/* Disable the port */
-	LM4_UART_CTL(port) = 0x0300;
-	/* Use the internal oscillator */
-	LM4_UART_CC(port) = 0x1;
-	/* Set the baud rate divisor */
-	LM4_UART_IBRD(port) = (INTERNAL_CLOCK / 16) / CONFIG_UART_BAUD_RATE;
-	LM4_UART_FBRD(port) =
-		(((INTERNAL_CLOCK / 16) % CONFIG_UART_BAUD_RATE) * 64
-		 + CONFIG_UART_BAUD_RATE / 2) / CONFIG_UART_BAUD_RATE;
-	/*
-	 * 8-N-1, FIFO enabled.  Must be done after setting
-	 * the divisor for the new divisor to take effect.
-	 */
-	LM4_UART_LCRH(port) = 0x70;
-	/*
-	 * Interrupt when RX fifo at minimum (>= 1/8 full), and TX fifo
-	 * when <= 1/4 full
-	 */
-	LM4_UART_IFLS(port) = 0x01;
-	/*
-	 * Unmask receive-FIFO, receive-timeout.  We need
-	 * receive-timeout because the minimum RX FIFO depth is 1/8 = 2
-	 * bytes; without the receive-timeout we'd never be notified
-	 * about single received characters.
-	 */
-	LM4_UART_IM(port) = 0x50;
-	/* Enable the port */
-	LM4_UART_CTL(port) |= 0x0001;
-}
-
-void uart_init(void)
-{
-	uint32_t mask = 0;
-
-	/*
-	 * Enable UART0 in run, sleep, and deep sleep modes. Enable the Host
-	 * UART in run and sleep modes.
-	 */
-	mask |= 1;
-	clock_enable_peripheral(CGC_OFFSET_UART, mask, CGC_MODE_ALL);
-
-#ifdef CONFIG_UART_HOST
-	mask |= BIT(CONFIG_UART_HOST);
-#endif
-
-	clock_enable_peripheral(CGC_OFFSET_UART, mask,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-
-	gpio_config_module(MODULE_UART, 1);
-
-	/* Configure UARTs (identically) */
-	uart_config(0);
-
-#ifdef CONFIG_UART_HOST
-	uart_config(CONFIG_UART_HOST);
-#endif
-
-	/*
-	 * Enable interrupts for UART0 only. Host UART will have to wait
-	 * until the LPC bus is initialized.
-	 */
-	uart_clear_rx_fifo(0);
-	task_enable_irq(LM4_IRQ_UART0);
-
-	init_done = 1;
-}
-
-#ifdef CONFIG_LOW_POWER_IDLE
-void uart_enter_dsleep(void)
-{
-	const struct gpio_info g = gpio_list[GPIO_UART0_RX];
-
-	/* Disable the UART0 module interrupt. */
-	task_disable_irq(LM4_IRQ_UART0);
-
-	/* Disable UART0 peripheral in deep sleep. */
-	clock_disable_peripheral(CGC_OFFSET_UART, 0x1, CGC_MODE_DSLEEP);
-
-	/*
-	 * Set the UART0 RX pin to be a generic GPIO with the flags defined
-	 * in the board.c file.
-	 */
-	gpio_reset(GPIO_UART0_RX);
-
-	/* Clear any pending GPIO interrupts on the UART0 RX pin. */
-	LM4_GPIO_ICR(g.port) = g.mask;
-
-	/* Enable GPIO interrupts on the UART0 RX pin. */
-	gpio_enable_interrupt(GPIO_UART0_RX);
-}
-
-void uart_exit_dsleep(void)
-{
-	const struct gpio_info g = gpio_list[GPIO_UART0_RX];
-
-	/*
-	 * If the UART0 RX GPIO interrupt has not fired, then no edge has been
-	 * detected. Disable the GPIO interrupt so that switching the pin over
-	 * to a UART pin doesn't inadvertently cause a GPIO edge interrupt.
-	 * Note: we can't disable this interrupt if it has already fired
-	 * because then the IRQ will not get called.
-	 */
-	if (!(LM4_GPIO_MIS(g.port) & g.mask))
-		gpio_disable_interrupt(GPIO_UART0_RX);
-
-	/* Configure UART0 pins for use in UART peripheral. */
-	gpio_config_module(MODULE_UART, 1);
-
-	/* Clear pending interrupts on UART peripheral and enable interrupts. */
-	uart_clear_rx_fifo(0);
-	task_enable_irq(LM4_IRQ_UART0);
-
-	/* Enable UART0 peripheral in deep sleep */
-	clock_enable_peripheral(CGC_OFFSET_UART, 0x1, CGC_MODE_DSLEEP);
-}
-
-void uart_deepsleep_interrupt(enum gpio_signal signal)
-{
-	/*
-	 * Activity seen on UART RX pin while UART was disabled for deep sleep.
-	 * The console won't see that character because the UART is disabled,
-	 * so we need to inform the clock module of UART activity ourselves.
-	 */
-	clock_refresh_console_in_use();
-
-	/* Disable interrupts on UART0 RX pin to avoid repeated interrupts. */
-	gpio_disable_interrupt(GPIO_UART0_RX);
-}
-#endif /* CONFIG_LOW_POWER_IDLE */
-
-
-/*****************************************************************************/
-/* COMx functions */
-
-#ifdef CONFIG_UART_HOST
-
-void uart_comx_enable(void)
-{
-	uart_clear_rx_fifo(CONFIG_UART_HOST);
-	task_enable_irq(IRQ_UART_HOST);
-}
-
-int uart_comx_putc_ok(void)
-{
-	if (LM4_UART_FR(CONFIG_UART_HOST) & 0x20) {
-		/*
-		 * FIFO is full, so enable transmit interrupt to let us know
-		 * when it empties.
-		 */
-		LM4_UART_IM(CONFIG_UART_HOST) |= 0x20;
-		return 0;
-	} else {
-		return 1;
-	}
-}
-
-void uart_comx_putc(int c)
-{
-	LM4_UART_DR(CONFIG_UART_HOST) = c;
-}
-
-#endif /* CONFIG_UART_HOST */
-
-/*****************************************************************************/
-/* Console commands */
-
-#ifdef CONFIG_CMD_COMXTEST
-
-/**
- * Write a character to COMx, waiting for space in the output buffer if
- * necessary.
- */
-static void uart_comx_putc_wait(int c)
-{
-		while (!uart_comx_putc_ok())
-			;
-		uart_comx_putc(c);
-}
-
-static int command_comxtest(int argc, char **argv)
-{
-	/* Put characters to COMX port */
-	const char *c = argc > 1 ? argv[1] : "testing comx output!";
-
-	ccprintf("Writing \"%s\\r\\n\" to COMx UART...\n", c);
-
-	while (*c)
-		uart_comx_putc_wait(*c++);
-
-	uart_comx_putc_wait('\r');
-	uart_comx_putc_wait('\n');
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(comxtest, command_comxtest,
-			"[string]",
-			"Write test data to COMx uart");
-
-#endif /* CONFIG_CMD_COMXTEST */
diff --git a/chip/lm4/watchdog.c b/chip/lm4/watchdog.c
deleted file mode 100644
index 50f122bf02..0000000000
--- a/chip/lm4/watchdog.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Watchdog driver */
-
-#include "clock.h"
-#include "common.h"
-#include "registers.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "task.h"
-#include "util.h"
-#include "watchdog.h"
-
-/*
- * We use watchdog 0 which is clocked on the system clock
- * to avoid the penalty cycles on each write access
- */
-
-/* magic value to unlock the watchdog registers */
-#define LM4_WATCHDOG_MAGIC_WORD  0x1ACCE551
-
-static uint32_t watchdog_period;     /* Watchdog counter initial value */
-
-void IRQ_HANDLER(LM4_IRQ_WATCHDOG)(void) __attribute__((naked));
-void IRQ_HANDLER(LM4_IRQ_WATCHDOG)(void)
-{
-	/* Naked call so we can extract raw LR and SP */
-	asm volatile("mov r0, lr\n"
-		     "mov r1, sp\n"
-		     /* Must push registers in pairs to keep 64-bit aligned
-		      * stack for ARM EABI.  This also conveniently saves
-		      * R0=LR so we can pass it to task_resched_if_needed. */
-		     "push {r0, lr}\n"
-		     "bl watchdog_trace\n"
-		      /* Do NOT reset the watchdog interrupt here; it will
-		       * be done in watchdog_reload(), or reset will be
-		       * triggered if we don't call that by the next watchdog
-		       * period.  Instead, de-activate the interrupt in the
-		       * NVIC, so the watchdog trace will only be printed
-		       * once.
-		       */
-		     "mov r0, %[irq]\n"
-		     "bl task_disable_irq\n"
-		     "pop {r0, lr}\n"
-		     "b task_resched_if_needed\n"
-			: : [irq] "i" (LM4_IRQ_WATCHDOG));
-}
-const struct irq_priority __keep IRQ_PRIORITY(LM4_IRQ_WATCHDOG)
-	__attribute__((section(".rodata.irqprio")))
-		= {LM4_IRQ_WATCHDOG, 0}; /* put the watchdog at the highest
-					    priority */
-
-void watchdog_reload(void)
-{
-	uint32_t status = LM4_WATCHDOG_RIS(0);
-
-	/* Unlock watchdog registers */
-	LM4_WATCHDOG_LOCK(0) = LM4_WATCHDOG_MAGIC_WORD;
-
-	/* As we reboot only on the second timeout, if we have already reached
-	 * the first timeout we need to reset the interrupt bit. */
-	if (status) {
-		LM4_WATCHDOG_ICR(0) = status;
-		/* That doesn't seem to unpend the watchdog interrupt (even if
-		 * we do writes to force the write to be committed), so
-		 * explicitly unpend the interrupt before re-enabling it. */
-		task_clear_pending_irq(LM4_IRQ_WATCHDOG);
-		task_enable_irq(LM4_IRQ_WATCHDOG);
-	}
-
-	/* Reload the watchdog counter */
-	LM4_WATCHDOG_LOAD(0) = watchdog_period;
-
-	/* Re-lock watchdog registers */
-	LM4_WATCHDOG_LOCK(0) = 0xdeaddead;
-}
-DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT);
-
-static void watchdog_freq_changed(void)
-{
-	/* Set the timeout period */
-	watchdog_period = CONFIG_WATCHDOG_PERIOD_MS * (clock_get_freq() / 1000);
-
-	/* Reload the watchdog timer now */
-	watchdog_reload();
-}
-DECLARE_HOOK(HOOK_FREQ_CHANGE, watchdog_freq_changed, HOOK_PRIO_DEFAULT);
-
-int watchdog_init(void)
-{
-	/* Enable watchdog 0 clock in run, sleep, and deep sleep modes */
-	clock_enable_peripheral(CGC_OFFSET_WD, 0x1, CGC_MODE_ALL);
-
-	/* Set initial timeout period */
-	watchdog_freq_changed();
-
-	/* Unlock watchdog registers */
-	LM4_WATCHDOG_LOCK(0) = LM4_WATCHDOG_MAGIC_WORD;
-
-	/* De-activate the watchdog when the JTAG stops the CPU */
-	LM4_WATCHDOG_TEST(0) |= BIT(8);
-
-	/* Reset after 2 time-out, activate the watchdog and lock the control
-	 * register. */
-	LM4_WATCHDOG_CTL(0) = 0x3;
-
-	/* Reset watchdog interrupt bits */
-	LM4_WATCHDOG_ICR(0) = LM4_WATCHDOG_RIS(0);
-
-	/* Lock watchdog registers against unintended accesses */
-	LM4_WATCHDOG_LOCK(0) = 0xdeaddead;
-
-	/* Enable watchdog interrupt */
-	task_enable_irq(LM4_IRQ_WATCHDOG);
-
-	return EC_SUCCESS;
-}
diff --git a/chip/max32660/build.mk b/chip/max32660/build.mk
index e0f5636b2e..e0db8bc646 100644
--- a/chip/max32660/build.mk
+++ b/chip/max32660/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -9,7 +9,7 @@
 # MAX32660 SoC has a Cortex-M4F ARM core
 CORE:=cortex-m
 # Allow the full Cortex-M4 instruction set
-CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
+CFLAGS_CPU+=-mcpu=cortex-m4
 
 # Required chip modules
 chip-y=clock_chip.o gpio_chip.o system_chip.o hwtimer_chip.o uart_chip.o
@@ -18,4 +18,3 @@ chip-$(CONFIG_I2C)+=i2c_chip.o
 # Optional chip modules
 chip-$(CONFIG_FLASH_PHYSICAL)+=flash_chip.o
 chip-$(CONFIG_WATCHDOG)+=wdt_chip.o
-
diff --git a/chip/max32660/clock_chip.c b/chip/max32660/clock_chip.c
index 901c5d559c..83fb2fa1d1 100644
--- a/chip/max32660/clock_chip.c
+++ b/chip/max32660/clock_chip.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,16 +9,16 @@
 #include "common.h"
 #include "console.h"
 #include "cpu.h"
+#include "gcr_regs.h"
 #include "hooks.h"
 #include "hwtimer.h"
+#include "pwrseq_regs.h"
 #include "registers.h"
 #include "system.h"
 #include "timer.h"
+#include "tmr_regs.h"
 #include "util.h"
 #include "watchdog.h"
-#include "tmr_regs.h"
-#include "gcr_regs.h"
-#include "pwrseq_regs.h"
 
 #define MAX32660_SYSTEMCLOCK SYS_CLOCK_HIRC
 
@@ -26,9 +26,9 @@
 typedef enum {
 	SYS_CLOCK_NANORING = MXC_V_GCR_CLKCN_CLKSEL_NANORING, /**< 8KHz nanoring
 								 on MAX32660 */
-	SYS_CLOCK_HFXIN =
-		MXC_V_GCR_CLKCN_CLKSEL_HFXIN, /**< 32KHz on MAX32660 */
-	SYS_CLOCK_HFXIN_DIGITAL = 0x9,	/**< External Clock Input*/
+	SYS_CLOCK_HFXIN = MXC_V_GCR_CLKCN_CLKSEL_HFXIN, /**< 32KHz on MAX32660
+							 */
+	SYS_CLOCK_HFXIN_DIGITAL = 0x9, /**< External Clock Input*/
 	SYS_CLOCK_HIRC = MXC_V_GCR_CLKCN_CLKSEL_HIRC, /**< High Frequency
 							 Internal Oscillator */
 } sys_system_clock_t;
@@ -139,3 +139,7 @@ void clock_init(void)
 		}
 	}
 }
+
+test_mockable void clock_enable_module(enum module_id module, int enable)
+{
+}
diff --git a/chip/max32660/config_chip.h b/chip/max32660/config_chip.h
index b74ec591ad..9fa939a918 100644
--- a/chip/max32660/config_chip.h
+++ b/chip/max32660/config_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -50,7 +50,7 @@
 #define TASK_STACK_SIZE 512
 
 #define CONFIG_PROGRAM_MEMORY_BASE 0x00000000
-#define CONFIG_FLASH_BANK_SIZE 0x00002000  /* protect bank size */
+#define CONFIG_FLASH_BANK_SIZE 0x00002000 /* protect bank size */
 #define CONFIG_FLASH_ERASE_SIZE 0x00002000 /* erase bank size */
 #define CONFIG_FLASH_WRITE_SIZE 0x00000004 /* minimum write size */
 
@@ -61,7 +61,7 @@
  * in order to emulate per-bank write-protection UNTIL REBOOT. The hardware
  * doesn't support a write-protect pin, and if we make the write-protection
  * permanent, it can't be undone easily enough to support RMA. */
-#define CONFIG_FLASH_SIZE 0x00040000 /* 256K MAX32660 FLASH Size */
+#define CONFIG_FLASH_SIZE_BYTES 0x00040000 /* 256K MAX32660 FLASH Size */
 
 /****************************************************************************/
 /* Define our flash layout. */
diff --git a/chip/max32660/flash_chip.c b/chip/max32660/flash_chip.c
index ace87294a7..01a26f94b5 100644
--- a/chip/max32660/flash_chip.c
+++ b/chip/max32660/flash_chip.c
@@ -1,20 +1,20 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* MAX32660 Flash Memory Module for Chrome EC */
 
+#include "common.h"
 #include "flash.h"
+#include "flc_regs.h"
+#include "icc_regs.h"
+#include "registers.h"
 #include "switch.h"
 #include "system.h"
 #include "timer.h"
 #include "util.h"
 #include "watchdog.h"
-#include "registers.h"
-#include "common.h"
-#include "icc_regs.h"
-#include "flc_regs.h"
 
 #define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
 #define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
@@ -25,7 +25,7 @@
 #define MXC_FLASH_PAGE_MASK ~(MXC_FLASH_PAGE_SIZE - 1)
 
 /// Calculate the address of a page in flash from the page number
-#define MXC_FLASH_PAGE_ADDR(page)                                              \
+#define MXC_FLASH_PAGE_ADDR(page) \
 	(MXC_FLASH_MEM_BASE + ((unsigned long)page * MXC_FLASH_PAGE_SIZE))
 
 void flash_operation(void)
@@ -108,7 +108,7 @@ static int flash_device_page_erase(uint32_t address)
 	return EC_SUCCESS;
 }
 
-int flash_physical_write(int offset, int size, const char *data)
+int crec_flash_physical_write(int offset, int size, const char *data)
 {
 	int err;
 	uint32_t bytes_written;
@@ -123,7 +123,6 @@ int flash_physical_write(int offset, int size, const char *data)
 
 	// Align the address and read/write if we have to
 	if (offset & 0x3) {
-
 		// Figure out how many bytes we have to write to round up the
 		// address
 		bytes_written = 4 - (offset & 0x3);
@@ -163,7 +162,6 @@ int flash_physical_write(int offset, int size, const char *data)
 	}
 
 	if (size >= 16) {
-
 		// write in 128-bit bursts while we can
 		MXC_FLC->cn &= ~MXC_F_FLC_CN_WDTH;
 
@@ -232,7 +230,7 @@ int flash_physical_write(int offset, int size, const char *data)
 /*****************************************************************************/
 /* Physical layer APIs */
 
-int flash_physical_erase(int offset, int size)
+int crec_flash_physical_erase(int offset, int size)
 {
 	int i;
 	int pages;
@@ -255,38 +253,38 @@ int flash_physical_erase(int offset, int size)
 	return EC_SUCCESS;
 }
 
-int flash_physical_get_protect(int bank)
+int crec_flash_physical_get_protect(int bank)
 {
 	/* Not protected */
 	return 0;
 }
 
-uint32_t flash_physical_get_protect_flags(void)
+uint32_t crec_flash_physical_get_protect_flags(void)
 {
 	/* no flags set */
 	return 0;
 }
 
-uint32_t flash_physical_get_valid_flags(void)
+uint32_t crec_flash_physical_get_valid_flags(void)
 {
 	/* These are the flags we're going to pay attention to */
 	return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW |
 	       EC_FLASH_PROTECT_ALL_NOW;
 }
 
-uint32_t flash_physical_get_writable_flags(uint32_t cur_flags)
+uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
 {
 	/* no flags writable */
 	return 0;
 }
 
-int flash_physical_protect_at_boot(uint32_t new_flags)
+int crec_flash_physical_protect_at_boot(uint32_t new_flags)
 {
 	/* nothing to do here */
 	return EC_SUCCESS;
 }
 
-int flash_physical_protect_now(int all)
+int crec_flash_physical_protect_now(int all)
 {
 	/* nothing to do here */
 	return EC_SUCCESS;
@@ -295,7 +293,7 @@ int flash_physical_protect_now(int all)
 /*****************************************************************************/
 /* High-level APIs */
 
-int flash_pre_init(void)
+int crec_flash_pre_init(void)
 {
 	return EC_SUCCESS;
 }
@@ -308,7 +306,7 @@ int flash_pre_init(void)
  * NOTE: This is a DESTRUCTIVE test for the range of flash pages tested
  *       make sure that PAGE_START is beyond your flash code.
  */
-static int command_flash_test1(int argc, char **argv)
+static int command_flash_test1(int argc, const char **argv)
 {
 	int i;
 	uint8_t *ptr;
@@ -330,10 +328,10 @@ static int command_flash_test1(int argc, char **argv)
 		/*
 		 * erase page
 		 */
-		error_status = flash_physical_erase(flash_address,
-						    CONFIG_FLASH_ERASE_SIZE);
+		error_status = crec_flash_physical_erase(
+			flash_address, CONFIG_FLASH_ERASE_SIZE);
 		if (error_status != EC_SUCCESS) {
-			CPRINTS("Error with flash_physical_erase\n");
+			CPRINTS("Error with crec_flash_physical_erase\n");
 			return EC_ERROR_UNKNOWN;
 		}
 
@@ -356,10 +354,10 @@ static int command_flash_test1(int argc, char **argv)
 		for (i = 0; i < BUFFER_SIZE; i++) {
 			buffer[i] = i + page;
 		}
-		error_status = flash_physical_write(flash_address, BUFFER_SIZE,
-						    buffer);
+		error_status = crec_flash_physical_write(flash_address,
+							 BUFFER_SIZE, buffer);
 		if (error_status != EC_SUCCESS) {
-			CPRINTS("Error with flash_physical_write\n");
+			CPRINTS("Error with crec_flash_physical_write\n");
 			return EC_ERROR_UNKNOWN;
 		}
 	}
@@ -389,10 +387,10 @@ static int command_flash_test1(int argc, char **argv)
 	 */
 	for (page = PAGE_START; page <= PAGE_END; page++) {
 		flash_address = page * CONFIG_FLASH_ERASE_SIZE;
-		error_status = flash_physical_erase(flash_address,
-						    CONFIG_FLASH_ERASE_SIZE);
+		error_status = crec_flash_physical_erase(
+			flash_address, CONFIG_FLASH_ERASE_SIZE);
 		if (error_status != EC_SUCCESS) {
-			CPRINTS("Error with flash_physical_erase\n");
+			CPRINTS("Error with crec_flash_physical_erase\n");
 			return EC_ERROR_UNKNOWN;
 		}
 	}
diff --git a/chip/max32660/flc_regs.h b/chip/max32660/flc_regs.h
index a484763c0b..fb7691e759 100644
--- a/chip/max32660/flc_regs.h
+++ b/chip/max32660/flc_regs.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -43,14 +43,14 @@ extern "C" {
  * Structure type to access the FLC Registers.
  */
 typedef struct {
-	__IO uint32_t addr;   /**< <tt>\b 0x00:<\tt> FLC ADDR Register */
+	__IO uint32_t addr; /**< <tt>\b 0x00:<\tt> FLC ADDR Register */
 	__IO uint32_t clkdiv; /**< <tt>\b 0x04:<\tt> FLC CLKDIV Register */
-	__IO uint32_t cn;     /**< <tt>\b 0x08:<\tt> FLC CN Register */
+	__IO uint32_t cn; /**< <tt>\b 0x08:<\tt> FLC CN Register */
 	__R uint32_t rsv_0xc_0x23[6];
 	__IO uint32_t intr; /**< <tt>\b 0x024:<\tt> FLC INTR Register */
 	__R uint32_t rsv_0x28_0x2f[2];
 	__IO uint32_t data[4]; /**< <tt>\b 0x30:<\tt> FLC DATA Register */
-	__O uint32_t acntl;    /**< <tt>\b 0x40:<\tt> FLC ACNTL Register */
+	__O uint32_t acntl; /**< <tt>\b 0x40:<\tt> FLC ACNTL Register */
 } mxc_flc_regs_t;
 
 /* Register offsets for module FLC */
@@ -58,32 +58,32 @@ typedef struct {
  * FLC Peripheral Register Offsets from the FLC Base Peripheral
  * Address.
  */
-#define MXC_R_FLC_ADDR                                                         \
-	((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: <tt>       \
+#define MXC_R_FLC_ADDR                                                   \
+	((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: <tt> \
 				    0x0x000 */
-#define MXC_R_FLC_CLKDIV                                                       \
-	((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: <tt>       \
+#define MXC_R_FLC_CLKDIV                                                 \
+	((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: <tt> \
 				    0x0x004 */
-#define MXC_R_FLC_CN                                                           \
-	((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: <tt>       \
+#define MXC_R_FLC_CN                                                     \
+	((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: <tt> \
 				    0x0x008 */
-#define MXC_R_FLC_INTR                                                         \
-	((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: <tt>       \
+#define MXC_R_FLC_INTR                                                   \
+	((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: <tt> \
 				    0x0x024 */
-#define MXC_R_FLC_DATA                                                         \
-	((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: <tt>       \
+#define MXC_R_FLC_DATA                                                   \
+	((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: <tt> \
 				    0x0x030 */
-#define MXC_R_FLC_ACNTL                                                        \
-	((uint32_t)0x00000040UL) /**< Offset from FLC Base Address: <tt>       \
+#define MXC_R_FLC_ACNTL                                                  \
+	((uint32_t)0x00000040UL) /**< Offset from FLC Base Address: <tt> \
 				    0x0x040 */
 
 /**
  * Flash Write Address.
  */
 #define MXC_F_FLC_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */
-#define MXC_F_FLC_ADDR_ADDR                                                    \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_FLC_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */
+#define MXC_F_FLC_ADDR_ADDR                                                  \
+	((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ADDR_ADDR_POS)) /**< ADDR_ADDR \
+								 Mask */
 
 /**
  * Flash Clock Divide. The clock (PLL0) is divided by this value to
@@ -91,177 +91,200 @@ typedef struct {
  */
 #define MXC_F_FLC_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */
 #define MXC_F_FLC_CLKDIV_CLKDIV                                                \
-	((uint32_t)(                                                           \
-		0xFFUL                                                         \
-		<< MXC_F_FLC_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */
+	((uint32_t)(0xFFUL << MXC_F_FLC_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV \
+							       Mask */
 
 /**
  * Flash Control Register.
  */
 #define MXC_F_FLC_CN_WR_POS 0 /**< CN_WR Position */
-#define MXC_F_FLC_CN_WR                                                        \
+#define MXC_F_FLC_CN_WR \
 	((uint32_t)(0x1UL << MXC_F_FLC_CN_WR_POS)) /**< CN_WR Mask */
-#define MXC_V_FLC_CN_WR_COMPLETE                                               \
-	((uint32_t)0x0UL) /**< CN_WR_COMPLETE Value                            \
+#define MXC_V_FLC_CN_WR_COMPLETE                    \
+	((uint32_t)0x0UL) /**< CN_WR_COMPLETE Value \
 			   */
-#define MXC_S_FLC_CN_WR_COMPLETE                                               \
-	(MXC_V_FLC_CN_WR_COMPLETE                                              \
-	 << MXC_F_FLC_CN_WR_POS)		/**< CN_WR_COMPLETE Setting */
+#define MXC_S_FLC_CN_WR_COMPLETE                                              \
+	(MXC_V_FLC_CN_WR_COMPLETE << MXC_F_FLC_CN_WR_POS) /**< CN_WR_COMPLETE \
+							     Setting */
 #define MXC_V_FLC_CN_WR_START ((uint32_t)0x1UL) /**< CN_WR_START Value */
-#define MXC_S_FLC_CN_WR_START                                                  \
-	(MXC_V_FLC_CN_WR_START                                                 \
-	 << MXC_F_FLC_CN_WR_POS) /**< CN_WR_START Setting */
+#define MXC_S_FLC_CN_WR_START                                           \
+	(MXC_V_FLC_CN_WR_START << MXC_F_FLC_CN_WR_POS) /**< CN_WR_START \
+							  Setting */
 
 #define MXC_F_FLC_CN_ME_POS 1 /**< CN_ME Position */
-#define MXC_F_FLC_CN_ME                                                        \
+#define MXC_F_FLC_CN_ME \
 	((uint32_t)(0x1UL << MXC_F_FLC_CN_ME_POS)) /**< CN_ME Mask */
 
 #define MXC_F_FLC_CN_PGE_POS 2 /**< CN_PGE Position */
-#define MXC_F_FLC_CN_PGE                                                       \
+#define MXC_F_FLC_CN_PGE \
 	((uint32_t)(0x1UL << MXC_F_FLC_CN_PGE_POS)) /**< CN_PGE Mask */
 
 #define MXC_F_FLC_CN_WDTH_POS 4 /**< CN_WDTH Position */
-#define MXC_F_FLC_CN_WDTH                                                      \
+#define MXC_F_FLC_CN_WDTH \
 	((uint32_t)(0x1UL << MXC_F_FLC_CN_WDTH_POS)) /**< CN_WDTH Mask */
-#define MXC_V_FLC_CN_WDTH_SIZE128                                              \
+#define MXC_V_FLC_CN_WDTH_SIZE128 \
 	((uint32_t)0x0UL) /**< CN_WDTH_SIZE128 Value */
-#define MXC_S_FLC_CN_WDTH_SIZE128                                              \
-	(MXC_V_FLC_CN_WDTH_SIZE128                                             \
-	 << MXC_F_FLC_CN_WDTH_POS) /**< CN_WDTH_SIZE128 Setting */
-#define MXC_V_FLC_CN_WDTH_SIZE32                                               \
-	((uint32_t)0x1UL) /**< CN_WDTH_SIZE32 Value                            \
+#define MXC_S_FLC_CN_WDTH_SIZE128                     \
+	(MXC_V_FLC_CN_WDTH_SIZE128                    \
+	 << MXC_F_FLC_CN_WDTH_POS) /**<               \
+				      CN_WDTH_SIZE128 \
+				      Setting */
+#define MXC_V_FLC_CN_WDTH_SIZE32                    \
+	((uint32_t)0x1UL) /**< CN_WDTH_SIZE32 Value \
 			   */
-#define MXC_S_FLC_CN_WDTH_SIZE32                                               \
-	(MXC_V_FLC_CN_WDTH_SIZE32                                              \
-	 << MXC_F_FLC_CN_WDTH_POS) /**< CN_WDTH_SIZE32 Setting */
+#define MXC_S_FLC_CN_WDTH_SIZE32                                              \
+	(MXC_V_FLC_CN_WDTH_SIZE32 << MXC_F_FLC_CN_WDTH_POS) /**<              \
+							       CN_WDTH_SIZE32 \
+							       Setting */
 
 #define MXC_F_FLC_CN_ERASE_CODE_POS 8 /**< CN_ERASE_CODE Position */
 #define MXC_F_FLC_CN_ERASE_CODE                                                \
-	((uint32_t)(                                                           \
-		0xFFUL                                                         \
-		<< MXC_F_FLC_CN_ERASE_CODE_POS)) /**< CN_ERASE_CODE Mask */
-#define MXC_V_FLC_CN_ERASE_CODE_NOP                                            \
+	((uint32_t)(0xFFUL << MXC_F_FLC_CN_ERASE_CODE_POS)) /**< CN_ERASE_CODE \
+							       Mask */
+#define MXC_V_FLC_CN_ERASE_CODE_NOP \
 	((uint32_t)0x0UL) /**< CN_ERASE_CODE_NOP Value */
-#define MXC_S_FLC_CN_ERASE_CODE_NOP                                            \
-	(MXC_V_FLC_CN_ERASE_CODE_NOP                                           \
-	 << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_NOP Setting */
-#define MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE                                      \
+#define MXC_S_FLC_CN_ERASE_CODE_NOP                           \
+	(MXC_V_FLC_CN_ERASE_CODE_NOP                          \
+	 << MXC_F_FLC_CN_ERASE_CODE_POS) /**<                 \
+					    CN_ERASE_CODE_NOP \
+					    Setting           \
+					  */
+#define MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE \
 	((uint32_t)0x55UL) /**< CN_ERASE_CODE_ERASEPAGE Value */
-#define MXC_S_FLC_CN_ERASE_CODE_ERASEPAGE                                      \
-	(MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE                                     \
-	 << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_ERASEPAGE Setting  \
+#define MXC_S_FLC_CN_ERASE_CODE_ERASEPAGE                                     \
+	(MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE                                    \
+	 << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_ERASEPAGE Setting \
 					  */
-#define MXC_V_FLC_CN_ERASE_CODE_ERASEALL                                       \
+#define MXC_V_FLC_CN_ERASE_CODE_ERASEALL \
 	((uint32_t)0xAAUL) /**< CN_ERASE_CODE_ERASEALL Value */
-#define MXC_S_FLC_CN_ERASE_CODE_ERASEALL                                       \
-	(MXC_V_FLC_CN_ERASE_CODE_ERASEALL                                      \
-	 << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_ERASEALL Setting   \
+#define MXC_S_FLC_CN_ERASE_CODE_ERASEALL                                     \
+	(MXC_V_FLC_CN_ERASE_CODE_ERASEALL                                    \
+	 << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_ERASEALL Setting \
 					  */
 
 #define MXC_F_FLC_CN_PEND_POS 24 /**< CN_PEND Position */
-#define MXC_F_FLC_CN_PEND                                                      \
+#define MXC_F_FLC_CN_PEND \
 	((uint32_t)(0x1UL << MXC_F_FLC_CN_PEND_POS)) /**< CN_PEND Mask */
-#define MXC_V_FLC_CN_PEND_IDLE ((uint32_t)0x0UL)     /**< CN_PEND_IDLE Value */
-#define MXC_S_FLC_CN_PEND_IDLE                                                 \
-	(MXC_V_FLC_CN_PEND_IDLE                                                \
-	 << MXC_F_FLC_CN_PEND_POS)		 /**< CN_PEND_IDLE Setting */
+#define MXC_V_FLC_CN_PEND_IDLE ((uint32_t)0x0UL) /**< CN_PEND_IDLE Value */
+#define MXC_S_FLC_CN_PEND_IDLE                                              \
+	(MXC_V_FLC_CN_PEND_IDLE << MXC_F_FLC_CN_PEND_POS) /**< CN_PEND_IDLE \
+							     Setting */
 #define MXC_V_FLC_CN_PEND_BUSY ((uint32_t)0x1UL) /**< CN_PEND_BUSY Value */
-#define MXC_S_FLC_CN_PEND_BUSY                                                 \
-	(MXC_V_FLC_CN_PEND_BUSY                                                \
-	 << MXC_F_FLC_CN_PEND_POS) /**< CN_PEND_BUSY Setting */
+#define MXC_S_FLC_CN_PEND_BUSY                                              \
+	(MXC_V_FLC_CN_PEND_BUSY << MXC_F_FLC_CN_PEND_POS) /**< CN_PEND_BUSY \
+							     Setting */
 
 #define MXC_F_FLC_CN_LVE_POS 25 /**< CN_LVE Position */
-#define MXC_F_FLC_CN_LVE                                                       \
+#define MXC_F_FLC_CN_LVE \
 	((uint32_t)(0x1UL << MXC_F_FLC_CN_LVE_POS)) /**< CN_LVE Mask */
-#define MXC_V_FLC_CN_LVE_DIS ((uint32_t)0x0UL)      /**< CN_LVE_DIS Value */
+#define MXC_V_FLC_CN_LVE_DIS ((uint32_t)0x0UL) /**< CN_LVE_DIS Value */
 #define MXC_S_FLC_CN_LVE_DIS                                                   \
-	(MXC_V_FLC_CN_LVE_DIS                                                  \
-	 << MXC_F_FLC_CN_LVE_POS)	     /**< CN_LVE_DIS Setting */
+	(MXC_V_FLC_CN_LVE_DIS << MXC_F_FLC_CN_LVE_POS) /**< CN_LVE_DIS Setting \
+							*/
 #define MXC_V_FLC_CN_LVE_EN ((uint32_t)0x1UL) /**< CN_LVE_EN Value */
-#define MXC_S_FLC_CN_LVE_EN                                                    \
-	(MXC_V_FLC_CN_LVE_EN << MXC_F_FLC_CN_LVE_POS) /**< CN_LVE_EN Setting   \
+#define MXC_S_FLC_CN_LVE_EN                                                  \
+	(MXC_V_FLC_CN_LVE_EN << MXC_F_FLC_CN_LVE_POS) /**< CN_LVE_EN Setting \
 						       */
 
 #define MXC_F_FLC_CN_BRST_POS 27 /**< CN_BRST Position */
-#define MXC_F_FLC_CN_BRST                                                      \
+#define MXC_F_FLC_CN_BRST \
 	((uint32_t)(0x1UL << MXC_F_FLC_CN_BRST_POS)) /**< CN_BRST Mask */
-#define MXC_V_FLC_CN_BRST_DISABLE                                              \
+#define MXC_V_FLC_CN_BRST_DISABLE \
 	((uint32_t)0x0UL) /**< CN_BRST_DISABLE Value */
-#define MXC_S_FLC_CN_BRST_DISABLE                                              \
-	(MXC_V_FLC_CN_BRST_DISABLE                                             \
-	 << MXC_F_FLC_CN_BRST_POS) /**< CN_BRST_DISABLE Setting */
-#define MXC_V_FLC_CN_BRST_ENABLE                                               \
-	((uint32_t)0x1UL) /**< CN_BRST_ENABLE Value                            \
+#define MXC_S_FLC_CN_BRST_DISABLE                     \
+	(MXC_V_FLC_CN_BRST_DISABLE                    \
+	 << MXC_F_FLC_CN_BRST_POS) /**<               \
+				      CN_BRST_DISABLE \
+				      Setting */
+#define MXC_V_FLC_CN_BRST_ENABLE                    \
+	((uint32_t)0x1UL) /**< CN_BRST_ENABLE Value \
 			   */
-#define MXC_S_FLC_CN_BRST_ENABLE                                               \
-	(MXC_V_FLC_CN_BRST_ENABLE                                              \
-	 << MXC_F_FLC_CN_BRST_POS) /**< CN_BRST_ENABLE Setting */
+#define MXC_S_FLC_CN_BRST_ENABLE                                              \
+	(MXC_V_FLC_CN_BRST_ENABLE << MXC_F_FLC_CN_BRST_POS) /**<              \
+							       CN_BRST_ENABLE \
+							       Setting */
 
 #define MXC_F_FLC_CN_UNLOCK_POS 28 /**< CN_UNLOCK Position */
-#define MXC_F_FLC_CN_UNLOCK                                                    \
+#define MXC_F_FLC_CN_UNLOCK \
 	((uint32_t)(0xFUL << MXC_F_FLC_CN_UNLOCK_POS)) /**< CN_UNLOCK Mask */
-#define MXC_V_FLC_CN_UNLOCK_UNLOCKED                                           \
+#define MXC_V_FLC_CN_UNLOCK_UNLOCKED \
 	((uint32_t)0x2UL) /**< CN_UNLOCK_UNLOCKED Value */
-#define MXC_S_FLC_CN_UNLOCK_UNLOCKED                                           \
-	(MXC_V_FLC_CN_UNLOCK_UNLOCKED                                          \
-	 << MXC_F_FLC_CN_UNLOCK_POS) /**< CN_UNLOCK_UNLOCKED Setting */
+#define MXC_S_FLC_CN_UNLOCK_UNLOCKED                       \
+	(MXC_V_FLC_CN_UNLOCK_UNLOCKED                      \
+	 << MXC_F_FLC_CN_UNLOCK_POS) /**<                  \
+					CN_UNLOCK_UNLOCKED \
+					Setting            \
+				      */
 
 /**
  * Flash Interrupt Register.
  */
 #define MXC_F_FLC_INTR_DONE_POS 0 /**< INTR_DONE Position */
-#define MXC_F_FLC_INTR_DONE                                                    \
+#define MXC_F_FLC_INTR_DONE \
 	((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_POS)) /**< INTR_DONE Mask */
-#define MXC_V_FLC_INTR_DONE_INACTIVE                                           \
+#define MXC_V_FLC_INTR_DONE_INACTIVE \
 	((uint32_t)0x0UL) /**< INTR_DONE_INACTIVE Value */
-#define MXC_S_FLC_INTR_DONE_INACTIVE                                           \
-	(MXC_V_FLC_INTR_DONE_INACTIVE                                          \
-	 << MXC_F_FLC_INTR_DONE_POS) /**< INTR_DONE_INACTIVE Setting */
-#define MXC_V_FLC_INTR_DONE_PENDING                                            \
+#define MXC_S_FLC_INTR_DONE_INACTIVE                       \
+	(MXC_V_FLC_INTR_DONE_INACTIVE                      \
+	 << MXC_F_FLC_INTR_DONE_POS) /**<                  \
+					INTR_DONE_INACTIVE \
+					Setting            \
+				      */
+#define MXC_V_FLC_INTR_DONE_PENDING \
 	((uint32_t)0x1UL) /**< INTR_DONE_PENDING Value */
-#define MXC_S_FLC_INTR_DONE_PENDING                                            \
-	(MXC_V_FLC_INTR_DONE_PENDING                                           \
-	 << MXC_F_FLC_INTR_DONE_POS) /**< INTR_DONE_PENDING Setting */
+#define MXC_S_FLC_INTR_DONE_PENDING                       \
+	(MXC_V_FLC_INTR_DONE_PENDING                      \
+	 << MXC_F_FLC_INTR_DONE_POS) /**<                 \
+					INTR_DONE_PENDING \
+					Setting */
 
 #define MXC_F_FLC_INTR_AF_POS 1 /**< INTR_AF Position */
-#define MXC_F_FLC_INTR_AF                                                      \
+#define MXC_F_FLC_INTR_AF \
 	((uint32_t)(0x1UL << MXC_F_FLC_INTR_AF_POS)) /**< INTR_AF Mask */
-#define MXC_V_FLC_INTR_AF_NOERROR                                              \
+#define MXC_V_FLC_INTR_AF_NOERROR \
 	((uint32_t)0x0UL) /**< INTR_AF_NOERROR Value */
-#define MXC_S_FLC_INTR_AF_NOERROR                                              \
-	(MXC_V_FLC_INTR_AF_NOERROR                                             \
-	 << MXC_F_FLC_INTR_AF_POS) /**< INTR_AF_NOERROR Setting */
+#define MXC_S_FLC_INTR_AF_NOERROR                     \
+	(MXC_V_FLC_INTR_AF_NOERROR                    \
+	 << MXC_F_FLC_INTR_AF_POS) /**<               \
+				      INTR_AF_NOERROR \
+				      Setting */
 #define MXC_V_FLC_INTR_AF_ERROR ((uint32_t)0x1UL) /**< INTR_AF_ERROR Value */
-#define MXC_S_FLC_INTR_AF_ERROR                                                \
-	(MXC_V_FLC_INTR_AF_ERROR                                               \
-	 << MXC_F_FLC_INTR_AF_POS) /**< INTR_AF_ERROR Setting */
+#define MXC_S_FLC_INTR_AF_ERROR                                               \
+	(MXC_V_FLC_INTR_AF_ERROR << MXC_F_FLC_INTR_AF_POS) /**< INTR_AF_ERROR \
+							      Setting */
 
 #define MXC_F_FLC_INTR_DONEIE_POS 8 /**< INTR_DONEIE Position */
 #define MXC_F_FLC_INTR_DONEIE                                                  \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_FLC_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask */
-#define MXC_V_FLC_INTR_DONEIE_DISABLE                                          \
+	((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask \
+							  */
+#define MXC_V_FLC_INTR_DONEIE_DISABLE \
 	((uint32_t)0x0UL) /**< INTR_DONEIE_DISABLE Value */
-#define MXC_S_FLC_INTR_DONEIE_DISABLE                                          \
-	(MXC_V_FLC_INTR_DONEIE_DISABLE                                         \
-	 << MXC_F_FLC_INTR_DONEIE_POS) /**< INTR_DONEIE_DISABLE Setting */
-#define MXC_V_FLC_INTR_DONEIE_ENABLE                                           \
+#define MXC_S_FLC_INTR_DONEIE_DISABLE                         \
+	(MXC_V_FLC_INTR_DONEIE_DISABLE                        \
+	 << MXC_F_FLC_INTR_DONEIE_POS) /**<                   \
+					  INTR_DONEIE_DISABLE \
+					  Setting             \
+					*/
+#define MXC_V_FLC_INTR_DONEIE_ENABLE \
 	((uint32_t)0x1UL) /**< INTR_DONEIE_ENABLE Value */
-#define MXC_S_FLC_INTR_DONEIE_ENABLE                                           \
-	(MXC_V_FLC_INTR_DONEIE_ENABLE                                          \
-	 << MXC_F_FLC_INTR_DONEIE_POS) /**< INTR_DONEIE_ENABLE Setting */
+#define MXC_S_FLC_INTR_DONEIE_ENABLE                         \
+	(MXC_V_FLC_INTR_DONEIE_ENABLE                        \
+	 << MXC_F_FLC_INTR_DONEIE_POS) /**<                  \
+					  INTR_DONEIE_ENABLE \
+					  Setting            \
+					*/
 
 #define MXC_F_FLC_INTR_AFIE_POS 9 /**< INTR_AFIE Position */
-#define MXC_F_FLC_INTR_AFIE                                                    \
+#define MXC_F_FLC_INTR_AFIE \
 	((uint32_t)(0x1UL << MXC_F_FLC_INTR_AFIE_POS)) /**< INTR_AFIE Mask */
 
 /**
  * Flash Write Data.
  */
 #define MXC_F_FLC_DATA_DATA_POS 0 /**< DATA_DATA Position */
-#define MXC_F_FLC_DATA_DATA                                                    \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_FLC_DATA_DATA_POS)) /**< DATA_DATA Mask */
+#define MXC_F_FLC_DATA_DATA                                                  \
+	((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_DATA_DATA_POS)) /**< DATA_DATA \
+								 Mask */
 
 /**
  * Access Control Register. Writing the ACNTL register with the
@@ -273,8 +296,9 @@ typedef struct {
  */
 #define MXC_F_FLC_ACNTL_ACNTL_POS 0 /**< ACNTL_ACNTL Position */
 #define MXC_F_FLC_ACNTL_ACNTL                                                  \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_FLC_ACNTL_ACNTL_POS)) /**< ACNTL_ACNTL Mask */
+	((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ACNTL_ACNTL_POS)) /**<           \
+								   ACNTL_ACNTL \
+								   Mask */
 
 #ifdef __cplusplus
 }
diff --git a/chip/max32660/gcr_regs.h b/chip/max32660/gcr_regs.h
index c9de13812c..bed6cf4550 100644
--- a/chip/max32660/gcr_regs.h
+++ b/chip/max32660/gcr_regs.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -39,118 +39,123 @@
  * Structure type to access the GCR Registers.
  */
 typedef struct {
-	__IO uint32_t scon;  /**< <tt>\b 0x00:<\tt> GCR SCON Register */
+	__IO uint32_t scon; /**< <tt>\b 0x00:<\tt> GCR SCON Register */
 	__IO uint32_t rstr0; /**< <tt>\b 0x04:<\tt> GCR RSTR0 Register */
 	__IO uint32_t clkcn; /**< <tt>\b 0x08:<\tt> GCR CLKCN Register */
-	__IO uint32_t pm;    /**< <tt>\b 0x0C:<\tt> GCR PM Register */
+	__IO uint32_t pm; /**< <tt>\b 0x0C:<\tt> GCR PM Register */
 	__R uint32_t rsv_0x10_0x17[2];
 	__IO uint32_t pckdiv; /**< <tt>\b 0x18:<\tt> GCR PCKDIV Register */
 	__R uint32_t rsv_0x1c_0x23[2];
 	__IO uint32_t perckcn0; /**< <tt>\b 0x24:<\tt> GCR PERCKCN0 Register */
-	__IO uint32_t memckcn;  /**< <tt>\b 0x28:<\tt> GCR MEMCKCN Register */
-	__IO uint32_t memzcn;   /**< <tt>\b 0x2C:<\tt> GCR MEMZCN Register */
+	__IO uint32_t memckcn; /**< <tt>\b 0x28:<\tt> GCR MEMCKCN Register */
+	__IO uint32_t memzcn; /**< <tt>\b 0x2C:<\tt> GCR MEMZCN Register */
 	__R uint32_t rsv_0x30;
-	__IO uint32_t scck;     /**< <tt>\b 0x34:<\tt> GCR SCCK Register */
-	__IO uint32_t mpri0;    /**< <tt>\b 0x38:<\tt> GCR MPRI0 Register */
-	__IO uint32_t mpri1;    /**< <tt>\b 0x3C:<\tt> GCR MPRI1 Register */
-	__IO uint32_t sysst;    /**< <tt>\b 0x40:<\tt> GCR SYSST Register */
-	__IO uint32_t rstr1;    /**< <tt>\b 0x44:<\tt> GCR RSTR1 Register */
+	__IO uint32_t scck; /**< <tt>\b 0x34:<\tt> GCR SCCK Register */
+	__IO uint32_t mpri0; /**< <tt>\b 0x38:<\tt> GCR MPRI0 Register */
+	__IO uint32_t mpri1; /**< <tt>\b 0x3C:<\tt> GCR MPRI1 Register */
+	__IO uint32_t sysst; /**< <tt>\b 0x40:<\tt> GCR SYSST Register */
+	__IO uint32_t rstr1; /**< <tt>\b 0x44:<\tt> GCR RSTR1 Register */
 	__IO uint32_t perckcn1; /**< <tt>\b 0x48:<\tt> GCR PERCKCN1 Register */
-	__IO uint32_t evten;    /**< <tt>\b 0x4C:<\tt> GCR EVTEN Register */
-	__I uint32_t revision;  /**< <tt>\b 0x50:<\tt> GCR REVISION Register */
-	__IO uint32_t syssie;   /**< <tt>\b 0x54:<\tt> GCR SYSSIE Register */
+	__IO uint32_t evten; /**< <tt>\b 0x4C:<\tt> GCR EVTEN Register */
+	__I uint32_t revision; /**< <tt>\b 0x50:<\tt> GCR REVISION Register */
+	__IO uint32_t syssie; /**< <tt>\b 0x54:<\tt> GCR SYSSIE Register */
 } mxc_gcr_regs_t;
 
 /**
  * GCR Peripheral Register Offsets from the GCR Base Peripheral
  * Address.
  */
-#define MXC_R_GCR_SCON                                                         \
-	((uint32_t)0x00000000UL) /**< Offset from GCR Base Address: <tt>       \
+#define MXC_R_GCR_SCON                                                   \
+	((uint32_t)0x00000000UL) /**< Offset from GCR Base Address: <tt> \
 				    0x0x000 */
-#define MXC_R_GCR_RSTR0                                                        \
-	((uint32_t)0x00000004UL) /**< Offset from GCR Base Address: <tt>       \
+#define MXC_R_GCR_RSTR0                                                  \
+	((uint32_t)0x00000004UL) /**< Offset from GCR Base Address: <tt> \
 				    0x0x004 */
-#define MXC_R_GCR_CLKCN                                                        \
-	((uint32_t)0x00000008UL) /**< Offset from GCR Base Address: <tt>       \
+#define MXC_R_GCR_CLKCN                                                  \
+	((uint32_t)0x00000008UL) /**< Offset from GCR Base Address: <tt> \
 				    0x0x008 */
-#define MXC_R_GCR_PM                                                           \
-	((uint32_t)0x0000000CUL) /**< Offset from GCR Base Address: <tt>       \
+#define MXC_R_GCR_PM                                                     \
+	((uint32_t)0x0000000CUL) /**< Offset from GCR Base Address: <tt> \
 				    0x0x00C */
-#define MXC_R_GCR_PCKDIV                                                       \
-	((uint32_t)0x00000018UL) /**< Offset from GCR Base Address: <tt>       \
+#define MXC_R_GCR_PCKDIV                                                 \
+	((uint32_t)0x00000018UL) /**< Offset from GCR Base Address: <tt> \
 				    0x0x018 */
-#define MXC_R_GCR_PERCKCN0                                                     \
-	((uint32_t)0x00000024UL) /**< Offset from GCR Base Address: <tt>       \
+#define MXC_R_GCR_PERCKCN0                                               \
+	((uint32_t)0x00000024UL) /**< Offset from GCR Base Address: <tt> \
 				    0x0x024 */
-#define MXC_R_GCR_MEMCKCN                                                      \
-	((uint32_t)0x00000028UL) /**< Offset from GCR Base Address: <tt>       \
+#define MXC_R_GCR_MEMCKCN                                                \
+	((uint32_t)0x00000028UL) /**< Offset from GCR Base Address: <tt> \
 				    0x0x028 */
-#define MXC_R_GCR_MEMZCN                                                       \
-	((uint32_t)0x0000002CUL) /**< Offset from GCR Base Address: <tt>       \
+#define MXC_R_GCR_MEMZCN                                                 \
+	((uint32_t)0x0000002CUL) /**< Offset from GCR Base Address: <tt> \
 				    0x0x02C */
-#define MXC_R_GCR_SCCK                                                         \
-	((uint32_t)0x00000034UL) /**< Offset from GCR Base Address: <tt>       \
+#define MXC_R_GCR_SCCK                                                   \
+	((uint32_t)0x00000034UL) /**< Offset from GCR Base Address: <tt> \
 				    0x0x034 */
-#define MXC_R_GCR_MPRI0                                                        \
-	((uint32_t)0x00000038UL) /**< Offset from GCR Base Address: <tt>       \
+#define MXC_R_GCR_MPRI0                                                  \
+	((uint32_t)0x00000038UL) /**< Offset from GCR Base Address: <tt> \
 				    0x0x038 */
-#define MXC_R_GCR_MPRI1                                                        \
-	((uint32_t)0x0000003CUL) /**< Offset from GCR Base Address: <tt>       \
+#define MXC_R_GCR_MPRI1                                                  \
+	((uint32_t)0x0000003CUL) /**< Offset from GCR Base Address: <tt> \
 				    0x0x03C */
-#define MXC_R_GCR_SYSST                                                        \
-	((uint32_t)0x00000040UL) /**< Offset from GCR Base Address: <tt>       \
+#define MXC_R_GCR_SYSST                                                  \
+	((uint32_t)0x00000040UL) /**< Offset from GCR Base Address: <tt> \
 				    0x0x040 */
-#define MXC_R_GCR_RSTR1                                                        \
-	((uint32_t)0x00000044UL) /**< Offset from GCR Base Address: <tt>       \
+#define MXC_R_GCR_RSTR1                                                  \
+	((uint32_t)0x00000044UL) /**< Offset from GCR Base Address: <tt> \
 				    0x0x044 */
-#define MXC_R_GCR_PERCKCN1                                                     \
-	((uint32_t)0x00000048UL) /**< Offset from GCR Base Address: <tt>       \
+#define MXC_R_GCR_PERCKCN1                                               \
+	((uint32_t)0x00000048UL) /**< Offset from GCR Base Address: <tt> \
 				    0x0x048 */
-#define MXC_R_GCR_EVTEN                                                        \
-	((uint32_t)0x0000004CUL) /**< Offset from GCR Base Address: <tt>       \
+#define MXC_R_GCR_EVTEN                                                  \
+	((uint32_t)0x0000004CUL) /**< Offset from GCR Base Address: <tt> \
 				    0x0x04C */
-#define MXC_R_GCR_REVISION                                                     \
-	((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: <tt>       \
+#define MXC_R_GCR_REVISION                                               \
+	((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: <tt> \
 				    0x0x050 */
-#define MXC_R_GCR_SYSSIE                                                       \
-	((uint32_t)0x00000054UL) /**< Offset from GCR Base Address: <tt>       \
+#define MXC_R_GCR_SYSSIE                                                 \
+	((uint32_t)0x00000054UL) /**< Offset from GCR Base Address: <tt> \
 				    0x0x054 */
 
 /**
  * System Control.
  */
 #define MXC_F_GCR_SCON_SBUSARB_POS 1 /**< SCON_SBUSARB Position */
-#define MXC_F_GCR_SCON_SBUSARB                                                 \
-	((uint32_t)(0x3UL                                                      \
-		    << MXC_F_GCR_SCON_SBUSARB_POS)) /**< SCON_SBUSARB Mask */
-#define MXC_V_GCR_SCON_SBUSARB_FIX                                             \
+#define MXC_F_GCR_SCON_SBUSARB                                              \
+	((uint32_t)(0x3UL << MXC_F_GCR_SCON_SBUSARB_POS)) /**< SCON_SBUSARB \
+							     Mask */
+#define MXC_V_GCR_SCON_SBUSARB_FIX \
 	((uint32_t)0x0UL) /**< SCON_SBUSARB_FIX Value */
-#define MXC_S_GCR_SCON_SBUSARB_FIX                                             \
-	(MXC_V_GCR_SCON_SBUSARB_FIX                                            \
-	 << MXC_F_GCR_SCON_SBUSARB_POS) /**< SCON_SBUSARB_FIX Setting */
-#define MXC_V_GCR_SCON_SBUSARB_ROUND                                           \
+#define MXC_S_GCR_SCON_SBUSARB_FIX                          \
+	(MXC_V_GCR_SCON_SBUSARB_FIX                         \
+	 << MXC_F_GCR_SCON_SBUSARB_POS) /**<                \
+					   SCON_SBUSARB_FIX \
+					   Setting          \
+					 */
+#define MXC_V_GCR_SCON_SBUSARB_ROUND \
 	((uint32_t)0x1UL) /**< SCON_SBUSARB_ROUND Value */
-#define MXC_S_GCR_SCON_SBUSARB_ROUND                                           \
-	(MXC_V_GCR_SCON_SBUSARB_ROUND                                          \
-	 << MXC_F_GCR_SCON_SBUSARB_POS) /**< SCON_SBUSARB_ROUND Setting */
+#define MXC_S_GCR_SCON_SBUSARB_ROUND                          \
+	(MXC_V_GCR_SCON_SBUSARB_ROUND                         \
+	 << MXC_F_GCR_SCON_SBUSARB_POS) /**<                  \
+					   SCON_SBUSARB_ROUND \
+					   Setting            \
+					 */
 
-#define MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS                                     \
+#define MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS \
 	4 /**< SCON_FLASH_PAGE_FLIP Position */
-#define MXC_F_GCR_SCON_FLASH_PAGE_FLIP                                          \
-	((uint32_t)(                                                            \
-		0x1UL                                                           \
-		<< MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS)) /**<                    \
-							   SCON_FLASH_PAGE_FLIP \
-							   Mask */
-#define MXC_V_GCR_SCON_FLASH_PAGE_FLIP_NORMAL                                  \
+#define MXC_F_GCR_SCON_FLASH_PAGE_FLIP                                              \
+	((uint32_t)(0x1UL                                                           \
+		    << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS)) /**<                    \
+							       SCON_FLASH_PAGE_FLIP \
+							       Mask */
+#define MXC_V_GCR_SCON_FLASH_PAGE_FLIP_NORMAL \
 	((uint32_t)0x0UL) /**< SCON_FLASH_PAGE_FLIP_NORMAL Value */
 #define MXC_S_GCR_SCON_FLASH_PAGE_FLIP_NORMAL                                  \
 	(MXC_V_GCR_SCON_FLASH_PAGE_FLIP_NORMAL                                 \
 	 << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS) /**<                           \
 						   SCON_FLASH_PAGE_FLIP_NORMAL \
 						   Setting */
-#define MXC_V_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED                                 \
+#define MXC_V_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED \
 	((uint32_t)0x1UL) /**< SCON_FLASH_PAGE_FLIP_SWAPPED Value */
 #define MXC_S_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED                                  \
 	(MXC_V_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED                                 \
@@ -159,1053 +164,1360 @@ typedef struct {
 						   Setting */
 
 #define MXC_F_GCR_SCON_FPU_DIS_POS 5 /**< SCON_FPU_DIS Position */
-#define MXC_F_GCR_SCON_FPU_DIS                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_SCON_FPU_DIS_POS)) /**< SCON_FPU_DIS Mask */
-#define MXC_V_GCR_SCON_FPU_DIS_ENABLE                                          \
+#define MXC_F_GCR_SCON_FPU_DIS                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_SCON_FPU_DIS_POS)) /**< SCON_FPU_DIS \
+							     Mask */
+#define MXC_V_GCR_SCON_FPU_DIS_ENABLE \
 	((uint32_t)0x0UL) /**< SCON_FPU_DIS_ENABLE Value */
-#define MXC_S_GCR_SCON_FPU_DIS_ENABLE                                          \
-	(MXC_V_GCR_SCON_FPU_DIS_ENABLE                                         \
-	 << MXC_F_GCR_SCON_FPU_DIS_POS) /**< SCON_FPU_DIS_ENABLE Setting */
-#define MXC_V_GCR_SCON_FPU_DIS_DISABLE                                         \
+#define MXC_S_GCR_SCON_FPU_DIS_ENABLE                          \
+	(MXC_V_GCR_SCON_FPU_DIS_ENABLE                         \
+	 << MXC_F_GCR_SCON_FPU_DIS_POS) /**<                   \
+					   SCON_FPU_DIS_ENABLE \
+					   Setting             \
+					 */
+#define MXC_V_GCR_SCON_FPU_DIS_DISABLE \
 	((uint32_t)0x1UL) /**< SCON_FPU_DIS_DISABLE Value */
-#define MXC_S_GCR_SCON_FPU_DIS_DISABLE                                         \
-	(MXC_V_GCR_SCON_FPU_DIS_DISABLE                                        \
-	 << MXC_F_GCR_SCON_FPU_DIS_POS) /**< SCON_FPU_DIS_DISABLE Setting */
+#define MXC_S_GCR_SCON_FPU_DIS_DISABLE                          \
+	(MXC_V_GCR_SCON_FPU_DIS_DISABLE                         \
+	 << MXC_F_GCR_SCON_FPU_DIS_POS) /**<                    \
+					   SCON_FPU_DIS_DISABLE \
+					   Setting              \
+					 */
 
 #define MXC_F_GCR_SCON_CCACHE_FLUSH_POS 6 /**< SCON_CCACHE_FLUSH Position */
-#define MXC_F_GCR_SCON_CCACHE_FLUSH                                            \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_SCON_CCACHE_FLUSH_POS)) /**< SCON_CCACHE_FLUSH    \
-							Mask */
-#define MXC_V_GCR_SCON_CCACHE_FLUSH_NORMAL                                     \
+#define MXC_F_GCR_SCON_CCACHE_FLUSH                                           \
+	((uint32_t)(0x1UL                                                     \
+		    << MXC_F_GCR_SCON_CCACHE_FLUSH_POS)) /**<                 \
+							    SCON_CCACHE_FLUSH \
+							    Mask */
+#define MXC_V_GCR_SCON_CCACHE_FLUSH_NORMAL \
 	((uint32_t)0x0UL) /**< SCON_CCACHE_FLUSH_NORMAL Value */
-#define MXC_S_GCR_SCON_CCACHE_FLUSH_NORMAL                                     \
-	(MXC_V_GCR_SCON_CCACHE_FLUSH_NORMAL                                    \
-	 << MXC_F_GCR_SCON_CCACHE_FLUSH_POS) /**< SCON_CCACHE_FLUSH_NORMAL     \
+#define MXC_S_GCR_SCON_CCACHE_FLUSH_NORMAL                                 \
+	(MXC_V_GCR_SCON_CCACHE_FLUSH_NORMAL                                \
+	 << MXC_F_GCR_SCON_CCACHE_FLUSH_POS) /**< SCON_CCACHE_FLUSH_NORMAL \
 						Setting */
-#define MXC_V_GCR_SCON_CCACHE_FLUSH_FLUSH                                      \
+#define MXC_V_GCR_SCON_CCACHE_FLUSH_FLUSH \
 	((uint32_t)0x1UL) /**< SCON_CCACHE_FLUSH_FLUSH Value */
-#define MXC_S_GCR_SCON_CCACHE_FLUSH_FLUSH                                      \
-	(MXC_V_GCR_SCON_CCACHE_FLUSH_FLUSH                                     \
-	 << MXC_F_GCR_SCON_CCACHE_FLUSH_POS) /**< SCON_CCACHE_FLUSH_FLUSH      \
+#define MXC_S_GCR_SCON_CCACHE_FLUSH_FLUSH                                 \
+	(MXC_V_GCR_SCON_CCACHE_FLUSH_FLUSH                                \
+	 << MXC_F_GCR_SCON_CCACHE_FLUSH_POS) /**< SCON_CCACHE_FLUSH_FLUSH \
 						Setting */
 
 #define MXC_F_GCR_SCON_SWD_DIS_POS 14 /**< SCON_SWD_DIS Position */
-#define MXC_F_GCR_SCON_SWD_DIS                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_SCON_SWD_DIS_POS)) /**< SCON_SWD_DIS Mask */
-#define MXC_V_GCR_SCON_SWD_DIS_ENABLE                                          \
+#define MXC_F_GCR_SCON_SWD_DIS                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_SCON_SWD_DIS_POS)) /**< SCON_SWD_DIS \
+							     Mask */
+#define MXC_V_GCR_SCON_SWD_DIS_ENABLE \
 	((uint32_t)0x0UL) /**< SCON_SWD_DIS_ENABLE Value */
-#define MXC_S_GCR_SCON_SWD_DIS_ENABLE                                          \
-	(MXC_V_GCR_SCON_SWD_DIS_ENABLE                                         \
-	 << MXC_F_GCR_SCON_SWD_DIS_POS) /**< SCON_SWD_DIS_ENABLE Setting */
-#define MXC_V_GCR_SCON_SWD_DIS_DISABLE                                         \
+#define MXC_S_GCR_SCON_SWD_DIS_ENABLE                          \
+	(MXC_V_GCR_SCON_SWD_DIS_ENABLE                         \
+	 << MXC_F_GCR_SCON_SWD_DIS_POS) /**<                   \
+					   SCON_SWD_DIS_ENABLE \
+					   Setting             \
+					 */
+#define MXC_V_GCR_SCON_SWD_DIS_DISABLE \
 	((uint32_t)0x1UL) /**< SCON_SWD_DIS_DISABLE Value */
-#define MXC_S_GCR_SCON_SWD_DIS_DISABLE                                         \
-	(MXC_V_GCR_SCON_SWD_DIS_DISABLE                                        \
-	 << MXC_F_GCR_SCON_SWD_DIS_POS) /**< SCON_SWD_DIS_DISABLE Setting */
+#define MXC_S_GCR_SCON_SWD_DIS_DISABLE                          \
+	(MXC_V_GCR_SCON_SWD_DIS_DISABLE                         \
+	 << MXC_F_GCR_SCON_SWD_DIS_POS) /**<                    \
+					   SCON_SWD_DIS_DISABLE \
+					   Setting              \
+					 */
 
 /**
  * Reset Register 0.
  */
 #define MXC_F_GCR_RSTR0_DMA_POS 0 /**< RSTR0_DMA Position */
-#define MXC_F_GCR_RSTR0_DMA                                                    \
+#define MXC_F_GCR_RSTR0_DMA \
 	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_DMA_POS)) /**< RSTR0_DMA Mask */
 #define MXC_V_GCR_RSTR0_DMA_RFU ((uint32_t)0x0UL) /**< RSTR0_DMA_RFU Value */
-#define MXC_S_GCR_RSTR0_DMA_RFU                                                \
-	(MXC_V_GCR_RSTR0_DMA_RFU                                               \
-	 << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_RFU Setting */
-#define MXC_V_GCR_RSTR0_DMA_RESET                                              \
+#define MXC_S_GCR_RSTR0_DMA_RFU                                               \
+	(MXC_V_GCR_RSTR0_DMA_RFU << MXC_F_GCR_RSTR0_DMA_POS) /**<             \
+								RSTR0_DMA_RFU \
+								Setting */
+#define MXC_V_GCR_RSTR0_DMA_RESET \
 	((uint32_t)0x1UL) /**< RSTR0_DMA_RESET Value */
-#define MXC_S_GCR_RSTR0_DMA_RESET                                              \
-	(MXC_V_GCR_RSTR0_DMA_RESET                                             \
-	 << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_RESET Setting */
-#define MXC_V_GCR_RSTR0_DMA_RESET_DONE                                         \
+#define MXC_S_GCR_RSTR0_DMA_RESET                       \
+	(MXC_V_GCR_RSTR0_DMA_RESET                      \
+	 << MXC_F_GCR_RSTR0_DMA_POS) /**<               \
+					RSTR0_DMA_RESET \
+					Setting */
+#define MXC_V_GCR_RSTR0_DMA_RESET_DONE \
 	((uint32_t)0x0UL) /**< RSTR0_DMA_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_DMA_RESET_DONE                                         \
-	(MXC_V_GCR_RSTR0_DMA_RESET_DONE                                        \
-	 << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_DMA_BUSY                                               \
-	((uint32_t)0x1UL) /**< RSTR0_DMA_BUSY Value                            \
+#define MXC_S_GCR_RSTR0_DMA_RESET_DONE                       \
+	(MXC_V_GCR_RSTR0_DMA_RESET_DONE                      \
+	 << MXC_F_GCR_RSTR0_DMA_POS) /**<                    \
+					RSTR0_DMA_RESET_DONE \
+					Setting              \
+				      */
+#define MXC_V_GCR_RSTR0_DMA_BUSY                    \
+	((uint32_t)0x1UL) /**< RSTR0_DMA_BUSY Value \
 			   */
-#define MXC_S_GCR_RSTR0_DMA_BUSY                                               \
-	(MXC_V_GCR_RSTR0_DMA_BUSY                                              \
-	 << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_BUSY Setting */
+#define MXC_S_GCR_RSTR0_DMA_BUSY                       \
+	(MXC_V_GCR_RSTR0_DMA_BUSY                      \
+	 << MXC_F_GCR_RSTR0_DMA_POS) /**<              \
+					RSTR0_DMA_BUSY \
+					Setting */
 
 #define MXC_F_GCR_RSTR0_WDT_POS 1 /**< RSTR0_WDT Position */
-#define MXC_F_GCR_RSTR0_WDT                                                    \
+#define MXC_F_GCR_RSTR0_WDT \
 	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_WDT_POS)) /**< RSTR0_WDT Mask */
 #define MXC_V_GCR_RSTR0_WDT_RFU ((uint32_t)0x0UL) /**< RSTR0_WDT_RFU Value */
-#define MXC_S_GCR_RSTR0_WDT_RFU                                                \
-	(MXC_V_GCR_RSTR0_WDT_RFU                                               \
-	 << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_RFU Setting */
-#define MXC_V_GCR_RSTR0_WDT_RESET                                              \
+#define MXC_S_GCR_RSTR0_WDT_RFU                                               \
+	(MXC_V_GCR_RSTR0_WDT_RFU << MXC_F_GCR_RSTR0_WDT_POS) /**<             \
+								RSTR0_WDT_RFU \
+								Setting */
+#define MXC_V_GCR_RSTR0_WDT_RESET \
 	((uint32_t)0x1UL) /**< RSTR0_WDT_RESET Value */
-#define MXC_S_GCR_RSTR0_WDT_RESET                                              \
-	(MXC_V_GCR_RSTR0_WDT_RESET                                             \
-	 << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_RESET Setting */
-#define MXC_V_GCR_RSTR0_WDT_RESET_DONE                                         \
+#define MXC_S_GCR_RSTR0_WDT_RESET                       \
+	(MXC_V_GCR_RSTR0_WDT_RESET                      \
+	 << MXC_F_GCR_RSTR0_WDT_POS) /**<               \
+					RSTR0_WDT_RESET \
+					Setting */
+#define MXC_V_GCR_RSTR0_WDT_RESET_DONE \
 	((uint32_t)0x0UL) /**< RSTR0_WDT_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_WDT_RESET_DONE                                         \
-	(MXC_V_GCR_RSTR0_WDT_RESET_DONE                                        \
-	 << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_WDT_BUSY                                               \
-	((uint32_t)0x1UL) /**< RSTR0_WDT_BUSY Value                            \
+#define MXC_S_GCR_RSTR0_WDT_RESET_DONE                       \
+	(MXC_V_GCR_RSTR0_WDT_RESET_DONE                      \
+	 << MXC_F_GCR_RSTR0_WDT_POS) /**<                    \
+					RSTR0_WDT_RESET_DONE \
+					Setting              \
+				      */
+#define MXC_V_GCR_RSTR0_WDT_BUSY                    \
+	((uint32_t)0x1UL) /**< RSTR0_WDT_BUSY Value \
 			   */
-#define MXC_S_GCR_RSTR0_WDT_BUSY                                               \
-	(MXC_V_GCR_RSTR0_WDT_BUSY                                              \
-	 << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_BUSY Setting */
+#define MXC_S_GCR_RSTR0_WDT_BUSY                       \
+	(MXC_V_GCR_RSTR0_WDT_BUSY                      \
+	 << MXC_F_GCR_RSTR0_WDT_POS) /**<              \
+					RSTR0_WDT_BUSY \
+					Setting */
 
 #define MXC_F_GCR_RSTR0_GPIO0_POS 2 /**< RSTR0_GPIO0 Position */
 #define MXC_F_GCR_RSTR0_GPIO0                                                  \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_GCR_RSTR0_GPIO0_POS)) /**< RSTR0_GPIO0 Mask */
-#define MXC_V_GCR_RSTR0_GPIO0_RFU                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_GPIO0_POS)) /**< RSTR0_GPIO0 Mask \
+							  */
+#define MXC_V_GCR_RSTR0_GPIO0_RFU \
 	((uint32_t)0x0UL) /**< RSTR0_GPIO0_RFU Value */
-#define MXC_S_GCR_RSTR0_GPIO0_RFU                                              \
-	(MXC_V_GCR_RSTR0_GPIO0_RFU                                             \
-	 << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_RFU Setting */
-#define MXC_V_GCR_RSTR0_GPIO0_RESET                                            \
+#define MXC_S_GCR_RSTR0_GPIO0_RFU                         \
+	(MXC_V_GCR_RSTR0_GPIO0_RFU                        \
+	 << MXC_F_GCR_RSTR0_GPIO0_POS) /**<               \
+					  RSTR0_GPIO0_RFU \
+					  Setting */
+#define MXC_V_GCR_RSTR0_GPIO0_RESET \
 	((uint32_t)0x1UL) /**< RSTR0_GPIO0_RESET Value */
-#define MXC_S_GCR_RSTR0_GPIO0_RESET                                            \
-	(MXC_V_GCR_RSTR0_GPIO0_RESET                                           \
-	 << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_RESET Setting */
-#define MXC_V_GCR_RSTR0_GPIO0_RESET_DONE                                       \
+#define MXC_S_GCR_RSTR0_GPIO0_RESET                         \
+	(MXC_V_GCR_RSTR0_GPIO0_RESET                        \
+	 << MXC_F_GCR_RSTR0_GPIO0_POS) /**<                 \
+					  RSTR0_GPIO0_RESET \
+					  Setting           \
+					*/
+#define MXC_V_GCR_RSTR0_GPIO0_RESET_DONE \
 	((uint32_t)0x0UL) /**< RSTR0_GPIO0_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_GPIO0_RESET_DONE                                       \
-	(MXC_V_GCR_RSTR0_GPIO0_RESET_DONE                                      \
-	 << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_GPIO0_BUSY                                             \
+#define MXC_S_GCR_RSTR0_GPIO0_RESET_DONE                         \
+	(MXC_V_GCR_RSTR0_GPIO0_RESET_DONE                        \
+	 << MXC_F_GCR_RSTR0_GPIO0_POS) /**<                      \
+					  RSTR0_GPIO0_RESET_DONE \
+					  Setting                \
+					*/
+#define MXC_V_GCR_RSTR0_GPIO0_BUSY \
 	((uint32_t)0x1UL) /**< RSTR0_GPIO0_BUSY Value */
-#define MXC_S_GCR_RSTR0_GPIO0_BUSY                                             \
-	(MXC_V_GCR_RSTR0_GPIO0_BUSY                                            \
-	 << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_BUSY Setting */
+#define MXC_S_GCR_RSTR0_GPIO0_BUSY                         \
+	(MXC_V_GCR_RSTR0_GPIO0_BUSY                        \
+	 << MXC_F_GCR_RSTR0_GPIO0_POS) /**<                \
+					  RSTR0_GPIO0_BUSY \
+					  Setting          \
+					*/
 
 #define MXC_F_GCR_RSTR0_TIMER0_POS 5 /**< RSTR0_TIMER0 Position */
-#define MXC_F_GCR_RSTR0_TIMER0                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_RSTR0_TIMER0_POS)) /**< RSTR0_TIMER0 Mask */
-#define MXC_V_GCR_RSTR0_TIMER0_RFU                                             \
+#define MXC_F_GCR_RSTR0_TIMER0                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER0_POS)) /**< RSTR0_TIMER0 \
+							     Mask */
+#define MXC_V_GCR_RSTR0_TIMER0_RFU \
 	((uint32_t)0x0UL) /**< RSTR0_TIMER0_RFU Value */
-#define MXC_S_GCR_RSTR0_TIMER0_RFU                                             \
-	(MXC_V_GCR_RSTR0_TIMER0_RFU                                            \
-	 << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_RFU Setting */
-#define MXC_V_GCR_RSTR0_TIMER0_RESET                                           \
+#define MXC_S_GCR_RSTR0_TIMER0_RFU                          \
+	(MXC_V_GCR_RSTR0_TIMER0_RFU                         \
+	 << MXC_F_GCR_RSTR0_TIMER0_POS) /**<                \
+					   RSTR0_TIMER0_RFU \
+					   Setting          \
+					 */
+#define MXC_V_GCR_RSTR0_TIMER0_RESET \
 	((uint32_t)0x1UL) /**< RSTR0_TIMER0_RESET Value */
-#define MXC_S_GCR_RSTR0_TIMER0_RESET                                           \
-	(MXC_V_GCR_RSTR0_TIMER0_RESET                                          \
-	 << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_RESET Setting */
-#define MXC_V_GCR_RSTR0_TIMER0_RESET_DONE                                      \
+#define MXC_S_GCR_RSTR0_TIMER0_RESET                          \
+	(MXC_V_GCR_RSTR0_TIMER0_RESET                         \
+	 << MXC_F_GCR_RSTR0_TIMER0_POS) /**<                  \
+					   RSTR0_TIMER0_RESET \
+					   Setting            \
+					 */
+#define MXC_V_GCR_RSTR0_TIMER0_RESET_DONE \
 	((uint32_t)0x0UL) /**< RSTR0_TIMER0_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_TIMER0_RESET_DONE                                      \
-	(MXC_V_GCR_RSTR0_TIMER0_RESET_DONE                                     \
-	 << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_RESET_DONE Setting   \
+#define MXC_S_GCR_RSTR0_TIMER0_RESET_DONE                                    \
+	(MXC_V_GCR_RSTR0_TIMER0_RESET_DONE                                   \
+	 << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_RESET_DONE Setting \
 					 */
-#define MXC_V_GCR_RSTR0_TIMER0_BUSY                                            \
+#define MXC_V_GCR_RSTR0_TIMER0_BUSY \
 	((uint32_t)0x1UL) /**< RSTR0_TIMER0_BUSY Value */
-#define MXC_S_GCR_RSTR0_TIMER0_BUSY                                            \
-	(MXC_V_GCR_RSTR0_TIMER0_BUSY                                           \
-	 << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_BUSY Setting */
+#define MXC_S_GCR_RSTR0_TIMER0_BUSY                          \
+	(MXC_V_GCR_RSTR0_TIMER0_BUSY                         \
+	 << MXC_F_GCR_RSTR0_TIMER0_POS) /**<                 \
+					   RSTR0_TIMER0_BUSY \
+					   Setting           \
+					 */
 
 #define MXC_F_GCR_RSTR0_TIMER1_POS 6 /**< RSTR0_TIMER1 Position */
-#define MXC_F_GCR_RSTR0_TIMER1                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_RSTR0_TIMER1_POS)) /**< RSTR0_TIMER1 Mask */
-#define MXC_V_GCR_RSTR0_TIMER1_RFU                                             \
+#define MXC_F_GCR_RSTR0_TIMER1                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER1_POS)) /**< RSTR0_TIMER1 \
+							     Mask */
+#define MXC_V_GCR_RSTR0_TIMER1_RFU \
 	((uint32_t)0x0UL) /**< RSTR0_TIMER1_RFU Value */
-#define MXC_S_GCR_RSTR0_TIMER1_RFU                                             \
-	(MXC_V_GCR_RSTR0_TIMER1_RFU                                            \
-	 << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_RFU Setting */
-#define MXC_V_GCR_RSTR0_TIMER1_RESET                                           \
+#define MXC_S_GCR_RSTR0_TIMER1_RFU                          \
+	(MXC_V_GCR_RSTR0_TIMER1_RFU                         \
+	 << MXC_F_GCR_RSTR0_TIMER1_POS) /**<                \
+					   RSTR0_TIMER1_RFU \
+					   Setting          \
+					 */
+#define MXC_V_GCR_RSTR0_TIMER1_RESET \
 	((uint32_t)0x1UL) /**< RSTR0_TIMER1_RESET Value */
-#define MXC_S_GCR_RSTR0_TIMER1_RESET                                           \
-	(MXC_V_GCR_RSTR0_TIMER1_RESET                                          \
-	 << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_RESET Setting */
-#define MXC_V_GCR_RSTR0_TIMER1_RESET_DONE                                      \
+#define MXC_S_GCR_RSTR0_TIMER1_RESET                          \
+	(MXC_V_GCR_RSTR0_TIMER1_RESET                         \
+	 << MXC_F_GCR_RSTR0_TIMER1_POS) /**<                  \
+					   RSTR0_TIMER1_RESET \
+					   Setting            \
+					 */
+#define MXC_V_GCR_RSTR0_TIMER1_RESET_DONE \
 	((uint32_t)0x0UL) /**< RSTR0_TIMER1_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_TIMER1_RESET_DONE                                      \
-	(MXC_V_GCR_RSTR0_TIMER1_RESET_DONE                                     \
-	 << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_RESET_DONE Setting   \
+#define MXC_S_GCR_RSTR0_TIMER1_RESET_DONE                                    \
+	(MXC_V_GCR_RSTR0_TIMER1_RESET_DONE                                   \
+	 << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_RESET_DONE Setting \
 					 */
-#define MXC_V_GCR_RSTR0_TIMER1_BUSY                                            \
+#define MXC_V_GCR_RSTR0_TIMER1_BUSY \
 	((uint32_t)0x1UL) /**< RSTR0_TIMER1_BUSY Value */
-#define MXC_S_GCR_RSTR0_TIMER1_BUSY                                            \
-	(MXC_V_GCR_RSTR0_TIMER1_BUSY                                           \
-	 << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_BUSY Setting */
+#define MXC_S_GCR_RSTR0_TIMER1_BUSY                          \
+	(MXC_V_GCR_RSTR0_TIMER1_BUSY                         \
+	 << MXC_F_GCR_RSTR0_TIMER1_POS) /**<                 \
+					   RSTR0_TIMER1_BUSY \
+					   Setting           \
+					 */
 
 #define MXC_F_GCR_RSTR0_TIMER2_POS 7 /**< RSTR0_TIMER2 Position */
-#define MXC_F_GCR_RSTR0_TIMER2                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_RSTR0_TIMER2_POS)) /**< RSTR0_TIMER2 Mask */
-#define MXC_V_GCR_RSTR0_TIMER2_RFU                                             \
+#define MXC_F_GCR_RSTR0_TIMER2                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER2_POS)) /**< RSTR0_TIMER2 \
+							     Mask */
+#define MXC_V_GCR_RSTR0_TIMER2_RFU \
 	((uint32_t)0x0UL) /**< RSTR0_TIMER2_RFU Value */
-#define MXC_S_GCR_RSTR0_TIMER2_RFU                                             \
-	(MXC_V_GCR_RSTR0_TIMER2_RFU                                            \
-	 << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_RFU Setting */
-#define MXC_V_GCR_RSTR0_TIMER2_RESET                                           \
+#define MXC_S_GCR_RSTR0_TIMER2_RFU                          \
+	(MXC_V_GCR_RSTR0_TIMER2_RFU                         \
+	 << MXC_F_GCR_RSTR0_TIMER2_POS) /**<                \
+					   RSTR0_TIMER2_RFU \
+					   Setting          \
+					 */
+#define MXC_V_GCR_RSTR0_TIMER2_RESET \
 	((uint32_t)0x1UL) /**< RSTR0_TIMER2_RESET Value */
-#define MXC_S_GCR_RSTR0_TIMER2_RESET                                           \
-	(MXC_V_GCR_RSTR0_TIMER2_RESET                                          \
-	 << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_RESET Setting */
-#define MXC_V_GCR_RSTR0_TIMER2_RESET_DONE                                      \
+#define MXC_S_GCR_RSTR0_TIMER2_RESET                          \
+	(MXC_V_GCR_RSTR0_TIMER2_RESET                         \
+	 << MXC_F_GCR_RSTR0_TIMER2_POS) /**<                  \
+					   RSTR0_TIMER2_RESET \
+					   Setting            \
+					 */
+#define MXC_V_GCR_RSTR0_TIMER2_RESET_DONE \
 	((uint32_t)0x0UL) /**< RSTR0_TIMER2_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_TIMER2_RESET_DONE                                      \
-	(MXC_V_GCR_RSTR0_TIMER2_RESET_DONE                                     \
-	 << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_RESET_DONE Setting   \
+#define MXC_S_GCR_RSTR0_TIMER2_RESET_DONE                                    \
+	(MXC_V_GCR_RSTR0_TIMER2_RESET_DONE                                   \
+	 << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_RESET_DONE Setting \
 					 */
-#define MXC_V_GCR_RSTR0_TIMER2_BUSY                                            \
+#define MXC_V_GCR_RSTR0_TIMER2_BUSY \
 	((uint32_t)0x1UL) /**< RSTR0_TIMER2_BUSY Value */
-#define MXC_S_GCR_RSTR0_TIMER2_BUSY                                            \
-	(MXC_V_GCR_RSTR0_TIMER2_BUSY                                           \
-	 << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_BUSY Setting */
+#define MXC_S_GCR_RSTR0_TIMER2_BUSY                          \
+	(MXC_V_GCR_RSTR0_TIMER2_BUSY                         \
+	 << MXC_F_GCR_RSTR0_TIMER2_POS) /**<                 \
+					   RSTR0_TIMER2_BUSY \
+					   Setting           \
+					 */
 
 #define MXC_F_GCR_RSTR0_UART0_POS 11 /**< RSTR0_UART0 Position */
 #define MXC_F_GCR_RSTR0_UART0                                                  \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_GCR_RSTR0_UART0_POS)) /**< RSTR0_UART0 Mask */
-#define MXC_V_GCR_RSTR0_UART0_RFU                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_UART0_POS)) /**< RSTR0_UART0 Mask \
+							  */
+#define MXC_V_GCR_RSTR0_UART0_RFU \
 	((uint32_t)0x0UL) /**< RSTR0_UART0_RFU Value */
-#define MXC_S_GCR_RSTR0_UART0_RFU                                              \
-	(MXC_V_GCR_RSTR0_UART0_RFU                                             \
-	 << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_RFU Setting */
-#define MXC_V_GCR_RSTR0_UART0_RESET                                            \
+#define MXC_S_GCR_RSTR0_UART0_RFU                         \
+	(MXC_V_GCR_RSTR0_UART0_RFU                        \
+	 << MXC_F_GCR_RSTR0_UART0_POS) /**<               \
+					  RSTR0_UART0_RFU \
+					  Setting */
+#define MXC_V_GCR_RSTR0_UART0_RESET \
 	((uint32_t)0x1UL) /**< RSTR0_UART0_RESET Value */
-#define MXC_S_GCR_RSTR0_UART0_RESET                                            \
-	(MXC_V_GCR_RSTR0_UART0_RESET                                           \
-	 << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_RESET Setting */
-#define MXC_V_GCR_RSTR0_UART0_RESET_DONE                                       \
+#define MXC_S_GCR_RSTR0_UART0_RESET                         \
+	(MXC_V_GCR_RSTR0_UART0_RESET                        \
+	 << MXC_F_GCR_RSTR0_UART0_POS) /**<                 \
+					  RSTR0_UART0_RESET \
+					  Setting           \
+					*/
+#define MXC_V_GCR_RSTR0_UART0_RESET_DONE \
 	((uint32_t)0x0UL) /**< RSTR0_UART0_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_UART0_RESET_DONE                                       \
-	(MXC_V_GCR_RSTR0_UART0_RESET_DONE                                      \
-	 << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_UART0_BUSY                                             \
+#define MXC_S_GCR_RSTR0_UART0_RESET_DONE                         \
+	(MXC_V_GCR_RSTR0_UART0_RESET_DONE                        \
+	 << MXC_F_GCR_RSTR0_UART0_POS) /**<                      \
+					  RSTR0_UART0_RESET_DONE \
+					  Setting                \
+					*/
+#define MXC_V_GCR_RSTR0_UART0_BUSY \
 	((uint32_t)0x1UL) /**< RSTR0_UART0_BUSY Value */
-#define MXC_S_GCR_RSTR0_UART0_BUSY                                             \
-	(MXC_V_GCR_RSTR0_UART0_BUSY                                            \
-	 << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_BUSY Setting */
+#define MXC_S_GCR_RSTR0_UART0_BUSY                         \
+	(MXC_V_GCR_RSTR0_UART0_BUSY                        \
+	 << MXC_F_GCR_RSTR0_UART0_POS) /**<                \
+					  RSTR0_UART0_BUSY \
+					  Setting          \
+					*/
 
 #define MXC_F_GCR_RSTR0_UART1_POS 12 /**< RSTR0_UART1 Position */
 #define MXC_F_GCR_RSTR0_UART1                                                  \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_GCR_RSTR0_UART1_POS)) /**< RSTR0_UART1 Mask */
-#define MXC_V_GCR_RSTR0_UART1_RFU                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_UART1_POS)) /**< RSTR0_UART1 Mask \
+							  */
+#define MXC_V_GCR_RSTR0_UART1_RFU \
 	((uint32_t)0x0UL) /**< RSTR0_UART1_RFU Value */
-#define MXC_S_GCR_RSTR0_UART1_RFU                                              \
-	(MXC_V_GCR_RSTR0_UART1_RFU                                             \
-	 << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_RFU Setting */
-#define MXC_V_GCR_RSTR0_UART1_RESET                                            \
+#define MXC_S_GCR_RSTR0_UART1_RFU                         \
+	(MXC_V_GCR_RSTR0_UART1_RFU                        \
+	 << MXC_F_GCR_RSTR0_UART1_POS) /**<               \
+					  RSTR0_UART1_RFU \
+					  Setting */
+#define MXC_V_GCR_RSTR0_UART1_RESET \
 	((uint32_t)0x1UL) /**< RSTR0_UART1_RESET Value */
-#define MXC_S_GCR_RSTR0_UART1_RESET                                            \
-	(MXC_V_GCR_RSTR0_UART1_RESET                                           \
-	 << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_RESET Setting */
-#define MXC_V_GCR_RSTR0_UART1_RESET_DONE                                       \
+#define MXC_S_GCR_RSTR0_UART1_RESET                         \
+	(MXC_V_GCR_RSTR0_UART1_RESET                        \
+	 << MXC_F_GCR_RSTR0_UART1_POS) /**<                 \
+					  RSTR0_UART1_RESET \
+					  Setting           \
+					*/
+#define MXC_V_GCR_RSTR0_UART1_RESET_DONE \
 	((uint32_t)0x0UL) /**< RSTR0_UART1_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_UART1_RESET_DONE                                       \
-	(MXC_V_GCR_RSTR0_UART1_RESET_DONE                                      \
-	 << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_UART1_BUSY                                             \
+#define MXC_S_GCR_RSTR0_UART1_RESET_DONE                         \
+	(MXC_V_GCR_RSTR0_UART1_RESET_DONE                        \
+	 << MXC_F_GCR_RSTR0_UART1_POS) /**<                      \
+					  RSTR0_UART1_RESET_DONE \
+					  Setting                \
+					*/
+#define MXC_V_GCR_RSTR0_UART1_BUSY \
 	((uint32_t)0x1UL) /**< RSTR0_UART1_BUSY Value */
-#define MXC_S_GCR_RSTR0_UART1_BUSY                                             \
-	(MXC_V_GCR_RSTR0_UART1_BUSY                                            \
-	 << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_BUSY Setting */
+#define MXC_S_GCR_RSTR0_UART1_BUSY                         \
+	(MXC_V_GCR_RSTR0_UART1_BUSY                        \
+	 << MXC_F_GCR_RSTR0_UART1_POS) /**<                \
+					  RSTR0_UART1_BUSY \
+					  Setting          \
+					*/
 
 #define MXC_F_GCR_RSTR0_SPI0_POS 13 /**< RSTR0_SPI0 Position */
-#define MXC_F_GCR_RSTR0_SPI0                                                   \
-	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI0_POS)) /**< RSTR0_SPI0 Mask   \
+#define MXC_F_GCR_RSTR0_SPI0                                                 \
+	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI0_POS)) /**< RSTR0_SPI0 Mask \
 							 */
-#define MXC_V_GCR_RSTR0_SPI0_RFU                                               \
-	((uint32_t)0x0UL) /**< RSTR0_SPI0_RFU Value                            \
+#define MXC_V_GCR_RSTR0_SPI0_RFU                    \
+	((uint32_t)0x0UL) /**< RSTR0_SPI0_RFU Value \
 			   */
-#define MXC_S_GCR_RSTR0_SPI0_RFU                                               \
-	(MXC_V_GCR_RSTR0_SPI0_RFU                                              \
-	 << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_RFU Setting */
-#define MXC_V_GCR_RSTR0_SPI0_RESET                                             \
+#define MXC_S_GCR_RSTR0_SPI0_RFU                        \
+	(MXC_V_GCR_RSTR0_SPI0_RFU                       \
+	 << MXC_F_GCR_RSTR0_SPI0_POS) /**<              \
+					 RSTR0_SPI0_RFU \
+					 Setting */
+#define MXC_V_GCR_RSTR0_SPI0_RESET \
 	((uint32_t)0x1UL) /**< RSTR0_SPI0_RESET Value */
-#define MXC_S_GCR_RSTR0_SPI0_RESET                                             \
-	(MXC_V_GCR_RSTR0_SPI0_RESET                                            \
-	 << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_RESET Setting */
-#define MXC_V_GCR_RSTR0_SPI0_RESET_DONE                                        \
+#define MXC_S_GCR_RSTR0_SPI0_RESET                        \
+	(MXC_V_GCR_RSTR0_SPI0_RESET                       \
+	 << MXC_F_GCR_RSTR0_SPI0_POS) /**<                \
+					 RSTR0_SPI0_RESET \
+					 Setting */
+#define MXC_V_GCR_RSTR0_SPI0_RESET_DONE \
 	((uint32_t)0x0UL) /**< RSTR0_SPI0_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_SPI0_RESET_DONE                                        \
-	(MXC_V_GCR_RSTR0_SPI0_RESET_DONE                                       \
-	 << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_SPI0_BUSY                                              \
+#define MXC_S_GCR_RSTR0_SPI0_RESET_DONE                        \
+	(MXC_V_GCR_RSTR0_SPI0_RESET_DONE                       \
+	 << MXC_F_GCR_RSTR0_SPI0_POS) /**<                     \
+					 RSTR0_SPI0_RESET_DONE \
+					 Setting               \
+				       */
+#define MXC_V_GCR_RSTR0_SPI0_BUSY \
 	((uint32_t)0x1UL) /**< RSTR0_SPI0_BUSY Value */
-#define MXC_S_GCR_RSTR0_SPI0_BUSY                                              \
-	(MXC_V_GCR_RSTR0_SPI0_BUSY                                             \
-	 << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_BUSY Setting */
+#define MXC_S_GCR_RSTR0_SPI0_BUSY                        \
+	(MXC_V_GCR_RSTR0_SPI0_BUSY                       \
+	 << MXC_F_GCR_RSTR0_SPI0_POS) /**<               \
+					 RSTR0_SPI0_BUSY \
+					 Setting */
 
 #define MXC_F_GCR_RSTR0_SPI1_POS 14 /**< RSTR0_SPI1 Position */
-#define MXC_F_GCR_RSTR0_SPI1                                                   \
-	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI1_POS)) /**< RSTR0_SPI1 Mask   \
+#define MXC_F_GCR_RSTR0_SPI1                                                 \
+	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI1_POS)) /**< RSTR0_SPI1 Mask \
 							 */
-#define MXC_V_GCR_RSTR0_SPI1_RFU                                               \
-	((uint32_t)0x0UL) /**< RSTR0_SPI1_RFU Value                            \
+#define MXC_V_GCR_RSTR0_SPI1_RFU                    \
+	((uint32_t)0x0UL) /**< RSTR0_SPI1_RFU Value \
 			   */
-#define MXC_S_GCR_RSTR0_SPI1_RFU                                               \
-	(MXC_V_GCR_RSTR0_SPI1_RFU                                              \
-	 << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_RFU Setting */
-#define MXC_V_GCR_RSTR0_SPI1_RESET                                             \
+#define MXC_S_GCR_RSTR0_SPI1_RFU                        \
+	(MXC_V_GCR_RSTR0_SPI1_RFU                       \
+	 << MXC_F_GCR_RSTR0_SPI1_POS) /**<              \
+					 RSTR0_SPI1_RFU \
+					 Setting */
+#define MXC_V_GCR_RSTR0_SPI1_RESET \
 	((uint32_t)0x1UL) /**< RSTR0_SPI1_RESET Value */
-#define MXC_S_GCR_RSTR0_SPI1_RESET                                             \
-	(MXC_V_GCR_RSTR0_SPI1_RESET                                            \
-	 << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_RESET Setting */
-#define MXC_V_GCR_RSTR0_SPI1_RESET_DONE                                        \
+#define MXC_S_GCR_RSTR0_SPI1_RESET                        \
+	(MXC_V_GCR_RSTR0_SPI1_RESET                       \
+	 << MXC_F_GCR_RSTR0_SPI1_POS) /**<                \
+					 RSTR0_SPI1_RESET \
+					 Setting */
+#define MXC_V_GCR_RSTR0_SPI1_RESET_DONE \
 	((uint32_t)0x0UL) /**< RSTR0_SPI1_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_SPI1_RESET_DONE                                        \
-	(MXC_V_GCR_RSTR0_SPI1_RESET_DONE                                       \
-	 << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_SPI1_BUSY                                              \
+#define MXC_S_GCR_RSTR0_SPI1_RESET_DONE                        \
+	(MXC_V_GCR_RSTR0_SPI1_RESET_DONE                       \
+	 << MXC_F_GCR_RSTR0_SPI1_POS) /**<                     \
+					 RSTR0_SPI1_RESET_DONE \
+					 Setting               \
+				       */
+#define MXC_V_GCR_RSTR0_SPI1_BUSY \
 	((uint32_t)0x1UL) /**< RSTR0_SPI1_BUSY Value */
-#define MXC_S_GCR_RSTR0_SPI1_BUSY                                              \
-	(MXC_V_GCR_RSTR0_SPI1_BUSY                                             \
-	 << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_BUSY Setting */
+#define MXC_S_GCR_RSTR0_SPI1_BUSY                        \
+	(MXC_V_GCR_RSTR0_SPI1_BUSY                       \
+	 << MXC_F_GCR_RSTR0_SPI1_POS) /**<               \
+					 RSTR0_SPI1_BUSY \
+					 Setting */
 
 #define MXC_F_GCR_RSTR0_I2C0_POS 16 /**< RSTR0_I2C0 Position */
-#define MXC_F_GCR_RSTR0_I2C0                                                   \
-	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_I2C0_POS)) /**< RSTR0_I2C0 Mask   \
+#define MXC_F_GCR_RSTR0_I2C0                                                 \
+	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_I2C0_POS)) /**< RSTR0_I2C0 Mask \
 							 */
-#define MXC_V_GCR_RSTR0_I2C0_RFU                                               \
-	((uint32_t)0x0UL) /**< RSTR0_I2C0_RFU Value                            \
+#define MXC_V_GCR_RSTR0_I2C0_RFU                    \
+	((uint32_t)0x0UL) /**< RSTR0_I2C0_RFU Value \
 			   */
-#define MXC_S_GCR_RSTR0_I2C0_RFU                                               \
-	(MXC_V_GCR_RSTR0_I2C0_RFU                                              \
-	 << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_RFU Setting */
-#define MXC_V_GCR_RSTR0_I2C0_RESET                                             \
+#define MXC_S_GCR_RSTR0_I2C0_RFU                        \
+	(MXC_V_GCR_RSTR0_I2C0_RFU                       \
+	 << MXC_F_GCR_RSTR0_I2C0_POS) /**<              \
+					 RSTR0_I2C0_RFU \
+					 Setting */
+#define MXC_V_GCR_RSTR0_I2C0_RESET \
 	((uint32_t)0x1UL) /**< RSTR0_I2C0_RESET Value */
-#define MXC_S_GCR_RSTR0_I2C0_RESET                                             \
-	(MXC_V_GCR_RSTR0_I2C0_RESET                                            \
-	 << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_RESET Setting */
-#define MXC_V_GCR_RSTR0_I2C0_RESET_DONE                                        \
+#define MXC_S_GCR_RSTR0_I2C0_RESET                        \
+	(MXC_V_GCR_RSTR0_I2C0_RESET                       \
+	 << MXC_F_GCR_RSTR0_I2C0_POS) /**<                \
+					 RSTR0_I2C0_RESET \
+					 Setting */
+#define MXC_V_GCR_RSTR0_I2C0_RESET_DONE \
 	((uint32_t)0x0UL) /**< RSTR0_I2C0_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_I2C0_RESET_DONE                                        \
-	(MXC_V_GCR_RSTR0_I2C0_RESET_DONE                                       \
-	 << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_I2C0_BUSY                                              \
+#define MXC_S_GCR_RSTR0_I2C0_RESET_DONE                        \
+	(MXC_V_GCR_RSTR0_I2C0_RESET_DONE                       \
+	 << MXC_F_GCR_RSTR0_I2C0_POS) /**<                     \
+					 RSTR0_I2C0_RESET_DONE \
+					 Setting               \
+				       */
+#define MXC_V_GCR_RSTR0_I2C0_BUSY \
 	((uint32_t)0x1UL) /**< RSTR0_I2C0_BUSY Value */
-#define MXC_S_GCR_RSTR0_I2C0_BUSY                                              \
-	(MXC_V_GCR_RSTR0_I2C0_BUSY                                             \
-	 << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_BUSY Setting */
+#define MXC_S_GCR_RSTR0_I2C0_BUSY                        \
+	(MXC_V_GCR_RSTR0_I2C0_BUSY                       \
+	 << MXC_F_GCR_RSTR0_I2C0_POS) /**<               \
+					 RSTR0_I2C0_BUSY \
+					 Setting */
 
 #define MXC_F_GCR_RSTR0_RTC_POS 17 /**< RSTR0_RTC Position */
-#define MXC_F_GCR_RSTR0_RTC                                                    \
+#define MXC_F_GCR_RSTR0_RTC \
 	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_RTC_POS)) /**< RSTR0_RTC Mask */
 #define MXC_V_GCR_RSTR0_RTC_RFU ((uint32_t)0x0UL) /**< RSTR0_RTC_RFU Value */
-#define MXC_S_GCR_RSTR0_RTC_RFU                                                \
-	(MXC_V_GCR_RSTR0_RTC_RFU                                               \
-	 << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_RFU Setting */
-#define MXC_V_GCR_RSTR0_RTC_RESET                                              \
+#define MXC_S_GCR_RSTR0_RTC_RFU                                               \
+	(MXC_V_GCR_RSTR0_RTC_RFU << MXC_F_GCR_RSTR0_RTC_POS) /**<             \
+								RSTR0_RTC_RFU \
+								Setting */
+#define MXC_V_GCR_RSTR0_RTC_RESET \
 	((uint32_t)0x1UL) /**< RSTR0_RTC_RESET Value */
-#define MXC_S_GCR_RSTR0_RTC_RESET                                              \
-	(MXC_V_GCR_RSTR0_RTC_RESET                                             \
-	 << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_RESET Setting */
-#define MXC_V_GCR_RSTR0_RTC_RESET_DONE                                         \
+#define MXC_S_GCR_RSTR0_RTC_RESET                       \
+	(MXC_V_GCR_RSTR0_RTC_RESET                      \
+	 << MXC_F_GCR_RSTR0_RTC_POS) /**<               \
+					RSTR0_RTC_RESET \
+					Setting */
+#define MXC_V_GCR_RSTR0_RTC_RESET_DONE \
 	((uint32_t)0x0UL) /**< RSTR0_RTC_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_RTC_RESET_DONE                                         \
-	(MXC_V_GCR_RSTR0_RTC_RESET_DONE                                        \
-	 << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_RTC_BUSY                                               \
-	((uint32_t)0x1UL) /**< RSTR0_RTC_BUSY Value                            \
+#define MXC_S_GCR_RSTR0_RTC_RESET_DONE                       \
+	(MXC_V_GCR_RSTR0_RTC_RESET_DONE                      \
+	 << MXC_F_GCR_RSTR0_RTC_POS) /**<                    \
+					RSTR0_RTC_RESET_DONE \
+					Setting              \
+				      */
+#define MXC_V_GCR_RSTR0_RTC_BUSY                    \
+	((uint32_t)0x1UL) /**< RSTR0_RTC_BUSY Value \
 			   */
-#define MXC_S_GCR_RSTR0_RTC_BUSY                                               \
-	(MXC_V_GCR_RSTR0_RTC_BUSY                                              \
-	 << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_BUSY Setting */
+#define MXC_S_GCR_RSTR0_RTC_BUSY                       \
+	(MXC_V_GCR_RSTR0_RTC_BUSY                      \
+	 << MXC_F_GCR_RSTR0_RTC_POS) /**<              \
+					RSTR0_RTC_BUSY \
+					Setting */
 
 #define MXC_F_GCR_RSTR0_SRST_POS 29 /**< RSTR0_SRST Position */
-#define MXC_F_GCR_RSTR0_SRST                                                   \
-	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SRST_POS)) /**< RSTR0_SRST Mask   \
+#define MXC_F_GCR_RSTR0_SRST                                                 \
+	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SRST_POS)) /**< RSTR0_SRST Mask \
 							 */
-#define MXC_V_GCR_RSTR0_SRST_RFU                                               \
-	((uint32_t)0x0UL) /**< RSTR0_SRST_RFU Value                            \
+#define MXC_V_GCR_RSTR0_SRST_RFU                    \
+	((uint32_t)0x0UL) /**< RSTR0_SRST_RFU Value \
 			   */
-#define MXC_S_GCR_RSTR0_SRST_RFU                                               \
-	(MXC_V_GCR_RSTR0_SRST_RFU                                              \
-	 << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_RFU Setting */
-#define MXC_V_GCR_RSTR0_SRST_RESET                                             \
+#define MXC_S_GCR_RSTR0_SRST_RFU                        \
+	(MXC_V_GCR_RSTR0_SRST_RFU                       \
+	 << MXC_F_GCR_RSTR0_SRST_POS) /**<              \
+					 RSTR0_SRST_RFU \
+					 Setting */
+#define MXC_V_GCR_RSTR0_SRST_RESET \
 	((uint32_t)0x1UL) /**< RSTR0_SRST_RESET Value */
-#define MXC_S_GCR_RSTR0_SRST_RESET                                             \
-	(MXC_V_GCR_RSTR0_SRST_RESET                                            \
-	 << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_RESET Setting */
-#define MXC_V_GCR_RSTR0_SRST_RESET_DONE                                        \
+#define MXC_S_GCR_RSTR0_SRST_RESET                        \
+	(MXC_V_GCR_RSTR0_SRST_RESET                       \
+	 << MXC_F_GCR_RSTR0_SRST_POS) /**<                \
+					 RSTR0_SRST_RESET \
+					 Setting */
+#define MXC_V_GCR_RSTR0_SRST_RESET_DONE \
 	((uint32_t)0x0UL) /**< RSTR0_SRST_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_SRST_RESET_DONE                                        \
-	(MXC_V_GCR_RSTR0_SRST_RESET_DONE                                       \
-	 << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_SRST_BUSY                                              \
+#define MXC_S_GCR_RSTR0_SRST_RESET_DONE                        \
+	(MXC_V_GCR_RSTR0_SRST_RESET_DONE                       \
+	 << MXC_F_GCR_RSTR0_SRST_POS) /**<                     \
+					 RSTR0_SRST_RESET_DONE \
+					 Setting               \
+				       */
+#define MXC_V_GCR_RSTR0_SRST_BUSY \
 	((uint32_t)0x1UL) /**< RSTR0_SRST_BUSY Value */
-#define MXC_S_GCR_RSTR0_SRST_BUSY                                              \
-	(MXC_V_GCR_RSTR0_SRST_BUSY                                             \
-	 << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_BUSY Setting */
+#define MXC_S_GCR_RSTR0_SRST_BUSY                        \
+	(MXC_V_GCR_RSTR0_SRST_BUSY                       \
+	 << MXC_F_GCR_RSTR0_SRST_POS) /**<               \
+					 RSTR0_SRST_BUSY \
+					 Setting */
 
 #define MXC_F_GCR_RSTR0_PRST_POS 30 /**< RSTR0_PRST Position */
-#define MXC_F_GCR_RSTR0_PRST                                                   \
-	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_PRST_POS)) /**< RSTR0_PRST Mask   \
+#define MXC_F_GCR_RSTR0_PRST                                                 \
+	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_PRST_POS)) /**< RSTR0_PRST Mask \
 							 */
-#define MXC_V_GCR_RSTR0_PRST_RFU                                               \
-	((uint32_t)0x0UL) /**< RSTR0_PRST_RFU Value                            \
+#define MXC_V_GCR_RSTR0_PRST_RFU                    \
+	((uint32_t)0x0UL) /**< RSTR0_PRST_RFU Value \
 			   */
-#define MXC_S_GCR_RSTR0_PRST_RFU                                               \
-	(MXC_V_GCR_RSTR0_PRST_RFU                                              \
-	 << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_RFU Setting */
-#define MXC_V_GCR_RSTR0_PRST_RESET                                             \
+#define MXC_S_GCR_RSTR0_PRST_RFU                        \
+	(MXC_V_GCR_RSTR0_PRST_RFU                       \
+	 << MXC_F_GCR_RSTR0_PRST_POS) /**<              \
+					 RSTR0_PRST_RFU \
+					 Setting */
+#define MXC_V_GCR_RSTR0_PRST_RESET \
 	((uint32_t)0x1UL) /**< RSTR0_PRST_RESET Value */
-#define MXC_S_GCR_RSTR0_PRST_RESET                                             \
-	(MXC_V_GCR_RSTR0_PRST_RESET                                            \
-	 << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_RESET Setting */
-#define MXC_V_GCR_RSTR0_PRST_RESET_DONE                                        \
+#define MXC_S_GCR_RSTR0_PRST_RESET                        \
+	(MXC_V_GCR_RSTR0_PRST_RESET                       \
+	 << MXC_F_GCR_RSTR0_PRST_POS) /**<                \
+					 RSTR0_PRST_RESET \
+					 Setting */
+#define MXC_V_GCR_RSTR0_PRST_RESET_DONE \
 	((uint32_t)0x0UL) /**< RSTR0_PRST_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_PRST_RESET_DONE                                        \
-	(MXC_V_GCR_RSTR0_PRST_RESET_DONE                                       \
-	 << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_PRST_BUSY                                              \
+#define MXC_S_GCR_RSTR0_PRST_RESET_DONE                        \
+	(MXC_V_GCR_RSTR0_PRST_RESET_DONE                       \
+	 << MXC_F_GCR_RSTR0_PRST_POS) /**<                     \
+					 RSTR0_PRST_RESET_DONE \
+					 Setting               \
+				       */
+#define MXC_V_GCR_RSTR0_PRST_BUSY \
 	((uint32_t)0x1UL) /**< RSTR0_PRST_BUSY Value */
-#define MXC_S_GCR_RSTR0_PRST_BUSY                                              \
-	(MXC_V_GCR_RSTR0_PRST_BUSY                                             \
-	 << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_BUSY Setting */
+#define MXC_S_GCR_RSTR0_PRST_BUSY                        \
+	(MXC_V_GCR_RSTR0_PRST_BUSY                       \
+	 << MXC_F_GCR_RSTR0_PRST_POS) /**<               \
+					 RSTR0_PRST_BUSY \
+					 Setting */
 
 #define MXC_F_GCR_RSTR0_SYSTEM_POS 31 /**< RSTR0_SYSTEM Position */
-#define MXC_F_GCR_RSTR0_SYSTEM                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_RSTR0_SYSTEM_POS)) /**< RSTR0_SYSTEM Mask */
-#define MXC_V_GCR_RSTR0_SYSTEM_RFU                                             \
+#define MXC_F_GCR_RSTR0_SYSTEM                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SYSTEM_POS)) /**< RSTR0_SYSTEM \
+							     Mask */
+#define MXC_V_GCR_RSTR0_SYSTEM_RFU \
 	((uint32_t)0x0UL) /**< RSTR0_SYSTEM_RFU Value */
-#define MXC_S_GCR_RSTR0_SYSTEM_RFU                                             \
-	(MXC_V_GCR_RSTR0_SYSTEM_RFU                                            \
-	 << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_RFU Setting */
-#define MXC_V_GCR_RSTR0_SYSTEM_RESET                                           \
+#define MXC_S_GCR_RSTR0_SYSTEM_RFU                          \
+	(MXC_V_GCR_RSTR0_SYSTEM_RFU                         \
+	 << MXC_F_GCR_RSTR0_SYSTEM_POS) /**<                \
+					   RSTR0_SYSTEM_RFU \
+					   Setting          \
+					 */
+#define MXC_V_GCR_RSTR0_SYSTEM_RESET \
 	((uint32_t)0x1UL) /**< RSTR0_SYSTEM_RESET Value */
-#define MXC_S_GCR_RSTR0_SYSTEM_RESET                                           \
-	(MXC_V_GCR_RSTR0_SYSTEM_RESET                                          \
-	 << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_RESET Setting */
-#define MXC_V_GCR_RSTR0_SYSTEM_RESET_DONE                                      \
+#define MXC_S_GCR_RSTR0_SYSTEM_RESET                          \
+	(MXC_V_GCR_RSTR0_SYSTEM_RESET                         \
+	 << MXC_F_GCR_RSTR0_SYSTEM_POS) /**<                  \
+					   RSTR0_SYSTEM_RESET \
+					   Setting            \
+					 */
+#define MXC_V_GCR_RSTR0_SYSTEM_RESET_DONE \
 	((uint32_t)0x0UL) /**< RSTR0_SYSTEM_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_SYSTEM_RESET_DONE                                      \
-	(MXC_V_GCR_RSTR0_SYSTEM_RESET_DONE                                     \
-	 << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_RESET_DONE Setting   \
+#define MXC_S_GCR_RSTR0_SYSTEM_RESET_DONE                                    \
+	(MXC_V_GCR_RSTR0_SYSTEM_RESET_DONE                                   \
+	 << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_RESET_DONE Setting \
 					 */
-#define MXC_V_GCR_RSTR0_SYSTEM_BUSY                                            \
+#define MXC_V_GCR_RSTR0_SYSTEM_BUSY \
 	((uint32_t)0x1UL) /**< RSTR0_SYSTEM_BUSY Value */
-#define MXC_S_GCR_RSTR0_SYSTEM_BUSY                                            \
-	(MXC_V_GCR_RSTR0_SYSTEM_BUSY                                           \
-	 << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_BUSY Setting */
+#define MXC_S_GCR_RSTR0_SYSTEM_BUSY                          \
+	(MXC_V_GCR_RSTR0_SYSTEM_BUSY                         \
+	 << MXC_F_GCR_RSTR0_SYSTEM_POS) /**<                 \
+					   RSTR0_SYSTEM_BUSY \
+					   Setting           \
+					 */
 
 /**
  * Clock Control.
  */
 #define MXC_F_GCR_CLKCN_PSC_POS 6 /**< CLKCN_PSC Position */
-#define MXC_F_GCR_CLKCN_PSC                                                    \
+#define MXC_F_GCR_CLKCN_PSC \
 	((uint32_t)(0x7UL << MXC_F_GCR_CLKCN_PSC_POS)) /**< CLKCN_PSC Mask */
-#define MXC_V_GCR_CLKCN_PSC_DIV1                                               \
-	((uint32_t)0x0UL) /**< CLKCN_PSC_DIV1 Value                            \
+#define MXC_V_GCR_CLKCN_PSC_DIV1                    \
+	((uint32_t)0x0UL) /**< CLKCN_PSC_DIV1 Value \
 			   */
-#define MXC_S_GCR_CLKCN_PSC_DIV1                                               \
-	(MXC_V_GCR_CLKCN_PSC_DIV1                                              \
-	 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV1 Setting */
-#define MXC_V_GCR_CLKCN_PSC_DIV2                                               \
-	((uint32_t)0x1UL) /**< CLKCN_PSC_DIV2 Value                            \
+#define MXC_S_GCR_CLKCN_PSC_DIV1                       \
+	(MXC_V_GCR_CLKCN_PSC_DIV1                      \
+	 << MXC_F_GCR_CLKCN_PSC_POS) /**<              \
+					CLKCN_PSC_DIV1 \
+					Setting */
+#define MXC_V_GCR_CLKCN_PSC_DIV2                    \
+	((uint32_t)0x1UL) /**< CLKCN_PSC_DIV2 Value \
 			   */
-#define MXC_S_GCR_CLKCN_PSC_DIV2                                               \
-	(MXC_V_GCR_CLKCN_PSC_DIV2                                              \
-	 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV2 Setting */
-#define MXC_V_GCR_CLKCN_PSC_DIV4                                               \
-	((uint32_t)0x2UL) /**< CLKCN_PSC_DIV4 Value                            \
+#define MXC_S_GCR_CLKCN_PSC_DIV2                       \
+	(MXC_V_GCR_CLKCN_PSC_DIV2                      \
+	 << MXC_F_GCR_CLKCN_PSC_POS) /**<              \
+					CLKCN_PSC_DIV2 \
+					Setting */
+#define MXC_V_GCR_CLKCN_PSC_DIV4                    \
+	((uint32_t)0x2UL) /**< CLKCN_PSC_DIV4 Value \
 			   */
-#define MXC_S_GCR_CLKCN_PSC_DIV4                                               \
-	(MXC_V_GCR_CLKCN_PSC_DIV4                                              \
-	 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV4 Setting */
-#define MXC_V_GCR_CLKCN_PSC_DIV8                                               \
-	((uint32_t)0x3UL) /**< CLKCN_PSC_DIV8 Value                            \
+#define MXC_S_GCR_CLKCN_PSC_DIV4                       \
+	(MXC_V_GCR_CLKCN_PSC_DIV4                      \
+	 << MXC_F_GCR_CLKCN_PSC_POS) /**<              \
+					CLKCN_PSC_DIV4 \
+					Setting */
+#define MXC_V_GCR_CLKCN_PSC_DIV8                    \
+	((uint32_t)0x3UL) /**< CLKCN_PSC_DIV8 Value \
 			   */
-#define MXC_S_GCR_CLKCN_PSC_DIV8                                               \
-	(MXC_V_GCR_CLKCN_PSC_DIV8                                              \
-	 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV8 Setting */
-#define MXC_V_GCR_CLKCN_PSC_DIV16                                              \
+#define MXC_S_GCR_CLKCN_PSC_DIV8                       \
+	(MXC_V_GCR_CLKCN_PSC_DIV8                      \
+	 << MXC_F_GCR_CLKCN_PSC_POS) /**<              \
+					CLKCN_PSC_DIV8 \
+					Setting */
+#define MXC_V_GCR_CLKCN_PSC_DIV16 \
 	((uint32_t)0x4UL) /**< CLKCN_PSC_DIV16 Value */
-#define MXC_S_GCR_CLKCN_PSC_DIV16                                              \
-	(MXC_V_GCR_CLKCN_PSC_DIV16                                             \
-	 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV16 Setting */
-#define MXC_V_GCR_CLKCN_PSC_DIV32                                              \
+#define MXC_S_GCR_CLKCN_PSC_DIV16                       \
+	(MXC_V_GCR_CLKCN_PSC_DIV16                      \
+	 << MXC_F_GCR_CLKCN_PSC_POS) /**<               \
+					CLKCN_PSC_DIV16 \
+					Setting */
+#define MXC_V_GCR_CLKCN_PSC_DIV32 \
 	((uint32_t)0x5UL) /**< CLKCN_PSC_DIV32 Value */
-#define MXC_S_GCR_CLKCN_PSC_DIV32                                              \
-	(MXC_V_GCR_CLKCN_PSC_DIV32                                             \
-	 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV32 Setting */
-#define MXC_V_GCR_CLKCN_PSC_DIV64                                              \
+#define MXC_S_GCR_CLKCN_PSC_DIV32                       \
+	(MXC_V_GCR_CLKCN_PSC_DIV32                      \
+	 << MXC_F_GCR_CLKCN_PSC_POS) /**<               \
+					CLKCN_PSC_DIV32 \
+					Setting */
+#define MXC_V_GCR_CLKCN_PSC_DIV64 \
 	((uint32_t)0x6UL) /**< CLKCN_PSC_DIV64 Value */
-#define MXC_S_GCR_CLKCN_PSC_DIV64                                              \
-	(MXC_V_GCR_CLKCN_PSC_DIV64                                             \
-	 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV64 Setting */
-#define MXC_V_GCR_CLKCN_PSC_DIV128                                             \
+#define MXC_S_GCR_CLKCN_PSC_DIV64                       \
+	(MXC_V_GCR_CLKCN_PSC_DIV64                      \
+	 << MXC_F_GCR_CLKCN_PSC_POS) /**<               \
+					CLKCN_PSC_DIV64 \
+					Setting */
+#define MXC_V_GCR_CLKCN_PSC_DIV128 \
 	((uint32_t)0x7UL) /**< CLKCN_PSC_DIV128 Value */
-#define MXC_S_GCR_CLKCN_PSC_DIV128                                             \
-	(MXC_V_GCR_CLKCN_PSC_DIV128                                            \
-	 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV128 Setting */
+#define MXC_S_GCR_CLKCN_PSC_DIV128                       \
+	(MXC_V_GCR_CLKCN_PSC_DIV128                      \
+	 << MXC_F_GCR_CLKCN_PSC_POS) /**<                \
+					CLKCN_PSC_DIV128 \
+					Setting */
 
 #define MXC_F_GCR_CLKCN_CLKSEL_POS 9 /**< CLKCN_CLKSEL Position */
-#define MXC_F_GCR_CLKCN_CLKSEL                                                 \
-	((uint32_t)(0x7UL                                                      \
-		    << MXC_F_GCR_CLKCN_CLKSEL_POS)) /**< CLKCN_CLKSEL Mask */
-#define MXC_V_GCR_CLKCN_CLKSEL_HIRC                                            \
+#define MXC_F_GCR_CLKCN_CLKSEL                                              \
+	((uint32_t)(0x7UL << MXC_F_GCR_CLKCN_CLKSEL_POS)) /**< CLKCN_CLKSEL \
+							     Mask */
+#define MXC_V_GCR_CLKCN_CLKSEL_HIRC \
 	((uint32_t)0x0UL) /**< CLKCN_CLKSEL_HIRC Value */
-#define MXC_S_GCR_CLKCN_CLKSEL_HIRC                                            \
-	(MXC_V_GCR_CLKCN_CLKSEL_HIRC                                           \
-	 << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_HIRC Setting */
-#define MXC_V_GCR_CLKCN_CLKSEL_NANORING                                        \
+#define MXC_S_GCR_CLKCN_CLKSEL_HIRC                          \
+	(MXC_V_GCR_CLKCN_CLKSEL_HIRC                         \
+	 << MXC_F_GCR_CLKCN_CLKSEL_POS) /**<                 \
+					   CLKCN_CLKSEL_HIRC \
+					   Setting           \
+					 */
+#define MXC_V_GCR_CLKCN_CLKSEL_NANORING \
 	((uint32_t)0x3UL) /**< CLKCN_CLKSEL_NANORING Value */
-#define MXC_S_GCR_CLKCN_CLKSEL_NANORING                                        \
-	(MXC_V_GCR_CLKCN_CLKSEL_NANORING                                       \
-	 << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_NANORING Setting */
-#define MXC_V_GCR_CLKCN_CLKSEL_HFXIN                                           \
+#define MXC_S_GCR_CLKCN_CLKSEL_NANORING                          \
+	(MXC_V_GCR_CLKCN_CLKSEL_NANORING                         \
+	 << MXC_F_GCR_CLKCN_CLKSEL_POS) /**<                     \
+					   CLKCN_CLKSEL_NANORING \
+					   Setting               \
+					 */
+#define MXC_V_GCR_CLKCN_CLKSEL_HFXIN \
 	((uint32_t)0x6UL) /**< CLKCN_CLKSEL_HFXIN Value */
-#define MXC_S_GCR_CLKCN_CLKSEL_HFXIN                                           \
-	(MXC_V_GCR_CLKCN_CLKSEL_HFXIN                                          \
-	 << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_HFXIN Setting */
+#define MXC_S_GCR_CLKCN_CLKSEL_HFXIN                          \
+	(MXC_V_GCR_CLKCN_CLKSEL_HFXIN                         \
+	 << MXC_F_GCR_CLKCN_CLKSEL_POS) /**<                  \
+					   CLKCN_CLKSEL_HFXIN \
+					   Setting            \
+					 */
 
 #define MXC_F_GCR_CLKCN_CKRDY_POS 13 /**< CLKCN_CKRDY Position */
 #define MXC_F_GCR_CLKCN_CKRDY                                                  \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_GCR_CLKCN_CKRDY_POS)) /**< CLKCN_CKRDY Mask */
-#define MXC_V_GCR_CLKCN_CKRDY_BUSY                                             \
+	((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_CKRDY_POS)) /**< CLKCN_CKRDY Mask \
+							  */
+#define MXC_V_GCR_CLKCN_CKRDY_BUSY \
 	((uint32_t)0x0UL) /**< CLKCN_CKRDY_BUSY Value */
-#define MXC_S_GCR_CLKCN_CKRDY_BUSY                                             \
-	(MXC_V_GCR_CLKCN_CKRDY_BUSY                                            \
-	 << MXC_F_GCR_CLKCN_CKRDY_POS) /**< CLKCN_CKRDY_BUSY Setting */
-#define MXC_V_GCR_CLKCN_CKRDY_READY                                            \
+#define MXC_S_GCR_CLKCN_CKRDY_BUSY                         \
+	(MXC_V_GCR_CLKCN_CKRDY_BUSY                        \
+	 << MXC_F_GCR_CLKCN_CKRDY_POS) /**<                \
+					  CLKCN_CKRDY_BUSY \
+					  Setting          \
+					*/
+#define MXC_V_GCR_CLKCN_CKRDY_READY \
 	((uint32_t)0x1UL) /**< CLKCN_CKRDY_READY Value */
-#define MXC_S_GCR_CLKCN_CKRDY_READY                                            \
-	(MXC_V_GCR_CLKCN_CKRDY_READY                                           \
-	 << MXC_F_GCR_CLKCN_CKRDY_POS) /**< CLKCN_CKRDY_READY Setting */
+#define MXC_S_GCR_CLKCN_CKRDY_READY                         \
+	(MXC_V_GCR_CLKCN_CKRDY_READY                        \
+	 << MXC_F_GCR_CLKCN_CKRDY_POS) /**<                 \
+					  CLKCN_CKRDY_READY \
+					  Setting           \
+					*/
 
 #define MXC_F_GCR_CLKCN_X32K_EN_POS 17 /**< CLKCN_X32K_EN Position */
-#define MXC_F_GCR_CLKCN_X32K_EN                                                \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_CLKCN_X32K_EN_POS)) /**< CLKCN_X32K_EN Mask */
-#define MXC_V_GCR_CLKCN_X32K_EN_DIS                                            \
+#define MXC_F_GCR_CLKCN_X32K_EN                                               \
+	((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_X32K_EN_POS)) /**< CLKCN_X32K_EN \
+							      Mask */
+#define MXC_V_GCR_CLKCN_X32K_EN_DIS \
 	((uint32_t)0x0UL) /**< CLKCN_X32K_EN_DIS Value */
-#define MXC_S_GCR_CLKCN_X32K_EN_DIS                                            \
-	(MXC_V_GCR_CLKCN_X32K_EN_DIS                                           \
-	 << MXC_F_GCR_CLKCN_X32K_EN_POS) /**< CLKCN_X32K_EN_DIS Setting */
-#define MXC_V_GCR_CLKCN_X32K_EN_EN                                             \
+#define MXC_S_GCR_CLKCN_X32K_EN_DIS                           \
+	(MXC_V_GCR_CLKCN_X32K_EN_DIS                          \
+	 << MXC_F_GCR_CLKCN_X32K_EN_POS) /**<                 \
+					    CLKCN_X32K_EN_DIS \
+					    Setting           \
+					  */
+#define MXC_V_GCR_CLKCN_X32K_EN_EN \
 	((uint32_t)0x1UL) /**< CLKCN_X32K_EN_EN Value */
-#define MXC_S_GCR_CLKCN_X32K_EN_EN                                             \
-	(MXC_V_GCR_CLKCN_X32K_EN_EN                                            \
-	 << MXC_F_GCR_CLKCN_X32K_EN_POS) /**< CLKCN_X32K_EN_EN Setting */
+#define MXC_S_GCR_CLKCN_X32K_EN_EN                           \
+	(MXC_V_GCR_CLKCN_X32K_EN_EN                          \
+	 << MXC_F_GCR_CLKCN_X32K_EN_POS) /**<                \
+					    CLKCN_X32K_EN_EN \
+					    Setting          \
+					  */
 
 #define MXC_F_GCR_CLKCN_HIRC_EN_POS 18 /**< CLKCN_HIRC_EN Position */
-#define MXC_F_GCR_CLKCN_HIRC_EN                                                \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_CLKCN_HIRC_EN_POS)) /**< CLKCN_HIRC_EN Mask */
-#define MXC_V_GCR_CLKCN_HIRC_EN_DIS                                            \
+#define MXC_F_GCR_CLKCN_HIRC_EN                                               \
+	((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC_EN_POS)) /**< CLKCN_HIRC_EN \
+							      Mask */
+#define MXC_V_GCR_CLKCN_HIRC_EN_DIS \
 	((uint32_t)0x0UL) /**< CLKCN_HIRC_EN_DIS Value */
-#define MXC_S_GCR_CLKCN_HIRC_EN_DIS                                            \
-	(MXC_V_GCR_CLKCN_HIRC_EN_DIS                                           \
-	 << MXC_F_GCR_CLKCN_HIRC_EN_POS) /**< CLKCN_HIRC_EN_DIS Setting */
-#define MXC_V_GCR_CLKCN_HIRC_EN_EN                                             \
+#define MXC_S_GCR_CLKCN_HIRC_EN_DIS                           \
+	(MXC_V_GCR_CLKCN_HIRC_EN_DIS                          \
+	 << MXC_F_GCR_CLKCN_HIRC_EN_POS) /**<                 \
+					    CLKCN_HIRC_EN_DIS \
+					    Setting           \
+					  */
+#define MXC_V_GCR_CLKCN_HIRC_EN_EN \
 	((uint32_t)0x1UL) /**< CLKCN_HIRC_EN_EN Value */
-#define MXC_S_GCR_CLKCN_HIRC_EN_EN                                             \
-	(MXC_V_GCR_CLKCN_HIRC_EN_EN                                            \
-	 << MXC_F_GCR_CLKCN_HIRC_EN_POS) /**< CLKCN_HIRC_EN_EN Setting */
+#define MXC_S_GCR_CLKCN_HIRC_EN_EN                           \
+	(MXC_V_GCR_CLKCN_HIRC_EN_EN                          \
+	 << MXC_F_GCR_CLKCN_HIRC_EN_POS) /**<                \
+					    CLKCN_HIRC_EN_EN \
+					    Setting          \
+					  */
 
 #define MXC_F_GCR_CLKCN_X32K_RDY_POS 25 /**< CLKCN_X32K_RDY Position */
-#define MXC_F_GCR_CLKCN_X32K_RDY                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_CLKCN_X32K_RDY_POS)) /**< CLKCN_X32K_RDY Mask */
-#define MXC_V_GCR_CLKCN_X32K_RDY_NOT                                           \
+#define MXC_F_GCR_CLKCN_X32K_RDY                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_X32K_RDY_POS)) /**<              \
+							       CLKCN_X32K_RDY \
+							       Mask */
+#define MXC_V_GCR_CLKCN_X32K_RDY_NOT \
 	((uint32_t)0x0UL) /**< CLKCN_X32K_RDY_NOT Value */
-#define MXC_S_GCR_CLKCN_X32K_RDY_NOT                                           \
-	(MXC_V_GCR_CLKCN_X32K_RDY_NOT                                          \
-	 << MXC_F_GCR_CLKCN_X32K_RDY_POS) /**< CLKCN_X32K_RDY_NOT Setting */
-#define MXC_V_GCR_CLKCN_X32K_RDY_READY                                         \
+#define MXC_S_GCR_CLKCN_X32K_RDY_NOT                            \
+	(MXC_V_GCR_CLKCN_X32K_RDY_NOT                           \
+	 << MXC_F_GCR_CLKCN_X32K_RDY_POS) /**<                  \
+					     CLKCN_X32K_RDY_NOT \
+					     Setting            \
+					   */
+#define MXC_V_GCR_CLKCN_X32K_RDY_READY \
 	((uint32_t)0x1UL) /**< CLKCN_X32K_RDY_READY Value */
-#define MXC_S_GCR_CLKCN_X32K_RDY_READY                                         \
-	(MXC_V_GCR_CLKCN_X32K_RDY_READY                                        \
-	 << MXC_F_GCR_CLKCN_X32K_RDY_POS) /**< CLKCN_X32K_RDY_READY Setting */
+#define MXC_S_GCR_CLKCN_X32K_RDY_READY                            \
+	(MXC_V_GCR_CLKCN_X32K_RDY_READY                           \
+	 << MXC_F_GCR_CLKCN_X32K_RDY_POS) /**<                    \
+					     CLKCN_X32K_RDY_READY \
+					     Setting              \
+					   */
 
 #define MXC_F_GCR_CLKCN_HIRC_RDY_POS 26 /**< CLKCN_HIRC_RDY Position */
-#define MXC_F_GCR_CLKCN_HIRC_RDY                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_CLKCN_HIRC_RDY_POS)) /**< CLKCN_HIRC_RDY Mask */
-#define MXC_V_GCR_CLKCN_HIRC_RDY_NOT                                           \
+#define MXC_F_GCR_CLKCN_HIRC_RDY                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC_RDY_POS)) /**<              \
+							       CLKCN_HIRC_RDY \
+							       Mask */
+#define MXC_V_GCR_CLKCN_HIRC_RDY_NOT \
 	((uint32_t)0x0UL) /**< CLKCN_HIRC_RDY_NOT Value */
-#define MXC_S_GCR_CLKCN_HIRC_RDY_NOT                                           \
-	(MXC_V_GCR_CLKCN_HIRC_RDY_NOT                                          \
-	 << MXC_F_GCR_CLKCN_HIRC_RDY_POS) /**< CLKCN_HIRC_RDY_NOT Setting */
-#define MXC_V_GCR_CLKCN_HIRC_RDY_READY                                         \
+#define MXC_S_GCR_CLKCN_HIRC_RDY_NOT                            \
+	(MXC_V_GCR_CLKCN_HIRC_RDY_NOT                           \
+	 << MXC_F_GCR_CLKCN_HIRC_RDY_POS) /**<                  \
+					     CLKCN_HIRC_RDY_NOT \
+					     Setting            \
+					   */
+#define MXC_V_GCR_CLKCN_HIRC_RDY_READY \
 	((uint32_t)0x1UL) /**< CLKCN_HIRC_RDY_READY Value */
-#define MXC_S_GCR_CLKCN_HIRC_RDY_READY                                         \
-	(MXC_V_GCR_CLKCN_HIRC_RDY_READY                                        \
-	 << MXC_F_GCR_CLKCN_HIRC_RDY_POS) /**< CLKCN_HIRC_RDY_READY Setting */
+#define MXC_S_GCR_CLKCN_HIRC_RDY_READY                            \
+	(MXC_V_GCR_CLKCN_HIRC_RDY_READY                           \
+	 << MXC_F_GCR_CLKCN_HIRC_RDY_POS) /**<                    \
+					     CLKCN_HIRC_RDY_READY \
+					     Setting              \
+					   */
 
 #define MXC_F_GCR_CLKCN_LIRC8K_RDY_POS 29 /**< CLKCN_LIRC8K_RDY Position */
-#define MXC_F_GCR_CLKCN_LIRC8K_RDY                                             \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS)) /**< CLKCN_LIRC8K_RDY  \
+#define MXC_F_GCR_CLKCN_LIRC8K_RDY                                            \
+	((uint32_t)(0x1UL                                                     \
+		    << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS)) /**< CLKCN_LIRC8K_RDY \
 							   Mask */
-#define MXC_V_GCR_CLKCN_LIRC8K_RDY_NOT                                         \
+#define MXC_V_GCR_CLKCN_LIRC8K_RDY_NOT \
 	((uint32_t)0x0UL) /**< CLKCN_LIRC8K_RDY_NOT Value */
-#define MXC_S_GCR_CLKCN_LIRC8K_RDY_NOT                                         \
-	(MXC_V_GCR_CLKCN_LIRC8K_RDY_NOT                                        \
-	 << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS) /**< CLKCN_LIRC8K_RDY_NOT Setting  \
+#define MXC_S_GCR_CLKCN_LIRC8K_RDY_NOT                                        \
+	(MXC_V_GCR_CLKCN_LIRC8K_RDY_NOT                                       \
+	 << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS) /**< CLKCN_LIRC8K_RDY_NOT Setting \
 					     */
-#define MXC_V_GCR_CLKCN_LIRC8K_RDY_READY                                       \
+#define MXC_V_GCR_CLKCN_LIRC8K_RDY_READY \
 	((uint32_t)0x1UL) /**< CLKCN_LIRC8K_RDY_READY Value */
-#define MXC_S_GCR_CLKCN_LIRC8K_RDY_READY                                       \
-	(MXC_V_GCR_CLKCN_LIRC8K_RDY_READY                                      \
-	 << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS) /**< CLKCN_LIRC8K_RDY_READY        \
+#define MXC_S_GCR_CLKCN_LIRC8K_RDY_READY                                \
+	(MXC_V_GCR_CLKCN_LIRC8K_RDY_READY                               \
+	 << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS) /**< CLKCN_LIRC8K_RDY_READY \
 					       Setting */
 
 /**
  * Power Management.
  */
 #define MXC_F_GCR_PM_MODE_POS 0 /**< PM_MODE Position */
-#define MXC_F_GCR_PM_MODE                                                      \
+#define MXC_F_GCR_PM_MODE \
 	((uint32_t)(0x7UL << MXC_F_GCR_PM_MODE_POS)) /**< PM_MODE Mask */
-#define MXC_V_GCR_PM_MODE_ACTIVE                                               \
-	((uint32_t)0x0UL) /**< PM_MODE_ACTIVE Value                            \
+#define MXC_V_GCR_PM_MODE_ACTIVE                    \
+	((uint32_t)0x0UL) /**< PM_MODE_ACTIVE Value \
 			   */
-#define MXC_S_GCR_PM_MODE_ACTIVE                                               \
-	(MXC_V_GCR_PM_MODE_ACTIVE                                              \
-	 << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_ACTIVE Setting */
-#define MXC_V_GCR_PM_MODE_SHUTDOWN                                             \
+#define MXC_S_GCR_PM_MODE_ACTIVE                                              \
+	(MXC_V_GCR_PM_MODE_ACTIVE << MXC_F_GCR_PM_MODE_POS) /**<              \
+							       PM_MODE_ACTIVE \
+							       Setting */
+#define MXC_V_GCR_PM_MODE_SHUTDOWN \
 	((uint32_t)0x3UL) /**< PM_MODE_SHUTDOWN Value */
-#define MXC_S_GCR_PM_MODE_SHUTDOWN                                             \
-	(MXC_V_GCR_PM_MODE_SHUTDOWN                                            \
-	 << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_SHUTDOWN Setting */
-#define MXC_V_GCR_PM_MODE_BACKUP                                               \
-	((uint32_t)0x4UL) /**< PM_MODE_BACKUP Value                            \
+#define MXC_S_GCR_PM_MODE_SHUTDOWN                     \
+	(MXC_V_GCR_PM_MODE_SHUTDOWN                    \
+	 << MXC_F_GCR_PM_MODE_POS) /**<                \
+				      PM_MODE_SHUTDOWN \
+				      Setting */
+#define MXC_V_GCR_PM_MODE_BACKUP                    \
+	((uint32_t)0x4UL) /**< PM_MODE_BACKUP Value \
 			   */
-#define MXC_S_GCR_PM_MODE_BACKUP                                               \
-	(MXC_V_GCR_PM_MODE_BACKUP                                              \
-	 << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_BACKUP Setting */
+#define MXC_S_GCR_PM_MODE_BACKUP                                              \
+	(MXC_V_GCR_PM_MODE_BACKUP << MXC_F_GCR_PM_MODE_POS) /**<              \
+							       PM_MODE_BACKUP \
+							       Setting */
 
 #define MXC_F_GCR_PM_GPIOWKEN_POS 4 /**< PM_GPIOWKEN Position */
 #define MXC_F_GCR_PM_GPIOWKEN                                                  \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_GCR_PM_GPIOWKEN_POS)) /**< PM_GPIOWKEN Mask */
-#define MXC_V_GCR_PM_GPIOWKEN_DIS                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_PM_GPIOWKEN_POS)) /**< PM_GPIOWKEN Mask \
+							  */
+#define MXC_V_GCR_PM_GPIOWKEN_DIS \
 	((uint32_t)0x0UL) /**< PM_GPIOWKEN_DIS Value */
-#define MXC_S_GCR_PM_GPIOWKEN_DIS                                              \
-	(MXC_V_GCR_PM_GPIOWKEN_DIS                                             \
-	 << MXC_F_GCR_PM_GPIOWKEN_POS) /**< PM_GPIOWKEN_DIS Setting */
-#define MXC_V_GCR_PM_GPIOWKEN_EN                                               \
-	((uint32_t)0x1UL) /**< PM_GPIOWKEN_EN Value                            \
+#define MXC_S_GCR_PM_GPIOWKEN_DIS                         \
+	(MXC_V_GCR_PM_GPIOWKEN_DIS                        \
+	 << MXC_F_GCR_PM_GPIOWKEN_POS) /**<               \
+					  PM_GPIOWKEN_DIS \
+					  Setting */
+#define MXC_V_GCR_PM_GPIOWKEN_EN                    \
+	((uint32_t)0x1UL) /**< PM_GPIOWKEN_EN Value \
 			   */
-#define MXC_S_GCR_PM_GPIOWKEN_EN                                               \
-	(MXC_V_GCR_PM_GPIOWKEN_EN                                              \
-	 << MXC_F_GCR_PM_GPIOWKEN_POS) /**< PM_GPIOWKEN_EN Setting */
+#define MXC_S_GCR_PM_GPIOWKEN_EN                         \
+	(MXC_V_GCR_PM_GPIOWKEN_EN                        \
+	 << MXC_F_GCR_PM_GPIOWKEN_POS) /**<              \
+					  PM_GPIOWKEN_EN \
+					  Setting */
 
 #define MXC_F_GCR_PM_RTCWKEN_POS 5 /**< PM_RTCWKEN Position */
-#define MXC_F_GCR_PM_RTCWKEN                                                   \
-	((uint32_t)(0x1UL << MXC_F_GCR_PM_RTCWKEN_POS)) /**< PM_RTCWKEN Mask   \
+#define MXC_F_GCR_PM_RTCWKEN                                                 \
+	((uint32_t)(0x1UL << MXC_F_GCR_PM_RTCWKEN_POS)) /**< PM_RTCWKEN Mask \
 							 */
-#define MXC_V_GCR_PM_RTCWKEN_DIS                                               \
-	((uint32_t)0x0UL) /**< PM_RTCWKEN_DIS Value                            \
+#define MXC_V_GCR_PM_RTCWKEN_DIS                    \
+	((uint32_t)0x0UL) /**< PM_RTCWKEN_DIS Value \
 			   */
-#define MXC_S_GCR_PM_RTCWKEN_DIS                                               \
-	(MXC_V_GCR_PM_RTCWKEN_DIS                                              \
-	 << MXC_F_GCR_PM_RTCWKEN_POS)		  /**< PM_RTCWKEN_DIS Setting */
+#define MXC_S_GCR_PM_RTCWKEN_DIS                        \
+	(MXC_V_GCR_PM_RTCWKEN_DIS                       \
+	 << MXC_F_GCR_PM_RTCWKEN_POS) /**<              \
+					 PM_RTCWKEN_DIS \
+					 Setting */
 #define MXC_V_GCR_PM_RTCWKEN_EN ((uint32_t)0x1UL) /**< PM_RTCWKEN_EN Value */
 #define MXC_S_GCR_PM_RTCWKEN_EN                                                \
-	(MXC_V_GCR_PM_RTCWKEN_EN                                               \
-	 << MXC_F_GCR_PM_RTCWKEN_POS) /**< PM_RTCWKEN_EN Setting */
+	(MXC_V_GCR_PM_RTCWKEN_EN << MXC_F_GCR_PM_RTCWKEN_POS) /**<             \
+								 PM_RTCWKEN_EN \
+								 Setting */
 
 #define MXC_F_GCR_PM_HIRCPD_POS 15 /**< PM_HIRCPD Position */
-#define MXC_F_GCR_PM_HIRCPD                                                    \
+#define MXC_F_GCR_PM_HIRCPD \
 	((uint32_t)(0x1UL << MXC_F_GCR_PM_HIRCPD_POS)) /**< PM_HIRCPD Mask */
-#define MXC_V_GCR_PM_HIRCPD_ACTIVE                                             \
+#define MXC_V_GCR_PM_HIRCPD_ACTIVE \
 	((uint32_t)0x0UL) /**< PM_HIRCPD_ACTIVE Value */
-#define MXC_S_GCR_PM_HIRCPD_ACTIVE                                             \
-	(MXC_V_GCR_PM_HIRCPD_ACTIVE                                            \
-	 << MXC_F_GCR_PM_HIRCPD_POS) /**< PM_HIRCPD_ACTIVE Setting */
-#define MXC_V_GCR_PM_HIRCPD_DEEPSLEEP                                          \
+#define MXC_S_GCR_PM_HIRCPD_ACTIVE                       \
+	(MXC_V_GCR_PM_HIRCPD_ACTIVE                      \
+	 << MXC_F_GCR_PM_HIRCPD_POS) /**<                \
+					PM_HIRCPD_ACTIVE \
+					Setting */
+#define MXC_V_GCR_PM_HIRCPD_DEEPSLEEP \
 	((uint32_t)0x1UL) /**< PM_HIRCPD_DEEPSLEEP Value */
-#define MXC_S_GCR_PM_HIRCPD_DEEPSLEEP                                          \
-	(MXC_V_GCR_PM_HIRCPD_DEEPSLEEP                                         \
-	 << MXC_F_GCR_PM_HIRCPD_POS) /**< PM_HIRCPD_DEEPSLEEP Setting */
+#define MXC_S_GCR_PM_HIRCPD_DEEPSLEEP                       \
+	(MXC_V_GCR_PM_HIRCPD_DEEPSLEEP                      \
+	 << MXC_F_GCR_PM_HIRCPD_POS) /**<                   \
+					PM_HIRCPD_DEEPSLEEP \
+					Setting             \
+				      */
 
 /**
  * Peripheral Clock Divider.
  */
 #define MXC_F_GCR_PCKDIV_AONCD_POS 0 /**< PCKDIV_AONCD Position */
-#define MXC_F_GCR_PCKDIV_AONCD                                                 \
-	((uint32_t)(0x3UL                                                      \
-		    << MXC_F_GCR_PCKDIV_AONCD_POS)) /**< PCKDIV_AONCD Mask */
-#define MXC_V_GCR_PCKDIV_AONCD_DIV_4                                           \
+#define MXC_F_GCR_PCKDIV_AONCD                                              \
+	((uint32_t)(0x3UL << MXC_F_GCR_PCKDIV_AONCD_POS)) /**< PCKDIV_AONCD \
+							     Mask */
+#define MXC_V_GCR_PCKDIV_AONCD_DIV_4 \
 	((uint32_t)0x0UL) /**< PCKDIV_AONCD_DIV_4 Value */
-#define MXC_S_GCR_PCKDIV_AONCD_DIV_4                                           \
-	(MXC_V_GCR_PCKDIV_AONCD_DIV_4                                          \
-	 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_4 Setting */
-#define MXC_V_GCR_PCKDIV_AONCD_DIV_8                                           \
+#define MXC_S_GCR_PCKDIV_AONCD_DIV_4                          \
+	(MXC_V_GCR_PCKDIV_AONCD_DIV_4                         \
+	 << MXC_F_GCR_PCKDIV_AONCD_POS) /**<                  \
+					   PCKDIV_AONCD_DIV_4 \
+					   Setting            \
+					 */
+#define MXC_V_GCR_PCKDIV_AONCD_DIV_8 \
 	((uint32_t)0x1UL) /**< PCKDIV_AONCD_DIV_8 Value */
-#define MXC_S_GCR_PCKDIV_AONCD_DIV_8                                           \
-	(MXC_V_GCR_PCKDIV_AONCD_DIV_8                                          \
-	 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_8 Setting */
-#define MXC_V_GCR_PCKDIV_AONCD_DIV_16                                          \
+#define MXC_S_GCR_PCKDIV_AONCD_DIV_8                          \
+	(MXC_V_GCR_PCKDIV_AONCD_DIV_8                         \
+	 << MXC_F_GCR_PCKDIV_AONCD_POS) /**<                  \
+					   PCKDIV_AONCD_DIV_8 \
+					   Setting            \
+					 */
+#define MXC_V_GCR_PCKDIV_AONCD_DIV_16 \
 	((uint32_t)0x2UL) /**< PCKDIV_AONCD_DIV_16 Value */
-#define MXC_S_GCR_PCKDIV_AONCD_DIV_16                                          \
-	(MXC_V_GCR_PCKDIV_AONCD_DIV_16                                         \
-	 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_16 Setting */
-#define MXC_V_GCR_PCKDIV_AONCD_DIV_32                                          \
+#define MXC_S_GCR_PCKDIV_AONCD_DIV_16                          \
+	(MXC_V_GCR_PCKDIV_AONCD_DIV_16                         \
+	 << MXC_F_GCR_PCKDIV_AONCD_POS) /**<                   \
+					   PCKDIV_AONCD_DIV_16 \
+					   Setting             \
+					 */
+#define MXC_V_GCR_PCKDIV_AONCD_DIV_32 \
 	((uint32_t)0x3UL) /**< PCKDIV_AONCD_DIV_32 Value */
-#define MXC_S_GCR_PCKDIV_AONCD_DIV_32                                          \
-	(MXC_V_GCR_PCKDIV_AONCD_DIV_32                                         \
-	 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_32 Setting */
+#define MXC_S_GCR_PCKDIV_AONCD_DIV_32                          \
+	(MXC_V_GCR_PCKDIV_AONCD_DIV_32                         \
+	 << MXC_F_GCR_PCKDIV_AONCD_POS) /**<                   \
+					   PCKDIV_AONCD_DIV_32 \
+					   Setting             \
+					 */
 
 /**
  * Peripheral Clock Disable.
  */
 #define MXC_F_GCR_PERCKCN0_GPIO0D_POS 0 /**< PERCKCN0_GPIO0D Position */
-#define MXC_F_GCR_PERCKCN0_GPIO0D                                              \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_GCR_PERCKCN0_GPIO0D_POS)) /**< PERCKCN0_GPIO0D  \
-							    Mask */
-#define MXC_V_GCR_PERCKCN0_GPIO0D_EN                                           \
+#define MXC_F_GCR_PERCKCN0_GPIO0D                                           \
+	((uint32_t)(0x1UL                                                   \
+		    << MXC_F_GCR_PERCKCN0_GPIO0D_POS)) /**< PERCKCN0_GPIO0D \
+							  Mask */
+#define MXC_V_GCR_PERCKCN0_GPIO0D_EN \
 	((uint32_t)0x0UL) /**< PERCKCN0_GPIO0D_EN Value */
-#define MXC_S_GCR_PERCKCN0_GPIO0D_EN                                           \
-	(MXC_V_GCR_PERCKCN0_GPIO0D_EN                                          \
-	 << MXC_F_GCR_PERCKCN0_GPIO0D_POS) /**< PERCKCN0_GPIO0D_EN Setting */
-#define MXC_V_GCR_PERCKCN0_GPIO0D_DIS                                          \
+#define MXC_S_GCR_PERCKCN0_GPIO0D_EN                             \
+	(MXC_V_GCR_PERCKCN0_GPIO0D_EN                            \
+	 << MXC_F_GCR_PERCKCN0_GPIO0D_POS) /**<                  \
+					      PERCKCN0_GPIO0D_EN \
+					      Setting            \
+					    */
+#define MXC_V_GCR_PERCKCN0_GPIO0D_DIS \
 	((uint32_t)0x1UL) /**< PERCKCN0_GPIO0D_DIS Value */
-#define MXC_S_GCR_PERCKCN0_GPIO0D_DIS                                          \
-	(MXC_V_GCR_PERCKCN0_GPIO0D_DIS                                         \
-	 << MXC_F_GCR_PERCKCN0_GPIO0D_POS) /**< PERCKCN0_GPIO0D_DIS Setting */
+#define MXC_S_GCR_PERCKCN0_GPIO0D_DIS                             \
+	(MXC_V_GCR_PERCKCN0_GPIO0D_DIS                            \
+	 << MXC_F_GCR_PERCKCN0_GPIO0D_POS) /**<                   \
+					      PERCKCN0_GPIO0D_DIS \
+					      Setting             \
+					    */
 
 #define MXC_F_GCR_PERCKCN0_DMAD_POS 5 /**< PERCKCN0_DMAD Position */
-#define MXC_F_GCR_PERCKCN0_DMAD                                                \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_PERCKCN0_DMAD_POS)) /**< PERCKCN0_DMAD Mask */
-#define MXC_V_GCR_PERCKCN0_DMAD_EN                                             \
+#define MXC_F_GCR_PERCKCN0_DMAD                                               \
+	((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_DMAD_POS)) /**< PERCKCN0_DMAD \
+							      Mask */
+#define MXC_V_GCR_PERCKCN0_DMAD_EN \
 	((uint32_t)0x0UL) /**< PERCKCN0_DMAD_EN Value */
-#define MXC_S_GCR_PERCKCN0_DMAD_EN                                             \
-	(MXC_V_GCR_PERCKCN0_DMAD_EN                                            \
-	 << MXC_F_GCR_PERCKCN0_DMAD_POS) /**< PERCKCN0_DMAD_EN Setting */
-#define MXC_V_GCR_PERCKCN0_DMAD_DIS                                            \
+#define MXC_S_GCR_PERCKCN0_DMAD_EN                           \
+	(MXC_V_GCR_PERCKCN0_DMAD_EN                          \
+	 << MXC_F_GCR_PERCKCN0_DMAD_POS) /**<                \
+					    PERCKCN0_DMAD_EN \
+					    Setting          \
+					  */
+#define MXC_V_GCR_PERCKCN0_DMAD_DIS \
 	((uint32_t)0x1UL) /**< PERCKCN0_DMAD_DIS Value */
-#define MXC_S_GCR_PERCKCN0_DMAD_DIS                                            \
-	(MXC_V_GCR_PERCKCN0_DMAD_DIS                                           \
-	 << MXC_F_GCR_PERCKCN0_DMAD_POS) /**< PERCKCN0_DMAD_DIS Setting */
+#define MXC_S_GCR_PERCKCN0_DMAD_DIS                           \
+	(MXC_V_GCR_PERCKCN0_DMAD_DIS                          \
+	 << MXC_F_GCR_PERCKCN0_DMAD_POS) /**<                 \
+					    PERCKCN0_DMAD_DIS \
+					    Setting           \
+					  */
 
 #define MXC_F_GCR_PERCKCN0_SPI0D_POS 6 /**< PERCKCN0_SPI0D Position */
-#define MXC_F_GCR_PERCKCN0_SPI0D                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_PERCKCN0_SPI0D_POS)) /**< PERCKCN0_SPI0D Mask */
-#define MXC_V_GCR_PERCKCN0_SPI0D_EN                                            \
+#define MXC_F_GCR_PERCKCN0_SPI0D                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_SPI0D_POS)) /**<              \
+							       PERCKCN0_SPI0D \
+							       Mask */
+#define MXC_V_GCR_PERCKCN0_SPI0D_EN \
 	((uint32_t)0x0UL) /**< PERCKCN0_SPI0D_EN Value */
-#define MXC_S_GCR_PERCKCN0_SPI0D_EN                                            \
-	(MXC_V_GCR_PERCKCN0_SPI0D_EN                                           \
-	 << MXC_F_GCR_PERCKCN0_SPI0D_POS) /**< PERCKCN0_SPI0D_EN Setting */
-#define MXC_V_GCR_PERCKCN0_SPI0D_DIS                                           \
+#define MXC_S_GCR_PERCKCN0_SPI0D_EN                            \
+	(MXC_V_GCR_PERCKCN0_SPI0D_EN                           \
+	 << MXC_F_GCR_PERCKCN0_SPI0D_POS) /**<                 \
+					     PERCKCN0_SPI0D_EN \
+					     Setting           \
+					   */
+#define MXC_V_GCR_PERCKCN0_SPI0D_DIS \
 	((uint32_t)0x1UL) /**< PERCKCN0_SPI0D_DIS Value */
-#define MXC_S_GCR_PERCKCN0_SPI0D_DIS                                           \
-	(MXC_V_GCR_PERCKCN0_SPI0D_DIS                                          \
-	 << MXC_F_GCR_PERCKCN0_SPI0D_POS) /**< PERCKCN0_SPI0D_DIS Setting */
+#define MXC_S_GCR_PERCKCN0_SPI0D_DIS                            \
+	(MXC_V_GCR_PERCKCN0_SPI0D_DIS                           \
+	 << MXC_F_GCR_PERCKCN0_SPI0D_POS) /**<                  \
+					     PERCKCN0_SPI0D_DIS \
+					     Setting            \
+					   */
 
 #define MXC_F_GCR_PERCKCN0_SPI1D_POS 7 /**< PERCKCN0_SPI1D Position */
-#define MXC_F_GCR_PERCKCN0_SPI1D                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_PERCKCN0_SPI1D_POS)) /**< PERCKCN0_SPI1D Mask */
-#define MXC_V_GCR_PERCKCN0_SPI1D_EN                                            \
+#define MXC_F_GCR_PERCKCN0_SPI1D                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_SPI1D_POS)) /**<              \
+							       PERCKCN0_SPI1D \
+							       Mask */
+#define MXC_V_GCR_PERCKCN0_SPI1D_EN \
 	((uint32_t)0x0UL) /**< PERCKCN0_SPI1D_EN Value */
-#define MXC_S_GCR_PERCKCN0_SPI1D_EN                                            \
-	(MXC_V_GCR_PERCKCN0_SPI1D_EN                                           \
-	 << MXC_F_GCR_PERCKCN0_SPI1D_POS) /**< PERCKCN0_SPI1D_EN Setting */
-#define MXC_V_GCR_PERCKCN0_SPI1D_DIS                                           \
+#define MXC_S_GCR_PERCKCN0_SPI1D_EN                            \
+	(MXC_V_GCR_PERCKCN0_SPI1D_EN                           \
+	 << MXC_F_GCR_PERCKCN0_SPI1D_POS) /**<                 \
+					     PERCKCN0_SPI1D_EN \
+					     Setting           \
+					   */
+#define MXC_V_GCR_PERCKCN0_SPI1D_DIS \
 	((uint32_t)0x1UL) /**< PERCKCN0_SPI1D_DIS Value */
-#define MXC_S_GCR_PERCKCN0_SPI1D_DIS                                           \
-	(MXC_V_GCR_PERCKCN0_SPI1D_DIS                                          \
-	 << MXC_F_GCR_PERCKCN0_SPI1D_POS) /**< PERCKCN0_SPI1D_DIS Setting */
+#define MXC_S_GCR_PERCKCN0_SPI1D_DIS                            \
+	(MXC_V_GCR_PERCKCN0_SPI1D_DIS                           \
+	 << MXC_F_GCR_PERCKCN0_SPI1D_POS) /**<                  \
+					     PERCKCN0_SPI1D_DIS \
+					     Setting            \
+					   */
 
 #define MXC_F_GCR_PERCKCN0_UART0D_POS 9 /**< PERCKCN0_UART0D Position */
-#define MXC_F_GCR_PERCKCN0_UART0D                                              \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_GCR_PERCKCN0_UART0D_POS)) /**< PERCKCN0_UART0D  \
-							    Mask */
-#define MXC_V_GCR_PERCKCN0_UART0D_EN                                           \
+#define MXC_F_GCR_PERCKCN0_UART0D                                           \
+	((uint32_t)(0x1UL                                                   \
+		    << MXC_F_GCR_PERCKCN0_UART0D_POS)) /**< PERCKCN0_UART0D \
+							  Mask */
+#define MXC_V_GCR_PERCKCN0_UART0D_EN \
 	((uint32_t)0x0UL) /**< PERCKCN0_UART0D_EN Value */
-#define MXC_S_GCR_PERCKCN0_UART0D_EN                                           \
-	(MXC_V_GCR_PERCKCN0_UART0D_EN                                          \
-	 << MXC_F_GCR_PERCKCN0_UART0D_POS) /**< PERCKCN0_UART0D_EN Setting */
-#define MXC_V_GCR_PERCKCN0_UART0D_DIS                                          \
+#define MXC_S_GCR_PERCKCN0_UART0D_EN                             \
+	(MXC_V_GCR_PERCKCN0_UART0D_EN                            \
+	 << MXC_F_GCR_PERCKCN0_UART0D_POS) /**<                  \
+					      PERCKCN0_UART0D_EN \
+					      Setting            \
+					    */
+#define MXC_V_GCR_PERCKCN0_UART0D_DIS \
 	((uint32_t)0x1UL) /**< PERCKCN0_UART0D_DIS Value */
-#define MXC_S_GCR_PERCKCN0_UART0D_DIS                                          \
-	(MXC_V_GCR_PERCKCN0_UART0D_DIS                                         \
-	 << MXC_F_GCR_PERCKCN0_UART0D_POS) /**< PERCKCN0_UART0D_DIS Setting */
+#define MXC_S_GCR_PERCKCN0_UART0D_DIS                             \
+	(MXC_V_GCR_PERCKCN0_UART0D_DIS                            \
+	 << MXC_F_GCR_PERCKCN0_UART0D_POS) /**<                   \
+					      PERCKCN0_UART0D_DIS \
+					      Setting             \
+					    */
 
 #define MXC_F_GCR_PERCKCN0_UART1D_POS 10 /**< PERCKCN0_UART1D Position */
-#define MXC_F_GCR_PERCKCN0_UART1D                                              \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_GCR_PERCKCN0_UART1D_POS)) /**< PERCKCN0_UART1D  \
-							    Mask */
-#define MXC_V_GCR_PERCKCN0_UART1D_EN                                           \
+#define MXC_F_GCR_PERCKCN0_UART1D                                           \
+	((uint32_t)(0x1UL                                                   \
+		    << MXC_F_GCR_PERCKCN0_UART1D_POS)) /**< PERCKCN0_UART1D \
+							  Mask */
+#define MXC_V_GCR_PERCKCN0_UART1D_EN \
 	((uint32_t)0x0UL) /**< PERCKCN0_UART1D_EN Value */
-#define MXC_S_GCR_PERCKCN0_UART1D_EN                                           \
-	(MXC_V_GCR_PERCKCN0_UART1D_EN                                          \
-	 << MXC_F_GCR_PERCKCN0_UART1D_POS) /**< PERCKCN0_UART1D_EN Setting */
-#define MXC_V_GCR_PERCKCN0_UART1D_DIS                                          \
+#define MXC_S_GCR_PERCKCN0_UART1D_EN                             \
+	(MXC_V_GCR_PERCKCN0_UART1D_EN                            \
+	 << MXC_F_GCR_PERCKCN0_UART1D_POS) /**<                  \
+					      PERCKCN0_UART1D_EN \
+					      Setting            \
+					    */
+#define MXC_V_GCR_PERCKCN0_UART1D_DIS \
 	((uint32_t)0x1UL) /**< PERCKCN0_UART1D_DIS Value */
-#define MXC_S_GCR_PERCKCN0_UART1D_DIS                                          \
-	(MXC_V_GCR_PERCKCN0_UART1D_DIS                                         \
-	 << MXC_F_GCR_PERCKCN0_UART1D_POS) /**< PERCKCN0_UART1D_DIS Setting */
+#define MXC_S_GCR_PERCKCN0_UART1D_DIS                             \
+	(MXC_V_GCR_PERCKCN0_UART1D_DIS                            \
+	 << MXC_F_GCR_PERCKCN0_UART1D_POS) /**<                   \
+					      PERCKCN0_UART1D_DIS \
+					      Setting             \
+					    */
 
 #define MXC_F_GCR_PERCKCN0_I2C0D_POS 13 /**< PERCKCN0_I2C0D Position */
-#define MXC_F_GCR_PERCKCN0_I2C0D                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_PERCKCN0_I2C0D_POS)) /**< PERCKCN0_I2C0D Mask */
-#define MXC_V_GCR_PERCKCN0_I2C0D_EN                                            \
+#define MXC_F_GCR_PERCKCN0_I2C0D                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_I2C0D_POS)) /**<              \
+							       PERCKCN0_I2C0D \
+							       Mask */
+#define MXC_V_GCR_PERCKCN0_I2C0D_EN \
 	((uint32_t)0x0UL) /**< PERCKCN0_I2C0D_EN Value */
-#define MXC_S_GCR_PERCKCN0_I2C0D_EN                                            \
-	(MXC_V_GCR_PERCKCN0_I2C0D_EN                                           \
-	 << MXC_F_GCR_PERCKCN0_I2C0D_POS) /**< PERCKCN0_I2C0D_EN Setting */
-#define MXC_V_GCR_PERCKCN0_I2C0D_DIS                                           \
+#define MXC_S_GCR_PERCKCN0_I2C0D_EN                            \
+	(MXC_V_GCR_PERCKCN0_I2C0D_EN                           \
+	 << MXC_F_GCR_PERCKCN0_I2C0D_POS) /**<                 \
+					     PERCKCN0_I2C0D_EN \
+					     Setting           \
+					   */
+#define MXC_V_GCR_PERCKCN0_I2C0D_DIS \
 	((uint32_t)0x1UL) /**< PERCKCN0_I2C0D_DIS Value */
-#define MXC_S_GCR_PERCKCN0_I2C0D_DIS                                           \
-	(MXC_V_GCR_PERCKCN0_I2C0D_DIS                                          \
-	 << MXC_F_GCR_PERCKCN0_I2C0D_POS) /**< PERCKCN0_I2C0D_DIS Setting */
+#define MXC_S_GCR_PERCKCN0_I2C0D_DIS                            \
+	(MXC_V_GCR_PERCKCN0_I2C0D_DIS                           \
+	 << MXC_F_GCR_PERCKCN0_I2C0D_POS) /**<                  \
+					     PERCKCN0_I2C0D_DIS \
+					     Setting            \
+					   */
 
 #define MXC_F_GCR_PERCKCN0_T0D_POS 15 /**< PERCKCN0_T0D Position */
-#define MXC_F_GCR_PERCKCN0_T0D                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_PERCKCN0_T0D_POS)) /**< PERCKCN0_T0D Mask */
-#define MXC_V_GCR_PERCKCN0_T0D_EN                                              \
+#define MXC_F_GCR_PERCKCN0_T0D                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T0D_POS)) /**< PERCKCN0_T0D \
+							     Mask */
+#define MXC_V_GCR_PERCKCN0_T0D_EN \
 	((uint32_t)0x0UL) /**< PERCKCN0_T0D_EN Value */
-#define MXC_S_GCR_PERCKCN0_T0D_EN                                              \
-	(MXC_V_GCR_PERCKCN0_T0D_EN                                             \
-	 << MXC_F_GCR_PERCKCN0_T0D_POS) /**< PERCKCN0_T0D_EN Setting */
-#define MXC_V_GCR_PERCKCN0_T0D_DIS                                             \
+#define MXC_S_GCR_PERCKCN0_T0D_EN                          \
+	(MXC_V_GCR_PERCKCN0_T0D_EN                         \
+	 << MXC_F_GCR_PERCKCN0_T0D_POS) /**<               \
+					   PERCKCN0_T0D_EN \
+					   Setting         \
+					 */
+#define MXC_V_GCR_PERCKCN0_T0D_DIS \
 	((uint32_t)0x1UL) /**< PERCKCN0_T0D_DIS Value */
-#define MXC_S_GCR_PERCKCN0_T0D_DIS                                             \
-	(MXC_V_GCR_PERCKCN0_T0D_DIS                                            \
-	 << MXC_F_GCR_PERCKCN0_T0D_POS) /**< PERCKCN0_T0D_DIS Setting */
+#define MXC_S_GCR_PERCKCN0_T0D_DIS                          \
+	(MXC_V_GCR_PERCKCN0_T0D_DIS                         \
+	 << MXC_F_GCR_PERCKCN0_T0D_POS) /**<                \
+					   PERCKCN0_T0D_DIS \
+					   Setting          \
+					 */
 
 #define MXC_F_GCR_PERCKCN0_T1D_POS 16 /**< PERCKCN0_T1D Position */
-#define MXC_F_GCR_PERCKCN0_T1D                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_PERCKCN0_T1D_POS)) /**< PERCKCN0_T1D Mask */
-#define MXC_V_GCR_PERCKCN0_T1D_EN                                              \
+#define MXC_F_GCR_PERCKCN0_T1D                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T1D_POS)) /**< PERCKCN0_T1D \
+							     Mask */
+#define MXC_V_GCR_PERCKCN0_T1D_EN \
 	((uint32_t)0x0UL) /**< PERCKCN0_T1D_EN Value */
-#define MXC_S_GCR_PERCKCN0_T1D_EN                                              \
-	(MXC_V_GCR_PERCKCN0_T1D_EN                                             \
-	 << MXC_F_GCR_PERCKCN0_T1D_POS) /**< PERCKCN0_T1D_EN Setting */
-#define MXC_V_GCR_PERCKCN0_T1D_DIS                                             \
+#define MXC_S_GCR_PERCKCN0_T1D_EN                          \
+	(MXC_V_GCR_PERCKCN0_T1D_EN                         \
+	 << MXC_F_GCR_PERCKCN0_T1D_POS) /**<               \
+					   PERCKCN0_T1D_EN \
+					   Setting         \
+					 */
+#define MXC_V_GCR_PERCKCN0_T1D_DIS \
 	((uint32_t)0x1UL) /**< PERCKCN0_T1D_DIS Value */
-#define MXC_S_GCR_PERCKCN0_T1D_DIS                                             \
-	(MXC_V_GCR_PERCKCN0_T1D_DIS                                            \
-	 << MXC_F_GCR_PERCKCN0_T1D_POS) /**< PERCKCN0_T1D_DIS Setting */
+#define MXC_S_GCR_PERCKCN0_T1D_DIS                          \
+	(MXC_V_GCR_PERCKCN0_T1D_DIS                         \
+	 << MXC_F_GCR_PERCKCN0_T1D_POS) /**<                \
+					   PERCKCN0_T1D_DIS \
+					   Setting          \
+					 */
 
 #define MXC_F_GCR_PERCKCN0_T2D_POS 17 /**< PERCKCN0_T2D Position */
-#define MXC_F_GCR_PERCKCN0_T2D                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_PERCKCN0_T2D_POS)) /**< PERCKCN0_T2D Mask */
-#define MXC_V_GCR_PERCKCN0_T2D_EN                                              \
+#define MXC_F_GCR_PERCKCN0_T2D                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T2D_POS)) /**< PERCKCN0_T2D \
+							     Mask */
+#define MXC_V_GCR_PERCKCN0_T2D_EN \
 	((uint32_t)0x0UL) /**< PERCKCN0_T2D_EN Value */
-#define MXC_S_GCR_PERCKCN0_T2D_EN                                              \
-	(MXC_V_GCR_PERCKCN0_T2D_EN                                             \
-	 << MXC_F_GCR_PERCKCN0_T2D_POS) /**< PERCKCN0_T2D_EN Setting */
-#define MXC_V_GCR_PERCKCN0_T2D_DIS                                             \
+#define MXC_S_GCR_PERCKCN0_T2D_EN                          \
+	(MXC_V_GCR_PERCKCN0_T2D_EN                         \
+	 << MXC_F_GCR_PERCKCN0_T2D_POS) /**<               \
+					   PERCKCN0_T2D_EN \
+					   Setting         \
+					 */
+#define MXC_V_GCR_PERCKCN0_T2D_DIS \
 	((uint32_t)0x1UL) /**< PERCKCN0_T2D_DIS Value */
-#define MXC_S_GCR_PERCKCN0_T2D_DIS                                             \
-	(MXC_V_GCR_PERCKCN0_T2D_DIS                                            \
-	 << MXC_F_GCR_PERCKCN0_T2D_POS) /**< PERCKCN0_T2D_DIS Setting */
+#define MXC_S_GCR_PERCKCN0_T2D_DIS                          \
+	(MXC_V_GCR_PERCKCN0_T2D_DIS                         \
+	 << MXC_F_GCR_PERCKCN0_T2D_POS) /**<                \
+					   PERCKCN0_T2D_DIS \
+					   Setting          \
+					 */
 
 #define MXC_F_GCR_PERCKCN0_I2C1D_POS 28 /**< PERCKCN0_I2C1D Position */
-#define MXC_F_GCR_PERCKCN0_I2C1D                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_PERCKCN0_I2C1D_POS)) /**< PERCKCN0_I2C1D Mask */
-#define MXC_V_GCR_PERCKCN0_I2C1D_EN                                            \
+#define MXC_F_GCR_PERCKCN0_I2C1D                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_I2C1D_POS)) /**<              \
+							       PERCKCN0_I2C1D \
+							       Mask */
+#define MXC_V_GCR_PERCKCN0_I2C1D_EN \
 	((uint32_t)0x0UL) /**< PERCKCN0_I2C1D_EN Value */
-#define MXC_S_GCR_PERCKCN0_I2C1D_EN                                            \
-	(MXC_V_GCR_PERCKCN0_I2C1D_EN                                           \
-	 << MXC_F_GCR_PERCKCN0_I2C1D_POS) /**< PERCKCN0_I2C1D_EN Setting */
-#define MXC_V_GCR_PERCKCN0_I2C1D_DIS                                           \
+#define MXC_S_GCR_PERCKCN0_I2C1D_EN                            \
+	(MXC_V_GCR_PERCKCN0_I2C1D_EN                           \
+	 << MXC_F_GCR_PERCKCN0_I2C1D_POS) /**<                 \
+					     PERCKCN0_I2C1D_EN \
+					     Setting           \
+					   */
+#define MXC_V_GCR_PERCKCN0_I2C1D_DIS \
 	((uint32_t)0x1UL) /**< PERCKCN0_I2C1D_DIS Value */
-#define MXC_S_GCR_PERCKCN0_I2C1D_DIS                                           \
-	(MXC_V_GCR_PERCKCN0_I2C1D_DIS                                          \
-	 << MXC_F_GCR_PERCKCN0_I2C1D_POS) /**< PERCKCN0_I2C1D_DIS Setting */
+#define MXC_S_GCR_PERCKCN0_I2C1D_DIS                            \
+	(MXC_V_GCR_PERCKCN0_I2C1D_DIS                           \
+	 << MXC_F_GCR_PERCKCN0_I2C1D_POS) /**<                  \
+					     PERCKCN0_I2C1D_DIS \
+					     Setting            \
+					   */
 
 /**
  * Memory Clock Control Register.
  */
 #define MXC_F_GCR_MEMCKCN_FWS_POS 0 /**< MEMCKCN_FWS Position */
 #define MXC_F_GCR_MEMCKCN_FWS                                                  \
-	((uint32_t)(                                                           \
-		0x7UL << MXC_F_GCR_MEMCKCN_FWS_POS)) /**< MEMCKCN_FWS Mask */
+	((uint32_t)(0x7UL << MXC_F_GCR_MEMCKCN_FWS_POS)) /**< MEMCKCN_FWS Mask \
+							  */
 
 #define MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS 8 /**< MEMCKCN_SYSRAM0LS Position */
-#define MXC_F_GCR_MEMCKCN_SYSRAM0LS                                            \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS)) /**< MEMCKCN_SYSRAM0LS    \
-							Mask */
-#define MXC_V_GCR_MEMCKCN_SYSRAM0LS_ACTIVE                                     \
+#define MXC_F_GCR_MEMCKCN_SYSRAM0LS                                           \
+	((uint32_t)(0x1UL                                                     \
+		    << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS)) /**<                 \
+							    MEMCKCN_SYSRAM0LS \
+							    Mask */
+#define MXC_V_GCR_MEMCKCN_SYSRAM0LS_ACTIVE \
 	((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM0LS_ACTIVE Value */
-#define MXC_S_GCR_MEMCKCN_SYSRAM0LS_ACTIVE                                     \
-	(MXC_V_GCR_MEMCKCN_SYSRAM0LS_ACTIVE                                    \
-	 << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS) /**< MEMCKCN_SYSRAM0LS_ACTIVE     \
+#define MXC_S_GCR_MEMCKCN_SYSRAM0LS_ACTIVE                                 \
+	(MXC_V_GCR_MEMCKCN_SYSRAM0LS_ACTIVE                                \
+	 << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS) /**< MEMCKCN_SYSRAM0LS_ACTIVE \
 						Setting */
-#define MXC_V_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP                                \
+#define MXC_V_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP \
 	((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM0LS_LIGHT_SLEEP Value */
-#define MXC_S_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP                                \
-	(MXC_V_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP                               \
-	 << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS) /**<                              \
-						MEMCKCN_SYSRAM0LS_LIGHT_SLEEP  \
+#define MXC_S_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP                               \
+	(MXC_V_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP                              \
+	 << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS) /**<                             \
+						MEMCKCN_SYSRAM0LS_LIGHT_SLEEP \
 						Setting */
 
 #define MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS 9 /**< MEMCKCN_SYSRAM1LS Position */
-#define MXC_F_GCR_MEMCKCN_SYSRAM1LS                                            \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS)) /**< MEMCKCN_SYSRAM1LS    \
-							Mask */
-#define MXC_V_GCR_MEMCKCN_SYSRAM1LS_ACTIVE                                     \
+#define MXC_F_GCR_MEMCKCN_SYSRAM1LS                                           \
+	((uint32_t)(0x1UL                                                     \
+		    << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS)) /**<                 \
+							    MEMCKCN_SYSRAM1LS \
+							    Mask */
+#define MXC_V_GCR_MEMCKCN_SYSRAM1LS_ACTIVE \
 	((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM1LS_ACTIVE Value */
-#define MXC_S_GCR_MEMCKCN_SYSRAM1LS_ACTIVE                                     \
-	(MXC_V_GCR_MEMCKCN_SYSRAM1LS_ACTIVE                                    \
-	 << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS) /**< MEMCKCN_SYSRAM1LS_ACTIVE     \
+#define MXC_S_GCR_MEMCKCN_SYSRAM1LS_ACTIVE                                 \
+	(MXC_V_GCR_MEMCKCN_SYSRAM1LS_ACTIVE                                \
+	 << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS) /**< MEMCKCN_SYSRAM1LS_ACTIVE \
 						Setting */
-#define MXC_V_GCR_MEMCKCN_SYSRAM1LS_LIGHT_SLEEP                                \
+#define MXC_V_GCR_MEMCKCN_SYSRAM1LS_LIGHT_SLEEP \
 	((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM1LS_LIGHT_SLEEP Value */
-#define MXC_S_GCR_MEMCKCN_SYSRAM1LS_LIGHT_SLEEP                                \
-	(MXC_V_GCR_MEMCKCN_SYSRAM1LS_LIGHT_SLEEP                               \
-	 << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS) /**<                              \
-						MEMCKCN_SYSRAM1LS_LIGHT_SLEEP  \
+#define MXC_S_GCR_MEMCKCN_SYSRAM1LS_LIGHT_SLEEP                               \
+	(MXC_V_GCR_MEMCKCN_SYSRAM1LS_LIGHT_SLEEP                              \
+	 << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS) /**<                             \
+						MEMCKCN_SYSRAM1LS_LIGHT_SLEEP \
 						Setting */
 
 #define MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS 10 /**< MEMCKCN_SYSRAM2LS Position */
-#define MXC_F_GCR_MEMCKCN_SYSRAM2LS                                            \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS)) /**< MEMCKCN_SYSRAM2LS    \
-							Mask */
-#define MXC_V_GCR_MEMCKCN_SYSRAM2LS_ACTIVE                                     \
+#define MXC_F_GCR_MEMCKCN_SYSRAM2LS                                           \
+	((uint32_t)(0x1UL                                                     \
+		    << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS)) /**<                 \
+							    MEMCKCN_SYSRAM2LS \
+							    Mask */
+#define MXC_V_GCR_MEMCKCN_SYSRAM2LS_ACTIVE \
 	((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM2LS_ACTIVE Value */
-#define MXC_S_GCR_MEMCKCN_SYSRAM2LS_ACTIVE                                     \
-	(MXC_V_GCR_MEMCKCN_SYSRAM2LS_ACTIVE                                    \
-	 << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS) /**< MEMCKCN_SYSRAM2LS_ACTIVE     \
+#define MXC_S_GCR_MEMCKCN_SYSRAM2LS_ACTIVE                                 \
+	(MXC_V_GCR_MEMCKCN_SYSRAM2LS_ACTIVE                                \
+	 << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS) /**< MEMCKCN_SYSRAM2LS_ACTIVE \
 						Setting */
-#define MXC_V_GCR_MEMCKCN_SYSRAM2LS_LIGHT_SLEEP                                \
+#define MXC_V_GCR_MEMCKCN_SYSRAM2LS_LIGHT_SLEEP \
 	((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM2LS_LIGHT_SLEEP Value */
-#define MXC_S_GCR_MEMCKCN_SYSRAM2LS_LIGHT_SLEEP                                \
-	(MXC_V_GCR_MEMCKCN_SYSRAM2LS_LIGHT_SLEEP                               \
-	 << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS) /**<                              \
-						MEMCKCN_SYSRAM2LS_LIGHT_SLEEP  \
+#define MXC_S_GCR_MEMCKCN_SYSRAM2LS_LIGHT_SLEEP                               \
+	(MXC_V_GCR_MEMCKCN_SYSRAM2LS_LIGHT_SLEEP                              \
+	 << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS) /**<                             \
+						MEMCKCN_SYSRAM2LS_LIGHT_SLEEP \
 						Setting */
 
 #define MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS 11 /**< MEMCKCN_SYSRAM3LS Position */
-#define MXC_F_GCR_MEMCKCN_SYSRAM3LS                                            \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS)) /**< MEMCKCN_SYSRAM3LS    \
-							Mask */
-#define MXC_V_GCR_MEMCKCN_SYSRAM3LS_ACTIVE                                     \
+#define MXC_F_GCR_MEMCKCN_SYSRAM3LS                                           \
+	((uint32_t)(0x1UL                                                     \
+		    << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS)) /**<                 \
+							    MEMCKCN_SYSRAM3LS \
+							    Mask */
+#define MXC_V_GCR_MEMCKCN_SYSRAM3LS_ACTIVE \
 	((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM3LS_ACTIVE Value */
-#define MXC_S_GCR_MEMCKCN_SYSRAM3LS_ACTIVE                                     \
-	(MXC_V_GCR_MEMCKCN_SYSRAM3LS_ACTIVE                                    \
-	 << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS) /**< MEMCKCN_SYSRAM3LS_ACTIVE     \
+#define MXC_S_GCR_MEMCKCN_SYSRAM3LS_ACTIVE                                 \
+	(MXC_V_GCR_MEMCKCN_SYSRAM3LS_ACTIVE                                \
+	 << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS) /**< MEMCKCN_SYSRAM3LS_ACTIVE \
 						Setting */
-#define MXC_V_GCR_MEMCKCN_SYSRAM3LS_LIGHT_SLEEP                                \
+#define MXC_V_GCR_MEMCKCN_SYSRAM3LS_LIGHT_SLEEP \
 	((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM3LS_LIGHT_SLEEP Value */
-#define MXC_S_GCR_MEMCKCN_SYSRAM3LS_LIGHT_SLEEP                                \
-	(MXC_V_GCR_MEMCKCN_SYSRAM3LS_LIGHT_SLEEP                               \
-	 << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS) /**<                              \
-						MEMCKCN_SYSRAM3LS_LIGHT_SLEEP  \
+#define MXC_S_GCR_MEMCKCN_SYSRAM3LS_LIGHT_SLEEP                               \
+	(MXC_V_GCR_MEMCKCN_SYSRAM3LS_LIGHT_SLEEP                              \
+	 << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS) /**<                             \
+						MEMCKCN_SYSRAM3LS_LIGHT_SLEEP \
 						Setting */
 
 #define MXC_F_GCR_MEMCKCN_ICACHELS_POS 12 /**< MEMCKCN_ICACHELS Position */
-#define MXC_F_GCR_MEMCKCN_ICACHELS                                             \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_MEMCKCN_ICACHELS_POS)) /**< MEMCKCN_ICACHELS  \
+#define MXC_F_GCR_MEMCKCN_ICACHELS                                            \
+	((uint32_t)(0x1UL                                                     \
+		    << MXC_F_GCR_MEMCKCN_ICACHELS_POS)) /**< MEMCKCN_ICACHELS \
 							   Mask */
-#define MXC_V_GCR_MEMCKCN_ICACHELS_ACTIVE                                      \
+#define MXC_V_GCR_MEMCKCN_ICACHELS_ACTIVE \
 	((uint32_t)0x0UL) /**< MEMCKCN_ICACHELS_ACTIVE Value */
-#define MXC_S_GCR_MEMCKCN_ICACHELS_ACTIVE                                      \
-	(MXC_V_GCR_MEMCKCN_ICACHELS_ACTIVE                                     \
-	 << MXC_F_GCR_MEMCKCN_ICACHELS_POS) /**< MEMCKCN_ICACHELS_ACTIVE       \
+#define MXC_S_GCR_MEMCKCN_ICACHELS_ACTIVE                                \
+	(MXC_V_GCR_MEMCKCN_ICACHELS_ACTIVE                               \
+	 << MXC_F_GCR_MEMCKCN_ICACHELS_POS) /**< MEMCKCN_ICACHELS_ACTIVE \
 					       Setting */
-#define MXC_V_GCR_MEMCKCN_ICACHELS_LIGHT_SLEEP                                 \
+#define MXC_V_GCR_MEMCKCN_ICACHELS_LIGHT_SLEEP \
 	((uint32_t)0x1UL) /**< MEMCKCN_ICACHELS_LIGHT_SLEEP Value */
-#define MXC_S_GCR_MEMCKCN_ICACHELS_LIGHT_SLEEP                                 \
-	(MXC_V_GCR_MEMCKCN_ICACHELS_LIGHT_SLEEP                                \
-	 << MXC_F_GCR_MEMCKCN_ICACHELS_POS) /**< MEMCKCN_ICACHELS_LIGHT_SLEEP  \
+#define MXC_S_GCR_MEMCKCN_ICACHELS_LIGHT_SLEEP                                \
+	(MXC_V_GCR_MEMCKCN_ICACHELS_LIGHT_SLEEP                               \
+	 << MXC_F_GCR_MEMCKCN_ICACHELS_POS) /**< MEMCKCN_ICACHELS_LIGHT_SLEEP \
 					       Setting */
 
 /**
  * Memory Zeroize Control.
  */
 #define MXC_F_GCR_MEMZCN_SRAM0Z_POS 0 /**< MEMZCN_SRAM0Z Position */
-#define MXC_F_GCR_MEMZCN_SRAM0Z                                                \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_MEMZCN_SRAM0Z_POS)) /**< MEMZCN_SRAM0Z Mask */
-#define MXC_V_GCR_MEMZCN_SRAM0Z_NOP                                            \
+#define MXC_F_GCR_MEMZCN_SRAM0Z                                               \
+	((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SRAM0Z_POS)) /**< MEMZCN_SRAM0Z \
+							      Mask */
+#define MXC_V_GCR_MEMZCN_SRAM0Z_NOP \
 	((uint32_t)0x0UL) /**< MEMZCN_SRAM0Z_NOP Value */
-#define MXC_S_GCR_MEMZCN_SRAM0Z_NOP                                            \
-	(MXC_V_GCR_MEMZCN_SRAM0Z_NOP                                           \
-	 << MXC_F_GCR_MEMZCN_SRAM0Z_POS) /**< MEMZCN_SRAM0Z_NOP Setting */
-#define MXC_V_GCR_MEMZCN_SRAM0Z_START                                          \
+#define MXC_S_GCR_MEMZCN_SRAM0Z_NOP                           \
+	(MXC_V_GCR_MEMZCN_SRAM0Z_NOP                          \
+	 << MXC_F_GCR_MEMZCN_SRAM0Z_POS) /**<                 \
+					    MEMZCN_SRAM0Z_NOP \
+					    Setting           \
+					  */
+#define MXC_V_GCR_MEMZCN_SRAM0Z_START \
 	((uint32_t)0x1UL) /**< MEMZCN_SRAM0Z_START Value */
-#define MXC_S_GCR_MEMZCN_SRAM0Z_START                                          \
-	(MXC_V_GCR_MEMZCN_SRAM0Z_START                                         \
-	 << MXC_F_GCR_MEMZCN_SRAM0Z_POS) /**< MEMZCN_SRAM0Z_START Setting */
+#define MXC_S_GCR_MEMZCN_SRAM0Z_START                           \
+	(MXC_V_GCR_MEMZCN_SRAM0Z_START                          \
+	 << MXC_F_GCR_MEMZCN_SRAM0Z_POS) /**<                   \
+					    MEMZCN_SRAM0Z_START \
+					    Setting             \
+					  */
 
 #define MXC_F_GCR_MEMZCN_ICACHEZ_POS 1 /**< MEMZCN_ICACHEZ Position */
-#define MXC_F_GCR_MEMZCN_ICACHEZ                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_MEMZCN_ICACHEZ_POS)) /**< MEMZCN_ICACHEZ Mask */
-#define MXC_V_GCR_MEMZCN_ICACHEZ_NOP                                           \
+#define MXC_F_GCR_MEMZCN_ICACHEZ                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_ICACHEZ_POS)) /**<              \
+							       MEMZCN_ICACHEZ \
+							       Mask */
+#define MXC_V_GCR_MEMZCN_ICACHEZ_NOP \
 	((uint32_t)0x0UL) /**< MEMZCN_ICACHEZ_NOP Value */
-#define MXC_S_GCR_MEMZCN_ICACHEZ_NOP                                           \
-	(MXC_V_GCR_MEMZCN_ICACHEZ_NOP                                          \
-	 << MXC_F_GCR_MEMZCN_ICACHEZ_POS) /**< MEMZCN_ICACHEZ_NOP Setting */
-#define MXC_V_GCR_MEMZCN_ICACHEZ_START                                         \
+#define MXC_S_GCR_MEMZCN_ICACHEZ_NOP                            \
+	(MXC_V_GCR_MEMZCN_ICACHEZ_NOP                           \
+	 << MXC_F_GCR_MEMZCN_ICACHEZ_POS) /**<                  \
+					     MEMZCN_ICACHEZ_NOP \
+					     Setting            \
+					   */
+#define MXC_V_GCR_MEMZCN_ICACHEZ_START \
 	((uint32_t)0x1UL) /**< MEMZCN_ICACHEZ_START Value */
-#define MXC_S_GCR_MEMZCN_ICACHEZ_START                                         \
-	(MXC_V_GCR_MEMZCN_ICACHEZ_START                                        \
-	 << MXC_F_GCR_MEMZCN_ICACHEZ_POS) /**< MEMZCN_ICACHEZ_START Setting */
+#define MXC_S_GCR_MEMZCN_ICACHEZ_START                            \
+	(MXC_V_GCR_MEMZCN_ICACHEZ_START                           \
+	 << MXC_F_GCR_MEMZCN_ICACHEZ_POS) /**<                    \
+					     MEMZCN_ICACHEZ_START \
+					     Setting              \
+					   */
 
 /**
  * System Status Register.
  */
 #define MXC_F_GCR_SYSST_ICECLOCK_POS 0 /**< SYSST_ICECLOCK Position */
-#define MXC_F_GCR_SYSST_ICECLOCK                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_SYSST_ICECLOCK_POS)) /**< SYSST_ICECLOCK Mask */
-#define MXC_V_GCR_SYSST_ICECLOCK_UNLOCKED                                      \
+#define MXC_F_GCR_SYSST_ICECLOCK                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_SYSST_ICECLOCK_POS)) /**<              \
+							       SYSST_ICECLOCK \
+							       Mask */
+#define MXC_V_GCR_SYSST_ICECLOCK_UNLOCKED \
 	((uint32_t)0x0UL) /**< SYSST_ICECLOCK_UNLOCKED Value */
 #define MXC_S_GCR_SYSST_ICECLOCK_UNLOCKED                                      \
 	(MXC_V_GCR_SYSST_ICECLOCK_UNLOCKED                                     \
 	 << MXC_F_GCR_SYSST_ICECLOCK_POS) /**< SYSST_ICECLOCK_UNLOCKED Setting \
 					   */
-#define MXC_V_GCR_SYSST_ICECLOCK_LOCKED                                        \
+#define MXC_V_GCR_SYSST_ICECLOCK_LOCKED \
 	((uint32_t)0x1UL) /**< SYSST_ICECLOCK_LOCKED Value */
-#define MXC_S_GCR_SYSST_ICECLOCK_LOCKED                                        \
-	(MXC_V_GCR_SYSST_ICECLOCK_LOCKED                                       \
-	 << MXC_F_GCR_SYSST_ICECLOCK_POS) /**< SYSST_ICECLOCK_LOCKED Setting   \
+#define MXC_S_GCR_SYSST_ICECLOCK_LOCKED                                      \
+	(MXC_V_GCR_SYSST_ICECLOCK_LOCKED                                     \
+	 << MXC_F_GCR_SYSST_ICECLOCK_POS) /**< SYSST_ICECLOCK_LOCKED Setting \
 					   */
 
 #define MXC_F_GCR_SYSST_CODEINTERR_POS 1 /**< SYSST_CODEINTERR Position */
-#define MXC_F_GCR_SYSST_CODEINTERR                                             \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_SYSST_CODEINTERR_POS)) /**< SYSST_CODEINTERR  \
+#define MXC_F_GCR_SYSST_CODEINTERR                                            \
+	((uint32_t)(0x1UL                                                     \
+		    << MXC_F_GCR_SYSST_CODEINTERR_POS)) /**< SYSST_CODEINTERR \
 							   Mask */
-#define MXC_V_GCR_SYSST_CODEINTERR_NORM                                        \
+#define MXC_V_GCR_SYSST_CODEINTERR_NORM \
 	((uint32_t)0x0UL) /**< SYSST_CODEINTERR_NORM Value */
 #define MXC_S_GCR_SYSST_CODEINTERR_NORM                                        \
 	(MXC_V_GCR_SYSST_CODEINTERR_NORM                                       \
 	 << MXC_F_GCR_SYSST_CODEINTERR_POS) /**< SYSST_CODEINTERR_NORM Setting \
 					     */
-#define MXC_V_GCR_SYSST_CODEINTERR_CODE                                        \
+#define MXC_V_GCR_SYSST_CODEINTERR_CODE \
 	((uint32_t)0x1UL) /**< SYSST_CODEINTERR_CODE Value */
 #define MXC_S_GCR_SYSST_CODEINTERR_CODE                                        \
 	(MXC_V_GCR_SYSST_CODEINTERR_CODE                                       \
@@ -1213,153 +1525,187 @@ typedef struct {
 					     */
 
 #define MXC_F_GCR_SYSST_SCMEMF_POS 5 /**< SYSST_SCMEMF Position */
-#define MXC_F_GCR_SYSST_SCMEMF                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_SYSST_SCMEMF_POS)) /**< SYSST_SCMEMF Mask */
-#define MXC_V_GCR_SYSST_SCMEMF_NORM                                            \
+#define MXC_F_GCR_SYSST_SCMEMF                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_SYSST_SCMEMF_POS)) /**< SYSST_SCMEMF \
+							     Mask */
+#define MXC_V_GCR_SYSST_SCMEMF_NORM \
 	((uint32_t)0x0UL) /**< SYSST_SCMEMF_NORM Value */
-#define MXC_S_GCR_SYSST_SCMEMF_NORM                                            \
-	(MXC_V_GCR_SYSST_SCMEMF_NORM                                           \
-	 << MXC_F_GCR_SYSST_SCMEMF_POS) /**< SYSST_SCMEMF_NORM Setting */
-#define MXC_V_GCR_SYSST_SCMEMF_MEMORY                                          \
+#define MXC_S_GCR_SYSST_SCMEMF_NORM                          \
+	(MXC_V_GCR_SYSST_SCMEMF_NORM                         \
+	 << MXC_F_GCR_SYSST_SCMEMF_POS) /**<                 \
+					   SYSST_SCMEMF_NORM \
+					   Setting           \
+					 */
+#define MXC_V_GCR_SYSST_SCMEMF_MEMORY \
 	((uint32_t)0x1UL) /**< SYSST_SCMEMF_MEMORY Value */
-#define MXC_S_GCR_SYSST_SCMEMF_MEMORY                                          \
-	(MXC_V_GCR_SYSST_SCMEMF_MEMORY                                         \
-	 << MXC_F_GCR_SYSST_SCMEMF_POS) /**< SYSST_SCMEMF_MEMORY Setting */
+#define MXC_S_GCR_SYSST_SCMEMF_MEMORY                          \
+	(MXC_V_GCR_SYSST_SCMEMF_MEMORY                         \
+	 << MXC_F_GCR_SYSST_SCMEMF_POS) /**<                   \
+					   SYSST_SCMEMF_MEMORY \
+					   Setting             \
+					 */
 
 /**
  * Reset Register.
  */
 #define MXC_F_GCR_RSTR1_I2C1_POS 0 /**< RSTR1_I2C1 Position */
-#define MXC_F_GCR_RSTR1_I2C1                                                   \
-	((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_I2C1_POS)) /**< RSTR1_I2C1 Mask   \
+#define MXC_F_GCR_RSTR1_I2C1                                                 \
+	((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_I2C1_POS)) /**< RSTR1_I2C1 Mask \
 							 */
-#define MXC_V_GCR_RSTR1_I2C1_RESET                                             \
+#define MXC_V_GCR_RSTR1_I2C1_RESET \
 	((uint32_t)0x1UL) /**< RSTR1_I2C1_RESET Value */
-#define MXC_S_GCR_RSTR1_I2C1_RESET                                             \
-	(MXC_V_GCR_RSTR1_I2C1_RESET                                            \
-	 << MXC_F_GCR_RSTR1_I2C1_POS) /**< RSTR1_I2C1_RESET Setting */
-#define MXC_V_GCR_RSTR1_I2C1_RESET_DONE                                        \
+#define MXC_S_GCR_RSTR1_I2C1_RESET                        \
+	(MXC_V_GCR_RSTR1_I2C1_RESET                       \
+	 << MXC_F_GCR_RSTR1_I2C1_POS) /**<                \
+					 RSTR1_I2C1_RESET \
+					 Setting */
+#define MXC_V_GCR_RSTR1_I2C1_RESET_DONE \
 	((uint32_t)0x0UL) /**< RSTR1_I2C1_RESET_DONE Value */
-#define MXC_S_GCR_RSTR1_I2C1_RESET_DONE                                        \
-	(MXC_V_GCR_RSTR1_I2C1_RESET_DONE                                       \
-	 << MXC_F_GCR_RSTR1_I2C1_POS) /**< RSTR1_I2C1_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR1_I2C1_BUSY                                              \
+#define MXC_S_GCR_RSTR1_I2C1_RESET_DONE                        \
+	(MXC_V_GCR_RSTR1_I2C1_RESET_DONE                       \
+	 << MXC_F_GCR_RSTR1_I2C1_POS) /**<                     \
+					 RSTR1_I2C1_RESET_DONE \
+					 Setting               \
+				       */
+#define MXC_V_GCR_RSTR1_I2C1_BUSY \
 	((uint32_t)0x1UL) /**< RSTR1_I2C1_BUSY Value */
-#define MXC_S_GCR_RSTR1_I2C1_BUSY                                              \
-	(MXC_V_GCR_RSTR1_I2C1_BUSY                                             \
-	 << MXC_F_GCR_RSTR1_I2C1_POS) /**< RSTR1_I2C1_BUSY Setting */
+#define MXC_S_GCR_RSTR1_I2C1_BUSY                        \
+	(MXC_V_GCR_RSTR1_I2C1_BUSY                       \
+	 << MXC_F_GCR_RSTR1_I2C1_POS) /**<               \
+					 RSTR1_I2C1_BUSY \
+					 Setting */
 
 /**
  * Peripheral Clock Disable.
  */
 #define MXC_F_GCR_PERCKCN1_FLCD_POS 3 /**< PERCKCN1_FLCD Position */
-#define MXC_F_GCR_PERCKCN1_FLCD                                                \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_PERCKCN1_FLCD_POS)) /**< PERCKCN1_FLCD Mask */
-#define MXC_V_GCR_PERCKCN1_FLCD_EN                                             \
+#define MXC_F_GCR_PERCKCN1_FLCD                                               \
+	((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_FLCD_POS)) /**< PERCKCN1_FLCD \
+							      Mask */
+#define MXC_V_GCR_PERCKCN1_FLCD_EN \
 	((uint32_t)0x0UL) /**< PERCKCN1_FLCD_EN Value */
-#define MXC_S_GCR_PERCKCN1_FLCD_EN                                             \
-	(MXC_V_GCR_PERCKCN1_FLCD_EN                                            \
-	 << MXC_F_GCR_PERCKCN1_FLCD_POS) /**< PERCKCN1_FLCD_EN Setting */
-#define MXC_V_GCR_PERCKCN1_FLCD_DIS                                            \
+#define MXC_S_GCR_PERCKCN1_FLCD_EN                           \
+	(MXC_V_GCR_PERCKCN1_FLCD_EN                          \
+	 << MXC_F_GCR_PERCKCN1_FLCD_POS) /**<                \
+					    PERCKCN1_FLCD_EN \
+					    Setting          \
+					  */
+#define MXC_V_GCR_PERCKCN1_FLCD_DIS \
 	((uint32_t)0x1UL) /**< PERCKCN1_FLCD_DIS Value */
-#define MXC_S_GCR_PERCKCN1_FLCD_DIS                                            \
-	(MXC_V_GCR_PERCKCN1_FLCD_DIS                                           \
-	 << MXC_F_GCR_PERCKCN1_FLCD_POS) /**< PERCKCN1_FLCD_DIS Setting */
+#define MXC_S_GCR_PERCKCN1_FLCD_DIS                           \
+	(MXC_V_GCR_PERCKCN1_FLCD_DIS                          \
+	 << MXC_F_GCR_PERCKCN1_FLCD_POS) /**<                 \
+					    PERCKCN1_FLCD_DIS \
+					    Setting           \
+					  */
 
 #define MXC_F_GCR_PERCKCN1_ICACHED_POS 11 /**< PERCKCN1_ICACHED Position */
-#define MXC_F_GCR_PERCKCN1_ICACHED                                             \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_PERCKCN1_ICACHED_POS)) /**< PERCKCN1_ICACHED  \
+#define MXC_F_GCR_PERCKCN1_ICACHED                                            \
+	((uint32_t)(0x1UL                                                     \
+		    << MXC_F_GCR_PERCKCN1_ICACHED_POS)) /**< PERCKCN1_ICACHED \
 							   Mask */
-#define MXC_V_GCR_PERCKCN1_ICACHED_EN                                          \
+#define MXC_V_GCR_PERCKCN1_ICACHED_EN \
 	((uint32_t)0x0UL) /**< PERCKCN1_ICACHED_EN Value */
-#define MXC_S_GCR_PERCKCN1_ICACHED_EN                                          \
-	(MXC_V_GCR_PERCKCN1_ICACHED_EN                                         \
-	 << MXC_F_GCR_PERCKCN1_ICACHED_POS) /**< PERCKCN1_ICACHED_EN Setting   \
+#define MXC_S_GCR_PERCKCN1_ICACHED_EN                                        \
+	(MXC_V_GCR_PERCKCN1_ICACHED_EN                                       \
+	 << MXC_F_GCR_PERCKCN1_ICACHED_POS) /**< PERCKCN1_ICACHED_EN Setting \
 					     */
-#define MXC_V_GCR_PERCKCN1_ICACHED_DIS                                         \
+#define MXC_V_GCR_PERCKCN1_ICACHED_DIS \
 	((uint32_t)0x1UL) /**< PERCKCN1_ICACHED_DIS Value */
-#define MXC_S_GCR_PERCKCN1_ICACHED_DIS                                         \
-	(MXC_V_GCR_PERCKCN1_ICACHED_DIS                                        \
-	 << MXC_F_GCR_PERCKCN1_ICACHED_POS) /**< PERCKCN1_ICACHED_DIS Setting  \
+#define MXC_S_GCR_PERCKCN1_ICACHED_DIS                                        \
+	(MXC_V_GCR_PERCKCN1_ICACHED_DIS                                       \
+	 << MXC_F_GCR_PERCKCN1_ICACHED_POS) /**< PERCKCN1_ICACHED_DIS Setting \
 					     */
 
 /**
  * Event Enable Register.
  */
 #define MXC_F_GCR_EVTEN_DMAEVENT_POS 0 /**< EVTEN_DMAEVENT Position */
-#define MXC_F_GCR_EVTEN_DMAEVENT                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_EVTEN_DMAEVENT_POS)) /**< EVTEN_DMAEVENT Mask */
+#define MXC_F_GCR_EVTEN_DMAEVENT                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_DMAEVENT_POS)) /**<              \
+							       EVTEN_DMAEVENT \
+							       Mask */
 
 #define MXC_F_GCR_EVTEN_RXEVENT_POS 1 /**< EVTEN_RXEVENT Position */
-#define MXC_F_GCR_EVTEN_RXEVENT                                                \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_EVTEN_RXEVENT_POS)) /**< EVTEN_RXEVENT Mask */
+#define MXC_F_GCR_EVTEN_RXEVENT                                               \
+	((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_RXEVENT_POS)) /**< EVTEN_RXEVENT \
+							      Mask */
 
 /**
  * Revision Register.
  */
 #define MXC_F_GCR_REVISION_REVISION_POS 0 /**< REVISION_REVISION Position */
-#define MXC_F_GCR_REVISION_REVISION                                            \
-	((uint32_t)(                                                           \
-		0xFFFFUL                                                       \
-		<< MXC_F_GCR_REVISION_REVISION_POS)) /**< REVISION_REVISION    \
-							Mask */
+#define MXC_F_GCR_REVISION_REVISION                                           \
+	((uint32_t)(0xFFFFUL                                                  \
+		    << MXC_F_GCR_REVISION_REVISION_POS)) /**<                 \
+							    REVISION_REVISION \
+							    Mask */
 
 /**
  * System Status Interrupt Enable Register.
  */
 #define MXC_F_GCR_SYSSIE_ICEULIE_POS 0 /**< SYSSIE_ICEULIE Position */
-#define MXC_F_GCR_SYSSIE_ICEULIE                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_SYSSIE_ICEULIE_POS)) /**< SYSSIE_ICEULIE Mask */
-#define MXC_V_GCR_SYSSIE_ICEULIE_DIS                                           \
+#define MXC_F_GCR_SYSSIE_ICEULIE                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_SYSSIE_ICEULIE_POS)) /**<              \
+							       SYSSIE_ICEULIE \
+							       Mask */
+#define MXC_V_GCR_SYSSIE_ICEULIE_DIS \
 	((uint32_t)0x0UL) /**< SYSSIE_ICEULIE_DIS Value */
-#define MXC_S_GCR_SYSSIE_ICEULIE_DIS                                           \
-	(MXC_V_GCR_SYSSIE_ICEULIE_DIS                                          \
-	 << MXC_F_GCR_SYSSIE_ICEULIE_POS) /**< SYSSIE_ICEULIE_DIS Setting */
-#define MXC_V_GCR_SYSSIE_ICEULIE_EN                                            \
+#define MXC_S_GCR_SYSSIE_ICEULIE_DIS                            \
+	(MXC_V_GCR_SYSSIE_ICEULIE_DIS                           \
+	 << MXC_F_GCR_SYSSIE_ICEULIE_POS) /**<                  \
+					     SYSSIE_ICEULIE_DIS \
+					     Setting            \
+					   */
+#define MXC_V_GCR_SYSSIE_ICEULIE_EN \
 	((uint32_t)0x1UL) /**< SYSSIE_ICEULIE_EN Value */
-#define MXC_S_GCR_SYSSIE_ICEULIE_EN                                            \
-	(MXC_V_GCR_SYSSIE_ICEULIE_EN                                           \
-	 << MXC_F_GCR_SYSSIE_ICEULIE_POS) /**< SYSSIE_ICEULIE_EN Setting */
+#define MXC_S_GCR_SYSSIE_ICEULIE_EN                            \
+	(MXC_V_GCR_SYSSIE_ICEULIE_EN                           \
+	 << MXC_F_GCR_SYSSIE_ICEULIE_POS) /**<                 \
+					     SYSSIE_ICEULIE_EN \
+					     Setting           \
+					   */
 
 #define MXC_F_GCR_SYSSIE_CIEIE_POS 1 /**< SYSSIE_CIEIE Position */
-#define MXC_F_GCR_SYSSIE_CIEIE                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_SYSSIE_CIEIE_POS)) /**< SYSSIE_CIEIE Mask */
-#define MXC_V_GCR_SYSSIE_CIEIE_DIS                                             \
+#define MXC_F_GCR_SYSSIE_CIEIE                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_SYSSIE_CIEIE_POS)) /**< SYSSIE_CIEIE \
+							     Mask */
+#define MXC_V_GCR_SYSSIE_CIEIE_DIS \
 	((uint32_t)0x0UL) /**< SYSSIE_CIEIE_DIS Value */
-#define MXC_S_GCR_SYSSIE_CIEIE_DIS                                             \
-	(MXC_V_GCR_SYSSIE_CIEIE_DIS                                            \
-	 << MXC_F_GCR_SYSSIE_CIEIE_POS) /**< SYSSIE_CIEIE_DIS Setting */
-#define MXC_V_GCR_SYSSIE_CIEIE_EN                                              \
+#define MXC_S_GCR_SYSSIE_CIEIE_DIS                          \
+	(MXC_V_GCR_SYSSIE_CIEIE_DIS                         \
+	 << MXC_F_GCR_SYSSIE_CIEIE_POS) /**<                \
+					   SYSSIE_CIEIE_DIS \
+					   Setting          \
+					 */
+#define MXC_V_GCR_SYSSIE_CIEIE_EN \
 	((uint32_t)0x1UL) /**< SYSSIE_CIEIE_EN Value */
-#define MXC_S_GCR_SYSSIE_CIEIE_EN                                              \
-	(MXC_V_GCR_SYSSIE_CIEIE_EN                                             \
-	 << MXC_F_GCR_SYSSIE_CIEIE_POS) /**< SYSSIE_CIEIE_EN Setting */
+#define MXC_S_GCR_SYSSIE_CIEIE_EN                          \
+	(MXC_V_GCR_SYSSIE_CIEIE_EN                         \
+	 << MXC_F_GCR_SYSSIE_CIEIE_POS) /**<               \
+					   SYSSIE_CIEIE_EN \
+					   Setting         \
+					 */
 
 #define MXC_F_GCR_SYSSIE_SCMFIE_POS 5 /**< SYSSIE_SCMFIE Position */
-#define MXC_F_GCR_SYSSIE_SCMFIE                                                \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_SYSSIE_SCMFIE_POS)) /**< SYSSIE_SCMFIE Mask */
-#define MXC_V_GCR_SYSSIE_SCMFIE_DIS                                            \
+#define MXC_F_GCR_SYSSIE_SCMFIE                                               \
+	((uint32_t)(0x1UL << MXC_F_GCR_SYSSIE_SCMFIE_POS)) /**< SYSSIE_SCMFIE \
+							      Mask */
+#define MXC_V_GCR_SYSSIE_SCMFIE_DIS \
 	((uint32_t)0x0UL) /**< SYSSIE_SCMFIE_DIS Value */
-#define MXC_S_GCR_SYSSIE_SCMFIE_DIS                                            \
-	(MXC_V_GCR_SYSSIE_SCMFIE_DIS                                           \
-	 << MXC_F_GCR_SYSSIE_SCMFIE_POS) /**< SYSSIE_SCMFIE_DIS Setting */
-#define MXC_V_GCR_SYSSIE_SCMFIE_EN                                             \
+#define MXC_S_GCR_SYSSIE_SCMFIE_DIS                           \
+	(MXC_V_GCR_SYSSIE_SCMFIE_DIS                          \
+	 << MXC_F_GCR_SYSSIE_SCMFIE_POS) /**<                 \
+					    SYSSIE_SCMFIE_DIS \
+					    Setting           \
+					  */
+#define MXC_V_GCR_SYSSIE_SCMFIE_EN \
 	((uint32_t)0x1UL) /**< SYSSIE_SCMFIE_EN Value */
-#define MXC_S_GCR_SYSSIE_SCMFIE_EN                                             \
-	(MXC_V_GCR_SYSSIE_SCMFIE_EN                                            \
-	 << MXC_F_GCR_SYSSIE_SCMFIE_POS) /**< SYSSIE_SCMFIE_EN Setting */
+#define MXC_S_GCR_SYSSIE_SCMFIE_EN                           \
+	(MXC_V_GCR_SYSSIE_SCMFIE_EN                          \
+	 << MXC_F_GCR_SYSSIE_SCMFIE_POS) /**<                \
+					    SYSSIE_SCMFIE_EN \
+					    Setting          \
+					  */
 
 #endif /* _GCR_REGS_H_ */
diff --git a/chip/max32660/gpio_chip.c b/chip/max32660/gpio_chip.c
index 5fe38cd657..b6deaa9111 100644
--- a/chip/max32660/gpio_chip.c
+++ b/chip/max32660/gpio_chip.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,25 +6,25 @@
 /* MAX32660 GPIO module for Chrome EC */
 
 #include "clock.h"
-#include "console.h"
 #include "common.h"
+#include "console.h"
 #include "gpio.h"
+#include "gpio_regs.h"
 #include "hooks.h"
+#include "registers.h"
 #include "switch.h"
 #include "task.h"
 #include "timer.h"
 #include "util.h"
-#include "registers.h"
-#include "gpio_regs.h"
 
 #define CPRINTF(format, args...) cprintf(CC_GPIO, format, ##args)
 #define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
 
 /* 0-terminated list of GPIO base addresses */
-static mxc_gpio_regs_t *gpio_bases[] = {MXC_GPIO0, 0};
+static mxc_gpio_regs_t *gpio_bases[] = { MXC_GPIO0, 0 };
 
 void gpio_set_alternate_function(uint32_t port, uint32_t mask,
-			enum gpio_alternate_func func)
+				 enum gpio_alternate_func func)
 {
 	mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(port);
 
@@ -42,7 +42,7 @@ void gpio_set_alternate_function(uint32_t port, uint32_t mask,
 		gpio->en1_set = mask;
 		break;
 	default:
-	    /* Default as input */
+		/* Default as input */
 		gpio->out_en_clr = mask;
 		gpio->en_set = mask;
 		gpio->en1_clr = mask;
@@ -184,7 +184,7 @@ void gpio_pre_init(void)
 
 		/* Use as GPIO, not alternate function */
 		gpio_set_alternate_function(g->port, g->mask,
-					GPIO_ALT_FUNC_NONE);
+					    GPIO_ALT_FUNC_NONE);
 
 		/* Set up GPIO based on flags */
 		gpio_set_flags_by_mask(g->port, g->mask, flags);
@@ -194,8 +194,8 @@ void gpio_pre_init(void)
 static void gpio_init(void)
 {
 	/*
-	 * Enable global GPIO0 Port interrupt. Note that interrupts still need to be
-	 * enabled at the per pin level.
+	 * Enable global GPIO0 Port interrupt. Note that interrupts still need
+	 * to be enabled at the per pin level.
 	 */
 	task_enable_irq(EC_GPIO0_IRQn);
 }
@@ -227,13 +227,13 @@ static void gpio_interrupt(int port, uint32_t mis)
  * Handlers for each GPIO port. Read the interrupt status, call the common GPIO
  * interrupt handler and clear the GPIO hardware interrupt status.
  */
-#define GPIO_IRQ_FUNC(irqfunc, gpiobase)                                       \
-	void irqfunc(void)                                                     \
-	{                                                                      \
-		mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(gpiobase);           \
-		uint32_t mis = gpio->int_stat;                                 \
-		gpio_interrupt(gpiobase, mis);                                 \
-		gpio->int_clr = mis;                                           \
+#define GPIO_IRQ_FUNC(irqfunc, gpiobase)                             \
+	static void irqfunc(void)                                    \
+	{                                                            \
+		mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(gpiobase); \
+		uint32_t mis = gpio->int_stat;                       \
+		gpio_interrupt(gpiobase, mis);                       \
+		gpio->int_clr = mis;                                 \
 	}
 
 GPIO_IRQ_FUNC(__gpio_0_interrupt, PORT_0);
diff --git a/chip/max32660/gpio_regs.h b/chip/max32660/gpio_regs.h
index 1c6fcf7a71..70b706b2c0 100644
--- a/chip/max32660/gpio_regs.h
+++ b/chip/max32660/gpio_regs.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -40,65 +40,65 @@
  * Structure type to access the GPIO Registers.
  */
 typedef struct {
-	__IO uint32_t en;     /**< <tt>\b 0x00:<\tt> GPIO EN Register */
+	__IO uint32_t en; /**< <tt>\b 0x00:<\tt> GPIO EN Register */
 	__IO uint32_t en_set; /**< <tt>\b 0x04:<\tt> GPIO EN_SET Register */
 	__IO uint32_t en_clr; /**< <tt>\b 0x08:<\tt> GPIO EN_CLR Register */
 	__IO uint32_t out_en; /**< <tt>\b 0x0C:<\tt> GPIO OUT_EN Register */
-	__IO uint32_t
-		out_en_set; /**< <tt>\b 0x10:<\tt> GPIO OUT_EN_SET Register */
-	__IO uint32_t
-		out_en_clr;   /**< <tt>\b 0x14:<\tt> GPIO OUT_EN_CLR Register */
-	__IO uint32_t out;    /**< <tt>\b 0x18:<\tt> GPIO OUT Register */
+	__IO uint32_t out_en_set; /**< <tt>\b 0x10:<\tt> GPIO OUT_EN_SET
+				     Register */
+	__IO uint32_t out_en_clr; /**< <tt>\b 0x14:<\tt> GPIO OUT_EN_CLR
+				     Register */
+	__IO uint32_t out; /**< <tt>\b 0x18:<\tt> GPIO OUT Register */
 	__O uint32_t out_set; /**< <tt>\b 0x1C:<\tt> GPIO OUT_SET Register */
 	__O uint32_t out_clr; /**< <tt>\b 0x20:<\tt> GPIO OUT_CLR Register */
-	__I uint32_t in;      /**< <tt>\b 0x24:<\tt> GPIO IN Register */
+	__I uint32_t in; /**< <tt>\b 0x24:<\tt> GPIO IN Register */
 	__IO uint32_t int_mod; /**< <tt>\b 0x28:<\tt> GPIO INT_MOD Register */
 	__IO uint32_t int_pol; /**< <tt>\b 0x2C:<\tt> GPIO INT_POL Register */
 	__R uint32_t rsv_0x30;
 	__IO uint32_t int_en; /**< <tt>\b 0x34:<\tt> GPIO INT_EN Register */
-	__IO uint32_t
-		int_en_set; /**< <tt>\b 0x38:<\tt> GPIO INT_EN_SET Register */
-	__IO uint32_t
-		int_en_clr; /**< <tt>\b 0x3C:<\tt> GPIO INT_EN_CLR Register */
+	__IO uint32_t int_en_set; /**< <tt>\b 0x38:<\tt> GPIO INT_EN_SET
+				     Register */
+	__IO uint32_t int_en_clr; /**< <tt>\b 0x3C:<\tt> GPIO INT_EN_CLR
+				     Register */
 	__I uint32_t int_stat; /**< <tt>\b 0x40:<\tt> GPIO INT_STAT Register */
 	__R uint32_t rsv_0x44;
 	__IO uint32_t int_clr; /**< <tt>\b 0x48:<\tt> GPIO INT_CLR Register */
 	__IO uint32_t wake_en; /**< <tt>\b 0x4C:<\tt> GPIO WAKE_EN Register */
-	__IO uint32_t
-		wake_en_set; /**< <tt>\b 0x50:<\tt> GPIO WAKE_EN_SET Register */
-	__IO uint32_t
-		wake_en_clr; /**< <tt>\b 0x54:<\tt> GPIO WAKE_EN_CLR Register */
+	__IO uint32_t wake_en_set; /**< <tt>\b 0x50:<\tt> GPIO WAKE_EN_SET
+				      Register */
+	__IO uint32_t wake_en_clr; /**< <tt>\b 0x54:<\tt> GPIO WAKE_EN_CLR
+				      Register */
 	__R uint32_t rsv_0x58;
 	__IO uint32_t int_dual_edge; /**< <tt>\b 0x5C:<\tt> GPIO INT_DUAL_EDGE
 					Register */
 	__IO uint32_t pad_cfg1; /**< <tt>\b 0x60:<\tt> GPIO PAD_CFG1 Register */
 	__IO uint32_t pad_cfg2; /**< <tt>\b 0x64:<\tt> GPIO PAD_CFG2 Register */
-	__IO uint32_t en1;      /**< <tt>\b 0x68:<\tt> GPIO EN1 Register */
-	__IO uint32_t en1_set;  /**< <tt>\b 0x6C:<\tt> GPIO EN1_SET Register */
-	__IO uint32_t en1_clr;  /**< <tt>\b 0x70:<\tt> GPIO EN1_CLR Register */
-	__IO uint32_t en2;      /**< <tt>\b 0x74:<\tt> GPIO EN2 Register */
-	__IO uint32_t en2_set;  /**< <tt>\b 0x78:<\tt> GPIO EN2_SET Register */
-	__IO uint32_t en2_clr;  /**< <tt>\b 0x7C:<\tt> GPIO EN2_CLR Register */
+	__IO uint32_t en1; /**< <tt>\b 0x68:<\tt> GPIO EN1 Register */
+	__IO uint32_t en1_set; /**< <tt>\b 0x6C:<\tt> GPIO EN1_SET Register */
+	__IO uint32_t en1_clr; /**< <tt>\b 0x70:<\tt> GPIO EN1_CLR Register */
+	__IO uint32_t en2; /**< <tt>\b 0x74:<\tt> GPIO EN2 Register */
+	__IO uint32_t en2_set; /**< <tt>\b 0x78:<\tt> GPIO EN2_SET Register */
+	__IO uint32_t en2_clr; /**< <tt>\b 0x7C:<\tt> GPIO EN2_CLR Register */
 	__R uint32_t rsv_0x80_0xa7[10];
-	__IO uint32_t is;  /**< <tt>\b 0xA8:<\tt> GPIO IS Register */
-	__IO uint32_t sr;  /**< <tt>\b 0xAC:<\tt> GPIO SR Register */
-	__IO uint32_t ds;  /**< <tt>\b 0xB0:<\tt> GPIO DS Register */
+	__IO uint32_t is; /**< <tt>\b 0xA8:<\tt> GPIO IS Register */
+	__IO uint32_t sr; /**< <tt>\b 0xAC:<\tt> GPIO SR Register */
+	__IO uint32_t ds; /**< <tt>\b 0xB0:<\tt> GPIO DS Register */
 	__IO uint32_t ds1; /**< <tt>\b 0xB4:<\tt> GPIO DS1 Register */
-	__IO uint32_t ps;  /**< <tt>\b 0xB8:<\tt> GPIO PS Register */
+	__IO uint32_t ps; /**< <tt>\b 0xB8:<\tt> GPIO PS Register */
 	__R uint32_t rsv_0xbc;
 	__IO uint32_t vssel; /**< <tt>\b 0xC0:<\tt> GPIO VSSEL Register */
 } mxc_gpio_regs_t;
 
-#define PIN_0 ((uint32_t)(1UL << 0))   /**< Pin 0 Define */
-#define PIN_1 ((uint32_t)(1UL << 1))   /**< Pin 1 Define */
-#define PIN_2 ((uint32_t)(1UL << 2))   /**< Pin 2 Define */
-#define PIN_3 ((uint32_t)(1UL << 3))   /**< Pin 3 Define */
-#define PIN_4 ((uint32_t)(1UL << 4))   /**< Pin 4 Define */
-#define PIN_5 ((uint32_t)(1UL << 5))   /**< Pin 5 Define */
-#define PIN_6 ((uint32_t)(1UL << 6))   /**< Pin 6 Define */
-#define PIN_7 ((uint32_t)(1UL << 7))   /**< Pin 7 Define */
-#define PIN_8 ((uint32_t)(1UL << 8))   /**< Pin 8 Define */
-#define PIN_9 ((uint32_t)(1UL << 9))   /**< Pin 9 Define */
+#define PIN_0 ((uint32_t)(1UL << 0)) /**< Pin 0 Define */
+#define PIN_1 ((uint32_t)(1UL << 1)) /**< Pin 1 Define */
+#define PIN_2 ((uint32_t)(1UL << 2)) /**< Pin 2 Define */
+#define PIN_3 ((uint32_t)(1UL << 3)) /**< Pin 3 Define */
+#define PIN_4 ((uint32_t)(1UL << 4)) /**< Pin 4 Define */
+#define PIN_5 ((uint32_t)(1UL << 5)) /**< Pin 5 Define */
+#define PIN_6 ((uint32_t)(1UL << 6)) /**< Pin 6 Define */
+#define PIN_7 ((uint32_t)(1UL << 7)) /**< Pin 7 Define */
+#define PIN_8 ((uint32_t)(1UL << 8)) /**< Pin 8 Define */
+#define PIN_9 ((uint32_t)(1UL << 9)) /**< Pin 9 Define */
 #define PIN_10 ((uint32_t)(1UL << 10)) /**< Pin 10 Define */
 #define PIN_11 ((uint32_t)(1UL << 11)) /**< Pin 11 Define */
 #define PIN_12 ((uint32_t)(1UL << 12)) /**< Pin 12 Define */
@@ -126,8 +126,8 @@ typedef struct {
  * Enumeration type for the GPIO Function Type
  */
 typedef enum {
-	GPIO_FUNC_IN,   /**< GPIO Input */
-	GPIO_FUNC_OUT,  /**< GPIO Output */
+	GPIO_FUNC_IN, /**< GPIO Input */
+	GPIO_FUNC_OUT, /**< GPIO Output */
 	GPIO_FUNC_ALT1, /**< Alternate Function Selection */
 	GPIO_FUNC_ALT2, /**< Alternate Function Selection */
 	GPIO_FUNC_ALT3, /**< Alternate Function Selection */
@@ -138,8 +138,8 @@ typedef enum {
  * Enumeration type for the type of GPIO pad on a given pin.
  */
 typedef enum {
-	GPIO_PAD_NONE,      /**< No pull-up or pull-down */
-	GPIO_PAD_PULL_UP,   /**< Set pad to weak pull-up */
+	GPIO_PAD_NONE, /**< No pull-up or pull-down */
+	GPIO_PAD_PULL_UP, /**< Set pad to weak pull-up */
 	GPIO_PAD_PULL_DOWN, /**< Set pad to weak pull-down */
 } gpio_pad_t;
 
@@ -147,10 +147,10 @@ typedef enum {
  * Structure type for configuring a GPIO port.
  */
 typedef struct {
-	uint32_t port;    /**< Index of GPIO port */
-	uint32_t mask;    /**< Pin mask (multiple pins may be set) */
+	uint32_t port; /**< Index of GPIO port */
+	uint32_t mask; /**< Pin mask (multiple pins may be set) */
 	gpio_func_t func; /**< Function type */
-	gpio_pad_t pad;   /**< Pad type */
+	gpio_pad_t pad; /**< Pad type */
 } gpio_cfg_t;
 
 typedef enum { GPIO_INTERRUPT_LEVEL, GPIO_INTERRUPT_EDGE } gpio_int_mode_t;
@@ -166,110 +166,110 @@ typedef enum {
 } gpio_int_pol_t;
 
 /* Register offsets for module GPIO */
-#define MXC_R_GPIO_EN                                                          \
-	((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_EN                                                     \
+	((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x000 */
-#define MXC_R_GPIO_EN_SET                                                      \
-	((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_EN_SET                                                 \
+	((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x004 */
-#define MXC_R_GPIO_EN_CLR                                                      \
-	((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_EN_CLR                                                 \
+	((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x008 */
-#define MXC_R_GPIO_OUT_EN                                                      \
-	((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_OUT_EN                                                 \
+	((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x00C */
-#define MXC_R_GPIO_OUT_EN_SET                                                  \
-	((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_OUT_EN_SET                                             \
+	((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x010 */
-#define MXC_R_GPIO_OUT_EN_CLR                                                  \
-	((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_OUT_EN_CLR                                             \
+	((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x014 */
-#define MXC_R_GPIO_OUT                                                         \
-	((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_OUT                                                    \
+	((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x018 */
-#define MXC_R_GPIO_OUT_SET                                                     \
-	((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_OUT_SET                                                \
+	((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x01C */
-#define MXC_R_GPIO_OUT_CLR                                                     \
-	((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_OUT_CLR                                                \
+	((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x020 */
-#define MXC_R_GPIO_IN                                                          \
-	((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_IN                                                     \
+	((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x024 */
-#define MXC_R_GPIO_INT_MOD                                                     \
-	((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_INT_MOD                                                \
+	((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x028 */
-#define MXC_R_GPIO_INT_POL                                                     \
-	((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_INT_POL                                                \
+	((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x02C */
-#define MXC_R_GPIO_INT_EN                                                      \
-	((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_INT_EN                                                 \
+	((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x034 */
-#define MXC_R_GPIO_INT_EN_SET                                                  \
-	((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_INT_EN_SET                                             \
+	((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x038 */
-#define MXC_R_GPIO_INT_EN_CLR                                                  \
-	((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_INT_EN_CLR                                             \
+	((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x03C */
-#define MXC_R_GPIO_INT_STAT                                                    \
-	((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_INT_STAT                                               \
+	((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x040 */
-#define MXC_R_GPIO_INT_CLR                                                     \
-	((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_INT_CLR                                                \
+	((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x048 */
-#define MXC_R_GPIO_WAKE_EN                                                     \
-	((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_WAKE_EN                                                \
+	((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x04C */
-#define MXC_R_GPIO_WAKE_EN_SET                                                 \
-	((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_WAKE_EN_SET                                            \
+	((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x050 */
-#define MXC_R_GPIO_WAKE_EN_CLR                                                 \
-	((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_WAKE_EN_CLR                                            \
+	((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x054 */
-#define MXC_R_GPIO_INT_DUAL_EDGE                                               \
-	((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_INT_DUAL_EDGE                                          \
+	((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x05C */
-#define MXC_R_GPIO_PAD_CFG1                                                    \
-	((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_PAD_CFG1                                               \
+	((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x060 */
-#define MXC_R_GPIO_PAD_CFG2                                                    \
-	((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_PAD_CFG2                                               \
+	((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x064 */
-#define MXC_R_GPIO_EN1                                                         \
-	((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_EN1                                                    \
+	((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x068 */
-#define MXC_R_GPIO_EN1_SET                                                     \
-	((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_EN1_SET                                                \
+	((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x06C */
-#define MXC_R_GPIO_EN1_CLR                                                     \
-	((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_EN1_CLR                                                \
+	((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x070 */
-#define MXC_R_GPIO_EN2                                                         \
-	((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_EN2                                                    \
+	((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x074 */
-#define MXC_R_GPIO_EN2_SET                                                     \
-	((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_EN2_SET                                                \
+	((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x078 */
-#define MXC_R_GPIO_EN2_CLR                                                     \
-	((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_EN2_CLR                                                \
+	((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x07C */
-#define MXC_R_GPIO_IS                                                          \
-	((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_IS                                                     \
+	((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x0A8 */
-#define MXC_R_GPIO_SR                                                          \
-	((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_SR                                                     \
+	((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x0AC */
-#define MXC_R_GPIO_DS                                                          \
-	((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_DS                                                     \
+	((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x0B0 */
-#define MXC_R_GPIO_DS1                                                         \
-	((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_DS1                                                    \
+	((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x0B4 */
-#define MXC_R_GPIO_PS                                                          \
-	((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_PS                                                     \
+	((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x0B8 */
-#define MXC_R_GPIO_VSSEL                                                       \
-	((uint32_t)0x000000C0UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_VSSEL                                                  \
+	((uint32_t)0x000000C0UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x0C0 */
 
 /**
@@ -277,19 +277,26 @@ typedef enum {
  * setting for one GPIO pin on the associated port.
  */
 #define MXC_F_GPIO_EN_GPIO_EN_POS 0 /**< EN_GPIO_EN Position */
-#define MXC_F_GPIO_EN_GPIO_EN                                                  \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_EN_GPIO_EN_POS)) /**< EN_GPIO_EN Mask */
-#define MXC_V_GPIO_EN_GPIO_EN_ALTERNATE                                        \
+#define MXC_F_GPIO_EN_GPIO_EN                                                 \
+	((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN_GPIO_EN_POS)) /**<          \
+								   EN_GPIO_EN \
+								   Mask */
+#define MXC_V_GPIO_EN_GPIO_EN_ALTERNATE \
 	((uint32_t)0x0UL) /**< EN_GPIO_EN_ALTERNATE Value */
-#define MXC_S_GPIO_EN_GPIO_EN_ALTERNATE                                        \
-	(MXC_V_GPIO_EN_GPIO_EN_ALTERNATE                                       \
-	 << MXC_F_GPIO_EN_GPIO_EN_POS) /**< EN_GPIO_EN_ALTERNATE Setting */
-#define MXC_V_GPIO_EN_GPIO_EN_GPIO                                             \
+#define MXC_S_GPIO_EN_GPIO_EN_ALTERNATE                        \
+	(MXC_V_GPIO_EN_GPIO_EN_ALTERNATE                       \
+	 << MXC_F_GPIO_EN_GPIO_EN_POS) /**<                    \
+					  EN_GPIO_EN_ALTERNATE \
+					  Setting              \
+					*/
+#define MXC_V_GPIO_EN_GPIO_EN_GPIO \
 	((uint32_t)0x1UL) /**< EN_GPIO_EN_GPIO Value */
-#define MXC_S_GPIO_EN_GPIO_EN_GPIO                                             \
-	(MXC_V_GPIO_EN_GPIO_EN_GPIO                                            \
-	 << MXC_F_GPIO_EN_GPIO_EN_POS) /**< EN_GPIO_EN_GPIO Setting */
+#define MXC_S_GPIO_EN_GPIO_EN_GPIO                        \
+	(MXC_V_GPIO_EN_GPIO_EN_GPIO                       \
+	 << MXC_F_GPIO_EN_GPIO_EN_POS) /**<               \
+					  EN_GPIO_EN_GPIO \
+					  Setting         \
+					*/
 
 /**
  * GPIO Set Function Enable Register. Writing a 1 to one or more bits
@@ -297,9 +304,10 @@ typedef enum {
  * affecting other bits in that register.
  */
 #define MXC_F_GPIO_EN_SET_ALL_POS 0 /**< EN_SET_ALL Position */
-#define MXC_F_GPIO_EN_SET_ALL                                                  \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_EN_SET_ALL_POS)) /**< EN_SET_ALL Mask */
+#define MXC_F_GPIO_EN_SET_ALL                                                 \
+	((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN_SET_ALL_POS)) /**<          \
+								   EN_SET_ALL \
+								   Mask */
 
 /**
  * GPIO Clear Function Enable Register. Writing a 1 to one or more
@@ -307,33 +315,34 @@ typedef enum {
  * without affecting other bits in that register.
  */
 #define MXC_F_GPIO_EN_CLR_ALL_POS 0 /**< EN_CLR_ALL Position */
-#define MXC_F_GPIO_EN_CLR_ALL                                                  \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_EN_CLR_ALL_POS)) /**< EN_CLR_ALL Mask */
+#define MXC_F_GPIO_EN_CLR_ALL                                                 \
+	((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN_CLR_ALL_POS)) /**<          \
+								   EN_CLR_ALL \
+								   Mask */
 
 /**
  * GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN
  * setting for one GPIO pin in the associated port.
  */
-#define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS                                      \
-	0 /**< OUT_EN_GPIO_OUT_EN Position                                     \
+#define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS  \
+	0 /**< OUT_EN_GPIO_OUT_EN Position \
 	   */
-#define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN                                          \
-	((uint32_t)(                                                           \
-		0xFFFFFFFFUL                                                   \
-		<< MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS)) /**< OUT_EN_GPIO_OUT_EN \
-							  Mask */
-#define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS                                      \
+#define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN                                            \
+	((uint32_t)(0xFFFFFFFFUL                                                 \
+		    << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS)) /**<                  \
+							      OUT_EN_GPIO_OUT_EN \
+							      Mask */
+#define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS \
 	((uint32_t)0x0UL) /**< OUT_EN_GPIO_OUT_EN_DIS Value */
-#define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_DIS                                      \
-	(MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS                                     \
-	 << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_DIS     \
+#define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_DIS                                  \
+	(MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS                                 \
+	 << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_DIS \
 						  Setting */
-#define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN                                       \
+#define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN \
 	((uint32_t)0x1UL) /**< OUT_EN_GPIO_OUT_EN_EN Value */
-#define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_EN                                       \
-	(MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN                                      \
-	 << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_EN      \
+#define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_EN                                  \
+	(MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN                                 \
+	 << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_EN \
 						  Setting */
 
 /**
@@ -342,10 +351,11 @@ typedef enum {
  * GPIO_OUT_EN to 1, without affecting other bits in that register.
  */
 #define MXC_F_GPIO_OUT_EN_SET_ALL_POS 0 /**< OUT_EN_SET_ALL Position */
-#define MXC_F_GPIO_OUT_EN_SET_ALL                                              \
-	((uint32_t)(                                                           \
-		0xFFFFFFFFUL                                                   \
-		<< MXC_F_GPIO_OUT_EN_SET_ALL_POS)) /**< OUT_EN_SET_ALL Mask */
+#define MXC_F_GPIO_OUT_EN_SET_ALL                                        \
+	((uint32_t)(0xFFFFFFFFUL                                         \
+		    << MXC_F_GPIO_OUT_EN_SET_ALL_POS)) /**<              \
+							  OUT_EN_SET_ALL \
+							  Mask */
 
 /**
  * GPIO Output Enable Clear Function Enable Register. Writing a 1 to
@@ -353,10 +363,11 @@ typedef enum {
  * GPIO_OUT_EN to 0, without affecting other bits in that register.
  */
 #define MXC_F_GPIO_OUT_EN_CLR_ALL_POS 0 /**< OUT_EN_CLR_ALL Position */
-#define MXC_F_GPIO_OUT_EN_CLR_ALL                                              \
-	((uint32_t)(                                                           \
-		0xFFFFFFFFUL                                                   \
-		<< MXC_F_GPIO_OUT_EN_CLR_ALL_POS)) /**< OUT_EN_CLR_ALL Mask */
+#define MXC_F_GPIO_OUT_EN_CLR_ALL                                        \
+	((uint32_t)(0xFFFFFFFFUL                                         \
+		    << MXC_F_GPIO_OUT_EN_CLR_ALL_POS)) /**<              \
+							  OUT_EN_CLR_ALL \
+							  Mask */
 
 /**
  * GPIO Output Register. Each bit controls the GPIO_OUT setting for
@@ -364,40 +375,47 @@ typedef enum {
  * directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers.
  */
 #define MXC_F_GPIO_OUT_GPIO_OUT_POS 0 /**< OUT_GPIO_OUT Position */
-#define MXC_F_GPIO_OUT_GPIO_OUT                                                \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_OUT_GPIO_OUT_POS)) /**< OUT_GPIO_OUT Mask */
-#define MXC_V_GPIO_OUT_GPIO_OUT_LOW                                            \
+#define MXC_F_GPIO_OUT_GPIO_OUT                                      \
+	((uint32_t)(0xFFFFFFFFUL                                     \
+		    << MXC_F_GPIO_OUT_GPIO_OUT_POS)) /**<            \
+							OUT_GPIO_OUT \
+							Mask */
+#define MXC_V_GPIO_OUT_GPIO_OUT_LOW \
 	((uint32_t)0x0UL) /**< OUT_GPIO_OUT_LOW Value */
-#define MXC_S_GPIO_OUT_GPIO_OUT_LOW                                            \
-	(MXC_V_GPIO_OUT_GPIO_OUT_LOW                                           \
-	 << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_LOW Setting */
-#define MXC_V_GPIO_OUT_GPIO_OUT_HIGH                                           \
+#define MXC_S_GPIO_OUT_GPIO_OUT_LOW                          \
+	(MXC_V_GPIO_OUT_GPIO_OUT_LOW                         \
+	 << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**<                \
+					    OUT_GPIO_OUT_LOW \
+					    Setting          \
+					  */
+#define MXC_V_GPIO_OUT_GPIO_OUT_HIGH \
 	((uint32_t)0x1UL) /**< OUT_GPIO_OUT_HIGH Value */
-#define MXC_S_GPIO_OUT_GPIO_OUT_HIGH                                           \
-	(MXC_V_GPIO_OUT_GPIO_OUT_HIGH                                          \
-	 << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_HIGH Setting */
+#define MXC_S_GPIO_OUT_GPIO_OUT_HIGH                          \
+	(MXC_V_GPIO_OUT_GPIO_OUT_HIGH                         \
+	 << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**<                 \
+					    OUT_GPIO_OUT_HIGH \
+					    Setting           \
+					  */
 
 /**
  * GPIO Output Set. Writing a 1 to one or more bits in this register
  * sets the bits in the same positions in GPIO_OUT to 1, without affecting other
  * bits in that register.
  */
-#define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS                                    \
+#define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS \
 	0 /**< OUT_SET_GPIO_OUT_SET Position */
-#define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET                                          \
-	((uint32_t)(                                                             \
-		0xFFFFFFFFUL                                                     \
-		<< MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS)) /**<                    \
-							    OUT_SET_GPIO_OUT_SET \
-							    Mask */
-#define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO                                     \
+#define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET                                              \
+	((uint32_t)(0xFFFFFFFFUL                                                     \
+		    << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS)) /**<                    \
+								OUT_SET_GPIO_OUT_SET \
+								Mask */
+#define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO \
 	((uint32_t)0x0UL) /**< OUT_SET_GPIO_OUT_SET_NO Value */
-#define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_NO                                     \
-	(MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO                                    \
-	 << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_NO  \
+#define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_NO                                    \
+	(MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO                                   \
+	 << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_NO \
 						    Setting */
-#define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET                                    \
+#define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET \
 	((uint32_t)0x1UL) /**< OUT_SET_GPIO_OUT_SET_SET Value */
 #define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_SET                                    \
 	(MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET                                   \
@@ -408,49 +426,48 @@ typedef enum {
  * clears the bits in the same positions in GPIO_OUT to 0, without affecting
  * other bits in that register.
  */
-#define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS                                    \
+#define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS \
 	0 /**< OUT_CLR_GPIO_OUT_CLR Position */
-#define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR                                          \
-	((uint32_t)(                                                             \
-		0xFFFFFFFFUL                                                     \
-		<< MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS)) /**<                    \
-							    OUT_CLR_GPIO_OUT_CLR \
-							    Mask */
+#define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR                                              \
+	((uint32_t)(0xFFFFFFFFUL                                                     \
+		    << MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS)) /**<                    \
+								OUT_CLR_GPIO_OUT_CLR \
+								Mask */
 
 /**
  * GPIO Input Register. Read-only register to read from the logic
  * states of the GPIO pins on this port.
  */
 #define MXC_F_GPIO_IN_GPIO_IN_POS 0 /**< IN_GPIO_IN Position */
-#define MXC_F_GPIO_IN_GPIO_IN                                                  \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_IN_GPIO_IN_POS)) /**< IN_GPIO_IN Mask */
+#define MXC_F_GPIO_IN_GPIO_IN                                                 \
+	((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IN_GPIO_IN_POS)) /**<          \
+								   IN_GPIO_IN \
+								   Mask */
 
 /**
  * GPIO Interrupt Mode Register. Each bit in this register controls
  * the interrupt mode setting for the associated GPIO pin on this port.
  */
-#define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS                                    \
+#define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS \
 	0 /**< INT_MOD_GPIO_INT_MOD Position */
-#define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD                                          \
-	((uint32_t)(                                                             \
-		0xFFFFFFFFUL                                                     \
-		<< MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS)) /**<                    \
-							    INT_MOD_GPIO_INT_MOD \
-							    Mask */
-#define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL                                  \
+#define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD                                              \
+	((uint32_t)(0xFFFFFFFFUL                                                     \
+		    << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS)) /**<                    \
+								INT_MOD_GPIO_INT_MOD \
+								Mask */
+#define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL \
 	((uint32_t)0x0UL) /**< INT_MOD_GPIO_INT_MOD_LEVEL Value */
 #define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL                                  \
 	(MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL                                 \
 	 << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**<                          \
 						    INT_MOD_GPIO_INT_MOD_LEVEL \
 						    Setting */
-#define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE                                   \
+#define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE \
 	((uint32_t)0x1UL) /**< INT_MOD_GPIO_INT_MOD_EDGE Value */
-#define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_EDGE                                   \
-	(MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE                                  \
-	 << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**<                          \
-						    INT_MOD_GPIO_INT_MOD_EDGE  \
+#define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_EDGE                                  \
+	(MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE                                 \
+	 << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**<                         \
+						    INT_MOD_GPIO_INT_MOD_EDGE \
 						    Setting */
 
 /**
@@ -458,22 +475,21 @@ typedef enum {
  * controls the interrupt polarity setting for one GPIO pin in the associated
  * port.
  */
-#define MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS                                    \
+#define MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS \
 	0 /**< INT_POL_GPIO_INT_POL Position */
-#define MXC_F_GPIO_INT_POL_GPIO_INT_POL                                          \
-	((uint32_t)(                                                             \
-		0xFFFFFFFFUL                                                     \
-		<< MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS)) /**<                    \
-							    INT_POL_GPIO_INT_POL \
-							    Mask */
-#define MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING                                \
+#define MXC_F_GPIO_INT_POL_GPIO_INT_POL                                              \
+	((uint32_t)(0xFFFFFFFFUL                                                     \
+		    << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS)) /**<                    \
+								INT_POL_GPIO_INT_POL \
+								Mask */
+#define MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING \
 	((uint32_t)0x0UL) /**< INT_POL_GPIO_INT_POL_FALLING Value */
 #define MXC_S_GPIO_INT_POL_GPIO_INT_POL_FALLING                                  \
 	(MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING                                 \
 	 << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) /**<                            \
 						    INT_POL_GPIO_INT_POL_FALLING \
 						    Setting */
-#define MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING                                 \
+#define MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING \
 	((uint32_t)0x1UL) /**< INT_POL_GPIO_INT_POL_RISING Value */
 #define MXC_S_GPIO_INT_POL_GPIO_INT_POL_RISING                                  \
 	(MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING                                 \
@@ -485,25 +501,25 @@ typedef enum {
  * GPIO Interrupt Enable Register. Each bit in this register controls
  * the GPIO interrupt enable for the associated pin on the GPIO port.
  */
-#define MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS                                      \
-	0 /**< INT_EN_GPIO_INT_EN Position                                     \
+#define MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS  \
+	0 /**< INT_EN_GPIO_INT_EN Position \
 	   */
-#define MXC_F_GPIO_INT_EN_GPIO_INT_EN                                          \
-	((uint32_t)(                                                           \
-		0xFFFFFFFFUL                                                   \
-		<< MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS)) /**< INT_EN_GPIO_INT_EN \
-							  Mask */
-#define MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS                                      \
+#define MXC_F_GPIO_INT_EN_GPIO_INT_EN                                            \
+	((uint32_t)(0xFFFFFFFFUL                                                 \
+		    << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS)) /**<                  \
+							      INT_EN_GPIO_INT_EN \
+							      Mask */
+#define MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS \
 	((uint32_t)0x0UL) /**< INT_EN_GPIO_INT_EN_DIS Value */
-#define MXC_S_GPIO_INT_EN_GPIO_INT_EN_DIS                                      \
-	(MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS                                     \
-	 << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_DIS     \
+#define MXC_S_GPIO_INT_EN_GPIO_INT_EN_DIS                                  \
+	(MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS                                 \
+	 << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_DIS \
 						  Setting */
-#define MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN                                       \
+#define MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN \
 	((uint32_t)0x1UL) /**< INT_EN_GPIO_INT_EN_EN Value */
-#define MXC_S_GPIO_INT_EN_GPIO_INT_EN_EN                                       \
-	(MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN                                      \
-	 << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_EN      \
+#define MXC_S_GPIO_INT_EN_GPIO_INT_EN_EN                                  \
+	(MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN                                 \
+	 << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_EN \
 						  Setting */
 
 /**
@@ -511,22 +527,21 @@ typedef enum {
  * register sets the bits in the same positions in GPIO_INT_EN to 1, without
  * affecting other bits in that register.
  */
-#define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS                              \
+#define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS \
 	0 /**< INT_EN_SET_GPIO_INT_EN_SET Position */
-#define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET                                                \
-	((uint32_t)(                                                                         \
-		0xFFFFFFFFUL                                                                 \
-		<< MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS)) /**<                          \
-								  INT_EN_SET_GPIO_INT_EN_SET \
-								  Mask */
-#define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO                               \
+#define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET                                                    \
+	((uint32_t)(0xFFFFFFFFUL                                                                 \
+		    << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS)) /**<                          \
+								      INT_EN_SET_GPIO_INT_EN_SET \
+								      Mask */
+#define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO \
 	((uint32_t)0x0UL) /**< INT_EN_SET_GPIO_INT_EN_SET_NO Value */
 #define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO                                        \
 	(MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO                                       \
 	 << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) /**<                             \
 							  INT_EN_SET_GPIO_INT_EN_SET_NO \
 							  Setting */
-#define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET                              \
+#define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET \
 	((uint32_t)0x1UL) /**< INT_EN_SET_GPIO_INT_EN_SET_SET Value */
 #define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET                                        \
 	(MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET                                       \
@@ -538,22 +553,21 @@ typedef enum {
  * this register clears the bits in the same positions in GPIO_INT_EN to 0,
  * without affecting other bits in that register.
  */
-#define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS                              \
+#define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS \
 	0 /**< INT_EN_CLR_GPIO_INT_EN_CLR Position */
-#define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR                                                \
-	((uint32_t)(                                                                         \
-		0xFFFFFFFFUL                                                                 \
-		<< MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS)) /**<                          \
-								  INT_EN_CLR_GPIO_INT_EN_CLR \
-								  Mask */
-#define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO                               \
+#define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR                                                    \
+	((uint32_t)(0xFFFFFFFFUL                                                                 \
+		    << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS)) /**<                          \
+								      INT_EN_CLR_GPIO_INT_EN_CLR \
+								      Mask */
+#define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO \
 	((uint32_t)0x0UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_NO Value */
 #define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO                                        \
 	(MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO                                       \
 	 << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) /**<                             \
 							  INT_EN_CLR_GPIO_INT_EN_CLR_NO \
 							  Setting */
-#define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR                            \
+#define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR \
 	((uint32_t)0x1UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR Value */
 #define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR                                        \
 	(MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR                                       \
@@ -564,22 +578,21 @@ typedef enum {
  * GPIO Interrupt Status Register. Each bit in this register contains
  * the pending interrupt status for the associated GPIO pin in this port.
  */
-#define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS                                  \
+#define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS \
 	0 /**< INT_STAT_GPIO_INT_STAT Position */
-#define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT                                            \
-	((uint32_t)(                                                                 \
-		0xFFFFFFFFUL                                                         \
-		<< MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS)) /**<                      \
-							      INT_STAT_GPIO_INT_STAT \
-							      Mask */
-#define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO                                   \
+#define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT                                                \
+	((uint32_t)(0xFFFFFFFFUL                                                         \
+		    << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS)) /**<                      \
+								  INT_STAT_GPIO_INT_STAT \
+								  Mask */
+#define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO \
 	((uint32_t)0x0UL) /**< INT_STAT_GPIO_INT_STAT_NO Value */
 #define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_NO                                    \
 	(MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO                                   \
 	 << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) /**<                         \
 						      INT_STAT_GPIO_INT_STAT_NO \
 						      Setting */
-#define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING                              \
+#define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING \
 	((uint32_t)0x1UL) /**< INT_STAT_GPIO_INT_STAT_PENDING Value */
 #define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_PENDING                                    \
 	(MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING                                   \
@@ -593,33 +606,34 @@ typedef enum {
  * affecting other bits in that register.
  */
 #define MXC_F_GPIO_INT_CLR_ALL_POS 0 /**< INT_CLR_ALL Position */
-#define MXC_F_GPIO_INT_CLR_ALL                                                 \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_INT_CLR_ALL_POS)) /**< INT_CLR_ALL Mask */
+#define MXC_F_GPIO_INT_CLR_ALL                                     \
+	((uint32_t)(0xFFFFFFFFUL                                   \
+		    << MXC_F_GPIO_INT_CLR_ALL_POS)) /**<           \
+						       INT_CLR_ALL \
+						       Mask */
 
 /**
  * GPIO Wake Enable Register. Each bit in this register controls the
  * PMU wakeup enable for the associated GPIO pin in this port.
  */
-#define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS                                    \
+#define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS \
 	0 /**< WAKE_EN_GPIO_WAKE_EN Position */
-#define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN                                          \
-	((uint32_t)(                                                             \
-		0xFFFFFFFFUL                                                     \
-		<< MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS)) /**<                    \
-							    WAKE_EN_GPIO_WAKE_EN \
-							    Mask */
-#define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS                                    \
+#define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN                                              \
+	((uint32_t)(0xFFFFFFFFUL                                                     \
+		    << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS)) /**<                    \
+								WAKE_EN_GPIO_WAKE_EN \
+								Mask */
+#define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS \
 	((uint32_t)0x0UL) /**< WAKE_EN_GPIO_WAKE_EN_DIS Value */
 #define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS                                    \
 	(MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS                                   \
 	 << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_DIS \
 						    Setting */
-#define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN                                     \
+#define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN \
 	((uint32_t)0x1UL) /**< WAKE_EN_GPIO_WAKE_EN_EN Value */
-#define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_EN                                     \
-	(MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN                                    \
-	 << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_EN  \
+#define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_EN                                    \
+	(MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN                                   \
+	 << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_EN \
 						    Setting */
 
 /**
@@ -628,9 +642,9 @@ typedef enum {
  * affecting other bits in that register.
  */
 #define MXC_F_GPIO_WAKE_EN_SET_ALL_POS 0 /**< WAKE_EN_SET_ALL Position */
-#define MXC_F_GPIO_WAKE_EN_SET_ALL                                             \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_WAKE_EN_SET_ALL_POS)) /**< WAKE_EN_SET_ALL   \
+#define MXC_F_GPIO_WAKE_EN_SET_ALL                                           \
+	((uint32_t)(0xFFFFFFFFUL                                             \
+		    << MXC_F_GPIO_WAKE_EN_SET_ALL_POS)) /**< WAKE_EN_SET_ALL \
 							   Mask */
 
 /**
@@ -639,32 +653,31 @@ typedef enum {
  * affecting other bits in that register.
  */
 #define MXC_F_GPIO_WAKE_EN_CLR_ALL_POS 0 /**< WAKE_EN_CLR_ALL Position */
-#define MXC_F_GPIO_WAKE_EN_CLR_ALL                                             \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_WAKE_EN_CLR_ALL_POS)) /**< WAKE_EN_CLR_ALL   \
+#define MXC_F_GPIO_WAKE_EN_CLR_ALL                                           \
+	((uint32_t)(0xFFFFFFFFUL                                             \
+		    << MXC_F_GPIO_WAKE_EN_CLR_ALL_POS)) /**< WAKE_EN_CLR_ALL \
 							   Mask */
 
 /**
  * GPIO Interrupt Dual Edge Mode Register. Each bit in this register
  * selects dual edge mode for the associated GPIO pin in this port.
  */
-#define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS                        \
+#define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS \
 	0 /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE Position */
-#define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE                                                      \
-	((uint32_t)(                                                                                     \
-		0xFFFFFFFFUL                                                                             \
-		<< MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS)) /**<                                \
-									INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE \
-									Mask                             \
-								      */
-#define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO                         \
+#define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE                                                          \
+	((uint32_t)(0xFFFFFFFFUL                                                                             \
+		    << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS)) /**<                                \
+									    INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE \
+									    Mask                             \
+									  */
+#define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO \
 	((uint32_t)0x0UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO Value */
 #define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO                                              \
 	(MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO                                             \
 	 << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) /**<                                   \
 								INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO \
 								Setting */
-#define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN                         \
+#define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN \
 	((uint32_t)0x1UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN Value */
 #define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN                                              \
 	(MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN                                             \
@@ -676,29 +689,28 @@ typedef enum {
  * GPIO Input Mode Config 1. Each bit in this register enables the
  * weak pull-up for the associated GPIO pin in this port.
  */
-#define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS                                  \
+#define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS \
 	0 /**< PAD_CFG1_GPIO_PAD_CFG1 Position */
-#define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1                                            \
-	((uint32_t)(                                                                 \
-		0xFFFFFFFFUL                                                         \
-		<< MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS)) /**<                      \
-							      PAD_CFG1_GPIO_PAD_CFG1 \
-							      Mask */
-#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE                            \
+#define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1                                                \
+	((uint32_t)(0xFFFFFFFFUL                                                         \
+		    << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS)) /**<                      \
+								  PAD_CFG1_GPIO_PAD_CFG1 \
+								  Mask */
+#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE \
 	((uint32_t)0x0UL) /**< PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE Value */
 #define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE                                    \
 	(MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE                                   \
 	 << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**<                                \
 						      PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE \
 						      Setting */
-#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU                                   \
+#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU \
 	((uint32_t)0x1UL) /**< PAD_CFG1_GPIO_PAD_CFG1_PU Value */
 #define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU                                    \
 	(MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU                                   \
 	 << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**<                         \
 						      PAD_CFG1_GPIO_PAD_CFG1_PU \
 						      Setting */
-#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD                                   \
+#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD \
 	((uint32_t)0x2UL) /**< PAD_CFG1_GPIO_PAD_CFG1_PD Value */
 #define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD                                    \
 	(MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD                                   \
@@ -710,29 +722,28 @@ typedef enum {
  * GPIO Input Mode Config 2. Each bit in this register enables the
  * weak pull-up for the associated GPIO pin in this port.
  */
-#define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS                                  \
+#define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS \
 	0 /**< PAD_CFG2_GPIO_PAD_CFG2 Position */
-#define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2                                            \
-	((uint32_t)(                                                                 \
-		0xFFFFFFFFUL                                                         \
-		<< MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS)) /**<                      \
-							      PAD_CFG2_GPIO_PAD_CFG2 \
-							      Mask */
-#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE                            \
+#define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2                                                \
+	((uint32_t)(0xFFFFFFFFUL                                                         \
+		    << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS)) /**<                      \
+								  PAD_CFG2_GPIO_PAD_CFG2 \
+								  Mask */
+#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE \
 	((uint32_t)0x0UL) /**< PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE Value */
 #define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE                                    \
 	(MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE                                   \
 	 << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**<                                \
 						      PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE \
 						      Setting */
-#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU                                   \
+#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU \
 	((uint32_t)0x1UL) /**< PAD_CFG2_GPIO_PAD_CFG2_PU Value */
 #define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU                                    \
 	(MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU                                   \
 	 << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**<                         \
 						      PAD_CFG2_GPIO_PAD_CFG2_PU \
 						      Setting */
-#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD                                   \
+#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD \
 	((uint32_t)0x2UL) /**< PAD_CFG2_GPIO_PAD_CFG2_PD Value */
 #define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD                                    \
 	(MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD                                   \
@@ -746,19 +757,24 @@ typedef enum {
  * this port.
  */
 #define MXC_F_GPIO_EN1_GPIO_EN1_POS 0 /**< EN1_GPIO_EN1 Position */
-#define MXC_F_GPIO_EN1_GPIO_EN1                                                \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_EN1_GPIO_EN1_POS)) /**< EN1_GPIO_EN1 Mask */
-#define MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY                                        \
+#define MXC_F_GPIO_EN1_GPIO_EN1                                      \
+	((uint32_t)(0xFFFFFFFFUL                                     \
+		    << MXC_F_GPIO_EN1_GPIO_EN1_POS)) /**<            \
+							EN1_GPIO_EN1 \
+							Mask */
+#define MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY \
 	((uint32_t)0x0UL) /**< EN1_GPIO_EN1_PRIMARY Value */
-#define MXC_S_GPIO_EN1_GPIO_EN1_PRIMARY                                        \
-	(MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY                                       \
-	 << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_PRIMARY Setting */
-#define MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY                                      \
+#define MXC_S_GPIO_EN1_GPIO_EN1_PRIMARY                          \
+	(MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY                         \
+	 << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**<                    \
+					    EN1_GPIO_EN1_PRIMARY \
+					    Setting              \
+					  */
+#define MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY \
 	((uint32_t)0x1UL) /**< EN1_GPIO_EN1_SECONDARY Value */
-#define MXC_S_GPIO_EN1_GPIO_EN1_SECONDARY                                      \
-	(MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY                                     \
-	 << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_SECONDARY Setting   \
+#define MXC_S_GPIO_EN1_GPIO_EN1_SECONDARY                                    \
+	(MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY                                   \
+	 << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_SECONDARY Setting \
 					  */
 
 /**
@@ -767,9 +783,11 @@ typedef enum {
  * affecting other bits in that register.
  */
 #define MXC_F_GPIO_EN1_SET_ALL_POS 0 /**< EN1_SET_ALL Position */
-#define MXC_F_GPIO_EN1_SET_ALL                                                 \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_EN1_SET_ALL_POS)) /**< EN1_SET_ALL Mask */
+#define MXC_F_GPIO_EN1_SET_ALL                                     \
+	((uint32_t)(0xFFFFFFFFUL                                   \
+		    << MXC_F_GPIO_EN1_SET_ALL_POS)) /**<           \
+						       EN1_SET_ALL \
+						       Mask */
 
 /**
  * GPIO Alternate Function Clear. Writing a 1 to one or more bits in
@@ -777,9 +795,11 @@ typedef enum {
  * affecting other bits in that register.
  */
 #define MXC_F_GPIO_EN1_CLR_ALL_POS 0 /**< EN1_CLR_ALL Position */
-#define MXC_F_GPIO_EN1_CLR_ALL                                                 \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_EN1_CLR_ALL_POS)) /**< EN1_CLR_ALL Mask */
+#define MXC_F_GPIO_EN1_CLR_ALL                                     \
+	((uint32_t)(0xFFFFFFFFUL                                   \
+		    << MXC_F_GPIO_EN1_CLR_ALL_POS)) /**<           \
+						       EN1_CLR_ALL \
+						       Mask */
 
 /**
  * GPIO Alternate Function Enable Register. Each bit in this register
@@ -787,19 +807,24 @@ typedef enum {
  * this port.
  */
 #define MXC_F_GPIO_EN2_GPIO_EN2_POS 0 /**< EN2_GPIO_EN2 Position */
-#define MXC_F_GPIO_EN2_GPIO_EN2                                                \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_EN2_GPIO_EN2_POS)) /**< EN2_GPIO_EN2 Mask */
-#define MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY                                        \
+#define MXC_F_GPIO_EN2_GPIO_EN2                                      \
+	((uint32_t)(0xFFFFFFFFUL                                     \
+		    << MXC_F_GPIO_EN2_GPIO_EN2_POS)) /**<            \
+							EN2_GPIO_EN2 \
+							Mask */
+#define MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY \
 	((uint32_t)0x0UL) /**< EN2_GPIO_EN2_PRIMARY Value */
-#define MXC_S_GPIO_EN2_GPIO_EN2_PRIMARY                                        \
-	(MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY                                       \
-	 << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_PRIMARY Setting */
-#define MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY                                      \
+#define MXC_S_GPIO_EN2_GPIO_EN2_PRIMARY                          \
+	(MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY                         \
+	 << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**<                    \
+					    EN2_GPIO_EN2_PRIMARY \
+					    Setting              \
+					  */
+#define MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY \
 	((uint32_t)0x1UL) /**< EN2_GPIO_EN2_SECONDARY Value */
-#define MXC_S_GPIO_EN2_GPIO_EN2_SECONDARY                                      \
-	(MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY                                     \
-	 << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_SECONDARY Setting   \
+#define MXC_S_GPIO_EN2_GPIO_EN2_SECONDARY                                    \
+	(MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY                                   \
+	 << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_SECONDARY Setting \
 					  */
 
 /**
@@ -808,9 +833,11 @@ typedef enum {
  * affecting other bits in that register.
  */
 #define MXC_F_GPIO_EN2_SET_ALL_POS 0 /**< EN2_SET_ALL Position */
-#define MXC_F_GPIO_EN2_SET_ALL                                                 \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_EN2_SET_ALL_POS)) /**< EN2_SET_ALL Mask */
+#define MXC_F_GPIO_EN2_SET_ALL                                     \
+	((uint32_t)(0xFFFFFFFFUL                                   \
+		    << MXC_F_GPIO_EN2_SET_ALL_POS)) /**<           \
+						       EN2_SET_ALL \
+						       Mask */
 
 /**
  * GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits
@@ -818,9 +845,11 @@ typedef enum {
  * without affecting other bits in that register.
  */
 #define MXC_F_GPIO_EN2_CLR_ALL_POS 0 /**< EN2_CLR_ALL Position */
-#define MXC_F_GPIO_EN2_CLR_ALL                                                 \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_EN2_CLR_ALL_POS)) /**< EN2_CLR_ALL Mask */
+#define MXC_F_GPIO_EN2_CLR_ALL                                     \
+	((uint32_t)(0xFFFFFFFFUL                                   \
+		    << MXC_F_GPIO_EN2_CLR_ALL_POS)) /**<           \
+						       EN2_CLR_ALL \
+						       Mask */
 
 /**
  * GPIO Drive Strength  Register. Each bit in this register selects
@@ -828,13 +857,13 @@ typedef enum {
  * Datasheet for sink/source current of GPIO pins in each mode.
  */
 #define MXC_F_GPIO_DS_DS_POS 0 /**< DS_DS Position */
-#define MXC_F_GPIO_DS_DS                                                       \
+#define MXC_F_GPIO_DS_DS \
 	((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS_DS_POS)) /**< DS_DS Mask */
 #define MXC_V_GPIO_DS_DS_LD ((uint32_t)0x0UL) /**< DS_DS_LD Value */
-#define MXC_S_GPIO_DS_DS_LD                                                    \
+#define MXC_S_GPIO_DS_DS_LD \
 	(MXC_V_GPIO_DS_DS_LD << MXC_F_GPIO_DS_DS_POS) /**< DS_DS_LD Setting */
-#define MXC_V_GPIO_DS_DS_HD ((uint32_t)0x1UL)	 /**< DS_DS_HD Value */
-#define MXC_S_GPIO_DS_DS_HD                                                    \
+#define MXC_V_GPIO_DS_DS_HD ((uint32_t)0x1UL) /**< DS_DS_HD Value */
+#define MXC_S_GPIO_DS_DS_HD \
 	(MXC_V_GPIO_DS_DS_HD << MXC_F_GPIO_DS_DS_POS) /**< DS_DS_HD Setting */
 
 /**
@@ -844,23 +873,23 @@ typedef enum {
  */
 #define MXC_F_GPIO_DS1_ALL_POS 0 /**< DS1_ALL Position */
 #define MXC_F_GPIO_DS1_ALL                                                     \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_DS1_ALL_POS)) /**< DS1_ALL Mask */
+	((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS1_ALL_POS)) /**< DS1_ALL Mask \
+							      */
 
 /**
  * GPIO Pull Select Mode.
  */
 #define MXC_F_GPIO_PS_ALL_POS 0 /**< PS_ALL Position */
-#define MXC_F_GPIO_PS_ALL                                                      \
-	((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PS_ALL_POS)) /**< PS_ALL Mask   \
+#define MXC_F_GPIO_PS_ALL                                                    \
+	((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PS_ALL_POS)) /**< PS_ALL Mask \
 							     */
 
 /**
  * GPIO Voltage Select.
  */
 #define MXC_F_GPIO_VSSEL_ALL_POS 0 /**< VSSEL_ALL Position */
-#define MXC_F_GPIO_VSSEL_ALL                                                   \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_VSSEL_ALL_POS)) /**< VSSEL_ALL Mask */
+#define MXC_F_GPIO_VSSEL_ALL                                                  \
+	((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_VSSEL_ALL_POS)) /**< VSSEL_ALL \
+								  Mask */
 
 #endif /* _GPIO_REGS_H_ */
diff --git a/chip/max32660/hwtimer_chip.c b/chip/max32660/hwtimer_chip.c
index 5417e161b2..b6c39f4036 100644
--- a/chip/max32660/hwtimer_chip.c
+++ b/chip/max32660/hwtimer_chip.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,15 +6,15 @@
 /* MAX32660 HW Timer module for Chrome EC */
 
 #include "clock.h"
-#include "console.h"
 #include "common.h"
+#include "console.h"
+#include "gcr_regs.h"
 #include "hooks.h"
 #include "hwtimer.h"
+#include "registers.h"
 #include "task.h"
 #include "timer.h"
-#include "registers.h"
 #include "tmr_regs.h"
-#include "gcr_regs.h"
 
 /* Define the rollover timer */
 #define TMR_ROLLOVER MXC_TMR0
@@ -41,36 +41,36 @@ static uint32_t last_deadline;
 
 /* brief Timer prescaler values */
 enum tmr_pres {
-	TMR_PRES_1 = MXC_V_TMR_CN_PRES_DIV1,     /// Divide input clock by 1
-	TMR_PRES_2 = MXC_V_TMR_CN_PRES_DIV2,     /// Divide input clock by 2
-	TMR_PRES_4 = MXC_V_TMR_CN_PRES_DIV4,     /// Divide input clock by 4
-	TMR_PRES_8 = MXC_V_TMR_CN_PRES_DIV8,     /// Divide input clock by 8
-	TMR_PRES_16 = MXC_V_TMR_CN_PRES_DIV16,   /// Divide input clock by 16
-	TMR_PRES_32 = MXC_V_TMR_CN_PRES_DIV32,   /// Divide input clock by 32
-	TMR_PRES_64 = MXC_V_TMR_CN_PRES_DIV64,   /// Divide input clock by 64
+	TMR_PRES_1 = MXC_V_TMR_CN_PRES_DIV1, /// Divide input clock by 1
+	TMR_PRES_2 = MXC_V_TMR_CN_PRES_DIV2, /// Divide input clock by 2
+	TMR_PRES_4 = MXC_V_TMR_CN_PRES_DIV4, /// Divide input clock by 4
+	TMR_PRES_8 = MXC_V_TMR_CN_PRES_DIV8, /// Divide input clock by 8
+	TMR_PRES_16 = MXC_V_TMR_CN_PRES_DIV16, /// Divide input clock by 16
+	TMR_PRES_32 = MXC_V_TMR_CN_PRES_DIV32, /// Divide input clock by 32
+	TMR_PRES_64 = MXC_V_TMR_CN_PRES_DIV64, /// Divide input clock by 64
 	TMR_PRES_128 = MXC_V_TMR_CN_PRES_DIV128, /// Divide input clock by 128
-	TMR_PRES_256 =
-		(0x20 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock by 256
-	TMR_PRES_512 =
-		(0x21 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock by 512
-	TMR_PRES_1024 =
-		(0x22 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock by 1024
-	TMR_PRES_2048 =
-		(0x23 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock by 2048
-	TMR_PRES_4096 =
-		(0x24 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock by 4096
+	TMR_PRES_256 = (0x20 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock
+							/// by 256
+	TMR_PRES_512 = (0x21 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock
+							/// by 512
+	TMR_PRES_1024 = (0x22 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock
+							 /// by 1024
+	TMR_PRES_2048 = (0x23 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock
+							 /// by 2048
+	TMR_PRES_4096 = (0x24 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock
+							 /// by 4096
 };
 
 /* Timer modes */
 enum tmr_mode {
 	TMR_MODE_ONESHOT = MXC_V_TMR_CN_TMODE_ONESHOT, /// Timer Mode ONESHOT
-	TMR_MODE_CONTINUOUS =
-		MXC_V_TMR_CN_TMODE_CONTINUOUS,	 /// Timer Mode CONTINUOUS
+	TMR_MODE_CONTINUOUS = MXC_V_TMR_CN_TMODE_CONTINUOUS, /// Timer Mode
+							     /// CONTINUOUS
 	TMR_MODE_COUNTER = MXC_V_TMR_CN_TMODE_COUNTER, /// Timer Mode COUNTER
-	TMR_MODE_PWM = MXC_V_TMR_CN_TMODE_PWM,	 /// Timer Mode PWM
+	TMR_MODE_PWM = MXC_V_TMR_CN_TMODE_PWM, /// Timer Mode PWM
 	TMR_MODE_CAPTURE = MXC_V_TMR_CN_TMODE_CAPTURE, /// Timer Mode CAPTURE
 	TMR_MODE_COMPARE = MXC_V_TMR_CN_TMODE_COMPARE, /// Timer Mode COMPARE
-	TMR_MODE_GATED = MXC_V_TMR_CN_TMODE_GATED,     /// Timer Mode GATED
+	TMR_MODE_GATED = MXC_V_TMR_CN_TMODE_GATED, /// Timer Mode GATED
 	TMR_MODE_CAPTURE_COMPARE =
 		MXC_V_TMR_CN_TMODE_CAPTURECOMPARE /// Timer Mode CAPTURECOMPARE
 };
@@ -220,7 +220,7 @@ int __hw_clock_source_init(uint32_t start_t)
 	return TMR_EVENT_IRQ;
 }
 
-static int hwtimer_display(int argc, char **argv)
+static int hwtimer_display(int argc, const char **argv)
 {
 	CPRINTS(" TMR_EVENT count 0x%08x", TMR_EVENT->cnt);
 	CPRINTS(" TMR_ROLLOVER count 0x%08x", TMR_ROLLOVER->cnt);
diff --git a/chip/max32660/i2c_chip.c b/chip/max32660/i2c_chip.c
index 1279e9e50c..1e4dd3f365 100644
--- a/chip/max32660/i2c_chip.c
+++ b/chip/max32660/i2c_chip.c
@@ -1,32 +1,34 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* MAX32660 I2C port module for Chrome EC. */
 
-#include <stdint.h>
-#include <stddef.h>
 #include "common.h"
 #include "config_chip.h"
+#include "gpio.h"
 #include "hooks.h"
 #include "i2c.h"
+#include "i2c_regs.h"
+#include "registers.h"
 #include "stdbool.h"
 #include "system.h"
 #include "task.h"
-#include "registers.h"
-#include "i2c_regs.h"
+
+#include <stddef.h>
+#include <stdint.h>
 
 /**
  * Byte to use if the EC HOST requested more data
- * than the I2C Slave is able to send.
+ * than the I2C Target is able to send.
  */
 #define EC_PADDING_BYTE 0xec
 
 /* **** Definitions **** */
-#define I2C_ERROR \
-	(MXC_F_I2C_INT_FL0_ARB_ER | MXC_F_I2C_INT_FL0_TO_ER | \
-	 MXC_F_I2C_INT_FL0_ADDR_NACK_ER | MXC_F_I2C_INT_FL0_DATA_ER | \
+#define I2C_ERROR                                                        \
+	(MXC_F_I2C_INT_FL0_ARB_ER | MXC_F_I2C_INT_FL0_TO_ER |            \
+	 MXC_F_I2C_INT_FL0_ADDR_NACK_ER | MXC_F_I2C_INT_FL0_DATA_ER |    \
 	 MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER | MXC_F_I2C_INT_FL0_START_ER | \
 	 MXC_F_I2C_INT_FL0_STOP_ER)
 
@@ -34,7 +36,7 @@
 #define T_HIGH_MIN (60) /* tHIGH minimum in nanoseconds */
 #define T_R_MAX_HS (40) /* tR maximum for high speed mode in nanoseconds */
 #define T_F_MAX_HS (40) /* tF maximum for high speed mode in nanoseconds */
-#define T_AF_MIN (10)	/* tAF minimun in nanoseconds */
+#define T_AF_MIN (10) /* tAF minimun in nanoseconds */
 
 /**
  * typedef i2c_speed_t - I2C speed modes.
@@ -59,23 +61,24 @@ typedef enum {
 } i2c_autoflush_disable_t;
 
 /**
- * typedef i2c_master_state_t - Available transaction states for I2C Master.
+ * typedef i2c_controller_state_t - Available transaction states for I2C
+ * Controller.
  */
 typedef enum {
-	I2C_MASTER_IDLE = 1,
-	I2C_MASTER_START = 2,
-	I2C_MASTER_WRITE_COMPLETE = 3,
-	I2C_MASTER_READ_COMPLETE = 4
-} i2c_master_state_t;
+	I2C_CONTROLLER_IDLE = 1,
+	I2C_CONTROLLER_START = 2,
+	I2C_CONTROLLER_WRITE_COMPLETE = 3,
+	I2C_CONTROLLER_READ_COMPLETE = 4
+} i2c_controller_state_t;
 
 /**
- * typedef i2c_slave_state_t - Available transaction states for I2C Slave.
+ * typedef i2c_target_state_t - Available transaction states for I2C Target.
  */
 typedef enum {
-	I2C_SLAVE_WRITE_COMPLETE = 0,
-	I2C_SLAVE_ADDR_MATCH_READ = 1,
-	I2C_SLAVE_ADDR_MATCH_WRITE = 2,
-} i2c_slave_state_t;
+	I2C_TARGET_WRITE_COMPLETE = 0,
+	I2C_TARGET_ADDR_MATCH_READ = 1,
+	I2C_TARGET_ADDR_MATCH_WRITE = 2,
+} i2c_target_state_t;
 
 /**
  * typedef i2c_req_t - I2C Transaction request.
@@ -93,29 +96,29 @@ typedef struct {
 /**
  * struct i2c_req - I2C Transaction request.
  * @addr: I2C 7-bit Address right aligned, bit 6 to bit 0.
- * 	  Only supports 7-bit addressing. LSb of the given
- * 	  address will be used as the read/write bit, the addr
- * 	  will not be shifted. Used for both master and slave
- * 	  transactions.
- * @addr_match_flag: Indicates which slave address was matched.
- *                   0x1 indicates first slave address matched.
- *                   0x2 indicates second slave address matched.
- *                   0x4 indicates third slave address matched.
- *                   0x8 indicates fourth slave address matched.
- * @tx_data: Data for master write/slave read.
- * @rx_data: Data for master read/slave write.
+ *        Only supports 7-bit addressing. LSb of the given
+ *        address will be used as the read/write bit, the addr
+ *        will not be shifted. Used for both controller and target
+ *        transactions.
+ * @addr_match_flag: Indicates which target address was matched.
+ *                   0x1 indicates first target address matched.
+ *                   0x2 indicates second target address matched.
+ *                   0x4 indicates third target address matched.
+ *                   0x8 indicates fourth target address matched.
+ * @tx_data: Data for controller write/target read.
+ * @rx_data: Data for controller read/target write.
  * @received_count:  Number of rx bytes sent.
- * @tx_remain: Number of bytes to transmit to the master. This
+ * @tx_remain: Number of bytes to transmit to the controller. This
  *             value is -1 if should clock stretch, 0 if start
  *             sending EC_PADDING_BYTE.  Any other values in this
- *             field will transmit data to the Master.
- * @state: I2C slave state that indicates address match, read and
+ *             field will transmit data to the Controller.
+ * @state: I2C target state that indicates address match, read and
  *         write status.
  * @restart: Restart or stop bit indicator.
  *           0 to send a stop bit at the end of the transaction
  *           Non-zero to send a restart at end of the transaction
- *           Only used for Master transactions.
- * @response_pending: Indicates that a response to the I2C master
+ *           Only used for Controller transactions.
+ * @response_pending: Indicates that a response to the I2C controller
  *           is pending.
  * @expecting_done: Indicates if an I2C done flag is expected. This
  *           is used by the driver to determine the order to process
@@ -129,9 +132,9 @@ struct i2c_req {
 	uint8_t addr_match_flag;
 	const uint8_t *tx_data;
 	uint8_t *rx_data;
-	volatile unsigned received_count;
+	volatile unsigned int received_count;
 	volatile int tx_remain;
-	volatile i2c_slave_state_t state;
+	volatile i2c_target_state_t state;
 	volatile int restart;
 	volatile bool response_pending;
 	volatile bool expecting_done;
@@ -167,35 +170,35 @@ static struct i2c_port_data pdata[I2C_PORT_COUNT];
 
 /* **** Function Prototypes **** */
 static int i2c_init_peripheral(mxc_i2c_regs_t *i2c, i2c_speed_t i2cspeed);
-static int i2c_master_write(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
-			    int stop, const uint8_t *data, int len,
-			    int restart);
-static int i2c_master_read(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
-			   int stop, uint8_t *data, int len, int restart);
+static int i2c_controller_write(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
+				int stop, const uint8_t *data, int len,
+				int restart);
+static int i2c_controller_read(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
+			       int stop, uint8_t *data, int len, int restart);
 
-#ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS
+#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
 static void init_i2cs(int port);
-static int i2c_slave_async(mxc_i2c_regs_t *i2c, i2c_req_t *req);
-static void i2c_slave_handler(mxc_i2c_regs_t *i2c);
-#endif /* CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS */
+static int i2c_target_async(mxc_i2c_regs_t *i2c, i2c_req_t *req);
+static void i2c_target_handler(mxc_i2c_regs_t *i2c);
+#endif /* CONFIG_HOSTCMD_I2C_ADDR_FLAGS */
 
 /* Port address for each I2C */
-static mxc_i2c_regs_t *i2c_bus_ports[] = {MXC_I2C0, MXC_I2C1};
+static mxc_i2c_regs_t *i2c_bus_ports[] = { MXC_I2C0, MXC_I2C1 };
 
-#ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS
+#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
 
-#ifdef CONFIG_BOARD_I2C_SLAVE_ADDR_FLAGS
+#ifdef CONFIG_BOARD_I2C_ADDR_FLAGS
 static void i2c_send_board_response(int len);
 static void i2c_process_board_command(int read, int addr, int len);
 void board_i2c_process(int read, uint8_t addr, int len, char *buffer,
 		       void (*send_response)(int len));
-#endif /* CONFIG_BOARD_I2C_SLAVE_ADDR_FLAGS */
-#endif /* CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS */
+#endif /* CONFIG_BOARD_I2C_ADDR_FLAGS */
+#endif /* CONFIG_HOSTCMD_I2C_ADDR_FLAGS */
 
 /**
- * chip_i2c_xfer() - Low Level function for I2C Master Reads and Writes.
+ * chip_i2c_xfer() - Low Level function for I2C Controller Reads and Writes.
  * @port: Port to access
- * @slave_addr:	Slave device address
+ * @addr_flags:	Device address and flags
  * @out: Data to send
  * @out_size: Number of bytes to send
  * @in: Destination buffer for received data
@@ -210,7 +213,7 @@ void board_i2c_process(int read, uint8_t addr, int len, char *buffer,
  *
  * Return EC_SUCCESS, or non-zero if error.
  */
-int chip_i2c_xfer(int port, const uint16_t slave_addr_flags, const uint8_t *out,
+int chip_i2c_xfer(int port, const uint16_t addr_flags, const uint8_t *out,
 		  int out_size, uint8_t *in, int in_size, int flags)
 {
 	int xfer_start;
@@ -221,16 +224,17 @@ int chip_i2c_xfer(int port, const uint16_t slave_addr_flags, const uint8_t *out,
 	xfer_stop = flags & I2C_XFER_STOP;
 
 	if (out_size) {
-		status = i2c_master_write(i2c_bus_ports[port], slave_addr_flags,
-					  xfer_start, xfer_stop, out, out_size,
-					  1);
+		status = i2c_controller_write(i2c_bus_ports[port], addr_flags,
+					      xfer_start, xfer_stop, out,
+					      out_size, 1);
 		if (status != EC_SUCCESS) {
 			return status;
 		}
 	}
 	if (in_size) {
-		status = i2c_master_read(i2c_bus_ports[port], slave_addr_flags,
-					 xfer_start, xfer_stop, in, in_size, 0);
+		status = i2c_controller_read(i2c_bus_ports[port], addr_flags,
+					     xfer_start, xfer_stop, in, in_size,
+					     0);
 		if (status != EC_SUCCESS) {
 			return status;
 		}
@@ -280,34 +284,33 @@ void i2c_init(void)
 		i2c_set_timeout(i, 0);
 	}
 
-#ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS
-	/* Initialize the I2C Slave */
+#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
+	/* Initialize the I2C Target */
 	init_i2cs(I2C_PORT_EC);
-#ifdef CONFIG_BOARD_I2C_SLAVE_ADDR_FLAGS
+#ifdef CONFIG_BOARD_I2C_ADDR_FLAGS
 	/*
-	 * Set the secondary I2C slave address for the board.
+	 * Set the secondary I2C target address for the board.
 	 */
-	/* Index the secondary slave address. */
-	i2c_bus_ports[I2C_PORT_EC]->slave_addr =
-		(i2c_bus_ports[I2C_PORT_EC]->slave_addr &
-		 ~(MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX |
-		   MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS)) |
-		(1 << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX_POS);
-	/* Set the secondary slave address. */
-	i2c_bus_ports[I2C_PORT_EC]->slave_addr =
-		(1 << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX_POS) |
-		CONFIG_BOARD_I2C_SLAVE_ADDR_FLAGS;
-#endif /* CONFIG_BOARD_I2C_SLAVE_ADDR_FLAGS */
-#endif /* CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS */
-
+	/* Index the secondary target address. */
+	i2c_bus_ports[I2C_PORT_EC]->target_addr =
+		(i2c_bus_ports[I2C_PORT_EC]->target_addr &
+		 ~(MXC_F_I2C_TARGET_ADDR_TARGET_ADDR_IDX |
+		   MXC_F_I2C_TARGET_ADDR_TARGET_ADDR_DIS)) |
+		(1 << MXC_F_I2C_TARGET_ADDR_TARGET_ADDR_IDX_POS);
+	/* Set the secondary target address. */
+	i2c_bus_ports[I2C_PORT_EC]->target_addr =
+		(1 << MXC_F_I2C_TARGET_ADDR_TARGET_ADDR_IDX_POS) |
+		CONFIG_BOARD_I2C_ADDR_FLAGS;
+#endif /* CONFIG_BOARD_I2C_ADDR_FLAGS */
+#endif /* CONFIG_HOSTCMD_I2C_ADDR_FLAGS */
 }
 
 /**
- *  I2C Slave Implentation
+ *  I2C Peripheral Implementation
  */
-#ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS
+#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
 /* IRQ for each I2C */
-static uint32_t i2c_bus_irqs[] = {EC_I2C0_IRQn, EC_I2C1_IRQn};
+static uint32_t i2c_bus_irqs[] = { EC_I2C0_IRQn, EC_I2C1_IRQn };
 
 /**
  * Buffer for received host command packets (including prefix byte on request,
@@ -320,7 +323,7 @@ static uint8_t *const host_buffer = host_buffer_padded + 2;
 static uint8_t params_copy[I2C_MAX_HOST_PACKET_SIZE] __aligned(4);
 static struct host_packet i2c_packet;
 
-static i2c_req_t req_slave;
+static i2c_req_t req_target;
 volatile int ec_pending_response = 0;
 
 /**
@@ -341,11 +344,11 @@ static void i2c_send_response_packet(struct host_packet *pkt)
 	*out++ = size;
 
 	/* Host_buffer data range. */
-	req_slave.tx_remain = size + 2;
-	req_slave.response_pending = true;
+	req_target.tx_remain = size + 2;
+	req_target.response_pending = true;
 
 	/* Call the handler to send the response packet. */
-	i2c_slave_handler(i2c_bus_ports[I2C_PORT_EC]);
+	i2c_target_handler(i2c_bus_ports[I2C_PORT_EC]);
 }
 
 /**
@@ -383,24 +386,24 @@ static void i2c_process_command(void)
 }
 
 /**
- * i2c_slave_service() - Called by the I2C slave interrupt controller.
+ * i2c_target_service() - Called by the I2C target interrupt controller.
  * @req:   Request currently being processed.
  */
-void i2c_slave_service(i2c_req_t *req)
+void i2c_target_service(i2c_req_t *req)
 {
-	/* Check if there was a host command (I2C master write). */
-	if (req->state == I2C_SLAVE_ADDR_MATCH_WRITE) {
-		req->state = I2C_SLAVE_WRITE_COMPLETE;
+	/* Check if there was a host command (I2C controller write). */
+	if (req->state == I2C_TARGET_ADDR_MATCH_WRITE) {
+		req->state = I2C_TARGET_WRITE_COMPLETE;
 		/* A response to this write is pending. */
 		/* Assume that there is nothing to send back to the HOST. */
 		req->tx_remain = -1;
-#ifdef CONFIG_BOARD_I2C_SLAVE_ADDR_FLAGS
+#ifdef CONFIG_BOARD_I2C_ADDR_FLAGS
 		if (req->addr_match_flag != 0x1) {
-			i2c_process_board_command(
-				0, CONFIG_BOARD_I2C_SLAVE_ADDR_FLAGS,
-				req->received_count);
+			i2c_process_board_command(0,
+						  CONFIG_BOARD_I2C_ADDR_FLAGS,
+						  req->received_count);
 		} else
-#endif /* CONFIG_BOARD_I2C_SLAVE_ADDR_FLAGS */
+#endif /* CONFIG_BOARD_I2C_ADDR_FLAGS */
 		{
 			i2c_process_command();
 		}
@@ -408,38 +411,39 @@ void i2c_slave_service(i2c_req_t *req)
 }
 
 /**
- * I2C0_IRQHandler() - Async Handler for I2C Slave driver.
+ * I2C0_IRQHandler() - Async Handler for I2C Target driver.
  */
-void I2C0_IRQHandler(void)
+static void I2C0_IRQHandler(void)
 {
-	i2c_slave_handler(i2c_bus_ports[0]);
+	i2c_target_handler(i2c_bus_ports[0]);
 }
 
 /**
- * I2C1_IRQHandler() - Async Handler for I2C Slave driver.
+ * I2C1_IRQHandler() - Async Handler for I2C Target driver.
  */
-void I2C1_IRQHandler(void)
+static void I2C1_IRQHandler(void)
 {
-	i2c_slave_handler(i2c_bus_ports[1]);
+	i2c_target_handler(i2c_bus_ports[1]);
 }
 
 DECLARE_IRQ(EC_I2C0_IRQn, I2C0_IRQHandler, 1);
 DECLARE_IRQ(EC_I2C1_IRQn, I2C1_IRQHandler, 1);
 
 /**
- * i2c_slave_service_read() - Services the Master I2C read from the slave.
+ * i2c_target_service_read() - Services the Controller I2C read from the target.
  * @i2c: I2C peripheral pointer.
  * @req: Pointer to the request info.
  */
-static void i2c_slave_service_read(mxc_i2c_regs_t *i2c, i2c_req_t *req)
+static void i2c_target_service_read(mxc_i2c_regs_t *i2c, i2c_req_t *req)
 {
 	/*
 	 * Clear the RX Threshold interrupt if set. Make sure and preserve
-	 * a possible done bit, address match, or multiple slave address
+	 * a possible done bit, address match, or multiple target address
 	 * flags.
 	 */
-	i2c->int_fl0 = i2c->int_fl0 & ~(MXC_F_I2C_INT_FL0_ADDR_MATCH |
-		MXC_F_I2C_INT_FL0_MAMI_MASK | MXC_F_I2C_INT_FL0_DONE);
+	i2c->int_fl0 = i2c->int_fl0 &
+		       ~(MXC_F_I2C_INT_FL0_ADDR_MATCH |
+			 MXC_F_I2C_INT_FL0_MAMI_MASK | MXC_F_I2C_INT_FL0_DONE);
 	i2c->int_fl1 = i2c->int_fl1;
 	/*
 	 * If there is nothing to transmit to the EC HOST, then default
@@ -448,19 +452,22 @@ static void i2c_slave_service_read(mxc_i2c_regs_t *i2c, i2c_req_t *req)
 	if (req->tx_remain < 0) {
 		return;
 	}
-	/* If there is data to send to the Master then fill the TX FIFO. */
+	/* If there is data to send to the Controller then fill the TX FIFO. */
 	if (req->tx_remain != 0) {
-		/* There is no longer a response pending from the slave to the master. */
+		/*
+		 * There is no longer a response pending from the target to the
+		 * controller.
+		 */
 		req->response_pending = false;
-		/* Fill the FIFO with data to transimit to the I2C Master. */
+		/* Fill the FIFO with data to transimit to the I2C Controller */
 		while ((req->tx_remain > 0) &&
-			!(i2c->status & MXC_F_I2C_STATUS_TX_FULL)) {
+		       !(i2c->status & MXC_F_I2C_STATUS_TX_FULL)) {
 			i2c->fifo = *(req->tx_data)++;
 			req->tx_remain--;
 		}
 	}
 	/*
-	 * If we have sent everything to the Master that we can,
+	 * If we have sent everything to the Controller that we can,
 	 * then send padding byte.
 	 */
 	if (req->tx_remain == 0) {
@@ -472,22 +479,23 @@ static void i2c_slave_service_read(mxc_i2c_regs_t *i2c, i2c_req_t *req)
 	}
 	/* Set the threshold for TX, the threshold is a four bit field. */
 	i2c->tx_ctrl0 = ((i2c->tx_ctrl0 & ~(MXC_F_I2C_TX_CTRL0_TX_THRESH)) |
-			(2 << MXC_F_I2C_TX_CTRL0_TX_THRESH_POS));
+			 (2 << MXC_F_I2C_TX_CTRL0_TX_THRESH_POS));
 	/* Enable interrupts of interest. */
 	i2c->int_en0 = MXC_F_I2C_INT_EN0_TX_THRESH | MXC_F_I2C_INT_EN0_DONE |
-			I2C_ERROR | MXC_F_I2C_INT_EN0_ADDR_MATCH;
+		       I2C_ERROR | MXC_F_I2C_INT_EN0_ADDR_MATCH;
 }
 
 /**
- * i2c_slave_service_write() - Services the Master I2C write to the slave.
+ * i2c_target_service_write() - Services the Controller I2C write to the target.
  * @i2c: I2C peripheral pointer.
  * @req: Pointer to the request info.
  */
-static void i2c_slave_service_write(mxc_i2c_regs_t *i2c, i2c_req_t *req)
+static void i2c_target_service_write(mxc_i2c_regs_t *i2c, i2c_req_t *req)
 {
 	/* Clear all flags except address matching and done. */
-	i2c->int_fl0 = i2c->int_fl0 & ~(MXC_F_I2C_INT_FL0_ADDR_MATCH |
-		MXC_F_I2C_INT_FL0_MAMI_MASK | MXC_F_I2C_INT_FL0_DONE);
+	i2c->int_fl0 = i2c->int_fl0 &
+		       ~(MXC_F_I2C_INT_FL0_ADDR_MATCH |
+			 MXC_F_I2C_INT_FL0_MAMI_MASK | MXC_F_I2C_INT_FL0_DONE);
 	i2c->int_fl1 = i2c->int_fl1;
 	/* Read out any data in the RX FIFO. */
 	while (!(i2c->status & MXC_F_I2C_STATUS_RX_EMPTY)) {
@@ -495,17 +503,16 @@ static void i2c_slave_service_write(mxc_i2c_regs_t *i2c, i2c_req_t *req)
 		req->received_count++;
 	}
 	/* Set the RX threshold interrupt level. */
-	i2c->rx_ctrl0 = ((i2c->rx_ctrl0 &
-			~(MXC_F_I2C_RX_CTRL0_RX_THRESH)) |
-			(MXC_I2C_FIFO_DEPTH - 1)
-				<< MXC_F_I2C_RX_CTRL0_RX_THRESH_POS);
+	i2c->rx_ctrl0 =
+		((i2c->rx_ctrl0 & ~(MXC_F_I2C_RX_CTRL0_RX_THRESH)) |
+		 (MXC_I2C_FIFO_DEPTH - 1) << MXC_F_I2C_RX_CTRL0_RX_THRESH_POS);
 	/* Enable interrupts of interest. */
 	i2c->int_en0 = MXC_F_I2C_INT_EN0_RX_THRESH | MXC_F_I2C_INT_EN0_DONE |
-			I2C_ERROR | MXC_F_I2C_INT_EN0_ADDR_MATCH;
+		       I2C_ERROR | MXC_F_I2C_INT_EN0_ADDR_MATCH;
 }
 
 /**
- * i2c_slave_handler() - I2C interrupt handler.
+ * i2c_target_handler() - I2C interrupt handler.
  * @i2c: Base address of the I2C module.
  *
  * This function should be called by the application from the interrupt
@@ -513,22 +520,22 @@ static void i2c_slave_service_write(mxc_i2c_regs_t *i2c, i2c_req_t *req)
  * can be periodically called by the application if I2C interrupts are
  * disabled.
  */
-static void i2c_slave_handler(mxc_i2c_regs_t *i2c)
+static void i2c_target_handler(mxc_i2c_regs_t *i2c)
 {
 	i2c_req_t *req;
 
 	/* Get the request context for this interrupt. */
 	req = states[MXC_I2C_GET_IDX(i2c)].req;
 
-
 	/* Check for an address match flag. */
-	if ((req->expecting_start) && (i2c->int_fl0 & MXC_F_I2C_INT_FL0_ADDR_MATCH)) {
+	if ((req->expecting_start) &&
+	    (i2c->int_fl0 & MXC_F_I2C_INT_FL0_ADDR_MATCH)) {
 		req->expecting_done = true;
 		req->expecting_start = false;
 		/*
-		* Save the address match index to identify
-		* targeted slave address.
-		*/
+		 * Save the address match index to identify
+		 * targeted target address.
+		 */
 		req->addr_match_flag =
 			(i2c->int_fl0 & MXC_F_I2C_INT_FL0_MAMI_MASK) >>
 			MXC_F_I2C_INT_FL0_MAMI_POS;
@@ -538,51 +545,64 @@ static void i2c_slave_handler(mxc_i2c_regs_t *i2c)
 		i2c->int_fl1 = i2c->int_fl1;
 
 		/* Only enable done, error and address match interrupts. */
-		i2c->int_en0 = MXC_F_I2C_INT_EN0_DONE |
-			I2C_ERROR | MXC_F_I2C_INT_EN0_ADDR_MATCH;
+		i2c->int_en0 = MXC_F_I2C_INT_EN0_DONE | I2C_ERROR |
+			       MXC_F_I2C_INT_EN0_ADDR_MATCH;
 
-		/* Check if Master is writing to the slave. */
+		/* Check if Controller is writing to the target. */
 		if (!(i2c->ctrl & MXC_F_I2C_CTRL_READ)) {
-			/* I2C Master is writing to the slave. */
+			/* I2C Controller is writing to the target. */
 			req->rx_data = host_buffer;
 			req->tx_data = host_buffer;
 			req->tx_remain = -1; /* Nothing to send yet. */
-			/* Clear the RX (receive from I2C Master) byte counter. */
+			/*
+			 * Clear the RX (receive from I2C Controller) byte
+			 * counter.
+			 */
 			req->received_count = 0;
-			req->state = I2C_SLAVE_ADDR_MATCH_WRITE;
-			/* The Master is writing, there can not be a response pending yet. */
+			req->state = I2C_TARGET_ADDR_MATCH_WRITE;
+			/*
+			 * The Controller is writing, there can not be a
+			 * response pending yet.
+			 */
 			req->response_pending = false;
 			/* Set the RX threshold interrupt level. */
-			i2c->rx_ctrl0 = ((i2c->rx_ctrl0 &
-					~(MXC_F_I2C_RX_CTRL0_RX_THRESH)) |
-					(MXC_I2C_FIFO_DEPTH - 2)
-						<< MXC_F_I2C_RX_CTRL0_RX_THRESH_POS);
+			i2c->rx_ctrl0 =
+				((i2c->rx_ctrl0 &
+				  ~(MXC_F_I2C_RX_CTRL0_RX_THRESH)) |
+				 (MXC_I2C_FIFO_DEPTH - 2)
+					 << MXC_F_I2C_RX_CTRL0_RX_THRESH_POS);
 		} else {
-			/* The Master is reading from the slave. */
-			/* Start transmitting to the Master from the start of buffer. */
+			/*
+			 * The Controller is reading from the target.
+			 * Start transmitting to the Controller from the start
+			 * of buffer.
+			 */
 			req->tx_data = host_buffer;
-			req->state = I2C_SLAVE_ADDR_MATCH_READ;
-			/* Set the threshold for TX, the threshold is a four bit field. */
-			i2c->tx_ctrl0 = ((i2c->tx_ctrl0 & ~(MXC_F_I2C_TX_CTRL0_TX_THRESH)) |
-				(2 << MXC_F_I2C_TX_CTRL0_TX_THRESH_POS));
-#ifdef CONFIG_BOARD_I2C_SLAVE_ADDR_FLAGS
+			req->state = I2C_TARGET_ADDR_MATCH_READ;
+			/* Set the threshold for TX, the threshold is a four bit
+			 * field. */
+			i2c->tx_ctrl0 =
+				((i2c->tx_ctrl0 &
+				  ~(MXC_F_I2C_TX_CTRL0_TX_THRESH)) |
+				 (2 << MXC_F_I2C_TX_CTRL0_TX_THRESH_POS));
+#ifdef CONFIG_BOARD_I2C_ADDR_FLAGS
 			/*
-			* If this is a board address match and there is not
-			* already a pending response to the I2C Master then
-			* fulfill this board read request.
-			*/
+			 * If this is a board address match and there is not
+			 * already a pending response to the I2C Controller then
+			 * fulfill this board read request.
+			 */
 			if ((req->response_pending == 0) &&
-				(req->addr_match_flag != 0x1)) {
+			    (req->addr_match_flag != 0x1)) {
 				i2c_process_board_command(
-					1, CONFIG_BOARD_I2C_SLAVE_ADDR_FLAGS, 0);
+					1, CONFIG_BOARD_I2C_ADDR_FLAGS, 0);
 			}
-#endif /* CONFIG_BOARD_I2C_SLAVE_ADDR_FLAGS */
+#endif /* CONFIG_BOARD_I2C_ADDR_FLAGS */
 		}
 		/* Only enable done, error and address match interrupts. */
-		i2c->int_en0 = MXC_F_I2C_INT_EN0_DONE |
-			I2C_ERROR | MXC_F_I2C_INT_EN0_ADDR_MATCH;
+		i2c->int_en0 = MXC_F_I2C_INT_EN0_DONE | I2C_ERROR |
+			       MXC_F_I2C_INT_EN0_ADDR_MATCH;
 		/* Inhibit sleep mode when addressed until STOPF flag is set. */
-		disable_sleep(SLEEP_MASK_I2C_SLAVE);
+		disable_sleep(SLEEP_MASK_I2C_PERIPHERAL);
 	}
 
 	/* Check for DONE interrupt. */
@@ -591,15 +611,16 @@ static void i2c_slave_handler(mxc_i2c_regs_t *i2c)
 		req->expecting_done = false;
 		/* Clear all interrupts except a possible address match. */
 		i2c->int_fl0 = i2c->int_fl0 & ~(MXC_F_I2C_INT_FL0_ADDR_MATCH |
-			MXC_F_I2C_INT_FL0_MAMI_MASK);
+						MXC_F_I2C_INT_FL0_MAMI_MASK);
 		i2c->int_fl1 = i2c->int_fl1;
 
 		/* Only enable done, error and address match interrupts. */
-		i2c->int_en0 = MXC_F_I2C_INT_EN0_DONE |
-			I2C_ERROR | MXC_F_I2C_INT_EN0_ADDR_MATCH;
+		i2c->int_en0 = MXC_F_I2C_INT_EN0_DONE | I2C_ERROR |
+			       MXC_F_I2C_INT_EN0_ADDR_MATCH;
 		i2c->int_en1 = 0;
-		/* If this was a DONE after a write then read the fifo until empty. */
-		if (req->state == I2C_SLAVE_ADDR_MATCH_WRITE) {
+		/* If this was a DONE after a write then read the fifo until
+		 * empty. */
+		if (req->state == I2C_TARGET_ADDR_MATCH_WRITE) {
 			/* Read out any data in the RX FIFO. */
 			while (!(i2c->status & MXC_F_I2C_STATUS_RX_EMPTY)) {
 				*(req->rx_data)++ = i2c->fifo;
@@ -611,14 +632,14 @@ static void i2c_slave_handler(mxc_i2c_regs_t *i2c)
 		/* Manually clear the TX FIFO. */
 		i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH;
 
-		/* Process the Master write that just finished. */
-		i2c_slave_service(req);
+		/* Process the Controller write that just finished. */
+		i2c_target_service(req);
 
 		/* No longer inhibit deep sleep after done. */
-		enable_sleep(SLEEP_MASK_I2C_SLAVE);
+		enable_sleep(SLEEP_MASK_I2C_PERIPHERAL);
 	}
 
-	/* Check for an I2C Master Read or Write. */
+	/* Check for an I2C Controller Read or Write. */
 	if (i2c->int_fl0 & I2C_ERROR) {
 		/* Clear the error interrupt. */
 		i2c->int_fl0 = I2C_ERROR;
@@ -633,18 +654,17 @@ static void i2c_slave_handler(mxc_i2c_regs_t *i2c)
 		/* Cycle the I2C peripheral enable on error. */
 		i2c->ctrl = 0;
 		i2c->ctrl = MXC_F_I2C_CTRL_I2C_EN;
-	} else if (req->state == I2C_SLAVE_ADDR_MATCH_READ) {
-		/* Service a read request from the I2C Master. */
-		i2c_slave_service_read(i2c, req);
-	} else if (req->state == I2C_SLAVE_ADDR_MATCH_WRITE) {
-		/* Service a write request from the I2C Master. */
-		i2c_slave_service_write(i2c, req);
+	} else if (req->state == I2C_TARGET_ADDR_MATCH_READ) {
+		/* Service a read request from the I2C Controller. */
+		i2c_target_service_read(i2c, req);
+	} else if (req->state == I2C_TARGET_ADDR_MATCH_WRITE) {
+		/* Service a write request from the I2C Controller. */
+		i2c_target_service_write(i2c, req);
 	}
-
 }
 
 /**
- * init_i2cs() - Async Handler for I2C Slave driver.
+ * init_i2cs() - Async Handler for I2C Target driver.
  * @port: I2C port number to initialize.
  */
 void init_i2cs(int port)
@@ -656,15 +676,15 @@ void init_i2cs(int port)
 		while (1)
 			;
 	}
-	/* Prepare for interrupt driven slave requests. */
-	req_slave.addr = CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS;
-	req_slave.tx_data = host_buffer; /* Transmitted to host. */
-	req_slave.tx_remain = -1;
-	req_slave.rx_data = host_buffer; /* Received from host. */
-	req_slave.restart = 0;
-	req_slave.response_pending = false;
-	states[port].req = &req_slave;
-	error = i2c_slave_async(i2c_bus_ports[port], &req_slave);
+	/* Prepare for interrupt driven target requests. */
+	req_target.addr = CONFIG_HOSTCMD_I2C_ADDR_FLAGS;
+	req_target.tx_data = host_buffer; /* Transmitted to host. */
+	req_target.tx_remain = -1;
+	req_target.rx_data = host_buffer; /* Received from host. */
+	req_target.restart = 0;
+	req_target.response_pending = false;
+	states[port].req = &req_target;
+	error = i2c_target_async(i2c_bus_ports[port], &req_target);
 	if (error != EC_SUCCESS) {
 		while (1)
 			;
@@ -675,22 +695,22 @@ void init_i2cs(int port)
 }
 
 /**
- * i2c_slave_async() - Slave Read and Write Asynchronous.
+ * i2c_target_async() - Target Read and Write Asynchronous.
  * @i2c:   Pointer to I2C regs.
  * @req:   Request for an I2C transaction.
  *
  * Return EC_SUCCESS if successful, otherwise returns a common error code.
  */
-static int i2c_slave_async(mxc_i2c_regs_t *i2c, i2c_req_t *req)
+static int i2c_target_async(mxc_i2c_regs_t *i2c, i2c_req_t *req)
 {
 	/* Make sure the I2C has been initialized. */
 	if (!(i2c->ctrl & MXC_F_I2C_CTRL_I2C_EN))
 		return EC_ERROR_UNKNOWN;
-	/* Disable master mode. */
+	/* Disable controller mode. */
 	i2c->ctrl &= ~(MXC_F_I2C_CTRL_MST);
-	/* Set the Slave Address in the I2C peripheral register. */
-	i2c->slave_addr = req->addr;
-	/* Clear the receive count from the I2C Master. */
+	/* Set the Target Address in the I2C peripheral register. */
+	i2c->target_addr = req->addr;
+	/* Clear the receive count from the I2C Controller. */
 	req->received_count = 0;
 	/* Disable and clear the interrupts. */
 	i2c->int_en0 = 0;
@@ -699,10 +719,9 @@ static int i2c_slave_async(mxc_i2c_regs_t *i2c, i2c_req_t *req)
 	i2c->int_fl1 = i2c->int_fl1;
 
 	/* Set the RX threshold interrupt level. */
-	i2c->rx_ctrl0 = ((i2c->rx_ctrl0 &
-			~(MXC_F_I2C_RX_CTRL0_RX_THRESH)) |
-			(MXC_I2C_FIFO_DEPTH - 2)
-				<< MXC_F_I2C_RX_CTRL0_RX_THRESH_POS);
+	i2c->rx_ctrl0 =
+		((i2c->rx_ctrl0 & ~(MXC_F_I2C_RX_CTRL0_RX_THRESH)) |
+		 (MXC_I2C_FIFO_DEPTH - 2) << MXC_F_I2C_RX_CTRL0_RX_THRESH_POS);
 
 	/* Only enable the I2C Address match interrupt. */
 	i2c->int_en0 = MXC_F_I2C_INT_EN0_ADDR_MATCH;
@@ -710,24 +729,23 @@ static int i2c_slave_async(mxc_i2c_regs_t *i2c, i2c_req_t *req)
 	return EC_SUCCESS;
 }
 
-#ifdef CONFIG_BOARD_I2C_SLAVE_ADDR_FLAGS
+#ifdef CONFIG_BOARD_I2C_ADDR_FLAGS
 
 static void i2c_send_board_response(int len)
 {
-	/* Set the number of bytes to send to the I2C master. */
-	req_slave.tx_remain = len;
-	/* Indicate that there is a response pending from the slave. */
-	req_slave.response_pending = true;
+	/* Set the number of bytes to send to the I2C controller. */
+	req_target.tx_remain = len;
+	/* Indicate that there is a response pending from the target. */
+	req_target.response_pending = true;
 }
 
-
 static void i2c_process_board_command(int read, int addr, int len)
 {
 	board_i2c_process(read, addr, len, &host_buffer[0],
 			  i2c_send_board_response);
 }
-#endif /* CONFIG_BOARD_I2C_SLAVE_ADDR_FLAGS */
-#endif /* CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS */
+#endif /* CONFIG_BOARD_I2C_ADDR_FLAGS */
+#endif /* CONFIG_HOSTCMD_I2C_ADDR_FLAGS */
 
 /**
  * i2c_set_speed() - Set the transfer speed of the selected I2C.
@@ -760,15 +778,17 @@ static int i2c_set_speed(mxc_i2c_regs_t *i2c, i2c_speed_t i2cspeed)
 		time_scl_min = 1000000 / (target_bus_freq / 1000);
 		clock_low_min =
 			((T_LOW_MIN + T_F_MAX_HS + (time_pclk - 1) - T_AF_MIN) /
-			 time_pclk) - 1;
+			 time_pclk) -
+			1;
 		clock_high_min = ((T_HIGH_MIN + T_R_MAX_HS + (time_pclk - 1) -
-				  T_AF_MIN) /
-				  time_pclk) - 1;
+				   T_AF_MIN) /
+				  time_pclk) -
+				 1;
 		clock_min = ((time_scl_min + (time_pclk - 1)) / time_pclk) - 2;
 
-		ticks_lo = (clock_low_min > (clock_min - clock_high_min))
-				   ? (clock_low_min)
-				   : (clock_min - clock_high_min);
+		ticks_lo = (clock_low_min > (clock_min - clock_high_min)) ?
+				   (clock_low_min) :
+				   (clock_min - clock_high_min);
 		ticks_hi = clock_high_min;
 
 		if ((ticks_lo > (MXC_F_I2C_HS_CLK_HS_CLK_LO >>
@@ -842,12 +862,12 @@ static int i2c_init_peripheral(mxc_i2c_regs_t *i2c, i2c_speed_t i2cspeed)
 
 	i2c->ctrl = 0; /* Clear configuration bits. */
 	i2c->ctrl = MXC_F_I2C_CTRL_I2C_EN; /* Enable I2C. */
-	i2c->master_ctrl = 0; /* Clear master configuration bits. */
+	i2c->controller_ctrl = 0; /* Clear controller configuration bits. */
 	i2c->status = 0; /* Clear status bits. */
 
 	i2c->ctrl = 0; /* Clear configuration bits. */
 	i2c->ctrl = MXC_F_I2C_CTRL_I2C_EN; /* Enable I2C. */
-	i2c->master_ctrl = 0; /* Clear master configuration bits. */
+	i2c->controller_ctrl = 0; /* Clear controller configuration bits. */
 	i2c->status = 0; /* Clear status bits. */
 
 	/* Check for HS mode. */
@@ -869,13 +889,13 @@ static int i2c_init_peripheral(mxc_i2c_regs_t *i2c, i2c_speed_t i2cspeed)
 }
 
 /**
- * i2c_master_write()
+ * i2c_controller_write()
  * @i2c:  Pointer to I2C regs.
  * @addr: I2C 7-bit Address left aligned, bit 7 to bit 1.
  *        Only supports 7-bit addressing. LSb of the given address
  *        will be used as the read/write bit, the \p addr <b>will
- *        not be shifted. Used for both master and
- *        slave transactions.
+ *        not be shifted. Used for both controller and
+ *        target transactions.
  * @data: Data to be written.
  * @len:  Number of bytes to Write.
  * @restart: 0 to send a stop bit at the end of the transaction,
@@ -885,8 +905,9 @@ static int i2c_init_peripheral(mxc_i2c_regs_t *i2c, i2c_speed_t i2cspeed)
  *
  * Return  EC_SUCCESS, or non-zero if error.
  */
-static int i2c_master_write(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
-			    int stop, const uint8_t *data, int len, int restart)
+static int i2c_controller_write(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
+				int stop, const uint8_t *data, int len,
+				int restart)
 {
 	if (len == 0) {
 		return EC_SUCCESS;
@@ -900,16 +921,16 @@ static int i2c_master_write(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
 		return EC_ERROR_UNKNOWN;
 	}
 
-	/* Enable master mode. */
+	/* Enable controller mode. */
 	i2c->ctrl |= MXC_F_I2C_CTRL_MST;
 
-	/* Load FIFO with slave address for WRITE and as much data as we can. */
+	/* Load FIFO with target address for WRITE and as much data as we can */
 	while (i2c->status & MXC_F_I2C_STATUS_TX_FULL) {
 	}
 
 	if (start) {
 		/**
-		 * The slave address is right-aligned, bits 6 to 0, shift
+		 * The target address is right-aligned, bits 6 to 0, shift
 		 * to the left and make room for the write bit.
 		 */
 		i2c->fifo = (addr << 1) & ~(0x1);
@@ -921,7 +942,7 @@ static int i2c_master_write(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
 	}
 	/* Generate Start signal. */
 	if (start) {
-		i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_START;
+		i2c->controller_ctrl |= MXC_F_I2C_CONTROLLER_CTRL_START;
 	}
 
 	/* Write remaining data to FIFO. */
@@ -929,8 +950,9 @@ static int i2c_master_write(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
 		/* Check for errors. */
 		if (i2c->int_fl0 & I2C_ERROR) {
 			/* Set the stop bit. */
-			i2c->master_ctrl &= ~(MXC_F_I2C_MASTER_CTRL_RESTART);
-			i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
+			i2c->controller_ctrl &=
+				~MXC_F_I2C_CONTROLLER_CTRL_RESTART;
+			i2c->controller_ctrl |= MXC_F_I2C_CONTROLLER_CTRL_STOP;
 			return EC_ERROR_UNKNOWN;
 		}
 
@@ -941,10 +963,10 @@ static int i2c_master_write(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
 	}
 	/* Check if Repeated Start requested. */
 	if (restart) {
-		i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_RESTART;
+		i2c->controller_ctrl |= MXC_F_I2C_CONTROLLER_CTRL_RESTART;
 	} else {
 		if (stop) {
-			i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
+			i2c->controller_ctrl |= MXC_F_I2C_CONTROLLER_CTRL_STOP;
 		}
 	}
 
@@ -954,9 +976,10 @@ static int i2c_master_write(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
 			/* Check for errors */
 			if (i2c->int_fl0 & I2C_ERROR) {
 				/* Set the stop bit */
-				i2c->master_ctrl &=
-					~(MXC_F_I2C_MASTER_CTRL_RESTART);
-				i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
+				i2c->controller_ctrl &=
+					~MXC_F_I2C_CONTROLLER_CTRL_RESTART;
+				i2c->controller_ctrl |=
+					MXC_F_I2C_CONTROLLER_CTRL_STOP;
 				return EC_ERROR_UNKNOWN;
 			}
 		}
@@ -970,9 +993,10 @@ static int i2c_master_write(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
 			/* Check for errors */
 			if (i2c->int_fl0 & I2C_ERROR) {
 				/* Set the stop bit */
-				i2c->master_ctrl &=
-					~(MXC_F_I2C_MASTER_CTRL_RESTART);
-				i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
+				i2c->controller_ctrl &=
+					~MXC_F_I2C_CONTROLLER_CTRL_RESTART;
+				i2c->controller_ctrl |=
+					MXC_F_I2C_CONTROLLER_CTRL_STOP;
 				return EC_ERROR_UNKNOWN;
 			}
 		}
@@ -989,7 +1013,7 @@ static int i2c_master_write(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
 }
 
 /**
- * i2c_master_read()
+ * i2c_controller_read()
  * @i2c:        Pointer to I2C regs.
  * @addr:       I2C 7-bit Address right aligned, bit 6 to bit 0.
  * @data:       Data to be written.
@@ -1001,8 +1025,8 @@ static int i2c_master_write(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
  *
  * Return:     EC_SUCCESS if successful, otherwise returns a common error code
  */
-static int i2c_master_read(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
-			   int stop, uint8_t *data, int len, int restart)
+static int i2c_controller_read(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
+			       int stop, uint8_t *data, int len, int restart)
 {
 	volatile int length = len;
 	int interactive_receive_mode;
@@ -1023,7 +1047,7 @@ static int i2c_master_read(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
 		return EC_ERROR_UNKNOWN;
 	}
 
-	/* Enable master mode. */
+	/* Enable controller mode. */
 	i2c->ctrl |= MXC_F_I2C_CTRL_MST;
 
 	if (stop) {
@@ -1037,13 +1061,13 @@ static int i2c_master_read(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
 		interactive_receive_mode = 1;
 	}
 
-	/* Load FIFO with slave address. */
+	/* Load FIFO with target address. */
 	if (start) {
-		i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_START;
+		i2c->controller_ctrl |= MXC_F_I2C_CONTROLLER_CTRL_START;
 		while (i2c->status & MXC_F_I2C_STATUS_TX_FULL) {
 		}
 		/**
-		 * The slave address is right-aligned, bits 6 to 0, shift
+		 * The target address is right-aligned, bits 6 to 0, shift
 		 * to the left and make room for the read bit.
 		 */
 		i2c->fifo = ((addr << 1) | 1);
@@ -1054,12 +1078,14 @@ static int i2c_master_read(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
 		/* Check for errors */
 		if (i2c->int_fl0 & I2C_ERROR) {
 			/* Set the stop bit. */
-			i2c->master_ctrl &= ~(MXC_F_I2C_MASTER_CTRL_RESTART);
-			i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
+			i2c->controller_ctrl &=
+				~MXC_F_I2C_CONTROLLER_CTRL_RESTART;
+			i2c->controller_ctrl |= MXC_F_I2C_CONTROLLER_CTRL_STOP;
 			return EC_ERROR_UNKNOWN;
 		}
 
-		/* If in interactive receive mode then ack each received byte. */
+		/* If in interactive receive mode then ack each received byte.
+		 */
 		if (interactive_receive_mode) {
 			while (!(i2c->int_fl0 & MXC_F_I2C_INT_EN0_RX_MODE))
 				;
@@ -1082,10 +1108,10 @@ static int i2c_master_read(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
 	}
 
 	if (restart) {
-		i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_RESTART;
+		i2c->controller_ctrl |= MXC_F_I2C_CONTROLLER_CTRL_RESTART;
 	} else {
 		if (stop) {
-			i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
+			i2c->controller_ctrl |= MXC_F_I2C_CONTROLLER_CTRL_STOP;
 		}
 	}
 
@@ -1095,9 +1121,10 @@ static int i2c_master_read(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
 			/* Check for errors. */
 			if (i2c->int_fl0 & I2C_ERROR) {
 				/* Set the stop bit. */
-				i2c->master_ctrl &=
-					~(MXC_F_I2C_MASTER_CTRL_RESTART);
-				i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
+				i2c->controller_ctrl &=
+					~MXC_F_I2C_CONTROLLER_CTRL_RESTART;
+				i2c->controller_ctrl |=
+					MXC_F_I2C_CONTROLLER_CTRL_STOP;
 				return EC_ERROR_UNKNOWN;
 			}
 		}
@@ -1106,22 +1133,20 @@ static int i2c_master_read(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
 	}
 
 	/* Wait for Stop. */
-	if (!restart) {
-		if (stop) {
-			while (!(i2c->int_fl0 & MXC_F_I2C_INT_FL0_STOP)) {
-				/* Check for errors. */
-				if (i2c->int_fl0 & I2C_ERROR) {
-					/* Set the stop bit. */
-					i2c->master_ctrl &= ~(
-						MXC_F_I2C_MASTER_CTRL_RESTART);
-					i2c->master_ctrl |=
-						MXC_F_I2C_MASTER_CTRL_STOP;
-					return EC_ERROR_UNKNOWN;
-				}
+	if (!restart && stop) {
+		while (!(i2c->int_fl0 & MXC_F_I2C_INT_FL0_STOP)) {
+			/* Check for errors. */
+			if (i2c->int_fl0 & I2C_ERROR) {
+				/* Set the stop bit. */
+				i2c->controller_ctrl &=
+					~MXC_F_I2C_CONTROLLER_CTRL_RESTART;
+				i2c->controller_ctrl |=
+					MXC_F_I2C_CONTROLLER_CTRL_STOP;
+				return EC_ERROR_UNKNOWN;
 			}
-			/* Clear Stop interrupt flag. */
-			i2c->int_fl0 = MXC_F_I2C_INT_FL0_STOP;
 		}
+		/* Clear Stop interrupt flag. */
+		i2c->int_fl0 = MXC_F_I2C_INT_FL0_STOP;
 	}
 
 	/* Check for errors. */
diff --git a/chip/max32660/i2c_regs.h b/chip/max32660/i2c_regs.h
index 8cd2fd8868..4d8daf63c7 100644
--- a/chip/max32660/i2c_regs.h
+++ b/chip/max32660/i2c_regs.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,8 @@
 #include <stdint.h>
 
 /*
-    If types are not defined elsewhere (CMSIS) define them here
-*/
+ * If types are not defined elsewhere (CMSIS) define them here
+ */
 #ifndef __IO
 #define __IO volatile
 #endif
@@ -26,1602 +26,1338 @@
 #define __R volatile const
 #endif
 
-/**
+/*
  * Registers, Bit Masks and Bit Positions for the I2C Peripheral Module.
  */
 
-/**
+/*
  * typedef mxc_i2c_regs_t - Structure type to access the I2C Registers.
  */
 typedef struct {
-	__IO uint32_t ctrl; /**< <tt>\b 0x00:</tt> I2C CTRL Register */
-	__IO uint32_t status; /**< <tt>\b 0x04:</tt> I2C STATUS Register */
-	__IO uint32_t int_fl0; /**< <tt>\b 0x08:</tt> I2C INT_FL0 Register */
-	__IO uint32_t int_en0; /**< <tt>\b 0x0C:</tt> I2C INT_EN0 Register */
-	__IO uint32_t int_fl1; /**< <tt>\b 0x10:</tt> I2C INT_FL1 Register */
-	__IO uint32_t int_en1; /**< <tt>\b 0x14:</tt> I2C INT_EN1 Register */
-	__IO uint32_t fifo_len; /**< <tt>\b 0x18:</tt> I2C FIFO_LEN Register */
-	__IO uint32_t rx_ctrl0; /**< <tt>\b 0x1C:</tt> I2C RX_CTRL0 Register */
-	__IO uint32_t rx_ctrl1; /**< <tt>\b 0x20:</tt> I2C RX_CTRL1 Register */
-	__IO uint32_t tx_ctrl0; /**< <tt>\b 0x24:</tt> I2C TX_CTRL0 Register */
-	__IO uint32_t tx_ctrl1; /**< <tt>\b 0x28:</tt> I2C TX_CTRL1 Register */
-	__IO uint32_t fifo; /**< <tt>\b 0x2C:</tt> I2C FIFO Register */
-	__IO uint32_t
-		master_ctrl; /**< <tt>\b 0x30:</tt> I2C MASTER_CTRL Register */
-	__IO uint32_t clk_lo; /**< <tt>\b 0x34:</tt> I2C CLK_LO Register */
-	__IO uint32_t clk_hi; /**< <tt>\b 0x38:</tt> I2C CLK_HI Register */
-	__IO uint32_t hs_clk; /**< <tt>\b 0x3C:</tt> I2C HS_CLK Register */
-	__IO uint32_t timeout; /**< <tt>\b 0x40:</tt> I2C TIMEOUT Register */
-	__IO uint32_t
-		slave_addr; /**< <tt>\b 0x44:</tt> I2C SLAVE_ADDR Register */
-	__IO uint32_t dma; /**< <tt>\b 0x48:</tt> I2C DMA Register */
+	__IO uint32_t ctrl; /* 0x00: I2C CTRL Register */
+	__IO uint32_t status; /* 0x04: I2C STATUS Register */
+	__IO uint32_t int_fl0; /* 0x08: I2C INT_FL0 Register */
+	__IO uint32_t int_en0; /* 0x0C: I2C INT_EN0 Register */
+	__IO uint32_t int_fl1; /* 0x10: I2C INT_FL1 Register */
+	__IO uint32_t int_en1; /* 0x14: I2C INT_EN1 Register */
+	__IO uint32_t fifo_len; /* 0x18: I2C FIFO_LEN Register */
+	__IO uint32_t rx_ctrl0; /* 0x1C: I2C RX_CTRL0 Register */
+	__IO uint32_t rx_ctrl1; /* 0x20: I2C RX_CTRL1 Register */
+	__IO uint32_t tx_ctrl0; /* 0x24: I2C TX_CTRL0 Register */
+	__IO uint32_t tx_ctrl1; /* 0x28: I2C TX_CTRL1 Register */
+	__IO uint32_t fifo; /* 0x2C: I2C FIFO Register */
+	__IO uint32_t controller_ctrl; /* 0x30: I2C CONTROLLER_CTRL Register */
+	__IO uint32_t clk_lo; /* 0x34: I2C CLK_LO Register */
+	__IO uint32_t clk_hi; /* 0x38: I2C CLK_HI Register */
+	__IO uint32_t hs_clk; /* 0x3C: I2C HS_CLK Register */
+	__IO uint32_t timeout; /* 0x40: I2C TIMEOUT Register */
+	__IO uint32_t target_addr; /* 0x44: I2C TARGET_ADDR Register */
+	__IO uint32_t dma; /* 0x48: I2C DMA Register */
 } mxc_i2c_regs_t;
 
 /* Register offsets for module I2C */
-/**
+/*
  * I2C Peripheral Register Offsets from the I2C Base Peripheral Address.
  */
-#define MXC_R_I2C_CTRL \
-	((uint32_t)0x00000000UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0000</tt> */
-#define MXC_R_I2C_STATUS \
-	((uint32_t)0x00000004UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0004</tt> */
-#define MXC_R_I2C_INT_FL0 \
-	((uint32_t)0x00000008UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0008</tt> */
-#define MXC_R_I2C_INT_EN0 \
-	((uint32_t)0x0000000CUL) /**< Offset from I2C Base Address: <tt>       \
-				    0x000C</tt> */
-#define MXC_R_I2C_INT_FL1 \
-	((uint32_t)0x00000010UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0010</tt> */
-#define MXC_R_I2C_INT_EN1 \
-	((uint32_t)0x00000014UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0014</tt> */
-#define MXC_R_I2C_FIFO_LEN \
-	((uint32_t)0x00000018UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0018</tt> */
-#define MXC_R_I2C_RX_CTRL0 \
-	((uint32_t)0x0000001CUL) /**< Offset from I2C Base Address: <tt>       \
-				    0x001C</tt> */
-#define MXC_R_I2C_RX_CTRL1 \
-	((uint32_t)0x00000020UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0020</tt> */
-#define MXC_R_I2C_TX_CTRL0 \
-	((uint32_t)0x00000024UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0024</tt> */
-#define MXC_R_I2C_TX_CTRL1 \
-	((uint32_t)0x00000028UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0028</tt> */
-#define MXC_R_I2C_FIFO \
-	((uint32_t)0x0000002CUL) /**< Offset from I2C Base Address: <tt>       \
-				    0x002C</tt> */
-#define MXC_R_I2C_MASTER_CTRL \
-	((uint32_t)0x00000030UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0030</tt> */
-#define MXC_R_I2C_CLK_LO \
-	((uint32_t)0x00000034UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0034</tt> */
-#define MXC_R_I2C_CLK_HI \
-	((uint32_t)0x00000038UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0038</tt> */
-#define MXC_R_I2C_HS_CLK \
-	((uint32_t)0x0000003CUL) /**< Offset from I2C Base Address: <tt>       \
-				    0x003C</tt> */
-#define MXC_R_I2C_TIMEOUT \
-	((uint32_t)0x00000040UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0040</tt> */
-#define MXC_R_I2C_SLAVE_ADDR \
-	((uint32_t)0x00000044UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0044</tt> */
-#define MXC_R_I2C_DMA \
-	((uint32_t)0x00000048UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0048</tt> */
+#define MXC_R_I2C_CTRL 0x00000000UL
+#define MXC_R_I2C_STATUS 0x00000004UL
+#define MXC_R_I2C_INT_FL0 0x00000008UL
+#define MXC_R_I2C_INT_EN0 0x0000000CUL
+#define MXC_R_I2C_INT_FL1 0x00000010UL
+#define MXC_R_I2C_INT_EN1 0x00000014UL
+#define MXC_R_I2C_FIFO_LEN 0x00000018UL
+#define MXC_R_I2C_RX_CTRL0 0x0000001CUL
+#define MXC_R_I2C_RX_CTRL1 0x00000020UL
+#define MXC_R_I2C_TX_CTRL0 0x00000024UL
+#define MXC_R_I2C_TX_CTRL1 0x00000028UL
+#define MXC_R_I2C_FIFO 0x0000002CUL
+#define MXC_R_I2C_CONTROLLER_CTRL 0x00000030UL
+#define MXC_R_I2C_CLK_LO 0x00000034UL
+#define MXC_R_I2C_CLK_HI 0x00000038UL
+#define MXC_R_I2C_HS_CLK 0x0000003CUL
+#define MXC_R_I2C_TIMEOUT 0x00000040UL
+#define MXC_R_I2C_TARGET_ADDR 0x00000044UL
+#define MXC_R_I2C_DMA 0x00000048UL
 
 /**
  * Control Register0.
  */
-#define MXC_F_I2C_CTRL_I2C_EN_POS 0 /**< CTRL_I2C_EN Position */
-#define MXC_F_I2C_CTRL_I2C_EN \
-	((uint32_t)(0x1UL     \
-		    << MXC_F_I2C_CTRL_I2C_EN_POS)) /**< CTRL_I2C_EN Mask */
-#define MXC_V_I2C_CTRL_I2C_EN_DIS \
-	((uint32_t)0x0UL) /**< CTRL_I2C_EN_DIS Value */
-#define MXC_S_I2C_CTRL_I2C_EN_DIS  \
-	(MXC_V_I2C_CTRL_I2C_EN_DIS \
-	 << MXC_F_I2C_CTRL_I2C_EN_POS) /**< CTRL_I2C_EN_DIS Setting */
-#define MXC_V_I2C_CTRL_I2C_EN_EN \
-	((uint32_t)0x1UL) /**< CTRL_I2C_EN_EN Value                            \
-			   */
-#define MXC_S_I2C_CTRL_I2C_EN_EN  \
-	(MXC_V_I2C_CTRL_I2C_EN_EN \
-	 << MXC_F_I2C_CTRL_I2C_EN_POS) /**< CTRL_I2C_EN_EN Setting */
-
-#define MXC_F_I2C_CTRL_MST_POS 1 /**< CTRL_MST Position */
-#define MXC_F_I2C_CTRL_MST \
-	((uint32_t)(0x1UL << MXC_F_I2C_CTRL_MST_POS)) /**< CTRL_MST Mask */
-#define MXC_V_I2C_CTRL_MST_SLAVE_MODE \
-	((uint32_t)0x0UL) /**< CTRL_MST_SLAVE_MODE Value */
-#define MXC_S_I2C_CTRL_MST_SLAVE_MODE  \
-	(MXC_V_I2C_CTRL_MST_SLAVE_MODE \
-	 << MXC_F_I2C_CTRL_MST_POS) /**< CTRL_MST_SLAVE_MODE Setting */
-#define MXC_V_I2C_CTRL_MST_MASTER_MODE \
-	((uint32_t)0x1UL) /**< CTRL_MST_MASTER_MODE Value */
-#define MXC_S_I2C_CTRL_MST_MASTER_MODE  \
-	(MXC_V_I2C_CTRL_MST_MASTER_MODE \
-	 << MXC_F_I2C_CTRL_MST_POS) /**< CTRL_MST_MASTER_MODE Setting */
-
-#define MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS 2 /**< CTRL_GEN_CALL_ADDR Position */
-#define MXC_F_I2C_CTRL_GEN_CALL_ADDR \
-	((uint32_t)(                 \
-		0x1UL                \
-		<< MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS)) /**< CTRL_GEN_CALL_ADDR  \
-							 Mask */
-#define MXC_V_I2C_CTRL_GEN_CALL_ADDR_DIS \
-	((uint32_t)0x0UL) /**< CTRL_GEN_CALL_ADDR_DIS Value */
-#define MXC_S_I2C_CTRL_GEN_CALL_ADDR_DIS  \
-	(MXC_V_I2C_CTRL_GEN_CALL_ADDR_DIS \
-	 << MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS) /**< CTRL_GEN_CALL_ADDR_DIS      \
-						 Setting */
-#define MXC_V_I2C_CTRL_GEN_CALL_ADDR_EN \
-	((uint32_t)0x1UL) /**< CTRL_GEN_CALL_ADDR_EN Value */
-#define MXC_S_I2C_CTRL_GEN_CALL_ADDR_EN  \
-	(MXC_V_I2C_CTRL_GEN_CALL_ADDR_EN \
-	 << MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS) /**< CTRL_GEN_CALL_ADDR_EN       \
-						 Setting */
-
-#define MXC_F_I2C_CTRL_RX_MODE_POS 3 /**< CTRL_RX_MODE Position */
-#define MXC_F_I2C_CTRL_RX_MODE \
-	((uint32_t)(0x1UL      \
-		    << MXC_F_I2C_CTRL_RX_MODE_POS)) /**< CTRL_RX_MODE Mask */
-#define MXC_V_I2C_CTRL_RX_MODE_DIS \
-	((uint32_t)0x0UL) /**< CTRL_RX_MODE_DIS Value */
-#define MXC_S_I2C_CTRL_RX_MODE_DIS  \
-	(MXC_V_I2C_CTRL_RX_MODE_DIS \
-	 << MXC_F_I2C_CTRL_RX_MODE_POS) /**< CTRL_RX_MODE_DIS Setting */
-#define MXC_V_I2C_CTRL_RX_MODE_EN \
-	((uint32_t)0x1UL) /**< CTRL_RX_MODE_EN Value */
-#define MXC_S_I2C_CTRL_RX_MODE_EN  \
-	(MXC_V_I2C_CTRL_RX_MODE_EN \
-	 << MXC_F_I2C_CTRL_RX_MODE_POS) /**< CTRL_RX_MODE_EN Setting */
-
-#define MXC_F_I2C_CTRL_RX_MODE_ACK_POS 4 /**< CTRL_RX_MODE_ACK Position */
-#define MXC_F_I2C_CTRL_RX_MODE_ACK \
-	((uint32_t)(               \
-		0x1UL              \
-		<< MXC_F_I2C_CTRL_RX_MODE_ACK_POS)) /**< CTRL_RX_MODE_ACK  \
-							   Mask */
-#define MXC_V_I2C_CTRL_RX_MODE_ACK_ACK \
-	((uint32_t)0x0UL) /**< CTRL_RX_MODE_ACK_ACK Value */
-#define MXC_S_I2C_CTRL_RX_MODE_ACK_ACK  \
-	(MXC_V_I2C_CTRL_RX_MODE_ACK_ACK \
-	 << MXC_F_I2C_CTRL_RX_MODE_ACK_POS) /**< CTRL_RX_MODE_ACK_ACK Setting  \
-					     */
-#define MXC_V_I2C_CTRL_RX_MODE_ACK_NACK \
-	((uint32_t)0x1UL) /**< CTRL_RX_MODE_ACK_NACK Value */
-#define MXC_S_I2C_CTRL_RX_MODE_ACK_NACK  \
-	(MXC_V_I2C_CTRL_RX_MODE_ACK_NACK \
-	 << MXC_F_I2C_CTRL_RX_MODE_ACK_POS) /**< CTRL_RX_MODE_ACK_NACK Setting \
-					     */
-
-#define MXC_F_I2C_CTRL_SCL_OUT_POS 6 /**< CTRL_SCL_OUT Position */
-#define MXC_F_I2C_CTRL_SCL_OUT \
-	((uint32_t)(0x1UL      \
-		    << MXC_F_I2C_CTRL_SCL_OUT_POS)) /**< CTRL_SCL_OUT Mask */
-#define MXC_V_I2C_CTRL_SCL_OUT_DRIVE_SCL_LOW \
-	((uint32_t)0x0UL) /**< CTRL_SCL_OUT_DRIVE_SCL_LOW Value */
-#define MXC_S_I2C_CTRL_SCL_OUT_DRIVE_SCL_LOW  \
-	(MXC_V_I2C_CTRL_SCL_OUT_DRIVE_SCL_LOW \
-	 << MXC_F_I2C_CTRL_SCL_OUT_POS) /**< CTRL_SCL_OUT_DRIVE_SCL_LOW        \
-					   Setting */
-#define MXC_V_I2C_CTRL_SCL_OUT_RELEASE_SCL \
-	((uint32_t)0x1UL) /**< CTRL_SCL_OUT_RELEASE_SCL Value */
-#define MXC_S_I2C_CTRL_SCL_OUT_RELEASE_SCL  \
-	(MXC_V_I2C_CTRL_SCL_OUT_RELEASE_SCL \
-	 << MXC_F_I2C_CTRL_SCL_OUT_POS) /**< CTRL_SCL_OUT_RELEASE_SCL Setting  \
-					 */
-
-#define MXC_F_I2C_CTRL_SDA_OUT_POS 7 /**< CTRL_SDA_OUT Position */
-#define MXC_F_I2C_CTRL_SDA_OUT \
-	((uint32_t)(0x1UL      \
-		    << MXC_F_I2C_CTRL_SDA_OUT_POS)) /**< CTRL_SDA_OUT Mask */
-#define MXC_V_I2C_CTRL_SDA_OUT_DRIVE_SDA_LOW \
-	((uint32_t)0x0UL) /**< CTRL_SDA_OUT_DRIVE_SDA_LOW Value */
-#define MXC_S_I2C_CTRL_SDA_OUT_DRIVE_SDA_LOW  \
-	(MXC_V_I2C_CTRL_SDA_OUT_DRIVE_SDA_LOW \
-	 << MXC_F_I2C_CTRL_SDA_OUT_POS) /**< CTRL_SDA_OUT_DRIVE_SDA_LOW        \
-					   Setting */
-#define MXC_V_I2C_CTRL_SDA_OUT_RELEASE_SDA \
-	((uint32_t)0x1UL) /**< CTRL_SDA_OUT_RELEASE_SDA Value */
-#define MXC_S_I2C_CTRL_SDA_OUT_RELEASE_SDA  \
-	(MXC_V_I2C_CTRL_SDA_OUT_RELEASE_SDA \
-	 << MXC_F_I2C_CTRL_SDA_OUT_POS) /**< CTRL_SDA_OUT_RELEASE_SDA Setting  \
-					 */
-
-#define MXC_F_I2C_CTRL_SCL_POS 8 /**< CTRL_SCL Position */
-#define MXC_F_I2C_CTRL_SCL \
-	((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_POS)) /**< CTRL_SCL Mask */
-
-#define MXC_F_I2C_CTRL_SDA_POS 9 /**< CTRL_SDA Position */
-#define MXC_F_I2C_CTRL_SDA \
-	((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_POS)) /**< CTRL_SDA Mask */
-
-#define MXC_F_I2C_CTRL_SW_OUT_EN_POS 10 /**< CTRL_SW_OUT_EN Position */
-#define MXC_F_I2C_CTRL_SW_OUT_EN \
-	((uint32_t)(             \
-		0x1UL            \
-		<< MXC_F_I2C_CTRL_SW_OUT_EN_POS)) /**< CTRL_SW_OUT_EN Mask */
-#define MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_DISABLE \
-	((uint32_t)0x0UL) /**< CTRL_SW_OUT_EN_OUTPUTS_DISABLE Value */
+/* CTRL_I2C_EN Position */
+#define MXC_F_I2C_CTRL_I2C_EN_POS 0
+/* CTRL_I2C_EN Mask  */
+#define MXC_F_I2C_CTRL_I2C_EN (0x1UL << MXC_F_I2C_CTRL_I2C_EN_POS)
+/* CTRL_I2C_EN_DIS Value */
+#define MXC_V_I2C_CTRL_I2C_EN_DIS 0x0UL
+/* CTRL_I2C_EN_DIS Setting */
+#define MXC_S_I2C_CTRL_I2C_EN_DIS \
+	(MXC_V_I2C_CTRL_I2C_EN_DIS << MXC_F_I2C_CTRL_I2C_EN_POS)
+/* CTRL_I2C_EN_EN Value */
+#define MXC_V_I2C_CTRL_I2C_EN_EN 0x1UL
+/* CTRL_I2C_EN_EN Setting */
+#define MXC_S_I2C_CTRL_I2C_EN_EN \
+	(MXC_V_I2C_CTRL_I2C_EN_EN << MXC_F_I2C_CTRL_I2C_EN_POS)
+
+/* CTRL_MST Position */
+#define MXC_F_I2C_CTRL_MST_POS 1
+/* CTRL_MST Mask */
+#define MXC_F_I2C_CTRL_MST (0x1UL << MXC_F_I2C_CTRL_MST_POS)
+/* CTRL_MST_TARGET_MODE Value */
+#define MXC_V_I2C_CTRL_MST_TARGET_MODE 0x0UL
+/* CTRL_MST_TARGET_MODE Setting */
+#define MXC_S_I2C_CTRL_MST_TARGET_MODE \
+	(MXC_V_I2C_CTRL_MST_TARGET_MODE << MXC_F_I2C_CTRL_MST_POS)
+/* CTRL_MST_CONTROLLER_MODE Value */
+#define MXC_V_I2C_CTRL_MST_CONTROLLER_MODE 0x1UL
+/* CTRL_MST_CONTROLLER_MODE Setting */
+#define MXC_S_I2C_CTRL_MST_CONTROLLER_MODE \
+	(MXC_V_I2C_CTRL_MST_CONTROLLER_MODE << MXC_F_I2C_CTRL_MST_POS)
+
+/* CTRL_GEN_CALL_ADDR Position */
+#define MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS 2
+/* CTRL_GEN_CALL_ADDR Mask */
+#define MXC_F_I2C_CTRL_GEN_CALL_ADDR (0x1UL << MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS)
+/* CTRL_GEN_CALL_ADDR_DIS Value */
+#define MXC_V_I2C_CTRL_GEN_CALL_ADDR_DIS 0x0UL
+/* CTRL_GEN_CALL_ADDR_DIS Setting */
+#define MXC_S_I2C_CTRL_GEN_CALL_ADDR_DIS \
+	(MXC_V_I2C_CTRL_GEN_CALL_ADDR_DIS << MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS)
+/* CTRL_GEN_CALL_ADDR_EN Value */
+#define MXC_V_I2C_CTRL_GEN_CALL_ADDR_EN 0x1UL
+/* CTRL_GEN_CALL_ADDR_EN Setting */
+#define MXC_S_I2C_CTRL_GEN_CALL_ADDR_EN \
+	(MXC_V_I2C_CTRL_GEN_CALL_ADDR_EN << MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS)
+
+/* CTRL_RX_MODE Position */
+#define MXC_F_I2C_CTRL_RX_MODE_POS 3
+/* CTRL_RX_MODE Mask */
+#define MXC_F_I2C_CTRL_RX_MODE (0x1UL << MXC_F_I2C_CTRL_RX_MODE_POS)
+/* CTRL_RX_MODE_DIS Value */
+#define MXC_V_I2C_CTRL_RX_MODE_DIS 0x0UL
+/* CTRL_RX_MODE_DIS Setting */
+#define MXC_S_I2C_CTRL_RX_MODE_DIS \
+	(MXC_V_I2C_CTRL_RX_MODE_DIS << MXC_F_I2C_CTRL_RX_MODE_POS)
+/* CTRL_RX_MODE_EN Value */
+#define MXC_V_I2C_CTRL_RX_MODE_EN 0x1UL
+/* CTRL_RX_MODE_EN Setting */
+#define MXC_S_I2C_CTRL_RX_MODE_EN \
+	(MXC_V_I2C_CTRL_RX_MODE_EN << MXC_F_I2C_CTRL_RX_MODE_POS)
+
+/* CTRL_RX_MODE_ACK Position */
+#define MXC_F_I2C_CTRL_RX_MODE_ACK_POS 4
+/* CTRL_RX_MODE_ACK Mask */
+#define MXC_F_I2C_CTRL_RX_MODE_ACK (0x1UL << MXC_F_I2C_CTRL_RX_MODE_ACK_POS)
+/* CTRL_RX_MODE_ACK_ACK Value */
+#define MXC_V_I2C_CTRL_RX_MODE_ACK_ACK 0x0UL
+/* CTRL_RX_MODE_ACK_ACK Setting */
+#define MXC_S_I2C_CTRL_RX_MODE_ACK_ACK \
+	(MXC_V_I2C_CTRL_RX_MODE_ACK_ACK << MXC_F_I2C_CTRL_RX_MODE_ACK_POS)
+/* CTRL_RX_MODE_ACK_NACK Value */
+#define MXC_V_I2C_CTRL_RX_MODE_ACK_NACK 0x1UL
+/* CTRL_RX_MODE_ACK_NACK Setting */
+#define MXC_S_I2C_CTRL_RX_MODE_ACK_NACK \
+	(MXC_V_I2C_CTRL_RX_MODE_ACK_NACK << MXC_F_I2C_CTRL_RX_MODE_ACK_POS)
+
+/* CTRL_SCL_OUT Position */
+#define MXC_F_I2C_CTRL_SCL_OUT_POS 6
+/* CTRL_SCL_OUT Mask */
+#define MXC_F_I2C_CTRL_SCL_OUT (0x1UL << MXC_F_I2C_CTRL_SCL_OUT_POS)
+/* CTRL_SCL_OUT_DRIVE_SCL_LOW Value */
+#define MXC_V_I2C_CTRL_SCL_OUT_DRIVE_SCL_LOW 0x0UL
+/* CTRL_SCL_OUT_DRIVE_SCL_LOW Setting */
+#define MXC_S_I2C_CTRL_SCL_OUT_DRIVE_SCL_LOW \
+	(MXC_V_I2C_CTRL_SCL_OUT_DRIVE_SCL_LOW << MXC_F_I2C_CTRL_SCL_OUT_POS)
+/* CTRL_SCL_OUT_RELEASE_SCL Value */
+#define MXC_V_I2C_CTRL_SCL_OUT_RELEASE_SCL 0x1UL
+/* CTRL_SCL_OUT_RELEASE_SCL Setting */
+#define MXC_S_I2C_CTRL_SCL_OUT_RELEASE_SCL \
+	(MXC_V_I2C_CTRL_SCL_OUT_RELEASE_SCL << MXC_F_I2C_CTRL_SCL_OUT_POS)
+
+/* CTRL_SDA_OUT Position */
+#define MXC_F_I2C_CTRL_SDA_OUT_POS 7
+/* CTRL_SDA_OUT Mask */
+#define MXC_F_I2C_CTRL_SDA_OUT (0x1UL << MXC_F_I2C_CTRL_SDA_OUT_POS)
+/* CTRL_SDA_OUT_DRIVE_SDA_LOW Value */
+#define MXC_V_I2C_CTRL_SDA_OUT_DRIVE_SDA_LOW 0x0UL
+/* CTRL_SDA_OUT_DRIVE_SDA_LOW Setting */
+#define MXC_S_I2C_CTRL_SDA_OUT_DRIVE_SDA_LOW \
+	(MXC_V_I2C_CTRL_SDA_OUT_DRIVE_SDA_LOW << MXC_F_I2C_CTRL_SDA_OUT_POS)
+/* CTRL_SDA_OUT_RELEASE_SDA Value */
+#define MXC_V_I2C_CTRL_SDA_OUT_RELEASE_SDA 0x1UL
+/* CTRL_SDA_OUT_RELEASE_SDA Setting */
+#define MXC_S_I2C_CTRL_SDA_OUT_RELEASE_SDA \
+	(MXC_V_I2C_CTRL_SDA_OUT_RELEASE_SDA << MXC_F_I2C_CTRL_SDA_OUT_POS)
+
+/* CTRL_SCL Position */
+#define MXC_F_I2C_CTRL_SCL_POS 8
+/* CTRL_SCL Mask */
+#define MXC_F_I2C_CTRL_SCL (0x1UL << MXC_F_I2C_CTRL_SCL_POS)
+
+/* CTRL_SDA Position */
+#define MXC_F_I2C_CTRL_SDA_POS 9
+/* CTRL_SDA Mask */
+#define MXC_F_I2C_CTRL_SDA (0x1UL << MXC_F_I2C_CTRL_SDA_POS)
+
+/* CTRL_SW_OUT_EN Position */
+#define MXC_F_I2C_CTRL_SW_OUT_EN_POS 10
+/* CTRL_SW_OUT_EN Mask */
+#define MXC_F_I2C_CTRL_SW_OUT_EN (0x1UL << MXC_F_I2C_CTRL_SW_OUT_EN_POS)
+/* CTRL_SW_OUT_EN_OUTPUTS_DISABLE Value */
+#define MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_DISABLE 0x0UL
+/* CTRL_SW_OUT_EN_OUTPUTS_DISABLE Setting */
 #define MXC_S_I2C_CTRL_SW_OUT_EN_OUTPUTS_DISABLE  \
 	(MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_DISABLE \
-	 << MXC_F_I2C_CTRL_SW_OUT_EN_POS) /**< CTRL_SW_OUT_EN_OUTPUTS_DISABLE  \
-					     Setting */
-#define MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_ENABLE \
-	((uint32_t)0x1UL) /**< CTRL_SW_OUT_EN_OUTPUTS_ENABLE Value */
+	 << MXC_F_I2C_CTRL_SW_OUT_EN_POS)
+/* CTRL_SW_OUT_EN_OUTPUTS_ENABLE Value */
+#define MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_ENABLE 0x1UL
+/* CTRL_SW_OUT_EN_OUTPUTS_ENABLE Setting */
 #define MXC_S_I2C_CTRL_SW_OUT_EN_OUTPUTS_ENABLE  \
 	(MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_ENABLE \
-	 << MXC_F_I2C_CTRL_SW_OUT_EN_POS) /**< CTRL_SW_OUT_EN_OUTPUTS_ENABLE   \
-					     Setting */
-
-#define MXC_F_I2C_CTRL_READ_POS 11 /**< CTRL_READ Position */
-#define MXC_F_I2C_CTRL_READ \
-	((uint32_t)(0x1UL << MXC_F_I2C_CTRL_READ_POS)) /**< CTRL_READ Mask */
-#define MXC_V_I2C_CTRL_READ_WRITE \
-	((uint32_t)0x0UL) /**< CTRL_READ_WRITE Value */
-#define MXC_S_I2C_CTRL_READ_WRITE  \
-	(MXC_V_I2C_CTRL_READ_WRITE \
-	 << MXC_F_I2C_CTRL_READ_POS) /**< CTRL_READ_WRITE Setting */
-#define MXC_V_I2C_CTRL_READ_READ \
-	((uint32_t)0x1UL) /**< CTRL_READ_READ Value                            \
-			   */
-#define MXC_S_I2C_CTRL_READ_READ  \
-	(MXC_V_I2C_CTRL_READ_READ \
-	 << MXC_F_I2C_CTRL_READ_POS) /**< CTRL_READ_READ Setting */
-
-#define MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS \
-	12 /**< CTRL_SCL_CLK_STRECH_DIS Position */
+	 << MXC_F_I2C_CTRL_SW_OUT_EN_POS)
+
+/* CTRL_READ Position */
+#define MXC_F_I2C_CTRL_READ_POS 11
+/* CTRL_READ Mask */
+#define MXC_F_I2C_CTRL_READ (0x1UL << MXC_F_I2C_CTRL_READ_POS)
+/* CTRL_READ_WRITE Value */
+#define MXC_V_I2C_CTRL_READ_WRITE 0x0UL
+/* CTRL_READ_WRITE Setting */
+#define MXC_S_I2C_CTRL_READ_WRITE \
+	(MXC_V_I2C_CTRL_READ_WRITE << MXC_F_I2C_CTRL_READ_POS)
+/* CTRL_READ_READ Value */
+#define MXC_V_I2C_CTRL_READ_READ 0x1UL
+/* CTRL_READ_READ Setting */
+#define MXC_S_I2C_CTRL_READ_READ \
+	(MXC_V_I2C_CTRL_READ_READ << MXC_F_I2C_CTRL_READ_POS)
+
+/* CTRL_SCL_CLK_STRECH_DIS Position */
+#define MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS 12
+/* CTRL_SCL_CLK_STRECH_DIS Mask */
 #define MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS \
-	((uint32_t)(                      \
-		0x1UL                     \
-		<< MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS)) /**<                       \
-							      CTRL_SCL_CLK_STRECH_DIS \
-							      Mask */
-#define MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_EN \
-	((uint32_t)0x0UL) /**< CTRL_SCL_CLK_STRECH_DIS_EN Value */
+	(0x1UL << MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS)
+/* CTRL_SCL_CLK_STRECH_DIS_EN Value */
+#define MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_EN 0x0UL
+/* CTRL_SCL_CLK_STRECH_DIS_EN Setting */
 #define MXC_S_I2C_CTRL_SCL_CLK_STRECH_DIS_EN  \
 	(MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_EN \
-	 << MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS) /**<                          \
-						      CTRL_SCL_CLK_STRECH_DIS_EN \
-						      Setting */
-#define MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_DIS \
-	((uint32_t)0x1UL) /**< CTRL_SCL_CLK_STRECH_DIS_DIS Value */
+	 << MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS)
+/* CTRL_SCL_CLK_STRECH_DIS_DIS Value */
+#define MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_DIS 0x1UL
+/* CTRL_SCL_CLK_STRECH_DIS_DIS Setting */
 #define MXC_S_I2C_CTRL_SCL_CLK_STRECH_DIS_DIS  \
 	(MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_DIS \
-	 << MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS) /**<                           \
-						      CTRL_SCL_CLK_STRECH_DIS_DIS \
-						      Setting */
-
-#define MXC_F_I2C_CTRL_SCL_PP_MODE_POS 13 /**< CTRL_SCL_PP_MODE Position */
-#define MXC_F_I2C_CTRL_SCL_PP_MODE \
-	((uint32_t)(               \
-		0x1UL              \
-		<< MXC_F_I2C_CTRL_SCL_PP_MODE_POS)) /**< CTRL_SCL_PP_MODE  \
-							   Mask */
-#define MXC_V_I2C_CTRL_SCL_PP_MODE_DIS \
-	((uint32_t)0x0UL) /**< CTRL_SCL_PP_MODE_DIS Value */
-#define MXC_S_I2C_CTRL_SCL_PP_MODE_DIS  \
-	(MXC_V_I2C_CTRL_SCL_PP_MODE_DIS \
-	 << MXC_F_I2C_CTRL_SCL_PP_MODE_POS) /**< CTRL_SCL_PP_MODE_DIS Setting  \
-					     */
-#define MXC_V_I2C_CTRL_SCL_PP_MODE_EN \
-	((uint32_t)0x1UL) /**< CTRL_SCL_PP_MODE_EN Value */
-#define MXC_S_I2C_CTRL_SCL_PP_MODE_EN  \
-	(MXC_V_I2C_CTRL_SCL_PP_MODE_EN \
-	 << MXC_F_I2C_CTRL_SCL_PP_MODE_POS) /**< CTRL_SCL_PP_MODE_EN Setting   \
-					     */
-
-#define MXC_F_I2C_CTRL_HS_MODE_POS 15 /**< CTRL_HS_MODE Position */
-#define MXC_F_I2C_CTRL_HS_MODE \
-	((uint32_t)(0x1UL      \
-		    << MXC_F_I2C_CTRL_HS_MODE_POS)) /**< CTRL_HS_MODE Mask */
-#define MXC_V_I2C_CTRL_HS_MODE_DIS \
-	((uint32_t)0x0UL) /**< CTRL_HS_MODE_DIS Value */
-#define MXC_S_I2C_CTRL_HS_MODE_DIS  \
-	(MXC_V_I2C_CTRL_HS_MODE_DIS \
-	 << MXC_F_I2C_CTRL_HS_MODE_POS) /**< CTRL_HS_MODE_DIS Setting */
-#define MXC_V_I2C_CTRL_HS_MODE_EN \
-	((uint32_t)0x1UL) /**< CTRL_HS_MODE_EN Value */
-#define MXC_S_I2C_CTRL_HS_MODE_EN  \
-	(MXC_V_I2C_CTRL_HS_MODE_EN \
-	 << MXC_F_I2C_CTRL_HS_MODE_POS) /**< CTRL_HS_MODE_EN Setting */
+	 << MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS)
+
+/* CTRL_SCL_PP_MODE Position */
+#define MXC_F_I2C_CTRL_SCL_PP_MODE_POS 13
+/* CTRL_SCL_PP_MODE Mask */
+#define MXC_F_I2C_CTRL_SCL_PP_MODE (0x1UL << MXC_F_I2C_CTRL_SCL_PP_MODE_POS)
+/* CTRL_SCL_PP_MODE_DIS Value */
+#define MXC_V_I2C_CTRL_SCL_PP_MODE_DIS 0x0UL
+/* CTRL_SCL_PP_MODE_DIS Setting */
+#define MXC_S_I2C_CTRL_SCL_PP_MODE_DIS \
+	(MXC_V_I2C_CTRL_SCL_PP_MODE_DIS << MXC_F_I2C_CTRL_SCL_PP_MODE_POS)
+/* CTRL_SCL_PP_MODE_EN Value */
+#define MXC_V_I2C_CTRL_SCL_PP_MODE_EN 0x1UL
+/* CTRL_SCL_PP_MODE_EN Setting */
+#define MXC_S_I2C_CTRL_SCL_PP_MODE_EN \
+	(MXC_V_I2C_CTRL_SCL_PP_MODE_EN << MXC_F_I2C_CTRL_SCL_PP_MODE_POS)
+
+/* CTRL_HS_MODE Position */
+#define MXC_F_I2C_CTRL_HS_MODE_POS 15
+/* CTRL_HS_MODE Mask */
+#define MXC_F_I2C_CTRL_HS_MODE (0x1UL << MXC_F_I2C_CTRL_HS_MODE_POS)
+/* CTRL_HS_MODE_DIS Value */
+#define MXC_V_I2C_CTRL_HS_MODE_DIS 0x0UL
+/* CTRL_HS_MODE_DIS Setting */
+#define MXC_S_I2C_CTRL_HS_MODE_DIS \
+	(MXC_V_I2C_CTRL_HS_MODE_DIS << MXC_F_I2C_CTRL_HS_MODE_POS)
+/* CTRL_HS_MODE_EN Value */
+#define MXC_V_I2C_CTRL_HS_MODE_EN 0x1UL
+/* CTRL_HS_MODE_EN Setting */
+#define MXC_S_I2C_CTRL_HS_MODE_EN \
+	(MXC_V_I2C_CTRL_HS_MODE_EN << MXC_F_I2C_CTRL_HS_MODE_POS)
 
 /**
  * I2C_STATUS I2C_STATUS
  */
-#define MXC_F_I2C_STATUS_BUS_POS 0 /**< STATUS_BUS Position */
-#define MXC_F_I2C_STATUS_BUS \
-	((uint32_t)(0x1UL    \
-		    << MXC_F_I2C_STATUS_BUS_POS)) /**< STATUS_BUS Mask   \
-							 */
-#define MXC_V_I2C_STATUS_BUS_IDLE \
-	((uint32_t)0x0UL) /**< STATUS_BUS_IDLE Value */
-#define MXC_S_I2C_STATUS_BUS_IDLE  \
-	(MXC_V_I2C_STATUS_BUS_IDLE \
-	 << MXC_F_I2C_STATUS_BUS_POS) /**< STATUS_BUS_IDLE Setting */
-#define MXC_V_I2C_STATUS_BUS_BUSY \
-	((uint32_t)0x1UL) /**< STATUS_BUS_BUSY Value */
-#define MXC_S_I2C_STATUS_BUS_BUSY  \
-	(MXC_V_I2C_STATUS_BUS_BUSY \
-	 << MXC_F_I2C_STATUS_BUS_POS) /**< STATUS_BUS_BUSY Setting */
-
-#define MXC_F_I2C_STATUS_RX_EMPTY_POS 1 /**< STATUS_RX_EMPTY Position */
-#define MXC_F_I2C_STATUS_RX_EMPTY \
-	((uint32_t)(0x1UL         \
-		    << MXC_F_I2C_STATUS_RX_EMPTY_POS)) /**< STATUS_RX_EMPTY  \
-							    Mask */
-#define MXC_V_I2C_STATUS_RX_EMPTY_NOT_EMPTY \
-	((uint32_t)0x0UL) /**< STATUS_RX_EMPTY_NOT_EMPTY Value */
-#define MXC_S_I2C_STATUS_RX_EMPTY_NOT_EMPTY  \
-	(MXC_V_I2C_STATUS_RX_EMPTY_NOT_EMPTY \
-	 << MXC_F_I2C_STATUS_RX_EMPTY_POS) /**< STATUS_RX_EMPTY_NOT_EMPTY      \
-					      Setting */
-#define MXC_V_I2C_STATUS_RX_EMPTY_EMPTY \
-	((uint32_t)0x1UL) /**< STATUS_RX_EMPTY_EMPTY Value */
-#define MXC_S_I2C_STATUS_RX_EMPTY_EMPTY  \
-	(MXC_V_I2C_STATUS_RX_EMPTY_EMPTY \
-	 << MXC_F_I2C_STATUS_RX_EMPTY_POS) /**< STATUS_RX_EMPTY_EMPTY Setting  \
-					    */
-
-#define MXC_F_I2C_STATUS_RX_FULL_POS 2 /**< STATUS_RX_FULL Position */
-#define MXC_F_I2C_STATUS_RX_FULL \
-	((uint32_t)(             \
-		0x1UL            \
-		<< MXC_F_I2C_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */
-#define MXC_V_I2C_STATUS_RX_FULL_NOT_FULL \
-	((uint32_t)0x0UL) /**< STATUS_RX_FULL_NOT_FULL Value */
-#define MXC_S_I2C_STATUS_RX_FULL_NOT_FULL  \
-	(MXC_V_I2C_STATUS_RX_FULL_NOT_FULL \
-	 << MXC_F_I2C_STATUS_RX_FULL_POS) /**< STATUS_RX_FULL_NOT_FULL Setting \
-					   */
-#define MXC_V_I2C_STATUS_RX_FULL_FULL \
-	((uint32_t)0x1UL) /**< STATUS_RX_FULL_FULL Value */
-#define MXC_S_I2C_STATUS_RX_FULL_FULL  \
-	(MXC_V_I2C_STATUS_RX_FULL_FULL \
-	 << MXC_F_I2C_STATUS_RX_FULL_POS) /**< STATUS_RX_FULL_FULL Setting */
-
-#define MXC_F_I2C_STATUS_TX_EMPTY_POS 3 /**< STATUS_TX_EMPTY Position */
-#define MXC_F_I2C_STATUS_TX_EMPTY \
-	((uint32_t)(0x1UL         \
-		    << MXC_F_I2C_STATUS_TX_EMPTY_POS)) /**< STATUS_TX_EMPTY  \
-							    Mask */
-#define MXC_V_I2C_STATUS_TX_EMPTY_NOT_EMPTY \
-	((uint32_t)0x0UL) /**< STATUS_TX_EMPTY_NOT_EMPTY Value */
-#define MXC_S_I2C_STATUS_TX_EMPTY_NOT_EMPTY  \
-	(MXC_V_I2C_STATUS_TX_EMPTY_NOT_EMPTY \
-	 << MXC_F_I2C_STATUS_TX_EMPTY_POS) /**< STATUS_TX_EMPTY_NOT_EMPTY      \
-					      Setting */
-#define MXC_V_I2C_STATUS_TX_EMPTY_EMPTY \
-	((uint32_t)0x1UL) /**< STATUS_TX_EMPTY_EMPTY Value */
-#define MXC_S_I2C_STATUS_TX_EMPTY_EMPTY  \
-	(MXC_V_I2C_STATUS_TX_EMPTY_EMPTY \
-	 << MXC_F_I2C_STATUS_TX_EMPTY_POS) /**< STATUS_TX_EMPTY_EMPTY Setting  \
-					    */
-
-#define MXC_F_I2C_STATUS_TX_FULL_POS 4 /**< STATUS_TX_FULL Position */
-#define MXC_F_I2C_STATUS_TX_FULL \
-	((uint32_t)(             \
-		0x1UL            \
-		<< MXC_F_I2C_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */
-#define MXC_V_I2C_STATUS_TX_FULL_NOT_EMPTY \
-	((uint32_t)0x0UL) /**< STATUS_TX_FULL_NOT_EMPTY Value */
-#define MXC_S_I2C_STATUS_TX_FULL_NOT_EMPTY  \
-	(MXC_V_I2C_STATUS_TX_FULL_NOT_EMPTY \
-	 << MXC_F_I2C_STATUS_TX_FULL_POS) /**< STATUS_TX_FULL_NOT_EMPTY        \
-					     Setting */
-#define MXC_V_I2C_STATUS_TX_FULL_EMPTY \
-	((uint32_t)0x1UL) /**< STATUS_TX_FULL_EMPTY Value */
-#define MXC_S_I2C_STATUS_TX_FULL_EMPTY  \
-	(MXC_V_I2C_STATUS_TX_FULL_EMPTY \
-	 << MXC_F_I2C_STATUS_TX_FULL_POS) /**< STATUS_TX_FULL_EMPTY Setting */
-
-#define MXC_F_I2C_STATUS_CLK_MODE_POS 5 /**< STATUS_CLK_MODE Position */
-#define MXC_F_I2C_STATUS_CLK_MODE \
-	((uint32_t)(0x1UL         \
-		    << MXC_F_I2C_STATUS_CLK_MODE_POS)) /**< STATUS_CLK_MODE  \
-							    Mask */
-#define MXC_V_I2C_STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK \
-	((uint32_t)0x0UL) /**< STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK  \
-			     Value */
+/* STATUS_BUS Position */
+#define MXC_F_I2C_STATUS_BUS_POS 0
+/* STATUS_BUS Mask */
+#define MXC_F_I2C_STATUS_BUS (0x1UL << MXC_F_I2C_STATUS_BUS_POS)
+#define MXC_V_I2C_STATUS_BUS_IDLE 0x0UL /* STATUS_BUS_IDLE Value */
+/* STATUS_BUS_IDLE Setting */
+#define MXC_S_I2C_STATUS_BUS_IDLE \
+	(MXC_V_I2C_STATUS_BUS_IDLE << MXC_F_I2C_STATUS_BUS_POS)
+/* STATUS_BUS_BUSY Value */
+#define MXC_V_I2C_STATUS_BUS_BUSY 0x1UL
+/* STATUS_BUS_BUSY Setting */
+#define MXC_S_I2C_STATUS_BUS_BUSY \
+	(MXC_V_I2C_STATUS_BUS_BUSY << MXC_F_I2C_STATUS_BUS_POS)
+
+/* STATUS_RX_EMPTY Position */
+#define MXC_F_I2C_STATUS_RX_EMPTY_POS 1
+/* STATUS_RX_EMPTY Mask */
+#define MXC_F_I2C_STATUS_RX_EMPTY (0x1UL << MXC_F_I2C_STATUS_RX_EMPTY_POS)
+/* STATUS_RX_EMPTY_NOT_EMPTY Value */
+#define MXC_V_I2C_STATUS_RX_EMPTY_NOT_EMPTY 0x0UL
+/* STATUS_RX_EMPTY_NOT_EMPTY Setting */
+#define MXC_S_I2C_STATUS_RX_EMPTY_NOT_EMPTY \
+	(MXC_V_I2C_STATUS_RX_EMPTY_NOT_EMPTY << MXC_F_I2C_STATUS_RX_EMPTY_POS)
+/* STATUS_RX_EMPTY_EMPTY Value */
+#define MXC_V_I2C_STATUS_RX_EMPTY_EMPTY 0x1UL
+/* STATUS_RX_EMPTY_EMPTY Setting */
+#define MXC_S_I2C_STATUS_RX_EMPTY_EMPTY \
+	(MXC_V_I2C_STATUS_RX_EMPTY_EMPTY << MXC_F_I2C_STATUS_RX_EMPTY_POS)
+
+/* STATUS_RX_FULL Position */
+#define MXC_F_I2C_STATUS_RX_FULL_POS 2
+/* STATUS_RX_FULL Mask */
+#define MXC_F_I2C_STATUS_RX_FULL (0x1UL << MXC_F_I2C_STATUS_RX_FULL_POS)
+/* STATUS_RX_FULL_NOT_FULL Value */
+#define MXC_V_I2C_STATUS_RX_FULL_NOT_FULL 0x0UL
+/* STATUS_RX_FULL_NOT_FULL Setting */
+#define MXC_S_I2C_STATUS_RX_FULL_NOT_FULL \
+	(MXC_V_I2C_STATUS_RX_FULL_NOT_FULL << MXC_F_I2C_STATUS_RX_FULL_POS)
+/* STATUS_RX_FULL_FULL Value */
+#define MXC_V_I2C_STATUS_RX_FULL_FULL 0x1UL
+/* STATUS_RX_FULL_FULL Setting */
+#define MXC_S_I2C_STATUS_RX_FULL_FULL \
+	(MXC_V_I2C_STATUS_RX_FULL_FULL << MXC_F_I2C_STATUS_RX_FULL_POS)
+
+/* STATUS_TX_EMPTY Position */
+#define MXC_F_I2C_STATUS_TX_EMPTY_POS 3
+/* STATUS_TX_EMPTY Mask */
+#define MXC_F_I2C_STATUS_TX_EMPTY (0x1UL << MXC_F_I2C_STATUS_TX_EMPTY_POS)
+/* STATUS_TX_EMPTY_NOT_EMPTY Value */
+#define MXC_V_I2C_STATUS_TX_EMPTY_NOT_EMPTY 0x0UL
+/* STATUS_TX_EMPTY_NOT_EMPTY Setting */
+#define MXC_S_I2C_STATUS_TX_EMPTY_NOT_EMPTY \
+	(MXC_V_I2C_STATUS_TX_EMPTY_NOT_EMPTY << MXC_F_I2C_STATUS_TX_EMPTY_POS)
+/* STATUS_TX_EMPTY_EMPTY Value */
+#define MXC_V_I2C_STATUS_TX_EMPTY_EMPTY 0x1UL
+/* STATUS_TX_EMPTY_EMPTY Setting */
+#define MXC_S_I2C_STATUS_TX_EMPTY_EMPTY \
+	(MXC_V_I2C_STATUS_TX_EMPTY_EMPTY << MXC_F_I2C_STATUS_TX_EMPTY_POS)
+
+/* STATUS_TX_FULL Position */
+#define MXC_F_I2C_STATUS_TX_FULL_POS 4
+/* STATUS_TX_FULL Mask */
+#define MXC_F_I2C_STATUS_TX_FULL (0x1UL << MXC_F_I2C_STATUS_TX_FULL_POS)
+/* STATUS_TX_FULL_NOT_EMPTY Value */
+#define MXC_V_I2C_STATUS_TX_FULL_NOT_EMPTY 0x0UL
+/* STATUS_TX_FULL_NOT_EMPTY Setting */
+#define MXC_S_I2C_STATUS_TX_FULL_NOT_EMPTY \
+	(MXC_V_I2C_STATUS_TX_FULL_NOT_EMPTY << MXC_F_I2C_STATUS_TX_FULL_POS)
+/* STATUS_TX_FULL_EMPTY Value */
+#define MXC_V_I2C_STATUS_TX_FULL_EMPTY 0x1UL
+/* STATUS_TX_FULL_EMPTY Setting */
+#define MXC_S_I2C_STATUS_TX_FULL_EMPTY \
+	(MXC_V_I2C_STATUS_TX_FULL_EMPTY << MXC_F_I2C_STATUS_TX_FULL_POS)
+
+/* STATUS_CLK_MODE Position */
+#define MXC_F_I2C_STATUS_CLK_MODE_POS 5
+/* STATUS_CLK_MODE Mask */
+#define MXC_F_I2C_STATUS_CLK_MODE (0x1UL << MXC_F_I2C_STATUS_CLK_MODE_POS)
+/* STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK Value */
+#define MXC_V_I2C_STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK 0x0UL
+/* STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK Setting */
 #define MXC_S_I2C_STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK  \
 	(MXC_V_I2C_STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK \
-	 << MXC_F_I2C_STATUS_CLK_MODE_POS) /**<                                              \
-					      STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK \
-					      Setting */
-#define MXC_V_I2C_STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK \
-	((uint32_t)0x1UL) /**< STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK      \
-			     Value */
+	 << MXC_F_I2C_STATUS_CLK_MODE_POS)
+/* STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK Value */
+#define MXC_V_I2C_STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK 0x1UL
+/* STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK Setting */
 #define MXC_S_I2C_STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK  \
 	(MXC_V_I2C_STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK \
-	 << MXC_F_I2C_STATUS_CLK_MODE_POS) /**<                                          \
-					      STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK \
-					      Setting */
-
-#define MXC_F_I2C_STATUS_STATUS_POS 8 /**< STATUS_STATUS Position */
-#define MXC_F_I2C_STATUS_STATUS \
-	((uint32_t)(            \
-		0xFUL           \
-		<< MXC_F_I2C_STATUS_STATUS_POS)) /**< STATUS_STATUS Mask */
-#define MXC_V_I2C_STATUS_STATUS_IDLE \
-	((uint32_t)0x0UL) /**< STATUS_STATUS_IDLE Value */
-#define MXC_S_I2C_STATUS_STATUS_IDLE  \
-	(MXC_V_I2C_STATUS_STATUS_IDLE \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_IDLE Setting */
-#define MXC_V_I2C_STATUS_STATUS_MTX_ADDR \
-	((uint32_t)0x1UL) /**< STATUS_STATUS_MTX_ADDR Value */
-#define MXC_S_I2C_STATUS_STATUS_MTX_ADDR  \
-	(MXC_V_I2C_STATUS_STATUS_MTX_ADDR \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MTX_ADDR Setting   \
-					  */
-#define MXC_V_I2C_STATUS_STATUS_MRX_ADDR_ACK \
-	((uint32_t)0x2UL) /**< STATUS_STATUS_MRX_ADDR_ACK Value */
-#define MXC_S_I2C_STATUS_STATUS_MRX_ADDR_ACK  \
-	(MXC_V_I2C_STATUS_STATUS_MRX_ADDR_ACK \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MRX_ADDR_ACK       \
-					    Setting */
-#define MXC_V_I2C_STATUS_STATUS_MTX_EX_ADDR \
-	((uint32_t)0x3UL) /**< STATUS_STATUS_MTX_EX_ADDR Value */
-#define MXC_S_I2C_STATUS_STATUS_MTX_EX_ADDR  \
-	(MXC_V_I2C_STATUS_STATUS_MTX_EX_ADDR \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MTX_EX_ADDR        \
-					    Setting */
-#define MXC_V_I2C_STATUS_STATUS_MRX_EX_ADDR \
-	((uint32_t)0x4UL) /**< STATUS_STATUS_MRX_EX_ADDR Value */
-#define MXC_S_I2C_STATUS_STATUS_MRX_EX_ADDR  \
-	(MXC_V_I2C_STATUS_STATUS_MRX_EX_ADDR \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MRX_EX_ADDR        \
-					    Setting */
-#define MXC_V_I2C_STATUS_STATUS_SRX_ADDR \
-	((uint32_t)0x5UL) /**< STATUS_STATUS_SRX_ADDR Value */
-#define MXC_S_I2C_STATUS_STATUS_SRX_ADDR  \
-	(MXC_V_I2C_STATUS_STATUS_SRX_ADDR \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_SRX_ADDR Setting   \
-					  */
-#define MXC_V_I2C_STATUS_STATUS_STX_ADDR_ACK \
-	((uint32_t)0x6UL) /**< STATUS_STATUS_STX_ADDR_ACK Value */
-#define MXC_S_I2C_STATUS_STATUS_STX_ADDR_ACK  \
-	(MXC_V_I2C_STATUS_STATUS_STX_ADDR_ACK \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_STX_ADDR_ACK       \
-					    Setting */
-#define MXC_V_I2C_STATUS_STATUS_SRX_EX_ADDR \
-	((uint32_t)0x7UL) /**< STATUS_STATUS_SRX_EX_ADDR Value */
-#define MXC_S_I2C_STATUS_STATUS_SRX_EX_ADDR  \
-	(MXC_V_I2C_STATUS_STATUS_SRX_EX_ADDR \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_SRX_EX_ADDR        \
-					    Setting */
-#define MXC_V_I2C_STATUS_STATUS_STX_EX_ADDR_ACK \
-	((uint32_t)0x8UL) /**< STATUS_STATUS_STX_EX_ADDR_ACK Value */
-#define MXC_S_I2C_STATUS_STATUS_STX_EX_ADDR_ACK  \
-	(MXC_V_I2C_STATUS_STATUS_STX_EX_ADDR_ACK \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_STX_EX_ADDR_ACK    \
-					    Setting */
-#define MXC_V_I2C_STATUS_STATUS_TX \
-	((uint32_t)0x9UL) /**< STATUS_STATUS_TX Value */
-#define MXC_S_I2C_STATUS_STATUS_TX  \
-	(MXC_V_I2C_STATUS_STATUS_TX \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_TX Setting */
-#define MXC_V_I2C_STATUS_STATUS_RX_ACK \
-	((uint32_t)0xAUL) /**< STATUS_STATUS_RX_ACK Value */
-#define MXC_S_I2C_STATUS_STATUS_RX_ACK  \
-	(MXC_V_I2C_STATUS_STATUS_RX_ACK \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_RX_ACK Setting */
-#define MXC_V_I2C_STATUS_STATUS_RX \
-	((uint32_t)0xBUL) /**< STATUS_STATUS_RX Value */
-#define MXC_S_I2C_STATUS_STATUS_RX  \
-	(MXC_V_I2C_STATUS_STATUS_RX \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_RX Setting */
-#define MXC_V_I2C_STATUS_STATUS_TX_ACK \
-	((uint32_t)0xCUL) /**< STATUS_STATUS_TX_ACK Value */
-#define MXC_S_I2C_STATUS_STATUS_TX_ACK  \
-	(MXC_V_I2C_STATUS_STATUS_TX_ACK \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_TX_ACK Setting */
-#define MXC_V_I2C_STATUS_STATUS_NACK \
-	((uint32_t)0xDUL) /**< STATUS_STATUS_NACK Value */
-#define MXC_S_I2C_STATUS_STATUS_NACK  \
-	(MXC_V_I2C_STATUS_STATUS_NACK \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_NACK Setting */
-#define MXC_V_I2C_STATUS_STATUS_BY_ST \
-	((uint32_t)0xFUL) /**< STATUS_STATUS_BY_ST Value */
-#define MXC_S_I2C_STATUS_STATUS_BY_ST  \
-	(MXC_V_I2C_STATUS_STATUS_BY_ST \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_BY_ST Setting */
+	 << MXC_F_I2C_STATUS_CLK_MODE_POS)
+
+/* STATUS_STATUS Position */
+#define MXC_F_I2C_STATUS_STATUS_POS 8
+/* STATUS_STATUS Mask */
+#define MXC_F_I2C_STATUS_STATUS (0xFUL << MXC_F_I2C_STATUS_STATUS_POS)
+/* STATUS_STATUS_IDLE Value */
+#define MXC_V_I2C_STATUS_STATUS_IDLE 0x0UL
+/* STATUS_STATUS_IDLE Setting */
+#define MXC_S_I2C_STATUS_STATUS_IDLE \
+	(MXC_V_I2C_STATUS_STATUS_IDLE << MXC_F_I2C_STATUS_STATUS_POS)
+/* STATUS_STATUS_MTX_ADDR Value */
+#define MXC_V_I2C_STATUS_STATUS_MTX_ADDR 0x1UL
+/* STATUS_STATUS_MTX_ADDR Setting */
+#define MXC_S_I2C_STATUS_STATUS_MTX_ADDR \
+	(MXC_V_I2C_STATUS_STATUS_MTX_ADDR << MXC_F_I2C_STATUS_STATUS_POS)
+/* STATUS_STATUS_MRX_ADDR_ACK Value */
+#define MXC_V_I2C_STATUS_STATUS_MRX_ADDR_ACK 0x2UL
+/* STATUS_STATUS_MRX_ADDR_ACK Setting */
+#define MXC_S_I2C_STATUS_STATUS_MRX_ADDR_ACK \
+	(MXC_V_I2C_STATUS_STATUS_MRX_ADDR_ACK << MXC_F_I2C_STATUS_STATUS_POS)
+/* STATUS_STATUS_MTX_EX_ADDR Value */
+#define MXC_V_I2C_STATUS_STATUS_MTX_EX_ADDR 0x3UL
+/* STATUS_STATUS_MTX_EX_ADDR Setting */
+#define MXC_S_I2C_STATUS_STATUS_MTX_EX_ADDR \
+	(MXC_V_I2C_STATUS_STATUS_MTX_EX_ADDR << MXC_F_I2C_STATUS_STATUS_POS)
+/* STATUS_STATUS_MRX_EX_ADDR Value */
+#define MXC_V_I2C_STATUS_STATUS_MRX_EX_ADDR 0x4UL
+/* STATUS_STATUS_MRX_EX_ADDR Setting */
+#define MXC_S_I2C_STATUS_STATUS_MRX_EX_ADDR \
+	(MXC_V_I2C_STATUS_STATUS_MRX_EX_ADDR << MXC_F_I2C_STATUS_STATUS_POS)
+/* STATUS_STATUS_SRX_ADDR Value */
+#define MXC_V_I2C_STATUS_STATUS_SRX_ADDR 0x5UL
+/* STATUS_STATUS_SRX_ADDR Setting */
+#define MXC_S_I2C_STATUS_STATUS_SRX_ADDR \
+	(MXC_V_I2C_STATUS_STATUS_SRX_ADDR << MXC_F_I2C_STATUS_STATUS_POS)
+/* STATUS_STATUS_STX_ADDR_ACK Value */
+#define MXC_V_I2C_STATUS_STATUS_STX_ADDR_ACK 0x6UL
+/* STATUS_STATUS_STX_ADDR_ACK Setting */
+#define MXC_S_I2C_STATUS_STATUS_STX_ADDR_ACK \
+	(MXC_V_I2C_STATUS_STATUS_STX_ADDR_ACK << MXC_F_I2C_STATUS_STATUS_POS)
+/* STATUS_STATUS_SRX_EX_ADDR Value */
+#define MXC_V_I2C_STATUS_STATUS_SRX_EX_ADDR 0x7UL
+/* STATUS_STATUS_SRX_EX_ADDR Setting */
+#define MXC_S_I2C_STATUS_STATUS_SRX_EX_ADDR \
+	(MXC_V_I2C_STATUS_STATUS_SRX_EX_ADDR << MXC_F_I2C_STATUS_STATUS_POS)
+/* STATUS_STATUS_STX_EX_ADDR_ACK Value */
+#define MXC_V_I2C_STATUS_STATUS_STX_EX_ADDR_ACK 0x8UL
+/* STATUS_STATUS_STX_EX_ADDR_ACK Setting */
+#define MXC_S_I2C_STATUS_STATUS_STX_EX_ADDR_ACK \
+	(MXC_V_I2C_STATUS_STATUS_STX_EX_ADDR_ACK << MXC_F_I2C_STATUS_STATUS_POS)
+/* STATUS_STATUS_TX Value */
+#define MXC_V_I2C_STATUS_STATUS_TX 0x9UL
+/* STATUS_STATUS_TX Setting */
+#define MXC_S_I2C_STATUS_STATUS_TX \
+	(MXC_V_I2C_STATUS_STATUS_TX << MXC_F_I2C_STATUS_STATUS_POS)
+/* STATUS_STATUS_RX_ACK Value */
+#define MXC_V_I2C_STATUS_STATUS_RX_ACK 0xAUL
+/* STATUS_STATUS_RX_ACK Setting */
+#define MXC_S_I2C_STATUS_STATUS_RX_ACK \
+	(MXC_V_I2C_STATUS_STATUS_RX_ACK << MXC_F_I2C_STATUS_STATUS_POS)
+/* STATUS_STATUS_RX Value */
+#define MXC_V_I2C_STATUS_STATUS_RX 0xBUL
+/* STATUS_STATUS_RX Setting */
+#define MXC_S_I2C_STATUS_STATUS_RX \
+	(MXC_V_I2C_STATUS_STATUS_RX << MXC_F_I2C_STATUS_STATUS_POS)
+/* STATUS_STATUS_TX_ACK Value */
+#define MXC_V_I2C_STATUS_STATUS_TX_ACK 0xCUL
+/* STATUS_STATUS_TX_ACK Setting */
+#define MXC_S_I2C_STATUS_STATUS_TX_ACK \
+	(MXC_V_I2C_STATUS_STATUS_TX_ACK << MXC_F_I2C_STATUS_STATUS_POS)
+/* STATUS_STATUS_NACK Value */
+#define MXC_V_I2C_STATUS_STATUS_NACK 0xDUL
+/* STATUS_STATUS_NACK Setting */
+#define MXC_S_I2C_STATUS_STATUS_NACK \
+	(MXC_V_I2C_STATUS_STATUS_NACK << MXC_F_I2C_STATUS_STATUS_POS)
+/* STATUS_STATUS_BY_ST Value */
+#define MXC_V_I2C_STATUS_STATUS_BY_ST 0xFUL
+/* STATUS_STATUS_BY_ST Setting */
+#define MXC_S_I2C_STATUS_STATUS_BY_ST \
+	(MXC_V_I2C_STATUS_STATUS_BY_ST << MXC_F_I2C_STATUS_STATUS_POS)
 
 /**
  * Interrupt Status Register.
  */
-#define MXC_F_I2C_INT_FL0_DONE_POS 0 /**< INT_FL0_DONE Position */
-#define MXC_F_I2C_INT_FL0_DONE \
-	((uint32_t)(0x1UL      \
-		    << MXC_F_I2C_INT_FL0_DONE_POS)) /**< INT_FL0_DONE Mask */
-#define MXC_V_I2C_INT_FL0_DONE_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_DONE_INACTIVE Value */
-#define MXC_S_I2C_INT_FL0_DONE_INACTIVE  \
-	(MXC_V_I2C_INT_FL0_DONE_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_DONE_POS) /**< INT_FL0_DONE_INACTIVE Setting */
-#define MXC_V_I2C_INT_FL0_DONE_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_DONE_PENDING Value */
-#define MXC_S_I2C_INT_FL0_DONE_PENDING  \
-	(MXC_V_I2C_INT_FL0_DONE_PENDING \
-	 << MXC_F_I2C_INT_FL0_DONE_POS) /**< INT_FL0_DONE_PENDING Setting */
-
-#define MXC_F_I2C_INT_FL0_RX_MODE_POS 1 /**< INT_FL0_RX_MODE Position */
-#define MXC_F_I2C_INT_FL0_RX_MODE \
-	((uint32_t)(0x1UL         \
-		    << MXC_F_I2C_INT_FL0_RX_MODE_POS)) /**< INT_FL0_RX_MODE  \
-							    Mask */
-#define MXC_V_I2C_INT_FL0_RX_MODE_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_RX_MODE_INACTIVE Value */
-#define MXC_S_I2C_INT_FL0_RX_MODE_INACTIVE  \
-	(MXC_V_I2C_INT_FL0_RX_MODE_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_RX_MODE_POS) /**< INT_FL0_RX_MODE_INACTIVE       \
-					      Setting */
-#define MXC_V_I2C_INT_FL0_RX_MODE_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_RX_MODE_PENDING Value */
-#define MXC_S_I2C_INT_FL0_RX_MODE_PENDING  \
-	(MXC_V_I2C_INT_FL0_RX_MODE_PENDING \
-	 << MXC_F_I2C_INT_FL0_RX_MODE_POS) /**< INT_FL0_RX_MODE_PENDING        \
-					      Setting */
-
-#define MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS \
-	2 /**< INT_FL0_GEN_CALL_ADDR Position */
+/* INT_FL0_DONE Position */
+#define MXC_F_I2C_INT_FL0_DONE_POS 0
+/* INT_FL0_DONE Mask */
+#define MXC_F_I2C_INT_FL0_DONE (0x1UL << MXC_F_I2C_INT_FL0_DONE_POS)
+/* INT_FL0_DONE_INACTIVE Value */
+#define MXC_V_I2C_INT_FL0_DONE_INACTIVE 0x0UL
+/* INT_FL0_DONE_INACTIVE Setting */
+#define MXC_S_I2C_INT_FL0_DONE_INACTIVE \
+	(MXC_V_I2C_INT_FL0_DONE_INACTIVE << MXC_F_I2C_INT_FL0_DONE_POS)
+/* INT_FL0_DONE_PENDING Value */
+#define MXC_V_I2C_INT_FL0_DONE_PENDING 0x1UL
+/* INT_FL0_DONE_PENDING Setting */
+#define MXC_S_I2C_INT_FL0_DONE_PENDING \
+	(MXC_V_I2C_INT_FL0_DONE_PENDING << MXC_F_I2C_INT_FL0_DONE_POS)
+
+/* INT_FL0_RX_MODE Position */
+#define MXC_F_I2C_INT_FL0_RX_MODE_POS 1
+/* INT_FL0_RX_MODE Mask */
+#define MXC_F_I2C_INT_FL0_RX_MODE (0x1UL << MXC_F_I2C_INT_FL0_RX_MODE_POS)
+/* INT_FL0_RX_MODE_INACTIVE Value */
+#define MXC_V_I2C_INT_FL0_RX_MODE_INACTIVE 0x0UL
+/* INT_FL0_RX_MODE_INACTIVE Setting */
+#define MXC_S_I2C_INT_FL0_RX_MODE_INACTIVE \
+	(MXC_V_I2C_INT_FL0_RX_MODE_INACTIVE << MXC_F_I2C_INT_FL0_RX_MODE_POS)
+/* INT_FL0_RX_MODE_PENDING Value */
+#define MXC_V_I2C_INT_FL0_RX_MODE_PENDING 0x1UL
+/* INT_FL0_RX_MODE_PENDING Setting */
+#define MXC_S_I2C_INT_FL0_RX_MODE_PENDING \
+	(MXC_V_I2C_INT_FL0_RX_MODE_PENDING << MXC_F_I2C_INT_FL0_RX_MODE_POS)
+
+/* INT_FL0_GEN_CALL_ADDR Position */
+#define MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS 2
+/* INT_FL0_GEN_CALL_ADDR Mask */
 #define MXC_F_I2C_INT_FL0_GEN_CALL_ADDR \
-	((uint32_t)(                    \
-		0x1UL                   \
-		<< MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS)) /**<                     \
-							    INT_FL0_GEN_CALL_ADDR \
-							    Mask */
-#define MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_GEN_CALL_ADDR_INACTIVE Value */
+	(0x1UL << MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS)
+/* INT_FL0_GEN_CALL_ADDR_INACTIVE Value */
+#define MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_INACTIVE 0x0UL
+/* INT_FL0_GEN_CALL_ADDR_INACTIVE Setting */
 #define MXC_S_I2C_INT_FL0_GEN_CALL_ADDR_INACTIVE  \
 	(MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS) /**<                              \
-						    INT_FL0_GEN_CALL_ADDR_INACTIVE \
-						    Setting */
-#define MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_GEN_CALL_ADDR_PENDING Value */
+	 << MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS)
+/* INT_FL0_GEN_CALL_ADDR_PENDING Value */
+#define MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_PENDING 0x1UL
+/* INT_FL0_GEN_CALL_ADDR_PENDING Setting */
 #define MXC_S_I2C_INT_FL0_GEN_CALL_ADDR_PENDING  \
 	(MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_PENDING \
-	 << MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS) /**<                             \
-						    INT_FL0_GEN_CALL_ADDR_PENDING \
-						    Setting */
-
-#define MXC_F_I2C_INT_FL0_ADDR_MATCH_POS 3 /**< INT_FL0_ADDR_MATCH Position */
-#define MXC_F_I2C_INT_FL0_ADDR_MATCH \
-	((uint32_t)(                 \
-		0x1UL                \
-		<< MXC_F_I2C_INT_FL0_ADDR_MATCH_POS)) /**< INT_FL0_ADDR_MATCH  \
-							 Mask */
-#define MXC_V_I2C_INT_FL0_ADDR_MATCH_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_ADDR_MATCH_INACTIVE Value */
+	 << MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS)
+
+/* INT_FL0_ADDR_MATCH Position */
+#define MXC_F_I2C_INT_FL0_ADDR_MATCH_POS 3
+/* INT_FL0_ADDR_MATCH Mask */
+#define MXC_F_I2C_INT_FL0_ADDR_MATCH (0x1UL << MXC_F_I2C_INT_FL0_ADDR_MATCH_POS)
+/* INT_FL0_ADDR_MATCH_INACTIVE Value */
+#define MXC_V_I2C_INT_FL0_ADDR_MATCH_INACTIVE 0x0UL
+/* INT_FL0_ADDR_MATCH_INACTIVE Setting */
 #define MXC_S_I2C_INT_FL0_ADDR_MATCH_INACTIVE  \
 	(MXC_V_I2C_INT_FL0_ADDR_MATCH_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_ADDR_MATCH_POS) /**< INT_FL0_ADDR_MATCH_INACTIVE \
-						 Setting */
-#define MXC_V_I2C_INT_FL0_ADDR_MATCH_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_ADDR_MATCH_PENDING Value */
+	 << MXC_F_I2C_INT_FL0_ADDR_MATCH_POS)
+/* INT_FL0_ADDR_MATCH_PENDING Value */
+#define MXC_V_I2C_INT_FL0_ADDR_MATCH_PENDING 0x1UL
+/* INT_FL0_ADDR_MATCH_PENDING Setting */
 #define MXC_S_I2C_INT_FL0_ADDR_MATCH_PENDING  \
 	(MXC_V_I2C_INT_FL0_ADDR_MATCH_PENDING \
-	 << MXC_F_I2C_INT_FL0_ADDR_MATCH_POS) /**< INT_FL0_ADDR_MATCH_PENDING  \
-						 Setting */
-
-#define MXC_F_I2C_INT_FL0_RX_THRESH_POS 4 /**< INT_FL0_RX_THRESH Position */
-#define MXC_F_I2C_INT_FL0_RX_THRESH \
-	((uint32_t)(                \
-		0x1UL               \
-		<< MXC_F_I2C_INT_FL0_RX_THRESH_POS)) /**< INT_FL0_RX_THRESH    \
-							Mask */
-#define MXC_V_I2C_INT_FL0_RX_THRESH_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_RX_THRESH_INACTIVE Value */
+	 << MXC_F_I2C_INT_FL0_ADDR_MATCH_POS)
+
+/* INT_FL0_RX_THRESH Position */
+#define MXC_F_I2C_INT_FL0_RX_THRESH_POS 4
+/* INT_FL0_RX_THRESH Mask */
+#define MXC_F_I2C_INT_FL0_RX_THRESH (0x1UL << MXC_F_I2C_INT_FL0_RX_THRESH_POS)
+/* INT_FL0_RX_THRESH_INACTIVE Value */
+#define MXC_V_I2C_INT_FL0_RX_THRESH_INACTIVE 0x0UL
+/* INT_FL0_RX_THRESH_INACTIVE Setting */
 #define MXC_S_I2C_INT_FL0_RX_THRESH_INACTIVE  \
 	(MXC_V_I2C_INT_FL0_RX_THRESH_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_RX_THRESH_POS) /**< INT_FL0_RX_THRESH_INACTIVE   \
-						Setting */
-#define MXC_V_I2C_INT_FL0_RX_THRESH_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_RX_THRESH_PENDING Value */
-#define MXC_S_I2C_INT_FL0_RX_THRESH_PENDING  \
-	(MXC_V_I2C_INT_FL0_RX_THRESH_PENDING \
-	 << MXC_F_I2C_INT_FL0_RX_THRESH_POS) /**< INT_FL0_RX_THRESH_PENDING    \
-						Setting */
-
-#define MXC_F_I2C_INT_FL0_TX_THRESH_POS 5 /**< INT_FL0_TX_THRESH Position */
-#define MXC_F_I2C_INT_FL0_TX_THRESH \
-	((uint32_t)(                \
-		0x1UL               \
-		<< MXC_F_I2C_INT_FL0_TX_THRESH_POS)) /**< INT_FL0_TX_THRESH    \
-							Mask */
-#define MXC_V_I2C_INT_FL0_TX_THRESH_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_TX_THRESH_INACTIVE Value */
+	 << MXC_F_I2C_INT_FL0_RX_THRESH_POS)
+/* INT_FL0_RX_THRESH_PENDING Value */
+#define MXC_V_I2C_INT_FL0_RX_THRESH_PENDING 0x1UL
+/* INT_FL0_RX_THRESH_PENDING Setting */
+#define MXC_S_I2C_INT_FL0_RX_THRESH_PENDING \
+	(MXC_V_I2C_INT_FL0_RX_THRESH_PENDING << MXC_F_I2C_INT_FL0_RX_THRESH_POS)
+
+/* INT_FL0_TX_THRESH Position */
+#define MXC_F_I2C_INT_FL0_TX_THRESH_POS 5
+/* INT_FL0_TX_THRESH Mask */
+#define MXC_F_I2C_INT_FL0_TX_THRESH (0x1UL << MXC_F_I2C_INT_FL0_TX_THRESH_POS)
+/* INT_FL0_TX_THRESH_INACTIVE Value */
+#define MXC_V_I2C_INT_FL0_TX_THRESH_INACTIVE 0x0UL
+/* INT_FL0_TX_THRESH_INACTIVE Setting */
 #define MXC_S_I2C_INT_FL0_TX_THRESH_INACTIVE  \
 	(MXC_V_I2C_INT_FL0_TX_THRESH_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_TX_THRESH_POS) /**< INT_FL0_TX_THRESH_INACTIVE   \
-						Setting */
-#define MXC_V_I2C_INT_FL0_TX_THRESH_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_TX_THRESH_PENDING Value */
-#define MXC_S_I2C_INT_FL0_TX_THRESH_PENDING  \
-	(MXC_V_I2C_INT_FL0_TX_THRESH_PENDING \
-	 << MXC_F_I2C_INT_FL0_TX_THRESH_POS) /**< INT_FL0_TX_THRESH_PENDING    \
-						Setting */
-
-#define MXC_F_I2C_INT_FL0_STOP_POS 6 /**< INT_FL0_STOP Position */
-#define MXC_F_I2C_INT_FL0_STOP \
-	((uint32_t)(0x1UL      \
-		    << MXC_F_I2C_INT_FL0_STOP_POS)) /**< INT_FL0_STOP Mask */
-#define MXC_V_I2C_INT_FL0_STOP_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_STOP_INACTIVE Value */
-#define MXC_S_I2C_INT_FL0_STOP_INACTIVE  \
-	(MXC_V_I2C_INT_FL0_STOP_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_STOP_POS) /**< INT_FL0_STOP_INACTIVE Setting */
-#define MXC_V_I2C_INT_FL0_STOP_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_STOP_PENDING Value */
-#define MXC_S_I2C_INT_FL0_STOP_PENDING  \
-	(MXC_V_I2C_INT_FL0_STOP_PENDING \
-	 << MXC_F_I2C_INT_FL0_STOP_POS) /**< INT_FL0_STOP_PENDING Setting */
-
-#define MXC_F_I2C_INT_FL0_ADDR_ACK_POS 7 /**< INT_FL0_ADDR_ACK Position */
-#define MXC_F_I2C_INT_FL0_ADDR_ACK \
-	((uint32_t)(               \
-		0x1UL              \
-		<< MXC_F_I2C_INT_FL0_ADDR_ACK_POS)) /**< INT_FL0_ADDR_ACK  \
-							   Mask */
-#define MXC_V_I2C_INT_FL0_ADDR_ACK_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_ADDR_ACK_INACTIVE Value */
-#define MXC_S_I2C_INT_FL0_ADDR_ACK_INACTIVE  \
-	(MXC_V_I2C_INT_FL0_ADDR_ACK_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_ADDR_ACK_POS) /**< INT_FL0_ADDR_ACK_INACTIVE     \
-					       Setting */
-#define MXC_V_I2C_INT_FL0_ADDR_ACK_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_ADDR_ACK_PENDING Value */
-#define MXC_S_I2C_INT_FL0_ADDR_ACK_PENDING  \
-	(MXC_V_I2C_INT_FL0_ADDR_ACK_PENDING \
-	 << MXC_F_I2C_INT_FL0_ADDR_ACK_POS) /**< INT_FL0_ADDR_ACK_PENDING      \
-					       Setting */
-
-#define MXC_F_I2C_INT_FL0_ARB_ER_POS 8 /**< INT_FL0_ARB_ER Position */
-#define MXC_F_I2C_INT_FL0_ARB_ER \
-	((uint32_t)(             \
-		0x1UL            \
-		<< MXC_F_I2C_INT_FL0_ARB_ER_POS)) /**< INT_FL0_ARB_ER Mask */
-#define MXC_V_I2C_INT_FL0_ARB_ER_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_ARB_ER_INACTIVE Value */
-#define MXC_S_I2C_INT_FL0_ARB_ER_INACTIVE  \
-	(MXC_V_I2C_INT_FL0_ARB_ER_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_ARB_ER_POS) /**< INT_FL0_ARB_ER_INACTIVE Setting \
-					   */
-#define MXC_V_I2C_INT_FL0_ARB_ER_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_ARB_ER_PENDING Value */
-#define MXC_S_I2C_INT_FL0_ARB_ER_PENDING  \
-	(MXC_V_I2C_INT_FL0_ARB_ER_PENDING \
-	 << MXC_F_I2C_INT_FL0_ARB_ER_POS) /**< INT_FL0_ARB_ER_PENDING Setting  \
-					   */
-
-#define MXC_F_I2C_INT_FL0_TO_ER_POS 9 /**< INT_FL0_TO_ER Position */
-#define MXC_F_I2C_INT_FL0_TO_ER \
-	((uint32_t)(            \
-		0x1UL           \
-		<< MXC_F_I2C_INT_FL0_TO_ER_POS)) /**< INT_FL0_TO_ER Mask */
-#define MXC_V_I2C_INT_FL0_TO_ER_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_TO_ER_INACTIVE Value */
-#define MXC_S_I2C_INT_FL0_TO_ER_INACTIVE  \
-	(MXC_V_I2C_INT_FL0_TO_ER_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_TO_ER_POS) /**< INT_FL0_TO_ER_INACTIVE Setting   \
-					  */
-#define MXC_V_I2C_INT_FL0_TO_ER_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_TO_ER_PENDING Value */
-#define MXC_S_I2C_INT_FL0_TO_ER_PENDING  \
-	(MXC_V_I2C_INT_FL0_TO_ER_PENDING \
-	 << MXC_F_I2C_INT_FL0_TO_ER_POS) /**< INT_FL0_TO_ER_PENDING Setting */
-
-#define MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS \
-	10 /**< INT_FL0_ADDR_NACK_ER Position */
+	 << MXC_F_I2C_INT_FL0_TX_THRESH_POS)
+/* INT_FL0_TX_THRESH_PENDING Value */
+#define MXC_V_I2C_INT_FL0_TX_THRESH_PENDING 0x1UL
+/* INT_FL0_TX_THRESH_PENDING Setting */
+#define MXC_S_I2C_INT_FL0_TX_THRESH_PENDING \
+	(MXC_V_I2C_INT_FL0_TX_THRESH_PENDING << MXC_F_I2C_INT_FL0_TX_THRESH_POS)
+
+/* INT_FL0_STOP Position */
+#define MXC_F_I2C_INT_FL0_STOP_POS 6
+/* INT_FL0_STOP Mask */
+#define MXC_F_I2C_INT_FL0_STOP (0x1UL << MXC_F_I2C_INT_FL0_STOP_POS)
+/* INT_FL0_STOP_INACTIVE Value */
+#define MXC_V_I2C_INT_FL0_STOP_INACTIVE 0x0UL
+/* INT_FL0_STOP_INACTIVE Setting */
+#define MXC_S_I2C_INT_FL0_STOP_INACTIVE \
+	(MXC_V_I2C_INT_FL0_STOP_INACTIVE << MXC_F_I2C_INT_FL0_STOP_POS)
+/* INT_FL0_STOP_PENDING Value */
+#define MXC_V_I2C_INT_FL0_STOP_PENDING 0x1UL
+/* INT_FL0_STOP_PENDING Setting */
+#define MXC_S_I2C_INT_FL0_STOP_PENDING \
+	(MXC_V_I2C_INT_FL0_STOP_PENDING << MXC_F_I2C_INT_FL0_STOP_POS)
+
+/* INT_FL0_ADDR_ACK Position */
+#define MXC_F_I2C_INT_FL0_ADDR_ACK_POS 7
+/* INT_FL0_ADDR_ACK Mask */
+#define MXC_F_I2C_INT_FL0_ADDR_ACK (0x1UL << MXC_F_I2C_INT_FL0_ADDR_ACK_POS)
+/* INT_FL0_ADDR_ACK_INACTIVE Value */
+#define MXC_V_I2C_INT_FL0_ADDR_ACK_INACTIVE 0x0UL
+/* INT_FL0_ADDR_ACK_INACTIVE Setting */
+#define MXC_S_I2C_INT_FL0_ADDR_ACK_INACTIVE \
+	(MXC_V_I2C_INT_FL0_ADDR_ACK_INACTIVE << MXC_F_I2C_INT_FL0_ADDR_ACK_POS)
+/* INT_FL0_ADDR_ACK_PENDING Value */
+#define MXC_V_I2C_INT_FL0_ADDR_ACK_PENDING 0x1UL
+/* INT_FL0_ADDR_ACK_PENDING Setting */
+#define MXC_S_I2C_INT_FL0_ADDR_ACK_PENDING \
+	(MXC_V_I2C_INT_FL0_ADDR_ACK_PENDING << MXC_F_I2C_INT_FL0_ADDR_ACK_POS)
+
+/* INT_FL0_ARB_ER Position */
+#define MXC_F_I2C_INT_FL0_ARB_ER_POS 8
+/* INT_FL0_ARB_ER Mask */
+#define MXC_F_I2C_INT_FL0_ARB_ER (0x1UL << MXC_F_I2C_INT_FL0_ARB_ER_POS)
+/* INT_FL0_ARB_ER_INACTIVE Value */
+#define MXC_V_I2C_INT_FL0_ARB_ER_INACTIVE 0x0UL
+/* INT_FL0_ARB_ER_INACTIVE Setting */
+#define MXC_S_I2C_INT_FL0_ARB_ER_INACTIVE \
+	(MXC_V_I2C_INT_FL0_ARB_ER_INACTIVE << MXC_F_I2C_INT_FL0_ARB_ER_POS)
+/* INT_FL0_ARB_ER_PENDING Value */
+#define MXC_V_I2C_INT_FL0_ARB_ER_PENDING 0x1UL
+/* INT_FL0_ARB_ER_PENDING Setting */
+#define MXC_S_I2C_INT_FL0_ARB_ER_PENDING \
+	(MXC_V_I2C_INT_FL0_ARB_ER_PENDING << MXC_F_I2C_INT_FL0_ARB_ER_POS)
+
+/* INT_FL0_TO_ER Position */
+#define MXC_F_I2C_INT_FL0_TO_ER_POS 9
+/* INT_FL0_TO_ER Mask */
+#define MXC_F_I2C_INT_FL0_TO_ER (0x1UL << MXC_F_I2C_INT_FL0_TO_ER_POS)
+/* INT_FL0_TO_ER_INACTIVE Value */
+#define MXC_V_I2C_INT_FL0_TO_ER_INACTIVE 0x0UL
+/* INT_FL0_TO_ER_INACTIVE Setting */
+#define MXC_S_I2C_INT_FL0_TO_ER_INACTIVE \
+	(MXC_V_I2C_INT_FL0_TO_ER_INACTIVE << MXC_F_I2C_INT_FL0_TO_ER_POS)
+/* INT_FL0_TO_ER_PENDING Value */
+#define MXC_V_I2C_INT_FL0_TO_ER_PENDING 0x1UL
+/* INT_FL0_TO_ER_PENDING Setting */
+#define MXC_S_I2C_INT_FL0_TO_ER_PENDING \
+	(MXC_V_I2C_INT_FL0_TO_ER_PENDING << MXC_F_I2C_INT_FL0_TO_ER_POS)
+
+/* INT_FL0_ADDR_NACK_ER Position */
+#define MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS 10
+/* INT_FL0_ADDR_NACK_ER Mask */
 #define MXC_F_I2C_INT_FL0_ADDR_NACK_ER \
-	((uint32_t)(                   \
-		0x1UL                  \
-		<< MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS)) /**<                    \
-							   INT_FL0_ADDR_NACK_ER \
-							   Mask */
-#define MXC_V_I2C_INT_FL0_ADDR_NACK_ER_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_ADDR_NACK_ER_INACTIVE Value */
+	(0x1UL << MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS)
+/* INT_FL0_ADDR_NACK_ER_INACTIVE Value */
+#define MXC_V_I2C_INT_FL0_ADDR_NACK_ER_INACTIVE 0x0UL
+/* INT_FL0_ADDR_NACK_ER_INACTIVE Setting */
 #define MXC_S_I2C_INT_FL0_ADDR_NACK_ER_INACTIVE  \
 	(MXC_V_I2C_INT_FL0_ADDR_NACK_ER_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS) /**<                             \
-						   INT_FL0_ADDR_NACK_ER_INACTIVE \
-						   Setting */
-#define MXC_V_I2C_INT_FL0_ADDR_NACK_ER_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_ADDR_NACK_ER_PENDING Value */
+	 << MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS)
+/* INT_FL0_ADDR_NACK_ER_PENDING Value */
+#define MXC_V_I2C_INT_FL0_ADDR_NACK_ER_PENDING 0x1UL
+/* INT_FL0_ADDR_NACK_ER_PENDING Setting */
 #define MXC_S_I2C_INT_FL0_ADDR_NACK_ER_PENDING  \
 	(MXC_V_I2C_INT_FL0_ADDR_NACK_ER_PENDING \
-	 << MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS) /**<                            \
-						   INT_FL0_ADDR_NACK_ER_PENDING \
-						   Setting */
-
-#define MXC_F_I2C_INT_FL0_DATA_ER_POS 11 /**< INT_FL0_DATA_ER Position */
-#define MXC_F_I2C_INT_FL0_DATA_ER \
-	((uint32_t)(0x1UL         \
-		    << MXC_F_I2C_INT_FL0_DATA_ER_POS)) /**< INT_FL0_DATA_ER  \
-							    Mask */
-#define MXC_V_I2C_INT_FL0_DATA_ER_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_DATA_ER_INACTIVE Value */
-#define MXC_S_I2C_INT_FL0_DATA_ER_INACTIVE  \
-	(MXC_V_I2C_INT_FL0_DATA_ER_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_DATA_ER_POS) /**< INT_FL0_DATA_ER_INACTIVE       \
-					      Setting */
-#define MXC_V_I2C_INT_FL0_DATA_ER_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_DATA_ER_PENDING Value */
-#define MXC_S_I2C_INT_FL0_DATA_ER_PENDING  \
-	(MXC_V_I2C_INT_FL0_DATA_ER_PENDING \
-	 << MXC_F_I2C_INT_FL0_DATA_ER_POS) /**< INT_FL0_DATA_ER_PENDING        \
-					      Setting */
-
-#define MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS \
-	12 /**< INT_FL0_DO_NOT_RESP_ER Position */
+	 << MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS)
+
+/* INT_FL0_DATA_ER Position */
+#define MXC_F_I2C_INT_FL0_DATA_ER_POS 11
+/* INT_FL0_DATA_ER Mask */
+#define MXC_F_I2C_INT_FL0_DATA_ER (0x1UL << MXC_F_I2C_INT_FL0_DATA_ER_POS)
+/* INT_FL0_DATA_ER_INACTIVE Value */
+#define MXC_V_I2C_INT_FL0_DATA_ER_INACTIVE 0x0UL
+/* INT_FL0_DATA_ER_INACTIVE Setting */
+#define MXC_S_I2C_INT_FL0_DATA_ER_INACTIVE \
+	(MXC_V_I2C_INT_FL0_DATA_ER_INACTIVE << MXC_F_I2C_INT_FL0_DATA_ER_POS)
+/* INT_FL0_DATA_ER_PENDING Value */
+#define MXC_V_I2C_INT_FL0_DATA_ER_PENDING 0x1UL
+/* INT_FL0_DATA_ER_PENDING Setting */
+#define MXC_S_I2C_INT_FL0_DATA_ER_PENDING \
+	(MXC_V_I2C_INT_FL0_DATA_ER_PENDING << MXC_F_I2C_INT_FL0_DATA_ER_POS)
+
+/* INT_FL0_DO_NOT_RESP_ER Position */
+#define MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS 12
+/* INT_FL0_DO_NOT_RESP_ER Mask */
 #define MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER \
-	((uint32_t)(                     \
-		0x1UL                    \
-		<< MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS)) /**<                      \
-							     INT_FL0_DO_NOT_RESP_ER \
-							     Mask */
-#define MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_DO_NOT_RESP_ER_INACTIVE Value */
+	(0x1UL << MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS)
+/* INT_FL0_DO_NOT_RESP_ER_INACTIVE Value */
+#define MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_INACTIVE 0x0UL
+/* INT_FL0_DO_NOT_RESP_ER_INACTIVE Setting */
 #define MXC_S_I2C_INT_FL0_DO_NOT_RESP_ER_INACTIVE  \
 	(MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS) /**<                               \
-						     INT_FL0_DO_NOT_RESP_ER_INACTIVE \
-						     Setting */
-#define MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_DO_NOT_RESP_ER_PENDING Value */
+	 << MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS)
+/* INT_FL0_DO_NOT_RESP_ER_PENDING Value */
+#define MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_PENDING 0x1UL
+/* INT_FL0_DO_NOT_RESP_ER_PENDING Setting */
 #define MXC_S_I2C_INT_FL0_DO_NOT_RESP_ER_PENDING  \
 	(MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_PENDING \
-	 << MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS) /**<                              \
-						     INT_FL0_DO_NOT_RESP_ER_PENDING \
-						     Setting */
-
-#define MXC_F_I2C_INT_FL0_START_ER_POS 13 /**< INT_FL0_START_ER Position */
-#define MXC_F_I2C_INT_FL0_START_ER \
-	((uint32_t)(               \
-		0x1UL              \
-		<< MXC_F_I2C_INT_FL0_START_ER_POS)) /**< INT_FL0_START_ER  \
-							   Mask */
-#define MXC_V_I2C_INT_FL0_START_ER_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_START_ER_INACTIVE Value */
-#define MXC_S_I2C_INT_FL0_START_ER_INACTIVE  \
-	(MXC_V_I2C_INT_FL0_START_ER_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_START_ER_POS) /**< INT_FL0_START_ER_INACTIVE     \
-					       Setting */
-#define MXC_V_I2C_INT_FL0_START_ER_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_START_ER_PENDING Value */
-#define MXC_S_I2C_INT_FL0_START_ER_PENDING  \
-	(MXC_V_I2C_INT_FL0_START_ER_PENDING \
-	 << MXC_F_I2C_INT_FL0_START_ER_POS) /**< INT_FL0_START_ER_PENDING      \
-					       Setting */
-
-#define MXC_F_I2C_INT_FL0_STOP_ER_POS 14 /**< INT_FL0_STOP_ER Position */
-#define MXC_F_I2C_INT_FL0_STOP_ER \
-	((uint32_t)(0x1UL         \
-		    << MXC_F_I2C_INT_FL0_STOP_ER_POS)) /**< INT_FL0_STOP_ER  \
-							    Mask */
-#define MXC_V_I2C_INT_FL0_STOP_ER_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_STOP_ER_INACTIVE Value */
-#define MXC_S_I2C_INT_FL0_STOP_ER_INACTIVE  \
-	(MXC_V_I2C_INT_FL0_STOP_ER_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_STOP_ER_POS) /**< INT_FL0_STOP_ER_INACTIVE       \
-					      Setting */
-#define MXC_V_I2C_INT_FL0_STOP_ER_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_STOP_ER_PENDING Value */
-#define MXC_S_I2C_INT_FL0_STOP_ER_PENDING  \
-	(MXC_V_I2C_INT_FL0_STOP_ER_PENDING \
-	 << MXC_F_I2C_INT_FL0_STOP_ER_POS) /**< INT_FL0_STOP_ER_PENDING        \
-					      Setting */
-
-#define MXC_F_I2C_INT_FL0_TX_LOCK_OUT_POS \
-	15 /**< INT_FL0_TX_LOCK_OUT Position */
+	 << MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS)
+
+/* INT_FL0_START_ER Position */
+#define MXC_F_I2C_INT_FL0_START_ER_POS 13
+/* INT_FL0_START_ER Mask */
+#define MXC_F_I2C_INT_FL0_START_ER (0x1UL << MXC_F_I2C_INT_FL0_START_ER_POS)
+/* INT_FL0_START_ER_INACTIVE Value */
+#define MXC_V_I2C_INT_FL0_START_ER_INACTIVE 0x0UL
+/* INT_FL0_START_ER_INACTIVE Setting */
+#define MXC_S_I2C_INT_FL0_START_ER_INACTIVE \
+	(MXC_V_I2C_INT_FL0_START_ER_INACTIVE << MXC_F_I2C_INT_FL0_START_ER_POS)
+/* INT_FL0_START_ER_PENDING Value */
+#define MXC_V_I2C_INT_FL0_START_ER_PENDING 0x1UL
+/* INT_FL0_START_ER_PENDING Setting */
+#define MXC_S_I2C_INT_FL0_START_ER_PENDING \
+	(MXC_V_I2C_INT_FL0_START_ER_PENDING << MXC_F_I2C_INT_FL0_START_ER_POS)
+
+/* INT_FL0_STOP_ER Position */
+#define MXC_F_I2C_INT_FL0_STOP_ER_POS 14
+/* INT_FL0_STOP_ER Mask */
+#define MXC_F_I2C_INT_FL0_STOP_ER (0x1UL << MXC_F_I2C_INT_FL0_STOP_ER_POS)
+/* INT_FL0_STOP_ER_INACTIVE Value */
+#define MXC_V_I2C_INT_FL0_STOP_ER_INACTIVE 0x0UL
+/* INT_FL0_STOP_ER_INACTIVE Setting */
+#define MXC_S_I2C_INT_FL0_STOP_ER_INACTIVE \
+	(MXC_V_I2C_INT_FL0_STOP_ER_INACTIVE << MXC_F_I2C_INT_FL0_STOP_ER_POS)
+/* INT_FL0_STOP_ER_PENDING Value */
+#define MXC_V_I2C_INT_FL0_STOP_ER_PENDING 0x1UL
+/* INT_FL0_STOP_ER_PENDING Setting */
+#define MXC_S_I2C_INT_FL0_STOP_ER_PENDING \
+	(MXC_V_I2C_INT_FL0_STOP_ER_PENDING << MXC_F_I2C_INT_FL0_STOP_ER_POS)
+
+/* INT_FL0_TX_LOCK_OUT Position */
+#define MXC_F_I2C_INT_FL0_TX_LOCK_OUT_POS 15
+/* INT_FL0_TX_LOCK_OUT Mask */
 #define MXC_F_I2C_INT_FL0_TX_LOCK_OUT \
-	((uint32_t)(                  \
-		0x1UL                 \
-		<< MXC_F_I2C_INT_FL0_TX_LOCK_OUT_POS)) /**<                    \
-							  INT_FL0_TX_LOCK_OUT  \
-							  Mask */
+	(0x1UL << MXC_F_I2C_INT_FL0_TX_LOCK_OUT_POS)
 
-#define MXC_F_I2C_INT_FL0_MAMI_POS 16 /**< INT_FL0_MAMI Position */
+/* INT_FL0_MAMI Position */
+#define MXC_F_I2C_INT_FL0_MAMI_POS 16
 /* INT_FL0_MAMI Mask */
-#define MXC_F_I2C_INT_FL0_MAMI_MASK \
-	((uint32_t)(0xFUL << MXC_F_I2C_INT_FL0_MAMI_POS))
+#define MXC_F_I2C_INT_FL0_MAMI_MASK (0xFUL << MXC_F_I2C_INT_FL0_MAMI_POS)
 /* INT_FL0_MAMI Address Match 0 */
-#define MXC_F_I2C_INT_FL0_MAMI_MATCH_0 \
-	((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_MAMI_POS))
+#define MXC_F_I2C_INT_FL0_MAMI_MATCH_0 (0x1UL << MXC_F_I2C_INT_FL0_MAMI_POS)
 /* INT_FL0_MAMI Address Match 1 */
-#define MXC_F_I2C_INT_FL0_MAMI_MATCH_1 \
-	((uint32_t)(0x2UL << MXC_F_I2C_INT_FL0_MAMI_POS))
+#define MXC_F_I2C_INT_FL0_MAMI_MATCH_1 (0x2UL << MXC_F_I2C_INT_FL0_MAMI_POS)
 /* INT_FL0_MAMI Address Match 2 */
-#define MXC_F_I2C_INT_FL0_MAMI_MATCH_2 \
-	((uint32_t)(0x4UL << MXC_F_I2C_INT_FL0_MAMI_POS))
+#define MXC_F_I2C_INT_FL0_MAMI_MATCH_2 (0x4UL << MXC_F_I2C_INT_FL0_MAMI_POS)
 /* INT_FL0_MAMI Address Match 3 */
-#define MXC_F_I2C_INT_FL0_MAMI_MATCH_3 \
-	((uint32_t)(0x8UL << MXC_F_I2C_INT_FL0_MAMI_POS)) 
+#define MXC_F_I2C_INT_FL0_MAMI_MATCH_3 (0x8UL << MXC_F_I2C_INT_FL0_MAMI_POS)
 
 /**
  * Interrupt Enable Register.
  */
-#define MXC_F_I2C_INT_EN0_DONE_POS 0 /**< INT_EN0_DONE Position */
-#define MXC_F_I2C_INT_EN0_DONE \
-	((uint32_t)(0x1UL      \
-		    << MXC_F_I2C_INT_EN0_DONE_POS)) /**< INT_EN0_DONE Mask */
-#define MXC_V_I2C_INT_EN0_DONE_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_DONE_DIS Value */
-#define MXC_S_I2C_INT_EN0_DONE_DIS  \
-	(MXC_V_I2C_INT_EN0_DONE_DIS \
-	 << MXC_F_I2C_INT_EN0_DONE_POS) /**< INT_EN0_DONE_DIS Setting */
-#define MXC_V_I2C_INT_EN0_DONE_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_DONE_EN Value */
-#define MXC_S_I2C_INT_EN0_DONE_EN  \
-	(MXC_V_I2C_INT_EN0_DONE_EN \
-	 << MXC_F_I2C_INT_EN0_DONE_POS) /**< INT_EN0_DONE_EN Setting */
-
-#define MXC_F_I2C_INT_EN0_RX_MODE_POS 1 /**< INT_EN0_RX_MODE Position */
-#define MXC_F_I2C_INT_EN0_RX_MODE \
-	((uint32_t)(0x1UL         \
-		    << MXC_F_I2C_INT_EN0_RX_MODE_POS)) /**< INT_EN0_RX_MODE  \
-							    Mask */
-#define MXC_V_I2C_INT_EN0_RX_MODE_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_RX_MODE_DIS Value */
-#define MXC_S_I2C_INT_EN0_RX_MODE_DIS  \
-	(MXC_V_I2C_INT_EN0_RX_MODE_DIS \
-	 << MXC_F_I2C_INT_EN0_RX_MODE_POS) /**< INT_EN0_RX_MODE_DIS Setting */
-#define MXC_V_I2C_INT_EN0_RX_MODE_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_RX_MODE_EN Value */
-#define MXC_S_I2C_INT_EN0_RX_MODE_EN  \
-	(MXC_V_I2C_INT_EN0_RX_MODE_EN \
-	 << MXC_F_I2C_INT_EN0_RX_MODE_POS) /**< INT_EN0_RX_MODE_EN Setting */
-
-#define MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS \
-	2 /**< INT_EN0_GEN_CTRL_ADDR Position */
+#define MXC_F_I2C_INT_EN0_DONE_POS 0 /* INT_EN0_DONE Position */
+/* INT_EN0_DONE Mask */
+#define MXC_F_I2C_INT_EN0_DONE (0x1UL << MXC_F_I2C_INT_EN0_DONE_POS)
+/* INT_EN0_DONE_DIS Value */
+#define MXC_V_I2C_INT_EN0_DONE_DIS 0x0UL
+/* INT_EN0_DONE_DIS Setting */
+#define MXC_S_I2C_INT_EN0_DONE_DIS \
+	(MXC_V_I2C_INT_EN0_DONE_DIS << MXC_F_I2C_INT_EN0_DONE_POS)
+/* INT_EN0_DONE_EN Value */
+#define MXC_V_I2C_INT_EN0_DONE_EN 0x1UL
+/* INT_EN0_DONE_EN Setting */
+#define MXC_S_I2C_INT_EN0_DONE_EN \
+	(MXC_V_I2C_INT_EN0_DONE_EN << MXC_F_I2C_INT_EN0_DONE_POS)
+
+/* INT_EN0_RX_MODE Position */
+#define MXC_F_I2C_INT_EN0_RX_MODE_POS 1
+/* INT_EN0_RX_MODE Mask */
+#define MXC_F_I2C_INT_EN0_RX_MODE (0x1UL << MXC_F_I2C_INT_EN0_RX_MODE_POS)
+/* INT_EN0_RX_MODE_DIS Value */
+#define MXC_V_I2C_INT_EN0_RX_MODE_DIS 0x0UL
+/* INT_EN0_RX_MODE_DIS Setting */
+#define MXC_S_I2C_INT_EN0_RX_MODE_DIS \
+	(MXC_V_I2C_INT_EN0_RX_MODE_DIS << MXC_F_I2C_INT_EN0_RX_MODE_POS)
+/* INT_EN0_RX_MODE_EN Value */
+#define MXC_V_I2C_INT_EN0_RX_MODE_EN 0x1UL
+/* INT_EN0_RX_MODE_EN Setting */
+#define MXC_S_I2C_INT_EN0_RX_MODE_EN \
+	(MXC_V_I2C_INT_EN0_RX_MODE_EN << MXC_F_I2C_INT_EN0_RX_MODE_POS)
+
+/* INT_EN0_GEN_CTRL_ADDR Position */
+#define MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS 2
+/*  INT_EN0_GEN_CTRL_ADDR Mask */
 #define MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR \
-	((uint32_t)(                    \
-		0x1UL                   \
-		<< MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS)) /**<                     \
-							    INT_EN0_GEN_CTRL_ADDR \
-							    Mask */
-#define MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_GEN_CTRL_ADDR_DIS Value */
+	(0x1UL << MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS)
+/* INT_EN0_GEN_CTRL_ADDR_DIS Value */
+#define MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_DIS 0x0UL
+/* INT_EN0_GEN_CTRL_ADDR_DIS Setting */
 #define MXC_S_I2C_INT_EN0_GEN_CTRL_ADDR_DIS  \
 	(MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_DIS \
-	 << MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS) /**<                          \
-						    INT_EN0_GEN_CTRL_ADDR_DIS  \
-						    Setting */
-#define MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_GEN_CTRL_ADDR_EN Value */
+	 << MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS)
+/* INT_EN0_GEN_CTRL_ADDR_EN Value */
+#define MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_EN 0x1UL
+/* INT_EN0_GEN_CTRL_ADDR_EN Setting */
 #define MXC_S_I2C_INT_EN0_GEN_CTRL_ADDR_EN  \
 	(MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_EN \
-	 << MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS) /**< INT_EN0_GEN_CTRL_ADDR_EN \
-						    Setting */
-
-#define MXC_F_I2C_INT_EN0_ADDR_MATCH_POS 3 /**< INT_EN0_ADDR_MATCH Position */
-#define MXC_F_I2C_INT_EN0_ADDR_MATCH \
-	((uint32_t)(                 \
-		0x1UL                \
-		<< MXC_F_I2C_INT_EN0_ADDR_MATCH_POS)) /**< INT_EN0_ADDR_MATCH  \
-							 Mask */
-#define MXC_V_I2C_INT_EN0_ADDR_MATCH_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_ADDR_MATCH_DIS Value */
-#define MXC_S_I2C_INT_EN0_ADDR_MATCH_DIS  \
-	(MXC_V_I2C_INT_EN0_ADDR_MATCH_DIS \
-	 << MXC_F_I2C_INT_EN0_ADDR_MATCH_POS) /**< INT_EN0_ADDR_MATCH_DIS      \
-						 Setting */
-#define MXC_V_I2C_INT_EN0_ADDR_MATCH_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_ADDR_MATCH_EN Value */
-#define MXC_S_I2C_INT_EN0_ADDR_MATCH_EN  \
-	(MXC_V_I2C_INT_EN0_ADDR_MATCH_EN \
-	 << MXC_F_I2C_INT_EN0_ADDR_MATCH_POS) /**< INT_EN0_ADDR_MATCH_EN       \
-						 Setting */
-
-#define MXC_F_I2C_INT_EN0_RX_THRESH_POS 4 /**< INT_EN0_RX_THRESH Position */
-#define MXC_F_I2C_INT_EN0_RX_THRESH \
-	((uint32_t)(                \
-		0x1UL               \
-		<< MXC_F_I2C_INT_EN0_RX_THRESH_POS)) /**< INT_EN0_RX_THRESH    \
-							Mask */
-#define MXC_V_I2C_INT_EN0_RX_THRESH_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_RX_THRESH_DIS Value */
-#define MXC_S_I2C_INT_EN0_RX_THRESH_DIS  \
-	(MXC_V_I2C_INT_EN0_RX_THRESH_DIS \
-	 << MXC_F_I2C_INT_EN0_RX_THRESH_POS) /**< INT_EN0_RX_THRESH_DIS        \
-						Setting */
-#define MXC_V_I2C_INT_EN0_RX_THRESH_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_RX_THRESH_EN Value */
-#define MXC_S_I2C_INT_EN0_RX_THRESH_EN  \
-	(MXC_V_I2C_INT_EN0_RX_THRESH_EN \
-	 << MXC_F_I2C_INT_EN0_RX_THRESH_POS) /**< INT_EN0_RX_THRESH_EN Setting \
-					      */
-
-#define MXC_F_I2C_INT_EN0_TX_THRESH_POS 5 /**< INT_EN0_TX_THRESH Position */
-#define MXC_F_I2C_INT_EN0_TX_THRESH \
-	((uint32_t)(                \
-		0x1UL               \
-		<< MXC_F_I2C_INT_EN0_TX_THRESH_POS)) /**< INT_EN0_TX_THRESH    \
-							Mask */
-#define MXC_V_I2C_INT_EN0_TX_THRESH_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_TX_THRESH_DIS Value */
-#define MXC_S_I2C_INT_EN0_TX_THRESH_DIS  \
-	(MXC_V_I2C_INT_EN0_TX_THRESH_DIS \
-	 << MXC_F_I2C_INT_EN0_TX_THRESH_POS) /**< INT_EN0_TX_THRESH_DIS        \
-						Setting */
-#define MXC_V_I2C_INT_EN0_TX_THRESH_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_TX_THRESH_EN Value */
-#define MXC_S_I2C_INT_EN0_TX_THRESH_EN  \
-	(MXC_V_I2C_INT_EN0_TX_THRESH_EN \
-	 << MXC_F_I2C_INT_EN0_TX_THRESH_POS) /**< INT_EN0_TX_THRESH_EN Setting \
-					      */
-
-#define MXC_F_I2C_INT_EN0_STOP_POS 6 /**< INT_EN0_STOP Position */
-#define MXC_F_I2C_INT_EN0_STOP \
-	((uint32_t)(0x1UL      \
-		    << MXC_F_I2C_INT_EN0_STOP_POS)) /**< INT_EN0_STOP Mask */
-#define MXC_V_I2C_INT_EN0_STOP_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_STOP_DIS Value */
-#define MXC_S_I2C_INT_EN0_STOP_DIS  \
-	(MXC_V_I2C_INT_EN0_STOP_DIS \
-	 << MXC_F_I2C_INT_EN0_STOP_POS) /**< INT_EN0_STOP_DIS Setting */
-#define MXC_V_I2C_INT_EN0_STOP_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_STOP_EN Value */
-#define MXC_S_I2C_INT_EN0_STOP_EN  \
-	(MXC_V_I2C_INT_EN0_STOP_EN \
-	 << MXC_F_I2C_INT_EN0_STOP_POS) /**< INT_EN0_STOP_EN Setting */
-
-#define MXC_F_I2C_INT_EN0_ADDR_ACK_POS 7 /**< INT_EN0_ADDR_ACK Position */
-#define MXC_F_I2C_INT_EN0_ADDR_ACK \
-	((uint32_t)(               \
-		0x1UL              \
-		<< MXC_F_I2C_INT_EN0_ADDR_ACK_POS)) /**< INT_EN0_ADDR_ACK  \
-							   Mask */
-#define MXC_V_I2C_INT_EN0_ADDR_ACK_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_ADDR_ACK_DIS Value */
-#define MXC_S_I2C_INT_EN0_ADDR_ACK_DIS  \
-	(MXC_V_I2C_INT_EN0_ADDR_ACK_DIS \
-	 << MXC_F_I2C_INT_EN0_ADDR_ACK_POS) /**< INT_EN0_ADDR_ACK_DIS Setting  \
-					     */
-#define MXC_V_I2C_INT_EN0_ADDR_ACK_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_ADDR_ACK_EN Value */
-#define MXC_S_I2C_INT_EN0_ADDR_ACK_EN  \
-	(MXC_V_I2C_INT_EN0_ADDR_ACK_EN \
-	 << MXC_F_I2C_INT_EN0_ADDR_ACK_POS) /**< INT_EN0_ADDR_ACK_EN Setting   \
-					     */
-
-#define MXC_F_I2C_INT_EN0_ARB_ER_POS 8 /**< INT_EN0_ARB_ER Position */
-#define MXC_F_I2C_INT_EN0_ARB_ER \
-	((uint32_t)(             \
-		0x1UL            \
-		<< MXC_F_I2C_INT_EN0_ARB_ER_POS)) /**< INT_EN0_ARB_ER Mask */
-#define MXC_V_I2C_INT_EN0_ARB_ER_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_ARB_ER_DIS Value */
-#define MXC_S_I2C_INT_EN0_ARB_ER_DIS  \
-	(MXC_V_I2C_INT_EN0_ARB_ER_DIS \
-	 << MXC_F_I2C_INT_EN0_ARB_ER_POS) /**< INT_EN0_ARB_ER_DIS Setting */
-#define MXC_V_I2C_INT_EN0_ARB_ER_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_ARB_ER_EN Value */
-#define MXC_S_I2C_INT_EN0_ARB_ER_EN  \
-	(MXC_V_I2C_INT_EN0_ARB_ER_EN \
-	 << MXC_F_I2C_INT_EN0_ARB_ER_POS) /**< INT_EN0_ARB_ER_EN Setting */
-
-#define MXC_F_I2C_INT_EN0_TO_ER_POS 9 /**< INT_EN0_TO_ER Position */
-#define MXC_F_I2C_INT_EN0_TO_ER \
-	((uint32_t)(            \
-		0x1UL           \
-		<< MXC_F_I2C_INT_EN0_TO_ER_POS)) /**< INT_EN0_TO_ER Mask */
-#define MXC_V_I2C_INT_EN0_TO_ER_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_TO_ER_DIS Value */
-#define MXC_S_I2C_INT_EN0_TO_ER_DIS  \
-	(MXC_V_I2C_INT_EN0_TO_ER_DIS \
-	 << MXC_F_I2C_INT_EN0_TO_ER_POS) /**< INT_EN0_TO_ER_DIS Setting */
-#define MXC_V_I2C_INT_EN0_TO_ER_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_TO_ER_EN Value */
-#define MXC_S_I2C_INT_EN0_TO_ER_EN  \
-	(MXC_V_I2C_INT_EN0_TO_ER_EN \
-	 << MXC_F_I2C_INT_EN0_TO_ER_POS) /**< INT_EN0_TO_ER_EN Setting */
-
-#define MXC_F_I2C_INT_EN0_ADDR_ER_POS 10 /**< INT_EN0_ADDR_ER Position */
-#define MXC_F_I2C_INT_EN0_ADDR_ER \
-	((uint32_t)(0x1UL         \
-		    << MXC_F_I2C_INT_EN0_ADDR_ER_POS)) /**< INT_EN0_ADDR_ER  \
-							    Mask */
-#define MXC_V_I2C_INT_EN0_ADDR_ER_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_ADDR_ER_DIS Value */
-#define MXC_S_I2C_INT_EN0_ADDR_ER_DIS  \
-	(MXC_V_I2C_INT_EN0_ADDR_ER_DIS \
-	 << MXC_F_I2C_INT_EN0_ADDR_ER_POS) /**< INT_EN0_ADDR_ER_DIS Setting */
-#define MXC_V_I2C_INT_EN0_ADDR_ER_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_ADDR_ER_EN Value */
-#define MXC_S_I2C_INT_EN0_ADDR_ER_EN  \
-	(MXC_V_I2C_INT_EN0_ADDR_ER_EN \
-	 << MXC_F_I2C_INT_EN0_ADDR_ER_POS) /**< INT_EN0_ADDR_ER_EN Setting */
-
-#define MXC_F_I2C_INT_EN0_DATA_ER_POS 11 /**< INT_EN0_DATA_ER Position */
-#define MXC_F_I2C_INT_EN0_DATA_ER \
-	((uint32_t)(0x1UL         \
-		    << MXC_F_I2C_INT_EN0_DATA_ER_POS)) /**< INT_EN0_DATA_ER  \
-							    Mask */
-#define MXC_V_I2C_INT_EN0_DATA_ER_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_DATA_ER_DIS Value */
-#define MXC_S_I2C_INT_EN0_DATA_ER_DIS  \
-	(MXC_V_I2C_INT_EN0_DATA_ER_DIS \
-	 << MXC_F_I2C_INT_EN0_DATA_ER_POS) /**< INT_EN0_DATA_ER_DIS Setting */
-#define MXC_V_I2C_INT_EN0_DATA_ER_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_DATA_ER_EN Value */
-#define MXC_S_I2C_INT_EN0_DATA_ER_EN  \
-	(MXC_V_I2C_INT_EN0_DATA_ER_EN \
-	 << MXC_F_I2C_INT_EN0_DATA_ER_POS) /**< INT_EN0_DATA_ER_EN Setting */
-
-#define MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS \
-	12 /**< INT_EN0_DO_NOT_RESP_ER Position */
+	 << MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS)
+
+/* INT_EN0_ADDR_MATCH Position */
+#define MXC_F_I2C_INT_EN0_ADDR_MATCH_POS 3
+/* INT_EN0_ADDR_MATCH Mask */
+#define MXC_F_I2C_INT_EN0_ADDR_MATCH (0x1UL << MXC_F_I2C_INT_EN0_ADDR_MATCH_POS)
+/* INT_EN0_ADDR_MATCH_DIS Value */
+#define MXC_V_I2C_INT_EN0_ADDR_MATCH_DIS 0x0UL
+/* INT_EN0_ADDR_MATCH_DIS Setting */
+#define MXC_S_I2C_INT_EN0_ADDR_MATCH_DIS \
+	(MXC_V_I2C_INT_EN0_ADDR_MATCH_DIS << MXC_F_I2C_INT_EN0_ADDR_MATCH_POS)
+/* INT_EN0_ADDR_MATCH_EN Value */
+#define MXC_V_I2C_INT_EN0_ADDR_MATCH_EN 0x1UL
+/* INT_EN0_ADDR_MATCH_EN Setting */
+#define MXC_S_I2C_INT_EN0_ADDR_MATCH_EN \
+	(MXC_V_I2C_INT_EN0_ADDR_MATCH_EN << MXC_F_I2C_INT_EN0_ADDR_MATCH_POS)
+
+/* INT_EN0_RX_THRESH Position */
+#define MXC_F_I2C_INT_EN0_RX_THRESH_POS 4
+/* INT_EN0_RX_THRESH Mask */
+#define MXC_F_I2C_INT_EN0_RX_THRESH (0x1UL << MXC_F_I2C_INT_EN0_RX_THRESH_POS)
+/* INT_EN0_RX_THRESH_DIS Value */
+#define MXC_V_I2C_INT_EN0_RX_THRESH_DIS 0x0UL
+/* INT_EN0_RX_THRESH_DIS Setting */
+#define MXC_S_I2C_INT_EN0_RX_THRESH_DIS \
+	(MXC_V_I2C_INT_EN0_RX_THRESH_DIS << MXC_F_I2C_INT_EN0_RX_THRESH_POS)
+/* INT_EN0_RX_THRESH_EN Value */
+#define MXC_V_I2C_INT_EN0_RX_THRESH_EN 0x1UL
+/* INT_EN0_RX_THRESH_EN Setting */
+#define MXC_S_I2C_INT_EN0_RX_THRESH_EN \
+	(MXC_V_I2C_INT_EN0_RX_THRESH_EN << MXC_F_I2C_INT_EN0_RX_THRESH_POS)
+
+/* INT_EN0_TX_THRESH Position */
+#define MXC_F_I2C_INT_EN0_TX_THRESH_POS 5
+/* INT_EN0_TX_THRESH Mask */
+#define MXC_F_I2C_INT_EN0_TX_THRESH (0x1UL << MXC_F_I2C_INT_EN0_TX_THRESH_POS)
+/* INT_EN0_TX_THRESH_DIS Value */
+#define MXC_V_I2C_INT_EN0_TX_THRESH_DIS 0x0UL
+/* INT_EN0_TX_THRESH_DIS Setting */
+#define MXC_S_I2C_INT_EN0_TX_THRESH_DIS \
+	(MXC_V_I2C_INT_EN0_TX_THRESH_DIS << MXC_F_I2C_INT_EN0_TX_THRESH_POS)
+/* INT_EN0_TX_THRESH_EN Value */
+#define MXC_V_I2C_INT_EN0_TX_THRESH_EN 0x1UL
+/* INT_EN0_TX_THRESH_EN Setting */
+#define MXC_S_I2C_INT_EN0_TX_THRESH_EN \
+	(MXC_V_I2C_INT_EN0_TX_THRESH_EN << MXC_F_I2C_INT_EN0_TX_THRESH_POS)
+
+/* INT_EN0_STOP Position */
+#define MXC_F_I2C_INT_EN0_STOP_POS 6
+/* INT_EN0_STOP Mask */
+#define MXC_F_I2C_INT_EN0_STOP (0x1UL << MXC_F_I2C_INT_EN0_STOP_POS)
+/* INT_EN0_STOP_DIS Value */
+#define MXC_V_I2C_INT_EN0_STOP_DIS 0x0UL
+/* INT_EN0_STOP_DIS Setting */
+#define MXC_S_I2C_INT_EN0_STOP_DIS \
+	(MXC_V_I2C_INT_EN0_STOP_DIS << MXC_F_I2C_INT_EN0_STOP_POS)
+/* INT_EN0_STOP_EN Value */
+#define MXC_V_I2C_INT_EN0_STOP_EN 0x1UL
+/* INT_EN0_STOP_EN Setting */
+#define MXC_S_I2C_INT_EN0_STOP_EN \
+	(MXC_V_I2C_INT_EN0_STOP_EN << MXC_F_I2C_INT_EN0_STOP_POS)
+
+/* INT_EN0_ADDR_ACK Position */
+#define MXC_F_I2C_INT_EN0_ADDR_ACK_POS 7
+/* INT_EN0_ADDR_ACK Mask */
+#define MXC_F_I2C_INT_EN0_ADDR_ACK (0x1UL << MXC_F_I2C_INT_EN0_ADDR_ACK_POS)
+/* INT_EN0_ADDR_ACK_DIS Value */
+#define MXC_V_I2C_INT_EN0_ADDR_ACK_DIS 0x0UL
+/* INT_EN0_ADDR_ACK_DIS Setting */
+#define MXC_S_I2C_INT_EN0_ADDR_ACK_DIS \
+	(MXC_V_I2C_INT_EN0_ADDR_ACK_DIS << MXC_F_I2C_INT_EN0_ADDR_ACK_POS)
+/* INT_EN0_ADDR_ACK_EN Value */
+#define MXC_V_I2C_INT_EN0_ADDR_ACK_EN 0x1UL
+/* INT_EN0_ADDR_ACK_EN Setting */
+#define MXC_S_I2C_INT_EN0_ADDR_ACK_EN \
+	(MXC_V_I2C_INT_EN0_ADDR_ACK_EN << MXC_F_I2C_INT_EN0_ADDR_ACK_POS)
+
+/* INT_EN0_ARB_ER Position */
+#define MXC_F_I2C_INT_EN0_ARB_ER_POS 8
+/* INT_EN0_ARB_ER Mask */
+#define MXC_F_I2C_INT_EN0_ARB_ER (0x1UL << MXC_F_I2C_INT_EN0_ARB_ER_POS)
+/* INT_EN0_ARB_ER_DIS Value */
+#define MXC_V_I2C_INT_EN0_ARB_ER_DIS 0x0UL
+/* INT_EN0_ARB_ER_DIS Setting */
+#define MXC_S_I2C_INT_EN0_ARB_ER_DIS \
+	(MXC_V_I2C_INT_EN0_ARB_ER_DIS << MXC_F_I2C_INT_EN0_ARB_ER_POS)
+/* INT_EN0_ARB_ER_EN Value */
+#define MXC_V_I2C_INT_EN0_ARB_ER_EN 0x1UL
+/* INT_EN0_ARB_ER_EN Setting */
+#define MXC_S_I2C_INT_EN0_ARB_ER_EN \
+	(MXC_V_I2C_INT_EN0_ARB_ER_EN << MXC_F_I2C_INT_EN0_ARB_ER_POS)
+
+/* INT_EN0_TO_ER Position */
+#define MXC_F_I2C_INT_EN0_TO_ER_POS 9
+/* INT_EN0_TO_ER Mask */
+#define MXC_F_I2C_INT_EN0_TO_ER (0x1UL << MXC_F_I2C_INT_EN0_TO_ER_POS)
+/* INT_EN0_TO_ER_DIS Value */
+#define MXC_V_I2C_INT_EN0_TO_ER_DIS 0x0UL
+/* INT_EN0_TO_ER_DIS Setting */
+#define MXC_S_I2C_INT_EN0_TO_ER_DIS \
+	(MXC_V_I2C_INT_EN0_TO_ER_DIS << MXC_F_I2C_INT_EN0_TO_ER_POS)
+/* INT_EN0_TO_ER_EN Value */
+#define MXC_V_I2C_INT_EN0_TO_ER_EN 0x1UL
+/* INT_EN0_TO_ER_EN Setting */
+#define MXC_S_I2C_INT_EN0_TO_ER_EN \
+	(MXC_V_I2C_INT_EN0_TO_ER_EN << MXC_F_I2C_INT_EN0_TO_ER_POS)
+
+/* INT_EN0_ADDR_ER Position */
+#define MXC_F_I2C_INT_EN0_ADDR_ER_POS 10
+/* INT_EN0_ADDR_ER Mask */
+#define MXC_F_I2C_INT_EN0_ADDR_ER (0x1UL << MXC_F_I2C_INT_EN0_ADDR_ER_POS)
+/* INT_EN0_ADDR_ER_DIS Value */
+#define MXC_V_I2C_INT_EN0_ADDR_ER_DIS 0x0UL
+/* INT_EN0_ADDR_ER_DIS Setting */
+#define MXC_S_I2C_INT_EN0_ADDR_ER_DIS \
+	(MXC_V_I2C_INT_EN0_ADDR_ER_DIS << MXC_F_I2C_INT_EN0_ADDR_ER_POS)
+/* INT_EN0_ADDR_ER_EN Value */
+#define MXC_V_I2C_INT_EN0_ADDR_ER_EN 0x1UL
+/* INT_EN0_ADDR_ER_EN Setting */
+#define MXC_S_I2C_INT_EN0_ADDR_ER_EN \
+	(MXC_V_I2C_INT_EN0_ADDR_ER_EN << MXC_F_I2C_INT_EN0_ADDR_ER_POS)
+
+/* INT_EN0_DATA_ER Position */
+#define MXC_F_I2C_INT_EN0_DATA_ER_POS 11
+/* INT_EN0_DATA_ER Mask */
+#define MXC_F_I2C_INT_EN0_DATA_ER (0x1UL << MXC_F_I2C_INT_EN0_DATA_ER_POS)
+/* INT_EN0_DATA_ER_DIS Value */
+#define MXC_V_I2C_INT_EN0_DATA_ER_DIS 0x0UL
+/* INT_EN0_DATA_ER_DIS Setting */
+#define MXC_S_I2C_INT_EN0_DATA_ER_DIS \
+	(MXC_V_I2C_INT_EN0_DATA_ER_DIS << MXC_F_I2C_INT_EN0_DATA_ER_POS)
+/* INT_EN0_DATA_ER_EN Value */
+#define MXC_V_I2C_INT_EN0_DATA_ER_EN 0x1UL
+/* INT_EN0_DATA_ER_EN Setting */
+#define MXC_S_I2C_INT_EN0_DATA_ER_EN \
+	(MXC_V_I2C_INT_EN0_DATA_ER_EN << MXC_F_I2C_INT_EN0_DATA_ER_POS)
+
+/* INT_EN0_DO_NOT_RESP_ER Position */
+#define MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS 12
+/* INT_EN0_DO_NOT_RESP_ER Mask */
 #define MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER \
-	((uint32_t)(                     \
-		0x1UL                    \
-		<< MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS)) /**<                      \
-							     INT_EN0_DO_NOT_RESP_ER \
-							     Mask */
-#define MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_DO_NOT_RESP_ER_DIS Value */
+	(0x1UL << MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS)
+/* INT_EN0_DO_NOT_RESP_ER_DIS Value */
+#define MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_DIS 0x0UL
+/* INT_EN0_DO_NOT_RESP_ER_DIS Setting */
 #define MXC_S_I2C_INT_EN0_DO_NOT_RESP_ER_DIS  \
 	(MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_DIS \
-	 << MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS) /**<                          \
-						     INT_EN0_DO_NOT_RESP_ER_DIS \
-						     Setting */
-#define MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_DO_NOT_RESP_ER_EN Value */
+	 << MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS)
+/* INT_EN0_DO_NOT_RESP_ER_EN Value */
+#define MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_EN 0x1UL
+/* INT_EN0_DO_NOT_RESP_ER_EN Setting */
 #define MXC_S_I2C_INT_EN0_DO_NOT_RESP_ER_EN  \
 	(MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_EN \
-	 << MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS) /**<                         \
-						     INT_EN0_DO_NOT_RESP_ER_EN \
-						     Setting */
-
-#define MXC_F_I2C_INT_EN0_START_ER_POS 13 /**< INT_EN0_START_ER Position */
-#define MXC_F_I2C_INT_EN0_START_ER \
-	((uint32_t)(               \
-		0x1UL              \
-		<< MXC_F_I2C_INT_EN0_START_ER_POS)) /**< INT_EN0_START_ER  \
-							   Mask */
-#define MXC_V_I2C_INT_EN0_START_ER_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_START_ER_DIS Value */
-#define MXC_S_I2C_INT_EN0_START_ER_DIS  \
-	(MXC_V_I2C_INT_EN0_START_ER_DIS \
-	 << MXC_F_I2C_INT_EN0_START_ER_POS) /**< INT_EN0_START_ER_DIS Setting  \
-					     */
-#define MXC_V_I2C_INT_EN0_START_ER_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_START_ER_EN Value */
-#define MXC_S_I2C_INT_EN0_START_ER_EN  \
-	(MXC_V_I2C_INT_EN0_START_ER_EN \
-	 << MXC_F_I2C_INT_EN0_START_ER_POS) /**< INT_EN0_START_ER_EN Setting   \
-					     */
-
-#define MXC_F_I2C_INT_EN0_STOP_ER_POS 14 /**< INT_EN0_STOP_ER Position */
-#define MXC_F_I2C_INT_EN0_STOP_ER \
-	((uint32_t)(0x1UL         \
-		    << MXC_F_I2C_INT_EN0_STOP_ER_POS)) /**< INT_EN0_STOP_ER  \
-							    Mask */
-#define MXC_V_I2C_INT_EN0_STOP_ER_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_STOP_ER_DIS Value */
-#define MXC_S_I2C_INT_EN0_STOP_ER_DIS  \
-	(MXC_V_I2C_INT_EN0_STOP_ER_DIS \
-	 << MXC_F_I2C_INT_EN0_STOP_ER_POS) /**< INT_EN0_STOP_ER_DIS Setting */
-#define MXC_V_I2C_INT_EN0_STOP_ER_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_STOP_ER_EN Value */
-#define MXC_S_I2C_INT_EN0_STOP_ER_EN  \
-	(MXC_V_I2C_INT_EN0_STOP_ER_EN \
-	 << MXC_F_I2C_INT_EN0_STOP_ER_POS) /**< INT_EN0_STOP_ER_EN Setting */
-
-#define MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS \
-	15 /**< INT_EN0_TX_LOCK_OUT Position */
+	 << MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS)
+
+/* INT_EN0_START_ER Position */
+#define MXC_F_I2C_INT_EN0_START_ER_POS 13
+/* INT_EN0_START_ER Mask */
+#define MXC_F_I2C_INT_EN0_START_ER (0x1UL << MXC_F_I2C_INT_EN0_START_ER_POS)
+/* INT_EN0_START_ER_DIS Value */
+#define MXC_V_I2C_INT_EN0_START_ER_DIS 0x0UL
+/* INT_EN0_START_ER_DIS Setting */
+#define MXC_S_I2C_INT_EN0_START_ER_DIS \
+	(MXC_V_I2C_INT_EN0_START_ER_DIS << MXC_F_I2C_INT_EN0_START_ER_POS)
+/* INT_EN0_START_ER_EN Value */
+#define MXC_V_I2C_INT_EN0_START_ER_EN 0x1UL
+/* INT_EN0_START_ER_EN Setting */
+#define MXC_S_I2C_INT_EN0_START_ER_EN \
+	(MXC_V_I2C_INT_EN0_START_ER_EN << MXC_F_I2C_INT_EN0_START_ER_POS)
+
+/* INT_EN0_STOP_ER Position */
+#define MXC_F_I2C_INT_EN0_STOP_ER_POS 14
+/* INT_EN0_STOP_ER Mask */
+#define MXC_F_I2C_INT_EN0_STOP_ER (0x1UL << MXC_F_I2C_INT_EN0_STOP_ER_POS)
+/* INT_EN0_STOP_ER_DIS Value */
+#define MXC_V_I2C_INT_EN0_STOP_ER_DIS 0x0UL
+/* INT_EN0_STOP_ER_DIS Setting */
+#define MXC_S_I2C_INT_EN0_STOP_ER_DIS \
+	(MXC_V_I2C_INT_EN0_STOP_ER_DIS << MXC_F_I2C_INT_EN0_STOP_ER_POS)
+/* INT_EN0_STOP_ER_EN Value */
+#define MXC_V_I2C_INT_EN0_STOP_ER_EN 0x1UL
+/* INT_EN0_STOP_ER_EN Setting */
+#define MXC_S_I2C_INT_EN0_STOP_ER_EN \
+	(MXC_V_I2C_INT_EN0_STOP_ER_EN << MXC_F_I2C_INT_EN0_STOP_ER_POS)
+
+/* INT_EN0_TX_LOCK_OUT Position */
+#define MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS 15
+/* INT_EN0_TX_LOCK_OUT Mask */
 #define MXC_F_I2C_INT_EN0_TX_LOCK_OUT \
-	((uint32_t)(                  \
-		0x1UL                 \
-		<< MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS)) /**<                    \
-							  INT_EN0_TX_LOCK_OUT  \
-							  Mask */
-#define MXC_V_I2C_INT_EN0_TX_LOCK_OUT_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_TX_LOCK_OUT_DIS Value */
-#define MXC_S_I2C_INT_EN0_TX_LOCK_OUT_DIS  \
-	(MXC_V_I2C_INT_EN0_TX_LOCK_OUT_DIS \
-	 << MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS) /**< INT_EN0_TX_LOCK_OUT_DIS    \
-						  Setting */
-#define MXC_V_I2C_INT_EN0_TX_LOCK_OUT_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_TX_LOCK_OUT_EN Value */
-#define MXC_S_I2C_INT_EN0_TX_LOCK_OUT_EN  \
-	(MXC_V_I2C_INT_EN0_TX_LOCK_OUT_EN \
-	 << MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS) /**< INT_EN0_TX_LOCK_OUT_EN     \
-						  Setting */
+	(0x1UL << MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS)
+/* INT_EN0_TX_LOCK_OUT_DIS Value */
+#define MXC_V_I2C_INT_EN0_TX_LOCK_OUT_DIS 0x0UL
+/* INT_EN0_TX_LOCK_OUT_DIS Setting */
+#define MXC_S_I2C_INT_EN0_TX_LOCK_OUT_DIS \
+	(MXC_V_I2C_INT_EN0_TX_LOCK_OUT_DIS << MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS)
+/* INT_EN0_TX_LOCK_OUT_EN Value */
+#define MXC_V_I2C_INT_EN0_TX_LOCK_OUT_EN 0x1UL
+/* INT_EN0_TX_LOCK_OUT_EN Setting */
+#define MXC_S_I2C_INT_EN0_TX_LOCK_OUT_EN \
+	(MXC_V_I2C_INT_EN0_TX_LOCK_OUT_EN << MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS)
 
 /**
  * Interrupt Status Register 1.
  */
-#define MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS \
-	0 /**< INT_FL1_RX_OVERFLOW Position                                    \
-	   */
+/* INT_FL1_RX_OVERFLOW Position */
+#define MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS 0
+/* INT_FL1_RX_OVERFLOW Mask */
 #define MXC_F_I2C_INT_FL1_RX_OVERFLOW \
-	((uint32_t)(                  \
-		0x1UL                 \
-		<< MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS)) /**<                    \
-							  INT_FL1_RX_OVERFLOW  \
-							  Mask */
-#define MXC_V_I2C_INT_FL1_RX_OVERFLOW_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL1_RX_OVERFLOW_INACTIVE Value */
+	(0x1UL << MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS)
+/* INT_FL1_RX_OVERFLOW_INACTIVE Value */
+#define MXC_V_I2C_INT_FL1_RX_OVERFLOW_INACTIVE 0x0UL
+/* INT_FL1_RX_OVERFLOW_INACTIVE Setting */
 #define MXC_S_I2C_INT_FL1_RX_OVERFLOW_INACTIVE  \
 	(MXC_V_I2C_INT_FL1_RX_OVERFLOW_INACTIVE \
-	 << MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS) /**<                            \
-						  INT_FL1_RX_OVERFLOW_INACTIVE \
-						  Setting */
-#define MXC_V_I2C_INT_FL1_RX_OVERFLOW_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL1_RX_OVERFLOW_PENDING Value */
+	 << MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS)
+/* INT_FL1_RX_OVERFLOW_PENDING Value */
+#define MXC_V_I2C_INT_FL1_RX_OVERFLOW_PENDING 0x1UL
+/* INT_FL1_RX_OVERFLOW_PENDING Setting */
 #define MXC_S_I2C_INT_FL1_RX_OVERFLOW_PENDING  \
 	(MXC_V_I2C_INT_FL1_RX_OVERFLOW_PENDING \
-	 << MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS) /**<                            \
-						  INT_FL1_RX_OVERFLOW_PENDING  \
-						  Setting */
+	 << MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS)
 
-#define MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS \
-	1 /**< INT_FL1_TX_UNDERFLOW Position */
+/* INT_FL1_TX_UNDERFLOW Position */
+#define MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS 1
+/* INT_FL1_TX_UNDERFLOW Mask */
 #define MXC_F_I2C_INT_FL1_TX_UNDERFLOW \
-	((uint32_t)(                   \
-		0x1UL                  \
-		<< MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS)) /**<                    \
-							   INT_FL1_TX_UNDERFLOW \
-							   Mask */
-#define MXC_V_I2C_INT_FL1_TX_UNDERFLOW_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL1_TX_UNDERFLOW_INACTIVE Value */
+	(0x1UL << MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS)
+/* INT_FL1_TX_UNDERFLOW_INACTIVE Value */
+#define MXC_V_I2C_INT_FL1_TX_UNDERFLOW_INACTIVE 0x0UL
+/* INT_FL1_TX_UNDERFLOW_INACTIVE Setting */
 #define MXC_S_I2C_INT_FL1_TX_UNDERFLOW_INACTIVE  \
 	(MXC_V_I2C_INT_FL1_TX_UNDERFLOW_INACTIVE \
-	 << MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS) /**<                             \
-						   INT_FL1_TX_UNDERFLOW_INACTIVE \
-						   Setting */
-#define MXC_V_I2C_INT_FL1_TX_UNDERFLOW_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL1_TX_UNDERFLOW_PENDING Value */
+	 << MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS)
+/* INT_FL1_TX_UNDERFLOW_PENDING Value */
+#define MXC_V_I2C_INT_FL1_TX_UNDERFLOW_PENDING 0x1UL
+/* INT_FL1_TX_UNDERFLOW_PENDING Setting */
 #define MXC_S_I2C_INT_FL1_TX_UNDERFLOW_PENDING  \
 	(MXC_V_I2C_INT_FL1_TX_UNDERFLOW_PENDING \
-	 << MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS) /**<                            \
-						   INT_FL1_TX_UNDERFLOW_PENDING \
-						   Setting */
+	 << MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS)
 
 /**
  * Interrupt Staus Register 1.
  */
-#define MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS \
-	0 /**< INT_EN1_RX_OVERFLOW Position                                    \
-	   */
+/* INT_EN1_RX_OVERFLOW Position */
+#define MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS 0
+/* INT_EN1_RX_OVERFLOW Mask */
 #define MXC_F_I2C_INT_EN1_RX_OVERFLOW \
-	((uint32_t)(                  \
-		0x1UL                 \
-		<< MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS)) /**<                    \
-							  INT_EN1_RX_OVERFLOW  \
-							  Mask */
-#define MXC_V_I2C_INT_EN1_RX_OVERFLOW_DIS \
-	((uint32_t)0x0UL) /**< INT_EN1_RX_OVERFLOW_DIS Value */
-#define MXC_S_I2C_INT_EN1_RX_OVERFLOW_DIS  \
-	(MXC_V_I2C_INT_EN1_RX_OVERFLOW_DIS \
-	 << MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS) /**< INT_EN1_RX_OVERFLOW_DIS    \
-						  Setting */
-#define MXC_V_I2C_INT_EN1_RX_OVERFLOW_EN \
-	((uint32_t)0x1UL) /**< INT_EN1_RX_OVERFLOW_EN Value */
-#define MXC_S_I2C_INT_EN1_RX_OVERFLOW_EN  \
-	(MXC_V_I2C_INT_EN1_RX_OVERFLOW_EN \
-	 << MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS) /**< INT_EN1_RX_OVERFLOW_EN     \
-						  Setting */
-
-#define MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS \
-	1 /**< INT_EN1_TX_UNDERFLOW Position */
+	(0x1UL << MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS)
+/* INT_EN1_RX_OVERFLOW_DIS Value */
+#define MXC_V_I2C_INT_EN1_RX_OVERFLOW_DIS 0x0UL
+/* INT_EN1_RX_OVERFLOW_DIS Setting */
+#define MXC_S_I2C_INT_EN1_RX_OVERFLOW_DIS \
+	(MXC_V_I2C_INT_EN1_RX_OVERFLOW_DIS << MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS)
+/* INT_EN1_RX_OVERFLOW_EN Value */
+#define MXC_V_I2C_INT_EN1_RX_OVERFLOW_EN 0x1UL
+/* INT_EN1_RX_OVERFLOW_EN Setting */
+#define MXC_S_I2C_INT_EN1_RX_OVERFLOW_EN \
+	(MXC_V_I2C_INT_EN1_RX_OVERFLOW_EN << MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS)
+
+/* INT_EN1_TX_UNDERFLOW Position */
+#define MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS 1
+/* INT_EN1_TX_UNDERFLOW Mask */
 #define MXC_F_I2C_INT_EN1_TX_UNDERFLOW \
-	((uint32_t)(                   \
-		0x1UL                  \
-		<< MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS)) /**<                    \
-							   INT_EN1_TX_UNDERFLOW \
-							   Mask */
-#define MXC_V_I2C_INT_EN1_TX_UNDERFLOW_DIS \
-	((uint32_t)0x0UL) /**< INT_EN1_TX_UNDERFLOW_DIS Value */
+	(0x1UL << MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS)
+/* INT_EN1_TX_UNDERFLOW_DIS Value */
+#define MXC_V_I2C_INT_EN1_TX_UNDERFLOW_DIS 0x0UL
+/* INT_EN1_TX_UNDERFLOW_DIS Setting */
 #define MXC_S_I2C_INT_EN1_TX_UNDERFLOW_DIS  \
 	(MXC_V_I2C_INT_EN1_TX_UNDERFLOW_DIS \
-	 << MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS) /**< INT_EN1_TX_UNDERFLOW_DIS  \
-						   Setting */
-#define MXC_V_I2C_INT_EN1_TX_UNDERFLOW_EN \
-	((uint32_t)0x1UL) /**< INT_EN1_TX_UNDERFLOW_EN Value */
+	 << MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS)
+/* INT_EN1_TX_UNDERFLOW_EN Value */
+#define MXC_V_I2C_INT_EN1_TX_UNDERFLOW_EN 0x1UL
+/* INT_EN1_TX_UNDERFLOW_EN Setting */
 #define MXC_S_I2C_INT_EN1_TX_UNDERFLOW_EN  \
 	(MXC_V_I2C_INT_EN1_TX_UNDERFLOW_EN \
-	 << MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS) /**< INT_EN1_TX_UNDERFLOW_EN   \
-						   Setting */
+	 << MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS)
 
 /**
  * FIFO Configuration Register.
  */
-#define MXC_F_I2C_FIFO_LEN_RX_LEN_POS 0 /**< FIFO_LEN_RX_LEN Position */
-#define MXC_F_I2C_FIFO_LEN_RX_LEN \
-	((uint32_t)(0xFFUL        \
-		    << MXC_F_I2C_FIFO_LEN_RX_LEN_POS)) /**< FIFO_LEN_RX_LEN \
-							     Mask */
-
-#define MXC_F_I2C_FIFO_LEN_TX_LEN_POS 8 /**< FIFO_LEN_TX_LEN Position */
-#define MXC_F_I2C_FIFO_LEN_TX_LEN \
-	((uint32_t)(0xFFUL        \
-		    << MXC_F_I2C_FIFO_LEN_TX_LEN_POS)) /**< FIFO_LEN_TX_LEN \
-							     Mask */
+/* FIFO_LEN_RX_LEN Position */
+#define MXC_F_I2C_FIFO_LEN_RX_LEN_POS 0
+/* FIFO_LEN_RX_LEN Mask */
+#define MXC_F_I2C_FIFO_LEN_RX_LEN (0xFFUL << MXC_F_I2C_FIFO_LEN_RX_LEN_POS)
+
+/* FIFO_LEN_TX_LEN Position */
+#define MXC_F_I2C_FIFO_LEN_TX_LEN_POS 8
+/* FIFO_LEN_TX_LEN Mask */
+#define MXC_F_I2C_FIFO_LEN_TX_LEN (0xFFUL << MXC_F_I2C_FIFO_LEN_TX_LEN_POS)
 
 /**
  * Receive Control Register 0.
  */
-#define MXC_F_I2C_RX_CTRL0_DNR_POS 0 /**< RX_CTRL0_DNR Position */
-#define MXC_F_I2C_RX_CTRL0_DNR \
-	((uint32_t)(0x1UL      \
-		    << MXC_F_I2C_RX_CTRL0_DNR_POS)) /**< RX_CTRL0_DNR Mask */
-#define MXC_V_I2C_RX_CTRL0_DNR_RESPOND \
-	((uint32_t)0x0UL) /**< RX_CTRL0_DNR_RESPOND Value */
-#define MXC_S_I2C_RX_CTRL0_DNR_RESPOND  \
-	(MXC_V_I2C_RX_CTRL0_DNR_RESPOND \
-	 << MXC_F_I2C_RX_CTRL0_DNR_POS) /**< RX_CTRL0_DNR_RESPOND Setting */
-#define MXC_V_I2C_RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY \
-	((uint32_t)0x1UL) /**< RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY Value */
+/* RX_CTRL0_DNR Position */
+#define MXC_F_I2C_RX_CTRL0_DNR_POS 0
+/* RX_CTRL0_DNR Mask */
+#define MXC_F_I2C_RX_CTRL0_DNR (0x1UL << MXC_F_I2C_RX_CTRL0_DNR_POS)
+/* RX_CTRL0_DNR_RESPOND Value */
+#define MXC_V_I2C_RX_CTRL0_DNR_RESPOND 0x0UL
+/* RX_CTRL0_DNR_RESPOND Setting */
+#define MXC_S_I2C_RX_CTRL0_DNR_RESPOND \
+	(MXC_V_I2C_RX_CTRL0_DNR_RESPOND << MXC_F_I2C_RX_CTRL0_DNR_POS)
+/* RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY Value */
+#define MXC_V_I2C_RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY 0x1UL
+/* RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY Setting */
 #define MXC_S_I2C_RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY  \
 	(MXC_V_I2C_RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY \
-	 << MXC_F_I2C_RX_CTRL0_DNR_POS) /**<                                      \
-					   RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY \
-					   Setting */
-
-#define MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS 7 /**< RX_CTRL0_RX_FLUSH Position */
-#define MXC_F_I2C_RX_CTRL0_RX_FLUSH \
-	((uint32_t)(                \
-		0x1UL               \
-		<< MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS)) /**< RX_CTRL0_RX_FLUSH    \
-							Mask */
-#define MXC_V_I2C_RX_CTRL0_RX_FLUSH_NOT_FLUSHED \
-	((uint32_t)0x0UL) /**< RX_CTRL0_RX_FLUSH_NOT_FLUSHED Value */
+	 << MXC_F_I2C_RX_CTRL0_DNR_POS)
+
+/* RX_CTRL0_RX_FLUSH Position */
+#define MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS 7
+/* RX_CTRL0_RX_FLUSH Mask */
+#define MXC_F_I2C_RX_CTRL0_RX_FLUSH (0x1UL << MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS)
+/* RX_CTRL0_RX_FLUSH_NOT_FLUSHED Value */
+#define MXC_V_I2C_RX_CTRL0_RX_FLUSH_NOT_FLUSHED 0x0UL
+/* RX_CTRL0_RX_FLUSH_NOT_FLUSHED Setting */
 #define MXC_S_I2C_RX_CTRL0_RX_FLUSH_NOT_FLUSHED  \
 	(MXC_V_I2C_RX_CTRL0_RX_FLUSH_NOT_FLUSHED \
-	 << MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS) /**<                              \
-						RX_CTRL0_RX_FLUSH_NOT_FLUSHED  \
-						Setting */
-#define MXC_V_I2C_RX_CTRL0_RX_FLUSH_FLUSH \
-	((uint32_t)0x1UL) /**< RX_CTRL0_RX_FLUSH_FLUSH Value */
-#define MXC_S_I2C_RX_CTRL0_RX_FLUSH_FLUSH  \
-	(MXC_V_I2C_RX_CTRL0_RX_FLUSH_FLUSH \
-	 << MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS) /**< RX_CTRL0_RX_FLUSH_FLUSH      \
-						Setting */
-
-#define MXC_F_I2C_RX_CTRL0_RX_THRESH_POS 8 /**< RX_CTRL0_RX_THRESH Position */
-#define MXC_F_I2C_RX_CTRL0_RX_THRESH \
-	((uint32_t)(                 \
-		0xFUL                \
-		<< MXC_F_I2C_RX_CTRL0_RX_THRESH_POS)) /**< RX_CTRL0_RX_THRESH  \
-							 Mask */
+	 << MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS)
+/* RX_CTRL0_RX_FLUSH_FLUSH Value */
+#define MXC_V_I2C_RX_CTRL0_RX_FLUSH_FLUSH 0x1UL
+/* RX_CTRL0_RX_FLUSH_FLUSH Setting */
+#define MXC_S_I2C_RX_CTRL0_RX_FLUSH_FLUSH \
+	(MXC_V_I2C_RX_CTRL0_RX_FLUSH_FLUSH << MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS)
+
+/* RX_CTRL0_RX_THRESH Position */
+#define MXC_F_I2C_RX_CTRL0_RX_THRESH_POS 8
+/* RX_CTRL0_RX_THRESH Mask */
+#define MXC_F_I2C_RX_CTRL0_RX_THRESH (0xFUL << MXC_F_I2C_RX_CTRL0_RX_THRESH_POS)
 
 /**
  * Receive Control Register 1.
  */
-#define MXC_F_I2C_RX_CTRL1_RX_CNT_POS 0 /**< RX_CTRL1_RX_CNT Position */
-#define MXC_F_I2C_RX_CTRL1_RX_CNT \
-	((uint32_t)(0xFFUL        \
-		    << MXC_F_I2C_RX_CTRL1_RX_CNT_POS)) /**< RX_CTRL1_RX_CNT \
-							     Mask */
-
-#define MXC_F_I2C_RX_CTRL1_RX_FIFO_POS 8 /**< RX_CTRL1_RX_FIFO Position */
-#define MXC_F_I2C_RX_CTRL1_RX_FIFO \
-	((uint32_t)(               \
-		0xFUL              \
-		<< MXC_F_I2C_RX_CTRL1_RX_FIFO_POS)) /**< RX_CTRL1_RX_FIFO  \
-							   Mask */
+/* RX_CTRL1_RX_CNT Position */
+#define MXC_F_I2C_RX_CTRL1_RX_CNT_POS 0
+/* RX_CTRL1_RX_CNT Mask */
+#define MXC_F_I2C_RX_CTRL1_RX_CNT (0xFFUL << MXC_F_I2C_RX_CTRL1_RX_CNT_POS)
+
+/* RX_CTRL1_RX_FIFO Position */
+#define MXC_F_I2C_RX_CTRL1_RX_FIFO_POS 8
+/* RX_CTRL1_RX_FIFO Mask */
+#define MXC_F_I2C_RX_CTRL1_RX_FIFO (0xFUL << MXC_F_I2C_RX_CTRL1_RX_FIFO_POS)
 
 /**
  * Transmit Control Register 0.
  */
-#define MXC_F_I2C_TX_CTRL0_TX_PRELOAD_POS \
-	0 /**< TX_CTRL0_TX_PRELOAD Position                                    \
-	   */
+/* TX_CTRL0_TX_PRELOAD Position */
+#define MXC_F_I2C_TX_CTRL0_TX_PRELOAD_POS 0
+/* TX_CTRL0_TX_PRELOAD Mask */
 #define MXC_F_I2C_TX_CTRL0_TX_PRELOAD \
-	((uint32_t)(                  \
-		0x1UL                 \
-		<< MXC_F_I2C_TX_CTRL0_TX_PRELOAD_POS)) /**<                    \
-							  TX_CTRL0_TX_PRELOAD  \
-							  Mask */
-
-#define MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS \
-	1 /**< TX_CTRL0_TX_READY_MODE Position */
+	(0x1UL << MXC_F_I2C_TX_CTRL0_TX_PRELOAD_POS)
+
+/* TX_CTRL0_TX_READY_MODE Position */
+#define MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS 1
+/* TX_CTRL0_TX_READY_MODE Mask */
 #define MXC_F_I2C_TX_CTRL0_TX_READY_MODE \
-	((uint32_t)(                     \
-		0x1UL                    \
-		<< MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS)) /**<                      \
-							     TX_CTRL0_TX_READY_MODE \
-							     Mask */
-#define MXC_V_I2C_TX_CTRL0_TX_READY_MODE_EN \
-	((uint32_t)0x0UL) /**< TX_CTRL0_TX_READY_MODE_EN Value */
+	(0x1UL << MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS)
+/* TX_CTRL0_TX_READY_MODE_EN Value */
+#define MXC_V_I2C_TX_CTRL0_TX_READY_MODE_EN 0x0UL
+/* TX_CTRL0_TX_READY_MODE_EN Setting */
 #define MXC_S_I2C_TX_CTRL0_TX_READY_MODE_EN  \
 	(MXC_V_I2C_TX_CTRL0_TX_READY_MODE_EN \
-	 << MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS) /**<                         \
-						     TX_CTRL0_TX_READY_MODE_EN \
-						     Setting */
-#define MXC_V_I2C_TX_CTRL0_TX_READY_MODE_DIS \
-	((uint32_t)0x1UL) /**< TX_CTRL0_TX_READY_MODE_DIS Value */
+	 << MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS)
+/* TX_CTRL0_TX_READY_MODE_DIS Value */
+#define MXC_V_I2C_TX_CTRL0_TX_READY_MODE_DIS 0x1UL
+/* TX_CTRL0_TX_READY_MODE_DIS Setting */
 #define MXC_S_I2C_TX_CTRL0_TX_READY_MODE_DIS  \
 	(MXC_V_I2C_TX_CTRL0_TX_READY_MODE_DIS \
-	 << MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS) /**<                          \
-						     TX_CTRL0_TX_READY_MODE_DIS \
-						     Setting */
-
-#define MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS 7 /**< TX_CTRL0_TX_FLUSH Position */
-#define MXC_F_I2C_TX_CTRL0_TX_FLUSH \
-	((uint32_t)(                \
-		0x1UL               \
-		<< MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS)) /**< TX_CTRL0_TX_FLUSH    \
-							Mask */
-#define MXC_V_I2C_TX_CTRL0_TX_FLUSH_NOT_FLUSHED \
-	((uint32_t)0x0UL) /**< TX_CTRL0_TX_FLUSH_NOT_FLUSHED Value */
+	 << MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS)
+
+/* TX_CTRL0_TX_FLUSH Position */
+#define MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS 7
+/* TX_CTRL0_TX_FLUSH Mask */
+#define MXC_F_I2C_TX_CTRL0_TX_FLUSH (0x1UL << MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS)
+/* TX_CTRL0_TX_FLUSH_NOT_FLUSHED Value */
+#define MXC_V_I2C_TX_CTRL0_TX_FLUSH_NOT_FLUSHED 0x0UL
+/* TX_CTRL0_TX_FLUSH_NOT_FLUSHED Setting */
 #define MXC_S_I2C_TX_CTRL0_TX_FLUSH_NOT_FLUSHED  \
 	(MXC_V_I2C_TX_CTRL0_TX_FLUSH_NOT_FLUSHED \
-	 << MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS) /**<                              \
-						TX_CTRL0_TX_FLUSH_NOT_FLUSHED  \
-						Setting */
-#define MXC_V_I2C_TX_CTRL0_TX_FLUSH_FLUSH \
-	((uint32_t)0x1UL) /**< TX_CTRL0_TX_FLUSH_FLUSH Value */
-#define MXC_S_I2C_TX_CTRL0_TX_FLUSH_FLUSH  \
-	(MXC_V_I2C_TX_CTRL0_TX_FLUSH_FLUSH \
-	 << MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS) /**< TX_CTRL0_TX_FLUSH_FLUSH      \
-						Setting */
-
-#define MXC_F_I2C_TX_CTRL0_TX_THRESH_POS 8 /**< TX_CTRL0_TX_THRESH Position */
-#define MXC_F_I2C_TX_CTRL0_TX_THRESH \
-	((uint32_t)(                 \
-		0xFUL                \
-		<< MXC_F_I2C_TX_CTRL0_TX_THRESH_POS)) /**< TX_CTRL0_TX_THRESH  \
-							 Mask */
+	 << MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS)
+/* TX_CTRL0_TX_FLUSH_FLUSH Value */
+#define MXC_V_I2C_TX_CTRL0_TX_FLUSH_FLUSH 0x1UL
+/* TX_CTRL0_TX_FLUSH_FLUSH Setting */
+#define MXC_S_I2C_TX_CTRL0_TX_FLUSH_FLUSH \
+	(MXC_V_I2C_TX_CTRL0_TX_FLUSH_FLUSH << MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS)
+
+/* TX_CTRL0_TX_THRESH Position */
+#define MXC_F_I2C_TX_CTRL0_TX_THRESH_POS 8
+/* TX_CTRL0_TX_THRESH Mask */
+#define MXC_F_I2C_TX_CTRL0_TX_THRESH (0xFUL << MXC_F_I2C_TX_CTRL0_TX_THRESH_POS)
 
 /**
  * Transmit Control Register 1.
  */
-#define MXC_F_I2C_TX_CTRL1_TX_READY_POS 0 /**< TX_CTRL1_TX_READY Position */
-#define MXC_F_I2C_TX_CTRL1_TX_READY \
-	((uint32_t)(                \
-		0x1UL               \
-		<< MXC_F_I2C_TX_CTRL1_TX_READY_POS)) /**< TX_CTRL1_TX_READY    \
-							Mask */
-
-#define MXC_F_I2C_TX_CTRL1_TX_LAST_POS 1 /**< TX_CTRL1_TX_LAST Position */
-#define MXC_F_I2C_TX_CTRL1_TX_LAST \
-	((uint32_t)(               \
-		0x1UL              \
-		<< MXC_F_I2C_TX_CTRL1_TX_LAST_POS)) /**< TX_CTRL1_TX_LAST  \
-							   Mask */
-#define MXC_V_I2C_TX_CTRL1_TX_LAST_HOLD_SCL_LOW \
-	((uint32_t)0x0UL) /**< TX_CTRL1_TX_LAST_HOLD_SCL_LOW Value */
+/* TX_CTRL1_TX_READY Position */
+#define MXC_F_I2C_TX_CTRL1_TX_READY_POS 0
+/* TX_CTRL1_TX_READY Mask */
+#define MXC_F_I2C_TX_CTRL1_TX_READY (0x1UL << MXC_F_I2C_TX_CTRL1_TX_READY_POS)
+
+/* TX_CTRL1_TX_LAST Position */
+#define MXC_F_I2C_TX_CTRL1_TX_LAST_POS 1
+/* TX_CTRL1_TX_LAST Mask */
+#define MXC_F_I2C_TX_CTRL1_TX_LAST (0x1UL << MXC_F_I2C_TX_CTRL1_TX_LAST_POS)
+/* TX_CTRL1_TX_LAST_HOLD_SCL_LOW Value */
+#define MXC_V_I2C_TX_CTRL1_TX_LAST_HOLD_SCL_LOW 0x0UL
+/* TX_CTRL1_TX_LAST_HOLD_SCL_LOW Setting */
 #define MXC_S_I2C_TX_CTRL1_TX_LAST_HOLD_SCL_LOW  \
 	(MXC_V_I2C_TX_CTRL1_TX_LAST_HOLD_SCL_LOW \
-	 << MXC_F_I2C_TX_CTRL1_TX_LAST_POS) /**< TX_CTRL1_TX_LAST_HOLD_SCL_LOW \
-					       Setting */
-#define MXC_V_I2C_TX_CTRL1_TX_LAST_END_TRANSACTION \
-	((uint32_t)0x1UL) /**< TX_CTRL1_TX_LAST_END_TRANSACTION Value */
+	 << MXC_F_I2C_TX_CTRL1_TX_LAST_POS)
+/* TX_CTRL1_TX_LAST_END_TRANSACTION Value */
+#define MXC_V_I2C_TX_CTRL1_TX_LAST_END_TRANSACTION 0x1UL
+/* TX_CTRL1_TX_LAST_END_TRANSACTION Setting */
 #define MXC_S_I2C_TX_CTRL1_TX_LAST_END_TRANSACTION  \
 	(MXC_V_I2C_TX_CTRL1_TX_LAST_END_TRANSACTION \
-	 << MXC_F_I2C_TX_CTRL1_TX_LAST_POS) /**<                                \
-					       TX_CTRL1_TX_LAST_END_TRANSACTION \
-					       Setting */
+	 << MXC_F_I2C_TX_CTRL1_TX_LAST_POS)
 
-#define MXC_F_I2C_TX_CTRL1_TX_FIFO_POS 8 /**< TX_CTRL1_TX_FIFO Position */
-#define MXC_F_I2C_TX_CTRL1_TX_FIFO \
-	((uint32_t)(               \
-		0xFUL              \
-		<< MXC_F_I2C_TX_CTRL1_TX_FIFO_POS)) /**< TX_CTRL1_TX_FIFO  \
-							   Mask */
+/* TX_CTRL1_TX_FIFO Position */
+#define MXC_F_I2C_TX_CTRL1_TX_FIFO_POS 8
+/* TX_CTRL1_TX_FIFO Mask */
+#define MXC_F_I2C_TX_CTRL1_TX_FIFO (0xFUL << MXC_F_I2C_TX_CTRL1_TX_FIFO_POS)
 
 /**
  * Data Register.
  */
-#define MXC_F_I2C_FIFO_DATA_POS 0 /**< FIFO_DATA Position */
-#define MXC_F_I2C_FIFO_DATA \
-	((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_DATA_POS)) /**< FIFO_DATA Mask */
+/* FIFO_DATA Position */
+#define MXC_F_I2C_FIFO_DATA_POS 0
+/* FIFO_DATA Mask */
+#define MXC_F_I2C_FIFO_DATA (0xFFUL << MXC_F_I2C_FIFO_DATA_POS)
 
 /**
- * Master Control Register.
+ * Controller Control Register.
  */
-#define MXC_F_I2C_MASTER_CTRL_START_POS 0 /**< MASTER_CTRL_START Position */
-#define MXC_F_I2C_MASTER_CTRL_START \
-	((uint32_t)(                \
-		0x1UL               \
-		<< MXC_F_I2C_MASTER_CTRL_START_POS)) /**< MASTER_CTRL_START    \
-							Mask */
-
-#define MXC_F_I2C_MASTER_CTRL_RESTART_POS \
-	1 /**< MASTER_CTRL_RESTART Position                                    \
-	   */
-#define MXC_F_I2C_MASTER_CTRL_RESTART \
-	((uint32_t)(                  \
-		0x1UL                 \
-		<< MXC_F_I2C_MASTER_CTRL_RESTART_POS)) /**<                    \
-							  MASTER_CTRL_RESTART  \
-							  Mask */
-
-#define MXC_F_I2C_MASTER_CTRL_STOP_POS 2 /**< MASTER_CTRL_STOP Position */
-#define MXC_F_I2C_MASTER_CTRL_STOP \
-	((uint32_t)(               \
-		0x1UL              \
-		<< MXC_F_I2C_MASTER_CTRL_STOP_POS)) /**< MASTER_CTRL_STOP  \
-							   Mask */
-
-#define MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS \
-	7 /**< MASTER_CTRL_SL_EX_ADDR Position */
-#define MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR \
-	((uint32_t)(                     \
-		0x1UL                    \
-		<< MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS)) /**<                      \
-							     MASTER_CTRL_SL_EX_ADDR \
-							     Mask */
-#define MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS \
-	((uint32_t)0x0UL) /**< MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS Value */
-#define MXC_S_I2C_MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS  \
-	(MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS \
-	 << MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS) /**<                                     \
-						     MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS \
-						     Setting */
-#define MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS \
-	((uint32_t)0x1UL) /**< MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS Value */
-#define MXC_S_I2C_MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS  \
-	(MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS \
-	 << MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS) /**<                                      \
-						     MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS \
-						     Setting */
-
-#define MXC_F_I2C_MASTER_CTRL_MASTER_CODE_POS \
-	8 /**< MASTER_CTRL_MASTER_CODE Position */
-#define MXC_F_I2C_MASTER_CTRL_MASTER_CODE \
-	((uint32_t)(                      \
-		0x7UL                     \
-		<< MXC_F_I2C_MASTER_CTRL_MASTER_CODE_POS)) /**<                       \
-							      MASTER_CTRL_MASTER_CODE \
-							      Mask */
-
-#define MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS \
-	11 /**< MASTER_CTRL_SCL_SPEED_UP Position */
-#define MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP \
-	((uint32_t)(                       \
-		0x1UL                      \
-		<< MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS)) /**<                        \
-							       MASTER_CTRL_SCL_SPEED_UP \
-							       Mask */
-#define MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_EN \
-	((uint32_t)0x0UL) /**< MASTER_CTRL_SCL_SPEED_UP_EN Value */
-#define MXC_S_I2C_MASTER_CTRL_SCL_SPEED_UP_EN  \
-	(MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_EN \
-	 << MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS) /**<                           \
-						       MASTER_CTRL_SCL_SPEED_UP_EN \
-						       Setting */
-#define MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_DIS \
-	((uint32_t)0x1UL) /**< MASTER_CTRL_SCL_SPEED_UP_DIS Value */
-#define MXC_S_I2C_MASTER_CTRL_SCL_SPEED_UP_DIS  \
-	(MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_DIS \
-	 << MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS) /**<                            \
-						       MASTER_CTRL_SCL_SPEED_UP_DIS \
-						       Setting */
+/* CONTROLLER_CTRL_START Position */
+#define MXC_F_I2C_CONTROLLER_CTRL_START_POS 0
+/* CONTROLLER_CTRL_START Mask */
+#define MXC_F_I2C_CONTROLLER_CTRL_START \
+	(0x1UL << MXC_F_I2C_CONTROLLER_CTRL_START_POS)
+
+/* CONTROLLER_CTRL_RESTART Position */
+#define MXC_F_I2C_CONTROLLER_CTRL_RESTART_POS 1
+/* CONTROLLER_CTRL_RESTART Mask */
+#define MXC_F_I2C_CONTROLLER_CTRL_RESTART \
+	(0x1UL << MXC_F_I2C_CONTROLLER_CTRL_RESTART_POS)
+
+/* CONTROLLER_CTRL_STOP Position */
+#define MXC_F_I2C_CONTROLLER_CTRL_STOP_POS 2
+/* CONTROLLER_CTRL_STOP Mask */
+#define MXC_F_I2C_CONTROLLER_CTRL_STOP \
+	(0x1UL << MXC_F_I2C_CONTROLLER_CTRL_STOP_POS)
+
+/* CONTROLLER_CTRL_SL_EX_ADDR Position */
+#define MXC_F_I2C_CONTROLLER_CTRL_SL_EX_ADDR_POS 7
+/* CONTROLLER_CTRL_SL_EX_ADDR Mask */
+#define MXC_F_I2C_CONTROLLER_CTRL_SL_EX_ADDR \
+	(0x1UL << MXC_F_I2C_CONTROLLER_CTRL_SL_EX_ADDR_POS)
+/* CONTROLLER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS Value */
+#define MXC_V_I2C_CONTROLLER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS 0x0UL
+/* CONTROLLER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS Setting */
+#define MXC_S_I2C_CONTROLLER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS  \
+	(MXC_V_I2C_CONTROLLER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS \
+	 << MXC_F_I2C_CONTROLLER_CTRL_SL_EX_ADDR_POS)
+/* CONTROLLER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS Value */
+#define MXC_V_I2C_CONTROLLER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS 0x1UL
+/* CONTROLLER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS Setting */
+#define MXC_S_I2C_CONTROLLER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS  \
+	(MXC_V_I2C_CONTROLLER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS \
+	 << MXC_F_I2C_CONTROLLER_CTRL_SL_EX_ADDR_POS)
+
+/* CONTROLLER_CTRL_CONTROLLER_CODE Position */
+#define MXC_F_I2C_CONTROLLER_CTRL_CONTROLLER_CODE_POS 8
+/* CONTROLLER_CTRL_CONTROLLER_CODE Mask */
+#define MXC_F_I2C_CONTROLLER_CTRL_CONTROLLER_CODE \
+	(0x7UL << MXC_F_I2C_CONTROLLER_CTRL_CONTROLLER_CODE_POS)
+
+/* CONTROLLER_CTRL_SCL_SPEED_UP Position */
+#define MXC_F_I2C_CONTROLLER_CTRL_SCL_SPEED_UP_POS 11
+/* CONTROLLER_CTRL_SCL_SPEED_UP Mask */
+#define MXC_F_I2C_CONTROLLER_CTRL_SCL_SPEED_UP \
+	(0x1UL << MXC_F_I2C_CONTROLLER_CTRL_SCL_SPEED_UP_POS)
+/* CONTROLLER_CTRL_SCL_SPEED_UP_EN Value */
+#define MXC_V_I2C_CONTROLLER_CTRL_SCL_SPEED_UP_EN 0x0UL
+/* CONTROLLER_CTRL_SCL_SPEED_UP_EN Setting */
+#define MXC_S_I2C_CONTROLLER_CTRL_SCL_SPEED_UP_EN  \
+	(MXC_V_I2C_CONTROLLER_CTRL_SCL_SPEED_UP_EN \
+	 << MXC_F_I2C_CONTROLLER_CTRL_SCL_SPEED_UP_POS)
+/* CONTROLLER_CTRL_SCL_SPEED_UP_DIS Value */
+#define MXC_V_I2C_CONTROLLER_CTRL_SCL_SPEED_UP_DIS 0x1UL
+/* CONTROLLER_CTRL_SCL_SPEED_UP_DIS Setting */
+#define MXC_S_I2C_CONTROLLER_CTRL_SCL_SPEED_UP_DIS  \
+	(MXC_V_I2C_CONTROLLER_CTRL_SCL_SPEED_UP_DIS \
+	 << MXC_F_I2C_CONTROLLER_CTRL_SCL_SPEED_UP_POS)
 
 /**
  * Clock Low Register.
  */
-#define MXC_F_I2C_CLK_LO_CLK_LO_POS 0 /**< CLK_LO_CLK_LO Position */
-#define MXC_F_I2C_CLK_LO_CLK_LO \
-	((uint32_t)(            \
-		0x1FFUL         \
-		<< MXC_F_I2C_CLK_LO_CLK_LO_POS)) /**< CLK_LO_CLK_LO Mask */
+/* CLK_LO_CLK_LO Position */
+#define MXC_F_I2C_CLK_LO_CLK_LO_POS 0
+/* CLK_LO_CLK_LO Mask */
+#define MXC_F_I2C_CLK_LO_CLK_LO (0x1FFUL << MXC_F_I2C_CLK_LO_CLK_LO_POS)
 
 /**
  * Clock high Register.
  */
-#define MXC_F_I2C_CLK_HI_CKH_POS 0 /**< CLK_HI_CKH Position */
-#define MXC_F_I2C_CLK_HI_CKH \
-	((uint32_t)(0x1FFUL  \
-		    << MXC_F_I2C_CLK_HI_CKH_POS)) /**< CLK_HI_CKH Mask */
+/* CLK_HI_CKH Position */
+#define MXC_F_I2C_CLK_HI_CKH_POS 0
+/* CLK_HI_CKH Mask */
+#define MXC_F_I2C_CLK_HI_CKH (0x1FFUL << MXC_F_I2C_CLK_HI_CKH_POS)
 
 /**
  * HS-Mode Clock Control Register
  */
-#define MXC_F_I2C_HS_CLK_HS_CLK_LO_POS 0 /**< HS_CLK_HS_CLK_LO Position */
-#define MXC_F_I2C_HS_CLK_HS_CLK_LO \
-	((uint32_t)(               \
-		0xFFUL             \
-		<< MXC_F_I2C_HS_CLK_HS_CLK_LO_POS)) /**< HS_CLK_HS_CLK_LO  \
-							   Mask */
-
-#define MXC_F_I2C_HS_CLK_HS_CLK_HI_POS 8 /**< HS_CLK_HS_CLK_HI Position */
-#define MXC_F_I2C_HS_CLK_HS_CLK_HI \
-	((uint32_t)(               \
-		0xFFUL             \
-		<< MXC_F_I2C_HS_CLK_HS_CLK_HI_POS)) /**< HS_CLK_HS_CLK_HI  \
-							   Mask */
+/* HS_CLK_HS_CLK_LO Position */
+#define MXC_F_I2C_HS_CLK_HS_CLK_LO_POS 0
+/* HS_CLK_HS_CLK_LO Mask */
+#define MXC_F_I2C_HS_CLK_HS_CLK_LO (0xFFUL << MXC_F_I2C_HS_CLK_HS_CLK_LO_POS)
+
+/* HS_CLK_HS_CLK_HI Position */
+#define MXC_F_I2C_HS_CLK_HS_CLK_HI_POS 8
+/* HS_CLK_HS_CLK_HI Mask */
+#define MXC_F_I2C_HS_CLK_HS_CLK_HI (0xFFUL << MXC_F_I2C_HS_CLK_HS_CLK_HI_POS)
 
 /**
  * Timeout Register
  */
-#define MXC_F_I2C_TIMEOUT_TO_POS 0 /**< TIMEOUT_TO Position */
-#define MXC_F_I2C_TIMEOUT_TO \
-	((uint32_t)(0xFFFFUL \
-		    << MXC_F_I2C_TIMEOUT_TO_POS)) /**< TIMEOUT_TO Mask */
+/* TIMEOUT_TO Position */
+#define MXC_F_I2C_TIMEOUT_TO_POS 0
+/* TIMEOUT_TO Mask */
+#define MXC_F_I2C_TIMEOUT_TO (0xFFFFUL << MXC_F_I2C_TIMEOUT_TO_POS)
 
 /**
- * Slave Address Register.
+ * Target Address Register.
  */
-#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_POS \
-	0 /**< SLAVE_ADDR_SLAVE_ADDR Position */
-#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR \
-	((uint32_t)(                    \
-		0x3FFUL                 \
-		<< MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_POS)) /**<                     \
-							    SLAVE_ADDR_SLAVE_ADDR \
-							    Mask */
-
-#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS_POS \
-	10 /**< SLAVE_ADDR_SLAVE_ADDR_DIS Position */
-#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS \
-	((uint32_t)(                        \
-		0x1UL                       \
-		<< MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS_POS)) /**<                         \
-								SLAVE_ADDR_SLAVE_ADDR_DIS \
-								Mask */
-
-#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX_POS \
-	11 /**< SLAVE_ADDR_SLAVE_ADDR_IDX Position */
-#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX \
-	((uint32_t)(                        \
-		0xFUL                       \
-		<< MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX_POS)) /**<                         \
-								SLAVE_ADDR_SLAVE_ADDR_IDX \
-								Mask */
-
-#define MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS \
-	15 /**< SLAVE_ADDR_EX_ADDR Position                                    \
-	    */
-#define MXC_F_I2C_SLAVE_ADDR_EX_ADDR \
-	((uint32_t)(                 \
-		0x1UL                \
-		<< MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS)) /**< SLAVE_ADDR_EX_ADDR  \
-							 Mask */
-#define MXC_V_I2C_SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS \
-	((uint32_t)0x0UL) /**< SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS Value */
-#define MXC_S_I2C_SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS  \
-	(MXC_V_I2C_SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS \
-	 << MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS) /**<                                 \
-						 SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS \
-						 Setting */
-#define MXC_V_I2C_SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS \
-	((uint32_t)0x1UL) /**< SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS Value */
-#define MXC_S_I2C_SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS  \
-	(MXC_V_I2C_SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS \
-	 << MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS) /**<                                  \
-						 SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS \
-						 Setting */
+/* TARGET_ADDR_TARGET_ADDR Position */
+#define MXC_F_I2C_TARGET_ADDR_TARGET_ADDR_POS 0
+/* TARGET_ADDR_TARGET_ADDR Mask */
+#define MXC_F_I2C_TARGET_ADDR_TARGET_ADDR \
+	(0x3FFUL << MXC_F_I2C_TARGET_ADDR_TARGET_ADDR_POS)
+
+/* TARGET_ADDR_TARGET_ADDR_DIS Position */
+#define MXC_F_I2C_TARGET_ADDR_TARGET_ADDR_DIS_POS 10
+/* TARGET_ADDR_TARGET_ADDR_DIS Mask */
+#define MXC_F_I2C_TARGET_ADDR_TARGET_ADDR_DIS \
+	(0x1UL << MXC_F_I2C_TARGET_ADDR_TARGET_ADDR_DIS_POS)
+
+/* TARGET_ADDR_TARGET_ADDR_IDX Position */
+#define MXC_F_I2C_TARGET_ADDR_TARGET_ADDR_IDX_POS 11
+/* TARGET_ADDR_TARGET_ADDR_IDX Mask */
+#define MXC_F_I2C_TARGET_ADDR_TARGET_ADDR_IDX \
+	(0xFUL << MXC_F_I2C_TARGET_ADDR_TARGET_ADDR_IDX_POS)
+
+/* TARGET_ADDR_EX_ADDR Position */
+#define MXC_F_I2C_TARGET_ADDR_EX_ADDR_POS 15
+/* TARGET_ADDR_EX_ADDR Mask */
+#define MXC_F_I2C_TARGET_ADDR_EX_ADDR \
+	(0x1UL << MXC_F_I2C_TARGET_ADDR_EX_ADDR_POS)
+/* TARGET_ADDR_EX_ADDR_7_BITS_ADDRESS Value */
+#define MXC_V_I2C_TARGET_ADDR_EX_ADDR_7_BITS_ADDRESS 0x0UL
+/* TARGET_ADDR_EX_ADDR_7_BITS_ADDRESS Setting */
+#define MXC_S_I2C_TARGET_ADDR_EX_ADDR_7_BITS_ADDRESS  \
+	(MXC_V_I2C_TARGET_ADDR_EX_ADDR_7_BITS_ADDRESS \
+	 << MXC_F_I2C_TARGET_ADDR_EX_ADDR_POS)
+/* TARGET_ADDR_EX_ADDR_10_BITS_ADDRESS Value */
+#define MXC_V_I2C_TARGET_ADDR_EX_ADDR_10_BITS_ADDRESS 0x1UL
+/* TARGET_ADDR_EX_ADDR_10_BITS_ADDRESS Setting */
+#define MXC_S_I2C_TARGET_ADDR_EX_ADDR_10_BITS_ADDRESS  \
+	(MXC_V_I2C_TARGET_ADDR_EX_ADDR_10_BITS_ADDRESS \
+	 << MXC_F_I2C_TARGET_ADDR_EX_ADDR_POS)
 
 /**
  * DMA Register.
  */
-#define MXC_F_I2C_DMA_TX_EN_POS 0 /**< DMA_TX_EN Position */
-#define MXC_F_I2C_DMA_TX_EN \
-	((uint32_t)(0x1UL << MXC_F_I2C_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */
-#define MXC_V_I2C_DMA_TX_EN_DIS ((uint32_t)0x0UL) /**< DMA_TX_EN_DIS Value */
-#define MXC_S_I2C_DMA_TX_EN_DIS  \
-	(MXC_V_I2C_DMA_TX_EN_DIS \
-	 << MXC_F_I2C_DMA_TX_EN_POS) /**< DMA_TX_EN_DIS Setting */
-#define MXC_V_I2C_DMA_TX_EN_EN ((uint32_t)0x1UL) /**< DMA_TX_EN_EN Value */
-#define MXC_S_I2C_DMA_TX_EN_EN  \
-	(MXC_V_I2C_DMA_TX_EN_EN \
-	 << MXC_F_I2C_DMA_TX_EN_POS) /**< DMA_TX_EN_EN Setting */
-
-#define MXC_F_I2C_DMA_RX_EN_POS 1 /**< DMA_RX_EN Position */
-#define MXC_F_I2C_DMA_RX_EN \
-	((uint32_t)(0x1UL << MXC_F_I2C_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */
-#define MXC_V_I2C_DMA_RX_EN_DIS ((uint32_t)0x0UL) /**< DMA_RX_EN_DIS Value */
-#define MXC_S_I2C_DMA_RX_EN_DIS  \
-	(MXC_V_I2C_DMA_RX_EN_DIS \
-	 << MXC_F_I2C_DMA_RX_EN_POS) /**< DMA_RX_EN_DIS Setting */
-#define MXC_V_I2C_DMA_RX_EN_EN ((uint32_t)0x1UL) /**< DMA_RX_EN_EN Value */
-#define MXC_S_I2C_DMA_RX_EN_EN  \
-	(MXC_V_I2C_DMA_RX_EN_EN \
-	 << MXC_F_I2C_DMA_RX_EN_POS) /**< DMA_RX_EN_EN Setting */
+/* DMA_TX_EN Position */
+#define MXC_F_I2C_DMA_TX_EN_POS 0
+/* DMA_TX_EN Mask */
+#define MXC_F_I2C_DMA_TX_EN (0x1UL << MXC_F_I2C_DMA_TX_EN_POS)
+/* DMA_TX_EN_DIS Value */
+#define MXC_V_I2C_DMA_TX_EN_DIS 0x0UL
+/* DMA_TX_EN_DIS Setting */
+#define MXC_S_I2C_DMA_TX_EN_DIS \
+	(MXC_V_I2C_DMA_TX_EN_DIS << MXC_F_I2C_DMA_TX_EN_POS)
+/* DMA_TX_EN_EN Value */
+#define MXC_V_I2C_DMA_TX_EN_EN 0x1UL
+/* DMA_TX_EN_EN Setting */
+#define MXC_S_I2C_DMA_TX_EN_EN \
+	(MXC_V_I2C_DMA_TX_EN_EN << MXC_F_I2C_DMA_TX_EN_POS)
+
+/* DMA_RX_EN Position */
+#define MXC_F_I2C_DMA_RX_EN_POS 1
+/* DMA_RX_EN Mask */
+#define MXC_F_I2C_DMA_RX_EN (0x1UL << MXC_F_I2C_DMA_RX_EN_POS)
+/* DMA_RX_EN_DIS Value */
+#define MXC_V_I2C_DMA_RX_EN_DIS 0x0UL
+/* DMA_RX_EN_DIS Setting */
+#define MXC_S_I2C_DMA_RX_EN_DIS \
+	(MXC_V_I2C_DMA_RX_EN_DIS << MXC_F_I2C_DMA_RX_EN_POS)
+/* DMA_RX_EN_EN Value */
+#define MXC_V_I2C_DMA_RX_EN_EN 0x1UL
+/* DMA_RX_EN_EN Setting */
+#define MXC_S_I2C_DMA_RX_EN_EN \
+	(MXC_V_I2C_DMA_RX_EN_EN << MXC_F_I2C_DMA_RX_EN_POS)
 
 #endif /* _I2C_REGS_H_ */
diff --git a/chip/max32660/icc_regs.h b/chip/max32660/icc_regs.h
index 5f40e4203d..b2dbc75ec3 100644
--- a/chip/max32660/icc_regs.h
+++ b/chip/max32660/icc_regs.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -32,112 +32,110 @@
  */
 typedef struct {
 	__I uint32_t cache_id; /**< <tt>\b 0x0000:<\tt> ICC CACHE_ID Register */
-	__I uint32_t memcfg;   /**< <tt>\b 0x0004:<\tt> ICC MEMCFG Register */
+	__I uint32_t memcfg; /**< <tt>\b 0x0004:<\tt> ICC MEMCFG Register */
 	__R uint32_t rsv_0x8_0xff[62];
-	__IO uint32_t
-		cache_ctrl; /**< <tt>\b 0x0100:<\tt> ICC CACHE_CTRL Register */
+	__IO uint32_t cache_ctrl; /**< <tt>\b 0x0100:<\tt> ICC CACHE_CTRL
+				     Register */
 	__R uint32_t rsv_0x104_0x6ff[383];
-	__IO uint32_t
-		invalidate; /**< <tt>\b 0x0700:<\tt> ICC INVALIDATE Register */
+	__IO uint32_t invalidate; /**< <tt>\b 0x0700:<\tt> ICC INVALIDATE
+				     Register */
 } mxc_icc_regs_t;
 
 /**
  * ICC Peripheral Register Offsets from the ICC Base Peripheral
  * Address.
  */
-#define MXC_R_ICC_CACHE_ID                                                     \
-	((uint32_t)0x00000000UL) /**< Offset from ICC Base Address: <tt>       \
+#define MXC_R_ICC_CACHE_ID                                               \
+	((uint32_t)0x00000000UL) /**< Offset from ICC Base Address: <tt> \
 				    0x0x000 */
-#define MXC_R_ICC_MEMCFG                                                       \
-	((uint32_t)0x00000004UL) /**< Offset from ICC Base Address: <tt>       \
+#define MXC_R_ICC_MEMCFG                                                 \
+	((uint32_t)0x00000004UL) /**< Offset from ICC Base Address: <tt> \
 				    0x0x004 */
-#define MXC_R_ICC_CACHE_CTRL                                                   \
-	((uint32_t)0x00000100UL) /**< Offset from ICC Base Address: <tt>       \
+#define MXC_R_ICC_CACHE_CTRL                                             \
+	((uint32_t)0x00000100UL) /**< Offset from ICC Base Address: <tt> \
 				    0x0x100 */
-#define MXC_R_ICC_INVALIDATE                                                   \
-	((uint32_t)0x00000700UL) /**< Offset from ICC Base Address: <tt>       \
+#define MXC_R_ICC_INVALIDATE                                             \
+	((uint32_t)0x00000700UL) /**< Offset from ICC Base Address: <tt> \
 				    0x0x700 */
 
 /**
  * Cache ID Register.
  */
 #define MXC_F_ICC_CACHE_ID_RELNUM_POS 0 /**< CACHE_ID_RELNUM Position */
-#define MXC_F_ICC_CACHE_ID_RELNUM                                              \
-	((uint32_t)(                                                           \
-		0x3FUL << MXC_F_ICC_CACHE_ID_RELNUM_POS)) /**< CACHE_ID_RELNUM \
-							     Mask */
+#define MXC_F_ICC_CACHE_ID_RELNUM                                           \
+	((uint32_t)(0x3FUL                                                  \
+		    << MXC_F_ICC_CACHE_ID_RELNUM_POS)) /**< CACHE_ID_RELNUM \
+							  Mask */
 
 #define MXC_F_ICC_CACHE_ID_PARTNUM_POS 6 /**< CACHE_ID_PARTNUM Position */
-#define MXC_F_ICC_CACHE_ID_PARTNUM                                             \
-	((uint32_t)(0xFUL                                                      \
-		    << MXC_F_ICC_CACHE_ID_PARTNUM_POS)) /**< CACHE_ID_PARTNUM  \
+#define MXC_F_ICC_CACHE_ID_PARTNUM                                            \
+	((uint32_t)(0xFUL                                                     \
+		    << MXC_F_ICC_CACHE_ID_PARTNUM_POS)) /**< CACHE_ID_PARTNUM \
 							   Mask */
 
 #define MXC_F_ICC_CACHE_ID_CCHID_POS 10 /**< CACHE_ID_CCHID Position */
 #define MXC_F_ICC_CACHE_ID_CCHID                                               \
-	((uint32_t)(                                                           \
-		0x3FUL                                                         \
-		<< MXC_F_ICC_CACHE_ID_CCHID_POS)) /**< CACHE_ID_CCHID Mask */
+	((uint32_t)(0x3FUL << MXC_F_ICC_CACHE_ID_CCHID_POS)) /**<              \
+								CACHE_ID_CCHID \
+								Mask */
 
 /**
  * Memory Configuration Register.
  */
 #define MXC_F_ICC_MEMCFG_CCHSZ_POS 0 /**< MEMCFG_CCHSZ Position */
 #define MXC_F_ICC_MEMCFG_CCHSZ                                                 \
-	((uint32_t)(0xFFFFUL                                                   \
-		    << MXC_F_ICC_MEMCFG_CCHSZ_POS)) /**< MEMCFG_CCHSZ Mask */
+	((uint32_t)(0xFFFFUL << MXC_F_ICC_MEMCFG_CCHSZ_POS)) /**< MEMCFG_CCHSZ \
+								Mask */
 
 #define MXC_F_ICC_MEMCFG_MEMSZ_POS 16 /**< MEMCFG_MEMSZ Position */
 #define MXC_F_ICC_MEMCFG_MEMSZ                                                 \
-	((uint32_t)(0xFFFFUL                                                   \
-		    << MXC_F_ICC_MEMCFG_MEMSZ_POS)) /**< MEMCFG_MEMSZ Mask */
+	((uint32_t)(0xFFFFUL << MXC_F_ICC_MEMCFG_MEMSZ_POS)) /**< MEMCFG_MEMSZ \
+								Mask */
 
 /**
  * Cache Control and Status Register.
  */
-#define MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS                                      \
-	0 /**< CACHE_CTRL_CACHE_EN Position                                    \
+#define MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS   \
+	0 /**< CACHE_CTRL_CACHE_EN Position \
 	   */
-#define MXC_F_ICC_CACHE_CTRL_CACHE_EN                                          \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS)) /**<                    \
-							  CACHE_CTRL_CACHE_EN  \
-							  Mask */
-#define MXC_V_ICC_CACHE_CTRL_CACHE_EN_DIS                                      \
+#define MXC_F_ICC_CACHE_CTRL_CACHE_EN                                             \
+	((uint32_t)(0x1UL                                                         \
+		    << MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS)) /**<                   \
+							      CACHE_CTRL_CACHE_EN \
+							      Mask */
+#define MXC_V_ICC_CACHE_CTRL_CACHE_EN_DIS \
 	((uint32_t)0x0UL) /**< CACHE_CTRL_CACHE_EN_DIS Value */
-#define MXC_S_ICC_CACHE_CTRL_CACHE_EN_DIS                                      \
-	(MXC_V_ICC_CACHE_CTRL_CACHE_EN_DIS                                     \
-	 << MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS) /**< CACHE_CTRL_CACHE_EN_DIS    \
+#define MXC_S_ICC_CACHE_CTRL_CACHE_EN_DIS                                   \
+	(MXC_V_ICC_CACHE_CTRL_CACHE_EN_DIS                                  \
+	 << MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS) /**< CACHE_CTRL_CACHE_EN_DIS \
 						  Setting */
-#define MXC_V_ICC_CACHE_CTRL_CACHE_EN_EN                                       \
+#define MXC_V_ICC_CACHE_CTRL_CACHE_EN_EN \
 	((uint32_t)0x1UL) /**< CACHE_CTRL_CACHE_EN_EN Value */
-#define MXC_S_ICC_CACHE_CTRL_CACHE_EN_EN                                       \
-	(MXC_V_ICC_CACHE_CTRL_CACHE_EN_EN                                      \
-	 << MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS) /**< CACHE_CTRL_CACHE_EN_EN     \
+#define MXC_S_ICC_CACHE_CTRL_CACHE_EN_EN                                   \
+	(MXC_V_ICC_CACHE_CTRL_CACHE_EN_EN                                  \
+	 << MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS) /**< CACHE_CTRL_CACHE_EN_EN \
 						  Setting */
 
-#define MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS                                     \
+#define MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS \
 	16 /**< CACHE_CTRL_CACHE_RDY Position */
-#define MXC_F_ICC_CACHE_CTRL_CACHE_RDY                                          \
-	((uint32_t)(                                                            \
-		0x1UL                                                           \
-		<< MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS)) /**<                    \
-							   CACHE_CTRL_CACHE_RDY \
-							   Mask */
-#define MXC_V_ICC_CACHE_CTRL_CACHE_RDY_NOTREADY                                \
+#define MXC_F_ICC_CACHE_CTRL_CACHE_RDY                                              \
+	((uint32_t)(0x1UL                                                           \
+		    << MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS)) /**<                    \
+							       CACHE_CTRL_CACHE_RDY \
+							       Mask */
+#define MXC_V_ICC_CACHE_CTRL_CACHE_RDY_NOTREADY \
 	((uint32_t)0x0UL) /**< CACHE_CTRL_CACHE_RDY_NOTREADY Value */
 #define MXC_S_ICC_CACHE_CTRL_CACHE_RDY_NOTREADY                                  \
 	(MXC_V_ICC_CACHE_CTRL_CACHE_RDY_NOTREADY                                 \
 	 << MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS) /**<                             \
 						   CACHE_CTRL_CACHE_RDY_NOTREADY \
 						   Setting */
-#define MXC_V_ICC_CACHE_CTRL_CACHE_RDY_READY                                   \
+#define MXC_V_ICC_CACHE_CTRL_CACHE_RDY_READY \
 	((uint32_t)0x1UL) /**< CACHE_CTRL_CACHE_RDY_READY Value */
-#define MXC_S_ICC_CACHE_CTRL_CACHE_RDY_READY                                   \
-	(MXC_V_ICC_CACHE_CTRL_CACHE_RDY_READY                                  \
-	 << MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS) /**<                           \
-						   CACHE_CTRL_CACHE_RDY_READY  \
+#define MXC_S_ICC_CACHE_CTRL_CACHE_RDY_READY                                  \
+	(MXC_V_ICC_CACHE_CTRL_CACHE_RDY_READY                                 \
+	 << MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS) /**<                          \
+						   CACHE_CTRL_CACHE_RDY_READY \
 						   Setting */
 
 #endif /* _ICC_REGS_H_ */
diff --git a/chip/max32660/pwrseq_regs.h b/chip/max32660/pwrseq_regs.h
index f323b4568c..e42ab8fd9d 100644
--- a/chip/max32660/pwrseq_regs.h
+++ b/chip/max32660/pwrseq_regs.h
@@ -1,489 +1,502 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MAX32660 Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral */
-
-#ifndef _PWRSEQ_REGS_H_
-#define _PWRSEQ_REGS_H_
-
-/* **** Includes **** */
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if defined(__ICCARM__)
-#pragma system_include
-#endif
-
-#if defined(__CC_ARM)
-#pragma anon_unions
-#endif
-
-/*
-    If types are not defined elsewhere (CMSIS) define them here
-*/
-#ifndef __IO
-#define __IO volatile
-#endif
-#ifndef __I
-#define __I volatile const
-#endif
-#ifndef __O
-#define __O volatile
-#endif
-#ifndef __R
-#define __R volatile const
-#endif
-
-/* **** Definitions **** */
-
-/**
- * mxc_pwrseq_regs_t
- * Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral
- * Module.
- */
-
-/**
- * pwrseq_registers
- * Structure type to access the PWRSEQ Registers.
- */
-typedef struct {
-	__IO uint32_t lp_ctrl; /**< <tt>\b 0x00:</tt> PWRSEQ LP_CTRL Register */
-	__IO uint32_t
-		lp_wakefl; /**< <tt>\b 0x04:</tt> PWRSEQ LP_WAKEFL Register */
-	__IO uint32_t lpwk_en; /**< <tt>\b 0x08:</tt> PWRSEQ LPWK_EN Register */
-	__R uint32_t rsv_0xc_0x3f[13];
-	__IO uint32_t lpmemsd; /**< <tt>\b 0x40:</tt> PWRSEQ LPMEMSD Register */
-} mxc_pwrseq_regs_t;
-
-/**
- * Register offsets for module PWRSEQ
- * PWRSEQ Peripheral Register Offsets from the PWRSEQ Base
- */
-#define MXC_R_PWRSEQ_LP_CTRL                                                   \
-	((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: <tt> \  \
-				    \ \ \ 0x0000</tt> */
-#define MXC_R_PWRSEQ_LP_WAKEFL                                                 \
-	((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: <tt> \  \
-				    \ \ \ 0x0004</tt> */
-#define MXC_R_PWRSEQ_LPWK_EN                                                   \
-	((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: <tt> \  \
-				    \ \ \ 0x0008</tt> */
-#define MXC_R_PWRSEQ_LPMEMSD                                                   \
-	((uint32_t)0x00000040UL) /**< Offset from PWRSEQ Base Address: <tt> \  \
-				    \ \ \ 0x0040</tt> */
-
-/**
- * pwrseq_registers
- * Low Power Control Register.
- */
-#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS                                   \
-	0 /**< LP_CTRL_RAMRET_SEL0 Position */
-#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0                                         \
-	((uint32_t)(                                                             \
-		0x1UL                                                            \
-		<< MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS)) /**< \ \ \ \                                                                               \
-							     LP_CTRL_RAMRET_SEL0 \
-							     \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS                                   \
-	((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL0_DIS Value */
-#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS                                   \
-	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS                                  \
-	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS) /**< LP_CTRL_RAMRET_SEL0_DIS \
-						     \ \ \ \ Setting */
-#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN                                    \
-	((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL0_EN Value */
-#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN                                    \
-	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN                                   \
-	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS) /**< LP_CTRL_RAMRET_SEL0_EN  \
-						     \ \ \ \ Setting */
-
-#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS                                   \
-	1 /**< LP_CTRL_RAMRET_SEL1 Position */
-#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1                                         \
-	((uint32_t)(                                                             \
-		0x1UL                                                            \
-		<< MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS)) /**< \ \ \ \                                                                               \
-							     LP_CTRL_RAMRET_SEL1 \
-							     \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS                                   \
-	((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL1_DIS Value */
-#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS                                   \
-	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS                                  \
-	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS) /**< LP_CTRL_RAMRET_SEL1_DIS \
-						     \ \ \ \ Setting */
-#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN                                    \
-	((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL1_EN Value */
-#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN                                    \
-	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN                                   \
-	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS) /**< LP_CTRL_RAMRET_SEL1_EN  \
-						     \ \ \ \ Setting */
-
-#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS                                   \
-	2 /**< LP_CTRL_RAMRET_SEL2 Position */
-#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2                                         \
-	((uint32_t)(                                                             \
-		0x1UL                                                            \
-		<< MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS)) /**< \ \ \ \                                                                               \
-							     LP_CTRL_RAMRET_SEL2 \
-							     \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS                                   \
-	((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL2_DIS Value */
-#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS                                   \
-	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS                                  \
-	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS) /**< LP_CTRL_RAMRET_SEL2_DIS \
-						     \ \ \ \ Setting */
-#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN                                    \
-	((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL2_EN Value */
-#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN                                    \
-	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN                                   \
-	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS) /**< LP_CTRL_RAMRET_SEL2_EN  \
-						     \ \ \ \ Setting */
-
-#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS                                   \
-	3 /**< LP_CTRL_RAMRET_SEL3 Position */
-#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3                                         \
-	((uint32_t)(                                                             \
-		0x1UL                                                            \
-		<< MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS)) /**< \ \ \ \                                                                               \
-							     LP_CTRL_RAMRET_SEL3 \
-							     \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS                                   \
-	((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL3_DIS Value */
-#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS                                   \
-	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS                                  \
-	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS) /**< LP_CTRL_RAMRET_SEL3_DIS \
-						     \ \ \ \ Setting */
-#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN                                    \
-	((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL3_EN Value */
-#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN                                    \
-	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN                                   \
-	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS) /**< LP_CTRL_RAMRET_SEL3_EN  \
-						     \ \ \ \ Setting */
-
-#define MXC_F_PWRSEQ_LP_CTRL_OVR_POS 4 /**< LP_CTRL_OVR Position */
-#define MXC_F_PWRSEQ_LP_CTRL_OVR                                               \
-	((uint32_t)(0x3UL                                                      \
-		    << MXC_F_PWRSEQ_LP_CTRL_OVR_POS)) /**< LP_CTRL_OVR Mask */
-#define MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V                                          \
-	((uint32_t)0x0UL) /**< LP_CTRL_OVR_0_9V Value */
-#define MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V                                          \
-	(MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V                                         \
-	 << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_0_9V Setting */
-#define MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V                                          \
-	((uint32_t)0x1UL) /**< LP_CTRL_OVR_1_0V Value */
-#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V                                          \
-	(MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V                                         \
-	 << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_1_0V Setting */
-#define MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V                                          \
-	((uint32_t)0x2UL) /**< LP_CTRL_OVR_1_1V Value */
-#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_1V                                          \
-	(MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V                                         \
-	 << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_1_1V Setting */
-
-#define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS                              \
-	6 /**< LP_CTRL_VCORE_DET_BYPASS Position */
-#define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS                                              \
-	((uint32_t)(                                                                       \
-		0x1UL                                                                      \
-		<< MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS)) /**< \ \ \ \                                                                                         \
-								  LP_CTRL_VCORE_DET_BYPASS \
-								  \                        \
-								  \ \ \ \                                                                                         \
-								  Mask */
-#define MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED                          \
-	((uint32_t)0x0UL) /**< LP_CTRL_VCORE_DET_BYPASS_ENABLED Value */
-#define MXC_S_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED                                      \
-	(MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED                                     \
-	 << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS) /**< \ \ \ \                                                                                         \
-							  LP_CTRL_VCORE_DET_BYPASS_ENABLED \
-							  \ \ \ \ Setting */
-#define MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE                          \
-	((uint32_t)0x1UL) /**< LP_CTRL_VCORE_DET_BYPASS_DISABLE Value */
-#define MXC_S_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE                                      \
-	(MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE                                     \
-	 << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS) /**< \ \ \ \                                                                                         \
-							  LP_CTRL_VCORE_DET_BYPASS_DISABLE \
-							  \ \ \ \ Setting */
-
-#define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS                                     \
-	8 /**< LP_CTRL_RETREG_EN Position   \ \ \ \                                                                             \
-	   */
-#define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN                                         \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS)) /**< LP_CTRL_RETREG_EN \
-							   \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_DIS                                     \
-	((uint32_t)0x0UL) /**< LP_CTRL_RETREG_EN_DIS Value */
-#define MXC_S_PWRSEQ_LP_CTRL_RETREG_EN_DIS                                     \
-	(MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_DIS                                    \
-	 << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS) /**< LP_CTRL_RETREG_EN_DIS \ \ \
-						   \ \ Setting */
-#define MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_EN                                      \
-	((uint32_t)0x1UL) /**< LP_CTRL_RETREG_EN_EN Value */
-#define MXC_S_PWRSEQ_LP_CTRL_RETREG_EN_EN                                      \
-	(MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_EN                                     \
-	 << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS) /**< LP_CTRL_RETREG_EN_EN \ \  \
-						   \ \ Setting */
-
-#define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS                                    \
-	10 /**< LP_CTRL_FAST_WK_EN Position */
-#define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN                                        \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS)) /**< \ \ \ \                                                                             \
-							    LP_CTRL_FAST_WK_EN \
-							    \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS                                    \
-	((uint32_t)0x0UL) /**< LP_CTRL_FAST_WK_EN_DIS Value */
-#define MXC_S_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS                                    \
-	(MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS                                   \
-	 << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS) /**< LP_CTRL_FAST_WK_EN_DIS \ \
-						    \ \ \ Setting */
-#define MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_EN                                     \
-	((uint32_t)0x1UL) /**< LP_CTRL_FAST_WK_EN_EN Value */
-#define MXC_S_PWRSEQ_LP_CTRL_FAST_WK_EN_EN                                     \
-	(MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_EN                                    \
-	 << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS) /**< LP_CTRL_FAST_WK_EN_EN \  \
-						    \ \ \ Setting */
-
-#define MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS 11 /**< LP_CTRL_BG_OFF Position */
-#define MXC_F_PWRSEQ_LP_CTRL_BG_OFF                                            \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS)) /**< LP_CTRL_BG_OFF \
-							      \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LP_CTRL_BG_OFF_ON                                         \
-	((uint32_t)0x0UL) /**< LP_CTRL_BG_OFF_ON Value */
-#define MXC_S_PWRSEQ_LP_CTRL_BG_OFF_ON                                         \
-	(MXC_V_PWRSEQ_LP_CTRL_BG_OFF_ON                                        \
-	 << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS) /**< LP_CTRL_BG_OFF_ON Setting */
-#define MXC_V_PWRSEQ_LP_CTRL_BG_OFF_OFF                                        \
-	((uint32_t)0x1UL) /**< LP_CTRL_BG_OFF_OFF Value */
-#define MXC_S_PWRSEQ_LP_CTRL_BG_OFF_OFF                                        \
-	(MXC_V_PWRSEQ_LP_CTRL_BG_OFF_OFF                                       \
-	 << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS) /**< LP_CTRL_BG_OFF_OFF Setting \ \
-					      * \                              \
-					      * \ \                                                                             \
-					      * \ \ \                                                                             \
-					      */
-
-#define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS                                 \
-	12 /**< LP_CTRL_VCORE_POR_DIS Position */
-#define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS                                           \
-	((uint32_t)(                                                                 \
-		0x1UL                                                                \
-		<< MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS)) /**< \ \ \ \                                                                                   \
-							       LP_CTRL_VCORE_POR_DIS \
-							       \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS                                 \
-	((uint32_t)0x0UL) /**< LP_CTRL_VCORE_POR_DIS_DIS Value */
-#define MXC_S_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS                                   \
-	(MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS                                  \
-	 << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS) /**< \ \ \ \                                                                               \
-						       LP_CTRL_VCORE_POR_DIS_DIS \
-						       \ \ \ \ Setting */
-#define MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN                                  \
-	((uint32_t)0x1UL) /**< LP_CTRL_VCORE_POR_DIS_EN Value */
-#define MXC_S_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN                                   \
-	(MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN                                  \
-	 << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS) /**< \ \ \ \                                                                              \
-						       LP_CTRL_VCORE_POR_DIS_EN \
-						       \ \ \ \ Setting */
-
-#define MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS 16 /**< LP_CTRL_LDO_DIS Position */
-#define MXC_F_PWRSEQ_LP_CTRL_LDO_DIS                                           \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS)) /**< LP_CTRL_LDO_DIS \
-							     \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_EN                                        \
-	((uint32_t)0x0UL) /**< LP_CTRL_LDO_DIS_EN Value */
-#define MXC_S_PWRSEQ_LP_CTRL_LDO_DIS_EN                                        \
-	(MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_EN                                       \
-	 << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS) /**< LP_CTRL_LDO_DIS_EN Setting  \
-					       * \                             \
-					       * \ \                                                                             \
-					       * \ \ \                                                                             \
-					       * \ \ \ \                                                                             \
-					       */
-#define MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_DIS                                       \
-	((uint32_t)0x1UL) /**< LP_CTRL_LDO_DIS_DIS Value */
-#define MXC_S_PWRSEQ_LP_CTRL_LDO_DIS_DIS                                       \
-	(MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_DIS                                      \
-	 << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS) /**< LP_CTRL_LDO_DIS_DIS Setting \
-					       * \                             \
-					       * \ \                                                                             \
-					       * \ \ \                                                                             \
-					       * \ \ \ \                                                                             \
-					       */
-
-#define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS                                 \
-	20 /**< LP_CTRL_VCORE_SVM_DIS Position */
-#define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS                                           \
-	((uint32_t)(                                                                 \
-		0x1UL                                                                \
-		<< MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS)) /**< \ \ \ \                                                                                   \
-							       LP_CTRL_VCORE_SVM_DIS \
-							       \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN                                  \
-	((uint32_t)0x0UL) /**< LP_CTRL_VCORE_SVM_DIS_EN Value */
-#define MXC_S_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN                                   \
-	(MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN                                  \
-	 << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS) /**< \ \ \ \                                                                              \
-						       LP_CTRL_VCORE_SVM_DIS_EN \
-						       \ \ \ \ Setting */
-#define MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS                                 \
-	((uint32_t)0x1UL) /**< LP_CTRL_VCORE_SVM_DIS_DIS Value */
-#define MXC_S_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS                                   \
-	(MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS                                  \
-	 << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS) /**< \ \ \ \                                                                               \
-						       LP_CTRL_VCORE_SVM_DIS_DIS \
-						       \ \ \ \ Setting */
-
-#define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS                                 \
-	25 /**< LP_CTRL_VDDIO_POR_DIS Position */
-#define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS                                           \
-	((uint32_t)(                                                                 \
-		0x1UL                                                                \
-		<< MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS)) /**< \ \ \ \                                                                                   \
-							       LP_CTRL_VDDIO_POR_DIS \
-							       \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN                                  \
-	((uint32_t)0x0UL) /**< LP_CTRL_VDDIO_POR_DIS_EN Value */
-#define MXC_S_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN                                   \
-	(MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN                                  \
-	 << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS) /**< \ \ \ \                                                                              \
-						       LP_CTRL_VDDIO_POR_DIS_EN \
-						       \ \ \ \ Setting */
-#define MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS                                 \
-	((uint32_t)0x1UL) /**< LP_CTRL_VDDIO_POR_DIS_DIS Value */
-#define MXC_S_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS                                   \
-	(MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS                                  \
-	 << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS) /**< \ \ \ \                                                                               \
-						       LP_CTRL_VDDIO_POR_DIS_DIS \
-						       \ \ \ \ Setting */
-
-/**
- * pwrseq_registers
- * Low Power Mode Wakeup Flags for GPIO0
- */
-#define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS 0 /**< LP_WAKEFL_WAKEST Position */
-#define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST                                          \
-	((uint32_t)(                                                           \
-		0x3FFFUL                                                       \
-		<< MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS)) /**< LP_WAKEFL_WAKEST \ \
-							  \ \ \ Mask */
-
-/**
- * pwrseq_registers
- * Low Power I/O Wakeup Enable Register 0. This register enables low
- * power wakeup functionality for GPIO0.
- */
-#define MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS 0 /**< LPWK_EN_WAKEEN Position */
-#define MXC_F_PWRSEQ_LPWK_EN_WAKEEN                                            \
-	((uint32_t)(0x3FFFUL                                                   \
-		    << MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS)) /**< LPWK_EN_WAKEEN \ \
-							    \ \ \ Mask */
-
-/**
- * pwrseq_registers
- * Low Power Memory Shutdown Control.
- */
-#define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS                                     \
-	0 /**< LPMEMSD_SRAM0_OFF Position   \ \ \ \                                                                             \
-	   */
-#define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF                                         \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS)) /**< LPMEMSD_SRAM0_OFF \
-							   \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL                                  \
-	((uint32_t)0x0UL) /**< LPMEMSD_SRAM0_OFF_NORMAL Value */
-#define MXC_S_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL                                  \
-	(MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL                                 \
-	 << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS) /**< LPMEMSD_SRAM0_OFF_NORMAL  \
-						   \ \ \ \ Setting */
-#define MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN                                \
-	((uint32_t)0x1UL) /**< LPMEMSD_SRAM0_OFF_SHUTDOWN Value */
-#define MXC_S_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN                                \
-	(MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN                               \
-	 << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS) /**< \ \ \ \                                                                             \
-						   LPMEMSD_SRAM0_OFF_SHUTDOWN  \
-						   \ \ \ \ Setting */
-
-#define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS                                     \
-	1 /**< LPMEMSD_SRAM1_OFF Position   \ \ \ \                                                                             \
-	   */
-#define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF                                         \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS)) /**< LPMEMSD_SRAM1_OFF \
-							   \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL                                  \
-	((uint32_t)0x0UL) /**< LPMEMSD_SRAM1_OFF_NORMAL Value */
-#define MXC_S_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL                                  \
-	(MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL                                 \
-	 << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS) /**< LPMEMSD_SRAM1_OFF_NORMAL  \
-						   \ \ \ \ Setting */
-#define MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN                                \
-	((uint32_t)0x1UL) /**< LPMEMSD_SRAM1_OFF_SHUTDOWN Value */
-#define MXC_S_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN                                \
-	(MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN                               \
-	 << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS) /**< \ \ \ \                                                                             \
-						   LPMEMSD_SRAM1_OFF_SHUTDOWN  \
-						   \ \ \ \ Setting */
-
-#define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS                                     \
-	2 /**< LPMEMSD_SRAM2_OFF Position   \ \ \ \                                                                             \
-	   */
-#define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF                                         \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS)) /**< LPMEMSD_SRAM2_OFF \
-							   \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL                                  \
-	((uint32_t)0x0UL) /**< LPMEMSD_SRAM2_OFF_NORMAL Value */
-#define MXC_S_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL                                  \
-	(MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL                                 \
-	 << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS) /**< LPMEMSD_SRAM2_OFF_NORMAL  \
-						   \ \ \ \ Setting */
-#define MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN                                \
-	((uint32_t)0x1UL) /**< LPMEMSD_SRAM2_OFF_SHUTDOWN Value */
-#define MXC_S_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN                                \
-	(MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN                               \
-	 << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS) /**< \ \ \ \                                                                             \
-						   LPMEMSD_SRAM2_OFF_SHUTDOWN  \
-						   \ \ \ \ Setting */
-
-#define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS                                     \
-	3 /**< LPMEMSD_SRAM3_OFF Position   \ \ \ \                                                                             \
-	   */
-#define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF                                         \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS)) /**< LPMEMSD_SRAM3_OFF \
-							   \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL                                  \
-	((uint32_t)0x0UL) /**< LPMEMSD_SRAM3_OFF_NORMAL Value */
-#define MXC_S_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL                                  \
-	(MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL                                 \
-	 << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS) /**< LPMEMSD_SRAM3_OFF_NORMAL  \
-						   \ \ \ \ Setting */
-#define MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN                                \
-	((uint32_t)0x1UL) /**< LPMEMSD_SRAM3_OFF_SHUTDOWN Value */
-#define MXC_S_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN                                \
-	(MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN                               \
-	 << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS) /**< \ \ \ \                                                                             \
-						   LPMEMSD_SRAM3_OFF_SHUTDOWN  \
-						   \ \ \ \ Setting */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _PWRSEQ_REGS_H_ */
+/* Copyright 2019 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* MAX32660 Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral */
+
+#ifndef _PWRSEQ_REGS_H_
+#define _PWRSEQ_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(__ICCARM__)
+#pragma system_include
+#endif
+
+#if defined(__CC_ARM)
+#pragma anon_unions
+#endif
+
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __R
+#define __R volatile const
+#endif
+
+/* **** Definitions **** */
+
+/**
+ * mxc_pwrseq_regs_t
+ * Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral
+ * Module.
+ */
+
+/**
+ * pwrseq_registers
+ * Structure type to access the PWRSEQ Registers.
+ */
+typedef struct {
+	__IO uint32_t lp_ctrl; /**< <tt>\b 0x00:</tt> PWRSEQ LP_CTRL Register */
+	__IO uint32_t lp_wakefl; /**< <tt>\b 0x04:</tt> PWRSEQ LP_WAKEFL
+				    Register */
+	__IO uint32_t lpwk_en; /**< <tt>\b 0x08:</tt> PWRSEQ LPWK_EN Register */
+	__R uint32_t rsv_0xc_0x3f[13];
+	__IO uint32_t lpmemsd; /**< <tt>\b 0x40:</tt> PWRSEQ LPMEMSD Register */
+} mxc_pwrseq_regs_t;
+
+/**
+ * Register offsets for module PWRSEQ
+ * PWRSEQ Peripheral Register Offsets from the PWRSEQ Base
+ */
+#define MXC_R_PWRSEQ_LP_CTRL                                                  \
+	((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: <tt> \ \
+				    \ \ \ 0x0000</tt> */
+#define MXC_R_PWRSEQ_LP_WAKEFL                                                \
+	((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: <tt> \ \
+				    \ \ \ 0x0004</tt> */
+#define MXC_R_PWRSEQ_LPWK_EN                                                  \
+	((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: <tt> \ \
+				    \ \ \ 0x0008</tt> */
+#define MXC_R_PWRSEQ_LPMEMSD                                                  \
+	((uint32_t)0x00000040UL) /**< Offset from PWRSEQ Base Address: <tt> \ \
+				    \ \ \ 0x0040</tt> */
+
+/**
+ * pwrseq_registers
+ * Low Power Control Register.
+ */
+#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS \
+	0 /**< LP_CTRL_RAMRET_SEL0 Position */
+#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0                                             \
+	((uint32_t)(0x1UL                                                            \
+		    << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS)) /**< \ \ \ \           \
+								 LP_CTRL_RAMRET_SEL0 \
+								 \ \ \ \ Mask        \
+							       */
+#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS \
+	((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL0_DIS Value */
+#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS                                   \
+	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS                                  \
+	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS) /**< LP_CTRL_RAMRET_SEL0_DIS \
+						     \ \ \ \ Setting */
+#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN \
+	((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL0_EN Value */
+#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN                                   \
+	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN                                  \
+	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS) /**< LP_CTRL_RAMRET_SEL0_EN \
+						     \ \ \ \ Setting */
+
+#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS \
+	1 /**< LP_CTRL_RAMRET_SEL1 Position */
+#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1                                             \
+	((uint32_t)(0x1UL                                                            \
+		    << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS)) /**< \ \ \ \           \
+								 LP_CTRL_RAMRET_SEL1 \
+								 \ \ \ \ Mask        \
+							       */
+#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS \
+	((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL1_DIS Value */
+#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS                                   \
+	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS                                  \
+	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS) /**< LP_CTRL_RAMRET_SEL1_DIS \
+						     \ \ \ \ Setting */
+#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN \
+	((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL1_EN Value */
+#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN                                   \
+	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN                                  \
+	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS) /**< LP_CTRL_RAMRET_SEL1_EN \
+						     \ \ \ \ Setting */
+
+#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS \
+	2 /**< LP_CTRL_RAMRET_SEL2 Position */
+#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2                                             \
+	((uint32_t)(0x1UL                                                            \
+		    << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS)) /**< \ \ \ \           \
+								 LP_CTRL_RAMRET_SEL2 \
+								 \ \ \ \ Mask        \
+							       */
+#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS \
+	((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL2_DIS Value */
+#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS                                   \
+	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS                                  \
+	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS) /**< LP_CTRL_RAMRET_SEL2_DIS \
+						     \ \ \ \ Setting */
+#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN \
+	((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL2_EN Value */
+#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN                                   \
+	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN                                  \
+	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS) /**< LP_CTRL_RAMRET_SEL2_EN \
+						     \ \ \ \ Setting */
+
+#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS \
+	3 /**< LP_CTRL_RAMRET_SEL3 Position */
+#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3                                             \
+	((uint32_t)(0x1UL                                                            \
+		    << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS)) /**< \ \ \ \           \
+								 LP_CTRL_RAMRET_SEL3 \
+								 \ \ \ \ Mask        \
+							       */
+#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS \
+	((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL3_DIS Value */
+#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS                                   \
+	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS                                  \
+	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS) /**< LP_CTRL_RAMRET_SEL3_DIS \
+						     \ \ \ \ Setting */
+#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN \
+	((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL3_EN Value */
+#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN                                   \
+	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN                                  \
+	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS) /**< LP_CTRL_RAMRET_SEL3_EN \
+						     \ \ \ \ Setting */
+
+#define MXC_F_PWRSEQ_LP_CTRL_OVR_POS 4 /**< LP_CTRL_OVR Position */
+#define MXC_F_PWRSEQ_LP_CTRL_OVR                                             \
+	((uint32_t)(0x3UL << MXC_F_PWRSEQ_LP_CTRL_OVR_POS)) /**< LP_CTRL_OVR \
+							       Mask */
+#define MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V \
+	((uint32_t)0x0UL) /**< LP_CTRL_OVR_0_9V Value */
+#define MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V                         \
+	(MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V                        \
+	 << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**<                \
+					     LP_CTRL_OVR_0_9V \
+					     Setting          \
+					   */
+#define MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V \
+	((uint32_t)0x1UL) /**< LP_CTRL_OVR_1_0V Value */
+#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V                         \
+	(MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V                        \
+	 << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**<                \
+					     LP_CTRL_OVR_1_0V \
+					     Setting          \
+					   */
+#define MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V \
+	((uint32_t)0x2UL) /**< LP_CTRL_OVR_1_1V Value */
+#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_1V                         \
+	(MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V                        \
+	 << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**<                \
+					     LP_CTRL_OVR_1_1V \
+					     Setting          \
+					   */
+
+#define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS \
+	6 /**< LP_CTRL_VCORE_DET_BYPASS Position */
+#define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS                                                  \
+	((uint32_t)(0x1UL                                                                      \
+		    << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS)) /**<                        \
+								      \ \ \ \                  \
+								      LP_CTRL_VCORE_DET_BYPASS \
+								      \                        \
+								      \ \ \ \                  \
+								      Mask */
+#define MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED \
+	((uint32_t)0x0UL) /**< LP_CTRL_VCORE_DET_BYPASS_ENABLED Value */
+#define MXC_S_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED                                      \
+	(MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED                                     \
+	 << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS) /**< \ \ \ \                        \
+							  LP_CTRL_VCORE_DET_BYPASS_ENABLED \
+							  \ \ \ \ Setting */
+#define MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE \
+	((uint32_t)0x1UL) /**< LP_CTRL_VCORE_DET_BYPASS_DISABLE Value */
+#define MXC_S_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE                                      \
+	(MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE                                     \
+	 << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS) /**< \ \ \ \                        \
+							  LP_CTRL_VCORE_DET_BYPASS_DISABLE \
+							  \ \ \ \ Setting */
+
+#define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS          \
+	8 /**< LP_CTRL_RETREG_EN Position   \ \ \ \ \
+	   */
+#define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN                                           \
+	((uint32_t)(0x1UL                                                        \
+		    << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS)) /**<                 \
+							       LP_CTRL_RETREG_EN \
+							       \ \ \ \ Mask */
+#define MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_DIS \
+	((uint32_t)0x0UL) /**< LP_CTRL_RETREG_EN_DIS Value */
+#define MXC_S_PWRSEQ_LP_CTRL_RETREG_EN_DIS                                     \
+	(MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_DIS                                    \
+	 << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS) /**< LP_CTRL_RETREG_EN_DIS \ \ \
+						   \ \ Setting */
+#define MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_EN \
+	((uint32_t)0x1UL) /**< LP_CTRL_RETREG_EN_EN Value */
+#define MXC_S_PWRSEQ_LP_CTRL_RETREG_EN_EN                                     \
+	(MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_EN                                    \
+	 << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS) /**< LP_CTRL_RETREG_EN_EN \ \ \
+						   \ \ Setting */
+
+#define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS \
+	10 /**< LP_CTRL_FAST_WK_EN Position */
+#define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN                                            \
+	((uint32_t)(0x1UL                                                          \
+		    << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS)) /**< \ \ \ \          \
+								LP_CTRL_FAST_WK_EN \
+								\ \ \ \ Mask       \
+							      */
+#define MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS \
+	((uint32_t)0x0UL) /**< LP_CTRL_FAST_WK_EN_DIS Value */
+#define MXC_S_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS                                    \
+	(MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS                                   \
+	 << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS) /**< LP_CTRL_FAST_WK_EN_DIS \ \
+						    \ \ \ Setting */
+#define MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_EN \
+	((uint32_t)0x1UL) /**< LP_CTRL_FAST_WK_EN_EN Value */
+#define MXC_S_PWRSEQ_LP_CTRL_FAST_WK_EN_EN                                    \
+	(MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_EN                                   \
+	 << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS) /**< LP_CTRL_FAST_WK_EN_EN \ \
+						    \ \ \ Setting */
+
+#define MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS 11 /**< LP_CTRL_BG_OFF Position */
+#define MXC_F_PWRSEQ_LP_CTRL_BG_OFF                                          \
+	((uint32_t)(0x1UL                                                    \
+		    << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS)) /**< LP_CTRL_BG_OFF \
+							    \ \ \ \ Mask */
+#define MXC_V_PWRSEQ_LP_CTRL_BG_OFF_ON \
+	((uint32_t)0x0UL) /**< LP_CTRL_BG_OFF_ON Value */
+#define MXC_S_PWRSEQ_LP_CTRL_BG_OFF_ON  \
+	(MXC_V_PWRSEQ_LP_CTRL_BG_OFF_ON \
+	 << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS) /**< LP_CTRL_BG_OFF_ON Setting */
+#define MXC_V_PWRSEQ_LP_CTRL_BG_OFF_OFF \
+	((uint32_t)0x1UL) /**< LP_CTRL_BG_OFF_OFF Value */
+#define MXC_S_PWRSEQ_LP_CTRL_BG_OFF_OFF                                        \
+	(MXC_V_PWRSEQ_LP_CTRL_BG_OFF_OFF                                       \
+	 << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS) /**< LP_CTRL_BG_OFF_OFF Setting \ \
+					      * \                              \
+					      * \ \                            \
+					      * \ \ \                          \
+					      */
+
+#define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS \
+	12 /**< LP_CTRL_VCORE_POR_DIS Position */
+#define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS                                               \
+	((uint32_t)(0x1UL                                                                \
+		    << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS)) /**< \ \ \ \             \
+								   LP_CTRL_VCORE_POR_DIS \
+								   \ \ \ \ Mask          \
+								 */
+#define MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS \
+	((uint32_t)0x0UL) /**< LP_CTRL_VCORE_POR_DIS_DIS Value */
+#define MXC_S_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS                                   \
+	(MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS                                  \
+	 << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS) /**< \ \ \ \                 \
+						       LP_CTRL_VCORE_POR_DIS_DIS \
+						       \ \ \ \ Setting */
+#define MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN \
+	((uint32_t)0x1UL) /**< LP_CTRL_VCORE_POR_DIS_EN Value */
+#define MXC_S_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN                                   \
+	(MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN                                  \
+	 << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS) /**< \ \ \ \                \
+						       LP_CTRL_VCORE_POR_DIS_EN \
+						       \ \ \ \ Setting */
+
+#define MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS 16 /**< LP_CTRL_LDO_DIS Position */
+#define MXC_F_PWRSEQ_LP_CTRL_LDO_DIS                                           \
+	((uint32_t)(0x1UL                                                      \
+		    << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS)) /**< LP_CTRL_LDO_DIS \
+							     \ \ \ \ Mask */
+#define MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_EN \
+	((uint32_t)0x0UL) /**< LP_CTRL_LDO_DIS_EN Value */
+#define MXC_S_PWRSEQ_LP_CTRL_LDO_DIS_EN                                       \
+	(MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_EN                                      \
+	 << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS) /**< LP_CTRL_LDO_DIS_EN Setting \
+					       * \                            \
+					       * \ \                          \
+					       * \ \ \                        \
+					       * \ \ \ \                      \
+					       */
+#define MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_DIS \
+	((uint32_t)0x1UL) /**< LP_CTRL_LDO_DIS_DIS Value */
+#define MXC_S_PWRSEQ_LP_CTRL_LDO_DIS_DIS                                       \
+	(MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_DIS                                      \
+	 << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS) /**< LP_CTRL_LDO_DIS_DIS Setting \
+					       * \                             \
+					       * \ \                           \
+					       * \ \ \                         \
+					       * \ \ \ \                       \
+					       */
+
+#define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS \
+	20 /**< LP_CTRL_VCORE_SVM_DIS Position */
+#define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS                                               \
+	((uint32_t)(0x1UL                                                                \
+		    << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS)) /**< \ \ \ \             \
+								   LP_CTRL_VCORE_SVM_DIS \
+								   \ \ \ \ Mask          \
+								 */
+#define MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN \
+	((uint32_t)0x0UL) /**< LP_CTRL_VCORE_SVM_DIS_EN Value */
+#define MXC_S_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN                                   \
+	(MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN                                  \
+	 << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS) /**< \ \ \ \                \
+						       LP_CTRL_VCORE_SVM_DIS_EN \
+						       \ \ \ \ Setting */
+#define MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS \
+	((uint32_t)0x1UL) /**< LP_CTRL_VCORE_SVM_DIS_DIS Value */
+#define MXC_S_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS                                   \
+	(MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS                                  \
+	 << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS) /**< \ \ \ \                 \
+						       LP_CTRL_VCORE_SVM_DIS_DIS \
+						       \ \ \ \ Setting */
+
+#define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS \
+	25 /**< LP_CTRL_VDDIO_POR_DIS Position */
+#define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS                                               \
+	((uint32_t)(0x1UL                                                                \
+		    << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS)) /**< \ \ \ \             \
+								   LP_CTRL_VDDIO_POR_DIS \
+								   \ \ \ \ Mask          \
+								 */
+#define MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN \
+	((uint32_t)0x0UL) /**< LP_CTRL_VDDIO_POR_DIS_EN Value */
+#define MXC_S_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN                                   \
+	(MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN                                  \
+	 << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS) /**< \ \ \ \                \
+						       LP_CTRL_VDDIO_POR_DIS_EN \
+						       \ \ \ \ Setting */
+#define MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS \
+	((uint32_t)0x1UL) /**< LP_CTRL_VDDIO_POR_DIS_DIS Value */
+#define MXC_S_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS                                   \
+	(MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS                                  \
+	 << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS) /**< \ \ \ \                 \
+						       LP_CTRL_VDDIO_POR_DIS_DIS \
+						       \ \ \ \ Setting */
+
+/**
+ * pwrseq_registers
+ * Low Power Mode Wakeup Flags for GPIO0
+ */
+#define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS 0 /**< LP_WAKEFL_WAKEST Position */
+#define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST                                          \
+	((uint32_t)(0x3FFFUL                                                   \
+		    << MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS)) /**<                \
+							      LP_WAKEFL_WAKEST \
+							      \                \
+							      \ \ \ Mask       \
+							    */
+
+/**
+ * pwrseq_registers
+ * Low Power I/O Wakeup Enable Register 0. This register enables low
+ * power wakeup functionality for GPIO0.
+ */
+#define MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS 0 /**< LPWK_EN_WAKEEN Position */
+#define MXC_F_PWRSEQ_LPWK_EN_WAKEEN                                        \
+	((uint32_t)(0x3FFFUL                                               \
+		    << MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS)) /**<              \
+							    LPWK_EN_WAKEEN \
+							    \              \
+							    \ \ \ Mask     \
+							  */
+
+/**
+ * pwrseq_registers
+ * Low Power Memory Shutdown Control.
+ */
+#define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS          \
+	0 /**< LPMEMSD_SRAM0_OFF Position   \ \ \ \ \
+	   */
+#define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF                                           \
+	((uint32_t)(0x1UL                                                        \
+		    << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS)) /**<                 \
+							       LPMEMSD_SRAM0_OFF \
+							       \ \ \ \ Mask */
+#define MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL \
+	((uint32_t)0x0UL) /**< LPMEMSD_SRAM0_OFF_NORMAL Value */
+#define MXC_S_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL                                 \
+	(MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL                                \
+	 << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS) /**< LPMEMSD_SRAM0_OFF_NORMAL \
+						   \ \ \ \ Setting */
+#define MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN \
+	((uint32_t)0x1UL) /**< LPMEMSD_SRAM0_OFF_SHUTDOWN Value */
+#define MXC_S_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN                               \
+	(MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN                              \
+	 << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS) /**< \ \ \ \                  \
+						   LPMEMSD_SRAM0_OFF_SHUTDOWN \
+						   \ \ \ \ Setting */
+
+#define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS          \
+	1 /**< LPMEMSD_SRAM1_OFF Position   \ \ \ \ \
+	   */
+#define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF                                           \
+	((uint32_t)(0x1UL                                                        \
+		    << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS)) /**<                 \
+							       LPMEMSD_SRAM1_OFF \
+							       \ \ \ \ Mask */
+#define MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL \
+	((uint32_t)0x0UL) /**< LPMEMSD_SRAM1_OFF_NORMAL Value */
+#define MXC_S_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL                                 \
+	(MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL                                \
+	 << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS) /**< LPMEMSD_SRAM1_OFF_NORMAL \
+						   \ \ \ \ Setting */
+#define MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN \
+	((uint32_t)0x1UL) /**< LPMEMSD_SRAM1_OFF_SHUTDOWN Value */
+#define MXC_S_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN                               \
+	(MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN                              \
+	 << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS) /**< \ \ \ \                  \
+						   LPMEMSD_SRAM1_OFF_SHUTDOWN \
+						   \ \ \ \ Setting */
+
+#define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS          \
+	2 /**< LPMEMSD_SRAM2_OFF Position   \ \ \ \ \
+	   */
+#define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF                                           \
+	((uint32_t)(0x1UL                                                        \
+		    << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS)) /**<                 \
+							       LPMEMSD_SRAM2_OFF \
+							       \ \ \ \ Mask */
+#define MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL \
+	((uint32_t)0x0UL) /**< LPMEMSD_SRAM2_OFF_NORMAL Value */
+#define MXC_S_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL                                 \
+	(MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL                                \
+	 << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS) /**< LPMEMSD_SRAM2_OFF_NORMAL \
+						   \ \ \ \ Setting */
+#define MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN \
+	((uint32_t)0x1UL) /**< LPMEMSD_SRAM2_OFF_SHUTDOWN Value */
+#define MXC_S_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN                               \
+	(MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN                              \
+	 << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS) /**< \ \ \ \                  \
+						   LPMEMSD_SRAM2_OFF_SHUTDOWN \
+						   \ \ \ \ Setting */
+
+#define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS          \
+	3 /**< LPMEMSD_SRAM3_OFF Position   \ \ \ \ \
+	   */
+#define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF                                           \
+	((uint32_t)(0x1UL                                                        \
+		    << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS)) /**<                 \
+							       LPMEMSD_SRAM3_OFF \
+							       \ \ \ \ Mask */
+#define MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL \
+	((uint32_t)0x0UL) /**< LPMEMSD_SRAM3_OFF_NORMAL Value */
+#define MXC_S_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL                                 \
+	(MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL                                \
+	 << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS) /**< LPMEMSD_SRAM3_OFF_NORMAL \
+						   \ \ \ \ Setting */
+#define MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN \
+	((uint32_t)0x1UL) /**< LPMEMSD_SRAM3_OFF_SHUTDOWN Value */
+#define MXC_S_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN                               \
+	(MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN                              \
+	 << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS) /**< \ \ \ \                  \
+						   LPMEMSD_SRAM3_OFF_SHUTDOWN \
+						   \ \ \ \ Setting */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _PWRSEQ_REGS_H_ */
diff --git a/chip/max32660/registers.h b/chip/max32660/registers.h
index e444888fa0..72118bf744 100644
--- a/chip/max32660/registers.h
+++ b/chip/max32660/registers.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -72,9 +72,8 @@
 
 extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)  */
 #ifndef PeripheralClock
-#define PeripheralClock    \
-	(SystemCoreClock / \
-	 2) /*!< Peripheral Clock Frequency                  \
+#define PeripheralClock                                       \
+	(SystemCoreClock / 2) /*!< Peripheral Clock Frequency \
 			       */
 #endif
 
@@ -173,14 +172,17 @@ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)  */
 #define MXC_BASE_TMR2 ((uint32_t)0x40012000UL)
 #define MXC_TMR2 ((mxc_tmr_regs_t *)MXC_BASE_TMR2)
 
-#define MXC_TMR_GET_IRQ(i)              \
-	(IRQn_Type)((i) == 0 ?          \
-			    TMR0_IRQn : \
-			    (i) == 1 ? TMR1_IRQn : (i) == 2 ? TMR2_IRQn : 0)
+#define MXC_TMR_GET_IRQ(i)                 \
+	(IRQn_Type)((i) == 0 ? TMR0_IRQn : \
+		    (i) == 1 ? TMR1_IRQn : \
+		    (i) == 2 ? TMR2_IRQn : \
+			       0)
 
 #define MXC_TMR_GET_BASE(i)         \
 	((i) == 0 ? MXC_BASE_TMR0 : \
-		    (i) == 1 ? MXC_BASE_TMR1 : (i) == 2 ? MXC_BASE_TMR2 : 0)
+	 (i) == 1 ? MXC_BASE_TMR1 : \
+	 (i) == 2 ? MXC_BASE_TMR2 : \
+		    0)
 
 #define MXC_TMR_GET_TMR(i) \
 	((i) == 0 ? MXC_TMR0 : (i) == 1 ? MXC_TMR1 : (i) == 2 ? MXC_TMR2 : 0)
diff --git a/chip/max32660/system_chip.c b/chip/max32660/system_chip.c
index 07127dc8c5..f63e22dc26 100644
--- a/chip/max32660/system_chip.c
+++ b/chip/max32660/system_chip.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,14 +9,14 @@
 #include "common.h"
 #include "console.h"
 #include "cpu.h"
+#include "gcr_regs.h"
 #include "host_command.h"
 #include "panic.h"
+#include "registers.h"
 #include "system.h"
 #include "task.h"
 #include "timer.h"
 #include "util.h"
-#include "registers.h"
-#include "gcr_regs.h"
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
diff --git a/chip/max32660/tmr_regs.h b/chip/max32660/tmr_regs.h
index 946cacbc50..ab3ac5c5ed 100644
--- a/chip/max32660/tmr_regs.h
+++ b/chip/max32660/tmr_regs.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -42,11 +42,11 @@ extern "C" {
  * Structure type to access the TMR Registers.
  */
 typedef struct {
-	__IO uint32_t cnt;    /**< <tt>\b 0x00:<\tt> TMR CNT Register */
-	__IO uint32_t cmp;    /**< <tt>\b 0x04:<\tt> TMR CMP Register */
-	__IO uint32_t pwm;    /**< <tt>\b 0x08:<\tt> TMR PWM Register */
-	__IO uint32_t intr;   /**< <tt>\b 0x0C:<\tt> TMR INTR Register */
-	__IO uint32_t cn;     /**< <tt>\b 0x10:<\tt> TMR CN Register */
+	__IO uint32_t cnt; /**< <tt>\b 0x00:<\tt> TMR CNT Register */
+	__IO uint32_t cmp; /**< <tt>\b 0x04:<\tt> TMR CMP Register */
+	__IO uint32_t pwm; /**< <tt>\b 0x08:<\tt> TMR PWM Register */
+	__IO uint32_t intr; /**< <tt>\b 0x0C:<\tt> TMR INTR Register */
+	__IO uint32_t cn; /**< <tt>\b 0x10:<\tt> TMR CN Register */
 	__IO uint32_t nolcmp; /**< <tt>\b 0x14:<\tt> TMR NOLCMP Register */
 } mxc_tmr_regs_t;
 
@@ -54,23 +54,23 @@ typedef struct {
  * TMR Peripheral Register Offsets from the TMR Base Peripheral
  * Address.
  */
-#define MXC_R_TMR_CNT                                                          \
-	((uint32_t)0x00000000UL) /**< Offset from TMR Base Address: <tt>       \
+#define MXC_R_TMR_CNT                                                    \
+	((uint32_t)0x00000000UL) /**< Offset from TMR Base Address: <tt> \
 				    0x0x000 */
-#define MXC_R_TMR_CMP                                                          \
-	((uint32_t)0x00000004UL) /**< Offset from TMR Base Address: <tt>       \
+#define MXC_R_TMR_CMP                                                    \
+	((uint32_t)0x00000004UL) /**< Offset from TMR Base Address: <tt> \
 				    0x0x004 */
-#define MXC_R_TMR_PWM                                                          \
-	((uint32_t)0x00000008UL) /**< Offset from TMR Base Address: <tt>       \
+#define MXC_R_TMR_PWM                                                    \
+	((uint32_t)0x00000008UL) /**< Offset from TMR Base Address: <tt> \
 				    0x0x008 */
-#define MXC_R_TMR_INTR                                                         \
-	((uint32_t)0x0000000CUL) /**< Offset from TMR Base Address: <tt>       \
+#define MXC_R_TMR_INTR                                                   \
+	((uint32_t)0x0000000CUL) /**< Offset from TMR Base Address: <tt> \
 				    0x0x00C */
-#define MXC_R_TMR_CN                                                           \
-	((uint32_t)0x00000010UL) /**< Offset from TMR Base Address: <tt>       \
+#define MXC_R_TMR_CN                                                     \
+	((uint32_t)0x00000010UL) /**< Offset from TMR Base Address: <tt> \
 				    0x0x010 */
-#define MXC_R_TMR_NOLCMP                                                       \
-	((uint32_t)0x00000014UL) /**< Offset from TMR Base Address: <tt>       \
+#define MXC_R_TMR_NOLCMP                                                 \
+	((uint32_t)0x00000014UL) /**< Offset from TMR Base Address: <tt> \
 				    0x0x014 */
 
 /**
@@ -78,199 +78,231 @@ typedef struct {
  * clears the associated interrupt.
  */
 #define MXC_F_TMR_INTR_IRQ_CLR_POS 0 /**< INTR_IRQ_CLR Position */
-#define MXC_F_TMR_INTR_IRQ_CLR                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_TMR_INTR_IRQ_CLR_POS)) /**< INTR_IRQ_CLR Mask */
+#define MXC_F_TMR_INTR_IRQ_CLR                                              \
+	((uint32_t)(0x1UL << MXC_F_TMR_INTR_IRQ_CLR_POS)) /**< INTR_IRQ_CLR \
+							     Mask */
 
 /**
  * Timer Control Register.
  */
 #define MXC_F_TMR_CN_TMODE_POS 0 /**< CN_TMODE Position */
-#define MXC_F_TMR_CN_TMODE                                                     \
+#define MXC_F_TMR_CN_TMODE \
 	((uint32_t)(0x7UL << MXC_F_TMR_CN_TMODE_POS)) /**< CN_TMODE Mask */
-#define MXC_V_TMR_CN_TMODE_ONESHOT                                             \
+#define MXC_V_TMR_CN_TMODE_ONESHOT \
 	((uint32_t)0x0UL) /**< CN_TMODE_ONESHOT Value */
-#define MXC_S_TMR_CN_TMODE_ONESHOT                                             \
-	(MXC_V_TMR_CN_TMODE_ONESHOT                                            \
-	 << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_ONESHOT Setting */
-#define MXC_V_TMR_CN_TMODE_CONTINUOUS                                          \
+#define MXC_S_TMR_CN_TMODE_ONESHOT                      \
+	(MXC_V_TMR_CN_TMODE_ONESHOT                     \
+	 << MXC_F_TMR_CN_TMODE_POS) /**<                \
+				       CN_TMODE_ONESHOT \
+				       Setting */
+#define MXC_V_TMR_CN_TMODE_CONTINUOUS \
 	((uint32_t)0x1UL) /**< CN_TMODE_CONTINUOUS Value */
-#define MXC_S_TMR_CN_TMODE_CONTINUOUS                                          \
-	(MXC_V_TMR_CN_TMODE_CONTINUOUS                                         \
-	 << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CONTINUOUS Setting */
-#define MXC_V_TMR_CN_TMODE_COUNTER                                             \
+#define MXC_S_TMR_CN_TMODE_CONTINUOUS                      \
+	(MXC_V_TMR_CN_TMODE_CONTINUOUS                     \
+	 << MXC_F_TMR_CN_TMODE_POS) /**<                   \
+				       CN_TMODE_CONTINUOUS \
+				       Setting             \
+				     */
+#define MXC_V_TMR_CN_TMODE_COUNTER \
 	((uint32_t)0x2UL) /**< CN_TMODE_COUNTER Value */
-#define MXC_S_TMR_CN_TMODE_COUNTER                                             \
-	(MXC_V_TMR_CN_TMODE_COUNTER                                            \
-	 << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_COUNTER Setting */
+#define MXC_S_TMR_CN_TMODE_COUNTER                      \
+	(MXC_V_TMR_CN_TMODE_COUNTER                     \
+	 << MXC_F_TMR_CN_TMODE_POS) /**<                \
+				       CN_TMODE_COUNTER \
+				       Setting */
 #define MXC_V_TMR_CN_TMODE_PWM ((uint32_t)0x3UL) /**< CN_TMODE_PWM Value */
-#define MXC_S_TMR_CN_TMODE_PWM                                                 \
-	(MXC_V_TMR_CN_TMODE_PWM                                                \
-	 << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_PWM Setting */
-#define MXC_V_TMR_CN_TMODE_CAPTURE                                             \
+#define MXC_S_TMR_CN_TMODE_PWM                                               \
+	(MXC_V_TMR_CN_TMODE_PWM << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_PWM \
+							      Setting */
+#define MXC_V_TMR_CN_TMODE_CAPTURE \
 	((uint32_t)0x4UL) /**< CN_TMODE_CAPTURE Value */
-#define MXC_S_TMR_CN_TMODE_CAPTURE                                             \
-	(MXC_V_TMR_CN_TMODE_CAPTURE                                            \
-	 << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CAPTURE Setting */
-#define MXC_V_TMR_CN_TMODE_COMPARE                                             \
+#define MXC_S_TMR_CN_TMODE_CAPTURE                      \
+	(MXC_V_TMR_CN_TMODE_CAPTURE                     \
+	 << MXC_F_TMR_CN_TMODE_POS) /**<                \
+				       CN_TMODE_CAPTURE \
+				       Setting */
+#define MXC_V_TMR_CN_TMODE_COMPARE \
 	((uint32_t)0x5UL) /**< CN_TMODE_COMPARE Value */
-#define MXC_S_TMR_CN_TMODE_COMPARE                                             \
-	(MXC_V_TMR_CN_TMODE_COMPARE                                            \
-	 << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_COMPARE Setting */
-#define MXC_V_TMR_CN_TMODE_GATED                                               \
-	((uint32_t)0x6UL) /**< CN_TMODE_GATED Value                            \
+#define MXC_S_TMR_CN_TMODE_COMPARE                      \
+	(MXC_V_TMR_CN_TMODE_COMPARE                     \
+	 << MXC_F_TMR_CN_TMODE_POS) /**<                \
+				       CN_TMODE_COMPARE \
+				       Setting */
+#define MXC_V_TMR_CN_TMODE_GATED                    \
+	((uint32_t)0x6UL) /**< CN_TMODE_GATED Value \
 			   */
 #define MXC_S_TMR_CN_TMODE_GATED                                               \
-	(MXC_V_TMR_CN_TMODE_GATED                                              \
-	 << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_GATED Setting */
-#define MXC_V_TMR_CN_TMODE_CAPTURECOMPARE                                      \
+	(MXC_V_TMR_CN_TMODE_GATED << MXC_F_TMR_CN_TMODE_POS) /**<              \
+								CN_TMODE_GATED \
+								Setting */
+#define MXC_V_TMR_CN_TMODE_CAPTURECOMPARE \
 	((uint32_t)0x7UL) /**< CN_TMODE_CAPTURECOMPARE Value */
-#define MXC_S_TMR_CN_TMODE_CAPTURECOMPARE                                      \
-	(MXC_V_TMR_CN_TMODE_CAPTURECOMPARE                                     \
-	 << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CAPTURECOMPARE Setting */
+#define MXC_S_TMR_CN_TMODE_CAPTURECOMPARE                      \
+	(MXC_V_TMR_CN_TMODE_CAPTURECOMPARE                     \
+	 << MXC_F_TMR_CN_TMODE_POS) /**<                       \
+				       CN_TMODE_CAPTURECOMPARE \
+				       Setting                 \
+				     */
 
 #define MXC_F_TMR_CN_PRES_POS 3 /**< CN_PRES Position */
-#define MXC_F_TMR_CN_PRES                                                      \
+#define MXC_F_TMR_CN_PRES \
 	((uint32_t)(0x7UL << MXC_F_TMR_CN_PRES_POS)) /**< CN_PRES Mask */
-#define MXC_V_TMR_CN_PRES_DIV1 ((uint32_t)0x0UL)     /**< CN_PRES_DIV1 Value */
-#define MXC_S_TMR_CN_PRES_DIV1                                                 \
-	(MXC_V_TMR_CN_PRES_DIV1                                                \
-	 << MXC_F_TMR_CN_PRES_POS)		 /**< CN_PRES_DIV1 Setting */
+#define MXC_V_TMR_CN_PRES_DIV1 ((uint32_t)0x0UL) /**< CN_PRES_DIV1 Value */
+#define MXC_S_TMR_CN_PRES_DIV1                                              \
+	(MXC_V_TMR_CN_PRES_DIV1 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV1 \
+							     Setting */
 #define MXC_V_TMR_CN_PRES_DIV2 ((uint32_t)0x1UL) /**< CN_PRES_DIV2 Value */
-#define MXC_S_TMR_CN_PRES_DIV2                                                 \
-	(MXC_V_TMR_CN_PRES_DIV2                                                \
-	 << MXC_F_TMR_CN_PRES_POS)		 /**< CN_PRES_DIV2 Setting */
+#define MXC_S_TMR_CN_PRES_DIV2                                              \
+	(MXC_V_TMR_CN_PRES_DIV2 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV2 \
+							     Setting */
 #define MXC_V_TMR_CN_PRES_DIV4 ((uint32_t)0x2UL) /**< CN_PRES_DIV4 Value */
-#define MXC_S_TMR_CN_PRES_DIV4                                                 \
-	(MXC_V_TMR_CN_PRES_DIV4                                                \
-	 << MXC_F_TMR_CN_PRES_POS)		 /**< CN_PRES_DIV4 Setting */
+#define MXC_S_TMR_CN_PRES_DIV4                                              \
+	(MXC_V_TMR_CN_PRES_DIV4 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV4 \
+							     Setting */
 #define MXC_V_TMR_CN_PRES_DIV8 ((uint32_t)0x3UL) /**< CN_PRES_DIV8 Value */
-#define MXC_S_TMR_CN_PRES_DIV8                                                 \
-	(MXC_V_TMR_CN_PRES_DIV8                                                \
-	 << MXC_F_TMR_CN_PRES_POS)		  /**< CN_PRES_DIV8 Setting */
+#define MXC_S_TMR_CN_PRES_DIV8                                              \
+	(MXC_V_TMR_CN_PRES_DIV8 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV8 \
+							     Setting */
 #define MXC_V_TMR_CN_PRES_DIV16 ((uint32_t)0x4UL) /**< CN_PRES_DIV16 Value */
-#define MXC_S_TMR_CN_PRES_DIV16                                                \
-	(MXC_V_TMR_CN_PRES_DIV16                                               \
-	 << MXC_F_TMR_CN_PRES_POS)		  /**< CN_PRES_DIV16 Setting */
+#define MXC_S_TMR_CN_PRES_DIV16                                               \
+	(MXC_V_TMR_CN_PRES_DIV16 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV16 \
+							      Setting */
 #define MXC_V_TMR_CN_PRES_DIV32 ((uint32_t)0x5UL) /**< CN_PRES_DIV32 Value */
-#define MXC_S_TMR_CN_PRES_DIV32                                                \
-	(MXC_V_TMR_CN_PRES_DIV32                                               \
-	 << MXC_F_TMR_CN_PRES_POS)		  /**< CN_PRES_DIV32 Setting */
+#define MXC_S_TMR_CN_PRES_DIV32                                               \
+	(MXC_V_TMR_CN_PRES_DIV32 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV32 \
+							      Setting */
 #define MXC_V_TMR_CN_PRES_DIV64 ((uint32_t)0x6UL) /**< CN_PRES_DIV64 Value */
-#define MXC_S_TMR_CN_PRES_DIV64                                                \
-	(MXC_V_TMR_CN_PRES_DIV64                                               \
-	 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV64 Setting */
-#define MXC_V_TMR_CN_PRES_DIV128                                               \
-	((uint32_t)0x7UL) /**< CN_PRES_DIV128 Value                            \
+#define MXC_S_TMR_CN_PRES_DIV64                                               \
+	(MXC_V_TMR_CN_PRES_DIV64 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV64 \
+							      Setting */
+#define MXC_V_TMR_CN_PRES_DIV128                    \
+	((uint32_t)0x7UL) /**< CN_PRES_DIV128 Value \
 			   */
-#define MXC_S_TMR_CN_PRES_DIV128                                               \
-	(MXC_V_TMR_CN_PRES_DIV128                                              \
-	 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV128 Setting */
+#define MXC_S_TMR_CN_PRES_DIV128                                              \
+	(MXC_V_TMR_CN_PRES_DIV128 << MXC_F_TMR_CN_PRES_POS) /**<              \
+							       CN_PRES_DIV128 \
+							       Setting */
 
 #define MXC_F_TMR_CN_TPOL_POS 6 /**< CN_TPOL Position */
-#define MXC_F_TMR_CN_TPOL                                                      \
+#define MXC_F_TMR_CN_TPOL \
 	((uint32_t)(0x1UL << MXC_F_TMR_CN_TPOL_POS)) /**< CN_TPOL Mask */
-#define MXC_V_TMR_CN_TPOL_ACTIVEHI                                             \
+#define MXC_V_TMR_CN_TPOL_ACTIVEHI \
 	((uint32_t)0x0UL) /**< CN_TPOL_ACTIVEHI Value */
-#define MXC_S_TMR_CN_TPOL_ACTIVEHI                                             \
-	(MXC_V_TMR_CN_TPOL_ACTIVEHI                                            \
-	 << MXC_F_TMR_CN_TPOL_POS) /**< CN_TPOL_ACTIVEHI Setting */
-#define MXC_V_TMR_CN_TPOL_ACTIVELO                                             \
+#define MXC_S_TMR_CN_TPOL_ACTIVEHI                     \
+	(MXC_V_TMR_CN_TPOL_ACTIVEHI                    \
+	 << MXC_F_TMR_CN_TPOL_POS) /**<                \
+				      CN_TPOL_ACTIVEHI \
+				      Setting */
+#define MXC_V_TMR_CN_TPOL_ACTIVELO \
 	((uint32_t)0x1UL) /**< CN_TPOL_ACTIVELO Value */
-#define MXC_S_TMR_CN_TPOL_ACTIVELO                                             \
-	(MXC_V_TMR_CN_TPOL_ACTIVELO                                            \
-	 << MXC_F_TMR_CN_TPOL_POS) /**< CN_TPOL_ACTIVELO Setting */
+#define MXC_S_TMR_CN_TPOL_ACTIVELO                     \
+	(MXC_V_TMR_CN_TPOL_ACTIVELO                    \
+	 << MXC_F_TMR_CN_TPOL_POS) /**<                \
+				      CN_TPOL_ACTIVELO \
+				      Setting */
 
 #define MXC_F_TMR_CN_TEN_POS 7 /**< CN_TEN Position */
-#define MXC_F_TMR_CN_TEN                                                       \
+#define MXC_F_TMR_CN_TEN \
 	((uint32_t)(0x1UL << MXC_F_TMR_CN_TEN_POS)) /**< CN_TEN Mask */
-#define MXC_V_TMR_CN_TEN_DIS ((uint32_t)0x0UL)      /**< CN_TEN_DIS Value */
+#define MXC_V_TMR_CN_TEN_DIS ((uint32_t)0x0UL) /**< CN_TEN_DIS Value */
 #define MXC_S_TMR_CN_TEN_DIS                                                   \
-	(MXC_V_TMR_CN_TEN_DIS                                                  \
-	 << MXC_F_TMR_CN_TEN_POS)	     /**< CN_TEN_DIS Setting */
+	(MXC_V_TMR_CN_TEN_DIS << MXC_F_TMR_CN_TEN_POS) /**< CN_TEN_DIS Setting \
+							*/
 #define MXC_V_TMR_CN_TEN_EN ((uint32_t)0x1UL) /**< CN_TEN_EN Value */
-#define MXC_S_TMR_CN_TEN_EN                                                    \
-	(MXC_V_TMR_CN_TEN_EN << MXC_F_TMR_CN_TEN_POS) /**< CN_TEN_EN Setting   \
+#define MXC_S_TMR_CN_TEN_EN                                                  \
+	(MXC_V_TMR_CN_TEN_EN << MXC_F_TMR_CN_TEN_POS) /**< CN_TEN_EN Setting \
 						       */
 
 #define MXC_F_TMR_CN_PRES3_POS 8 /**< CN_PRES3 Position */
-#define MXC_F_TMR_CN_PRES3                                                     \
+#define MXC_F_TMR_CN_PRES3 \
 	((uint32_t)(0x1UL << MXC_F_TMR_CN_PRES3_POS)) /**< CN_PRES3 Mask */
 
 #define MXC_F_TMR_CN_PWMSYNC_POS 9 /**< CN_PWMSYNC Position */
-#define MXC_F_TMR_CN_PWMSYNC                                                   \
-	((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMSYNC_POS)) /**< CN_PWMSYNC Mask   \
+#define MXC_F_TMR_CN_PWMSYNC                                                 \
+	((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMSYNC_POS)) /**< CN_PWMSYNC Mask \
 							 */
-#define MXC_V_TMR_CN_PWMSYNC_DIS                                               \
-	((uint32_t)0x0UL) /**< CN_PWMSYNC_DIS Value                            \
+#define MXC_V_TMR_CN_PWMSYNC_DIS                    \
+	((uint32_t)0x0UL) /**< CN_PWMSYNC_DIS Value \
 			   */
-#define MXC_S_TMR_CN_PWMSYNC_DIS                                               \
-	(MXC_V_TMR_CN_PWMSYNC_DIS                                              \
-	 << MXC_F_TMR_CN_PWMSYNC_POS)		  /**< CN_PWMSYNC_DIS Setting */
+#define MXC_S_TMR_CN_PWMSYNC_DIS                        \
+	(MXC_V_TMR_CN_PWMSYNC_DIS                       \
+	 << MXC_F_TMR_CN_PWMSYNC_POS) /**<              \
+					 CN_PWMSYNC_DIS \
+					 Setting */
 #define MXC_V_TMR_CN_PWMSYNC_EN ((uint32_t)0x1UL) /**< CN_PWMSYNC_EN Value */
 #define MXC_S_TMR_CN_PWMSYNC_EN                                                \
-	(MXC_V_TMR_CN_PWMSYNC_EN                                               \
-	 << MXC_F_TMR_CN_PWMSYNC_POS) /**< CN_PWMSYNC_EN Setting */
+	(MXC_V_TMR_CN_PWMSYNC_EN << MXC_F_TMR_CN_PWMSYNC_POS) /**<             \
+								 CN_PWMSYNC_EN \
+								 Setting */
 
 #define MXC_F_TMR_CN_NOLHPOL_POS 10 /**< CN_NOLHPOL Position */
-#define MXC_F_TMR_CN_NOLHPOL                                                   \
-	((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLHPOL_POS)) /**< CN_NOLHPOL Mask   \
+#define MXC_F_TMR_CN_NOLHPOL                                                 \
+	((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLHPOL_POS)) /**< CN_NOLHPOL Mask \
 							 */
-#define MXC_V_TMR_CN_NOLHPOL_DIS                                               \
-	((uint32_t)0x0UL) /**< CN_NOLHPOL_DIS Value                            \
+#define MXC_V_TMR_CN_NOLHPOL_DIS                    \
+	((uint32_t)0x0UL) /**< CN_NOLHPOL_DIS Value \
 			   */
-#define MXC_S_TMR_CN_NOLHPOL_DIS                                               \
-	(MXC_V_TMR_CN_NOLHPOL_DIS                                              \
-	 << MXC_F_TMR_CN_NOLHPOL_POS)		  /**< CN_NOLHPOL_DIS Setting */
+#define MXC_S_TMR_CN_NOLHPOL_DIS                        \
+	(MXC_V_TMR_CN_NOLHPOL_DIS                       \
+	 << MXC_F_TMR_CN_NOLHPOL_POS) /**<              \
+					 CN_NOLHPOL_DIS \
+					 Setting */
 #define MXC_V_TMR_CN_NOLHPOL_EN ((uint32_t)0x1UL) /**< CN_NOLHPOL_EN Value */
 #define MXC_S_TMR_CN_NOLHPOL_EN                                                \
-	(MXC_V_TMR_CN_NOLHPOL_EN                                               \
-	 << MXC_F_TMR_CN_NOLHPOL_POS) /**< CN_NOLHPOL_EN Setting */
+	(MXC_V_TMR_CN_NOLHPOL_EN << MXC_F_TMR_CN_NOLHPOL_POS) /**<             \
+								 CN_NOLHPOL_EN \
+								 Setting */
 
 #define MXC_F_TMR_CN_NOLLPOL_POS 11 /**< CN_NOLLPOL Position */
-#define MXC_F_TMR_CN_NOLLPOL                                                   \
-	((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLLPOL_POS)) /**< CN_NOLLPOL Mask   \
+#define MXC_F_TMR_CN_NOLLPOL                                                 \
+	((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLLPOL_POS)) /**< CN_NOLLPOL Mask \
 							 */
-#define MXC_V_TMR_CN_NOLLPOL_DIS                                               \
-	((uint32_t)0x0UL) /**< CN_NOLLPOL_DIS Value                            \
+#define MXC_V_TMR_CN_NOLLPOL_DIS                    \
+	((uint32_t)0x0UL) /**< CN_NOLLPOL_DIS Value \
 			   */
-#define MXC_S_TMR_CN_NOLLPOL_DIS                                               \
-	(MXC_V_TMR_CN_NOLLPOL_DIS                                              \
-	 << MXC_F_TMR_CN_NOLLPOL_POS)		  /**< CN_NOLLPOL_DIS Setting */
+#define MXC_S_TMR_CN_NOLLPOL_DIS                        \
+	(MXC_V_TMR_CN_NOLLPOL_DIS                       \
+	 << MXC_F_TMR_CN_NOLLPOL_POS) /**<              \
+					 CN_NOLLPOL_DIS \
+					 Setting */
 #define MXC_V_TMR_CN_NOLLPOL_EN ((uint32_t)0x1UL) /**< CN_NOLLPOL_EN Value */
 #define MXC_S_TMR_CN_NOLLPOL_EN                                                \
-	(MXC_V_TMR_CN_NOLLPOL_EN                                               \
-	 << MXC_F_TMR_CN_NOLLPOL_POS) /**< CN_NOLLPOL_EN Setting */
+	(MXC_V_TMR_CN_NOLLPOL_EN << MXC_F_TMR_CN_NOLLPOL_POS) /**<             \
+								 CN_NOLLPOL_EN \
+								 Setting */
 
 #define MXC_F_TMR_CN_PWMCKBD_POS 12 /**< CN_PWMCKBD Position */
-#define MXC_F_TMR_CN_PWMCKBD                                                   \
-	((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMCKBD_POS)) /**< CN_PWMCKBD Mask   \
+#define MXC_F_TMR_CN_PWMCKBD                                                 \
+	((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMCKBD_POS)) /**< CN_PWMCKBD Mask \
 							 */
-#define MXC_V_TMR_CN_PWMCKBD_DIS                                               \
-	((uint32_t)0x1UL) /**< CN_PWMCKBD_DIS Value                            \
+#define MXC_V_TMR_CN_PWMCKBD_DIS                    \
+	((uint32_t)0x1UL) /**< CN_PWMCKBD_DIS Value \
 			   */
-#define MXC_S_TMR_CN_PWMCKBD_DIS                                               \
-	(MXC_V_TMR_CN_PWMCKBD_DIS                                              \
-	 << MXC_F_TMR_CN_PWMCKBD_POS)		  /**< CN_PWMCKBD_DIS Setting */
+#define MXC_S_TMR_CN_PWMCKBD_DIS                        \
+	(MXC_V_TMR_CN_PWMCKBD_DIS                       \
+	 << MXC_F_TMR_CN_PWMCKBD_POS) /**<              \
+					 CN_PWMCKBD_DIS \
+					 Setting */
 #define MXC_V_TMR_CN_PWMCKBD_EN ((uint32_t)0x0UL) /**< CN_PWMCKBD_EN Value */
 #define MXC_S_TMR_CN_PWMCKBD_EN                                                \
-	(MXC_V_TMR_CN_PWMCKBD_EN                                               \
-	 << MXC_F_TMR_CN_PWMCKBD_POS) /**< CN_PWMCKBD_EN Setting */
+	(MXC_V_TMR_CN_PWMCKBD_EN << MXC_F_TMR_CN_PWMCKBD_POS) /**<             \
+								 CN_PWMCKBD_EN \
+								 Setting */
 
 /**
  * Timer Non-Overlapping Compare Register.
  */
 #define MXC_F_TMR_NOLCMP_NOLLCMP_POS 0 /**< NOLCMP_NOLLCMP Position */
 #define MXC_F_TMR_NOLCMP_NOLLCMP                                               \
-	((uint32_t)(                                                           \
-		0xFFUL                                                         \
-		<< MXC_F_TMR_NOLCMP_NOLLCMP_POS)) /**< NOLCMP_NOLLCMP Mask */
+	((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_NOLLCMP_POS)) /**<              \
+								NOLCMP_NOLLCMP \
+								Mask */
 
 #define MXC_F_TMR_NOLCMP_NOLHCMP_POS 8 /**< NOLCMP_NOLHCMP Position */
 #define MXC_F_TMR_NOLCMP_NOLHCMP                                               \
-	((uint32_t)(                                                           \
-		0xFFUL                                                         \
-		<< MXC_F_TMR_NOLCMP_NOLHCMP_POS)) /**< NOLCMP_NOLHCMP Mask */
+	((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_NOLHCMP_POS)) /**<              \
+								NOLCMP_NOLHCMP \
+								Mask */
 
 #ifdef __cplusplus
 }
diff --git a/chip/max32660/uart_chip.c b/chip/max32660/uart_chip.c
index c30a6ebd45..ec25d9e476 100644
--- a/chip/max32660/uart_chip.c
+++ b/chip/max32660/uart_chip.c
@@ -1,21 +1,23 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* MAX32660 Console UART Module for Chrome EC */
 
-#include <stdint.h>
+#include "common.h"
+#include "gcr_regs.h"
+#include "gpio.h"
+#include "gpio_regs.h"
+#include "registers.h"
 #include "system.h"
 #include "task.h"
-#include "uart.h"
-#include "registers.h"
 #include "tmr_regs.h"
-#include "gpio_regs.h"
-#include "common.h"
-#include "gcr_regs.h"
+#include "uart.h"
 #include "uart_regs.h"
 
+#include <stdint.h>
+
 static int done_uart_init_yet;
 
 #ifndef UARTN
@@ -34,24 +36,24 @@ static int done_uart_init_yet;
 
 #define UART_BAUD 115200
 
-#define UART_ER_IF                                                             \
-	(MXC_F_UART_INT_FL_RX_FRAME_ERROR |                                    \
+#define UART_ER_IF                          \
+	(MXC_F_UART_INT_FL_RX_FRAME_ERROR | \
 	 MXC_F_UART_INT_FL_RX_PARITY_ERROR | MXC_F_UART_INT_FL_RX_OVERRUN)
 
-#define UART_ER_IE                                                             \
-	(MXC_F_UART_INT_EN_RX_FRAME_ERROR |                                    \
+#define UART_ER_IE                          \
+	(MXC_F_UART_INT_EN_RX_FRAME_ERROR | \
 	 MXC_F_UART_INT_EN_RX_PARITY_ERROR | MXC_F_UART_INT_EN_RX_OVERRUN)
 
 #define UART_RX_IF (UART_ER_IF | MXC_F_UART_INT_FL_RX_FIFO_THRESH)
 
 #define UART_RX_IE (UART_ER_IE | MXC_F_UART_INT_EN_RX_FIFO_THRESH)
 
-#define UART_TX_IF                                                             \
-	(UART_ER_IF | MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY |                 \
+#define UART_TX_IF                                             \
+	(UART_ER_IF | MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY | \
 	 MXC_F_UART_INT_FL_TX_FIFO_THRESH)
 
-#define UART_TX_IE                                                             \
-	(UART_ER_IE | MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY |                 \
+#define UART_TX_IE                                             \
+	(UART_ER_IE | MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY | \
 	 MXC_F_UART_INT_EN_TX_FIFO_THRESH)
 
 #define UART_RX_THRESHOLD_LEVEL 1
@@ -221,7 +223,7 @@ int uart_read_char(void)
 /**
  * Interrupt handlers for UART
  */
-void uart_rxtx_interrupt(void)
+static void uart_rxtx_interrupt(void)
 {
 	/* Process the Console Input */
 	uart_process_input();
@@ -241,19 +243,20 @@ void uart_init(void)
 	gpio_config_module(MODULE_UART, 1);
 
 	/* Drain FIFOs and enable UART and set configuration */
-	MXC_UART->ctrl = (MXC_F_UART_CTRL_ENABLE | MXC_S_UART_CTRL_CHAR_SIZE_8 | 1);
+	MXC_UART->ctrl =
+		(MXC_F_UART_CTRL_ENABLE | MXC_S_UART_CTRL_CHAR_SIZE_8 | 1);
 
 	/* Set the baud rate */
-	div = PeripheralClock / (UART_BAUD); 	// constant part of DIV (i.e. DIV
-					     					// * (Baudrate*factor_int))
+	div = PeripheralClock / (UART_BAUD); // constant part of DIV (i.e. DIV
+					     // * (Baudrate*factor_int))
 
 	do {
 		factor += 1;
-		baud0 = div >> (7 - factor); 	// divide by 128,64,32,16 to
-					     				// extract integer part
-		baud1 = ((div << factor) -
-			 (baud0 << 7)); 			// subtract factor corrected div -
-										// integer parts
+		baud0 = div >> (7 - factor); // divide by 128,64,32,16 to
+					     // extract integer part
+		baud1 = ((div << factor) - (baud0 << 7)); // subtract factor
+							  // corrected div -
+							  // integer parts
 
 	} while ((baud0 == 0) && (factor < 4));
 
@@ -261,7 +264,7 @@ void uart_init(void)
 	MXC_UART->baud1 = baud1;
 
 	MXC_UART->thresh_ctrl = UART_RX_THRESHOLD_LEVEL
-			    << MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS;
+				<< MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS;
 
 	/* Clear Interrupt Flags */
 	flags = MXC_UART->int_fl;
diff --git a/chip/max32660/uart_regs.h b/chip/max32660/uart_regs.h
index a2de0cc0a0..64d4ac5654 100644
--- a/chip/max32660/uart_regs.h
+++ b/chip/max32660/uart_regs.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -32,15 +32,15 @@
  */
 typedef struct {
 	__IO uint32_t ctrl; /**< <tt>\b 0x00:<\tt> UART CTRL Register */
-	__IO uint32_t
-		thresh_ctrl; /**< <tt>\b 0x04:<\tt> UART THRESH_CTRL Register */
+	__IO uint32_t thresh_ctrl; /**< <tt>\b 0x04:<\tt> UART THRESH_CTRL
+				      Register */
 	__I uint32_t status; /**< <tt>\b 0x08:<\tt> UART STATUS Register */
-	__IO uint32_t int_en;  /**< <tt>\b 0x0C:<\tt> UART INT_EN Register */
-	__IO uint32_t int_fl;  /**< <tt>\b 0x10:<\tt> UART INT_FL Register */
-	__IO uint32_t baud0;   /**< <tt>\b 0x14:<\tt> UART BAUD0 Register */
-	__IO uint32_t baud1;   /**< <tt>\b 0x18:<\tt> UART BAUD1 Register */
-	__IO uint32_t fifo;    /**< <tt>\b 0x1C:<\tt> UART FIFO Register */
-	__IO uint32_t dma;     /**< <tt>\b 0x20:<\tt> UART DMA Register */
+	__IO uint32_t int_en; /**< <tt>\b 0x0C:<\tt> UART INT_EN Register */
+	__IO uint32_t int_fl; /**< <tt>\b 0x10:<\tt> UART INT_FL Register */
+	__IO uint32_t baud0; /**< <tt>\b 0x14:<\tt> UART BAUD0 Register */
+	__IO uint32_t baud1; /**< <tt>\b 0x18:<\tt> UART BAUD1 Register */
+	__IO uint32_t fifo; /**< <tt>\b 0x1C:<\tt> UART FIFO Register */
+	__IO uint32_t dma; /**< <tt>\b 0x20:<\tt> UART DMA Register */
 	__IO uint32_t tx_fifo; /**< <tt>\b 0x24:<\tt> UART TX_FIFO Register */
 } mxc_uart_regs_t;
 
@@ -48,630 +48,707 @@ typedef struct {
  * UART Peripheral Register Offsets from the UART Base Peripheral
  * Address.
  */
-#define MXC_R_UART_CTRL                                                        \
-	((uint32_t)0x00000000UL) /**< Offset from UART Base Address: <tt>      \
+#define MXC_R_UART_CTRL                                                   \
+	((uint32_t)0x00000000UL) /**< Offset from UART Base Address: <tt> \
 				    0x0x000 */
-#define MXC_R_UART_THRESH_CTRL                                                 \
-	((uint32_t)0x00000004UL) /**< Offset from UART Base Address: <tt>      \
+#define MXC_R_UART_THRESH_CTRL                                            \
+	((uint32_t)0x00000004UL) /**< Offset from UART Base Address: <tt> \
 				    0x0x004 */
-#define MXC_R_UART_STATUS                                                      \
-	((uint32_t)0x00000008UL) /**< Offset from UART Base Address: <tt>      \
+#define MXC_R_UART_STATUS                                                 \
+	((uint32_t)0x00000008UL) /**< Offset from UART Base Address: <tt> \
 				    0x0x008 */
-#define MXC_R_UART_INT_EN                                                      \
-	((uint32_t)0x0000000CUL) /**< Offset from UART Base Address: <tt>      \
+#define MXC_R_UART_INT_EN                                                 \
+	((uint32_t)0x0000000CUL) /**< Offset from UART Base Address: <tt> \
 				    0x0x00C */
-#define MXC_R_UART_INT_FL                                                      \
-	((uint32_t)0x00000010UL) /**< Offset from UART Base Address: <tt>      \
+#define MXC_R_UART_INT_FL                                                 \
+	((uint32_t)0x00000010UL) /**< Offset from UART Base Address: <tt> \
 				    0x0x010 */
-#define MXC_R_UART_BAUD0                                                       \
-	((uint32_t)0x00000014UL) /**< Offset from UART Base Address: <tt>      \
+#define MXC_R_UART_BAUD0                                                  \
+	((uint32_t)0x00000014UL) /**< Offset from UART Base Address: <tt> \
 				    0x0x014 */
-#define MXC_R_UART_BAUD1                                                       \
-	((uint32_t)0x00000018UL) /**< Offset from UART Base Address: <tt>      \
+#define MXC_R_UART_BAUD1                                                  \
+	((uint32_t)0x00000018UL) /**< Offset from UART Base Address: <tt> \
 				    0x0x018 */
-#define MXC_R_UART_FIFO                                                        \
-	((uint32_t)0x0000001CUL) /**< Offset from UART Base Address: <tt>      \
+#define MXC_R_UART_FIFO                                                   \
+	((uint32_t)0x0000001CUL) /**< Offset from UART Base Address: <tt> \
 				    0x0x01C */
-#define MXC_R_UART_DMA                                                         \
-	((uint32_t)0x00000020UL) /**< Offset from UART Base Address: <tt>      \
+#define MXC_R_UART_DMA                                                    \
+	((uint32_t)0x00000020UL) /**< Offset from UART Base Address: <tt> \
 				    0x0x020 */
-#define MXC_R_UART_TX_FIFO                                                     \
-	((uint32_t)0x00000024UL) /**< Offset from UART Base Address: <tt>      \
+#define MXC_R_UART_TX_FIFO                                                \
+	((uint32_t)0x00000024UL) /**< Offset from UART Base Address: <tt> \
 				    0x0x024 */
 
 /**
  * Control Register.
  */
 #define MXC_F_UART_CTRL_ENABLE_POS 0 /**< CTRL_ENABLE Position */
-#define MXC_F_UART_CTRL_ENABLE                                                 \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_UART_CTRL_ENABLE_POS)) /**< CTRL_ENABLE Mask */
-#define MXC_V_UART_CTRL_ENABLE_DIS                                             \
+#define MXC_F_UART_CTRL_ENABLE                                             \
+	((uint32_t)(0x1UL << MXC_F_UART_CTRL_ENABLE_POS)) /**< CTRL_ENABLE \
+							     Mask */
+#define MXC_V_UART_CTRL_ENABLE_DIS \
 	((uint32_t)0x0UL) /**< CTRL_ENABLE_DIS Value */
-#define MXC_S_UART_CTRL_ENABLE_DIS                                             \
-	(MXC_V_UART_CTRL_ENABLE_DIS                                            \
-	 << MXC_F_UART_CTRL_ENABLE_POS) /**< CTRL_ENABLE_DIS Setting */
-#define MXC_V_UART_CTRL_ENABLE_EN                                              \
-	((uint32_t)0x1UL) /**< CTRL_ENABLE_EN Value                            \
+#define MXC_S_UART_CTRL_ENABLE_DIS                         \
+	(MXC_V_UART_CTRL_ENABLE_DIS                        \
+	 << MXC_F_UART_CTRL_ENABLE_POS) /**<               \
+					   CTRL_ENABLE_DIS \
+					   Setting         \
+					 */
+#define MXC_V_UART_CTRL_ENABLE_EN                   \
+	((uint32_t)0x1UL) /**< CTRL_ENABLE_EN Value \
 			   */
-#define MXC_S_UART_CTRL_ENABLE_EN                                              \
-	(MXC_V_UART_CTRL_ENABLE_EN                                             \
-	 << MXC_F_UART_CTRL_ENABLE_POS) /**< CTRL_ENABLE_EN Setting */
+#define MXC_S_UART_CTRL_ENABLE_EN                         \
+	(MXC_V_UART_CTRL_ENABLE_EN                        \
+	 << MXC_F_UART_CTRL_ENABLE_POS) /**<              \
+					   CTRL_ENABLE_EN \
+					   Setting        \
+					 */
 
 #define MXC_F_UART_CTRL_PARITY_EN_POS 1 /**< CTRL_PARITY_EN Position */
 #define MXC_F_UART_CTRL_PARITY_EN                                              \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_CTRL_PARITY_EN_POS)) /**< CTRL_PARITY_EN Mask */
-#define MXC_V_UART_CTRL_PARITY_EN_DIS                                          \
+	((uint32_t)(0x1UL << MXC_F_UART_CTRL_PARITY_EN_POS)) /**<              \
+								CTRL_PARITY_EN \
+								Mask */
+#define MXC_V_UART_CTRL_PARITY_EN_DIS \
 	((uint32_t)0x0UL) /**< CTRL_PARITY_EN_DIS Value */
-#define MXC_S_UART_CTRL_PARITY_EN_DIS                                          \
-	(MXC_V_UART_CTRL_PARITY_EN_DIS                                         \
-	 << MXC_F_UART_CTRL_PARITY_EN_POS) /**< CTRL_PARITY_EN_DIS Setting */
-#define MXC_V_UART_CTRL_PARITY_EN_EN                                           \
+#define MXC_S_UART_CTRL_PARITY_EN_DIS                            \
+	(MXC_V_UART_CTRL_PARITY_EN_DIS                           \
+	 << MXC_F_UART_CTRL_PARITY_EN_POS) /**<                  \
+					      CTRL_PARITY_EN_DIS \
+					      Setting            \
+					    */
+#define MXC_V_UART_CTRL_PARITY_EN_EN \
 	((uint32_t)0x1UL) /**< CTRL_PARITY_EN_EN Value */
-#define MXC_S_UART_CTRL_PARITY_EN_EN                                           \
-	(MXC_V_UART_CTRL_PARITY_EN_EN                                          \
-	 << MXC_F_UART_CTRL_PARITY_EN_POS) /**< CTRL_PARITY_EN_EN Setting */
+#define MXC_S_UART_CTRL_PARITY_EN_EN                            \
+	(MXC_V_UART_CTRL_PARITY_EN_EN                           \
+	 << MXC_F_UART_CTRL_PARITY_EN_POS) /**<                 \
+					      CTRL_PARITY_EN_EN \
+					      Setting           \
+					    */
 
 #define MXC_F_UART_CTRL_PARITY_POS 2 /**< CTRL_PARITY Position */
-#define MXC_F_UART_CTRL_PARITY                                                 \
-	((uint32_t)(                                                           \
-		0x3UL << MXC_F_UART_CTRL_PARITY_POS)) /**< CTRL_PARITY Mask */
-#define MXC_V_UART_CTRL_PARITY_EVEN                                            \
+#define MXC_F_UART_CTRL_PARITY                                             \
+	((uint32_t)(0x3UL << MXC_F_UART_CTRL_PARITY_POS)) /**< CTRL_PARITY \
+							     Mask */
+#define MXC_V_UART_CTRL_PARITY_EVEN \
 	((uint32_t)0x0UL) /**< CTRL_PARITY_EVEN Value */
-#define MXC_S_UART_CTRL_PARITY_EVEN                                            \
-	(MXC_V_UART_CTRL_PARITY_EVEN                                           \
-	 << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_EVEN Setting */
-#define MXC_V_UART_CTRL_PARITY_ODD                                             \
+#define MXC_S_UART_CTRL_PARITY_EVEN                         \
+	(MXC_V_UART_CTRL_PARITY_EVEN                        \
+	 << MXC_F_UART_CTRL_PARITY_POS) /**<                \
+					   CTRL_PARITY_EVEN \
+					   Setting          \
+					 */
+#define MXC_V_UART_CTRL_PARITY_ODD \
 	((uint32_t)0x1UL) /**< CTRL_PARITY_ODD Value */
-#define MXC_S_UART_CTRL_PARITY_ODD                                             \
-	(MXC_V_UART_CTRL_PARITY_ODD                                            \
-	 << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_ODD Setting */
-#define MXC_V_UART_CTRL_PARITY_MARK                                            \
+#define MXC_S_UART_CTRL_PARITY_ODD                         \
+	(MXC_V_UART_CTRL_PARITY_ODD                        \
+	 << MXC_F_UART_CTRL_PARITY_POS) /**<               \
+					   CTRL_PARITY_ODD \
+					   Setting         \
+					 */
+#define MXC_V_UART_CTRL_PARITY_MARK \
 	((uint32_t)0x2UL) /**< CTRL_PARITY_MARK Value */
-#define MXC_S_UART_CTRL_PARITY_MARK                                            \
-	(MXC_V_UART_CTRL_PARITY_MARK                                           \
-	 << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_MARK Setting */
-#define MXC_V_UART_CTRL_PARITY_SPACE                                           \
+#define MXC_S_UART_CTRL_PARITY_MARK                         \
+	(MXC_V_UART_CTRL_PARITY_MARK                        \
+	 << MXC_F_UART_CTRL_PARITY_POS) /**<                \
+					   CTRL_PARITY_MARK \
+					   Setting          \
+					 */
+#define MXC_V_UART_CTRL_PARITY_SPACE \
 	((uint32_t)0x3UL) /**< CTRL_PARITY_SPACE Value */
-#define MXC_S_UART_CTRL_PARITY_SPACE                                           \
-	(MXC_V_UART_CTRL_PARITY_SPACE                                          \
-	 << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_SPACE Setting */
+#define MXC_S_UART_CTRL_PARITY_SPACE                         \
+	(MXC_V_UART_CTRL_PARITY_SPACE                        \
+	 << MXC_F_UART_CTRL_PARITY_POS) /**<                 \
+					   CTRL_PARITY_SPACE \
+					   Setting           \
+					 */
 
 #define MXC_F_UART_CTRL_PARMD_POS 4 /**< CTRL_PARMD Position */
-#define MXC_F_UART_CTRL_PARMD                                                  \
-	((uint32_t)(0x1UL << MXC_F_UART_CTRL_PARMD_POS)) /**< CTRL_PARMD Mask  \
+#define MXC_F_UART_CTRL_PARMD                                                 \
+	((uint32_t)(0x1UL << MXC_F_UART_CTRL_PARMD_POS)) /**< CTRL_PARMD Mask \
 							  */
 #define MXC_V_UART_CTRL_PARMD_1 ((uint32_t)0x0UL) /**< CTRL_PARMD_1 Value */
 #define MXC_S_UART_CTRL_PARMD_1                                                \
-	(MXC_V_UART_CTRL_PARMD_1                                               \
-	 << MXC_F_UART_CTRL_PARMD_POS)		  /**< CTRL_PARMD_1 Setting */
+	(MXC_V_UART_CTRL_PARMD_1 << MXC_F_UART_CTRL_PARMD_POS) /**<            \
+								  CTRL_PARMD_1 \
+								  Setting */
 #define MXC_V_UART_CTRL_PARMD_0 ((uint32_t)0x1UL) /**< CTRL_PARMD_0 Value */
 #define MXC_S_UART_CTRL_PARMD_0                                                \
-	(MXC_V_UART_CTRL_PARMD_0                                               \
-	 << MXC_F_UART_CTRL_PARMD_POS) /**< CTRL_PARMD_0 Setting */
+	(MXC_V_UART_CTRL_PARMD_0 << MXC_F_UART_CTRL_PARMD_POS) /**<            \
+								  CTRL_PARMD_0 \
+								  Setting */
 
 #define MXC_F_UART_CTRL_TX_FLUSH_POS 5 /**< CTRL_TX_FLUSH Position */
 #define MXC_F_UART_CTRL_TX_FLUSH                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_CTRL_TX_FLUSH_POS)) /**< CTRL_TX_FLUSH Mask */
+	((uint32_t)(0x1UL << MXC_F_UART_CTRL_TX_FLUSH_POS)) /**< CTRL_TX_FLUSH \
+							       Mask */
 
 #define MXC_F_UART_CTRL_RX_FLUSH_POS 6 /**< CTRL_RX_FLUSH Position */
 #define MXC_F_UART_CTRL_RX_FLUSH                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_CTRL_RX_FLUSH_POS)) /**< CTRL_RX_FLUSH Mask */
+	((uint32_t)(0x1UL << MXC_F_UART_CTRL_RX_FLUSH_POS)) /**< CTRL_RX_FLUSH \
+							       Mask */
 
 #define MXC_F_UART_CTRL_BITACC_POS 7 /**< CTRL_BITACC Position */
-#define MXC_F_UART_CTRL_BITACC                                                 \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_UART_CTRL_BITACC_POS)) /**< CTRL_BITACC Mask */
-#define MXC_V_UART_CTRL_BITACC_FRAME                                           \
+#define MXC_F_UART_CTRL_BITACC                                             \
+	((uint32_t)(0x1UL << MXC_F_UART_CTRL_BITACC_POS)) /**< CTRL_BITACC \
+							     Mask */
+#define MXC_V_UART_CTRL_BITACC_FRAME \
 	((uint32_t)0x0UL) /**< CTRL_BITACC_FRAME Value */
-#define MXC_S_UART_CTRL_BITACC_FRAME                                           \
-	(MXC_V_UART_CTRL_BITACC_FRAME                                          \
-	 << MXC_F_UART_CTRL_BITACC_POS) /**< CTRL_BITACC_FRAME Setting */
-#define MXC_V_UART_CTRL_BITACC_BIT                                             \
+#define MXC_S_UART_CTRL_BITACC_FRAME                         \
+	(MXC_V_UART_CTRL_BITACC_FRAME                        \
+	 << MXC_F_UART_CTRL_BITACC_POS) /**<                 \
+					   CTRL_BITACC_FRAME \
+					   Setting           \
+					 */
+#define MXC_V_UART_CTRL_BITACC_BIT \
 	((uint32_t)0x1UL) /**< CTRL_BITACC_BIT Value */
-#define MXC_S_UART_CTRL_BITACC_BIT                                             \
-	(MXC_V_UART_CTRL_BITACC_BIT                                            \
-	 << MXC_F_UART_CTRL_BITACC_POS) /**< CTRL_BITACC_BIT Setting */
+#define MXC_S_UART_CTRL_BITACC_BIT                         \
+	(MXC_V_UART_CTRL_BITACC_BIT                        \
+	 << MXC_F_UART_CTRL_BITACC_POS) /**<               \
+					   CTRL_BITACC_BIT \
+					   Setting         \
+					 */
 
 #define MXC_F_UART_CTRL_CHAR_SIZE_POS 8 /**< CTRL_CHAR_SIZE Position */
 #define MXC_F_UART_CTRL_CHAR_SIZE                                              \
-	((uint32_t)(                                                           \
-		0x3UL                                                          \
-		<< MXC_F_UART_CTRL_CHAR_SIZE_POS)) /**< CTRL_CHAR_SIZE Mask */
-#define MXC_V_UART_CTRL_CHAR_SIZE_5                                            \
+	((uint32_t)(0x3UL << MXC_F_UART_CTRL_CHAR_SIZE_POS)) /**<              \
+								CTRL_CHAR_SIZE \
+								Mask */
+#define MXC_V_UART_CTRL_CHAR_SIZE_5 \
 	((uint32_t)0x0UL) /**< CTRL_CHAR_SIZE_5 Value */
-#define MXC_S_UART_CTRL_CHAR_SIZE_5                                            \
-	(MXC_V_UART_CTRL_CHAR_SIZE_5                                           \
-	 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_5 Setting */
-#define MXC_V_UART_CTRL_CHAR_SIZE_6                                            \
+#define MXC_S_UART_CTRL_CHAR_SIZE_5                            \
+	(MXC_V_UART_CTRL_CHAR_SIZE_5                           \
+	 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**<                \
+					      CTRL_CHAR_SIZE_5 \
+					      Setting          \
+					    */
+#define MXC_V_UART_CTRL_CHAR_SIZE_6 \
 	((uint32_t)0x1UL) /**< CTRL_CHAR_SIZE_6 Value */
-#define MXC_S_UART_CTRL_CHAR_SIZE_6                                            \
-	(MXC_V_UART_CTRL_CHAR_SIZE_6                                           \
-	 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_6 Setting */
-#define MXC_V_UART_CTRL_CHAR_SIZE_7                                            \
+#define MXC_S_UART_CTRL_CHAR_SIZE_6                            \
+	(MXC_V_UART_CTRL_CHAR_SIZE_6                           \
+	 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**<                \
+					      CTRL_CHAR_SIZE_6 \
+					      Setting          \
+					    */
+#define MXC_V_UART_CTRL_CHAR_SIZE_7 \
 	((uint32_t)0x2UL) /**< CTRL_CHAR_SIZE_7 Value */
-#define MXC_S_UART_CTRL_CHAR_SIZE_7                                            \
-	(MXC_V_UART_CTRL_CHAR_SIZE_7                                           \
-	 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_7 Setting */
-#define MXC_V_UART_CTRL_CHAR_SIZE_8                                            \
+#define MXC_S_UART_CTRL_CHAR_SIZE_7                            \
+	(MXC_V_UART_CTRL_CHAR_SIZE_7                           \
+	 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**<                \
+					      CTRL_CHAR_SIZE_7 \
+					      Setting          \
+					    */
+#define MXC_V_UART_CTRL_CHAR_SIZE_8 \
 	((uint32_t)0x3UL) /**< CTRL_CHAR_SIZE_8 Value */
-#define MXC_S_UART_CTRL_CHAR_SIZE_8                                            \
-	(MXC_V_UART_CTRL_CHAR_SIZE_8                                           \
-	 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_8 Setting */
+#define MXC_S_UART_CTRL_CHAR_SIZE_8                            \
+	(MXC_V_UART_CTRL_CHAR_SIZE_8                           \
+	 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**<                \
+					      CTRL_CHAR_SIZE_8 \
+					      Setting          \
+					    */
 
 #define MXC_F_UART_CTRL_STOPBITS_POS 10 /**< CTRL_STOPBITS Position */
 #define MXC_F_UART_CTRL_STOPBITS                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_CTRL_STOPBITS_POS)) /**< CTRL_STOPBITS Mask */
-#define MXC_V_UART_CTRL_STOPBITS_1                                             \
+	((uint32_t)(0x1UL << MXC_F_UART_CTRL_STOPBITS_POS)) /**< CTRL_STOPBITS \
+							       Mask */
+#define MXC_V_UART_CTRL_STOPBITS_1 \
 	((uint32_t)0x0UL) /**< CTRL_STOPBITS_1 Value */
-#define MXC_S_UART_CTRL_STOPBITS_1                                             \
-	(MXC_V_UART_CTRL_STOPBITS_1                                            \
-	 << MXC_F_UART_CTRL_STOPBITS_POS) /**< CTRL_STOPBITS_1 Setting */
-#define MXC_V_UART_CTRL_STOPBITS_1_5                                           \
+#define MXC_S_UART_CTRL_STOPBITS_1                           \
+	(MXC_V_UART_CTRL_STOPBITS_1                          \
+	 << MXC_F_UART_CTRL_STOPBITS_POS) /**<               \
+					     CTRL_STOPBITS_1 \
+					     Setting         \
+					   */
+#define MXC_V_UART_CTRL_STOPBITS_1_5 \
 	((uint32_t)0x1UL) /**< CTRL_STOPBITS_1_5 Value */
-#define MXC_S_UART_CTRL_STOPBITS_1_5                                           \
-	(MXC_V_UART_CTRL_STOPBITS_1_5                                          \
-	 << MXC_F_UART_CTRL_STOPBITS_POS) /**< CTRL_STOPBITS_1_5 Setting */
+#define MXC_S_UART_CTRL_STOPBITS_1_5                           \
+	(MXC_V_UART_CTRL_STOPBITS_1_5                          \
+	 << MXC_F_UART_CTRL_STOPBITS_POS) /**<                 \
+					     CTRL_STOPBITS_1_5 \
+					     Setting           \
+					   */
 
 #define MXC_F_UART_CTRL_FLOW_CTRL_POS 11 /**< CTRL_FLOW_CTRL Position */
 #define MXC_F_UART_CTRL_FLOW_CTRL                                              \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_CTRL_FLOW_CTRL_POS)) /**< CTRL_FLOW_CTRL Mask */
-#define MXC_V_UART_CTRL_FLOW_CTRL_EN                                           \
+	((uint32_t)(0x1UL << MXC_F_UART_CTRL_FLOW_CTRL_POS)) /**<              \
+								CTRL_FLOW_CTRL \
+								Mask */
+#define MXC_V_UART_CTRL_FLOW_CTRL_EN \
 	((uint32_t)0x1UL) /**< CTRL_FLOW_CTRL_EN Value */
-#define MXC_S_UART_CTRL_FLOW_CTRL_EN                                           \
-	(MXC_V_UART_CTRL_FLOW_CTRL_EN                                          \
-	 << MXC_F_UART_CTRL_FLOW_CTRL_POS) /**< CTRL_FLOW_CTRL_EN Setting */
-#define MXC_V_UART_CTRL_FLOW_CTRL_DIS                                          \
+#define MXC_S_UART_CTRL_FLOW_CTRL_EN                            \
+	(MXC_V_UART_CTRL_FLOW_CTRL_EN                           \
+	 << MXC_F_UART_CTRL_FLOW_CTRL_POS) /**<                 \
+					      CTRL_FLOW_CTRL_EN \
+					      Setting           \
+					    */
+#define MXC_V_UART_CTRL_FLOW_CTRL_DIS \
 	((uint32_t)0x0UL) /**< CTRL_FLOW_CTRL_DIS Value */
-#define MXC_S_UART_CTRL_FLOW_CTRL_DIS                                          \
-	(MXC_V_UART_CTRL_FLOW_CTRL_DIS                                         \
-	 << MXC_F_UART_CTRL_FLOW_CTRL_POS) /**< CTRL_FLOW_CTRL_DIS Setting */
+#define MXC_S_UART_CTRL_FLOW_CTRL_DIS                            \
+	(MXC_V_UART_CTRL_FLOW_CTRL_DIS                           \
+	 << MXC_F_UART_CTRL_FLOW_CTRL_POS) /**<                  \
+					      CTRL_FLOW_CTRL_DIS \
+					      Setting            \
+					    */
 
 #define MXC_F_UART_CTRL_FLOW_POL_POS 12 /**< CTRL_FLOW_POL Position */
 #define MXC_F_UART_CTRL_FLOW_POL                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_CTRL_FLOW_POL_POS)) /**< CTRL_FLOW_POL Mask */
-#define MXC_V_UART_CTRL_FLOW_POL_0                                             \
+	((uint32_t)(0x1UL << MXC_F_UART_CTRL_FLOW_POL_POS)) /**< CTRL_FLOW_POL \
+							       Mask */
+#define MXC_V_UART_CTRL_FLOW_POL_0 \
 	((uint32_t)0x0UL) /**< CTRL_FLOW_POL_0 Value */
-#define MXC_S_UART_CTRL_FLOW_POL_0                                             \
-	(MXC_V_UART_CTRL_FLOW_POL_0                                            \
-	 << MXC_F_UART_CTRL_FLOW_POL_POS) /**< CTRL_FLOW_POL_0 Setting */
-#define MXC_V_UART_CTRL_FLOW_POL_1                                             \
+#define MXC_S_UART_CTRL_FLOW_POL_0                           \
+	(MXC_V_UART_CTRL_FLOW_POL_0                          \
+	 << MXC_F_UART_CTRL_FLOW_POL_POS) /**<               \
+					     CTRL_FLOW_POL_0 \
+					     Setting         \
+					   */
+#define MXC_V_UART_CTRL_FLOW_POL_1 \
 	((uint32_t)0x1UL) /**< CTRL_FLOW_POL_1 Value */
-#define MXC_S_UART_CTRL_FLOW_POL_1                                             \
-	(MXC_V_UART_CTRL_FLOW_POL_1                                            \
-	 << MXC_F_UART_CTRL_FLOW_POL_POS) /**< CTRL_FLOW_POL_1 Setting */
+#define MXC_S_UART_CTRL_FLOW_POL_1                           \
+	(MXC_V_UART_CTRL_FLOW_POL_1                          \
+	 << MXC_F_UART_CTRL_FLOW_POL_POS) /**<               \
+					     CTRL_FLOW_POL_1 \
+					     Setting         \
+					   */
 
 #define MXC_F_UART_CTRL_NULL_MODEM_POS 13 /**< CTRL_NULL_MODEM Position */
-#define MXC_F_UART_CTRL_NULL_MODEM                                             \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_UART_CTRL_NULL_MODEM_POS)) /**< CTRL_NULL_MODEM \
-							     Mask */
-#define MXC_V_UART_CTRL_NULL_MODEM_DIS                                         \
+#define MXC_F_UART_CTRL_NULL_MODEM                                           \
+	((uint32_t)(0x1UL                                                    \
+		    << MXC_F_UART_CTRL_NULL_MODEM_POS)) /**< CTRL_NULL_MODEM \
+							   Mask */
+#define MXC_V_UART_CTRL_NULL_MODEM_DIS \
 	((uint32_t)0x0UL) /**< CTRL_NULL_MODEM_DIS Value */
-#define MXC_S_UART_CTRL_NULL_MODEM_DIS                                         \
-	(MXC_V_UART_CTRL_NULL_MODEM_DIS                                        \
-	 << MXC_F_UART_CTRL_NULL_MODEM_POS) /**< CTRL_NULL_MODEM_DIS Setting   \
+#define MXC_S_UART_CTRL_NULL_MODEM_DIS                                       \
+	(MXC_V_UART_CTRL_NULL_MODEM_DIS                                      \
+	 << MXC_F_UART_CTRL_NULL_MODEM_POS) /**< CTRL_NULL_MODEM_DIS Setting \
 					     */
-#define MXC_V_UART_CTRL_NULL_MODEM_EN                                          \
+#define MXC_V_UART_CTRL_NULL_MODEM_EN \
 	((uint32_t)0x1UL) /**< CTRL_NULL_MODEM_EN Value */
-#define MXC_S_UART_CTRL_NULL_MODEM_EN                                          \
-	(MXC_V_UART_CTRL_NULL_MODEM_EN                                         \
+#define MXC_S_UART_CTRL_NULL_MODEM_EN  \
+	(MXC_V_UART_CTRL_NULL_MODEM_EN \
 	 << MXC_F_UART_CTRL_NULL_MODEM_POS) /**< CTRL_NULL_MODEM_EN Setting */
 
 #define MXC_F_UART_CTRL_BREAK_POS 14 /**< CTRL_BREAK Position */
-#define MXC_F_UART_CTRL_BREAK                                                  \
-	((uint32_t)(0x1UL << MXC_F_UART_CTRL_BREAK_POS)) /**< CTRL_BREAK Mask  \
+#define MXC_F_UART_CTRL_BREAK                                                 \
+	((uint32_t)(0x1UL << MXC_F_UART_CTRL_BREAK_POS)) /**< CTRL_BREAK Mask \
 							  */
-#define MXC_V_UART_CTRL_BREAK_DIS                                              \
-	((uint32_t)0x0UL) /**< CTRL_BREAK_DIS Value                            \
+#define MXC_V_UART_CTRL_BREAK_DIS                   \
+	((uint32_t)0x0UL) /**< CTRL_BREAK_DIS Value \
 			   */
-#define MXC_S_UART_CTRL_BREAK_DIS                                              \
-	(MXC_V_UART_CTRL_BREAK_DIS                                             \
-	 << MXC_F_UART_CTRL_BREAK_POS) /**< CTRL_BREAK_DIS Setting */
+#define MXC_S_UART_CTRL_BREAK_DIS                        \
+	(MXC_V_UART_CTRL_BREAK_DIS                       \
+	 << MXC_F_UART_CTRL_BREAK_POS) /**<              \
+					  CTRL_BREAK_DIS \
+					  Setting */
 #define MXC_V_UART_CTRL_BREAK_EN ((uint32_t)0x1UL) /**< CTRL_BREAK_EN Value */
-#define MXC_S_UART_CTRL_BREAK_EN                                               \
-	(MXC_V_UART_CTRL_BREAK_EN                                              \
-	 << MXC_F_UART_CTRL_BREAK_POS) /**< CTRL_BREAK_EN Setting */
+#define MXC_S_UART_CTRL_BREAK_EN                        \
+	(MXC_V_UART_CTRL_BREAK_EN                       \
+	 << MXC_F_UART_CTRL_BREAK_POS) /**<             \
+					  CTRL_BREAK_EN \
+					  Setting */
 
 #define MXC_F_UART_CTRL_CLKSEL_POS 15 /**< CTRL_CLKSEL Position */
-#define MXC_F_UART_CTRL_CLKSEL                                                 \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_UART_CTRL_CLKSEL_POS)) /**< CTRL_CLKSEL Mask */
-#define MXC_V_UART_CTRL_CLKSEL_SYSTEM                                          \
+#define MXC_F_UART_CTRL_CLKSEL                                             \
+	((uint32_t)(0x1UL << MXC_F_UART_CTRL_CLKSEL_POS)) /**< CTRL_CLKSEL \
+							     Mask */
+#define MXC_V_UART_CTRL_CLKSEL_SYSTEM \
 	((uint32_t)0x0UL) /**< CTRL_CLKSEL_SYSTEM Value */
-#define MXC_S_UART_CTRL_CLKSEL_SYSTEM                                          \
-	(MXC_V_UART_CTRL_CLKSEL_SYSTEM                                         \
-	 << MXC_F_UART_CTRL_CLKSEL_POS) /**< CTRL_CLKSEL_SYSTEM Setting */
-#define MXC_V_UART_CTRL_CLKSEL_ALTERNATE                                       \
+#define MXC_S_UART_CTRL_CLKSEL_SYSTEM                         \
+	(MXC_V_UART_CTRL_CLKSEL_SYSTEM                        \
+	 << MXC_F_UART_CTRL_CLKSEL_POS) /**<                  \
+					   CTRL_CLKSEL_SYSTEM \
+					   Setting            \
+					 */
+#define MXC_V_UART_CTRL_CLKSEL_ALTERNATE \
 	((uint32_t)0x1UL) /**< CTRL_CLKSEL_ALTERNATE Value */
-#define MXC_S_UART_CTRL_CLKSEL_ALTERNATE                                       \
-	(MXC_V_UART_CTRL_CLKSEL_ALTERNATE                                      \
-	 << MXC_F_UART_CTRL_CLKSEL_POS) /**< CTRL_CLKSEL_ALTERNATE Setting */
+#define MXC_S_UART_CTRL_CLKSEL_ALTERNATE                         \
+	(MXC_V_UART_CTRL_CLKSEL_ALTERNATE                        \
+	 << MXC_F_UART_CTRL_CLKSEL_POS) /**<                     \
+					   CTRL_CLKSEL_ALTERNATE \
+					   Setting               \
+					 */
 
 #define MXC_F_UART_CTRL_RX_TO_POS 16 /**< CTRL_RX_TO Position */
 #define MXC_F_UART_CTRL_RX_TO                                                  \
-	((uint32_t)(                                                           \
-		0xFFUL << MXC_F_UART_CTRL_RX_TO_POS)) /**< CTRL_RX_TO Mask */
+	((uint32_t)(0xFFUL << MXC_F_UART_CTRL_RX_TO_POS)) /**< CTRL_RX_TO Mask \
+							   */
 
 /**
  * Threshold Control register.
  */
-#define MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS                              \
+#define MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS \
 	0 /**< THRESH_CTRL_RX_FIFO_THRESH Position */
-#define MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH                                                \
-	((uint32_t)(                                                                         \
-		0x3FUL                                                                       \
-		<< MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS)) /**<                          \
-								  THRESH_CTRL_RX_FIFO_THRESH \
-								  Mask */
+#define MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH                                                    \
+	((uint32_t)(0x3FUL                                                                       \
+		    << MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS)) /**<                          \
+								      THRESH_CTRL_RX_FIFO_THRESH \
+								      Mask */
 
-#define MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH_POS                              \
+#define MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH_POS \
 	8 /**< THRESH_CTRL_TX_FIFO_THRESH Position */
-#define MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH                                                \
-	((uint32_t)(                                                                         \
-		0x3FUL                                                                       \
-		<< MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH_POS)) /**<                          \
-								  THRESH_CTRL_TX_FIFO_THRESH \
-								  Mask */
+#define MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH                                                    \
+	((uint32_t)(0x3FUL                                                                       \
+		    << MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH_POS)) /**<                          \
+								      THRESH_CTRL_TX_FIFO_THRESH \
+								      Mask */
 
-#define MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH_POS                             \
+#define MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH_POS \
 	16 /**< THRESH_CTRL_RTS_FIFO_THRESH Position */
-#define MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH                                                 \
-	((uint32_t)(                                                                           \
-		0x3FUL                                                                         \
-		<< MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH_POS)) /**<                           \
-								   THRESH_CTRL_RTS_FIFO_THRESH \
-								   Mask */
+#define MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH                                                     \
+	((uint32_t)(0x3FUL                                                                         \
+		    << MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH_POS)) /**<                           \
+								       THRESH_CTRL_RTS_FIFO_THRESH \
+								       Mask */
 
 /**
  * Status Register.
  */
 #define MXC_F_UART_STATUS_TX_BUSY_POS 0 /**< STATUS_TX_BUSY Position */
 #define MXC_F_UART_STATUS_TX_BUSY                                              \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_STATUS_TX_BUSY_POS)) /**< STATUS_TX_BUSY Mask */
+	((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_BUSY_POS)) /**<              \
+								STATUS_TX_BUSY \
+								Mask */
 
 #define MXC_F_UART_STATUS_RX_BUSY_POS 1 /**< STATUS_RX_BUSY Position */
 #define MXC_F_UART_STATUS_RX_BUSY                                              \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_STATUS_RX_BUSY_POS)) /**< STATUS_RX_BUSY Mask */
+	((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_BUSY_POS)) /**<              \
+								STATUS_RX_BUSY \
+								Mask */
 
 #define MXC_F_UART_STATUS_PARITY_POS 2 /**< STATUS_PARITY Position */
 #define MXC_F_UART_STATUS_PARITY                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_STATUS_PARITY_POS)) /**< STATUS_PARITY Mask */
+	((uint32_t)(0x1UL << MXC_F_UART_STATUS_PARITY_POS)) /**< STATUS_PARITY \
+							       Mask */
 
 #define MXC_F_UART_STATUS_BREAK_POS 3 /**< STATUS_BREAK Position */
-#define MXC_F_UART_STATUS_BREAK                                                \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_UART_STATUS_BREAK_POS)) /**< STATUS_BREAK Mask */
+#define MXC_F_UART_STATUS_BREAK                                              \
+	((uint32_t)(0x1UL << MXC_F_UART_STATUS_BREAK_POS)) /**< STATUS_BREAK \
+							      Mask */
 
 #define MXC_F_UART_STATUS_RX_EMPTY_POS 4 /**< STATUS_RX_EMPTY Position */
-#define MXC_F_UART_STATUS_RX_EMPTY                                             \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_UART_STATUS_RX_EMPTY_POS)) /**< STATUS_RX_EMPTY \
-							     Mask */
+#define MXC_F_UART_STATUS_RX_EMPTY                                           \
+	((uint32_t)(0x1UL                                                    \
+		    << MXC_F_UART_STATUS_RX_EMPTY_POS)) /**< STATUS_RX_EMPTY \
+							   Mask */
 
 #define MXC_F_UART_STATUS_RX_FULL_POS 5 /**< STATUS_RX_FULL Position */
 #define MXC_F_UART_STATUS_RX_FULL                                              \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */
+	((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_FULL_POS)) /**<              \
+								STATUS_RX_FULL \
+								Mask */
 
 #define MXC_F_UART_STATUS_TX_EMPTY_POS 6 /**< STATUS_TX_EMPTY Position */
-#define MXC_F_UART_STATUS_TX_EMPTY                                             \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_UART_STATUS_TX_EMPTY_POS)) /**< STATUS_TX_EMPTY \
-							     Mask */
+#define MXC_F_UART_STATUS_TX_EMPTY                                           \
+	((uint32_t)(0x1UL                                                    \
+		    << MXC_F_UART_STATUS_TX_EMPTY_POS)) /**< STATUS_TX_EMPTY \
+							   Mask */
 
 #define MXC_F_UART_STATUS_TX_FULL_POS 7 /**< STATUS_TX_FULL Position */
 #define MXC_F_UART_STATUS_TX_FULL                                              \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */
+	((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_FULL_POS)) /**<              \
+								STATUS_TX_FULL \
+								Mask */
 
-#define MXC_F_UART_STATUS_RX_FIFO_CNT_POS                                      \
-	8 /**< STATUS_RX_FIFO_CNT Position                                     \
+#define MXC_F_UART_STATUS_RX_FIFO_CNT_POS  \
+	8 /**< STATUS_RX_FIFO_CNT Position \
 	   */
-#define MXC_F_UART_STATUS_RX_FIFO_CNT                                          \
-	((uint32_t)(                                                           \
-		0x3FUL                                                         \
-		<< MXC_F_UART_STATUS_RX_FIFO_CNT_POS)) /**< STATUS_RX_FIFO_CNT \
-							  Mask */
-
-#define MXC_F_UART_STATUS_TX_FIFO_CNT_POS                                      \
-	16 /**< STATUS_TX_FIFO_CNT Position                                    \
+#define MXC_F_UART_STATUS_RX_FIFO_CNT                                            \
+	((uint32_t)(0x3FUL                                                       \
+		    << MXC_F_UART_STATUS_RX_FIFO_CNT_POS)) /**<                  \
+							      STATUS_RX_FIFO_CNT \
+							      Mask */
+
+#define MXC_F_UART_STATUS_TX_FIFO_CNT_POS   \
+	16 /**< STATUS_TX_FIFO_CNT Position \
 	    */
-#define MXC_F_UART_STATUS_TX_FIFO_CNT                                          \
-	((uint32_t)(                                                           \
-		0x3FUL                                                         \
-		<< MXC_F_UART_STATUS_TX_FIFO_CNT_POS)) /**< STATUS_TX_FIFO_CNT \
-							  Mask */
+#define MXC_F_UART_STATUS_TX_FIFO_CNT                                            \
+	((uint32_t)(0x3FUL                                                       \
+		    << MXC_F_UART_STATUS_TX_FIFO_CNT_POS)) /**<                  \
+							      STATUS_TX_FIFO_CNT \
+							      Mask */
 
 #define MXC_F_UART_STATUS_RX_TO_POS 24 /**< STATUS_RX_TO Position */
-#define MXC_F_UART_STATUS_RX_TO                                                \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_UART_STATUS_RX_TO_POS)) /**< STATUS_RX_TO Mask */
+#define MXC_F_UART_STATUS_RX_TO                                              \
+	((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_TO_POS)) /**< STATUS_RX_TO \
+							      Mask */
 
 /**
  * Interrupt Enable Register.
  */
-#define MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS                                   \
+#define MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS \
 	0 /**< INT_EN_RX_FRAME_ERROR Position */
-#define MXC_F_UART_INT_EN_RX_FRAME_ERROR                                           \
-	((uint32_t)(                                                               \
-		0x1UL                                                              \
-		<< MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS)) /**<                     \
-							     INT_EN_RX_FRAME_ERROR \
-							     Mask */
+#define MXC_F_UART_INT_EN_RX_FRAME_ERROR                                               \
+	((uint32_t)(0x1UL                                                              \
+		    << MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS)) /**<                     \
+								 INT_EN_RX_FRAME_ERROR \
+								 Mask */
 
-#define MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS                                  \
+#define MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS \
 	1 /**< INT_EN_RX_PARITY_ERROR Position */
-#define MXC_F_UART_INT_EN_RX_PARITY_ERROR                                            \
-	((uint32_t)(                                                                 \
-		0x1UL                                                                \
-		<< MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS)) /**<                      \
-							      INT_EN_RX_PARITY_ERROR \
-							      Mask */
+#define MXC_F_UART_INT_EN_RX_PARITY_ERROR                                                \
+	((uint32_t)(0x1UL                                                                \
+		    << MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS)) /**<                      \
+								  INT_EN_RX_PARITY_ERROR \
+								  Mask */
 
 #define MXC_F_UART_INT_EN_CTS_CHANGE_POS 2 /**< INT_EN_CTS_CHANGE Position */
 #define MXC_F_UART_INT_EN_CTS_CHANGE                                           \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_INT_EN_CTS_CHANGE_POS)) /**< INT_EN_CTS_CHANGE   \
-							 Mask */
+	((uint32_t)(0x1UL                                                      \
+		    << MXC_F_UART_INT_EN_CTS_CHANGE_POS)) /**<                 \
+							     INT_EN_CTS_CHANGE \
+							     Mask */
 
 #define MXC_F_UART_INT_EN_RX_OVERRUN_POS 3 /**< INT_EN_RX_OVERRUN Position */
 #define MXC_F_UART_INT_EN_RX_OVERRUN                                           \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_INT_EN_RX_OVERRUN_POS)) /**< INT_EN_RX_OVERRUN   \
-							 Mask */
+	((uint32_t)(0x1UL                                                      \
+		    << MXC_F_UART_INT_EN_RX_OVERRUN_POS)) /**<                 \
+							     INT_EN_RX_OVERRUN \
+							     Mask */
 
-#define MXC_F_UART_INT_EN_RX_FIFO_THRESH_POS                                   \
+#define MXC_F_UART_INT_EN_RX_FIFO_THRESH_POS \
 	4 /**< INT_EN_RX_FIFO_THRESH Position */
-#define MXC_F_UART_INT_EN_RX_FIFO_THRESH                                           \
-	((uint32_t)(                                                               \
-		0x1UL                                                              \
-		<< MXC_F_UART_INT_EN_RX_FIFO_THRESH_POS)) /**<                     \
-							     INT_EN_RX_FIFO_THRESH \
-							     Mask */
+#define MXC_F_UART_INT_EN_RX_FIFO_THRESH                                               \
+	((uint32_t)(0x1UL                                                              \
+		    << MXC_F_UART_INT_EN_RX_FIFO_THRESH_POS)) /**<                     \
+								 INT_EN_RX_FIFO_THRESH \
+								 Mask */
 
-#define MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY_POS                             \
+#define MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY_POS \
 	5 /**< INT_EN_TX_FIFO_ALMOST_EMPTY Position */
-#define MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY                                                 \
-	((uint32_t)(                                                                           \
-		0x1UL                                                                          \
-		<< MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY_POS)) /**<                           \
-								   INT_EN_TX_FIFO_ALMOST_EMPTY \
-								   Mask */
-
-#define MXC_F_UART_INT_EN_TX_FIFO_THRESH_POS                                   \
+#define MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY                                                     \
+	((uint32_t)(0x1UL                                                                          \
+		    << MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY_POS)) /**<                           \
+								       INT_EN_TX_FIFO_ALMOST_EMPTY \
+								       Mask */
+
+#define MXC_F_UART_INT_EN_TX_FIFO_THRESH_POS \
 	6 /**< INT_EN_TX_FIFO_THRESH Position */
-#define MXC_F_UART_INT_EN_TX_FIFO_THRESH                                           \
-	((uint32_t)(                                                               \
-		0x1UL                                                              \
-		<< MXC_F_UART_INT_EN_TX_FIFO_THRESH_POS)) /**<                     \
-							     INT_EN_TX_FIFO_THRESH \
-							     Mask */
+#define MXC_F_UART_INT_EN_TX_FIFO_THRESH                                               \
+	((uint32_t)(0x1UL                                                              \
+		    << MXC_F_UART_INT_EN_TX_FIFO_THRESH_POS)) /**<                     \
+								 INT_EN_TX_FIFO_THRESH \
+								 Mask */
 
 #define MXC_F_UART_INT_EN_BREAK_POS 7 /**< INT_EN_BREAK Position */
-#define MXC_F_UART_INT_EN_BREAK                                                \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_UART_INT_EN_BREAK_POS)) /**< INT_EN_BREAK Mask */
+#define MXC_F_UART_INT_EN_BREAK                                              \
+	((uint32_t)(0x1UL << MXC_F_UART_INT_EN_BREAK_POS)) /**< INT_EN_BREAK \
+							      Mask */
 
 #define MXC_F_UART_INT_EN_RX_TIMEOUT_POS 8 /**< INT_EN_RX_TIMEOUT Position */
 #define MXC_F_UART_INT_EN_RX_TIMEOUT                                           \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_INT_EN_RX_TIMEOUT_POS)) /**< INT_EN_RX_TIMEOUT   \
-							 Mask */
+	((uint32_t)(0x1UL                                                      \
+		    << MXC_F_UART_INT_EN_RX_TIMEOUT_POS)) /**<                 \
+							     INT_EN_RX_TIMEOUT \
+							     Mask */
 
 #define MXC_F_UART_INT_EN_LAST_BREAK_POS 9 /**< INT_EN_LAST_BREAK Position */
 #define MXC_F_UART_INT_EN_LAST_BREAK                                           \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_INT_EN_LAST_BREAK_POS)) /**< INT_EN_LAST_BREAK   \
-							 Mask */
+	((uint32_t)(0x1UL                                                      \
+		    << MXC_F_UART_INT_EN_LAST_BREAK_POS)) /**<                 \
+							     INT_EN_LAST_BREAK \
+							     Mask */
 
 /**
  * Interrupt Status Flags.
  */
-#define MXC_F_UART_INT_FL_RX_FRAME_ERROR_POS                                   \
+#define MXC_F_UART_INT_FL_RX_FRAME_ERROR_POS \
 	0 /**< INT_FL_RX_FRAME_ERROR Position */
-#define MXC_F_UART_INT_FL_RX_FRAME_ERROR                                           \
-	((uint32_t)(                                                               \
-		0x1UL                                                              \
-		<< MXC_F_UART_INT_FL_RX_FRAME_ERROR_POS)) /**<                     \
-							     INT_FL_RX_FRAME_ERROR \
-							     Mask */
+#define MXC_F_UART_INT_FL_RX_FRAME_ERROR                                               \
+	((uint32_t)(0x1UL                                                              \
+		    << MXC_F_UART_INT_FL_RX_FRAME_ERROR_POS)) /**<                     \
+								 INT_FL_RX_FRAME_ERROR \
+								 Mask */
 
-#define MXC_F_UART_INT_FL_RX_PARITY_ERROR_POS                                  \
+#define MXC_F_UART_INT_FL_RX_PARITY_ERROR_POS \
 	1 /**< INT_FL_RX_PARITY_ERROR Position */
-#define MXC_F_UART_INT_FL_RX_PARITY_ERROR                                            \
-	((uint32_t)(                                                                 \
-		0x1UL                                                                \
-		<< MXC_F_UART_INT_FL_RX_PARITY_ERROR_POS)) /**<                      \
-							      INT_FL_RX_PARITY_ERROR \
-							      Mask */
+#define MXC_F_UART_INT_FL_RX_PARITY_ERROR                                                \
+	((uint32_t)(0x1UL                                                                \
+		    << MXC_F_UART_INT_FL_RX_PARITY_ERROR_POS)) /**<                      \
+								  INT_FL_RX_PARITY_ERROR \
+								  Mask */
 
 #define MXC_F_UART_INT_FL_CTS_CHANGE_POS 2 /**< INT_FL_CTS_CHANGE Position */
 #define MXC_F_UART_INT_FL_CTS_CHANGE                                           \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_INT_FL_CTS_CHANGE_POS)) /**< INT_FL_CTS_CHANGE   \
-							 Mask */
+	((uint32_t)(0x1UL                                                      \
+		    << MXC_F_UART_INT_FL_CTS_CHANGE_POS)) /**<                 \
+							     INT_FL_CTS_CHANGE \
+							     Mask */
 
 #define MXC_F_UART_INT_FL_RX_OVERRUN_POS 3 /**< INT_FL_RX_OVERRUN Position */
 #define MXC_F_UART_INT_FL_RX_OVERRUN                                           \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_INT_FL_RX_OVERRUN_POS)) /**< INT_FL_RX_OVERRUN   \
-							 Mask */
+	((uint32_t)(0x1UL                                                      \
+		    << MXC_F_UART_INT_FL_RX_OVERRUN_POS)) /**<                 \
+							     INT_FL_RX_OVERRUN \
+							     Mask */
 
-#define MXC_F_UART_INT_FL_RX_FIFO_THRESH_POS                                   \
+#define MXC_F_UART_INT_FL_RX_FIFO_THRESH_POS \
 	4 /**< INT_FL_RX_FIFO_THRESH Position */
-#define MXC_F_UART_INT_FL_RX_FIFO_THRESH                                           \
-	((uint32_t)(                                                               \
-		0x1UL                                                              \
-		<< MXC_F_UART_INT_FL_RX_FIFO_THRESH_POS)) /**<                     \
-							     INT_FL_RX_FIFO_THRESH \
-							     Mask */
+#define MXC_F_UART_INT_FL_RX_FIFO_THRESH                                               \
+	((uint32_t)(0x1UL                                                              \
+		    << MXC_F_UART_INT_FL_RX_FIFO_THRESH_POS)) /**<                     \
+								 INT_FL_RX_FIFO_THRESH \
+								 Mask */
 
-#define MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY_POS                             \
+#define MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY_POS \
 	5 /**< INT_FL_TX_FIFO_ALMOST_EMPTY Position */
-#define MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY                                                 \
-	((uint32_t)(                                                                           \
-		0x1UL                                                                          \
-		<< MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY_POS)) /**<                           \
-								   INT_FL_TX_FIFO_ALMOST_EMPTY \
-								   Mask */
-
-#define MXC_F_UART_INT_FL_TX_FIFO_THRESH_POS                                   \
+#define MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY                                                     \
+	((uint32_t)(0x1UL                                                                          \
+		    << MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY_POS)) /**<                           \
+								       INT_FL_TX_FIFO_ALMOST_EMPTY \
+								       Mask */
+
+#define MXC_F_UART_INT_FL_TX_FIFO_THRESH_POS \
 	6 /**< INT_FL_TX_FIFO_THRESH Position */
-#define MXC_F_UART_INT_FL_TX_FIFO_THRESH                                           \
-	((uint32_t)(                                                               \
-		0x1UL                                                              \
-		<< MXC_F_UART_INT_FL_TX_FIFO_THRESH_POS)) /**<                     \
-							     INT_FL_TX_FIFO_THRESH \
-							     Mask */
+#define MXC_F_UART_INT_FL_TX_FIFO_THRESH                                               \
+	((uint32_t)(0x1UL                                                              \
+		    << MXC_F_UART_INT_FL_TX_FIFO_THRESH_POS)) /**<                     \
+								 INT_FL_TX_FIFO_THRESH \
+								 Mask */
 
 #define MXC_F_UART_INT_FL_BREAK_POS 7 /**< INT_FL_BREAK Position */
-#define MXC_F_UART_INT_FL_BREAK                                                \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_UART_INT_FL_BREAK_POS)) /**< INT_FL_BREAK Mask */
+#define MXC_F_UART_INT_FL_BREAK                                              \
+	((uint32_t)(0x1UL << MXC_F_UART_INT_FL_BREAK_POS)) /**< INT_FL_BREAK \
+							      Mask */
 
 #define MXC_F_UART_INT_FL_RX_TIMEOUT_POS 8 /**< INT_FL_RX_TIMEOUT Position */
 #define MXC_F_UART_INT_FL_RX_TIMEOUT                                           \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_INT_FL_RX_TIMEOUT_POS)) /**< INT_FL_RX_TIMEOUT   \
-							 Mask */
+	((uint32_t)(0x1UL                                                      \
+		    << MXC_F_UART_INT_FL_RX_TIMEOUT_POS)) /**<                 \
+							     INT_FL_RX_TIMEOUT \
+							     Mask */
 
 #define MXC_F_UART_INT_FL_LAST_BREAK_POS 9 /**< INT_FL_LAST_BREAK Position */
 #define MXC_F_UART_INT_FL_LAST_BREAK                                           \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_INT_FL_LAST_BREAK_POS)) /**< INT_FL_LAST_BREAK   \
-							 Mask */
+	((uint32_t)(0x1UL                                                      \
+		    << MXC_F_UART_INT_FL_LAST_BREAK_POS)) /**<                 \
+							     INT_FL_LAST_BREAK \
+							     Mask */
 
 /**
  * Baud rate register. Integer portion.
  */
 #define MXC_F_UART_BAUD0_IBAUD_POS 0 /**< BAUD0_IBAUD Position */
-#define MXC_F_UART_BAUD0_IBAUD                                                 \
-	((uint32_t)(0xFFFUL                                                    \
-		    << MXC_F_UART_BAUD0_IBAUD_POS)) /**< BAUD0_IBAUD Mask */
+#define MXC_F_UART_BAUD0_IBAUD                                               \
+	((uint32_t)(0xFFFUL << MXC_F_UART_BAUD0_IBAUD_POS)) /**< BAUD0_IBAUD \
+							       Mask */
 
 #define MXC_F_UART_BAUD0_FACTOR_POS 16 /**< BAUD0_FACTOR Position */
-#define MXC_F_UART_BAUD0_FACTOR                                                \
-	((uint32_t)(0x3UL                                                      \
-		    << MXC_F_UART_BAUD0_FACTOR_POS)) /**< BAUD0_FACTOR Mask */
-#define MXC_V_UART_BAUD0_FACTOR_128                                            \
+#define MXC_F_UART_BAUD0_FACTOR                                              \
+	((uint32_t)(0x3UL << MXC_F_UART_BAUD0_FACTOR_POS)) /**< BAUD0_FACTOR \
+							      Mask */
+#define MXC_V_UART_BAUD0_FACTOR_128 \
 	((uint32_t)0x0UL) /**< BAUD0_FACTOR_128 Value */
-#define MXC_S_UART_BAUD0_FACTOR_128                                            \
-	(MXC_V_UART_BAUD0_FACTOR_128                                           \
-	 << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_128 Setting */
-#define MXC_V_UART_BAUD0_FACTOR_64                                             \
+#define MXC_S_UART_BAUD0_FACTOR_128                          \
+	(MXC_V_UART_BAUD0_FACTOR_128                         \
+	 << MXC_F_UART_BAUD0_FACTOR_POS) /**<                \
+					    BAUD0_FACTOR_128 \
+					    Setting          \
+					  */
+#define MXC_V_UART_BAUD0_FACTOR_64 \
 	((uint32_t)0x1UL) /**< BAUD0_FACTOR_64 Value */
-#define MXC_S_UART_BAUD0_FACTOR_64                                             \
-	(MXC_V_UART_BAUD0_FACTOR_64                                            \
-	 << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_64 Setting */
-#define MXC_V_UART_BAUD0_FACTOR_32                                             \
+#define MXC_S_UART_BAUD0_FACTOR_64                          \
+	(MXC_V_UART_BAUD0_FACTOR_64                         \
+	 << MXC_F_UART_BAUD0_FACTOR_POS) /**<               \
+					    BAUD0_FACTOR_64 \
+					    Setting         \
+					  */
+#define MXC_V_UART_BAUD0_FACTOR_32 \
 	((uint32_t)0x2UL) /**< BAUD0_FACTOR_32 Value */
-#define MXC_S_UART_BAUD0_FACTOR_32                                             \
-	(MXC_V_UART_BAUD0_FACTOR_32                                            \
-	 << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_32 Setting */
-#define MXC_V_UART_BAUD0_FACTOR_16                                             \
+#define MXC_S_UART_BAUD0_FACTOR_32                          \
+	(MXC_V_UART_BAUD0_FACTOR_32                         \
+	 << MXC_F_UART_BAUD0_FACTOR_POS) /**<               \
+					    BAUD0_FACTOR_32 \
+					    Setting         \
+					  */
+#define MXC_V_UART_BAUD0_FACTOR_16 \
 	((uint32_t)0x3UL) /**< BAUD0_FACTOR_16 Value */
-#define MXC_S_UART_BAUD0_FACTOR_16                                             \
-	(MXC_V_UART_BAUD0_FACTOR_16                                            \
-	 << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_16 Setting */
+#define MXC_S_UART_BAUD0_FACTOR_16                          \
+	(MXC_V_UART_BAUD0_FACTOR_16                         \
+	 << MXC_F_UART_BAUD0_FACTOR_POS) /**<               \
+					    BAUD0_FACTOR_16 \
+					    Setting         \
+					  */
 
 /**
  * Baud rate register. Decimal Setting.
  */
 #define MXC_F_UART_BAUD1_DBAUD_POS 0 /**< BAUD1_DBAUD Position */
-#define MXC_F_UART_BAUD1_DBAUD                                                 \
-	((uint32_t)(0xFFFUL                                                    \
-		    << MXC_F_UART_BAUD1_DBAUD_POS)) /**< BAUD1_DBAUD Mask */
+#define MXC_F_UART_BAUD1_DBAUD                                               \
+	((uint32_t)(0xFFFUL << MXC_F_UART_BAUD1_DBAUD_POS)) /**< BAUD1_DBAUD \
+							       Mask */
 
 /**
  * FIFO Data buffer.
  */
 #define MXC_F_UART_FIFO_FIFO_POS 0 /**< FIFO_FIFO Position */
-#define MXC_F_UART_FIFO_FIFO                                                   \
-	((uint32_t)(0xFFUL << MXC_F_UART_FIFO_FIFO_POS)) /**< FIFO_FIFO Mask   \
+#define MXC_F_UART_FIFO_FIFO                                                 \
+	((uint32_t)(0xFFUL << MXC_F_UART_FIFO_FIFO_POS)) /**< FIFO_FIFO Mask \
 							  */
 
-
 /**
  * DMA Configuration.
  */
 #define MXC_F_UART_DMA_TDMA_EN_POS 0 /**< DMA_TDMA_EN Position */
-#define MXC_F_UART_DMA_TDMA_EN                                                 \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_UART_DMA_TDMA_EN_POS)) /**< DMA_TDMA_EN Mask */
-#define MXC_V_UART_DMA_TDMA_EN_DIS                                             \
+#define MXC_F_UART_DMA_TDMA_EN                                             \
+	((uint32_t)(0x1UL << MXC_F_UART_DMA_TDMA_EN_POS)) /**< DMA_TDMA_EN \
+							     Mask */
+#define MXC_V_UART_DMA_TDMA_EN_DIS \
 	((uint32_t)0x0UL) /**< DMA_TDMA_EN_DIS Value */
-#define MXC_S_UART_DMA_TDMA_EN_DIS                                             \
-	(MXC_V_UART_DMA_TDMA_EN_DIS                                            \
-	 << MXC_F_UART_DMA_TDMA_EN_POS) /**< DMA_TDMA_EN_DIS Setting */
-#define MXC_V_UART_DMA_TDMA_EN_EN                                              \
-	((uint32_t)0x1UL) /**< DMA_TDMA_EN_EN Value                            \
+#define MXC_S_UART_DMA_TDMA_EN_DIS                         \
+	(MXC_V_UART_DMA_TDMA_EN_DIS                        \
+	 << MXC_F_UART_DMA_TDMA_EN_POS) /**<               \
+					   DMA_TDMA_EN_DIS \
+					   Setting         \
+					 */
+#define MXC_V_UART_DMA_TDMA_EN_EN                   \
+	((uint32_t)0x1UL) /**< DMA_TDMA_EN_EN Value \
 			   */
-#define MXC_S_UART_DMA_TDMA_EN_EN                                              \
-	(MXC_V_UART_DMA_TDMA_EN_EN                                             \
-	 << MXC_F_UART_DMA_TDMA_EN_POS) /**< DMA_TDMA_EN_EN Setting */
+#define MXC_S_UART_DMA_TDMA_EN_EN                         \
+	(MXC_V_UART_DMA_TDMA_EN_EN                        \
+	 << MXC_F_UART_DMA_TDMA_EN_POS) /**<              \
+					   DMA_TDMA_EN_EN \
+					   Setting        \
+					 */
 
 #define MXC_F_UART_DMA_RXDMA_EN_POS 1 /**< DMA_RXDMA_EN Position */
-#define MXC_F_UART_DMA_RXDMA_EN                                                \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_UART_DMA_RXDMA_EN_POS)) /**< DMA_RXDMA_EN Mask */
-#define MXC_V_UART_DMA_RXDMA_EN_DIS                                            \
+#define MXC_F_UART_DMA_RXDMA_EN                                              \
+	((uint32_t)(0x1UL << MXC_F_UART_DMA_RXDMA_EN_POS)) /**< DMA_RXDMA_EN \
+							      Mask */
+#define MXC_V_UART_DMA_RXDMA_EN_DIS \
 	((uint32_t)0x0UL) /**< DMA_RXDMA_EN_DIS Value */
-#define MXC_S_UART_DMA_RXDMA_EN_DIS                                            \
-	(MXC_V_UART_DMA_RXDMA_EN_DIS                                           \
-	 << MXC_F_UART_DMA_RXDMA_EN_POS) /**< DMA_RXDMA_EN_DIS Setting */
-#define MXC_V_UART_DMA_RXDMA_EN_EN                                             \
+#define MXC_S_UART_DMA_RXDMA_EN_DIS                          \
+	(MXC_V_UART_DMA_RXDMA_EN_DIS                         \
+	 << MXC_F_UART_DMA_RXDMA_EN_POS) /**<                \
+					    DMA_RXDMA_EN_DIS \
+					    Setting          \
+					  */
+#define MXC_V_UART_DMA_RXDMA_EN_EN \
 	((uint32_t)0x1UL) /**< DMA_RXDMA_EN_EN Value */
-#define MXC_S_UART_DMA_RXDMA_EN_EN                                             \
-	(MXC_V_UART_DMA_RXDMA_EN_EN                                            \
-	 << MXC_F_UART_DMA_RXDMA_EN_POS) /**< DMA_RXDMA_EN_EN Setting */
+#define MXC_S_UART_DMA_RXDMA_EN_EN                          \
+	(MXC_V_UART_DMA_RXDMA_EN_EN                         \
+	 << MXC_F_UART_DMA_RXDMA_EN_POS) /**<               \
+					    DMA_RXDMA_EN_EN \
+					    Setting         \
+					  */
 
 #define MXC_F_UART_DMA_TXDMA_LEVEL_POS 8 /**< DMA_TXDMA_LEVEL Position */
-#define MXC_F_UART_DMA_TXDMA_LEVEL                                             \
-	((uint32_t)(0x3FUL                                                     \
-		    << MXC_F_UART_DMA_TXDMA_LEVEL_POS)) /**< DMA_TXDMA_LEVEL   \
+#define MXC_F_UART_DMA_TXDMA_LEVEL                                           \
+	((uint32_t)(0x3FUL                                                   \
+		    << MXC_F_UART_DMA_TXDMA_LEVEL_POS)) /**< DMA_TXDMA_LEVEL \
 							   Mask */
 
 #define MXC_F_UART_DMA_RXDMA_LEVEL_POS 16 /**< DMA_RXDMA_LEVEL Position */
-#define MXC_F_UART_DMA_RXDMA_LEVEL                                             \
-	((uint32_t)(0x3FUL                                                     \
-		    << MXC_F_UART_DMA_RXDMA_LEVEL_POS)) /**< DMA_RXDMA_LEVEL   \
+#define MXC_F_UART_DMA_RXDMA_LEVEL                                           \
+	((uint32_t)(0x3FUL                                                   \
+		    << MXC_F_UART_DMA_RXDMA_LEVEL_POS)) /**< DMA_RXDMA_LEVEL \
 							   Mask */
 
 /**
  * Transmit FIFO Status register.
  */
 #define MXC_F_UART_TX_FIFO_DATA_POS 0 /**< TX_FIFO_DATA Position */
-#define MXC_F_UART_TX_FIFO_DATA                                                \
-	((uint32_t)(0x7FUL                                                     \
-		    << MXC_F_UART_TX_FIFO_DATA_POS)) /**< TX_FIFO_DATA Mask */
+#define MXC_F_UART_TX_FIFO_DATA                                               \
+	((uint32_t)(0x7FUL << MXC_F_UART_TX_FIFO_DATA_POS)) /**< TX_FIFO_DATA \
+							       Mask */
 
 #endif /* _UART_REGS_H_ */
diff --git a/chip/max32660/wdt_chip.c b/chip/max32660/wdt_chip.c
index 1c99c798fc..4890c34536 100644
--- a/chip/max32660/wdt_chip.c
+++ b/chip/max32660/wdt_chip.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,20 +7,20 @@
 
 #include "clock.h"
 #include "common.h"
+#include "config.h"
+#include "console.h"
 #include "gpio.h"
 #include "hooks.h"
+#include "registers.h"
 #include "task.h"
 #include "util.h"
 #include "watchdog.h"
-#include "console.h"
-#include "registers.h"
-#include "board.h"
 #include "wdt_regs.h"
 
 #define CPUTS(outstr) cputs(CC_COMMAND, outstr)
 #define CPRINTS(format, args...) cprints(CC_COMMAND, format, ##args)
 
-/* For a System clock of 96MHz, 
+/* For a System clock of 96MHz,
  *     Time in seconds = 96000000 / 2 * 2^power
  * Example for MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW29
  *     Time in seconds = 96000000 / 2 * 2^29
@@ -56,7 +56,7 @@ int watchdog_init(void)
 	return EC_SUCCESS;
 }
 
-static int command_watchdog_test(int argc, char **argv)
+static int command_watchdog_test(int argc, const char **argv)
 {
 	starve_dog = 1;
 
diff --git a/chip/max32660/wdt_regs.h b/chip/max32660/wdt_regs.h
index 32d6fe0925..440e8e8b0d 100644
--- a/chip/max32660/wdt_regs.h
+++ b/chip/max32660/wdt_regs.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -31,325 +31,347 @@
  */
 typedef struct {
 	__IO uint32_t ctrl; /**< <tt>\b 0x00:<\tt> WDT CTRL Register */
-	__O uint32_t rst;   /**< <tt>\b 0x04:<\tt> WDT RST Register */
+	__O uint32_t rst; /**< <tt>\b 0x04:<\tt> WDT RST Register */
 } mxc_wdt_regs_t;
 
 /**
  * WDT Peripheral Register Offsets from the WDT Base Peripheral
  * Address.
  */
-#define MXC_R_WDT_CTRL                                                         \
-	((uint32_t)0x00000000UL) /**< Offset from WDT Base Address: <tt>       \
+#define MXC_R_WDT_CTRL                                                   \
+	((uint32_t)0x00000000UL) /**< Offset from WDT Base Address: <tt> \
 				    0x0x000 */
-#define MXC_R_WDT_RST                                                          \
-	((uint32_t)0x00000004UL) /**< Offset from WDT Base Address: <tt>       \
+#define MXC_R_WDT_RST                                                    \
+	((uint32_t)0x00000004UL) /**< Offset from WDT Base Address: <tt> \
 				    0x0x004 */
 
 /**
  * Watchdog Timer Control Register.
  */
 #define MXC_F_WDT_CTRL_INT_PERIOD_POS 0 /**< CTRL_INT_PERIOD Position */
-#define MXC_F_WDT_CTRL_INT_PERIOD                                              \
-	((uint32_t)(                                                           \
-		0xFUL << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< CTRL_INT_PERIOD  \
-							    Mask */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW31                                    \
+#define MXC_F_WDT_CTRL_INT_PERIOD                                           \
+	((uint32_t)(0xFUL                                                   \
+		    << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< CTRL_INT_PERIOD \
+							  Mask */
+#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW31 \
 	((uint32_t)0x0UL) /**< CTRL_INT_PERIOD_WDT2POW31 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW31                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW31                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW31      \
+#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW31                               \
+	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW31                              \
+	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW31 \
 					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW30                                    \
+#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW30 \
 	((uint32_t)0x1UL) /**< CTRL_INT_PERIOD_WDT2POW30 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW30                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW30                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW30      \
+#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW30                               \
+	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW30                              \
+	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW30 \
 					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW29                                    \
+#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW29 \
 	((uint32_t)0x2UL) /**< CTRL_INT_PERIOD_WDT2POW29 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW29                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW29                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW29      \
+#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW29                               \
+	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW29                              \
+	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW29 \
 					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW28                                    \
+#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW28 \
 	((uint32_t)0x3UL) /**< CTRL_INT_PERIOD_WDT2POW28 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW28                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW28                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW28      \
+#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW28                               \
+	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW28                              \
+	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW28 \
 					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW27                                    \
+#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW27 \
 	((uint32_t)0x4UL) /**< CTRL_INT_PERIOD_WDT2POW27 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW27                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW27                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW27      \
+#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW27                               \
+	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW27                              \
+	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW27 \
 					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW26                                    \
+#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW26 \
 	((uint32_t)0x5UL) /**< CTRL_INT_PERIOD_WDT2POW26 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW26                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW26                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW26      \
+#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW26                               \
+	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW26                              \
+	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW26 \
 					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW25                                    \
+#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW25 \
 	((uint32_t)0x6UL) /**< CTRL_INT_PERIOD_WDT2POW25 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW25                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW25                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW25      \
+#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW25                               \
+	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW25                              \
+	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW25 \
 					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW24                                    \
+#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW24 \
 	((uint32_t)0x7UL) /**< CTRL_INT_PERIOD_WDT2POW24 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW24                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW24                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW24      \
+#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW24                               \
+	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW24                              \
+	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW24 \
 					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW23                                    \
+#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW23 \
 	((uint32_t)0x8UL) /**< CTRL_INT_PERIOD_WDT2POW23 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW23                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW23                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW23      \
+#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW23                               \
+	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW23                              \
+	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW23 \
 					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW22                                    \
+#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW22 \
 	((uint32_t)0x9UL) /**< CTRL_INT_PERIOD_WDT2POW22 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW22                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW22                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW22      \
+#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW22                               \
+	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW22                              \
+	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW22 \
 					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW21                                    \
+#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW21 \
 	((uint32_t)0xAUL) /**< CTRL_INT_PERIOD_WDT2POW21 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW21                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW21                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW21      \
+#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW21                               \
+	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW21                              \
+	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW21 \
 					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW20                                    \
+#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW20 \
 	((uint32_t)0xBUL) /**< CTRL_INT_PERIOD_WDT2POW20 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW20                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW20                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW20      \
+#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW20                               \
+	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW20                              \
+	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW20 \
 					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW19                                    \
+#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW19 \
 	((uint32_t)0xCUL) /**< CTRL_INT_PERIOD_WDT2POW19 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW19                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW19                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW19      \
+#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW19                               \
+	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW19                              \
+	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW19 \
 					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW18                                    \
+#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW18 \
 	((uint32_t)0xDUL) /**< CTRL_INT_PERIOD_WDT2POW18 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW18                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW18                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW18      \
+#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW18                               \
+	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW18                              \
+	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW18 \
 					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW17                                    \
+#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW17 \
 	((uint32_t)0xEUL) /**< CTRL_INT_PERIOD_WDT2POW17 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW17                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW17                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW17      \
+#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW17                               \
+	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW17                              \
+	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW17 \
 					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW16                                    \
+#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW16 \
 	((uint32_t)0xFUL) /**< CTRL_INT_PERIOD_WDT2POW16 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW16                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW16                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW16      \
+#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW16                               \
+	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW16                              \
+	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW16 \
 					      Setting */
 
 #define MXC_F_WDT_CTRL_RST_PERIOD_POS 4 /**< CTRL_RST_PERIOD Position */
-#define MXC_F_WDT_CTRL_RST_PERIOD                                              \
-	((uint32_t)(                                                           \
-		0xFUL << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< CTRL_RST_PERIOD  \
-							    Mask */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW31                                    \
+#define MXC_F_WDT_CTRL_RST_PERIOD                                           \
+	((uint32_t)(0xFUL                                                   \
+		    << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< CTRL_RST_PERIOD \
+							  Mask */
+#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW31 \
 	((uint32_t)0x0UL) /**< CTRL_RST_PERIOD_WDT2POW31 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW31                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW31                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW31      \
+#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW31                               \
+	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW31                              \
+	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW31 \
 					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW30                                    \
+#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW30 \
 	((uint32_t)0x1UL) /**< CTRL_RST_PERIOD_WDT2POW30 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW30                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW30                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW30      \
+#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW30                               \
+	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW30                              \
+	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW30 \
 					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW29                                    \
+#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW29 \
 	((uint32_t)0x2UL) /**< CTRL_RST_PERIOD_WDT2POW29 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW29                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW29                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW29      \
+#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW29                               \
+	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW29                              \
+	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW29 \
 					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW28                                    \
+#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW28 \
 	((uint32_t)0x3UL) /**< CTRL_RST_PERIOD_WDT2POW28 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW28                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW28                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW28      \
+#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW28                               \
+	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW28                              \
+	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW28 \
 					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW27                                    \
+#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW27 \
 	((uint32_t)0x4UL) /**< CTRL_RST_PERIOD_WDT2POW27 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW27                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW27                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW27      \
+#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW27                               \
+	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW27                              \
+	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW27 \
 					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW26                                    \
+#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW26 \
 	((uint32_t)0x5UL) /**< CTRL_RST_PERIOD_WDT2POW26 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW26                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW26                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW26      \
+#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW26                               \
+	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW26                              \
+	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW26 \
 					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW25                                    \
+#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW25 \
 	((uint32_t)0x6UL) /**< CTRL_RST_PERIOD_WDT2POW25 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW25                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW25                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW25      \
+#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW25                               \
+	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW25                              \
+	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW25 \
 					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW24                                    \
+#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW24 \
 	((uint32_t)0x7UL) /**< CTRL_RST_PERIOD_WDT2POW24 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW24                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW24                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW24      \
+#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW24                               \
+	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW24                              \
+	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW24 \
 					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW23                                    \
+#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW23 \
 	((uint32_t)0x8UL) /**< CTRL_RST_PERIOD_WDT2POW23 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW23                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW23                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW23      \
+#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW23                               \
+	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW23                              \
+	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW23 \
 					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW22                                    \
+#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW22 \
 	((uint32_t)0x9UL) /**< CTRL_RST_PERIOD_WDT2POW22 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW22                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW22                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW22      \
+#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW22                               \
+	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW22                              \
+	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW22 \
 					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW21                                    \
+#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW21 \
 	((uint32_t)0xAUL) /**< CTRL_RST_PERIOD_WDT2POW21 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW21                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW21                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW21      \
+#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW21                               \
+	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW21                              \
+	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW21 \
 					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW20                                    \
+#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW20 \
 	((uint32_t)0xBUL) /**< CTRL_RST_PERIOD_WDT2POW20 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW20                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW20                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW20      \
+#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW20                               \
+	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW20                              \
+	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW20 \
 					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW19                                    \
+#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW19 \
 	((uint32_t)0xCUL) /**< CTRL_RST_PERIOD_WDT2POW19 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW19                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW19                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW19      \
+#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW19                               \
+	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW19                              \
+	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW19 \
 					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW18                                    \
+#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW18 \
 	((uint32_t)0xDUL) /**< CTRL_RST_PERIOD_WDT2POW18 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW18                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW18                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW18      \
+#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW18                               \
+	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW18                              \
+	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW18 \
 					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW17                                    \
+#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW17 \
 	((uint32_t)0xEUL) /**< CTRL_RST_PERIOD_WDT2POW17 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW17                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW17                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW17      \
+#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW17                               \
+	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW17                              \
+	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW17 \
 					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW16                                    \
+#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW16 \
 	((uint32_t)0xFUL) /**< CTRL_RST_PERIOD_WDT2POW16 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW16                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW16                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW16      \
+#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW16                               \
+	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW16                              \
+	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW16 \
 					      Setting */
 
 #define MXC_F_WDT_CTRL_WDT_EN_POS 8 /**< CTRL_WDT_EN Position */
 #define MXC_F_WDT_CTRL_WDT_EN                                                  \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_WDT_CTRL_WDT_EN_POS)) /**< CTRL_WDT_EN Mask */
-#define MXC_V_WDT_CTRL_WDT_EN_DIS                                              \
+	((uint32_t)(0x1UL << MXC_F_WDT_CTRL_WDT_EN_POS)) /**< CTRL_WDT_EN Mask \
+							  */
+#define MXC_V_WDT_CTRL_WDT_EN_DIS \
 	((uint32_t)0x0UL) /**< CTRL_WDT_EN_DIS Value */
-#define MXC_S_WDT_CTRL_WDT_EN_DIS                                              \
-	(MXC_V_WDT_CTRL_WDT_EN_DIS                                             \
-	 << MXC_F_WDT_CTRL_WDT_EN_POS) /**< CTRL_WDT_EN_DIS Setting */
-#define MXC_V_WDT_CTRL_WDT_EN_EN                                               \
-	((uint32_t)0x1UL) /**< CTRL_WDT_EN_EN Value                            \
+#define MXC_S_WDT_CTRL_WDT_EN_DIS                         \
+	(MXC_V_WDT_CTRL_WDT_EN_DIS                        \
+	 << MXC_F_WDT_CTRL_WDT_EN_POS) /**<               \
+					  CTRL_WDT_EN_DIS \
+					  Setting */
+#define MXC_V_WDT_CTRL_WDT_EN_EN                    \
+	((uint32_t)0x1UL) /**< CTRL_WDT_EN_EN Value \
 			   */
-#define MXC_S_WDT_CTRL_WDT_EN_EN                                               \
-	(MXC_V_WDT_CTRL_WDT_EN_EN                                              \
-	 << MXC_F_WDT_CTRL_WDT_EN_POS) /**< CTRL_WDT_EN_EN Setting */
+#define MXC_S_WDT_CTRL_WDT_EN_EN                         \
+	(MXC_V_WDT_CTRL_WDT_EN_EN                        \
+	 << MXC_F_WDT_CTRL_WDT_EN_POS) /**<              \
+					  CTRL_WDT_EN_EN \
+					  Setting */
 
 #define MXC_F_WDT_CTRL_INT_FLAG_POS 9 /**< CTRL_INT_FLAG Position */
-#define MXC_F_WDT_CTRL_INT_FLAG                                                \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_WDT_CTRL_INT_FLAG_POS)) /**< CTRL_INT_FLAG Mask */
-#define MXC_V_WDT_CTRL_INT_FLAG_INACTIVE                                       \
+#define MXC_F_WDT_CTRL_INT_FLAG                                               \
+	((uint32_t)(0x1UL << MXC_F_WDT_CTRL_INT_FLAG_POS)) /**< CTRL_INT_FLAG \
+							      Mask */
+#define MXC_V_WDT_CTRL_INT_FLAG_INACTIVE \
 	((uint32_t)0x0UL) /**< CTRL_INT_FLAG_INACTIVE Value */
-#define MXC_S_WDT_CTRL_INT_FLAG_INACTIVE                                       \
-	(MXC_V_WDT_CTRL_INT_FLAG_INACTIVE                                      \
-	 << MXC_F_WDT_CTRL_INT_FLAG_POS) /**< CTRL_INT_FLAG_INACTIVE Setting   \
+#define MXC_S_WDT_CTRL_INT_FLAG_INACTIVE                                     \
+	(MXC_V_WDT_CTRL_INT_FLAG_INACTIVE                                    \
+	 << MXC_F_WDT_CTRL_INT_FLAG_POS) /**< CTRL_INT_FLAG_INACTIVE Setting \
 					  */
-#define MXC_V_WDT_CTRL_INT_FLAG_PENDING                                        \
+#define MXC_V_WDT_CTRL_INT_FLAG_PENDING \
 	((uint32_t)0x1UL) /**< CTRL_INT_FLAG_PENDING Value */
-#define MXC_S_WDT_CTRL_INT_FLAG_PENDING                                        \
-	(MXC_V_WDT_CTRL_INT_FLAG_PENDING                                       \
-	 << MXC_F_WDT_CTRL_INT_FLAG_POS) /**< CTRL_INT_FLAG_PENDING Setting */
+#define MXC_S_WDT_CTRL_INT_FLAG_PENDING                           \
+	(MXC_V_WDT_CTRL_INT_FLAG_PENDING                          \
+	 << MXC_F_WDT_CTRL_INT_FLAG_POS) /**<                     \
+					    CTRL_INT_FLAG_PENDING \
+					    Setting               \
+					  */
 
 #define MXC_F_WDT_CTRL_INT_EN_POS 10 /**< CTRL_INT_EN Position */
 #define MXC_F_WDT_CTRL_INT_EN                                                  \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_WDT_CTRL_INT_EN_POS)) /**< CTRL_INT_EN Mask */
-#define MXC_V_WDT_CTRL_INT_EN_DIS                                              \
+	((uint32_t)(0x1UL << MXC_F_WDT_CTRL_INT_EN_POS)) /**< CTRL_INT_EN Mask \
+							  */
+#define MXC_V_WDT_CTRL_INT_EN_DIS \
 	((uint32_t)0x0UL) /**< CTRL_INT_EN_DIS Value */
-#define MXC_S_WDT_CTRL_INT_EN_DIS                                              \
-	(MXC_V_WDT_CTRL_INT_EN_DIS                                             \
-	 << MXC_F_WDT_CTRL_INT_EN_POS) /**< CTRL_INT_EN_DIS Setting */
-#define MXC_V_WDT_CTRL_INT_EN_EN                                               \
-	((uint32_t)0x1UL) /**< CTRL_INT_EN_EN Value                            \
+#define MXC_S_WDT_CTRL_INT_EN_DIS                         \
+	(MXC_V_WDT_CTRL_INT_EN_DIS                        \
+	 << MXC_F_WDT_CTRL_INT_EN_POS) /**<               \
+					  CTRL_INT_EN_DIS \
+					  Setting */
+#define MXC_V_WDT_CTRL_INT_EN_EN                    \
+	((uint32_t)0x1UL) /**< CTRL_INT_EN_EN Value \
 			   */
-#define MXC_S_WDT_CTRL_INT_EN_EN                                               \
-	(MXC_V_WDT_CTRL_INT_EN_EN                                              \
-	 << MXC_F_WDT_CTRL_INT_EN_POS) /**< CTRL_INT_EN_EN Setting */
+#define MXC_S_WDT_CTRL_INT_EN_EN                         \
+	(MXC_V_WDT_CTRL_INT_EN_EN                        \
+	 << MXC_F_WDT_CTRL_INT_EN_POS) /**<              \
+					  CTRL_INT_EN_EN \
+					  Setting */
 
 #define MXC_F_WDT_CTRL_RST_EN_POS 11 /**< CTRL_RST_EN Position */
 #define MXC_F_WDT_CTRL_RST_EN                                                  \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_WDT_CTRL_RST_EN_POS)) /**< CTRL_RST_EN Mask */
-#define MXC_V_WDT_CTRL_RST_EN_DIS                                              \
+	((uint32_t)(0x1UL << MXC_F_WDT_CTRL_RST_EN_POS)) /**< CTRL_RST_EN Mask \
+							  */
+#define MXC_V_WDT_CTRL_RST_EN_DIS \
 	((uint32_t)0x0UL) /**< CTRL_RST_EN_DIS Value */
-#define MXC_S_WDT_CTRL_RST_EN_DIS                                              \
-	(MXC_V_WDT_CTRL_RST_EN_DIS                                             \
-	 << MXC_F_WDT_CTRL_RST_EN_POS) /**< CTRL_RST_EN_DIS Setting */
-#define MXC_V_WDT_CTRL_RST_EN_EN                                               \
-	((uint32_t)0x1UL) /**< CTRL_RST_EN_EN Value                            \
+#define MXC_S_WDT_CTRL_RST_EN_DIS                         \
+	(MXC_V_WDT_CTRL_RST_EN_DIS                        \
+	 << MXC_F_WDT_CTRL_RST_EN_POS) /**<               \
+					  CTRL_RST_EN_DIS \
+					  Setting */
+#define MXC_V_WDT_CTRL_RST_EN_EN                    \
+	((uint32_t)0x1UL) /**< CTRL_RST_EN_EN Value \
 			   */
-#define MXC_S_WDT_CTRL_RST_EN_EN                                               \
-	(MXC_V_WDT_CTRL_RST_EN_EN                                              \
-	 << MXC_F_WDT_CTRL_RST_EN_POS) /**< CTRL_RST_EN_EN Setting */
+#define MXC_S_WDT_CTRL_RST_EN_EN                         \
+	(MXC_V_WDT_CTRL_RST_EN_EN                        \
+	 << MXC_F_WDT_CTRL_RST_EN_POS) /**<              \
+					  CTRL_RST_EN_EN \
+					  Setting */
 
 #define MXC_F_WDT_CTRL_RST_FLAG_POS 31 /**< CTRL_RST_FLAG Position */
-#define MXC_F_WDT_CTRL_RST_FLAG                                                \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_WDT_CTRL_RST_FLAG_POS)) /**< CTRL_RST_FLAG Mask */
-#define MXC_V_WDT_CTRL_RST_FLAG_NOEVENT                                        \
+#define MXC_F_WDT_CTRL_RST_FLAG                                               \
+	((uint32_t)(0x1UL << MXC_F_WDT_CTRL_RST_FLAG_POS)) /**< CTRL_RST_FLAG \
+							      Mask */
+#define MXC_V_WDT_CTRL_RST_FLAG_NOEVENT \
 	((uint32_t)0x0UL) /**< CTRL_RST_FLAG_NOEVENT Value */
-#define MXC_S_WDT_CTRL_RST_FLAG_NOEVENT                                        \
-	(MXC_V_WDT_CTRL_RST_FLAG_NOEVENT                                       \
-	 << MXC_F_WDT_CTRL_RST_FLAG_POS) /**< CTRL_RST_FLAG_NOEVENT Setting */
-#define MXC_V_WDT_CTRL_RST_FLAG_OCCURRED                                       \
+#define MXC_S_WDT_CTRL_RST_FLAG_NOEVENT                           \
+	(MXC_V_WDT_CTRL_RST_FLAG_NOEVENT                          \
+	 << MXC_F_WDT_CTRL_RST_FLAG_POS) /**<                     \
+					    CTRL_RST_FLAG_NOEVENT \
+					    Setting               \
+					  */
+#define MXC_V_WDT_CTRL_RST_FLAG_OCCURRED \
 	((uint32_t)0x1UL) /**< CTRL_RST_FLAG_OCCURRED Value */
-#define MXC_S_WDT_CTRL_RST_FLAG_OCCURRED                                       \
-	(MXC_V_WDT_CTRL_RST_FLAG_OCCURRED                                      \
-	 << MXC_F_WDT_CTRL_RST_FLAG_POS) /**< CTRL_RST_FLAG_OCCURRED Setting   \
+#define MXC_S_WDT_CTRL_RST_FLAG_OCCURRED                                     \
+	(MXC_V_WDT_CTRL_RST_FLAG_OCCURRED                                    \
+	 << MXC_F_WDT_CTRL_RST_FLAG_POS) /**< CTRL_RST_FLAG_OCCURRED Setting \
 					  */
 
 /**
  * Watchdog Timer Reset Register.
  */
 #define MXC_F_WDT_RST_WDT_RST_POS 0 /**< RST_WDT_RST Position */
-#define MXC_F_WDT_RST_WDT_RST                                                  \
-	((uint32_t)(                                                           \
-		0xFFUL << MXC_F_WDT_RST_WDT_RST_POS)) /**< RST_WDT_RST Mask */
-#define MXC_V_WDT_RST_WDT_RST_SEQ0                                             \
+#define MXC_F_WDT_RST_WDT_RST                                              \
+	((uint32_t)(0xFFUL << MXC_F_WDT_RST_WDT_RST_POS)) /**< RST_WDT_RST \
+							     Mask */
+#define MXC_V_WDT_RST_WDT_RST_SEQ0 \
 	((uint32_t)0xA5UL) /**< RST_WDT_RST_SEQ0 Value */
-#define MXC_S_WDT_RST_WDT_RST_SEQ0                                             \
-	(MXC_V_WDT_RST_WDT_RST_SEQ0                                            \
-	 << MXC_F_WDT_RST_WDT_RST_POS) /**< RST_WDT_RST_SEQ0 Setting */
-#define MXC_V_WDT_RST_WDT_RST_SEQ1                                             \
+#define MXC_S_WDT_RST_WDT_RST_SEQ0                         \
+	(MXC_V_WDT_RST_WDT_RST_SEQ0                        \
+	 << MXC_F_WDT_RST_WDT_RST_POS) /**<                \
+					  RST_WDT_RST_SEQ0 \
+					  Setting          \
+					*/
+#define MXC_V_WDT_RST_WDT_RST_SEQ1 \
 	((uint32_t)0x5AUL) /**< RST_WDT_RST_SEQ1 Value */
-#define MXC_S_WDT_RST_WDT_RST_SEQ1                                             \
-	(MXC_V_WDT_RST_WDT_RST_SEQ1                                            \
-	 << MXC_F_WDT_RST_WDT_RST_POS) /**< RST_WDT_RST_SEQ1 Setting */
+#define MXC_S_WDT_RST_WDT_RST_SEQ1                         \
+	(MXC_V_WDT_RST_WDT_RST_SEQ1                        \
+	 << MXC_F_WDT_RST_WDT_RST_POS) /**<                \
+					  RST_WDT_RST_SEQ1 \
+					  Setting          \
+					*/
 
 #endif /* _WDT_REGS_H_ */
diff --git a/chip/mchp/adc.c b/chip/mchp/adc.c
index e8ec10a0e5..f09c04d26b 100644
--- a/chip/mchp/adc.c
+++ b/chip/mchp/adc.c
@@ -1,19 +1,18 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "common.h"
 #include "console.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "registers.h"
 #include "task.h"
+#include "tfdp_chip.h"
 #include "timer.h"
 #include "util.h"
-#include "tfdp_chip.h"
 
 /*
  * Conversion on a single channel takes less than 12 ms. Set timeout to
@@ -54,7 +53,7 @@ static int start_single_and_wait(int timeout)
 	/* clear GIRQ single status */
 	MCHP_INT_SOURCE(MCHP_ADC_GIRQ) = MCHP_ADC_GIRQ_SINGLE_BIT;
 	/* make sure all writes are issued before starting conversion */
-	asm volatile ("dsb");
+	asm volatile("dsb");
 
 	/* Start conversion */
 	MCHP_ADC_CTRL |= BIT(1);
@@ -78,7 +77,8 @@ int adc_read_channel(enum adc_channel ch)
 
 	if (start_single_and_wait(ADC_SINGLE_READ_TIME))
 		value = (MCHP_ADC_READ(adc->channel) * adc->factor_mul) /
-			adc->factor_div + adc->shift;
+				adc->factor_div +
+			adc->shift;
 	else
 		value = ADC_READ_ERROR;
 
@@ -106,7 +106,8 @@ int adc_read_all_channels(int *data)
 	for (i = 0; i < ADC_CH_COUNT; ++i) {
 		adc = adc_channels + i;
 		data[i] = (MCHP_ADC_READ(adc->channel) * adc->factor_mul) /
-			  adc->factor_div + adc->shift;
+				  adc->factor_div +
+			  adc->shift;
 	}
 
 exit_all_channels:
@@ -140,7 +141,7 @@ static void adc_init(void)
 }
 DECLARE_HOOK(HOOK_INIT, adc_init, HOOK_PRIO_INIT_ADC);
 
-void adc_interrupt(void)
+static void adc_interrupt(void)
 {
 	MCHP_INT_DISABLE(MCHP_ADC_GIRQ) = MCHP_ADC_GIRQ_SINGLE_BIT;
 
diff --git a/chip/mchp/adc_chip.h b/chip/mchp/adc_chip.h
index 4b1f8df8f1..fa60efa960 100644
--- a/chip/mchp/adc_chip.h
+++ b/chip/mchp/adc_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,15 +17,27 @@ struct adc_t {
 	int channel;
 };
 
-/*
- * Boards must provide this list of ADC channel definitions.
- * This must match the enum adc_channel list provided by the board.
- */
-extern const struct adc_t adc_channels[];
+/* List of ADC channels */
+enum chip_adc_channel {
+	CHIP_ADC_CH0 = 0,
+	CHIP_ADC_CH1,
+	CHIP_ADC_CH2,
+	CHIP_ADC_CH3,
+	CHIP_ADC_CH4,
+	CHIP_ADC_CH5,
+	CHIP_ADC_CH6,
+	CHIP_ADC_CH7,
+	CHIP_ADC_COUNT,
+};
 
 /* Minimum and maximum values returned by adc_read_channel(). */
 #define ADC_READ_MIN 0
+#ifdef CHIP_FAMILY_MEC172X
+/* MEC172x ADC is 12BIT resolution in default */
+#define ADC_READ_MAX 4095
+#else
 #define ADC_READ_MAX 1023
+#endif
 
 /* Just plain id mapping for code readability */
 #define MCHP_ADC_CH(x) (x)
diff --git a/chip/mchp/build.mk b/chip/mchp/build.mk
index cea514ec43..972dd972ae 100644
--- a/chip/mchp/build.mk
+++ b/chip/mchp/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
+# Copyright 2013 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -15,7 +15,7 @@ endif
 # MCHP MEC SoC's have a Cortex-M4 ARM core
 CORE:=cortex-m
 # Allow the full Cortex-M4 instruction set
-CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
+CFLAGS_CPU+=-mcpu=cortex-m4
 
 # JTAG debug with Keil ARM MDK debugger
 # do not allow GCC dwarf debug extensions
@@ -31,8 +31,8 @@ endif
 # Required chip modules
 chip-y=clock.o gpio.o hwtimer.o system.o uart.o port80.o tfdp.o
 chip-$(CONFIG_ADC)+=adc.o
-chip-$(CONFIG_DMA)+=dma.o
-chip-$(CONFIG_HOSTCMD_ESPI)+=espi.o
+chip-$(CONFIG_DMA_CROS)+=dma.o
+chip-$(CONFIG_HOST_INTERFACE_ESPI)+=espi.o
 chip-$(CONFIG_FANS)+=fan.o
 chip-$(CONFIG_FLASH_PHYSICAL)+=flash.o
 chip-$(CONFIG_I2C)+=i2c.o
@@ -43,7 +43,7 @@ chip-$(CONFIG_PWM)+=pwm.o
 chip-$(CONFIG_SPI)+=spi.o qmspi.o
 chip-$(CONFIG_TFDP)+=tfdp.o
 chip-$(CONFIG_WATCHDOG)+=watchdog.o
-ifndef CONFIG_KEYBOARD_NOT_RAW
+ifndef CONFIG_KEYBOARD_DISCRETE
 chip-$(HAS_TASK_KEYSCAN)+=keyboard_raw.o
 endif
 
@@ -58,11 +58,20 @@ ifeq ($(CONFIG_MCHP_LFW_DEBUG),y)
 	TEST_SPI=--test_spi
 endif
 
+# Select chip. Default is MEC170X
+PACK_EC=pack_ec.py
+ifeq ($(CHIP_FAMILY),mec152x)
+	PACK_EC=pack_ec_mec152x.py
+endif
+ifeq ($(CHIP_FAMILY),mec172x)
+	PACK_EC=pack_ec_mec172x.py
+endif
+
 # pack_ec.py creates SPI flash image for MEC
 # _rw_size is CONFIG_RW_SIZE
 # Commands to convert $^ to $@.tmp
 cmd_obj_to_bin = $(OBJCOPY) --gap-fill=0xff -O binary $< $@.tmp1 ; \
-		 ${SCRIPTDIR}/pack_ec.py -o $@.tmp -i $@.tmp1 \
+		 ${SCRIPTDIR}/${PACK_EC} -o $@.tmp -i $@.tmp1 \
 		--loader_file $(chip-lfw-flat) ${TEST_SPI} \
 		--spi_size ${CHIP_SPI_SIZE_KB} \
 		--image_size $(_rw_size) ${SCRIPTVERBOSE}; rm -f $@.tmp1
@@ -74,7 +83,9 @@ chip-lfw-flat = $(out)/RW/$(chip-lfw)-lfw.flat
 objs_lfw = $(patsubst %, $(out)/RW/%-lfw.o, \
 		$(addprefix common/, util gpio) \
 		$(addprefix chip/$(CHIP)/, spi qmspi dma gpio clock hwtimer tfdp) \
-		core/$(CORE)/cpu $(chip-lfw))
+		core/$(CORE)/cpu $(chip-lfw) \
+		builtin/stdlib \
+		)
 
 # reuse version.o (and its dependencies) from main board
 objs_lfw += $(out)/RW/common/version.o
@@ -82,7 +93,7 @@ objs_lfw += $(out)/RW/common/version.o
 dirs-y+=chip/$(CHIP)/lfw
 
 # objs with -lfw suffix are to include lfw's gpio
-$(out)/RW/%-lfw.o: private CC+=-I$(BDIR)/lfw -DLFW=$(EMPTY)
+$(out)/RW/%-lfw.o: private CC+=-Ichip/mchp/lfw -DLFW=$(EMPTY)
 # Remove the lto flag for the loader.  It actually causes it to bloat in size.
 ifeq ($(CONFIG_LTO),y)
 $(out)/RW/%-lfw.o: private CFLAGS_CPU := $(filter-out -flto, $(CFLAGS_CPU))
@@ -91,6 +102,15 @@ $(out)/RW/%-lfw.o: %.c
 	$(call quiet,c_to_o,CC     )
 
 # let lfw's elf link only with selected objects
+ifeq ($(CHIP_FAMILY),mec172x)
+$(out)/RW/%-lfw.elf: private objs = $(objs_lfw)
+$(out)/RW/%-lfw.elf: override shlib :=
+$(out)/RW/%-lfw.elf: %_416kb.ld $(objs_lfw)
+	$(call quiet,elf,LD     )
+
+# final image needs lfw loader
+$(out)/$(PROJECT).bin: $(chip-lfw-flat)
+else
 $(out)/RW/%-lfw.elf: private objs = $(objs_lfw)
 $(out)/RW/%-lfw.elf: override shlib :=
 $(out)/RW/%-lfw.elf: %.ld $(objs_lfw)
@@ -98,3 +118,4 @@ $(out)/RW/%-lfw.elf: %.ld $(objs_lfw)
 
 # final image needs lfw loader
 $(out)/$(PROJECT).bin: $(chip-lfw-flat)
+endif
diff --git a/chip/mchp/clock.c b/chip/mchp/clock.c
index 9fdb058898..812825db5a 100644
--- a/chip/mchp/clock.c
+++ b/chip/mchp/clock.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,25 +17,25 @@
 #include "shared_mem.h"
 #include "system.h"
 #include "task.h"
+#include "tfdp_chip.h"
 #include "timer.h"
 #include "uart.h"
 #include "util.h"
-#include "tfdp_chip.h"
 #include "vboot_hash.h"
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args)
 
 #ifdef CONFIG_LOW_POWER_IDLE
 
-#define HTIMER_DIV_1_US_MAX	(1998848)
-#define HTIMER_DIV_1_1SEC	(0x8012)
+#define HTIMER_DIV_1_US_MAX (1998848)
+#define HTIMER_DIV_1_1SEC (0x8012)
 
-/* Recovery time for HvySlp2 is 0 usec */
-#define HEAVY_SLEEP_RECOVER_TIME_USEC   75
+/* Recovery time for HvySlp2 is 0 us */
+#define HEAVY_SLEEP_RECOVER_TIME_USEC 75
 
-#define SET_HTIMER_DELAY_USEC           200
+#define SET_HTIMER_DELAY_USEC 200
 
 static int idle_sleep_cnt;
 static int idle_dsleep_cnt;
@@ -52,7 +52,7 @@ static uint32_t ecia_result[MCHP_INT_GIRQ_NUM];
  * boot in order to give a permanent window in which the heavy sleep
  * mode is not used.
  */
-#define CONSOLE_IN_USE_ON_BOOT_TIME (15*SECOND)
+#define CONSOLE_IN_USE_ON_BOOT_TIME (15 * SECOND)
 static int console_in_use_timeout_sec = 60;
 static timestamp_t console_expire_time;
 #endif /*CONFIG_LOW_POWER_IDLE */
@@ -62,7 +62,8 @@ static int freq = 48000000;
 void clock_wait_cycles(uint32_t cycles)
 {
 	asm volatile("1: subs %0, #1\n"
-		     "   bne 1b\n" : "+r"(cycles));
+		     "   bne 1b\n"
+		     : "+r"(cycles));
 }
 
 int clock_get_freq(void)
@@ -70,6 +71,51 @@ int clock_get_freq(void)
 	return freq;
 }
 
+/*
+ * MEC170x and MEC152x have the same 32 KHz clock enable hardware.
+ * MEC172x 32 KHz clock configuration is different and includes
+ * hardware to check the crystal before switching and to monitor
+ * the 32 KHz input if desired.
+ */
+#ifdef CHIP_FAMILY_MEC172X
+/* 32 KHz crystal connected in parallel */
+static inline void config_32k_src_crystal(void)
+{
+	MCHP_VBAT_CSS = MCHP_VBAT_CSS_XTAL_EN | MCHP_VBAT_CSS_SRC_XTAL;
+}
+
+/* 32 KHz source is 32KHZ_IN pin which must be configured */
+static inline void config_32k_src_se_input(void)
+{
+	MCHP_VBAT_CSS = MCHP_VBAT_CSS_SIL32K_EN | MCHP_VBAT_CSS_SRC_SWPS;
+}
+
+static inline void config_32k_src_sil_osc(void)
+{
+	MCHP_VBAT_CSS = MCHP_VBAT_CSS_SIL32K_EN;
+}
+
+#else
+static void config_32k_src_crystal(void)
+{
+	MCHP_VBAT_CE = MCHP_VBAT_CE_XOSEL_PAR |
+		       MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_CRYSTAL;
+}
+
+/* 32 KHz source is 32KHZ_IN pin which must be configured */
+static inline void config_32k_src_se_input(void)
+{
+	MCHP_VBAT_CE = MCHP_VBAT_CE_32K_DOMAIN_32KHZ_IN_PIN |
+		       MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_INT;
+}
+
+static inline void config_32k_src_sil_osc(void)
+{
+	MCHP_VBAT_CE = ~(MCHP_VBAT_CE_32K_DOMAIN_32KHZ_IN_PIN |
+			 MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_CRYSTAL);
+}
+#endif
+
 /** clock_init
  * @note
  * MCHP MEC implements 4 control bits in the VBAT Clock Enable register.
@@ -94,32 +140,19 @@ int clock_get_freq(void)
  */
 void clock_init(void)
 {
-	int __attribute__((unused)) unused;
-
-	trace0(0, MEC, 0, "Clock Init");
-
-#ifdef CONFIG_CLOCK_CRYSTAL
-	/* XOSEL: 0 = Parallel resonant crystal */
-	MCHP_VBAT_CE &= ~(1ul << 3);
-
-#else
-	/* XOSEL: 1 = Single ended clock source */
-	MCHP_VBAT_CE |= (1ul << 3);
-#endif
-
-	/* 32K clock enable */
-	MCHP_VBAT_CE = (MCHP_VBAT_CE & ~(0x03)) | (1ul << 2);
+	if (IS_ENABLED(CONFIG_CLOCK_SRC_EXTERNAL))
+		if (IS_ENABLED(CONFIG_CLOCK_CRYSTAL))
+			config_32k_src_crystal();
+		else
+			/* 32KHz 50% duty waveform on 32KHZ_IN pin */
+			config_32k_src_se_input();
+	else
+		/* Use internal silicon 32KHz OSC */
+		config_32k_src_sil_osc();
 
-#ifdef CONFIG_CLOCK_CRYSTAL
-	/* Wait for crystal to stabilize (OSC_LOCK == 1) */
+	/* Wait for PLL to lock onto 32KHz source (OSC_LOCK == 1) */
 	while (!(MCHP_PCR_CHIP_OSC_ID & 0x100))
 		;
-#endif
-	trace0(0, MEC, 0, "PLL OSC is Locked");
-#ifndef LFW
-	unused = shared_mem_size();
-	trace11(0, MEC, 0, "Shared Memory size = 0x%08x", (uint32_t)unused);
-#endif
 }
 
 /**
@@ -137,14 +170,12 @@ static void clock_turbo_disable(void)
 	else
 #endif
 		/* Use 12 MHz processor clock for power savings */
-		MCHP_PCR_PROC_CLK_CTL = 4;
+		MCHP_PCR_PROC_CLK_CTL = MCHP_PCR_CLK_CTL_12MHZ;
 }
-DECLARE_HOOK(HOOK_INIT,
-		clock_turbo_disable,
-		HOOK_PRIO_INIT_VBOOT_HASH + 1);
+DECLARE_HOOK(HOOK_INIT, clock_turbo_disable, HOOK_PRIO_INIT_VBOOT_HASH + 1);
 
 /**
- * initialization of Hibernation timer0
+ * initialization of Hibernation timer 0
  * Clear PCR sleep enable.
  * GIRQ=21, aggregator bit = 1, Direct NVIC = 112
  * NVIC direct connect interrupts are used for all peripherals
@@ -155,10 +186,8 @@ void htimer_init(void)
 {
 	MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_HTMR0);
 	MCHP_HTIMER_PRELOAD(0) = 0; /* disable at beginning */
-	MCHP_INT_SOURCE(MCHP_HTIMER_GIRQ) =
-			MCHP_HTIMER_GIRQ_BIT(0);
-	MCHP_INT_ENABLE(MCHP_HTIMER_GIRQ) =
-			MCHP_HTIMER_GIRQ_BIT(0);
+	MCHP_INT_SOURCE(MCHP_HTIMER_GIRQ) = MCHP_HTIMER_GIRQ_BIT(0);
+	MCHP_INT_ENABLE(MCHP_HTIMER_GIRQ) = MCHP_HTIMER_GIRQ_BIT(0);
 
 	task_enable_irq(MCHP_IRQ_HTIMER0);
 }
@@ -171,22 +200,18 @@ void htimer_init(void)
  * @param microseconds Number of microseconds before htimer interrupt
  * @note hibernation timer input clock is 32.768KHz.
  * Control register bit[0] selects the divider.
- * 0 is divide by 1 for 30.5us per LSB for a maximum of
- *	65535 * 30.5us = 1998817.5 us or 32.786 counts per second
- * 1 is divide by 4096 for 0.125s per LSB for a maximum of ~2 hours.
- *	65535 * 0.125s ~ 8192 s = 2.27 hours
+ * 0 is divide by 1 for 30.5 us per LSB for a maximum of
+ *	65535 * 30.5 us = 1998817.5 us or 32.786 counts per second
+ * 1 is divide by 4096 for 0.125 s per LSB for a maximum of ~2 hours.
+ *	65535 * 0.125 s ~ 8192 s = 2.27 hours
  */
-void system_set_htimer_alarm(uint32_t seconds,
-		uint32_t microseconds)
+void system_set_htimer_alarm(uint32_t seconds, uint32_t microseconds)
 {
 	uint32_t hcnt, ns;
 	uint8_t hctrl;
 
 	MCHP_HTIMER_PRELOAD(0) = 0; /* disable */
 
-	trace12(0, SLP, 0, "sys set htimer: sec=%d us=%d",
-		seconds, microseconds);
-
 	if (microseconds > 1000000ul) {
 		ns = (microseconds / 1000000ul);
 		microseconds %= 1000000ul;
@@ -197,23 +222,20 @@ void system_set_htimer_alarm(uint32_t seconds,
 	}
 
 	if (seconds > 1) {
-		hcnt = (seconds << 3);	/* divide by 0.125 */
+		hcnt = (seconds << 3); /* divide by 0.125 */
 		if (hcnt > 0xfffful)
 			hcnt = 0xfffful;
 		hctrl = 1;
 	} else {
 		/*
 		 * approximate(~2% error) as seconds is 0 or 1
-		 * seconds / 30.5e-6 + microseonds / 30.5
+		 * seconds / 30.5e-6 + microseconds / 30.5
 		 */
 		hcnt = (seconds << 15) + (microseconds >> 5) +
-			(microseconds >> 10);
+		       (microseconds >> 10);
 		hctrl = 0;
 	}
 
-	trace12(0, SLP, 0,
-		"sys set htimer: ctrl=0x%0x preload=0x%0x",
-		hctrl, hcnt);
 	MCHP_HTIMER_CONTROL(0) = hctrl;
 	MCHP_HTIMER_PRELOAD(0) = hcnt;
 }
@@ -228,19 +250,18 @@ static timestamp_t system_get_htimer(void)
 	uint16_t count;
 	timestamp_t time;
 
-	count =  MCHP_HTIMER_COUNT(0);
-
+	count = MCHP_HTIMER_COUNT(0);
 
 	if (MCHP_HTIMER_CONTROL(0) == 1) /* if > 2 sec */
 		/* 0.125 sec per count */
 		time.le.lo = (uint32_t)(count * 125000);
-	else    /* if < 2 sec */
-		/* 30.5(=61/2)usec per count */
+	else /* if < 2 sec */
+		/* 30.5(=61/2) us per count */
 		time.le.lo = (uint32_t)(count * 61 / 2);
 
 	time.le.hi = 0;
 
-	return time;  /* in uSec */
+	return time; /* in uSec */
 }
 
 /**
@@ -249,8 +270,7 @@ static timestamp_t system_get_htimer(void)
 static void system_reset_htimer_alarm(void)
 {
 	MCHP_HTIMER_PRELOAD(0) = 0;
-	MCHP_INT_SOURCE(MCHP_HTIMER_GIRQ) =
-			MCHP_HTIMER_GIRQ_BIT(0);
+	MCHP_INT_SOURCE(MCHP_HTIMER_GIRQ) = MCHP_HTIMER_GIRQ_BIT(0);
 }
 
 #ifdef CONFIG_MCHP_DEEP_SLP_DEBUG
@@ -260,10 +280,10 @@ static void print_pcr_regs(void)
 
 	trace0(0, MEC, 0, "Current PCR registers");
 	for (i = 0; i < 5; i++) {
-		trace12(0, MEC, 0, "REG  SLP_EN[%d] = 0x%08X",
-			i, MCHP_PCR_SLP_EN(i));
-		trace12(0, MEC, 0, "REG CLK_REQ[%d] = 0x%08X",
-			i, MCHP_PCR_CLK_REQ(i));
+		trace12(0, MEC, 0, "REG  SLP_EN[%d] = 0x%08X", i,
+			MCHP_PCR_SLP_EN(i));
+		trace12(0, MEC, 0, "REG CLK_REQ[%d] = 0x%08X", i,
+			MCHP_PCR_CLK_REQ(i));
 	}
 }
 
@@ -272,10 +292,9 @@ static void print_ecia_regs(void)
 	int i;
 
 	trace0(0, MEC, 0, "Current GIRQn.Result registers");
-	for (i = MCHP_INT_GIRQ_FIRST;
-			i <= MCHP_INT_GIRQ_LAST; i++)
-		trace12(0, MEC, 0, "GIRQ[%d].Result = 0x%08X",
-			i, MCHP_INT_RESULT(i));
+	for (i = MCHP_INT_GIRQ_FIRST; i <= MCHP_INT_GIRQ_LAST; i++)
+		trace12(0, MEC, 0, "GIRQ[%d].Result = 0x%08X", i,
+			MCHP_INT_RESULT(i));
 }
 
 static void save_regs(void)
@@ -288,8 +307,7 @@ static void save_regs(void)
 	}
 
 	for (i = 0; i < MCHP_INT_GIRQ_NUM; i++)
-		ecia_result[i] =
-			MCHP_INT_RESULT(MCHP_INT_GIRQ_FIRST + i);
+		ecia_result[i] = MCHP_INT_RESULT(MCHP_INT_GIRQ_FIRST + i);
 }
 
 static void print_saved_regs(void)
@@ -298,15 +316,28 @@ static void print_saved_regs(void)
 
 	trace0(0, BRD, 0, "Before sleep saved registers");
 	for (i = 0; i < MCHP_PCR_SLP_RST_REG_MAX; i++) {
-		trace12(0, BRD, 0, "PCR_SLP_EN[%d]  = 0x%08X",
-			i, pcr_slp_en[i]);
-		trace12(0, BRD, 0, "PCR_CLK_REQ[%d] = 0x%08X",
-			i, pcr_clk_req[i]);
+		trace12(0, BRD, 0, "PCR_SLP_EN[%d]  = 0x%08X", i,
+			pcr_slp_en[i]);
+		trace12(0, BRD, 0, "PCR_CLK_REQ[%d] = 0x%08X", i,
+			pcr_clk_req[i]);
 	}
 
 	for (i = 0; i < MCHP_INT_GIRQ_NUM; i++)
 		trace12(0, BRD, 0, "GIRQ[%d].Result = 0x%08X",
-			(i+MCHP_INT_GIRQ_FIRST), ecia_result[i]);
+			(i + MCHP_INT_GIRQ_FIRST), ecia_result[i]);
+}
+#else
+static __maybe_unused void print_pcr_regs(void)
+{
+}
+static __maybe_unused void print_ecia_regs(void)
+{
+}
+static __maybe_unused void save_regs(void)
+{
+}
+static __maybe_unused void print_saved_regs(void)
+{
 }
 #endif /* #ifdef CONFIG_MCHP_DEEP_SLP_DEBUG */
 
@@ -320,7 +351,7 @@ static void print_saved_regs(void)
  * 3. System sleeps
  * 4. wake event wakes system
  * 5. HW restores original values of all PCR.SLP_EN registers
- * NOTE1: Current RTOS core (Cortex-Mx) does not use SysTick timer.
+ * NOTE1: Current RTOS core (Cortex-M4) does not use SysTick timer.
  * We can leave code to disable it but do not re-enable on wake.
  * NOTE2: Some peripherals will not sleep until outstanding transactions
  * are complete: I2C, DMA, GPSPI, QMSPI, etc.
@@ -330,8 +361,6 @@ static void print_saved_regs(void)
  */
 static void prepare_for_deep_sleep(void)
 {
-	trace0(0, MEC, 0, "Prepare for Deep Sleep");
-
 	/* sysTick timer */
 	CPU_NVIC_ST_CTRL &= ~ST_ENABLE;
 	CPU_NVIC_ST_CTRL &= ~ST_COUNTFLAG;
@@ -348,25 +377,20 @@ static void prepare_for_deep_sleep(void)
 	MCHP_TMR32_CTL(1) &= ~1;
 #ifdef CONFIG_WATCHDOG_HELP
 	MCHP_TMR16_CTL(0) &= ~1;
-	MCHP_INT_DISABLE(MCHP_TMR16_GIRQ) =
-			MCHP_TMR16_GIRQ_BIT(0);
-	MCHP_INT_SOURCE(MCHP_TMR16_GIRQ) =
-			MCHP_TMR16_GIRQ_BIT(0);
+	MCHP_INT_DISABLE(MCHP_TMR16_GIRQ) = MCHP_TMR16_GIRQ_BIT(0);
+	MCHP_INT_SOURCE(MCHP_TMR16_GIRQ) = MCHP_TMR16_GIRQ_BIT(0);
 #endif
 	MCHP_INT_DISABLE(MCHP_TMR32_GIRQ) =
-			MCHP_TMR32_GIRQ_BIT(0) +
-			MCHP_TMR32_GIRQ_BIT(1);
+		MCHP_TMR32_GIRQ_BIT(0) + MCHP_TMR32_GIRQ_BIT(1);
 	MCHP_INT_SOURCE(MCHP_TMR32_GIRQ) =
-			MCHP_TMR32_GIRQ_BIT(0) +
-			MCHP_TMR32_GIRQ_BIT(1);
+		MCHP_TMR32_GIRQ_BIT(0) + MCHP_TMR32_GIRQ_BIT(1);
 
 #ifdef CONFIG_WATCHDOG
 	/* Stop watchdog */
 	MCHP_WDG_CTL &= ~1;
 #endif
 
-
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	MCHP_INT_SOURCE(22) = MCHP_INT22_WAKE_ONLY_ESPI;
 	MCHP_INT_ENABLE(22) = MCHP_INT22_WAKE_ONLY_ESPI;
 #else
@@ -377,14 +401,16 @@ static void prepare_for_deep_sleep(void)
 #ifdef CONFIG_ADC
 	/*
 	 * Clear ADC activate bit. If a conversion is in progress the
-	 * ADC block will not enter low power until the converstion is
+	 * ADC block will not enter low power until the conversion is
 	 * complete.
 	 */
 	MCHP_ADC_CTRL &= ~1;
 #endif
 
 	/* stop Port80 capture timer */
+#ifndef CHIP_FAMILY_MEC172X
 	MCHP_P80_ACTIVATE(0) = 0;
+#endif
 
 	/*
 	 * Clear SLP_EN bit(s) for wake sources.
@@ -417,9 +443,7 @@ static void prepare_for_deep_sleep(void)
 
 static void resume_from_deep_sleep(void)
 {
-	trace0(0, MEC, 0, "resume_from_deep_sleep");
-
-	MCHP_PCR_SYS_SLP_CTL = 0x00;  /* default */
+	MCHP_PCR_SYS_SLP_CTL = 0x00; /* default */
 
 	/* Disable assertion of DeepSleep signal when core executes WFI */
 	CPU_SCB_SYSCTRL &= ~BIT(2);
@@ -446,24 +470,26 @@ static void resume_from_deep_sleep(void)
 	 */
 	MCHP_PCR_SLP_EN3 |= (MCHP_PCR_SLP_EN3_HTMR0);
 
-#ifdef CONFIG_HOSTCMD_ESPI
-	#ifdef CONFIG_POWER_S0IX
+#ifdef CONFIG_HOST_INTERFACE_ESPI
+#ifdef CONFIG_POWER_S0IX
 	MCHP_INT_DISABLE(22) = MCHP_INT22_WAKE_ONLY_ESPI;
 	MCHP_INT_SOURCE(22) = MCHP_INT22_WAKE_ONLY_ESPI;
-	#else
+#else
 	MCHP_ESPI_ACTIVATE |= 1;
-	#endif
+#endif
 #else
-	#ifdef CONFIG_POWER_S0IX
+#ifdef CONFIG_POWER_S0IX
 	MCHP_INT_DISABLE(22) = MCHP_INT22_WAKE_ONLY_LPC;
 	MCHP_INT_SOURCE(22) = MCHP_INT22_WAKE_ONLY_LPC;
-	#else
+#else
 	MCHP_LPC_ACT |= 1;
-	#endif
+#endif
 #endif
 
-	/* re-enable Port80 capture */
+	/* re-enable Port 80 capture */
+#ifndef CHIP_FAMILY_MEC172X
 	MCHP_P80_ACTIVATE(0) = 1;
+#endif
 
 #ifdef CONFIG_ADC
 	MCHP_ADC_CTRL |= 1;
@@ -474,10 +500,8 @@ static void resume_from_deep_sleep(void)
 	MCHP_TMR32_CTL(1) |= 1;
 	MCHP_TMR16_CTL(0) |= 1;
 	MCHP_INT_ENABLE(MCHP_TMR32_GIRQ) =
-			MCHP_TMR32_GIRQ_BIT(0) +
-			MCHP_TMR32_GIRQ_BIT(1);
-	MCHP_INT_ENABLE(MCHP_TMR16_GIRQ) =
-			MCHP_TMR16_GIRQ_BIT(0);
+		MCHP_TMR32_GIRQ_BIT(0) + MCHP_TMR32_GIRQ_BIT(1);
+	MCHP_INT_ENABLE(MCHP_TMR16_GIRQ) = MCHP_TMR16_GIRQ_BIT(0);
 
 	/* Enable watchdog */
 #ifdef CONFIG_WATCHDOG
@@ -490,7 +514,6 @@ static void resume_from_deep_sleep(void)
 #endif
 }
 
-
 void clock_refresh_console_in_use(void)
 {
 	disable_sleep(SLEEP_MASK_CONSOLE);
@@ -516,43 +539,38 @@ void __idle(void)
 	htimer_init(); /* hibernation timer initialize */
 
 	disable_sleep(SLEEP_MASK_CONSOLE);
-	console_expire_time.val = get_time().val +
-			CONSOLE_IN_USE_ON_BOOT_TIME;
-
+	console_expire_time.val = get_time().val + CONSOLE_IN_USE_ON_BOOT_TIME;
 
 	/*
 	 * Print when the idle task starts. This is the lowest priority
 	 * task, so this only starts once all other tasks have gotten a
-	 * chance to do their task inits and have gone to sleep.
+	 * chance to do their task initializations and have gone to sleep.
 	 */
-	CPRINTS("MEC1701 low power idle task started");
+	CPRINTS("MEC low power idle task started");
 
 	while (1) {
 		/* Disable interrupts */
 		interrupt_disable();
 
-		t0 = get_time();  /* uSec */
+		t0 = get_time(); /* uSec */
 
 		/* __hw_clock_event_get() is next programmed timer event */
 		next_delay = __hw_clock_event_get() - t0.le.lo;
 
-		time_for_dsleep = next_delay >
-			(HEAVY_SLEEP_RECOVER_TIME_USEC +
-			SET_HTIMER_DELAY_USEC);
+		time_for_dsleep = next_delay > (HEAVY_SLEEP_RECOVER_TIME_USEC +
+						SET_HTIMER_DELAY_USEC);
 
-		max_sleep_time = next_delay -
-				HEAVY_SLEEP_RECOVER_TIME_USEC;
+		max_sleep_time = next_delay - HEAVY_SLEEP_RECOVER_TIME_USEC;
 
 		/* check if there enough time for deep sleep */
 		if (DEEP_SLEEP_ALLOWED && time_for_dsleep) {
-			trace0(0, MEC, 0, "Enough time for Deep Sleep");
 			/*
 			 * Check if the console use has expired and
 			 * console sleep is masked by GPIO(UART-RX)
 			 * interrupt.
 			 */
 			if ((sleep_mask & SLEEP_MASK_CONSOLE) &&
-				t0.val > console_expire_time.val) {
+			    t0.val > console_expire_time.val) {
 				/* allow console to sleep. */
 				enable_sleep(SLEEP_MASK_CONSOLE);
 
@@ -564,29 +582,26 @@ void __idle(void)
 				clock_wait_cycles(1);
 
 				if (LOW_SPEED_DEEP_SLEEP_ALLOWED)
-					CPRINTS("MEC1701 Disable console "
-						"in deepsleep");
+					CPRINTS("MEC Disable console "
+						"in deep sleep");
 			}
 
-
 			/* UART is not being used  */
 			uart_ready_for_deepsleep =
 				LOW_SPEED_DEEP_SLEEP_ALLOWED &&
-					!uart_tx_in_progress() &&
-					uart_buffer_empty();
+				!uart_tx_in_progress() && uart_buffer_empty();
 
 			/*
 			 * Since MCHP's heavy sleep mode requires all
-			 * blocks to be sleepable, UART/console's
+			 * blocks to be sleep capable, UART/console
 			 * readiness is final decision factor of
 			 * heavy sleep of EC.
 			 */
 			if (uart_ready_for_deepsleep) {
-
 				idle_dsleep_cnt++;
 
 				/*
-				 * config UART Rx as GPIO wakeup
+				 * configure UART Rx as GPIO wakeup
 				 * interrupt source
 				 */
 				uart_enter_dsleep();
@@ -598,20 +613,16 @@ void __idle(void)
 				 * 'max_sleep_time' value should be big
 				 * enough so that hibernation timer's
 				 * interrupt triggers only after 'wfi'
-				 * completes its excution.
+				 * completes its execution.
 				 */
-				max_sleep_time -=
-					(get_time().le.lo - t0.le.lo);
+				max_sleep_time -= (get_time().le.lo - t0.le.lo);
 
 				/* setup/enable htimer wakeup interrupt */
-				system_set_htimer_alarm(0,
-						max_sleep_time);
+				system_set_htimer_alarm(0, max_sleep_time);
 
 				/* set sleep all just before WFI */
-				MCHP_PCR_SYS_SLP_CTL |=
-						MCHP_PCR_SYS_SLP_HEAVY;
-				MCHP_PCR_SYS_SLP_CTL |=
-						MCHP_PCR_SYS_SLP_ALL;
+				MCHP_PCR_SYS_SLP_CTL |= MCHP_PCR_SYS_SLP_HEAVY;
+				MCHP_PCR_SYS_SLP_CTL |= MCHP_PCR_SYS_SLP_ALL;
 
 			} else {
 				idle_sleep_cnt++;
@@ -619,12 +630,11 @@ void __idle(void)
 
 			/* Wait for interrupt: goes into deep sleep. */
 			asm("dsb");
-			asm("wfi");
+			cpu_enter_suspend_mode();
 			asm("isb");
 			asm("nop");
 
 			if (uart_ready_for_deepsleep) {
-
 				resume_from_deep_sleep();
 
 				/*
@@ -643,27 +653,25 @@ void __idle(void)
 				/* disable/clear htimer wakeup interrupt */
 				system_reset_htimer_alarm();
 
-				t1.val = t0.val +
-					(uint64_t)(max_sleep_time -
-							ht_t1.le.lo);
+				t1.val = t0.val + (uint64_t)(max_sleep_time -
+							     ht_t1.le.lo);
 
 				force_time(t1);
 
-				/* re-eanble UART */
+				/* re-enable UART */
 				uart_exit_dsleep();
 
 				/* Record time spent in deep sleep. */
 				total_idle_dsleep_time_us +=
 					(uint64_t)(max_sleep_time -
-							ht_t1.le.lo);
+						   ht_t1.le.lo);
 			}
 
 		} else { /* CPU 'Sleep' mode */
 
 			idle_sleep_cnt++;
 
-			asm("wfi");
-
+			cpu_enter_suspend_mode();
 		}
 
 		interrupt_enable();
@@ -675,47 +683,30 @@ void __idle(void)
  * Print low power idle statistics
  */
 
-#ifdef CONFIG_MCHP_DEEP_SLP_DEBUG
-static void print_pcr_regs(void)
-{
-	int i;
-
-	ccprintf("PCR regs before WFI\n");
-	for (i = 0; i < 5; i++) {
-		ccprintf("PCR SLP_EN[%d]  = 0x%08X\n", pcr_slp_en[i]);
-		ccprintf("PCR CLK_REQ[%d] = 0x%08X\n", pcr_clk_req[i]);
-	}
-}
-#endif
-
-static int command_idle_stats(int argc, char **argv)
+static int command_idle_stats(int argc, const char **argv)
 {
 	timestamp_t ts = get_time();
 
-	ccprintf("Num idle calls that sleep:           %d\n",
-			idle_sleep_cnt);
-	ccprintf("Num idle calls that deep-sleep:      %d\n",
-			idle_dsleep_cnt);
+	ccprintf("Num idle calls that sleep:           %d\n", idle_sleep_cnt);
+	ccprintf("Num idle calls that deep-sleep:      %d\n", idle_dsleep_cnt);
 
 	ccprintf("Total Time spent in deep-sleep(sec): %.6lld(s)\n",
-			total_idle_dsleep_time_us);
-	ccprintf("Total time on:                       %.6llds\n\n",
-			ts.val);
+		 total_idle_dsleep_time_us);
+	ccprintf("Total time on:                       %.6llds\n\n", ts.val);
+
+	if (IS_ENABLED(CONFIG_MCHP_DEEP_SLP_DEBUG))
+		print_pcr_regs(); /* debug */
 
-#ifdef CONFIG_MCHP_DEEP_SLP_DEBUG
-	print_pcr_regs();	/* debug */
-#endif
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats,
-			"",
+DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, "",
 			"Print last idle stats");
 #endif /* defined(CONFIG_CMD_IDLE_STATS) */
 
 /**
  * Configure deep sleep clock settings.
  */
-static int command_dsleep(int argc, char **argv)
+static int command_dsleep(int argc, const char **argv)
 {
 	int v;
 
@@ -725,12 +716,10 @@ static int command_dsleep(int argc, char **argv)
 			 * Force deep sleep not to use heavy sleep mode or
 			 * allow it to use the heavy sleep mode.
 			 */
-			if (v)  /* 'on' */
-				disable_sleep(
-					SLEEP_MASK_FORCE_NO_LOW_SPEED);
-			else    /* 'off' */
-				enable_sleep(
-					SLEEP_MASK_FORCE_NO_LOW_SPEED);
+			if (v) /* 'on' */
+				disable_sleep(SLEEP_MASK_FORCE_NO_LOW_SPEED);
+			else /* 'off' */
+				enable_sleep(SLEEP_MASK_FORCE_NO_LOW_SPEED);
 		} else {
 			/* Set console in use timeout. */
 			char *e;
@@ -746,18 +735,22 @@ static int command_dsleep(int argc, char **argv)
 		}
 	}
 
-	ccprintf("Sleep mask: %08x\n", sleep_mask);
+	ccprintf("Sleep mask: %08x\n", (int)sleep_mask);
 	ccprintf("Console in use timeout:   %d sec\n",
-			console_in_use_timeout_sec);
+		 console_in_use_timeout_sec);
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(dsleep, command_dsleep,
-		"[ on | off | <timeout> sec]",
-		"Deep sleep clock settings:\nUse 'on' to force deep "
-		"sleep NOT to enter heavysleep mode.\nUse 'off' to "
-		"allow deepsleep to use heavysleep whenever conditions "
-		"allow.\n"
-		"Give a timeout value for the console in use timeout.\n"
-		"See also 'sleepmask'.");
+DECLARE_CONSOLE_COMMAND(
+	dsleep, command_dsleep, "[ on | off | <timeout> sec]",
+	"Deep sleep clock settings:\nUse 'on' to force deep "
+	"sleep NOT to enter heavy sleep mode.\nUse 'off' to "
+	"allow deep sleep to use heavy sleep whenever conditions "
+	"allow.\n"
+	"Give a timeout value for the console in use timeout.\n"
+	"See also 'sleep mask'.");
 #endif /* CONFIG_LOW_POWER_IDLE */
+
+test_mockable void clock_enable_module(enum module_id module, int enable)
+{
+}
diff --git a/chip/mchp/clock_chip.h b/chip/mchp/clock_chip.h
index 2e7de60358..4b851aa2bd 100644
--- a/chip/mchp/clock_chip.h
+++ b/chip/mchp/clock_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,7 +11,6 @@
 #include <stdint.h>
 
 void htimer_init(void);
-void system_set_htimer_alarm(uint32_t seconds,
-		uint32_t microseconds);
+void system_set_htimer_alarm(uint32_t seconds, uint32_t microseconds);
 
 #endif /* __CROS_EC_I2C_CLOCK_H */
diff --git a/chip/mchp/config_chip.h b/chip/mchp/config_chip.h
index 747a10a8b8..fbd1a3565b 100644
--- a/chip/mchp/config_chip.h
+++ b/chip/mchp/config_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,15 +10,21 @@
 #include "core/cortex-m/config_core.h"
 
 /* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT	157
+#ifdef CHIP_FAMILY_MEC152X
+#define CONFIG_IRQ_COUNT 174
+#elif defined(CHIP_FAMILY_MEC170X)
+#define CONFIG_IRQ_COUNT 157
+#elif defined(CHIP_FAMILY_MEC172X)
+#define CONFIG_IRQ_COUNT 181
+#endif
 
 /* Use a bigger console output buffer */
 #undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE	1024
+#define CONFIG_UART_TX_BUF_SIZE 1024
 
 /* Interval between HOOK_TICK notifications */
-#define HOOK_TICK_INTERVAL_MS	250
-#define HOOK_TICK_INTERVAL	(HOOK_TICK_INTERVAL_MS * MSEC)
+#define HOOK_TICK_INTERVAL_MS 250
+#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC)
 
 /*
  * Enable chip_pre_init called from main
@@ -28,93 +34,132 @@
 #define CONFIG_CHIP_PRE_INIT
 
 /*
- * MCHP EC's have I2C master/slave
- * controllers and multiple I2C ports. Any
- * port may be mapped to any controller.
- * Enable multi-port controller feature.
- * Board level configuration determines
- * how many controllers/ports are used and
- * the mapping of port(s) to controller(s).
- * NOTE: Some MCHP reduced pin packages
- * may not implement all 11 I2C ports.
+ * MCHP EC's have I2C controllers and multiple I2C ports. Any port may be
+ * mapped to any controller at run time. Enable multi-port controller feature.
+ * Board level configuration determines how many controllers/ports are used
+ * and the mapping of port(s) to controller(s). NOTE: Some MCHP packages
+ * may not implement all I2C ports.
  */
 #define CONFIG_I2C_MULTI_PORT_CONTROLLER
 
 /*
- * MCHP I2C controller is master-slave capable and requires
- * a slave address be programmed even if used as master only.
- * Each I2C controller can respond to two slave address.
- * Define fake slave addresses that aren't used on the I2C port(s)
- * connected to each controller.
+ * MCHP I2C controllers also act as I2C peripherals listening for their
+ * peripheral address. Each controller has two programmable peripheral
+ * addresses. Define fake peripheral addresses that aren't used by
+ * peripherals on the board.
  */
-#define CONFIG_MCHP_I2C0_SLAVE_ADDRS	0xE3E1
-#define CONFIG_MCHP_I2C1_SLAVE_ADDRS	0xE3E1
-#define CONFIG_MCHP_I2C2_SLAVE_ADDRS	0xE3E1
-#define CONFIG_MCHP_I2C3_SLAVE_ADDRS	0xE3E1
-
+#define CONFIG_MCHP_I2C0_SLAVE_ADDRS 0xE3E1
+#define CONFIG_MCHP_I2C1_SLAVE_ADDRS 0xE3E1
+#define CONFIG_MCHP_I2C2_SLAVE_ADDRS 0xE3E1
+#define CONFIG_MCHP_I2C3_SLAVE_ADDRS 0xE3E1
+#define CONFIG_MCHP_I2C4_SLAVE_ADDRS 0xE3E1
+#define CONFIG_MCHP_I2C5_SLAVE_ADDRS 0xE3E1
+#define CONFIG_MCHP_I2C6_SLAVE_ADDRS 0xE3E1
+#define CONFIG_MCHP_I2C7_SLAVE_ADDRS 0xE3E1
 
 /************************************************************************/
 /* Memory mapping */
 
 /*
- * MEC1701H has a total of 256KB SRAM.
+ * MEC170x-H and MEC152x-H have a total of 256KB SRAM.
  *   CODE at 0xE0000 - 0x117FFF, DATA at 0x118000 - 0x11FFFF
- *   MCHP MEC can fetch code from data or data from code.
+ * MEC172x-N has a total of 416KB SRAM: 352KB CODE 64KB DATA
+ *   CODE at 0xC0000 - 0x117FFF, DATA at 0x118000 - 0x127FFF
+ *   Customer data preserved across reset is 1KB at 0x12_7400.
+ *   Set top of SRAM to 0x12_7800.  We lose the top 2KB.
+ * MCHP MEC can fetch code from data or data from code.
  */
 
 /************************************************************************/
 /* Define our RAM layout. */
 
-#define CONFIG_MEC_SRAM_BASE_START	0x000E0000
-#define CONFIG_MEC_SRAM_BASE_END	0x00120000
-#define CONFIG_MEC_SRAM_SIZE		(CONFIG_MEC_SRAM_BASE_END - \
-					CONFIG_MEC_SRAM_BASE_START)
+#if defined(CHIP_FAMILY_MEC172X)
+#define CONFIG_MEC_SRAM_BASE_START 0x000C0000
+#define CONFIG_MEC_SRAM_BASE_END (0x00128000 - (2 * 1024))
+#else
+#define CONFIG_MEC_SRAM_BASE_START 0x000E0000
+#define CONFIG_MEC_SRAM_BASE_END 0x00120000
+#endif
 
+#define CONFIG_MEC_SRAM_SIZE \
+	(CONFIG_MEC_SRAM_BASE_END - CONFIG_MEC_SRAM_BASE_START)
 /* 64k Data RAM for RO / RW / loader */
-#define CONFIG_RAM_SIZE			0x00010000
-#define CONFIG_RAM_BASE			(CONFIG_MEC_SRAM_BASE_END - \
-					CONFIG_RAM_SIZE)
+#define CONFIG_RAM_SIZE 0x00010000
+#define CONFIG_RAM_BASE (CONFIG_MEC_SRAM_BASE_END - CONFIG_RAM_SIZE)
 
 /* System stack size */
 /* was 1024, temporarily expanded to 2048 for debug */
-#define CONFIG_STACK_SIZE		2048
+#define CONFIG_STACK_SIZE 2048
 
 /* non-standard task stack sizes */
-/* temporarily expanded for debug */
-#define IDLE_TASK_STACK_SIZE		1024	/* 512 */
-#define LARGER_TASK_STACK_SIZE		1024	/* 640 */
-#define VENTI_TASK_STACK_SIZE		1024	/* 768 */
+#define IDLE_TASK_STACK_SIZE 672
+#define LARGER_TASK_STACK_SIZE 800
+#define VENTI_TASK_STACK_SIZE 928
+#define ULTRA_TASK_STACK_SIZE 1056
+#define TRENTA_TASK_STACK_SIZE 1184
 
-#define CHARGER_TASK_STACK_SIZE		1024	/* 640 */
-#define HOOKS_TASK_STACK_SIZE		1024	/* 640 */
-#define CONSOLE_TASK_STACK_SIZE		1024	/* 640 */
-#define HOST_CMD_TASK_STACK_SIZE	1024	/* 640 */
+#define CHARGER_TASK_STACK_SIZE 1024 /* 640 */
+#define HOOKS_TASK_STACK_SIZE 1024 /* 640 */
+#define CONSOLE_TASK_STACK_SIZE 1024 /* 640 */
+#define HOST_CMD_TASK_STACK_SIZE 1024 /* 640 */
 
 /*
  * TODO: Large stack consumption
  * https://code.google.com/p/chrome-os-partner/issues/detail?id=49245
  */
-/* dsw original = 800, if stack exceptions expand to 1024 for debug */
-#define PD_TASK_STACK_SIZE		2048
+/* original = 800, if stack exceptions expand to 1024 for debug */
+#define PD_TASK_STACK_SIZE 2048
 
 /* Default task stack size */
-#define TASK_STACK_SIZE			1024	/* 512 */
+#define TASK_STACK_SIZE 672
 
 /************************************************************************/
 /* Define our flash layout. */
 
+/*
+ * MEC1521H loads firmware using QMSPI controller
+ * CONFIG_SPI_FLASH_PORT is the index into
+ * spi_devices[] in board.c
+ */
+#define CONFIG_SPI_FLASH_PORT 0
+#define CONFIG_SPI_FLASH
+
+/*
+ * MEC1727 chip has integrated SPI flash with 512KB size
+ */
+#if (defined(CHIP_VARIANT_MEC1727SZ) || defined(CHIP_VARIANT_MEC1727LJ))
+/* Total size of writable flash */
+#define CONFIG_FLASH_SIZE_BYTES 524288
+#endif
+
 /* Protect bank size 4K bytes */
-#define CONFIG_FLASH_BANK_SIZE		0x00001000
+#define CONFIG_FLASH_BANK_SIZE 0x00001000
 /* Sector erase size 4K bytes */
-#define CONFIG_FLASH_ERASE_SIZE		0x00001000
+#define CONFIG_FLASH_ERASE_SIZE 0x00001000
 /* Minimum write size */
-#define CONFIG_FLASH_WRITE_SIZE		0x00000004
+#define CONFIG_FLASH_WRITE_SIZE 0x00000004
 
 /* One page size for write */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE	256
+#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256
 
 /* Program memory base address */
-#define CONFIG_PROGRAM_MEMORY_BASE	0x000E0000
+#if defined(CHIP_FAMILY_MEC172X)
+#define CONFIG_PROGRAM_MEMORY_BASE 0x000C0000
+#else
+#define CONFIG_PROGRAM_MEMORY_BASE 0x000E0000
+#endif
+
+/*
+ * Optimize SPI flash read timing, MEC172x QMSPI controller controls CS#
+ * by hardware, it will add several system clock cycles delay between CS
+ * deassertion to CS assertion at the start of the next transaction, this
+ * guarantees SPI back to back transactions, so 1ms delay can be removed
+ * to optimze timing. MEC172x chip supports this hardware feature.
+ */
+#if defined(CHIP_FAMILY_MEC172X)
+#undef CONFIG_SPI_FLASH_READ_WAIT_MS
+#define CONFIG_SPI_FLASH_READ_WAIT_MS 0
+#endif
 
 #include "config_flash_layout.h"
 
@@ -122,7 +167,7 @@
 /* Customize the build */
 /* Optional features present on this chip */
 #define CONFIG_ADC
-#define CONFIG_DMA
+#define CONFIG_DMA_CROS
 #define CONFIG_HOSTCMD_X86
 #define CONFIG_SPI
 #define CONFIG_SWITCH
@@ -159,7 +204,9 @@
  * Use DMA when transmitting commands & data
  * with GPSPI controllers.
  */
+#if defined(CHIP_FAMILY_MEC170X) || defined(CHIP_FAMILY_MEC172X)
 #define CONFIG_MCHP_GPSPI_TX_DMA
+#endif
 
 /*
  * Use DMA when transmitting command & data of length
@@ -184,14 +231,13 @@
  * GPIO(PCH_SLP_S0_L, PIN(0x89), GPIO_INPUT | GPIO_PULL_DOWN)
  */
 #define GPIO_BANK(index) ((index) >> 5)
-#define GPIO_BANK_MASK(index) (1ul << ((index) & 0x1F))
+#define GPIO_BANK_MASK(index) (1ul << ((index)&0x1F))
 
 #define GPIO_PIN(index) GPIO_BANK(index), GPIO_BANK_MASK(index)
 #define GPIO_PIN_MASK(p, m) .port = (p), .mask = (m)
 
 #ifndef __ASSEMBLER__
 
-
 #endif /* #ifndef __ASSEMBLER__ */
 
-#endif  /* __CROS_EC_CONFIG_CHIP_H */
+#endif /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/chip/mchp/config_flash_layout.h b/chip/mchp/config_flash_layout.h
index b25ab02b06..f495f65465 100644
--- a/chip/mchp/config_flash_layout.h
+++ b/chip/mchp/config_flash_layout.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,14 +14,14 @@
  * - Loader + (RO | RW) loaded into program memory.
  */
 
-/* Non-memmapped, external SPI */
+/* Non-memmory mapped, external SPI */
 #define CONFIG_EXTERNAL_STORAGE
-#undef  CONFIG_MAPPED_STORAGE
-#undef  CONFIG_FLASH_PSTATE
+#undef CONFIG_MAPPED_STORAGE
+#undef CONFIG_FLASH_PSTATE
 #define CONFIG_SPI_FLASH
 
 /*
- * MEC17xx BootROM uses two 4-byte TAG's at SPI offset 0x0 and 0x04.
+ * MEC170x/MEC152x BootROM uses two 4-byte TAG's at SPI offset 0x0 and 0x04.
  * One valid TAG must be present.
  * TAG's point to a Header which must be located on a 256 byte
  * boundary anywhere in the flash (24-bit addressing).
@@ -33,32 +33,30 @@
  * EC_RO and EC_RW padded sizes from the build are 188KB each.
  * Storage size is 1/2 flash size.
  */
-#define CONFIG_EC_PROTECTED_STORAGE_OFF	0
+#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
 /* Lower 256KB of flash is protected region */
 #define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x40000
 /* Writable storage for EC_RW starts at 256KB */
 #define CONFIG_EC_WRITABLE_STORAGE_OFF 0x40000
 /* Writeable storage is 256KB */
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE  0x40000
-
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x40000
 
 /* Loader resides at the beginning of program memory */
-#define CONFIG_LOADER_MEM_OFF		0
-#define CONFIG_LOADER_SIZE		0x1000
+#define CONFIG_LOADER_MEM_OFF 0
+#define CONFIG_LOADER_SIZE 0x1000
 
 /* Write protect Loader and RO Image */
-#define CONFIG_WP_STORAGE_OFF		CONFIG_EC_PROTECTED_STORAGE_OFF
+#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
 /*
  * Write protect LFW + EC_RO
  */
-#define CONFIG_WP_STORAGE_SIZE		CONFIG_EC_PROTECTED_STORAGE_SIZE
+#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
 
 /*
  * RO / RW images follow the loader in program memory. Either RO or RW
  * image will be loaded -- both cannot be loaded at the same time.
  */
-#define CONFIG_RO_MEM_OFF		(CONFIG_LOADER_MEM_OFF + \
-					CONFIG_LOADER_SIZE)
+#define CONFIG_RO_MEM_OFF (CONFIG_LOADER_MEM_OFF + CONFIG_LOADER_SIZE)
 /*
  * Total SRAM and the amount allocated for data are specified
  * by CONFIG_MEC_SRAM_SIZE and CONFIG_RAM_SIZE in config_chip.h
@@ -68,50 +66,86 @@
  * defined by CONFIG_FLASH_ERASE_SIZE in chip/config_chip.h
  * and must be located on a erase block boundary. !!!
  */
-#define CONFIG_RO_SIZE			(CONFIG_MEC_SRAM_SIZE - \
-					CONFIG_RAM_SIZE - CONFIG_LOADER_SIZE)
-#define CONFIG_RW_MEM_OFF		CONFIG_RO_MEM_OFF
+#if (CONFIG_MEC_SRAM_SIZE > CONFIG_EC_PROTECTED_STORAGE_SIZE)
+#define CONFIG_RO_SIZE \
+	(CONFIG_EC_PROTECTED_STORAGE_SIZE - CONFIG_LOADER_SIZE - 0x2000)
+#else
+#define CONFIG_RO_SIZE \
+	(CONFIG_MEC_SRAM_SIZE - CONFIG_RAM_SIZE - CONFIG_LOADER_SIZE)
+#endif
+
+#define CONFIG_RW_MEM_OFF CONFIG_RO_MEM_OFF
 /*
- * NOTE: CONFIG_RW_SIZE is passed to chip/mchp/util/pack_ec.py
+ * NOTE: CONFIG_RW_SIZE is passed to the SPI image generation script by
+ * chip build.mk
+ * LFW requires CONFIG_RW_SIZE is equal to CONFIG_RO_SIZE !!!
  */
-#define CONFIG_RW_SIZE			CONFIG_RO_SIZE
+#define CONFIG_RW_SIZE CONFIG_RO_SIZE
 
 /*
  * WP region consists of first half of SPI containing TAGs at beginning
  * of SPI flash and header + binary(LFW+EC_RO) an offset aligned on
  * a 256 byte boundary.
  * NOTE: Changing CONFIG_BOOT_HEADER_STORAGE_OFF requires changing
- * parameter --payload_offset of pack_ec.py in build.mk!
+ * parameter --payload_offset parameter in build.mk passed to the
+ * python image builder.
  * Two 4-byte TAG's exist at offset 0 and 4 in the SPI flash device.
  * We only use first TAG pointing to LFW + EC_RO.
- * Header size is 128 bytes. Firmware binary is located immediately
- * after the header.
+ * MEC170x Header size is 128 bytes.
+ * MEC152x Header size is 320 bytes.
+ * Firmware binary is located immediately after the header.
  * Second half of SPI flash contains:
- * Header(128 bytes) + EC_RW
- * EC flash erase/write commands check alginment base on
+ * Header(128/320 bytes) + EC_RW
+ * EC flash erase/write commands check alignment base on
  * CONFIG_FLASH_ERASE_SIZE defined in config_chip.h
  * NOTE: EC_RO and EC_RW must start at CONFIG_FLASH_ERASE_SIZE or
  * greater aligned boundaries.
  */
-#define CONFIG_BOOT_HEADER_STORAGE_OFF		0x1000
-#define CONFIG_RW_BOOT_HEADER_STORAGE_OFF	0
-#define CONFIG_BOOT_HEADER_STORAGE_SIZE		0x80
-#define CONFIG_RW_BOOT_HEADER_STORAGE_SIZE	0
+
+#define CONFIG_RW_BOOT_HEADER_STORAGE_OFF 0
+#if defined(CHIP_FAMILY_MEC172X)
+/*
+ * Changed to 0x140 original 0xc0 which is incorrect
+ * Python SPI image generator is locating header at offset 0x100 which is
+ * in first 4KB. We moved header into first 4KB to free up the 0x140 (320)
+ * bytes of code image space. Layout is:
+ * SPI Offset:
+ * 0x0 - 0x3 = Boot-ROM TAG
+ * 0x4 - 0xff = 0xFF padding
+ * 0x100 - 0x23F = Boot-ROM Header must be on >= 0x100 boundary
+ *                 This header points to LFW at 0x1000
+ * 0x240 - 0xfff = 0xFF padding
+ * 0x1000 - 0x1fff = 4KB Little Firmware loaded by Boot-ROM into first 4KB
+ *                   of CODE SRAM.
+ * 0x2000 - 0x3ffff = EC_RO padded with 0xFF
+ * 0x40000 - 0x7ffff = EC_RW padded with 0xFF
+ * To EC the "header" is one 4KB chunk at offset 0
+ */
+#define CONFIG_BOOT_HEADER_STORAGE_OFF 0
+#define CONFIG_BOOT_HEADER_STORAGE_SIZE 0x1000
+#elif defined(CHIP_FAMILY_MEC152X)
+#define CONFIG_BOOT_HEADER_STORAGE_OFF 0x1000
+#define CONFIG_BOOT_HEADER_STORAGE_SIZE 0x140
+#elif defined(CHIP_FAMILY_MEC170X)
+#define CONFIG_BOOT_HEADER_STORAGE_OFF 0x1000
+#define CONFIG_BOOT_HEADER_STORAGE_SIZE 0x80
+#else
+#error "FORCED BUILD ERROR: CHIP_FAMILY_xxxx not set or invalid"
+#endif
+#define CONFIG_RW_BOOT_HEADER_STORAGE_SIZE 0
 
 /* Loader / lfw image immediately follows the boot header on SPI */
-#define CONFIG_LOADER_STORAGE_OFF	(CONFIG_BOOT_HEADER_STORAGE_OFF + \
-					CONFIG_BOOT_HEADER_STORAGE_SIZE)
+#define CONFIG_LOADER_STORAGE_OFF \
+	(CONFIG_BOOT_HEADER_STORAGE_OFF + CONFIG_BOOT_HEADER_STORAGE_SIZE)
 
 /* RO image immediately follows the loader image */
-#define CONFIG_RO_STORAGE_OFF		(CONFIG_LOADER_STORAGE_OFF + \
-					CONFIG_LOADER_SIZE)
+#define CONFIG_RO_STORAGE_OFF (CONFIG_LOADER_STORAGE_OFF + CONFIG_LOADER_SIZE)
 
 /*
  * RW image starts at offset 0 of second half of SPI.
  * RW Header not needed.
  */
-#define CONFIG_RW_STORAGE_OFF		(CONFIG_RW_BOOT_HEADER_STORAGE_OFF + \
-					CONFIG_RW_BOOT_HEADER_STORAGE_SIZE)
-
+#define CONFIG_RW_STORAGE_OFF \
+	(CONFIG_RW_BOOT_HEADER_STORAGE_OFF + CONFIG_RW_BOOT_HEADER_STORAGE_SIZE)
 
 #endif /* __CROS_EC_CONFIG_FLASH_LAYOUT_H */
diff --git a/chip/mchp/dma.c b/chip/mchp/dma.c
index 982dfa8122..180735dbb5 100644
--- a/chip/mchp/dma.c
+++ b/chip/mchp/dma.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,13 +9,13 @@
 #include "hooks.h"
 #include "registers.h"
 #include "task.h"
+#include "tfdp_chip.h"
 #include "timer.h"
 #include "util.h"
-#include "tfdp_chip.h"
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_DMA, outstr)
-#define CPRINTS(format, args...) cprints(CC_DMA, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_DMA, format, ##args)
 
 dma_chan_t *dma_get_channel(enum dma_channel channel)
 {
@@ -23,7 +23,7 @@ dma_chan_t *dma_get_channel(enum dma_channel channel)
 
 	if (channel < MCHP_DMAC_COUNT) {
 		pd = (dma_chan_t *)(MCHP_DMA_BASE + MCHP_DMA_CH_OFS +
-				(channel << MCHP_DMA_CH_OFS_BITPOS));
+				    (channel << MCHP_DMA_CH_OFS_BITPOS));
 	}
 
 	return pd;
@@ -35,7 +35,7 @@ void dma_disable(enum dma_channel channel)
 		if (MCHP_DMA_CH_CTRL(channel) & MCHP_DMA_RUN)
 			MCHP_DMA_CH_CTRL(channel) &= ~(MCHP_DMA_RUN);
 
-		if (MCHP_DMA_CH_ACT(channel)	& MCHP_DMA_ACT_EN)
+		if (MCHP_DMA_CH_ACT(channel) & MCHP_DMA_ACT_EN)
 			MCHP_DMA_CH_ACT(channel) = 0;
 	}
 }
@@ -74,10 +74,9 @@ void dma_disable_all(void)
  * is the number of bytes to transfer memory start - memory end = count.
  */
 static void prepare_channel(enum dma_channel ch, unsigned int count,
-		void *periph, void *memory, unsigned int flags)
+			    void *periph, void *memory, unsigned int flags)
 {
 	if (ch < MCHP_DMAC_COUNT) {
-
 		MCHP_DMA_CH_CTRL(ch) = 0;
 		MCHP_DMA_CH_MEM_START(ch) = (uint32_t)memory;
 		MCHP_DMA_CH_MEM_END(ch) = (uint32_t)memory + count;
@@ -107,7 +106,7 @@ void dma_go_chan(enum dma_channel ch)
 		MCHP_DMA_CH_CTRL(ch) |= MCHP_DMA_RUN;
 }
 
-void dma_prepare_tx(const struct dma_option *option, unsigned count,
+void dma_prepare_tx(const struct dma_option *option, unsigned int count,
 		    const void *memory)
 {
 	if (option != NULL)
@@ -115,16 +114,14 @@ void dma_prepare_tx(const struct dma_option *option, unsigned count,
 		 * Cast away const for memory pointer; this is ok because
 		 * we know we're preparing the channel for transmit.
 		 */
-		prepare_channel(option->channel, count, option->periph,
-			(void *)memory,
-			MCHP_DMA_INC_MEM |
-			MCHP_DMA_TO_DEV |
-			MCHP_DMA_DEV(option->channel) |
-			option->flags);
+		prepare_channel(
+			option->channel, count, option->periph, (void *)memory,
+			MCHP_DMA_INC_MEM | MCHP_DMA_TO_DEV |
+				MCHP_DMA_DEV(option->channel) | option->flags);
 }
 
 void dma_xfr_prepare_tx(const struct dma_option *option, uint32_t count,
-		const void *memory, uint32_t dma_xfr_units)
+			const void *memory, uint32_t dma_xfr_units)
 {
 	uint32_t nflags;
 
@@ -136,23 +133,20 @@ void dma_xfr_prepare_tx(const struct dma_option *option, uint32_t count,
 		 * we know we're preparing the channel for transmit.
 		 */
 		prepare_channel(option->channel, count, option->periph,
-			(void *)memory,
-			MCHP_DMA_INC_MEM |
-			MCHP_DMA_TO_DEV |
-			MCHP_DMA_DEV(option->channel) |
-			nflags);
+				(void *)memory,
+				MCHP_DMA_INC_MEM | MCHP_DMA_TO_DEV |
+					MCHP_DMA_DEV(option->channel) | nflags);
 	}
 }
 
-void dma_start_rx(const struct dma_option *option, unsigned count,
+void dma_start_rx(const struct dma_option *option, unsigned int count,
 		  void *memory)
 {
 	if (option != NULL) {
-		prepare_channel(option->channel, count, option->periph,
-				memory,
+		prepare_channel(option->channel, count, option->periph, memory,
 				MCHP_DMA_INC_MEM |
-				MCHP_DMA_DEV(option->channel) |
-				option->flags);
+					MCHP_DMA_DEV(option->channel) |
+					option->flags);
 		dma_go_chan(option->channel);
 	}
 }
@@ -161,26 +155,21 @@ void dma_start_rx(const struct dma_option *option, unsigned count,
  * Configure and start DMA channel for read from device and write to
  * memory. Allow caller to override DMA transfer unit length.
  */
-void dma_xfr_start_rx(const struct dma_option *option,
-		uint32_t dma_xfr_ulen,
-		uint32_t count, void *memory)
+void dma_xfr_start_rx(const struct dma_option *option, uint32_t dma_xfr_ulen,
+		      uint32_t count, void *memory)
 {
 	uint32_t ch, ctrl;
 
 	if (option != NULL) {
 		ch = option->channel;
 		if (ch < MCHP_DMAC_COUNT) {
-
 			MCHP_DMA_CH_CTRL(ch) = 0;
 			MCHP_DMA_CH_MEM_START(ch) = (uint32_t)memory;
-			MCHP_DMA_CH_MEM_END(ch) = (uint32_t)memory +
-					count;
+			MCHP_DMA_CH_MEM_END(ch) = (uint32_t)memory + count;
 
-			MCHP_DMA_CH_DEV_ADDR(ch) =
-					(uint32_t)option->periph;
+			MCHP_DMA_CH_DEV_ADDR(ch) = (uint32_t)option->periph;
 
-			ctrl = option->flags &
-					~(MCHP_DMA_XFER_SIZE_MASK);
+			ctrl = option->flags & ~(MCHP_DMA_XFER_SIZE_MASK);
 			ctrl |= MCHP_DMA_INC_MEM;
 			ctrl |= MCHP_DMA_XFER_SIZE(dma_xfr_ulen);
 			ctrl |= MCHP_DMA_DEV(option->channel);
@@ -228,8 +217,8 @@ int dma_bytes_done_chan(enum dma_channel ch, uint32_t orig_count)
 	if (ch < MCHP_DMAC_COUNT)
 		if (MCHP_DMA_CH_CTRL(ch) & MCHP_DMA_RUN)
 			cnt = (uint32_t)orig_count -
-					(MCHP_DMA_CH_MEM_END(ch) -
-					 MCHP_DMA_CH_MEM_START(ch));
+			      (MCHP_DMA_CH_MEM_END(ch) -
+			       MCHP_DMA_CH_MEM_START(ch));
 
 	return (int)cnt;
 }
@@ -259,9 +248,7 @@ int dma_wait(enum dma_channel channel)
 
 		deadline.val = get_time().val + DMA_TRANSFER_TIMEOUT_US;
 
-		while (!(MCHP_DMA_CH_ISTS(channel) &
-			 MCHP_DMA_STS_DONE)) {
-
+		while (!(MCHP_DMA_CH_ISTS(channel) & MCHP_DMA_STS_DONE)) {
 			if (deadline.val <= get_time().val)
 				return EC_ERROR_TIMEOUT;
 
@@ -282,8 +269,8 @@ void dma_clear_isr(enum dma_channel channel)
 		MCHP_DMA_CH_ISTS(channel) = 0x0f;
 }
 
-void dma_cfg_buffers(enum dma_channel ch, const void *membuf,
-			uint32_t nb, const void *pdev)
+void dma_cfg_buffers(enum dma_channel ch, const void *membuf, uint32_t nb,
+		     const void *pdev)
 {
 	if (ch < MCHP_DMAC_COUNT) {
 		MCHP_DMA_CH_MEM_START(ch) = (uint32_t)membuf;
@@ -301,8 +288,8 @@ void dma_cfg_buffers(enum dma_channel ch, const void *membuf,
  *   b[2] = 1 increment device address
  *   b[3] = disable HW flow control
  */
-void dma_cfg_xfr(enum dma_channel ch, uint8_t unit_len,
-			uint8_t dev_id, uint8_t flags)
+void dma_cfg_xfr(enum dma_channel ch, uint8_t unit_len, uint8_t dev_id,
+		 uint8_t flags)
 {
 	uint32_t ctrl;
 
@@ -378,7 +365,7 @@ int dma_crc32_start(const uint8_t *mstart, const uint32_t nbytes, int ien)
 	MCHP_DMA_CH_IEN(0) = 0;
 	MCHP_DMA_CH_ISTS(0) = 0xff;
 	MCHP_DMA_CH0_CRC32_EN = 1;
-	MCHP_DMA_CH0_CRC32_DATA	= 0xfffffffful;
+	MCHP_DMA_CH0_CRC32_DATA = 0xfffffffful;
 	/* program device address to point to read-only register */
 	MCHP_DMA_CH_DEV_ADDR(0) = (uint32_t)(MCHP_DMA_CH_BASE + 0x1c);
 	MCHP_DMA_CH_MEM_START(0) = (uint32_t)mstart;
@@ -387,7 +374,7 @@ int dma_crc32_start(const uint8_t *mstart, const uint32_t nbytes, int ien)
 		MCHP_DMA_CH_IEN(0) = 0x07;
 	MCHP_DMA_CH_ACT(0) = 1;
 	MCHP_DMA_CH_CTRL(0) = MCHP_DMA_TO_DEV + MCHP_DMA_INC_MEM +
-		MCHP_DMA_DIS_HW_FLOW + MCHP_DMA_XFER_SIZE(4);
+			      MCHP_DMA_DIS_HW_FLOW + MCHP_DMA_XFER_SIZE(4);
 	MCHP_DMA_CH_CTRL(0) |= MCHP_DMA_SW_GO;
 	return EC_SUCCESS;
 }
diff --git a/chip/mchp/dma_chip.h b/chip/mchp/dma_chip.h
index 4784b2c922..bfdb8ab9be 100644
--- a/chip/mchp/dma_chip.h
+++ b/chip/mchp/dma_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -13,9 +13,8 @@
 #ifndef _DMA_CHIP_H
 #define _DMA_CHIP_H
 
-#include <stdint.h>
 #include <stddef.h>
-
+#include <stdint.h>
 
 #ifdef __cplusplus
 extern "C" {
@@ -23,17 +22,16 @@ extern "C" {
 
 /* Place any C interfaces here */
 
-void dma_xfr_start_rx(const struct dma_option *option,
-		uint32_t dma_xfr_ulen,
-		uint32_t count, void *memory);
+void dma_xfr_start_rx(const struct dma_option *option, uint32_t dma_xfr_ulen,
+		      uint32_t count, void *memory);
 
 void dma_xfr_prepare_tx(const struct dma_option *option, uint32_t count,
-		const void *memory, uint32_t dma_xfr_units);
+			const void *memory, uint32_t dma_xfr_units);
 
 void dma_clr_chan(enum dma_channel ch);
 
-void dma_cfg_buffers(enum dma_channel ch, const void *membuf,
-			uint32_t nb, const void *pdev);
+void dma_cfg_buffers(enum dma_channel ch, const void *membuf, uint32_t nb,
+		     const void *pdev);
 
 /*
  * ch = zero based DMA channel number
@@ -44,13 +42,13 @@ void dma_cfg_buffers(enum dma_channel ch, const void *membuf,
  *   b[2] = 1 increment device address
  *   b[3] = disable HW flow control
  */
-#define DMA_FLAG_D2M		0
-#define DMA_FLAG_M2D		1
-#define DMA_FLAG_INCR_MEM	2
-#define DMA_FLAG_INCR_DEV	4
-#define DMA_FLAG_SW_FLOW	8
-void dma_cfg_xfr(enum dma_channel ch, uint8_t unit_len,
-			uint8_t dev_id, uint8_t flags);
+#define DMA_FLAG_D2M 0
+#define DMA_FLAG_M2D 1
+#define DMA_FLAG_INCR_MEM 2
+#define DMA_FLAG_INCR_DEV 4
+#define DMA_FLAG_SW_FLOW 8
+void dma_cfg_xfr(enum dma_channel ch, uint8_t unit_len, uint8_t dev_id,
+		 uint8_t flags);
 
 void dma_run(enum dma_channel ch);
 
@@ -65,4 +63,3 @@ int dma_crc32_start(const uint8_t *mstart, const uint32_t nbytes, int ien);
 #endif /* #ifndef _DMA_CHIP_H */
 /**   @}
  */
-
diff --git a/chip/mchp/espi.c b/chip/mchp/espi.c
index 1cc06d8f90..552739abc7 100644
--- a/chip/mchp/espi.c
+++ b/chip/mchp/espi.c
@@ -1,33 +1,31 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* ESPI module for Chrome EC */
 
-#include "common.h"
 #include "acpi.h"
+#include "chipset.h"
+#include "common.h"
 #include "console.h"
+#include "espi.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "host_command.h"
 #include "keyboard_protocol.h"
-#include "port80.h"
-#include "util.h"
-#include "chipset.h"
-
-#include "registers.h"
-#include "espi.h"
 #include "lpc.h"
 #include "lpc_chip.h"
+#include "port80.h"
+#include "power.h"
+#include "registers.h"
 #include "system.h"
+#include "system_boot_time.h"
 #include "task.h"
-#include "console.h"
+#include "tfdp_chip.h"
+#include "timer.h"
 #include "uart.h"
 #include "util.h"
-#include "power.h"
-#include "timer.h"
-#include "tfdp_chip.h"
 
 /* Console output macros */
 #ifdef CONFIG_MCHP_ESPI_DEBUG
@@ -36,18 +34,36 @@
 #define CPRINTS(...)
 #else
 #define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args)
 #endif
 #else
 #define CPUTS(...)
 #define CPRINTS(...)
 #endif
 
+/* Default config to use maximum frequency */
+#ifndef CONFIG_HOST_INTERFACE_ESPI_EC_MAX_FREQ
+#if defined(CHIP_FAMILY_MEC172X)
+#define CONFIG_HOST_INTERFACE_ESPI_EC_MAX_FREQ MCHP_ESPI_CAP1_MAX_FREQ_66M
+#else
+#define CONFIG_HOST_INTERFACE_ESPI_EC_MAX_FREQ MCHP_ESPI_CAP1_MAX_FREQ_50M
+#endif
+#endif
+
+/* Default config to support all modes */
+#ifndef CONFIG_HOST_INTERFACE_ESPI_EC_MODE
+#define CONFIG_HOST_INTERFACE_ESPI_EC_MODE MCHP_ESPI_CAP1_ALL_MODE
+#endif
+
+/* Default config to support all channels */
+#ifndef CONFIG_HOST_INTERFACE_ESPI_EC_CHAN_BITMAP
+#define CONFIG_HOST_INTERFACE_ESPI_EC_CHAN_BITMAP MCHP_ESPI_CAP0_ALL_CHAN_SUPP
+#endif
 /*
  * eSPI slave to master virtual wire pulse timeout.
  */
-#define ESPI_S2M_VW_PULSE_LOOP_CNT		50
-#define ESPI_S2M_VW_PULSE_LOOP_DLY_US		10
+#define ESPI_S2M_VW_PULSE_LOOP_CNT 50
+#define ESPI_S2M_VW_PULSE_LOOP_DLY_US 10
 
 /*
  * eSPI master enable virtual wire channel timeout.
@@ -86,16 +102,15 @@ static uint32_t espi_channels_ready;
  *
  */
 struct vw_info_t {
-	uint16_t name;		/* signal name */
-	uint8_t  host_idx;	/* Host VWire index of signal */
-	uint8_t  reset_val;	/* reset value of VWire */
-	uint8_t  flags;		/* b[0]=0(MSVW), =1(SMVW) */
-	uint8_t  reg_idx;	/* MSVW or SMVW index */
-	uint8_t  src_num;	/* SRC number */
-	uint8_t  rsvd;
+	uint16_t name; /* signal name */
+	uint8_t host_idx; /* Host VWire index of signal */
+	uint8_t reset_val; /* reset value of VWire */
+	uint8_t flags; /* b[0]=0(MSVW), =1(SMVW) */
+	uint8_t reg_idx; /* MSVW or SMVW index */
+	uint8_t src_num; /* SRC number */
+	uint8_t rsvd;
 };
 
-
 /* VW signals used in eSPI */
 /*
  * MEC1701H VWire mapping based on eSPI Spec 1.0,
@@ -137,7 +152,7 @@ struct vw_info_t {
  *	SRC0 = SLAVE_BOOT_LOAD_DONE   !!! NOTE: Google combines SRC0 & SRC3
  *	SRC1 = VW_ERROR_FATAL
  *	SRC2 = VW_ERROR_NON_FATAL
- *	SRC3 = SLAVE_BOOT_LOAD_STATUS !!! into VW_SLAVE_BTLD_STATUS_DONE
+ *	SRC3 = SLAVE_BOOT_LOAD_STATUS !!! into VW_PERIPHERAL_BTLD_STATUS_DONE
  * SMVW02 index=06h PORValue=00010101_00007306 STOM=0111 reset=PLTRST
  *	SRC0 = VW_SCI_L
  *	SRC1 = VW_SMI_L
@@ -175,41 +190,40 @@ static const struct vw_info_t vw_info_tbl[] = {
 	 *				index value flags index num   rsvd
 	 */
 	/* MSVW00 Host index 02h (In) */
-	{VW_SLP_S3_L,			0x02, 0x00, 0x00, 0x00, 0x00, 0x00},
-	{VW_SLP_S4_L,			0x02, 0x00, 0x00, 0x00, 0x01, 0x00},
-	{VW_SLP_S5_L,			0x02, 0x00, 0x10, 0x00, 0x02, 0x00},
+	{ VW_SLP_S3_L, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00 },
+	{ VW_SLP_S4_L, 0x02, 0x00, 0x00, 0x00, 0x01, 0x00 },
+	{ VW_SLP_S5_L, 0x02, 0x00, 0x10, 0x00, 0x02, 0x00 },
 	/* MSVW01 Host index 03h (In) */
-	{VW_SUS_STAT_L,			0x03, 0x00, 0x10, 0x01, 0x00, 0x00},
-	{VW_PLTRST_L,			0x03, 0x00, 0x10, 0x01, 0x01, 0x00},
-	{VW_OOB_RST_WARN,		0x03, 0x00, 0x10, 0x01, 0x02, 0x00},
+	{ VW_SUS_STAT_L, 0x03, 0x00, 0x10, 0x01, 0x00, 0x00 },
+	{ VW_PLTRST_L, 0x03, 0x00, 0x10, 0x01, 0x01, 0x00 },
+	{ VW_OOB_RST_WARN, 0x03, 0x00, 0x10, 0x01, 0x02, 0x00 },
 	/* SMVW00 Host Index 04h (Out) */
-	{VW_OOB_RST_ACK,		0x04, 0x00, 0x01, 0x00, 0x00, 0x00},
-	{VW_WAKE_L,			0x04, 0x01, 0x01, 0x00, 0x02, 0x00},
-	{VW_PME_L,			0x04, 0x01, 0x01, 0x00, 0x03, 0x00},
+	{ VW_OOB_RST_ACK, 0x04, 0x00, 0x01, 0x00, 0x00, 0x00 },
+	{ VW_WAKE_L, 0x04, 0x01, 0x01, 0x00, 0x02, 0x00 },
+	{ VW_PME_L, 0x04, 0x01, 0x01, 0x00, 0x03, 0x00 },
 	/* SMVW01 Host index 05h (Out) */
-	{VW_ERROR_FATAL,		0x05, 0x00, 0x01, 0x01, 0x01, 0x00},
-	{VW_ERROR_NON_FATAL,		0x05, 0x00, 0x01, 0x01, 0x02, 0x00},
-	{VW_SLAVE_BTLD_STATUS_DONE,	0x05, 0x00, 0x01, 0x01, 0x30, 0x00},
+	{ VW_ERROR_FATAL, 0x05, 0x00, 0x01, 0x01, 0x01, 0x00 },
+	{ VW_ERROR_NON_FATAL, 0x05, 0x00, 0x01, 0x01, 0x02, 0x00 },
+	{ VW_PERIPHERAL_BTLD_STATUS_DONE, 0x05, 0x00, 0x01, 0x01, 0x30, 0x00 },
 	/* SMVW02 Host index 06h (Out) */
-	{VW_SCI_L,			0x06, 0x01, 0x01, 0x02, 0x00, 0x00},
-	{VW_SMI_L,			0x06, 0x01, 0x01, 0x02, 0x01, 0x00},
-	{VW_RCIN_L,			0x06, 0x01, 0x01, 0x02, 0x02, 0x00},
-	{VW_HOST_RST_ACK,		0x06, 0x00, 0x01, 0x02, 0x03, 0x00},
+	{ VW_SCI_L, 0x06, 0x01, 0x01, 0x02, 0x00, 0x00 },
+	{ VW_SMI_L, 0x06, 0x01, 0x01, 0x02, 0x01, 0x00 },
+	{ VW_RCIN_L, 0x06, 0x01, 0x01, 0x02, 0x02, 0x00 },
+	{ VW_HOST_RST_ACK, 0x06, 0x00, 0x01, 0x02, 0x03, 0x00 },
 	/* MSVW02 Host index 07h (In) */
-	{VW_HOST_RST_WARN,		0x07, 0x00, 0x10, 0x02, 0x00, 0x00},
+	{ VW_HOST_RST_WARN, 0x07, 0x00, 0x10, 0x02, 0x00, 0x00 },
 	/* SMVW03 Host Index 40h (Out) */
-	{VW_SUS_ACK,			0x40, 0x00, 0x01, 0x03, 0x00, 0x00},
+	{ VW_SUS_ACK, 0x40, 0x00, 0x01, 0x03, 0x00, 0x00 },
 	/* MSVW03 Host Index 41h (In) */
-	{VW_SUS_WARN_L,			0x41, 0x00, 0x10, 0x03, 0x00, 0x00},
-	{VW_SUS_PWRDN_ACK_L,		0x41, 0x00, 0x10, 0x03, 0x01, 0x00},
-	{VW_SLP_A_L,			0x41, 0x00, 0x10, 0x03, 0x03, 0x00},
+	{ VW_SUS_WARN_L, 0x41, 0x00, 0x10, 0x03, 0x00, 0x00 },
+	{ VW_SUS_PWRDN_ACK_L, 0x41, 0x00, 0x10, 0x03, 0x01, 0x00 },
+	{ VW_SLP_A_L, 0x41, 0x00, 0x10, 0x03, 0x03, 0x00 },
 	/* MSVW04 Host index 42h (In) */
-	{VW_SLP_LAN,			0x42, 0x00, 0x10, 0x04, 0x00, 0x00},
-	{VW_SLP_WLAN,			0x42, 0x00, 0x10, 0x04, 0x01, 0x00}
+	{ VW_SLP_LAN, 0x42, 0x00, 0x10, 0x04, 0x00, 0x00 },
+	{ VW_SLP_WLAN, 0x42, 0x00, 0x10, 0x04, 0x01, 0x00 }
 };
 BUILD_ASSERT(ARRAY_SIZE(vw_info_tbl) == VW_SIGNAL_COUNT);
 
-
 /************************************************************************/
 /* eSPI internal utilities */
 
@@ -226,14 +240,12 @@ static int espi_vw_get_signal_index(enum espi_vw_signal event)
 	return -1;
 }
 
-
 /*
  * Initialize eSPI hardware upon ESPI_RESET# de-assertion
  */
 #ifdef CONFIG_MCHP_ESPI_RESET_DEASSERT_INIT
 static void espi_reset_deassert_init(void)
 {
-
 }
 #endif
 
@@ -311,7 +323,6 @@ static void espi_vw_restore(void)
 	}
 	MCHP_ESPI_VW_M2S_SRC_ALL(MSVW_H02) = r;
 	CPRINTS("eSPI restore MSVW00(Index 02h) = 0x%08x", r);
-	trace11(0, ESPI, 0, "eSPI restore MSVW00(Index 02h) = 0x%08x", r);
 
 	vb >>= 4;
 	r = 0;
@@ -321,11 +332,9 @@ static void espi_vw_restore(void)
 	}
 	MCHP_ESPI_VW_M2S_SRC_ALL(MSVW_H42) = r;
 	CPRINTS("eSPI restore MSVW00(Index 42h) = 0x%08x", r);
-	trace11(0, ESPI, 0, "eSPI restore MSVW04(Index 42h) = 0x%08x", r);
 
 	r = MCHP_VBAT_RAM(MCHP_VBAT_VWIRE_BACKUP);
 	MCHP_VBAT_RAM(MCHP_VBAT_VWIRE_BACKUP) = r & 0xFFFFFF00;
-
 }
 #endif
 
@@ -346,8 +355,8 @@ static uint8_t __attribute__((unused)) espi_msvw_srcs_get(uint8_t msvw_id)
 	return msvw;
 }
 
-static void __attribute__((unused)) espi_msvw_srcs_set(uint8_t msvw_id,
-						       uint8_t src_bitmap)
+static void __attribute__((unused))
+espi_msvw_srcs_set(uint8_t msvw_id, uint8_t src_bitmap)
 {
 	if (msvw_id < MSVW_MAX) {
 		uint32_t r = (src_bitmap & 0x08) << 21;
@@ -376,8 +385,8 @@ static uint8_t __attribute__((unused)) espi_smvw_srcs_get(uint8_t smvw_id)
 	return smvw;
 }
 
-static void __attribute__((unused)) espi_smvw_srcs_set(uint8_t smvw_id,
-						       uint8_t src_bitmap)
+static void __attribute__((unused))
+espi_smvw_srcs_set(uint8_t smvw_id, uint8_t src_bitmap)
 {
 	if (smvw_id < SMVW_MAX) {
 		uint32_t r = (src_bitmap & 0x08) << 21;
@@ -389,7 +398,6 @@ static void __attribute__((unused)) espi_smvw_srcs_set(uint8_t smvw_id,
 	}
 }
 
-
 /*
  * Called before releasing RSMRST#
  *	ESPI_RESET# is asserted
@@ -416,7 +424,6 @@ static void espi_vw_pre_init(void)
 	uint32_t i;
 
 	CPRINTS("eSPI VW Pre-Init");
-	trace0(0, ESPI, 0, "eSPI VW Pre-Init");
 
 #ifdef CONFIG_MCHP_ESPI_VW_SAVE_ON_SLEEP
 	espi_vw_restore();
@@ -449,10 +456,8 @@ static void espi_vw_pre_init(void)
 	task_enable_irq(MCHP_IRQ_GIRQ25);
 
 	CPRINTS("eSPI VW Pre-Init Done");
-	trace0(0, ESPI, 0, "eSPI VW Pre-Init Done");
 }
 
-
 /*
  * If VWire, Flash, and OOB channels have been enabled
  * then set VWires SLAVE_BOOT_LOAD_STATUS = SLAVE_BOOT_LOAD_DONE = 1
@@ -472,10 +477,8 @@ static void espi_send_boot_load_done(void)
 	MCHP_ESPI_VW_S2M_SRC0(SMVW_H05) = 1;
 
 	CPRINTS("eSPI Send SLAVE_BOOT_LOAD_STATUS/DONE = 1");
-	trace0(0, ESPI, 0, "VW SLAVE_BOOT_LOAD_STATUS/DONE = 1");
 }
 
-
 /*
  * Called when eSPI PLTRST# VWire de-asserts
  * Re-initialize any hardware that was reset while PLTRST# was
@@ -498,7 +501,6 @@ static void espi_send_boot_load_done(void)
 static void espi_host_init(void)
 {
 	CPRINTS("eSPI - espi_host_init");
-	trace0(0, ESPI, 0, "eSPI Host Init");
 
 	/* BAR's */
 
@@ -529,7 +531,6 @@ static void espi_host_init(void)
 	/* PC enable & Mastering enable changes */
 	MCHP_ESPI_PC_IEN = (1ul << 25) + (1ul << 28);
 
-
 	/* Sufficiently initialized */
 	lpc_set_init_done(1);
 
@@ -546,11 +547,9 @@ static void espi_host_init(void)
 	lpc_update_host_event_status();
 
 	CPRINTS("eSPI - espi_host_init Done");
-	trace0(0, ESPI, 0, "eSPI Host Init Done");
 }
 DECLARE_HOOK(HOOK_CHIPSET_STARTUP, espi_host_init, HOOK_PRIO_FIRST);
 
-
 /*
  * Called in response to VWire OOB_RST_WARN==1 from
  * espi_vw_evt_oob_rst_warn.
@@ -562,7 +561,6 @@ static void espi_oob_flush(void)
 {
 }
 
-
 /*
  * Called in response to VWire HOST_RST_WARN==1 from
  * espi_vw_evt_host_rst_warn.
@@ -578,14 +576,12 @@ static void espi_pc_flush(void)
 void espi_vw_power_signal_interrupt(enum espi_vw_signal signal)
 {
 	CPRINTS("eSPI power signal interrupt for VW %d", signal);
-	trace1(0, ESPI, 0, "eSPI pwr intr VW %d", (signal - VW_SIGNAL_START));
-	power_signal_interrupt((enum gpio_signal) signal);
+	power_signal_interrupt((enum gpio_signal)signal);
 }
 
 /************************************************************************/
 /* IC specific low-level driver */
 
-
 /**
  * Set eSPI Virtual-Wire signal to Host
  *
@@ -612,7 +608,7 @@ int espi_vw_set_wire(enum espi_vw_signal signal, uint8_t level)
 	if (level)
 		level = 1;
 
-	if (signal == VW_SLAVE_BTLD_STATUS_DONE) {
+	if (signal == VW_PERIPHERAL_BTLD_STATUS_DONE) {
 		/* SLAVE_BOOT_LOAD_STATUS */
 		MCHP_ESPI_VW_S2M_SRC3(ridx) = level;
 		/* SLAVE_BOOT_LOAD_DONE after status */
@@ -622,10 +618,8 @@ int espi_vw_set_wire(enum espi_vw_signal signal, uint8_t level)
 	}
 
 #ifdef CONFIG_MCHP_ESPI_DEBUG
-	CPRINTS("eSPI VW Set Wire %s = %d",
-		espi_vw_get_wire_name(signal), level);
-	trace2(0, ESPI, 0, "VW SetWire[%d] = %d",
-	       ((uint32_t)signal - VW_SIGNAL_START), level);
+	CPRINTS("eSPI VW Set Wire %s = %d", espi_vw_get_wire_name(signal),
+		level);
 #endif
 
 	return EC_SUCCESS;
@@ -641,16 +635,14 @@ int espi_vw_set_wire(enum espi_vw_signal signal, uint8_t level)
  * happen quickly is bus is idle. Poll for hardware clearing change bit
  * until timeout.
  */
-static int espi_vw_s2m_set_w4m(uint32_t ridx, uint32_t src_num,
-		uint8_t level)
+static int espi_vw_s2m_set_w4m(uint32_t ridx, uint32_t src_num, uint8_t level)
 {
 	uint32_t i;
 
 	MCHP_ESPI_VW_S2M_SRC(ridx, src_num) = level & 0x01;
 
 	for (i = 0; i < ESPI_S2M_VW_PULSE_LOOP_CNT; i++) {
-		if ((MCHP_ESPI_VW_S2M_CHANGE(ridx) &
-		     (1u << src_num)) == 0)
+		if ((MCHP_ESPI_VW_S2M_CHANGE(ridx) & (1u << src_num)) == 0)
 			return EC_SUCCESS;
 		udelay(ESPI_S2M_VW_PULSE_LOOP_DLY_US);
 	}
@@ -691,10 +683,8 @@ int espi_vw_pulse_wire(enum espi_vw_signal signal, int pulse_level)
 		level = 1;
 
 #ifdef CONFIG_MCHP_ESPI_DEBUG
-	CPRINTS("eSPI VW Pulse Wire %s to %d",
-		espi_vw_get_wire_name(signal), level);
-	trace2(0, ESPI, 0, "eSPI pulse VW[%d] = %d", signal, level);
-	trace2(0, ESPI, 0, " S2M index=%d src=%d", ridx, src_num);
+	CPRINTS("eSPI VW Pulse Wire %s to %d", espi_vw_get_wire_name(signal),
+		level);
 #endif
 
 	/* set requested inactive state */
@@ -702,6 +692,9 @@ int espi_vw_pulse_wire(enum espi_vw_signal signal, int pulse_level)
 	if (rc != EC_SUCCESS)
 		return rc;
 
+	/* Ensure a minimum pulse width is met. */
+	udelay(CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US);
+
 	/* drive to requested active state */
 	rc = espi_vw_s2m_set_w4m(ridx, src_num, level);
 	if (rc != EC_SUCCESS)
@@ -732,10 +725,8 @@ int espi_vw_get_wire(enum espi_vw_signal signal)
 		src_num = vw_info_tbl[tidx].src_num;
 		vw = MCHP_ESPI_VW_M2S_SRC(ridx, src_num) & 0x01;
 #ifdef CONFIG_MCHP_ESPI_DEBUG
-		CPRINTS("VW GetWire %s = %d",
-			espi_vw_get_wire_name(signal), vw);
-		trace2(0, ESPI, 0, "VW GetWire[%d] = %d",
-		       ((uint32_t)signal - VW_SIGNAL_START), vw);
+		CPRINTS("VW GetWire %s = %d", espi_vw_get_wire_name(signal),
+			vw);
 #endif
 	}
 
@@ -762,10 +753,7 @@ int espi_vw_enable_wire_int(enum espi_vw_signal signal)
 		return EC_ERROR_PARAM1; /* signal is Slave-to-Master */
 
 #ifdef CONFIG_MCHP_ESPI_DEBUG
-	CPRINTS("VW IntrEn for VW[%s]",
-		espi_vw_get_wire_name(signal));
-	trace1(0, ESPI, 0, "VW IntrEn for VW[%d]",
-	       ((uint32_t)signal - VW_SIGNAL_START));
+	CPRINTS("VW IntrEn for VW[%s]", espi_vw_get_wire_name(signal));
 #endif
 
 	ridx = vw_info_tbl[tidx].reg_idx;
@@ -778,7 +766,7 @@ int espi_vw_enable_wire_int(enum espi_vw_signal signal)
 	 * GIRQ25 MSVW07[0:3] through MSVW10[0:3] (bits[0:25])
 	 */
 	MCHP_ESPI_VW_M2S_IRQSEL(ridx, src_num) =
-			MCHP_ESPI_MSVW_IRQSEL_BOTH_EDGES;
+		MCHP_ESPI_MSVW_IRQSEL_BOTH_EDGES;
 
 	girq_num = 24;
 	if (ridx > 6) {
@@ -813,10 +801,7 @@ int espi_vw_disable_wire_int(enum espi_vw_signal signal)
 		return EC_ERROR_PARAM1; /* signal is Slave-to-Master */
 
 #ifdef CONFIG_MCHP_ESPI_DEBUG
-	CPRINTS("VW IntrDis for VW[%s]",
-		espi_vw_get_wire_name(signal));
-	trace1(0, ESPI, 0, "VW IntrDis for VW[%d]",
-	       (signal - VW_SIGNAL_START));
+	CPRINTS("VW IntrDis for VW[%s]", espi_vw_get_wire_name(signal));
 #endif
 
 	ridx = vw_info_tbl[tidx].reg_idx;
@@ -828,8 +813,7 @@ int espi_vw_disable_wire_int(enum espi_vw_signal signal)
 	 * GIRQ24 MSVW00[0:3] through MSVW06[0:3] (bits[0:27])
 	 * GIRQ25 MSVW07[0:3] through MSVW10[0:3] (bits[0:25])
 	 */
-	MCHP_ESPI_VW_M2S_IRQSEL(ridx, src_num) =
-			MCHP_ESPI_MSVW_IRQSEL_DISABLED;
+	MCHP_ESPI_VW_M2S_IRQSEL(ridx, src_num) = MCHP_ESPI_MSVW_IRQSEL_DISABLED;
 
 	if (ridx < 7) {
 		bpos = (ridx << 2) + src_num;
@@ -850,37 +834,33 @@ int espi_vw_disable_wire_int(enum espi_vw_signal signal)
 static void espi_chipset_reset(void)
 {
 	hook_notify(HOOK_CHIPSET_RESET);
+	update_ap_boot_time(ESPIRST);
 }
 DECLARE_DEFERRED(espi_chipset_reset);
 #endif
 
-
 /* SLP_Sx event handler */
 void espi_vw_evt_slp_s3_n(uint32_t wire_state, uint32_t bpos)
 {
 	CPRINTS("VW SLP_S3: %d", wire_state);
-	trace1(0, ESPI, 0, "VW_SLP_S3_L change to %d", wire_state);
 	espi_vw_power_signal_interrupt(VW_SLP_S3_L);
 }
 
 void espi_vw_evt_slp_s4_n(uint32_t wire_state, uint32_t bpos)
 {
 	CPRINTS("VW SLP_S4: %d", wire_state);
-	trace1(0, ESPI, 0, "VW_SLP_S4_L change to %d", wire_state);
 	espi_vw_power_signal_interrupt(VW_SLP_S4_L);
 }
 
 void espi_vw_evt_slp_s5_n(uint32_t wire_state, uint32_t bpos)
 {
 	CPRINTS("VW SLP_S5: %d", wire_state);
-	trace1(0, ESPI, 0, "VW_SLP_S5_L change to %d", wire_state);
 	espi_vw_power_signal_interrupt(VW_SLP_S5_L);
 }
 
 void espi_vw_evt_sus_stat_n(uint32_t wire_state, uint32_t bpos)
 {
 	CPRINTS("VW SUS_STAT: %d", wire_state);
-	trace1(0, ESPI, 0, "VW_SUS_STAT change to %d", wire_state);
 	espi_vw_power_signal_interrupt(VW_SUS_STAT_L);
 }
 
@@ -888,22 +868,22 @@ void espi_vw_evt_sus_stat_n(uint32_t wire_state, uint32_t bpos)
 void espi_vw_evt_pltrst_n(uint32_t wire_state, uint32_t bpos)
 {
 	CPRINTS("VW PLTRST#: %d", wire_state);
-	trace1(0, ESPI, 0, "VW_PLTRST# change to %d", wire_state);
 
-	if (wire_state) /* Platform Reset de-assertion */
+	if (wire_state) { /* Platform Reset de-assertion */
 		espi_host_init();
-	else /* assertion */
+		update_ap_boot_time(PLTRST_HIGH);
+	} else { /* assertion */
 #ifdef CONFIG_CHIPSET_RESET_HOOK
 		hook_call_deferred(&espi_chipset_reset_data, MSEC);
 #endif
-
+		update_ap_boot_time(PLTRST_LOW);
+	}
 }
 
 /* OOB Reset Warn event handler */
 void espi_vw_evt_oob_rst_warn(uint32_t wire_state, uint32_t bpos)
 {
 	CPRINTS("VW OOB_RST_WARN: %d", wire_state);
-	trace1(0, ESPI, 0, "VW_OOB_RST_WARN change to %d", wire_state);
 
 	espi_oob_flush();
 
@@ -914,7 +894,6 @@ void espi_vw_evt_oob_rst_warn(uint32_t wire_state, uint32_t bpos)
 void espi_vw_evt_sus_warn_n(uint32_t wire_state, uint32_t bpos)
 {
 	CPRINTS("VW SUS_WARN#: %d", wire_state);
-	trace1(0, ESPI, 0, "VW_SUS_WARN# change to %d", wire_state);
 
 	udelay(100);
 
@@ -938,7 +917,6 @@ void espi_vw_evt_sus_warn_n(uint32_t wire_state, uint32_t bpos)
  */
 void espi_vw_evt_sus_pwrdn_ack(uint32_t wire_state, uint32_t bpos)
 {
-	trace1(0, ESPI, 0, "VW_SUS_PWRDN_ACK change to %d", wire_state);
 	CPRINTS("VW SUS_PWRDN_ACK: %d", wire_state);
 }
 
@@ -946,7 +924,6 @@ void espi_vw_evt_sus_pwrdn_ack(uint32_t wire_state, uint32_t bpos)
 void espi_vw_evt_slp_a_n(uint32_t wire_state, uint32_t bpos)
 {
 	CPRINTS("VW SLP_A: %d", wire_state);
-	trace1(0, ESPI, 0, "VW_SLP_A# change to %d", wire_state);
 
 	/* Put handling of ASW well devices here, if any */
 }
@@ -955,7 +932,6 @@ void espi_vw_evt_slp_a_n(uint32_t wire_state, uint32_t bpos)
 void espi_vw_evt_host_rst_warn(uint32_t wire_state, uint32_t bpos)
 {
 	CPRINTS("VW HOST_RST_WARN: %d", wire_state);
-	trace1(0, ESPI, 0, "VW_HOST_RST_WARN change to %d", wire_state);
 
 	espi_pc_flush();
 
@@ -967,32 +943,27 @@ void espi_vw_evt_host_rst_warn(uint32_t wire_state, uint32_t bpos)
 void espi_vw_evt_slp_lan_n(uint32_t wire_state, uint32_t bpos)
 {
 	CPRINTS("VW SLP_LAN: %d", wire_state);
-	trace1(0, ESPI, 0, "VW_SLP_LAN# change to %d", wire_state);
 }
 
 /* SLP_WLAN# */
 void espi_vw_evt_slp_wlan_n(uint32_t wire_state, uint32_t bpos)
 {
 	CPRINTS("VW SLP_WLAN: %d", wire_state);
-	trace1(0, ESPI, 0, "VW_SLP_WLAN# change to %d", wire_state);
 }
 
 void espi_vw_evt_host_c10(uint32_t wire_state, uint32_t bpos)
 {
 	CPRINTS("VW HOST_C10: %d", wire_state);
-	trace1(0, ESPI, 0, "VW_HOST_C10 change to %d", wire_state);
 }
 
 void espi_vw_evt1_dflt(uint32_t wire_state, uint32_t bpos)
 {
 	CPRINTS("Unknown M2S VW: state=%d GIRQ24 bitpos=%d", wire_state, bpos);
-	MCHP_INT_DISABLE(24) = (1ul << bpos);
 }
 
 void espi_vw_evt2_dflt(uint32_t wire_state, uint32_t bpos)
 {
 	CPRINTS("Unknown M2S VW: state=%d GIRQ25 bitpos=%d", wire_state, bpos);
-	MCHP_INT_DISABLE(25) = (1ul << bpos);
 }
 
 /************************************************************************/
@@ -1035,13 +1006,13 @@ void espi_vw_evt2_dflt(uint32_t wire_state, uint32_t bpos)
 
 typedef void (*FPVW)(uint32_t, uint32_t);
 
-#define MCHP_GIRQ24_NUM_M2S	(7 * 4)
+#define MCHP_GIRQ24_NUM_M2S (7 * 4)
 const FPVW girq24_vw_handlers[MCHP_GIRQ24_NUM_M2S] = {
-	espi_vw_evt_slp_s3_n,	/* MSVW00, Host M2S 02h */
+	espi_vw_evt_slp_s3_n, /* MSVW00, Host M2S 02h */
 	espi_vw_evt_slp_s4_n,
 	espi_vw_evt_slp_s5_n,
 	espi_vw_evt1_dflt,
-	espi_vw_evt_sus_stat_n,	/* MSVW01, Host M2S 03h */
+	espi_vw_evt_sus_stat_n, /* MSVW01, Host M2S 03h */
 	espi_vw_evt_pltrst_n,
 	espi_vw_evt_oob_rst_warn,
 	espi_vw_evt1_dflt,
@@ -1049,46 +1020,38 @@ const FPVW girq24_vw_handlers[MCHP_GIRQ24_NUM_M2S] = {
 	espi_vw_evt1_dflt,
 	espi_vw_evt1_dflt,
 	espi_vw_evt1_dflt,
-	espi_vw_evt_sus_warn_n,	/* MSVW03, Host M2S 41h */
+	espi_vw_evt_sus_warn_n, /* MSVW03, Host M2S 41h */
 	espi_vw_evt_sus_pwrdn_ack,
 	espi_vw_evt1_dflt,
 	espi_vw_evt_slp_a_n,
-	espi_vw_evt_slp_lan_n,	/* MSVW04, Host M2S 42h */
+	espi_vw_evt_slp_lan_n, /* MSVW04, Host M2S 42h */
 	espi_vw_evt_slp_wlan_n,
 	espi_vw_evt1_dflt,
 	espi_vw_evt1_dflt,
-	espi_vw_evt1_dflt,	/* MSVW05, Host M2S 43h */
+	espi_vw_evt1_dflt, /* MSVW05, Host M2S 43h */
 	espi_vw_evt1_dflt,
 	espi_vw_evt1_dflt,
 	espi_vw_evt1_dflt,
-	espi_vw_evt1_dflt,	/* MSVW06, Host M2S 44h */
+	espi_vw_evt1_dflt, /* MSVW06, Host M2S 44h */
 	espi_vw_evt1_dflt,
 	espi_vw_evt1_dflt,
 	espi_vw_evt1_dflt
 };
 
-#define MCHP_GIRQ25_NUM_M2S	(4 * 4)
+#define MCHP_GIRQ25_NUM_M2S (4 * 4)
 const FPVW girq25_vw_handlers[MCHP_GIRQ25_NUM_M2S] = {
-	espi_vw_evt_host_c10,	/* MSVW07, Host M2S 47h */
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,	/* MSVW08 unassigned */
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,	/* MSVW09 unassigned */
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,	/* MSVW10 unassigned */
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,
+	espi_vw_evt_host_c10, /* MSVW07, Host M2S 47h */
+	espi_vw_evt2_dflt,    espi_vw_evt2_dflt, espi_vw_evt2_dflt,
+	espi_vw_evt2_dflt, /* MSVW08 unassigned */
+	espi_vw_evt2_dflt,    espi_vw_evt2_dflt, espi_vw_evt2_dflt,
+	espi_vw_evt2_dflt, /* MSVW09 unassigned */
+	espi_vw_evt2_dflt,    espi_vw_evt2_dflt, espi_vw_evt2_dflt,
+	espi_vw_evt2_dflt, /* MSVW10 unassigned */
+	espi_vw_evt2_dflt,    espi_vw_evt2_dflt, espi_vw_evt2_dflt,
 };
 
 /* Interrupt handler for eSPI virtual wires in MSVW00 - MSVW01 */
-void espi_mswv1_interrupt(void)
+static void espi_mswv1_interrupt(void)
 {
 	uint32_t d, girq24_result, bpos;
 
@@ -1096,20 +1059,19 @@ void espi_mswv1_interrupt(void)
 	girq24_result = MCHP_INT_RESULT(24);
 	MCHP_INT_SOURCE(24) = girq24_result;
 
-	bpos = __builtin_ctz(girq24_result); /* rbit, clz sequence */
-	while (bpos != 32) {
-		d = *(uint8_t *)(MCHP_ESPI_MSVW_BASE + 8 +
-				(12 * (bpos >> 2)) + (bpos & 0x03)) & 0x01;
+	while (girq24_result) {
+		bpos = __builtin_ctz(girq24_result); /* rbit, clz sequence */
+		d = *(uint8_t *)(MCHP_ESPI_MSVW_BASE + 8 + (12 * (bpos >> 2)) +
+				 (bpos & 0x03)) &
+		    0x01;
 		(girq24_vw_handlers[bpos])(d, bpos);
 		girq24_result &= ~(1ul << bpos);
-		bpos = __builtin_ctz(girq24_result);
 	}
 }
 DECLARE_IRQ(MCHP_IRQ_GIRQ24, espi_mswv1_interrupt, 2);
 
-
 /* Interrupt handler for eSPI virtual wires in MSVW07 - MSVW10 */
-void espi_msvw2_interrupt(void)
+static void espi_msvw2_interrupt(void)
 {
 	uint32_t d, girq25_result, bpos;
 
@@ -1117,19 +1079,17 @@ void espi_msvw2_interrupt(void)
 	girq25_result = MCHP_INT_RESULT(25);
 	MCHP_INT_SOURCE(25) = girq25_result;
 
-	bpos = __builtin_ctz(girq25_result); /* rbit, clz sequence */
-	while (bpos != 32) {
+	while (girq25_result) {
+		bpos = __builtin_ctz(girq25_result); /* rbit, clz sequence */
 		d = *(uint8_t *)(MCHP_ESPI_MSVW_BASE + (12 * 7) + 8 +
-				(12 * (bpos >> 2)) + (bpos & 0x03)) & 0x01;
+				 (12 * (bpos >> 2)) + (bpos & 0x03)) &
+		    0x01;
 		(girq25_vw_handlers[bpos])(d, bpos);
 		girq25_result &= ~(1ul << bpos);
-		bpos = __builtin_ctz(girq25_result);
 	}
 }
 DECLARE_IRQ(MCHP_IRQ_GIRQ25, espi_msvw2_interrupt, 2);
 
-
-
 /*
  * NOTES:
  * While ESPI_RESET# is asserted, all eSPI blocks are held in reset and
@@ -1170,7 +1130,7 @@ DECLARE_IRQ(MCHP_IRQ_GIRQ25, espi_msvw2_interrupt, 2);
  * equivalent to eSPI Platform Reset.
  *
  */
-void espi_reset_isr(void)
+static void espi_reset_isr(void)
 {
 	uint8_t erst;
 
@@ -1178,34 +1138,26 @@ void espi_reset_isr(void)
 	MCHP_ESPI_IO_RESET_STATUS = erst;
 	MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) = MCHP_ESPI_RESET_GIRQ_BIT;
 	if (erst & (1ul << 1)) { /* rising edge - reset de-asserted */
-		MCHP_INT_ENABLE(MCHP_ESPI_GIRQ) = (
-				MCHP_ESPI_PC_GIRQ_BIT +
-				MCHP_ESPI_OOB_TX_GIRQ_BIT +
-				MCHP_ESPI_FC_GIRQ_BIT +
-				MCHP_ESPI_VW_EN_GIRQ_BIT);
+		MCHP_INT_ENABLE(MCHP_ESPI_GIRQ) =
+			(MCHP_ESPI_PC_GIRQ_BIT + MCHP_ESPI_OOB_TX_GIRQ_BIT +
+			 MCHP_ESPI_FC_GIRQ_BIT + MCHP_ESPI_VW_EN_GIRQ_BIT);
 		MCHP_ESPI_OOB_TX_IEN = (1ul << 1);
 		MCHP_ESPI_FC_IEN = (1ul << 1);
 		MCHP_ESPI_PC_IEN = (1ul << 25);
 		CPRINTS("eSPI Reset de-assert");
-		trace0(0, ESPI, 0, "eSPI Reset de-assert");
 
 	} else { /* falling edge - reset asserted */
-		MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) = (
-					MCHP_ESPI_PC_GIRQ_BIT +
-					MCHP_ESPI_OOB_TX_GIRQ_BIT +
-					MCHP_ESPI_FC_GIRQ_BIT +
-					MCHP_ESPI_VW_EN_GIRQ_BIT);
-		MCHP_INT_DISABLE(MCHP_ESPI_GIRQ) = (
-					MCHP_ESPI_PC_GIRQ_BIT +
-					MCHP_ESPI_OOB_TX_GIRQ_BIT +
-					MCHP_ESPI_FC_GIRQ_BIT +
-					MCHP_ESPI_VW_EN_GIRQ_BIT);
+		MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) =
+			(MCHP_ESPI_PC_GIRQ_BIT + MCHP_ESPI_OOB_TX_GIRQ_BIT +
+			 MCHP_ESPI_FC_GIRQ_BIT + MCHP_ESPI_VW_EN_GIRQ_BIT);
+		MCHP_INT_DISABLE(MCHP_ESPI_GIRQ) =
+			(MCHP_ESPI_PC_GIRQ_BIT + MCHP_ESPI_OOB_TX_GIRQ_BIT +
+			 MCHP_ESPI_FC_GIRQ_BIT + MCHP_ESPI_VW_EN_GIRQ_BIT);
 		espi_channels_ready = 0;
 
 		chipset_handle_espi_reset_assert();
 
 		CPRINTS("eSPI Reset assert");
-		trace0(0, ESPI, 0, "eSPI Reset assert");
 	}
 }
 DECLARE_IRQ(MCHP_IRQ_ESPI_RESET, espi_reset_isr, 3);
@@ -1214,7 +1166,7 @@ DECLARE_IRQ(MCHP_IRQ_ESPI_RESET, espi_reset_isr, 3);
  * eSPI Virtual Wire channel enable handler
  * Must disable once VW Enable is set by eSPI Master
  */
-void espi_vw_en_isr(void)
+static void espi_vw_en_isr(void)
 {
 	MCHP_INT_DISABLE(MCHP_ESPI_GIRQ) = MCHP_ESPI_VW_EN_GIRQ_BIT;
 	MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) = MCHP_ESPI_VW_EN_GIRQ_BIT;
@@ -1224,18 +1176,16 @@ void espi_vw_en_isr(void)
 	espi_channels_ready |= (1ul << 0);
 
 	CPRINTS("eSPI VW Enable received, set VW Ready");
-	trace0(0, ESPI, 0, "VW Enable. Set VW Ready");
 
 	if (0x03 == (espi_channels_ready & 0x03))
 		espi_send_boot_load_done();
 }
 DECLARE_IRQ(MCHP_IRQ_ESPI_VW_EN, espi_vw_en_isr, 2);
 
-
 /*
  * eSPI OOB TX and OOB channel enable change interrupt handler
  */
-void espi_oob_tx_isr(void)
+static void espi_oob_tx_isr(void)
 {
 	uint32_t sts;
 
@@ -1249,23 +1199,19 @@ void espi_oob_tx_isr(void)
 			MCHP_ESPI_IO_OOB_READY = 1;
 			espi_channels_ready |= (1ul << 2);
 			CPRINTS("eSPI OOB_UP ISR: OOB Channel Enable");
-			trace0(0, ESPI, 0, "OOB_TX OOB Enable");
 		} else { /* no, disabled by Master */
 			espi_channels_ready &= ~(1ul << 2);
 			CPRINTS("eSPI OOB_UP ISR: OOB Channel Disable");
-			trace0(0, ESPI, 0, "eSPI OOB_TX OOB Disable");
 		}
 	} else {
 		/* Handle OOB Up transmit status: done and/or errors, here */
 		CPRINTS("eSPI OOB_UP status = 0x%x", sts);
-		trace11(0, ESPI, 0, "eSPI OOB_TX Status = 0x%08x", sts);
 	}
 }
 DECLARE_IRQ(MCHP_IRQ_ESPI_OOB_UP, espi_oob_tx_isr, 2);
 
-
 /* eSPI OOB RX interrupt handler */
-void espi_oob_rx_isr(void)
+static void espi_oob_rx_isr(void)
 {
 	uint32_t sts;
 
@@ -1274,16 +1220,14 @@ void espi_oob_rx_isr(void)
 	MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) = MCHP_ESPI_OOB_RX_GIRQ_BIT;
 	/* Handle OOB Up transmit status: done and/or errors, if any */
 	CPRINTS("eSPI OOB_DN status = 0x%x", sts);
-	trace11(0, ESPI, 0, "eSPI OOB_RX Status = 0x%08x", sts);
 }
 DECLARE_IRQ(MCHP_IRQ_ESPI_OOB_DN, espi_oob_rx_isr, 2);
 
-
 /*
  * eSPI Flash Channel enable change and data transfer
  * interrupt handler
  */
-void espi_fc_isr(void)
+static void espi_fc_isr(void)
 {
 	uint32_t sts;
 
@@ -1296,25 +1240,21 @@ void espi_fc_isr(void)
 			MCHP_ESPI_IO_FC_READY = 1;
 			espi_channels_ready |= (1ul << 1);
 			CPRINTS("eSPI FC ISR: Enable");
-			trace0(0, ESPI, 0, "eSPI FC Enable");
 			if (0x03 == (espi_channels_ready & 0x03))
 				espi_send_boot_load_done();
 		} else { /* no, disabled by Master */
 			espi_channels_ready &= ~(1ul << 1);
 			CPRINTS("eSPI FC ISR: Disable");
-			trace0(0, ESPI, 0, "eSPI FC Disable");
 		}
 	} else {
 		/* Handle FC command status: done and/or errors */
 		CPRINTS("eSPI FC status = 0x%x", sts);
-		trace11(0, ESPI, 0, "eSPI FC Status = 0x%08x", sts);
 	}
 }
 DECLARE_IRQ(MCHP_IRQ_ESPI_FC, espi_fc_isr, 2);
 
-
 /* eSPI Peripheral Channel interrupt handler */
-void espi_pc_isr(void)
+static void espi_pc_isr(void)
 {
 	uint32_t sts;
 
@@ -1326,22 +1266,18 @@ void espi_pc_isr(void)
 			MCHP_ESPI_IO_PC_READY = 1;
 			espi_channels_ready |= (1ul << 3);
 			CPRINTS("eSPI PC Channel Enable");
-			trace0(0, ESPI, 0, "eSPI PC Enable");
 		} else {
 			espi_channels_ready &= ~(1ul << 3);
 			CPRINTS("eSPI PC Channel Disable");
-			trace0(0, ESPI, 0, "eSPI PC Disable");
 		}
 
 	} else {
 		/* Handler PC channel errors here */
 		CPRINTS("eSPI PC status = 0x%x", sts);
-		trace11(0, ESPI, 0, "eSPI PC Status = 0x%08x", sts);
 	}
 }
 DECLARE_IRQ(MCHP_IRQ_ESPI_PC, espi_pc_isr, 2);
 
-
 /************************************************************************/
 
 /*
@@ -1352,25 +1288,21 @@ static void espi_reset_ictrl(int enable, int clr_status)
 {
 	if (enable) {
 		if (clr_status) {
-			MCHP_ESPI_IO_RESET_STATUS =
-					MCHP_ESPI_RST_CHG_STS;
+			MCHP_ESPI_IO_RESET_STATUS = MCHP_ESPI_RST_CHG_STS;
 			MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) =
-					MCHP_ESPI_RESET_GIRQ_BIT;
+				MCHP_ESPI_RESET_GIRQ_BIT;
 		}
 		MCHP_ESPI_IO_RESET_IEN |= MCHP_ESPI_RST_IEN;
-		MCHP_INT_ENABLE(MCHP_ESPI_GIRQ) =
-				MCHP_ESPI_RESET_GIRQ_BIT;
+		MCHP_INT_ENABLE(MCHP_ESPI_GIRQ) = MCHP_ESPI_RESET_GIRQ_BIT;
 		task_enable_irq(MCHP_IRQ_ESPI_RESET);
 	} else {
 		task_disable_irq(MCHP_IRQ_ESPI_RESET);
-		MCHP_INT_DISABLE(MCHP_ESPI_GIRQ) =
-				MCHP_ESPI_RESET_GIRQ_BIT;
+		MCHP_INT_DISABLE(MCHP_ESPI_GIRQ) = MCHP_ESPI_RESET_GIRQ_BIT;
 		MCHP_ESPI_IO_RESET_IEN &= ~(MCHP_ESPI_RST_IEN);
 		if (clr_status) {
-			MCHP_ESPI_IO_RESET_STATUS =
-					MCHP_ESPI_RST_CHG_STS;
+			MCHP_ESPI_IO_RESET_STATUS = MCHP_ESPI_RST_CHG_STS;
 			MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) =
-					MCHP_ESPI_RESET_GIRQ_BIT;
+				MCHP_ESPI_RESET_GIRQ_BIT;
 		}
 	}
 }
@@ -1383,7 +1315,6 @@ void espi_init(void)
 	espi_channels_ready = 0;
 
 	CPRINTS("eSPI - espi_init");
-	trace0(0, ESPI, 0, "eSPI Init");
 
 	/* Clear PCR eSPI sleep enable */
 	MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_ESPI);
@@ -1403,40 +1334,24 @@ void espi_init(void)
 	 */
 	gpio_config_module(MODULE_LPC, 1);
 
-	/* Override Boot-ROM configuration */
-#ifdef CONFIG_HOSTCMD_ESPI_EC_CHAN_BITMAP
-	MCHP_ESPI_IO_CAP0 = CONFIG_HOSTCMD_ESPI_EC_CHAN_BITMAP;
-#endif
-
-#ifdef CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ
-	MCHP_ESPI_IO_CAP1 &= ~(MCHP_ESPI_CAP1_MAX_FREQ_MASK);
-#if CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ == 25
-	MCHP_ESPI_IO_CAP1 |= MCHP_ESPI_CAP1_MAX_FREQ_25M;
-#elif CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ == 33
-	MCHP_ESPI_IO_CAP1 |= MCHP_ESPI_CAP1_MAX_FREQ_33M;
-#elif CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ == 50
-	MCHP_ESPI_IO_CAP1 |= MCHP_ESPI_CAP1_MAX_FREQ_50M;
-#elif CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ == 66
-	MCHP_ESPI_IO_CAP1 |= MCHP_ESPI_CAP1_MAX_FREQ_66M;
-#else
-	MCHP_ESPI_IO_CAP1 |= MCHP_ESPI_CAP1_MAX_FREQ_20M;
-#endif
-#endif
+	/* Set channel */
+	MCHP_ESPI_IO_CAP0 = CONFIG_HOST_INTERFACE_ESPI_EC_CHAN_BITMAP;
 
-#ifdef CONFIG_HOSTCMD_ESPI_EC_MODE
-	MCHP_ESPI_IO_CAP1 &= ~(MCHP_ESPI_CAP1_IO_MASK);
-	MCHP_ESPI_IO_CAP1 |= ((CONFIG_HOSTCMD_ESPI_EC_MODE)
-		<< MCHP_ESPI_CAP1_IO_BITPOS);
-#endif
+	/* Set eSPI frequency & mode */
+	MCHP_ESPI_IO_CAP1 =
+		(MCHP_ESPI_IO_CAP1 &
+		 (~(MCHP_ESPI_CAP1_MAX_FREQ_MASK | MCHP_ESPI_CAP1_IO_MASK))) |
+		CONFIG_HOST_INTERFACE_ESPI_EC_MAX_FREQ |
+		(CONFIG_HOST_INTERFACE_ESPI_EC_MODE
+		 << MCHP_ESPI_CAP1_IO_BITPOS);
 
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	MCHP_ESPI_IO_PLTRST_SRC = MCHP_ESPI_PLTRST_SRC_VW;
 #else
 	MCHP_ESPI_IO_PLTRST_SRC = MCHP_ESPI_PLTRST_SRC_PIN;
 #endif
 
-	MCHP_PCR_PWR_RST_CTL &=
-		~(1ul << MCHP_PCR_PWR_HOST_RST_SEL_BITPOS);
+	MCHP_PCR_PWR_RST_CTL &= ~(1ul << MCHP_PCR_PWR_HOST_RST_SEL_BITPOS);
 
 	MCHP_ESPI_ACTIVATE = 1;
 
@@ -1462,8 +1377,8 @@ void espi_init(void)
 	MCHP_ESPI_PC_STATUS = 0xfffffffful;
 	MCHP_ESPI_OOB_RX_STATUS = 0xfffffffful;
 	MCHP_ESPI_FC_STATUS = 0xfffffffful;
-	MCHP_INT_DISABLE(MCHP_ESPI_GIRQ) = 0x1FFul;
-	MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) = 0x1FFul;
+	MCHP_INT_DISABLE(MCHP_ESPI_GIRQ) = 0xfffffffful;
+	MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) = 0xfffffffful;
 
 	task_enable_irq(MCHP_IRQ_ESPI_PC);
 	task_enable_irq(MCHP_IRQ_ESPI_OOB_UP);
@@ -1476,27 +1391,22 @@ void espi_init(void)
 	 * and will be controlled by espi_vw_enable/disable_wire_in
 	 */
 	CPRINTS("eSPI - enable ESPI_RESET# interrupt");
-	trace0(0, ESPI, 0, "Enable ESPI_RESET# interrupt");
 
 	/* Enable ESPI_RESET# interrupt and clear status */
 	espi_reset_ictrl(1, 1);
 
 	CPRINTS("eSPI - espi_init - done");
-	trace0(0, ESPI, 0, "eSPI Init Done");
-
 }
 
-
 #ifdef CONFIG_MCHP_ESPI_EC_CMD
-/* TODO */
-static int command_espi(int argc, char **argv)
+static int command_espi(int argc, const char **argv)
 {
 	uint32_t chan, w0, w1, w2;
 	char *e;
 
 	if (argc == 1) {
 		return EC_ERROR_INVAL;
-	/* Get value of eSPI registers */
+		/* Get value of eSPI registers */
 	} else if (argc == 2) {
 		int i;
 
@@ -1514,8 +1424,8 @@ static int command_espi(int argc, char **argv)
 				w0 = MSVW(i, 0);
 				w1 = MSVW(i, 1);
 				w2 = MSVW(i, 2);
-				ccprintf("MSVW%d: 0x%08x:%08x:%08x\n", i,
-					w2, w1, w0);
+				ccprintf("MSVW%d: 0x%08x:%08x:%08x\n", i, w2,
+					 w1, w0);
 			}
 		} else if (strcasecmp(argv[1], "vms") == 0) {
 			for (i = 0; i < SMVW_MAX; i++) {
@@ -1524,9 +1434,9 @@ static int command_espi(int argc, char **argv)
 				ccprintf("SMVW%d: 0x%08x:%08x\n", i, w1, w0);
 			}
 		}
-	/* Enable/Disable the channels of eSPI */
+		/* Enable/Disable the channels of eSPI */
 	} else if (argc == 3) {
-		uint32_t m = (uint32_t) strtoi(argv[2], &e, 0);
+		uint32_t m = (uint32_t)strtoi(argv[2], &e, 0);
 
 		if (*e)
 			return EC_ERROR_PARAM2;
@@ -1546,7 +1456,6 @@ static int command_espi(int argc, char **argv)
 	}
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(espi, command_espi,
-			"cfg/vms/vsm/en/dis [channel]",
+DECLARE_CONSOLE_COMMAND(espi, command_espi, "cfg/vms/vsm/en/dis [channel]",
 			"eSPI configurations");
 #endif
diff --git a/chip/mchp/fan.c b/chip/mchp/fan.c
index dc939bb58f..c68d71bcc8 100644
--- a/chip/mchp/fan.c
+++ b/chip/mchp/fan.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,8 +9,14 @@
 
 #include "fan.h"
 #include "registers.h"
-#include "util.h"
 #include "tfdp_chip.h"
+#include "util.h"
+
+/* Maximum fan driver setting value */
+#define MAX_FAN_DRIVER_SETTING 0x3ff
+
+/* Fan driver setting data in bit[15:6] of hardware register */
+#define FAN_DRIVER_SETTING_SHIFT 6
 
 /* Maximum tach reading/target value */
 #define MAX_TACH 0x1fff
@@ -32,7 +38,6 @@ static int rpm_setting;
 static int duty_setting;
 static int in_rpm_mode = 1;
 
-
 static void clear_status(void)
 {
 	/* Clear DRIVE_FAIL, FAN_SPIN, and FAN_STALL bits */
@@ -71,12 +76,15 @@ void fan_set_duty(int ch, int percent)
 		percent = 100;
 
 	duty_setting = percent;
-	MCHP_FAN_SETTING(0) = percent * 255 / 100;
+	MCHP_FAN_SETTING(0) = (percent * MAX_FAN_DRIVER_SETTING / 100)
+			      << FAN_DRIVER_SETTING_SHIFT;
 	clear_status();
 }
 
 int fan_get_duty(int ch)
 {
+	duty_setting = (MCHP_FAN_SETTING(0) >> FAN_DRIVER_SETTING_SHIFT) * 100 /
+		       MAX_FAN_DRIVER_SETTING;
 	return duty_setting;
 }
 
@@ -140,7 +148,8 @@ void fan_channel_setup(int ch, unsigned int flags)
 {
 	/* Clear PCR sleep enable for RPM2FAN0 */
 	MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_RPMPWM0);
-
+	/* Configure PWM Min drive */
+	MCHP_FAN_MIN_DRV(0) = 0x0A;
 	/*
 	 * Fan configuration 1 register:
 	 *   0x80 = bit 7    = RPM mode (0x00 if FAN_USE_RPM_MODE not set)
@@ -149,16 +158,17 @@ void fan_channel_setup(int ch, unsigned int flags)
 	 *   0x03 = bits 2:0 = 400 ms update time
 	 *
 	 * Fan configuration 2 register:
-	 *   0x00 = bit 6    = Ramp control disabled
-	 *   0x00 = bit 5    = Glitch filter enabled
-	 *   0x18 = bits 4:3 = Using both derivative options
-	 *   0x02 = bits 2:1 = error range is 50 RPM
-	 *   0x00 = bits 0   = normal polarity
+	 *   0x00 = bit 7    = Ramp control disabled
+	 *   0x00 = bit 6    = Glitch filter enabled
+	 *   0x30 = bits 5:4 = Using both derivative options
+	 *   0x04 = bits 3:2 = error range is 50 RPM
+	 *   0x00 = bits 1   = normal polarity
+	 *   0x00 = bit 0    = Reserved
 	 */
 	if (flags & FAN_USE_RPM_MODE)
 		MCHP_FAN_CFG1(0) = 0xab;
 	else
 		MCHP_FAN_CFG1(0) = 0x2b;
-	MCHP_FAN_CFG2(0) = 0x1a;
+	MCHP_FAN_CFG2(0) = 0x34;
 	clear_status();
 }
diff --git a/chip/mchp/flash.c b/chip/mchp/flash.c
index 043e2b268f..f0f3a5575e 100644
--- a/chip/mchp/flash.c
+++ b/chip/mchp/flash.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,14 +6,14 @@
 #include "common.h"
 #include "console.h"
 #include "flash.h"
+#include "hooks.h"
 #include "host_command.h"
 #include "shared_mem.h"
 #include "spi.h"
 #include "spi_flash.h"
 #include "system.h"
-#include "util.h"
-#include "hooks.h"
 #include "tfdp_chip.h"
+#include "util.h"
 
 #define PAGE_SIZE 256
 
@@ -35,7 +35,7 @@ struct flash_wp_state {
  * @param size          Number of bytes to write.
  * @param data          Destination buffer for data.
  */
-int flash_physical_read(int offset, int size, char *data)
+int crec_flash_physical_read(int offset, int size, char *data)
 {
 	trace13(0, FLASH, 0,
 		"flash_phys_read: offset=0x%08X size=0x%08X dataptr=0x%08X",
@@ -52,10 +52,10 @@ int flash_physical_read(int offset, int size, char *data)
  * @param size          Number of bytes to write.
  * @param data          Data to write to flash.  Must be 32-bit aligned.
  */
-int flash_physical_write(int offset, int size, const char *data)
+int crec_flash_physical_write(int offset, int size, const char *data)
 {
 	int ret = EC_SUCCESS;
-	int  i, write_size;
+	int i, write_size;
 
 	trace13(0, FLASH, 0,
 		"flash_phys_write: offset=0x%08X size=0x%08X dataptr=0x%08X",
@@ -70,8 +70,7 @@ int flash_physical_write(int offset, int size, const char *data)
 
 	for (i = 0; i < size; i += write_size) {
 		write_size = MIN((size - i), SPI_FLASH_MAX_WRITE_SIZE);
-		ret = spi_flash_write(offset + i,
-				      write_size,
+		ret = spi_flash_write(offset + i, write_size,
 				      (uint8_t *)data + i);
 		if (ret != EC_SUCCESS)
 			break;
@@ -87,15 +86,14 @@ int flash_physical_write(int offset, int size, const char *data)
  * @param offset        Flash offset to erase.
  * @param size          Number of bytes to erase.
  */
-int flash_physical_erase(int offset, int size)
+int crec_flash_physical_erase(int offset, int size)
 {
 	int ret;
 
 	if (entire_flash_locked)
 		return EC_ERROR_ACCESS_DENIED;
 
-	trace12(0, FLASH, 0,
-		"flash_phys_erase: offset=0x%08X size=0x%08X",
+	trace12(0, FLASH, 0, "flash_phys_erase: offset=0x%08X size=0x%08X",
 		offset, size);
 	ret = spi_flash_erase(offset, size);
 	return ret;
@@ -107,10 +105,10 @@ int flash_physical_erase(int offset, int size)
  * @param bank    Bank index to check.
  * @return        non-zero if bank is protected until reboot.
  */
-int flash_physical_get_protect(int bank)
+int crec_flash_physical_get_protect(int bank)
 {
 	return spi_flash_check_protect(bank * CONFIG_FLASH_BANK_SIZE,
-			CONFIG_FLASH_BANK_SIZE);
+				       CONFIG_FLASH_BANK_SIZE);
 }
 
 /**
@@ -121,7 +119,7 @@ int flash_physical_get_protect(int bank)
  * @param all      Protect all (=1) or just read-only
  * @return         non-zero if error.
  */
-int flash_physical_protect_now(int all)
+int crec_flash_physical_protect_now(int all)
 {
 	if (all)
 		entire_flash_locked = 1;
@@ -142,7 +140,7 @@ int flash_physical_protect_now(int all)
  *
  * Uses the EC_FLASH_PROTECT_* flags from ec_commands.h
  */
-uint32_t flash_physical_get_protect_flags(void)
+uint32_t crec_flash_physical_get_protect_flags(void)
 {
 	uint32_t flags = 0;
 
@@ -162,10 +160,9 @@ uint32_t flash_physical_get_protect_flags(void)
  *
  * @return   A combination of EC_FLASH_PROTECT_* flags from ec_commands.h
  */
-uint32_t flash_physical_get_valid_flags(void)
+uint32_t crec_flash_physical_get_valid_flags(void)
 {
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-	       EC_FLASH_PROTECT_RO_NOW |
+	return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW |
 	       EC_FLASH_PROTECT_ALL_NOW;
 }
 
@@ -175,15 +172,16 @@ uint32_t flash_physical_get_valid_flags(void)
  * @param    cur_flags The current flash protect flags.
  * @return   A combination of EC_FLASH_PROTECT_* flags from ec_commands.h
  */
-uint32_t flash_physical_get_writable_flags(uint32_t cur_flags)
+uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
 {
 	uint32_t ret = 0;
 	enum spi_flash_wp wp_status = SPI_WP_NONE;
 
 	wp_status = spi_flash_check_wp();
 
-	if (wp_status == SPI_WP_NONE || (wp_status == SPI_WP_HARDWARE &&
-	   !(cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED)))
+	if (wp_status == SPI_WP_NONE ||
+	    (wp_status == SPI_WP_HARDWARE &&
+	     !(cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED)))
 		ret = EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW;
 
 	if (!entire_flash_locked)
@@ -204,7 +202,7 @@ uint32_t flash_physical_get_writable_flags(uint32_t cur_flags)
  * @param range         The range to protect.
  * @return              EC_SUCCESS, or nonzero if error.
  */
-int flash_physical_protect_at_boot(uint32_t new_flags)
+int crec_flash_physical_protect_at_boot(uint32_t new_flags)
 {
 	int offset, size, ret;
 	enum spi_flash_wp flashwp = SPI_WP_NONE;
@@ -234,13 +232,13 @@ int flash_physical_protect_at_boot(uint32_t new_flags)
  *
  * Applies at-boot protection settings if necessary.
  */
-int flash_pre_init(void)
+int crec_flash_pre_init(void)
 {
-	flash_physical_restore_state();
+	crec_flash_physical_restore_state();
 	return EC_SUCCESS;
 }
 
-int flash_physical_restore_state(void)
+int crec_flash_physical_restore_state(void)
 {
 	uint32_t reset_flags = system_get_reset_flags();
 	int version, size;
@@ -253,7 +251,7 @@ int flash_physical_restore_state(void)
 	 */
 	if (reset_flags & EC_RESET_FLAG_SYSJUMP) {
 		prev = (const struct flash_wp_state *)system_get_jump_tag(
-				FLASH_SYSJUMP_TAG, &version, &size);
+			FLASH_SYSJUMP_TAG, &version, &size);
 		if (prev && version == FLASH_HOOK_VERSION &&
 		    size == sizeof(*prev))
 			entire_flash_locked = prev->entire_flash_locked;
diff --git a/chip/mchp/gpio.c b/chip/mchp/gpio.c
index 1de74dafcc..3ad9d7b6e4 100644
--- a/chip/mchp/gpio.c
+++ b/chip/mchp/gpio.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,18 +8,17 @@
 #include "common.h"
 #include "gpio.h"
 #include "hooks.h"
+#include "lpc_chip.h"
 #include "registers.h"
 #include "system.h"
 #include "task.h"
+#include "tfdp_chip.h"
 #include "timer.h"
 #include "util.h"
-#include "lpc_chip.h"
-#include "tfdp_chip.h"
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-
+#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args)
 
 struct gpio_int_mapping {
 	int8_t girq_id;
@@ -38,23 +37,73 @@ struct gpio_int_mapping {
  * 4		0200 - 0235	12
  * 5		0240 - 0276	26
  */
-static const struct gpio_int_mapping int_map[6] = {
-	{ 11, 0 }, { 10, 1 }, { 9, 2 },
-	{ 8, 3 }, { 12, 4 }, { 26, 5 }
+static const struct gpio_int_mapping int_map[] = { { 11, 0 }, { 10, 1 },
+						   { 9, 2 },  { 8, 3 },
+						   { 12, 4 }, { 26, 5 } };
+BUILD_ASSERT(ARRAY_SIZE(int_map) == MCHP_GPIO_MAX_PORT);
+
+/*
+ * These pins default to BGPO functionality. BGPO overrides GPIO Control
+ * register programming. If the pin is in the GPIO list the user wants to
+ * use the pin as GPIO and we must disable BGPIO functionality for this pin.
+ */
+struct bgpo_pin {
+	uint16_t pin;
+	uint8_t bgpo_pos;
 };
 
+static const struct bgpo_pin bgpo_list[] = {
+	{ 0101, 1 }, /* GPIO 0101 */
+	{ 0102, 2 }, /* GPIO 0102 */
+#if defined(CHIP_FAMILY_MEC152X)
+	{ 0253, 0 }, /* GPIO 0253 */
+#elif defined(CHIP_FAMILY_MEC170X)
+	{ 0172, 3 }, /* GPIO 0172 */
+#endif
+};
+
+static const uint32_t bgpo_map[] = {
+#if defined(CHIP_FAMILY_MEC152X)
+	0, 0, (BIT(1) | BIT(2)), 0, 0, BIT(11)
+#elif defined(CHIP_FAMILY_MEC170X)
+	0, 0, (BIT(1) | BIT(2)), BIT(26), 0, 0
+#else
+	0, 0, 0, 0, 0, 0
+#endif
+};
+BUILD_ASSERT(ARRAY_SIZE(bgpo_map) == MCHP_GPIO_MAX_PORT);
 
+/* Check for BGPO capable pins on this port and disable BGPO feature */
+static void disable_bgpo(uint32_t port, uint32_t mask)
+{
+	int i, n;
+	uint32_t gpnum;
+	uint32_t m = bgpo_map[port] & mask;
+
+	while (m) {
+		i = __builtin_ffs(m) - 1;
+		gpnum = (port * 32U) + i;
+		for (n = 0; n < ARRAY_SIZE(bgpo_list); n++)
+			if (gpnum == bgpo_list[n].pin)
+				MCHP_WKTIMER_BGPO_POWER &=
+					~BIT(bgpo_list[n].bgpo_pos);
+		m &= ~BIT(i);
+	}
+}
 
 /*
  * NOTE: GCC __builtin_ffs(val) returns (index + 1) of least significant
  * 1-bit of val or if val == 0 returns 0
  */
 void gpio_set_alternate_function(uint32_t port, uint32_t mask,
-				enum gpio_alternate_func func)
+				 enum gpio_alternate_func func)
 {
 	int i;
 	uint32_t val;
 
+	if (port >= MCHP_GPIO_MAX_PORT)
+		return;
+
 	while (mask) {
 		i = __builtin_ffs(mask) - 1;
 		val = MCHP_GPIO_CTL(port, i);
@@ -98,18 +147,21 @@ void gpio_set_level(enum gpio_signal signal, int value)
 
 /*
  * Add support for new #ifdef CONFIG_CMD_GPIO_POWER_DOWN.
- * If GPIO_POWER_DONW flag is set force GPIO Control to
+ * If GPIO_POWER_DOWN flag is set force GPIO Control to
  * GPIO input, interrupt detect disabled, power control field
  * in bits[3:2]=10b.
  * NOTE: if interrupt detect is enabled when pin is powered down
  * then a false edge may be detected.
- *
+ * NOTE 2: MEC152x family implements input pad disable (bit[15]=1).
  */
 void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
 {
 	int i;
 	uint32_t val;
 
+	if (port >= MCHP_GPIO_MAX_PORT)
+		return;
+
 	while (mask) {
 		i = GPIO_MASK_TO_NUM(mask);
 		mask &= ~BIT(i);
@@ -117,15 +169,18 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
 
 #ifdef CONFIG_GPIO_POWER_DOWN
 		if (flags & GPIO_POWER_DOWN) {
-			val = (MCHP_GPIO_CTRL_PWR_OFF +
-					MCHP_GPIO_INTDET_DISABLED);
+			val = (MCHP_GPIO_CTRL_PWR_OFF |
+			       MCHP_GPIO_INTDET_DISABLED |
+			       MCHP_GPIO_CTRL_DIS_INPUT_BIT);
+
 			MCHP_GPIO_CTL(port, i) = val;
 			continue;
 		}
 #endif
-		val &= ~(MCHP_GPIO_CTRL_PWR_MASK);
-		val |= MCHP_GPIO_CTRL_PWR_VTR;
+		val &= ~(MCHP_GPIO_CTRL_PWR_MASK |
+			 MCHP_GPIO_CTRL_DIS_INPUT_BIT);
 
+		val |= MCHP_GPIO_CTRL_PWR_VTR;
 		/*
 		 * Select open drain first, so that we don't
 		 * glitch the signal when changing the line to
@@ -190,12 +245,15 @@ void gpio_power_off_by_mask(uint32_t port, uint32_t mask)
 {
 	int i;
 
+	if (port >= MCHP_GPIO_MAX_PORT)
+		return;
+
 	while (mask) {
 		i = GPIO_MASK_TO_NUM(mask);
 		mask &= ~BIT(i);
-
-		MCHP_GPIO_CTL(port, i) = (MCHP_GPIO_CTRL_PWR_OFF +
-					MCHP_GPIO_INTDET_DISABLED);
+		MCHP_GPIO_CTL(port, i) =
+			(MCHP_GPIO_CTRL_PWR_OFF | MCHP_GPIO_INTDET_DISABLED |
+			 MCHP_GPIO_CTRL_DIS_INPUT_BIT);
 	}
 }
 
@@ -208,9 +266,9 @@ int gpio_power_off(enum gpio_signal signal)
 
 	i = GPIO_MASK_TO_NUM(gpio_list[signal].mask);
 	port = gpio_list[signal].port;
-
-	MCHP_GPIO_CTL(port, i) = (MCHP_GPIO_CTRL_PWR_OFF +
-			MCHP_GPIO_INTDET_DISABLED);
+	MCHP_GPIO_CTL(port, i) =
+		(MCHP_GPIO_CTRL_PWR_OFF | MCHP_GPIO_INTDET_DISABLED |
+		 MCHP_GPIO_CTRL_DIS_INPUT_BIT);
 
 	return EC_SUCCESS;
 }
@@ -253,7 +311,6 @@ int gpio_disable_interrupt(enum gpio_signal signal)
 	port = gpio_list[signal].port;
 	girq_id = int_map[port].girq_id;
 
-
 	MCHP_INT_DISABLE(girq_id) = BIT(i);
 
 	return EC_SUCCESS;
@@ -309,7 +366,6 @@ void gpio_pre_init(void)
 	int is_warm = system_is_reboot_warm();
 	const struct gpio_info *g = gpio_list;
 
-
 	for (i = 0; i < GPIO_COUNT; i++, g++) {
 		flags = g->flags;
 
@@ -323,11 +379,13 @@ void gpio_pre_init(void)
 		if (is_warm)
 			flags &= ~(GPIO_LOW | GPIO_HIGH);
 
+		disable_bgpo(g->port, g->mask);
+
 		gpio_set_flags_by_mask(g->port, g->mask, flags);
 
 		/* Use as GPIO, not alternate function */
 		gpio_set_alternate_function(g->port, g->mask,
-					GPIO_ALT_FUNC_NONE);
+					    GPIO_ALT_FUNC_NONE);
 	}
 }
 
@@ -343,14 +401,13 @@ void gpio_pre_init(void)
  *    assumption for the GPIO's that have been enabled.
  * 2. Clear NVIC pending to prevent ISR firing on false edge.
  */
-#define ENABLE_GPIO_GIRQ(x) \
-	do { \
-		MCHP_INT_SOURCE(x) = 0xfffffffful; \
-		task_clear_pending_irq(MCHP_IRQ_GIRQ ## x); \
-		task_enable_irq(MCHP_IRQ_GIRQ ## x); \
+#define ENABLE_GPIO_GIRQ(x)                               \
+	do {                                              \
+		MCHP_INT_SOURCE(x) = 0xfffffffful;        \
+		task_clear_pending_irq(MCHP_IRQ_GIRQ##x); \
+		task_enable_irq(MCHP_IRQ_GIRQ##x);        \
 	} while (0)
 
-
 static void gpio_init(void)
 {
 	ENABLE_GPIO_GIRQ(8);
@@ -365,7 +422,6 @@ DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
 /************************************************************************/
 /* Interrupt handlers */
 
-
 /**
  * Handler for each GIRQ interrupt. This reads and clears the interrupt
  * bits for the GIRQ interrupt, then finds and calls the corresponding
@@ -386,8 +442,8 @@ static void gpio_interrupt(int girq, int port)
 	MCHP_INT_SOURCE(girq) = sts;
 
 	trace12(0, GPIO, 0, "GPIO GIRQ %d result = 0x%08x", girq, sts);
-	trace12(0, GPIO, 0, "GPIO ParIn[%d]      = 0x%08x",
-		port, MCHP_GPIO_PARIN(port));
+	trace12(0, GPIO, 0, "GPIO ParIn[%d]      = 0x%08x", port,
+		MCHP_GPIO_PARIN(port));
 
 	for (i = 0; (i < GPIO_IH_COUNT) && sts; ++i, ++g) {
 		if (g->port != port)
@@ -397,9 +453,8 @@ static void gpio_interrupt(int girq, int port)
 		if (bit) {
 			bit--;
 			if (sts & BIT(bit)) {
-				trace12(0, GPIO, 0,
-					"Bit[%d]: handler @ 0x%08x", bit,
-					(uint32_t)gpio_irq_handlers[i]);
+				trace12(0, GPIO, 0, "Bit[%d]: handler @ 0x%08x",
+					bit, (uint32_t)gpio_irq_handlers[i]);
 				gpio_irq_handlers[i](i);
 			}
 			sts &= ~BIT(bit);
@@ -407,10 +462,10 @@ static void gpio_interrupt(int girq, int port)
 	}
 }
 
-#define GPIO_IRQ_FUNC(irqfunc, girq, port)\
-	void irqfunc(void) \
-	{ \
-		gpio_interrupt(girq, port);\
+#define GPIO_IRQ_FUNC(irqfunc, girq, port)  \
+	static void irqfunc(void)           \
+	{                                   \
+		gpio_interrupt(girq, port); \
 	}
 
 GPIO_IRQ_FUNC(__girq_8_interrupt, 8, 3);
@@ -432,4 +487,3 @@ DECLARE_IRQ(MCHP_IRQ_GIRQ10, __girq_10_interrupt, 1);
 DECLARE_IRQ(MCHP_IRQ_GIRQ11, __girq_11_interrupt, 1);
 DECLARE_IRQ(MCHP_IRQ_GIRQ12, __girq_12_interrupt, 1);
 DECLARE_IRQ(MCHP_IRQ_GIRQ26, __girq_26_interrupt, 1);
-
diff --git a/chip/mchp/gpio_chip.h b/chip/mchp/gpio_chip.h
index 7baaa76fa2..ec0f3d2278 100644
--- a/chip/mchp/gpio_chip.h
+++ b/chip/mchp/gpio_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -13,11 +13,11 @@
 #ifndef _GPIO_CHIP_H
 #define _GPIO_CHIP_H
 
-#include <stdint.h>
-#include <stddef.h>
-
 #include "gpio.h"
 
+#include <stddef.h>
+#include <stdint.h>
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -35,4 +35,3 @@ void gpio_power_off_by_mask(uint32_t port, uint32_t mask);
 #endif /* #ifndef _GPIO_CHIP_H */
 /**   @}
  */
-
diff --git a/chip/mchp/gpio_cmds.c b/chip/mchp/gpio_cmds.c
index cbf5f4c462..a53f8cca2a 100644
--- a/chip/mchp/gpio_cmds.c
+++ b/chip/mchp/gpio_cmds.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,20 +8,18 @@
 #include "common.h"
 #include "console.h"
 #include "gpio.h"
+#include "gpio_chip.h"
 #include "hooks.h"
 #include "registers.h"
 #include "system.h"
-#include "util.h"
-#include "gpio_chip.h"
 #include "tfdp_chip.h"
+#include "util.h"
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args)
 
-
-
-static int cmd_gp_get_config(int argc, char **argv)
+static int cmd_gp_get_config(int argc, const char **argv)
 {
 	char *e;
 	int i;
@@ -43,7 +41,7 @@ static int cmd_gp_get_config(int argc, char **argv)
 	} else { /* Otherwise print them all */
 		for (i = 0; i < GPIO_COUNT; i++) {
 			if (!gpio_is_implemented(i))
-				continue;  /* Skip unsupported signals */
+				continue; /* Skip unsupported signals */
 
 			gctrl = MCHP_GPIO_CTRL(i);
 
@@ -56,11 +54,10 @@ static int cmd_gp_get_config(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(gpgetcfg, cmd_gp_get_config,
-			"[number]",
+DECLARE_CONSOLE_COMMAND(gpgetcfg, cmd_gp_get_config, "[number]",
 			"Read GPIO config");
 
-static int cmd_gp_set_config(int argc, char **argv)
+static int cmd_gp_set_config(int argc, const char **argv)
 {
 	char *e;
 	int i;
@@ -91,7 +88,5 @@ static int cmd_gp_set_config(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(gpsetcfg, cmd_gp_set_config,
-			"gp_num val",
+DECLARE_CONSOLE_COMMAND(gpsetcfg, cmd_gp_set_config, "gp_num val",
 			"Set GPIO config");
-
diff --git a/chip/mchp/gpspi.c b/chip/mchp/gpspi.c
index 4edf57ee11..a7f7b388c4 100644
--- a/chip/mchp/gpspi.c
+++ b/chip/mchp/gpspi.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,18 +9,18 @@
 #include "console.h"
 #include "dma.h"
 #include "gpio.h"
+#include "gpspi_chip.h"
+#include "hooks.h"
 #include "registers.h"
 #include "spi.h"
-#include "timer.h"
-#include "util.h"
-#include "hooks.h"
-#include "task.h"
 #include "spi_chip.h"
-#include "gpspi_chip.h"
+#include "task.h"
 #include "tfdp_chip.h"
+#include "timer.h"
+#include "util.h"
 
 #define CPUTS(outstr) cputs(CC_SPI, outstr)
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SPI, format, ##args)
 
 #define SPI_BYTE_TRANSFER_TIMEOUT_US (3 * MSEC)
 /* One byte at 12 MHz full duplex = 0.67 us */
@@ -91,8 +91,8 @@ static int gpspi_tx(const int ctrl, const uint8_t *txdata, int txlen)
 #endif
 
 int gpspi_transaction_async(const struct spi_device_t *spi_device,
-				const uint8_t *txdata, int txlen,
-				uint8_t *rxdata, int rxlen)
+			    const uint8_t *txdata, int txlen, uint8_t *rxdata,
+			    int rxlen)
 {
 	int hw_port, ctrl;
 	int ret = EC_SUCCESS;
@@ -212,7 +212,7 @@ int gpspi_transaction_wait(const struct spi_device_t *spi_device)
 }
 
 /**
- * Enable GPSPI controller and MODULE_SPI_MASTER pins
+ * Enable GPSPI controller and MODULE_SPI_CONTROLLER pins
  *
  * @param hw_port b[7:4]=1 b[3:0]=0(GPSPI0), 1(GPSPI1)
  * @param enable
@@ -227,12 +227,11 @@ int gpspi_enable(int hw_port, int enable)
 	if ((hw_port != GPSPI0_PORT) && (hw_port != GPSPI1_PORT))
 		return EC_ERROR_INVAL;
 
-	gpio_config_module(MODULE_SPI_MASTER, (enable > 0));
+	gpio_config_module(MODULE_SPI_CONTROLLER, (enable > 0));
 
 	ctrl = (uint32_t)hw_port & 0x0f;
 
 	if (enable) {
-
 		if (ctrl)
 			MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_GPSPI1);
 		else
@@ -264,4 +263,3 @@ int gpspi_enable(int hw_port, int enable)
 
 	return EC_SUCCESS;
 }
-
diff --git a/chip/mchp/gpspi_chip.h b/chip/mchp/gpspi_chip.h
index 529a727e36..16c3208410 100644
--- a/chip/mchp/gpspi_chip.h
+++ b/chip/mchp/gpspi_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -13,8 +13,8 @@
 #ifndef _GPSPI_CHIP_H
 #define _GPSPI_CHIP_H
 
-#include <stdint.h>
 #include <stddef.h>
+#include <stdint.h>
 
 /* struct spi_device_t */
 #include "spi.h"
@@ -24,12 +24,11 @@ int gpspi_transaction_flush(const struct spi_device_t *spi_device);
 int gpspi_transaction_wait(const struct spi_device_t *spi_device);
 
 int gpspi_transaction_async(const struct spi_device_t *spi_device,
-				const uint8_t *txdata, int txlen,
-				uint8_t *rxdata, int rxlen);
+			    const uint8_t *txdata, int txlen, uint8_t *rxdata,
+			    int rxlen);
 
 int gpspi_enable(int port, int enable);
 
 #endif /* #ifndef _GPSPI_CHIP_H */
 /**   @}
  */
-
diff --git a/chip/mchp/hwtimer.c b/chip/mchp/hwtimer.c
index e84f278f4a..c72140b18f 100644
--- a/chip/mchp/hwtimer.c
+++ b/chip/mchp/hwtimer.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,13 +11,12 @@
 #include "hwtimer.h"
 #include "registers.h"
 #include "task.h"
-#include "timer.h"
 #include "tfdp_chip.h"
+#include "timer.h"
 
 void __hw_clock_event_set(uint32_t deadline)
 {
-	MCHP_TMR32_CNT(1) = MCHP_TMR32_CNT(0) -
-			       (0xffffffff - deadline);
+	MCHP_TMR32_CNT(1) = MCHP_TMR32_CNT(0) - (0xffffffff - deadline);
 	MCHP_TMR32_CTL(1) |= BIT(5);
 }
 
@@ -49,16 +48,21 @@ void __hw_clock_source_set(uint32_t ts)
 static void __hw_clock_source_irq(int timer_id)
 {
 	MCHP_TMR32_STS(timer_id & 0x01) |= 1;
-	MCHP_INT_SOURCE(MCHP_TMR32_GIRQ) =
-			MCHP_TMR32_GIRQ_BIT(timer_id & 0x01);
+	MCHP_INT_SOURCE(MCHP_TMR32_GIRQ) = MCHP_TMR32_GIRQ_BIT(timer_id & 0x01);
 
 	/* If IRQ is from timer 0, 32-bit timer overflowed */
 	process_timers(timer_id == 0);
 }
 
-void __hw_clock_source_irq_0(void) { __hw_clock_source_irq(0); }
+static void __hw_clock_source_irq_0(void)
+{
+	__hw_clock_source_irq(0);
+}
 DECLARE_IRQ(MCHP_IRQ_TIMER32_0, __hw_clock_source_irq_0, 1);
-void __hw_clock_source_irq_1(void) { __hw_clock_source_irq(1); }
+static void __hw_clock_source_irq_1(void)
+{
+	__hw_clock_source_irq(1);
+}
 DECLARE_IRQ(MCHP_IRQ_TIMER32_1, __hw_clock_source_irq_1, 1);
 
 static void configure_timer(int timer_id)
@@ -88,7 +92,7 @@ static void configure_timer(int timer_id)
 int __hw_clock_source_init(uint32_t start_t)
 {
 	MCHP_PCR_SLP_DIS_DEV_MASK(3, MCHP_PCR_SLP_EN3_BTMR32_0 +
-			MCHP_PCR_SLP_EN3_BTMR32_1);
+					     MCHP_PCR_SLP_EN3_BTMR32_1);
 
 	/*
 	 * The timer can only fire interrupt when its value reaches zero.
@@ -111,8 +115,8 @@ int __hw_clock_source_init(uint32_t start_t)
 	/* Enable interrupt */
 	task_enable_irq(MCHP_IRQ_TIMER32_0);
 	task_enable_irq(MCHP_IRQ_TIMER32_1);
-	MCHP_INT_ENABLE(MCHP_TMR32_GIRQ) = MCHP_TMR32_GIRQ_BIT(0) +
-			MCHP_TMR32_GIRQ_BIT(1);
+	MCHP_INT_ENABLE(MCHP_TMR32_GIRQ) =
+		MCHP_TMR32_GIRQ_BIT(0) + MCHP_TMR32_GIRQ_BIT(1);
 	/*
 	 * Not needed when using direct mode interrupts
 	 * MCHP_INT_BLK_EN |= BIT(MCHP_TMR32_GIRQ);
diff --git a/chip/mchp/i2c.c b/chip/mchp/i2c.c
index da7136a6b2..2b21d17dc4 100644
--- a/chip/mchp/i2c.c
+++ b/chip/mchp/i2c.c
@@ -1,50 +1,55 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-/* I2C port module for MCHP MEC
- * TODO handle chip variants
- */
+/* I2C port module for MCHP MEC */
 
 #include "common.h"
 #include "console.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "i2c.h"
+#include "i2c_chip.h"
 #include "registers.h"
 #include "task.h"
+#include "tfdp_chip.h"
 #include "timer.h"
 #include "util.h"
-#include "tfdp_chip.h"
 
 #define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
 
 /*
  * MCHP I2C BAUD clock source is 16 MHz.
  */
-#define I2C_CLOCK 16000000 /* 16 MHz */
+#define I2C_CLOCK 16000000UL
+#define MCHP_I2C_SUPPORTED_BUS_CLOCKS 6
 
 /* SMBus Timing values for 1MHz Speed */
-#define SPEED_1MHZ_BUS_CLOCK		0x0509
-#define SPEED_1MHZ_DATA_TIMING		0x06060601
-#define SPEED_1MHZ_DATA_TIMING_2	0x06
-#define SPEED_1MHZ_IDLE_SCALING		0x01000050
-#define SPEED_1MHZ_TIMEOUT_SCALING	0x149CC2C7
+#define SPEED_1MHZ_BUS_CLOCK 0x0509ul
+#define SPEED_1MHZ_DATA_TIMING 0x06060601ul
+#define SPEED_1MHZ_DATA_TIMING_2 0x06ul
+#define SPEED_1MHZ_IDLE_SCALING 0x01000050ul
+#define SPEED_1MHZ_TIMEOUT_SCALING 0x149CC2C7ul
 /* SMBus Timing values for 400kHz speed */
-#define SPEED_400KHZ_BUS_CLOCK		0x0F17
-#define SPEED_400KHZ_DATA_TIMING	0x040A0F01
-#define SPEED_400KHZ_DATA_TIMING_2	0x0A
-#define SPEED_400KHZ_IDLE_SCALING	0x01000050
-#define SPEED_400KHZ_TIMEOUT_SCALING	0x149CC2C7
+#define SPEED_400KHZ_BUS_CLOCK 0x0F17ul
+#define SPEED_400KHZ_DATA_TIMING 0x040A0F01ul
+#define SPEED_400KHZ_DATA_TIMING_2 0x0Aul
+#define SPEED_400KHZ_IDLE_SCALING 0x01000050ul
+#define SPEED_400KHZ_TIMEOUT_SCALING 0x149CC2C7ul
 /* SMBus Timing values for 100kHz speed */
-#define SPEED_100KHZ_BUS_CLOCK		0x4F4Ful
-#define SPEED_100KHZ_DATA_TIMING	0x0C4D4306ul
-#define SPEED_100KHZ_DATA_TIMING_2	0x4Dul
-#define SPEED_100KHZ_IDLE_SCALING	0x01FC01EDul
-#define SPEED_100KHZ_TIMEOUT_SCALING	0x4B9CC2C7ul
+#define SPEED_100KHZ_BUS_CLOCK 0x4F4Ful
+#define SPEED_100KHZ_DATA_TIMING 0x0C4D4306ul
+#define SPEED_100KHZ_DATA_TIMING_2 0x4Dul
+#define SPEED_100KHZ_IDLE_SCALING 0x01FC01EDul
+#define SPEED_100KHZ_TIMEOUT_SCALING 0x4B9CC2C7ul
+/* Bus clock dividers for 333, 80, and 40 kHz */
+#define SPEED_333KHZ_BUS_CLOCK 0x0F1Ful
+#define SPEED_80KHZ_BUS_CLOCK 0x6363ul
+#define SPEED_40KHZ_BUS_CLOCK 0xC7C7ul
+
 /* Status */
 #define STS_NBB BIT(0) /* Bus busy */
 #define STS_LAB BIT(1) /* Arbitration lost */
@@ -59,37 +64,37 @@
 #define CTRL_ESO BIT(6) /* Enable serial output */
 #define CTRL_PIN BIT(7) /* Pending interrupt not */
 /* Completion */
-#define COMP_DTEN	BIT(2) /* enable device timeouts */
-#define COMP_MCEN	BIT(3) /* enable master cumulative timeouts */
-#define COMP_SCEN	BIT(4) /* enable slave cumulative timeouts */
-#define COMP_BIDEN	BIT(5) /* enable Bus idle timeouts */
-#define COMP_IDLE	BIT(29)  /* i2c bus is idle */
+#define COMP_DTEN BIT(2) /* enable device timeouts */
+#define COMP_MCEN BIT(3) /* enable ctrl. cumulative timeouts */
+#define COMP_SCEN BIT(4) /* enable periph. cumulative timeouts */
+#define COMP_BIDEN BIT(5) /* enable Bus idle timeouts */
+#define COMP_IDLE BIT(29) /* i2c bus is idle */
 #define COMP_RW_BITS_MASK 0x3C /* R/W bits mask */
 /* Configuration */
-#define CFG_PORT_MASK	(0x0F)	/* port selection field */
-#define CFG_TCEN	BIT(4) /* Enable HW bus timeouts */
-#define CFG_FEN		BIT(8) /* enable input filtering */
-#define CFG_RESET	BIT(9) /* reset controller */
-#define CFG_ENABLE	BIT(10) /* enable controller */
-#define CFG_GC_DIS	BIT(14) /* disable general call address */
-#define CFG_ENIDI	BIT(29) /* Enable I2C idle interrupt */
-/* Enable network layer master done interrupt */
-#define CFG_ENMI	BIT(30)
-/* Enable network layer slave done interrupt */
-#define CFG_ENSI	BIT(31)
-/* Master Command */
-#define MCMD_MRUN		BIT(0)
-#define MCMD_MPROCEED		BIT(1)
-#define MCMD_START0		BIT(8)
-#define MCMD_STARTN		BIT(9)
-#define MCMD_STOP		BIT(10)
-#define MCMD_READM		BIT(12)
-#define MCMD_WCNT_BITPOS	(16)
-#define MCMD_WCNT_MASK0		(0xFF)
-#define MCMD_WCNT_MASK		(0xFF << 16)
-#define MCMD_RCNT_BITPOS	(24)
-#define MCMD_RCNT_MASK0		(0xFF)
-#define MCMD_RCNT_MASK		(0xFF << 24)
+#define CFG_PORT_MASK (0x0F) /* port selection field */
+#define CFG_TCEN BIT(4) /* Enable HW bus timeouts */
+#define CFG_FEN BIT(8) /* enable input filtering */
+#define CFG_RESET BIT(9) /* reset controller */
+#define CFG_ENABLE BIT(10) /* enable controller */
+#define CFG_GC_DIS BIT(14) /* disable general call address */
+#define CFG_ENIDI BIT(29) /* Enable I2C idle interrupt */
+/* Enable network layer controller done interrupt */
+#define CFG_ENMI BIT(30)
+/* Enable network layer peripheral done interrupt */
+#define CFG_ENSI BIT(31)
+/* Controller Command */
+#define MCMD_MRUN BIT(0)
+#define MCMD_MPROCEED BIT(1)
+#define MCMD_START0 BIT(8)
+#define MCMD_STARTN BIT(9)
+#define MCMD_STOP BIT(10)
+#define MCMD_READM BIT(12)
+#define MCMD_WCNT_BITPOS (16)
+#define MCMD_WCNT_MASK0 (0xFF)
+#define MCMD_WCNT_MASK (0xFF << 16)
+#define MCMD_RCNT_BITPOS (24)
+#define MCMD_RCNT_MASK0 (0xFF)
+#define MCMD_RCNT_MASK (0xFF << 24)
 
 /* Maximum transfer of a SMBUS block transfer */
 #define SMBUS_MAX_BLOCK_SIZE 32
@@ -132,7 +137,7 @@ static struct {
 	uint32_t i2c_complete; /* ISR write */
 	uint32_t flags;
 	uint8_t port;
-	uint8_t slv_addr_8bit;
+	uint8_t periph_addr_8bit;
 	uint8_t ctrl;
 	uint8_t hwsts;
 	uint8_t hwsts2;
@@ -141,18 +146,62 @@ static struct {
 	uint8_t lines;
 } cdata[I2C_CONTROLLER_COUNT];
 
-static const uint16_t i2c_controller_pcr[MCHP_I2C_CTRL_MAX] = {
-	MCHP_PCR_I2C0,
-	MCHP_PCR_I2C1,
-	MCHP_PCR_I2C2,
-	MCHP_PCR_I2C3
+static const uint16_t i2c_ctrl_nvic_id[] = { MCHP_IRQ_I2C_0, MCHP_IRQ_I2C_1,
+					     MCHP_IRQ_I2C_2, MCHP_IRQ_I2C_3,
+#if defined(CHIP_FAMILY_MEC172X)
+					     MCHP_IRQ_I2C_4
+#elif defined(CHIP_FAMILY_MEC152X)
+					     MCHP_IRQ_I2C_4, MCHP_IRQ_I2C_5,
+					     MCHP_IRQ_I2C_6, MCHP_IRQ_I2C_7
+#endif
 };
+BUILD_ASSERT(ARRAY_SIZE(i2c_ctrl_nvic_id) == MCHP_I2C_CTRL_MAX);
+
+static const uint16_t i2c_controller_pcr[] = { MCHP_PCR_I2C0, MCHP_PCR_I2C1,
+					       MCHP_PCR_I2C2, MCHP_PCR_I2C3,
+#if defined(CHIP_FAMILY_MEC172X)
+					       MCHP_PCR_I2C4
+#elif defined(CHIP_FAMILY_MEC152X)
+	MCHP_PCR_I2C4, MCHP_PCR_I2C5, MCHP_PCR_I2C6, MCHP_PCR_I2C7,
+#endif
+};
+BUILD_ASSERT(ARRAY_SIZE(i2c_controller_pcr) == MCHP_I2C_CTRL_MAX);
+
+static uintptr_t i2c_ctrl_base_addr[] = { MCHP_I2C0_BASE, MCHP_I2C1_BASE,
+					  MCHP_I2C2_BASE, MCHP_I2C3_BASE,
+#if defined(CHIP_FAMILY_MEC172X)
+					  MCHP_I2C4_BASE
+#elif defined(CHIP_FAMILY_MEC152X)
+					  MCHP_I2C4_BASE,
+					  /* NOTE: 5-7 do not implement network
+					     layer hardware */
+					  MCHP_I2C5_BASE, MCHP_I2C6_BASE,
+					  MCHP_I2C7_BASE
+#endif
+};
+BUILD_ASSERT(ARRAY_SIZE(i2c_ctrl_base_addr) == MCHP_I2C_CTRL_MAX);
 
-static int chip_i2c_is_controller_valid(int controller)
+static bool chip_i2c_is_controller_valid(int controller)
 {
 	if ((controller < 0) || (controller >= MCHP_I2C_CTRL_MAX))
+		return false;
+	return true;
+}
+
+static uintptr_t chip_i2c_ctrl_base(int controller)
+{
+	if (!chip_i2c_is_controller_valid(controller))
 		return 0;
-	return 1;
+
+	return i2c_ctrl_base_addr[controller];
+}
+
+static uint32_t chip_i2c_ctrl_nvic_id(int controller)
+{
+	if (!chip_i2c_is_controller_valid(controller))
+		return 0;
+
+	return (uint32_t)i2c_ctrl_nvic_id[controller];
 }
 
 static void i2c_ctrl_slp_en(int controller, int sleep_en)
@@ -184,39 +233,38 @@ struct i2c_bus_clk {
 };
 
 const struct i2c_bus_clk i2c_freq_tbl[] = {
-	{ 40, 0xC7C7 },
-	{ 80, 0x6363 },
-	{ 100, 0x4F4F },
-	{ 333, 0x0F1F },
-	{ 400, 0x0F17 },
-	{ 1000, 0x0509 },
+	{ 40, SPEED_40KHZ_BUS_CLOCK },	 { 80, SPEED_80KHZ_BUS_CLOCK },
+	{ 100, SPEED_100KHZ_BUS_CLOCK }, { 333, SPEED_333KHZ_BUS_CLOCK },
+	{ 400, SPEED_400KHZ_BUS_CLOCK }, { 1000, SPEED_1MHZ_BUS_CLOCK },
 };
+BUILD_ASSERT(ARRAY_SIZE(i2c_freq_tbl) == MCHP_I2C_SUPPORTED_BUS_CLOCKS);
+
+/* I2C controller assignment to a port */
+static int i2c_p2c[MCHP_I2C_PORT_COUNT];
 
 static int get_closest(int lesser, int greater, int target)
 {
 	if (target - i2c_freq_tbl[lesser].freq_khz >=
-			i2c_freq_tbl[greater].freq_khz - target)
+	    i2c_freq_tbl[greater].freq_khz - target)
 		return greater;
 	else
 		return lesser;
 }
 
 /*
- * Return index in i2c_freq_tbl of supported frequeny
+ * Return index in i2c_freq_tbl of supported frequencies
  * closest to requested frequency.
  */
 static const struct i2c_bus_clk *get_supported_speed_idx(int req_kbps)
 {
 	int i, limit, m, imax;
 
-	ASSERT(ARRAY_SIZE(i2c_freq_tbl) != 0);
-
 	if (req_kbps <= i2c_freq_tbl[0].freq_khz)
 		return &i2c_freq_tbl[0];
 
 	imax = ARRAY_SIZE(i2c_freq_tbl);
-	if (req_kbps >= i2c_freq_tbl[imax-1].freq_khz)
-		return &i2c_freq_tbl[imax-1];
+	if (req_kbps >= i2c_freq_tbl[imax - 1].freq_khz)
+		return &i2c_freq_tbl[imax - 1];
 
 	/* we only get here if ARRAY_SIZE(...) > 1
 	 * and req_kbps is in range.
@@ -229,15 +277,15 @@ static const struct i2c_bus_clk *get_supported_speed_idx(int req_kbps)
 			break;
 
 		if (req_kbps < i2c_freq_tbl[m].freq_khz) {
-			if (m > 0 && req_kbps > i2c_freq_tbl[m-1].freq_khz) {
-				m = get_closest(m-1, m, req_kbps);
+			if (m > 0 && req_kbps > i2c_freq_tbl[m - 1].freq_khz) {
+				m = get_closest(m - 1, m, req_kbps);
 				break;
 			}
 			limit = m;
 		} else {
-			if (m < imax-1 &&
-				req_kbps < i2c_freq_tbl[m+1].freq_khz) {
-				m = get_closest(m, m+1, req_kbps);
+			if (m < imax - 1 &&
+			    req_kbps < i2c_freq_tbl[m + 1].freq_khz) {
+				m = get_closest(m, m + 1, req_kbps);
 				break;
 			}
 			i = m + 1;
@@ -258,25 +306,28 @@ static const struct i2c_bus_clk *get_supported_speed_idx(int req_kbps)
 static void configure_controller_speed(int controller, int kbps)
 {
 	const struct i2c_bus_clk *p;
+	uintptr_t raddr;
+
+	raddr = chip_i2c_ctrl_base(controller);
 
 	p = get_supported_speed_idx(kbps);
-	MCHP_I2C_BUS_CLK(controller) = p->bus_clk;
+	MCHP_I2C_BUS_CLK(raddr) = p->bus_clk;
 
 	if (p->freq_khz > 400) { /* Fast mode plus */
-		MCHP_I2C_DATA_TIM(controller) = SPEED_1MHZ_DATA_TIMING;
-		MCHP_I2C_DATA_TIM_2(controller) = SPEED_1MHZ_DATA_TIMING_2;
-		MCHP_I2C_IDLE_SCALE(controller) = SPEED_1MHZ_IDLE_SCALING;
-		MCHP_I2C_TOUT_SCALE(controller) = SPEED_1MHZ_TIMEOUT_SCALING;
+		MCHP_I2C_DATA_TIM(raddr) = SPEED_1MHZ_DATA_TIMING;
+		MCHP_I2C_DATA_TIM_2(raddr) = SPEED_1MHZ_DATA_TIMING_2;
+		MCHP_I2C_IDLE_SCALE(raddr) = SPEED_1MHZ_IDLE_SCALING;
+		MCHP_I2C_TOUT_SCALE(raddr) = SPEED_1MHZ_TIMEOUT_SCALING;
 	} else if (p->freq_khz > 100) { /* Fast mode */
-		MCHP_I2C_DATA_TIM(controller) = SPEED_400KHZ_DATA_TIMING;
-		MCHP_I2C_DATA_TIM_2(controller) = SPEED_400KHZ_DATA_TIMING_2;
-		MCHP_I2C_IDLE_SCALE(controller) = SPEED_400KHZ_IDLE_SCALING;
-		MCHP_I2C_TOUT_SCALE(controller) = SPEED_400KHZ_TIMEOUT_SCALING;
+		MCHP_I2C_DATA_TIM(raddr) = SPEED_400KHZ_DATA_TIMING;
+		MCHP_I2C_DATA_TIM_2(raddr) = SPEED_400KHZ_DATA_TIMING_2;
+		MCHP_I2C_IDLE_SCALE(raddr) = SPEED_400KHZ_IDLE_SCALING;
+		MCHP_I2C_TOUT_SCALE(raddr) = SPEED_400KHZ_TIMEOUT_SCALING;
 	} else { /* Standard mode */
-		MCHP_I2C_DATA_TIM(controller) = SPEED_100KHZ_DATA_TIMING;
-		MCHP_I2C_DATA_TIM_2(controller) = SPEED_100KHZ_DATA_TIMING_2;
-		MCHP_I2C_IDLE_SCALE(controller) = SPEED_100KHZ_IDLE_SCALING;
-		MCHP_I2C_TOUT_SCALE(controller) = SPEED_100KHZ_TIMEOUT_SCALING;
+		MCHP_I2C_DATA_TIM(raddr) = SPEED_100KHZ_DATA_TIMING;
+		MCHP_I2C_DATA_TIM_2(raddr) = SPEED_100KHZ_DATA_TIMING_2;
+		MCHP_I2C_IDLE_SCALE(raddr) = SPEED_100KHZ_IDLE_SCALING;
+		MCHP_I2C_TOUT_SCALE(raddr) = SPEED_100KHZ_TIMEOUT_SCALING;
 	}
 }
 
@@ -286,70 +337,79 @@ static void configure_controller_speed(int controller, int kbps)
  */
 static void enable_controller_irq(int controller)
 {
-	MCHP_INT_ENABLE(MCHP_I2C_GIRQ) =
-			MCHP_I2C_GIRQ_BIT(controller);
-	task_enable_irq(MCHP_IRQ_I2C_0 + controller);
+	uint32_t nvic_id = chip_i2c_ctrl_nvic_id(controller);
+
+	MCHP_INT_ENABLE(MCHP_I2C_GIRQ) = MCHP_I2C_GIRQ_BIT(controller);
+	task_enable_irq(nvic_id);
 }
 
 static void disable_controller_irq(int controller)
 {
-	MCHP_INT_DISABLE(MCHP_I2C_GIRQ) =
-			MCHP_I2C_GIRQ_BIT(controller);
+	uint32_t nvic_id = chip_i2c_ctrl_nvic_id(controller);
+
+	MCHP_INT_DISABLE(MCHP_I2C_GIRQ) = MCHP_I2C_GIRQ_BIT(controller);
 	/* read back into read-only reg. to insure disable takes effect */
 	MCHP_INT_BLK_IRQ = MCHP_INT_DISABLE(MCHP_I2C_GIRQ);
-	task_disable_irq(MCHP_IRQ_I2C_0 + controller);
-	task_clear_pending_irq(MCHP_IRQ_I2C_0 + controller);
+	task_disable_irq(nvic_id);
+	task_clear_pending_irq(nvic_id);
 }
 
 /*
  * Do NOT enable controller's IDLE interrupt in the configuration
- * register. IDLE is meant for mult-master and controller as slave.
+ * register. IDLE is meant for multi-controller and controller acting
+ * as a peripheral.
  */
 static void configure_controller(int controller, int port, int kbps)
 {
-	if (!chip_i2c_is_controller_valid(controller))
+	uintptr_t raddr = chip_i2c_ctrl_base(controller);
+
+	if (raddr == 0)
 		return;
 
 	disable_controller_irq(controller);
-	MCHP_INT_SOURCE(MCHP_I2C_GIRQ) =
-			MCHP_I2C_GIRQ_BIT(controller);
+	MCHP_INT_SOURCE(MCHP_I2C_GIRQ) = MCHP_I2C_GIRQ_BIT(controller);
 
 	/* set to default except for port select field b[3:0] */
-	MCHP_I2C_CONFIG(controller) = (uint32_t)(port & 0xf);
-	MCHP_I2C_CTRL(controller) = CTRL_PIN;
+	MCHP_I2C_CONFIG(raddr) = (uint32_t)(port & 0xf);
+	MCHP_I2C_CTRL(raddr) = CTRL_PIN;
 
-	/* Set both controller slave addresses to 0 the
+	/* Set both controller peripheral addresses to 0 the
 	 * general call address. We disable general call
 	 * below.
 	 */
-	MCHP_I2C_OWN_ADDR(controller) = 0;
+	MCHP_I2C_OWN_ADDR(raddr) = 0;
 
 	configure_controller_speed(controller, kbps);
 
 	/* Controller timings done, clear RO status, enable
 	 * output, and ACK generation.
 	 */
-	MCHP_I2C_CTRL(controller) = CTRL_PIN | CTRL_ESO | CTRL_ACK;
+	MCHP_I2C_CTRL(raddr) = CTRL_PIN | CTRL_ESO | CTRL_ACK;
 
 	/* filter enable, disable General Call */
-	MCHP_I2C_CONFIG(controller) |= CFG_FEN + CFG_GC_DIS;
+	MCHP_I2C_CONFIG(raddr) |= CFG_FEN + CFG_GC_DIS;
 	/* enable controller */
-	MCHP_I2C_CONFIG(controller) |= CFG_ENABLE;
+	MCHP_I2C_CONFIG(raddr) |= CFG_ENABLE;
 }
 
 static void reset_controller(int controller)
 {
 	int i;
+	uintptr_t raddr;
+
+	raddr = chip_i2c_ctrl_base(controller);
+	if (raddr == 0)
+		return;
 
 	/* Reset asserted for at least one AHB clock */
-	MCHP_I2C_CONFIG(controller) |= BIT(9);
+	MCHP_I2C_CONFIG(raddr) |= BIT(9);
 	MCHP_EC_ID_RO = 0;
-	MCHP_I2C_CONFIG(controller) &= ~BIT(9);
+	MCHP_I2C_CONFIG(raddr) &= ~BIT(9);
 
 	for (i = 0; i < i2c_ports_used; ++i)
 		if (controller == i2c_port_to_controller(i2c_ports[i].port)) {
 			configure_controller(controller, i2c_ports[i].port,
-						i2c_ports[i].kbps);
+					     i2c_ports[i].kbps);
 			cdata[controller].transaction_state =
 				I2C_TRANSACTION_STOPPED;
 			break;
@@ -383,18 +443,19 @@ static int wait_for_interrupt(int controller, int timeout)
 
 static int wait_idle(int controller)
 {
-	uint8_t sts = MCHP_I2C_STATUS(controller);
+	uintptr_t raddr = chip_i2c_ctrl_base(controller);
 	uint64_t block_timeout = get_time().val + I2C_WAIT_BLOCKING_TIMEOUT_US;
 	uint64_t task_timeout = block_timeout + cdata[controller].timeout_us;
 	int rv = 0;
+	uint8_t sts = MCHP_I2C_STATUS(raddr);
 
 	while (!(sts & STS_NBB)) {
 		if (rv)
 			return rv;
 		if (get_time().val > block_timeout)
 			rv = wait_for_interrupt(controller,
-					task_timeout - get_time().val);
-		sts = MCHP_I2C_STATUS(controller);
+						task_timeout - get_time().val);
+		sts = MCHP_I2C_STATUS(raddr);
 	}
 
 	if (sts & (STS_BER | STS_LAB))
@@ -406,39 +467,41 @@ static int wait_idle(int controller)
  * Return EC_SUCCESS on ACK of byte else EC_ERROR_UNKNOWN.
  * Record I2C.Status in cdata[controller] structure.
  * Byte transmit finished with no I2C bus error or lost arbitration.
- *	PIN -> 0. LRB bit contains slave ACK/NACK bit.
- *	Slave ACK:  I2C.Status == 0x00
- *	Slave NACK: I2C.Status == 0x08
+ *	PIN -> 0. LRB bit contains peripheral ACK/NACK bit.
+ *	Peripheral ACK:  I2C.Status == 0x00
+ *	Peripheral NACK: I2C.Status == 0x08
  * Byte transmit finished with I2C bus errors or lost arbitration.
  *	PIN -> 0 and BER and/or LAB set.
  *
  * Byte receive finished with no I2C bus errors or lost arbitration.
  *	PIN -> 0. LRB=0/1 based on ACK bit in I2C.Control.
- *	Master receiver must NACK last byte it wants to receive.
+ *	Controller receiver must NACK last byte it wants to receive.
  *	How do we handle this if we don't know direction of transfer?
- *	I2C.Control is write-only so we can't see Master's ACK control bit.
- *
+ *	I2C.Control is write-only so we can't see Controller's ACK control
+ *	bit.
  */
 static int wait_byte_done(int controller, uint8_t mask, uint8_t expected)
 {
 	uint64_t block_timeout;
 	uint64_t task_timeout;
+	uintptr_t raddr;
 	int rv;
 	uint8_t sts;
 
 	rv = 0;
+	raddr = chip_i2c_ctrl_base(controller);
 	block_timeout = get_time().val + I2C_WAIT_BLOCKING_TIMEOUT_US;
 	task_timeout = block_timeout + cdata[controller].timeout_us;
-	sts = MCHP_I2C_STATUS(controller);
+	sts = MCHP_I2C_STATUS(raddr);
 	cdata[controller].hwsts = sts;
 	while (sts & STS_PIN) {
 		if (rv)
 			return rv;
 		if (get_time().val > block_timeout) {
 			rv = wait_for_interrupt(controller,
-					task_timeout - get_time().val);
+						task_timeout - get_time().val);
 		}
-		sts = MCHP_I2C_STATUS(controller);
+		sts = MCHP_I2C_STATUS(raddr);
 		cdata[controller].hwsts = sts;
 	}
 
@@ -452,21 +515,23 @@ static int wait_byte_done(int controller, uint8_t mask, uint8_t expected)
  * Select port on controller. If controller configured
  * for port do nothing.
  * Switch port by reset and reconfigure to handle cases where
- * the slave on current port is driving line(s) low.
+ * the peripheral on current port is driving line(s) low.
  * NOTE: I2C hardware reset only requires one AHB clock, back to back
  * writes is OK but we added an extra write as insurance.
  */
 static void select_port(int port, int controller)
 {
 	uint32_t port_sel;
+	uintptr_t raddr;
 
+	raddr = chip_i2c_ctrl_base(controller);
 	port_sel = (uint32_t)(port & 0x0f);
-	if ((MCHP_I2C_CONFIG(controller) & 0x0f) == port_sel)
+	if ((MCHP_I2C_CONFIG(raddr) & 0x0f) == port_sel)
 		return;
 
-	MCHP_I2C_CONFIG(controller) |= BIT(9);
+	MCHP_I2C_CONFIG(raddr) |= BIT(9);
 	MCHP_EC_ID_RO = 0; /* extra write to read-only as delay */
-	MCHP_I2C_CONFIG(controller) &= ~BIT(9);
+	MCHP_I2C_CONFIG(raddr) &= ~BIT(9);
 	configure_controller(controller, port_sel, i2c_ports[port].kbps);
 }
 
@@ -489,17 +554,20 @@ static uint32_t get_line_level(int port)
 
 /*
  * Check if I2C port connected to controller has bus error or
- * other signalling issues such as stuck clock/data lines.
+ * other issues such as stuck clock/data lines.
  */
 static int i2c_check_recover(int port, int controller)
 {
+	uintptr_t raddr;
 	uint32_t lines;
 	uint8_t reg;
+
+	raddr = chip_i2c_ctrl_base(controller);
 	lines = get_line_level(port);
-	reg = MCHP_I2C_STATUS(controller);
+	reg = MCHP_I2C_STATUS(raddr);
 
 	if ((((reg & (STS_BER | STS_LAB)) || !(reg & STS_NBB)) ||
-			(lines != I2C_LINE_IDLE))) {
+	     (lines != I2C_LINE_IDLE))) {
 		cdata[controller].flags |= (1ul << 16);
 		CPRINTS("I2C%d port%d recov status 0x%02x, SDA:SCL=0x%0x",
 			controller, port, reg, lines);
@@ -512,14 +580,15 @@ static int i2c_check_recover(int port, int controller)
 		reset_controller(controller);
 		select_port(port, controller);
 		/*
-		 * We don't know what edges the slave saw, so sleep long enough
-		 * that the slave will see the new start condition below.
+		 * We don't know what edges the peripheral saw, so sleep long
+		 * enough that the peripheral will see the new start condition
+		 * below.
 		 */
 		usleep(1000);
-		reg = MCHP_I2C_STATUS(controller);
+		reg = MCHP_I2C_STATUS(raddr);
 		lines = get_line_level(port);
 		if ((reg & (STS_BER | STS_LAB)) || !(reg & STS_NBB) ||
-				(lines != I2C_LINE_IDLE))
+		    (lines != I2C_LINE_IDLE))
 			return EC_ERROR_UNKNOWN;
 	}
 	return EC_SUCCESS;
@@ -534,21 +603,23 @@ static inline void push_in_buf(uint8_t **in, uint8_t val, int skip)
 }
 
 /*
- * I2C Master transmit
+ * I2C Controller transmit
  * Caller has filled in cdata[ctrl] parameters
  */
 static int i2c_mtx(int ctrl)
 {
+	uintptr_t raddr;
 	int i, rv;
 
+	raddr = chip_i2c_ctrl_base(ctrl);
 	rv = EC_SUCCESS;
 	cdata[ctrl].flags |= (1ul << 1);
 	if (cdata[ctrl].xflags & I2C_XFER_START) {
 		cdata[ctrl].flags |= (1ul << 2);
-		MCHP_I2C_DATA(ctrl) = cdata[ctrl].slv_addr_8bit;
-		/* Clock out the slave address, sending START bit */
-		MCHP_I2C_CTRL(ctrl) = CTRL_PIN | CTRL_ESO | CTRL_ENI |
-			CTRL_ACK | CTRL_STA;
+		MCHP_I2C_DATA(raddr) = cdata[ctrl].periph_addr_8bit;
+		/* Clock out the peripheral address, sending START bit */
+		MCHP_I2C_CTRL(raddr) = CTRL_PIN | CTRL_ESO | CTRL_ENI |
+				       CTRL_ACK | CTRL_STA;
 		cdata[ctrl].transaction_state = I2C_TRANSACTION_OPEN;
 	}
 
@@ -556,19 +627,19 @@ static int i2c_mtx(int ctrl)
 		rv = wait_byte_done(ctrl, 0xff, 0x00);
 		if (rv) {
 			cdata[ctrl].flags |= (1ul << 17);
-			MCHP_I2C_CTRL(ctrl) = CTRL_PIN | CTRL_ESO |
-					CTRL_ENI | CTRL_STO | CTRL_ACK;
+			MCHP_I2C_CTRL(ctrl) = CTRL_PIN | CTRL_ESO | CTRL_ENI |
+					      CTRL_STO | CTRL_ACK;
 			return rv;
 		}
 		cdata[ctrl].flags |= (1ul << 15);
-		MCHP_I2C_DATA(ctrl) = cdata[ctrl].outp[i];
+		MCHP_I2C_DATA(raddr) = cdata[ctrl].outp[i];
 	}
 
 	rv = wait_byte_done(ctrl, 0xff, 0x00);
 	if (rv) {
 		cdata[ctrl].flags |= (1ul << 18);
-		MCHP_I2C_CTRL(ctrl) = CTRL_PIN | CTRL_ESO | CTRL_ENI |
-			CTRL_STO | CTRL_ACK;
+		MCHP_I2C_CTRL(raddr) = CTRL_PIN | CTRL_ESO | CTRL_ENI |
+				       CTRL_STO | CTRL_ACK;
 		return rv;
 	}
 
@@ -577,17 +648,17 @@ static int i2c_mtx(int ctrl)
 	 * doesn't expect to receive data.
 	 */
 	if ((cdata[ctrl].xflags & I2C_XFER_STOP) &&
-			(cdata[ctrl].in_size == 0)) {
+	    (cdata[ctrl].in_size == 0)) {
 		cdata[ctrl].flags |= (1ul << 3);
-		MCHP_I2C_CTRL(ctrl) = CTRL_PIN | CTRL_ESO |
-			CTRL_STO | CTRL_ACK;
+		MCHP_I2C_CTRL(raddr) = CTRL_PIN | CTRL_ESO | CTRL_STO |
+				       CTRL_ACK;
 		cdata[ctrl].transaction_state = I2C_TRANSACTION_STOPPED;
 	}
 	return rv;
 }
 
 /*
- * I2C Master-Receive helper routine for sending START or
+ * I2C Controller-Receive helper routine for sending START or
  * Repeated-START.
  * This routine should only be called if a (Repeated-)START
  * is required.
@@ -602,10 +673,9 @@ static int i2c_mtx(int ctrl)
  *	will generate START but not transmit data.
  *	Write read address to I2C.Data. Controller will transmit
  *	8-bits of data
- * Endif
  * NOTE: Controller clocks in address on SDA as its transmitting.
  * Therefore 1-byte RX-FIFO will contain address plus R/nW bit.
- * Controller will wait for slave to release SCL before transmitting
+ * Controller will wait for peripheral to release SCL before transmitting
  * 9th clock and latching (N)ACK on SDA.
  * Spin on I2C.Status PIN -> 0. Enable I2C interrupt if spin time
  * exceeds threshold. If a timeout occurs generate STOP and return
@@ -615,39 +685,42 @@ static int i2c_mtx(int ctrl)
  * register we must prepare control logic.
  * If the caller requests STOP and read length is 1 then set
  * clear ACK bit in I2C.Ctrl. Set ESO=ENI=1, PIN=STA=STO=ACK=0
- * in I2C.Ctrl. Master must NACK last byte.
+ * in I2C.Ctrl. Controller must NACK last byte.
  */
 static int i2c_mrx_start(int ctrl)
 {
-	uint8_t u8;
+	uintptr_t raddr;
 	int rv;
+	uint8_t u8;
+
+	raddr = chip_i2c_ctrl_base(ctrl);
 
 	cdata[ctrl].flags |= (1ul << 4);
 	u8 = CTRL_ESO | CTRL_ENI | CTRL_STA | CTRL_ACK;
 	if (cdata[ctrl].transaction_state == I2C_TRANSACTION_OPEN) {
 		cdata[ctrl].flags |= (1ul << 5);
 		/* Repeated-START then address */
-		MCHP_I2C_CTRL(ctrl) = u8;
+		MCHP_I2C_CTRL(raddr) = u8;
 	}
-	MCHP_I2C_DATA(ctrl) = cdata[ctrl].slv_addr_8bit | 0x01;
+	MCHP_I2C_DATA(raddr) = cdata[ctrl].periph_addr_8bit | 0x01;
 	if (cdata[ctrl].transaction_state == I2C_TRANSACTION_STOPPED) {
 		cdata[ctrl].flags |= (1ul << 6);
 		/* address then START */
-		MCHP_I2C_CTRL(ctrl) = u8 | CTRL_PIN;
+		MCHP_I2C_CTRL(raddr) = u8 | CTRL_PIN;
 	}
 	cdata[ctrl].transaction_state = I2C_TRANSACTION_OPEN;
 	/* Controller generates START, transmits data(address) capturing
 	 * 9-bits from SDA (8-bit address + (N)Ack bit).
 	 * We leave captured address in I2C.Data register.
-	 * Master Receive data read routine assumes data is pending
+	 * Controller receive data read routine assumes data is pending
 	 * in I2C.Data
 	 */
 	cdata[ctrl].flags |= (1ul << 7);
 	rv = wait_byte_done(ctrl, 0xff, 0x00);
 	if (rv) {
 		cdata[ctrl].flags |= (1ul << 19);
-		MCHP_I2C_CTRL(ctrl) = CTRL_PIN | CTRL_ESO |
-			CTRL_STO | CTRL_ACK;
+		MCHP_I2C_CTRL(raddr) = CTRL_PIN | CTRL_ESO | CTRL_STO |
+				       CTRL_ACK;
 		return rv;
 	}
 	/* if STOP requested and last 1 or 2 bytes prepare controller
@@ -655,29 +728,28 @@ static int i2c_mrx_start(int ctrl)
 	 * controller is setup to NACK last byte.
 	 */
 	cdata[ctrl].flags |= (1ul << 8);
-	if (cdata[ctrl].xflags & I2C_XFER_STOP &&
-			(cdata[ctrl].in_size < 2)) {
+	if (cdata[ctrl].xflags & I2C_XFER_STOP && (cdata[ctrl].in_size < 2)) {
 		cdata[ctrl].flags |= (1ul << 9);
-		MCHP_I2C_CTRL(ctrl) = CTRL_ESO | CTRL_ENI;
+		MCHP_I2C_CTRL(raddr) = CTRL_ESO | CTRL_ENI;
 	}
 	/*
-	 * Read & discard slave address.
+	 * Read & discard peripheral address.
 	 * Generates clocks for next data
 	 */
 	cdata[ctrl].flags |= (1ul << 10);
-	u8 = MCHP_I2C_DATA(ctrl);
+	u8 = MCHP_I2C_DATA(raddr);
 	return rv;
 }
 /*
- * I2C Master-Receive data read helper.
+ * I2C Controller-Receive data read helper.
  * Assumes I2C is in use, (Rpt-)START was previously sent.
  * Reading I2C.Data generates clocks for the next byte. If caller
  * requests STOP then we must clear I2C.Ctrl ACK before reading
  * second to last byte from RX-FIFO data register. Before reading
  * the last byte we must set I2C.Ctrl to generate a stop after
  * the read from RX-FIFO register.
- * NOTE: I2C.Status.LRB only records the (N)ACK bit in master
- * transmit mode, not in master receive mode.
+ * NOTE: I2C.Status.LRB only records the (N)ACK bit in controller
+ * transmit mode, not in controller receive mode.
  * NOTE2: Do not set ENI bit in I2C.Ctrl for STOP generation.
  */
 static int i2c_mrx_data(int ctrl)
@@ -686,27 +758,30 @@ static int i2c_mrx_data(int ctrl)
 	uint32_t stop = (uint32_t)cdata[ctrl].xflags & I2C_XFER_STOP;
 	uint8_t *pdest = cdata[ctrl].inp;
 	int rv;
+	uintptr_t raddr;
+
+	raddr = chip_i2c_ctrl_base(ctrl);
 
 	cdata[ctrl].flags |= (1ul << 11);
 	while (nrx) {
 		rv = wait_byte_done(ctrl, 0xff, 0x00);
 		if (rv) {
 			cdata[ctrl].flags |= (1ul << 20);
-			MCHP_I2C_CTRL(ctrl) = CTRL_PIN | CTRL_ESO |
-				CTRL_STO | CTRL_ACK;
+			MCHP_I2C_CTRL(raddr) = CTRL_PIN | CTRL_ESO | CTRL_STO |
+					       CTRL_ACK;
 			return rv;
 		}
 		if (stop) {
 			if (nrx == 2) {
 				cdata[ctrl].flags |= (1ul << 12);
-				MCHP_I2C_CTRL(ctrl) = CTRL_ESO | CTRL_ENI;
+				MCHP_I2C_CTRL(raddr) = CTRL_ESO | CTRL_ENI;
 			} else if (nrx == 1) {
 				cdata[ctrl].flags |= (1ul << 13);
-				MCHP_I2C_CTRL(ctrl) = CTRL_PIN | CTRL_ESO |
-					CTRL_STO | CTRL_ACK;
+				MCHP_I2C_CTRL(raddr) = CTRL_PIN | CTRL_ESO |
+						       CTRL_STO | CTRL_ACK;
 			}
 		}
-		*pdest++ = MCHP_I2C_DATA(ctrl);
+		*pdest++ = MCHP_I2C_DATA(raddr);
 		nrx--;
 	}
 	cdata[ctrl].flags |= (1ul << 14);
@@ -714,14 +789,14 @@ static int i2c_mrx_data(int ctrl)
 }
 
 /*
- * Called from common/i2c_master
+ * Called from common I2C
  */
-int chip_i2c_xfer(int port, uint16_t slave_addr_flags,
-		  const uint8_t *out, int out_size,
-		  uint8_t *in, int in_size, int flags)
+int chip_i2c_xfer(int port, uint16_t periph_addr_flags, const uint8_t *out,
+		  int out_size, uint8_t *in, int in_size, int flags)
 {
 	int ctrl;
 	int ret_done;
+	uintptr_t raddr;
 
 	if (out_size == 0 && in_size == 0)
 		return EC_SUCCESS;
@@ -730,6 +805,10 @@ int chip_i2c_xfer(int port, uint16_t slave_addr_flags,
 	if (ctrl < 0)
 		return EC_ERROR_INVAL;
 
+	raddr = chip_i2c_ctrl_base(ctrl);
+	if (raddr == 0)
+		return EC_ERROR_INVAL;
+
 	cdata[ctrl].flags = (1ul << 0);
 	disable_controller_irq(ctrl);
 	select_port(port, ctrl);
@@ -741,7 +820,7 @@ int chip_i2c_xfer(int port, uint16_t slave_addr_flags,
 	cdata[ctrl].hwsts3 = 0;
 	cdata[ctrl].hwsts4 = 0;
 	cdata[ctrl].port = port & 0xff;
-	cdata[ctrl].slv_addr_8bit = I2C_GET_ADDR(slave_addr_flags) << 1;
+	cdata[ctrl].periph_addr_8bit = I2C_STRIP_FLAGS(periph_addr_flags) << 1;
 	cdata[ctrl].out_size = out_size;
 	cdata[ctrl].outp = out;
 	cdata[ctrl].in_size = in_size;
@@ -749,7 +828,7 @@ int chip_i2c_xfer(int port, uint16_t slave_addr_flags,
 	cdata[ctrl].xflags = flags;
 
 	if ((flags & I2C_XFER_START) &&
-		cdata[ctrl].transaction_state == I2C_TRANSACTION_STOPPED) {
+	    cdata[ctrl].transaction_state == I2C_TRANSACTION_STOPPED) {
 		wait_idle(ctrl);
 		ret_done = i2c_check_recover(port, ctrl);
 		if (ret_done)
@@ -780,7 +859,7 @@ int chip_i2c_xfer(int port, uint16_t slave_addr_flags,
 		wait_idle(ctrl);
 
 	/* Check for error conditions */
-	if (MCHP_I2C_STATUS(ctrl) & (STS_LAB | STS_BER)) {
+	if (MCHP_I2C_STATUS(raddr) & (STS_LAB | STS_BER)) {
 		cdata[ctrl].flags |= (1ul << 21);
 		goto err_chip_i2c_xfer;
 	}
@@ -789,15 +868,14 @@ int chip_i2c_xfer(int port, uint16_t slave_addr_flags,
 
 err_chip_i2c_xfer:
 	cdata[ctrl].flags |= (1ul << 22);
-	cdata[ctrl].hwsts2 = MCHP_I2C_STATUS(ctrl); /* record status */
+	cdata[ctrl].hwsts2 = MCHP_I2C_STATUS(raddr); /* record status */
 	/* NOTE: writing I2C.Ctrl.PIN=1 will clear all bits
 	 * except NBB in I2C.Status
 	 */
-	MCHP_I2C_CTRL(ctrl) = CTRL_PIN | CTRL_ESO |
-				       CTRL_STO | CTRL_ACK;
+	MCHP_I2C_CTRL(raddr) = CTRL_PIN | CTRL_ESO | CTRL_STO | CTRL_ACK;
 	cdata[ctrl].transaction_state = I2C_TRANSACTION_STOPPED;
 	/* record status after STOP */
-	cdata[ctrl].hwsts4 = MCHP_I2C_STATUS(ctrl);
+	cdata[ctrl].hwsts4 = MCHP_I2C_STATUS(raddr);
 
 	/* record line levels.
 	 * Note line levels may reflect STOP condition
@@ -855,6 +933,17 @@ int i2c_get_line_levels(int port)
 	return rv;
 }
 
+/*
+ * this function returns the controller for I2C
+ * return mod of MCHP_I2C_CTRL_MAX
+ */
+__overridable int board_i2c_p2c(int port)
+{
+	if (port < 0 || port >= I2C_PORT_COUNT)
+		return -1;
+	return i2c_p2c[port];
+}
+
 /*
  * I2C port must be a zero based number.
  * MCHP I2C can map any port to any of the 4 controllers.
@@ -868,7 +957,7 @@ int i2c_port_to_controller(int port)
 
 void i2c_set_timeout(int port, uint32_t timeout)
 {
-	/* Param is port, but timeout is stored by-controller. */
+	/* Parameter is port, but timeout is stored by-controller. */
 	cdata[i2c_port_to_controller(port)].timeout_us =
 		timeout ? timeout : I2C_TIMEOUT_DEFAULT_US;
 }
@@ -893,6 +982,9 @@ void i2c_init(void)
 	memset(cdata, 0, sizeof(cdata));
 
 	for (i = 0; i < i2c_ports_used; ++i) {
+		/* Assign I2C controller to I2C port */
+		i2c_p2c[i2c_ports[i].port] = i % MCHP_I2C_CTRL_MAX;
+
 		controller = i2c_port_to_controller(i2c_ports[i].port);
 		kbps = i2c_ports[i].kbps;
 
@@ -900,10 +992,9 @@ void i2c_init(void)
 		i2c_ctrl_slp_en(controller, 0);
 
 		if (controller_kbps[controller] &&
-				(controller_kbps[controller] != kbps)) {
+		    (controller_kbps[controller] != kbps)) {
 			CPRINTF("I2C[%d] init speed conflict: %d != %d\n",
-				controller, kbps,
-				controller_kbps[controller]);
+				controller, kbps, controller_kbps[controller]);
 			kbps = MIN(kbps, controller_kbps[controller]);
 		}
 
@@ -916,7 +1007,7 @@ void i2c_init(void)
 
 		controller_kbps[controller] = pbc->freq_khz;
 		configure_controller(controller, i2c_ports[i].port,
-					controller_kbps[controller]);
+				     controller_kbps[controller]);
 		cdata[controller].task_waiting = TASK_ID_INVALID;
 		cdata[controller].transaction_state = I2C_TRANSACTION_STOPPED;
 		/* Use default timeout. */
@@ -934,6 +1025,7 @@ static void handle_interrupt(int controller)
 {
 	uint32_t r;
 	int id = cdata[controller].task_waiting;
+	uintptr_t raddr = chip_i2c_ctrl_base(controller);
 
 	/*
 	 * Write to control register interferes with I2C transaction.
@@ -941,24 +1033,67 @@ static void handle_interrupt(int controller)
 	 * we want to wait for STS_PIN/STS_NBB.
 	 */
 	disable_controller_irq(controller);
-	cdata[controller].hwsts3 = MCHP_I2C_STATUS(controller);
+	cdata[controller].hwsts3 = MCHP_I2C_STATUS(raddr);
 	/* Clear all interrupt status */
-	r = MCHP_I2C_COMPLETE(controller);
-	MCHP_I2C_COMPLETE(controller) = r;
+	r = MCHP_I2C_COMPLETE(raddr);
+	MCHP_I2C_COMPLETE(raddr) = r;
 	cdata[controller].i2c_complete = r;
 	MCHP_INT_SOURCE(MCHP_I2C_GIRQ) = MCHP_I2C_GIRQ_BIT(controller);
 
 	/* Wake up the task which was waiting on the I2C interrupt, if any. */
 	if (id != TASK_ID_INVALID)
-		task_set_event(id, TASK_EVENT_I2C_IDLE, 0);
+		task_set_event(id, TASK_EVENT_I2C_IDLE);
 }
 
-void i2c0_interrupt(void) { handle_interrupt(0); }
-void i2c1_interrupt(void) { handle_interrupt(1); }
-void i2c2_interrupt(void) { handle_interrupt(2); }
-void i2c3_interrupt(void) { handle_interrupt(3); }
+static void i2c0_interrupt(void)
+{
+	handle_interrupt(0);
+}
+static void i2c1_interrupt(void)
+{
+	handle_interrupt(1);
+}
+static void i2c2_interrupt(void)
+{
+	handle_interrupt(2);
+}
+static void i2c3_interrupt(void)
+{
+	handle_interrupt(3);
+}
+#if defined(CHIP_FAMILY_MEC172X)
+static void i2c4_interrupt(void)
+{
+	handle_interrupt(4);
+}
+#elif defined(CHIP_FAMILY_MEC152X)
+static void i2c4_interrupt(void)
+{
+	handle_interrupt(4);
+}
+static void i2c5_interrupt(void)
+{
+	handle_interrupt(5);
+}
+static void i2c6_interrupt(void)
+{
+	handle_interrupt(6);
+}
+static void i2c7_interrupt(void)
+{
+	handle_interrupt(7);
+}
+#endif
 
 DECLARE_IRQ(MCHP_IRQ_I2C_0, i2c0_interrupt, 2);
 DECLARE_IRQ(MCHP_IRQ_I2C_1, i2c1_interrupt, 2);
 DECLARE_IRQ(MCHP_IRQ_I2C_2, i2c2_interrupt, 2);
 DECLARE_IRQ(MCHP_IRQ_I2C_3, i2c3_interrupt, 2);
+#if defined(CHIP_FAMILY_MEC172X)
+DECLARE_IRQ(MCHP_IRQ_I2C_4, i2c4_interrupt, 2);
+#elif defined(CHIP_FAMILY_MEC152X)
+DECLARE_IRQ(MCHP_IRQ_I2C_4, i2c4_interrupt, 2);
+DECLARE_IRQ(MCHP_IRQ_I2C_5, i2c5_interrupt, 2);
+DECLARE_IRQ(MCHP_IRQ_I2C_6, i2c6_interrupt, 2);
+DECLARE_IRQ(MCHP_IRQ_I2C_7, i2c7_interrupt, 2);
+#endif
diff --git a/chip/mchp/i2c_chip.h b/chip/mchp/i2c_chip.h
new file mode 100644
index 0000000000..b7109c4c69
--- /dev/null
+++ b/chip/mchp/i2c_chip.h
@@ -0,0 +1,33 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* MCHP-specific I2C module for Chrome EC */
+
+#ifndef _I2C_CHIP_H
+#define _I2C_CHIP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Place any C interfaces here */
+
+/*
+ * Function returns the controller for I2C.
+ *
+ * Default function assigns controller for I2C port with modulo operation. If
+ * the I2C ports used are greater than MCHP_I2C_CTRL_MAX, then I2C ports will
+ * share the controller. Typically Type-C chips need individual controller per
+ * port because of heavy I2C transactions. Hence, define a board specific
+ * controller assignment when the I2C ports used are greater than
+ * MCHP_I2C_CTRL_MAX.
+ */
+__override_proto int board_i2c_p2c(int port);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _I2C_CHIP_H */
diff --git a/chip/mchp/keyboard_raw.c b/chip/mchp/keyboard_raw.c
index 946ea1ca90..30181776fa 100644
--- a/chip/mchp/keyboard_raw.c
+++ b/chip/mchp/keyboard_raw.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,8 +11,8 @@
 #include "keyboard_scan.h"
 #include "registers.h"
 #include "task.h"
-#include "util.h"
 #include "tfdp_chip.h"
+#include "util.h"
 
 /*
  * Using direct mode interrupt, do not enable
@@ -86,7 +86,7 @@ void keyboard_raw_enable_interrupt(int enable)
 	}
 }
 
-void keyboard_raw_interrupt(void)
+static void keyboard_raw_interrupt(void)
 {
 	/* Clear interrupt status bits */
 	MCHP_KS_KSI_STATUS = 0xff;
diff --git a/chip/mchp/lfw/ec_lfw.c b/chip/mchp/lfw/ec_lfw.c
index edd945037c..94b851cf1f 100644
--- a/chip/mchp/lfw/ec_lfw.c
+++ b/chip/mchp/lfw/ec_lfw.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -6,23 +6,22 @@
  *
  */
 
-#include <stdint.h>
-
+#include "clock.h"
 #include "config.h"
+#include "cpu.h"
+#include "cros_version.h"
+#include "dma.h"
 #include "gpio.h"
+#include "hwtimer.h"
+#include "registers.h"
 #include "spi.h"
 #include "spi_flash.h"
-#include "util.h"
-#include "timer.h"
-#include "dma.h"
-#include "registers.h"
-#include "cpu.h"
-#include "clock.h"
 #include "system.h"
-#include "version.h"
-#include "hwtimer.h"
-#include "gpio_list.h"
 #include "tfdp_chip.h"
+#include "timer.h"
+#include "util.h"
+
+#include <stdint.h>
 
 #ifdef CONFIG_MCHP_LFW_DEBUG
 #include "dma_chip.h"
@@ -30,26 +29,30 @@
 
 #include "ec_lfw.h"
 
+/* Must come after other header files and interrupt handler declarations */
+#include "gpio_list.h"
+
 /*
  * Check if LFW build is pulling in GPSPI which is not
  * used for EC firmware SPI flash access.
  */
 #ifdef CONFIG_MCHP_GPSPI
-#error "FORCED BUILD ERROR: CONFIG_MCHP_CMX_GPSPI is defined"
+#error "FORCED BUILD ERROR: CONFIG_MCHP_GPSPI is defined"
 #endif
 
 #define LFW_SPI_BYTE_TRANSFER_TIMEOUT_US (1 * MSEC)
 #define LFW_SPI_BYTE_TRANSFER_POLL_INTERVAL_US 100
 
-__attribute__ ((section(".intvector")))
+__attribute__((section(".intvector")))
 const struct int_vector_t hdr_int_vect = {
 	/* init sp, unused. set by MEC ROM loader */
-	(void *)lfw_stack_top,  /* preserve ROM log. was (void *)0x11FA00, */
-	&lfw_main,	/* was &lfw_main, */	  /* reset vector */
-	&fault_handler,   /* NMI handler */
-	&fault_handler,   /* HardFault handler */
-	&fault_handler,   /* MPU fault handler */
-	&fault_handler    /* Bus fault handler */
+	(void *)lfw_stack_top, /* preserve ROM log. was (void *)0x11FA00, */
+	&lfw_main,
+	/* was &lfw_main, */ /* reset vector */
+	&fault_handler, /* NMI handler */
+	&fault_handler, /* HardFault handler */
+	&fault_handler, /* MPU fault handler */
+	&fault_handler /* Bus fault handler */
 };
 
 /* SPI devices - from board.c */
@@ -62,7 +65,7 @@ const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
  * At POR or EC reset MCHP Boot-ROM should only load LFW and jumps
  * into LFW entry point located at offset 0x04 of LFW.
  * Entry point is programmed into SPI Header by Python SPI image
- * builder at chip/mec1701/util/pack_ec.py
+ * builder in chip/mchp/util.
  *
  * EC_RO/RW calling LFW should enter through this routine if you
  * want the vector table updated. The stack should be set to
@@ -107,7 +110,7 @@ void timer_init(void)
 
 	val = MCHP_TMR32_CTL(0);
 
-	/* Pre-scale = 48 -> 1MHz -> Period = 1us */
+	/* Prescale = 48 -> 1MHz -> Period = 1 us */
 	val = (val & 0xffff) | (47 << 16);
 
 	MCHP_TMR32_CTL(0) = val;
@@ -123,7 +126,6 @@ void timer_init(void)
 
 	/* Start counting in timer 0 */
 	MCHP_TMR32_CTL(0) |= BIT(5);
-
 }
 
 /*
@@ -132,16 +134,13 @@ void timer_init(void)
  * before starting SPI read to minimize probability of
  * timer wrap.
  */
-static int spi_flash_readloc(uint8_t *buf_usr,
-				unsigned int offset,
-				unsigned int bytes)
+static int spi_flash_readloc(uint8_t *buf_usr, unsigned int offset,
+			     unsigned int bytes)
 {
-	uint8_t cmd[4] = {SPI_FLASH_READ,
-				(offset >> 16) & 0xFF,
-				(offset >> 8) & 0xFF,
-				offset & 0xFF};
+	uint8_t cmd[4] = { SPI_FLASH_READ, (offset >> 16) & 0xFF,
+			   (offset >> 8) & 0xFF, offset & 0xFF };
 
-	if (offset + bytes > CONFIG_FLASH_SIZE)
+	if (offset + bytes > CONFIG_FLASH_SIZE_BYTES)
 		return EC_ERROR_INVAL;
 
 	__hw_clock_source_set(0); /* restart free run timer */
@@ -156,8 +155,8 @@ static int spi_flash_readloc(uint8_t *buf_usr,
  */
 int spi_image_load(uint32_t offset)
 {
-	uint8_t *buf = (uint8_t *) (CONFIG_RW_MEM_OFF +
-				    CONFIG_PROGRAM_MEMORY_BASE);
+	uint8_t *buf =
+		(uint8_t *)(CONFIG_RW_MEM_OFF + CONFIG_PROGRAM_MEMORY_BASE);
 	uint32_t i;
 #ifdef CONFIG_MCHP_LFW_DEBUG
 	uint32_t crc_calc, crc_exp;
@@ -172,13 +171,11 @@ int spi_image_load(uint32_t offset)
 	for (i = 0; i < CONFIG_RO_SIZE; i += SPI_CHUNK_SIZE)
 #ifdef CONFIG_MCHP_LFW_DEBUG
 		rc = spi_flash_readloc(&buf[i], offset + i, SPI_CHUNK_SIZE);
-		if (rc != EC_SUCCESS) {
-			trace2(0, LFW, 0,
-				"spi_flash_readloc block %d ret = %d",
-				i, rc);
-			while (MCHP_PCR_PROC_CLK_CTL)
-				MCHP_PCR_CHIP_OSC_ID &= 0x1FE;
-		}
+	if (rc != EC_SUCCESS) {
+		trace2(0, LFW, 0, "spi_flash_readloc block %d ret = %d", i, rc);
+		while (MCHP_PCR_PROC_CLK_CTL)
+			MCHP_PCR_CHIP_OSC_ID &= 0x1FE;
+	}
 #else
 		spi_flash_readloc(&buf[i], offset + i, SPI_CHUNK_SIZE);
 #endif
@@ -234,11 +231,15 @@ timestamp_t get_time(void)
 {
 	timestamp_t ts;
 
-	ts.le.hi = 0;	/* clksrc_high; */
+	ts.le.hi = 0; /* clksrc_high; */
 	ts.le.lo = __hw_clock_source_read();
 	return ts;
 }
 
+#ifdef CONFIG_UART_CONSOLE
+
+BUILD_ASSERT(CONFIG_UART_CONSOLE < MCHP_UART_INSTANCES);
+
 void uart_write_c(char c)
 {
 	/* Put in carriage return prior to newline to mimic uart_vprintf() */
@@ -246,9 +247,9 @@ void uart_write_c(char c)
 		uart_write_c('\r');
 
 	/* Wait for space in transmit FIFO. */
-	while (!(MCHP_UART_LSR(0) & BIT(5)))
+	while (!(MCHP_UART_LSR(CONFIG_UART_CONSOLE) & BIT(5)))
 		;
-	MCHP_UART_TB(0) = c;
+	MCHP_UART_TB(CONFIG_UART_CONSOLE) = c;
 }
 
 void uart_puts(const char *str)
@@ -261,55 +262,72 @@ void uart_puts(const char *str)
 	} while (*str);
 }
 
-void fault_handler(void)
-{
-	uart_puts("EXCEPTION!\nTriggering watchdog reset\n");
-	/* trigger reset in 1 ms */
-	usleep(1000);
-	MCHP_PCR_SYS_RST = MCHP_PCR_SYS_SOFT_RESET;
-	while (1)
-		;
-
-}
-
-void jump_to_image(uintptr_t init_addr)
-{
-	void (*resetvec)(void) = (void(*)(void))init_addr;
-
-	resetvec();
-}
-
 void uart_init(void)
 {
-	/* Set UART to reset on VCC1_RESET instaed of nSIO_RESET */
-	MCHP_UART_CFG(0) &= ~BIT(1);
+	/* Set UART to reset on VCC1_RESET instead of nSIO_RESET */
+	MCHP_UART_CFG(CONFIG_UART_CONSOLE) &= ~BIT(1);
 
 	/* Baud rate = 115200. 1.8432MHz clock. Divisor = 1 */
 
 	/* Set CLK_SRC = 0 */
-	MCHP_UART_CFG(0) &= ~BIT(0);
+	MCHP_UART_CFG(CONFIG_UART_CONSOLE) &= ~BIT(0);
 
 	/* Set DLAB = 1 */
-	MCHP_UART_LCR(0) |= BIT(7);
+	MCHP_UART_LCR(CONFIG_UART_CONSOLE) |= BIT(7);
 
 	/* PBRG0/PBRG1 */
-	MCHP_UART_PBRG0(0) = 1;
-	MCHP_UART_PBRG1(0) = 0;
+	MCHP_UART_PBRG0(CONFIG_UART_CONSOLE) = 1;
+	MCHP_UART_PBRG1(CONFIG_UART_CONSOLE) = 0;
 
 	/* Set DLAB = 0 */
-	MCHP_UART_LCR(0) &= ~BIT(7);
+	MCHP_UART_LCR(CONFIG_UART_CONSOLE) &= ~BIT(7);
 
 	/* Set word length to 8-bit */
-	MCHP_UART_LCR(0) |= BIT(0) | BIT(1);
+	MCHP_UART_LCR(CONFIG_UART_CONSOLE) |= BIT(0) | BIT(1);
 
 	/* Enable FIFO */
-	MCHP_UART_FCR(0) = BIT(0);
+	MCHP_UART_FCR(CONFIG_UART_CONSOLE) = BIT(0);
 
 	/* Activate UART */
-	MCHP_UART_ACT(0) |= BIT(0);
+	MCHP_UART_ACT(CONFIG_UART_CONSOLE) |= BIT(0);
 
 	gpio_config_module(MODULE_UART, 1);
 }
+#else
+void uart_write_c(char c __attribute__((unused)))
+{
+}
+
+void uart_puts(const char *str __attribute__((unused)))
+{
+}
+
+void uart_init(void)
+{
+}
+#endif /* #ifdef CONFIG_UART_CONSOLE */
+
+noreturn void watchdog_reset(void)
+{
+	uart_puts("EXCEPTION!\nTriggering watchdog reset\n");
+	/* trigger reset in 1 ms */
+	usleep(1000);
+	MCHP_PCR_SYS_RST = MCHP_PCR_SYS_SOFT_RESET;
+	while (1)
+		;
+}
+
+void fault_handler(void)
+{
+	asm("b watchdog_reset");
+}
+
+void jump_to_image(uintptr_t init_addr)
+{
+	void (*resetvec)(void) = (void (*)(void))init_addr;
+
+	resetvec();
+}
 
 /*
  * If any of VTR POR, VBAT POR, chip resets, or WDT reset are active
@@ -318,16 +336,13 @@ void uart_init(void)
 void system_init(void)
 {
 	uint32_t wdt_sts = MCHP_VBAT_STS & MCHP_VBAT_STS_ANY_RST;
-	uint32_t rst_sts = MCHP_PCR_PWR_RST_STS &
-				MCHP_PWR_RST_STS_VTR;
+	uint32_t rst_sts = MCHP_PCR_PWR_RST_STS & MCHP_PWR_RST_STS_SYS;
 
-	trace12(0, LFW, 0,
-		"VBAT_STS = 0x%08x  PCR_PWR_RST_STS = 0x%08x",
+	trace12(0, LFW, 0, "VBAT_STS = 0x%08x  PCR_PWR_RST_STS = 0x%08x",
 		wdt_sts, rst_sts);
 
 	if (rst_sts || wdt_sts)
-		MCHP_VBAT_RAM(MCHP_IMAGETYPE_IDX)
-					= EC_IMAGE_UNKNOWN;
+		MCHP_VBAT_RAM(MCHP_IMAGETYPE_IDX) = EC_IMAGE_UNKNOWN;
 }
 
 enum ec_image system_get_image_copy(void)
@@ -335,7 +350,6 @@ enum ec_image system_get_image_copy(void)
 	return MCHP_VBAT_RAM(MCHP_IMAGETYPE_IDX);
 }
 
-
 /*
  * lfw_main is entered by MEC BootROM or EC_RO/RW calling it directly.
  * NOTE: Based on LFW from MEC1322
@@ -349,11 +363,10 @@ enum ec_image system_get_image_copy(void)
  */
 void lfw_main(void)
 {
-
 	uintptr_t init_addr;
 
 	/* install vector table */
-	*((uintptr_t *) 0xe000ed08) = (uintptr_t) &hdr_int_vect;
+	*((uintptr_t *)0xe000ed08) = (uintptr_t)&hdr_int_vect;
 
 	/* Use 48 MHz processor clock to power through boot */
 	MCHP_PCR_PROC_CLK_CTL = 1;
@@ -381,7 +394,7 @@ void lfw_main(void)
 	uart_init();
 	system_init();
 
-	spi_enable(CONFIG_SPI_FLASH_PORT, 1);
+	spi_enable(SPI_FLASH_DEVICE, 1);
 
 	uart_puts("littlefw ");
 	uart_puts(current_image_data.version);
diff --git a/chip/mchp/lfw/ec_lfw.h b/chip/mchp/lfw/ec_lfw.h
index c989a3bc1b..0c677e5d0b 100644
--- a/chip/mchp/lfw/ec_lfw.h
+++ b/chip/mchp/lfw/ec_lfw.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -7,6 +7,7 @@
  */
 
 #include <stdint.h>
+
 #include <stdnoreturn.h>
 
 /* Why naked?  This is dangerous except for
@@ -30,12 +31,12 @@ void fault_handler(void) __attribute__((naked));
 extern uint32_t lfw_stack_top[];
 
 struct int_vector_t {
-	void   *stack_ptr;
-	void   *reset_vector;
-	void   *nmi;
-	void   *hard_fault;
-	void   *bus_fault;
-	void   *usage_fault;
+	void *stack_ptr;
+	void *reset_vector;
+	void *nmi;
+	void *hard_fault;
+	void *bus_fault;
+	void *usage_fault;
 };
 
-#define SPI_CHUNK_SIZE			1024
+#define SPI_CHUNK_SIZE 1024
diff --git a/chip/mchp/lfw/ec_lfw.ld b/chip/mchp/lfw/ec_lfw.ld
index 8e8601a5ee..d178a42280 100644
--- a/chip/mchp/lfw/ec_lfw.ld
+++ b/chip/mchp/lfw/ec_lfw.ld
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -79,7 +79,15 @@ SECTIONS
         FILL(0xFF);
         . = ORIGIN(SRAM) + LENGTH(SRAM) - 1;
         BYTE(0xFF);   /* emit at least a byte to make linker happy */
-    }
+    } >SRAM
 
     __image_size = LOADADDR(.text) + SIZEOF(.text) - ORIGIN(VECTOR);
+
+    /*
+     * Discard C++ exception index table and exception table. These are
+     * described in more detail in "Exception Handling ABI for ARM
+     * Architecture":
+     * https://github.com/ARM-software/abi-aa/blob/60a8eb8c55e999d74dac5e368fc9d7e36e38dda4/ehabi32/ehabi32.rst#54the-object-producer-interface
+     */
+    /DISCARD/ : { *(.ARM.*) }
 }
diff --git a/chip/mchp/lfw/ec_lfw_416kb.ld b/chip/mchp/lfw/ec_lfw_416kb.ld
new file mode 100644
index 0000000000..c7dfacada3
--- /dev/null
+++ b/chip/mchp/lfw/ec_lfw_416kb.ld
@@ -0,0 +1,97 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * MCHP MEC parts with 416KB SRAM SoC little FW
+ *
+ */
+
+/*
+ * Memory Spaces Definitions
+ * LFW occupies first 4KB of CODE SRAM.
+ * First 24 bytes contain a minimal Cortex-M4
+ * vector table.
+ */
+MEMORY
+{
+    VECTOR(r )  : ORIGIN =  0x0C0000, LENGTH = 0x18
+    SRAM (xrw)  : ORIGIN =  0x0C0018, LENGTH = 0xFE8
+}
+
+/*
+ * ld does not allow mathematical expressions in ORIGIN/LENGTH, so check the
+ * values here.
+ */
+ASSERT(ORIGIN(VECTOR) + LENGTH(VECTOR) == ORIGIN(SRAM), "Invalid SRAM origin.")
+ASSERT(LENGTH(VECTOR) + LENGTH(SRAM) == 0x1000, "Invalid VECTOR+SRAM length.")
+
+/*
+ * The entry point is informative, for debuggers and simulators,
+ * since the Cortex-M vector points to it anyway.
+ */
+ENTRY(lfw_main)
+
+/*
+ * MEC172xN has 416KB total SRAM: 352KB CODE 64KB DATA
+ * CODE: 0x0C0000 - 0x117FFF
+ * DATA: 0x118000 - 0x127FFF
+ * Boot-ROM log is 0x11FF00 - 0x11FFFF
+ * MEC172x Top 1KB is not cleared if OTP customer flag enabled.
+ * !!! TODO !!! Does presence of PUF feature move customer area?
+ * Boot-ROM spec states 3.5KB from top is lost.
+ * 0x12_7800 - 0x12_7fff 2KB used by PUF option
+ * 0x12_7400 - 0x12_77ff 1KB Customer use. Not cleared by Boot-ROM
+ * 0x12_7200 - 0x12_73ff 512 byte Boot-ROM log
+ * CrOS EC puts panic data at Top of RAM.
+ * We must set Top of RAM to be customer region far enough to
+ * hold panic data.
+ * Set Top of SRAM to 0x12_7800.
+ * This requires size of SRAM = 0x127800 - 0x118000 = 0xF800 (62 KB)
+ */
+PROVIDE( lfw_stack_top = 0x127800 );
+
+/* Sections Definitions */
+
+SECTIONS
+{
+
+    /*
+     * The vector table goes first
+     */
+    .intvector :
+    {
+        . = ALIGN(4);
+        KEEP(*(.intvector))
+    } > VECTOR
+
+    /*
+     * The program code is stored in the .text section,
+     * which goes to FLASH.
+     */
+
+    .text :
+    {
+        *(.text .text.*)                        /* all remaining code */
+        *(.rodata .rodata.*)            /* read-only data (constants) */
+    } >SRAM
+
+    . = ALIGN(4);
+
+    /* Padding */
+
+    .fill : {
+        FILL(0xFF);
+        . = ORIGIN(SRAM) + LENGTH(SRAM) - 1;
+        BYTE(0xFF);   /* emit at least a byte to make linker happy */
+    } >SRAM
+
+    __image_size = LOADADDR(.text) + SIZEOF(.text) - ORIGIN(VECTOR);
+
+    /*
+     * Discard C++ exception index table and exception table. These are
+     * described in more detail in "Exception Handling ABI for ARM
+     * Architecture":
+     * https://github.com/ARM-software/abi-aa/blob/60a8eb8c55e999d74dac5e368fc9d7e36e38dda4/ehabi32/ehabi32.rst#54the-object-producer-interface
+     */
+    /DISCARD/ : { *(.ARM.*) }
+}
diff --git a/chip/mchp/lfw/gpio.inc b/chip/mchp/lfw/gpio.inc
new file mode 100644
index 0000000000..76de618bf3
--- /dev/null
+++ b/chip/mchp/lfw/gpio.inc
@@ -0,0 +1,107 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Common GPIOs needed for LFW loader and main process FW
+ */
+
+/* SPI
+ * External SPI chip select must be open drain and driven high or
+ * internal SPI chip select must be push-pull and driven high before
+ * SPI controller configuration.
+ * QMSPI external Shared CS0# is GPIO_0055
+ * QMSPI internal CS0# is GPIO_0116
+ */
+#if defined(CHIP_VARIANT_MEC1727SZ)
+GPIO(QMSPI_CS0, PIN(0116), GPIO_PULL_UP | GPIO_HIGH)
+#else
+GPIO(QMSPI_CS0, PIN(055), GPIO_ODR_HIGH)
+#endif
+
+/* Boot-ROM loads from external or internal SPI flash.
+ * There are two external ports: shared(default) and private.
+ * NOTE: QMSPI Shared SPI Port pins are on VTR2
+ * SHD_CS0# = GPIO 0055 Func 2 bank 1 b[13]
+ * SHD_CLK  = GPIO 0056 Func 2 bank 1 b[14]
+ * SHD_IO0  = GPIO 0223 Func 1 bank 4 b[19]
+ * SHD_IO1  = GPIO 0224 Func 2 bank 4 b[20]
+ * Not using IO2 and IO2 as data
+ * SHD_IO2  = GPIO 0227 Func 1 bank 4 b[23]
+ * SHD_IO3  = GPIO 0016 Func 2 bank 0 b[14]
+ * MEC1727 variants load from internal 512KB SPI flash(internal only pins)
+ * INT_CS# = GPIO 0116 Func 1 bank 2 14
+ * INT_SCK = GPIO 0117 Func 1 bank 2 15
+ * INT_IO0 = GPIO 0074 Func 1 bank 1 28
+ * INT_IO1 = GPIO 0075 Func 1 bank 1 29
+ * INT_WP# = GPIO 0076 Func 0 for WP# control
+ * Internal flash HOLD# connected to VTR1 rail.
+ */
+#if defined(CHIP_VARIANT_MEC1727SZ)
+/* MEC1727 variants have internal SPI flash on internal only pins */
+ALTERNATE(PIN_MASK(2, 0x4000), 1, MODULE_SPI_FLASH, GPIO_PULL_UP)
+ALTERNATE(PIN_MASK(2, 0x8000), 1, MODULE_SPI_FLASH, 0)
+ALTERNATE(PIN_MASK(1, 0x30000000), 1, MODULE_SPI_FLASH, 0)
+#else
+/* external SPI flash on QMSPI SHD_xx pins */
+ALTERNATE(PIN_MASK(1, 0x2000), 2, MODULE_SPI_FLASH, GPIO_ODR_HIGH)
+ALTERNATE(PIN_MASK(1, 0x4000), 2, MODULE_SPI_FLASH, 0)
+ALTERNATE(PIN_MASK(4, 0x080000), 1, MODULE_SPI_FLASH, 0)
+ALTERNATE(PIN_MASK(4, 0x100000), 2, MODULE_SPI_FLASH, 0)
+#endif
+
+/* UART
+ * Per CONFIG_UART_CONSOLE and chip to configure UART pins
+ */
+#if CONFIG_UART_CONSOLE == 0
+/* select UART0 */
+/* MEC170X, MEC152X and MEC172X support same UART0 pins and ALT function */
+/*
+ * UART0
+ * GPIO_0105 Func 1 = UART_RX
+ * GPIO_0104 Func 1 = UART_TX
+ * Bank 2 bits[5:4]
+ */
+ALTERNATE(PIN_MASK(2, 0x30), 1, MODULE_UART, 0)
+
+#elif CONFIG_UART_CONSOLE == 1
+/* select UART1 */
+/* MEC170X, MEC152X and MEC172X support same UART1 pins
+ * but ALT function 2 on MEC170X, function 1 on others
+ */
+#if defined(CHIP_FAMILY_MEC170X)
+/*
+ * UART1
+ * GPIO_0171 Func 2 = UART_RX
+ * GPIO_0170 Func 2 = UART_TX
+ * Bank 3 bits[25:24]
+ */
+ALTERNATE(PIN_MASK(3, 0x03000000), 2, MODULE_UART, 0)
+
+#else
+/*
+ * UART1
+ * GPIO_0171 Func 1 = UART_RX
+ * GPIO_0170 Func 1 = UART_TX
+ * Bank 3 bits[25:24]
+ */
+ALTERNATE(PIN_MASK(3, 0x03000000), 1, MODULE_UART, 0)
+
+#endif /* defined(CHIP_FAMILY_MEC170X) */
+
+#else
+/* select UART2 */
+/* only MEC152X supports UART2 pins */
+#if defined(CHIP_FAMILY_MEC152X)
+/*
+ * UART2
+ * GPIO_0145 Func 2 = UART_RX
+ * GPIO_0146 Func 2 = UART_TX
+ * Bank 3 bits[6:5]
+ */
+ALTERNATE(PIN_MASK(3, 0x60), 2, MODULE_UART, 0)
+
+#endif /* defined(CHIP_FAMILY_MEC152X) */
+
+#endif /* CONFIG_UART_CONSOLE == 0 */
diff --git a/chip/mchp/lpc.c b/chip/mchp/lpc.c
index 91adb7f17c..e41e4b0c78 100644
--- a/chip/mchp/lpc.c
+++ b/chip/mchp/lpc.c
@@ -1,49 +1,48 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* LPC module for MCHP MEC family */
 
-#include "common.h"
 #include "acpi.h"
+#include "chipset.h"
+#include "common.h"
 #include "console.h"
+#include "espi.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "host_command.h"
 #include "keyboard_protocol.h"
 #include "lpc.h"
 #include "lpc_chip.h"
-#include "espi.h"
 #include "port80.h"
 #include "registers.h"
 #include "system.h"
 #include "task.h"
+#include "tfdp_chip.h"
 #include "timer.h"
 #include "util.h"
-#include "chipset.h"
-#include "tfdp_chip.h"
 
 /* Console output macros */
 #ifdef CONFIG_MCHP_DEBUG_LPC
 #define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args)
 #else
 #define CPUTS(...)
 #define CPRINTS(...)
 #endif
 
-static uint8_t
-mem_mapped[0x200] __attribute__((section(".bss.big_align")));
+static uint8_t mem_mapped[0x200] __attribute__((section(".bss.big_align")));
 
 static struct host_packet lpc_packet;
 static struct host_cmd_handler_args host_cmd_args;
-static uint8_t host_cmd_flags;   /* Flags from host command */
+static uint8_t host_cmd_flags; /* Flags from host command */
 
 static uint8_t params_copy[EC_LPC_HOST_PACKET_SIZE] __aligned(4);
 static int init_done;
 
-static struct ec_lpc_host_args * const lpc_host_args =
+static struct ec_lpc_host_args *const lpc_host_args =
 	(struct ec_lpc_host_args *)mem_mapped;
 
 #ifdef CONFIG_BOARD_ID_CMD_ACPI_EC1
@@ -52,13 +51,12 @@ static uint8_t custom_acpi_ec2os_cnt;
 static uint8_t custom_apci_ec2os[4];
 #endif
 
-
 static void keyboard_irq_assert(void)
 {
 #ifdef CONFIG_KEYBOARD_IRQ_GPIO
 	/*
 	 * Enforce signal-high for long enough for the signal to be
-	 * pulled high by the external pullup resistor. This ensures the
+	 * pulled high by the external pull up resistor. This ensures the
 	 * host will see the following falling edge, regardless of the
 	 * line state before this function call.
 	 */
@@ -81,14 +79,14 @@ static void keyboard_irq_assert(void)
  * Generate SMI pulse to the host chipset via GPIO.
  *
  * If the x86 is in S0, SMI# is sampled at 33MHz, so minimum pulse length
- * is 60ns. If the x86 is in S3, SMI# is sampled at 32.768KHz, so we need
+ * is 60 ns. If the x86 is in S3, SMI# is sampled at 32.768KHz, so we need
  * pulse length >61us. Both are short enough and events are infrequent,
- * so just delay for 65us.
+ * so just delay for 65 us.
  */
 static void lpc_generate_smi(void)
 {
 	CPUTS("LPC Pulse SMI");
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	/* eSPI: pulse SMI# Virtual Wire low */
 	espi_vw_pulse_wire(VW_SMI_L, 0);
 #else
@@ -106,11 +104,11 @@ static void lpc_generate_sci(void)
 	udelay(65);
 	gpio_set_level(CONFIG_SCI_GPIO, 1);
 #else
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	espi_vw_pulse_wire(VW_SCI_L, 0);
 #else
 	MCHP_ACPI_PM_STS |= 1;
-	udelay(65);
+	udelay(CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US);
 	MCHP_ACPI_PM_STS &= ~1;
 #endif
 #endif
@@ -129,7 +127,7 @@ static void lpc_update_wake(host_event_t wake_events)
 	 */
 	wake_events &= ~EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON);
 
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	espi_vw_set_wire(VW_WAKE_L, !wake_events);
 #else
 	/* Signal is asserted low when wake events is non-zero */
@@ -142,7 +140,6 @@ static uint8_t *lpc_get_hostcmd_data_range(void)
 	return mem_mapped;
 }
 
-
 /**
  * Update the host event status.
  *
@@ -182,7 +179,7 @@ void lpc_update_host_event_status(void)
 
 	/* Copy host events to mapped memory */
 	*(uint32_t *)host_get_memmap(EC_MEMMAP_HOST_EVENTS) =
-			lpc_get_host_events();
+		lpc_get_host_events();
 
 	task_enable_irq(MCHP_IRQ_ACPIEC0_IBF);
 
@@ -216,22 +213,20 @@ static void lpc_send_response(struct host_cmd_handler_args *args)
 	}
 
 	/* New-style response */
-	lpc_host_args->flags =
-		(host_cmd_flags & ~EC_HOST_ARGS_FLAG_FROM_HOST) |
-			EC_HOST_ARGS_FLAG_TO_HOST;
+	lpc_host_args->flags = (host_cmd_flags & ~EC_HOST_ARGS_FLAG_FROM_HOST) |
+			       EC_HOST_ARGS_FLAG_TO_HOST;
 
 	lpc_host_args->data_size = size;
 
 	csum = args->command + lpc_host_args->flags +
-			lpc_host_args->command_version +
-			lpc_host_args->data_size;
+	       lpc_host_args->command_version + lpc_host_args->data_size;
 
 	for (i = 0, out = (uint8_t *)args->response; i < size; i++, out++)
 		csum += *out;
 
 	lpc_host_args->checksum = (uint8_t)csum;
 
-	/* Fail if response doesn't fit in the param buffer */
+	/* Fail if response doesn't fit in the parameter buffer */
 	if (size > EC_PROTO2_MAX_PARAM_SIZE)
 		args->result = EC_RES_INVALID_RESPONSE;
 
@@ -240,12 +235,10 @@ static void lpc_send_response(struct host_cmd_handler_args *args)
 
 	/*
 	 * Clear processing flag in hardware and
-         * sticky status in interrupt aggregator.
+	 * sticky status in interrupt aggregator.
 	 */
 	MCHP_ACPI_EC_STATUS(1) &= ~EC_LPC_STATUS_PROCESSING;
-	MCHP_INT_SOURCE(MCHP_ACPI_EC_GIRQ) =
-				MCHP_ACPI_EC_IBF_GIRQ_BIT(1);
-
+	MCHP_INT_SOURCE(MCHP_ACPI_EC_GIRQ) = MCHP_ACPI_EC_IBF_GIRQ_BIT(1);
 }
 
 static void lpc_send_response_packet(struct host_packet *pkt)
@@ -265,8 +258,7 @@ static void lpc_send_response_packet(struct host_packet *pkt)
 
 	/* Clear the busy bit, so the host knows the EC is done. */
 	MCHP_ACPI_EC_STATUS(1) &= ~EC_LPC_STATUS_PROCESSING;
-	MCHP_INT_SOURCE(MCHP_ACPI_EC_GIRQ) =
-				MCHP_ACPI_EC_IBF_GIRQ_BIT(1);
+	MCHP_INT_SOURCE(MCHP_ACPI_EC_GIRQ) = MCHP_ACPI_EC_IBF_GIRQ_BIT(1);
 }
 
 uint8_t *lpc_get_memmap_range(void)
@@ -276,57 +268,60 @@ uint8_t *lpc_get_memmap_range(void)
 
 void lpc_mem_mapped_init(void)
 {
-	/* We support LPC args and version 3 protocol */
+	/* We support LPC arguments and version 3 protocol */
 	*(lpc_get_memmap_range() + EC_MEMMAP_HOST_CMD_FLAGS) =
 		EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED |
 		EC_HOST_CMD_FLAG_VERSION_3;
 }
 
-const int acpi_ec_pcr_slp[MCHP_ACPI_EC_MAX] = {
-	MCHP_PCR_ACPI_EC0,
-	MCHP_PCR_ACPI_EC1,
-	MCHP_PCR_ACPI_EC2,
-	MCHP_PCR_ACPI_EC3,
+const int acpi_ec_pcr_slp[] = {
+	MCHP_PCR_ACPI_EC0, MCHP_PCR_ACPI_EC1,
+	MCHP_PCR_ACPI_EC2, MCHP_PCR_ACPI_EC3,
+#ifndef CHIP_FAMILY_MEC152X
 	MCHP_PCR_ACPI_EC4,
+#endif
 };
+BUILD_ASSERT(ARRAY_SIZE(acpi_ec_pcr_slp) == MCHP_ACPI_EC_INSTANCES);
 
-const int acpi_ec_nvic_ibf[MCHP_ACPI_EC_MAX] = {
-	MCHP_IRQ_ACPIEC0_IBF,
-	MCHP_IRQ_ACPIEC1_IBF,
-	MCHP_IRQ_ACPIEC2_IBF,
-	MCHP_IRQ_ACPIEC3_IBF,
+const int acpi_ec_nvic_ibf[] = {
+	MCHP_IRQ_ACPIEC0_IBF, MCHP_IRQ_ACPIEC1_IBF,
+	MCHP_IRQ_ACPIEC2_IBF, MCHP_IRQ_ACPIEC3_IBF,
+#ifndef CHIP_FAMILY_MEC152X
 	MCHP_IRQ_ACPIEC4_IBF,
+#endif
 };
+BUILD_ASSERT(ARRAY_SIZE(acpi_ec_nvic_ibf) == MCHP_ACPI_EC_INSTANCES);
 
-#ifdef CONFIG_HOSTCMD_ESPI
-const int acpi_ec_espi_bar_id[MCHP_ACPI_EC_MAX] = {
-	MCHP_ESPI_IO_BAR_ID_ACPI_EC0,
-	MCHP_ESPI_IO_BAR_ID_ACPI_EC1,
-	MCHP_ESPI_IO_BAR_ID_ACPI_EC2,
-	MCHP_ESPI_IO_BAR_ID_ACPI_EC3,
+#ifdef CONFIG_HOST_INTERFACE_ESPI
+const int acpi_ec_espi_bar_id[] = {
+	MCHP_ESPI_IO_BAR_ID_ACPI_EC0, MCHP_ESPI_IO_BAR_ID_ACPI_EC1,
+	MCHP_ESPI_IO_BAR_ID_ACPI_EC2, MCHP_ESPI_IO_BAR_ID_ACPI_EC3,
+#ifndef CHIP_FAMILY_MEC152X
 	MCHP_ESPI_IO_BAR_ID_ACPI_EC4,
+#endif
 };
+BUILD_ASSERT(ARRAY_SIZE(acpi_ec_espi_bar_id) == MCHP_ACPI_EC_INSTANCES);
 #endif
 
 void chip_acpi_ec_config(int instance, uint32_t io_base, uint8_t mask)
 {
-	if (instance >= MCHP_ACPI_EC_MAX)
+	if (instance >= MCHP_ACPI_EC_INSTANCES) {
 		CPUTS("ACPI EC CFG invalid");
+		return;
+	}
 
 	MCHP_PCR_SLP_DIS_DEV(acpi_ec_pcr_slp[instance]);
 
-#ifdef CONFIG_HOSTCMD_ESPI
-	MCHP_ESPI_IO_BAR_CTL_MASK(acpi_ec_espi_bar_id[instance]) =
-			mask;
+#ifdef CONFIG_HOST_INTERFACE_ESPI
+	MCHP_ESPI_IO_BAR_CTL_MASK(acpi_ec_espi_bar_id[instance]) = mask;
 	MCHP_ESPI_IO_BAR(acpi_ec_espi_bar_id[instance]) =
-			(io_base << 16) + 0x01ul;
+		(io_base << 16) + 0x01ul;
 #else
-	MCHP_LPC_ACPI_EC_BAR(instance) = (io_base << 16) +
-		(1ul << 15) + mask;
+	MCHP_LPC_ACPI_EC_BAR(instance) = (io_base << 16) + (1ul << 15) + mask;
 #endif
 	MCHP_ACPI_EC_STATUS(instance) &= ~EC_LPC_STATUS_PROCESSING;
 	MCHP_INT_ENABLE(MCHP_ACPI_EC_GIRQ) =
-			MCHP_ACPI_EC_IBF_GIRQ_BIT(instance);
+		MCHP_ACPI_EC_IBF_GIRQ_BIT(instance);
 	task_enable_irq(acpi_ec_nvic_ibf[instance]);
 }
 
@@ -339,21 +334,20 @@ void chip_8042_config(uint32_t io_base)
 {
 	MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_8042);
 
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	MCHP_ESPI_IO_BAR_CTL_MASK(MCHP_ESPI_IO_BAR_ID_8042) = 0x04;
-	MCHP_ESPI_IO_BAR(MCHP_ESPI_IO_BAR_ID_8042) =
-			(io_base << 16) + 0x01ul;
+	MCHP_ESPI_IO_BAR(MCHP_ESPI_IO_BAR_ID_8042) = (io_base << 16) + 0x01ul;
 #else
 	/* Set up 8042 interface at 0x60/0x64 */
 	MCHP_LPC_8042_BAR = (io_base << 16) + (1ul << 15);
 #endif
-	/* Set up indication of Auxiliary sts */
+	/* Set up indication of Auxiliary status */
 	MCHP_8042_KB_CTRL |= BIT(7);
 
 	MCHP_8042_ACT |= 1;
 
-	MCHP_INT_ENABLE(MCHP_8042_GIRQ) = MCHP_8042_OBE_GIRQ_BIT +
-			MCHP_8042_IBF_GIRQ_BIT;
+	MCHP_INT_ENABLE(MCHP_8042_GIRQ) =
+		MCHP_8042_OBE_GIRQ_BIT + MCHP_8042_IBF_GIRQ_BIT;
 
 	task_enable_irq(MCHP_IRQ_8042EM_IBF);
 	task_enable_irq(MCHP_IRQ_8042EM_OBE);
@@ -361,8 +355,13 @@ void chip_8042_config(uint32_t io_base)
 #ifndef CONFIG_KEYBOARD_IRQ_GPIO
 	/* Set up SERIRQ for keyboard */
 	MCHP_8042_KB_CTRL |= BIT(5);
+#ifdef CONFIG_HOST_INTERFACE_ESPI
+	/* Delivery 8042 keyboard interrupt as IRQ1 using eSPI SERIRQ */
+	MCHP_ESPI_IO_SERIRQ_REG(MCHP_ESPI_SIRQ_8042_KB) = 1;
+#else
 	MCHP_LPC_SIRQ(1) = 0x01;
 #endif
+#endif
 }
 
 /*
@@ -371,15 +370,14 @@ void chip_8042_config(uint32_t io_base)
  * in SRAM. EMI hardware adds 16-bit offset Host programs into
  * EC_Address_LSB/MSB registers.
  * Limit EMI read / write range. First 256 bytes are RW for host
- * commands. Second 256 bytes are RO for mem-mapped data.
+ * commands. Second 256 bytes are RO for memory-mapped data.
  * Hardware decodes a fixed 16 byte IO range.
  */
 void chip_emi0_config(uint32_t io_base)
 {
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	MCHP_ESPI_IO_BAR_CTL_MASK(MCHP_ESPI_IO_BAR_ID_EMI0) = 0x0F;
-	MCHP_ESPI_IO_BAR(MCHP_ESPI_IO_BAR_ID_EMI0) =
-			(io_base << 16) + 0x01ul;
+	MCHP_ESPI_IO_BAR(MCHP_ESPI_IO_BAR_ID_EMI0) = (io_base << 16) + 0x01ul;
 #else
 	MCHP_LPC_EMI0_BAR = (io_base << 16) + (1ul << 15);
 #endif
@@ -393,35 +391,53 @@ void chip_emi0_config(uint32_t io_base)
 	task_enable_irq(MCHP_IRQ_EMI0);
 }
 
-/* Setup Port80 Debug Hardware ports.
+/* Setup Port 80 Debug Hardware ports.
  * First instance for I/O 80h only.
- * Clear FIFO's and timestamp.
+ * Clear FIFO's and time stamp.
  * Set FIFO interrupt threshold to maximum of 14 bytes.
  */
+#if defined(CHIP_FAMILY_MEC172X)
+void chip_port80_config(uint32_t io_base)
+{
+	MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_BDP0);
+
+	/* reset, configure, and enable */
+	MCHP_BDP0_CONFIG = MCHP_BDP_CFG_SRST;
+	MCHP_BDP0_CONFIG = MCHP_BDP_CFG_FIFO_THRH_28;
+	MCHP_BDP0_INTR_EN = MCHP_BDP_IEN_THRH;
+	MCHP_BDP0_ACTV = 1;
+
+	MCHP_INT_SOURCE(15) = MCHP_INT15_BDP0;
+	MCHP_INT_ENABLE(15) = MCHP_INT15_BDP0;
+	task_enable_irq(MCHP_IRQ_BDP0);
+
+	/* Last: Enable Host access via eSPI IO BAR */
+	MCHP_ESPI_IO_BAR_CTL_MASK(MCHP_ESPI_IO_BAR_BDP0) = 0x00;
+	MCHP_ESPI_IO_BAR(MCHP_ESPI_IO_BAR_BDP0) = (io_base << 16) + 0x01ul;
+}
+#else
 void chip_port80_config(uint32_t io_base)
 {
 	MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_P80CAP0);
 
-	MCHP_P80_CFG(0) = MCHP_P80_FLUSH_FIFO_WO +
-			MCHP_P80_RESET_TIMESTAMP_WO;
+	MCHP_P80_CFG(0) = MCHP_P80_FLUSH_FIFO_WO + MCHP_P80_RESET_TIMESTAMP_WO;
 
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	MCHP_ESPI_IO_BAR_CTL_MASK(MCHP_ESPI_IO_BAR_P80_0) = 0x00;
-	MCHP_ESPI_IO_BAR(MCHP_ESPI_IO_BAR_P80_0) =
-			(io_base << 16) + 0x01ul;
+	MCHP_ESPI_IO_BAR(MCHP_ESPI_IO_BAR_P80_0) = (io_base << 16) + 0x01ul;
 #else
 	MCHP_LPC_P80DBG0_BAR = (io_base << 16) + (1ul << 15);
 #endif
-	MCHP_P80_CFG(0) = MCHP_P80_FIFO_THRHOLD_14 +
-			MCHP_P80_TIMEBASE_1500KHZ +
-			MCHP_P80_TIMER_ENABLE;
+	MCHP_P80_CFG(0) = MCHP_P80_FIFO_THRHOLD_14 + MCHP_P80_TIMEBASE_1500KHZ +
+			  MCHP_P80_TIMER_ENABLE;
 
 	MCHP_P80_ACTIVATE(0) = 1;
 
-	MCHP_INT_SOURCE(15) = MCHP_INT15_P80(0);
-	MCHP_INT_ENABLE(15) = MCHP_INT15_P80(0);
+	MCHP_INT_SOURCE(15) = MCHP_P80_GIRQ_BIT(0);
+	MCHP_INT_ENABLE(15) = MCHP_P80_GIRQ_BIT(0);
 	task_enable_irq(MCHP_IRQ_PORT80DBG0);
 }
+#endif
 
 #ifdef CONFIG_MCHP_DEBUG_LPC
 static void chip_lpc_iobar_debug(void)
@@ -438,19 +454,17 @@ static void chip_lpc_iobar_debug(void)
  * Most registers in LPC module are reset when the host is off.
  * We need to set up LPC again when the host is starting up.
  * MCHP LRESET# can be one of two pins
- *	GPIO_0052 Func 2
- *	GPIO_0064 Func 1
+ *	GPIO_0052 Function 2
+ *	GPIO_0064 Function 1
  * Use GPIO interrupt to detect LRESET# changes.
  * Use GPIO_0064 for LRESET#. Must update board/board_name/gpio.inc
  *
  * For eSPI PLATFORM_RESET# virtual wire is used as LRESET#
  *
  */
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
 static void setup_lpc(void)
 {
-	TRACE0(55, LPC, 0, "setup_lpc");
-
 	MCHP_LPC_CFG_BAR |= (1ul << 15);
 
 	/* Set up ACPI0 for 0x62/0x66 */
@@ -501,18 +515,15 @@ static void lpc_init(void)
 	/*
 	 * Clear PCR sleep enables for peripherals we are using for
 	 * both LPC and eSPI.
-	 * Global Config, ACPI EC0/1, 8042 Keyboard controller,
-	 * Port80 Capture0, and EMI.
+	 * Global Configuration, ACPI EC0/1, 8042 Keyboard controller.
 	 * NOTE: EMI doesn't have a sleep enable.
 	 */
 	MCHP_PCR_SLP_DIS_DEV_MASK(2, MCHP_PCR_SLP_EN2_GCFG +
-		MCHP_PCR_SLP_EN2_ACPI_EC0 +
-		MCHP_PCR_SLP_EN2_ACPI_EC0 +
-		MCHP_PCR_SLP_EN2_MIF8042);
-
-	MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_P80CAP0);
+					     MCHP_PCR_SLP_EN2_ACPI_EC0 +
+					     MCHP_PCR_SLP_EN2_ACPI_EC0 +
+					     MCHP_PCR_SLP_EN2_MIF8042);
 
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 
 	espi_init();
 
@@ -541,8 +552,7 @@ static void lpc_init(void)
 	 * clock stop and there are no pending SERIRQ
 	 * or LPC DMA.
 	 */
-	MCHP_LPC_EC_CLK_CTRL =
-		(MCHP_LPC_EC_CLK_CTRL & ~(0x03ul)) | 0x01ul;
+	MCHP_LPC_EC_CLK_CTRL = (MCHP_LPC_EC_CLK_CTRL & ~(0x03ul)) | 0x01ul;
 
 	setup_lpc();
 #endif
@@ -588,8 +598,8 @@ void lpc_set_init_done(int val)
  */
 void lpcrst_interrupt(enum gpio_signal signal)
 {
-#ifndef CONFIG_HOSTCMD_ESPI
-	/* Initialize LPC module when LRESET# is deasserted */
+#ifndef CONFIG_HOST_INTERFACE_ESPI
+	/* Initialize LPC module when LRESET# is de-asserted */
 	if (!lpc_get_pltrst_asserted()) {
 		setup_lpc();
 	} else {
@@ -602,8 +612,7 @@ void lpcrst_interrupt(enum gpio_signal signal)
 #endif
 	}
 #ifdef CONFIG_MCHP_DEBUG_LPC
-	CPRINTS("LPC RESET# %sasserted",
-		lpc_get_pltrst_asserted() ? "" : "de");
+	CPRINTS("LPC RESET# %sasserted", lpc_get_pltrst_asserted() ? "" : "de");
 #endif
 #endif
 }
@@ -613,7 +622,7 @@ void lpcrst_interrupt(enum gpio_signal signal)
  * or logging of EMI host communication? We don't observe
  * this ISR so Host is not writing to MCHP_EMI_H2E_MBX(0).
  */
-void emi0_interrupt(void)
+static void emi0_interrupt(void)
 {
 	uint8_t h2e;
 
@@ -627,14 +636,24 @@ DECLARE_IRQ(MCHP_IRQ_EMI0, emi0_interrupt, 1);
  * ISR empties BIOS Debug 0 FIFO and
  * writes data to circular buffer. How can we be
  * sure this routine can read the last Port 80h byte?
+ * MEC172x BDP capture data is different. It returns a
+ * 16-bit value where bits [7:0] are the data and bits [15:7]
+ * are flags indicating if the data is part of a multi-byte
+ * write sequence by the host and read-only FIFO status bits.
+ * The capture HW in previous chips included an optional time
+ * stamp in bits[31:8] of the data register.
  */
 int port_80_read(void)
 {
-	int data;
+	int data = PORT_80_IGNORE;
 
-	data = PORT_80_IGNORE;
+#if defined(CHIP_FAMILY_MEC172X)
+	if (MCHP_BDP0_STATUS & MCHP_BDP_STATUS_NOT_EMPTY)
+		data = MCHP_BDP0_DATTR & 0xFFU;
+#else
 	if (MCHP_P80_STS(0) & MCHP_P80_STS_NOT_EMPTY)
 		data = MCHP_P80_CAP(0) & 0xFF;
+#endif
 
 	return data;
 }
@@ -642,11 +661,10 @@ int port_80_read(void)
 #ifdef CONFIG_BOARD_ID_CMD_ACPI_EC1
 /*
  * Handle custom ACPI EC0 commands.
- * Some chipset's CoreBoot will send read board ID command expecting
+ * Some chipset CoreBoot will send read board ID command expecting
  * a two byte response.
  */
-static int acpi_ec0_custom(int is_cmd, uint8_t value,
-		uint8_t *resultptr)
+static int acpi_ec0_custom(int is_cmd, uint8_t value, uint8_t *resultptr)
 {
 	int rval;
 
@@ -656,7 +674,7 @@ static int acpi_ec0_custom(int is_cmd, uint8_t value,
 
 	if (is_cmd && (value == 0x0d)) {
 		MCHP_INT_SOURCE(MCHP_ACPI_EC_GIRQ) =
-				MCHP_ACPI_EC_OBE_GIRQ_BIT(0);
+			MCHP_ACPI_EC_OBE_GIRQ_BIT(0);
 		/* Write two bytes sequence 0xC2, 0x04 to Host */
 		if (MCHP_ACPI_EC_BYTE_CTL(0) & 0x01) {
 			/* Host enabled 4-byte mode */
@@ -672,7 +690,7 @@ static int acpi_ec0_custom(int is_cmd, uint8_t value,
 			custom_apci_ec2os[0] = 0x04;
 			MCHP_ACPI_EC_EC2OS(0, 0) = 0x02;
 			MCHP_INT_ENABLE(MCHP_ACPI_EC_GIRQ) =
-					MCHP_ACPI_EC_OBE_GIRQ_BIT(0);
+				MCHP_ACPI_EC_OBE_GIRQ_BIT(0);
 			task_enable_irq(MCHP_IRQ_ACPIEC0_OBE);
 		}
 		custom_acpi_cmd = 0;
@@ -683,7 +701,7 @@ static int acpi_ec0_custom(int is_cmd, uint8_t value,
 }
 #endif
 
-void acpi_0_interrupt(void)
+static void acpi_0_interrupt(void)
 {
 	uint8_t value, result, is_cmd;
 
@@ -711,8 +729,7 @@ void acpi_0_interrupt(void)
 	MCHP_ACPI_EC_STATUS(0) &= ~EC_LPC_STATUS_PROCESSING;
 
 	/* Clear R/W1C status bit in Aggregator */
-	MCHP_INT_SOURCE(MCHP_ACPI_EC_GIRQ) =
-			MCHP_ACPI_EC_IBF_GIRQ_BIT(0);
+	MCHP_INT_SOURCE(MCHP_ACPI_EC_GIRQ) = MCHP_ACPI_EC_IBF_GIRQ_BIT(0);
 
 	/*
 	 * ACPI 5.0-12.6.1: Generate SCI for Input Buffer Empty /
@@ -728,12 +745,11 @@ DECLARE_IRQ(MCHP_IRQ_ACPIEC0_IBF, acpi_0_interrupt, 1);
  * Used to handle custom ACPI EC0 command requiring
  * two byte response.
  */
-void acpi_0_obe_isr(void)
+static void acpi_0_obe_isr(void)
 {
 	uint8_t sts, data;
 
-	MCHP_INT_SOURCE(MCHP_ACPI_EC_GIRQ) =
-			MCHP_ACPI_EC_OBE_GIRQ_BIT(0);
+	MCHP_INT_SOURCE(MCHP_ACPI_EC_GIRQ) = MCHP_ACPI_EC_OBE_GIRQ_BIT(0);
 
 	sts = MCHP_ACPI_EC_STATUS(0);
 	data = MCHP_ACPI_EC_BYTE_CTL(0);
@@ -745,7 +761,7 @@ void acpi_0_obe_isr(void)
 
 	if (custom_acpi_ec2os_cnt == 0) { /* was last byte? */
 		MCHP_INT_DISABLE(MCHP_ACPI_EC_GIRQ) =
-				MCHP_ACPI_EC_OBE_GIRQ_BIT(0);
+			MCHP_ACPI_EC_OBE_GIRQ_BIT(0);
 	}
 
 	lpc_generate_sci();
@@ -753,12 +769,11 @@ void acpi_0_obe_isr(void)
 DECLARE_IRQ(MCHP_IRQ_ACPIEC0_OBE, acpi_0_obe_isr, 1);
 #endif
 
-void acpi_1_interrupt(void)
+static void acpi_1_interrupt(void)
 {
 	uint8_t st = MCHP_ACPI_EC_STATUS(1);
 
-	if (!(st & EC_LPC_STATUS_FROM_HOST) ||
-	    !(st & EC_LPC_STATUS_LAST_CMD))
+	if (!(st & EC_LPC_STATUS_FROM_HOST) || !(st & EC_LPC_STATUS_LAST_CMD))
 		return;
 
 	/* Set the busy bit */
@@ -778,8 +793,7 @@ void acpi_1_interrupt(void)
 	if (host_cmd_args.command == EC_COMMAND_PROTOCOL_3) {
 		lpc_packet.send_response = lpc_send_response_packet;
 
-		lpc_packet.request =
-			(const void *)lpc_get_hostcmd_data_range();
+		lpc_packet.request = (const void *)lpc_get_hostcmd_data_range();
 		lpc_packet.request_temp = params_copy;
 		lpc_packet.request_max = sizeof(params_copy);
 		/* Don't know the request size so
@@ -787,8 +801,7 @@ void acpi_1_interrupt(void)
 		 */
 		lpc_packet.request_size = EC_LPC_HOST_PACKET_SIZE;
 
-		lpc_packet.response =
-			(void *)lpc_get_hostcmd_data_range();
+		lpc_packet.response = (void *)lpc_get_hostcmd_data_range();
 		lpc_packet.response_max = EC_LPC_HOST_PACKET_SIZE;
 		lpc_packet.response_size = 0;
 
@@ -811,11 +824,10 @@ DECLARE_IRQ(MCHP_IRQ_ACPIEC1_IBF, acpi_1_interrupt, 1);
  * Reading data out of input buffer clears read-only status
  * in 8042EM. Next, we must clear aggregator status.
  */
-void kb_ibf_interrupt(void)
+static void kb_ibf_interrupt(void)
 {
 	if (lpc_keyboard_input_pending())
-		keyboard_host_write(MCHP_8042_H2E,
-				    MCHP_8042_STS & BIT(3));
+		keyboard_host_write(MCHP_8042_H2E, MCHP_8042_STS & BIT(3));
 
 	MCHP_INT_SOURCE(MCHP_8042_GIRQ) = MCHP_8042_IBF_GIRQ_BIT;
 	task_wake(TASK_ID_KEYPROTO);
@@ -829,7 +841,7 @@ DECLARE_IRQ(MCHP_IRQ_8042EM_IBF, kb_ibf_interrupt, 1);
  * aggregator. Clear aggregator 8042EM OBE R/WC status bit before
  * invoking task.
  */
-void kb_obe_interrupt(void)
+static void kb_obe_interrupt(void)
 {
 	MCHP_INT_SOURCE(MCHP_8042_GIRQ) = MCHP_8042_OBE_GIRQ_BIT;
 	task_wake(TASK_ID_KEYPROTO);
@@ -898,10 +910,10 @@ void lpc_clear_acpi_status_mask(uint8_t mask)
  */
 int lpc_get_pltrst_asserted(void)
 {
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	/*
 	 * eSPI PLTRST# a VWire or side-band signal
-	 * Controlled by CONFIG_HOSTCMD_ESPI
+	 * Controlled by CONFIG_HOST_INTERFACE_ESPI
 	 */
 	return !espi_vw_get_wire(VW_PLTRST_L);
 #else
@@ -911,7 +923,7 @@ int lpc_get_pltrst_asserted(void)
 	return !gpio_get_level(GPIO_PCH_PLTRST_L);
 #else
 	/* assumes LPC clock is running when host changes LRESET# */
-	return (MCHP_LPC_BUS_MONITOR & (1<<1)) ? 1 : 0;
+	return (MCHP_LPC_BUS_MONITOR & (1 << 1)) ? 1 : 0;
 #endif
 #endif
 }
@@ -929,7 +941,7 @@ void lpc_disable_acpi_interrupts(void)
 }
 
 /* On boards without a host, this command is used to set up LPC */
-static int lpc_command_init(int argc, char **argv)
+static int lpc_command_init(int argc, const char **argv)
 {
 	lpc_init();
 	return EC_SUCCESS;
@@ -951,14 +963,13 @@ static enum ec_status lpc_get_protocol_info(struct host_cmd_handler_args *args)
 
 	args->response_size = sizeof(*r);
 
-	return EC_SUCCESS;
+	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO,
-		lpc_get_protocol_info,
-		EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, lpc_get_protocol_info,
+		     EC_VER_MASK(0));
 
 #ifdef CONFIG_MCHP_DEBUG_LPC
-static int command_lpc(int argc, char **argv)
+static int command_lpc(int argc, const char **argv)
 {
 	if (argc == 1)
 		return EC_ERROR_PARAM1;
@@ -973,7 +984,5 @@ static int command_lpc(int argc, char **argv)
 		return EC_ERROR_PARAM1;
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(lpc, command_lpc, "[sci|smi|wake]",
-	"Trigger SCI/SMI");
+DECLARE_CONSOLE_COMMAND(lpc, command_lpc, "[sci|smi|wake]", "Trigger SCI/SMI");
 #endif
-
diff --git a/chip/mchp/lpc_chip.h b/chip/mchp/lpc_chip.h
index dcb5577fc1..7d9965f156 100644
--- a/chip/mchp/lpc_chip.h
+++ b/chip/mchp/lpc_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,11 +8,11 @@
 #ifndef __CROS_EC_LPC_CHIP_H
 #define __CROS_EC_LPC_CHIP_H
 
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 
 #include "espi.h"
 
-#define MCHP_HOST_IF_LPC  (0)
+#define MCHP_HOST_IF_LPC (0)
 #define MCHP_HOST_IF_ESPI (1)
 
 /* eSPI Initialization functions */
@@ -37,7 +37,7 @@ void lpc_set_init_done(int val);
 
 void lpc_mem_mapped_init(void);
 
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
 void lpcrst_interrupt(enum gpio_signal signal);
 #endif
 
diff --git a/chip/mchp/port80.c b/chip/mchp/port80.c
index 8be91e9d3d..57ceaac8fa 100644
--- a/chip/mchp/port80.c
+++ b/chip/mchp/port80.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,16 +14,43 @@
 #include "task.h"
 #include "tfdp_chip.h"
 
+#if defined(CHIP_FAMILY_MEC172X)
+/*
+ * MEC172x family implements a new Port 0x80 capture block.
+ * The BDP HW can capture 8, 16, and 32 bit writes.
+ * Interrupt fires when BDP FIFO threshold is reached.
+ * Data can be read from a 16-bit register containing:
+ * b[7:0] data byte
+ * b[9:8] = byte lane
+ * b[11:10]= flags indicating current byte is a single byte or part of
+ * a multi-byte sequence.
+ * b[14:12] = copy of bits[2:0] of the status register
+ * b[15] = 0 reserved
+ * NOTE: The overrun bit could be used to set a flag indicating EC could
+ * not keep up with the host.
+ */
+static void port_80_interrupt(void)
+{
+	int d = MCHP_BDP0_DATTR;
+
+	while (d & MCHP_BDP_DATTR_NE) {
+		port_80_write(d & 0xffU);
+		d = MCHP_BDP0_DATTR;
+	}
 
+	MCHP_INT_SOURCE(MCHP_BDP0_GIRQ) = MCHP_BDP0_GIRQ_BIT;
+}
+DECLARE_IRQ(MCHP_IRQ_BDP0, port_80_interrupt, 3);
+#else
 /*
  * Interrupt fires when number of bytes written
  * to eSPI/LPC I/O 80h-81h exceeds Por80_0 FIFO level
  * Issues:
  * 1. eSPI will not break 16-bit I/O into two 8-bit writes
- *    as LPC does. This means Port80 hardware will capture
+ *    as LPC does. This means Port 80h hardware will capture
  *    only bits[7:0] of data.
  * 2. If Host performs write of 16-bit code as consecutive
- *    byte writes the Port80 hardware will capture both but
+ *    byte writes the Port 80h hardware will capture both but
  *    we do not know the order it was written.
  * 3. If Host sometimes writes one byte code to I/O 80h and
  *    sometimes two byte code to I/O 80h/81h how do we determine
@@ -33,13 +60,16 @@
  * to I/O 80h and 90h.  LSB to 0x80 and MSB to 0x90.
  *
  */
-void port_80_interrupt(void)
+static void port_80_interrupt(void)
 {
 	int d;
 
 	while (MCHP_P80_STS(0) & MCHP_P80_STS_NOT_EMPTY) {
-		/* this masks off time stamp d = port_80_read(); */
-		d = MCHP_P80_CAP(0);	/* b[7:0] = data, b[31:8] = timestamp */
+		/*
+		 * This masks off time stamp d = port_80_read();
+		 * b[7:0] = data, b[32:8] = time stamp
+		 */
+		d = MCHP_P80_CAP(0);
 		trace1(0, P80, 0, "Port80h = 0x%02x", (d & 0xff));
 		port_80_write(d & 0xff);
 	}
@@ -47,5 +77,4 @@ void port_80_interrupt(void)
 	MCHP_INT_SOURCE(MCHP_P80_GIRQ) = MCHP_P80_GIRQ_BIT(0);
 }
 DECLARE_IRQ(MCHP_IRQ_PORT80DBG0, port_80_interrupt, 3);
-
-
+#endif
diff --git a/chip/mchp/pwm.c b/chip/mchp/pwm.c
index 53a8c15806..706228fa53 100644
--- a/chip/mchp/pwm.c
+++ b/chip/mchp/pwm.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,53 +12,34 @@
 #include "pwm.h"
 #include "pwm_chip.h"
 #include "registers.h"
-#include "util.h"
 #include "tfdp_chip.h"
+#include "util.h"
 
 #define CPUTS(outstr) cputs(CC_PWM, outstr)
-#define CPRINTS(format, args...) cprints(CC_PWM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_PWM, format, ##args)
 
-/*
- * PWMs that must remain active in low-power idle -
- * PWM 0,1-8 are b[4,20:27] of MCHP_PCR_SLP_EN1
- * PWM 9 is b[31] of MCHP_PCR_SLP_EN3
- * PWM 10 - 11 are b[0:1] of MCHP_PCR_SLP_EN4
- * store 32-bit word with
- * b[0:1] = PWM 10-11
- * b[4,20:27] = PWM 0, 1-8
- * b[31] = PWM 9
- */
+/* Bit map of PWM channels that must remain active during low power idle. */
 static uint32_t pwm_keep_awake_mask;
 
-const uint8_t pwm_slp_bitpos[12] = {
-	4, 20, 21, 22, 23, 24, 25, 26, 27, 31, 0, 1
+/* Table of PWM PCR sleep enable register index and bit position. */
+static const uint16_t pwm_pcr[] = {
+	MCHP_PCR_PWM0, MCHP_PCR_PWM1, MCHP_PCR_PWM2,
+	MCHP_PCR_PWM3, MCHP_PCR_PWM4, MCHP_PCR_PWM5,
+	MCHP_PCR_PWM6, MCHP_PCR_PWM7, MCHP_PCR_PWM8,
 };
-
-static uint32_t pwm_get_sleep_mask(int id)
-{
-	uint32_t bitpos = 32;
-
-	if (id < 12)
-		bitpos = (uint32_t)pwm_slp_bitpos[id];
-
-	return (1ul << bitpos);
-}
-
+BUILD_ASSERT(ARRAY_SIZE(pwm_pcr) == MCHP_PWM_ID_MAX);
 
 void pwm_enable(enum pwm_channel ch, int enabled)
 {
 	int id = pwm_channels[ch].channel;
-	uint32_t pwm_slp_mask;
-
-	pwm_slp_mask = pwm_get_sleep_mask(id);
 
 	if (enabled) {
-		MCHP_PWM_CFG(id) |= 0x1;
+		MCHP_PWM_CFG(id) |= BIT(0);
 		if (pwm_channels[ch].flags & PWM_CONFIG_DSLEEP)
-			pwm_keep_awake_mask |= pwm_slp_mask;
+			pwm_keep_awake_mask |= BIT(id);
 	} else {
-		MCHP_PWM_CFG(id) &= ~0x1;
-		pwm_keep_awake_mask &= ~pwm_slp_mask;
+		MCHP_PWM_CFG(id) &= ~BIT(0);
+		pwm_keep_awake_mask &= ~BIT(id);
 	}
 }
 
@@ -88,47 +69,25 @@ int pwm_get_duty(enum pwm_channel ch)
 void pwm_keep_awake(void)
 {
 	if (pwm_keep_awake_mask) {
-		/* b[4,20:27] */
-		MCHP_PCR_SLP_EN1 &= ~(pwm_keep_awake_mask &
-					 (MCHP_PCR_SLP_EN1_PWM_ALL));
-		/* b[31] */
-		MCHP_PCR_SLP_EN3 &= ~(pwm_keep_awake_mask &
-					 (MCHP_PCR_SLP_EN3_PWM_ALL));
-		/* b[1:0] */
-		MCHP_PCR_SLP_EN4 &= ~(pwm_keep_awake_mask &
-					 (MCHP_PCR_SLP_EN4_PWM_ALL));
+		for (uint32_t i = 0; i < MCHP_PWM_ID_MAX; i++)
+			if (pwm_keep_awake_mask & BIT(i))
+				MCHP_PCR_SLP_DIS_DEV(pwm_pcr[i]);
 	} else {
-		MCHP_PCR_SLOW_CLK_CTL &= 0xFFFFFC00;
+		MCHP_PCR_SLOW_CLK_CTL &= ~(MCHP_PCR_SLOW_CLK_CTL_MASK);
 	}
 }
 
-
+/*
+ * clock_low=0 selects the 48MHz Ring Oscillator source
+ * clock_low=1 selects the 100kHz_Clk source
+ */
 static void pwm_configure(int ch, int active_low, int clock_low)
 {
-	/*
-	 * clock_low=0 selects the 48MHz Ring Oscillator source
-	 * clock_low=1 selects the 100kHz_Clk source
-	 */
-	MCHP_PWM_CFG(ch) = (15 << 3) |    /* Pre-divider = 16 */
-			      (active_low ? BIT(2) : 0) |
-			      (clock_low  ? BIT(1) : 0);
+	MCHP_PWM_CFG(ch) = (15 << 3) /* divider = 16 */
+			   | (active_low ? BIT(2) : 0) |
+			   (clock_low ? BIT(1) : 0);
 }
 
-static const uint16_t pwm_pcr[MCHP_PWM_ID_MAX] = {
-	MCHP_PCR_PWM0,
-	MCHP_PCR_PWM1,
-	MCHP_PCR_PWM2,
-	MCHP_PCR_PWM3,
-	MCHP_PCR_PWM4,
-	MCHP_PCR_PWM5,
-	MCHP_PCR_PWM6,
-	MCHP_PCR_PWM7,
-	MCHP_PCR_PWM8,
-	MCHP_PCR_PWM9,
-	MCHP_PCR_PWM10,
-	MCHP_PCR_PWM11,
-};
-
 static void pwm_slp_en(int pwm_id, int sleep_en)
 {
 	if ((pwm_id < 0) || (pwm_id > MCHP_PWM_ID_MAX))
diff --git a/chip/mchp/pwm_chip.h b/chip/mchp/pwm_chip.h
index 85ff484f86..848656bb03 100644
--- a/chip/mchp/pwm_chip.h
+++ b/chip/mchp/pwm_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,6 +7,34 @@
 #ifndef __CROS_EC_PWM_CHIP_H
 #define __CROS_EC_PWM_CHIP_H
 
+/*
+ * MEC152x SZ 144-pin has 9 PWM and 4 TACH
+ * MEC170x SZ 144-pin has 9 PWM and 3 TACH
+ * MEC172x SZ 144-pin has 9 PWM and 4 TACH
+ */
+enum pwm_hw_id {
+	PWM_HW_CH_0 = 0,
+	PWM_HW_CH_1,
+	PWM_HW_CH_2,
+	PWM_HW_CH_3,
+	PWM_HW_CH_4,
+	PWM_HW_CH_5,
+	PWM_HW_CH_6,
+	PWM_HW_CH_7,
+	PWM_HW_CH_8,
+	PWM_HW_CH_COUNT
+};
+
+enum tach_hw_id {
+	TACH_HW_CH_0 = 0,
+	TACH_HW_CH_1,
+	TACH_HW_CH_2,
+#ifndef CHIP_FAMILY_MEC170X
+	TACH_HW_CH_3,
+#endif
+	TACH_HW_CH_COUNT
+};
+
 /* Data structure to define PWM channels. */
 struct pwm_t {
 	/* PWM Channel ID */
@@ -20,4 +48,4 @@ extern const struct pwm_t pwm_channels[];
 
 void pwm_keep_awake(void);
 
-#endif  /* __CROS_EC_PWM_CHIP_H */
+#endif /* __CROS_EC_PWM_CHIP_H */
diff --git a/chip/mchp/qmspi.c b/chip/mchp/qmspi.c
index 72eaa91d37..a0d31b72e3 100644
--- a/chip/mchp/qmspi.c
+++ b/chip/mchp/qmspi.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,27 +8,25 @@
 #include "common.h"
 #include "console.h"
 #include "dma.h"
+#include "dma_chip.h"
 #include "gpio.h"
+#include "hooks.h"
+#include "qmspi_chip.h"
 #include "registers.h"
 #include "spi.h"
-#include "timer.h"
-#include "util.h"
-#include "hooks.h"
-#include "task.h"
-#include "dma_chip.h"
 #include "spi_chip.h"
-#include "qmspi_chip.h"
+#include "task.h"
 #include "tfdp_chip.h"
+#include "timer.h"
+#include "util.h"
 
 #define CPUTS(outstr) cputs(CC_SPI, outstr)
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SPI, format, ##args)
 
 #define QMSPI_TRANSFER_TIMEOUT (100 * MSEC)
 #define QMSPI_BYTE_TRANSFER_TIMEOUT_US (3 * MSEC)
 #define QMSPI_BYTE_TRANSFER_POLL_INTERVAL_US 20
 
-
-
 #ifndef CONFIG_MCHP_QMSPI_TX_DMA
 #ifdef LFW
 /*
@@ -137,8 +135,8 @@ static uint32_t qmspi_build_tx_descr(uint32_t ntx, uint32_t ndid)
  * value (1, 2, or 4).
  * Caller will apply close and last flags if applicable.
  */
-static uint64_t qmspi_build_rx_descr(uint32_t raddr,
-		uint32_t nrx, uint32_t ndid)
+static uint64_t qmspi_build_rx_descr(uint32_t raddr, uint32_t nrx,
+				     uint32_t ndid)
 {
 	uint32_t d, dmau, na;
 	uint64_t u;
@@ -182,9 +180,9 @@ static uint64_t qmspi_build_rx_descr(uint32_t raddr,
 
 #ifdef CONFIG_MCHP_QMSPI_TX_DMA
 
-#define QMSPI_ERR_ANY			0x80
-#define QMSPI_ERR_BAD_PTR		0x81
-#define QMSPI_ERR_OUT_OF_DESCR		0x85
+#define QMSPI_ERR_ANY 0x80
+#define QMSPI_ERR_BAD_PTR 0x81
+#define QMSPI_ERR_OUT_OF_DESCR 0x85
 
 /*
  * bits[1:0] of word
@@ -206,9 +204,9 @@ static void qmspi_descr_mode_ready(void)
 	int i;
 
 	MCHP_QMSPI0_CTRL = 0;
-	MCHP_QMSPI0_IEN  = 0;
-	MCHP_QMSPI0_EXE  = MCHP_QMSPI_EXE_CLR_FIFOS;
-	MCHP_QMSPI0_STS  = 0xfffffffful;
+	MCHP_QMSPI0_IEN = 0;
+	MCHP_QMSPI0_EXE = MCHP_QMSPI_EXE_CLR_FIFOS;
+	MCHP_QMSPI0_STS = 0xfffffffful;
 	MCHP_QMSPI0_CTRL = MCHP_QMSPI_C_DESCR_MODE_EN;
 	/* clear all descriptors */
 	for (i = 0; i < MCHP_QMSPI_MAX_DESCR; i++)
@@ -229,8 +227,7 @@ static void qmspi_descr_mode_ready(void)
  * and remaining < 16 bytes in byte unit descriptor until all bytes
  * exhausted or out of descriptors error.
  */
-static uint32_t qmspi_descr_alloc(uint32_t did,
-				uint32_t descr, uint32_t nb)
+static uint32_t qmspi_descr_alloc(uint32_t did, uint32_t descr, uint32_t nb)
 {
 	uint32_t nu;
 
@@ -238,8 +235,8 @@ static uint32_t qmspi_descr_alloc(uint32_t did,
 		if (did >= MCHP_QMSPI_MAX_DESCR)
 			return 0xffff;
 
-		descr &= ~(MCHP_QMSPI_C_NUM_UNITS_MASK +
-			MCHP_QMSPI_C_XFRU_MASK);
+		descr &=
+			~(MCHP_QMSPI_C_NUM_UNITS_MASK + MCHP_QMSPI_C_XFRU_MASK);
 
 		if (nb < (MCHP_QMSPI_C_MAX_UNITS + 1)) {
 			descr |= MCHP_QMSPI_C_XFRU_1B;
@@ -252,7 +249,7 @@ static uint32_t qmspi_descr_alloc(uint32_t did,
 			nb -= (nu << 4);
 		}
 
-		descr |= ((did+1) << MCHP_QMSPI_C_NEXT_DESCR_BITPOS);
+		descr |= ((did + 1) << MCHP_QMSPI_C_NEXT_DESCR_BITPOS);
 		MCHP_QMSPI0_DESCR(did) = descr;
 		if (nb)
 			did++;
@@ -271,9 +268,8 @@ static uint32_t qmspi_descr_alloc(uint32_t did,
  * channel and configure the DMA channel for memory to device transfer.
  */
 static uint32_t qmspi_xmit_data_descr(const struct dma_option *opdma,
-					uint32_t cfg,
-					const uint8_t *data,
-					uint32_t ndata)
+				      uint32_t cfg, const uint8_t *data,
+				      uint32_t ndata)
 {
 	uint32_t d, d2, did, dma_cfg;
 
@@ -282,7 +278,7 @@ static uint32_t qmspi_xmit_data_descr(const struct dma_option *opdma,
 
 	if (ndata <= MCHP_QMSPI_TX_FIFO_LEN) {
 		d2 = d + (ndata << MCHP_QMSPI_C_NUM_UNITS_BITPOS) +
-			MCHP_QMSPI_C_XFRU_1B + MCHP_QMSPI_C_TX_DATA;
+		     MCHP_QMSPI_C_XFRU_1B + MCHP_QMSPI_C_TX_DATA;
 		d2 += ((did + 1) << MCHP_QMSPI_C_NEXT_DESCR_BITPOS);
 		MCHP_QMSPI0_DESCR(did) = d2;
 		while (ndata--)
@@ -290,12 +286,10 @@ static uint32_t qmspi_xmit_data_descr(const struct dma_option *opdma,
 	} else { // TX DMA
 		if (((uint32_t)data | ndata) & 0x03) {
 			dma_cfg = 1;
-			d |= (MCHP_QMSPI_C_TX_DATA +
-				MCHP_QMSPI_C_TX_DMA_1B);
+			d |= (MCHP_QMSPI_C_TX_DATA + MCHP_QMSPI_C_TX_DMA_1B);
 		} else {
 			dma_cfg = 4;
-			d |= (MCHP_QMSPI_C_TX_DATA +
-				MCHP_QMSPI_C_TX_DMA_4B);
+			d |= (MCHP_QMSPI_C_TX_DATA + MCHP_QMSPI_C_TX_DMA_4B);
 		}
 		did = qmspi_descr_alloc(did, d, ndata);
 		if (did == 0xffff)
@@ -303,10 +297,9 @@ static uint32_t qmspi_xmit_data_descr(const struct dma_option *opdma,
 
 		dma_clr_chan(opdma->channel);
 		dma_cfg_buffers(opdma->channel, data, ndata,
-			(void *)MCHP_QMSPI0_TX_FIFO_ADDR);
-		dma_cfg_xfr(opdma->channel, dma_cfg,
-			MCHP_DMA_QMSPI0_TX_REQ_ID,
-			(DMA_FLAG_M2D + DMA_FLAG_INCR_MEM));
+				(void *)MCHP_QMSPI0_TX_FIFO_ADDR);
+		dma_cfg_xfr(opdma->channel, dma_cfg, MCHP_DMA_QMSPI0_TX_REQ_ID,
+			    (DMA_FLAG_M2D + DMA_FLAG_INCR_MEM));
 		dma_run(opdma->channel);
 	}
 
@@ -327,8 +320,8 @@ void qmspi_cfg_irq_start(uint8_t flags)
 	MCHP_QMSPI0_IEN = 0;
 
 	if (flags & (1u << 1)) {
-		MCHP_QMSPI0_IEN = (MCHP_QMSPI_STS_DONE +
-			MCHP_QMSPI_STS_PROG_ERR);
+		MCHP_QMSPI0_IEN =
+			(MCHP_QMSPI_STS_DONE + MCHP_QMSPI_STS_PROG_ERR);
 		MCHP_INT_ENABLE(MCHP_QMSPI_GIRQ) = MCHP_QMSPI_GIRQ_BIT;
 	}
 
@@ -349,10 +342,9 @@ void qmspi_cfg_irq_start(uint8_t flags)
  * returns last descriptor 0 <= index < MCHP_QMSPI_MAX_DESCR
  * or error (bit[7]==1)
  */
-uint8_t qmspi_xfr(const struct spi_device_t *spi_device,
-			uint32_t np_flags,
-			const uint8_t *txdata, uint32_t ntx,
-			uint8_t *rxdata, uint32_t nrx)
+uint8_t qmspi_xfr(const struct spi_device_t *spi_device, uint32_t np_flags,
+		  const uint8_t *txdata, uint32_t ntx, uint8_t *rxdata,
+		  uint32_t nrx)
 {
 	uint32_t d, did, dma_cfg;
 	const struct dma_option *opdma;
@@ -399,10 +391,9 @@ uint8_t qmspi_xfr(const struct spi_device_t *spi_device,
 		opdma = spi_dma_option(spi_device, SPI_DMA_OPTION_RD);
 		dma_clr_chan(opdma->channel);
 		dma_cfg_buffers(opdma->channel, rxdata, nrx,
-			(void *)MCHP_QMSPI0_RX_FIFO_ADDR);
-		dma_cfg_xfr(opdma->channel, dma_cfg,
-			MCHP_DMA_QMSPI0_RX_REQ_ID,
-			(DMA_FLAG_D2M + DMA_FLAG_INCR_MEM));
+				(void *)MCHP_QMSPI0_RX_FIFO_ADDR);
+		dma_cfg_xfr(opdma->channel, dma_cfg, MCHP_DMA_QMSPI0_RX_REQ_ID,
+			    (DMA_FLAG_D2M + DMA_FLAG_INCR_MEM));
 		dma_run(opdma->channel);
 	}
 
@@ -466,8 +457,8 @@ uint8_t qmspi_xfr(const struct spi_device_t *spi_device,
  */
 #ifdef CONFIG_MCHP_QMSPI_TX_DMA
 int qmspi_transaction_async(const struct spi_device_t *spi_device,
-				const uint8_t *txdata, int txlen,
-				uint8_t *rxdata, int rxlen)
+			    const uint8_t *txdata, int txlen, uint8_t *rxdata,
+			    int rxlen)
 {
 	uint32_t np_flags, ntx, nrx;
 	int ret;
@@ -482,9 +473,7 @@ int qmspi_transaction_async(const struct spi_device_t *spi_device,
 		nrx = (uint32_t)rxlen;
 
 	np_flags = 0x010105; /* b[0]=1 close on done, b[2]=1 start */
-	rc = qmspi_xfr(spi_device, np_flags,
-			txdata, ntx,
-			rxdata, nrx);
+	rc = qmspi_xfr(spi_device, np_flags, txdata, ntx, rxdata, nrx);
 
 	if (rc & QMSPI_ERR_ANY)
 		return EC_ERROR_INVAL;
@@ -498,8 +487,8 @@ int qmspi_transaction_async(const struct spi_device_t *spi_device,
  * Receive using DMA as above.
  */
 int qmspi_transaction_async(const struct spi_device_t *spi_device,
-				const uint8_t *txdata, int txlen,
-				uint8_t *rxdata, int rxlen)
+			    const uint8_t *txdata, int txlen, uint8_t *rxdata,
+			    int rxlen)
 {
 	const struct dma_option *opdma;
 	uint32_t d, did, dmau;
@@ -533,8 +522,7 @@ int qmspi_transaction_async(const struct spi_device_t *spi_device,
 		if (rxdata == NULL)
 			return EC_ERROR_PARAM4;
 
-		u = qmspi_build_rx_descr((uint32_t)rxdata,
-				(uint32_t)rxlen, 2);
+		u = qmspi_build_rx_descr((uint32_t)rxdata, (uint32_t)rxlen, 2);
 
 		d = (uint32_t)u;
 		dmau = u >> 32;
@@ -547,16 +535,16 @@ int qmspi_transaction_async(const struct spi_device_t *spi_device,
 		dma_xfr_start_rx(opdma, dmau, (uint32_t)rxlen, rxdata);
 	}
 
-	MCHP_QMSPI0_DESCR(did) |= (MCHP_QMSPI_C_CLOSE +
-			MCHP_QMSPI_C_DESCR_LAST);
+	MCHP_QMSPI0_DESCR(did) |=
+		(MCHP_QMSPI_C_CLOSE + MCHP_QMSPI_C_DESCR_LAST);
 
 	MCHP_QMSPI0_EXE = MCHP_QMSPI_EXE_START;
 
 	while (txlen--) {
 		if (MCHP_QMSPI0_STS & MCHP_QMSPI_STS_TX_BUFF_FULL) {
 			if (qmspi_wait(MCHP_QMSPI_STS_TX_BUFF_EMPTY,
-					MCHP_QMSPI_STS_TX_BUFF_EMPTY) !=
-							EC_SUCCESS) {
+				       MCHP_QMSPI_STS_TX_BUFF_EMPTY) !=
+			    EC_SUCCESS) {
 				MCHP_QMSPI0_EXE = MCHP_QMSPI_EXE_STOP;
 				return EC_ERROR_TIMEOUT;
 			}
@@ -673,8 +661,8 @@ int qmspi_enable(int hw_port, int enable)
 {
 	uint8_t unused __attribute__((unused)) = 0;
 
-	trace2(0, QMSPI, 0, "qmspi_enable: port = %d enable = %d",
-			hw_port, enable);
+	trace2(0, QMSPI, 0, "qmspi_enable: port = %d enable = %d", hw_port,
+	       enable);
 
 	if (hw_port != QMSPI0_PORT)
 		return EC_ERROR_INVAL;
@@ -685,9 +673,9 @@ int qmspi_enable(int hw_port, int enable)
 		MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_QMSPI);
 		MCHP_QMSPI0_MODE_ACT_SRST = MCHP_QMSPI_M_SOFT_RESET;
 		unused = MCHP_QMSPI0_MODE_ACT_SRST;
-		MCHP_QMSPI0_MODE = (MCHP_QMSPI_M_ACTIVATE +
-				MCHP_QMSPI_M_SPI_MODE0 +
-				MCHP_QMSPI_M_CLKDIV_12M);
+		MCHP_QMSPI0_MODE =
+			(MCHP_QMSPI_M_ACTIVATE + MCHP_QMSPI_M_SPI_MODE0 +
+			 MCHP_QMSPI_M_CLKDIV_12M);
 	} else {
 		MCHP_QMSPI0_MODE_ACT_SRST = MCHP_QMSPI_M_SOFT_RESET;
 		unused = MCHP_QMSPI0_MODE_ACT_SRST;
@@ -697,4 +685,3 @@ int qmspi_enable(int hw_port, int enable)
 
 	return EC_SUCCESS;
 }
-
diff --git a/chip/mchp/qmspi_chip.h b/chip/mchp/qmspi_chip.h
index 1a1d764267..899f59516f 100644
--- a/chip/mchp/qmspi_chip.h
+++ b/chip/mchp/qmspi_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -13,24 +13,23 @@
 #ifndef _QMSPI_CHIP_H
 #define _QMSPI_CHIP_H
 
-#include <stdint.h>
 #include <stddef.h>
+#include <stdint.h>
 
 /* struct spi_device_t */
 #include "spi.h"
 
-
 int qmspi_transaction_flush(const struct spi_device_t *spi_device);
 
 int qmspi_transaction_wait(const struct spi_device_t *spi_device);
 
 int qmspi_transaction_sync(const struct spi_device_t *spi_device,
-				const uint8_t *txdata, int txlen,
-				uint8_t *rxdata, int rxlen);
+			   const uint8_t *txdata, int txlen, uint8_t *rxdata,
+			   int rxlen);
 
 int qmspi_transaction_async(const struct spi_device_t *spi_device,
-				const uint8_t *txdata, int txlen,
-				uint8_t *rxdata, int rxlen);
+			    const uint8_t *txdata, int txlen, uint8_t *rxdata,
+			    int rxlen);
 
 int qmspi_enable(int port, int enable);
 
@@ -56,12 +55,10 @@ void qmspi_cfg_irq_start(uint8_t flags);
  * returns last descriptor 0 <= index < MCHP_QMSPI_MAX_DESCR
  * or error (bit[7]==1)
  */
-uint8_t qmspi_xfr(const struct spi_device_t *spi_device,
-			uint32_t np_flags,
-			const uint8_t *txdata, uint32_t ntx,
-			uint8_t *rxdata, uint32_t nrx);
+uint8_t qmspi_xfr(const struct spi_device_t *spi_device, uint32_t np_flags,
+		  const uint8_t *txdata, uint32_t ntx, uint8_t *rxdata,
+		  uint32_t nrx);
 
 #endif /* #ifndef _QMSPI_CHIP_H */
 /**   @}
  */
-
diff --git a/chip/mchp/registers-mec152x.h b/chip/mchp/registers-mec152x.h
new file mode 100644
index 0000000000..166ca63310
--- /dev/null
+++ b/chip/mchp/registers-mec152x.h
@@ -0,0 +1,1268 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Register map for Microchip MEC152x family controllers
+ */
+
+#ifndef __CROS_EC_REGISTERS_H
+#error "This header file should not be included directly."
+#endif
+
+/*
+ * IRQ Numbers
+ * NOTE: GIRQ22 aggregated output and its sources are not connected to
+ * the NVIC.
+ */
+#define MCHP_IRQ_GIRQ8 0
+#define MCHP_IRQ_GIRQ9 1
+#define MCHP_IRQ_GIRQ10 2
+#define MCHP_IRQ_GIRQ11 3
+#define MCHP_IRQ_GIRQ12 4
+#define MCHP_IRQ_GIRQ13 5
+#define MCHP_IRQ_GIRQ14 6
+#define MCHP_IRQ_GIRQ15 7
+#define MCHP_IRQ_GIRQ16 8
+#define MCHP_IRQ_GIRQ17 9
+#define MCHP_IRQ_GIRQ18 10
+#define MCHP_IRQ_GIRQ19 11
+#define MCHP_IRQ_GIRQ20 12
+#define MCHP_IRQ_GIRQ21 13
+#define MCHP_IRQ_GIRQ23 14
+#define MCHP_IRQ_GIRQ24 15
+#define MCHP_IRQ_GIRQ25 16
+#define MCHP_IRQ_GIRQ26 17
+/* GIRQ13 direct sources */
+#define MCHP_IRQ_I2C_0 20
+#define MCHP_IRQ_I2C_1 21
+#define MCHP_IRQ_I2C_2 22
+#define MCHP_IRQ_I2C_3 23
+#define MCHP_IRQ_I2C_4 158
+#define MCHP_IRQ_I2C_5 168
+#define MCHP_IRQ_I2C_6 169
+#define MCHP_IRQ_I2C_7 170
+/* GIRQ14 direct sources */
+#define MCHP_IRQ_DMA_0 24
+#define MCHP_IRQ_DMA_1 25
+#define MCHP_IRQ_DMA_2 26
+#define MCHP_IRQ_DMA_3 27
+#define MCHP_IRQ_DMA_4 28
+#define MCHP_IRQ_DMA_5 29
+#define MCHP_IRQ_DMA_6 30
+#define MCHP_IRQ_DMA_7 31
+#define MCHP_IRQ_DMA_8 32
+#define MCHP_IRQ_DMA_9 33
+#define MCHP_IRQ_DMA_10 34
+#define MCHP_IRQ_DMA_11 35
+/* GIRQ15 direct sources */
+#define MCHP_IRQ_UART0 40
+#define MCHP_IRQ_UART1 41
+#define MCHP_IRQ_EMI0 42
+#define MCHP_IRQ_EMI1 43
+#define MCHP_IRQ_UART2 44
+#define MCHP_IRQ_ACPIEC0_IBF 45
+#define MCHP_IRQ_ACPIEC0_OBE 46
+#define MCHP_IRQ_ACPIEC1_IBF 47
+#define MCHP_IRQ_ACPIEC1_OBE 48
+#define MCHP_IRQ_ACPIEC2_IBF 49
+#define MCHP_IRQ_ACPIEC2_OBE 50
+#define MCHP_IRQ_ACPIEC3_IBF 51
+#define MCHP_IRQ_ACPIEC3_OBE 52
+#define MCHP_IRQ_ACPIPM1_CTL 55
+#define MCHP_IRQ_ACPIPM1_EN 56
+#define MCHP_IRQ_ACPIPM1_STS 57
+#define MCHP_IRQ_8042EM_OBE 58
+#define MCHP_IRQ_8042EM_IBF 59
+#define MCHP_IRQ_MAILBOX_DATA 60
+#define MCHP_IRQ_PORT80DBG0 62
+#define MCHP_IRQ_PORT80DBG1 63
+#define MCHP_IRQ_LASIC 64
+/* GIRQ16 direct sources */
+#define MCHP_IRQ_PKE_ERR 65
+#define MCHP_IRQ_PKE_END 66
+#define MCHP_IRQ_NDRNG 67
+#define MCHP_IRQ_AES 68
+#define MCHP_IRQ_HASH 69
+/* GIRQ17 direct sources */
+#define MCHP_IRQ_PECI_HOST 70
+#define MCHP_IRQ_TACH_0 71
+#define MCHP_IRQ_TACH_1 72
+#define MCHP_IRQ_TACH_2 73
+#define MCHP_IRQ_TACH_3 159
+#define MCHP_IRQ_HDMI_CEC 160
+#define MCHP_IRQ_ADC_SNGL 78
+#define MCHP_IRQ_ADC_RPT 79
+#define MCHP_IRQ_LED0_WDT 83
+#define MCHP_IRQ_LED1_WDT 84
+#define MCHP_IRQ_LED2_WDT 85
+#define MCHP_IRQ_PROCHOT 87
+/* GIRQ18 direct sources */
+#define MCHP_IRQ_SLAVE_SPI 90
+#define MCHP_IRQ_QMSPI0 91
+#define MCHP_IRQ_PS2_0 100
+#define MCHP_IRQ_PS2_1 101
+#define MCHP_IRQ_PSPI 155
+#define MCHP_IRQ_SGPIO_0 161
+#define MCHP_IRQ_SGPIO_1 162
+#define MCHP_IRQ_SGPIO_2 163
+#define MCHP_IRQ_SGPIO_3 164
+#define MCHP_IRQ_CCT_TMR 146
+#define MCHP_IRQ_CCT_CAP0 147
+#define MCHP_IRQ_CCT_CAP1 148
+#define MCHP_IRQ_CCT_CAP2 149
+#define MCHP_IRQ_CCT_CAP3 150
+#define MCHP_IRQ_CCT_CAP4 151
+#define MCHP_IRQ_CCT_CAP5 152
+#define MCHP_IRQ_CCT_CMP0 153
+#define MCHP_IRQ_CCT_CMP1 154
+/* GIRQ19 direct sources */
+#define MCHP_IRQ_ESPI_PC 103
+#define MCHP_IRQ_ESPI_BM1 104
+#define MCHP_IRQ_ESPI_BM2 105
+#define MCHP_IRQ_ESPI_LTR 106
+#define MCHP_IRQ_ESPI_OOB_UP 107
+#define MCHP_IRQ_ESPI_OOB_DN 108
+#define MCHP_IRQ_ESPI_FC 109
+#define MCHP_IRQ_ESPI_RESET 110
+#define MCHP_IRQ_ESPI_VW_EN 156
+/* GIRQ20 direct sources */
+#define MCHP_IRQ_OTP 173
+/* GIRQ21 direct sources */
+#define MCHP_IRQ_WDG 171
+#define MCHP_IRQ_WEEK_ALARM 114
+#define MCHP_IRQ_SUBWEEK 115
+#define MCHP_IRQ_WEEK_SEC 116
+#define MCHP_IRQ_WEEK_SUBSEC 117
+#define MCHP_IRQ_WEEK_SYSPWR 118
+#define MCHP_IRQ_RTC 119
+#define MCHP_IRQ_RTC_ALARM 120
+#define MCHP_IRQ_VCI_OVRD_IN 121
+#define MCHP_IRQ_VCI_IN0 122
+#define MCHP_IRQ_VCI_IN1 123
+#define MCHP_IRQ_VCI_IN2 124
+#define MCHP_IRQ_VCI_IN3 125
+#define MCHP_IRQ_PS20A_WAKE 129
+#define MCHP_IRQ_PS20B_WAKE 130
+#define MCHP_IRQ_PS21B_WAKE 132
+#define MCHP_IRQ_KSC_INT 135
+/* GIRQ23 direct sources */
+#define MCHP_IRQ_TIMER16_0 136
+#define MCHP_IRQ_TIMER16_1 137
+#define MCHP_IRQ_TIMER32_0 140
+#define MCHP_IRQ_TIMER32_1 141
+#define MCHP_IRQ_RTOS_TIMER 111
+#define MCHP_IRQ_HTIMER0 112
+#define MCHP_IRQ_HTIMER1 113
+/* Must match CONFIG_IRQ_COUNT in config_chip.h */
+#define MCHP_IRQ_MAX 174
+
+/* Block base addresses */
+#define MCHP_WDG_BASE 0x40000400
+#define MCHP_TMR16_0_BASE 0x40000c00
+#define MCHP_TMR32_0_BASE 0x40000c80
+#define MCHP_DMA_BASE 0x40002400
+#define MCHP_PROCHOT_BASE 0x40003400
+#define MCHP_I2C0_BASE 0x40004000
+#define MCHP_I2C1_BASE 0x40004400
+#define MCHP_I2C2_BASE 0x40004800
+#define MCHP_I2C3_BASE 0x40004C00
+#define MCHP_I2C4_BASE 0x40005000
+#define MCHP_I2C5_BASE 0x40005100
+#define MCHP_I2C6_BASE 0x40005200
+#define MCHP_I2C7_BASE 0x40005300
+#define MCHP_QMSPI0_BASE 0x40070000
+#define MCHP_PWM_0_BASE 0x40005800
+#define MCHP_TACH_0_BASE 0x40006000
+#define MCHP_PECI_BASE 0x40006400
+#define MCHP_RTMR_BASE 0x40007400
+#define MCHP_ADC_BASE 0x40007c00
+#define MCHP_TFDP_BASE 0x40008c00
+#define MCHP_HTIMER_BASE 0x40009800
+#define MCHP_KEYSCAN_BASE 0x40009c00
+#define MCHP_VBAT_BASE 0x4000a400
+#define MCHP_VBAT_RAM_BASE 0x4000a800
+#define MCHP_WKTIMER_BASE 0x4000ac80
+#define MCHP_BBLED_0_BASE 0x4000B800
+#define MCHP_INT_BASE 0x4000e000
+#define MCHP_EC_BASE 0x4000fc00
+
+#define MCHP_PCR_BASE 0x40080100
+#define MCHP_GPIO_BASE 0x40081000
+
+#define MCHP_MBOX_BASE 0x400f0000
+#define MCHP_8042_BASE 0x400f0400
+#define MCHP_ACPI_EC_0_BASE 0x400f0800
+#define MCHP_ACPI_PM1_BASE 0x400f1c00
+#define MCHP_UART0_BASE 0x400f2400
+#define MCHP_UART1_BASE 0x400f2800
+#define MCHP_UART2_BASE 0x400f2c00
+#define MCHP_ESPI_IO_BASE 0x400f3400
+#define MCHP_ESPI_MEM_BASE 0x400f3800
+#define MCHP_EMI_0_BASE 0x400f4000
+#define MCHP_EMI_1_BASE 0x400f4400
+#define MCHP_P80CAP0_BASE 0x400f8000
+#define MCHP_P80CAP1_BASE 0x400f8400
+#define MCHP_ESPI_VW_BASE 0x400f9c00
+#define MCHP_CHIP_BASE 0x400fff00
+
+#ifndef __ASSEMBLER__
+
+/*
+ * Helper function for RAM address aliasing
+ * NOTE: MCHP AHB masters do NOT require aliasing.
+ * Cortex-M4 bit-banding does require aliasing of the
+ * DATA SRAM region.
+ */
+#define MCHP_RAM_ALIAS(x) ((x) >= 0x118000 ? (x)-0x118000 + 0x20000000 : (x))
+
+/* EC Chip Configuration */
+/* 16-bit Device ID */
+#define MCHP_CHIP_DEV_ID REG16(MCHP_CHIP_BASE + 0x1E)
+/* 8-bit Device Sub ID */
+#define MCHP_CHIP_DEV_SUB_ID REG8(MCHP_CHIP_BASE + 0x1D)
+/* 8-bit Device Revision */
+#define MCHP_CHIP_DEV_REV REG8(MCHP_CHIP_BASE + 0x1C)
+/* All in one */
+#define MCHP_CHIP_DEVRID32 REG32(MCHP_CHIP_BASE + 0x1C)
+#define MCHP_CHIP_DEVID_POS 16
+#define MCHP_CHIP_DEVID_MASK (0xfffful << MCHP_CHIP_DEVID_POS)
+#define MCHP_CHIP_SUBID_POS 8
+#define MCHP_CHIP_SUBID_MASK (0xfful << MCHP_CHIP_SUBID_POS)
+#define MCHP_CHIP_REV_POS 0
+#define MCHP_CHIP_REV_MASK (0xfful << MCHP_CHIP_REV_POS)
+#define MCHP_CHIP_EXTRACT_DEVID(d) \
+	(((uint32_t)(d)&MCHP_CHIP_DEVID_MASK) >> MCHP_CHIP_DEVID_POS)
+#define MCHP_CHIP_EXTRACT_SUBID(d) \
+	(((uint32_t)(d)&MCHP_CHIP_SUBID_MASK) >> MCHP_CHIP_SUBID_POS)
+#define MCHP_CHIP_EXTRACT_REV(d) \
+	(((uint32_t)(d)&MCHP_CHIP_REV_MASK) >> MCHP_CHIP_REV_POS)
+
+/* PCR clock control dividers */
+#define MCHP_PCR_CLK_CTL_FASTEST 1U
+#define MCHP_PCR_CLK_CTL_48MHZ 1U
+#define MCHP_PCR_CLK_CTL_12MHZ 4U
+
+/*
+ * PCR Peripheral Reset Lock register
+ * MEC152x PCR Peripheral reset registers do not reset on
+ * peripheral sleep. The peripheral is reset immediately.
+ * Firmware must write an unlock value to this new lock
+ * register, write to PCR reset enable register(s), and
+ * write a lock value.
+ */
+#define MCHP_PCR_RST_LOCK REG32(MCHP_PCR_BASE + 0x84)
+#define MCHP_PCR_RST_LOCK_VAL 0xa6382d4d
+#define MCHP_PCR_RST_UNLOCK_VAL 0xa6382d4c
+
+/* Number of PCR Sleep Enable, Clock Required, and Reset registers */
+#define MCHP_PCR_SLP_RST_REG_MAX 5
+
+/* MC152x new bit allow sleep entry when PLL is not locked */
+#define MCHP_PCR_SYS_SLP_NO_PLL BIT(8)
+
+/* Sleep 0: Sleep Enable, Clock Required, and Reset bits */
+#define MCHP_PCR_JTAG BIT(0) /* CLKREQ only */
+#define MCHP_PCR_OTP BIT(1)
+
+/* Command all blocks to sleep */
+#define MCHP_PCR_SLP_EN0_JTAG BIT(0)
+#define MCHP_PCR_SLP_EN0_OTP BIT(1)
+#define MCHP_PCR_SLP_EN0_SLEEP 0xffffffff
+
+/*
+ * Encode register number and bit position
+ * b[4:0] = bit number
+ * b[10:8] = zero based register number
+ */
+#define MCHP_PCR_ERB(rnum, bnum) ((((rnum)&0x0f) << 8) | ((bnum)&0x1f))
+
+/* PCR Sleep 1: Sleep Enable, Clock Required, and Reset bits */
+#define MCHP_PCR_BTMR16_1 MCHP_PCR_ERB(1, 31)
+#define MCHP_PCR_BTMR16_0 MCHP_PCR_ERB(1, 30)
+#define MCHP_PCR_ECS MCHP_PCR_ERB(1, 29)
+#define MCHP_PCR_PWM8 MCHP_PCR_ERB(1, 27)
+#define MCHP_PCR_PWM7 MCHP_PCR_ERB(1, 26)
+#define MCHP_PCR_PWM6 MCHP_PCR_ERB(1, 25)
+#define MCHP_PCR_PWM5 MCHP_PCR_ERB(1, 24)
+#define MCHP_PCR_PWM4 MCHP_PCR_ERB(1, 23)
+#define MCHP_PCR_PWM3 MCHP_PCR_ERB(1, 22)
+#define MCHP_PCR_PWM2 MCHP_PCR_ERB(1, 21)
+#define MCHP_PCR_PWM1 MCHP_PCR_ERB(1, 20)
+#define MCHP_PCR_TACH3 MCHP_PCR_ERB(1, 13)
+#define MCHP_PCR_TACH2 MCHP_PCR_ERB(1, 12)
+#define MCHP_PCR_TACH1 MCHP_PCR_ERB(1, 11)
+#define MCHP_PCR_I2C0 MCHP_PCR_ERB(1, 10)
+#define MCHP_PCR_WDT MCHP_PCR_ERB(1, 9)
+#define MCHP_PCR_CPU MCHP_PCR_ERB(1, 8)
+#define MCHP_PCR_TFDP MCHP_PCR_ERB(1, 7)
+#define MCHP_PCR_DMA MCHP_PCR_ERB(1, 6)
+#define MCHP_PCR_PMC MCHP_PCR_ERB(1, 5)
+#define MCHP_PCR_PWM0 MCHP_PCR_ERB(1, 4)
+#define MCHP_PCR_TACH0 MCHP_PCR_ERB(1, 2)
+#define MCHP_PCR_PECI MCHP_PCR_ERB(1, 1)
+#define MCHP_PCR_ECIA MCHP_PCR_ERB(1, 0)
+
+/* Command all blocks to sleep */
+#define MCHP_PCR_SLP_EN1_BTMR16_1 BIT(31)
+#define MCHP_PCR_SLP_EN1_BTMR16_0 BIT(30)
+#define MCHP_PCR_SLP_EN1_ECS BIT(29)
+#define MCHP_PCR_SLP_EN1_PWM_ALL (BIT(4) + (0xff << 20))
+#define MCHP_PCR_SLP_EN1_PWM8 BIT(27)
+#define MCHP_PCR_SLP_EN1_PWM7 BIT(26)
+#define MCHP_PCR_SLP_EN1_PWM6 BIT(25)
+#define MCHP_PCR_SLP_EN1_PWM5 BIT(24)
+#define MCHP_PCR_SLP_EN1_PWM4 BIT(23)
+#define MCHP_PCR_SLP_EN1_PWM3 BIT(22)
+#define MCHP_PCR_SLP_EN1_PWM2 BIT(21)
+#define MCHP_PCR_SLP_EN1_PWM1 BIT(20)
+#define MCHP_PCR_SLP_EN1_TACH3 BIT(13)
+#define MCHP_PCR_SLP_EN1_TACH2 BIT(12)
+#define MCHP_PCR_SLP_EN1_TACH1 BIT(11)
+#define MCHP_PCR_SLP_EN1_I2C0 BIT(10)
+#define MCHP_PCR_SLP_EN1_WDT BIT(9)
+#define MCHP_PCR_SLP_EN1_CPU BIT(8)
+#define MCHP_PCR_SLP_EN1_TFDP BIT(7)
+#define MCHP_PCR_SLP_EN1_DMA BIT(6)
+#define MCHP_PCR_SLP_EN1_PMC BIT(5)
+#define MCHP_PCR_SLP_EN1_PWM0 BIT(4)
+#define MCHP_PCR_SLP_EN1_TACH0 BIT(2)
+#define MCHP_PCR_SLP_EN1_PECI BIT(1)
+#define MCHP_PCR_SLP_EN1_ECIA BIT(0)
+/* all sleep enable 1 bits */
+#define MCHP_PCR_SLP_EN1_SLEEP 0xffffffff
+/*
+ * block not used by default
+ * Do not sleep ECIA, PMC, CPU and ECS
+ */
+#define MCHP_PCR_SLP_EN1_UNUSED_BLOCKS 0xdffffede
+
+/* PCR Sleep 2: Sleep Enable, Clock Required 2, Reset bits */
+#define MCHP_PCR_GLUE MCHP_PCR_ERB(2, 29)
+#define MCHP_PCR_UART2 MCHP_PCR_ERB(2, 28)
+#define MCHP_PCR_SAF MCHP_PCR_ERB(2, 27)
+#define MCHP_PCR_P80CAP1 MCHP_PCR_ERB(2, 26)
+#define MCHP_PCR_P80CAP0 MCHP_PCR_ERB(2, 25)
+#define MCHP_PCR_ASIF MCHP_PCR_ERB(2, 24)
+#define MCHP_PCR_ACPI_EC3 MCHP_PCR_ERB(2, 22)
+#define MCHP_PCR_ACPI_EC2 MCHP_PCR_ERB(2, 21)
+#define MCHP_PCR_ESPI_SCR MCHP_PCR_ERB(2, 20)
+#define MCHP_PCR_ESPI MCHP_PCR_ERB(2, 19)
+#define MCHP_PCR_RTC MCHP_PCR_ERB(2, 18)
+#define MCHP_PCR_MBOX MCHP_PCR_ERB(2, 17)
+#define MCHP_PCR_8042 MCHP_PCR_ERB(2, 26)
+#define MCHP_PCR_ACPI_PM1 MCHP_PCR_ERB(2, 15)
+#define MCHP_PCR_ACPI_EC1 MCHP_PCR_ERB(2, 14)
+#define MCHP_PCR_ACPI_EC0 MCHP_PCR_ERB(2, 13)
+#define MCHP_PCR_GCFG MCHP_PCR_ERB(2, 12)
+#define MCHP_PCR_UART1 MCHP_PCR_ERB(2, 2)
+#define MCHP_PCR_UART0 MCHP_PCR_ERB(2, 1)
+#define MCHP_PCR_EMI0 MCHP_PCR_ERB(2, 0)
+
+/* Command all blocks to sleep */
+#define MCHP_PCR_SLP_EN2_GLUE BIT(29)
+#define MCHP_PCR_SLP_EN2_UART2 BIT(28)
+#define MCHP_PCR_SLP_EN2_SAF BIT(27)
+#define MCHP_PCR_SLP_EN2_P80CAP1 BIT(26)
+#define MCHP_PCR_SLP_EN2_P80CAP0 BIT(25)
+#define MCHP_PCR_SLP_EN2_ASIF BIT(24)
+#define MCHP_PCR_SLP_EN2_ACPI_EC3 BIT(22)
+#define MCHP_PCR_SLP_EN2_ACPI_EC2 BIT(21)
+#define MCHP_PCR_SLP_EN2_ESPI_SCR BIT(20)
+#define MCHP_PCR_SLP_EN2_ESPI BIT(19)
+#define MCHP_PCR_SLP_EN2_RTC BIT(18)
+#define MCHP_PCR_SLP_EN2_MAILBOX BIT(17)
+#define MCHP_PCR_SLP_EN2_MIF8042 BIT(16)
+#define MCHP_PCR_SLP_EN2_ACPI_PM1 BIT(15)
+#define MCHP_PCR_SLP_EN2_ACPI_EC1 BIT(14)
+#define MCHP_PCR_SLP_EN2_ACPI_EC0 BIT(13)
+#define MCHP_PCR_SLP_EN2_GCFG BIT(12)
+#define MCHP_PCR_SLP_EN2_UART1 BIT(2)
+#define MCHP_PCR_SLP_EN2_UART0 BIT(1)
+#define MCHP_PCR_SLP_EN2_EMI0 BIT(0)
+/* all sleep enable 2 bits */
+#define MCHP_PCR_SLP_EN2_SLEEP 0xffffffff
+
+/* PCR Sleep 3: Sleep Enable, Clock Required, and Reset */
+#define MCHP_PCR_CCT0 MCHP_PCR_ERB(3, 30)
+#define MCHP_PCR_HTMR1 MCHP_PCR_ERB(3, 29)
+#define MCHP_PCR_AESHASH MCHP_PCR_ERB(3, 28)
+#define MCHP_PCR_RNG MCHP_PCR_ERB(3, 27)
+#define MCHP_PCR_PKE MCHP_PCR_ERB(3, 26)
+#define MCHP_PCR_BTMR32_1 MCHP_PCR_ERB(3, 24)
+#define MCHP_PCR_BTMR32_0 MCHP_PCR_ERB(3, 23)
+#define MCHP_PCR_I2C4 MCHP_PCR_ERB(3, 20)
+#define MCHP_PCR_LED2 MCHP_PCR_ERB(3, 18)
+#define MCHP_PCR_LED1 MCHP_PCR_ERB(3, 17)
+#define MCHP_PCR_LED0 MCHP_PCR_ERB(3, 16)
+#define MCHP_PCR_I2C3 MCHP_PCR_ERB(3, 15)
+#define MCHP_PCR_I2C2 MCHP_PCR_ERB(3, 14)
+#define MCHP_PCR_I2C1 MCHP_PCR_ERB(3, 13)
+#define MCHP_PCR_KEYSCAN MCHP_PCR_ERB(3, 11)
+#define MCHP_PCR_HTMR0 MCHP_PCR_ERB(3, 10)
+#define MCHP_PCR_PS2_1 MCHP_PCR_ERB(3, 6)
+#define MCHP_PCR_PS2_0 MCHP_PCR_ERB(3, 5)
+#define MCHP_PCR_ADC MCHP_PCR_ERB(3, 3)
+#define MCHP_PCR_HDMI_CEC MCHP_PCR_ERB(3, 1)
+
+/* Command blocks to sleep */
+#define MCHP_PCR_SLP_EN3_CCT0 BIT(30)
+#define MCHP_PCR_SLP_EN3_HTMR1 BIT(29)
+#define MCHP_PCR_SLP_EN3_AESHASH BIT(28)
+#define MCHP_PCR_SLP_EN3_RNG BIT(27)
+#define MCHP_PCR_SLP_EN3_PKE BIT(26)
+#define MCHP_PCR_SLP_EN3_BTMR32_1 BIT(24)
+#define MCHP_PCR_SLP_EN3_BTMR32_0 BIT(23)
+#define MCHP_PCR_SLP_EN3_I2C4 BIT(20)
+#define MCHP_PCR_SLP_EN3_LED2 BIT(18)
+#define MCHP_PCR_SLP_EN3_LED1 BIT(17)
+#define MCHP_PCR_SLP_EN3_LED0 BIT(16)
+#define MCHP_PCR_SLP_EN3_I2C3 BIT(15)
+#define MCHP_PCR_SLP_EN3_I2C2 BIT(14)
+#define MCHP_PCR_SLP_EN3_I2C1 BIT(13)
+#define MCHP_PCR_SLP_EN3_KEYSCAN BIT(11)
+#define MCHP_PCR_SLP_EN3_HTMR0 BIT(10)
+#define MCHP_PCR_SLP_EN3_PS2_1 BIT(6)
+#define MCHP_PCR_SLP_EN3_PS2_0 BIT(5)
+#define MCHP_PCR_SLP_EN3_ADC BIT(3)
+#define MCHP_PCR_SLP_EN3_HDMI_CEC BIT(1)
+#define MCHP_PCR_SLP_EN3_ALL_CRYPTO (0x07 << 26)
+/* all sleep enable 3 bits */
+#define MCHP_PCR_SLP_EN3_SLEEP 0xfffffffd
+#define MCHP_PCR_SLP_EN3_PWM_ALL 0
+
+/* PCR Sleep 4: Sleep Enable, Clock Required, Reset */
+#define MCHP_PCR_SGPIO3 MCHP_PCR_ERB(4, 20)
+#define MCHP_PCR_SGPIO2 MCHP_PCR_ERB(4, 19)
+#define MCHP_PCR_SGPIO1 MCHP_PCR_ERB(4, 18)
+#define MCHP_PCR_SGPIO0 MCHP_PCR_ERB(4, 17)
+#define MCHP_PCR_SLV_SPI MCHP_PCR_ERB(4, 16)
+#define MCHP_PCR_PSPI MCHP_PCR_ERB(4, 14)
+#define MCHP_PCR_PROCHOT MCHP_PCR_ERB(4, 13)
+#define MCHP_PCR_I2C7 MCHP_PCR_ERB(4, 12)
+#define MCHP_PCR_I2C6 MCHP_PCR_ERB(4, 11)
+#define MCHP_PCR_I2C5 MCHP_PCR_ERB(4, 10)
+#define MCHP_PCR_QMSPI MCHP_PCR_ERB(4, 8)
+#define MCHP_PCR_RTMR MCHP_PCR_ERB(4, 6)
+
+/* Command blocks to sleep */
+#define MCHP_PCR_SLP_EN4_SGPIO3 BIT(20)
+#define MCHP_PCR_SLP_EN4_SGPIO2 BIT(19)
+#define MCHP_PCR_SLP_EN4_SGPIO1 BIT(18)
+#define MCHP_PCR_SLP_EN4_SGPIO0 BIT(17)
+#define MCHP_PCR_SLP_EN4_SLV_SPI BIT(16)
+#define MCHP_PCR_SLP_EN4_PSPI BIT(14)
+#define MCHP_PCR_SLP_EN4_PROCHOT BIT(13)
+#define MCHP_PCR_SLP_EN4_I2C7 BIT(12)
+#define MCHP_PCR_SLP_EN4_I2C6 BIT(11)
+#define MCHP_PCR_SLP_EN4_I2C5 BIT(10)
+#define MCHP_PCR_SLP_EN4_QMSPI BIT(8)
+#define MCHP_PCR_SLP_EN4_RTMR BIT(6)
+/* all sleep enable 4 bits */
+#define MCHP_PCR_SLP_EN4_SLEEP 0xffffffff
+#define MCHP_PCR_SLP_EN4_PWM_ALL 0
+
+/* Allow all blocks to request clocks */
+#define MCHP_PCR_SLP_EN0_WAKE (~(MCHP_PCR_SLP_EN0_SLEEP))
+#define MCHP_PCR_SLP_EN1_WAKE (~(MCHP_PCR_SLP_EN1_SLEEP))
+#define MCHP_PCR_SLP_EN2_WAKE (~(MCHP_PCR_SLP_EN2_SLEEP))
+#define MCHP_PCR_SLP_EN3_WAKE (~(MCHP_PCR_SLP_EN3_SLEEP))
+#define MCHP_PCR_SLP_EN4_WAKE (~(MCHP_PCR_SLP_EN4_SLEEP))
+
+/* Bit defines for MCHP_PCR_PWR_RST_STS */
+#define MCHP_PWR_RST_STS_MASK_RO 0xc8c
+#define MCHP_PWR_RST_STS_MASK_RWC 0x170
+#define MCHP_PWR_RST_STS_MASK \
+	((MCHP_PWR_RST_STS_MASK_RO) | (MCHP_PWR_RST_STS_MASK_RWC))
+
+#define MCHP_PWR_RST_STS_ESPI_CLK_ACT BIT(11) /* RO */
+#define MCHP_PWR_RST_STS_32K_ACT BIT(10) /* RO */
+#define MCHP_PWR_RST_STS_WDT BIT(8) /* R/WC */
+#define MCHP_PWR_RST_STS_JTAG_RSTN BIT(7) /* RO */
+#define MCHP_PWR_RST_STS_SYS BIT(6) /* R/WC */
+#define MCHP_PWR_RST_STS_VBAT BIT(5) /* R/WC */
+#define MCHP_PWR_RST_STS_VTR BIT(4) /* R/WC */
+#define MCHP_PWR_RST_STS_HOST BIT(3) /* RO */
+#define MCHP_PWR_RST_STS_VCC_PWRGD BIT(2) /* RO */
+
+/* Bit defines for MCHP_PCR_PWR_RST_CTL */
+#define MCHP_PCR_PWR_HOST_RST_SEL_BITPOS 8
+#define MCHP_PCR_PWR_HOST_RST_PCI_RESET BIT(8)
+#define MCHP_PCR_PWR_HOST_RST_ESPI_PLTRST (0 << 8)
+#define MCHP_PCR_PWR_OK_INV_BITPOS 0
+
+/* Bit defines for MCHP_PCR_SYS_RST */
+#define MCHP_PCR_SYS_SOFT_RESET BIT(8)
+
+/* EC Subsystem */
+#define MCHP_EC_AHB_ERR REG32(MCHP_EC_BASE + 0x04)
+#define MCHP_EC_ID_RO REG32(MCHP_EC_BASE + 0x10)
+#define MCHP_EC_AHB_ERR_EN REG32(MCHP_EC_BASE + 0x14)
+#define MCHP_EC_INT_CTRL REG32(MCHP_EC_BASE + 0x18)
+#define MCHP_EC_TRACE_EN REG32(MCHP_EC_BASE + 0x1c)
+#define MCHP_EC_JTAG_EN REG32(MCHP_EC_BASE + 0x20)
+#define MCHP_EC_WDT_CNT REG32(MCHP_EC_BASE + 0x28)
+#define MCHP_EC_AES_SHA_SWAP_CTRL REG8(MCHP_EC_BASE + 0x2c)
+#define MCHP_EC_VCI_FW_OVRD REG8(MCHP_EC_BASE + 0x50)
+#define MCHP_EC_CRYPTO_SRESET REG8(MCHP_EC_BASE + 0x5c)
+#define MCHP_EC_GPIO_BANK_PWR REG8(MCHP_EC_BASE + 0x64)
+#define MCHP_EC_SLP_STS_MIRROR REG8(MCHP_EC_BASE + 0x114)
+
+/* AHB ERR Enable bit[0]=0(enable), 1(disable) */
+#define MCHP_EC_AHB_ERROR_ENABLE 0
+#define MCHP_EC_AHB_ERROR_DISABLE 1
+
+/* MCHP_EC_JTAG_EN bit definitions */
+#define MCHP_JTAG_ENABLE 0x01
+/* bits [2:1] */
+#define MCHP_JTAG_MODE_4PIN 0x00
+/* ARM 2-pin SWD plus 1-pin Serial Wire Viewer (ITM) */
+#define MCHP_JTAG_MODE_SWD_SWV 0x02
+/* ARM 2-pin SWD with no SWV */
+#define MCHP_JTAG_MODE_SWD 0x04
+
+/* MCHP_EC_CRYPTO_SRESET bit definitions. Bits cleared by HW */
+#define MCHP_CRYPTO_NDRNG_SRST 0x01
+#define MCHP_CRYPTO_PKE_SRST 0x02
+#define MCHP_CRYPTO_AES_SHA_SRST 0x04
+#define MCHP_CRYPTO_ALL_SRST 0x07
+
+/* MCHP_GPIO_BANK_PWR bit definitions */
+#define MCHP_EC_GPIO_BANK_PWR_MASK 0x86
+#define MCHP_EC_GPIO_BANK_PWR_VTR2_18 0x02
+#define MCHP_EC_GPIO_BANK_PWR_VTR3_18 0x04
+#define MCHP_EC_GPIO_BANK_PWR_LOCK 0x80
+
+/* EC Interrupt aggregator (ECIA) */
+#define MCHP_INT_GIRQ_LEN 20 /* 5 32-bit registers */
+#define MCHP_INT_GIRQ_FIRST 8
+#define MCHP_INT_GIRQ_LAST 26
+#define MCHP_INT_GIRQ_NUM (26 - 8 + 1)
+/* MCHP_INT_GIRQ_FIRST <= x <= MCHP_INT_GIRQ_LAST */
+#define MCHP_INTx_BASE(x) (MCHP_INT_BASE + (((x)-8) * MCHP_INT_GIRQ_LEN))
+
+/*
+ * GPIO GIRQ's are not direct capable
+ * GIRQ08 GPIO 0140 - 0176
+ * GIRQ09 GPIO 0100 - 0136
+ * GIRQ10 GPIO 040 - 076
+ * GIRQ11 GPIO 000 - 036
+ * GIRQ12 GPIO 0200 - 0236
+ * GIRQ26 GPIO 0240 - 0276
+ * Other GIRQ's not direct capable:
+ * GIRQ22 wake peripheral clock only
+ * GIRQ24, GIRQ25 eSPI host to endpoint virtual wires
+ */
+#define MCHP_INT_AGGR_ONLY_BITMAP 0x07401F00U
+#define MCHP_INT_DIRECT_CAPABLE_BITMAP 0x00BFE000U
+
+/* GIRQ13 I2C controllers. Direct capable */
+#define MCHP_INT13_I2C(x) (1ul << (x))
+
+/* GIRQ14 DMA channels 0 - 11. Direct capable */
+#define MCHP_INT14_DMA(x) (1ul << (x))
+
+/* GIQ15 interrupt sources. Direct capable */
+#define MCHP_INT15_UART_0 BIT(0)
+#define MCHP_INT15_UART_1 BIT(1)
+#define MCHP_INT15_UART_2 BIT(4)
+#define MCHP_INT15_EMI_0 BIT(2)
+#define MCHP_INT15_EMI_1 BIT(3)
+#define MCHP_INT15_ACPI_EC0_IBF BIT(5)
+#define MCHP_INT15_ACPI_EC0_OBE BIT(6)
+#define MCHP_INT15_ACPI_EC1_IBF BIT(7)
+#define MCHP_INT15_ACPI_EC1_OBE BIT(8)
+#define MCHP_INT15_ACPI_EC2_IBF BIT(9)
+#define MCHP_INT15_ACPI_EC2_OBE BIT(10)
+#define MCHP_INT15_ACPI_EC3_IBF BIT(11)
+#define MCHP_INT15_ACPI_EC3_OBE BIT(12)
+#define MCHP_INT15_ACPI_PM1_CTL BIT(15)
+#define MCHP_INT15_ACPI_PM1_EN BIT(16)
+#define MCHP_INT15_ACPI_PM1_STS BIT(17)
+#define MCHP_INT15_8042_OBE BIT(18)
+#define MCHP_INT15_8042_IBF BIT(19)
+#define MCHP_INT15_MAILBOX BIT(20)
+#define MCHP_INT15_P80_0 BIT(22)
+#define MCHP_INT15_P80_1 BIT(23)
+#define MCHP_INT15_P80(x) BIT(22 + ((x)&0x01U))
+
+/* GIRQ16 interrupt sources. Direct capable */
+#define MCHP_INT16_PKE_ERR BIT(0)
+#define MCHP_INT16_PKE_DONE BIT(1)
+#define MCHP_INT16_RNG_DONE BIT(2)
+#define MCHP_INT16_AES_DONE BIT(3)
+#define MCHP_INT16_HASH_DONE BIT(4)
+
+/* GIR17 interrupt sources. Direct capable */
+#define MCHP_INT17_PECI BIT(0)
+#define MCHP_INT17_TACH_0 BIT(1)
+#define MCHP_INT17_TACH_1 BIT(2)
+#define MCHP_INT17_TACH_2 BIT(3)
+#define MCHP_INT17_TACH_3 BIT(4)
+#define MCHP_INT17_HDMI_CEC BIT(5)
+#define MCHP_INT17_ADC_SINGLE BIT(8)
+#define MCHP_INT17_ADC_REPEAT BIT(9)
+#define MCHP_INT17_LED_WDT_0 BIT(13)
+#define MCHP_INT17_LED_WDT_1 BIT(14)
+#define MCHP_INT17_LED_WDT_2 BIT(15)
+#define MCHP_INT17_PROCHOT BIT(17)
+
+/* GIRQ18 interrupt sources. Direct capable */
+#define MCHP_INT18_SLV_SPI BIT(0)
+#define MCHP_INT18_QMSPI BIT(1)
+#define MCHP_INT18_PS2_0 BIT(10)
+#define MCHP_INT18_PS2_1 BIT(11)
+#define MCHP_INT18_CCT BIT(20)
+#define MCHP_INT18_CCT_CAP0 BIT(21)
+#define MCHP_INT18_CCT_CAP1 BIT(22)
+#define MCHP_INT18_CCT_CAP2 BIT(23)
+#define MCHP_INT18_CCT_CAP3 BIT(24)
+#define MCHP_INT18_CCT_CAP4 BIT(25)
+#define MCHP_INT18_CCT_CAP6 BIT(26)
+#define MCHP_INT18_CCT_CMP0 BIT(27)
+#define MCHP_INT18_CCT_CMP1 BIT(28)
+
+/* GIRQ19 interrupt sources. Direct capable */
+#define MCHP_INT19_ESPI_PC BIT(0)
+#define MCHP_INT19_ESPI_BM1 BIT(1)
+#define MCHP_INT19_ESPI_BM2 BIT(2)
+#define MCHP_INT19_ESPI_LTR BIT(3)
+#define MCHP_INT19_ESPI_OOB_TX BIT(4)
+#define MCHP_INT19_ESPI_OOB_RX BIT(5)
+#define MCHP_INT19_ESPI_FC BIT(6)
+#define MCHP_INT19_ESPI_RESET BIT(7)
+#define MCHP_INT19_ESPI_VW_EN BIT(8)
+#define MCHP_INT19_ESPI_SAF BIT(9)
+#define MCHP_INT19_ESPI_SAF_ERR BIT(10)
+
+/* GIRQ20 interrupt sources. Direct capable */
+#define MCHP_INT20_OPT BIT(3)
+
+/* GIRQ21 interrupt sources. Direct capable */
+#define MCHP_INT21_WDT BIT(2)
+#define MCHP_INT21_WEEK_ALARM BIT(3)
+#define MCHP_INT21_WEEK_SUB BIT(4)
+#define MCHP_INT21_WEEK_1SEC BIT(5)
+#define MCHP_INT21_WEEK_1SEC_SUB BIT(6)
+#define MCHP_INT21_WEEK_PWR_PRES BIT(7)
+#define MCHP_INT21_RTC BIT(8)
+#define MCHP_INT21_RTC_ALARM BIT(9)
+#define MCHP_INT21_VCI_OVRD BIT(10)
+#define MCHP_INT21_VCI_IN0 BIT(11)
+#define MCHP_INT21_VCI_IN1 BIT(12)
+#define MCHP_INT21_VCI_IN2 BIT(13)
+#define MCHP_INT21_VCI_IN3 BIT(14)
+#define MCHP_INT21_PS2_0A_WAKE BIT(18)
+#define MCHP_INT21_PS2_0B_WAKE BIT(19)
+#define MCHP_INT21_PS2_1B_WAKE BIT(21)
+#define MCHP_INT21_KEYSCAN BIT(25)
+
+/* GIRQ22 peripheral wake only. GIRQ22 not connected to NVIC */
+#define MCHP_INT22_WAKE_ONLY_SLV_SPI BIT(0)
+#define MCHP_INT22_WAKE_ONLY_I2C0 BIT(1)
+#define MCHP_INT22_WAKE_ONLY_I2C1 BIT(2)
+#define MCHP_INT22_WAKE_ONLY_I2C2 BIT(3)
+#define MCHP_INT22_WAKE_ONLY_I2C3 BIT(4)
+#define MCHP_INT22_WAKE_ONLY_I2C4 BIT(5)
+#define MCHP_INT22_WAKE_ONLY_I2C5 BIT(6)
+#define MCHP_INT22_WAKE_ONLY_I2C6 BIT(7)
+#define MCHP_INT22_WAKE_ONLY_I2C7 BIT(8)
+#define MCHP_INT22_WAKE_ONLY_ESPI BIT(9)
+
+/* GIRQ23 sources. Direct capable */
+#define MCHP_INT23_BTMR16_0 BIT(0)
+#define MCHP_INT23_BTMR16_1 BIT(1)
+#define MCHP_INT23_BTMR32_0 BIT(4)
+#define MCHP_INT23_BTMR32_1 BIT(5)
+#define MCHP_INT23_RTMR BIT(10)
+#define MCHP_INT23_HTMR_0 BIT(16)
+#define MCHP_INT23_HTMR_1 BIT(17)
+
+/* GIRQ24 sources. Master-to-Slave v=[0:6], Source=[0:3] */
+#define MCHP_INT24_MSVW_SRC(v, s) (1ul << ((4 * (v)) + (s)))
+
+/* GIRQ25 sources Master-to-Slave v=[7:10], Source=[0:3] */
+#define MCHP_INT25_MSVW_SRC(v, s) (1ul << ((4 * ((v)-7)) + (s)))
+
+/* UART Peripheral 0 <= x <= 2 */
+#define MCHP_UART_INSTANCES 3
+#define MCHP_UART_SPACING 0x400
+#define MCHP_UART_CFG_OFS 0x300
+#define MCHP_UART_CONFIG_BASE(x) \
+	(MCHP_UART0_BASE + MCHP_UART_CFG_OFS + ((x)*MCHP_UART_SPACING))
+#define MCHP_UART_RUNTIME_BASE(x) (MCHP_UART0_BASE + ((x)*MCHP_UART_SPACING))
+#define MCHP_UART_GIRQ 15
+#define MCHP_UART0_GIRQ_BIT (MCHP_INT15_UART_0)
+#define MCHP_UART1_GIRQ_BIT (MCHP_INT15_UART_1)
+#define MCHP_UART2_GIRQ_BIT (MCHP_INT15_UART_2)
+#define MCHP_UART_GIRQ_BIT(x) BIT(x)
+/* BIT defines for MCHP_UARTx_LSR */
+#define MCHP_LSR_TX_EMPTY BIT(5)
+
+/*
+ * GPIO
+ * MCHP each Port contains 32 GPIO's.
+ * GPIO Control 1 registers are 32-bit registers starting at
+ * MCHP_GPIO_BASE.
+ * index = octal GPIO number from MCHP specification.
+ * port/bank = index >> 5
+ * id = index & 0x1F
+ *
+ * The port/bank, id pair may also be used to access GPIO's via
+ * parallel I/O registers if GPIO control is configured for
+ * parallel I/O.
+ *
+ * From ec/chip/mec1701/config_chip.h
+ * #define GPIO_PIN(index) ((index) >> 5), ((index) & 0x1F)
+ *
+ * GPIO Control 1 Address = 0x40081000 + (((bank << 5) + id) << 2)
+ *
+ * Example: GPIO043, Control 1 register address = 0x4008108c
+ * port/bank = 0x23 >> 5 = 1
+ * id        = 0x23 & 0x1F = 0x03
+ * Control 1 Address = 0x40081000 + ((BIT(5) + 0x03) << 2) = 0x4008108c
+ *
+ * Example: GPIO235, Control 1 register address = 0x40081274
+ * port/bank = 0x9d >> 5   = 4
+ * id        = 0x9d & 0x1f = 0x1d
+ * Control 1 Address = 0x40081000 + (((4 << 5) + 0x1d) << 2) = 0x40081274
+ */
+#define MCHP_GPIO_CTL(port, id) \
+	REG32(MCHP_GPIO_BASE + (((port << 5) + id) << 2))
+
+/* MCHP implements 6 GPIO ports */
+#define MCHP_GPIO_MAX_PORT 6
+#define UNIMPLEMENTED_GPIO_BANK MCHP_GPIO_MAX_PORT
+
+/*
+ * In MECxxxx documentation GPIO numbers are octal, each control
+ * register is located on a 32-bit boundary.
+ */
+#define MCHP_GPIO_CTRL(gpio_num) REG32(MCHP_GPIO_BASE + ((gpio_num) << 2))
+
+/*
+ * GPIO control register bit fields
+ */
+#define MCHP_GPIO_CTRL_PUD_BITPOS 0
+#define MCHP_GPIO_CTRL_PUD_MASK0 0x03
+#define MCHP_GPIO_CTRL_PUD_MASK 0x03
+#define MCHP_GPIO_CTRL_PUD_NONE 0x00
+#define MCHP_GPIO_CTRL_PUD_PU 0x01
+#define MCHP_GPIO_CTRL_PUD_PD 0x02
+#define MCHP_GPIO_CTRL_PUD_KEEPER 0x03
+#define MCHP_GPIO_CTRL_PWR_BITPOS 2
+#define MCHP_GPIO_CTRL_PWR_MASK0 0x03
+#define MCHP_GPIO_CTRL_PWR_MASK (0x03 << 2)
+#define MCHP_GPIO_CTRL_PWR_VTR (0x00 << 2)
+#define MCHP_GPIO_CTRL_PWR_OFF (0x02 << 2)
+#define MCHP_GPIO_INTDET_MASK 0xF0
+#define MCHP_GPIO_INTDET_LVL_LO 0x00
+#define MCHP_GPIO_INTDET_LVL_HI 0x10
+#define MCHP_GPIO_INTDET_DISABLED 0x40
+#define MCHP_GPIO_INTDET_EDGE_RIS 0xD0
+#define MCHP_GPIO_INTDET_EDGE_FALL 0xE0
+#define MCHP_GPIO_INTDET_EDGE_BOTH 0xF0
+#define MCHP_GPIO_INTDET_EDGE_EN BIT(7)
+#define MCHP_GPIO_PUSH_PULL 0u
+#define MCHP_GPIO_OPEN_DRAIN BIT(8)
+#define MCHP_GPIO_INPUT 0u
+#define MCHP_GPIO_OUTPUT BIT(9)
+#define MCHP_GPIO_OUTSET_CTRL 0u
+#define MCHP_GPIO_OUTSEL_PAR BIT(10)
+#define MCHP_GPIO_POLARITY_NINV 0u
+#define MCHP_GPIO_POLARITY_INV BIT(11)
+#define MCHP_GPIO_CTRL_ALT_FUNC_BITPOS 12
+#define MCHP_GPIO_CTRL_ALT_FUNC_MASK0 0x0F
+#define MCHP_GPIO_CTRL_ALT_FUNC_MASK (0x0F << 12)
+#define MCHP_GPIO_CTRL_FUNC_GPIO (0 << 12)
+#define MCHP_GPIO_CTRL_FUNC_1 (1 << 12)
+#define MCHP_GPIO_CTRL_FUNC_2 (2 << 12)
+#define MCHP_GPIO_CTRL_FUNC_3 (3 << 12)
+#define MCHP_GPIO_CTRL_OUT_LVL BIT(16)
+/* MEC15xx only */
+#define MCHP_GPIO_CTRL_DIS_INPUT_BITPOS 15
+#define MCHP_GPIO_CTRL_DIS_INPUT_BIT BIT(15)
+
+/*
+ * GPIO Parallel Input and Output registers.
+ * gpio_bank in [0, 5]
+ */
+#define MCHP_GPIO_PARIN(bank) REG32(MCHP_GPIO_BASE + 0x0300 + ((bank) << 2))
+#define MCHP_GPIO_PAROUT(bank) REG32(MCHP_GPIO_BASE + 0x0380 + ((bank) << 2))
+
+/* Basic timers */
+#define MCHP_TMR_SPACING 0x20
+#define MCHP_TMR16_INSTANCES 2
+#define MCHP_TMR32_INSTANCES 2
+#define MCHP_TMR16_MAX (MCHP_TMR16_INSTANCES)
+#define MCHP_TMR32_MAX (MCHP_TMR32_INSTANCES)
+#define MCHP_TMR16_BASE(n) (MCHP_TMR16_0_BASE + (n)*MCHP_TMR_SPACING)
+#define MCHP_TMR32_BASE(n) (MCHP_TMR32_0_BASE + (n)*MCHP_TMR_SPACING)
+#define MCHP_TMR16_GIRQ 23
+#define MCHP_TMR16_GIRQ_BIT(n) BIT(0 + (n))
+#define MCHP_TMR32_GIRQ 23
+#define MCHP_TMR32_GIRQ_BIT(n) BIT(4 + (n))
+
+/* RTimer */
+#define MCHP_RTMR_GIRQ 23
+#define MCHP_RTMR_GIRQ_BIT(x) BIT(10)
+
+/* Watchdog */
+/* MEC152x specific registers */
+#define MCHP_WDG_STATUS REG32(MCHP_WDG_BASE + 0x10)
+#define MCHP_WDG_IEN REG32(MCHP_WDG_BASE + 0x14)
+/* Status */
+#define MCHP_WDG_STS_IRQ BIT(0)
+/* Interrupt enable */
+#define MCHP_WDG_IEN_IRQ_EN BIT(0)
+#define MCHP_WDG_GIRQ 21
+#define MCHP_WDG_GIRQ_BIT BIT(2)
+/* Control register has a bit to enable IRQ generation */
+#define MCHP_WDG_RESET_IRQ_EN BIT(9)
+
+/* VBAT */
+#define MCHP_VBAT_STS REG32(MCHP_VBAT_BASE + 0x0)
+#define MCHP_VBAT_CE REG32(MCHP_VBAT_BASE + 0x8)
+#define MCHP_VBAT_SHDN_DIS REG32(MCHP_VBAT_BASE + 0xC)
+#define MCHP_VBAT_MONOTONIC_CTR_LO REG32(MCHP_VBAT_BASE + 0x20)
+#define MCHP_VBAT_MONOTONIC_CTR_HI REG32(MCHP_VBAT_BASE + 0x24)
+/* read 32-bit word at 32-bit offset x where 0 <= x <= 16 */
+#define MCHP_VBAT_RAM_SIZE 64
+#define MCHP_VBAT_RAM(wnum) REG32(MCHP_VBAT_RAM_BASE + ((wnum)*4))
+#define MCHP_VBAT_RAM8(bnum) REG8(MCHP_VBAT_RAM_BASE + (bnum))
+#define MCHP_VBAT_VWIRE_BACKUP 14
+/*
+ * Miscellaneous firmware control fields
+ * scratch pad index cannot be more than 32 as
+ * MEC152x has 64 bytes = 16 words of scratch pad RAM
+ */
+#define MCHP_IMAGETYPE_IDX 15
+
+/* Bit definition for MCHP_VBAT_STS */
+#define MCHP_VBAT_STS_SOFTRESET BIT(2)
+#define MCHP_VBAT_STS_RESETI BIT(4)
+#define MCHP_VBAT_STS_WDT BIT(5)
+#define MCHP_VBAT_STS_SYSRESETREQ BIT(6)
+#define MCHP_VBAT_STS_VBAT_RST BIT(7)
+#define MCHP_VBAT_STS_ANY_RST 0xF4u
+
+/* Bit definitions for MCHP_VBAT_CE */
+#define MCHP_VBAT_CE_XOSEL_BITPOS 3
+#define MCHP_VBAT_CE_XOSEL_MASK BIT(3)
+#define MCHP_VBAT_CE_XOSEL_PAR 0
+#define MCHP_VBAT_CE_XOSEL_SE BIT(3)
+
+#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_BITPOS 2
+#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_MASK BIT(2)
+#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_INT 0
+#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_CRYSTAL BIT(2)
+
+#define MCHP_VBAT_CE_32K_DOMAIN_SRC_BITPOS 1
+#define MCHP_VBAT_CE_32K_DOMAIN_SRC_MASK BIT(1)
+#define MCHP_VBAT_CE_32K_DOMAIN_ALWAYS_ON 0
+#define MCHP_VBAT_CE_32K_DOMAIN_32KHZ_IN_PIN BIT(1)
+
+/* Blinking-Breathing LED 0 <= n <= 2 */
+#define MCHP_BBLEB_INSTANCES 3
+#define MCHP_BBLED_BASE(n) (MCHP_BBLED_0_BASE + (((n)&0x03) * 256))
+
+/* EMI */
+#define MCHP_EMI_INSTANCES 2
+#define MCHP_EMI_SPACING 0x400
+#define MCHP_EMI_ECREG_OFS 0x100
+/* base of EMI registers only accessible by EC */
+#define MCHP_EMI_BASE(n) \
+	(MCHP_EMI_0_BASE + MCHP_EMI_ECREG_OFS + ((n)*MCHP_EMI_SPACING))
+/* base of EMI registers accessible by EC and Host */
+#define MCHP_EMI_RT_BASE(n) (MCHP_EMI_0_BASE + ((n)*MCHP_EMI_SPACING))
+#define MCHP_EMI_GIRQ 15
+#define MCHP_EMI_GIRQ_BIT(n) BIT(2 + (n))
+
+/* Mailbox */
+#define MCHP_MBX_ECREGS_OFS 0x100
+#define MCHP_MBX_RT_BASE MCHP_MBOX_BASE
+#define MCHP_MBX_BASE (MCHP_MBOX_BASE + MCHP_MBX_ECREGS_OFS)
+#define MCHP_MBX_GIRQ 15
+#define MCHP_MBX_GIRQ_BIT BIT(20)
+
+/* Port 80 Capture */
+#define MCHP_P80_SPACING 0x400
+#define MCHP_P80_BASE(n) (MCHP_P80CAP0_BASE + ((n) * (MCHP_P80_SPACING)))
+#define MCHP_P80_HOST_DATA(n) REG8(MCHP_P80_BASE(n))
+/* Data capture with time stamp register */
+#define MCHP_P80_CAP(n) REG32(MCHP_P80_BASE(n) + 0x100)
+#define MCHP_P80_CFG(n) REG8(MCHP_P80_BASE(n) + 0x104)
+#define MCHP_P80_STS(n) REG8(MCHP_P80_BASE(n) + 0x108)
+#define MCHP_P80_CNT(n) REG32(MCHP_P80_BASE(n) + 0x10c)
+#define MCHP_P80_CNT_GET(n) (REG32(MCHP_P80_BASE(n) + 0x10c) >> 8)
+#define MCHP_P80_CNT_SET(n, c) (REG32(MCHP_P80_BASE(n) + 0x10c) = ((c) << 8))
+#define MCHP_P80_ACTIVATE(n) REG8(MCHP_P80_BASE(n) + 0x330)
+#define MCHP_P80_GIRQ 15
+#define MCHP_P80_GIRQ_BIT(n) BIT(22 + (n))
+/*
+ * Port 80 Data register bits
+ * bits[7:0] = data captured on Host write
+ * bits[31:8] = optional time stamp
+ */
+#define MCHP_P80_CAP_DATA_MASK 0xFFul
+#define MCHP_P80_CAP_TS_BITPOS 8
+#define MCHP_P80_CAP_TS_MASK0 0xfffffful
+#define MCHP_P80_CAP_TS_MASK \
+	((MCHP_P80_CAP_TS_MASK0) << (MCHP_P80_CAP_TS_BITPOS))
+
+/* Port 80 Configuration register bits */
+#define MCHP_P80_FLUSH_FIFO_WO BIT(1)
+#define MCHP_P80_RESET_TIMESTAMP_WO BIT(2)
+#define MCHP_P80_TIMEBASE_BITPOS 3
+#define MCHP_P80_TIMEBASE_MASK0 0x03
+#define MCHP_P80_TIMEBASE_MASK \
+	((MCHP_P80_TIMEBASE_MASK0) << (MCHP_P80_TIMEBASE_BITPOS))
+#define MCHP_P80_TIMEBASE_750KHZ (0x03 << (MCHP_P80_TIMEBASE_BITPOS))
+#define MCHP_P80_TIMEBASE_1500KHZ (0x02 << (MCHP_P80_TIMEBASE_BITPOS))
+#define MCHP_P80_TIMEBASE_3MHZ (0x01 << (MCHP_P80_TIMEBASE_BITPOS))
+#define MCHP_P80_TIMEBASE_6MHZ (0x00 << (MCHP_P80_TIMEBASE_BITPOS))
+#define MCHP_P80_TIMER_ENABLE BIT(5)
+#define MCHP_P80_FIFO_THRHOLD_MASK (3u << 6)
+#define MCHP_P80_FIFO_THRHOLD_1 0u
+#define MCHP_P80_FIFO_THRHOLD_4 (1u << 6)
+#define MCHP_P80_FIFO_THRHOLD_8 (2u << 6)
+#define MCHP_P80_FIFO_THRHOLD_14 (3u << 6)
+#define MCHP_P80_FIFO_LEN 16
+/* Port 80 Status register bits, read-only */
+#define MCHP_P80_STS_NOT_EMPTY BIT(0)
+#define MCHP_P80_STS_OVERRUN BIT(1)
+/* Port 80 Count register bits */
+#define MCHP_P80_CNT_BITPOS 8
+#define MCHP_P80_CNT_MASK0 0xfffffful
+#define MCHP_P80_CNT_MASK ((MCHP_P80_CNT_MASK0) << (MCHP_P80_CNT_BITPOS))
+
+/* PWM */
+#define MCHP_PWM_INSTANCES 9
+#define MCHP_PWM_ID_MAX (MCHP_PWM_INSTANCES)
+#define MCHP_PWM_SPACING 16
+#define MCHP_PWM_BASE(x) (MCHP_PWM_0_BASE + ((x)*MCHP_PWM_SPACING))
+
+/* TACH */
+#define MCHP_TACH_INSTANCES 4
+#define MCHP_TACH_SPACING 16
+#define MCHP_TACH_BASE(x) (MCHP_TACH_0_BASE + ((x)*MCHP_TACH_SPACING))
+#define MCHP_TACH_GIRQ 17
+#define MCHP_TACH_GIRQ_BIT(x) BIT(1 + (x))
+
+/* ACPI EC */
+#define MCHP_ACPI_EC_INSTANCES 4
+#define MCHP_ACPI_EC_MAX (ACPI_EC_INSTANCES)
+#define MCHP_ACPI_EC_SPACING 0x400
+#define MCHP_ACPI_EC_BASE(x) (MCHP_ACPI_EC_0_BASE + ((x)*MCHP_ACPI_EC_SPACING))
+#define MCHP_ACPI_EC_GIRQ 15
+#define MCHP_ACPI_EC_IBF_GIRQ_BIT(x) BIT(5 + ((x)*2))
+#define MCHP_ACPI_EC_OBE_GIRQ_BIT(x) BIT(6 + ((x)*2))
+
+/* ACPI PM1 */
+#define MCHP_ACPI_PM1_ECREGS_OFS 0x100
+#define MCHP_ACPI_PM_RT_BASE MCHP_ACPI_PM1_BASE
+#define MCHP_ACPI_PM_EC_BASE (MCHP_ACPI_PM1_BASE + MCHP_ACPI_PM1_ECREGS_OFS)
+#define MCHP_ACPI_PM1_CTL_GIRQ_BIT BIT(15)
+#define MCHP_ACPI_PM1_EN_GIRQ_BIT BIT(16)
+#define MCHP_ACPI_PM1_STS_GIRQ_BIT BIT(17)
+
+/* 8042 */
+#define MCHP_8042_ECREGS_OFS 0x100
+#define MCHP_8042_GIRQ 15
+#define MCHP_8042_OBE_GIRQ_BIT BIT(18)
+#define MCHP_8042_IBF_GIRQ_BIT BIT(19)
+
+/*
+ * I2C controllers 0 - 4 include SMBus network layer functionality.
+ * I2C controllers 5 - 7 are I2C only and include slave mode
+ * promiscuous functionality.
+ */
+#define MCHP_I2C_CTRL0 0
+#define MCHP_I2C_CTRL1 1
+#define MCHP_I2C_CTRL2 2
+#define MCHP_I2C_CTRL3 3
+#define MCHP_I2C_CTRL4 4
+#define MCHP_I2C_CTRL5 5
+#define MCHP_I2C_CTRL6 6
+#define MCHP_I2C_CTRL7 7
+#define MCHP_I2C_CTRL_MAX 8
+
+#define MCHP_I2C_SEP0 0x400
+#define MCHP_I2C_SEP1 0x100
+
+/*
+ * MEC152xH 144-pin package has eight I2C controllers and sixteen ports.
+ * Any port can be mapped to any I2C controller.
+ *
+ * I2C port values must be zero based consecutive whole numbers due to
+ * port number used as an index for I2C mutex array, etc.
+ *
+ * Refer to chip i2c_port_to_controller function for mapping
+ * of port to controller.
+ *
+ * Locking must occur by-controller (not by-port).
+ * I2C00_SCL/SDA on GPIO004 F1, GPIO003 F1
+ * I2C01_SCL/SDA on GPIO0131 F1, GPIO130 F1
+ *	Alternate pins: GPIO073 F2, GPIO072 F2
+ * I2C02_SCL/SDA on GPIO0155 F1, GPIO0154 F1
+ * I2C03_SCL/SDA on GPIO010 F1, GPIO007 F1
+ * I2C04_SCL/SDA on GPIO0144 F1, GPIO0143 F1
+ * I2C05_SCL/SDA on GPIO0142 F1, GPIO0141 F1
+ * I2C06_SCL/SDA on GPIO0140 F1, GPIO0132 F1
+ * I2C07_SCL/SDA on GPIO013 F1, GPIO012 F1
+ *	Alternate pins: GPIO0024 F3, GPIO0152 F3
+ * I2C08_SCL/SDA on GPIO012 F1, GPIO0211 F1
+ * I2C09_SCL/SDA on GPIO0146 F1, GPIO0145 F1
+ * I2C10_SCL/SDA on GPIO0107 F3, GPIO030 F2
+ * I2C11_SCL/SDA on GPIO062 F2, GPIO000 F3
+ * I2C12_SCL/SDA on GPIO027 F3, GPIO026 F3
+ * I2C13_SCL/SDA on GPIO065 F2, GPIO066 F2
+ * I2C14_SCL/SDA on GPIO071 F2, GPIO070 F2
+ * I2C15_SCL/SDA on GPIO0150 F1, GPIO0147 F1
+ */
+
+#define MCHP_MEC1521SZ_I2C_PORT_MASK 0xFEFFul
+#define MCHP_MEC1523SZ_I2C_PORT_MASK 0xFFFFul
+
+#define MCHP_I2C_PORT_MASK MCHP_MEC1521SZ_I2C_PORT_MASK
+
+enum MCHP_i2c_port {
+	MCHP_I2C_PORT0 = 0,
+	MCHP_I2C_PORT1,
+	MCHP_I2C_PORT2,
+	MCHP_I2C_PORT3,
+	MCHP_I2C_PORT4,
+	MCHP_I2C_PORT5,
+	MCHP_I2C_PORT6,
+	MCHP_I2C_PORT7,
+	MCHP_I2C_PORT8,
+	MCHP_I2C_PORT9,
+	MCHP_I2C_PORT10,
+	MCHP_I2C_PORT11,
+	MCHP_I2C_PORT12,
+	MCHP_I2C_PORT13,
+	MCHP_I2C_PORT14,
+	MCHP_I2C_PORT15,
+	MCHP_I2C_PORT_COUNT,
+};
+
+/* I2C ports & Configs */
+#define I2C_CONTROLLER_COUNT MCHP_I2C_CTRL_MAX
+#define I2C_PORT_COUNT MCHP_I2C_PORT_COUNT
+
+/*
+ * I2C controllers 0-4 implement network layer hardware.
+ * I2C controllers 5-7 do include network layer hardware.
+ * MEC152x has I2C promiscuous mode feature in the following
+ * additional registers.
+ */
+#define MCHP_I2C_SLAVE_ADDR(ctrl) REG32(MCHP_I2C_ADDR(ctrl, 0x6c))
+#define MCHP_I2C_PROM_INTR(ctrl) REG32(MCHP_I2C_ADDR(ctrl, 0x70))
+#define MCHP_I2C_PROM_INTR_EN(ctrl) REG32(MCHP_I2C_ADDR(ctrl, 0x74))
+#define MCHP_I2C_PROM_CTRL(ctrl) REG32(MCHP_I2C_ADDR(ctrl, 0x78))
+
+/* All I2C controllers connected to GIRQ13 */
+#define MCHP_I2C_GIRQ 13
+/* I2C[0:7] -> GIRQ13 bits[0:7] */
+#define MCHP_I2C_GIRQ_BIT(n) BIT((n))
+
+/* Keyboard scan matrix */
+#define MCHP_KS_GIRQ 21
+#define MCHP_KS_GIRQ_BIT BIT(25)
+#define MCHP_KS_DIRECT_NVIC 135
+
+/* ADC */
+#define MCHP_ADC_GIRQ 17
+#define MCHP_ADC_GIRQ_SINGLE_BIT BIT(8)
+#define MCHP_ADC_GIRQ_REPEAT_BIT BIT(9)
+#define MCHP_ADC_SINGLE_DIRECT_NVIC 78
+#define MCHP_ADC_REPEAT_DIRECT_NVIC 79
+
+/* Hibernation timer */
+#define MCHP_HTIMER_SPACING 0x20
+#define MCHP_HTIMER_ADDR(n) (MCHP_HTIMER_BASE + ((n)*MCHP_HTIMER_SPACING))
+#define MCHP_HTIMER_GIRQ 23
+/* HTIMER[0:1] -> GIRQ23 bits[16:17] */
+#define MCHP_HTIMER_GIRQ_BIT(n) BIT(16 + (n))
+#define MCHP_HTIMER_DIRECT_NVIC(n) (112 + (n))
+
+/*
+ * Quad Master SPI (QMSPI)
+ * MEC152x implements 16 descriptors, support for two chip selects,
+ * and additional SPI signal timing registers.
+ */
+#define MCHP_QMSPI_MAX_DESCR 16
+/*
+ * Chip select implemented in bit[13:12] of the Mode register.
+ * These bits are reserved in earlier chips.
+ */
+#define MCHP_QMSPI_M_CS_POS 12
+#define MCHP_QMSPI_M_CS_MASK0 0x03
+#define MCHP_QMSPI_M_CS_MASK (0x03 << MCHP_QMSPI_M_CS_POS)
+#define MCHP_QMSPI_M_CS0 (0x00 << MCHP_QMSPI_M_CS_POS)
+#define MCHP_QMSPI_M_CS1 (0x01 << MCHP_QMSPI_M_CS_POS)
+
+/* New QMSPI chip select timing register */
+#define MCHP_QMSPI_CS_TIMING REG32(MCHP_QMSPI0_BASE + 0x28)
+#define MCHP_QMSPI_CST_DFLT_VAL 0x06060406
+#define MCHP_QMSPI_CST_ON2CLK_MASK 0x0f
+#define MCHP_QMSPI_CST_ON2CLK_DFLT 0x06
+#define MCHP_QMSPI_CST_DLY_CLK2OFF_POS 8
+#define MCHP_QMSPI_CST_DLY_CLK2OFF_MASK0 0x0f
+#define MCHP_QMSPI_CST_DLY_CLK2OFF_MASK 0x0f00
+#define MCHP_QMSPI_CST_DLY_CLK2OFF_DFLT 0x0400
+#define MCHP_QMSPI_CST_DLY_LDH_POS 16
+#define MCHP_QMSPI_CST_DLY_LDH_MASK0 0x0f
+#define MCHP_QMSPI_CST_DLY_LDH_MASK 0xf0000
+#define MCHP_QMSPI_CST_DLY_LDH_DFLT 0x60000
+#define MCHP_QMSPI_CST_DLY_OFF2ON_POS 24
+#define MCHP_QMSPI_CST_DLY_OFF2ON_DFLT 0x06000000
+#define MCHP_QMSPI_CST_DLY_OFF2ON_MASK0 0xff
+#define MCHP_QMSPI_CST_DLY_OFF2ON_MASK 0xff000000
+
+#define MCHP_QMSPI_GIRQ 18
+#define MCHP_QMSPI_GIRQ_BIT BIT(1)
+#define MCHP_QMSPI_DIRECT_NVIC 91
+
+/* eSPI */
+
+/* IO BAR defines. Use with MCHP_ESPI_IO_BAR_xxxx macros */
+#define MCHP_ESPI_IO_BAR_ID_CFG_PORT 0
+#define MCHP_ESPI_IO_BAR_ID_MEM_CMPNT 1
+#define MCHP_ESPI_IO_BAR_ID_MAILBOX 2
+#define MCHP_ESPI_IO_BAR_ID_8042 3
+#define MCHP_ESPI_IO_BAR_ID_ACPI_EC0 4
+#define MCHP_ESPI_IO_BAR_ID_ACPI_EC1 5
+#define MCHP_ESPI_IO_BAR_ID_ACPI_EC2 6
+#define MCHP_ESPI_IO_BAR_ID_ACPI_EC3 7
+#define MCHP_ESPI_IO_BAR_ID_ACPI_PM1 9
+#define MCHP_ESPI_IO_BAR_ID_P92 0xA
+#define MCHP_ESPI_IO_BAR_ID_UART0 0xB
+#define MCHP_ESPI_IO_BAR_ID_UART1 0xC
+#define MCHP_ESPI_IO_BAR_ID_EMI0 0xD
+#define MCHP_ESPI_IO_BAR_ID_EMI1 0xE
+#define MCHP_ESPI_IO_BAR_P80_0 0x10
+#define MCHP_ESPI_IO_BAR_P80_1 0x11
+#define MCHP_ESPI_IO_BAR_RTC 0x12
+#define MCHP_ESPI_IO_BAR_ID_UART2 0x15
+
+/* Use with MCHP_ESPI_MBAR_EC_xxxx(x) macros */
+#define MCHP_ESPI_MBAR_ID_MBOX 0
+#define MCHP_ESPI_MBAR_ID_ACPI_EC_0 1
+#define MCHP_ESPI_MBAR_ID_ACPI_EC_1 2
+#define MCHP_ESPI_MBAR_ID_ACPI_EC_2 3
+#define MCHP_ESPI_MBAR_ID_ACPI_EC_3 4
+#define MCHP_ESPI_MBAR_ID_EMI_0 6
+#define MCHP_ESPI_MBAR_ID_EMI_1 7
+
+/* Use with MCHP_ESPI_IO_SERIRQ_REG(x) */
+#define MCHP_ESPI_SIRQ_MBOX 0 /* Host SIRQ */
+#define MCHP_ESPI_SIRQ_MBOX_SMI 1 /* Host SMI */
+#define MCHP_ESPI_SIRQ_8042_KB 2 /* KIRQ */
+#define MCHP_ESPI_SIRQ_8042_MS 3 /* MIRQ */
+#define MCHP_ESPI_SIRQ_ACPI_EC0_OBF 4
+#define MCHP_ESPI_SIRQ_ACPI_EC1_OBF 5
+#define MCHP_ESPI_SIRQ_ACPI_EC2_OBF 6
+#define MCHP_ESPI_SIRQ_ACPI_EC3_OBF 7
+#define MCHP_ESPI_SIRQ_UART0 9
+#define MCHP_ESPI_SIRQ_UART1 10
+#define MCHP_ESPI_SIRQ_EMI0_HEV 11 /* Host Event */
+#define MCHP_ESPI_SIRQ_EMI0_EC2H 12 /* EC to Host */
+#define MCHP_ESPI_SIRQ_EMI1_HEV 13
+#define MCHP_ESPI_SIRQ_EMI1_EC2H 14
+#define MCHP_ESPI_SIRQ_RTC 17
+#define MCHP_ESPI_SIRQ_EC 18
+#define MCHP_ESPI_SIRQ_UART2 19
+
+#define MCHP_ESPI_MSVW_BASE (MCHP_ESPI_VW_BASE)
+#define MCHP_ESPI_SMVW_BASE ((MCHP_ESPI_VW_BASE) + 0x200ul)
+
+/*
+ * eSPI RESET, channel enables and operations except Master-to-Slave
+ * WWires are all on GIRQ19
+ */
+#define MCHP_ESPI_GIRQ 19
+#define MCHP_ESPI_PC_GIRQ_BIT BIT(0)
+#define MCHP_ESPI_BM1_GIRQ_BIT BIT(1)
+#define MCHP_ESPI_BM2_GIRQ_BIT BIT(2)
+#define MCHP_ESPI_LTR_GIRQ_BIT BIT(3)
+#define MCHP_ESPI_OOB_TX_GIRQ_BIT BIT(4)
+#define MCHP_ESPI_OOB_RX_GIRQ_BIT BIT(5)
+#define MCHP_ESPI_FC_GIRQ_BIT BIT(6)
+#define MCHP_ESPI_RESET_GIRQ_BIT BIT(7)
+#define MCHP_ESPI_VW_EN_GIRQ_BIT BIT(8)
+#define MCHP_ESPI_SAF_DONE_GIRQ_BIT BIT(9)
+#define MCHP_ESPI_SAF_ERR_GIRQ_BIT BIT(10)
+
+/*
+ * eSPI Master-to-Slave WWire interrupts are on GIRQ24 and GIRQ25
+ */
+#define MCHP_ESPI_MSVW_0_6_GIRQ 24
+#define MCHP_ESPI_MSVW_7_10_GIRQ 25
+/*
+ * Four source bits, SRC[0:3] per Master-to-Slave register
+ * v = MSVW [0:10]
+ * n = VWire SRC bit = [0:3]
+ */
+#define MCHP_ESPI_MSVW_GIRQ(v) (24 + ((v) > 6 ? 1 : 0))
+
+#define MCHP_ESPI_MSVW_SRC_GIRQ_BIT(v, n) \
+	(((v) > 6) ? (1ul << (((v)-7) + (n))) : (1ul << ((v) + (n))))
+
+/* DMA */
+#define MCHP_DMA_MAX_CHAN 12
+#define MCHP_DMA_CH_OFS 0x40
+#define MCHP_DMA_CH_OFS_BITPOS 6
+#define MCHP_DMA_CH_BASE (MCHP_DMA_BASE + MCHP_DMA_CH_OFS)
+
+/*
+ * Available DMA channels.
+ * On MCHP, any DMA channel may serve any device. Since we have
+ * 12 channels and 12 devices request signals, we make each channel
+ * dedicated to the device of the same number.
+ */
+enum dma_channel {
+	/* Channel numbers */
+	MCHP_DMAC_I2C0_SLAVE = 0,
+	MCHP_DMAC_I2C0_MASTER,
+	MCHP_DMAC_I2C1_SLAVE,
+	MCHP_DMAC_I2C1_MASTER,
+	MCHP_DMAC_I2C2_SLAVE,
+	MCHP_DMAC_I2C2_MASTER,
+	MCHP_DMAC_I2C3_SLAVE,
+	MCHP_DMAC_I2C3_MASTER,
+	MCHP_DMAC_I2C4_SLAVE,
+	MCHP_DMAC_I2C4_MASTER,
+	MCHP_DMAC_QMSPI0_TX,
+	MCHP_DMAC_QMSPI0_RX,
+	/* Channel count */
+	MCHP_DMAC_COUNT,
+};
+
+/*
+ * Peripheral device DMA Device ID's for bits [15:9]
+ * in DMA channel control register.
+ */
+#define MCHP_DMA_I2C0_SLV_REQ_ID 0
+#define MCHP_DMA_I2C0_MTR_REQ_ID 1
+#define MCHP_DMA_I2C1_SLV_REQ_ID 2
+#define MCHP_DMA_I2C1_MTR_REQ_ID 3
+#define MCHP_DMA_I2C2_SLV_REQ_ID 4
+#define MCHP_DMA_I2C2_MTR_REQ_ID 5
+#define MCHP_DMA_I2C3_SLV_REQ_ID 6
+#define MCHP_DMA_I2C3_MTR_REQ_ID 7
+#define MCHP_DMA_I2C4_SLV_REQ_ID 8
+#define MCHP_DMA_I2C4_MTR_REQ_ID 9
+#define MCHP_DMA_QMSPI0_TX_REQ_ID 10
+#define MCHP_DMA_QMSPI0_RX_REQ_ID 11
+
+/*
+ * Hardware delay register.
+ * Write of 0 <= n <= 31 will stall the Cortex-M4
+ * for n+1 microseconds. Interrupts will not be
+ * serviced during the delay period. Reads have
+ * no effect.
+ */
+#define MCHP_USEC_DELAY_REG_ADDR 0x10000000
+#define MCHP_USEC_DELAY(x) (REG8(MCHP_USEC_DELAY_REG_ADDR) = (x))
+
+#endif /* #ifndef __ASSEMBLER__ */
diff --git a/chip/mchp/registers-mec1701.h b/chip/mchp/registers-mec1701.h
new file mode 100644
index 0000000000..6894dc4056
--- /dev/null
+++ b/chip/mchp/registers-mec1701.h
@@ -0,0 +1,1334 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Register map for Microchip MEC170x family controllers
+ */
+
+#ifndef __CROS_EC_REGISTERS_H
+#error "This header file should not be included directly."
+#endif
+
+/*
+ * IRQ Numbers
+ * NOTE: GIRQ22 aggregated output and its sources are not connected to
+ * the NVIC.
+ */
+#define MCHP_IRQ_GIRQ8 0
+#define MCHP_IRQ_GIRQ9 1
+#define MCHP_IRQ_GIRQ10 2
+#define MCHP_IRQ_GIRQ11 3
+#define MCHP_IRQ_GIRQ12 4
+#define MCHP_IRQ_GIRQ13 5
+#define MCHP_IRQ_GIRQ14 6
+#define MCHP_IRQ_GIRQ15 7
+#define MCHP_IRQ_GIRQ16 8
+#define MCHP_IRQ_GIRQ17 9
+#define MCHP_IRQ_GIRQ18 10
+#define MCHP_IRQ_GIRQ19 11
+#define MCHP_IRQ_GIRQ20 12
+#define MCHP_IRQ_GIRQ21 13
+#define MCHP_IRQ_GIRQ23 14
+#define MCHP_IRQ_GIRQ24 15
+#define MCHP_IRQ_GIRQ25 16
+#define MCHP_IRQ_GIRQ26 17
+/* GIRQ13 direct sources */
+#define MCHP_IRQ_I2C_0 20
+#define MCHP_IRQ_I2C_1 21
+#define MCHP_IRQ_I2C_2 22
+#define MCHP_IRQ_I2C_3 23
+/* GIRQ14 direct sources */
+#define MCHP_IRQ_DMA_0 24
+#define MCHP_IRQ_DMA_1 25
+#define MCHP_IRQ_DMA_2 26
+#define MCHP_IRQ_DMA_3 27
+#define MCHP_IRQ_DMA_4 28
+#define MCHP_IRQ_DMA_5 29
+#define MCHP_IRQ_DMA_6 30
+#define MCHP_IRQ_DMA_7 31
+#define MCHP_IRQ_DMA_8 32
+#define MCHP_IRQ_DMA_9 33
+#define MCHP_IRQ_DMA_10 34
+#define MCHP_IRQ_DMA_11 35
+#define MCHP_IRQ_DMA_12 36
+#define MCHP_IRQ_DMA_13 37
+/* GIRQ15 direct sources */
+#define MCHP_IRQ_UART0 40
+#define MCHP_IRQ_UART1 41
+#define MCHP_IRQ_EMI0 42
+#define MCHP_IRQ_EMI1 43
+#define MCHP_IRQ_EMI2 44
+#define MCHP_IRQ_ACPIEC0_IBF 45
+#define MCHP_IRQ_ACPIEC0_OBE 46
+#define MCHP_IRQ_ACPIEC1_IBF 47
+#define MCHP_IRQ_ACPIEC1_OBE 48
+#define MCHP_IRQ_ACPIEC2_IBF 49
+#define MCHP_IRQ_ACPIEC2_OBE 50
+#define MCHP_IRQ_ACPIEC3_IBF 51
+#define MCHP_IRQ_ACPIEC3_OBE 52
+#define MCHP_IRQ_ACPIEC4_IBF 53
+#define MCHP_IRQ_ACPIEC4_OBE 54
+#define MCHP_IRQ_ACPIPM1_CTL 55
+#define MCHP_IRQ_ACPIPM1_EN 56
+#define MCHP_IRQ_ACPIPM1_STS 57
+#define MCHP_IRQ_8042EM_OBE 58
+#define MCHP_IRQ_8042EM_IBF 59
+#define MCHP_IRQ_MAILBOX_DATA 60
+#define MCHP_IRQ_PORT80DBG0 62
+#define MCHP_IRQ_PORT80DBG1 63
+/* GIRQ16 direct sources */
+#define MCHP_IRQ_PKE_ERR 65
+#define MCHP_IRQ_PKE_END 66
+#define MCHP_IRQ_NDRNG 67
+#define MCHP_IRQ_AES 68
+#define MCHP_IRQ_HASH 69
+/* GIRQ17 direct sources */
+#define MCHP_IRQ_PECI_HOST 70
+#define MCHP_IRQ_TACH_0 71
+#define MCHP_IRQ_TACH_1 72
+#define MCHP_IRQ_TACH_2 73
+#define MCHP_IRQ_FAN0_FAIL 74
+#define MCHP_IRQ_FAN0_STALL 75
+#define MCHP_IRQ_FAN1_FAIL 76
+#define MCHP_IRQ_FAN1_STALL 77
+#define MCHP_IRQ_ADC_SNGL 78
+#define MCHP_IRQ_ADC_RPT 79
+#define MCHP_IRQ_RCID0 80
+#define MCHP_IRQ_RCID1 81
+#define MCHP_IRQ_RCID2 82
+#define MCHP_IRQ_LED0_WDT 83
+#define MCHP_IRQ_LED1_WDT 84
+#define MCHP_IRQ_LED2_WDT 85
+#define MCHP_IRQ_LED3_WDT 86
+#define MCHP_IRQ_PHOT 87
+#define MCHP_IRQ_PWRGRD0 88
+#define MCHP_IRQ_PWRGRD1 89
+/* GIRQ18 direct sources */
+#define MCHP_IRQ_LPC 90
+#define MCHP_IRQ_QMSPI0 91
+#define MCHP_IRQ_SPI0_TX 92
+#define MCHP_IRQ_SPI0_RX 93
+#define MCHP_IRQ_SPI1_TX 94
+#define MCHP_IRQ_SPI1_RX 95
+#define MCHP_IRQ_BCM0_ERR 96
+#define MCHP_IRQ_BCM0_BUSY 97
+#define MCHP_IRQ_BCM1_ERR 98
+#define MCHP_IRQ_BCM1_BUSY 99
+#define MCHP_IRQ_PS2_0 100
+#define MCHP_IRQ_PS2_1 101
+#define MCHP_IRQ_PS2_2 102
+#define MCHP_IRQ_EEPROM 155
+/* GIRQ19 direct sources */
+#define MCHP_IRQ_ESPI_PC 103
+#define MCHP_IRQ_ESPI_BM1 104
+#define MCHP_IRQ_ESPI_BM2 105
+#define MCHP_IRQ_ESPI_LTR 106
+#define MCHP_IRQ_ESPI_OOB_UP 107
+#define MCHP_IRQ_ESPI_OOB_DN 108
+#define MCHP_IRQ_ESPI_FC 109
+#define MCHP_IRQ_ESPI_RESET 110
+#define MCHP_IRQ_ESPI_VW_EN 156
+/* GIRQ21 direct sources */
+#define MCHP_IRQ_RTOS_TIMER 111
+#define MCHP_IRQ_HTIMER0 112
+#define MCHP_IRQ_HTIMER1 113
+#define MCHP_IRQ_WEEK_ALARM 114
+#define MCHP_IRQ_SUBWEEK 115
+#define MCHP_IRQ_WEEK_SEC 116
+#define MCHP_IRQ_WEEK_SUBSEC 117
+#define MCHP_IRQ_WEEK_SYSPWR 118
+#define MCHP_IRQ_RTC 119
+#define MCHP_IRQ_RTC_ALARM 120
+#define MCHP_IRQ_VCI_OVRD_IN 121
+#define MCHP_IRQ_VCI_IN0 122
+#define MCHP_IRQ_VCI_IN1 123
+#define MCHP_IRQ_VCI_IN2 124
+#define MCHP_IRQ_VCI_IN3 125
+#define MCHP_IRQ_VCI_IN4 126
+#define MCHP_IRQ_VCI_IN5 127
+#define MCHP_IRQ_VCI_IN6 128
+#define MCHP_IRQ_PS20A_WAKE 129
+#define MCHP_IRQ_PS20B_WAKE 130
+#define MCHP_IRQ_PS21A_WAKE 131
+#define MCHP_IRQ_PS21B_WAKE 132
+#define MCHP_IRQ_PS2_2_WAKE 133
+#define MCHP_IRQ_ENVMON 134
+#define MCHP_IRQ_KSC_INT 135
+/* GIRQ23 direct sources */
+#define MCHP_IRQ_TIMER16_0 136
+#define MCHP_IRQ_TIMER16_1 137
+#define MCHP_IRQ_TIMER16_2 138
+#define MCHP_IRQ_TIMER16_3 139
+#define MCHP_IRQ_TIMER32_0 140
+#define MCHP_IRQ_TIMER32_1 141
+#define MCHP_IRQ_CNTR_TM0 142
+#define MCHP_IRQ_CNTR_TM1 143
+#define MCHP_IRQ_CNTR_TM2 144
+#define MCHP_IRQ_CNTR_TM3 145
+#define MCHP_IRQ_CCT_TMR 146
+#define MCHP_IRQ_CCT_CAP0 147
+#define MCHP_IRQ_CCT_CAP1 148
+#define MCHP_IRQ_CCT_CAP2 149
+#define MCHP_IRQ_CCT_CAP3 150
+#define MCHP_IRQ_CCT_CAP4 151
+#define MCHP_IRQ_CCT_CAP5 152
+#define MCHP_IRQ_CCT_CMP0 153
+#define MCHP_IRQ_CCT_CMP1 154
+/* Must match CONFIG_IRQ_COUNT in config_chip.h */
+#define MCHP_IRQ_MAX 157
+
+/* Block base addresses */
+#define MCHP_WDG_BASE 0x40000000
+#define MCHP_TMR16_0_BASE 0x40000c00
+#define MCHP_TMR32_0_BASE 0x40000c80
+#define MCHP_CNT16_0_BASE 0x40000d00
+#define MCHP_DMA_BASE 0x40002400
+#define MCHP_PROCHOT_BASE 0x40003400
+#define MCHP_I2C0_BASE 0x40004000
+#define MCHP_I2C1_BASE 0x40004400
+#define MCHP_I2C2_BASE 0x40004800
+#define MCHP_I2C3_BASE 0x40004C00
+#define MCHP_QMSPI0_BASE 0x40005400
+#define MCHP_PWM_0_BASE 0x40005800
+#define MCHP_TACH_0_BASE 0x40006000
+#define MCHP_PECI_BASE 0x40006400
+#define MCHP_RTMR_BASE 0x40007400
+#define MCHP_ADC_BASE 0x40007c00
+#define MCHP_TFDP_BASE 0x40008c00
+#define MCHP_GPSPI0_BASE 0x40009400
+#define MCHP_GPSPI1_BASE 0x40009480
+#define MCHP_HTIMER_BASE 0x40009800
+#define MCHP_KEYSCAN_BASE 0x40009c00
+#define MCHP_RPM2PWM0_BASE 0x4000a000
+#define MCHP_RPM2PWM1_BASE 0x4000a080
+#define MCHP_VBAT_BASE 0x4000a400
+#define MCHP_VBAT_RAM_BASE 0x4000a800
+#define MCHP_WKTIMER_BASE 0x4000ac80
+#define MCHP_BBLED_0_BASE 0x4000B800
+#define MCHP_INT_BASE 0x4000e000
+#define MCHP_EC_BASE 0x4000fc00
+
+#define MCHP_PCR_BASE 0x40080100
+#define MCHP_GPIO_BASE 0x40081000
+
+#define MCHP_MBOX_BASE 0x400f0000
+#define MCHP_8042_BASE 0x400f0400
+#define MCHP_ACPI_EC_0_BASE 0x400f0800
+#define MCHP_ACPI_PM1_BASE 0x400f1c00
+#define MCHP_UART0_BASE 0x400f2400
+#define MCHP_UART1_BASE 0x400f2800
+#define MCHP_LPC_BASE 0x400f3000
+#define MCHP_ESPI_IO_BASE 0x400f3400
+#define MCHP_ESPI_MEM_BASE 0x400f3800
+#define MCHP_EMI_0_BASE 0x400f4000
+#define MCHP_EMI_1_BASE 0x400f4400
+#define MCHP_EMI_2_BASE 0x400f4800
+#define MCHP_P80CAP0_BASE 0x400f8000
+#define MCHP_P80CAP1_BASE 0x400f8400
+#define MCHP_ESPI_VW_BASE 0x400f9c00
+#define MCHP_CHIP_BASE 0x400fff00
+
+#ifndef __ASSEMBLER__
+
+/*
+ * Helper function for RAM address aliasing
+ * NOTE: MCHP AHB masters do NOT require aliasing.
+ * Cortex-M4 bit-banding does require aliasing of the
+ * DATA SRAM region.
+ */
+#define MCHP_RAM_ALIAS(x) ((x) >= 0x118000 ? (x)-0x118000 + 0x20000000 : (x))
+
+/* EC Chip Configuration */
+/* 8-bit Device ID */
+#define MCHP_CHIP_DEV_ID REG8(MCHP_CHIP_BASE + 0x20)
+/* 8-bit Device Revision */
+#define MCHP_CHIP_DEV_REV REG8(MCHP_CHIP_BASE + 0x21)
+
+/* PCR clock control dividers */
+#define MCHP_PCR_CLK_CTL_FASTEST 1U
+#define MCHP_PCR_CLK_CTL_48MHZ 1U
+#define MCHP_PCR_CLK_CTL_12MHZ 4U
+
+/* Number of PCR Sleep Enable, Clock Required, and Reset registers */
+#define MCHP_PCR_SLP_RST_REG_MAX 5
+
+/* Sleep 0: Sleep Enable, Clock Required, and Reset bits */
+#define MCHP_PCR_JTAG BIT(0) /* CLKREQ only */
+#define MCHP_PCR_OTP BIT(1)
+#define MCHP_PCR_ISPI BIT(2)
+
+/* Command all blocks to sleep */
+#define MCHP_PCR_SLP_EN0_JTAG BIT(0)
+#define MCHP_PCR_SLP_EN0_OTP BIT(1)
+#define MCHP_PCR_SLP_EN0_ISPI BIT(2)
+#define MCHP_PCR_SLP_EN0_SLEEP 0xffffffff
+
+/*
+ * Encode register number and bit position
+ * b[4:0] = bit number
+ * b[10:8] = zero based register number
+ */
+#define MCHP_PCR_ERB(rnum, bnum) ((((rnum)&0x0f) << 8) | ((bnum)&0x1f))
+
+/* PCR Sleep 1: Sleep Enable, Clock Required, and Reset bits */
+#define MCHP_PCR_BTMR16_1 MCHP_PCR_ERB(1, 31)
+#define MCHP_PCR_BTMR16_0 MCHP_PCR_ERB(1, 30)
+#define MCHP_PCR_ECS MCHP_PCR_ERB(1, 29)
+#define MCHP_PCR_PWM8 MCHP_PCR_ERB(1, 27)
+#define MCHP_PCR_PWM7 MCHP_PCR_ERB(1, 26)
+#define MCHP_PCR_PWM6 MCHP_PCR_ERB(1, 25)
+#define MCHP_PCR_PWM5 MCHP_PCR_ERB(1, 24)
+#define MCHP_PCR_PWM4 MCHP_PCR_ERB(1, 23)
+#define MCHP_PCR_PWM3 MCHP_PCR_ERB(1, 22)
+#define MCHP_PCR_PWM2 MCHP_PCR_ERB(1, 21)
+#define MCHP_PCR_PWM1 MCHP_PCR_ERB(1, 20)
+#define MCHP_PCR_TACH2 MCHP_PCR_ERB(1, 12)
+#define MCHP_PCR_TACH1 MCHP_PCR_ERB(1, 11)
+#define MCHP_PCR_I2C0 MCHP_PCR_ERB(1, 10)
+#define MCHP_PCR_WDT MCHP_PCR_ERB(1, 9)
+#define MCHP_PCR_CPU MCHP_PCR_ERB(1, 8)
+#define MCHP_PCR_TFDP MCHP_PCR_ERB(1, 7)
+#define MCHP_PCR_DMA MCHP_PCR_ERB(1, 6)
+#define MCHP_PCR_PMC MCHP_PCR_ERB(1, 5)
+#define MCHP_PCR_PWM0 MCHP_PCR_ERB(1, 4)
+#define MCHP_PCR_TACH0 MCHP_PCR_ERB(1, 2)
+#define MCHP_PCR_PECI MCHP_PCR_ERB(1, 1)
+#define MCHP_PCR_ECIA MCHP_PCR_ERB(1, 0)
+
+/* Command all blocks to sleep */
+#define MCHP_PCR_SLP_EN1_BTMR16_1 BIT(31)
+#define MCHP_PCR_SLP_EN1_BTMR16_0 BIT(30)
+#define MCHP_PCR_SLP_EN1_ECS BIT(29)
+#define MCHP_PCR_SLP_EN1_PWM_ALL (BIT(4) + (0xff << 20))
+#define MCHP_PCR_SLP_EN1_PWM8 BIT(27)
+#define MCHP_PCR_SLP_EN1_PWM7 BIT(26)
+#define MCHP_PCR_SLP_EN1_PWM6 BIT(25)
+#define MCHP_PCR_SLP_EN1_PWM5 BIT(24)
+#define MCHP_PCR_SLP_EN1_PWM4 BIT(23)
+#define MCHP_PCR_SLP_EN1_PWM3 BIT(22)
+#define MCHP_PCR_SLP_EN1_PWM2 BIT(21)
+#define MCHP_PCR_SLP_EN1_PWM1 BIT(20)
+#define MCHP_PCR_SLP_EN1_TACH2 BIT(12)
+#define MCHP_PCR_SLP_EN1_TACH1 BIT(11)
+#define MCHP_PCR_SLP_EN1_I2C0 BIT(10)
+#define MCHP_PCR_SLP_EN1_WDT BIT(9)
+#define MCHP_PCR_SLP_EN1_CPU BIT(8)
+#define MCHP_PCR_SLP_EN1_TFDP BIT(7)
+#define MCHP_PCR_SLP_EN1_DMA BIT(6)
+#define MCHP_PCR_SLP_EN1_PMC BIT(5)
+#define MCHP_PCR_SLP_EN1_PWM0 BIT(4)
+#define MCHP_PCR_SLP_EN1_TACH0 BIT(2)
+#define MCHP_PCR_SLP_EN1_PECI BIT(1)
+#define MCHP_PCR_SLP_EN1_ECIA BIT(0)
+/* all sleep enable 1 bits */
+#define MCHP_PCR_SLP_EN1_SLEEP 0xffffffff
+/*
+ * block not used by default
+ * Do not sleep ECIA, PMC, CPU and ECS
+ */
+#define MCHP_PCR_SLP_EN1_UNUSED_BLOCKS 0xdffffede
+
+/* PCR Sleep 2: Sleep Enable, Clock Required 2, Reset bits */
+#define MCHP_PCR_P80CAP1 MCHP_PCR_ERB(2, 26)
+#define MCHP_PCR_P80CAP0 MCHP_PCR_ERB(2, 25)
+#define MCHP_PCR_ACPI_EC4 MCHP_PCR_ERB(2, 23)
+#define MCHP_PCR_ACPI_EC3 MCHP_PCR_ERB(2, 22)
+#define MCHP_PCR_ACPI_EC2 MCHP_PCR_ERB(2, 21)
+#define MCHP_PCR_ESPI MCHP_PCR_ERB(2, 19)
+#define MCHP_PCR_RTC MCHP_PCR_ERB(2, 18)
+#define MCHP_PCR_MBOX MCHP_PCR_ERB(2, 17)
+#define MCHP_PCR_8042 MCHP_PCR_ERB(2, 26)
+#define MCHP_PCR_ACPI_PM1 MCHP_PCR_ERB(2, 15)
+#define MCHP_PCR_ACPI_EC1 MCHP_PCR_ERB(2, 14)
+#define MCHP_PCR_ACPI_EC0 MCHP_PCR_ERB(2, 13)
+#define MCHP_PCR_GCFG MCHP_PCR_ERB(2, 12)
+#define MCHP_PCR_UART1 MCHP_PCR_ERB(2, 2)
+#define MCHP_PCR_UART0 MCHP_PCR_ERB(2, 1)
+#define MCHP_PCR_LPC MCHP_PCR_ERB(2, 0)
+
+/* Command all blocks to sleep */
+#define MCHP_PCR_SLP_EN2_P80CAP1 BIT(26)
+#define MCHP_PCR_SLP_EN2_P80CAP0 BIT(25)
+#define MCHP_PCR_SLP_EN2_ACPI_EC4 BIT(23)
+#define MCHP_PCR_SLP_EN2_ACPI_EC3 BIT(22)
+#define MCHP_PCR_SLP_EN2_ACPI_EC2 BIT(21)
+#define MCHP_PCR_SLP_EN2_ESPI_SCR BIT(20)
+#define MCHP_PCR_SLP_EN2_ESPI BIT(19)
+#define MCHP_PCR_SLP_EN2_RTC BIT(18)
+#define MCHP_PCR_SLP_EN2_MAILBOX BIT(17)
+#define MCHP_PCR_SLP_EN2_MIF8042 BIT(16)
+#define MCHP_PCR_SLP_EN2_ACPI_PM1 BIT(15)
+#define MCHP_PCR_SLP_EN2_ACPI_EC1 BIT(14)
+#define MCHP_PCR_SLP_EN2_ACPI_EC0 BIT(13)
+#define MCHP_PCR_SLP_EN2_GCFG BIT(12)
+#define MCHP_PCR_SLP_EN2_UART1 BIT(2)
+#define MCHP_PCR_SLP_EN2_UART0 BIT(1)
+#define MCHP_PCR_SLP_EN2_LPC BIT(0)
+/* all sleep enable 2 bits */
+#define MCHP_PCR_SLP_EN2_SLEEP 0xffffffff
+
+/* PCR Sleep 3: Sleep Enable, Clock Required, and Reset */
+#define MCHP_PCR_PWM9 MCHP_PCR_ERB(3, 31)
+#define MCHP_PCR_CCT0 MCHP_PCR_ERB(3, 30)
+#define MCHP_PCR_HTMR1 MCHP_PCR_ERB(3, 29)
+#define MCHP_PCR_AESHASH MCHP_PCR_ERB(3, 28)
+#define MCHP_PCR_RNG MCHP_PCR_ERB(3, 27)
+#define MCHP_PCR_PKE MCHP_PCR_ERB(3, 26)
+#define MCHP_PCR_LED3 MCHP_PCR_ERB(3, 25)
+#define MCHP_PCR_BTMR32_1 MCHP_PCR_ERB(3, 24)
+#define MCHP_PCR_BTMR32_0 MCHP_PCR_ERB(3, 23)
+#define MCHP_PCR_BTMR16_3 MCHP_PCR_ERB(3, 22)
+#define MCHP_PCR_BTMR16_2 MCHP_PCR_ERB(3, 21)
+#define MCHP_PCR_GPSPI1 MCHP_PCR_ERB(3, 20)
+#define MCHP_PCR_BCM0 MCHP_PCR_ERB(3, 19)
+#define MCHP_PCR_LED2 MCHP_PCR_ERB(3, 18)
+#define MCHP_PCR_LED1 MCHP_PCR_ERB(3, 17)
+#define MCHP_PCR_LED0 MCHP_PCR_ERB(3, 16)
+#define MCHP_PCR_I2C3 MCHP_PCR_ERB(3, 15)
+#define MCHP_PCR_I2C2 MCHP_PCR_ERB(3, 14)
+#define MCHP_PCR_I2C1 MCHP_PCR_ERB(3, 13)
+#define MCHP_PCR_RPMPWM0 MCHP_PCR_ERB(3, 12)
+#define MCHP_PCR_KEYSCAN MCHP_PCR_ERB(3, 11)
+#define MCHP_PCR_HTMR0 MCHP_PCR_ERB(3, 10)
+#define MCHP_PCR_GPSPI0 MCHP_PCR_ERB(3, 9)
+#define MCHP_PCR_PS2_2 MCHP_PCR_ERB(3, 7)
+#define MCHP_PCR_PS2_1 MCHP_PCR_ERB(3, 6)
+#define MCHP_PCR_PS2_0 MCHP_PCR_ERB(3, 5)
+#define MCHP_PCR_ADC MCHP_PCR_ERB(3, 3)
+
+/* Command blocks to sleep */
+#define MCHP_PCR_SLP_EN3_PWM9 BIT(31)
+#define MCHP_PCR_SLP_EN3_CCT0 BIT(30)
+#define MCHP_PCR_SLP_EN3_HTMR1 BIT(29)
+#define MCHP_PCR_SLP_EN3_AESHASH BIT(28)
+#define MCHP_PCR_SLP_EN3_RNG BIT(27)
+#define MCHP_PCR_SLP_EN3_PKE BIT(26)
+#define MCHP_PCR_SLP_EN3_LED3 BIT(25)
+#define MCHP_PCR_SLP_EN3_BTMR32_1 BIT(24)
+#define MCHP_PCR_SLP_EN3_BTMR32_0 BIT(23)
+#define MCHP_PCR_SLP_EN3_BTMR16_3 BIT(22)
+#define MCHP_PCR_SLP_EN3_BTMR16_2 BIT(21)
+#define MCHP_PCR_SLP_EN3_I2C4 BIT(20)
+#define MCHP_PCR_SLP_EN3_BCM0 BIT(19)
+#define MCHP_PCR_SLP_EN3_LED2 BIT(18)
+#define MCHP_PCR_SLP_EN3_LED1 BIT(17)
+#define MCHP_PCR_SLP_EN3_LED0 BIT(16)
+#define MCHP_PCR_SLP_EN3_I2C3 BIT(15)
+#define MCHP_PCR_SLP_EN3_I2C2 BIT(14)
+#define MCHP_PCR_SLP_EN3_I2C1 BIT(13)
+#define MCHP_PCR_SLP_EN3_RPM2PWM0 BIT(12)
+#define MCHP_PCR_SLP_EN3_KEYSCAN BIT(11)
+#define MCHP_PCR_SLP_EN3_HTMR0 BIT(10)
+#define MCHP_PCR_SLP_EN3_GPSPI0 BIT(9)
+#define MCHP_PCR_SLP_EN3_PS2_2 BIT(7)
+#define MCHP_PCR_SLP_EN3_PS2_1 BIT(6)
+#define MCHP_PCR_SLP_EN3_PS2_0 BIT(5)
+#define MCHP_PCR_SLP_EN3_ADC BIT(3)
+#define MCHP_PCR_SLP_EN3_ALL_CRYPTO (0x07 << 26)
+/* all sleep enable 3 bits */
+#define MCHP_PCR_SLP_EN3_SLEEP 0xffffffff
+#define MCHP_PCR_SLP_EN3_PWM_ALL (MCHP_PCR_SLP_EN3_PWM9)
+
+/* PCR Sleep 4: Sleep Enable, Clock Required, Reset */
+#define MCHP_PCR_FJCL MCHP_PCR_ERB(4, 15)
+#define MCHP_PCR_PSPI MCHP_PCR_ERB(4, 14)
+#define MCHP_PCR_PROCHOT MCHP_PCR_ERB(4, 13)
+#define MCHP_PCR_RCID2 MCHP_PCR_ERB(4, 12)
+#define MCHP_PCR_RCID1 MCHP_PCR_ERB(4, 11)
+#define MCHP_PCR_RCID0 MCHP_PCR_ERB(4, 10)
+#define MCHP_PCR_BCM1 MCHP_PCR_ERB(4, 9)
+#define MCHP_PCR_QMSPI MCHP_PCR_ERB(4, 8)
+#define MCHP_PCR_RPMPWM1 MCHP_PCR_ERB(4, 7)
+#define MCHP_PCR_RTMR MCHP_PCR_ERB(4, 6)
+#define MCHP_PCR_CNT16_3 MCHP_PCR_ERB(4, 5)
+#define MCHP_PCR_CNT16_2 MCHP_PCR_ERB(4, 4)
+#define MCHP_PCR_CNT16_1 MCHP_PCR_ERB(4, 3)
+#define MCHP_PCR_CNT16_0 MCHP_PCR_ERB(4, 2)
+#define MCHP_PCR_PWM11 MCHP_PCR_ERB(4, 1)
+#define MCHP_PCR_PWM10 MCHP_PCR_ERB(4, 0)
+
+/* Command blocks to sleep */
+#define MCHP_PCR_SLP_EN4_FJCL BIT(15)
+#define MCHP_PCR_SLP_EN4_PSPI BIT(14)
+#define MCHP_PCR_SLP_EN4_PROCHOT BIT(13)
+#define MCHP_PCR_SLP_EN4_RCID2 BIT(12)
+#define MCHP_PCR_SLP_EN4_RCID1 BIT(11)
+#define MCHP_PCR_SLP_EN4_RCID0 BIT(10)
+#define MCHP_PCR_SLP_EN4_QMSPI BIT(8)
+#define MCHP_PCR_SLP_EN4_RPMPWM1 BIT(7)
+#define MCHP_PCR_SLP_EN4_RTMR BIT(6)
+#define MCHP_PCR_SLP_EN4_CNT16_3 BIT(5)
+#define MCHP_PCR_SLP_EN4_CNT16_2 BIT(4)
+#define MCHP_PCR_SLP_EN4_CNT16_1 BIT(3)
+#define MCHP_PCR_SLP_EN4_CNT16_0 BIT(2)
+#define MCHP_PCR_SLP_EN4_PWM11 BIT(1)
+#define MCHP_PCR_SLP_EN4_PWM10 BIT(0)
+
+/* all sleep enable 4 bits */
+#define MCHP_PCR_SLP_EN4_SLEEP 0xffffffff
+#define MCHP_PCR_SLP_EN4_PWM_ALL \
+	(MCHP_PCR_SLP_EN4_PWM10 | MCHP_PCR_SLP_EN4_PWM11)
+
+/* Allow all blocks to request clocks */
+#define MCHP_PCR_SLP_EN0_WAKE (~(MCHP_PCR_SLP_EN0_SLEEP))
+#define MCHP_PCR_SLP_EN1_WAKE (~(MCHP_PCR_SLP_EN1_SLEEP))
+#define MCHP_PCR_SLP_EN2_WAKE (~(MCHP_PCR_SLP_EN2_SLEEP))
+#define MCHP_PCR_SLP_EN3_WAKE (~(MCHP_PCR_SLP_EN3_SLEEP))
+#define MCHP_PCR_SLP_EN4_WAKE (~(MCHP_PCR_SLP_EN4_SLEEP))
+
+/* Bit defines for MCHP_PCR_PWR_RST_STS */
+#define MCHP_PWR_RST_STS_MASK_RO 0xc8c
+#define MCHP_PWR_RST_STS_MASK_RWC 0x060
+#define MCHP_PWR_RST_STS_MASK \
+	((MCHP_PWR_RST_STS_MASK_RO) | (MCHP_PWR_RST_STS_MASK_RWC))
+
+#define MCHP_PWR_RST_STS_ESPI_CLK_ACT BIT(11) /* RO */
+#define MCHP_PWR_RST_STS_32K_ACT BIT(10) /* RO */
+#define MCHP_PWR_RST_STS_JTAG_RSTN BIT(7) /* RO */
+#define MCHP_PWR_RST_STS_SYS BIT(6) /* R/WC */
+/* same function, old bit name */
+#define MCHP_PWR_RST_STS_VTR BIT(6)
+#define MCHP_PWR_RST_STS_VBAT BIT(5) /* R/WC */
+#define MCHP_PWR_RST_STS_HOST BIT(3) /* RO */
+#define MCHP_PWR_RST_STS_VCC_PWRGD BIT(2) /* RO */
+
+/* Bit defines for MCHP_PCR_PWR_RST_CTL */
+#define MCHP_PCR_PWR_HOST_RST_SEL_BITPOS 8
+#define MCHP_PCR_PWR_HOST_RST_PCI_RESET BIT(8)
+#define MCHP_PCR_PWR_HOST_RST_ESPI_PLTRST (0 << 8)
+#define MCHP_PCR_PWR_OK_INV_BITPOS 0
+
+/* Bit defines for MCHP_PCR_SYS_RST */
+#define MCHP_PCR_SYS_SOFT_RESET BIT(8)
+
+/* EC Subsystem */
+#define MCHP_EC_AHB_ERR REG32(MCHP_EC_BASE + 0x04)
+#define MCHP_EC_ID_RO REG32(MCHP_EC_BASE + 0x10)
+#define MCHP_EC_AHB_ERR_EN REG32(MCHP_EC_BASE + 0x14)
+#define MCHP_EC_INT_CTRL REG32(MCHP_EC_BASE + 0x18)
+#define MCHP_EC_TRACE_EN REG32(MCHP_EC_BASE + 0x1c)
+#define MCHP_EC_JTAG_EN REG32(MCHP_EC_BASE + 0x20)
+#define MCHP_EC_WDT_CNT REG32(MCHP_EC_BASE + 0x28)
+#define MCHP_EC_AES_SHA_SWAP_CTRL REG8(MCHP_EC_BASE + 0x2c)
+#define MCHP_EC_PECI_DISABLE REG8(MCHP_EC_BASE + 0x40)
+#define MCHP_EC_CRYPTO_SRESET REG8(MCHP_EC_BASE + 0x5c)
+#define MCHP_EC_GPIO_BANK_PWR REG8(MCHP_EC_BASE + 0x64)
+
+/* AHB ERR Enable bit[0]=0(enable), 1(disable) */
+#define MCHP_EC_AHB_ERROR_ENABLE 0
+#define MCHP_EC_AHB_ERROR_DISABLE 1
+
+/* MCHP_EC_JTAG_EN bit definitions */
+#define MCHP_JTAG_ENABLE 0x01
+/* bits [2:1] */
+#define MCHP_JTAG_MODE_4PIN 0x00
+/* ARM 2-pin SWD plus 1-pin Serial Wire Viewer (ITM) */
+#define MCHP_JTAG_MODE_SWD_SWV 0x02
+/* ARM 2-pin SWD with no SWV */
+#define MCHP_JTAG_MODE_SWD 0x04
+
+/* MCHP_EC_CRYPTO_SRESET bit definitions. Bits cleared by HW */
+#define MCHP_CRYPTO_NDRNG_SRST 0x01
+#define MCHP_CRYPTO_PKE_SRST 0x02
+#define MCHP_CRYPTO_AES_SHA_SRST 0x04
+#define MCHP_CRYPTO_ALL_SRST 0x07
+
+/* MCHP_GPIO_BANK_PWR bit definitions */
+#define MCHP_EC_GPIO_BANK_PWR_MASK 0x86
+#define MCHP_EC_GPIO_BANK_PWR_VTR2_18 0x02
+#define MCHP_EC_GPIO_BANK_PWR_VTR3_18 0x04
+#define MCHP_EC_GPIO_BANK_PWR_LOCK 0x80
+
+/* EC Interrupt aggregator (ECIA) */
+#define MCHP_INT_GIRQ_LEN 20 /* 5 32-bit registers */
+#define MCHP_INT_GIRQ_FIRST 8
+#define MCHP_INT_GIRQ_LAST 26
+#define MCHP_INT_GIRQ_NUM (26 - 8 + 1)
+/* MCHP_INT_GIRQ_FIRST <= x <= MCHP_INT_GIRQ_LAST */
+#define MCHP_INTx_BASE(x) (MCHP_INT_BASE + (((x)-8) * MCHP_INT_GIRQ_LEN))
+
+/*
+ * GPIO GIRQ's are not direct capable
+ * GIRQ08 GPIO 0140 - 0176
+ * GIRQ09 GPIO 0100 - 0136
+ * GIRQ10 GPIO 040 - 076
+ * GIRQ11 GPIO 000 - 036
+ * GIRQ12 GPIO 0200 - 0236
+ * GIRQ26 GPIO 0240 - 0276
+ * Other GIRQ's not direct capable:
+ * GIRQ22 wake peripheral clock only
+ * GIRQ24, GIRQ25 eSPI host to endpoint virtual wires
+ */
+#define MCHP_INT_AGGR_ONLY_BITMAP 0x07401F00U
+#define MCHP_INT_DIRECT_CAPABLE_BITMAP 0x00BFE000U
+
+/* GIRQ13 I2C controllers. Direct capable */
+#define MCHP_INT13_I2C(x) (1ul << (x))
+
+/* GIRQ14 DMA channels 0 - 13. Direct capable */
+#define MCHP_INT14_DMA(x) (1ul << (x))
+
+/* GIQ15 interrupt sources. Direct capable */
+#define MCHP_INT15_UART_0 BIT(0)
+#define MCHP_INT15_UART_1 BIT(1)
+#define MCHP_INT15_EMI_0 BIT(2)
+#define MCHP_INT15_EMI_1 BIT(3)
+#define MCHP_INT15_EMI_2 BIT(4)
+#define MCHP_INT15_ACPI_EC0_IBF BIT(5)
+#define MCHP_INT15_ACPI_EC0_OBE BIT(6)
+#define MCHP_INT15_ACPI_EC1_IBF BIT(7)
+#define MCHP_INT15_ACPI_EC1_OBE BIT(8)
+#define MCHP_INT15_ACPI_EC2_IBF BIT(9)
+#define MCHP_INT15_ACPI_EC2_OBE BIT(10)
+#define MCHP_INT15_ACPI_EC3_IBF BIT(11)
+#define MCHP_INT15_ACPI_EC3_OBE BIT(12)
+#define MCHP_INT15_ACPI_EC4_IBF BIT(13)
+#define MCHP_INT15_ACPI_EC4_OBE BIT(14)
+#define MCHP_INT15_ACPI_PM1_CTL BIT(15)
+#define MCHP_INT15_ACPI_PM1_EN BIT(16)
+#define MCHP_INT15_ACPI_PM1_STS BIT(17)
+#define MCHP_INT15_8042_OBE BIT(18)
+#define MCHP_INT15_8042_IBF BIT(19)
+#define MCHP_INT15_MAILBOX BIT(20)
+#define MCHP_INT15_P80_0 BIT(22)
+#define MCHP_INT15_P80_1 BIT(23)
+#define MCHP_INT15_P80(x) BIT(22 + ((x)&0x01U))
+
+/* GIRQ16 interrupt sources. Direct capable */
+#define MCHP_INT16_PKE_ERR BIT(0)
+#define MCHP_INT16_PKE_DONE BIT(1)
+#define MCHP_INT16_RNG_DONE BIT(2)
+#define MCHP_INT16_AES_DONE BIT(3)
+#define MCHP_INT16_HASH_DONE BIT(4)
+
+/* GIR17 interrupt sources. Direct capable */
+#define MCHP_INT17_PECI BIT(0)
+#define MCHP_INT17_TACH_0 BIT(1)
+#define MCHP_INT17_TACH_1 BIT(2)
+#define MCHP_INT17_TACH_2 BIT(3)
+#define MCHP_INT17_RPM2PWM0_FAIL BIT(4)
+#define MCHP_INT17_RPM2PWM0_STALL BIT(5)
+#define MCHP_INT17_RPM2PWM1_FAIL BIT(6)
+#define MCHP_INT17_RPM2PWM1_STALL BIT(7)
+#define MCHP_INT17_ADC_SINGLE BIT(8)
+#define MCHP_INT17_ADC_REPEAT BIT(9)
+#define MCHP_INT17_RCID_0 BIT(10)
+#define MCHP_INT17_RCID_1 BIT(11)
+#define MCHP_INT17_RCID_2 BIT(12)
+#define MCHP_INT17_LED_WDT_0 BIT(13)
+#define MCHP_INT17_LED_WDT_1 BIT(14)
+#define MCHP_INT17_LED_WDT_2 BIT(15)
+#define MCHP_INT17_LED_WDT_3 BIT(16)
+#define MCHP_INT17_PROCHOT BIT(17)
+#define MCHP_INT17_PWRGRD0 BIT(18)
+#define MCHP_INT17_PWRGRD1 BIT(19)
+
+/* GIRQ18 interrupt sources. Direct capable */
+#define MCHP_INT18_LPC_ERR BIT(0)
+#define MCHP_INT18_QMSPI BIT(1)
+#define MCHP_INT18_GPSPI0_TXBE BIT(2)
+#define MCHP_INT18_GPSPI0_RXBF BIT(3)
+#define MCHP_INT18_GPSPI1_TXBE BIT(4)
+#define MCHP_INT18_GPSPI1_RXBF BIT(5)
+#define MCHP_INT18_BCM0_BUSY BIT(6)
+#define MCHP_INT18_BCM0_ERR BIT(7)
+#define MCHP_INT18_BCM1_BUSY BIT(8)
+#define MCHP_INT18_BCM1_ERR BIT(9)
+#define MCHP_INT18_PS2_0 BIT(10)
+#define MCHP_INT18_PS2_1 BIT(11)
+#define MCHP_INT18_PS2_2 BIT(12)
+#define MCHP_INT18_PSPI BIT(13)
+
+/* GIRQ19 interrupt sources. Direct capable */
+#define MCHP_INT19_ESPI_PC BIT(0)
+#define MCHP_INT19_ESPI_BM1 BIT(1)
+#define MCHP_INT19_ESPI_BM2 BIT(2)
+#define MCHP_INT19_ESPI_LTR BIT(3)
+#define MCHP_INT19_ESPI_OOB_TX BIT(4)
+#define MCHP_INT19_ESPI_OOB_RX BIT(5)
+#define MCHP_INT19_ESPI_FC BIT(6)
+#define MCHP_INT19_ESPI_RESET BIT(7)
+#define MCHP_INT19_ESPI_VW_EN BIT(8)
+
+/* GIRQ20 interrupt sources. Direct capable */
+#define MCHP_INT20_STAP_OBF BIT(0)
+#define MCHP_INT20_STAP_IBF BIT(1)
+#define MCHP_INT20_STAP_WAKE BIT(2)
+#define MCHP_INT20_ISPI BIT(8)
+
+/* GIRQ21 interrupt sources. Direct capable */
+#define MCHP_INT21_RTMR BIT(0)
+#define MCHP_INT21_HTMR_0 BIT(1)
+#define MCHP_INT21_HTMR_1 BIT(2)
+#define MCHP_INT21_WEEK_ALARM BIT(3)
+#define MCHP_INT21_WEEK_SUB BIT(4)
+#define MCHP_INT21_WEEK_1SEC BIT(5)
+#define MCHP_INT21_WEEK_1SEC_SUB BIT(6)
+#define MCHP_INT21_WEEK_PWR_PRES BIT(7)
+#define MCHP_INT21_RTC BIT(8)
+#define MCHP_INT21_RTC_ALARM BIT(9)
+#define MCHP_INT21_VCI_OVRD BIT(10)
+#define MCHP_INT21_VCI_IN0 BIT(11)
+#define MCHP_INT21_VCI_IN1 BIT(12)
+#define MCHP_INT21_VCI_IN2 BIT(13)
+#define MCHP_INT21_VCI_IN3 BIT(14)
+#define MCHP_INT21_VCI_IN4 BIT(15)
+#define MCHP_INT21_VCI_IN5 BIT(16)
+#define MCHP_INT21_VCI_IN6 BIT(17)
+#define MCHP_INT21_PS2_0A_WAKE BIT(18)
+#define MCHP_INT21_PS2_0B_WAKE BIT(19)
+#define MCHP_INT21_PS2_1A_WAKE BIT(20)
+#define MCHP_INT21_PS2_1B_WAKE BIT(21)
+#define MCHP_INT21_PS2_2_WAKE BIT(22)
+#define MCHP_INT21_ENVMON BIT(24)
+#define MCHP_INT21_KEYSCAN BIT(25)
+
+/* GIRQ22 peripheral wake only. GIRQ22 not connected to NVIC */
+#define MCHP_INT22_WAKE_ONLY_LPC BIT(0)
+#define MCHP_INT22_WAKE_ONLY_I2C0 BIT(1)
+#define MCHP_INT22_WAKE_ONLY_I2C1 BIT(2)
+#define MCHP_INT22_WAKE_ONLY_I2C2 BIT(3)
+#define MCHP_INT22_WAKE_ONLY_I2C3 BIT(4)
+#define MCHP_INT22_WAKE_ONLY_ESPI BIT(9)
+
+/* GIRQ23 sources. Direct capable */
+#define MCHP_INT23_BTMR16_0 BIT(0)
+#define MCHP_INT23_BTMR16_1 BIT(1)
+#define MCHP_INT23_BTMR16_2 BIT(2)
+#define MCHP_INT23_BTMR16_3 BIT(3)
+#define MCHP_INT23_BTMR32_0 BIT(4)
+#define MCHP_INT23_BTMR32_1 BIT(5)
+#define MCHP_INT23_CNT16_0 BIT(6)
+#define MCHP_INT23_CNT16_1 BIT(7)
+#define MCHP_INT23_CNT16_2 BIT(8)
+#define MCHP_INT23_CNT16_3 BIT(9)
+#define MCHP_INT23_CCT BIT(10)
+#define MCHP_INT23_CCT_CAP0 BIT(11)
+#define MCHP_INT23_CCT_CAP1 BIT(12)
+#define MCHP_INT23_CCT_CAP2 BIT(13)
+#define MCHP_INT23_CCT_CAP3 BIT(14)
+#define MCHP_INT23_CCT_CAP4 BIT(15)
+#define MCHP_INT23_CCT_CAP6 BIT(16)
+#define MCHP_INT23_CCT_CMP0 BIT(17)
+#define MCHP_INT23_CCT_CMP1 BIT(18)
+
+/* GIRQ24 sources. Master-to-Slave v=[0:6], Source=[0:3] */
+#define MCHP_INT24_MSVW_SRC(v, s) (1ul << ((4 * (v)) + (s)))
+
+/* GIRQ25 sources Master-to-Slave v=[7:10], Source=[0:3] */
+#define MCHP_INT25_MSVW_SRC(v, s) (1ul << ((4 * ((v)-7)) + (s)))
+
+/* UART Peripheral 0 <= x <= 1 */
+#define MCHP_UART_INSTANCES 2
+#define MCHP_UART_SPACING 0x400
+#define MCHP_UART_CFG_OFS 0x300
+#define MCHP_UART_CONFIG_BASE(x) \
+	(MCHP_UART0_BASE + MCHP_UART_CFG_OFS + ((x)*MCHP_UART_SPACING))
+#define MCHP_UART_RUNTIME_BASE(x) (MCHP_UART0_BASE + ((x)*MCHP_UART_SPACING))
+#define MCHP_UART_GIRQ 15
+#define MCHP_UART0_GIRQ_BIT (MCHP_INT15_UART_0)
+#define MCHP_UART1_GIRQ_BIT (MCHP_INT15_UART_1)
+#define MCHP_UART_GIRQ_BIT(x) BIT(x)
+/* Bit defines for MCHP_UARTx_LSR */
+#define MCHP_LSR_TX_EMPTY BIT(5)
+
+/*
+ * GPIO
+ * MCHP each Port contains 32 GPIO's.
+ * GPIO Control 1 registers are 32-bit registers starting at
+ * MCHP_GPIO_BASE.
+ * index = octal GPIO number from MCHP specification.
+ * port/bank = index >> 5
+ * id = index & 0x1F
+ *
+ * The port/bank, id pair may also be used to access GPIO's via
+ * parallel I/O registers if GPIO control is configured for
+ * parallel I/O.
+ *
+ * From ec/chip/mec1701/config_chip.h
+ * #define GPIO_PIN(index) ((index) >> 5), ((index) & 0x1F)
+ *
+ * GPIO Control 1 Address = 0x40081000 + (((bank << 5) + id) << 2)
+ *
+ * Example: GPIO043, Control 1 register address = 0x4008108c
+ * port/bank = 0x23 >> 5 = 1
+ * id        = 0x23 & 0x1F = 0x03
+ * Control 1 Address = 0x40081000 + ((BIT(5) + 0x03) << 2) = 0x4008108c
+ *
+ * Example: GPIO235, Control 1 register address = 0x40081274
+ * port/bank = 0x9d >> 5   = 4
+ * id        = 0x9d & 0x1f = 0x1d
+ * Control 1 Address = 0x40081000 + (((4 << 5) + 0x1d) << 2) = 0x40081274
+ *
+ */
+#define MCHP_GPIO_CTL(port, id) \
+	REG32(MCHP_GPIO_BASE + (((port << 5) + id) << 2))
+
+/* MCHP implements 6 GPIO ports */
+#define MCHP_GPIO_MAX_PORT 6
+#define UNIMPLEMENTED_GPIO_BANK MCHP_GPIO_MAX_PORT
+/*
+ * In MECxxxx documentation GPIO numbers are octal, each control
+ * register is located on a 32-bit boundary.
+ */
+#define MCHP_GPIO_CTRL(gpio_num) REG32(MCHP_GPIO_BASE + ((gpio_num) << 2))
+
+/*
+ * GPIO control register bit fields
+ */
+#define MCHP_GPIO_CTRL_PUD_BITPOS 0
+#define MCHP_GPIO_CTRL_PUD_MASK0 0x03
+#define MCHP_GPIO_CTRL_PUD_MASK 0x03
+#define MCHP_GPIO_CTRL_PUD_NONE 0x00
+#define MCHP_GPIO_CTRL_PUD_PU 0x01
+#define MCHP_GPIO_CTRL_PUD_PD 0x02
+#define MCHP_GPIO_CTRL_PUD_KEEPER 0x03
+#define MCHP_GPIO_CTRL_PWR_BITPOS 2
+#define MCHP_GPIO_CTRL_PWR_MASK0 0x03
+#define MCHP_GPIO_CTRL_PWR_MASK (0x03 << 2)
+#define MCHP_GPIO_CTRL_PWR_VTR 0
+#define MCHP_GPIO_CTRL_PWR_OFF (0x02 << 2)
+#define MCHP_GPIO_INTDET_MASK 0xF0
+#define MCHP_GPIO_INTDET_LVL_LO 0x00
+#define MCHP_GPIO_INTDET_LVL_HI 0x10
+#define MCHP_GPIO_INTDET_DISABLED 0x40
+#define MCHP_GPIO_INTDET_EDGE_RIS 0xD0
+#define MCHP_GPIO_INTDET_EDGE_FALL 0xE0
+#define MCHP_GPIO_INTDET_EDGE_BOTH 0xF0
+#define MCHP_GPIO_INTDET_EDGE_EN BIT(7)
+#define MCHP_GPIO_PUSH_PULL 0u
+#define MCHP_GPIO_OPEN_DRAIN BIT(8)
+#define MCHP_GPIO_INPUT 0u
+#define MCHP_GPIO_OUTPUT BIT(9)
+#define MCHP_GPIO_OUTSET_CTRL 0u
+#define MCHP_GPIO_OUTSEL_PAR BIT(10)
+#define MCHP_GPIO_POLARITY_NINV 0u
+#define MCHP_GPIO_POLARITY_INV BIT(11)
+#define MCHP_GPIO_CTRL_ALT_FUNC_BITPOS 12
+#define MCHP_GPIO_CTRL_ALT_FUNC_MASK0 0x0F
+#define MCHP_GPIO_CTRL_ALT_FUNC_MASK (0x0F << 12)
+#define MCHP_GPIO_CTRL_FUNC_GPIO (0 << 12)
+#define MCHP_GPIO_CTRL_FUNC_1 (1 << 12)
+#define MCHP_GPIO_CTRL_FUNC_2 (2 << 12)
+#define MCHP_GPIO_CTRL_FUNC_3 (3 << 12)
+#define MCHP_GPIO_CTRL_OUT_LVL BIT(16)
+/* MEC170x reserved read-only 0 bit. Value set to 0 */
+#define MCHP_GPIO_CTRL_DIS_INPUT_BITPOS 15
+#define MCHP_GPIO_CTRL_DIS_INPUT_BIT 0
+
+/*
+ * GPIO Parallel Input and Output registers.
+ * gpio_bank in [0, 5]
+ */
+#define MCHP_GPIO_PARIN(bank) REG32(MCHP_GPIO_BASE + 0x0300 + ((bank) << 2))
+#define MCHP_GPIO_PAROUT(bank) REG32(MCHP_GPIO_BASE + 0x0380 + ((bank) << 2))
+
+/* Basic timers */
+#define MCHP_TMR_SPACING 0x20
+#define MCHP_TMR16_INSTANCES 4
+#define MCHP_TMR32_INSTANCES 2
+#define MCHP_TMR16_MAX (MCHP_TMR16_INSTANCES)
+#define MCHP_TMR32_MAX (MCHP_TMR32_INSTANCES)
+#define MCHP_TMR16_BASE(n) (MCHP_TMR16_0_BASE + (n)*MCHP_TMR_SPACING)
+#define MCHP_TMR32_BASE(n) (MCHP_TMR32_0_BASE + (n)*MCHP_TMR_SPACING)
+#define MCHP_TMR16_GIRQ 23
+#define MCHP_TMR16_GIRQ_BIT(n) BIT(0 + (n))
+#define MCHP_TMR32_GIRQ 23
+#define MCHP_TMR32_GIRQ_BIT(n) BIT(4 + (n))
+
+/* 16-bit Counter/timer */
+#define MCHP_CNT16_SPACING 0x20
+#define MCHP_CNT16_INSTANCES 4
+#define MCHP_CNT16_BASE(n) (MCHP_CNT16_0_BASE + (n)*MCHP_CNT16_SPACING)
+#define MCHP_CNT16_GIRQ 23
+#define MCHP_CNT16_GIRQ_BIT(x) BIT(6 + (x))
+
+/* RTimer */
+#define MCHP_RTMR_GIRQ 21
+#define MCHP_RTMR_GIRQ_BIT(x) MCHP_INT21_RTMR
+
+/* VBAT */
+#define MCHP_VBAT_STS REG32(MCHP_VBAT_BASE + 0x0)
+#define MCHP_VBAT_CE REG32(MCHP_VBAT_BASE + 0x8)
+#define MCHP_VBAT_SHDN_DIS REG32(MCHP_VBAT_BASE + 0xC)
+#define MCHP_VBAT_MONOTONIC_CTR_LO REG32(MCHP_VBAT_BASE + 0x20)
+#define MCHP_VBAT_MONOTONIC_CTR_HI REG32(MCHP_VBAT_BASE + 0x24)
+/* read 32-bit word at 32-bit offset x where 0 <= x <= 32 */
+#define MCHP_VBAT_RAM_SIZE 128
+#define MCHP_VBAT_RAM(wnum) REG32(MCHP_VBAT_RAM_BASE + ((wnum)*4))
+#define MCHP_VBAT_RAM8(bnum) REG8(MCHP_VBAT_RAM_BASE + (bnum))
+#define MCHP_VBAT_VWIRE_BACKUP 30
+/*
+ * Miscellaneous firmware control fields
+ * scratch pad index cannot be more than 32 as
+ * MEC152x has 64 bytes = 16 words of scratch RAM
+ */
+#define MCHP_IMAGETYPE_IDX 31
+
+/* Bit definition for MCHP_VBAT_STS */
+#define MCHP_VBAT_STS_SOFTRESET BIT(2)
+#define MCHP_VBAT_STS_RESETI BIT(4)
+#define MCHP_VBAT_STS_WDT BIT(5)
+#define MCHP_VBAT_STS_SYSRESETREQ BIT(6)
+#define MCHP_VBAT_STS_VBAT_RST BIT(7)
+#define MCHP_VBAT_STS_ANY_RST 0xF4u
+
+/* Bit definitions for MCHP_VBAT_CE */
+#define MCHP_VBAT_CE_XOSEL_BITPOS 3
+#define MCHP_VBAT_CE_XOSEL_MASK BIT(3)
+#define MCHP_VBAT_CE_XOSEL_PAR 0
+#define MCHP_VBAT_CE_XOSEL_SE BIT(3)
+
+#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_BITPOS 2
+#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_MASK BIT(2)
+#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_INT 0
+#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_CRYSTAL BIT(2)
+
+#define MCHP_VBAT_CE_32K_DOMAIN_SRC_BITPOS 1
+#define MCHP_VBAT_CE_32K_DOMAIN_SRC_MASK BIT(1)
+#define MCHP_VBAT_CE_32K_DOMAIN_ALWAYS_ON 0
+#define MCHP_VBAT_CE_32K_DOMAIN_32KHZ_IN_PIN BIT(1)
+
+/* Blinking-Breathing LED 0 <= n <= 2 */
+#define MCHP_BBLEB_INSTANCES 4
+#define MCHP_BBLED_BASE(n) (MCHP_BBLED_0_BASE + (((n)&0x03) * 256))
+
+/* EMI */
+#define MCHP_EMI_INSTANCES 3
+#define MCHP_EMI_SPACING 0x400
+#define MCHP_EMI_ECREG_OFS 0x100
+/* base of EMI registers only accessible by EC */
+#define MCHP_EMI_BASE(n) \
+	(MCHP_EMI_0_BASE + MCHP_EMI_ECREG_OFS + ((n)*MCHP_EMI_SPACING))
+/* base of EMI registers accessible by EC and Host */
+#define MCHP_EMI_RT_BASE(n) (MCHP_EMI_0_BASE + ((n)*MCHP_EMI_SPACING))
+#define MCHP_EMI_GIRQ 15
+#define MCHP_EMI_GIRQ_BIT(n) BIT(2 + (n))
+
+/* Mailbox */
+#define MCHP_MBX_ECREGS_OFS 0x100
+#define MCHP_MBX_RT_BASE MCHP_MBOX_BASE
+#define MCHP_MBX_BASE (MCHP_MBOX_BASE + MCHP_MBX_ECREGS_OFS)
+#define MCHP_MBX_GIRQ 15
+#define MCHP_MBX_GIRQ_BIT BIT(20)
+
+/* Port 80 Capture */
+#define MCHP_P80_SPACING 0x400
+#define MCHP_P80_BASE(n) (MCHP_P80CAP0_BASE + ((n) * (MCHP_P80_SPACING)))
+#define MCHP_P80_HOST_DATA(n) REG8(MCHP_P80_BASE(n))
+/* Data capture with time stamp register */
+#define MCHP_P80_CAP(n) REG32(MCHP_P80_BASE(n) + 0x100)
+#define MCHP_P80_CFG(n) REG8(MCHP_P80_BASE(n) + 0x104)
+#define MCHP_P80_STS(n) REG8(MCHP_P80_BASE(n) + 0x108)
+#define MCHP_P80_CNT(n) REG32(MCHP_P80_BASE(n) + 0x10c)
+#define MCHP_P80_CNT_GET(n) (REG32(MCHP_P80_BASE(n) + 0x10c) >> 8)
+#define MCHP_P80_CNT_SET(n, c) (REG32(MCHP_P80_BASE(n) + 0x10c) = ((c) << 8))
+#define MCHP_P80_ACTIVATE(n) REG8(MCHP_P80_BASE(n) + 0x330)
+#define MCHP_P80_GIRQ 15
+#define MCHP_P80_GIRQ_BIT(n) BIT(22 + (n))
+/*
+ * Port 80 Data register bits
+ * bits[7:0] = data captured on Host write
+ * bits[31:8] = optional time stamp
+ */
+#define MCHP_P80_CAP_DATA_MASK 0xFFul
+#define MCHP_P80_CAP_TS_BITPOS 8
+#define MCHP_P80_CAP_TS_MASK0 0xfffffful
+#define MCHP_P80_CAP_TS_MASK \
+	((MCHP_P80_CAP_TS_MASK0) << (MCHP_P80_CAP_TS_BITPOS))
+
+/* Port 80 Configuration register bits */
+#define MCHP_P80_FLUSH_FIFO_WO BIT(1)
+#define MCHP_P80_RESET_TIMESTAMP_WO BIT(2)
+#define MCHP_P80_TIMEBASE_BITPOS 3
+#define MCHP_P80_TIMEBASE_MASK0 0x03
+#define MCHP_P80_TIMEBASE_MASK \
+	((MCHP_P80_TIMEBASE_MASK0) << (MCHP_P80_TIMEBASE_BITPOS))
+#define MCHP_P80_TIMEBASE_750KHZ (0x03 << (MCHP_P80_TIMEBASE_BITPOS))
+#define MCHP_P80_TIMEBASE_1500KHZ (0x02 << (MCHP_P80_TIMEBASE_BITPOS))
+#define MCHP_P80_TIMEBASE_3MHZ (0x01 << (MCHP_P80_TIMEBASE_BITPOS))
+#define MCHP_P80_TIMEBASE_6MHZ (0x00 << (MCHP_P80_TIMEBASE_BITPOS))
+#define MCHP_P80_TIMER_ENABLE BIT(5)
+#define MCHP_P80_FIFO_THRHOLD_MASK (3u << 6)
+#define MCHP_P80_FIFO_THRHOLD_1 0u
+#define MCHP_P80_FIFO_THRHOLD_4 (1u << 6)
+#define MCHP_P80_FIFO_THRHOLD_8 (2u << 6)
+#define MCHP_P80_FIFO_THRHOLD_14 (3u << 6)
+#define MCHP_P80_FIFO_LEN 16
+/* Port 80 Status register bits, read-only */
+#define MCHP_P80_STS_NOT_EMPTY BIT(0)
+#define MCHP_P80_STS_OVERRUN BIT(1)
+/* Port 80 Count register bits */
+#define MCHP_P80_CNT_BITPOS 8
+#define MCHP_P80_CNT_MASK0 0xfffffful
+#define MCHP_P80_CNT_MASK ((MCHP_P80_CNT_MASK0) << (MCHP_P80_CNT_BITPOS))
+
+/* PWM SZ 144 pin package has 9 PWM's */
+#define MCHP_PWM_INSTANCES 9
+#define MCHP_PWM_ID_MAX (MCHP_PWM_INSTANCES)
+#define MCHP_PWM_SPACING 16
+#define MCHP_PWM_BASE(x) (MCHP_PWM_0_BASE + ((x)*MCHP_PWM_SPACING))
+
+/* TACH */
+#define MCHP_TACH_INSTANCES 3
+#define MCHP_TACH_SPACING 16
+#define MCHP_TACH_BASE(x) (MCHP_TACH_0_BASE + ((x)*MCHP_TACH_SPACING))
+#define MCHP_TACH_GIRQ 17
+#define MCHP_TACH_GIRQ_BIT(x) BIT(1 + (x))
+
+/* FAN */
+#define MCHP_FAN_INSTANCES 2
+#define MCHP_FAN_SPACING 0x80U
+#define MCHP_FAN_BASE(x) (MCHP_RPM2PWM0_BASE + ((x)*MCHP_FAN_SPACING))
+#define MCHP_FAN_SETTING(x) REG16(MCHP_FAN_BASE(x) + 0x0)
+#define MCHP_FAN_CFG1(x) REG8(MCHP_FAN_BASE(x) + 0x2)
+#define MCHP_FAN_CFG2(x) REG8(MCHP_FAN_BASE(x) + 0x3)
+#define MCHP_FAN_PWM_DIVIDE(x) REG8(MCHP_FAN_BASE(x) + 0x4)
+#define MCHP_FAN_GAIN(x) REG8(MCHP_FAN_BASE(x) + 0x5)
+#define MCHP_FAN_SPIN_UP(x) REG8(MCHP_FAN_BASE(x) + 0x6)
+#define MCHP_FAN_STEP(x) REG8(MCHP_FAN_BASE(x) + 0x7)
+#define MCHP_FAN_MIN_DRV(x) REG8(MCHP_FAN_BASE(x) + 0x8)
+#define MCHP_FAN_VALID_CNT(x) REG8(MCHP_FAN_BASE(x) + 0x9)
+#define MCHP_FAN_DRV_FAIL(x) REG16(MCHP_FAN_BASE(x) + 0xa)
+#define MCHP_FAN_TARGET(x) REG16(MCHP_FAN_BASE(x) + 0xc)
+#define MCHP_FAN_READING(x) REG16(MCHP_FAN_BASE(x) + 0xe)
+#define MCHP_FAN_BASE_FREQ(x) REG8(MCHP_FAN_BASE(x) + 0x10)
+#define MCHP_FAN_STATUS(x) REG8(MCHP_FAN_BASE(x) + 0x11)
+
+/* ACPI EC */
+#define MCHP_ACPI_EC_INSTANCES 5
+#define MCHP_ACPI_EC_MAX (MCHP_ACPI_EC_INSTANCES)
+#define MCHP_ACPI_EC_SPACING 0x400
+#define MCHP_ACPI_EC_BASE(x) (MCHP_ACPI_EC_0_BASE + ((x)*MCHP_ACPI_EC_SPACING))
+#define MCHP_ACPI_EC_GIRQ 15
+#define MCHP_ACPI_EC_IBF_GIRQ_BIT(x) BIT(5 + ((x)*2))
+#define MCHP_ACPI_EC_OBE_GIRQ_BIT(x) BIT(6 + ((x)*2))
+
+/* ACPI PM1 */
+#define MCHP_ACPI_PM1_ECREGS_OFS 0x100
+#define MCHP_ACPI_PM_RT_BASE MCHP_ACPI_PM1_BASE
+#define MCHP_ACPI_PM_EC_BASE (MCHP_ACPI_PM1_BASE + MCHP_ACPI_PM1_ECREGS_OFS)
+#define MCHP_ACPI_PM1_CTL_GIRQ_BIT BIT(15)
+#define MCHP_ACPI_PM1_EN_GIRQ_BIT BIT(16)
+#define MCHP_ACPI_PM1_STS_GIRQ_BIT BIT(17)
+
+/* 8042 */
+#define MCHP_8042_ECREGS_OFS 0x100
+#define MCHP_8042_GIRQ 15
+#define MCHP_8042_OBE_GIRQ_BIT BIT(18)
+#define MCHP_8042_IBF_GIRQ_BIT BIT(19)
+
+/* I2C controllers 0 - 4 include SMBus network layer functionality. */
+#define MCHP_I2C_CTRL0 0
+#define MCHP_I2C_CTRL1 1
+#define MCHP_I2C_CTRL2 2
+#define MCHP_I2C_CTRL3 3
+#define MCHP_I2C_CTRL_MAX 4
+
+#define MCHP_I2C_SEP0 0x400
+
+/*
+ * MEC1701H 144-pin package has four I2C controllers and eleven ports.
+ * Any port can be mapped to any I2C controller.
+ * NOTE: 144-pin package does not implement port 1.
+ *
+ * I2C port values must be zero based consecutive whole numbers due to
+ * port number used as an index for I2C mutex array, etc.
+ *
+ * Refer to chip i2c_port_to_controller function for mapping
+ * of port to controller.
+ *
+ * Locking must occur by-controller (not by-port).
+ */
+#define MCHP_I2C_PORT_MASK 0x07FDul
+enum MCHP_i2c_port {
+	MCHP_I2C_PORT0 = 0,
+	MCHP_I2C_PORT1, /* port 1, do not use. pins not present */
+	MCHP_I2C_PORT2,
+	MCHP_I2C_PORT3,
+	MCHP_I2C_PORT4,
+	MCHP_I2C_PORT5,
+	MCHP_I2C_PORT6,
+	MCHP_I2C_PORT7,
+	MCHP_I2C_PORT8,
+	MCHP_I2C_PORT9,
+	MCHP_I2C_PORT10,
+	MCHP_I2C_PORT_COUNT,
+};
+
+/* All I2C controllers connected to GIRQ13 */
+#define MCHP_I2C_GIRQ 13
+/* I2C[0:7] -> GIRQ13 bits[0:7] */
+#define MCHP_I2C_GIRQ_BIT(n) BIT((n))
+
+/* Keyboard scan matrix */
+#define MCHP_KS_GIRQ 21
+#define MCHP_KS_GIRQ_BIT BIT(25)
+#define MCHP_KS_DIRECT_NVIC 135
+
+/* ADC */
+#define MCHP_ADC_GIRQ 17
+#define MCHP_ADC_GIRQ_SINGLE_BIT BIT(8)
+#define MCHP_ADC_GIRQ_REPEAT_BIT BIT(9)
+#define MCHP_ADC_SINGLE_DIRECT_NVIC 78
+#define MCHP_ADC_REPEAT_DIRECT_NVIC 79
+
+/* Hibernation timer */
+#define MCHP_HTIMER_SPACING 0x20
+#define MCHP_HTIMER_ADDR(n) (MCHP_HTIMER_BASE + ((n)*MCHP_HTIMER_SPACING))
+#define MCHP_HTIMER_GIRQ 21
+/* HTIMER[0:1] -> GIRQ21 bits[1:2] */
+#define MCHP_HTIMER_GIRQ_BIT(n) BIT(1 + (n))
+#define MCHP_HTIMER_DIRECT_NVIC(n) (112 + (n))
+
+/* General Purpose SPI (GP-SPI) */
+#define MCHP_SPI_BASE(port) (MCHP_GPSPI0_BASE + ((port)*0x80))
+#define MCHP_SPI_AR(port) REG8(MCHP_SPI_BASE(port) + 0x00)
+#define MCHP_SPI_CR(port) REG8(MCHP_SPI_BASE(port) + 0x04)
+#define MCHP_SPI_SR(port) REG8(MCHP_SPI_BASE(port) + 0x08)
+#define MCHP_SPI_TD(port) REG8(MCHP_SPI_BASE(port) + 0x0c)
+#define MCHP_SPI_RD(port) REG8(MCHP_SPI_BASE(port) + 0x10)
+#define MCHP_SPI_CC(port) REG8(MCHP_SPI_BASE(port) + 0x14)
+#define MCHP_SPI_CG(port) REG8(MCHP_SPI_BASE(port) + 0x18)
+/* Addresses of TX/RX register used in tables */
+#define MCHP_SPI_TD_ADDR(ctrl) (MCHP_SPI_BASE(ctrl) + 0x0c)
+#define MCHP_SPI_RD_ADDR(ctrl) (MCHP_SPI_BASE(ctrl) + 0x10)
+/* All GP-SPI controllers connected to GIRQ18 */
+#define MCHP_SPI_GIRQ 18
+#define MCHP_SPI_GIRQ_TXBE_BIT(x) BIT(2 + ((x)*2))
+#define MCHP_SPI_GIRQ_RXBF_BIT(x) BIT(3 + ((x)*2))
+#define MCHP_GPSPI0_ID 0
+#define MCHP_GPSPI1_ID 1
+
+/*
+ * Quad Master SPI (QMSPI)
+ * MEC1701 implements 5 descriptors and a single chip select.
+ */
+#define MCHP_QMSPI_MAX_DESCR 5
+#define MCHP_QMSPI_GIRQ 18
+#define MCHP_QMSPI_GIRQ_BIT BIT(1)
+#define MCHP_QMSPI_DIRECT_NVIC 91
+
+/* LPC */
+#define MCHP_LPC_RT_BASE (MCHP_LPC_BASE + 0x100)
+#define MCHP_LPC_CFG_BASE (MCHP_LPC_BASE + 0x300)
+#define MCHP_LPC_ACT REG8(MCHP_LPC_CFG_BASE + 0x30)
+#define MCHP_LPC_SIRQ(x) REG8(MCHP_LPC_CFG_BASE + 0x40 + (x))
+#define MCHP_LPC_CFG_BAR REG32(MCHP_LPC_CFG_BASE + 0x60)
+#define MCHP_LPC_MAILBOX_BAR REG32(MCHP_LPC_CFG_BASE + 0x64)
+#define MCHP_LPC_8042_BAR REG32(MCHP_LPC_CFG_BASE + 0x68)
+#define MCHP_LPC_ACPI_EC0_BAR REG32(MCHP_LPC_CFG_BASE + 0x6C)
+#define MCHP_LPC_ACPI_EC1_BAR REG32(MCHP_LPC_CFG_BASE + 0x70)
+#define MCHP_LPC_ACPI_EC2_BAR REG32(MCHP_LPC_CFG_BASE + 0x74)
+#define MCHP_LPC_ACPI_EC3_BAR REG32(MCHP_LPC_CFG_BASE + 0x78)
+#define MCHP_LPC_ACPI_EC4_BAR REG32(MCHP_LPC_CFG_BASE + 0x7C)
+#define MCHP_LPC_ACPI_PM1_BAR REG32(MCHP_LPC_CFG_BASE + 0x80)
+#define MCHP_LPC_PORT92_BAR REG32(MCHP_LPC_CFG_BASE + 0x84)
+#define MCHP_LPC_UART0_BAR REG32(MCHP_LPC_CFG_BASE + 0x88)
+#define MCHP_LPC_UART1_BAR REG32(MCHP_LPC_CFG_BASE + 0x8C)
+#define MCHP_LPC_EMI0_BAR REG32(MCHP_LPC_CFG_BASE + 0x90)
+#define MCHP_LPC_EMI1_BAR REG32(MCHP_LPC_CFG_BASE + 0x94)
+#define MCHP_LPC_EMI2_BAR REG32(MCHP_LPC_CFG_BASE + 0x98)
+#define MCHP_LPC_P80DBG0_BAR REG32(MCHP_LPC_CFG_BASE + 0x9C)
+#define MCHP_LPC_P80DBG1_BAR REG32(MCHP_LPC_CFG_BASE + 0xA0)
+#define MCHP_LPC_RTC_BAR REG32(MCHP_LPC_CFG_BASE + 0xA4)
+#define MCHP_LPC_ACPI_EC_BAR(x) REG32(MCHP_LPC_CFG_BASE + 0x6C + ((x) << 2))
+/* LPC BAR bits */
+#define MCHP_LPC_IO_BAR_ADDR_BITPOS (16)
+#define MCHP_LPC_IO_BAR_EN (1ul << 15)
+/* LPC Generic Memory BAR's, 64-bit registers */
+#define MCHP_LPC_SRAM0_BAR_LO REG32(MCHP_LPC_CFG_BASE + 0xB0)
+#define MCHP_LPC_SRAM0_BAR_HI REG32(MCHP_LPC_CFG_BASE + 0xB4)
+#define MCHP_LPC_SRAM1_BAR_LO REG32(MCHP_LPC_CFG_BASE + 0xB8)
+#define MCHP_LPC_SRAM1_BAR_HI REG32(MCHP_LPC_CFG_BASE + 0xBC)
+/*
+ * LPC Logical Device Memory BAR's, 48-bit registers
+ * Use 16-bit aligned access
+ */
+#define MCHP_LPC_MAILBOX_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xC0)
+#define MCHP_LPC_MAILBOX_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xC2)
+#define MCHP_LPC_MAILBOX_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xC4)
+#define MCHP_LPC_ACPI_EC0_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xC6)
+#define MCHP_LPC_ACPI_EC0_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xC8)
+#define MCHP_LPC_ACPI_EC0_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xCA)
+#define MCHP_LPC_ACPI_EC1_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xCC)
+#define MCHP_LPC_ACPI_EC1_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xCE)
+#define MCHP_LPC_ACPI_EC1_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xD0)
+#define MCHP_LPC_ACPI_EC2_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xD2)
+#define MCHP_LPC_ACPI_EC2_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xD4)
+#define MCHP_LPC_ACPI_EC2_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xD6)
+#define MCHP_LPC_ACPI_EC3_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xD8)
+#define MCHP_LPC_ACPI_EC3_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xDA)
+#define MCHP_LPC_ACPI_EC3_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xDC)
+#define MCHP_LPC_ACPI_EC4_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xDE)
+#define MCHP_LPC_ACPI_EC4_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xE0)
+#define MCHP_LPC_ACPI_EC4_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xE2)
+#define MCHP_LPC_ACPI_EMI0_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xE4)
+#define MCHP_LPC_ACPI_EMI0_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xE6)
+#define MCHP_LPC_ACPI_EMI0_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xE8)
+#define MCHP_LPC_ACPI_EMI1_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xEA)
+#define MCHP_LPC_ACPI_EMI1_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xEC)
+#define MCHP_LPC_ACPI_EMI1_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xEE)
+#define MCHP_LPC_ACPI_EMI2_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xF0)
+#define MCHP_LPC_ACPI_EMI2_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xF2)
+#define MCHP_LPC_ACPI_EMI2_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xF4)
+
+#define MCHP_LPC_BUS_MONITOR REG32(MCHP_LPC_RT_BASE + 0x4)
+#define MCHP_LPC_HOST_ERROR REG32(MCHP_LPC_RT_BASE + 0x8)
+#define MCHP_LPC_EC_SERIRQ REG32(MCHP_LPC_RT_BASE + 0xC)
+#define MCHP_LPC_EC_CLK_CTRL REG32(MCHP_LPC_RT_BASE + 0x10)
+#define MCHP_LPC_BAR_INHIBIT REG32(MCHP_LPC_RT_BASE + 0x20)
+#define MCHP_LPC_BAR_INIT REG32(MCHP_LPC_RT_BASE + 0x30)
+#define MCHP_LPC_SRAM0_BAR REG32(MCHP_LPC_RT_BASE + 0xf8)
+#define MCHP_LPC_SRAM1_BAR REG32(MCHP_LPC_RT_BASE + 0xfc)
+
+/* eSPI */
+/* IO BAR defines. Use with MCHP_ESPI_IO_BAR_xxxx macros */
+#define MCHP_ESPI_IO_BAR_ID_CFG_PORT 0
+#define MCHP_ESPI_IO_BAR_ID_MEM_CMPNT 1
+#define MCHP_ESPI_IO_BAR_ID_MAILBOX 2
+#define MCHP_ESPI_IO_BAR_ID_8042 3
+#define MCHP_ESPI_IO_BAR_ID_ACPI_EC0 4
+#define MCHP_ESPI_IO_BAR_ID_ACPI_EC1 5
+#define MCHP_ESPI_IO_BAR_ID_ACPI_EC2 6
+#define MCHP_ESPI_IO_BAR_ID_ACPI_EC3 7
+#define MCHP_ESPI_IO_BAR_ID_ACPI_EC4 8
+#define MCHP_ESPI_IO_BAR_ID_ACPI_PM1 9
+#define MCHP_ESPI_IO_BAR_ID_P92 0xA
+#define MCHP_ESPI_IO_BAR_ID_UART0 0xB
+#define MCHP_ESPI_IO_BAR_ID_UART1 0xC
+#define MCHP_ESPI_IO_BAR_ID_EMI0 0xD
+#define MCHP_ESPI_IO_BAR_ID_EMI1 0xE
+#define MCHP_ESPI_IO_BAR_ID_EMI2 0xF
+#define MCHP_ESPI_IO_BAR_P80_0 0x10
+#define MCHP_ESPI_IO_BAR_P80_1 0x11
+#define MCHP_ESPI_IO_BAR_RTC 0x12
+
+/* Use with MCHP_ESPI_MBAR_EC_xxxx(x) macros */
+#define MCHP_ESPI_MBAR_ID_MBOX 0
+#define MCHP_ESPI_MBAR_ID_ACPI_EC_0 1
+#define MCHP_ESPI_MBAR_ID_ACPI_EC_1 2
+#define MCHP_ESPI_MBAR_ID_ACPI_EC_2 3
+#define MCHP_ESPI_MBAR_ID_ACPI_EC_3 4
+#define MCHP_ESPI_MBAR_ID_ACPI_EC_4 5
+#define MCHP_ESPI_MBAR_ID_EMI_0 6
+#define MCHP_ESPI_MBAR_ID_EMI_1 7
+#define MCHP_ESPI_MBAR_ID_EMI_2 8
+
+/* Use with MCHP_ESPI_IO_SERIRQ_REG(x) */
+#define MCHP_ESPI_SIRQ_MBOX 0 /* Host SIRQ */
+#define MCHP_ESPI_SIRQ_MBOX_SMI 1 /* Host SMI */
+#define MCHP_ESPI_SIRQ_8042_KB 2 /* KIRQ */
+#define MCHP_ESPI_SIRQ_8042_MS 3 /* MIRQ */
+#define MCHP_ESPI_SIRQ_ACPI_EC0_OBF 4
+#define MCHP_ESPI_SIRQ_ACPI_EC1_OBF 5
+#define MCHP_ESPI_SIRQ_ACPI_EC2_OBF 6
+#define MCHP_ESPI_SIRQ_ACPI_EC3_OBF 7
+#define MCHP_ESPI_SIRQ_ACPI_EC4_OBF 8
+#define MCHP_ESPI_SIRQ_UART0 9
+#define MCHP_ESPI_SIRQ_UART1 10
+#define MCHP_ESPI_SIRQ_EMI0_HEV 11 /* Host Event */
+#define MCHP_ESPI_SIRQ_EMI0_EC2H 12 /* EC to Host */
+#define MCHP_ESPI_SIRQ_EMI1_HEV 13
+#define MCHP_ESPI_SIRQ_EMI1_EC2H 14
+#define MCHP_ESPI_SIRQ_EMI2_HEV 15
+#define MCHP_ESPI_SIRQ_EMI2_EC2H 16
+#define MCHP_ESPI_SIRQ_RTC 17
+#define MCHP_ESPI_SIRQ_EC 18
+
+#define MCHP_ESPI_MSVW_BASE (MCHP_ESPI_VW_BASE)
+#define MCHP_ESPI_SMVW_BASE ((MCHP_ESPI_VW_BASE) + 0x200ul)
+
+/*
+ * eSPI RESET, channel enables and operations except Master-to-Slave
+ * WWires are all on GIRQ19
+ */
+#define MCHP_ESPI_GIRQ 19
+#define MCHP_ESPI_PC_GIRQ_BIT BIT(0)
+#define MCHP_ESPI_BM1_GIRQ_BIT BIT(1)
+#define MCHP_ESPI_BM2_GIRQ_BIT BIT(2)
+#define MCHP_ESPI_LTR_GIRQ_BIT BIT(3)
+#define MCHP_ESPI_OOB_TX_GIRQ_BIT BIT(4)
+#define MCHP_ESPI_OOB_RX_GIRQ_BIT BIT(5)
+#define MCHP_ESPI_FC_GIRQ_BIT BIT(6)
+#define MCHP_ESPI_RESET_GIRQ_BIT BIT(7)
+#define MCHP_ESPI_VW_EN_GIRQ_BIT BIT(8)
+
+/*
+ * eSPI Master-to-Slave WWire interrupts are on GIRQ24 and GIRQ25
+ */
+#define MCHP_ESPI_MSVW_0_6_GIRQ 24
+#define MCHP_ESPI_MSVW_7_10_GIRQ 25
+/*
+ * Four source bits, SRC[0:3] per Master-to-Slave register
+ * v = MSVW [0:10]
+ * n = VWire SRC bit = [0:3]
+ */
+#define MCHP_ESPI_MSVW_GIRQ(v) (24 + ((v) > 6 ? 1 : 0))
+
+#define MCHP_ESPI_MSVW_SRC_GIRQ_BIT(v, n) \
+	(((v) > 6) ? (1ul << (((v)-7) + (n))) : (1ul << ((v) + (n))))
+
+/* DMA */
+#define MCHP_DMA_MAX_CHAN 14
+#define MCHP_DMA_CH_OFS 0x40
+#define MCHP_DMA_CH_OFS_BITPOS 6
+#define MCHP_DMA_CH_BASE (MCHP_DMA_BASE + MCHP_DMA_CH_OFS)
+
+/*
+ * Available DMA channels.
+ *
+ * On MCHP, any DMA channel may serve any device. Since we have
+ * 14 channels and 14 device request signals, we make each channel
+ * dedicated to the device of the same number.
+ */
+enum dma_channel {
+	/* Channel numbers */
+	MCHP_DMAC_I2C0_SLAVE = 0,
+	MCHP_DMAC_I2C0_MASTER,
+	MCHP_DMAC_I2C1_SLAVE,
+	MCHP_DMAC_I2C1_MASTER,
+	MCHP_DMAC_I2C2_SLAVE,
+	MCHP_DMAC_I2C2_MASTER,
+	MCHP_DMAC_I2C3_SLAVE,
+	MCHP_DMAC_I2C3_MASTER,
+	MCHP_DMAC_SPI0_TX,
+	MCHP_DMAC_SPI0_RX,
+	MCHP_DMAC_SPI1_TX,
+	MCHP_DMAC_SPI1_RX,
+	MCHP_DMAC_QMSPI0_TX,
+	MCHP_DMAC_QMSPI0_RX,
+	/* Channel count */
+	MCHP_DMAC_COUNT,
+};
+
+/*
+ * Peripheral device DMA Device ID's for bits [15:9]
+ * in DMA channel control register.
+ */
+#define MCHP_DMA_I2C0_SLV_REQ_ID 0
+#define MCHP_DMA_I2C0_MTR_REQ_ID 1
+#define MCHP_DMA_I2C1_SLV_REQ_ID 2
+#define MCHP_DMA_I2C1_MTR_REQ_ID 3
+#define MCHP_DMA_I2C2_SLV_REQ_ID 4
+#define MCHP_DMA_I2C2_MTR_REQ_ID 5
+#define MCHP_DMA_I2C3_SLV_REQ_ID 6
+#define MCHP_DMA_I2C3_MTR_REQ_ID 7
+#define MCHP_DMA_SPI0_TX_REQ_ID 8
+#define MCHP_DMA_SPI0_RX_REQ_ID 9
+#define MCHP_DMA_SPI1_TX_REQ_ID 10
+#define MCHP_DMA_SPI1_RX_REQ_ID 11
+#define MCHP_DMA_QMSPI0_TX_REQ_ID 12
+#define MCHP_DMA_QMSPI0_RX_REQ_ID 13
+
+/*
+ * Hardware delay register.
+ * Write of 0 <= n <= 31 will stall the Cortex-M4
+ * for n+1 microseconds. Interrupts will not be
+ * serviced during the delay period. Reads have
+ * no effect.
+ */
+#define MCHP_USEC_DELAY_REG_ADDR 0x10000000
+#define MCHP_USEC_DELAY(x) (REG8(MCHP_USEC_DELAY_REG_ADDR) = (x))
+
+#endif /* #ifndef __ASSEMBLER__ */
diff --git a/chip/mchp/registers-mec172x.h b/chip/mchp/registers-mec172x.h
new file mode 100644
index 0000000000..0bd010ac05
--- /dev/null
+++ b/chip/mchp/registers-mec172x.h
@@ -0,0 +1,1495 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Register map for Microchip MEC172x family controllers
+ */
+
+#ifndef __CROS_EC_REGISTERS_H
+#error "This header file should not be included directly."
+#endif
+
+/*
+ * IRQ Numbers
+ * NOTE: GIRQ22 aggregated output and its sources are not connected to
+ * the NVIC.
+ */
+#define MCHP_IRQ_GIRQ8 0
+#define MCHP_IRQ_GIRQ9 1
+#define MCHP_IRQ_GIRQ10 2
+#define MCHP_IRQ_GIRQ11 3
+#define MCHP_IRQ_GIRQ12 4
+#define MCHP_IRQ_GIRQ13 5
+#define MCHP_IRQ_GIRQ14 6
+#define MCHP_IRQ_GIRQ15 7
+#define MCHP_IRQ_GIRQ16 8
+#define MCHP_IRQ_GIRQ17 9
+#define MCHP_IRQ_GIRQ18 10
+#define MCHP_IRQ_GIRQ19 11
+#define MCHP_IRQ_GIRQ20 12
+#define MCHP_IRQ_GIRQ21 13
+#define MCHP_IRQ_GIRQ23 14
+#define MCHP_IRQ_GIRQ24 15
+#define MCHP_IRQ_GIRQ25 16
+#define MCHP_IRQ_GIRQ26 17
+/* GIRQ13 direct sources */
+#define MCHP_IRQ_I2C_0 20
+#define MCHP_IRQ_I2C_1 21
+#define MCHP_IRQ_I2C_2 22
+#define MCHP_IRQ_I2C_3 23
+#define MCHP_IRQ_I2C_4 158
+/* GIRQ14 direct sources */
+#define MCHP_IRQ_DMA_0 24
+#define MCHP_IRQ_DMA_1 25
+#define MCHP_IRQ_DMA_2 26
+#define MCHP_IRQ_DMA_3 27
+#define MCHP_IRQ_DMA_4 28
+#define MCHP_IRQ_DMA_5 29
+#define MCHP_IRQ_DMA_6 30
+#define MCHP_IRQ_DMA_7 31
+#define MCHP_IRQ_DMA_8 32
+#define MCHP_IRQ_DMA_9 33
+#define MCHP_IRQ_DMA_10 34
+#define MCHP_IRQ_DMA_11 35
+#define MCHP_IRQ_DMA_12 36
+#define MCHP_IRQ_DMA_13 37
+#define MCHP_IRQ_DMA_14 38
+#define MCHP_IRQ_DMA_15 39
+/* GIRQ15 direct sources */
+#define MCHP_IRQ_UART0 40
+#define MCHP_IRQ_UART1 41
+#define MCHP_IRQ_EMI0 42
+#define MCHP_IRQ_EMI1 43
+#define MCHP_IRQ_EMI2 44
+#define MCHP_IRQ_ACPIEC0_IBF 45
+#define MCHP_IRQ_ACPIEC0_OBE 46
+#define MCHP_IRQ_ACPIEC1_IBF 47
+#define MCHP_IRQ_ACPIEC1_OBE 48
+#define MCHP_IRQ_ACPIEC2_IBF 49
+#define MCHP_IRQ_ACPIEC2_OBE 50
+#define MCHP_IRQ_ACPIEC3_IBF 51
+#define MCHP_IRQ_ACPIEC3_OBE 52
+#define MCHP_IRQ_ACPIEC4_IBF 53
+#define MCHP_IRQ_ACPIEC4_OBE 54
+#define MCHP_IRQ_ACPIPM1_CTL 55
+#define MCHP_IRQ_ACPIPM1_EN 56
+#define MCHP_IRQ_ACPIPM1_STS 57
+#define MCHP_IRQ_8042EM_OBE 58
+#define MCHP_IRQ_8042EM_IBF 59
+#define MCHP_IRQ_MAILBOX_DATA 60
+#define MCHP_IRQ_BDP0 62
+/* GIRQ16 direct sources */
+#define MCHP_IRQ_PKE 65
+#define MCHP_IRQ_NDRNG 67
+#define MCHP_IRQ_AESH 68
+/* GIRQ17 direct sources */
+#define MCHP_IRQ_PECI_HOST 70
+#define MCHP_IRQ_TACH_0 71
+#define MCHP_IRQ_TACH_1 72
+#define MCHP_IRQ_TACH_2 73
+#define MCHP_IRQ_TACH_3 159
+#define MCHP_IRQ_FAN0_FAIL 74
+#define MCHP_IRQ_FAN0_STALL 75
+#define MCHP_IRQ_FAN1_FAIL 76
+#define MCHP_IRQ_FAN1_STALL 77
+#define MCHP_IRQ_ADC_SNGL 78
+#define MCHP_IRQ_ADC_RPT 79
+#define MCHP_IRQ_RCID0 80
+#define MCHP_IRQ_RCID1 81
+#define MCHP_IRQ_RCID2 82
+#define MCHP_IRQ_LED0_WDT 83
+#define MCHP_IRQ_LED1_WDT 84
+#define MCHP_IRQ_LED2_WDT 85
+#define MCHP_IRQ_LED3_WDT 86
+#define MCHP_IRQ_PHOT 87
+/* GIRQ18 direct sources */
+#define MCHP_IRQ_SLAVE_SPI 90
+#define MCHP_IRQ_QMSPI0 91
+#define MCHP_IRQ_SPI0_TX 92
+#define MCHP_IRQ_SPI0_RX 93
+#define MCHP_IRQ_SPI1_TX 94
+#define MCHP_IRQ_SPI1_RX 95
+#define MCHP_IRQ_BCM0_ERR 96
+#define MCHP_IRQ_BCM0_BUSY 97
+#define MCHP_IRQ_PS2_0 100
+#define MCHP_IRQ_EEPROM 155
+#define MCHP_IRQ_CCT_TMR 146
+#define MCHP_IRQ_CCT_CAP0 147
+#define MCHP_IRQ_CCT_CAP1 148
+#define MCHP_IRQ_CCT_CAP2 149
+#define MCHP_IRQ_CCT_CAP3 150
+#define MCHP_IRQ_CCT_CAP4 151
+#define MCHP_IRQ_CCT_CAP5 152
+#define MCHP_IRQ_CCT_CMP0 153
+#define MCHP_IRQ_CCT_CMP1 154
+/* GIRQ19 direct sources */
+#define MCHP_IRQ_ESPI_PC 103
+#define MCHP_IRQ_ESPI_BM1 104
+#define MCHP_IRQ_ESPI_BM2 105
+#define MCHP_IRQ_ESPI_LTR 106
+#define MCHP_IRQ_ESPI_OOB_UP 107
+#define MCHP_IRQ_ESPI_OOB_DN 108
+#define MCHP_IRQ_ESPI_FC 109
+#define MCHP_IRQ_ESPI_RESET 110
+#define MCHP_IRQ_ESPI_VW_EN 156
+#define MCHP_IRQ_ESPI_SAF_DONE 166
+#define MCHP_IRQ_ESPI_SAF_ERR 166
+#define MCHP_IRQ_ESPI_SAF_CACHE 169
+/* GIRQ20 direct sources */
+#define MCHP_IRQ_OTP 173
+#define MCHP_IRQ_CLK32K_MON 174
+/* GIRQ21 direct sources */
+#define MCHP_IRQ_WDG 171
+#define MCHP_IRQ_WEEK_ALARM 114
+#define MCHP_IRQ_SUBWEEK 115
+#define MCHP_IRQ_WEEK_SEC 116
+#define MCHP_IRQ_WEEK_SUBSEC 117
+#define MCHP_IRQ_WEEK_SYSPWR 118
+#define MCHP_IRQ_RTC 119
+#define MCHP_IRQ_RTC_ALARM 120
+#define MCHP_IRQ_VCI_OVRD_IN 121
+#define MCHP_IRQ_VCI_IN0 122
+#define MCHP_IRQ_VCI_IN1 123
+#define MCHP_IRQ_VCI_IN2 124
+#define MCHP_IRQ_VCI_IN3 125
+#define MCHP_IRQ_VCI_IN4 126
+#define MCHP_IRQ_PS20A_WAKE 129
+#define MCHP_IRQ_PS20B_WAKE 130
+#define MCHP_IRQ_KSC_INT 135
+#define MCHP_IRQ_GLUE 172
+/* GIRQ23 direct sources */
+#define MCHP_IRQ_TIMER16_0 136
+#define MCHP_IRQ_TIMER16_1 137
+#define MCHP_IRQ_TIMER16_2 138
+#define MCHP_IRQ_TIMER16_3 139
+#define MCHP_IRQ_TIMER32_0 140
+#define MCHP_IRQ_TIMER32_1 141
+#define MCHP_IRQ_CNTR_TM0 142
+#define MCHP_IRQ_CNTR_TM1 143
+#define MCHP_IRQ_CNTR_TM2 144
+#define MCHP_IRQ_CNTR_TM3 145
+#define MCHP_IRQ_RTOS_TIMER 111
+#define MCHP_IRQ_HTIMER0 112
+#define MCHP_IRQ_HTIMER1 113
+/* Must match CONFIG_IRQ_COUNT in config_chip.h */
+#define MCHP_IRQ_MAX 180
+
+/* Block base addresses */
+#define MCHP_WDG_BASE 0x40000400
+#define MCHP_TMR16_0_BASE 0x40000c00
+#define MCHP_TMR32_0_BASE 0x40000c80
+#define MCHP_CNT16_0_BASE 0x40000d00
+#define MCHP_DMA_BASE 0x40002400
+#define MCHP_PROCHOT_BASE 0x40003400
+#define MCHP_I2C0_BASE 0x40004000
+#define MCHP_I2C1_BASE 0x40004400
+#define MCHP_I2C2_BASE 0x40004800
+#define MCHP_I2C3_BASE 0x40004C00
+#define MCHP_I2C4_BASE 0x40005000
+#define MCHP_CACHE_CTRL_BASE 0x40005400
+#define MCHP_PWM_0_BASE 0x40005800
+#define MCHP_TACH_0_BASE 0x40006000
+#define MCHP_PECI_BASE 0x40006400
+#define MCHP_SPIEP_BASE 0x40007000
+#define MCHP_RTMR_BASE 0x40007400
+#define MCHP_ADC_BASE 0x40007c00
+#define MCHP_ESPI_SAF_BASE 0x40008000
+#define MCHP_TFDP_BASE 0x40008c00
+#define MCHP_GPSPI0_BASE 0x40009400
+#define MCHP_GPSPI1_BASE 0x40009480
+#define MCHP_HTIMER_BASE 0x40009800
+#define MCHP_KEYSCAN_BASE 0x40009c00
+#define MCHP_RPM2PWM0_BASE 0x4000a000
+#define MCHP_RPM2PWM1_BASE 0x4000a080
+#define MCHP_VBAT_BASE 0x4000a400
+#define MCHP_VBAT_RAM_BASE 0x4000a800
+#define MCHP_WKTIMER_BASE 0x4000ac80
+#define MCHP_VCI_BASE 0x4000ae00
+#define MCHP_BBLED_0_BASE 0x4000B800
+#define MCHP_BCL_0_BASE 0x4000cd00
+#define MCHP_INT_BASE 0x4000e000
+#define MCHP_EC_BASE 0x4000fc00
+
+#define MCHP_QMSPI0_BASE 0x40070000
+#define MCHP_ESPI_SAF_COMM_BASE 0x40071000
+
+#define MCHP_PCR_BASE 0x40080100
+#define MCHP_GPIO_BASE 0x40081000
+#define MCHP_OTP_BASE 0x40082000
+
+#define MCHP_MBOX_BASE 0x400f0000
+#define MCHP_8042_BASE 0x400f0400
+#define MCHP_ACPI_EC_0_BASE 0x400f0800
+#define MCHP_ACPI_PM1_BASE 0x400f1c00
+#define MCHP_PORT92_BASE 0x400f2000
+#define MCHP_UART0_BASE 0x400f2400
+#define MCHP_UART1_BASE 0x400f2800
+#define MCHP_LPC_BASE 0x400f3000
+#define MCHP_ESPI_IO_BASE 0x400f3400
+#define MCHP_ESPI_MEM_BASE 0x400f3800
+#define MCHP_GLUE_BASE 0x400f3c00
+#define MCHP_EMI_0_BASE 0x400f4000
+#define MCHP_EMI_1_BASE 0x400f4400
+#define MCHP_EMI_2_BASE 0x400f4800
+#define MCHP_RTC_BASE 0x400f5000
+#define MCHP_BDP0_BASE 0x400f8000
+#define MCHP_ESPI_VW_BASE 0x400f9c00
+#define MCHP_CHIP_BASE 0x400fff00
+
+#ifndef __ASSEMBLER__
+
+/*
+ * Helper function for RAM address aliasing
+ * NOTE: MEC17xx and MEC15xx AHB controllers do NOT require aliasing.
+ * Cortex-M4 bit-banding does require aliasing of the
+ * DATA SRAM region.
+ */
+#define MCHP_RAM_ALIAS(x) ((x) >= 0x118000 ? (x)-0x118000 + 0x20000000 : (x))
+
+/* EC Chip Configuration */
+/* 16-bit Device ID */
+#define MCHP_CHIP_DEV_ID REG16(MCHP_CHIP_BASE + 0x1E)
+/* 8-bit Device Sub ID */
+#define MCHP_CHIP_DEV_SUB_ID REG8(MCHP_CHIP_BASE + 0x1D)
+/* 8-bit Device Revision */
+#define MCHP_CHIP_DEV_REV REG8(MCHP_CHIP_BASE + 0x1C)
+/* All in one */
+#define MCHP_CHIP_DEVRID32 REG32(MCHP_CHIP_BASE + 0x1C)
+#define MCHP_CHIP_DEVID_POS 16
+#define MCHP_CHIP_DEVID_MASK (0xfffful << MCHP_CHIP_DEVID_POS)
+#define MCHP_CHIP_SUBID_POS 8
+#define MCHP_CHIP_SUBID_MASK (0xfful << MCHP_CHIP_SUBID_POS)
+#define MCHP_CHIP_REV_POS 0
+#define MCHP_CHIP_REV_MASK (0xfful << MCHP_CHIP_REV_POS)
+#define MCHP_CHIP_EXTRACT_DEVID(d) \
+	(((uint32_t)(d)&MCHP_CHIP_DEVID_MASK) >> MCHP_CHIP_DEVID_POS)
+#define MCHP_CHIP_EXTRACT_SUBID(d) \
+	(((uint32_t)(d)&MCHP_CHIP_SUBID_MASK) >> MCHP_CHIP_SUBID_POS)
+#define MCHP_CHIP_EXTRACT_REV(d) \
+	(((uint32_t)(d)&MCHP_CHIP_REV_MASK) >> MCHP_CHIP_REV_POS)
+
+/* PCR clock control dividers */
+#define MCHP_PCR_CLK_CTL_FASTEST 1U
+#define MCHP_PCR_CLK_CTL_96MHZ 1U
+#define MCHP_PCR_CLK_CTL_48MHZ 2U
+#define MCHP_PCR_CLK_CTL_24MHZ 4U
+#define MCHP_PCR_CLK_CTL_12MHZ 8U
+
+/* Number of PCR Sleep Enable, Clock Required, and Reset registers */
+#define MCHP_PCR_SLP_RST_REG_MAX 5
+
+/* Sleep 0: Sleep Enable, Clock Required, and Reset bits */
+#define MCHP_PCR_JTAG BIT(0) /* CLKREQ only */
+#define MCHP_PCR_OTP BIT(1)
+#define MCHP_PCR_ISPI BIT(2)
+
+/* Command all blocks to sleep */
+#define MCHP_PCR_SLP_EN0_JTAG BIT(0)
+#define MCHP_PCR_SLP_EN0_OTP BIT(1)
+#define MCHP_PCR_SLP_EN0_ISPI BIT(2)
+#define MCHP_PCR_SLP_EN0_SLEEP 0xffffffff
+
+/*
+ * Encode register number and bit position
+ * b[4:0] = bit number
+ * b[10:8] = zero based register number
+ */
+#define MCHP_PCR_ERB(rnum, bnum) ((((rnum)&0x0f) << 8) | ((bnum)&0x1f))
+
+/* PCR Sleep 1: Sleep Enable, Clock Required, and Reset bits */
+#define MCHP_PCR_BTMR16_1 MCHP_PCR_ERB(1, 31)
+#define MCHP_PCR_BTMR16_0 MCHP_PCR_ERB(1, 30)
+#define MCHP_PCR_ECS MCHP_PCR_ERB(1, 29)
+#define MCHP_PCR_PWM8 MCHP_PCR_ERB(1, 27)
+#define MCHP_PCR_PWM7 MCHP_PCR_ERB(1, 26)
+#define MCHP_PCR_PWM6 MCHP_PCR_ERB(1, 25)
+#define MCHP_PCR_PWM5 MCHP_PCR_ERB(1, 24)
+#define MCHP_PCR_PWM4 MCHP_PCR_ERB(1, 23)
+#define MCHP_PCR_PWM3 MCHP_PCR_ERB(1, 22)
+#define MCHP_PCR_PWM2 MCHP_PCR_ERB(1, 21)
+#define MCHP_PCR_PWM1 MCHP_PCR_ERB(1, 20)
+#define MCHP_PCR_TACH3 MCHP_PCR_ERB(1, 13)
+#define MCHP_PCR_TACH2 MCHP_PCR_ERB(1, 12)
+#define MCHP_PCR_TACH1 MCHP_PCR_ERB(1, 11)
+#define MCHP_PCR_I2C0 MCHP_PCR_ERB(1, 10)
+#define MCHP_PCR_WDT MCHP_PCR_ERB(1, 9)
+#define MCHP_PCR_CPU MCHP_PCR_ERB(1, 8)
+#define MCHP_PCR_TFDP MCHP_PCR_ERB(1, 7)
+#define MCHP_PCR_DMA MCHP_PCR_ERB(1, 6)
+#define MCHP_PCR_PMC MCHP_PCR_ERB(1, 5)
+#define MCHP_PCR_PWM0 MCHP_PCR_ERB(1, 4)
+#define MCHP_PCR_TACH0 MCHP_PCR_ERB(1, 2)
+#define MCHP_PCR_PECI MCHP_PCR_ERB(1, 1)
+#define MCHP_PCR_ECIA MCHP_PCR_ERB(1, 0)
+
+/* Command all blocks to sleep */
+#define MCHP_PCR_SLP_EN1_BTMR16_1 BIT(31)
+#define MCHP_PCR_SLP_EN1_BTMR16_0 BIT(30)
+#define MCHP_PCR_SLP_EN1_ECS BIT(29)
+#define MCHP_PCR_SLP_EN1_PWM_ALL                                              \
+	(BIT(4) | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) | BIT(25) | \
+	 BIT(26) | BIT(27))
+#define MCHP_PCR_SLP_EN1_PWM8 BIT(27)
+#define MCHP_PCR_SLP_EN1_PWM7 BIT(26)
+#define MCHP_PCR_SLP_EN1_PWM6 BIT(25)
+#define MCHP_PCR_SLP_EN1_PWM5 BIT(24)
+#define MCHP_PCR_SLP_EN1_PWM4 BIT(23)
+#define MCHP_PCR_SLP_EN1_PWM3 BIT(22)
+#define MCHP_PCR_SLP_EN1_PWM2 BIT(21)
+#define MCHP_PCR_SLP_EN1_PWM1 BIT(20)
+#define MCHP_PCR_SLP_EN1_TACH3 BIT(13)
+#define MCHP_PCR_SLP_EN1_TACH2 BIT(12)
+#define MCHP_PCR_SLP_EN1_TACH1 BIT(11)
+#define MCHP_PCR_SLP_EN1_I2C0 BIT(10)
+#define MCHP_PCR_SLP_EN1_WDT BIT(9)
+#define MCHP_PCR_SLP_EN1_CPU BIT(8)
+#define MCHP_PCR_SLP_EN1_TFDP BIT(7)
+#define MCHP_PCR_SLP_EN1_DMA BIT(6)
+#define MCHP_PCR_SLP_EN1_PMC BIT(5)
+#define MCHP_PCR_SLP_EN1_PWM0 BIT(4)
+#define MCHP_PCR_SLP_EN1_TACH0 BIT(2)
+#define MCHP_PCR_SLP_EN1_PECI BIT(1)
+#define MCHP_PCR_SLP_EN1_ECIA BIT(0)
+/* all sleep enable 1 bits */
+#define MCHP_PCR_SLP_EN1_SLEEP 0xffffffff
+/*
+ * block not used by default
+ * Do not sleep ECIA, PMC, CPU and ECS
+ */
+#define MCHP_PCR_SLP_EN1_UNUSED_BLOCKS 0xdffffede
+
+/* PCR Sleep 2: Sleep Enable, Clock Required 2, Reset bits */
+#define MCHP_PCR_GLUE MCHP_PCR_ERB(2, 29)
+#define MCHP_PCR_SAF MCHP_PCR_ERB(2, 27)
+#define MCHP_PCR_BDP0 MCHP_PCR_ERB(2, 25)
+#define MCHP_PCR_ACPI_EC4 MCHP_PCR_ERB(2, 23)
+#define MCHP_PCR_ACPI_EC3 MCHP_PCR_ERB(2, 22)
+#define MCHP_PCR_ACPI_EC2 MCHP_PCR_ERB(2, 21)
+#define MCHP_PCR_ESPI_SCR MCHP_PCR_ERB(2, 20)
+#define MCHP_PCR_ESPI MCHP_PCR_ERB(2, 19)
+#define MCHP_PCR_RTC MCHP_PCR_ERB(2, 18)
+#define MCHP_PCR_MBOX MCHP_PCR_ERB(2, 17)
+#define MCHP_PCR_8042 MCHP_PCR_ERB(2, 16)
+#define MCHP_PCR_ACPI_PM1 MCHP_PCR_ERB(2, 15)
+#define MCHP_PCR_ACPI_EC1 MCHP_PCR_ERB(2, 14)
+#define MCHP_PCR_ACPI_EC0 MCHP_PCR_ERB(2, 13)
+#define MCHP_PCR_GCFG MCHP_PCR_ERB(2, 12)
+#define MCHP_PCR_UART1 MCHP_PCR_ERB(2, 2)
+#define MCHP_PCR_UART0 MCHP_PCR_ERB(2, 1)
+#define MCHP_PCR_EMI0 MCHP_PCR_ERB(2, 0)
+
+/* Command all blocks to sleep */
+#define MCHP_PCR_SLP_EN2_GLUE BIT(29)
+#define MCHP_PCR_SLP_EN2_SAF BIT(27)
+#define MCHP_PCR_SLP_EN2_BDP0 BIT(25)
+#define MCHP_PCR_SLP_EN2_ACPI_EC4 BIT(23)
+#define MCHP_PCR_SLP_EN2_ACPI_EC3 BIT(22)
+#define MCHP_PCR_SLP_EN2_ACPI_EC2 BIT(21)
+#define MCHP_PCR_SLP_EN2_ESPI_SCR BIT(20)
+#define MCHP_PCR_SLP_EN2_ESPI BIT(19)
+#define MCHP_PCR_SLP_EN2_RTC BIT(18)
+#define MCHP_PCR_SLP_EN2_MAILBOX BIT(17)
+#define MCHP_PCR_SLP_EN2_MIF8042 BIT(16)
+#define MCHP_PCR_SLP_EN2_ACPI_PM1 BIT(15)
+#define MCHP_PCR_SLP_EN2_ACPI_EC1 BIT(14)
+#define MCHP_PCR_SLP_EN2_ACPI_EC0 BIT(13)
+#define MCHP_PCR_SLP_EN2_GCFG BIT(12)
+#define MCHP_PCR_SLP_EN2_UART1 BIT(2)
+#define MCHP_PCR_SLP_EN2_UART0 BIT(1)
+#define MCHP_PCR_SLP_EN2_EMI0 BIT(0)
+/* all sleep enable 2 bits */
+#define MCHP_PCR_SLP_EN2_SLEEP 0xffffffff
+
+/* PCR Sleep 3: Sleep Enable, Clock Required, and Reset */
+#define MCHP_PCR_PWM9 MCHP_PCR_ERB(3, 31)
+#define MCHP_PCR_CCT0 MCHP_PCR_ERB(3, 30)
+#define MCHP_PCR_HTMR1 MCHP_PCR_ERB(3, 29)
+#define MCHP_PCR_CRYPTO MCHP_PCR_ERB(3, 26)
+#define MCHP_PCR_LED3 MCHP_PCR_ERB(3, 25)
+#define MCHP_PCR_BTMR32_1 MCHP_PCR_ERB(3, 24)
+#define MCHP_PCR_BTMR32_0 MCHP_PCR_ERB(3, 23)
+#define MCHP_PCR_BTMR16_3 MCHP_PCR_ERB(3, 22)
+#define MCHP_PCR_BTMR16_2 MCHP_PCR_ERB(3, 21)
+#define MCHP_PCR_I2C4 MCHP_PCR_ERB(3, 20)
+#define MCHP_PCR_BCM0 MCHP_PCR_ERB(3, 19)
+#define MCHP_PCR_LED2 MCHP_PCR_ERB(3, 18)
+#define MCHP_PCR_LED1 MCHP_PCR_ERB(3, 17)
+#define MCHP_PCR_LED0 MCHP_PCR_ERB(3, 16)
+#define MCHP_PCR_I2C3 MCHP_PCR_ERB(3, 15)
+#define MCHP_PCR_I2C2 MCHP_PCR_ERB(3, 14)
+#define MCHP_PCR_I2C1 MCHP_PCR_ERB(3, 13)
+#define MCHP_PCR_RPMPWM0 MCHP_PCR_ERB(3, 12)
+#define MCHP_PCR_KEYSCAN MCHP_PCR_ERB(3, 11)
+#define MCHP_PCR_HTMR0 MCHP_PCR_ERB(3, 10)
+#define MCHP_PCR_GPSPI0 MCHP_PCR_ERB(3, 9)
+#define MCHP_PCR_PS2_0 MCHP_PCR_ERB(3, 5)
+#define MCHP_PCR_ADC MCHP_PCR_ERB(3, 3)
+
+/* Command blocks to sleep */
+#define MCHP_PCR_SLP_EN3_PWM9 BIT(31)
+#define MCHP_PCR_SLP_EN3_CCT0 BIT(30)
+#define MCHP_PCR_SLP_EN3_HTMR1 BIT(29)
+#define MCHP_PCR_SLP_EN3_CRYPTO BIT(26)
+#define MCHP_PCR_SLP_EN3_LED3 BIT(25)
+#define MCHP_PCR_SLP_EN3_BTMR32_1 BIT(24)
+#define MCHP_PCR_SLP_EN3_BTMR32_0 BIT(23)
+#define MCHP_PCR_SLP_EN3_BTMR16_3 BIT(22)
+#define MCHP_PCR_SLP_EN3_BTMR16_2 BIT(21)
+#define MCHP_PCR_SLP_EN3_I2C4 BIT(20)
+#define MCHP_PCR_SLP_EN3_BCM0 BIT(19)
+#define MCHP_PCR_SLP_EN3_LED2 BIT(18)
+#define MCHP_PCR_SLP_EN3_LED1 BIT(17)
+#define MCHP_PCR_SLP_EN3_LED0 BIT(16)
+#define MCHP_PCR_SLP_EN3_I2C3 BIT(15)
+#define MCHP_PCR_SLP_EN3_I2C2 BIT(14)
+#define MCHP_PCR_SLP_EN3_I2C1 BIT(13)
+#define MCHP_PCR_SLP_EN3_RPM2PWM0 BIT(12)
+#define MCHP_PCR_SLP_EN3_KEYSCAN BIT(11)
+#define MCHP_PCR_SLP_EN3_HTMR0 BIT(10)
+#define MCHP_PCR_SLP_EN3_GPSPI0 BIT(9)
+#define MCHP_PCR_SLP_EN3_PS2_0 BIT(5)
+#define MCHP_PCR_SLP_EN3_ADC BIT(3)
+#define MCHP_PCR_SLP_EN3_ALL_CRYPTO BIT(26)
+/* all sleep enable 3 bits */
+#define MCHP_PCR_SLP_EN3_SLEEP 0xffffffff
+#define MCHP_PCR_SLP_EN3_PWM_ALL (MCHP_PCR_SLP_EN3_PWM9)
+
+/* PCR Sleep 4: Sleep Enable, Clock Required, Reset */
+#define MCHP_PCR_GPSPI1 MCHP_PCR_ERB(4, 22)
+#define MCHP_PCR_PSPI MCHP_PCR_ERB(4, 14)
+#define MCHP_PCR_PROCHOT MCHP_PCR_ERB(4, 13)
+#define MCHP_PCR_RCID2 MCHP_PCR_ERB(4, 12)
+#define MCHP_PCR_RCID1 MCHP_PCR_ERB(4, 11)
+#define MCHP_PCR_RCID0 MCHP_PCR_ERB(4, 10)
+#define MCHP_PCR_QMSPI MCHP_PCR_ERB(4, 8)
+#define MCHP_PCR_RPMPWM1 MCHP_PCR_ERB(4, 7)
+#define MCHP_PCR_RTMR MCHP_PCR_ERB(4, 6)
+#define MCHP_PCR_CNT16_3 MCHP_PCR_ERB(4, 5)
+#define MCHP_PCR_CNT16_2 MCHP_PCR_ERB(4, 4)
+#define MCHP_PCR_CNT16_1 MCHP_PCR_ERB(4, 3)
+#define MCHP_PCR_CNT16_0 MCHP_PCR_ERB(4, 2)
+#define MCHP_PCR_PWM11 MCHP_PCR_ERB(4, 1)
+#define MCHP_PCR_PWM10 MCHP_PCR_ERB(4, 0)
+
+/* Command blocks to sleep */
+#define MCHP_PCR_SLP_EN4_GPSPI1 BIT(22)
+#define MCHP_PCR_SLP_EN4_PSPI BIT(14)
+#define MCHP_PCR_SLP_EN4_PROCHOT BIT(13)
+#define MCHP_PCR_SLP_EN4_RCID2 BIT(12)
+#define MCHP_PCR_SLP_EN4_RCID1 BIT(11)
+#define MCHP_PCR_SLP_EN4_RCID0 BIT(10)
+#define MCHP_PCR_SLP_EN4_QMSPI BIT(8)
+#define MCHP_PCR_SLP_EN4_RPMPWM1 BIT(7)
+#define MCHP_PCR_SLP_EN4_RTMR BIT(6)
+#define MCHP_PCR_SLP_EN4_CNT16_3 BIT(5)
+#define MCHP_PCR_SLP_EN4_CNT16_2 BIT(4)
+#define MCHP_PCR_SLP_EN4_CNT16_1 BIT(3)
+#define MCHP_PCR_SLP_EN4_CNT16_0 BIT(2)
+#define MCHP_PCR_SLP_EN4_PWM11 BIT(1)
+#define MCHP_PCR_SLP_EN4_PWM10 BIT(0)
+
+/* all sleep enable 4 bits */
+#define MCHP_PCR_SLP_EN4_SLEEP 0xffffffff
+#define MCHP_PCR_SLP_EN4_PWM_ALL \
+	(MCHP_PCR_SLP_EN4_PWM10 | MCHP_PCR_SLP_EN4_PWM11)
+
+/* Allow all blocks to request clocks */
+#define MCHP_PCR_SLP_EN0_WAKE (~(MCHP_PCR_SLP_EN0_SLEEP))
+#define MCHP_PCR_SLP_EN1_WAKE (~(MCHP_PCR_SLP_EN1_SLEEP))
+#define MCHP_PCR_SLP_EN2_WAKE (~(MCHP_PCR_SLP_EN2_SLEEP))
+#define MCHP_PCR_SLP_EN3_WAKE (~(MCHP_PCR_SLP_EN3_SLEEP))
+#define MCHP_PCR_SLP_EN4_WAKE (~(MCHP_PCR_SLP_EN4_SLEEP))
+
+/* Bit defines for MCHP_PCR_PWR_RST_STS */
+#define MCHP_PWR_RST_STS_MASK_RO 0xc8c
+#define MCHP_PWR_RST_STS_MASK_RWC 0x170
+#define MCHP_PWR_RST_STS_MASK \
+	((MCHP_PWR_RST_STS_MASK_RO) | (MCHP_PWR_RST_STS_MASK_RWC))
+
+#define MCHP_PWR_RST_STS_ESPI_CLK_ACT BIT(11) /* RO */
+#define MCHP_PWR_RST_STS_32K_ACT BIT(10) /* RO */
+#define MCHP_PWR_RST_STS_WDT BIT(8) /* R/WC */
+#define MCHP_PWR_RST_STS_JTAG_RSTN BIT(7) /* RO */
+#define MCHP_PWR_RST_STS_SYS BIT(6) /* R/WC */
+#define MCHP_PWR_RST_STS_VBAT BIT(5) /* R/WC */
+#define MCHP_PWR_RST_STS_VTR BIT(4) /* R/WC */
+#define MCHP_PWR_RST_STS_HOST BIT(3) /* RO */
+#define MCHP_PWR_RST_STS_VCC_PWRGD BIT(2) /* RO */
+
+/* Bit defines for MCHP_PCR_PWR_RST_CTL */
+#define MCHP_PCR_PWR_HOST_RST_SEL_BITPOS 8
+#define MCHP_PCR_PWR_HOST_RST_PCI_RESET BIT(8)
+#define MCHP_PCR_PWR_HOST_RST_ESPI_PLTRST 0
+#define MCHP_PCR_PWR_OK_INV_BITPOS 0
+
+/* Bit defines for MCHP_PCR_SYS_RST */
+#define MCHP_PCR_SYS_SOFT_RESET BIT(8)
+
+/*
+ * PCR Peripheral Reset Lock register
+ * MEC152x PCR Peripheral reset registers do not reset on
+ * peripheral sleep. The peripheral is reset immediately.
+ * Firmware must write an unlock value to this new lock
+ * register, write to PCR reset enable register(s), and
+ * write a lock value.
+ */
+#define MCHP_PCR_RST_LOCK REG32(MCHP_PCR_BASE + 0x84)
+#define MCHP_PCR_RST_LOCK_VAL 0xa6382d4d
+#define MCHP_PCR_RST_UNLOCK_VAL 0xa6382d4c
+
+/* PCR VBAT soft reset. Trigger a VBAT reset */
+#define MCHP_PCR_VBAT_SRST REG32(MCHP_PCR_BASE + 0x88)
+#define MCHP_PCR_VBAT_SRST_EN BIT(0)
+
+/* PCR 32KHz clock source select */
+#define MCHP_PCR_CK32_SS REG32(MCHP_PCR_BASE + 0x8c)
+#define MCHP_PCR_CK32_SEL_MASK GENMASK(1, 0)
+#define MCHP_PCR_CK32_SEL_SIL 0
+#define MCHP_PCR_CK32_SEL_XTAL 1
+#define MCHP_PCR_CK32_SEL_PIN 2
+#define MCHP_PCR_CK32_SEL_OFF 3
+
+/* PCR 32KHz period count (RO) */
+#define MCHP_PCR_CK32_PER_CNT REG32(MCHP_PCR_BASE + 0xc0)
+#define MCHP_PCR_CD32_PER_CNT_MSK GENMASK(15, 0)
+
+/* PCR 32KHz high pulse count (RO) */
+#define MCHP_PCR_CK32_HP_CNT REG32(MCHP_PCR_BASE + 0xc4)
+#define MCHP_PCR_CK32_HP_CNT_MSK GENMASK(15, 0)
+
+/* PCR 32KHz minimum acceptable period count */
+#define MCHP_PCR_CK32_MIN_PER_CNT REG32(MCHP_PCR_BASE + 0xc8)
+#define MCHP_PCR_CK32_MIN_PER_CNT_MSK GENMASK(15, 0)
+
+/* PCR 32KHz maximum acceptable period count */
+#define MCHP_PCR_CK32_MAX_PER_CNT REG32(MCHP_PCR_BASE + 0xcc)
+#define MCHP_PCR_CK32_MAX_PER_CNT_MSK GENMASK(15, 0)
+
+/* PCR 32KHz duty cycle variation count (RO) */
+#define MCHP_PCR_CK32_DC_VAR_CNT REG32(MCHP_PCR_BASE + 0xd0)
+#define MCHP_PCR_CK32_DC_VAR_CNT_MSK GENMASK(15, 0)
+
+/* PCR 32KHz duty cycle variation acceptable maximum */
+#define MCHP_PCR_CK32_DC_VAR_MAX REG32(MCHP_PCR_BASE + 0xd4)
+#define MCHP_PCR_CK32_DC_VAR_MAX_MSK GENMASK(15, 0)
+
+/* PCR 32KHz valid count */
+#define MCHP_PCR_CK32_VAL_CNT REG32(MCHP_PCR_BASE + 0xd8)
+#define MCHP_PCR_CK32_VAL_CNT_MSK GENMASK(7, 0)
+
+/* PCR 32KHz valid count minimum */
+#define MCHP_PCR_CK32_MIN_VAL_CNT REG32(MCHP_PCR_BASE + 0xdc)
+#define MCHP_PCR_CK32_MIN_VAL_CNT_MSK GENMASK(7, 0)
+
+/* PCR 32KHz control */
+#define MCHP_PCR_CK32_CTRL REG32(MCHP_PCR_BASE + 0xe0)
+#define MCHP_PCR_CK32_CTRL_MSK (GENMASK(2, 0) | BIT(4) | BIT(24))
+#define MCHP_PCR_CK32_CTRL_PER_EN BIT(0)
+#define MCHP_PCR_CK32_CTRL_DC_EN BIT(1)
+#define MCHP_PCR_CK32_CTRL_VAL_EN BIT(2)
+#define MCHP_PCR_CK32_CTRL_SRC_SIL BIT(3)
+#define MCHP_PCR_CK32_CTRL_CLR_CNT BIT(24)
+
+/* PCR 32KHz interrupt status */
+#define MCHP_PCR_CK32_INTR_STS REG8(MCHP_PCR_BASE + 0xe4)
+/* PCR 32KHz interrupt enable */
+#define MCHP_PCR_CK32_INTR_EN REG8(MCHP_PCR_BASE + 0xe8)
+#define MCHP_PCR_CK32_INTR_PULSE_RDY BIT(0)
+#define MCHP_PCR_CK32_INTR_PASS_PER BIT(1)
+#define MCHP_PCR_CK32_INTR_PASS_DUTY BIT(2)
+#define MCHP_PCR_CK32_INTR_FAIL BIT(3)
+#define MCHP_PCR_CK32_INTR_STALL BIT(4)
+#define MCHP_PCR_CK32_INTR_VALID BIT(5)
+#define MCHP_PCR_CK32_INTR_UNWELL BIT(6)
+
+/* EC Subsystem */
+#define MCHP_EC_AHB_ERR REG32(MCHP_EC_BASE + 0x04)
+#define MCHP_EC_ID_RO REG32(MCHP_EC_BASE + 0x10)
+#define MCHP_EC_AHB_ERR_EN REG32(MCHP_EC_BASE + 0x14)
+#define MCHP_EC_INT_CTRL REG32(MCHP_EC_BASE + 0x18)
+#define MCHP_EC_TRACE_EN REG32(MCHP_EC_BASE + 0x1c)
+#define MCHP_EC_JTAG_EN REG32(MCHP_EC_BASE + 0x20)
+#define MCHP_EC_WDT_CNT REG32(MCHP_EC_BASE + 0x28)
+#define MCHP_EC_PECI_DISABLE REG8(MCHP_EC_BASE + 0x40)
+#define MCHP_EC_VCI_FW_OVRD REG32(MCHP_EC_BASE + 0x50)
+#define MCHP_EC_BROM_STS REG32(MCHP_EC_BASE + 0x54)
+#define MCHP_EC_VW_SRC_CFG REG32(MCHP_EC_BASE + 0x90)
+#define MCHP_EC_CMP_CTRL REG32(MCHP_EC_BASE + 0x94)
+#define MCHP_EC_CMP_SLP_CTRL REG32(MCHP_EC_BASE + 0x98)
+
+/* AHB ERR Disable bit[0]=0(enable), 1(disable) */
+#define MCHP_EC_AHB_ERROR_ENABLE 0
+#define MCHP_EC_AHB_ERROR_DISABLE 1
+
+/* MCHP_EC_JTAG_EN bit definitions */
+#define MCHP_JTAG_ENABLE 0x01
+/* bits [2:1] */
+#define MCHP_JTAG_MODE_4PIN 0x00
+/* ARM 2-pin SWD plus 1-pin Serial Wire Viewer (ITM) */
+#define MCHP_JTAG_MODE_SWD_SWV 0x02
+/* ARM 2-pin SWD with no SWV */
+#define MCHP_JTAG_MODE_SWD 0x04
+
+/* EC Interrupt aggregator (ECIA) */
+#define MCHP_INT_GIRQ_LEN 20 /* 5 32-bit registers */
+#define MCHP_INT_GIRQ_FIRST 8
+#define MCHP_INT_GIRQ_LAST 26
+#define MCHP_INT_GIRQ_NUM (26 - 8 + 1)
+/* MCHP_INT_GIRQ_FIRST <= x <= MCHP_INT_GIRQ_LAST */
+#define MCHP_INTx_BASE(x) (MCHP_INT_BASE + (((x)-8) * MCHP_INT_GIRQ_LEN))
+
+/*
+ * GPIO GIRQ's are not direct capable
+ * GIRQ08 GPIO 0140 - 0176
+ * GIRQ09 GPIO 0100 - 0136
+ * GIRQ10 GPIO 040 - 076
+ * GIRQ11 GPIO 000 - 036
+ * GIRQ12 GPIO 0200 - 0236
+ * GIRQ26 GPIO 0240 - 0276
+ * Other GIRQ's not direct capable:
+ * GIRQ22 wake peripheral clock only
+ * GIRQ24, GIRQ25 eSPI host to endpoint virtual wires
+ */
+#define MCHP_INT_AGGR_ONLY_BITMAP                                            \
+	(BIT(8) | BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(22) | BIT(24) | \
+	 BIT(25) | BIT(26))
+
+#define MCHP_INT_DIRECT_CAPABLE_BITMAP                                         \
+	(BIT(13) | BIT(14) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) | \
+	 BIT(20) | BIT(21) | BIT(23))
+
+/* GIRQ13 I2C controllers 0 - 4. Direct capable */
+#define MCHP_INT13_I2C(x) BIT(x)
+
+/* GIRQ14 DMA channels 0 - 15. Direct capable */
+#define MCHP_INT14_DMA(x) BIT(x)
+
+/* GIQ15 interrupt sources. Direct capable */
+#define MCHP_INT15_UART_0 BIT(0)
+#define MCHP_INT15_UART_1 BIT(1)
+#define MCHP_INT15_EMI_0 BIT(2)
+#define MCHP_INT15_EMI_1 BIT(3)
+#define MCHP_INT15_EMI_2 BIT(4)
+#define MCHP_INT15_ACPI_EC0_IBF BIT(5)
+#define MCHP_INT15_ACPI_EC0_OBE BIT(6)
+#define MCHP_INT15_ACPI_EC1_IBF BIT(7)
+#define MCHP_INT15_ACPI_EC1_OBE BIT(8)
+#define MCHP_INT15_ACPI_EC2_IBF BIT(9)
+#define MCHP_INT15_ACPI_EC2_OBE BIT(10)
+#define MCHP_INT15_ACPI_EC3_IBF BIT(11)
+#define MCHP_INT15_ACPI_EC3_OBE BIT(12)
+#define MCHP_INT15_ACPI_EC4_IBF BIT(13)
+#define MCHP_INT15_ACPI_EC4_OBE BIT(14)
+#define MCHP_INT15_ACPI_PM1_CTL BIT(15)
+#define MCHP_INT15_ACPI_PM1_EN BIT(16)
+#define MCHP_INT15_ACPI_PM1_STS BIT(17)
+#define MCHP_INT15_8042_OBE BIT(18)
+#define MCHP_INT15_8042_IBF BIT(19)
+#define MCHP_INT15_MAILBOX BIT(20)
+#define MCHP_INT15_BDP0 BIT(22)
+
+/* GIRQ16 interrupt sources. Direct capable */
+#define MCHP_INT16_PKE_DONE BIT(0)
+#define MCHP_INT16_RNG_DONE BIT(2)
+#define MCHP_INT16_AESH_DONE BIT(3)
+
+/* GIR17 interrupt sources. Direct capable */
+#define MCHP_INT17_PECI BIT(0)
+#define MCHP_INT17_TACH_0 BIT(1)
+#define MCHP_INT17_TACH_1 BIT(2)
+#define MCHP_INT17_TACH_2 BIT(3)
+#define MCHP_INT17_TACH_3 BIT(4)
+#define MCHP_INT17_ADC_SINGLE BIT(8)
+#define MCHP_INT17_ADC_REPEAT BIT(9)
+#define MCHP_INT17_RCID_0 BIT(10)
+#define MCHP_INT17_RCID_1 BIT(11)
+#define MCHP_INT17_RCID_2 BIT(12)
+#define MCHP_INT17_LED_WDT_0 BIT(13)
+#define MCHP_INT17_LED_WDT_1 BIT(14)
+#define MCHP_INT17_LED_WDT_2 BIT(15)
+#define MCHP_INT17_LED_WDT_3 BIT(16)
+#define MCHP_INT17_PROCHOT BIT(17)
+#define MCHP_INT17_RPM2PWM0_FAIL BIT(20)
+#define MCHP_INT17_RPM2PWM0_STALL BIT(21)
+#define MCHP_INT17_RPM2PWM1_FAIL BIT(22)
+#define MCHP_INT17_RPM2PWM1_STALL BIT(23)
+
+/* GIRQ18 interrupt sources. Direct capable */
+#define MCHP_INT18_SPIEP BIT(0)
+#define MCHP_INT18_QMSPI BIT(1)
+#define MCHP_INT18_GPSPI0_TXBE BIT(2)
+#define MCHP_INT18_GPSPI0_RXBF BIT(3)
+#define MCHP_INT18_GPSPI1_TXBE BIT(4)
+#define MCHP_INT18_GPSPI1_RXBF BIT(5)
+#define MCHP_INT18_BCM0_BUSY BIT(6)
+#define MCHP_INT18_BCM0_ERR BIT(7)
+#define MCHP_INT18_PS2_0 BIT(10)
+#define MCHP_INT18_PSPI BIT(13)
+#define MCHP_INT18_CCT BIT(20)
+#define MCHP_INT18_CCT_CAP0 BIT(21)
+#define MCHP_INT18_CCT_CAP1 BIT(22)
+#define MCHP_INT18_CCT_CAP2 BIT(23)
+#define MCHP_INT18_CCT_CAP3 BIT(24)
+#define MCHP_INT18_CCT_CAP4 BIT(25)
+#define MCHP_INT18_CCT_CAP6 BIT(26)
+#define MCHP_INT18_CCT_CMP0 BIT(27)
+#define MCHP_INT18_CCT_CMP1 BIT(28)
+
+/* GIRQ19 interrupt sources. Direct capable */
+#define MCHP_INT19_ESPI_PC BIT(0)
+#define MCHP_INT19_ESPI_BM1 BIT(1)
+#define MCHP_INT19_ESPI_BM2 BIT(2)
+#define MCHP_INT19_ESPI_LTR BIT(3)
+#define MCHP_INT19_ESPI_OOB_TX BIT(4)
+#define MCHP_INT19_ESPI_OOB_RX BIT(5)
+#define MCHP_INT19_ESPI_FC BIT(6)
+#define MCHP_INT19_ESPI_RESET BIT(7)
+#define MCHP_INT19_ESPI_VW_EN BIT(8)
+#define MCHP_INT19_ESPI_SAF BIT(9)
+#define MCHP_INT19_ESPI_SAF_ERR BIT(10)
+#define MCHP_INT19_ESPI_SAF_CACHE BIT(11)
+
+/* GIRQ20 interrupt sources. Direct capable */
+#define MCHP_INT20_STAP_OBF BIT(0)
+#define MCHP_INT20_STAP_IBF BIT(1)
+#define MCHP_INT20_STAP_WAKE BIT(2)
+#define MCHP_INT20_OTP BIT(3)
+#define MCHP_INT20_ISPI BIT(8)
+#define MCHP_INT20_CLK32K_MON BIT(9)
+
+/* GIRQ21 interrupt sources. Direct capable */
+#define MCHP_INT21_WDG BIT(2)
+#define MCHP_INT21_WEEK_ALARM BIT(3)
+#define MCHP_INT21_WEEK_SUB BIT(4)
+#define MCHP_INT21_WEEK_1SEC BIT(5)
+#define MCHP_INT21_WEEK_1SEC_SUB BIT(6)
+#define MCHP_INT21_WEEK_PWR_PRES BIT(7)
+#define MCHP_INT21_RTC BIT(8)
+#define MCHP_INT21_RTC_ALARM BIT(9)
+#define MCHP_INT21_VCI_OVRD BIT(10)
+#define MCHP_INT21_VCI_IN0 BIT(11)
+#define MCHP_INT21_VCI_IN1 BIT(12)
+#define MCHP_INT21_VCI_IN2 BIT(13)
+#define MCHP_INT21_VCI_IN3 BIT(14)
+#define MCHP_INT21_VCI_IN4 BIT(15)
+#define MCHP_INT21_PS2_0A_WAKE BIT(18)
+#define MCHP_INT21_PS2_0B_WAKE BIT(19)
+#define MCHP_INT21_KEYSCAN BIT(25)
+#define MCHP_INT21_GLUE BIT(26)
+
+/* GIRQ22 peripheral wake only. GIRQ22 not connected to NVIC */
+#define MCHP_INT22_WAKE_ONLY_SPIEP BIT(0)
+#define MCHP_INT22_WAKE_ONLY_I2C0 BIT(1)
+#define MCHP_INT22_WAKE_ONLY_I2C1 BIT(2)
+#define MCHP_INT22_WAKE_ONLY_I2C2 BIT(3)
+#define MCHP_INT22_WAKE_ONLY_I2C3 BIT(4)
+#define MCHP_INT22_WAKE_ONLY_I2C4 BIT(5)
+#define MCHP_INT22_WAKE_ONLY_ESPI BIT(9)
+#define MCHP_INT22_WAKE_ONLY_STAP BIT(15)
+
+/* GIRQ23 sources. Direct capable */
+#define MCHP_INT23_BTMR16_0 BIT(0)
+#define MCHP_INT23_BTMR16_1 BIT(1)
+#define MCHP_INT23_BTMR16_2 BIT(2)
+#define MCHP_INT23_BTMR16_3 BIT(3)
+#define MCHP_INT23_BTMR32_0 BIT(4)
+#define MCHP_INT23_BTMR32_1 BIT(5)
+#define MCHP_INT23_CNT16_0 BIT(6)
+#define MCHP_INT23_CNT16_1 BIT(7)
+#define MCHP_INT23_CNT16_2 BIT(8)
+#define MCHP_INT23_CNT16_3 BIT(9)
+#define MCHP_INT21_RTMR BIT(10)
+#define MCHP_INT21_HTMR_0 BIT(16)
+#define MCHP_INT21_HTMR_1 BIT(17)
+
+/* GIRQ24 sources. Master-to-Slave v=[0:6], Source=[0:3] */
+#define MCHP_INT24_MSVW_SRC(v, s) (1ul << ((4 * (v)) + (s)))
+
+/* GIRQ25 sources Master-to-Slave v=[7:10], Source=[0:3] */
+#define MCHP_INT25_MSVW_SRC(v, s) (1ul << ((4 * ((v)-7)) + (s)))
+
+/* UART Peripheral 0 <= x <= 1 */
+#define MCHP_UART_INSTANCES 2
+#define MCHP_UART_SPACING 0x400
+#define MCHP_UART_CFG_OFS 0x300
+#define MCHP_UART_CONFIG_BASE(x) \
+	(MCHP_UART0_BASE + MCHP_UART_CFG_OFS + ((x)*MCHP_UART_SPACING))
+#define MCHP_UART_RUNTIME_BASE(x) (MCHP_UART0_BASE + ((x)*MCHP_UART_SPACING))
+#define MCHP_UART_GIRQ 15
+#define MCHP_UART0_GIRQ_BIT (MCHP_INT15_UART_0)
+#define MCHP_UART1_GIRQ_BIT (MCHP_INT15_UART_1)
+#define MCHP_UART_GIRQ_BIT(x) BIT(x)
+/* Bit defines for MCHP_UARTx_LSR */
+#define MCHP_LSR_TX_EMPTY BIT(5)
+
+/*
+ * GPIO
+ * MCHP each Port contains 32 GPIO's.
+ * GPIO Control 1 registers are 32-bit registers starting at
+ * MCHP_GPIO_BASE.
+ * index = octal GPIO number from MCHP specification.
+ * port/bank = index >> 5
+ * id = index & 0x1F
+ *
+ * The port/bank, id pair may also be used to access GPIO's via
+ * parallel I/O registers if GPIO control is configured for
+ * parallel I/O.
+ *
+ * From ec/chip/mec1701/config_chip.h
+ * #define GPIO_PIN(index) ((index) >> 5), ((index) & 0x1F)
+ *
+ * GPIO Control 1 Address = 0x40081000 + (((bank << 5) + id) << 2)
+ *
+ * Example: GPIO043, Control 1 register address = 0x4008108c
+ * port/bank = 0x23 >> 5 = 1
+ * id        = 0x23 & 0x1F = 0x03
+ * Control 1 Address = 0x40081000 + ((BIT(5) + 0x03) << 2) = 0x4008108c
+ *
+ * Example: GPIO235, Control 1 register address = 0x40081274
+ * port/bank = 0x9d >> 5   = 4
+ * id        = 0x9d & 0x1f = 0x1d
+ * Control 1 Address = 0x40081000 + (((4 << 5) + 0x1d) << 2) = 0x40081274
+ *
+ */
+#define MCHP_GPIO_CTL(port, id) \
+	REG32(MCHP_GPIO_BASE + (((port << 5) + id) << 2))
+
+/* MCHP implements 6 GPIO ports */
+#define MCHP_GPIO_MAX_PORT 6
+#define UNIMPLEMENTED_GPIO_BANK MCHP_GPIO_MAX_PORT
+/*
+ * In MECxxxx documentation GPIO numbers are octal, each control
+ * register is located on a 32-bit boundary.
+ */
+#define MCHP_GPIO_CTRL(gpio_num) REG32(MCHP_GPIO_BASE + ((gpio_num) << 2))
+
+/*
+ * GPIO control register bit fields
+ */
+#define MCHP_GPIO_CTRL_PUD_BITPOS 0
+#define MCHP_GPIO_CTRL_PUD_MASK0 0x03
+#define MCHP_GPIO_CTRL_PUD_MASK 0x03
+#define MCHP_GPIO_CTRL_PUD_NONE 0x00
+#define MCHP_GPIO_CTRL_PUD_PU 0x01
+#define MCHP_GPIO_CTRL_PUD_PD 0x02
+#define MCHP_GPIO_CTRL_PUD_KEEPER 0x03
+#define MCHP_GPIO_CTRL_PWR_BITPOS 2
+#define MCHP_GPIO_CTRL_PWR_MASK0 0x03
+#define MCHP_GPIO_CTRL_PWR_MASK GENMASK(2, 1)
+#define MCHP_GPIO_CTRL_PWR_VTR 0
+#define MCHP_GPIO_CTRL_PWR_OFF (0x02U << 2)
+#define MCHP_GPIO_INTDET_MASK 0xF0U
+#define MCHP_GPIO_INTDET_LVL_LO 0x00
+#define MCHP_GPIO_INTDET_LVL_HI 0x10U
+#define MCHP_GPIO_INTDET_DISABLED 0x40U
+#define MCHP_GPIO_INTDET_EDGE_RIS 0xD0U
+#define MCHP_GPIO_INTDET_EDGE_FALL 0xE0U
+#define MCHP_GPIO_INTDET_EDGE_BOTH 0xF0U
+#define MCHP_GPIO_INTDET_EDGE_EN BIT(7)
+#define MCHP_GPIO_PUSH_PULL 0U
+#define MCHP_GPIO_OPEN_DRAIN BIT(8)
+#define MCHP_GPIO_INPUT 0U
+#define MCHP_GPIO_OUTPUT BIT(9)
+#define MCHP_GPIO_OUTSET_CTRL 0U
+#define MCHP_GPIO_OUTSEL_PAR BIT(10)
+#define MCHP_GPIO_POLARITY_NINV 0U
+#define MCHP_GPIO_POLARITY_INV BIT(11)
+#define MCHP_GPIO_CTRL_ALT_FUNC_BITPOS 12
+#define MCHP_GPIO_CTRL_ALT_FUNC_MASK0 0x07U
+#define MCHP_GPIO_CTRL_ALT_FUNC_MASK (0x07U << 12)
+#define MCHP_GPIO_CTRL_FUNC_GPIO 0
+#define MCHP_GPIO_CTRL_FUNC_1 (1U << 12)
+#define MCHP_GPIO_CTRL_FUNC_2 (2U << 12)
+#define MCHP_GPIO_CTRL_FUNC_3 (3U << 12)
+#define MCHP_GPIO_CTRL_FUNC_4 (4U << 12)
+#define MCHP_GPIO_CTRL_FUNC_5 (5U << 12)
+#define MCHP_GPIO_CTRL_OUT_LVL BIT(16)
+/* MEC172x implements input pad disable */
+#define MCHP_GPIO_CTRL_DIS_INPUT_BITPOS 15
+#define MCHP_GPIO_CTRL_DIS_INPUT_BIT BIT(15)
+
+/*
+ * GPIO Parallel Input and Output registers.
+ * gpio_bank in [0, 5]
+ */
+#define MCHP_GPIO_PARIN(bank) REG32(MCHP_GPIO_BASE + 0x0300 + ((bank) << 2))
+#define MCHP_GPIO_PAROUT(bank) REG32(MCHP_GPIO_BASE + 0x0380 + ((bank) << 2))
+
+/* Basic timers */
+#define MCHP_TMR_SPACING 0x20
+#define MCHP_TMR16_INSTANCES 4
+#define MCHP_TMR32_INSTANCES 2
+#define MCHP_TMR16_MAX (MCHP_TMR16_INSTANCES)
+#define MCHP_TMR32_MAX (MCHP_TMR32_INSTANCES)
+#define MCHP_TMR16_BASE(n) (MCHP_TMR16_0_BASE + (n)*MCHP_TMR_SPACING)
+#define MCHP_TMR32_BASE(n) (MCHP_TMR32_0_BASE + (n)*MCHP_TMR_SPACING)
+#define MCHP_TMR16_GIRQ 23
+#define MCHP_TMR16_GIRQ_BIT(n) BIT(0 + (n))
+#define MCHP_TMR32_GIRQ 23
+#define MCHP_TMR32_GIRQ_BIT(n) BIT(4 + (n))
+
+/* 16-bit Counter/timer */
+#define MCHP_CNT16_SPACING 0x20
+#define MCHP_CNT16_INSTANCES 4
+#define MCHP_CNT16_BASE(n) (MCHP_CNT16_0_BASE + (n)*MCHP_CNT16_SPACING)
+#define MCHP_CNT16_GIRQ 23
+#define MCHP_CNT16_GIRQ_BIT(x) BIT(6 + (x))
+
+/* RTimer */
+#define MCHP_RTMR_GIRQ 21
+#define MCHP_RTMR_GIRQ_BIT(x) MCHP_INT21_RTMR
+
+/* Watchdog */
+/* MEC152x specific registers */
+#define MCHP_WDG_STATUS REG32(MCHP_WDG_BASE + 0x10)
+#define MCHP_WDG_IEN REG32(MCHP_WDG_BASE + 0x14)
+/* Status */
+#define MCHP_WDG_STS_IRQ BIT(0)
+/* Interrupt enable */
+#define MCHP_WDG_IEN_IRQ_EN BIT(0)
+#define MCHP_WDG_GIRQ 21
+#define MCHP_WDG_GIRQ_BIT BIT(2)
+/* Control register has a bit to enable IRQ generation */
+#define MCHP_WDG_RESET_IRQ_EN BIT(9)
+
+/* VBAT */
+#define MCHP_VBAT_STS REG32(MCHP_VBAT_BASE + 0x0)
+#define MCHP_VBAT_CSS REG32(MCHP_VBAT_BASE + 0x8)
+#define MCHP_VBAT_MONOTONIC_CTR_LO REG32(MCHP_VBAT_BASE + 0x20)
+#define MCHP_VBAT_MONOTONIC_CTR_HI REG32(MCHP_VBAT_BASE + 0x24)
+#define MCHP_VBAT_ROM_FEAT REG32(MCHP_VBAT_BASE + 0x28)
+#define MCHP_VBAT_EMB_DEBOUNCE_EN REG32(MCHP_VBAT_BASE + 0x34)
+/* read 32-bit word at 32-bit offset x where 0 <= x <= 32 */
+#define MCHP_VBAT_RAM_SIZE 128
+#define MCHP_VBAT_RAM(wnum) REG32(MCHP_VBAT_RAM_BASE + ((wnum)*4))
+#define MCHP_VBAT_RAM8(bnum) REG8(MCHP_VBAT_RAM_BASE + (bnum))
+#define MCHP_VBAT_VWIRE_BACKUP 30
+/*
+ * Miscellaneous firmware control fields
+ * scratch pad index cannot be more than 32 as
+ * MEC152x has 64 bytes = 16 words of scratch RAM
+ */
+#define MCHP_IMAGETYPE_IDX 31
+
+/* Bit definition for MCHP_VBAT_STS */
+#define MCHP_VBAT_STS_SOFTRESET BIT(2)
+#define MCHP_VBAT_STS_RESETI BIT(4)
+#define MCHP_VBAT_STS_WDT BIT(5)
+#define MCHP_VBAT_STS_SYSRESETREQ BIT(6)
+#define MCHP_VBAT_STS_VBAT_RST BIT(7)
+#define MCHP_VBAT_STS_ANY_RST 0xF4u
+
+/* Bit definitions for MCHP_VBAT_CSS */
+#define MCHP_VBAT_CSS_SIL32K_EN BIT(0)
+#define MCHP_VBAT_CSS_XTAL_EN BIT(8)
+#define MCHP_VBAT_CSS_XTAL_SINGLE BIT(9)
+#define MCHP_VBAT_CSS_XTAL_HSC_DIS BIT(10)
+#define MCHP_VBAT_CSS_XTAL_CNT_POS 11
+#define MCHP_VBAT_CSS_XTAL_CNT_MASK (0x03U << 11)
+#define MCHP_VBAT_CSS_SRC_POS 16
+#define MCHP_VBAT_CSS_SRC_MASK (0x03U << 16)
+#define MCHP_VBAT_CSS_SRC_SIL_OSC 0
+#define MCHP_VBAT_CSS_SRC_XTAL (1U << 16)
+/* Switch from 32KHZ_IN input to silicon OSC when VTR goes down */
+#define MCHP_VBAT_CSS_SRC_SWPS (2U << 16)
+/* Switch from 32KHZ_IN input to XTAL on VBAT when VTR goes down */
+#define MCHP_VBAT_CSS_SRC_SWPX (3U << 16)
+/* Disable 32Khz silicon oscillator when VBAT goes off */
+#define MCHP_VBAT_CSS_NVB_SUPS BIT(18)
+
+/* Blinking-Breathing LED 0 <= n <= 2 */
+#define MCHP_BBLEB_INSTANCES 4
+#define MCHP_BBLED_BASE(n) (MCHP_BBLED_0_BASE + (((n)&0x03) * 256))
+
+/* EMI */
+#define MCHP_EMI_INSTANCES 3
+#define MCHP_EMI_SPACING 0x400
+#define MCHP_EMI_ECREG_OFS 0x100
+/* base of EMI registers only accessible by EC */
+#define MCHP_EMI_BASE(n) \
+	(MCHP_EMI_0_BASE + MCHP_EMI_ECREG_OFS + ((n)*MCHP_EMI_SPACING))
+/* base of EMI registers accessible by EC and Host */
+#define MCHP_EMI_RT_BASE(n) (MCHP_EMI_0_BASE + ((n)*MCHP_EMI_SPACING))
+#define MCHP_EMI_GIRQ 15
+#define MCHP_EMI_GIRQ_BIT(n) BIT(2 + (n))
+
+/* Mailbox */
+#define MCHP_MBX_ECREGS_OFS 0x100
+#define MCHP_MBX_RT_BASE MCHP_MBOX_BASE
+#define MCHP_MBX_BASE (MCHP_MBOX_BASE + MCHP_MBX_ECREGS_OFS)
+#define MCHP_MBX_GIRQ 15
+#define MCHP_MBX_GIRQ_BIT BIT(20)
+
+/* MEC172x includes one instance of the BIOS Debug Port
+ * capable of capturing Host I/O port 0x80 and 0x90 writes.
+ * EC Data Value register:
+ * bits[7:0] oldest FIFO data from Host
+ * bits[15:16] data attributes/status
+ * Read with 16 or 32 access guarantees attributes/status bits
+ * correspond to data in bits[7:0].
+ */
+#define MCHP_BDP0_HDATA REG32(MCHP_BDP0_BASE)
+#define MCHP_BDP0_DATTR REG16(MCHP_BDP0_BASE + 0x100)
+#define MCHP_BDP0_CONFIG REG32(MCHP_BDP0_BASE + 0x104)
+#define MCHP_BDP0_STATUS REG8(MCHP_BDP0_BASE + 0x108)
+#define MCHP_BDP0_INTR_EN REG8(MCHP_BDP0_BASE + 0x109)
+#define MCHP_BDP0_STS_IEN REG16(MCHP_BDP0_BASE + 0x108)
+#define MCHP_BDP0_SNAPSHOT REG32(MCHP_BDP0_BASE + 0x10C)
+#define MCHP_BDP0_CAPTURE REG32(MCHP_BDP0_BASE + 0x110)
+#define MCHP_BDP0_ACTV REG8(MCHP_BDP0_BASE + 0x330)
+#define MCHP_BDP0_ALIAS_HDATA REG8(MCHP_BDP0_BASE + 0x400)
+#define MCHP_BDP0_ALIAS_ACTV REG8(MCHP_BDP0_BASE + 0x730)
+#define MCHP_BDP0_ALIAS_BLN REG8(MCHP_BDP0_BASE + 0x7F0)
+
+#define MCHP_BDP0_GIRQ 15
+#define MCHP_BDP0_GIRQ_BIT BIT(22)
+
+/* BDP DATATR as 16-bit value bit definitions */
+#define MCHP_BDP_DATTR_POS 0
+#define MCHP_BDP_DATTR_DATA_MASK 0xff
+#define MCHP_BDP_DATTR_LANE_POS 8
+#define MCHP_BDP_DATTR_LANE_MASK GENMASK(9, 8)
+#define MCHP_BDP_DATTR_LANE_0 0
+#define MCHP_BDP_DATTR_LANE_1 (1U << 8)
+#define MCHP_BDP_DATTR_LANE_2 (2U << 8)
+#define MCHP_BDP_DATTR_LANE_3 (3U << 8)
+#define MCHP_BDP_DATTR_LEN_POS 10
+#define MCHP_BDP_DATTR_LEN_MASK GENMASK(11, 10)
+#define MCHP_BDP_DATTR_LEN_1 0
+#define MCHP_BDP_DATTR_LEN_2 (1U << 10)
+#define MCHP_BDP_DATTR_LEN_4 (2U << 10)
+#define MCHP_BDP_DATTR_LEN_INVAL (3U << 10)
+#define MCHP_BDP_DATTR_NE BIT(12)
+#define MCHP_BDP_DATTR_OVR BIT(13)
+#define MCHP_BDP_DATTR_THRH BIT(14)
+
+/* BDP Configuration */
+#define MCHP_BDP_CFG_FLUSH_FIFO BIT(0)
+#define MCHP_BDP_CFG_SNAPSHOT_CLR BIT(1)
+#define MCHP_BDP_CFG_FIFO_THRH_POS 8
+#define MCHP_BDP_CFG_FIFO_THRH_1 0
+#define MCHP_BDP_CFG_FIFO_THRH_4 (1U << 8)
+#define MCHP_BDP_CFG_FIFO_THRH_8 (2U << 8)
+#define MCHP_BDP_CFG_FIFO_THRH_16 (3U << 8)
+#define MCHP_BDP_CFG_FIFO_THRH_20 (4U << 8)
+#define MCHP_BDP_CFG_FIFO_THRH_24 (5U << 8)
+#define MCHP_BDP_CFG_FIFO_THRH_28 (6U << 8)
+#define MCHP_BDP_CFG_FIFO_THRH_30 (7U << 8)
+#define MCHP_BDP_CFG_SRST BIT(31)
+
+/* BDP Status */
+#define MCHP_BDP_STATUS_MASK GENMASK(2, 0)
+#define MCHP_BDP_STATUS_NOT_EMPTY BIT(0)
+#define MCHP_BDP_STATUS_OVERRUN BIT(1)
+#define MCHP_BDP_STATUS_THRH BIT(2)
+
+/* BDP Interrupt enable */
+#define MCHP_BDP_IEN_THRH BIT(0)
+
+/* PWM SZ 144 pin package has 9 PWM's */
+#define MCHP_PWM_INSTANCES 9
+#define MCHP_PWM_ID_MAX (MCHP_PWM_INSTANCES)
+#define MCHP_PWM_SPACING 16
+#define MCHP_PWM_BASE(x) (MCHP_PWM_0_BASE + ((x)*MCHP_PWM_SPACING))
+
+/* TACH */
+#define MCHP_TACH_INSTANCES 4
+#define MCHP_TACH_SPACING 16
+#define MCHP_TACH_BASE(x) (MCHP_TACH_0_BASE + ((x)*MCHP_TACH_SPACING))
+#define MCHP_TACH_GIRQ 17
+#define MCHP_TACH_GIRQ_BIT(x) BIT(1 + (x))
+
+/* FAN */
+#define MCHP_FAN_INSTANCES 2
+#define MCHP_FAN_SPACING 0x80U
+#define MCHP_FAN_BASE(x) (MCHP_RPM2PWM0_BASE + ((x)*MCHP_FAN_SPACING))
+#define MCHP_FAN_SETTING(x) REG16(MCHP_FAN_BASE(x) + 0x0)
+#define MCHP_FAN_CFG1(x) REG8(MCHP_FAN_BASE(x) + 0x2)
+#define MCHP_FAN_CFG2(x) REG8(MCHP_FAN_BASE(x) + 0x3)
+#define MCHP_FAN_PWM_DIVIDE(x) REG8(MCHP_FAN_BASE(x) + 0x4)
+#define MCHP_FAN_GAIN(x) REG8(MCHP_FAN_BASE(x) + 0x5)
+#define MCHP_FAN_SPIN_UP(x) REG8(MCHP_FAN_BASE(x) + 0x6)
+#define MCHP_FAN_STEP(x) REG8(MCHP_FAN_BASE(x) + 0x7)
+#define MCHP_FAN_MIN_DRV(x) REG8(MCHP_FAN_BASE(x) + 0x8)
+#define MCHP_FAN_VALID_CNT(x) REG8(MCHP_FAN_BASE(x) + 0x9)
+#define MCHP_FAN_DRV_FAIL(x) REG16(MCHP_FAN_BASE(x) + 0xa)
+#define MCHP_FAN_TARGET(x) REG16(MCHP_FAN_BASE(x) + 0xc)
+#define MCHP_FAN_READING(x) REG16(MCHP_FAN_BASE(x) + 0xe)
+#define MCHP_FAN_BASE_FREQ(x) REG8(MCHP_FAN_BASE(x) + 0x10)
+#define MCHP_FAN_STATUS(x) REG8(MCHP_FAN_BASE(x) + 0x11)
+
+/* ACPI EC */
+#define MCHP_ACPI_EC_INSTANCES 5
+#define MCHP_ACPI_EC_MAX (MCHP_ACPI_EC_INSTANCES)
+#define MCHP_ACPI_EC_SPACING 0x400
+#define MCHP_ACPI_EC_BASE(x) (MCHP_ACPI_EC_0_BASE + ((x)*MCHP_ACPI_EC_SPACING))
+#define MCHP_ACPI_EC_GIRQ 15
+#define MCHP_ACPI_EC_IBF_GIRQ_BIT(x) BIT(5 + ((x)*2))
+#define MCHP_ACPI_EC_OBE_GIRQ_BIT(x) BIT(6 + ((x)*2))
+
+/* ACPI PM1 */
+#define MCHP_ACPI_PM1_ECREGS_OFS 0x100
+#define MCHP_ACPI_PM_RT_BASE MCHP_ACPI_PM1_BASE
+#define MCHP_ACPI_PM_EC_BASE (MCHP_ACPI_PM1_BASE + MCHP_ACPI_PM1_ECREGS_OFS)
+#define MCHP_ACPI_PM1_CTL_GIRQ_BIT BIT(15)
+#define MCHP_ACPI_PM1_EN_GIRQ_BIT BIT(16)
+#define MCHP_ACPI_PM1_STS_GIRQ_BIT BIT(17)
+
+/* 8042 */
+#define MCHP_8042_ECREGS_OFS 0x100
+#define MCHP_8042_GIRQ 15
+#define MCHP_8042_OBE_GIRQ_BIT BIT(18)
+#define MCHP_8042_IBF_GIRQ_BIT BIT(19)
+
+/* I2C controllers 0 - 4 include SMBus network layer functionality. */
+#define MCHP_I2C_CTRL0 0
+#define MCHP_I2C_CTRL1 1
+#define MCHP_I2C_CTRL2 2
+#define MCHP_I2C_CTRL3 3
+#define MCHP_I2C_CTRL4 4
+#define MCHP_I2C_CTRL_MAX 5
+
+#define MCHP_I2C_SEP0 0x400
+
+/*
+ * MEC172x SZ(144-pin) package implements 15 ports. No Port 11.
+ * LJ(176-pin) package implements 16 ports.
+ * Any port can be mapped to any I2C controller.
+ * I2C port values must be zero based consecutive whole numbers due to
+ * port number used as an index for I2C the mutex list, etc.
+ * Refer to chip i2c_port_to_controller function for mapping
+ * of port to controller.
+ * Locking must occur by-controller (not by-port).
+ */
+#if (defined(CHIP_VARIANT_MEC1721LJ) || defined(CHIP_VARIANT_MEC1723LJ) || \
+     defined(CHIP_VARIANT_MEC1727LJ))
+#define MCHP_I2C_PORT_MASK GENMASK(15, 0)
+#else
+#define MCHP_I2C_PORT_MASK (GENMASK(15, 0) & ~BIT(11))
+#endif
+enum MCHP_i2c_port {
+	MCHP_I2C_PORT0 = 0,
+	MCHP_I2C_PORT1,
+	MCHP_I2C_PORT2,
+	MCHP_I2C_PORT3,
+	MCHP_I2C_PORT4,
+	MCHP_I2C_PORT5,
+	MCHP_I2C_PORT6,
+	MCHP_I2C_PORT7,
+	MCHP_I2C_PORT8,
+	MCHP_I2C_PORT9,
+	MCHP_I2C_PORT10,
+	MCHP_I2C_PORT11,
+	MCHP_I2C_PORT12,
+	MCHP_I2C_PORT13,
+	MCHP_I2C_PORT14,
+	MCHP_I2C_PORT15,
+	MCHP_I2C_PORT_COUNT,
+};
+
+/* I2C ports & Configs */
+#define I2C_CONTROLLER_COUNT MCHP_I2C_CTRL_MAX
+#define I2C_PORT_COUNT MCHP_I2C_PORT_COUNT
+
+/* All I2C controllers connected to GIRQ13 */
+#define MCHP_I2C_GIRQ 13
+/* I2C[0:7] -> GIRQ13 bits[0:7] */
+#define MCHP_I2C_GIRQ_BIT(n) BIT((n))
+
+/* Keyboard scan matrix */
+#define MCHP_KS_GIRQ 21
+#define MCHP_KS_GIRQ_BIT BIT(25)
+#define MCHP_KS_DIRECT_NVIC 135
+
+/* ADC */
+#if (defined(CHIP_VARIANT_MEC1721LJ) || defined(CHIP_VARIANT_MEC1723LJ) || \
+     defined(CHIP_VARIANT_MEC1727LJ))
+#define MCHP_ADC_CHAN_MASK GENMASK(15, 0)
+#else
+#define MCHP_ADC_CHAN_MASK GENMASK(7, 0)
+#endif
+#define MCHP_ADC_GIRQ 17
+#define MCHP_ADC_GIRQ_SINGLE_BIT BIT(8)
+#define MCHP_ADC_GIRQ_REPEAT_BIT BIT(9)
+#define MCHP_ADC_SINGLE_DIRECT_NVIC 78
+#define MCHP_ADC_REPEAT_DIRECT_NVIC 79
+#define MCHP_ADC_CONFIG REG32(MCHP_ADC_BASE + 0x7c)
+#define MCHP_ADC_CONFIG_DFLT 0x0101U
+#define MCHP_ADC_CFG_CLK_LO_TM_MSK GENMASK(7, 0)
+#define MCHP_ADC_CFG_CLK_HI_TM_MSK GENMASK(15, 8)
+#define MCHP_ADC_VREF_CSEL REG32(MCHP_ADC_BASE + 0x80)
+#define MCHP_ADC_VREF_CSEL_MSK(ch) (0x03U << ((ch)*2U))
+#define MCHP_ADC_VREF_CSEL_GPIO(ch) BIT((ch)*2U)
+#define MCHP_ADC_VREF_CTRL REG32(MCHP_ADC_BASE + 0x84)
+#define MCHP_ADC_VREF_CTRL_DFLT 0U
+#define MCHP_ADC_VCTRL_CHRG_DLY_MSK GENMASK(15, 0)
+#define MCHP_ADC_VCTRL_SW_DLY_MSK GENMASK(28, 16)
+#define MCHP_ADC_VCTRL_DRV_UNUSED_LO BIT(29)
+#define MCHP_ADC_VCTRL_SEL_STS_RO_POS 30
+#define MCHP_ADC_VCTRL_SEL_STS_RO_MSK GENMASK(31, 30)
+#define MCHP_ADC_SAR_ADC_CTRL REG32(MCHP_ADC_BASE + 0x88)
+#define MCHP_ADC_SAR_ADC_CTRL_DFLT ((0x202U << 7) | (0x03U << 1))
+#define MCHP_ADC_SAC_DIFF_INPUT BIT(0)
+#define MCHP_ADC_SAC_RES_POS 1
+#define MCHP_ADC_SAC_RES_MSK GENMASK(2, 1)
+#define MCHP_ADC_SAC_RES_10BIT (2U << 1)
+#define MCHP_ADC_SAC_RES_12BIT (3U << 1)
+#define MCHP_ADC_SAC_RJ_10BIT BIT(3)
+#define MCHP_ADC_SAC_WU_DLY_POS 7
+#define MCHP_ADC_SAC_WU_DLY_MSK GENMASK(16, 7)
+#define MCHP_ADC_SAC_WU_DLY_DLFT (0x202U << 7)
+
+/* Hibernation timer */
+#define MCHP_HTIMER_SPACING 0x20
+#define MCHP_HTIMER_ADDR(n) (MCHP_HTIMER_BASE + ((n)*MCHP_HTIMER_SPACING))
+#define MCHP_HTIMER_GIRQ 21
+/* HTIMER[0:1] -> GIRQ21 bits[1:2] */
+#define MCHP_HTIMER_GIRQ_BIT(n) BIT(1 + (n))
+#define MCHP_HTIMER_DIRECT_NVIC(n) (112 + (n))
+
+/* General Purpose SPI (GP-SPI) */
+#define MCHP_SPI_BASE(port) (MCHP_GPSPI0_BASE + ((port)*0x80))
+#define MCHP_SPI_AR(port) REG8(MCHP_SPI_BASE(port) + 0x00)
+#define MCHP_SPI_CR(port) REG8(MCHP_SPI_BASE(port) + 0x04)
+#define MCHP_SPI_SR(port) REG8(MCHP_SPI_BASE(port) + 0x08)
+#define MCHP_SPI_TD(port) REG8(MCHP_SPI_BASE(port) + 0x0c)
+#define MCHP_SPI_RD(port) REG8(MCHP_SPI_BASE(port) + 0x10)
+#define MCHP_SPI_CC(port) REG8(MCHP_SPI_BASE(port) + 0x14)
+#define MCHP_SPI_CG(port) REG8(MCHP_SPI_BASE(port) + 0x18)
+/* Addresses of TX/RX register used in tables */
+#define MCHP_SPI_TD_ADDR(ctrl) (MCHP_SPI_BASE(ctrl) + 0x0c)
+#define MCHP_SPI_RD_ADDR(ctrl) (MCHP_SPI_BASE(ctrl) + 0x10)
+/* All GP-SPI controllers connected to GIRQ18 */
+#define MCHP_SPI_GIRQ 18
+#define MCHP_SPI_GIRQ_TXBE_BIT(x) BIT(2 + ((x)*2))
+#define MCHP_SPI_GIRQ_RXBF_BIT(x) BIT(3 + ((x)*2))
+#define MCHP_GPSPI0_ID 0
+#define MCHP_GPSPI1_ID 1
+
+/*
+ * Quad Master SPI (QMSPI)
+ * MEC172x implements 16 descriptors, support for two chip selects,
+ * chip select timing and a local DMA unit with 3 RX channels and
+ * 3 TX channels. It retains support of the legacy DMA block.
+ */
+#define MCHP_QMSPI_MAX_DESCR 16
+#define MCHP_QMSPI_GIRQ 18
+#define MCHP_QMSPI_GIRQ_BIT BIT(1)
+#define MCHP_QMSPI_DIRECT_NVIC 91
+/* SAF DMA mode when QMSPI when eSPI SAF is enabled */
+#define MCHP_QMSPI_M_SAF_EN BIT(2)
+/* Local DMA enables in Mode register */
+#define MCHP_QMSPI_M_LDRX_EN BIT(3)
+#define MCHP_QMSPI_M_LDTX_EN BIT(4)
+/* Chip select implemented in bit[13:12] of the Mode register. */
+#define MCHP_QMSPI_M_CS_POS 12
+#define MCHP_QMSPI_M_CS_MASK0 0x03
+#define MCHP_QMSPI_M_CS_MASK GENMASK(13, 12)
+#define MCHP_QMSPI_M_CS0 0U
+#define MCHP_QMSPI_M_CS1 BIT(12)
+/* QMSPI alternate clock divider when CS1 is active. */
+#define MCHP_QMSPI0_ALTM REG32(MCHP_QMSPI0_BASE + 0xc0)
+#define MCHP_QMSPI0_ALTM_EN BIT(0)
+/* QMSPI taps select */
+#define MCHP_QMSPI0_TAPS REG32(MCHP_QMSPI0_BASE + 0xd0)
+/* QMSPI Taps adjust */
+#define MCHP_QMSPI0_TAPS_ADJ REG32(MCHP_QMSPI0_BASE + 0xd4)
+#define MCHP_QMSPI0_TAPS_SCK_POS 0
+#define MCHP_QMSPI0_TAPS_SCK_MSK GENMASK(7, 0)
+#define MCHP_QMSPI0_TAPS_CTL_POS 8
+#define MCHP_QMSPI0_TAPS_CTL_MSK GENMASK(15, 8)
+/* QMSPI Taps control */
+#define MCHP_QMSPI0_TAPS_CTRL REG32(MCHP_QMSPI0_BASE + 0xd4)
+#define MCHP_QMSPI0_TAPS_CTRL_MODE_POS 0
+#define MCHP_QMSPI0_TAPS_CTRL_MODE_MSK GENMASK(1, 0)
+#define MCHP_QMSPI0_TAPS_CTRL_UPDATE BIT(2)
+#define MCHP_QMSPI0_TAPS_CTRL_GO BIT(8)
+#define MCHP_QMSPI0_TAPS_CTRL_MULT_POS 16
+#define MCHP_QMSPI0_TAPS_CTRL_MULT_MSK GENMASK(18, 16)
+/* QMSPI LDMA descriptor enables */
+#define MCHP_QMSPI0_LDRX_DEN REG32(MCHP_QMSPI0_BASE + 0x100)
+#define MCHP_QMSPI0_LDTX_DEN REG32(MCHP_QMSPI0_BASE + 0x104)
+/*
+ * QMSPI LDMA channel registers.
+ * Each channel implement 3 32-bit registers:
+ * control, memory base address, and transfer length.
+ */
+#define MCHP_QMSPI0_LDRX_CHANS 3U
+#define MCHP_QMSPI0_LDTX_CHANS 3U
+#define MCHP_QMSPI0_LDRX_CTRL(n) REG32(MCHP_QMSPI0_BASE + 0x110 + ((n)*16U))
+#define MCHP_QMSPI0_LDRX_MBASE(n) REG32(MCHP_QMSPI0_BASE + 0x114 + ((n)*16U))
+#define MCHP_QMSPI0_LDRX_LEN(n) REG32(MCHP_QMSPI0_BASE + 0x118 + ((n)*16U))
+#define MCHP_QMSPI0_LDTX_CTRL(n) REG32(MCHP_QMSPI0_BASE + 0x140 + ((n)*16U))
+#define MCHP_QMSPI0_LDTX_MBASE(n) REG32(MCHP_QMSPI0_BASE + 0x144 + ((n)*16U))
+#define MCHP_QMSPI0_LDTX_LEN(n) REG32(MCHP_QMSPI0_BASE + 0x148 + ((n)*16U))
+/* LDMA RX or TX channel control register */
+#define MCHP_QMSPI_LDC_MSK GENMASK(6, 0)
+#define MCHP_QMSPI_LDC_EN BIT(0)
+#define MCHP_QMSPI_LDC_RSTART_EN BIT(1)
+#define MCHP_QMSPI_LDC_RSTART_MA_EN BIT(2)
+#define MCHP_QMSPI_LDC_LEN_EN BIT(3)
+#define MCHP_QMSPI_LDC_ACC_SZ_POS 4
+#define MCHP_QMSPI_LDC_ACC_SZ_MSK GENMASK(5, 4)
+#define MCHP_QMSPI_LDC_ACC_1BYTE 0
+#define MCHP_QMSPI_LDC_ACC_2BYTES (1U << 4)
+#define MCHP_QMSPI_LDC_ACC_4BYTES (2U << 4)
+#define MCHP_QMSPI_LDC_INCR_ADDR BIT(6)
+
+/* eSPI */
+/* IO BAR defines. Use with MCHP_ESPI_IO_BAR_xxxx macros */
+#define MCHP_ESPI_IO_BAR_ID_CFG_PORT 0
+#define MCHP_ESPI_IO_BAR_ID_MEM_CMPNT 1
+#define MCHP_ESPI_IO_BAR_ID_MAILBOX 2
+#define MCHP_ESPI_IO_BAR_ID_8042 3
+#define MCHP_ESPI_IO_BAR_ID_ACPI_EC0 4
+#define MCHP_ESPI_IO_BAR_ID_ACPI_EC1 5
+#define MCHP_ESPI_IO_BAR_ID_ACPI_EC2 6
+#define MCHP_ESPI_IO_BAR_ID_ACPI_EC3 7
+#define MCHP_ESPI_IO_BAR_ID_ACPI_EC4 8
+#define MCHP_ESPI_IO_BAR_ID_ACPI_PM1 9
+#define MCHP_ESPI_IO_BAR_ID_P92 0xA
+#define MCHP_ESPI_IO_BAR_ID_UART0 0xB
+#define MCHP_ESPI_IO_BAR_ID_UART1 0xC
+#define MCHP_ESPI_IO_BAR_ID_EMI0 0xD
+#define MCHP_ESPI_IO_BAR_ID_EMI1 0xE
+#define MCHP_ESPI_IO_BAR_ID_EMI2 0xF
+#define MCHP_ESPI_IO_BAR_BDP0 0x10
+#define MCHP_ESPI_IO_BAR_BDP0_ALT 0x11
+#define MCHP_ESPI_IO_BAR_RTC 0x12
+#define MCHP_ESPI_IO_BAR_TB32 0x14
+#define MCHP_ESPI_IO_BAR_GLUE 0x16
+
+/* Use with MCHP_ESPI_MBAR_EC_xxxx(x) macros */
+#define MCHP_ESPI_MBAR_ID_MBOX 0
+#define MCHP_ESPI_MBAR_ID_ACPI_EC_0 1
+#define MCHP_ESPI_MBAR_ID_ACPI_EC_1 2
+#define MCHP_ESPI_MBAR_ID_ACPI_EC_2 3
+#define MCHP_ESPI_MBAR_ID_ACPI_EC_3 4
+#define MCHP_ESPI_MBAR_ID_ACPI_EC_4 5
+#define MCHP_ESPI_MBAR_ID_EMI_0 6
+#define MCHP_ESPI_MBAR_ID_EMI_1 7
+#define MCHP_ESPI_MBAR_ID_EMI_2 8
+#define MCHP_ESPI_MBAR_ID_TB32 9
+
+/* Use with MCHP_ESPI_IO_SERIRQ_REG(x) */
+#define MCHP_ESPI_SIRQ_MBOX 0 /* Host SIRQ */
+#define MCHP_ESPI_SIRQ_MBOX_SMI 1 /* Host SMI */
+#define MCHP_ESPI_SIRQ_8042_KB 2 /* KIRQ */
+#define MCHP_ESPI_SIRQ_8042_MS 3 /* MIRQ */
+#define MCHP_ESPI_SIRQ_ACPI_EC0_OBF 4
+#define MCHP_ESPI_SIRQ_ACPI_EC1_OBF 5
+#define MCHP_ESPI_SIRQ_ACPI_EC2_OBF 6
+#define MCHP_ESPI_SIRQ_ACPI_EC3_OBF 7
+#define MCHP_ESPI_SIRQ_ACPI_EC4_OBF 8
+#define MCHP_ESPI_SIRQ_UART0 9
+#define MCHP_ESPI_SIRQ_UART1 10
+#define MCHP_ESPI_SIRQ_EMI0_HEV 11 /* Host Event */
+#define MCHP_ESPI_SIRQ_EMI0_EC2H 12 /* EC to Host */
+#define MCHP_ESPI_SIRQ_EMI1_HEV 13
+#define MCHP_ESPI_SIRQ_EMI1_EC2H 14
+#define MCHP_ESPI_SIRQ_EMI2_HEV 15
+#define MCHP_ESPI_SIRQ_EMI2_EC2H 16
+#define MCHP_ESPI_SIRQ_RTC 17
+#define MCHP_ESPI_SIRQ_EC 18
+
+#define MCHP_ESPI_MSVW_BASE (MCHP_ESPI_VW_BASE)
+#define MCHP_ESPI_SMVW_BASE ((MCHP_ESPI_VW_BASE) + 0x200ul)
+
+/*
+ * eSPI RESET, channel enables and operations except Master-to-Slave
+ * WWires are all on GIRQ19
+ */
+#define MCHP_ESPI_GIRQ 19
+#define MCHP_ESPI_PC_GIRQ_BIT BIT(0)
+#define MCHP_ESPI_BM1_GIRQ_BIT BIT(1)
+#define MCHP_ESPI_BM2_GIRQ_BIT BIT(2)
+#define MCHP_ESPI_LTR_GIRQ_BIT BIT(3)
+#define MCHP_ESPI_OOB_TX_GIRQ_BIT BIT(4)
+#define MCHP_ESPI_OOB_RX_GIRQ_BIT BIT(5)
+#define MCHP_ESPI_FC_GIRQ_BIT BIT(6)
+#define MCHP_ESPI_RESET_GIRQ_BIT BIT(7)
+#define MCHP_ESPI_VW_EN_GIRQ_BIT BIT(8)
+#define MCHP_ESPI_SAF_DONE_GIRQ_BIT BIT(9)
+#define MCHP_ESPI_SAF_ERR_GIRQ_BIT BIT(10)
+#define MCHP_ESPI_SAF_CACHE_GIRQ_BIT BIT(11)
+
+/* eSPI Master-to-Slave WWire interrupts are on GIRQ24 and GIRQ25 */
+#define MCHP_ESPI_MSVW_0_6_GIRQ 24
+#define MCHP_ESPI_MSVW_7_10_GIRQ 25
+/*
+ * Four source bits, SRC[0:3] per Master-to-Slave register
+ * v = MSVW [0:10]
+ * n = VWire SRC bit = [0:3]
+ */
+#define MCHP_ESPI_MSVW_GIRQ(v) (24 + ((v) > 6 ? 1 : 0))
+
+#define MCHP_ESPI_MSVW_SRC_GIRQ_BIT(v, n) \
+	(((v) > 6) ? (1ul << (((v)-7) + (n))) : (1ul << ((v) + (n))))
+
+/* DMA */
+#define MCHP_DMA_MAX_CHAN 16
+#define MCHP_DMA_CH_OFS 0x40
+#define MCHP_DMA_CH_OFS_BITPOS 6
+#define MCHP_DMA_CH_BASE (MCHP_DMA_BASE + MCHP_DMA_CH_OFS)
+
+/*
+ * Available DMA channels.
+ *
+ * On MCHP, any DMA channel may serve any device. Since we have
+ * 14 channels and 14 device request signals, we make each channel
+ * dedicated to the device of the same number.
+ */
+enum dma_channel {
+	/* Channel numbers */
+	MCHP_DMAC_I2C0_SLAVE = 0,
+	MCHP_DMAC_I2C0_MASTER,
+	MCHP_DMAC_I2C1_SLAVE,
+	MCHP_DMAC_I2C1_MASTER,
+	MCHP_DMAC_I2C2_SLAVE,
+	MCHP_DMAC_I2C2_MASTER,
+	MCHP_DMAC_I2C3_SLAVE,
+	MCHP_DMAC_I2C3_MASTER,
+	MCHP_DMAC_I2C4_SLAVE,
+	MCHP_DMAC_I2C5_MASTER,
+	MCHP_DMAC_QMSPI0_TX,
+	MCHP_DMAC_QMSPI0_RX,
+	MCHP_DMAC_SPI0_TX,
+	MCHP_DMAC_SPI0_RX,
+	MCHP_DMAC_SPI1_TX,
+	MCHP_DMAC_SPI1_RX,
+	/* Channel count */
+	MCHP_DMAC_COUNT,
+};
+
+/*
+ * Peripheral device DMA Device ID's for bits [15:9]
+ * in DMA channel control register.
+ */
+#define MCHP_DMA_I2C0_SLV_REQ_ID 0
+#define MCHP_DMA_I2C0_MTR_REQ_ID 1
+#define MCHP_DMA_I2C1_SLV_REQ_ID 2
+#define MCHP_DMA_I2C1_MTR_REQ_ID 3
+#define MCHP_DMA_I2C2_SLV_REQ_ID 4
+#define MCHP_DMA_I2C2_MTR_REQ_ID 5
+#define MCHP_DMA_I2C3_SLV_REQ_ID 6
+#define MCHP_DMA_I2C3_MTR_REQ_ID 7
+#define MCHP_DMA_I2C4_SLV_REQ_ID 8
+#define MCHP_DMA_I2C4_MTR_REQ_ID 9
+#define MCHP_DMA_QMSPI0_TX_REQ_ID 10
+#define MCHP_DMA_QMSPI0_RX_REQ_ID 11
+#define MCHP_DMA_SPI0_TX_REQ_ID 12
+#define MCHP_DMA_SPI0_RX_REQ_ID 13
+#define MCHP_DMA_SPI1_TX_REQ_ID 14
+#define MCHP_DMA_SPI1_RX_REQ_ID 15
+
+/*
+ * Hardware delay register.
+ * Write of 0 <= n <= 31 will stall the Cortex-M4
+ * for n+1 microseconds. Interrupts will not be
+ * serviced during the delay period. Reads have
+ * no effect.
+ */
+#define MCHP_USEC_DELAY_REG_ADDR 0x08000000
+#define MCHP_USEC_DELAY(x) (REG8(MCHP_USEC_DELAY_REG_ADDR) = (x))
+
+#endif /* #ifndef __ASSEMBLER__ */
diff --git a/chip/mchp/registers.h b/chip/mchp/registers.h
index 05ecb42aad..7b541b18da 100644
--- a/chip/mchp/registers.h
+++ b/chip/mchp/registers.h
@@ -1,1487 +1,547 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Register map for Microchip MEC family processors
  */
-
 #ifndef __CROS_EC_REGISTERS_H
 #define __CROS_EC_REGISTERS_H
 
 #include "common.h"
+#include "compile_time_macros.h"
+
+#if defined(CHIP_FAMILY_MEC152X)
+#include "registers-mec152x.h"
+#elif defined(CHIP_FAMILY_MEC170X)
+#include "registers-mec1701.h"
+#elif defined(CHIP_FAMILY_MEC172X)
+#include "registers-mec172x.h"
+#else
+#error "Unsupported chip family"
+#endif
 
-/*
- * Helper function for RAM address aliasing
- * NOTE: MCHP AHB masters do NOT require aliasing.
- * Cortex-M4 bit-banding does require aliasing of the
- * DATA SRAM region.
- */
-#define MCHP_RAM_ALIAS(x)   \
-	((x) >= 0x118000 ? (x) - 0x118000 + 0x20000000 : (x))
+/* Common registers */
+/* EC Interrupt aggregator (ECIA) */
+#define MCHP_INT_SOURCE(x) REG32(MCHP_INTx_BASE(x) + 0x0)
+#define MCHP_INT_ENABLE(x) REG32(MCHP_INTx_BASE(x) + 0x4)
+#define MCHP_INT_RESULT(x) REG32(MCHP_INTx_BASE(x) + 0x8)
+#define MCHP_INT_DISABLE(x) REG32(MCHP_INTx_BASE(x) + 0xc)
+#define MCHP_INT_BLK_EN REG32(MCHP_INT_BASE + 0x200)
+#define MCHP_INT_BLK_DIS REG32(MCHP_INT_BASE + 0x204)
+#define MCHP_INT_BLK_IRQ REG32(MCHP_INT_BASE + 0x208)
 
 /* EC Chip Configuration */
-#define MCHP_CHIP_BASE      0x400fff00
-#define MCHP_CHIP_DEV_ID    REG8(MCHP_CHIP_BASE + 0x20)
-#define MCHP_CHIP_DEV_REV   REG8(MCHP_CHIP_BASE + 0x21)
-
+#define MCHP_CHIP_LEGACY_DEV_ID REG8(MCHP_CHIP_BASE + 0x20)
+#define MCHP_CHIP_LEGACY_DEV_REV REG8(MCHP_CHIP_BASE + 0x21)
 
 /* Power/Clocks/Resets */
-#define MCHP_PCR_BASE       0x40080100
-
-#define MCHP_PCR_SYS_SLP_CTL	REG32(MCHP_PCR_BASE + 0x00)
-#define MCHP_PCR_PROC_CLK_CTL	REG32(MCHP_PCR_BASE + 0x04)
-#define MCHP_PCR_SLOW_CLK_CTL	REG32(MCHP_PCR_BASE + 0x08)
-#define MCHP_PCR_CHIP_OSC_ID	REG32(MCHP_PCR_BASE + 0x0C)
-#define MCHP_PCR_PWR_RST_STS	REG32(MCHP_PCR_BASE + 0x10)
-#define MCHP_PCR_PWR_RST_CTL	REG32(MCHP_PCR_BASE + 0x14)
-#define MCHP_PCR_SYS_RST	REG32(MCHP_PCR_BASE + 0x18)
-#define MCHP_PCR_SLP_EN0	REG32(MCHP_PCR_BASE + 0x30)
-#define MCHP_PCR_SLP_EN1	REG32(MCHP_PCR_BASE + 0x34)
-#define MCHP_PCR_SLP_EN2	REG32(MCHP_PCR_BASE + 0x38)
-#define MCHP_PCR_SLP_EN3	REG32(MCHP_PCR_BASE + 0x3C)
-#define MCHP_PCR_SLP_EN4	REG32(MCHP_PCR_BASE + 0x40)
-#define MCHP_PCR_CLK_REQ0	REG32(MCHP_PCR_BASE + 0x50)
-#define MCHP_PCR_CLK_REQ1	REG32(MCHP_PCR_BASE + 0x54)
-#define MCHP_PCR_CLK_REQ2	REG32(MCHP_PCR_BASE + 0x58)
-#define MCHP_PCR_CLK_REQ3	REG32(MCHP_PCR_BASE + 0x5C)
-#define MCHP_PCR_CLK_REQ4	REG32(MCHP_PCR_BASE + 0x60)
-#define MCHP_PCR_RST_EN0	REG32(MCHP_PCR_BASE + 0x70)
-#define MCHP_PCR_RST_EN1	REG32(MCHP_PCR_BASE + 0x74)
-#define MCHP_PCR_RST_EN2	REG32(MCHP_PCR_BASE + 0x78)
-#define MCHP_PCR_RST_EN3	REG32(MCHP_PCR_BASE + 0x7C)
-#define MCHP_PCR_RST_EN4	REG32(MCHP_PCR_BASE + 0x80)
-
-#define MCHP_PCR_SLP_EN(x)	REG32(MCHP_PCR_BASE + 0x30 + ((x)<<2))
-#define MCHP_PCR_CLK_REQ(x)	REG32(MCHP_PCR_BASE + 0x50 + ((x)<<2))
-#define MCHP_PCR_RST_EN(x)	REG32(MCHP_PCR_BASE + 0x70 + ((x)<<2))
-
-#define MCHP_PCR_SLP_RST_REG_MAX	(5)
+#define MCHP_PCR_SYS_SLP_CTL REG32(MCHP_PCR_BASE + 0x00)
+#define MCHP_PCR_PROC_CLK_CTL REG32(MCHP_PCR_BASE + 0x04)
+#define MCHP_PCR_SLOW_CLK_CTL REG32(MCHP_PCR_BASE + 0x08)
+#define MCHP_PCR_CHIP_OSC_ID REG32(MCHP_PCR_BASE + 0x0C)
+#define MCHP_PCR_PWR_RST_STS REG32(MCHP_PCR_BASE + 0x10)
+#define MCHP_PCR_PWR_RST_CTL REG32(MCHP_PCR_BASE + 0x14)
+#define MCHP_PCR_SYS_RST REG32(MCHP_PCR_BASE + 0x18)
+#define MCHP_PCR_SLP_EN0 REG32(MCHP_PCR_BASE + 0x30)
+#define MCHP_PCR_SLP_EN1 REG32(MCHP_PCR_BASE + 0x34)
+#define MCHP_PCR_SLP_EN2 REG32(MCHP_PCR_BASE + 0x38)
+#define MCHP_PCR_SLP_EN3 REG32(MCHP_PCR_BASE + 0x3C)
+#define MCHP_PCR_SLP_EN4 REG32(MCHP_PCR_BASE + 0x40)
+#define MCHP_PCR_CLK_REQ0 REG32(MCHP_PCR_BASE + 0x50)
+#define MCHP_PCR_CLK_REQ1 REG32(MCHP_PCR_BASE + 0x54)
+#define MCHP_PCR_CLK_REQ2 REG32(MCHP_PCR_BASE + 0x58)
+#define MCHP_PCR_CLK_REQ3 REG32(MCHP_PCR_BASE + 0x5C)
+#define MCHP_PCR_CLK_REQ4 REG32(MCHP_PCR_BASE + 0x60)
+#define MCHP_PCR_RST_EN0 REG32(MCHP_PCR_BASE + 0x70)
+#define MCHP_PCR_RST_EN1 REG32(MCHP_PCR_BASE + 0x74)
+#define MCHP_PCR_RST_EN2 REG32(MCHP_PCR_BASE + 0x78)
+#define MCHP_PCR_RST_EN3 REG32(MCHP_PCR_BASE + 0x7C)
+#define MCHP_PCR_RST_EN4 REG32(MCHP_PCR_BASE + 0x80)
+#define MCHP_PCR_SLP_EN(x) REG32(MCHP_PCR_BASE + 0x30 + ((x) << 2))
+#define MCHP_PCR_CLK_REQ(x) REG32(MCHP_PCR_BASE + 0x50 + ((x) << 2))
+#define MCHP_PCR_RST_EN(x) REG32(MCHP_PCR_BASE + 0x70 + ((x) << 2))
 
 /* Bit definitions for MCHP_PCR_SYS_SLP_CTL */
-#define MCHP_PCR_SYS_SLP_LIGHT	(0ul << 0)
-#define MCHP_PCR_SYS_SLP_HEAVY	(1ul << 0)
-#define MCHP_PCR_SYS_SLP_ALL	(1ul << 3)
-
+#define MCHP_PCR_SYS_SLP_LIGHT (0ul << 0)
+#define MCHP_PCR_SYS_SLP_HEAVY (1ul << 0)
+#define MCHP_PCR_SYS_SLP_ALL (1ul << 3)
 /*
  * Set/clear PCR sleep enable bit for single device
  * d bits[10:8] = register 0 - 4
  * d bits[4:0] = register bit position
  */
-#define MCHP_PCR_SLP_EN_DEV(d)	(MCHP_PCR_SLP_EN(((d) >> 8) & 0x07) |=\
-						(1ul << ((d) & 0x1f)))
-#define MCHP_PCR_SLP_DIS_DEV(d)	(MCHP_PCR_SLP_EN(((d) >> 8) & 0x07) &=\
-						~(1ul << ((d) & 0x1f)))
-
+#define MCHP_PCR_SLP_EN_DEV(d) \
+	(MCHP_PCR_SLP_EN(((d) >> 8) & 0x07) |= (1ul << ((d)&0x1f)))
+#define MCHP_PCR_SLP_DIS_DEV(d) \
+	(MCHP_PCR_SLP_EN(((d) >> 8) & 0x07) &= ~(1ul << ((d)&0x1f)))
 /*
  * Set/clear bit pattern specified by mask in a single PCR sleep enable
  * register.
  * id = zero based ID of sleep enable register (0-4)
  * m = bit mask of bits to change
  */
-#define MCHP_PCR_SLP_EN_DEV_MASK(id, m)  MCHP_PCR_SLP_EN((id)) |= (m)
-#define MCHP_PCR_SLP_DIS_DEV_MASK(id, m) MCHP_PCR_SLP_EN((id)) &= ~(m)
-
+#define MCHP_PCR_SLP_EN_DEV_MASK(id, m) (MCHP_PCR_SLP_EN((id)) |= (m))
+#define MCHP_PCR_SLP_DIS_DEV_MASK(id, m) (MCHP_PCR_SLP_EN((id)) &= ~(m))
 /* Slow Clock Control Mask */
-#define MCHP_PCR_SLOW_CLK_CTL_MASK	0x03FFul
-
-/* Sleep Enable, Clock Required, Reset on Sleep 0 bits */
-#define MCHP_PCR_ISPI		(0x0002)
-#define MCHP_PCR_EFUSE		(0x0001)
-#define MCHP_PCR_JTAG		(0x0000)
-
-/* Command all blocks to sleep */
-#define MCHP_PCR_SLP_EN0_ISPI	BIT(2)
-#define MCHP_PCR_SLP_EN0_EFUSE	BIT(1)
-#define MCHP_PCR_SLP_EN0_JTAG	BIT(0)
-#define MCHP_PCR_SLP_EN0_SLEEP	0x07ul
-
-/* Sleep Enable, Clock Required, Reset on Sleep 1 bits */
-#define MCHP_PCR_BTMR16_1	(BIT(8) + 31)
-#define MCHP_PCR_BTMR16_0	(BIT(8) + 30)
-#define MCHP_PCR_ECS		(BIT(8) + 29)
-#define MCHP_PCR_PWM8		(BIT(8) + 27)
-#define MCHP_PCR_PWM7		(BIT(8) + 26)
-#define MCHP_PCR_PWM6		(BIT(8) + 25)
-#define MCHP_PCR_PWM5		(BIT(8) + 24)
-#define MCHP_PCR_PWM4		(BIT(8) + 23)
-#define MCHP_PCR_PWM3		(BIT(8) + 22)
-#define MCHP_PCR_PWM2		(BIT(8) + 21)
-#define MCHP_PCR_PWM1		(BIT(8) + 20)
-#define MCHP_PCR_TACH2		(BIT(8) + 12)
-#define MCHP_PCR_TACH1		(BIT(8) + 11)
-#define MCHP_PCR_I2C0		(BIT(8) + 10)
-#define MCHP_PCR_WDT		(BIT(8) + 9)
-#define MCHP_PCR_CPU		(BIT(8) + 8)
-#define MCHP_PCR_TFDP		(BIT(8) + 7)
-#define MCHP_PCR_DMA		(BIT(8) + 6)
-#define MCHP_PCR_PMC		(BIT(8) + 5)
-#define MCHP_PCR_PWM0		(BIT(8) + 4)
-#define MCHP_PCR_TACH0		(BIT(8) + 2)
-#define MCHP_PCR_PECI		(BIT(8) + 1)
-#define MCHP_PCR_ECIA		(BIT(8) + 0)
-
-/* Command all blocks to sleep */
-#define MCHP_PCR_SLP_EN1_BTMR16_1	BIT(31)
-#define MCHP_PCR_SLP_EN1_BTMR16_0	BIT(30)
-#define MCHP_PCR_SLP_EN1_ECS		BIT(29)
-/* bit[28] reserved */
-#define MCHP_PCR_SLP_EN1_PWM_ALL	(BIT(4) + (0xff << 20))
-#define MCHP_PCR_SLP_EN1_PWM8		BIT(27)
-#define MCHP_PCR_SLP_EN1_PWM7		BIT(26)
-#define MCHP_PCR_SLP_EN1_PWM6		BIT(25)
-#define MCHP_PCR_SLP_EN1_PWM5		BIT(24)
-#define MCHP_PCR_SLP_EN1_PWM4		BIT(23)
-#define MCHP_PCR_SLP_EN1_PWM3		BIT(22)
-#define MCHP_PCR_SLP_EN1_PWM2		BIT(21)
-#define MCHP_PCR_SLP_EN1_PWM1		BIT(20)
-/* bits[19:13] reserved */
-#define MCHP_PCR_SLP_EN1_TACH2		BIT(12)
-#define MCHP_PCR_SLP_EN1_TACH1		BIT(11)
-#define MCHP_PCR_SLP_EN1_I2C0		BIT(10)
-#define MCHP_PCR_SLP_EN1_WDT		BIT(9)
-#define MCHP_PCR_SLP_EN1_CPU		BIT(8)
-#define MCHP_PCR_SLP_EN1_TFDP		BIT(7)
-#define MCHP_PCR_SLP_EN1_DMA		BIT(6)
-#define MCHP_PCR_SLP_EN1_PMC		BIT(5)
-#define MCHP_PCR_SLP_EN1_PWM0		BIT(4)
-/* bit[3] reserved */
-#define MCHP_PCR_SLP_EN1_TACH0		BIT(2)
-#define MCHP_PCR_SLP_EN1_PECI		BIT(1)
-#define MCHP_PCR_SLP_EN1_ECIA		BIT(0)
-/* all sleep enable 1 bits */
-#define MCHP_PCR_SLP_EN1_SLEEP		0xffffffff
-/*
- * block not used by default
- * Always use ECIA, PMC, CPU and ECS
- */
-#define MCHP_PCR_SLP_EN1_UNUSED_BLOCKS	0xdffffede
-
-/* Sleep Enable2, Clock Required2, Reset on Sleep2 bits */
-#define MCHP_PCR_P80CAP1		((2 << 8) + 26)
-#define MCHP_PCR_P80CAP0		((2 << 8) + 25)
-#define MCHP_PCR_ACPI_EC4		((2 << 8) + 23)
-#define MCHP_PCR_ACPI_EC3		((2 << 8) + 22)
-#define MCHP_PCR_ACPI_EC2		((2 << 8) + 21)
-#define MCHP_PCR_ESPI			((2 << 8) + 19)
-#define MCHP_PCR_RTC			((2 << 8) + 18)
-#define MCHP_PCR_MBOX			((2 << 8) + 17)
-#define MCHP_PCR_8042			((2 << 8) + 16)
-#define MCHP_PCR_ACPI_PM1		((2 << 8) + 15)
-#define MCHP_PCR_ACPI_EC1		((2 << 8) + 14)
-#define MCHP_PCR_ACPI_EC0		((2 << 8) + 13)
-#define MCHP_PCR_GCFG			((2 << 8) + 12)
-#define MCHP_PCR_UART1			((2 << 8) + 2)
-#define MCHP_PCR_UART0			((2 << 8) + 1)
-#define MCHP_PCR_LPC			((2 << 8) + 0)
-
-/* Command all blocks to sleep */
-/* bits[31:27] reserved */
-#define MCHP_PCR_SLP_EN2_P80CAP1	BIT(26)
-#define MCHP_PCR_SLP_EN2_P80CAP0	BIT(25)
-/* bit[24] reserved */
-#define MCHP_PCR_SLP_EN2_ACPI_EC4	BIT(23)
-#define MCHP_PCR_SLP_EN2_ACPI_EC3	BIT(22)
-#define MCHP_PCR_SLP_EN2_ACPI_EC2	BIT(21)
-/* bit[20] reserved */
-#define MCHP_PCR_SLP_EN2_ESPI		BIT(19)
-#define MCHP_PCR_SLP_EN2_RTC		BIT(18)
-#define MCHP_PCR_SLP_EN2_MAILBOX	BIT(17)
-#define MCHP_PCR_SLP_EN2_MIF8042	BIT(16)
-#define MCHP_PCR_SLP_EN2_ACPI_PM1	BIT(15)
-#define MCHP_PCR_SLP_EN2_ACPI_EC1	BIT(14)
-#define MCHP_PCR_SLP_EN2_ACPI_EC0	BIT(13)
-#define MCHP_PCR_SLP_EN2_GCFG		BIT(12)
-/* bits[11:3] reserved */
-#define MCHP_PCR_SLP_EN2_UART1		BIT(2)
-#define MCHP_PCR_SLP_EN2_UART0		BIT(1)
-#define MCHP_PCR_SLP_EN2_LPC		BIT(0)
-/* all sleep enable 2 bits */
-#define MCHP_PCR_SLP_EN2_SLEEP		0x07ffffff
-
-/* Sleep Enable3, Clock Required3, Reset on Sleep3 bits */
-#define MCHP_PCR_PWM9		((3 << 8) + 31)
-#define MCHP_PCR_CCT0		((3 << 8) + 30)
-#define MCHP_PCR_HTMR1		((3 << 8) + 29)
-#define MCHP_PCR_AESHASH	((3 << 8) + 28)
-#define MCHP_PCR_RNG		((3 << 8) + 27)
-#define MCHP_PCR_PKE		((3 << 8) + 26)
-#define MCHP_PCR_LED3		((3 << 8) + 25)
-#define MCHP_PCR_BTMR32_1	((3 << 8) + 24)
-#define MCHP_PCR_BTMR32_0	((3 << 8) + 23)
-#define MCHP_PCR_BTMR16_3	((3 << 8) + 22)
-#define MCHP_PCR_BTMR16_2	((3 << 8) + 21)
-#define MCHP_PCR_GPSPI1		((3 << 8) + 20)
-#define MCHP_PCR_BCM0		((3 << 8) + 19)
-#define MCHP_PCR_LED2		((3 << 8) + 18)
-#define MCHP_PCR_LED1		((3 << 8) + 17)
-#define MCHP_PCR_LED0		((3 << 8) + 16)
-#define MCHP_PCR_I2C3		((3 << 8) + 15)
-#define MCHP_PCR_I2C2		((3 << 8) + 14)
-#define MCHP_PCR_I2C1		((3 << 8) + 13)
-#define MCHP_PCR_RPMPWM0	((3 << 8) + 12)
-#define MCHP_PCR_KEYSCAN	((3 << 8) + 11)
-#define MCHP_PCR_HTMR0		((3 << 8) + 10)
-#define MCHP_PCR_GPSPI0		((3 << 8) + 9)
-#define MCHP_PCR_PS2_2		((3 << 8) + 7)
-#define MCHP_PCR_PS2_1		((3 << 8) + 6)
-#define MCHP_PCR_PS2_0		((3 << 8) + 5)
-#define MCHP_PCR_ADC		((3 << 8) + 3)
-
-/* Command all blocks to sleep */
-#define MCHP_PCR_SLP_EN3_PWM9		BIT(31)
-#define MCHP_PCR_SLP_EN3_CCT0		BIT(30)
-#define MCHP_PCR_SLP_EN3_HTMR1		BIT(29)
-#define MCHP_PCR_SLP_EN3_AESHASH	BIT(28)
-#define MCHP_PCR_SLP_EN3_RNG		BIT(27)
-#define MCHP_PCR_SLP_EN3_PKE		BIT(26)
-#define MCHP_PCR_SLP_EN3_LED3		BIT(25)
-#define MCHP_PCR_SLP_EN3_BTMR32_1	BIT(24)
-#define MCHP_PCR_SLP_EN3_BTMR32_0	BIT(23)
-#define MCHP_PCR_SLP_EN3_BTMR16_3	BIT(22)
-#define MCHP_PCR_SLP_EN3_BTMR16_2	BIT(21)
-#define MCHP_PCR_SLP_EN3_GPSPI1		BIT(20)
-#define MCHP_PCR_SLP_EN3_BCM0		BIT(19)
-#define MCHP_PCR_SLP_EN3_LED2		BIT(18)
-#define MCHP_PCR_SLP_EN3_LED1		BIT(17)
-#define MCHP_PCR_SLP_EN3_LED0		BIT(16)
-#define MCHP_PCR_SLP_EN3_I2C3		BIT(15)
-#define MCHP_PCR_SLP_EN3_I2C2		BIT(14)
-#define MCHP_PCR_SLP_EN3_I2C1		BIT(13)
-#define MCHP_PCR_SLP_EN3_RPMPWM0	BIT(12)
-#define MCHP_PCR_SLP_EN3_KEYSCAN	BIT(11)
-#define MCHP_PCR_SLP_EN3_HTMR0		BIT(10)
-#define MCHP_PCR_SLP_EN3_GPSPI0		BIT(9)
-/* bit[8] reserved */
-#define MCHP_PCR_SLP_EN3_PS2_2		BIT(7)
-#define MCHP_PCR_SLP_EN3_PS2_1		BIT(6)
-#define MCHP_PCR_SLP_EN3_PS2_0		BIT(5)
-/* bit[4] reserved */
-#define MCHP_PCR_SLP_EN3_ADC		BIT(3)
-/* bits[2:0] reserved */
-/* all sleep enable 3 bits */
-#define MCHP_PCR_SLP_EN3_SLEEP		0xfffffeed
-#define MCHP_PCR_SLP_EN3_PWM_ALL	(1ul << 31)
-
-/* Sleep Enable4, Clock Required4, Reset on Sleep4 bits */
-#define MCHP_PCR_FJCL		((4 << 8) + 15)
-#define MCHP_PCR_PSPI		((4 << 8) + 14)
-#define MCHP_PCR_PROCHOT	((4 << 8) + 13)
-#define MCHP_PCR_RCID2		((4 << 8) + 12)
-#define MCHP_PCR_RCID1		((4 << 8) + 11)
-#define MCHP_PCR_RCID0		((4 << 8) + 10)
-#define MCHP_PCR_BCM1		((4 << 8) + 9)
-#define MCHP_PCR_QMSPI		((4 << 8) + 8)
-#define MCHP_PCR_RPMPWM1	((4 << 8) + 7)
-#define MCHP_PCR_RTMR		((4 << 8) + 6)
-#define MCHP_PCR_CNT16_3	((4 << 8) + 5)
-#define MCHP_PCR_CNT16_2	((4 << 8) + 4)
-#define MCHP_PCR_CNT16_1	((4 << 8) + 3)
-#define MCHP_PCR_CNT16_0	((4 << 8) + 2)
-#define MCHP_PCR_PWM11		((4 << 8) + 1)
-#define MCHP_PCR_PWM10		((4 << 8) + 0)
-
-/* Command all blocks to sleep */
-#define MCHP_PCR_SLP_EN4_FJCL		BIT(15)
-#define MCHP_PCR_SLP_EN4_PSPI		BIT(14)
-#define MCHP_PCR_SLP_EN4_PROCHOT	BIT(13)
-#define MCHP_PCR_SLP_EN4_RCID2		BIT(12)
-#define MCHP_PCR_SLP_EN4_RCID1		BIT(11)
-#define MCHP_PCR_SLP_EN4_RCID0		BIT(10)
-#define MCHP_PCR_SLP_EN4_BCM1		BIT(9)
-#define MCHP_PCR_SLP_EN4_QMSPI		BIT(8)
-#define MCHP_PCR_SLP_EN4_RPMPWM1	BIT(7)
-#define MCHP_PCR_SLP_EN4_RTMR		BIT(6)
-#define MCHP_PCR_SLP_EN4_CNT16_3	BIT(5)
-#define MCHP_PCR_SLP_EN4_CNT16_2	BIT(4)
-#define MCHP_PCR_SLP_EN4_CNT16_1	BIT(3)
-#define MCHP_PCR_SLP_EN4_CNT16_0	BIT(2)
-#define MCHP_PCR_SLP_EN4_PWM_ALL	(3 << 0)
-#define MCHP_PCR_SLP_EN4_PWM11		BIT(1)
-#define MCHP_PCR_SLP_EN4_PWM10		BIT(0)
-/* all sleep enable 4 bits */
-#define MCHP_PCR_SLP_EN4_SLEEP		0x0000ffff
-
-/* Allow all blocks to request clocks */
-#define MCHP_PCR_SLP_EN0_WAKE	(~(MCHP_PCR_SLP_EN0_SLEEP))
-#define MCHP_PCR_SLP_EN1_WAKE	(~(MCHP_PCR_SLP_EN1_SLEEP))
-#define MCHP_PCR_SLP_EN2_WAKE	(~(MCHP_PCR_SLP_EN2_SLEEP))
-#define MCHP_PCR_SLP_EN3_WAKE	(~(MCHP_PCR_SLP_EN3_SLEEP))
-#define MCHP_PCR_SLP_EN4_WAKE	(~(MCHP_PCR_SLP_EN4_SLEEP))
-
-
-/* Bit definitions for MCHP_PCR_SLP_EN1/CLK_REQ1/RST_EN1 */
-
-/* Bit definitions for MCHP_PCR_SLP_EN2/CLK_REQ2/RST_EN2 */
-
-/* Bit definitions for MCHP_PCR_SLP_EN3/CLK_REQ3/RST_EN3 */
-#define MCHP_PCR_SLP_EN1_PKE		BIT(26)
-#define MCHP_PCR_SLP_EN1_NDRNG		BIT(27)
-#define MCHP_PCR_SLP_EN1_AES_SHA	BIT(28)
-#define MCHP_PCR_SLP_EN1_ALL_CRYPTO	(0x07 << 26)
-
-/* Bit definitions for MCHP_PCR_SLP_EN4/CLK_REQ4/RST_EN4 */
-
-
-/* Bit defines for MCHP_PCR_PWR_RST_STS */
-#define MCHP_PWR_RST_STS_VTR		BIT(6)
-#define MCHP_PWR_RST_STS_VBAT		BIT(5)
-
-/* Bit defines for MCHP_PCR_PWR_RST_CTL */
-#define MCHP_PCR_PWR_HOST_RST_SEL_BITPOS	8
-#define MCHP_PCR_PWR_HOST_RST_LRESET		1
-#define MCHP_PCR_PWR_HOST_RST_ESPI_PLTRST	0
-
-
-/* Bit defines for MCHP_PCR_SYS_RST */
-#define MCHP_PCR_SYS_SOFT_RESET  BIT(8)
-
+#define MCHP_PCR_SLOW_CLK_CTL_MASK 0x03FFul
 
 /* TFDP */
-#define MCHP_TFDP_BASE	0x40008c00
-#define MCHP_TFDP_DATA	REG8(MCHP_TFDP_BASE + 0x00)
-#define MCHP_TFDP_CTRL	REG8(MCHP_TFDP_BASE + 0x04)
-
-
-/* EC Subsystem */
-#define MCHP_EC_BASE			0x4000fc00
-#define MCHP_EC_AHB_ERR			REG32(MCHP_EC_BASE + 0x04)
-#define MCHP_EC_ID_RO			REG32(MCHP_EC_BASE + 0x10)
-#define MCHP_EC_AHB_ERR_EN		REG32(MCHP_EC_BASE + 0x14)
-#define MCHP_EC_INT_CTRL		REG32(MCHP_EC_BASE + 0x18)
-#define MCHP_EC_TRACE_EN		REG32(MCHP_EC_BASE + 0x1c)
-#define MCHP_EC_JTAG_EN			REG32(MCHP_EC_BASE + 0x20)
-#define MCHP_EC_WDT_CNT			REG32(MCHP_EC_BASE + 0x28)
-#define MCHP_EC_AES_SHA_SWAP_CTRL	REG8(MCHP_EC_BASE + 0x2c)
-#define MCHP_EC_CRYPTO_SRESET		REG8(MCHP_EC_BASE + 0x5c)
-#define MCHP_EC_GPIO_BANK_PWR		REG8(MCHP_EC_BASE + 0x64)
-
-/* MCHP_EC_JTAG_EN bit definitions */
-#define MCHP_JTAG_ENABLE		0x01
-/* bits [2:1] */
-#define MCHP_JTAG_MODE_4PIN		0x00
-/* ARM 2-pin SWD plus 1-pin Serial Wire Viewer (ITM) */
-#define MCHP_JTAG_MODE_SWD_SWV		0x02
-/* ARM 2-pin SWD with no SWV */
-#define MCHP_JTAG_MODE_SWD		0x04
-
-
-/* MCHP_EC_CRYPTO_SRESET bit definitions */
-#define MCHP_CRYPTO_NDRNG_SRST			0x01
-#define MCHP_CRYPTO_PKE_SRST			0x02
-#define MCHP_CRYPTO_AES_SHA_SRST		0x04
-#define MCHP_CRYPTO_ALL_SRST			0x07
-
-/* MCHP_GPIO_BANK_PWR bit definitions */
-#define MCHP_EC_GPIO_BANK_PWR_VTR1_18	(0x01)
-#define MCHP_EC_GPIO_BANK_PWR_VTR2_18	(0x02)
-#define MCHP_EC_GPIO_BANK_PWR_VTR3_18	(0x04)
-
-
-/* AHB ERR Enable */
-#define MCHP_EC_AHB_ERROR_ENABLE	0
-#define MCHP_EC_AHB_ERROR_DISABLE	1
-
-
-/* Interrupt aggregator */
-#define MCHP_INT_BASE       0x4000e000
-#define MCHP_INTx_BASE(x)   (MCHP_INT_BASE + ((x)<<4) + ((x)<<2) - 160)
-#define MCHP_INT_SOURCE(x)  REG32(MCHP_INTx_BASE(x) + 0x0)
-#define MCHP_INT_ENABLE(x)  REG32(MCHP_INTx_BASE(x) + 0x4)
-#define MCHP_INT_RESULT(x)  REG32(MCHP_INTx_BASE(x) + 0x8)
-#define MCHP_INT_DISABLE(x) REG32(MCHP_INTx_BASE(x) + 0xc)
-#define MCHP_INT_BLK_EN     REG32(MCHP_INT_BASE + 0x200)
-#define MCHP_INT_BLK_DIS    REG32(MCHP_INT_BASE + 0x204)
-#define MCHP_INT_BLK_IRQ    REG32(MCHP_INT_BASE + 0x208)
-#define MCHP_INT_GIRQ_FIRST	8
-#define MCHP_INT_GIRQ_LAST	26
-#define MCHP_INT_GIRQ_NUM	(26-8+1)
-
-/*
- * Bits for INT=13(GIRQ13) registers
- * SMBus[0:3] = bits[0:3]
- */
-#define MCHP_INT13_SMB(x)		(1ul << (x))
-
-
-/*
- * Bits for INT=14(GIRQ14) registers
- * DMA channels 0 - 13
- */
-#define MCHP_INT14_DMA(x)		(1ul << (x))
-
-
-/* Bits for INT=15(GIRQ15) registers
- * UART[0:1] = bits[0:1]
- * EMI[0:2] = bits[2:4]
- */
-#define MCHP_INT15_UART(x)		(1ul << ((x) & 0x01))
-#define MCHP_INT15_EMI(x)		(1ul << (2 + (x)))
-/*
- * ACPI_EC[0:4] IBF = bits[5,7,9,11,13]
- * ACPI_EC[0:4] OBE = bits[6,8,10,12,14]
- */
-#define MCHP_INT15_ACPI_EC_IBF(x)	(1ul << (5 + ((x) << 1)))
-#define MCHP_INT15_ACPI_EC_OBE(x)	(1ul << (6 + ((x) << 1)))
-#define MCHP_INT15_ACPI_PM1_CTL		(1ul << 15)
-#define MCHP_INT15_ACPI_PM1_EN		(1ul << 16)
-#define MCHP_INT15_ACPI_PM1_STS		(1ul << 17)
-#define MCHP_INT15_8042_OBE		(1ul << 18)
-#define MCHP_INT15_8042_IBF		(1ul << 19)
-#define MCHP_INT15_MAILBOX		(1ul << 20)
-#define MCHP_INT15_P80(x)		(1ul << (22 + ((x) & 0x01)))
-
-
-/* Bits for INT=16(GIRQ16) registers */
-#define MCHP_INT16_PKE_ERR		(1ul << 0)
-#define MCHP_INT16_PKE_DONE		(1ul << 1)
-#define MCHP_INT16_RNG_DONE		(1ul << 2)
-#define MCHP_INT16_AES_DONE		(1ul << 3)
-#define MCHP_INT16_HASH_DONE		(1ul << 4)
-
-
-/* Bits for INT=17(GIRQ17) registers */
-#define MCHP_INT17_PECI			(1ul << 0)
-/*    TACH[0:2] = bits[1:3] */
-#define MCHP_INT17_TACH(x)		(1ul << (1 + (x)))
-/*    RPMFAN_FAIL[0:1] = bits[4,6] */
-#define MCHP_INT17_RPMFAN_FAIL(x)	(1ul << (4 + ((x) << 1)))
-/*    RPMFAN_STALL[0:1] = bits[5,7] */
-#define MCHP_INT17_RPMFAN_STALL(x)	(1ul << (5 + ((x) << 1)))
-#define MCHP_INT17_ADC_SINGLE		(1ul << 8)
-#define MCHP_INT17_ADC_REPEAT		(1ul << 9)
-/*    RCIC[0:2] = bits[10:12] */
-#define MCHP_INT17_RCID(x)		(1ul << (10 + (x)))
-#define MCHP_INT17_LED_WDT(x)		(1ul << (13 + (x)))
-
-
-/* Bits for INT=18(GIRQ18) registers */
-#define MCHP_INT18_LPC			(1ul << 0)
-#define MCHP_INT18_QMSPI0		(1ul << 1)
-/*    SPI_TX[0:1] = bits[2,4] */
-#define MCHP_INT18_SPI_TX(x)		(1ul << (2 + ((x) << 1)))
-/*    SPI_RX[0:1] = bits[3,5] */
-#define MCHP_INT18_SPI_RX(x)		(1ul << (3 + ((x) << 1)))
-
-
-/* Bits for INT=19(GIRQ19) registers */
-#define MCHP_INT19_ESPI_PC		(1ul << 0)
-#define MCHP_INT19_ESPI_BM1		(1ul << 1)
-#define MCHP_INT19_ESPI_BM2		(1ul << 2)
-#define MCHP_INT19_ESPI_LTR		(1ul << 3)
-#define MCHP_INT19_ESPI_OOB_TX		(1ul << 4)
-#define MCHP_INT19_ESPI_OOB_RX		(1ul << 5)
-#define MCHP_INT19_ESPI_FC		(1ul << 6)
-#define MCHP_INT19_ESPI_RESET		(1ul << 7)
-#define MCHP_INT19_ESPI_VW_EN		(1ul << 8)
-
-
-/* Bits for INT=21(GIRQ21) registers */
-#define MCHP_INT21_RTOS_TMR		(1ul << 0)
-/*    HibernationTimer[0:1] = bits[1:2] */
-#define MCHP_INT21_HIB_TMR(x)		(1ul << (1 + (x)))
-#define MCHP_INT21_WEEK_ALARM		(1ul << 3)
-#define MCHP_INT21_WEEK_SUB		(1ul << 4)
-#define MCHP_INT21_WEEK_1SEC		(1ul << 5)
-#define MCHP_INT21_WEEK_1SEC_SUB	(1ul << 6)
-#define MCHP_INT21_WEEK_PWR_PRES	(1ul << 7)
-#define MCHP_INT21_RTC			(1ul << 8)
-#define MCHP_INT21_RTC_ALARM		(1ul << 9)
-#define MCHP_INT21_VCI_OVRD		(1ul << 10)
-/*    VCI_IN[0:6] = bits[11:17] */
-#define MCHP_INT21_VCI_IN(x)		(1ul << (11 + (x)))
-/*    PS2 Port Wake[0:4] =[0A,0B,1A,1B,2] = bits[18:22] */
-#define MCHP_INT21_PS2_WAKE(x)		(1ul << (18 + (x)))
-#define MCHP_INT21_KEYSCAN		(1ul << 25)
-
-/* Bits for INT=22(GIRQ22) wake only registers */
-#define MCHP_INT22_WAKE_ONLY_LPC	(1ul << 0)
-#define MCHP_INT22_WAKE_ONLY_I2C0	(1ul << 1)
-#define MCHP_INT22_WAKE_ONLY_I2C1	(1ul << 2)
-#define MCHP_INT22_WAKE_ONLY_I2C2	(1ul << 3)
-#define MCHP_INT22_WAKE_ONLY_I2C3	(1ul << 4)
-#define MCHP_INT22_WAKE_ONLY_ESPI	(1ul << 9)
-
-/* Bits for INT=23(GIRQ23) registers */
-/*    16-bit Basic Timers[0:3] = bits[0:3] */
-#define MCHP_INT23_BASIC_TMR16(x)	(1ul << (x))
-/*    32-bit Basic Timers[0:1] = bits[4:5] */
-#define MCHP_INT23_BASIC_TMR32(x)	(1ul << (4 + (x)))
-/*    16-bit Counter-Timer[0:3] = bits[6:9] */
-#define MCHP_INT23_CNT(x)		(1ul << (6 + (x)))
-#define MCHP_INT23_CCT_TMR		(1ul << 10)
-/*    CCT Capture events[0:5] = bits[11:16] */
-#define MCHP_INT23_CCT_CAP(x)		(1ul << (11 + (x)))
-/*    CCT Compare events[0:1] = bits[17:18] */
-#define MCHP_INT23_CCT_CMP(x)		(1ul << (17 + (x)))
-
-
-/* Bits for INT=24(GIRQ24) registers */
-/*    Master-to-Slave v=[0:6], Source=[0:3] */
-#define MCHP_INT24_MSVW_SRC(v, s)	(1ul << ((4 * (v)) + (s)))
-
-/* Bits for INT25(GIRQ25) registers */
-/*    Master-to-Slave v=[7:10], Source=[0:3] */
-#define MCHP_INT25_MSVW_SRC(v, s)	(1ul << ((4 * ((v)-7)) + (s)))
-
-/* End MCHP_INTxy bit definitions */
-
-/* UART Peripheral */
-#define MCHP_UART_CONFIG_BASE(x)     (0x400f2700 + ((x) * 0x400))
-#define MCHP_UART_RUNTIME_BASE(x)    (0x400f2400 + ((x) * 0x400))
-
-#define MCHP_UART_ACT(x)     REG8(MCHP_UART_CONFIG_BASE(x) + 0x30)
-#define MCHP_UART_CFG(x)     REG8(MCHP_UART_CONFIG_BASE(x) + 0xf0)
+#define MCHP_TFDP_DATA REG8(MCHP_TFDP_BASE + 0x00)
+#define MCHP_TFDP_CTRL REG8(MCHP_TFDP_BASE + 0x04)
 
+/* UART */
+#define MCHP_UART_ACT(x) REG8(MCHP_UART_CONFIG_BASE(x) + 0x30)
+#define MCHP_UART_CFG(x) REG8(MCHP_UART_CONFIG_BASE(x) + 0xf0)
 /* DLAB=0 */
 #define MCHP_UART_RB(x) /*R*/ REG8(MCHP_UART_RUNTIME_BASE(x) + 0x0)
 #define MCHP_UART_TB(x) /*W*/ REG8(MCHP_UART_RUNTIME_BASE(x) + 0x0)
-#define MCHP_UART_IER(x)      REG8(MCHP_UART_RUNTIME_BASE(x) + 0x1)
+#define MCHP_UART_IER(x) REG8(MCHP_UART_RUNTIME_BASE(x) + 0x1)
 /* DLAB=1 */
-#define MCHP_UART_PBRG0(x)    REG8(MCHP_UART_RUNTIME_BASE(x) + 0x0)
-#define MCHP_UART_PBRG1(x)    REG8(MCHP_UART_RUNTIME_BASE(x) + 0x1)
-
+#define MCHP_UART_PBRG0(x) REG8(MCHP_UART_RUNTIME_BASE(x) + 0x0)
+#define MCHP_UART_PBRG1(x) REG8(MCHP_UART_RUNTIME_BASE(x) + 0x1)
 #define MCHP_UART_FCR(x) /*W*/ REG8(MCHP_UART_RUNTIME_BASE(x) + 0x2)
 #define MCHP_UART_IIR(x) /*R*/ REG8(MCHP_UART_RUNTIME_BASE(x) + 0x2)
-#define MCHP_UART_LCR(x)       REG8(MCHP_UART_RUNTIME_BASE(x) + 0x3)
-#define MCHP_UART_MCR(x)       REG8(MCHP_UART_RUNTIME_BASE(x) + 0x4)
-#define MCHP_UART_LSR(x)       REG8(MCHP_UART_RUNTIME_BASE(x) + 0x5)
-#define MCHP_UART_MSR(x)       REG8(MCHP_UART_RUNTIME_BASE(x) + 0x6)
-#define MCHP_UART_SCR(x)       REG8(MCHP_UART_RUNTIME_BASE(x) + 0x7)
-/*
- * UART[0:1] connected to GIRQ15 bits[0:1]
- */
-#define MCHP_UART_GIRQ		15
-#define MCHP_UART_GIRQ_BIT(x)	(1ul << (x))
-
+#define MCHP_UART_LCR(x) REG8(MCHP_UART_RUNTIME_BASE(x) + 0x3)
+#define MCHP_UART_MCR(x) REG8(MCHP_UART_RUNTIME_BASE(x) + 0x4)
+#define MCHP_UART_LSR(x) REG8(MCHP_UART_RUNTIME_BASE(x) + 0x5)
+#define MCHP_UART_MSR(x) REG8(MCHP_UART_RUNTIME_BASE(x) + 0x6)
+#define MCHP_UART_SCR(x) REG8(MCHP_UART_RUNTIME_BASE(x) + 0x7)
 /* Bit defines for MCHP_UARTx_LSR */
-#define MCHP_LSR_TX_EMPTY     BIT(5)
-
-
-/* GPIO */
-#define MCHP_GPIO_BASE      0x40081000
-
-
-/* MCHP each Port contains 32 GPIO's.
- * GPIO Control 1 registers are 32-bit registers starting at
- * MCHP_GPIO_BASE.
- * index = octal GPIO number from MCHP specification.
- * port/bank = index >> 5
- * id = index & 0x1F
- *
- * The port/bank, id pair may also be used to access GPIO's via
- * parallel I/O registers if GPIO control is configured for
- * parallel I/O.
- *
- * From ec/chip/mec1701/config_chip.h
- * #define GPIO_PIN(index) ((index) >> 5), ((index) & 0x1F)
- *
- * GPIO Control 1 Address = 0x40081000 + (((bank << 5) + id) << 2)
- *
- * Example: GPIO043, Control 1 register address = 0x4008108c
- * port/bank = 0x23 >> 5 = 1
- * id        = 0x23 & 0x1F = 0x03
- * Control 1 Address = 0x40081000 + ((BIT(5) + 0x03) << 2) = 0x4008108c
- *
- * Example: GPIO235, Control 1 register address = 0x40081274
- * port/bank = 0x9d >> 5   = 4
- * id        = 0x9d & 0x1f = 0x1d
- * Control 1 Address = 0x40081000 + (((4 << 5) + 0x1d) << 2) = 0x40081274
- *
- */
-#define MCHP_GPIO_CTL(port, id) REG32(MCHP_GPIO_BASE + \
-	(((port << 5) + id) << 2))
-
-/* MCHP implements 6 GPIO ports */
-#define MCHP_GPIO_MAX_PORT	(7)
-
-#define UNIMPLEMENTED_GPIO_BANK 0
-
-/*
- * MEC1701 documentation GPIO numbers are octal, each control
- * register is located on a 32-bit boundary.
- */
-#define MCHP_GPIO_CTRL(gpio_num) REG32(MCHP_GPIO_BASE + \
-	((gpio_num) << 2))
-
-/*
- * GPIO control register bit fields
- */
-#define MCHP_GPIO_CTRL_PUD_BITPOS	0
-#define MCHP_GPIO_CTRL_PUD_MASK0	0x03
-#define MCHP_GPIO_CTRL_PUD_MASK		0x03
-#define MCHP_GPIO_CTRL_PUD_NONE		0x00
-#define MCHP_GPIO_CTRL_PUD_PU		0x01
-#define MCHP_GPIO_CTRL_PUD_PD		0x02
-#define MCHP_GPIO_CTRL_PUD_KEEPER	0x03
-#define MCHP_GPIO_CTRL_PWR_BITPOS	2
-#define MCHP_GPIO_CTRL_PWR_MASK0	0x03
-#define MCHP_GPIO_CTRL_PWR_MASK		(0x03 << 2)
-#define MCHP_GPIO_CTRL_PWR_VTR		(0x00 << 2)
-#define MCHP_GPIO_CTRL_PWR_OFF		(0x02 << 2)
-#define MCHP_GPIO_INTDET_MASK		(0xF0)
-#define MCHP_GPIO_INTDET_LVL_LO		(0x00)
-#define MCHP_GPIO_INTDET_LVL_HI		(0x10)
-#define MCHP_GPIO_INTDET_DISABLED	(0x40)
-#define MCHP_GPIO_INTDET_EDGE_RIS	(0xD0)
-#define MCHP_GPIO_INTDET_EDGE_FALL	(0xE0)
-#define MCHP_GPIO_INTDET_EDGE_BOTH	(0xF0)
-#define MCHP_GPIO_INTDET_EDGE_EN	(1u << 7)
-#define MCHP_GPIO_PUSH_PULL		(0u << 8)
-#define MCHP_GPIO_OPEN_DRAIN		(1u << 8)
-#define MCHP_GPIO_INPUT			(0u << 9)
-#define MCHP_GPIO_OUTPUT		(1u << 9)
-#define MCHP_GPIO_OUTSET_CTRL		(0u << 10)
-#define MCHP_GPIO_OUTSEL_PAR		(1u << 10)
-#define MCHP_GPIO_POLARITY_NINV		(0u << 11)
-#define MCHP_GPIO_POLARITY_INV		(1u << 11)
-#define MCHP_GPIO_CTRL_ALT_FUNC_BITPOS	12
-#define MCHP_GPIO_CTRL_ALT_FUNC_MASK0	0x0F
-#define MCHP_GPIO_CTRL_ALT_FUNC_MASK	(0x0F << 12)
-#define MCHP_GPIO_CTRL_FUNC_GPIO	(0 << 12)
-#define MCHP_GPIO_CTRL_FUNC_1		(1 << 12)
-#define MCHP_GPIO_CTRL_FUNC_2		(2 << 12)
-#define MCHP_GPIO_CTRL_FUNC_3		(3 << 12)
-#define MCHP_GPIO_CTRL_OUT_LVL		BIT(16)
-
-/* GPIO Parallel Input and Output registers.
- * gpio_bank in [0, 5]
- */
-#define MCHP_GPIO_PARIN(gpio_bank) REG32(MCHP_GPIO_BASE + 0x0300 +\
-	((gpio_bank) << 2))
-
-#define MCHP_GPIO_PAROUT(gpio_bank) REG32(MCHP_GPIO_BASE + 0x0380 +\
-	((gpio_bank) << 2))
+#define MCHP_LSR_TX_EMPTY BIT(5)
 
 /* Timer */
-#define MCHP_TMR16_MAX		(4)
-#define MCHP_TMR32_MAX		(2)
-#define MCHP_TMR16_BASE(x)  (0x40000c00 + (x) * 0x20)
-#define MCHP_TMR32_BASE(x)  (0x40000c80 + (x) * 0x20)
-
-#define MCHP_TMR16_CNT(x)   REG32(MCHP_TMR16_BASE(x) + 0x0)
-#define MCHP_TMR16_PRE(x)   REG32(MCHP_TMR16_BASE(x) + 0x4)
-#define MCHP_TMR16_STS(x)   REG32(MCHP_TMR16_BASE(x) + 0x8)
-#define MCHP_TMR16_IEN(x)   REG32(MCHP_TMR16_BASE(x) + 0xc)
-#define MCHP_TMR16_CTL(x)   REG32(MCHP_TMR16_BASE(x) + 0x10)
-#define MCHP_TMR32_CNT(x)   REG32(MCHP_TMR32_BASE(x) + 0x0)
-#define MCHP_TMR32_PRE(x)   REG32(MCHP_TMR32_BASE(x) + 0x4)
-#define MCHP_TMR32_STS(x)   REG32(MCHP_TMR32_BASE(x) + 0x8)
-#define MCHP_TMR32_IEN(x)   REG32(MCHP_TMR32_BASE(x) + 0xc)
-#define MCHP_TMR32_CTL(x)   REG32(MCHP_TMR32_BASE(x) + 0x10)
-/* 16-bit Basic Timers[0:3] = GIRQ23 bits[0:3] */
-#define MCHP_TMR16_GIRQ		23
-#define MCHP_TMR16_GIRQ_BIT(x)	(1ul << (x))
-/* 32-bit Basic Timers[0:1] = GIRQ23 bits[4:5] */
-#define MCHP_TMR32_GIRQ		23
-#define MCHP_TMR32_GIRQ_BIT(x)	(1ul << ((x) + 4))
+#define MCHP_TMR16_CNT(x) REG32(MCHP_TMR16_BASE(x) + 0x0)
+#define MCHP_TMR16_PRE(x) REG32(MCHP_TMR16_BASE(x) + 0x4)
+#define MCHP_TMR16_STS(x) REG32(MCHP_TMR16_BASE(x) + 0x8)
+#define MCHP_TMR16_IEN(x) REG32(MCHP_TMR16_BASE(x) + 0xc)
+#define MCHP_TMR16_CTL(x) REG32(MCHP_TMR16_BASE(x) + 0x10)
+#define MCHP_TMR32_CNT(x) REG32(MCHP_TMR32_BASE(x) + 0x0)
+#define MCHP_TMR32_PRE(x) REG32(MCHP_TMR32_BASE(x) + 0x4)
+#define MCHP_TMR32_STS(x) REG32(MCHP_TMR32_BASE(x) + 0x8)
+#define MCHP_TMR32_IEN(x) REG32(MCHP_TMR32_BASE(x) + 0xc)
+#define MCHP_TMR32_CTL(x) REG32(MCHP_TMR32_BASE(x) + 0x10)
 
 /* RTimer */
-#define MCHP_RTMR_BASE		(0x40007400)
-#define MCHP_RTMR_COUNTER	REG32(MCHP_RTMR_BASE + 0x00)
-#define MCHP_RTMR_PRELOAD	REG32(MCHP_RTMR_BASE + 0x04)
-#define MCHP_RTMR_CONTROL	REG8(MCHP_RTMR_BASE + 0x08)
-#define MCHP_RTMR_SOFT_INTR	REG8(MCHP_RTMR_BASE + 0x0c)
-/* RTimer GIRQ21 bit[0] */
-#define MCHP_RTMR_GIRQ		21
-#define MCHP_RTMR_GIRQ_BIT(x)	(1ul << 0)
-
-/* Watchdog */
-#define MCHP_WDG_BASE       0x40000000
-#define MCHP_WDG_LOAD       REG16(MCHP_WDG_BASE + 0x0)
-#define MCHP_WDG_CTL        REG8(MCHP_WDG_BASE + 0x4)
-#define MCHP_WDG_KICK       REG8(MCHP_WDG_BASE + 0x8)
-#define MCHP_WDG_CNT        REG16(MCHP_WDG_BASE + 0xc)
-
-
-/* VBAT */
-#define MCHP_VBAT_BASE               0x4000a400
-#define MCHP_VBAT_STS                REG32(MCHP_VBAT_BASE + 0x0)
-#define MCHP_VBAT_CE                 REG32(MCHP_VBAT_BASE + 0x8)
-#define MCHP_VBAT_SHDN_DIS           REG32(MCHP_VBAT_BASE + 0xC)
-#define MCHP_VBAT_MONOTONIC_CTR_LO   REG32(MCHP_VBAT_BASE + 0x20)
-#define MCHP_VBAT_MONOTONIC_CTR_HI   REG32(MCHP_VBAT_BASE + 0x24)
-/* read 32-bit word at 32-bit offset x where 0 <= x <= 31 */
-#define MCHP_VBAT_RAM(x)   REG32(MCHP_VBAT_BASE + 0x400 + ((x) * 4))
-#define MCHP_VBAT_VWIRE_BACKUP       30
-
-/* Bit definition for MCHP_VBAT_STS */
-#define MCHP_VBAT_STS_SOFTRESET		BIT(2)
-#define MCHP_VBAT_STS_RESETI		BIT(4)
-#define MCHP_VBAT_STS_WDT	        BIT(5)
-#define MCHP_VBAT_STS_SYSRESETREQ	BIT(6)
-#define MCHP_VBAT_STS_VBAT_RST		BIT(7)
-#define MCHP_VBAT_STS_ANY_RST		(0xF4u)
-
-/* Bit definitions for MCHP_VBAT_CE */
-#define MCHP_VBAT_CE_XOSEL_BITPOS    (3)
-#define MCHP_VBAT_CE_XOSEL_MASK      (1ul << 3)
-#define MCHP_VBAT_CE_XOSEL_PAR       (0ul << 3)
-#define MCHP_VBAT_CE_XOSEL_SE        (1ul << 3)
-
-#define MCHP_VBAT_CE_32K_SRC_BITPOS  (2)
-#define MCHP_VBAT_CE_32K_SRC_MASK    (1ul << 2)
-#define MCHP_VBAT_CE_32K_SRC_INT     (0ul << 2)
-#define MCHP_VBAT_CE_32K_SRC_CRYS    (1ul << 2)
-
-#define MCHP_VBAT_CE_EXT_32K_BITPOS  (1)
-#define MCHP_VBAT_CE_EXT_32K_MASK    (1ul << 1)
-#define MCHP_VBAT_CE_INT_32K         (0ul << 1)
-#define MCHP_VBAT_CE_EXT_32K         (1ul << 1)
-
-#define MCHP_VBAT_CE_32K_VTR_BITPOS  (0)
-#define MCHP_VBAT_CE_32K_VTR_MASK    (1ul << 0)
-#define MCHP_VBAT_CE_32K_VTR_ON      (0ul << 0)
-#define MCHP_VBAT_CE_32K_VTR_OFF     (1ul << 0)
-
-
-/*
- * Blinking-Breathing LED
- * 4 instances
- */
-#define MCHP_BBLED_BASE(x)	(0x4000B800 + (((x) & 0x03) << 8))
-#define MCHP_BBLEN_INSTANCES	4
-
-#define MCHP_BBLED_CONFIG(x)		REG32(MCHP_BBLED_BASE(x) + 0x00)
-#define MCHP_BBLED_LIMITS(x)		REG32(MCHP_BBLED_BASE(x) + 0x04)
-#define MCHP_BBLED_LIMIT_MIN(x)		REG8(MCHP_BBLED_BASE(x) + 0x04)
-#define MCHP_BBLED_LIMIT_MAX(x)		REG8(MCHP_BBLED_BASE(x) + 0x06)
-#define MCHP_BBLED_DELAY(x)		REG32(MCHP_BBLED_BASE(x) + 0x08)
-#define MCHP_BBLED_UPDATE_STEP(x)	REG32(MCHP_BBLED_BASE(x) + 0x0C)
-#define MCHP_BBLED_UPDATE_INTV(x)	REG32(MCHP_BBLED_BASE(x) + 0x10)
-#define MCHP_BBLED_OUTPUT_DLY(x)	REG8(MCHP_BBLED_BASE(x) + 0x14)
-
+#define MCHP_RTMR_COUNTER REG32(MCHP_RTMR_BASE + 0x00)
+#define MCHP_RTMR_PRELOAD REG32(MCHP_RTMR_BASE + 0x04)
+#define MCHP_RTMR_CONTROL REG8(MCHP_RTMR_BASE + 0x08)
+#define MCHP_RTMR_SOFT_INTR REG8(MCHP_RTMR_BASE + 0x0c)
+
+/* Watch dog timer */
+#define MCHP_WDG_LOAD REG16(MCHP_WDG_BASE + 0x0)
+#define MCHP_WDG_CTL REG16(MCHP_WDG_BASE + 0x4)
+#define MCHP_WDG_KICK REG8(MCHP_WDG_BASE + 0x8)
+#define MCHP_WDG_CNT REG16(MCHP_WDG_BASE + 0xc)
+#define MCHP_WDT_CTL_ENABLE BIT(0)
+#define MCHP_WDT_CTL_HTMR_STALL_EN BIT(2)
+#define MCHP_WDT_CTL_WKTMR_STALL_EN BIT(3)
+#define MCHP_WDT_CTL_JTAG_STALL_EN BIT(4)
+
+/* Blinking-Breathing LED */
+#define MCHP_BBLED_CONFIG(x) REG32(MCHP_BBLED_BASE(x) + 0x00)
+#define MCHP_BBLED_LIMITS(x) REG32(MCHP_BBLED_BASE(x) + 0x04)
+#define MCHP_BBLED_LIMIT_MIN(x) REG8(MCHP_BBLED_BASE(x) + 0x04)
+#define MCHP_BBLED_LIMIT_MAX(x) REG8(MCHP_BBLED_BASE(x) + 0x06)
+#define MCHP_BBLED_DELAY(x) REG32(MCHP_BBLED_BASE(x) + 0x08)
+#define MCHP_BBLED_UPDATE_STEP(x) REG32(MCHP_BBLED_BASE(x) + 0x0C)
+#define MCHP_BBLED_UPDATE_INTV(x) REG32(MCHP_BBLED_BASE(x) + 0x10)
+#define MCHP_BBLED_OUTPUT_DLY(x) REG8(MCHP_BBLED_BASE(x) + 0x14)
 /* BBLED Configuration Register */
-#define MCHP_BBLED_ASYMMETRIC		(1ul << 16)
-#define MCHP_BBLED_WDT_RELOAD_BITPOS	(8)
-#define MCHP_BBLED_WDT_RELOAD_MASK0	(0xFFul)
-#define MCHP_BBLED_WDT_RELOAD_MASK	(0xFFul << 8)
-#define MCHP_BBLED_RESET		(1ul << 7)
-#define MCHP_BBLED_EN_UPDATE		(1ul << 6)
-#define MCHP_BBLED_PWM_SIZE_BITPOS	(4)
-#define MCHP_BBLED_PWM_SIZE_MASK0	(0x03ul)
-#define MCHP_BBLED_PWM_SIZE_MASK	(0x03ul << 4)
-#define MCHP_BBLED_PWM_SIZE_6BIT	(0x02ul << 4)
-#define MCHP_BBLED_PWM_SIZE_7BIT	(0x01ul << 4)
-#define MCHP_BBLED_PWM_SIZE_8BIT	(0x00ul << 4)
-#define MCHP_BBLED_SYNC			(1ul << 3)
-#define MCHP_BBLED_CLK_48M		(1ul << 2)
-#define MCHP_BBLED_CLK_32K		(0ul << 2)
-#define MCHP_BBLED_CTRL_MASK		(0x03ul)
-#define MCHP_BBLED_CTRL_ALWAYS_ON	(0x03ul)
-#define MCHP_BBLED_CTRL_BLINK		(0x02ul)
-#define MCHP_BBLED_CTRL_BREATHE		(0x01ul)
-#define MCHP_BBLED_CTRL_OFF		(0x00ul)
-
+#define MCHP_BBLED_ASYMMETRIC BIT(16)
+#define MCHP_BBLED_WDT_RELOAD_BITPOS 8
+#define MCHP_BBLED_WDT_RELOAD_MASK0 0xFFul
+#define MCHP_BBLED_WDT_RELOAD_MASK (0xFFul << 8)
+#define MCHP_BBLED_RESET BIT(7)
+#define MCHP_BBLED_EN_UPDATE BIT(6)
+#define MCHP_BBLED_PWM_SIZE_BITPOS 4
+#define MCHP_BBLED_PWM_SIZE_MASK0 0x03ul
+#define MCHP_BBLED_PWM_SIZE_MASK (0x03ul << 4)
+#define MCHP_BBLED_PWM_SIZE_6BIT (0x02ul << 4)
+#define MCHP_BBLED_PWM_SIZE_7BIT (0x01ul << 4)
+#define MCHP_BBLED_PWM_SIZE_8BIT (0x00ul << 4)
+#define MCHP_BBLED_SYNC BIT(3)
+#define MCHP_BBLED_CLK_48M BIT(2)
+#define MCHP_BBLED_CLK_32K 0
+#define MCHP_BBLED_CTRL_MASK 0x03ul
+#define MCHP_BBLED_CTRL_ALWAYS_ON 0x03ul
+#define MCHP_BBLED_CTRL_BLINK 0x02ul
+#define MCHP_BBLED_CTRL_BREATHE 0x01ul
+#define MCHP_BBLED_CTRL_OFF 0x00ul
 /* BBLED Delay Register */
-#define MCHP_BBLED_DLY_MASK		(0x0FFFul)
-#define MCHP_BBLED_DLY_LO_BITPOS	(0)
-#define MCHP_BBLED_DLY_LO_MASK		(0x0FFFul << 0)
-#define MCHP_BBLED_DLY_HI_BITPOS	(12)
-#define MCHP_BBLED_DLY_HI_MASK		(0x0FFFul << 12)
-
+#define MCHP_BBLED_DLY_MASK 0x0FFFul
+#define MCHP_BBLED_DLY_LO_BITPOS 0
+#define MCHP_BBLED_DLY_LO_MASK 0x0FFFul
+#define MCHP_BBLED_DLY_HI_BITPOS 12
+#define MCHP_BBLED_DLY_HI_MASK (0x0FFFul << 12)
 /*
  * BBLED Update Step Register
  * 8 update fields numbered 0 - 7
  */
-#define MCHP_BBLED_UPD_STEP_MASK0	(0x0Ful)
-#define MCHP_BBLED_UPD_STEP_MASK(u)	(0x0Ful << (((u) & 0x07) + 4))
-
+#define MCHP_BBLED_UPD_STEP_MASK0 0x0Ful
+#define MCHP_BBLED_UPD_STEP_MASK(u) (0x0Ful << (((u)&0x07) + 4))
 /*
  * BBLED Update Interval Register
  * 8 interval fields numbered 0 - 7
  */
-#define MCHP_BBLED_UPD_INTV_MASK0	(0x0Ful)
-#define MCHP_BBLED_UPD_INTV_MASK(i)	(0x0Ful << (((i) & 0x07) + 4))
-
-
-/* Miscellaneous firmware control fields
- * scratch pad index cannot be more than 32 as
- * MCHP has 128 bytes = 32 indexes of scratchpad RAM
- */
-#define MCHP_IMAGETYPE_IDX     31
-
-
-/* LPC */
-#define MCHP_LPC_CFG_BASE     0x400f3300
-#define MCHP_LPC_ACT          REG8(MCHP_LPC_CFG_BASE + 0x30)
-#define MCHP_LPC_SIRQ(x)      REG8(MCHP_LPC_CFG_BASE + 0x40 + (x))
-#define MCHP_LPC_CFG_BAR      REG32(MCHP_LPC_CFG_BASE + 0x60)
-#define MCHP_LPC_MAILBOX_BAR  REG32(MCHP_LPC_CFG_BASE + 0x64)
-#define MCHP_LPC_8042_BAR     REG32(MCHP_LPC_CFG_BASE + 0x68)
-#define MCHP_LPC_ACPI_EC0_BAR REG32(MCHP_LPC_CFG_BASE + 0x6C)
-#define MCHP_LPC_ACPI_EC1_BAR REG32(MCHP_LPC_CFG_BASE + 0x70)
-#define MCHP_LPC_ACPI_EC2_BAR REG32(MCHP_LPC_CFG_BASE + 0x74)
-#define MCHP_LPC_ACPI_EC3_BAR REG32(MCHP_LPC_CFG_BASE + 0x78)
-#define MCHP_LPC_ACPI_EC4_BAR REG32(MCHP_LPC_CFG_BASE + 0x7C)
-#define MCHP_LPC_ACPI_PM1_BAR REG32(MCHP_LPC_CFG_BASE + 0x80)
-#define MCHP_LPC_PORT92_BAR   REG32(MCHP_LPC_CFG_BASE + 0x84)
-#define MCHP_LPC_UART0_BAR    REG32(MCHP_LPC_CFG_BASE + 0x88)
-#define MCHP_LPC_UART1_BAR    REG32(MCHP_LPC_CFG_BASE + 0x8C)
-#define MCHP_LPC_EMI0_BAR     REG32(MCHP_LPC_CFG_BASE + 0x90)
-#define MCHP_LPC_EMI1_BAR     REG32(MCHP_LPC_CFG_BASE + 0x94)
-#define MCHP_LPC_EMI2_BAR     REG32(MCHP_LPC_CFG_BASE + 0x98)
-#define MCHP_LPC_P80DBG0_BAR  REG32(MCHP_LPC_CFG_BASE + 0x9C)
-#define MCHP_LPC_P80DBG1_BAR  REG32(MCHP_LPC_CFG_BASE + 0xA0)
-#define MCHP_LPC_RTC_BAR      REG32(MCHP_LPC_CFG_BASE + 0xA4)
-
-#define MCHP_LPC_ACPI_EC_BAR(x) REG32(MCHP_LPC_CFG_BASE + 0x6C + ((x)<<2))
-
-/* LPC BAR bits */
-#define MCHP_LPC_IO_BAR_ADDR_BITPOS	(16)
-#define MCHP_LPC_IO_BAR_EN		(1ul << 15)
-
-/* LPC Generic Memory BAR's, 64-bit registers */
-#define MCHP_LPC_SRAM0_BAR_LO    REG32(MCHP_LPC_CFG_BASE + 0xB0)
-#define MCHP_LPC_SRAM0_BAR_HI    REG32(MCHP_LPC_CFG_BASE + 0xB4)
-#define MCHP_LPC_SRAM1_BAR_LO    REG32(MCHP_LPC_CFG_BASE + 0xB8)
-#define MCHP_LPC_SRAM1_BAR_HI    REG32(MCHP_LPC_CFG_BASE + 0xBC)
-
-/*
- * LPC Logical Device Memory BAR's, 48-bit registers
- * Use 16-bit aligned access
- */
-#define MCHP_LPC_MAILBOX_MEM_BAR_H0  REG32(MCHP_LPC_CFG_BASE + 0xC0)
-#define MCHP_LPC_MAILBOX_MEM_BAR_H1  REG32(MCHP_LPC_CFG_BASE + 0xC2)
-#define MCHP_LPC_MAILBOX_MEM_BAR_H2  REG32(MCHP_LPC_CFG_BASE + 0xC4)
-#define MCHP_LPC_ACPI_EC0_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xC6)
-#define MCHP_LPC_ACPI_EC0_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xC8)
-#define MCHP_LPC_ACPI_EC0_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xCA)
-#define MCHP_LPC_ACPI_EC1_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xCC)
-#define MCHP_LPC_ACPI_EC1_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xCE)
-#define MCHP_LPC_ACPI_EC1_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xD0)
-#define MCHP_LPC_ACPI_EC2_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xD2)
-#define MCHP_LPC_ACPI_EC2_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xD4)
-#define MCHP_LPC_ACPI_EC2_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xD6)
-#define MCHP_LPC_ACPI_EC3_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xD8)
-#define MCHP_LPC_ACPI_EC3_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xDA)
-#define MCHP_LPC_ACPI_EC3_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xDC)
-#define MCHP_LPC_ACPI_EC4_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xDE)
-#define MCHP_LPC_ACPI_EC4_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xE0)
-#define MCHP_LPC_ACPI_EC4_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xE2)
-#define MCHP_LPC_ACPI_EMI0_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xE4)
-#define MCHP_LPC_ACPI_EMI0_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xE6)
-#define MCHP_LPC_ACPI_EMI0_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xE8)
-#define MCHP_LPC_ACPI_EMI1_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xEA)
-#define MCHP_LPC_ACPI_EMI1_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xEC)
-#define MCHP_LPC_ACPI_EMI1_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xEE)
-#define MCHP_LPC_ACPI_EMI2_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xF0)
-#define MCHP_LPC_ACPI_EMI2_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xF2)
-#define MCHP_LPC_ACPI_EMI2_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xF4)
-
-
-#define MCHP_LPC_RT_BASE		0x400f3100
-#define MCHP_LPC_BUS_MONITOR		REG32(MCHP_LPC_RT_BASE + 0x4)
-#define MCHP_LPC_HOST_ERROR		REG32(MCHP_LPC_RT_BASE + 0x8)
-#define MCHP_LPC_EC_SERIRQ		REG32(MCHP_LPC_RT_BASE + 0xC)
-#define MCHP_LPC_EC_CLK_CTRL		REG32(MCHP_LPC_RT_BASE + 0x10)
-#define MCHP_LPC_BAR_INHIBIT		REG32(MCHP_LPC_RT_BASE + 0x20)
-#define MCHP_LPC_BAR_INIT		REG32(MCHP_LPC_RT_BASE + 0x30)
-#define MCHP_LPC_SRAM0_BAR		REG32(MCHP_LPC_RT_BASE + 0xf8)
-#define MCHP_LPC_SRAM1_BAR		REG32(MCHP_LPC_RT_BASE + 0xfc)
-
+#define MCHP_BBLED_UPD_INTV_MASK0 0x0Ful
+#define MCHP_BBLED_UPD_INTV_MASK(i) (0x0Ful << (((i)&0x07) + 4))
 
 /* EMI */
-#define MCHP_EMI_BASE(x)     (0x400F4100 + ((x) << 10))
-#define MCHP_EMI_H2E_MBX(x)  REG8(MCHP_EMI_BASE(x) + 0x0)
-#define MCHP_EMI_E2H_MBX(x)  REG8(MCHP_EMI_BASE(x) + 0x1)
-#define MCHP_EMI_MBA0(x)     REG32(MCHP_EMI_BASE(x) + 0x4)
-#define MCHP_EMI_MRL0(x)     REG16(MCHP_EMI_BASE(x) + 0x8)
-#define MCHP_EMI_MWL0(x)     REG16(MCHP_EMI_BASE(x) + 0xa)
-#define MCHP_EMI_MBA1(x)     REG32(MCHP_EMI_BASE(x) + 0xc)
-#define MCHP_EMI_MRL1(x)     REG16(MCHP_EMI_BASE(x) + 0x10)
-#define MCHP_EMI_MWL1(x)     REG16(MCHP_EMI_BASE(x) + 0x12)
-#define MCHP_EMI_ISR(x)      REG16(MCHP_EMI_BASE(x) + 0x14)
-#define MCHP_EMI_HCE(x)      REG16(MCHP_EMI_BASE(x) + 0x16)
-
-#define MCHP_EMI_RT_BASE(x)  (0x400F4000 + ((x) << 10))
-#define MCHP_EMI_ISR_B0(x)   REG8(MCHP_EMI_RT_BASE(x) + 0x8)
-#define MCHP_EMI_ISR_B1(x)   REG8(MCHP_EMI_RT_BASE(x) + 0x9)
-#define MCHP_EMI_IMR_B0(x)   REG8(MCHP_EMI_RT_BASE(x) + 0xa)
-#define MCHP_EMI_IMR_B1(x)   REG8(MCHP_EMI_RT_BASE(x) + 0xb)
-/*
- * EMI[0:2] on GIRQ15 bits[2:4]
- */
-#define MCHP_EMI_GIRQ	15
-#define MCHP_EMI_GIRQ_BIT(x)	(1ul << ((x)+2))
-
+#define MCHP_EMI_H2E_MBX(n) REG8(MCHP_EMI_BASE(n) + 0x0)
+#define MCHP_EMI_E2H_MBX(n) REG8(MCHP_EMI_BASE(n) + 0x1)
+#define MCHP_EMI_MBA0(n) REG32(MCHP_EMI_BASE(n) + 0x4)
+#define MCHP_EMI_MRL0(n) REG16(MCHP_EMI_BASE(n) + 0x8)
+#define MCHP_EMI_MWL0(n) REG16(MCHP_EMI_BASE(n) + 0xa)
+#define MCHP_EMI_MBA1(n) REG32(MCHP_EMI_BASE(n) + 0xc)
+#define MCHP_EMI_MRL1(n) REG16(MCHP_EMI_BASE(n) + 0x10)
+#define MCHP_EMI_MWL1(n) REG16(MCHP_EMI_BASE(n) + 0x12)
+#define MCHP_EMI_ISR(n) REG16(MCHP_EMI_BASE(n) + 0x14)
+#define MCHP_EMI_HCE(n) REG16(MCHP_EMI_BASE(n) + 0x16)
+#define MCHP_EMI_ISR_B0(n) REG8(MCHP_EMI_RT_BASE(n) + 0x8)
+#define MCHP_EMI_ISR_B1(n) REG8(MCHP_EMI_RT_BASE(n) + 0x9)
+#define MCHP_EMI_IMR_B0(n) REG8(MCHP_EMI_RT_BASE(n) + 0xa)
+#define MCHP_EMI_IMR_B1(n) REG8(MCHP_EMI_RT_BASE(n) + 0xb)
 
 /* Mailbox */
-#define MCHP_MBX_RT_BASE    0x400f0000
-#define MCHP_MBX_INDEX      REG8(MCHP_MBX_RT_BASE + 0x0)
-#define MCHP_MBX_DATA       REG8(MCHP_MBX_RT_BASE + 0x1)
-
-#define MCHP_MBX_BASE       0x400f0100
-#define MCHP_MBX_H2E_MBX    REG8(MCHP_MBX_BASE + 0x0)
-#define MCHP_MBX_E2H_MBX    REG8(MCHP_MBX_BASE + 0x4)
-#define MCHP_MBX_ISR        REG8(MCHP_MBX_BASE + 0x8)
-#define MCHP_MBX_IMR        REG8(MCHP_MBX_BASE + 0xc)
-#define MCHP_MBX_REG(x)     REG8(MCHP_MBX_BASE + 0x10 + (x))
-/*
- * Mailbox on GIRQ15 bit[20]
- */
-#define MCHP_MBX_GIRQ		15
-#define MCHP_MBX_GIRQ_BIT	(1ul << 20)
-
-
-/* Port80 Capture */
-#define MCHP_P80_BASE(x)	(0x400f8000 + ((x) << 10))
-#define MCHP_P80_HOST_DATA(x)	REG8(MCHP_P80_BASE(x))
-/* Data catpure with timestamp register */
-#define MCHP_P80_CAP(x)		REG32(MCHP_P80_BASE(x) + 0x100)
-#define MCHP_P80_CFG(x)		REG8(MCHP_P80_BASE(x) + 0x104)
-#define MCHP_P80_STS(x)		REG8(MCHP_P80_BASE(x) + 0x108)
-#define MCHP_P80_CNT(x)		REG32(MCHP_P80_BASE(x) + 0x10c)
-#define MCHP_P80_CNT_GET(x)	(REG32(MCHP_P80_BASE(x) + 0x10c) >> 8)
-#define MCHP_P80_CNT_SET(x, c)	(REG32(MCHP_P80_BASE(x) + 0x10c) = (c << 8))
-#define MCHP_P80_ACTIVATE(x)	REG8(MCHP_P80_BASE(x) + 0x330)
-/*
- * Port80 [0:1] GIRQ15 bits[22:23]
- */
-#define MCHP_P80_GIRQ		15
-#define MCHP_P80_GIRQ_BIT(x)	(1ul << ((x) + 22))
-
-/* Port80 Data register bits
- * bits[7:0] = data captured on Host write
- * bits[31:8] = optional time stamp
- */
-#define MCHP_P80_CAP_DATA_MASK	0xFFul
-#define MCHP_P80_CAP_TS_BITPOS	8
-#define MCHP_P80_CAP_TS_MASK0	0xfffffful
-#define MCHP_P80_CAP_TS_MASK	(\
-	(MCHP_P80_CAP_TS_MASK0) << (MCHP_P80_CAP_TS_BITPOS))
-
-/* Port80 Configuration register bits */
-#define MCHP_P80_FLUSH_FIFO_WO		(1u << 1)
-#define MCHP_P80_RESET_TIMESTAMP_WO	(1u << 2)
-#define MCHP_P80_TIMEBASE_BITPOS	3
-#define MCHP_P80_TIMEBASE_MASK0		0x03
-#define MCHP_P80_TIMEBASE_MASK		(\
-	(MCHP_P80_TIMEBASE_MASK0) << (MCHP_P80_TIMEBASE_BITPOS))
-#define MCHP_P80_TIMEBASE_750KHZ	(\
-	0x03 << (MCHP_P80_TIMEBASE_BITPOS))
-#define MCHP_P80_TIMEBASE_1500KHZ	(\
-	0x02 << (MCHP_P80_TIMEBASE_BITPOS))
-#define MCHP_P80_TIMEBASE_3MHZ		(\
-	0x01 << (MCHP_P80_TIMEBASE_BITPOS))
-#define MCHP_P80_TIMEBASE_6MHZ		(\
-	0x00 << (MCHP_P80_TIMEBASE_BITPOS))
-#define MCHP_P80_TIMER_ENABLE		(1u << 5)
-#define MCHP_P80_FIFO_THRHOLD_MASK	(3u << 6)
-#define MCHP_P80_FIFO_THRHOLD_1		(0u << 6)
-#define MCHP_P80_FIFO_THRHOLD_4		(1u << 6)
-#define MCHP_P80_FIFO_THRHOLD_8		(2u << 6)
-#define MCHP_P80_FIFO_THRHOLD_14	(3u << 6)
-#define MCHP_P80_FIFO_LEN		16
-
-/* Port80 Status register bits, read-only */
-#define MCHP_P80_STS_NOT_EMPTY		0x01
-#define MCHP_P80_STS_OVERRUN		0x02
-
-/* Port80 Count register bits */
-#define MCHP_P80_CNT_BITPOS		8
-#define MCHP_P80_CNT_MASK0		0xfffffful
-#define MCHP_P80_CNT_MASK	((MCHP_P80_CNT_MASK0) <<\
-	(MCHP_P80_CNT_BITPOS))
-
+#define MCHP_MBX_INDEX REG8(MCHP_MBX_RT_BASE + 0x0)
+#define MCHP_MBX_DATA REG8(MCHP_MBX_RT_BASE + 0x1)
+#define MCHP_MBX_H2E_MBX REG8(MCHP_MBX_BASE + 0x0)
+#define MCHP_MBX_E2H_MBX REG8(MCHP_MBX_BASE + 0x4)
+#define MCHP_MBX_ISR REG8(MCHP_MBX_BASE + 0x8)
+#define MCHP_MBX_IMR REG8(MCHP_MBX_BASE + 0xc)
+#define MCHP_MBX_REG(x) REG8(MCHP_MBX_BASE + 0x10 + (x))
 
 /* PWM */
-#define MCHP_PWM_ID_MAX		(12)
-#define MCHP_PWM_BASE(x)	(0x40005800 + ((x) << 4))
-#define MCHP_PWM_ON(x)		REG32(MCHP_PWM_BASE(x) + 0x00)
-#define MCHP_PWM_OFF(x)		REG32(MCHP_PWM_BASE(x) + 0x04)
-#define MCHP_PWM_CFG(x)		REG32(MCHP_PWM_BASE(x) + 0x08)
+#define MCHP_PWM_ON(x) REG32(MCHP_PWM_BASE(x) + 0x00)
+#define MCHP_PWM_OFF(x) REG32(MCHP_PWM_BASE(x) + 0x04)
+#define MCHP_PWM_CFG(x) REG32(MCHP_PWM_BASE(x) + 0x08)
 
 /* TACH */
-#define MCHP_TACH_BASE(x)	(0x40006000 + (x) << 4)
-#define MCHP_TACH_CTRL(x)	REG32(MCHP_TACH_BASE(x))
-#define MCHP_TACH_CTRL_LO(x)	REG16(MCHP_TACH_BASE(x) + 0x00)
-#define MCHP_TACH_CTRL_CNT(x)	REG16(MCHP_TACH_BASE(x) + 0x02)
-#define MCHP_TACH_STATUS(x)	REG8(MCHP_TACH_BASE(x) + 0x04)
-#define MCHP_TACH_LIMIT_HI(x)	REG16(MCHP_TACH_BASE(x) + 0x08)
-#define MCHP_TACH_LIMIT_LO(x)	REG16(MCHP_TACH_BASE(x) + 0x0C)
-/*
- * TACH [2:0] GIRQ17 bits[3:1]
- */
-#define MCHP_TACH_GIRQ		17
-#define MCHP_TACH_GIRQ_BIT(x)	(1ul << ((x) + 1))
-
+#define MCHP_TACH_CTRL(x) REG32(MCHP_TACH_BASE(x))
+#define MCHP_TACH_CTRL_LO(x) REG16(MCHP_TACH_BASE(x) + 0x00)
+#define MCHP_TACH_CTRL_CNT(x) REG16(MCHP_TACH_BASE(x) + 0x02)
+#define MCHP_TACH_STATUS(x) REG8(MCHP_TACH_BASE(x) + 0x04)
+#define MCHP_TACH_LIMIT_HI(x) REG16(MCHP_TACH_BASE(x) + 0x08)
+#define MCHP_TACH_LIMIT_LO(x) REG16(MCHP_TACH_BASE(x) + 0x0C)
 
 /* ACPI */
-#define MCHP_ACPI_EC_MAX		(5)
-#define MCHP_ACPI_EC_BASE(x)		(0x400f0800 + ((x) << 10))
-#define MCHP_ACPI_EC_EC2OS(x, y)	REG8(MCHP_ACPI_EC_BASE(x) +\
-	0x100 + (y))
-#define MCHP_ACPI_EC_STATUS(x)		REG8(MCHP_ACPI_EC_BASE(x) + 0x104)
-#define MCHP_ACPI_EC_BYTE_CTL(x)	REG8(MCHP_ACPI_EC_BASE(x) + 0x105)
-#define MCHP_ACPI_EC_OS2EC(x, y)	REG8(MCHP_ACPI_EC_BASE(x) +\
-	0x108 + (y))
-
-#define MCHP_ACPI_PM_RT_BASE     0x400f1c00
-#define MCHP_ACPI_PM1_STS1       REG8(MCHP_ACPI_PM_RT_BASE + 0x0)
-#define MCHP_ACPI_PM1_STS2       REG8(MCHP_ACPI_PM_RT_BASE + 0x1)
-#define MCHP_ACPI_PM1_EN1        REG8(MCHP_ACPI_PM_RT_BASE + 0x2)
-#define MCHP_ACPI_PM1_EN2        REG8(MCHP_ACPI_PM_RT_BASE + 0x3)
-#define MCHP_ACPI_PM1_CTL1       REG8(MCHP_ACPI_PM_RT_BASE + 0x4)
-#define MCHP_ACPI_PM1_CTL2       REG8(MCHP_ACPI_PM_RT_BASE + 0x5)
-#define MCHP_ACPI_PM2_CTL1       REG8(MCHP_ACPI_PM_RT_BASE + 0x6)
-#define MCHP_ACPI_PM2_CTL2       REG8(MCHP_ACPI_PM_RT_BASE + 0x7)
-#define MCHP_ACPI_PM_EC_BASE     0x400f1d00
-#define MCHP_ACPI_PM_STS         REG8(MCHP_ACPI_PM_EC_BASE + 0x10)
-/*
- * All ACPI EC controllers connected to GIRQ15
- * ACPI EC[0:4] IBF = GIRQ15 bits[5,7,9,11,13]
- * ACPI EC[0:4] OBE = GIRQ15 bits[6,8,10,12,14]
- * ACPI PM1_CTL = GIRQ15 bit[15]
- * ACPI PM1_EN  = GIRQ15 bit[16]
- * ACPI PM1_STS = GIRQ16 bit[17]
- */
-#define MCHP_ACPI_EC_GIRQ		15
-#define MCHP_ACPI_EC_IBF_GIRQ_BIT(x)	(1ul << (((x)<<1) + 5))
-#define MCHP_ACPI_EC_OBE_GIRQ_BIT(x)	(1ul << (((x)<<1) + 6))
-#define MCHP_ACPI_PM1_CTL_GIRQ_BIT	15
-#define MCHP_ACPI_PM1_EN_GIRQ_BIT	16
-#define MCHP_ACPI_PM1_STS_GIRQ_BIT	17
+#define MCHP_ACPI_EC_EC2OS(x, y) REG8(MCHP_ACPI_EC_BASE(x) + 0x100 + (y))
+#define MCHP_ACPI_EC_STATUS(x) REG8(MCHP_ACPI_EC_BASE(x) + 0x104)
+#define MCHP_ACPI_EC_BYTE_CTL(x) REG8(MCHP_ACPI_EC_BASE(x) + 0x105)
+#define MCHP_ACPI_EC_OS2EC(x, y) REG8(MCHP_ACPI_EC_BASE(x) + 0x108 + (y))
+#define MCHP_ACPI_PM1_STS1 REG8(MCHP_ACPI_PM_RT_BASE + 0x0)
+#define MCHP_ACPI_PM1_STS2 REG8(MCHP_ACPI_PM_RT_BASE + 0x1)
+#define MCHP_ACPI_PM1_EN1 REG8(MCHP_ACPI_PM_RT_BASE + 0x2)
+#define MCHP_ACPI_PM1_EN2 REG8(MCHP_ACPI_PM_RT_BASE + 0x3)
+#define MCHP_ACPI_PM1_CTL1 REG8(MCHP_ACPI_PM_RT_BASE + 0x4)
+#define MCHP_ACPI_PM1_CTL2 REG8(MCHP_ACPI_PM_RT_BASE + 0x5)
+#define MCHP_ACPI_PM2_CTL1 REG8(MCHP_ACPI_PM_RT_BASE + 0x6)
+#define MCHP_ACPI_PM2_CTL2 REG8(MCHP_ACPI_PM_RT_BASE + 0x7)
+#define MCHP_ACPI_PM_STS REG8(MCHP_ACPI_PM_EC_BASE + 0x10)
 
 /* 8042 */
-#define MCHP_8042_BASE      0x400f0400
-#define MCHP_8042_OBF_CLR   REG8(MCHP_8042_BASE + 0x0)
-#define MCHP_8042_H2E       REG8(MCHP_8042_BASE + 0x100)
-#define MCHP_8042_E2H       REG8(MCHP_8042_BASE + 0x100)
-#define MCHP_8042_STS       REG8(MCHP_8042_BASE + 0x104)
-#define MCHP_8042_KB_CTRL   REG8(MCHP_8042_BASE + 0x108)
-#define MCHP_8042_PCOBF     REG8(MCHP_8042_BASE + 0x114)
-#define MCHP_8042_ACT       REG8(MCHP_8042_BASE + 0x330)
-/*
- * 8042 [OBE:IBF] = GIRQ15 bits[18:19]
- */
-#define MCHP_8042_GIRQ		15
-#define MCHP_8042_OBE_GIRQ_BIT	(1ul << 18)
-#define MCHP_8042_IBF_GIRQ_BIT	(1ul << 19)
-
-/* FAN */
-#define MCHP_FAN_BASE(x)         (0x4000a000 + ((x) << 7))
-#define MCHP_FAN_SETTING(x)      REG8(MCHP_FAN_BASE(x) + 0x0)
-#define MCHP_FAN_PWM_DIVIDE(x)   REG8(MCHP_FAN_BASE(x) + 0x1)
-#define MCHP_FAN_CFG1(x)         REG8(MCHP_FAN_BASE(x) + 0x2)
-#define MCHP_FAN_CFG2(x)         REG8(MCHP_FAN_BASE(x) + 0x3)
-#define MCHP_FAN_GAIN(x)         REG8(MCHP_FAN_BASE(x) + 0x5)
-#define MCHP_FAN_SPIN_UP(x)      REG8(MCHP_FAN_BASE(x) + 0x6)
-#define MCHP_FAN_STEP(x)         REG8(MCHP_FAN_BASE(x) + 0x7)
-#define MCHP_FAN_MIN_DRV(x)      REG8(MCHP_FAN_BASE(x) + 0x8)
-#define MCHP_FAN_VALID_CNT(x)    REG8(MCHP_FAN_BASE(x) + 0x9)
-#define MCHP_FAN_DRV_FAIL(x)     REG16(MCHP_FAN_BASE(x) + 0xa)
-#define MCHP_FAN_TARGET(x)       REG16(MCHP_FAN_BASE(x) + 0xc)
-#define MCHP_FAN_READING(x)      REG16(MCHP_FAN_BASE(x) + 0xe)
-#define MCHP_FAN_BASE_FREQ(x)    REG8(MCHP_FAN_BASE(x) + 0x10)
-#define MCHP_FAN_STATUS(x)       REG8(MCHP_FAN_BASE(x) + 0x11)
-/*
- * FAN(RPM2PWM) all instances on GIRQ17
- * FAN[0:1] Fail  = GIRQ17 bits[4,6]
- * FAN[0:1] Stall = GIRQ17 bits[5,7]
- */
-#define MCHP_FAN_GIRQ			17
-#define MCHP_FAN_FAIL_GIRQ_BIT(x)	(1ul << (((x)<<1)+4))
-#define MCHP_FAN_STALL_GIRQ_BIT(x)	(1ul << (((x)<<1)+5))
-
-
-/* I2C */
-#define MCHP_I2C_CTRL0		(0)
-#define MCHP_I2C_CTRL1		(1)
-#define MCHP_I2C_CTRL2		(2)
-#define MCHP_I2C_CTRL3		(3)
-#define MCHP_I2C_CTRL_MAX	(4)
-
-#define MCHP_I2C_BASE(x)	(0x40004000 + ((x) << 10))
-#define MCHP_I2C0_BASE		0x40004000
-#define MCHP_I2C1_BASE		0x40004400
-#define MCHP_I2C2_BASE		0x40004800
-#define MCHP_I2C3_BASE		0x40004C00
-#define MCHP_I2C_BASESEP	0x00000400
-#define MCHP_I2C_ADDR(controller, offset) \
-	(offset + MCHP_I2C_BASE(controller))
-
-/*
- * MEC1701H 144-pin package has four I2C controller and eleven ports.
- * Any port can be mapped to any I2C controller.
- * This package does not implement pins for I2C01 (Port 1).
- *
- * I2C port values must be zero based consecutive whole numbers due to
- * port number used as an index for I2C mutex array, etc.
- *
- * Refer to chip i2c_port_to_controller function for mapping
- * of port to controller.
- *
- * Locking must occur by-controller (not by-port).
- */
-#define MCHP_I2C_PORT_MASK	0x07FDul
-
-enum MCHP_i2c_port {
-	MCHP_I2C_PORT0 = 0,
-	MCHP_I2C_PORT1,	/* port 1, do not use. pins not present */
-	MCHP_I2C_PORT2,
-	MCHP_I2C_PORT3,
-	MCHP_I2C_PORT4,
-	MCHP_I2C_PORT5,
-	MCHP_I2C_PORT6,
-	MCHP_I2C_PORT7,
-	MCHP_I2C_PORT8,
-	MCHP_I2C_PORT9,
-	MCHP_I2C_PORT10,
-
-	MCHP_I2C_PORT_COUNT,
-};
-
-#define MCHP_I2C_CTRL(ctrl)          REG8(MCHP_I2C_ADDR(ctrl, 0x0))
-#define MCHP_I2C_STATUS(ctrl)        REG8(MCHP_I2C_ADDR(ctrl, 0x0))
-#define MCHP_I2C_OWN_ADDR(ctrl)      REG16(MCHP_I2C_ADDR(ctrl, 0x4))
-#define MCHP_I2C_DATA(ctrl)          REG8(MCHP_I2C_ADDR(ctrl, 0x8))
-#define MCHP_I2C_MASTER_CMD(ctrl)    REG32(MCHP_I2C_ADDR(ctrl, 0xc))
-#define MCHP_I2C_SLAVE_CMD(ctrl)     REG32(MCHP_I2C_ADDR(ctrl, 0x10))
-#define MCHP_I2C_PEC(ctrl)           REG8(MCHP_I2C_ADDR(ctrl, 0x14))
-#define MCHP_I2C_DATA_TIM_2(ctrl)    REG8(MCHP_I2C_ADDR(ctrl, 0x18))
-#define MCHP_I2C_COMPLETE(ctrl)      REG32(MCHP_I2C_ADDR(ctrl, 0x20))
-#define MCHP_I2C_IDLE_SCALE(ctrl)    REG32(MCHP_I2C_ADDR(ctrl, 0x24))
-#define MCHP_I2C_CONFIG(ctrl)        REG32(MCHP_I2C_ADDR(ctrl, 0x28))
-#define MCHP_I2C_BUS_CLK(ctrl)       REG16(MCHP_I2C_ADDR(ctrl, 0x2c))
-#define MCHP_I2C_BLK_ID(ctrl)        REG8(MCHP_I2C_ADDR(ctrl, 0x30))
-#define MCHP_I2C_REV(ctrl)           REG8(MCHP_I2C_ADDR(ctrl, 0x34))
-#define MCHP_I2C_BB_CTRL(ctrl)       REG8(MCHP_I2C_ADDR(ctrl, 0x38))
-#define MCHP_I2C_DATA_TIM(ctrl)      REG32(MCHP_I2C_ADDR(ctrl, 0x40))
-#define MCHP_I2C_TOUT_SCALE(ctrl)    REG32(MCHP_I2C_ADDR(ctrl, 0x44))
-#define MCHP_I2C_SLAVE_TX_BUF(ctrl)  REG8(MCHP_I2C_ADDR(ctrl, 0x48))
-#define MCHP_I2C_SLAVE_RX_BUF(ctrl)  REG8(MCHP_I2C_ADDR(ctrl, 0x4c))
-#define MCHP_I2C_MASTER_TX_BUF(ctrl) REG8(MCHP_I2C_ADDR(ctrl, 0x50))
-#define MCHP_I2C_MASTER_RX_BUF(ctrl) REG8(MCHP_I2C_ADDR(ctrl, 0x54))
-#define MCHP_I2C_WAKE_STS(ctrl)      REG8(MCHP_I2C_ADDR(ctrl, 0x60))
-#define MCHP_I2C_WAKE_EN(ctrl)       REG8(MCHP_I2C_ADDR(ctrl, 0x64))
-/* All I2C controller connected to GIRQ13 */
-#define MCHP_I2C_GIRQ			13
-/* I2C[0:3] -> GIRQ13 bits[0:3] */
-#define MCHP_I2C_GIRQ_BIT(x)		(1ul << (x))
-
+#define MCHP_8042_OBF_CLR REG8(MCHP_8042_BASE + 0x0)
+#define MCHP_8042_H2E REG8(MCHP_8042_BASE + 0x100)
+#define MCHP_8042_E2H REG8(MCHP_8042_BASE + 0x100)
+#define MCHP_8042_STS REG8(MCHP_8042_BASE + 0x104)
+#define MCHP_8042_KB_CTRL REG8(MCHP_8042_BASE + 0x108)
+#define MCHP_8042_PCOBF REG8(MCHP_8042_BASE + 0x114)
+#define MCHP_8042_ACT REG8(MCHP_8042_BASE + 0x330)
+
+/* PROCHOT */
+#define MCHP_PCHOT_CUM_CNT REG32(MCHP_PROCHOT_BASE + 0x00)
+#define MCHP_PCHOT_DTY_CYC_CNT REG32(MCHP_PROCHOT_BASE + 0x04)
+#define MCHP_PCHOT_DTY_PRD_CNT REG32(MCHP_PROCHOT_BASE + 0x08)
+#define MCHP_PCHOT_STS_CTRL REG32(MCHP_PROCHOT_BASE + 0x0C)
+#define MCHP_PCHOT_ASERT_CNT REG32(MCHP_PROCHOT_BASE + 0x10)
+#define MCHP_PCHOT_ASERT_CNT_LMT REG32(MCHP_PROCHOT_BASE + 0x14)
+#define MCHP_PCHOT_TEST REG32(MCHP_PROCHOT_BASE + 0x18)
+
+/* I2C registers access given controller base address */
+#define MCHP_I2C_CTRL(addr) REG8(addr)
+#define MCHP_I2C_STATUS(addr) REG8(addr)
+#define MCHP_I2C_OWN_ADDR(addr) REG16(addr + 0x4)
+#define MCHP_I2C_DATA(addr) REG8(addr + 0x8)
+#define MCHP_I2C_MASTER_CMD(addr) REG32(addr + 0xc)
+#define MCHP_I2C_SLAVE_CMD(addr) REG32(addr + 0x10)
+#define MCHP_I2C_PEC(addr) REG8(addr + 0x14)
+#define MCHP_I2C_DATA_TIM_2(addr) REG8(addr + 0x18)
+#define MCHP_I2C_COMPLETE(addr) REG32(addr + 0x20)
+#define MCHP_I2C_IDLE_SCALE(addr) REG32(addr + 0x24)
+#define MCHP_I2C_CONFIG(addr) REG32(addr + 0x28)
+#define MCHP_I2C_BUS_CLK(addr) REG16(addr + 0x2c)
+#define MCHP_I2C_BLK_ID(addr) REG8(addr + 0x30)
+#define MCHP_I2C_REV(addr) REG8(addr + 0x34)
+#define MCHP_I2C_BB_CTRL(addr) REG8(addr + 0x38)
+#define MCHP_I2C_TST_DATA_TIM(addr) REG32(addr + 0x3c)
+#define MCHP_I2C_DATA_TIM(addr) REG32(addr + 0x40)
+#define MCHP_I2C_TOUT_SCALE(addr) REG32(addr + 0x44)
+#define MCHP_I2C_SLAVE_TX_BUF(addr) REG8(addr + 0x48)
+#define MCHP_I2C_SLAVE_RX_BUF(addr) REG8(addr + 0x4c)
+#define MCHP_I2C_MASTER_TX_BUF(addr) REG8(addr + 0x50)
+#define MCHP_I2C_MASTER_RX_BUF(addr) REG8(addr + 0x54)
+#define MCHP_I2C_TEST_1(addr) REG32(addr + 0x58)
+#define MCHP_I2C_TEST_2(addr) REG32(addr + 0x5c)
+#define MCHP_I2C_WAKE_STS(addr) REG8(addr + 0x60)
+#define MCHP_I2C_WAKE_EN(addr) REG8(addr + 0x64)
+#define MCHP_I2C_TEST_3(addr) REG32(addr + 0x68)
 
 /* Keyboard scan matrix */
-#define MCHP_KS_BASE		0x40009c00
-#define MCHP_KS_KSO_SEL		REG32(MCHP_KS_BASE + 0x4)
-#define MCHP_KS_KSI_INPUT	REG32(MCHP_KS_BASE + 0x8)
-#define MCHP_KS_KSI_STATUS	REG32(MCHP_KS_BASE + 0xc)
-#define MCHP_KS_KSI_INT_EN	REG32(MCHP_KS_BASE + 0x10)
-#define MCHP_KS_EXT_CTRL	REG32(MCHP_KS_BASE + 0x14)
-#define MCHP_KS_GIRQ		21
-#define MCHP_KS_GIRQ_BIT	(1ul << 25)
-
+#define MCHP_KS_KSO_SEL REG32(MCHP_KEYSCAN_BASE + 0x4)
+#define MCHP_KS_KSI_INPUT REG32(MCHP_KEYSCAN_BASE + 0x8)
+#define MCHP_KS_KSI_STATUS REG32(MCHP_KEYSCAN_BASE + 0xc)
+#define MCHP_KS_KSI_INT_EN REG32(MCHP_KEYSCAN_BASE + 0x10)
+#define MCHP_KS_EXT_CTRL REG32(MCHP_KEYSCAN_BASE + 0x14)
 
 /* ADC */
-#define MCHP_ADC_BASE       0x40007c00
-#define MCHP_ADC_CTRL       REG32(MCHP_ADC_BASE + 0x0)
-#define MCHP_ADC_DELAY      REG32(MCHP_ADC_BASE + 0x4)
-#define MCHP_ADC_STS        REG32(MCHP_ADC_BASE + 0x8)
-#define MCHP_ADC_SINGLE     REG32(MCHP_ADC_BASE + 0xc)
-#define MCHP_ADC_REPEAT     REG32(MCHP_ADC_BASE + 0x10)
-#define MCHP_ADC_READ(x)    REG32(MCHP_ADC_BASE + 0x14 + ((x) * 0x4))
-
-#define MCHP_ADC_GIRQ			17
-#define MCHP_ADC_GIRQ_SINGLE_BIT	(1ul << 8)
-#define MCHP_ADC_GIRQ_REPEAT_BIT	(1ul << 9)
-
+#define MCHP_ADC_CTRL REG32(MCHP_ADC_BASE + 0x0)
+#define MCHP_ADC_DELAY REG32(MCHP_ADC_BASE + 0x4)
+#define MCHP_ADC_STS REG32(MCHP_ADC_BASE + 0x8)
+#define MCHP_ADC_SINGLE REG32(MCHP_ADC_BASE + 0xc)
+#define MCHP_ADC_REPEAT REG32(MCHP_ADC_BASE + 0x10)
+#define MCHP_ADC_READ(x) REG32(MCHP_ADC_BASE + 0x14 + ((x)*0x4))
 
 /* Hibernation timer */
-#define MCHP_HTIMER_BASE(x)     (0x40009800 + ((x) << 5))
-#define MCHP_HTIMER_PRELOAD(x)  REG16(MCHP_HTIMER_BASE(x) + 0x0)
-#define MCHP_HTIMER_CONTROL(x)  REG16(MCHP_HTIMER_BASE(x) + 0x4)
-#define MCHP_HTIMER_COUNT(x)    REG16(MCHP_HTIMER_BASE(x) + 0x8)
-/* All Hibernation timers connected to GIRQ21 */
-#define MCHP_HTIMER_GIRQ	21
-/* HTIMER[0:1] -> GIRQ21 bits[1:2] */
-#define MCHP_HTIMER_GIRQ_BIT(x)	(1ul << ((x) + 1))
-
-
-/* General Purpose SPI (GP-SPI) */
-#define MCHP_SPI_BASE(port) (0x40009400 + ((port) << 7))
-#define MCHP_SPI_AR(port)   REG8(MCHP_SPI_BASE(port) + 0x00)
-#define MCHP_SPI_CR(port)   REG8(MCHP_SPI_BASE(port) + 0x04)
-#define MCHP_SPI_SR(port)   REG8(MCHP_SPI_BASE(port) + 0x08)
-#define MCHP_SPI_TD(port)   REG8(MCHP_SPI_BASE(port) + 0x0c)
-#define MCHP_SPI_RD(port)   REG8(MCHP_SPI_BASE(port) + 0x10)
-#define MCHP_SPI_CC(port)   REG8(MCHP_SPI_BASE(port) + 0x14)
-#define MCHP_SPI_CG(port)   REG8(MCHP_SPI_BASE(port) + 0x18)
-/* Addresses of TX/RX register used in tables */
-#define MCHP_SPI_TD_ADDR(ctrl)	(MCHP_SPI_BASE(ctrl) + 0x0c)
-#define MCHP_SPI_RD_ADDR(ctrl)	(MCHP_SPI_BASE(ctrl) + 0x10)
-/* All GP-SPI controllers connected to GIRQ18 */
-#define MCHP_SPI_GIRQ		18
-/*
- * SPI[0:1] TXBE -> GIRQ18 bits[2,4]
- * SPI[0:1] RXBF -> GIRQ18 bits[3,5]
- */
-#define MCHP_SPI_GIRQ_TXBE_BIT(x)	(1ul << (((x) << 1) + 2))
-#define MCHP_SPI_GIRQ_RXBF_BIT(x)	(1ul << (((x) << 1) + 3))
-
-#define MCHP_GPSPI0_ID	0
-#define MCHP_GPSPI1_ID	1
-
-#ifdef CHIP_FAMILY_MEC17XX
+#define MCHP_HTIMER_PRELOAD(x) REG16(MCHP_HTIMER_ADDR(x) + 0x0)
+#define MCHP_HTIMER_CONTROL(x) REG16(MCHP_HTIMER_ADDR(x) + 0x4)
+#define MCHP_HTIMER_COUNT(x) REG16(MCHP_HTIMER_ADDR(x) + 0x8)
+
+/* Week timer and BGPO control */
+#define MCHP_WKTIMER_CTRL REG32(MCHP_WKTIMER_BASE + 0)
+#define MCHP_WKTIMER_ALARM_CNT REG32(MCHP_WKTIMER_BASE + 0x04)
+#define MCHP_WKTIMER_COMPARE REG32(MCHP_WKTIMER_BASE + 0x08)
+#define MCHP_WKTIMER_CLK_DIV REG32(MCHP_WKTIMER_BASE + 0x0c)
+#define MCHP_WKTIMER_SUBSEC_ISEL REG32(MCHP_WKTIMER_BASE + 0x10)
+#define MCHP_WKTIMER_SUBWK_CTRL REG32(MCHP_WKTIMER_BASE + 0x14)
+#define MCHP_WKTIMER_SUBWK_ALARM REG32(MCHP_WKTIMER_BASE + 0x18)
+#define MCHP_WKTIMER_BGPO_DATA REG32(MCHP_WKTIMER_BASE + 0x1c)
+#define MCHP_WKTIMER_BGPO_POWER REG32(MCHP_WKTIMER_BASE + 0x20)
+#define MCHP_WKTIMER_BGPO_RESET REG32(MCHP_WKTIMER_BASE + 0x24)
 
 /* Quad Master SPI (QMSPI) */
-#define MCHP_QMSPI0_BASE		0x40005400
-#define MCHP_QMSPI0_MODE		REG32(MCHP_QMSPI0_BASE + 0x00)
-#define MCHP_QMSPI0_MODE_ACT_SRST	REG8(MCHP_QMSPI0_BASE + 0x00)
-#define MCHP_QMSPI0_MODE_SPI_MODE	REG8(MCHP_QMSPI0_BASE + 0x01)
-#define MCHP_QMSPI0_MODE_FDIV		REG8(MCHP_QMSPI0_BASE + 0x02)
-#define MCHP_QMSPI0_CTRL		REG32(MCHP_QMSPI0_BASE + 0x04)
-#define MCHP_QMSPI0_EXE			REG8(MCHP_QMSPI0_BASE + 0x08)
-#define MCHP_QMSPI0_IFCTRL		REG8(MCHP_QMSPI0_BASE + 0x0C)
-#define MCHP_QMSPI0_STS			REG32(MCHP_QMSPI0_BASE + 0x10)
-#define MCHP_QMSPI0_BUFCNT_STS		REG32(MCHP_QMSPI0_BASE + 0x14)
-#define MCHP_QMSPI0_IEN			REG32(MCHP_QMSPI0_BASE + 0x18)
-#define MCHP_QMSPI0_BUFCNT_TRIG		REG32(MCHP_QMSPI0_BASE + 0x1C)
-#define MCHP_QMSPI0_TX_FIFO_ADDR	(MCHP_QMSPI0_BASE + 0x20)
-#define MCHP_QMSPI0_TX_FIFO8		REG8(MCHP_QMSPI0_BASE + 0x20)
-#define MCHP_QMSPI0_TX_FIFO16		REG16(MCHP_QMSPI0_BASE + 0x20)
-#define MCHP_QMSPI0_TX_FIFO32		REG32(MCHP_QMSPI0_BASE + 0x20)
-#define MCHP_QMSPI0_RX_FIFO_ADDR	(MCHP_QMSPI0_BASE + 0x24)
-#define MCHP_QMSPI0_RX_FIFO8		REG8(MCHP_QMSPI0_BASE + 0x24)
-#define MCHP_QMSPI0_RX_FIFO16		REG16(MCHP_QMSPI0_BASE + 0x24)
-#define MCHP_QMSPI0_RX_FIFO32		REG32(MCHP_QMSPI0_BASE + 0x24)
-#define MCHP_QMSPI0_DESCR(x)		REG32(MCHP_QMSPI0_BASE +\
-	0x30 + ((x)<<2))
-#define MCHP_QMSPI_GIRQ			18
-#define MCHP_QMSPI_GIRQ_BIT		(1ul << 1)
-
-#define MCHP_QMSPI_MAX_DESCR		5
-
+#define MCHP_QMSPI0_MODE REG32(MCHP_QMSPI0_BASE + 0x00)
+#define MCHP_QMSPI0_MODE_ACT_SRST REG8(MCHP_QMSPI0_BASE + 0x00)
+#define MCHP_QMSPI0_MODE_SPI_MODE REG8(MCHP_QMSPI0_BASE + 0x01)
+#define MCHP_QMSPI0_MODE_FDIV REG8(MCHP_QMSPI0_BASE + 0x02)
+#define MCHP_QMSPI0_CTRL REG32(MCHP_QMSPI0_BASE + 0x04)
+#define MCHP_QMSPI0_EXE REG8(MCHP_QMSPI0_BASE + 0x08)
+#define MCHP_QMSPI0_IFCTRL REG8(MCHP_QMSPI0_BASE + 0x0C)
+#define MCHP_QMSPI0_STS REG32(MCHP_QMSPI0_BASE + 0x10)
+#define MCHP_QMSPI0_BUFCNT_STS REG32(MCHP_QMSPI0_BASE + 0x14)
+#define MCHP_QMSPI0_IEN REG32(MCHP_QMSPI0_BASE + 0x18)
+#define MCHP_QMSPI0_BUFCNT_TRIG REG32(MCHP_QMSPI0_BASE + 0x1C)
+#define MCHP_QMSPI0_TX_FIFO_ADDR (MCHP_QMSPI0_BASE + 0x20)
+#define MCHP_QMSPI0_TX_FIFO8 REG8(MCHP_QMSPI0_BASE + 0x20)
+#define MCHP_QMSPI0_TX_FIFO16 REG16(MCHP_QMSPI0_BASE + 0x20)
+#define MCHP_QMSPI0_TX_FIFO32 REG32(MCHP_QMSPI0_BASE + 0x20)
+#define MCHP_QMSPI0_RX_FIFO_ADDR (MCHP_QMSPI0_BASE + 0x24)
+#define MCHP_QMSPI0_RX_FIFO8 REG8(MCHP_QMSPI0_BASE + 0x24)
+#define MCHP_QMSPI0_RX_FIFO16 REG16(MCHP_QMSPI0_BASE + 0x24)
+#define MCHP_QMSPI0_RX_FIFO32 REG32(MCHP_QMSPI0_BASE + 0x24)
+#define MCHP_QMSPI0_DESCR(x) REG32(MCHP_QMSPI0_BASE + 0x30 + ((x)*4))
 /* Bits in MCHP_QMSPI0_MODE */
-#define MCHP_QMSPI_M_ACTIVATE        (1ul << 0)
-#define MCHP_QMSPI_M_SOFT_RESET      (1ul << 1)
-#define MCHP_QMSPI_M_SPI_MODE_MASK   (0x7ul << 8)
-#define MCHP_QMSPI_M_SPI_MODE0       (0x0ul << 8)
-#define MCHP_QMSPI_M_SPI_MODE3       (0x3ul << 8)
-#define MCHP_QMSPI_M_SPI_MODE0_48M   (0x4ul << 8)
-#define MCHP_QMSPI_M_SPI_MODE3_48M   (0x7ul << 8)
+#define MCHP_QMSPI_M_ACTIVATE BIT(0)
+#define MCHP_QMSPI_M_SOFT_RESET BIT(1)
+#define MCHP_QMSPI_M_SPI_MODE_MASK (0x7ul << 8)
+#define MCHP_QMSPI_M_SPI_MODE0 (0x0ul << 8)
+#define MCHP_QMSPI_M_SPI_MODE3 (0x3ul << 8)
+#define MCHP_QMSPI_M_SPI_MODE0_48M (0x4ul << 8)
+#define MCHP_QMSPI_M_SPI_MODE3_48M (0x7ul << 8)
 /*
  * clock divider is 8-bit field in bits[23:16]
  * [1, 255] -> 48MHz / [1, 255], 0 -> 48MHz / 256
  */
-#define MCHP_QMSPI_M_CLKDIV_BITPOS	16
-#define MCHP_QMSPI_M_CLKDIV_48M		(1ul << 16)
-#define MCHP_QMSPI_M_CLKDIV_24M		(2ul << 16)
-#define MCHP_QMSPI_M_CLKDIV_16M		(3ul << 16)
-#define MCHP_QMSPI_M_CLKDIV_12M		(4ul << 16)
-#define MCHP_QMSPI_M_CLKDIV_8M		(6ul << 16)
-#define MCHP_QMSPI_M_CLKDIV_6M		(8ul << 16)
-#define MCHP_QMSPI_M_CLKDIV_1M		(48ul << 16)
-#define MCHP_QMSPI_M_CLKDIV_188K	(0x100ul << 16)
-
+#define MCHP_QMSPI_M_CLKDIV_BITPOS 16
+#define MCHP_QMSPI_M_CLKDIV_48M (1ul << 16)
+#define MCHP_QMSPI_M_CLKDIV_24M (2ul << 16)
+#define MCHP_QMSPI_M_CLKDIV_16M (3ul << 16)
+#define MCHP_QMSPI_M_CLKDIV_12M (4ul << 16)
+#define MCHP_QMSPI_M_CLKDIV_8M (6ul << 16)
+#define MCHP_QMSPI_M_CLKDIV_6M (8ul << 16)
+#define MCHP_QMSPI_M_CLKDIV_1M (48ul << 16)
+#define MCHP_QMSPI_M_CLKDIV_188K (0x100ul << 16)
 /* Bits in MCHP_QMSPI0_CTRL and MCHP_QMSPI_DESCR(x) */
-#define MCHP_QMSPI_C_1X			(0ul << 0) /* Full Duplex */
-#define MCHP_QMSPI_C_2X			(1ul << 0) /* Dual IO */
-#define MCHP_QMSPI_C_4X			(2ul << 0) /* Quad IO */
-#define MCHP_QMSPI_C_TX_DIS		(0ul << 2)
-#define MCHP_QMSPI_C_TX_DATA		(1ul << 2)
-#define MCHP_QMSPI_C_TX_ZEROS		(2ul << 2)
-#define MCHP_QMSPI_C_TX_ONES		(3ul << 2)
-#define MCHP_QMSPI_C_TX_DMA_DIS		(0ul << 4)
-#define MCHP_QMSPI_C_TX_DMA_1B		(1ul << 4)
-#define MCHP_QMSPI_C_TX_DMA_2B		(2ul << 4)
-#define MCHP_QMSPI_C_TX_DMA_4B		(3ul << 4)
-#define MCHP_QMSPI_C_TX_DMA_MASK	(3ul << 4)
-#define MCHP_QMSPI_C_RX_DIS		(0ul << 6)
-#define MCHP_QMSPI_C_RX_EN		(1ul << 6)
-#define MCHP_QMSPI_C_RX_DMA_DIS		(0ul << 7)
-#define MCHP_QMSPI_C_RX_DMA_1B		(1ul << 7)
-#define MCHP_QMSPI_C_RX_DMA_2B		(2ul << 7)
-#define MCHP_QMSPI_C_RX_DMA_4B		(3ul << 7)
-#define MCHP_QMSPI_C_RX_DMA_MASK	(3ul << 7)
-#define MCHP_QMSPI_C_NO_CLOSE		(0ul << 9)
-#define MCHP_QMSPI_C_CLOSE		(1ul << 9)
-#define MCHP_QMSPI_C_XFRU_BITS		(0ul << 10)
-#define MCHP_QMSPI_C_XFRU_1B		(1ul << 10)
-#define MCHP_QMSPI_C_XFRU_4B		(2ul << 10)
-#define MCHP_QMSPI_C_XFRU_16B		(3ul << 10)
-#define MCHP_QMSPI_C_XFRU_MASK		(3ul << 10)
+#define MCHP_QMSPI_C_1X (0ul << 0) /* Full Duplex */
+#define MCHP_QMSPI_C_2X (1ul << 0) /* Dual IO */
+#define MCHP_QMSPI_C_4X (2ul << 0) /* Quad IO */
+#define MCHP_QMSPI_C_TX_DIS (0ul << 2)
+#define MCHP_QMSPI_C_TX_DATA (1ul << 2)
+#define MCHP_QMSPI_C_TX_ZEROS (2ul << 2)
+#define MCHP_QMSPI_C_TX_ONES (3ul << 2)
+#define MCHP_QMSPI_C_TX_DMA_DIS (0ul << 4)
+#define MCHP_QMSPI_C_TX_DMA_1B (1ul << 4)
+#define MCHP_QMSPI_C_TX_DMA_2B (2ul << 4)
+#define MCHP_QMSPI_C_TX_DMA_4B (3ul << 4)
+#define MCHP_QMSPI_C_TX_DMA_MASK (3ul << 4)
+#define MCHP_QMSPI_C_RX_DIS 0
+#define MCHP_QMSPI_C_RX_EN BIT(6)
+#define MCHP_QMSPI_C_RX_DMA_DIS (0ul << 7)
+#define MCHP_QMSPI_C_RX_DMA_1B (1ul << 7)
+#define MCHP_QMSPI_C_RX_DMA_2B (2ul << 7)
+#define MCHP_QMSPI_C_RX_DMA_4B (3ul << 7)
+#define MCHP_QMSPI_C_RX_DMA_MASK (3ul << 7)
+#define MCHP_QMSPI_C_NO_CLOSE 0
+#define MCHP_QMSPI_C_CLOSE BIT(9)
+#define MCHP_QMSPI_C_XFRU_BITS (0ul << 10)
+#define MCHP_QMSPI_C_XFRU_1B (1ul << 10)
+#define MCHP_QMSPI_C_XFRU_4B (2ul << 10)
+#define MCHP_QMSPI_C_XFRU_16B (3ul << 10)
+#define MCHP_QMSPI_C_XFRU_MASK (3ul << 10)
 /* Control */
-#define MCHP_QMSPI_C_START_DESCR_BITPOS (12)
-#define MCHP_QMSPI_C_START_DESCR_MASK	(0xFul << 12)
-#define MCHP_QMSPI_C_DESCR_MODE_EN	(1ul << 16)
+#define MCHP_QMSPI_C_START_DESCR_BITPOS 12
+#define MCHP_QMSPI_C_START_DESCR_MASK (0xFul << 12)
+#define MCHP_QMSPI_C_DESCR_MODE_EN BIT(16)
 /* Descriptors, indicates the current descriptor is the last */
-#define MCHP_QMSPI_C_NEXT_DESCR_BITPOS	12
-#define MCHP_QMSPI_C_NEXT_DESCR_MASK0	0xFul
-#define MCHP_QMSPI_C_NEXT_DESCR_MASK \
-	((MCHP_QMSPI_C_NEXT_DESCR_MASK0) << 12)
-#define MCHP_QMSPI_C_NXTD(n)		(n << 12)
-#define MCHP_QMSPI_C_NEXTD0		(0ul << 12)
-#define MCHP_QMSPI_C_NEXTD1		(1ul << 12)
-#define MCHP_QMSPI_C_NEXTD2		(2ul << 12)
-#define MCHP_QMSPI_C_NEXTD3		(3ul << 12)
-#define MCHP_QMSPI_C_NEXTD4		(4ul << 12)
-#define MCHP_QMSPI_C_DESCR_LAST		(1ul << 16)
+#define MCHP_QMSPI_C_NEXT_DESCR_BITPOS 12
+#define MCHP_QMSPI_C_NEXT_DESCR_MASK0 0xFul
+#define MCHP_QMSPI_C_NEXT_DESCR_MASK ((MCHP_QMSPI_C_NEXT_DESCR_MASK0) << 12)
+#define MCHP_QMSPI_C_NXTD(n) ((n) << 12)
+#define MCHP_QMSPI_C_DESCR_LAST BIT(16)
 /*
  * Total transfer length is the count in this field
  * scaled by units in MCHP_QMSPI_CTRL_XFRU_xxxx
  */
-#define MCHP_QMSPI_C_NUM_UNITS_BITPOS	(17)
-#define MCHP_QMSPI_C_MAX_UNITS		(0x7ffful)
-#define MCHP_QMSPI_C_NUM_UNITS_MASK0	(0x7ffful)
-#define MCHP_QMSPI_C_NUM_UNITS_MASK \
-	((MCHP_QMSPI_C_NUM_UNITS_MASK0) << 17)
-
+#define MCHP_QMSPI_C_NUM_UNITS_BITPOS 17
+#define MCHP_QMSPI_C_MAX_UNITS 0x7ffful
+#define MCHP_QMSPI_C_NUM_UNITS_MASK0 0x7ffful
+#define MCHP_QMSPI_C_NUM_UNITS_MASK ((MCHP_QMSPI_C_NUM_UNITS_MASK0) << 17)
 /* Bits in MCHP_QMSPI0_EXE */
-#define MCHP_QMSPI_EXE_START		BIT(0)
-#define MCHP_QMSPI_EXE_STOP		BIT(1)
-#define MCHP_QMSPI_EXE_CLR_FIFOS	BIT(2)
-
+#define MCHP_QMSPI_EXE_START BIT(0)
+#define MCHP_QMSPI_EXE_STOP BIT(1)
+#define MCHP_QMSPI_EXE_CLR_FIFOS BIT(2)
 /* MCHP QMSPI FIFO Sizes */
-#define MCHP_QMSPI_TX_FIFO_LEN	8
-#define MCHP_QMSPI_RX_FIFO_LEN	8
-
+#define MCHP_QMSPI_TX_FIFO_LEN 8
+#define MCHP_QMSPI_RX_FIFO_LEN 8
 /* Bits in MCHP_QMSPI0_STS and MCHP_QMSPI0_IEN */
-#define MCHP_QMSPI_STS_DONE		(1ul << 0)
-#define MCHP_QMSPI_STS_DMA_DONE		(1ul << 1)
-#define MCHP_QMSPI_STS_TX_BUFF_ERR	(1ul << 2)
-#define MCHP_QMSPI_STS_RX_BUFF_ERR	(1ul << 3)
-#define MCHP_QMSPI_STS_PROG_ERR		(1ul << 4)
-#define MCHP_QMSPI_STS_TX_BUFF_FULL	(1ul << 8)
-#define MCHP_QMSPI_STS_TX_BUFF_EMPTY	(1ul << 9)
-#define MCHP_QMSPI_STS_TX_BUFF_REQ	(1ul << 10)
-#define MCHP_QMSPI_STS_TX_BUFF_STALL	(1ul << 11) /* status only */
-#define MCHP_QMSPI_STS_RX_BUFF_FULL	(1ul << 12)
-#define MCHP_QMSPI_STS_RX_BUFF_EMPTY	(1ul << 13)
-#define MCHP_QMSPI_STS_RX_BUFF_REQ	(1ul << 14)
-#define MCHP_QMSPI_STS_RX_BUFF_STALL	(1ul << 15) /* status only */
-#define MCHP_QMSPI_STS_ACTIVE		(1ul << 16) /* status only */
-
+#define MCHP_QMSPI_STS_DONE BIT(0)
+#define MCHP_QMSPI_STS_DMA_DONE BIT(1)
+#define MCHP_QMSPI_STS_TX_BUFF_ERR BIT(2)
+#define MCHP_QMSPI_STS_RX_BUFF_ERR BIT(3)
+#define MCHP_QMSPI_STS_PROG_ERR BIT(4)
+#define MCHP_QMSPI_STS_TX_BUFF_FULL BIT(8)
+#define MCHP_QMSPI_STS_TX_BUFF_EMPTY BIT(9)
+#define MCHP_QMSPI_STS_TX_BUFF_REQ BIT(10)
+#define MCHP_QMSPI_STS_TX_BUFF_STALL BIT(11) /* status only */
+#define MCHP_QMSPI_STS_RX_BUFF_FULL BIT(12)
+#define MCHP_QMSPI_STS_RX_BUFF_EMPTY BIT(13)
+#define MCHP_QMSPI_STS_RX_BUFF_REQ BIT(14)
+#define MCHP_QMSPI_STS_RX_BUFF_STALL BIT(15) /* status only */
+#define MCHP_QMSPI_STS_ACTIVE BIT(16) /* status only */
 /* Bits in MCHP_QMSPI0_BUFCNT (read-only) */
-#define MCHP_QMSPI_BUFCNT_TX_BITPOS	(0)
-#define MCHP_QMSPI_BUFCNT_TX_MASK	(0xFFFFul)
-#define MCHP_QMSPI_BUFCNT_RX_BITPOS	(16)
-#define MCHP_QMSPI_BUFCNT_RX_MASK	(0xFFFFul << 16)
-
-#define MCHP_QMSPI0_ID	0
-
-#endif /* #ifdef CHIP_FAMILY_MEC17XX */
+#define MCHP_QMSPI_BUFCNT_TX_BITPOS 0
+#define MCHP_QMSPI_BUFCNT_TX_MASK 0xFFFFul
+#define MCHP_QMSPI_BUFCNT_RX_BITPOS 16
+#define MCHP_QMSPI_BUFCNT_RX_MASK (0xFFFFul << 16)
+#define MCHP_QMSPI0_ID 0
 
 /* eSPI */
-
-/* eSPI IO Component Base Address */
-#define MCHP_ESPI_IO_BASE		0x400f3400
-
+/* eSPI IO Component */
 /* Peripheral Channel Registers */
-#define MCHP_ESPI_PC_STATUS		REG32(MCHP_ESPI_IO_BASE + 0x114)
-#define MCHP_ESPI_PC_IEN		REG32(MCHP_ESPI_IO_BASE + 0x118)
-#define MCHP_ESPI_PC_BAR_INHIBIT_LO	REG32(MCHP_ESPI_IO_BASE + 0x120)
-#define MCHP_ESPI_PC_BAR_INHIBIT_HI	REG32(MCHP_ESPI_IO_BASE + 0x124)
-#define MCHP_ESPI_PC_BAR_INIT_LD_0C	REG16(MCHP_ESPI_IO_BASE + 0x128)
-#define MCHP_ESPI_PC_EC_IRQ		REG8(MCHP_ESPI_IO_BASE + 0x12C)
-
+#define MCHP_ESPI_PC_STATUS REG32(MCHP_ESPI_IO_BASE + 0x114)
+#define MCHP_ESPI_PC_IEN REG32(MCHP_ESPI_IO_BASE + 0x118)
+#define MCHP_ESPI_PC_BAR_INHIBIT_LO REG32(MCHP_ESPI_IO_BASE + 0x120)
+#define MCHP_ESPI_PC_BAR_INHIBIT_HI REG32(MCHP_ESPI_IO_BASE + 0x124)
+#define MCHP_ESPI_PC_BAR_INIT_LD_0C REG16(MCHP_ESPI_IO_BASE + 0x128)
+#define MCHP_ESPI_PC_EC_IRQ REG8(MCHP_ESPI_IO_BASE + 0x12C)
 /* LTR Registers */
-#define MCHP_ESPI_IO_LTR_STATUS		REG16(MCHP_ESPI_IO_BASE + 0x220)
-#define MCHP_ESPI_IO_LTR_IEN		REG8(MCHP_ESPI_IO_BASE + 0x224)
-#define MCHP_ESPI_IO_LTR_CTRL		REG16(MCHP_ESPI_IO_BASE + 0x228)
-#define MCHP_ESPI_IO_LTR_MSG		REG16(MCHP_ESPI_IO_BASE + 0x22C)
-
+#define MCHP_ESPI_IO_LTR_STATUS REG16(MCHP_ESPI_IO_BASE + 0x220)
+#define MCHP_ESPI_IO_LTR_IEN REG8(MCHP_ESPI_IO_BASE + 0x224)
+#define MCHP_ESPI_IO_LTR_CTRL REG16(MCHP_ESPI_IO_BASE + 0x228)
+#define MCHP_ESPI_IO_LTR_MSG REG16(MCHP_ESPI_IO_BASE + 0x22C)
 /* OOB Channel Registers */
-#define MCHP_ESPI_OOB_RX_ADDR_LO	REG32(MCHP_ESPI_IO_BASE + 0x240)
-#define MCHP_ESPI_OOB_RX_ADDR_HI	REG32(MCHP_ESPI_IO_BASE + 0x244)
-#define MCHP_ESPI_OOB_TX_ADDR_LO	REG32(MCHP_ESPI_IO_BASE + 0x248)
-#define MCHP_ESPI_OOB_TX_ADDR_HI	REG32(MCHP_ESPI_IO_BASE + 0x24C)
-#define MCHP_ESPI_OOB_RX_LEN		REG32(MCHP_ESPI_IO_BASE + 0x250)
-#define MCHP_ESPI_OOB_TX_LEN		REG32(MCHP_ESPI_IO_BASE + 0x254)
-#define MCHP_ESPI_OOB_RX_CTL		REG32(MCHP_ESPI_IO_BASE + 0x258)
-#define MCHP_ESPI_OOB_RX_IEN		REG8(MCHP_ESPI_IO_BASE + 0x25C)
-#define MCHP_ESPI_OOB_RX_STATUS		REG32(MCHP_ESPI_IO_BASE + 0x260)
-#define MCHP_ESPI_OOB_TX_CTL		REG32(MCHP_ESPI_IO_BASE + 0x264)
-#define MCHP_ESPI_OOB_TX_IEN		REG8(MCHP_ESPI_IO_BASE + 0x268)
-#define MCHP_ESPI_OOB_TX_STATUS		REG32(MCHP_ESPI_IO_BASE + 0x26C)
-
+#define MCHP_ESPI_OOB_RX_ADDR_LO REG32(MCHP_ESPI_IO_BASE + 0x240)
+#define MCHP_ESPI_OOB_RX_ADDR_HI REG32(MCHP_ESPI_IO_BASE + 0x244)
+#define MCHP_ESPI_OOB_TX_ADDR_LO REG32(MCHP_ESPI_IO_BASE + 0x248)
+#define MCHP_ESPI_OOB_TX_ADDR_HI REG32(MCHP_ESPI_IO_BASE + 0x24C)
+#define MCHP_ESPI_OOB_RX_LEN REG32(MCHP_ESPI_IO_BASE + 0x250)
+#define MCHP_ESPI_OOB_TX_LEN REG32(MCHP_ESPI_IO_BASE + 0x254)
+#define MCHP_ESPI_OOB_RX_CTL REG32(MCHP_ESPI_IO_BASE + 0x258)
+#define MCHP_ESPI_OOB_RX_IEN REG8(MCHP_ESPI_IO_BASE + 0x25C)
+#define MCHP_ESPI_OOB_RX_STATUS REG32(MCHP_ESPI_IO_BASE + 0x260)
+#define MCHP_ESPI_OOB_TX_CTL REG32(MCHP_ESPI_IO_BASE + 0x264)
+#define MCHP_ESPI_OOB_TX_IEN REG8(MCHP_ESPI_IO_BASE + 0x268)
+#define MCHP_ESPI_OOB_TX_STATUS REG32(MCHP_ESPI_IO_BASE + 0x26C)
 /* Flash Channel Registers */
-#define MCHP_ESPI_FC_ADDR_LO		REG32(MCHP_ESPI_IO_BASE + 0x280)
-#define MCHP_ESPI_FC_ADDR_HI		REG32(MCHP_ESPI_IO_BASE + 0x284)
-#define MCHP_ESPI_FC_BUF_ADDR_LO	REG32(MCHP_ESPI_IO_BASE + 0x288)
-#define MCHP_ESPI_FC_BUF_ADDR_HI	REG32(MCHP_ESPI_IO_BASE + 0x28C)
-#define MCHP_ESPI_FC_XFR_LEN		REG32(MCHP_ESPI_IO_BASE + 0x290)
-#define MCHP_ESPI_FC_CTL		REG32(MCHP_ESPI_IO_BASE + 0x294)
-#define MCHP_ESPI_FC_IEN		REG8(MCHP_ESPI_IO_BASE + 0x298)
-#define MCHP_ESPI_FC_CONFIG		REG32(MCHP_ESPI_IO_BASE + 0x29C)
-#define MCHP_ESPI_FC_STATUS		REG32(MCHP_ESPI_IO_BASE + 0x2A0)
-
+#define MCHP_ESPI_FC_ADDR_LO REG32(MCHP_ESPI_IO_BASE + 0x280)
+#define MCHP_ESPI_FC_ADDR_HI REG32(MCHP_ESPI_IO_BASE + 0x284)
+#define MCHP_ESPI_FC_BUF_ADDR_LO REG32(MCHP_ESPI_IO_BASE + 0x288)
+#define MCHP_ESPI_FC_BUF_ADDR_HI REG32(MCHP_ESPI_IO_BASE + 0x28C)
+#define MCHP_ESPI_FC_XFR_LEN REG32(MCHP_ESPI_IO_BASE + 0x290)
+#define MCHP_ESPI_FC_CTL REG32(MCHP_ESPI_IO_BASE + 0x294)
+#define MCHP_ESPI_FC_IEN REG8(MCHP_ESPI_IO_BASE + 0x298)
+#define MCHP_ESPI_FC_CONFIG REG32(MCHP_ESPI_IO_BASE + 0x29C)
+#define MCHP_ESPI_FC_STATUS REG32(MCHP_ESPI_IO_BASE + 0x2A0)
 /* VWire Channel Registers */
-#define MCHP_ESPI_VW_STATUS		REG8(MCHP_ESPI_IO_BASE + 0x2B0)
-
+#define MCHP_ESPI_VW_STATUS REG8(MCHP_ESPI_IO_BASE + 0x2B0)
 /* Global Registers */
 /* 32-bit register containing CAP_ID/CAP0/CAP1/PC_CAP */
-#define MCHP_ESPI_IO_REG32_A		REG32(MCHP_ESPI_IO_BASE + 0x2E0)
-#define MCHP_ESPI_IO_CAP_ID		REG8(MCHP_ESPI_IO_BASE + 0x2E0)
-#define MCHP_ESPI_IO_CAP0		REG8(MCHP_ESPI_IO_BASE + 0x2E1)
-#define MCHP_ESPI_IO_CAP1		REG8(MCHP_ESPI_IO_BASE + 0x2E2)
-#define MCHP_ESPI_IO_PC_CAP		REG8(MCHP_ESPI_IO_BASE + 0x2E3)
+#define MCHP_ESPI_IO_REG32_A REG32(MCHP_ESPI_IO_BASE + 0x2E0)
+#define MCHP_ESPI_IO_CAP_ID REG8(MCHP_ESPI_IO_BASE + 0x2E0)
+#define MCHP_ESPI_IO_CAP0 REG8(MCHP_ESPI_IO_BASE + 0x2E1)
+#define MCHP_ESPI_IO_CAP1 REG8(MCHP_ESPI_IO_BASE + 0x2E2)
+#define MCHP_ESPI_IO_PC_CAP REG8(MCHP_ESPI_IO_BASE + 0x2E3)
 /* 32-bit register containing VW_CAP/OOB_CAP/FC_CAP/PC_READY */
-#define MCHP_ESPI_IO_REG32_B		REG32(MCHP_ESPI_IO_BASE + 0x2E4)
-#define MCHP_ESPI_IO_VW_CAP		REG8(MCHP_ESPI_IO_BASE + 0x2E4)
-#define MCHP_ESPI_IO_OOB_CAP		REG8(MCHP_ESPI_IO_BASE + 0x2E5)
-#define MCHP_ESPI_IO_FC_CAP		REG8(MCHP_ESPI_IO_BASE + 0x2E6)
-#define MCHP_ESPI_IO_PC_READY		REG8(MCHP_ESPI_IO_BASE + 0x2E7)
+#define MCHP_ESPI_IO_REG32_B REG32(MCHP_ESPI_IO_BASE + 0x2E4)
+#define MCHP_ESPI_IO_VW_CAP REG8(MCHP_ESPI_IO_BASE + 0x2E4)
+#define MCHP_ESPI_IO_OOB_CAP REG8(MCHP_ESPI_IO_BASE + 0x2E5)
+#define MCHP_ESPI_IO_FC_CAP REG8(MCHP_ESPI_IO_BASE + 0x2E6)
+#define MCHP_ESPI_IO_PC_READY REG8(MCHP_ESPI_IO_BASE + 0x2E7)
 /* 32-bit register containing OOB_READY/FC_READY/RESET_STATUS/RESET_IEN */
-#define MCHP_ESPI_IO_REG32_C		REG32(MCHP_ESPI_IO_BASE + 0x2E8)
-#define MCHP_ESPI_IO_OOB_READY		REG8(MCHP_ESPI_IO_BASE + 0x2E8)
-#define MCHP_ESPI_IO_FC_READY		REG8(MCHP_ESPI_IO_BASE + 0x2E9)
-#define MCHP_ESPI_IO_RESET_STATUS	REG8(MCHP_ESPI_IO_BASE + 0x2EA)
-#define MCHP_ESPI_IO_RESET_IEN		REG8(MCHP_ESPI_IO_BASE + 0x2EB)
+#define MCHP_ESPI_IO_REG32_C REG32(MCHP_ESPI_IO_BASE + 0x2E8)
+#define MCHP_ESPI_IO_OOB_READY REG8(MCHP_ESPI_IO_BASE + 0x2E8)
+#define MCHP_ESPI_IO_FC_READY REG8(MCHP_ESPI_IO_BASE + 0x2E9)
+#define MCHP_ESPI_IO_RESET_STATUS REG8(MCHP_ESPI_IO_BASE + 0x2EA)
+#define MCHP_ESPI_IO_RESET_IEN REG8(MCHP_ESPI_IO_BASE + 0x2EB)
 /* 32-bit register containing PLTRST_SRC/VW_READY */
-#define MCHP_ESPI_IO_REG32_D		REG32(MCHP_ESPI_IO_BASE + 0x2EC)
-#define MCHP_ESPI_IO_PLTRST_SRC		REG8(MCHP_ESPI_IO_BASE + 0x2EC)
-#define MCHP_ESPI_IO_VW_READY		REG8(MCHP_ESPI_IO_BASE + 0x2ED)
-
-
+#define MCHP_ESPI_IO_REG32_D REG32(MCHP_ESPI_IO_BASE + 0x2EC)
+#define MCHP_ESPI_IO_PLTRST_SRC REG8(MCHP_ESPI_IO_BASE + 0x2EC)
+#define MCHP_ESPI_IO_VW_READY REG8(MCHP_ESPI_IO_BASE + 0x2ED)
 /* Bits in MCHP_ESPI_IO_CAP0 */
-#define MCHP_ESPI_CAP0_PC_SUPP		0x01
-#define MCHP_ESPI_CAP0_VW_SUPP		0x02
-#define MCHP_ESPI_CAP0_OOB_SUPP		0x04
-#define MCHP_ESPI_CAP0_FC_SUPP		0x08
-#define MCHP_ESPI_CAP0_ALL_CHAN_SUPP	(MCHP_ESPI_CAP0_PC_SUPP | \
-						MCHP_ESPI_CAP0_VW_SUPP | \
-						MCHP_ESPI_CAP0_OOB_SUPP | \
-						MCHP_ESPI_CAP0_FC_SUPP)
-
+#define MCHP_ESPI_CAP0_PC_SUPP 0x01
+#define MCHP_ESPI_CAP0_VW_SUPP 0x02
+#define MCHP_ESPI_CAP0_OOB_SUPP 0x04
+#define MCHP_ESPI_CAP0_FC_SUPP 0x08
+#define MCHP_ESPI_CAP0_ALL_CHAN_SUPP                       \
+	(MCHP_ESPI_CAP0_PC_SUPP | MCHP_ESPI_CAP0_VW_SUPP | \
+	 MCHP_ESPI_CAP0_OOB_SUPP | MCHP_ESPI_CAP0_FC_SUPP)
 /* Bits in MCHP_ESPI_IO_CAP1 */
-#define MCHP_ESPI_CAP1_RW_MASK		0x37
-#define MCHP_ESPI_CAP1_MAX_FREQ_MASK	0x07
-#define MCHP_ESPI_CAP1_MAX_FREQ_20M	0x00
-#define MCHP_ESPI_CAP1_MAX_FREQ_25M	0x01
-#define MCHP_ESPI_CAP1_MAX_FREQ_33M	0x02
-#define MCHP_ESPI_CAP1_MAX_FREQ_50M	0x03
-#define MCHP_ESPI_CAP1_MAX_FREQ_66M	0x04
-#define MCHP_ESPI_CAP1_IO_BITPOS	4
-#define MCHP_ESPI_CAP1_IO_MASK0		0x03
-#define MCHP_ESPI_CAP1_IO_MASK		(0x03ul << 4)
-#define MCHP_ESPI_CAP1_IO1_VAL		0x00
-#define MCHP_ESPI_CAP1_IO12_VAL		0x01
-#define MCHP_ESPI_CAP1_IO24_VAL		0x02
-#define MCHP_ESPI_CAP1_IO124_VAL	0x03
-#define MCHP_ESPI_CAP1_IO1		(0x00 << 4)
-#define MCHP_ESPI_CAP1_IO12		(0x01 << 4)
-#define MCHP_ESPI_CAP1_IO24		(0x02 << 4)
-#define MCHP_ESPI_CAP1_IO124		(0x03 << 4)
-
-
+#define MCHP_ESPI_CAP1_RW_MASK 0x37
+#define MCHP_ESPI_CAP1_MAX_FREQ_MASK 0x07
+#define MCHP_ESPI_CAP1_MAX_FREQ_20M 0
+#define MCHP_ESPI_CAP1_MAX_FREQ_25M 1
+#define MCHP_ESPI_CAP1_MAX_FREQ_33M 2
+#define MCHP_ESPI_CAP1_MAX_FREQ_50M 3
+#define MCHP_ESPI_CAP1_MAX_FREQ_66M 4
+#define MCHP_ESPI_CAP1_SINGLE_MODE 0
+#define MCHP_ESPI_CAP1_SINGLE_DUAL_MODE BIT(0)
+#define MCHP_ESPI_CAP1_SINGLE_QUAD_MODE BIT(1)
+#define MCHP_ESPI_CAP1_ALL_MODE                                         \
+	(MCHP_ESPI_CAP1_SINGLE_MODE | MCHP_ESPI_CAP1_SINGLE_DUAL_MODE | \
+	 MCHP_ESPI_CAP1_SINGLE_QUAD_MODE)
+#define MCHP_ESPI_CAP1_IO_BITPOS 4
+#define MCHP_ESPI_CAP1_IO_MASK0 0x03
+#define MCHP_ESPI_CAP1_IO_MASK (0x03ul << MCHP_ESPI_CAP1_IO_BITPOS)
+#define MCHP_ESPI_CAP1_IO1_VAL 0x00
+#define MCHP_ESPI_CAP1_IO12_VAL 0x01
+#define MCHP_ESPI_CAP1_IO24_VAL 0x02
+#define MCHP_ESPI_CAP1_IO124_VAL 0x03
+#define MCHP_ESPI_CAP1_IO1 (0x00 << 4)
+#define MCHP_ESPI_CAP1_IO12 (0x01 << 4)
+#define MCHP_ESPI_CAP1_IO24 (0x02 << 4)
+#define MCHP_ESPI_CAP1_IO124 (0x03 << 4)
 /* Bits in MCHP_ESPI_IO_RESET_STATUS and MCHP_ESPI_IO_RESET_IEN */
-#define MCHP_ESPI_RST_PIN_MASK	0x02
-#define MCHP_ESPI_RST_CHG_STS	1
-#define MCHP_ESPI_RST_IEN	1
-
-
+#define MCHP_ESPI_RST_PIN_MASK BIT(1)
+#define MCHP_ESPI_RST_CHG_STS BIT(0)
+#define MCHP_ESPI_RST_IEN BIT(0)
 /* Bits in MCHP_ESPI_IO_PLTRST_SRC */
-#define MCHP_ESPI_PLTRST_SRC_VW		0
-#define MCHP_ESPI_PLTRST_SRC_PIN	1
-
-
+#define MCHP_ESPI_PLTRST_SRC_VW 0
+#define MCHP_ESPI_PLTRST_SRC_PIN 1
 /*
  * eSPI Slave Activate Register
  * bit[0] = 0 de-active block is clock-gates
  * bit[0] = 1 block is powered and functional
  */
-#define MCHP_ESPI_ACTIVATE	REG8(MCHP_ESPI_IO_BASE + 0x330)
-
-
+#define MCHP_ESPI_ACTIVATE REG8(MCHP_ESPI_IO_BASE + 0x330)
 /*
  * IO BAR's starting at offset 0x134
  * b[16]=virtualized R/W
@@ -1489,80 +549,24 @@ enum MCHP_i2c_port {
  * b[13:8]=Logical Device Number RO
  * b[7:0]=mask
  */
-#define MCHP_ESPI_IO_BAR_CTL(x)	REG32(MCHP_ESPI_IO_BASE + \
-	0x134 + ((x) << 2))
+#define MCHP_ESPI_IO_BAR_CTL(x) REG32(MCHP_ESPI_IO_BASE + ((x)*4) + 0x134)
 /* access mask field of eSPI IO BAR Control register */
-#define MCHP_ESPI_IO_BAR_CTL_MASK(x) REG8(MCHP_ESPI_IO_BASE + \
-	0x134 + ((x) << 2))
-
+#define MCHP_ESPI_IO_BAR_CTL_MASK(x) REG8(MCHP_ESPI_IO_BASE + ((x)*4) + 0x134)
 /*
  * IO BAR's starting at offset 0x334
  * b[31:16] = I/O address
  * b[15:1]=0 reserved
  * b[0] = valid
  */
-#define MCHP_ESPI_IO_BAR(x) REG32(MCHP_ESPI_IO_BASE + 0x334 + ((x) << 2))
-
-#define MCHP_ESPI_IO_BAR_VALID(x)	REG8(MCHP_ESPI_IO_BASE + \
-	0x334 + ((x) << 2) + 0)
-#define MCHP_ESPI_IO_BAR_ADDR_LSB(x)	REG8(MCHP_ESPI_IO_BASE + \
-	0x334 + ((x) << 2) + 2)
-#define MCHP_ESPI_IO_BAR_ADDR_MSB(x)	REG8(MCHP_ESPI_IO_BASE + \
-	0x334 + ((x) << 2) + 3)
-#define MCHP_ESPI_IO_BAR_ADDR(x)	REG16(MCHP_ESPI_IO_BASE + \
-	0x334 + ((x) << 2) + 2)
-
-/* Indices for use in above macros */
-#define MCHP_ESPI_IO_BAR_ID_CFG_PORT	0
-#define MCHP_ESPI_IO_BAR_ID_MEM_CMPNT	1
-#define MCHP_ESPI_IO_BAR_ID_MAILBOX	2
-#define MCHP_ESPI_IO_BAR_ID_8042	3
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC0	4
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC1	5
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC2	6
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC3	7
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC4	8
-#define MCHP_ESPI_IO_BAR_ID_ACPI_PM1	9
-#define MCHP_ESPI_IO_BAR_ID_P92		0xA
-#define MCHP_ESPI_IO_BAR_ID_UART0	0xB
-#define MCHP_ESPI_IO_BAR_ID_UART1	0xC
-#define MCHP_ESPI_IO_BAR_ID_EMI0	0xD
-#define MCHP_ESPI_IO_BAR_ID_EMI1	0xE
-#define MCHP_ESPI_IO_BAR_ID_EMI		0xF
-#define MCHP_ESPI_IO_BAR_P80_0		0x10
-#define MCHP_ESPI_IO_BAR_P80_1		0x11
-#define MCHP_ESPI_IO_BAR_RTC		0x12
-
+#define MCHP_ESPI_IO_BAR(x) REG32(MCHP_ESPI_IO_BASE + ((x)*4) + 0x334)
+#define MCHP_ESPI_IO_BAR_VALID(x) REG8(MCHP_ESPI_IO_BASE + ((x)*4) + 0x334)
+#define MCHP_ESPI_IO_BAR_ADDR_LSB(x) REG8(MCHP_ESPI_IO_BASE + ((x)*4) + 0x336)
+#define MCHP_ESPI_IO_BAR_ADDR_MSB(x) REG8(MCHP_ESPI_IO_BASE + ((x)*4) + 0x337)
+#define MCHP_ESPI_IO_BAR_ADDR(x) REG16(MCHP_ESPI_IO_BASE + ((x)*4) + 0x336)
 /* eSPI Serial IRQ registers */
-#define MCHP_ESPI_IO_SERIRQ_REG(x)	REG8(MCHP_ESPI_IO_BASE + \
-						0x3ac + (x))
-#define MCHP_ESPI_MBOX_SIRQ0		0
-#define MCHP_ESPI_MBOX_SIRQ1		1
-#define MCHP_ESPI_8042_SIRQ0		2
-#define MCHP_ESPI_8042_SIRQ1		3
-#define MCHP_ESPI_ACPI_EC0_SIRQ		4
-#define MCHP_ESPI_ACPI_EC1_SIRQ		5
-#define MCHP_ESPI_ACPI_EC2_SIRQ		6
-#define MCHP_ESPI_ACPI_EC3_SIRQ		7
-#define MCHP_ESPI_ACPI_EC4_SIRQ		8
-#define MCHP_ESPI_UART0_SIRQ		9
-#define MCHP_ESPI_UART1_SIRQ		10
-#define MCHP_ESPI_EMI0_SIRQ0		11
-#define MCHP_ESPI_EMI0_SIRQ1		12
-#define MCHP_ESPI_EMI1_SIRQ0		13
-#define MCHP_ESPI_EMI1_SIRQ1		14
-#define MCHP_ESPI_EMI2_SIRQ0		15
-#define MCHP_ESPI_EMI2_SIRQ1		16
-#define MCHP_ESPI_RTC_SIRQ		17
-#define MCHP_ESPI_EC_SIRQ		18
-
+#define MCHP_ESPI_IO_SERIRQ_REG(x) REG8(MCHP_ESPI_IO_BASE + 0x3ac + (x))
 /* eSPI Virtual Wire Error Register */
-#define MCHP_ESPI_IO_VW_ERROR	REG8(MCHP_ESPI_IO_BASE + 0x3f0)
-
-
-/* eSPI Memory Component Base Address */
-#define MCHP_ESPI_MEM_BASE		0x400f3800
-
+#define MCHP_ESPI_IO_VW_ERROR REG8(MCHP_ESPI_IO_BASE + 0x3f0)
 /*
  * eSPI Logical Device Memory Host BAR's to specify Host memory
  * base address and valid bit.
@@ -1571,31 +575,15 @@ enum MCHP_i2c_port {
  * b[15:1]=0(reserved)
  * b[79:16]=eSPI bus memory address(Host address space)
  */
-#define MCHP_ESPI_MBAR_MBOX_ID		0
-#define MCHP_ESPI_MBAR_ACPI_EC0_ID	1
-#define MCHP_ESPI_MBAR_ACPI_EC1_ID	2
-#define MCHP_ESPI_MBAR_ACPI_EC2_ID	3
-#define MCHP_ESPI_MBAR_ACPI_EC3_ID	4
-#define MCHP_ESPI_MBAR_ACPI_EC4_ID	5
-#define MCHP_ESPI_MBAR_EMI0_ID		6
-#define MCHP_ESPI_MBAR_EMI1_ID		7
-#define MCHP_ESPI_MBAR_EMI2_ID		8
-
-#define MCHP_ESPI_MBAR_VALID(x) \
-	REG8(MCHP_ESPI_MEM_BASE + 0x130 + ((x) << 3) + ((x) << 1))
-
+#define MCHP_ESPI_MBAR_VALID(x) REG8(MCHP_ESPI_MEM_BASE + ((x)*10) + 0x130)
 #define MCHP_ESPI_MBAR_HOST_ADDR_0_15(x) \
-	REG16(MCHP_ESPI_MEM_BASE + 0x132 + ((x) << 3) + ((x) << 1))
-
+	REG16(MCHP_ESPI_MEM_BASE + ((x)*10) + 0x132)
 #define MCHP_ESPI_MBAR_HOST_ADDR_16_31(x) \
-	REG16(MCHP_ESPI_MEM_BASE + 0x134 + ((x) << 3) + ((x) << 1))
-
+	REG16(MCHP_ESPI_MEM_BASE + ((x)*10) + 0x134)
 #define MCHP_ESPI_MBAR_HOST_ADDR_32_47(x) \
-	REG16(MCHP_ESPI_MEM_BASE + 0x136 + ((x) << 3) + ((x) << 1))
-
+	REG16(MCHP_ESPI_MEM_BASE + ((x)*10) + 0x136)
 #define MCHP_ESPI_MBAR_HOST_ADDR_48_63(x) \
-	REG16(MCHP_ESPI_MEM_BASE + 0x138 + ((x) << 3) + ((x) << 1))
-
+	REG16(MCHP_ESPI_MEM_BASE + ((x)*10) + 0x138)
 /*
  * eSPI SRAM BAR's
  * b[0,3,8:15] = 0 reserved
@@ -1603,45 +591,27 @@ enum MCHP_i2c_port {
  * b[7:4] = size
  * b[79:16] = Host address
  */
-#define MCHP_ESPI_SRAM_BAR_CFG(x) \
-	REG8(MCHP_ESPI_MEM_BASE + 0x1ac + ((x) << 3) + ((x) << 1))
-
+#define MCHP_ESPI_SRAM_BAR_CFG(x) REG8(MCHP_ESPI_MEM_BASE + ((x)*10) + 0x1ac)
 #define MCHP_ESPI_SRAM_BAR_ADDR_0_15(x) \
-	REG16(MCHP_ESPI_MEM_BASE + 0x1ae + ((x) << 3) + ((x) << 1))
-
+	REG16(MCHP_ESPI_MEM_BASE + ((x)*10) + 0x1ae)
 #define MCHP_ESPI_SRAM_BAR_ADDR_16_31(x) \
-	REG16(MCHP_ESPI_MEM_BASE + 0x1b0 + ((x) << 3) + ((x) << 1))
-
+	REG16(MCHP_ESPI_MEM_BASE + ((x)*10) + 0x1b0)
 #define MCHP_ESPI_SRAM_BAR_ADDR_32_47(x) \
-	REG16(MCHP_ESPI_MEM_BASE + 0x1b2 + ((x) << 3) + ((x) << 1))
-
+	REG16(MCHP_ESPI_MEM_BASE + ((x)*10) + 0x1b2)
 #define MCHP_ESPI_SRAM_BAR_ADDR_48_63(x) \
-	REG16(MCHP_ESPI_MEM_BASE + 0x1b4 + ((x) << 3) + ((x) << 1))
-
+	REG16(MCHP_ESPI_MEM_BASE + ((x)*10) + 0x1b4)
 /* eSPI Memory Bus Master Registers */
-#define MCHP_ESPI_BM_STATUS \
-	REG32(MCHP_ESPI_MEM_BASE + 0x200)
-#define MCHP_ESPI_BM_IEN \
-	REG32(MCHP_ESPI_MEM_BASE + 0x204)
-#define MCHP_ESPI_BM_CONFIG \
-	REG32(MCHP_ESPI_MEM_BASE + 0x208)
-#define MCHP_ESPI_BM1_CTL \
-	REG32(MCHP_ESPI_MEM_BASE + 0x210)
-#define MCHP_ESPI_BM1_HOST_ADDR_LO \
-		REG32(MCHP_ESPI_MEM_BASE + 0x214)
-#define MCHP_ESPI_BM1_HOST_ADDR_HI \
-	REG32(MCHP_ESPI_MEM_BASE + 0x218)
-#define MCHP_ESPI_BM1_EC_ADDR \
-	REG32(MCHP_ESPI_MEM_BASE + 0x21c)
-#define MCHP_ESPI_BM2_CTL \
-	REG32(MCHP_ESPI_MEM_BASE + 0x224)
-#define MCHP_ESPI_BM2_HOST_ADDR_LO \
-	REG32(MCHP_ESPI_MEM_BASE + 0x228)
-#define MCHP_ESPI_BM2_HOST_ADDR_HI \
-	REG32(MCHP_ESPI_MEM_BASE + 0x22c)
-#define MCHP_ESPI_BM2_EC_ADDR \
-	REG32(MCHP_ESPI_MEM_BASE + 0x230)
-
+#define MCHP_ESPI_BM_STATUS REG32(MCHP_ESPI_MEM_BASE + 0x200)
+#define MCHP_ESPI_BM_IEN REG32(MCHP_ESPI_MEM_BASE + 0x204)
+#define MCHP_ESPI_BM_CONFIG REG32(MCHP_ESPI_MEM_BASE + 0x208)
+#define MCHP_ESPI_BM1_CTL REG32(MCHP_ESPI_MEM_BASE + 0x210)
+#define MCHP_ESPI_BM1_HOST_ADDR_LO REG32(MCHP_ESPI_MEM_BASE + 0x214)
+#define MCHP_ESPI_BM1_HOST_ADDR_HI REG32(MCHP_ESPI_MEM_BASE + 0x218)
+#define MCHP_ESPI_BM1_EC_ADDR REG32(MCHP_ESPI_MEM_BASE + 0x21c)
+#define MCHP_ESPI_BM2_CTL REG32(MCHP_ESPI_MEM_BASE + 0x224)
+#define MCHP_ESPI_BM2_HOST_ADDR_LO REG32(MCHP_ESPI_MEM_BASE + 0x228)
+#define MCHP_ESPI_BM2_HOST_ADDR_HI REG32(MCHP_ESPI_MEM_BASE + 0x22c)
+#define MCHP_ESPI_BM2_EC_ADDR REG32(MCHP_ESPI_MEM_BASE + 0x230)
 /*
  * eSPI Memory BAR's for Logical Devices
  * b[0] = Valid
@@ -1654,37 +624,29 @@ enum MCHP_i2c_port {
  *
  * BAR's start at offset 0x330
  */
-#define MCHP_ESPI_MBAR_EC_VSIZE(x) \
-	REG32(MCHP_ESPI_MEM_BASE + 0x330 + ((x) << 3) + ((x) << 1))
+#define MCHP_ESPI_MBAR_EC_VSIZE(x) REG32(MCHP_ESPI_MEM_BASE + ((x)*10) + 0x330)
 #define MCHP_ESPI_MBAR_EC_ADDR_0_15(x) \
-	REG16(MCHP_ESPI_MEM_BASE + 0x332 + ((x) << 3) + ((x) << 1))
+	REG16(MCHP_ESPI_MEM_BASE + ((x)*10) + 0x332)
 #define MCHP_ESPI_MBAR_EC_ADDR_16_31(x) \
-	REG16(MCHP_ESPI_MEM_BASE + 0x334 + ((x) << 3) + ((x) << 1))
+	REG16(MCHP_ESPI_MEM_BASE + ((x)*10) + 0x334)
 #define MCHP_ESPI_MBAR_EC_ADDR_32_47(x) \
-	REG16(MCHP_ESPI_MEM_BASE + 0x336 + ((x) << 3) + ((x) << 1))
-
-/* eSPI Virtual Wire Component Base Address */
-#define MCHP_ESPI_VW_BASE		0x400f9c00
-
-#define MCHP_ESPI_MSVW_BASE	(MCHP_ESPI_VW_BASE)
-#define MCHP_ESPI_SMVW_BASE	((MCHP_ESPI_VW_BASE) + 0x200ul)
+	REG16(MCHP_ESPI_MEM_BASE + ((x)*10) + 0x336)
 
-#define MCHP_ESPI_MSVW_LEN	12
-#define MCHP_ESPI_SMVW_LEN	8
+/* eSPI Virtual Wire registers */
+#define MCHP_ESPI_MSVW_LEN 12
+#define MCHP_ESPI_SMVW_LEN 8
 
-#define MCHP_ESPI_MSVW_ADDR(n) ((MCHP_ESPI_MSVW_BASE) + \
-	((n) * (MCHP_ESPI_MSVW_LEN)))
-
-#define MCHP_ESPI_MSVW_MTOS_BITPOS		4
-
-#define MCHP_ESPI_MSVW_IRQSEL_LEVEL_LO		0
-#define MCHP_ESPI_MSVW_IRQSEL_LEVEL_HI		1
-#define MCHP_ESPI_MSVW_IRQSEL_DISABLED		4
-#define MCHP_ESPI_MSVW_IRQSEL_RISING		0x0d
-#define MCHP_ESPI_MSVW_IRQSEL_FALLING		0x0e
-#define MCHP_ESPI_MSVW_IRQSEL_BOTH_EDGES	0x0f
+#define MCHP_ESPI_MSVW_ADDR(n) \
+	((MCHP_ESPI_MSVW_BASE) + ((n) * (MCHP_ESPI_MSVW_LEN)))
 
+#define MCHP_ESPI_MSVW_MTOS_BITPOS 4
 
+#define MCHP_ESPI_MSVW_IRQSEL_LEVEL_LO 0
+#define MCHP_ESPI_MSVW_IRQSEL_LEVEL_HI 1
+#define MCHP_ESPI_MSVW_IRQSEL_DISABLED 4
+#define MCHP_ESPI_MSVW_IRQSEL_RISING 0x0d
+#define MCHP_ESPI_MSVW_IRQSEL_FALLING 0x0e
+#define MCHP_ESPI_MSVW_IRQSEL_BOTH_EDGES 0x0f
 
 /*
  * Mapping of eSPI Master Host VWire group indices to
@@ -1692,93 +654,60 @@ enum MCHP_i2c_port {
  * MSVW_xy where xy = PCH VWire number.
  * Each PCH VWire number controls 4 virtual wires.
  */
-#define MSVW_H02	0
-#define MSVW_H03	1
-#define MSVW_H07	2
-#define MSVW_H41	3
-#define MSVW_H42	4
-#define MSVW_H43	5
-#define MSVW_H44	6
-#define MSVW_H47	7
-#define MSVW_H4A	8
-#define MSVW_HSPARE0	9
-#define MSVW_HSPARE1	10
-#define MSVW_MAX	11
-
+#define MSVW_H02 0
+#define MSVW_H03 1
+#define MSVW_H07 2
+#define MSVW_H41 3
+#define MSVW_H42 4
+#define MSVW_H43 5
+#define MSVW_H44 6
+#define MSVW_H47 7
+#define MSVW_H4A 8
+#define MSVW_HSPARE0 9
+#define MSVW_HSPARE1 10
+#define MSVW_MAX 11
 
 /* Access 32-bit word in 96-bit MSVW register. 0 <= w <= 2 */
-#define MSVW(id, w) REG32(MCHP_ESPI_MSVW_BASE + ((id) << 3) + \
-	((id << 2)) + (((w) & 0x03) << 2))
-
+#define MSVW(id, w) REG32(MCHP_ESPI_MSVW_BASE + ((id)*12) + (((w)&0x03) * 4))
 /* Access index value in byte 0 */
-#define MCHP_ESPI_VW_M2S_INDEX(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) << 3) + ((id) << 2))
-
+#define MCHP_ESPI_VW_M2S_INDEX(id) REG8(MCHP_ESPI_VW_BASE + ((id)*12))
 /*
  * Access MTOS_SOURCE and MTOS_STATE in byte 1
  * MTOS_SOURCE = b[1:0] specifies reset source
  * MTOS_STATE = b[7:4] are states loaded into SRC[0:3] on reset event
  */
-#define MCHP_ESPI_VW_M2S_MTOS(id) \
-	REG8(MCHP_ESPI_VW_BASE + 1 + ((id) << 3) + ((id) << 2))
-
+#define MCHP_ESPI_VW_M2S_MTOS(id) REG8(MCHP_ESPI_VW_BASE + 1 + ((id)*12))
 /*
  * Access Index, MTOS Source, and MTOS State as 16-bit quantity.
  * Index in b[7:0]
  * MTOS Source in b[9:8]
  * MTOS State in b[15:12]
  */
-#define MCHP_ESPI_VW_M2S_INDEX_MTOS(id) \
-	REG16(MCHP_ESPI_VW_BASE + ((id) << 3) + ((id) << 2))
-
+#define MCHP_ESPI_VW_M2S_INDEX_MTOS(id) REG16(MCHP_ESPI_VW_BASE + ((id)*12))
 /* Access SRCn IRQ Select bit fields */
-#define MCHP_ESPI_VW_M2S_IRQSEL0(id) \
-	(REG8(MCHP_ESPI_VW_BASE + 4 + ((id) << 3) + ((id) << 2)))
-
-#define MCHP_ESPI_VW_M2S_IRQSEL1(id) \
-	(REG8(MCHP_ESPI_VW_BASE + 5 + ((id) << 3) + ((id) << 2)))
-
-#define MCHP_ESPI_VW_M2S_IRQSEL2(id) \
-	(REG8(MCHP_ESPI_VW_BASE + 6 + ((id) << 3) + ((id) << 2)))
-
-#define MCHP_ESPI_VW_M2S_IRQSEL3(id) \
-	(REG8(MCHP_ESPI_VW_BASE + 7 + ((id) << 3) + ((id) << 2)))
-
+#define MCHP_ESPI_VW_M2S_IRQSEL0(id) REG8(MCHP_ESPI_VW_BASE + ((id)*12) + 4)
+#define MCHP_ESPI_VW_M2S_IRQSEL1(id) REG8(MCHP_ESPI_VW_BASE + ((id)*12) + 5)
+#define MCHP_ESPI_VW_M2S_IRQSEL2(id) REG8(MCHP_ESPI_VW_BASE + ((id)*12) + 6)
+#define MCHP_ESPI_VW_M2S_IRQSEL3(id) REG8(MCHP_ESPI_VW_BASE + ((id)*12) + 7)
 #define MCHP_ESPI_VW_M2S_IRQSEL(id, src) \
-	REG8(MCHP_ESPI_VW_BASE + 4 + ((id) << 3) + ((id) << 2) + \
-						((src) & 0x03))
-
-#define MCHP_ESPI_VW_M2S_IRQSEL_ALL(id) \
-	(REG32(MCHP_ESPI_VW_BASE + 4 + ((id) << 3) + ((id) << 2)))
-
+	REG8(MCHP_ESPI_VW_BASE + ((id)*12) + 4 + ((src)&0x03))
+#define MCHP_ESPI_VW_M2S_IRQSEL_ALL(id) REG32(MCHP_ESPI_VW_BASE + ((id)*12) + 4)
 /* Access individual source bits */
-#define MCHP_ESPI_VW_M2S_SRC0(id) \
-	REG8(MCHP_ESPI_VW_BASE + 8 + ((id) << 3) + ((id) << 2))
-
-#define MCHP_ESPI_VW_M2S_SRC1(id) \
-	REG8(MCHP_ESPI_VW_BASE + 9 + ((id) << 3) + ((id) << 2))
-
-#define MCHP_ESPI_VW_M2S_SRC2(id) \
-	REG8(MCHP_ESPI_VW_BASE + 10 + ((id) << 3) + ((id) << 2))
-
-#define MCHP_ESPI_VW_M2S_SRC3(id) \
-	REG8(MCHP_ESPI_VW_BASE + 11 + ((id) << 3) + ((id) << 2))
-
+#define MCHP_ESPI_VW_M2S_SRC0(id) REG8(MCHP_ESPI_VW_BASE + ((id)*12) + 8)
+#define MCHP_ESPI_VW_M2S_SRC1(id) REG8(MCHP_ESPI_VW_BASE + ((id)*12) + 9)
+#define MCHP_ESPI_VW_M2S_SRC2(id) REG8(MCHP_ESPI_VW_BASE + ((id)*12) + 10)
+#define MCHP_ESPI_VW_M2S_SRC3(id) REG8(MCHP_ESPI_VW_BASE + ((id)*12) + 11)
 /*
  * Access all four Source bits as 32-bit value, Source bits are located
  * at bits[0, 8, 16, 24] of 32-bit word.
  */
-#define MCHP_ESPI_VW_M2S_SRC_ALL(id) \
-	REG32(MCHP_ESPI_VW_BASE + 8 + ((id) << 3) + ((id) << 2))
-
+#define MCHP_ESPI_VW_M2S_SRC_ALL(id) REG32(MCHP_ESPI_VW_BASE + 8 + ((id)*12))
 /*
  * Access an individual Source bit as byte where
  * bit[0] contains the source bit.
  */
 #define MCHP_ESPI_VW_M2S_SRC(id, src) \
-	REG8(MCHP_ESPI_VW_BASE + 8 + ((id) << 3) + ((src) & 0x03))
-
-
+	REG8(MCHP_ESPI_VW_BASE + 8 + ((id)*8) + ((src)&0x03))
 
 /*
  * Indices of Slave to Master Virtual Wire registers.
@@ -1789,461 +718,141 @@ enum MCHP_i2c_port {
  * MCHP maps Host indices into its Slave to Master
  * 64-bit registers.
  */
-#define SMVW_H04	0
-#define SMVW_H05	1
-#define SMVW_H06	2
-#define SMVW_H40	3
-#define SMVW_H45	4
-#define SMVW_H46	5
-#define SMVW_HSPARE6	6
-#define SMVW_HSPARE7	7
-#define SMVW_HSPARE8	8
-#define SMVW_HSPARE9	9
-#define SMVW_HSPARE10	10
-#define SMVW_MAX	11
-
+#define SMVW_H04 0
+#define SMVW_H05 1
+#define SMVW_H06 2
+#define SMVW_H40 3
+#define SMVW_H45 4
+#define SMVW_H46 5
+#define SMVW_HSPARE6 6
+#define SMVW_HSPARE7 7
+#define SMVW_HSPARE8 8
+#define SMVW_HSPARE9 9
+#define SMVW_HSPARE10 10
+#define SMVW_MAX 11
 
 /* Access 32-bit word of 64-bit SMVW register, 0 <= w <= 1 */
-#define SMVW(id, w) REG32(MCHP_ESPI_VW_BASE + 0x200 + ((id) << 3) + \
-		(((w) & 0x01) << 2))
-
+#define SMVW(id, w) \
+	REG32(MCHP_ESPI_VW_BASE + ((id)*8) + 0x200 + (((w)&0x01) * 4))
 /* Access Index in b[7:0] of byte 0 */
-#define MCHP_ESPI_VW_S2M_INDEX(id) \
-	REG8(MCHP_ESPI_VW_BASE + 0x200 + ((id) << 3))
-
+#define MCHP_ESPI_VW_S2M_INDEX(id) REG8(MCHP_ESPI_VW_BASE + ((id)*8) + 0x200)
 /* Access STOM_SOURCE and STOM_STATE in byte 1
  * STOM_SOURCE = b[1:0]
  * STOM_STATE = b[7:4]
  */
-#define MCHP_ESPI_VW_S2M_STOM(id) \
-	REG8(MCHP_ESPI_VW_BASE + 0x201 + ((id) << 3))
-
+#define MCHP_ESPI_VW_S2M_STOM(id) REG8(MCHP_ESPI_VW_BASE + ((id)*8) + 0x201)
 /* Access Index, STOM_SOURCE, and STOM_STATE in bytes[1:0]
  * Index = b[7:0]
  * STOM_SOURCE = b[9:8]
  * STOM_STATE = [15:12]
  */
 #define MCHP_ESPI_VW_S2M_INDEX_STOM(id) \
-	REG16(MCHP_ESPI_VW_BASE + 0x200 + ((id) << 3))
-
+	REG16(MCHP_ESPI_VW_BASE + ((id)*8) + 0x200)
 /* Access Change[0:3] RO bits. Set to 1 if any of SRC[0:3] change */
-#define MCHP_ESPI_VW_S2M_CHANGE(id) \
-	REG8(MCHP_ESPI_VW_BASE + 0x202 + ((id) << 3))
-
+#define MCHP_ESPI_VW_S2M_CHANGE(id) REG8(MCHP_ESPI_VW_BASE + ((id)*8) + 0x202)
 /* Access individual SRC bits
  * bit[0] = SRCn
  */
-#define MCHP_ESPI_VW_S2M_SRC0(id) \
-	REG8(MCHP_ESPI_VW_BASE + 0x204 + ((id) << 3))
-
-#define MCHP_ESPI_VW_S2M_SRC1(id) \
-	REG8(MCHP_ESPI_VW_BASE + 0x205 + ((id) << 3))
-
-#define MCHP_ESPI_VW_S2M_SRC2(id) \
-	REG8(MCHP_ESPI_VW_BASE + 0x206 + ((id) << 3))
-
-#define MCHP_ESPI_VW_S2M_SRC3(id) \
-	REG8(MCHP_ESPI_VW_BASE + 0x206 + ((id) << 3))
-
+#define MCHP_ESPI_VW_S2M_SRC0(id) REG8(MCHP_ESPI_VW_BASE + ((id)*8) + 0x204)
+#define MCHP_ESPI_VW_S2M_SRC1(id) REG8(MCHP_ESPI_VW_BASE + ((id)*8) + 0x205)
+#define MCHP_ESPI_VW_S2M_SRC2(id) REG8(MCHP_ESPI_VW_BASE + ((id)*8) + 0x206)
+#define MCHP_ESPI_VW_S2M_SRC3(id) REG8(MCHP_ESPI_VW_BASE + ((id)*8) + 0x207)
 /*
  * Access specified source bit as byte read/write.
  * Source bit is in bit[0] of byte.
  */
 #define MCHP_ESPI_VW_S2M_SRC(id, src) \
-	REG8(MCHP_ESPI_VW_BASE + 0x204 + ((id) << 3) + ((src) & 0x03))
-
-
+	REG8(MCHP_ESPI_VW_BASE + 0x204 + ((id)*8) + ((src)&0x03))
 /* Access SRC[0:3] as 32-bit word
  * SRC0 = b[0]
  * SRC1 = b[8]
  * SRC2 = b[16]
  * SRC3 = b[24]
  */
-#define MCHP_ESPI_VW_S2M_SRC_ALL(id) \
-	REG32(MCHP_ESPI_VW_BASE + 0x204 + ((id) << 3))
-
-
-/*
- * eSPI RESET, channel enables and operations except Master-to-Slave
- * WWires are all on GIRQ19
- */
-#define MCHP_ESPI_GIRQ			19
-#define MCHP_ESPI_PC_GIRQ_BIT		(1ul << 0)
-#define MCHP_ESPI_BM1_GIRQ_BIT		(1ul << 1)
-#define MCHP_ESPI_BM2_GIRQ_BIT		(1ul << 2)
-#define MCHP_ESPI_LTR_GIRQ_BIT		(1ul << 3)
-#define MCHP_ESPI_OOB_TX_GIRQ_BIT	(1ul << 4)
-#define MCHP_ESPI_OOB_RX_GIRQ_BIT	(1ul << 5)
-#define MCHP_ESPI_FC_GIRQ_BIT		(1ul << 6)
-#define MCHP_ESPI_RESET_GIRQ_BIT	(1ul << 7)
-#define MCHP_ESPI_VW_EN_GIRQ_BIT	(1ul << 8)
-
-/*
- * eSPI Master-to-Slave WWire interrupts are on GIRQ24 and GIRQ25
- */
-#define MCHP_ESPI_MSVW_0_6_GIRQ		24
-#define MCHP_ESPI_MSVW_7_10_GIRQ	25
-/*
- * Four source bits, SRC[0:3] per Master-to-Slave register
- * v = MSVW [0:10]
- * n = VWire SRC bit = [0:3]
- */
-#define MCHP_ESPI_MSVW_GIRQ(v) (24 + ((v) > 6 ? 1 : 0))
-
-#define MCHP_ESPI_MSVW_SRC_GIRQ_BIT(v, n) \
-	(((v) > 6) ? (1ul << (((v)-7)+(n))) : (1ul << ((v)+(n))))
-
-
+#define MCHP_ESPI_VW_S2M_SRC_ALL(id) REG32(MCHP_ESPI_VW_BASE + ((id)*8) + 0x204)
 
 /* DMA */
-#define MCHP_DMA_BASE		0x40002400
-#define MCHP_DMA_CH_OFS		0x40
-#define MCHP_DMA_CH_OFS_BITPOS	6
-#define MCHP_DMA_CH_BASE (MCHP_DMA_BASE + MCHP_DMA_CH_OFS)
-
-#define MCHP_DMA_MAIN_CTRL	REG8(MCHP_DMA_BASE + 0x00)
-#define MCHP_DMA_MAIN_PKT_RO	REG32(MCHP_DMA_BASE + 0x04)
-#define MCHP_DMA_MAIN_FSM_RO	REG8(MCHP_DMA_BASE + 0x08)
-
+#define MCHP_DMA_MAIN_CTRL REG8(MCHP_DMA_BASE + 0x00)
+#define MCHP_DMA_MAIN_PKT_RO REG32(MCHP_DMA_BASE + 0x04)
+#define MCHP_DMA_MAIN_FSM_RO REG8(MCHP_DMA_BASE + 0x08)
 /* DMA Channel Registers */
-#define MCHP_DMA_CH_ACT(n) \
-	REG8(MCHP_DMA_CH_BASE + ((n) << MCHP_DMA_CH_OFS_BITPOS))
-
+#define MCHP_DMA_CH_ACT(n) REG8(MCHP_DMA_CH_BASE + ((n)*MCHP_DMA_CH_OFS))
 #define MCHP_DMA_CH_MEM_START(n) \
-	REG32(MCHP_DMA_CH_BASE + 0x04 + \
-			((n) << MCHP_DMA_CH_OFS_BITPOS))
-
+	REG32(MCHP_DMA_CH_BASE + ((n)*MCHP_DMA_CH_OFS) + 0x04)
 #define MCHP_DMA_CH_MEM_END(n) \
-	REG32(MCHP_DMA_CH_BASE + 0x08 + \
-			((n) << MCHP_DMA_CH_OFS_BITPOS))
-
+	REG32(MCHP_DMA_CH_BASE + ((n)*MCHP_DMA_CH_OFS) + 0x08)
 #define MCHP_DMA_CH_DEV_ADDR(n) \
-	REG32(MCHP_DMA_CH_BASE + 0x0c + \
-			((n) << MCHP_DMA_CH_OFS_BITPOS))
-
+	REG32(MCHP_DMA_CH_BASE + ((n)*MCHP_DMA_CH_OFS) + 0x0c)
 #define MCHP_DMA_CH_CTRL(n) \
-	REG32(MCHP_DMA_CH_BASE + 0x10 + \
-			((n) << MCHP_DMA_CH_OFS_BITPOS))
-
+	REG32(MCHP_DMA_CH_BASE + ((n)*MCHP_DMA_CH_OFS) + 0x10)
 #define MCHP_DMA_CH_ISTS(n) \
-	REG8(MCHP_DMA_CH_BASE + 0x14 + \
-			((n) << MCHP_DMA_CH_OFS_BITPOS))
-
+	REG32(MCHP_DMA_CH_BASE + ((n)*MCHP_DMA_CH_OFS) + 0x14)
 #define MCHP_DMA_CH_IEN(n) \
-	REG8(MCHP_DMA_CH_BASE + 0x18 + \
-			((n) << MCHP_DMA_CH_OFS_BITPOS))
-
+	REG32(MCHP_DMA_CH_BASE + ((n)*MCHP_DMA_CH_OFS) + 0x18)
 #define MCHP_DMA_CH_FSM_RO(n) \
-	REG16(MCHP_DMA_CH_BASE + 0x1c + \
-			((n) << MCHP_DMA_CH_OFS_BITPOS))
-
+	REG32(MCHP_DMA_CH_BASE + ((n)*MCHP_DMA_CH_OFS) + 0x1c)
 /*
  * DMA Channel 0 implements CRC-32 feature
  */
-#define MCHP_DMA_CH0_CRC32_EN		REG8(MCHP_DMA_CH_BASE + 0x20)
-#define MCHP_DMA_CH0_CRC32_DATA		REG32(MCHP_DMA_CH_BASE + 0x24)
-#define MCHP_DMA_CH0_CRC32_POST_STS	REG8(MCHP_DMA_CH_BASE + 0x28)
-
+#define MCHP_DMA_CH0_CRC32_EN REG8(MCHP_DMA_CH_BASE + 0x20)
+#define MCHP_DMA_CH0_CRC32_DATA REG32(MCHP_DMA_CH_BASE + 0x24)
+#define MCHP_DMA_CH0_CRC32_POST_STS REG8(MCHP_DMA_CH_BASE + 0x28)
 /*
  * DMA Channel 1 implements memory fill feature
  */
-#define MCHP_DMA_CH1_FILL_EN \
-	REG8(MCHP_DMA_CH_BASE + MCHP_DMA_CH_OFS + 0x20)
-#define MCHP_DMA_CH1_FILL_DATA \
-	REG32(MCHP_DMA_CH_BASE + MCHP_DMA_CH_OFS + 0x24)
-
-
-/*
- * Available DMA channels.
- *
- * On MCHP, any DMA channel may serve any device. Since we have
- * 14 channels and 14 devices, we make each channel dedicated to the
- * device of the same number.
- */
-enum dma_channel {
-	/* Channel numbers */
-	MCHP_DMAC_I2C0_SLAVE =  0,
-	MCHP_DMAC_I2C0_MASTER = 1,
-	MCHP_DMAC_I2C1_SLAVE =  2,
-	MCHP_DMAC_I2C1_MASTER = 3,
-	MCHP_DMAC_I2C2_SLAVE =  4,
-	MCHP_DMAC_I2C2_MASTER = 5,
-	MCHP_DMAC_I2C3_SLAVE =  6,
-	MCHP_DMAC_I2C3_MASTER = 7,
-	MCHP_DMAC_SPI0_TX =     8,
-	MCHP_DMAC_SPI0_RX =     9,
-	MCHP_DMAC_SPI1_TX =    10,
-	MCHP_DMAC_SPI1_RX =    11,
-	MCHP_DMAC_QMSPI0_TX =  12,
-	MCHP_DMAC_QMSPI0_RX =  13,
-	/* Channel count */
-	MCHP_DMAC_COUNT =      14,
-};
-
-
+#define MCHP_DMA_CH1_FILL_EN REG8(MCHP_DMA_CH_BASE + MCHP_DMA_CH_OFS + 0x20)
+#define MCHP_DMA_CH1_FILL_DATA REG32(MCHP_DMA_CH_BASE + MCHP_DMA_CH_OFS + 0x24)
 /* Bits for DMA Main Control */
-#define MCHP_DMA_MAIN_CTRL_ACT	BIT(0)
-#define MCHP_DMA_MAIN_CTRL_SRST	BIT(1)
-
+#define MCHP_DMA_MAIN_CTRL_ACT BIT(0)
+#define MCHP_DMA_MAIN_CTRL_SRST BIT(1)
 /* Bits for DMA channel regs */
-#define MCHP_DMA_ACT_EN		BIT(0)
+#define MCHP_DMA_ACT_EN BIT(0)
 /* DMA Channel Control */
-#define MCHP_DMA_ABORT		BIT(25)
-#define MCHP_DMA_SW_GO		BIT(24)
-#define MCHP_DMA_XFER_SIZE_MASK	(7ul << 20)
-#define MCHP_DMA_XFER_SIZE(x)	((x) << 20)
-#define MCHP_DMA_DIS_HW_FLOW	BIT(19)
-#define MCHP_DMA_INC_DEV	BIT(17)
-#define MCHP_DMA_INC_MEM	BIT(16)
-#define MCHP_DMA_DEV(x)		((x) << 9)
-#define MCHP_DMA_DEV_MASK0	(0x7f)
-#define MCHP_DMA_DEV_MASK	(0x7f << 9)
-#define MCHP_DMA_TO_DEV		BIT(8)
-#define MCHP_DMA_DONE		BIT(2)
-#define MCHP_DMA_RUN		BIT(0)
+#define MCHP_DMA_ABORT BIT(25)
+#define MCHP_DMA_SW_GO BIT(24)
+#define MCHP_DMA_XFER_SIZE_MASK (7ul << 20)
+#define MCHP_DMA_XFER_SIZE(x) ((x) << 20)
+#define MCHP_DMA_DIS_HW_FLOW BIT(19)
+#define MCHP_DMA_INC_DEV BIT(17)
+#define MCHP_DMA_INC_MEM BIT(16)
+#define MCHP_DMA_DEV(x) ((x) << 9)
+#define MCHP_DMA_DEV_MASK0 (0x7f)
+#define MCHP_DMA_DEV_MASK (0x7f << 9)
+#define MCHP_DMA_TO_DEV BIT(8)
+#define MCHP_DMA_DONE BIT(2)
+#define MCHP_DMA_RUN BIT(0)
 /* DMA Channel Status */
-#define MCHP_DMA_STS_ALU_DONE	BIT(3)
-#define MCHP_DMA_STS_DONE	BIT(2)
-#define MCHP_DMA_STS_HWFL_ERR	BIT(1)
-#define MCHP_DMA_STS_BUS_ERR	BIT(0)
-
-/*
- * Peripheral device DMA Device ID's for bits [15:9]
- * in DMA channel control register.
- */
-#define MCHP_DMA_I2C0_SLV_REQ_ID	0
-#define MCHP_DMA_I2C0_MTR_REQ_ID	1
-#define MCHP_DMA_I2C1_SLV_REQ_ID	2
-#define MCHP_DMA_I2C1_MTR_REQ_ID	3
-#define MCHP_DMA_I2C2_SLV_REQ_ID	4
-#define MCHP_DMA_I2C2_MTR_REQ_ID	5
-#define MCHP_DMA_I2C3_SLV_REQ_ID	6
-#define MCHP_DMA_I2C3_MTR_REQ_ID	7
-#define MCHP_DMA_GPSPI0_TX_REQ_ID	8
-#define MCHP_DMA_GPSPI0_RX_REQ_ID	9
-#define MCHP_DMA_GPSPI1_TX_REQ_ID	10
-#define MCHP_DMA_GPSPI1_RX_REQ_ID	11
-#define MCHP_DMA_QMSPI0_TX_REQ_ID	12
-#define MCHP_DMA_QMSPI0_RX_REQ_ID	13
+#define MCHP_DMA_STS_ALU_DONE BIT(3)
+#define MCHP_DMA_STS_DONE BIT(2)
+#define MCHP_DMA_STS_HWFL_ERR BIT(1)
+#define MCHP_DMA_STS_BUS_ERR BIT(0)
 
 /*
  * Required structure typedef for common/dma.h interface
  * !!! checkpatch.pl will not like this !!!
+ * structure moved to chip level dma.c
+ * We can't remove dma_chan_t as its used in DMA API header.
  */
-
-/* Registers for a single channel of the DMA controller */
 struct MCHP_dma_chan {
-	uint32_t act;		/* Activate */
-	uint32_t mem_start;	/* Memory start address */
-	uint32_t mem_end;	/* Memory end address */
-	uint32_t dev;		/* Device address */
-	uint32_t ctrl;		/* Control */
-	uint32_t int_status;	/* Interrupt status */
-	uint32_t int_enabled;	/* Interrupt enabled */
-	uint32_t chfsm;		/* channel fsm read-only */
-	uint32_t alu_en;	/* channels 0 & 1 only */
-	uint32_t alu_data;	/* channels 0 & 1 only */
-	uint32_t alu_sts;	/* channel 0 only */
-	uint32_t alu_ro;	/* channel 0 only */
-	uint32_t rsvd[4];	/* 0x30 - 0x3F */
+	uint32_t act; /* Activate */
+	uint32_t mem_start; /* Memory start address */
+	uint32_t mem_end; /* Memory end address */
+	uint32_t dev; /* Device address */
+	uint32_t ctrl; /* Control */
+	uint32_t int_status; /* Interrupt status */
+	uint32_t int_enabled; /* Interrupt enabled */
+	uint32_t chfsm; /* channel fsm read-only */
+	uint32_t alu_en; /* channels 0 & 1 only */
+	uint32_t alu_data; /* channels 0 & 1 only */
+	uint32_t alu_sts; /* channel 0 only */
+	uint32_t alu_ro; /* channel 0 only */
+	uint32_t rsvd[4]; /* 0x30 - 0x3F */
 };
 
 /* Common code and header file must use this */
 typedef struct MCHP_dma_chan dma_chan_t;
 
-/*
- * Hardware delay register.
- * Write of 0 <= n <= 31 will stall the Cortex-M4
- * for n+1 microseconds. Interrupts will not be
- * serviced during the delay period. Reads have
- * no effect.
- */
-#define MCHP_USEC_DELAY_REG_ADDR	(0x10000000)
-#define MCHP_USEC_DELAY(x)	(REG8(MCHP_USEC_DELAY_REG_ADDR) = (x))
-
-/* IRQ Numbers */
-#ifdef CHIP_FAMILY
-
-#ifdef CHIP_FAMILY_MEC17XX
-
-#define MCHP_IRQ_GIRQ8		0
-#define MCHP_IRQ_GIRQ9		1
-#define MCHP_IRQ_GIRQ10		2
-#define MCHP_IRQ_GIRQ11		3
-#define MCHP_IRQ_GIRQ12		4
-#define MCHP_IRQ_GIRQ13		5
-#define MCHP_IRQ_GIRQ14		6
-#define MCHP_IRQ_GIRQ15		7
-#define MCHP_IRQ_GIRQ16		8
-#define MCHP_IRQ_GIRQ17		9
-#define MCHP_IRQ_GIRQ18		10
-#define MCHP_IRQ_GIRQ19		11
-#define MCHP_IRQ_GIRQ20		12
-#define MCHP_IRQ_GIRQ21		13
-/*
- * GIRQ22 is not connected to NVIC, it wakes peripheral
- * subsystem but not ARM core.
- */
-#define MCHP_IRQ_GIRQ23		14
-#define MCHP_IRQ_GIRQ24		15
-#define MCHP_IRQ_GIRQ25		16
-#define MCHP_IRQ_GIRQ26		17
-/* 18 - 19 Not connected */
-#define MCHP_IRQ_I2C_0		20
-#define MCHP_IRQ_I2C_1		21
-#define MCHP_IRQ_I2C_2		22
-#define MCHP_IRQ_I2C_3		23
-#define MCHP_IRQ_DMA_0		24
-#define MCHP_IRQ_DMA_1		25
-#define MCHP_IRQ_DMA_2		26
-#define MCHP_IRQ_DMA_3		27
-#define MCHP_IRQ_DMA_4		28
-#define MCHP_IRQ_DMA_5		29
-#define MCHP_IRQ_DMA_6		30
-#define MCHP_IRQ_DMA_7		31
-#define MCHP_IRQ_DMA_8		32
-#define MCHP_IRQ_DMA_9		33
-#define MCHP_IRQ_DMA_10		34
-#define MCHP_IRQ_DMA_11		35
-#define MCHP_IRQ_DMA_12		36
-#define MCHP_IRQ_DMA_13		37
-/* 38 - 39 Not connected */
-#define MCHP_IRQ_UART0		40
-#define MCHP_IRQ_UART1		41
-#define MCHP_IRQ_EMI0		42
-#define MCHP_IRQ_EMI1		43
-#define MCHP_IRQ_EMI2		44
-#define MCHP_IRQ_ACPIEC0_IBF	45
-#define MCHP_IRQ_ACPIEC0_OBE	46
-#define MCHP_IRQ_ACPIEC1_IBF	47
-#define MCHP_IRQ_ACPIEC1_OBE	48
-#define MCHP_IRQ_ACPIEC2_IBF	49
-#define MCHP_IRQ_ACPIEC2_OBE	50
-#define MCHP_IRQ_ACPIEC3_IBF	51
-#define MCHP_IRQ_ACPIEC3_OBE	52
-#define MCHP_IRQ_ACPIEC4_IBF	53
-#define MCHP_IRQ_ACPIEC4_OBE	54
-#define MCHP_IRQ_ACPIPM1_CTL	55
-#define MCHP_IRQ_ACPIPM1_EN	56
-#define MCHP_IRQ_ACPIPM1_STS	57
-#define MCHP_IRQ_8042EM_OBE	58
-#define MCHP_IRQ_8042EM_IBF	59
-#define MCHP_IRQ_MAILBOX_DATA	60
-/* 61 Not connected */
-#define MCHP_IRQ_PORT80DBG0	62
-#define MCHP_IRQ_PORT80DBG1	63
-/* 64 Not connected */
-#define MCHP_IRQ_PKE_ERR	65
-#define MCHP_IRQ_PKE_END	66
-#define MCHP_IRQ_NDRNG		67
-#define MCHP_IRQ_AES		68
-#define MCHP_IRQ_HASH		69
-#define MCHP_IRQ_PECI_HOST	70
-#define MCHP_IRQ_TACH_0		71
-#define MCHP_IRQ_TACH_1		72
-#define MCHP_IRQ_TACH_2		73
-#define MCHP_IRQ_FAN0_FAIL	74
-#define MCHP_IRQ_FAN0_STALL	75
-#define MCHP_IRQ_FAN1_FAIL	76
-#define MCHP_IRQ_FAN1_STALL	77
-#define MCHP_IRQ_ADC_SNGL	78
-#define MCHP_IRQ_ADC_RPT	79
-#define MCHP_IRQ_RCID0		80
-#define MCHP_IRQ_RCID1		81
-#define MCHP_IRQ_RCID2		82
-#define MCHP_IRQ_LED0_WDT	83
-#define MCHP_IRQ_LED1_WDT	84
-#define MCHP_IRQ_LED2_WDT	85
-#define MCHP_IRQ_LED3_WDT	86
-#define MCHP_IRQ_PHOT		87
-#define MCHP_IRQ_PWRGRD0	88
-#define MCHP_IRQ_PWRGRD1	89
-#define MCHP_IRQ_LPC		90
-#define MCHP_IRQ_QMSPI0		91
-#define MCHP_IRQ_SPI0_TX	92
-#define MCHP_IRQ_SPI0_RX	93
-#define MCHP_IRQ_SPI1_TX	94
-#define MCHP_IRQ_SPI1_RX	95
-#define MCHP_IRQ_BCM0_ERR	96
-#define MCHP_IRQ_BCM0_BUSY	97
-#define MCHP_IRQ_BCM1_ERR	98
-#define MCHP_IRQ_BCM1_BUSY	99
-#define MCHP_IRQ_PS2_0		100
-#define MCHP_IRQ_PS2_1		101
-#define MCHP_IRQ_PS2_2		102
-#define MCHP_IRQ_ESPI_PC	103
-#define MCHP_IRQ_ESPI_BM1	104
-#define MCHP_IRQ_ESPI_BM2	105
-#define MCHP_IRQ_ESPI_LTR	106
-#define MCHP_IRQ_ESPI_OOB_UP	107
-#define MCHP_IRQ_ESPI_OOB_DN	108
-#define MCHP_IRQ_ESPI_FC	109
-#define MCHP_IRQ_ESPI_RESET	110
-#define MCHP_IRQ_RTOS_TIMER	111
-#define MCHP_IRQ_HTIMER0	112
-#define MCHP_IRQ_HTIMER1	113
-#define MCHP_IRQ_WEEK_ALARM	114
-#define MCHP_IRQ_SUBWEEK	115
-#define MCHP_IRQ_WEEK_SEC	116
-#define MCHP_IRQ_WEEK_SUBSEC	117
-#define MCHP_IRQ_WEEK_SYSPWR	118
-#define MCHP_IRQ_RTC		119
-#define MCHP_IRQ_RTC_ALARM	120
-#define MCHP_IRQ_VCI_OVRD_IN	121
-#define MCHP_IRQ_VCI_IN0	122
-#define MCHP_IRQ_VCI_IN1	123
-#define MCHP_IRQ_VCI_IN2	124
-#define MCHP_IRQ_VCI_IN3	125
-#define MCHP_IRQ_VCI_IN4	126
-#define MCHP_IRQ_VCI_IN5	127
-#define MCHP_IRQ_VCI_IN6	128
-#define MCHP_IRQ_PS20A_WAKE	129
-#define MCHP_IRQ_PS20B_WAKE	130
-#define MCHP_IRQ_PS21A_WAKE	131
-#define MCHP_IRQ_PS21B_WAKE	132
-#define MCHP_IRQ_PS2_2_WAKE	133
-#define MCHP_IRQ_ENVMON		134
-#define MCHP_IRQ_KSC_INT	135
-#define MCHP_IRQ_TIMER16_0	136
-#define MCHP_IRQ_TIMER16_1	137
-#define MCHP_IRQ_TIMER16_2	138
-#define MCHP_IRQ_TIMER16_3	139
-#define MCHP_IRQ_TIMER32_0	140
-#define MCHP_IRQ_TIMER32_1	141
-#define MCHP_IRQ_CNTR_TM0	142
-#define MCHP_IRQ_CNTR_TM1	143
-#define MCHP_IRQ_CNTR_TM2	144
-#define MCHP_IRQ_CNTR_TM3	145
-#define MCHP_IRQ_CCT_TMR	146
-#define MCHP_IRQ_CCT_CAP0	147
-#define MCHP_IRQ_CCT_CAP1	148
-#define MCHP_IRQ_CCT_CAP2	149
-#define MCHP_IRQ_CCT_CAP3	150
-#define MCHP_IRQ_CCT_CAP4	151
-#define MCHP_IRQ_CCT_CAP5	152
-#define MCHP_IRQ_CCT_CMP0	153
-#define MCHP_IRQ_CCT_CMP1	154
-#define MCHP_IRQ_EEPROM		155
-#define MCHP_IRQ_ESPI_VW_EN	156
-
-#define MCHP_IRQ_MAX		157
-
-#else
-#error "BUILD ERROR: CHIP_FAMILY_MEC17XX not defined!"
-#endif /* #ifdef CHIP_FAMILY_MEC17XX */
-
-#else
-#error "BUILD ERROR: CHIP_FAMILY not defined!"
-#endif /* #ifdef CHIP_FAMILY */
-
 /* Wake pin definitions, defined at board-level */
-#ifndef CONFIG_HIBERNATE_WAKE_PINS_DYNAMIC
 extern const enum gpio_signal hibernate_wake_pins[];
 extern const int hibernate_wake_pins_used;
-#else
-extern enum gpio_signal hibernate_wake_pins[];
-extern int hibernate_wake_pins_used;
-#endif
-
-
 #endif /* __CROS_EC_REGISTERS_H */
diff --git a/chip/mchp/spi.c b/chip/mchp/spi.c
index 2d5a7e9a3f..4445666790 100644
--- a/chip/mchp/spi.c
+++ b/chip/mchp/spi.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,71 +9,55 @@
 #include "console.h"
 #include "dma.h"
 #include "gpio.h"
+#include "hooks.h"
+#include "qmspi_chip.h"
 #include "registers.h"
 #include "spi.h"
+#include "spi_chip.h"
+#include "task.h"
 #include "timer.h"
 #include "util.h"
-#include "hooks.h"
-#include "task.h"
-#include "spi_chip.h"
-#include "qmspi_chip.h"
 #if defined(CONFIG_MCHP_GPSPI) && !defined(LFW)
 #include "gpspi_chip.h"
 #endif
 #include "tfdp_chip.h"
 
 #define CPUTS(outstr) cputs(CC_SPI, outstr)
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SPI, format, ##args)
 
 #define SPI_BYTE_TRANSFER_TIMEOUT_US (3 * MSEC)
 #define SPI_BYTE_TRANSFER_POLL_INTERVAL_US 100
 
-
+#if defined(CONFIG_MCHP_GPSPI) && defined(CHIP_FAMILY_MEC152X)
+#error "FORCED BUILD ERROR: MEC152X does not implement GPSPI!"
+#endif
 
 static const struct dma_option spi_rx_option[] = {
-	{
-		MCHP_DMAC_QMSPI0_RX,
-		(void *)(MCHP_QMSPI0_RX_FIFO_ADDR),
-		MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM
-	},
+	{ MCHP_DMAC_QMSPI0_RX, (void *)(MCHP_QMSPI0_RX_FIFO_ADDR),
+	  MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM },
 #if defined(CONFIG_MCHP_GPSPI) && !defined(LFW)
 #if CONFIG_MCHP_GPSPI & 0x01
-	{
-		MCHP_DMAC_SPI0_RX,
-		(void *)&MCHP_SPI_RD(0),
-		MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM
-	},
+	{ MCHP_DMAC_SPI0_RX, (void *)&MCHP_SPI_RD(0),
+	  MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM },
 #endif
 #if CONFIG_MCHP_GPSPI & 0x02
-	{
-		MCHP_DMAC_SPI1_RX,
-		(void *)&MCHP_SPI_RD(1),
-		MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM
-	},
+	{ MCHP_DMAC_SPI1_RX, (void *)&MCHP_SPI_RD(1),
+	  MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM },
 #endif
 #endif
 };
 
 static const struct dma_option spi_tx_option[] = {
-	{
-		MCHP_DMAC_QMSPI0_TX,
-		(void *)(MCHP_QMSPI0_TX_FIFO_ADDR),
-		MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM
-	},
+	{ MCHP_DMAC_QMSPI0_TX, (void *)(MCHP_QMSPI0_TX_FIFO_ADDR),
+	  MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM },
 #if defined(CONFIG_MCHP_GPSPI) && !defined(LFW)
 #if CONFIG_MCHP_GPSPI & 0x01
-	{
-		MCHP_DMAC_SPI0_TX,
-		(void *)&MCHP_SPI_TD(0),
-		MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM
-	},
+	{ MCHP_DMAC_SPI0_TX, (void *)&MCHP_SPI_TD(0),
+	  MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM },
 #endif
 #if CONFIG_MCHP_GPSPI & 0x02
-	{
-		MCHP_DMAC_SPI1_TX,
-		(void *)&MCHP_SPI_TD(1),
-		MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM
-	},
+	{ MCHP_DMAC_SPI1_TX, (void *)&MCHP_SPI_TD(1),
+	  MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM },
 #endif
 #endif
 };
@@ -129,8 +113,7 @@ static void spi_mutex_unlock(uint8_t hw_port)
  * Public SPI interface
  */
 
-const void *spi_dma_option(const struct spi_device_t *spi_device,
-				int is_tx)
+const void *spi_dma_option(const struct spi_device_t *spi_device, int is_tx)
 {
 	uint32_t n;
 
@@ -155,8 +138,8 @@ const void *spi_dma_option(const struct spi_device_t *spi_device,
 }
 
 int spi_transaction_async(const struct spi_device_t *spi_device,
-				const uint8_t *txdata, int txlen,
-				uint8_t *rxdata, int rxlen)
+			  const uint8_t *txdata, int txlen, uint8_t *rxdata,
+			  int rxlen)
 {
 	int rc;
 
@@ -167,13 +150,13 @@ int spi_transaction_async(const struct spi_device_t *spi_device,
 #if defined(CONFIG_MCHP_GPSPI) && !defined(LFW)
 	case GPSPI0_PORT:
 	case GPSPI1_PORT:
-		rc = gpspi_transaction_async(spi_device, txdata,
-				txlen, rxdata, rxlen);
+		rc = gpspi_transaction_async(spi_device, txdata, txlen, rxdata,
+					     rxlen);
 		break;
 #endif
 	case QMSPI0_PORT:
-		rc = qmspi_transaction_async(spi_device, txdata,
-				txlen, rxdata, rxlen);
+		rc = qmspi_transaction_async(spi_device, txdata, txlen, rxdata,
+					     rxlen);
 		break;
 	default:
 		rc = EC_ERROR_INVAL;
@@ -241,8 +224,8 @@ int spi_transaction_wait(const struct spi_device_t *spi_device)
  * without the overhead of DMA setup.
  */
 int spi_transaction(const struct spi_device_t *spi_device,
-		    const uint8_t *txdata, int txlen,
-		    uint8_t *rxdata, int rxlen)
+		    const uint8_t *txdata, int txlen, uint8_t *rxdata,
+		    int rxlen)
 {
 	int rc;
 
@@ -267,31 +250,26 @@ int spi_transaction(const struct spi_device_t *spi_device,
 /**
  * Enable SPI port and associated controller
  *
- * @param port Zero based index into spi_device an array of
- *             struct spi_device_t
+ * @param spi_device SPI device
  * @param enable
  * @return EC_SUCCESS or EC_ERROR_INVAL if port is unrecognized
  * @note called from common/spi_flash.c
  *
- * spi_devices[].port is defined as
+ * spi_device->port is defined as
  * bits[3:0] = controller instance
  * bits[7:4] = controller family 0 = QMSPI, 1 = GPSPI
  */
-int spi_enable(int port, int enable)
+int spi_enable(const struct spi_device_t *spi_device, int enable)
 {
 	int rc;
-	uint8_t hw_port;
-
+	uint8_t hw_port = spi_device->port;
 	rc = EC_ERROR_INVAL;
-	if (port < spi_devices_used) {
-		hw_port = spi_devices[port].port;
-		if ((hw_port & 0xF0) == QMSPI_CLASS)
-			rc = qmspi_enable(hw_port, enable);
+
+	if ((hw_port & 0xF0) == QMSPI_CLASS)
+		rc = qmspi_enable(hw_port, enable);
 #if defined(CONFIG_MCHP_GPSPI) && !defined(LFW)
-		if ((hw_port & 0xF0) == GPSPI_CLASS)
-			rc = gpspi_enable(hw_port, enable);
+	if ((hw_port & 0xF0) == GPSPI_CLASS)
+		rc = gpspi_enable(hw_port, enable);
 #endif
-	}
-
 	return rc;
 }
diff --git a/chip/mchp/spi_chip.h b/chip/mchp/spi_chip.h
index 75973e4a78..e651901ea4 100644
--- a/chip/mchp/spi_chip.h
+++ b/chip/mchp/spi_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -13,34 +13,33 @@
 #ifndef _SPI_CHIP_H
 #define _SPI_CHIP_H
 
-#include <stdint.h>
 #include <stddef.h>
+#include <stdint.h>
 
 /* struct spi_device_t */
 #include "spi.h"
 
-#define SPI_DMA_OPTION_RD	0
-#define SPI_DMA_OPTION_WR	1
+#define SPI_DMA_OPTION_RD 0
+#define SPI_DMA_OPTION_WR 1
 
 /*
  * bits[3:0] = controller instance
  * bits[7:4] = controller family
  * 0 = QMSPI, 1 = GPSPI
  */
-#define QMSPI0_PORT	0x00
-#define GPSPI0_PORT	0x10
-#define GPSPI1_PORT	0x11
+#define QMSPI0_PORT 0x00
+#define GPSPI0_PORT 0x10
+#define GPSPI1_PORT 0x11
 
+#define QMSPI_CLASS0 0
+#define GPSPI_CLASS0 1
 
-#define QMSPI_CLASS0	0
-#define GPSPI_CLASS0	1
+#define QMSPI_CLASS (0 << 4)
+#define GPSPI_CLASS BIT(4)
 
-#define QMSPI_CLASS	(0 << 4)
-#define GPSPI_CLASS	BIT(4)
-
-#define QMSPI_CTRL0	0
-#define GPSPI_CTRL0	0
-#define GPSPI_CTRL1	1
+#define QMSPI_CTRL0 0
+#define GPSPI_CTRL0 0
+#define GPSPI_CTRL1 1
 
 /*
  * Encode zero based controller class and instance values
@@ -51,10 +50,8 @@
 /*
  * helper to return pointer to QMSPI or GPSPI struct dma_option
  */
-const void *spi_dma_option(const struct spi_device_t *spi_device,
-				int is_tx);
+const void *spi_dma_option(const struct spi_device_t *spi_device, int is_tx);
 
 #endif /* #ifndef _QMSPI_CHIP_H */
 /**   @}
  */
-
diff --git a/chip/mchp/system.c b/chip/mchp/system.c
index 1d152f0b79..65470c43b9 100644
--- a/chip/mchp/system.c
+++ b/chip/mchp/system.c
@@ -1,81 +1,103 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* System module for Chrome EC : MCHP hardware specific implementation */
 
-#include <stdnoreturn.h>
-
 #include "clock.h"
-#include "common.h"
+#include "clock_chip.h"
+#include "common.h" /* includes config.h and board.h */
 #include "console.h"
 #include "cpu.h"
 #include "gpio.h"
+#include "hooks.h"
 #include "host_command.h"
+#include "lpc_chip.h"
 #include "registers.h"
 #include "shared_mem.h"
+#include "spi.h"
 #include "system.h"
-#include "hooks.h"
 #include "task.h"
+#include "tfdp_chip.h"
 #include "timer.h"
 #include "util.h"
-#include "spi.h"
-#include "clock_chip.h"
-#include "lpc_chip.h"
-#include "tfdp_chip.h"
 
+#include <stdnoreturn.h>
 
 #define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-
+#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args)
 
-/* Indices for hibernate data registers (RAM backed by VBAT) */
+/* Index values for hibernate data registers (RAM backed by VBAT) */
 enum hibdata_index {
-	HIBDATA_INDEX_SCRATCHPAD = 0,    /* General-purpose scratchpad */
+	HIBDATA_INDEX_SCRATCHPAD = 0, /* General-purpose scratch pad */
 	HIBDATA_INDEX_SAVED_RESET_FLAGS, /* Saved reset flags */
-	HIBDATA_INDEX_PD0,		/* USB-PD0 saved port state */
-	HIBDATA_INDEX_PD1,		/* USB-PD1 saved port state */
-	HIBDATA_INDEX_PD2,		/* USB-PD2 saved port state */
+	HIBDATA_INDEX_PD0, /* USB-PD0 saved port state */
+	HIBDATA_INDEX_PD1, /* USB-PD1 saved port state */
+	HIBDATA_INDEX_PD2, /* USB-PD2 saved port state */
 };
 
+/*
+ * Voltage rail configuration
+ * MEC172x VTR1 is 3.3V only, VTR2 is auto-detected 3.3 or 1.8V, and
+ * VTR3 is always 1.8V.
+ * MEC170x and MEC152x require manual selection of VTR3 for 1.8 or 3.3V.
+ * The eSPI pins are on VTR3 and require 1.8V
+ */
+#ifdef CHIP_FAMILY_MEC172X
+static void vtr3_voltage_select(int use18v)
+{
+	(void)use18v;
+}
+#else
+static void vtr3_voltage_select(int use18v)
+{
+	if (use18v)
+		MCHP_EC_GPIO_BANK_PWR |= MCHP_EC_GPIO_BANK_PWR_VTR3_18;
+	else
+		MCHP_EC_GPIO_BANK_PWR &= ~(MCHP_EC_GPIO_BANK_PWR_VTR3_18);
+}
+#endif
+
+/*
+ * The current logic will set EC_RESET_FLAG_RESET_PIN flag
+ * even if the reset was caused by WDT. MEC170x/MEC152x HW RESET_SYS
+ * status goes active for any of the following:
+ *	RESET_VTR: power rail change
+ *	WDT Event: WDT timed out
+ *	FW triggered chip reset: SYSRESETREQ or PCR sys reset bit
+ * The code does check WDT status in the VBAT PFR register.
+ * Is it correct to report both EC_RESET_FLAG_RESET_PIN and
+ * EC_RESET_FLAG_WATCHDOG on a WDT only reset?
+ */
 static void check_reset_cause(void)
 {
 	uint32_t status = MCHP_VBAT_STS;
 	uint32_t flags = 0;
 	uint32_t rst_sts = MCHP_PCR_PWR_RST_STS &
-				(MCHP_PWR_RST_STS_VTR |
-				MCHP_PWR_RST_STS_VBAT);
-
-	trace12(0, MEC, 0,
-		"check_reset_cause: VBAT_PFR = 0x%08X  PCR PWRST = 0x%08X",
-		status, rst_sts);
+			   (MCHP_PWR_RST_STS_SYS | MCHP_PWR_RST_STS_VBAT);
 
 	/* Clear the reset causes now that we've read them */
 	MCHP_VBAT_STS |= status;
 	MCHP_PCR_PWR_RST_STS |= rst_sts;
 
-	trace0(0, MEC, 0, "check_reset_cause: after clear");
-	trace11(0, MEC, 0, "  VBAT_PFR  = 0x%08X", MCHP_VBAT_STS);
-	trace11(0, MEC, 0, "  PCR PWRST = 0x%08X", MCHP_PCR_PWR_RST_STS);
-
 	/*
-	 * BIT[6] determine VTR reset
+	 * BIT[6] indicates RESET_SYS asserted.
+	 * RESET_SYS will assert on VTR reset, WDT reset, or
+	 * firmware triggering a reset using Cortex-M4 SYSRESETREQ
+	 * or MCHP PCR system reset register.
 	 */
-	if (rst_sts & MCHP_PWR_RST_STS_VTR)
+	if (rst_sts & MCHP_PWR_RST_STS_SYS)
 		flags |= EC_RESET_FLAG_RESET_PIN;
 
-
 	flags |= chip_read_reset_flags();
 	chip_save_reset_flags(0);
 
-	if ((status & MCHP_VBAT_STS_WDT) && !(flags & (EC_RESET_FLAG_SOFT |
-					    EC_RESET_FLAG_HARD |
-					    EC_RESET_FLAG_HIBERNATE)))
+	if ((status & MCHP_VBAT_STS_WDT) &&
+	    !(flags & (EC_RESET_FLAG_SOFT | EC_RESET_FLAG_HARD |
+		       EC_RESET_FLAG_HIBERNATE)))
 		flags |= EC_RESET_FLAG_WATCHDOG;
 
-	trace11(0, MEC, 0, "check_reset_cause: EC reset flags = 0x%08x", flags);
-
 	system_set_reset_flags(flags);
 }
 
@@ -90,10 +112,10 @@ int system_is_reboot_warm(void)
 	reset_flags = system_get_reset_flags();
 
 	if ((reset_flags & EC_RESET_FLAG_RESET_PIN) ||
-		(reset_flags & EC_RESET_FLAG_POWER_ON) ||
-		(reset_flags & EC_RESET_FLAG_WATCHDOG) ||
-		(reset_flags & EC_RESET_FLAG_HARD) ||
-		(reset_flags & EC_RESET_FLAG_SOFT))
+	    (reset_flags & EC_RESET_FLAG_POWER_ON) ||
+	    (reset_flags & EC_RESET_FLAG_WATCHDOG) ||
+	    (reset_flags & EC_RESET_FLAG_HARD) ||
+	    (reset_flags & EC_RESET_FLAG_SOFT))
 		return 0;
 	else
 		return 1;
@@ -101,31 +123,25 @@ int system_is_reboot_warm(void)
 
 /*
  * Sleep unused blocks to reduce power.
- * Drivers/modules will unsleep their blocks.
+ * Drivers/modules will clear PCR sleep enables for their blocks.
  * Keep sleep enables cleared for required blocks:
  * ECIA, PMC, CPU, ECS and optionally JTAG.
  * SLEEP_ALL feature will set these upon sleep entry.
- * Based on CONFIG_CHIPSET_DEBUG enable or disable JTAG.
- * JTAG mode (4-pin or 2-pin SWD + 1-pin SWV) was set
- * by Boot-ROM. We can override Boot-ROM JTAG mode
- * using
- * CONFIG_MCHP_JTAG_MODE
+ * Based on CONFIG_CHIPSET_DEBUG enable or disable ARM SWD
+ * 2-pin JTAG mode.
  */
 static void chip_periph_sleep_control(void)
 {
 	uint32_t d;
 
 	d = MCHP_PCR_SLP_EN0_SLEEP;
-#ifdef CONFIG_CHIPSET_DEBUG
-	d &= ~(MCHP_PCR_SLP_EN0_JTAG);
-#ifdef CONFIG_MCHP_JTAG_MODE
-	MCHP_EC_JTAG_EN = CONFIG_MCHP_JTAG_MODE;
-#else
-	MCHP_EC_JTAG_EN |= 0x01;
-#endif
-#else
-	MCHP_EC_JTAG_EN &= ~0x01;
-#endif
+
+	if (IS_ENABLED(CONFIG_CHIPSET_DEBUG)) {
+		d &= ~(MCHP_PCR_SLP_EN0_JTAG);
+		MCHP_EC_JTAG_EN = MCHP_JTAG_MODE_SWD | MCHP_JTAG_ENABLE;
+	} else
+		MCHP_EC_JTAG_EN &= ~(MCHP_JTAG_ENABLE);
+
 	MCHP_PCR_SLP_EN0 = d;
 	MCHP_PCR_SLP_EN1 = MCHP_PCR_SLP_EN1_UNUSED_BLOCKS;
 	MCHP_PCR_SLP_EN2 = MCHP_PCR_SLP_EN2_SLEEP;
@@ -136,30 +152,15 @@ static void chip_periph_sleep_control(void)
 #ifdef CONFIG_CHIP_PRE_INIT
 void chip_pre_init(void)
 {
-#ifdef CONFIG_MCHP_TFDP
-	uint8_t imgtype;
-#endif
 	chip_periph_sleep_control();
 
-#ifdef CONFIG_MCHP_TFDP
-	/*
-	 * MCHP Enable TFDP for fast debug messages
-	 * If not defined then traceN() and TRACEN() macros are empty
-	 */
-	tfdp_power(1);
-	tfdp_enable(1, 1);
-	imgtype = MCHP_VBAT_RAM(MCHP_IMAGETYPE_IDX);
-	CPRINTS("chip_pre_init: Image type = 0x%02x", imgtype);
-	trace1(0, MEC, 0,
-		"chip_pre_init: Image type = 0x%02x", imgtype);
-
-	trace11(0, MEC, 0,
-		"chip_pre_init: MCHP_VBAT_STS = 0x%0x",
-		MCHP_VBAT_STS);
-	trace11(0, MEC, 0,
-		"chip_pre_init: MCHP_PCR_PWR_RST_STS = 0x%0x",
-		MCHP_VBAT_STS);
-#endif
+	if (IS_ENABLED(CONFIG_MCHP_TFDP)) {
+		/* MCHP Enable TFDP for fast debug messages */
+		tfdp_power(1);
+		tfdp_enable(1, 1);
+		CPRINTS("chip_pre_init: Image type = 0x%02x",
+			MCHP_VBAT_RAM(MCHP_IMAGETYPE_IDX));
+	}
 }
 #endif
 
@@ -170,16 +171,17 @@ void system_pre_init(void)
 	 * Signals bus fault to Cortex-M4 core if an address presented
 	 * to AHB is not claimed by any HW block.
 	 */
-	MCHP_EC_AHB_ERR = 0;	/* write any value to clear */
+	MCHP_EC_AHB_ERR = 0; /* write any value to clear */
 	MCHP_EC_AHB_ERR_EN = 0; /* enable capture of address on error */
 
-#ifdef CONFIG_HOSTCMD_ESPI
-	MCHP_EC_GPIO_BANK_PWR |= MCHP_EC_GPIO_BANK_PWR_VTR3_18;
-#endif
+	/* Manual voltage selection only required for MEC170x and MEC152x */
+	if (IS_ENABLED(CONFIG_HOST_INTERFACE_ESPI))
+		vtr3_voltage_select(1);
+	else
+		vtr3_voltage_select(0);
 
-#ifndef CONFIG_CHIP_PRE_INIT
-	chip_periph_sleep_control();
-#endif
+	if (!IS_ENABLED(CONFIG_CHIP_PRE_INIT))
+		chip_periph_sleep_control();
 
 	/* Enable direct NVIC */
 	MCHP_EC_INT_CTRL |= 1;
@@ -197,9 +199,9 @@ void system_pre_init(void)
 	 * NOTE: GIRQ22 wake for AHB peripherals not processor.
 	 */
 	MCHP_INT_BLK_DIS = 0xfffffffful;
-	MCHP_INT_BLK_EN = (0x1Ful << 8) + (0x07ul << 24);
+	MCHP_INT_BLK_EN = MCHP_INT_AGGR_ONLY_BITMAP;
 
-	spi_enable(CONFIG_SPI_FLASH_PORT, 1);
+	spi_enable(SPI_FLASH_DEVICE, 1);
 }
 
 uint32_t chip_read_reset_flags(void)
@@ -216,13 +218,13 @@ noreturn void _system_reset(int flags, int wake_from_hibernate)
 {
 	uint32_t save_flags = 0;
 
+	/* DEBUG */
+	CPRINTS("MEC system reset: flag = 0x%08x wake = %d", flags,
+		wake_from_hibernate);
+
 	/* Disable interrupts to avoid task swaps during reboot */
 	interrupt_disable();
 
-	trace12(0, MEC, 0,
-		"_system_reset: flags=0x%08X  wake_from_hibernate=%d",
-		flags, wake_from_hibernate);
-
 	/* Save current reset reasons if necessary */
 	if (flags & SYSTEM_RESET_PRESERVE_FLAGS)
 		save_flags = system_get_reset_flags() | EC_RESET_FLAG_PRESERVED;
@@ -239,15 +241,12 @@ noreturn void _system_reset(int flags, int wake_from_hibernate)
 
 	chip_save_reset_flags(save_flags);
 
-	trace11(0, MEC, 0, "_system_reset: save_flags=0x%08X", save_flags);
-
 	/*
 	 * Trigger chip reset
 	 */
-#if defined(CONFIG_CHIPSET_DEBUG)
-#else
-	MCHP_PCR_SYS_RST |= MCHP_PCR_SYS_SOFT_RESET;
-#endif
+	if (!IS_ENABLED(CONFIG_DEBUG_BRINGUP))
+		MCHP_PCR_SYS_RST |= MCHP_PCR_SYS_SOFT_RESET;
+
 	/* Spin and wait for reboot; should never return */
 	while (1)
 		;
@@ -263,6 +262,7 @@ const char *system_get_chip_vendor(void)
 	return "mchp";
 }
 
+#ifdef CHIP_VARIANT_MEC1701
 /*
  * MEC1701H Chip ID = 0x2D
  *              Rev = 0x82
@@ -276,6 +276,79 @@ const char *system_get_chip_name(void)
 		return "unknown";
 	}
 }
+#endif
+
+#ifdef CHIP_FAMILY_MEC152X
+/*
+ * MEC152x family implements chip ID as a 32-bit
+ * register where:
+ * b[31:16] = 16-bit Device ID
+ * b[15:8] = 8-bit Sub ID
+ * b[7:0] = Revision
+ *
+ * MEC1521-128 WFBGA 0023_33_xxh
+ * MEC1521-144 WFBGA 0023_34_xxh
+ * MEC1523-144 WFBGA 0023_B4_xxh
+ * MEC1527-144 WFBGA 0023_74_xxh
+ * MEC1527-128 WFBGA 0023_73_xxh
+ */
+const char *system_get_chip_name(void)
+{
+	switch (MCHP_CHIP_DEVRID32 & ~(MCHP_CHIP_REV_MASK)) {
+	case 0x00201400: /* 144 pin rev A? */
+		return "mec1503_revA";
+	case 0x00203400: /* 144 pin */
+		return "mec1501";
+	case 0x00207400: /* 144 pin */
+		return "mec1507";
+	case 0x00208400: /* 144 pin */
+		return "mec1503";
+	case 0x00233300: /* 128 pin */
+	case 0x00233400: /* 144 pin */
+		return "mec1521";
+	case 0x0023B400: /* 144 pin */
+		return "mec1523";
+	case 0x00237300: /* 128 pin */
+	case 0x00237400: /* 144 pin */
+		return "mec1527";
+	default:
+		return "unknown";
+	}
+}
+#endif
+
+#ifdef CHIP_FAMILY_MEC172X
+/*
+ * MEC172x family implements chip ID as a 32-bit
+ * register where:
+ * b[31:16] = 16-bit Device ID
+ * b[15:8] = 8-bit Sub ID
+ * b[7:0] = Revision
+ *
+ * MEC1723N-B0-I/SZ 144 pin: 0x0022_34_xx
+ * MEC1727N-B0-I/SZ 144 pin: 0x0022_74_xx
+ * MEC1721N-B0-I/LJ 176 pin: 0x0022_27_xx
+ * MEC1723N-B0-I/LJ 176 pin: 0x0022_37_xx
+ * MEC1727N-B0-I/LJ 176 pin: 0x0022_77_xx
+ */
+const char *system_get_chip_name(void)
+{
+	switch (MCHP_CHIP_DEVRID32 & ~(MCHP_CHIP_REV_MASK)) {
+	case 0x00223400:
+		return "MEC1723NSZ";
+	case 0x00227400:
+		return "MEC1727NSZ";
+	case 0x00222700:
+		return "MEC1721NLJ";
+	case 0x00223700:
+		return "MEC1723NLJ";
+	case 0x00227700:
+		return "MEC1727NLJ";
+	default:
+		return "unknown";
+	}
+}
+#endif
 
 static char to_hex(int x)
 {
@@ -337,21 +410,62 @@ int system_set_scratchpad(uint32_t value)
 	return EC_SUCCESS;
 }
 
-uint32_t system_get_scratchpad(void)
+int system_get_scratchpad(uint32_t *value)
+{
+	*value = MCHP_VBAT_RAM(HIBDATA_INDEX_SCRATCHPAD);
+	return EC_SUCCESS;
+}
+
+/*
+ * Local function to disable clocks in the chip's host interface
+ * so the chip can enter deep sleep. Only MEC170X has LPC.
+ * MEC152x and MEC172x only include eSPI and SPI host interfaces.
+ * NOTE: we do it this way because the LPC registers are only
+ * defined for MEC170x and the IS_ENABLED() macro causes the
+ * compiler to evaluate both true and false code paths.
+ */
+#if defined(CONFIG_HOST_INTERFACE_ESPI)
+static void disable_host_ifc_clocks(void)
+{
+	MCHP_ESPI_ACTIVATE &= ~0x01;
+}
+#else
+static void disable_host_ifc_clocks(void)
+{
+#ifdef CHIP_FAMILY_MEC170X
+	MCHP_LPC_ACT &= ~0x1;
+#endif
+}
+#endif
+
+/*
+ * Called when hibernation timer is not used in deep sleep.
+ * Switch 32 KHz clock logic from external 32KHz input to
+ * internal silicon OSC.
+ * NOTE: MEC172x auto-switches from external source to silicon
+ * oscillator.
+ */
+#ifdef CHIP_FAMILY_MEC172X
+static void switch_32k_pin2sil(void)
+{
+}
+#else
+static void switch_32k_pin2sil(void)
 {
-	return MCHP_VBAT_RAM(HIBDATA_INDEX_SCRATCHPAD);
+	MCHP_VBAT_CE &= ~(MCHP_VBAT_CE_32K_DOMAIN_32KHZ_IN_PIN);
 }
+#endif
 
 void system_hibernate(uint32_t seconds, uint32_t microseconds)
 {
 	int i;
 
-#ifdef CONFIG_HOSTCMD_PD
-	/* Inform the PD MCU that we are going to hibernate. */
-	host_command_pd_request_hibernate();
-	/* Wait to ensure exchange with PD before hibernating. */
-	msleep(100);
-#endif
+	if (IS_ENABLED(CONFIG_HOSTCMD_PD)) {
+		/* Inform the PD MCU that we are going to hibernate. */
+		host_command_pd_request_hibernate();
+		/* Wait to ensure exchange with PD before hibernating. */
+		msleep(100);
+	}
 
 	cflush();
 
@@ -367,26 +481,24 @@ void system_hibernate(uint32_t seconds, uint32_t microseconds)
 
 	for (i = MCHP_INT_GIRQ_FIRST; i <= MCHP_INT_GIRQ_LAST; ++i) {
 		MCHP_INT_DISABLE(i) = 0xffffffff;
-		MCHP_INT_SOURCE(i)  = 0xffffffff;
+		MCHP_INT_SOURCE(i) = 0xffffffff;
 	}
 
 	/* Disable UART */
 	MCHP_UART_ACT(0) &= ~0x1;
-#ifdef CONFIG_HOSTCMD_ESPI
-	MCHP_ESPI_ACTIVATE &= ~0x01;
-#else
-	MCHP_LPC_ACT &= ~0x1;
-#endif
+
+	disable_host_ifc_clocks();
+
 	/* Disable JTAG */
 	MCHP_EC_JTAG_EN &= ~1;
 
 	/* Stop watchdog */
-	MCHP_WDG_CTL &= ~1;
+	MCHP_WDG_CTL &= ~(MCHP_WDT_CTL_ENABLE);
 
 	/* Stop timers */
 	MCHP_TMR32_CTL(0) &= ~1;
 	MCHP_TMR32_CTL(1) &= ~1;
-	for (i = 0; i < MCHP_TMR16_MAX; i++)
+	for (i = 0; i < MCHP_TMR16_INSTANCES; i++)
 		MCHP_TMR16_CTL(i) &= ~1;
 
 	/* Power down ADC */
@@ -423,10 +535,8 @@ void system_hibernate(uint32_t seconds, uint32_t microseconds)
 		htimer_init();
 		system_set_htimer_alarm(seconds, microseconds);
 		interrupt_enable();
-	} else {
-		/* Not using hibernation timer. Disable 32KHz clock */
-		MCHP_VBAT_CE &= ~0x2;
-	}
+	} else
+		switch_32k_pin2sil();
 
 	/*
 	 * Set sleep state
@@ -437,14 +547,12 @@ void system_hibernate(uint32_t seconds, uint32_t microseconds)
 	MCHP_PCR_SYS_SLP_CTL = MCHP_PCR_SYS_SLP_ALL;
 
 	asm("dsb");
-	asm("wfi");
+	cpu_enter_suspend_mode();
 	asm("isb");
 	asm("nop");
 
-	/* Use 48MHz clock to speed through wake-up */
-	MCHP_PCR_PROC_CLK_CTL = 1;
-
-	trace0(0, SYS, 0, "Wake from hibernate: _system_reset[0,1]");
+	/* Use fastest clock to speed through wake-up */
+	MCHP_PCR_PROC_CLK_CTL = MCHP_PCR_CLK_CTL_FASTEST;
 
 	/* Reboot */
 	_system_reset(0, 1);
@@ -454,7 +562,7 @@ void system_hibernate(uint32_t seconds, uint32_t microseconds)
 		;
 }
 
-void htimer_interrupt(void)
+static void htimer_interrupt(void)
 {
 	/* Time to wake up */
 }
@@ -467,15 +575,14 @@ enum ec_image system_get_shrspi_image_copy(void)
 
 uint32_t system_get_lfw_address(void)
 {
-	uint32_t * const lfw_vector =
-		(uint32_t * const)CONFIG_PROGRAM_MEMORY_BASE;
+	uint32_t *const lfw_vector =
+		(uint32_t *const)CONFIG_PROGRAM_MEMORY_BASE;
 
 	return *(lfw_vector + 1);
 }
 
 void system_set_image_copy(enum ec_image copy)
 {
-	MCHP_VBAT_RAM(MCHP_IMAGETYPE_IDX) = (copy == EC_IMAGE_RW) ?
-				EC_IMAGE_RW : EC_IMAGE_RO;
+	MCHP_VBAT_RAM(MCHP_IMAGETYPE_IDX) =
+		(copy == EC_IMAGE_RW) ? EC_IMAGE_RW : EC_IMAGE_RO;
 }
-
diff --git a/chip/mchp/tfdp.c b/chip/mchp/tfdp.c
index b4368b46a8..eb9b903cb5 100644
--- a/chip/mchp/tfdp.c
+++ b/chip/mchp/tfdp.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,12 +17,11 @@
 
 #ifdef CONFIG_MCHP_TFDP
 
-
 static uint32_t get_disable_intr(void)
 {
 	uint32_t m;
 
-	__asm__ __volatile__ ("mrs %0, primask;cpsid i" : "=r" (m));
+	__asm__ __volatile__("mrs %0, primask;cpsid i" : "=r"(m));
 
 	return m;
 }
@@ -30,10 +29,9 @@ static uint32_t get_disable_intr(void)
 static void restore_intr(uint32_t m)
 {
 	if (!m)
-		__asm__ __volatile__ ("cpsie i" : : : "memory");
+		__asm__ __volatile__("cpsie i" : : : "memory");
 }
 
-
 /**
  * tfdp_power - Gate clocks On/Off to TFDP block when idle
  *
@@ -48,7 +46,6 @@ void tfdp_power(uint8_t pwr_on)
 		MCHP_PCR_SLP_EN_DEV(MCHP_PCR_TFDP);
 }
 
-
 /**
  * tfdp_enable - Init Trace FIFO Data Port
  * @param uint8_t non-zero=enable TFDP, false=disable TFDP
@@ -57,8 +54,8 @@ void tfdp_power(uint8_t pwr_on)
  * Else GPIO170/171 set to GPIO input, internal pull-up enabled.
  * @note -
  */
-#define MCHP_TFDP_DATA	REG8(MCHP_TFDP_BASE + 0x00)
-#define MCHP_TFDP_CTRL	REG8(MCHP_TFDP_BASE + 0x04)
+#define MCHP_TFDP_DATA REG8(MCHP_TFDP_BASE + 0x00)
+#define MCHP_TFDP_CTRL REG8(MCHP_TFDP_BASE + 0x04)
 
 void tfdp_enable(uint8_t en, uint8_t pin_cfg)
 {
@@ -73,7 +70,6 @@ void tfdp_enable(uint8_t en, uint8_t pin_cfg)
 	}
 } /* end tfdp_enable() */
 
-
 /**
  * TFDPTrace0 - TRACE0: transmit 16-bit trace number lsb first
  * over TFDP.
@@ -106,7 +102,6 @@ void TFDPTrace0(uint16_t nbr)
 #endif
 }
 
-
 /**
  * TRDPTrace1 - TRACE1: transmit 16-bit trace number lsb first
  * and 16-bit data lsb first over TFDP.
@@ -144,7 +139,6 @@ void TFDPTrace1(uint16_t nbr, uint32_t p1)
 #endif
 }
 
-
 /**
  * TFDPTrace2 - TRACE2: transmit 16-bit trace number lsb first
  * and two 16-bit data parameters lsb first over TFDP.
@@ -187,7 +181,6 @@ void TFDPTrace2(uint16_t nbr, uint32_t p1, uint32_t p2)
 #endif
 }
 
-
 /**
  * TFDPTrace3 - TRACE3: transmit 16-bit trace number lsb first
  * and three 16-bit data parameters lsb first over TFDP.
@@ -203,8 +196,7 @@ void TFDPTrace2(uint16_t nbr, uint32_t p1, uint32_t p2)
  *       interrupts for critical section. These may use
  *       priviledged instructions.
  */
-void TFDPTrace3(uint16_t nbr, uint32_t p1,
-		uint32_t p2, uint32_t p3)
+void TFDPTrace3(uint16_t nbr, uint32_t p1, uint32_t p2, uint32_t p3)
 {
 #ifdef MCHP_TRACE_MASK_IRQ
 	uint32_t prim;
@@ -236,7 +228,6 @@ void TFDPTrace3(uint16_t nbr, uint32_t p1,
 #endif
 }
 
-
 /**
  * TFDPTrace4 - TRACE3: transmit 16-bit trace number lsb first
  * and four 16-bit data parameters lsb first over TFDP.
@@ -253,8 +244,8 @@ void TFDPTrace3(uint16_t nbr, uint32_t p1,
  *       interrupts for critical section. These may use
  *       priviledged instructions.
  */
-void TFDPTrace4(uint16_t nbr, uint32_t p1, uint32_t p2,
-		 uint32_t p3, uint32_t p4)
+void TFDPTrace4(uint16_t nbr, uint32_t p1, uint32_t p2, uint32_t p3,
+		uint32_t p4)
 {
 #ifdef MCHP_TRACE_MASK_IRQ
 	uint32_t prim;
@@ -290,7 +281,6 @@ void TFDPTrace4(uint16_t nbr, uint32_t p1, uint32_t p2,
 #endif
 }
 
-
 /**
  *  TFDPTrace11 - Transmit one 32-bit data item over TFDP
  *
@@ -327,7 +317,6 @@ void TFDPTrace11(uint16_t nbr, uint32_t p1)
 #endif
 }
 
-
 /**
  *  TFDPTrace12 - Transmit two 32-bit data items over TFDP
  *
@@ -383,8 +372,7 @@ void TFDPTrace12(uint16_t nbr, uint32_t p1, uint32_t p2)
  *  @param uint32_t p3 32-bit data3 to be transmitted
  *
  */
-void TFDPTrace13(uint16_t nbr, uint32_t p1,
-		 uint32_t p2, uint32_t p3)
+void TFDPTrace13(uint16_t nbr, uint32_t p1, uint32_t p2, uint32_t p3)
 {
 #ifdef MCHP_TRACE_MASK_IRQ
 	uint32_t prim;
@@ -438,8 +426,8 @@ void TFDPTrace13(uint16_t nbr, uint32_t p1,
  *  @param uint32_t p3 32-bit data3 to be transmitted
  *  @param uint32_t p4 32-bit data4 to be transmitted
  */
-void TFDPTrace14(uint16_t nbr, uint32_t p1, uint32_t p2,
-		 uint32_t p3, uint32_t p4)
+void TFDPTrace14(uint16_t nbr, uint32_t p1, uint32_t p2, uint32_t p3,
+		 uint32_t p4)
 {
 #ifdef MCHP_TRACE_MASK_IRQ
 	uint32_t prim;
@@ -493,7 +481,6 @@ void TFDPTrace14(uint16_t nbr, uint32_t p1, uint32_t p2,
 
 #endif /* #ifdef CONFIG_MCHP_TFDP */
 
-
 /* end tfdp.c */
 /**   @}
  */
diff --git a/chip/mchp/tfdp_chip.h b/chip/mchp/tfdp_chip.h
index 64d4d0b77e..894bfaf876 100644
--- a/chip/mchp/tfdp_chip.h
+++ b/chip/mchp/tfdp_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,7 +13,6 @@
 
 #include <stdint.h>
 
-
 #ifdef CONFIG_MCHP_TFDP
 
 #undef TRACE0
@@ -35,19 +34,19 @@
 #undef trace13
 #undef trace14
 
-#define MCHP_TFDP_BASE_ADDR	(0x40008c00ul)
+#define MCHP_TFDP_BASE_ADDR (0x40008c00ul)
 
-#define TFDP_FRAME_START   (0xFD)
+#define TFDP_FRAME_START (0xFD)
 
-#define TFDP_POWER_ON   (1u)
-#define TFDP_POWER_OFF  (0u)
+#define TFDP_POWER_ON (1u)
+#define TFDP_POWER_OFF (0u)
 
-#define TFDP_ENABLE         (1u)
-#define TFDP_DISABLE        (0u)
-#define TFDP_CFG_PINS       (1u)
-#define TFDP_NO_CFG_PINS    (0u)
+#define TFDP_ENABLE (1u)
+#define TFDP_DISABLE (0u)
+#define TFDP_CFG_PINS (1u)
+#define TFDP_NO_CFG_PINS (0u)
 
-#define  MCHP_TRACE_MASK_IRQ
+#define MCHP_TRACE_MASK_IRQ
 
 #define TFDP_DELAY()
 
@@ -59,18 +58,15 @@ void tfdp_power(uint8_t pwr_on);
 void tfdp_enable(uint8_t en, uint8_t pin_cfg);
 void TFDPTrace0(uint16_t nbr);
 void TFDPTrace1(uint16_t nbr, uint32_t p1);
-void TFDPTrace2(uint16_t nbr, uint32_t p1,
-		uint32_t p2);
-void TFDPTrace3(uint16_t nbr, uint32_t p1,
-		uint32_t p2, uint32_t p3);
-void TFDPTrace4(uint16_t nbr, uint32_t p1, uint32_t p2,
-		uint32_t p3, uint32_t p4);
+void TFDPTrace2(uint16_t nbr, uint32_t p1, uint32_t p2);
+void TFDPTrace3(uint16_t nbr, uint32_t p1, uint32_t p2, uint32_t p3);
+void TFDPTrace4(uint16_t nbr, uint32_t p1, uint32_t p2, uint32_t p3,
+		uint32_t p4);
 void TFDPTrace11(uint16_t nbr, uint32_t p1);
 void TFDPTrace12(uint16_t nbr, uint32_t p1, uint32_t p2);
-void TFDPTrace13(uint16_t nbr, uint32_t p1, uint32_t p2,
-		 uint32_t p3);
-void TFDPTrace14(uint16_t nbr, uint32_t p1, uint32_t p2,
-		 uint32_t p3, uint32_t p4);
+void TFDPTrace13(uint16_t nbr, uint32_t p1, uint32_t p2, uint32_t p3);
+void TFDPTrace14(uint16_t nbr, uint32_t p1, uint32_t p2, uint32_t p3,
+		 uint32_t p4);
 
 #ifdef __cplusplus
 }
@@ -80,15 +76,13 @@ void TFDPTrace14(uint16_t nbr, uint32_t p1, uint32_t p2,
 #define TRACE1(nbr, cat, b, str, p1) TFDPTrace1(nbr, p1)
 #define TRACE2(nbr, cat, b, str, p1, p2) TFDPTrace2(nbr, p1, p2)
 #define TRACE3(nbr, cat, b, str, p1, p2, p3) TFDPTrace3(nbr, p1, p2, p3)
-#define TRACE4(nbr, cat, b, str, p1, p2, p3, p4) TFDPTrace4(nbr, p1, p2, \
-	p3, p4)
+#define TRACE4(nbr, cat, b, str, p1, p2, p3, p4) TFDPTrace4(nbr, p1, p2, p3, p4)
 #define TRACE11(nbr, cat, b, str, p1) TFDPTrace11(nbr, p1)
 #define TRACE12(nbr, cat, b, str, p1, p2) TFDPTrace12(nbr, p1, p2)
 #define TRACE13(nbr, cat, b, str, p1, p2, p3) TFDPTrace13(nbr, p1, p2, p3)
 #define TRACE14(nbr, cat, b, str, p1, p2, p3, p4) \
 	TFDPTrace14(nbr, p1, p2, p3, p4)
 
-
 #else /* #ifdef MCHP_TRACE */
 
 /* !!! To prevent compiler warnings of unused parameters,
diff --git a/chip/mchp/uart.c b/chip/mchp/uart.c
index 0f8bd62db8..59ea3e1c35 100644
--- a/chip/mchp/uart.c
+++ b/chip/mchp/uart.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,12 +13,47 @@
 #include "registers.h"
 #include "system.h"
 #include "task.h"
+#include "tfdp_chip.h"
 #include "uart.h"
 #include "util.h"
-#include "tfdp_chip.h"
 
 #define TX_FIFO_SIZE 16
 
+BUILD_ASSERT((CONFIG_UART_CONSOLE >= 0) &&
+	     (CONFIG_UART_CONSOLE < MCHP_UART_INSTANCES));
+
+#if CONFIG_UART_CONSOLE == 2
+
+#define UART_IRQ MCHP_IRQ_UART2
+#define UART_IRQ_BIT MCHP_UART2_GIRQ_BIT
+#define UART_PCR MCHP_PCR_UART2
+#define GPIO_UART_RX GPIO_UART2_RX
+/* MEC152x only. UART2 RX Pin = GPIO 0145 GIRQ08 bit[5] */
+#define UART_RX_PIN_GIRQ 8
+#define UART_RX_PIN_BIT BIT(5)
+
+#elif CONFIG_UART_CONSOLE == 1
+
+#define UART_IRQ MCHP_IRQ_UART1
+#define UART_IRQ_BIT MCHP_UART1_GIRQ_BIT
+#define UART_PCR MCHP_PCR_UART1
+#define GPIO_UART_RX GPIO_UART1_RX
+/* MEC152x and MEC170x UART1 RX Pin = GPIO 0171. GIRQ08 bit[25] */
+#define UART_RX_PIN_GIRQ 8
+#define UART_RX_PIN_BIT BIT(25)
+
+#else
+
+#define UART_IRQ MCHP_IRQ_UART0
+#define UART_IRQ_BIT MCHP_UART0_GIRQ_BIT
+#define UART_PCR MCHP_PCR_UART0
+#define GPIO_UART_RX GPIO_UART0_RX
+/* MEC152x and MEC170x UART0 RX Pin = GPIO 0105. GIRQ09 bit[5] */
+#define UART_RX_PIN_GIRQ 9
+#define UART_RX_PIN_BIT BIT(5)
+
+#endif /* CONFIG_UART_CONSOLE == 2 */
+
 static int init_done;
 static int tx_fifo_used;
 
@@ -30,7 +65,7 @@ int uart_init_done(void)
 void uart_tx_start(void)
 {
 	/* If interrupt is already enabled, nothing to do */
-	if (MCHP_UART_IER(0) & BIT(1))
+	if (MCHP_UART_IER(CONFIG_UART_CONSOLE) & BIT(1))
 		return;
 
 	/* Do not allow deep sleep while transmit in progress */
@@ -42,13 +77,13 @@ void uart_tx_start(void)
 	 * UART where the FIFO only triggers the interrupt when its
 	 * threshold is _crossed_, not just met.
 	 */
-	MCHP_UART_IER(0) |= BIT(1);
-	task_trigger_irq(MCHP_IRQ_UART0);
+	MCHP_UART_IER(CONFIG_UART_CONSOLE) |= BIT(1);
+	task_trigger_irq(UART_IRQ);
 }
 
 void uart_tx_stop(void)
 {
-	MCHP_UART_IER(0) &= ~BIT(1);
+	MCHP_UART_IER(CONFIG_UART_CONSOLE) &= ~BIT(1);
 
 	/* Re-allow deep sleep */
 	enable_sleep(SLEEP_MASK_UART);
@@ -57,7 +92,7 @@ void uart_tx_stop(void)
 void uart_tx_flush(void)
 {
 	/* Wait for transmit FIFO empty */
-	while (!(MCHP_UART_LSR(0) & MCHP_LSR_TX_EMPTY))
+	while (!(MCHP_UART_LSR(CONFIG_UART_CONSOLE) & MCHP_LSR_TX_EMPTY))
 		;
 }
 
@@ -68,18 +103,18 @@ int uart_tx_ready(void)
 	 * this, we check transmit FIFO empty bit every 16 characters written.
 	 */
 	return tx_fifo_used != 0 ||
-			(MCHP_UART_LSR(0) & MCHP_LSR_TX_EMPTY);
+	       (MCHP_UART_LSR(CONFIG_UART_CONSOLE) & MCHP_LSR_TX_EMPTY);
 }
 
 int uart_tx_in_progress(void)
 {
 	/* return 0: FIFO is empty, 1: FIFO NOT Empty */
-	return !(MCHP_UART_LSR(0) & MCHP_LSR_TX_EMPTY);
+	return !(MCHP_UART_LSR(CONFIG_UART_CONSOLE) & MCHP_LSR_TX_EMPTY);
 }
 
 int uart_rx_available(void)
 {
-	return MCHP_UART_LSR(0) & BIT(0);
+	return MCHP_UART_LSR(CONFIG_UART_CONSOLE) & BIT(0);
 }
 
 void uart_write_char(char c)
@@ -89,85 +124,86 @@ void uart_write_char(char c)
 		;
 
 	tx_fifo_used = (tx_fifo_used + 1) % TX_FIFO_SIZE;
-	MCHP_UART_TB(0) = c;
+	MCHP_UART_TB(CONFIG_UART_CONSOLE) = c;
 }
 
 int uart_read_char(void)
 {
-	return MCHP_UART_RB(0);
+	return MCHP_UART_RB(CONFIG_UART_CONSOLE);
 }
 
 static void uart_clear_rx_fifo(int channel)
 {
-	MCHP_UART_FCR(0) = BIT(0) | BIT(1);
+	MCHP_UART_FCR(channel) = BIT(0) | BIT(1);
 }
 
 void uart_disable_interrupt(void)
 {
-	task_disable_irq(MCHP_IRQ_UART0);
+	task_disable_irq(UART_IRQ);
 }
 
 void uart_enable_interrupt(void)
 {
-	task_enable_irq(MCHP_IRQ_UART0);
+	task_enable_irq(UART_IRQ);
 }
 
 /**
  * Interrupt handler for UART.
  * Lower priority below other critical ISR's.
  */
-void uart_ec_interrupt(void)
+static void uart_ec_interrupt(void)
 {
 	/* Read input FIFO until empty, then fill output FIFO */
 	uart_process_input();
 	/* Trace statement to provide time marker for UART output? */
 	uart_process_output();
 }
-DECLARE_IRQ(MCHP_IRQ_UART0, uart_ec_interrupt, 2);
+DECLARE_IRQ(UART_IRQ, uart_ec_interrupt, 2);
 
 void uart_init(void)
 {
 	/* Clear UART PCR sleep enable */
-	MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_UART0);
+	MCHP_PCR_SLP_DIS_DEV(UART_PCR);
 
 	/* Set UART to reset on VCC1_RESET instead of nSIO_RESET */
-	MCHP_UART_CFG(0) &= ~BIT(1);
+	MCHP_UART_CFG(CONFIG_UART_CONSOLE) &= ~BIT(1);
 
 	/* Baud rate = 115200. 1.8432MHz clock. Divisor = 1 */
 
 	/* Set CLK_SRC = 0 */
-	MCHP_UART_CFG(0) &= ~BIT(0);
+	MCHP_UART_CFG(CONFIG_UART_CONSOLE) &= ~BIT(0);
 
 	/* Set DLAB = 1 */
-	MCHP_UART_LCR(0) |= BIT(7);
+	MCHP_UART_LCR(CONFIG_UART_CONSOLE) |= BIT(7);
 
 	/* PBRG0/PBRG1 */
-	MCHP_UART_PBRG0(0) = 1;
-	MCHP_UART_PBRG1(0) = 0;
+	MCHP_UART_PBRG0(CONFIG_UART_CONSOLE) = 1;
+	MCHP_UART_PBRG1(CONFIG_UART_CONSOLE) = 0;
 
 	/* Set DLAB = 0 */
-	MCHP_UART_LCR(0) &= ~BIT(7);
+	MCHP_UART_LCR(CONFIG_UART_CONSOLE) &= ~BIT(7);
 
 	/* Set word length to 8-bit */
-	MCHP_UART_LCR(0) |= BIT(0) | BIT(1);
+	MCHP_UART_LCR(CONFIG_UART_CONSOLE) |= BIT(0) | BIT(1);
 
 	/* Enable FIFO */
-	MCHP_UART_FCR(0) = BIT(0);
+	MCHP_UART_FCR(CONFIG_UART_CONSOLE) = BIT(0);
 
 	/* Activate UART */
-	MCHP_UART_ACT(0) |= BIT(0);
+	MCHP_UART_ACT(CONFIG_UART_CONSOLE) |= BIT(0);
 
 	gpio_config_module(MODULE_UART, 1);
 
 	/*
-	 * Enable interrupts for UART0.
+	 * Enable interrupts for UART
 	 */
-	uart_clear_rx_fifo(0);
-	MCHP_UART_IER(0) |= BIT(0);
-	MCHP_UART_MCR(0) |= BIT(3);
-	MCHP_INT_ENABLE(MCHP_UART_GIRQ) = MCHP_UART_GIRQ_BIT(0);
+	uart_clear_rx_fifo(CONFIG_UART_CONSOLE);
+	MCHP_UART_IER(CONFIG_UART_CONSOLE) |= BIT(0);
+	MCHP_UART_MCR(CONFIG_UART_CONSOLE) |= BIT(3);
+
+	MCHP_INT_ENABLE(MCHP_UART_GIRQ) = UART_IRQ_BIT;
 
-	task_enable_irq(MCHP_IRQ_UART0);
+	task_enable_irq(UART_IRQ);
 
 	init_done = 1;
 }
@@ -176,28 +212,27 @@ void uart_init(void)
 void uart_enter_dsleep(void)
 {
 	/* Disable the UART interrupt. */
-	task_disable_irq(MCHP_IRQ_UART0);  /* NVIC interrupt for UART=13 */
+	task_disable_irq(UART_IRQ); /* NVIC interrupt for UART=13 */
 
 	/*
 	 * Set the UART0 RX pin to be a GPIO-162(fixed pin) interrupt
 	 * with the flags defined in the gpio.inc file.
 	 */
-	gpio_reset(GPIO_UART0_RX);
+	gpio_reset(GPIO_UART_RX);
 
-	/* power-down/de-activate UART0 */
-	MCHP_UART_ACT(0) &= ~BIT(0);
+	/* power-down/deactivate UART */
+	MCHP_UART_ACT(CONFIG_UART_CONSOLE) &= ~BIT(0);
 
-	/* clear interrupt enable for UART0 */
-	MCHP_INT_DISABLE(MCHP_UART_GIRQ) = MCHP_UART_GIRQ_BIT(0);
+	/* clear interrupt enable for UART */
+	MCHP_INT_DISABLE(MCHP_UART_GIRQ) = UART_IRQ_BIT;
 
-	/* Clear pending interrupts on GPIO_UART0_RX(GPIO105, girq=9, bit=5) */
-	MCHP_INT_SOURCE(9) = BIT(5);
+	/* Clear pending interrupts on UART RX pin */
+	MCHP_INT_SOURCE(UART_RX_PIN_GIRQ) = UART_RX_PIN_BIT;
 
 	/* Enable GPIO interrupts on the UART0 RX pin. */
-	gpio_enable_interrupt(GPIO_UART0_RX);
+	gpio_enable_interrupt(GPIO_UART_RX);
 }
 
-
 void uart_exit_dsleep(void)
 {
 	/*
@@ -208,19 +243,19 @@ void uart_exit_dsleep(void)
 	 * because then the IRQ will not run at all.
 	 */
 	if (!(BIT(5) & MCHP_INT_SOURCE(9))) /* if edge interrupt */
-		gpio_disable_interrupt(GPIO_UART0_RX);
+		gpio_disable_interrupt(GPIO_UART_RX);
 
 	/* Configure UART0 pins for use in UART peripheral. */
 	gpio_config_module(MODULE_UART, 1);
 
 	/* Clear pending interrupts on UART peripheral and enable interrupts. */
-	uart_clear_rx_fifo(0);
-	MCHP_INT_SOURCE(MCHP_UART_GIRQ) = MCHP_UART_GIRQ_BIT(0);
-	MCHP_INT_ENABLE(MCHP_UART_GIRQ) = MCHP_UART_GIRQ_BIT(0);
-	task_enable_irq(MCHP_IRQ_UART0); /* NVIC interrupt for UART = 40 */
+	uart_clear_rx_fifo(CONFIG_UART_CONSOLE);
+	MCHP_INT_SOURCE(MCHP_UART_GIRQ) = UART_IRQ_BIT;
+	MCHP_INT_ENABLE(MCHP_UART_GIRQ) = UART_IRQ_BIT;
+	task_enable_irq(UART_IRQ);
 
 	/* power-up/activate UART0 */
-	MCHP_UART_ACT(0) |= BIT(0);
+	MCHP_UART_ACT(CONFIG_UART_CONSOLE) |= BIT(0);
 }
 
 void uart_deepsleep_interrupt(enum gpio_signal signal)
@@ -233,6 +268,6 @@ void uart_deepsleep_interrupt(enum gpio_signal signal)
 	clock_refresh_console_in_use();
 
 	/* Disable interrupts on UART0 RX pin to avoid repeated interrupts. */
-	gpio_disable_interrupt(GPIO_UART0_RX);
+	gpio_disable_interrupt(GPIO_UART_RX);
 }
 #endif /* CONFIG_LOW_POWER_IDLE */
diff --git a/chip/mchp/util/pack_ec.py b/chip/mchp/util/pack_ec.py
index 4917deee5d..8991718cf9 100755
--- a/chip/mchp/util/pack_ec.py
+++ b/chip/mchp/util/pack_ec.py
@@ -1,6 +1,6 @@
 #!/usr/bin/env python3
 
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
+# Copyright 2013 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -12,7 +12,8 @@
 import struct
 import subprocess
 import tempfile
-import zlib # CRC32
+import zlib  # CRC32
+
 
 # MEC1701 has 256KB SRAM from 0xE0000 - 0x120000
 # SRAM is divided into contiguous CODE & DATA
@@ -26,165 +27,199 @@
 LOAD_ADDR_RW = 0xE1000
 HEADER_SIZE = 0x40
 SPI_CLOCK_LIST = [48, 24, 16, 12]
-SPI_READ_CMD_LIST = [0x3, 0xb, 0x3b, 0x6b]
+SPI_READ_CMD_LIST = [0x3, 0xB, 0x3B, 0x6B]
+
+CRC_TABLE = [
+    0x00,
+    0x07,
+    0x0E,
+    0x09,
+    0x1C,
+    0x1B,
+    0x12,
+    0x15,
+    0x38,
+    0x3F,
+    0x36,
+    0x31,
+    0x24,
+    0x23,
+    0x2A,
+    0x2D,
+]
 
-CRC_TABLE = [0x00, 0x07, 0x0e, 0x09, 0x1c, 0x1b, 0x12, 0x15,
-             0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d]
 
 def mock_print(*args, **kwargs):
-  pass
+    pass
+
 
 debug_print = mock_print
 
+
 def Crc8(crc, data):
-  """Update CRC8 value."""
-  for v in data:
-    crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v >> 4)]);
-    crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v & 0xf)]);
-  return crc ^ 0x55
+    """Update CRC8 value."""
+    for v in data:
+        crc = ((crc << 4) & 0xFF) ^ (CRC_TABLE[(crc >> 4) ^ (v >> 4)])
+        crc = ((crc << 4) & 0xFF) ^ (CRC_TABLE[(crc >> 4) ^ (v & 0xF)])
+    return crc ^ 0x55
+
 
 def GetEntryPoint(payload_file):
-  """Read entry point from payload EC image."""
-  with open(payload_file, 'rb') as f:
-    f.seek(4)
-    s = f.read(4)
-  return struct.unpack('<I', s)[0]
+    """Read entry point from payload EC image."""
+    with open(payload_file, "rb") as f:
+        f.seek(4)
+        s = f.read(4)
+    return struct.unpack("<I", s)[0]
+
 
 def GetPayloadFromOffset(payload_file, offset):
-  """Read payload and pad it to 64-byte aligned."""
-  with open(payload_file, 'rb') as f:
-    f.seek(offset)
-    payload = bytearray(f.read())
-  rem_len = len(payload) % 64
-  if rem_len:
-    payload += b'\0' * (64 - rem_len)
-  return payload
+    """Read payload and pad it to 64-byte aligned."""
+    with open(payload_file, "rb") as f:
+        f.seek(offset)
+        payload = bytearray(f.read())
+    rem_len = len(payload) % 64
+    if rem_len:
+        payload += b"\0" * (64 - rem_len)
+    return payload
+
 
 def GetPayload(payload_file):
-  """Read payload and pad it to 64-byte aligned."""
-  return GetPayloadFromOffset(payload_file, 0)
+    """Read payload and pad it to 64-byte aligned."""
+    return GetPayloadFromOffset(payload_file, 0)
+
 
 def GetPublicKey(pem_file):
-  """Extract public exponent and modulus from PEM file."""
-  result = subprocess.run(['openssl', 'rsa', '-in', pem_file, '-text',
-                           '-noout'], stdout=subprocess.PIPE, encoding='utf-8')
-  modulus_raw = []
-  in_modulus = False
-  for line in result.stdout.splitlines():
-    if line.startswith('modulus'):
-      in_modulus = True
-    elif not line.startswith(' '):
-      in_modulus = False
-    elif in_modulus:
-      modulus_raw.extend(line.strip().strip(':').split(':'))
-    if line.startswith('publicExponent'):
-      exp = int(line.split(' ')[1], 10)
-  modulus_raw.reverse()
-  modulus = bytearray((int(x, 16) for x in modulus_raw[:256]))
-  return struct.pack('<Q', exp), modulus
+    """Extract public exponent and modulus from PEM file."""
+    result = subprocess.run(
+        ["openssl", "rsa", "-in", pem_file, "-text", "-noout"],
+        stdout=subprocess.PIPE,
+        encoding="utf-8",
+    )
+    modulus_raw = []
+    in_modulus = False
+    for line in result.stdout.splitlines():
+        if line.startswith("modulus"):
+            in_modulus = True
+        elif not line.startswith(" "):
+            in_modulus = False
+        elif in_modulus:
+            modulus_raw.extend(line.strip().strip(":").split(":"))
+        if line.startswith("publicExponent"):
+            exp = int(line.split(" ")[1], 10)
+    modulus_raw.reverse()
+    modulus = bytearray((int(x, 16) for x in modulus_raw[:256]))
+    return struct.pack("<Q", exp), modulus
+
 
 def GetSpiClockParameter(args):
-  assert args.spi_clock in SPI_CLOCK_LIST, \
-         "Unsupported SPI clock speed %d MHz" % args.spi_clock
-  return SPI_CLOCK_LIST.index(args.spi_clock)
+    assert args.spi_clock in SPI_CLOCK_LIST, (
+        "Unsupported SPI clock speed %d MHz" % args.spi_clock
+    )
+    return SPI_CLOCK_LIST.index(args.spi_clock)
+
 
 def GetSpiReadCmdParameter(args):
-  assert args.spi_read_cmd in SPI_READ_CMD_LIST, \
-         "Unsupported SPI read command 0x%x" % args.spi_read_cmd
-  return SPI_READ_CMD_LIST.index(args.spi_read_cmd)
+    assert args.spi_read_cmd in SPI_READ_CMD_LIST, (
+        "Unsupported SPI read command 0x%x" % args.spi_read_cmd
+    )
+    return SPI_READ_CMD_LIST.index(args.spi_read_cmd)
+
 
 def PadZeroTo(data, size):
-  data.extend(b'\0' * (size - len(data)))
+    data.extend(b"\0" * (size - len(data)))
+
 
 def BuildHeader(args, payload_len, load_addr, rorofile):
-  # Identifier and header version
-  header = bytearray(b'PHCM\0')
+    # Identifier and header version
+    header = bytearray(b"PHCM\0")
 
-  # byte[5]
-  b = GetSpiClockParameter(args)
-  b |= (1 << 2)
-  header.append(b)
+    # byte[5]
+    b = GetSpiClockParameter(args)
+    b |= 1 << 2
+    header.append(b)
 
-  # byte[6]
-  b = 0
-  header.append(b)
+    # byte[6]
+    b = 0
+    header.append(b)
 
-  # byte[7]
-  header.append(GetSpiReadCmdParameter(args))
+    # byte[7]
+    header.append(GetSpiReadCmdParameter(args))
 
-  # bytes 0x08 - 0x0b
-  header.extend(struct.pack('<I', load_addr))
-  # bytes 0x0c - 0x0f
-  header.extend(struct.pack('<I', GetEntryPoint(rorofile)))
-  # bytes 0x10 - 0x13
-  header.append((payload_len >> 6) & 0xff)
-  header.append((payload_len >> 14) & 0xff)
-  PadZeroTo(header, 0x14)
-  # bytes 0x14 - 0x17
-  header.extend(struct.pack('<I', args.payload_offset))
+    # bytes 0x08 - 0x0b
+    header.extend(struct.pack("<I", load_addr))
+    # bytes 0x0c - 0x0f
+    header.extend(struct.pack("<I", GetEntryPoint(rorofile)))
+    # bytes 0x10 - 0x13
+    header.append((payload_len >> 6) & 0xFF)
+    header.append((payload_len >> 14) & 0xFF)
+    PadZeroTo(header, 0x14)
+    # bytes 0x14 - 0x17
+    header.extend(struct.pack("<I", args.payload_offset))
 
-  # bytes 0x14 - 0x3F all 0
-  PadZeroTo(header, 0x40)
+    # bytes 0x14 - 0x3F all 0
+    PadZeroTo(header, 0x40)
 
-  # header signature is appended by the caller
+    # header signature is appended by the caller
 
-  return header
+    return header
 
 
 def BuildHeader2(args, payload_len, load_addr, payload_entry):
-  # Identifier and header version
-  header = bytearray(b'PHCM\0')
+    # Identifier and header version
+    header = bytearray(b"PHCM\0")
+
+    # byte[5]
+    b = GetSpiClockParameter(args)
+    b |= 1 << 2
+    header.append(b)
 
-  # byte[5]
-  b = GetSpiClockParameter(args)
-  b |= (1 << 2)
-  header.append(b)
+    # byte[6]
+    b = 0
+    header.append(b)
 
-  # byte[6]
-  b = 0
-  header.append(b)
+    # byte[7]
+    header.append(GetSpiReadCmdParameter(args))
 
-  # byte[7]
-  header.append(GetSpiReadCmdParameter(args))
+    # bytes 0x08 - 0x0b
+    header.extend(struct.pack("<I", load_addr))
+    # bytes 0x0c - 0x0f
+    header.extend(struct.pack("<I", payload_entry))
+    # bytes 0x10 - 0x13
+    header.append((payload_len >> 6) & 0xFF)
+    header.append((payload_len >> 14) & 0xFF)
+    PadZeroTo(header, 0x14)
+    # bytes 0x14 - 0x17
+    header.extend(struct.pack("<I", args.payload_offset))
 
-  # bytes 0x08 - 0x0b
-  header.extend(struct.pack('<I', load_addr))
-  # bytes 0x0c - 0x0f
-  header.extend(struct.pack('<I', payload_entry))
-  # bytes 0x10 - 0x13
-  header.append((payload_len >> 6) & 0xff)
-  header.append((payload_len >> 14) & 0xff)
-  PadZeroTo(header, 0x14)
-  # bytes 0x14 - 0x17
-  header.extend(struct.pack('<I', args.payload_offset))
+    # bytes 0x14 - 0x3F all 0
+    PadZeroTo(header, 0x40)
 
-  # bytes 0x14 - 0x3F all 0
-  PadZeroTo(header, 0x40)
+    # header signature is appended by the caller
 
-  # header signature is appended by the caller
+    return header
 
-  return header
 
 #
 # Compute SHA-256 of data and return digest
 # as a bytearray
 #
 def HashByteArray(data):
-  hasher = hashlib.sha256()
-  hasher.update(data)
-  h = hasher.digest()
-  bah = bytearray(h)
-  return bah
+    hasher = hashlib.sha256()
+    hasher.update(data)
+    h = hasher.digest()
+    bah = bytearray(h)
+    return bah
+
 
 #
 # Return 64-byte signature of byte array data.
 # Signature is SHA256 of data with 32 0 bytes appended
 #
 def SignByteArray(data):
-  debug_print("Signature is SHA-256 of data")
-  sigb = HashByteArray(data)
-  sigb.extend(b'\0' * 32)
-  return sigb
+    debug_print("Signature is SHA-256 of data")
+    sigb = HashByteArray(data)
+    sigb.extend(b"\0" * 32)
+    return sigb
 
 
 # MEC1701H supports two 32-bit Tags located at offsets 0x0 and 0x4
@@ -197,16 +232,25 @@ def SignByteArray(data):
 # to the same flash part.
 #
 def BuildTag(args):
-  tag = bytearray([(args.header_loc >> 8) & 0xff,
-                   (args.header_loc >> 16) & 0xff,
-                   (args.header_loc >> 24) & 0xff])
-  tag.append(Crc8(0, tag))
-  return tag
+    tag = bytearray(
+        [
+            (args.header_loc >> 8) & 0xFF,
+            (args.header_loc >> 16) & 0xFF,
+            (args.header_loc >> 24) & 0xFF,
+        ]
+    )
+    tag.append(Crc8(0, tag))
+    return tag
+
 
 def BuildTagFromHdrAddr(header_loc):
-    tag = bytearray([(header_loc >> 8) & 0xff,
-                     (header_loc >> 16) & 0xff,
-                     (header_loc >> 24) & 0xff])
+    tag = bytearray(
+        [
+            (header_loc >> 8) & 0xFF,
+            (header_loc >> 16) & 0xFF,
+            (header_loc >> 24) & 0xFF,
+        ]
+    )
     tag.append(Crc8(0, tag))
     return tag
 
@@ -220,20 +264,21 @@ def BuildTagFromHdrAddr(header_loc):
 # Returns temporary file name
 #
 def PacklfwRoImage(rorw_file, loader_file, image_size):
-  """Create a temp file with the
-  first image_size bytes from the loader file and append bytes
-  from the rorw file.
-  return the filename"""
-  fo=tempfile.NamedTemporaryFile(delete=False) # Need to keep file around
-  with open(loader_file,'rb') as fin1: # read 4KB loader file
-    pro = fin1.read()
-  fo.write(pro)            # write 4KB loader data to temp file
-  with open(rorw_file, 'rb') as fin:
-    ro = fin.read(image_size)
-
-  fo.write(ro)
-  fo.close()
-  return fo.name
+    """Create a temp file with the
+    first image_size bytes from the loader file and append bytes
+    from the rorw file.
+    return the filename"""
+    fo = tempfile.NamedTemporaryFile(delete=False)  # Need to keep file around
+    with open(loader_file, "rb") as fin1:  # read 4KB loader file
+        pro = fin1.read()
+    fo.write(pro)  # write 4KB loader data to temp file
+    with open(rorw_file, "rb") as fin:
+        ro = fin.read(image_size)
+
+    fo.write(ro)
+    fo.close()
+    return fo.name
+
 
 #
 # Generate a test EC_RW image of same size
@@ -244,105 +289,152 @@ def PacklfwRoImage(rorw_file, loader_file, image_size):
 # process hash generation.
 #
 def gen_test_ecrw(pldrw):
-  debug_print("gen_test_ecrw: pldrw type =", type(pldrw))
-  debug_print("len pldrw =", len(pldrw), " = ", hex(len(pldrw)))
-  cookie1_pos = pldrw.find(b'\x99\x88\x77\xce')
-  cookie2_pos = pldrw.find(b'\xdd\xbb\xaa\xce', cookie1_pos+4)
-  t = struct.unpack("<L", pldrw[cookie1_pos+0x24:cookie1_pos+0x28])
-  size = t[0]
-  debug_print("EC_RW size =", size, " = ", hex(size))
-
-  debug_print("Found cookie1 at ", hex(cookie1_pos))
-  debug_print("Found cookie2 at ", hex(cookie2_pos))
-
-  if cookie1_pos > 0 and cookie2_pos > cookie1_pos:
-    for i in range(0, cookie1_pos):
-      pldrw[i] = 0xA5
-    for i in range(cookie2_pos+4, len(pldrw)):
-      pldrw[i] = 0xA5
-
-  with open("ec_RW_test.bin", "wb") as fecrw:
-      fecrw.write(pldrw[:size])
+    debug_print("gen_test_ecrw: pldrw type =", type(pldrw))
+    debug_print("len pldrw =", len(pldrw), " = ", hex(len(pldrw)))
+    cookie1_pos = pldrw.find(b"\x99\x88\x77\xce")
+    cookie2_pos = pldrw.find(b"\xdd\xbb\xaa\xce", cookie1_pos + 4)
+    t = struct.unpack("<L", pldrw[cookie1_pos + 0x24 : cookie1_pos + 0x28])
+    size = t[0]
+    debug_print("EC_RW size =", size, " = ", hex(size))
+
+    debug_print("Found cookie1 at ", hex(cookie1_pos))
+    debug_print("Found cookie2 at ", hex(cookie2_pos))
+
+    if cookie1_pos > 0 and cookie2_pos > cookie1_pos:
+        for i in range(0, cookie1_pos):
+            pldrw[i] = 0xA5
+        for i in range(cookie2_pos + 4, len(pldrw)):
+            pldrw[i] = 0xA5
+
+    with open("ec_RW_test.bin", "wb") as fecrw:
+        fecrw.write(pldrw[:size])
+
 
 def parseargs():
-  rpath = os.path.dirname(os.path.relpath(__file__))
-
-  parser = argparse.ArgumentParser()
-  parser.add_argument("-i", "--input",
-              help="EC binary to pack, usually ec.bin or ec.RO.flat.",
-              metavar="EC_BIN", default="ec.bin")
-  parser.add_argument("-o", "--output",
-                      help="Output flash binary file",
-                      metavar="EC_SPI_FLASH", default="ec.packed.bin")
-  parser.add_argument("--loader_file",
-                      help="EC loader binary",
-                      default="ecloader.bin")
-  parser.add_argument("-s", "--spi_size", type=int,
-                      help="Size of the SPI flash in KB",
-                      default=512)
-  parser.add_argument("-l", "--header_loc", type=int,
-                      help="Location of header in SPI flash",
-                      default=0x1000)
-  parser.add_argument("-p", "--payload_offset", type=int,
-                      help="The offset of payload from the start of header",
-                      default=0x80)
-  parser.add_argument("-r", "--rw_loc", type=int,
-                      help="Start offset of EC_RW. Default is -1 meaning 1/2 flash size",
-                      default=-1)
-  parser.add_argument("--spi_clock", type=int,
-                      help="SPI clock speed. 8, 12, 24, or 48 MHz.",
-                      default=24)
-  parser.add_argument("--spi_read_cmd", type=int,
-                      help="SPI read command. 0x3, 0xB, or 0x3B.",
-                      default=0xb)
-  parser.add_argument("--image_size", type=int,
-                      help="Size of a single image. Default 220KB",
-                      default=(220 * 1024))
-  parser.add_argument("--test_spi", action='store_true',
-                      help="Test SPI data integrity by adding CRC32 in last 4-bytes of RO/RW binaries",
-                      default=False)
-  parser.add_argument("--test_ecrw", action='store_true',
-                      help="Use fixed pattern for EC_RW but preserve image_data",
-                      default=False)
-  parser.add_argument("--verbose", action='store_true',
-                      help="Enable verbose output",
-                      default=False)
-
-  return parser.parse_args()
+    rpath = os.path.dirname(os.path.relpath(__file__))
+
+    parser = argparse.ArgumentParser()
+    parser.add_argument(
+        "-i",
+        "--input",
+        help="EC binary to pack, usually ec.bin or ec.RO.flat.",
+        metavar="EC_BIN",
+        default="ec.bin",
+    )
+    parser.add_argument(
+        "-o",
+        "--output",
+        help="Output flash binary file",
+        metavar="EC_SPI_FLASH",
+        default="ec.packed.bin",
+    )
+    parser.add_argument(
+        "--loader_file", help="EC loader binary", default="ecloader.bin"
+    )
+    parser.add_argument(
+        "-s",
+        "--spi_size",
+        type=int,
+        help="Size of the SPI flash in KB",
+        default=512,
+    )
+    parser.add_argument(
+        "-l",
+        "--header_loc",
+        type=int,
+        help="Location of header in SPI flash",
+        default=0x1000,
+    )
+    parser.add_argument(
+        "-p",
+        "--payload_offset",
+        type=int,
+        help="The offset of payload from the start of header",
+        default=0x80,
+    )
+    parser.add_argument(
+        "-r",
+        "--rw_loc",
+        type=int,
+        help="Start offset of EC_RW. Default is -1 meaning 1/2 flash size",
+        default=-1,
+    )
+    parser.add_argument(
+        "--spi_clock",
+        type=int,
+        help="SPI clock speed. 8, 12, 24, or 48 MHz.",
+        default=24,
+    )
+    parser.add_argument(
+        "--spi_read_cmd",
+        type=int,
+        help="SPI read command. 0x3, 0xB, or 0x3B.",
+        default=0xB,
+    )
+    parser.add_argument(
+        "--image_size",
+        type=int,
+        help="Size of a single image. Default 220KB",
+        default=(220 * 1024),
+    )
+    parser.add_argument(
+        "--test_spi",
+        action="store_true",
+        help="Test SPI data integrity by adding CRC32 in last 4-bytes of RO/RW binaries",
+        default=False,
+    )
+    parser.add_argument(
+        "--test_ecrw",
+        action="store_true",
+        help="Use fixed pattern for EC_RW but preserve image_data",
+        default=False,
+    )
+    parser.add_argument(
+        "--verbose",
+        action="store_true",
+        help="Enable verbose output",
+        default=False,
+    )
+
+    return parser.parse_args()
+
 
 # Debug helper routine
 def dumpsects(spi_list):
-  debug_print("spi_list has {0} entries".format(len(spi_list)))
-  for s in spi_list:
-    debug_print("0x{0:x} 0x{1:x} {2:s}".format(s[0],len(s[1]),s[2]))
+    debug_print("spi_list has {0} entries".format(len(spi_list)))
+    for s in spi_list:
+        debug_print("0x{0:x} 0x{1:x} {2:s}".format(s[0], len(s[1]), s[2]))
+
 
 def printByteArrayAsHex(ba, title):
-  debug_print(title,"= ")
-  count = 0
-  for b in ba:
-    count = count + 1
-    debug_print("0x{0:02x}, ".format(b),end="")
-    if (count % 8) == 0:
-      debug_print("")
-  debug_print("\n")
+    debug_print(title, "= ")
+    count = 0
+    for b in ba:
+        count = count + 1
+        debug_print("0x{0:02x}, ".format(b), end="")
+        if (count % 8) == 0:
+            debug_print("")
+    debug_print("\n")
+
 
 def print_args(args):
-  debug_print("parsed arguments:")
-  debug_print(".input  = ", args.input)
-  debug_print(".output = ", args.output)
-  debug_print(".loader_file = ", args.loader_file)
-  debug_print(".spi_size (KB) = ", hex(args.spi_size))
-  debug_print(".image_size = ", hex(args.image_size))
-  debug_print(".header_loc = ", hex(args.header_loc))
-  debug_print(".payload_offset = ", hex(args.payload_offset))
-  if args.rw_loc < 0:
-    debug_print(".rw_loc = ", args.rw_loc)
-  else:
-    debug_print(".rw_loc = ", hex(args.rw_loc))
-  debug_print(".spi_clock = ", args.spi_clock)
-  debug_print(".spi_read_cmd = ", args.spi_read_cmd)
-  debug_print(".test_spi = ", args.test_spi)
-  debug_print(".verbose = ", args.verbose)
+    debug_print("parsed arguments:")
+    debug_print(".input  = ", args.input)
+    debug_print(".output = ", args.output)
+    debug_print(".loader_file = ", args.loader_file)
+    debug_print(".spi_size (KB) = ", hex(args.spi_size))
+    debug_print(".image_size = ", hex(args.image_size))
+    debug_print(".header_loc = ", hex(args.header_loc))
+    debug_print(".payload_offset = ", hex(args.payload_offset))
+    if args.rw_loc < 0:
+        debug_print(".rw_loc = ", args.rw_loc)
+    else:
+        debug_print(".rw_loc = ", hex(args.rw_loc))
+    debug_print(".spi_clock = ", args.spi_clock)
+    debug_print(".spi_read_cmd = ", args.spi_read_cmd)
+    debug_print(".test_spi = ", args.test_spi)
+    debug_print(".verbose = ", args.verbose)
+
 
 #
 # Handle quiet mode build from Makefile
@@ -350,183 +442,206 @@ def print_args(args):
 # Verbose mode when V=1
 #
 def main():
-  global debug_print
-
-  args = parseargs()
-
-  if args.verbose:
-    debug_print = print
-
-  debug_print("Begin MEC17xx pack_ec.py script")
-
-
-  # MEC17xx maximum 192KB each for RO & RW
-  # mec1701 chip Makefile sets args.spi_size = 512
-  # Tags at offset 0
-  #
-  print_args(args)
-
-  spi_size = args.spi_size * 1024
-  debug_print("SPI Flash image size in bytes =", hex(spi_size))
-
-  # !!! IMPORTANT !!!
-  # These values MUST match chip/mec1701/config_flash_layout.h
-  # defines.
-  # MEC17xx Boot-ROM TAGs are at offset 0 and 4.
-  # lfw + EC_RO starts at beginning of second 4KB sector
-  # EC_RW starts at offset 0x40000 (256KB)
-
-  spi_list = []
-
-  debug_print("args.input = ",args.input)
-  debug_print("args.loader_file = ",args.loader_file)
-  debug_print("args.image_size = ",hex(args.image_size))
-
-  rorofile=PacklfwRoImage(args.input, args.loader_file, args.image_size)
-
-  payload = GetPayload(rorofile)
-  payload_len = len(payload)
-  # debug
-  debug_print("EC_LFW + EC_RO length = ",hex(payload_len))
-
-  # SPI image integrity test
-  # compute CRC32 of EC_RO except for last 4 bytes
-  # skip over 4KB LFW
-  # Store CRC32 in last 4 bytes
-  if args.test_spi == True:
-    crc = zlib.crc32(bytes(payload[LFW_SIZE:(payload_len - 4)]))
-    crc_ofs = payload_len - 4
-    debug_print("EC_RO CRC32 = 0x{0:08x} @ 0x{1:08x}".format(crc, crc_ofs))
-    for i in range(4):
-      payload[crc_ofs + i] = crc & 0xff
-      crc = crc >> 8
-
-  # Chromebooks are not using MEC BootROM ECDSA.
-  # We implemented the ECDSA disabled case where
-  # the 64-byte signature contains a SHA-256 of the binary plus
-  # 32 zeros bytes.
-  payload_signature = SignByteArray(payload)
-  # debug
-  printByteArrayAsHex(payload_signature, "LFW + EC_RO payload_signature")
-
-  # MEC17xx Header is 0x80 bytes with an 64 byte signature
-  # (32 byte SHA256 + 32 zero bytes)
-  header = BuildHeader(args, payload_len, LOAD_ADDR, rorofile)
-  # debug
-  printByteArrayAsHex(header, "Header LFW + EC_RO")
-
-  # MEC17xx payload ECDSA not used, 64 byte signature is
-  # SHA256 + 32 zero bytes
-  header_signature = SignByteArray(header)
-  # debug
-  printByteArrayAsHex(header_signature, "header_signature")
-
-  tag = BuildTag(args)
-  # MEC17xx truncate RW length to args.image_size to not overwrite LFW
-  # offset may be different due to Header size and other changes
-  # MCHP we want to append a SHA-256 to the end of the actual payload
-  # to test SPI read routines.
-  debug_print("Call to GetPayloadFromOffset")
-  debug_print("args.input = ", args.input)
-  debug_print("args.image_size = ", hex(args.image_size))
-
-  payload_rw = GetPayloadFromOffset(args.input, args.image_size)
-  debug_print("type(payload_rw) is ", type(payload_rw))
-  debug_print("len(payload_rw) is ", hex(len(payload_rw)))
-
-  # truncate to args.image_size
-  rw_len = args.image_size
-  payload_rw = payload_rw[:rw_len]
-  payload_rw_len = len(payload_rw)
-  debug_print("Truncated size of EC_RW = ", hex(payload_rw_len))
-
-  payload_entry_tuple = struct.unpack_from('<I', payload_rw, 4)
-  debug_print("payload_entry_tuple = ", payload_entry_tuple)
-
-  payload_entry = payload_entry_tuple[0]
-  debug_print("payload_entry = ", hex(payload_entry))
-
-  # Note: payload_rw is a bytearray therefore is mutable
-  if args.test_ecrw:
-    gen_test_ecrw(payload_rw)
-
-  # SPI image integrity test
-  # compute CRC32 of EC_RW except for last 4 bytes
-  # Store CRC32 in last 4 bytes
-  if args.test_spi == True:
-    crc = zlib.crc32(bytes(payload_rw[:(payload_rw_len - 32)]))
-    crc_ofs = payload_rw_len - 4
-    debug_print("EC_RW CRC32 = 0x{0:08x} at offset 0x{1:08x}".format(crc, crc_ofs))
-    for i in range(4):
-      payload_rw[crc_ofs + i] = crc & 0xff
-      crc = crc >> 8
-
-  payload_rw_sig = SignByteArray(payload_rw)
-  # debug
-  printByteArrayAsHex(payload_rw_sig, "payload_rw_sig")
-
-  os.remove(rorofile)           # clean up the temp file
-
-  # MEC170x Boot-ROM Tags are located at SPI offset 0
-  spi_list.append((0, tag, "tag"))
-
-  spi_list.append((args.header_loc, header, "header(lwf + ro)"))
-  spi_list.append((args.header_loc + HEADER_SIZE, header_signature,
-    "header(lwf + ro) signature"))
-  spi_list.append((args.header_loc + args.payload_offset, payload,
-    "payload(lfw + ro)"))
-
-  offset = args.header_loc + args.payload_offset + payload_len
-
-  # No SPI Header for EC_RW as its not loaded by BootROM
-  spi_list.append((offset, payload_signature,
-                   "payload(lfw_ro) signature"))
-
-  # EC_RW location
-  rw_offset = int(spi_size // 2)
-  if args.rw_loc >= 0:
-    rw_offset = args.rw_loc
-
-  debug_print("rw_offset = 0x{0:08x}".format(rw_offset))
-
-  if rw_offset < offset + len(payload_signature):
-    print("ERROR: EC_RW overlaps EC_RO")
-
-  spi_list.append((rw_offset, payload_rw, "payload(rw)"))
-
-  # don't add to EC_RW. We don't know if Google will process
-  # EC SPI flash binary with other tools during build of
-  # coreboot and OS.
-  #offset = rw_offset + payload_rw_len
-  #spi_list.append((offset, payload_rw_sig, "payload(rw) signature"))
-
-  spi_list = sorted(spi_list)
-
-  dumpsects(spi_list)
-
-  #
-  # MEC17xx Boot-ROM locates TAG at SPI offset 0 instead of end of SPI.
-  #
-  with open(args.output, 'wb') as f:
-    debug_print("Write spi list to file", args.output)
-    addr = 0
-    for s in spi_list:
-      if addr < s[0]:
-        debug_print("Offset ",hex(addr)," Length", hex(s[0]-addr),
-                "fill with 0xff")
-        f.write(b'\xff' * (s[0] - addr))
-        addr = s[0]
-        debug_print("Offset ",hex(addr), " Length", hex(len(s[1])), "write data")
-
-      f.write(s[1])
-      addr += len(s[1])
-
-    if addr < spi_size:
-      debug_print("Offset ",hex(addr), " Length", hex(spi_size - addr),
-              "fill with 0xff")
-      f.write(b'\xff' * (spi_size - addr))
-
-    f.flush()
-
-if __name__ == '__main__':
-  main()
+    global debug_print
+
+    args = parseargs()
+
+    if args.verbose:
+        debug_print = print
+
+    debug_print("Begin MEC17xx pack_ec.py script")
+
+    # MEC17xx maximum 192KB each for RO & RW
+    # mec1701 chip Makefile sets args.spi_size = 512
+    # Tags at offset 0
+    #
+    print_args(args)
+
+    spi_size = args.spi_size * 1024
+    debug_print("SPI Flash image size in bytes =", hex(spi_size))
+
+    # !!! IMPORTANT !!!
+    # These values MUST match chip/mec1701/config_flash_layout.h
+    # defines.
+    # MEC17xx Boot-ROM TAGs are at offset 0 and 4.
+    # lfw + EC_RO starts at beginning of second 4KB sector
+    # EC_RW starts at offset 0x40000 (256KB)
+
+    spi_list = []
+
+    debug_print("args.input = ", args.input)
+    debug_print("args.loader_file = ", args.loader_file)
+    debug_print("args.image_size = ", hex(args.image_size))
+
+    rorofile = PacklfwRoImage(args.input, args.loader_file, args.image_size)
+
+    payload = GetPayload(rorofile)
+    payload_len = len(payload)
+    # debug
+    debug_print("EC_LFW + EC_RO length = ", hex(payload_len))
+
+    # SPI image integrity test
+    # compute CRC32 of EC_RO except for last 4 bytes
+    # skip over 4KB LFW
+    # Store CRC32 in last 4 bytes
+    if args.test_spi == True:
+        crc = zlib.crc32(bytes(payload[LFW_SIZE : (payload_len - 4)]))
+        crc_ofs = payload_len - 4
+        debug_print("EC_RO CRC32 = 0x{0:08x} @ 0x{1:08x}".format(crc, crc_ofs))
+        for i in range(4):
+            payload[crc_ofs + i] = crc & 0xFF
+            crc = crc >> 8
+
+    # Chromebooks are not using MEC BootROM ECDSA.
+    # We implemented the ECDSA disabled case where
+    # the 64-byte signature contains a SHA-256 of the binary plus
+    # 32 zeros bytes.
+    payload_signature = SignByteArray(payload)
+    # debug
+    printByteArrayAsHex(payload_signature, "LFW + EC_RO payload_signature")
+
+    # MEC17xx Header is 0x80 bytes with an 64 byte signature
+    # (32 byte SHA256 + 32 zero bytes)
+    header = BuildHeader(args, payload_len, LOAD_ADDR, rorofile)
+    # debug
+    printByteArrayAsHex(header, "Header LFW + EC_RO")
+
+    # MEC17xx payload ECDSA not used, 64 byte signature is
+    # SHA256 + 32 zero bytes
+    header_signature = SignByteArray(header)
+    # debug
+    printByteArrayAsHex(header_signature, "header_signature")
+
+    tag = BuildTag(args)
+    # MEC17xx truncate RW length to args.image_size to not overwrite LFW
+    # offset may be different due to Header size and other changes
+    # MCHP we want to append a SHA-256 to the end of the actual payload
+    # to test SPI read routines.
+    debug_print("Call to GetPayloadFromOffset")
+    debug_print("args.input = ", args.input)
+    debug_print("args.image_size = ", hex(args.image_size))
+
+    payload_rw = GetPayloadFromOffset(args.input, args.image_size)
+    debug_print("type(payload_rw) is ", type(payload_rw))
+    debug_print("len(payload_rw) is ", hex(len(payload_rw)))
+
+    # truncate to args.image_size
+    rw_len = args.image_size
+    payload_rw = payload_rw[:rw_len]
+    payload_rw_len = len(payload_rw)
+    debug_print("Truncated size of EC_RW = ", hex(payload_rw_len))
+
+    payload_entry_tuple = struct.unpack_from("<I", payload_rw, 4)
+    debug_print("payload_entry_tuple = ", payload_entry_tuple)
+
+    payload_entry = payload_entry_tuple[0]
+    debug_print("payload_entry = ", hex(payload_entry))
+
+    # Note: payload_rw is a bytearray therefore is mutable
+    if args.test_ecrw:
+        gen_test_ecrw(payload_rw)
+
+    # SPI image integrity test
+    # compute CRC32 of EC_RW except for last 4 bytes
+    # Store CRC32 in last 4 bytes
+    if args.test_spi == True:
+        crc = zlib.crc32(bytes(payload_rw[: (payload_rw_len - 32)]))
+        crc_ofs = payload_rw_len - 4
+        debug_print(
+            "EC_RW CRC32 = 0x{0:08x} at offset 0x{1:08x}".format(crc, crc_ofs)
+        )
+        for i in range(4):
+            payload_rw[crc_ofs + i] = crc & 0xFF
+            crc = crc >> 8
+
+    payload_rw_sig = SignByteArray(payload_rw)
+    # debug
+    printByteArrayAsHex(payload_rw_sig, "payload_rw_sig")
+
+    os.remove(rorofile)  # clean up the temp file
+
+    # MEC170x Boot-ROM Tags are located at SPI offset 0
+    spi_list.append((0, tag, "tag"))
+
+    spi_list.append((args.header_loc, header, "header(lwf + ro)"))
+    spi_list.append(
+        (
+            args.header_loc + HEADER_SIZE,
+            header_signature,
+            "header(lwf + ro) signature",
+        )
+    )
+    spi_list.append(
+        (args.header_loc + args.payload_offset, payload, "payload(lfw + ro)")
+    )
+
+    offset = args.header_loc + args.payload_offset + payload_len
+
+    # No SPI Header for EC_RW as its not loaded by BootROM
+    spi_list.append((offset, payload_signature, "payload(lfw_ro) signature"))
+
+    # EC_RW location
+    rw_offset = int(spi_size // 2)
+    if args.rw_loc >= 0:
+        rw_offset = args.rw_loc
+
+    debug_print("rw_offset = 0x{0:08x}".format(rw_offset))
+
+    if rw_offset < offset + len(payload_signature):
+        print("ERROR: EC_RW overlaps EC_RO")
+
+    spi_list.append((rw_offset, payload_rw, "payload(rw)"))
+
+    # don't add to EC_RW. We don't know if Google will process
+    # EC SPI flash binary with other tools during build of
+    # coreboot and OS.
+    # offset = rw_offset + payload_rw_len
+    # spi_list.append((offset, payload_rw_sig, "payload(rw) signature"))
+
+    spi_list = sorted(spi_list)
+
+    dumpsects(spi_list)
+
+    #
+    # MEC17xx Boot-ROM locates TAG at SPI offset 0 instead of end of SPI.
+    #
+    with open(args.output, "wb") as f:
+        debug_print("Write spi list to file", args.output)
+        addr = 0
+        for s in spi_list:
+            if addr < s[0]:
+                debug_print(
+                    "Offset ",
+                    hex(addr),
+                    " Length",
+                    hex(s[0] - addr),
+                    "fill with 0xff",
+                )
+                f.write(b"\xff" * (s[0] - addr))
+                addr = s[0]
+                debug_print(
+                    "Offset ",
+                    hex(addr),
+                    " Length",
+                    hex(len(s[1])),
+                    "write data",
+                )
+
+            f.write(s[1])
+            addr += len(s[1])
+
+        if addr < spi_size:
+            debug_print(
+                "Offset ",
+                hex(addr),
+                " Length",
+                hex(spi_size - addr),
+                "fill with 0xff",
+            )
+            f.write(b"\xff" * (spi_size - addr))
+
+        f.flush()
+
+
+if __name__ == "__main__":
+    main()
diff --git a/chip/mchp/util/pack_ec_mec152x.py b/chip/mchp/util/pack_ec_mec152x.py
new file mode 100755
index 0000000000..43721b3336
--- /dev/null
+++ b/chip/mchp/util/pack_ec_mec152x.py
@@ -0,0 +1,941 @@
+#!/usr/bin/env python3
+
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# A script to pack EC binary into SPI flash image for MEC152x
+# Based on MEC1521/MEC1523_ROM_Description.pdf
+import argparse
+import hashlib
+import os
+import struct
+import subprocess
+import tempfile
+import zlib  # CRC32
+
+
+# MEC152xH has 256KB SRAM from 0xE0000 - 0x120000
+# SRAM is divided into contiguous CODE & DATA
+# CODE at [0xE0000, 0x117FFF] DATA at [0x118000, 0x11FFFF]
+# SPI flash size for board is 512KB
+# Boot-ROM TAG is located at SPI offset 0 (two 4-byte tags)
+
+LFW_SIZE = 0x1000
+LOAD_ADDR = 0x0E0000
+LOAD_ADDR_RW = 0xE1000
+MEC152X_HEADER_SIZE = 0x140
+MEC152X_HEADER_VERSION = 0x02
+PAYLOAD_PAD_BYTE = b"\xff"
+SPI_ERASE_BLOCK_SIZE = 0x1000
+SPI_CLOCK_LIST = [48, 24, 16, 12]
+SPI_READ_CMD_LIST = [0x3, 0xB, 0x3B, 0x6B]
+SPI_DRIVE_STR_DICT = {2: 0, 4: 1, 8: 2, 12: 3}
+CHIP_MAX_CODE_SRAM_KB = 224
+
+MEC152X_DICT = {
+    "HEADER_SIZE": 0x140,
+    "HEADER_VER": 0x02,
+    "PAYLOAD_OFFSET": 0x140,
+    "PAYLOAD_GRANULARITY": 128,
+    "EC_INFO_BLK_SZ": 128,
+    "ENCR_KEY_HDR_SZ": 128,
+    "COSIG_SZ": 96,
+    "TRAILER_SZ": 160,
+    "TAILER_PAD_BYTE": b"\xff",
+    "PAD_SIZE": 128,
+}
+
+CRC_TABLE = [
+    0x00,
+    0x07,
+    0x0E,
+    0x09,
+    0x1C,
+    0x1B,
+    0x12,
+    0x15,
+    0x38,
+    0x3F,
+    0x36,
+    0x31,
+    0x24,
+    0x23,
+    0x2A,
+    0x2D,
+]
+
+
+def mock_print(*args, **kwargs):
+    pass
+
+
+debug_print = mock_print
+
+# Debug helper routine
+def dumpsects(spi_list):
+    debug_print("spi_list has {0} entries".format(len(spi_list)))
+    for s in spi_list:
+        debug_print("0x{0:x} 0x{1:x} {2:s}".format(s[0], len(s[1]), s[2]))
+
+
+def printByteArrayAsHex(ba, title):
+    debug_print(title, "= ")
+    if ba == None:
+        debug_print("None")
+        return
+
+    count = 0
+    for b in ba:
+        count = count + 1
+        debug_print("0x{0:02x}, ".format(b), end="")
+        if (count % 8) == 0:
+            debug_print("")
+    debug_print("")
+
+
+def Crc8(crc, data):
+    """Update CRC8 value."""
+    for v in data:
+        crc = ((crc << 4) & 0xFF) ^ (CRC_TABLE[(crc >> 4) ^ (v >> 4)])
+        crc = ((crc << 4) & 0xFF) ^ (CRC_TABLE[(crc >> 4) ^ (v & 0xF)])
+    return crc ^ 0x55
+
+
+def GetEntryPoint(payload_file):
+    """Read entry point from payload EC image."""
+    with open(payload_file, "rb") as f:
+        f.seek(4)
+        s = f.read(4)
+    return int.from_bytes(s, byteorder="little")
+
+
+def GetPayloadFromOffset(payload_file, offset, padsize):
+    """Read payload and pad it to padsize."""
+    with open(payload_file, "rb") as f:
+        f.seek(offset)
+        payload = bytearray(f.read())
+    rem_len = len(payload) % padsize
+    debug_print(
+        "GetPayload: padsize={0:0x} len(payload)={1:0x} rem={2:0x}".format(
+            padsize, len(payload), rem_len
+        )
+    )
+
+    if rem_len:
+        payload += PAYLOAD_PAD_BYTE * (padsize - rem_len)
+        debug_print(
+            "GetPayload: Added {0} padding bytes".format(padsize - rem_len)
+        )
+
+    return payload
+
+
+def GetPayload(payload_file, padsize):
+    """Read payload and pad it to padsize"""
+    return GetPayloadFromOffset(payload_file, 0, padsize)
+
+
+def GetPublicKey(pem_file):
+    """Extract public exponent and modulus from PEM file."""
+    result = subprocess.run(
+        ["openssl", "rsa", "-in", pem_file, "-text", "-noout"],
+        stdout=subprocess.PIPE,
+        encoding="utf-8",
+    )
+    modulus_raw = []
+    in_modulus = False
+    for line in result.stdout.splitlines():
+        if line.startswith("modulus"):
+            in_modulus = True
+        elif not line.startswith(" "):
+            in_modulus = False
+        elif in_modulus:
+            modulus_raw.extend(line.strip().strip(":").split(":"))
+        if line.startswith("publicExponent"):
+            exp = int(line.split(" ")[1], 10)
+    modulus_raw.reverse()
+    modulus = bytearray((int(x, 16) for x in modulus_raw[:256]))
+    return struct.pack("<Q", exp), modulus
+
+
+def GetSpiClockParameter(args):
+    assert args.spi_clock in SPI_CLOCK_LIST, (
+        "Unsupported SPI clock speed %d MHz" % args.spi_clock
+    )
+    return SPI_CLOCK_LIST.index(args.spi_clock)
+
+
+def GetSpiReadCmdParameter(args):
+    assert args.spi_read_cmd in SPI_READ_CMD_LIST, (
+        "Unsupported SPI read command 0x%x" % args.spi_read_cmd
+    )
+    return SPI_READ_CMD_LIST.index(args.spi_read_cmd)
+
+
+def GetEncodedSpiDriveStrength(args):
+    assert args.spi_drive_str in SPI_DRIVE_STR_DICT, (
+        "Unsupported SPI drive strength %d mA" % args.spi_drive_str
+    )
+    return SPI_DRIVE_STR_DICT.get(args.spi_drive_str)
+
+
+# Return 0=Slow slew rate or 1=Fast slew rate
+def GetSpiSlewRate(args):
+    if args.spi_slew_fast == True:
+        return 1
+    return 0
+
+
+# Return SPI CPOL = 0 or 1
+def GetSpiCpol(args):
+    if args.spi_cpol == 0:
+        return 0
+    return 1
+
+
+# Return SPI CPHA_MOSI
+# 0 = SPI Master drives data is stable on inactive to clock edge
+# 1 = SPI Master drives data is stable on active to inactive clock edge
+def GetSpiCphaMosi(args):
+    if args.spi_cpha_mosi == 0:
+        return 0
+    return 1
+
+
+# Return SPI CPHA_MISO 0 or 1
+# 0 = SPI Master samples data on inactive to active clock edge
+# 1 = SPI Master samples data on active to inactive clock edge
+def GetSpiCphaMiso(args):
+    if args.spi_cpha_miso == 0:
+        return 0
+    return 1
+
+
+def PadZeroTo(data, size):
+    data.extend(b"\0" * (size - len(data)))
+
+
+#
+# Build SPI image header for MEC152x
+# MEC152x image header size = 320(0x140) bytes
+#
+# Description using Python slice notation [start:start+len]
+#
+# header[0:4] = 'PHCM'
+# header[4] = header version = 0x02(MEC152x)
+# header[5] = SPI clock speed, drive strength, sampling mode
+#   bits[1:0] = SPI clock speed: 0=48, 1=24, 2=16, 3=12
+#   bits[3:2] = SPI controller pins drive strength
+#               00b=2mA, 01b=4mA, 10b=8mA, 11b=12mA
+#   bit[4] = SPI controller pins slew rate: 0=slow, 1=fast
+#   bit[5] = SPI CPOL: 0=SPI clock idle is low, 1=idle is high
+#   bit[6] = CHPHA_MOSI
+#       1:data change on first inactive to active clock edge
+#       0:data change on first active to inactive clock edge
+#   bit[7] = CHPHA_MISO:
+#       1: Data captured on first inactive to active clock edge
+#       0: Data captured on first active to inactive clock edge
+# header[6] Boot-ROM loader flags
+#   bits[2:0] = VTR0,1,2 rails. 0=3.3V, 1=1.8V. NOTE VTR1=0 always
+#   bits[5:3] = 111b
+#   bit[6]: For MEC152x controls authentication
+#           0=Authentication disabled. Signature is SHA-384 of FW payload
+#           1=Authentication enabled. Signature is ECDSA P-384
+#   bit[7]: 0=FW pyload not encrypted, 1=FW payload is encrypted
+# header[7]: SPI Flash read command
+#            0x03 1-1-1 read freq < 33MHz
+#            0x0B 1-1-1 + 8 clocks(data tri-stated)
+#            0x3B 1-1-2 + 8 clocks(data tri-stated). Data phase is dual I/O
+#            0x6B 1-1-4 + 8 clocks(data tri-stated). Data phase is Quad I/O
+#            NOTE: Quad requires SPI flash device QE(quad enable) bit
+#            to be factory set. Enabling QE disables HOLD# and WP#
+#            functionality of the SPI flash device.
+# header[0x8:0xC] SRAM Load address little-endian format
+# header[0xC:0x10] SRAM FW entry point. Boot-ROM jumps to
+#                  this address on successful load. (little-endian)
+# header[0x10:0x12] little-endian format: FW binary size in units of
+#                   128 bytes(MEC152x)
+# header[0x12:0x14] = 0 reserved
+# header[0x14:0x18] = Little-ending format: Unsigned offset from start of
+#                     header to FW payload.
+#                     MEC152x: Offset must be a multiple of 128
+#                     Offset must be > header size.
+#                     NOTE: If Authentication is enabled size includes
+#                     the appended signature.
+# MEC152x:
+# header[0x18] = Authentication key select. Set to 0 for no Authentication.
+# header[0x19:0x50] = 0 reserved.
+# header[0x50:0x80] = ECDSA-384 public key x-coord. = 0 Auth. disabled
+# header[0x80:0xB0] = ECDSA-384 public key y-coord. = 0 Auth. disabled
+# header[0xB0:0xE0] = SHA-384 digest of header[0:0xB0]
+# header[0xE0:0x110] = Header ECDSA-384 signature x-coord. = 0 Auth. disabled
+# header[0x110:0x140] = Header ECDSA-384 signature y-coor. = 0 Auth. disabled
+#
+def BuildHeader2(args, chip_dict, payload_len, load_addr, payload_entry):
+    header_size = MEC152X_HEADER_SIZE
+
+    # allocate zero filled header
+    header = bytearray(b"\x00" * header_size)
+    debug_print("len(header) = ", len(header))
+
+    # Identifier and header version
+    header[0:4] = b"PHCM"
+    header[4] = MEC152X_HEADER_VERSION
+
+    # SPI frequency, drive strength, CPOL/CPHA encoding same for both chips
+    spiFreqMHz = GetSpiClockParameter(args)
+    header[5] = (int(spiFreqMHz // 48) - 1) & 0x03
+    header[5] |= (GetEncodedSpiDriveStrength(args) & 0x03) << 2
+    header[5] |= (GetSpiSlewRate(args) & 0x01) << 4
+    header[5] |= (GetSpiCpol(args) & 0x01) << 5
+    header[5] |= (GetSpiCphaMosi(args) & 0x01) << 6
+    header[5] |= (GetSpiCphaMiso(args) & 0x01) << 7
+
+    # b[0]=0 VTR1 must be 3.3V
+    # b[1]=0(VTR2 3.3V), 1(VTR2 1.8V)
+    # b[2]=0(VTR3 3.3V), 1(VTR3 1.8V)
+    # b[5:3]=111b
+    # b[6]=0 No ECDSA
+    # b[7]=0 No encrypted FW image
+    header[6] = 0x7 << 3
+    if args.vtr2_V18 == True:
+        header[6] |= 0x02
+    if args.vtr3_V18 == True:
+        header[6] |= 0x04
+
+    # SPI read command set same for both chips
+    header[7] = GetSpiReadCmdParameter(args) & 0xFF
+
+    # bytes 0x08 - 0x0b
+    header[0x08:0x0C] = load_addr.to_bytes(4, byteorder="little")
+    # bytes 0x0c - 0x0f
+    header[0x0C:0x10] = payload_entry.to_bytes(4, byteorder="little")
+    # bytes 0x10 - 0x11 payload length in units of 128 bytes
+
+    payload_units = int(payload_len // chip_dict["PAYLOAD_GRANULARITY"])
+    assert payload_units < 0x10000, print(
+        "Payload too large: len={0} units={1}".format(
+            payload_len, payload_units
+        )
+    )
+
+    header[0x10:0x12] = payload_units.to_bytes(2, "little")
+
+    # bytes 0x14 - 0x17
+    header[0x14:0x18] = chip_dict["PAYLOAD_OFFSET"].to_bytes(4, "little")
+
+    # MEC152x: Disable ECDSA and encryption
+    header[0x18] = 0
+
+    # header[0xB0:0xE0] = SHA384(header[0:0xB0])
+    header[0xB0:0xE0] = hashlib.sha384(header[0:0xB0]).digest()
+    # When ECDSA authentication is disabled MCHP SPI image generator
+    # is filling the last 48 bytes of the Header with 0xff
+    header[-48:] = b"\xff" * 48
+
+    debug_print("After hash: len(header) = ", len(header))
+
+    return header
+
+
+#
+# MEC152x 128-byte EC Info Block appended to
+# end of padded FW binary
+# bytes 0 through 103 are undefined, we set to 0xFF
+# bytes 104 through 119 are rollback permissions
+# bytes 120 through 123 are key revocation permissions
+# byte 124 = customer platform ID[7:0]
+# byte 125 = customer platform ID[15:8]
+# byte 126 = customer auto rollback flags
+# byte 127 = customer current image revision
+#
+def GenEcInfoBlock(args, chip_dict):
+    ecinfo = bytearray(chip_dict["EC_INFO_BLK_SZ"])
+    return ecinfo
+
+
+#
+# Generate SPI FW image co-signature.
+# MEC152X cosignature is 96 bytes used by OEM FW
+# developer to sign their binary with ECDSA-P384-SHA384 or
+# some other signature algorithm that fits in 96 bytes.
+# At this time Cros-EC is not using this field, fill with 0xFF.
+# If this feature is implemented we need to read the OEM's
+# generated signature from a file and extract the binary
+# signature.
+#
+def GenCoSignature(args, chip_dict, payload):
+    return bytearray(b"\xff" * chip_dict["COSIG_SZ"])
+
+
+#
+# Generate SPI FW Image trailer.
+# MEC152X: Size = 160 bytes
+#   binary = payload || encryption_key_header || ec_info_block || cosignature
+#   trailer[0:48] = SHA384(binary)
+#   trailer[48:144] = 0xFF
+#   trailer[144:160] = 0xFF. Boot-ROM spec. says these bytes should be random.
+#       Authentication & encryption are not used therefore random data
+#       is not necessary.
+def GenTrailer(
+    args, chip_dict, payload, encryption_key_header, ec_info_block, cosignature
+):
+    trailer = bytearray(chip_dict["TAILER_PAD_BYTE"] * chip_dict["TRAILER_SZ"])
+    hasher = hashlib.sha384()
+    hasher.update(payload)
+    if ec_info_block != None:
+        hasher.update(ec_info_block)
+    if encryption_key_header != None:
+        hasher.update(encryption_key_header)
+    if cosignature != None:
+        hasher.update(cosignature)
+    trailer[0:48] = hasher.digest()
+    trailer[-16:] = 16 * b"\xff"
+
+    return trailer
+
+
+# MEC152xH supports two 32-bit Tags located at offsets 0x0 and 0x4
+# in the SPI flash.
+# Tag format:
+#   bits[23:0] correspond to bits[31:8] of the Header SPI address
+#       Header is always on a 256-byte boundary.
+#   bits[31:24] = CRC8-ITU of bits[23:0].
+# Notice there is no chip-select field in the Tag both Tag's point
+# to the same flash part.
+#
+def BuildTag(args):
+    tag = bytearray(
+        [
+            (args.header_loc >> 8) & 0xFF,
+            (args.header_loc >> 16) & 0xFF,
+            (args.header_loc >> 24) & 0xFF,
+        ]
+    )
+    tag.append(Crc8(0, tag))
+    return tag
+
+
+def BuildTagFromHdrAddr(header_loc):
+    tag = bytearray(
+        [
+            (header_loc >> 8) & 0xFF,
+            (header_loc >> 16) & 0xFF,
+            (header_loc >> 24) & 0xFF,
+        ]
+    )
+    tag.append(Crc8(0, tag))
+    return tag
+
+
+# FlashMap is an option for MEC152x
+# It is a 32 bit structure
+# bits[18:0] = bits[30:12] of second SPI flash base address
+# bits[23:19] = 0 reserved
+# bits[31:24] = CRC8 of bits[23:0]
+# Input:
+#   integer containing base address of second SPI flash
+#   This value is usually equal to the size of the first
+#   SPI flash and should be a multiple of 4KB
+# Output:
+#   bytearray of length 4
+def BuildFlashMap(secondSpiFlashBaseAddr):
+    flashmap = bytearray(4)
+    flashmap[0] = (secondSpiFlashBaseAddr >> 12) & 0xFF
+    flashmap[1] = (secondSpiFlashBaseAddr >> 20) & 0xFF
+    flashmap[2] = (secondSpiFlashBaseAddr >> 28) & 0xFF
+    flashmap[3] = Crc8(0, flashmap)
+    return flashmap
+
+
+#
+# Creates temporary file for read/write
+# Reads binary file containing LFW image_size (loader_file)
+# Writes LFW image to temporary file
+# Reads RO image at beginning of rorw_file up to image_size
+#  (assumes RO/RW images have been padded with 0xFF
+# Returns temporary file name
+#
+def PacklfwRoImage(rorw_file, loader_file, image_size):
+    """Create a temp file with the
+    first image_size bytes from the loader file and append bytes
+    from the rorw file.
+    return the filename"""
+    fo = tempfile.NamedTemporaryFile(delete=False)  # Need to keep file around
+    with open(loader_file, "rb") as fin1:  # read 4KB loader file
+        pro = fin1.read()
+    fo.write(pro)  # write 4KB loader data to temp file
+    with open(rorw_file, "rb") as fin:
+        ro = fin.read(image_size)
+
+    fo.write(ro)
+    fo.close()
+
+    return fo.name
+
+
+#
+# Generate a test EC_RW image of same size
+# as original.
+# Preserve image_data structure and fill all
+# other bytes with 0xA5.
+# useful for testing SPI read and EC build
+# process hash generation.
+#
+def gen_test_ecrw(pldrw):
+    debug_print("gen_test_ecrw: pldrw type =", type(pldrw))
+    debug_print("len pldrw =", len(pldrw), " = ", hex(len(pldrw)))
+    cookie1_pos = pldrw.find(b"\x99\x88\x77\xce")
+    cookie2_pos = pldrw.find(b"\xdd\xbb\xaa\xce", cookie1_pos + 4)
+    t = struct.unpack("<L", pldrw[cookie1_pos + 0x24 : cookie1_pos + 0x28])
+    size = t[0]
+    debug_print("EC_RW size =", size, " = ", hex(size))
+
+    debug_print("Found cookie1 at ", hex(cookie1_pos))
+    debug_print("Found cookie2 at ", hex(cookie2_pos))
+
+    if cookie1_pos > 0 and cookie2_pos > cookie1_pos:
+        for i in range(0, cookie1_pos):
+            pldrw[i] = 0xA5
+        for i in range(cookie2_pos + 4, len(pldrw)):
+            pldrw[i] = 0xA5
+
+    with open("ec_RW_test.bin", "wb") as fecrw:
+        fecrw.write(pldrw[:size])
+
+
+def parseargs():
+    parser = argparse.ArgumentParser()
+    parser.add_argument(
+        "-i",
+        "--input",
+        help="EC binary to pack, usually ec.bin or ec.RO.flat.",
+        metavar="EC_BIN",
+        default="ec.bin",
+    )
+    parser.add_argument(
+        "-o",
+        "--output",
+        help="Output flash binary file",
+        metavar="EC_SPI_FLASH",
+        default="ec.packed.bin",
+    )
+    parser.add_argument(
+        "--loader_file", help="EC loader binary", default="ecloader.bin"
+    )
+    parser.add_argument(
+        "-s",
+        "--spi_size",
+        type=int,
+        help="Size of the SPI flash in KB",
+        default=512,
+    )
+    parser.add_argument(
+        "-l",
+        "--header_loc",
+        type=int,
+        help="Location of header in SPI flash",
+        default=0x1000,
+    )
+    parser.add_argument(
+        "-r",
+        "--rw_loc",
+        type=int,
+        help="Start offset of EC_RW. Default is -1 meaning 1/2 flash size",
+        default=-1,
+    )
+    parser.add_argument(
+        "--spi_clock",
+        type=int,
+        help="SPI clock speed. 8, 12, 24, or 48 MHz.",
+        default=24,
+    )
+    parser.add_argument(
+        "--spi_read_cmd",
+        type=int,
+        help="SPI read command. 0x3, 0xB, or 0x3B.",
+        default=0xB,
+    )
+    parser.add_argument(
+        "--image_size",
+        type=int,
+        help="Size of a single image. Default 220KB",
+        default=(220 * 1024),
+    )
+    parser.add_argument(
+        "--test_spi",
+        action="store_true",
+        help="Test SPI data integrity by adding CRC32 in last 4-bytes of RO/RW binaries",
+        default=False,
+    )
+    parser.add_argument(
+        "--test_ecrw",
+        action="store_true",
+        help="Use fixed pattern for EC_RW but preserve image_data",
+        default=False,
+    )
+    parser.add_argument(
+        "--verbose",
+        action="store_true",
+        help="Enable verbose output",
+        default=False,
+    )
+    parser.add_argument(
+        "--tag0_loc", type=int, help="MEC152X TAG0 SPI offset", default=0
+    )
+    parser.add_argument(
+        "--tag1_loc", type=int, help="MEC152X TAG1 SPI offset", default=4
+    )
+    parser.add_argument(
+        "--spi_drive_str",
+        type=int,
+        help="Chip SPI drive strength in mA: 2, 4, 8, or 12",
+        default=4,
+    )
+    parser.add_argument(
+        "--spi_slew_fast",
+        action="store_true",
+        help="SPI use fast slew rate. Default is False",
+        default=False,
+    )
+    parser.add_argument(
+        "--spi_cpol",
+        type=int,
+        help="SPI clock polarity when idle. Defealt is 0(low)",
+        default=0,
+    )
+    parser.add_argument(
+        "--spi_cpha_mosi",
+        type=int,
+        help="""SPI clock phase master drives data.
+                              0=Data driven on active to inactive clock edge,
+                              1=Data driven on inactive to active clock edge""",
+        default=0,
+    )
+    parser.add_argument(
+        "--spi_cpha_miso",
+        type=int,
+        help="""SPI clock phase master samples data.
+                              0=Data sampled on inactive to active clock edge,
+                              1=Data sampled on active to inactive clock edge""",
+        default=0,
+    )
+
+    parser.add_argument(
+        "--vtr2_V18",
+        action="store_true",
+        help="Chip VTR2 rail is 1.8V. Default is False(3.3V)",
+        default=False,
+    )
+
+    parser.add_argument(
+        "--vtr3_V18",
+        action="store_true",
+        help="Chip VTR3 rail is 1.8V. Default is False(3.3V)",
+        default=False,
+    )
+
+    return parser.parse_args()
+
+
+def print_args(args):
+    debug_print("parsed arguments:")
+    debug_print(".input  = ", args.input)
+    debug_print(".output = ", args.output)
+    debug_print(".loader_file = ", args.loader_file)
+    debug_print(".spi_size (KB) = ", hex(args.spi_size))
+    debug_print(".image_size = ", hex(args.image_size))
+    debug_print(".tag0_loc = ", hex(args.tag0_loc))
+    debug_print(".tag1_loc = ", hex(args.tag1_loc))
+    debug_print(".header_loc = ", hex(args.header_loc))
+    if args.rw_loc < 0:
+        debug_print(".rw_loc = ", args.rw_loc)
+    else:
+        debug_print(".rw_loc = ", hex(args.rw_loc))
+    debug_print(".spi_clock (MHz) = ", args.spi_clock)
+    debug_print(".spi_read_cmd = ", hex(args.spi_read_cmd))
+    debug_print(".test_spi = ", args.test_spi)
+    debug_print(".test_ecrw = ", args.test_ecrw)
+    debug_print(".verbose = ", args.verbose)
+    debug_print(".spi_drive_str = ", args.spi_drive_str)
+    debug_print(".spi_slew_fast = ", args.spi_slew_fast)
+    debug_print(".spi_cpol = ", args.spi_cpol)
+    debug_print(".spi_cpha_mosi = ", args.spi_cpha_mosi)
+    debug_print(".spi_cpha_miso = ", args.spi_cpha_miso)
+    debug_print(".vtr2_V18 = ", args.vtr2_V18)
+    debug_print(".vtr3_V18 = ", args.vtr3_V18)
+
+
+#
+# Handle quiet mode build from Makefile
+# Quiet mode when V is unset or V=0
+# Verbose mode when V=1
+#
+# MEC152x SPI Image Generator
+# No authentication
+# No payload encryption
+#
+# SPI Offset 0x0 = TAG0 points to Header for EC-RO FW
+# SPI Offset 0x4 = TAG1 points to Header for EC-RO FW
+# TAG Size = 4 bytes
+#  bits[23:0] = bits[31:8] of Header SPI offset
+#  bits[31:24] = CRC8-ITU checksum of bits[23:0].
+#
+# MEC152X SPI header and payload layout for minimum size
+# header offset aligned on 256 byte boundary
+# header_spi_address:
+#   header[0:0x4F] = Header data
+#   header[0x50:0x80] = ECDSA-P384 public key x for Header authentication
+#   header[0x80:0xB0] = ECDSA-P384 public key y for Header authentication
+#   header[0xB0:0xE0] = SHA384 digest of header[0:0xB0]
+#   header[0xE0:0x110] = ECDSA-P384-SHA384 Signature.R of header[0:0xB0]
+#   header[0x110:0x140] = ECDSA-P384-SHA384 Signature.S of header[0:0xB0]
+# payload_spi_address = header_spi_address + len(Header)
+#       Payload had been padded such that len(padded_payload) % 128 == 0
+#   padded_payload[padded_payload_len]
+# payload_signature_address = payload_spi_address + len(padded_payload)
+#  payload_encryption_key_header[128] Not present if encryption disabled
+#  payload_cosignature[96] = 0 if Authentication is disabled
+#  payload_trailer[160] = SHA384(padded_payload ||
+#                                optional payload_encryption_key_header)
+#                       || 48 * [0]
+#                       || 48 * [0]
+#
+def main():
+    global debug_print
+
+    args = parseargs()
+
+    if args.verbose:
+        debug_print = print
+
+    debug_print("Begin pack_ec_mec152x.py script")
+
+    print_args(args)
+
+    chip_dict = MEC152X_DICT
+
+    # Boot-ROM requires header location aligned >= 256 bytes.
+    # CrOS EC flash image update code requires EC_RO/RW location to be aligned
+    # on a flash erase size boundary and EC_RO/RW size to be a multiple of
+    # the smallest flash erase block size.
+    #
+    assert (args.header_loc % SPI_ERASE_BLOCK_SIZE) == 0, (
+        "Header location %d is not on a flash erase block boundary boundary"
+        % args.header_loc
+    )
+
+    max_image_size = CHIP_MAX_CODE_SRAM_KB - LFW_SIZE
+    if args.test_spi:
+        max_image_size -= 32  # SHA256 digest
+
+    assert args.image_size > max_image_size, (
+        "Image size exceeds maximum" % args.image_size
+    )
+
+    spi_size = args.spi_size * 1024
+    debug_print("SPI Flash image size in bytes =", hex(spi_size))
+
+    # !!! IMPORTANT !!!
+    # These values MUST match chip/mchp/config_flash_layout.h
+    # defines.
+    # MEC152x Boot-ROM TAGs are at offset 0 and 4.
+    # lfw + EC_RO starts at beginning of second 4KB sector
+    # EC_RW starts at (flash size / 2) i.e. 0x40000 for a 512KB flash.
+
+    spi_list = []
+
+    debug_print("args.input = ", args.input)
+    debug_print("args.loader_file = ", args.loader_file)
+    debug_print("args.image_size = ", hex(args.image_size))
+
+    rorofile = PacklfwRoImage(args.input, args.loader_file, args.image_size)
+    debug_print("Temporary file containing LFW + EC_RO is ", rorofile)
+
+    lfw_ecro = GetPayload(rorofile, chip_dict["PAD_SIZE"])
+    lfw_ecro_len = len(lfw_ecro)
+    debug_print("Padded LFW + EC_RO length = ", hex(lfw_ecro_len))
+
+    # SPI test mode compute CRC32 of EC_RO and store in last 4 bytes
+    if args.test_spi:
+        crc32_ecro = zlib.crc32(bytes(lfw_ecro[LFW_SIZE:-4]))
+        crc32_ecro_bytes = crc32_ecro.to_bytes(4, byteorder="little")
+        lfw_ecro[-4:] = crc32_ecro_bytes
+        debug_print("ecro len = ", hex(len(lfw_ecro) - LFW_SIZE))
+        debug_print("CRC32(ecro-4) = ", hex(crc32_ecro))
+
+    # Reads entry point from offset 4 of file.
+    # This assumes binary has Cortex-M4 vector table at offset 0.
+    # 32-bit word at offset 0x0 initial stack pointer value
+    # 32-bit word at offset 0x4 address of reset handler
+    # NOTE: reset address will have bit[0]=1 to ensure thumb mode.
+    lfw_ecro_entry = GetEntryPoint(rorofile)
+
+    # Chromebooks are not using MEC BootROM SPI header/payload authentication
+    # or payload encryption. In this case the header authentication signature
+    # is filled with the hash digest of the respective entity.
+    # BuildHeader2 computes the hash digest and stores it in the correct
+    # header location.
+    header = BuildHeader2(
+        args, chip_dict, lfw_ecro_len, LOAD_ADDR, lfw_ecro_entry
+    )
+    printByteArrayAsHex(header, "Header(lfw_ecro)")
+
+    ec_info_block = GenEcInfoBlock(args, chip_dict)
+    printByteArrayAsHex(ec_info_block, "EC Info Block")
+
+    cosignature = GenCoSignature(args, chip_dict, lfw_ecro)
+    printByteArrayAsHex(cosignature, "LFW + EC_RO cosignature")
+
+    trailer = GenTrailer(
+        args, chip_dict, lfw_ecro, None, ec_info_block, cosignature
+    )
+
+    printByteArrayAsHex(trailer, "LFW + EC_RO trailer")
+
+    # Build TAG0. Set TAG1=TAG0 Boot-ROM is allowed to load EC-RO only.
+    tag0 = BuildTag(args)
+    tag1 = tag0
+
+    debug_print("Call to GetPayloadFromOffset")
+    debug_print("args.input = ", args.input)
+    debug_print("args.image_size = ", hex(args.image_size))
+
+    ecrw = GetPayloadFromOffset(
+        args.input, args.image_size, chip_dict["PAD_SIZE"]
+    )
+    debug_print("type(ecrw) is ", type(ecrw))
+    debug_print("len(ecrw) is ", hex(len(ecrw)))
+
+    # truncate to args.image_size
+    ecrw_len = len(ecrw)
+    if ecrw_len > args.image_size:
+        debug_print(
+            "Truncate EC_RW len={0:0x} to image_size={1:0x}".format(
+                ecrw_len, args.image_size
+            )
+        )
+        ecrw = ecrw[: args.image_size]
+        ecrw_len = len(ecrw)
+
+    debug_print("len(EC_RW) = ", hex(ecrw_len))
+
+    # SPI test mode compute CRC32 of EC_RW and store in last 4 bytes
+    if args.test_spi:
+        crc32_ecrw = zlib.crc32(bytes(ecrw[0:-4]))
+        crc32_ecrw_bytes = crc32_ecrw.to_bytes(4, byteorder="little")
+        ecrw[-4:] = crc32_ecrw_bytes
+        debug_print("ecrw len = ", hex(len(ecrw)))
+        debug_print("CRC32(ecrw) = ", hex(crc32_ecrw))
+
+    # Assume FW layout is standard Cortex-M style with vector
+    # table at start of binary.
+    # 32-bit word at offset 0x0 = Initial stack pointer
+    # 32-bit word at offset 0x4 = Address of reset handler
+    ecrw_entry_tuple = struct.unpack_from("<I", ecrw, 4)
+    debug_print("ecrw_entry_tuple[0] = ", hex(ecrw_entry_tuple[0]))
+
+    ecrw_entry = ecrw_entry_tuple[0]
+    debug_print("ecrw_entry = ", hex(ecrw_entry))
+
+    # Note: payload_rw is a bytearray therefore is mutable
+    if args.test_ecrw:
+        gen_test_ecrw(ecrw)
+
+    os.remove(rorofile)  # clean up the temp file
+
+    # MEC152X Add TAG's
+    spi_list.append((args.tag0_loc, tag0, "tag0"))
+    spi_list.append((args.tag1_loc, tag1, "tag1"))
+
+    # flashmap is non-zero only for systems with two external
+    # SPI flash chips.
+    flashmap = BuildFlashMap(0)
+    spi_list.append((8, flashmap, "flashmap"))
+
+    # Boot-ROM SPI image header for LFW+EC-RO
+    spi_list.append((args.header_loc, header, "header(lfw + ro)"))
+    spi_list.append(
+        (args.header_loc + chip_dict["PAYLOAD_OFFSET"], lfw_ecro, "lfw_ecro")
+    )
+
+    offset = args.header_loc + chip_dict["PAYLOAD_OFFSET"] + lfw_ecro_len
+
+    if ec_info_block != None:
+        spi_list.append((offset, ec_info_block, "EC Info Block"))
+        offset += len(ec_info_block)
+
+    if cosignature != None:
+        spi_list.append((offset, cosignature, "ECRO Cosignature"))
+        offset += len(cosignature)
+
+    if trailer != None:
+        spi_list.append((offset, trailer, "ECRO Trailer"))
+        offset += len(trailer)
+
+    # EC_RW location
+    rw_offset = int(spi_size // 2)
+    if args.rw_loc >= 0:
+        rw_offset = args.rw_loc
+
+    debug_print("rw_offset = 0x{0:08x}".format(rw_offset))
+
+    assert rw_offset >= offset, print(
+        """Offset of EC_RW at {0:08x} overlaps end
+               of EC_RO at {1:08x}""".format(
+            rw_offset, offset
+        )
+    )
+
+    spi_list.append((rw_offset, ecrw, "ecrw"))
+    offset = rw_offset + len(ecrw)
+
+    spi_list = sorted(spi_list)
+
+    dumpsects(spi_list)
+
+    #
+    # MEC152X Boot-ROM locates TAG0/1 at SPI offset 0
+    # instead of end of SPI.
+    #
+    with open(args.output, "wb") as f:
+        debug_print("Write spi list to file", args.output)
+        addr = 0
+        for s in spi_list:
+            if addr < s[0]:
+                debug_print(
+                    "Offset ",
+                    hex(addr),
+                    " Length",
+                    hex(s[0] - addr),
+                    "fill with 0xff",
+                )
+                f.write(b"\xff" * (s[0] - addr))
+                addr = s[0]
+                debug_print(
+                    "Offset ",
+                    hex(addr),
+                    " Length",
+                    hex(len(s[1])),
+                    "write data",
+                )
+
+            f.write(s[1])
+            addr += len(s[1])
+
+        if addr < spi_size:
+            debug_print(
+                "Offset ",
+                hex(addr),
+                " Length",
+                hex(spi_size - addr),
+                "fill with 0xff",
+            )
+            f.write(b"\xff" * (spi_size - addr))
+
+        f.flush()
+
+
+if __name__ == "__main__":
+    main()
diff --git a/chip/mchp/util/pack_ec_mec172x.py b/chip/mchp/util/pack_ec_mec172x.py
new file mode 100755
index 0000000000..a8e867888c
--- /dev/null
+++ b/chip/mchp/util/pack_ec_mec172x.py
@@ -0,0 +1,1001 @@
+#!/usr/bin/env python3
+
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# A script to pack EC binary into SPI flash image for MEC172x
+# Based on MEC172x_ROM_Description.pdf revision 6/8/2020
+import argparse
+import hashlib
+import os
+import struct
+import subprocess
+import tempfile
+import zlib  # CRC32
+
+
+# MEC172x has 416KB SRAM from 0xC0000 - 0x127FFF
+# SRAM is divided into contiguous CODE & DATA
+# CODE at [0xC0000, 0x117FFF] DATA at [0x118000, 0x127FFF]
+# Google EC SPI flash size for board is currently 512KB
+# split into 1/2.
+# EC_RO: 0 - 0x3FFFF
+# EC_RW: 0x40000 - 0x7FFFF
+#
+SPI_ERASE_BLOCK_SIZE = 0x1000
+SPI_CLOCK_LIST = [48, 24, 16, 12, 96]
+SPI_READ_CMD_LIST = [0x3, 0xB, 0x3B, 0x6B]
+SPI_DRIVE_STR_DICT = {2: 0, 4: 1, 8: 2, 12: 3}
+# Maximum EC_RO/EC_RW code size is based upon SPI flash erase
+# sector size, MEC172x Boot-ROM TAG, Header, Footer.
+# SPI Offset      Description
+# 0x00 - 0x07     TAG0 and TAG1
+# 0x1000 - 0x113F Boot-ROM SPI Header
+# 0x1140 - 0x213F 4KB LFW
+# 0x2040 - 0x3EFFF
+# 0x3F000 - 0x3FFFF BootROM EC_INFO_BLK || COSIG || ENCR_KEY_HDR(optional) || TRAILER
+CHIP_MAX_CODE_SRAM_KB = 256 - 12
+
+MEC172X_DICT = {
+    "LFW_SIZE": 0x1000,
+    "LOAD_ADDR": 0xC0000,
+    "TAG_SIZE": 4,
+    "KEY_BLOB_SIZE": 1584,
+    "HEADER_SIZE": 0x140,
+    "HEADER_VER": 0x03,
+    "PAYLOAD_GRANULARITY": 128,
+    "PAYLOAD_PAD_BYTE": b"\xff",
+    "EC_INFO_BLK_SZ": 128,
+    "ENCR_KEY_HDR_SZ": 128,
+    "COSIG_SZ": 96,
+    "TRAILER_SZ": 160,
+    "TAILER_PAD_BYTE": b"\xff",
+    "PAD_SIZE": 128,
+}
+
+CRC_TABLE = [
+    0x00,
+    0x07,
+    0x0E,
+    0x09,
+    0x1C,
+    0x1B,
+    0x12,
+    0x15,
+    0x38,
+    0x3F,
+    0x36,
+    0x31,
+    0x24,
+    0x23,
+    0x2A,
+    0x2D,
+]
+
+
+def mock_print(*args, **kwargs):
+    pass
+
+
+debug_print = mock_print
+
+# Debug helper routine
+def dumpsects(spi_list):
+    debug_print("spi_list has {0} entries".format(len(spi_list)))
+    for s in spi_list:
+        debug_print("0x{0:x} 0x{1:x} {2:s}".format(s[0], len(s[1]), s[2]))
+
+
+def printByteArrayAsHex(ba, title):
+    debug_print(title, "= ")
+    if ba == None:
+        debug_print("None")
+        return
+
+    count = 0
+    for b in ba:
+        count = count + 1
+        debug_print("0x{0:02x}, ".format(b), end="")
+        if (count % 8) == 0:
+            debug_print("")
+    debug_print("")
+
+
+def Crc8(crc, data):
+    """Update CRC8 value."""
+    for v in data:
+        crc = ((crc << 4) & 0xFF) ^ (CRC_TABLE[(crc >> 4) ^ (v >> 4)])
+        crc = ((crc << 4) & 0xFF) ^ (CRC_TABLE[(crc >> 4) ^ (v & 0xF)])
+    return crc ^ 0x55
+
+
+def GetEntryPoint(payload_file):
+    """Read entry point from payload EC image."""
+    with open(payload_file, "rb") as f:
+        f.seek(4)
+        s = f.read(4)
+    return int.from_bytes(s, byteorder="little")
+
+
+def GetPayloadFromOffset(payload_file, offset, chip_dict):
+    """Read payload and pad it to chip_dict["PAD_SIZE"]."""
+    padsize = chip_dict["PAD_SIZE"]
+    with open(payload_file, "rb") as f:
+        f.seek(offset)
+        payload = bytearray(f.read())
+    rem_len = len(payload) % padsize
+    debug_print(
+        "GetPayload: padsize={0:0x} len(payload)={1:0x} rem={2:0x}".format(
+            padsize, len(payload), rem_len
+        )
+    )
+
+    if rem_len:
+        payload += chip_dict["PAYLOAD_PAD_BYTE"] * (padsize - rem_len)
+        debug_print(
+            "GetPayload: Added {0} padding bytes".format(padsize - rem_len)
+        )
+
+    return payload
+
+
+def GetPayload(payload_file, chip_dict):
+    """Read payload and pad it to chip_dict["PAD_SIZE"]"""
+    return GetPayloadFromOffset(payload_file, 0, chip_dict)
+
+
+def GetPublicKey(pem_file):
+    """Extract public exponent and modulus from PEM file."""
+    result = subprocess.run(
+        ["openssl", "rsa", "-in", pem_file, "-text", "-noout"],
+        stdout=subprocess.PIPE,
+        encoding="utf-8",
+    )
+    modulus_raw = []
+    in_modulus = False
+    for line in result.stdout.splitlines():
+        if line.startswith("modulus"):
+            in_modulus = True
+        elif not line.startswith(" "):
+            in_modulus = False
+        elif in_modulus:
+            modulus_raw.extend(line.strip().strip(":").split(":"))
+        if line.startswith("publicExponent"):
+            exp = int(line.split(" ")[1], 10)
+    modulus_raw.reverse()
+    modulus = bytearray((int(x, 16) for x in modulus_raw[:256]))
+    return struct.pack("<Q", exp), modulus
+
+
+def GetSpiClockParameter(args):
+    assert args.spi_clock in SPI_CLOCK_LIST, (
+        "Unsupported SPI clock speed %d MHz" % args.spi_clock
+    )
+    return SPI_CLOCK_LIST.index(args.spi_clock)
+
+
+def GetSpiReadCmdParameter(args):
+    assert args.spi_read_cmd in SPI_READ_CMD_LIST, (
+        "Unsupported SPI read command 0x%x" % args.spi_read_cmd
+    )
+    return SPI_READ_CMD_LIST.index(args.spi_read_cmd)
+
+
+def GetEncodedSpiDriveStrength(args):
+    assert args.spi_drive_str in SPI_DRIVE_STR_DICT, (
+        "Unsupported SPI drive strength %d mA" % args.spi_drive_str
+    )
+    return SPI_DRIVE_STR_DICT.get(args.spi_drive_str)
+
+
+# Return 0=Slow slew rate or 1=Fast slew rate
+def GetSpiSlewRate(args):
+    if args.spi_slew_fast == True:
+        return 1
+    return 0
+
+
+# Return SPI CPOL = 0 or 1
+def GetSpiCpol(args):
+    if args.spi_cpol == 0:
+        return 0
+    return 1
+
+
+# Return SPI CPHA_MOSI
+# 0 = SPI Master drives data is stable on inactive to clock edge
+# 1 = SPI Master drives data is stable on active to inactive clock edge
+def GetSpiCphaMosi(args):
+    if args.spi_cpha_mosi == 0:
+        return 0
+    return 1
+
+
+# Return SPI CPHA_MISO 0 or 1
+# 0 = SPI Master samples data on inactive to active clock edge
+# 1 = SPI Master samples data on active to inactive clock edge
+def GetSpiCphaMiso(args):
+    if args.spi_cpha_miso == 0:
+        return 0
+    return 1
+
+
+def PadZeroTo(data, size):
+    data.extend(b"\0" * (size - len(data)))
+
+
+#
+# Build SPI image header for MEC172x
+# MEC172x image header size = 320(0x140) bytes
+#
+# Description using Python slice notation [start:start+len]
+#
+# header[0:4] = 'PHCM'
+# header[4] = header version = 0x03(MEC172x)
+# header[5] = SPI clock speed, drive strength, sampling mode
+#   bits[1:0] = SPI clock speed: 0=48, 1=24, 2=16, 3=12
+#   bits[3:2] = SPI controller pins drive strength
+#               00b=2mA, 01b=4mA, 10b=8mA, 11b=12mA
+#   bit[4] = SPI controller pins slew rate: 0=slow, 1=fast
+#   bit[5] = SPI CPOL: 0=SPI clock idle is low, 1=idle is high
+#   bit[6] = CHPHA_MOSI
+#       1:data change on first inactive to active clock edge
+#       0:data change on first active to inactive clock edge
+#   bit[7] = CHPHA_MISO:
+#       1: Data captured on first inactive to active clock edge
+#       0: Data captured on first active to inactive clock edge
+# header[6] Boot-ROM loader flags
+#   bits[0] = 0(use header[5] b[1:0]), 1(96 MHz)
+#   bits[2:1] = 0 reserved
+#   bits[5:3] = 111b
+#   bit[6]: For MEC172x controls authentication
+#           0=Authentication disabled. Signature is SHA-384 of FW payload
+#           1=Authentication enabled. Signature is ECDSA P-384
+#   bit[7]: 0=FW pyload not encrypted, 1=FW payload is encrypted
+# header[7]: SPI Flash read command
+#            0 -> 0x03 1-1-1 read freq < 33MHz
+#            1 -> 0x0B 1-1-1 + 8 clocks(data tri-stated)
+#            2 -> 0x3B 1-1-2 + 8 clocks(data tri-stated). Data phase is dual I/O
+#            3 -> 0x6B 1-1-4 + 8 clocks(data tri-stated). Data phase is Quad I/O
+#            NOTE: Quad requires SPI flash device QE(quad enable) bit
+#            to be factory set. Enabling QE disables HOLD# and WP#
+#            functionality of the SPI flash device.
+# header[0x8:0xC] SRAM Load address little-endian format
+# header[0xC:0x10] SRAM FW entry point. Boot-ROM jumps to
+#                  this address on successful load. (little-endian)
+# header[0x10:0x12] little-endian format: FW binary size in units of
+#                   128 bytes(MEC172x)
+# header[0x12:0x14] = 0 reserved
+# header[0x14:0x18] = Little-ending format: Unsigned offset from start of
+#                     header to FW payload.
+#                     MEC172x: Offset must be a multiple of 128
+#                     Offset must be >= header size.
+#                     NOTE: If Authentication is enabled size includes
+#                     the appended signature.
+# MEC172x:
+# header[0x18] = Authentication key select. Set to 0 for no Authentication.
+# header[0x19] = SPI flash device(s) drive strength feature flags
+#                 b[0]=1 SPI flash device 0 has drive strength feature
+#                 b[1]=SPI flash 0: DrvStr Write format(0=2 bytes, 1=1 byte)
+#                 b[2]=1 SPI flash device 1 has drive strength feature
+#                 b[3]=SPI flash 1: DrvStr Write format(0=2 bytes, 1=1 byte)
+#                 b[7:4] = 0 reserved
+# header[0x1A:0x20] = 0 reserved
+# header[0x20] = SPI opcode to read drive strength from SPI flash 0
+# header[0x21] = SPI opcode to write drive strength to SPI flash 0
+# header[0x22] = SPI flash 0: drvStr value
+# header[0x23] = SPI flash 0: drvStr mask
+# header[0x24] = SPI opcode to read drive strength from SPI flash 1
+# header[0x25] = SPI opcode to write drive strength to SPI flash 1
+# header[0x26] = SPI flash 1: drvStr value
+# header[0x27] = SPI flash 1: drvStr mask
+# header[0x28:0x48] = reserved, may be any value
+# header[0x48:0x50] = reserved for customer use
+# header[0x50:0x80] = ECDSA-384 public key x-coord. = 0 Auth. disabled
+# header[0x80:0xB0] = ECDSA-384 public key y-coord. = 0 Auth. disabled
+# header[0xB0:0xE0] = SHA-384 digest of header[0:0xB0]
+# header[0xE0:0x110] = Header ECDSA-384 signature x-coord. = 0 Auth. disabled
+# header[0x110:0x140] = Header ECDSA-384 signature y-coor. = 0 Auth. disabled
+#
+def BuildHeader2(args, chip_dict, payload_len, load_addr, payload_entry):
+    header_size = chip_dict["HEADER_SIZE"]
+
+    # allocate zero filled header
+    header = bytearray(b"\x00" * header_size)
+    debug_print("len(header) = ", len(header))
+
+    # Identifier and header version
+    header[0:4] = b"PHCM"
+    header[4] = chip_dict["HEADER_VER"]
+
+    # SPI frequency, drive strength, CPOL/CPHA encoding same for both chips
+    spiFreqIndex = GetSpiClockParameter(args)
+    if spiFreqIndex > 3:
+        header[6] |= 0x01
+    else:
+        header[5] = spiFreqIndex
+
+    header[5] |= (GetEncodedSpiDriveStrength(args) & 0x03) << 2
+    header[5] |= (GetSpiSlewRate(args) & 0x01) << 4
+    header[5] |= (GetSpiCpol(args) & 0x01) << 5
+    header[5] |= (GetSpiCphaMosi(args) & 0x01) << 6
+    header[5] |= (GetSpiCphaMiso(args) & 0x01) << 7
+
+    # header[6]
+    # b[0] value set above
+    # b[2:1] = 00b, b[5:3]=111b
+    # b[7]=0 No encryption of FW payload
+    header[6] |= 0x7 << 3
+
+    # SPI read command set same for both chips
+    header[7] = GetSpiReadCmdParameter(args) & 0xFF
+
+    # bytes 0x08 - 0x0b
+    header[0x08:0x0C] = load_addr.to_bytes(4, byteorder="little")
+    # bytes 0x0c - 0x0f
+    header[0x0C:0x10] = payload_entry.to_bytes(4, byteorder="little")
+
+    # bytes 0x10 - 0x11 payload length in units of 128 bytes
+    assert payload_len % chip_dict["PAYLOAD_GRANULARITY"] == 0, print(
+        "Payload size not a multiple of {0}".format(
+            chip_dict["PAYLOAD_GRANULARITY"]
+        )
+    )
+
+    payload_units = int(payload_len // chip_dict["PAYLOAD_GRANULARITY"])
+    assert payload_units < 0x10000, print(
+        "Payload too large: len={0} units={1}".format(
+            payload_len, payload_units
+        )
+    )
+
+    header[0x10:0x12] = payload_units.to_bytes(2, "little")
+
+    # bytes 0x14 - 0x17 TODO offset from start of payload to FW payload to be
+    # loaded by Boot-ROM. We ask Boot-ROM to load (LFW || EC_RO).
+    # LFW location provided on the command line.
+    assert args.lfw_loc % 4096 == 0, print(
+        "LFW location not on a 4KB boundary! 0x{0:0x}".format(args.lfw_loc)
+    )
+
+    assert args.lfw_loc >= (args.header_loc + chip_dict["HEADER_SIZE"]), print(
+        "LFW location not greater than header location + header size"
+    )
+
+    lfw_ofs = args.lfw_loc - args.header_loc
+    header[0x14:0x18] = lfw_ofs.to_bytes(4, "little")
+
+    # MEC172x: authentication key select. Authentication not used, set to 0.
+    header[0x18] = 0
+
+    # header[0x19], header[0x20:0x28]
+    # header[0x1A:0x20] reserved 0
+    # MEC172x: supports SPI flash devices with drive strength settings
+    # TODO leave these fields at 0 for now. We must add 6 command line
+    # arguments.
+
+    # header[0x28:0x48] reserve can be any value
+    # header[0x48:0x50] Customer use. TODO
+    # authentication disabled, leave these 0.
+    # header[0x50:0x80] ECDSA P384 Authentication Public key Rx
+    # header[0x80:0xB0] ECDSA P384 Authentication Public key Ry
+
+    # header[0xB0:0xE0] = SHA384(header[0:0xB0])
+    header[0xB0:0xE0] = hashlib.sha384(header[0:0xB0]).digest()
+    # When ECDSA authentication is disabled MCHP SPI image generator
+    # is filling the last 48 bytes of the Header with 0xff
+    header[-48:] = b"\xff" * 48
+
+    debug_print("After hash: len(header) = ", len(header))
+
+    return header
+
+
+#
+# MEC172x 128-byte EC Info Block appended to end of padded FW binary.
+# Python slice notation
+# byte[0:0x64] are undefined, we set to 0xFF
+# byte[0x64] = FW Build LSB
+# byte[0x65] = FW Build MSB
+# byte[0x66:0x68] = undefined, set to 0xFF
+# byte[0x68:0x78] = Roll back permissions bit maps
+# byte[0x78:0x7c] = key revocation bit maps
+# byte[0x7c] = platform ID LSB
+# byte[0x7d] = platform ID MSB
+# byte[0x7e] = auto-rollback protection enable
+# byte[0x7f] = current imeage revision
+#
+def GenEcInfoBlock(args, chip_dict):
+    # ecinfo = bytearray([0xff] * chip_dict["EC_INFO_BLK_SZ"])
+    ecinfo = bytearray(chip_dict["EC_INFO_BLK_SZ"])
+    return ecinfo
+
+
+#
+# Generate SPI FW image co-signature.
+# MEC172x cosignature is 96 bytes used by OEM FW
+# developer to sign their binary with ECDSA-P384-SHA384 or
+# some other signature algorithm that fits in 96 bytes.
+# At this time Cros-EC is not using this field, fill with 0xFF.
+# If this feature is implemented we need to read the OEM's
+# generated signature from a file and extract the binary
+# signature.
+#
+def GenCoSignature(args, chip_dict, payload):
+    return bytearray(b"\xff" * chip_dict["COSIG_SZ"])
+
+
+#
+# Generate SPI FW Image trailer.
+# MEC172x: Size = 160 bytes
+#   binary = payload || encryption_key_header || ec_info_block || cosignature
+#   trailer[0:48] = SHA384(binary)
+#   trailer[48:144] = 0xFF
+#   trailer[144:160] = 0xFF. Boot-ROM spec. says these bytes should be random.
+#       Authentication & encryption are not used therefore random data
+#       is not necessary.
+def GenTrailer(
+    args, chip_dict, payload, encryption_key_header, ec_info_block, cosignature
+):
+    debug_print("GenTrailer SHA384 computation")
+    trailer = bytearray(chip_dict["TAILER_PAD_BYTE"] * chip_dict["TRAILER_SZ"])
+    hasher = hashlib.sha384()
+    hasher.update(payload)
+    debug_print("  Update: payload len=0x{0:0x}".format(len(payload)))
+    if ec_info_block != None:
+        hasher.update(ec_info_block)
+        debug_print(
+            "  Update: ec_info_block len=0x{0:0x}".format(len(ec_info_block))
+        )
+    if encryption_key_header != None:
+        hasher.update(encryption_key_header)
+        debug_print(
+            "  Update: encryption_key_header len=0x{0:0x}".format(
+                len(encryption_key_header)
+            )
+        )
+    if cosignature != None:
+        hasher.update(cosignature)
+        debug_print(
+            "  Update: cosignature len=0x{0:0x}".format(len(cosignature))
+        )
+    trailer[0:48] = hasher.digest()
+    trailer[-16:] = 16 * b"\xff"
+
+    return trailer
+
+
+# MEC172x supports two 32-bit Tags located at offsets 0x0 and 0x4
+# in the SPI flash.
+# Tag format:
+#   bits[23:0] correspond to bits[31:8] of the Header SPI address
+#       Header is always on a 256-byte boundary.
+#   bits[31:24] = CRC8-ITU of bits[23:0].
+# Notice there is no chip-select field in the Tag both Tag's point
+# to the same flash part.
+#
+def BuildTag(args):
+    tag = bytearray(
+        [
+            (args.header_loc >> 8) & 0xFF,
+            (args.header_loc >> 16) & 0xFF,
+            (args.header_loc >> 24) & 0xFF,
+        ]
+    )
+    tag.append(Crc8(0, tag))
+    return tag
+
+
+def BuildTagFromHdrAddr(header_loc):
+    tag = bytearray(
+        [
+            (header_loc >> 8) & 0xFF,
+            (header_loc >> 16) & 0xFF,
+            (header_loc >> 24) & 0xFF,
+        ]
+    )
+    tag.append(Crc8(0, tag))
+    return tag
+
+
+# FlashMap is an option for MEC172x
+# It is a 32 bit structure
+# bits[18:0] = bits[30:12] of second SPI flash base address
+# bits[23:19] = 0 reserved
+# bits[31:24] = CRC8 of bits[23:0]
+# Input:
+#   integer containing base address of second SPI flash
+#   This value is usually equal to the size of the first
+#   SPI flash and should be a multiple of 4KB
+# Output:
+#   bytearray of length 4
+def BuildFlashMap(secondSpiFlashBaseAddr):
+    flashmap = bytearray(4)
+    flashmap[0] = (secondSpiFlashBaseAddr >> 12) & 0xFF
+    flashmap[1] = (secondSpiFlashBaseAddr >> 20) & 0xFF
+    flashmap[2] = (secondSpiFlashBaseAddr >> 28) & 0xFF
+    flashmap[3] = Crc8(0, flashmap)
+    return flashmap
+
+
+#
+# Creates temporary file for read/write
+# Reads binary file containing LFW image_size (loader_file)
+# Writes LFW image to temporary file
+# Reads RO image at beginning of rorw_file up to image_size
+#  (assumes RO/RW images have been padded with 0xFF
+# Returns temporary file name
+#
+def PacklfwRoImage(rorw_file, loader_file, image_size):
+    """Create a temp file with the
+    first image_size bytes from the loader file and append bytes
+    from the rorw file.
+    return the filename"""
+    fo = tempfile.NamedTemporaryFile(delete=False)  # Need to keep file around
+    with open(loader_file, "rb") as fin1:  # read 4KB loader file
+        pro = fin1.read()
+    fo.write(pro)  # write 4KB loader data to temp file
+    with open(rorw_file, "rb") as fin:
+        ro = fin.read(image_size)
+
+    fo.write(ro)
+    fo.close()
+
+    return fo.name
+
+
+#
+# Generate a test EC_RW image of same size
+# as original.
+# Preserve image_data structure and fill all
+# other bytes with 0xA5.
+# useful for testing SPI read and EC build
+# process hash generation.
+#
+def gen_test_ecrw(pldrw):
+    debug_print("gen_test_ecrw: pldrw type =", type(pldrw))
+    debug_print("len pldrw =", len(pldrw), " = ", hex(len(pldrw)))
+    cookie1_pos = pldrw.find(b"\x99\x88\x77\xce")
+    cookie2_pos = pldrw.find(b"\xdd\xbb\xaa\xce", cookie1_pos + 4)
+    t = struct.unpack("<L", pldrw[cookie1_pos + 0x24 : cookie1_pos + 0x28])
+    size = t[0]
+    debug_print("EC_RW size =", size, " = ", hex(size))
+
+    debug_print("Found cookie1 at ", hex(cookie1_pos))
+    debug_print("Found cookie2 at ", hex(cookie2_pos))
+
+    if cookie1_pos > 0 and cookie2_pos > cookie1_pos:
+        for i in range(0, cookie1_pos):
+            pldrw[i] = 0xA5
+        for i in range(cookie2_pos + 4, len(pldrw)):
+            pldrw[i] = 0xA5
+
+    with open("ec_RW_test.bin", "wb") as fecrw:
+        fecrw.write(pldrw[:size])
+
+
+def parseargs():
+    rpath = os.path.dirname(os.path.relpath(__file__))
+
+    parser = argparse.ArgumentParser()
+    parser.add_argument(
+        "-i",
+        "--input",
+        help="EC binary to pack, usually ec.bin or ec.RO.flat.",
+        metavar="EC_BIN",
+        default="ec.bin",
+    )
+    parser.add_argument(
+        "-o",
+        "--output",
+        help="Output flash binary file",
+        metavar="EC_SPI_FLASH",
+        default="ec.packed.bin",
+    )
+    parser.add_argument(
+        "--loader_file", help="EC loader binary", default="ecloader.bin"
+    )
+    parser.add_argument(
+        "--load_addr", type=int, help="EC SRAM load address", default=0xC0000
+    )
+    parser.add_argument(
+        "-s",
+        "--spi_size",
+        type=int,
+        help="Size of the SPI flash in KB",
+        default=512,
+    )
+    parser.add_argument(
+        "-l",
+        "--header_loc",
+        type=int,
+        help="Location of header in SPI flash. Must be on a 256 byte boundary",
+        default=0x0100,
+    )
+    parser.add_argument(
+        "--lfw_loc",
+        type=int,
+        help="Location of LFW in SPI flash. Must be on a 4KB boundary",
+        default=0x1000,
+    )
+    parser.add_argument(
+        "--lfw_size", type=int, help="LFW size in bytes", default=0x1000
+    )
+    parser.add_argument(
+        "-r",
+        "--rw_loc",
+        type=int,
+        help="Start offset of EC_RW. Default is -1 meaning 1/2 flash size",
+        default=-1,
+    )
+    parser.add_argument(
+        "--spi_clock",
+        type=int,
+        help="SPI clock speed. 8, 12, 24, or 48 MHz.",
+        default=24,
+    )
+    parser.add_argument(
+        "--spi_read_cmd",
+        type=int,
+        help="SPI read command. 0x3, 0xB, 0x3B, or 0x6B.",
+        default=0xB,
+    )
+    parser.add_argument(
+        "--image_size",
+        type=int,
+        help="Size of a single image. Default 244KB",
+        default=(244 * 1024),
+    )
+    parser.add_argument(
+        "--test_spi",
+        action="store_true",
+        help="Test SPI data integrity by adding CRC32 in last 4-bytes of RO/RW binaries",
+        default=False,
+    )
+    parser.add_argument(
+        "--test_ecrw",
+        action="store_true",
+        help="Use fixed pattern for EC_RW but preserve image_data",
+        default=False,
+    )
+    parser.add_argument(
+        "--verbose",
+        action="store_true",
+        help="Enable verbose output",
+        default=False,
+    )
+    parser.add_argument(
+        "--tag0_loc", type=int, help="MEC172x TAG0 SPI offset", default=0
+    )
+    parser.add_argument(
+        "--tag1_loc", type=int, help="MEC172x TAG1 SPI offset", default=4
+    )
+    parser.add_argument(
+        "--spi_drive_str",
+        type=int,
+        help="Chip SPI drive strength in mA: 2, 4, 8, or 12",
+        default=4,
+    )
+    parser.add_argument(
+        "--spi_slew_fast",
+        action="store_true",
+        help="SPI use fast slew rate. Default is False",
+        default=False,
+    )
+    parser.add_argument(
+        "--spi_cpol",
+        type=int,
+        help="SPI clock polarity when idle. Defealt is 0(low)",
+        default=0,
+    )
+    parser.add_argument(
+        "--spi_cpha_mosi",
+        type=int,
+        help="""SPI clock phase controller drives data.
+                              0=Data driven on active to inactive clock edge,
+                              1=Data driven on inactive to active clock edge""",
+        default=0,
+    )
+    parser.add_argument(
+        "--spi_cpha_miso",
+        type=int,
+        help="""SPI clock phase controller samples data.
+                              0=Data sampled on inactive to active clock edge,
+                              1=Data sampled on active to inactive clock edge""",
+        default=0,
+    )
+
+    return parser.parse_args()
+
+
+def print_args(args):
+    debug_print("parsed arguments:")
+    debug_print(".input  = ", args.input)
+    debug_print(".output = ", args.output)
+    debug_print(".loader_file = ", args.loader_file)
+    debug_print(".spi_size (KB) = ", hex(args.spi_size))
+    debug_print(".image_size = ", hex(args.image_size))
+    debug_print(".load_addr", hex(args.load_addr))
+    debug_print(".tag0_loc = ", hex(args.tag0_loc))
+    debug_print(".tag1_loc = ", hex(args.tag1_loc))
+    debug_print(".header_loc = ", hex(args.header_loc))
+    debug_print(".lfw_loc = ", hex(args.lfw_loc))
+    debug_print(".lfw_size = ", hex(args.lfw_size))
+    if args.rw_loc < 0:
+        debug_print(".rw_loc = ", args.rw_loc)
+    else:
+        debug_print(".rw_loc = ", hex(args.rw_loc))
+    debug_print(".spi_clock (MHz) = ", args.spi_clock)
+    debug_print(".spi_read_cmd = ", hex(args.spi_read_cmd))
+    debug_print(".test_spi = ", args.test_spi)
+    debug_print(".test_ecrw = ", args.test_ecrw)
+    debug_print(".verbose = ", args.verbose)
+    debug_print(".spi_drive_str = ", args.spi_drive_str)
+    debug_print(".spi_slew_fast = ", args.spi_slew_fast)
+    debug_print(".spi_cpol = ", args.spi_cpol)
+    debug_print(".spi_cpha_mosi = ", args.spi_cpha_mosi)
+    debug_print(".spi_cpha_miso = ", args.spi_cpha_miso)
+
+
+def spi_list_append(mylist, loc, data, description):
+    """Append SPI data block tuple to list"""
+    t = (loc, data, description)
+    mylist.append(t)
+    debug_print(
+        "Add SPI entry: offset=0x{0:08x} len=0x{1:0x} descr={2}".format(
+            loc, len(data), description
+        )
+    )
+
+
+#
+# Handle quiet mode build from Makefile
+# Quiet mode when V is unset or V=0
+# Verbose mode when V=1
+#
+# MEC172x SPI Image Generator
+# No authentication
+# No payload encryption
+#
+# SPI Offset 0x0 = TAG0 points to Header for EC-RO FW
+# SPI Offset 0x4 = TAG1 points to Header for EC-RO FW
+# TAG Size = 4 bytes
+#  bits[23:0] = bits[31:8] of Header SPI offset
+#  bits[31:24] = CRC8-ITU checksum of bits[23:0].
+#
+# MEC172x SPI header and payload layout for minimum size
+# header offset aligned on 256 byte boundary
+# header_spi_address:
+#   header[0:0x4F] = Header data
+#   header[0x50:0x80] = ECDSA-P384 public key x for Header authentication
+#   header[0x80:0xB0] = ECDSA-P384 public key y for Header authentication
+#   header[0xB0:0xE0] = SHA384 digest of header[0:0xB0]
+#   header[0xE0:0x110] = ECDSA-P384-SHA384 Signature.R of header[0:0xB0]
+#   header[0x110:0x140] = ECDSA-P384-SHA384 Signature.S of header[0:0xB0]
+# payload_spi_address = header_spi_address + len(Header)
+#       Payload had been padded such that len(padded_payload) % 128 == 0
+#   padded_payload[padded_payload_len]
+# payload_signature_address = payload_spi_address + len(padded_payload)
+#  payload_encryption_key_header[128] Not present if encryption disabled
+#  payload_cosignature[96] = 0 if Authentication is disabled
+#  payload_trailer[160] = SHA384(padded_payload ||
+#                                optional payload_encryption_key_header)
+#                       || 48 * [0]
+#                       || 48 * [0]
+#
+def main():
+    global debug_print
+
+    args = parseargs()
+
+    if args.verbose:
+        debug_print = print
+
+    debug_print("Begin pack_ec_mec172x.py script")
+
+    print_args(args)
+
+    chip_dict = MEC172X_DICT
+
+    # Boot-ROM requires header location aligned >= 256 bytes.
+    # CrOS EC flash image update code requires EC_RO/RW location to be aligned
+    # on a flash erase size boundary and EC_RO/RW size to be a multiple of
+    # the smallest flash erase block size.
+
+    spi_size = args.spi_size * 1024
+    spi_image_size = spi_size // 2
+
+    rorofile = PacklfwRoImage(args.input, args.loader_file, args.image_size)
+    debug_print("Temporary file containing LFW + EC_RO is ", rorofile)
+
+    lfw_ecro = GetPayload(rorofile, chip_dict)
+    lfw_ecro_len = len(lfw_ecro)
+    debug_print("Padded LFW + EC_RO length = ", hex(lfw_ecro_len))
+
+    # SPI test mode compute CRC32 of EC_RO and store in last 4 bytes
+    if args.test_spi:
+        crc32_ecro = zlib.crc32(bytes(lfw_ecro[args.lfw_size : -4]))
+        crc32_ecro_bytes = crc32_ecro.to_bytes(4, byteorder="little")
+        lfw_ecro[-4:] = crc32_ecro_bytes
+        debug_print("ecro len = ", hex(len(lfw_ecro) - args.lfw_size))
+        debug_print("CRC32(ecro-4) = ", hex(crc32_ecro))
+
+    # Reads entry point from offset 4 of file.
+    # This assumes binary has Cortex-M4 vector table at offset 0.
+    # 32-bit word at offset 0x0 initial stack pointer value
+    # 32-bit word at offset 0x4 address of reset handler
+    # NOTE: reset address will have bit[0]=1 to ensure thumb mode.
+    lfw_ecro_entry = GetEntryPoint(rorofile)
+    debug_print(
+        "LFW Entry point from GetEntryPoint = 0x{0:08x}".format(lfw_ecro_entry)
+    )
+
+    # Chromebooks are not using MEC BootROM SPI header/payload authentication
+    # or payload encryption. In this case the header authentication signature
+    # is filled with the hash digest of the respective entity.
+    # BuildHeader2 computes the hash digest and stores it in the correct
+    # header location.
+    header = BuildHeader2(
+        args, chip_dict, lfw_ecro_len, args.load_addr, lfw_ecro_entry
+    )
+    printByteArrayAsHex(header, "Header(lfw_ecro)")
+
+    ec_info_block = GenEcInfoBlock(args, chip_dict)
+    printByteArrayAsHex(ec_info_block, "EC Info Block")
+
+    cosignature = GenCoSignature(args, chip_dict, lfw_ecro)
+    printByteArrayAsHex(cosignature, "LFW + EC_RO cosignature")
+
+    trailer = GenTrailer(
+        args, chip_dict, lfw_ecro, None, ec_info_block, cosignature
+    )
+
+    printByteArrayAsHex(trailer, "LFW + EC_RO trailer")
+
+    # Build TAG0. Set TAG1=TAG0 Boot-ROM is allowed to load EC-RO only.
+    tag0 = BuildTag(args)
+    tag1 = tag0
+
+    debug_print("Call to GetPayloadFromOffset")
+    debug_print("args.input = ", args.input)
+    debug_print("args.image_size = ", hex(args.image_size))
+
+    ecrw = GetPayloadFromOffset(args.input, args.image_size, chip_dict)
+    debug_print("type(ecrw) is ", type(ecrw))
+    debug_print("len(ecrw) is ", hex(len(ecrw)))
+
+    # truncate to args.image_size
+    ecrw_len = len(ecrw)
+    if ecrw_len > args.image_size:
+        debug_print(
+            "Truncate EC_RW len={0:0x} to image_size={1:0x}".format(
+                ecrw_len, args.image_size
+            )
+        )
+        ecrw = ecrw[: args.image_size]
+        ecrw_len = len(ecrw)
+
+    debug_print("len(EC_RW) = ", hex(ecrw_len))
+
+    # SPI test mode compute CRC32 of EC_RW and store in last 4 bytes
+    if args.test_spi:
+        crc32_ecrw = zlib.crc32(bytes(ecrw[0:-4]))
+        crc32_ecrw_bytes = crc32_ecrw.to_bytes(4, byteorder="little")
+        ecrw[-4:] = crc32_ecrw_bytes
+        debug_print("ecrw len = ", hex(len(ecrw)))
+        debug_print("CRC32(ecrw) = ", hex(crc32_ecrw))
+
+    # Assume FW layout is standard Cortex-M style with vector
+    # table at start of binary.
+    # 32-bit word at offset 0x0 = Initial stack pointer
+    # 32-bit word at offset 0x4 = Address of reset handler
+    ecrw_entry_tuple = struct.unpack_from("<I", ecrw, 4)
+    debug_print("ecrw_entry_tuple[0] = ", hex(ecrw_entry_tuple[0]))
+
+    ecrw_entry = ecrw_entry_tuple[0]
+    debug_print("ecrw_entry = ", hex(ecrw_entry))
+
+    # Note: payload_rw is a bytearray therefore is mutable
+    if args.test_ecrw:
+        gen_test_ecrw(ecrw)
+
+    os.remove(rorofile)  # clean up the temp file
+
+    spi_list = []
+
+    # MEC172x Add TAG's
+    # spi_list.append((args.tag0_loc, tag0, "tag0"))
+    # spi_list.append((args.tag1_loc, tag1, "tag1"))
+    spi_list_append(spi_list, args.tag0_loc, tag0, "TAG0")
+    spi_list_append(spi_list, args.tag1_loc, tag1, "TAG1")
+
+    # Boot-ROM SPI image header for LFW+EC-RO
+    # spi_list.append((args.header_loc, header, "header(lfw + ro)"))
+    spi_list_append(spi_list, args.header_loc, header, "LFW-EC_RO Header")
+
+    spi_list_append(spi_list, args.lfw_loc, lfw_ecro, "LFW-EC_RO FW")
+
+    offset = args.lfw_loc + len(lfw_ecro)
+    debug_print("SPI offset after LFW_ECRO = 0x{0:08x}".format(offset))
+
+    if ec_info_block != None:
+        spi_list_append(spi_list, offset, ec_info_block, "LFW-EC_RO Info Block")
+        offset += len(ec_info_block)
+
+    debug_print("SPI offset after ec_info_block = 0x{0:08x}".format(offset))
+
+    if cosignature != None:
+        # spi_list.append((offset, co-signature, "ECRO Co-signature"))
+        spi_list_append(spi_list, offset, cosignature, "LFW-EC_RO Co-signature")
+        offset += len(cosignature)
+
+    debug_print("SPI offset after co-signature = 0x{0:08x}".format(offset))
+
+    if trailer != None:
+        # spi_list.append((offset, trailer, "ECRO Trailer"))
+        spi_list_append(spi_list, offset, trailer, "LFW-EC_RO trailer")
+        offset += len(trailer)
+
+    debug_print("SPI offset after trailer = 0x{0:08x}".format(offset))
+
+    # EC_RW location
+    rw_offset = int(spi_size // 2)
+    if args.rw_loc >= 0:
+        rw_offset = args.rw_loc
+
+    debug_print("rw_offset = 0x{0:08x}".format(rw_offset))
+
+    # spi_list.append((rw_offset, ecrw, "ecrw"))
+    spi_list_append(spi_list, rw_offset, ecrw, "EC_RW")
+    offset = rw_offset + len(ecrw)
+
+    spi_list = sorted(spi_list)
+
+    debug_print("Display spi_list:")
+    dumpsects(spi_list)
+
+    #
+    # MEC172x Boot-ROM locates TAG0/1 at SPI offset 0
+    # instead of end of SPI.
+    #
+    with open(args.output, "wb") as f:
+        debug_print("Write spi list to file", args.output)
+        addr = 0
+        for s in spi_list:
+            if addr < s[0]:
+                debug_print(
+                    "Offset ",
+                    hex(addr),
+                    " Length",
+                    hex(s[0] - addr),
+                    "fill with 0xff",
+                )
+                f.write(b"\xff" * (s[0] - addr))
+                addr = s[0]
+                debug_print(
+                    "Offset ",
+                    hex(addr),
+                    " Length",
+                    hex(len(s[1])),
+                    "write data",
+                )
+
+            f.write(s[1])
+            addr += len(s[1])
+
+        if addr < spi_size:
+            debug_print(
+                "Offset ",
+                hex(addr),
+                " Length",
+                hex(spi_size - addr),
+                "fill with 0xff",
+            )
+            f.write(b"\xff" * (spi_size - addr))
+
+        f.flush()
+
+
+if __name__ == "__main__":
+    main()
diff --git a/chip/mchp/watchdog.c b/chip/mchp/watchdog.c
index 0533155e08..50edda70e0 100644
--- a/chip/mchp/watchdog.c
+++ b/chip/mchp/watchdog.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,86 +8,171 @@
 #include "hooks.h"
 #include "registers.h"
 #include "task.h"
-#include "watchdog.h"
 #include "tfdp_chip.h"
+#include "watchdog.h"
 
 void watchdog_reload(void)
 {
 	MCHP_WDG_KICK = 1;
 
-#ifdef CONFIG_WATCHDOG_HELP
-	/* Reload the auxiliary timer */
-	MCHP_TMR16_CTL(0) &= ~BIT(5);
-	MCHP_TMR16_CNT(0) = CONFIG_AUX_TIMER_PERIOD_MS;
-	MCHP_TMR16_CTL(0) |= BIT(5);
-#endif
+	if (IS_ENABLED(CONFIG_WATCHDOG_HELP)) {
+		/* Reload the auxiliary timer */
+		MCHP_TMR16_CTL(0) &= ~BIT(5);
+		MCHP_TMR16_CNT(0) = CONFIG_AUX_TIMER_PERIOD_MS;
+		MCHP_TMR16_CTL(0) |= BIT(5);
+	}
 }
 DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT);
 
-int watchdog_init(void)
+#if defined(CHIP_FAMILY_MEC152X) || defined(CHIP_FAMILY_MEC172X)
+static void wdg_intr_enable(int enable)
 {
-#ifdef CONFIG_WATCHDOG_HELP
-	uint32_t val;
-
-	/*
-	 * Watchdog does not warn us before expiring. Let's use a 16-bit
-	 * timer as an auxiliary timer.
-	 */
+	if (enable) {
+		MCHP_WDG_STATUS = MCHP_WDG_STS_IRQ;
+		MCHP_WDG_IEN = MCHP_WDG_IEN_IRQ_EN;
+		MCHP_WDG_CTL |= MCHP_WDG_RESET_IRQ_EN;
+		MCHP_INT_ENABLE(MCHP_WDG_GIRQ) = MCHP_WDG_GIRQ_BIT;
+		task_enable_irq(MCHP_IRQ_WDG);
+	} else {
+		MCHP_WDG_IEN = 0U;
+		MCHP_WDG_CTL &= ~(MCHP_WDG_RESET_IRQ_EN);
+		MCHP_INT_DISABLE(MCHP_WDG_GIRQ) = MCHP_WDG_GIRQ_BIT;
+		task_disable_irq(MCHP_IRQ_WDG);
+	}
+}
+#else
+static void wdg_intr_enable(int enable)
+{
+	(void)enable;
+}
+#endif
 
-	/* Clear 16-bit basic timer 0 PCR sleep enable */
-	MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_BTMR16_0);
+/*
+ * MEC1701 WDG asserts chip reset on LOAD count expiration.
+ * WDG interrupt is simulated using a 16-bit general purpose
+ * timer whose period is sufficiently less that the WDG timeout
+ * period allowing watchdog trace data to be saved.
+ *
+ * MEC152x adds interrupt capability to the WDT.
+ * Enable MEC152x WDG interrupt. WDG event will assert
+ * IRQ and kick itself starting another LOAD timeout.
+ * After the new LOAD expires WDG will assert chip reset.
+ * The WDG ISR calls watchdog trace save API, upon return we
+ * enter a spin loop waiting for the LOAD period to expire.
+ * WDG does not have a way to trigger an immediate reset except
+ * by re-programming it.
+ */
+int watchdog_init(void)
+{
+	if (IS_ENABLED(CONFIG_WATCHDOG_HELP)) {
+		/*
+		 * MEC170x Watchdog does not warn us before expiring.
+		 * Let's use a 16-bit timer as an auxiliary timer.
+		 */
 
-	/* Stop the auxiliary timer if it's running */
-	MCHP_TMR16_CTL(0) &= ~BIT(5);
+		/* Clear 16-bit basic timer 0 PCR sleep enable */
+		MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_BTMR16_0);
 
-	/* Enable auxiliary timer */
-	MCHP_TMR16_CTL(0) |= BIT(0);
+		/* Stop the auxiliary timer if it's running */
+		MCHP_TMR16_CTL(0) &= ~BIT(5);
 
-	val = MCHP_TMR16_CTL(0);
+		/* Enable auxiliary timer */
+		MCHP_TMR16_CTL(0) |= BIT(0);
 
-	/* Pre-scale = 48000 -> 1kHz -> Period = 1ms */
-	val = (val & 0xffff) | (47999 << 16);
+		/* Prescaler = 48000 -> 1kHz -> Period = 1 ms */
+		MCHP_TMR16_CTL(0) = (MCHP_TMR16_CTL(0) & 0xffffU) |
+				    (47999 << 16);
 
-	/* No auto restart */
-	val &= ~BIT(3);
+		/* No auto restart */
+		MCHP_TMR16_CTL(0) &= ~BIT(3);
 
-	/* Count down */
-	val &= ~BIT(2);
+		/* Count down */
+		MCHP_TMR16_CTL(0) &= ~BIT(2);
 
-	MCHP_TMR16_CTL(0) = val;
+		/* Enable interrupt from auxiliary timer */
+		MCHP_TMR16_IEN(0) |= BIT(0);
+		task_enable_irq(MCHP_IRQ_TIMER16_0);
+		MCHP_INT_ENABLE(MCHP_TMR16_GIRQ) = MCHP_TMR16_GIRQ_BIT(0);
 
-	/* Enable interrupt from auxiliary timer */
-	MCHP_TMR16_IEN(0) |= 1;
-	task_enable_irq(MCHP_IRQ_TIMER16_0);
-	MCHP_INT_ENABLE(MCHP_TMR16_GIRQ) = MCHP_TMR16_GIRQ_BIT(0);
+		/* Load and start the auxiliary timer */
+		MCHP_TMR16_CNT(0) = CONFIG_AUX_TIMER_PERIOD_MS;
+		MCHP_TMR16_CNT(0) |= BIT(5);
+	}
 
-	/* Load and start the auxiliary timer */
-	MCHP_TMR16_CNT(0) = CONFIG_AUX_TIMER_PERIOD_MS;
-	MCHP_TMR16_CNT(0) |= BIT(5);
-#endif
+	MCHP_WDG_CTL = 0;
 
 	/* Clear WDT PCR sleep enable */
 	MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_WDT);
 
-	/* Set timeout. It takes 1007us to decrement WDG_CNT by 1. */
+	/* Set timeout. It takes 1007 us to decrement WDG_CNT by 1. */
 	MCHP_WDG_LOAD = CONFIG_WATCHDOG_PERIOD_MS * 1000 / 1007;
 
-	/* Start watchdog */
-#ifdef CONFIG_CHIPSET_DEBUG
-	/* WDT will not count if JTAG TRST# is pulled high by JTAG cable */
-	MCHP_WDG_CTL = BIT(4) | BIT(0);
-#else
-	MCHP_WDG_CTL |= 1;
-#endif
+	wdg_intr_enable(1);
+
+	/*
+	 * Start watchdog
+	 * If chipset debug build enable feature to prevent watchdog from
+	 * counting if a debug cable is attached to JTAG_RST#.
+	 */
+	if (IS_ENABLED(CONFIG_CHIPSET_DEBUG))
+		MCHP_WDG_CTL |=
+			(MCHP_WDT_CTL_ENABLE | MCHP_WDT_CTL_JTAG_STALL_EN);
+	else
+		MCHP_WDG_CTL |= MCHP_WDT_CTL_ENABLE;
 
 	return EC_SUCCESS;
 }
 
-#ifdef CONFIG_WATCHDOG_HELP
+/* MEC152x Watchdog can fire an interrupt to CPU before system reset */
+#if defined(CHIP_FAMILY_MEC152X) || defined(CHIP_FAMILY_MEC172X)
+
 void __keep watchdog_check(uint32_t excep_lr, uint32_t excep_sp)
 {
-	trace0(0, WDT, 0, "Watchdog check from 16-bit basic timer0 ISR");
+	/* Clear WDG first then aggregator */
+	MCHP_WDG_STATUS = MCHP_WDG_STS_IRQ;
+	MCHP_INT_SOURCE(MCHP_WDG_GIRQ) = MCHP_WDG_GIRQ_BIT;
 
+	/* Cause WDG to reload again. */
+	MCHP_WDG_KICK = 1;
+
+	watchdog_trace(excep_lr, excep_sp);
+
+	/* Reset system by re-programing WDT to trigger after 2 32KHz clocks */
+	MCHP_WDG_CTL = 0; /* clear enable to allow write to load register */
+	MCHP_WDG_LOAD = 2;
+	MCHP_WDG_CTL |= MCHP_WDT_CTL_ENABLE;
+}
+
+/* ISR for watchdog warning naked will keep SP & LR */
+void IRQ_HANDLER(MCHP_IRQ_WDG)(void) __keep __attribute__((naked));
+void IRQ_HANDLER(MCHP_IRQ_WDG)(void)
+{
+	/* Naked call so we can extract raw LR and SP */
+	asm volatile("mov r0, lr\n"
+		     "mov r1, sp\n"
+		     /*
+		      * Must push registers in pairs to keep 64-bit aligned
+		      * stack for ARM EABI.  This also conveniently saves
+		      * R0=LR so we can pass it to task_resched_if_needed.
+		      */
+		     "push {r0, lr}\n"
+		     "bl watchdog_check\n"
+		     "pop {r0, lr}\n"
+		     "b task_resched_if_needed\n");
+}
+
+/* put the watchdog at the highest priority */
+const struct irq_priority __keep IRQ_PRIORITY(MCHP_IRQ_WDG)
+	__attribute__((section(".rodata.irqprio"))) = { MCHP_IRQ_WDG, 0 };
+
+#else
+/*
+ * MEC1701 watchdog only resets. Use a 16-bit timer to fire in interrupt
+ * for saving watchdog trace.
+ */
+#ifdef CONFIG_WATCHDOG_HELP
+void __keep watchdog_check(uint32_t excep_lr, uint32_t excep_sp)
+{
 	/* Clear status */
 	MCHP_TMR16_STS(0) |= 1;
 	/* clear aggregator status */
@@ -96,8 +181,7 @@ void __keep watchdog_check(uint32_t excep_lr, uint32_t excep_sp)
 	watchdog_trace(excep_lr, excep_sp);
 }
 
-void
-IRQ_HANDLER(MCHP_IRQ_TIMER16_0)(void) __keep __attribute__((naked));
+void IRQ_HANDLER(MCHP_IRQ_TIMER16_0)(void) __keep __attribute__((naked));
 void IRQ_HANDLER(MCHP_IRQ_TIMER16_0)(void)
 {
 	/* Naked call so we can extract raw LR and SP */
@@ -105,7 +189,7 @@ void IRQ_HANDLER(MCHP_IRQ_TIMER16_0)(void)
 		     "mov r1, sp\n"
 		     /*
 		      * Must push registers in pairs to keep 64-bit aligned
-		      * stack for ARM EABI.  This also conveninently saves
+		      * stack for ARM EABI.  This also conveniently saves
 		      * R0=LR so we can pass it to task_resched_if_needed.
 		      */
 		     "push {r0, lr}\n"
@@ -114,10 +198,9 @@ void IRQ_HANDLER(MCHP_IRQ_TIMER16_0)(void)
 		     "b task_resched_if_needed\n");
 }
 
-/*
- * Put the watchdog at the highest interrupt priority.
- */
-const struct irq_priority __keep IRQ_PRIORITY(MEC1322_IRQ_TIMER16_0)
-	__attribute__((section(".rodata.irqprio")))
-		= {MCHP_IRQ_TIMER16_0, 0};
-#endif
+/* Put the watchdog at the highest interrupt priority. */
+const struct irq_priority __keep IRQ_PRIORITY(MCHP_IRQ_TIMER16_0)
+	__attribute__((section(".rodata.irqprio"))) = { MCHP_IRQ_TIMER16_0, 0 };
+
+#endif /* #ifdef CONFIG_WATCHDOG_HELP */
+#endif /* #if defined(CHIP_FAMILY_MEC152X) || defined(CHIP_FAMILY_MEC172X) */
diff --git a/chip/mec1322/adc.c b/chip/mec1322/adc.c
deleted file mode 100644
index fd797a7f15..0000000000
--- a/chip/mec1322/adc.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "adc_chip.h"
-#include "common.h"
-#include "console.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/*
- * Conversion on a single channel takes less than 12 ms. Set timeout to
- * 15 ms so that we have a 3-ms margin.
- */
-#define ADC_SINGLE_READ_TIME 15000
-
-struct mutex adc_lock;
-
-static volatile task_id_t task_waiting;
-
-static int start_single_and_wait(int timeout)
-{
-	int event;
-
-	task_waiting = task_get_current();
-
-	/* Start conversion */
-	MEC1322_ADC_CTRL |= BIT(1);
-
-	/* Wait for interrupt */
-	event = task_wait_event(timeout);
-	task_waiting = TASK_ID_INVALID;
-	return event != TASK_EVENT_TIMER;
-}
-
-int adc_read_channel(enum adc_channel ch)
-{
-	const struct adc_t *adc = adc_channels + ch;
-	int value;
-
-	mutex_lock(&adc_lock);
-
-	MEC1322_ADC_SINGLE = 1 << adc->channel;
-
-	if (start_single_and_wait(ADC_SINGLE_READ_TIME))
-		value = MEC1322_ADC_READ(adc->channel) * adc->factor_mul /
-			adc->factor_div + adc->shift;
-	else
-		value = ADC_READ_ERROR;
-
-	mutex_unlock(&adc_lock);
-	return value;
-}
-
-static void adc_init(void)
-{
-	/* Activate ADC module */
-	MEC1322_ADC_CTRL |= BIT(0);
-
-	/* Enable interrupt */
-	task_waiting = TASK_ID_INVALID;
-	MEC1322_INT_ENABLE(17) |= BIT(10);
-	MEC1322_INT_BLK_EN |= BIT(17);
-	task_enable_irq(MEC1322_IRQ_ADC_SNGL);
-}
-DECLARE_HOOK(HOOK_INIT, adc_init, HOOK_PRIO_INIT_ADC);
-
-void adc_interrupt(void)
-{
-	/* Clear interrupt status bit */
-	MEC1322_ADC_CTRL |= BIT(7);
-
-	if (task_waiting != TASK_ID_INVALID)
-		task_wake(task_waiting);
-}
-DECLARE_IRQ(MEC1322_IRQ_ADC_SNGL, adc_interrupt, 2);
diff --git a/chip/mec1322/adc_chip.h b/chip/mec1322/adc_chip.h
deleted file mode 100644
index bc25344b11..0000000000
--- a/chip/mec1322/adc_chip.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MEC1322-specific ADC module for Chrome EC */
-
-#ifndef __CROS_EC_ADC_CHIP_H
-#define __CROS_EC_ADC_CHIP_H
-
-/* Data structure to define ADC channels. */
-struct adc_t {
-	const char *name;
-	int factor_mul;
-	int factor_div;
-	int shift;
-	int channel;
-};
-
-/*
- * Boards must provide this list of ADC channel definitions.  This must match
- * the enum adc_channel list provided by the board.
- */
-extern const struct adc_t adc_channels[];
-
-/* Minimum and maximum values returned by adc_read_channel(). */
-#define ADC_READ_MIN 0
-#define ADC_READ_MAX 1023
-
-/* Just plain id mapping for code readability */
-#define MEC1322_ADC_CH(x) (x)
-
-#endif /* __CROS_EC_ADC_CHIP_H */
diff --git a/chip/mec1322/build.mk b/chip/mec1322/build.mk
deleted file mode 100644
index 2b0c9cc229..0000000000
--- a/chip/mec1322/build.mk
+++ /dev/null
@@ -1,79 +0,0 @@
-# -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# MEC1322 chip specific files build
-#
-
-# MEC1322 SoC has a Cortex-M4 ARM core
-CORE:=cortex-m
-# Allow the full Cortex-M4 instruction set
-CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
-
-ifeq ($(CONFIG_LTO),y)
-# Re-include the core's build.mk file so we can remove the lto flag.
-include core/$(CORE)/build.mk
-endif
-
-# Required chip modules
-chip-y=clock.o gpio.o hwtimer.o system.o uart.o port80.o
-chip-$(CONFIG_ADC)+=adc.o
-chip-$(CONFIG_FANS)+=fan.o
-chip-$(CONFIG_FLASH_PHYSICAL)+=flash.o
-chip-$(CONFIG_I2C)+=i2c.o
-chip-$(CONFIG_HOSTCMD_LPC)+=lpc.o
-chip-$(CONFIG_PWM)+=pwm.o
-chip-$(CONFIG_WATCHDOG)+=watchdog.o
-ifndef CONFIG_KEYBOARD_NOT_RAW
-chip-$(HAS_TASK_KEYSCAN)+=keyboard_raw.o
-endif
-chip-$(CONFIG_DMA)+=dma.o
-chip-$(CONFIG_SPI)+=spi.o
-
-# location of the scripts and keys used to pack the SPI flash image
-SCRIPTDIR:=./chip/${CHIP}/util
-
-# Allow SPI size to be overridden by board specific size, default to 256KB.
-CHIP_SPI_SIZE_KB?=256
-
-# Commands to convert $^ to $@.tmp
-cmd_obj_to_bin = $(OBJCOPY) --gap-fill=0xff -O binary $< $@.tmp1 ; \
-		 ${SCRIPTDIR}/pack_ec.py -o $@.tmp -i $@.tmp1 \
-		--loader_file $(mec1322-lfw-flat) \
-		--payload_key ${SCRIPTDIR}/rsakey_sign_payload.pem \
-		--header_key ${SCRIPTDIR}/rsakey_sign_header.pem \
-		--spi_size ${CHIP_SPI_SIZE_KB} \
-		--image_size $(_rw_size); rm -f $@.tmp1
-
-mec1322-lfw = chip/mec1322/lfw/ec_lfw
-mec1322-lfw-flat = $(out)/RW/$(mec1322-lfw)-lfw.flat
-
-# build these specifically for lfw with -lfw suffix
-objs_lfw = $(patsubst %, $(out)/RW/%-lfw.o, \
-		$(addprefix common/, util gpio) \
-		$(addprefix chip/$(CHIP)/, spi dma gpio clock hwtimer) \
-		core/$(CORE)/cpu $(mec1322-lfw))
-
-# reuse version.o (and its dependencies) from main board
-objs_lfw += $(out)/RW/common/version.o
-
-dirs-y+=chip/$(CHIP)/lfw
-
-# objs with -lfw suffix are to include lfw's gpio
-$(out)/RW/%-lfw.o: private CC+=-I$(BDIR)/lfw -DLFW=$(EMPTY)
-# Remove the lto flag for the loader.  It actually causes it to bloat in size.
-ifeq ($(CONFIG_LTO),y)
-$(out)/RW/%-lfw.o: private CFLAGS_CPU := $(filter-out -flto, $(CFLAGS_CPU))
-endif
-$(out)/RW/%-lfw.o: %.c
-	$(call quiet,c_to_o,CC     )
-
-# let lfw's elf link only with selected objects
-$(out)/RW/%-lfw.elf: private objs = $(objs_lfw)
-$(out)/RW/%-lfw.elf: override shlib :=
-$(out)/RW/%-lfw.elf: %.ld $(objs_lfw)
-	$(call quiet,elf,LD     )
-
-# final image needs lfw loader
-$(out)/$(PROJECT).bin: $(mec1322-lfw-flat)
diff --git a/chip/mec1322/clock.c b/chip/mec1322/clock.c
deleted file mode 100644
index ce07284891..0000000000
--- a/chip/mec1322/clock.c
+++ /dev/null
@@ -1,484 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks and power management settings */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "shared_mem.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "uart.h"
-#include "util.h"
-#include "vboot_hash.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
-
-#ifdef CONFIG_LOW_POWER_IDLE
-/* Recovery time for HvySlp2 is 0 usec */
-#define HEAVY_SLEEP_RECOVER_TIME_USEC   75
-
-#define SET_HTIMER_DELAY_USEC           200
-
-static int idle_sleep_cnt;
-static int idle_dsleep_cnt;
-static uint64_t total_idle_dsleep_time_us;
-
-/*
- * Fixed amount of time to keep the console in use flag true after boot in
- * order to give a permanent window in which the heavy sleep mode is not used.
- */
-#define CONSOLE_IN_USE_ON_BOOT_TIME (15*SECOND)
-static int console_in_use_timeout_sec = 60;
-static timestamp_t console_expire_time;
-#endif /*CONFIG_LOW_POWER_IDLE */
-
-static int freq = 48000000;
-
-void clock_wait_cycles(uint32_t cycles)
-{
-	asm volatile("1: subs %0, #1\n"
-		     "   bne 1b\n" : "+r"(cycles));
-}
-
-int clock_get_freq(void)
-{
-	return freq;
-}
-
-void clock_init(void)
-{
-#ifdef CONFIG_CLOCK_CRYSTAL
-	/* XOSEL: 0 = Parallel resonant crystal */
-	MEC1322_VBAT_CE &= ~0x1;
-#else
-	/* XOSEL: 1 = Single ended clock source */
-	MEC1322_VBAT_CE |= 0x1;
-#endif
-
-	/* 32K clock enable */
-	MEC1322_VBAT_CE |= 0x2;
-
-#ifdef CONFIG_CLOCK_CRYSTAL
-	/* Wait for crystal to stabilize (OSC_LOCK == 1) */
-	while (!(MEC1322_PCR_CHIP_OSC_ID & 0x100))
-		;
-#endif
-}
-
-/**
- * Speed through boot + vboot hash calculation, dropping our processor clock
- * only after vboot hashing is completed.
- */
-static void clock_turbo_disable(void);
-DECLARE_DEFERRED(clock_turbo_disable);
-
-static void clock_turbo_disable(void)
-{
-#ifdef CONFIG_VBOOT_HASH
-	if (vboot_hash_in_progress())
-		hook_call_deferred(&clock_turbo_disable_data, 100 * MSEC);
-	else
-#endif
-		/* Use 12 MHz processor clock for power savings */
-		MEC1322_PCR_PROC_CLK_CTL = 4;
-}
-DECLARE_HOOK(HOOK_INIT, clock_turbo_disable, HOOK_PRIO_INIT_VBOOT_HASH + 1);
-
-#ifdef CONFIG_LOW_POWER_IDLE
-/**
- * initialization of Hibernation timer
- */
-static void htimer_init(void)
-{
-	MEC1322_INT_BLK_EN |= BIT(17);
-	MEC1322_INT_ENABLE(17) |= BIT(20);  /* GIRQ=17, aggregator bit = 20 */
-	MEC1322_HTIMER_PRELOAD = 0;  /* disable at beginning */
-
-	task_enable_irq(MEC1322_IRQ_HTIMER);
-}
-
-/**
- * Use hibernate module to set up an htimer interrupt at a given
- * time from now
- *
- * @param seconds      Number of seconds before htimer interrupt
- * @param microseconds Number of microseconds before htimer interrupt
- */
-static void system_set_htimer_alarm(uint32_t seconds, uint32_t microseconds)
-{
-	if (seconds || microseconds) {
-
-		if (seconds > 2) {
-			/* count from 2 sec to 2 hrs, mec1322 sec 18.10.2 */
-			ASSERT(seconds <= 0xffff / 8);
-			MEC1322_HTIMER_CONTROL = 1; /* 0.125(=1/8) per clock */
-			/* (number of counts to be loaded)
-			 * = seconds * ( 8 clocks per second )
-			 *   + microseconds / 125000
-			 *   ---> (0 if (microseconds < 125000)
-			 */
-			MEC1322_HTIMER_PRELOAD =
-				(seconds * 8 + microseconds / 125000);
-
-		} else { /* count up to 2 sec. */
-
-			MEC1322_HTIMER_CONTROL = 0; /* 30.5(= 2/61) usec */
-
-			/* (number of counts to be loaded)
-			 * = (total microseconds) / 30.5;
-			 */
-			MEC1322_HTIMER_PRELOAD =
-				(seconds * 1000000 + microseconds) * 2 / 61;
-		}
-	}
-}
-
-/**
- * return time slept in micro-seconds
- */
-static timestamp_t system_get_htimer(void)
-{
-	uint16_t count;
-	timestamp_t time;
-
-	count =  MEC1322_HTIMER_COUNT;
-
-
-	if (MEC1322_HTIMER_CONTROL == 1) /* if > 2 sec */
-		/* 0.125 sec per count */
-		time.le.lo = (uint32_t)(count * 125000);
-	else    /* if < 2 sec */
-		/* 30.5(=61/2)usec per count */
-		time.le.lo = (uint32_t)(count * 61 / 2);
-
-	time.le.hi = 0;
-
-	return time;  /* in uSec */
-}
-
-/**
- * Disable and clear hibernation timer interrupt
- */
-static void system_reset_htimer_alarm(void)
-{
-	MEC1322_HTIMER_PRELOAD = 0;
-}
-
-/**
- * This is mec1322 specific and equivalent to ARM Cortex's
- * 'DeepSleep' via system control block register, CPU_SCB_SYSCTRL
- */
-static void prepare_for_deep_sleep(void)
-{
-	uint32_t ec_slp_en = MEC1322_PCR_EC_SLP_EN |
-			     MEC1322_PCR_EC_SLP_EN_SLEEP;
-
-	/* sysTick timer */
-	CPU_NVIC_ST_CTRL &= ~ST_ENABLE;
-	CPU_NVIC_ST_CTRL &= ~ST_COUNTFLAG;
-
-	/* Disable JTAG */
-	MEC1322_EC_JTAG_EN &= ~1;
-	/* Power down ADC VREF, ADC_VREF overrides ADC_CTRL. */
-	MEC1322_EC_ADC_VREF_PD |= 1;
-
-	/* Stop watchdog */
-	MEC1322_WDG_CTL &= ~1;
-
-	/* Stop timers */
-	MEC1322_TMR32_CTL(0) &= ~1;
-	MEC1322_TMR32_CTL(1) &= ~1;
-	MEC1322_TMR16_CTL(0) &= ~1;
-
-	MEC1322_PCR_CHIP_SLP_EN |= 0x3;
-#ifdef CONFIG_PWM
-	if (pwm_get_keep_awake_mask())
-		ec_slp_en &= ~pwm_get_keep_awake_mask();
-	else
-#endif
-		/* Disable 100 Khz clock */
-		MEC1322_PCR_SLOW_CLK_CTL &= 0xFFFFFC00;
-
-	MEC1322_PCR_EC_SLP_EN = ec_slp_en;
-	MEC1322_PCR_HOST_SLP_EN |= MEC1322_PCR_HOST_SLP_EN_SLEEP;
-	MEC1322_PCR_EC_SLP_EN2 |= MEC1322_PCR_EC_SLP_EN2_SLEEP;
-
-#ifndef CONFIG_POWER_S0IX
-	MEC1322_LPC_ACT = 0x0;
-#endif
-
-	MEC1322_PCR_SYS_SLP_CTL = 0x2;  /* heavysleep 2 */
-
-	CPU_NVIC_ST_CTRL &= ~ST_TICKINT; /* SYS_TICK_INT_DISABLE */
-}
-
-static void resume_from_deep_sleep(void)
-{
-	CPU_NVIC_ST_CTRL |= ST_TICKINT; /* SYS_TICK_INT_ENABLE */
-	CPU_NVIC_ST_CTRL |= ST_ENABLE;
-
-	MEC1322_EC_JTAG_EN = 1;
-	MEC1322_EC_ADC_VREF_PD &= ~1;
-	/* ADC_VREF_PD overrides ADC_CTRL ! */
-
-	/* Enable timer */
-	MEC1322_TMR32_CTL(0) |= 1;
-	MEC1322_TMR32_CTL(1) |= 1;
-	MEC1322_TMR16_CTL(0) |= 1;
-
-	/* Enable watchdog */
-	MEC1322_WDG_CTL |= 1;
-
-	MEC1322_PCR_SLOW_CLK_CTL |= 0x1e0;
-	MEC1322_PCR_CHIP_SLP_EN &= ~0x3;
-	MEC1322_PCR_EC_SLP_EN &= MEC1322_PCR_EC_SLP_EN_WAKE;
-	MEC1322_PCR_HOST_SLP_EN &= MEC1322_PCR_HOST_SLP_EN_WAKE;
-	MEC1322_PCR_EC_SLP_EN2 &= MEC1322_PCR_EC_SLP_EN2_WAKE;
-
-	MEC1322_PCR_SYS_SLP_CTL = 0xF8;  /* default */
-
-#ifndef CONFIG_POWER_S0IX
-	/* Enable LPC */
-	MEC1322_LPC_ACT |= 1;
-#endif
-}
-
-
-void clock_refresh_console_in_use(void)
-{
-	disable_sleep(SLEEP_MASK_CONSOLE);
-
-	/* Set console in use expire time. */
-	console_expire_time = get_time();
-	console_expire_time.val += console_in_use_timeout_sec * SECOND;
-}
-
-/**
- * Low power idle task.  Executed when no tasks are ready to be scheduled.
- */
-void __idle(void)
-{
-	timestamp_t t0;
-	timestamp_t t1;
-	timestamp_t ht_t1;
-	uint32_t next_delay;
-	uint32_t max_sleep_time;
-	int time_for_dsleep;
-	int uart_ready_for_deepsleep;
-
-	htimer_init(); /* hibernation timer initialize */
-
-	disable_sleep(SLEEP_MASK_CONSOLE);
-	console_expire_time.val = get_time().val + CONSOLE_IN_USE_ON_BOOT_TIME;
-
-
-	/*
-	 * Print when the idle task starts.  This is the lowest priority task,
-	 * so this only starts once all other tasks have gotten a chance to do
-	 * their task inits and have gone to sleep.
-	 */
-	CPRINTS("low power idle task started");
-
-	while (1) {
-		/* Disable interrupts */
-		interrupt_disable();
-
-		t0 = get_time();  /* uSec */
-
-		/* __hw_clock_event_get() is next programmed timer event */
-		next_delay = __hw_clock_event_get() - t0.le.lo;
-
-		time_for_dsleep = next_delay > (HEAVY_SLEEP_RECOVER_TIME_USEC +
-						SET_HTIMER_DELAY_USEC);
-
-		max_sleep_time = next_delay - HEAVY_SLEEP_RECOVER_TIME_USEC;
-
-		/* check if there enough time for deep sleep */
-		if (DEEP_SLEEP_ALLOWED && time_for_dsleep) {
-
-
-			/*
-			 * Check if the console use has expired and console
-			 * sleep is masked by GPIO(UART-RX) interrupt.
-			 */
-			if ((sleep_mask & SLEEP_MASK_CONSOLE) &&
-					t0.val > console_expire_time.val) {
-				/* allow console to sleep. */
-				enable_sleep(SLEEP_MASK_CONSOLE);
-
-				/*
-				 * Wait one clock before checking if heavy sleep
-				 * is allowed to give time for sleep mask
-				 * to be updated.
-				 */
-				clock_wait_cycles(1);
-
-				if (LOW_SPEED_DEEP_SLEEP_ALLOWED)
-					CPRINTS("Disable console in deepsleep");
-			}
-
-
-			/* UART is not being used  */
-			uart_ready_for_deepsleep = LOW_SPEED_DEEP_SLEEP_ALLOWED
-						&& !uart_tx_in_progress()
-						&& uart_buffer_empty();
-
-			/*
-			 * Since MEC1322's heavysleep modes requires all block
-			 * to be sleepable, UART/console's readiness is final
-			 * decision factor of heavysleep of EC.
-			 */
-			if (uart_ready_for_deepsleep) {
-
-				idle_dsleep_cnt++;
-
-				/*
-				 * config UART Rx as GPIO wakeup interrupt
-				 * source
-				 */
-				uart_enter_dsleep();
-
-				/* MEC1322 specific deep-sleep mode */
-				prepare_for_deep_sleep();
-
-				/*
-				 * 'max_sleep_time' value should be big
-				 * enough so that hibernation timer's interrupt
-				 * triggers only after 'wfi' completes its
-				 * excution.
-				 */
-				max_sleep_time -= (get_time().le.lo - t0.le.lo);
-
-				/* setup/enable htimer wakeup interrupt */
-				system_set_htimer_alarm(0, max_sleep_time);
-			} else {
-				idle_sleep_cnt++;
-			}
-
-			/* Wait for interrupt: goes into deep sleep. */
-			asm("wfi");
-
-			if (uart_ready_for_deepsleep) {
-
-				resume_from_deep_sleep();
-
-				/*
-				 * Fast forward timer according to htimer
-				 * counter:
-				 * Since all blocks including timers will be in
-				 * sleep mode, timers stops except hibernate
-				 * timer.
-				 * And system schedule timer should be corrected
-				 * after wakeup by either hibernate timer or
-				 * GPIO_UART_RX interrupt.
-				 */
-				ht_t1 = system_get_htimer();
-
-				/* disable/clear htimer wakeup interrupt */
-				system_reset_htimer_alarm();
-
-				t1.val = t0.val +
-				       (uint64_t)(max_sleep_time - ht_t1.le.lo);
-
-				force_time(t1);
-
-				/* re-eanble UART */
-				uart_exit_dsleep();
-
-				/* Record time spent in deep sleep. */
-				total_idle_dsleep_time_us +=
-				       (uint64_t)(max_sleep_time - ht_t1.le.lo);
-			}
-
-		} else { /* CPU 'Sleep' mode */
-
-			idle_sleep_cnt++;
-
-			asm("wfi");
-
-		}
-
-		interrupt_enable();
-	} /* while(1) */
-}
-
-#ifdef CONFIG_CMD_IDLE_STATS
-/**
- * Print low power idle statistics
- */
-static int command_idle_stats(int argc, char **argv)
-{
-	timestamp_t ts = get_time();
-
-	ccprintf("Num idle calls that sleep:           %d\n", idle_sleep_cnt);
-	ccprintf("Num idle calls that deep-sleep:      %d\n", idle_dsleep_cnt);
-
-	ccprintf("Total Time spent in deep-sleep(sec): %.6lld(s)\n",
-						total_idle_dsleep_time_us);
-	ccprintf("Total time on:                       %.6llds\n\n", ts.val);
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats,
-			"",
-			"Print last idle stats");
-#endif /* defined(CONFIG_CMD_IDLE_STATS) */
-
-/**
- * Configure deep sleep clock settings.
- */
-static int command_dsleep(int argc, char **argv)
-{
-	int v;
-
-	if (argc > 1) {
-		if (parse_bool(argv[1], &v)) {
-			/*
-			 * Force deep sleep not to use heavy sleep mode or
-			 * allow it to use the heavy sleep mode.
-			 */
-			if (v)  /* 'on' */
-				disable_sleep(SLEEP_MASK_FORCE_NO_LOW_SPEED);
-			else    /* 'off' */
-				enable_sleep(SLEEP_MASK_FORCE_NO_LOW_SPEED);
-		} else {
-			/* Set console in use timeout. */
-			char *e;
-			v = strtoi(argv[1], &e, 10);
-			if (*e)
-				return EC_ERROR_PARAM1;
-
-			console_in_use_timeout_sec = v;
-
-			/* Refresh console in use to use new timeout. */
-			clock_refresh_console_in_use();
-		}
-	}
-
-	ccprintf("Sleep mask: %08x\n", sleep_mask);
-	ccprintf("Console in use timeout:   %d sec\n",
-			console_in_use_timeout_sec);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(dsleep, command_dsleep,
-			"[ on | off | <timeout> sec]",
-			"Deep sleep clock settings:\nUse 'on' to force deep "
-			"sleep NOT to enter heavysleep mode.\nUse 'off' to "
-			"allow deep sleep to use heavysleep whenever conditions"
-			"allow.\n"
-			"Give a timeout value for the console in use timeout.\n"
-			"See also 'sleepmask'.");
-#endif /* CONFIG_LOW_POWER_IDLE */
diff --git a/chip/mec1322/config_chip.h b/chip/mec1322/config_chip.h
deleted file mode 100644
index 414fb492bf..0000000000
--- a/chip/mec1322/config_chip.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_CHIP_H
-#define __CROS_EC_CONFIG_CHIP_H
-
-/* CPU core BFD configuration */
-#include "core/cortex-m/config_core.h"
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT	93
-
-/* Use a bigger console output buffer */
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE	2048
-
-/* Interval between HOOK_TICK notifications */
-#define HOOK_TICK_INTERVAL_MS	250
-#define HOOK_TICK_INTERVAL	(HOOK_TICK_INTERVAL_MS * MSEC)
-
-/*
- * Number of I2C controllers. Controller 0 has 2 ports, so the chip has one
- * additional port.
- */
-#define CONFIG_I2C_MULTI_PORT_CONTROLLER
-
-#define I2C_CONTROLLER_COUNT	4
-#define I2C_PORT_COUNT		5
-
-/****************************************************************************/
-/* Memory mapping */
-
-/*
- * The memory region for RAM is actually 0x00100000-0x00120000.
- * RAM for RO/RW = 20k
- * CODE size of the Loader is 3k
- * As per the above configuartion the upper 20k
- * is used to store data.The rest is for code.
- * the lower 107K is flash[ 3k Loader and 104k RO/RW],
- * and the higher 20K is RAM shared by loader and RO/RW.
- */
-
-/****************************************************************************/
-/* Define our RAM layout. */
-
-#define CONFIG_MEC_SRAM_BASE_START	0x00100000
-#define CONFIG_MEC_SRAM_BASE_END	0x00120000
-#define CONFIG_MEC_SRAM_SIZE		(CONFIG_MEC_SRAM_BASE_END - \
-					CONFIG_MEC_SRAM_BASE_START)
-
-/* 20k RAM for RO / RW / loader */
-#define CONFIG_RAM_SIZE			0x00005000
-#define CONFIG_RAM_BASE			(CONFIG_MEC_SRAM_BASE_END - \
-					CONFIG_RAM_SIZE)
-
-/* System stack size */
-#define CONFIG_STACK_SIZE		1024
-
-/* non-standard task stack sizes */
-#define IDLE_TASK_STACK_SIZE		512
-#define LARGER_TASK_STACK_SIZE		640
-
-#define CHARGER_TASK_STACK_SIZE		640
-#define HOOKS_TASK_STACK_SIZE		640
-#define CONSOLE_TASK_STACK_SIZE		640
-#define HOST_CMD_TASK_STACK_SIZE	640
-
-/*
- * TODO: Large stack consumption
- * https://code.google.com/p/chrome-os-partner/issues/detail?id=49245
- */
-#define PD_TASK_STACK_SIZE		800
-
-/* Default task stack size */
-#define TASK_STACK_SIZE			512
-
-/****************************************************************************/
-/* Define our flash layout. */
-
-/* Protect bank size 4K bytes */
-#define CONFIG_FLASH_BANK_SIZE		0x00001000
-/* Sector erase size 4K bytes */
-#define CONFIG_FLASH_ERASE_SIZE		0x00001000
-/* Minimum write size */
-#define CONFIG_FLASH_WRITE_SIZE		0x00000004
-
-/* One page size for write */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE	256
-
-/* Program memory base address */
-#define CONFIG_PROGRAM_MEMORY_BASE	0x00100000
-
-#include "config_flash_layout.h"
-
-/****************************************************************************/
-/* Customize the build */
-/* Optional features present on this chip */
-#if 0
-#define CONFIG_ADC
-#define CONFIG_PECI
-#define CONFIG_MPU
-#endif
-#define CONFIG_DMA
-#define CONFIG_HOSTCMD_LPC
-#define CONFIG_SPI
-#define CONFIG_SWITCH
-
-#define GPIO_PIN(index) (index / 10), (1 << (index % 10))
-#define GPIO_PIN_MASK(p, m) .port = (p), .mask = (m)
-
-#endif  /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/chip/mec1322/config_flash_layout.h b/chip/mec1322/config_flash_layout.h
deleted file mode 100644
index 3ab249668d..0000000000
--- a/chip/mec1322/config_flash_layout.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_FLASH_LAYOUT_H
-#define __CROS_EC_CONFIG_FLASH_LAYOUT_H
-
-/*
- * mec1322 flash layout:
- * - Non memory-mapped, external SPI.
- * - RW image at the beginning of writable region.
- * - Bootloader at the beginning of protected region, followed by RO image.
- * - Loader + (RO | RW) loaded into program memory.
- */
-
-/* Non-memmapped, external SPI */
-#define CONFIG_EXTERNAL_STORAGE
-#undef  CONFIG_MAPPED_STORAGE
-#undef  CONFIG_FLASH_PSTATE
-#define CONFIG_SPI_FLASH
-
-/* EC region of SPI resides at end of ROM, protected region follows writable */
-#define CONFIG_EC_PROTECTED_STORAGE_OFF  (CONFIG_FLASH_SIZE - 0x20000)
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x20000
-#define CONFIG_EC_WRITABLE_STORAGE_OFF   (CONFIG_FLASH_SIZE - 0x40000)
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE  0x20000
-
-/* Loader resides at the beginning of program memory */
-#define CONFIG_LOADER_MEM_OFF		0
-#define CONFIG_LOADER_SIZE		0xC00
-
-/* Write protect Loader and RO Image */
-#define CONFIG_WP_STORAGE_OFF		CONFIG_EC_PROTECTED_STORAGE_OFF
-/*
- * Write protect 128k section of 256k physical flash which contains loader
- * and RO Images.
- */
-#define CONFIG_WP_STORAGE_SIZE		CONFIG_EC_PROTECTED_STORAGE_SIZE
-
-/*
- * RO / RW images follow the loader in program memory. Either RO or RW
- * image will be loaded -- both cannot be loaded at the same time.
- */
-#define CONFIG_RO_MEM_OFF		(CONFIG_LOADER_MEM_OFF + \
-					CONFIG_LOADER_SIZE)
-#define CONFIG_RO_SIZE			(97 * 1024)
-#define CONFIG_RW_MEM_OFF		CONFIG_RO_MEM_OFF
-#define CONFIG_RW_SIZE			CONFIG_RO_SIZE
-
-/* WP region consists of second half of SPI, and begins with the boot header */
-#define CONFIG_BOOT_HEADER_STORAGE_OFF	0
-#define CONFIG_BOOT_HEADER_STORAGE_SIZE	0x240
-
-/* Loader / lfw image immediately follows the boot header on SPI */
-#define CONFIG_LOADER_STORAGE_OFF	(CONFIG_BOOT_HEADER_STORAGE_OFF + \
-					CONFIG_BOOT_HEADER_STORAGE_SIZE)
-
-/* RO image immediately follows the loader image */
-#define CONFIG_RO_STORAGE_OFF		(CONFIG_LOADER_STORAGE_OFF + \
-					CONFIG_LOADER_SIZE)
-
-/* RW image starts at the beginning of SPI */
-#define CONFIG_RW_STORAGE_OFF		0
-
-#endif /* __CROS_EC_CONFIG_FLASH_LAYOUT_H */
diff --git a/chip/mec1322/dma.c b/chip/mec1322/dma.c
deleted file mode 100644
index a6c6fed5ad..0000000000
--- a/chip/mec1322/dma.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "dma.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_DMA, outstr)
-#define CPRINTS(format, args...) cprints(CC_DMA, format, ## args)
-
-mec1322_dma_chan_t *dma_get_channel(enum dma_channel channel)
-{
-	mec1322_dma_regs_t *dma = MEC1322_DMA_REGS;
-
-	return &dma->chan[channel];
-}
-
-void dma_disable(enum dma_channel channel)
-{
-	mec1322_dma_chan_t *chan = dma_get_channel(channel);
-
-	if (chan->ctrl & BIT(0))
-		chan->ctrl &= ~BIT(0);
-
-	if (chan->act == 1)
-		chan->act = 0;
-}
-
-void dma_disable_all(void)
-{
-	int ch;
-	mec1322_dma_regs_t *dma;
-
-	for (ch = 0; ch < MEC1322_DMAC_COUNT; ch++) {
-		mec1322_dma_chan_t *chan = dma_get_channel(ch);
-		/* Abort any current transfer. */
-		chan->ctrl |= BIT(25);
-		/* Disable the channel. */
-		chan->ctrl &= ~BIT(0);
-		chan->act = 0;
-	}
-
-	/* Soft-reset the block. */
-	dma = MEC1322_DMA_REGS;
-	dma->ctrl |= 0x2;
-}
-
-/**
- * Prepare a channel for use and start it
- *
- * @param chan		Channel to read
- * @param count		Number of bytes to transfer
- * @param periph	Pointer to peripheral data register
- * @param memory	Pointer to memory address for receive/transmit
- * @param flags		DMA flags for the control register, normally:
- *				MEC1322_DMA_INC_MEM | MEC1322_DMA_TO_DEV for tx
- *				MEC1322_DMA_INC_MEM for rx
- */
-static void prepare_channel(mec1322_dma_chan_t *chan, unsigned count,
-		void *periph, void *memory, unsigned flags)
-{
-	int xfer_size = (flags >> 20) & 0x7;
-
-	if (chan->ctrl & BIT(0))
-		chan->ctrl &= ~BIT(0);
-
-	chan->act |= 0x1;
-	chan->dev = (uint32_t)periph;
-	chan->mem_start = MEC1322_RAM_ALIAS((uint32_t)memory);
-	chan->mem_end = MEC1322_RAM_ALIAS((uint32_t)memory) + xfer_size * count;
-	chan->ctrl = flags;
-}
-
-void dma_go(mec1322_dma_chan_t *chan)
-{
-	/* Flush data in write buffer so that DMA can get the latest data */
-	asm volatile("dsb;");
-
-	/* Fire it up */
-	chan->ctrl |= MEC1322_DMA_RUN;
-}
-
-void dma_prepare_tx(const struct dma_option *option, unsigned count,
-		    const void *memory)
-{
-	mec1322_dma_chan_t *chan = dma_get_channel(option->channel);
-
-	/*
-	 * Cast away const for memory pointer; this is ok because we know
-	 * we're preparing the channel for transmit.
-	 */
-	prepare_channel(chan, count, option->periph, (void *)memory,
-			MEC1322_DMA_INC_MEM | MEC1322_DMA_TO_DEV |
-			MEC1322_DMA_DEV(option->channel) | option->flags);
-}
-
-void dma_start_rx(const struct dma_option *option, unsigned count,
-		  void *memory)
-{
-	mec1322_dma_chan_t *chan;
-
-	chan = dma_get_channel(option->channel);
-
-	prepare_channel(chan, count, option->periph, memory,
-			MEC1322_DMA_INC_MEM | MEC1322_DMA_DEV(option->channel) |
-			option->flags);
-	dma_go(chan);
-}
-
-int dma_bytes_done(mec1322_dma_chan_t *chan, int orig_count)
-{
-	int xfer_size = (chan->ctrl >> 20) & 0x7;
-
-	return orig_count - (chan->mem_end - chan->mem_start) / xfer_size;
-}
-
-bool dma_is_enabled(mec1322_dma_chan_t *chan)
-{
-	return (chan->ctrl & MEC1322_DMA_RUN);
-}
-
-void dma_init(void)
-{
-	mec1322_dma_regs_t *dma = MEC1322_DMA_REGS;
-	dma->ctrl |= 0x1;
-}
-
-int dma_wait(enum dma_channel channel)
-{
-	mec1322_dma_chan_t *chan = dma_get_channel(channel);
-	timestamp_t deadline;
-
-	if (chan->act == 0)
-		return EC_SUCCESS;
-
-	deadline.val = get_time().val + DMA_TRANSFER_TIMEOUT_US;
-	while (!(chan->int_status & 0x4)) {
-		if (deadline.val <= get_time().val)
-			return EC_ERROR_TIMEOUT;
-
-		udelay(DMA_POLLING_INTERVAL_US);
-	}
-	return EC_SUCCESS;
-}
-
-void dma_clear_isr(enum dma_channel channel)
-{
-	mec1322_dma_chan_t *chan = dma_get_channel(channel);
-
-	chan->int_status |= 0x4;
-}
diff --git a/chip/mec1322/fan.c b/chip/mec1322/fan.c
deleted file mode 100644
index 1f54389fc7..0000000000
--- a/chip/mec1322/fan.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MEC1322 fan control module. */
-
-/* This assumes 2-pole fan. For each rotation, 5 edges are measured. */
-
-#include "fan.h"
-#include "registers.h"
-#include "util.h"
-
-/* Maximum tach reading/target value */
-#define MAX_TACH 0x1fff
-
-/* Tach target value for disable fan */
-#define FAN_OFF_TACH 0xfff8
-
-/*
- * RPM = (n - 1) * m * f * 60 / poles / TACH
- *   n = number of edges = 5
- *   m = multiplier defined by RANGE = 2 in our case
- *   f = 32.768K
- *   poles = 2
- */
-#define RPM_TO_TACH(rpm) MIN((7864320 / MAX((rpm), 1)), MAX_TACH)
-#define TACH_TO_RPM(tach) (7864320 / MAX((tach), 1))
-
-static int rpm_setting;
-static int duty_setting;
-static int in_rpm_mode = 1;
-
-
-static void clear_status(void)
-{
-	/* Clear DRIVE_FAIL, FAN_SPIN, and FAN_STALL bits */
-	MEC1322_FAN_STATUS = 0x23;
-}
-
-void fan_set_enabled(int ch, int enabled)
-{
-	if (in_rpm_mode) {
-		if (enabled)
-			fan_set_rpm_target(ch, rpm_setting);
-		else
-			MEC1322_FAN_TARGET = FAN_OFF_TACH;
-	} else {
-		if (enabled)
-			fan_set_duty(ch, duty_setting);
-		else
-			MEC1322_FAN_SETTING = 0;
-	}
-	clear_status();
-}
-
-int fan_get_enabled(int ch)
-{
-	if (in_rpm_mode)
-		return (MEC1322_FAN_TARGET & 0xff00) != 0xff00;
-	else
-		return !!MEC1322_FAN_SETTING;
-}
-
-void fan_set_duty(int ch, int percent)
-{
-	if (percent < 0)
-		percent = 0;
-	else if (percent > 100)
-		percent = 100;
-
-	duty_setting = percent;
-	MEC1322_FAN_SETTING = percent * 255 / 100;
-	clear_status();
-}
-
-int fan_get_duty(int ch)
-{
-	return duty_setting;
-}
-
-int fan_get_rpm_mode(int ch)
-{
-	return !!(MEC1322_FAN_CFG1 & BIT(7));
-}
-
-void fan_set_rpm_mode(int ch, int rpm_mode)
-{
-	if (rpm_mode)
-		MEC1322_FAN_CFG1 |= BIT(7);
-	else
-		MEC1322_FAN_CFG1 &= ~BIT(7);
-	clear_status();
-}
-
-int fan_get_rpm_actual(int ch)
-{
-	if ((MEC1322_FAN_READING >> 8) == 0xff)
-		return 0;
-	else
-		return TACH_TO_RPM(MEC1322_FAN_READING >> 3);
-}
-
-int fan_get_rpm_target(int ch)
-{
-	return rpm_setting;
-}
-
-void fan_set_rpm_target(int ch, int rpm)
-{
-	rpm_setting = rpm;
-	MEC1322_FAN_TARGET = RPM_TO_TACH(rpm) << 3;
-	clear_status();
-}
-
-enum fan_status fan_get_status(int ch)
-{
-	uint8_t sts = MEC1322_FAN_STATUS;
-
-	if (sts & (BIT(5) | BIT(1)))
-		return FAN_STATUS_FRUSTRATED;
-	if (fan_get_rpm_actual(ch) == 0)
-		return FAN_STATUS_STOPPED;
-	return FAN_STATUS_LOCKED;
-}
-
-int fan_is_stalled(int ch)
-{
-	uint8_t sts = MEC1322_FAN_STATUS;
-	if (fan_get_rpm_actual(ch)) {
-		MEC1322_FAN_STATUS = 0x1;
-		return 0;
-	}
-	return sts & 0x1;
-}
-
-void fan_channel_setup(int ch, unsigned int flags)
-{
-	/*
-	 * Fan configuration 1 register:
-	 *   0x80 = bit 7    = RPM mode (0x00 if FAN_USE_RPM_MODE not set)
-	 *   0x20 = bits 6:5 = min 1000 RPM, multiplier = 2
-	 *   0x08 = bits 4:3 = 5 edges, 2 poles
-	 *   0x03 = bits 2:0 = 400 ms update time
-	 *
-	 * Fan configuration 2 register:
-	 *   0x00 = bit 6    = Ramp control disabled
-	 *   0x00 = bit 5    = Glitch filter enabled
-	 *   0x18 = bits 4:3 = Using both derivative options
-	 *   0x02 = bits 2:1 = error range is 50 RPM
-	 *   0x00 = bits 0   = normal polarity
-	 */
-	if (flags & FAN_USE_RPM_MODE)
-		MEC1322_FAN_CFG1 = 0xab;
-	else
-		MEC1322_FAN_CFG1 = 0x2b;
-	MEC1322_FAN_CFG2 = 0x1a;
-	clear_status();
-}
diff --git a/chip/mec1322/flash.c b/chip/mec1322/flash.c
deleted file mode 100644
index b6ab76113b..0000000000
--- a/chip/mec1322/flash.c
+++ /dev/null
@@ -1,268 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "flash.h"
-#include "host_command.h"
-#include "shared_mem.h"
-#include "spi.h"
-#include "spi_flash.h"
-#include "system.h"
-#include "util.h"
-#include "hooks.h"
-
-#define PAGE_SIZE 256
-
-#define FLASH_SYSJUMP_TAG 0x5750 /* "WP" - Write Protect */
-#define FLASH_HOOK_VERSION 1
-
-static int entire_flash_locked;
-
-/* The previous write protect state before sys jump */
-
-struct flash_wp_state {
-	int entire_flash_locked;
-};
-
-/**
- * Read from physical flash.
- *
- * @param offset        Flash offset to write.
- * @param size          Number of bytes to write.
- * @param data          Destination buffer for data.
- */
-int flash_physical_read(int offset, int size, char *data)
-{
-	return spi_flash_read(data, offset, size);
-}
-
-/**
- * Write to physical flash.
- *
- * Offset and size must be a multiple of CONFIG_FLASH_WRITE_SIZE.
- *
- * @param offset        Flash offset to write.
- * @param size          Number of bytes to write.
- * @param data          Data to write to flash.  Must be 32-bit aligned.
- */
-int flash_physical_write(int offset, int size, const char *data)
-{
-	int ret = EC_SUCCESS;
-	int  i, write_size;
-
-	if (entire_flash_locked)
-		return EC_ERROR_ACCESS_DENIED;
-
-	/* Fail if offset, size, and data aren't at least word-aligned */
-	if ((offset | size | (uint32_t)(uintptr_t)data) & 3)
-		return EC_ERROR_INVAL;
-
-	for (i = 0; i < size; i += write_size) {
-		write_size = MIN((size - i), SPI_FLASH_MAX_WRITE_SIZE);
-		ret = spi_flash_write(offset + i,
-				      write_size,
-				      (uint8_t *)data + i);
-		if (ret != EC_SUCCESS)
-			break;
-	}
-	return ret;
-}
-
-/**
- * Erase physical flash.
- *
- * Offset and size must be a multiple of CONFIG_FLASH_ERASE_SIZE.
- *
- * @param offset        Flash offset to erase.
- * @param size          Number of bytes to erase.
- */
-int flash_physical_erase(int offset, int size)
-{
-	int ret;
-
-	if (entire_flash_locked)
-		return EC_ERROR_ACCESS_DENIED;
-
-	ret = spi_flash_erase(offset, size);
-	return ret;
-}
-
-/**
- * Read physical write protect setting for a flash bank.
- *
- * @param bank    Bank index to check.
- * @return        non-zero if bank is protected until reboot.
- */
-int flash_physical_get_protect(int bank)
-{
-	return spi_flash_check_protect(bank * CONFIG_FLASH_BANK_SIZE,
-			CONFIG_FLASH_BANK_SIZE);
-}
-
-/**
- * Protect flash now.
- *
- * This is always successful, and only emulates "now" protection
- *
- * @param all      Protect all (=1) or just read-only
- * @return         non-zero if error.
- */
-int flash_physical_protect_now(int all)
-{
-	if (all)
-		entire_flash_locked = 1;
-
-	/*
-	 * RO "now" protection is not currently implemented. If needed, it
-	 * can be added by splitting the entire_flash_locked variable into
-	 * and RO and RW vars, and setting + checking the appropriate var
-	 * as required.
-	 */
-	return EC_SUCCESS;
-}
-
-/**
- * Return flash protect state flags from the physical layer.
- *
- * This should only be called by flash_get_protect().
- *
- * Uses the EC_FLASH_PROTECT_* flags from ec_commands.h
- */
-uint32_t flash_physical_get_protect_flags(void)
-{
-	uint32_t flags = 0;
-
-	if (spi_flash_check_protect(CONFIG_WP_STORAGE_OFF,
-				    CONFIG_WP_STORAGE_SIZE)) {
-		flags |= EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW;
-	}
-
-	if (entire_flash_locked)
-		flags |= EC_FLASH_PROTECT_ALL_NOW;
-
-	return flags;
-}
-
-/**
- * Return the valid flash protect flags.
- *
- * @return   A combination of EC_FLASH_PROTECT_* flags from ec_commands.h
- */
-uint32_t flash_physical_get_valid_flags(void)
-{
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-	       EC_FLASH_PROTECT_RO_NOW |
-	       EC_FLASH_PROTECT_ALL_NOW;
-}
-
-/**
- * Return the writable flash protect flags.
- *
- * @param    cur_flags The current flash protect flags.
- * @return   A combination of EC_FLASH_PROTECT_* flags from ec_commands.h
- */
-uint32_t flash_physical_get_writable_flags(uint32_t cur_flags)
-{
-	uint32_t ret = 0;
-	enum spi_flash_wp wp_status = SPI_WP_NONE;
-
-	wp_status = spi_flash_check_wp();
-
-	if (wp_status == SPI_WP_NONE || (wp_status == SPI_WP_HARDWARE &&
-	   !(cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED)))
-		ret = EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW;
-
-	if (!entire_flash_locked)
-		ret |= EC_FLASH_PROTECT_ALL_NOW;
-
-	return ret;
-}
-
-/**
- * Enable write protect for the specified range.
- *
- * Once write protect is enabled, it will stay enabled until HW PIN is
- * de-asserted and SRP register is unset.
- *
- * However, this implementation treats EC_FLASH_PROTECT_ALL_AT_BOOT as
- * EC_FLASH_PROTECT_RO_AT_BOOT but tries to remember if "all" region
- * is protected.
- *
- * @param new_flags to protect (only EC_FLASH_PROTECT_*_AT_BOOT are
- * taken care of)
- * @return              EC_SUCCESS, or nonzero if error.
- */
-int flash_physical_protect_at_boot(uint32_t new_flags)
-{
-	int offset, size, ret;
-	enum spi_flash_wp flashwp = SPI_WP_NONE;
-
-	if ((new_flags & (EC_FLASH_PROTECT_RO_AT_BOOT |
-			  EC_FLASH_PROTECT_ALL_AT_BOOT)) == 0) {
-		/* Clear protection */
-		offset = size = 0;
-		flashwp = SPI_WP_NONE;
-	} else {
-		if (new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT)
-			entire_flash_locked = 1;
-
-		offset = CONFIG_WP_STORAGE_OFF;
-		size = CONFIG_WP_STORAGE_SIZE;
-		flashwp = SPI_WP_HARDWARE;
-	}
-
-	ret = spi_flash_set_protect(offset, size);
-	if (ret == EC_SUCCESS)
-		ret = spi_flash_set_wp(flashwp);
-	return ret;
-}
-
-/**
- * Initialize the module.
- *
- * Applies at-boot protection settings if necessary.
- */
-int flash_pre_init(void)
-{
-	flash_physical_restore_state();
-	return EC_SUCCESS;
-}
-
-int flash_physical_restore_state(void)
-{
-	uint32_t reset_flags = system_get_reset_flags();
-	int version, size;
-	const struct flash_wp_state *prev;
-
-	/*
-	 * If we have already jumped between images, an earlier image could
-	 * have applied write protection. Nothing additional needs to be done.
-	 */
-	if (reset_flags & EC_RESET_FLAG_SYSJUMP) {
-		prev = (const struct flash_wp_state *)system_get_jump_tag(
-				FLASH_SYSJUMP_TAG, &version, &size);
-		if (prev && version == FLASH_HOOK_VERSION &&
-		    size == sizeof(*prev))
-			entire_flash_locked = prev->entire_flash_locked;
-		return 1;
-	}
-
-	return 0;
-}
-
-/*****************************************************************************/
-/* Hooks */
-
-static void flash_preserve_state(void)
-{
-	struct flash_wp_state state;
-
-	state.entire_flash_locked = entire_flash_locked;
-
-	system_add_jump_tag(FLASH_SYSJUMP_TAG, FLASH_HOOK_VERSION,
-			    sizeof(state), &state);
-}
-DECLARE_HOOK(HOOK_SYSJUMP, flash_preserve_state, HOOK_PRIO_DEFAULT);
diff --git a/chip/mec1322/gpio.c b/chip/mec1322/gpio.c
deleted file mode 100644
index 331022c87c..0000000000
--- a/chip/mec1322/gpio.c
+++ /dev/null
@@ -1,291 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GPIO module for MEC1322 */
-
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-struct gpio_int_mapping {
-	int8_t girq_id;
-	int8_t port_offset;
-};
-
-/* Mapping from GPIO port to GIRQ info */
-static const struct gpio_int_mapping int_map[22] = {
-	{11, 0}, {11, 0}, {11, 0}, {11, 0},
-	{10, 4}, {10, 4}, {10, 4}, {-1, -1},
-	{-1, -1}, {-1, -1}, {9, 10}, {9, 10},
-	{9, 10}, {9, 10}, {8, 14}, {8, 14},
-	{8, 14}, {-1, -1}, {-1, -1}, {-1, -1},
-	{20, 20}, {20, 20}
-};
-
-void gpio_set_alternate_function(uint32_t port, uint32_t mask,
-				enum gpio_alternate_func func)
-{
-	int i;
-	uint32_t val;
-
-	while (mask) {
-		i = __builtin_ffs(mask) - 1;
-		val = MEC1322_GPIO_CTL(port, i);
-		val &= ~(BIT(12) | BIT(13));
-		/* mux_control = DEFAULT, indicates GPIO */
-		if (func > GPIO_ALT_FUNC_DEFAULT)
-			val |= (func & 0x3) << 12;
-		MEC1322_GPIO_CTL(port, i) = val;
-		mask &= ~BIT(i);
-	}
-}
-
-test_mockable int gpio_get_level(enum gpio_signal signal)
-{
-	uint32_t mask = gpio_list[signal].mask;
-	int i;
-	uint32_t val;
-
-	if (mask == 0)
-		return 0;
-	i = GPIO_MASK_TO_NUM(mask);
-	val = MEC1322_GPIO_CTL(gpio_list[signal].port, i);
-
-	return (val & BIT(24)) ? 1 : 0;
-}
-
-void gpio_set_level(enum gpio_signal signal, int value)
-{
-	uint32_t mask = gpio_list[signal].mask;
-	int i;
-
-	if (mask == 0)
-		return;
-	i = GPIO_MASK_TO_NUM(mask);
-
-	if (value)
-		MEC1322_GPIO_CTL(gpio_list[signal].port, i) |= BIT(16);
-	else
-		MEC1322_GPIO_CTL(gpio_list[signal].port, i) &= ~BIT(16);
-}
-
-void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
-{
-	int i;
-	uint32_t val;
-	while (mask) {
-		i = GPIO_MASK_TO_NUM(mask);
-		mask &= ~BIT(i);
-		val = MEC1322_GPIO_CTL(port, i);
-
-		/*
-		 * Select open drain first, so that we don't glitch the signal
-		 * when changing the line to an output.
-		 */
-		if (flags & GPIO_OPEN_DRAIN)
-			val |= BIT(8);
-		else
-			val &= ~BIT(8);
-
-		if (flags & GPIO_OUTPUT) {
-			val |= BIT(9);
-			val &= ~BIT(10);
-		} else {
-			val &= ~BIT(9);
-			val |= BIT(10);
-		}
-
-		/* Handle pullup / pulldown */
-		if (flags & GPIO_PULL_UP)
-			val = (val & ~0x3) | 0x1;
-		else if (flags & GPIO_PULL_DOWN)
-			val = (val & ~0x3) | 0x2;
-		else
-			val &= ~0x3;
-
-		/* Set up interrupt */
-		if (flags & (GPIO_INT_F_RISING | GPIO_INT_F_FALLING))
-			val |= BIT(7);
-		else
-			val &= ~BIT(7);
-
-		val &= ~(0x7 << 4);
-
-		if ((flags & GPIO_INT_F_RISING) && (flags & GPIO_INT_F_FALLING))
-			val |= 0x7 << 4;
-		else if (flags & GPIO_INT_F_RISING)
-			val |= 0x5 << 4;
-		else if (flags & GPIO_INT_F_FALLING)
-			val |= 0x6 << 4;
-		else if (flags & GPIO_INT_F_HIGH)
-			val |= 0x1 << 4;
-		else if (!(flags & GPIO_INT_F_LOW)) /* No interrupt flag set */
-			val |= 0x4 << 4;
-
-		/* Set up level */
-		if (flags & GPIO_HIGH)
-			val |= BIT(16);
-		else if (flags & GPIO_LOW)
-			val &= ~BIT(16);
-
-		MEC1322_GPIO_CTL(port, i) = val;
-	}
-}
-
-int gpio_enable_interrupt(enum gpio_signal signal)
-{
-	int i, port, girq_id, bit_id;
-
-	if (gpio_list[signal].mask == 0)
-		return EC_SUCCESS;
-
-	i = GPIO_MASK_TO_NUM(gpio_list[signal].mask);
-	port = gpio_list[signal].port;
-	girq_id = int_map[port].girq_id;
-	bit_id = (port - int_map[port].port_offset) * 8 + i;
-
-	MEC1322_INT_ENABLE(girq_id) |= BIT(bit_id);
-	MEC1322_INT_BLK_EN |= BIT(girq_id);
-
-	return EC_SUCCESS;
-}
-
-int gpio_disable_interrupt(enum gpio_signal signal)
-{
-	int i, port, girq_id, bit_id;
-
-	if (gpio_list[signal].mask == 0)
-		return EC_SUCCESS;
-
-	i = GPIO_MASK_TO_NUM(gpio_list[signal].mask);
-	port = gpio_list[signal].port;
-	girq_id = int_map[port].girq_id;
-	bit_id = (port - int_map[port].port_offset) * 8 + i;
-
-	MEC1322_INT_DISABLE(girq_id) = BIT(bit_id);
-
-	return EC_SUCCESS;
-}
-
-int gpio_clear_pending_interrupt(enum gpio_signal signal)
-{
-	int i, port, girq_id, bit_id;
-
-	if (gpio_list[signal].mask == 0)
-		return EC_SUCCESS;
-
-	i = GPIO_MASK_TO_NUM(gpio_list[signal].mask);
-	port = gpio_list[signal].port;
-	girq_id = int_map[port].girq_id;
-	bit_id = (port - int_map[port].port_offset) * 8 + i;
-
-	/* Clear interrupt source sticky status bit even if not enabled */
-	MEC1322_INT_SOURCE(girq_id) |= 1 << bit_id;
-
-	return EC_SUCCESS;
-}
-
-void gpio_pre_init(void)
-{
-	int i;
-	int flags;
-	int is_warm = system_is_reboot_warm();
-	const struct gpio_info *g = gpio_list;
-
-
-	for (i = 0; i < GPIO_COUNT; i++, g++) {
-		flags = g->flags;
-
-		if (flags & GPIO_DEFAULT)
-			continue;
-
-		/*
-		 * If this is a warm reboot, don't set the output levels or
-		 * we'll shut off the AP.
-		 */
-		if (is_warm)
-			flags &= ~(GPIO_LOW | GPIO_HIGH);
-
-		gpio_set_flags_by_mask(g->port, g->mask, flags);
-
-		/* Use as GPIO, not alternate function */
-		gpio_set_alternate_function(g->port, g->mask,
-					GPIO_ALT_FUNC_NONE);
-	}
-}
-
-/* Clear any interrupt flags before enabling GPIO interrupt */
-#define ENABLE_GPIO_GIRQ(x) \
-	do { \
-		MEC1322_INT_SOURCE(x) |= MEC1322_INT_RESULT(x); \
-		task_enable_irq(MEC1322_IRQ_GIRQ ## x); \
-	} while (0)
-
-static void gpio_init(void)
-{
-	ENABLE_GPIO_GIRQ(8);
-	ENABLE_GPIO_GIRQ(9);
-	ENABLE_GPIO_GIRQ(10);
-	ENABLE_GPIO_GIRQ(11);
-	ENABLE_GPIO_GIRQ(20);
-}
-DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
-
-/*****************************************************************************/
-/* Interrupt handlers */
-
-
-/**
- * Handler for each GIRQ interrupt. This reads and clears the interrupt bits for
- * the GIRQ interrupt, then finds and calls the corresponding GPIO interrupt
- * handlers.
- *
- * @param girq		GIRQ index
- * @param port_offset	GPIO port offset for the given GIRQ
- */
-static void gpio_interrupt(int girq, int port_offset)
-{
-	int i, bit;
-	const struct gpio_info *g = gpio_list;
-	uint32_t sts = MEC1322_INT_RESULT(girq);
-
-	MEC1322_INT_SOURCE(girq) |= sts;
-
-	for (i = 0; i < GPIO_IH_COUNT && sts; ++i, ++g) {
-		bit = (g->port - port_offset) * 8 + __builtin_ffs(g->mask) - 1;
-		if (sts & BIT(bit))
-			gpio_irq_handlers[i](i);
-		sts &= ~BIT(bit);
-	}
-}
-
-#define GPIO_IRQ_FUNC(irqfunc, girq, port_offset)  \
-	void irqfunc(void)                         \
-	{                                          \
-		gpio_interrupt(girq, port_offset); \
-	}
-
-GPIO_IRQ_FUNC(__girq_8_interrupt, 8, 14);
-GPIO_IRQ_FUNC(__girq_9_interrupt, 9, 10);
-GPIO_IRQ_FUNC(__girq_10_interrupt, 10, 4);
-GPIO_IRQ_FUNC(__girq_11_interrupt, 11, 0);
-GPIO_IRQ_FUNC(__girq_20_interrupt, 20, 20);
-
-#undef GPIO_IRQ_FUNC
-
-/*
- * Declare IRQs.  Nesting this macro inside the GPIO_IRQ_FUNC macro works
- * poorly because DECLARE_IRQ() stringizes its inputs.
- */
-DECLARE_IRQ(MEC1322_IRQ_GIRQ8, __girq_8_interrupt, 1);
-DECLARE_IRQ(MEC1322_IRQ_GIRQ9, __girq_9_interrupt, 1);
-DECLARE_IRQ(MEC1322_IRQ_GIRQ10, __girq_10_interrupt, 1);
-DECLARE_IRQ(MEC1322_IRQ_GIRQ11, __girq_11_interrupt, 1);
-DECLARE_IRQ(MEC1322_IRQ_GIRQ20, __girq_20_interrupt, 1);
diff --git a/chip/mec1322/hwtimer.c b/chip/mec1322/hwtimer.c
deleted file mode 100644
index a5c5858620..0000000000
--- a/chip/mec1322/hwtimer.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Hardware timers driver */
-
-#include "clock.h"
-#include "common.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-
-void __hw_clock_event_set(uint32_t deadline)
-{
-	MEC1322_TMR32_CNT(1) = MEC1322_TMR32_CNT(0) -
-			       (0xffffffff - deadline);
-	MEC1322_TMR32_CTL(1) |= BIT(5);
-}
-
-uint32_t __hw_clock_event_get(void)
-{
-	return MEC1322_TMR32_CNT(1) - MEC1322_TMR32_CNT(0) + 0xffffffff;
-}
-
-void __hw_clock_event_clear(void)
-{
-	MEC1322_TMR32_CTL(1) &= ~BIT(5);
-}
-
-uint32_t __hw_clock_source_read(void)
-{
-	return 0xffffffff - MEC1322_TMR32_CNT(0);
-}
-
-void __hw_clock_source_set(uint32_t ts)
-{
-	MEC1322_TMR32_CTL(0) &= ~BIT(5);
-	MEC1322_TMR32_CNT(0) = 0xffffffff - ts;
-	MEC1322_TMR32_CTL(0) |= BIT(5);
-}
-
-static void __hw_clock_source_irq(int timer_id)
-{
-	if (timer_id == 1)
-		MEC1322_TMR32_STS(1) |= 1;
-	/* If IRQ is from timer 0, 32-bit timer overflowed */
-	process_timers(timer_id == 0);
-}
-
-void __hw_clock_source_irq_0(void) { __hw_clock_source_irq(0); }
-DECLARE_IRQ(MEC1322_IRQ_TIMER32_0, __hw_clock_source_irq_0, 1);
-void __hw_clock_source_irq_1(void) { __hw_clock_source_irq(1); }
-DECLARE_IRQ(MEC1322_IRQ_TIMER32_1, __hw_clock_source_irq_1, 1);
-
-static void configure_timer(int timer_id)
-{
-	uint32_t val;
-
-	/* Ensure timer is not running */
-	MEC1322_TMR32_CTL(timer_id) &= ~BIT(5);
-
-	/* Enable timer */
-	MEC1322_TMR32_CTL(timer_id) |= BIT(0);
-
-	val = MEC1322_TMR32_CTL(timer_id);
-
-	/* Pre-scale = 48 -> 1MHz -> Period = 1us */
-	val = (val & 0xffff) | (47 << 16);
-
-	MEC1322_TMR32_CTL(timer_id) = val;
-
-	/* Set preload to use the full 32 bits of the timer */
-	MEC1322_TMR32_PRE(timer_id) = 0xffffffff;
-
-	/* Enable interrupt */
-	MEC1322_TMR32_IEN(timer_id) |= 1;
-}
-
-int __hw_clock_source_init(uint32_t start_t)
-{
-	/*
-	 * The timer can only fire interrupt when its value reaches zero.
-	 * Therefore we need two timers:
-	 *   - Timer 0 as free running timer
-	 *   - Timer 1 as event timer
-	 */
-	configure_timer(0);
-	configure_timer(1);
-
-	/* Override the count */
-	MEC1322_TMR32_CNT(0) = 0xffffffff - start_t;
-
-	/* Auto restart */
-	MEC1322_TMR32_CTL(0) |= BIT(3);
-
-	/* Start counting in timer 0 */
-	MEC1322_TMR32_CTL(0) |= BIT(5);
-
-	/* Enable interrupt */
-	task_enable_irq(MEC1322_IRQ_TIMER32_0);
-	task_enable_irq(MEC1322_IRQ_TIMER32_1);
-	MEC1322_INT_ENABLE(23) |= BIT(4) | BIT(5);
-	MEC1322_INT_BLK_EN |= BIT(23);
-
-	return MEC1322_IRQ_TIMER32_1;
-}
diff --git a/chip/mec1322/i2c.c b/chip/mec1322/i2c.c
deleted file mode 100644
index 69344d8390..0000000000
--- a/chip/mec1322/i2c.c
+++ /dev/null
@@ -1,531 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* I2C port module for MEC1322 */
-
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-
-#define I2C_CLOCK 16000000 /* 16 MHz */
-
-/* Status */
-#define STS_NBB BIT(0) /* Bus busy */
-#define STS_LAB BIT(1) /* Arbitration lost */
-#define STS_LRB BIT(3) /* Last received bit */
-#define STS_BER BIT(4) /* Bus error */
-#define STS_PIN BIT(7) /* Pending interrupt */
-
-/* Control */
-#define CTRL_ACK BIT(0) /* Acknowledge */
-#define CTRL_STO BIT(1) /* STOP */
-#define CTRL_STA BIT(2) /* START */
-#define CTRL_ENI BIT(3) /* Enable interrupt */
-#define CTRL_ESO BIT(6) /* Enable serial output */
-#define CTRL_PIN BIT(7) /* Pending interrupt not */
-
-/* Completion */
-#define COMP_IDLE BIT(29)    /* i2c bus is idle */
-#define COMP_RW_BITS_MASK 0x3C /* R/W bits mask */
-
-/* Maximum transfer of a SMBUS block transfer */
-#define SMBUS_MAX_BLOCK_SIZE 32
-
-/*
- * Amount of time to blocking wait for i2c bus to finish. After this blocking
- * timeout, if the bus is still not finished, then allow other tasks to run.
- * Note: this is just long enough for a 400kHz bus to finish transmitting one
- * byte assuming the bus isn't being held.
- */
-#define I2C_WAIT_BLOCKING_TIMEOUT_US 25
-
-enum i2c_transaction_state {
-	/* Stop condition was sent in previous transaction */
-	I2C_TRANSACTION_STOPPED,
-	/* Stop condition was not sent in previous transaction */
-	I2C_TRANSACTION_OPEN,
-};
-
-/* I2C controller state data */
-static struct {
-	/* Transaction timeout, or 0 to use default. */
-	uint32_t timeout_us;
-	/* Task waiting on port, or TASK_ID_INVALID if none. */
-	volatile task_id_t task_waiting;
-	enum i2c_transaction_state transaction_state;
-} cdata[I2C_CONTROLLER_COUNT];
-
-/* Map port number to port name in datasheet, for debug prints. */
-static const char *i2c_port_names[MEC1322_I2C_PORT_COUNT] = {
-	[MEC1322_I2C0_0] = "0_0",
-	[MEC1322_I2C0_1] = "0_1",
-	[MEC1322_I2C1] = "1",
-	[MEC1322_I2C2] = "2",
-	[MEC1322_I2C3] = "3",
-};
-
-static void configure_controller_speed(int controller, int kbps)
-{
-	int t_low, t_high;
-	const int period = I2C_CLOCK / 1000 / kbps;
-
-	/*
-	 * Refer to NXP UM10204 for minimum timing requirement of T_Low and
-	 * T_High.
-	 * http://www.nxp.com/documents/user_manual/UM10204.pdf
-	 */
-	if (kbps > 400) {
-		/* Fast mode plus */
-		t_low = t_high = period / 2 - 1;
-		MEC1322_I2C_DATA_TIM(controller) = 0x06060601;
-		MEC1322_I2C_DATA_TIM_2(controller) = 0x06;
-	} else if (kbps > 100) {
-		/* Fast mode */
-		/* By spec, clk low period is 1.3us min */
-		t_low = MAX((int)(I2C_CLOCK * 1.3 / 1000000), period / 2 - 1);
-		t_high = period - t_low - 2;
-		MEC1322_I2C_DATA_TIM(controller) = 0x040a0a01;
-		MEC1322_I2C_DATA_TIM_2(controller) = 0x0a;
-	} else {
-		/* Standard mode */
-		t_low = t_high = period / 2 - 1;
-		MEC1322_I2C_DATA_TIM(controller) = 0x0c4d5006;
-		MEC1322_I2C_DATA_TIM_2(controller) = 0x4d;
-	}
-
-	/* Clock periods is one greater than the contents of these fields */
-	MEC1322_I2C_BUS_CLK(controller) = ((t_high & 0xff) << 8) |
-					  (t_low & 0xff);
-}
-
-static void configure_controller(int controller, int kbps)
-{
-	MEC1322_I2C_CTRL(controller) = CTRL_PIN;
-	MEC1322_I2C_OWN_ADDR(controller) = 0x0;
-	configure_controller_speed(controller, kbps);
-	MEC1322_I2C_CTRL(controller) = CTRL_PIN | CTRL_ESO |
-				       CTRL_ACK | CTRL_ENI;
-	MEC1322_I2C_CONFIG(controller) |= BIT(10); /* ENAB */
-
-	/* Enable interrupt */
-	MEC1322_I2C_CONFIG(controller) |= BIT(29); /* ENIDI */
-	MEC1322_INT_ENABLE(12) |= BIT(controller);
-	MEC1322_INT_BLK_EN |= BIT(12);
-}
-
-static void reset_controller(int controller)
-{
-	int i;
-
-	MEC1322_I2C_CONFIG(controller) |= BIT(9);
-	udelay(100);
-	MEC1322_I2C_CONFIG(controller) &= ~BIT(9);
-
-	for (i = 0; i < i2c_ports_used; ++i)
-		if (controller == i2c_port_to_controller(i2c_ports[i].port)) {
-			configure_controller(controller, i2c_ports[i].kbps);
-			cdata[controller].transaction_state =
-				I2C_TRANSACTION_STOPPED;
-			break;
-		}
-}
-
-static int wait_for_interrupt(int controller, int timeout)
-{
-	int event;
-
-	if (timeout <= 0)
-		return EC_ERROR_TIMEOUT;
-
-	cdata[controller].task_waiting = task_get_current();
-	task_enable_irq(MEC1322_IRQ_I2C_0 + controller);
-
-	/* Wait until I2C interrupt or timeout. */
-	event = task_wait_event_mask(TASK_EVENT_I2C_IDLE, timeout);
-
-	task_disable_irq(MEC1322_IRQ_I2C_0 + controller);
-	cdata[controller].task_waiting = TASK_ID_INVALID;
-
-	return (event & TASK_EVENT_TIMER) ? EC_ERROR_TIMEOUT : EC_SUCCESS;
-}
-
-static int wait_idle(int controller)
-{
-	uint8_t sts = MEC1322_I2C_STATUS(controller);
-	uint64_t block_timeout = get_time().val + I2C_WAIT_BLOCKING_TIMEOUT_US;
-	uint64_t task_timeout = block_timeout + cdata[controller].timeout_us;
-	int rv = 0;
-
-	while (!(sts & STS_NBB)) {
-		if (rv)
-			return rv;
-		if (get_time().val > block_timeout)
-			rv = wait_for_interrupt(controller,
-						task_timeout - get_time().val);
-		sts = MEC1322_I2C_STATUS(controller);
-	}
-
-	if (sts & (STS_BER | STS_LAB))
-		return EC_ERROR_UNKNOWN;
-	return EC_SUCCESS;
-}
-
-static int wait_byte_done(int controller)
-{
-	uint8_t sts = MEC1322_I2C_STATUS(controller);
-	uint64_t block_timeout = get_time().val + I2C_WAIT_BLOCKING_TIMEOUT_US;
-	uint64_t task_timeout = block_timeout + cdata[controller].timeout_us;
-	int rv = 0;
-
-	while (sts & STS_PIN) {
-		if (rv)
-			return rv;
-		if (get_time().val > block_timeout)
-			rv = wait_for_interrupt(controller,
-						task_timeout - get_time().val);
-		sts = MEC1322_I2C_STATUS(controller);
-	}
-
-	return sts & STS_LRB;
-}
-
-static void select_port(int port)
-{
-	/*
-	 * I2C0_1 uses port 1 of controller 0. All other I2C pin sets
-	 * use port 0.
-	 */
-	uint8_t port_sel = (port == MEC1322_I2C0_1) ? 1 : 0;
-	int controller = i2c_port_to_controller(port);
-
-	MEC1322_I2C_CONFIG(controller) &= ~0xf;
-	MEC1322_I2C_CONFIG(controller) |= port_sel;
-
-}
-
-static inline int get_line_level(int controller)
-{
-	int ret, ctrl;
-	/*
-	* We need to enable BB (Bit Bang) mode in order to read line level
-	* properly, othervise line levels return always idle (0x60).
-	*/
-	ctrl = MEC1322_I2C_BB_CTRL(controller);
-	MEC1322_I2C_BB_CTRL(controller) |= 1;
-	ret = (MEC1322_I2C_BB_CTRL(controller) >> 5) & 0x3;
-	MEC1322_I2C_BB_CTRL(controller) = ctrl;
-	return ret;
-}
-
-static inline void push_in_buf(uint8_t **in, uint8_t val, int skip)
-{
-	if (!skip) {
-		**in = val;
-		(*in)++;
-	}
-}
-
-int chip_i2c_xfer(const int port,
-		  const uint16_t slave_addr_flags,
-		  const uint8_t *out, int out_size,
-		  uint8_t *in, int in_size, int flags)
-{
-	int i;
-	int controller;
-	int send_start = flags & I2C_XFER_START;
-	int send_stop = flags & I2C_XFER_STOP;
-	int skip = 0;
-	int bytes_to_read;
-	uint8_t reg;
-	int ret_done;
-
-	if (out_size == 0 && in_size == 0)
-		return EC_SUCCESS;
-
-	select_port(port);
-	controller = i2c_port_to_controller(port);
-	if (send_start &&
-	    cdata[controller].transaction_state == I2C_TRANSACTION_STOPPED)
-		wait_idle(controller);
-
-	reg = MEC1322_I2C_STATUS(controller);
-	if (send_start &&
-	    cdata[controller].transaction_state == I2C_TRANSACTION_STOPPED &&
-	    (((reg & (STS_BER | STS_LAB)) || !(reg & STS_NBB)) ||
-			    (get_line_level(controller)
-			    != I2C_LINE_IDLE))) {
-		CPRINTS("i2c%s bad status 0x%02x, SCL=%d, SDA=%d",
-			i2c_port_names[port], reg,
-			get_line_level(controller) & I2C_LINE_SCL_HIGH,
-			get_line_level(controller) & I2C_LINE_SDA_HIGH);
-
-		/* Attempt to unwedge the port. */
-		i2c_unwedge(port);
-
-		/* Bus error, bus busy, or arbitration lost. Try reset. */
-		reset_controller(controller);
-		select_port(port);
-
-		/*
-		 * We don't know what edges the slave saw, so sleep long enough
-		 * that the slave will see the new start condition below.
-		 */
-		usleep(1000);
-	}
-
-	if (out_size) {
-		if (send_start) {
-			MEC1322_I2C_DATA(controller) =
-				(uint8_t)(I2C_GET_ADDR(slave_addr_flags)
-					  << 1);
-
-			/* Clock out the slave address, sending START bit */
-			MEC1322_I2C_CTRL(controller) = CTRL_PIN | CTRL_ESO |
-						       CTRL_ENI | CTRL_ACK |
-						       CTRL_STA;
-			cdata[controller].transaction_state =
-				I2C_TRANSACTION_OPEN;
-		}
-
-		for (i = 0; i < out_size; ++i) {
-			ret_done = wait_byte_done(controller);
-			if (ret_done)
-				goto err_chip_i2c_xfer;
-			MEC1322_I2C_DATA(controller) = out[i];
-		}
-		ret_done = wait_byte_done(controller);
-		if (ret_done)
-			goto err_chip_i2c_xfer;
-
-		/*
-		 * Send STOP bit if the stop flag is on, and caller
-		 * doesn't expect to receive data.
-		 */
-		if (send_stop && in_size == 0) {
-			MEC1322_I2C_CTRL(controller) = CTRL_PIN | CTRL_ESO |
-						       CTRL_STO | CTRL_ACK;
-			cdata[controller].transaction_state =
-				I2C_TRANSACTION_STOPPED;
-		}
-	}
-
-	if (in_size) {
-		/* Resend start bit when changing direction */
-		if (out_size || send_start) {
-			/* Repeated start case */
-			if (cdata[controller].transaction_state ==
-			    I2C_TRANSACTION_OPEN)
-				MEC1322_I2C_CTRL(controller) = CTRL_ESO |
-							       CTRL_STA |
-							       CTRL_ACK |
-							       CTRL_ENI;
-
-			MEC1322_I2C_DATA(controller) =
-				(uint8_t)(I2C_GET_ADDR(slave_addr_flags)
-					  << 1)
-				| 0x01;
-
-			/* New transaction case, clock out slave address. */
-			if (cdata[controller].transaction_state ==
-			    I2C_TRANSACTION_STOPPED)
-				MEC1322_I2C_CTRL(controller) = CTRL_ESO |
-							       CTRL_STA |
-							       CTRL_ACK |
-							       CTRL_ENI |
-							       CTRL_PIN;
-
-			cdata[controller].transaction_state =
-				I2C_TRANSACTION_OPEN;
-
-			/* Skip over the unused byte */
-			skip = 1;
-			in_size++;
-		}
-
-		/* Special flags need to be set for last two bytes */
-		bytes_to_read = send_stop ? in_size - 2 : in_size;
-
-		for (i = 0; i < bytes_to_read; ++i) {
-			ret_done = wait_byte_done(controller);
-			if (ret_done)
-				goto err_chip_i2c_xfer;
-			push_in_buf(&in, MEC1322_I2C_DATA(controller), skip);
-			skip = 0;
-		}
-		ret_done = wait_byte_done(controller);
-		if (ret_done)
-			goto err_chip_i2c_xfer;
-
-		if (send_stop) {
-			/*
-			 * De-assert ACK bit before reading the next to last
-			 * byte, so that the last byte is NACK'ed.
-			 */
-			MEC1322_I2C_CTRL(controller) = CTRL_ESO | CTRL_ENI;
-			push_in_buf(&in, MEC1322_I2C_DATA(controller), skip);
-			ret_done = wait_byte_done(controller);
-			if (ret_done)
-				goto err_chip_i2c_xfer;
-
-			/* Send STOP */
-			MEC1322_I2C_CTRL(controller) =
-				CTRL_PIN | CTRL_ESO | CTRL_ACK | CTRL_STO;
-
-			cdata[controller].transaction_state =
-				I2C_TRANSACTION_STOPPED;
-
-			/*
-			 * We need to know our stop point two bytes in
-			 * advance. If we don't know soon enough, we need
-			 * to do an extra read (to last_addr + 1) to
-			 * issue the stop.
-			 */
-			push_in_buf(&in, MEC1322_I2C_DATA(controller),
-				    in_size == 1);
-		}
-	}
-
-	/* Check for error conditions */
-	if (MEC1322_I2C_STATUS(controller) & (STS_LAB | STS_BER))
-		return EC_ERROR_UNKNOWN;
-
-	return EC_SUCCESS;
-err_chip_i2c_xfer:
-	/* Send STOP and return error */
-	MEC1322_I2C_CTRL(controller) = CTRL_PIN | CTRL_ESO |
-				       CTRL_STO | CTRL_ACK;
-	cdata[controller].transaction_state = I2C_TRANSACTION_STOPPED;
-	if (ret_done == STS_LRB)
-		return EC_ERROR_BUSY;
-	else if (ret_done == EC_ERROR_TIMEOUT) {
-		/*
-		 * If our transaction timed out then our i2c controller
-		 * may be wedged without showing any other outward signs
-		 * of failure. Reset the controller so that future
-		 * transactions have a chance of success.
-		 */
-		reset_controller(controller);
-		return EC_ERROR_TIMEOUT;
-	}
-	else
-		return EC_ERROR_UNKNOWN;
-}
-
-int i2c_raw_get_scl(int port)
-{
-	enum gpio_signal g;
-
-	/* If no SCL pin defined for this port, then return 1 to appear idle. */
-	if (get_scl_from_i2c_port(port, &g) != EC_SUCCESS)
-		return 1;
-
-	return gpio_get_level(g);
-}
-
-int i2c_raw_get_sda(int port)
-{
-	enum gpio_signal g;
-
-	/* If no SDA pin defined for this port, then return 1 to appear idle. */
-	if (get_sda_from_i2c_port(port, &g) != EC_SUCCESS)
-		return 1;
-
-	return gpio_get_level(g);
-}
-
-int i2c_get_line_levels(int port)
-{
-	int rv;
-
-	i2c_lock(port, 1);
-	select_port(port);
-	rv = get_line_level(i2c_port_to_controller(port));
-	i2c_lock(port, 0);
-	return rv;
-}
-
-int i2c_port_to_controller(int port)
-{
-	if (port < 0 || port >= MEC1322_I2C_PORT_COUNT)
-		return -1;
-	return (port == MEC1322_I2C0_0) ? 0 : port - 1;
-}
-
-void i2c_set_timeout(int port, uint32_t timeout)
-{
-	/* Param is port, but timeout is stored by-controller. */
-	cdata[i2c_port_to_controller(port)].timeout_us =
-		timeout ? timeout : I2C_TIMEOUT_DEFAULT_US;
-}
-
-void i2c_init(void)
-{
-	int i;
-	int controller;
-	int controller0_kbps = -1;
-
-	/* Configure GPIOs */
-	gpio_config_module(MODULE_I2C, 1);
-
-	for (i = 0; i < i2c_ports_used; ++i) {
-		/*
-		 * If this controller has multiple ports, check if we already
-		 * configured it. If so, ensure previously configured bitrate
-		 * matches.
-		 */
-		controller = i2c_port_to_controller(i2c_ports[i].port);
-		if (controller == 0) {
-			if (controller0_kbps != -1) {
-				ASSERT(controller0_kbps == i2c_ports[i].kbps);
-				continue;
-			}
-			controller0_kbps = i2c_ports[i].kbps;
-		}
-		configure_controller(controller, i2c_ports[i].kbps);
-		cdata[controller].task_waiting = TASK_ID_INVALID;
-		cdata[controller].transaction_state = I2C_TRANSACTION_STOPPED;
-
-		/* Use default timeout. */
-		i2c_set_timeout(i2c_ports[i].port, 0);
-	}
-}
-
-static void handle_interrupt(int controller)
-{
-	int id = cdata[controller].task_waiting;
-
-	/* Clear the interrupt status */
-	MEC1322_I2C_COMPLETE(controller) &= (COMP_RW_BITS_MASK | COMP_IDLE);
-
-	/*
-	 * Write to control register interferes with I2C transaction.
-	 * Instead, let's disable IRQ from the core until the next time
-	 * we want to wait for STS_PIN/STS_NBB.
-	 */
-	task_disable_irq(MEC1322_IRQ_I2C_0 + controller);
-
-	/* Wake up the task which was waiting on the I2C interrupt, if any. */
-	if (id != TASK_ID_INVALID)
-		task_set_event(id, TASK_EVENT_I2C_IDLE, 0);
-}
-
-void i2c0_interrupt(void) { handle_interrupt(0); }
-void i2c1_interrupt(void) { handle_interrupt(1); }
-void i2c2_interrupt(void) { handle_interrupt(2); }
-void i2c3_interrupt(void) { handle_interrupt(3); }
-
-DECLARE_IRQ(MEC1322_IRQ_I2C_0, i2c0_interrupt, 2);
-DECLARE_IRQ(MEC1322_IRQ_I2C_1, i2c1_interrupt, 2);
-DECLARE_IRQ(MEC1322_IRQ_I2C_2, i2c2_interrupt, 2);
-DECLARE_IRQ(MEC1322_IRQ_I2C_3, i2c3_interrupt, 2);
diff --git a/chip/mec1322/keyboard_raw.c b/chip/mec1322/keyboard_raw.c
deleted file mode 100644
index 2c62ada9ac..0000000000
--- a/chip/mec1322/keyboard_raw.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Raw keyboard I/O layer for MEC1322
- */
-
-#include "gpio.h"
-#include "keyboard_config.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-void keyboard_raw_init(void)
-{
-	keyboard_raw_enable_interrupt(0);
-	gpio_config_module(MODULE_KEYBOARD_SCAN, 1);
-
-	/* Enable keyboard scan interrupt */
-	MEC1322_INT_ENABLE(17) |= BIT(21);
-	MEC1322_INT_BLK_EN |= BIT(17);
-	MEC1322_KS_KSI_INT_EN = 0xff;
-}
-
-void keyboard_raw_task_start(void)
-{
-	task_enable_irq(MEC1322_IRQ_KSC_INT);
-}
-
-test_mockable void keyboard_raw_drive_column(int out)
-{
-	if (out == KEYBOARD_COLUMN_ALL) {
-		MEC1322_KS_KSO_SEL = BIT(5); /* KSEN=0, KSALL=1 */
-#ifdef CONFIG_KEYBOARD_COL2_INVERTED
-		gpio_set_level(GPIO_KBD_KSO2, 1);
-#endif
-	} else if (out == KEYBOARD_COLUMN_NONE) {
-		MEC1322_KS_KSO_SEL = BIT(6); /* KSEN=1 */
-#ifdef CONFIG_KEYBOARD_COL2_INVERTED
-		gpio_set_level(GPIO_KBD_KSO2, 0);
-#endif
-	} else {
-#ifdef CONFIG_KEYBOARD_COL2_INVERTED
-		if (out == 2) {
-			MEC1322_KS_KSO_SEL = BIT(6); /* KSEN=1 */
-			gpio_set_level(GPIO_KBD_KSO2, 1);
-		} else {
-			MEC1322_KS_KSO_SEL = out + CONFIG_KEYBOARD_KSO_BASE;
-			gpio_set_level(GPIO_KBD_KSO2, 0);
-		}
-#else
-		MEC1322_KS_KSO_SEL = out + CONFIG_KEYBOARD_KSO_BASE;
-#endif
-	}
-}
-
-test_mockable int keyboard_raw_read_rows(void)
-{
-	/* Invert it so 0=not pressed, 1=pressed */
-	return (MEC1322_KS_KSI_INPUT & 0xff) ^ 0xff;
-}
-
-void keyboard_raw_enable_interrupt(int enable)
-{
-	if (enable) {
-		task_clear_pending_irq(MEC1322_IRQ_KSC_INT);
-		task_enable_irq(MEC1322_IRQ_KSC_INT);
-	} else {
-		task_disable_irq(MEC1322_IRQ_KSC_INT);
-	}
-}
-
-void keyboard_raw_interrupt(void)
-{
-	/* Clear interrupt status bits */
-	MEC1322_KS_KSI_STATUS = 0xff;
-
-	/* Wake keyboard scan task to handle interrupt */
-	task_wake(TASK_ID_KEYSCAN);
-}
-DECLARE_IRQ(MEC1322_IRQ_KSC_INT, keyboard_raw_interrupt, 1);
-
-int keyboard_raw_is_input_low(int port, int id)
-{
-	return (MEC1322_GPIO_CTL(port, id) & BIT(24)) == 0;
-}
diff --git a/chip/mec1322/lfw/ec_lfw.c b/chip/mec1322/lfw/ec_lfw.c
deleted file mode 100644
index 39f4e378ae..0000000000
--- a/chip/mec1322/lfw/ec_lfw.c
+++ /dev/null
@@ -1,283 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * MEC1322 SoC little FW
- *
- */
-
-#include <stdint.h>
-
-#include "config.h"
-#include "gpio.h"
-#include "spi.h"
-#include "spi_flash.h"
-#include "util.h"
-#include "timer.h"
-#include "dma.h"
-#include "registers.h"
-#include "cpu.h"
-#include "clock.h"
-#include "system.h"
-#include "version.h"
-#include "hwtimer.h"
-#include "gpio_list.h"
-
-#include "ec_lfw.h"
-
-__attribute__ ((section(".intvector")))
-const struct int_vector_t hdr_int_vect = {
-			(void *)0x11FA00, /* init sp, unused,
-						set by MEC ROM loader*/
-			&lfw_main,	  /* reset vector */
-			&fault_handler,   /* NMI handler */
-			&fault_handler,   /* HardFault handler */
-			&fault_handler,   /* MPU fault handler */
-			&fault_handler    /* Bus fault handler */
-};
-
-/* SPI devices - from glados/board.c*/
-const struct spi_device_t spi_devices[] = {
-	{ CONFIG_SPI_FLASH_PORT, 0, GPIO_PVT_CS0},
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-
-void timer_init()
-{
-	uint32_t val = 0;
-
-	/* Ensure timer is not running */
-	MEC1322_TMR32_CTL(0) &= ~BIT(5);
-
-	/* Enable timer */
-	MEC1322_TMR32_CTL(0) |= BIT(0);
-
-	val = MEC1322_TMR32_CTL(0);
-
-	/* Pre-scale = 48 -> 1MHz -> Period = 1us */
-	val = (val & 0xffff) | (47 << 16);
-
-	MEC1322_TMR32_CTL(0) = val;
-
-	/* Set preload to use the full 32 bits of the timer */
-	MEC1322_TMR32_PRE(0) = 0xffffffff;
-
-	/* Override the count */
-	MEC1322_TMR32_CNT(0) = 0xffffffff;
-
-	/* Auto restart */
-	MEC1322_TMR32_CTL(0) |= BIT(3);
-
-	/* Start counting in timer 0 */
-	MEC1322_TMR32_CTL(0) |= BIT(5);
-
-}
-
-static int spi_flash_readloc(uint8_t *buf_usr,
-				unsigned int offset,
-				unsigned int bytes)
-{
-	uint8_t cmd[4] = {SPI_FLASH_READ,
-				(offset >> 16) & 0xFF,
-				(offset >> 8) & 0xFF,
-				offset & 0xFF};
-
-	if (offset + bytes > CONFIG_FLASH_SIZE)
-		return EC_ERROR_INVAL;
-
-	return spi_transaction(SPI_FLASH_DEVICE, cmd, 4, buf_usr, bytes);
-}
-
-int spi_image_load(uint32_t offset)
-{
-	uint8_t *buf = (uint8_t *) (CONFIG_RW_MEM_OFF +
-				    CONFIG_PROGRAM_MEMORY_BASE);
-	uint32_t i;
-
-	BUILD_ASSERT(CONFIG_RO_SIZE == CONFIG_RW_SIZE);
-	memset((void *)buf, 0xFF, (CONFIG_RO_SIZE - 4));
-
-	for (i = 0; i < CONFIG_RO_SIZE; i += SPI_CHUNK_SIZE)
-		spi_flash_readloc(&buf[i], offset + i, SPI_CHUNK_SIZE);
-
-	return 0;
-
-}
-
-void udelay(unsigned us)
-{
-	uint32_t t0 = __hw_clock_source_read();
-	while (__hw_clock_source_read() - t0 < us)
-		;
-}
-
-void usleep(unsigned us)
-{
-	udelay(us);
-}
-
-int timestamp_expired(timestamp_t deadline, const timestamp_t *now)
-{
-	timestamp_t now_val;
-
-	if (!now) {
-		now_val = get_time();
-		now = &now_val;
-	}
-
-	return now->le.lo >= deadline.le.lo;
-}
-
-
-timestamp_t get_time(void)
-{
-	timestamp_t ts;
-
-	ts.le.hi = 0;
-	ts.le.lo = __hw_clock_source_read();
-	return ts;
-}
-
-void uart_write_c(char c)
-{
-	/* Put in carriage return prior to newline to mimic uart_vprintf() */
-	if (c == '\n')
-		uart_write_c('\r');
-
-	/* Wait for space in transmit FIFO. */
-	while (!(MEC1322_UART_LSR & BIT(5)))
-		;
-	MEC1322_UART_TB = c;
-}
-
-void uart_puts(const char *str)
-{
-	if (!str || !*str)
-		return;
-
-	do {
-		uart_write_c(*str++);
-	} while (*str);
-}
-
-void fault_handler(void)
-{
-	uart_puts("EXCEPTION!\nTriggering watchdog reset\n");
-	/* trigger reset in 1 ms */
-	MEC1322_WDG_LOAD = 1;
-	MEC1322_WDG_CTL |= 1;
-	while (1)
-		;
-
-}
-
-void jump_to_image(uintptr_t init_addr)
-{
-	void (*resetvec)(void) = (void(*)(void))init_addr;
-	resetvec();
-}
-
-void uart_init(void)
-{
-	/* Set UART to reset on VCC1_RESET instaed of nSIO_RESET */
-	MEC1322_UART_CFG &= ~BIT(1);
-
-	/* Baud rate = 115200. 1.8432MHz clock. Divisor = 1 */
-
-	/* Set CLK_SRC = 0 */
-	MEC1322_UART_CFG &= ~BIT(0);
-
-	/* Set DLAB = 1 */
-	MEC1322_UART_LCR |= BIT(7);
-
-	/* PBRG0/PBRG1 */
-	MEC1322_UART_PBRG0 = 1;
-	MEC1322_UART_PBRG1 = 0;
-
-	/* Set DLAB = 0 */
-	MEC1322_UART_LCR &= ~BIT(7);
-
-	/* Set word length to 8-bit */
-	MEC1322_UART_LCR |= BIT(0) | BIT(1);
-
-	/* Enable FIFO */
-	MEC1322_UART_FCR = BIT(0);
-
-	/* Activate UART */
-	MEC1322_UART_ACT |= BIT(0);
-
-	gpio_config_module(MODULE_UART, 1);
-}
-
-void system_init(void)
-{
-
-	uint32_t wdt_sts = MEC1322_VBAT_STS & MEC1322_VBAT_STS_WDT;
-	uint32_t rst_sts = MEC1322_PCR_CHIP_PWR_RST &
-				MEC1322_PWR_RST_STS_VCC1;
-
-	if (rst_sts || wdt_sts)
-		MEC1322_VBAT_RAM(MEC1322_IMAGETYPE_IDX) = EC_IMAGE_RO;
-}
-
-enum ec_image system_get_image_copy(void)
-{
-	return MEC1322_VBAT_RAM(MEC1322_IMAGETYPE_IDX);
-}
-
-void lfw_main()
-{
-
-	uintptr_t init_addr;
-
-	/* install vector table */
-	*((uintptr_t *) 0xe000ed08) = (uintptr_t) &hdr_int_vect;
-
-	/* Use 48 MHz processor clock to power through boot */
-	MEC1322_PCR_PROC_CLK_CTL = 1;
-
-#ifdef CONFIG_WATCHDOG
-	/* Reload watchdog which may be running in case of sysjump */
-	MEC1322_WDG_KICK = 1;
-#ifdef CONFIG_WATCHDOG_HELP
-	/* Stop aux timer */
-	MEC1322_TMR16_CTL(0) &= ~1;
-#endif
-#endif
-
-	timer_init();
-	clock_init();
-	cpu_init();
-	dma_init();
-	uart_init();
-	system_init();
-	spi_enable(CONFIG_SPI_FLASH_PORT, 1);
-
-	uart_puts("littlefw ");
-	uart_puts(current_image_data.version);
-	uart_puts("\n");
-
-	switch (system_get_image_copy()) {
-	case EC_IMAGE_RW:
-		uart_puts("lfw-RW load\n");
-		init_addr = CONFIG_RW_MEM_OFF + CONFIG_PROGRAM_MEMORY_BASE;
-		spi_image_load(CONFIG_EC_WRITABLE_STORAGE_OFF +
-			       CONFIG_RW_STORAGE_OFF);
-		break;
-	case EC_IMAGE_RO:
-		uart_puts("lfw-RO load\n");
-		spi_image_load(CONFIG_EC_PROTECTED_STORAGE_OFF +
-			       CONFIG_RO_STORAGE_OFF);
-		/* fall through */
-	default:
-		MEC1322_VBAT_RAM(MEC1322_IMAGETYPE_IDX) = EC_IMAGE_RO;
-		init_addr = CONFIG_RO_MEM_OFF + CONFIG_PROGRAM_MEMORY_BASE;
-	}
-
-	jump_to_image(*(uintptr_t *)(init_addr + 4));
-
-	/* should never get here */
-	while (1)
-		;
-}
diff --git a/chip/mec1322/lfw/ec_lfw.h b/chip/mec1322/lfw/ec_lfw.h
deleted file mode 100644
index dd26fbd323..0000000000
--- a/chip/mec1322/lfw/ec_lfw.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * MEC1322 SoC little FW
- *
- */
-
-#include <stdnoreturn.h>
-
-noreturn void lfw_main(void) __attribute__ ((naked));
-void fault_handler(void) __attribute__((naked));
-
-struct int_vector_t {
-	void   *stack_ptr;
-	void   *reset_vector;
-	void   *nmi;
-	void   *hard_fault;
-	void   *bus_fault;
-	void   *usage_fault;
-};
-
-#define SPI_CHUNK_SIZE			1024
diff --git a/chip/mec1322/lfw/ec_lfw.ld b/chip/mec1322/lfw/ec_lfw.ld
deleted file mode 100644
index 65e17e4941..0000000000
--- a/chip/mec1322/lfw/ec_lfw.ld
+++ /dev/null
@@ -1,65 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * MEC1322 SoC little FW
- *
- */
-
-/* Memory Spaces Definitions */
-MEMORY
-{
-    VECTOR(r )  : ORIGIN =  0x100000, LENGTH = 0x18
-    SRAM (xrw)  : ORIGIN =  0x100018, LENGTH = 0xBE8
-}
-
-/*
- * ld does not allow mathematical expressions in ORIGIN/LENGTH, so check the
- * values here.
- */
-ASSERT(ORIGIN(VECTOR) + LENGTH(VECTOR) == ORIGIN(SRAM), "Invalid SRAM origin.")
-ASSERT(LENGTH(VECTOR) + LENGTH(SRAM) == 0xC00, "Invalid VECTOR+SRAM length.")
-
-/*
- * The entry point is informative, for debuggers and simulators,
- * since the Cortex-M vector points to it anyway.
- */
-ENTRY(lfw_main)
-
-/* Sections Definitions */
-
-SECTIONS
-{
-
-    /*
-     * The vector table goes first
-     */
-    .intvector :
-    {
-        . = ALIGN(4);
-        KEEP(*(.intvector))
-    } > VECTOR
-
-    /*
-     * The program code is stored in the .text section,
-     * which goes to FLASH.
-     */
-
-    .text :
-    {
-        *(.text .text.*)                        /* all remaining code */
-        *(.rodata .rodata.*)            /* read-only data (constants) */
-    } >SRAM
-
-    . = ALIGN(4);
-
-    /* Padding */
-
-    .fill : {
-        FILL(0xFF);
-        . = ORIGIN(SRAM) + LENGTH(SRAM) - 1;
-        BYTE(0xFF);   /* emit at least a byte to make linker happy */
-    }
-
-    __image_size = LOADADDR(.text) + SIZEOF(.text) - ORIGIN(VECTOR);
-}
diff --git a/chip/mec1322/lpc.c b/chip/mec1322/lpc.c
deleted file mode 100644
index 020cd0e23e..0000000000
--- a/chip/mec1322/lpc.c
+++ /dev/null
@@ -1,520 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* LPC module for MEC1322 */
-
-#include "acpi.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "keyboard_protocol.h"
-#include "lpc.h"
-#include "port80.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "chipset.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-
-static uint8_t mem_mapped[0x200] __attribute__((section(".bss.big_align")));
-
-static struct host_packet lpc_packet;
-static struct host_cmd_handler_args host_cmd_args;
-static uint8_t host_cmd_flags;   /* Flags from host command */
-
-static uint8_t params_copy[EC_LPC_HOST_PACKET_SIZE] __aligned(4);
-static int init_done;
-
-static struct ec_lpc_host_args * const lpc_host_args =
-	(struct ec_lpc_host_args *)mem_mapped;
-
-static void keyboard_irq_assert(void)
-{
-#ifdef CONFIG_KEYBOARD_IRQ_GPIO
-	/*
-	 * Enforce signal-high for long enough for the signal to be pulled high
-	 * by the external pullup resistor.  This ensures the host will see the
-	 * following falling edge, regardless of the line state before this
-	 * function call.
-	 */
-	gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 1);
-	udelay(4);
-	/* Generate a falling edge */
-	gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 0);
-	udelay(4);
-
-	/* Set signal high, now that we've generated the edge */
-	gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 1);
-#else
-	/*
-	 * SERIRQ is automatically sent by KBC
-	 */
-#endif
-}
-
-/**
- * Generate SMI pulse to the host chipset via GPIO.
- *
- * If the x86 is in S0, SMI# is sampled at 33MHz, so minimum pulse length is
- * 60ns.  If the x86 is in S3, SMI# is sampled at 32.768KHz, so we need pulse
- * length >61us.  Both are short enough and events are infrequent, so just
- * delay for 65us.
- */
-static void lpc_generate_smi(void)
-{
-	gpio_set_level(GPIO_PCH_SMI_L, 0);
-	udelay(65);
-	gpio_set_level(GPIO_PCH_SMI_L, 1);
-}
-
-static void lpc_generate_sci(void)
-{
-#ifdef CONFIG_SCI_GPIO
-	gpio_set_level(CONFIG_SCI_GPIO, 0);
-	udelay(65);
-	gpio_set_level(CONFIG_SCI_GPIO, 1);
-#else
-	MEC1322_ACPI_PM_STS |= 1;
-	udelay(65);
-	MEC1322_ACPI_PM_STS &= ~1;
-#endif
-}
-
-/**
- * Update the level-sensitive wake signal to the AP.
- *
- * @param wake_events	Currently asserted wake events
- */
-static void lpc_update_wake(host_event_t wake_events)
-{
-	/*
-	 * Mask off power button event, since the AP gets that through a
-	 * separate dedicated GPIO.
-	 */
-	wake_events &= ~EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON);
-
-	/* Signal is asserted low when wake events is non-zero */
-	gpio_set_level(GPIO_PCH_WAKE_L, !wake_events);
-}
-
-uint8_t *lpc_get_memmap_range(void)
-{
-	return mem_mapped + 0x100;
-}
-
-static uint8_t *lpc_get_hostcmd_data_range(void)
-{
-	return mem_mapped;
-}
-
-/**
- * Update the host event status.
- *
- * Sends a pulse if masked event status becomes non-zero:
- *   - SMI pulse via PCH_SMI_L GPIO
- *   - SCI pulse via PCH_SCI_L GPIO
- */
-void lpc_update_host_event_status(void)
-{
-	int need_sci = 0;
-	int need_smi = 0;
-
-	if (!init_done)
-		return;
-
-	/* Disable LPC interrupt while updating status register */
-	task_disable_irq(MEC1322_IRQ_ACPIEC0_IBF);
-
-	if (lpc_get_host_events_by_type(LPC_HOST_EVENT_SMI)) {
-		/* Only generate SMI for first event */
-		if (!(MEC1322_ACPI_EC_STATUS(0) & EC_LPC_STATUS_SMI_PENDING))
-			need_smi = 1;
-		MEC1322_ACPI_EC_STATUS(0) |= EC_LPC_STATUS_SMI_PENDING;
-	} else {
-		MEC1322_ACPI_EC_STATUS(0) &= ~EC_LPC_STATUS_SMI_PENDING;
-	}
-
-	if (lpc_get_host_events_by_type(LPC_HOST_EVENT_SCI)) {
-		/* Generate SCI for every event */
-		need_sci = 1;
-		MEC1322_ACPI_EC_STATUS(0) |= EC_LPC_STATUS_SCI_PENDING;
-	} else {
-		MEC1322_ACPI_EC_STATUS(0) &= ~EC_LPC_STATUS_SCI_PENDING;
-	}
-
-	/* Copy host events to mapped memory */
-	*(host_event_t *)host_get_memmap(EC_MEMMAP_HOST_EVENTS) =
-				lpc_get_host_events();
-
-	task_enable_irq(MEC1322_IRQ_ACPIEC0_IBF);
-
-	/* Process the wake events. */
-	lpc_update_wake(lpc_get_host_events_by_type(LPC_HOST_EVENT_WAKE));
-
-	/* Send pulse on SMI signal if needed */
-	if (need_smi)
-		lpc_generate_smi();
-
-	/* ACPI 5.0-12.6.1: Generate SCI for SCI_EVT=1. */
-	if (need_sci)
-		lpc_generate_sci();
-}
-
-static void lpc_send_response_packet(struct host_packet *pkt)
-{
-	/* Ignore in-progress on LPC since interface is synchronous anyway */
-	if (pkt->driver_result == EC_RES_IN_PROGRESS)
-		return;
-
-	/* Write result to the data byte. */
-	MEC1322_ACPI_EC_EC2OS(1, 0) = pkt->driver_result;
-
-	/* Clear the busy bit, so the host knows the EC is done. */
-	MEC1322_ACPI_EC_STATUS(1) &= ~EC_LPC_STATUS_PROCESSING;
-}
-
-/*
- * Most registers in LPC module are reset when the host is off. We need to
- * set up LPC again when the host is starting up.
- */
-static void setup_lpc(void)
-{
-	gpio_config_module(MODULE_LPC, 1);
-
-	/* Set up interrupt on LRESET# deassert */
-	MEC1322_INT_SOURCE(19) = BIT(1);
-	MEC1322_INT_ENABLE(19) |= BIT(1);
-	MEC1322_INT_BLK_EN |= BIT(19);
-	task_enable_irq(MEC1322_IRQ_GIRQ19);
-
-	/* Set up ACPI0 for 0x62/0x66 */
-	MEC1322_LPC_ACPI_EC0_BAR = 0x00628304;
-	MEC1322_INT_ENABLE(15) |= BIT(6);
-	MEC1322_INT_BLK_EN |= BIT(15);
-	/* Clear STATUS_PROCESSING bit in case it was set during sysjump */
-	MEC1322_ACPI_EC_STATUS(0) &= ~EC_LPC_STATUS_PROCESSING;
-	task_enable_irq(MEC1322_IRQ_ACPIEC0_IBF);
-
-	/* Set up ACPI1 for 0x200/0x204 */
-	MEC1322_LPC_ACPI_EC1_BAR = 0x02008407;
-	MEC1322_INT_ENABLE(15) |= BIT(8);
-	MEC1322_INT_BLK_EN |= BIT(15);
-	MEC1322_ACPI_EC_STATUS(1) &= ~EC_LPC_STATUS_PROCESSING;
-	task_enable_irq(MEC1322_IRQ_ACPIEC1_IBF);
-
-	/* Set up 8042 interface at 0x60/0x64 */
-	MEC1322_LPC_8042_BAR = 0x00608104;
-
-	/* Set up indication of Auxiliary sts */
-	MEC1322_8042_KB_CTRL |= BIT(7);
-
-	MEC1322_8042_ACT |= 1;
-	MEC1322_INT_ENABLE(15) |= (BIT(13) | BIT(14));
-	MEC1322_INT_BLK_EN |= BIT(15);
-	task_enable_irq(MEC1322_IRQ_8042EM_IBF);
-	task_enable_irq(MEC1322_IRQ_8042EM_OBF);
-
-#ifndef CONFIG_KEYBOARD_IRQ_GPIO
-	/* Set up SERIRQ for keyboard */
-	MEC1322_8042_KB_CTRL |= BIT(5);
-	MEC1322_LPC_SIRQ(1) = 0x01;
-#endif
-
-	/* Set up EMI module for memory mapped region, base address 0x800 */
-	MEC1322_LPC_EMI_BAR = 0x0800800f;
-	MEC1322_INT_ENABLE(15) |= BIT(2);
-	MEC1322_INT_BLK_EN |= BIT(15);
-	task_enable_irq(MEC1322_IRQ_EMI);
-
-	/* Access data RAM through alias address */
-	MEC1322_EMI_MBA0 = (uint32_t)mem_mapped - 0x118000 + 0x20000000;
-
-	/*
-	 * Limit EMI read / write range. First 256 bytes are RW for host
-	 * commands. Second 256 bytes are RO for mem-mapped data.
-	 */
-	MEC1322_EMI_MRL0 = 0x200;
-	MEC1322_EMI_MWL0 = 0x100;
-
-	/* Set up Mailbox for Port80 trapping */
-	MEC1322_MBX_INDEX = 0xff;
-	MEC1322_LPC_MAILBOX_BAR = 0x00808901;
-
-	/* We support LPC args and version 3 protocol */
-	*(lpc_get_memmap_range() + EC_MEMMAP_HOST_CMD_FLAGS) =
-		EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED |
-		EC_HOST_CMD_FLAG_VERSION_3;
-
-	/* Sufficiently initialized */
-	init_done = 1;
-
-	/* Update host events now that we can copy them to memmap */
-	lpc_update_host_event_status();
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, setup_lpc, HOOK_PRIO_FIRST);
-
-static void lpc_init(void)
-{
-	/* Activate LPC interface */
-	MEC1322_LPC_ACT |= 1;
-
-	/*
-	* Ring Oscillator not permitted to shut down
-	* until LPC activate bit is cleared
-	*/
-	MEC1322_LPC_CLK_CTRL |= 3;
-
-	/* Initialize host args and memory map to all zero */
-	memset(lpc_host_args, 0, sizeof(*lpc_host_args));
-	memset(lpc_get_memmap_range(), 0, EC_MEMMAP_SIZE);
-
-	setup_lpc();
-}
-/*
- * Set prio to higher than default; this way LPC memory mapped data is ready
- * before other inits try to initialize their memmap data.
- */
-DECLARE_HOOK(HOOK_INIT, lpc_init, HOOK_PRIO_INIT_LPC);
-
-#ifdef CONFIG_CHIPSET_RESET_HOOK
-static void lpc_chipset_reset(void)
-{
-	hook_notify(HOOK_CHIPSET_RESET);
-}
-DECLARE_DEFERRED(lpc_chipset_reset);
-#endif
-
-void girq19_interrupt(void)
-{
-	/* Check interrupt result for LRESET# trigger */
-	if (MEC1322_INT_RESULT(19) & BIT(1)) {
-		/* Initialize LPC module when LRESET# is deasserted */
-		if (!lpc_get_pltrst_asserted()) {
-			setup_lpc();
-		} else {
-			/* Store port 80 reset event */
-			port_80_write(PORT_80_EVENT_RESET);
-
-#ifdef CONFIG_CHIPSET_RESET_HOOK
-			/* Notify HOOK_CHIPSET_RESET */
-			hook_call_deferred(&lpc_chipset_reset_data, MSEC);
-#endif
-		}
-
-		CPRINTS("LPC RESET# %sasserted",
-			lpc_get_pltrst_asserted() ? "" : "de");
-
-		/* Clear interrupt source */
-		MEC1322_INT_SOURCE(19) = BIT(1);
-	}
-}
-DECLARE_IRQ(MEC1322_IRQ_GIRQ19, girq19_interrupt, 1);
-
-void emi_interrupt(void)
-{
-	port_80_write(MEC1322_EMI_H2E_MBX);
-}
-DECLARE_IRQ(MEC1322_IRQ_EMI, emi_interrupt, 1);
-
-/*
- * Port80 POST code polling limitation:
- * - POST code 0xFF is ignored.
- */
-int port_80_read(void)
-{
-	int data;
-
-	/* read MBX_INDEX for POST code */
-	data = MEC1322_MBX_INDEX;
-
-	/* clear MBX_INDEX for next POST code*/
-	MEC1322_MBX_INDEX = 0xff;
-
-	/* mark POST code 0xff as invalid */
-	if (data == 0xff)
-		data = PORT_80_IGNORE;
-
-	return data;
-}
-
-void acpi_0_interrupt(void)
-{
-	uint8_t value, result, is_cmd;
-
-	is_cmd = MEC1322_ACPI_EC_STATUS(0) & EC_LPC_STATUS_LAST_CMD;
-
-	/* Set the bust bi */
-	MEC1322_ACPI_EC_STATUS(0) |= EC_LPC_STATUS_PROCESSING;
-
-	/* Read command/data; this clears the FRMH bit. */
-	value = MEC1322_ACPI_EC_OS2EC(0, 0);
-
-	/* Handle whatever this was. */
-	if (acpi_ap_to_ec(is_cmd, value, &result))
-		MEC1322_ACPI_EC_EC2OS(0, 0) = result;
-
-	/* Clear the busy bit */
-	MEC1322_ACPI_EC_STATUS(0) &= ~EC_LPC_STATUS_PROCESSING;
-
-	/*
-	 * ACPI 5.0-12.6.1: Generate SCI for Input Buffer Empty / Output Buffer
-	 * Full condition on the kernel channel.
-	 */
-	lpc_generate_sci();
-}
-DECLARE_IRQ(MEC1322_IRQ_ACPIEC0_IBF, acpi_0_interrupt, 1);
-
-void acpi_1_interrupt(void)
-{
-	uint8_t st = MEC1322_ACPI_EC_STATUS(1);
-	if (!(st & EC_LPC_STATUS_FROM_HOST) ||
-	    !(st & EC_LPC_STATUS_LAST_CMD))
-		return;
-
-	/* Set the busy bit */
-	MEC1322_ACPI_EC_STATUS(1) |= EC_LPC_STATUS_PROCESSING;
-
-	/*
-	 * Read the command byte.  This clears the FRMH bit in
-	 * the status byte.
-	 */
-	host_cmd_args.command = MEC1322_ACPI_EC_OS2EC(1, 0);
-
-	host_cmd_args.result = EC_RES_SUCCESS;
-	host_cmd_flags = lpc_host_args->flags;
-
-	/* We only support new style command (v3) now */
-	if (host_cmd_args.command == EC_COMMAND_PROTOCOL_3) {
-		lpc_packet.send_response = lpc_send_response_packet;
-
-		lpc_packet.request = (const void *)lpc_get_hostcmd_data_range();
-		lpc_packet.request_temp = params_copy;
-		lpc_packet.request_max = sizeof(params_copy);
-		/* Don't know the request size so pass in the entire buffer */
-		lpc_packet.request_size = EC_LPC_HOST_PACKET_SIZE;
-
-		lpc_packet.response = (void *)lpc_get_hostcmd_data_range();
-		lpc_packet.response_max = EC_LPC_HOST_PACKET_SIZE;
-		lpc_packet.response_size = 0;
-
-		lpc_packet.driver_result = EC_RES_SUCCESS;
-		host_packet_receive(&lpc_packet);
-		return;
-	} else {
-		/* Old style command unsupported */
-		host_cmd_args.result = EC_RES_INVALID_COMMAND;
-	}
-
-	/* Hand off to host command handler */
-	host_command_received(&host_cmd_args);
-}
-DECLARE_IRQ(MEC1322_IRQ_ACPIEC1_IBF, acpi_1_interrupt, 1);
-
-#ifdef HAS_TASK_KEYPROTO
-void kb_ibf_interrupt(void)
-{
-	if (lpc_keyboard_input_pending())
-		keyboard_host_write(MEC1322_8042_H2E,
-				    MEC1322_8042_STS & BIT(3));
-	task_wake(TASK_ID_KEYPROTO);
-}
-DECLARE_IRQ(MEC1322_IRQ_8042EM_IBF, kb_ibf_interrupt, 1);
-
-void kb_obf_interrupt(void)
-{
-	task_wake(TASK_ID_KEYPROTO);
-}
-DECLARE_IRQ(MEC1322_IRQ_8042EM_OBF, kb_obf_interrupt, 1);
-#endif
-
-int lpc_keyboard_has_char(void)
-{
-	return (MEC1322_8042_STS & BIT(0)) ? 1 : 0;
-}
-
-int lpc_keyboard_input_pending(void)
-{
-	return (MEC1322_8042_STS & BIT(1)) ? 1 : 0;
-}
-
-void lpc_keyboard_put_char(uint8_t chr, int send_irq)
-{
-	MEC1322_8042_E2H = chr;
-	if (send_irq)
-		keyboard_irq_assert();
-}
-
-void lpc_keyboard_clear_buffer(void)
-{
-	volatile char unused __attribute__((unused));
-
-	unused = MEC1322_8042_OBF_CLR;
-}
-
-void lpc_keyboard_resume_irq(void)
-{
-	if (lpc_keyboard_has_char())
-		keyboard_irq_assert();
-}
-
-void lpc_set_acpi_status_mask(uint8_t mask)
-{
-	MEC1322_ACPI_EC_STATUS(0) |= mask;
-}
-
-void lpc_clear_acpi_status_mask(uint8_t mask)
-{
-	MEC1322_ACPI_EC_STATUS(0) &= ~mask;
-}
-
-int lpc_get_pltrst_asserted(void)
-{
-	return (MEC1322_LPC_BUS_MONITOR & (1<<1)) ? 1 : 0;
-}
-
-/* Enable LPC ACPI-EC0 interrupts */
-void lpc_enable_acpi_interrupts(void)
-{
-	task_enable_irq(MEC1322_IRQ_ACPIEC0_IBF);
-}
-
-/* Disable LPC ACPI-EC0 interrupts */
-void lpc_disable_acpi_interrupts(void)
-{
-	task_disable_irq(MEC1322_IRQ_ACPIEC0_IBF);
-}
-
-/* On boards without a host, this command is used to set up LPC */
-static int lpc_command_init(int argc, char **argv)
-{
-	lpc_init();
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(lpcinit, lpc_command_init, NULL, NULL);
-
-/* Get protocol information */
-static enum ec_status lpc_get_protocol_info(struct host_cmd_handler_args *args)
-{
-	struct ec_response_get_protocol_info *r = args->response;
-
-	memset(r, 0, sizeof(*r));
-	r->protocol_versions = BIT(3);
-	r->max_request_packet_size = EC_LPC_HOST_PACKET_SIZE;
-	r->max_response_packet_size = EC_LPC_HOST_PACKET_SIZE;
-	r->flags = 0;
-
-	args->response_size = sizeof(*r);
-
-	return EC_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO,
-		lpc_get_protocol_info,
-		EC_VER_MASK(0));
diff --git a/chip/mec1322/port80.c b/chip/mec1322/port80.c
deleted file mode 100644
index df4583ed8b..0000000000
--- a/chip/mec1322/port80.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Port 80 Timer Interrupt for MEC1322 */
-
-#include "common.h"
-#include "console.h"
-#include "hooks.h"
-#include "lpc.h"
-#include "port80.h"
-#include "registers.h"
-#include "task.h"
-
-/* Fire timer interrupt every 1000 usec to check for port80 data. */
-#define POLL_PERIOD_USEC 1000
-/* After 30 seconds of no port 80 data, disable the timer interrupt. */
-#define INTERRUPT_DISABLE_TIMEOUT_SEC 30
-#define INTERRUPT_DISABLE_IDLE_COUNT (INTERRUPT_DISABLE_TIMEOUT_SEC \
-				      * 1000000 \
-				      / POLL_PERIOD_USEC)
-
-/* Count the number of consecutive interrupts with no port 80 data. */
-static int idle_count;
-
-static void port_80_interrupt_enable(void)
-{
-	idle_count = 0;
-
-	/* Enable the interrupt. */
-	task_enable_irq(MEC1322_IRQ_TIMER16_1);
-	/* Enable and start the timer. */
-	MEC1322_TMR16_CTL(1) |= 1 | BIT(5);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, port_80_interrupt_enable, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_RESET, port_80_interrupt_enable, HOOK_PRIO_DEFAULT);
-
-static void port_80_interrupt_disable(void)
-{
-	/* Disable the timer block. */
-	MEC1322_TMR16_CTL(1) &= ~1;
-	/* Disable the interrupt. */
-	task_disable_irq(MEC1322_IRQ_TIMER16_1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, port_80_interrupt_disable,
-	     HOOK_PRIO_DEFAULT);
-
-/*
- * The port 80 interrupt will use TIMER16 instance 1 for a 1ms countdown
- * timer.  This timer is on GIRQ23, bit 1.
- */
-static void port_80_interrupt_init(void)
-{
-	uint32_t val = 0;
-
-	/*
-	 * The timers are driven by a 48MHz oscillator.  Prescale down to
-	 * 1MHz. 48MHz/48 -> 1MHz
-	 */
-	val = MEC1322_TMR16_CTL(1);
-	val = (val & 0xFFFF) | (47 << 16);
-	/* Automatically restart the timer. */
-	val |= BIT(3);
-	/* The counter should decrement. */
-	val &= ~BIT(2);
-	MEC1322_TMR16_CTL(1) = val;
-
-	/* Set the reload value(us). */
-	MEC1322_TMR16_PRE(1) = POLL_PERIOD_USEC;
-
-	/* Clear the status if any. */
-	MEC1322_TMR16_STS(1) |= 1;
-
-	/* Clear any pending interrupt. */
-	MEC1322_INT_SOURCE(23) = BIT(1);
-	/* Enable IRQ vector 23. */
-	MEC1322_INT_BLK_EN |= BIT(23);
-	/* Enable the interrupt. */
-	MEC1322_TMR16_IEN(1) |= 1;
-	MEC1322_INT_ENABLE(23) = BIT(1);
-
-	port_80_interrupt_enable();
-}
-DECLARE_HOOK(HOOK_INIT, port_80_interrupt_init, HOOK_PRIO_DEFAULT);
-
-void port_80_interrupt(void)
-{
-	int data;
-
-	MEC1322_TMR16_STS(1) = 1; /* Ack the interrupt */
-	if (BIT(1) & MEC1322_INT_RESULT(23)) {
-		data = port_80_read();
-
-		if (data != PORT_80_IGNORE) {
-			idle_count = 0;
-			port_80_write(data);
-		}
-	}
-
-	if (++idle_count >= INTERRUPT_DISABLE_IDLE_COUNT)
-		port_80_interrupt_disable();
-}
-DECLARE_IRQ(MEC1322_IRQ_TIMER16_1, port_80_interrupt, 2);
diff --git a/chip/mec1322/pwm.c b/chip/mec1322/pwm.c
deleted file mode 100644
index ce94e50e7e..0000000000
--- a/chip/mec1322/pwm.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* PWM control module for MEC1322 */
-
-#include "hooks.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "util.h"
-
-/*
- * PWMs that must remain active in low-power idle - MEC1322_PCR_EC_SLP_EN
- * bit mask.
- */
-static uint32_t pwm_keep_awake_mask;
-
-void pwm_enable(enum pwm_channel ch, int enabled)
-{
-	int id = pwm_channels[ch].channel;
-
-	if (enabled) {
-		MEC1322_PWM_CFG(id) |= 0x1;
-		if (pwm_channels[ch].flags & PWM_CONFIG_DSLEEP)
-			pwm_keep_awake_mask |=
-				MEC1322_PCR_EC_SLP_EN_PWM(id);
-	} else {
-		MEC1322_PWM_CFG(id) &= ~0x1;
-		pwm_keep_awake_mask &= ~MEC1322_PCR_EC_SLP_EN_PWM(id);
-	}
-}
-
-int pwm_get_enabled(enum pwm_channel ch)
-{
-	return MEC1322_PWM_CFG(pwm_channels[ch].channel) & 0x1;
-}
-
-void pwm_set_duty(enum pwm_channel ch, int percent)
-{
-	int id = pwm_channels[ch].channel;
-
-	if (percent < 0)
-		percent = 0;
-	else if (percent > 100)
-		percent = 100;
-
-	MEC1322_PWM_ON(id) = percent;
-	MEC1322_PWM_OFF(id) = 100 - percent;
-}
-
-int pwm_get_duty(enum pwm_channel ch)
-{
-	return MEC1322_PWM_ON(pwm_channels[ch].channel);
-}
-
-uint32_t pwm_get_keep_awake_mask(void)
-{
-	return pwm_keep_awake_mask;
-}
-
-static void pwm_configure(int ch, int active_low, int clock_low)
-{
-	/*
-	 * clock_low=0 selects the 48MHz Ring Oscillator source
-	 * clock_low=1 selects the 100kHz_Clk source
-	 */
-	MEC1322_PWM_CFG(ch) = (15 << 3) |    /* Pre-divider = 16 */
-			      (active_low ? BIT(2) : 0) |
-			      (clock_low  ? BIT(1) : 0);
-}
-
-static void pwm_init(void)
-{
-	int i;
-
-	for (i = 0; i < PWM_CH_COUNT; ++i) {
-		pwm_configure(pwm_channels[i].channel,
-			      pwm_channels[i].flags & PWM_CONFIG_ACTIVE_LOW,
-			      pwm_channels[i].flags & PWM_CONFIG_ALT_CLOCK);
-		pwm_set_duty(i, 0);
-	}
-}
-DECLARE_HOOK(HOOK_INIT, pwm_init, HOOK_PRIO_INIT_PWM);
diff --git a/chip/mec1322/pwm_chip.h b/chip/mec1322/pwm_chip.h
deleted file mode 100644
index 9c441aaecd..0000000000
--- a/chip/mec1322/pwm_chip.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MEC1322-specific PWM module for Chrome EC */
-#ifndef __CROS_EC_PWM_CHIP_H
-#define __CROS_EC_PWM_CHIP_H
-
-/* Data structure to define PWM channels. */
-struct pwm_t {
-	/* PWM Channel ID */
-	int channel;
-
-	/* PWM channel flags. See include/pwm.h */
-	uint32_t flags;
-};
-
-extern const struct pwm_t pwm_channels[];
-
-/*
- * Returns PWMs that must remain active in low-power idle -
- * MEC1322_PCR_EC_SLP_EN bit mask.
- */
-uint32_t pwm_get_keep_awake_mask(void);
-#endif  /* __CROS_EC_PWM_CHIP_H */
diff --git a/chip/mec1322/registers.h b/chip/mec1322/registers.h
deleted file mode 100644
index 7bbd9fb068..0000000000
--- a/chip/mec1322/registers.h
+++ /dev/null
@@ -1,510 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Register map for MEC1322 processor
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#define __CROS_EC_REGISTERS_H
-
-#include "common.h"
-
-/* Helper function for RAM address aliasing */
-#define MEC1322_RAM_ALIAS(x)   \
-	((x) >= 0x118000 ? (x) - 0x118000 + 0x20000000 : (x))
-
-/* EC Chip Configuration */
-#define MEC1322_CHIP_BASE      0x400fff00
-#define MEC1322_CHIP_DEV_ID    REG8(MEC1322_CHIP_BASE + 0x20)
-#define MEC1322_CHIP_DEV_REV   REG8(MEC1322_CHIP_BASE + 0x21)
-
-
-/* Power/Clocks/Resets */
-#define MEC1322_PCR_BASE         0x40080100
-#define MEC1322_PCR_CHIP_SLP_EN  REG32(MEC1322_PCR_BASE + 0x0)
-#define MEC1322_PCR_CHIP_CLK_REQ REG32(MEC1322_PCR_BASE + 0x4)
-#define MEC1322_PCR_EC_SLP_EN    REG32(MEC1322_PCR_BASE + 0x8)
-/* Command all blocks to sleep */
-#define  MEC1322_PCR_EC_SLP_EN_SLEEP	0xe0700ff7
-#define  MEC1322_PCR_EC_SLP_EN_PWM(n)	(1 << ((n) ? (19 + (n)) : 4))
-#define  MEC1322_PCR_EC_SLP_EN_PWM3	BIT(22)
-#define  MEC1322_PCR_EC_SLP_EN_PWM2	BIT(21)
-#define  MEC1322_PCR_EC_SLP_EN_PWM1	BIT(20)
-#define  MEC1322_PCR_EC_SLP_EN_PWM0	BIT(4)
-/* Allow all blocks to request clocks */
-#define  MEC1322_PCR_EC_SLP_EN_WAKE	(~0xe0700ff7)
-#define MEC1322_PCR_EC_CLK_REQ   REG32(MEC1322_PCR_BASE + 0xc)
-#define MEC1322_PCR_HOST_SLP_EN  REG32(MEC1322_PCR_BASE + 0x10)
-/* Command all blocks to sleep */
-#define  MEC1322_PCR_HOST_SLP_EN_SLEEP	0x5f003
-/* Allow all blocks to request clocks */
-#define  MEC1322_PCR_HOST_SLP_EN_WAKE	(~0x5f003)
-#define MEC1322_PCR_HOST_CLK_REQ REG32(MEC1322_PCR_BASE + 0x14)
-#define MEC1322_PCR_SYS_SLP_CTL  REG32(MEC1322_PCR_BASE + 0x18)
-#define MEC1322_PCR_PROC_CLK_CTL REG32(MEC1322_PCR_BASE + 0x20)
-#define MEC1322_PCR_EC_SLP_EN2   REG32(MEC1322_PCR_BASE + 0x24)
-/* Mask to command all blocks to sleep */
-#define  MEC1322_PCR_EC_SLP_EN2_SLEEP	0x1ffffff8
-/* Allow all blocks to request clocks */
-#define  MEC1322_PCR_EC_SLP_EN2_WAKE	(~0x03fffff8)
-#define MEC1322_PCR_EC_CLK_REQ2  REG32(MEC1322_PCR_BASE + 0x28)
-#define MEC1322_PCR_SLOW_CLK_CTL REG32(MEC1322_PCR_BASE + 0x2c)
-#define MEC1322_PCR_CHIP_OSC_ID  REG32(MEC1322_PCR_BASE + 0x30)
-#define MEC1322_PCR_CHIP_PWR_RST REG32(MEC1322_PCR_BASE + 0x34)
-#define MEC1322_PCR_CHIP_RST_EN  REG32(MEC1322_PCR_BASE + 0x38)
-#define MEC1322_PCR_HOST_RST_EN  REG32(MEC1322_PCR_BASE + 0x3c)
-#define MEC1322_PCR_EC_RST_EN    REG32(MEC1322_PCR_BASE + 0x40)
-#define MEC1322_PCR_EC_RST_EN2   REG32(MEC1322_PCR_BASE + 0x44)
-#define MEC1322_PCR_PWR_RST_CTL  REG32(MEC1322_PCR_BASE + 0x48)
-
-/* Bit defines for MEC1322_PCR_CHIP_PWR_RST */
-#define MEC1322_PWR_RST_STS_VCC1 BIT(6)
-#define MEC1322_PWR_RST_STS_VBAT BIT(5)
-
-/* EC Subsystem */
-#define MEC1322_EC_BASE        0x4000fc00
-#define MEC1322_EC_INT_CTRL    REG32(MEC1322_EC_BASE + 0x18)
-#define MEC1322_EC_TRACE_EN    REG32(MEC1322_EC_BASE + 0x1c)
-#define MEC1322_EC_JTAG_EN     REG32(MEC1322_EC_BASE + 0x20)
-#define MEC1322_EC_WDT_CNT     REG32(MEC1322_EC_BASE + 0x28)
-#define MEC1322_EC_ADC_VREF_PD REG32(MEC1322_EC_BASE + 0x38)
-
-/* Interrupt aggregator */
-#define MEC1322_INT_BASE       0x4000c000
-#define MEC1322_INTx_BASE(x)   (MEC1322_INT_BASE + ((x) - 8) * 0x14)
-#define MEC1322_INT_SOURCE(x)  REG32(MEC1322_INTx_BASE(x) + 0x0)
-#define MEC1322_INT_ENABLE(x)  REG32(MEC1322_INTx_BASE(x) + 0x4)
-#define MEC1322_INT_RESULT(x)  REG32(MEC1322_INTx_BASE(x) + 0x8)
-#define MEC1322_INT_DISABLE(x) REG32(MEC1322_INTx_BASE(x) + 0xc)
-#define MEC1322_INT_BLK_EN     REG32(MEC1322_INT_BASE + 0x200)
-#define MEC1322_INT_BLK_DIS    REG32(MEC1322_INT_BASE + 0x204)
-#define MEC1322_INT_BLK_IRQ    REG32(MEC1322_INT_BASE + 0x208)
-
-
-/* UART */
-#define MEC1322_UART_CONFIG_BASE  0x400f1f00
-#define MEC1322_UART_RUNTIME_BASE 0x400f1c00
-
-#define MEC1322_UART_ACT       REG8(MEC1322_UART_CONFIG_BASE + 0x30)
-#define MEC1322_UART_CFG       REG8(MEC1322_UART_CONFIG_BASE + 0xf0)
-
-/* DLAB=0 */
-#define MEC1322_UART_RB /*R*/  REG8(MEC1322_UART_RUNTIME_BASE + 0x0)
-#define MEC1322_UART_TB /*W*/  REG8(MEC1322_UART_RUNTIME_BASE + 0x0)
-#define MEC1322_UART_IER       REG8(MEC1322_UART_RUNTIME_BASE + 0x1)
-/* DLAB=1 */
-#define MEC1322_UART_PBRG0     REG8(MEC1322_UART_RUNTIME_BASE + 0x0)
-#define MEC1322_UART_PBRG1     REG8(MEC1322_UART_RUNTIME_BASE + 0x1)
-
-#define MEC1322_UART_FCR /*W*/ REG8(MEC1322_UART_RUNTIME_BASE + 0x2)
-#define MEC1322_UART_IIR /*R*/ REG8(MEC1322_UART_RUNTIME_BASE + 0x2)
-#define MEC1322_UART_LCR       REG8(MEC1322_UART_RUNTIME_BASE + 0x3)
-#define MEC1322_UART_MCR       REG8(MEC1322_UART_RUNTIME_BASE + 0x4)
-#define MEC1322_UART_LSR       REG8(MEC1322_UART_RUNTIME_BASE + 0x5)
-#define MEC1322_UART_MSR       REG8(MEC1322_UART_RUNTIME_BASE + 0x6)
-#define MEC1322_UART_SCR       REG8(MEC1322_UART_RUNTIME_BASE + 0x7)
-
-/* Bit defines for MEC1322_UART_LSR */
-#define MEC1322_LSR_TX_EMPTY     BIT(5)
-
-/* GPIO */
-#define MEC1322_GPIO_BASE      0x40081000
-
-static inline uintptr_t gpio_port_base(int port_id)
-{
-	int oct = (port_id / 10) * 8 + port_id % 10;
-	return MEC1322_GPIO_BASE + oct * 0x20;
-}
-#define MEC1322_GPIO_CTL(port, id) REG32(gpio_port_base(port) + (id << 2))
-
-#define UNIMPLEMENTED_GPIO_BANK 0
-
-
-/* Timer */
-#define MEC1322_TMR16_BASE(x)  (0x40000c00 + (x) * 0x20)
-#define MEC1322_TMR32_BASE(x)  (0x40000c80 + (x) * 0x20)
-
-#define MEC1322_TMR16_CNT(x)   REG32(MEC1322_TMR16_BASE(x) + 0x0)
-#define MEC1322_TMR16_PRE(x)   REG32(MEC1322_TMR16_BASE(x) + 0x4)
-#define MEC1322_TMR16_STS(x)   REG32(MEC1322_TMR16_BASE(x) + 0x8)
-#define MEC1322_TMR16_IEN(x)   REG32(MEC1322_TMR16_BASE(x) + 0xc)
-#define MEC1322_TMR16_CTL(x)   REG32(MEC1322_TMR16_BASE(x) + 0x10)
-#define MEC1322_TMR32_CNT(x)   REG32(MEC1322_TMR32_BASE(x) + 0x0)
-#define MEC1322_TMR32_PRE(x)   REG32(MEC1322_TMR32_BASE(x) + 0x4)
-#define MEC1322_TMR32_STS(x)   REG32(MEC1322_TMR32_BASE(x) + 0x8)
-#define MEC1322_TMR32_IEN(x)   REG32(MEC1322_TMR32_BASE(x) + 0xc)
-#define MEC1322_TMR32_CTL(x)   REG32(MEC1322_TMR32_BASE(x) + 0x10)
-
-
-/* Watchdog */
-#define MEC1322_WDG_BASE       0x40000400
-#define MEC1322_WDG_LOAD       REG16(MEC1322_WDG_BASE + 0x0)
-#define MEC1322_WDG_CTL        REG8(MEC1322_WDG_BASE + 0x4)
-#define MEC1322_WDG_KICK       REG8(MEC1322_WDG_BASE + 0x8)
-#define MEC1322_WDG_CNT        REG16(MEC1322_WDG_BASE + 0xc)
-
-
-/* VBAT */
-#define MEC1322_VBAT_BASE      0x4000a400
-#define MEC1322_VBAT_STS       REG32(MEC1322_VBAT_BASE + 0x0)
-#define MEC1322_VBAT_CE        REG32(MEC1322_VBAT_BASE + 0x8)
-#define MEC1322_VBAT_RAM(x)    REG32(MEC1322_VBAT_BASE + 0x400 + 4 * (x))
-
-/* Bit definition for MEC1322_VBAT_STS */
-#define MEC1322_VBAT_STS_WDT	BIT(5)
-
-/* Miscellaneous firmware control fields
- * scratch pad index cannot be more than 16 as
- * mec has 64 bytes = 16 indexes of scratchpad RAM
- */
-#define MEC1322_IMAGETYPE_IDX     15
-
-/* LPC */
-#define MEC1322_LPC_CFG_BASE     0x400f3300
-#define MEC1322_LPC_ACT          REG8(MEC1322_LPC_CFG_BASE + 0x30)
-#define MEC1322_LPC_SIRQ(x)      REG8(MEC1322_LPC_CFG_BASE + 0x40 + (x))
-#define MEC1322_LPC_CFG_BAR      REG32(MEC1322_LPC_CFG_BASE + 0x60)
-#define MEC1322_LPC_EMI_BAR      REG32(MEC1322_LPC_CFG_BASE + 0x64)
-#define MEC1322_LPC_UART_BAR     REG32(MEC1322_LPC_CFG_BASE + 0x68)
-#define MEC1322_LPC_8042_BAR     REG32(MEC1322_LPC_CFG_BASE + 0x78)
-#define MEC1322_LPC_ACPI_EC0_BAR REG32(MEC1322_LPC_CFG_BASE + 0x88)
-#define MEC1322_LPC_ACPI_EC1_BAR REG32(MEC1322_LPC_CFG_BASE + 0x8c)
-#define MEC1322_LPC_ACPI_PM1_BAR REG32(MEC1322_LPC_CFG_BASE + 0x90)
-#define MEC1322_LPC_PORT92_BAR   REG32(MEC1322_LPC_CFG_BASE + 0x94)
-#define MEC1322_LPC_MAILBOX_BAR  REG32(MEC1322_LPC_CFG_BASE + 0x98)
-#define MEC1322_LPC_RTC_BAR      REG32(MEC1322_LPC_CFG_BASE + 0x9c)
-#define MEC1322_LPC_MEM_BAR      REG32(MEC1322_LPC_CFG_BASE + 0xa0)
-#define MEC1322_LPC_MEM_BAR_CFG  REG32(MEC1322_LPC_CFG_BASE + 0xa4)
-
-#define MEC1322_LPC_RT_BASE      0x400f3100
-#define MEC1322_LPC_BUS_MONITOR  REG32(MEC1322_LPC_RT_BASE + 0x4)
-#define MEC1322_LPC_CLK_CTRL     REG32(MEC1322_LPC_RT_BASE + 0x10)
-#define MEC1322_LPC_MEM_HOST_CFG REG32(MEC1322_LPC_RT_BASE + 0xfc)
-
-
-/* EMI */
-#define MEC1322_EMI_BASE       0x400f0100
-#define MEC1322_EMI_H2E_MBX    REG8(MEC1322_EMI_BASE + 0x0)
-#define MEC1322_EMI_E2H_MBX    REG8(MEC1322_EMI_BASE + 0x1)
-#define MEC1322_EMI_MBA0       REG32(MEC1322_EMI_BASE + 0x4)
-#define MEC1322_EMI_MRL0       REG16(MEC1322_EMI_BASE + 0x8)
-#define MEC1322_EMI_MWL0       REG16(MEC1322_EMI_BASE + 0xa)
-#define MEC1322_EMI_MBA1       REG32(MEC1322_EMI_BASE + 0xc)
-#define MEC1322_EMI_MRL1       REG16(MEC1322_EMI_BASE + 0x10)
-#define MEC1322_EMI_MWL1       REG16(MEC1322_EMI_BASE + 0x12)
-#define MEC1322_EMI_ISR        REG16(MEC1322_EMI_BASE + 0x14)
-#define MEC1322_EMI_HCE        REG16(MEC1322_EMI_BASE + 0x16)
-
-#define MEC1322_EMI_RT_BASE    0x400f0000
-#define MEC1322_EMI_ISR_B0     REG8(MEC1322_EMI_RT_BASE + 0x8)
-#define MEC1322_EMI_ISR_B1     REG8(MEC1322_EMI_RT_BASE + 0x9)
-#define MEC1322_EMI_IMR_B0     REG8(MEC1322_EMI_RT_BASE + 0xa)
-#define MEC1322_EMI_IMR_B1     REG8(MEC1322_EMI_RT_BASE + 0xb)
-
-
-/* Mailbox */
-#define MEC1322_MBX_RT_BASE    0x400f2400
-#define MEC1322_MBX_INDEX      REG8(MEC1322_MBX_RT_BASE + 0x0)
-#define MEC1322_MBX_DATA       REG8(MEC1322_MBX_RT_BASE + 0x1)
-
-#define MEC1322_MBX_BASE       0x400f2500
-#define MEC1322_MBX_H2E_MBX    REG8(MEC1322_MBX_BASE + 0x0)
-#define MEC1322_MBX_E2H_MBX    REG8(MEC1322_MBX_BASE + 0x4)
-#define MEC1322_MBX_ISR        REG8(MEC1322_MBX_BASE + 0x8)
-#define MEC1322_MBX_IMR        REG8(MEC1322_MBX_BASE + 0xc)
-#define MEC1322_MBX_REG(x)     REG8(MEC1322_MBX_BASE + 0x10 + (x))
-
-
-/* PWM */
-#define MEC1322_PWM_BASE(x)    (0x40005800 + (x) * 0x10)
-#define MEC1322_PWM_ON(x)      REG32(MEC1322_PWM_BASE(x) + 0x00)
-#define MEC1322_PWM_OFF(x)     REG32(MEC1322_PWM_BASE(x) + 0x04)
-#define MEC1322_PWM_CFG(x)     REG32(MEC1322_PWM_BASE(x) + 0x08)
-
-
-/* ACPI */
-#define MEC1322_ACPI_EC_BASE(x)     (0x400f0c00 + (x) * 0x400)
-#define MEC1322_ACPI_EC_EC2OS(x, y) REG8(MEC1322_ACPI_EC_BASE(x) + 0x100 + (y))
-#define MEC1322_ACPI_EC_STATUS(x)   REG8(MEC1322_ACPI_EC_BASE(x) + 0x104)
-#define MEC1322_ACPI_EC_BYTE_CTL(x) REG8(MEC1322_ACPI_EC_BASE(x) + 0x105)
-#define MEC1322_ACPI_EC_OS2EC(x, y) REG8(MEC1322_ACPI_EC_BASE(x) + 0x108 + (y))
-
-#define MEC1322_ACPI_PM_RT_BASE     0x400f1400
-#define MEC1322_ACPI_PM1_STS1       REG8(MEC1322_ACPI_PM_RT_BASE + 0x0)
-#define MEC1322_ACPI_PM1_STS2       REG8(MEC1322_ACPI_PM_RT_BASE + 0x1)
-#define MEC1322_ACPI_PM1_EN1        REG8(MEC1322_ACPI_PM_RT_BASE + 0x2)
-#define MEC1322_ACPI_PM1_EN2        REG8(MEC1322_ACPI_PM_RT_BASE + 0x3)
-#define MEC1322_ACPI_PM1_CTL1       REG8(MEC1322_ACPI_PM_RT_BASE + 0x4)
-#define MEC1322_ACPI_PM1_CTL2       REG8(MEC1322_ACPI_PM_RT_BASE + 0x5)
-#define MEC1322_ACPI_PM2_CTL1       REG8(MEC1322_ACPI_PM_RT_BASE + 0x6)
-#define MEC1322_ACPI_PM2_CTL2       REG8(MEC1322_ACPI_PM_RT_BASE + 0x7)
-#define MEC1322_ACPI_PM_EC_BASE     0x400f1500
-#define MEC1322_ACPI_PM_STS         REG8(MEC1322_ACPI_PM_EC_BASE + 0x10)
-
-
-/* 8042 */
-#define MEC1322_8042_BASE      0x400f0400
-#define MEC1322_8042_OBF_CLR   REG8(MEC1322_8042_BASE + 0x0)
-#define MEC1322_8042_H2E       REG8(MEC1322_8042_BASE + 0x100)
-#define MEC1322_8042_E2H       REG8(MEC1322_8042_BASE + 0x100)
-#define MEC1322_8042_STS       REG8(MEC1322_8042_BASE + 0x104)
-#define MEC1322_8042_KB_CTRL   REG8(MEC1322_8042_BASE + 0x108)
-#define MEC1322_8042_PCOBF     REG8(MEC1322_8042_BASE + 0x114)
-#define MEC1322_8042_ACT       REG8(MEC1322_8042_BASE + 0x330)
-
-
-/* FAN */
-#define MEC1322_FAN_BASE       0x4000a000
-#define MEC1322_FAN_SETTING    REG8(MEC1322_FAN_BASE + 0x0)
-#define MEC1322_FAN_PWM_DIVIDE REG8(MEC1322_FAN_BASE + 0x1)
-#define MEC1322_FAN_CFG1       REG8(MEC1322_FAN_BASE + 0x2)
-#define MEC1322_FAN_CFG2       REG8(MEC1322_FAN_BASE + 0x3)
-#define MEC1322_FAN_GAIN       REG8(MEC1322_FAN_BASE + 0x5)
-#define MEC1322_FAN_SPIN_UP    REG8(MEC1322_FAN_BASE + 0x6)
-#define MEC1322_FAN_STEP       REG8(MEC1322_FAN_BASE + 0x7)
-#define MEC1322_FAN_MIN_DRV    REG8(MEC1322_FAN_BASE + 0x8)
-#define MEC1322_FAN_VALID_CNT  REG8(MEC1322_FAN_BASE + 0x9)
-#define MEC1322_FAN_DRV_FAIL   REG16(MEC1322_FAN_BASE + 0xa)
-#define MEC1322_FAN_TARGET     REG16(MEC1322_FAN_BASE + 0xc)
-#define MEC1322_FAN_READING    REG16(MEC1322_FAN_BASE + 0xe)
-#define MEC1322_FAN_BASE_FREQ  REG8(MEC1322_FAN_BASE + 0x10)
-#define MEC1322_FAN_STATUS     REG8(MEC1322_FAN_BASE + 0x11)
-
-
-/* I2C */
-#define MEC1322_I2C0_BASE      0x40001800
-#define MEC1322_I2C1_BASE      0x4000ac00
-#define MEC1322_I2C2_BASE      0x4000b000
-#define MEC1322_I2C3_BASE      0x4000b400
-#define MEC1322_I2C_BASESEP    0x00000400
-#define MEC1322_I2C_ADDR(controller, offset) \
-	(offset + (controller == 0 ? MEC1322_I2C0_BASE : \
-		   MEC1322_I2C1_BASE + MEC1322_I2C_BASESEP * (controller - 1)))
-
-/*
- * MEC1322 has five ports distributed among four controllers. Locking must
- * occur by-controller (not by-port).
- */
-enum mec1322_i2c_port {
-	MEC1322_I2C0_0 = 0,      /* Controller 0, port 0 */
-	MEC1322_I2C0_1 = 1,      /* Controller 0, port 1 */
-	MEC1322_I2C1   = 2,      /* Controller 1 */
-	MEC1322_I2C2   = 3,      /* Controller 2 */
-	MEC1322_I2C3   = 4,      /* Controller 3 */
-	MEC1322_I2C_PORT_COUNT,
-};
-
-#define MEC1322_I2C_CTRL(ctrl)          REG8(MEC1322_I2C_ADDR(ctrl, 0x0))
-#define MEC1322_I2C_STATUS(ctrl)        REG8(MEC1322_I2C_ADDR(ctrl, 0x0))
-#define MEC1322_I2C_OWN_ADDR(ctrl)      REG16(MEC1322_I2C_ADDR(ctrl, 0x4))
-#define MEC1322_I2C_DATA(ctrl)          REG8(MEC1322_I2C_ADDR(ctrl, 0x8))
-#define MEC1322_I2C_MASTER_CMD(ctrl)    REG32(MEC1322_I2C_ADDR(ctrl, 0xc))
-#define MEC1322_I2C_SLAVE_CMD(ctrl)     REG32(MEC1322_I2C_ADDR(ctrl, 0x10))
-#define MEC1322_I2C_PEC(ctrl)           REG8(MEC1322_I2C_ADDR(ctrl, 0x14))
-#define MEC1322_I2C_DATA_TIM_2(ctrl)    REG8(MEC1322_I2C_ADDR(ctrl, 0x18))
-#define MEC1322_I2C_COMPLETE(ctrl)      REG32(MEC1322_I2C_ADDR(ctrl, 0x20))
-#define MEC1322_I2C_IDLE_SCALE(ctrl)    REG32(MEC1322_I2C_ADDR(ctrl, 0x24))
-#define MEC1322_I2C_CONFIG(ctrl)        REG32(MEC1322_I2C_ADDR(ctrl, 0x28))
-#define MEC1322_I2C_BUS_CLK(ctrl)       REG16(MEC1322_I2C_ADDR(ctrl, 0x2c))
-#define MEC1322_I2C_BLK_ID(ctrl)        REG8(MEC1322_I2C_ADDR(ctrl, 0x30))
-#define MEC1322_I2C_REV(ctrl)           REG8(MEC1322_I2C_ADDR(ctrl, 0x34))
-#define MEC1322_I2C_BB_CTRL(ctrl)       REG8(MEC1322_I2C_ADDR(ctrl, 0x38))
-#define MEC1322_I2C_DATA_TIM(ctrl)      REG32(MEC1322_I2C_ADDR(ctrl, 0x40))
-#define MEC1322_I2C_TOUT_SCALE(ctrl)    REG32(MEC1322_I2C_ADDR(ctrl, 0x44))
-#define MEC1322_I2C_SLAVE_TX_BUF(ctrl)  REG8(MEC1322_I2C_ADDR(ctrl, 0x48))
-#define MEC1322_I2C_SLAVE_RX_BUF(ctrl)  REG8(MEC1322_I2C_ADDR(ctrl, 0x4c))
-#define MEC1322_I2C_MASTER_TX_BUF(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x50))
-#define MEC1322_I2C_MASTER_RX_BUF(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x54))
-
-
-/* Keyboard scan matrix */
-#define MEC1322_KS_BASE        0x40009c00
-#define MEC1322_KS_KSO_SEL     REG32(MEC1322_KS_BASE + 0x4)
-#define MEC1322_KS_KSI_INPUT   REG32(MEC1322_KS_BASE + 0x8)
-#define MEC1322_KS_KSI_STATUS  REG32(MEC1322_KS_BASE + 0xc)
-#define MEC1322_KS_KSI_INT_EN  REG32(MEC1322_KS_BASE + 0x10)
-#define MEC1322_KS_EXT_CTRL    REG32(MEC1322_KS_BASE + 0x14)
-
-
-/* ADC */
-#define MEC1322_ADC_BASE       0x40007c00
-#define MEC1322_ADC_CTRL       REG32(MEC1322_ADC_BASE + 0x0)
-#define MEC1322_ADC_DELAY      REG32(MEC1322_ADC_BASE + 0x4)
-#define MEC1322_ADC_STS        REG32(MEC1322_ADC_BASE + 0x8)
-#define MEC1322_ADC_SINGLE     REG32(MEC1322_ADC_BASE + 0xc)
-#define MEC1322_ADC_REPEAT     REG32(MEC1322_ADC_BASE + 0x10)
-#define MEC1322_ADC_READ(x)    REG32(MEC1322_ADC_BASE + 0x14 + (x) * 0x4)
-
-
-/* Hibernation timer */
-#define MEC1322_HTIMER_BASE    0x40009800
-#define MEC1322_HTIMER_PRELOAD REG16(MEC1322_HTIMER_BASE + 0x0)
-#define MEC1322_HTIMER_CONTROL REG16(MEC1322_HTIMER_BASE + 0x4)
-#define MEC1322_HTIMER_COUNT   REG16(MEC1322_HTIMER_BASE + 0x8)
-
-
-/* SPI */
-#define MEC1322_SPI_BASE(port) (0x40009400 + 0x80 * (port))
-#define MEC1322_SPI_AR(port)   REG8(MEC1322_SPI_BASE(port) + 0x00)
-#define MEC1322_SPI_CR(port)   REG8(MEC1322_SPI_BASE(port) + 0x04)
-#define MEC1322_SPI_SR(port)   REG8(MEC1322_SPI_BASE(port) + 0x08)
-#define MEC1322_SPI_TD(port)   REG8(MEC1322_SPI_BASE(port) + 0x0c)
-#define MEC1322_SPI_RD(port)   REG8(MEC1322_SPI_BASE(port) + 0x10)
-#define MEC1322_SPI_CC(port)   REG8(MEC1322_SPI_BASE(port) + 0x14)
-#define MEC1322_SPI_CG(port)   REG8(MEC1322_SPI_BASE(port) + 0x18)
-
-
-/* DMA */
-#define MEC1322_DMA_BASE            0x40002400
-
-/*
- * Available DMA channels.
- *
- * On MEC1322, any DMA channel may serve any device. Since we have
- * 12 channels and 12 devices, we make each channel dedicated to the
- * device of the same number.
- */
-enum dma_channel {
-	/* Channel numbers */
-	MEC1322_DMAC_I2C0_SLAVE =  0,
-	MEC1322_DMAC_I2C0_MASTER = 1,
-	MEC1322_DMAC_I2C1_SLAVE =  2,
-	MEC1322_DMAC_I2C1_MASTER = 3,
-	MEC1322_DMAC_I2C2_SLAVE =  4,
-	MEC1322_DMAC_I2C2_MASTER = 5,
-	MEC1322_DMAC_I2C3_SLAVE =  6,
-	MEC1322_DMAC_I2C3_MASTER = 7,
-	MEC1322_DMAC_SPI0_TX =     8,
-	MEC1322_DMAC_SPI0_RX =     9,
-	MEC1322_DMAC_SPI1_TX =    10,
-	MEC1322_DMAC_SPI1_RX =    11,
-
-	/* Channel count */
-	MEC1322_DMAC_COUNT =      12,
-};
-
-/* Registers for a single channel of the DMA controller */
-struct mec1322_dma_chan {
-	uint32_t act;         /* Activate */
-	uint32_t mem_start;   /* Memory start address */
-	uint32_t mem_end;     /* Memory end address */
-	uint32_t dev;         /* Device address */
-	uint32_t ctrl;        /* Control */
-	uint32_t int_status;  /* Interrupt status */
-	uint32_t int_enabled; /* Interrupt enabled */
-	uint32_t pad;
-};
-
-/* Always use mec1322_dma_chan_t so volatile keyword is included! */
-typedef volatile struct mec1322_dma_chan mec1322_dma_chan_t;
-
-/* Common code and header file must use this */
-typedef mec1322_dma_chan_t dma_chan_t;
-
-/* Registers for the DMA controller */
-struct mec1322_dma_regs {
-	uint32_t ctrl;
-	uint32_t data;
-	uint32_t pad[2];
-	mec1322_dma_chan_t chan[MEC1322_DMAC_COUNT];
-};
-
-/* Always use mec1322_dma_regs_t so volatile keyword is included! */
-typedef volatile struct mec1322_dma_regs mec1322_dma_regs_t;
-
-#define MEC1322_DMA_REGS ((mec1322_dma_regs_t *)MEC1322_DMA_BASE)
-
-/* Bits for DMA channel regs */
-#define MEC1322_DMA_ACT_EN		BIT(0)
-#define MEC1322_DMA_XFER_SIZE(x)	((x) << 20)
-#define MEC1322_DMA_INC_DEV		BIT(17)
-#define MEC1322_DMA_INC_MEM		BIT(16)
-#define MEC1322_DMA_DEV(x)		((x) << 9)
-#define MEC1322_DMA_TO_DEV		BIT(8)
-#define MEC1322_DMA_DONE		BIT(2)
-#define MEC1322_DMA_RUN			BIT(0)
-
-
-/* IRQ Numbers */
-#define MEC1322_IRQ_I2C_0        0
-#define MEC1322_IRQ_I2C_1        1
-#define MEC1322_IRQ_I2C_2        2
-#define MEC1322_IRQ_I2C_3        3
-#define MEC1322_IRQ_DMA_0        4
-#define MEC1322_IRQ_DMA_1        5
-#define MEC1322_IRQ_DMA_2        6
-#define MEC1322_IRQ_DMA_3        7
-#define MEC1322_IRQ_DMA_4        8
-#define MEC1322_IRQ_DMA_5        9
-#define MEC1322_IRQ_DMA_6        10
-#define MEC1322_IRQ_DMA_7        11
-#define MEC1322_IRQ_LPC          12
-#define MEC1322_IRQ_UART         13
-#define MEC1322_IRQ_EMI          14
-#define MEC1322_IRQ_ACPIEC0_IBF  15
-#define MEC1322_IRQ_ACPIEC0_OBF  16
-#define MEC1322_IRQ_ACPIEC1_IBF  17
-#define MEC1322_IRQ_ACPIEC1_OBF  18
-#define MEC1322_IRQ_ACPIPM1_CTL  19
-#define MEC1322_IRQ_ACPIPM1_EN   20
-#define MEC1322_IRQ_ACPIPM1_STS  21
-#define MEC1322_IRQ_8042EM_OBF   22
-#define MEC1322_IRQ_8042EM_IBF   23
-#define MEC1322_IRQ_MAILBOX      24
-#define MEC1322_IRQ_PECI_HOST    25
-#define MEC1322_IRQ_TACH_0       26
-#define MEC1322_IRQ_TACH_1       27
-#define MEC1322_IRQ_ADC_SNGL     28
-#define MEC1322_IRQ_ADC_RPT      29
-#define MEC1322_IRQ_PS2_0        32
-#define MEC1322_IRQ_PS2_1        33
-#define MEC1322_IRQ_PS2_2        34
-#define MEC1322_IRQ_PS2_3        35
-#define MEC1322_IRQ_SPI0_TX      36
-#define MEC1322_IRQ_SPI0_RX      37
-#define MEC1322_IRQ_HTIMER       38
-#define MEC1322_IRQ_KSC_INT      39
-#define MEC1322_IRQ_MAILBOX_DATA 40
-#define MEC1322_IRQ_TIMER16_0    49
-#define MEC1322_IRQ_TIMER16_1    50
-#define MEC1322_IRQ_TIMER16_2    51
-#define MEC1322_IRQ_TIMER16_3    52
-#define MEC1322_IRQ_TIMER32_0    53
-#define MEC1322_IRQ_TIMER32_1    54
-#define MEC1322_IRQ_SPI1_TX      55
-#define MEC1322_IRQ_SPI1_RX      56
-#define MEC1322_IRQ_GIRQ8        57
-#define MEC1322_IRQ_GIRQ9        58
-#define MEC1322_IRQ_GIRQ10       59
-#define MEC1322_IRQ_GIRQ11       60
-#define MEC1322_IRQ_GIRQ12       61
-#define MEC1322_IRQ_GIRQ13       62
-#define MEC1322_IRQ_GIRQ14       63
-#define MEC1322_IRQ_GIRQ15       64
-#define MEC1322_IRQ_GIRQ16       65
-#define MEC1322_IRQ_GIRQ17       66
-#define MEC1322_IRQ_GIRQ18       67
-#define MEC1322_IRQ_GIRQ19       68
-#define MEC1322_IRQ_GIRQ20       69
-#define MEC1322_IRQ_GIRQ21       70
-#define MEC1322_IRQ_GIRQ22       71
-#define MEC1322_IRQ_GIRQ23       72
-#define MEC1322_IRQ_DMA_8        81
-#define MEC1322_IRQ_DMA_9        82
-#define MEC1322_IRQ_DMA_10       83
-#define MEC1322_IRQ_DMA_11       84
-#define MEC1322_IRQ_PWM_WDT3     85
-#define MEC1322_IRQ_RTC          91
-#define MEC1322_IRQ_RTC_ALARM    92
-
-/* Wake pin definitions, defined at board-level */
-#ifndef CONFIG_HIBERNATE_WAKE_PINS_DYNAMIC
-extern const enum gpio_signal hibernate_wake_pins[];
-extern const int hibernate_wake_pins_used;
-#else
-extern enum gpio_signal hibernate_wake_pins[];
-extern int hibernate_wake_pins_used;
-#endif
-
-#endif /* __CROS_EC_REGISTERS_H */
diff --git a/chip/mec1322/spi.c b/chip/mec1322/spi.c
deleted file mode 100644
index ba58bfb0bd..0000000000
--- a/chip/mec1322/spi.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* SPI master module for MEC1322 */
-
-#include "common.h"
-#include "console.h"
-#include "dma.h"
-#include "gpio.h"
-#include "registers.h"
-#include "spi.h"
-#include "timer.h"
-#include "util.h"
-#include "hooks.h"
-#include "task.h"
-
-#define CPUTS(outstr) cputs(CC_SPI, outstr)
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
-
-#define SPI_BYTE_TRANSFER_TIMEOUT_US (3 * MSEC)
-#define SPI_BYTE_TRANSFER_POLL_INTERVAL_US 100
-
-#define SPI_DMA_CHANNEL(port) (MEC1322_DMAC_SPI0_RX + (port) * 2)
-
-/* only regular image needs mutex, LFW does not have scheduling */
-/* TODO: Move SPI locking to common code */
-#ifndef LFW
-static struct mutex spi_mutex;
-#endif
-
-static const struct dma_option spi_rx_option[] = {
-	{
-		SPI_DMA_CHANNEL(0),
-		(void *)&MEC1322_SPI_RD(0),
-		MEC1322_DMA_XFER_SIZE(1)
-	},
-	{
-		SPI_DMA_CHANNEL(1),
-		(void *)&MEC1322_SPI_RD(1),
-		MEC1322_DMA_XFER_SIZE(1)
-	},
-};
-
-static int wait_byte(const int port)
-{
-	timestamp_t deadline;
-
-	deadline.val = get_time().val + SPI_BYTE_TRANSFER_TIMEOUT_US;
-	while ((MEC1322_SPI_SR(port) & 0x3) != 0x3) {
-		if (timestamp_expired(deadline, NULL))
-			return EC_ERROR_TIMEOUT;
-		usleep(SPI_BYTE_TRANSFER_POLL_INTERVAL_US);
-	}
-	return EC_SUCCESS;
-}
-
-static int spi_tx(const int port, const uint8_t *txdata, int txlen)
-{
-	int i;
-	int ret = EC_SUCCESS;
-	uint8_t unused __attribute__((unused)) = 0;
-
-	for (i = 0; i < txlen; ++i) {
-		MEC1322_SPI_TD(port) = txdata[i];
-		ret = wait_byte(port);
-		if (ret != EC_SUCCESS)
-			return ret;
-		unused = MEC1322_SPI_RD(port);
-	}
-
-	return ret;
-}
-
-int spi_transaction_async(const struct spi_device_t *spi_device,
-			  const uint8_t *txdata, int txlen,
-			  uint8_t *rxdata, int rxlen)
-{
-	int port = spi_device->port;
-	int ret = EC_SUCCESS;
-
-	gpio_set_level(spi_device->gpio_cs, 0);
-
-	/* Disable auto read */
-	MEC1322_SPI_CR(port) &= ~BIT(5);
-
-	ret = spi_tx(port, txdata, txlen);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	/* Enable auto read */
-	MEC1322_SPI_CR(port) |= BIT(5);
-
-	if (rxlen != 0) {
-		dma_start_rx(&spi_rx_option[port], rxlen, rxdata);
-		MEC1322_SPI_TD(port) = 0;
-	}
-	return ret;
-}
-
-int spi_transaction_flush(const struct spi_device_t *spi_device)
-{
-	int port = spi_device->port;
-	int ret = dma_wait(SPI_DMA_CHANNEL(port));
-	uint8_t unused __attribute__((unused)) = 0;
-
-	timestamp_t deadline;
-
-	/* Disable auto read */
-	MEC1322_SPI_CR(port) &= ~BIT(5);
-
-	deadline.val = get_time().val + SPI_BYTE_TRANSFER_TIMEOUT_US;
-	/* Wait for FIFO empty SPISR_TXBE */
-	while ((MEC1322_SPI_SR(port) & 0x01) != 0x1) {
-		if (timestamp_expired(deadline, NULL))
-			return EC_ERROR_TIMEOUT;
-		usleep(SPI_BYTE_TRANSFER_POLL_INTERVAL_US);
-	}
-
-	dma_disable(SPI_DMA_CHANNEL(port));
-	dma_clear_isr(SPI_DMA_CHANNEL(port));
-	if (MEC1322_SPI_SR(port) & 0x2)
-		unused = MEC1322_SPI_RD(port);
-
-	gpio_set_level(spi_device->gpio_cs, 1);
-
-	return ret;
-}
-
-int spi_transaction(const struct spi_device_t *spi_device,
-		    const uint8_t *txdata, int txlen,
-		    uint8_t *rxdata, int rxlen)
-{
-	int ret;
-
-#ifndef LFW
-	mutex_lock(&spi_mutex);
-#endif
-	ret = spi_transaction_async(spi_device, txdata, txlen, rxdata, rxlen);
-	if (ret)
-		return ret;
-	ret = spi_transaction_flush(spi_device);
-
-#ifndef LFW
-	mutex_unlock(&spi_mutex);
-#endif
-	return ret;
-}
-
-int spi_enable(int port, int enable)
-{
-	if (enable) {
-		gpio_config_module(MODULE_SPI, 1);
-
-		/* Set enable bit in SPI_AR */
-		MEC1322_SPI_AR(port) |= 0x1;
-
-		/* Set SPDIN to 0 -> Full duplex */
-		MEC1322_SPI_CR(port) &= ~(0x3 << 2);
-
-		/* Set CLKPOL, TCLKPH, RCLKPH to 0 */
-		MEC1322_SPI_CC(port) &= ~0x7;
-
-		/* Set LSBF to 0 -> MSB first */
-		MEC1322_SPI_CR(port) &= ~0x1;
-	} else {
-		/* Clear enable bit in SPI_AR */
-		MEC1322_SPI_AR(port) &= ~0x1;
-
-		gpio_config_module(MODULE_SPI, 0);
-	}
-
-	return EC_SUCCESS;
-}
-
diff --git a/chip/mec1322/system.c b/chip/mec1322/system.c
deleted file mode 100644
index a3043ba46b..0000000000
--- a/chip/mec1322/system.c
+++ /dev/null
@@ -1,393 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* System module for Chrome EC : MEC1322 hardware specific implementation */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "gpio.h"
-#include "host_command.h"
-#include "registers.h"
-#include "shared_mem.h"
-#include "system.h"
-#include "hooks.h"
-#include "task.h"
-#include "timer.h"
-#include "usb_pd.h"
-#include "util.h"
-#include "spi.h"
-
-/* Indices for hibernate data registers (RAM backed by VBAT) */
-enum hibdata_index {
-	HIBDATA_INDEX_SCRATCHPAD = 0,    /* General-purpose scratchpad */
-	HIBDATA_INDEX_SAVED_RESET_FLAGS, /* Saved reset flags */
-	HIBDATA_INDEX_PD0,               /* USB-PD0 saved port state */
-	HIBDATA_INDEX_PD1,               /* USB-PD1 saved port state */
-	HIBDATA_INDEX_PD2,               /* USB-PD2 saved port state */
-};
-
-static void check_reset_cause(void)
-{
-	uint32_t status = MEC1322_VBAT_STS;
-	uint32_t flags = 0;
-	uint32_t rst_sts = MEC1322_PCR_CHIP_PWR_RST &
-				(MEC1322_PWR_RST_STS_VCC1 |
-				MEC1322_PWR_RST_STS_VBAT);
-
-	/* Clear the reset causes now that we've read them */
-	MEC1322_VBAT_STS |= status;
-	MEC1322_PCR_CHIP_PWR_RST |= rst_sts;
-
-	/*
-	* BIT[6] determine VCC1 reset
-	*/
-	if (rst_sts & MEC1322_PWR_RST_STS_VCC1)
-		flags |= EC_RESET_FLAG_RESET_PIN;
-
-
-	flags |= MEC1322_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS);
-	MEC1322_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS) = 0;
-
-	if ((status & MEC1322_VBAT_STS_WDT) && !(flags & (EC_RESET_FLAG_SOFT |
-					    EC_RESET_FLAG_HARD |
-					    EC_RESET_FLAG_HIBERNATE)))
-		flags |= EC_RESET_FLAG_WATCHDOG;
-
-	system_set_reset_flags(flags);
-}
-
-int system_is_reboot_warm(void)
-{
-	uint32_t reset_flags;
-	/*
-	* Check reset cause here,
-	* gpio_pre_init is executed faster than system_pre_init
-	*/
-	check_reset_cause();
-	reset_flags = system_get_reset_flags();
-
-	if ((reset_flags & EC_RESET_FLAG_RESET_PIN) ||
-		(reset_flags & EC_RESET_FLAG_POWER_ON) ||
-		(reset_flags & EC_RESET_FLAG_WATCHDOG) ||
-		(reset_flags & EC_RESET_FLAG_HARD) ||
-		(reset_flags & EC_RESET_FLAG_SOFT) ||
-		(reset_flags & EC_RESET_FLAG_HIBERNATE))
-		return 0;
-	else
-		return 1;
-}
-
-void system_pre_init(void)
-{
-	/* Enable direct NVIC */
-	MEC1322_EC_INT_CTRL |= 1;
-
-	/* Disable ARM TRACE debug port */
-	MEC1322_EC_TRACE_EN &= ~1;
-
-	/* Deassert nSIO_RESET */
-	MEC1322_PCR_PWR_RST_CTL &= ~BIT(0);
-
-	spi_enable(CONFIG_SPI_FLASH_PORT, 1);
-}
-
-void chip_save_reset_flags(uint32_t flags)
-{
-	MEC1322_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS) = flags;
-}
-
-uint32_t chip_read_reset_flags(void)
-{
-	return MEC1322_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS);
-}
-
-noreturn
-void _system_reset(int flags, int wake_from_hibernate)
-{
-	uint32_t save_flags = 0;
-
-	/* Disable interrupts to avoid task swaps during reboot */
-	interrupt_disable();
-
-	/* Save current reset reasons if necessary */
-	if (flags & SYSTEM_RESET_PRESERVE_FLAGS)
-		save_flags = system_get_reset_flags() | EC_RESET_FLAG_PRESERVED;
-
-	if (flags & SYSTEM_RESET_LEAVE_AP_OFF)
-		save_flags |= EC_RESET_FLAG_AP_OFF;
-
-	if (wake_from_hibernate)
-		save_flags |= EC_RESET_FLAG_HIBERNATE;
-	else if (flags & SYSTEM_RESET_HARD)
-		save_flags |= EC_RESET_FLAG_HARD;
-	else
-		save_flags |= EC_RESET_FLAG_SOFT;
-
-	chip_save_reset_flags(save_flags);
-
-	/* Trigger watchdog in 1ms */
-	MEC1322_WDG_LOAD = 1;
-	MEC1322_WDG_CTL |= 1;
-
-	/* Spin and wait for reboot; should never return */
-	while (1)
-		;
-}
-
-void system_reset(int flags)
-{
-	_system_reset(flags, 0);
-}
-
-const char *system_get_chip_vendor(void)
-{
-	return "smsc";
-}
-
-const char *system_get_chip_name(void)
-{
-	switch (MEC1322_CHIP_DEV_ID) {
-	case 0x15:
-		return "mec1322";
-	default:
-		return "unknown";
-	}
-}
-
-static char to_hex(int x)
-{
-	if (x >= 0 && x <= 9)
-		return '0' + x;
-	return 'a' + x - 10;
-}
-
-const char *system_get_chip_revision(void)
-{
-	static char buf[3];
-	uint8_t rev = MEC1322_CHIP_DEV_REV;
-
-	buf[0] = to_hex(rev / 16);
-	buf[1] = to_hex(rev & 0xf);
-	buf[2] = '\0';
-	return buf;
-}
-
-static int bbram_idx_lookup(enum system_bbram_idx idx)
-{
-	switch (idx) {
-	case SYSTEM_BBRAM_IDX_PD0:
-		return HIBDATA_INDEX_PD0;
-	case SYSTEM_BBRAM_IDX_PD1:
-		return HIBDATA_INDEX_PD1;
-	case SYSTEM_BBRAM_IDX_PD2:
-		return HIBDATA_INDEX_PD2;
-	default:
-		return -1;
-	}
-}
-
-int system_get_bbram(enum system_bbram_idx idx, uint8_t *value)
-{
-	int hibdata = bbram_idx_lookup(idx);
-
-	if (hibdata < 0)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	*value = MEC1322_VBAT_RAM(hibdata);
-	return EC_SUCCESS;
-}
-
-int system_set_bbram(enum system_bbram_idx idx, uint8_t value)
-{
-	int hibdata = bbram_idx_lookup(idx);
-
-	if (hibdata < 0)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	MEC1322_VBAT_RAM(hibdata) = value;
-	return EC_SUCCESS;
-}
-
-int system_set_scratchpad(uint32_t value)
-{
-	MEC1322_VBAT_RAM(HIBDATA_INDEX_SCRATCHPAD) = value;
-	return EC_SUCCESS;
-}
-
-uint32_t system_get_scratchpad(void)
-{
-	return MEC1322_VBAT_RAM(HIBDATA_INDEX_SCRATCHPAD);
-}
-
-void system_hibernate(uint32_t seconds, uint32_t microseconds)
-{
-	int i;
-
-#ifdef CONFIG_HOSTCMD_PD
-	/* Inform the PD MCU that we are going to hibernate. */
-	host_command_pd_request_hibernate();
-	/* Wait to ensure exchange with PD before hibernating. */
-	msleep(100);
-#endif
-
-	cflush();
-
-	if (board_hibernate)
-		board_hibernate();
-
-	/* Disable interrupts */
-	interrupt_disable();
-	for (i = 0; i <= 92; ++i) {
-		task_disable_irq(i);
-		task_clear_pending_irq(i);
-	}
-
-	for (i = 8; i <= 23; ++i)
-		MEC1322_INT_DISABLE(i) = 0xffffffff;
-
-	MEC1322_INT_BLK_DIS |= 0xffff00;
-
-	/* Power down ADC VREF */
-	MEC1322_EC_ADC_VREF_PD |= 1;
-
-	/* Assert nSIO_RESET */
-	MEC1322_PCR_PWR_RST_CTL |= 1;
-
-	/* Disable UART */
-	MEC1322_UART_ACT &= ~0x1;
-	MEC1322_LPC_ACT &= ~0x1;
-
-	/* Disable JTAG */
-	MEC1322_EC_JTAG_EN &= ~1;
-
-	/* Disable 32KHz clock */
-	MEC1322_VBAT_CE &= ~0x2;
-
-	/* Stop watchdog */
-	MEC1322_WDG_CTL &= ~1;
-
-	/* Stop timers */
-	MEC1322_TMR32_CTL(0) &= ~1;
-	MEC1322_TMR32_CTL(1) &= ~1;
-	MEC1322_TMR16_CTL(0) &= ~1;
-
-	/* Power down ADC */
-	MEC1322_ADC_CTRL &= ~1;
-
-	/* Disable blocks */
-	MEC1322_PCR_CHIP_SLP_EN |= 0x3;
-	MEC1322_PCR_EC_SLP_EN |= MEC1322_PCR_EC_SLP_EN_SLEEP;
-	MEC1322_PCR_HOST_SLP_EN |= MEC1322_PCR_HOST_SLP_EN_SLEEP;
-	MEC1322_PCR_EC_SLP_EN2 |= MEC1322_PCR_EC_SLP_EN2_SLEEP;
-	MEC1322_PCR_SLOW_CLK_CTL &= 0xfffffc00;
-
-	/* Set sleep state */
-	MEC1322_PCR_SYS_SLP_CTL = (MEC1322_PCR_SYS_SLP_CTL & ~0x7) | 0x2;
-	CPU_SCB_SYSCTRL |= 0x4;
-
-	/* Setup GPIOs for hibernate */
-	if (board_hibernate_late)
-		board_hibernate_late();
-
-#ifdef CONFIG_USB_PD_PORT_MAX_COUNT
-	/*
-	 * Leave USB-C charging enabled in hibernate, in order to
-	 * allow wake-on-plug. 5V enable must be pulled low.
-	 */
-	switch (board_get_usb_pd_port_count()) {
-#if CONFIG_USB_PD_PORT_MAX_COUNT >= 2
-	case 2:
-		gpio_set_flags(GPIO_USB_C1_5V_EN, GPIO_PULL_DOWN | GPIO_INPUT);
-		gpio_set_level(GPIO_USB_C1_CHARGE_EN_L, 0);
-		/* Fall through */
-#endif
-#if CONFIG_USB_PD_PORT_MAX_COUNT >= 1
-	case 1:
-		gpio_set_flags(GPIO_USB_C0_5V_EN, GPIO_PULL_DOWN | GPIO_INPUT);
-		gpio_set_level(GPIO_USB_C0_CHARGE_EN_L, 0);
-		/* Fall through */
-#endif
-	case 0:
-		/* Nothing to do but break */
-		break;
-	default:
-		/* More ports needs to be defined */
-		ASSERT(false);
-		break;
-	}
-#endif /* CONFIG_USB_PD_PORT_MAX_COUNT */
-
-	if (hibernate_wake_pins_used > 0) {
-		for (i = 0; i < hibernate_wake_pins_used; ++i) {
-			const enum gpio_signal pin = hibernate_wake_pins[i];
-
-			gpio_reset(pin);
-			gpio_enable_interrupt(pin);
-		}
-
-		interrupt_enable();
-		task_enable_irq(MEC1322_IRQ_GIRQ8);
-		task_enable_irq(MEC1322_IRQ_GIRQ9);
-		task_enable_irq(MEC1322_IRQ_GIRQ10);
-		task_enable_irq(MEC1322_IRQ_GIRQ11);
-		task_enable_irq(MEC1322_IRQ_GIRQ20);
-	}
-
-	if (seconds || microseconds) {
-		MEC1322_INT_BLK_EN |= BIT(17);
-		MEC1322_INT_ENABLE(17) |= BIT(20);
-		interrupt_enable();
-		task_enable_irq(MEC1322_IRQ_HTIMER);
-		if (seconds > 2) {
-			ASSERT(seconds <= 0xffff / 8);
-			MEC1322_HTIMER_CONTROL = 1;
-			MEC1322_HTIMER_PRELOAD =
-				(seconds * 8 + microseconds / 125000);
-		} else {
-			MEC1322_HTIMER_CONTROL = 0;
-			MEC1322_HTIMER_PRELOAD =
-				(seconds * 1000000 + microseconds) * 2 / 71;
-		}
-	}
-
-	asm("wfi");
-
-	/* Use 48MHz clock to speed through wake-up */
-	MEC1322_PCR_PROC_CLK_CTL = 1;
-
-	/* Reboot */
-	_system_reset(0, 1);
-
-	/* We should never get here. */
-	while (1)
-		;
-}
-
-void htimer_interrupt(void)
-{
-	/* Time to wake up */
-}
-DECLARE_IRQ(MEC1322_IRQ_HTIMER, htimer_interrupt, 1);
-
-enum ec_image system_get_shrspi_image_copy(void)
-{
-	return MEC1322_VBAT_RAM(MEC1322_IMAGETYPE_IDX);
-}
-
-uint32_t system_get_lfw_address(void)
-{
-	uint32_t * const lfw_vector =
-		(uint32_t * const)CONFIG_PROGRAM_MEMORY_BASE;
-
-	return *(lfw_vector + 1);
-}
-
-void system_set_image_copy(enum ec_image copy)
-{
-	MEC1322_VBAT_RAM(MEC1322_IMAGETYPE_IDX) = (copy == EC_IMAGE_RW) ?
-				EC_IMAGE_RW : EC_IMAGE_RO;
-}
diff --git a/chip/mec1322/uart.c b/chip/mec1322/uart.c
deleted file mode 100644
index 2c607d0b72..0000000000
--- a/chip/mec1322/uart.c
+++ /dev/null
@@ -1,220 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* UART module for MEC1322 */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "lpc.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "uart.h"
-#include "util.h"
-
-#define TX_FIFO_SIZE 16
-
-static int init_done;
-static int tx_fifo_used;
-
-int uart_init_done(void)
-{
-	return init_done;
-}
-
-void uart_tx_start(void)
-{
-	/* If interrupt is already enabled, nothing to do */
-	if (MEC1322_UART_IER & BIT(1))
-		return;
-
-	/* Do not allow deep sleep while transmit in progress */
-	disable_sleep(SLEEP_MASK_UART);
-
-	/*
-	 * Re-enable the transmit interrupt, then forcibly trigger the
-	 * interrupt.  This works around a hardware problem with the
-	 * UART where the FIFO only triggers the interrupt when its
-	 * threshold is _crossed_, not just met.
-	 */
-	MEC1322_UART_IER |= BIT(1);
-	task_trigger_irq(MEC1322_IRQ_UART);
-}
-
-void uart_tx_stop(void)
-{
-	MEC1322_UART_IER &= ~BIT(1);
-
-	/* Re-allow deep sleep */
-	enable_sleep(SLEEP_MASK_UART);
-}
-
-void uart_tx_flush(void)
-{
-	/* Wait for transmit FIFO empty */
-	while (!(MEC1322_UART_LSR & MEC1322_LSR_TX_EMPTY))
-		;
-}
-
-int uart_tx_ready(void)
-{
-	/*
-	 * We have no indication of free space in transmit FIFO. To work around
-	 * this, we check transmit FIFO empty bit every 16 characters written.
-	 */
-	return tx_fifo_used != 0 || (MEC1322_UART_LSR & MEC1322_LSR_TX_EMPTY);
-}
-
-int uart_tx_in_progress(void)
-{
-	/* return 0: FIFO is empty, 1: FIFO NOT Empty */
-	return !(MEC1322_UART_LSR & MEC1322_LSR_TX_EMPTY);
-}
-
-int uart_rx_available(void)
-{
-	return MEC1322_UART_LSR & BIT(0);
-}
-
-void uart_write_char(char c)
-{
-	/* Wait for space in transmit FIFO. */
-	while (!uart_tx_ready())
-		;
-
-	tx_fifo_used = (tx_fifo_used + 1) % TX_FIFO_SIZE;
-	MEC1322_UART_TB = c;
-}
-
-int uart_read_char(void)
-{
-	return MEC1322_UART_RB;
-}
-
-static void uart_clear_rx_fifo(int channel)
-{
-	MEC1322_UART_FCR = BIT(0) | BIT(1);
-}
-
-/**
- * Interrupt handler for UART
- */
-void uart_ec_interrupt(void)
-{
-	/* Read input FIFO until empty, then fill output FIFO */
-	uart_process_input();
-	uart_process_output();
-}
-DECLARE_IRQ(MEC1322_IRQ_UART, uart_ec_interrupt, 1);
-
-void uart_init(void)
-{
-	/* Set UART to reset on VCC1_RESET instaed of nSIO_RESET */
-	MEC1322_UART_CFG &= ~BIT(1);
-
-	/* Baud rate = 115200. 1.8432MHz clock. Divisor = 1 */
-
-	/* Set CLK_SRC = 0 */
-	MEC1322_UART_CFG &= ~BIT(0);
-
-	/* Set DLAB = 1 */
-	MEC1322_UART_LCR |= BIT(7);
-
-	/* PBRG0/PBRG1 */
-	MEC1322_UART_PBRG0 = 1;
-	MEC1322_UART_PBRG1 = 0;
-
-	/* Set DLAB = 0 */
-	MEC1322_UART_LCR &= ~BIT(7);
-
-	/* Set word length to 8-bit */
-	MEC1322_UART_LCR |= BIT(0) | BIT(1);
-
-	/* Enable FIFO */
-	MEC1322_UART_FCR = BIT(0);
-
-	/* Activate UART */
-	MEC1322_UART_ACT |= BIT(0);
-
-	/*
-	clock_enable_peripheral(CGC_OFFSET_UART, mask,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);*/
-
-	gpio_config_module(MODULE_UART, 1);
-
-	/*
-	 * Enable interrupts for UART0.
-	 */
-	uart_clear_rx_fifo(0);
-	MEC1322_UART_IER |= BIT(0);
-	MEC1322_UART_MCR |= BIT(3);
-	MEC1322_INT_ENABLE(15) |= BIT(0);
-	MEC1322_INT_BLK_EN |= BIT(15);
-	task_enable_irq(MEC1322_IRQ_UART);
-
-	init_done = 1;
-}
-
-#ifdef CONFIG_LOW_POWER_IDLE
-void uart_enter_dsleep(void)
-{
-	/* Disable the UART interrupt. */
-	task_disable_irq(MEC1322_IRQ_UART);  /* NVIC interrupt for UART=13 */
-
-	/*
-	 * Set the UART0 RX pin to be a GPIO-162(fixed pin) interrupt
-	 * with the flags defined in the gpio.inc file.
-	 */
-	gpio_reset(GPIO_UART0_RX);
-
-	/* power-down/de-activate UART0 */
-	MEC1322_UART_ACT &= ~BIT(0);
-
-	/* Clear pending interrupts on GPIO_UART0_RX(GPIO162, girq=8, bit=18) */
-	MEC1322_INT_SOURCE(8) = (1<<18);
-
-	/* Enable GPIO interrupts on the UART0 RX pin. */
-	gpio_enable_interrupt(GPIO_UART0_RX);
-}
-
-
-void uart_exit_dsleep(void)
-{
-	/*
-	 * If the UART0 RX GPIO interrupt has not fired, then no edge has been
-	 * detected. Disable the GPIO interrupt so that switching the pin over
-	 * to a UART pin doesn't inadvertently cause a GPIO edge interrupt.
-	 * Note: we can't disable this interrupt if it has already fired
-	 * because then the IRQ will not run at all.
-	 */
-	if (!(BIT(18) & MEC1322_INT_SOURCE(8))) /* if edge interrupt */
-		gpio_disable_interrupt(GPIO_UART0_RX);
-
-	/* Configure UART0 pins for use in UART peripheral. */
-	gpio_config_module(MODULE_UART, 1);
-
-	/* Clear pending interrupts on UART peripheral and enable interrupts. */
-	uart_clear_rx_fifo(0);
-	task_enable_irq(MEC1322_IRQ_UART); /* NVIC interrupt for UART = 13 */
-
-	/* power-up/activate UART0 */
-	MEC1322_UART_ACT |= BIT(0);
-}
-
-void uart_deepsleep_interrupt(enum gpio_signal signal)
-{
-	/*
-	 * Activity seen on UART RX pin while UART was disabled for deep sleep.
-	 * The console won't see that character because the UART is disabled,
-	 * so we need to inform the clock module of UART activity ourselves.
-	 */
-	clock_refresh_console_in_use();
-
-	/* Disable interrupts on UART0 RX pin to avoid repeated interrupts. */
-	gpio_disable_interrupt(GPIO_UART0_RX);
-}
-#endif /* CONFIG_LOW_POWER_IDLE */
diff --git a/chip/mec1322/util/pack_ec.py b/chip/mec1322/util/pack_ec.py
deleted file mode 100755
index bec27bdcce..0000000000
--- a/chip/mec1322/util/pack_ec.py
+++ /dev/null
@@ -1,244 +0,0 @@
-#!/usr/bin/env python3
-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# A script to pack EC binary into SPI flash image for MEC1322
-# Based on MEC1322_ROM_Doc_Rev0.5.pdf.
-
-import argparse
-import hashlib
-import os
-import struct
-import subprocess
-import tempfile
-
-LOAD_ADDR = 0x100000
-HEADER_SIZE = 0x140
-SPI_CLOCK_LIST = [48, 24, 12, 8]
-SPI_READ_CMD_LIST = [0x3, 0xb, 0x3b]
-
-CRC_TABLE = [0x00, 0x07, 0x0e, 0x09, 0x1c, 0x1b, 0x12, 0x15,
-             0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d]
-
-def Crc8(crc, data):
-  """Update CRC8 value."""
-  for v in data:
-    crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v >> 4)]);
-    crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v & 0xf)]);
-  return crc ^ 0x55
-
-def GetEntryPoint(payload_file):
-  """Read entry point from payload EC image."""
-  with open(payload_file, 'rb') as f:
-    f.seek(4)
-    s = f.read(4)
-  return struct.unpack('<I', s)[0]
-
-def GetPayloadFromOffset(payload_file,offset):
-  """Read payload and pad it to 64-byte aligned."""
-  with open(payload_file, 'rb') as f:
-    f.seek(offset)
-    payload = bytearray(f.read())
-  rem_len = len(payload) % 64
-  if rem_len:
-    payload += b'\0' * (64 - rem_len)
-  return payload
-
-def GetPayload(payload_file):
-  """Read payload and pad it to 64-byte aligned."""
-  return GetPayloadFromOffset(payload_file, 0)
-
-def GetPublicKey(pem_file):
-  """Extract public exponent and modulus from PEM file."""
-  result = subprocess.run(['openssl', 'rsa', '-in', pem_file, '-text',
-                           '-noout'], stdout=subprocess.PIPE, encoding='utf-8')
-  modulus_raw = []
-  in_modulus = False
-  for line in result.stdout.splitlines():
-    if line.startswith('modulus'):
-      in_modulus = True
-    elif not line.startswith(' '):
-      in_modulus = False
-    elif in_modulus:
-      modulus_raw.extend(line.strip().strip(':').split(':'))
-    if line.startswith('publicExponent'):
-      exp = int(line.split(' ')[1], 10)
-  modulus_raw.reverse()
-  modulus = bytearray((int(x, 16) for x in modulus_raw[:256]))
-  return struct.pack('<Q', exp), modulus
-
-def GetSpiClockParameter(args):
-  assert args.spi_clock in SPI_CLOCK_LIST, \
-         "Unsupported SPI clock speed %d MHz" % args.spi_clock
-  return SPI_CLOCK_LIST.index(args.spi_clock)
-
-def GetSpiReadCmdParameter(args):
-  assert args.spi_read_cmd in SPI_READ_CMD_LIST, \
-         "Unsupported SPI read command 0x%x" % args.spi_read_cmd
-  return SPI_READ_CMD_LIST.index(args.spi_read_cmd)
-
-def PadZeroTo(data, size):
-  data.extend(b'\0' * (size - len(data)))
-
-def BuildHeader(args, payload_len, rorofile):
-  # Identifier and header version
-  header = bytearray(b'CSMS\0')
-
-  PadZeroTo(header, 0x6)
-  header.append(GetSpiClockParameter(args))
-  header.append(GetSpiReadCmdParameter(args))
-
-  header.extend(struct.pack('<I', LOAD_ADDR))
-  header.extend(struct.pack('<I', GetEntryPoint(rorofile)))
-  header.append((payload_len >> 6) & 0xff)
-  header.append((payload_len >> 14) & 0xff)
-  PadZeroTo(header, 0x14)
-  header.extend(struct.pack('<I', args.payload_offset))
-
-  exp, modulus = GetPublicKey(args.payload_key)
-  PadZeroTo(header, 0x20)
-  header.extend(exp)
-  PadZeroTo(header, 0x30)
-  header.extend(modulus)
-  PadZeroTo(header, HEADER_SIZE)
-
-  return header
-
-def SignByteArray(data, pem_file):
-  hash_file = tempfile.mkstemp(prefix='pack_ec.')[1]
-  sign_file = tempfile.mkstemp(prefix='pack_ec.')[1]
-  try:
-      with open(hash_file, 'wb') as f:
-        hasher = hashlib.sha256()
-        hasher.update(data)
-        f.write(hasher.digest())
-      subprocess.run(['openssl', 'rsautl', '-sign', '-inkey', pem_file,
-                      '-keyform', 'PEM', '-in', hash_file, '-out', sign_file],
-                     check=True)
-      with open(sign_file, 'rb') as f:
-        signed = f.read()
-        return bytearray(reversed(signed))
-  finally:
-    os.remove(hash_file)
-    os.remove(sign_file)
-
-def BuildTag(args):
-  tag = bytearray([(args.header_loc >> 8) & 0xff,
-                   (args.header_loc >> 16) & 0xff,
-                   (args.header_loc >> 24) & 0xff])
-  if args.chip_select != 0:
-    tag[2] |= 0x80
-  tag.append(Crc8(0, tag))
-  return tag
-
-def PacklfwRoImage(rorw_file, loader_file, image_size):
-  """TODO:Clean up to get rid of Temp file and just use memory
-  to save data"""
-  """Create a temp file with the
-  first image_size bytes from the rorw file and the
-  bytes from the loader_file appended
-  return the filename"""
-  fo=tempfile.NamedTemporaryFile(delete=False) # Need to keep file around
-  with open(loader_file,'rb') as fin1:
-    pro = fin1.read()
-  fo.write(pro)
-  with open(rorw_file, 'rb') as fin:
-    ro = fin.read(image_size)
-  fo.write(ro)
-  fo.close()
-  return fo.name
-
-def parseargs():
-  parser = argparse.ArgumentParser()
-  parser.add_argument("-i", "--input",
-                      help="EC binary to pack, usually ec.bin or ec.RO.flat.",
-                      metavar="EC_BIN", default="ec.bin")
-  parser.add_argument("-o", "--output",
-                      help="Output flash binary file",
-                      metavar="EC_SPI_FLASH", default="ec.packed.bin")
-  parser.add_argument("--header_key",
-                      help="PEM key file for signing header",
-                      default="rsakey_sign_header.pem")
-  parser.add_argument("--payload_key",
-                      help="PEM key file for signing payload",
-                      default="rsakey_sign_payload.pem")
-  parser.add_argument("--loader_file",
-                      help="EC loader binary",
-                      default="ecloader.bin")
-  parser.add_argument("-s", "--spi_size", type=int,
-                      help="Size of the SPI flash in MB",
-                      default=4)
-  parser.add_argument("-l", "--header_loc", type=int,
-                      help="Location of header in SPI flash",
-                      default=0x170000)
-  parser.add_argument("-p", "--payload_offset", type=int,
-                      help="The offset of payload from the header",
-                      default=0x240)
-  parser.add_argument("-r", "--rwpayload_loc", type=int,
-                      help="The offset of payload from the header",
-                      default=0x190000)
-  parser.add_argument("-z", "--romstart", type=int,
-                      help="The first location to output of the rom",
-                      default=0)
-  parser.add_argument("-c", "--chip_select", type=int,
-                      help="Chip select signal to use, either 0 or 1.",
-                      default=0)
-  parser.add_argument("--spi_clock", type=int,
-                      help="SPI clock speed. 8, 12, 24, or 48 MHz.",
-                      default=24)
-  parser.add_argument("--spi_read_cmd", type=int,
-                      help="SPI read command. 0x3, 0xB, or 0x3B.",
-                      default=0xb)
-  parser.add_argument("--image_size", type=int,
-                      help="Size of a single image.",
-                      default=(96 * 1024))
-  return parser.parse_args()
-
-def main():
-  args = parseargs()
-
-  spi_size = args.spi_size * 1024
-  args.header_loc = spi_size - (128 * 1024)
-  args.rwpayload_loc = spi_size - (256 * 1024)
-  args.romstart = spi_size - (256 * 1024)
-
-  spi_list = []
-
-  rorofile=PacklfwRoImage(args.input, args.loader_file, args.image_size)
-  payload = GetPayload(rorofile)
-  payload_len = len(payload)
-  payload_signature = SignByteArray(payload, args.payload_key)
-  header = BuildHeader(args, payload_len, rorofile)
-  header_signature = SignByteArray(header, args.header_key)
-  tag = BuildTag(args)
-  # truncate the RW to 128k
-  payloadrw = GetPayloadFromOffset(args.input,args.image_size)[:128*1024]
-  os.remove(rorofile)           # clean up the temp file
-
-  spi_list.append((args.header_loc, header, "header"))
-  spi_list.append((args.header_loc + HEADER_SIZE, header_signature, "header_signature"))
-  spi_list.append((args.header_loc + args.payload_offset, payload, "payload"))
-  spi_list.append((args.header_loc + args.payload_offset + payload_len,
-                   payload_signature, "payload_signature"))
-  spi_list.append((spi_size - 256, tag, "tag"))
-  spi_list.append((args.rwpayload_loc, payloadrw, "payloadrw"))
-
-
-  spi_list = sorted(spi_list)
-
-  with open(args.output, 'wb') as f:
-    addr = args.romstart
-    for s in spi_list:
-      assert addr <= s[0]
-      if addr < s[0]:
-        f.write(b'\xff' * (s[0] - addr))
-        addr = s[0]
-      f.write(s[1])
-      addr += len(s[1])
-    if addr < spi_size:
-      f.write(b'\xff' * (spi_size - addr))
-
-if __name__ == '__main__':
-  main()
diff --git a/chip/mec1322/util/rsakey_sign_header.pem b/chip/mec1322/util/rsakey_sign_header.pem
deleted file mode 100644
index 37799ebbec..0000000000
--- a/chip/mec1322/util/rsakey_sign_header.pem
+++ /dev/null
@@ -1,28 +0,0 @@
------BEGIN PRIVATE KEY-----
-MIIEvwIBADANBgkqhkiG9w0BAQEFAASCBKkwggSlAgEAAoIBAQCd0knJ+sVzkO40
-g7VguqpqrmwqgYPfgq3m7GHGitWgxjM/JDpKaOvq4G9O+yYUD/75V5GZJkRY0iE8
-MJCCvSkyoFHcCP0jvma9G/c13wXfLPGUunrJnV+Wzwy5+S1MXdax532gK9qeUmOB
-HpIttkFRl3qhVHu9to2dbsx1S/AIA0GIPAINkcZxfRCAcheIoqK/oMqse+EDS9Zm
-6frha9oS1+iRlqMPYKrOgWTKnkY3H/4M/HFj90hVzxun3qQj0mo3EdYoSrbCnyjG
-JNjnuCdSEODmG5+FCTVWCfl/AolYmOWjMfCnfX7/HlfhOY+fOR91FKrgOjWHHf3a
-0FhdUZDNAgMBAAECggEBAJKea6j2jXu42GP3PIk5wdrMYnb2zeHXEOJpFskR8Dem
-CrQNXw4D/bC+gwo4Lv8SgUl6PiyurW5rAS9e2tJrFBwRbxthSnNrjxz/HyJwKI9W
-vLT0reAikUyU3Hjl8lxxDWVH76DfPQI6/nBVS26mVHaNqQK6bx8nutbYuZ/7RWra
-zatdjrl29D0E/xTva0S4AUPI7DmflwS6YbfVlTsyhnwphaEwD7eCDhD9h4nGQG8z
-0WKDN2X1F7CmjrK9fy7SCHO9SKc3WNSjp2Dc0ImF2k72Mfw5jtOs81lczktztPy0
-gv4x6Tg0ws4Et9eI6Ub80tAZ+wQ5Vj+wzExMOp4K5KECgYEA0jz5IsRmie6y/WRG
-6dI98nnyLoISIQue8xOA5J/OUyYfHn9CgJvGslRVg2mmSQ9GPkaMIN0dADvB6Tsh
-XelAZZjnAo8pSyahz3OdcdgP6xksMjtKReXiLqu0ntfQS42nQDYNvRd2/clrYYRN
-SlijT53QMqI4DSMz+0rLqUwvRskCgYEAwCyEEJ1Z/CI2ONN1tIEnJSuzZRYxlwNL
-mVXx03ZSVi+L2MOMJjiCoeUZ/MVSacW+Elg6aU3U1GdOhNfQaPZJNqISACtm314Y
-Xi9bMXegyQp3uBRnEah82ejm8hloOAOKZNgbqgt9o6FDrsccw3udIgzsgPY4koUK
-1fNrDPJ5x+UCgYBwlEH8whr+hZnHYqkukGynqXFsQi6fD3AATlNZGdIMaH+FfzQH
-VmNiHxLjmfF3cfx1YKWs+3qKI3XFBOrrNPpM7UHW9v5vxbIkOo725XIwvHwUMfel
-0mH6B+ximsJpkuMa2VcmCKipYfBkecpBo5FgEuvoEUHelxlA2V6Ru8AdMQKBgQC/
-uanoiZQFIHzIJPABrfjH9Nl9uK6w4vDBgiVJu3pZ0gXLtQxV9Xse2dsbfCHEtSv0
-UWG1PZlgb9C+aDHdBhn1D6y1zpdLsizNiqGIsLkQ2gim9nP+AgLNxLbkQsTfXWjt
-Q04WUHCAl5tW+/+OZ/1Uw2ARKZU3WNR+r+PVfvRQoQKBgQCjksWLe3Zx2yxnUenz
-vaY09UTt42rawbUkm+xpNzOt7K1TudRODe444XG9fFgkNa5HPiAENoZ91Jv223x8
-Fi2SjfGA6/r/J1ash4cDcJLogTEP27YyJyhwXZFKtjfFeD3e2hvcMFMDG4EBHHXd
-Bv/r6+6E+f30Y4bN3ZgK/rN6Tg==
------END PRIVATE KEY-----
diff --git a/chip/mec1322/util/rsakey_sign_payload.pem b/chip/mec1322/util/rsakey_sign_payload.pem
deleted file mode 100644
index 6845097749..0000000000
--- a/chip/mec1322/util/rsakey_sign_payload.pem
+++ /dev/null
@@ -1,28 +0,0 @@
------BEGIN PRIVATE KEY-----
-MIIEvQIBADANBgkqhkiG9w0BAQEFAASCBKcwggSjAgEAAoIBAQDQaeNJ6+a/KXhs
-/0Xa2coG+4d+pc+4qs4O/6caxAtzr1YP155C4QxqfZw0DETreK7K/kgSgOJ6Q1gW
-Yo88Fb4foxVYJbV2Bb+mdNlaHP/o6TrvBmqdsIjP5u1FwtmjquaewL2E3T4rHCXl
-QgM7AQXAFzKt2HeaMeHvC2t+x/AganhfztOpqhGTL6lHiLC55SPNkWCb3GokotbL
-Ul7q+wLSTpKS0vNuigjGVBVuV7YrwWhehOoLuV5FDMXHlMTemYH6+V5j78ZtSrXm
-0RmKAKXoO+HbKbgALICUw5kzxXLSAoHx2rXLlou9I00olxsWir1lokxaWa1La3wA
-pr214pxXAgMBAAECggEAdsXxrz4OeaEDrXJpeAioNwR/unB6ie5lkmyl6f4R3LLu
-5AZofgrNTZ8aNxtK57sWOj9iCZGEAFOCzvcKVB68BEGnt11+Ja2vBAkRmWZvfWf1
-myTX+9gQkBM144zhBYIu/ggvuZlwhZb8DcRqHOU/RrKxwhtcRfbpoJasg0skkQO0
-bU2hwSu4kM+T2diyXp4V1PR4vrxZPNQ+B8sWxWKJs58+3NdWswwe9NcFQla0QTFz
-7MIlMJNlJgTXjSYC8TjDlBlevwE5HoikpfSSvFr4uouyfpfWBxNFd8Tm/yFSTUqY
-XO3oyU/NLK+BN7Sxj6Cs1Fx65yhMCmsqGQqCNOz2OQKBgQD4gIF6vVduyKfPV3EE
-4lhFktlFRXeR+z9LXpGth3vwNN0XpPql1jr8hYPQqpSKefZRF5r8hLjt2ZaLDbnb
-iVYwHxbXRuF5P6qsaSy1uVYG4og5LV5ddSBzf+/MhDInQk/O5tdvOrgQfcJzRJRg
-MSx5uzs66r8/AFKCVTB/ptNgzQKBgQDWs7qqaHNHGRRfegRhwkkDvhRAMQKWsgL7
-kTWw/qW+b8mRYhCC4JvbU+OeFkf5kejGpFgDuvB4eH+rsPRVU8jSWZXrMKjGdZN1
-T6fFa5vz1VsRNhiVU3F2jfXTY5t7qQ18jEoMQxGxdGJy52Py+3N34ZWNS4cifLNS
-rYjZnQmhswKBgD3rd1foGgMmyHmnpie7ZpdfcfgKyTJ80larZ80/dyhxY63ik/oC
-mYwWkLPL7Vtb7H5kTWAiihnqH9LiRq9nVyyCcqSNqt0VeiefxV46oi7w/1SP83WC
-G+XruQrS3dRed5hseL3kebzSOUOTkQ0u85AZkTarC6BdKjIDnCQSo5T5AoGAKNep
-087o1waTVJJOkRY3c4nOKmPoXShh3t9BunjGqNJ1Ir3n7C20GGX9783HRVeXU2ph
-/9uo8RHjH5Ma97xngHRgS4xHHvGw6mkLvkd5NEpK95w10vo7pFTfBaZ2JnEDSsUZ
-NPnxPLOqIreX0No6nfyAyY8rlsjoB/tRBCyWb3cCgYEAgzJCllzahDvgCbmjI9Km
-h7mUVc5U2fQR5B/WRa5iTSlQd+O4TXna7ZCxKDyYlesSBAiKanX0669Iri6cu4S6
-gMc7MJmm3VrnZGXoukSv3Zyot+hkaFrZTrXAIQiuYDK6YC5OK7kqM+DqtJOWUsfg
-itdiqPKeYtViDQkxqJ1nkSw=
------END PRIVATE KEY-----
diff --git a/chip/mec1322/watchdog.c b/chip/mec1322/watchdog.c
deleted file mode 100644
index ad93fb1240..0000000000
--- a/chip/mec1322/watchdog.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Watchdog driver */
-
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "watchdog.h"
-
-void watchdog_reload(void)
-{
-	MEC1322_WDG_KICK = 1;
-
-#ifdef CONFIG_WATCHDOG_HELP
-	/* Reload the auxiliary timer */
-	MEC1322_TMR16_CTL(0) &= ~BIT(5);
-	MEC1322_TMR16_CNT(0) = CONFIG_AUX_TIMER_PERIOD_MS;
-	MEC1322_TMR16_CTL(0) |= BIT(5);
-#endif
-}
-DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT);
-
-int watchdog_init(void)
-{
-#ifdef CONFIG_WATCHDOG_HELP
-	uint32_t val;
-
-	/*
-	 * Watchdog does not warn us before expiring. Let's use a 16-bit
-	 * timer as an auxiliary timer.
-	 */
-
-	/* Stop the auxiliary timer if it's running */
-	MEC1322_TMR16_CTL(0) &= ~BIT(5);
-
-	/* Enable auxiliary timer */
-	MEC1322_TMR16_CTL(0) |= BIT(0);
-
-	val = MEC1322_TMR16_CTL(0);
-
-	/* Pre-scale = 48000 -> 1kHz -> Period = 1ms */
-	val = (val & 0xffff) | (47999 << 16);
-
-	/* No auto restart */
-	val &= ~BIT(3);
-
-	/* Count down */
-	val &= ~BIT(2);
-
-	MEC1322_TMR16_CTL(0) = val;
-
-	/* Enable interrupt from auxiliary timer */
-	MEC1322_TMR16_IEN(0) |= 1;
-	task_enable_irq(MEC1322_IRQ_TIMER16_0);
-	MEC1322_INT_ENABLE(23) |= BIT(0);
-	MEC1322_INT_BLK_EN |= BIT(23);
-
-	/* Load and start the auxiliary timer */
-	MEC1322_TMR16_CNT(0) = CONFIG_AUX_TIMER_PERIOD_MS;
-	MEC1322_TMR16_CNT(0) |= BIT(5);
-#endif
-
-	/* Set timeout. It takes 1007us to decrement WDG_CNT by 1. */
-	MEC1322_WDG_LOAD = CONFIG_WATCHDOG_PERIOD_MS * 1000 / 1007;
-
-	/* Start watchdog */
-	MEC1322_WDG_CTL |= 1;
-
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_WATCHDOG_HELP
-void __keep watchdog_check(uint32_t excep_lr, uint32_t excep_sp)
-{
-	/* Clear status */
-	MEC1322_TMR16_STS(0) |= 1;
-
-	watchdog_trace(excep_lr, excep_sp);
-}
-
-void IRQ_HANDLER(MEC1322_IRQ_TIMER16_0)(void) __attribute__((naked));
-void IRQ_HANDLER(MEC1322_IRQ_TIMER16_0)(void)
-{
-	/* Naked call so we can extract raw LR and SP */
-	asm volatile("mov r0, lr\n"
-		     "mov r1, sp\n"
-		     /* Must push registers in pairs to keep 64-bit aligned
-		      * stack for ARM EABI.  This also conveninently saves
-		      * R0=LR so we can pass it to task_resched_if_needed. */
-		     "push {r0, lr}\n"
-		     "bl watchdog_check\n"
-		     "pop {r0, lr}\n"
-		     "b task_resched_if_needed\n");
-}
-const struct irq_priority __keep IRQ_PRIORITY(MEC1322_IRQ_TIMER16_0)
-	__attribute__((section(".rodata.irqprio")))
-		= {MEC1322_IRQ_TIMER16_0, 0}; /* put the watchdog at the
-						 highest priority */
-#endif
diff --git a/chip/mt8192_scp/build.mk b/chip/mt8192_scp/build.mk
deleted file mode 100644
index 0925ff2245..0000000000
--- a/chip/mt8192_scp/build.mk
+++ /dev/null
@@ -1,27 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# SCP specific files build
-#
-
-CORE:=riscv-rv32i
-
-# Required chip modules
-chip-y+=clock.o
-chip-y+=gpio.o
-chip-y+=intc.o
-chip-y+=memmap.o
-chip-y+=system.o
-chip-y+=uart.o
-
-ifeq ($(CONFIG_IPI),y)
-$(out)/RW/chip/$(CHIP)/ipi_table.o: $(out)/ipi_table_gen.inc
-endif
-
-# Optional chip modules
-chip-$(CONFIG_COMMON_TIMER)+=hrtimer.o
-chip-$(CONFIG_IPI)+=ipi.o ipi_table.o
-chip-$(CONFIG_WATCHDOG)+=watchdog.o
-chip-$(HAS_TASK_HOSTCMD)+=hostcmd.o
diff --git a/chip/mt8192_scp/clock.c b/chip/mt8192_scp/clock.c
deleted file mode 100644
index ee7970a71a..0000000000
--- a/chip/mt8192_scp/clock.c
+++ /dev/null
@@ -1,343 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks, PLL and power settings */
-
-#include <assert.h>
-#include <string.h>
-
-#include "clock_chip.h"
-#include "clock.h"
-#include "console.h"
-#include "csr.h"
-#include "registers.h"
-#include "timer.h"
-
-#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ##args)
-
-static struct opp_ulposc_cfg {
-	uint32_t osc;
-	uint32_t div;
-	uint32_t fband;
-	uint32_t mod;
-	uint32_t cali;
-	uint32_t target_mhz;
-} opp[] = {
-	{
-		.osc = 1, .target_mhz = 196, .div = 20, .fband = 10, .mod = 3,
-		.cali = 64,
-	},
-	{
-		.osc = 0, .target_mhz = 260, .div = 14, .fband = 2, .mod = 0,
-		.cali = 64,
-	},
-	{
-		.osc = 1, .target_mhz = 280, .div = 20, .fband = 2, .mod = 0,
-		.cali = 64,
-	},
-	{
-		.osc = 1, .target_mhz = 360, .div = 20, .fband = 10, .mod = 0,
-		.cali = 64,
-	},
-};
-
-static inline void clock_busy_udelay(int usec)
-{
-	/*
-	 * Delaying by busy-looping, for place that can't use udelay because of
-	 * the clock not configured yet. The value 28 is chosen approximately
-	 * from experiment.
-	 *
-	 * `volatile' in order to avoid compiler to optimize the function out
-	 * (otherwise, the function will be eliminated).
-	 */
-	volatile int i = usec * 28;
-
-	while (--i)
-		;
-}
-
-static void clock_ulposc_config_default(struct opp_ulposc_cfg *opp)
-{
-	unsigned int val = 0;
-
-	/* set div */
-	val |= opp->div << OSC_DIV_SHIFT;
-	/* set F-band; I-band = 82 */
-	val |= (opp->fband << OSC_FBAND_SHIFT) | (82 << OSC_IBAND_SHIFT);
-	/* set calibration */
-	val |= opp->cali;
-	/* set control register 0 */
-	AP_ULPOSC_CON0(opp->osc) = val;
-
-	/* set mod */
-	val = opp->mod << OSC_MOD_SHIFT;
-	/* rsv2 = 0, rsv1 = 41, cali_32k = 0 */
-	val |= 41 << OSC_RSV1_SHIFT;
-	/* set control register 1 */
-	AP_ULPOSC_CON1(opp->osc) = val;
-
-	/* bias = 64 */
-	AP_ULPOSC_CON2(opp->osc) = 64;
-}
-
-static void clock_ulposc_config_cali(struct opp_ulposc_cfg *opp,
-				     uint32_t cali_val)
-{
-	uint32_t val;
-
-	val = AP_ULPOSC_CON0(opp->osc);
-	val &= ~OSC_CALI_MASK;
-	val |= cali_val;
-	AP_ULPOSC_CON0(opp->osc) = val;
-
-	clock_busy_udelay(50);
-}
-
-static uint32_t clock_ulposc_measure_freq(uint32_t osc)
-{
-	uint32_t result = 0;
-	int cnt;
-
-	/* before select meter clock input, bit[1:0] = b00 */
-	AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_MODE_MASK) |
-			 DBG_MODE_SET_CLOCK;
-
-	/* select source, bit[21:16] = clk_src */
-	AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_BIST_SOURCE_MASK) |
-			 (osc == 0 ? DBG_BIST_SOURCE_ULPOSC1 :
-				     DBG_BIST_SOURCE_ULPOSC2);
-
-	/* set meter divisor to 1, bit[31:24] = b00000000 */
-	AP_CLK_MISC_CFG_0 = (AP_CLK_MISC_CFG_0 & ~MISC_METER_DIVISOR_MASK) |
-			    MISC_METER_DIV_1;
-
-	/* enable frequency meter, without start */
-	AP_SCP_CFG_0 |= CFG_FREQ_METER_ENABLE;
-
-	/* trigger frequency meter start */
-	AP_SCP_CFG_0 |= CFG_FREQ_METER_RUN;
-
-	/*
-	 * Frequency meter counts cycles in 1 / (26 * 1024) second period.
-	 *   freq_in_hz = freq_counter * 26 * 1024
-	 *
-	 * The hardware takes 38us to count cycles. Delay up to 100us,
-	 * as clock_busy_udelay may not be accurate when sysclk is not 26Mhz
-	 * (e.g. when recalibrating/measuring after boot).
-	 */
-	for (cnt = 100; cnt > 0; --cnt) {
-		clock_busy_udelay(1);
-		if (!(AP_SCP_CFG_0 & CFG_FREQ_METER_RUN)) {
-			result = CFG_FREQ_COUNTER(AP_SCP_CFG_1);
-			break;
-		}
-	}
-
-	/* disable freq meter */
-	AP_SCP_CFG_0 &= ~CFG_FREQ_METER_ENABLE;
-
-	return result;
-}
-
-#define CAL_MIS_RATE	40
-static int clock_ulposc_is_calibrated(struct opp_ulposc_cfg *opp)
-{
-	uint32_t curr, target;
-
-	curr = clock_ulposc_measure_freq(opp->osc);
-	target = opp->target_mhz * 1024 / 26;
-
-	/* check if calibrated value is in the range of target value +- 4% */
-	if (curr > (target * (1000 - CAL_MIS_RATE) / 1000) &&
-	    curr < (target * (1000 + CAL_MIS_RATE) / 1000))
-		return 1;
-	else
-		return 0;
-}
-
-static uint32_t clock_ulposc_process_cali(struct opp_ulposc_cfg *opp)
-{
-	uint32_t current_val = 0;
-	uint32_t target_val = opp->target_mhz * 1024 / 26;
-	uint32_t middle, min = 0, max = OSC_CALI_MASK;
-	uint32_t diff_by_min, diff_by_max, cal_result;
-
-	do {
-		middle = (min + max) / 2;
-		if (middle == min)
-			break;
-
-		clock_ulposc_config_cali(opp, middle);
-		current_val = clock_ulposc_measure_freq(opp->osc);
-
-		if (current_val > target_val)
-			max = middle;
-		else
-			min = middle;
-	} while (min <= max);
-
-	clock_ulposc_config_cali(opp, min);
-	current_val = clock_ulposc_measure_freq(opp->osc);
-	if (current_val > target_val)
-		diff_by_min = current_val - target_val;
-	else
-		diff_by_min = target_val - current_val;
-
-	clock_ulposc_config_cali(opp, max);
-	current_val = clock_ulposc_measure_freq(opp->osc);
-	if (current_val > target_val)
-		diff_by_max = current_val - target_val;
-	else
-		diff_by_max = target_val - current_val;
-
-	if (diff_by_min < diff_by_max)
-		cal_result = min;
-	else
-		cal_result = max;
-
-	clock_ulposc_config_cali(opp, cal_result);
-	if (!clock_ulposc_is_calibrated(opp))
-		assert(0);
-
-	return cal_result;
-}
-
-static void clock_high_enable(int osc)
-{
-	/* enable high speed clock */
-	SCP_CLK_ENABLE |= CLK_HIGH_EN;
-
-	switch (osc) {
-	case 0:
-		/* after 150us, enable ULPOSC */
-		clock_busy_udelay(150);
-		SCP_CLK_ENABLE |= CLK_HIGH_CG;
-		break;
-	case 1:
-		/* turn off ULPOSC2 high-core-disable switch */
-		SCP_CLK_ON_CTRL &= ~HIGH_CORE_DIS_SUB;
-		/* after 150us, turn on ULPOSC2 high core clock gate */
-		clock_busy_udelay(150);
-		SCP_CLK_HIGH_CORE_CG |= HIGH_CORE_CG;
-		clock_busy_udelay(50);
-		break;
-	default:
-		break;
-	}
-}
-
-static void clock_high_disable(int osc)
-{
-	switch (osc) {
-	case 0:
-		SCP_CLK_ENABLE &= ~CLK_HIGH_CG;
-		clock_busy_udelay(50);
-		SCP_CLK_ENABLE &= ~CLK_HIGH_EN;
-		clock_busy_udelay(50);
-		break;
-	case 1:
-		SCP_CLK_HIGH_CORE_CG &= ~HIGH_CORE_CG;
-		clock_busy_udelay(50);
-		SCP_CLK_ON_CTRL |= HIGH_CORE_DIS_SUB;
-		clock_busy_udelay(50);
-		break;
-	default:
-		break;
-	}
-}
-
-static void clock_calibrate_ulposc(struct opp_ulposc_cfg *opp)
-{
-	/*
-	 * ULPOSC1(osc=0) is already
-	 * - calibrated
-	 * - enabled in coreboot
-	 * - used by pmic wrapper
-	 */
-	if (opp->osc != 0) {
-		clock_high_disable(opp->osc);
-		clock_ulposc_config_default(opp);
-		clock_high_enable(opp->osc);
-	}
-
-	/* Calibrate only if it is not accurate enough. */
-	if (!clock_ulposc_is_calibrated(opp))
-		opp->cali = clock_ulposc_process_cali(opp);
-
-#ifdef DEBUG
-	CPRINTF("osc:%u, target=%uMHz, cal:%u\n",
-		opp->osc, opp->target_mhz, opp->cali);
-#endif
-}
-
-void clock_select_clock(enum scp_clock_source src)
-{
-	/*
-	 * DIV2 divider takes precedence over clock selection to prevent
-	 * over-clocking.
-	 */
-	if (src == SCP_CLK_ULPOSC1)
-		SCP_CLK_DIV_SEL = CLK_DIV_SEL2;
-
-	SCP_CLK_SW_SEL = src;
-
-	if (src != SCP_CLK_ULPOSC1)
-		SCP_CLK_DIV_SEL = CLK_DIV_SEL1;
-}
-
-void clock_init(void)
-{
-	int i;
-
-	/* select default 26M system clock */
-	clock_select_clock(SCP_CLK_26M);
-
-	/* set VREQ to HW mode */
-	SCP_CPU_VREQ_CTRL = VREQ_SEL | VREQ_DVFS_SEL;
-	SCP_CLK_CTRL_GENERAL_CTRL &= ~VREQ_PMIC_WRAP_SEL;
-	SCP_SEC_CTRL &= ~VREQ_SECURE_DIS;
-
-	/* set DDREN to auto mode */
-	SCP_SYS_CTRL |= AUTO_DDREN;
-
-	/* set settle time */
-	SCP_CLK_SYS_VAL =
-		(SCP_CLK_SYS_VAL & ~CLK_SYS_VAL_MASK) | CLK_SYS_VAL_VAL(1);
-	SCP_CLK_HIGH_VAL =
-		(SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) | CLK_HIGH_VAL_VAL(1);
-	SCP_SLEEP_CTRL =
-		(SCP_SLEEP_CTRL & ~VREQ_COUNT_MASK) | VREQ_COUNT_VAL(1);
-
-	/* turn off ULPOSC2 */
-	SCP_CLK_ON_CTRL |= HIGH_CORE_DIS_SUB;
-
-	/* calibrate ULPOSC */
-	for (i = 0; i < ARRAY_SIZE(opp); ++i)
-		clock_calibrate_ulposc(&opp[i]);
-
-	/* select ULPOSC2 high speed CPU clock */
-	clock_select_clock(SCP_CLK_ULPOSC2);
-
-	/* enable default clock gate */
-	SCP_SET_CLK_CG |= CG_DMA_CH3 | CG_DMA_CH2 | CG_DMA_CH1 | CG_DMA_CH0 |
-		CG_I2C_MCLK | CG_MAD_MCLK | CG_AP2P_MCLK;
-}
-
-#ifdef DEBUG
-int command_ulposc(int argc, char *argv[])
-{
-	int i;
-
-	for (i = 0; i <= 1; ++i)
-		ccprintf("ULPOSC%u frequency: %u kHz\n",
-			 i + 1,
-			 clock_ulposc_measure_freq(i) * 26 * 1000 / 1024);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(ulposc, command_ulposc, "[ulposc]",
-			"Measure ULPOSC frequency");
-#endif
diff --git a/chip/mt8192_scp/clock_chip.h b/chip/mt8192_scp/clock_chip.h
deleted file mode 100644
index ee1c22be92..0000000000
--- a/chip/mt8192_scp/clock_chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks, PLL and power settings */
-
-#ifndef __CROS_EC_CLOCK_CHIP_H
-#define __CROS_EC_CLOCK_CHIP_H
-
-#include "registers.h"
-
-enum scp_clock_source {
-	SCP_CLK_26M = CLK_SW_SEL_26M,
-	SCP_CLK_32K = CLK_SW_SEL_32K,
-	SCP_CLK_ULPOSC2 = CLK_SW_SEL_ULPOSC2,
-	SCP_CLK_ULPOSC1 = CLK_SW_SEL_ULPOSC1,
-};
-
-/* Switches to use 'src' clock */
-void clock_select_clock(enum scp_clock_source src);
-
-#endif /* __CROS_EC_CLOCK_CHIP_H */
diff --git a/chip/mt8192_scp/config_chip.h b/chip/mt8192_scp/config_chip.h
deleted file mode 100644
index 2a4c5f7925..0000000000
--- a/chip/mt8192_scp/config_chip.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_CHIP_H
-#define __CROS_EC_CONFIG_CHIP_H
-
-#include "core/riscv-rv32i/config_core.h"
-
-/* Interval between HOOK_TICK notifications */
-#define HOOK_TICK_INTERVAL_MS 500
-#define HOOK_TICK_INTERVAL    (HOOK_TICK_INTERVAL_MS * MSEC)
-
-/* RW only, no flash */
-#undef  CONFIG_FW_INCLUDE_RO
-#define CONFIG_RO_MEM_OFF 0
-#define CONFIG_RO_SIZE 0
-#define CONFIG_RW_MEM_OFF 0
-#define CONFIG_RW_SIZE 0x40000 /* 256KB */
-#define CONFIG_EC_WRITABLE_STORAGE_OFF 0
-#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
-#define CONFIG_RO_STORAGE_OFF 0
-#define CONFIG_RW_STORAGE_OFF 0
-#define CONFIG_PROGRAM_MEMORY_BASE 0
-#define CONFIG_MAPPED_STORAGE_BASE 0
-
-/* Unsupported features/commands */
-#undef CONFIG_CMD_FLASHINFO
-#undef CONFIG_CMD_POWER_AP
-#undef CONFIG_FLASH
-#undef CONFIG_FLASH_PHYSICAL
-#undef CONFIG_FMAP
-#undef CONFIG_HIBERNATE
-#undef CONFIG_LID_SWITCH
-
-/* Task stack size */
-#define CONFIG_STACK_SIZE 1024
-#define IDLE_TASK_STACK_SIZE 640
-#define SMALLER_TASK_STACK_SIZE 384
-#define TASK_STACK_SIZE 488
-#define LARGER_TASK_STACK_SIZE 640
-#define VENTI_TASK_STACK_SIZE 768
-#define ULTRA_TASK_STACK_SIZE 1056
-#define TRENTA_TASK_STACK_SIZE 1184
-
-/* TODO: need to confirm, placeholder */
-#define GPIO_PIN(num) ((num) / 32), ((num) % 32)
-#define GPIO_PIN_MASK(p, m) .port = (p), .mask = (m)
-#undef CONFIG_TASK_PROFILING
-/* TODO: not yet supported */
-#undef CONFIG_MPU
-/* TODO: core/riscv-rv32i pollution */
-#define __ram_code
-
-#endif /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/chip/mt8192_scp/csr.h b/chip/mt8192_scp/csr.h
deleted file mode 100644
index e9e95f3ffa..0000000000
--- a/chip/mt8192_scp/csr.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Control and status register */
-
-/* TODO: move to core/riscv-rv32i? */
-
-#ifndef __CROS_EC_CSR_H
-#define __CROS_EC_CSR_H
-
-#include "common.h"
-
-static inline uint32_t read_csr(uint32_t reg)
-{
-	uint32_t val;
-
-	asm volatile("csrr %0, %1" : "=r"(val) : "i"(reg));
-	return val;
-}
-
-static inline void write_csr(uint32_t reg, uint32_t val)
-{
-	asm volatile ("csrw %0, %1" :: "i"(reg), "r"(val));
-}
-
-static inline uint32_t set_csr(uint32_t reg, uint32_t bit)
-{
-	uint32_t val;
-
-	asm volatile ("csrrs %0, %1, %2" : "=r"(val) : "i"(reg), "r"(bit));
-	return val;
-}
-
-static inline uint32_t clear_csr(uint32_t reg, uint32_t bit)
-{
-	uint32_t val;
-
-	asm volatile ("csrrc %0, %1, %2" : "=r"(val) : "i"(reg), "r"(bit));
-	return val;
-}
-
-/* VIC */
-#define CSR_VIC_MICAUSE		(0x5c0)
-#define CSR_VIC_MIEMS		(0x5c2)
-#define CSR_VIC_MIPEND_G0	(0x5d0)
-#define CSR_VIC_MIMASK_G0	(0x5d8)
-#define CSR_VIC_MIWAKEUP_G0	(0x5e0)
-#define CSR_VIC_MILSEL_G0	(0x5e8)
-#define CSR_VIC_MIEMASK_G0	(0x5f0)
-
-/* centralized control enable */
-#define CSR_MCTREN		(0x7c0)
-/* I$, D$, ITCM, DTCM, BTB, RAS, VIC, CG, mpu */
-#define   CSR_MCTREN_ICACHE	BIT(0)
-#define   CSR_MCTREN_DCACHE	BIT(1)
-#define   CSR_MCTREN_ITCM	BIT(2)
-#define   CSR_MCTREN_DTCM	BIT(3)
-#define   CSR_MCTREN_BTB	BIT(4)
-#define   CSR_MCTREN_RAS	BIT(5)
-#define   CSR_MCTREN_VIC	BIT(6)
-#define   CSR_MCTREN_CG		BIT(7)
-#define   CSR_MCTREN_MPU	BIT(8)
-
-#endif /* __CROS_EC_CSR_H */
diff --git a/chip/mt8192_scp/gpio.c b/chip/mt8192_scp/gpio.c
deleted file mode 100644
index 0ca3e3ac25..0000000000
--- a/chip/mt8192_scp/gpio.c
+++ /dev/null
@@ -1,21 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GPIO module */
-
-#include "gpio.h"
-
-void gpio_pre_init(void)
-{
-}
-
-test_mockable int gpio_get_level(enum gpio_signal signal)
-{
-	return 0;
-}
-
-void gpio_set_level(enum gpio_signal signal, int value)
-{
-}
diff --git a/chip/mt8192_scp/hrtimer.c b/chip/mt8192_scp/hrtimer.c
deleted file mode 100644
index a3f0ed3298..0000000000
--- a/chip/mt8192_scp/hrtimer.c
+++ /dev/null
@@ -1,221 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * High-res hardware timer
- *
- * SCP hardware 32bit count down timer can be configured to source clock from
- * 32KHz, 26MHz, BCLK or PCLK. This implementation selects BCLK (ULPOSC1/8) as a
- * source, countdown mode and converts to micro second value matching common
- * timer.
- */
-
-#include "common.h"
-#include "hwtimer.h"
-#include "registers.h"
-#include "task.h"
-
-#define TIMER_SYSTEM 5
-#define TIMER_EVENT 3
-#define TIMER_CLOCK_MHZ 26
-#define OVERFLOW_TICKS (TIMER_CLOCK_MHZ * 0x100000000 - 1)
-
-/* High 32-bit for system timer. */
-static uint8_t sys_high;
-/* High 32-bit for event timer. */
-static uint8_t event_high;
-
-static void timer_enable(int n)
-{
-	/* cannot be changed when timer is enabled */
-	SCP_CORE0_TIMER_IRQ_CTRL(n) |= TIMER_IRQ_EN;
-	SCP_CORE0_TIMER_EN(n) |= TIMER_EN;
-}
-
-static void timer_disable(int n)
-{
-	SCP_CORE0_TIMER_EN(n) &= ~TIMER_EN;
-	/* cannot be changed when timer is enabled */
-	SCP_CORE0_TIMER_IRQ_CTRL(n) &= ~TIMER_IRQ_EN;
-}
-
-static int timer_is_irq(int n)
-{
-	return SCP_CORE0_TIMER_IRQ_CTRL(n) & TIMER_IRQ_STATUS;
-}
-
-static void timer_ack_irq(int n)
-{
-	SCP_CORE0_TIMER_IRQ_CTRL(n) |= TIMER_IRQ_CLR;
-}
-
-static void timer_set_reset_value(int n, uint32_t reset_value)
-{
-	/* cannot be changed when timer is enabled */
-	SCP_CORE0_TIMER_RST_VAL(n) = reset_value;
-}
-
-static void timer_set_clock(int n, uint32_t clock_source)
-{
-	SCP_CORE0_TIMER_EN(n) =
-		(SCP_CORE0_TIMER_EN(n) & ~TIMER_CLK_SRC_MASK) | clock_source;
-}
-
-static void timer_reset(int n)
-{
-	timer_disable(n);
-	timer_ack_irq(n);
-	timer_set_reset_value(n, 0xffffffff);
-	timer_set_clock(n, TIMER_CLK_SRC_32K);
-}
-
-/* Convert hardware countdown timer to 64bit countup ticks. */
-static uint64_t timer_read_raw_system(void)
-{
-	uint32_t timer_ctrl = SCP_CORE0_TIMER_IRQ_CTRL(TIMER_SYSTEM);
-	uint32_t sys_high_adj = sys_high;
-
-	/*
-	 * If an IRQ is pending, but has not been serviced yet, adjust the
-	 * sys_high value.
-	 */
-	if (timer_ctrl & TIMER_IRQ_STATUS)
-		sys_high_adj = sys_high ? (sys_high - 1)
-					: (TIMER_CLOCK_MHZ - 1);
-
-	return OVERFLOW_TICKS - (((uint64_t)sys_high_adj << 32) |
-				 SCP_CORE0_TIMER_CUR_VAL(TIMER_SYSTEM));
-}
-
-static uint64_t timer_read_raw_event(void)
-{
-	return OVERFLOW_TICKS - (((uint64_t)event_high << 32) |
-				 SCP_CORE0_TIMER_CUR_VAL(TIMER_EVENT));
-}
-
-static void timer_reload(int n, uint32_t value)
-{
-	timer_disable(n);
-	timer_set_reset_value(n, value);
-	timer_enable(n);
-}
-
-static int timer_reload_event_high(void)
-{
-	if (event_high) {
-		if (SCP_CORE0_TIMER_RST_VAL(TIMER_EVENT) == 0xffffffff)
-			timer_enable(TIMER_EVENT);
-		else
-			timer_reload(TIMER_EVENT, 0xffffffff);
-		event_high--;
-		return 1;
-	}
-
-	timer_disable(TIMER_EVENT);
-	return 0;
-}
-
-int __hw_clock_source_init(uint32_t start_t)
-{
-	int t;
-
-	/* enable clock gate */
-	SCP_SET_CLK_CG |= CG_TIMER_MCLK | CG_TIMER_BCLK;
-
-	/* reset all timer, select 32768Hz clock source */
-	for (t = 0; t < NUM_TIMERS; ++t)
-		timer_reset(t);
-
-	/* System timestamp timer */
-	timer_set_clock(TIMER_SYSTEM, TIMER_CLK_SRC_26M);
-	sys_high = TIMER_CLOCK_MHZ - 1;
-	timer_set_reset_value(TIMER_SYSTEM, 0xffffffff);
-	task_enable_irq(SCP_IRQ_TIMER(TIMER_SYSTEM));
-	timer_enable(TIMER_SYSTEM);
-
-	/* Event tick timer */
-	timer_set_clock(TIMER_EVENT, TIMER_CLK_SRC_26M);
-	task_enable_irq(SCP_IRQ_TIMER(TIMER_EVENT));
-
-	return SCP_IRQ_TIMER(TIMER_SYSTEM);
-}
-
-uint32_t __hw_clock_source_read(void)
-{
-	return timer_read_raw_system() / TIMER_CLOCK_MHZ;
-}
-
-uint32_t __hw_clock_event_get(void)
-{
-	return (timer_read_raw_event() + timer_read_raw_system())
-			/ TIMER_CLOCK_MHZ;
-}
-
-void __hw_clock_event_clear(void)
-{
-	/* c1ea4, magic number for clear state */
-	timer_disable(TIMER_EVENT);
-	timer_set_reset_value(TIMER_EVENT, 0x0000c1ea4);
-	event_high = 0;
-}
-
-void __hw_clock_event_set(uint32_t deadline)
-{
-	uint64_t deadline_raw = (uint64_t)deadline * TIMER_CLOCK_MHZ;
-	uint64_t now_raw = timer_read_raw_system();
-	uint32_t event_deadline;
-
-	if (deadline_raw > now_raw) {
-		deadline_raw -= now_raw;
-		event_deadline = (uint32_t)deadline_raw;
-		event_high = deadline_raw >> 32;
-	} else {
-		event_deadline = 1;
-		event_high = 0;
-	}
-
-	if (event_deadline)
-		timer_reload(TIMER_EVENT, event_deadline);
-	else
-		timer_reload_event_high();
-}
-
-static void irq_group6_handler(void)
-{
-	extern volatile int ec_int;
-
-	switch (ec_int) {
-	case SCP_IRQ_TIMER(TIMER_EVENT):
-		if (timer_is_irq(TIMER_EVENT)) {
-			timer_ack_irq(TIMER_EVENT);
-
-			if (!timer_reload_event_high())
-				process_timers(0);
-
-			task_clear_pending_irq(ec_int);
-		}
-		break;
-	case SCP_IRQ_TIMER(TIMER_SYSTEM):
-		/* If this is a hardware irq, check overflow */
-		if (!in_soft_interrupt_context()) {
-			timer_ack_irq(TIMER_SYSTEM);
-
-			if (sys_high) {
-				--sys_high;
-				process_timers(0);
-			} else {
-				/* Overflow, reload system timer */
-				sys_high = TIMER_CLOCK_MHZ - 1;
-				process_timers(1);
-			}
-
-			task_clear_pending_irq(ec_int);
-		} else {
-			process_timers(0);
-		}
-		break;
-	}
-}
-DECLARE_IRQ(6, irq_group6_handler, 0);
diff --git a/chip/mt8192_scp/intc.c b/chip/mt8192_scp/intc.c
deleted file mode 100644
index bd7416c31e..0000000000
--- a/chip/mt8192_scp/intc.c
+++ /dev/null
@@ -1,260 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* INTC control module */
-
-#include "console.h"
-#include "csr.h"
-#include "registers.h"
-
-/*
- * INTC_GRP_0 is reserved.  See swirq of syscall_handler() in
- * core/riscv-rv32i/task.c for more details.
- *
- * Lower group has higher priority.
- */
-enum INTC_GROUP {
-	INTC_GRP_0 = 0x0,
-	INTC_GRP_1,
-	INTC_GRP_2,
-	INTC_GRP_3,
-	INTC_GRP_4,
-	INTC_GRP_5,
-	INTC_GRP_6,
-	INTC_GRP_7,
-	INTC_GRP_8,
-	INTC_GRP_9,
-	INTC_GRP_10,
-	INTC_GRP_11,
-	INTC_GRP_12,
-	INTC_GRP_13,
-	INTC_GRP_14,
-};
-
-static struct {
-	uint8_t group;
-} irqs[SCP_INTC_IRQ_COUNT] = {
-	/* 0 */
-	[SCP_IRQ_GIPC_IN0]		= { INTC_GRP_7 },
-	[SCP_IRQ_GIPC_IN1]		= { INTC_GRP_0 },
-	[SCP_IRQ_GIPC_IN2]		= { INTC_GRP_0 },
-	[SCP_IRQ_GIPC_IN3]		= { INTC_GRP_0 },
-	/* 4 */
-	[SCP_IRQ_SPM]			= { INTC_GRP_0 },
-	[SCP_IRQ_AP_CIRQ]		= { INTC_GRP_0 },
-	[SCP_IRQ_EINT]			= { INTC_GRP_0 },
-	[SCP_IRQ_PMIC]			= { INTC_GRP_0 },
-	/* 8 */
-	[SCP_IRQ_UART0_TX]		= { INTC_GRP_12 },
-	[SCP_IRQ_UART1_TX]		= { INTC_GRP_12 },
-	[SCP_IRQ_I2C0]			= { INTC_GRP_0 },
-	[SCP_IRQ_I2C1_0]		= { INTC_GRP_0 },
-	/* 12 */
-	[SCP_IRQ_BUS_DBG_TRACKER]	= { INTC_GRP_0 },
-	[SCP_IRQ_CLK_CTRL]		= { INTC_GRP_0 },
-	[SCP_IRQ_VOW]			= { INTC_GRP_0 },
-	[SCP_IRQ_TIMER0]		= { INTC_GRP_6 },
-	/* 16 */
-	[SCP_IRQ_TIMER1]		= { INTC_GRP_6 },
-	[SCP_IRQ_TIMER2]		= { INTC_GRP_6 },
-	[SCP_IRQ_TIMER3]		= { INTC_GRP_6 },
-	[SCP_IRQ_TIMER4]		= { INTC_GRP_6 },
-	/* 20 */
-	[SCP_IRQ_TIMER5]		= { INTC_GRP_6 },
-	[SCP_IRQ_OS_TIMER]		= { INTC_GRP_0 },
-	[SCP_IRQ_UART0_RX]		= { INTC_GRP_12 },
-	[SCP_IRQ_UART1_RX]		= { INTC_GRP_12 },
-	/* 24 */
-	[SCP_IRQ_GDMA]			= { INTC_GRP_0 },
-	[SCP_IRQ_AUDIO]			= { INTC_GRP_0 },
-	[SCP_IRQ_MD_DSP]		= { INTC_GRP_0 },
-	[SCP_IRQ_ADSP]			= { INTC_GRP_0 },
-	/* 28 */
-	[SCP_IRQ_CPU_TICK]		= { INTC_GRP_0 },
-	[SCP_IRQ_SPI0]			= { INTC_GRP_0 },
-	[SCP_IRQ_SPI1]			= { INTC_GRP_0 },
-	[SCP_IRQ_SPI2]			= { INTC_GRP_0 },
-	/* 32 */
-	[SCP_IRQ_NEW_INFRA_SYS_CIRQ]	= { INTC_GRP_0 },
-	[SCP_IRQ_DBG]			= { INTC_GRP_0 },
-	[SCP_IRQ_CCIF0]			= { INTC_GRP_0 },
-	[SCP_IRQ_CCIF1]			= { INTC_GRP_0 },
-	/* 36 */
-	[SCP_IRQ_CCIF2]			= { INTC_GRP_0 },
-	[SCP_IRQ_WDT]			= { INTC_GRP_0 },
-	[SCP_IRQ_USB0]			= { INTC_GRP_0 },
-	[SCP_IRQ_USB1]			= { INTC_GRP_0 },
-	/* 40 */
-	[SCP_IRQ_DPMAIF]		= { INTC_GRP_0 },
-	[SCP_IRQ_INFRA]			= { INTC_GRP_0 },
-	[SCP_IRQ_CLK_CTRL_CORE]		= { INTC_GRP_0 },
-	[SCP_IRQ_CLK_CTRL2_CORE]	= { INTC_GRP_0 },
-	/* 44 */
-	[SCP_IRQ_CLK_CTRL2]		= { INTC_GRP_0 },
-	[SCP_IRQ_GIPC_IN4]		= { INTC_GRP_0 },
-	[SCP_IRQ_PERIBUS_TIMEOUT]	= { INTC_GRP_0 },
-	[SCP_IRQ_INFRABUS_TIMEOUT]	= { INTC_GRP_0 },
-	/* 48 */
-	[SCP_IRQ_MET0]			= { INTC_GRP_0 },
-	[SCP_IRQ_MET1]			= { INTC_GRP_0 },
-	[SCP_IRQ_MET2]			= { INTC_GRP_0 },
-	[SCP_IRQ_MET3]			= { INTC_GRP_0 },
-	/* 52 */
-	[SCP_IRQ_AP_WDT]		= { INTC_GRP_0 },
-	[SCP_IRQ_L2TCM_SEC_VIO]		= { INTC_GRP_0 },
-	[SCP_IRQ_CPU_TICK1]		= { INTC_GRP_0 },
-	[SCP_IRQ_MAD_DATAIN]		= { INTC_GRP_0 },
-	/* 56 */
-	[SCP_IRQ_I3C0_IBI_WAKE]		= { INTC_GRP_0 },
-	[SCP_IRQ_I3C1_IBI_WAKE]		= { INTC_GRP_0 },
-	[SCP_IRQ_I3C2_IBI_WAKE]		= { INTC_GRP_0 },
-	[SCP_IRQ_APU_ENGINE]		= { INTC_GRP_0 },
-	/* 60 */
-	[SCP_IRQ_MBOX0]			= { INTC_GRP_0 },
-	[SCP_IRQ_MBOX1]			= { INTC_GRP_0 },
-	[SCP_IRQ_MBOX2]			= { INTC_GRP_0 },
-	[SCP_IRQ_MBOX3]			= { INTC_GRP_0 },
-	/* 64 */
-	[SCP_IRQ_MBOX4]			= { INTC_GRP_0 },
-	[SCP_IRQ_SYS_CLK_REQ]		= { INTC_GRP_0 },
-	[SCP_IRQ_BUS_REQ]		= { INTC_GRP_0 },
-	[SCP_IRQ_APSRC_REQ]		= { INTC_GRP_0 },
-	/* 68 */
-	[SCP_IRQ_APU_MBOX]		= { INTC_GRP_0 },
-	[SCP_IRQ_DEVAPC_SECURE_VIO]	= { INTC_GRP_0 },
-	/* 72 */
-	/* 76 */
-	[SCP_IRQ_I2C1_2]		= { INTC_GRP_0 },
-	[SCP_IRQ_I2C2]			= { INTC_GRP_0 },
-	/* 80 */
-	[SCP_IRQ_AUD2AUDIODSP]		= { INTC_GRP_0 },
-	[SCP_IRQ_AUD2AUDIODSP_2]	= { INTC_GRP_0 },
-	[SCP_IRQ_CONN2ADSP_A2DPOL]	= { INTC_GRP_0 },
-	[SCP_IRQ_CONN2ADSP_BTCVSD]	= { INTC_GRP_0 },
-	/* 84 */
-	[SCP_IRQ_CONN2ADSP_BLEISO]	= { INTC_GRP_0 },
-	[SCP_IRQ_PCIE2ADSP]		= { INTC_GRP_0 },
-	[SCP_IRQ_APU2ADSP_ENGINE]	= { INTC_GRP_0 },
-	[SCP_IRQ_APU2ADSP_MBOX]		= { INTC_GRP_0 },
-	/* 88 */
-	[SCP_IRQ_CCIF3]			= { INTC_GRP_0 },
-	[SCP_IRQ_I2C_DMA0]		= { INTC_GRP_0 },
-	[SCP_IRQ_I2C_DMA1]		= { INTC_GRP_0 },
-	[SCP_IRQ_I2C_DMA2]		= { INTC_GRP_0 },
-	/* 92 */
-	[SCP_IRQ_I2C_DMA3]		= { INTC_GRP_0 },
-};
-BUILD_ASSERT(ARRAY_SIZE(irqs) == SCP_INTC_IRQ_COUNT);
-
-/*
- * Find current interrupt source.
- *
- * Lower group has higher priority.
- * Higher INT number has higher priority.
- */
-int chip_get_ec_int(void)
-{
-	extern volatile int ec_int;
-	unsigned int group, sta;
-	int word;
-
-	if (!SCP_CORE0_INTC_IRQ_OUT)
-		goto error;
-
-	group = read_csr(CSR_VIC_MICAUSE);
-
-	for (word = SCP_INTC_GRP_LEN - 1; word >= 0; --word) {
-		sta = SCP_CORE0_INTC_IRQ_GRP_STA(group, word);
-		if (sta) {
-			ec_int = __fls(sta) + word * 32;
-			return ec_int;
-		}
-	}
-
-error:
-	/* unreachable, SCP crashes and dumps registers after returning */
-	return -1;
-}
-
-int chip_get_intc_group(int irq)
-{
-	return irqs[irq].group;
-}
-
-void chip_enable_irq(int irq)
-{
-	unsigned int word, group, mask;
-
-	word = SCP_INTC_WORD(irq);
-	group = irqs[irq].group;
-	mask = BIT(SCP_INTC_BIT(irq));
-
-	/* disable interrupt */
-	SCP_CORE0_INTC_IRQ_EN(word) &= ~mask;
-	/* set group */
-	SCP_CORE0_INTC_IRQ_GRP(group, word) |= mask;
-	/* set as a wakeup source */
-	SCP_CORE0_INTC_SLP_WAKE_EN(word) |= mask;
-	/* enable interrupt */
-	SCP_CORE0_INTC_IRQ_EN(word) |= mask;
-}
-
-void chip_disable_irq(int irq)
-{
-	/*
-	 * Disabling INTC IRQ in runtime is unstable in MT8192 SCP.
-	 * See b/163682416#comment17.
-	 *
-	 * Ideally, this function will be removed by LTO.
-	 */
-	ccprints("WARNING: %s is unsupported", __func__);
-}
-
-void chip_clear_pending_irq(int irq)
-{
-	unsigned int group = irqs[irq].group;
-
-	/* must clear interrupt source before writing this */
-	write_csr(CSR_VIC_MIEMS, group);
-}
-
-int chip_trigger_irq(int irq)
-{
-	extern volatile int ec_int;
-
-	ec_int = irq;
-	return irqs[irq].group;
-}
-
-void chip_init_irqs(void)
-{
-	unsigned int word, group;
-
-	/* INTC init */
-	/* clear enable and wakeup settings */
-	for (word = 0; word < SCP_INTC_GRP_LEN; ++word) {
-		SCP_CORE0_INTC_IRQ_EN(word) = 0x0;
-		SCP_CORE0_INTC_SLP_WAKE_EN(word) = 0x0;
-
-		/* clear group settings */
-		for (group = 0; group < SCP_INTC_GRP_COUNT; ++group)
-			SCP_CORE0_INTC_IRQ_GRP(group, word) = 0x0;
-	}
-	/* reset to default polarity */
-	SCP_CORE0_INTC_IRQ_POL(0) = SCP_INTC_IRQ_POL0;
-	SCP_CORE0_INTC_IRQ_POL(1) = SCP_INTC_IRQ_POL1;
-	SCP_CORE0_INTC_IRQ_POL(2) = SCP_INTC_IRQ_POL2;
-
-	/* GVIC init */
-	/* enable all groups as interrupt sources */
-	write_csr(CSR_VIC_MIMASK_G0, 0xffffffff);
-	/* use level trigger */
-	write_csr(CSR_VIC_MILSEL_G0, 0xffffffff);
-	/* enable all groups as wakeup sources */
-	write_csr(CSR_VIC_MIWAKEUP_G0, 0xffffffff);
-
-	/* enable GVIC */
-	set_csr(CSR_MCTREN, CSR_MCTREN_VIC);
-}
diff --git a/chip/mt8192_scp/ipi.c b/chip/mt8192_scp/ipi.c
deleted file mode 100644
index a6b2028329..0000000000
--- a/chip/mt8192_scp/ipi.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "atomic.h"
-#include "common.h"
-#include "console.h"
-#include "hooks.h"
-#include "hostcmd.h"
-#include "ipi_chip.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_IPI, format, ##args)
-#define CPRINTS(format, args...) cprints(CC_IPI, format, ##args)
-
-static uint8_t init_done;
-
-static struct mutex ipi_lock;
-static struct ipc_shared_obj *const ipi_send_buf =
-	(struct ipc_shared_obj *)CONFIG_IPC_SHARED_OBJ_ADDR;
-static struct ipc_shared_obj *const ipi_recv_buf =
-	(struct ipc_shared_obj *)(CONFIG_IPC_SHARED_OBJ_ADDR +
-				  sizeof(struct ipc_shared_obj));
-
-static uint32_t disable_irq_count, saved_int_mask;
-
-void ipi_disable_irq(void)
-{
-	if (deprecated_atomic_read_add(&disable_irq_count, 1) == 0)
-		saved_int_mask = read_clear_int_mask();
-}
-
-void ipi_enable_irq(void)
-{
-	if (deprecated_atomic_read_sub(&disable_irq_count, 1) == 1)
-		set_int_mask(saved_int_mask);
-}
-
-static int ipi_is_busy(void)
-{
-	return SCP_SCP2APMCU_IPC_SET & IPC_SCP2HOST;
-}
-
-static void ipi_wake_ap(int32_t id)
-{
-	if (id >= IPI_COUNT)
-		return;
-
-	if (*ipi_wakeup_table[id])
-		SCP_SCP2SPM_IPC_SET = IPC_SCP2HOST;
-}
-
-int ipi_send(int32_t id, const void *buf, uint32_t len, int wait)
-{
-	int ret;
-
-	if (!init_done) {
-		CPRINTS("IPI has not initialized");
-		return EC_ERROR_BUSY;
-	}
-
-	if (in_interrupt_context()) {
-		CPRINTS("invoke %s() in ISR context", __func__);
-		return EC_ERROR_BUSY;
-	}
-
-	if (len > sizeof(ipi_send_buf->buffer)) {
-		CPRINTS("data length exceeds limitation");
-		return EC_ERROR_INVAL;
-	}
-
-	ipi_disable_irq();
-	mutex_lock(&ipi_lock);
-
-	if (ipi_is_busy()) {
-		/*
-		 * If the following conditions meet,
-		 *   1) There is an IPI pending in AP.
-		 *   2) The incoming IPI is a wakeup IPI.
-		 * then it assumes that AP is in suspend state.
-		 * Send a AP wakeup request to SPM.
-		 *
-		 * The incoming IPI will be checked if it's a wakeup source.
-		 */
-		ipi_wake_ap(id);
-
-		CPRINTS("IPI busy, id=%d", id);
-		ret = EC_ERROR_BUSY;
-		goto error;
-	}
-
-	ipi_send_buf->id = id;
-	ipi_send_buf->len = len;
-	memcpy(ipi_send_buf->buffer, buf, len);
-
-	/* interrupt AP to handle the message */
-	ipi_wake_ap(id);
-	SCP_SCP2APMCU_IPC_SET = IPC_SCP2HOST;
-
-	if (wait)
-		while (ipi_is_busy())
-			;
-
-	ret = EC_SUCCESS;
-error:
-	mutex_unlock(&ipi_lock);
-	ipi_enable_irq();
-	return ret;
-}
-
-static void ipi_enable_deferred(void)
-{
-	struct scp_run_t scp_run;
-	int ret;
-
-	init_done = 1;
-
-	/* inform AP that SCP is up */
-	scp_run.signaled = 1;
-	strncpy(scp_run.fw_ver, system_get_version(EC_IMAGE_RW),
-		SCP_FW_VERSION_LEN);
-	scp_run.dec_capability = VCODEC_CAPABILITY_4K_DISABLED;
-	scp_run.enc_capability = 0;
-
-	ret = ipi_send(SCP_IPI_INIT, (void *)&scp_run, sizeof(scp_run), 1);
-	if (ret) {
-		CPRINTS("failed to send initialization IPC messages");
-		init_done = 0;
-		return;
-	}
-
-#ifdef HAS_TASK_HOSTCMD
-	hostcmd_init();
-#endif
-
-	task_enable_irq(SCP_IRQ_GIPC_IN0);
-}
-DECLARE_DEFERRED(ipi_enable_deferred);
-
-static void ipi_init(void)
-{
-	memset(ipi_send_buf, 0, sizeof(struct ipc_shared_obj));
-	memset(ipi_recv_buf, 0, sizeof(struct ipc_shared_obj));
-
-	/* enable IRQ after all tasks are up */
-	hook_call_deferred(&ipi_enable_deferred_data, 0);
-}
-DECLARE_HOOK(HOOK_INIT, ipi_init, HOOK_PRIO_DEFAULT);
-
-static void ipi_handler(void)
-{
-	if (ipi_recv_buf->id >= IPI_COUNT) {
-		CPRINTS("invalid IPI, id=%d", ipi_recv_buf->id);
-		return;
-	}
-
-	CPRINTS("IPI %d", ipi_recv_buf->id);
-
-	ipi_handler_table[ipi_recv_buf->id](
-		ipi_recv_buf->id, ipi_recv_buf->buffer, ipi_recv_buf->len);
-}
-
-static void irq_group7_handler(void)
-{
-	extern volatile int ec_int;
-
-	if (SCP_GIPC_IN_SET & GIPC_IN(0)) {
-		ipi_handler();
-		SCP_GIPC_IN_CLR = GIPC_IN(0);
-		task_clear_pending_irq(ec_int);
-	}
-}
-DECLARE_IRQ(7, irq_group7_handler, 0);
diff --git a/chip/mt8192_scp/ipi_chip.h b/chip/mt8192_scp/ipi_chip.h
deleted file mode 100644
index 8cc3376880..0000000000
--- a/chip/mt8192_scp/ipi_chip.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_IPI_CHIP_H
-#define __CROS_EC_IPI_CHIP_H
-
-/*
- * Length of EC version string is at most 32 byte (NULL included), which
- * also aligns SCP fw_version length.
- */
-#define SCP_FW_VERSION_LEN 32
-
-/*
- * Video decoder supported capability:
- * BIT(4): 0 enable 4K
- *         1 disable 4K
- */
-#define VCODEC_CAPABILITY_4K_DISABLED BIT(4)
-
-#ifndef SCP_IPI_INIT
-#error If CONFIG_IPI is enabled, SCP_IPI_INIT must be defined.
-#endif
-
-/*
- * Share buffer layout for SCP_IPI_INIT response. This structure should sync
- * across kernel and EC.
- */
-struct scp_run_t {
-	uint32_t signaled;
-	int8_t fw_ver[SCP_FW_VERSION_LEN];
-	uint32_t dec_capability;
-	uint32_t enc_capability;
-};
-
-/*
- * The layout of the IPC0 AP/SCP shared buffer.
- * This should sync across kernel and EC.
- */
-struct ipc_shared_obj {
-	/* IPI ID */
-	int32_t id;
-	/* Length of the contents in buffer. */
-	uint32_t len;
-	/* Shared buffer contents. */
-	uint8_t buffer[CONFIG_IPC_SHARED_OBJ_BUF_SIZE];
-};
-
-/* Send a IPI contents to AP.  This shouldn't be used in ISR context. */
-int ipi_send(int32_t id, const void *buf, uint32_t len, int wait);
-
-/*
- * An IPC IRQ could be shared across many IPI handlers.
- * Those handlers would usually operate on disabling or enabling the IPC IRQ.
- * This may disorder the actual timing to on/off the IRQ when there are many
- * tasks try to operate on it.  As a result, any access to the SCP_IRQ_*
- * should go through ipi_{en,dis}able_irq(), which support a counter to
- * enable/disable the IRQ at correct timing.
- */
-/* Disable IPI IRQ. */
-void ipi_disable_irq(void);
-/* Enable IPI IRQ. */
-void ipi_enable_irq(void);
-
-/* IPI tables */
-extern void (*const ipi_handler_table[])(int32_t, void *, uint32_t);
-extern int *const ipi_wakeup_table[];
-
-/* Helper macros to build the IPI handler and wakeup functions. */
-#define IPI_HANDLER(id) CONCAT3(ipi_, id, _handler)
-#define IPI_WAKEUP(id) CONCAT3(ipi_, id, _wakeup)
-
-/*
- * Macro to declare an IPI handler.
- * _id: The ID of the IPI
- * handler: The IPI handler function
- * is_wakeup_src: Declare IPI ID as a wake-up source or not
- */
-#define DECLARE_IPI(_id, handler, is_wakeup_src) \
-	struct ipi_num_check##_id { \
-		int tmp1[_id < IPI_COUNT ? 1 : -1]; \
-		int tmp2[is_wakeup_src == 0 || is_wakeup_src == 1 ? 1 : -1]; \
-	};  \
-	void __keep IPI_HANDLER(_id)(int32_t id, void *buf, uint32_t len) \
-	{ \
-		handler(id, buf, len); \
-	} \
-	const int __keep IPI_WAKEUP(_id) = is_wakeup_src
-
-#endif /* __CROS_EC_IPI_CHIP_H */
diff --git a/chip/mt8192_scp/ipi_table.c b/chip/mt8192_scp/ipi_table.c
deleted file mode 100644
index 8fe3f1e598..0000000000
--- a/chip/mt8192_scp/ipi_table.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * IPI handlers declaration
- */
-
-#include "common.h"
-#include "ipi_chip.h"
-
-typedef void (*ipi_handler_t)(int32_t id, void *data, uint32_t len);
-
-#ifndef PASS
-#define PASS 1
-#endif
-
-#define ipi_arguments int32_t id, void *data, uint32_t len
-
-#if PASS == 1
-void ipi_handler_undefined(ipi_arguments) { }
-
-const int ipi_wakeup_undefined;
-
-#define table(type, name, x) x
-
-#define ipi_x_func(suffix, args, number)                                       \
-	extern void __attribute__(                                             \
-		(used, weak, alias(STRINGIFY(ipi_##suffix##_undefined))))      \
-		ipi_##number##_##suffix(args);
-
-#define ipi_x_var(suffix, number)                                              \
-	extern int __attribute__(                                              \
-		(weak, alias(STRINGIFY(ipi_##suffix##_undefined))))            \
-		ipi_##number##_##suffix;
-
-#endif /* PASS == 1 */
-
-#if PASS == 2
-
-#undef table
-#undef ipi_x_func
-#undef ipi_x_var
-
-#define table(type, name, x)                                                   \
-	type const name[]                                                      \
-		__attribute__((aligned(4), used, section(".rodata.ipi"))) = {x}
-
-#define ipi_x_var(suffix, number)                                              \
-	[number < IPI_COUNT ? number : -1] = &ipi_##number##_##suffix,
-
-#define ipi_x_func(suffix, args, number) ipi_x_var(suffix, number)
-
-#endif /* PASS == 2 */
-
-/*
- * Include generated IPI table (by util/gen_ipi_table). The contents originate
- * from IPI_COUNT definition in board.h
- */
-#include "ipi_table_gen.inc"
-
-#if PASS == 1
-#undef PASS
-#define PASS 2
-#include "ipi_table.c"
-BUILD_ASSERT(ARRAY_SIZE(ipi_handler_table) == IPI_COUNT);
-BUILD_ASSERT(ARRAY_SIZE(ipi_wakeup_table) == IPI_COUNT);
-#endif
diff --git a/chip/mt8192_scp/memmap.c b/chip/mt8192_scp/memmap.c
deleted file mode 100644
index 63fa4f8fc5..0000000000
--- a/chip/mt8192_scp/memmap.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "registers.h"
-#include "stdint.h"
-
-/*
- * Map SCP address (bits 31~28) to AP address
- *
- * SCP address	AP address	Note
- *
- * 0x0000_0000			SRAM
- * 0x1000_0000	0x6000_0000	un-cached DRAM
- * 0x2000_0000	0x7000_0000	un-cached DRAM
- * 0x3000_0000
- *
- * 0x4000_0000
- * 0x5000_0000	0x0000_0000
- * 0x6000_0000	0x1000_0000
- * 0x7000_0000	0xa000_0000
- *
- * 0x8000_0000
- * 0x9000_0000	0x8000_0000
- * 0xa000_0000	0x9000_0000
- * 0xb000_0000
- *
- * 0xc000_0000	0x8000_0000
- * 0xd000_0000	0x2000_0000
- * 0xe000_0000	0x3000_0000
- * 0xf000_0000	0x5000_0000
- */
-
-#define REMAP_ADDR_SHIFT		28
-#define REMAP_ADDR_LSB_MASK		(BIT(REMAP_ADDR_SHIFT) - 1)
-#define REMAP_ADDR_MSB_MASK		((~0) << REMAP_ADDR_SHIFT)
-#define MAP_INVALID 0xff
-
-static const uint8_t addr_map[16] = {
-	MAP_INVALID,	/* SRAM */
-	0x6,		/* ext_addr_0x1 */
-	0x7,		/* ext_addr_0x2 */
-	MAP_INVALID,	/* no ext_addr_0x3 */
-
-	MAP_INVALID,	/* no ext_addr_0x4 */
-	0x0,		/* ext_addr_0x5 */
-	0x1,		/* ext_addr_0x6 */
-	0xa,		/* ext_addr_0x7 */
-
-	MAP_INVALID,	/* no ext_addr_0x8 */
-	0x8,		/* ext_addr_0x9 */
-	0x9,		/* ext_addr_0xa */
-	MAP_INVALID,	/* no ext_addr_0xb */
-
-	0x8,		/* ext_addr_0xc */
-	0x2,		/* ext_addr_0xd */
-	0x3,		/* ext_addr_0xe */
-	0x5,		/* ext_addr_0xf */
-};
-
-void memmap_init(void)
-{
-	SCP_R_REMAP_0X0123 =
-		(uint32_t)addr_map[0x1] << 8 |
-		(uint32_t)addr_map[0x2] << 16;
-
-	SCP_R_REMAP_0X4567 =
-		(uint32_t)addr_map[0x5] << 8 |
-		(uint32_t)addr_map[0x6] << 16 |
-		(uint32_t)addr_map[0x7] << 24;
-
-	SCP_R_REMAP_0X89AB =
-		(uint32_t)addr_map[0x9] << 8 |
-		(uint32_t)addr_map[0xa] << 16;
-
-	SCP_R_REMAP_0XCDEF =
-		(uint32_t)addr_map[0xc] |
-		(uint32_t)addr_map[0xd] << 8 |
-		(uint32_t)addr_map[0xe] << 16 |
-		(uint32_t)addr_map[0xf] << 24;
-}
-
-int memmap_ap_to_scp(uintptr_t ap_addr, uintptr_t *scp_addr)
-{
-	int i;
-	uint8_t msb = ap_addr >> REMAP_ADDR_SHIFT;
-
-	for (i = 0; i < ARRAY_SIZE(addr_map); ++i) {
-		if (addr_map[i] != msb)
-			continue;
-
-		*scp_addr = (ap_addr & REMAP_ADDR_LSB_MASK) |
-			(i << REMAP_ADDR_SHIFT);
-		return EC_SUCCESS;
-	}
-
-	return EC_ERROR_INVAL;
-}
-
-int memmap_scp_to_ap(uintptr_t scp_addr, uintptr_t *ap_addr)
-{
-	int i = scp_addr >> REMAP_ADDR_SHIFT;
-
-	if (addr_map[i] == MAP_INVALID)
-		return EC_ERROR_INVAL;
-
-	*ap_addr = (scp_addr & REMAP_ADDR_LSB_MASK) |
-		(addr_map[i] << REMAP_ADDR_SHIFT);
-	return EC_SUCCESS;
-}
diff --git a/chip/mt8192_scp/memmap.h b/chip/mt8192_scp/memmap.h
deleted file mode 100644
index 0857c9a89e..0000000000
--- a/chip/mt8192_scp/memmap.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_MEMMAP_H
-#define __CROS_EC_MEMMAP_H
-
-#include "stdint.h"
-
-void memmap_init(void);
-
-/**
- * Translate AP addr to SCP addr.
- *
- * @param ap_addr		AP address to translate
- * @param scp_addr		Translated AP address
- * @return			EC_SUCCESS or EC_ERROR_INVAL
- */
-int memmap_ap_to_scp(uintptr_t ap_addr, uintptr_t *scp_addr);
-
-/**
- * Translate SCP addr to AP addr.
- *
- * @param scp_addr		SCP address to translate
- * @param ap_addr		Translated SCP address
- * @return			EC_SUCCESS or EC_ERROR_INVAL
- */
-int memmap_scp_to_ap(uintptr_t scp_addr, uintptr_t *ap_addr);
-
-#endif /* #ifndef __CROS_EC_MEMMAP_H */
diff --git a/chip/mt8192_scp/registers.h b/chip/mt8192_scp/registers.h
deleted file mode 100644
index cde931a2ba..0000000000
--- a/chip/mt8192_scp/registers.h
+++ /dev/null
@@ -1,386 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Register map */
-
-#ifndef __CROS_EC_REGISTERS_H
-#define __CROS_EC_REGISTERS_H
-
-#include "common.h"
-#include "compile_time_macros.h"
-
-#define UNIMPLEMENTED_GPIO_BANK 0
-
-#define SCP_REG_BASE			0x70000000
-
-/* clock control */
-#define SCP_CLK_CTRL_BASE		(SCP_REG_BASE + 0x21000)
-/* clock source select */
-#define SCP_CLK_SW_SEL			REG32(SCP_CLK_CTRL_BASE + 0x0000)
-#define   CLK_SW_SEL_26M		0
-#define   CLK_SW_SEL_32K		1
-#define   CLK_SW_SEL_ULPOSC2		2
-#define   CLK_SW_SEL_ULPOSC1		3
-#define SCP_CLK_ENABLE			REG32(SCP_CLK_CTRL_BASE + 0x0004)
-#define   CLK_HIGH_EN			BIT(1) /* ULPOSC */
-#define   CLK_HIGH_CG			BIT(2)
-/* system clock counter value */
-#define SCP_CLK_SYS_VAL			REG32(SCP_CLK_CTRL_BASE + 0x0014)
-#define   CLK_SYS_VAL_MASK		(0x3ff << 0)
-#define   CLK_SYS_VAL_VAL(v)		((v) & CLK_SYS_VAL_MASK)
-/* ULPOSC clock counter value */
-#define SCP_CLK_HIGH_VAL		REG32(SCP_CLK_CTRL_BASE + 0x0018)
-#define   CLK_HIGH_VAL_MASK             (0x1f << 0)
-#define   CLK_HIGH_VAL_VAL(v)		((v) & CLK_HIGH_VAL_MASK)
-/* sleep mode control */
-#define SCP_SLEEP_CTRL                  REG32(SCP_CLK_CTRL_BASE + 0x0020)
-#define   SLP_CTRL_EN			BIT(0)
-#define   VREQ_COUNT_MASK		(0x7F << 1)
-#define   VREQ_COUNT_VAL(v)		(((v) << 1) & VREQ_COUNT_MASK)
-#define   SPM_SLP_MODE			BIT(8)
-/* clock divider select */
-#define SCP_CLK_DIV_SEL			REG32(SCP_CLK_CTRL_BASE + 0x0024)
-#define   CLK_DIV_SEL1			0
-#define   CLK_DIV_SEL2			1
-#define   CLK_DIV_SEL4			2
-#define   CLK_DIV_SEL3			3
-/* clock gate */
-#define SCP_SET_CLK_CG			REG32(SCP_CLK_CTRL_BASE + 0x0030)
-#define   CG_TIMER_MCLK			BIT(0)
-#define   CG_TIMER_BCLK			BIT(1)
-#define   CG_MAD_MCLK			BIT(2)
-#define   CG_I2C_MCLK			BIT(3)
-#define   CG_I2C_BCLK			BIT(4)
-#define   CG_GPIO_MCLK			BIT(5)
-#define   CG_AP2P_MCLK			BIT(6)
-#define   CG_UART0_MCLK			BIT(7)
-#define   CG_UART0_BCLK			BIT(8)
-#define   CG_UART0_RST			BIT(9)
-#define   CG_UART1_MCLK			BIT(10)
-#define   CG_UART1_BCLK			BIT(11)
-#define   CG_UART1_RST			BIT(12)
-#define   CG_SPI0			BIT(13)
-#define   CG_SPI1			BIT(14)
-#define   CG_SPI2			BIT(15)
-#define   CG_DMA_CH0			BIT(16)
-#define   CG_DMA_CH1			BIT(17)
-#define   CG_DMA_CH2			BIT(18)
-#define   CG_DMA_CH3			BIT(19)
-#define   CG_I3C0			BIT(21)
-#define   CG_I3C1			BIT(22)
-#define   CG_DMA2_CH0			BIT(23)
-#define   CG_DMA2_CH1			BIT(24)
-#define   CG_DMA2_CH2			BIT(25)
-#define   CG_DMA2_CH3			BIT(26)
-/* UART clock select */
-#define SCP_UART_CK_SEL			REG32(SCP_CLK_CTRL_BASE + 0x0044)
-#define   UART0_CK_SEL_SHIFT		0
-#define   UART0_CK_SEL_MASK		(0x3 << UART0_CK_SEL_SHIFT)
-#define   UART0_CK_SEL_VAL(v)		((v) & UART0_CK_SEL_MASK)
-#define   UART0_CK_SW_STATUS_MASK	(0xf << 8)
-#define   UART0_CK_SW_STATUS_VAL(v)	((v) & UART0_CK_SW_STATUS_MASK)
-#define   UART1_CK_SEL_SHIFT		16
-#define   UART1_CK_SEL_MASK		(0x3 << UART1_CK_SEL_SHIFT)
-#define   UART1_CK_SEL_VAL(v)		((v) & UART1_CK_SEL_MASK)
-#define   UART1_CK_SW_STATUS_MASK	(0xf << 24)
-#define   UART1_CK_SW_STATUS_VAL(v)	((v) & UART1_CK_SW_STATUS_MASK)
-#define     UART_CK_SEL_26M		0
-#define     UART_CK_SEL_32K		1
-#define     UART_CK_SEL_ULPOSC		2
-#define     UART_CK_SW_STATUS_26M	BIT(0)
-#define     UART_CK_SW_STATUS_32K	BIT(1)
-#define     UART_CK_SW_STATUS_ULPOS	BIT(2)
-/* VREQ control */
-#define SCP_CPU_VREQ_CTRL		REG32(SCP_CLK_CTRL_BASE + 0x0054)
-#define   VREQ_SEL			BIT(0)
-#define   VREQ_VALUE			BIT(4)
-#define   VREQ_EXT_SEL			BIT(8)
-#define   VREQ_DVFS_SEL			BIT(16)
-#define   VREQ_DVFS_VALUE		BIT(20)
-#define   VREQ_DVFS_EXT_SEL		BIT(24)
-#define   VREQ_SRCLKEN_SEL		BIT(27)
-#define   VREQ_SRCLKEN_VALUE		BIT(28)
-/* clock on control */
-#define SCP_CLK_HIGH_CORE_CG		REG32(SCP_CLK_CTRL_BASE + 0x005C)
-#define   HIGH_CORE_CG			BIT(1)
-#define SCP_CLK_ON_CTRL			REG32(SCP_CLK_CTRL_BASE + 0x006C)
-#define   HIGH_AO			BIT(0)
-#define   HIGH_DIS_SUB			BIT(1)
-#define   HIGH_CG_AO			BIT(2)
-#define   HIGH_CORE_AO			BIT(4)
-#define   HIGH_CORE_DIS_SUB		BIT(5)
-#define   HIGH_CORE_CG_AO		BIT(6)
-/* clock general control */
-#define SCP_CLK_CTRL_GENERAL_CTRL	REG32(SCP_CLK_CTRL_BASE + 0x009C)
-#define   VREQ_PMIC_WRAP_SEL		(0x2)
-
-/* system control */
-#define SCP_SYS_CTRL			REG32(SCP_REG_BASE + 0x24000)
-#define   AUTO_DDREN			BIT(9)
-
-/* IPC */
-#define SCP_SCP2APMCU_IPC_SET		REG32(SCP_REG_BASE + 0x24080)
-#define SCP_SCP2SPM_IPC_SET		REG32(SCP_REG_BASE + 0x24090)
-#define   IPC_SCP2HOST			BIT(0)
-#define SCP_GIPC_IN_SET			REG32(SCP_REG_BASE + 0x24098)
-#define SCP_GIPC_IN_CLR			REG32(SCP_REG_BASE + 0x2409C)
-#define   GIPC_IN(n)			BIT(n)
-
-/* UART */
-#define SCP_UART_COUNT			2
-#define UART_TX_IRQ(n)			CONCAT3(SCP_IRQ_UART, n, _TX)
-#define UART_RX_IRQ(n)			CONCAT3(SCP_IRQ_UART, n, _RX)
-#define SCP_UART0_BASE			(SCP_REG_BASE + 0x26000)
-#define SCP_UART1_BASE			(SCP_REG_BASE + 0x27000)
-#define SCP_UART_BASE(n)		CONCAT3(SCP_UART, n, _BASE)
-#define UART_REG(n, offset)		REG32_ADDR(SCP_UART_BASE(n))[offset]
-
-/* WDT */
-#define SCP_CORE0_WDT_IRQ		REG32(SCP_REG_BASE + 0x30030)
-#define SCP_CORE0_WDT_CFG		REG32(SCP_REG_BASE + 0x30034)
-#define   WDT_FREQ			33825 /* 0xFFFFF / 31 */
-#define   WDT_MAX_PERIOD		0xFFFFF /* 31 seconds */
-#define   WDT_PERIOD(ms)		(WDT_FREQ * (ms) / 1000)
-#define   WDT_EN			BIT(31)
-#define SCP_CORE0_WDT_KICK		REG32(SCP_REG_BASE + 0x30038)
-#define SCP_CORE0_WDT_CUR_VAL		REG32(SCP_REG_BASE + 0x3003C)
-
-/* INTC */
-#define SCP_INTC_IRQ_POL0		0xef001f20
-#define SCP_INTC_IRQ_POL1		0x0800001d
-#define SCP_INTC_IRQ_POL2		0x00000020
-#define SCP_INTC_WORD(irq)		((irq) >> 5) /* word length = 2^5 */
-#define SCP_INTC_BIT(irq)		((irq) & 0x1F) /* bit shift =LSB[0:4] */
-#define SCP_INTC_GRP_COUNT		15
-#define SCP_INTC_GRP_LEN		3
-#define SCP_INTC_GRP_GAP		4
-#define SCP_INTC_IRQ_COUNT		96
-#define SCP_CORE0_INTC_IRQ_BASE		(SCP_REG_BASE + 0x32000)
-#define SCP_CORE0_INTC_IRQ_STA(w) \
-		REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0010)[(w)]
-#define SCP_CORE0_INTC_IRQ_EN(w) \
-		REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0020)[(w)]
-#define SCP_CORE0_INTC_IRQ_POL(w) \
-		REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0040)[(w)]
-#define SCP_CORE0_INTC_IRQ_GRP(g, w) \
-		REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0050 + \
-			   ((g) << SCP_INTC_GRP_GAP))[(w)]
-#define SCP_CORE0_INTC_IRQ_GRP_STA(g, w) \
-		REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0150 + \
-			   ((g) << SCP_INTC_GRP_GAP))[(w)]
-#define SCP_CORE0_INTC_SLP_WAKE_EN(w) \
-		REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0240)[(w)]
-#define SCP_CORE0_INTC_IRQ_OUT		REG32(SCP_CORE0_INTC_IRQ_BASE + 0x0250)
-/* UART */
-#define SCP_CORE0_INTC_UART0_RX_IRQ	REG32(SCP_CORE0_INTC_IRQ_BASE + 0x0258)
-#define SCP_CORE0_INTC_UART1_RX_IRQ	REG32(SCP_CORE0_INTC_IRQ_BASE + 0x025C)
-#define SCP_CORE0_INTC_UART_RX_IRQ(n)	CONCAT3(SCP_CORE0_INTC_UART, n, _RX_IRQ)
-
-/* XGPT (general purpose timer) */
-#define NUM_TIMERS			6
-#define SCP_CORE0_TIMER_BASE(n)		(SCP_REG_BASE + 0x33000 + (0x10 * (n)))
-#define SCP_CORE0_TIMER_EN(n)		REG32(SCP_CORE0_TIMER_BASE(n) + 0x0000)
-#define   TIMER_EN			BIT(0)
-#define   TIMER_CLK_SRC_32K		(0 << 4)
-#define   TIMER_CLK_SRC_26M		(1 << 4)
-#define   TIMER_CLK_SRC_BCLK		(2 << 4)
-#define   TIMER_CLK_SRC_MCLK		(3 << 4)
-#define   TIMER_CLK_SRC_MASK		(3 << 4)
-#define SCP_CORE0_TIMER_RST_VAL(n)	REG32(SCP_CORE0_TIMER_BASE(n) + 0x0004)
-#define SCP_CORE0_TIMER_CUR_VAL(n)	REG32(SCP_CORE0_TIMER_BASE(n) + 0x0008)
-#define SCP_CORE0_TIMER_IRQ_CTRL(n)	REG32(SCP_CORE0_TIMER_BASE(n) + 0x000C)
-#define   TIMER_IRQ_EN			BIT(0)
-#define   TIMER_IRQ_STATUS		BIT(4)
-#define   TIMER_IRQ_CLR			BIT(5)
-#define SCP_IRQ_TIMER(n)		CONCAT2(SCP_IRQ_TIMER, n)
-
-/* secure control */
-#define SCP_SEC_CTRL			REG32(SCP_REG_BASE + 0xA5000)
-#define   VREQ_SECURE_DIS		BIT(4)
-/* memory remap */
-#define SCP_R_REMAP_0X0123		REG32(SCP_REG_BASE + 0xA5060)
-#define SCP_R_REMAP_0X4567		REG32(SCP_REG_BASE + 0xA5064)
-#define SCP_R_REMAP_0X89AB		REG32(SCP_REG_BASE + 0xA5068)
-#define SCP_R_REMAP_0XCDEF		REG32(SCP_REG_BASE + 0xA506C)
-
-/* external address: AP */
-#define AP_REG_BASE			0x60000000 /* 0x10000000 remap to 0x6 */
-/* OSC meter */
-#define TOPCK_BASE			AP_REG_BASE
-#define AP_CLK_MISC_CFG_0		REG32(TOPCK_BASE + 0x0140)
-#define   MISC_METER_DIVISOR_MASK	0xff000000
-#define   MISC_METER_DIV_1		0
-#define AP_CLK_DBG_CFG			REG32(TOPCK_BASE + 0x017C)
-#define   DBG_MODE_MASK			3
-#define   DBG_MODE_SET_CLOCK		0
-#define   DBG_BIST_SOURCE_MASK		(0x3f << 16)
-#define   DBG_BIST_SOURCE_ULPOSC1	(0x25 << 16)
-#define   DBG_BIST_SOURCE_ULPOSC2	(0x24 << 16)
-#define AP_SCP_CFG_0			REG32(TOPCK_BASE + 0x0220)
-#define   CFG_FREQ_METER_RUN		BIT(4)
-#define   CFG_FREQ_METER_ENABLE		BIT(12)
-#define AP_SCP_CFG_1			REG32(TOPCK_BASE + 0x0224)
-#define   CFG_FREQ_COUNTER(CFG1)	((CFG1) & 0xFFFF)
-/* AP GPIO */
-#define AP_GPIO_BASE			(AP_REG_BASE + 0x5000)
-#define AP_GPIO_MODE11_SET		REG32(AP_GPIO_BASE + 0x03B4)
-#define AP_GPIO_MODE11_CLR		REG32(AP_GPIO_BASE + 0x03B8)
-#define AP_GPIO_MODE20_SET		REG32(AP_GPIO_BASE + 0x0444)
-#define AP_GPIO_MODE20_CLR		REG32(AP_GPIO_BASE + 0x0448)
-/*
- * ULPOSC
- * osc: 0 for ULPOSC1, 1 for ULPOSC2.
- */
-#define AP_ULPOSC_CON0_BASE		(AP_REG_BASE + 0xC2B0)
-#define AP_ULPOSC_CON1_BASE		(AP_REG_BASE + 0xC2B4)
-#define AP_ULPOSC_CON2_BASE		(AP_REG_BASE + 0xC2B8)
-#define AP_ULPOSC_CON0(osc) \
-		REG32(AP_ULPOSC_CON0_BASE + (osc) * 0x10)
-#define AP_ULPOSC_CON1(osc) \
-		REG32(AP_ULPOSC_CON1_BASE + (osc) * 0x10)
-#define AP_ULPOSC_CON2(osc) \
-		REG32(AP_ULPOSC_CON2_BASE + (osc) * 0x10)
-/*
- * AP_ULPOSC_CON0
- * bit0-6: calibration
- * bit7-13: iband
- * bit14-17: fband
- * bit18-23: div
- * bit24: cp_en
- * bit25-31: reserved
- */
-#define OSC_CALI_MASK		0x7f
-#define OSC_IBAND_SHIFT		7
-#define OSC_FBAND_SHIFT		14
-#define OSC_DIV_SHIFT		18
-#define OSC_CP_EN		BIT(24)
-/* AP_ULPOSC_CON1
- * bit0-7: 32K calibration
- * bit 8-15: rsv1
- * bit 16-23: rsv2
- * bit 24-25: mod
- * bit26: div2_en
- * bit27-31: reserved
- */
-#define OSC_RSV1_SHIFT		8
-#define OSC_RSV2_SHIFT		16
-#define OSC_MOD_SHIFT		24
-#define OSC_DIV2_EN		BIT(26)
-/* AP_ULPOSC_CON2
- * bit0-7: bias
- * bit8-31: reserved
- */
-
-/* IRQ numbers */
-#define SCP_IRQ_GIPC_IN0		0
-#define SCP_IRQ_GIPC_IN1		1
-#define SCP_IRQ_GIPC_IN2		2
-#define SCP_IRQ_GIPC_IN3		3
-/* 4 */
-#define SCP_IRQ_SPM			4
-#define SCP_IRQ_AP_CIRQ			5
-#define SCP_IRQ_EINT			6
-#define SCP_IRQ_PMIC			7
-/* 8 */
-#define SCP_IRQ_UART0_TX		8
-#define SCP_IRQ_UART1_TX		9
-#define SCP_IRQ_I2C0			10
-#define SCP_IRQ_I2C1_0			11
-/* 12 */
-#define SCP_IRQ_BUS_DBG_TRACKER		12
-#define SCP_IRQ_CLK_CTRL		13
-#define SCP_IRQ_VOW			14
-#define SCP_IRQ_TIMER0			15
-/* 16 */
-#define SCP_IRQ_TIMER1			16
-#define SCP_IRQ_TIMER2			17
-#define SCP_IRQ_TIMER3			18
-#define SCP_IRQ_TIMER4			19
-/* 20 */
-#define SCP_IRQ_TIMER5			20
-#define SCP_IRQ_OS_TIMER		21
-#define SCP_IRQ_UART0_RX		22
-#define SCP_IRQ_UART1_RX		23
-/* 24 */
-#define SCP_IRQ_GDMA			24
-#define SCP_IRQ_AUDIO			25
-#define SCP_IRQ_MD_DSP			26
-#define SCP_IRQ_ADSP			27
-/* 28 */
-#define SCP_IRQ_CPU_TICK		28
-#define SCP_IRQ_SPI0			29
-#define SCP_IRQ_SPI1			30
-#define SCP_IRQ_SPI2			31
-/* 32 */
-#define SCP_IRQ_NEW_INFRA_SYS_CIRQ	32
-#define SCP_IRQ_DBG			33
-#define SCP_IRQ_CCIF0			34
-#define SCP_IRQ_CCIF1			35
-/* 36 */
-#define SCP_IRQ_CCIF2			36
-#define SCP_IRQ_WDT			37
-#define SCP_IRQ_USB0			38
-#define SCP_IRQ_USB1			39
-/* 40 */
-#define SCP_IRQ_DPMAIF			40
-#define SCP_IRQ_INFRA			41
-#define SCP_IRQ_CLK_CTRL_CORE		42
-#define SCP_IRQ_CLK_CTRL2_CORE		43
-/* 44 */
-#define SCP_IRQ_CLK_CTRL2		44
-#define SCP_IRQ_GIPC_IN4		45 /* HALT */
-#define SCP_IRQ_PERIBUS_TIMEOUT		46
-#define SCP_IRQ_INFRABUS_TIMEOUT	47
-/* 48 */
-#define SCP_IRQ_MET0			48
-#define SCP_IRQ_MET1			49
-#define SCP_IRQ_MET2			50
-#define SCP_IRQ_MET3			51
-/* 52 */
-#define SCP_IRQ_AP_WDT			52
-#define SCP_IRQ_L2TCM_SEC_VIO		53
-#define SCP_IRQ_CPU_TICK1		54
-#define SCP_IRQ_MAD_DATAIN		55
-/* 56 */
-#define SCP_IRQ_I3C0_IBI_WAKE		56
-#define SCP_IRQ_I3C1_IBI_WAKE		57
-#define SCP_IRQ_I3C2_IBI_WAKE		58
-#define SCP_IRQ_APU_ENGINE		59
-/* 60 */
-#define SCP_IRQ_MBOX0			60
-#define SCP_IRQ_MBOX1			61
-#define SCP_IRQ_MBOX2			62
-#define SCP_IRQ_MBOX3			63
-/* 64 */
-#define SCP_IRQ_MBOX4			64
-#define SCP_IRQ_SYS_CLK_REQ		65
-#define SCP_IRQ_BUS_REQ			66
-#define SCP_IRQ_APSRC_REQ		67
-/* 68 */
-#define SCP_IRQ_APU_MBOX		68
-#define SCP_IRQ_DEVAPC_SECURE_VIO	69
-/* 72 */
-/* 76 */
-#define SCP_IRQ_I2C1_2			78
-#define SCP_IRQ_I2C2			79
-/* 80 */
-#define SCP_IRQ_AUD2AUDIODSP		80
-#define SCP_IRQ_AUD2AUDIODSP_2		81
-#define SCP_IRQ_CONN2ADSP_A2DPOL	82
-#define SCP_IRQ_CONN2ADSP_BTCVSD	83
-/* 84 */
-#define SCP_IRQ_CONN2ADSP_BLEISO	84
-#define SCP_IRQ_PCIE2ADSP		85
-#define SCP_IRQ_APU2ADSP_ENGINE		86
-#define SCP_IRQ_APU2ADSP_MBOX		87
-/* 88 */
-#define SCP_IRQ_CCIF3			88
-#define SCP_IRQ_I2C_DMA0		89
-#define SCP_IRQ_I2C_DMA1		90
-#define SCP_IRQ_I2C_DMA2		91
-/* 92 */
-#define SCP_IRQ_I2C_DMA3		92
-
-#endif /* __CROS_EC_REGISTERS_H */
diff --git a/chip/mt8192_scp/system.c b/chip/mt8192_scp/system.c
deleted file mode 100644
index 8ee0cb382d..0000000000
--- a/chip/mt8192_scp/system.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* System : hardware specific implementation */
-
-#include "csr.h"
-#include "memmap.h"
-#include "registers.h"
-#include "system.h"
-
-void system_pre_init(void)
-{
-	memmap_init();
-
-	/* enable CPU and platform low power CG */
-	/* enable CPU DCM */
-	set_csr(CSR_MCTREN, CSR_MCTREN_CG);
-
-	/* Disable jump (it has only RW) and enable MPU. */
-	/* TODO: implement MPU */
-	system_disable_jump();
-}
-
-void system_reset(int flags)
-{
-	while (1)
-		;
-}
-
-int system_get_bbram(enum system_bbram_idx idx, uint8_t *value)
-{
-	return EC_ERROR_INVAL;
-}
-
-const char *system_get_chip_vendor(void)
-{
-	return "mtk";
-}
-
-const char *system_get_chip_name(void)
-{
-	/* Support only SCP_A for now */
-	return "scp_a";
-}
-
-const char *system_get_chip_revision(void)
-{
-	return "";
-}
diff --git a/chip/mt8192_scp/uart.c b/chip/mt8192_scp/uart.c
deleted file mode 100644
index 8b9f7452ae..0000000000
--- a/chip/mt8192_scp/uart.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* SCP UART module */
-
-#include "csr.h"
-#include "system.h"
-#include "uart.h"
-#include "uart_regs.h"
-#include "util.h"
-
-/*
- * UARTN == 0, SCP UART0
- * UARTN == 1, SCP UART1
- * UARTN == 2, AP UART1
- */
-#define UARTN CONFIG_UART_CONSOLE
-#define UART_IDLE_WAIT_US 500
-#define UART_INTC_GROUP 12
-
-static uint8_t init_done, tx_started;
-
-void uart_init(void)
-{
-	const uint32_t baud_rate = CONFIG_UART_BAUD_RATE;
-	/* TODO: use ULPOSC1 for S3 */
-	const uint32_t uart_clock = 26000000;
-	const uint32_t div = DIV_ROUND_NEAREST(uart_clock, baud_rate * 16);
-
-#if UARTN == 0
-	SCP_UART_CK_SEL |= UART0_CK_SEL_VAL(UART_CK_SEL_26M);
-	SCP_SET_CLK_CG |= CG_UART0_MCLK | CG_UART0_BCLK | CG_UART0_RST;
-
-	/* set AP GPIO164 and GPIO165 to alt func 3 */
-	AP_GPIO_MODE20_CLR = 0x00770000;
-	AP_GPIO_MODE20_SET = 0x00330000;
-#elif UARTN == 1
-	SCP_UART_CK_SEL |= UART1_CK_SEL_VAL(UART_CK_SEL_26M);
-	SCP_SET_CLK_CG |= CG_UART1_MCLK | CG_UART1_BCLK | CG_UART1_RST;
-#endif
-
-	/* Clear FIFO */
-	UART_FCR(UARTN) = UART_FCR_ENABLE_FIFO
-		| UART_FCR_CLEAR_RCVR
-		| UART_FCR_CLEAR_XMIT;
-	/* Line control: parity none, 8 bit, 1 stop bit */
-	UART_LCR(UARTN) = UART_LCR_WLEN8;
-	/* For baud rate <= 115200 */
-	UART_HIGHSPEED(UARTN) = 0;
-
-	/* DLAB start */
-	UART_LCR(UARTN) |= UART_LCR_DLAB;
-	UART_DLL(UARTN) = div & 0xff;
-	UART_DLH(UARTN) = (div >> 8) & 0xff;
-	UART_LCR(UARTN) &= ~UART_LCR_DLAB;
-	/* DLAB end */
-
-	/* Enable received data interrupt */
-	UART_IER(UARTN) |= UART_IER_RDI;
-
-#if (UARTN < SCP_UART_COUNT)
-	task_enable_irq(UART_TX_IRQ(UARTN));
-	task_enable_irq(UART_RX_IRQ(UARTN));
-#endif
-
-	init_done = 1;
-}
-
-int uart_init_done(void)
-{
-	return init_done;
-}
-
-void uart_tx_flush(void)
-{
-	while (!(UART_LSR(UARTN) & UART_LSR_TEMT))
-		;
-}
-
-int uart_tx_ready(void)
-{
-	return UART_LSR(UARTN) & UART_LSR_THRE;
-}
-
-int uart_rx_available(void)
-{
-	return UART_LSR(UARTN) & UART_LSR_DR;
-}
-
-void uart_write_char(char c)
-{
-	while (!uart_tx_ready())
-		;
-
-	UART_THR(UARTN) = c;
-}
-
-int uart_read_char(void)
-{
-	return UART_RBR(UARTN);
-}
-
-void uart_tx_start(void)
-{
-	tx_started = 1;
-	if (UART_IER(UARTN) & UART_IER_THRI)
-		return;
-	disable_sleep(SLEEP_MASK_UART);
-	UART_IER(UARTN) |= UART_IER_THRI;
-}
-
-void uart_tx_stop(void)
-{
-	/*
-	 * Workaround for b/157541273.
-	 * Don't unset the THRI flag unless we are in the UART ISR.
-	 *
-	 * Note:
-	 * MICAUSE denotes current INTC group number.
-	 */
-	if (in_interrupt_context() &&
-	    read_csr(CSR_VIC_MICAUSE) != UART_INTC_GROUP)
-		return;
-
-	tx_started = 0;
-	UART_IER(UARTN) &= ~UART_IER_THRI;
-	enable_sleep(SLEEP_MASK_UART);
-}
-
-static void uart_process(void)
-{
-	uart_process_input();
-	uart_process_output();
-}
-
-#if (UARTN < SCP_UART_COUNT)
-static void uart_irq_handler(void)
-{
-	extern volatile int ec_int;
-
-	switch (ec_int) {
-	case UART_TX_IRQ(UARTN):
-		uart_process();
-		task_clear_pending_irq(ec_int);
-		break;
-	case UART_RX_IRQ(UARTN):
-		uart_process();
-		SCP_CORE0_INTC_UART_RX_IRQ(UARTN) = BIT(0);
-		task_clear_pending_irq(ec_int);
-		break;
-	}
-}
-DECLARE_IRQ(UART_INTC_GROUP, uart_irq_handler, 0);
-#else
-
-#ifndef HAS_TASK_APUART
-#error "APUART task hasn't defined in ec.tasklist."
-#endif
-
-void uart_task(void)
-{
-	while (1) {
-		if (uart_rx_available() || tx_started)
-			uart_process();
-		else
-			task_wait_event(UART_IDLE_WAIT_US);
-	}
-}
-#endif
diff --git a/chip/mt8192_scp/uart_regs.h b/chip/mt8192_scp/uart_regs.h
deleted file mode 100644
index 1a421a413b..0000000000
--- a/chip/mt8192_scp/uart_regs.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* SCP UART module registers */
-
-#ifndef __CROS_EC_UART_REGS_H
-#define __CROS_EC_UART_REGS_H
-
-#include "registers.h"
-
-/* DLAB (Divisor Latch Access Bit) == 0 */
-
-/* (Read) receiver buffer register */
-#define UART_RBR(n)			UART_REG(n, 0)
-/* (Write) transmitter holding register */
-#define UART_THR(n)			UART_REG(n, 0)
-/* (Write) interrupt enable register */
-#define UART_IER(n)			UART_REG(n, 1)
-#define   UART_IER_RDI			BIT(0) /* received data */
-#define   UART_IER_THRI			BIT(1) /* THR empty */
-#define   UART_IER_RLSI			BIT(2) /* receiver LSR change */
-#define   UART_IER_MSI			BIT(3) /* MSR change */
-/* (Read) interrupt identification register */
-#define UART_IIR(n)			UART_REG(n, 2)
-#define   UART_IIR_ID_MASK		0x0e
-#define   UART_IIR_MSI			0x00 /* modem status change */
-#define   UART_IIR_NO_INT		0x01 /* no int pending */
-#define   UART_IIR_THRI			0x02 /* THR empty */
-#define   UART_IIR_RDI			0x04 /* received data available */
-#define   UART_IIR_RLSI			0x06 /* line status change */
-/* (Write) FIFO control register */
-#define UART_FCR(n)			UART_REG(n, 2)
-#define   UART_FCR_ENABLE_FIFO		BIT(0) /* enable FIFO */
-#define   UART_FCR_CLEAR_RCVR		BIT(1) /* clear receive FIFO */
-#define   UART_FCR_CLEAR_XMIT		BIT(2) /* clear transmit FIFO */
-#define   UART_FCR_DMA_SELECT		BIT(3) /* select DMA mode */
-/* (Write) line control register */
-#define UART_LCR(n)			UART_REG(n, 3)
-#define   UART_LCR_WLEN5		0 /* word length 5 bits */
-#define   UART_LCR_WLEN6		1
-#define   UART_LCR_WLEN7		2
-#define   UART_LCR_WLEN8		3
-#define   UART_LCR_STOP			BIT(2) /* stop bits: 1bit, 2bits */
-#define   UART_LCR_PARITY		BIT(3) /* parity enable */
-#define   UART_LCR_EPAR			BIT(4) /* even parity */
-#define   UART_LCR_SPAR			BIT(5) /* stick parity */
-#define   UART_LCR_SBC			BIT(6) /* set break control */
-#define   UART_LCR_DLAB			BIT(7) /* divisor latch access */
-/* (Write) modem control register */
-#define UART_MCR(n)			UART_REG(n, 4)
-/* (Read) line status register */
-#define UART_LSR(n)			UART_REG(n, 5)
-#define   UART_LSR_DR			BIT(0) /* data ready */
-#define   UART_LSR_OE			BIT(1) /* overrun error */
-#define   UART_LSR_PE			BIT(2) /* parity error */
-#define   UART_LSR_FE			BIT(3) /* frame error */
-#define   UART_LSR_BI			BIT(4) /* break interrupt */
-#define   UART_LSR_THRE			BIT(5) /* THR empty */
-#define   UART_LSR_TEMT			BIT(6) /* THR empty, line idle */
-#define   UART_LSR_FIFOE		BIT(7) /* FIFO error */
-/* (Read) modem status register */
-#define UART_MSR(n)			UART_REG(n, 6)
-/* (Read/Write) scratch register */
-#define UART_SCR(n)			UART_REG(n, 7)
-
-/* DLAB == 1 */
-
-/* (Write) divisor latch */
-#define UART_DLL(n)			UART_REG(n, 0)
-#define UART_DLH(n)			UART_REG(n, 1)
-
-/* MTK extension */
-#define UART_HIGHSPEED(n)		UART_REG(n, 9)
-
-#endif /* __CROS_EC_UART_REGS_H */
diff --git a/chip/mt8192_scp/watchdog.c b/chip/mt8192_scp/watchdog.c
deleted file mode 100644
index 72ca5edad8..0000000000
--- a/chip/mt8192_scp/watchdog.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Watchdog driver */
-
-#include "common.h"
-#include "hooks.h"
-#include "registers.h"
-#include "watchdog.h"
-
-void watchdog_reload(void)
-{
-	SCP_CORE0_WDT_KICK = BIT(0);
-}
-DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT);
-
-int watchdog_init(void)
-{
-	const uint32_t timeout = WDT_PERIOD(CONFIG_WATCHDOG_PERIOD_MS);
-
-	/* disable watchdog */
-	SCP_CORE0_WDT_CFG &= ~WDT_EN;
-	/* clear watchdog irq */
-	SCP_CORE0_WDT_IRQ |= BIT(0);
-	/* enable watchdog */
-	SCP_CORE0_WDT_CFG = WDT_EN | timeout;
-	/* reload watchdog */
-	watchdog_reload();
-
-	return EC_SUCCESS;
-}
diff --git a/chip/mt_scp/build.mk b/chip/mt_scp/build.mk
index fa6164056e..3f4baab128 100644
--- a/chip/mt_scp/build.mk
+++ b/chip/mt_scp/build.mk
@@ -1,34 +1,24 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
 # SCP specific files build
 #
 
-CORE:=cortex-m
-CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
-
 # Required chip modules
-chip-y=clock.o gpio.o memmap.o system.o uart.o
+chip-y=
 
-ifeq ($(CONFIG_IPI),y)
-$(out)/RO/chip/$(CHIP)/ipi_table.o: $(out)/ipi_table_gen.inc
-$(out)/RW/chip/$(CHIP)/ipi_table.o: $(out)/ipi_table_gen.inc
+ifeq ($(CHIP_VARIANT),$(filter $(CHIP_VARIANT),mt8183 mt8186))
+CPPFLAGS+=-Ichip/$(CHIP)/mt818x
+dirs-y+=chip/$(CHIP)/mt818x
+include chip/$(CHIP)/mt818x/build.mk
 endif
 
-ifeq ($(CONFIG_AUDIO_CODEC_WOV),y)
-HOTWORD_PRIVATE_LIB:=private/libkukui_scp_google_hotword_dsp_api.a
-ifneq ($(wildcard $(HOTWORD_PRIVATE_LIB)),)
-LDFLAGS_EXTRA+=$(HOTWORD_PRIVATE_LIB)
-HAVE_PRIVATE_AUDIO_CODEC_WOV_LIBS:=y
-endif
+ifeq ($(CHIP_VARIANT),$(filter $(CHIP_VARIANT),mt8192 mt8195))
+CPPFLAGS+=-Ichip/$(CHIP)/rv32i_common -Ichip/$(CHIP)/$(CHIP_VARIANT)
+dirs-y+=chip/$(CHIP)/rv32i_common chip/$(CHIP)/$(CHIP_VARIANT)
+include chip/$(CHIP)/rv32i_common/build.mk
+# Each chip variant can provide specific build.mk if any
+include chip/$(CHIP)/$(CHIP_VARIANT)/build.mk
 endif
-
-# Optional chip modules
-chip-$(CONFIG_AUDIO_CODEC_WOV)+=audio_codec_wov.o
-chip-$(CONFIG_COMMON_TIMER)+=hrtimer.o
-chip-$(CONFIG_I2C)+=i2c.o
-chip-$(CONFIG_IPI)+=ipi.o ipi_table.o
-chip-$(CONFIG_SPI)+=spi.o
-chip-$(CONFIG_WATCHDOG)+=watchdog.o
diff --git a/chip/mt_scp/clock.c b/chip/mt_scp/clock.c
deleted file mode 100644
index a6f1883d31..0000000000
--- a/chip/mt_scp/clock.c
+++ /dev/null
@@ -1,374 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks, PLL and power settings */
-
-#include "clock.h"
-#include "clock_chip.h"
-#include "common.h"
-#include "console.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ## args)
-
-#define ULPOSC_DIV_MAX (1 << OSC_DIV_BITS)
-#define ULPOSC_CALI_MAX (1 << OSC_CALI_BITS)
-
-void clock_init(void)
-{
-	/* Set VREQ to HW mode */
-	SCP_CPU_VREQ = CPU_VREQ_HW_MODE;
-	SCP_SECURE_CTRL &= ~ENABLE_SPM_MASK_VREQ;
-
-	/* Set DDREN auto mode */
-	SCP_SYS_CTRL |= AUTO_DDREN;
-
-	/* Initialize 26MHz system clock counter reset value to 1. */
-	SCP_CLK_SYS_VAL =
-		(SCP_CLK_SYS_VAL & ~CLK_SYS_VAL_MASK) | CLK_SYS_VAL(1);
-	/* Initialize high frequency ULPOSC counter reset value to 1. */
-	SCP_CLK_HIGH_VAL =
-		(SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) | CLK_HIGH_VAL(1);
-	/* Initialize sleep mode control VREQ counter. */
-	SCP_CLK_SLEEP_CTRL =
-		(SCP_CLK_SLEEP_CTRL & ~VREQ_COUNTER_MASK) | VREQ_COUNTER_VAL(1);
-
-	/* Set normal wake clock */
-	SCP_WAKE_CKSW &= ~WAKE_CKSW_SEL_NORMAL_MASK;
-
-	/* Enable fast wakeup support */
-	SCP_CLK_SLEEP = 0;
-	SCP_CLK_ON_CTRL = (SCP_CLK_ON_CTRL & ~HIGH_FINAL_VAL_MASK) |
-			  HIGH_FINAL_VAL_DEFAULT;
-	SCP_FAST_WAKE_CNT_END =
-		(SCP_FAST_WAKE_CNT_END & ~FAST_WAKE_CNT_END_MASK) |
-		FAST_WAKE_CNT_END_DEFAULT;
-
-	/* Set slow wake clock */
-	SCP_WAKE_CKSW = (SCP_WAKE_CKSW & ~WAKE_CKSW_SEL_SLOW_MASK) |
-			WAKE_CKSW_SEL_SLOW_DEFAULT;
-
-	/* Select CLK_HIGH as wakeup clock */
-	SCP_CLK_SLOW_SEL = (SCP_CLK_SLOW_SEL &
-			    ~(CKSW_SEL_SLOW_MASK | CKSW_SEL_SLOW_DIV_MASK)) |
-			   CKSW_SEL_SLOW_ULPOSC2_CLK;
-
-	/*
-	 * Set legacy wakeup
-	 *   - disable SPM sleep control
-	 *   - disable SCP sleep mode
-	 */
-	SCP_CLK_SLEEP_CTRL &= ~(EN_SLEEP_CTRL | SPM_SLEEP_MODE);
-
-	task_enable_irq(SCP_IRQ_CLOCK);
-	task_enable_irq(SCP_IRQ_CLOCK2);
-}
-
-static void scp_ulposc_config(int osc, uint32_t osc_div, uint32_t osc_cali)
-{
-	uint32_t val;
-
-	/* Clear all bits */
-	val = 0;
-	/* Enable CP */
-	val |= OSC_CP_EN;
-	/* Set div */
-	val |= osc_div << 17;
-	/* F-band = 0, I-band = 4 */
-	val |= 4 << 6;
-	/* Set calibration */
-	val |= osc_cali;
-	/* Set control register 1 */
-	AP_ULPOSC_CON02(osc) = val;
-	/* Set control register 2, enable div2 */
-	AP_ULPOSC_CON13(osc) |= OSC_DIV2_EN;
-}
-
-static inline void busy_udelay(int usec)
-{
-	/*
-	 * Delaying by busy-looping, for place that can't use udelay because of
-	 * the clock not configured yet. The value 28 is chosen approximately
-	 * from experiment.
-	 */
-	volatile int i = usec * 28;
-
-	while (i--)
-		;
-}
-
-static unsigned int scp_measure_ulposc_freq(int osc)
-{
-	unsigned int result = 0;
-	int cnt;
-
-	/* Before select meter clock input, bit[1:0] = b00 */
-	AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_MODE_MASK) |
-			 DBG_MODE_SET_CLOCK;
-
-	/* Select source, bit[21:16] = clk_src */
-	AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_BIST_SOURCE_MASK) |
-			 (osc == 0 ? DBG_BIST_SOURCE_ULPOSC1 :
-				     DBG_BIST_SOURCE_ULPOSC2);
-
-	/* Set meter divisor to 1, bit[31:24] = b00000000 */
-	AP_CLK_MISC_CFG_0 = (AP_CLK_MISC_CFG_0 & ~MISC_METER_DIVISOR_MASK) |
-			    MISC_METER_DIV_1;
-
-	/* Enable frequency meter, without start */
-	AP_SCP_CFG_0 |= CFG_FREQ_METER_ENABLE;
-
-	/* Trigger frequency meter start */
-	AP_SCP_CFG_0 |= CFG_FREQ_METER_RUN;
-
-	/*
-	 * Frequency meter counts cycles in 1 / (26 * 1024) second period.
-	 *   freq_in_hz = freq_counter * 26 * 1024
-	 *
-	 * The hardware takes 38us to count cycles. Delay up to 100us,
-	 * as busy_udelay may not be accurate when sysclk is not 26Mhz
-	 * (e.g. when recalibrating/measuring after boot).
-	 */
-	for (cnt = 100; cnt; cnt--) {
-		busy_udelay(1);
-		if (!(AP_SCP_CFG_0 & CFG_FREQ_METER_RUN)) {
-			result = CFG_FREQ_COUNTER(AP_SCP_CFG_1);
-			break;
-		}
-	}
-
-	/* Disable freq meter */
-	AP_SCP_CFG_0 &= ~CFG_FREQ_METER_ENABLE;
-	return result;
-}
-
-static inline int signum(int v)
-{
-	return (v > 0) - (v < 0);
-}
-
-static inline int abs(int v)
-{
-	return (v >= 0) ? v : -v;
-}
-
-static int scp_ulposc_config_measure(int osc, int div, int cali)
-{
-	int freq;
-
-	scp_ulposc_config(osc, div, cali);
-	freq = scp_measure_ulposc_freq(osc);
-	CPRINTF("ULPOSC%d: %d %d %d (%dkHz)\n",
-		osc + 1, div, cali, freq,
-		freq * 26 * 1000 / 1024);
-
-	return freq;
-}
-
-/**
- * Calibrate ULPOSC to target frequency.
- *
- * @param osc           0:ULPOSC1, 1:ULPOSC2
- * @param target_mhz    Target frequency to set
- * @return              Frequency counter output
- *
- */
-static int scp_calibrate_ulposc(int osc, int target_mhz)
-{
-	int target_freq = DIV_ROUND_NEAREST(target_mhz * 1024, 26);
-	struct ulposc {
-		int div;        /* frequency divisor/multiplier */
-		int cali;       /* variable resistor calibrator */
-		int freq;       /* frequency counter measure result */
-	} curr, prev = {0};
-	enum { STAGE_DIV, STAGE_CALI } stage = STAGE_DIV;
-	int param, param_max;
-
-	curr.div = ULPOSC_DIV_MAX / 2;
-	curr.cali = ULPOSC_CALI_MAX / 2;
-
-	param = curr.div;
-	param_max = ULPOSC_DIV_MAX;
-
-	/*
-	 * In the loop below, linear search closest div value to get desired
-	 * frequency counter value. Then adjust cali to get a better result.
-	 * Note that this doesn't give optimal output frequency, but it's
-	 * usually close enough.
-	 * TODO(b:120176040): See if we can efficiently calibrate the clock with
-	 * more precision by exploring more of the cali/div space.
-	 *
-	 * The frequency function follows. Note that f is positively correlated
-	 * with both div and cali:
-	 * f(div, cali) = k1 * (div + k2) / R(cali) * C
-	 * Where:
-	 *   R(cali) = k3 / (1 + k4 * (cali - k4))
-	 */
-	while (1) {
-		curr.freq = scp_ulposc_config_measure(osc, curr.div, curr.cali);
-
-		if (!curr.freq)
-			return 0;
-
-		/*
-		 * If previous and current are on either side of the desired
-		 * frequency, pick the closest one.
-		 */
-		if (prev.freq && signum(target_freq - curr.freq) !=
-				 signum(target_freq - prev.freq)) {
-			if (abs(target_freq - prev.freq) <
-					abs(target_freq - curr.freq))
-				curr = prev;
-
-			if (stage == STAGE_CALI)
-				break;
-
-			/* Switch to optimizing cali */
-			stage = STAGE_CALI;
-			param = curr.cali;
-			param_max = ULPOSC_CALI_MAX;
-		}
-
-		prev = curr;
-		param += signum(target_freq - curr.freq);
-
-		if (param < 0 || param >= param_max)
-			return 0;
-
-		if (stage == STAGE_DIV)
-			curr.div = param;
-		else
-			curr.cali = param;
-	}
-
-	/*
-	 * It's possible we end up using prev, so reset the configuration and
-	 * measure again.
-	 */
-	return scp_ulposc_config_measure(osc, curr.div, curr.cali);
-}
-
-static void scp_clock_high_enable(int osc)
-{
-	/* Enable high speed clock */
-	SCP_CLK_EN |= EN_CLK_HIGH;
-
-	switch (osc) {
-	case 0:
-		/* After 25ms, enable ULPOSC */
-		busy_udelay(25 * MSEC);
-		SCP_CLK_EN |= CG_CLK_HIGH;
-		break;
-	case 1:
-		/* Turn off ULPOSC2 high-core-disable switch */
-		SCP_CLK_ON_CTRL &= ~HIGH_CORE_DIS_SUB;
-		/* After 25ms, turn on ULPOSC2 high core clock gate */
-		busy_udelay(25 * MSEC);
-		SCP_CLK_HIGH_CORE |= CLK_HIGH_CORE_CG;
-		break;
-	default:
-		break;
-	}
-}
-
-void scp_use_clock(enum scp_clock_source src)
-{
-	/*
-	 * DIV2 divider takes precedence over clock selection to prevent
-	 * over-clocking.
-	 */
-	if (src == SCP_CLK_ULPOSC1)
-		SCP_CLK_DIV_SEL = CLK_DIV2;
-
-	SCP_CLK_SEL = src;
-
-	if (src != SCP_CLK_ULPOSC1)
-		SCP_CLK_DIV_SEL = CLK_DIV1;
-}
-
-void scp_enable_clock(void)
-{
-	/* Select default CPU clock */
-	scp_use_clock(SCP_CLK_26M);
-
-	/* VREQ */
-	SCP_CPU_VREQ = 0x10001;
-	SCP_SECURE_CTRL &= ~ENABLE_SPM_MASK_VREQ;
-
-	/* DDREN auto mode */
-	SCP_SYS_CTRL |= AUTO_DDREN;
-
-	/* Set settle time */
-	SCP_CLK_SYS_VAL = 1;  /* System clock */
-	SCP_CLK_HIGH_VAL = 1; /* ULPOSC */
-	SCP_CLK_SLEEP_CTRL = (SCP_CLK_SLEEP_CTRL & ~VREQ_COUNTER_MASK) | 2;
-
-	/* Disable slow wake */
-	SCP_CLK_SLEEP = SLOW_WAKE_DISABLE;
-	/* Disable SPM sleep control, disable sleep mode */
-	SCP_CLK_SLEEP_CTRL &= ~(SPM_SLEEP_MODE | EN_SLEEP_CTRL);
-
-	/* Turn off ULPOSC2 */
-	SCP_CLK_ON_CTRL |= HIGH_CORE_DIS_SUB;
-	scp_ulposc_config(0, 12, 32);
-	scp_clock_high_enable(0); /* Turn on ULPOSC1 */
-	scp_ulposc_config(1, 16, 32);
-	scp_clock_high_enable(1); /* Turn on ULPOSC2 */
-
-	/* Calibrate ULPOSC */
-	scp_calibrate_ulposc(0, ULPOSC1_CLOCK_MHZ);
-	scp_calibrate_ulposc(1, ULPOSC2_CLOCK_MHZ);
-
-	/* Select ULPOSC2 high speed CPU clock */
-	scp_use_clock(SCP_CLK_ULPOSC2);
-
-	/* Enable default clock gate */
-	SCP_CLK_GATE |= CG_DMA_CH3 | CG_DMA_CH2 | CG_DMA_CH1 | CG_DMA_CH0 |
-			CG_I2C_M | CG_MAD_M | CG_AP2P_M;
-
-	/* Select pwrap_ulposc */
-	AP_CLK_CFG_5 = (AP_CLK_CFG_5 & ~PWRAP_ULPOSC_MASK) | OSC_D16;
-
-	/* Enable pwrap_ulposc clock gate */
-	AP_CLK_CFG_5_CLR = PWRAP_ULPOSC_CG;
-}
-
-void clock_control_irq(void)
-{
-	/* Read ack CLK_IRQ */
-	(SCP_CLK_IRQ_ACK);
-	task_clear_pending_irq(SCP_IRQ_CLOCK);
-}
-DECLARE_IRQ(SCP_IRQ_CLOCK, clock_control_irq, 3);
-
-void clock_fast_wakeup_irq(void)
-{
-	/* Ack fast wakeup */
-	SCP_SLEEP_IRQ2 = 1;
-	task_clear_pending_irq(SCP_IRQ_CLOCK2);
-}
-DECLARE_IRQ(SCP_IRQ_CLOCK2, clock_fast_wakeup_irq, 3);
-
-/* Console command */
-int command_ulposc(int argc, char *argv[])
-{
-	if (argc > 1 && !strncmp(argv[1], "cal", 3)) {
-		scp_calibrate_ulposc(0, ULPOSC1_CLOCK_MHZ);
-		scp_calibrate_ulposc(1, ULPOSC2_CLOCK_MHZ);
-	}
-
-	/* SCP clock meter counts every (26MHz / 1024) tick */
-	ccprintf("ULPOSC1 frequency: %u kHz\n",
-		 scp_measure_ulposc_freq(0) * 26 * 1000 / 1024);
-	ccprintf("ULPOSC2 frequency: %u kHz\n",
-		 scp_measure_ulposc_freq(1) * 26 * 1000 / 1024);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(ulposc, command_ulposc, "[calibrate]",
-			"Calibrate ULPOSC frequency");
diff --git a/chip/mt_scp/clock_chip.h b/chip/mt_scp/clock_chip.h
deleted file mode 100644
index a16bf2e54e..0000000000
--- a/chip/mt_scp/clock_chip.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks, PLL and power settings */
-
-#ifndef __CROS_EC_CLOCK_CHIP_H
-#define __CROS_EC_CLOCK_CHIP_H
-
-#include "common.h"
-#include "registers.h"
-
-/* Default ULPOSC clock speed in MHz */
-#ifndef ULPOSC1_CLOCK_MHZ
-#define ULPOSC1_CLOCK_MHZ 240
-#endif
-#ifndef ULPOSC2_CLOCK_MHZ
-#define ULPOSC2_CLOCK_MHZ 330
-#endif
-
-void scp_enable_clock(void);
-
-enum scp_clock_source {
-	SCP_CLK_26M = CLK_SEL_SYS_26M,
-	SCP_CLK_32K = CLK_SEL_32K,
-	SCP_CLK_ULPOSC2 = CLK_SEL_ULPOSC_2,
-	SCP_CLK_ULPOSC1 = CLK_SEL_ULPOSC_1,
-};
-
-/* Switches to use 'src' clock */
-void scp_use_clock(enum scp_clock_source src);
-
-#endif /* __CROS_EC_CLOCK_CHIP_H */
diff --git a/chip/mt_scp/config_chip.h b/chip/mt_scp/config_chip.h
index 89311cda38..65d529f8e9 100644
--- a/chip/mt_scp/config_chip.h
+++ b/chip/mt_scp/config_chip.h
@@ -1,64 +1,12 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#ifndef __CROS_EC_CONFIG_CHIP_H
-#define __CROS_EC_CONFIG_CHIP_H
+#if defined(CHIP_VARIANT_MT8183) || defined(CHIP_VARIANT_MT8186)
+#include "mt818x/config_chip.h"
+#endif
 
-#include "core/cortex-m/config_core.h"
-
-/* Interval between HOOK_TICK notifications */
-#define HOOK_TICK_INTERVAL_MS 500
-#define HOOK_TICK_INTERVAL    (HOOK_TICK_INTERVAL_MS * MSEC)
-
-/* Default to UART 2 (AP UART) for EC console */
-#define CONFIG_UART_CONSOLE 2
-
-/* Number of IRQ vectors */
-#define CONFIG_IRQ_COUNT 56
-
-/*
- * Number of EINT can be 0 ~ 160. Change this to conditional macro
- * on adding other variants.
- */
-#define MAX_NUM_EINT 8
-#define MAX_EINT_PORT (MAX_NUM_EINT / 32)
-
-/* RW only, no flash */
-#undef  CONFIG_FW_INCLUDE_RO
-#define CONFIG_RO_MEM_OFF 0
-#define CONFIG_RO_SIZE 0
-#define CONFIG_RW_MEM_OFF 0
-#define CONFIG_RW_SIZE 0x40000 /* 256KB */
-#define CONFIG_EC_WRITABLE_STORAGE_OFF 0
-#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
-#define CONFIG_RO_STORAGE_OFF 0
-#define CONFIG_RW_STORAGE_OFF 0
-#define CONFIG_PROGRAM_MEMORY_BASE 0
-#define CONFIG_MAPPED_STORAGE_BASE 0
-/* Enable MPU to protect code RAM from writing, and data RAM from execution.*/
-#define CONFIG_MPU
-
-/* Unsupported features/commands */
-#undef CONFIG_CMD_FLASHINFO
-#undef CONFIG_CMD_POWER_AP
-#undef CONFIG_FLASH
-#undef CONFIG_FLASH_PHYSICAL
-#undef CONFIG_FMAP
-#undef CONFIG_HIBERNATE
-
-/* Task stack size */
-#define CONFIG_STACK_SIZE 1024
-#define IDLE_TASK_STACK_SIZE 256
-#define SMALLER_TASK_STACK_SIZE 384
-#define TASK_STACK_SIZE 512
-#define LARGER_TASK_STACK_SIZE 640
-#define VENTI_TASK_STACK_SIZE 768
-
-#define CONFIG_CHIP_PRE_INIT
-
-#define GPIO_PIN(num) ((num) / 32), ((num) % 32)
-#define GPIO_PIN_MASK(p, m) .port = (p), .mask = (m)
-
-#endif /* __CROS_EC_CONFIG_CHIP_H */
+#if defined(CHIP_VARIANT_MT8192) || defined(CHIP_VARIANT_MT8195)
+#include "rv32i_common/config_chip.h"
+#endif
diff --git a/chip/mt_scp/gpio.c b/chip/mt_scp/gpio.c
deleted file mode 100644
index a4896aae72..0000000000
--- a/chip/mt_scp/gpio.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GPIO module */
-
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-
-void gpio_set_alternate_function(uint32_t port, uint32_t mask,
-				enum gpio_alternate_func func)
-{
-	int bit, mode_reg_index, shift;
-	uint32_t mode_bits, mode_mask;
-
-	/* Up to 8 alt functions per port */
-	if (func > GPIO_ALT_FUNC_7)
-		return;
-
-	if (func == GPIO_ALT_FUNC_NONE)
-		func = GPIO_ALT_FUNC_DEFAULT;
-
-	while (mask) {
-		/* 32 gpio per port */
-		bit = get_next_bit(&mask);
-		/* 8 gpio per mode reg */
-		mode_reg_index = (port << 2) | (bit >> 3);
-		/*
-		 * b[3]   - write enable(?)
-		 * b[2:0] - mode
-		 */
-		shift = (bit & 7) << 2;
-		mode_bits = func << shift;
-		mode_mask = ~(0xf << shift);
-		AP_GPIO_MODE(mode_reg_index) = (AP_GPIO_MODE(mode_reg_index) &
-						mode_mask) | mode_bits;
-	}
-}
-
-test_mockable int gpio_get_level(enum gpio_signal signal)
-{
-	return !!(AP_GPIO_DIN(gpio_list[signal].port) &
-		  gpio_list[signal].mask);
-}
-
-
-void gpio_set_level(enum gpio_signal signal, int value)
-{
-	if (value)
-		AP_GPIO_DOUT(gpio_list[signal].port) |= gpio_list[signal].mask;
-	else
-		AP_GPIO_DOUT(gpio_list[signal].port) &= ~gpio_list[signal].mask;
-}
-
-void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
-{
-	/* Set input/output mode */
-	if (flags & GPIO_OUTPUT) {
-		/* Set level before changing to output mode */
-		if (flags & GPIO_HIGH)
-			AP_GPIO_DOUT(port) |= mask;
-		if (flags & GPIO_LOW)
-			AP_GPIO_DOUT(port) &= ~mask;
-		AP_GPIO_DIR(port) |= mask;
-	} else {
-		AP_GPIO_DIR(port) &= ~mask;
-	}
-
-	if (flags & (GPIO_INT_F_RISING | GPIO_INT_F_HIGH))
-		SCP_EINT_POLARITY_SET[port] = mask;
-
-	if (flags & (GPIO_INT_F_FALLING | GPIO_INT_F_LOW))
-		SCP_EINT_POLARITY_CLR[port] = mask;
-	else
-		SCP_EINT_POLARITY_SET[port] = mask;
-
-	/* Set sensitivity register on edge trigger */
-	if (flags & (GPIO_INT_F_RISING | GPIO_INT_F_FALLING))
-		SCP_EINT_SENS_SET[port] = mask;
-	else
-		SCP_EINT_SENS_CLR[port] = mask;
-}
-
-int gpio_get_flags_by_mask(uint32_t port, uint32_t mask)
-{
-	/* TODO(b/120167145): implement get flags */
-	return 0;
-}
-
-int gpio_enable_interrupt(enum gpio_signal signal)
-{
-	const struct gpio_info *g = gpio_list + signal;
-
-	if (signal >= GPIO_IH_COUNT || !g->mask)
-		return EC_ERROR_INVAL;
-
-	SCP_EINT_MASK_CLR[g->port] = g->mask;
-
-	return EC_SUCCESS;
-}
-
-int gpio_disable_interrupt(enum gpio_signal signal)
-{
-	const struct gpio_info *g = gpio_list + signal;
-
-	if (signal >= GPIO_IH_COUNT || !g->mask)
-		return EC_ERROR_INVAL;
-
-	SCP_EINT_MASK_SET[g->port] = g->mask;
-
-	return EC_SUCCESS;
-}
-
-int gpio_clear_pending_interrupt(enum gpio_signal signal)
-{
-	const struct gpio_info *g = gpio_list + signal;
-
-	if (signal >= GPIO_IH_COUNT || !g->mask)
-		return EC_ERROR_INVAL;
-
-	SCP_EINT_ACK[g->port] = g->mask;
-
-	return EC_SUCCESS;
-}
-
-void gpio_pre_init(void)
-{
-	const struct gpio_info *g = gpio_list;
-	int i;
-	int is_warm = system_is_reboot_warm();
-
-	for (i = 0; i < GPIO_COUNT; i++, g++) {
-		int flags = g->flags;
-
-		if (flags & GPIO_DEFAULT)
-			continue;
-
-		if (is_warm)
-			flags &= ~(GPIO_LOW | GPIO_HIGH);
-
-		gpio_set_flags_by_mask(g->port, g->mask, flags);
-	}
-}
-
-void gpio_init(void)
-{
-	/* Enable EINT IRQ */
-	task_enable_irq(SCP_IRQ_EINT);
-}
-DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
-
-/* Interrupt handler */
-void __keep gpio_interrupt(void)
-{
-	int bit, port;
-	uint32_t pending;
-	enum gpio_signal signal;
-
-	for (port = 0; port <= MAX_EINT_PORT; port++) {
-		pending = SCP_EINT_STATUS[port];
-
-		while (pending) {
-			bit = get_next_bit(&pending);
-			SCP_EINT_ACK[port] = BIT(bit);
-			/* Skip masked gpio */
-			if (SCP_EINT_MASK_GET[port] & BIT(bit))
-				continue;
-			/* Call handler */
-			signal = port * 32 + bit;
-			if (signal < GPIO_IH_COUNT)
-				gpio_irq_handlers[signal](signal);
-		}
-	}
-}
-DECLARE_IRQ(SCP_IRQ_EINT, gpio_interrupt, 1);
diff --git a/chip/mt_scp/hrtimer.c b/chip/mt_scp/hrtimer.c
deleted file mode 100644
index f970af6eb5..0000000000
--- a/chip/mt_scp/hrtimer.c
+++ /dev/null
@@ -1,253 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * High-res hardware timer
- *
- * SCP hardware 32bit count down timer can be configured to source clock from
- * 32KHz, 26MHz, BCLK or PCLK. This implementation selects BCLK (ULPOSC1/8) as a
- * source, countdown mode and converts to micro second value matching common
- * timer.
- */
-
-#include "clock.h"
-#include "clock_chip.h"
-#include "common.h"
-#include "console.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "panic.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "watchdog.h"
-
-#define IRQ_TIMER(n) CONCAT2(SCP_IRQ_TIMER, n)
-
-#define TIMER_SYSTEM 5
-#define TIMER_EVENT 3
-
-/* ULPOSC1 should be a multiple of 8. */
-BUILD_ASSERT((ULPOSC1_CLOCK_MHZ % 8) == 0);
-#define TIMER_CLOCK_MHZ (ULPOSC1_CLOCK_MHZ / 8)
-
-/* Common timer overflows at 0x100000000 micro seconds */
-#define OVERFLOW_TICKS (TIMER_CLOCK_MHZ * 0x100000000 - 1)
-
-static uint8_t sys_high;
-static uint8_t event_high;
-
-/* Convert hardware countdown timer to 64bit countup ticks */
-static inline uint64_t timer_read_raw_system(void)
-{
-	uint32_t timer_ctrl = SCP_TIMER_IRQ_CTRL(TIMER_SYSTEM);
-	uint32_t sys_high_adj = sys_high;
-
-	/*
-	 * If an IRQ is pending, but has not been serviced yet, adjust the
-	 * sys_high value.
-	 */
-	if (timer_ctrl & TIMER_IRQ_STATUS)
-		sys_high_adj = sys_high ? (sys_high - 1) : (TIMER_CLOCK_MHZ-1);
-
-	return OVERFLOW_TICKS - (((uint64_t)sys_high_adj << 32) |
-				 SCP_TIMER_VAL(TIMER_SYSTEM));
-}
-
-static inline uint64_t timer_read_raw_event(void)
-{
-	return OVERFLOW_TICKS - (((uint64_t)event_high << 32) |
-				 SCP_TIMER_VAL(TIMER_EVENT));
-}
-
-static inline void timer_set_clock(int n, uint32_t clock_source)
-{
-	SCP_TIMER_EN(n) = (SCP_TIMER_EN(n) & ~TIMER_CLK_MASK) |
-			  clock_source;
-}
-
-static inline void timer_ack_irq(int n)
-{
-	SCP_TIMER_IRQ_CTRL(n) |= TIMER_IRQ_CLEAR;
-}
-
-/* Set hardware countdown value */
-static inline void timer_set_reset_value(int n, uint32_t reset_value)
-{
-	SCP_TIMER_RESET_VAL(n) = reset_value;
-}
-
-static void timer_reset(int n)
-{
-	__hw_timer_enable_clock(n, 0);
-	timer_ack_irq(n);
-	timer_set_reset_value(n, 0xffffffff);
-	timer_set_clock(n, TIMER_CLK_32K);
-}
-
-/* Reload a new 32bit countdown value */
-static void timer_reload(int n, uint32_t value)
-{
-	__hw_timer_enable_clock(n, 0);
-	timer_set_reset_value(n, value);
-	__hw_timer_enable_clock(n, 1);
-}
-
-static int timer_reload_event_high(void)
-{
-	if (event_high) {
-		if (SCP_TIMER_RESET_VAL(TIMER_EVENT) == 0xffffffff)
-			__hw_timer_enable_clock(TIMER_EVENT, 1);
-		else
-			timer_reload(TIMER_EVENT, 0xffffffff);
-		event_high--;
-		return 1;
-	}
-
-	/* Disable event timer clock when done. */
-	__hw_timer_enable_clock(TIMER_EVENT, 0);
-	return 0;
-}
-
-void __hw_clock_event_clear(void)
-{
-	__hw_timer_enable_clock(TIMER_EVENT, 0);
-	timer_set_reset_value(TIMER_EVENT, 0x0000c1ea4);
-	event_high = 0;
-}
-
-void __hw_clock_event_set(uint32_t deadline)
-{
-	uint64_t deadline_raw = (uint64_t)deadline * TIMER_CLOCK_MHZ;
-	uint64_t now_raw = timer_read_raw_system();
-	uint32_t event_deadline;
-
-	if (deadline_raw > now_raw) {
-		deadline_raw -= now_raw;
-		event_deadline = (uint32_t)deadline_raw;
-		event_high = deadline_raw >> 32;
-	} else {
-		event_deadline = 1;
-		event_high = 0;
-	}
-
-	if (event_deadline)
-		timer_reload(TIMER_EVENT, event_deadline);
-	else
-		timer_reload_event_high();
-}
-
-void __hw_timer_enable_clock(int n, int enable)
-{
-	if (enable) {
-		SCP_TIMER_IRQ_CTRL(n) |= 1;
-		SCP_TIMER_EN(n) |= 1;
-	} else {
-		SCP_TIMER_EN(n) &= ~1;
-		SCP_TIMER_IRQ_CTRL(n) &= ~1;
-	}
-}
-
-int __hw_clock_source_init(uint32_t start_t)
-{
-	int t;
-
-	/*
-	 * TODO(b/120169529): check clock tree to see if we need to turn on
-	 * MCLK and BCLK gate.
-	 */
-	SCP_CLK_GATE |= (CG_TIMER_M | CG_TIMER_B);
-
-	/* Reset all timer, select 32768Hz clock source */
-	for (t = 0; t < NUM_TIMERS; t++)
-		timer_reset(t);
-
-	/* Enable timer IRQ wake source */
-	SCP_INTC_IRQ_WAKEUP |= (1 << IRQ_TIMER(0)) | (1 << IRQ_TIMER(1)) |
-			       (1 << IRQ_TIMER(2)) | (1 << IRQ_TIMER(3)) |
-			       (1 << IRQ_TIMER(4)) | (1 << IRQ_TIMER(5));
-	/*
-	 * Timer configuration:
-	 *   OS TIMER    - count up @ 13MHz, 64bit value with latch.
-	 *   SYS TICK    - count down @ 26MHz
-	 *   EVENT TICK  - count down @ 26MHz
-	 */
-
-	/* Turn on OS TIMER, tick at 13MHz */
-	SCP_OSTIMER_CON |= 1;
-
-	/* System timestamp timer from BCLK (sourced from ULPOSC) */
-	SCP_CLK_BCLK = CLK_BCLK_SEL_ULPOSC1_DIV8;
-
-	timer_set_clock(TIMER_SYSTEM, TIMER_CLK_BCLK);
-	sys_high = TIMER_CLOCK_MHZ-1;
-	timer_set_reset_value(TIMER_SYSTEM, 0xffffffff);
-	__hw_timer_enable_clock(TIMER_SYSTEM, 1);
-	task_enable_irq(IRQ_TIMER(TIMER_SYSTEM));
-	/* Event tick timer */
-	timer_set_clock(TIMER_EVENT, TIMER_CLK_BCLK);
-	task_enable_irq(IRQ_TIMER(TIMER_EVENT));
-
-	return IRQ_TIMER(TIMER_SYSTEM);
-}
-
-uint32_t __hw_clock_source_read(void)
-{
-	return timer_read_raw_system() / TIMER_CLOCK_MHZ;
-}
-
-uint32_t __hw_clock_event_get(void)
-{
-	return (timer_read_raw_event() + timer_read_raw_system())
-			/ TIMER_CLOCK_MHZ;
-}
-
-static void __hw_clock_source_irq(int n)
-{
-	uint32_t timer_ctrl = SCP_TIMER_IRQ_CTRL(n);
-
-	/* Ack if we're hardware interrupt */
-	if (timer_ctrl & TIMER_IRQ_STATUS)
-		timer_ack_irq(n);
-
-	switch (n) {
-	case TIMER_EVENT:
-		if (timer_ctrl & TIMER_IRQ_STATUS) {
-			if (timer_reload_event_high())
-				return;
-		}
-		process_timers(0);
-		break;
-	case TIMER_SYSTEM:
-		/* If this is a hardware irq, check overflow */
-		if (timer_ctrl & TIMER_IRQ_STATUS) {
-			if (sys_high) {
-				sys_high--;
-				process_timers(0);
-			} else {
-				/* Overflow, reload system timer */
-				sys_high = TIMER_CLOCK_MHZ-1;
-				process_timers(1);
-			}
-		} else {
-			process_timers(0);
-		}
-		break;
-	default:
-		return;
-	}
-
-}
-
-#define DECLARE_TIMER_IRQ(n) \
-	void __hw_clock_source_irq_##n(void) { __hw_clock_source_irq(n); } \
-	DECLARE_IRQ(IRQ_TIMER(n), __hw_clock_source_irq_##n, 2)
-
-DECLARE_TIMER_IRQ(0);
-DECLARE_TIMER_IRQ(1);
-DECLARE_TIMER_IRQ(2);
-DECLARE_TIMER_IRQ(3);
-DECLARE_TIMER_IRQ(4);
-DECLARE_TIMER_IRQ(5);
diff --git a/chip/mt_scp/ipi.c b/chip/mt_scp/ipi.c
deleted file mode 100644
index db371f02b4..0000000000
--- a/chip/mt_scp/ipi.c
+++ /dev/null
@@ -1,394 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Inter-Processor Communication (IPC) and Inter-Processor Interrupt (IPI)
- *
- * IPC is a communication bridge between AP and SCP.  AP/SCP sends an IPC
- * interrupt to SCP/AP to inform to collect the commmunication mesesages in the
- * shared buffer.
- *
- * There are 4 IPCs in the current architecture, from IPC0 to IPC3.  The
- * priority of IPC is proportional to its IPC index. IPC3 has the highest
- * priority and IPC0 has the lowest one.
- *
- * IPC0 may contain zero or more IPIs.  Each IPI represents a task or a service,
- * e.g. host command, or video encoding.  IPIs are recognized by IPI ID, which
- * should sync across AP and SCP.  Shared buffer should designated which IPI
- * ID it talks to.
- *
- * Currently, we don't have IPC handlers for IPC1, IPC2, and IPC3.
- */
-
-#include "clock_chip.h"
-#include "console.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "ipi_chip.h"
-#include "mkbp_event.h"
-#include "power.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-#include "hwtimer.h"
-
-#define CPRINTF(format, args...) cprintf(CC_IPI, format, ##args)
-#define CPRINTS(format, args...) cprints(CC_IPI, format, ##args)
-
-#define IPI_MAX_REQUEST_SIZE CONFIG_IPC_SHARED_OBJ_BUF_SIZE
-/* Reserve 1 extra byte for HOSTCMD_TYPE and 3 bytes for padding. */
-#define IPI_MAX_RESPONSE_SIZE (CONFIG_IPC_SHARED_OBJ_BUF_SIZE - 4)
-#define HOSTCMD_TYPE_HOSTCMD 1
-#define HOSTCMD_TYPE_HOSTEVENT 2
-
-static volatile int16_t ipc0_enabled_count;
-static struct mutex ipc0_lock;
-static struct mutex ipi_lock;
-/* IPC0 shared objects, including send object and receive object. */
-static struct ipc_shared_obj *const scp_send_obj =
-	(struct ipc_shared_obj *)CONFIG_IPC_SHARED_OBJ_ADDR;
-static struct ipc_shared_obj *const scp_recv_obj =
-	(struct ipc_shared_obj *)(CONFIG_IPC_SHARED_OBJ_ADDR +
-				  sizeof(struct ipc_shared_obj));
-static char ipi_ready;
-
-#ifdef HAS_TASK_HOSTCMD
-/*
- * hostcmd and hostevent share the same IPI ID, and use first byte type to
- * indicate its type.
- */
-static struct hostcmd_data {
-	const uint8_t type;
-	/* To be compatible with CONFIG_HOSTCMD_ALIGNED */
-	uint8_t response[IPI_MAX_RESPONSE_SIZE] __aligned(4);
-} hc_cmd_obj = { .type = HOSTCMD_TYPE_HOSTCMD };
-BUILD_ASSERT(sizeof(struct hostcmd_data) == CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
-
-static struct host_packet ipi_packet;
-#endif
-
-/* Check if SCP to AP IPI is in use. */
-static inline int is_ipi_busy(void)
-{
-	return SCP_HOST_INT & IPC_SCP2HOST_BIT;
-}
-
-/* If IPI is declared as a wake-up source, wake AP up. */
-static inline void try_to_wakeup_ap(int32_t id)
-{
-#ifdef CONFIG_RPMSG_NAME_SERVICE
-	if (id == IPI_NS_SERVICE)
-		return;
-#endif
-
-	if (*ipi_wakeup_table[id])
-		SCP_SPM_INT = SPM_INT_A2SPM;
-}
-
-void ipi_disable_irq(int irq)
-{
-	/* Only support SCP_IRQ_IPC0 for now. */
-	if (irq != SCP_IRQ_IPC0)
-		return;
-
-	mutex_lock(&ipc0_lock);
-
-	if ((--ipc0_enabled_count) == 0)
-		task_disable_irq(irq);
-
-	mutex_unlock(&ipc0_lock);
-}
-
-void ipi_enable_irq(int irq)
-{
-	/* Only support SCP_IRQ_IPC0 for now. */
-	if (irq != SCP_IRQ_IPC0)
-		return;
-
-	mutex_lock(&ipc0_lock);
-
-	if ((++ipc0_enabled_count) == 1) {
-		int pending_ipc = SCP_GIPC_IN & SCP_GPIC_IN_CLEAR_ALL;
-
-		task_enable_irq(irq);
-
-		if (ipi_ready && pending_ipc)
-			/*
-			 * IPC may be triggered while SCP_IRQ_IPC0 was disabled.
-			 * AP will still updates SCP_GIPC_IN.
-			 * Trigger the IRQ handler if it has a
-			 * pending IPC.
-			 */
-			task_trigger_irq(irq);
-	}
-
-	mutex_unlock(&ipc0_lock);
-}
-
-__override void
-power_chipset_handle_host_sleep_event(enum host_sleep_event state,
-				      struct host_sleep_event_context *ctx)
-{
-	int i;
-	const task_id_t s3_suspend_tasks[] = {
-#ifndef S3_SUSPEND_TASK_LIST
-#define S3_SUSPEND_TASK_LIST
-#endif
-#define TASK(n, ...) TASK_ID_##n,
-		S3_SUSPEND_TASK_LIST
-	};
-
-	if (state == HOST_SLEEP_EVENT_S3_SUSPEND) {
-		ccprints("AP suspend");
-		/*
-		 * On AP suspend, Vcore is 0.6V, and we should not use ULPOSC2,
-		 * which needs at least 0.7V.  Switch to ULPOSC1 instead.
-		 */
-		scp_use_clock(SCP_CLK_ULPOSC1);
-
-		for (i = 0; i < ARRAY_SIZE(s3_suspend_tasks); ++i)
-			task_disable_task(s3_suspend_tasks[i]);
-	} else if (state == HOST_SLEEP_EVENT_S3_RESUME) {
-		ccprints("AP resume");
-		/* Vcore is raised to >=0.7V, switch back to ULPSOC2 */
-		scp_use_clock(SCP_CLK_ULPOSC2);
-
-		for (i = 0; i < ARRAY_SIZE(s3_suspend_tasks); ++i)
-			task_enable_task(s3_suspend_tasks[i]);
-	}
-}
-
-/* Send data from SCP to AP. */
-int ipi_send(int32_t id, const void *buf, uint32_t len, int wait)
-{
-	if (!ipi_ready)
-		return EC_ERROR_BUSY;
-
-	/* TODO(b:117917141): Remove this check completely. */
-	if (in_interrupt_context()) {
-		CPRINTS("Err: invoke %s() in ISR CTX", __func__);
-		return EC_ERROR_BUSY;
-	}
-
-	if (len > sizeof(scp_send_obj->buffer))
-		return EC_ERROR_INVAL;
-
-	ipi_disable_irq(SCP_IRQ_IPC0);
-	mutex_lock(&ipi_lock);
-
-	/* Check if there is already an IPI pending in AP. */
-	if (is_ipi_busy()) {
-		/*
-		 * If the following conditions meet,
-		 *   1) There is an IPI pending in AP.
-		 *   2) The incoming IPI is a wakeup IPI.
-		 * then it assumes that AP is in suspend state.
-		 * Send a AP wakeup request to SPM.
-		 *
-		 * The incoming IPI will be checked if it's a wakeup source.
-		 */
-		try_to_wakeup_ap(id);
-
-		mutex_unlock(&ipi_lock);
-		ipi_enable_irq(SCP_IRQ_IPC0);
-		CPRINTS("Err: IPI Busy, %d", id);
-
-		return EC_ERROR_BUSY;
-	}
-
-
-	scp_send_obj->id = id;
-	scp_send_obj->len = len;
-	memcpy(scp_send_obj->buffer, buf, len);
-
-	/* Send IPI to AP: interrutp AP to receive IPI messages. */
-	try_to_wakeup_ap(id);
-	SCP_HOST_INT = IPC_SCP2HOST_BIT;
-
-	while (wait && is_ipi_busy())
-		;
-
-	mutex_unlock(&ipi_lock);
-	ipi_enable_irq(SCP_IRQ_IPC0);
-
-	return EC_SUCCESS;
-}
-
-static void ipi_handler(void)
-{
-	if (scp_recv_obj->id >= IPI_COUNT) {
-		CPRINTS("#ERR IPI %d", scp_recv_obj->id);
-		return;
-	}
-
-	/*
-	 * Only print IPI that is not host command channel, which will
-	 * be printed by host command driver.
-	 */
-	if (scp_recv_obj->id != IPI_HOST_COMMAND)
-		CPRINTS("IPI %d", scp_recv_obj->id);
-
-	/*
-	 * Pass the buffer to handler. Each handler should be in charge of
-	 * the buffer copying/reading before returning from handler.
-	 */
-	ipi_handler_table[scp_recv_obj->id](
-		scp_recv_obj->id, scp_recv_obj->buffer, scp_recv_obj->len);
-}
-
-void ipi_inform_ap(void)
-{
-	struct scp_run_t scp_run;
-	int ret;
-#ifdef CONFIG_RPMSG_NAME_SERVICE
-	struct rpmsg_ns_msg ns_msg;
-#endif
-
-	scp_run.signaled = 1;
-	strncpy(scp_run.fw_ver, system_get_version(EC_IMAGE_RW),
-		SCP_FW_VERSION_LEN);
-	scp_run.dec_capability = VCODEC_CAPABILITY_4K_DISABLED;
-	scp_run.enc_capability = 0;
-
-	ret = ipi_send(IPI_SCP_INIT, (void *)&scp_run, sizeof(scp_run), 1);
-
-	if (ret)
-		ccprintf("Failed to send initialization IPC messages.\n");
-
-#ifdef CONFIG_RPMSG_NAME_SERVICE
-	ns_msg.id = IPI_HOST_COMMAND;
-	strncpy(ns_msg.name, "cros-ec-rpmsg", RPMSG_NAME_SIZE);
-	ret = ipi_send(IPI_NS_SERVICE, &ns_msg, sizeof(ns_msg), 1);
-	if (ret)
-		ccprintf("Failed to announce host command channel.\n");
-#endif
-}
-
-#ifdef HAS_TASK_HOSTCMD
-#if defined(CONFIG_MKBP_USE_CUSTOM)
-int mkbp_set_host_active_via_custom(int active, uint32_t *timestamp)
-{
-	static const uint8_t hc_evt_obj = HOSTCMD_TYPE_HOSTEVENT;
-
-	/* This should be moved into ipi_send for more accuracy */
-	if (timestamp)
-		*timestamp = __hw_clock_source_read();
-
-	if (active)
-		return ipi_send(IPI_HOST_COMMAND, &hc_evt_obj,
-				sizeof(hc_evt_obj), 1);
-	return EC_SUCCESS;
-}
-#endif
-
-static void ipi_send_response_packet(struct host_packet *pkt)
-{
-	int ret;
-
-	ret = ipi_send(IPI_HOST_COMMAND, &hc_cmd_obj,
-		       pkt->response_size +
-			       offsetof(struct hostcmd_data, response),
-		       1);
-	if (ret)
-		CPRINTS("#ERR IPI HOSTCMD %d", ret);
-}
-
-static void ipi_hostcmd_handler(int32_t id, void *buf, uint32_t len)
-{
-	uint8_t *in_msg = buf;
-	struct ec_host_request *r = (struct ec_host_request *)in_msg;
-	int i;
-
-	if (in_msg[0] != EC_HOST_REQUEST_VERSION) {
-		CPRINTS("ERROR: Protocol V2 is not supported!");
-		CPRINTF("in_msg=[");
-		for (i = 0; i < len; i++)
-			CPRINTF("%02x ", in_msg[i]);
-		CPRINTF("]\n");
-		return;
-	}
-
-	/* Protocol version 3 */
-
-	ipi_packet.send_response = ipi_send_response_packet;
-
-	/*
-	 * Just assign the buffer to request, host_packet_receive
-	 * handles the buffer copy.
-	 */
-	ipi_packet.request = (void *)r;
-	ipi_packet.request_temp = NULL;
-	ipi_packet.request_max = IPI_MAX_REQUEST_SIZE;
-	ipi_packet.request_size = host_request_expected_size(r);
-
-	ipi_packet.response = hc_cmd_obj.response;
-	/* Reserve space for the preamble and trailing byte */
-	ipi_packet.response_max = IPI_MAX_RESPONSE_SIZE;
-	ipi_packet.response_size = 0;
-
-	ipi_packet.driver_result = EC_RES_SUCCESS;
-
-	host_packet_receive(&ipi_packet);
-}
-DECLARE_IPI(IPI_HOST_COMMAND, ipi_hostcmd_handler, 0);
-
-/*
- * Get protocol information
- */
-static enum ec_status ipi_get_protocol_info(struct host_cmd_handler_args *args)
-{
-	struct ec_response_get_protocol_info *r = args->response;
-
-	memset(r, 0, sizeof(*r));
-	r->protocol_versions |= BIT(3);
-	r->max_request_packet_size = IPI_MAX_REQUEST_SIZE;
-	r->max_response_packet_size = IPI_MAX_RESPONSE_SIZE;
-
-	args->response_size = sizeof(*r);
-
-	return EC_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, ipi_get_protocol_info,
-		     EC_VER_MASK(0));
-#endif
-
-static void ipi_enable_ipc0_deferred(void)
-{
-	/* Clear IPC0 IRQs. */
-	SCP_GIPC_IN = SCP_GPIC_IN_CLEAR_ALL;
-
-	/* All tasks are up, we can safely enable IPC0 IRQ now. */
-	SCP_INTC_IRQ_ENABLE |= IPC0_IRQ_EN;
-	ipi_enable_irq(SCP_IRQ_IPC0);
-
-	ipi_ready = 1;
-
-	/* Inform AP that SCP is inited.  */
-	ipi_inform_ap();
-
-	CPRINTS("ipi init");
-}
-DECLARE_DEFERRED(ipi_enable_ipc0_deferred);
-
-/* Initialize IPI. */
-static void ipi_init(void)
-{
-	/* Clear send share buffer. */
-	memset(scp_send_obj, 0, sizeof(struct ipc_shared_obj));
-
-	/* Enable IRQ after all tasks are up.  */
-	hook_call_deferred(&ipi_enable_ipc0_deferred_data, 0);
-}
-DECLARE_HOOK(HOOK_INIT, ipi_init, HOOK_PRIO_DEFAULT);
-
-void ipc_handler(void)
-{
-	/* TODO(b/117917141): We only support IPC_ID(0) for now. */
-	if (SCP_GIPC_IN & SCP_GIPC_IN_CLEAR_IPCN(0)) {
-		ipi_handler();
-		SCP_GIPC_IN &= SCP_GIPC_IN_CLEAR_IPCN(0);
-	}
-
-	SCP_GIPC_IN &= (SCP_GPIC_IN_CLEAR_ALL & ~SCP_GIPC_IN_CLEAR_IPCN(0));
-}
-DECLARE_IRQ(SCP_IRQ_IPC0, ipc_handler, 4);
diff --git a/chip/mt_scp/ipi_chip.h b/chip/mt_scp/ipi_chip.h
deleted file mode 100644
index 867a84c9f8..0000000000
--- a/chip/mt_scp/ipi_chip.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_IPI_CHIP_H
-#define __CROS_EC_IPI_CHIP_H
-
-#include "chip/mt_scp/registers.h"
-#include "common.h"
-
-#define IPC_MAX 1
-#define IPC_ID(n) (n)
-
-/*
- * Length of EC version string is at most 32 byte (NULL included), which
- * also aligns SCP fw_version length.
- */
-#define SCP_FW_VERSION_LEN 32
-
-/*
- * Video decoder supported capability:
- * BIT(4): 0 enable 4K
- *         1 disable 4K
- */
-#define VCODEC_CAPABILITY_4K_DISABLED BIT(4)
-
-#ifndef IPI_SCP_INIT
-#error If CONFIG_IPI is enabled, IPI_SCP_INIT must be defined.
-#endif
-
-/*
- * Share buffer layout for IPI_SCP_INIT response. This structure should sync
- * across kernel and EC.
- */
-struct scp_run_t {
-	uint32_t signaled;
-	int8_t fw_ver[SCP_FW_VERSION_LEN];
-	uint32_t dec_capability;
-	uint32_t enc_capability;
-};
-
-/*
- * The layout of the IPC0 AP/SCP shared buffer.
- * This should sync across kernel and EC.
- */
-struct ipc_shared_obj {
-	/* IPI ID */
-	int32_t id;
-	/* Length of the contents in buffer. */
-	uint32_t len;
-	/* Shared buffer contents. */
-	uint8_t buffer[CONFIG_IPC_SHARED_OBJ_BUF_SIZE];
-};
-
-/* Send a IPI contents to AP. This shouldn't be used in ISR context. */
-int ipi_send(int32_t id, const void *buf, uint32_t len, int wait);
-
-/* Size of the rpmsg device name, should sync across kernel and EC. */
-#define RPMSG_NAME_SIZE 32
-
-/*
- * The layout of name service message.
- * This should sync across kernel and EC.
- */
-struct rpmsg_ns_msg {
-	/* Name of the corresponding rpmsg_driver. */
-	char name[RPMSG_NAME_SIZE];
-	/* IPC ID */
-	uint32_t id;
-};
-
-/*
- * IPC Handler.
- */
-void ipc_handler(void);
-
-/*
- * An IPC IRQ could be shared across many IPI handlers.
- * Those handlers would usually operate on disabling or enabling the IPC IRQ.
- * This may disorder the actual timing to on/off the IRQ when there are many
- * tasks try to operate on it.  As a result, any access to the SCP_IRQ_*
- * should go through ipi_{en,dis}able_irq(), which support a counter to
- * enable/disable the IRQ at correct timeing.
- */
-/* Disable IPI IRQ. */
-void ipi_disable_irq(int irq);
-/* Enable IPI IRQ. */
-void ipi_enable_irq(int irq);
-
-/* IPI tables */
-extern void (*ipi_handler_table[])(int32_t, void *, uint32_t);
-extern int *ipi_wakeup_table[];
-
-/* Helper macros to build the IPI handler and wakeup functions. */
-#define IPI_HANDLER(id) CONCAT3(ipi_, id, _handler)
-#define IPI_WAKEUP(id) CONCAT3(ipi_, id, _wakeup)
-
-/*
- * Macro to declare an IPI handler.
- * _id: The ID of the IPI
- * handler: The IPI handler function
- * is_wakeup_src: Declare IPI ID as a wake-up source or not
- */
-#define DECLARE_IPI(_id, handler, is_wakeup_src) \
-	struct ipi_num_check##_id { \
-		int tmp1[_id < IPI_COUNT ? 1 : -1]; \
-		int tmp2[is_wakeup_src == 0 || is_wakeup_src == 1 ? 1 : -1]; \
-	};  \
-	void __keep IPI_HANDLER(_id)(int32_t id, void *buf, uint32_t len) \
-	{ \
-		handler(id, buf, len); \
-	} \
-	const int __keep IPI_WAKEUP(_id) = is_wakeup_src
-
-#endif /* __CROS_EC_IPI_CHIP_H */
diff --git a/chip/mt_scp/ipi_table.c b/chip/mt_scp/ipi_table.c
deleted file mode 100644
index 8569ab24a7..0000000000
--- a/chip/mt_scp/ipi_table.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * IPI handlers declaration
- */
-
-#include "common.h"
-#include "ipi_chip.h"
-
-typedef void (*ipi_handler_t)(int32_t id, void *data, uint32_t len);
-
-#ifndef PASS
-#define PASS 1
-#endif
-
-#define ipi_arguments int32_t id, void *data, uint32_t len
-
-#if PASS == 1
-void ipi_handler_undefined(ipi_arguments) { }
-
-const int ipi_wakeup_undefined;
-
-#define table(type, name, x) x
-
-#define ipi_x_func(suffix, args, number)                                       \
-	extern void __attribute__(                                             \
-		(used, weak, alias(STRINGIFY(ipi_##suffix##_undefined))))      \
-		ipi_##number##_##suffix(args);
-
-#define ipi_x_var(suffix, number)                                              \
-	extern int __attribute__(                                              \
-		(weak, alias(STRINGIFY(ipi_##suffix##_undefined))))            \
-		ipi_##number##_##suffix;
-
-#endif /* PASS == 1 */
-
-#if PASS == 2
-
-#undef table
-#undef ipi_x_func
-#undef ipi_x_var
-
-#define table(type, name, x)                                                   \
-	type name[] __aligned(4)                                               \
-		__attribute__((section(".rodata.ipi, \"a\" @"))) = {x}
-
-#define ipi_x_var(suffix, number)                                              \
-	[number < IPI_COUNT ? number : -1] = &ipi_##number##_##suffix,
-
-#define ipi_x_func(suffix, args, number) ipi_x_var(suffix, number)
-
-#endif /* PASS == 2 */
-
-/*
- * Include generated IPI table (by util/gen_ipi_table). The contents originate
- * from IPI_COUNT definition in board.h
- */
-#include "ipi_table_gen.inc"
-
-#if PASS == 1
-#undef PASS
-#define PASS 2
-#include "ipi_table.c"
-BUILD_ASSERT(ARRAY_SIZE(ipi_handler_table) == IPI_COUNT);
-BUILD_ASSERT(ARRAY_SIZE(ipi_wakeup_table) == IPI_COUNT);
-#endif
diff --git a/chip/mt_scp/memmap.c b/chip/mt_scp/memmap.c
deleted file mode 100644
index 6d8f2b0c87..0000000000
--- a/chip/mt_scp/memmap.c
+++ /dev/null
@@ -1,322 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * SCP memory map
- */
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "hooks.h"
-#include "memmap.h"
-#include "registers.h"
-#include "util.h"
-
-/*
- * Map SCP address (bits 31~28) to AP address
- *
- * SCP addr    :  AP addr
- * 0x20000000     0x40000000
- * 0x30000000     0x50000000
- * 0x60000000     0x60000000
- * 0x70000000     0x70000000
- * 0x80000000     0x80000000
- * 0x90000000     0x00000000
- * 0xA0000000     0x10000000
- * 0xB0000000     0x20000000
- * 0xC0000000     0x30000000
- * 0xD0000000     0x10000000
- * 0xE0000000     0xA0000000
- * 0xF0000000     0x90000000
- */
-
-#define MAP_INVALID 0xff
-
-static const uint8_t addr_map[16] = {
-	MAP_INVALID,			/* 0x0: SRAM */
-	MAP_INVALID,			/* 0x1: Cached access (see below) */
-	0x4, 0x5,			/* 0x2-0x3 */
-	MAP_INVALID, MAP_INVALID,	/* 0x4-0x5 (unmapped: registers) */
-	0x6, 0x7, 0x8,			/* 0x6-0x8 */
-	0x0, 0x1, 0x2, 0x3,		/* 0x9-0xc */
-	0x1, 0xa, 0x9			/* 0xd-0xf */
-};
-
-/*
- * AP addr     :  SCP cache addr
- * 0x50000000     0x10000000
- */
-#define CACHE_TRANS_AP_ADDR 0x50000000
-#define CACHE_TRANS_SCP_CACHE_ADDR 0x10000000
-/* FIXME: This should be configurable */
-#define CACHE_TRANS_AP_SIZE 0x00400000
-
-#ifdef CONFIG_DRAM_BASE
-BUILD_ASSERT(CONFIG_DRAM_BASE_LOAD == CACHE_TRANS_AP_ADDR);
-BUILD_ASSERT(CONFIG_DRAM_BASE == CACHE_TRANS_SCP_CACHE_ADDR);
-#endif
-
-static void cpu_invalidate_icache(void)
-{
-	SCP_CACHE_OP(CACHE_ICACHE) &= ~SCP_CACHE_OP_OP_MASK;
-	SCP_CACHE_OP(CACHE_ICACHE) |=
-		OP_INVALIDATE_ALL_LINES | SCP_CACHE_OP_EN;
-	asm volatile("dsb; isb");
-}
-
-void cpu_invalidate_dcache(void)
-{
-	SCP_CACHE_OP(CACHE_DCACHE) &= ~SCP_CACHE_OP_OP_MASK;
-	SCP_CACHE_OP(CACHE_DCACHE) |=
-		OP_INVALIDATE_ALL_LINES | SCP_CACHE_OP_EN;
-	/* Read is necessary to confirm the invalidation finish. */
-	REG32(CACHE_TRANS_SCP_CACHE_ADDR);
-	asm volatile("dsb;");
-}
-
-void cpu_invalidate_dcache_range(uintptr_t base, unsigned int length)
-{
-	size_t pos;
-	uintptr_t addr;
-
-	for (pos = 0; pos < length; pos += SCP_CACHE_LINE_SIZE) {
-		addr = base + pos;
-		SCP_CACHE_OP(CACHE_DCACHE) = addr & SCP_CACHE_OP_TADDR_MASK;
-		SCP_CACHE_OP(CACHE_DCACHE) |=
-			OP_INVALIDATE_ONE_LINE_BY_ADDRESS | SCP_CACHE_OP_EN;
-		/* Read necessary to confirm the invalidation finish. */
-		REG32(addr);
-	}
-	asm volatile("dsb;");
-}
-
-void cpu_clean_invalidate_dcache(void)
-{
-	SCP_CACHE_OP(CACHE_DCACHE) &= ~SCP_CACHE_OP_OP_MASK;
-	SCP_CACHE_OP(CACHE_DCACHE) |=
-		OP_CACHE_FLUSH_ALL_LINES | SCP_CACHE_OP_EN;
-	SCP_CACHE_OP(CACHE_DCACHE) &= ~SCP_CACHE_OP_OP_MASK;
-	SCP_CACHE_OP(CACHE_DCACHE) |=
-		OP_INVALIDATE_ALL_LINES | SCP_CACHE_OP_EN;
-	/* Read necessary to confirm the invalidation finish. */
-	REG32(CACHE_TRANS_SCP_CACHE_ADDR);
-	asm volatile("dsb;");
-}
-
-void cpu_clean_invalidate_dcache_range(uintptr_t base, unsigned int length)
-{
-	size_t pos;
-	uintptr_t addr;
-
-	for (pos = 0; pos < length; pos += SCP_CACHE_LINE_SIZE) {
-		addr = base + pos;
-		SCP_CACHE_OP(CACHE_DCACHE) = addr & SCP_CACHE_OP_TADDR_MASK;
-		SCP_CACHE_OP(CACHE_DCACHE) |=
-			OP_CACHE_FLUSH_ONE_LINE_BY_ADDRESS | SCP_CACHE_OP_EN;
-		SCP_CACHE_OP(CACHE_DCACHE) = addr & SCP_CACHE_OP_TADDR_MASK;
-		SCP_CACHE_OP(CACHE_DCACHE) |=
-			OP_INVALIDATE_ONE_LINE_BY_ADDRESS | SCP_CACHE_OP_EN;
-		/* Read necessary to confirm the invalidation finish. */
-		REG32(addr);
-	}
-	asm volatile("dsb;");
-}
-
-static void scp_cache_init(void)
-{
-	int c;
-	const int region = 0;
-
-	/* First make sure all caches are disabled, and reset stats. */
-	for (c = 0; c < CACHE_COUNT; c++) {
-		/*
-		 * Changing cache-size config may change the SRAM logical
-		 * address in the mean time.  This may break the loaded
-		 * memory layout, and thus break the system.  Cache-size
-		 * should only be be configured in kernel driver before
-		 * laoding the firmware. b/137920815#comment18
-		 */
-		SCP_CACHE_CON(c) &= (SCP_CACHE_CON_CACHESIZE_MASK |
-				     SCP_CACHE_CON_WAYEN);
-		SCP_CACHE_REGION_EN(c) = 0;
-		SCP_CACHE_ENTRY(c, region) = 0;
-		SCP_CACHE_END_ENTRY(c, region) = 0;
-
-		/* Reset statistics. */
-		SCP_CACHE_HCNT0U(c) = 0;
-		SCP_CACHE_HCNT0L(c) = 0;
-		SCP_CACHE_CCNT0U(c) = 0;
-		SCP_CACHE_CCNT0L(c) = 0;
-	}
-
-	/* No "normal" remap. */
-	SCP_L1_REMAP_CFG0 = 0;
-	SCP_L1_REMAP_CFG1 = 0;
-	SCP_L1_REMAP_CFG2 = 0;
-	SCP_L1_REMAP_CFG3 = 0;
-	/*
-	 * Setup OTHER1: Remap register for addr msb 31 to 28 equal to 0x1 and
-	 * not overlap with L1C_EXT_ADDR0 to L1C_EXT_ADDR7.
-	 */
-	SCP_L1_REMAP_OTHER =
-		(CACHE_TRANS_AP_ADDR >> SCP_L1_EXT_ADDR_OTHER_SHIFT) << 8;
-
-	/* Disable sleep protect */
-	SCP_SLP_PROTECT_CFG = SCP_SLP_PROTECT_CFG &
-		~(P_CACHE_SLP_PROT_EN | D_CACHE_SLP_PROT_EN);
-
-	/* Enable region 0 for both I-cache and D-cache. */
-	for (c = 0; c < CACHE_COUNT; c++) {
-		SCP_CACHE_ENTRY(c, region) = CACHE_TRANS_SCP_CACHE_ADDR;
-		SCP_CACHE_END_ENTRY(c, region) =
-			CACHE_TRANS_SCP_CACHE_ADDR + CACHE_TRANS_AP_SIZE;
-		SCP_CACHE_ENTRY(c, region) |= SCP_CACHE_ENTRY_C;
-
-		SCP_CACHE_REGION_EN(c) |= 1 << region;
-
-		/*
-		 * Enable cache. Note that cache size setting should have been
-		 * done in kernel driver. b/137920815#comment18
-		 */
-		SCP_CACHE_CON(c) |= SCP_CACHE_CON_MCEN | SCP_CACHE_CON_CNTEN0;
-	}
-
-	cpu_invalidate_icache();
-	cpu_invalidate_dcache();
-}
-
-static int command_cacheinfo(int argc, char **argv)
-{
-	const char cache_name[] = {'I', 'D'};
-	int c;
-
-	for (c = 0; c < 2; c++) {
-		uint64_t hit = ((uint64_t)SCP_CACHE_HCNT0U(c) << 32) |
-			SCP_CACHE_HCNT0L(c);
-		uint64_t access = ((uint64_t)SCP_CACHE_CCNT0U(c) << 32) |
-			SCP_CACHE_CCNT0L(c);
-
-		ccprintf("%ccache hit count:    %llu\n", cache_name[c], hit);
-		ccprintf("%ccache access count: %llu\n", cache_name[c], access);
-	}
-
-	return EC_SUCCESS;
-}
-DECLARE_SAFE_CONSOLE_COMMAND(cacheinfo, command_cacheinfo,
-			     NULL,
-			     "Dump cache info");
-
-void scp_memmap_init(void)
-{
-	/*
-	 * Default config, LARGE DRAM not active:
-	 *   REG32(0xA0001F00) & 0x2000 != 0
-	 */
-
-	/*
-	 * SCP_REMAP_CFG1
-	 * EXT_ADDR3[29:24] remap register for addr msb 31~28 equal to 0x7
-	 * EXT_ADDR2[21:16] remap register for addr msb 31~28 equal to 0x6
-	 * EXT_ADDR1[13:8]  remap register for addr msb 31~28 equal to 0x3
-	 * EXT_ADDR0[5:0]   remap register for addr msb 31~28 equal to 0x2
-	 */
-	SCP_REMAP_CFG1 =
-		(uint32_t)addr_map[0x7] << 24 |
-		(uint32_t)addr_map[0x6] << 16 |
-		(uint32_t)addr_map[0x3] << 8 |
-		(uint32_t)addr_map[0x2];
-
-	/*
-	 * SCP_REMAP_CFG2
-	 * EXT_ADDR7[29:24] remap register for addr msb 31~28 equal to 0xb
-	 * EXT_ADDR6[21:16] remap register for addr msb 31~28 equal to 0xa
-	 * EXT_ADDR5[13:8]  remap register for addr msb 31~28 equal to 0x9
-	 * EXT_ADDR4[5:0]   remap register for addr msb 31~28 equal to 0x8
-	 */
-	SCP_REMAP_CFG2 =
-		(uint32_t)addr_map[0xb] << 24 |
-		(uint32_t)addr_map[0xa] << 16 |
-		(uint32_t)addr_map[0x9] << 8 |
-		(uint32_t)addr_map[0x8];
-	/*
-	 * SCP_REMAP_CFG3
-	 * AUD_ADDR[31:28]  remap register for addr msb 31~28 equal to 0xd
-	 * EXT_ADDR10[21:16]remap register for addr msb 31~28 equal to 0xf
-	 * EXT_ADDR9[13:8]  remap register for addr msb 31~28 equal to 0xe
-	 * EXT_ADDR8[5:0]   remap register for addr msb 31~28 equal to 0xc
-	 */
-	SCP_REMAP_CFG3 =
-		(uint32_t)addr_map[0xd] << 28 |
-		(uint32_t)addr_map[0xf] << 16 |
-		(uint32_t)addr_map[0xe] << 8 |
-		(uint32_t)addr_map[0xc];
-
-	/* Initialize cache remapping. */
-	scp_cache_init();
-}
-
-int memmap_ap_to_scp(uintptr_t ap_addr, uintptr_t *scp_addr)
-{
-	int i;
-	uint8_t msb = ap_addr >> SCP_REMAP_ADDR_SHIFT;
-
-	for (i = 0; i < ARRAY_SIZE(addr_map); i++) {
-		if (addr_map[i] != msb)
-			continue;
-
-		*scp_addr = (ap_addr & SCP_REMAP_ADDR_LSB_MASK) |
-			(i << SCP_REMAP_ADDR_SHIFT);
-		return EC_SUCCESS;
-	}
-
-	return EC_ERROR_INVAL;
-}
-
-int memmap_scp_to_ap(uintptr_t scp_addr, uintptr_t *ap_addr)
-{
-	int i = scp_addr >> SCP_REMAP_ADDR_SHIFT;
-
-	if (addr_map[i] == MAP_INVALID)
-		return EC_ERROR_INVAL;
-
-	*ap_addr = (scp_addr & SCP_REMAP_ADDR_LSB_MASK) |
-		(addr_map[i] << SCP_REMAP_ADDR_SHIFT);
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_DRAM_BASE
-BUILD_ASSERT(CONFIG_DRAM_BASE_LOAD == CACHE_TRANS_AP_ADDR);
-BUILD_ASSERT(CONFIG_DRAM_BASE == CACHE_TRANS_SCP_CACHE_ADDR);
-#endif
-
-int memmap_ap_to_scp_cache(uintptr_t ap_addr, uintptr_t *scp_addr)
-{
-	uintptr_t lsb;
-
-	if ((ap_addr & SCP_L1_EXT_ADDR_OTHER_MSB_MASK) != CACHE_TRANS_AP_ADDR)
-		return EC_ERROR_INVAL;
-
-	lsb = ap_addr & SCP_L1_EXT_ADDR_OTHER_LSB_MASK;
-	if (lsb > CACHE_TRANS_AP_SIZE)
-		return EC_ERROR_INVAL;
-
-	*scp_addr = CACHE_TRANS_SCP_CACHE_ADDR | lsb;
-	return EC_SUCCESS;
-}
-
-int memmap_scp_cache_to_ap(uintptr_t scp_addr, uintptr_t *ap_addr)
-{
-	uintptr_t lsb;
-
-	if ((scp_addr & SCP_L1_EXT_ADDR_OTHER_MSB_MASK) !=
-			CACHE_TRANS_SCP_CACHE_ADDR)
-		return EC_ERROR_INVAL;
-
-	lsb = scp_addr & SCP_L1_EXT_ADDR_OTHER_LSB_MASK;
-	if (lsb >= CACHE_TRANS_AP_SIZE)
-		return EC_ERROR_INVAL;
-
-	*ap_addr = CACHE_TRANS_AP_ADDR | lsb;
-	return EC_SUCCESS;
-}
diff --git a/chip/mt_scp/memmap.h b/chip/mt_scp/memmap.h
deleted file mode 100644
index fbecb5e8cf..0000000000
--- a/chip/mt_scp/memmap.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * SCP memory map
- */
-
-#ifndef __CROS_EC_MEMMAP_H
-#define __CROS_EC_MEMMAP_H
-
-void scp_memmap_init(void);
-
-/**
- * Translate AP addr to SCP addr.
- *
- * @param ap_addr		AP address to translate
- * @param scp_addr		Tranlated AP address
- * @return			EC_SUCCESS or EC_ERROR_INVAL
- */
-int memmap_ap_to_scp(uintptr_t ap_addr, uintptr_t *scp_addr);
-
-/**
- * Translate SCP addr to AP addr.
- *
- * @param scp_addr		SCP address to tranlate
- * @param ap_addr		Translated SCP address
- * @return			EC_SUCCESS or EC_ERROR_INVAL
- */
-int memmap_scp_to_ap(uintptr_t scp_addr, uintptr_t *ap_addr);
-
-/**
- * Translate AP addr to SCP cache addr.
- *
- * @param ap_addr		AP address to translate
- * @param scp_addr		Tranlated AP cache address
- * @return			EC_SUCCESS or EC_ERROR_INVAL
- */
-int memmap_ap_to_scp_cache(uintptr_t ap_addr, uintptr_t *scp_addr);
-
-/**
- * Translate SCP addr to AP addr.
- *
- * @param scp_addr		SCP cache address to tranlate
- * @param ap_addr		Translated SCP cache address
- * @return			EC_SUCCESS or EC_ERROR_INVAL
- */
-int memmap_scp_cache_to_ap(uintptr_t scp_addr, uintptr_t *ap_addr);
-
-#endif /* #ifndef __CROS_EC_MEMMAP_H */
diff --git a/chip/mt_scp/audio_codec_wov.c b/chip/mt_scp/mt818x/audio_codec_wov.c
similarity index 95%
rename from chip/mt_scp/audio_codec_wov.c
rename to chip/mt_scp/mt818x/audio_codec_wov.c
index 0a4684f909..466494b53f 100644
--- a/chip/mt_scp/audio_codec_wov.c
+++ b/chip/mt_scp/mt818x/audio_codec_wov.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -79,7 +79,7 @@ int32_t audio_codec_wov_read(void *buf, uint32_t count)
 	while (count-- && wov_fifo_level()) {
 		if (IS_ENABLED(CONFIG_AUDIO_CODEC_DMIC_SOFTWARE_GAIN))
 			*out++ = audio_codec_s16_scale_and_clip(
-					SCP_VIF_FIFO_DATA, gain);
+				SCP_VIF_FIFO_DATA, gain);
 		else
 			*out++ = SCP_VIF_FIFO_DATA;
 	}
diff --git a/chip/mt_scp/mt818x/build.mk b/chip/mt_scp/mt818x/build.mk
new file mode 100644
index 0000000000..c44b2f0ebe
--- /dev/null
+++ b/chip/mt_scp/mt818x/build.mk
@@ -0,0 +1,36 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CORE:=cortex-m
+CFLAGS_CPU+=-mcpu=cortex-m4
+
+# Required chip modules
+chip-y+=mt818x/clock_$(CHIP_VARIANT).o
+chip-y+=mt818x/gpio.o
+chip-y+=mt818x/memmap.o
+chip-y+=mt818x/system.o
+chip-y+=mt818x/uart.o
+chip-y+=mt818x/video.o
+
+# Optional chip modules
+chip-$(CONFIG_AUDIO_CODEC_WOV)+=mt818x/audio_codec_wov.o
+chip-$(CONFIG_COMMON_TIMER)+=mt818x/hrtimer.o
+chip-$(CONFIG_I2C)+=mt818x/i2c.o
+chip-$(CONFIG_IPI)+=mt818x/ipi.o mt818x/ipi_table.o
+chip-$(CONFIG_SPI)+=mt818x/spi.o
+chip-$(CONFIG_WATCHDOG)+=mt818x/watchdog.o
+
+ifeq ($(CONFIG_IPI),y)
+$(out)/RO/chip/$(CHIP)/mt818x/ipi_table.o: $(out)/ipi_table_gen.inc
+$(out)/RW/chip/$(CHIP)/mt818x/ipi_table.o: $(out)/ipi_table_gen.inc
+endif
+
+ifeq ($(CONFIG_AUDIO_CODEC_WOV),y)
+HOTWORD_PRIVATE_LIB:=private/libkukui_scp_google_hotword_dsp_api.a
+ifneq ($(wildcard $(HOTWORD_PRIVATE_LIB)),)
+LDFLAGS_EXTRA+=$(HOTWORD_PRIVATE_LIB)
+HAVE_PRIVATE_AUDIO_CODEC_WOV_LIBS:=y
+endif
+endif
diff --git a/chip/mt_scp/mt818x/clock_chip.h b/chip/mt_scp/mt818x/clock_chip.h
new file mode 100644
index 0000000000..6568999176
--- /dev/null
+++ b/chip/mt_scp/mt818x/clock_chip.h
@@ -0,0 +1,33 @@
+/* Copyright 2019 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Clocks, PLL and power settings */
+
+#ifndef __CROS_EC_CLOCK_CHIP_H
+#define __CROS_EC_CLOCK_CHIP_H
+
+#include "common.h"
+#include "registers.h"
+
+/* Default ULPOSC clock speed in MHz */
+#ifndef ULPOSC1_CLOCK_MHZ
+#define ULPOSC1_CLOCK_MHZ 240
+#endif
+#ifndef ULPOSC2_CLOCK_MHZ
+#define ULPOSC2_CLOCK_MHZ 330
+#endif
+void scp_enable_clock(void);
+
+enum scp_clock_source {
+	SCP_CLK_26M = CLK_SEL_SYS_26M,
+	SCP_CLK_32K = CLK_SEL_32K,
+	SCP_CLK_ULPOSC2 = CLK_SEL_ULPOSC_2,
+	SCP_CLK_ULPOSC1 = CLK_SEL_ULPOSC_1,
+};
+
+/* Switches to use 'src' clock */
+void scp_use_clock(enum scp_clock_source src);
+
+#endif /* __CROS_EC_CLOCK_CHIP_H */
diff --git a/chip/mt_scp/mt818x/clock_mt8183.c b/chip/mt_scp/mt818x/clock_mt8183.c
new file mode 100644
index 0000000000..5c99d7b393
--- /dev/null
+++ b/chip/mt_scp/mt818x/clock_mt8183.c
@@ -0,0 +1,376 @@
+/* Copyright 2018 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Clocks, PLL and power settings */
+
+#include "clock.h"
+#include "clock_chip.h"
+#include "common.h"
+#include "console.h"
+#include "registers.h"
+#include "task.h"
+#include "timer.h"
+#include "util.h"
+
+#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ##args)
+
+#define ULPOSC_DIV_MAX (1 << OSC_DIV_BITS)
+#define ULPOSC_CALI_MAX (1 << OSC_CALI_BITS)
+
+void clock_init(void)
+{
+	/* Set VREQ to HW mode */
+	SCP_CPU_VREQ = CPU_VREQ_HW_MODE;
+	SCP_SECURE_CTRL &= ~ENABLE_SPM_MASK_VREQ;
+
+	/* Set DDREN auto mode */
+	SCP_SYS_CTRL |= AUTO_DDREN;
+
+	/* Initialize 26MHz system clock counter reset value to 1. */
+	SCP_CLK_SYS_VAL = (SCP_CLK_SYS_VAL & ~CLK_SYS_VAL_MASK) |
+			  CLK_SYS_VAL(1);
+	/* Initialize high frequency ULPOSC counter reset value to 1. */
+	SCP_CLK_HIGH_VAL = (SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) |
+			   CLK_HIGH_VAL(1);
+	/* Initialize sleep mode control VREQ counter. */
+	SCP_CLK_SLEEP_CTRL = (SCP_CLK_SLEEP_CTRL & ~VREQ_COUNTER_MASK) |
+			     VREQ_COUNTER_VAL(1);
+
+	/* Set normal wake clock */
+	SCP_WAKE_CKSW &= ~WAKE_CKSW_SEL_NORMAL_MASK;
+
+	/* Enable fast wakeup support */
+	SCP_CLK_SLEEP = 0;
+	SCP_CLK_ON_CTRL = (SCP_CLK_ON_CTRL & ~HIGH_FINAL_VAL_MASK) |
+			  HIGH_FINAL_VAL_DEFAULT;
+	SCP_FAST_WAKE_CNT_END =
+		(SCP_FAST_WAKE_CNT_END & ~FAST_WAKE_CNT_END_MASK) |
+		FAST_WAKE_CNT_END_DEFAULT;
+
+	/* Set slow wake clock */
+	SCP_WAKE_CKSW = (SCP_WAKE_CKSW & ~WAKE_CKSW_SEL_SLOW_MASK) |
+			WAKE_CKSW_SEL_SLOW_DEFAULT;
+
+	/* Select CLK_HIGH as wakeup clock */
+	SCP_CLK_SLOW_SEL = (SCP_CLK_SLOW_SEL &
+			    ~(CKSW_SEL_SLOW_MASK | CKSW_SEL_SLOW_DIV_MASK)) |
+			   CKSW_SEL_SLOW_ULPOSC2_CLK;
+
+	/*
+	 * Set legacy wakeup
+	 *   - disable SPM sleep control
+	 *   - disable SCP sleep mode
+	 */
+	SCP_CLK_SLEEP_CTRL &= ~(EN_SLEEP_CTRL | SPM_SLEEP_MODE);
+
+	task_enable_irq(SCP_IRQ_CLOCK);
+	task_enable_irq(SCP_IRQ_CLOCK2);
+}
+
+static void scp_ulposc_config(int osc, uint32_t osc_div, uint32_t osc_cali)
+{
+	uint32_t val;
+
+	/* Clear all bits */
+	val = 0;
+	/* Enable CP */
+	val |= OSC_CP_EN;
+	/* Set div */
+	val |= osc_div << 17;
+	/* F-band = 0, I-band = 4 */
+	val |= 4 << 6;
+	/* Set calibration */
+	val |= osc_cali;
+	/* Set control register 1 */
+	AP_ULPOSC_CON02(osc) = val;
+	/* Set control register 2, enable div2 */
+	AP_ULPOSC_CON13(osc) |= OSC_DIV2_EN;
+}
+
+static inline void busy_udelay(int usec)
+{
+	/*
+	 * Delaying by busy-looping, for place that can't use udelay because of
+	 * the clock not configured yet. The value 28 is chosen approximately
+	 * from experiment.
+	 */
+	volatile int i = usec * 28;
+
+	while (i--)
+		;
+}
+
+static unsigned int scp_measure_ulposc_freq(int osc)
+{
+	unsigned int result = 0;
+	int cnt;
+
+	/* Before select meter clock input, bit[1:0] = b00 */
+	AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_MODE_MASK) | DBG_MODE_SET_CLOCK;
+
+	/* Select source, bit[21:16] = clk_src */
+	AP_CLK_DBG_CFG =
+		(AP_CLK_DBG_CFG & ~DBG_BIST_SOURCE_MASK) |
+		(osc == 0 ? DBG_BIST_SOURCE_ULPOSC1 : DBG_BIST_SOURCE_ULPOSC2);
+
+	/* Set meter divisor to 1, bit[31:24] = b00000000 */
+	AP_CLK_MISC_CFG_0 = (AP_CLK_MISC_CFG_0 & ~MISC_METER_DIVISOR_MASK) |
+			    MISC_METER_DIV_1;
+
+	/* Enable frequency meter, without start */
+	AP_SCP_CFG_0 |= CFG_FREQ_METER_ENABLE;
+
+	/* Trigger frequency meter start */
+	AP_SCP_CFG_0 |= CFG_FREQ_METER_RUN;
+
+	/*
+	 * Frequency meter counts cycles in 1 / (26 * 1024) second period.
+	 *   freq_in_hz = freq_counter * 26 * 1024
+	 *
+	 * The hardware takes 38us to count cycles. Delay up to 100us,
+	 * as busy_udelay may not be accurate when sysclk is not 26Mhz
+	 * (e.g. when recalibrating/measuring after boot).
+	 */
+	for (cnt = 100; cnt; cnt--) {
+		busy_udelay(1);
+		if (!(AP_SCP_CFG_0 & CFG_FREQ_METER_RUN)) {
+			result = CFG_FREQ_COUNTER(AP_SCP_CFG_1);
+			break;
+		}
+	}
+
+	/* Disable freq meter */
+	AP_SCP_CFG_0 &= ~CFG_FREQ_METER_ENABLE;
+	return result;
+}
+
+static inline int signum(int v)
+{
+	return (v > 0) - (v < 0);
+}
+
+static inline int abs(int v)
+{
+	return (v >= 0) ? v : -v;
+}
+
+static int scp_ulposc_config_measure(int osc, int div, int cali)
+{
+	int freq;
+
+	scp_ulposc_config(osc, div, cali);
+	freq = scp_measure_ulposc_freq(osc);
+	CPRINTF("ULPOSC%d: %d %d %d (%dkHz)\n", osc + 1, div, cali, freq,
+		freq * 26 * 1000 / 1024);
+
+	return freq;
+}
+
+/**
+ * Calibrate ULPOSC to target frequency.
+ *
+ * @param osc           0:ULPOSC1, 1:ULPOSC2
+ * @param target_mhz    Target frequency to set
+ * @return              Frequency counter output
+ *
+ */
+static int scp_calibrate_ulposc(int osc, int target_mhz)
+{
+	int target_freq = DIV_ROUND_NEAREST(target_mhz * 1024, 26);
+	struct ulposc {
+		int div; /* frequency divisor/multiplier */
+		int cali; /* variable resistor calibrator */
+		int freq; /* frequency counter measure result */
+	} curr, prev = { 0 };
+	enum { STAGE_DIV, STAGE_CALI } stage = STAGE_DIV;
+	int param, param_max;
+
+	curr.div = ULPOSC_DIV_MAX / 2;
+	curr.cali = ULPOSC_CALI_MAX / 2;
+
+	param = curr.div;
+	param_max = ULPOSC_DIV_MAX;
+
+	/*
+	 * In the loop below, linear search closest div value to get desired
+	 * frequency counter value. Then adjust cali to get a better result.
+	 * Note that this doesn't give optimal output frequency, but it's
+	 * usually close enough.
+	 * TODO(b:120176040): See if we can efficiently calibrate the clock with
+	 * more precision by exploring more of the cali/div space.
+	 *
+	 * The frequency function follows. Note that f is positively correlated
+	 * with both div and cali:
+	 * f(div, cali) = k1 * (div + k2) / R(cali) * C
+	 * Where:
+	 *   R(cali) = k3 / (1 + k4 * (cali - k4))
+	 */
+	while (1) {
+		curr.freq = scp_ulposc_config_measure(osc, curr.div, curr.cali);
+
+		if (!curr.freq)
+			return 0;
+
+		/*
+		 * If previous and current are on either side of the desired
+		 * frequency, pick the closest one.
+		 */
+		if (prev.freq && signum(target_freq - curr.freq) !=
+					 signum(target_freq - prev.freq)) {
+			if (abs(target_freq - prev.freq) <
+			    abs(target_freq - curr.freq))
+				curr = prev;
+
+			if (stage == STAGE_CALI)
+				break;
+
+			/* Switch to optimizing cali */
+			stage = STAGE_CALI;
+			param = curr.cali;
+			param_max = ULPOSC_CALI_MAX;
+		}
+
+		prev = curr;
+		param += signum(target_freq - curr.freq);
+
+		if (param < 0 || param >= param_max)
+			return 0;
+
+		if (stage == STAGE_DIV)
+			curr.div = param;
+		else
+			curr.cali = param;
+	}
+
+	/*
+	 * It's possible we end up using prev, so reset the configuration and
+	 * measure again.
+	 */
+	return scp_ulposc_config_measure(osc, curr.div, curr.cali);
+}
+
+static void scp_clock_high_enable(int osc)
+{
+	/* Enable high speed clock */
+	SCP_CLK_EN |= EN_CLK_HIGH;
+
+	switch (osc) {
+	case 0:
+		/* After 25ms, enable ULPOSC */
+		busy_udelay(25 * MSEC);
+		SCP_CLK_EN |= CG_CLK_HIGH;
+		break;
+	case 1:
+		/* Turn off ULPOSC2 high-core-disable switch */
+		SCP_CLK_ON_CTRL &= ~HIGH_CORE_DIS_SUB;
+		/* After 25ms, turn on ULPOSC2 high core clock gate */
+		busy_udelay(25 * MSEC);
+		SCP_CLK_HIGH_CORE |= CLK_HIGH_CORE_CG;
+		break;
+	default:
+		break;
+	}
+}
+
+void scp_use_clock(enum scp_clock_source src)
+{
+	/*
+	 * DIV2 divider takes precedence over clock selection to prevent
+	 * over-clocking.
+	 */
+	if (src == SCP_CLK_ULPOSC1)
+		SCP_CLK_DIV_SEL = CLK_DIV2;
+
+	SCP_CLK_SEL = src;
+
+	if (src != SCP_CLK_ULPOSC1)
+		SCP_CLK_DIV_SEL = CLK_DIV1;
+}
+
+void scp_enable_clock(void)
+{
+	/* Select default CPU clock */
+	scp_use_clock(SCP_CLK_26M);
+
+	/* VREQ */
+	SCP_CPU_VREQ = 0x10001;
+	SCP_SECURE_CTRL &= ~ENABLE_SPM_MASK_VREQ;
+
+	/* DDREN auto mode */
+	SCP_SYS_CTRL |= AUTO_DDREN;
+
+	/* Set settle time */
+	SCP_CLK_SYS_VAL = 1; /* System clock */
+	SCP_CLK_HIGH_VAL = 1; /* ULPOSC */
+	SCP_CLK_SLEEP_CTRL = (SCP_CLK_SLEEP_CTRL & ~VREQ_COUNTER_MASK) | 2;
+
+	/* Disable slow wake */
+	SCP_CLK_SLEEP = SLOW_WAKE_DISABLE;
+	/* Disable SPM sleep control, disable sleep mode */
+	SCP_CLK_SLEEP_CTRL &= ~(SPM_SLEEP_MODE | EN_SLEEP_CTRL);
+
+	/* Turn off ULPOSC2 */
+	SCP_CLK_ON_CTRL |= HIGH_CORE_DIS_SUB;
+	scp_ulposc_config(0, 12, 32);
+	scp_clock_high_enable(0); /* Turn on ULPOSC1 */
+	scp_ulposc_config(1, 16, 32);
+	scp_clock_high_enable(1); /* Turn on ULPOSC2 */
+
+	/* Calibrate ULPOSC */
+	scp_calibrate_ulposc(0, ULPOSC1_CLOCK_MHZ);
+	scp_calibrate_ulposc(1, ULPOSC2_CLOCK_MHZ);
+
+	/* Select ULPOSC2 high speed CPU clock */
+	scp_use_clock(SCP_CLK_ULPOSC2);
+
+	/* Enable default clock gate */
+	SCP_CLK_GATE |= CG_DMA_CH3 | CG_DMA_CH2 | CG_DMA_CH1 | CG_DMA_CH0 |
+			CG_I2C_M | CG_MAD_M | CG_AP2P_M;
+
+	/* Select pwrap_ulposc */
+	AP_CLK_CFG_5 = (AP_CLK_CFG_5 & ~PWRAP_ULPOSC_MASK) | OSC_D16;
+
+	/* Enable pwrap_ulposc clock gate */
+	AP_CLK_CFG_5_CLR = PWRAP_ULPOSC_CG;
+}
+
+DECLARE_IRQ(SCP_IRQ_CLOCK, clock_control_irq, 3);
+static void clock_control_irq(void)
+{
+	/* Read ack CLK_IRQ */
+	(SCP_CLK_IRQ_ACK);
+	task_clear_pending_irq(SCP_IRQ_CLOCK);
+}
+
+DECLARE_IRQ(SCP_IRQ_CLOCK2, clock_fast_wakeup_irq, 3);
+static void clock_fast_wakeup_irq(void)
+{
+	/* Ack fast wakeup */
+	SCP_SLEEP_IRQ2 = 1;
+	task_clear_pending_irq(SCP_IRQ_CLOCK2);
+}
+
+/* Console command */
+static int command_ulposc(int argc, const char *argv[])
+{
+	if (argc > 1 && !strncmp(argv[1], "cal", 3)) {
+		scp_calibrate_ulposc(0, ULPOSC1_CLOCK_MHZ);
+		scp_calibrate_ulposc(1, ULPOSC2_CLOCK_MHZ);
+	}
+
+	/* SCP clock meter counts every (26MHz / 1024) tick */
+	ccprintf("ULPOSC1 frequency: %u kHz\n",
+		 scp_measure_ulposc_freq(0) * 26 * 1000 / 1024);
+	ccprintf("ULPOSC2 frequency: %u kHz\n",
+		 scp_measure_ulposc_freq(1) * 26 * 1000 / 1024);
+
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(ulposc, command_ulposc, "[calibrate]",
+			"Calibrate ULPOSC frequency");
+
+test_mockable void clock_enable_module(enum module_id module, int enable)
+{
+}
diff --git a/chip/mt_scp/mt818x/clock_mt8186.c b/chip/mt_scp/mt818x/clock_mt8186.c
new file mode 100644
index 0000000000..a31ab6059c
--- /dev/null
+++ b/chip/mt_scp/mt818x/clock_mt8186.c
@@ -0,0 +1,382 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Clocks, PLL and power settings */
+
+#include "builtin/assert.h"
+#include "clock.h"
+#include "clock_chip.h"
+#include "common.h"
+#include "console.h"
+#include "registers.h"
+#include "task.h"
+#include "timer.h"
+#include "util.h"
+
+#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ##args)
+
+#define ULPOSC_CAL_MIN_VALUE 3
+#define ULPOSC_CAL_MAX_VALUE 60
+#define ULPOSC_CAL_START_VALUE \
+	((ULPOSC_CAL_MIN_VALUE + ULPOSC_CAL_MAX_VALUE) / 2)
+
+static struct opp_ulposc_cfg {
+	uint32_t osc;
+	uint32_t div;
+	uint32_t iband;
+	uint32_t mod;
+	uint32_t cali;
+	uint32_t target_mhz;
+} opp[] = {
+	{
+		.osc = 1,
+		.target_mhz = ULPOSC2_CLOCK_MHZ,
+		.div = 16,
+		.iband = 4,
+		.mod = 1,
+		.cali = ULPOSC_CAL_START_VALUE,
+	},
+	{
+		.osc = 0,
+		.target_mhz = ULPOSC1_CLOCK_MHZ,
+		.div = 12,
+		.iband = 4,
+		.mod = 1,
+		.cali = ULPOSC_CAL_START_VALUE,
+	},
+};
+
+static inline void clock_busy_udelay(int usec)
+{
+	/*
+	 * Delaying by busy-looping, for place that can't use udelay because of
+	 * the clock not configured yet. The value 28 is chosen approximately
+	 * from experiment.
+	 *
+	 * `volatile' in order to avoid compiler to optimize the function out
+	 * (otherwise, the function will be eliminated).
+	 */
+	volatile int i = usec * 28;
+
+	while (--i)
+		;
+}
+
+static void clock_ulposc_config_default(struct opp_ulposc_cfg *opp)
+{
+	unsigned int val = 0;
+
+	/* Enable CP */
+	val |= OSC_CP_EN;
+	/* set div */
+	val |= opp->div << OSC_DIV_SHIFT;
+	/* set I-band */
+	val |= (opp->iband << OSC_IBAND_SHIFT);
+	/* set calibration */
+	val |= opp->cali;
+	/* set control register */
+	AP_ULPOSC_CON02(opp->osc) = val;
+
+	/* OSC_DIV2_EN = 1 */
+	AP_ULPOSC_CON13(opp->osc) |= OSC_DIV2_EN;
+	/* OSC_MOD = 00 */
+	AP_ULPOSC_CON13(opp->osc) &= ~OSC_MOD_MASK;
+}
+
+static void clock_ulposc_config_cali(struct opp_ulposc_cfg *opp,
+				     uint32_t cali_val)
+{
+	uint32_t val;
+
+	val = AP_ULPOSC_CON02(opp->osc);
+	val &= ~OSC_CALI_MASK;
+	val |= cali_val;
+	AP_ULPOSC_CON02(opp->osc) = val;
+
+	clock_busy_udelay(50);
+}
+
+static unsigned int clock_ulposc_measure_freq(int osc)
+{
+	unsigned int clk_dbg_cfg, clk_misc_cfg_0, clk26cali_0, clk26cali_1,
+		result = 0;
+	int cnt;
+
+	/* backup */
+	clk_dbg_cfg = AP_CLK_DBG_CFG;
+	clk_misc_cfg_0 = AP_CLK_MISC_CFG_0;
+	clk26cali_0 = AP_SCP_CFG_0;
+	clk26cali_1 = AP_SCP_CFG_1;
+
+	/* Before select meter clock input, bit[1:0] = b00 */
+	AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_MODE_MASK) | DBG_MODE_SET_CLOCK;
+
+	/* Select source, bit[21:16] = clk_src */
+	AP_CLK_DBG_CFG =
+		(AP_CLK_DBG_CFG & ~DBG_BIST_SOURCE_MASK) |
+		(osc == 0 ? DBG_BIST_SOURCE_ULPOSC1 : DBG_BIST_SOURCE_ULPOSC2);
+
+	/* Set meter divisor to 1, bit[31:24] = b00000000 */
+	AP_CLK_MISC_CFG_0 = (AP_CLK_MISC_CFG_0 & ~MISC_METER_DIVISOR_MASK) |
+			    MISC_METER_DIV_1;
+
+	/* Enable frequency meter, without start */
+	AP_SCP_CFG_0 |= CFG_FREQ_METER_ENABLE;
+
+	/* Trigger frequency meter start */
+	AP_SCP_CFG_0 |= CFG_FREQ_METER_RUN;
+	/*
+	 * Frequency meter counts cycles in 1 / (26 * 1024) second period.
+	 *   freq_in_hz = freq_counter * 26 * 1024
+	 *
+	 * The hardware takes 38us to count cycles. Delay up to 100us,
+	 * as clock_busy_udelay may not be accurate when sysclk is not 26Mhz
+	 * (e.g. when recalibrating/measuring after boot).
+	 */
+	for (cnt = 100; cnt; cnt--) {
+		clock_busy_udelay(1);
+		if (!(AP_SCP_CFG_0 & CFG_FREQ_METER_RUN)) {
+			result = CFG_FREQ_COUNTER(AP_SCP_CFG_1);
+			break;
+		}
+	}
+
+	/* Disable freq meter */
+	AP_SCP_CFG_0 &= ~CFG_FREQ_METER_ENABLE;
+
+	/* restore */
+	AP_CLK_DBG_CFG = clk_dbg_cfg;
+	AP_CLK_MISC_CFG_0 = clk_misc_cfg_0;
+	AP_SCP_CFG_0 = clk26cali_0;
+	AP_SCP_CFG_1 = clk26cali_1;
+
+	return result;
+}
+
+#define CAL_MIS_RATE 40
+static int clock_ulposc_is_calibrated(struct opp_ulposc_cfg *opp)
+{
+	uint32_t curr, target;
+
+	curr = clock_ulposc_measure_freq(opp->osc);
+	target = opp->target_mhz * 1024 / 26;
+
+	/* check if calibrated value is in the range of target value +- 4% */
+	if (curr > (target * (1000 - CAL_MIS_RATE) / 1000) &&
+	    curr < (target * (1000 + CAL_MIS_RATE) / 1000))
+		return 1;
+	else
+		return 0;
+}
+
+static uint32_t clock_ulposc_process_cali(struct opp_ulposc_cfg *opp)
+{
+	uint32_t current_val = 0;
+	uint32_t target_val = opp->target_mhz * 1024 / 26;
+	uint32_t middle, min = 0, max = OSC_CALI_MASK;
+	uint32_t diff_by_min, diff_by_max, cal_result;
+
+	do {
+		middle = (min + max) / 2;
+		if (middle == min)
+			break;
+
+		clock_ulposc_config_cali(opp, middle);
+		current_val = clock_ulposc_measure_freq(opp->osc);
+
+		if (current_val > target_val)
+			max = middle;
+		else
+			min = middle;
+	} while (min <= max);
+
+	clock_ulposc_config_cali(opp, min);
+	current_val = clock_ulposc_measure_freq(opp->osc);
+	if (current_val > target_val)
+		diff_by_min = current_val - target_val;
+	else
+		diff_by_min = target_val - current_val;
+
+	clock_ulposc_config_cali(opp, max);
+	current_val = clock_ulposc_measure_freq(opp->osc);
+	if (current_val > target_val)
+		diff_by_max = current_val - target_val;
+	else
+		diff_by_max = target_val - current_val;
+
+	if (diff_by_min < diff_by_max)
+		cal_result = min;
+	else
+		cal_result = max;
+
+	clock_ulposc_config_cali(opp, cal_result);
+	if (!clock_ulposc_is_calibrated(opp))
+		assert(0);
+
+	return cal_result;
+}
+
+static void clock_high_enable(int osc)
+{
+	/* Enable high speed clock */
+	SCP_CLK_EN |= EN_CLK_HIGH;
+
+	switch (osc) {
+	case 0:
+		/* After 25ms, enable ULPOSC */
+		clock_busy_udelay(25 * MSEC);
+		SCP_CLK_EN |= CG_CLK_HIGH;
+		break;
+	case 1:
+		/* Turn off ULPOSC2 high-core-disable switch */
+		SCP_CLK_ON_CTRL &= ~HIGH_CORE_DIS_SUB;
+		/* After 25ms, turn on ULPOSC2 high core clock gate */
+		clock_busy_udelay(25 * MSEC);
+		SCP_CLK_HIGH_CORE |= CLK_HIGH_CORE_CG;
+		break;
+	default:
+		break;
+	}
+	clock_busy_udelay(25 * MSEC);
+}
+
+static void clock_calibrate_ulposc(struct opp_ulposc_cfg *opp)
+{
+	/*
+	 * TODO: Check ULPOSC1(osc=0) is already ?
+	 * - calibrated
+	 * - enabled in coreboot
+	 * - used by pmic wrapper
+	 */
+
+	clock_ulposc_config_default(opp);
+	clock_high_enable(opp->osc);
+
+	/* Calibrate only if it is not accurate enough. */
+	if (!clock_ulposc_is_calibrated(opp))
+		opp->cali = clock_ulposc_process_cali(opp);
+
+	CPRINTF("osc:%u, target=%uMHz, cal:%u\n", opp->osc, opp->target_mhz,
+		opp->cali);
+}
+
+void scp_use_clock(enum scp_clock_source src)
+{
+	/*
+	 * DIV2 divider takes precedence over clock selection to prevent
+	 * over-clocking.
+	 */
+	if (src == SCP_CLK_ULPOSC1)
+		SCP_CLK_DIV_SEL = CLK_DIV2;
+
+	SCP_CLK_SEL = src;
+
+	if (src != SCP_CLK_ULPOSC1)
+		SCP_CLK_DIV_SEL = CLK_DIV1;
+}
+
+void clock_init(void)
+{
+	/* Enable fast wakeup support */
+	SCP_CLK_ON_CTRL = (SCP_CLK_ON_CTRL & ~HIGH_FINAL_VAL_MASK) |
+			  HIGH_FINAL_VAL_DEFAULT;
+	SCP_FAST_WAKE_CNT_END =
+		(SCP_FAST_WAKE_CNT_END & ~FAST_WAKE_CNT_END_MASK) |
+		FAST_WAKE_CNT_END_DEFAULT;
+
+	/* Set slow wake clock */
+	SCP_WAKE_CKSW = (SCP_WAKE_CKSW & ~WAKE_CKSW_SEL_SLOW_MASK) |
+			WAKE_CKSW_SEL_SLOW_DEFAULT;
+
+	/* Select CLK_HIGH as wakeup clock */
+	SCP_CLK_SLOW_SEL = (SCP_CLK_SLOW_SEL &
+			    (CKSW_SEL_SLOW_MASK | CKSW_SEL_SLOW_DIV_MASK)) |
+			   CKSW_SEL_SLOW_ULPOSC2_CLK;
+}
+
+void scp_enable_clock(void)
+{
+	int i;
+
+	/* Select default CPU clock */
+	scp_use_clock(SCP_CLK_26M);
+
+	/* VREQ */
+	SCP_CPU_VREQ = VREQ_DVFS_SEL;
+	SCP_SECURE_CTRL |= ENABLE_SPM_MASK_VREQ;
+	SCP_CLK_CTRL_GENERAL_CTRL &= ~VREQ_PMIC_WRAP_SEL;
+
+	/* DDREN auto mode */
+	SCP_SYS_CTRL |= AUTO_DDREN;
+
+	/* Set settle time */
+	SCP_CLK_SYS_VAL = (SCP_CLK_SYS_VAL & ~CLK_SYS_VAL_MASK) |
+			  CLK_SYS_VAL(1);
+	SCP_CLK_HIGH_VAL = (SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) |
+			   CLK_HIGH_VAL(1);
+	SCP_CLK_SLEEP_CTRL = (SCP_CLK_SLEEP_CTRL & ~VREQ_COUNTER_MASK) |
+			     VREQ_COUNTER_VAL(1);
+
+	/* Disable slow wake */
+	SCP_CLK_SLEEP = SLOW_WAKE_DISABLE;
+	/* Disable SPM sleep control, disable sleep mode */
+	SCP_CLK_SLEEP_CTRL &= ~(SPM_SLEEP_MODE | EN_SLEEP_CTRL);
+
+	/* Set RG MUX to SW mode */
+	AP_PLL_CON0 = LTECLKSQ_EN | LTECLKSQ_LPF_EN | LTECLKSQ_HYS_EN |
+		      LTECLKSQ_VOD_EN | LTECLKSQ_HYS_SEL | CLKSQ_RESERVE |
+		      SSUSB26M_CK2_EN | SSUSB26M_CK_EN | XTAL26M_CK_EN |
+		      ULPOSC_CTRL_SEL;
+
+	/* Turn off ULPOSC2 */
+	SCP_CLK_ON_CTRL |= HIGH_CORE_DIS_SUB;
+
+	/* calibrate ULPOSC1 & ULPOSC2 */
+	for (i = 0; i < ARRAY_SIZE(opp); ++i)
+		clock_calibrate_ulposc(&opp[i]);
+
+	/* Select ULPOSC2 high speed CPU clock */
+	scp_use_clock(SCP_CLK_ULPOSC2);
+
+	/* Enable default clock gate */
+	SCP_CLK_GATE |= CG_DMA_CH3 | CG_DMA_CH2 | CG_DMA_CH1 | CG_DMA_CH0 |
+			CG_I2C_M | CG_MAD_M | CG_AP2P_M;
+
+	task_enable_irq(SCP_IRQ_CLOCK);
+	task_enable_irq(SCP_IRQ_CLOCK2);
+}
+
+DECLARE_IRQ(SCP_IRQ_CLOCK, clock_control_irq, 3);
+void clock_control_irq(void)
+{
+	/* Read ack CLK_IRQ */
+	(SCP_CLK_IRQ_ACK);
+	task_clear_pending_irq(SCP_IRQ_CLOCK);
+}
+
+DECLARE_IRQ(SCP_IRQ_CLOCK2, clock_fast_wakeup_irq, 3);
+void clock_fast_wakeup_irq(void)
+{
+	/* Ack fast wakeup */
+	SCP_SLEEP_IRQ2 = 1;
+	task_clear_pending_irq(SCP_IRQ_CLOCK2);
+}
+
+/* Console command */
+static int command_ulposc(int argc, const char *argv[])
+{
+	int i;
+
+	for (i = 0; i <= 1; ++i)
+		ccprintf("ULPOSC%u frequency: %u kHz\n", i + 1,
+			 clock_ulposc_measure_freq(i) * 26 * 1000 / 1024);
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(ulposc, command_ulposc, "[calibrate]",
+			"Calibrate ULPOSC frequency");
+
+test_mockable void clock_enable_module(enum module_id module, int enable)
+{
+}
diff --git a/chip/mt_scp/mt818x/config_chip.h b/chip/mt_scp/mt818x/config_chip.h
new file mode 100644
index 0000000000..e0222e33fa
--- /dev/null
+++ b/chip/mt_scp/mt818x/config_chip.h
@@ -0,0 +1,75 @@
+/* Copyright 2018 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_CONFIG_CHIP_H
+#define __CROS_EC_CONFIG_CHIP_H
+
+#include "core/cortex-m/config_core.h"
+
+/* Interval between HOOK_TICK notifications */
+#define HOOK_TICK_INTERVAL_MS 500
+#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC)
+
+#ifdef CHIP_VARIANT_MT8186
+/* Default to UART 1 (AP UART) for EC console */
+#define CONFIG_UART_CONSOLE 1
+#else
+/* Default to UART 2 (AP UART) for EC console */
+#define CONFIG_UART_CONSOLE 2
+#endif
+
+/* Number of IRQ vectors */
+#define CONFIG_IRQ_COUNT 56
+
+/*
+ * Number of EINT can be 0 ~ 160. Change this to conditional macro
+ * on adding other variants.
+ */
+#define MAX_NUM_EINT 8
+#define MAX_EINT_PORT (MAX_NUM_EINT / 32)
+
+/* RW only, no flash */
+#undef CONFIG_FW_INCLUDE_RO
+#define CONFIG_RO_MEM_OFF 0
+#define CONFIG_RO_SIZE 0
+#define CONFIG_RW_MEM_OFF 0
+
+#ifdef CHIP_VARIANT_MT8186
+#define CONFIG_RW_SIZE 0x20000 /* 128KB */
+#else
+#define CONFIG_RW_SIZE 0x40000 /* 256KB */
+#endif
+
+#define CONFIG_EC_WRITABLE_STORAGE_OFF 0
+#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
+#define CONFIG_RO_STORAGE_OFF 0
+#define CONFIG_RW_STORAGE_OFF 0
+#define CONFIG_PROGRAM_MEMORY_BASE 0
+#define CONFIG_MAPPED_STORAGE_BASE 0
+/* Enable MPU to protect code RAM from writing, and data RAM from execution.*/
+#define CONFIG_MPU
+
+/* Unsupported features/commands */
+#undef CONFIG_CMD_FLASHINFO
+#undef CONFIG_CMD_POWER_AP
+#undef CONFIG_FLASH_CROS
+#undef CONFIG_FLASH_PHYSICAL
+#undef CONFIG_FMAP
+#undef CONFIG_HIBERNATE
+
+/* Task stack size */
+#define CONFIG_STACK_SIZE 1024
+#define IDLE_TASK_STACK_SIZE 256
+#define SMALLER_TASK_STACK_SIZE 384
+#define TASK_STACK_SIZE 512
+#define LARGER_TASK_STACK_SIZE 640
+#define VENTI_TASK_STACK_SIZE 768
+
+#define CONFIG_CHIP_PRE_INIT
+
+#define GPIO_PIN(num) ((num) / 32), ((num) % 32)
+#define GPIO_PIN_MASK(p, m) .port = (p), .mask = (m)
+
+#endif /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/chip/mt_scp/mt818x/gpio.c b/chip/mt_scp/mt818x/gpio.c
new file mode 100644
index 0000000000..6d9a3b8418
--- /dev/null
+++ b/chip/mt_scp/mt818x/gpio.c
@@ -0,0 +1,178 @@
+/* Copyright 2018 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* GPIO module */
+
+#include "gpio.h"
+#include "hooks.h"
+#include "registers.h"
+#include "system.h"
+#include "task.h"
+#include "util.h"
+
+void gpio_set_alternate_function(uint32_t port, uint32_t mask,
+				 enum gpio_alternate_func func)
+{
+	int bit, mode_reg_index, shift;
+	uint32_t mode_bits, mode_mask;
+
+	/* Up to 8 alt functions per port */
+	if (func > GPIO_ALT_FUNC_7)
+		return;
+
+	if (func == GPIO_ALT_FUNC_NONE)
+		func = GPIO_ALT_FUNC_DEFAULT;
+
+	while (mask) {
+		/* 32 gpio per port */
+		bit = get_next_bit(&mask);
+		/* 8 gpio per mode reg */
+		mode_reg_index = (port << 2) | (bit >> 3);
+		/*
+		 * b[3]   - write enable(?)
+		 * b[2:0] - mode
+		 */
+		shift = (bit & 7) << 2;
+		mode_bits = func << shift;
+		mode_mask = ~(0xf << shift);
+		AP_GPIO_MODE(mode_reg_index) =
+			(AP_GPIO_MODE(mode_reg_index) & mode_mask) | mode_bits;
+	}
+}
+
+test_mockable int gpio_get_level(enum gpio_signal signal)
+{
+	return !!(AP_GPIO_DIN(gpio_list[signal].port) & gpio_list[signal].mask);
+}
+
+void gpio_set_level(enum gpio_signal signal, int value)
+{
+	if (value)
+		AP_GPIO_DOUT(gpio_list[signal].port) |= gpio_list[signal].mask;
+	else
+		AP_GPIO_DOUT(gpio_list[signal].port) &= ~gpio_list[signal].mask;
+}
+
+void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
+{
+	/* Set input/output mode */
+	if (flags & GPIO_OUTPUT) {
+		/* Set level before changing to output mode */
+		if (flags & GPIO_HIGH)
+			AP_GPIO_DOUT(port) |= mask;
+		if (flags & GPIO_LOW)
+			AP_GPIO_DOUT(port) &= ~mask;
+		AP_GPIO_DIR(port) |= mask;
+	} else {
+		AP_GPIO_DIR(port) &= ~mask;
+	}
+
+	if (flags & (GPIO_INT_F_RISING | GPIO_INT_F_HIGH))
+		SCP_EINT_POLARITY_SET[port] = mask;
+
+	if (flags & (GPIO_INT_F_FALLING | GPIO_INT_F_LOW))
+		SCP_EINT_POLARITY_CLR[port] = mask;
+	else
+		SCP_EINT_POLARITY_SET[port] = mask;
+
+	/* Set sensitivity register on edge trigger */
+	if (flags & (GPIO_INT_F_RISING | GPIO_INT_F_FALLING))
+		SCP_EINT_SENS_SET[port] = mask;
+	else
+		SCP_EINT_SENS_CLR[port] = mask;
+}
+
+int gpio_get_flags_by_mask(uint32_t port, uint32_t mask)
+{
+	/* TODO(b/120167145): implement get flags */
+	return 0;
+}
+
+int gpio_enable_interrupt(enum gpio_signal signal)
+{
+	const struct gpio_info *g = gpio_list + signal;
+
+	if (signal >= GPIO_IH_COUNT || !g->mask)
+		return EC_ERROR_INVAL;
+
+	SCP_EINT_MASK_CLR[g->port] = g->mask;
+
+	return EC_SUCCESS;
+}
+
+int gpio_disable_interrupt(enum gpio_signal signal)
+{
+	const struct gpio_info *g = gpio_list + signal;
+
+	if (signal >= GPIO_IH_COUNT || !g->mask)
+		return EC_ERROR_INVAL;
+
+	SCP_EINT_MASK_SET[g->port] = g->mask;
+
+	return EC_SUCCESS;
+}
+
+int gpio_clear_pending_interrupt(enum gpio_signal signal)
+{
+	const struct gpio_info *g = gpio_list + signal;
+
+	if (signal >= GPIO_IH_COUNT || !g->mask)
+		return EC_ERROR_INVAL;
+
+	SCP_EINT_ACK[g->port] = g->mask;
+
+	return EC_SUCCESS;
+}
+
+void gpio_pre_init(void)
+{
+	const struct gpio_info *g = gpio_list;
+	int i;
+	int is_warm = system_is_reboot_warm();
+
+	for (i = 0; i < GPIO_COUNT; i++, g++) {
+		int flags = g->flags;
+
+		if (flags & GPIO_DEFAULT)
+			continue;
+
+		if (is_warm)
+			flags &= ~(GPIO_LOW | GPIO_HIGH);
+
+		gpio_set_flags_by_mask(g->port, g->mask, flags);
+	}
+}
+
+void gpio_init(void)
+{
+	/* Enable EINT IRQ */
+	task_enable_irq(SCP_IRQ_EINT);
+}
+DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
+
+/* Interrupt handler */
+static void __attribute__((used)) gpio_interrupt(void)
+{
+	int bit, port;
+	uint32_t pending;
+	enum gpio_signal signal;
+
+	for (port = 0; port <= MAX_EINT_PORT; port++) {
+		pending = SCP_EINT_STATUS[port];
+
+		while (pending) {
+			bit = get_next_bit(&pending);
+			SCP_EINT_ACK[port] = BIT(bit);
+			/* Skip masked gpio */
+			if (SCP_EINT_MASK_GET[port] & BIT(bit))
+				continue;
+			/* Call handler */
+			signal = port * 32 + bit;
+			if (signal < GPIO_IH_COUNT)
+				gpio_irq_handlers[signal](signal);
+		}
+	}
+}
+DECLARE_IRQ(SCP_IRQ_EINT, gpio_interrupt, 1);
diff --git a/chip/mt_scp/mt818x/hrtimer.c b/chip/mt_scp/mt818x/hrtimer.c
new file mode 100644
index 0000000000..e68c3e48e7
--- /dev/null
+++ b/chip/mt_scp/mt818x/hrtimer.c
@@ -0,0 +1,255 @@
+/* Copyright 2018 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * High-res hardware timer
+ *
+ * SCP hardware 32bit count down timer can be configured to source clock from
+ * 32KHz, 26MHz, BCLK or PCLK. This implementation selects BCLK (ULPOSC1/8) as a
+ * source, countdown mode and converts to micro second value matching common
+ * timer.
+ */
+
+#include "clock.h"
+#include "clock_chip.h"
+#include "common.h"
+#include "console.h"
+#include "hooks.h"
+#include "hwtimer.h"
+#include "panic.h"
+#include "registers.h"
+#include "task.h"
+#include "timer.h"
+#include "watchdog.h"
+
+#define IRQ_TIMER(n) CONCAT2(SCP_IRQ_TIMER, n)
+
+#define TIMER_SYSTEM 5
+#define TIMER_EVENT 3
+
+/* ULPOSC1 should be a multiple of 8. */
+BUILD_ASSERT((ULPOSC1_CLOCK_MHZ % 8) == 0);
+#define TIMER_CLOCK_MHZ (ULPOSC1_CLOCK_MHZ / 8)
+
+/* Common timer overflows at 0x100000000 micro seconds */
+#define OVERFLOW_TICKS (TIMER_CLOCK_MHZ * 0x100000000 - 1)
+
+static uint8_t sys_high;
+static uint8_t event_high;
+
+/* Convert hardware countdown timer to 64bit countup ticks */
+static inline uint64_t timer_read_raw_system(void)
+{
+	uint32_t timer_ctrl = SCP_TIMER_IRQ_CTRL(TIMER_SYSTEM);
+	uint32_t sys_high_adj = sys_high;
+
+	/*
+	 * If an IRQ is pending, but has not been serviced yet, adjust the
+	 * sys_high value.
+	 */
+	if (timer_ctrl & TIMER_IRQ_STATUS)
+		sys_high_adj = sys_high ? (sys_high - 1) :
+					  (TIMER_CLOCK_MHZ - 1);
+
+	return OVERFLOW_TICKS -
+	       (((uint64_t)sys_high_adj << 32) | SCP_TIMER_VAL(TIMER_SYSTEM));
+}
+
+static inline uint64_t timer_read_raw_event(void)
+{
+	return OVERFLOW_TICKS -
+	       (((uint64_t)event_high << 32) | SCP_TIMER_VAL(TIMER_EVENT));
+}
+
+static inline void timer_set_clock(int n, uint32_t clock_source)
+{
+	SCP_TIMER_EN(n) = (SCP_TIMER_EN(n) & ~TIMER_CLK_MASK) | clock_source;
+}
+
+static inline void timer_ack_irq(int n)
+{
+	SCP_TIMER_IRQ_CTRL(n) |= TIMER_IRQ_CLEAR;
+}
+
+/* Set hardware countdown value */
+static inline void timer_set_reset_value(int n, uint32_t reset_value)
+{
+	SCP_TIMER_RESET_VAL(n) = reset_value;
+}
+
+static void timer_reset(int n)
+{
+	__hw_timer_enable_clock(n, 0);
+	timer_ack_irq(n);
+	timer_set_reset_value(n, 0xffffffff);
+	timer_set_clock(n, TIMER_CLK_32K);
+}
+
+/* Reload a new 32bit countdown value */
+static void timer_reload(int n, uint32_t value)
+{
+	__hw_timer_enable_clock(n, 0);
+	timer_set_reset_value(n, value);
+	__hw_timer_enable_clock(n, 1);
+}
+
+static int timer_reload_event_high(void)
+{
+	if (event_high) {
+		if (SCP_TIMER_RESET_VAL(TIMER_EVENT) == 0xffffffff)
+			__hw_timer_enable_clock(TIMER_EVENT, 1);
+		else
+			timer_reload(TIMER_EVENT, 0xffffffff);
+		event_high--;
+		return 1;
+	}
+
+	/* Disable event timer clock when done. */
+	__hw_timer_enable_clock(TIMER_EVENT, 0);
+	return 0;
+}
+
+void __hw_clock_event_clear(void)
+{
+	__hw_timer_enable_clock(TIMER_EVENT, 0);
+	timer_set_reset_value(TIMER_EVENT, 0x0000c1ea4);
+	event_high = 0;
+}
+
+void __hw_clock_event_set(uint32_t deadline)
+{
+	uint64_t deadline_raw = (uint64_t)deadline * TIMER_CLOCK_MHZ;
+	uint64_t now_raw = timer_read_raw_system();
+	uint32_t event_deadline;
+
+	if (deadline_raw > now_raw) {
+		deadline_raw -= now_raw;
+		event_deadline = (uint32_t)deadline_raw;
+		event_high = deadline_raw >> 32;
+	} else {
+		event_deadline = 1;
+		event_high = 0;
+	}
+
+	if (event_deadline)
+		timer_reload(TIMER_EVENT, event_deadline);
+	else
+		timer_reload_event_high();
+}
+
+void __hw_timer_enable_clock(int n, int enable)
+{
+	if (enable) {
+		SCP_TIMER_IRQ_CTRL(n) |= 1;
+		SCP_TIMER_EN(n) |= 1;
+	} else {
+		SCP_TIMER_EN(n) &= ~1;
+		SCP_TIMER_IRQ_CTRL(n) &= ~1;
+	}
+}
+
+int __hw_clock_source_init(uint32_t start_t)
+{
+	int t;
+
+	/*
+	 * TODO(b/120169529): check clock tree to see if we need to turn on
+	 * MCLK and BCLK gate.
+	 */
+	SCP_CLK_GATE |= (CG_TIMER_M | CG_TIMER_B);
+
+	/* Reset all timer, select 32768Hz clock source */
+	for (t = 0; t < NUM_TIMERS; t++)
+		timer_reset(t);
+
+	/* Enable timer IRQ wake source */
+	SCP_INTC_IRQ_WAKEUP |= (1 << IRQ_TIMER(0)) | (1 << IRQ_TIMER(1)) |
+			       (1 << IRQ_TIMER(2)) | (1 << IRQ_TIMER(3)) |
+			       (1 << IRQ_TIMER(4)) | (1 << IRQ_TIMER(5));
+	/*
+	 * Timer configuration:
+	 *   OS TIMER    - count up @ 13MHz, 64bit value with latch.
+	 *   SYS TICK    - count down @ 26MHz
+	 *   EVENT TICK  - count down @ 26MHz
+	 */
+
+	/* Turn on OS TIMER, tick at 13MHz */
+	SCP_OSTIMER_CON |= 1;
+
+	/* System timestamp timer from BCLK (sourced from ULPOSC) */
+	SCP_CLK_BCLK = CLK_BCLK_SEL_ULPOSC1_DIV8;
+
+	timer_set_clock(TIMER_SYSTEM, TIMER_CLK_BCLK);
+	sys_high = TIMER_CLOCK_MHZ - 1;
+	timer_set_reset_value(TIMER_SYSTEM, 0xffffffff);
+	__hw_timer_enable_clock(TIMER_SYSTEM, 1);
+	task_enable_irq(IRQ_TIMER(TIMER_SYSTEM));
+	/* Event tick timer */
+	timer_set_clock(TIMER_EVENT, TIMER_CLK_BCLK);
+	task_enable_irq(IRQ_TIMER(TIMER_EVENT));
+
+	return IRQ_TIMER(TIMER_SYSTEM);
+}
+
+uint32_t __hw_clock_source_read(void)
+{
+	return timer_read_raw_system() / TIMER_CLOCK_MHZ;
+}
+
+uint32_t __hw_clock_event_get(void)
+{
+	return (timer_read_raw_event() + timer_read_raw_system()) /
+	       TIMER_CLOCK_MHZ;
+}
+
+static void __hw_clock_source_irq(int n)
+{
+	uint32_t timer_ctrl = SCP_TIMER_IRQ_CTRL(n);
+
+	/* Ack if we're hardware interrupt */
+	if (timer_ctrl & TIMER_IRQ_STATUS)
+		timer_ack_irq(n);
+
+	switch (n) {
+	case TIMER_EVENT:
+		if (timer_ctrl & TIMER_IRQ_STATUS) {
+			if (timer_reload_event_high())
+				return;
+		}
+		process_timers(0);
+		break;
+	case TIMER_SYSTEM:
+		/* If this is a hardware irq, check overflow */
+		if (timer_ctrl & TIMER_IRQ_STATUS) {
+			if (sys_high) {
+				sys_high--;
+				process_timers(0);
+			} else {
+				/* Overflow, reload system timer */
+				sys_high = TIMER_CLOCK_MHZ - 1;
+				process_timers(1);
+			}
+		} else {
+			process_timers(0);
+		}
+		break;
+	default:
+		return;
+	}
+}
+
+#define DECLARE_TIMER_IRQ(n)                                     \
+	DECLARE_IRQ(IRQ_TIMER(n), __hw_clock_source_irq_##n, 2); \
+	static void __hw_clock_source_irq_##n(void)              \
+	{                                                        \
+		__hw_clock_source_irq(n);                        \
+	}
+
+DECLARE_TIMER_IRQ(0);
+DECLARE_TIMER_IRQ(1);
+DECLARE_TIMER_IRQ(2);
+DECLARE_TIMER_IRQ(3);
+DECLARE_TIMER_IRQ(4);
+DECLARE_TIMER_IRQ(5);
diff --git a/chip/mt_scp/mt818x/ipi.c b/chip/mt_scp/mt818x/ipi.c
new file mode 100644
index 0000000000..d0d9292fd1
--- /dev/null
+++ b/chip/mt_scp/mt818x/ipi.c
@@ -0,0 +1,398 @@
+/* Copyright 2018 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Inter-Processor Communication (IPC) and Inter-Processor Interrupt (IPI)
+ *
+ * IPC is a communication bridge between AP and SCP.  AP/SCP sends an IPC
+ * interrupt to SCP/AP to inform to collect the commmunication mesesages in the
+ * shared buffer.
+ *
+ * There are 4 IPCs in the current architecture, from IPC0 to IPC3.  The
+ * priority of IPC is proportional to its IPC index. IPC3 has the highest
+ * priority and IPC0 has the lowest one.
+ *
+ * IPC0 may contain zero or more IPIs.  Each IPI represents a task or a service,
+ * e.g. host command, or video encoding.  IPIs are recognized by IPI ID, which
+ * should sync across AP and SCP.  Shared buffer should designated which IPI
+ * ID it talks to.
+ *
+ * Currently, we don't have IPC handlers for IPC1, IPC2, and IPC3.
+ */
+
+#include "clock_chip.h"
+#include "console.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "hwtimer.h"
+#include "ipi_chip.h"
+#include "mkbp_event.h"
+#include "power.h"
+#include "system.h"
+#include "task.h"
+#include "util.h"
+#include "video.h"
+
+#define CPRINTF(format, args...) cprintf(CC_IPI, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_IPI, format, ##args)
+
+#define IPI_MAX_REQUEST_SIZE CONFIG_IPC_SHARED_OBJ_BUF_SIZE
+/* Reserve 1 extra byte for HOSTCMD_TYPE and 3 bytes for padding. */
+#define IPI_MAX_RESPONSE_SIZE (CONFIG_IPC_SHARED_OBJ_BUF_SIZE - 4)
+#define HOSTCMD_TYPE_HOSTCMD 1
+#define HOSTCMD_TYPE_HOSTEVENT 2
+
+static volatile int16_t ipc0_enabled_count;
+static struct mutex ipc0_lock;
+static struct mutex ipi_lock;
+/* IPC0 shared objects, including send object and receive object. */
+static struct ipc_shared_obj *const scp_send_obj =
+	(struct ipc_shared_obj *)CONFIG_IPC_SHARED_OBJ_ADDR;
+static struct ipc_shared_obj *const scp_recv_obj =
+	(struct ipc_shared_obj *)(CONFIG_IPC_SHARED_OBJ_ADDR +
+				  sizeof(struct ipc_shared_obj));
+static char ipi_ready;
+
+#ifdef HAS_TASK_HOSTCMD
+/*
+ * hostcmd and hostevent share the same IPI ID, and use first byte type to
+ * indicate its type.
+ */
+static struct hostcmd_data {
+	const uint8_t type;
+	/* To be compatible with CONFIG_HOSTCMD_ALIGNED */
+	uint8_t response[IPI_MAX_RESPONSE_SIZE] __aligned(4);
+} hc_cmd_obj = { .type = HOSTCMD_TYPE_HOSTCMD };
+BUILD_ASSERT(sizeof(struct hostcmd_data) == CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
+
+static struct host_packet ipi_packet;
+#endif
+
+/* Check if SCP to AP IPI is in use. */
+static inline int is_ipi_busy(void)
+{
+	return SCP_HOST_INT & IPC_SCP2HOST_BIT;
+}
+
+/* If IPI is declared as a wake-up source, wake AP up. */
+static inline void try_to_wakeup_ap(int32_t id)
+{
+#ifdef CONFIG_RPMSG_NAME_SERVICE
+	if (id == IPI_NS_SERVICE)
+		return;
+#endif
+
+	if (*ipi_wakeup_table[id])
+		SCP_SPM_INT = SPM_INT_A2SPM;
+}
+
+void ipi_disable_irq(int irq)
+{
+	/* Only support SCP_IRQ_IPC0 for now. */
+	if (irq != SCP_IRQ_IPC0)
+		return;
+
+	mutex_lock(&ipc0_lock);
+
+	if ((--ipc0_enabled_count) == 0)
+		task_disable_irq(irq);
+
+	mutex_unlock(&ipc0_lock);
+}
+
+void ipi_enable_irq(int irq)
+{
+	/* Only support SCP_IRQ_IPC0 for now. */
+	if (irq != SCP_IRQ_IPC0)
+		return;
+
+	mutex_lock(&ipc0_lock);
+
+	if ((++ipc0_enabled_count) == 1) {
+		int pending_ipc = SCP_GIPC_IN & SCP_GPIC_IN_CLEAR_ALL;
+
+		task_enable_irq(irq);
+
+		if (ipi_ready && pending_ipc)
+			/*
+			 * IPC may be triggered while SCP_IRQ_IPC0 was disabled.
+			 * AP will still updates SCP_GIPC_IN.
+			 * Trigger the IRQ handler if it has a
+			 * pending IPC.
+			 */
+			task_trigger_irq(irq);
+	}
+
+	mutex_unlock(&ipc0_lock);
+}
+
+__override void
+power_chipset_handle_host_sleep_event(enum host_sleep_event state,
+				      struct host_sleep_event_context *ctx)
+{
+	int i;
+	const task_id_t s3_suspend_tasks[] = {
+#ifndef S3_SUSPEND_TASK_LIST
+#define S3_SUSPEND_TASK_LIST
+#endif
+#define TASK(n, ...) TASK_ID_##n,
+		S3_SUSPEND_TASK_LIST
+	};
+
+	if (state == HOST_SLEEP_EVENT_S3_SUSPEND) {
+		ccprints("AP suspend");
+		/*
+		 * On AP suspend, Vcore is 0.6V, and we should not use ULPOSC2,
+		 * which needs at least 0.7V.  Switch to ULPOSC1 instead.
+		 */
+		scp_use_clock(SCP_CLK_ULPOSC1);
+
+		for (i = 0; i < ARRAY_SIZE(s3_suspend_tasks); ++i)
+			task_disable_task(s3_suspend_tasks[i]);
+	} else if (state == HOST_SLEEP_EVENT_S3_RESUME) {
+		ccprints("AP resume");
+		/* Vcore is raised to >=0.7V, switch back to ULPSOC2 */
+		scp_use_clock(SCP_CLK_ULPOSC2);
+
+		for (i = 0; i < ARRAY_SIZE(s3_suspend_tasks); ++i)
+			task_enable_task(s3_suspend_tasks[i]);
+	}
+}
+
+/* Send data from SCP to AP. */
+int ipi_send(int32_t id, const void *buf, uint32_t len, int wait)
+{
+	if (!ipi_ready)
+		return EC_ERROR_BUSY;
+
+	/* TODO(b:117917141): Remove this check completely. */
+	if (in_interrupt_context()) {
+		CPRINTS("Err: invoke %s() in ISR CTX", __func__);
+		return EC_ERROR_BUSY;
+	}
+
+	if (len > sizeof(scp_send_obj->buffer))
+		return EC_ERROR_INVAL;
+
+	ipi_disable_irq(SCP_IRQ_IPC0);
+	mutex_lock(&ipi_lock);
+
+	/* Check if there is already an IPI pending in AP. */
+	if (is_ipi_busy()) {
+		/*
+		 * If the following conditions meet,
+		 *   1) There is an IPI pending in AP.
+		 *   2) The incoming IPI is a wakeup IPI.
+		 * then it assumes that AP is in suspend state.
+		 * Send a AP wakeup request to SPM.
+		 *
+		 * The incoming IPI will be checked if it's a wakeup source.
+		 */
+		try_to_wakeup_ap(id);
+
+		mutex_unlock(&ipi_lock);
+		ipi_enable_irq(SCP_IRQ_IPC0);
+		CPRINTS("Err: IPI Busy, %d", id);
+
+		return EC_ERROR_BUSY;
+	}
+
+	scp_send_obj->id = id;
+	scp_send_obj->len = len;
+	memcpy(scp_send_obj->buffer, buf, len);
+
+	/* Send IPI to AP: interrutp AP to receive IPI messages. */
+	try_to_wakeup_ap(id);
+	SCP_HOST_INT = IPC_SCP2HOST_BIT;
+
+	while (wait && is_ipi_busy())
+		;
+
+	mutex_unlock(&ipi_lock);
+	ipi_enable_irq(SCP_IRQ_IPC0);
+
+	return EC_SUCCESS;
+}
+
+static void ipi_handler(void)
+{
+	if (scp_recv_obj->id >= IPI_COUNT) {
+		CPRINTS("#ERR IPI %d", scp_recv_obj->id);
+		return;
+	}
+
+	/*
+	 * Only print IPI that is not host command channel, which will
+	 * be printed by host command driver.
+	 */
+	if (scp_recv_obj->id != IPI_HOST_COMMAND)
+		CPRINTS("IPI %d", scp_recv_obj->id);
+
+	/*
+	 * Pass the buffer to handler. Each handler should be in charge of
+	 * the buffer copying/reading before returning from handler.
+	 */
+	ipi_handler_table[scp_recv_obj->id](
+		scp_recv_obj->id, scp_recv_obj->buffer, scp_recv_obj->len);
+}
+
+void ipi_inform_ap(void)
+{
+	struct scp_run_t scp_run;
+	int ret;
+#ifdef CONFIG_RPMSG_NAME_SERVICE
+	struct rpmsg_ns_msg ns_msg;
+#endif
+
+	scp_run.signaled = 1;
+	strncpy(scp_run.fw_ver, system_get_version(EC_IMAGE_RW),
+		SCP_FW_VERSION_LEN);
+#ifdef HAVE_PRIVATE_MT8183
+	scp_run.dec_capability = VCODEC_CAPABILITY_4K_DISABLED;
+#else
+	scp_run.dec_capability = video_get_dec_capability();
+#endif
+	scp_run.enc_capability = 0;
+
+	ret = ipi_send(IPI_SCP_INIT, (void *)&scp_run, sizeof(scp_run), 1);
+
+	if (ret)
+		ccprintf("Failed to send initialization IPC messages.\n");
+
+#ifdef CONFIG_RPMSG_NAME_SERVICE
+	ns_msg.id = IPI_HOST_COMMAND;
+	strncpy(ns_msg.name, "cros-ec-rpmsg", RPMSG_NAME_SIZE);
+	ret = ipi_send(IPI_NS_SERVICE, &ns_msg, sizeof(ns_msg), 1);
+	if (ret)
+		ccprintf("Failed to announce host command channel.\n");
+#endif
+}
+
+#ifdef HAS_TASK_HOSTCMD
+#if defined(CONFIG_MKBP_USE_CUSTOM)
+int mkbp_set_host_active_via_custom(int active, uint32_t *timestamp)
+{
+	static const uint8_t hc_evt_obj = HOSTCMD_TYPE_HOSTEVENT;
+
+	/* This should be moved into ipi_send for more accuracy */
+	if (timestamp)
+		*timestamp = __hw_clock_source_read();
+
+	if (active)
+		return ipi_send(IPI_HOST_COMMAND, &hc_evt_obj,
+				sizeof(hc_evt_obj), 1);
+	return EC_SUCCESS;
+}
+#endif
+
+static void ipi_send_response_packet(struct host_packet *pkt)
+{
+	int ret;
+
+	ret = ipi_send(IPI_HOST_COMMAND, &hc_cmd_obj,
+		       pkt->response_size +
+			       offsetof(struct hostcmd_data, response),
+		       1);
+	if (ret)
+		CPRINTS("#ERR IPI HOSTCMD %d", ret);
+}
+
+static void ipi_hostcmd_handler(int32_t id, void *buf, uint32_t len)
+{
+	uint8_t *in_msg = buf;
+	struct ec_host_request *r = (struct ec_host_request *)in_msg;
+	int i;
+
+	if (in_msg[0] != EC_HOST_REQUEST_VERSION) {
+		CPRINTS("ERROR: Protocol V2 is not supported!");
+		CPRINTF("in_msg=[");
+		for (i = 0; i < len; i++)
+			CPRINTF("%02x ", in_msg[i]);
+		CPRINTF("]\n");
+		return;
+	}
+
+	/* Protocol version 3 */
+
+	ipi_packet.send_response = ipi_send_response_packet;
+
+	/*
+	 * Just assign the buffer to request, host_packet_receive
+	 * handles the buffer copy.
+	 */
+	ipi_packet.request = (void *)r;
+	ipi_packet.request_temp = NULL;
+	ipi_packet.request_max = IPI_MAX_REQUEST_SIZE;
+	ipi_packet.request_size = host_request_expected_size(r);
+
+	ipi_packet.response = hc_cmd_obj.response;
+	/* Reserve space for the preamble and trailing byte */
+	ipi_packet.response_max = IPI_MAX_RESPONSE_SIZE;
+	ipi_packet.response_size = 0;
+
+	ipi_packet.driver_result = EC_RES_SUCCESS;
+
+	host_packet_receive(&ipi_packet);
+}
+DECLARE_IPI(IPI_HOST_COMMAND, ipi_hostcmd_handler, 0);
+
+/*
+ * Get protocol information
+ */
+static enum ec_status ipi_get_protocol_info(struct host_cmd_handler_args *args)
+{
+	struct ec_response_get_protocol_info *r = args->response;
+
+	memset(r, 0, sizeof(*r));
+	r->protocol_versions |= BIT(3);
+	r->max_request_packet_size = IPI_MAX_REQUEST_SIZE;
+	r->max_response_packet_size = IPI_MAX_RESPONSE_SIZE;
+
+	args->response_size = sizeof(*r);
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, ipi_get_protocol_info,
+		     EC_VER_MASK(0));
+#endif
+
+static void ipi_enable_ipc0_deferred(void)
+{
+	/* Clear IPC0 IRQs. */
+	SCP_GIPC_IN = SCP_GPIC_IN_CLEAR_ALL;
+
+	/* All tasks are up, we can safely enable IPC0 IRQ now. */
+	SCP_INTC_IRQ_ENABLE |= IPC0_IRQ_EN;
+	ipi_enable_irq(SCP_IRQ_IPC0);
+
+	ipi_ready = 1;
+
+	/* Inform AP that SCP is inited.  */
+	ipi_inform_ap();
+
+	CPRINTS("ipi init");
+}
+DECLARE_DEFERRED(ipi_enable_ipc0_deferred);
+
+/* Initialize IPI. */
+static void ipi_init(void)
+{
+	/* Clear send share buffer. */
+	memset(scp_send_obj, 0, sizeof(struct ipc_shared_obj));
+
+	/* Enable IRQ after all tasks are up.  */
+	hook_call_deferred(&ipi_enable_ipc0_deferred_data, 0);
+}
+DECLARE_HOOK(HOOK_INIT, ipi_init, HOOK_PRIO_DEFAULT);
+
+DECLARE_IRQ(SCP_IRQ_IPC0, ipc_handler, 4);
+static void ipc_handler(void)
+{
+	/* TODO(b/117917141): We only support IPC_ID(0) for now. */
+	if (SCP_GIPC_IN & SCP_GIPC_IN_CLEAR_IPCN(0)) {
+		ipi_handler();
+		SCP_GIPC_IN &= SCP_GIPC_IN_CLEAR_IPCN(0);
+	}
+
+	SCP_GIPC_IN &= (SCP_GPIC_IN_CLEAR_ALL & ~SCP_GIPC_IN_CLEAR_IPCN(0));
+}
diff --git a/chip/mt_scp/mt818x/ipi_chip.h b/chip/mt_scp/mt818x/ipi_chip.h
new file mode 100644
index 0000000000..37be00dabb
--- /dev/null
+++ b/chip/mt_scp/mt818x/ipi_chip.h
@@ -0,0 +1,111 @@
+/* Copyright 2018 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_IPI_CHIP_H
+#define __CROS_EC_IPI_CHIP_H
+
+#include "common.h"
+#include "registers.h"
+
+#define IPC_MAX 1
+#define IPC_ID(n) (n)
+
+/*
+ * Length of EC version string is at most 32 byte (NULL included), which
+ * also aligns SCP fw_version length.
+ */
+#define SCP_FW_VERSION_LEN 32
+
+/*
+ * Video decoder supported capability:
+ * BIT(4): 0 enable 4K
+ *         1 disable 4K
+ */
+#define VCODEC_CAPABILITY_4K_DISABLED BIT(4)
+
+#ifndef IPI_SCP_INIT
+#error If CONFIG_IPI is enabled, IPI_SCP_INIT must be defined.
+#endif
+
+/*
+ * Share buffer layout for IPI_SCP_INIT response. This structure should sync
+ * across kernel and EC.
+ */
+struct scp_run_t {
+	uint32_t signaled;
+	int8_t fw_ver[SCP_FW_VERSION_LEN];
+	uint32_t dec_capability;
+	uint32_t enc_capability;
+};
+
+/*
+ * The layout of the IPC0 AP/SCP shared buffer.
+ * This should sync across kernel and EC.
+ */
+struct ipc_shared_obj {
+	/* IPI ID */
+	int32_t id;
+	/* Length of the contents in buffer. */
+	uint32_t len;
+	/* Shared buffer contents. */
+	uint8_t buffer[CONFIG_IPC_SHARED_OBJ_BUF_SIZE];
+};
+
+/* Send a IPI contents to AP. This shouldn't be used in ISR context. */
+int ipi_send(int32_t id, const void *buf, uint32_t len, int wait);
+
+/* Size of the rpmsg device name, should sync across kernel and EC. */
+#define RPMSG_NAME_SIZE 32
+
+/*
+ * The layout of name service message.
+ * This should sync across kernel and EC.
+ */
+struct rpmsg_ns_msg {
+	/* Name of the corresponding rpmsg_driver. */
+	char name[RPMSG_NAME_SIZE];
+	/* IPC ID */
+	uint32_t id;
+};
+
+/*
+ * An IPC IRQ could be shared across many IPI handlers.
+ * Those handlers would usually operate on disabling or enabling the IPC IRQ.
+ * This may disorder the actual timing to on/off the IRQ when there are many
+ * tasks try to operate on it.  As a result, any access to the SCP_IRQ_*
+ * should go through ipi_{en,dis}able_irq(), which support a counter to
+ * enable/disable the IRQ at correct timeing.
+ */
+/* Disable IPI IRQ. */
+void ipi_disable_irq(int irq);
+/* Enable IPI IRQ. */
+void ipi_enable_irq(int irq);
+
+/* IPI tables */
+extern void (*ipi_handler_table[])(int32_t, void *, uint32_t);
+extern int *ipi_wakeup_table[];
+
+/* Helper macros to build the IPI handler and wakeup functions. */
+#define IPI_HANDLER(id) CONCAT3(ipi_, id, _handler)
+#define IPI_WAKEUP(id) CONCAT3(ipi_, id, _wakeup)
+
+/*
+ * Macro to declare an IPI handler.
+ * _id: The ID of the IPI
+ * handler: The IPI handler function
+ * is_wakeup_src: Declare IPI ID as a wake-up source or not
+ */
+#define DECLARE_IPI(_id, handler, is_wakeup_src)                             \
+	struct ipi_num_check##_id {                                          \
+		int tmp1[_id < IPI_COUNT ? 1 : -1];                          \
+		int tmp2[is_wakeup_src == 0 || is_wakeup_src == 1 ? 1 : -1]; \
+	};                                                                   \
+	void __keep IPI_HANDLER(_id)(int32_t id, void *buf, uint32_t len)    \
+	{                                                                    \
+		handler(id, buf, len);                                       \
+	}                                                                    \
+	const int __keep IPI_WAKEUP(_id) = is_wakeup_src
+
+#endif /* __CROS_EC_IPI_CHIP_H */
diff --git a/chip/mt_scp/mt818x/ipi_table.c b/chip/mt_scp/mt818x/ipi_table.c
new file mode 100644
index 0000000000..153b8b8dbc
--- /dev/null
+++ b/chip/mt_scp/mt818x/ipi_table.c
@@ -0,0 +1,70 @@
+/* Copyright 2018 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * IPI handlers declaration
+ */
+
+#include "common.h"
+#include "ipi_chip.h"
+
+typedef void (*ipi_handler_t)(int32_t id, void *data, uint32_t len);
+
+#ifndef PASS
+#define PASS 1
+#endif
+
+#define ipi_arguments int32_t id, void *data, uint32_t len
+
+#if PASS == 1
+void ipi_handler_undefined(ipi_arguments)
+{
+}
+
+const int ipi_wakeup_undefined;
+
+#define table(type, name, x) x
+
+#define ipi_x_func(suffix, args, number)                                    \
+	extern void                                                         \
+		__attribute__((used, weak,                                  \
+			       alias(STRINGIFY(ipi_##suffix##_undefined)))) \
+		ipi_##number##_##suffix(args);
+
+#define ipi_x_var(suffix, number)                                              \
+	extern int __attribute__((weak,                                        \
+				  alias(STRINGIFY(ipi_##suffix##_undefined)))) \
+	ipi_##number##_##suffix;
+
+#endif /* PASS == 1 */
+
+#if PASS == 2
+
+#undef table
+#undef ipi_x_func
+#undef ipi_x_var
+
+#define table(type, name, x)     \
+	type name[] __aligned(4) \
+		__attribute__((section(".rodata.ipi, \"a\" @"))) = { x }
+
+#define ipi_x_var(suffix, number) \
+	[number < IPI_COUNT ? number : -1] = &ipi_##number##_##suffix,
+
+#define ipi_x_func(suffix, args, number) ipi_x_var(suffix, number)
+
+#endif /* PASS == 2 */
+
+/*
+ * Include generated IPI table (by util/gen_ipi_table). The contents originate
+ * from IPI_COUNT definition in board.h
+ */
+#include "ipi_table_gen.inc"
+
+#if PASS == 1
+#undef PASS
+#define PASS 2
+#include "ipi_table.c"
+BUILD_ASSERT(ARRAY_SIZE(ipi_handler_table) == IPI_COUNT);
+BUILD_ASSERT(ARRAY_SIZE(ipi_wakeup_table) == IPI_COUNT);
+#endif
diff --git a/chip/mt_scp/mt818x/memmap.c b/chip/mt_scp/mt818x/memmap.c
new file mode 100644
index 0000000000..24c0fd8f7a
--- /dev/null
+++ b/chip/mt_scp/mt818x/memmap.c
@@ -0,0 +1,318 @@
+/* Copyright 2018 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * SCP memory map
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "hooks.h"
+#include "memmap.h"
+#include "registers.h"
+#include "task.h"
+#include "util.h"
+
+/*
+ * Map SCP address (bits 31~28) to AP address
+ *
+ * SCP addr    :  AP addr
+ * 0x20000000     0x40000000
+ * 0x30000000     0x50000000
+ * 0x60000000     0x60000000
+ * 0x70000000     0x70000000
+ * 0x80000000     0x80000000
+ * 0x90000000     0x00000000
+ * 0xA0000000     0x10000000
+ * 0xB0000000     0x20000000
+ * 0xC0000000     0x30000000
+ * 0xD0000000     0x10000000
+ * 0xE0000000     0xA0000000
+ * 0xF0000000     0x90000000
+ */
+
+#define MAP_INVALID 0xff
+
+static const uint8_t addr_map[16] = {
+	MAP_INVALID, /* 0x0: SRAM */
+	MAP_INVALID, /* 0x1: Cached access (see below) */
+	0x4,	     0x5, /* 0x2-0x3 */
+	MAP_INVALID, MAP_INVALID, /* 0x4-0x5 (unmapped: registers) */
+	0x6,	     0x7,	  0x8, /* 0x6-0x8 */
+	0x0,	     0x1,	  0x2, 0x3, /* 0x9-0xc */
+	0x1,	     0xa,	  0x9 /* 0xd-0xf */
+};
+
+/*
+ * AP addr     :  SCP cache addr
+ * 0x50000000     0x10000000
+ */
+#define CACHE_TRANS_AP_ADDR 0x50000000
+#define CACHE_TRANS_SCP_CACHE_ADDR 0x10000000
+
+#ifdef CONFIG_DRAM_BASE
+BUILD_ASSERT(CONFIG_DRAM_BASE_LOAD == CACHE_TRANS_AP_ADDR);
+BUILD_ASSERT(CONFIG_DRAM_BASE == CACHE_TRANS_SCP_CACHE_ADDR);
+#endif
+
+static void cpu_invalidate_icache(void)
+{
+	SCP_CACHE_OP(CACHE_ICACHE) &= ~SCP_CACHE_OP_OP_MASK;
+	SCP_CACHE_OP(CACHE_ICACHE) |= OP_INVALIDATE_ALL_LINES | SCP_CACHE_OP_EN;
+	asm volatile("dsb; isb");
+}
+
+void cpu_invalidate_dcache(void)
+{
+	SCP_CACHE_OP(CACHE_DCACHE) &= ~SCP_CACHE_OP_OP_MASK;
+	SCP_CACHE_OP(CACHE_DCACHE) |= OP_INVALIDATE_ALL_LINES | SCP_CACHE_OP_EN;
+	/* Read is necessary to confirm the invalidation finish. */
+	REG32(CACHE_TRANS_SCP_CACHE_ADDR);
+	asm volatile("dsb;");
+}
+
+void cpu_invalidate_dcache_range(uintptr_t base, unsigned int length)
+{
+	size_t pos;
+	uintptr_t addr;
+
+	interrupt_disable();
+
+	for (pos = 0; pos < length; pos += SCP_CACHE_LINE_SIZE) {
+		addr = base + pos;
+		SCP_CACHE_OP(CACHE_DCACHE) = addr & SCP_CACHE_OP_TADDR_MASK;
+		SCP_CACHE_OP(CACHE_DCACHE) |=
+			OP_INVALIDATE_ONE_LINE_BY_ADDRESS | SCP_CACHE_OP_EN;
+		/* Read necessary to confirm the invalidation finish. */
+		REG32(addr);
+	}
+
+	asm volatile("dsb;");
+	interrupt_enable();
+}
+
+void cpu_clean_invalidate_dcache(void)
+{
+	SCP_CACHE_OP(CACHE_DCACHE) &= ~SCP_CACHE_OP_OP_MASK;
+	SCP_CACHE_OP(CACHE_DCACHE) |= OP_CACHE_FLUSH_ALL_LINES |
+				      SCP_CACHE_OP_EN;
+	SCP_CACHE_OP(CACHE_DCACHE) &= ~SCP_CACHE_OP_OP_MASK;
+	SCP_CACHE_OP(CACHE_DCACHE) |= OP_INVALIDATE_ALL_LINES | SCP_CACHE_OP_EN;
+	/* Read necessary to confirm the invalidation finish. */
+	REG32(CACHE_TRANS_SCP_CACHE_ADDR);
+	asm volatile("dsb;");
+}
+
+void cpu_clean_invalidate_dcache_range(uintptr_t base, unsigned int length)
+{
+	size_t pos;
+	uintptr_t addr;
+
+	interrupt_disable();
+	for (pos = 0; pos < length; pos += SCP_CACHE_LINE_SIZE) {
+		addr = base + pos;
+		SCP_CACHE_OP(CACHE_DCACHE) = addr & SCP_CACHE_OP_TADDR_MASK;
+		SCP_CACHE_OP(CACHE_DCACHE) |=
+			OP_CACHE_FLUSH_ONE_LINE_BY_ADDRESS | SCP_CACHE_OP_EN;
+		SCP_CACHE_OP(CACHE_DCACHE) = addr & SCP_CACHE_OP_TADDR_MASK;
+		SCP_CACHE_OP(CACHE_DCACHE) |=
+			OP_INVALIDATE_ONE_LINE_BY_ADDRESS | SCP_CACHE_OP_EN;
+		/* Read necessary to confirm the invalidation finish. */
+		REG32(addr);
+	}
+
+	asm volatile("dsb;");
+	interrupt_enable();
+}
+
+static void scp_cache_init(void)
+{
+	int c;
+	const int region = 0;
+
+	/* First make sure all caches are disabled, and reset stats. */
+	for (c = 0; c < CACHE_COUNT; c++) {
+		/*
+		 * Changing cache-size config may change the SRAM logical
+		 * address in the mean time.  This may break the loaded
+		 * memory layout, and thus break the system.  Cache-size
+		 * should only be be configured in kernel driver before
+		 * laoding the firmware. b/137920815#comment18
+		 */
+		SCP_CACHE_CON(c) &=
+			(SCP_CACHE_CON_CACHESIZE_MASK | SCP_CACHE_CON_WAYEN);
+		SCP_CACHE_REGION_EN(c) = 0;
+		SCP_CACHE_ENTRY(c, region) = 0;
+		SCP_CACHE_END_ENTRY(c, region) = 0;
+
+		/* Reset statistics. */
+		SCP_CACHE_HCNT0U(c) = 0;
+		SCP_CACHE_HCNT0L(c) = 0;
+		SCP_CACHE_CCNT0U(c) = 0;
+		SCP_CACHE_CCNT0L(c) = 0;
+	}
+
+	/* No "normal" remap. */
+	SCP_L1_REMAP_CFG0 = 0;
+	SCP_L1_REMAP_CFG1 = 0;
+	SCP_L1_REMAP_CFG2 = 0;
+	SCP_L1_REMAP_CFG3 = 0;
+	/*
+	 * Setup OTHER1: Remap register for addr msb 31 to 28 equal to 0x1 and
+	 * not overlap with L1C_EXT_ADDR0 to L1C_EXT_ADDR7.
+	 */
+	SCP_L1_REMAP_OTHER =
+		(CACHE_TRANS_AP_ADDR >> SCP_L1_EXT_ADDR_OTHER_SHIFT) << 8;
+
+	/* Disable sleep protect */
+	SCP_SLP_PROTECT_CFG = SCP_SLP_PROTECT_CFG &
+			      ~(P_CACHE_SLP_PROT_EN | D_CACHE_SLP_PROT_EN);
+
+	/* Enable region 0 for both I-cache and D-cache. */
+	for (c = 0; c < CACHE_COUNT; c++) {
+		SCP_CACHE_ENTRY(c, region) = CACHE_TRANS_SCP_CACHE_ADDR;
+		SCP_CACHE_END_ENTRY(c, region) =
+			CACHE_TRANS_SCP_CACHE_ADDR + CACHE_TRANS_AP_SIZE;
+		SCP_CACHE_ENTRY(c, region) |= SCP_CACHE_ENTRY_C;
+
+		SCP_CACHE_REGION_EN(c) |= 1 << region;
+
+		/*
+		 * Enable cache. Note that cache size setting should have been
+		 * done in kernel driver. b/137920815#comment18
+		 */
+		SCP_CACHE_CON(c) |= SCP_CACHE_CON_MCEN | SCP_CACHE_CON_CNTEN0;
+	}
+
+	cpu_invalidate_icache();
+	cpu_invalidate_dcache();
+}
+
+static int command_cacheinfo(int argc, const char **argv)
+{
+	const char cache_name[] = { 'I', 'D' };
+	int c;
+
+	for (c = 0; c < 2; c++) {
+		uint64_t hit = ((uint64_t)SCP_CACHE_HCNT0U(c) << 32) |
+			       SCP_CACHE_HCNT0L(c);
+		uint64_t access = ((uint64_t)SCP_CACHE_CCNT0U(c) << 32) |
+				  SCP_CACHE_CCNT0L(c);
+
+		ccprintf("%ccache hit count:    %llu\n", cache_name[c], hit);
+		ccprintf("%ccache access count: %llu\n", cache_name[c], access);
+	}
+
+	return EC_SUCCESS;
+}
+DECLARE_SAFE_CONSOLE_COMMAND(cacheinfo, command_cacheinfo, NULL,
+			     "Dump cache info");
+
+void scp_memmap_init(void)
+{
+	/*
+	 * Default config, LARGE DRAM not active:
+	 *   REG32(0xA0001F00) & 0x2000 != 0
+	 */
+
+	/*
+	 * SCP_REMAP_CFG1
+	 * EXT_ADDR3[29:24] remap register for addr msb 31~28 equal to 0x7
+	 * EXT_ADDR2[21:16] remap register for addr msb 31~28 equal to 0x6
+	 * EXT_ADDR1[13:8]  remap register for addr msb 31~28 equal to 0x3
+	 * EXT_ADDR0[5:0]   remap register for addr msb 31~28 equal to 0x2
+	 */
+	SCP_REMAP_CFG1 = (uint32_t)addr_map[0x7] << 24 |
+			 (uint32_t)addr_map[0x6] << 16 |
+			 (uint32_t)addr_map[0x3] << 8 | (uint32_t)addr_map[0x2];
+
+	/*
+	 * SCP_REMAP_CFG2
+	 * EXT_ADDR7[29:24] remap register for addr msb 31~28 equal to 0xb
+	 * EXT_ADDR6[21:16] remap register for addr msb 31~28 equal to 0xa
+	 * EXT_ADDR5[13:8]  remap register for addr msb 31~28 equal to 0x9
+	 * EXT_ADDR4[5:0]   remap register for addr msb 31~28 equal to 0x8
+	 */
+	SCP_REMAP_CFG2 = (uint32_t)addr_map[0xb] << 24 |
+			 (uint32_t)addr_map[0xa] << 16 |
+			 (uint32_t)addr_map[0x9] << 8 | (uint32_t)addr_map[0x8];
+	/*
+	 * SCP_REMAP_CFG3
+	 * AUD_ADDR[31:28]  remap register for addr msb 31~28 equal to 0xd
+	 * EXT_ADDR10[21:16]remap register for addr msb 31~28 equal to 0xf
+	 * EXT_ADDR9[13:8]  remap register for addr msb 31~28 equal to 0xe
+	 * EXT_ADDR8[5:0]   remap register for addr msb 31~28 equal to 0xc
+	 */
+	SCP_REMAP_CFG3 = (uint32_t)addr_map[0xd] << 28 |
+			 (uint32_t)addr_map[0xf] << 16 |
+			 (uint32_t)addr_map[0xe] << 8 | (uint32_t)addr_map[0xc];
+
+	/* Initialize cache remapping. */
+	scp_cache_init();
+}
+
+int memmap_ap_to_scp(uintptr_t ap_addr, uintptr_t *scp_addr)
+{
+	int i;
+	uint8_t msb = ap_addr >> SCP_REMAP_ADDR_SHIFT;
+
+	for (i = 0; i < ARRAY_SIZE(addr_map); i++) {
+		if (addr_map[i] != msb)
+			continue;
+
+		*scp_addr = (ap_addr & SCP_REMAP_ADDR_LSB_MASK) |
+			    (i << SCP_REMAP_ADDR_SHIFT);
+		return EC_SUCCESS;
+	}
+
+	return EC_ERROR_INVAL;
+}
+
+int memmap_scp_to_ap(uintptr_t scp_addr, uintptr_t *ap_addr)
+{
+	int i = scp_addr >> SCP_REMAP_ADDR_SHIFT;
+
+	if (addr_map[i] == MAP_INVALID)
+		return EC_ERROR_INVAL;
+
+	*ap_addr = (scp_addr & SCP_REMAP_ADDR_LSB_MASK) |
+		   (addr_map[i] << SCP_REMAP_ADDR_SHIFT);
+	return EC_SUCCESS;
+}
+
+#ifdef CONFIG_DRAM_BASE
+BUILD_ASSERT(CONFIG_DRAM_BASE_LOAD == CACHE_TRANS_AP_ADDR);
+BUILD_ASSERT(CONFIG_DRAM_BASE == CACHE_TRANS_SCP_CACHE_ADDR);
+#endif
+
+int memmap_ap_to_scp_cache(uintptr_t ap_addr, uintptr_t *scp_addr)
+{
+	uintptr_t lsb;
+
+	if ((ap_addr & SCP_L1_EXT_ADDR_OTHER_MSB_MASK) != CACHE_TRANS_AP_ADDR)
+		return EC_ERROR_INVAL;
+
+	lsb = ap_addr & SCP_L1_EXT_ADDR_OTHER_LSB_MASK;
+	if (lsb > CACHE_TRANS_AP_SIZE)
+		return EC_ERROR_INVAL;
+
+	*scp_addr = CACHE_TRANS_SCP_CACHE_ADDR | lsb;
+	return EC_SUCCESS;
+}
+
+int memmap_scp_cache_to_ap(uintptr_t scp_addr, uintptr_t *ap_addr)
+{
+	uintptr_t lsb;
+
+	if ((scp_addr & SCP_L1_EXT_ADDR_OTHER_MSB_MASK) !=
+	    CACHE_TRANS_SCP_CACHE_ADDR)
+		return EC_ERROR_INVAL;
+
+	lsb = scp_addr & SCP_L1_EXT_ADDR_OTHER_LSB_MASK;
+	if (lsb >= CACHE_TRANS_AP_SIZE)
+		return EC_ERROR_INVAL;
+
+	*ap_addr = CACHE_TRANS_AP_ADDR | lsb;
+	return EC_SUCCESS;
+}
diff --git a/chip/mt_scp/mt818x/memmap.h b/chip/mt_scp/mt818x/memmap.h
new file mode 100644
index 0000000000..a3dee1710a
--- /dev/null
+++ b/chip/mt_scp/mt818x/memmap.h
@@ -0,0 +1,51 @@
+/* Copyright 2018 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * SCP memory map
+ */
+
+#ifndef __CROS_EC_MEMMAP_H
+#define __CROS_EC_MEMMAP_H
+
+#include "stdint.h"
+
+void scp_memmap_init(void);
+
+/**
+ * Translate AP addr to SCP addr.
+ *
+ * @param ap_addr		AP address to translate
+ * @param scp_addr		Tranlated AP address
+ * @return			EC_SUCCESS or EC_ERROR_INVAL
+ */
+int memmap_ap_to_scp(uintptr_t ap_addr, uintptr_t *scp_addr);
+
+/**
+ * Translate SCP addr to AP addr.
+ *
+ * @param scp_addr		SCP address to tranlate
+ * @param ap_addr		Translated SCP address
+ * @return			EC_SUCCESS or EC_ERROR_INVAL
+ */
+int memmap_scp_to_ap(uintptr_t scp_addr, uintptr_t *ap_addr);
+
+/**
+ * Translate AP addr to SCP cache addr.
+ *
+ * @param ap_addr		AP address to translate
+ * @param scp_addr		Tranlated AP cache address
+ * @return			EC_SUCCESS or EC_ERROR_INVAL
+ */
+int memmap_ap_to_scp_cache(uintptr_t ap_addr, uintptr_t *scp_addr);
+
+/**
+ * Translate SCP addr to AP addr.
+ *
+ * @param scp_addr		SCP cache address to tranlate
+ * @param ap_addr		Translated SCP cache address
+ * @return			EC_SUCCESS or EC_ERROR_INVAL
+ */
+int memmap_scp_cache_to_ap(uintptr_t scp_addr, uintptr_t *ap_addr);
+
+#endif /* #ifndef __CROS_EC_MEMMAP_H */
diff --git a/chip/mt_scp/mt818x/registers.h b/chip/mt_scp/mt818x/registers.h
new file mode 100644
index 0000000000..7bfcf184af
--- /dev/null
+++ b/chip/mt_scp/mt818x/registers.h
@@ -0,0 +1,735 @@
+/* Copyright 2018 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Register map for SCP
+ */
+
+#ifndef __CROS_EC_REGISTERS_H
+#define __CROS_EC_REGISTERS_H
+
+#include "common.h"
+#include "compile_time_macros.h"
+
+/* IRQ numbers */
+#define SCP_IRQ_IPC0 0
+#define SCP_IRQ_IPC1 1
+#define SCP_IRQ_IPC2 2
+#define SCP_IRQ_IPC3 3
+#define SCP_IRQ_SPM 4
+#define SCP_IRQ_CIRQ 5
+#define SCP_IRQ_EINT 6
+#define SCP_IRQ_PMIC 7
+#define SCP_IRQ_UART0 8
+#define SCP_IRQ_UART1 9
+#define SCP_IRQ_I2C0 10
+#define SCP_IRQ_I2C1 11
+#define SCP_IRQ_I2C2 12
+#define SCP_IRQ_CLOCK 13
+#define SCP_IRQ_MAD_FIFO 14
+#define SCP_IRQ_TIMER0 15
+#define SCP_IRQ_TIMER1 16
+#define SCP_IRQ_TIMER2 17
+#define SCP_IRQ_TIMER3 18
+#define SCP_IRQ_TIMER4 19
+#define SCP_IRQ_TIMER5 20
+#define SCP_IRQ_TIMER_STATUS 21
+#define SCP_IRQ_UART0_RX 22
+#define SCP_IRQ_UART1_RX 23
+#define SCP_IRQ_DMA 24
+#define SCP_IRQ_AUDIO 25
+#define SCP_IRQ_MD1_F216 26
+#define SCP_IRQ_MD1 27
+#define SCP_IRQ_C2K 28
+#define SCP_IRQ_SPI0 29
+#define SCP_IRQ_SPI1 30
+#define SCP_IRQ_SPI2 31
+#define SCP_IRQ_AP_EINT 32
+#define SCP_IRQ_DEBUG 33
+#define SCP_CCIF0 34
+#define SCP_CCIF1 35
+#define SCP_CCIF2 36
+#define SCP_IRQ_WDT 37
+#define SCP_IRQ_USB0 38
+#define SCP_IRQ_USB1 39
+#define SCP_IRQ_TWAM 40
+#define SCP_IRQ_INFRA 41
+#define SCP_IRQ_HWDVFS_HIGH 42
+#define SCP_IRQ_HWDVFS_LOW 43
+#define SCP_IRQ_CLOCK2 44
+/* RESERVED 45-52 */
+#define SCP_IRQ_AP_EINT2 53
+#define SCP_IRQ_AP_EINT_EVT 54
+#define SCP_IRQ_MAD_DATA 55
+
+#define SCP_CFG_BASE 0x405C0000
+
+#define SCP_AP_RESOURCE REG32(SCP_CFG_BASE + 0x04)
+#define SCP_BUS_RESOURCE REG32(SCP_CFG_BASE + 0x08)
+
+#ifdef CHIP_VARIANT_MT8186
+#define SCP_TCM_LOCK_CFG (CFGREG_BASE + 0x10)
+#endif
+
+/* SCP to host interrupt */
+#define SCP_HOST_INT REG32(SCP_CFG_BASE + 0x1C)
+#define IPC_SCP2HOST_SSHUB 0xff0000
+#define WDT_INT 0x100
+#define IPC_SCP2HOST 0xff
+#define IPC_SCP2HOST_BIT 0x1
+
+/* SCP to SPM interrupt */
+#define SCP_SPM_INT REG32(SCP_CFG_BASE + 0x20)
+#define SPM_INT_A2SPM BIT(0)
+#define SPM_INT_B2SPM BIT(1)
+#define SCP_SPM_INT2 REG32(SCP_CFG_BASE + 0x24)
+
+/*
+ * AP side to SCP IPC
+ * APMCU writes 1 bit to trigger ith IPC to SCP.
+ * SCP writes 1 bit to ith bit to clear ith IPC.
+ */
+#define SCP_GIPC_IN REG32(SCP_CFG_BASE + 0x28)
+#define SCP_GIPC_IN_CLEAR_IPCN(n) (1 << (n))
+#define SCP_GPIC_IN_CLEAR_ALL 0x7FFFF
+#define SCP_CONN_INT REG32(SCP_CFG_BASE + 0x2C)
+
+/* 8 general purpose registers, 0 ~ 7 */
+#define SCP_GPR REG32_ADDR(SCP_CFG_BASE + 0x50)
+/*
+ * SCP_GPR[0]
+ *   b15-b0   : scratchpad
+ *   b31-b16  : saved flags
+ * SCP_GPR[1]
+ *   b15-b0   : power on state
+ */
+#define SCP_PWRON_STATE SCP_GPR[1]
+#define PWRON_DEFAULT 0xdee80000
+#define PWRON_WATCHDOG BIT(0)
+#define PWRON_RESET BIT(1)
+/* AP defined features */
+#define SCP_EXPECTED_FREQ SCP_GPR[3]
+#define SCP_CURRENT_FREQ SCP_GPR[4]
+#define SCP_REBOOT SCP_GPR[5]
+#define READY_TO_REBOOT 0x34
+#define REBOOT_OK 1
+
+/* Miscellaneous */
+#define SCP_SEMAPHORE REG32(SCP_CFG_BASE + 0x90)
+#define CORE_CONTROL REG32(SCP_CFG_BASE + 0xA0)
+#define CORE_FPU_FLAGS REG32(SCP_CFG_BASE + 0xA4)
+#define CORE_REG_SP REG32(SCP_CFG_BASE + 0xA8)
+#define CORE_REG_LR REG32(SCP_CFG_BASE + 0xAC)
+#define CORE_REG_PSP REG32(SCP_CFG_BASE + 0xB0)
+#define CORE_REG_PC REG32(SCP_CFG_BASE + 0xB4)
+#define SCP_SLP_PROTECT_CFG REG32(SCP_CFG_BASE + 0xC8)
+#define P_CACHE_SLP_PROT_EN BIT(3)
+#define D_CACHE_SLP_PROT_EN BIT(4)
+#define SCP_ONE_TIME_LOCK REG32(SCP_CFG_BASE + 0xDC)
+#define SCP_SECURE_CTRL REG32(SCP_CFG_BASE + 0xE0)
+
+#ifdef CHIP_VARIANT_MT8186
+#define JTAG_DBG_REQ_BIT BIT(3)
+#define DISABLE_REMAP BIT(31)
+#else
+#define DISABLE_REMAP BIT(22)
+#endif
+
+#define ENABLE_SPM_MASK_VREQ BIT(28)
+#define DISABLE_JTAG BIT(21)
+#define DISABLE_AP_TCM BIT(20)
+#define SCP_SYS_CTRL REG32(SCP_CFG_BASE + 0xE4)
+#define DDREN_FIX_VALUE BIT(28)
+#define AUTO_DDREN BIT(18)
+
+/* Memory remap control */
+/*
+ * EXT_ADDR3[29:24] remap register for addr msb 31~28 equal to 0x7
+ * EXT_ADDR2[21:16] remap register for addr msb 31~28 equal to 0x6
+ * EXT_ADDR1[13:8]  remap register for addr msb 31~28 equal to 0x3
+ * EXT_ADDR0[5:0]   remap register for addr msb 31~28 equal to 0x2
+ */
+#define SCP_REMAP_CFG1 REG32(SCP_CFG_BASE + 0x120)
+/*
+ * EXT_ADDR7[29:24] remap register for addr msb 31~28 equal to 0xb
+ * EXT_ADDR6[21:16] remap register for addr msb 31~28 equal to 0xa
+ * EXT_ADDR5[13:8]  remap register for addr msb 31~28 equal to 0x9
+ * EXT_ADDR4[5:0]   remap register for addr msb 31~28 equal to 0x8
+ */
+#define SCP_REMAP_CFG2 REG32(SCP_CFG_BASE + 0x124)
+/*
+ * AUD_ADDR[31:28]  remap register for addr msb 31~28 equal to 0xd
+ * EXT_ADDR10[21:16]remap register for addr msb 31~28 equal to 0xf
+ * EXT_ADDR9[13:8]  remap register for addr msb 31~28 equal to 0xe
+ * EXT_ADDR8[5:0]   remap register for addr msb 31~28 equal to 0xc
+ */
+#define SCP_REMAP_CFG3 REG32(SCP_CFG_BASE + 0x128)
+
+#define SCP_REMAP_ADDR_SHIFT 28
+#define SCP_REMAP_ADDR_LSB_MASK (BIT(SCP_REMAP_ADDR_SHIFT) - 1)
+#define SCP_REMAP_ADDR_MSB_MASK ((~0) << SCP_REMAP_ADDR_SHIFT)
+
+/* Cached memory remap control */
+#define SCP_L1_REMAP_CFG0 REG32(SCP_CFG_BASE + 0x12C)
+/*
+ * L1C_EXT_ADDR1[29:16] remap register for addr msb 31~20 equal to 0x401
+ * L1C_EXT_ADDR0[13:0]  remap register for addr msb 31~20 equal to 0x400
+ */
+#define SCP_L1_REMAP_CFG1 REG32(SCP_CFG_BASE + 0x130)
+/*
+ * L1C_EXT_ADDR3[29:16] remap register for addr msb 31~20 equal to 0x403
+ * L1C_EXT_ADDR2[13:0]  remap register for addr msb 31~20 equal to 0x402
+ */
+#define SCP_L1_REMAP_CFG2 REG32(SCP_CFG_BASE + 0x134)
+/*
+ * L1C_EXT_ADDR5[29:16] remap register for addr msb 31~20 equal to 0x405
+ * L1C_EXT_ADDR4[13:0]  remap register for addr msb 31~20 equal to 0x404
+ */
+#define SCP_L1_REMAP_CFG3 REG32(SCP_CFG_BASE + 0x138)
+/*
+ * L1C_EXT_ADDR_OTHER1[13:8] Remap register for addr msb 31 to 28 equal to 0x1
+ * L1C_EXT_ADDR_OTHER0[5:0] Remap register for addr msb 31 to 28 equal to 0x0
+ * and not overlap with L1C_EXT_ADDR0 to L1C_EXT_ADDR7
+ */
+#define SCP_L1_REMAP_OTHER REG32(SCP_CFG_BASE + 0x13C)
+
+#define SCP_L1_EXT_ADDR_SHIFT 20
+#define SCP_L1_EXT_ADDR_OTHER_SHIFT 28
+#define SCP_L1_EXT_ADDR_OTHER_LSB_MASK (BIT(SCP_REMAP_ADDR_SHIFT) - 1)
+#define SCP_L1_EXT_ADDR_OTHER_MSB_MASK ((~0) << SCP_REMAP_ADDR_SHIFT)
+
+/* Audio/voice FIFO */
+#define SCP_AUDIO_BASE (SCP_CFG_BASE + 0x1000)
+#define SCP_VIF_FIFO_EN REG32(SCP_AUDIO_BASE)
+#define VIF_FIFO_RSTN (1 << 0)
+#define VIF_FIFO_IRQ_EN (1 << 1)
+#define VIF_FIFO_SRAM_PWR (1 << 2)
+#define VIF_FIFO_RSTN_STATUS (1 << 4)
+#define SCP_VIF_FIFO_STATUS REG32(SCP_AUDIO_BASE + 0x04)
+#define VIF_FIFO_VALID (1 << 0)
+#define VIF_FIFO_FULL (1 << 4)
+#define VIF_FIFO_LEVEL(status) (((status) >> 16) & 0xff)
+#define VIF_FIFO_MAX 256
+#define SCP_VIF_FIFO_DATA REG32(SCP_AUDIO_BASE + 0x08)
+#define SCP_VIF_FIFO_DATA_THRE REG32(SCP_AUDIO_BASE + 0x0C)
+/* VIF IRQ status clears on read! */
+#define SCP_VIF_FIFO_IRQ_STATUS REG32(SCP_AUDIO_BASE + 0x10)
+/* Audio/voice serial interface */
+#define SCP_RXIF_CFG0 REG32(SCP_AUDIO_BASE + 0x14)
+#define RXIF_CFG0_RESET_VAL 0x2A130001
+#define RXIF_AFE_ON (1 << 0)
+#define RXIF_SCKINV (1 << 1)
+#define RXIF_RG_DL_2_IN_MODE(mode) (((mode)&0xf) << 8)
+#define RXIF_RGDL2_AMIC_16K (0x1 << 8)
+#define RXIF_RGDL2_DMIC_16K (0x2 << 8)
+#define RXIF_RGDL2_DMIC_LP_16K (0x3 << 8)
+#define RXIF_RGDL2_AMIC_32K (0x5 << 8)
+#define RXIF_RGDL2_MASK (0xf << 8)
+#define RXIF_UP8X_RSP(p) (((p)&0x7) << 16)
+#define RXIF_RG_RX_READEN (1 << 19)
+#define RXIF_MONO (1 << 20)
+#define RXIF_RG_CLK_A16P7K_EN(cnt) (((cnt)&0xff) << 24)
+#define SCP_RXIF_CFG1 REG32(SCP_AUDIO_BASE + 0x18)
+#define RXIF_CFG1_RESET_VAL 0x33180014
+#define RXIF_RG_SYNC_CNT_TBL(t) ((t)&0x1ff)
+#define RXIF_RG_SYNC_SEARCH_TBL(t) (((t)&0x1f) << 16)
+#define RXIF_RG_SYNC_CHECK_ROUND(r) (((r)&0xf) << 24)
+#define RXIF_RG_INSYNC_CHECK_ROUND(r) (((r)&0xf) << 28)
+#define SCP_RXIF_CFG2 REG32(SCP_AUDIO_BASE + 0x1C)
+#define RXIF_SYNC_WORD(w) ((w)&0xffff)
+#define SCP_RXIF_OUT REG32(SCP_AUDIO_BASE + 0x20)
+#define SCP_RXIF_STATUS REG32(SCP_AUDIO_BASE + 0x24)
+#define SCP_RXIF_IRQ_EN REG32(SCP_AUDIO_BASE + 0x28)
+
+/* INTC control */
+#define SCP_INTC_BASE (SCP_CFG_BASE + 0x2000)
+#define SCP_INTC_IRQ_STATUS REG32(SCP_INTC_BASE)
+#define SCP_INTC_IRQ_ENABLE REG32(SCP_INTC_BASE + 0x04)
+#define IPC0_IRQ_EN BIT(0)
+#define SCP_INTC_IRQ_OUTPUT REG32(SCP_INTC_BASE + 0x08)
+#define SCP_INTC_IRQ_WAKEUP REG32(SCP_INTC_BASE + 0x0C)
+#define SCP_INTC_NMI REG32(SCP_INTC_BASE + 0x10)
+#define SCP_INTC_SPM_WAKEUP REG32(SCP_INTC_BASE + 0x14)
+#define SCP_INTC_SPM_WAKEUP_MSB REG32(SCP_INTC_BASE + 0x18)
+#define SCP_INTC_UART_RX_IRQ REG32(SCP_INTC_BASE + 0x1C)
+#define SCP_INTC_IRQ_STATUS_MSB REG32(SCP_INTC_BASE + 0x80)
+#define SCP_INTC_IRQ_ENABLE_MSB REG32(SCP_INTC_BASE + 0x84)
+#define SCP_INTC_IRQ_OUTPUT_MSB REG32(SCP_INTC_BASE + 0x88)
+#define SCP_INTC_IRQ_WAKEUP_MSB REG32(SCP_INTC_BASE + 0x8C)
+
+/* Timer */
+#define NUM_TIMERS 6
+#define SCP_TIMER_BASE(n) (SCP_CFG_BASE + 0x3000 + (0x10 * (n)))
+#define SCP_TIMER_EN(n) REG32(SCP_TIMER_BASE(n))
+#define SCP_TIMER_RESET_VAL(n) REG32(SCP_TIMER_BASE(n) + 0x04)
+#define SCP_TIMER_VAL(n) REG32(SCP_TIMER_BASE(n) + 0x08)
+#define SCP_TIMER_IRQ_CTRL(n) REG32(SCP_TIMER_BASE(n) + 0x0C)
+#define TIMER_IRQ_ENABLE BIT(0)
+#define TIMER_IRQ_STATUS BIT(4)
+#define TIMER_IRQ_CLEAR BIT(5)
+#define SCP_TIMER_CLK_SEL(n) REG32(SCP_TIMER_BASE(n) + 0x40)
+#define TIMER_CLK_32K (0 << 4)
+#define TIMER_CLK_26M BIT(4)
+#define TIMER_CLK_BCLK (2 << 4)
+#define TIMER_CLK_PCLK (3 << 4)
+#define TIMER_CLK_MASK (3 << 4)
+/* OS timer */
+#define SCP_OSTIMER_BASE (SCP_CFG_BASE + 0x3080)
+#define SCP_OSTIMER_CON REG32(SCP_OSTIMER_BASE)
+#define SCP_OSTIMER_INIT_L REG32(SCP_OSTIMER_BASE + 0x04)
+#define SCP_OSTIMER_INIT_H REG32(SCP_OSTIMER_BASE + 0x08)
+#define SCP_OSTIMER_VAL_L REG32(SCP_OSTIMER_BASE + 0x0C)
+#define SCP_OSTIMER_VAL_H REG32(SCP_OSTIMER_BASE + 0x10)
+#define SCP_OSTIMER_TVAL REG32(SCP_OSTIMER_BASE + 0x14)
+#define SCP_OSTIMER_IRQ_ACK REG32(SCP_OSTIMER_BASE + 0x18)
+#define OSTIMER_LATCH0_EN BIT(5)
+#define OSTIMER_LATCH1_EN BIT(13)
+#define OSTIMER_LATCH2_EN BIT(21)
+#define SCP_OSTIMER_LATCH_CTRL REG32(SCP_OSTIMER_BASE + 0x20)
+#define SCP_OSTIMER_LATCH0_L REG32(SCP_OSTIMER_BASE + 0x24)
+#define SCP_OSTIMER_LATCH0_H REG32(SCP_OSTIMER_BASE + 0x28)
+#define SCP_OSTIMER_LATCH1_L REG32(SCP_OSTIMER_BASE + 0x2C)
+#define SCP_OSTIMER_LATCH1_H REG32(SCP_OSTIMER_BASE + 0x30)
+#define SCP_OSTIMER_LATCH2_L REG32(SCP_OSTIMER_BASE + 0x34)
+#define SCP_OSTIMER_LATCH2_H REG32(SCP_OSTIMER_BASE + 0x38)
+
+/* Clock, PMIC wrapper, etc. */
+#define SCP_CLK_BASE (SCP_CFG_BASE + 0x4000)
+#define SCP_CLK_SEL REG32(SCP_CLK_BASE)
+#define CLK_SEL_SYS_26M 0
+#define CLK_SEL_32K 1
+#define CLK_SEL_ULPOSC_2 2
+#define CLK_SEL_ULPOSC_1 3
+
+#define SCP_CLK_EN REG32(SCP_CLK_BASE + 0x04)
+#define EN_CLK_SYS BIT(0) /* System clock */
+#define EN_CLK_HIGH BIT(1) /* ULPOSC */
+#define CG_CLK_HIGH BIT(2)
+#define EN_SYS_IRQ BIT(16)
+#define EN_HIGH_IRQ BIT(17)
+#define SCP_CLK_SAFE_ACK REG32(SCP_CLK_BASE + 0x08)
+#define SCP_CLK_ACK REG32(SCP_CLK_BASE + 0x0C)
+#define SCP_CLK_IRQ_ACK REG32(SCP_CLK_BASE + 0x10)
+/*
+ * System clock counter value.
+ * CLK_SYS_VAL[9:0] System clock counter initial/reset value.
+ */
+#define SCP_CLK_SYS_VAL REG32(SCP_CLK_BASE + 0x14)
+#define CLK_SYS_VAL_MASK 0x3ff /* 10 bits */
+#define CLK_SYS_VAL(n) ((n)&CLK_SYS_VAL_MASK)
+/*
+ * ULPOSC clock counter value.
+ * CLK_HIGH_VAL[9:0] ULPOSC clock counter initial/reset value.
+ */
+#define SCP_CLK_HIGH_VAL REG32(SCP_CLK_BASE + 0x18)
+#define CLK_HIGH_VAL_MASK 0x3ff /* 10 bits */
+#define CLK_HIGH_VAL(n) ((n)&CLK_HIGH_VAL_MASK)
+#define SCP_CLK_SLOW_SEL REG32(SCP_CLK_BASE + 0x1C)
+#define CKSW_SEL_SLOW_MASK 0x3
+#define CKSW_SEL_SLOW_DIV_MASK 0x30
+#define CKSW_SEL_SLOW_SYS_CLK 0
+#define CKSW_SEL_SLOW_32K_CLK 1
+#define CKSW_SEL_SLOW_ULPOSC2_CLK 2
+#define CKSW_SEL_SLOW_ULPOSC1_CLK 3
+/*
+ * Sleep mode control.
+ * VREQ_COUNT[7:1] Number of cycles to wait when requesting PMIC to raise the
+ *     voltage after returning from  sleep mode.
+ */
+#define SCP_CLK_SLEEP_CTRL REG32(SCP_CLK_BASE + 0x20)
+#define EN_SLEEP_CTRL BIT(0)
+
+#ifdef CHIP_VARIANT_MT8186
+#define VREQ_COUNTER_MASK 0x7F
+#else
+#define VREQ_COUNTER_MASK 0xfe
+#endif
+
+#define VREQ_COUNTER_VAL(v) (((v) << 1) & VREQ_COUNTER_MASK)
+#define SPM_SLEEP_MODE BIT(8)
+#define SPM_SLEEP_MODE_CLK_AO BIT(9)
+#define SCP_CLK_DIV_SEL REG32(SCP_CLK_BASE + 0x24)
+#define CLK_DIV1 0
+#define CLK_DIV2 1
+#define CLK_DIV4 2
+#define CLK_DIV8 3
+#define SCP_CLK_DEBUG REG32(SCP_CLK_BASE + 0x28)
+#define SCP_CLK_SRAM_POWERDOWN REG32(SCP_CLK_BASE + 0x2C)
+#define SCP_CLK_GATE REG32(SCP_CLK_BASE + 0x30)
+#define CG_TIMER_M BIT(0)
+#define CG_TIMER_B BIT(1)
+#define CG_MAD_M BIT(2)
+#define CG_I2C_M BIT(3)
+#define CG_I2C_B BIT(4)
+#define CG_GPIO_M BIT(5)
+#define CG_AP2P_M BIT(6)
+#define CG_UART_M BIT(7)
+#define CG_UART_B BIT(8)
+#define CG_UART_RSTN BIT(9)
+#define CG_UART1_M BIT(10)
+#define CG_UART1_B BIT(11)
+#define CG_UART1_RSTN BIT(12)
+#define CG_SPI0 BIT(13)
+#define CG_SPI1 BIT(14)
+#define CG_SPI2 BIT(15)
+#define CG_DMA_CH0 BIT(16)
+#define CG_DMA_CH1 BIT(17)
+#define CG_DMA_CH2 BIT(18)
+#define CG_DMA_CH3 BIT(19)
+#define CG_TWAM BIT(20)
+#define CG_CACHE_I_CTRL BIT(21)
+#define CG_CACHE_D_CTRL BIT(22)
+#define SCP_PMICW_CTRL REG32(SCP_CLK_BASE + 0x34)
+#define PMICW_SLEEP_REQ BIT(0)
+#define PMICW_SLEEP_ACK BIT(4)
+#define PMICW_CLK_MUX BIT(8)
+#define PMICW_DCM BIT(9)
+#define SCP_SLEEP_WAKE_DEBUG REG32(SCP_CLK_BASE + 0x38)
+#define SCP_DCM_EN REG32(SCP_CLK_BASE + 0x3C)
+#define SCP_WAKE_CKSW REG32(SCP_CLK_BASE + 0x40)
+
+#define WAKE_CKSW_SEL_SLOW_MASK 0x30
+#define WAKE_CKSW_SEL_SLOW_DEFAULT 0x10
+
+#define WAKE_CKSW_SEL_NORMAL_MASK 0x3
+#define SCP_CLK_UART REG32(SCP_CLK_BASE + 0x44)
+#define CLK_UART_SEL_MASK 0x3
+#define CLK_UART_SEL_26M 0x0
+#define CLK_UART_SEL_32K 0x1
+/* This is named ulposc_div_to_26m in datasheet */
+#define CLK_UART_SEL_ULPOSC1_DIV10 0x2
+#define CLK_UART1_SEL_MASK (0x3 << 16)
+#define CLK_UART1_SEL_26M (0x0 << 16)
+#define CLK_UART1_SEL_32K (0x1 << 16)
+/* This is named ulposc_div_to_26m in datasheet */
+#define CLK_UART1_SEL_ULPOSC1_DIV10 (0x2 << 16)
+#define SCP_CLK_BCLK REG32(SCP_CLK_BASE + 0x48)
+#define CLK_BCLK_SEL_MASK 0x3
+#define CLK_BCLK_SEL_SYS_DIV8 0x0
+#define CLK_BCLK_SEL_32K 0x1
+#define CLK_BCLK_SEL_ULPOSC1_DIV8 0x2
+#define SCP_CLK_SPI_BCK REG32(SCP_CLK_BASE + 0x4C)
+#define SCP_CLK_DIV_CNT REG32(SCP_CLK_BASE + 0x50)
+#define SCP_CPU_VREQ REG32(SCP_CLK_BASE + 0x54)
+#define CPU_VREQ_HW_MODE 0x10001
+
+#ifdef CHIP_VARIANT_MT8186
+#define VREQ_SEL BIT(0)
+#define VREQ_PMIC_WRAP_SEL BIT(1)
+#define VREQ_VALUE BIT(4)
+#define VREQ_EXT_SEL BIT(8)
+#define VREQ_DVFS_SEL BIT(16)
+#define VREQ_DVFS_VALUE BIT(20)
+#define VREQ_DVFS_EXT_SEL BIT(24)
+#define VREQ_SRCLKEN_SEL BIT(27)
+#define VREQ_SRCLKEN_VALUE BIT(28)
+#endif
+
+#define SCP_CLK_CLEAR REG32(SCP_CLK_BASE + 0x58)
+#define SCP_CLK_HIGH_CORE REG32(SCP_CLK_BASE + 0x5C)
+#define CLK_HIGH_CORE_CG (1 << 1)
+#define SCP_SLEEP_IRQ2 REG32(SCP_CLK_BASE + 0x64)
+#define SCP_CLK_ON_CTRL REG32(SCP_CLK_BASE + 0x6C)
+#define HIGH_AO BIT(0)
+#define HIGH_CG_AO BIT(2)
+#define HIGH_CORE_AO BIT(4)
+#define HIGH_CORE_DIS_SUB BIT(5)
+#define HIGH_CORE_CG_AO BIT(6)
+#define HIGH_FINAL_VAL_MASK 0x1f00
+#define HIGH_FINAL_VAL_DEFAULT 0x300
+#define SCP_CLK_L1_SRAM_PD REG32(SCP_CLK_BASE + 0x80)
+#define SCP_CLK_TCM_TAIL_SRAM_PD REG32(SCP_CLK_BASE + 0x94)
+
+#ifdef CHIP_VARIANT_MT8186
+#define SCP_CLK_CTRL_GENERAL_CTRL REG32(SCP_CLK_BASE + 0x9C)
+#endif
+
+#define SCP_CLK_SLEEP REG32(SCP_CLK_BASE + 0xA0)
+#define SLOW_WAKE_DISABLE 1
+#define SCP_FAST_WAKE_CNT_END REG32(SCP_CLK_BASE + 0xA4)
+#define FAST_WAKE_CNT_END_MASK 0xfff
+#define FAST_WAKE_CNT_END_DEFAULT 0x18
+#define MEM_CK_CS_ISO_CNT_END_MASK 0x7f0000
+
+/* Peripherals */
+#define SCP_I2C0_BASE (SCP_CFG_BASE + 0x5000)
+#define SCP_I2C1_BASE (SCP_CFG_BASE + 0x6000)
+#define SCP_I2C2_BASE (SCP_CFG_BASE + 0x7000)
+
+#define SCP_GPIO_BASE (SCP_CFG_BASE + 0x8000)
+#define SCP_UART0_BASE (SCP_CFG_BASE + 0x9000)
+#define SCP_UART1_BASE (SCP_CFG_BASE + 0xE000)
+#define SCP_UART_COUNT 2
+
+/* External GPIO interrupt */
+#define SCP_EINT_BASE (SCP_CFG_BASE + 0xA000)
+#define SCP_EINT_STATUS REG32_ADDR(SCP_EINT_BASE)
+#define SCP_EINT_ACK REG32_ADDR(SCP_EINT_BASE + 0x040)
+#define SCP_EINT_MASK_GET REG32_ADDR(SCP_EINT_BASE + 0x080)
+#define SCP_EINT_MASK_SET REG32_ADDR(SCP_EINT_BASE + 0x0C0)
+#define SCP_EINT_MASK_CLR REG32_ADDR(SCP_EINT_BASE + 0x100)
+#define SCP_EINT_SENS_GET REG32_ADDR(SCP_EINT_BASE + 0x140)
+#define SCP_EINT_SENS_SET REG32_ADDR(SCP_EINT_BASE + 0x180)
+#define SCP_EINT_SENS_CLR REG32_ADDR(SCP_EINT_BASE + 0x1C0)
+#define SCP_EINT_SOFT_GET REG32_ADDR(SCP_EINT_BASE + 0x200)
+#define SCP_EINT_SOFT_SET REG32_ADDR(SCP_EINT_BASE + 0x240)
+#define SCP_EINT_SOFT_CLR REG32_ADDR(SCP_EINT_BASE + 0x280)
+#define SCP_EINT_POLARITY_GET REG32_ADDR(SCP_EINT_BASE + 0x300)
+#define SCP_EINT_POLARITY_SET REG32_ADDR(SCP_EINT_BASE + 0x340)
+#define SCP_EINT_POLARITY_CLR REG32_ADDR(SCP_EINT_BASE + 0x380)
+#define SCP_EINT_D0_EN REG32_ADDR(SCP_EINT_BASE + 0x400)
+#define SCP_EINT_D1_EN REG32_ADDR(SCP_EINT_BASE + 0x420)
+#define SCP_EINT_DBNC_GET REG32_ADDR(SCP_EINT_BASE + 0x500)
+#define SCP_EINT_DBNC_SET REG32_ADDR(SCP_EINT_BASE + 0x600)
+#define SCP_EINT_DBNC_CLR REG32_ADDR(SCP_EINT_BASE + 0x700)
+
+#define SCP_PMICWP2P_BASE (SCP_CFG_BASE + 0xB000)
+#define PMICW_WACS_CMD REG32(SCP_PMICWP2P_BASE + 0x200)
+#define PMICW_WACS_RDATA REG32(SCP_PMICWP2P_BASE + 0x204)
+#define PMICW_WACS_VLDCLR REG32(SCP_PMICWP2P_BASE + 0x208)
+#define SCP_SPMP2P_BASE (SCP_CFG_BASE + 0xC000)
+#define SCP_DMA_BASE (SCP_CFG_BASE + 0xD000)
+#define DMA_ACKINT_CHX REG32(SCP_DMA_BASE + 0x20)
+#define SCP_SPI0_BASE (SCP_CFG_BASE + 0xF000)
+#define SCP_SPI1_BASE (SCP_CFG_BASE + 0x10000)
+#define SCP_SPI2_BASE (SCP_CFG_BASE + 0x11000)
+
+#define CACHE_ICACHE 0
+#define CACHE_DCACHE 1
+#define CACHE_COUNT 2
+#define SCP_CACHE_BASE (SCP_CFG_BASE + 0x14000)
+#define SCP_CACHE_SEL(x) (SCP_CACHE_BASE + (x)*0x3000)
+#define SCP_CACHE_CON(x) REG32(SCP_CACHE_SEL(x))
+#define SCP_CACHE_CON_MCEN BIT(0)
+#define SCP_CACHE_CON_CNTEN0 BIT(2)
+#define SCP_CACHE_CON_CNTEN1 BIT(3)
+#define SCP_CACHE_CON_CACHESIZE_SHIFT 8
+#define SCP_CACHE_CON_CACHESIZE_MASK (0x3 << SCP_CACHE_CON_CACHESIZE_SHIFT)
+#define SCP_CACHE_CON_CACHESIZE_0KB (0x0 << SCP_CACHE_CON_CACHESIZE_SHIFT)
+#define SCP_CACHE_CON_CACHESIZE_8KB (0x1 << SCP_CACHE_CON_CACHESIZE_SHIFT)
+#define SCP_CACHE_CON_CACHESIZE_16KB (0x2 << SCP_CACHE_CON_CACHESIZE_SHIFT)
+#define SCP_CACHE_CON_CACHESIZE_32KB (0x3 << SCP_CACHE_CON_CACHESIZE_SHIFT)
+#define SCP_CACHE_CON_WAYEN BIT(10)
+
+#define SCP_CACHE_OP(x) REG32(SCP_CACHE_SEL(x) + 0x04)
+#define SCP_CACHE_OP_EN BIT(0)
+#define SCP_CACHE_OP_OP_SHIFT 1
+#define SCP_CACHE_OP_OP_MASK (0xf << SCP_CACHE_OP_OP_SHIFT)
+
+#define OP_INVALIDATE_ALL_LINES (0x1 << SCP_CACHE_OP_OP_SHIFT)
+#define OP_INVALIDATE_ONE_LINE_BY_ADDRESS (0x2 << SCP_CACHE_OP_OP_SHIFT)
+#define OP_INVALIDATE_ONE_LINE_BY_SET_WAY (0x4 << SCP_CACHE_OP_OP_SHIFT)
+#define OP_CACHE_FLUSH_ALL_LINES (0x9 << SCP_CACHE_OP_OP_SHIFT)
+#define OP_CACHE_FLUSH_ONE_LINE_BY_ADDRESS (0xa << SCP_CACHE_OP_OP_SHIFT)
+#define OP_CACHE_FLUSH_ONE_LINE_BY_SET_WAY (0xc << SCP_CACHE_OP_OP_SHIFT)
+
+#define SCP_CACHE_OP_TADDR_SHIFT 5
+#define SCP_CACHE_OP_TADDR_MASK (0x7ffffff << SCP_CACHE_OP_TADDR_SHIFT)
+#define SCP_CACHE_LINE_SIZE BIT(SCP_CACHE_OP_TADDR_SHIFT)
+
+/* Cache statistics */
+#define SCP_CACHE_HCNT0L(x) REG32(SCP_CACHE_SEL(x) + 0x08)
+#define SCP_CACHE_HCNT0U(x) REG32(SCP_CACHE_SEL(x) + 0x0c)
+#define SCP_CACHE_CCNT0L(x) REG32(SCP_CACHE_SEL(x) + 0x10)
+#define SCP_CACHE_CCNT0U(x) REG32(SCP_CACHE_SEL(x) + 0x14)
+#define SCP_CACHE_HCNT1L(x) REG32(SCP_CACHE_SEL(x) + 0x18)
+#define SCP_CACHE_HCNT1U(x) REG32(SCP_CACHE_SEL(x) + 0x1c)
+#define SCP_CACHE_CCNT1L(x) REG32(SCP_CACHE_SEL(x) + 0x20)
+#define SCP_CACHE_CCNT1U(x) REG32(SCP_CACHE_SEL(x) + 0x24)
+
+#define SCP_CACHE_REGION_EN(x) REG32(SCP_CACHE_SEL(x) + 0x2c)
+
+#define SCP_CACHE_ENTRY_BASE(x) (SCP_CACHE_SEL(x) + 0x2000)
+#define SCP_CACHE_ENTRY(x, reg) REG32(SCP_CACHE_ENTRY_BASE(x) + (reg)*4)
+#define SCP_CACHE_END_ENTRY_BASE(x) (SCP_CACHE_SEL(x) + 0x2040)
+#define SCP_CACHE_END_ENTRY(x, reg) REG32(SCP_CACHE_END_ENTRY_BASE(x) + (reg)*4)
+#define SCP_CACHE_ENTRY_C BIT(8)
+#define SCP_CACHE_ENTRY_BASEADDR_MASK (0xfffff << 12)
+
+/* ARMV7 regs */
+#define ARM_SCB_SCR REG32(0xE000ED10)
+#define SCR_DEEPSLEEP BIT(2)
+
+/* AP regs */
+#define AP_BASE 0xA0000000
+#define TOPCK_BASE AP_BASE /* Top clock */
+#define SCP_UART2_BASE (AP_BASE + 0x01002000) /* AP UART0 */
+
+/* CLK_CFG_5 regs */
+#define AP_CLK_CFG_5 REG32(TOPCK_BASE + 0x0090)
+#define PWRAP_ULPOSC_MASK (0x3000000)
+#define CLK26M (0 << 24)
+#define OSC_D16 (1 << 24)
+#define OSC_D4 (2 << 24)
+#define OSC_D8 (3 << 24)
+#define AP_CLK_CFG_5_CLR REG32(TOPCK_BASE + 0x0098)
+#define PWRAP_ULPOSC_CG BIT(31)
+
+#ifdef CHIP_VARIANT_MT8186
+/* SCP PLL MUX RG */
+#define CLK_CFG_UPDATE (TOPCK_BASE + 0x0004)
+#define SCP_CK_UPDATE_SHFT 1
+#define CLK_CFG_0 (TOPCK_BASE + 0x0040)
+#define CLK_CFG_0_SET (TOPCK_BASE + 0x0044)
+#define CLK_CFG_0_CLR (TOPCK_BASE + 0x0048)
+#define CLK_SCP_SEL_MSK 0x7
+#define CLK_SCP_SEL_SHFT 8
+#endif
+
+/* OSC meter */
+#ifdef CHIP_VARIANT_MT8186
+#define AP_CLK_MISC_CFG_0 REG32(TOPCK_BASE + 0x0140)
+#define AP_CLK_DBG_CFG REG32(TOPCK_BASE + 0x017C)
+#else
+#define AP_CLK_MISC_CFG_0 REG32(TOPCK_BASE + 0x0104)
+#define AP_CLK_DBG_CFG REG32(TOPCK_BASE + 0x010C)
+#endif
+
+#define MISC_METER_DIVISOR_MASK 0xff000000
+#define MISC_METER_DIV_1 0
+#define DBG_MODE_MASK 3
+#define DBG_MODE_SET_CLOCK 0
+#define DBG_BIST_SOURCE_MASK (0x3f << 16)
+
+#ifdef CHIP_VARIANT_MT8186
+#define DBG_BIST_SOURCE_ULPOSC1 (35 << 16)
+#define DBG_BIST_SOURCE_ULPOSC2 (34 << 16)
+#else
+#define DBG_BIST_SOURCE_ULPOSC1 (0x26 << 16)
+#define DBG_BIST_SOURCE_ULPOSC2 (0x25 << 16)
+#endif
+
+#define AP_SCP_CFG_0 REG32(TOPCK_BASE + 0x0220)
+#define CFG_FREQ_METER_RUN (1 << 4)
+#define CFG_FREQ_METER_ENABLE (1 << 12)
+#define AP_SCP_CFG_1 REG32(TOPCK_BASE + 0x0224)
+#define CFG_FREQ_COUNTER(CFG1) ((CFG1)&0xFFFF)
+
+/* GPIO */
+#define AP_GPIO_BASE (AP_BASE + 0x00005000)
+/*
+ * AP_GPIO_DIR
+ * GPIO input/out direction, 1 bit per pin.
+ * 0:input 1:output
+ */
+#define AP_GPIO_DIR(n) REG32(AP_GPIO_BASE + ((n) << 4))
+/*
+ * AP_GPIO_DOUT, n in [0..5]
+ * GPIO output level, 1 bit per pin
+ * 0:low 1:high
+ */
+#define AP_GPIO_DOUT(n) REG32(AP_GPIO_BASE + 0x100 + ((n) << 4))
+/*
+ * AP_GPIO_DIN, n in [0..5]
+ * GPIO input level, 1 bit per pin
+ * 0:low 1:high
+ */
+#define AP_GPIO_DIN(n) REG32(AP_GPIO_BASE + 0x200 + ((n) << 4))
+/*
+ * AP_GPIO_MODE, n in [0..22]
+ * Pin mode selection, 4 bit per pin
+ * bit3   - write enable, set to 1 for hw to fetch bit2,1,0.
+ * bit2-0 - mode 0 ~ 7
+ */
+#define AP_GPIO_MODE(n) REG32(AP_GPIO_BASE + 0x300 + ((n) << 4))
+#define AP_GPIO_TRAP REG32(AP_GPIO_BASE + 0x6B0)
+#define AP_GPIO_UNIMPLEMENTED REG32(AP_GPIO_BASE + 0x6C0)
+#define AP_GPIO_DBG REG32(AP_GPIO_BASE + 0x6D0)
+#define AP_GPIO_BANK REG32(AP_GPIO_BASE + 0x6E0)
+/* AP_GPIO_SEC, n in [0..5] */
+#define AP_GPIO_SEC(n) REG32(AP_GPIO_BASE + 0xF00 + ((n) << 4))
+
+#ifdef CHIP_VARIANT_MT8186
+#define AP_PLL_CON0 REG32(AP_BASE + 0xC000)
+#define LTECLKSQ_EN BIT(0)
+#define LTECLKSQ_LPF_EN BIT(1)
+#define LTECLKSQ_HYS_EN BIT(2)
+#define LTECLKSQ_VOD_EN BIT(3)
+#define LTECLKSQ_HYS_SEL (0x1 << 4)
+#define CLKSQ_RESERVE (0x1 << 10)
+#define SSUSB26M_CK2_EN BIT(13)
+#define SSUSB26M_CK_EN BIT(14)
+#define XTAL26M_CK_EN BIT(15)
+#define ULPOSC_CTRL_SEL (0xf << 16)
+#endif
+
+/*
+ * PLL ULPOSC
+ * ULPOSC1:  AP_ULPOSC_CON[0] AP_ULPOSC_CON[1]
+ * ULPOSC2:  AP_ULPOSC_CON[2] AP_ULPOSC_CON[3]
+ * osc: 0 for ULPOSC1, 1 for ULPSOC2.
+ */
+#ifdef CHIP_VARIANT_MT8186
+#define AP_ULPOSC_BASE0 (AP_BASE + 0xC500)
+#define AP_ULPOSC_BASE1 (AP_BASE + 0xC504)
+#define AP_ULPOSC_CON02(osc) REG32(AP_ULPOSC_BASE0 + (osc)*0x80)
+#define AP_ULPOSC_CON13(osc) REG32(AP_ULPOSC_BASE1 + (osc)*0x80)
+#else
+#define AP_ULPOSC_BASE0 (AP_BASE + 0xC700)
+#define AP_ULPOSC_BASE1 (AP_BASE + 0xC704)
+#define AP_ULPOSC_CON02(osc) REG32(AP_ULPOSC_BASE0 + (osc)*0x8)
+#define AP_ULPOSC_CON13(osc) REG32(AP_ULPOSC_BASE1 + (osc)*0x8)
+#endif
+/*
+ * AP_ULPOSC_CON[0,2]
+ * bit0-5:   calibration
+ * bit6-12:  I-band
+ * bit13-16: F-band
+ * bit17-22: div
+ * bit23:    CP_EN
+ * bit24-31: reserved
+ */
+#ifdef CHIP_VARIANT_MT8186
+#define OSC_CALI_MASK 0x3f
+#define OSC_IBAND_SHIFT 6
+#define OSC_FBAND_MASK 0xf
+#define OSC_FBAND_SHIFT 13
+#define OSC_DIV_SHIFT 17
+#else
+#define OSC_CALI_MSK (0x3f << 0)
+#define OSC_CALI_BITS 6
+#define OSC_IBAND_MASK (0x7f << 6)
+#define OSC_FBAND_MASK (0x0f << 13)
+#define OSC_DIV_MASK (0x1f << 17)
+#define OSC_DIV_BITS 5
+#define OSC_RESERVED_MASK (0xff << 24)
+#endif
+
+#define OSC_CP_EN BIT(23)
+/* AP_ULPOSC_CON[1,3] */
+#define OSC_MOD_MASK (0x03 << 0)
+#define OSC_DIV2_EN BIT(2)
+
+#define UNIMPLEMENTED_GPIO_BANK 0
+
+#ifndef __ASSEMBLER__
+
+/*
+ * Cortex-M4 mod
+ * Available power saving features:
+ * 1. FPU freeze - freeze FPU operand when FPU is not used
+ * 2. LSU gating - gate LSU clock when not LSU operation
+ * 3. Trace clk disable - gate trace clock
+ * 4. DCM for CPU stall - gate CPU clock when CPU stall
+ */
+#define CM4_MODIFICATION REG32(0xE00FE000)
+#define CM4_DCM_FEATURE REG32(0xE00FE004)
+/* UART, 16550 compatible */
+#define SCP_UART_BASE(n) CONCAT3(SCP_UART, n, _BASE)
+#define UART_REG(n, offset) REG32_ADDR(SCP_UART_BASE(n))[offset]
+#define UART_IRQ(n) CONCAT2(SCP_IRQ_UART, n)
+#define UART_RX_IRQ(n) CONCAT3(SCP_IRQ_UART, n, _RX)
+
+/* Watchdog */
+#define SCP_WDT_BASE (SCP_CFG_BASE + 0x84)
+#define SCP_WDT_REG(offset) REG32(SCP_WDT_BASE + offset)
+#define SCP_WDT_CFG SCP_WDT_REG(0)
+#define SCP_WDT_FREQ 33825
+#define SCP_WDT_MAX_PERIOD 0xFFFFF /* 31 seconds */
+#define SCP_WDT_PERIOD(ms) (SCP_WDT_FREQ * (ms) / 1000)
+#define SCP_WDT_ENABLE BIT(31)
+#define SCP_WDT_RELOAD SCP_WDT_REG(4)
+#define SCP_WDT_RELOAD_VALUE 1
+
+#endif /* !__ASSEMBLER__ */
+#endif /* __CROS_EC_REGISTERS_H */
diff --git a/chip/mt_scp/mt818x/serial_reg.h b/chip/mt_scp/mt818x/serial_reg.h
new file mode 100644
index 0000000000..8dd2864a98
--- /dev/null
+++ b/chip/mt_scp/mt818x/serial_reg.h
@@ -0,0 +1,90 @@
+/* Copyright 2018 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * UART register map
+ */
+
+#ifndef __CROS_EC_SERIAL_REG_H
+#define __CROS_EC_SERIAL_REG_H
+
+#include "registers.h"
+
+/* Number of hardware ports */
+#define HW_UART_PORTS 2
+
+/* DLAB (Divisor Latch Access Bit) == 0 */
+
+/* Data register
+ *   (Read) Rcvr buffer register
+ *   (Write) Xmit holding register
+ */
+#define UART_DATA(n) UART_REG(n, 0)
+/* (Write) Interrupt enable register */
+#define UART_IER(n) UART_REG(n, 1)
+#define UART_IER_RDI BIT(0) /* Recv data int */
+#define UART_IER_THRI BIT(1) /* Xmit holding register int */
+#define UART_IER_RLSI BIT(2) /* Rcvr line status int */
+#define UART_IER_MSI BIT(3) /* Modem status int */
+/* (Read) Interrupt ID register */
+#define UART_IIR(n) UART_REG(n, 2)
+#define UART_IIR_NO_INT BIT(0) /* No int pending */
+#define UART_IIR_ID_MASK 0x0e /* Interrupt ID mask */
+#define UART_IIR_MSI 0x00
+#define UART_IIR_THRI 0x02
+#define UART_IIR_RDI 0x04
+#define UART_IIR_RLSI 0x06
+#define UART_IIR_BUSY 0x07 /* DW APB busy */
+/* (Write) FIFO control register */
+#define UART_FCR(n) UART_REG(n, 2)
+#define UART_FCR_ENABLE_FIFO BIT(0) /* Enable FIFO */
+#define UART_FCR_CLEAR_RCVR BIT(1) /* Clear rcvr FIFO */
+#define UART_FCR_CLEAR_XMIT BIT(2) /* Clear xmit FIFO */
+#define UART_FCR_DMA_SELECT BIT(3)
+/* FIFO trigger levels */
+#define UART_FCR_T_TRIG_00 0x00
+#define UART_FCR_T_TRIG_01 0x10
+#define UART_FCR_T_TRIG_10 0x20
+#define UART_FCR_T_TRIG_11 0x30
+#define UART_FCR_R_TRIG_00 0x00
+#define UART_FCR_R_TRIG_01 0x40
+#define UART_FCR_R_TRIG_10 0x80
+#define UART_FCR_R_TRIG_11 0x80
+/* (Write) Line control register */
+#define UART_LCR(n) UART_REG(n, 3)
+#define UART_LCR_WLEN5 0 /* Word length 5 bits */
+#define UART_LCR_WLEN6 1
+#define UART_LCR_WLEN7 2
+#define UART_LCR_WLEN8 3
+#define UART_LCR_STOP BIT(2) /* Stop bits: 1bit, 2bits */
+#define UART_LCR_PARITY BIT(3) /* Parity enable */
+#define UART_LCR_EPAR BIT(4) /* Even parity */
+#define UART_LCR_SPAR BIT(5) /* Stick parity */
+#define UART_LCR_SBC BIT(6) /* Set break control */
+#define UART_LCR_DLAB BIT(7) /* Divisor latch access */
+/* (Write) Modem control register */
+#define UART_MCR(n) UART_REG(n, 4)
+/* (Read) Line status register */
+#define UART_LSR(n) UART_REG(n, 5)
+#define UART_LSR_DR BIT(0) /* Data ready */
+#define UART_LSR_OE BIT(1) /* Overrun error */
+#define UART_LSR_PE BIT(2) /* Parity error */
+#define UART_LSR_FE BIT(3) /* Frame error */
+#define UART_LSR_BI BIT(4) /* Break interrupt */
+#define UART_LSR_THRE BIT(5) /* Xmit-hold-register empty */
+#define UART_LSR_TEMT BIT(6) /* Xmit empty */
+#define UART_LSR_FIFOE BIT(7) /* FIFO error */
+
+/* DLAB == 1 */
+
+/* (Write) Divisor latch */
+#define UART_DLL(n) UART_REG(n, 0) /* Low */
+#define UART_DLH(n) UART_REG(n, 1) /* High */
+
+/* MTK extension */
+#define UART_HIGHSPEED(n) UART_REG(n, 9)
+#define UART_SAMPLE_COUNT(n) UART_REG(n, 10)
+#define UART_SAMPLE_POINT(n) UART_REG(n, 11)
+#define UART_RATE_FIX(n) UART_REG(n, 13)
+
+#endif /* __CROS_EC_SERIAL_REG_H */
diff --git a/chip/mt_scp/mt818x/system.c b/chip/mt_scp/mt818x/system.c
new file mode 100644
index 0000000000..8bf523c0f7
--- /dev/null
+++ b/chip/mt_scp/mt818x/system.c
@@ -0,0 +1,177 @@
+/* Copyright 2018 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* System : hardware specific implementation */
+
+#include "builtin/assert.h"
+#include "clock_chip.h"
+#include "console.h"
+#include "cpu.h"
+#include "cros_version.h"
+#include "flash.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "memmap.h"
+#include "registers.h"
+#include "system.h"
+#include "task.h"
+#include "util.h"
+#include "watchdog.h"
+
+/*
+ * SCP_GPR[0] b15-b0  - scratchpad
+ * SCP_GPR[0] b31-b16 - saved_flags
+ */
+
+int system_set_scratchpad(uint32_t value)
+{
+	/* Check if value fits in 16 bits */
+	if (value & 0xffff0000)
+		return EC_ERROR_INVAL;
+
+	SCP_GPR[0] = (SCP_GPR[0] & 0xffff0000) | value;
+
+	return EC_SUCCESS;
+}
+
+int system_get_scratchpad(uint32_t *value)
+{
+	*value = SCP_GPR[0] & 0xffff;
+	return EC_SUCCESS;
+}
+
+const char *system_get_chip_vendor(void)
+{
+	return "mtk";
+}
+
+const char *system_get_chip_name(void)
+{
+	/* Support only SCP_A for now */
+	return "scp_a";
+}
+
+const char *system_get_chip_revision(void)
+{
+	return "";
+}
+
+void chip_pre_init(void)
+{
+}
+
+static void scp_cm4_mod(void)
+{
+	CM4_MODIFICATION = 3;
+	CM4_DCM_FEATURE = 3;
+}
+
+static void scp_enable_pirq(void)
+{
+	/* Enable all peripheral to SCP IRQ, except IPC0. */
+	SCP_INTC_IRQ_ENABLE = 0xFFFFFFFE;
+	SCP_INTC_IRQ_ENABLE_MSB = 0xFFFFFFFF;
+}
+
+void system_pre_init(void)
+{
+	/* CM4 Modification */
+	scp_cm4_mod();
+
+	/* Clock */
+	scp_enable_clock();
+
+	/* Peripheral IRQ */
+	scp_enable_pirq();
+	/* Init dram mapping (and cache) */
+	scp_memmap_init();
+	/* Disable jump (mt_scp has only RW) and enable MPU. */
+	system_disable_jump();
+}
+
+void system_reset(int flags)
+{
+	uint32_t save_flags = 0;
+
+	/* Disable interrupts to avoid task swaps during reboot */
+	interrupt_disable();
+
+	/* Save current reset reasons if necessary */
+	if (flags & SYSTEM_RESET_PRESERVE_FLAGS)
+		save_flags = system_get_reset_flags() | EC_RESET_FLAG_PRESERVED;
+
+	if (flags & SYSTEM_RESET_LEAVE_AP_OFF)
+		save_flags |= EC_RESET_FLAG_AP_OFF;
+
+	/* Remember that the software asked us to hard reboot */
+	if (flags & SYSTEM_RESET_HARD)
+		save_flags |= EC_RESET_FLAG_HARD;
+
+	/* Reset flags are 32-bits, but save only 16 bits. */
+	ASSERT(!(save_flags >> 16));
+	SCP_GPR[0] = (save_flags << 16) | (SCP_GPR[0] & 0xffff);
+
+	/* SCP can not hard reset itself */
+	ASSERT(!(flags & SYSTEM_RESET_HARD));
+
+	if (flags & SYSTEM_RESET_WAIT_EXT) {
+		int i;
+
+		/* Wait 10 seconds for external reset */
+		for (i = 0; i < 1000; i++) {
+			watchdog_reload();
+			udelay(10000);
+		}
+	}
+
+	/* Set watchdog timer to small value, and spin wait for watchdog reset
+	 */
+	SCP_WDT_CFG = 0;
+	SCP_WDT_CFG = SCP_WDT_ENABLE | SCP_WDT_PERIOD(1);
+	watchdog_reload();
+	while (1)
+		;
+}
+
+static void check_reset_cause(void)
+{
+	uint32_t flags = 0;
+	uint32_t raw_reset_cause = SCP_GPR[1];
+
+	/* Set state to power-on */
+	SCP_PWRON_STATE = PWRON_DEFAULT;
+
+	if ((raw_reset_cause & 0xffff0000) == PWRON_DEFAULT) {
+		/* Reboot */
+		if (raw_reset_cause & PWRON_WATCHDOG)
+			flags |= EC_RESET_FLAG_WATCHDOG;
+		else if (raw_reset_cause & PWRON_RESET)
+			flags |= EC_RESET_FLAG_POWER_ON;
+		else
+			flags |= EC_RESET_FLAG_OTHER;
+	} else {
+		/* Power lost restart */
+		flags |= EC_RESET_FLAG_POWER_ON;
+	}
+	system_set_reset_flags(SCP_GPR[0] >> 16);
+	SCP_GPR[0] &= 0xffff;
+}
+
+int system_is_reboot_warm(void)
+{
+	const uint32_t cold_flags =
+		EC_RESET_FLAG_RESET_PIN | EC_RESET_FLAG_POWER_ON |
+		EC_RESET_FLAG_WATCHDOG | EC_RESET_FLAG_HARD |
+		EC_RESET_FLAG_SOFT | EC_RESET_FLAG_HIBERNATE;
+
+	check_reset_cause();
+
+	return !(system_get_reset_flags() & cold_flags);
+}
+
+int system_get_bbram(enum system_bbram_idx idx, uint8_t *value)
+{
+	return EC_ERROR_INVAL;
+}
diff --git a/chip/mt_scp/mt818x/uart.c b/chip/mt_scp/mt818x/uart.c
new file mode 100644
index 0000000000..6bcfa89d9b
--- /dev/null
+++ b/chip/mt_scp/mt818x/uart.c
@@ -0,0 +1,178 @@
+/* Copyright 2018 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* SCP UART module */
+
+#include "clock_chip.h"
+#include "console.h"
+#include "gpio.h"
+#include "registers.h"
+#include "serial_reg.h"
+#include "system.h"
+#include "task.h"
+#include "uart.h"
+#include "util.h"
+
+/* Console UART index */
+#define UARTN CONFIG_UART_CONSOLE
+#define UART_IDLE_WAIT_US 500
+
+static uint8_t uart_done, tx_started;
+
+int uart_init_done(void)
+{
+	/*
+	 * TODO: AP UART support
+	 * When access AP UART port, wait for AP peripheral clock
+	 */
+	return uart_done;
+}
+
+void uart_tx_start(void)
+{
+	tx_started = 1;
+
+	/* AP UART mode doesn't support interrupt */
+	if (UARTN >= SCP_UART_COUNT)
+		return;
+
+	if (UART_IER(UARTN) & UART_IER_THRI)
+		return;
+	disable_sleep(SLEEP_MASK_UART);
+	UART_IER(UARTN) |= UART_IER_THRI;
+}
+
+void uart_tx_stop(void)
+{
+	tx_started = 0;
+
+	/* AP UART mode doesn't support interrupt */
+	if (UARTN >= SCP_UART_COUNT)
+		return;
+
+	UART_IER(UARTN) &= ~UART_IER_THRI;
+	enable_sleep(SLEEP_MASK_UART);
+}
+
+void uart_tx_flush(void)
+{
+	while (!(UART_LSR(UARTN) & UART_LSR_TEMT))
+		;
+}
+
+int uart_tx_ready(void)
+{
+	/* Check xmit FIFO empty */
+	return UART_LSR(UARTN) & UART_LSR_THRE;
+}
+
+int uart_rx_available(void)
+{
+	/* Check rcvr data ready */
+	return UART_LSR(UARTN) & UART_LSR_DR;
+}
+
+void uart_write_char(char c)
+{
+	while (!uart_tx_ready())
+		;
+
+	UART_DATA(UARTN) = c;
+}
+
+int uart_read_char(void)
+{
+	return UART_DATA(UARTN);
+}
+
+void uart_process(void)
+{
+	uart_process_input();
+	uart_process_output();
+}
+
+#if (UARTN < SCP_UART_COUNT)
+DECLARE_IRQ(UART_IRQ(UARTN), uart_interrupt, 2);
+static void uart_interrupt(void)
+{
+	uint8_t ier;
+
+	task_clear_pending_irq(UART_IRQ(UARTN));
+	uart_process();
+	ier = UART_IER(UARTN);
+	UART_IER(UARTN) = 0;
+	UART_IER(UARTN) = ier;
+}
+
+DECLARE_IRQ(UART_RX_IRQ(UARTN), uart_rx_interrupt, 2);
+static void uart_rx_interrupt(void)
+{
+	uint8_t ier;
+
+	task_clear_pending_irq(UART_RX_IRQ(UARTN));
+	SCP_INTC_UART_RX_IRQ &= ~BIT(UARTN);
+	uart_process();
+	ier = UART_IER(UARTN);
+	UART_IER(UARTN) = 0;
+	UART_IER(UARTN) = ier;
+	SCP_INTC_UART_RX_IRQ |= 1 << UARTN;
+}
+#endif
+
+void uart_task(void)
+{
+#if (UARTN >= SCP_UART_COUNT)
+	while (1) {
+		if (uart_rx_available() || tx_started)
+			uart_process();
+		else
+			task_wait_event(UART_IDLE_WAIT_US);
+	}
+#endif
+}
+
+void uart_init(void)
+{
+	const uint32_t baud_rate = CONFIG_UART_BAUD_RATE;
+	/*
+	 * UART clock source is set to ULPOSC1 / 10 below.
+	 *
+	 * TODO(b:134035444): We could get slightly more precise frequency by
+	 * using the _measured_ ULPOSC1 frequency (instead of the target).
+	 */
+	const uint32_t uart_clock = ULPOSC1_CLOCK_MHZ * 1000 / 10 * 1000;
+	const uint32_t div = DIV_ROUND_NEAREST(uart_clock, baud_rate * 16);
+
+	/* Init clock */
+#if UARTN == 0
+	SCP_CLK_UART = CLK_UART_SEL_ULPOSC1_DIV10;
+	SCP_CLK_GATE |= CG_UART_M | CG_UART_B | CG_UART_RSTN;
+#elif UARTN == 1
+	SCP_CLK_UART = CLK_UART1_SEL_ULPOSC1_DIV10;
+	SCP_CLK_GATE |= CG_UART1_M | CG_UART1_B | CG_UART1_RSTN;
+#endif
+
+	/* Init and clear FIFO */
+	UART_FCR(UARTN) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR |
+			  UART_FCR_CLEAR_XMIT;
+	/* Line control: parity none, 8 bit, 1 stop bit */
+	UART_LCR(UARTN) = UART_LCR_WLEN8;
+	/* For baud rate <= 115200 */
+	UART_HIGHSPEED(UARTN) = 0;
+	/* DLAB = 1 and update DLL DLH */
+	UART_LCR(UARTN) |= UART_LCR_DLAB;
+	UART_DLL(UARTN) = div & 0xff;
+	UART_DLH(UARTN) = (div >> 8) & 0xff;
+	UART_LCR(UARTN) &= ~UART_LCR_DLAB;
+	UART_IER(UARTN) |= UART_IER_RDI;
+
+#if (UARTN < SCP_UART_COUNT)
+	task_enable_irq(UART_IRQ(UARTN));
+	task_enable_irq(UART_RX_IRQ(UARTN));
+	/* UART RX IRQ needs an extra enable */
+	SCP_INTC_UART_RX_IRQ |= 1 << UARTN;
+#endif
+	uart_done = 1;
+}
diff --git a/chip/mt_scp/mt818x/video.c b/chip/mt_scp/mt818x/video.c
new file mode 100644
index 0000000000..10ea586575
--- /dev/null
+++ b/chip/mt_scp/mt818x/video.c
@@ -0,0 +1,19 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "video.h"
+
+uint32_t video_get_enc_capability(void)
+{
+	/* not support 4K */
+	return 0;
+}
+
+uint32_t video_get_dec_capability(void)
+{
+	return VDEC_CAP_MM21 | VDEC_CAP_4K_DISABLED | VDEC_CAP_H264_SLICE |
+	       VDEC_CAP_VP8_FRAME | VDEC_CAP_VP9_FRAME;
+}
diff --git a/chip/mt_scp/mt818x/video.h b/chip/mt_scp/mt818x/video.h
new file mode 100644
index 0000000000..feb2215cfd
--- /dev/null
+++ b/chip/mt_scp/mt818x/video.h
@@ -0,0 +1,31 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_VIDEO_H
+#define __CROS_EC_VIDEO_H
+
+#include "common.h"
+
+/*
+ * Video decoder supported capability
+ */
+#define VDEC_CAP_4K_DISABLED BIT(4)
+#define VDEC_CAP_MM21 BIT(5)
+#define VDEC_CAP_MT21C BIT(6)
+#define VDEC_CAP_H264_SLICE BIT(8)
+#define VDEC_CAP_VP8_FRAME BIT(9)
+#define VDEC_CAP_VP9_FRAME BIT(10)
+#define VDEC_CAP_IRQ_IN_SCP BIT(16)
+
+/*
+ * Video encoder supported capability:
+ * BIT(0): enable 4K
+ */
+#define VENC_CAP_4K BIT(0)
+
+uint32_t video_get_enc_capability(void);
+uint32_t video_get_dec_capability(void);
+
+#endif /* #ifndef __CROS_EC_VIDEO_H */
diff --git a/chip/mt_scp/mt818x/watchdog.c b/chip/mt_scp/mt818x/watchdog.c
new file mode 100644
index 0000000000..efadeab0fd
--- /dev/null
+++ b/chip/mt_scp/mt818x/watchdog.c
@@ -0,0 +1,33 @@
+/* Copyright 2018 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Watchdog driver */
+
+#include "common.h"
+#include "hooks.h"
+#include "panic.h"
+#include "registers.h"
+#include "watchdog.h"
+
+void watchdog_reload(void)
+{
+	SCP_WDT_RELOAD = SCP_WDT_RELOAD_VALUE;
+}
+DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT);
+
+int watchdog_init(void)
+{
+	const uint32_t watchdog_timeout =
+		SCP_WDT_PERIOD(CONFIG_WATCHDOG_PERIOD_MS);
+
+	/* Disable watchdog */
+	SCP_WDT_CFG = 0;
+	/* Enable watchdog */
+	SCP_WDT_CFG = SCP_WDT_ENABLE | watchdog_timeout;
+	/* Reload watchdog */
+	watchdog_reload();
+
+	return EC_SUCCESS;
+}
diff --git a/chip/mt_scp/mt8192/build.mk b/chip/mt_scp/mt8192/build.mk
new file mode 100644
index 0000000000..c188ea6d17
--- /dev/null
+++ b/chip/mt_scp/mt8192/build.mk
@@ -0,0 +1,9 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Required chip modules
+chip-y+=$(CHIP_VARIANT)/uart.o
+chip-y+=$(CHIP_VARIANT)/clock.o
+chip-y+=$(CHIP_VARIANT)/video.o
diff --git a/chip/mt_scp/mt8192/clock.c b/chip/mt_scp/mt8192/clock.c
new file mode 100644
index 0000000000..62339dae5f
--- /dev/null
+++ b/chip/mt_scp/mt8192/clock.c
@@ -0,0 +1,387 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Clocks, PLL and power settings */
+
+#include "clock.h"
+#include "common.h"
+#include "console.h"
+#include "csr.h"
+#include "ec_commands.h"
+#include "power.h"
+#include "registers.h"
+#include "timer.h"
+
+#include <assert.h>
+#include <string.h>
+
+#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args)
+
+enum scp_clock_source {
+	SCP_CLK_26M = CLK_SW_SEL_26M,
+	SCP_CLK_32K = CLK_SW_SEL_32K,
+	SCP_CLK_ULPOSC2 = CLK_SW_SEL_ULPOSC2,
+	SCP_CLK_ULPOSC1 = CLK_SW_SEL_ULPOSC1,
+};
+
+static struct opp_ulposc_cfg {
+	uint32_t osc;
+	uint32_t div;
+	uint32_t fband;
+	uint32_t mod;
+	uint32_t cali;
+	uint32_t target_mhz;
+} opp[] = {
+	{
+		.osc = 1,
+		.target_mhz = 196,
+		.div = 20,
+		.fband = 10,
+		.mod = 3,
+		.cali = 64,
+	},
+	{
+		.osc = 0,
+		.target_mhz = 260,
+		.div = 14,
+		.fband = 2,
+		.mod = 0,
+		.cali = 64,
+	},
+	{
+		.osc = 1,
+		.target_mhz = 280,
+		.div = 20,
+		.fband = 2,
+		.mod = 0,
+		.cali = 64,
+	},
+	{
+		.osc = 1,
+		.target_mhz = 360,
+		.div = 20,
+		.fband = 10,
+		.mod = 0,
+		.cali = 64,
+	},
+};
+
+static inline void clock_busy_udelay(int usec)
+{
+	/*
+	 * Delaying by busy-looping, for place that can't use udelay because of
+	 * the clock not configured yet. The value 28 is chosen approximately
+	 * from experiment.
+	 *
+	 * `volatile' in order to avoid compiler to optimize the function out
+	 * (otherwise, the function will be eliminated).
+	 */
+	volatile int i = usec * 28;
+
+	while (--i)
+		;
+}
+
+static void clock_ulposc_config_default(struct opp_ulposc_cfg *opp)
+{
+	unsigned int val = 0;
+
+	/* set div */
+	val |= opp->div << OSC_DIV_SHIFT;
+	/* set F-band; I-band = 82 */
+	val |= (opp->fband << OSC_FBAND_SHIFT) | (82 << OSC_IBAND_SHIFT);
+	/* set calibration */
+	val |= opp->cali;
+	/* set control register 0 */
+	AP_ULPOSC_CON0(opp->osc) = val;
+
+	/* set mod */
+	val = opp->mod << OSC_MOD_SHIFT;
+	/* rsv2 = 0, rsv1 = 41, cali_32k = 0 */
+	val |= 41 << OSC_RSV1_SHIFT;
+	/* set control register 1 */
+	AP_ULPOSC_CON1(opp->osc) = val;
+
+	/* bias = 64 */
+	AP_ULPOSC_CON2(opp->osc) = 64;
+}
+
+static void clock_ulposc_config_cali(struct opp_ulposc_cfg *opp,
+				     uint32_t cali_val)
+{
+	uint32_t val;
+
+	val = AP_ULPOSC_CON0(opp->osc);
+	val &= ~OSC_CALI_MASK;
+	val |= cali_val;
+	AP_ULPOSC_CON0(opp->osc) = val;
+
+	clock_busy_udelay(50);
+}
+
+static uint32_t clock_ulposc_measure_freq(uint32_t osc)
+{
+	uint32_t result = 0;
+	int cnt;
+
+	/* before select meter clock input, bit[1:0] = b00 */
+	AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_MODE_MASK) | DBG_MODE_SET_CLOCK;
+
+	/* select source, bit[21:16] = clk_src */
+	AP_CLK_DBG_CFG =
+		(AP_CLK_DBG_CFG & ~DBG_BIST_SOURCE_MASK) |
+		(osc == 0 ? DBG_BIST_SOURCE_ULPOSC1 : DBG_BIST_SOURCE_ULPOSC2);
+
+	/* set meter divisor to 1, bit[31:24] = b00000000 */
+	AP_CLK_MISC_CFG_0 = (AP_CLK_MISC_CFG_0 & ~MISC_METER_DIVISOR_MASK) |
+			    MISC_METER_DIV_1;
+
+	/* enable frequency meter, without start */
+	AP_SCP_CFG_0 |= CFG_FREQ_METER_ENABLE;
+
+	/* trigger frequency meter start */
+	AP_SCP_CFG_0 |= CFG_FREQ_METER_RUN;
+
+	/*
+	 * Frequency meter counts cycles in 1 / (26 * 1024) second period.
+	 *   freq_in_hz = freq_counter * 26 * 1024
+	 *
+	 * The hardware takes 38us to count cycles. Delay up to 100us,
+	 * as clock_busy_udelay may not be accurate when sysclk is not 26Mhz
+	 * (e.g. when recalibrating/measuring after boot).
+	 */
+	for (cnt = 100; cnt > 0; --cnt) {
+		clock_busy_udelay(1);
+		if (!(AP_SCP_CFG_0 & CFG_FREQ_METER_RUN)) {
+			result = CFG_FREQ_COUNTER(AP_SCP_CFG_1);
+			break;
+		}
+	}
+
+	/* disable freq meter */
+	AP_SCP_CFG_0 &= ~CFG_FREQ_METER_ENABLE;
+
+	return result;
+}
+
+#define CAL_MIS_RATE 40
+static int clock_ulposc_is_calibrated(struct opp_ulposc_cfg *opp)
+{
+	uint32_t curr, target;
+
+	curr = clock_ulposc_measure_freq(opp->osc);
+	target = opp->target_mhz * 1024 / 26;
+
+	/* check if calibrated value is in the range of target value +- 4% */
+	if (curr > (target * (1000 - CAL_MIS_RATE) / 1000) &&
+	    curr < (target * (1000 + CAL_MIS_RATE) / 1000))
+		return 1;
+	else
+		return 0;
+}
+
+static uint32_t clock_ulposc_process_cali(struct opp_ulposc_cfg *opp)
+{
+	uint32_t current_val = 0;
+	uint32_t target_val = opp->target_mhz * 1024 / 26;
+	uint32_t middle, min = 0, max = OSC_CALI_MASK;
+	uint32_t diff_by_min, diff_by_max, cal_result;
+
+	do {
+		middle = (min + max) / 2;
+		if (middle == min)
+			break;
+
+		clock_ulposc_config_cali(opp, middle);
+		current_val = clock_ulposc_measure_freq(opp->osc);
+
+		if (current_val > target_val)
+			max = middle;
+		else
+			min = middle;
+	} while (min <= max);
+
+	clock_ulposc_config_cali(opp, min);
+	current_val = clock_ulposc_measure_freq(opp->osc);
+	if (current_val > target_val)
+		diff_by_min = current_val - target_val;
+	else
+		diff_by_min = target_val - current_val;
+
+	clock_ulposc_config_cali(opp, max);
+	current_val = clock_ulposc_measure_freq(opp->osc);
+	if (current_val > target_val)
+		diff_by_max = current_val - target_val;
+	else
+		diff_by_max = target_val - current_val;
+
+	if (diff_by_min < diff_by_max)
+		cal_result = min;
+	else
+		cal_result = max;
+
+	clock_ulposc_config_cali(opp, cal_result);
+	if (!clock_ulposc_is_calibrated(opp))
+		assert(0);
+
+	return cal_result;
+}
+
+static void clock_high_enable(int osc)
+{
+	/* enable high speed clock */
+	SCP_CLK_ENABLE |= CLK_HIGH_EN;
+
+	switch (osc) {
+	case 0:
+		/* after 150us, enable ULPOSC */
+		clock_busy_udelay(150);
+		SCP_CLK_ENABLE |= CLK_HIGH_CG;
+		break;
+	case 1:
+		/* turn off ULPOSC2 high-core-disable switch */
+		SCP_CLK_ON_CTRL &= ~HIGH_CORE_DIS_SUB;
+		/* after 150us, turn on ULPOSC2 high core clock gate */
+		clock_busy_udelay(150);
+		SCP_CLK_HIGH_CORE_CG |= HIGH_CORE_CG;
+		clock_busy_udelay(50);
+		break;
+	default:
+		break;
+	}
+}
+
+static void clock_high_disable(int osc)
+{
+	switch (osc) {
+	case 0:
+		SCP_CLK_ENABLE &= ~CLK_HIGH_CG;
+		clock_busy_udelay(50);
+		SCP_CLK_ENABLE &= ~CLK_HIGH_EN;
+		clock_busy_udelay(50);
+		break;
+	case 1:
+		SCP_CLK_HIGH_CORE_CG &= ~HIGH_CORE_CG;
+		clock_busy_udelay(50);
+		SCP_CLK_ON_CTRL |= HIGH_CORE_DIS_SUB;
+		clock_busy_udelay(50);
+		break;
+	default:
+		break;
+	}
+}
+
+static void clock_calibrate_ulposc(struct opp_ulposc_cfg *opp)
+{
+	/*
+	 * ULPOSC1(osc=0) is already
+	 * - calibrated
+	 * - enabled in coreboot
+	 * - used by pmic wrapper
+	 */
+	if (opp->osc != 0) {
+		clock_high_disable(opp->osc);
+		clock_ulposc_config_default(opp);
+		clock_high_enable(opp->osc);
+	}
+
+	/* Calibrate only if it is not accurate enough. */
+	if (!clock_ulposc_is_calibrated(opp))
+		opp->cali = clock_ulposc_process_cali(opp);
+
+#ifdef DEBUG
+	CPRINTF("osc:%u, target=%uMHz, cal:%u\n", opp->osc, opp->target_mhz,
+		opp->cali);
+#endif
+}
+
+static void clock_select_clock(enum scp_clock_source src)
+{
+	/*
+	 * DIV2 divider takes precedence over clock selection to prevent
+	 * over-clocking.
+	 */
+	if (src == SCP_CLK_ULPOSC1)
+		SCP_CLK_DIV_SEL = CLK_DIV_SEL2;
+
+	SCP_CLK_SW_SEL = src;
+
+	if (src != SCP_CLK_ULPOSC1)
+		SCP_CLK_DIV_SEL = CLK_DIV_SEL1;
+}
+
+__override void
+power_chipset_handle_host_sleep_event(enum host_sleep_event state,
+				      struct host_sleep_event_context *ctx)
+{
+	if (state == HOST_SLEEP_EVENT_S3_SUSPEND) {
+		CPRINTS("AP suspend");
+		clock_select_clock(SCP_CLK_ULPOSC1);
+	} else if (state == HOST_SLEEP_EVENT_S3_RESUME) {
+		CPRINTS("AP resume");
+		clock_select_clock(SCP_CLK_ULPOSC2);
+	}
+}
+
+void clock_init(void)
+{
+	int i;
+
+	/* select default 26M system clock */
+	clock_select_clock(SCP_CLK_26M);
+
+	/* set VREQ to HW mode */
+	SCP_CPU_VREQ_CTRL = VREQ_SEL | VREQ_DVFS_SEL;
+	SCP_CLK_CTRL_GENERAL_CTRL &= ~VREQ_PMIC_WRAP_SEL;
+	SCP_SEC_CTRL &= ~VREQ_SECURE_DIS;
+
+	/* set DDREN to auto mode */
+	SCP_SYS_CTRL |= AUTO_DDREN;
+
+	/* set settle time */
+	SCP_CLK_SYS_VAL = (SCP_CLK_SYS_VAL & ~CLK_SYS_VAL_MASK) |
+			  CLK_SYS_VAL_VAL(1);
+	SCP_CLK_HIGH_VAL = (SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) |
+			   CLK_HIGH_VAL_VAL(1);
+	SCP_SLEEP_CTRL = (SCP_SLEEP_CTRL & ~VREQ_COUNT_MASK) |
+			 VREQ_COUNT_VAL(1);
+
+	/* turn off ULPOSC2 */
+	SCP_CLK_ON_CTRL |= HIGH_CORE_DIS_SUB;
+
+	/* calibrate ULPOSC */
+	for (i = 0; i < ARRAY_SIZE(opp); ++i)
+		clock_calibrate_ulposc(&opp[i]);
+
+	/* select ULPOSC2 high speed CPU clock */
+	clock_select_clock(SCP_CLK_ULPOSC2);
+
+	/* select BCLK to use ULPOSC1 / 8 = 260MHz / 8 = 32.5MHz */
+	SCP_BCLK_CK_SEL = BCLK_CK_SEL_ULPOSC_DIV8;
+
+	/* enable default clock gate */
+	SCP_SET_CLK_CG |= CG_DMA_CH3 | CG_DMA_CH2 | CG_DMA_CH1 | CG_DMA_CH0 |
+			  CG_I2C_MCLK | CG_MAD_MCLK | CG_AP2P_MCLK;
+}
+
+#ifdef DEBUG
+int command_ulposc(int argc, const char *argv[])
+{
+	int i;
+
+	for (i = 0; i <= 1; ++i)
+		ccprintf("ULPOSC%u frequency: %u kHz\n", i + 1,
+			 clock_ulposc_measure_freq(i) * 26 * 1000 / 1024);
+
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(ulposc, command_ulposc, "[ulposc]",
+			"Measure ULPOSC frequency");
+#endif
+
+test_mockable void clock_enable_module(enum module_id module, int enable)
+{
+}
diff --git a/chip/mt_scp/mt8192/clock_regs.h b/chip/mt_scp/mt8192/clock_regs.h
new file mode 100644
index 0000000000..7e1f77e92d
--- /dev/null
+++ b/chip/mt_scp/mt8192/clock_regs.h
@@ -0,0 +1,82 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* SCP clock module registers */
+
+#ifndef __CROS_EC_CLOCK_REGS_H
+#define __CROS_EC_CLOCK_REGS_H
+
+/* clock source select */
+#define SCP_CLK_SW_SEL REG32(SCP_CLK_CTRL_BASE + 0x0000)
+#define CLK_SW_SEL_26M 0
+#define CLK_SW_SEL_32K 1
+#define CLK_SW_SEL_ULPOSC2 2
+#define CLK_SW_SEL_ULPOSC1 3
+#define SCP_CLK_ENABLE REG32(SCP_CLK_CTRL_BASE + 0x0004)
+#define CLK_HIGH_EN BIT(1) /* ULPOSC */
+#define CLK_HIGH_CG BIT(2)
+/* clock general control */
+#define SCP_CLK_CTRL_GENERAL_CTRL REG32(SCP_CLK_CTRL_BASE + 0x009C)
+#define VREQ_PMIC_WRAP_SEL (0x2)
+
+/* TOPCK clk */
+#define TOPCK_BASE AP_REG_BASE
+#define AP_CLK_MISC_CFG_0 REG32(TOPCK_BASE + 0x0140)
+#define MISC_METER_DIVISOR_MASK 0xff000000
+#define MISC_METER_DIV_1 0
+/* OSC meter */
+#define AP_CLK_DBG_CFG REG32(TOPCK_BASE + 0x017C)
+#define DBG_MODE_MASK 3
+#define DBG_MODE_SET_CLOCK 0
+#define DBG_BIST_SOURCE_MASK (0x3f << 16)
+#define DBG_BIST_SOURCE_ULPOSC1 (0x25 << 16)
+#define DBG_BIST_SOURCE_ULPOSC2 (0x24 << 16)
+#define AP_SCP_CFG_0 REG32(TOPCK_BASE + 0x0220)
+#define CFG_FREQ_METER_RUN BIT(4)
+#define CFG_FREQ_METER_ENABLE BIT(12)
+#define AP_SCP_CFG_1 REG32(TOPCK_BASE + 0x0224)
+#define CFG_FREQ_COUNTER(CFG1) ((CFG1)&0xFFFF)
+/*
+ * ULPOSC
+ * osc: 0 for ULPOSC1, 1 for ULPOSC2.
+ */
+#define AP_ULPOSC_CON0_BASE (AP_REG_BASE + 0xC2B0)
+#define AP_ULPOSC_CON1_BASE (AP_REG_BASE + 0xC2B4)
+#define AP_ULPOSC_CON2_BASE (AP_REG_BASE + 0xC2B8)
+#define AP_ULPOSC_CON0(osc) REG32(AP_ULPOSC_CON0_BASE + (osc)*0x10)
+#define AP_ULPOSC_CON1(osc) REG32(AP_ULPOSC_CON1_BASE + (osc)*0x10)
+#define AP_ULPOSC_CON2(osc) REG32(AP_ULPOSC_CON2_BASE + (osc)*0x10)
+/*
+ * AP_ULPOSC_CON0
+ * bit0-6: calibration
+ * bit7-13: iband
+ * bit14-17: fband
+ * bit18-23: div
+ * bit24: cp_en
+ * bit25-31: reserved
+ */
+#define OSC_CALI_MASK 0x7f
+#define OSC_IBAND_SHIFT 7
+#define OSC_FBAND_SHIFT 14
+#define OSC_DIV_SHIFT 18
+#define OSC_CP_EN BIT(24)
+/* AP_ULPOSC_CON1
+ * bit0-7: 32K calibration
+ * bit 8-15: rsv1
+ * bit 16-23: rsv2
+ * bit 24-25: mod
+ * bit26: div2_en
+ * bit27-31: reserved
+ */
+#define OSC_RSV1_SHIFT 8
+#define OSC_RSV2_SHIFT 16
+#define OSC_MOD_SHIFT 24
+#define OSC_DIV2_EN BIT(26)
+/* AP_ULPOSC_CON2
+ * bit0-7: bias
+ * bit8-31: reserved
+ */
+
+#endif /* __CROS_EC_CLOCK_REGS_H */
diff --git a/chip/mt_scp/mt8192/intc.h b/chip/mt_scp/mt8192/intc.h
new file mode 100644
index 0000000000..6c1d3c549c
--- /dev/null
+++ b/chip/mt_scp/mt8192/intc.h
@@ -0,0 +1,126 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_INTC_H
+#define __CROS_EC_INTC_H
+
+/* INTC */
+#define SCP_INTC_IRQ_POL0 0xef001f20
+#define SCP_INTC_IRQ_POL1 0x0800001d
+#define SCP_INTC_IRQ_POL2 0x00000020
+#define SCP_INTC_GRP_LEN 3
+#define SCP_INTC_IRQ_COUNT 96
+
+/* IRQ numbers */
+#define SCP_IRQ_GIPC_IN0 0
+#define SCP_IRQ_GIPC_IN1 1
+#define SCP_IRQ_GIPC_IN2 2
+#define SCP_IRQ_GIPC_IN3 3
+/* 4 */
+#define SCP_IRQ_SPM 4
+#define SCP_IRQ_AP_CIRQ 5
+#define SCP_IRQ_EINT 6
+#define SCP_IRQ_PMIC 7
+/* 8 */
+#define SCP_IRQ_UART0_TX 8
+#define SCP_IRQ_UART1_TX 9
+#define SCP_IRQ_I2C0 10
+#define SCP_IRQ_I2C1_0 11
+/* 12 */
+#define SCP_IRQ_BUS_DBG_TRACKER 12
+#define SCP_IRQ_CLK_CTRL 13
+#define SCP_IRQ_VOW 14
+#define SCP_IRQ_TIMER0 15
+/* 16 */
+#define SCP_IRQ_TIMER1 16
+#define SCP_IRQ_TIMER2 17
+#define SCP_IRQ_TIMER3 18
+#define SCP_IRQ_TIMER4 19
+/* 20 */
+#define SCP_IRQ_TIMER5 20
+#define SCP_IRQ_OS_TIMER 21
+#define SCP_IRQ_UART0_RX 22
+#define SCP_IRQ_UART1_RX 23
+/* 24 */
+#define SCP_IRQ_GDMA 24
+#define SCP_IRQ_AUDIO 25
+#define SCP_IRQ_MD_DSP 26
+#define SCP_IRQ_ADSP 27
+/* 28 */
+#define SCP_IRQ_CPU_TICK 28
+#define SCP_IRQ_SPI0 29
+#define SCP_IRQ_SPI1 30
+#define SCP_IRQ_SPI2 31
+/* 32 */
+#define SCP_IRQ_NEW_INFRA_SYS_CIRQ 32
+#define SCP_IRQ_DBG 33
+#define SCP_IRQ_CCIF0 34
+#define SCP_IRQ_CCIF1 35
+/* 36 */
+#define SCP_IRQ_CCIF2 36
+#define SCP_IRQ_WDT 37
+#define SCP_IRQ_USB0 38
+#define SCP_IRQ_USB1 39
+/* 40 */
+#define SCP_IRQ_DPMAIF 40
+#define SCP_IRQ_INFRA 41
+#define SCP_IRQ_CLK_CTRL_CORE 42
+#define SCP_IRQ_CLK_CTRL2_CORE 43
+/* 44 */
+#define SCP_IRQ_CLK_CTRL2 44
+#define SCP_IRQ_GIPC_IN4 45 /* HALT */
+#define SCP_IRQ_PERIBUS_TIMEOUT 46
+#define SCP_IRQ_INFRABUS_TIMEOUT 47
+/* 48 */
+#define SCP_IRQ_MET0 48
+#define SCP_IRQ_MET1 49
+#define SCP_IRQ_MET2 50
+#define SCP_IRQ_MET3 51
+/* 52 */
+#define SCP_IRQ_AP_WDT 52
+#define SCP_IRQ_L2TCM_SEC_VIO 53
+#define SCP_IRQ_CPU_TICK1 54
+#define SCP_IRQ_MAD_DATAIN 55
+/* 56 */
+#define SCP_IRQ_I3C0_IBI_WAKE 56
+#define SCP_IRQ_I3C1_IBI_WAKE 57
+#define SCP_IRQ_I3C2_IBI_WAKE 58
+#define SCP_IRQ_APU_ENGINE 59
+/* 60 */
+#define SCP_IRQ_MBOX0 60
+#define SCP_IRQ_MBOX1 61
+#define SCP_IRQ_MBOX2 62
+#define SCP_IRQ_MBOX3 63
+/* 64 */
+#define SCP_IRQ_MBOX4 64
+#define SCP_IRQ_SYS_CLK_REQ 65
+#define SCP_IRQ_BUS_REQ 66
+#define SCP_IRQ_APSRC_REQ 67
+/* 68 */
+#define SCP_IRQ_APU_MBOX 68
+#define SCP_IRQ_DEVAPC_SECURE_VIO 69
+/* 72 */
+/* 76 */
+#define SCP_IRQ_I2C1_2 78
+#define SCP_IRQ_I2C2 79
+/* 80 */
+#define SCP_IRQ_AUD2AUDIODSP 80
+#define SCP_IRQ_AUD2AUDIODSP_2 81
+#define SCP_IRQ_CONN2ADSP_A2DPOL 82
+#define SCP_IRQ_CONN2ADSP_BTCVSD 83
+/* 84 */
+#define SCP_IRQ_CONN2ADSP_BLEISO 84
+#define SCP_IRQ_PCIE2ADSP 85
+#define SCP_IRQ_APU2ADSP_ENGINE 86
+#define SCP_IRQ_APU2ADSP_MBOX 87
+/* 88 */
+#define SCP_IRQ_CCIF3 88
+#define SCP_IRQ_I2C_DMA0 89
+#define SCP_IRQ_I2C_DMA1 90
+#define SCP_IRQ_I2C_DMA2 91
+/* 92 */
+#define SCP_IRQ_I2C_DMA3 92
+
+#endif /* __CROS_EC_INTC_H */
diff --git a/chip/mt_scp/mt8192/uart.c b/chip/mt_scp/mt8192/uart.c
new file mode 100644
index 0000000000..da17857edf
--- /dev/null
+++ b/chip/mt_scp/mt8192/uart.c
@@ -0,0 +1,26 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* SCP UART module for MT8192 specific */
+
+#include "uart_regs.h"
+
+/*
+ * UARTN == 0, SCP UART0
+ * UARTN == 1, SCP UART1
+ * UARTN == 2, AP UART1
+ */
+#define UARTN CONFIG_UART_CONSOLE
+
+void uart_init_pinmux(void)
+{
+#if UARTN == 0
+	SCP_UART_CK_SEL |= UART0_CK_SEL_VAL(UART_CK_SEL_ULPOSC);
+	SCP_SET_CLK_CG |= CG_UART0_MCLK | CG_UART0_BCLK | CG_UART0_RST;
+#elif UARTN == 1
+	SCP_UART_CK_SEL |= UART1_CK_SEL_VAL(UART_CK_SEL_ULPOSC);
+	SCP_SET_CLK_CG |= CG_UART1_MCLK | CG_UART1_BCLK | CG_UART1_RST;
+#endif
+}
diff --git a/chip/mt_scp/mt8192/video.c b/chip/mt_scp/mt8192/video.c
new file mode 100644
index 0000000000..8cb4f9588e
--- /dev/null
+++ b/chip/mt_scp/mt8192/video.c
@@ -0,0 +1,18 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "video.h"
+
+uint32_t video_get_enc_capability(void)
+{
+	return VENC_CAP_4K;
+}
+
+uint32_t video_get_dec_capability(void)
+{
+	return VDEC_CAP_4K_DISABLED | VDEC_CAP_MM21 | VDEC_CAP_H264_SLICE |
+	       VDEC_CAP_VP8_FRAME | VDEC_CAP_VP9_FRAME;
+}
diff --git a/chip/mt_scp/mt8195/build.mk b/chip/mt_scp/mt8195/build.mk
new file mode 100644
index 0000000000..c188ea6d17
--- /dev/null
+++ b/chip/mt_scp/mt8195/build.mk
@@ -0,0 +1,9 @@
+# -*- makefile -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Required chip modules
+chip-y+=$(CHIP_VARIANT)/uart.o
+chip-y+=$(CHIP_VARIANT)/clock.o
+chip-y+=$(CHIP_VARIANT)/video.o
diff --git a/chip/mt_scp/mt8195/clock.c b/chip/mt_scp/mt8195/clock.c
new file mode 100644
index 0000000000..9a0b978929
--- /dev/null
+++ b/chip/mt_scp/mt8195/clock.c
@@ -0,0 +1,507 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Clocks, PLL and power settings */
+
+#include "clock.h"
+#include "common.h"
+#include "console.h"
+#include "csr.h"
+#include "ec_commands.h"
+#include "power.h"
+#include "registers.h"
+#include "scp_timer.h"
+#include "scp_watchdog.h"
+#include "task.h"
+#include "timer.h"
+
+#include <assert.h>
+#include <string.h>
+
+#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args)
+
+#define TASK_EVENT_SUSPEND TASK_EVENT_CUSTOM_BIT(4)
+#define TASK_EVENT_RESUME TASK_EVENT_CUSTOM_BIT(5)
+#define CHECK_26M_PERIOD_US 50000
+
+enum scp_sr_state {
+	SR_S0,
+	SR_S02S3,
+	SR_S3,
+};
+
+enum scp_clock_source {
+	SCP_CLK_SYSTEM,
+	SCP_CLK_32K,
+	SCP_CLK_ULPOSC1,
+	SCP_CLK_ULPOSC2_LOW_SPEED,
+	SCP_CLK_ULPOSC2_HIGH_SPEED,
+};
+
+enum {
+	OPP_ULPOSC2_LOW_SPEED,
+	OPP_ULPOSC2_HIGH_SPEED,
+};
+
+static struct opp_ulposc_cfg {
+	uint32_t osc;
+	uint32_t div;
+	uint32_t fband;
+	uint32_t mod;
+	uint32_t cali;
+	uint32_t target_mhz;
+	uint32_t clk_div;
+} opp[] = {
+	[OPP_ULPOSC2_LOW_SPEED] = {
+		.osc = 1, .target_mhz = 326, .clk_div = CLK_DIV_SEL2, .div = 19,
+		.fband = 10, .mod = 0, .cali = 64, /* 326MHz / 2 = 163MHz */
+	},
+	[OPP_ULPOSC2_HIGH_SPEED] = {
+		.osc = 1, .target_mhz = 360, .clk_div = CLK_DIV_SEL1, .div = 21,
+		.fband = 10, .mod = 0, .cali = 64, /* 360MHz / 1 = 360MHz */
+	},
+};
+
+static inline void clock_busy_udelay(int usec)
+{
+	/*
+	 * Delaying by busy-looping, for place that can't use udelay because of
+	 * the clock not configured yet. The value 28 is chosen approximately
+	 * from experiment.
+	 *
+	 * `volatile' in order to avoid compiler to optimize the function out
+	 * (otherwise, the function will be eliminated).
+	 */
+	volatile int i = usec * 28;
+
+	while (--i)
+		;
+}
+
+static void clock_ulposc_config_default(struct opp_ulposc_cfg *opp)
+{
+	uint32_t val = 0;
+
+	/* set mod, div2_en = 0, cp_en = 0 */
+	val |= opp->mod << OSC_MOD_SHIFT;
+	/* set div */
+	val |= opp->div << OSC_DIV_SHIFT;
+	/* set F-band, I-band = 82 */
+	val |= (opp->fband << OSC_FBAND_SHIFT) | (82 << OSC_IBAND_SHIFT);
+	/* set calibration */
+	val |= opp->cali;
+	/* set control register 0 */
+	AP_ULPOSC_CON0(opp->osc) = val;
+
+	clock_busy_udelay(50);
+
+	/* bias = 65 */
+	val = 65 << OSC_BIAS_SHIFT;
+	/* rsv2 = 0, rsv1 = 41, cali_32k = 0 */
+	val |= 41 << OSC_RSV1_SHIFT;
+	/* set control register 1 */
+	AP_ULPOSC_CON1(opp->osc) = val;
+
+	/* set settle time */
+	SCP_CLK_HIGH_VAL = (SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) |
+			   CLK_HIGH_VAL_VAL(2);
+}
+
+static void clock_ulposc_config_cali(struct opp_ulposc_cfg *opp,
+				     uint32_t cali_val)
+{
+	uint32_t val;
+
+	val = AP_ULPOSC_CON0(opp->osc);
+	val &= ~OSC_CALI_MASK;
+	val |= cali_val;
+	AP_ULPOSC_CON0(opp->osc) = val;
+	opp->cali = cali_val;
+
+	clock_busy_udelay(50);
+}
+
+static uint32_t clock_ulposc_measure_freq(uint32_t osc)
+{
+	uint32_t result = 0;
+	int cnt;
+	uint32_t cali_0 = AP_CLK26CALI_0;
+	uint32_t cali_1 = AP_CLK26CALI_1;
+	uint32_t dbg_cfg = AP_CLK_DBG_CFG;
+	uint32_t misc_cfg = AP_CLK_MISC_CFG_0;
+
+	/* Set ckgen_load_cnt: CLK26CALI_1[25:16] */
+	AP_CLK26CALI_1 = CFG_CKGEN_LOAD_CNT;
+
+	/* before select meter clock input, bit[1:0] = b00 */
+	AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_MODE_MASK) | DBG_MODE_SET_CLOCK;
+
+	/* select monclk_ext2fqmtr_sel: AP_CLK_DBG_CFG[14:8] */
+	AP_CLK_DBG_CFG =
+		(AP_CLK_DBG_CFG & ~DBG_BIST_SOURCE_MASK) |
+		(osc == 0 ? DBG_BIST_SOURCE_ULPOSC1 : DBG_BIST_SOURCE_ULPOSC2);
+
+	/* set meter divisor to 1, bit[31:24] = b00000000 */
+	AP_CLK_MISC_CFG_0 = (AP_CLK_MISC_CFG_0 & ~MISC_METER_DIVISOR_MASK) |
+			    MISC_METER_DIV_1;
+
+	/* enable frequency meter, without start */
+	AP_CLK26CALI_0 |= CFG_FREQ_METER_ENABLE;
+
+	/* trigger frequency meter start */
+	AP_CLK26CALI_0 |= CFG_FREQ_METER_RUN;
+
+	clock_busy_udelay(45);
+
+	for (cnt = 10000; cnt > 0; --cnt) {
+		clock_busy_udelay(10);
+		if (!(AP_CLK26CALI_0 & CFG_FREQ_METER_RUN)) {
+			result = CFG_FREQ_COUNTER(AP_CLK26CALI_1);
+			break;
+		}
+	}
+
+	AP_CLK26CALI_0 = cali_0;
+	AP_CLK26CALI_1 = cali_1;
+	AP_CLK_DBG_CFG = dbg_cfg;
+	AP_CLK_MISC_CFG_0 = misc_cfg;
+
+	/* disable freq meter */
+	AP_CLK26CALI_0 &= ~CFG_FREQ_METER_ENABLE;
+
+	return result;
+}
+
+#define CAL_MIS_RATE 40
+static int clock_ulposc_is_calibrated(struct opp_ulposc_cfg *opp)
+{
+	uint32_t curr, target;
+
+	curr = clock_ulposc_measure_freq(opp->osc);
+	target = opp->target_mhz * 512 / 26;
+
+#ifdef DEBUG
+	CPRINTF("osc:%u, target=%uMHz, curr=%uMHz, cali:%u\n", opp->osc,
+		opp->target_mhz, (curr * 26) / 512, opp->cali);
+#endif
+
+	/* check if calibrated value is in the range of target value +- 4% */
+	if (curr > (target * (1000 - CAL_MIS_RATE) / 1000) &&
+	    curr < (target * (1000 + CAL_MIS_RATE) / 1000))
+		return 1;
+	else
+		return 0;
+}
+
+static uint32_t clock_ulposc_process_cali(struct opp_ulposc_cfg *opp)
+{
+	uint32_t current_val = 0;
+	uint32_t target_val = opp->target_mhz * 512 / 26;
+	uint32_t middle, min = 0, max = OSC_CALI_MASK;
+	uint32_t diff_by_min, diff_by_max, cal_result;
+
+	do {
+		middle = (min + max) / 2;
+		if (middle == min)
+			break;
+
+		clock_ulposc_config_cali(opp, middle);
+		current_val = clock_ulposc_measure_freq(opp->osc);
+
+		if (current_val > target_val)
+			max = middle;
+		else
+			min = middle;
+	} while (min <= max);
+
+	clock_ulposc_config_cali(opp, min);
+	current_val = clock_ulposc_measure_freq(opp->osc);
+	if (current_val > target_val)
+		diff_by_min = current_val - target_val;
+	else
+		diff_by_min = target_val - current_val;
+
+	clock_ulposc_config_cali(opp, max);
+	current_val = clock_ulposc_measure_freq(opp->osc);
+	if (current_val > target_val)
+		diff_by_max = current_val - target_val;
+	else
+		diff_by_max = target_val - current_val;
+
+	if (diff_by_min < diff_by_max)
+		cal_result = min;
+	else
+		cal_result = max;
+
+	clock_ulposc_config_cali(opp, cal_result);
+	if (!clock_ulposc_is_calibrated(opp))
+		assert(0);
+
+	return cal_result;
+}
+
+static void clock_high_enable(int osc)
+{
+	/* enable high speed clock */
+	SCP_CLK_ENABLE |= CLK_HIGH_EN;
+
+	switch (osc) {
+	case 0:
+		/* after 150us, enable ULPOSC */
+		clock_busy_udelay(150);
+		SCP_CLK_ENABLE |= CLK_HIGH_CG | CLK_HIGH_EN;
+
+		/* topck ulposc1 clk gating off */
+		AP_CLK_CFG_29_CLR = PDN_F_ULPOSC_CK;
+		/* select topck ulposc1 as scp clk parent */
+		AP_CLK_CFG_29_CLR = ULPOSC1_CLK_SEL;
+
+		AP_CLK_CFG_UPDATE3 = F_ULPOSC_CK_UPDATE;
+		clock_busy_udelay(50);
+		break;
+	case 1:
+		/* turn off ULPOSC2 high-core-disable switch */
+		SCP_CLK_ON_CTRL &= ~HIGH_CORE_DIS_SUB;
+		/* after 150us, scp requests ULPOSC2 high core clock */
+		clock_busy_udelay(150);
+		SCP_CLK_HIGH_CORE_CG |= HIGH_CORE_CG;
+		SCP_CLK_ENABLE &= ~CLK_HIGH_CG;
+		clock_busy_udelay(50);
+
+		/* topck ulposc2 clk gating off */
+		AP_CLK_CFG_29_CLR = PDN_F_ULPOSC_CORE_CK;
+		/* select topck ulposc2 as scp clk parent */
+		AP_CLK_CFG_29_CLR = ULPOSC2_CLK_SEL;
+
+		AP_CLK_CFG_UPDATE3 = F_ULPOSC_CORE_CK_UPDATE;
+		clock_busy_udelay(50);
+		break;
+	default:
+		break;
+	}
+}
+
+static void clock_high_disable(int osc)
+{
+	switch (osc) {
+	case 0:
+		/* topck ulposc1 clk gating on */
+		AP_CLK_CFG_29_SET = PDN_F_ULPOSC_CK;
+		AP_CLK_CFG_UPDATE3 = F_ULPOSC_CK_UPDATE;
+		clock_busy_udelay(50);
+
+		/* scp doesn't request ulposc1 clk */
+		SCP_CLK_ENABLE &= ~CLK_HIGH_CG;
+		clock_busy_udelay(50);
+		SCP_CLK_ENABLE &= ~CLK_HIGH_EN;
+		clock_busy_udelay(50);
+		break;
+	case 1:
+		/* topck ulposc2 clk gating on */
+		AP_CLK_CFG_29_SET = PDN_F_ULPOSC_CORE_CK;
+		AP_CLK_CFG_UPDATE3 = F_ULPOSC_CORE_CK_UPDATE;
+		clock_busy_udelay(50);
+
+		/* scp doesn't request ulposc2 clk */
+		SCP_CLK_HIGH_CORE_CG &= ~HIGH_CORE_CG;
+		clock_busy_udelay(50);
+		SCP_CLK_ON_CTRL |= HIGH_CORE_DIS_SUB;
+		clock_busy_udelay(50);
+		break;
+	default:
+		break;
+	}
+}
+
+static void clock_calibrate_ulposc(struct opp_ulposc_cfg *opp)
+{
+	/*
+	 * ULPOSC1(osc=0) is already
+	 * - calibrated
+	 * - enabled in coreboot
+	 * - used by pmic wrapper
+	 */
+	if (opp->osc != 0) {
+		clock_high_disable(opp->osc);
+		clock_ulposc_config_default(opp);
+		clock_high_enable(opp->osc);
+	}
+
+	/* Calibrate only if it is not accurate enough. */
+	if (!clock_ulposc_is_calibrated(opp))
+		opp->cali = clock_ulposc_process_cali(opp);
+}
+
+static void clock_select_clock(enum scp_clock_source src)
+{
+	uint32_t sel;
+	uint32_t div;
+
+	switch (src) {
+	case SCP_CLK_SYSTEM:
+		div = CLK_DIV_SEL1;
+		sel = CLK_SW_SEL_SYSTEM;
+		break;
+	case SCP_CLK_32K:
+		div = CLK_DIV_SEL1;
+		sel = CLK_SW_SEL_32K;
+		break;
+	case SCP_CLK_ULPOSC1:
+		div = CLK_DIV_SEL1;
+		sel = CLK_SW_SEL_ULPOSC1;
+		break;
+	case SCP_CLK_ULPOSC2_LOW_SPEED:
+		/* parking at scp system clk until ulposc clk is ready */
+		clock_select_clock(SCP_CLK_SYSTEM);
+
+		clock_ulposc_config_cali(&opp[OPP_ULPOSC2_LOW_SPEED],
+					 opp[OPP_ULPOSC2_LOW_SPEED].cali);
+		div = opp[OPP_ULPOSC2_LOW_SPEED].clk_div;
+
+		sel = CLK_SW_SEL_ULPOSC2;
+		break;
+	case SCP_CLK_ULPOSC2_HIGH_SPEED:
+		/* parking at scp system clk until ulposc clk is ready */
+		clock_select_clock(SCP_CLK_SYSTEM);
+
+		clock_ulposc_config_cali(&opp[OPP_ULPOSC2_HIGH_SPEED],
+					 opp[OPP_ULPOSC2_HIGH_SPEED].cali);
+		div = opp[OPP_ULPOSC2_HIGH_SPEED].clk_div;
+
+		sel = CLK_SW_SEL_ULPOSC2;
+		break;
+	default:
+		div = CLK_DIV_SEL1;
+		sel = CLK_SW_SEL_SYSTEM;
+		break;
+	}
+
+	SCP_CLK_DIV_SEL = div;
+	SCP_CLK_SW_SEL = sel;
+}
+
+__override void
+power_chipset_handle_host_sleep_event(enum host_sleep_event state,
+				      struct host_sleep_event_context *ctx)
+{
+	if (state == HOST_SLEEP_EVENT_S3_SUSPEND) {
+		task_set_event(TASK_ID_SR, TASK_EVENT_SUSPEND);
+	} else if (state == HOST_SLEEP_EVENT_S3_RESUME) {
+		task_set_event(TASK_ID_SR, TASK_EVENT_RESUME);
+	}
+}
+
+void sr_task(void *u)
+{
+	enum scp_sr_state state = SR_S0;
+	uint32_t event;
+	uint32_t prev, now;
+
+	while (1) {
+		switch (state) {
+		case SR_S0:
+			event = task_wait_event(-1);
+			if (event & TASK_EVENT_SUSPEND) {
+				timer_enable(TIMER_SR);
+				prev = timer_read_raw_sr();
+				state = SR_S02S3;
+			}
+			break;
+		case SR_S02S3:
+			event = task_wait_event(CHECK_26M_PERIOD_US);
+			if (event & TASK_EVENT_RESUME) {
+				/* suspend is aborted */
+				timer_disable(TIMER_SR);
+				state = SR_S0;
+			} else if (event & TASK_EVENT_TIMER) {
+				now = timer_read_raw_sr();
+				if (now != prev) {
+					/* 26M is still on */
+					prev = now;
+				} else {
+					/* 26M is off */
+					state = SR_S3;
+				}
+			}
+			break;
+		case SR_S3:
+			interrupt_disable();
+			watchdog_disable();
+
+			/* change to 26M to stop core at here */
+			clock_select_clock(SCP_CLK_SYSTEM);
+
+			/* 26M is back */
+			clock_select_clock(SCP_CLK_ULPOSC2_HIGH_SPEED);
+
+			watchdog_enable();
+			interrupt_enable();
+			timer_disable(TIMER_SR);
+			state = SR_S0;
+			break;
+		}
+	}
+}
+
+void clock_init(void)
+{
+	uint32_t i;
+
+	/* select scp system clock (default 26MHz) */
+	clock_select_clock(SCP_CLK_SYSTEM);
+
+	/* set VREQ to HW mode */
+	SCP_CPU_VREQ_CTRL = VREQ_SEL | VREQ_DVFS_SEL;
+	SCP_CLK_CTRL_GENERAL_CTRL &= ~VREQ_PMIC_WRAP_SEL;
+	SCP_SEC_CTRL &= ~VREQ_SECURE_DIS;
+
+	/* set DDREN to auto mode */
+	SCP_SYS_CTRL |= AUTO_DDREN;
+
+	/* set settle time */
+	SCP_CLK_SYS_VAL = (SCP_CLK_SYS_VAL & ~CLK_SYS_VAL_MASK) |
+			  CLK_SYS_VAL_VAL(1);
+	SCP_CLK_HIGH_VAL = (SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) |
+			   CLK_HIGH_VAL_VAL(1);
+	SCP_SLEEP_CTRL = (SCP_SLEEP_CTRL & ~VREQ_COUNT_MASK) |
+			 VREQ_COUNT_VAL(1);
+
+	/* turn off ULPOSC2 */
+	SCP_CLK_ON_CTRL |= HIGH_CORE_DIS_SUB;
+
+	/* calibrate ULPOSC2 */
+	for (i = 0; i < ARRAY_SIZE(opp); ++i)
+		clock_calibrate_ulposc(&opp[i]);
+
+	/* select ULPOSC2 high speed SCP clock */
+	clock_select_clock(SCP_CLK_ULPOSC2_HIGH_SPEED);
+
+	/* select BCLK to use ULPOSC / 8 */
+	SCP_BCLK_CK_SEL = BCLK_CK_SEL_ULPOSC_DIV8;
+
+	/* enable default clock gate */
+	SCP_SET_CLK_CG |= CG_DMA_CH3 | CG_DMA_CH2 | CG_DMA_CH1 | CG_DMA_CH0 |
+			  CG_I2C_MCLK | CG_MAD_MCLK | CG_AP2P_MCLK;
+}
+
+#ifdef DEBUG
+int command_ulposc(int argc, const char *argv[])
+{
+	uint32_t osc;
+
+	for (osc = 0; osc <= OPP_ULPOSC2_HIGH_SPEED; ++osc)
+		ccprintf("ULPOSC%u frequency: %u kHz\n", osc + 1,
+			 clock_ulposc_measure_freq(osc) * 26 * 1000 / 512);
+
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(ulposc, command_ulposc, "[ulposc]",
+			"Measure ULPOSC frequency");
+#endif
+
+test_mockable void clock_enable_module(enum module_id module, int enable)
+{
+}
diff --git a/chip/mt_scp/mt8195/clock_regs.h b/chip/mt_scp/mt8195/clock_regs.h
new file mode 100644
index 0000000000..7744c3df54
--- /dev/null
+++ b/chip/mt_scp/mt8195/clock_regs.h
@@ -0,0 +1,90 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* SCP clock module registers */
+
+#ifndef __CROS_EC_CLOCK_REGS_H
+#define __CROS_EC_CLOCK_REGS_H
+
+/* clock source select */
+#define SCP_CLK_SW_SEL REG32(SCP_CLK_CTRL_BASE + 0x0000)
+#define CLK_SW_SEL_SYSTEM 0
+#define CLK_SW_SEL_32K 1
+#define CLK_SW_SEL_ULPOSC2 2
+#define CLK_SW_SEL_ULPOSC1 3
+#define SCP_CLK_ENABLE REG32(SCP_CLK_CTRL_BASE + 0x0004)
+#define CLK_HIGH_EN BIT(1) /* ULPOSC */
+#define CLK_HIGH_CG BIT(2)
+/* clock general control */
+#define SCP_CLK_CTRL_GENERAL_CTRL REG32(SCP_CLK_CTRL_BASE + 0x009C)
+#define VREQ_PMIC_WRAP_SEL (0x3)
+
+/* TOPCK clk */
+#define TOPCK_BASE AP_REG_BASE
+#define AP_CLK_CFG_UPDATE3 REG32(TOPCK_BASE + 0x0010)
+#define F_ULPOSC_CK_UPDATE BIT(21)
+#define F_ULPOSC_CORE_CK_UPDATE BIT(22)
+#define AP_CLK_CFG_29_SET REG32(TOPCK_BASE + 0x0180)
+#define AP_CLK_CFG_29_CLR REG32(TOPCK_BASE + 0x0184)
+#define ULPOSC1_CLK_SEL (0x3 << 8)
+#define PDN_F_ULPOSC_CK BIT(15)
+#define ULPOSC2_CLK_SEL (0x3 << 16)
+#define PDN_F_ULPOSC_CORE_CK BIT(23)
+/* OSC meter */
+#define AP_CLK_DBG_CFG REG32(TOPCK_BASE + 0x020C)
+#define DBG_MODE_MASK 3
+#define DBG_MODE_SET_CLOCK 0
+#define DBG_BIST_SOURCE_MASK (0x7f << 8)
+#define DBG_BIST_SOURCE_ULPOSC1 (0x30 << 8)
+#define DBG_BIST_SOURCE_ULPOSC2 (0x32 << 8)
+#define AP_CLK26CALI_0 REG32(TOPCK_BASE + 0x0218)
+#define CFG_FREQ_METER_RUN BIT(4)
+#define CFG_FREQ_METER_ENABLE BIT(7)
+#define AP_CLK26CALI_1 REG32(TOPCK_BASE + 0x021C)
+#define CFG_CKGEN_LOAD_CNT 0x01ff0000
+#define CFG_FREQ_COUNTER(CFG1) ((CFG1)&0xFFFF)
+#define AP_CLK_MISC_CFG_0 REG32(TOPCK_BASE + 0x022C)
+#define MISC_METER_DIVISOR_MASK 0xff000000
+#define MISC_METER_DIV_1 0
+/*
+ * ULPOSC
+ * osc: 0 for ULPOSC1, 1 for ULPOSC2.
+ */
+#define AP_ULPOSC_CON0_BASE (AP_REG_BASE + 0xC2B0)
+#define AP_ULPOSC_CON1_BASE (AP_REG_BASE + 0xC2B4)
+#define AP_ULPOSC_CON0(osc) REG32(AP_ULPOSC_CON0_BASE + (osc)*0x10)
+#define AP_ULPOSC_CON1(osc) REG32(AP_ULPOSC_CON1_BASE + (osc)*0x10)
+/*
+ * AP_ULPOSC_CON0
+ * bit0-6: calibration
+ * bit7-13: iband
+ * bit14-17: fband
+ * bit18-23: div
+ * bit24: cp_en
+ * bit25-26: mod
+ * bit27: div2_en
+ * bit28-31: reserved
+ */
+#define OSC_CALI_SHIFT 0
+#define OSC_CALI_MASK 0x7f
+#define OSC_IBAND_SHIFT 7
+#define OSC_FBAND_SHIFT 14
+#define OSC_DIV_SHIFT 18
+#define OSC_CP_EN BIT(24)
+#define OSC_MOD_SHIFT 25
+#define OSC_DIV2_EN BIT(27)
+/*
+ * AP_ULPOSC_CON1
+ * bit0-7: rsv1
+ * bit8-15: rsv2
+ * bit16-23: 32K calibration
+ * bit24-31: bias
+ */
+#define OSC_RSV1_SHIFT 0
+#define OSC_RSV2_SHIFT 8
+#define OSC_32KCALI_SHIFT 16
+#define OSC_BIAS_SHIFT 24
+
+#endif /* __CROS_EC_CLOCK_REGS_H */
diff --git a/chip/mt_scp/mt8195/intc.h b/chip/mt_scp/mt8195/intc.h
new file mode 100644
index 0000000000..dd3874718e
--- /dev/null
+++ b/chip/mt_scp/mt8195/intc.h
@@ -0,0 +1,166 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_INTC_H
+#define __CROS_EC_INTC_H
+
+/* INTC */
+#define SCP_INTC_IRQ_POL0 0xef001f20
+#define SCP_INTC_IRQ_POL1 0x044001dd
+#define SCP_INTC_IRQ_POL2 0xffffdfe0
+#define SCP_INTC_IRQ_POL3 0xfffffff3
+#define SCP_INTC_GRP_LEN 4
+#define SCP_INTC_IRQ_COUNT 127
+
+/* IRQ numbers */
+#define SCP_IRQ_GIPC_IN0 0
+#define SCP_IRQ_GIPC_IN1 1
+#define SCP_IRQ_GIPC_IN2 2
+#define SCP_IRQ_GIPC_IN3 3
+/* 4 */
+#define SCP_IRQ_SPM 4
+#define SCP_IRQ_AP_CIRQ 5
+#define SCP_IRQ_EINT 6
+#define SCP_IRQ_PMIC 7
+/* 8 */
+#define SCP_IRQ_UART0_TX 8
+#define SCP_IRQ_UART1_TX 9
+#define SCP_IRQ_I2C0 10
+#define SCP_IRQ_I2C1_0 11
+/* 12 */
+#define SCP_IRQ_BUS_DBG_TRACKER 12
+#define SCP_IRQ_CLK_CTRL 13
+#define SCP_IRQ_VOW 14
+#define SCP_IRQ_TIMER0 15
+/* 16 */
+#define SCP_IRQ_TIMER1 16
+#define SCP_IRQ_TIMER2 17
+#define SCP_IRQ_TIMER3 18
+#define SCP_IRQ_TIMER4 19
+/* 20 */
+#define SCP_IRQ_TIMER5 20
+#define SCP_IRQ_OS_TIMER 21
+#define SCP_IRQ_UART0_RX 22
+#define SCP_IRQ_UART1_RX 23
+/* 24 */
+#define SCP_IRQ_GDMA 24
+#define SCP_IRQ_AUDIO 25
+#define SCP_IRQ_MD_DSP 26
+#define SCP_IRQ_ADSP 27
+/* 28 */
+#define SCP_IRQ_CPU_TICK 28
+#define SCP_IRQ_SPI0 29
+#define SCP_IRQ_SPI1 30
+#define SCP_IRQ_SPI2 31
+/* 32 */
+#define SCP_IRQ_NEW_INFRA_SYS_CIRQ 32
+#define SCP_IRQ_DBG 33
+#define SCP_IRQ_GCE 34
+#define SCP_IRQ_MDP_GCE 35
+/* 36 */
+#define SCP_IRQ_VDEC 36
+#define SCP_IRQ_WDT 37
+#define SCP_IRQ_VDEC_LAT 38
+#define SCP_IRQ_VDEC1 39
+/* 40 */
+#define SCP_IRQ_VDEC1_LAT 40
+#define SCP_IRQ_INFRA 41
+#define SCP_IRQ_CLK_CTRL_CORE 42
+#define SCP_IRQ_CLK_CTRL2_CORE 43
+/* 44 */
+#define SCP_IRQ_CLK_CTRL2 44
+#define SCP_IRQ_GIPC_IN4 45 /* HALT */
+#define SCP_IRQ_PERIBUS_TIMEOUT 46
+#define SCP_IRQ_INFRABUS_TIMEOUT 47
+/* 48 */
+#define SCP_IRQ_MET0 48
+#define SCP_IRQ_MET1 49
+#define SCP_IRQ_MET2 50
+#define SCP_IRQ_MET3 51
+/* 52 */
+#define SCP_IRQ_AP_WDT 52
+#define SCP_IRQ_L2TCM_SEC_VIO 53
+#define SCP_IRQ_VDEC_INT_LINE_CNT 54
+#define SCP_IRQ_VOW_DATAIN 55
+/* 56 */
+#define SCP_IRQ_I3C0_IBI_WAKE 56
+#define SCP_IRQ_I3C1_IBI_WAKE 57
+#define SCP_IRQ_VENC 58
+#define SCP_IRQ_APU_ENGINE 59
+/* 60 */
+#define SCP_IRQ_MBOX0 60
+#define SCP_IRQ_MBOX1 61
+#define SCP_IRQ_MBOX2 62
+#define SCP_IRQ_MBOX3 63
+/* 64 */
+#define SCP_IRQ_MBOX4 64
+#define SCP_IRQ_SYS_CLK_REQ 65
+#define SCP_IRQ_BUS_REQ 66
+#define SCP_IRQ_APSRC_REQ 67
+/* 68 */
+#define SCP_IRQ_APU_MBOX 68
+#define SCP_IRQ_DEVAPC_SECURE_VIO 69
+#define SCP_IRQ_APDMA0 70
+#define SCP_IRQ_APDMA1 71
+/* 72 */
+#define SCP_IRQ_APDMA2 72
+#define SCP_IRQ_APDMA3 73
+#define SCP_IRQ_APDMA4 74
+#define SCP_IRQ_APDMA5 75
+/* 76 */
+#define SCP_IRQ_HDMIRX_PM_DVI_SQH 76
+#define SCP_IRQ_HDMIRX_RESERVED 77
+#define SCP_IRQ_NNA0_0 78
+#define SCP_IRQ_NNA0_1 79
+/* 80 */
+#define SCP_IRQ_NNA0_2 80
+#define SCP_IRQ_NNA1_0 81
+#define SCP_IRQ_NNA1_1 82
+#define SCP_IRQ_NNA1_2 83
+/* 84 */
+#define SCP_IRQ_JPEGENC 84
+#define SCP_IRQ_JPEGDEC 85
+#define SCP_IRQ_JPEGDEC_C2 86
+#define SCP_IRQ_VENC_C1 87
+/* 88 */
+#define SCP_IRQ_JPEGENC_C1 88
+#define SCP_IRQ_JPEGDEC_C1 89
+#define SCP_IRQ_HDMITX 90
+#define SCP_IRQ_HDMI2 91
+/* 92 */
+#define SCP_IRQ_EARC 92
+#define SCP_IRQ_CEC 93
+#define SCP_IRQ_HDMI_DEV_DET 94
+#define SCP_IRQ_HDMIRX_OUT_ARM_PHY 95
+/* 96 */
+#define SCP_IRQ_I2C2 96
+#define SCP_IRQ_I2C3 97
+#define SCP_IRQ_I3C2_IBI_WAKE 98
+#define SCP_IRQ_I3C3_IBI_WAKE 99
+/* 100 */
+#define SCP_IRQ_SYS_I2C_0 100
+#define SCP_IRQ_SYS_I2C_1 101
+#define SCP_IRQ_SYS_I2C_2 102
+#define SCP_IRQ_SYS_I2C_3 103
+/* 104 */
+#define SCP_IRQ_SYS_I2C_4 104
+#define SCP_IRQ_SYS_I2C_5 105
+#define SCP_IRQ_SYS_I2C_6 106
+#define SCP_IRQ_SYS_I2C_7 107
+/* 108 */
+#define SCP_IRQ_DISP2ADSP_0 108
+#define SCP_IRQ_DISP2ADSP_1 109
+#define SCP_IRQ_DISP2ADSP_2 110
+#define SCP_IRQ_DISP2ADSP_3 111
+/* 112 */
+#define SCP_IRQ_DISP2ADSP_4 112
+#define SCP_IRQ_VDO1_DISP_MON2ADSP_0 113
+#define SCP_IRQ_VDO1_DISP_MON2ADSP_1 114
+#define SCP_IRQ_VDO1_DISP_MON2ADSP_2 115
+/* 116 */
+#define SCP_IRQ_GCE1_SECURE 116
+#define SCP_IRQ_GCE_SECURE 117
+
+#endif /* __CROS_EC_INTC_H */
diff --git a/chip/mt_scp/mt8195/uart.c b/chip/mt_scp/mt8195/uart.c
new file mode 100644
index 0000000000..faad1a41a4
--- /dev/null
+++ b/chip/mt_scp/mt8195/uart.c
@@ -0,0 +1,23 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* SCP UART module for MT8195 specific */
+
+#include "uart_regs.h"
+
+/*
+ * UARTN == 0, SCP UART0
+ * UARTN == 1, SCP UART1
+ * UARTN == 2, AP UART1
+ */
+#define UARTN CONFIG_UART_CONSOLE
+
+void uart_init_pinmux(void)
+{
+#if UARTN == 0
+	SCP_UART_CK_SEL |= UART0_CK_SEL_VAL(UART_CK_SEL_ULPOSC);
+	SCP_SET_CLK_CG |= CG_UART0_MCLK | CG_UART0_BCLK | CG_UART0_RST;
+#endif
+}
diff --git a/chip/mt_scp/mt8195/video.c b/chip/mt_scp/mt8195/video.c
new file mode 100644
index 0000000000..1b70f56b4a
--- /dev/null
+++ b/chip/mt_scp/mt8195/video.c
@@ -0,0 +1,19 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "video.h"
+
+uint32_t video_get_enc_capability(void)
+{
+	return VENC_CAP_4K;
+}
+
+uint32_t video_get_dec_capability(void)
+{
+	return VDEC_CAP_INNER_RACING | VDEC_CAP_MM21 | VDEC_CAP_H264_SLICE |
+	       VDEC_CAP_VP8_FRAME | VDEC_CAP_VP9_FRAME | VDEC_CAP_AV1_FRAME |
+	       VDEC_CAP_HEVC_SLICE;
+}
diff --git a/chip/mt_scp/registers.h b/chip/mt_scp/registers.h
deleted file mode 100644
index 21270b452d..0000000000
--- a/chip/mt_scp/registers.h
+++ /dev/null
@@ -1,645 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Register map for SCP
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#define __CROS_EC_REGISTERS_H
-
-#include "common.h"
-#include "compile_time_macros.h"
-
-/* IRQ numbers */
-#define SCP_IRQ_IPC0			0
-#define SCP_IRQ_IPC1			1
-#define SCP_IRQ_IPC2			2
-#define SCP_IRQ_IPC3			3
-#define SCP_IRQ_SPM			4
-#define SCP_IRQ_CIRQ			5
-#define SCP_IRQ_EINT			6
-#define SCP_IRQ_PMIC			7
-#define SCP_IRQ_UART0			8
-#define SCP_IRQ_UART1			9
-#define SCP_IRQ_I2C0			10
-#define SCP_IRQ_I2C1			11
-#define SCP_IRQ_I2C2			12
-#define SCP_IRQ_CLOCK			13
-#define SCP_IRQ_MAD_FIFO		14
-#define SCP_IRQ_TIMER0			15
-#define SCP_IRQ_TIMER1			16
-#define SCP_IRQ_TIMER2			17
-#define SCP_IRQ_TIMER3			18
-#define SCP_IRQ_TIMER4			19
-#define SCP_IRQ_TIMER5			20
-#define SCP_IRQ_TIMER_STATUS		21
-#define SCP_IRQ_UART0_RX		22
-#define SCP_IRQ_UART1_RX		23
-#define SCP_IRQ_DMA			24
-#define SCP_IRQ_AUDIO			25
-#define SCP_IRQ_MD1_F216		26
-#define SCP_IRQ_MD1			27
-#define SCP_IRQ_C2K			28
-#define SCP_IRQ_SPI0			29
-#define SCP_IRQ_SPI1			30
-#define SCP_IRQ_SPI2			31
-#define SCP_IRQ_AP_EINT			32
-#define SCP_IRQ_DEBUG			33
-#define SCP_CCIF0			34
-#define SCP_CCIF1			35
-#define SCP_CCIF2			36
-#define SCP_IRQ_WDT			37
-#define SCP_IRQ_USB0			38
-#define SCP_IRQ_USB1			39
-#define SCP_IRQ_TWAM			40
-#define SCP_IRQ_INFRA			41
-#define SCP_IRQ_HWDVFS_HIGH		42
-#define SCP_IRQ_HWDVFS_LOW		43
-#define SCP_IRQ_CLOCK2			44
-/* RESERVED 45-52 */
-#define SCP_IRQ_AP_EINT2		53
-#define SCP_IRQ_AP_EINT_EVT		54
-#define SCP_IRQ_MAD_DATA		55
-
-#define SCP_CFG_BASE			0x405C0000
-
-#define SCP_AP_RESOURCE			REG32(SCP_CFG_BASE + 0x04)
-#define SCP_BUS_RESOURCE		REG32(SCP_CFG_BASE + 0x08)
-
-/* SCP to host interrupt */
-#define SCP_HOST_INT			REG32(SCP_CFG_BASE + 0x1C)
-#define   IPC_SCP2HOST_SSHUB		0xff0000
-#define   WDT_INT			0x100
-#define   IPC_SCP2HOST                  0xff
-#define   IPC_SCP2HOST_BIT		0x1
-
-/* SCP to SPM interrupt */
-#define SCP_SPM_INT			REG32(SCP_CFG_BASE + 0x20)
-#define   SPM_INT_A2SPM			BIT(0)
-#define   SPM_INT_B2SPM			BIT(1)
-#define SCP_SPM_INT2			REG32(SCP_CFG_BASE + 0x24)
-
-/*
- * AP side to SCP IPC
- * APMCU writes 1 bit to trigger ith IPC to SCP.
- * SCP writes 1 bit to ith bit to clear ith IPC.
- */
-#define SCP_GIPC_IN			REG32(SCP_CFG_BASE + 0x28)
-  #define SCP_GIPC_IN_CLEAR_IPCN(n)	(1 << (n))
-  #define SCP_GPIC_IN_CLEAR_ALL		0x7FFFF
-#define SCP_CONN_INT			REG32(SCP_CFG_BASE + 0x2C)
-
-/* 8 general purpose registers, 0 ~ 7 */
-#define SCP_GPR				REG32_ADDR(SCP_CFG_BASE + 0x50)
-/*
- * SCP_GPR[0]
- *   b15-b0   : scratchpad
- *   b31-b16  : saved flags
- * SCP_GPR[1]
- *   b15-b0   : power on state
- */
-#define SCP_PWRON_STATE			SCP_GPR[1]
-#define   PWRON_DEFAULT			0xdee80000
-#define   PWRON_WATCHDOG		BIT(0)
-#define   PWRON_RESET			BIT(1)
-/* AP defined features */
-#define SCP_EXPECTED_FREQ		SCP_GPR[3]
-#define SCP_CURRENT_FREQ		SCP_GPR[4]
-#define SCP_REBOOT			SCP_GPR[5]
-#define  READY_TO_REBOOT		0x34
-#define  REBOOT_OK			1
-
-/* Miscellaneous */
-#define SCP_SEMAPHORE			REG32(SCP_CFG_BASE + 0x90)
-#define CORE_CONTROL			REG32(SCP_CFG_BASE + 0xA0)
-#define CORE_FPU_FLAGS			REG32(SCP_CFG_BASE + 0xA4)
-#define CORE_REG_SP			REG32(SCP_CFG_BASE + 0xA8)
-#define CORE_REG_LR			REG32(SCP_CFG_BASE + 0xAC)
-#define CORE_REG_PSP			REG32(SCP_CFG_BASE + 0xB0)
-#define CORE_REG_PC			REG32(SCP_CFG_BASE + 0xB4)
-#define SCP_SLP_PROTECT_CFG		REG32(SCP_CFG_BASE + 0xC8)
-#define   P_CACHE_SLP_PROT_EN		BIT(3)
-#define   D_CACHE_SLP_PROT_EN		BIT(4)
-#define SCP_ONE_TIME_LOCK		REG32(SCP_CFG_BASE + 0xDC)
-#define SCP_SECURE_CTRL			REG32(SCP_CFG_BASE + 0xE0)
-#define   ENABLE_SPM_MASK_VREQ		BIT(28)
-#define   DISABLE_REMAP			BIT(22)
-#define   DISABLE_JTAG			BIT(21)
-#define   DISABLE_AP_TCM		BIT(20)
-#define SCP_SYS_CTRL			REG32(SCP_CFG_BASE + 0xE4)
-#define   DDREN_FIX_VALUE		BIT(28)
-#define   AUTO_DDREN			BIT(18)
-
-/* Memory remap control */
-/*
- * EXT_ADDR3[29:24] remap register for addr msb 31~28 equal to 0x7
- * EXT_ADDR2[21:16] remap register for addr msb 31~28 equal to 0x6
- * EXT_ADDR1[13:8]  remap register for addr msb 31~28 equal to 0x3
- * EXT_ADDR0[5:0]   remap register for addr msb 31~28 equal to 0x2
- */
-#define SCP_REMAP_CFG1			REG32(SCP_CFG_BASE + 0x120)
-/*
- * EXT_ADDR7[29:24] remap register for addr msb 31~28 equal to 0xb
- * EXT_ADDR6[21:16] remap register for addr msb 31~28 equal to 0xa
- * EXT_ADDR5[13:8]  remap register for addr msb 31~28 equal to 0x9
- * EXT_ADDR4[5:0]   remap register for addr msb 31~28 equal to 0x8
- */
-#define SCP_REMAP_CFG2			REG32(SCP_CFG_BASE + 0x124)
-/*
- * AUD_ADDR[31:28]  remap register for addr msb 31~28 equal to 0xd
- * EXT_ADDR10[21:16]remap register for addr msb 31~28 equal to 0xf
- * EXT_ADDR9[13:8]  remap register for addr msb 31~28 equal to 0xe
- * EXT_ADDR8[5:0]   remap register for addr msb 31~28 equal to 0xc
- */
-#define SCP_REMAP_CFG3			REG32(SCP_CFG_BASE + 0x128)
-
-#define SCP_REMAP_ADDR_SHIFT		28
-#define SCP_REMAP_ADDR_LSB_MASK		(BIT(SCP_REMAP_ADDR_SHIFT) - 1)
-#define SCP_REMAP_ADDR_MSB_MASK		((~0) << SCP_REMAP_ADDR_SHIFT)
-
-/* Cached memory remap control */
-#define SCP_L1_REMAP_CFG0		REG32(SCP_CFG_BASE + 0x12C)
-/*
- * L1C_EXT_ADDR1[29:16] remap register for addr msb 31~20 equal to 0x401
- * L1C_EXT_ADDR0[13:0]  remap register for addr msb 31~20 equal to 0x400
- */
-#define SCP_L1_REMAP_CFG1		REG32(SCP_CFG_BASE + 0x130)
-/*
- * L1C_EXT_ADDR3[29:16] remap register for addr msb 31~20 equal to 0x403
- * L1C_EXT_ADDR2[13:0]  remap register for addr msb 31~20 equal to 0x402
- */
-#define SCP_L1_REMAP_CFG2		REG32(SCP_CFG_BASE + 0x134)
-/*
- * L1C_EXT_ADDR5[29:16] remap register for addr msb 31~20 equal to 0x405
- * L1C_EXT_ADDR4[13:0]  remap register for addr msb 31~20 equal to 0x404
- */
-#define SCP_L1_REMAP_CFG3		REG32(SCP_CFG_BASE + 0x138)
-/*
- * L1C_EXT_ADDR_OTHER1[13:8] Remap register for addr msb 31 to 28 equal to 0x1
- * L1C_EXT_ADDR_OTHER0[5:0] Remap register for addr msb 31 to 28 equal to 0x0
- * and not overlap with L1C_EXT_ADDR0 to L1C_EXT_ADDR7
- */
-#define SCP_L1_REMAP_OTHER		REG32(SCP_CFG_BASE + 0x13C)
-
-#define SCP_L1_EXT_ADDR_SHIFT		20
-#define SCP_L1_EXT_ADDR_OTHER_SHIFT	28
-#define SCP_L1_EXT_ADDR_OTHER_LSB_MASK	(BIT(SCP_REMAP_ADDR_SHIFT) - 1)
-#define SCP_L1_EXT_ADDR_OTHER_MSB_MASK	((~0) << SCP_REMAP_ADDR_SHIFT)
-
-/* Audio/voice FIFO */
-#define SCP_AUDIO_BASE			(SCP_CFG_BASE + 0x1000)
-#define SCP_VIF_FIFO_EN			REG32(SCP_AUDIO_BASE)
-#define   VIF_FIFO_RSTN			(1 << 0)
-#define   VIF_FIFO_IRQ_EN		(1 << 1)
-#define   VIF_FIFO_SRAM_PWR		(1 << 2)
-#define   VIF_FIFO_RSTN_STATUS		(1 << 4)
-#define SCP_VIF_FIFO_STATUS		REG32(SCP_AUDIO_BASE + 0x04)
-#define   VIF_FIFO_VALID		(1 << 0)
-#define   VIF_FIFO_FULL			(1 << 4)
-#define   VIF_FIFO_LEVEL(status)	(((status) >> 16) & 0xff)
-#define   VIF_FIFO_MAX			256
-#define SCP_VIF_FIFO_DATA		REG32(SCP_AUDIO_BASE + 0x08)
-#define SCP_VIF_FIFO_DATA_THRE		REG32(SCP_AUDIO_BASE + 0x0C)
-/* VIF IRQ status clears on read! */
-#define SCP_VIF_FIFO_IRQ_STATUS		REG32(SCP_AUDIO_BASE + 0x10)
-/* Audio/voice serial interface */
-#define SCP_RXIF_CFG0			REG32(SCP_AUDIO_BASE + 0x14)
-#define   RXIF_CFG0_RESET_VAL		0x2A130001
-#define   RXIF_AFE_ON			(1 << 0)
-#define   RXIF_SCKINV			(1 << 1)
-#define   RXIF_RG_DL_2_IN_MODE(mode)	(((mode) & 0xf) << 8)
-#define   RXIF_RGDL2_AMIC_16K		(0x1 << 8)
-#define   RXIF_RGDL2_DMIC_16K		(0x2 << 8)
-#define   RXIF_RGDL2_DMIC_LP_16K	(0x3 << 8)
-#define   RXIF_RGDL2_AMIC_32K		(0x5 << 8)
-#define   RXIF_RGDL2_MASK		(0xf << 8)
-#define   RXIF_UP8X_RSP(p)		(((p) & 0x7) << 16)
-#define   RXIF_RG_RX_READEN		(1 << 19)
-#define   RXIF_MONO			(1 << 20)
-#define   RXIF_RG_CLK_A16P7K_EN(cnt)	(((cnt) & 0xff) << 24)
-#define SCP_RXIF_CFG1			REG32(SCP_AUDIO_BASE + 0x18)
-#define   RXIF_CFG1_RESET_VAL		0x33180014
-#define   RXIF_RG_SYNC_CNT_TBL(t)	((t) & 0x1ff)
-#define   RXIF_RG_SYNC_SEARCH_TBL(t)	(((t) & 0x1f) << 16)
-#define   RXIF_RG_SYNC_CHECK_ROUND(r)	(((r) & 0xf) << 24)
-#define   RXIF_RG_INSYNC_CHECK_ROUND(r)	(((r) & 0xf) << 28)
-#define SCP_RXIF_CFG2			REG32(SCP_AUDIO_BASE + 0x1C)
-#define   RXIF_SYNC_WORD(w)		((w) & 0xffff)
-#define SCP_RXIF_OUT			REG32(SCP_AUDIO_BASE + 0x20)
-#define SCP_RXIF_STATUS			REG32(SCP_AUDIO_BASE + 0x24)
-#define SCP_RXIF_IRQ_EN			REG32(SCP_AUDIO_BASE + 0x28)
-
-/* INTC control */
-#define SCP_INTC_BASE			(SCP_CFG_BASE + 0x2000)
-#define SCP_INTC_IRQ_STATUS		REG32(SCP_INTC_BASE)
-#define SCP_INTC_IRQ_ENABLE		REG32(SCP_INTC_BASE + 0x04)
-#define   IPC0_IRQ_EN			BIT(0)
-#define SCP_INTC_IRQ_OUTPUT		REG32(SCP_INTC_BASE + 0x08)
-#define SCP_INTC_IRQ_WAKEUP		REG32(SCP_INTC_BASE + 0x0C)
-#define SCP_INTC_NMI			REG32(SCP_INTC_BASE + 0x10)
-#define SCP_INTC_SPM_WAKEUP		REG32(SCP_INTC_BASE + 0x14)
-#define SCP_INTC_SPM_WAKEUP_MSB		REG32(SCP_INTC_BASE + 0x18)
-#define SCP_INTC_UART_RX_IRQ		REG32(SCP_INTC_BASE + 0x1C)
-#define SCP_INTC_IRQ_STATUS_MSB		REG32(SCP_INTC_BASE + 0x80)
-#define SCP_INTC_IRQ_ENABLE_MSB		REG32(SCP_INTC_BASE + 0x84)
-#define SCP_INTC_IRQ_OUTPUT_MSB		REG32(SCP_INTC_BASE + 0x88)
-#define SCP_INTC_IRQ_WAKEUP_MSB		REG32(SCP_INTC_BASE + 0x8C)
-
-/* Timer */
-#define NUM_TIMERS			6
-#define SCP_TIMER_BASE(n)		(SCP_CFG_BASE + 0x3000 + (0x10 * (n)))
-#define SCP_TIMER_EN(n)			REG32(SCP_TIMER_BASE(n))
-#define SCP_TIMER_RESET_VAL(n)		REG32(SCP_TIMER_BASE(n) + 0x04)
-#define SCP_TIMER_VAL(n)		REG32(SCP_TIMER_BASE(n) + 0x08)
-#define SCP_TIMER_IRQ_CTRL(n)		REG32(SCP_TIMER_BASE(n) + 0x0C)
-#define   TIMER_IRQ_ENABLE		BIT(0)
-#define   TIMER_IRQ_STATUS		BIT(4)
-#define   TIMER_IRQ_CLEAR		BIT(5)
-#define SCP_TIMER_CLK_SEL(n)		REG32(SCP_TIMER_BASE(n) + 0x40)
-#define   TIMER_CLK_32K			(0 << 4)
-#define   TIMER_CLK_26M			BIT(4)
-#define   TIMER_CLK_BCLK		(2 << 4)
-#define   TIMER_CLK_PCLK		(3 << 4)
-#define   TIMER_CLK_MASK		(3 << 4)
-/* OS timer */
-#define SCP_OSTIMER_BASE		(SCP_CFG_BASE + 0x3080)
-#define SCP_OSTIMER_CON			REG32(SCP_OSTIMER_BASE)
-#define SCP_OSTIMER_INIT_L		REG32(SCP_OSTIMER_BASE + 0x04)
-#define SCP_OSTIMER_INIT_H		REG32(SCP_OSTIMER_BASE + 0x08)
-#define SCP_OSTIMER_VAL_L		REG32(SCP_OSTIMER_BASE + 0x0C)
-#define SCP_OSTIMER_VAL_H		REG32(SCP_OSTIMER_BASE + 0x10)
-#define SCP_OSTIMER_TVAL		REG32(SCP_OSTIMER_BASE + 0x14)
-#define SCP_OSTIMER_IRQ_ACK		REG32(SCP_OSTIMER_BASE + 0x18)
-#define   OSTIMER_LATCH0_EN		BIT(5)
-#define   OSTIMER_LATCH1_EN		BIT(13)
-#define   OSTIMER_LATCH2_EN		BIT(21)
-#define SCP_OSTIMER_LATCH_CTRL		REG32(SCP_OSTIMER_BASE + 0x20)
-#define SCP_OSTIMER_LATCH0_L		REG32(SCP_OSTIMER_BASE + 0x24)
-#define SCP_OSTIMER_LATCH0_H		REG32(SCP_OSTIMER_BASE + 0x28)
-#define SCP_OSTIMER_LATCH1_L		REG32(SCP_OSTIMER_BASE + 0x2C)
-#define SCP_OSTIMER_LATCH1_H		REG32(SCP_OSTIMER_BASE + 0x30)
-#define SCP_OSTIMER_LATCH2_L		REG32(SCP_OSTIMER_BASE + 0x34)
-#define SCP_OSTIMER_LATCH2_H		REG32(SCP_OSTIMER_BASE + 0x38)
-
-/* Clock, PMIC wrapper, etc. */
-#define SCP_CLK_BASE			(SCP_CFG_BASE + 0x4000)
-#define SCP_CLK_SEL			REG32(SCP_CLK_BASE)
-#define   CLK_SEL_SYS_26M		0
-#define   CLK_SEL_32K			1
-#define   CLK_SEL_ULPOSC_2		2
-#define   CLK_SEL_ULPOSC_1		3
-
-#define SCP_CLK_EN			REG32(SCP_CLK_BASE + 0x04)
-#define   EN_CLK_SYS			BIT(0) /* System clock */
-#define   EN_CLK_HIGH			BIT(1) /* ULPOSC */
-#define   CG_CLK_HIGH			BIT(2)
-#define   EN_SYS_IRQ			BIT(16)
-#define   EN_HIGH_IRQ			BIT(17)
-#define SCP_CLK_SAFE_ACK		REG32(SCP_CLK_BASE + 0x08)
-#define SCP_CLK_ACK			REG32(SCP_CLK_BASE + 0x0C)
-#define SCP_CLK_IRQ_ACK			REG32(SCP_CLK_BASE + 0x10)
-/*
- * System clock counter value.
- * CLK_SYS_VAL[9:0] System clock counter initial/reset value.
- */
-#define SCP_CLK_SYS_VAL			REG32(SCP_CLK_BASE + 0x14)
-#define   CLK_SYS_VAL_MASK		0x3ff /* 10 bits */
-#define   CLK_SYS_VAL(n)		((n) & CLK_SYS_VAL_MASK)
-/*
- * ULPOSC clock counter value.
- * CLK_HIGH_VAL[9:0] ULPOSC clock counter initial/reset value.
- */
-#define SCP_CLK_HIGH_VAL		REG32(SCP_CLK_BASE + 0x18)
-#define   CLK_HIGH_VAL_MASK		0x3ff /* 10 bits */
-#define   CLK_HIGH_VAL(n)		((n) & CLK_HIGH_VAL_MASK)
-#define SCP_CLK_SLOW_SEL		REG32(SCP_CLK_BASE + 0x1C)
-#define   CKSW_SEL_SLOW_MASK		0x3
-#define   CKSW_SEL_SLOW_DIV_MASK	0x30
-#define   CKSW_SEL_SLOW_SYS_CLK		0
-#define   CKSW_SEL_SLOW_32K_CLK		1
-#define   CKSW_SEL_SLOW_ULPOSC2_CLK	2
-#define   CKSW_SEL_SLOW_ULPOSC1_CLK	3
-/*
- * Sleep mode control.
- * VREQ_COUNT[7:1] Number of cycles to wait when requesting PMIC to raise the
- *     voltage after returning from  sleep mode.
- */
-#define SCP_CLK_SLEEP_CTRL		REG32(SCP_CLK_BASE + 0x20)
-#define   EN_SLEEP_CTRL			BIT(0)
-#define   VREQ_COUNTER_MASK		0xfe
-#define   VREQ_COUNTER_VAL(v)		(((v) << 1) & VREQ_COUNTER_MASK)
-#define   SPM_SLEEP_MODE		BIT(8)
-#define   SPM_SLEEP_MODE_CLK_AO		BIT(9)
-#define SCP_CLK_DIV_SEL			REG32(SCP_CLK_BASE + 0x24)
-#define   CLK_DIV1			0
-#define   CLK_DIV2			1
-#define   CLK_DIV4			2
-#define   CLK_DIV8			3
-#define SCP_CLK_DEBUG			REG32(SCP_CLK_BASE + 0x28)
-#define SCP_CLK_SRAM_POWERDOWN		REG32(SCP_CLK_BASE + 0x2C)
-#define SCP_CLK_GATE			REG32(SCP_CLK_BASE + 0x30)
-#define   CG_TIMER_M			BIT(0)
-#define   CG_TIMER_B			BIT(1)
-#define   CG_MAD_M			BIT(2)
-#define   CG_I2C_M			BIT(3)
-#define   CG_I2C_B			BIT(4)
-#define   CG_GPIO_M			BIT(5)
-#define   CG_AP2P_M			BIT(6)
-#define   CG_UART_M			BIT(7)
-#define   CG_UART_B			BIT(8)
-#define   CG_UART_RSTN			BIT(9)
-#define   CG_UART1_M			BIT(10)
-#define   CG_UART1_B			BIT(11)
-#define   CG_UART1_RSTN			BIT(12)
-#define   CG_SPI0			BIT(13)
-#define   CG_SPI1			BIT(14)
-#define   CG_SPI2			BIT(15)
-#define   CG_DMA_CH0			BIT(16)
-#define   CG_DMA_CH1			BIT(17)
-#define   CG_DMA_CH2			BIT(18)
-#define   CG_DMA_CH3			BIT(19)
-#define   CG_TWAM			BIT(20)
-#define   CG_CACHE_I_CTRL		BIT(21)
-#define   CG_CACHE_D_CTRL		BIT(22)
-#define SCP_PMICW_CTRL			REG32(SCP_CLK_BASE + 0x34)
-#define   PMICW_SLEEP_REQ		BIT(0)
-#define   PMICW_SLEEP_ACK		BIT(4)
-#define   PMICW_CLK_MUX			BIT(8)
-#define   PMICW_DCM			BIT(9)
-#define SCP_SLEEP_WAKE_DEBUG		REG32(SCP_CLK_BASE + 0x38)
-#define SCP_DCM_EN			REG32(SCP_CLK_BASE + 0x3C)
-#define SCP_WAKE_CKSW			REG32(SCP_CLK_BASE + 0x40)
-#define   WAKE_CKSW_SEL_NORMAL_MASK	0x3
-#define   WAKE_CKSW_SEL_SLOW_MASK	0x30
-#define   WAKE_CKSW_SEL_SLOW_DEFAULT	0x10
-#define SCP_CLK_UART			REG32(SCP_CLK_BASE + 0x44)
-#define   CLK_UART_SEL_MASK		0x3
-#define   CLK_UART_SEL_26M		0x0
-#define   CLK_UART_SEL_32K		0x1
-/* This is named ulposc_div_to_26m in datasheet */
-#define   CLK_UART_SEL_ULPOSC1_DIV10	0x2
-#define   CLK_UART1_SEL_MASK		(0x3 << 16)
-#define   CLK_UART1_SEL_26M		(0x0 << 16)
-#define   CLK_UART1_SEL_32K		(0x1 << 16)
-/* This is named ulposc_div_to_26m in datasheet */
-#define   CLK_UART1_SEL_ULPOSC1_DIV10	(0x2 << 16)
-#define SCP_CLK_BCLK			REG32(SCP_CLK_BASE + 0x48)
-#define   CLK_BCLK_SEL_MASK		0x3
-#define   CLK_BCLK_SEL_SYS_DIV8		0x0
-#define   CLK_BCLK_SEL_32K		0x1
-#define   CLK_BCLK_SEL_ULPOSC1_DIV8	0x2
-#define SCP_CLK_SPI_BCK			REG32(SCP_CLK_BASE + 0x4C)
-#define SCP_CLK_DIV_CNT			REG32(SCP_CLK_BASE + 0x50)
-#define SCP_CPU_VREQ			REG32(SCP_CLK_BASE + 0x54)
-#define   CPU_VREQ_HW_MODE		0x10001
-#define SCP_CLK_CLEAR			REG32(SCP_CLK_BASE + 0x58)
-#define SCP_CLK_HIGH_CORE		REG32(SCP_CLK_BASE + 0x5C)
-#define   CLK_HIGH_CORE_CG		(1 << 1)
-#define SCP_SLEEP_IRQ2			REG32(SCP_CLK_BASE + 0x64)
-#define SCP_CLK_ON_CTRL			REG32(SCP_CLK_BASE + 0x6C)
-#define   HIGH_AO			BIT(0)
-#define   HIGH_CG_AO			BIT(2)
-#define   HIGH_CORE_AO			BIT(4)
-#define   HIGH_CORE_DIS_SUB		BIT(5)
-#define   HIGH_CORE_CG_AO		BIT(6)
-#define   HIGH_FINAL_VAL_MASK		0x1f00
-#define   HIGH_FINAL_VAL_DEFAULT	0x300
-#define SCP_CLK_L1_SRAM_PD		REG32(SCP_CLK_BASE + 0x80)
-#define SCP_CLK_TCM_TAIL_SRAM_PD	REG32(SCP_CLK_BASE + 0x94)
-#define SCP_CLK_SLEEP			REG32(SCP_CLK_BASE + 0xA0)
-#define   SLOW_WAKE_DISABLE		1
-#define SCP_FAST_WAKE_CNT_END		REG32(SCP_CLK_BASE + 0xA4)
-#define   FAST_WAKE_CNT_END_MASK	0xfff
-#define   FAST_WAKE_CNT_END_DEFAULT	0x18
-#define   MEM_CK_CS_ISO_CNT_END_MASK	0x7f0000
-
-/* Peripherals */
-#define SCP_I2C0_BASE			(SCP_CFG_BASE + 0x5000)
-#define SCP_I2C1_BASE			(SCP_CFG_BASE + 0x6000)
-#define SCP_I2C2_BASE			(SCP_CFG_BASE + 0x7000)
-
-#define SCP_GPIO_BASE			(SCP_CFG_BASE + 0x8000)
-#define SCP_UART0_BASE			(SCP_CFG_BASE + 0x9000)
-#define SCP_UART1_BASE			(SCP_CFG_BASE + 0xE000)
-#define SCP_UART_COUNT			2
-
-/* External GPIO interrupt */
-#define SCP_EINT_BASE			(SCP_CFG_BASE + 0xA000)
-#define SCP_EINT_STATUS			REG32_ADDR(SCP_EINT_BASE)
-#define SCP_EINT_ACK			REG32_ADDR(SCP_EINT_BASE + 0x040)
-#define SCP_EINT_MASK_GET		REG32_ADDR(SCP_EINT_BASE + 0x080)
-#define SCP_EINT_MASK_SET		REG32_ADDR(SCP_EINT_BASE + 0x0C0)
-#define SCP_EINT_MASK_CLR		REG32_ADDR(SCP_EINT_BASE + 0x100)
-#define SCP_EINT_SENS_GET		REG32_ADDR(SCP_EINT_BASE + 0x140)
-#define SCP_EINT_SENS_SET		REG32_ADDR(SCP_EINT_BASE + 0x180)
-#define SCP_EINT_SENS_CLR		REG32_ADDR(SCP_EINT_BASE + 0x1C0)
-#define SCP_EINT_SOFT_GET		REG32_ADDR(SCP_EINT_BASE + 0x200)
-#define SCP_EINT_SOFT_SET		REG32_ADDR(SCP_EINT_BASE + 0x240)
-#define SCP_EINT_SOFT_CLR		REG32_ADDR(SCP_EINT_BASE + 0x280)
-#define SCP_EINT_POLARITY_GET		REG32_ADDR(SCP_EINT_BASE + 0x300)
-#define SCP_EINT_POLARITY_SET		REG32_ADDR(SCP_EINT_BASE + 0x340)
-#define SCP_EINT_POLARITY_CLR		REG32_ADDR(SCP_EINT_BASE + 0x380)
-#define SCP_EINT_D0_EN			REG32_ADDR(SCP_EINT_BASE + 0x400)
-#define SCP_EINT_D1_EN			REG32_ADDR(SCP_EINT_BASE + 0x420)
-#define SCP_EINT_DBNC_GET		REG32_ADDR(SCP_EINT_BASE + 0x500)
-#define SCP_EINT_DBNC_SET		REG32_ADDR(SCP_EINT_BASE + 0x600)
-#define SCP_EINT_DBNC_CLR		REG32_ADDR(SCP_EINT_BASE + 0x700)
-
-#define SCP_PMICWP2P_BASE		(SCP_CFG_BASE + 0xB000)
-#define   PMICW_WACS_CMD		REG32(SCP_PMICWP2P_BASE + 0x200)
-#define   PMICW_WACS_RDATA		REG32(SCP_PMICWP2P_BASE + 0x204)
-#define   PMICW_WACS_VLDCLR		REG32(SCP_PMICWP2P_BASE + 0x208)
-#define SCP_SPMP2P_BASE			(SCP_CFG_BASE + 0xC000)
-#define SCP_DMA_BASE			(SCP_CFG_BASE + 0xD000)
-#define   DMA_ACKINT_CHX		REG32(SCP_DMA_BASE + 0x20)
-#define SCP_SPI0_BASE			(SCP_CFG_BASE + 0xF000)
-#define SCP_SPI1_BASE			(SCP_CFG_BASE + 0x10000)
-#define SCP_SPI2_BASE			(SCP_CFG_BASE + 0x11000)
-
-#define CACHE_ICACHE 0
-#define CACHE_DCACHE 1
-#define CACHE_COUNT 2
-#define SCP_CACHE_BASE			(SCP_CFG_BASE + 0x14000)
-#define SCP_CACHE_SEL(x)		(SCP_CACHE_BASE + (x)*0x3000)
-#define SCP_CACHE_CON(x)		REG32(SCP_CACHE_SEL(x))
-#define SCP_CACHE_CON_MCEN		BIT(0)
-#define SCP_CACHE_CON_CNTEN0		BIT(2)
-#define SCP_CACHE_CON_CNTEN1		BIT(3)
-#define SCP_CACHE_CON_CACHESIZE_SHIFT	8
-#define SCP_CACHE_CON_CACHESIZE_MASK	(0x3 << SCP_CACHE_CON_CACHESIZE_SHIFT)
-#define SCP_CACHE_CON_CACHESIZE_0KB	(0x0 << SCP_CACHE_CON_CACHESIZE_SHIFT)
-#define SCP_CACHE_CON_CACHESIZE_8KB	(0x1 << SCP_CACHE_CON_CACHESIZE_SHIFT)
-#define SCP_CACHE_CON_CACHESIZE_16KB	(0x2 << SCP_CACHE_CON_CACHESIZE_SHIFT)
-#define SCP_CACHE_CON_CACHESIZE_32KB	(0x3 << SCP_CACHE_CON_CACHESIZE_SHIFT)
-#define SCP_CACHE_CON_WAYEN		BIT(10)
-
-#define SCP_CACHE_OP(x)			REG32(SCP_CACHE_SEL(x) + 0x04)
-#define SCP_CACHE_OP_EN			BIT(0)
-#define SCP_CACHE_OP_OP_SHIFT		1
-#define SCP_CACHE_OP_OP_MASK		(0xf << SCP_CACHE_OP_OP_SHIFT)
-
-#define   OP_INVALIDATE_ALL_LINES		(0x1 << SCP_CACHE_OP_OP_SHIFT)
-#define   OP_INVALIDATE_ONE_LINE_BY_ADDRESS	(0x2 << SCP_CACHE_OP_OP_SHIFT)
-#define   OP_INVALIDATE_ONE_LINE_BY_SET_WAY	(0x4 << SCP_CACHE_OP_OP_SHIFT)
-#define   OP_CACHE_FLUSH_ALL_LINES		(0x9 << SCP_CACHE_OP_OP_SHIFT)
-#define   OP_CACHE_FLUSH_ONE_LINE_BY_ADDRESS	(0xa << SCP_CACHE_OP_OP_SHIFT)
-#define   OP_CACHE_FLUSH_ONE_LINE_BY_SET_WAY	(0xc << SCP_CACHE_OP_OP_SHIFT)
-
-#define SCP_CACHE_OP_TADDR_SHIFT	5
-#define SCP_CACHE_OP_TADDR_MASK		(0x7ffffff << SCP_CACHE_OP_TADDR_SHIFT)
-#define SCP_CACHE_LINE_SIZE		BIT(SCP_CACHE_OP_TADDR_SHIFT)
-
-/* Cache statistics */
-#define SCP_CACHE_HCNT0L(x)		REG32(SCP_CACHE_SEL(x) + 0x08)
-#define SCP_CACHE_HCNT0U(x)		REG32(SCP_CACHE_SEL(x) + 0x0c)
-#define SCP_CACHE_CCNT0L(x)		REG32(SCP_CACHE_SEL(x) + 0x10)
-#define SCP_CACHE_CCNT0U(x)		REG32(SCP_CACHE_SEL(x) + 0x14)
-#define SCP_CACHE_HCNT1L(x)		REG32(SCP_CACHE_SEL(x) + 0x18)
-#define SCP_CACHE_HCNT1U(x)		REG32(SCP_CACHE_SEL(x) + 0x1c)
-#define SCP_CACHE_CCNT1L(x)		REG32(SCP_CACHE_SEL(x) + 0x20)
-#define SCP_CACHE_CCNT1U(x)		REG32(SCP_CACHE_SEL(x) + 0x24)
-
-#define SCP_CACHE_REGION_EN(x)		REG32(SCP_CACHE_SEL(x) + 0x2c)
-
-#define SCP_CACHE_ENTRY_BASE(x)		(SCP_CACHE_SEL(x) + 0x2000)
-#define SCP_CACHE_ENTRY(x, reg)		REG32(SCP_CACHE_ENTRY_BASE(x) + (reg)*4)
-#define SCP_CACHE_END_ENTRY_BASE(x)	(SCP_CACHE_SEL(x) + 0x2040)
-#define SCP_CACHE_END_ENTRY(x, reg)	REG32(SCP_CACHE_END_ENTRY_BASE(x) + \
-						(reg)*4)
-#define SCP_CACHE_ENTRY_C		BIT(8)
-#define SCP_CACHE_ENTRY_BASEADDR_MASK	(0xfffff << 12)
-
-/* ARMV7 regs */
-#define ARM_SCB_SCR			REG32(0xE000ED10)
-#define   SCR_DEEPSLEEP			BIT(2)
-
-/* AP regs */
-#define AP_BASE				0xA0000000
-#define TOPCK_BASE			AP_BASE /* Top clock */
-#define SCP_UART2_BASE			(AP_BASE + 0x01002000) /* AP UART0 */
-
-/* CLK_CFG_5 regs */
-#define AP_CLK_CFG_5		REG32(TOPCK_BASE + 0x0090)
-#define   PWRAP_ULPOSC_MASK	(0x3000000)
-#define   CLK26M			(0 << 24)
-#define   OSC_D16			(1 << 24)
-#define   OSC_D4			(2 << 24)
-#define   OSC_D8			(3 << 24)
-#define AP_CLK_CFG_5_CLR	REG32(TOPCK_BASE + 0x0098)
-#define   PWRAP_ULPOSC_CG	BIT(31)
-
-/* OSC meter */
-#define AP_CLK_MISC_CFG_0		REG32(TOPCK_BASE + 0x0104)
-#define   MISC_METER_DIVISOR_MASK	0xff000000
-#define   MISC_METER_DIV_1		0
-#define AP_CLK_DBG_CFG			REG32(TOPCK_BASE + 0x010C)
-#define   DBG_MODE_MASK			3
-#define   DBG_MODE_SET_CLOCK            0
-#define   DBG_BIST_SOURCE_MASK		(0x3f << 16)
-#define   DBG_BIST_SOURCE_ULPOSC1	(0x26 << 16)
-#define   DBG_BIST_SOURCE_ULPOSC2	(0x25 << 16)
-#define AP_SCP_CFG_0			REG32(TOPCK_BASE + 0x0220)
-#define   CFG_FREQ_METER_RUN		(1 << 4)
-#define   CFG_FREQ_METER_ENABLE		(1 << 12)
-#define AP_SCP_CFG_1			REG32(TOPCK_BASE + 0x0224)
-#define   CFG_FREQ_COUNTER(CFG1)	((CFG1) & 0xFFFF)
-
-/* GPIO */
-#define AP_GPIO_BASE			(AP_BASE + 0x00005000)
-/*
- * AP_GPIO_DIR
- * GPIO input/out direction, 1 bit per pin.
- * 0:input 1:output
- */
-#define AP_GPIO_DIR(n)			REG32(AP_GPIO_BASE + ((n) << 4))
-/*
- * AP_GPIO_DOUT, n in [0..5]
- * GPIO output level, 1 bit per pin
- * 0:low 1:high
- */
-#define AP_GPIO_DOUT(n)			REG32(AP_GPIO_BASE + 0x100 + ((n) << 4))
-/*
- * AP_GPIO_DIN, n in [0..5]
- * GPIO input level, 1 bit per pin
- * 0:low 1:high
- */
-#define AP_GPIO_DIN(n)			REG32(AP_GPIO_BASE + 0x200 + ((n) << 4))
-/*
- * AP_GPIO_MODE, n in [0..22]
- * Pin mode selection, 4 bit per pin
- * bit3   - write enable, set to 1 for hw to fetch bit2,1,0.
- * bit2-0 - mode 0 ~ 7
- */
-#define AP_GPIO_MODE(n)			REG32(AP_GPIO_BASE + 0x300 + ((n) << 4))
-#define AP_GPIO_TRAP			REG32(AP_GPIO_BASE + 0x6B0)
-#define AP_GPIO_UNIMPLEMENTED		REG32(AP_GPIO_BASE + 0x6C0)
-#define AP_GPIO_DBG			REG32(AP_GPIO_BASE + 0x6D0)
-#define AP_GPIO_BANK			REG32(AP_GPIO_BASE + 0x6E0)
-/* AP_GPIO_SEC, n in [0..5] */
-#define AP_GPIO_SEC(n)			REG32(AP_GPIO_BASE + 0xF00 + ((n) << 4))
-
-/*
- * PLL ULPOSC
- * ULPOSC1:  AP_ULPOSC_CON[0] AP_ULPOSC_CON[1]
- * ULPOSC2:  AP_ULPOSC_CON[2] AP_ULPOSC_CON[3]
- * osc: 0 for ULPOSC1, 1 for ULPSOC2.
- */
-#define AP_ULPOSC_BASE0			(AP_BASE + 0xC700)
-#define AP_ULPOSC_BASE1			(AP_BASE + 0xC704)
-#define AP_ULPOSC_CON02(osc)		REG32(AP_ULPOSC_BASE0 + (osc) * 0x8)
-#define AP_ULPOSC_CON13(osc)		REG32(AP_ULPOSC_BASE1 + (osc) * 0x8)
-/*
- * AP_ULPOSC_CON[0,2]
- * bit0-5:   calibration
- * bit6-12:  I-band
- * bit13-16: F-band
- * bit17-22: div
- * bit23:    CP_EN
- * bit24-31: reserved
- */
-#define OSC_CALI_MSK			(0x3f << 0)
-#define OSC_CALI_BITS			6
-#define OSC_IBAND_MASK			(0x7f << 6)
-#define OSC_FBAND_MASK			(0x0f << 13)
-#define OSC_DIV_MASK			(0x1f << 17)
-#define OSC_DIV_BITS			5
-#define OSC_CP_EN			BIT(23)
-#define OSC_RESERVED_MASK		(0xff << 24)
-/* AP_ULPOSC_CON[1,3] */
-#define OSC_MOD_MASK			(0x03 << 0)
-#define OSC_DIV2_EN			BIT(2)
-
-#define UNIMPLEMENTED_GPIO_BANK 0
-
-#ifndef __ASSEMBLER__
-
-/*
- * Cortex-M4 mod
- * Available power saving features:
- * 1. FPU freeze - freeze FPU operand when FPU is not used
- * 2. LSU gating - gate LSU clock when not LSU operation
- * 3. Trace clk disable - gate trace clock
- * 4. DCM for CPU stall - gate CPU clock when CPU stall
- */
-#define CM4_MODIFICATION		REG32(0xE00FE000)
-#define CM4_DCM_FEATURE			REG32(0xE00FE004)
-/* UART, 16550 compatible */
-#define SCP_UART_BASE(n)		CONCAT3(SCP_UART, n, _BASE)
-#define UART_REG(n, offset)		REG32_ADDR(SCP_UART_BASE(n))[offset]
-#define UART_IRQ(n)			CONCAT2(SCP_IRQ_UART, n)
-#define UART_RX_IRQ(n)			CONCAT3(SCP_IRQ_UART, n, _RX)
-
-/* Watchdog */
-#define SCP_WDT_BASE			(SCP_CFG_BASE + 0x84)
-#define SCP_WDT_REG(offset)		REG32(SCP_WDT_BASE + offset)
-#define SCP_WDT_CFG			SCP_WDT_REG(0)
-#define   SCP_WDT_FREQ			33825
-#define   SCP_WDT_MAX_PERIOD		0xFFFFF /* 31 seconds */
-#define   SCP_WDT_PERIOD(ms)		(SCP_WDT_FREQ * (ms) / 1000)
-#define   SCP_WDT_ENABLE		BIT(31)
-#define SCP_WDT_RELOAD			SCP_WDT_REG(4)
-#define   SCP_WDT_RELOAD_VALUE		1
-
-#endif /* !__ASSEMBLER__ */
-#endif /* __CROS_EC_REGISTERS_H */
diff --git a/chip/mt_scp/rv32i_common/build.mk b/chip/mt_scp/rv32i_common/build.mk
new file mode 100644
index 0000000000..eff299f98d
--- /dev/null
+++ b/chip/mt_scp/rv32i_common/build.mk
@@ -0,0 +1,27 @@
+# -*- makefile -*-
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# SCP specific files build
+#
+
+CORE:=riscv-rv32i
+
+# Required chip modules
+chip-y+=rv32i_common/cache.o
+chip-y+=rv32i_common/gpio.o
+chip-y+=rv32i_common/intc.o
+chip-y+=rv32i_common/memmap.o
+chip-y+=rv32i_common/system.o
+chip-y+=rv32i_common/uart.o
+
+ifeq ($(CONFIG_IPI),y)
+$(out)/RW/chip/$(CHIP)/rv32i_common/ipi_table.o: $(out)/ipi_table_gen.inc
+endif
+
+# Optional chip modules
+chip-$(CONFIG_COMMON_TIMER)+=rv32i_common/hrtimer.o
+chip-$(CONFIG_IPI)+=rv32i_common/ipi.o rv32i_common/ipi_table.o
+chip-$(CONFIG_WATCHDOG)+=rv32i_common/watchdog.o
+chip-$(HAS_TASK_HOSTCMD)+=rv32i_common/hostcmd.o
diff --git a/chip/mt_scp/rv32i_common/cache.c b/chip/mt_scp/rv32i_common/cache.c
new file mode 100644
index 0000000000..b04f28ebae
--- /dev/null
+++ b/chip/mt_scp/rv32i_common/cache.c
@@ -0,0 +1,205 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cache.h"
+#include "console.h"
+#include "csr.h"
+
+extern struct mpu_entry mpu_entries[];
+
+void cache_init(void)
+{
+	int i;
+	uint32_t mpu_en = 0;
+
+	/* disable mpu */
+	clear_csr(CSR_MCTREN, CSR_MCTREN_MPU);
+
+	/* enable i$, d$ */
+	set_csr(CSR_MCTREN, CSR_MCTREN_ICACHE);
+	set_csr(CSR_MCTREN, CSR_MCTREN_DCACHE);
+
+	/* invalidate icache and dcache */
+	cache_invalidate_icache();
+	cache_invalidate_dcache();
+
+	/* set mpu entries
+	 *
+	 * The pragma is for force GCC unrolls the following loop.
+	 * See b/172886808
+	 */
+#pragma GCC unroll 16
+	for (i = 0; i < NR_MPU_ENTRIES; ++i) {
+		if (mpu_entries[i].end_addr - mpu_entries[i].start_addr) {
+			write_csr(CSR_MPU_L(i),
+				  mpu_entries[i].start_addr |
+					  mpu_entries[i].attribute);
+			write_csr(CSR_MPU_H(i), mpu_entries[i].end_addr);
+			mpu_en |= BIT(i);
+		}
+	}
+
+	/* enable mpu entries */
+	write_csr(CSR_MPU_ENTRY_EN, mpu_en);
+
+	/* enable mpu */
+	set_csr(CSR_MCTREN, CSR_MCTREN_MPU);
+
+	/* fence */
+	asm volatile("fence.i" ::: "memory");
+}
+
+#ifdef DEBUG
+/*
+ * I for I-cache
+ * D for D-cache
+ * C for control transfer instructions (branch, jump, ret, interrupt, ...)
+ */
+static enum { PMU_SELECT_I = 0, PMU_SELECT_D, PMU_SELECT_C } pmu_select;
+
+int command_enable_pmu(int argc, const char **argv)
+{
+	static const char *const selectors[] = {
+		[PMU_SELECT_I] = "I",
+		[PMU_SELECT_D] = "D",
+		[PMU_SELECT_C] = "C",
+	};
+	int i;
+
+	if (argc != 2)
+		return EC_ERROR_PARAM1;
+
+	for (i = 0; i < ARRAY_SIZE(selectors); ++i) {
+		if (strcasecmp(argv[1], selectors[i]) == 0) {
+			pmu_select = i;
+			break;
+		}
+	}
+	if (i >= ARRAY_SIZE(selectors))
+		return EC_ERROR_PARAM1;
+
+	ccprintf("select \"%s\"\n", selectors[pmu_select]);
+
+	/* disable all PMU */
+	clear_csr(CSR_PMU_MPMUCTR,
+		  CSR_PMU_MPMUCTR_C | CSR_PMU_MPMUCTR_I | CSR_PMU_MPMUCTR_H3 |
+			  CSR_PMU_MPMUCTR_H4 | CSR_PMU_MPMUCTR_H5);
+
+	/* reset cycle count */
+	write_csr(CSR_PMU_MCYCLE, 0);
+	write_csr(CSR_PMU_MCYCLEH, 0);
+	/* reset retired-instruction count */
+	write_csr(CSR_PMU_MINSTRET, 0);
+	write_csr(CSR_PMU_MINSTRETH, 0);
+	/* reset counter{3,4,5} */
+	write_csr(CSR_PMU_MHPMCOUNTER3, 0);
+	write_csr(CSR_PMU_MHPMCOUNTER3H, 0);
+	write_csr(CSR_PMU_MHPMCOUNTER4, 0);
+	write_csr(CSR_PMU_MHPMCOUNTER4H, 0);
+	write_csr(CSR_PMU_MHPMCOUNTER5, 0);
+	write_csr(CSR_PMU_MHPMCOUNTER5H, 0);
+
+	/* select different event IDs for counter{3,4,5} */
+	switch (pmu_select) {
+	case PMU_SELECT_I:
+		/* I-cache access count */
+		write_csr(CSR_PMU_MHPMEVENT3, 1);
+		/* I-cache miss count */
+		write_csr(CSR_PMU_MHPMEVENT4, 3);
+		/* noncacheable I-AXI access count */
+		write_csr(CSR_PMU_MHPMEVENT5, 5);
+		break;
+	case PMU_SELECT_D:
+		/* D-cache access count */
+		write_csr(CSR_PMU_MHPMEVENT3, 11);
+		/* D-cache miss count */
+		write_csr(CSR_PMU_MHPMEVENT4, 12);
+		/* noncacheable D-AXI access count */
+		write_csr(CSR_PMU_MHPMEVENT5, 14);
+		break;
+	case PMU_SELECT_C:
+		/* control transfer instruction count */
+		write_csr(CSR_PMU_MHPMEVENT3, 27);
+		/* control transfer miss-predict count */
+		write_csr(CSR_PMU_MHPMEVENT4, 28);
+		/* interrupt count */
+		write_csr(CSR_PMU_MHPMEVENT5, 29);
+		break;
+	}
+
+	cache_invalidate_icache();
+	cache_flush_dcache();
+
+	/* enable all PMU */
+	set_csr(CSR_PMU_MPMUCTR,
+		CSR_PMU_MPMUCTR_C | CSR_PMU_MPMUCTR_I | CSR_PMU_MPMUCTR_H3 |
+			CSR_PMU_MPMUCTR_H4 | CSR_PMU_MPMUCTR_H5);
+
+	return EC_SUCCESS;
+}
+DECLARE_SAFE_CONSOLE_COMMAND(enable_pmu, command_enable_pmu, "[I | D | C]",
+			     "Enable PMU");
+
+int command_disable_pmu(int argc, const char **argv)
+{
+	clear_csr(CSR_PMU_MPMUCTR,
+		  CSR_PMU_MPMUCTR_C | CSR_PMU_MPMUCTR_I | CSR_PMU_MPMUCTR_H3 |
+			  CSR_PMU_MPMUCTR_H4 | CSR_PMU_MPMUCTR_H5);
+	return EC_SUCCESS;
+}
+DECLARE_SAFE_CONSOLE_COMMAND(disable_pmu, command_disable_pmu, NULL,
+			     "Disable PMU");
+
+int command_show_pmu(int argc, const char **argv)
+{
+	uint64_t val3, val4, val5;
+	uint32_t p;
+
+	val3 = ((uint64_t)read_csr(CSR_PMU_MCYCLEH) << 32) |
+	       read_csr(CSR_PMU_MCYCLE);
+	ccprintf("cycles: %lld\n", val3);
+
+	val3 = ((uint64_t)read_csr(CSR_PMU_MINSTRETH) << 32) |
+	       read_csr(CSR_PMU_MINSTRET);
+	ccprintf("retired instructions: %lld\n", val3);
+
+	val3 = ((uint64_t)read_csr(CSR_PMU_MHPMCOUNTER3H) << 32) |
+	       read_csr(CSR_PMU_MHPMCOUNTER3);
+	val4 = ((uint64_t)read_csr(CSR_PMU_MHPMCOUNTER4H) << 32) |
+	       read_csr(CSR_PMU_MHPMCOUNTER4);
+	val5 = ((uint64_t)read_csr(CSR_PMU_MHPMCOUNTER5H) << 32) |
+	       read_csr(CSR_PMU_MHPMCOUNTER5);
+
+	if (val3)
+		p = val4 * 10000 / val3;
+	else
+		p = 0;
+
+	switch (pmu_select) {
+	case PMU_SELECT_I:
+		ccprintf("I-cache:\n");
+		ccprintf("  access: %lld\n", val3);
+		ccprintf("  miss: %lld (%d.%d%%)\n", val4, p / 100, p % 100);
+		ccprintf("non-cacheable I: %lld\n", val5);
+		break;
+	case PMU_SELECT_D:
+		ccprintf("D-cache:\n");
+		ccprintf("  access: %lld\n", val3);
+		ccprintf("  miss: %lld (%d.%d%%)\n", val4, p / 100, p % 100);
+		ccprintf("non-cacheable D: %lld\n", val5);
+		break;
+	case PMU_SELECT_C:
+		ccprintf("control transfer instruction:\n");
+		ccprintf("  total: %lld\n", val3);
+		ccprintf("  miss-predict: %lld (%d.%d%%)\n", val4, p / 100,
+			 p % 100);
+		ccprintf("interrupts: %lld\n", val5);
+		break;
+	}
+
+	return EC_SUCCESS;
+}
+DECLARE_SAFE_CONSOLE_COMMAND(show_pmu, command_show_pmu, NULL, "Show PMU");
+#endif
diff --git a/chip/mt_scp/rv32i_common/cache.h b/chip/mt_scp/rv32i_common/cache.h
new file mode 100644
index 0000000000..15572962ac
--- /dev/null
+++ b/chip/mt_scp/rv32i_common/cache.h
@@ -0,0 +1,140 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_CACHE_H
+#define __CROS_EC_CACHE_H
+
+#include "common.h"
+#include "csr.h"
+#include "stdint.h"
+#include "util.h"
+
+/* rs1 0~31 register X0~X31 */
+#define COP(rs1) (((rs1) << 15) | 0x400f)
+
+#define COP_OP_BARRIER_ICACHE 0x0
+#define COP_OP_INVALIDATE_ICACHE 0x8
+#define COP_OP_INVALIDATE_ICACHE_ADDR 0x9
+
+#define COP_OP_BARRIER_DCACHE 0x10
+#define COP_OP_WRITEBACK_DCACHE 0x14
+#define COP_OP_WRITEBACK_DCACHE_ADDR 0x15
+#define COP_OP_INVALIDATE_DCACHE 0x18
+#define COP_OP_INVALIDATE_DCACHE_ADDR 0x19
+/* FLUSH = WRITEBACK + INVALIDATE */
+#define COP_OP_FLUSH_DCACHE 0x1C
+#define COP_OP_FLUSH_DCACHE_ADDR 0x1D
+
+static inline void cache_op_all(uint32_t op)
+{
+	register int t0 asm("t0") = op;
+	asm volatile(".word " STRINGIFY(COP(5))::"r"(t0));
+}
+
+static inline int cache_op_addr(uintptr_t addr, uint32_t length, uint32_t op)
+{
+	size_t offset;
+	register int t0 asm("t0");
+
+	/* NOTE: cache operations must use 32 byte aligned address */
+	if (addr & GENMASK(3, 0))
+		return EC_ERROR_INVAL;
+
+	for (offset = 0; offset < length; offset += 4) {
+		t0 = addr + offset + op;
+		asm volatile(".word " STRINGIFY(COP(5))::"r"(t0));
+	}
+
+	return EC_SUCCESS;
+}
+
+/* memory barrier of I$ */
+static inline void cache_barrier_icache(void)
+{
+	cache_op_all(COP_OP_BARRIER_ICACHE);
+}
+
+/* invalidate all I$ */
+static inline void cache_invalidate_icache(void)
+{
+	cache_op_all(COP_OP_INVALIDATE_ICACHE);
+}
+
+/* invalidate a range of I$ */
+static inline int cache_invalidate_icache_range(uintptr_t addr, uint32_t length)
+{
+	return cache_op_addr(addr, length, COP_OP_INVALIDATE_ICACHE_ADDR);
+}
+
+/* memory barrier of D$ */
+static inline void cache_barrier_dcache(void)
+{
+	cache_op_all(COP_OP_BARRIER_DCACHE);
+}
+
+/* writeback all D$ */
+static inline void cache_writeback_dcache(void)
+{
+	cache_op_all(COP_OP_WRITEBACK_DCACHE);
+	cache_barrier_icache();
+	cache_barrier_dcache();
+}
+
+/* writeback a range of D$ */
+static inline int cache_writeback_dcache_range(uintptr_t addr, uint32_t length)
+{
+	int ret = cache_op_addr(addr, length, COP_OP_WRITEBACK_DCACHE_ADDR);
+	cache_barrier_icache();
+	cache_barrier_dcache();
+	return ret;
+}
+
+/* invalidate all D$ */
+static inline void cache_invalidate_dcache(void)
+{
+	cache_op_all(COP_OP_INVALIDATE_DCACHE);
+}
+
+/* invalidate a range of D$ */
+static inline int cache_invalidate_dcache_range(uintptr_t addr, uint32_t length)
+{
+	return cache_op_addr(addr, length, COP_OP_INVALIDATE_DCACHE_ADDR);
+}
+
+/* writeback and invalidate all D$ */
+static inline void cache_flush_dcache(void)
+{
+	cache_op_all(COP_OP_FLUSH_DCACHE);
+	cache_barrier_icache();
+	cache_barrier_dcache();
+}
+
+/* writeback and invalidate a range of D$ */
+static inline int cache_flush_dcache_range(uintptr_t addr, uint32_t length)
+{
+	int ret = cache_op_addr(addr, length, COP_OP_FLUSH_DCACHE_ADDR);
+	cache_barrier_icache();
+	cache_barrier_dcache();
+	return ret;
+}
+
+struct mpu_entry {
+	/* 1k alignment and the address is inclusive */
+	uintptr_t start_addr;
+	/* 1k alignment in 4GB boundary and non-inclusive */
+	uintptr_t end_addr;
+	/* MPU_ATTR */
+	uint32_t attribute;
+};
+
+void cache_init(void);
+
+#ifdef DEBUG
+int command_enable_pmu(int argc, const char **argv);
+int command_disable_pmu(int argc, const char **argv);
+int command_show_pmu(int argc, const char **argv);
+#endif
+
+#endif /* #ifndef __CROS_EC_CACHE_H */
diff --git a/chip/mt_scp/rv32i_common/config_chip.h b/chip/mt_scp/rv32i_common/config_chip.h
new file mode 100644
index 0000000000..775dd02461
--- /dev/null
+++ b/chip/mt_scp/rv32i_common/config_chip.h
@@ -0,0 +1,57 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_CONFIG_CHIP_H
+#define __CROS_EC_CONFIG_CHIP_H
+
+#include "core/riscv-rv32i/config_core.h"
+
+/* Interval between HOOK_TICK notifications */
+#define HOOK_TICK_INTERVAL_MS 500
+#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC)
+
+/* RW only, no flash */
+#undef CONFIG_FW_INCLUDE_RO
+#define CONFIG_RO_MEM_OFF 0
+#define CONFIG_RO_SIZE 0
+#define CONFIG_RW_MEM_OFF 0
+#define CONFIG_RW_SIZE 0x40000 /* 256KB */
+#define CONFIG_EC_WRITABLE_STORAGE_OFF 0
+#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
+#define CONFIG_RO_STORAGE_OFF 0
+#define CONFIG_RW_STORAGE_OFF 0
+#define CONFIG_PROGRAM_MEMORY_BASE 0
+#define CONFIG_PROGRAM_MEMORY_BASE_LOAD 0x10500000
+#define CONFIG_MAPPED_STORAGE_BASE 0
+
+/* Unsupported features/commands */
+#undef CONFIG_CMD_FLASHINFO
+#undef CONFIG_CMD_POWER_AP
+#undef CONFIG_FLASH_CROS
+#undef CONFIG_FLASH_PHYSICAL
+#undef CONFIG_FMAP
+#undef CONFIG_HIBERNATE
+#undef CONFIG_LID_SWITCH
+
+/* Task stack size */
+#define CONFIG_STACK_SIZE 1024
+#define IDLE_TASK_STACK_SIZE 640
+#define SMALLER_TASK_STACK_SIZE 384
+#define TASK_STACK_SIZE 488
+#define LARGER_TASK_STACK_SIZE 640
+#define VENTI_TASK_STACK_SIZE 768
+#define ULTRA_TASK_STACK_SIZE 1056
+#define TRENTA_TASK_STACK_SIZE 1184
+
+/* TODO: need to confirm, placeholder */
+#define GPIO_PIN(num) ((num) / 32), ((num) % 32)
+#define GPIO_PIN_MASK(p, m) .port = (p), .mask = (m)
+#undef CONFIG_TASK_PROFILING
+/* TODO: not yet supported */
+#undef CONFIG_MPU
+/* TODO: core/riscv-rv32i pollution */
+#define __ram_code
+
+#endif /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/chip/mt_scp/rv32i_common/csr.h b/chip/mt_scp/rv32i_common/csr.h
new file mode 100644
index 0000000000..88ea869cbd
--- /dev/null
+++ b/chip/mt_scp/rv32i_common/csr.h
@@ -0,0 +1,111 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Control and status register */
+
+/* TODO: move to core/riscv-rv32i? */
+
+#ifndef __CROS_EC_CSR_H
+#define __CROS_EC_CSR_H
+
+#include "common.h"
+
+static inline uint32_t read_csr(uint32_t reg)
+{
+	uint32_t val;
+
+	asm volatile("csrr %0, %1" : "=r"(val) : "i"(reg));
+	return val;
+}
+
+static inline void write_csr(uint32_t reg, uint32_t val)
+{
+	asm volatile("csrw %0, %1" ::"i"(reg), "r"(val));
+}
+
+static inline uint32_t set_csr(uint32_t reg, uint32_t bit)
+{
+	uint32_t val;
+
+	asm volatile("csrrs %0, %1, %2" : "=r"(val) : "i"(reg), "r"(bit));
+	return val;
+}
+
+static inline uint32_t clear_csr(uint32_t reg, uint32_t bit)
+{
+	uint32_t val;
+
+	asm volatile("csrrc %0, %1, %2" : "=r"(val) : "i"(reg), "r"(bit));
+	return val;
+}
+
+/* VIC */
+#define CSR_VIC_MICAUSE (0x5c0)
+#define CSR_VIC_MIEMS (0x5c2)
+#define CSR_VIC_MIPEND_G0 (0x5d0)
+#define CSR_VIC_MIMASK_G0 (0x5d8)
+#define CSR_VIC_MIWAKEUP_G0 (0x5e0)
+#define CSR_VIC_MILSEL_G0 (0x5e8)
+#define CSR_VIC_MIEMASK_G0 (0x5f0)
+
+/* centralized control enable */
+#define CSR_MCTREN (0x7c0)
+/* I$, D$, ITCM, DTCM, BTB, RAS, VIC, CG, mpu */
+#define CSR_MCTREN_ICACHE BIT(0)
+#define CSR_MCTREN_DCACHE BIT(1)
+#define CSR_MCTREN_ITCM BIT(2)
+#define CSR_MCTREN_DTCM BIT(3)
+#define CSR_MCTREN_BTB BIT(4)
+#define CSR_MCTREN_RAS BIT(5)
+#define CSR_MCTREN_VIC BIT(6)
+#define CSR_MCTREN_CG BIT(7)
+#define CSR_MCTREN_MPU BIT(8)
+
+/* MPU */
+#define CSR_MPU_ENTRY_EN (0x9c0)
+#define CSR_MPU_LITCM (0x9dc)
+#define CSR_MPU_LDTCM (0x9dd)
+#define CSR_MPU_HITCM (0x9de)
+#define CSR_MPU_HDTCM (0x9df)
+#define CSR_MPU_L(n) (0x9e0 + (n))
+#define CSR_MPU_H(n) (0x9f0 + (n))
+/* MPU attributes: set if permitted */
+/* Privilege, machine mode in RISC-V.  We don't use the flag because
+ * we don't separate user / machine mode in EC OS. */
+#define MPU_ATTR_P BIT(5)
+/* Readable */
+#define MPU_ATTR_R BIT(6)
+/* Writable */
+#define MPU_ATTR_W BIT(7)
+/* Cacheable */
+#define MPU_ATTR_C BIT(8)
+/* Bufferable */
+#define MPU_ATTR_B BIT(9)
+
+/* PMU */
+#define CSR_PMU_MPMUCTR (0xbc0)
+#define CSR_PMU_MPMUCTR_C BIT(0)
+#define CSR_PMU_MPMUCTR_I BIT(1)
+#define CSR_PMU_MPMUCTR_H3 BIT(2)
+#define CSR_PMU_MPMUCTR_H4 BIT(3)
+#define CSR_PMU_MPMUCTR_H5 BIT(4)
+
+#define CSR_PMU_MCYCLE (0xb00)
+#define CSR_PMU_MINSTRET (0xb02)
+#define CSR_PMU_MHPMCOUNTER3 (0xb03)
+#define CSR_PMU_MHPMCOUNTER4 (0xb04)
+#define CSR_PMU_MHPMCOUNTER5 (0xb05)
+
+#define CSR_PMU_MCYCLEH (0xb80)
+#define CSR_PMU_MINSTRETH (0xb82)
+#define CSR_PMU_MHPMCOUNTER3H (0xb83)
+#define CSR_PMU_MHPMCOUNTER4H (0xb84)
+#define CSR_PMU_MHPMCOUNTER5H (0xb85)
+
+#define CSR_PMU_MHPMEVENT3 (0x323)
+#define CSR_PMU_MHPMEVENT4 (0x324)
+#define CSR_PMU_MHPMEVENT5 (0x325)
+
+#endif /* __CROS_EC_CSR_H */
diff --git a/chip/mt_scp/rv32i_common/gpio.c b/chip/mt_scp/rv32i_common/gpio.c
new file mode 100644
index 0000000000..d56cff97fb
--- /dev/null
+++ b/chip/mt_scp/rv32i_common/gpio.c
@@ -0,0 +1,21 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* GPIO module */
+
+#include "gpio.h"
+
+void gpio_pre_init(void)
+{
+}
+
+test_mockable int gpio_get_level(enum gpio_signal signal)
+{
+	return 0;
+}
+
+void gpio_set_level(enum gpio_signal signal, int value)
+{
+}
diff --git a/chip/mt8192_scp/hostcmd.c b/chip/mt_scp/rv32i_common/hostcmd.c
similarity index 95%
rename from chip/mt8192_scp/hostcmd.c
rename to chip/mt_scp/rv32i_common/hostcmd.c
index 42a463ee56..fee1ce110a 100644
--- a/chip/mt8192_scp/hostcmd.c
+++ b/chip/mt_scp/rv32i_common/hostcmd.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -97,7 +97,8 @@ DECLARE_IPI(SCP_IPI_HOST_COMMAND, hostcmd_handler, 0);
 /*
  * Get protocol information
  */
-static enum ec_status hostcmd_get_protocol_info(struct host_cmd_handler_args *args)
+static enum ec_status
+hostcmd_get_protocol_info(struct host_cmd_handler_args *args)
 {
 	struct ec_response_get_protocol_info *r = args->response;
 
diff --git a/chip/mt8192_scp/hostcmd.h b/chip/mt_scp/rv32i_common/hostcmd.h
similarity index 79%
rename from chip/mt8192_scp/hostcmd.h
rename to chip/mt_scp/rv32i_common/hostcmd.h
index b93f1e725d..067a4c14ab 100644
--- a/chip/mt8192_scp/hostcmd.h
+++ b/chip/mt_scp/rv32i_common/hostcmd.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/mt_scp/rv32i_common/hrtimer.c b/chip/mt_scp/rv32i_common/hrtimer.c
new file mode 100644
index 0000000000..fff5fb6436
--- /dev/null
+++ b/chip/mt_scp/rv32i_common/hrtimer.c
@@ -0,0 +1,231 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * High-res hardware timer
+ *
+ * SCP hardware 32bit count down timer can be configured to source clock from
+ * 32KHz, 26MHz, BCLK or PCLK. This implementation selects BCLK (ULPOSC1/8) as a
+ * source, countdown mode and converts to micro second value matching common
+ * timer.
+ */
+
+#include "common.h"
+#include "hwtimer.h"
+#include "registers.h"
+#include "scp_timer.h"
+#include "task.h"
+
+#define TIMER_SYSTEM 5
+#define TIMER_EVENT 3
+#define TIMER_CLOCK_MHZ 32.5
+#define OVERFLOW_TICKS (TIMER_CLOCK_MHZ * 0x100000000 - 1)
+
+/* High 32-bit for system timer. */
+static uint8_t sys_high;
+/* High 32-bit for event timer. */
+static uint8_t event_high;
+
+void timer_enable(int n)
+{
+	/* cannot be changed when timer is enabled */
+	SCP_CORE0_TIMER_IRQ_CTRL(n) |= TIMER_IRQ_EN;
+	SCP_CORE0_TIMER_EN(n) |= TIMER_EN;
+}
+
+void timer_disable(int n)
+{
+	SCP_CORE0_TIMER_EN(n) &= ~TIMER_EN;
+	/* cannot be changed when timer is enabled */
+	SCP_CORE0_TIMER_IRQ_CTRL(n) &= ~TIMER_IRQ_EN;
+}
+
+uint32_t timer_read_raw_sr(void)
+{
+	return SCP_CORE0_TIMER_CUR_VAL(TIMER_SR);
+}
+
+static int timer_is_irq(int n)
+{
+	return SCP_CORE0_TIMER_IRQ_CTRL(n) & TIMER_IRQ_STATUS;
+}
+
+static void timer_ack_irq(int n)
+{
+	SCP_CORE0_TIMER_IRQ_CTRL(n) |= TIMER_IRQ_CLR;
+}
+
+static void timer_set_reset_value(int n, uint32_t reset_value)
+{
+	/* cannot be changed when timer is enabled */
+	SCP_CORE0_TIMER_RST_VAL(n) = reset_value;
+}
+
+static void timer_set_clock(int n, uint32_t clock_source)
+{
+	SCP_CORE0_TIMER_EN(n) = (SCP_CORE0_TIMER_EN(n) & ~TIMER_CLK_SRC_MASK) |
+				clock_source;
+}
+
+static void timer_reset(int n)
+{
+	timer_disable(n);
+	timer_ack_irq(n);
+	timer_set_reset_value(n, 0xffffffff);
+	timer_set_clock(n, TIMER_CLK_SRC_32K);
+}
+
+/* Convert hardware countdown timer to 64bit countup ticks. */
+static uint64_t timer_read_raw_system(void)
+{
+	uint32_t timer_ctrl = SCP_CORE0_TIMER_IRQ_CTRL(TIMER_SYSTEM);
+	uint32_t sys_high_adj = sys_high;
+
+	/*
+	 * If an IRQ is pending, but has not been serviced yet, adjust the
+	 * sys_high value.
+	 */
+	if (timer_ctrl & TIMER_IRQ_STATUS)
+		sys_high_adj = sys_high ? (sys_high - 1) :
+					  (TIMER_CLOCK_MHZ - 1);
+
+	return OVERFLOW_TICKS - (((uint64_t)sys_high_adj << 32) |
+				 SCP_CORE0_TIMER_CUR_VAL(TIMER_SYSTEM));
+}
+
+static uint64_t timer_read_raw_event(void)
+{
+	return OVERFLOW_TICKS - (((uint64_t)event_high << 32) |
+				 SCP_CORE0_TIMER_CUR_VAL(TIMER_EVENT));
+}
+
+static void timer_reload(int n, uint32_t value)
+{
+	timer_disable(n);
+	timer_set_reset_value(n, value);
+	timer_enable(n);
+}
+
+static int timer_reload_event_high(void)
+{
+	if (event_high) {
+		if (SCP_CORE0_TIMER_RST_VAL(TIMER_EVENT) == 0xffffffff)
+			timer_enable(TIMER_EVENT);
+		else
+			timer_reload(TIMER_EVENT, 0xffffffff);
+		event_high--;
+		return 1;
+	}
+
+	timer_disable(TIMER_EVENT);
+	return 0;
+}
+
+int __hw_clock_source_init(uint32_t start_t)
+{
+	int t;
+
+	/* enable clock gate */
+	SCP_SET_CLK_CG |= CG_TIMER_MCLK | CG_TIMER_BCLK;
+
+	/* reset all timer, select 32768Hz clock source */
+	for (t = 0; t < NUM_TIMERS; ++t)
+		timer_reset(t);
+
+	/* System timestamp timer */
+	timer_set_clock(TIMER_SYSTEM, TIMER_CLK_SRC_BCLK);
+	sys_high = TIMER_CLOCK_MHZ - 1;
+	timer_set_reset_value(TIMER_SYSTEM, 0xffffffff);
+	task_enable_irq(SCP_IRQ_TIMER(TIMER_SYSTEM));
+	timer_enable(TIMER_SYSTEM);
+
+	/* Event tick timer */
+	timer_set_clock(TIMER_EVENT, TIMER_CLK_SRC_BCLK);
+	task_enable_irq(SCP_IRQ_TIMER(TIMER_EVENT));
+
+	/* SR timer */
+	timer_set_clock(TIMER_SR, TIMER_CLK_SRC_26M);
+	task_disable_irq(SCP_IRQ_TIMER(TIMER_SR));
+
+	return SCP_IRQ_TIMER(TIMER_SYSTEM);
+}
+
+uint32_t __hw_clock_source_read(void)
+{
+	return timer_read_raw_system() / TIMER_CLOCK_MHZ;
+}
+
+uint32_t __hw_clock_event_get(void)
+{
+	return (timer_read_raw_event() + timer_read_raw_system()) /
+	       TIMER_CLOCK_MHZ;
+}
+
+void __hw_clock_event_clear(void)
+{
+	/* c1ea4, magic number for clear state */
+	timer_disable(TIMER_EVENT);
+	timer_set_reset_value(TIMER_EVENT, 0x0000c1ea4);
+	event_high = 0;
+}
+
+void __hw_clock_event_set(uint32_t deadline)
+{
+	uint64_t deadline_raw = (uint64_t)deadline * TIMER_CLOCK_MHZ;
+	uint64_t now_raw = timer_read_raw_system();
+	uint32_t event_deadline;
+
+	if (deadline_raw > now_raw) {
+		deadline_raw -= now_raw;
+		event_deadline = (uint32_t)deadline_raw;
+		event_high = deadline_raw >> 32;
+	} else {
+		event_deadline = 1;
+		event_high = 0;
+	}
+
+	if (event_deadline)
+		timer_reload(TIMER_EVENT, event_deadline);
+	else
+		timer_reload_event_high();
+}
+
+static void irq_group6_handler(void)
+{
+	extern volatile int ec_int;
+
+	switch (ec_int) {
+	case SCP_IRQ_TIMER(TIMER_EVENT):
+		if (timer_is_irq(TIMER_EVENT)) {
+			timer_ack_irq(TIMER_EVENT);
+
+			if (!timer_reload_event_high())
+				process_timers(0);
+
+			task_clear_pending_irq(ec_int);
+		}
+		break;
+	case SCP_IRQ_TIMER(TIMER_SYSTEM):
+		/* If this is a hardware irq, check overflow */
+		if (!in_soft_interrupt_context()) {
+			timer_ack_irq(TIMER_SYSTEM);
+
+			if (sys_high) {
+				--sys_high;
+				process_timers(0);
+			} else {
+				/* Overflow, reload system timer */
+				sys_high = TIMER_CLOCK_MHZ - 1;
+				process_timers(1);
+			}
+
+			task_clear_pending_irq(ec_int);
+		} else {
+			process_timers(0);
+		}
+		break;
+	}
+}
+DECLARE_IRQ(6, irq_group6_handler, 0);
diff --git a/chip/mt_scp/rv32i_common/intc.c b/chip/mt_scp/rv32i_common/intc.c
new file mode 100644
index 0000000000..641d0cf516
--- /dev/null
+++ b/chip/mt_scp/rv32i_common/intc.c
@@ -0,0 +1,425 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* INTC control module */
+
+#include "console.h"
+#include "csr.h"
+#include "intc.h"
+#include "registers.h"
+
+/*
+ * INTC_GRP_0 is reserved.  See swirq of syscall_handler() in
+ * core/riscv-rv32i/task.c for more details.
+ *
+ * Lower group has higher priority.  Group 0 has highest priority.
+ */
+enum INTC_GROUP {
+	INTC_GRP_0 = 0x0,
+	INTC_GRP_1,
+	INTC_GRP_2,
+	INTC_GRP_3,
+	INTC_GRP_4,
+	INTC_GRP_5,
+	INTC_GRP_6,
+	INTC_GRP_7,
+	INTC_GRP_8,
+	INTC_GRP_9,
+	INTC_GRP_10,
+	INTC_GRP_11,
+	INTC_GRP_12,
+	INTC_GRP_13,
+	INTC_GRP_14,
+};
+
+#ifdef BOARD_ASURADA_SCP
+static struct {
+	uint8_t group;
+} irqs[SCP_INTC_IRQ_COUNT] = {
+	/* 0 */
+	[SCP_IRQ_GIPC_IN0] = { INTC_GRP_7 },
+	[SCP_IRQ_GIPC_IN1] = { INTC_GRP_0 },
+	[SCP_IRQ_GIPC_IN2] = { INTC_GRP_0 },
+	[SCP_IRQ_GIPC_IN3] = { INTC_GRP_0 },
+	/* 4 */
+	[SCP_IRQ_SPM] = { INTC_GRP_0 },
+	[SCP_IRQ_AP_CIRQ] = { INTC_GRP_0 },
+	[SCP_IRQ_EINT] = { INTC_GRP_0 },
+	[SCP_IRQ_PMIC] = { INTC_GRP_0 },
+	/* 8 */
+	[SCP_IRQ_UART0_TX] = { INTC_GRP_12 },
+	[SCP_IRQ_UART1_TX] = { INTC_GRP_12 },
+	[SCP_IRQ_I2C0] = { INTC_GRP_0 },
+	[SCP_IRQ_I2C1_0] = { INTC_GRP_0 },
+	/* 12 */
+	[SCP_IRQ_BUS_DBG_TRACKER] = { INTC_GRP_0 },
+	[SCP_IRQ_CLK_CTRL] = { INTC_GRP_0 },
+	[SCP_IRQ_VOW] = { INTC_GRP_0 },
+	[SCP_IRQ_TIMER0] = { INTC_GRP_6 },
+	/* 16 */
+	[SCP_IRQ_TIMER1] = { INTC_GRP_6 },
+	[SCP_IRQ_TIMER2] = { INTC_GRP_6 },
+	[SCP_IRQ_TIMER3] = { INTC_GRP_6 },
+	[SCP_IRQ_TIMER4] = { INTC_GRP_6 },
+	/* 20 */
+	[SCP_IRQ_TIMER5] = { INTC_GRP_6 },
+	[SCP_IRQ_OS_TIMER] = { INTC_GRP_0 },
+	[SCP_IRQ_UART0_RX] = { INTC_GRP_12 },
+	[SCP_IRQ_UART1_RX] = { INTC_GRP_12 },
+	/* 24 */
+	[SCP_IRQ_GDMA] = { INTC_GRP_0 },
+	[SCP_IRQ_AUDIO] = { INTC_GRP_0 },
+	[SCP_IRQ_MD_DSP] = { INTC_GRP_0 },
+	[SCP_IRQ_ADSP] = { INTC_GRP_0 },
+	/* 28 */
+	[SCP_IRQ_CPU_TICK] = { INTC_GRP_0 },
+	[SCP_IRQ_SPI0] = { INTC_GRP_0 },
+	[SCP_IRQ_SPI1] = { INTC_GRP_0 },
+	[SCP_IRQ_SPI2] = { INTC_GRP_0 },
+	/* 32 */
+	[SCP_IRQ_NEW_INFRA_SYS_CIRQ] = { INTC_GRP_0 },
+	[SCP_IRQ_DBG] = { INTC_GRP_0 },
+	[SCP_IRQ_CCIF0] = { INTC_GRP_0 },
+	[SCP_IRQ_CCIF1] = { INTC_GRP_0 },
+	/* 36 */
+	[SCP_IRQ_CCIF2] = { INTC_GRP_0 },
+	[SCP_IRQ_WDT] = { INTC_GRP_0 },
+	[SCP_IRQ_USB0] = { INTC_GRP_0 },
+	[SCP_IRQ_USB1] = { INTC_GRP_0 },
+	/* 40 */
+	[SCP_IRQ_DPMAIF] = { INTC_GRP_0 },
+	[SCP_IRQ_INFRA] = { INTC_GRP_0 },
+	[SCP_IRQ_CLK_CTRL_CORE] = { INTC_GRP_0 },
+	[SCP_IRQ_CLK_CTRL2_CORE] = { INTC_GRP_0 },
+	/* 44 */
+	[SCP_IRQ_CLK_CTRL2] = { INTC_GRP_0 },
+	[SCP_IRQ_GIPC_IN4] = { INTC_GRP_0 },
+	[SCP_IRQ_PERIBUS_TIMEOUT] = { INTC_GRP_0 },
+	[SCP_IRQ_INFRABUS_TIMEOUT] = { INTC_GRP_0 },
+	/* 48 */
+	[SCP_IRQ_MET0] = { INTC_GRP_0 },
+	[SCP_IRQ_MET1] = { INTC_GRP_0 },
+	[SCP_IRQ_MET2] = { INTC_GRP_0 },
+	[SCP_IRQ_MET3] = { INTC_GRP_0 },
+	/* 52 */
+	[SCP_IRQ_AP_WDT] = { INTC_GRP_0 },
+	[SCP_IRQ_L2TCM_SEC_VIO] = { INTC_GRP_0 },
+	[SCP_IRQ_CPU_TICK1] = { INTC_GRP_0 },
+	[SCP_IRQ_MAD_DATAIN] = { INTC_GRP_0 },
+	/* 56 */
+	[SCP_IRQ_I3C0_IBI_WAKE] = { INTC_GRP_0 },
+	[SCP_IRQ_I3C1_IBI_WAKE] = { INTC_GRP_0 },
+	[SCP_IRQ_I3C2_IBI_WAKE] = { INTC_GRP_0 },
+	[SCP_IRQ_APU_ENGINE] = { INTC_GRP_0 },
+	/* 60 */
+	[SCP_IRQ_MBOX0] = { INTC_GRP_0 },
+	[SCP_IRQ_MBOX1] = { INTC_GRP_0 },
+	[SCP_IRQ_MBOX2] = { INTC_GRP_0 },
+	[SCP_IRQ_MBOX3] = { INTC_GRP_0 },
+	/* 64 */
+	[SCP_IRQ_MBOX4] = { INTC_GRP_0 },
+	[SCP_IRQ_SYS_CLK_REQ] = { INTC_GRP_0 },
+	[SCP_IRQ_BUS_REQ] = { INTC_GRP_0 },
+	[SCP_IRQ_APSRC_REQ] = { INTC_GRP_0 },
+	/* 68 */
+	[SCP_IRQ_APU_MBOX] = { INTC_GRP_0 },
+	[SCP_IRQ_DEVAPC_SECURE_VIO] = { INTC_GRP_0 },
+	/* 72 */
+	/* 76 */
+	[SCP_IRQ_I2C1_2] = { INTC_GRP_0 },
+	[SCP_IRQ_I2C2] = { INTC_GRP_0 },
+	/* 80 */
+	[SCP_IRQ_AUD2AUDIODSP] = { INTC_GRP_0 },
+	[SCP_IRQ_AUD2AUDIODSP_2] = { INTC_GRP_0 },
+	[SCP_IRQ_CONN2ADSP_A2DPOL] = { INTC_GRP_0 },
+	[SCP_IRQ_CONN2ADSP_BTCVSD] = { INTC_GRP_0 },
+	/* 84 */
+	[SCP_IRQ_CONN2ADSP_BLEISO] = { INTC_GRP_0 },
+	[SCP_IRQ_PCIE2ADSP] = { INTC_GRP_0 },
+	[SCP_IRQ_APU2ADSP_ENGINE] = { INTC_GRP_0 },
+	[SCP_IRQ_APU2ADSP_MBOX] = { INTC_GRP_0 },
+	/* 88 */
+	[SCP_IRQ_CCIF3] = { INTC_GRP_0 },
+	[SCP_IRQ_I2C_DMA0] = { INTC_GRP_0 },
+	[SCP_IRQ_I2C_DMA1] = { INTC_GRP_0 },
+	[SCP_IRQ_I2C_DMA2] = { INTC_GRP_0 },
+	/* 92 */
+	[SCP_IRQ_I2C_DMA3] = { INTC_GRP_0 },
+};
+BUILD_ASSERT(ARRAY_SIZE(irqs) == SCP_INTC_IRQ_COUNT);
+#endif
+
+#ifdef BOARD_CHERRY_SCP
+static struct {
+	uint8_t group;
+} irqs[SCP_INTC_IRQ_COUNT] = {
+	/* 0 */
+	[SCP_IRQ_GIPC_IN0] = { INTC_GRP_7 },
+	[SCP_IRQ_GIPC_IN1] = { INTC_GRP_0 },
+	[SCP_IRQ_GIPC_IN2] = { INTC_GRP_0 },
+	[SCP_IRQ_GIPC_IN3] = { INTC_GRP_0 },
+	/* 4 */
+	[SCP_IRQ_SPM] = { INTC_GRP_0 },
+	[SCP_IRQ_AP_CIRQ] = { INTC_GRP_0 },
+	[SCP_IRQ_EINT] = { INTC_GRP_0 },
+	[SCP_IRQ_PMIC] = { INTC_GRP_0 },
+	/* 8 */
+	[SCP_IRQ_UART0_TX] = { INTC_GRP_12 },
+	[SCP_IRQ_UART1_TX] = { INTC_GRP_12 },
+	[SCP_IRQ_I2C0] = { INTC_GRP_0 },
+	[SCP_IRQ_I2C1_0] = { INTC_GRP_0 },
+	/* 12 */
+	[SCP_IRQ_BUS_DBG_TRACKER] = { INTC_GRP_0 },
+	[SCP_IRQ_CLK_CTRL] = { INTC_GRP_0 },
+	[SCP_IRQ_VOW] = { INTC_GRP_0 },
+	[SCP_IRQ_TIMER0] = { INTC_GRP_6 },
+	/* 16 */
+	[SCP_IRQ_TIMER1] = { INTC_GRP_6 },
+	[SCP_IRQ_TIMER2] = { INTC_GRP_6 },
+	[SCP_IRQ_TIMER3] = { INTC_GRP_6 },
+	[SCP_IRQ_TIMER4] = { INTC_GRP_6 },
+	/* 20 */
+	[SCP_IRQ_TIMER5] = { INTC_GRP_6 },
+	[SCP_IRQ_OS_TIMER] = { INTC_GRP_0 },
+	[SCP_IRQ_UART0_RX] = { INTC_GRP_12 },
+	[SCP_IRQ_UART1_RX] = { INTC_GRP_12 },
+	/* 24 */
+	[SCP_IRQ_GDMA] = { INTC_GRP_0 },
+	[SCP_IRQ_AUDIO] = { INTC_GRP_0 },
+	[SCP_IRQ_MD_DSP] = { INTC_GRP_0 },
+	[SCP_IRQ_ADSP] = { INTC_GRP_0 },
+	/* 28 */
+	[SCP_IRQ_CPU_TICK] = { INTC_GRP_0 },
+	[SCP_IRQ_SPI0] = { INTC_GRP_0 },
+	[SCP_IRQ_SPI1] = { INTC_GRP_0 },
+	[SCP_IRQ_SPI2] = { INTC_GRP_0 },
+	/* 32 */
+	[SCP_IRQ_NEW_INFRA_SYS_CIRQ] = { INTC_GRP_0 },
+	[SCP_IRQ_DBG] = { INTC_GRP_0 },
+	[SCP_IRQ_GCE] = { INTC_GRP_0 },
+	[SCP_IRQ_MDP_GCE] = { INTC_GRP_0 },
+	/* 36 */
+	[SCP_IRQ_VDEC] = { INTC_GRP_8 },
+	[SCP_IRQ_WDT] = { INTC_GRP_0 },
+	[SCP_IRQ_VDEC_LAT] = { INTC_GRP_8 },
+	[SCP_IRQ_VDEC1] = { INTC_GRP_8 },
+	/* 40 */
+	[SCP_IRQ_VDEC1_LAT] = { INTC_GRP_8 },
+	[SCP_IRQ_INFRA] = { INTC_GRP_0 },
+	[SCP_IRQ_CLK_CTRL_CORE] = { INTC_GRP_0 },
+	[SCP_IRQ_CLK_CTRL2_CORE] = { INTC_GRP_0 },
+	/* 44 */
+	[SCP_IRQ_CLK_CTRL2] = { INTC_GRP_0 },
+	[SCP_IRQ_GIPC_IN4] = { INTC_GRP_0 },
+	[SCP_IRQ_PERIBUS_TIMEOUT] = { INTC_GRP_0 },
+	[SCP_IRQ_INFRABUS_TIMEOUT] = { INTC_GRP_0 },
+	/* 48 */
+	[SCP_IRQ_MET0] = { INTC_GRP_0 },
+	[SCP_IRQ_MET1] = { INTC_GRP_0 },
+	[SCP_IRQ_MET2] = { INTC_GRP_0 },
+	[SCP_IRQ_MET3] = { INTC_GRP_0 },
+	/* 52 */
+	[SCP_IRQ_AP_WDT] = { INTC_GRP_0 },
+	[SCP_IRQ_L2TCM_SEC_VIO] = { INTC_GRP_0 },
+	[SCP_IRQ_VDEC_INT_LINE_CNT] = { INTC_GRP_0 },
+	[SCP_IRQ_VOW_DATAIN] = { INTC_GRP_0 },
+	/* 56 */
+	[SCP_IRQ_I3C0_IBI_WAKE] = { INTC_GRP_0 },
+	[SCP_IRQ_I3C1_IBI_WAKE] = { INTC_GRP_0 },
+	[SCP_IRQ_VENC] = { INTC_GRP_8 },
+	[SCP_IRQ_APU_ENGINE] = { INTC_GRP_0 },
+	/* 60 */
+	[SCP_IRQ_MBOX0] = { INTC_GRP_0 },
+	[SCP_IRQ_MBOX1] = { INTC_GRP_0 },
+	[SCP_IRQ_MBOX2] = { INTC_GRP_0 },
+	[SCP_IRQ_MBOX3] = { INTC_GRP_0 },
+	/* 64 */
+	[SCP_IRQ_MBOX4] = { INTC_GRP_0 },
+	[SCP_IRQ_SYS_CLK_REQ] = { INTC_GRP_0 },
+	[SCP_IRQ_BUS_REQ] = { INTC_GRP_0 },
+	[SCP_IRQ_APSRC_REQ] = { INTC_GRP_0 },
+	/* 68 */
+	[SCP_IRQ_APU_MBOX] = { INTC_GRP_0 },
+	[SCP_IRQ_DEVAPC_SECURE_VIO] = { INTC_GRP_0 },
+	[SCP_IRQ_APDMA0] = { INTC_GRP_0 },
+	[SCP_IRQ_APDMA1] = { INTC_GRP_0 },
+	/* 72 */
+	[SCP_IRQ_APDMA2] = { INTC_GRP_0 },
+	[SCP_IRQ_APDMA3] = { INTC_GRP_0 },
+	[SCP_IRQ_APDMA4] = { INTC_GRP_0 },
+	[SCP_IRQ_APDMA5] = { INTC_GRP_0 },
+	/* 76 */
+	[SCP_IRQ_HDMIRX_PM_DVI_SQH] = { INTC_GRP_0 },
+	[SCP_IRQ_HDMIRX_RESERVED] = { INTC_GRP_0 },
+	[SCP_IRQ_NNA0_0] = { INTC_GRP_0 },
+	[SCP_IRQ_NNA0_1] = { INTC_GRP_0 },
+	/* 80 */
+	[SCP_IRQ_NNA0_2] = { INTC_GRP_0 },
+	[SCP_IRQ_NNA1_0] = { INTC_GRP_0 },
+	[SCP_IRQ_NNA1_1] = { INTC_GRP_0 },
+	[SCP_IRQ_NNA1_2] = { INTC_GRP_0 },
+	/* 84 */
+	[SCP_IRQ_JPEGENC] = { INTC_GRP_0 },
+	[SCP_IRQ_JPEGDEC] = { INTC_GRP_0 },
+	[SCP_IRQ_JPEGDEC_C2] = { INTC_GRP_0 },
+	[SCP_IRQ_VENC_C1] = { INTC_GRP_8 },
+	/* 88 */
+	[SCP_IRQ_JPEGENC_C1] = { INTC_GRP_0 },
+	[SCP_IRQ_JPEGDEC_C1] = { INTC_GRP_0 },
+	[SCP_IRQ_HDMITX] = { INTC_GRP_0 },
+	[SCP_IRQ_HDMI2] = { INTC_GRP_0 },
+	/* 92 */
+	[SCP_IRQ_EARC] = { INTC_GRP_0 },
+	[SCP_IRQ_CEC] = { INTC_GRP_0 },
+	[SCP_IRQ_HDMI_DEV_DET] = { INTC_GRP_0 },
+	[SCP_IRQ_HDMIRX_OUT_ARM_PHY] = { INTC_GRP_0 },
+	/* 96 */
+	[SCP_IRQ_I2C2] = { INTC_GRP_0 },
+	[SCP_IRQ_I2C3] = { INTC_GRP_0 },
+	[SCP_IRQ_I3C2_IBI_WAKE] = { INTC_GRP_0 },
+	[SCP_IRQ_I3C3_IBI_WAKE] = { INTC_GRP_0 },
+	/* 100 */
+	[SCP_IRQ_SYS_I2C_0] = { INTC_GRP_0 },
+	[SCP_IRQ_SYS_I2C_1] = { INTC_GRP_0 },
+	[SCP_IRQ_SYS_I2C_2] = { INTC_GRP_0 },
+	[SCP_IRQ_SYS_I2C_3] = { INTC_GRP_0 },
+	/* 104 */
+	[SCP_IRQ_SYS_I2C_4] = { INTC_GRP_0 },
+	[SCP_IRQ_SYS_I2C_5] = { INTC_GRP_0 },
+	[SCP_IRQ_SYS_I2C_6] = { INTC_GRP_0 },
+	[SCP_IRQ_SYS_I2C_7] = { INTC_GRP_0 },
+	/* 108 */
+	[SCP_IRQ_DISP2ADSP_0] = { INTC_GRP_0 },
+	[SCP_IRQ_DISP2ADSP_1] = { INTC_GRP_0 },
+	[SCP_IRQ_DISP2ADSP_2] = { INTC_GRP_0 },
+	[SCP_IRQ_DISP2ADSP_3] = { INTC_GRP_0 },
+	/* 112 */
+	[SCP_IRQ_DISP2ADSP_4] = { INTC_GRP_0 },
+	[SCP_IRQ_VDO1_DISP_MON2ADSP_0] = { INTC_GRP_0 },
+	[SCP_IRQ_VDO1_DISP_MON2ADSP_1] = { INTC_GRP_0 },
+	[SCP_IRQ_VDO1_DISP_MON2ADSP_2] = { INTC_GRP_0 },
+	/* 116 */
+	[SCP_IRQ_GCE1_SECURE] = { INTC_GRP_0 },
+	[SCP_IRQ_GCE_SECURE] = { INTC_GRP_0 },
+};
+BUILD_ASSERT(ARRAY_SIZE(irqs) == SCP_INTC_IRQ_COUNT);
+#endif
+
+/*
+ * Find current interrupt source.
+ *
+ * Lower group has higher priority.
+ * Higher INT number has higher priority.
+ */
+#define EC_INT_MAGIC_DUMP_GROUP BIT(15)
+int chip_get_ec_int(void)
+{
+	extern volatile int ec_int;
+	unsigned int group, sta;
+	int word;
+
+	group = read_csr(CSR_VIC_MICAUSE);
+
+	if (!SCP_CORE0_INTC_IRQ_OUT) {
+		ec_int = EC_INT_MAGIC_DUMP_GROUP | group;
+		goto error;
+	}
+
+	for (word = SCP_INTC_GRP_LEN - 1; word >= 0; --word) {
+		sta = SCP_CORE0_INTC_IRQ_GRP_STA(group, word);
+		if (sta) {
+			ec_int = __fls(sta) + word * 32;
+			return ec_int;
+		}
+	}
+
+error:
+	/* unreachable, SCP crashes and dumps registers after returning */
+	return -1;
+}
+
+int chip_get_intc_group(int irq)
+{
+	return irqs[irq].group;
+}
+
+void chip_enable_irq(int irq)
+{
+	unsigned int word, group, mask;
+
+	word = SCP_INTC_WORD(irq);
+	group = irqs[irq].group;
+	mask = BIT(SCP_INTC_BIT(irq));
+
+	/* disable interrupt */
+	SCP_CORE0_INTC_IRQ_EN(word) &= ~mask;
+	/* set group */
+	SCP_CORE0_INTC_IRQ_GRP(group, word) |= mask;
+	/* set as a wakeup source */
+	SCP_CORE0_INTC_SLP_WAKE_EN(word) |= mask;
+	/* enable interrupt */
+	SCP_CORE0_INTC_IRQ_EN(word) |= mask;
+}
+
+void chip_disable_irq(int irq)
+{
+	/*
+	 * Disabling INTC IRQ in runtime is unstable in MT8192 SCP.
+	 * See b/163682416#comment17.
+	 *
+	 * Ideally, this function will be removed by LTO.
+	 */
+	ccprints("WARNING: %s is unsupported", __func__);
+}
+
+void chip_clear_pending_irq(int irq)
+{
+	unsigned int group = irqs[irq].group;
+
+	/* must clear interrupt source before writing this */
+	write_csr(CSR_VIC_MIEMS, group);
+}
+
+int chip_trigger_irq(int irq)
+{
+	extern volatile int ec_int;
+
+	ec_int = irq;
+	return irqs[irq].group;
+}
+
+void chip_init_irqs(void)
+{
+	unsigned int word, group;
+
+	/* INTC init */
+	/* clear enable and wakeup settings */
+	for (word = 0; word < SCP_INTC_GRP_LEN; ++word) {
+		SCP_CORE0_INTC_IRQ_EN(word) = 0x0;
+		SCP_CORE0_INTC_SLP_WAKE_EN(word) = 0x0;
+
+		/* clear group settings */
+		for (group = 0; group < SCP_INTC_GRP_COUNT; ++group)
+			SCP_CORE0_INTC_IRQ_GRP(group, word) = 0x0;
+	}
+	/* reset to default polarity */
+	SCP_CORE0_INTC_IRQ_POL(0) = SCP_INTC_IRQ_POL0;
+	SCP_CORE0_INTC_IRQ_POL(1) = SCP_INTC_IRQ_POL1;
+	SCP_CORE0_INTC_IRQ_POL(2) = SCP_INTC_IRQ_POL2;
+#if SCP_INTC_GRP_LEN > 3
+	SCP_CORE0_INTC_IRQ_POL(3) = SCP_INTC_IRQ_POL3;
+#endif
+
+	/* GVIC init */
+	/* enable all groups as interrupt sources */
+	write_csr(CSR_VIC_MIMASK_G0, 0xffffffff);
+	/* use level trigger */
+	write_csr(CSR_VIC_MILSEL_G0, 0xffffffff);
+	/* enable all groups as wakeup sources */
+	write_csr(CSR_VIC_MIWAKEUP_G0, 0xffffffff);
+
+	/* enable GVIC */
+	set_csr(CSR_MCTREN, CSR_MCTREN_VIC);
+}
diff --git a/chip/mt_scp/rv32i_common/ipi.c b/chip/mt_scp/rv32i_common/ipi.c
new file mode 100644
index 0000000000..b8db16b9ea
--- /dev/null
+++ b/chip/mt_scp/rv32i_common/ipi.c
@@ -0,0 +1,184 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "atomic.h"
+#include "cache.h"
+#include "common.h"
+#include "console.h"
+#include "hooks.h"
+#include "hostcmd.h"
+#include "ipi_chip.h"
+#include "registers.h"
+#include "system.h"
+#include "task.h"
+#include "util.h"
+#include "video.h"
+
+#define CPRINTF(format, args...) cprintf(CC_IPI, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_IPI, format, ##args)
+
+static uint8_t init_done;
+
+static struct mutex ipi_lock;
+static struct ipc_shared_obj *const ipi_send_buf =
+	(struct ipc_shared_obj *)CONFIG_IPC_SHARED_OBJ_ADDR;
+static struct ipc_shared_obj *const ipi_recv_buf =
+	(struct ipc_shared_obj *)(CONFIG_IPC_SHARED_OBJ_ADDR +
+				  sizeof(struct ipc_shared_obj));
+
+static atomic_t disable_irq_count, saved_int_mask;
+
+void ipi_disable_irq(void)
+{
+	if (atomic_read_add(&disable_irq_count, 1) == 0)
+		saved_int_mask = read_clear_int_mask();
+}
+
+void ipi_enable_irq(void)
+{
+	if (atomic_read_sub(&disable_irq_count, 1) == 1)
+		set_int_mask(saved_int_mask);
+}
+
+static int ipi_is_busy(void)
+{
+	return SCP_SCP2APMCU_IPC_SET & IPC_SCP2HOST;
+}
+
+static void ipi_wake_ap(int32_t id)
+{
+	if (id >= IPI_COUNT)
+		return;
+
+	if (*ipi_wakeup_table[id])
+		SCP_SCP2SPM_IPC_SET = IPC_SCP2HOST;
+}
+
+int ipi_send(int32_t id, const void *buf, uint32_t len, int wait)
+{
+	int ret;
+
+	if (!init_done) {
+		CPRINTS("IPI has not initialized");
+		return EC_ERROR_BUSY;
+	}
+
+	if (in_interrupt_context()) {
+		CPRINTS("invoke %s() in ISR context", __func__);
+		return EC_ERROR_BUSY;
+	}
+
+	if (len > sizeof(ipi_send_buf->buffer)) {
+		CPRINTS("data length exceeds limitation");
+		return EC_ERROR_INVAL;
+	}
+
+	ipi_disable_irq();
+	mutex_lock(&ipi_lock);
+
+	if (ipi_is_busy()) {
+		/*
+		 * If the following conditions meet,
+		 *   1) There is an IPI pending in AP.
+		 *   2) The incoming IPI is a wakeup IPI.
+		 * then it assumes that AP is in suspend state.
+		 * Send a AP wakeup request to SPM.
+		 *
+		 * The incoming IPI will be checked if it's a wakeup source.
+		 */
+		ipi_wake_ap(id);
+
+		CPRINTS("IPI busy, id=%d", id);
+		ret = EC_ERROR_BUSY;
+		goto error;
+	}
+
+	ipi_send_buf->id = id;
+	ipi_send_buf->len = len;
+	memcpy(ipi_send_buf->buffer, buf, len);
+
+	/* flush memory cache (if any) */
+	cache_flush_dcache_range((uintptr_t)ipi_send_buf,
+				 sizeof(*ipi_send_buf));
+
+	/* interrupt AP to handle the message */
+	ipi_wake_ap(id);
+	SCP_SCP2APMCU_IPC_SET = IPC_SCP2HOST;
+
+	if (wait)
+		while (ipi_is_busy())
+			;
+
+	ret = EC_SUCCESS;
+error:
+	mutex_unlock(&ipi_lock);
+	ipi_enable_irq();
+	return ret;
+}
+
+static void ipi_enable_deferred(void)
+{
+	struct scp_run_t scp_run;
+	int ret;
+
+	init_done = 1;
+
+	/* inform AP that SCP is up */
+	scp_run.signaled = 1;
+	strncpy(scp_run.fw_ver, system_get_version(EC_IMAGE_RW),
+		SCP_FW_VERSION_LEN);
+	scp_run.dec_capability = video_get_dec_capability();
+	scp_run.enc_capability = video_get_enc_capability();
+
+	ret = ipi_send(SCP_IPI_INIT, (void *)&scp_run, sizeof(scp_run), 1);
+	if (ret) {
+		CPRINTS("failed to send initialization IPC messages");
+		init_done = 0;
+		return;
+	}
+
+#ifdef HAS_TASK_HOSTCMD
+	hostcmd_init();
+#endif
+
+	task_enable_irq(SCP_IRQ_GIPC_IN0);
+}
+DECLARE_DEFERRED(ipi_enable_deferred);
+
+static void ipi_init(void)
+{
+	memset(ipi_send_buf, 0, sizeof(struct ipc_shared_obj));
+	memset(ipi_recv_buf, 0, sizeof(struct ipc_shared_obj));
+
+	/* enable IRQ after all tasks are up */
+	hook_call_deferred(&ipi_enable_deferred_data, 0);
+}
+DECLARE_HOOK(HOOK_INIT, ipi_init, HOOK_PRIO_DEFAULT);
+
+static void ipi_handler(void)
+{
+	if (ipi_recv_buf->id >= IPI_COUNT) {
+		CPRINTS("invalid IPI, id=%d", ipi_recv_buf->id);
+		return;
+	}
+
+	CPRINTS("IPI %d", ipi_recv_buf->id);
+
+	ipi_handler_table[ipi_recv_buf->id](
+		ipi_recv_buf->id, ipi_recv_buf->buffer, ipi_recv_buf->len);
+}
+
+static void irq_group7_handler(void)
+{
+	extern volatile int ec_int;
+
+	if (SCP_GIPC_IN_SET & GIPC_IN(0)) {
+		ipi_handler();
+		SCP_GIPC_IN_CLR = GIPC_IN(0);
+		asm volatile("fence.i" ::: "memory");
+		task_clear_pending_irq(ec_int);
+	}
+}
+DECLARE_IRQ(7, irq_group7_handler, 0);
diff --git a/chip/mt_scp/rv32i_common/ipi_chip.h b/chip/mt_scp/rv32i_common/ipi_chip.h
new file mode 100644
index 0000000000..22ab85b39e
--- /dev/null
+++ b/chip/mt_scp/rv32i_common/ipi_chip.h
@@ -0,0 +1,86 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_IPI_CHIP_H
+#define __CROS_EC_IPI_CHIP_H
+
+#include "common.h"
+
+/*
+ * Length of EC version string is at most 32 byte (NULL included), which
+ * also aligns SCP fw_version length.
+ */
+#define SCP_FW_VERSION_LEN 32
+
+#ifndef SCP_IPI_INIT
+#error If CONFIG_IPI is enabled, SCP_IPI_INIT must be defined.
+#endif
+
+/*
+ * Share buffer layout for SCP_IPI_INIT response. This structure should sync
+ * across kernel and EC.
+ */
+struct scp_run_t {
+	uint32_t signaled;
+	int8_t fw_ver[SCP_FW_VERSION_LEN];
+	uint32_t dec_capability;
+	uint32_t enc_capability;
+};
+
+/*
+ * The layout of the IPC0 AP/SCP shared buffer.
+ * This should sync across kernel and EC.
+ */
+struct ipc_shared_obj {
+	/* IPI ID */
+	int32_t id;
+	/* Length of the contents in buffer. */
+	uint32_t len;
+	/* Shared buffer contents. */
+	uint8_t buffer[CONFIG_IPC_SHARED_OBJ_BUF_SIZE];
+};
+
+/* Send a IPI contents to AP.  This shouldn't be used in ISR context. */
+int ipi_send(int32_t id, const void *buf, uint32_t len, int wait);
+
+/*
+ * An IPC IRQ could be shared across many IPI handlers.
+ * Those handlers would usually operate on disabling or enabling the IPC IRQ.
+ * This may disorder the actual timing to on/off the IRQ when there are many
+ * tasks try to operate on it.  As a result, any access to the SCP_IRQ_*
+ * should go through ipi_{en,dis}able_irq(), which support a counter to
+ * enable/disable the IRQ at correct timing.
+ */
+/* Disable IPI IRQ. */
+void ipi_disable_irq(void);
+/* Enable IPI IRQ. */
+void ipi_enable_irq(void);
+
+/* IPI tables */
+extern void (*const ipi_handler_table[])(int32_t, void *, uint32_t);
+extern int *const ipi_wakeup_table[];
+
+/* Helper macros to build the IPI handler and wakeup functions. */
+#define IPI_HANDLER(id) CONCAT3(ipi_, id, _handler)
+#define IPI_WAKEUP(id) CONCAT3(ipi_, id, _wakeup)
+
+/*
+ * Macro to declare an IPI handler.
+ * _id: The ID of the IPI
+ * handler: The IPI handler function
+ * is_wakeup_src: Declare IPI ID as a wake-up source or not
+ */
+#define DECLARE_IPI(_id, handler, is_wakeup_src)                             \
+	struct ipi_num_check##_id {                                          \
+		int tmp1[_id < IPI_COUNT ? 1 : -1];                          \
+		int tmp2[is_wakeup_src == 0 || is_wakeup_src == 1 ? 1 : -1]; \
+	};                                                                   \
+	void __keep IPI_HANDLER(_id)(int32_t id, void *buf, uint32_t len)    \
+	{                                                                    \
+		handler(id, buf, len);                                       \
+	}                                                                    \
+	const int __keep IPI_WAKEUP(_id) = is_wakeup_src
+
+#endif /* __CROS_EC_IPI_CHIP_H */
diff --git a/chip/mt_scp/rv32i_common/ipi_table.c b/chip/mt_scp/rv32i_common/ipi_table.c
new file mode 100644
index 0000000000..3a6411d4d2
--- /dev/null
+++ b/chip/mt_scp/rv32i_common/ipi_table.c
@@ -0,0 +1,70 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * IPI handlers declaration
+ */
+
+#include "common.h"
+#include "ipi_chip.h"
+
+typedef void (*ipi_handler_t)(int32_t id, void *data, uint32_t len);
+
+#ifndef PASS
+#define PASS 1
+#endif
+
+#define ipi_arguments int32_t id, void *data, uint32_t len
+
+#if PASS == 1
+void ipi_handler_undefined(ipi_arguments)
+{
+}
+
+const int ipi_wakeup_undefined;
+
+#define table(type, name, x) x
+
+#define ipi_x_func(suffix, args, number)                                    \
+	extern void                                                         \
+		__attribute__((used, weak,                                  \
+			       alias(STRINGIFY(ipi_##suffix##_undefined)))) \
+		ipi_##number##_##suffix(args);
+
+#define ipi_x_var(suffix, number)                                              \
+	extern int __attribute__((weak,                                        \
+				  alias(STRINGIFY(ipi_##suffix##_undefined)))) \
+	ipi_##number##_##suffix;
+
+#endif /* PASS == 1 */
+
+#if PASS == 2
+
+#undef table
+#undef ipi_x_func
+#undef ipi_x_var
+
+#define table(type, name, x)                               \
+	type const name[] __attribute__((aligned(4), used, \
+					 section(".rodata.ipi"))) = { x }
+
+#define ipi_x_var(suffix, number) \
+	[number < IPI_COUNT ? number : -1] = &ipi_##number##_##suffix,
+
+#define ipi_x_func(suffix, args, number) ipi_x_var(suffix, number)
+
+#endif /* PASS == 2 */
+
+/*
+ * Include generated IPI table (by util/gen_ipi_table). The contents originate
+ * from IPI_COUNT definition in board.h
+ */
+#include "ipi_table_gen.inc"
+
+#if PASS == 1
+#undef PASS
+#define PASS 2
+#include "ipi_table.c"
+BUILD_ASSERT(ARRAY_SIZE(ipi_handler_table) == IPI_COUNT);
+BUILD_ASSERT(ARRAY_SIZE(ipi_wakeup_table) == IPI_COUNT);
+#endif
diff --git a/chip/mt_scp/rv32i_common/memmap.c b/chip/mt_scp/rv32i_common/memmap.c
new file mode 100644
index 0000000000..8ae64cf585
--- /dev/null
+++ b/chip/mt_scp/rv32i_common/memmap.c
@@ -0,0 +1,109 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cache.h"
+#include "registers.h"
+#include "stdint.h"
+
+/*
+ * Map SCP address (bits 31~28) to AP address
+ *
+ * SCP address	AP address	Note
+ *
+ * 0x0000_0000			SRAM
+ * 0x1000_0000	0x5000_0000	CPU DRAM
+ * 0x2000_0000	0x7000_0000
+ * 0x3000_0000
+ *
+ * 0x4000_0000
+ * 0x5000_0000	0x0000_0000
+ * 0x6000_0000	0x1000_0000
+ * 0x7000_0000	0xa000_0000
+ *
+ * 0x8000_0000
+ * 0x9000_0000	0x8000_0000
+ * 0xa000_0000	0x9000_0000
+ * 0xb000_0000
+ *
+ * 0xc000_0000	0x8000_0000
+ * 0xd000_0000	0x2000_0000
+ * 0xe000_0000	0x3000_0000
+ * 0xf000_0000	0x6000_0000
+ */
+
+#define REMAP_ADDR_SHIFT 28
+#define REMAP_ADDR_LSB_MASK (BIT(REMAP_ADDR_SHIFT) - 1)
+#define REMAP_ADDR_MSB_MASK ((~0) << REMAP_ADDR_SHIFT)
+#define MAP_INVALID 0xff
+
+static const uint8_t addr_map[16] = {
+	MAP_INVALID, /* SRAM */
+	0x5, /* ext_addr_0x1 */
+	0x7, /* ext_addr_0x2 */
+	MAP_INVALID, /* no ext_addr_0x3 */
+
+	MAP_INVALID, /* no ext_addr_0x4 */
+	0x0, /* ext_addr_0x5 */
+	0x1, /* ext_addr_0x6 */
+	0xa, /* ext_addr_0x7 */
+
+	MAP_INVALID, /* no ext_addr_0x8 */
+	0x8, /* ext_addr_0x9 */
+	0x9, /* ext_addr_0xa */
+	MAP_INVALID, /* no ext_addr_0xb */
+
+	0x8, /* ext_addr_0xc */
+	0x2, /* ext_addr_0xd */
+	0x3, /* ext_addr_0xe */
+	0x6, /* ext_addr_0xf */
+};
+
+void memmap_init(void)
+{
+	SCP_R_REMAP_0X0123 = (uint32_t)addr_map[0x1] << 8 |
+			     (uint32_t)addr_map[0x2] << 16;
+
+	SCP_R_REMAP_0X4567 = (uint32_t)addr_map[0x5] << 8 |
+			     (uint32_t)addr_map[0x6] << 16 |
+			     (uint32_t)addr_map[0x7] << 24;
+
+	SCP_R_REMAP_0X89AB = (uint32_t)addr_map[0x9] << 8 |
+			     (uint32_t)addr_map[0xa] << 16;
+
+	SCP_R_REMAP_0XCDEF =
+		(uint32_t)addr_map[0xc] | (uint32_t)addr_map[0xd] << 8 |
+		(uint32_t)addr_map[0xe] << 16 | (uint32_t)addr_map[0xf] << 24;
+
+	cache_init();
+}
+
+int memmap_ap_to_scp(uintptr_t ap_addr, uintptr_t *scp_addr)
+{
+	int i;
+	uint8_t msb = ap_addr >> REMAP_ADDR_SHIFT;
+
+	for (i = 0; i < ARRAY_SIZE(addr_map); ++i) {
+		if (addr_map[i] != msb)
+			continue;
+
+		*scp_addr = (ap_addr & REMAP_ADDR_LSB_MASK) |
+			    (i << REMAP_ADDR_SHIFT);
+		return EC_SUCCESS;
+	}
+
+	return EC_ERROR_INVAL;
+}
+
+int memmap_scp_to_ap(uintptr_t scp_addr, uintptr_t *ap_addr)
+{
+	int i = scp_addr >> REMAP_ADDR_SHIFT;
+
+	if (addr_map[i] == MAP_INVALID)
+		return EC_ERROR_INVAL;
+
+	*ap_addr = (scp_addr & REMAP_ADDR_LSB_MASK) |
+		   (addr_map[i] << REMAP_ADDR_SHIFT);
+	return EC_SUCCESS;
+}
diff --git a/chip/mt_scp/rv32i_common/memmap.h b/chip/mt_scp/rv32i_common/memmap.h
new file mode 100644
index 0000000000..2c043fbe9c
--- /dev/null
+++ b/chip/mt_scp/rv32i_common/memmap.h
@@ -0,0 +1,31 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_MEMMAP_H
+#define __CROS_EC_MEMMAP_H
+
+#include "stdint.h"
+
+void memmap_init(void);
+
+/**
+ * Translate AP addr to SCP addr.
+ *
+ * @param ap_addr		AP address to translate
+ * @param scp_addr		Translated AP address
+ * @return			EC_SUCCESS or EC_ERROR_INVAL
+ */
+int memmap_ap_to_scp(uintptr_t ap_addr, uintptr_t *scp_addr);
+
+/**
+ * Translate SCP addr to AP addr.
+ *
+ * @param scp_addr		SCP address to translate
+ * @param ap_addr		Translated SCP address
+ * @return			EC_SUCCESS or EC_ERROR_INVAL
+ */
+int memmap_scp_to_ap(uintptr_t scp_addr, uintptr_t *ap_addr);
+
+#endif /* #ifndef __CROS_EC_MEMMAP_H */
diff --git a/chip/mt_scp/rv32i_common/registers.h b/chip/mt_scp/rv32i_common/registers.h
new file mode 100644
index 0000000000..8688bbc033
--- /dev/null
+++ b/chip/mt_scp/rv32i_common/registers.h
@@ -0,0 +1,216 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Register map */
+
+#ifndef __CROS_EC_REGISTERS_H
+#define __CROS_EC_REGISTERS_H
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "intc.h"
+
+#define UNIMPLEMENTED_GPIO_BANK 0
+
+#define SCP_REG_BASE 0x70000000
+
+/* clock control */
+#define SCP_CLK_CTRL_BASE (SCP_REG_BASE + 0x21000)
+/* system clock counter value */
+#define SCP_CLK_SYS_VAL REG32(SCP_CLK_CTRL_BASE + 0x0014)
+#define CLK_SYS_VAL_MASK (0x3ff << 0)
+#define CLK_SYS_VAL_VAL(v) ((v)&CLK_SYS_VAL_MASK)
+/* ULPOSC clock counter value */
+#define SCP_CLK_HIGH_VAL REG32(SCP_CLK_CTRL_BASE + 0x0018)
+#define CLK_HIGH_VAL_MASK (0x1f << 0)
+#define CLK_HIGH_VAL_VAL(v) ((v)&CLK_HIGH_VAL_MASK)
+/* sleep mode control */
+#define SCP_SLEEP_CTRL REG32(SCP_CLK_CTRL_BASE + 0x0020)
+#define SLP_CTRL_EN BIT(0)
+#define VREQ_COUNT_MASK (0x7F << 1)
+#define VREQ_COUNT_VAL(v) (((v) << 1) & VREQ_COUNT_MASK)
+#define SPM_SLP_MODE BIT(8)
+/* clock divider select */
+#define SCP_CLK_DIV_SEL REG32(SCP_CLK_CTRL_BASE + 0x0024)
+#define CLK_DIV_SEL1 0
+#define CLK_DIV_SEL2 1
+#define CLK_DIV_SEL4 2
+#define CLK_DIV_SEL3 3
+/* clock gate */
+#define SCP_SET_CLK_CG REG32(SCP_CLK_CTRL_BASE + 0x0030)
+#define CG_TIMER_MCLK BIT(0)
+#define CG_TIMER_BCLK BIT(1)
+#define CG_MAD_MCLK BIT(2)
+#define CG_I2C_MCLK BIT(3)
+#define CG_I2C_BCLK BIT(4)
+#define CG_GPIO_MCLK BIT(5)
+#define CG_AP2P_MCLK BIT(6)
+#define CG_UART0_MCLK BIT(7)
+#define CG_UART0_BCLK BIT(8)
+#define CG_UART0_RST BIT(9)
+#define CG_UART1_MCLK BIT(10)
+#define CG_UART1_BCLK BIT(11)
+#define CG_UART1_RST BIT(12)
+#define CG_SPI0 BIT(13)
+#define CG_SPI1 BIT(14)
+#define CG_SPI2 BIT(15)
+#define CG_DMA_CH0 BIT(16)
+#define CG_DMA_CH1 BIT(17)
+#define CG_DMA_CH2 BIT(18)
+#define CG_DMA_CH3 BIT(19)
+#define CG_I3C0 BIT(21)
+#define CG_I3C1 BIT(22)
+#define CG_DMA2_CH0 BIT(23)
+#define CG_DMA2_CH1 BIT(24)
+#define CG_DMA2_CH2 BIT(25)
+#define CG_DMA2_CH3 BIT(26)
+/* UART clock select */
+#define SCP_UART_CK_SEL REG32(SCP_CLK_CTRL_BASE + 0x0044)
+#define UART0_CK_SEL_SHIFT 0
+#define UART0_CK_SEL_MASK (0x3 << UART0_CK_SEL_SHIFT)
+#define UART0_CK_SEL_VAL(v) ((v)&UART0_CK_SEL_MASK)
+#define UART0_CK_SW_STATUS_MASK (0xf << 8)
+#define UART0_CK_SW_STATUS_VAL(v) ((v)&UART0_CK_SW_STATUS_MASK)
+#define UART1_CK_SEL_SHIFT 16
+#define UART1_CK_SEL_MASK (0x3 << UART1_CK_SEL_SHIFT)
+#define UART1_CK_SEL_VAL(v) ((v)&UART1_CK_SEL_MASK)
+#define UART1_CK_SW_STATUS_MASK (0xf << 24)
+#define UART1_CK_SW_STATUS_VAL(v) ((v)&UART1_CK_SW_STATUS_MASK)
+#define UART_CK_SEL_26M 0
+#define UART_CK_SEL_32K 1
+#define UART_CK_SEL_ULPOSC 2
+#define UART_CK_SW_STATUS_26M BIT(0)
+#define UART_CK_SW_STATUS_32K BIT(1)
+#define UART_CK_SW_STATUS_ULPOS BIT(2)
+/* BCLK clock select */
+#define SCP_BCLK_CK_SEL REG32(SCP_CLK_CTRL_BASE + 0x0048)
+#define BCLK_CK_SEL_SYS_DIV8 0
+#define BCLK_CK_SEL_32K 1
+#define BCLK_CK_SEL_ULPOSC_DIV8 2
+/* VREQ control */
+#define SCP_CPU_VREQ_CTRL REG32(SCP_CLK_CTRL_BASE + 0x0054)
+#define VREQ_SEL BIT(0)
+#define VREQ_VALUE BIT(4)
+#define VREQ_EXT_SEL BIT(8)
+#define VREQ_DVFS_SEL BIT(16)
+#define VREQ_DVFS_VALUE BIT(20)
+#define VREQ_DVFS_EXT_SEL BIT(24)
+#define VREQ_SRCLKEN_SEL BIT(27)
+#define VREQ_SRCLKEN_VALUE BIT(28)
+/* clock on control */
+#define SCP_CLK_HIGH_CORE_CG REG32(SCP_CLK_CTRL_BASE + 0x005C)
+#define HIGH_CORE_CG BIT(1)
+#define SCP_CLK_ON_CTRL REG32(SCP_CLK_CTRL_BASE + 0x006C)
+#define HIGH_AO BIT(0)
+#define HIGH_DIS_SUB BIT(1)
+#define HIGH_CG_AO BIT(2)
+#define HIGH_CORE_AO BIT(4)
+#define HIGH_CORE_DIS_SUB BIT(5)
+#define HIGH_CORE_CG_AO BIT(6)
+
+/* system control */
+#define SCP_SYS_CTRL REG32(SCP_REG_BASE + 0x24000)
+#define AUTO_DDREN BIT(9)
+
+/* IPC */
+#define SCP_SCP2APMCU_IPC_SET REG32(SCP_REG_BASE + 0x24080)
+#define SCP_SCP2SPM_IPC_SET REG32(SCP_REG_BASE + 0x24090)
+#define IPC_SCP2HOST BIT(0)
+#define SCP_GIPC_IN_SET REG32(SCP_REG_BASE + 0x24098)
+#define SCP_GIPC_IN_CLR REG32(SCP_REG_BASE + 0x2409C)
+#define GIPC_IN(n) BIT(n)
+
+/* UART */
+#define SCP_UART_COUNT 2
+#define UART_TX_IRQ(n) CONCAT3(SCP_IRQ_UART, n, _TX)
+#define UART_RX_IRQ(n) CONCAT3(SCP_IRQ_UART, n, _RX)
+#define SCP_UART0_BASE (SCP_REG_BASE + 0x26000)
+#define SCP_UART1_BASE (SCP_REG_BASE + 0x27000)
+#define SCP_UART_BASE(n) CONCAT3(SCP_UART, n, _BASE)
+#define UART_REG(n, offset) REG32_ADDR(SCP_UART_BASE(n))[offset]
+
+/* WDT */
+#define SCP_CORE0_WDT_IRQ REG32(SCP_REG_BASE + 0x30030)
+#define SCP_CORE0_WDT_CFG REG32(SCP_REG_BASE + 0x30034)
+#define WDT_FREQ 33825 /* 0xFFFFF / 31 */
+#define WDT_MAX_PERIOD 0xFFFFF /* 31 seconds */
+#define WDT_PERIOD(ms) (WDT_FREQ * (ms) / 1000)
+#define WDT_EN BIT(31)
+#define SCP_CORE0_WDT_KICK REG32(SCP_REG_BASE + 0x30038)
+#define SCP_CORE0_WDT_CUR_VAL REG32(SCP_REG_BASE + 0x3003C)
+#define SCP_CORE0_MON_PC_LATCH REG32(SCP_REG_BASE + 0x300D0)
+#define SCP_CORE0_MON_LR_LATCH REG32(SCP_REG_BASE + 0x300D4)
+#define SCP_CORE0_MON_SP_LATCH REG32(SCP_REG_BASE + 0x300D8)
+
+/* INTC */
+#define SCP_INTC_WORD(irq) ((irq) >> 5) /* word length = 2^5 */
+#define SCP_INTC_BIT(irq) ((irq)&0x1F) /* bit shift =LSB[0:4] */
+#define SCP_INTC_GRP_COUNT 15
+#define SCP_INTC_GRP_GAP 4
+
+#define SCP_CORE0_INTC_IRQ_BASE (SCP_REG_BASE + 0x32000)
+#define SCP_CORE0_INTC_IRQ_STA(w) \
+	REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0010)[(w)]
+#define SCP_CORE0_INTC_IRQ_EN(w) \
+	REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0020)[(w)]
+#define SCP_CORE0_INTC_IRQ_POL(w) \
+	REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0040)[(w)]
+#define SCP_CORE0_INTC_IRQ_GRP(g, w)                  \
+	REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0050 + \
+		   ((g) << SCP_INTC_GRP_GAP))         \
+	[(w)]
+#define SCP_CORE0_INTC_IRQ_GRP_STA(g, w)              \
+	REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0150 + \
+		   ((g) << SCP_INTC_GRP_GAP))         \
+	[(w)]
+#define SCP_CORE0_INTC_SLP_WAKE_EN(w) \
+	REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0240)[(w)]
+#define SCP_CORE0_INTC_IRQ_OUT REG32(SCP_CORE0_INTC_IRQ_BASE + 0x0250)
+/* UART */
+#define SCP_CORE0_INTC_UART0_RX_IRQ REG32(SCP_CORE0_INTC_IRQ_BASE + 0x0258)
+#define SCP_CORE0_INTC_UART1_RX_IRQ REG32(SCP_CORE0_INTC_IRQ_BASE + 0x025C)
+#define SCP_CORE0_INTC_UART_RX_IRQ(n) CONCAT3(SCP_CORE0_INTC_UART, n, _RX_IRQ)
+
+/* XGPT (general purpose timer) */
+#define NUM_TIMERS 6
+#define SCP_CORE0_TIMER_BASE(n) (SCP_REG_BASE + 0x33000 + (0x10 * (n)))
+#define SCP_CORE0_TIMER_EN(n) REG32(SCP_CORE0_TIMER_BASE(n) + 0x0000)
+#define TIMER_EN BIT(0)
+#define TIMER_CLK_SRC_32K (0 << 4)
+#define TIMER_CLK_SRC_26M (1 << 4)
+#define TIMER_CLK_SRC_BCLK (2 << 4)
+#define TIMER_CLK_SRC_MCLK (3 << 4)
+#define TIMER_CLK_SRC_MASK (3 << 4)
+#define SCP_CORE0_TIMER_RST_VAL(n) REG32(SCP_CORE0_TIMER_BASE(n) + 0x0004)
+#define SCP_CORE0_TIMER_CUR_VAL(n) REG32(SCP_CORE0_TIMER_BASE(n) + 0x0008)
+#define SCP_CORE0_TIMER_IRQ_CTRL(n) REG32(SCP_CORE0_TIMER_BASE(n) + 0x000C)
+#define TIMER_IRQ_EN BIT(0)
+#define TIMER_IRQ_STATUS BIT(4)
+#define TIMER_IRQ_CLR BIT(5)
+#define SCP_IRQ_TIMER(n) CONCAT2(SCP_IRQ_TIMER, n)
+
+/* secure control */
+#define SCP_SEC_CTRL REG32(SCP_REG_BASE + 0xA5000)
+#define VREQ_SECURE_DIS BIT(4)
+/* memory remap */
+#define SCP_R_REMAP_0X0123 REG32(SCP_REG_BASE + 0xA5060)
+#define SCP_R_REMAP_0X4567 REG32(SCP_REG_BASE + 0xA5064)
+#define SCP_R_REMAP_0X89AB REG32(SCP_REG_BASE + 0xA5068)
+#define SCP_R_REMAP_0XCDEF REG32(SCP_REG_BASE + 0xA506C)
+
+/* external address: AP */
+#define AP_REG_BASE 0x60000000 /* 0x10000000 remap to 0x6 */
+/* AP GPIO */
+#define AP_GPIO_BASE (AP_REG_BASE + 0x5000)
+#define AP_GPIO_MODE11_SET REG32(AP_GPIO_BASE + 0x03B4)
+#define AP_GPIO_MODE11_CLR REG32(AP_GPIO_BASE + 0x03B8)
+#define AP_GPIO_MODE12_SET REG32(AP_GPIO_BASE + 0x03C4)
+#define AP_GPIO_MODE12_CLR REG32(AP_GPIO_BASE + 0x03C8)
+#define AP_GPIO_MODE20_SET REG32(AP_GPIO_BASE + 0x0444)
+#define AP_GPIO_MODE20_CLR REG32(AP_GPIO_BASE + 0x0448)
+
+#include "clock_regs.h"
+
+#endif /* __CROS_EC_REGISTERS_H */
diff --git a/chip/mt_scp/rv32i_common/scp_timer.h b/chip/mt_scp/rv32i_common/scp_timer.h
new file mode 100644
index 0000000000..1eed1d7792
--- /dev/null
+++ b/chip/mt_scp/rv32i_common/scp_timer.h
@@ -0,0 +1,16 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __SCP_TIMER_H
+#define __SCP_TIMER_H
+
+/* detect existance of 26m clock in S3 stage */
+#define TIMER_SR 4
+
+void timer_enable(int n);
+void timer_disable(int n);
+uint32_t timer_read_raw_sr(void);
+
+#endif /* __SCP_TIMER_H */
diff --git a/chip/mt_scp/rv32i_common/scp_watchdog.h b/chip/mt_scp/rv32i_common/scp_watchdog.h
new file mode 100644
index 0000000000..2a8225c047
--- /dev/null
+++ b/chip/mt_scp/rv32i_common/scp_watchdog.h
@@ -0,0 +1,15 @@
+
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __SCP_WATCHDOG_H
+#define __SCP_WATCHDOG_H
+
+#include "watchdog.h"
+
+void watchdog_disable(void);
+void watchdog_enable(void);
+
+#endif /* __SCP_WATCHDOG_H */
diff --git a/chip/mt_scp/rv32i_common/system.c b/chip/mt_scp/rv32i_common/system.c
new file mode 100644
index 0000000000..0eed2ae3ff
--- /dev/null
+++ b/chip/mt_scp/rv32i_common/system.c
@@ -0,0 +1,50 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* System : hardware specific implementation */
+
+#include "csr.h"
+#include "memmap.h"
+#include "registers.h"
+#include "system.h"
+
+void system_pre_init(void)
+{
+	memmap_init();
+
+	/* enable CPU and platform low power CG */
+	/* enable CPU DCM */
+	set_csr(CSR_MCTREN, CSR_MCTREN_CG);
+
+	/* Disable jump (it has only RW) */
+	system_disable_jump();
+}
+
+void system_reset(int flags)
+{
+	while (1)
+		;
+}
+
+int system_get_bbram(enum system_bbram_idx idx, uint8_t *value)
+{
+	return EC_ERROR_INVAL;
+}
+
+const char *system_get_chip_vendor(void)
+{
+	return "mtk";
+}
+
+const char *system_get_chip_name(void)
+{
+	/* Support only SCP_A for now */
+	return "scp_a";
+}
+
+const char *system_get_chip_revision(void)
+{
+	return "";
+}
diff --git a/chip/mt_scp/rv32i_common/uart.c b/chip/mt_scp/rv32i_common/uart.c
new file mode 100644
index 0000000000..a67a0bb276
--- /dev/null
+++ b/chip/mt_scp/rv32i_common/uart.c
@@ -0,0 +1,160 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* SCP UART module */
+
+#include "csr.h"
+#include "system.h"
+#include "uart.h"
+#include "uart_regs.h"
+#include "util.h"
+
+/*
+ * UARTN == 0, SCP UART0
+ * UARTN == 1, SCP UART1
+ * UARTN == 2, AP UART1
+ */
+#define UARTN CONFIG_UART_CONSOLE
+#define UART_IDLE_WAIT_US 500
+#define UART_INTC_GROUP 12
+
+static uint8_t init_done, tx_started;
+
+void uart_init(void)
+{
+	const uint32_t baud_rate = CONFIG_UART_BAUD_RATE;
+	const uint32_t uart_clock = 26000000;
+	const uint32_t div = DIV_ROUND_NEAREST(uart_clock, baud_rate * 16);
+
+	uart_init_pinmux();
+
+	/* Clear FIFO */
+	UART_FCR(UARTN) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR |
+			  UART_FCR_CLEAR_XMIT;
+	/* Line control: parity none, 8 bit, 1 stop bit */
+	UART_LCR(UARTN) = UART_LCR_WLEN8;
+	/* For baud rate <= 115200 */
+	UART_HIGHSPEED(UARTN) = 0;
+
+	/* DLAB start */
+	UART_LCR(UARTN) |= UART_LCR_DLAB;
+	UART_DLL(UARTN) = div & 0xff;
+	UART_DLH(UARTN) = (div >> 8) & 0xff;
+	UART_LCR(UARTN) &= ~UART_LCR_DLAB;
+	/* DLAB end */
+
+	/* Enable received data interrupt */
+	UART_IER(UARTN) |= UART_IER_RDI;
+
+#if (UARTN < SCP_UART_COUNT)
+	task_enable_irq(UART_TX_IRQ(UARTN));
+	task_enable_irq(UART_RX_IRQ(UARTN));
+#endif
+
+	init_done = 1;
+}
+
+int uart_init_done(void)
+{
+	return init_done;
+}
+
+void uart_tx_flush(void)
+{
+	while (!(UART_LSR(UARTN) & UART_LSR_TEMT))
+		;
+}
+
+int uart_tx_ready(void)
+{
+	return UART_LSR(UARTN) & UART_LSR_THRE;
+}
+
+int uart_rx_available(void)
+{
+	return UART_LSR(UARTN) & UART_LSR_DR;
+}
+
+void uart_write_char(char c)
+{
+	while (!uart_tx_ready())
+		;
+
+	UART_THR(UARTN) = c;
+}
+
+int uart_read_char(void)
+{
+	return UART_RBR(UARTN);
+}
+
+void uart_tx_start(void)
+{
+	tx_started = 1;
+	if (UART_IER(UARTN) & UART_IER_THRI)
+		return;
+	disable_sleep(SLEEP_MASK_UART);
+	UART_IER(UARTN) |= UART_IER_THRI;
+}
+
+void uart_tx_stop(void)
+{
+	/*
+	 * Workaround for b/157541273.
+	 * Don't unset the THRI flag unless we are in the UART ISR.
+	 *
+	 * Note:
+	 * MICAUSE denotes current INTC group number.
+	 */
+	if (in_interrupt_context() &&
+	    read_csr(CSR_VIC_MICAUSE) != UART_INTC_GROUP)
+		return;
+
+	tx_started = 0;
+	UART_IER(UARTN) &= ~UART_IER_THRI;
+	enable_sleep(SLEEP_MASK_UART);
+}
+
+static void uart_process(void)
+{
+	uart_process_input();
+	uart_process_output();
+}
+
+#if (UARTN < SCP_UART_COUNT)
+static void uart_irq_handler(void)
+{
+	extern volatile int ec_int;
+
+	switch (ec_int) {
+	case UART_TX_IRQ(UARTN):
+		uart_process();
+		task_clear_pending_irq(ec_int);
+		break;
+	case UART_RX_IRQ(UARTN):
+		uart_process();
+		SCP_CORE0_INTC_UART_RX_IRQ(UARTN) = BIT(0);
+		asm volatile("fence.i" ::: "memory");
+		task_clear_pending_irq(ec_int);
+		break;
+	}
+}
+DECLARE_IRQ(UART_INTC_GROUP, uart_irq_handler, 0);
+#else
+
+#ifndef HAS_TASK_APUART
+#error "APUART task hasn't defined in ec.tasklist."
+#endif
+
+void uart_task(void)
+{
+	while (1) {
+		if (uart_rx_available() || tx_started)
+			uart_process();
+		else
+			task_wait_event(UART_IDLE_WAIT_US);
+	}
+}
+#endif
diff --git a/chip/mt_scp/rv32i_common/uart_regs.h b/chip/mt_scp/rv32i_common/uart_regs.h
new file mode 100644
index 0000000000..d0eeaa81c2
--- /dev/null
+++ b/chip/mt_scp/rv32i_common/uart_regs.h
@@ -0,0 +1,80 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* SCP UART module registers */
+
+#ifndef __CROS_EC_UART_REGS_H
+#define __CROS_EC_UART_REGS_H
+
+#include "registers.h"
+
+/* Chip specific function for setting UART pinmux. */
+void uart_init_pinmux(void);
+
+/* DLAB (Divisor Latch Access Bit) == 0 */
+
+/* (Read) receiver buffer register */
+#define UART_RBR(n) UART_REG(n, 0)
+/* (Write) transmitter holding register */
+#define UART_THR(n) UART_REG(n, 0)
+/* (Write) interrupt enable register */
+#define UART_IER(n) UART_REG(n, 1)
+#define UART_IER_RDI BIT(0) /* received data */
+#define UART_IER_THRI BIT(1) /* THR empty */
+#define UART_IER_RLSI BIT(2) /* receiver LSR change */
+#define UART_IER_MSI BIT(3) /* MSR change */
+/* (Read) interrupt identification register */
+#define UART_IIR(n) UART_REG(n, 2)
+#define UART_IIR_ID_MASK 0x0e
+#define UART_IIR_MSI 0x00 /* modem status change */
+#define UART_IIR_NO_INT 0x01 /* no int pending */
+#define UART_IIR_THRI 0x02 /* THR empty */
+#define UART_IIR_RDI 0x04 /* received data available */
+#define UART_IIR_RLSI 0x06 /* line status change */
+/* (Write) FIFO control register */
+#define UART_FCR(n) UART_REG(n, 2)
+#define UART_FCR_ENABLE_FIFO BIT(0) /* enable FIFO */
+#define UART_FCR_CLEAR_RCVR BIT(1) /* clear receive FIFO */
+#define UART_FCR_CLEAR_XMIT BIT(2) /* clear transmit FIFO */
+#define UART_FCR_DMA_SELECT BIT(3) /* select DMA mode */
+/* (Write) line control register */
+#define UART_LCR(n) UART_REG(n, 3)
+#define UART_LCR_WLEN5 0 /* word length 5 bits */
+#define UART_LCR_WLEN6 1
+#define UART_LCR_WLEN7 2
+#define UART_LCR_WLEN8 3
+#define UART_LCR_STOP BIT(2) /* stop bits: 1bit, 2bits */
+#define UART_LCR_PARITY BIT(3) /* parity enable */
+#define UART_LCR_EPAR BIT(4) /* even parity */
+#define UART_LCR_SPAR BIT(5) /* stick parity */
+#define UART_LCR_SBC BIT(6) /* set break control */
+#define UART_LCR_DLAB BIT(7) /* divisor latch access */
+/* (Write) modem control register */
+#define UART_MCR(n) UART_REG(n, 4)
+/* (Read) line status register */
+#define UART_LSR(n) UART_REG(n, 5)
+#define UART_LSR_DR BIT(0) /* data ready */
+#define UART_LSR_OE BIT(1) /* overrun error */
+#define UART_LSR_PE BIT(2) /* parity error */
+#define UART_LSR_FE BIT(3) /* frame error */
+#define UART_LSR_BI BIT(4) /* break interrupt */
+#define UART_LSR_THRE BIT(5) /* THR empty */
+#define UART_LSR_TEMT BIT(6) /* THR empty, line idle */
+#define UART_LSR_FIFOE BIT(7) /* FIFO error */
+/* (Read) modem status register */
+#define UART_MSR(n) UART_REG(n, 6)
+/* (Read/Write) scratch register */
+#define UART_SCR(n) UART_REG(n, 7)
+
+/* DLAB == 1 */
+
+/* (Write) divisor latch */
+#define UART_DLL(n) UART_REG(n, 0)
+#define UART_DLH(n) UART_REG(n, 1)
+
+/* MTK extension */
+#define UART_HIGHSPEED(n) UART_REG(n, 9)
+
+#endif /* __CROS_EC_UART_REGS_H */
diff --git a/chip/mt_scp/rv32i_common/video.h b/chip/mt_scp/rv32i_common/video.h
new file mode 100644
index 0000000000..d2a4384e80
--- /dev/null
+++ b/chip/mt_scp/rv32i_common/video.h
@@ -0,0 +1,34 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_VIDEO_H
+#define __CROS_EC_VIDEO_H
+
+#include "common.h"
+
+/*
+ * Video decoder supported capability
+ */
+#define VDEC_CAP_4K_DISABLED BIT(4)
+#define VDEC_CAP_MM21 BIT(5)
+#define VDEC_CAP_MT21C BIT(6)
+#define VDEC_CAP_H264_SLICE BIT(8)
+#define VDEC_CAP_VP8_FRAME BIT(9)
+#define VDEC_CAP_VP9_FRAME BIT(10)
+#define VDEC_CAP_AV1_FRAME BIT(11)
+#define VDEC_CAP_HEVC_SLICE BIT(12)
+#define VDEC_CAP_IRQ_IN_SCP BIT(16)
+#define VDEC_CAP_INNER_RACING BIT(17)
+
+/*
+ * Video encoder supported capability:
+ * BIT(0): enable 4K
+ */
+#define VENC_CAP_4K BIT(0)
+
+uint32_t video_get_enc_capability(void);
+uint32_t video_get_dec_capability(void);
+
+#endif /* #ifndef __CROS_EC_VIDEO_H */
diff --git a/chip/mt_scp/rv32i_common/watchdog.c b/chip/mt_scp/rv32i_common/watchdog.c
new file mode 100644
index 0000000000..e8f5b5c3f9
--- /dev/null
+++ b/chip/mt_scp/rv32i_common/watchdog.c
@@ -0,0 +1,47 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Watchdog driver */
+
+#include "common.h"
+#include "hooks.h"
+#include "registers.h"
+#include "scp_watchdog.h"
+#include "watchdog.h"
+
+void watchdog_reload(void)
+{
+	SCP_CORE0_WDT_KICK = BIT(0);
+}
+DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT);
+
+void watchdog_disable(void)
+{
+	/* disable watchdog */
+	SCP_CORE0_WDT_CFG &= ~WDT_EN;
+	/* clear watchdog irq */
+	SCP_CORE0_WDT_IRQ |= BIT(0);
+}
+
+void watchdog_enable(void)
+{
+	const uint32_t timeout = WDT_PERIOD(CONFIG_WATCHDOG_PERIOD_MS);
+
+	/* disable watchdog */
+	SCP_CORE0_WDT_CFG &= ~WDT_EN;
+	/* clear watchdog irq */
+	SCP_CORE0_WDT_IRQ |= BIT(0);
+	/* enable watchdog */
+	SCP_CORE0_WDT_CFG = WDT_EN | timeout;
+	/* reload watchdog */
+	watchdog_reload();
+}
+
+int watchdog_init(void)
+{
+	watchdog_enable();
+
+	return EC_SUCCESS;
+}
diff --git a/chip/mt_scp/serial_reg.h b/chip/mt_scp/serial_reg.h
deleted file mode 100644
index 5344566272..0000000000
--- a/chip/mt_scp/serial_reg.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * UART register map
- */
-
-#ifndef __CROS_EC_SERIAL_REG_H
-#define __CROS_EC_SERIAL_REG_H
-
-#include "registers.h"
-
-/* Number of hardware ports */
-#define HW_UART_PORTS 2
-
-/* DLAB (Divisor Latch Access Bit) == 0 */
-
-/* Data register
- *   (Read) Rcvr buffer register
- *   (Write) Xmit holding register
- */
-#define UART_DATA(n)			UART_REG(n, 0)
-/* (Write) Interrupt enable register */
-#define UART_IER(n)			UART_REG(n, 1)
-#define UART_IER_RDI			BIT(0) /* Recv data int */
-#define UART_IER_THRI			BIT(1) /* Xmit holding register int */
-#define UART_IER_RLSI			BIT(2) /* Rcvr line status int */
-#define UART_IER_MSI			BIT(3) /* Modem status int */
-/* (Read) Interrupt ID register */
-#define UART_IIR(n)			UART_REG(n, 2)
-#define UART_IIR_NO_INT			BIT(0) /* No int pending */
-#define UART_IIR_ID_MASK		0x0e /* Interrupt ID mask */
-#define UART_IIR_MSI			0x00
-#define UART_IIR_THRI			0x02
-#define UART_IIR_RDI			0x04
-#define UART_IIR_RLSI			0x06
-#define UART_IIR_BUSY			0x07 /* DW APB busy */
-/* (Write) FIFO control register */
-#define UART_FCR(n)			UART_REG(n, 2)
-#define UART_FCR_ENABLE_FIFO		BIT(0) /* Enable FIFO */
-#define UART_FCR_CLEAR_RCVR		BIT(1) /* Clear rcvr FIFO */
-#define UART_FCR_CLEAR_XMIT		BIT(2) /* Clear xmit FIFO */
-#define UART_FCR_DMA_SELECT		BIT(3)
-/* FIFO trigger levels */
-#define UART_FCR_T_TRIG_00		0x00
-#define UART_FCR_T_TRIG_01		0x10
-#define UART_FCR_T_TRIG_10		0x20
-#define UART_FCR_T_TRIG_11		0x30
-#define UART_FCR_R_TRIG_00		0x00
-#define UART_FCR_R_TRIG_01		0x40
-#define UART_FCR_R_TRIG_10		0x80
-#define UART_FCR_R_TRIG_11		0x80
-/* (Write) Line control register */
-#define UART_LCR(n)			UART_REG(n, 3)
-#define UART_LCR_WLEN5			0 /* Word length 5 bits */
-#define UART_LCR_WLEN6			1
-#define UART_LCR_WLEN7			2
-#define UART_LCR_WLEN8			3
-#define UART_LCR_STOP			BIT(2) /* Stop bits: 1bit, 2bits */
-#define UART_LCR_PARITY			BIT(3) /* Parity enable */
-#define UART_LCR_EPAR			BIT(4) /* Even parity */
-#define UART_LCR_SPAR			BIT(5) /* Stick parity */
-#define UART_LCR_SBC			BIT(6) /* Set break control */
-#define UART_LCR_DLAB			BIT(7) /* Divisor latch access */
-/* (Write) Modem control register */
-#define UART_MCR(n)			UART_REG(n, 4)
-/* (Read) Line status register */
-#define UART_LSR(n)			UART_REG(n, 5)
-#define UART_LSR_DR			BIT(0) /* Data ready */
-#define UART_LSR_OE			BIT(1) /* Overrun error */
-#define UART_LSR_PE			BIT(2) /* Parity error */
-#define UART_LSR_FE			BIT(3) /* Frame error */
-#define UART_LSR_BI			BIT(4) /* Break interrupt */
-#define UART_LSR_THRE			BIT(5) /* Xmit-hold-register empty */
-#define UART_LSR_TEMT			BIT(6) /* Xmit empty */
-#define UART_LSR_FIFOE			BIT(7) /* FIFO error */
-
-/* DLAB == 1 */
-
-/* (Write) Divisor latch */
-#define UART_DLL(n)			UART_REG(n, 0) /* Low */
-#define UART_DLH(n)			UART_REG(n, 1) /* High */
-
-/* MTK extension */
-#define UART_HIGHSPEED(n)		UART_REG(n, 9)
-#define UART_SAMPLE_COUNT(n)		UART_REG(n, 10)
-#define UART_SAMPLE_POINT(n)		UART_REG(n, 11)
-#define UART_RATE_FIX(n)		UART_REG(n, 13)
-
-#endif /* __CROS_EC_SERIAL_REG_H */
diff --git a/chip/mt_scp/system.c b/chip/mt_scp/system.c
deleted file mode 100644
index 6bd2e76644..0000000000
--- a/chip/mt_scp/system.c
+++ /dev/null
@@ -1,175 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* System : hardware specific implementation */
-
-#include "clock_chip.h"
-#include "console.h"
-#include "cpu.h"
-#include "flash.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "memmap.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-#include "version.h"
-#include "watchdog.h"
-
-/*
- * SCP_GPR[0] b15-b0  - scratchpad
- * SCP_GPR[0] b31-b16 - saved_flags
- */
-
-int system_set_scratchpad(uint32_t value)
-{
-	/* Check if value fits in 16 bits */
-	if (value & 0xffff0000)
-		return EC_ERROR_INVAL;
-
-	SCP_GPR[0] = (SCP_GPR[0] & 0xffff0000) | value;
-
-	return EC_SUCCESS;
-}
-
-uint32_t system_get_scratchpad(void)
-{
-	return SCP_GPR[0] & 0xffff;
-}
-
-const char *system_get_chip_vendor(void)
-{
-	return "mtk";
-}
-
-const char *system_get_chip_name(void)
-{
-	/* Support only SCP_A for now */
-	return "scp_a";
-}
-
-const char *system_get_chip_revision(void)
-{
-	return "";
-}
-
-void chip_pre_init(void)
-{
-}
-
-static void scp_cm4_mod(void)
-{
-	CM4_MODIFICATION = 3;
-	CM4_DCM_FEATURE = 3;
-}
-
-static void scp_enable_pirq(void)
-{
-	/* Enable all peripheral to SCP IRQ, except IPC0. */
-	SCP_INTC_IRQ_ENABLE = 0xFFFFFFFE;
-	SCP_INTC_IRQ_ENABLE_MSB = 0xFFFFFFFF;
-}
-
-void system_pre_init(void)
-{
-	/* CM4 Modification */
-	scp_cm4_mod();
-	/* Clock */
-	scp_enable_clock();
-	/* Peripheral IRQ */
-	scp_enable_pirq();
-	/* Init dram mapping (and cache) */
-	scp_memmap_init();
-	/* Disable jump (mt_scp has only RW) and enable MPU. */
-	system_disable_jump();
-}
-
-void system_reset(int flags)
-{
-	uint32_t save_flags = 0;
-
-	/* Disable interrupts to avoid task swaps during reboot */
-	interrupt_disable();
-
-	/* Save current reset reasons if necessary */
-	if (flags & SYSTEM_RESET_PRESERVE_FLAGS)
-		save_flags = system_get_reset_flags() | EC_RESET_FLAG_PRESERVED;
-
-	if (flags & SYSTEM_RESET_LEAVE_AP_OFF)
-		save_flags |= EC_RESET_FLAG_AP_OFF;
-
-	/* Remember that the software asked us to hard reboot */
-	if (flags & SYSTEM_RESET_HARD)
-		save_flags |= EC_RESET_FLAG_HARD;
-
-	/* Reset flags are 32-bits, but save only 16 bits. */
-	ASSERT(!(save_flags >> 16));
-	SCP_GPR[0] = (save_flags << 16) | (SCP_GPR[0] & 0xffff);
-
-	/* SCP can not hard reset itself */
-	ASSERT(!(flags & SYSTEM_RESET_HARD));
-
-	if (flags & SYSTEM_RESET_WAIT_EXT) {
-		int i;
-
-		/* Wait 10 seconds for external reset */
-		for (i = 0; i < 1000; i++) {
-			watchdog_reload();
-			udelay(10000);
-		}
-	}
-
-	/* Set watchdog timer to small value, and spin wait for watchdog reset */
-	SCP_WDT_CFG = 0;
-	SCP_WDT_CFG = SCP_WDT_ENABLE | SCP_WDT_PERIOD(1);
-	watchdog_reload();
-	while (1)
-		;
-}
-
-static void check_reset_cause(void)
-{
-	uint32_t flags = 0;
-	uint32_t raw_reset_cause = SCP_GPR[1];
-
-	/* Set state to power-on */
-	SCP_PWRON_STATE = PWRON_DEFAULT;
-
-	if ((raw_reset_cause & 0xffff0000) == PWRON_DEFAULT) {
-		/* Reboot */
-		if (raw_reset_cause & PWRON_WATCHDOG)
-			flags |= EC_RESET_FLAG_WATCHDOG;
-		else if (raw_reset_cause & PWRON_RESET)
-			flags |= EC_RESET_FLAG_POWER_ON;
-		else
-			flags |= EC_RESET_FLAG_OTHER;
-	} else {
-		/* Power lost restart */
-		flags |= EC_RESET_FLAG_POWER_ON;
-	}
-	system_set_reset_flags(SCP_GPR[0] >> 16);
-	SCP_GPR[0] &= 0xffff;
-}
-
-int system_is_reboot_warm(void)
-{
-	const uint32_t cold_flags =
-		EC_RESET_FLAG_RESET_PIN |
-		EC_RESET_FLAG_POWER_ON  |
-		EC_RESET_FLAG_WATCHDOG  |
-		EC_RESET_FLAG_HARD      |
-		EC_RESET_FLAG_SOFT      |
-		EC_RESET_FLAG_HIBERNATE;
-
-	check_reset_cause();
-
-	return !(system_get_reset_flags() & cold_flags);
-}
-
-int system_get_bbram(enum system_bbram_idx idx, uint8_t *value)
-{
-	return EC_ERROR_INVAL;
-}
diff --git a/chip/mt_scp/uart.c b/chip/mt_scp/uart.c
deleted file mode 100644
index 78ea594c6b..0000000000
--- a/chip/mt_scp/uart.c
+++ /dev/null
@@ -1,179 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* SCP UART module */
-
-#include "clock_chip.h"
-#include "console.h"
-#include "registers.h"
-#include "serial_reg.h"
-#include "system.h"
-#include "task.h"
-#include "uart.h"
-#include "util.h"
-
-/* Console UART index */
-#define UARTN           CONFIG_UART_CONSOLE
-#define UART_IDLE_WAIT_US 500
-
-static uint8_t uart_done, tx_started;
-
-int uart_init_done(void)
-{
-	/*
-	 * TODO: AP UART support
-	 * When access AP UART port, wait for AP peripheral clock
-	 */
-	return uart_done;
-}
-
-void uart_tx_start(void)
-{
-	tx_started = 1;
-
-	/* AP UART mode doesn't support interrupt */
-	if (UARTN >= SCP_UART_COUNT)
-		return;
-
-	if (UART_IER(UARTN) & UART_IER_THRI)
-		return;
-	disable_sleep(SLEEP_MASK_UART);
-	UART_IER(UARTN) |= UART_IER_THRI;
-}
-
-void uart_tx_stop(void)
-{
-	tx_started = 0;
-
-	/* AP UART mode doesn't support interrupt */
-	if (UARTN >= SCP_UART_COUNT)
-		return;
-
-	UART_IER(UARTN) &= ~UART_IER_THRI;
-	enable_sleep(SLEEP_MASK_UART);
-}
-
-void uart_tx_flush(void)
-{
-	while (!(UART_LSR(UARTN) & UART_LSR_TEMT))
-		;
-}
-
-int uart_tx_ready(void)
-{
-	/* Check xmit FIFO empty */
-	return UART_LSR(UARTN) & UART_LSR_THRE;
-}
-
-int uart_rx_available(void)
-{
-	/* Check rcvr data ready */
-	return UART_LSR(UARTN) & UART_LSR_DR;
-}
-
-void uart_write_char(char c)
-{
-	while (!uart_tx_ready())
-		;
-
-	UART_DATA(UARTN) = c;
-}
-
-int uart_read_char(void)
-{
-	return UART_DATA(UARTN);
-}
-
-void uart_process(void)
-{
-	uart_process_input();
-	uart_process_output();
-}
-
-#if (UARTN < SCP_UART_COUNT)
-void uart_interrupt(void)
-{
-	uint8_t ier;
-
-	task_clear_pending_irq(UART_IRQ(UARTN));
-	uart_process();
-	ier = UART_IER(UARTN);
-	UART_IER(UARTN) = 0;
-	UART_IER(UARTN) = ier;
-}
-DECLARE_IRQ(UART_IRQ(UARTN), uart_interrupt, 2);
-
-void uart_rx_interrupt(void)
-{
-	uint8_t ier;
-
-	task_clear_pending_irq(UART_RX_IRQ(UARTN));
-	SCP_INTC_UART_RX_IRQ &= ~BIT(UARTN);
-	uart_process();
-	ier = UART_IER(UARTN);
-	UART_IER(UARTN) = 0;
-	UART_IER(UARTN) = ier;
-	SCP_INTC_UART_RX_IRQ |= 1 << UARTN;
-}
-DECLARE_IRQ(UART_RX_IRQ(UARTN), uart_rx_interrupt, 2);
-#endif
-
-void uart_task(void)
-{
-#if (UARTN >= SCP_UART_COUNT)
-	while (1) {
-		if (uart_rx_available() || tx_started)
-			uart_process();
-		else
-			task_wait_event(UART_IDLE_WAIT_US);
-	}
-#endif
-}
-
-void uart_init(void)
-{
-	const uint32_t baud_rate = CONFIG_UART_BAUD_RATE;
-	/*
-	 * UART clock source is set to ULPOSC1 / 10 below.
-	 *
-	 * TODO(b:134035444): We could get slightly more precise frequency by
-	 * using the _measured_ ULPOSC1 frequency (instead of the target).
-	 */
-	const uint32_t uart_clock = ULPOSC1_CLOCK_MHZ * 1000 / 10 * 1000;
-	const uint32_t div = DIV_ROUND_NEAREST(uart_clock, baud_rate * 16);
-
-	/* Init clock */
-#if UARTN == 0
-	SCP_CLK_UART = CLK_UART_SEL_ULPOSC1_DIV10;
-	SCP_CLK_GATE |= CG_UART_M | CG_UART_B | CG_UART_RSTN;
-#elif UARTN == 1
-	SCP_CLK_UART = CLK_UART1_SEL_ULPOSC1_DIV10;
-	SCP_CLK_GATE |= CG_UART1_M | CG_UART1_B | CG_UART1_RSTN;
-#endif
-
-	/* Init and clear FIFO */
-	UART_FCR(UARTN) = UART_FCR_ENABLE_FIFO
-		| UART_FCR_CLEAR_RCVR
-		| UART_FCR_CLEAR_XMIT;
-	/* Line control: parity none, 8 bit, 1 stop bit */
-	UART_LCR(UARTN) = UART_LCR_WLEN8;
-	/* For baud rate <= 115200 */
-	UART_HIGHSPEED(UARTN) = 0;
-	/* DLAB = 1 and update DLL DLH */
-	UART_LCR(UARTN) |= UART_LCR_DLAB;
-	UART_DLL(UARTN) = div & 0xff;
-	UART_DLH(UARTN) = (div >> 8) & 0xff;
-	UART_LCR(UARTN) &= ~UART_LCR_DLAB;
-	UART_IER(UARTN) |= UART_IER_RDI;
-
-#if (UARTN < SCP_UART_COUNT)
-	task_enable_irq(UART_IRQ(UARTN));
-	task_enable_irq(UART_RX_IRQ(UARTN));
-	/* UART RX IRQ needs an extra enable */
-	SCP_INTC_UART_RX_IRQ |= 1 << UARTN;
-#endif
-	gpio_config_module(MODULE_UART, 1);
-	uart_done = 1;
-}
diff --git a/chip/mt_scp/watchdog.c b/chip/mt_scp/watchdog.c
deleted file mode 100644
index 74e2cad8e5..0000000000
--- a/chip/mt_scp/watchdog.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Watchdog driver */
-
-#include "common.h"
-#include "hooks.h"
-#include "panic.h"
-#include "registers.h"
-#include "watchdog.h"
-
-void watchdog_reload(void)
-{
-	SCP_WDT_RELOAD = SCP_WDT_RELOAD_VALUE;
-}
-DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT);
-
-int watchdog_init(void)
-{
-	const uint32_t watchdog_timeout =
-		SCP_WDT_PERIOD(CONFIG_WATCHDOG_PERIOD_MS);
-
-	/* Disable watchdog */
-	SCP_WDT_CFG = 0;
-	/* Enable watchdog */
-	SCP_WDT_CFG = SCP_WDT_ENABLE | watchdog_timeout;
-	/* Reload watchdog */
-	watchdog_reload();
-
-	return EC_SUCCESS;
-}
diff --git a/chip/npcx/adc.c b/chip/npcx/adc.c
index 365b401b87..73d4ec48b3 100644
--- a/chip/npcx/adc.c
+++ b/chip/npcx/adc.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,12 +6,11 @@
 /* NPCX-specific ADC module for Chrome EC */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "atomic.h"
 #include "clock.h"
 #include "clock_chip.h"
-#include "console.h"
 #include "common.h"
+#include "console.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "registers.h"
@@ -20,21 +19,38 @@
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
 /* Maximum time we allow for an ADC conversion */
-#define ADC_TIMEOUT_US            SECOND
-#define ADC_CLK                   2000000
-#define ADC_REGULAR_DLY           0x11
-#define ADC_REGULAR_ADCCNF2       0x8B07
-#define ADC_REGULAR_GENDLY        0x0100
-#define ADC_REGULAR_MEAST         0x0001
+#define ADC_TIMEOUT_US SECOND
+/*
+ * ADC basic clock is from APB1.
+ * In npcx5, APB1 clock frequency is (15 MHz / 4).
+ * Configure ADC clock divider and speed parameters to set the ADC clock to
+ * ~2 MHz.
+ * In npcx7 and later chips, APB1 clock frequency is 15 MHz.
+ * Configure ADC clock divider and speed parameters to set the ADC clock to
+ * 7.5 MHz.
+ */
+#if defined(CHIP_FAMILY_NPCX5)
+#define ADC_CLK 2000000
+#define ADC_DLY 0x03
+#define ADC_ADCCNF2 0x8B07
+#define ADC_GENDLY 0x0100
+#define ADC_MEAST 0x0001
+#else
+#define ADC_CLK 7500000
+#define ADC_DLY 0x02
+#define ADC_ADCCNF2 0x8901
+#define ADC_GENDLY 0x0100
+#define ADC_MEAST 0x0405
+#endif
 
 /* ADC conversion mode */
 enum npcx_adc_conversion_mode {
-	ADC_CHN_CONVERSION_MODE   = 0,
-	ADC_SCAN_CONVERSION_MODE  = 1
+	ADC_CHN_CONVERSION_MODE = 0,
+	ADC_SCAN_CONVERSION_MODE = 1
 };
 
 /* Global variables */
@@ -42,6 +58,8 @@ static volatile task_id_t task_waiting;
 
 struct mutex adc_lock;
 
+static volatile bool adc_done;
+
 /**
  * Preset ADC operation clock.
  *
@@ -51,7 +69,7 @@ struct mutex adc_lock;
  */
 void adc_freq_changed(void)
 {
-	uint8_t prescaler_divider    = 0;
+	uint8_t prescaler_divider = 0;
 
 	/* Set clock prescaler divider to ADC module*/
 	prescaler_divider = (uint8_t)(clock_get_apb1_freq() / ADC_CLK);
@@ -73,19 +91,23 @@ DECLARE_HOOK(HOOK_FREQ_CHANGE, adc_freq_changed, HOOK_PRIO_DEFAULT);
  * @return  TRUE/FALSE  success/fail
  * @notes   set SW-triggered interrupt conversion and one-shot mode in npcx chip
  */
-static int start_single_and_wait(enum npcx_adc_input_channel input_ch
-		, int timeout)
+static int start_single_and_wait(enum npcx_adc_input_channel input_ch,
+				 int timeout)
 {
 	int event;
 
-	task_waiting = task_get_current();
+	if (IS_ENABLED(CONFIG_KEYBOARD_SCAN_ADC)) {
+		if (task_start_called())
+			task_waiting = task_get_current();
+	} else
+		task_waiting = task_get_current();
 
 	/* Stop ADC conversion first */
 	SET_BIT(NPCX_ADCCNF, NPCX_ADCCNF_STOP);
 
 	/* Set ADC conversion code to SW conversion mode */
 	SET_FIELD(NPCX_ADCCNF, NPCX_ADCCNF_ADCMD_FIELD,
-			ADC_CHN_CONVERSION_MODE);
+		  ADC_CHN_CONVERSION_MODE);
 
 	/* Set conversion type to one-shot type */
 	CLEAR_BIT(NPCX_ADCCNF, NPCX_ADCCNF_ADCRPTC);
@@ -102,13 +124,35 @@ static int start_single_and_wait(enum npcx_adc_input_channel input_ch
 	/* Start conversion */
 	SET_BIT(NPCX_ADCCNF, NPCX_ADCCNF_START);
 
-	/* Wait for interrupt */
-	event = task_wait_event_mask(TASK_EVENT_ADC_DONE, timeout);
+	/*
+	 * If tasks have started, we can suspend to the task that called us.
+	 * If not, we need to busy poll for adc to finish before proceeding
+	 */
+	if (IS_ENABLED(CONFIG_KEYBOARD_SCAN_ADC)) {
+		if (!task_start_called()) {
+			/* Wait for the ADC interrupt to set the flag */
+			do {
+				usleep(10);
+			} while (adc_done == false);
 
-	task_waiting = TASK_ID_INVALID;
+			adc_done = false;
 
-	return (event == TASK_EVENT_ADC_DONE);
+			event = TASK_EVENT_ADC_DONE;
+		} else {
+			/* Wait for interrupt */
+			event = task_wait_event_mask(TASK_EVENT_ADC_DONE,
+						     timeout);
+
+			task_waiting = TASK_ID_INVALID;
+		}
+	} else {
+		/* Wait for interrupt */
+		event = task_wait_event_mask(TASK_EVENT_ADC_DONE, timeout);
 
+		task_waiting = TASK_ID_INVALID;
+	}
+
+	return (event == TASK_EVENT_ADC_DONE);
 }
 
 static uint16_t repetitive_enabled;
@@ -168,8 +212,9 @@ int adc_read_data(enum npcx_adc_input_channel input_ch)
 	uint16_t chn_data;
 
 	chn_data = NPCX_CHNDAT(adc->input_ch);
-	value = GET_FIELD(chn_data, NPCX_CHNDAT_CHDAT_FIELD) *
-		 adc->factor_mul / adc->factor_div + adc->shift;
+	value = GET_FIELD(chn_data, NPCX_CHNDAT_CHDAT_FIELD) * adc->factor_mul /
+			adc->factor_div +
+		adc->shift;
 	return value;
 }
 
@@ -196,11 +241,11 @@ int adc_read_channel(enum adc_channel ch)
 	if (start_single_and_wait(adc->input_ch, ADC_TIMEOUT_US)) {
 		chn_data = NPCX_CHNDAT(adc->input_ch);
 		if ((adc->input_ch ==
-			GET_FIELD(NPCX_ASCADD, NPCX_ASCADD_SADDR_FIELD))
-			&& (IS_BIT_SET(chn_data,
-					NPCX_CHNDAT_NEW))) {
+		     GET_FIELD(NPCX_ASCADD, NPCX_ASCADD_SADDR_FIELD)) &&
+		    (IS_BIT_SET(chn_data, NPCX_CHNDAT_NEW))) {
 			value = GET_FIELD(chn_data, NPCX_CHNDAT_CHDAT_FIELD) *
-				adc->factor_mul / adc->factor_div + adc->shift;
+					adc->factor_mul / adc->factor_div +
+				adc->shift;
 		} else {
 			value = ADC_READ_ERROR;
 		}
@@ -216,7 +261,7 @@ int adc_read_channel(enum adc_channel ch)
 	} else {
 		/* Set ADC conversion code to SW conversion mode */
 		SET_FIELD(NPCX_ADCCNF, NPCX_ADCCNF_ADCMD_FIELD,
-		  ADC_SCAN_CONVERSION_MODE);
+			  ADC_SCAN_CONVERSION_MODE);
 		/* Set conversion type to repetitive (runs continuously) */
 		SET_BIT(NPCX_ADCCNF, NPCX_ADCCNF_ADCRPTC);
 		/* Start conversion */
@@ -238,8 +283,7 @@ void npcx_adc_thresh_int_enable(int threshold_idx, int enable)
 	enable = !!enable;
 
 	if ((threshold_idx < 1) || (threshold_idx > NPCX_ADC_THRESH_CNT)) {
-		CPRINTS("Invalid ADC thresh index! (%d)",
-			threshold_idx);
+		CPRINTS("Invalid ADC thresh index! (%d)", threshold_idx);
 		return;
 	}
 	threshold_idx--; /* convert to 0-based */
@@ -268,24 +312,21 @@ void npcx_adc_register_thresh_irq(int threshold_idx,
 	int shift;
 
 	if ((threshold_idx < 1) || (threshold_idx > NPCX_ADC_THRESH_CNT)) {
-		CPRINTS("Invalid ADC thresh index! (%d)",
-			threshold_idx);
+		CPRINTS("Invalid ADC thresh index! (%d)", threshold_idx);
 		return;
 	}
 	npcx_adc_ch = adc_channels[thresh_cfg->adc_ch].input_ch;
 
 	if (!thresh_cfg->adc_thresh_cb) {
-		CPRINTS("No callback for ADC Threshold %d!",
-			threshold_idx);
+		CPRINTS("No callback for ADC Threshold %d!", threshold_idx);
 		return;
 	}
 
 	/* Fill in the table */
-	adc_thresh_irqs[threshold_idx-1] = thresh_cfg->adc_thresh_cb;
+	adc_thresh_irqs[threshold_idx - 1] = thresh_cfg->adc_thresh_cb;
 
 	/* Select the channel */
-	SET_FIELD(NPCX_THRCTL(threshold_idx), NPCX_THRCTL_CHNSEL,
-		  npcx_adc_ch);
+	SET_FIELD(NPCX_THRCTL(threshold_idx), NPCX_THRCTL_CHNSEL, npcx_adc_ch);
 
 	if (thresh_cfg->lower_or_higher)
 		SET_BIT(NPCX_THRCTL(threshold_idx), NPCX_THRCTL_L_H);
@@ -300,8 +341,7 @@ void npcx_adc_register_thresh_irq(int threshold_idx,
 	raw_val = (thresh_cfg->thresh_assert - shift) * div / mul;
 	CPRINTS("ADC THR%d: Setting THRVAL = %d, L_H: %d", threshold_idx,
 		raw_val, thresh_cfg->lower_or_higher);
-	SET_FIELD(NPCX_THRCTL(threshold_idx), NPCX_THRCTL_THRVAL,
-		  raw_val);
+	SET_FIELD(NPCX_THRCTL(threshold_idx), NPCX_THRCTL_THRVAL, raw_val);
 
 #if NPCX_FAMILY_VERSION <= NPCX_FAMILY_NPCX7
 	/* Disable deassertion threshold function */
@@ -319,7 +359,7 @@ void npcx_adc_register_thresh_irq(int threshold_idx,
  * @return  none
  * @notes   Only handle SW-triggered conversion in npcx chip
  */
-void adc_interrupt(void)
+static void adc_interrupt(void)
 {
 	int i;
 	uint16_t thrcts;
@@ -338,7 +378,12 @@ void adc_interrupt(void)
 
 		/* Wake up the task which was waiting for the interrupt */
 		if (task_waiting != TASK_ID_INVALID)
-			task_set_event(task_waiting, TASK_EVENT_ADC_DONE, 0);
+			task_set_event(task_waiting, TASK_EVENT_ADC_DONE);
+
+		if (IS_ENABLED(CONFIG_KEYBOARD_SCAN_ADC)) {
+			if (!task_start_called())
+				adc_done = true;
+		}
 	}
 
 	for (i = NPCX_THRCTS_THR1_STS; i < NPCX_ADC_THRESH_CNT; i++) {
@@ -346,7 +391,7 @@ void adc_interrupt(void)
 		    IS_BIT_SET(NPCX_THRCTS, i)) {
 			/* avoid clearing other threshold status */
 			thrcts = NPCX_THRCTS &
-					~GENMASK(NPCX_ADC_THRESH_CNT - 1, 0);
+				 ~GENMASK(NPCX_ADC_THRESH_CNT - 1, 0);
 			/* Clear threshold status */
 			SET_BIT(thrcts, i);
 			NPCX_THRCTS = thrcts;
@@ -357,35 +402,47 @@ void adc_interrupt(void)
 }
 DECLARE_IRQ(NPCX_IRQ_ADC, adc_interrupt, 4);
 
+/*
+ * For Antighost keyboard, we need to initialize adc from
+ * main before keyboard_scan_init is called in order to
+ * detect boot keys
+ */
+
 /**
  * ADC initial.
  *
  * @param none
  * @return none
  */
+#ifndef CONFIG_KEYBOARD_SCAN_ADC
 static void adc_init(void)
+#else
+void adc_init(void)
+#endif
 {
 	/* Configure pins from GPIOs to ADCs */
 	gpio_config_module(MODULE_ADC, 1);
 
 	/* Enable ADC clock (bit4 mask = 0x10) */
 	clock_enable_peripheral(CGC_OFFSET_ADC, CGC_ADC_MASK,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
+				CGC_MODE_RUN | CGC_MODE_SLEEP);
 
 	/* Set Core Clock Division Factor in order to obtain the ADC clock */
 	adc_freq_changed();
 
 	/* Set regular speed */
-	SET_FIELD(NPCX_ATCTL, NPCX_ATCTL_DLY_FIELD, (ADC_REGULAR_DLY - 1));
+	SET_FIELD(NPCX_ATCTL, NPCX_ATCTL_DLY_FIELD, ADC_DLY);
 
 	/* Set the other ADC settings */
-	NPCX_ADCCNF2 = ADC_REGULAR_ADCCNF2;
-	NPCX_GENDLY = ADC_REGULAR_GENDLY;
-	NPCX_MEAST = ADC_REGULAR_MEAST;
+	NPCX_ADCCNF2 = ADC_ADCCNF2;
+	NPCX_GENDLY = ADC_GENDLY;
+	NPCX_MEAST = ADC_MEAST;
 
 	task_waiting = TASK_ID_INVALID;
 
 	/* Enable IRQs */
 	task_enable_irq(NPCX_IRQ_ADC);
 }
+#ifndef CONFIG_KEYBOARD_SCAN_ADC
 DECLARE_HOOK(HOOK_INIT, adc_init, HOOK_PRIO_INIT_ADC);
+#endif
diff --git a/chip/npcx/adc_chip.h b/chip/npcx/adc_chip.h
index 9c2de3000d..5f3862829a 100644
--- a/chip/npcx/adc_chip.h
+++ b/chip/npcx/adc_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,7 +8,7 @@
 #ifndef __CROS_EC_ADC_CHIP_H
 #define __CROS_EC_ADC_CHIP_H
 
-#include "adc.h"
+#include "common.h"
 
 /* Minimum and maximum values returned by raw ADC read. */
 #define ADC_READ_MIN 0
@@ -32,7 +32,7 @@ enum npcx_adc_input_channel {
 #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
 	NPCX_ADC_CH10,
 	NPCX_ADC_CH11,
- #endif
+#endif
 	NPCX_ADC_CH_COUNT
 };
 
@@ -45,12 +45,6 @@ struct adc_t {
 	int shift;
 };
 
-/*
- * Boards must provide this list of ADC channel definitions.  This must match
- * the enum adc_channel list provided by the board.
- */
-extern const struct adc_t adc_channels[];
-
 /*
  * Boards may configure a ADC channel for use with thershold interrupts.
  * The threshold levels may be set from 0 to ADC_MAX_VOLT inclusive.
diff --git a/chip/npcx/apm.c b/chip/npcx/apm.c
index 4ab64774c1..b66a77a276 100644
--- a/chip/npcx/apm.c
+++ b/chip/npcx/apm.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,13 +12,12 @@
 #include "wov_chip.h"
 
 static struct apm_config apm_conf;
-static struct apm_auto_gain_config	apm_gain_conf;
-
+static struct apm_auto_gain_config apm_gain_conf;
 
 static uint32_t apm_indirect_reg[][3] = {
-	{(NPCX_APM_BASE_ADDR + 0x034), (NPCX_APM_BASE_ADDR + 0x038)},
-	{(NPCX_APM_BASE_ADDR + 0x04C), (NPCX_APM_BASE_ADDR + 0x050)},
-	{(NPCX_APM_BASE_ADDR + 0x05C), (NPCX_APM_BASE_ADDR + 0x060)}
+	{ (NPCX_APM_BASE_ADDR + 0x034), (NPCX_APM_BASE_ADDR + 0x038) },
+	{ (NPCX_APM_BASE_ADDR + 0x04C), (NPCX_APM_BASE_ADDR + 0x050) },
+	{ (NPCX_APM_BASE_ADDR + 0x05C), (NPCX_APM_BASE_ADDR + 0x060) }
 };
 
 #define APM_CNTRL_REG 0
@@ -37,11 +36,11 @@ static uint8_t apm_read_indirect_data(enum apm_indirect_reg_offset reg_offset,
 {
 	/* Set the indirect access address. */
 	SET_FIELD(REG8(apm_indirect_reg[reg_offset][APM_CNTRL_REG]),
-			NPCX_APM_CONTROL_ADD, indirect_addr);
+		  NPCX_APM_CONTROL_ADD, indirect_addr);
 
 	/* Read command. */
 	CLEAR_BIT(REG8(apm_indirect_reg[reg_offset][APM_CNTRL_REG]),
-			NPCX_APM_CONTROL_LOAD);
+		  NPCX_APM_CONTROL_LOAD);
 
 	/* Get the data. */
 	return REG8(apm_indirect_reg[reg_offset][APM_DATA_REG]);
@@ -57,20 +56,20 @@ static uint8_t apm_read_indirect_data(enum apm_indirect_reg_offset reg_offset,
  * @return  None
  */
 static void apm_write_indirect_data(enum apm_indirect_reg_offset reg_offset,
-				uint8_t indirect_addr, uint8_t value)
+				    uint8_t indirect_addr, uint8_t value)
 {
 	/* Set the data. */
 	REG8(apm_indirect_reg[reg_offset][APM_DATA_REG]) = value;
 
 	/* Set the indirect access address. */
 	SET_FIELD(REG8(apm_indirect_reg[reg_offset][APM_CNTRL_REG]),
-			NPCX_APM_CONTROL_ADD, indirect_addr);
+		  NPCX_APM_CONTROL_ADD, indirect_addr);
 
 	/* Write command. */
 	SET_BIT(REG8(apm_indirect_reg[reg_offset][APM_CNTRL_REG]),
-			NPCX_APM_CONTROL_LOAD);
+		NPCX_APM_CONTROL_LOAD);
 	CLEAR_BIT(REG8(apm_indirect_reg[reg_offset][APM_CNTRL_REG]),
-			NPCX_APM_CONTROL_LOAD);
+		  NPCX_APM_CONTROL_LOAD);
 }
 
 /**
@@ -83,13 +82,13 @@ void apm_set_adc_dmic_config_l(enum apm_dmic_rate rate)
 {
 	if (rate == APM_DMIC_RATE_0_75)
 		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_RATE,
-			APM_DMIC_RATE_3_0);
+			  APM_DMIC_RATE_3_0);
 	else if (rate == APM_DMIC_RATE_1_2)
 		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_RATE,
-			APM_DMIC_RATE_2_4);
+			  APM_DMIC_RATE_2_4);
 	else
 		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_RATE,
-			rate);
+			  rate);
 }
 
 /**
@@ -108,7 +107,7 @@ void apm_set_vad_dmic_rate_l(enum apm_dmic_rate rate)
 	/* Set VAD_0 register. */
 	if (rate == APM_DMIC_RATE_0_75)
 		SET_FIELD(vad_data, NPCX_VAD_0_VAD_DMIC_FREQ,
-				APM_DMIC_RATE_3_0);
+			  APM_DMIC_RATE_3_0);
 	else if (rate == APM_DMIC_RATE_1_2)
 		SET_FIELD(vad_data, NPCX_VAD_0_VAD_DMIC_FREQ,
 			  APM_DMIC_RATE_2_4);
@@ -172,15 +171,15 @@ void apm_init(void)
 	apm_conf.left_chan_gain = 0;
 	apm_conf.right_chan_gain = 0;
 
-	apm_gain_conf.stereo_enable	 = 0;
-	apm_gain_conf.agc_target	 = APM_ADC_MAX_TARGET_LEVEL_19_5;
-	apm_gain_conf.nois_gate_en	 = 0;
+	apm_gain_conf.stereo_enable = 0;
+	apm_gain_conf.agc_target = APM_ADC_MAX_TARGET_LEVEL_19_5;
+	apm_gain_conf.nois_gate_en = 0;
 	apm_gain_conf.nois_gate_thold = APM_MIN_NOISE_GET_THRESHOLD;
-	apm_gain_conf.hold_time	 = APM_HOLD_TIME_128;
-	apm_gain_conf.attack_time	 = APM_GAIN_RAMP_TIME_160;
-	apm_gain_conf.decay_time	 = APM_GAIN_RAMP_TIME_160;
-	apm_gain_conf.gain_max	 = APM_GAIN_VALUE_42_5;
-	apm_gain_conf.gain_min	 = APM_GAIN_VALUE_0_0;
+	apm_gain_conf.hold_time = APM_HOLD_TIME_128;
+	apm_gain_conf.attack_time = APM_GAIN_RAMP_TIME_160;
+	apm_gain_conf.decay_time = APM_GAIN_RAMP_TIME_160;
+	apm_gain_conf.gain_max = APM_GAIN_VALUE_42_5;
+	apm_gain_conf.gain_min = APM_GAIN_VALUE_0_0;
 }
 
 /**
@@ -226,11 +225,11 @@ void apm_enable_vad_interrupt(int enable)
 void apm_adc_wov_enable(int enable)
 {
 	if (enable) {
-		SET_FIELD(NPCX_APM_AICR_ADC,
-				NPCX_APM_AICR_ADC_ADC_AUDIOIF, 0x00);
+		SET_FIELD(NPCX_APM_AICR_ADC, NPCX_APM_AICR_ADC_ADC_AUDIOIF,
+			  0x00);
 	} else {
-		SET_FIELD(NPCX_APM_AICR_ADC,
-				NPCX_APM_AICR_ADC_ADC_AUDIOIF, 0x03);
+		SET_FIELD(NPCX_APM_AICR_ADC, NPCX_APM_AICR_ADC_ADC_AUDIOIF,
+			  0x03);
 	}
 }
 
@@ -244,12 +243,12 @@ void apm_adc_enable(int enable)
 {
 	if (enable) {
 		CLEAR_BIT(NPCX_APM_AICR_ADC, NPCX_APM_AICR_ADC_PD_AICR_ADC);
-		SET_FIELD(NPCX_APM_AICR_ADC,
-				NPCX_APM_AICR_ADC_ADC_AUDIOIF, 0x00);
+		SET_FIELD(NPCX_APM_AICR_ADC, NPCX_APM_AICR_ADC_ADC_AUDIOIF,
+			  0x00);
 	} else {
 		SET_BIT(NPCX_APM_AICR_ADC, NPCX_APM_AICR_ADC_PD_AICR_ADC);
-		SET_FIELD(NPCX_APM_AICR_ADC,
-				NPCX_APM_AICR_ADC_ADC_AUDIOIF, 0x03);
+		SET_FIELD(NPCX_APM_AICR_ADC, NPCX_APM_AICR_ADC_ADC_AUDIOIF,
+			  0x03);
 	}
 }
 
@@ -273,8 +272,8 @@ void apm_adc_set_freq(enum apm_adc_frequency adc_freq)
  * @return  None
  */
 void apm_adc_config(int hpf_enable,
-		enum apm_adc_wind_noise_filter_mode filter_mode,
-		enum apm_adc_frequency adc_freq)
+		    enum apm_adc_wind_noise_filter_mode filter_mode,
+		    enum apm_adc_frequency adc_freq)
 {
 	if (hpf_enable)
 		SET_BIT(NPCX_APM_FCR_ADC, NPCX_APM_FCR_ADC_ADC_HPF);
@@ -491,7 +490,8 @@ void apm_vad_restart(void)
  * @return  EC_ERROR_INVAL or EC_SUCCESS
  */
 enum ec_error_list apm_adc_gain_config(enum apm_adc_gain_coupling gain_coupling,
-		uint8_t left_chan_gain, uint8_t right_chan_gain)
+				       uint8_t left_chan_gain,
+				       uint8_t right_chan_gain)
 {
 	/* Check parameters validity. */
 	if ((left_chan_gain > 0x2B) || (right_chan_gain > 0x2B))
@@ -538,8 +538,8 @@ void apm_auto_gain_cntrl_enable(int enable)
  * @param   gain_cfg - struct of apm auto gain config
  * @return  EC_ERROR_INVAL or EC_SUCCESS
  */
-enum ec_error_list apm_adc_auto_gain_config(
-				struct apm_auto_gain_config *gain_cfg)
+enum ec_error_list
+apm_adc_auto_gain_config(struct apm_auto_gain_config *gain_cfg)
 {
 	uint8_t gain_data = 0;
 
@@ -668,9 +668,8 @@ void apm_set_mode(enum wov_modes wov_mode)
 		break;
 	}
 
-	apm_adc_gain_config(apm_conf.gain_coupling,
-				apm_conf.left_chan_gain,
-				apm_conf.right_chan_gain);
+	apm_adc_gain_config(apm_conf.gain_coupling, apm_conf.left_chan_gain,
+			    apm_conf.right_chan_gain);
 
 	apm_adc_auto_gain_config(&apm_gain_conf);
 
diff --git a/chip/npcx/apm_chip.h b/chip/npcx/apm_chip.h
index ad62538374..9b330321ea 100644
--- a/chip/npcx/apm_chip.h
+++ b/chip/npcx/apm_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,31 +9,27 @@
 #include "common.h"
 
 /* MIX indirect registers. */
-#define APM_INDIRECT_MIX_2_REG      0x02
+#define APM_INDIRECT_MIX_2_REG 0x02
 
 /* ADC_AGC indirect registers. */
-#define APM_INDIRECT_ADC_AGC_0_REG  0x00
-#define APM_INDIRECT_ADC_AGC_1_REG  0x01
-#define APM_INDIRECT_ADC_AGC_2_REG  0x02
-#define APM_INDIRECT_ADC_AGC_3_REG  0x03
-#define APM_INDIRECT_ADC_AGC_4_REG  0x04
+#define APM_INDIRECT_ADC_AGC_0_REG 0x00
+#define APM_INDIRECT_ADC_AGC_1_REG 0x01
+#define APM_INDIRECT_ADC_AGC_2_REG 0x02
+#define APM_INDIRECT_ADC_AGC_3_REG 0x03
+#define APM_INDIRECT_ADC_AGC_4_REG 0x04
 
 /* APM_VAD_REG indirect registers. */
-#define APM_INDIRECT_VAD_0_REG       0x00
-#define APM_INDIRECT_VAD_1_REG       0x01
+#define APM_INDIRECT_VAD_0_REG 0x00
+#define APM_INDIRECT_VAD_1_REG 0x01
 
 /* APM macros. */
-#define APM_IS_IRQ_PENDING    IS_BIT_SET(NPCX_APM_SR, NPCX_APM_SR_IRQ_PEND)
+#define APM_IS_IRQ_PENDING IS_BIT_SET(NPCX_APM_SR, NPCX_APM_SR_IRQ_PEND)
 #define APM_IS_VOICE_ACTIVITY_DETECTED \
 	IS_BIT_SET(NPCX_APM_IFR, NPCX_APM_IFR_VAD_DTC)
-#define APM_CLEAR_VAD_INTERRUPT    SET_BIT(NPCX_APM_IFR, NPCX_APM_IFR_VAD_DTC)
+#define APM_CLEAR_VAD_INTERRUPT SET_BIT(NPCX_APM_IFR, NPCX_APM_IFR_VAD_DTC)
 
 /* Indirect registers. */
-enum apm_indirect_reg_offset {
-	APM_MIX_REG = 0,
-	APM_ADC_AGC_REG,
-	APM_VAD_REG
-};
+enum apm_indirect_reg_offset { APM_MIX_REG = 0, APM_ADC_AGC_REG, APM_VAD_REG };
 
 /* ADC wind noise filter modes. */
 enum apm_adc_wind_noise_filter_mode {
@@ -60,22 +56,22 @@ enum apm_adc_frequency {
 /* DMIC source. */
 enum apm_dmic_src {
 	APM_CURRENT_DMIC_CHANNEL = 0x01, /* Current channel, left or rigth. */
-	APM_AVERAGE_DMIC_CHANNEL = 0x02  /* Average between left & right.   */
+	APM_AVERAGE_DMIC_CHANNEL = 0x02 /* Average between left & right.   */
 };
 
 /* ADC digital microphone rate. */
 enum apm_dmic_rate {
 	/* 3.0, 2.4 & 1.0 must be 0, 1 & 2 respectively */
-	APM_DMIC_RATE_3_0 = 0,   /* 3.0 -3.25 MHz (default). */
-	APM_DMIC_RATE_2_4,       /* 2.4 -2.6 MHz.            */
-	APM_DMIC_RATE_1_0,       /* 1.0 -1.08 MHz.           */
-	APM_DMIC_RATE_1_2,       /* 1.2 MHz.                        */
-	APM_DMIC_RATE_0_75       /* 750 KHz.                 */
+	APM_DMIC_RATE_3_0 = 0, /* 3.0 -3.25 MHz (default). */
+	APM_DMIC_RATE_2_4, /* 2.4 -2.6 MHz.            */
+	APM_DMIC_RATE_1_0, /* 1.0 -1.08 MHz.           */
+	APM_DMIC_RATE_1_2, /* 1.2 MHz.                        */
+	APM_DMIC_RATE_0_75 /* 750 KHz.                 */
 };
 
 /* Digitla mixer output. */
 enum apm_dig_mix {
-	APM_OUT_MIX_NORMAL_INPUT = 0,    /* Default. */
+	APM_OUT_MIX_NORMAL_INPUT = 0, /* Default. */
 	APM_OUT_MIX_CROSS_INPUT,
 	APM_OUT_MIX_MIXED_INPUT,
 	APM_OUT_MIX_NO_INPUT
@@ -341,8 +337,8 @@ void apm_adc_set_freq(enum apm_adc_frequency adc_freq);
  * @return  None
  */
 void apm_adc_config(int hpf_enable,
-		enum apm_adc_wind_noise_filter_mode filter_mode,
-		enum apm_adc_frequency adc_freq);
+		    enum apm_adc_wind_noise_filter_mode filter_mode,
+		    enum apm_adc_frequency adc_freq);
 
 /**
  * Enables/Disables Digital Microphone.
@@ -360,7 +356,7 @@ void apm_dmic_enable(int enable);
  * @return  None
  */
 void apm_digital_mixer_config(enum apm_dig_mix mix_left,
-		enum apm_dig_mix mix_right);
+			      enum apm_dig_mix mix_right);
 
 /**
  * Enables/Disables the VAD functionality.
@@ -422,7 +418,8 @@ void apm_vad_restart(void);
  * @return  EC_ERROR_INVAL or EC_SUCCESS
  */
 enum ec_error_list apm_adc_gain_config(enum apm_adc_gain_coupling gain_coupling,
-			uint8_t left_chan_gain, uint8_t right_chan_gain);
+				       uint8_t left_chan_gain,
+				       uint8_t right_chan_gain);
 
 /**
  * Enables/Disables the automatic gain.
@@ -438,8 +435,8 @@ void apm_auto_gain_cntrl_enable(int enable);
  * @param   gain_cfg - struct of apm auto gain config
  * @return  EC_ERROR_INVAL or EC_SUCCESS
  */
-enum ec_error_list apm_adc_auto_gain_config(
-				struct apm_auto_gain_config *gain_cfg);
+enum ec_error_list
+apm_adc_auto_gain_config(struct apm_auto_gain_config *gain_cfg);
 
 /**
  * Sets APM mode (enables & disables APN sub modules accordingly
diff --git a/chip/npcx/audio_codec_dmic.c b/chip/npcx/audio_codec_dmic.c
index e242a8b2d2..7e1bfa9bce 100644
--- a/chip/npcx/audio_codec_dmic.c
+++ b/chip/npcx/audio_codec_dmic.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/npcx/audio_codec_i2s_rx.c b/chip/npcx/audio_codec_i2s_rx.c
index 12c4173048..02224be437 100644
--- a/chip/npcx/audio_codec_i2s_rx.c
+++ b/chip/npcx/audio_codec_i2s_rx.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,7 +8,7 @@
 #include "ec_commands.h"
 #include "wov_chip.h"
 
-#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ##args)
 
 int audio_codec_i2s_rx_enable(void)
 {
diff --git a/chip/npcx/build.mk b/chip/npcx/build.mk
index 4409c33c5d..cbedd2bf68 100644
--- a/chip/npcx/build.mk
+++ b/chip/npcx/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
+# Copyright 2014 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -9,7 +9,10 @@
 # NPCX SoC has a Cortex-M4F ARM core
 CORE:=cortex-m
 # Allow the full Cortex-M4 instruction set
-CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
+CFLAGS_CPU+=-mcpu=cortex-m4
+
+# Disable overlapping section warning that linker emits due to NPCX_RO_HEADER.
+LDFLAGS_EXTRA+=-Wl,--no-check-sections
 
 # Assign default CHIP_FAMILY as npcx5 for old boards used npcx5 series
 ifeq ($(CHIP_FAMILY),)
@@ -30,15 +33,16 @@ chip-$(CONFIG_FANS)+=fan.o
 chip-$(CONFIG_FLASH_PHYSICAL)+=flash.o
 chip-$(CONFIG_I2C)+=i2c.o i2c-$(CHIP_FAMILY).o
 chip-$(CONFIG_HOSTCMD_X86)+=lpc.o
-chip-$(CONFIG_HOSTCMD_ESPI)+=espi.o
+chip-$(CONFIG_HOST_INTERFACE_ESPI)+=espi.o
 chip-$(CONFIG_PECI)+=peci.o
-chip-$(CONFIG_HOSTCMD_SPS)+=shi.o
-chip-$(CONFIG_CEC)+=cec.o
+chip-$(CONFIG_HOST_INTERFACE_SHI)+=shi.o
+chip-$(CONFIG_CEC_BITBANG)+=cec_bitbang.o
 # pwm functions are implemented with the fan functions
 chip-$(CONFIG_PWM)+=pwm.o
 chip-$(CONFIG_SPI)+=spi.o
+chip-$(CONFIG_RNG)+=trng.o
 chip-$(CONFIG_WATCHDOG)+=watchdog.o
-ifndef CONFIG_KEYBOARD_NOT_RAW
+ifndef CONFIG_KEYBOARD_DISCRETE
 chip-$(HAS_TASK_KEYSCAN)+=keyboard_raw.o
 endif
 
@@ -48,6 +52,8 @@ ifneq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),npcx5 npcx7))
 chip-y+=lct.o
 endif
 
+chip-$(CONFIG_SHA256_HW_ACCELERATE)+=sha256_chip.o
+
 # spi monitor program fw for openocd and UUT(UART Update Tool)
 npcx-monitor-fw=chip/npcx/spiflashfw/npcx_monitor
 npcx-monitor-fw-bin=${out}/$(npcx-monitor-fw).bin
@@ -67,13 +73,13 @@ show_esct_cmd=$(if $(V),,echo '  ECST   ' $(subst $(out)/,,$@) ; )
 # size when the CONFIG_CHIP_INIT_ROM_REGION is used. Note that the -fwlen
 # parameter for the ecst utility must be in hex.
 cmd_fwlen=$(shell awk '\
-  /__flash_used =/ {flash_used = strtonum($$1)} \
+  /__flash_used/ {flash_used = strtonum("0x" $$1)} \
   END {printf ("%x", flash_used)}' $(1))
 
 # ECST options for header
 bld_ecst=${out}/util/ecst -chip $(CHIP_VARIANT) \
 	-usearmrst -mode bt -ph -i $(1) -o $(2) -nohcrc -nofcrc -flashsize 8 \
-	-fwlen $(call cmd_fwlen, $(patsubst %.flat,%.map,$(2))) \
+	-fwlen $(call cmd_fwlen, $(patsubst %.flat,%.smap,$(2))) \
 	-spimaxclk 50 -spireadmode dual 1> /dev/null
 
 # Replace original one with the flat file including header
@@ -86,5 +92,5 @@ cmd_ecst=$(show_esct_cmd)$(call moveflat,$@,$@.tmp);$(call bld_ecst,$@.tmp,$@)
 cmd_org_ec_elf_to_flat = $(OBJCOPY) --set-section-flags .roshared=share \
                          -O binary $(patsubst %.flat,%.elf,$@) $@
 cmd_npcx_ro_elf_to_flat=$(cmd_org_ec_elf_to_flat);$(cmd_ecst)
-cmd_ec_elf_to_flat = $(if $(filter $(out)/RO/ec.RO.flat, $@), \
+cmd_ec_elf_to_flat = $(if $(filter %.RO.flat, $@), \
                      $(cmd_npcx_ro_elf_to_flat), $(cmd_org_ec_elf_to_flat) )
diff --git a/chip/npcx/cec.c b/chip/npcx/cec.c
deleted file mode 100644
index 76fbf8279f..0000000000
--- a/chip/npcx/cec.c
+++ /dev/null
@@ -1,1040 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "atomic.h"
-#include "cec.h"
-#include "clock_chip.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "mkbp_event.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#if !(DEBUG_CEC)
-#define CPRINTF(...)
-#define CPRINTS(...)
-#else
-#define CPRINTF(format, args...) cprintf(CC_CEC, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CEC, format, ## args)
-#endif
-
-/* Time in us to timer clock ticks */
-#define APB1_TICKS(t) ((t) * apb1_freq_div_10k / 100)
-#if DEBUG_CEC
-/* Timer clock ticks to us */
-#define APB1_US(ticks) (100*(ticks)/apb1_freq_div_10k)
-#endif
-
-/* Notification from interrupt to CEC task that data has been received */
-#define TASK_EVENT_RECEIVED_DATA TASK_EVENT_CUSTOM_BIT(0)
-
-/* CEC broadcast address. Also the highest possible CEC address */
-#define CEC_BROADCAST_ADDR 15
-
-/* Address to indicate that no logical address has been set */
-#define CEC_UNREGISTERED_ADDR 255
-
-/*
- * The CEC specification requires at least one and a maximum of
- * five resends attempts
- */
-#define CEC_MAX_RESENDS 5
-
-/*
- * Free time timing (us). Our free-time is calculated from the end of
- * the last bit (not from the start). We compensate by having one
- * free-time period less than in the spec.
- */
-#define NOMINAL_BIT_TICKS APB1_TICKS(2400)
- /* Resend */
-#define FREE_TIME_RS_TICKS (2 * (NOMINAL_BIT_TICKS))
-/* New initiator */
-#define FREE_TIME_NI_TICKS (4 * (NOMINAL_BIT_TICKS))
-/* Present initiator */
-#define FREE_TIME_PI_TICKS (6 * (NOMINAL_BIT_TICKS))
-
-/* Start bit timing */
-#define START_BIT_LOW_TICKS		APB1_TICKS(3700)
-#define START_BIT_MIN_LOW_TICKS		APB1_TICKS(3500)
-#define START_BIT_MAX_LOW_TICKS		APB1_TICKS(3900)
-#define START_BIT_HIGH_TICKS		APB1_TICKS(800)
-#define START_BIT_MIN_DURATION_TICKS	APB1_TICKS(4300)
-#define START_BIT_MAX_DURATION_TICKS	APB1_TICKS(5700)
-
-/* Data bit timing */
-#define DATA_ZERO_LOW_TICKS		APB1_TICKS(1500)
-#define DATA_ZERO_MIN_LOW_TICKS		APB1_TICKS(1300)
-#define DATA_ZERO_MAX_LOW_TICKS		APB1_TICKS(1700)
-#define DATA_ZERO_HIGH_TICKS		APB1_TICKS(900)
-#define DATA_ZERO_MIN_DURATION_TICKS	APB1_TICKS(2050)
-#define DATA_ZERO_MAX_DURATION_TICKS	APB1_TICKS(2750)
-
-#define DATA_ONE_LOW_TICKS		APB1_TICKS(600)
-#define DATA_ONE_MIN_LOW_TICKS		APB1_TICKS(400)
-#define DATA_ONE_MAX_LOW_TICKS		APB1_TICKS(800)
-#define DATA_ONE_HIGH_TICKS		APB1_TICKS(1800)
-#define DATA_ONE_MIN_DURATION_TICKS	APB1_TICKS(2050)
-#define DATA_ONE_MAX_DURATION_TICKS	APB1_TICKS(2750)
-
-/* Time from low that it should be safe to sample an ACK */
-#define NOMINAL_SAMPLE_TIME_TICKS APB1_TICKS(1050)
-
-#define DATA_TIME(type, data) ((data) ? (DATA_ONE_ ## type ## _TICKS) : \
-					(DATA_ZERO_ ## type ## _TICKS))
-#define DATA_HIGH(data) DATA_TIME(HIGH, data)
-#define DATA_LOW(data) DATA_TIME(LOW, data)
-
-/*
- * Number of short pulses seen before the debounce logic goes into ignoring
- * the bus for DEBOUNCE_WAIT_LONG instead of DEBOUNCE_WAIT_SHORT
- */
-#define DEBOUNCE_CUTOFF 3
-
-/* The limit how short a start-bit can be to trigger debounce logic */
-#define DEBOUNCE_LIMIT_TICKS APB1_TICKS(200)
-/* The time we ignore the bus for the first three debounce cases */
-#define DEBOUNCE_WAIT_SHORT_TICKS APB1_TICKS(100)
-/* The time we ignore the bus after the three initial debounce cases */
-#define DEBOUNCE_WAIT_LONG_TICKS APB1_TICKS(500)
-
-/*
- * The variance in timing we allow outside of the CEC specification for
- * incoming signals. Our measurements aren't 100% accurate either, so this
- * gives some robustness.
- */
-#define VALID_TOLERANCE_TICKS APB1_TICKS(100)
-
-/*
- * Defines used for setting capture timers to a point where we are
- * sure that if we get a timeout, something is wrong.
- */
-#define CAP_START_LOW_TICKS (START_BIT_MAX_LOW_TICKS + VALID_TOLERANCE_TICKS)
-#define CAP_START_HIGH_TICKS (START_BIT_MAX_DURATION_TICKS - \
-			      START_BIT_MIN_LOW_TICKS +	\
-			      VALID_TOLERANCE_TICKS)
-#define CAP_DATA_LOW_TICKS (DATA_ZERO_MAX_LOW_TICKS + VALID_TOLERANCE_TICKS)
-#define CAP_DATA_HIGH_TICKS (DATA_ONE_MAX_DURATION_TICKS - \
-			     DATA_ONE_MIN_LOW_TICKS + \
-			     VALID_TOLERANCE_TICKS)
-
-#define VALID_TIME(type, bit, t) \
-	((t) >= ((bit ## _MIN_ ## type ## _TICKS) - (VALID_TOLERANCE_TICKS)) \
-	 && (t) <=  (bit ##_MAX_ ## type ## _TICKS) + (VALID_TOLERANCE_TICKS))
-#define VALID_LOW(bit, t) VALID_TIME(LOW, bit, t)
-#define VALID_HIGH(bit, low_time, high_time) \
-	(((low_time) + (high_time) <= \
-	  bit ## _MAX_DURATION_TICKS + VALID_TOLERANCE_TICKS) && \
-	 ((low_time) + (high_time) >= \
-	  bit ## _MIN_DURATION_TICKS - VALID_TOLERANCE_TICKS))
-#define VALID_DATA_HIGH(data, low_time, high_time) ((data) ? \
-				VALID_HIGH(DATA_ONE, low_time, high_time) : \
-				VALID_HIGH(DATA_ZERO, low_time, high_time))
-
-/*
- * CEC state machine states. Each state typically takes action on entry and
- * timeouts. INITIATIOR states are used for sending, FOLLOWER states are used
- *  for receiving.
- */
-enum cec_state {
-	CEC_STATE_DISABLED = 0,
-	CEC_STATE_IDLE,
-	CEC_STATE_INITIATOR_FREE_TIME,
-	CEC_STATE_INITIATOR_START_LOW,
-	CEC_STATE_INITIATOR_START_HIGH,
-	CEC_STATE_INITIATOR_HEADER_INIT_LOW,
-	CEC_STATE_INITIATOR_HEADER_INIT_HIGH,
-	CEC_STATE_INITIATOR_HEADER_DEST_LOW,
-	CEC_STATE_INITIATOR_HEADER_DEST_HIGH,
-	CEC_STATE_INITIATOR_DATA_LOW,
-	CEC_STATE_INITIATOR_DATA_HIGH,
-	CEC_STATE_INITIATOR_EOM_LOW,
-	CEC_STATE_INITIATOR_EOM_HIGH,
-	CEC_STATE_INITIATOR_ACK_LOW,
-	CEC_STATE_INITIATOR_ACK_HIGH,
-	CEC_STATE_INITIATOR_ACK_VERIFY,
-	CEC_STATE_FOLLOWER_START_LOW,
-	CEC_STATE_FOLLOWER_START_HIGH,
-	CEC_STATE_FOLLOWER_DEBOUNCE,
-	CEC_STATE_FOLLOWER_HEADER_INIT_LOW,
-	CEC_STATE_FOLLOWER_HEADER_INIT_HIGH,
-	CEC_STATE_FOLLOWER_HEADER_DEST_LOW,
-	CEC_STATE_FOLLOWER_HEADER_DEST_HIGH,
-	CEC_STATE_FOLLOWER_EOM_LOW,
-	CEC_STATE_FOLLOWER_EOM_HIGH,
-	CEC_STATE_FOLLOWER_ACK_LOW,
-	CEC_STATE_FOLLOWER_ACK_VERIFY,
-	CEC_STATE_FOLLOWER_ACK_FINISH,
-	CEC_STATE_FOLLOWER_DATA_LOW,
-	CEC_STATE_FOLLOWER_DATA_HIGH,
-};
-
-/* Edge to trigger capture timer interrupt on */
-enum cap_edge {
-	CAP_EDGE_FALLING,
-	CAP_EDGE_RISING
-};
-
-/* Receive buffer and states */
-struct cec_rx {
-	/*
-	 * The current incoming message being parsed. Copied to
-	 * receive queue upon completion
-	 */
-	struct cec_msg_transfer transfer;
-	/* End of Message received from source? */
-	uint8_t eom;
-	/* A follower NAK:ed a broadcast transfer */
-	uint8_t broadcast_nak;
-	/*
-	 * Keep track of pulse low time to be able to verify
-	 * pulse duration
-	 */
-	int low_ticks;
-	/* Number of too short pulses seen in a row */
-	int debounce_count;
-};
-
-/* Transfer buffer and states */
-struct cec_tx {
-	/* Outgoing message */
-	struct cec_msg_transfer transfer;
-	/* Message length */
-	uint8_t len;
-	/* Number of resends attempted in current send */
-	uint8_t resends;
-	/* Acknowledge received from sink? */
-	uint8_t ack;
-	/*
-	 * When sending multiple concurrent frames,
-	 * the free-time is slightly higher
-	 */
-	int present_initiator;
-};
-
-/* Single state for CEC. We are INITIATOR, FOLLOWER or IDLE */
-static enum cec_state cec_state;
-
-/* Parameters and buffers for follower (receiver) state */
-static struct cec_rx cec_rx;
-
-/* Queue of completed incoming CEC messages */
-static struct cec_rx_queue cec_rx_queue;
-
-/* Parameters and buffer for initiator (sender) state */
-static struct cec_tx cec_tx;
-
-/*
- * Time between interrupt triggered and the next timer was
- * set when measuring pulse width
- */
-static int cap_delay;
-
-/* Value charged into the capture timer on last capture start */
-static int cap_charge;
-
-/*
- * CEC address of ourself. We ack incoming packages on this address.
- * However, the AP is responsible for writing the initiator address
- * on writes. UINT32_MAX means means that the address hasn't been
- * set by the AP yet.
- */
-static uint8_t cec_addr = UINT8_MAX;
-
-/* Events to send to AP */
-static uint32_t cec_events;
-
-/* APB1 frequency. Store divided by 10k to avoid some runtime divisions */
-static uint32_t apb1_freq_div_10k;
-
-static void send_mkbp_event(uint32_t event)
-{
-	deprecated_atomic_or(&cec_events, event);
-	mkbp_send_event(EC_MKBP_EVENT_CEC_EVENT);
-}
-
-static void tmr_cap_start(enum cap_edge edge, int timeout)
-{
-	int mdl = NPCX_MFT_MODULE_1;
-
-	/* Select edge to trigger capture on */
-	UPDATE_BIT(NPCX_TMCTRL(mdl), NPCX_TMCTRL_TAEDG,
-		   edge == CAP_EDGE_RISING);
-
-	/*
-	 * Set capture timeout. If we don't have a timeout, we
-	 * turn the timeout interrupt off and only care about
-	 * the edge change.
-	 */
-	if (timeout > 0) {
-		/*
-		 * Store the time it takes from the interrupts starts to when we
-		 * actually get here. This part of the pulse-width needs to be
-		 * taken into account
-		 */
-		cap_delay = (0xffff - NPCX_TCNT1(mdl));
-		cap_charge = timeout - cap_delay;
-		NPCX_TCNT1(mdl) = cap_charge;
-		SET_BIT(NPCX_TIEN(mdl), NPCX_TIEN_TCIEN);
-	} else {
-		CLEAR_BIT(NPCX_TIEN(mdl), NPCX_TIEN_TCIEN);
-		NPCX_TCNT1(mdl) = 0;
-	}
-
-	/* Clear out old events */
-	SET_BIT(NPCX_TECLR(mdl), NPCX_TECLR_TACLR);
-	SET_BIT(NPCX_TECLR(mdl), NPCX_TECLR_TCCLR);
-	NPCX_TCRA(mdl) = 0;
-	/* Start the capture timer */
-	SET_FIELD(NPCX_TCKC(mdl), NPCX_TCKC_C1CSEL_FIELD, 1);
-}
-
-static void tmr_cap_stop(void)
-{
-	int mdl = NPCX_MFT_MODULE_1;
-
-	CLEAR_BIT(NPCX_TIEN(mdl), NPCX_TIEN_TCIEN);
-	SET_FIELD(NPCX_TCKC(mdl), NPCX_TCKC_C1CSEL_FIELD, 0);
-}
-
-static int tmr_cap_get(void)
-{
-	int mdl = NPCX_MFT_MODULE_1;
-
-	return (cap_charge + cap_delay - NPCX_TCRA(mdl));
-}
-
-static void tmr_oneshot_start(int timeout)
-{
-	int mdl = NPCX_MFT_MODULE_1;
-
-	NPCX_TCNT1(mdl) = timeout;
-	SET_FIELD(NPCX_TCKC(mdl), NPCX_TCKC_C1CSEL_FIELD, 1);
-}
-
-static void tmr2_start(int timeout)
-{
-	int mdl = NPCX_MFT_MODULE_1;
-
-	NPCX_TCNT2(mdl) = timeout;
-	SET_FIELD(NPCX_TCKC(mdl), NPCX_TCKC_C2CSEL_FIELD, 1);
-}
-
-static void tmr2_stop(void)
-{
-	int mdl = NPCX_MFT_MODULE_1;
-
-	SET_FIELD(NPCX_TCKC(mdl), NPCX_TCKC_C2CSEL_FIELD, 0);
-}
-
-void enter_state(enum cec_state new_state)
-{
-	int gpio = -1, timeout = -1;
-	enum cap_edge cap_edge = -1;
-	uint8_t addr;
-
-	cec_state = new_state;
-	switch (new_state) {
-	case CEC_STATE_DISABLED:
-		gpio = 1;
-		memset(&cec_rx, 0, sizeof(struct cec_rx));
-		memset(&cec_tx, 0, sizeof(struct cec_tx));
-		memset(&cec_rx_queue, 0, sizeof(struct cec_rx_queue));
-		cap_charge = 0;
-		cap_delay = 0;
-		cec_events = 0;
-		break;
-	case CEC_STATE_IDLE:
-		cec_tx.transfer.bit = 0;
-		cec_tx.transfer.byte = 0;
-		cec_rx.transfer.bit = 0;
-		cec_rx.transfer.byte = 0;
-		if (cec_tx.len > 0) {
-			/* Execute a postponed send */
-			enter_state(CEC_STATE_INITIATOR_FREE_TIME);
-		} else {
-			/* Wait for incoming command */
-			gpio = 1;
-			cap_edge = CAP_EDGE_FALLING;
-			timeout = 0;
-		}
-		break;
-	case CEC_STATE_INITIATOR_FREE_TIME:
-		gpio = 1;
-		cap_edge = CAP_EDGE_FALLING;
-		if (cec_tx.resends)
-			timeout = FREE_TIME_RS_TICKS;
-		else if (cec_tx.present_initiator)
-			timeout = FREE_TIME_PI_TICKS;
-		else
-			timeout = FREE_TIME_NI_TICKS;
-		break;
-	case CEC_STATE_INITIATOR_START_LOW:
-		cec_tx.present_initiator = 1;
-		cec_tx.transfer.bit = 0;
-		cec_tx.transfer.byte = 0;
-		gpio = 0;
-		timeout = START_BIT_LOW_TICKS;
-		break;
-	case CEC_STATE_INITIATOR_START_HIGH:
-		gpio = 1;
-		cap_edge = CAP_EDGE_FALLING;
-		timeout = START_BIT_HIGH_TICKS;
-		break;
-	case CEC_STATE_INITIATOR_HEADER_INIT_LOW:
-	case CEC_STATE_INITIATOR_HEADER_DEST_LOW:
-	case CEC_STATE_INITIATOR_DATA_LOW:
-		gpio = 0;
-		timeout = DATA_LOW(cec_transfer_get_bit(&cec_tx.transfer));
-		break;
-	case CEC_STATE_INITIATOR_HEADER_INIT_HIGH:
-		gpio = 1;
-		cap_edge = CAP_EDGE_FALLING;
-		timeout = DATA_HIGH(cec_transfer_get_bit(&cec_tx.transfer));
-		break;
-	case CEC_STATE_INITIATOR_HEADER_DEST_HIGH:
-	case CEC_STATE_INITIATOR_DATA_HIGH:
-		gpio = 1;
-		timeout = DATA_HIGH(cec_transfer_get_bit(&cec_tx.transfer));
-		break;
-	case CEC_STATE_INITIATOR_EOM_LOW:
-		gpio = 0;
-		timeout = DATA_LOW(cec_transfer_is_eom(&cec_tx.transfer,
-						       cec_tx.len));
-		break;
-	case CEC_STATE_INITIATOR_EOM_HIGH:
-		gpio = 1;
-		timeout = DATA_HIGH(cec_transfer_is_eom(&cec_tx.transfer,
-							cec_tx.len));
-		break;
-	case CEC_STATE_INITIATOR_ACK_LOW:
-		gpio = 0;
-		timeout = DATA_LOW(1);
-		break;
-	case CEC_STATE_INITIATOR_ACK_HIGH:
-		gpio = 1;
-		/* Aim for the middle of the safe sample time */
-		timeout = (DATA_ONE_LOW_TICKS + DATA_ZERO_LOW_TICKS)/2 -
-							DATA_ONE_LOW_TICKS;
-		break;
-	case CEC_STATE_INITIATOR_ACK_VERIFY:
-		cec_tx.ack = !gpio_get_level(CEC_GPIO_OUT);
-		if ((cec_tx.transfer.buf[0] & 0x0f) == CEC_BROADCAST_ADDR) {
-			/*
-			 * We are sending a broadcast. Any follower can
-			 * can NAK a broadcast message the same way they
-			 * would ACK a direct message
-			 */
-			cec_tx.ack = !cec_tx.ack;
-		}
-		/*
-		 * We are at the safe sample time. Wait
-		 * until the end of this bit
-		 */
-		timeout = NOMINAL_BIT_TICKS - NOMINAL_SAMPLE_TIME_TICKS;
-		break;
-	case CEC_STATE_FOLLOWER_START_LOW:
-		cec_tx.present_initiator = 0;
-		cap_edge = CAP_EDGE_RISING;
-		timeout = CAP_START_LOW_TICKS;
-		break;
-	case CEC_STATE_FOLLOWER_START_HIGH:
-		cec_rx.debounce_count = 0;
-		cap_edge = CAP_EDGE_FALLING;
-		timeout = CAP_START_HIGH_TICKS;
-		break;
-	case CEC_STATE_FOLLOWER_DEBOUNCE:
-		if (cec_rx.debounce_count >= DEBOUNCE_CUTOFF) {
-			timeout = DEBOUNCE_WAIT_LONG_TICKS;
-		} else {
-			timeout = DEBOUNCE_WAIT_SHORT_TICKS;
-			cec_rx.debounce_count++;
-		}
-		break;
-	case CEC_STATE_FOLLOWER_HEADER_INIT_LOW:
-	case CEC_STATE_FOLLOWER_HEADER_DEST_LOW:
-	case CEC_STATE_FOLLOWER_EOM_LOW:
-		cap_edge = CAP_EDGE_RISING;
-		timeout = CAP_DATA_LOW_TICKS;
-		break;
-	case CEC_STATE_FOLLOWER_HEADER_INIT_HIGH:
-	case CEC_STATE_FOLLOWER_HEADER_DEST_HIGH:
-	case CEC_STATE_FOLLOWER_EOM_HIGH:
-		cap_edge = CAP_EDGE_FALLING;
-		timeout = CAP_DATA_HIGH_TICKS;
-		break;
-	case CEC_STATE_FOLLOWER_ACK_LOW:
-		addr = cec_rx.transfer.buf[0] & 0x0f;
-		if (addr == cec_addr) {
-			/* Destination is our address */
-			gpio = 0;
-			timeout = NOMINAL_SAMPLE_TIME_TICKS;
-		} else if (addr == CEC_BROADCAST_ADDR) {
-			/* Don't ack broadcast or packets which destination
-			 * are us, but continue reading
-			 */
-			timeout = NOMINAL_SAMPLE_TIME_TICKS;
-		}
-		break;
-	case CEC_STATE_FOLLOWER_ACK_VERIFY:
-		/*
-		 * We are at safe sample time. A broadcast frame is considered
-		 * lost if any follower pulls the line low
-		 */
-		if ((cec_rx.transfer.buf[0] & 0x0f) == CEC_BROADCAST_ADDR)
-			cec_rx.broadcast_nak = !gpio_get_level(CEC_GPIO_OUT);
-		else
-			cec_rx.broadcast_nak = 0;
-
-		/*
-		 * We release the ACK at the end of data zero low
-		 * period (ACK is technically a zero).
-		 */
-		timeout = DATA_ZERO_LOW_TICKS - NOMINAL_SAMPLE_TIME_TICKS;
-		break;
-	case CEC_STATE_FOLLOWER_ACK_FINISH:
-		gpio = 1;
-		if (cec_rx.eom || cec_rx.transfer.byte >= MAX_CEC_MSG_LEN) {
-			addr = cec_rx.transfer.buf[0] & 0x0f;
-			if (addr == cec_addr || addr == CEC_BROADCAST_ADDR) {
-				task_set_event(TASK_ID_CEC,
-					       TASK_EVENT_RECEIVED_DATA, 0);
-			}
-			timeout = DATA_ZERO_HIGH_TICKS;
-		} else {
-			cap_edge = CAP_EDGE_FALLING;
-			timeout = CAP_DATA_HIGH_TICKS;
-		}
-		break;
-	case CEC_STATE_FOLLOWER_DATA_LOW:
-		cap_edge = CAP_EDGE_RISING;
-		timeout = CAP_DATA_LOW_TICKS;
-		break;
-	case CEC_STATE_FOLLOWER_DATA_HIGH:
-		cap_edge = CAP_EDGE_FALLING;
-		timeout = CAP_DATA_HIGH_TICKS;
-		break;
-	/* No default case, since all states must be handled explicitly */
-	}
-
-	if (gpio >= 0)
-		gpio_set_level(CEC_GPIO_OUT, gpio);
-	if (timeout >= 0) {
-		if (cap_edge >= 0)
-			tmr_cap_start(cap_edge, timeout);
-		else
-			tmr_oneshot_start(timeout);
-	}
-}
-
-static void cec_event_timeout(void)
-{
-	switch (cec_state) {
-	case CEC_STATE_DISABLED:
-	case CEC_STATE_IDLE:
-		break;
-	case CEC_STATE_INITIATOR_FREE_TIME:
-		enter_state(CEC_STATE_INITIATOR_START_LOW);
-		break;
-	case CEC_STATE_INITIATOR_START_LOW:
-		enter_state(CEC_STATE_INITIATOR_START_HIGH);
-		break;
-	case CEC_STATE_INITIATOR_START_HIGH:
-		enter_state(CEC_STATE_INITIATOR_HEADER_INIT_LOW);
-		break;
-	case CEC_STATE_INITIATOR_HEADER_INIT_LOW:
-		enter_state(CEC_STATE_INITIATOR_HEADER_INIT_HIGH);
-		break;
-	case CEC_STATE_INITIATOR_HEADER_INIT_HIGH:
-		cec_transfer_inc_bit(&cec_tx.transfer);
-		if (cec_tx.transfer.bit == 4)
-			enter_state(CEC_STATE_INITIATOR_HEADER_DEST_LOW);
-		else
-			enter_state(CEC_STATE_INITIATOR_HEADER_INIT_LOW);
-		break;
-	case CEC_STATE_INITIATOR_HEADER_DEST_LOW:
-		enter_state(CEC_STATE_INITIATOR_HEADER_DEST_HIGH);
-		break;
-	case CEC_STATE_INITIATOR_HEADER_DEST_HIGH:
-		cec_transfer_inc_bit(&cec_tx.transfer);
-		if (cec_tx.transfer.byte == 1)
-			enter_state(CEC_STATE_INITIATOR_EOM_LOW);
-		else
-			enter_state(CEC_STATE_INITIATOR_HEADER_DEST_LOW);
-		break;
-	case CEC_STATE_INITIATOR_EOM_LOW:
-		enter_state(CEC_STATE_INITIATOR_EOM_HIGH);
-		break;
-	case CEC_STATE_INITIATOR_EOM_HIGH:
-		enter_state(CEC_STATE_INITIATOR_ACK_LOW);
-		break;
-	case CEC_STATE_INITIATOR_ACK_LOW:
-		enter_state(CEC_STATE_INITIATOR_ACK_HIGH);
-		break;
-	case CEC_STATE_INITIATOR_ACK_HIGH:
-		enter_state(CEC_STATE_INITIATOR_ACK_VERIFY);
-		break;
-	case CEC_STATE_INITIATOR_ACK_VERIFY:
-		if (cec_tx.ack) {
-			if (!cec_transfer_is_eom(&cec_tx.transfer,
-						 cec_tx.len)) {
-				/* More data in this frame */
-				enter_state(CEC_STATE_INITIATOR_DATA_LOW);
-			} else {
-				/* Transfer completed successfully */
-				cec_tx.len = 0;
-				cec_tx.resends = 0;
-				enter_state(CEC_STATE_IDLE);
-				send_mkbp_event(EC_MKBP_CEC_SEND_OK);
-			}
-		} else {
-			if (cec_tx.resends < CEC_MAX_RESENDS) {
-				/* Resend */
-				cec_tx.resends++;
-				enter_state(CEC_STATE_INITIATOR_FREE_TIME);
-			} else {
-				/* Transfer failed */
-				cec_tx.len = 0;
-				cec_tx.resends = 0;
-				enter_state(CEC_STATE_IDLE);
-				send_mkbp_event(EC_MKBP_CEC_SEND_FAILED);
-			}
-		}
-		break;
-	case CEC_STATE_INITIATOR_DATA_LOW:
-		enter_state(CEC_STATE_INITIATOR_DATA_HIGH);
-		break;
-	case CEC_STATE_INITIATOR_DATA_HIGH:
-		cec_transfer_inc_bit(&cec_tx.transfer);
-		if (cec_tx.transfer.bit == 0)
-			enter_state(CEC_STATE_INITIATOR_EOM_LOW);
-		else
-			enter_state(CEC_STATE_INITIATOR_DATA_LOW);
-		break;
-	case CEC_STATE_FOLLOWER_ACK_LOW:
-		enter_state(CEC_STATE_FOLLOWER_ACK_VERIFY);
-		break;
-	case CEC_STATE_FOLLOWER_ACK_VERIFY:
-		if (cec_rx.broadcast_nak)
-			enter_state(CEC_STATE_IDLE);
-		else
-			enter_state(CEC_STATE_FOLLOWER_ACK_FINISH);
-		break;
-	case CEC_STATE_FOLLOWER_START_LOW:
-	case CEC_STATE_FOLLOWER_START_HIGH:
-	case CEC_STATE_FOLLOWER_DEBOUNCE:
-	case CEC_STATE_FOLLOWER_HEADER_INIT_LOW:
-	case CEC_STATE_FOLLOWER_HEADER_INIT_HIGH:
-	case CEC_STATE_FOLLOWER_HEADER_DEST_LOW:
-	case CEC_STATE_FOLLOWER_HEADER_DEST_HIGH:
-	case CEC_STATE_FOLLOWER_EOM_LOW:
-	case CEC_STATE_FOLLOWER_EOM_HIGH:
-	case CEC_STATE_FOLLOWER_ACK_FINISH:
-	case CEC_STATE_FOLLOWER_DATA_LOW:
-	case CEC_STATE_FOLLOWER_DATA_HIGH:
-		enter_state(CEC_STATE_IDLE);
-		break;
-
-	}
-}
-
-static void cec_event_cap(void)
-{
-	int t;
-	int data;
-
-	switch (cec_state) {
-	case CEC_STATE_IDLE:
-		/* A falling edge during idle, likely a start bit */
-		enter_state(CEC_STATE_FOLLOWER_START_LOW);
-		break;
-	case CEC_STATE_INITIATOR_FREE_TIME:
-	case CEC_STATE_INITIATOR_START_HIGH:
-	case CEC_STATE_INITIATOR_HEADER_INIT_HIGH:
-		/*
-		 * A falling edge during free-time, postpone
-		 * this send and listen
-		 */
-		cec_tx.transfer.bit = 0;
-		cec_tx.transfer.byte = 0;
-		enter_state(CEC_STATE_FOLLOWER_START_LOW);
-		break;
-	case CEC_STATE_FOLLOWER_START_LOW:
-		/* Rising edge of start bit, validate low time */
-		t =  tmr_cap_get();
-		if (VALID_LOW(START_BIT, t)) {
-			cec_rx.low_ticks = t;
-			enter_state(CEC_STATE_FOLLOWER_START_HIGH);
-		} else if (t < DEBOUNCE_LIMIT_TICKS) {
-			/* Wait a bit if start-pulses are really short */
-			enter_state(CEC_STATE_FOLLOWER_DEBOUNCE);
-		} else {
-			enter_state(CEC_STATE_IDLE);
-		}
-		break;
-	case CEC_STATE_FOLLOWER_START_HIGH:
-		if (VALID_HIGH(START_BIT, cec_rx.low_ticks, tmr_cap_get()))
-			enter_state(CEC_STATE_FOLLOWER_HEADER_INIT_LOW);
-		else
-			enter_state(CEC_STATE_IDLE);
-		break;
-	case CEC_STATE_FOLLOWER_HEADER_INIT_LOW:
-	case CEC_STATE_FOLLOWER_HEADER_DEST_LOW:
-	case CEC_STATE_FOLLOWER_DATA_LOW:
-		t = tmr_cap_get();
-		if (VALID_LOW(DATA_ZERO, t)) {
-			cec_rx.low_ticks = t;
-			cec_transfer_set_bit(&cec_rx.transfer, 0);
-			enter_state(cec_state + 1);
-		} else if (VALID_LOW(DATA_ONE, t)) {
-			cec_rx.low_ticks = t;
-			cec_transfer_set_bit(&cec_rx.transfer, 1);
-			enter_state(cec_state + 1);
-		} else {
-			enter_state(CEC_STATE_IDLE);
-		}
-		break;
-	case CEC_STATE_FOLLOWER_HEADER_INIT_HIGH:
-		t = tmr_cap_get();
-		data = cec_transfer_get_bit(&cec_rx.transfer);
-		if (VALID_DATA_HIGH(data, cec_rx.low_ticks, t)) {
-			cec_transfer_inc_bit(&cec_rx.transfer);
-			if (cec_rx.transfer.bit == 4)
-				enter_state(CEC_STATE_FOLLOWER_HEADER_DEST_LOW);
-			else
-				enter_state(CEC_STATE_FOLLOWER_HEADER_INIT_LOW);
-		} else {
-			enter_state(CEC_STATE_IDLE);
-		}
-		break;
-	case CEC_STATE_FOLLOWER_HEADER_DEST_HIGH:
-		t = tmr_cap_get();
-		data = cec_transfer_get_bit(&cec_rx.transfer);
-		if (VALID_DATA_HIGH(data, cec_rx.low_ticks, t)) {
-			cec_transfer_inc_bit(&cec_rx.transfer);
-			if (cec_rx.transfer.bit == 0)
-				enter_state(CEC_STATE_FOLLOWER_EOM_LOW);
-			else
-				enter_state(CEC_STATE_FOLLOWER_HEADER_DEST_LOW);
-		} else {
-			enter_state(CEC_STATE_IDLE);
-		}
-		break;
-	case CEC_STATE_FOLLOWER_EOM_LOW:
-		t = tmr_cap_get();
-		if (VALID_LOW(DATA_ZERO, t)) {
-			cec_rx.low_ticks = t;
-			cec_rx.eom = 0;
-			enter_state(CEC_STATE_FOLLOWER_EOM_HIGH);
-		} else if (VALID_LOW(DATA_ONE, t)) {
-			cec_rx.low_ticks = t;
-			cec_rx.eom = 1;
-			enter_state(CEC_STATE_FOLLOWER_EOM_HIGH);
-		} else {
-			enter_state(CEC_STATE_IDLE);
-		}
-		break;
-	case CEC_STATE_FOLLOWER_EOM_HIGH:
-		t = tmr_cap_get();
-		data = cec_rx.eom;
-		if (VALID_DATA_HIGH(data, cec_rx.low_ticks, t))
-			enter_state(CEC_STATE_FOLLOWER_ACK_LOW);
-		else
-			enter_state(CEC_STATE_IDLE);
-		break;
-	case CEC_STATE_FOLLOWER_ACK_LOW:
-		enter_state(CEC_STATE_FOLLOWER_ACK_FINISH);
-		break;
-	case CEC_STATE_FOLLOWER_ACK_FINISH:
-		enter_state(CEC_STATE_FOLLOWER_DATA_LOW);
-		break;
-	case CEC_STATE_FOLLOWER_DATA_HIGH:
-		t = tmr_cap_get();
-		data = cec_transfer_get_bit(&cec_rx.transfer);
-		if (VALID_DATA_HIGH(data, cec_rx.low_ticks, t)) {
-			cec_transfer_inc_bit(&cec_rx.transfer);
-			if (cec_rx.transfer.bit == 0)
-				enter_state(CEC_STATE_FOLLOWER_EOM_LOW);
-			else
-				enter_state(CEC_STATE_FOLLOWER_DATA_LOW);
-		} else {
-			enter_state(CEC_STATE_IDLE);
-		}
-		break;
-	default:
-		break;
-	}
-}
-
-static void cec_event_tx(void)
-{
-	/*
-	 * If we have an ongoing receive, this transfer
-	 * will start when transitioning to IDLE
-	 */
-	if (cec_state == CEC_STATE_IDLE)
-		enter_state(CEC_STATE_INITIATOR_FREE_TIME);
-}
-
-void cec_isr(void)
-{
-	int mdl = NPCX_MFT_MODULE_1;
-	uint8_t events;
-
-	/* Retrieve events NPCX_TECTRL_TAXND */
-	events = GET_FIELD(NPCX_TECTRL(mdl), FIELD(0, 4));
-
-	if (events & BIT(NPCX_TECTRL_TAPND)) {
-		/* Capture event */
-		cec_event_cap();
-	} else {
-		/*
-		 * Capture timeout
-		 * We only care about this if the capture event is not
-		 * happening, since we will get both events in the
-		 * edge-trigger case
-		 */
-		if (events & BIT(NPCX_TECTRL_TCPND))
-			cec_event_timeout();
-	}
-	/* Oneshot timer, a transfer has been initiated from AP */
-	if (events & BIT(NPCX_TECTRL_TDPND)) {
-		tmr2_stop();
-		cec_event_tx();
-	}
-
-	/* Clear handled events */
-	SET_FIELD(NPCX_TECLR(mdl), FIELD(0, 4), events);
-}
-DECLARE_IRQ(NPCX_IRQ_MFT_1, cec_isr, 4);
-
-static int cec_send(const uint8_t *msg, uint8_t len)
-{
-	int i;
-
-	if (cec_tx.len != 0)
-		return -1;
-
-	cec_tx.len = len;
-
-	CPRINTS("Send CEC:");
-	for (i = 0; i < len && i < MAX_CEC_MSG_LEN; i++)
-		CPRINTS(" 0x%02x", msg[i]);
-
-	memcpy(cec_tx.transfer.buf, msg, len);
-
-	/* Elevate to interrupt context */
-	tmr2_start(0);
-
-	return 0;
-}
-
-static enum ec_status hc_cec_write(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_cec_write *params = args->params;
-
-	if (cec_state == CEC_STATE_DISABLED)
-		return EC_RES_UNAVAILABLE;
-
-	if (args->params_size == 0 || args->params_size > MAX_CEC_MSG_LEN)
-		return EC_RES_INVALID_PARAM;
-
-	if (cec_send(params->msg, args->params_size) != 0)
-		return EC_RES_BUSY;
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_CEC_WRITE_MSG, hc_cec_write, EC_VER_MASK(0));
-
-static int cec_set_enable(uint8_t enable)
-{
-	int mdl = NPCX_MFT_MODULE_1;
-
-	if (enable != 0 && enable != 1)
-		return EC_RES_INVALID_PARAM;
-
-	/* Enabling when already enabled? */
-	if (enable && cec_state != CEC_STATE_DISABLED)
-		return EC_RES_SUCCESS;
-
-	/* Disabling when already disabled? */
-	if (!enable && cec_state == CEC_STATE_DISABLED)
-		return EC_RES_SUCCESS;
-
-	if (enable) {
-		/* Configure GPIO40/TA1 as capture timer input (TA1) */
-		CLEAR_BIT(NPCX_DEVALT(0xC), NPCX_DEVALTC_TA1_SL2);
-		SET_BIT(NPCX_DEVALT(3), NPCX_DEVALT3_TA1_SL1);
-
-		enter_state(CEC_STATE_IDLE);
-
-		/*
-		 * Capture falling edge of first start
-		 * bit to get things going
-		 */
-		tmr_cap_start(CAP_EDGE_FALLING, 0);
-
-		/* Enable timer interrupts */
-		SET_BIT(NPCX_TIEN(mdl), NPCX_TIEN_TAIEN);
-		SET_BIT(NPCX_TIEN(mdl), NPCX_TIEN_TDIEN);
-
-		/* Enable multifunction timer interrupt */
-		task_enable_irq(NPCX_IRQ_MFT_1);
-
-		CPRINTF("CEC enabled\n");
-	} else {
-		/* Disable timer interrupts */
-		CLEAR_BIT(NPCX_TIEN(mdl), NPCX_TIEN_TAIEN);
-		CLEAR_BIT(NPCX_TIEN(mdl), NPCX_TIEN_TDIEN);
-
-		tmr2_stop();
-		tmr_cap_stop();
-
-		task_disable_irq(NPCX_IRQ_MFT_1);
-
-		/* Configure GPIO40/TA1 back to GPIO */
-		CLEAR_BIT(NPCX_DEVALT(3), NPCX_DEVALT3_TA1_SL1);
-		SET_BIT(NPCX_DEVALT(0xC), NPCX_DEVALTC_TA1_SL2);
-
-		enter_state(CEC_STATE_DISABLED);
-
-		CPRINTF("CEC disabled\n");
-	}
-
-	return EC_RES_SUCCESS;
-}
-
-static int cec_set_logical_addr(uint8_t logical_addr)
-{
-	if (logical_addr >= CEC_BROADCAST_ADDR &&
-	    logical_addr != CEC_UNREGISTERED_ADDR)
-		return EC_RES_INVALID_PARAM;
-
-	cec_addr = logical_addr;
-	CPRINTF("CEC address set to: %u\n", cec_addr);
-
-	return EC_RES_SUCCESS;
-}
-
-static enum ec_status hc_cec_set(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_cec_set *params = args->params;
-
-	switch (params->cmd) {
-	case CEC_CMD_ENABLE:
-		return cec_set_enable(params->val);
-	case CEC_CMD_LOGICAL_ADDRESS:
-		return cec_set_logical_addr(params->val);
-	}
-
-	return EC_RES_INVALID_PARAM;
-}
-DECLARE_HOST_COMMAND(EC_CMD_CEC_SET, hc_cec_set, EC_VER_MASK(0));
-
-
-static enum ec_status hc_cec_get(struct host_cmd_handler_args *args)
-{
-	struct ec_response_cec_get *response = args->response;
-	const struct ec_params_cec_get *params = args->params;
-
-	switch (params->cmd) {
-	case CEC_CMD_ENABLE:
-		response->val = cec_state == CEC_STATE_DISABLED ? 0 : 1;
-		break;
-	case CEC_CMD_LOGICAL_ADDRESS:
-		response->val = cec_addr;
-		break;
-	default:
-		return EC_RES_INVALID_PARAM;
-	}
-
-	args->response_size = sizeof(*response);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_CEC_GET, hc_cec_get, EC_VER_MASK(0));
-
-static int cec_get_next_event(uint8_t *out)
-{
-	uint32_t event_out = deprecated_atomic_read_clear(&cec_events);
-
-	memcpy(out, &event_out, sizeof(event_out));
-
-	return sizeof(event_out);
-}
-DECLARE_EVENT_SOURCE(EC_MKBP_EVENT_CEC_EVENT, cec_get_next_event);
-
-static int cec_get_next_msg(uint8_t *out)
-{
-	int rv;
-	uint8_t msg_len, msg[MAX_CEC_MSG_LEN];
-
-	rv = cec_rx_queue_pop(&cec_rx_queue, msg, &msg_len);
-	if (rv != 0)
-		return EC_RES_UNAVAILABLE;
-
-	memcpy(out, msg, msg_len);
-
-	return msg_len;
-}
-DECLARE_EVENT_SOURCE(EC_MKBP_EVENT_CEC_MESSAGE, cec_get_next_msg);
-
-
-static void cec_init(void)
-{
-	int mdl = NPCX_MFT_MODULE_1;
-
-	/* APB1 is the clock we base the timers on */
-	apb1_freq_div_10k = clock_get_apb1_freq()/10000;
-
-	/* Ensure Multi-Function timer is powered up. */
-	CLEAR_BIT(NPCX_PWDWN_CTL(mdl), NPCX_PWDWN_CTL1_MFT1_PD);
-
-	/* Mode 2 - Dual-input capture */
-	SET_FIELD(NPCX_TMCTRL(mdl), NPCX_TMCTRL_MDSEL_FIELD, NPCX_MFT_MDSEL_2);
-
-	/* Enable capture TCNT1 into TCRA and preset TCNT1. */
-	SET_BIT(NPCX_TMCTRL(mdl), NPCX_TMCTRL_TAEN);
-
-	/* If RO doesn't set it, RW needs to set it explicitly. */
-	gpio_set_level(CEC_GPIO_PULL_UP, 1);
-
-	/* Ensure the CEC bus is not pulled low by default on startup. */
-	gpio_set_level(CEC_GPIO_OUT, 1);
-
-	CPRINTS("CEC initialized");
-}
-DECLARE_HOOK(HOOK_INIT, cec_init, HOOK_PRIO_LAST);
-
-void cec_task(void *unused)
-{
-	int rv;
-	uint32_t events;
-
-	CPRINTF("CEC task starting\n");
-
-	while (1) {
-		events = task_wait_event(-1);
-		if (events & TASK_EVENT_RECEIVED_DATA) {
-			rv = cec_rx_queue_push(&cec_rx_queue,
-					       cec_rx.transfer.buf,
-					       cec_rx.transfer.byte);
-			if (rv == EC_ERROR_OVERFLOW) {
-				/* Queue full, prefer the most recent msg */
-				cec_rx_queue_flush(&cec_rx_queue);
-				rv = cec_rx_queue_push(&cec_rx_queue,
-						       cec_rx.transfer.buf,
-						       cec_rx.transfer.byte);
-			}
-			if (rv == EC_SUCCESS)
-				mkbp_send_event(EC_MKBP_EVENT_CEC_MESSAGE);
-		}
-	}
-}
diff --git a/chip/npcx/cec_bitbang.c b/chip/npcx/cec_bitbang.c
new file mode 100644
index 0000000000..2d75edccc2
--- /dev/null
+++ b/chip/npcx/cec_bitbang.c
@@ -0,0 +1,200 @@
+/* Copyright 2018 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cec.h"
+#include "clock_chip.h"
+#include "console.h"
+#include "driver/cec/bitbang.h"
+#include "fan_chip.h"
+#include "registers.h"
+#include "task.h"
+#include "util.h"
+
+#if !(DEBUG_CEC)
+#define CPRINTF(...)
+#define CPRINTS(...)
+#else
+#define CPRINTF(format, args...) cprintf(CC_CEC, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CEC, format, ##args)
+#endif
+
+/*
+ * Time between interrupt triggered and the next timer was
+ * set when measuring pulse width
+ */
+static int cap_delay;
+
+/* Value charged into the capture timer on last capture start */
+static int cap_charge;
+
+/* APB1 frequency. Store divided by 10k to avoid some runtime divisions */
+uint32_t apb1_freq_div_10k;
+
+void cec_tmr_cap_start(enum cec_cap_edge edge, int timeout)
+{
+	int mdl = NPCX_MFT_MODULE_1;
+
+	if (edge == CEC_CAP_EDGE_NONE) {
+		/*
+		 * If edge is NONE, disable capture interrupts and wait for a
+		 * timeout only.
+		 */
+		CLEAR_BIT(NPCX_TIEN(mdl), NPCX_TIEN_TAIEN);
+	} else {
+		/* Select edge to trigger capture on */
+		UPDATE_BIT(NPCX_TMCTRL(mdl), NPCX_TMCTRL_TAEDG,
+			   edge == CEC_CAP_EDGE_RISING);
+		SET_BIT(NPCX_TIEN(mdl), NPCX_TIEN_TAIEN);
+	}
+
+	/*
+	 * Set capture timeout. If we don't have a timeout, we
+	 * turn the timeout interrupt off and only care about
+	 * the edge change.
+	 */
+	if (timeout > 0) {
+		/*
+		 * Store the time it takes from the interrupts starts to when we
+		 * actually get here. This part of the pulse-width needs to be
+		 * taken into account
+		 */
+		cap_delay = (0xffff - NPCX_TCNT1(mdl));
+		cap_charge = timeout - cap_delay;
+		NPCX_TCNT1(mdl) = cap_charge;
+		SET_BIT(NPCX_TIEN(mdl), NPCX_TIEN_TCIEN);
+	} else {
+		CLEAR_BIT(NPCX_TIEN(mdl), NPCX_TIEN_TCIEN);
+		NPCX_TCNT1(mdl) = 0;
+	}
+
+	/* Clear out old events */
+	SET_BIT(NPCX_TECLR(mdl), NPCX_TECLR_TACLR);
+	SET_BIT(NPCX_TECLR(mdl), NPCX_TECLR_TCCLR);
+	NPCX_TCRA(mdl) = 0;
+	/* Start the capture timer */
+	SET_FIELD(NPCX_TCKC(mdl), NPCX_TCKC_C1CSEL_FIELD, 1);
+}
+
+void cec_tmr_cap_stop(void)
+{
+	int mdl = NPCX_MFT_MODULE_1;
+
+	CLEAR_BIT(NPCX_TIEN(mdl), NPCX_TIEN_TCIEN);
+	SET_FIELD(NPCX_TCKC(mdl), NPCX_TCKC_C1CSEL_FIELD, 0);
+}
+
+int cec_tmr_cap_get(void)
+{
+	int mdl = NPCX_MFT_MODULE_1;
+
+	return (cap_charge + cap_delay - NPCX_TCRA(mdl));
+}
+
+static void tmr2_start(int timeout)
+{
+	int mdl = NPCX_MFT_MODULE_1;
+
+	NPCX_TCNT2(mdl) = timeout;
+	SET_FIELD(NPCX_TCKC(mdl), NPCX_TCKC_C2CSEL_FIELD, 1);
+}
+
+static void tmr2_stop(void)
+{
+	int mdl = NPCX_MFT_MODULE_1;
+
+	SET_FIELD(NPCX_TCKC(mdl), NPCX_TCKC_C2CSEL_FIELD, 0);
+}
+
+static void cec_isr(void)
+{
+	int mdl = NPCX_MFT_MODULE_1;
+	uint8_t events;
+
+	/* Retrieve events NPCX_TECTRL_TAXND */
+	events = GET_FIELD(NPCX_TECTRL(mdl), FIELD(0, 4));
+
+	if (events & BIT(NPCX_TECTRL_TAPND)) {
+		/* Capture event */
+		cec_event_cap();
+	} else {
+		/*
+		 * Capture timeout
+		 * We only care about this if the capture event is not
+		 * happening, since we will get both events in the
+		 * edge-trigger case
+		 */
+		if (events & BIT(NPCX_TECTRL_TCPND))
+			cec_event_timeout();
+	}
+	/* Oneshot timer, a transfer has been initiated from AP */
+	if (events & BIT(NPCX_TECTRL_TDPND)) {
+		tmr2_stop();
+		cec_event_tx();
+	}
+
+	/* Clear handled events */
+	SET_FIELD(NPCX_TECLR(mdl), FIELD(0, 4), events);
+}
+DECLARE_IRQ(NPCX_IRQ_MFT_1, cec_isr, 4);
+
+void cec_trigger_send(void)
+{
+	/* Elevate to interrupt context */
+	tmr2_start(0);
+}
+
+void cec_enable_timer(void)
+{
+	int mdl = NPCX_MFT_MODULE_1;
+
+	/* Configure GPIO40/TA1 as capture timer input (TA1) */
+	CLEAR_BIT(NPCX_DEVALT(0xC), NPCX_DEVALTC_TA1_SL2);
+	SET_BIT(NPCX_DEVALT(3), NPCX_DEVALT3_TA1_SL1);
+
+	/* Enable timer interrupts */
+	SET_BIT(NPCX_TIEN(mdl), NPCX_TIEN_TAIEN);
+	SET_BIT(NPCX_TIEN(mdl), NPCX_TIEN_TDIEN);
+
+	/* Enable multifunction timer interrupt */
+	task_enable_irq(NPCX_IRQ_MFT_1);
+}
+
+void cec_disable_timer(void)
+{
+	int mdl = NPCX_MFT_MODULE_1;
+
+	/* Disable timer interrupts */
+	CLEAR_BIT(NPCX_TIEN(mdl), NPCX_TIEN_TAIEN);
+	CLEAR_BIT(NPCX_TIEN(mdl), NPCX_TIEN_TDIEN);
+
+	tmr2_stop();
+	cec_tmr_cap_stop();
+
+	task_disable_irq(NPCX_IRQ_MFT_1);
+
+	/* Configure GPIO40/TA1 back to GPIO */
+	CLEAR_BIT(NPCX_DEVALT(3), NPCX_DEVALT3_TA1_SL1);
+	SET_BIT(NPCX_DEVALT(0xC), NPCX_DEVALTC_TA1_SL2);
+
+	cap_charge = 0;
+	cap_delay = 0;
+}
+
+void cec_init_timer(void)
+{
+	int mdl = NPCX_MFT_MODULE_1;
+
+	/* APB1 is the clock we base the timers on */
+	apb1_freq_div_10k = clock_get_apb1_freq() / 10000;
+
+	/* Ensure Multi-Function timer is powered up. */
+	CLEAR_BIT(NPCX_PWDWN_CTL(mdl), NPCX_PWDWN_CTL1_MFT1_PD);
+
+	/* Mode 2 - Dual-input capture */
+	SET_FIELD(NPCX_TMCTRL(mdl), NPCX_TMCTRL_MDSEL_FIELD, NPCX_MFT_MDSEL_2);
+
+	/* Enable capture TCNT1 into TCRA and preset TCNT1. */
+	SET_BIT(NPCX_TMCTRL(mdl), NPCX_TMCTRL_TAEN);
+}
diff --git a/chip/npcx/cec_bitbang_chip.h b/chip/npcx/cec_bitbang_chip.h
new file mode 100644
index 0000000000..91a3cbdd56
--- /dev/null
+++ b/chip/npcx/cec_bitbang_chip.h
@@ -0,0 +1,19 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_CEC_CHIP_H
+#define __CROS_EC_CEC_CHIP_H
+
+/* APB1 frequency. Store divided by 10k to avoid some runtime divisions */
+extern uint32_t apb1_freq_div_10k;
+
+/* Time in us to timer clock ticks */
+#define CEC_US_TO_TICKS(t) ((t)*apb1_freq_div_10k / 100)
+#if DEBUG_CEC
+/* Timer clock ticks to us */
+#define CEC_TICKS_TO_US(ticks) (100 * (ticks) / apb1_freq_div_10k)
+#endif
+
+#endif /* __CROS_EC_CEC_CHIP_H */
diff --git a/chip/npcx/clock.c b/chip/npcx/clock.c
index 0f8f737401..8b47d847e8 100644
--- a/chip/npcx/clock.c
+++ b/chip/npcx/clock.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,10 +26,10 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args)
 
-#define WAKE_INTERVAL   61        /* Unit: 61 usec */
-#define IDLE_PARAMS     0x7       /* Support deep idle, instant wake-up */
+#define WAKE_INTERVAL 61 /* Unit: 61 usec */
+#define IDLE_PARAMS 0x7 /* Support deep idle, instant wake-up */
 
 /* Low power idle statistics */
 #ifdef CONFIG_LOW_POWER_IDLE
@@ -40,7 +40,7 @@ static uint64_t idle_dsleep_time_us;
  * Fixed amount of time to keep the console in use flag true after boot in
  * order to give a permanent window in which the low speed clock is not used.
  */
-#define CONSOLE_IN_USE_ON_BOOT_TIME (15*SECOND)
+#define CONSOLE_IN_USE_ON_BOOT_TIME (15 * SECOND)
 static int console_in_use_timeout_sec = 15;
 static timestamp_t console_expire_time;
 #endif
@@ -79,7 +79,6 @@ void clock_disable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode)
 
 	/* Set PD bit to 1 */
 	NPCX_PWDWN_CTL(offset) |= reg_mask;
-
 }
 
 /*****************************************************************************/
@@ -100,13 +99,13 @@ void clock_init(void)
 	 * unstable for a little which can affect peripheral communication like
 	 * eSPI. Skip this if not needed (e.g. RW jump)
 	 */
-	if (NPCX_HFCGN != HFCGN || NPCX_HFCGML != HFCGML
-				|| NPCX_HFCGMH != HFCGMH) {
+	if (NPCX_HFCGN != HFCGN || NPCX_HFCGML != HFCGML ||
+	    NPCX_HFCGMH != HFCGMH) {
 		/*
 		 * Configure frequency multiplier M/N values according to
 		 * the requested OSC_CLK (Unit:Hz).
 		 */
-		NPCX_HFCGN  = HFCGN;
+		NPCX_HFCGN = HFCGN;
 		NPCX_HFCGML = HFCGML;
 		NPCX_HFCGMH = HFCGMH;
 
@@ -119,11 +118,11 @@ void clock_init(void)
 
 	/* Set all clock prescalers of core and peripherals. */
 #if defined(CHIP_FAMILY_NPCX5)
-	NPCX_HFCGP  = (FPRED << 4);
+	NPCX_HFCGP = (FPRED << 4);
 	NPCX_HFCBCD = (NPCX_HFCBCD & 0xF0) | (APB1DIV | (APB2DIV << 2));
 #elif NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-	NPCX_HFCGP   = ((FPRED << 4) | AHB6DIV);
-	NPCX_HFCBCD  = (FIUDIV << 4);
+	NPCX_HFCGP = ((FPRED << 4) | AHB6DIV);
+	NPCX_HFCBCD = (FIUDIV << 4);
 	NPCX_HFCBCD1 = (APB1DIV | (APB2DIV << 4));
 #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
 	NPCX_HFCBCD2 = (APB3DIV | (APB4DIV << 4));
@@ -143,7 +142,7 @@ void clock_init(void)
 void clock_turbo(void)
 {
 	/* Configure Frequency multiplier values to 50MHz */
-	NPCX_HFCGN  = 0x02;
+	NPCX_HFCGN = 0x02;
 	NPCX_HFCGML = 0xEC;
 	NPCX_HFCGMH = 0x0B;
 
@@ -163,14 +162,28 @@ void clock_turbo(void)
 	 */
 	NPCX_HFCBCD = NPCX_HFCBCD & 0xF3;
 }
+
+test_mockable void clock_enable_module(enum module_id module, int enable)
+{
+}
+
 #elif NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
 void clock_turbo(void)
 {
-	/*
+#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
+	/* For NPCX9:
+	 * Increase CORE_CLK (CPU) as the same as OSC_CLK. Since
+	 * CORE_CLK > 66MHz, we also need to set FIUDIV as 1 but
+	 * can keep AHB6DIV to 0.
+	 */
+	NPCX_HFCGP = 0x00;
+#else
+	/* For NPCX7:
 	 * Increase CORE_CLK (CPU) as the same as OSC_CLK. Since
 	 * CORE_CLK > 66MHz, we also need to set AHB6DIV and FIUDIV as 1.
 	 */
 	NPCX_HFCGP = 0x01;
+#endif
 	NPCX_HFCBCD = BIT(4);
 }
 
@@ -181,7 +194,7 @@ void clock_normal(void)
 	NPCX_HFCBCD = (FIUDIV << 4);
 }
 
-void clock_enable_module(enum module_id module, int enable)
+test_mockable void clock_enable_module(enum module_id module, int enable)
 {
 	/* Assume we have a single task using MODULE_FAST_CPU */
 	if (module == MODULE_FAST_CPU) {
@@ -192,6 +205,12 @@ void clock_enable_module(enum module_id module, int enable)
 	}
 }
 
+#else
+
+test_mockable void clock_enable_module(enum module_id module, int enable)
+{
+}
+
 #endif
 
 /**
@@ -246,7 +265,8 @@ int clock_get_apb3_freq(void)
 void clock_wait_cycles(uint32_t cycles)
 {
 	asm volatile("1: subs %0, #1\n"
-		     "   bne 1b\n" : "+r"(cycles));
+		     "   bne 1b\n"
+		     : "+r"(cycles));
 }
 
 #ifdef CONFIG_LOW_POWER_IDLE
@@ -369,12 +389,11 @@ void __idle(void)
 			 * more detail.
 			 * Workaround: Apply the same bypass of idle.
 			 */
-			asm ("push {r0-r5}\n"
-			     "wfi\n"
-			     "ldm %0, {r0-r5}\n"
-			     "pop {r0-r5}\n"
-			     "isb\n" :: "r" (0x100A8000)
-			);
+			asm("push {r0-r5}\n"
+			    "wfi\n"
+			    "ldm %0, {r0-r5}\n"
+			    "pop {r0-r5}\n"
+			    "isb\n" ::"r"(0x100A8000));
 
 			/* Get time delay cause of deep idle */
 			next_evt_us = __hw_clock_get_sleep_time(evt_count);
@@ -413,7 +432,7 @@ void __idle(void)
 			 * CSAE bit is set. Please notice this symptom only
 			 * occurs at npcx5.
 			 */
-#if defined(CHIP_FAMILY_NPCX5) && defined(CONFIG_HOSTCMD_ESPI)
+#if defined(CHIP_FAMILY_NPCX5) && defined(CONFIG_HOST_INTERFACE_ESPI)
 			/* Enable Host access wakeup */
 			SET_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6);
 #endif
@@ -422,12 +441,11 @@ void __idle(void)
 			 * TODO (ML): Workaround method for wfi issue.
 			 * Please see task.c for more detail
 			 */
-			asm ("push {r0-r5}\n"
-			     "wfi\n"
-			     "ldm %0, {r0-r5}\n"
-			     "pop {r0-r5}\n"
-			     "isb\n" :: "r" (0x100A8000)
-			);
+			asm("push {r0-r5}\n"
+			    "wfi\n"
+			    "ldm %0, {r0-r5}\n"
+			    "pop {r0-r5}\n"
+			    "isb\n" ::"r"(0x100A8000));
 		}
 
 		/*
@@ -439,30 +457,28 @@ void __idle(void)
 }
 #endif /* CONFIG_LOW_POWER_IDLE */
 
-
 #ifdef CONFIG_LOW_POWER_IDLE
 /**
  * Print low power idle statistics
  */
-static int command_idle_stats(int argc, char **argv)
+static int command_idle_stats(int argc, const char **argv)
 {
 	timestamp_t ts = get_time();
 
 	ccprintf("Num idle calls that sleep:           %d\n", idle_sleep_cnt);
 	ccprintf("Num idle calls that deep-sleep:      %d\n", idle_dsleep_cnt);
 	ccprintf("Time spent in deep-sleep:            %.6llds\n",
-			idle_dsleep_time_us);
+		 idle_dsleep_time_us);
 	ccprintf("Total time on:                       %.6llds\n", ts.val);
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats,
-		"",
-		"Print last idle stats");
+DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, "",
+			"Print last idle stats");
 
 /**
  * Configure deep sleep clock settings.
  */
-static int command_dsleep(int argc, char **argv)
+static int command_dsleep(int argc, const char **argv)
 {
 	int v;
 
@@ -490,19 +506,18 @@ static int command_dsleep(int argc, char **argv)
 		}
 	}
 
-	ccprintf("Sleep mask: %08x\n", sleep_mask);
+	ccprintf("Sleep mask: %08x\n", (int)sleep_mask);
 	ccprintf("Console in use timeout:   %d sec\n",
-			console_in_use_timeout_sec);
+		 console_in_use_timeout_sec);
 	ccprintf("PMCSR register:      0x%02x\n", NPCX_PMCSR);
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(dsleep, command_dsleep,
-		"[ on | off | <timeout> sec]",
-		"Deep sleep clock settings:\nUse 'on' to force deep "
-		"sleep not to use low speed clock.\nUse 'off' to "
-		"allow deep sleep to auto-select using the low speed "
-		"clock.\n"
-		"Give a timeout value for the console in use timeout.\n"
-		"See also 'sleepmask'.");
+DECLARE_CONSOLE_COMMAND(dsleep, command_dsleep, "[ on | off | <timeout> sec]",
+			"Deep sleep clock settings:\nUse 'on' to force deep "
+			"sleep not to use low speed clock.\nUse 'off' to "
+			"allow deep sleep to auto-select using the low speed "
+			"clock.\n"
+			"Give a timeout value for the console in use timeout.\n"
+			"See also 'sleepmask'.");
 #endif /* CONFIG_LOW_POWER_IDLE */
diff --git a/chip/npcx/clock_chip.h b/chip/npcx/clock_chip.h
index 702b55c52a..c105194fdf 100644
--- a/chip/npcx/clock_chip.h
+++ b/chip/npcx/clock_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -95,40 +95,40 @@
  * OSC_CLK (Unit:Hz).
  */
 #if (OSC_CLK > 80000000)
-#define HFCGN    0x82 /* Set XF_RANGE as 1 if OSC_CLK >= 80MHz */
+#define HFCGN 0x82 /* Set XF_RANGE as 1 if OSC_CLK >= 80MHz */
 #else
-#define HFCGN    0x02
+#define HFCGN 0x02
 #endif
-#if   (OSC_CLK == 100000000)
-#define HFCGMH   0x0B
-#define HFCGML   0xEC
+#if (OSC_CLK == 100000000)
+#define HFCGMH 0x0B
+#define HFCGML 0xEC
 #elif (OSC_CLK == 90000000)
-#define HFCGMH   0x0A
-#define HFCGML   0xBA
+#define HFCGMH 0x0A
+#define HFCGML 0xBA
 #elif (OSC_CLK == 80000000)
-#define HFCGMH   0x09
-#define HFCGML   0x89
+#define HFCGMH 0x09
+#define HFCGML 0x89
 #elif (OSC_CLK == 66000000)
-#define HFCGMH   0x0F
-#define HFCGML   0xBC
+#define HFCGMH 0x0F
+#define HFCGML 0xBC
 #elif (OSC_CLK == 50000000)
-#define HFCGMH   0x0B
-#define HFCGML   0xEC
+#define HFCGMH 0x0B
+#define HFCGML 0xEC
 #elif (OSC_CLK == 48000000)
-#define HFCGMH   0x0B
-#define HFCGML   0x72
+#define HFCGMH 0x0B
+#define HFCGML 0x72
 #elif (OSC_CLK == 40000000)
-#define HFCGMH   0x09
-#define HFCGML   0x89
+#define HFCGMH 0x09
+#define HFCGML 0x89
 #elif (OSC_CLK == 33000000)
-#define HFCGMH   0x07
-#define HFCGML   0xDE
+#define HFCGMH 0x07
+#define HFCGML 0xDE
 #elif (OSC_CLK == 30000000)
-#define HFCGMH   0x07
-#define HFCGML   0x27
+#define HFCGMH 0x07
+#define HFCGML 0x27
 #elif (OSC_CLK == 26000000)
-#define HFCGMH   0x06
-#define HFCGML   0x33
+#define HFCGMH 0x06
+#define HFCGML 0x33
 #else
 #error "Unsupported OSC_CLK Frequency"
 #endif
diff --git a/chip/npcx/config_chip-npcx5.h b/chip/npcx/config_chip-npcx5.h
index 331b5e5474..53713b2dfb 100644
--- a/chip/npcx/config_chip-npcx5.h
+++ b/chip/npcx/config_chip-npcx5.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,10 +14,10 @@
  */
 
 /* Chip ID for all variants */
-#define NPCX585G_CHIP_ID		0x12
-#define NPCX575G_CHIP_ID		0x13
-#define NPCX586G_CHIP_ID		0x16
-#define NPCX576G_CHIP_ID		0x17
+#define NPCX585G_CHIP_ID 0x12
+#define NPCX575G_CHIP_ID 0x13
+#define NPCX586G_CHIP_ID 0x16
+#define NPCX576G_CHIP_ID 0x17
 
 /*****************************************************************************/
 /* Hardware features */
@@ -25,24 +25,30 @@
 /* Number of UART modules. */
 #define UART_MODULE_COUNT 1
 
+/*
+ * For NPCX5, PS2_3 pins also support other alternate functions (e.g., TA2).
+ * PS2_3 should be Explicit defined.
+ */
+#undef NPCX_PS2_MODULE_3
+
 /*
  * Number of I2C controllers. Controller 0 has 2 ports, so the chip has one
  * additional port.
  */
 #define CONFIG_I2C_MULTI_PORT_CONTROLLER
 /* Number of I2C controllers */
-#define I2C_CONTROLLER_COUNT	4
+#define I2C_CONTROLLER_COUNT 4
 /* Number of I2C ports */
-#define I2C_PORT_COUNT		5
+#define I2C_PORT_COUNT 5
 
 /*****************************************************************************/
 /* Memory mapping */
-#define NPCX_BTRAM_SIZE		0x800 /* 2KB data ram used by booter. */
-#define CONFIG_RAM_BASE		0x200C0000 /* memory address of data ram */
-#define CONFIG_DATA_RAM_SIZE	0x00008000 /* Size of data RAM */
-#define CONFIG_RAM_SIZE		(CONFIG_DATA_RAM_SIZE - NPCX_BTRAM_SIZE)
-#define CONFIG_LPRAM_BASE	0x40001600 /* memory address of lpwr ram */
-#define CONFIG_LPRAM_SIZE	0x00000620 /* 1568B low power ram */
+#define NPCX_BTRAM_SIZE 0x800 /* 2KB data ram used by booter. */
+#define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */
+#define CONFIG_DATA_RAM_SIZE 0x00008000 /* Size of data RAM */
+#define CONFIG_RAM_SIZE (CONFIG_DATA_RAM_SIZE - NPCX_BTRAM_SIZE)
+#define CONFIG_LPRAM_BASE 0x40001600 /* memory address of lpwr ram */
+#define CONFIG_LPRAM_SIZE 0x00000620 /* 1568B low power ram */
 
 /* Use chip variant to specify the size and start address of program memory */
 #if defined(CHIP_VARIANT_NPCX5M5G)
diff --git a/chip/npcx/config_chip-npcx7.h b/chip/npcx/config_chip-npcx7.h
index 5919f69af8..e44aebe6cf 100644
--- a/chip/npcx/config_chip-npcx7.h
+++ b/chip/npcx/config_chip-npcx7.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,26 +16,27 @@
  */
 
 /* Chip ID for all variants */
-#define NPCX787G_CHIP_ID		0x1F
-#define NPCX796F_A_B_CHIP_ID		0x21
-#define NPCX796F_C_CHIP_ID		0x29
-#define NPCX797F_C_CHIP_ID		0x20
-#define NPCX797W_B_CHIP_ID		0x24
-#define NPCX797W_C_CHIP_ID		0x2C
+#define NPCX787G_CHIP_ID 0x1F
+#define NPCX796F_A_B_CHIP_ID 0x21
+#define NPCX796F_C_CHIP_ID 0x29
+#define NPCX797F_C_CHIP_ID 0x20
+#define NPCX797W_B_CHIP_ID 0x24
+#define NPCX797W_C_CHIP_ID 0x2C
 
 /*****************************************************************************/
 /* Hardware features */
 
 /* The optional hardware features depend on chip variant */
-#if defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \
+#if defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) ||      \
 	defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M7FC) || \
 	defined(CHIP_VARIANT_NPCX7M7WB) || defined(CHIP_VARIANT_NPCX7M7WC)
 #define NPCX_INT_FLASH_SUPPORT /* Internal flash support */
-#define NPCX_PSL_MODE_SUPPORT /* Power switch logic mode for ultra-low power */
+#define NPCX_PSL_MODE_SUPPORT /* Power switch logic mode for ultra-low power \
+			       */
 #define NPCX_EXT32K_OSC_SUPPORT /* External 32KHz crytal osc. input support */
 #endif
 
-#if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) || \
+#if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) ||     \
 	defined(CHIP_VARIANT_NPCX7M7FC) || defined(CHIP_VARIANT_NPCX7M7WB) || \
 	defined(CHIP_VARIANT_NPCX7M7WC)
 #define NPCX_UART_FIFO_SUPPORT
@@ -43,8 +44,24 @@
 #define NPCX_SECOND_UART
 #define UART_MODULE_COUNT 2
 
+/*
+ * For NPCX7, PS2_2 & PS2_3 pins also support other alternate functions
+ * (e.g., ADC5, ADC6, TA2). PS2_2 & PS2_3 should be Explicit defined.
+ */
+#undef NPCX_PS2_MODULE_2
+#undef NPCX_PS2_MODULE_3
+
 /* 64-bit timer support */
 #define NPCX_ITIM64_SUPPORT
+
+/*
+ * Workaound the issue 3.10 in the NPCX99nF errata rev1.2
+ * Enabling an eSPI channel (e.g. Peripheral Channel, Virtual Wire Channel, etc.
+ * ) during an eSPI transaction might (with low probability) cause the eSPI_SIF
+ * module to transition to a wrong state and therefore response with FATAL_ERROR
+ * on an incoming transaction.
+ */
+#define NPCX_ESPI_BYPASS_CH_ENABLE_FATAL_ERROR
 #else
 #define UART_MODULE_COUNT 1
 #endif
@@ -74,68 +91,68 @@
 
 /*****************************************************************************/
 /* Memory mapping */
-#define NPCX_BTRAM_SIZE    0x800 /* 2KB data ram used by booter. */
+#define NPCX_BTRAM_SIZE 0x800 /* 2KB data ram used by booter. */
 
 #define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + NPCX_PROGRAM_MEMORY_SIZE)
 
 #if defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \
 	defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M6G)
-	/* 192KB RAM for FW code */
-#	define NPCX_PROGRAM_MEMORY_SIZE (192 * 1024)
-	/* program memory base address for Code RAM (0x100C0000 - 192KB) */
-#	define CONFIG_PROGRAM_MEMORY_BASE 0x10090000
-#	define CONFIG_RAM_BASE    0x200C0000 /* memory address of data ram */
-	/* 62 KB data RAM + 2 KB BT RAM size */
-#	define CONFIG_DATA_RAM_SIZE    0x00010000
+/* 192KB RAM for FW code */
+#define NPCX_PROGRAM_MEMORY_SIZE (192 * 1024)
+/* program memory base address for Code RAM (0x100C0000 - 192KB) */
+#define CONFIG_PROGRAM_MEMORY_BASE 0x10090000
+#define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */
+/* 62 KB data RAM + 2 KB BT RAM size */
+#define CONFIG_DATA_RAM_SIZE 0x00010000
 #elif defined(CHIP_VARIANT_NPCX7M7WB)
-	/* 256KB RAM for FW code */
-#	define NPCX_PROGRAM_MEMORY_SIZE (256 * 1024)
-	/* program memory base address for Code RAM (0x100B0000 - 256KB) */
-#	define CONFIG_PROGRAM_MEMORY_BASE 0x10070000
-#	define CONFIG_RAM_BASE    0x200B0000 /* memory address of data ram */
-	/* 126 KB data RAM + 2 KB BT RAM size */
-#	define CONFIG_DATA_RAM_SIZE    0x00020000
+/* 256KB RAM for FW code */
+#define NPCX_PROGRAM_MEMORY_SIZE (256 * 1024)
+/* program memory base address for Code RAM (0x100B0000 - 256KB) */
+#define CONFIG_PROGRAM_MEMORY_BASE 0x10070000
+#define CONFIG_RAM_BASE 0x200B0000 /* memory address of data ram */
+/* 126 KB data RAM + 2 KB BT RAM size */
+#define CONFIG_DATA_RAM_SIZE 0x00020000
 #elif defined(CHIP_VARIANT_NPCX7M7FC) || defined(CHIP_VARIANT_NPCX7M7WC)
-	/*
-	 * Code RAM is normally assumed to be same as image size, but since
-	 * we exclude 4k from the image (see NPCX_PROGRAM_MEMORY_SIZE) we
-	 * need to explicitly configure it. This is the actual size of code
-	 * RAM on-chip.
-	 */
-#	define CONFIG_CODE_RAM_SIZE (256 * 1024)
-	/*
-	 * In npcx797wc and npcx797fc, the code RAM size is limited by the
-	 * internal flash size (i.e. 512 KB/2=256 KB.) The driver has to
-	 * re-organize the memory to:
-	 * 1. the overall memory (RAM) layout is re-organized against the
-	 * datasheet:
-	 *     In datasheet: 320 KB code RAM + 64 KB data RAM
-	 *     After re-organization: 256 KB code RAM + 128 KB data RAM.
-	 * 2. 256KB program RAM, but only 512K of Flash (vs 1M for the
-	 * -WB). After the boot header is added, a 256K image would be
-	 * too large to fit in either RO or RW sections of Flash (each
-	 * of which is half of it). Because other code assumes that
-	 * image size is a multiple of Flash erase granularity, we
-	 * sacrifice a whole sector.
-	 */
-#	define NPCX_PROGRAM_MEMORY_SIZE (CONFIG_CODE_RAM_SIZE - 0x1000)
-	/* program memory base address for Code RAM (0x100B0000 - 256KB) */
-#	define CONFIG_PROGRAM_MEMORY_BASE 0x10070000
-#	define CONFIG_RAM_BASE    0x200B0000 /* memory address of data ram */
-	/* 126 KB data RAM + 2 KB BT RAM size */
-#	define CONFIG_DATA_RAM_SIZE    0x00020000
-
-	/*
-	 * Override default NPCX_RAM_SIZE because NPCX_PROGRAM_MEMORY_SIZE
-	 * is not the actual size of code RAM.
-	 */
-#	undef NPCX_RAM_SIZE
-#	define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + CONFIG_CODE_RAM_SIZE)
+/*
+ * Code RAM is normally assumed to be same as image size, but since
+ * we exclude 4k from the image (see NPCX_PROGRAM_MEMORY_SIZE) we
+ * need to explicitly configure it. This is the actual size of code
+ * RAM on-chip.
+ */
+#define CONFIG_CODE_RAM_SIZE (256 * 1024)
+/*
+ * In npcx797wc and npcx797fc, the code RAM size is limited by the
+ * internal flash size (i.e. 512 KB/2=256 KB.) The driver has to
+ * re-organize the memory to:
+ * 1. the overall memory (RAM) layout is re-organized against the
+ * datasheet:
+ *     In datasheet: 320 KB code RAM + 64 KB data RAM
+ *     After re-organization: 256 KB code RAM + 128 KB data RAM.
+ * 2. 256KB program RAM, but only 512K of Flash (vs 1M for the
+ * -WB). After the boot header is added, a 256K image would be
+ * too large to fit in either RO or RW sections of Flash (each
+ * of which is half of it). Because other code assumes that
+ * image size is a multiple of Flash erase granularity, we
+ * sacrifice a whole sector.
+ */
+#define NPCX_PROGRAM_MEMORY_SIZE (CONFIG_CODE_RAM_SIZE - 0x1000)
+/* program memory base address for Code RAM (0x100B0000 - 256KB) */
+#define CONFIG_PROGRAM_MEMORY_BASE 0x10070000
+#define CONFIG_RAM_BASE 0x200B0000 /* memory address of data ram */
+/* 126 KB data RAM + 2 KB BT RAM size */
+#define CONFIG_DATA_RAM_SIZE 0x00020000
+
+/*
+ * Override default NPCX_RAM_SIZE because NPCX_PROGRAM_MEMORY_SIZE
+ * is not the actual size of code RAM.
+ */
+#undef NPCX_RAM_SIZE
+#define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + CONFIG_CODE_RAM_SIZE)
 #else
-#	error "Unsupported chip variant"
+#error "Unsupported chip variant"
 #endif
 
-#define CONFIG_RAM_SIZE         (CONFIG_DATA_RAM_SIZE - NPCX_BTRAM_SIZE)
+#define CONFIG_RAM_SIZE (CONFIG_DATA_RAM_SIZE - NPCX_BTRAM_SIZE)
 /* no low power ram in npcx7 series */
 
 #endif /* __CROS_EC_CONFIG_CHIP_NPCX7_H */
diff --git a/chip/npcx/config_chip-npcx9.h b/chip/npcx/config_chip-npcx9.h
index 9f7b0f52d0..137611007e 100644
--- a/chip/npcx/config_chip-npcx9.h
+++ b/chip/npcx/config_chip-npcx9.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,8 +16,8 @@
  */
 
 /* Chip ID for all variants */
-#define NPCX996F_CHIP_ID		0x21
-#define NPCX993F_CHIP_ID		0x25
+#define NPCX996F_CHIP_ID 0x21
+#define NPCX993F_CHIP_ID 0x25
 
 /*****************************************************************************/
 /* Hardware features */
@@ -25,13 +25,21 @@
 #define NPCX_EXT32K_OSC_SUPPORT /* External 32KHz crytal osc. input support */
 #define NPCX_INT_FLASH_SUPPORT /* Internal flash support */
 #define NPCX_LCT_SUPPORT /* Long Countdown Timer support */
-#define NPCX_PSL_MODE_SUPPORT /* Power switch logic mode for ultra-low power */
+#define NPCX_PSL_MODE_SUPPORT /* Power switch logic mode for ultra-low power \
+			       */
 
 #define NPCX_UART_FIFO_SUPPORT
 /* Number of UART modules. */
 #define NPCX_SECOND_UART
 #define UART_MODULE_COUNT 2
 
+/*
+ * For NPCX9, PS2_2 & PS2_3 pins also support other alternate functions
+ * (e.g., ADC5, ADC6, TA2). PS2_2 & PS2_3 should be Explicit defined.
+ */
+#undef NPCX_PS2_MODULE_2
+#undef NPCX_PS2_MODULE_3
+
 /*
  * Number of I2C controllers. Controller 5/6 has 2 ports, so the chip has
  * two additional ports.
@@ -48,61 +56,86 @@
 
 /* PSL_OUT optional configuration */
 /* Set PSL_OUT mode to pulse mode */
-#define NPCX_PSL_CFG_PSL_OUT_PULSE	BIT(0)
+#define NPCX_PSL_CFG_PSL_OUT_PULSE BIT(0)
 /* set PSL_OUT to open-drain */
-#define NPCX_PSL_CFG_PSL_OUT_OD		BIT(1)
-#define CONFIG_HIBERNATE_PSL_OUT_FLAGS	0
+#define NPCX_PSL_CFG_PSL_OUT_OD BIT(1)
+#define CONFIG_HIBERNATE_PSL_OUT_FLAGS 0
 
+/*
+ * Workaound the issue 3.10 in the NPCX99nF errata rev1.2
+ * Enabling an eSPI channel (e.g. Peripheral Channel, Virtual Wire Channel, etc.
+ * ) during an eSPI transaction might (with low probability) cause the eSPI_SIF
+ * module to transition to a wrong state and therefore response with FATAL_ERROR
+ * on an incoming transaction.
+ */
+#define NPCX_ESPI_BYPASS_CH_ENABLE_FATAL_ERROR
 
-#define CONFIG_WORKAROUND_FLASH_DOWNLOAD_API
 /*****************************************************************************/
 /* Memory mapping */
-#ifdef CONFIG_WORKAROUND_FLASH_DOWNLOAD_API
-#define CONFIG_LPRAM_BASE	0x40001400 /* memory address of lpwr ram */
-#define CONFIG_LPRAM_SIZE	0x00000620 /* 1568B low power ram */
-#endif
 
 #define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + NPCX_PROGRAM_MEMORY_SIZE)
 
 #if defined(CHIP_VARIANT_NPCX9M3F)
-	/*
-	 * 256KB program RAM, but only 512K of Flash. After the boot header is
-	 * added, a 256K image would be too large to fit in either RO or RW
-	 * sections of Flash (each of which is half of it). Because other code
-	 * assumes that image size is a multiple of Flash erase granularity, we
-	 * sacrifice a whole sector.
-	 */
-#	define NPCX_PROGRAM_MEMORY_SIZE (256 * 1024 - 0x1000)
-	/* program memory base address for Code RAM (0x100C0000 - 256KB) */
-#	define CONFIG_PROGRAM_MEMORY_BASE 0x10080000
-#	define CONFIG_RAM_BASE    0x200C0000 /* memory address of data ram */
-	/* Two blocks of data RAM - total size is 64KB */
-#	define CONFIG_DATA_RAM_SIZE    0x00010000
-#	define CONFIG_RAM_SIZE         CONFIG_DATA_RAM_SIZE
-
-	/* Override default NPCX_RAM_SIZE because we're excluding a block. */
-#	undef NPCX_RAM_SIZE
-#	define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + \
-			      NPCX_PROGRAM_MEMORY_SIZE + 0x1000)
+/*
+ * 256KB program RAM, but only 512K of Flash. After the boot header is
+ * added, a 256K image would be too large to fit in either RO or RW
+ * sections of Flash (each of which is half of it). Because other code
+ * assumes that image size is a multiple of Flash erase granularity, we
+ * sacrifice a whole sector.
+ */
+#define NPCX_PROGRAM_MEMORY_SIZE (256 * 1024 - 0x1000)
+/* program memory base address for Code RAM (0x100C0000 - 256KB) */
+#define CONFIG_PROGRAM_MEMORY_BASE 0x10080000
+#define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */
+/* Two blocks of data RAM - total size is 64KB */
+#define CONFIG_DATA_RAM_SIZE 0x00010000
+#define CONFIG_RAM_SIZE CONFIG_DATA_RAM_SIZE
+
+/* Override default NPCX_RAM_SIZE because we're excluding a block. */
+#undef NPCX_RAM_SIZE
+#define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + NPCX_PROGRAM_MEMORY_SIZE + 0x1000)
 #elif defined(CHIP_VARIANT_NPCX9M6F)
-	/* 192KB RAM for FW code */
-#	define NPCX_PROGRAM_MEMORY_SIZE (192 * 1024)
-	/* program memory base address for Code RAM (0x100C0000 - 192KB) */
-#	define CONFIG_PROGRAM_MEMORY_BASE 0x10090000
-#	define CONFIG_RAM_BASE    0x200C0000 /* memory address of data ram */
-	/* Two blocks of data RAM - total size is 64KB */
-#	define CONFIG_DATA_RAM_SIZE    0x00010000
-#	define CONFIG_RAM_SIZE         CONFIG_DATA_RAM_SIZE
+/* 192KB RAM for FW code */
+#define NPCX_PROGRAM_MEMORY_SIZE (192 * 1024)
+/* program memory base address for Code RAM (0x100C0000 - 192KB) */
+#define CONFIG_PROGRAM_MEMORY_BASE 0x10090000
+#define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */
+/* Two blocks of data RAM - total size is 64KB */
+#define CONFIG_DATA_RAM_SIZE 0x00010000
+#define CONFIG_RAM_SIZE CONFIG_DATA_RAM_SIZE
+#elif defined(CHIP_VARIANT_NPCX9M8S)
+/*
+ * 416KB program RAM, 1MB of Flash.
+ */
+#define NPCX_PROGRAM_MEMORY_SIZE (416 * 1024)
+/* program memory base address for Code RAM (0x100C0000 - 416KB) */
+#define CONFIG_PROGRAM_MEMORY_BASE 0x10058000
+#define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */
+/*
+ * Three blocks of data RAM - reserve 4KB for ROM utilities and
+ *data ram size is 92KB
+ */
+#define CONFIG_DATA_RAM_SIZE (96 * 1024 - 0x1000)
+#define CONFIG_RAM_SIZE CONFIG_DATA_RAM_SIZE
+
+/* Override default NPCX_RAM_SIZE because we're excluding a block. */
+#undef NPCX_RAM_SIZE
+#define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + NPCX_PROGRAM_MEMORY_SIZE + 0x1000)
 #else
-#	error "Unsupported chip variant"
+#error "Unsupported chip variant"
 #endif
 
 /* Internal spi-flash setting */
-#define CONFIG_SPI_FLASH_PORT 0
-#define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_REGS
+#if defined(CHIP_VARIANT_NPCX9M8S)
+#define CONFIG_SPI_FLASH_W25Q80 /* Internal spi flash type */
+#define CONFIG_FLASH_SIZE_BYTES 0x00100000 /* 1 MB internal spi flash */
+#else
 #define CONFIG_SPI_FLASH_W25Q40 /* Internal spi flash type */
-#define CONFIG_FLASH_SIZE 0x00080000 /* 512 KB internal spi flash */
+#define CONFIG_FLASH_SIZE_BYTES 0x00080000 /* 512 KB internal spi flash */
+#endif
 
+/* All NPCX9 variants support SHA256 accelerator. */
+#define CONFIG_SHA256_HW_ACCELERATE
 
 #endif /* __CROS_EC_CONFIG_CHIP_NPCX9_H */
diff --git a/chip/npcx/config_chip.h b/chip/npcx/config_chip.h
index cee339206c..d0bfe0a767 100644
--- a/chip/npcx/config_chip.h
+++ b/chip/npcx/config_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,20 +13,20 @@
  * Set the chip family version to 4 digits to keep the flexibility in case
  * we need the minor version for chip variants in a family.
  */
-#define NPCX_FAMILY_NPCX5        5000
-#define NPCX_FAMILY_NPCX7        7000
-#define NPCX_FAMILY_NPCX9        9000
+#define NPCX_FAMILY_NPCX5 5000
+#define NPCX_FAMILY_NPCX7 7000
+#define NPCX_FAMILY_NPCX9 9000
 
 /* Features depend on chip family */
 #if defined(CHIP_FAMILY_NPCX5)
 #include "config_chip-npcx5.h"
-#define NPCX_FAMILY_VERSION      NPCX_FAMILY_NPCX5
+#define NPCX_FAMILY_VERSION NPCX_FAMILY_NPCX5
 #elif defined(CHIP_FAMILY_NPCX7)
 #include "config_chip-npcx7.h"
-#define NPCX_FAMILY_VERSION      NPCX_FAMILY_NPCX7
+#define NPCX_FAMILY_VERSION NPCX_FAMILY_NPCX7
 #elif defined(CHIP_FAMILY_NPCX9)
 #include "config_chip-npcx9.h"
-#define NPCX_FAMILY_VERSION      NPCX_FAMILY_NPCX9
+#define NPCX_FAMILY_VERSION NPCX_FAMILY_NPCX9
 #else
 #error "Unsupported chip family"
 #endif
@@ -46,27 +46,27 @@
  * Notice instant wake-up from deep-idle cannot exceed 200 ms
  */
 #define HOOK_TICK_INTERVAL_MS 200
-#define HOOK_TICK_INTERVAL    (HOOK_TICK_INTERVAL_MS * MSEC)
+#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC)
 
 /* System stack size */
-#define CONFIG_STACK_SIZE       1024
+#define CONFIG_STACK_SIZE 1024
 
 /* non-standard task stack sizes */
-#define IDLE_TASK_STACK_SIZE		672
-#define LARGER_TASK_STACK_SIZE		800
-#define VENTI_TASK_STACK_SIZE		928
-#define ULTRA_TASK_STACK_SIZE		1056
-#define TRENTA_TASK_STACK_SIZE		1184
+#define IDLE_TASK_STACK_SIZE 672
+#define LARGER_TASK_STACK_SIZE 800
+#define VENTI_TASK_STACK_SIZE 928
+#define ULTRA_TASK_STACK_SIZE 1056
+#define TRENTA_TASK_STACK_SIZE 1184
 
-#define CHARGER_TASK_STACK_SIZE		800
-#define HOOKS_TASK_STACK_SIZE		800
-#define CONSOLE_TASK_STACK_SIZE		800
+#define CHARGER_TASK_STACK_SIZE 800
+#define HOOKS_TASK_STACK_SIZE 800
+#define CONSOLE_TASK_STACK_SIZE 800
 
 /* Default task stack size */
-#define TASK_STACK_SIZE			672
+#define TASK_STACK_SIZE 672
 
 /* Address of RAM log used by Booter */
-#define ADDR_BOOT_RAMLOG        0x100C7FC0
+#define ADDR_BOOT_RAMLOG 0x100C7FC0
 
 #include "config_flash_layout.h"
 
@@ -79,9 +79,13 @@
 /* Chip needs to do custom pre-init */
 #define CONFIG_CHIP_PRE_INIT
 /* Default use UART1 as console */
-#define CONFIG_CONSOLE_UART    0
+#define CONFIG_CONSOLE_UART 0
 
 #define GPIO_PIN(port, index) GPIO_##port, BIT(index)
 #define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m)
 
-#endif  /* __CROS_EC_CONFIG_CHIP_H */
+#if !defined(HAS_TASK_KEYSCAN)
+#define NPCX_SELECT_KSI_TO_GPIO
+#endif
+
+#endif /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/chip/npcx/config_flash_layout.h b/chip/npcx/config_flash_layout.h
index c45f4c53fd..ca2e909031 100644
--- a/chip/npcx/config_flash_layout.h
+++ b/chip/npcx/config_flash_layout.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,56 +18,61 @@
 #define CONFIG_MAPPED_STORAGE
 /* Storage is memory-mapped, but program runs from SRAM */
 #define CONFIG_MAPPED_STORAGE_BASE 0x64000000
-#undef  CONFIG_FLASH_PSTATE
+#undef CONFIG_FLASH_PSTATE
 
 #if defined(CHIP_VARIANT_NPCX5M5G)
-#define CONFIG_EC_PROTECTED_STORAGE_OFF  0
+#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
 #define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x20000
-#define CONFIG_EC_WRITABLE_STORAGE_OFF   0x20000
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE  0x20000
+#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x20000
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x20000
 #elif defined(CHIP_VARIANT_NPCX5M6G)
-#define CONFIG_EC_PROTECTED_STORAGE_OFF  0
+#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
 #define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x40000
-#define CONFIG_EC_WRITABLE_STORAGE_OFF   0x40000
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE  0x40000
-#elif defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \
+#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x40000
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x40000
+#elif defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) ||   \
 	defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M6G) || \
 	defined(CHIP_VARIANT_NPCX7M7FC) || defined(CHIP_VARIANT_NPCX7M7WC)
-#define CONFIG_EC_PROTECTED_STORAGE_OFF  0
+#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
 #define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x40000
-#define CONFIG_EC_WRITABLE_STORAGE_OFF   0x40000
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE  0x40000
+#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x40000
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x40000
 #elif defined(CHIP_VARIANT_NPCX7M7WB)
-#define CONFIG_EC_PROTECTED_STORAGE_OFF  0
+#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
 #define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x80000
-#define CONFIG_EC_WRITABLE_STORAGE_OFF   0x80000
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE  0x80000
+#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x80000
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x80000
 #elif defined(CHIP_VARIANT_NPCX9M3F) || defined(CHIP_VARIANT_NPCX9M6F)
-#define CONFIG_EC_PROTECTED_STORAGE_OFF  0
+#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
 #define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x40000
-#define CONFIG_EC_WRITABLE_STORAGE_OFF   0x40000
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE  0x40000
+#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x40000
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x40000
+#elif defined(CHIP_VARIANT_NPCX9M8S)
+#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
+#define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x80000
+#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x80000
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x80000
 #else
 #error "Unsupported chip variant"
 #endif
 
 /* Header support which is used by booter to copy FW from flash to code ram */
 #define NPCX_RO_HEADER
-#define CONFIG_RO_HDR_MEM_OFF	0x0
-#define CONFIG_RO_HDR_SIZE	0x40
+#define CONFIG_RO_HDR_MEM_OFF 0x0
+#define CONFIG_RO_HDR_SIZE 0x40
 
-#define CONFIG_WP_STORAGE_OFF	CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE	CONFIG_EC_PROTECTED_STORAGE_SIZE
+#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
+#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
 
 /* RO firmware in program memory - use all of program memory */
-#define CONFIG_RO_MEM_OFF	0
-#define CONFIG_RO_SIZE		NPCX_PROGRAM_MEMORY_SIZE
+#define CONFIG_RO_MEM_OFF 0
+#define CONFIG_RO_SIZE NPCX_PROGRAM_MEMORY_SIZE
 
 /*
  * ROM resident area in flash used to store data objects that are not copied
  * into code RAM. Enable using the CONFIG_CHIP_INIT_ROM_REGION option.
  */
-#define CONFIG_RO_ROM_RESIDENT_MEM_OFF	CONFIG_RO_SIZE
+#define CONFIG_RO_ROM_RESIDENT_MEM_OFF CONFIG_RO_SIZE
 #define CONFIG_RO_ROM_RESIDENT_SIZE \
 	(CONFIG_EC_PROTECTED_STORAGE_SIZE - CONFIG_RO_SIZE)
 
@@ -75,10 +80,10 @@
  * RW firmware in program memory - Identical to RO, only one image loaded at
  * a time.
  */
-#define CONFIG_RW_MEM_OFF	CONFIG_RO_MEM_OFF
-#define CONFIG_RW_SIZE		CONFIG_RO_SIZE
+#define CONFIG_RW_MEM_OFF CONFIG_RO_MEM_OFF
+#define CONFIG_RW_SIZE CONFIG_RO_SIZE
 
-#define CONFIG_RW_ROM_RESIDENT_MEM_OFF	CONFIG_RW_SIZE
+#define CONFIG_RW_ROM_RESIDENT_MEM_OFF CONFIG_RW_SIZE
 #define CONFIG_RW_ROM_RESIDENT_SIZE \
 	(CONFIG_EC_WRITABLE_STORAGE_SIZE - CONFIG_RW_SIZE)
 
@@ -91,36 +96,49 @@
 #endif
 
 /*
- * CONFIG_FLASH_ERASE_SIZE is set to maximum possible out of 64k, 32k and 4k
- * depending upon alignment of CONFIG_RO_SIZE. There are two assumptions here:
- * 1. CONFIG_RO_MEM_OFF is always 0 i.e. RO starts at 0.
- * 2. CONFIG_RO_SIZE and CONFIG_RW_SIZE are the same.
+ * The common flash support requires that the CONFIG_WP_STORAGE_SIZE and
+ * CONFIG_EC_WRITABLE_STORAGE_SIZE are both a multiple of
+ * CONFIG_FLASH_ERASE_SIZE.
  *
- * If above assumptions are not true, then additional checks would be required
- * to ensure that erase block size is selected based on the alignment of both
- * CONFIG_RO_SIZE and CONFIG_RW_SIZE and the offset of RO.
+ * THE NPCX supports erase sizes of 64 KiB, 32 KiB, and 4 KiB. The NPCX flash
+ * driver does not currently support CONFIG_FLASH_MULTIPLE_REGION, so set
+ * the erase size to the maximum (64 KiB) for the best performance.
+ * Using smaller erase sizes increases boot time. If write protected and
+ * writable flash regions are not a multiple of 64 KiB, then support
+ * for CONFIG_FLASH_MULTIPLE_REGION must be added.
  */
-#if ((CONFIG_RO_SIZE & (0x10000 - 1)) == 0)
-#define CONFIG_FLASH_ERASE_SIZE	0x10000
-#define NPCX_ERASE_COMMAND		CMD_BLOCK_64K_ERASE
-#elif ((CONFIG_RO_SIZE & (0x8000 - 1)) == 0)
-#define CONFIG_FLASH_ERASE_SIZE	0x8000
-#define NPCX_ERASE_COMMAND		CMD_BLOCK_32K_ERASE
-#else
-#define CONFIG_FLASH_ERASE_SIZE	0x1000
-#define NPCX_ERASE_COMMAND		CMD_SECTOR_ERASE
+#define CONFIG_FLASH_ERASE_SIZE 0x10000
+#define NPCX_ERASE_COMMAND CMD_BLOCK_64K_ERASE
+
+#if (CONFIG_WP_STORAGE_SIZE != CONFIG_EC_WRITABLE_STORAGE_SIZE)
+#error "NPCX flash support assumes CONFIG_WP_STORAGE_SIZE and " \
+	"CONFIG_EC_WRITABLE_STORAGE_SIZE are the same."
 #endif
 
-#define CONFIG_FLASH_BANK_SIZE		CONFIG_FLASH_ERASE_SIZE
-#define CONFIG_FLASH_WRITE_SIZE		0x1  /* minimum write size */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE	256   /* one page size for write */
+/*
+ * If the total flash size is not a multiple of 64k, this slows the boot
+ * time. CONFIG_FLASH_MULTIPLE_REGION should be enabled in this case to
+ * optimize the erase block handling.
+ */
+#if ((CONFIG_WP_STORAGE_SIZE % CONFIG_FLASH_ERASE_SIZE) != 0)
+#error "CONFIG_WP_STORAGE_SIZE is not a multiple of 64K. Correct the flash " \
+	"size or add support for CONFIG_FLASH_MULTIPLE_REGION."
+#endif
+
+/*
+ * The smallest protection bank size is 1/8 of 512 KB or 1/16 of 1M flash,
+ * i.e. 64KB.
+ */
+#define CONFIG_FLASH_BANK_SIZE 0x10000
+#define CONFIG_FLASH_WRITE_SIZE 0x1 /* minimum write size */
+#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* one page size for write */
 
 /* Use 4k sector erase for NPCX monitor flash erase operations. */
-#define NPCX_MONITOR_FLASH_ERASE_SIZE	0x1000
+#define NPCX_MONITOR_FLASH_ERASE_SIZE 0x1000
 
 /* RO image resides at start of protected region, right after header */
-#define CONFIG_RO_STORAGE_OFF	CONFIG_RO_HDR_SIZE
+#define CONFIG_RO_STORAGE_OFF CONFIG_RO_HDR_SIZE
 /* RW image resides at start of writable region */
-#define CONFIG_RW_STORAGE_OFF	0
+#define CONFIG_RW_STORAGE_OFF 0
 
 #endif /* __CROS_EC_CONFIG_FLASH_LAYOUT_H */
diff --git a/chip/npcx/espi.c b/chip/npcx/espi.c
index 9073838bd6..3bed4f4564 100644
--- a/chip/npcx/espi.c
+++ b/chip/npcx/espi.c
@@ -1,22 +1,23 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* ESPI module for Chrome EC */
 
-#include "registers.h"
-#include "system.h"
-#include "task.h"
 #include "chipset.h"
 #include "console.h"
-#include "uart.h"
-#include "util.h"
-#include "power.h"
 #include "espi.h"
-#include "lpc_chip.h"
 #include "hooks.h"
+#include "lpc_chip.h"
+#include "power.h"
+#include "registers.h"
+#include "system.h"
+#include "system_boot_time.h"
+#include "task.h"
 #include "timer.h"
+#include "uart.h"
+#include "util.h"
 
 /* Console output macros */
 #if !(DEBUG_ESPI)
@@ -24,113 +25,117 @@
 #define CPRINTS(...)
 #else
 #define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args)
 #endif
 
 /* Default eSPI configuration for VW events */
 struct vwevms_config_t {
-	uint8_t idx;        /* VW index */
-	uint8_t idx_en;     /* Index enable */
-	uint8_t pltrst_en;  /* Enable reset by PLTRST assert */
+	uint8_t idx; /* VW index */
+	uint8_t idx_en; /* Index enable */
+	uint8_t pltrst_en; /* Enable reset by PLTRST assert */
 	uint8_t espirst_en; /* Enable reset by eSPI_RST assert */
-	uint8_t int_en;     /* Interrupt/Wake-up enable */
+	uint8_t int_en; /* Interrupt/Wake-up enable */
 };
 
 struct vwevsm_config_t {
-	uint8_t idx;        /* VW index */
-	uint8_t idx_en;     /* Index enable */
-	uint8_t pltrst_en;  /* Enable reset by PLTRST assert */
-	uint8_t cdrst_en;   /* Enable cold reset */
-	uint8_t valid;      /* Valid VW mask */
+	uint8_t idx; /* VW index */
+	uint8_t idx_en; /* Index enable */
+	uint8_t pltrst_en; /* Enable reset by PLTRST assert */
+	uint8_t cdrst_en; /* Enable cold reset */
+	uint8_t valid; /* Valid VW mask */
 };
 
 /* Default MIWU configurations for VW events */
 struct host_wui_item {
 	uint16_t table : 2; /* MIWU table 0-2 */
 	uint16_t group : 3; /* MIWU group 0-7 */
-	uint16_t num   : 3; /* MIWU bit   0-7 */
-	uint16_t edge  : 4; /* MIWU edge trigger type rising/falling/any */
+	uint16_t num : 3; /* MIWU bit   0-7 */
+	uint16_t edge : 4; /* MIWU edge trigger type rising/falling/any */
 };
 
 /* Mapping item between VW signal, index and value */
 struct vw_event_t {
-	uint16_t name;     /* Name of signal */
-	uint8_t  evt_idx;  /* VW index of signal */
-	uint8_t  evt_val;  /* VW value of signal */
+	uint16_t name; /* Name of signal */
+	uint8_t evt_idx; /* VW index of signal */
+	uint8_t evt_val; /* VW value of signal */
 };
 
 /* Default settings of VWEVMS registers (Please refer Table.43/44) */
 static const struct vwevms_config_t espi_in_list[] = {
-	/* IDX EN ENPL ENESP IE/WE          VW Event Bit 0 - 3 (M->S)         */
-	{0x02,  1,  0,  0,  1},  /* SLP_S3#,   SLP_S4#,    SLP_S5#,   Reserve */
-	{0x03,  1,  0,  1,  1},  /* SUS_STAT#, PLTRST#,    ORST_WARN, Reserve */
-	{0x07,  1,  1,  1,  1},  /* HRST_WARN, SMIOUT#,    NMIOUT#,   Reserve */
-	{0x41,  1,  0,  1,  1},  /* SUS_WARN#, SPWRDN_ACK, Reserve,   SLP_A#  */
-	{0x42,  1,  0,  0,  1},  /* SLP_LAN#,  SLP_WAN#,   Reserve,   Reserve */
-	{0x47,  1,  1,  1,  1},  /* HOST_C10,  Reserve,    Reserve,   Reserve */
+/* IDX EN ENPL ENESP IE/WE          VW Event Bit 0 - 3 (M->S)         */
+#ifdef CONFIG_HOST_INTERFACE_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST
+	{ 0x02, 1, 0, 1, 1 }, /* SLP_S3#,   SLP_S4#,    SLP_S5#,   Reserve */
+#else
+	{ 0x02, 1, 0, 0, 1 }, /* SLP_S3#,   SLP_S4#,    SLP_S5#,   Reserve */
+#endif
+	{ 0x03, 1, 0, 1, 1 }, /* SUS_STAT#, PLTRST#,    ORST_WARN, Reserve */
+	{ 0x07, 1, 1, 1, 1 }, /* HRST_WARN, SMIOUT#,    NMIOUT#,   Reserve */
+	{ 0x41, 1, 0, 1, 1 }, /* SUS_WARN#, SPWRDN_ACK, Reserve,   SLP_A#  */
+	{ 0x42, 1, 0, 0, 1 }, /* SLP_LAN#,  SLP_WAN#,   Reserve,   Reserve */
+	{ 0x47, 1, 1, 1, 1 }, /* HOST_C10,  Reserve,    Reserve,   Reserve */
 };
 
 /* Default settings of VWEVSM registers (Please refer Table.43/44) */
 static const struct vwevsm_config_t espi_out_list[] = {
 	/* IDX EN ENPL ENCDR VDMASK         VW Event Bit 0 - 3 (S->M)         */
-	{0x04,  1,  0,  0, 0x0D}, /* ORST_ACK,   Reserve, WAKE#,   PME#       */
-	{0x05,  1,  0,  0, 0x0F}, /* SLV_BL_DNE, ERR_F,   ERR_NF,  SLV_BL_STS */
+	{ 0x04, 1, 0, 0, 0x0D }, /* ORST_ACK,   Reserve, WAKE#,   PME#       */
+	{ 0x05, 1, 0, 0, 0x0F }, /* SLV_BL_DNE, ERR_F,   ERR_NF,  SLV_BL_STS */
 #ifdef CONFIG_SCI_GPIO
-	{0x06,  1,  1,  0, 0x0C}, /* SCI#,       SMI#,    RCIN#,   HRST_ACK   */
+	{ 0x06, 1, 1, 0, 0x0C }, /* SCI#,       SMI#,    RCIN#,   HRST_ACK   */
 #else
-	{0x06,  1,  1,  0, 0x0F}, /* SCI#,       SMI#,    RCIN#,   HRST_ACK   */
+	{ 0x06, 1, 1, 0, 0x0F }, /* SCI#,       SMI#,    RCIN#,   HRST_ACK   */
 #endif
-	{0x40,  1,  0,  0, 0x01}, /* SUS_ACK,    Reserve, Reserve, Reserve    */
+	{ 0x40, 1, 0, 0, 0x01 }, /* SUS_ACK,    Reserve, Reserve, Reserve    */
 };
 
 /* eSPI interrupts used in MIWU */
 static const struct host_wui_item espi_vw_int_list[] = {
 	/* ESPI_RESET  */
-	{MIWU_TABLE_0, MIWU_GROUP_5, 5, MIWU_EDGE_FALLING},
+	{ MIWU_TABLE_0, MIWU_GROUP_5, 5, MIWU_EDGE_FALLING },
 	/* SLP_S3 */
-	{MIWU_TABLE_2, MIWU_GROUP_1, 0, MIWU_EDGE_ANYING},
+	{ MIWU_TABLE_2, MIWU_GROUP_1, 0, MIWU_EDGE_ANYING },
 	/* SLP_S4 */
-	{MIWU_TABLE_2, MIWU_GROUP_1, 1, MIWU_EDGE_ANYING},
+	{ MIWU_TABLE_2, MIWU_GROUP_1, 1, MIWU_EDGE_ANYING },
 	/* SLP_S5 */
-	{MIWU_TABLE_2, MIWU_GROUP_1, 2, MIWU_EDGE_ANYING},
+	{ MIWU_TABLE_2, MIWU_GROUP_1, 2, MIWU_EDGE_ANYING },
 	/* VW_WIRE_PLTRST */
-	{MIWU_TABLE_2, MIWU_GROUP_1, 5, MIWU_EDGE_ANYING},
+	{ MIWU_TABLE_2, MIWU_GROUP_1, 5, MIWU_EDGE_ANYING },
 	/* VW_WIRE_OOB_RST_WARN */
-	{MIWU_TABLE_2, MIWU_GROUP_1, 6, MIWU_EDGE_ANYING},
+	{ MIWU_TABLE_2, MIWU_GROUP_1, 6, MIWU_EDGE_ANYING },
 	/* VW_WIRE_HOST_RST_WARN */
-	{MIWU_TABLE_2, MIWU_GROUP_2, 0, MIWU_EDGE_ANYING},
+	{ MIWU_TABLE_2, MIWU_GROUP_2, 0, MIWU_EDGE_ANYING },
 	/* VW_WIRE_SUS_WARN */
-	{MIWU_TABLE_2, MIWU_GROUP_2, 4, MIWU_EDGE_ANYING},
+	{ MIWU_TABLE_2, MIWU_GROUP_2, 4, MIWU_EDGE_ANYING },
 };
 
 /* VW signals used in eSPI */
 static const struct vw_event_t vw_events_list[] = {
-	{VW_SLP_S3_L,               0x02,   0x01},	/* index 02h (In)  */
-	{VW_SLP_S4_L,               0x02,   0x02},
-	{VW_SLP_S5_L,               0x02,   0x04},
-	{VW_SUS_STAT_L,             0x03,   0x01},	/* index 03h (In)  */
-	{VW_PLTRST_L,               0x03,   0x02},
-	{VW_OOB_RST_WARN,           0x03,   0x04},
-	{VW_OOB_RST_ACK,            0x04,   0x01},	/* index 04h (Out) */
-	{VW_WAKE_L,                 0x04,   0x04},
-	{VW_PME_L,                  0x04,   0x08},
-	{VW_ERROR_FATAL,            0x05,   0x02},	/* index 05h (Out) */
-	{VW_ERROR_NON_FATAL,        0x05,   0x04},
-	{VW_SLAVE_BTLD_STATUS_DONE, 0x05,   0x09},
-	{VW_SCI_L,                  0x06,   0x01},	/* index 06h (Out) */
-	{VW_SMI_L,                  0x06,   0x02},
-	{VW_RCIN_L,                 0x06,   0x04},
-	{VW_HOST_RST_ACK,           0x06,   0x08},
-	{VW_HOST_RST_WARN,          0x07,   0x01},	/* index 07h (In)  */
-	{VW_SUS_ACK,                0x40,   0x01},	/* index 40h (Out) */
-	{VW_SUS_WARN_L,             0x41,   0x01},	/* index 41h (In)  */
-	{VW_SUS_PWRDN_ACK_L,        0x41,   0x02},
-	{VW_SLP_A_L,                0x41,   0x08},
-	{VW_SLP_LAN,                0x42,   0x01},	/* index 42h (In)  */
-	{VW_SLP_WLAN,               0x42,   0x02},
+	{ VW_SLP_S3_L, 0x02, 0x01 }, /* index 02h (In)  */
+	{ VW_SLP_S4_L, 0x02, 0x02 },
+	{ VW_SLP_S5_L, 0x02, 0x04 },
+	{ VW_SUS_STAT_L, 0x03, 0x01 }, /* index 03h (In)  */
+	{ VW_PLTRST_L, 0x03, 0x02 },
+	{ VW_OOB_RST_WARN, 0x03, 0x04 },
+	{ VW_OOB_RST_ACK, 0x04, 0x01 }, /* index 04h (Out) */
+	{ VW_WAKE_L, 0x04, 0x04 },
+	{ VW_PME_L, 0x04, 0x08 },
+	{ VW_ERROR_FATAL, 0x05, 0x02 }, /* index 05h (Out) */
+	{ VW_ERROR_NON_FATAL, 0x05, 0x04 },
+	{ VW_PERIPHERAL_BTLD_STATUS_DONE, 0x05, 0x09 },
+	{ VW_SCI_L, 0x06, 0x01 }, /* index 06h (Out) */
+	{ VW_SMI_L, 0x06, 0x02 },
+	{ VW_RCIN_L, 0x06, 0x04 },
+	{ VW_HOST_RST_ACK, 0x06, 0x08 },
+	{ VW_HOST_RST_WARN, 0x07, 0x01 }, /* index 07h (In)  */
+	{ VW_SUS_ACK, 0x40, 0x01 }, /* index 40h (Out) */
+	{ VW_SUS_WARN_L, 0x41, 0x01 }, /* index 41h (In)  */
+	{ VW_SUS_PWRDN_ACK_L, 0x41, 0x02 },
+	{ VW_SLP_A_L, 0x41, 0x08 },
+	{ VW_SLP_LAN, 0x42, 0x01 }, /* index 42h (In)  */
+	{ VW_SLP_WLAN, 0x42, 0x02 },
 };
 
-/* Flag for SLAVE_BOOT_LOAD siganls */
+/* Flag for boot load signals */
 static uint8_t boot_load_done;
 
 /*****************************************************************************/
@@ -145,11 +150,11 @@ static void espi_reset_recovery(void)
 	boot_load_done = 0;
 }
 
-/* Configure Master-to-Slave virtual wire inputs */
+/* Configure Controller-to-Peripheral virtual wire inputs */
 static void espi_vw_config_in(const struct vwevms_config_t *config)
 {
 	uint32_t val;
-	uint8_t  i, index;
+	uint8_t i, index;
 
 	switch (VM_TYPE(config->idx)) {
 	case ESPI_VW_TYPE_SYS_EV:
@@ -160,11 +165,10 @@ static void espi_vw_config_in(const struct vwevms_config_t *config)
 			if (index == config->idx) {
 				/* Get Wire field */
 				val = NPCX_VWEVMS(i) & 0x0F;
-				val |= VWEVMS_FIELD(config->idx,
-						config->idx_en,
-						config->pltrst_en,
-						config->int_en,
-						config->espirst_en);
+				val |= VWEVMS_FIELD(config->idx, config->idx_en,
+						    config->pltrst_en,
+						    config->int_en,
+						    config->espirst_en);
 				NPCX_VWEVMS(i) = val;
 				return;
 			}
@@ -177,7 +181,7 @@ static void espi_vw_config_in(const struct vwevms_config_t *config)
 	}
 }
 
-/* Configure Slave-to-Master virtual wire outputs */
+/* Configure Peripheral-to-Controller virtual wire outputs */
 static void espi_vw_config_out(const struct vwevsm_config_t *config)
 {
 	uint32_t val;
@@ -192,11 +196,10 @@ static void espi_vw_config_out(const struct vwevsm_config_t *config)
 			if (index == config->idx) {
 				/* Preserve WIRE(3-0) and HW_WIRE (27-24). */
 				val = NPCX_VWEVSM(i) & 0x0F00000F;
-				val |= VWEVSM_FIELD(config->idx,
-						config->idx_en,
-						config->valid,
-						config->pltrst_en,
-						config->cdrst_en);
+				val |= VWEVSM_FIELD(config->idx, config->idx_en,
+						    config->valid,
+						    config->pltrst_en,
+						    config->cdrst_en);
 				NPCX_VWEVSM(i) = val;
 				return;
 			}
@@ -209,13 +212,13 @@ static void espi_vw_config_out(const struct vwevsm_config_t *config)
 	}
 }
 
-/* Config Master-to-Slave VWire interrupt edge type and enable it */
+/* Config Controller-to-Peripheral VWire interrupt edge type and enable it */
 static void espi_enable_vw_int(const struct host_wui_item *vwire_int)
 {
 	uint8_t table = vwire_int->table;
 	uint8_t group = vwire_int->group;
-	uint8_t num   = vwire_int->num;
-	uint8_t edge  = vwire_int->edge;
+	uint8_t num = vwire_int->num;
+	uint8_t edge = vwire_int->edge;
 
 	/* Set detection mode to edge */
 	CLEAR_BIT(NPCX_WKMOD(table, group), num);
@@ -262,7 +265,35 @@ void espi_vw_power_signal_interrupt(enum espi_vw_signal signal)
 {
 	if (IS_ENABLED(CONFIG_HOST_ESPI_VW_POWER_SIGNAL))
 		/* TODO: Add VW handler in power/common.c */
-		power_signal_interrupt((enum gpio_signal) signal);
+		power_signal_interrupt((enum gpio_signal)signal);
+}
+
+void espi_wait_vw_not_dirty(enum espi_vw_signal signal, unsigned int timeout_us)
+{
+	int sig_idx;
+	uint8_t offset;
+	uint64_t timeout;
+
+	sig_idx = espi_vw_get_signal_index(signal);
+	/* Cannot find signal index */
+	if (sig_idx < 0)
+		return;
+
+	for (offset = 0; offset < ESPI_VWEVSM_NUM; offset++) {
+		uint8_t vw_idx = VWEVSM_IDX_GET(NPCX_VWEVSM(offset));
+
+		if (vw_idx == vw_events_list[sig_idx].evt_idx)
+			break;
+	}
+
+	if (offset == ESPI_VWEVSM_NUM)
+		return;
+
+	timeout = get_time().val + (uint64_t)timeout_us;
+	while ((NPCX_VWEVSM(offset) & VWEVSM_DIRTY(1)) &&
+	       (get_time().val < timeout)) {
+		udelay(10);
+	}
 }
 
 /*****************************************************************************/
@@ -408,22 +439,35 @@ void espi_vw_evt_pltrst(void)
 
 	if (pltrst) {
 		/* PLTRST# deasserted */
+#if defined(CHIP_FAMILY_NPCX5)
+		/* See errata 2.22 */
+
 		/* Disable eSPI peripheral channel support first */
 		CLEAR_BIT(NPCX_ESPICFG, NPCX_ESPICFG_PCCHN_SUPP);
 
+		/* Initialize host settings */
+		host_register_init();
+
 		/* Enable eSPI peripheral channel */
 		SET_BIT(NPCX_ESPICFG, NPCX_ESPICFG_PCHANEN);
 
+		/* Re-enable eSPI peripheral channel support */
+		SET_BIT(NPCX_ESPICFG, NPCX_ESPICFG_PCCHN_SUPP);
+#else
 		/* Initialize host settings */
 		host_register_init();
 
-		/* Re-enable eSPI peripheral channel support */
-		SET_BIT(NPCX_ESPICFG, NPCX_ESPICFG_PCCHN_SUPP);
+		/* Enable eSPI peripheral channel */
+		SET_BIT(NPCX_ESPICFG, NPCX_ESPICFG_PCHANEN);
+#endif
+		update_ap_boot_time(PLTRST_HIGH);
+
 	} else {
 		/* PLTRST# asserted */
 #ifdef CONFIG_CHIPSET_RESET_HOOK
 		hook_call_deferred(&espi_chipset_reset_data, MSEC);
 #endif
+		update_ap_boot_time(PLTRST_LOW);
 	}
 }
 
@@ -484,11 +528,13 @@ void espi_espirst_handler(void)
 	/* Clear pending bit of WUI */
 	SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_5), 5);
 
+	update_ap_boot_time(ESPIRST);
+
 	CPRINTS("eSPI RST issued!");
 }
 
 /* Handle eSPI virtual wire interrupt 1 */
-void __espi_wk2a_interrupt(void)
+static void __espi_wk2a_interrupt(void)
 {
 	uint8_t pending_bits = NPCX_WKPND(MIWU_TABLE_2, MIWU_GROUP_1);
 
@@ -510,7 +556,7 @@ void __espi_wk2a_interrupt(void)
 DECLARE_IRQ(NPCX_IRQ_WKINTA_2, __espi_wk2a_interrupt, 3);
 
 /* Handle eSPI virtual wire interrupt 2 */
-void __espi_wk2b_interrupt(void)
+static void __espi_wk2b_interrupt(void)
 {
 	uint8_t pending_bits = NPCX_WKPND(MIWU_TABLE_2, MIWU_GROUP_2);
 
@@ -526,7 +572,7 @@ void __espi_wk2b_interrupt(void)
 DECLARE_IRQ(NPCX_IRQ_WKINTB_2, __espi_wk2b_interrupt, 3);
 
 /* Interrupt handler for eSPI status changed */
-void espi_interrupt(void)
+static void espi_interrupt(void)
 {
 	int chan;
 	uint32_t mask, status;
@@ -547,7 +593,8 @@ void espi_interrupt(void)
 		NPCX_ESPISTS = status;
 
 		if (IS_BIT_SET(status, NPCX_ESPISTS_BERR))
-			CPRINTS("eSPI Bus Error");
+			/* Always print eSPI Bus Errors */
+			cprints(CC_LPC, "eSPI Bus Error");
 
 		/* eSPI inband reset(from VW) */
 		if (IS_BIT_SET(status, NPCX_ESPISTS_IBRST)) {
@@ -569,24 +616,24 @@ void espi_interrupt(void)
 			 * handled by PLTRST separately.
 			 */
 			for (chan = NPCX_ESPI_CH_VW; chan < NPCX_ESPI_CH_COUNT;
-					chan++) {
-				if (!IS_SLAVE_CHAN_ENABLE(chan) &&
-						IS_HOST_CHAN_EN(chan))
+			     chan++) {
+				if (!IS_PERIPHERAL_CHAN_ENABLE(chan) &&
+				    IS_HOST_CHAN_EN(chan))
 					ENABLE_ESPI_CHAN(chan);
-				else if (IS_SLAVE_CHAN_ENABLE(chan) &&
-						!IS_HOST_CHAN_EN(chan))
+				else if (IS_PERIPHERAL_CHAN_ENABLE(chan) &&
+					 !IS_HOST_CHAN_EN(chan))
 					DISABLE_ESPI_CHAN(chan);
 			}
 
 			/*
-			 * Send SLAVE_BOOTLOAD_DONE and SLAVE_BOOTLOAD_STATUS
+			 * Send BOOTLOAD_DONE and BOOTLOAD_STATUS
 			 * events to host simultaneously. To indicate the
 			 * completion of EC firmware code loading.
 			 */
 			if (boot_load_done == 0 &&
-					IS_SLAVE_CHAN_ENABLE(NPCX_ESPI_CH_VW)) {
-
-				espi_vw_set_wire(VW_SLAVE_BTLD_STATUS_DONE, 1);
+			    IS_PERIPHERAL_CHAN_ENABLE(NPCX_ESPI_CH_VW)) {
+				espi_vw_set_wire(VW_PERIPHERAL_BTLD_STATUS_DONE,
+						 1);
 				boot_load_done = 1;
 			}
 		}
@@ -607,22 +654,31 @@ void espi_init(void)
 {
 	int i;
 
+	if (IS_ENABLED(NPCX_ESPI_BYPASS_CH_ENABLE_FATAL_ERROR)) {
+		/* Enable the access to the NPCX_ONLY_ESPI_REG2 register */
+		NPCX_ONLY_ESPI_REG1 = NPCX_ONLY_ESPI_REG1_UNLOCK_REG2;
+		CLEAR_BIT(NPCX_ONLY_ESPI_REG2,
+			  NPCX_ONLY_ESPI_REG2_TRANS_END_CONFIG);
+		/* Disable the access to the NPCX_ONLY_ESPI_REG2 register */
+		NPCX_ONLY_ESPI_REG1 = NPCX_ONLY_ESPI_REG1_LOCK_REG2;
+	}
+
 	/* Support all channels */
 	NPCX_ESPICFG |= ESPI_SUPP_CH_ALL;
 
 	/* Support all I/O modes */
 	SET_FIELD(NPCX_ESPICFG, NPCX_ESPICFG_IOMODE_FIELD,
-		NPCX_ESPI_IO_MODE_ALL);
+		  NPCX_ESPI_IO_MODE_ALL);
 
 	/* Set eSPI speed to max supported */
 	SET_FIELD(NPCX_ESPICFG, NPCX_ESPICFG_MAXFREQ_FIELD,
 		  NPCX_ESPI_MAXFREQ_MAX);
 
-	/* Configure Master-to-Slave Virtual Wire indexes (Inputs) */
+	/* Configure Controller-to-Peripheral Virtual Wire indexes (Inputs) */
 	for (i = 0; i < ARRAY_SIZE(espi_in_list); i++)
 		espi_vw_config_in(&espi_in_list[i]);
 
-	/* Configure Slave-to-Master Virtual Wire indexes (Outputs) */
+	/* Configure Peripheral-to-Controller Virtual Wire indexes (Outputs) */
 	for (i = 0; i < ARRAY_SIZE(espi_out_list); i++)
 		espi_vw_config_out(&espi_out_list[i]);
 
@@ -631,14 +687,14 @@ void espi_init(void)
 		espi_enable_vw_int(&espi_vw_int_list[i]);
 }
 
-static int command_espi(int argc, char **argv)
+static int command_espi(int argc, const char **argv)
 {
 	uint32_t chan;
 	char *e;
 
 	if (argc == 1) {
 		return EC_ERROR_INVAL;
-	/* Get value of eSPI registers */
+		/* Get value of eSPI registers */
 	} else if (argc == 2) {
 		int i;
 
@@ -647,23 +703,23 @@ static int command_espi(int argc, char **argv)
 		} else if (strcasecmp(argv[1], "vsm") == 0) {
 			for (i = 0; i < ESPI_VWEVSM_NUM; i++) {
 				uint32_t val = NPCX_VWEVSM(i);
-				uint8_t  idx = VWEVSM_IDX_GET(val);
+				uint8_t idx = VWEVSM_IDX_GET(val);
 
 				ccprintf("VWEVSM%d: %02x [0x%08x]\n", i, idx,
-						val);
+					 val);
 			}
 		} else if (strcasecmp(argv[1], "vms") == 0) {
 			for (i = 0; i < ESPI_VWEVMS_NUM; i++) {
 				uint32_t val = NPCX_VWEVMS(i);
-				uint8_t  idx = VWEVMS_IDX_GET(val);
+				uint8_t idx = VWEVMS_IDX_GET(val);
 
 				ccprintf("VWEVMS%d: %02x [0x%08x]\n", i, idx,
-						val);
+					 val);
 			}
 		}
-	/* Enable/Disable the channels of eSPI */
+		/* Enable/Disable the channels of eSPI */
 	} else if (argc == 3) {
-		uint32_t m = (uint32_t) strtoi(argv[2], &e, 0);
+		uint32_t m = (uint32_t)strtoi(argv[2], &e, 0);
 
 		if (*e)
 			return EC_ERROR_PARAM2;
@@ -683,6 +739,5 @@ static int command_espi(int argc, char **argv)
 	}
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(espi, command_espi,
-			"cfg/vms/vsm/en/dis [channel]",
+DECLARE_CONSOLE_COMMAND(espi, command_espi, "cfg/vms/vsm/en/dis [channel]",
 			"eSPI configurations");
diff --git a/chip/npcx/fan.c b/chip/npcx/fan.c
index f0b3215ce0..9ceccaba33 100644
--- a/chip/npcx/fan.c
+++ b/chip/npcx/fan.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,25 +7,24 @@
 
 #include "clock.h"
 #include "clock_chip.h"
+#include "console.h"
 #include "fan.h"
 #include "fan_chip.h"
 #include "gpio.h"
 #include "hooks.h"
-#include "registers.h"
-#include "util.h"
+#include "math_util.h"
 #include "pwm.h"
 #include "pwm_chip.h"
-#include "console.h"
-#include "timer.h"
-#include "task.h"
-#include "hooks.h"
+#include "registers.h"
 #include "system.h"
-#include "math_util.h"
+#include "task.h"
+#include "timer.h"
+#include "util.h"
 
 #if !(DEBUG_FAN)
 #define CPRINTS(...)
 #else
-#define CPRINTS(format, args...) cprints(CC_PWM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_PWM, format, ##args)
 #endif
 
 /* Tacho measurement state */
@@ -92,7 +91,7 @@ static int rpm_pre[FAN_CH_COUNT];
 #define TACHO_MAX_CNT (BIT(16) - 1)
 
 /* Margin of target rpm */
-#define RPM_MARGIN(rpm_target) (((rpm_target) * RPM_DEVIATION) / 100)
+#define RPM_MARGIN(rpm_target) (((rpm_target)*RPM_DEVIATION) / 100)
 
 /**
  * MFT get fan rpm value
@@ -144,7 +143,7 @@ static int mft_fan_rpm(int ch)
 /**
  * Set fan prescaler based on apb1 clock
  *
- * @param   none
+ * @param   ch      operation channel
  * @return  none
  * @notes   changed when initial or HOOK_FREQ_CHANGE command
  */
@@ -154,14 +153,14 @@ void mft_set_apb1_prescaler(int ch)
 	uint16_t prescaler_divider = 0;
 
 	/* Set clock prescaler divider to MFT module*/
-	prescaler_divider = (uint16_t)(clock_get_apb1_freq()
-			/ fan_status[ch].mft_freq);
+	prescaler_divider =
+		(uint16_t)(clock_get_apb1_freq() / fan_status[ch].mft_freq);
 	if (prescaler_divider >= 1)
 		prescaler_divider = prescaler_divider - 1;
 	if (prescaler_divider > 0xFF)
 		prescaler_divider = 0xFF;
 
-	NPCX_TPRSC(mdl) = (uint8_t) prescaler_divider;
+	NPCX_TPRSC(mdl) = (uint8_t)prescaler_divider;
 }
 
 /**
@@ -184,7 +183,6 @@ static void fan_config(int ch, int enable_mft_read_rpm)
 
 	/* Need to initialize MFT or not */
 	if (enable_mft_read_rpm) {
-
 		/* Initialize tacho sampling rate */
 		if (clk_src == TCKC_LFCLK)
 			p_status->mft_freq = INT_32K_CLOCK;
@@ -195,7 +193,7 @@ static void fan_config(int ch, int enable_mft_read_rpm)
 
 		/* Set mode 5 to MFT module */
 		SET_FIELD(NPCX_TMCTRL(mdl), NPCX_TMCTRL_MDSEL_FIELD,
-				NPCX_MFT_MDSEL_5);
+			  NPCX_MFT_MDSEL_5);
 
 		/* Set MFT operation frequency */
 		if (clk_src == TCKC_PRESCALE_APB1_CLK)
@@ -203,11 +201,11 @@ static void fan_config(int ch, int enable_mft_read_rpm)
 
 		/* Set the low power mode or not. */
 		UPDATE_BIT(NPCX_TCKC(mdl), NPCX_TCKC_LOW_PWR,
-				clk_src == TCKC_LFCLK);
+			   clk_src == TCKC_LFCLK);
 
 		/* Set the default count-down timer. */
 		NPCX_TCNT1(mdl) = TACHO_MAX_CNT;
-		NPCX_TCRA(mdl)  = TACHO_MAX_CNT;
+		NPCX_TCRA(mdl) = TACHO_MAX_CNT;
 
 		/* Set the edge polarity to rising. */
 		SET_BIT(NPCX_TMCTRL(mdl), NPCX_TMCTRL_TAEDG);
@@ -293,11 +291,22 @@ enum fan_status fan_smart_control(int ch, int rpm_actual, int rpm_target)
 		return FAN_STATUS_CHANGING;
 	}
 
+	/*
+	 * A specific type of fan needs a longer time to output the TACH
+	 * signal to EC after EC outputs the PWM signal to the fan.
+	 * During this period, the driver will read two consecutive RPM = 0.
+	 * In this case, don't step the PWM duty too aggressively.
+	 * See b:225208265 for more detail.
+	 */
+	if (rpm_pre[ch] == 0 && rpm_actual == 0 &&
+	    IS_ENABLED(CONFIG_FAN_BYPASS_SLOW_RESPONSE)) {
+		rpm_diff = RPM_MARGIN(rpm_target) + 1;
+	} else {
+		rpm_diff = rpm_target - rpm_actual;
+	}
+
 	/* Record previous rpm */
 	rpm_pre[ch] = rpm_actual;
-
-	/* Adjust PWM duty */
-	rpm_diff = rpm_target - rpm_actual;
 	duty = fan_get_duty(ch);
 	if (duty == 0 && rpm_target == 0)
 		return FAN_STATUS_STOPPED;
@@ -309,7 +318,7 @@ enum fan_status fan_smart_control(int ch, int rpm_actual, int rpm_target)
 
 		fan_adjust_duty(ch, rpm_diff, duty);
 		return FAN_STATUS_CHANGING;
-	/* Decrease PWM duty */
+		/* Decrease PWM duty */
 	} else if (rpm_diff < -RPM_MARGIN(rpm_target)) {
 		if (duty == 1 && rpm_target != 0)
 			return FAN_STATUS_FRUSTRATED;
@@ -330,11 +339,12 @@ void fan_tick_func(void)
 {
 	int ch;
 
-	for (ch = 0; ch < FAN_CH_COUNT ; ch++) {
+	for (ch = 0; ch < FAN_CH_COUNT; ch++) {
 		volatile struct fan_status_t *p_status = fan_status + ch;
 		/* Make sure rpm mode is enabled */
 		if (p_status->fan_mode != TACHO_FAN_RPM) {
-		/* Fan in duty mode still want rpm_actual being updated. */
+			/* Fan in duty mode still want rpm_actual being updated.
+			 */
 			p_status->rpm_actual = mft_fan_rpm(ch);
 			if (p_status->rpm_actual > 0)
 				p_status->auto_status = FAN_STATUS_LOCKED;
@@ -347,8 +357,8 @@ void fan_tick_func(void)
 		/* Get actual rpm */
 		p_status->rpm_actual = mft_fan_rpm(ch);
 		/* Do smart fan stuff */
-		p_status->auto_status = fan_smart_control(ch,
-				p_status->rpm_actual, p_status->rpm_target);
+		p_status->auto_status = fan_smart_control(
+			ch, p_status->rpm_actual, p_status->rpm_target);
 	}
 }
 DECLARE_HOOK(HOOK_TICK, fan_tick_func, HOOK_PRIO_DEFAULT);
@@ -520,7 +530,7 @@ enum fan_status fan_get_status(int ch)
 int fan_is_stalled(int ch)
 {
 	return fan_get_enabled(ch) && fan_get_duty(ch) &&
-			fan_status[ch].cur_state == TACHO_UNDERFLOW;
+	       fan_status[ch].cur_state == TACHO_UNDERFLOW;
 }
 
 /**
diff --git a/chip/npcx/fan_chip.h b/chip/npcx/fan_chip.h
index bc97011895..36eb13f4cb 100644
--- a/chip/npcx/fan_chip.h
+++ b/chip/npcx/fan_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -32,7 +32,7 @@ enum npcx_mft_module {
 enum npcx_mft_clk_src {
 	TCKC_NOCLK = 0,
 	TCKC_PRESCALE_APB1_CLK = 1,
-	TCKC_LFCLK = 5,
+	TCKC_LFCLK = 4,
 };
 
 /* Data structure to define MFT channels. */
diff --git a/chip/npcx/flash.c b/chip/npcx/flash.c
index 7afb413c2c..dc8de6e3ee 100644
--- a/chip/npcx/flash.c
+++ b/chip/npcx/flash.c
@@ -1,27 +1,27 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Flash memory module for Chrome EC */
 
+#include "builtin/assert.h"
+#include "console.h"
 #include "flash.h"
 #include "host_command.h"
+#include "hwtimer_chip.h"
 #include "registers.h"
 #include "spi_flash_reg.h"
 #include "switch.h"
 #include "system.h"
+#include "task.h"
 #include "timer.h"
 #include "util.h"
-#include "task.h"
 #include "watchdog.h"
-#include "console.h"
-#include "hwtimer_chip.h"
 
 static int all_protected; /* Has all-flash protection been requested? */
 static int addr_prot_start;
 static int addr_prot_length;
-static uint8_t flag_prot_inconsistent;
 
 /* SR regs aren't readable when UMA lock is on, so save a copy */
 static uint8_t saved_sr1;
@@ -69,7 +69,7 @@ static void flash_execute_cmd(uint8_t code, uint8_t cts)
 	/* set UMA_CODE */
 	NPCX_UMA_CODE = code;
 	/* execute UMA flash transaction */
-	NPCX_UMA_CTS  = cts;
+	NPCX_UMA_CTS = cts;
 	while (IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE))
 		;
 }
@@ -95,7 +95,7 @@ static int flash_wait_ready(void)
 	flash_execute_cmd(CMD_READ_STATUS_REG, MASK_CMD_ONLY);
 	do {
 		/* Read status register */
-		NPCX_UMA_CTS  = MASK_RD_1BYTE;
+		NPCX_UMA_CTS = MASK_RD_1BYTE;
 		while (IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE))
 			;
 		/* Busy bit is clear */
@@ -145,54 +145,70 @@ static void flash_set_address(uint32_t dest_addr)
 	NPCX_UMA_AB0 = addr[0];
 }
 
-static uint8_t flash_get_status1(void)
+static void flash_get_status(uint8_t *sr1, uint8_t *sr2)
 {
-	uint8_t ret;
-
-	if (all_protected)
-		return saved_sr1;
+	if (all_protected) {
+		*sr1 = saved_sr1;
+		*sr2 = saved_sr2;
+		return;
+	}
 
 	/* Lock physical flash operations */
-	flash_lock_mapped_storage(1);
+	crec_flash_lock_mapped_storage(1);
 
 	/* Disable tri-state */
 	TRISTATE_FLASH(0);
 	/* Read status register1 */
 	flash_execute_cmd(CMD_READ_STATUS_REG, MASK_CMD_RD_1BYTE);
+	*sr1 = NPCX_UMA_DB0;
+	/* Read status register2 */
+	flash_execute_cmd(CMD_READ_STATUS_REG2, MASK_CMD_RD_1BYTE);
+	*sr2 = NPCX_UMA_DB0;
 	/* Enable tri-state */
 	TRISTATE_FLASH(1);
 
-	ret = NPCX_UMA_DB0;
-
 	/* Unlock physical flash operations */
-	flash_lock_mapped_storage(0);
-
-	return ret;
+	crec_flash_lock_mapped_storage(0);
 }
 
-static uint8_t flash_get_status2(void)
+static void flash_set_status(uint8_t sr1, uint8_t sr2)
 {
-	uint8_t ret;
-
-	if (all_protected)
-		return saved_sr2;
-
 	/* Lock physical flash operations */
-	flash_lock_mapped_storage(1);
+	crec_flash_lock_mapped_storage(1);
 
 	/* Disable tri-state */
 	TRISTATE_FLASH(0);
-	/* Read status register2 */
-	flash_execute_cmd(CMD_READ_STATUS_REG2, MASK_CMD_RD_1BYTE);
+	/* Enable write */
+	flash_write_enable();
+
+	NPCX_UMA_DB0 = sr1;
+	NPCX_UMA_DB1 = sr2;
+
+	/* Write status register 1/2 */
+	flash_execute_cmd(CMD_WRITE_STATUS_REG, MASK_CMD_WR_2BYTE);
 	/* Enable tri-state */
 	TRISTATE_FLASH(1);
 
-	ret = NPCX_UMA_DB0;
-
 	/* Unlock physical flash operations */
-	flash_lock_mapped_storage(0);
+	crec_flash_lock_mapped_storage(0);
+}
 
-	return ret;
+static void flash_set_quad_enable(int enable)
+{
+	uint8_t sr1, sr2;
+
+	flash_get_status(&sr1, &sr2);
+
+	/* If QE is the same value, return directly. */
+	if (!!(sr2 & SPI_FLASH_SR2_QE) == enable)
+		return;
+
+	if (enable)
+		sr2 |= SPI_FLASH_SR2_QE;
+	else
+		sr2 &= ~SPI_FLASH_SR2_QE;
+
+	flash_set_status(sr1, sr2);
 }
 
 #ifdef NPCX_INT_FLASH_SUPPORT
@@ -217,7 +233,7 @@ static void flash_protect_int_flash(int enable)
 void flash_get_mfr_dev_id(uint8_t *dest)
 {
 	/* Lock physical flash operations */
-	flash_lock_mapped_storage(1);
+	crec_flash_lock_mapped_storage(1);
 
 	/* Disable tri-state */
 	TRISTATE_FLASH(0);
@@ -232,7 +248,7 @@ void flash_get_mfr_dev_id(uint8_t *dest)
 	dest[1] = NPCX_UMA_DB1;
 
 	/* Unlock physical flash operations */
-	flash_lock_mapped_storage(0);
+	crec_flash_lock_mapped_storage(0);
 }
 
 #endif /* CONFIG_HOSTCMD_FLASH_SPI_INFO */
@@ -240,7 +256,7 @@ void flash_get_mfr_dev_id(uint8_t *dest)
 void flash_get_jedec_id(uint8_t *dest)
 {
 	/* Lock physical flash operations */
-	flash_lock_mapped_storage(1);
+	crec_flash_lock_mapped_storage(1);
 
 	/* Disable tri-state */
 	TRISTATE_FLASH(0);
@@ -254,7 +270,7 @@ void flash_get_jedec_id(uint8_t *dest)
 	dest[2] = NPCX_UMA_DB2;
 
 	/* Unlock physical flash operations */
-	flash_lock_mapped_storage(0);
+	crec_flash_lock_mapped_storage(0);
 }
 
 static void flash_uma_lock(int enable)
@@ -264,8 +280,7 @@ static void flash_uma_lock(int enable)
 		 * Store SR1 / SR2 for later use since we're about to lock
 		 * out all access (including read access) to these regs.
 		 */
-		saved_sr1 = flash_get_status1();
-		saved_sr2 = flash_get_status2();
+		flash_get_status(&saved_sr1, &saved_sr2);
 	}
 
 	all_protected = enable;
@@ -284,7 +299,7 @@ static int flash_set_status_for_prot(int reg1, int reg2)
 			return EC_ERROR_ACCESS_DENIED;
 #endif
 
-		if (flash_get_protect() & EC_FLASH_PROTECT_GPIO_ASSERTED)
+		if (crec_flash_get_protect() & EC_FLASH_PROTECT_GPIO_ASSERTED)
 			return EC_ERROR_ACCESS_DENIED;
 		flash_uma_lock(0);
 	}
@@ -300,28 +315,10 @@ static int flash_set_status_for_prot(int reg1, int reg2)
 	flash_protect_int_flash(!gpio_get_level(GPIO_WP_L));
 #endif /*_CONFIG_WP_ACTIVE_HIGH_*/
 #endif
+	flash_set_status(reg1, reg2);
 
-	/* Lock physical flash operations */
-	flash_lock_mapped_storage(1);
-
-	/* Disable tri-state */
-	TRISTATE_FLASH(0);
-	/* Enable write */
-	flash_write_enable();
-
-	NPCX_UMA_DB0 = reg1;
-	NPCX_UMA_DB1 = reg2;
-
-	/* Write status register 1/2 */
-	flash_execute_cmd(CMD_WRITE_STATUS_REG, MASK_CMD_WR_2BYTE);
-	/* Enable tri-state */
-	TRISTATE_FLASH(1);
-
-	/* Unlock physical flash operations */
-	flash_lock_mapped_storage(0);
-
-	spi_flash_reg_to_protect(reg1, reg2,
-				 &addr_prot_start, &addr_prot_length);
+	spi_flash_reg_to_protect(reg1, reg2, &addr_prot_start,
+				 &addr_prot_length);
 
 	return EC_SUCCESS;
 }
@@ -329,11 +326,11 @@ static int flash_set_status_for_prot(int reg1, int reg2)
 static int flash_check_prot_range(unsigned int offset, unsigned int bytes)
 {
 	/* Invalid value */
-	if (offset + bytes > CONFIG_FLASH_SIZE)
+	if (offset + bytes > CONFIG_FLASH_SIZE_BYTES)
 		return EC_ERROR_INVAL;
 	/* Check if ranges overlap */
-	if (MAX(addr_prot_start, offset) < MIN(addr_prot_start +
-		addr_prot_length, offset + bytes))
+	if (MAX(addr_prot_start, offset) <
+	    MIN(addr_prot_start + addr_prot_length, offset + bytes))
 		return EC_ERROR_ACCESS_DENIED;
 
 	return EC_SUCCESS;
@@ -358,14 +355,12 @@ static int flash_check_prot_reg(unsigned int offset, unsigned int bytes)
 #endif /* CONFIG_WP_ACTIVE_HIGH */
 #endif
 
-	sr1 = flash_get_status1();
-	sr2 = flash_get_status2();
-
 	/* Invalid value */
-	if (offset + bytes > CONFIG_FLASH_SIZE)
+	if (offset + bytes > CONFIG_FLASH_SIZE_BYTES)
 		return EC_ERROR_INVAL;
 
 	/* Compute current protect range */
+	flash_get_status(&sr1, &sr2);
 	rv = spi_flash_reg_to_protect(sr1, sr2, &start, &len);
 	if (rv)
 		return rv;
@@ -375,21 +370,20 @@ static int flash_check_prot_reg(unsigned int offset, unsigned int bytes)
 		return EC_ERROR_ACCESS_DENIED;
 
 	return EC_SUCCESS;
-
 }
 
 static int flash_write_prot_reg(unsigned int offset, unsigned int bytes,
 				int hw_protect)
 {
 	int rv;
-	uint8_t sr1 = flash_get_status1();
-	uint8_t sr2 = flash_get_status2();
+	uint8_t sr1, sr2;
 
 	/* Invalid values */
-	if (offset + bytes > CONFIG_FLASH_SIZE)
+	if (offset + bytes > CONFIG_FLASH_SIZE_BYTES)
 		return EC_ERROR_INVAL;
 
 	/* Compute desired protect range */
+	flash_get_status(&sr1, &sr2);
 	rv = spi_flash_protect_to_reg(offset, bytes, &sr1, &sr2);
 	if (rv)
 		return rv;
@@ -401,7 +395,7 @@ static int flash_write_prot_reg(unsigned int offset, unsigned int bytes,
 }
 
 static void flash_burst_write(unsigned int dest_addr, unsigned int bytes,
-		const char *data)
+			      const char *data)
 {
 	unsigned int i;
 	/* Chip Select down */
@@ -419,15 +413,17 @@ static void flash_burst_write(unsigned int dest_addr, unsigned int bytes,
 }
 
 static int flash_program_bytes(uint32_t offset, uint32_t bytes,
-	const uint8_t *data)
+			       const uint8_t *data)
 {
 	int write_size;
 	int rv;
 
 	while (bytes > 0) {
 		/* Write length can not go beyond the end of the flash page */
-		write_size = MIN(bytes, CONFIG_FLASH_WRITE_IDEAL_SIZE -
-		(offset & (CONFIG_FLASH_WRITE_IDEAL_SIZE - 1)));
+		write_size = MIN(bytes,
+				 CONFIG_FLASH_WRITE_IDEAL_SIZE -
+					 (offset &
+					  (CONFIG_FLASH_WRITE_IDEAL_SIZE - 1)));
 
 		/* Enable write */
 		rv = flash_write_enable();
@@ -442,9 +438,9 @@ static int flash_program_bytes(uint32_t offset, uint32_t bytes,
 		if (rv)
 			return rv;
 
-		data   += write_size;
+		data += write_size;
 		offset += write_size;
-		bytes  -= write_size;
+		bytes -= write_size;
 	}
 
 	return rv;
@@ -452,13 +448,13 @@ static int flash_program_bytes(uint32_t offset, uint32_t bytes,
 
 /*****************************************************************************/
 
-int flash_physical_read(int offset, int size, char *data)
+int crec_flash_physical_read(int offset, int size, char *data)
 {
 	int dest_addr = offset;
 	uint32_t idx;
 
 	/* Lock physical flash operations */
-	flash_lock_mapped_storage(1);
+	crec_flash_lock_mapped_storage(1);
 
 	/* Disable tri-state */
 	TRISTATE_FLASH(0);
@@ -473,7 +469,7 @@ int flash_physical_read(int offset, int size, char *data)
 	/* Burst read transaction */
 	for (idx = 0; idx < size; idx++) {
 		/* 1101 0101 - EXEC, RD, NO CMD, NO ADDR, 4 bytes */
-		NPCX_UMA_CTS  = MASK_RD_1BYTE;
+		NPCX_UMA_CTS = MASK_RD_1BYTE;
 		/* wait for UMA to complete */
 		while (IS_BIT_SET(NPCX_UMA_CTS, EXEC_DONE))
 			;
@@ -487,20 +483,20 @@ int flash_physical_read(int offset, int size, char *data)
 	TRISTATE_FLASH(1);
 
 	/* Unlock physical flash operations */
-	flash_lock_mapped_storage(0);
+	crec_flash_lock_mapped_storage(0);
 
 	return EC_SUCCESS;
 }
 
-int flash_physical_write(int offset, int size, const char *data)
+int crec_flash_physical_write(int offset, int size, const char *data)
 {
 	int dest_addr = offset;
 	int write_len;
 	int rv;
 
 	/* Fail if offset, size, and data aren't at least word-aligned */
-	if ((offset | size
-	     | (uint32_t)(uintptr_t)data) & (CONFIG_FLASH_WRITE_SIZE - 1))
+	if ((offset | size | (uint32_t)(uintptr_t)data) &
+	    (CONFIG_FLASH_WRITE_SIZE - 1))
 		return EC_ERROR_INVAL;
 
 	/* check protection */
@@ -508,7 +504,7 @@ int flash_physical_write(int offset, int size, const char *data)
 		return EC_ERROR_ACCESS_DENIED;
 
 	/* Lock physical flash operations */
-	flash_lock_mapped_storage(1);
+	crec_flash_lock_mapped_storage(1);
 
 	/* Disable tri-state */
 	TRISTATE_FLASH(0);
@@ -516,7 +512,8 @@ int flash_physical_write(int offset, int size, const char *data)
 	while (size > 0) {
 		/* First write multiples of 256, then (size % 256) last */
 		write_len = ((size % CONFIG_FLASH_WRITE_IDEAL_SIZE) == size) ?
-					size : CONFIG_FLASH_WRITE_IDEAL_SIZE;
+				    size :
+				    CONFIG_FLASH_WRITE_IDEAL_SIZE;
 
 		/* check protection */
 		if (flash_check_prot_range(dest_addr, write_len)) {
@@ -528,21 +525,21 @@ int flash_physical_write(int offset, int size, const char *data)
 		if (rv)
 			break;
 
-		data      += write_len;
+		data += write_len;
 		dest_addr += write_len;
-		size      -= write_len;
+		size -= write_len;
 	}
 
 	/* Enable tri-state */
 	TRISTATE_FLASH(1);
 
 	/* Unlock physical flash operations */
-	flash_lock_mapped_storage(0);
+	crec_flash_lock_mapped_storage(0);
 
 	return rv;
 }
 
-int flash_physical_erase(int offset, int size)
+int crec_flash_physical_erase(int offset, int size)
 {
 	int rv = EC_SUCCESS;
 	/* check protection */
@@ -550,14 +547,14 @@ int flash_physical_erase(int offset, int size)
 		return EC_ERROR_ACCESS_DENIED;
 
 	/* Lock physical flash operations */
-	flash_lock_mapped_storage(1);
+	crec_flash_lock_mapped_storage(1);
 
 	/* Disable tri-state */
 	TRISTATE_FLASH(0);
 
 	/* Alignment has been checked in upper layer */
 	for (; size > 0; size -= CONFIG_FLASH_ERASE_SIZE,
-		offset += CONFIG_FLASH_ERASE_SIZE) {
+			 offset += CONFIG_FLASH_ERASE_SIZE) {
 		/* check protection */
 		if (flash_check_prot_range(offset, CONFIG_FLASH_ERASE_SIZE)) {
 			rv = EC_ERROR_ACCESS_DENIED;
@@ -591,32 +588,42 @@ int flash_physical_erase(int offset, int size)
 	TRISTATE_FLASH(1);
 
 	/* Unlock physical flash operations */
-	flash_lock_mapped_storage(0);
+	crec_flash_lock_mapped_storage(0);
 
 	return rv;
 }
 
-int flash_physical_get_protect(int bank)
+int crec_flash_physical_get_protect(int bank)
 {
 	uint32_t addr = bank * CONFIG_FLASH_BANK_SIZE;
 
 	return flash_check_prot_reg(addr, CONFIG_FLASH_BANK_SIZE);
 }
 
-uint32_t flash_physical_get_protect_flags(void)
+uint32_t crec_flash_physical_get_protect_flags(void)
 {
 	uint32_t flags = 0;
+	uint8_t sr1, sr2;
+	unsigned int start, len;
+	int rv;
 
 	/* Check if WP region is protected in status register */
-	if (flash_check_prot_reg(WP_BANK_OFFSET*CONFIG_FLASH_BANK_SIZE,
-				 WP_BANK_COUNT*CONFIG_FLASH_BANK_SIZE))
+	rv = flash_check_prot_reg(WP_BANK_OFFSET * CONFIG_FLASH_BANK_SIZE,
+				  WP_BANK_COUNT * CONFIG_FLASH_BANK_SIZE);
+	if (rv == EC_ERROR_ACCESS_DENIED)
 		flags |= EC_FLASH_PROTECT_RO_AT_BOOT;
+	else if (rv)
+		return EC_FLASH_PROTECT_ERROR_UNKNOWN;
 
 	/*
-	 * TODO: If status register protects a range, but SRP0 is not set,
-	 * flags should indicate EC_FLASH_PROTECT_ERROR_INCONSISTENT.
+	 * If the status register protects a range, but SRP0 is not set, or QE
+	 * is set, flags should indicate EC_FLASH_PROTECT_ERROR_INCONSISTENT.
 	 */
-	if (flag_prot_inconsistent)
+	flash_get_status(&sr1, &sr2);
+	rv = spi_flash_reg_to_protect(sr1, sr2, &start, &len);
+	if (rv)
+		return EC_FLASH_PROTECT_ERROR_UNKNOWN;
+	if (len && (!(sr1 & SPI_FLASH_SR1_SRP0) || (sr2 & SPI_FLASH_SR2_QE)))
 		flags |= EC_FLASH_PROTECT_ERROR_INCONSISTENT;
 
 	/* Read all-protected state from our shadow copy */
@@ -626,7 +633,7 @@ uint32_t flash_physical_get_protect_flags(void)
 	return flags;
 }
 
-int flash_physical_protect_now(int all)
+int crec_flash_physical_protect_now(int all)
 {
 	if (all) {
 		/*
@@ -641,8 +648,7 @@ int flash_physical_protect_now(int all)
 	return EC_SUCCESS;
 }
 
-
-int flash_physical_protect_at_boot(uint32_t new_flags)
+int crec_flash_physical_protect_at_boot(uint32_t new_flags)
 {
 	int ret;
 
@@ -653,8 +659,7 @@ int flash_physical_protect_at_boot(uint32_t new_flags)
 	}
 
 	ret = flash_write_prot_reg(CONFIG_WP_STORAGE_OFF,
-				   CONFIG_WP_STORAGE_SIZE,
-				   1);
+				   CONFIG_WP_STORAGE_SIZE, 1);
 
 	/*
 	 * Set UMA_LOCK bit for locking all UMA transaction.
@@ -666,14 +671,13 @@ int flash_physical_protect_at_boot(uint32_t new_flags)
 	return ret;
 }
 
-uint32_t flash_physical_get_valid_flags(void)
+uint32_t crec_flash_physical_get_valid_flags(void)
 {
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-			EC_FLASH_PROTECT_RO_NOW |
-			EC_FLASH_PROTECT_ALL_NOW;
+	return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW |
+	       EC_FLASH_PROTECT_ALL_NOW;
 }
 
-uint32_t flash_physical_get_writable_flags(uint32_t cur_flags)
+uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
 {
 	uint32_t ret = 0;
 
@@ -686,7 +690,7 @@ uint32_t flash_physical_get_writable_flags(uint32_t cur_flags)
 	 * the WP GPIO is asserted.
 	 */
 	if (!(cur_flags & EC_FLASH_PROTECT_ALL_NOW) &&
-			(cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED))
+	    (cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED))
 		ret |= EC_FLASH_PROTECT_ALL_NOW;
 
 	return ret;
@@ -695,20 +699,8 @@ uint32_t flash_physical_get_writable_flags(uint32_t cur_flags)
 /*****************************************************************************/
 /* High-level APIs */
 
-int flash_pre_init(void)
+int crec_flash_pre_init(void)
 {
-	/*
-	 * Protect status registers of internal spi-flash if WP# is active
-	 * during ec initialization.
-	 */
-#ifdef NPCX_INT_FLASH_SUPPORT
-#ifdef CONFIG_WP_ACTIVE_HIGH
-	flash_protect_int_flash(gpio_get_level(GPIO_WP));
-#else
-	flash_protect_int_flash(!gpio_get_level(GPIO_WP_L));
-#endif /*CONFIG_WP_ACTIVE_HIGH */
-#endif
-
 #if !defined(NPCX_INT_FLASH_SUPPORT)
 	/* Enable FIU interface */
 	flash_pinmux(1);
@@ -721,10 +713,27 @@ int flash_pre_init(void)
 
 	/* Initialize UMA to unlocked */
 	flash_uma_lock(0);
+
+	/*
+	 * Disable flash quad enable to avoid /WP pin function is not
+	 * available. */
+	flash_set_quad_enable(0);
+
+	/*
+	 * Protect status registers of internal spi-flash if WP# is active
+	 * during ec initialization.
+	 */
+#ifdef NPCX_INT_FLASH_SUPPORT
+#ifdef CONFIG_WP_ACTIVE_HIGH
+	flash_protect_int_flash(gpio_get_level(GPIO_WP));
+#else
+	flash_protect_int_flash(!gpio_get_level(GPIO_WP_L));
+#endif /*CONFIG_WP_ACTIVE_HIGH */
+#endif
 	return EC_SUCCESS;
 }
 
-void flash_lock_mapped_storage(int lock)
+void crec_flash_lock_mapped_storage(int lock)
 {
 	if (lock)
 		mutex_lock(&flash_lock);
@@ -745,14 +754,12 @@ static enum ec_status flash_command_spi_info(struct host_cmd_handler_args *args)
 	flash_get_jedec_id(r->jedec);
 	r->reserved0 = 0;
 	flash_get_mfr_dev_id(r->mfr_dev_id);
-	r->sr1 = flash_get_status1();
-	r->sr2 = flash_get_status2();
+	flash_get_status(&r->sr1, &r->sr2);
 
 	args->response_size = sizeof(*r);
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_FLASH_SPI_INFO,
-		     flash_command_spi_info,
+DECLARE_HOST_COMMAND(EC_CMD_FLASH_SPI_INFO, flash_command_spi_info,
 		     EC_VER_MASK(0));
 
 #endif
@@ -780,7 +787,7 @@ static int flash_spi_sel_lock(int enable)
 /*****************************************************************************/
 /* Console commands */
 
-static int command_flash_spi_sel_lock(int argc, char **argv)
+static int command_flash_spi_sel_lock(int argc, const char **argv)
 {
 	int ena;
 
@@ -793,10 +800,9 @@ static int command_flash_spi_sel_lock(int argc, char **argv)
 	return EC_SUCCESS;
 }
 DECLARE_CONSOLE_COMMAND(flash_spi_lock, command_flash_spi_sel_lock,
-			"[on | off]",
-			"Lock spi flash interface selection");
+			"[on | off]", "Lock spi flash interface selection");
 
-static int command_flash_tristate(int argc, char **argv)
+static int command_flash_tristate(int argc, const char **argv)
 {
 	int ena;
 
@@ -809,24 +815,23 @@ static int command_flash_tristate(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(flash_tristate, command_flash_tristate,
-			"[on | off]",
+DECLARE_CONSOLE_COMMAND(flash_tristate, command_flash_tristate, "[on | off]",
 			"Tristate spi flash pins");
 #endif /* CONFIG_CMD_FLASH_TRISTATE */
 
-static int command_flash_chip(int argc, char **argv)
+static int command_flash_chip(int argc, const char **argv)
 {
 	uint8_t jedec_id[3];
+	uint8_t sr1, sr2;
 
-	ccprintf("Status 1: 0x%02x, Status 2: 0x%02x\n", flash_get_status1(),
-			flash_get_status2());
+	flash_get_status(&sr1, &sr2);
+	ccprintf("Status 1: 0x%02x, Status 2: 0x%02x\n", sr1, sr2);
 
 	flash_get_jedec_id(jedec_id);
 	ccprintf("Manufacturer: 0x%02x, DID: 0x%02x%02x\n", jedec_id[0],
-			jedec_id[1], jedec_id[2]);
+		 jedec_id[1], jedec_id[2]);
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(flashchip, command_flash_chip,
-			NULL,
+DECLARE_CONSOLE_COMMAND(flashchip, command_flash_chip, NULL,
 			"Print flash chip info");
diff --git a/chip/npcx/gpio-npcx5.c b/chip/npcx/gpio-npcx5.c
index d6a28300ba..2201bb65c2 100644
--- a/chip/npcx/gpio-npcx5.c
+++ b/chip/npcx/gpio-npcx5.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -29,7 +29,7 @@ static void gpio_init(void)
 	task_enable_irq(NPCX_IRQ_TWD_WKINTB_0);
 	task_enable_irq(NPCX_IRQ_WKINTA_1);
 	task_enable_irq(NPCX_IRQ_WKINTB_1);
-#ifndef HAS_TASK_KEYSCAN
+#ifdef NPCX_SELECT_KSI_TO_GPIO
 	task_enable_irq(NPCX_IRQ_KSI_WKINTC_1);
 #endif
 	task_enable_irq(NPCX_IRQ_WKINTD_1);
@@ -48,36 +48,38 @@ DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
  * the port, then call the master handler above.
  */
 
-#define GPIO_IRQ_FUNC(_irq_func, wui_int)		\
-void _irq_func(void)					\
-{							\
-	gpio_interrupt(wui_int);			\
-}
+#define GPIO_IRQ_FUNC(_irq_func, wui_int) \
+	static void _irq_func(void)       \
+	{                                 \
+		gpio_interrupt(wui_int);  \
+	}
 
 /* If we need to handle the other type interrupts except GPIO, add code here */
-void __gpio_wk0efgh_interrupt(void)
+static void __gpio_wk0efgh_interrupt(void)
 {
 	if (IS_ENABLED(CONFIG_HOSTCMD_X86)) {
 		/* Pending bit 7 or 6 or 5? */
 		if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6) &&
-			IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 6)) {
+		    IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 6)) {
 			/* Disable host wake-up */
 			CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6);
 			/* Clear pending bit of WUI */
 			SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_5), 6);
 			return;
 		}
-		if (IS_ENABLED(CONFIG_HOSTCMD_ESPI)) {
-			if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 5)
-				&&
-			IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 5)) {
+		if (IS_ENABLED(CONFIG_HOST_INTERFACE_ESPI)) {
+			if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5),
+				       5) &&
+			    IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5),
+				       5)) {
 				espi_espirst_handler();
 				return;
 			}
 		} else {
-			if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 7)
-				&&
-			IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 7)) {
+			if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5),
+				       7) &&
+			    IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5),
+				       7)) {
 				lpc_lreset_pltrst_handler();
 				return;
 			}
@@ -97,7 +99,7 @@ static void set_rtc_host_event(void)
 DECLARE_DEFERRED(set_rtc_host_event);
 #endif
 
-void __gpio_rtc_interrupt(void)
+static void __gpio_rtc_interrupt(void)
 {
 	/* Check pending bit 7 */
 #ifdef CONFIG_HOSTCMD_RTC
@@ -130,7 +132,7 @@ void __gpio_rtc_interrupt(void)
 	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_4));
 }
 
-void __gpio_wk1h_interrupt(void)
+static void __gpio_wk1h_interrupt(void)
 {
 #if defined(CHIP_FAMILY_NPCX7) && defined(CONFIG_LOW_POWER_IDLE) && \
 	(CONFIG_CONSOLE_UART == 0)
@@ -156,7 +158,7 @@ GPIO_IRQ_FUNC(__gpio_wk0b_interrupt, WUI_INT(MIWU_TABLE_0, MIWU_GROUP_2));
 GPIO_IRQ_FUNC(__gpio_wk0c_interrupt, WUI_INT(MIWU_TABLE_0, MIWU_GROUP_3));
 GPIO_IRQ_FUNC(__gpio_wk1a_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_1));
 GPIO_IRQ_FUNC(__gpio_wk1b_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_2));
-#ifndef HAS_TASK_KEYSCAN
+#ifdef NPCX_SELECT_KSI_TO_GPIO
 /* Declare GPIO irq functions for KSI pins if there's no keyboard scan task, */
 GPIO_IRQ_FUNC(__gpio_wk1c_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_3));
 #endif
@@ -169,30 +171,30 @@ GPIO_IRQ_FUNC(__gpio_wk2fg_interrupt, WUI_INT(MIWU_TABLE_2, MIWU_GROUP_6));
 #endif
 
 DECLARE_IRQ(NPCX_IRQ_MTC_WKINTAD_0, __gpio_rtc_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_TWD_WKINTB_0,  __gpio_wk0b_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTC_0,      __gpio_wk0c_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTEFGH_0,   __gpio_wk0efgh_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTA_1,      __gpio_wk1a_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTB_1,      __gpio_wk1b_interrupt, 3);
-#ifndef HAS_TASK_KEYSCAN
-DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1,  __gpio_wk1c_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_TWD_WKINTB_0, __gpio_wk0b_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTC_0, __gpio_wk0c_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTEFGH_0, __gpio_wk0efgh_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTA_1, __gpio_wk1a_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTB_1, __gpio_wk1b_interrupt, 3);
+#ifdef NPCX_SELECT_KSI_TO_GPIO
+DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1, __gpio_wk1c_interrupt, 3);
 #endif
-DECLARE_IRQ(NPCX_IRQ_WKINTD_1,      __gpio_wk1d_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTE_1,      __gpio_wk1e_interrupt, 3);
-#ifdef CONFIG_HOSTCMD_SPS
+DECLARE_IRQ(NPCX_IRQ_WKINTD_1, __gpio_wk1d_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTE_1, __gpio_wk1e_interrupt, 3);
+#ifdef CONFIG_HOST_INTERFACE_SHI
 /*
  * HACK: Make CS GPIO P2 to improve SHI reliability.
  * TODO: Increase CS-assertion-to-transaction-start delay on host to
  * accommodate P3 CS interrupt.
  */
-DECLARE_IRQ(NPCX_IRQ_WKINTF_1,      __gpio_wk1f_interrupt, 2);
+DECLARE_IRQ(NPCX_IRQ_WKINTF_1, __gpio_wk1f_interrupt, 2);
 #else
-DECLARE_IRQ(NPCX_IRQ_WKINTF_1,      __gpio_wk1f_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTF_1, __gpio_wk1f_interrupt, 3);
 #endif
-DECLARE_IRQ(NPCX_IRQ_WKINTG_1,      __gpio_wk1g_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTH_1,      __gpio_wk1h_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTG_1, __gpio_wk1g_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTH_1, __gpio_wk1h_interrupt, 3);
 #if defined(CHIP_FAMILY_NPCX7)
-DECLARE_IRQ(NPCX_IRQ_WKINTFG_2,     __gpio_wk2fg_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTFG_2, __gpio_wk2fg_interrupt, 3);
 #endif
 
 #undef GPIO_IRQ_FUNC
diff --git a/chip/npcx/gpio-npcx7.c b/chip/npcx/gpio-npcx7.c
deleted file mode 120000
index 39b939f44c..0000000000
--- a/chip/npcx/gpio-npcx7.c
+++ /dev/null
@@ -1 +0,0 @@
-gpio-npcx5.c
\ No newline at end of file
diff --git a/chip/npcx/gpio-npcx7.c b/chip/npcx/gpio-npcx7.c
new file mode 100644
index 0000000000..2201bb65c2
--- /dev/null
+++ b/chip/npcx/gpio-npcx7.c
@@ -0,0 +1,200 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* GPIO module for Chrome EC */
+
+#include "clock.h"
+#include "common.h"
+#include "ec_commands.h"
+#include "gpio_chip.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "lpc_chip.h"
+#include "registers.h"
+#include "task.h"
+
+/*
+ * List of GPIO IRQs to enable. Don't automatically enable interrupts for
+ * the keyboard input GPIO bank - that's handled separately. Of course the
+ * bank is different for different systems.
+ */
+static void gpio_init(void)
+{
+	/* Enable IRQs now that pins are set up */
+	task_enable_irq(NPCX_IRQ_MTC_WKINTAD_0);
+	task_enable_irq(NPCX_IRQ_WKINTEFGH_0);
+	task_enable_irq(NPCX_IRQ_WKINTC_0);
+	task_enable_irq(NPCX_IRQ_TWD_WKINTB_0);
+	task_enable_irq(NPCX_IRQ_WKINTA_1);
+	task_enable_irq(NPCX_IRQ_WKINTB_1);
+#ifdef NPCX_SELECT_KSI_TO_GPIO
+	task_enable_irq(NPCX_IRQ_KSI_WKINTC_1);
+#endif
+	task_enable_irq(NPCX_IRQ_WKINTD_1);
+	task_enable_irq(NPCX_IRQ_WKINTE_1);
+	task_enable_irq(NPCX_IRQ_WKINTF_1);
+	task_enable_irq(NPCX_IRQ_WKINTG_1);
+	task_enable_irq(NPCX_IRQ_WKINTH_1);
+#if defined(CHIP_FAMILY_NPCX7)
+	task_enable_irq(NPCX_IRQ_WKINTFG_2);
+#endif
+}
+DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
+
+/**
+ * Handlers for each GPIO port.  These read and clear the interrupt bits for
+ * the port, then call the master handler above.
+ */
+
+#define GPIO_IRQ_FUNC(_irq_func, wui_int) \
+	static void _irq_func(void)       \
+	{                                 \
+		gpio_interrupt(wui_int);  \
+	}
+
+/* If we need to handle the other type interrupts except GPIO, add code here */
+static void __gpio_wk0efgh_interrupt(void)
+{
+	if (IS_ENABLED(CONFIG_HOSTCMD_X86)) {
+		/* Pending bit 7 or 6 or 5? */
+		if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6) &&
+		    IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 6)) {
+			/* Disable host wake-up */
+			CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6);
+			/* Clear pending bit of WUI */
+			SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_5), 6);
+			return;
+		}
+		if (IS_ENABLED(CONFIG_HOST_INTERFACE_ESPI)) {
+			if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5),
+				       5) &&
+			    IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5),
+				       5)) {
+				espi_espirst_handler();
+				return;
+			}
+		} else {
+			if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5),
+				       7) &&
+			    IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5),
+				       7)) {
+				lpc_lreset_pltrst_handler();
+				return;
+			}
+		}
+	}
+	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_5));
+	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_6));
+	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_7));
+	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_8));
+}
+
+#ifdef CONFIG_HOSTCMD_RTC
+static void set_rtc_host_event(void)
+{
+	host_set_single_event(EC_HOST_EVENT_RTC);
+}
+DECLARE_DEFERRED(set_rtc_host_event);
+#endif
+
+static void __gpio_rtc_interrupt(void)
+{
+	/* Check pending bit 7 */
+#ifdef CONFIG_HOSTCMD_RTC
+	if (NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_4) & 0x80) {
+		/* Clear pending bit for WUI */
+		SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_4), 7);
+		hook_call_deferred(&set_rtc_host_event_data, 0);
+		return;
+	}
+#endif
+#if defined(CHIP_FAMILY_NPCX7) && defined(CONFIG_LOW_POWER_IDLE) && \
+	(CONFIG_CONSOLE_UART == 1)
+	/* Handle the interrupt from UART wakeup event */
+	if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_1), 6) &&
+	    IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_1), 6)) {
+		/*
+		 * Disable WKEN bit to avoid the other unnecessary interrupts
+		 * from the coming data bits after the start bit. (Pending bit
+		 * of CR_SIN is set when a high-to-low transaction occurs.)
+		 */
+		CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_1), 6);
+		/* Clear pending bit for WUI */
+		SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_1), 6);
+		/* Notify the clock module that the console is in use. */
+		clock_refresh_console_in_use();
+		return;
+	}
+#endif
+	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_1));
+	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_4));
+}
+
+static void __gpio_wk1h_interrupt(void)
+{
+#if defined(CHIP_FAMILY_NPCX7) && defined(CONFIG_LOW_POWER_IDLE) && \
+	(CONFIG_CONSOLE_UART == 0)
+	/* Handle the interrupt from UART wakeup event */
+	if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_1, MIWU_GROUP_8), 7) &&
+	    IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_1, MIWU_GROUP_8), 7)) {
+		/*
+		 * Disable WKEN bit to avoid the other unnecessary interrupts
+		 * from the coming data bits after the start bit. (Pending bit
+		 * of CR_SIN is set when a high-to-low transaction occurs.)
+		 */
+		CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_1, MIWU_GROUP_8), 7);
+		/* Clear pending bit for WUI */
+		SET_BIT(NPCX_WKPCL(MIWU_TABLE_1, MIWU_GROUP_8), 7);
+		/* Notify the clock module that the console is in use. */
+		clock_refresh_console_in_use();
+	} else
+#endif
+		gpio_interrupt(WUI_INT(MIWU_TABLE_1, MIWU_GROUP_8));
+}
+
+GPIO_IRQ_FUNC(__gpio_wk0b_interrupt, WUI_INT(MIWU_TABLE_0, MIWU_GROUP_2));
+GPIO_IRQ_FUNC(__gpio_wk0c_interrupt, WUI_INT(MIWU_TABLE_0, MIWU_GROUP_3));
+GPIO_IRQ_FUNC(__gpio_wk1a_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_1));
+GPIO_IRQ_FUNC(__gpio_wk1b_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_2));
+#ifdef NPCX_SELECT_KSI_TO_GPIO
+/* Declare GPIO irq functions for KSI pins if there's no keyboard scan task, */
+GPIO_IRQ_FUNC(__gpio_wk1c_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_3));
+#endif
+GPIO_IRQ_FUNC(__gpio_wk1d_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_4));
+GPIO_IRQ_FUNC(__gpio_wk1e_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_5));
+GPIO_IRQ_FUNC(__gpio_wk1f_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_6));
+GPIO_IRQ_FUNC(__gpio_wk1g_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_7));
+#if defined(CHIP_FAMILY_NPCX7)
+GPIO_IRQ_FUNC(__gpio_wk2fg_interrupt, WUI_INT(MIWU_TABLE_2, MIWU_GROUP_6));
+#endif
+
+DECLARE_IRQ(NPCX_IRQ_MTC_WKINTAD_0, __gpio_rtc_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_TWD_WKINTB_0, __gpio_wk0b_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTC_0, __gpio_wk0c_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTEFGH_0, __gpio_wk0efgh_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTA_1, __gpio_wk1a_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTB_1, __gpio_wk1b_interrupt, 3);
+#ifdef NPCX_SELECT_KSI_TO_GPIO
+DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1, __gpio_wk1c_interrupt, 3);
+#endif
+DECLARE_IRQ(NPCX_IRQ_WKINTD_1, __gpio_wk1d_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTE_1, __gpio_wk1e_interrupt, 3);
+#ifdef CONFIG_HOST_INTERFACE_SHI
+/*
+ * HACK: Make CS GPIO P2 to improve SHI reliability.
+ * TODO: Increase CS-assertion-to-transaction-start delay on host to
+ * accommodate P3 CS interrupt.
+ */
+DECLARE_IRQ(NPCX_IRQ_WKINTF_1, __gpio_wk1f_interrupt, 2);
+#else
+DECLARE_IRQ(NPCX_IRQ_WKINTF_1, __gpio_wk1f_interrupt, 3);
+#endif
+DECLARE_IRQ(NPCX_IRQ_WKINTG_1, __gpio_wk1g_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTH_1, __gpio_wk1h_interrupt, 3);
+#if defined(CHIP_FAMILY_NPCX7)
+DECLARE_IRQ(NPCX_IRQ_WKINTFG_2, __gpio_wk2fg_interrupt, 3);
+#endif
+
+#undef GPIO_IRQ_FUNC
diff --git a/chip/npcx/gpio-npcx9.c b/chip/npcx/gpio-npcx9.c
index 441924d89e..3a7378083c 100644
--- a/chip/npcx/gpio-npcx9.c
+++ b/chip/npcx/gpio-npcx9.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -34,7 +34,7 @@ static void gpio_init(void)
 	task_enable_irq(NPCX_IRQ_WKINTH_0);
 	task_enable_irq(NPCX_IRQ_WKINTA_1);
 	task_enable_irq(NPCX_IRQ_WKINTB_1);
-#ifndef HAS_TASK_KEYSCAN
+#ifdef NPCX_SELECT_KSI_TO_GPIO
 	task_enable_irq(NPCX_IRQ_KSI_WKINTC_1);
 #endif
 	task_enable_irq(NPCX_IRQ_WKINTD_1);
@@ -51,36 +51,38 @@ DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
  * the port, then call the master handler above.
  */
 
-#define GPIO_IRQ_FUNC(_irq_func, wui_int)		\
-void _irq_func(void)					\
-{							\
-	gpio_interrupt(wui_int);			\
-}
+#define GPIO_IRQ_FUNC(_irq_func, wui_int) \
+	static void _irq_func(void)       \
+	{                                 \
+		gpio_interrupt(wui_int);  \
+	}
 
 /* If we need to handle the other type interrupts except GPIO, add code here */
-void __gpio_host_interrupt(void)
+static void __gpio_host_interrupt(void)
 {
 	if (IS_ENABLED(CONFIG_HOSTCMD_X86)) {
 		/* Pending bit 7 or 6 or 5? */
 		if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6) &&
-			IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 6)) {
+		    IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 6)) {
 			/* Disable host wake-up */
 			CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6);
 			/* Clear pending bit of WUI */
 			SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_5), 6);
 			return;
 		}
-		if (IS_ENABLED(CONFIG_HOSTCMD_ESPI)) {
-			if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 5)
-					&&
-			IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 5)) {
+		if (IS_ENABLED(CONFIG_HOST_INTERFACE_ESPI)) {
+			if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5),
+				       5) &&
+			    IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5),
+				       5)) {
 				espi_espirst_handler();
 				return;
 			}
 		} else {
-			if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 7)
-					&&
-			IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 7)) {
+			if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5),
+				       7) &&
+			    IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5),
+				       7)) {
 				lpc_lreset_pltrst_handler();
 				return;
 			}
@@ -97,7 +99,7 @@ static void set_rtc_host_event(void)
 DECLARE_DEFERRED(set_rtc_host_event);
 #endif
 
-void __gpio_rtc_interrupt(void)
+static void __gpio_rtc_interrupt(void)
 {
 	/* Check pending bit 7 */
 #ifdef CONFIG_HOSTCMD_RTC
@@ -110,7 +112,7 @@ void __gpio_rtc_interrupt(void)
 #endif
 	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_4));
 }
-void __gpio_cr_sin2_interrupt(void)
+static void __gpio_cr_sin2_interrupt(void)
 {
 #if defined(CONFIG_LOW_POWER_IDLE) && (CONFIG_CONSOLE_UART == 1)
 	/* Handle the interrupt from UART wakeup event */
@@ -130,10 +132,9 @@ void __gpio_cr_sin2_interrupt(void)
 	}
 #endif
 	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_1));
-
 }
 
-void __gpio_wk1h_interrupt(void)
+static void __gpio_wk1h_interrupt(void)
 {
 #if defined(CONFIG_LOW_POWER_IDLE) && (CONFIG_CONSOLE_UART == 0)
 	/* Handle the interrupt from UART wakeup event */
@@ -154,7 +155,7 @@ void __gpio_wk1h_interrupt(void)
 		gpio_interrupt(WUI_INT(MIWU_TABLE_1, MIWU_GROUP_8));
 }
 
-void __gpio_lct_interrupt(void)
+static void __gpio_lct_interrupt(void)
 {
 	if (NPCX_WKPND(MIWU_TABLE_2, MIWU_GROUP_6) & LCT_WUI_MASK) {
 		NPCX_WKPCL(MIWU_TABLE_2, MIWU_GROUP_6) |= LCT_WUI_MASK;
@@ -171,7 +172,7 @@ GPIO_IRQ_FUNC(__gpio_wk0g_interrupt, WUI_INT(MIWU_TABLE_0, MIWU_GROUP_7));
 GPIO_IRQ_FUNC(__gpio_wk0h_interrupt, WUI_INT(MIWU_TABLE_0, MIWU_GROUP_8));
 GPIO_IRQ_FUNC(__gpio_wk1a_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_1));
 GPIO_IRQ_FUNC(__gpio_wk1b_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_2));
-#ifndef HAS_TASK_KEYSCAN
+#ifdef NPCX_SELECT_KSI_TO_GPIO
 /* Declare GPIO irq functions for KSI pins if there's no keyboard scan task, */
 GPIO_IRQ_FUNC(__gpio_wk1c_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_3));
 #endif
@@ -179,35 +180,35 @@ GPIO_IRQ_FUNC(__gpio_wk1d_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_4));
 GPIO_IRQ_FUNC(__gpio_wk1e_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_5));
 GPIO_IRQ_FUNC(__gpio_wk1f_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_6));
 GPIO_IRQ_FUNC(__gpio_wk1g_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_7));
-GPIO_IRQ_FUNC(__gpio_wk2fg_interrupt, WUI_INT(MIWU_TABLE_2, MIWU_GROUP_6));
 
-DECLARE_IRQ(NPCX_IRQ_CR_SIN2_WKINTA_0, __gpio_cr_sin2_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_TWD_WKINTB_0,     __gpio_wk0b_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTC_0,         __gpio_wk0c_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_MTC_WKINTD_0,     __gpio_rtc_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTE_0,         __gpio_host_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTF_0,         __gpio_wk0f_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTG_0,         __gpio_wk0g_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTH_0,         __gpio_wk0h_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTA_1,         __gpio_wk1a_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTB_1,         __gpio_wk1b_interrupt, 3);
-#ifndef HAS_TASK_KEYSCAN
-DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1,     __gpio_wk1c_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_CR_SIN2_WKINTA_0, __gpio_cr_sin2_interrupt,
+	    NPCX_MIWU0_GROUP_A);
+DECLARE_IRQ(NPCX_IRQ_TWD_WKINTB_0, __gpio_wk0b_interrupt, NPCX_MIWU0_GROUP_B);
+DECLARE_IRQ(NPCX_IRQ_WKINTC_0, __gpio_wk0c_interrupt, NPCX_MIWU0_GROUP_C);
+DECLARE_IRQ(NPCX_IRQ_MTC_WKINTD_0, __gpio_rtc_interrupt, NPCX_MIWU0_GROUP_D);
+DECLARE_IRQ(NPCX_IRQ_WKINTE_0, __gpio_host_interrupt, NPCX_MIWU0_GROUP_E);
+DECLARE_IRQ(NPCX_IRQ_WKINTF_0, __gpio_wk0f_interrupt, NPCX_MIWU0_GROUP_F);
+DECLARE_IRQ(NPCX_IRQ_WKINTG_0, __gpio_wk0g_interrupt, NPCX_MIWU0_GROUP_G);
+DECLARE_IRQ(NPCX_IRQ_WKINTH_0, __gpio_wk0h_interrupt, NPCX_MIWU0_GROUP_H);
+DECLARE_IRQ(NPCX_IRQ_WKINTA_1, __gpio_wk1a_interrupt, NPCX_MIWU1_GROUP_A);
+DECLARE_IRQ(NPCX_IRQ_WKINTB_1, __gpio_wk1b_interrupt, NPCX_MIWU1_GROUP_B);
+#ifdef NPCX_SELECT_KSI_TO_GPIO
+DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1, __gpio_wk1c_interrupt, NPCX_MIWU1_GROUP_C);
 #endif
-DECLARE_IRQ(NPCX_IRQ_WKINTD_1,         __gpio_wk1d_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTE_1,         __gpio_wk1e_interrupt, 3);
-#ifdef CONFIG_HOSTCMD_SPS
+DECLARE_IRQ(NPCX_IRQ_WKINTD_1, __gpio_wk1d_interrupt, NPCX_MIWU1_GROUP_D);
+DECLARE_IRQ(NPCX_IRQ_WKINTE_1, __gpio_wk1e_interrupt, NPCX_MIWU1_GROUP_E);
+#ifdef CONFIG_HOST_INTERFACE_SHI
 /*
  * HACK: Make CS GPIO P2 to improve SHI reliability.
  * TODO: Increase CS-assertion-to-transaction-start delay on host to
  * accommodate P3 CS interrupt.
  */
-DECLARE_IRQ(NPCX_IRQ_WKINTF_1,         __gpio_wk1f_interrupt, 2);
+DECLARE_IRQ(NPCX_IRQ_WKINTF_1, __gpio_wk1f_interrupt, 2);
 #else
-DECLARE_IRQ(NPCX_IRQ_WKINTF_1,         __gpio_wk1f_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTF_1, __gpio_wk1f_interrupt, NPCX_MIWU1_GROUP_F);
 #endif
-DECLARE_IRQ(NPCX_IRQ_WKINTG_1,         __gpio_wk1g_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTH_1,         __gpio_wk1h_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_LCT_WKINTF_2,     __gpio_lct_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTG_1, __gpio_wk1g_interrupt, NPCX_MIWU1_GROUP_G);
+DECLARE_IRQ(NPCX_IRQ_WKINTH_1, __gpio_wk1h_interrupt, NPCX_MIWU1_GROUP_H);
+DECLARE_IRQ(NPCX_IRQ_LCT_WKINTF_2, __gpio_lct_interrupt, 3);
 
 #undef GPIO_IRQ_FUNC
diff --git a/chip/npcx/gpio.c b/chip/npcx/gpio.c
index 75c8142d63..a976b3b122 100644
--- a/chip/npcx/gpio.c
+++ b/chip/npcx/gpio.c
@@ -1,31 +1,32 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* GPIO module for Chrome EC */
 
+#include "builtin/assert.h"
 #include "common.h"
+#include "ec_commands.h"
 #include "gpio.h"
 #include "gpio_chip.h"
-#include "i2c.h"
 #include "hooks.h"
+#include "host_command.h"
+#include "hwtimer_chip.h"
+#include "i2c.h"
 #include "registers.h"
+#include "system.h"
+#include "system_chip.h"
 #include "task.h"
 #include "timer.h"
 #include "util.h"
-#include "system.h"
-#include "system_chip.h"
-#include "ec_commands.h"
-#include "host_command.h"
-#include "hwtimer_chip.h"
 
 #if !(DEBUG_GPIO)
 #define CPUTS(...)
 #define CPRINTS(...)
 #else
 #define CPUTS(outstr) cputs(CC_GPIO, outstr)
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
 #endif
 
 /* Constants for GPIO interrupt mapping */
@@ -40,12 +41,12 @@
 #define UNIMPLEMENTED(name)
 #endif
 static const struct npcx_wui gpio_wui_table[] = {
-	#include "gpio.wrap"
+#include "gpio.wrap"
 };
 
 struct npcx_gpio {
-	uint8_t port  : 4;
-	uint8_t bit   : 3;
+	uint8_t port : 4;
+	uint8_t bit : 3;
 	uint8_t valid : 1;
 };
 
@@ -54,21 +55,21 @@ BUILD_ASSERT(sizeof(struct npcx_gpio) == 1);
 #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
 struct npcx_alt {
 	uint8_t group;
-	uint8_t bit       : 3;
-	uint8_t inverted  : 1;
-	uint8_t reserved  : 4;
+	uint8_t bit : 3;
+	uint8_t inverted : 1;
+	uint8_t reserved : 4;
 };
 #else
 struct npcx_alt {
-	uint8_t group     : 4;
-	uint8_t bit       : 3;
-	uint8_t inverted  : 1;
+	uint8_t group : 4;
+	uint8_t bit : 3;
+	uint8_t inverted : 1;
 };
 #endif
 
 struct gpio_alt_map {
 	struct npcx_gpio gpio;
-	struct npcx_alt  alt;
+	struct npcx_alt alt;
 };
 
 #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
@@ -78,7 +79,7 @@ BUILD_ASSERT(sizeof(struct gpio_alt_map) == 2);
 #endif
 
 /* Constants for GPIO alternative mapping */
-const struct gpio_alt_map gpio_alt_table[] = NPCX_ALT_TABLE;
+const __const_data struct gpio_alt_map gpio_alt_table[] = NPCX_ALT_TABLE;
 
 struct gpio_lvol_item {
 	struct npcx_gpio lvol_gpio[8];
@@ -101,8 +102,7 @@ static uint8_t gpio_is_alt_sel(uint8_t port, uint8_t bit)
 	struct gpio_alt_map const *map;
 	uint8_t alt_mask, devalt;
 
-	for (map = ARRAY_BEGIN(gpio_alt_table);
-	     map < ARRAY_END(gpio_alt_table);
+	for (map = ARRAY_BEGIN(gpio_alt_table); map < ARRAY_END(gpio_alt_table);
 	     map++) {
 		if (gpio_match(port, bit, map->gpio)) {
 			alt_mask = 1 << map->alt.bit;
@@ -127,8 +127,7 @@ static int gpio_alt_sel(uint8_t port, uint8_t bit,
 {
 	struct gpio_alt_map const *map;
 
-	for (map = ARRAY_BEGIN(gpio_alt_table);
-	     map < ARRAY_END(gpio_alt_table);
+	for (map = ARRAY_BEGIN(gpio_alt_table); map < ARRAY_END(gpio_alt_table);
 	     map++) {
 		if (gpio_match(port, bit, map->gpio)) {
 			uint8_t alt_mask = 1 << map->alt.bit;
@@ -140,7 +139,7 @@ static int gpio_alt_sel(uint8_t port, uint8_t bit,
 			if ((func < GPIO_ALT_FUNC_DEFAULT) ^ map->alt.inverted)
 				NPCX_DEVALT(map->alt.group) &= ~alt_mask;
 			else
-				NPCX_DEVALT(map->alt.group) |=  alt_mask;
+				NPCX_DEVALT(map->alt.group) |= alt_mask;
 
 			return 1;
 		}
@@ -183,7 +182,7 @@ static void gpio_interrupt_type_sel(enum gpio_signal signal, uint32_t flags)
 		NPCX_WKMOD(table, group) &= ~pmask;
 		/* Handle interrupting on both edges */
 		if ((flags & GPIO_INT_F_RISING) &&
-			(flags & GPIO_INT_F_FALLING)) {
+		    (flags & GPIO_INT_F_FALLING)) {
 			/* Enable any edge */
 			NPCX_WKAEDG(table, group) |= pmask;
 		}
@@ -252,7 +251,7 @@ void gpio_low_voltage_level_sel(uint8_t port, uint8_t bit, uint8_t low_voltage)
 
 	if (low_voltage)
 		CPRINTS("Warn! No low voltage support in port:0x%x, bit:%d",
-								port, bit);
+			port, bit);
 }
 
 /* Set the low voltage detection level by mask */
@@ -290,7 +289,7 @@ static void gpio_enable_wake_up_input(enum gpio_signal signal, int enable)
 			SET_BIT(NPCX_WKINEN(wui->table, wui->group), wui->bit);
 		else
 			CLEAR_BIT(NPCX_WKINEN(wui->table, wui->group),
-						wui->bit);
+				  wui->bit);
 	}
 }
 
@@ -317,9 +316,9 @@ BUILD_ASSERT(ARRAY_SIZE(gpio_lvol_table[0].lvol_gpio) == 8);
 /* IC specific low-level driver */
 
 void gpio_set_alternate_function(uint32_t port, uint32_t mask,
-				enum gpio_alternate_func func)
+				 enum gpio_alternate_func func)
 {
-	/* Enable alternative pins by func*/
+	/* Enable alternative pins by func */
 	int pin;
 
 	/* check each bit from mask  */
@@ -340,7 +339,7 @@ void gpio_set_level(enum gpio_signal signal, int value)
 	ASSERT(signal_is_gpio(signal));
 
 	if (value)
-		NPCX_PDOUT(gpio_list[signal].port) |=  gpio_list[signal].mask;
+		NPCX_PDOUT(gpio_list[signal].port) |= gpio_list[signal].mask;
 	else
 		NPCX_PDOUT(gpio_list[signal].port) &= ~gpio_list[signal].mask;
 }
@@ -355,10 +354,12 @@ int gpio_get_flags_by_mask(uint32_t port, uint32_t mask)
 	else
 		flags |= GPIO_INPUT;
 
-	if (NPCX_PDIN(port) & mask)
-		flags |= GPIO_HIGH;
-	else
-		flags |= GPIO_LOW;
+	if (flags & GPIO_OUTPUT) {
+		if (NPCX_PDOUT(port) & mask)
+			flags |= GPIO_HIGH;
+		else
+			flags |= GPIO_LOW;
+	}
 
 	if (NPCX_PTYPE(port) & mask)
 		flags |= GPIO_OPEN_DRAIN;
@@ -410,14 +411,14 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
 	if (flags & GPIO_PULL_UP) {
 		if (flags & GPIO_SEL_1P8V) {
 			CPRINTS("Warn! enable internal PU and low voltage mode"
-					" at the same time is illegal. port 0x%x, mask 0x%x",
-					port, mask);
+				" at the same time is illegal. port 0x%x, mask 0x%x",
+				port, mask);
 		} else {
-			NPCX_PPUD(port)  &= ~mask;
+			NPCX_PPUD(port) &= ~mask;
 			NPCX_PPULL(port) |= mask; /* enable pull down/up */
 		}
 	} else if (flags & GPIO_PULL_DOWN) {
-		NPCX_PPUD(port)  |= mask;
+		NPCX_PPUD(port) |= mask;
 		NPCX_PPULL(port) |= mask; /* enable pull down/up */
 	} else {
 		/* No pull up/down */
@@ -455,7 +456,7 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
 	if (flags & GPIO_OUTPUT)
 		NPCX_PDIR(port) |= mask;
 
-	/* Lock GPIO output and configuration if need */
+		/* Lock GPIO output and configuration if need */
 #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
 	if (flags & GPIO_LOCKED)
 		NPCX_PLOCK_CTL(port) |= mask;
@@ -508,6 +509,7 @@ int gpio_clear_pending_interrupt(enum gpio_signal signal)
 void gpio_pre_init(void)
 {
 	const struct gpio_info *g = gpio_list;
+	const struct unused_pin_info *u = unused_pin_list;
 	int is_warm;
 	int flags;
 	int i, j;
@@ -559,7 +561,7 @@ void gpio_pre_init(void)
 #endif
 
 	/* Pin_Mux for LPC & SHI */
-#ifdef CONFIG_HOSTCMD_SPS
+#ifdef CONFIG_HOST_INTERFACE_SHI
 	/* Switching to eSPI mode for SHI interface */
 	NPCX_DEVCNT |= 0x08;
 	/* Alternate Intel bus interface LPC/eSPI to GPIOs first */
@@ -597,7 +599,7 @@ void gpio_pre_init(void)
 		 * which may or may not be as a GPIO.
 		 */
 		gpio_set_alternate_function(g->port, g->mask,
-					GPIO_ALT_FUNC_NONE);
+					    GPIO_ALT_FUNC_NONE);
 	}
 
 	/* The bypass of low voltage IOs for better power consumption */
@@ -614,6 +616,14 @@ void gpio_pre_init(void)
 			gpio_enable_wake_up_input(i, 0);
 	}
 #endif
+
+	/* Configure unused pins as GPIO INPUT with PU to save power. */
+	for (i = 0; i < unused_pin_count; i++, u++) {
+		gpio_set_flags_by_mask(u->port, u->mask,
+				       GPIO_INPUT | GPIO_PULL_UP);
+		gpio_set_alternate_function(g->port, g->mask,
+					    GPIO_ALT_FUNC_NONE);
+	}
 }
 
 /*****************************************************************************/
@@ -640,8 +650,8 @@ void gpio_interrupt(struct npcx_wui wui_int)
 		uint8_t pin_mask = 1 << gpio_wui_table[i].bit;
 
 		if ((gpio_wui_table[i].table == table) &&
-			(gpio_wui_table[i].group == group) &&
-			(wui_mask & pin_mask)) {
+		    (gpio_wui_table[i].group == group) &&
+		    (wui_mask & pin_mask)) {
 			/* Clear pending bit of GPIO */
 			NPCX_WKPCL(table, group) = pin_mask;
 			/* Execute GPIO's ISR */
@@ -662,7 +672,7 @@ void gpio_interrupt(struct npcx_wui wui_int)
  * Command used to disable input buffer of gpios one by one to
  * investigate power consumption
  */
-static int command_gpiodisable(int argc, char **argv)
+static int command_gpiodisable(int argc, const char **argv)
 {
 	uint8_t i;
 	uint8_t offset;
@@ -682,7 +692,7 @@ static int command_gpiodisable(int argc, char **argv)
 
 			ccprintf("Total GPIO declaration: %d\n", GPIO_COUNT);
 			ccprintf("Total Non-ISR GPIO declaration: %d\n",
-						non_isr_gpio_num);
+				 non_isr_gpio_num);
 			ccprintf("Next GPIO Num to check by ");
 			ccprintf("\"gpiodisable next\"\n");
 			ccprintf("  offset: %d\n", offset);
@@ -705,8 +715,8 @@ static int command_gpiodisable(int argc, char **argv)
 				offset = idx + GPIO_IH_COUNT;
 				g_list = gpio_list + offset;
 				flags = g_list->flags;
-				ccprintf("current GPIO : %d %s --> ",
-							offset, g_list->name);
+				ccprintf("current GPIO : %d %s --> ", offset,
+					 g_list->name);
 				if (gpio_is_i2c_pin(offset)) {
 					ccprintf("Ignore I2C pin!\n");
 					idx++;
@@ -717,10 +727,10 @@ static int command_gpiodisable(int argc, char **argv)
 					continue;
 				} else {
 					if ((flags & GPIO_INPUT) ||
-						    (flags & GPIO_OPEN_DRAIN)) {
+					    (flags & GPIO_OPEN_DRAIN)) {
 						ccprintf("Disable WKINEN!\n");
 						gpio_enable_wake_up_input(
-								offset, 0);
+							offset, 0);
 						idx++;
 						break;
 					}
@@ -750,7 +760,7 @@ static int command_gpiodisable(int argc, char **argv)
 	}
 	return EC_ERROR_INVAL;
 }
-DECLARE_CONSOLE_COMMAND(gpiodisable, command_gpiodisable,
-		"info/list/next/<num> on|off",
-		"Disable GPIO input buffer to investigate power consumption");
+DECLARE_CONSOLE_COMMAND(
+	gpiodisable, command_gpiodisable, "info/list/next/<num> on|off",
+	"Disable GPIO input buffer to investigate power consumption");
 #endif
diff --git a/chip/npcx/gpio_chip-npcx5.h b/chip/npcx/gpio_chip-npcx5.h
index ee113aea44..81ef957236 100644
--- a/chip/npcx/gpio_chip-npcx5.h
+++ b/chip/npcx/gpio_chip-npcx5.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -206,7 +206,7 @@
 
 /* MFT Module */
 #define NPCX_ALT_GPIO_9_3 ALT(9, 3, NPCX_ALT(C, TA1_SL2)) /* TA1_SEL2 */
-#ifdef CONFIG_PS2
+#if defined(CONFIG_PS2) && defined(NPCX_PS2_MODULE_3)
 #define NPCX_ALT_GPIO_A_6 ALT(A, 6, NPCX_ALT(C, PS2_3_SL2)) /* PS2_CLK3 */
 #else
 #define NPCX_ALT_GPIO_A_6 ALT(A, 6, NPCX_ALT(C, TA2_SL2)) /* TA2_SEL2 */
@@ -245,7 +245,7 @@
 #define NPCX_ALT_GPIO_B_1 ALT(B, 1, NPCX_ALT_INV(A, NO_KSO17_SL)) /* KSO17 */
 
 /* Clock module */
-#define NPCX_ALT_GPIO_7_5 ALT(7, 5, NPCX_ALT(A, 32K_OUT_SL))  /* 32KHZ_OUT */
+#define NPCX_ALT_GPIO_7_5 ALT(7, 5, NPCX_ALT(A, 32K_OUT_SL)) /* 32KHZ_OUT */
 #define NPCX_ALT_GPIO_E_7 ALT(E, 7, NPCX_ALT(A, 32KCLKIN_SL)) /* 32KCLKIN */
 
 /* PS/2 module */
@@ -255,8 +255,13 @@
 #define NPCX_ALT_GPIO_6_3 ALT(6, 3, NPCX_ALT(3, PS2_1_SL)) /* PS2_DATA1 */
 #define NPCX_ALT_GPIO_3_7 ALT(3, 7, NPCX_ALT(3, PS2_2_SL)) /* PS2_CLK2 */
 #define NPCX_ALT_GPIO_3_4 ALT(3, 4, NPCX_ALT(3, PS2_2_SL)) /* PS2_DATA2 */
+#if defined(CONFIG_PS2) && defined(NPCX_PS2_MODULE_3)
 #define NPCX_ALT_GPIO_A_7 ALT(A, 7, NPCX_ALT(C, PS2_3_SL2)) /* PS2_DAT3 */
+#else
+#define NPCX_ALT_GPIO_A_7
+#endif
 
+/* clang-format off */
 #define NPCX_ALT_TABLE { \
 	NPCX_ALT_GPIO_0_3  /* KSO16 */               \
 	NPCX_ALT_GPIO_0_4  /* KSO13 */               \
@@ -327,54 +332,66 @@
 	NPCX_ALT_GPIO_D_1  /* SMB3SCL */             \
 	NPCX_ALT_GPIO_E_7  /* 32KCLKIN */            \
 }
+/* clang-format on */
 
 /*****************************************************************************/
 /* Macro functions for Low-Voltage mapping table */
 
 /* Low-Voltage GPIO Control 0 */
-#define NPCX_LVOL_CTRL_0_0  NPCX_GPIO(B, 5)
-#define NPCX_LVOL_CTRL_0_1  NPCX_GPIO(B, 4)
-#define NPCX_LVOL_CTRL_0_2  NPCX_GPIO(B, 3)
-#define NPCX_LVOL_CTRL_0_3  NPCX_GPIO(B, 2)
-#define NPCX_LVOL_CTRL_0_4  NPCX_GPIO(9, 0)
-#define NPCX_LVOL_CTRL_0_5  NPCX_GPIO(8, 7)
-#define NPCX_LVOL_CTRL_0_6  NPCX_GPIO(0, 0)
-#define NPCX_LVOL_CTRL_0_7  NPCX_GPIO(3, 3)
+#define NPCX_LVOL_CTRL_0_0 NPCX_GPIO(B, 5)
+#define NPCX_LVOL_CTRL_0_1 NPCX_GPIO(B, 4)
+#define NPCX_LVOL_CTRL_0_2 NPCX_GPIO(B, 3)
+#define NPCX_LVOL_CTRL_0_3 NPCX_GPIO(B, 2)
+#define NPCX_LVOL_CTRL_0_4 NPCX_GPIO(9, 0)
+#define NPCX_LVOL_CTRL_0_5 NPCX_GPIO(8, 7)
+#define NPCX_LVOL_CTRL_0_6 NPCX_GPIO(0, 0)
+#define NPCX_LVOL_CTRL_0_7 NPCX_GPIO(3, 3)
 
 /* Low-Voltage GPIO Control 1 */
-#define NPCX_LVOL_CTRL_1_0  NPCX_GPIO(9, 2)
-#define NPCX_LVOL_CTRL_1_1  NPCX_GPIO(9, 1)
-#define NPCX_LVOL_CTRL_1_2  NPCX_GPIO(D, 1)
-#define NPCX_LVOL_CTRL_1_3  NPCX_GPIO(D, 0)
-#define NPCX_LVOL_CTRL_1_4  NPCX_GPIO(3, 6)
-#define NPCX_LVOL_CTRL_1_5  NPCX_GPIO(6, 4)
-#define NPCX_LVOL_CTRL_1_6  NPCX_GPIO(6, 5)
-#define NPCX_LVOL_CTRL_1_7  NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_1_0 NPCX_GPIO(9, 2)
+#define NPCX_LVOL_CTRL_1_1 NPCX_GPIO(9, 1)
+#define NPCX_LVOL_CTRL_1_2 NPCX_GPIO(D, 1)
+#define NPCX_LVOL_CTRL_1_3 NPCX_GPIO(D, 0)
+#define NPCX_LVOL_CTRL_1_4 NPCX_GPIO(3, 6)
+#define NPCX_LVOL_CTRL_1_5 NPCX_GPIO(6, 4)
+#define NPCX_LVOL_CTRL_1_6 NPCX_GPIO(6, 5)
+#define NPCX_LVOL_CTRL_1_7 NPCX_GPIO_NONE
 
 /* Low-Voltage GPIO Control 2 */
-#define NPCX_LVOL_CTRL_2_0  NPCX_GPIO(7, 4)
-#define NPCX_LVOL_CTRL_2_1  NPCX_GPIO(8, 4)
-#define NPCX_LVOL_CTRL_2_2  NPCX_GPIO(8, 5)
-#define NPCX_LVOL_CTRL_2_3  NPCX_GPIO(7, 3)
-#define NPCX_LVOL_CTRL_2_4  NPCX_GPIO(C, 1)
-#define NPCX_LVOL_CTRL_2_5  NPCX_GPIO(C, 7)
-#define NPCX_LVOL_CTRL_2_6  NPCX_GPIO(E, 7)
-#define NPCX_LVOL_CTRL_2_7  NPCX_GPIO(3, 4)
+#define NPCX_LVOL_CTRL_2_0 NPCX_GPIO(7, 4)
+#define NPCX_LVOL_CTRL_2_1 NPCX_GPIO(8, 4)
+#define NPCX_LVOL_CTRL_2_2 NPCX_GPIO(8, 5)
+#define NPCX_LVOL_CTRL_2_3 NPCX_GPIO(7, 3)
+#define NPCX_LVOL_CTRL_2_4 NPCX_GPIO(C, 1)
+#define NPCX_LVOL_CTRL_2_5 NPCX_GPIO(C, 7)
+#define NPCX_LVOL_CTRL_2_6 NPCX_GPIO(E, 7)
+#define NPCX_LVOL_CTRL_2_7 NPCX_GPIO(3, 4)
 
 /* Low-Voltage GPIO Control 3 */
-#define NPCX_LVOL_CTRL_3_0  NPCX_GPIO(C, 6)
-#define NPCX_LVOL_CTRL_3_1  NPCX_GPIO(3, 7)
-#define NPCX_LVOL_CTRL_3_2  NPCX_GPIO(4, 0)
-#define NPCX_LVOL_CTRL_3_3  NPCX_GPIO(7, 1)
-#define NPCX_LVOL_CTRL_3_4  NPCX_GPIO(8, 2)
-#define NPCX_LVOL_CTRL_3_5  NPCX_GPIO(7, 5)
-#define NPCX_LVOL_CTRL_3_6  NPCX_GPIO(8, 0)
-#define NPCX_LVOL_CTRL_3_7  NPCX_GPIO(C, 5)
+#define NPCX_LVOL_CTRL_3_0 NPCX_GPIO(C, 6)
+#define NPCX_LVOL_CTRL_3_1 NPCX_GPIO(3, 7)
+#define NPCX_LVOL_CTRL_3_2 NPCX_GPIO(4, 0)
+#define NPCX_LVOL_CTRL_3_3 NPCX_GPIO(7, 1)
+#define NPCX_LVOL_CTRL_3_4 NPCX_GPIO(8, 2)
+#define NPCX_LVOL_CTRL_3_5 NPCX_GPIO(7, 5)
+#define NPCX_LVOL_CTRL_3_6 NPCX_GPIO(8, 0)
+#define NPCX_LVOL_CTRL_3_7 NPCX_GPIO(C, 5)
 
 /* 4 Low-Voltage Control Groups on npcx5 */
-#define NPCX_LVOL_TABLE { { NPCX_LVOL_CTRL_ITEMS(0), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(1), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(2), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(3), }, }
+#define NPCX_LVOL_TABLE                                  \
+	{                                                \
+		{                                        \
+			NPCX_LVOL_CTRL_ITEMS(0),         \
+		},                                       \
+			{                                \
+				NPCX_LVOL_CTRL_ITEMS(1), \
+			},                               \
+			{                                \
+				NPCX_LVOL_CTRL_ITEMS(2), \
+			},                               \
+			{                                \
+				NPCX_LVOL_CTRL_ITEMS(3), \
+			},                               \
+	}
 
 #endif /* __CROS_EC_GPIO_CHIP_NPCX5_H */
diff --git a/chip/npcx/gpio_chip-npcx7.h b/chip/npcx/gpio_chip-npcx7.h
index 2f6337d896..39654bc09e 100644
--- a/chip/npcx/gpio_chip-npcx7.h
+++ b/chip/npcx/gpio_chip-npcx7.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -82,7 +82,9 @@
 #define NPCX_WUI_GPIO_F_0 WUI(0, MIWU_GROUP_8, 5)
 #define NPCX_WUI_GPIO_F_3 WUI(0, MIWU_GROUP_8, 6)
 #ifndef NPCX_EXT32K_OSC_SUPPORT
-#define NPCX_WUI_GPIO_E_7 WUI(0, MIWU_GROUP_8, 7) /* Used as CLKIN if support */
+#define NPCX_WUI_GPIO_E_7                                   \
+	WUI(0, MIWU_GROUP_8, 7) /* Used as CLKIN if support \
+				 */
 #endif
 
 /* MIWU1 */
@@ -151,7 +153,9 @@
 #define NPCX_WUI_GPIO_6_3 WUI(1, MIWU_GROUP_7, 3)
 #define NPCX_WUI_GPIO_6_4 WUI(1, MIWU_GROUP_7, 4)
 #ifndef NPCX_EXT32K_OSC_SUPPORT
-#define NPCX_WUI_GPIO_7_1 WUI(1, MIWU_GROUP_7, 7) /* Used as CLKOUT if support*/
+#define NPCX_WUI_GPIO_7_1                            \
+	WUI(1, MIWU_GROUP_7, 7) /* Used as CLKOUT if \
+				   support*/
 #endif
 
 /* Group H: NPCX_IRQ_WKINTH_1 */
@@ -194,7 +198,7 @@
 /* Pin-Mux for PSL/UART2/SMB4_0 */
 #ifdef NPCX_PSL_MODE_SUPPORT
 #if defined(NPCX_SECOND_UART) && (CONFIG_CONSOLE_UART == 1)
-#define NPCX_ALT_GPIO_8_6 ALT(8, 6, NPCX_ALT(A, UART2_SL))  /* CR_SOUT2 */
+#define NPCX_ALT_GPIO_8_6 ALT(8, 6, NPCX_ALT(A, UART2_SL)) /* CR_SOUT2 */
 #define NPCX_ALT_GPIO_8_5 /* Used as PSL_OUT */
 #else
 #define NPCX_ALT_GPIO_8_6 /* No I2CSDA since GPIO85 used as PSL_OUT */
@@ -214,7 +218,7 @@
 /* Pin-Mux for PWM1/SMB6_0 */
 #if NPCX7_PWM1_SEL
 #define NPCX_ALT_GPIO_C_1 /* No I2CSDA since GPIOC2 used as PWM1 */
-#define NPCX_ALT_GPIO_C_2 ALT(C, 2, NPCX_ALT(4, PWM1_SL))   /* PWM1 */
+#define NPCX_ALT_GPIO_C_2 ALT(C, 2, NPCX_ALT(4, PWM1_SL)) /* PWM1 */
 #else
 #define NPCX_ALT_GPIO_C_1 ALT(C, 1, NPCX_ALT(2, I2C6_0_SL)) /* SMB6SDA0 */
 #define NPCX_ALT_GPIO_C_2 ALT(C, 2, NPCX_ALT(2, I2C6_0_SL)) /* SMB6SCL0 */
@@ -230,7 +234,7 @@
 #define NPCX_ALT_GPIO_4_3 ALT(4, 3, NPCX_ALT(6, ADC2_SL)) /* ADC2  */
 #define NPCX_ALT_GPIO_4_2 ALT(4, 2, NPCX_ALT(6, ADC3_SL)) /* ADC3  */
 #define NPCX_ALT_GPIO_4_1 ALT(4, 1, NPCX_ALT(6, ADC4_SL)) /* ADC4  */
-#ifdef CONFIG_PS2
+#if defined(CONFIG_PS2) && defined(NPCX_PS2_MODULE_2)
 #define NPCX_ALT_GPIO_3_7 ALT(3, 7, NPCX_ALT(3, PS2_2_SL)) /* PS2_CLK2 */
 #define NPCX_ALT_GPIO_3_4 ALT(3, 4, NPCX_ALT(3, PS2_2_SL)) /* PS2_DATA2 */
 #else
@@ -264,7 +268,7 @@
 #define NPCX_ALT_GPIO_4_0 ALT(4, 0, NPCX_ALT(3, TA1_SL1)) /* TA1_SEL1 */
 #define NPCX_ALT_GPIO_7_3 ALT(7, 3, NPCX_ALT(3, TA2_SL1)) /* TA2_SEL1 */
 #define NPCX_ALT_GPIO_9_3 ALT(9, 3, NPCX_ALT(C, TA1_SL2)) /* TA1_SEL2 */
-#ifdef CONFIG_PS2
+#if defined(CONFIG_PS2) && defined(NPCX_PS2_MODULE_3)
 #define NPCX_ALT_GPIO_A_6 ALT(A, 6, NPCX_ALT(C, PS2_3_SL2)) /* PS2_CLK3 */
 #else
 #define NPCX_ALT_GPIO_A_6 ALT(A, 6, NPCX_ALT(C, TA2_SL2)) /* TA2_SEL2 */
@@ -289,7 +293,7 @@
 #define NPCX_ALT_GPIO_1_2 ALT(1, 2, NPCX_ALT_INV(8, NO_KSO07_SL)) /* KSO07 */
 /* KSO08 & CR_SOUT */
 #define NPCX_ALT_GPIO_1_1 ALT(1, 1, NPCX_ALT_INV(9, NO_KSO08_SL))
- /* KSO09 & CR_SIN */
+/* KSO09 & CR_SIN */
 #define NPCX_ALT_GPIO_1_0 ALT(1, 0, NPCX_ALT_INV(9, NO_KSO09_SL))
 #define NPCX_ALT_GPIO_0_7 ALT(0, 7, NPCX_ALT_INV(9, NO_KSO10_SL)) /* KSO10 */
 #define NPCX_ALT_GPIO_0_6 ALT(0, 6, NPCX_ALT_INV(9, NO_KSO11_SL)) /* KSO11 */
@@ -309,17 +313,21 @@
 
 /* Pin-Mux for UART2/32KHZ_OUT */
 #if defined(NPCX_SECOND_UART) && (CONFIG_CONSOLE_UART == 1)
-#define NPCX_ALT_GPIO_7_5 ALT(7, 5, NPCX_ALT(A, UART2_SL))    /* CR_SIN2 */
+#define NPCX_ALT_GPIO_7_5 ALT(7, 5, NPCX_ALT(A, UART2_SL)) /* CR_SIN2 */
 #else
-#define NPCX_ALT_GPIO_7_5 ALT(7, 5, NPCX_ALT(A, 32K_OUT_SL))  /* 32KHZ_OUT */
+#define NPCX_ALT_GPIO_7_5 ALT(7, 5, NPCX_ALT(A, 32K_OUT_SL)) /* 32KHZ_OUT */
 #endif
 
 /* PSL module (Optional) */
 #ifdef NPCX_PSL_MODE_SUPPORT
-#define NPCX_ALT_GPIO_D_2 ALT(D, 2, NPCX_ALT_INV(D, NPSL_IN1_SL)) /* PSL_IN1 */
-#define NPCX_ALT_GPIO_0_0 ALT(0, 0, NPCX_ALT_INV(D, NPSL_IN2_SL)) /* PSL_IN2 */
-#define NPCX_ALT_GPIO_0_1 ALT(0, 1, NPCX_ALT(D, PSL_IN3_SL))      /* PSL_IN3 */
-#define NPCX_ALT_GPIO_0_2 ALT(0, 2, NPCX_ALT(D, PSL_IN4_SL))      /* PSL_IN4 */
+#define NPCX_ALT_GPIO_D_2                                  \
+	ALT(D, 2, NPCX_ALT_INV(D, NPSL_IN1_SL)) /* PSL_IN1 \
+						 */
+#define NPCX_ALT_GPIO_0_0                                  \
+	ALT(0, 0, NPCX_ALT_INV(D, NPSL_IN2_SL)) /* PSL_IN2 \
+						 */
+#define NPCX_ALT_GPIO_0_1 ALT(0, 1, NPCX_ALT(D, PSL_IN3_SL)) /* PSL_IN3 */
+#define NPCX_ALT_GPIO_0_2 ALT(0, 2, NPCX_ALT(D, PSL_IN4_SL)) /* PSL_IN4 */
 #else
 #define NPCX_ALT_GPIO_D_2 /* NO PSL in NPCX7mnG series */
 #define NPCX_ALT_GPIO_0_0 /* NO PSL in NPCX7mnG series */
@@ -328,8 +336,8 @@
 #endif
 
 /* WOV module (Optional) */
-#if defined(NPCX_WOV_SUPPORT) && \
-	(defined(CONFIG_AUDIO_CODEC_I2S_RX) || defined(CONFIG_AUDIO_CODEC_WOV))
+#if defined(NPCX_WOV_SUPPORT) && (defined(CONFIG_AUDIO_CODEC_I2S_RX) || \
+				  defined(CONFIG_AUDIO_CODEC_WOV))
 #define NPCX_ALT_GPIO_9_5 /* Disable SPIP module if WOV is supported */
 #define NPCX_ALT_GPIO_A_3 /* Disable SPIP module if WOV is supported */
 #define NPCX_ALT_GPIO_A_1 /* Disable SPIP module if WOV is supported */
@@ -346,7 +354,7 @@
 #define NPCX_ALT_GPIO_A_3 ALT(A, 3, NPCX_ALT(0, SPIP_SL)) /* SPIP_MOSI */
 #define NPCX_ALT_GPIO_A_1 ALT(A, 1, NPCX_ALT(0, SPIP_SL)) /* SPIP_SCLK */
 
-#ifdef CONFIG_PS2
+#if defined(CONFIG_PS2) && defined(NPCX_PS2_MODULE_3)
 #define NPCX_ALT_GPIO_A_7 ALT(A, 7, NPCX_ALT(C, PS2_3_SL2)) /* PS2_DAT3 */
 #else
 #define NPCX_ALT_GPIO_A_7
@@ -356,6 +364,7 @@
 #define NPCX_ALT_GPIO_9_7
 #endif
 
+/* clang-format off */
 #define NPCX_ALT_TABLE { \
 	NPCX_ALT_GPIO_0_0 /* PSL_IN2 */               \
 	NPCX_ALT_GPIO_0_1 /* PSL_IN3 */               \
@@ -447,90 +456,110 @@
 	NPCX_ALT_GPIO_F_4 /* SMB5SDA1 */              \
 	NPCX_ALT_GPIO_F_5 /* SMB5SCL1 */              \
 }
+/* clang-format on */
 
 /*****************************************************************************/
 /* Macro functions for Low-Voltage mapping table */
 
 /* Low-Voltage GPIO Control 0 */
-#define NPCX_LVOL_CTRL_0_0  NPCX_GPIO(B, 5)
-#define NPCX_LVOL_CTRL_0_1  NPCX_GPIO(B, 4)
-#define NPCX_LVOL_CTRL_0_2  NPCX_GPIO(B, 3)
-#define NPCX_LVOL_CTRL_0_3  NPCX_GPIO(B, 2)
-#define NPCX_LVOL_CTRL_0_4  NPCX_GPIO(9, 0)
-#define NPCX_LVOL_CTRL_0_5  NPCX_GPIO(8, 7)
-#define NPCX_LVOL_CTRL_0_6  NPCX_GPIO(0, 0)
-#define NPCX_LVOL_CTRL_0_7  NPCX_GPIO(3, 3)
+#define NPCX_LVOL_CTRL_0_0 NPCX_GPIO(B, 5)
+#define NPCX_LVOL_CTRL_0_1 NPCX_GPIO(B, 4)
+#define NPCX_LVOL_CTRL_0_2 NPCX_GPIO(B, 3)
+#define NPCX_LVOL_CTRL_0_3 NPCX_GPIO(B, 2)
+#define NPCX_LVOL_CTRL_0_4 NPCX_GPIO(9, 0)
+#define NPCX_LVOL_CTRL_0_5 NPCX_GPIO(8, 7)
+#define NPCX_LVOL_CTRL_0_6 NPCX_GPIO(0, 0)
+#define NPCX_LVOL_CTRL_0_7 NPCX_GPIO(3, 3)
 
 /* Low-Voltage GPIO Control 1 */
-#define NPCX_LVOL_CTRL_1_0  NPCX_GPIO(9, 2)
-#define NPCX_LVOL_CTRL_1_1  NPCX_GPIO(9, 1)
-#define NPCX_LVOL_CTRL_1_2  NPCX_GPIO(D, 1)
-#define NPCX_LVOL_CTRL_1_3  NPCX_GPIO(D, 0)
-#define NPCX_LVOL_CTRL_1_4  NPCX_GPIO(3, 6)
-#define NPCX_LVOL_CTRL_1_5  NPCX_GPIO(6, 4)
-#define NPCX_LVOL_CTRL_1_6  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_1_7  NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_1_0 NPCX_GPIO(9, 2)
+#define NPCX_LVOL_CTRL_1_1 NPCX_GPIO(9, 1)
+#define NPCX_LVOL_CTRL_1_2 NPCX_GPIO(D, 1)
+#define NPCX_LVOL_CTRL_1_3 NPCX_GPIO(D, 0)
+#define NPCX_LVOL_CTRL_1_4 NPCX_GPIO(3, 6)
+#define NPCX_LVOL_CTRL_1_5 NPCX_GPIO(6, 4)
+#define NPCX_LVOL_CTRL_1_6 NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_1_7 NPCX_GPIO_NONE
 
 /* Low-Voltage GPIO Control 2 */
-#define NPCX_LVOL_CTRL_2_0  NPCX_GPIO(7, 4)
+#define NPCX_LVOL_CTRL_2_0 NPCX_GPIO(7, 4)
 #ifdef NPCX_PSL_MODE_SUPPORT
-#define NPCX_LVOL_CTRL_2_1  NPCX_GPIO_NONE /* Remove 1.8V support since PSL */
-#define NPCX_LVOL_CTRL_2_2  NPCX_GPIO_NONE /* Remove 1.8V support since PSL */
+#define NPCX_LVOL_CTRL_2_1 NPCX_GPIO_NONE /* Remove 1.8V support since PSL */
+#define NPCX_LVOL_CTRL_2_2 NPCX_GPIO_NONE /* Remove 1.8V support since PSL */
 #else
-#define NPCX_LVOL_CTRL_2_1  NPCX_GPIO(8, 4)
-#define NPCX_LVOL_CTRL_2_2  NPCX_GPIO(8, 5)
+#define NPCX_LVOL_CTRL_2_1 NPCX_GPIO(8, 4)
+#define NPCX_LVOL_CTRL_2_2 NPCX_GPIO(8, 5)
 #endif
 
-#define NPCX_LVOL_CTRL_2_3  NPCX_GPIO(7, 3)
-#define NPCX_LVOL_CTRL_2_4  NPCX_GPIO(C, 1)
-#define NPCX_LVOL_CTRL_2_5  NPCX_GPIO(C, 7)
+#define NPCX_LVOL_CTRL_2_3 NPCX_GPIO(7, 3)
+#define NPCX_LVOL_CTRL_2_4 NPCX_GPIO(C, 1)
+#define NPCX_LVOL_CTRL_2_5 NPCX_GPIO(C, 7)
 #ifdef NPCX_EXT32K_OSC_SUPPORT
-#define NPCX_LVOL_CTRL_2_6  NPCX_GPIO_NONE /* Remove 1.8V support since CLKIN */
+#define NPCX_LVOL_CTRL_2_6                                \
+	NPCX_GPIO_NONE /* Remove 1.8V support since CLKIN \
+			*/
 #else
-#define NPCX_LVOL_CTRL_2_6  NPCX_GPIO(E, 7)
+#define NPCX_LVOL_CTRL_2_6 NPCX_GPIO(E, 7)
 #endif
-#define NPCX_LVOL_CTRL_2_7  NPCX_GPIO(3, 4)
+#define NPCX_LVOL_CTRL_2_7 NPCX_GPIO(3, 4)
 
 /* Low-Voltage GPIO Control 3 */
-#define NPCX_LVOL_CTRL_3_0  NPCX_GPIO(C, 6)
-#define NPCX_LVOL_CTRL_3_1  NPCX_GPIO(3, 7)
-#define NPCX_LVOL_CTRL_3_2  NPCX_GPIO(4, 0)
+#define NPCX_LVOL_CTRL_3_0 NPCX_GPIO(C, 6)
+#define NPCX_LVOL_CTRL_3_1 NPCX_GPIO(3, 7)
+#define NPCX_LVOL_CTRL_3_2 NPCX_GPIO(4, 0)
 #ifdef NPCX_EXT32K_OSC_SUPPORT
-#define NPCX_LVOL_CTRL_3_3  NPCX_GPIO_NONE /* Remove 1.8V support since CLKOUT*/
+#define NPCX_LVOL_CTRL_3_3                          \
+	NPCX_GPIO_NONE /* Remove 1.8V support since \
+			  CLKOUT*/
 #else
-#define NPCX_LVOL_CTRL_3_3  NPCX_GPIO(7, 1)
+#define NPCX_LVOL_CTRL_3_3 NPCX_GPIO(7, 1)
 #endif
-#define NPCX_LVOL_CTRL_3_4  NPCX_GPIO(8, 2)
-#define NPCX_LVOL_CTRL_3_5  NPCX_GPIO(7, 5)
-#define NPCX_LVOL_CTRL_3_6  NPCX_GPIO(8, 0)
-#define NPCX_LVOL_CTRL_3_7  NPCX_GPIO(C, 5)
+#define NPCX_LVOL_CTRL_3_4 NPCX_GPIO(8, 2)
+#define NPCX_LVOL_CTRL_3_5 NPCX_GPIO(7, 5)
+#define NPCX_LVOL_CTRL_3_6 NPCX_GPIO(8, 0)
+#define NPCX_LVOL_CTRL_3_7 NPCX_GPIO(C, 5)
 
 /* Low-Voltage GPIO Control 4 */
-#define NPCX_LVOL_CTRL_4_0  NPCX_GPIO(8, 6)
-#define NPCX_LVOL_CTRL_4_1  NPCX_GPIO(C, 2)
-#define NPCX_LVOL_CTRL_4_2  NPCX_GPIO(F, 3)
-#define NPCX_LVOL_CTRL_4_3  NPCX_GPIO(F, 2)
-#define NPCX_LVOL_CTRL_4_4  NPCX_GPIO(F, 5)
-#define NPCX_LVOL_CTRL_4_5  NPCX_GPIO(F, 4)
-#define NPCX_LVOL_CTRL_4_6  NPCX_GPIO(E, 4)
-#define NPCX_LVOL_CTRL_4_7  NPCX_GPIO(E, 3)
+#define NPCX_LVOL_CTRL_4_0 NPCX_GPIO(8, 6)
+#define NPCX_LVOL_CTRL_4_1 NPCX_GPIO(C, 2)
+#define NPCX_LVOL_CTRL_4_2 NPCX_GPIO(F, 3)
+#define NPCX_LVOL_CTRL_4_3 NPCX_GPIO(F, 2)
+#define NPCX_LVOL_CTRL_4_4 NPCX_GPIO(F, 5)
+#define NPCX_LVOL_CTRL_4_5 NPCX_GPIO(F, 4)
+#define NPCX_LVOL_CTRL_4_6 NPCX_GPIO(E, 4)
+#define NPCX_LVOL_CTRL_4_7 NPCX_GPIO(E, 3)
 
 /* Low-Voltage GPIO Control 5 */
-#define NPCX_LVOL_CTRL_5_0  NPCX_GPIO(7, 2)
-#define NPCX_LVOL_CTRL_5_1  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_5_2  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_5_3  NPCX_GPIO(5, 0)
-#define NPCX_LVOL_CTRL_5_4  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_5_5  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_5_6  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_5_7  NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_5_0 NPCX_GPIO(7, 2)
+#define NPCX_LVOL_CTRL_5_1 NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_5_2 NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_5_3 NPCX_GPIO(5, 0)
+#define NPCX_LVOL_CTRL_5_4 NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_5_5 NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_5_6 NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_5_7 NPCX_GPIO_NONE
 
 /* 6 Low-Voltage Control Groups on npcx7 */
-#define NPCX_LVOL_TABLE { { NPCX_LVOL_CTRL_ITEMS(0), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(1), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(2), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(3), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(4), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(5), }, }
+#define NPCX_LVOL_TABLE                                  \
+	{                                                \
+		{                                        \
+			NPCX_LVOL_CTRL_ITEMS(0),         \
+		},                                       \
+			{                                \
+				NPCX_LVOL_CTRL_ITEMS(1), \
+			},                               \
+			{                                \
+				NPCX_LVOL_CTRL_ITEMS(2), \
+			},                               \
+			{                                \
+				NPCX_LVOL_CTRL_ITEMS(3), \
+			},                               \
+			{                                \
+				NPCX_LVOL_CTRL_ITEMS(4), \
+			},                               \
+			{                                \
+				NPCX_LVOL_CTRL_ITEMS(5), \
+			},                               \
+	}
 
 #endif /* __CROS_EC_GPIO_CHIP_NPCX7_H */
diff --git a/chip/npcx/gpio_chip-npcx9.h b/chip/npcx/gpio_chip-npcx9.h
index a80a1b899a..aef2f4f044 100644
--- a/chip/npcx/gpio_chip-npcx9.h
+++ b/chip/npcx/gpio_chip-npcx9.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,6 +6,10 @@
 #ifndef __CROS_EC_GPIO_CHIP_NPCX9_H
 #define __CROS_EC_GPIO_CHIP_NPCX9_H
 
+#ifndef NPCX9_PWM1_SEL
+#define NPCX9_PWM1_SEL 0
+#endif /* NPCX9_PWM1_SEL */
+
 /*****************************************************************************/
 /* Macro functions for MIWU mapping table */
 
@@ -196,7 +200,7 @@
 /* Pin-Mux for PWM1/SMB6_0 */
 #if NPCX9_PWM1_SEL
 #define NPCX_ALT_GPIO_C_1 /* No I2CSDA since GPIOC2 used as PWM1 */
-#define NPCX_ALT_GPIO_C_2 ALT(C, 2, NPCX_ALT(4, PWM1_SL))   /* PWM1 */
+#define NPCX_ALT_GPIO_C_2 ALT(C, 2, NPCX_ALT(4, PWM1_SL)) /* PWM1 */
 #else
 #define NPCX_ALT_GPIO_C_1 ALT(C, 1, NPCX_ALT(2, I2C6_0_SL)) /* SMB6SDA0 */
 #define NPCX_ALT_GPIO_C_2 ALT(C, 2, NPCX_ALT(2, I2C6_0_SL)) /* SMB6SCL0 */
@@ -208,33 +212,44 @@
 #define NPCX_ALT_GPIO_4_3 ALT(4, 3, NPCX_ALT(6, ADC2_SL)) /* ADC2  */
 #define NPCX_ALT_GPIO_4_2 ALT(4, 2, NPCX_ALT(6, ADC3_SL)) /* ADC3  */
 #define NPCX_ALT_GPIO_4_1 ALT(4, 1, NPCX_ALT(6, ADC4_SL)) /* ADC4  */
-#ifdef CONFIG_PS2
+#if defined(CONFIG_PS2) && defined(NPCX_PS2_MODULE_2)
 #define NPCX_ALT_GPIO_3_7 ALT(3, 7, NPCX_ALT(3, PS2_2_SL)) /* PS2_CLK2 */
 #define NPCX_ALT_GPIO_3_4 ALT(3, 4, NPCX_ALT(3, PS2_2_SL)) /* PS2_DATA2 */
 #else
 #define NPCX_ALT_GPIO_3_7 ALT(3, 7, NPCX_ALT(F, ADC5_SL)) /* ADC5  */
 #define NPCX_ALT_GPIO_3_4 ALT(3, 4, NPCX_ALT(F, ADC6_SL)) /* ADC6  */
 #endif
-#define NPCX_ALT_GPIO_F_1 ALT(F, 1, NPCX_ALT(F, ADC8_SL))  /* ADC8  */
-#define NPCX_ALT_GPIO_E_1 ALT(E, 1, NPCX_ALT(F, ADC7_SL))  /* ADC7  */
-#define NPCX_ALT_GPIO_F_0 ALT(F, 0, NPCX_ALT(F, ADC9_SL))  /* ADC9  */
+#define NPCX_ALT_GPIO_F_1 ALT(F, 1, NPCX_ALT(F, ADC8_SL)) /* ADC8  */
+#define NPCX_ALT_GPIO_E_1 ALT(E, 1, NPCX_ALT(F, ADC7_SL)) /* ADC7  */
+#define NPCX_ALT_GPIO_F_0 ALT(F, 0, NPCX_ALT(F, ADC9_SL)) /* ADC9  */
 #define NPCX_ALT_GPIO_E_0 ALT(E, 0, NPCX_ALT(F, ADC10_SL)) /* AD10  */
 #define NPCX_ALT_GPIO_C_7 ALT(C, 7, NPCX_ALT(F, ADC11_SL)) /* AD11  */
 
 /* PS/2 Module */
-#define NPCX_ALT_GPIO_6_7 ALT(6, 7, NPCX_ALT(3, PS2_0_SL))  /* PS2_CLK0 */
-#define NPCX_ALT_GPIO_7_0 ALT(7, 0, NPCX_ALT(3, PS2_0_SL))  /* PS2_DATA0 */
-#define NPCX_ALT_GPIO_6_2 ALT(6, 2, NPCX_ALT(3, PS2_1_SL))  /* PS2_CLK1 */
-#define NPCX_ALT_GPIO_6_3 ALT(6, 3, NPCX_ALT(3, PS2_1_SL))  /* PS2_DATA1 */
+#define NPCX_ALT_GPIO_6_7 ALT(6, 7, NPCX_ALT(3, PS2_0_SL)) /* PS2_CLK0 */
+#define NPCX_ALT_GPIO_7_0 ALT(7, 0, NPCX_ALT(3, PS2_0_SL)) /* PS2_DATA0 */
+#define NPCX_ALT_GPIO_6_2 ALT(6, 2, NPCX_ALT(3, PS2_1_SL)) /* PS2_CLK1 */
+#define NPCX_ALT_GPIO_6_3 ALT(6, 3, NPCX_ALT(3, PS2_1_SL)) /* PS2_DATA1 */
+#if defined(CONFIG_PS2) && defined(NPCX_PS2_MODULE_3)
 #define NPCX_ALT_GPIO_A_7 ALT(A, 7, NPCX_ALT(C, PS2_3_SL2)) /* PS2_DAT3 */
+#else
+#define NPCX_ALT_GPIO_A_7
+#endif
 
 /* UART Module */
-#define NPCX_ALT_GPIO_6_4 ALT(6, 4, NPCX_ALT(J, CR_SIN1_SL2)) /* CR_SIN1_SL2 */
-#define NPCX_ALT_GPIO_6_5 ALT(6, 5, NPCX_ALT(J, CR_SOUT1_SL2))/* CR_SOUT1_SL2 */
-#define NPCX_ALT_GPIO_7_5 ALT(7, 5, NPCX_ALT(J, CR_SIN2_SL))  /* CR_SIN2_SL */
-#define NPCX_ALT_GPIO_8_6 ALT(8, 6, NPCX_ALT(J, CR_SOUT2_SL)) /* CR_SOUT2_SL */
-#define NPCX_ALT_GPIO_D_4 ALT(D, 4, NPCX_ALT(J, CR_SIN3_SL))  /* CR_SIN3_SL */
-#define NPCX_ALT_GPIO_D_6 ALT(D, 6, NPCX_ALT(J, CR_SOUT3_SL)) /* CR_SOUT3_SL */
+#define NPCX_ALT_GPIO_6_4                                  \
+	ALT(6, 4, NPCX_ALT(J, CR_SIN1_SL2)) /* CR_SIN1_SL2 \
+					     */
+#define NPCX_ALT_GPIO_6_5 \
+	ALT(6, 5, NPCX_ALT(J, CR_SOUT1_SL2)) /* CR_SOUT1_SL2 */
+#define NPCX_ALT_GPIO_7_5 ALT(7, 5, NPCX_ALT(J, CR_SIN2_SL)) /* CR_SIN2_SL */
+#define NPCX_ALT_GPIO_8_6                                  \
+	ALT(8, 6, NPCX_ALT(J, CR_SOUT2_SL)) /* CR_SOUT2_SL \
+					     */
+#define NPCX_ALT_GPIO_D_4 ALT(D, 4, NPCX_ALT(J, CR_SIN3_SL)) /* CR_SIN3_SL */
+#define NPCX_ALT_GPIO_D_6                                  \
+	ALT(D, 6, NPCX_ALT(J, CR_SOUT3_SL)) /* CR_SOUT3_SL \
+					     */
 
 /* PWM Module */
 #define NPCX_ALT_GPIO_C_3 ALT(C, 3, NPCX_ALT(4, PWM0_SL)) /* PWM0 */
@@ -249,7 +264,7 @@
 #define NPCX_ALT_GPIO_4_0 ALT(4, 0, NPCX_ALT(3, TA1_SL1)) /* TA1_SEL1 */
 #define NPCX_ALT_GPIO_7_3 ALT(7, 3, NPCX_ALT(3, TA2_SL1)) /* TA2_SEL1 */
 #define NPCX_ALT_GPIO_9_3 ALT(9, 3, NPCX_ALT(C, TA1_SL2)) /* TA1_SEL2 */
-#ifdef CONFIG_PS2
+#if defined(CONFIG_PS2) && defined(NPCX_PS2_MODULE_3)
 #define NPCX_ALT_GPIO_A_6 ALT(A, 6, NPCX_ALT(C, PS2_3_SL2)) /* PS2_CLK3 */
 #else
 #define NPCX_ALT_GPIO_A_6 ALT(A, 6, NPCX_ALT(C, TA2_SL2)) /* TA2_SEL2 */
@@ -274,7 +289,7 @@
 #define NPCX_ALT_GPIO_1_2 ALT(1, 2, NPCX_ALT_INV(8, NO_KSO07_SL)) /* KSO07 */
 /* KSO08 & CR_SOUT */
 #define NPCX_ALT_GPIO_1_1 ALT(1, 1, NPCX_ALT_INV(9, NO_KSO08_SL))
- /* KSO09 & CR_SIN */
+/* KSO09 & CR_SIN */
 #define NPCX_ALT_GPIO_1_0 ALT(1, 0, NPCX_ALT_INV(9, NO_KSO09_SL))
 #define NPCX_ALT_GPIO_0_7 ALT(0, 7, NPCX_ALT_INV(9, NO_KSO10_SL)) /* KSO10 */
 #define NPCX_ALT_GPIO_0_6 ALT(0, 6, NPCX_ALT_INV(9, NO_KSO11_SL)) /* KSO11 */
@@ -286,17 +301,22 @@
 #define NPCX_ALT_GPIO_B_1 ALT(B, 1, NPCX_ALT_INV(A, NO_KSO17_SL)) /* KSO17 */
 
 /* PSL module */
-#define NPCX_ALT_GPIO_D_2 ALT(D, 2, NPCX_ALT_INV(D, NPSL_IN1_SL)) /* PSL_IN1 */
-#define NPCX_ALT_GPIO_0_0 ALT(0, 0, NPCX_ALT_INV(D, NPSL_IN2_SL)) /* PSL_IN2 */
-#define NPCX_ALT_GPIO_0_1 ALT(0, 1, NPCX_ALT(D, PSL_IN3_SL))      /* PSL_IN3 */
-#define NPCX_ALT_GPIO_0_2 ALT(0, 2, NPCX_ALT(D, PSL_IN4_SL))      /* PSL_IN4 */
-#define NPCX_ALT_GPIO_D_7 ALT(D, 7, NPCX_ALT(G, PSL_GPO_SL))      /* PSL_GPO */
+#define NPCX_ALT_GPIO_D_2                                  \
+	ALT(D, 2, NPCX_ALT_INV(D, NPSL_IN1_SL)) /* PSL_IN1 \
+						 */
+#define NPCX_ALT_GPIO_0_0                                  \
+	ALT(0, 0, NPCX_ALT_INV(D, NPSL_IN2_SL)) /* PSL_IN2 \
+						 */
+#define NPCX_ALT_GPIO_0_1 ALT(0, 1, NPCX_ALT(D, PSL_IN3_SL)) /* PSL_IN3 */
+#define NPCX_ALT_GPIO_0_2 ALT(0, 2, NPCX_ALT(D, PSL_IN4_SL)) /* PSL_IN4 */
+#define NPCX_ALT_GPIO_D_7 ALT(D, 7, NPCX_ALT(G, PSL_GPO_SL)) /* PSL_GPO */
 
 /* SPI Module */
 #define NPCX_ALT_GPIO_9_5 ALT(9, 5, NPCX_ALT(0, SPIP_SL)) /* SPIP_MISO */
 #define NPCX_ALT_GPIO_A_3 ALT(A, 3, NPCX_ALT(0, SPIP_SL)) /* SPIP_MOSI */
 #define NPCX_ALT_GPIO_A_1 ALT(A, 1, NPCX_ALT(0, SPIP_SL)) /* SPIP_SCLK */
 
+/* clang-format off */
 #define NPCX_ALT_TABLE { \
 	NPCX_ALT_GPIO_0_0 /* PSL_IN2 */               \
 	NPCX_ALT_GPIO_0_1 /* PSL_IN3 */               \
@@ -387,76 +407,92 @@
 	NPCX_ALT_GPIO_F_4 /* SMB5SDA1 */              \
 	NPCX_ALT_GPIO_F_5 /* SMB5SCL1 */              \
 }
+/* clang-format on */
 
 /*****************************************************************************/
 /* Macro functions for Low-Voltage mapping table */
 
 /* Low-Voltage GPIO Control 0 */
-#define NPCX_LVOL_CTRL_0_0  NPCX_GPIO(B, 5)
-#define NPCX_LVOL_CTRL_0_1  NPCX_GPIO(B, 4)
-#define NPCX_LVOL_CTRL_0_2  NPCX_GPIO(B, 3)
-#define NPCX_LVOL_CTRL_0_3  NPCX_GPIO(B, 2)
-#define NPCX_LVOL_CTRL_0_4  NPCX_GPIO(9, 0)
-#define NPCX_LVOL_CTRL_0_5  NPCX_GPIO(8, 7)
-#define NPCX_LVOL_CTRL_0_6  NPCX_GPIO(0, 0)
-#define NPCX_LVOL_CTRL_0_7  NPCX_GPIO(3, 3)
+#define NPCX_LVOL_CTRL_0_0 NPCX_GPIO(B, 5)
+#define NPCX_LVOL_CTRL_0_1 NPCX_GPIO(B, 4)
+#define NPCX_LVOL_CTRL_0_2 NPCX_GPIO(B, 3)
+#define NPCX_LVOL_CTRL_0_3 NPCX_GPIO(B, 2)
+#define NPCX_LVOL_CTRL_0_4 NPCX_GPIO(9, 0)
+#define NPCX_LVOL_CTRL_0_5 NPCX_GPIO(8, 7)
+#define NPCX_LVOL_CTRL_0_6 NPCX_GPIO(0, 0)
+#define NPCX_LVOL_CTRL_0_7 NPCX_GPIO(3, 3)
 
 /* Low-Voltage GPIO Control 1 */
-#define NPCX_LVOL_CTRL_1_0  NPCX_GPIO(9, 2)
-#define NPCX_LVOL_CTRL_1_1  NPCX_GPIO(9, 1)
-#define NPCX_LVOL_CTRL_1_2  NPCX_GPIO(D, 1)
-#define NPCX_LVOL_CTRL_1_3  NPCX_GPIO(D, 0)
-#define NPCX_LVOL_CTRL_1_4  NPCX_GPIO(3, 6)
-#define NPCX_LVOL_CTRL_1_5  NPCX_GPIO(6, 4)
-#define NPCX_LVOL_CTRL_1_6  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_1_7  NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_1_0 NPCX_GPIO(9, 2)
+#define NPCX_LVOL_CTRL_1_1 NPCX_GPIO(9, 1)
+#define NPCX_LVOL_CTRL_1_2 NPCX_GPIO(D, 1)
+#define NPCX_LVOL_CTRL_1_3 NPCX_GPIO(D, 0)
+#define NPCX_LVOL_CTRL_1_4 NPCX_GPIO(3, 6)
+#define NPCX_LVOL_CTRL_1_5 NPCX_GPIO(6, 4)
+#define NPCX_LVOL_CTRL_1_6 NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_1_7 NPCX_GPIO_NONE
 
 /* Low-Voltage GPIO Control 2 */
-#define NPCX_LVOL_CTRL_2_0  NPCX_GPIO(7, 4)
-#define NPCX_LVOL_CTRL_2_1  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_2_2  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_2_3  NPCX_GPIO(7, 3)
-#define NPCX_LVOL_CTRL_2_4  NPCX_GPIO(C, 1)
-#define NPCX_LVOL_CTRL_2_5  NPCX_GPIO(C, 7)
-#define NPCX_LVOL_CTRL_2_6  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_2_7  NPCX_GPIO(3, 4)
+#define NPCX_LVOL_CTRL_2_0 NPCX_GPIO(7, 4)
+#define NPCX_LVOL_CTRL_2_1 NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_2_2 NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_2_3 NPCX_GPIO(7, 3)
+#define NPCX_LVOL_CTRL_2_4 NPCX_GPIO(C, 1)
+#define NPCX_LVOL_CTRL_2_5 NPCX_GPIO(C, 7)
+#define NPCX_LVOL_CTRL_2_6 NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_2_7 NPCX_GPIO(3, 4)
 
 /* Low-Voltage GPIO Control 3 */
-#define NPCX_LVOL_CTRL_3_0  NPCX_GPIO(C, 6)
-#define NPCX_LVOL_CTRL_3_1  NPCX_GPIO(3, 7)
-#define NPCX_LVOL_CTRL_3_2  NPCX_GPIO(4, 0)
-#define NPCX_LVOL_CTRL_3_3  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_3_4  NPCX_GPIO(8, 2)
-#define NPCX_LVOL_CTRL_3_5  NPCX_GPIO(7, 5)
-#define NPCX_LVOL_CTRL_3_6  NPCX_GPIO(8, 0)
-#define NPCX_LVOL_CTRL_3_7  NPCX_GPIO(C, 5)
+#define NPCX_LVOL_CTRL_3_0 NPCX_GPIO(C, 6)
+#define NPCX_LVOL_CTRL_3_1 NPCX_GPIO(3, 7)
+#define NPCX_LVOL_CTRL_3_2 NPCX_GPIO(4, 0)
+#define NPCX_LVOL_CTRL_3_3 NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_3_4 NPCX_GPIO(8, 2)
+#define NPCX_LVOL_CTRL_3_5 NPCX_GPIO(7, 5)
+#define NPCX_LVOL_CTRL_3_6 NPCX_GPIO(8, 0)
+#define NPCX_LVOL_CTRL_3_7 NPCX_GPIO(C, 5)
 
 /* Low-Voltage GPIO Control 4 */
-#define NPCX_LVOL_CTRL_4_0  NPCX_GPIO(8, 6)
-#define NPCX_LVOL_CTRL_4_1  NPCX_GPIO(C, 2)
-#define NPCX_LVOL_CTRL_4_2  NPCX_GPIO(F, 3)
-#define NPCX_LVOL_CTRL_4_3  NPCX_GPIO(F, 2)
-#define NPCX_LVOL_CTRL_4_4  NPCX_GPIO(F, 5)
-#define NPCX_LVOL_CTRL_4_5  NPCX_GPIO(F, 4)
-#define NPCX_LVOL_CTRL_4_6  NPCX_GPIO(E, 4)
-#define NPCX_LVOL_CTRL_4_7  NPCX_GPIO(E, 3)
+#define NPCX_LVOL_CTRL_4_0 NPCX_GPIO(8, 6)
+#define NPCX_LVOL_CTRL_4_1 NPCX_GPIO(C, 2)
+#define NPCX_LVOL_CTRL_4_2 NPCX_GPIO(F, 3)
+#define NPCX_LVOL_CTRL_4_3 NPCX_GPIO(F, 2)
+#define NPCX_LVOL_CTRL_4_4 NPCX_GPIO(F, 5)
+#define NPCX_LVOL_CTRL_4_5 NPCX_GPIO(F, 4)
+#define NPCX_LVOL_CTRL_4_6 NPCX_GPIO(E, 4)
+#define NPCX_LVOL_CTRL_4_7 NPCX_GPIO(E, 3)
 
 /* Low-Voltage GPIO Control 5 */
-#define NPCX_LVOL_CTRL_5_0  NPCX_GPIO(7, 2)
-#define NPCX_LVOL_CTRL_5_1  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_5_2  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_5_3  NPCX_GPIO(5, 0)
-#define NPCX_LVOL_CTRL_5_4  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_5_5  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_5_6  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_5_7  NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_5_0 NPCX_GPIO(7, 2)
+#define NPCX_LVOL_CTRL_5_1 NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_5_2 NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_5_3 NPCX_GPIO(5, 0)
+#define NPCX_LVOL_CTRL_5_4 NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_5_5 NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_5_6 NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_5_7 NPCX_GPIO_NONE
 
 /* 6 Low-Voltage Control Groups on npcx7 */
-#define NPCX_LVOL_TABLE { { NPCX_LVOL_CTRL_ITEMS(0), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(1), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(2), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(3), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(4), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(5), }, }
+#define NPCX_LVOL_TABLE                                  \
+	{                                                \
+		{                                        \
+			NPCX_LVOL_CTRL_ITEMS(0),         \
+		},                                       \
+			{                                \
+				NPCX_LVOL_CTRL_ITEMS(1), \
+			},                               \
+			{                                \
+				NPCX_LVOL_CTRL_ITEMS(2), \
+			},                               \
+			{                                \
+				NPCX_LVOL_CTRL_ITEMS(3), \
+			},                               \
+			{                                \
+				NPCX_LVOL_CTRL_ITEMS(4), \
+			},                               \
+			{                                \
+				NPCX_LVOL_CTRL_ITEMS(5), \
+			},                               \
+	}
 
 #endif /* __CROS_EC_GPIO_CHIP_NPCX9_H */
diff --git a/chip/npcx/gpio_chip.h b/chip/npcx/gpio_chip.h
index 2d0b2b4e9b..5f60cdfb40 100644
--- a/chip/npcx/gpio_chip.h
+++ b/chip/npcx/gpio_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,37 +9,40 @@
 struct npcx_wui {
 	uint8_t table : 2;
 	uint8_t group : 3;
-	uint8_t bit   : 3;
+	uint8_t bit : 3;
 };
 
 /* Macros to initialize the MIWU mapping table. */
 #define NPCX_WUI_GPIO_PIN(port, index) NPCX_WUI_GPIO_##port##_##index
-#define WUI(tbl, grp, idx) ((struct npcx_wui) { .table = tbl, .group = grp, \
-						.bit = idx })
-#define WUI_INT(tbl, grp)  WUI(tbl, grp, 0)
-#define WUI_NONE ((struct npcx_wui) { .table = MIWU_TABLE_COUNT, .group = 0, \
-				      .bit = 0 })
+#define WUI(tbl, grp, idx) \
+	((struct npcx_wui){ .table = tbl, .group = grp, .bit = idx })
+#define WUI_INT(tbl, grp) WUI(tbl, grp, 0)
+#define WUI_NONE \
+	((struct npcx_wui){ .table = MIWU_TABLE_COUNT, .group = 0, .bit = 0 })
 
 /* Macros to initialize the alternative and low voltage mapping table. */
-#define NPCX_GPIO_NONE ((struct npcx_gpio) {.port = 0, .bit = 0, .valid = 0})
-#define NPCX_GPIO(grp, pin) ((struct npcx_gpio) {.port = GPIO_PORT_##grp, \
-							.bit = pin, .valid = 1})
+#define NPCX_GPIO_NONE ((struct npcx_gpio){ .port = 0, .bit = 0, .valid = 0 })
+#define NPCX_GPIO(grp, pin) \
+	((struct npcx_gpio){ .port = GPIO_PORT_##grp, .bit = pin, .valid = 1 })
 
-#define NPCX_ALT(grp, pin) ((struct npcx_alt) {.group = ALT_GROUP_##grp, \
-			.bit = NPCX_DEVALT##grp##_##pin, .inverted = 0 })
-#define NPCX_ALT_INV(grp, pin) ((struct npcx_alt) {.group = ALT_GROUP_##grp, \
-			.bit = NPCX_DEVALT##grp##_##pin, .inverted = 1 })
-#define ALT(port, index, _alt) { .gpio = NPCX_GPIO(port, index), \
-			.alt = (_alt) },
+#define NPCX_ALT(grp, pin)                                   \
+	((struct npcx_alt){ .group = ALT_GROUP_##grp,        \
+			    .bit = NPCX_DEVALT##grp##_##pin, \
+			    .inverted = 0 })
+#define NPCX_ALT_INV(grp, pin)                               \
+	((struct npcx_alt){ .group = ALT_GROUP_##grp,        \
+			    .bit = NPCX_DEVALT##grp##_##pin, \
+			    .inverted = 1 })
+#define ALT(port, index, _alt) \
+	{ .gpio = NPCX_GPIO(port, index), .alt = (_alt) },
 
-#define NPCX_LVOL_CTRL_ITEMS(ctrl) { NPCX_LVOL_CTRL_##ctrl##_0, \
-				     NPCX_LVOL_CTRL_##ctrl##_1, \
-				     NPCX_LVOL_CTRL_##ctrl##_2, \
-				     NPCX_LVOL_CTRL_##ctrl##_3, \
-				     NPCX_LVOL_CTRL_##ctrl##_4, \
-				     NPCX_LVOL_CTRL_##ctrl##_5, \
-				     NPCX_LVOL_CTRL_##ctrl##_6, \
-				     NPCX_LVOL_CTRL_##ctrl##_7, }
+#define NPCX_LVOL_CTRL_ITEMS(ctrl)                                            \
+	{                                                                     \
+		NPCX_LVOL_CTRL_##ctrl##_0, NPCX_LVOL_CTRL_##ctrl##_1,         \
+			NPCX_LVOL_CTRL_##ctrl##_2, NPCX_LVOL_CTRL_##ctrl##_3, \
+			NPCX_LVOL_CTRL_##ctrl##_4, NPCX_LVOL_CTRL_##ctrl##_5, \
+			NPCX_LVOL_CTRL_##ctrl##_6, NPCX_LVOL_CTRL_##ctrl##_7, \
+	}
 
 /**
  * Switch NPCX UART pins back to normal GPIOs.
diff --git a/chip/npcx/header.c b/chip/npcx/header.c
index 0ba3ee59d6..81e5e986af 100644
--- a/chip/npcx/header.c
+++ b/chip/npcx/header.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,65 +10,66 @@
  * This header is used by Nuvoton EC Booter.
  */
 
-#include <stdint.h>
-
 #include "config.h"
 #include "registers.h"
 
+#include <stdint.h>
+
 /* Signature used by fw header */
-#define SIG_FW_EC           0x2A3B4D5E
+#define SIG_FW_EC 0x2A3B4D5E
 
 /* Definition used by error detection configuration */
-#define CHECK_CRC	    0x00
-#define CHECK_CHECKSUM	    0x01
-#define ERROR_DETECTION_EN  0x02
+#define CHECK_CRC 0x00
+#define CHECK_CHECKSUM 0x01
+#define ERROR_DETECTION_EN 0x02
 #define ERROR_DETECTION_DIS 0x00
 
 /* Code RAM addresses use by header */
 /* Put FW at the begin of CODE RAM */
-#define FW_START_ADDR  CONFIG_PROGRAM_MEMORY_BASE
+#define FW_START_ADDR CONFIG_PROGRAM_MEMORY_BASE
 
 /* TODO: It will be filled automatically by ECST */
 /* The entry point of reset handler (filled by ECST tool)*/
-#define FW_ENTRY_ADDR  0x100A8169
+#define FW_ENTRY_ADDR 0x100A8169
 
 /* Error detection addresses use by header (A offset relative to flash image) */
-#define ERRCHK_START_ADDR  0x0
-#define ERRCHK_END_ADDR    0x0
+#define ERRCHK_START_ADDR 0x0
+#define ERRCHK_END_ADDR 0x0
 
 /* Firmware Size -> Booter loads RO region after hard reset (16 bytes aligned)*/
-#define FW_SIZE            CONFIG_RO_SIZE
+#define FW_SIZE CONFIG_RO_SIZE
 
 /* FW Header used by NPCX5M5G Booter */
 struct __packed fw_header_t {
-	uint32_t anchor;         /* A constant used to verify FW header       */
-	uint16_t ext_anchor;     /* Enable/disable firmware header CRC check  */
-	uint8_t  spi_max_freq;   /* Spi maximum allowable clock frequency     */
-	uint8_t  spi_read_mode;  /* Spi read mode used for firmware loading   */
-	uint8_t  cfg_err_detect; /* FW load error detection configuration     */
-	uint32_t fw_load_addr;   /* Firmware load start address               */
-	uint32_t fw_entry;       /* Firmware entry point                      */
+	uint32_t anchor; /* A constant used to verify FW header       */
+	uint16_t ext_anchor; /* Enable/disable firmware header CRC check  */
+	uint8_t spi_max_freq; /* Spi maximum allowable clock frequency     */
+	uint8_t spi_read_mode; /* Spi read mode used for firmware loading   */
+	uint8_t cfg_err_detect; /* FW load error detection configuration     */
+	uint32_t fw_load_addr; /* Firmware load start address               */
+	uint32_t fw_entry; /* Firmware entry point                      */
 	uint32_t err_detect_start_addr; /* FW error detect start address      */
-	uint32_t err_detect_end_addr;   /* FW error detect end address        */
-	uint32_t fw_length;      /* Firmware length in bytes                  */
-	uint8_t  flash_size;     /* Indicate SPI flash size                   */
-	uint8_t  reserved[26];   /* Reserved bytes                            */
-	uint32_t sig_header;     /* The CRC signature of the firmware header  */
-	uint32_t sig_fw_image;   /* The CRC or Checksum of the firmware image */
+	uint32_t err_detect_end_addr; /* FW error detect end address        */
+	uint32_t fw_length; /* Firmware length in bytes                  */
+	uint8_t flash_size; /* Indicate SPI flash size                   */
+	uint8_t reserved[26]; /* Reserved bytes                            */
+	uint32_t sig_header; /* The CRC signature of the firmware header  */
+	uint32_t sig_fw_image; /* The CRC or Checksum of the firmware image */
 } __aligned(1);
 
-__keep  __attribute__ ((section(".header")))
+__keep __attribute__((section(".header")))
 const struct fw_header_t fw_header = {
 	/* 00 */ SIG_FW_EC,
 	/* 04 */ 0x54E1, /* Header CRC check Enable/Disable -> AB1Eh/54E1h    */
-	/* 06 */ 0x04,   /* 20/25/33/40/50 MHz -> 00/01/02/03/04h             */
-	/* 07 */ 0x03,   /* Normal/Fast/Rev/D_IO/Q_IO Mode -> 00/01/02/03/04h */
-	/* 08 */ 0x00,   /* Disable CRC check functionality */
+	/* 06 */ 0x04, /* 20/25/33/40/50 MHz -> 00/01/02/03/04h             */
+	/* 07 */ 0x03, /* Normal/Fast/Rev/D_IO/Q_IO Mode -> 00/01/02/03/04h */
+	/* 08 */ 0x00, /* Disable CRC check functionality */
 	/* 09 */ FW_START_ADDR,
-	/* 0D */ FW_ENTRY_ADDR,/* Filling by ECST tool with -usearmrst option */
+	/* 0D */ FW_ENTRY_ADDR, /* Filling by ECST tool with -usearmrst option
+				 */
 	/* 11 */ ERRCHK_START_ADDR,
 	/* 15 */ ERRCHK_END_ADDR,
-	/* 19 */ FW_SIZE,/* Filling by ECST tool */
-	/* 1D */ 0x0F,   /* Flash Size 1/2/4/8/16 Mbytes -> 01/03/07/0F/1Fh   */
+	/* 19 */ FW_SIZE, /* Filling by ECST tool */
+	/* 1D */ 0x0F, /* Flash Size 1/2/4/8/16 Mbytes -> 01/03/07/0F/1Fh   */
 	/* 1E-3F Other fields are filled by ECST tool or reserved         */
 };
diff --git a/chip/npcx/hwtimer.c b/chip/npcx/hwtimer.c
index 92f9843d09..e2e2fe4b19 100644
--- a/chip/npcx/hwtimer.c
+++ b/chip/npcx/hwtimer.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,21 +8,21 @@
 #include "clock.h"
 #include "clock_chip.h"
 #include "common.h"
+#include "console.h"
 #include "hooks.h"
 #include "hwtimer.h"
 #include "hwtimer_chip.h"
 #include "math_util.h"
 #include "registers.h"
-#include "console.h"
 #include "task.h"
 #include "timer.h"
 #include "util.h"
 
 /* Depth of event timer */
-#define TICK_EVT_DEPTH         16 /* Depth of event timer Unit: bits */
-#define TICK_EVT_INTERVAL      BIT(TICK_EVT_DEPTH) /* Unit: us */
+#define TICK_EVT_DEPTH 16 /* Depth of event timer Unit: bits */
+#define TICK_EVT_INTERVAL BIT(TICK_EVT_DEPTH) /* Unit: us */
 #define TICK_EVT_INTERVAL_MASK (TICK_EVT_INTERVAL - 1) /* Mask of interval */
-#define TICK_EVT_MAX_CNT     (TICK_EVT_INTERVAL - 1) /* Maximum event counter */
+#define TICK_EVT_MAX_CNT (TICK_EVT_INTERVAL - 1) /* Maximum event counter */
 
 /* Time when event will be expired unit:us */
 static volatile uint32_t evt_expired_us;
@@ -39,7 +39,7 @@ static volatile uint32_t cur_cnt_us_dbg;
 #define CPRINTS(...)
 #else
 #define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args)
 #endif
 
 /*****************************************************************************/
@@ -48,7 +48,7 @@ void init_hw_timer(int itim_no, enum ITIM_SOURCE_CLOCK_T source)
 {
 	/* Select which clock to use for this timer */
 	UPDATE_BIT(NPCX_ITCTS(itim_no), NPCX_ITCTS_CKSEL,
-			source != ITIM_SOURCE_CLOCK_APB2);
+		   source != ITIM_SOURCE_CLOCK_APB2);
 
 	/* Clear timeout status */
 	SET_BIT(NPCX_ITCTS(itim_no), NPCX_ITCTS_TO_STS);
@@ -64,8 +64,8 @@ void init_hw_timer(int itim_no, enum ITIM_SOURCE_CLOCK_T source)
 /* HWTimer event handlers */
 void __hw_clock_event_set(uint32_t deadline)
 {
-	fp_t inv_evt_tick = FLOAT_TO_FP(INT_32K_CLOCK/(float)SECOND);
-	int32_t  evt_cnt_us;
+	fp_t inv_evt_tick = FLOAT_TO_FP(INT_32K_CLOCK / (float)SECOND);
+	int32_t evt_cnt_us;
 	/* Is deadline min value? */
 	if (evt_expired_us != 0 && evt_expired_us < deadline)
 		return;
@@ -87,10 +87,10 @@ void __hw_clock_event_set(uint32_t deadline)
 	 * ITIM count down : event expired : Unit: 1/32768 sec
 	 * It must exceed evt_expired_us for process_timers function
 	 */
-	evt_cnt = FP_TO_INT((fp_inter_t)(evt_cnt_us) * inv_evt_tick);
+	evt_cnt = FP_TO_INT((fp_inter_t)(evt_cnt_us)*inv_evt_tick);
 	if (evt_cnt > TICK_EVT_MAX_CNT) {
-		CPRINTS("Event overflow! 0x%08x, us is %d",
-				evt_cnt, evt_cnt_us);
+		CPRINTS("Event overflow! 0x%08x, us is %d", evt_cnt,
+			evt_cnt_us);
 		evt_cnt = TICK_EVT_MAX_CNT;
 	}
 
@@ -136,16 +136,17 @@ uint16_t __hw_clock_event_count(void)
 /* Returns time delay cause of deep idle */
 uint32_t __hw_clock_get_sleep_time(uint16_t pre_evt_cnt)
 {
-	fp_t evt_tick = FLOAT_TO_FP(SECOND/(float)INT_32K_CLOCK);
+	fp_t evt_tick = FLOAT_TO_FP(SECOND / (float)INT_32K_CLOCK);
 	uint32_t sleep_time;
 	uint16_t cnt = __hw_clock_event_count();
 
 	/* Event has been triggered but timer ISR doesn't handle it */
 	if (IS_BIT_SET(NPCX_ITCTS(ITIM_EVENT_NO), NPCX_ITCTS_TO_STS))
-		sleep_time = FP_TO_INT((fp_inter_t)(pre_evt_cnt+1) * evt_tick);
+		sleep_time =
+			FP_TO_INT((fp_inter_t)(pre_evt_cnt + 1) * evt_tick);
 	/* Event hasn't been triggered */
 	else
-		sleep_time = FP_TO_INT((fp_inter_t)(pre_evt_cnt+1 - cnt) *
+		sleep_time = FP_TO_INT((fp_inter_t)(pre_evt_cnt + 1 - cnt) *
 				       evt_tick);
 
 	return sleep_time;
@@ -166,7 +167,7 @@ void __hw_clock_event_clear(void)
 }
 
 /* Irq for hwtimer event */
-void __hw_clock_event_irq(void)
+static void __hw_clock_event_irq(void)
 {
 	/* ITIM event module disable */
 	CLEAR_BIT(NPCX_ITCTS(ITIM_EVENT_NO), NPCX_ITCTS_ITEN);
@@ -194,7 +195,6 @@ void __hw_clock_event_irq(void)
 	if (evt_expired_us == 0)
 		__hw_clock_event_set(EVT_MAX_EXPIRED_US);
 #endif
-
 }
 DECLARE_IRQ(ITIM_INT(ITIM_EVENT_NO), __hw_clock_event_irq, 3);
 
@@ -246,7 +246,7 @@ void __hw_clock_source_set(uint32_t ts)
 }
 
 /* Irq for hwtimer tick */
-void __hw_clock_source_irq(void)
+static void __hw_clock_source_irq(void)
 {
 	/* Is timeout trigger trigger? */
 	if (IS_BIT_SET(NPCX_ITCTS(ITIM_SYSTEM_NO), NPCX_ITCTS_TO_STS)) {
@@ -295,10 +295,9 @@ static void update_prescaler(void)
 	 * Ttick_unit = (PRE_8+1) * Tapb2_clk
 	 * PRE_8 = (Ttick_unit/Tapb2_clk) -1
 	 */
-	NPCX_ITPRE(ITIM_SYSTEM_NO)  = (clock_get_apb2_freq() / SECOND) - 1;
+	NPCX_ITPRE(ITIM_SYSTEM_NO) = (clock_get_apb2_freq() / SECOND) - 1;
 	/* Set event tick unit = 1/32768 sec */
 	NPCX_ITPRE(ITIM_EVENT_NO) = 0;
-
 }
 DECLARE_HOOK(HOOK_FREQ_CHANGE, update_prescaler, HOOK_PRIO_DEFAULT);
 
@@ -311,10 +310,10 @@ void __hw_early_init_hwtimer(uint32_t start_t)
 
 	/* Enable clock for ITIM peripheral */
 	clock_enable_peripheral(CGC_OFFSET_TIMER, CGC_TIMER_MASK,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
+				CGC_MODE_RUN | CGC_MODE_SLEEP);
 
 	/* init tick & event timer first */
-	init_hw_timer(ITIM_SYSTEM_NO,  ITIM_SOURCE_CLOCK_APB2);
+	init_hw_timer(ITIM_SYSTEM_NO, ITIM_SOURCE_CLOCK_APB2);
 	init_hw_timer(ITIM_EVENT_NO, ITIM_SOURCE_CLOCK_32K);
 
 	/* Set initial prescaler */
diff --git a/chip/npcx/hwtimer_chip.h b/chip/npcx/hwtimer_chip.h
index 987f3b52bd..7964d9619b 100644
--- a/chip/npcx/hwtimer_chip.h
+++ b/chip/npcx/hwtimer_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,14 +9,14 @@
 #define __CROS_EC_HWTIMER_CHIP_H
 
 /* Use ITIM32 as main hardware timer */
-#define TICK_ITIM32_MAX_CNT  0xFFFFFFFF
+#define TICK_ITIM32_MAX_CNT 0xFFFFFFFF
 /* Maximum deadline of event */
-#define EVT_MAX_EXPIRED_US   TICK_ITIM32_MAX_CNT
+#define EVT_MAX_EXPIRED_US TICK_ITIM32_MAX_CNT
 
 /* Clock source for ITIM16 */
 enum ITIM_SOURCE_CLOCK_T {
 	ITIM_SOURCE_CLOCK_APB2 = 0,
-	ITIM_SOURCE_CLOCK_32K  = 1,
+	ITIM_SOURCE_CLOCK_32K = 1,
 };
 
 /**
diff --git a/chip/npcx/i2c-npcx5.c b/chip/npcx/i2c-npcx5.c
index 6b78fd53f9..ef04b447c6 100644
--- a/chip/npcx/i2c-npcx5.c
+++ b/chip/npcx/i2c-npcx5.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -32,7 +32,7 @@ void i2c_select_port(int port)
 
 	/* Select IO pins for multi-ports I2C controllers */
 	UPDATE_BIT(NPCX_GLUE_SMBSEL, NPCX_SMBSEL_SMB0SEL,
-			(port == NPCX_I2C_PORT0_1));
+		   (port == NPCX_I2C_PORT0_1));
 }
 
 int i2c_is_raw_mode(int port)
@@ -44,4 +44,3 @@ int i2c_is_raw_mode(int port)
 	else
 		return 1;
 }
-
diff --git a/chip/npcx/i2c-npcx7.c b/chip/npcx/i2c-npcx7.c
index 3f27aff49e..427b9cae9f 100644
--- a/chip/npcx/i2c-npcx7.c
+++ b/chip/npcx/i2c-npcx7.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -37,13 +37,13 @@ void i2c_select_port(int port)
 	/* Select I2C ports for the same controller */
 	else if (port <= NPCX_I2C_PORT4_1) {
 		UPDATE_BIT(NPCX_GLUE_SMBSEL, NPCX_SMBSEL_SMB4SEL,
-			(port == NPCX_I2C_PORT4_1));
+			   (port == NPCX_I2C_PORT4_1));
 	} else if (port <= NPCX_I2C_PORT5_1) {
 		UPDATE_BIT(NPCX_GLUE_SMBSEL, NPCX_SMBSEL_SMB5SEL,
-			(port == NPCX_I2C_PORT5_1));
+			   (port == NPCX_I2C_PORT5_1));
 	} else {
 		UPDATE_BIT(NPCX_GLUE_SMBSEL, NPCX_SMBSEL_SMB6SEL,
-			(port == NPCX_I2C_PORT6_1));
+			   (port == NPCX_I2C_PORT6_1));
 	}
 }
 
@@ -52,7 +52,7 @@ int i2c_is_raw_mode(int port)
 	int group, bit;
 
 	if (port == NPCX_I2C_PORT4_1 || port == NPCX_I2C_PORT5_1 ||
-			port == NPCX_I2C_PORT6_1) {
+	    port == NPCX_I2C_PORT6_1) {
 		group = 6;
 		bit = 7 - (port - NPCX_I2C_PORT4_1) / 2;
 	} else {
diff --git a/chip/npcx/i2c-npcx9.c b/chip/npcx/i2c-npcx9.c
deleted file mode 120000
index b1b16a3198..0000000000
--- a/chip/npcx/i2c-npcx9.c
+++ /dev/null
@@ -1 +0,0 @@
-i2c-npcx7.c
\ No newline at end of file
diff --git a/chip/npcx/i2c-npcx9.c b/chip/npcx/i2c-npcx9.c
new file mode 100644
index 0000000000..427b9cae9f
--- /dev/null
+++ b/chip/npcx/i2c-npcx9.c
@@ -0,0 +1,70 @@
+/* Copyright 2017 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* I2C module driver depends on chip series for Chrome EC */
+
+#include "common.h"
+#include "i2c.h"
+#include "i2c_chip.h"
+#include "registers.h"
+#include "util.h"
+
+/*****************************************************************************/
+/* IC specific low-level driver depends on chip series */
+
+int i2c_port_to_controller(int port)
+{
+	if (port < 0 || port >= I2C_PORT_COUNT)
+		return -1;
+
+	if (port <= NPCX_I2C_PORT3_0)
+		return port;
+#ifndef NPCX_PSL_MODE_SUPPORT
+	else if (port == NPCX_I2C_PORT4_0)
+		return 4;
+#endif
+	else /* If port >= NPCX_I2C_PORT4_1 */
+		return 4 + ((port - NPCX_I2C_PORT4_1 + 1) / 2);
+}
+
+void i2c_select_port(int port)
+{
+	/* Only I2C 4/5/6 have multiple ports in series npcx7 */
+	if (port <= NPCX_I2C_PORT3_0 || port >= NPCX_I2C_PORT7_0)
+		return;
+	/* Select I2C ports for the same controller */
+	else if (port <= NPCX_I2C_PORT4_1) {
+		UPDATE_BIT(NPCX_GLUE_SMBSEL, NPCX_SMBSEL_SMB4SEL,
+			   (port == NPCX_I2C_PORT4_1));
+	} else if (port <= NPCX_I2C_PORT5_1) {
+		UPDATE_BIT(NPCX_GLUE_SMBSEL, NPCX_SMBSEL_SMB5SEL,
+			   (port == NPCX_I2C_PORT5_1));
+	} else {
+		UPDATE_BIT(NPCX_GLUE_SMBSEL, NPCX_SMBSEL_SMB6SEL,
+			   (port == NPCX_I2C_PORT6_1));
+	}
+}
+
+int i2c_is_raw_mode(int port)
+{
+	int group, bit;
+
+	if (port == NPCX_I2C_PORT4_1 || port == NPCX_I2C_PORT5_1 ||
+	    port == NPCX_I2C_PORT6_1) {
+		group = 6;
+		bit = 7 - (port - NPCX_I2C_PORT4_1) / 2;
+	} else {
+		group = 2;
+		if (port <= NPCX_I2C_PORT3_0)
+			bit = 2 * port;
+		else
+			bit = I2C_PORT_COUNT - port;
+	}
+
+	if (IS_BIT_SET(NPCX_DEVALT(group), bit))
+		return 0;
+	else
+		return 1;
+}
diff --git a/chip/npcx/i2c.c b/chip/npcx/i2c.c
index 9d72c80c71..ebfba26c58 100644
--- a/chip/npcx/i2c.c
+++ b/chip/npcx/i2c.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,14 +24,14 @@
 #define CPRINTF(...)
 #else
 #define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args)
 #endif
 
 /* Timeout for device should be available after reset (SMBus spec. unit:ms) */
 #define I2C_MAX_TIMEOUT 35
 /*
- * Timeout for SCL held to low by slave device . (SMBus spec. unit:ms).
+ * Timeout for SCL held to low by peripheral device. (SMBus spec. unit:ms).
  * Some I2C devices may violate this timing and clock stretch for longer.
  * TODO: Consider increasing this timeout.
  */
@@ -41,53 +41,54 @@
  * I2C module that supports FIFO mode has 32 bytes Tx FIFO and
  * 32 bytes Rx FIFO.
  */
-#define NPCX_I2C_FIFO_MAX_SIZE    32
+#define NPCX_I2C_FIFO_MAX_SIZE 32
 
 /* Macro functions of I2C */
 #define I2C_START(ctrl) SET_BIT(NPCX_SMBCTL1(ctrl), NPCX_SMBCTL1_START)
-#define I2C_STOP(ctrl)  SET_BIT(NPCX_SMBCTL1(ctrl), NPCX_SMBCTL1_STOP)
-#define I2C_NACK(ctrl)  SET_BIT(NPCX_SMBCTL1(ctrl), NPCX_SMBCTL1_ACK)
-/* I2C moudule automatically stall bus after sending slave address */
+#define I2C_STOP(ctrl) SET_BIT(NPCX_SMBCTL1(ctrl), NPCX_SMBCTL1_STOP)
+#define I2C_NACK(ctrl) SET_BIT(NPCX_SMBCTL1(ctrl), NPCX_SMBCTL1_ACK)
+/* I2C module automatically stall bus after sending peripheral address */
 #define I2C_STALL(ctrl) SET_BIT(NPCX_SMBCTL1(ctrl), NPCX_SMBCTL1_STASTRE)
 #define I2C_WRITE_BYTE(ctrl, data) (NPCX_SMBSDA(ctrl) = data)
-#define I2C_READ_BYTE(ctrl, data)  (data = NPCX_SMBSDA(ctrl))
+#define I2C_READ_BYTE(ctrl, data) (data = NPCX_SMBSDA(ctrl))
 #define I2C_TX_FIFO_OCCUPIED(ctrl) (NPCX_SMBTXF_STS(ctrl) & 0x3F)
 #define I2C_TX_FIFO_AVAILABLE(ctrl) \
-		(NPCX_I2C_FIFO_MAX_SIZE - I2C_TX_FIFO_OCCUPIED(ctrl))
+	(NPCX_I2C_FIFO_MAX_SIZE - I2C_TX_FIFO_OCCUPIED(ctrl))
 
 #define I2C_RX_FIFO_OCCUPIED(ctrl) (NPCX_SMBRXF_STS(ctrl) & 0x3F)
 #define I2C_RX_FIFO_AVAILABLE(ctrl) \
-			(NPCX_I2C_FIFO_MAX_SIZE - I2C_RX_FIFO_OCCUPIED(ctrl))
+	(NPCX_I2C_FIFO_MAX_SIZE - I2C_RX_FIFO_OCCUPIED(ctrl))
 /* Drive the SCL signal to low */
-#define I2C_SCL_STALL(ctrl) \
-		(NPCX_SMBCTL3(ctrl) = \
-			(NPCX_SMBCTL3(ctrl) & ~BIT(NPCX_SMBCTL3_SCL_LVL)) | \
-			 BIT(NPCX_SMBCTL3_SDA_LVL))
+#define I2C_SCL_STALL(ctrl)                                          \
+	(NPCX_SMBCTL3(ctrl) =                                        \
+		 (NPCX_SMBCTL3(ctrl) & ~BIT(NPCX_SMBCTL3_SCL_LVL)) | \
+		 BIT(NPCX_SMBCTL3_SDA_LVL))
 /*
  * Release the SCL signal to be pulled up to high level.
  * Note: The SCL might be still driven low either by I2C module or external
  * devices connected to ths bus.
  */
-#define I2C_SCL_FREE(ctrl) \
-		(NPCX_SMBCTL3(ctrl) |= BIT(NPCX_SMBCTL3_SCL_LVL) | \
-			 BIT(NPCX_SMBCTL3_SDA_LVL))
+#define I2C_SCL_FREE(ctrl)                                 \
+	(NPCX_SMBCTL3(ctrl) |= BIT(NPCX_SMBCTL3_SCL_LVL) | \
+			       BIT(NPCX_SMBCTL3_SDA_LVL))
 
 /* Error values that functions can return */
 enum smb_error {
-	SMB_OK = 0,                 /* No error                            */
-	SMB_CH_OCCUPIED,            /* Channel is already occupied         */
-	SMB_MEM_POOL_INIT_ERROR,    /* Memory pool initialization error    */
-	SMB_BUS_FREQ_ERROR,         /* SMbus freq was not valid            */
-	SMB_INVLAID_REGVALUE,       /* Invalid SMbus register value        */
-	SMB_UNEXIST_CH_ERROR,       /* Channel does not exist              */
-	SMB_NO_SUPPORT_PTL,         /* Not support SMBus Protocol          */
-	SMB_BUS_ERROR,              /* Encounter bus error                 */
-	SMB_MASTER_NO_ADDRESS_MATCH,/* No slave address match (Master Mode)*/
-	SMB_READ_DATA_ERROR,        /* Read data for SDA error             */
-	SMB_READ_OVERFLOW_ERROR,    /* Read data over than we predict      */
-	SMB_TIMEOUT_ERROR,          /* Timeout expired                     */
-	SMB_MODULE_ISBUSY,          /* Module is occupied by other device  */
-	SMB_BUS_BUSY,               /* SMBus is occupied by other device   */
+	SMB_OK = 0, /* No error                           */
+	SMB_CH_OCCUPIED, /* Channel is already occupied        */
+	SMB_MEM_POOL_INIT_ERROR, /* Memory pool initialization error   */
+	SMB_BUS_FREQ_ERROR, /* SMbus freq was not valid           */
+	SMB_INVLAID_REGVALUE, /* Invalid SMbus register value       */
+	SMB_UNEXIST_CH_ERROR, /* Channel does not exist             */
+	SMB_NO_SUPPORT_PTL, /* Not support SMBus Protocol         */
+	SMB_BUS_ERROR, /* Encounter bus error                */
+	SMB_NO_ADDRESS_MATCH, /* No peripheral address match        */
+	/*  (Controller Mode)                 */
+	SMB_READ_DATA_ERROR, /* Read data for SDA error            */
+	SMB_READ_OVERFLOW_ERROR, /* Read data over than we predict     */
+	SMB_TIMEOUT_ERROR, /* Timeout expired                    */
+	SMB_MODULE_ISBUSY, /* Module is occupied by other device */
+	SMB_BUS_BUSY, /* SMBus is occupied by other device  */
 };
 
 /*
@@ -96,7 +97,7 @@ enum smb_error {
  */
 enum smb_oper_state_t {
 	SMB_IDLE,
-	SMB_MASTER_START,
+	SMB_CONTROLLER_START,
 	SMB_WRITE_OPER,
 	SMB_READ_OPER,
 	SMB_FAKE_READ_OPER,
@@ -107,17 +108,18 @@ enum smb_oper_state_t {
 
 /* I2C controller state data */
 struct i2c_status {
-	int                   flags;     /* Flags (I2C_XFER_*) */
-	const uint8_t        *tx_buf;    /* Entry pointer of transmit buffer */
-	uint8_t              *rx_buf;    /* Entry pointer of receive buffer  */
-	uint16_t              sz_txbuf;  /* Size of Tx buffer in bytes */
-	uint16_t              sz_rxbuf;  /* Size of rx buffer in bytes */
-	uint16_t              idx_buf;   /* Current index of Tx/Rx buffer */
-	uint16_t              slave_addr_flags;/* Target slave address */
-	enum smb_oper_state_t oper_state;/* Smbus operation state */
-	enum smb_error        err_code;  /* Error code */
-	int                   task_waiting; /* Task waiting on controller */
-	uint32_t              timeout_us;/* Transaction timeout */
+	int flags; /* Flags (I2C_XFER_*) */
+	const uint8_t *tx_buf; /* Entry pointer of transmit buffer */
+	uint8_t *rx_buf; /* Entry pointer of receive buffer  */
+	uint16_t sz_txbuf; /* Size of Tx buffer in bytes */
+	uint16_t sz_rxbuf; /* Size of rx buffer in bytes */
+	uint16_t idx_buf; /* Current index of Tx/Rx buffer */
+	uint16_t addr_flags; /* Target address */
+	enum smb_oper_state_t oper_state; /* Smbus operation state */
+	enum smb_error err_code; /* Error code */
+	int task_waiting; /* Task waiting on controller */
+	uint32_t timeout_us; /* Transaction timeout */
+	uint16_t kbps; /* Speed */
 };
 /* I2C controller state data array */
 static struct i2c_status i2c_stsobjs[I2C_CONTROLLER_COUNT];
@@ -125,27 +127,29 @@ static struct i2c_status i2c_stsobjs[I2C_CONTROLLER_COUNT];
 /* I2C timing setting */
 struct i2c_timing {
 	uint8_t clock; /* I2C source clock. (Unit: MHz)*/
-	uint8_t HLDT;  /* I2C hold-time. (Unit: clocks) */
-	uint8_t k1;    /* k1 = SCL low-time (Unit: clocks) */
-	uint8_t k2;    /* k2 = SCL high-time (Unit: clocks) */
+	uint8_t HLDT; /* I2C hold-time. (Unit: clocks) */
+	uint8_t k1; /* k1 = SCL low-time (Unit: clocks) */
+	uint8_t k2; /* k2 = SCL high-time (Unit: clocks) */
 };
 
 /* I2C timing setting array of 400K & 1M Hz */
 static const struct i2c_timing i2c_400k_timings[] = {
-	{20,  7, 32, 22},
-	{15,  7, 24, 18},};
+	{ 20, 7, 32, 22 },
+	{ 15, 7, 24, 18 },
+};
 const unsigned int i2c_400k_timing_used = ARRAY_SIZE(i2c_400k_timings);
 
 static const struct i2c_timing i2c_1m_timings[] = {
-	{20, 7, 16, 10},
-	{15, 7, 14, 10},};
+	{ 20, 7, 16, 10 },
+	{ 15, 7, 14, 10 },
+};
 const unsigned int i2c_1m_timing_used = ARRAY_SIZE(i2c_1m_timings);
 
 /* IRQ for each port */
 const uint32_t i2c_irqs[I2C_CONTROLLER_COUNT] = {
-		NPCX_IRQ_SMB1, NPCX_IRQ_SMB2, NPCX_IRQ_SMB3, NPCX_IRQ_SMB4,
+	NPCX_IRQ_SMB1, NPCX_IRQ_SMB2, NPCX_IRQ_SMB3, NPCX_IRQ_SMB4,
 #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-		NPCX_IRQ_SMB5, NPCX_IRQ_SMB6, NPCX_IRQ_SMB7, NPCX_IRQ_SMB8,
+	NPCX_IRQ_SMB5, NPCX_IRQ_SMB6, NPCX_IRQ_SMB7, NPCX_IRQ_SMB8,
 #endif
 };
 BUILD_ASSERT(ARRAY_SIZE(i2c_irqs) == I2C_CONTROLLER_COUNT);
@@ -196,8 +200,8 @@ static void i2c_abort_data(int controller)
 	SET_BIT(NPCX_SMBST(controller), NPCX_SMBST_NEGACK);
 
 	/* Wait till STOP condition is generated */
-	if (i2c_wait_stop_completed(controller, I2C_MAX_TIMEOUT)
-			!= EC_SUCCESS) {
+	if (i2c_wait_stop_completed(controller, I2C_MAX_TIMEOUT) !=
+	    EC_SUCCESS) {
 		cprintf(CC_I2C, "Abort i2c %02x fail!\n", controller);
 		/* Clear BB (BUS BUSY) bit */
 		SET_BIT(NPCX_SMBCST(controller), NPCX_SMBCST_BB);
@@ -211,13 +215,15 @@ static void i2c_abort_data(int controller)
 static int i2c_reset(int controller)
 {
 	uint16_t timeout = I2C_MAX_TIMEOUT;
+
 	/* Disable the SMB module */
 	CLEAR_BIT(NPCX_SMBCTL2(controller), NPCX_SMBCTL2_ENABLE);
 
 	while (--timeout) {
 		/* WAIT FOR SCL & SDA IS HIGH */
-		if (IS_BIT_SET(NPCX_SMBCTL3(controller), NPCX_SMBCTL3_SCL_LVL)
-		  && IS_BIT_SET(NPCX_SMBCTL3(controller), NPCX_SMBCTL3_SDA_LVL))
+		if (IS_BIT_SET(NPCX_SMBCTL3(controller),
+			       NPCX_SMBCTL3_SCL_LVL) &&
+		    IS_BIT_SET(NPCX_SMBCTL3(controller), NPCX_SMBCTL3_SDA_LVL))
 			break;
 		msleep(1);
 	}
@@ -303,14 +309,13 @@ static void i2c_fifo_write_data(int controller)
 	}
 	for (i = 0; i < len; i++) {
 		I2C_WRITE_BYTE(controller,
-				p_status->tx_buf[p_status->idx_buf++]);
-		CPRINTF("%02x ",
-				p_status->tx_buf[p_status->idx_buf - 1]);
+			       p_status->tx_buf[p_status->idx_buf++]);
+		CPRINTF("%02x ", p_status->tx_buf[p_status->idx_buf - 1]);
 	}
 	CPRINTF("\n");
 }
 
-enum smb_error i2c_master_transaction(int controller)
+enum smb_error i2c_controller_transaction(int controller)
 {
 	/* Set i2c mode to object */
 	int events = 0;
@@ -323,7 +328,7 @@ enum smb_error i2c_master_transaction(int controller)
 	/* Assign current SMB status of controller */
 	if (p_status->oper_state == SMB_IDLE) {
 		/* New transaction */
-		p_status->oper_state = SMB_MASTER_START;
+		p_status->oper_state = SMB_CONTROLLER_START;
 		/* Clear FIFO and status bit */
 		if (IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) {
 			NPCX_SMBFIF_CTS(controller) =
@@ -352,13 +357,13 @@ enum smb_error i2c_master_transaction(int controller)
 			 * is set simultaneously.
 			 */
 			if (p_status->sz_rxbuf == 1 &&
-					(p_status->flags & I2C_XFER_STOP)) {
+			    (p_status->flags & I2C_XFER_STOP)) {
 				/*
 				 * Since SCL is released after reading last
 				 * byte from previous transaction, adding a
 				 * extra byte for next transaction which let
 				 * ec sets NACK bit in time is necessary.
-				 * Or i2c master cannot generate STOP
+				 * Or i2c controller cannot generate STOP
 				 * when the last byte is ACK during receiving.
 				 */
 				p_status->sz_rxbuf++;
@@ -372,30 +377,30 @@ enum smb_error i2c_master_transaction(int controller)
 		}
 	} else
 		cprintf(CC_I2C, "Unexpected i2c state machine! %d\n",
-				p_status->oper_state);
+			p_status->oper_state);
 
 	if (IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) {
 		if (p_status->sz_rxbuf > 0) {
 			if (p_status->sz_rxbuf > NPCX_I2C_FIFO_MAX_SIZE) {
 				/* Set RX threshold = FIFO_MAX_SIZE */
 				SET_FIELD(NPCX_SMBRXF_CTL(controller),
-						NPCX_SMBRXF_CTL_RX_THR,
-						NPCX_I2C_FIFO_MAX_SIZE);
+					  NPCX_SMBRXF_CTL_RX_THR,
+					  NPCX_I2C_FIFO_MAX_SIZE);
 			} else {
 				/*
 				 * set RX threshold = remaining data bytes
 				 * (it should be <= FIFO_MAX_SIZE)
 				 */
 				SET_FIELD(NPCX_SMBRXF_CTL(controller),
-						NPCX_SMBRXF_CTL_RX_THR,
-						p_status->sz_rxbuf);
+					  NPCX_SMBRXF_CTL_RX_THR,
+					  p_status->sz_rxbuf);
 				/*
 				 * Set LAST bit generate the NACK at the
 				 * last byte of the data group in FIFO
 				 */
 				if (p_status->flags & I2C_XFER_STOP) {
 					SET_BIT(NPCX_SMBRXF_CTL(controller),
-							NPCX_SMBRXF_CTL_LAST);
+						NPCX_SMBRXF_CTL_LAST);
 				}
 			}
 
@@ -408,8 +413,8 @@ enum smb_error i2c_master_transaction(int controller)
 	}
 
 	/* Generate a START condition */
-	if (p_status->oper_state == SMB_MASTER_START ||
-			p_status->oper_state == SMB_REPEAT_START) {
+	if (p_status->oper_state == SMB_CONTROLLER_START ||
+	    p_status->oper_state == SMB_REPEAT_START) {
 		I2C_START(controller);
 		CPUTS("ST");
 	}
@@ -418,8 +423,8 @@ enum smb_error i2c_master_transaction(int controller)
 	task_enable_irq(i2c_irqs[controller]);
 
 	/* Wait for transfer complete or timeout */
-	events = task_wait_event_mask(TASK_EVENT_I2C_IDLE,
-			p_status->timeout_us);
+	events =
+		task_wait_event_mask(TASK_EVENT_I2C_IDLE, p_status->timeout_us);
 
 	/* Disable event and error interrupts */
 	task_disable_irq(i2c_irqs[controller]);
@@ -449,8 +454,9 @@ enum smb_error i2c_master_transaction(int controller)
 		i2c_recovery(controller, p_status);
 
 	/* Wait till STOP condition is generated for normal transaction */
-	if (p_status->err_code == SMB_OK && i2c_wait_stop_completed(controller,
-			I2C_MIN_TIMEOUT) != EC_SUCCESS) {
+	if (p_status->err_code == SMB_OK &&
+	    i2c_wait_stop_completed(controller, I2C_MIN_TIMEOUT) !=
+		    EC_SUCCESS) {
 		cprintf(CC_I2C,
 			"STOP fail! scl %02x is held by slave device!\n",
 			controller);
@@ -473,7 +479,7 @@ void i2c_done(int controller)
 		/* Clear RXF_TXE bit (RX FIFO full/TX FIFO empty) */
 		if (IS_ENABLED(NPCX_I2C_FIFO_SUPPORT))
 			NPCX_SMBFIF_CTS(controller) =
-						BIT(NPCX_SMBFIF_CTS_RXF_TXE);
+				BIT(NPCX_SMBFIF_CTS_RXF_TXE);
 
 		/* Clear SDAST by writing mock byte */
 		I2C_WRITE_BYTE(controller, 0xFF);
@@ -482,10 +488,11 @@ void i2c_done(int controller)
 	/* Set error code */
 	p_status->err_code = SMB_OK;
 	/* Set SMB status if we need stall bus */
-	p_status->oper_state = (p_status->flags & I2C_XFER_STOP)
-				? SMB_IDLE : SMB_WRITE_SUSPEND;
+	p_status->oper_state = (p_status->flags & I2C_XFER_STOP) ?
+				       SMB_IDLE :
+				       SMB_WRITE_SUSPEND;
 	/*
-	 * Disable interrupt for i2c master stall SCL
+	 * Disable interrupt for i2c controller stall SCL
 	 * and forbid SDAST generate interrupt
 	 * until common layer start other transactions
 	 */
@@ -493,8 +500,7 @@ void i2c_done(int controller)
 		task_disable_irq(i2c_irqs[controller]);
 
 	/* Notify upper layer */
-	task_set_event(p_status->task_waiting,
-		       TASK_EVENT_I2C_IDLE, 0);
+	task_set_event(p_status->task_waiting, TASK_EVENT_I2C_IDLE);
 	CPUTS("-END");
 }
 
@@ -512,7 +518,7 @@ static void i2c_handle_receive(int controller)
 			CPUTS("-SP");
 		} else {
 			/*
-			 * Disable interrupt before i2c master read SDA
+			 * Disable interrupt before i2c controller read SDA
 			 * reg (stall SCL) and forbid SDAST generate
 			 * interrupt until starting other transactions
 			 */
@@ -538,7 +544,7 @@ static void i2c_handle_receive(int controller)
 
 	/* Read to buf. Skip last byte if meet SMB_FAKE_READ_OPER */
 	if (p_status->oper_state == SMB_FAKE_READ_OPER &&
-			p_status->idx_buf == (p_status->sz_rxbuf - 1))
+	    p_status->idx_buf == (p_status->sz_rxbuf - 1))
 		p_status->idx_buf++;
 	else
 		p_status->rx_buf[p_status->idx_buf++] = data;
@@ -546,13 +552,13 @@ static void i2c_handle_receive(int controller)
 	/* last byte is read - end of transaction */
 	if (p_status->idx_buf == p_status->sz_rxbuf) {
 		/* Set current status */
-		p_status->oper_state = (p_status->flags & I2C_XFER_STOP)
-				? SMB_IDLE : SMB_READ_SUSPEND;
+		p_status->oper_state = (p_status->flags & I2C_XFER_STOP) ?
+					       SMB_IDLE :
+					       SMB_READ_SUSPEND;
 		/* Set error code */
 		p_status->err_code = SMB_OK;
 		/* Notify upper layer of missing data */
-		task_set_event(p_status->task_waiting,
-				TASK_EVENT_I2C_IDLE, 0);
+		task_set_event(p_status->task_waiting, TASK_EVENT_I2C_IDLE);
 		CPUTS("-END");
 	}
 }
@@ -622,53 +628,50 @@ static void i2c_fifo_handle_receive(int controller)
 		if (remaining_bytes > 0) {
 			if (remaining_bytes > NPCX_I2C_FIFO_MAX_SIZE) {
 				SET_FIELD(NPCX_SMBRXF_CTL(controller),
-						NPCX_SMBRXF_CTL_RX_THR,
-						NPCX_I2C_FIFO_MAX_SIZE);
+					  NPCX_SMBRXF_CTL_RX_THR,
+					  NPCX_I2C_FIFO_MAX_SIZE);
 			} else {
 				SET_FIELD(NPCX_SMBRXF_CTL(controller),
-						NPCX_SMBRXF_CTL_RX_THR,
-						remaining_bytes);
+					  NPCX_SMBRXF_CTL_RX_THR,
+					  remaining_bytes);
 				if (p_status->flags & I2C_XFER_STOP) {
 					SET_BIT(NPCX_SMBRXF_CTL(controller),
-							NPCX_SMBRXF_CTL_LAST);
+						NPCX_SMBRXF_CTL_LAST);
 					CPRINTS("-FGNA");
 				}
 			}
-
 		}
 		i2c_stall_bus(controller, 0);
-
 	}
 	/* last byte is read - end of transaction */
 	if (p_status->idx_buf == p_status->sz_rxbuf) {
 		/* Set current status */
-		p_status->oper_state = (p_status->flags & I2C_XFER_STOP)
-				? SMB_IDLE : SMB_READ_SUSPEND;
+		p_status->oper_state = (p_status->flags & I2C_XFER_STOP) ?
+					       SMB_IDLE :
+					       SMB_READ_SUSPEND;
 		/* Set error code */
 		p_status->err_code = SMB_OK;
 		/* Notify upper layer of missing data */
-		task_set_event(p_status->task_waiting,
-				TASK_EVENT_I2C_IDLE, 0);
+		task_set_event(p_status->task_waiting, TASK_EVENT_I2C_IDLE);
 		CPUTS("-END");
 	}
-
 }
 
 static void i2c_handle_sda_irq(int controller)
 {
 	volatile struct i2c_status *p_status = i2c_stsobjs + controller;
-	uint8_t addr_8bit = I2C_GET_ADDR(p_status->slave_addr_flags) << 1;
+	uint8_t addr_8bit = I2C_STRIP_FLAGS(p_status->addr_flags) << 1;
 
 	/* 1 Issue Start is successful ie. write address byte */
-	if (p_status->oper_state == SMB_MASTER_START
-			|| p_status->oper_state == SMB_REPEAT_START) {
+	if (p_status->oper_state == SMB_CONTROLLER_START ||
+	    p_status->oper_state == SMB_REPEAT_START) {
 		/* Prepare address byte */
-		if (p_status->sz_txbuf == 0) {/* Receive mode */
+		if (p_status->sz_txbuf == 0) { /* Receive mode */
 			p_status->oper_state = SMB_READ_OPER;
 			/*
-			 * Receiving one or zero bytes - stall bus after START
-			 * condition. If there's no slave devices on bus, FW
-			 * needn't to set ACK bit.
+			 * Receiving one or zero bytes - stall bus after
+			 * START condition. If there's no peripheral
+			 * devices on bus, FW needn't to set ACK bit.
 			 */
 			if (p_status->sz_rxbuf < 2)
 				I2C_STALL(controller);
@@ -676,7 +679,7 @@ static void i2c_handle_sda_irq(int controller)
 			/* Write the address to the bus R bit*/
 			I2C_WRITE_BYTE(controller, (addr_8bit | 0x1));
 			CPRINTS("-ARR-0x%02x", addr_8bit);
-		} else {/* Transmit mode */
+		} else { /* Transmit mode */
 			p_status->oper_state = SMB_WRITE_OPER;
 			/* Write the address to the bus W bit*/
 			I2C_WRITE_BYTE(controller, addr_8bit);
@@ -685,14 +688,17 @@ static void i2c_handle_sda_irq(int controller)
 		/* Completed handling START condition */
 		return;
 	}
-	/* 2 Handle master write operation  */
+	/* 2 Handle controller write operation */
 	else if (p_status->oper_state == SMB_WRITE_OPER) {
 		/* all bytes have been written, in a pure write operation */
 		if (p_status->idx_buf == p_status->sz_txbuf) {
 			/*  no more message */
 			if (p_status->sz_rxbuf == 0)
 				i2c_done(controller);
-			/* need to restart & send slave address immediately */
+			/*
+			 * need to restart & send peripheral address
+			 * immediately
+			 */
 			else {
 				/*
 				 * Prepare address byte
@@ -717,18 +723,20 @@ static void i2c_handle_sda_irq(int controller)
 				 * in the SMBnTXF_CTL register.
 				 */
 				if (p_status->sz_rxbuf == 1 &&
-					(p_status->flags & I2C_XFER_STOP) &&
-					!IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) {
+				    (p_status->flags & I2C_XFER_STOP) &&
+				    !IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) {
 					I2C_NACK(controller);
 					CPUTS("-GNA");
 				}
 				/* Write the address to the bus R bit*/
-				I2C_WRITE_BYTE(controller,
-					       (addr_8bit | 0x1));
+				I2C_WRITE_BYTE(controller, (addr_8bit | 0x1));
 				CPUTS("-ARR");
 			}
 		}
-		/* write next byte (not last byte and not slave address */
+		/*
+		 * write next byte (not last byte and not peripheral
+		 * address)
+		 */
 		else {
 			/*
 			 * This function can be called in either single-byte
@@ -738,9 +746,12 @@ static void i2c_handle_sda_irq(int controller)
 			i2c_fifo_write_data(controller);
 		}
 	}
-	/* 3 Handle master read operation (read or after a write operation) */
+	/*
+	 * 3 Handle controller read operation (read or after a write
+	 * operation)
+	 */
 	else if (p_status->oper_state == SMB_READ_OPER ||
-			p_status->oper_state == SMB_FAKE_READ_OPER) {
+		 p_status->oper_state == SMB_FAKE_READ_OPER) {
 		if (IS_ENABLED(NPCX_I2C_FIFO_SUPPORT))
 			i2c_fifo_handle_receive(controller);
 		else
@@ -748,7 +759,7 @@ static void i2c_handle_sda_irq(int controller)
 	}
 }
 
-void i2c_master_int_handler (int controller)
+static void i2c_controller_int_handler(int controller)
 {
 	volatile struct i2c_status *p_status = i2c_stsobjs + controller;
 
@@ -760,14 +771,14 @@ void i2c_master_int_handler (int controller)
 		CPUTS("-SP");
 		/* Clear BER Bit */
 		SET_BIT(NPCX_SMBST(controller), NPCX_SMBST_BER);
-		/* Make sure slave doesn't hold bus by reading */
+		/* Make sure peripheral doesn't hold bus by reading */
 		I2C_READ_BYTE(controller, data);
 
 		/* Set error code */
 		p_status->err_code = SMB_BUS_ERROR;
 		/* Notify upper layer */
 		p_status->oper_state = SMB_IDLE;
-		task_set_event(p_status->task_waiting, TASK_EVENT_I2C_IDLE, 0);
+		task_set_event(p_status->task_waiting, TASK_EVENT_I2C_IDLE);
 		CPUTS("-BER");
 
 		/*
@@ -788,10 +799,10 @@ void i2c_master_int_handler (int controller)
 		/* Clear NEGACK Bit */
 		SET_BIT(NPCX_SMBST(controller), NPCX_SMBST_NEGACK);
 		/* Set error code */
-		p_status->err_code = SMB_MASTER_NO_ADDRESS_MATCH;
+		p_status->err_code = SMB_NO_ADDRESS_MATCH;
 		/* Notify upper layer */
 		p_status->oper_state = SMB_IDLE;
-		task_set_event(p_status->task_waiting, TASK_EVENT_I2C_IDLE, 0);
+		task_set_event(p_status->task_waiting, TASK_EVENT_I2C_IDLE);
 		CPUTS("-NA");
 	}
 
@@ -817,7 +828,7 @@ void i2c_master_int_handler (int controller)
 		 * register.
 		 */
 		else if ((p_status->flags & I2C_XFER_STOP) &&
-				 !IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) {
+			 !IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) {
 			I2C_NACK(controller);
 		}
 
@@ -831,9 +842,10 @@ void i2c_master_int_handler (int controller)
 #if DEBUG_I2C
 		/* SDAST still issued with unexpected state machine */
 		if (IS_BIT_SET(NPCX_SMBST(controller), NPCX_SMBST_SDAST) &&
-				p_status->oper_state != SMB_WRITE_SUSPEND) {
+		    p_status->oper_state != SMB_WRITE_SUSPEND) {
 			cprints(CC_I2C, "i2c %d unknown state %d, error %d\n",
-			  controller, p_status->oper_state, p_status->err_code);
+				controller, p_status->oper_state,
+				p_status->err_code);
 		}
 #endif
 	}
@@ -846,18 +858,42 @@ void i2c_master_int_handler (int controller)
  */
 void handle_interrupt(int controller)
 {
-	i2c_master_int_handler(controller);
+	i2c_controller_int_handler(controller);
 }
 
-void i2c0_interrupt(void) { handle_interrupt(0); }
-void i2c1_interrupt(void) { handle_interrupt(1); }
-void i2c2_interrupt(void) { handle_interrupt(2); }
-void i2c3_interrupt(void) { handle_interrupt(3); }
+static void i2c0_interrupt(void)
+{
+	handle_interrupt(0);
+}
+static void i2c1_interrupt(void)
+{
+	handle_interrupt(1);
+}
+static void i2c2_interrupt(void)
+{
+	handle_interrupt(2);
+}
+static void i2c3_interrupt(void)
+{
+	handle_interrupt(3);
+}
 #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-void i2c4_interrupt(void) { handle_interrupt(4); }
-void i2c5_interrupt(void) { handle_interrupt(5); }
-void i2c6_interrupt(void) { handle_interrupt(6); }
-void i2c7_interrupt(void) { handle_interrupt(7); }
+static void i2c4_interrupt(void)
+{
+	handle_interrupt(4);
+}
+static void i2c5_interrupt(void)
+{
+	handle_interrupt(5);
+}
+static void i2c6_interrupt(void)
+{
+	handle_interrupt(6);
+}
+static void i2c7_interrupt(void)
+{
+	handle_interrupt(7);
+}
 #endif
 
 DECLARE_IRQ(NPCX_IRQ_SMB1, i2c0_interrupt, 4);
@@ -883,14 +919,12 @@ void i2c_set_timeout(int port, uint32_t timeout)
 		return;
 
 	/* Param is port, but timeout is stored by-controller. */
-	i2c_stsobjs[ctrl].timeout_us =
-		timeout ? timeout : I2C_TIMEOUT_DEFAULT_US;
+	i2c_stsobjs[ctrl].timeout_us = timeout ? timeout :
+						 I2C_TIMEOUT_DEFAULT_US;
 }
 
-int chip_i2c_xfer(const int port,
-		  const uint16_t slave_addr_flags,
-		  const uint8_t *out, int out_size,
-		  uint8_t *in, int in_size, int flags)
+int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out,
+		  int out_size, uint8_t *in, int in_size, int flags)
 {
 	volatile struct i2c_status *p_status;
 	int ctrl = i2c_port_to_controller(port);
@@ -912,23 +946,23 @@ int chip_i2c_xfer(const int port,
 	i2c_select_port(port);
 
 	/* Copy data to controller struct */
-	p_status->flags       = flags;
-	p_status->tx_buf      = out;
-	p_status->sz_txbuf    = out_size;
-	p_status->rx_buf      = in;
-	p_status->sz_rxbuf    = in_size;
-	p_status->slave_addr_flags = slave_addr_flags;
+	p_status->flags = flags;
+	p_status->tx_buf = out;
+	p_status->sz_txbuf = out_size;
+	p_status->rx_buf = in;
+	p_status->sz_rxbuf = in_size;
+	p_status->addr_flags = addr_flags;
 
 	/* Reset index & error */
-	p_status->idx_buf     = 0;
-	p_status->err_code    = SMB_OK;
+	p_status->idx_buf = 0;
+	p_status->err_code = SMB_OK;
 
 	/* Make sure we're in a good state to start */
 	if ((flags & I2C_XFER_START) &&
-	     /* Ignore busy bus for repeated start */
-	     p_status->oper_state != SMB_WRITE_SUSPEND &&
-	     (i2c_bus_busy(ctrl)
-	     || (i2c_get_line_levels(port) != I2C_LINE_IDLE))) {
+	    /* Ignore busy bus for repeated start */
+	    p_status->oper_state != SMB_WRITE_SUSPEND &&
+	    (i2c_bus_busy(ctrl) ||
+	     (i2c_get_line_levels(port) != I2C_LINE_IDLE))) {
 		int ret;
 
 		/* Attempt to unwedge the i2c port */
@@ -944,8 +978,8 @@ int chip_i2c_xfer(const int port,
 
 	CPUTS("\n");
 
-	/* Start master transaction */
-	i2c_master_transaction(ctrl);
+	/* Start controller transaction */
+	i2c_controller_transaction(ctrl);
 
 	/* Reset task ID */
 	p_status->task_waiting = TASK_ID_INVALID;
@@ -965,7 +999,7 @@ int chip_i2c_xfer(const int port,
 int i2c_get_line_levels(int port)
 {
 	return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) |
-		   (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
+	       (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
 }
 
 int i2c_raw_get_scl(int port)
@@ -980,8 +1014,9 @@ int i2c_raw_get_scl(int port)
 		if (i2c_is_raw_mode(port))
 			return gpio_get_level(g);
 		else
-			return IS_BIT_SET(NPCX_SMBCTL3(
-			i2c_port_to_controller(port)), NPCX_SMBCTL3_SCL_LVL);
+			return IS_BIT_SET(
+				NPCX_SMBCTL3(i2c_port_to_controller(port)),
+				NPCX_SMBCTL3_SCL_LVL);
 	}
 
 	/* If no SCL pin defined for this port, then return 1 to appear idle */
@@ -1000,102 +1035,175 @@ int i2c_raw_get_sda(int port)
 		if (i2c_is_raw_mode(port))
 			return gpio_get_level(g);
 		else
-			return IS_BIT_SET(NPCX_SMBCTL3(
-			i2c_port_to_controller(port)), NPCX_SMBCTL3_SDA_LVL);
+			return IS_BIT_SET(
+				NPCX_SMBCTL3(i2c_port_to_controller(port)),
+				NPCX_SMBCTL3_SDA_LVL);
 	}
 
-
 	/* If no SDA pin defined for this port, then return 1 to appear idle */
 	return 1;
 }
 
 /*****************************************************************************/
-/* Hooks */
-static void i2c_freq_changed(void)
-{
-	int freq, i, j;
 
-	for (i = 0; i < i2c_ports_used; i++) {
-		int bus_freq = i2c_ports[i].kbps;
-		int ctrl = i2c_port_to_controller(i2c_ports[i].port);
-		int scl_freq;
+static void i2c_port_set_freq(const int ctrl, const int bus_freq_kbps)
+{
+	int freq, j;
+	int scl_freq;
+	const struct i2c_timing *pTiming;
+	int i2c_timing_used;
 
 #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-		/*
-		 * SMB0/1/4/5/6/7 use APB3 clock
-		 * SMB2/3 use APB2 clock
-		 */
-		freq = (ctrl < 2 || ctrl > 3) ?
-		       clock_get_apb3_freq() : clock_get_apb2_freq();
+	/*
+	 * SMB0/1/4/5/6/7 use APB3 clock
+	 * SMB2/3 use APB2 clock
+	 */
+	freq = (ctrl < 2 || ctrl > 3) ? clock_get_apb3_freq() :
+					clock_get_apb2_freq();
 #else /* CHIP_FAMILY_NPCX5 */
-		/*
-		 * SMB0/1 use core clock
-		 * SMB2/3 use APB2 clock
-		 */
-		freq = (ctrl < 2) ? clock_get_freq() : clock_get_apb2_freq();
+	/*
+	 * SMB0/1 use core clock
+	 * SMB2/3 use APB2 clock
+	 */
+	freq = (ctrl < 2) ? clock_get_freq() : clock_get_apb2_freq();
 #endif
 
-		/*
-		 * Set SCL frequency by formula:
-		 * tSCL = 4 * SCLFRQ * tCLK
-		 * fSCL = fCLK / (4*SCLFRQ)
-		 * SCLFRQ = ceil(fCLK/(4*fSCL))
-		 */
-		scl_freq = DIV_ROUND_UP(freq, bus_freq*4000); /* Unit in bps */
-
-		/* Normal mode if i2c freq is under 100kHz */
-		if (bus_freq <= 100) {
-			/* Set divider value of SCL */
-			SET_FIELD(NPCX_SMBCTL2(ctrl), NPCX_SMBCTL2_SCLFRQ7_FIELD
-					, (scl_freq & 0x7F));
-			SET_FIELD(NPCX_SMBCTL3(ctrl), NPCX_SMBCTL3_SCLFRQ2_FIELD
-					, (scl_freq >> 7));
-		} else {
-			const struct i2c_timing *pTiming;
-			int i2c_timing_used;
+	if (bus_freq_kbps == i2c_stsobjs[ctrl].kbps)
+		return;
 
-			/* use Fast Mode */
-			SET_BIT(NPCX_SMBCTL3(ctrl), NPCX_SMBCTL3_400K);
-			/*
-			 * Set SCLH(L)T and hold-time directly for best i2c
-			 * timing condition for all source clocks. Please refer
-			 * Section 7.5.9 "SMBus Timing - Fast Mode" for detail.
-			 */
-			if (bus_freq == 400) {
-				pTiming = i2c_400k_timings;
-				i2c_timing_used = i2c_400k_timing_used;
-			} else if (bus_freq == 1000) {
-				pTiming = i2c_1m_timings;
-				i2c_timing_used = i2c_1m_timing_used;
-			} else {
-				/* Set value from formula */
-				NPCX_SMBSCLLT(ctrl) = scl_freq;
-				NPCX_SMBSCLHT(ctrl) = scl_freq;
-				cprints(CC_I2C,
-					"Warning: Use 400K or 1MHz for better timing of I2c %d",
-					ctrl);
-				continue;
-			}
+	/*
+	 * Set SCL frequency by formula:
+	 * tSCL = 4 * SCLFRQ * tCLK
+	 * fSCL = fCLK / (4*SCLFRQ)
+	 * SCLFRQ = ceil(fCLK/(4*fSCL))
+	 */
+	scl_freq = DIV_ROUND_UP(freq, bus_freq_kbps * 4000); /* Unit in bps */
+
+	/* Normal mode if I2C freq is under 100kHz */
+	if (bus_freq_kbps <= 100) {
+		i2c_stsobjs[ctrl].kbps = bus_freq_kbps;
+		/* Set divider value of SCL */
+		SET_FIELD(NPCX_SMBCTL2(ctrl), NPCX_SMBCTL2_SCLFRQ7_FIELD,
+			  (scl_freq & 0x7F));
+		SET_FIELD(NPCX_SMBCTL3(ctrl), NPCX_SMBCTL3_SCLFRQ2_FIELD,
+			  (scl_freq >> 7));
+		return;
+	}
 
-			for (j = 0; j < i2c_timing_used; j++, pTiming++) {
-				if (pTiming->clock == (freq/SECOND)) {
-					/* Set SCLH(L)T and hold-time */
-					NPCX_SMBSCLLT(ctrl) = pTiming->k1/2;
-					NPCX_SMBSCLHT(ctrl) = pTiming->k2/2;
-					SET_FIELD(NPCX_SMBCTL4(ctrl),
-					NPCX_SMBCTL4_HLDT_FIELD, pTiming->HLDT);
-					break;
-				}
-			}
-			if (j == i2c_timing_used)
-				cprints(CC_I2C,
-					"Error: Please make sure src clock of i2c %d is supported",
-					ctrl);
+	/* use Fast Mode */
+	SET_BIT(NPCX_SMBCTL3(ctrl), NPCX_SMBCTL3_400K);
+	/*
+	 * Set SCLH(L)T and hold-time directly for best I2C
+	 * timing condition for all source clocks. Please refer
+	 * Section 7.5.9 "SMBus Timing - Fast Mode" for detail.
+	 */
+	if (bus_freq_kbps == 400) {
+		pTiming = i2c_400k_timings;
+		i2c_timing_used = i2c_400k_timing_used;
+	} else if (bus_freq_kbps == 1000) {
+		pTiming = i2c_1m_timings;
+		i2c_timing_used = i2c_1m_timing_used;
+	} else {
+		i2c_stsobjs[ctrl].kbps = bus_freq_kbps;
+		/* Set value from formula */
+		NPCX_SMBSCLLT(ctrl) = scl_freq;
+		NPCX_SMBSCLHT(ctrl) = scl_freq;
+		cprints(CC_I2C,
+			"Warning: I2C %d: Use 400kHz or 1MHz for better timing",
+			ctrl);
+		return;
+	}
+
+	for (j = 0; j < i2c_timing_used; j++, pTiming++) {
+		if (pTiming->clock == (freq / SECOND)) {
+			i2c_stsobjs[ctrl].kbps = bus_freq_kbps;
+			/* Set SCLH(L)T and hold-time */
+			NPCX_SMBSCLLT(ctrl) = pTiming->k1 / 2;
+			NPCX_SMBSCLHT(ctrl) = pTiming->k2 / 2;
+			SET_FIELD(NPCX_SMBCTL4(ctrl), NPCX_SMBCTL4_HLDT_FIELD,
+				  pTiming->HLDT);
+			break;
 		}
 	}
+	if (j == i2c_timing_used)
+		cprints(CC_I2C, "Error: I2C %d: src clk %d not supported", ctrl,
+			freq / SECOND);
+}
+
+/* Hooks */
+
+static void i2c_freq_changed(void)
+{
+	int i;
+
+	for (i = 0; i < I2C_CONTROLLER_COUNT; ++i) {
+		/* No bus speed configured */
+		i2c_stsobjs[i].kbps = 0;
+	}
+
+	for (i = 0; i < i2c_ports_used; i++) {
+		const struct i2c_port_t *p;
+		int ctrl;
+
+		p = &i2c_ports[i];
+		ctrl = i2c_port_to_controller(p->port);
+		if (ctrl < 0)
+			continue;
+		i2c_port_set_freq(ctrl, p->kbps);
+	}
 }
+
 DECLARE_HOOK(HOOK_FREQ_CHANGE, i2c_freq_changed, HOOK_PRIO_DEFAULT);
 
+enum i2c_freq chip_i2c_get_freq(int chip_i2c_port)
+{
+	int ctrl;
+	int kbps;
+
+	ctrl = i2c_port_to_controller(chip_i2c_port);
+	if (ctrl < 0)
+		return I2C_FREQ_COUNT;
+
+	kbps = i2c_stsobjs[ctrl].kbps;
+
+	if (kbps > 400)
+		return I2C_FREQ_1000KHZ;
+	if (kbps > 100)
+		return I2C_FREQ_400KHZ;
+
+	if (kbps == 100)
+		return I2C_FREQ_100KHZ;
+
+	return I2C_FREQ_COUNT;
+}
+
+int chip_i2c_set_freq(int chip_i2c_port, enum i2c_freq freq)
+{
+	int ctrl;
+	int bus_freq_kbps;
+
+	ctrl = i2c_port_to_controller(chip_i2c_port);
+	if (ctrl < 0)
+		return EC_ERROR_INVAL;
+
+	switch (freq) {
+	case I2C_FREQ_100KHZ:
+		bus_freq_kbps = 100;
+		break;
+	case I2C_FREQ_400KHZ:
+		bus_freq_kbps = 400;
+		break;
+	case I2C_FREQ_1000KHZ:
+		bus_freq_kbps = 1000;
+		break;
+	default:
+		return EC_ERROR_INVAL;
+	}
+
+	i2c_port_set_freq(ctrl, bus_freq_kbps);
+	return EC_SUCCESS;
+}
+
 void i2c_init(void)
 {
 	int i;
@@ -1105,10 +1213,10 @@ void i2c_init(void)
 
 	/* Enable clock for I2C peripheral */
 	clock_enable_peripheral(CGC_OFFSET_I2C, CGC_I2C_MASK,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
+				CGC_MODE_RUN | CGC_MODE_SLEEP);
 #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
 	clock_enable_peripheral(CGC_OFFSET_I2C2, CGC_I2C_MASK2,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
+				CGC_MODE_RUN | CGC_MODE_SLEEP);
 #endif
 
 	/* Set I2C freq */
@@ -1140,4 +1248,3 @@ void i2c_init(void)
 		i2c_init_bus(ctrl);
 	}
 }
-
diff --git a/chip/npcx/i2c_chip.h b/chip/npcx/i2c_chip.h
index 014e6cddf2..d1a7cf6851 100644
--- a/chip/npcx/i2c_chip.h
+++ b/chip/npcx/i2c_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/npcx/keyboard_raw.c b/chip/npcx/keyboard_raw.c
index e6b8cad7bd..1774e7353d 100644
--- a/chip/npcx/keyboard_raw.c
+++ b/chip/npcx/keyboard_raw.c
@@ -1,15 +1,15 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Functions needed by keyboard scanner module for Chrome EC */
 
+#include "clock.h"
 #include "common.h"
+#include "gpio.h"
 #include "keyboard_raw.h"
 #include "keyboard_scan.h"
-#include "clock.h"
-#include "gpio.h"
 #include "registers.h"
 #include "task.h"
 
@@ -20,7 +20,7 @@ void keyboard_raw_init(void)
 {
 	/* Enable clock for KBS peripheral */
 	clock_enable_peripheral(CGC_OFFSET_KBS, CGC_KBS_MASK,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
+				CGC_MODE_RUN | CGC_MODE_SLEEP);
 
 	/* Ensure top-level interrupt is disabled */
 	keyboard_raw_enable_interrupt(0);
@@ -52,7 +52,7 @@ void keyboard_raw_init(void)
 	gpio_config_module(MODULE_KEYBOARD_SCAN, 1);
 
 	/*
-	 * Enable interrupts for the inputs.  The top-level interrupt is still
+	 * Enable interrupts for the inputs. The top-level interrupt is still
 	 * masked off, so this won't trigger interrupts yet.
 	 */
 
@@ -63,7 +63,7 @@ void keyboard_raw_init(void)
 	NPCX_WKEN(MIWU_TABLE_WKKEY, MIWU_GROUP_WKKEY) = 0xFF;
 
 	/* Select high to low transition (falling edge) */
-	NPCX_WKEDG(MIWU_TABLE_WKKEY, MIWU_GROUP_WKKEY) =  0xFF;
+	NPCX_WKEDG(MIWU_TABLE_WKKEY, MIWU_GROUP_WKKEY) = 0xFF;
 
 	/* Enable interrupt of WK KBS */
 	keyboard_raw_enable_interrupt(1);
@@ -72,6 +72,7 @@ void keyboard_raw_init(void)
 /**
  * Finish initialization after task scheduling has started.
  */
+#if !defined(CONFIG_KEYBOARD_SCAN_ADC)
 void keyboard_raw_task_start(void)
 {
 	/* Enable MIWU to trigger KBS interrupt */
@@ -138,6 +139,7 @@ test_mockable int keyboard_raw_read_rows(void)
 	return (~NPCX_KBSIN) & KB_ROW_MASK;
 }
 
+#ifndef NPCX_SELECT_KSI_TO_GPIO
 /**
  * Enable or disable keyboard interrupts.
  */
@@ -152,7 +154,7 @@ void keyboard_raw_enable_interrupt(int enable)
 /*
  * Interrupt handler for the entire GPIO bank of keyboard rows.
  */
-void keyboard_raw_interrupt(void)
+static void keyboard_raw_interrupt(void)
 {
 	/* Clear pending input sources used by scanner */
 	NPCX_WKPCL(MIWU_TABLE_WKKEY, MIWU_GROUP_WKKEY) = 0xFF;
@@ -161,9 +163,81 @@ void keyboard_raw_interrupt(void)
 	task_wake(TASK_ID_KEYSCAN);
 }
 DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1, keyboard_raw_interrupt, 5);
+#endif
+
+#else
+void keyboard_raw_task_start(void)
+{
+	/* Enable interrupts for keyboard matrix inputs */
+	keyboard_raw_enable_interrupt(1);
+}
+
+static void set_kb_columns(int level)
+{
+	gpio_set_level(GPIO_KSO_00, level & BIT(0));
+	gpio_set_level(GPIO_KSO_01, level & BIT(1));
+	gpio_set_level(GPIO_KSO_02, level & BIT(2));
+	gpio_set_level(GPIO_KSO_03, level & BIT(3));
+	gpio_set_level(GPIO_KSO_04, level & BIT(4));
+	gpio_set_level(GPIO_KSO_05, level & BIT(5));
+	gpio_set_level(GPIO_KSO_06, level & BIT(6));
+	gpio_set_level(GPIO_KSO_07, level & BIT(7));
+	gpio_set_level(GPIO_KSO_08, level & BIT(8));
+	gpio_set_level(GPIO_KSO_09, level & BIT(9));
+	gpio_set_level(GPIO_KSO_10, level & BIT(10));
+	gpio_set_level(GPIO_KSO_11, level & BIT(11));
+	gpio_set_level(GPIO_KSO_12, level & BIT(12));
+	gpio_set_level(GPIO_KSO_13, level & BIT(13));
+	gpio_set_level(GPIO_KSO_14, level & BIT(14));
+}
+
+void keyboard_raw_drive_column(int col)
+{
+	if (col == KEYBOARD_COLUMN_NONE)
+		/* Drive all lines to low */
+		set_kb_columns(0);
+
+	else if (col == KEYBOARD_COLUMN_ALL)
+		/* Drive all lines to high to detect any key press */
+		set_kb_columns(0xFFFF);
+
+	else
+		set_kb_columns(BIT(col));
+}
+
+void keyboard_raw_enable_interrupt(int enable)
+{
+	if (enable) {
+		gpio_enable_interrupt(GPIO_KSI_00);
+		gpio_enable_interrupt(GPIO_KSI_01);
+		gpio_enable_interrupt(GPIO_KSI_02);
+		gpio_enable_interrupt(GPIO_KSI_03);
+		gpio_enable_interrupt(GPIO_KSI_04);
+		gpio_enable_interrupt(GPIO_KSI_05);
+		gpio_enable_interrupt(GPIO_KSI_06);
+		gpio_enable_interrupt(GPIO_KSI_07);
+		gpio_enable_interrupt(GPIO_RFR_KEY_L);
+	} else {
+		gpio_disable_interrupt(GPIO_KSI_00);
+		gpio_disable_interrupt(GPIO_KSI_01);
+		gpio_disable_interrupt(GPIO_KSI_02);
+		gpio_disable_interrupt(GPIO_KSI_03);
+		gpio_disable_interrupt(GPIO_KSI_04);
+		gpio_disable_interrupt(GPIO_KSI_05);
+		gpio_disable_interrupt(GPIO_KSI_06);
+		gpio_disable_interrupt(GPIO_KSI_07);
+		gpio_disable_interrupt(GPIO_RFR_KEY_L);
+	}
+}
+
+void keyboard_raw_gpio_interrupt(enum gpio_signal signal)
+{
+	/* Wake the scan task */
+	task_wake(TASK_ID_KEYSCAN);
+}
+#endif
 
 int keyboard_raw_is_input_low(int port, int id)
 {
 	return (NPCX_PDIN(port) & BIT(id)) == 0;
 }
-
diff --git a/chip/npcx/lct.c b/chip/npcx/lct.c
index 1df2628c4f..8f720e1376 100644
--- a/chip/npcx/lct.c
+++ b/chip/npcx/lct.c
@@ -1,23 +1,22 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* LCT (Long Countdown Timer) module for Chrome EC */
-#include "lct_chip.h"
 #include "console.h"
 #include "hooks.h"
+#include "lct_chip.h"
 #include "registers.h"
 #include "rtc.h"
 #include "task.h"
 #include "timer.h"
 #include "util.h"
 
-#define LCT_CLK_ENABLE_DELAY_USEC    150
-#define LCT_WEEKS_MAX                 15
+#define LCT_CLK_ENABLE_DELAY_USEC 150
 
-#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args)
 
 void npcx_lct_sel_power_src(enum NPCX_LCT_PWR_SRC pwr_src)
 {
@@ -68,7 +67,7 @@ void npcx_lct_config(int seconds, int psl_ena, int int_ena)
 	}
 
 	/* LCT can count max to (16 weeks - 1 second) */
-	if (seconds >= (LCT_WEEKS_MAX + 1) * SECS_PER_WEEK) {
+	if (seconds > NPCX_LCT_MAX) {
 		CPRINTS("LCT time is out of range");
 		return;
 	}
@@ -94,7 +93,27 @@ void npcx_lct_config(int seconds, int psl_ena, int int_ena)
 
 	if (int_ena)
 		SET_BIT(NPCX_LCTCONT, NPCX_LCTCONT_EVEN);
+}
 
+uint32_t npcx_lct_get_time(void)
+{
+	uint32_t second;
+	uint8_t week, day, hour, minute;
+
+	do {
+		week = NPCX_LCTWEEK;
+		day = NPCX_LCTDAY;
+		hour = NPCX_LCTHOUR;
+		minute = NPCX_LCTMINUTE;
+		second = NPCX_LCTSECOND;
+	} while (week != NPCX_LCTWEEK || day != NPCX_LCTDAY ||
+		 hour != NPCX_LCTHOUR || minute != NPCX_LCTMINUTE ||
+		 second != NPCX_LCTSECOND);
+
+	second += minute * SECS_PER_MINUTE + hour * SECS_PER_HOUR +
+		  day * SECS_PER_DAY + week * SECS_PER_WEEK;
+
+	return second;
 }
 
 void npcx_lct_clear_event(void)
@@ -124,7 +143,7 @@ static void npcx_lct_init(void)
 DECLARE_HOOK(HOOK_INIT, npcx_lct_init, HOOK_PRIO_DEFAULT);
 
 #ifdef CONFIG_CMD_RTC_ALARM
-static int command_lctalarm(int argc, char **argv)
+static int command_lctalarm(int argc, const char **argv)
 {
 	char *e;
 	int seconds;
@@ -140,9 +159,9 @@ static int command_lctalarm(int argc, char **argv)
 	npcx_lct_config(seconds, 0, 1);
 	task_disable_irq(NPCX_IRQ_LCT_WKINTF_2);
 	/* Enable wake-up input sources & clear pending bit */
-	NPCX_WKPCL(MIWU_TABLE_2, LCT_WUI_GROUP)  |= LCT_WUI_MASK;
+	NPCX_WKPCL(MIWU_TABLE_2, LCT_WUI_GROUP) |= LCT_WUI_MASK;
 	NPCX_WKINEN(MIWU_TABLE_2, LCT_WUI_GROUP) |= LCT_WUI_MASK;
-	NPCX_WKEN(MIWU_TABLE_2, LCT_WUI_GROUP)   |= LCT_WUI_MASK;
+	NPCX_WKEN(MIWU_TABLE_2, LCT_WUI_GROUP) |= LCT_WUI_MASK;
 	task_enable_irq(NPCX_IRQ_LCT_WKINTF_2);
 	npcx_lct_enable(1);
 
diff --git a/chip/npcx/lct_chip.h b/chip/npcx/lct_chip.h
index 9e612f9e53..8b4ee804cf 100644
--- a/chip/npcx/lct_chip.h
+++ b/chip/npcx/lct_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,11 +6,11 @@
 #ifndef __CROS_EC_LCT_CHIP_H
 #define __CROS_EC_LCT_CHIP_H
 #include "registers.h"
+#include "rtc.h"
 
-enum NPCX_LCT_PWR_SRC {
-	NPCX_LCT_PWR_SRC_VCC1,
-	NPCX_LCT_PWR_SRC_VSBY
-};
+#define NPCX_LCT_MAX (16 * SECS_PER_WEEK - 1)
+
+enum NPCX_LCT_PWR_SRC { NPCX_LCT_PWR_SRC_VCC1, NPCX_LCT_PWR_SRC_VSBY };
 
 void npcx_lct_config(int seconds, int psl_ena, int int_ena);
 void npcx_lct_enable(uint8_t enable);
@@ -19,4 +19,7 @@ void npcx_lct_sel_power_src(enum NPCX_LCT_PWR_SRC pwr_src);
 void npcx_lct_clear_event(void);
 int npcx_lct_is_event_set(void);
 
-#endif  /* __CROS_EC_LCT_CHIP_H */
+/* return the current time of LCT in second */
+uint32_t npcx_lct_get_time(void);
+
+#endif /* __CROS_EC_LCT_CHIP_H */
diff --git a/chip/npcx/lfw/ec_lfw.h b/chip/npcx/lfw/ec_lfw.h
index 88c0a9ed83..3b7e4da459 100644
--- a/chip/npcx/lfw/ec_lfw.h
+++ b/chip/npcx/lfw/ec_lfw.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c
index d614c1788b..b44420e025 100644
--- a/chip/npcx/lpc.c
+++ b/chip/npcx/lpc.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,6 +10,7 @@
 #include "clock.h"
 #include "common.h"
 #include "console.h"
+#include "espi.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "host_command.h"
@@ -19,12 +20,12 @@
 #include "lpc_chip.h"
 #include "port80.h"
 #include "registers.h"
-#include "system.h"
 #include "sib_chip.h"
+#include "system.h"
+#include "system_chip.h"
 #include "task.h"
 #include "uart.h"
 #include "util.h"
-#include "system_chip.h"
 
 /* Console output macros */
 #if !(DEBUG_LPC)
@@ -32,24 +33,30 @@
 #define CPRINTS(...)
 #else
 #define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args)
 #endif
 
 /* PM channel definitions */
-#define PMC_ACPI     PM_CHAN_1
+#define PMC_ACPI PM_CHAN_1
 #define PMC_HOST_CMD PM_CHAN_2
 
-static struct	host_packet lpc_packet;
-static struct	host_cmd_handler_args host_cmd_args;
-static uint8_t	host_cmd_flags;         /* Flags from host command */
-static uint8_t	shm_mem_host_cmd[256] __aligned(8);
-static uint8_t	shm_memmap[256] __aligned(8);
+/* Microseconds to wait for eSPI VW changes to propagate */
+#define ESPI_DIRTY_WAIT_TIME_US 150
+
+#define PORT80_MAX_BUF_SIZE 16
+static uint16_t port80_buf[PORT80_MAX_BUF_SIZE];
+
+static struct host_packet lpc_packet;
+static struct host_cmd_handler_args host_cmd_args;
+static uint8_t host_cmd_flags; /* Flags from host command */
+static uint8_t shm_mem_host_cmd[256] __aligned(8);
+static uint8_t shm_memmap[256] __aligned(8);
 /* Params must be 32-bit aligned */
 static uint8_t params_copy[EC_LPC_HOST_PACKET_SIZE] __aligned(4);
 static int init_done;
 
-static struct ec_lpc_host_args * const lpc_host_args =
-		(struct ec_lpc_host_args *)shm_mem_host_cmd;
+static struct ec_lpc_host_args *const lpc_host_args =
+	(struct ec_lpc_host_args *)shm_mem_host_cmd;
 
 /*****************************************************************************/
 /* IC specific low-level driver */
@@ -83,7 +90,7 @@ static void lpc_task_enable_irq(void)
 #endif
 	task_enable_irq(NPCX_IRQ_PM_CHAN_IBF);
 	task_enable_irq(NPCX_IRQ_PORT80);
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	task_enable_irq(NPCX_IRQ_ESPI);
 	/* Virtual Wire: SLP_S3/4/5, SUS_STAT, PLTRST, OOB_RST_WARN */
 	task_enable_irq(NPCX_IRQ_WKINTA_2);
@@ -102,7 +109,7 @@ static void lpc_task_disable_irq(void)
 #endif
 	task_disable_irq(NPCX_IRQ_PM_CHAN_IBF);
 	task_disable_irq(NPCX_IRQ_PORT80);
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	task_disable_irq(NPCX_IRQ_ESPI);
 	/* Virtual Wire: SLP_S3/4/5, SUS_STAT, PLTRST, OOB_RST_WARN */
 	task_disable_irq(NPCX_IRQ_WKINTA_2);
@@ -134,7 +141,7 @@ static void lpc_generate_smi(void)
 	udelay(65);
 	/* Set signal high, now that we've generated the edge */
 	gpio_set_level(GPIO_PCH_SMI_L, 1);
-#elif defined(CONFIG_HOSTCMD_ESPI)
+#elif defined(CONFIG_HOST_INTERFACE_ESPI)
 	/*
 	 * Don't use SET_BIT/CLEAR_BIT macro to toggle SMIB/SCIB to generate
 	 * virtual wire. Use NPCX_VW_SMI/NPCX_VW_SCI macro instead.
@@ -142,20 +149,21 @@ static void lpc_generate_smi(void)
 	 * from SMIB/SCIB doesn't really reflect the SMI/SCI status. SMI/SCI
 	 * status should be read from bit 1/0 in eSPI VMEVSM(2) register.
 	 */
-	NPCX_HIPMIC(PMC_ACPI) = NPCX_VW_SMI(1);
-	udelay(65);
 	/* Generate a falling edge */
+	espi_wait_vw_not_dirty(VW_SMI_L, ESPI_DIRTY_WAIT_TIME_US);
 	NPCX_HIPMIC(PMC_ACPI) = NPCX_VW_SMI(0);
-	udelay(65);
+	udelay(CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US);
+	espi_wait_vw_not_dirty(VW_SMI_L, ESPI_DIRTY_WAIT_TIME_US);
+
 	/* Set signal high */
 	NPCX_HIPMIC(PMC_ACPI) = NPCX_VW_SMI(1);
 #else
 	/* SET SMIB bit to pull SMI_L to high.*/
 	SET_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SMIB);
-	udelay(65);
+	udelay(CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US);
 	/* Generate a falling edge */
 	CLEAR_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SMIB);
-	udelay(65);
+	udelay(CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US);
 	/* Set signal high */
 	SET_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SMIB);
 #endif
@@ -180,7 +188,7 @@ static void lpc_generate_sci(void)
 	udelay(65);
 	/* Set signal high, now that we've generated the edge */
 	gpio_set_level(CONFIG_SCI_GPIO, 1);
-#elif defined(CONFIG_HOSTCMD_ESPI)
+#elif defined(CONFIG_HOST_INTERFACE_ESPI)
 	/*
 	 * Don't use SET_BIT/CLEAR_BIT macro to toggle SMIB/SCIB to generate
 	 * virtual wire. Use NPCX_VW_SMI/NPCX_VW_SCI macro instead.
@@ -188,20 +196,21 @@ static void lpc_generate_sci(void)
 	 * from SMIB/SCIB doesn't really reflect the SMI/SCI status. SMI/SCI
 	 * status should be read from bit 1/0 in eSPI VMEVSM(2) register.
 	 */
-	NPCX_HIPMIC(PMC_ACPI) = NPCX_VW_SCI(1);
-	udelay(65);
 	/* Generate a falling edge */
+	espi_wait_vw_not_dirty(VW_SCI_L, ESPI_DIRTY_WAIT_TIME_US);
 	NPCX_HIPMIC(PMC_ACPI) = NPCX_VW_SCI(0);
-	udelay(65);
+	udelay(CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US);
+	espi_wait_vw_not_dirty(VW_SCI_L, ESPI_DIRTY_WAIT_TIME_US);
+
 	/* Set signal high */
 	NPCX_HIPMIC(PMC_ACPI) = NPCX_VW_SCI(1);
 #else
 	/* Set SCIB bit to pull SCI_L to high.*/
 	SET_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SCIB);
-	udelay(65);
+	udelay(CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US);
 	/* Generate a falling edge */
 	CLEAR_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SCIB);
-	udelay(65);
+	udelay(CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US);
 	/* Set signal high */
 	SET_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SCIB);
 #endif
@@ -251,15 +260,13 @@ static void lpc_send_response(struct host_cmd_handler_args *args)
 	}
 
 	/* New-style response */
-	lpc_host_args->flags =
-			(host_cmd_flags & ~EC_HOST_ARGS_FLAG_FROM_HOST) |
-			EC_HOST_ARGS_FLAG_TO_HOST;
+	lpc_host_args->flags = (host_cmd_flags & ~EC_HOST_ARGS_FLAG_FROM_HOST) |
+			       EC_HOST_ARGS_FLAG_TO_HOST;
 
 	lpc_host_args->data_size = size;
 
 	csum = args->command + lpc_host_args->flags +
-			lpc_host_args->command_version +
-			lpc_host_args->data_size;
+	       lpc_host_args->command_version + lpc_host_args->data_size;
 
 	for (i = 0, out = (uint8_t *)args->response; i < size; i++, out++)
 		csum += *out;
@@ -291,13 +298,13 @@ static void lpc_send_response_packet(struct host_packet *pkt)
 int lpc_keyboard_has_char(void)
 {
 	/* if OBF bit is '1', that mean still have a data in DBBOUT */
-	return (NPCX_HIKMST&0x01) ? 1 : 0;
+	return (NPCX_HIKMST & 0x01) ? 1 : 0;
 }
 
 int lpc_keyboard_input_pending(void)
 {
 	/* if IBF bit is '1', that mean still have a data in DBBIN */
-	return (NPCX_HIKMST&0x02) ? 1 : 0;
+	return (NPCX_HIKMST & 0x02) ? 1 : 0;
 }
 
 /* Put a char to host buffer by HIKDO and send IRQ if specified. */
@@ -398,7 +405,7 @@ void lpc_update_host_event_status(void)
 
 	/* Copy host events to mapped memory */
 	*(host_event_t *)host_get_memmap(EC_MEMMAP_HOST_EVENTS) =
-				lpc_get_host_events();
+		lpc_get_host_events();
 
 	lpc_task_enable_irq();
 
@@ -516,7 +523,7 @@ static void handle_host_write(int is_cmd)
 /* Interrupt handlers */
 #ifdef HAS_TASK_KEYPROTO
 /* KB controller input buffer full ISR */
-void lpc_kbc_ibf_interrupt(void)
+static void lpc_kbc_ibf_interrupt(void)
 {
 	uint8_t status;
 	uint8_t ibf;
@@ -540,7 +547,7 @@ void lpc_kbc_ibf_interrupt(void)
 DECLARE_IRQ(NPCX_IRQ_KBC_IBF, lpc_kbc_ibf_interrupt, 4);
 
 /* KB controller output buffer empty ISR */
-void lpc_kbc_obe_interrupt(void)
+static void lpc_kbc_obe_interrupt(void)
 {
 	/* Disable KBC OBE interrupt */
 	CLEAR_BIT(NPCX_HICTRL, NPCX_HICTRL_OBECIE);
@@ -556,38 +563,70 @@ DECLARE_IRQ(NPCX_IRQ_KBC_OBE, lpc_kbc_obe_interrupt, 4);
 #endif
 
 /* PM channel input buffer full ISR */
-void lpc_pmc_ibf_interrupt(void)
+static void lpc_pmc_ibf_interrupt(void)
 {
 	/* Channel-1 for ACPI usage*/
 	/* Channel-2 for Host Command usage , so the argument data had been
 	 * put on the share memory firstly*/
 	if (NPCX_HIPMST(PMC_ACPI) & 0x02)
-		handle_acpi_write((NPCX_HIPMST(PMC_ACPI)&0x08) ? 1 : 0);
+		handle_acpi_write((NPCX_HIPMST(PMC_ACPI) & 0x08) ? 1 : 0);
 	else if (NPCX_HIPMST(PMC_HOST_CMD) & 0x02)
-		handle_host_write((NPCX_HIPMST(PMC_HOST_CMD)&0x08) ? 1 : 0);
+		handle_host_write((NPCX_HIPMST(PMC_HOST_CMD) & 0x08) ? 1 : 0);
 }
 DECLARE_IRQ(NPCX_IRQ_PM_CHAN_IBF, lpc_pmc_ibf_interrupt, 4);
 
 /* PM channel output buffer empty ISR */
-void lpc_pmc_obe_interrupt(void)
+static void lpc_pmc_obe_interrupt(void)
 {
 }
 DECLARE_IRQ(NPCX_IRQ_PM_CHAN_OBE, lpc_pmc_obe_interrupt, 4);
 
-void lpc_port80_interrupt(void)
+static void lpc_port80_interrupt(void)
 {
-	/* Send port 80 data to UART continuously if FIFO is not empty */
-	while (IS_BIT_SET(NPCX_DP80STS, 6))
-		port_80_write(NPCX_DP80BUF);
+	uint8_t i;
+	uint8_t count = 0;
+	uint32_t code = 0;
+
+	/* buffer Port80 data to the local buffer if FIFO is not empty */
+	while (IS_BIT_SET(NPCX_DP80STS, NPCX_DP80STS_FNE) &&
+	       (count < ARRAY_SIZE(port80_buf)))
+		port80_buf[count++] = NPCX_DP80BUF;
+
+	for (i = 0; i < count; i++) {
+		uint8_t offset;
+		uint32_t buf_data;
+
+		buf_data = port80_buf[i];
+		offset = GET_FIELD(buf_data, NPCX_DP80BUF_OFFS_FIELD);
+		code |= (buf_data & 0xFF) << (8 * offset);
+
+		if (i == count - 1) {
+			port_80_write(code);
+			break;
+		}
+
+		/* peek the offset of the next byte */
+		buf_data = port80_buf[i + 1];
+		offset = GET_FIELD(buf_data, NPCX_DP80BUF_OFFS_FIELD);
+		/*
+		 * If the peeked next byte's offset is 0 means it is the start
+		 * of the new code. Pass the current code to Port80
+		 * common layer.
+		 */
+		if (offset == 0) {
+			port_80_write(code);
+			code = 0;
+		}
+	}
 
 	/* If FIFO is overflow */
-	if (IS_BIT_SET(NPCX_DP80STS, 7)) {
-		SET_BIT(NPCX_DP80STS, 7);
+	if (IS_BIT_SET(NPCX_DP80STS, NPCX_DP80STS_FOR)) {
+		SET_BIT(NPCX_DP80STS, NPCX_DP80STS_FOR);
 		CPRINTS("DP80 FIFO Overflow!");
 	}
 
 	/* Clear pending bit of host writing */
-	SET_BIT(NPCX_DP80STS, 5);
+	SET_BIT(NPCX_DP80STS, NPCX_DP80STS_FWR);
 }
 DECLARE_IRQ(NPCX_IRQ_PORT80, lpc_port80_interrupt, 4);
 
@@ -649,19 +688,26 @@ void host_register_init(void)
 	/* LDN register = 0x0F(SHM) */
 	sib_write_reg(SIO_OFFSET, 0x07, 0x0F);
 	/* WIN1&2 mapping to IO */
-	sib_write_reg(SIO_OFFSET, 0xF1,
-			sib_read_reg(SIO_OFFSET, 0xF1) | 0x30);
+	sib_write_reg(SIO_OFFSET, 0xF1, sib_read_reg(SIO_OFFSET, 0xF1) | 0x30);
 	/* WIN1 as Host Command on the IO:0x0800 */
 	sib_write_reg(SIO_OFFSET, 0xF5, 0x08);
 	sib_write_reg(SIO_OFFSET, 0xF4, 0x00);
 	/* WIN2 as MEMMAP on the IO:0x900 */
 	sib_write_reg(SIO_OFFSET, 0xF9, 0x09);
 	sib_write_reg(SIO_OFFSET, 0xF8, 0x00);
+
+	/*
+	 * eSPI allows sending 4 bytes of Port80 code in a single PUT_IOWR_SHORT
+	 * transaction. When setting OFS0_SEL~OFS3_SEL in DPAR1 register to 1,
+	 * EC hardware will put those 4 bytes of Port80 code to DP80BUF FIFO.
+	 * This is only supported when CHIP_FAMILY >= NPCX9.
+	 */
+	if (IS_ENABLED(CONFIG_HOST_INTERFACE_ESPI))
+		sib_write_reg(SIO_OFFSET, 0xFD, 0x0F);
 	/* enable SHM */
 	sib_write_reg(SIO_OFFSET, 0x30, 0x01);
 
 	CPRINTS("Host settings are done!");
-
 }
 
 #ifdef CONFIG_CHIPSET_RESET_HOOK
@@ -678,14 +724,14 @@ int lpc_get_pltrst_asserted(void)
 	return IS_BIT_SET(NPCX_MSWCTL1, NPCX_MSWCTL1_PLTRST_ACT);
 }
 
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
 /* Initialize host settings by interrupt */
 void lpc_lreset_pltrst_handler(void)
 {
 	int pltrst_asserted;
 
 	/* Clear pending bit of WUI */
-	SET_BIT(NPCX_WKPCL(MIWU_TABLE_0 , MIWU_GROUP_5), 7);
+	SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_5), 7);
 
 	/* Ignore PLTRST# from SOC if it is not valid */
 	if (chipset_pltrst_is_valid && !chipset_pltrst_is_valid())
@@ -720,7 +766,7 @@ static void lpc_init(void)
 {
 	/* Enable clock for LPC peripheral */
 	clock_enable_peripheral(CGC_OFFSET_LPC, CGC_LPC_MASK,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
+				CGC_MODE_RUN | CGC_MODE_SLEEP);
 	/*
 	 * In npcx5/7, the host interface type (HIF_TYP_SEL in the DEVCNT
 	 * register) is updated by booter after VCC1 Power-Up reset according to
@@ -728,7 +774,7 @@ static void lpc_init(void)
 	 * In npcx9, the booter will not do this anymore. The HIF_TYP_SEL
 	 * field should be set by firmware.
 	 */
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	/* Initialize eSPI module */
 	NPCX_DEVCNT |= 0x08;
 	espi_init();
@@ -744,7 +790,7 @@ static void lpc_init(void)
 	/* Clear Host Access Hold state */
 	NPCX_SMC_CTL = 0xC0;
 
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
 	/*
 	 * Set alternative pin from GPIO to CLKRUN no matter SERIRQ is under
 	 * continuous or quiet mode.
@@ -757,7 +803,7 @@ static void lpc_init(void)
 	 * valid if CONFIG_SCI_GPIO isn't defined. eSPI sends SMI/SCI through VW
 	 * automatically by toggling them, too. It's unnecessary to set pin mux.
 	 */
-#if !defined(CONFIG_SCI_GPIO) && !defined(CONFIG_HOSTCMD_ESPI)
+#if !defined(CONFIG_SCI_GPIO) && !defined(CONFIG_HOST_INTERFACE_ESPI)
 	SET_BIT(NPCX_DEVALT(1), NPCX_DEVALT1_EC_SCI_SL);
 	SET_BIT(NPCX_DEVALT(1), NPCX_DEVALT1_SMI_SL);
 #endif
@@ -789,8 +835,8 @@ static void lpc_init(void)
 
 	/* We support LPC args and version 3 protocol */
 	*(lpc_get_memmap_range() + EC_MEMMAP_HOST_CMD_FLAGS) =
-			EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED |
-			EC_HOST_CMD_FLAG_VERSION_3;
+		EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED |
+		EC_HOST_CMD_FLAG_VERSION_3;
 
 	/*
 	 * Clear processing flag before enabling lpc's interrupts in case
@@ -804,7 +850,7 @@ static void lpc_init(void)
 	/*
 	 * Set required control value (avoid setting HOSTWAIT bit at this stage)
 	 */
-	NPCX_SMC_CTL = NPCX_SMC_CTL&~0x7F;
+	NPCX_SMC_CTL = NPCX_SMC_CTL & ~0x7F;
 	/* Clear status */
 	NPCX_SMC_STS = NPCX_SMC_STS;
 
@@ -833,7 +879,7 @@ static void lpc_init(void)
 	 * Init PORT80
 	 * Enable Port80, Enable Port80 function & Interrupt & Read auto
 	 */
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	NPCX_DP80CTL = 0x2b;
 #else
 	NPCX_DP80CTL = 0x29;
@@ -853,8 +899,8 @@ static void lpc_init(void)
 	CLEAR_BIT(NPCX_HIPMCTL(PMC_ACPI), NPCX_HIPMCTL_SCIPOL);
 	CLEAR_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SMIPOL);
 	/* Set SMIB/SCIB to make sure SMI/SCI are high at init */
-	NPCX_HIPMIC(PMC_ACPI) = NPCX_HIPMIC(PMC_ACPI)
-			| BIT(NPCX_HIPMIC_SMIB) | BIT(NPCX_HIPMIC_SCIB);
+	NPCX_HIPMIC(PMC_ACPI) = NPCX_HIPMIC(PMC_ACPI) | BIT(NPCX_HIPMIC_SMIB) |
+				BIT(NPCX_HIPMIC_SCIB);
 #ifndef CONFIG_SCI_GPIO
 	/*
 	 * Allow SMI/SCI generated from PM module.
@@ -883,7 +929,7 @@ static void lpc_init(void)
 	/* initial IO port address via SIB-write modules */
 	host_register_init();
 #else
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
 	/*
 	 * Initialize LRESET# interrupt only in case of LPC. For eSPI, there is
 	 * no dedicated GPIO pin for LRESET/PLTRST. PLTRST is indicated as a VW
@@ -921,14 +967,13 @@ static enum ec_status lpc_get_protocol_info(struct host_cmd_handler_args *args)
 
 	args->response_size = sizeof(*r);
 
-	return EC_SUCCESS;
+	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO,
-		lpc_get_protocol_info,
-		EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, lpc_get_protocol_info,
+		     EC_VER_MASK(0));
 
 #if DEBUG_LPC
-static int command_lpc(int argc, char **argv)
+static int command_lpc(int argc, const char **argv)
 {
 	if (argc == 1)
 		return EC_ERROR_PARAM1;
diff --git a/chip/npcx/lpc_chip.h b/chip/npcx/lpc_chip.h
index 607fdde5fa..872b20f915 100644
--- a/chip/npcx/lpc_chip.h
+++ b/chip/npcx/lpc_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/npcx/peci.c b/chip/npcx/peci.c
index f3145bd2a7..8a4372f7bd 100644
--- a/chip/npcx/peci.c
+++ b/chip/npcx/peci.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,35 +15,33 @@
 #include "peci.h"
 #include "registers.h"
 #include "task.h"
-#include "timer.h"
 #include "temp_sensor.h"
+#include "timer.h"
 #include "util.h"
 
-
 /* Initial PECI baud rate */
-#define PECI_BAUD_RATE        750000
-
-#define TEMP_AVG_LENGTH       4  /* Should be power of 2 */
+#define PECI_BAUD_RATE 750000
 
+#define TEMP_AVG_LENGTH 4 /* Should be power of 2 */
 
 /* PECI Time-out */
-#define PECI_DONE_TIMEOUT_US  (10*MSEC)
+#define PECI_DONE_TIMEOUT_US (10 * MSEC)
 
-#define NULL_PENDING_TASK_ID  0xFFFFFFFF
-#define PECI_MAX_FIFO_SIZE    16
-#define PROC_SOCKET           0x30
+#define NULL_PENDING_TASK_ID 0xFFFFFFFF
+#define PECI_MAX_FIFO_SIZE 16
+#define PROC_SOCKET 0x30
 /* PECI Command Code */
 enum peci_command_t {
-	PECI_COMMAND_PING               = 0x00,
-	PECI_COMMAND_GET_DIB            = 0xF7,
-	PECI_COMMAND_GET_TEMP           = 0x01,
-	PECI_COMMAND_RD_PKG_CFG         = 0xA1,
-	PECI_COMMAND_WR_PKG_CFG         = 0xA5,
-	PECI_COMMAND_RD_IAMSR           = 0xB1,
-	PECI_COMMAND_RD_PCI_CFG         = 0x61,
-	PECI_COMMAND_RD_PCI_CFG_LOCAL   = 0xE1,
-	PECI_COMMAND_WR_PCI_CFG_LOCAL   = 0xE5,
-	PECI_COMMAND_NONE               = 0xFF
+	PECI_COMMAND_PING = 0x00,
+	PECI_COMMAND_GET_DIB = 0xF7,
+	PECI_COMMAND_GET_TEMP = 0x01,
+	PECI_COMMAND_RD_PKG_CFG = 0xA1,
+	PECI_COMMAND_WR_PKG_CFG = 0xA5,
+	PECI_COMMAND_RD_IAMSR = 0xB1,
+	PECI_COMMAND_RD_PCI_CFG = 0x61,
+	PECI_COMMAND_RD_PCI_CFG_LOCAL = 0xE1,
+	PECI_COMMAND_WR_PCI_CFG_LOCAL = 0xE5,
+	PECI_COMMAND_NONE = 0xFF
 };
 
 #define PECI_COMMAND_GET_TEMP_WR_LENS 0x00
@@ -68,12 +66,8 @@ static int peci_pending_task_id;
  * @param   *wr_data  Buffer pointer of write data
  * @return  TASK_EVENT_PECI_DONE that mean slave had a response
  */
-static uint32_t peci_trans(
-		uint8_t             wr_length,
-		uint8_t             rd_length,
-		enum peci_command_t cmd_code,
-		uint8_t            *wr_data
-)
+static uint32_t peci_trans(uint8_t wr_length, uint8_t rd_length,
+			   enum peci_command_t cmd_code, uint8_t *wr_data)
 {
 	uint32_t events;
 	/* Ensure no PECI transaction is in progress */
@@ -100,7 +94,7 @@ static uint32_t peci_trans(
 	/* Write-Length */
 	if (cmd_code != PECI_COMMAND_PING) {
 		if ((cmd_code == PECI_COMMAND_WR_PKG_CFG) ||
-				(cmd_code == PECI_COMMAND_WR_PCI_CFG_LOCAL)) {
+		    (cmd_code == PECI_COMMAND_WR_PCI_CFG_LOCAL)) {
 			/*CMD+AWFCS*/
 			NPCX_PECI_WR_LENGTH = wr_length + 2;
 			/* Enable AWFCS */
@@ -110,7 +104,7 @@ static uint32_t peci_trans(
 			NPCX_PECI_WR_LENGTH = wr_length + 1;
 			/* Enable AWFCS */
 			CLEAR_BIT(NPCX_PECI_CTL_STS,
-					NPCX_PECI_CTL_STS_AWFCS_EN);
+				  NPCX_PECI_CTL_STS_AWFCS_EN);
 		}
 	}
 
@@ -119,9 +113,7 @@ static uint32_t peci_trans(
 
 	/* It should be using a interrupt , don't waste cpu computing power */
 	peci_pending_task_id = task_get_current();
-	return task_wait_event_mask(TASK_EVENT_PECI_DONE,
-					PECI_DONE_TIMEOUT_US);
-
+	return task_wait_event_mask(TASK_EVENT_PECI_DONE, PECI_DONE_TIMEOUT_US);
 }
 
 /**
@@ -143,8 +135,8 @@ int peci_get_cpu_temp(void)
 
 	/* Start PECI trans */
 	events = peci_trans(PECI_COMMAND_GET_TEMP_WR_LENS,
-				PECI_COMMAND_GET_TEMP_RD_LENS,
-				PECI_COMMAND_GET_TEMP, NULL);
+			    PECI_COMMAND_GET_TEMP_RD_LENS,
+			    PECI_COMMAND_GET_TEMP, NULL);
 	/* if return DONE , that mean slave had a PECI response */
 	if ((events & TASK_EVENT_PECI_DONE) == TASK_EVENT_PECI_DONE) {
 		/* check CRC & ABRT */
@@ -223,7 +215,7 @@ static void peci_freq_changed(void)
 	 * Maximum bit rate should not extend the field's boundaries.
 	 */
 	if (freq != 0) {
-		baud = (uint8_t)(freq  / (4 * PECI_BAUD_RATE)) - 1;
+		baud = (uint8_t)(freq / (4 * PECI_BAUD_RATE)) - 1;
 		/* Set maximum PECI baud rate (bit0 - bit4) */
 		if (baud > 0x1F)
 			baud = 0x1F;
@@ -247,7 +239,7 @@ static void peci_init(void)
 
 	/* Enable clock for PECI peripheral */
 	clock_enable_peripheral(CGC_OFFSET_PECI, CGC_PECI_MASK,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
+				CGC_MODE_RUN | CGC_MODE_SLEEP);
 	/* Set PECI freq */
 	peci_freq_changed();
 
@@ -269,9 +261,10 @@ static void peci_init(void)
 DECLARE_HOOK(HOOK_INIT, peci_init, HOOK_PRIO_DEFAULT);
 
 /* If received a PECI DONE interrupt, post the event to PECI task */
-void peci_done_interrupt(void){
+static void peci_done_interrupt(void)
+{
 	if (peci_pending_task_id != NULL_PENDING_TASK_ID)
-		task_set_event(peci_pending_task_id, TASK_EVENT_PECI_DONE, 0);
+		task_set_event(peci_pending_task_id, TASK_EVENT_PECI_DONE);
 	peci_sts = NPCX_PECI_CTL_STS & 0x18;
 	/* no matter what, clear status bit again */
 	SET_BIT(NPCX_PECI_CTL_STS, NPCX_PECI_CTL_STS_DONE);
@@ -283,7 +276,7 @@ DECLARE_IRQ(NPCX_IRQ_PECI, peci_done_interrupt, 4);
 /*****************************************************************************/
 /* Console commands */
 
-static int command_peci_temp(int argc, char **argv)
+static int command_peci_temp(int argc, const char **argv)
 {
 	int t = peci_get_cpu_temp();
 	if (t == -1) {
@@ -293,6 +286,5 @@ static int command_peci_temp(int argc, char **argv)
 	ccprintf("CPU temp = %d K = %d\n", t, K_TO_C(t));
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(pecitemp, command_peci_temp,
-		NULL,
-		"Print CPU temperature");
+DECLARE_CONSOLE_COMMAND(pecitemp, command_peci_temp, NULL,
+			"Print CPU temperature");
diff --git a/chip/npcx/ps2.c b/chip/npcx/ps2.c
index c470bbe68d..5fc91ef241 100644
--- a/chip/npcx/ps2.c
+++ b/chip/npcx/ps2.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,33 +8,33 @@
 #include "atomic.h"
 #include "clock.h"
 #include "console.h"
-#include "hooks.h"
 #include "gpio.h"
+#include "hooks.h"
 #include "ps2_chip.h"
-#include "task.h"
 #include "registers.h"
+#include "task.h"
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_PS2, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_PS2, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_PS2, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_PS2, format, ##args)
 
 #if !(DEBUG_PS2)
 #define DEBUG_CPRINTS(...)
 #define DEBUG_CPRINTF(...)
 #else
-#define DEBUG_CPRINTS(format, args...) cprints(CC_PS2, format, ## args)
-#define DEBUG_CPRINTF(format, args...) cprintf(CC_PS2, format, ## args)
+#define DEBUG_CPRINTS(format, args...) cprints(CC_PS2, format, ##args)
+#define DEBUG_CPRINTF(format, args...) cprintf(CC_PS2, format, ##args)
 #endif
 
 /*
  * Set WDAT3-0 and clear CLK3-0 in the PSOSIG register to
  * reset the shift mechanism.
  */
-#define PS2_SHIFT_MECH_RESET       0x47
+#define PS2_SHIFT_MECH_RESET 0x47
 
-#define PS2_TRANSACTION_TIMEOUT    (20 * MSEC)
-#define PS2_BUSY_RETRY             10
+#define PS2_TRANSACTION_TIMEOUT (20 * MSEC)
+#define PS2_BUSY_RETRY 10
 
 enum ps2_input_debounce_cycle {
 	PS2_IDB_1_CYCLE,
@@ -60,7 +60,7 @@ struct ps2_data {
 	void (*rx_handler_cb)(uint8_t data);
 };
 static struct ps2_data ps2_ch_data[NPCX_PS2_CH_COUNT] = {
-	 [0 ... (NPCX_PS2_CH_COUNT - 1)] =  { PS2_RX_MODE, NULL }
+	[0 ...(NPCX_PS2_CH_COUNT - 1)] = { PS2_RX_MODE, NULL }
 };
 
 /*
@@ -76,7 +76,7 @@ static void ps2_init(void)
 {
 	/* Disable the power down bit of PS/2 */
 	clock_enable_peripheral(CGC_OFFSET_PS2, CGC_PS2_MASK,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
+				CGC_MODE_RUN | CGC_MODE_SLEEP);
 
 	/* Disable shift mechanism and configure PS/2 to received mode. */
 	NPCX_PS2_PSCON = 0x0;
@@ -90,10 +90,9 @@ static void ps2_init(void)
 	 * [4] - : WUE     = 1: Wake-Up Enable
 	 * [7] - : CLK_SEL = 1: Select Free-Run clock as the basic clock
 	 */
-	NPCX_PS2_PSIEN = BIT(NPCX_PS2_PSIEN_SOTIE) |
-				BIT(NPCX_PS2_PSIEN_EOTIE) |
-				BIT(NPCX_PS2_PSIEN_PS2_WUE) |
-				BIT(NPCX_PS2_PSIEN_PS2_CLK_SEL);
+	NPCX_PS2_PSIEN = BIT(NPCX_PS2_PSIEN_SOTIE) | BIT(NPCX_PS2_PSIEN_EOTIE) |
+			 BIT(NPCX_PS2_PSIEN_PS2_WUE) |
+			 BIT(NPCX_PS2_PSIEN_PS2_CLK_SEL);
 
 	/* Enable weak internal pull-up */
 	SET_BIT(NPCX_PS2_PSCON, NPCX_PS2_PSCON_WPUED);
@@ -106,8 +105,7 @@ static void ps2_init(void)
 }
 DECLARE_HOOK(HOOK_INIT, ps2_init, HOOK_PRIO_DEFAULT);
 
-void ps2_enable_channel(int channel, int enable,
-					void (*callback)(uint8_t data))
+void ps2_enable_channel(int channel, int enable, void (*callback)(uint8_t data))
 {
 	if (channel >= NPCX_PS2_CH_COUNT) {
 		CPRINTS("Err:PS/2 CH exceed %d", NPCX_PS2_CH_COUNT);
@@ -125,7 +123,7 @@ void ps2_enable_channel(int channel, int enable,
 		/* Enable the relevant channel clock */
 		SET_BIT(NPCX_PS2_PSOSIG, NPCX_PS2_PSOSIG_CLK(channel));
 	} else {
-		channel_enabled_mask &=  ~BIT(NPCX_PS2_PSOSIG_CLK(channel));
+		channel_enabled_mask &= ~BIT(NPCX_PS2_PSOSIG_CLK(channel));
 		/* Disable the relevant channel clock */
 		CLEAR_BIT(NPCX_PS2_PSOSIG, NPCX_PS2_PSOSIG_CLK(channel));
 		ps2_ch_data[channel].rx_handler_cb = NULL;
@@ -144,7 +142,9 @@ static int ps2_is_busy(void)
 	 * (due to Shift Mechanism is reset)
 	 */
 	return (IS_BIT_SET(NPCX_PS2_PSTAT, NPCX_PS2_PSTAT_SOT) |
-		IS_BIT_SET(NPCX_PS2_PSTAT, NPCX_PS2_PSTAT_EOT)) ? 1 : 0;
+		IS_BIT_SET(NPCX_PS2_PSTAT, NPCX_PS2_PSTAT_EOT)) ?
+		       1 :
+		       0;
 }
 
 int ps2_transmit_byte(int channel, uint8_t data)
@@ -194,7 +194,7 @@ int ps2_transmit_byte(int channel, uint8_t data)
 
 	/* Wait for interrupt */
 	event = task_wait_event_mask(TASK_EVENT_PS2_DONE,
-					PS2_TRANSACTION_TIMEOUT);
+				     PS2_TRANSACTION_TIMEOUT);
 	task_waiting = TASK_ID_INVALID;
 
 	if (event == TASK_EVENT_TIMER) {
@@ -216,7 +216,6 @@ int ps2_transmit_byte(int channel, uint8_t data)
 
 	DEBUG_CPRINTF("Evt:0x%08x\n", event);
 	return (event == TASK_EVENT_PS2_DONE) ? EC_SUCCESS : EC_ERROR_TIMEOUT;
-
 }
 
 static void ps2_stop_inactive_ch_clk(uint8_t active_ch)
@@ -224,20 +223,17 @@ static void ps2_stop_inactive_ch_clk(uint8_t active_ch)
 	uint8_t mask;
 
 	mask = ~NPCX_PS2_PSOSIG_CLK_MASK_ALL |
-					BIT(NPCX_PS2_PSOSIG_CLK(active_ch));
+	       BIT(NPCX_PS2_PSOSIG_CLK(active_ch));
 	NPCX_PS2_PSOSIG &= mask;
-
 }
 
 static int ps2_is_rx_error(uint8_t ch)
 {
-	uint8_t	status;
+	uint8_t status;
 
 	status = NPCX_PS2_PSTAT &
-				(BIT(NPCX_PS2_PSTAT_PERR) |
-				 BIT(NPCX_PS2_PSTAT_RFERR));
+		 (BIT(NPCX_PS2_PSTAT_PERR) | BIT(NPCX_PS2_PSTAT_RFERR));
 	if (status) {
-
 		if (status & BIT(NPCX_PS2_PSTAT_PERR))
 			CPRINTF("PS2 CH %d RX parity error\n", ch);
 		if (status & BIT(NPCX_PS2_PSTAT_RFERR))
@@ -247,7 +243,7 @@ static int ps2_is_rx_error(uint8_t ch)
 		return 0;
 }
 
-void ps2_int_handler(void)
+static void ps2_int_handler(void)
 {
 	uint8_t active_ch;
 
@@ -270,7 +266,7 @@ void ps2_int_handler(void)
 
 	/* PS/2 Start of Transaction */
 	if (IS_BIT_SET(NPCX_PS2_PSTAT, NPCX_PS2_PSTAT_SOT) &&
-			IS_BIT_SET(NPCX_PS2_PSIEN, NPCX_PS2_PSIEN_SOTIE)) {
+	    IS_BIT_SET(NPCX_PS2_PSIEN, NPCX_PS2_PSIEN_SOTIE)) {
 		DEBUG_CPRINTF("SOT-");
 		/*
 		 * Once set, SOT is not cleared until the shift mechanism
@@ -278,7 +274,7 @@ void ps2_int_handler(void)
 		 * first occurrence of an SOT interrupt.
 		 */
 		CLEAR_BIT(NPCX_PS2_PSIEN, NPCX_PS2_PSIEN_SOTIE);
-	/* PS/2 End of Transaction */
+		/* PS/2 End of Transaction */
 	} else if (IS_BIT_SET(NPCX_PS2_PSTAT, NPCX_PS2_PSTAT_EOT)) {
 		DEBUG_CPRINTF("EOT-");
 		CLEAR_BIT(NPCX_PS2_PSIEN, NPCX_PS2_PSIEN_EOTIE);
@@ -293,12 +289,12 @@ void ps2_int_handler(void)
 			/* Change the PS/2 module to receive mode */
 			CLEAR_BIT(NPCX_PS2_PSCON, NPCX_PS2_PSCON_XMT);
 			ps2_ch_data[active_ch].opr_mode = PS2_RX_MODE;
-			task_set_event(task_waiting, TASK_EVENT_PS2_DONE, 0);
+			task_set_event(task_waiting, TASK_EVENT_PS2_DONE);
 		} else {
 			if (!ps2_is_rx_error(active_ch)) {
 				uint8_t data_read = NPCX_PS2_PSDAT;
 				struct ps2_data *ps2_ptr =
-							&ps2_ch_data[active_ch];
+					&ps2_ch_data[active_ch];
 
 				DEBUG_CPRINTF("Recv:0x%02x", data_read);
 				if (ps2_ptr->rx_handler_cb)
@@ -316,12 +312,11 @@ void ps2_int_handler(void)
 		SET_BIT(NPCX_PS2_PSIEN, NPCX_PS2_PSIEN_EOTIE);
 	}
 	DEBUG_CPRINTF("\n");
-
 }
 DECLARE_IRQ(NPCX_IRQ_PS2, ps2_int_handler, 5);
 
 #ifdef CONFIG_CMD_PS2
-static int command_ps2ench(int argc, char **argv)
+static int command_ps2ench(int argc, const char **argv)
 {
 	uint8_t ch;
 	uint8_t enable;
@@ -341,11 +336,10 @@ static int command_ps2ench(int argc, char **argv)
 
 	return 0;
 }
-DECLARE_CONSOLE_COMMAND(ps2ench, command_ps2ench,
-			"ps2_ench channel 1|0",
+DECLARE_CONSOLE_COMMAND(ps2ench, command_ps2ench, "ps2_ench channel 1|0",
 			"Enable/Disable PS/2 channel");
 
-static int command_ps2write(int argc, char **argv)
+static int command_ps2write(int argc, const char **argv)
 {
 	uint8_t ch, data;
 	char *e;
@@ -360,7 +354,6 @@ static int command_ps2write(int argc, char **argv)
 	ps2_transmit_byte(ch, data);
 	return 0;
 }
-DECLARE_CONSOLE_COMMAND(ps2write, command_ps2write,
-		"ps2_write channel data",
-		"Write data byte to PS/2 channel ");
+DECLARE_CONSOLE_COMMAND(ps2write, command_ps2write, "ps2_write channel data",
+			"Write data byte to PS/2 channel ");
 #endif
diff --git a/chip/npcx/ps2_chip.h b/chip/npcx/ps2_chip.h
index d88e6791ad..871b1ab6e5 100644
--- a/chip/npcx/ps2_chip.h
+++ b/chip/npcx/ps2_chip.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,4 +21,4 @@ void ps2_enable_channel(int channel, int enable,
 			void (*callback)(uint8_t data));
 int ps2_transmit_byte(int channel, uint8_t data);
 
-#endif  /* __CROS_EC_PS2_CHIP_H */
+#endif /* __CROS_EC_PS2_CHIP_H */
diff --git a/chip/npcx/pwm.c b/chip/npcx/pwm.c
index 541c29de99..53a278a0ba 100644
--- a/chip/npcx/pwm.c
+++ b/chip/npcx/pwm.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,7 +8,7 @@
  * On this chip, the PWM logic is implemented by the hardware FAN modules.
  */
 
-#include "assert.h"
+#include "builtin/assert.h"
 #include "clock.h"
 #include "clock_chip.h"
 #include "console.h"
@@ -23,7 +23,7 @@
 #if !(DEBUG_PWM)
 #define CPRINTS(...)
 #else
-#define CPRINTS(format, args...) cprints(CC_PWM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_PWM, format, ##args)
 #endif
 
 /* pwm resolution for each channel */
@@ -31,20 +31,20 @@ static uint32_t pwm_res[PWM_CH_COUNT];
 
 /* PWM clock source */
 enum npcx_pwm_source_clock {
-	NPCX_PWM_CLOCK_APB2_LFCLK  = 0,
-	NPCX_PWM_CLOCK_FX          = 1,
-	NPCX_PWM_CLOCK_FR          = 2,
-	NPCX_PWM_CLOCK_RESERVED    = 3,
-	NPCX_PWM_CLOCK_UNDEF       = 0xFF
+	NPCX_PWM_CLOCK_APB2_LFCLK = 0,
+	NPCX_PWM_CLOCK_FX = 1,
+	NPCX_PWM_CLOCK_FR = 2,
+	NPCX_PWM_CLOCK_RESERVED = 3,
+	NPCX_PWM_CLOCK_UNDEF = 0xFF
 };
 
 /* PWM heartbeat mode */
 enum npcx_pwm_heartbeat_mode {
-	NPCX_PWM_HBM_NORMAL    = 0,
-	NPCX_PWM_HBM_25        = 1,
-	NPCX_PWM_HBM_50        = 2,
-	NPCX_PWM_HBM_100       = 3,
-	NPCX_PWM_HBM_UNDEF     = 0xFF
+	NPCX_PWM_HBM_NORMAL = 0,
+	NPCX_PWM_HBM_25 = 1,
+	NPCX_PWM_HBM_50 = 2,
+	NPCX_PWM_HBM_100 = 3,
+	NPCX_PWM_HBM_UNDEF = 0xFF
 };
 
 /**
@@ -127,7 +127,7 @@ int pwm_get_enabled(enum pwm_channel ch)
  */
 void pwm_set_duty(enum pwm_channel ch, int percent)
 {
-	/* Convert 16 bit duty to percent on [0, 100] */
+	/* Convert percent on [0, 100] to 16 bit duty */
 	pwm_set_raw_duty(ch, (percent * EC_PWM_MAX_DUTY) / 100);
 }
 
@@ -146,7 +146,7 @@ void pwm_set_raw_duty(enum pwm_channel ch, uint16_t duty)
 
 	/* Assume the fan control is active high and invert it ourselves */
 	UPDATE_BIT(NPCX_PWMCTL(mdl), NPCX_PWMCTL_INVP,
-			(pwm_channels[ch].flags & PWM_CONFIG_ACTIVE_LOW));
+		   (pwm_channels[ch].flags & PWM_CONFIG_ACTIVE_LOW));
 
 	CPRINTS("initial freq=0x%x", pwm_channels[ch].freq);
 	CPRINTS("duty_cycle_cnt=%d", duty);
@@ -189,7 +189,7 @@ uint16_t pwm_get_raw_duty(enum pwm_channel ch)
 		 * so scale to 0 - 0xffff
 		 */
 		return DIV_ROUND_NEAREST(NPCX_DCR(mdl) * EC_PWM_MAX_DUTY,
-						pwm_res[ch]);
+					 pwm_res[ch]);
 }
 
 /**
@@ -206,22 +206,22 @@ void pwm_config(enum pwm_channel ch)
 
 	/* Set PWM heartbeat mode is no heartbeat */
 	SET_FIELD(NPCX_PWMCTL(mdl), NPCX_PWMCTL_HB_DC_CTL_FIELD,
-			NPCX_PWM_HBM_NORMAL);
+		  NPCX_PWM_HBM_NORMAL);
 
 	/* Select default CLK or LFCLK clock input to PWM module */
 	SET_FIELD(NPCX_PWMCTLEX(mdl), NPCX_PWMCTLEX_FCK_SEL_FIELD,
-			NPCX_PWM_CLOCK_APB2_LFCLK);
+		  NPCX_PWM_CLOCK_APB2_LFCLK);
 
 	/* Set PWM polarity normal first */
 	CLEAR_BIT(NPCX_PWMCTL(mdl), NPCX_PWMCTL_INVP);
 
 	/* Select PWM clock source */
 	UPDATE_BIT(NPCX_PWMCTL(mdl), NPCX_PWMCTL_CKSEL,
-			(pwm_channels[ch].flags & PWM_CONFIG_DSLEEP));
+		   (pwm_channels[ch].flags & PWM_CONFIG_DSLEEP));
 
 	/* Select PWM IO type */
 	UPDATE_BIT(NPCX_PWMCTLEX(mdl), NPCX_PWMCTLEX_OD_OUT,
-			(pwm_channels[ch].flags & PWM_CONFIG_OPEN_DRAIN));
+		   (pwm_channels[ch].flags & PWM_CONFIG_OPEN_DRAIN));
 
 	/* Set PWM operation frequency */
 	pwm_set_freq(ch, pwm_channels[ch].freq);
diff --git a/chip/npcx/pwm_chip.h b/chip/npcx/pwm_chip.h
index 7acfef81e5..714ecfb4a3 100644
--- a/chip/npcx/pwm_chip.h
+++ b/chip/npcx/pwm_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/npcx/registers-npcx5.h b/chip/npcx/registers-npcx5.h
index da0f215d0a..b7302bdd13 100644
--- a/chip/npcx/registers-npcx5.h
+++ b/chip/npcx/registers-npcx5.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,79 +19,87 @@
 #endif
 
 /* NPCX-IRQ numbers */
-#define NPCX_IRQ0_NOUSED		NPCX_IRQ_0
-#define NPCX_IRQ1_NOUSED		NPCX_IRQ_1
-#define NPCX_IRQ_KBSCAN			NPCX_IRQ_2
-#define NPCX_IRQ_PM_CHAN_OBE		NPCX_IRQ_3
-#define NPCX_IRQ_PECI			NPCX_IRQ_4
-#define NPCX_IRQ5_NOUSED		NPCX_IRQ_5
-#define NPCX_IRQ_PORT80			NPCX_IRQ_6
-#define NPCX_IRQ_MTC_WKINTAD_0		NPCX_IRQ_7
-#define NPCX_IRQ_MTC			NPCX_IRQ_MTC_WKINTAD_0
-#define NPCX_IRQ8_NOUSED		NPCX_IRQ_8
-#define NPCX_IRQ_MFT_1			NPCX_IRQ_9
-#define NPCX_IRQ_ADC			NPCX_IRQ_10
-#define NPCX_IRQ_WKINTEFGH_0		NPCX_IRQ_11
-#define NPCX_IRQ_GDMA			NPCX_IRQ_12
-#define NPCX_IRQ_SMB1			NPCX_IRQ_13
-#define NPCX_IRQ_SMB2			NPCX_IRQ_14
-#define NPCX_IRQ_WKINTC_0		NPCX_IRQ_15
-#define NPCX_IRQ16_NOUSED		NPCX_IRQ_16
-#define NPCX_IRQ_ITIM16_3		NPCX_IRQ_17
-#define NPCX_IRQ_SHI			NPCX_IRQ_18
-#define NPCX_IRQ_ESPI			NPCX_IRQ_18
-#define NPCX_IRQ19_NOUSED		NPCX_IRQ_19
-#define NPCX_IRQ20_NOUSED		NPCX_IRQ_20
-#define NPCX_IRQ_PS2			NPCX_IRQ_21
-#define NPCX_IRQ22_NOUSED		NPCX_IRQ_22
-#define NPCX_IRQ_MFT_2			NPCX_IRQ_23
-#define NPCX_IRQ_SHM			NPCX_IRQ_24
-#define NPCX_IRQ_KBC_IBF		NPCX_IRQ_25
-#define NPCX_IRQ_PM_CHAN_IBF		NPCX_IRQ_26
-#define NPCX_IRQ_ITIM16_2		NPCX_IRQ_27
-#define NPCX_IRQ_ITIM16_1		NPCX_IRQ_28
-#define NPCX_IRQ29_NOUSED		NPCX_IRQ_29
-#define NPCX_IRQ30_NOUSED		NPCX_IRQ_30
-#define NPCX_IRQ_TWD_WKINTB_0		NPCX_IRQ_31
-#define NPCX_IRQ32_NOUSED		NPCX_IRQ_32
-#define NPCX_IRQ_UART			NPCX_IRQ_33
-#define NPCX_IRQ34_NOUSED		NPCX_IRQ_34
-#define NPCX_IRQ35_NOUSED		NPCX_IRQ_35
-#define NPCX_IRQ_SMB3			NPCX_IRQ_36
-#define NPCX_IRQ_SMB4			NPCX_IRQ_37
-#define NPCX_IRQ38_NOUSED		NPCX_IRQ_38
-#define NPCX_IRQ39_NOUSED		NPCX_IRQ_39
-#define NPCX_IRQ40_NOUSED		NPCX_IRQ_40
-#define NPCX_IRQ_MFT_3			NPCX_IRQ_41
-#define NPCX_IRQ42_NOUSED		NPCX_IRQ_42
-#define NPCX_IRQ_ITIM16_4		NPCX_IRQ_43
-#define NPCX_IRQ_ITIM16_5		NPCX_IRQ_44
-#define NPCX_IRQ_ITIM16_6		NPCX_IRQ_45
-#define NPCX_IRQ_ITIM32			NPCX_IRQ_46
-#define NPCX_IRQ_WKINTA_1		NPCX_IRQ_47
-#define NPCX_IRQ_WKINTB_1		NPCX_IRQ_48
-#define NPCX_IRQ_KSI_WKINTC_1		NPCX_IRQ_49
-#define NPCX_IRQ_WKINTD_1		NPCX_IRQ_50
-#define NPCX_IRQ_WKINTE_1		NPCX_IRQ_51
-#define NPCX_IRQ_WKINTF_1		NPCX_IRQ_52
-#define NPCX_IRQ_WKINTG_1		NPCX_IRQ_53
-#define NPCX_IRQ_WKINTH_1		NPCX_IRQ_54
-#define NPCX_IRQ55_NOUSED		NPCX_IRQ_55
-#define NPCX_IRQ_KBC_OBE		NPCX_IRQ_56
-#define NPCX_IRQ_SPI			NPCX_IRQ_57
-#define NPCX_IRQ58_NOUSED		NPCX_IRQ_58
-#define NPCX_IRQ_WKINTFG_2		NPCX_IRQ_59
-#define NPCX_IRQ_WKINTA_2		NPCX_IRQ_60
-#define NPCX_IRQ_WKINTB_2		NPCX_IRQ_61
-#define NPCX_IRQ_WKINTC_2		NPCX_IRQ_62
-#define NPCX_IRQ_WKINTD_2		NPCX_IRQ_63
+#define NPCX_IRQ0_NOUSED NPCX_IRQ_0
+#define NPCX_IRQ1_NOUSED NPCX_IRQ_1
+#define NPCX_IRQ_KBSCAN NPCX_IRQ_2
+#define NPCX_IRQ_PM_CHAN_OBE NPCX_IRQ_3
+#define NPCX_IRQ_PECI NPCX_IRQ_4
+#define NPCX_IRQ5_NOUSED NPCX_IRQ_5
+#define NPCX_IRQ_PORT80 NPCX_IRQ_6
+#define NPCX_IRQ_MTC_WKINTAD_0 NPCX_IRQ_7
+#define NPCX_IRQ_MTC NPCX_IRQ_MTC_WKINTAD_0
+#define NPCX_IRQ8_NOUSED NPCX_IRQ_8
+#define NPCX_IRQ_MFT_1 NPCX_IRQ_9
+#define NPCX_IRQ_ADC NPCX_IRQ_10
+#define NPCX_IRQ_WKINTEFGH_0 NPCX_IRQ_11
+#define NPCX_IRQ_GDMA NPCX_IRQ_12
+#define NPCX_IRQ_SMB1 NPCX_IRQ_13
+#define NPCX_IRQ_SMB2 NPCX_IRQ_14
+#define NPCX_IRQ_WKINTC_0 NPCX_IRQ_15
+#define NPCX_IRQ16_NOUSED NPCX_IRQ_16
+#define NPCX_IRQ_ITIM16_3 NPCX_IRQ_17
+#define NPCX_IRQ_SHI NPCX_IRQ_18
+#define NPCX_IRQ_ESPI NPCX_IRQ_18
+#define NPCX_IRQ19_NOUSED NPCX_IRQ_19
+#define NPCX_IRQ20_NOUSED NPCX_IRQ_20
+#define NPCX_IRQ_PS2 NPCX_IRQ_21
+#define NPCX_IRQ22_NOUSED NPCX_IRQ_22
+#define NPCX_IRQ_MFT_2 NPCX_IRQ_23
+#define NPCX_IRQ_SHM NPCX_IRQ_24
+#define NPCX_IRQ_KBC_IBF NPCX_IRQ_25
+#define NPCX_IRQ_PM_CHAN_IBF NPCX_IRQ_26
+#define NPCX_IRQ_ITIM16_2 NPCX_IRQ_27
+#define NPCX_IRQ_ITIM16_1 NPCX_IRQ_28
+#define NPCX_IRQ29_NOUSED NPCX_IRQ_29
+#define NPCX_IRQ30_NOUSED NPCX_IRQ_30
+#define NPCX_IRQ_TWD_WKINTB_0 NPCX_IRQ_31
+#define NPCX_IRQ32_NOUSED NPCX_IRQ_32
+#define NPCX_IRQ_UART NPCX_IRQ_33
+#define NPCX_IRQ34_NOUSED NPCX_IRQ_34
+#define NPCX_IRQ35_NOUSED NPCX_IRQ_35
+#define NPCX_IRQ_SMB3 NPCX_IRQ_36
+#define NPCX_IRQ_SMB4 NPCX_IRQ_37
+#define NPCX_IRQ38_NOUSED NPCX_IRQ_38
+#define NPCX_IRQ39_NOUSED NPCX_IRQ_39
+#define NPCX_IRQ40_NOUSED NPCX_IRQ_40
+#define NPCX_IRQ_MFT_3 NPCX_IRQ_41
+#define NPCX_IRQ42_NOUSED NPCX_IRQ_42
+#define NPCX_IRQ_ITIM16_4 NPCX_IRQ_43
+#define NPCX_IRQ_ITIM16_5 NPCX_IRQ_44
+#define NPCX_IRQ_ITIM16_6 NPCX_IRQ_45
+#define NPCX_IRQ_ITIM32 NPCX_IRQ_46
+#define NPCX_IRQ_WKINTA_1 NPCX_IRQ_47
+#define NPCX_IRQ_WKINTB_1 NPCX_IRQ_48
+#define NPCX_IRQ_KSI_WKINTC_1 NPCX_IRQ_49
+#define NPCX_IRQ_WKINTD_1 NPCX_IRQ_50
+#define NPCX_IRQ_WKINTE_1 NPCX_IRQ_51
+#define NPCX_IRQ_WKINTF_1 NPCX_IRQ_52
+#define NPCX_IRQ_WKINTG_1 NPCX_IRQ_53
+#define NPCX_IRQ_WKINTH_1 NPCX_IRQ_54
+#define NPCX_IRQ55_NOUSED NPCX_IRQ_55
+#define NPCX_IRQ_KBC_OBE NPCX_IRQ_56
+#define NPCX_IRQ_SPI NPCX_IRQ_57
+#define NPCX_IRQ58_NOUSED NPCX_IRQ_58
+#define NPCX_IRQ_WKINTFG_2 NPCX_IRQ_59
+#define NPCX_IRQ_WKINTA_2 NPCX_IRQ_60
+#define NPCX_IRQ_WKINTB_2 NPCX_IRQ_61
+#define NPCX_IRQ_WKINTC_2 NPCX_IRQ_62
+#define NPCX_IRQ_WKINTD_2 NPCX_IRQ_63
 
 /* Modules Map */
-#define NPCX_ITIM32_BASE_ADDR		0x400BC000
-#define NPCX_CR_UART_BASE_ADDR(mdl)	(0x400C4000 + ((mdl) * 0x2000L))
-#define NPCX_SMB_BASE_ADDR(mdl)	(((mdl) < 2) ? \
-				(0x40009000 + ((mdl) * 0x2000L)) : \
-				(0x400C0000 + (((mdl) - 2) * 0x2000L)))
+
+/* Miscellaneous Device Control (MDC) registers */
+#define NPCX_FWCTRL REG8(NPCX_MDC_BASE_ADDR + 0x007)
+
+/* MDC register fields */
+#define NPCX_FWCTRL_RO_REGION 0
+#define NPCX_FWCTRL_FW_SLOT 1
+
+#define NPCX_ITIM32_BASE_ADDR 0x400BC000
+#define NPCX_CR_UART_BASE_ADDR(mdl) (0x400C4000 + ((mdl)*0x2000L))
+#define NPCX_SMB_BASE_ADDR(mdl)                         \
+	(((mdl) < 2) ? (0x40009000 + ((mdl)*0x2000L)) : \
+		       (0x400C0000 + (((mdl)-2) * 0x2000L)))
 
 enum {
 	NPCX_UART_PORT0 = 0, /* UART port 0 */
@@ -121,35 +129,39 @@ enum {
 	ALT_GROUP_COUNT
 };
 
-#define NPCX_DEVALT(n)			REG8(NPCX_SCFG_BASE_ADDR + 0x010 + (n))
+#define NPCX_DEVALT(n) REG8(NPCX_SCFG_BASE_ADDR + 0x010 + (n))
+
+#define NPCX_LV_GPIO_CTL(n) REG8(NPCX_SCFG_BASE_ADDR + 0x02A + (n))
 
-#define NPCX_LV_GPIO_CTL(n)		REG8(NPCX_SCFG_BASE_ADDR + 0x02A + (n))
+/* pin-mux for JTAG */
+#define NPCX_DEVALT5_NJEN1_EN 1
+#define NPCX_DEVALT5_NJEN0_EN 2
 
 /* pin-mux for I2C */
-#define NPCX_DEVALT2_I2C0_0_SL		0
-#define NPCX_DEVALT2_I2C0_1_SL		1
-#define NPCX_DEVALT2_I2C1_0_SL		2
-#define NPCX_DEVALT2_I2C2_0_SL		4
-#define NPCX_DEVALT2_I2C3_0_SL		6
+#define NPCX_DEVALT2_I2C0_0_SL 0
+#define NPCX_DEVALT2_I2C0_1_SL 1
+#define NPCX_DEVALT2_I2C1_0_SL 2
+#define NPCX_DEVALT2_I2C2_0_SL 4
+#define NPCX_DEVALT2_I2C3_0_SL 6
 
 /* pin-mux for UART */
-#define NPCX_DEVALTA_UART_SL1		7
-#define NPCX_DEVALTC_UART_SL2		0
+#define NPCX_DEVALTA_UART_SL1 7
+#define NPCX_DEVALTC_UART_SL2 0
 
 /* pin-mux for Misc. */
 /* External 32KHz crytal osc. input support */
-#define NPCX_DEVALTA_32KCLKIN_SL	3
+#define NPCX_DEVALTA_32KCLKIN_SL 3
 
 /* SMBus register fields */
-#define NPCX_SMBSEL_SMB0SEL		0
+#define NPCX_SMBSEL_SMB0SEL 0
 
 /* SMB enumeration: I2C port definitions. */
 enum {
-	NPCX_I2C_PORT0_0 = 0,	/* I2C port 0, bus 0 */
-	NPCX_I2C_PORT0_1,	/* I2C port 0, bus 1 */
-	NPCX_I2C_PORT1,		/* I2C port 1 */
-	NPCX_I2C_PORT2,		/* I2C port 2 */
-	NPCX_I2C_PORT3,		/* I2C port 3 */
+	NPCX_I2C_PORT0_0 = 0, /* I2C port 0, bus 0 */
+	NPCX_I2C_PORT0_1, /* I2C port 0, bus 1 */
+	NPCX_I2C_PORT1, /* I2C port 1 */
+	NPCX_I2C_PORT2, /* I2C port 2 */
+	NPCX_I2C_PORT3, /* I2C port 3 */
 	NPCX_I2C_COUNT,
 };
 
@@ -183,32 +195,31 @@ enum NPCX_PMC_PWDWN_CTL_T {
 	NPCX_PMC_PWDWN_CNT,
 };
 
-#define CGC_I2C_MASK			(BIT(NPCX_PWDWN_CTL3_SMB0_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB1_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB2_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB3_PD))
+#define CGC_I2C_MASK                                                   \
+	(BIT(NPCX_PWDWN_CTL3_SMB0_PD) | BIT(NPCX_PWDWN_CTL3_SMB1_PD) | \
+	 BIT(NPCX_PWDWN_CTL3_SMB2_PD) | BIT(NPCX_PWDWN_CTL3_SMB3_PD))
 
 /* BBRAM register fields */
 #define NPCX_BKUP_STS_ALL_MASK BIT(NPCX_BKUP_STS_IBBR)
-#define NPCX_BBRAM_SIZE			64 /* Size of BBRAM */
+#define NPCX_BBRAM_SIZE 64 /* Size of BBRAM */
 
 /* ITIM registers */
-#define NPCX_ITCNT8(n)			REG8(NPCX_ITIM_BASE_ADDR(n) + 0x000)
-#define NPCX_ITCNT16(n)			REG16(NPCX_ITIM_BASE_ADDR(n) + 0x002)
+#define NPCX_ITCNT8(n) REG8(NPCX_ITIM_BASE_ADDR(n) + 0x000)
+#define NPCX_ITCNT16(n) REG16(NPCX_ITIM_BASE_ADDR(n) + 0x002)
 /* ITIM32 registers */
-#define NPCX_ITCNT32			REG32(NPCX_ITIM32_BASE_ADDR + 0x008)
+#define NPCX_ITCNT32 REG32(NPCX_ITIM32_BASE_ADDR + 0x008)
 
 /* Timer counter register used for 1 micro-second system tick */
-#define NPCX_ITCNT_SYSTEM		NPCX_ITCNT32
+#define NPCX_ITCNT_SYSTEM NPCX_ITCNT32
 /* Timer counter register used for others */
-#define NPCX_ITCNT			NPCX_ITCNT16
+#define NPCX_ITCNT NPCX_ITCNT16
 
 /* ITIM module No. used for event */
-#define ITIM_EVENT_NO			ITIM16_1
+#define ITIM_EVENT_NO ITIM16_1
 /* ITIM module No. used for watchdog */
-#define ITIM_WDG_NO			ITIM16_5
+#define ITIM_WDG_NO ITIM16_5
 /* ITIM module No. used for 1 micro-second system tick */
-#define ITIM_SYSTEM_NO			ITIM32
+#define ITIM_SYSTEM_NO ITIM32
 
 /* ITIM enumeration */
 enum ITIM_MODULE_T {
@@ -223,11 +234,11 @@ enum ITIM_MODULE_T {
 };
 
 /* Serial Host Interface (SHI) Registers */
-#define NPCX_OBUF(n)			REG8(NPCX_SHI_BASE_ADDR + 0x020 + (n))
-#define NPCX_IBUF(n)			REG8(NPCX_SHI_BASE_ADDR + 0x060 + (n))
+#define NPCX_OBUF(n) REG8(NPCX_SHI_BASE_ADDR + 0x020 + (n))
+#define NPCX_IBUF(n) REG8(NPCX_SHI_BASE_ADDR + 0x060 + (n))
 
 /* Bit field manipulation for VWEVMS Value */
-#define VWEVMS_INTWK_EN			VWEVMS_INT_EN
+#define VWEVMS_INTWK_EN VWEVMS_INT_EN
 
 /* eSPI max supported frequency */
 enum {
@@ -241,35 +252,35 @@ enum {
 
 /* eSPI max frequency support per FMCLK */
 #if (FMCLK <= 33000000)
-#define NPCX_ESPI_MAXFREQ_MAX		NPCX_ESPI_MAXFREQ_33
+#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_33
 #elif (FMCLK <= 48000000)
-#define NPCX_ESPI_MAXFREQ_MAX		NPCX_ESPI_MAXFREQ_50
+#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_50
 #else
-#define NPCX_ESPI_MAXFREQ_MAX		NPCX_ESPI_MAXFREQ_66
+#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_66
 #endif
 
 /* MIWU registers */
-#define NPCX_WKEDG_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x00 + \
-					((n) * 2L) + ((n) < 5 ? 0 : 0x1E))
-#define NPCX_WKAEDG_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x01 + \
-					((n) * 2L) + ((n) < 5 ? 0 : 0x1E))
-#define NPCX_WKPND_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x0A + \
-					((n) * 4L) + ((n) < 5 ? 0 : 0x10))
-#define NPCX_WKPCL_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x0C + \
-					((n) * 4L) + ((n) < 5 ? 0 : 0x10))
-#define NPCX_WKEN_ADDR(port, n)		(NPCX_MIWU_BASE_ADDR(port) + 0x1E + \
-					((n) * 2L) + ((n) < 5 ? 0 : 0x12))
-#define NPCX_WKINEN_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x1F + \
-					((n) * 2L) + ((n) < 5 ? 0 : 0x12))
-#define NPCX_WKMOD_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x70 + (n))
-
-#define NPCX_WKEDG(port, n)		REG8(NPCX_WKEDG_ADDR(port, n))
-#define NPCX_WKAEDG(port, n)		REG8(NPCX_WKAEDG_ADDR(port, n))
-#define NPCX_WKPND(port, n)		REG8(NPCX_WKPND_ADDR(port, n))
-#define NPCX_WKPCL(port, n)		REG8(NPCX_WKPCL_ADDR(port, n))
-#define NPCX_WKEN(port, n)		REG8(NPCX_WKEN_ADDR(port, n))
-#define NPCX_WKINEN(port, n)		REG8(NPCX_WKINEN_ADDR(port, n))
-#define NPCX_WKMOD(port, n)		REG8(NPCX_WKMOD_ADDR(port, n))
+#define NPCX_WKEDG_ADDR(port, n) \
+	(NPCX_MIWU_BASE_ADDR(port) + 0x00 + ((n)*2L) + ((n) < 5 ? 0 : 0x1E))
+#define NPCX_WKAEDG_ADDR(port, n) \
+	(NPCX_MIWU_BASE_ADDR(port) + 0x01 + ((n)*2L) + ((n) < 5 ? 0 : 0x1E))
+#define NPCX_WKPND_ADDR(port, n) \
+	(NPCX_MIWU_BASE_ADDR(port) + 0x0A + ((n)*4L) + ((n) < 5 ? 0 : 0x10))
+#define NPCX_WKPCL_ADDR(port, n) \
+	(NPCX_MIWU_BASE_ADDR(port) + 0x0C + ((n)*4L) + ((n) < 5 ? 0 : 0x10))
+#define NPCX_WKEN_ADDR(port, n) \
+	(NPCX_MIWU_BASE_ADDR(port) + 0x1E + ((n)*2L) + ((n) < 5 ? 0 : 0x12))
+#define NPCX_WKINEN_ADDR(port, n) \
+	(NPCX_MIWU_BASE_ADDR(port) + 0x1F + ((n)*2L) + ((n) < 5 ? 0 : 0x12))
+#define NPCX_WKMOD_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x70 + (n))
+
+#define NPCX_WKEDG(port, n) REG8(NPCX_WKEDG_ADDR(port, n))
+#define NPCX_WKAEDG(port, n) REG8(NPCX_WKAEDG_ADDR(port, n))
+#define NPCX_WKPND(port, n) REG8(NPCX_WKPND_ADDR(port, n))
+#define NPCX_WKPCL(port, n) REG8(NPCX_WKPCL_ADDR(port, n))
+#define NPCX_WKEN(port, n) REG8(NPCX_WKEN_ADDR(port, n))
+#define NPCX_WKINEN(port, n) REG8(NPCX_WKINEN_ADDR(port, n))
+#define NPCX_WKMOD(port, n) REG8(NPCX_WKMOD_ADDR(port, n))
 
 /* UART registers and functions */
 #if NPCX_UART_MODULE2
@@ -277,22 +288,22 @@ enum {
  * To be used as 2nd parameter to NPCX_WK*() macro, table (1st parameter) is
  * always 1 == MIWU_TABLE_1.
  */
-#define NPCX_UART_WK_GROUP		6
-#define NPCX_UART_WK_BIT		4
-#define NPCX_UART_MIWU_IRQ		NPCX_IRQ_WKINTG_1
-#define NPCX_UART_DEVALT		NPCX_DEVALT(0x0C)
-#define NPCX_UART_DEVALT_SL		NPCX_DEVALTC_UART_SL2
-#define NPCX_UART_ALT_DEVALT		NPCX_DEVALT(0x0A)
-#define NPCX_UART_ALT_DEVALT_SL		NPCX_DEVALTA_UART_SL1
+#define NPCX_UART_WK_GROUP 6
+#define NPCX_UART_WK_BIT 4
+#define NPCX_UART_MIWU_IRQ NPCX_IRQ_WKINTG_1
+#define NPCX_UART_DEVALT NPCX_DEVALT(0x0C)
+#define NPCX_UART_DEVALT_SL NPCX_DEVALTC_UART_SL2
+#define NPCX_UART_ALT_DEVALT NPCX_DEVALT(0x0A)
+#define NPCX_UART_ALT_DEVALT_SL NPCX_DEVALTA_UART_SL1
 #else /* !NPCX_UART_MODULE2 */
 
-#define NPCX_UART_WK_GROUP		1
-#define NPCX_UART_WK_BIT		0
-#define NPCX_UART_MIWU_IRQ		NPCX_IRQ_WKINTB_1
-#define NPCX_UART_DEVALT		NPCX_DEVALT(0x0A)
-#define NPCX_UART_DEVALT_SL		NPCX_DEVALTA_UART_SL1
-#define NPCX_UART_ALT_DEVALT		NPCX_DEVALT(0x0C)
-#define NPCX_UART_ALT_DEVALT_SL		NPCX_DEVALTC_UART_SL2
+#define NPCX_UART_WK_GROUP 1
+#define NPCX_UART_WK_BIT 0
+#define NPCX_UART_MIWU_IRQ NPCX_IRQ_WKINTB_1
+#define NPCX_UART_DEVALT NPCX_DEVALT(0x0A)
+#define NPCX_UART_DEVALT_SL NPCX_DEVALTA_UART_SL1
+#define NPCX_UART_ALT_DEVALT NPCX_DEVALT(0x0C)
+#define NPCX_UART_ALT_DEVALT_SL NPCX_DEVALTC_UART_SL2
 #endif /* NPCX_UART_MODULE2 */
 
 /* This routine checks pending bit of GPIO wake-up functionality */
@@ -316,8 +327,7 @@ static inline void uart_clear_pending_wakeup(void)
 /* This routine enables wake-up functionality from GPIO on UART rx pin */
 static inline void uart_enable_wakeup(int enable)
 {
-	UPDATE_BIT(NPCX_WKEN(1, NPCX_UART_WK_GROUP), NPCX_UART_WK_BIT,
-		enable);
+	UPDATE_BIT(NPCX_WKEN(1, NPCX_UART_WK_GROUP), NPCX_UART_WK_BIT, enable);
 }
 
 /* This routine checks functionality is UART rx or not */
@@ -327,50 +337,50 @@ static inline int npcx_is_uart(void)
 }
 
 /* ADC Registers */
-#define NPCX_ADCSTS		REG16(NPCX_ADC_BASE_ADDR + 0x000)
-#define NPCX_ADCCNF		REG16(NPCX_ADC_BASE_ADDR + 0x002)
-#define NPCX_ATCTL		REG16(NPCX_ADC_BASE_ADDR + 0x004)
-#define NPCX_ASCADD		REG16(NPCX_ADC_BASE_ADDR + 0x006)
-#define NPCX_ADCCS		REG16(NPCX_ADC_BASE_ADDR + 0x008)
+#define NPCX_ADCSTS REG16(NPCX_ADC_BASE_ADDR + 0x000)
+#define NPCX_ADCCNF REG16(NPCX_ADC_BASE_ADDR + 0x002)
+#define NPCX_ATCTL REG16(NPCX_ADC_BASE_ADDR + 0x004)
+#define NPCX_ASCADD REG16(NPCX_ADC_BASE_ADDR + 0x006)
+#define NPCX_ADCCS REG16(NPCX_ADC_BASE_ADDR + 0x008)
 /* NOTE: These are 1-based for the threshold detectors. */
-#define NPCX_THRCTL(n)		REG16(NPCX_ADC_BASE_ADDR + 0x012 + (2L*(n)))
-#define NPCX_THRCTS		REG16(NPCX_ADC_BASE_ADDR + 0x01A)
-#define NPCX_THR_DCTL(n)	REG16(NPCX_ADC_BASE_ADDR + 0x038 + (2L*(n)))
+#define NPCX_THRCTL(n) REG16(NPCX_ADC_BASE_ADDR + 0x012 + (2L * (n)))
+#define NPCX_THRCTS REG16(NPCX_ADC_BASE_ADDR + 0x01A)
+#define NPCX_THR_DCTL(n) REG16(NPCX_ADC_BASE_ADDR + 0x038 + (2L * (n)))
 /* NOTE: This is 0-based for the ADC channels. */
-#define NPCX_CHNDAT(n)		REG16(NPCX_ADC_BASE_ADDR + 0x040 + (2L*(n)))
-#define NPCX_ADCCNF2		REG16(NPCX_ADC_BASE_ADDR + 0x020)
-#define NPCX_GENDLY		REG16(NPCX_ADC_BASE_ADDR + 0x022)
-#define NPCX_MEAST		REG16(NPCX_ADC_BASE_ADDR + 0x026)
+#define NPCX_CHNDAT(n) REG16(NPCX_ADC_BASE_ADDR + 0x040 + (2L * (n)))
+#define NPCX_ADCCNF2 REG16(NPCX_ADC_BASE_ADDR + 0x020)
+#define NPCX_GENDLY REG16(NPCX_ADC_BASE_ADDR + 0x022)
+#define NPCX_MEAST REG16(NPCX_ADC_BASE_ADDR + 0x026)
 
 /* ADC register fields */
-#define NPCX_ATCTL_SCLKDIV_FIELD	FIELD(0, 6)
-#define NPCX_ATCTL_DLY_FIELD		FIELD(8, 3)
-#define NPCX_ASCADD_SADDR_FIELD		FIELD(0, 5)
-#define NPCX_ADCSTS_EOCEV		0
-#define NPCX_ADCCNF_ADCMD_FIELD		FIELD(1, 2)
-#define NPCX_ADCCNF_ADCRPTC		3
-#define NPCX_ADCCNF_INTECEN		6
-#define NPCX_ADCCNF_START		4
-#define NPCX_ADCCNF_ADCEN		0
-#define NPCX_ADCCNF_STOP		11
-#define NPCX_CHNDAT_CHDAT_FIELD		FIELD(0, 10)
-#define NPCX_CHNDAT_NEW			15
-#define NPCX_THRCTL_THEN		15
-#define NPCX_THRCTL_L_H			14
-#define NPCX_THRCTL_CHNSEL		FIELD(10, 4)
-#define NPCX_THRCTL_THRVAL		FIELD(0, 10)
-#define NPCX_THRCTS_ADC_WKEN		15
-#define NPCX_THRCTS_THR3_IEN		10
-#define NPCX_THRCTS_THR2_IEN		9
-#define NPCX_THRCTS_THR1_IEN		8
-#define NPCX_THRCTS_ADC_EVENT		7
-#define NPCX_THRCTS_THR3_STS		2
-#define NPCX_THRCTS_THR2_STS		1
-#define NPCX_THRCTS_THR1_STS		0
-#define NPCX_THR_DCTL_THRD_EN		15
-#define NPCX_THR_DCTL_THR_DVAL		FIELD(0, 10)
-
-#define NPCX_ADC_THRESH1		1
-#define NPCX_ADC_THRESH2		2
-#define NPCX_ADC_THRESH3		3
-#define NPCX_ADC_THRESH_CNT		3
+#define NPCX_ATCTL_SCLKDIV_FIELD FIELD(0, 6)
+#define NPCX_ATCTL_DLY_FIELD FIELD(8, 3)
+#define NPCX_ASCADD_SADDR_FIELD FIELD(0, 5)
+#define NPCX_ADCSTS_EOCEV 0
+#define NPCX_ADCCNF_ADCMD_FIELD FIELD(1, 2)
+#define NPCX_ADCCNF_ADCRPTC 3
+#define NPCX_ADCCNF_INTECEN 6
+#define NPCX_ADCCNF_START 4
+#define NPCX_ADCCNF_ADCEN 0
+#define NPCX_ADCCNF_STOP 11
+#define NPCX_CHNDAT_CHDAT_FIELD FIELD(0, 10)
+#define NPCX_CHNDAT_NEW 15
+#define NPCX_THRCTL_THEN 15
+#define NPCX_THRCTL_L_H 14
+#define NPCX_THRCTL_CHNSEL FIELD(10, 4)
+#define NPCX_THRCTL_THRVAL FIELD(0, 10)
+#define NPCX_THRCTS_ADC_WKEN 15
+#define NPCX_THRCTS_THR3_IEN 10
+#define NPCX_THRCTS_THR2_IEN 9
+#define NPCX_THRCTS_THR1_IEN 8
+#define NPCX_THRCTS_ADC_EVENT 7
+#define NPCX_THRCTS_THR3_STS 2
+#define NPCX_THRCTS_THR2_STS 1
+#define NPCX_THRCTS_THR1_STS 0
+#define NPCX_THR_DCTL_THRD_EN 15
+#define NPCX_THR_DCTL_THR_DVAL FIELD(0, 10)
+
+#define NPCX_ADC_THRESH1 1
+#define NPCX_ADC_THRESH2 2
+#define NPCX_ADC_THRESH3 3
+#define NPCX_ADC_THRESH_CNT 3
diff --git a/chip/npcx/registers-npcx7.h b/chip/npcx/registers-npcx7.h
index 6fa10f5430..2a4334149f 100644
--- a/chip/npcx/registers-npcx7.h
+++ b/chip/npcx/registers-npcx7.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,98 +24,104 @@
 #endif
 
 /* NPCX-IRQ numbers */
-#define NPCX_IRQ0_NOUSED		NPCX_IRQ_0
-#define NPCX_IRQ1_NOUSED		NPCX_IRQ_1
-#define NPCX_IRQ_KBSCAN			NPCX_IRQ_2
-#define NPCX_IRQ_PM_CHAN_OBE		NPCX_IRQ_3
+#define NPCX_IRQ0_NOUSED NPCX_IRQ_0
+#define NPCX_IRQ1_NOUSED NPCX_IRQ_1
+#define NPCX_IRQ_KBSCAN NPCX_IRQ_2
+#define NPCX_IRQ_PM_CHAN_OBE NPCX_IRQ_3
 #ifdef NPCX_WOV_SUPPORT
-#define NPCX_IRQ4_NOUSED		NPCX_IRQ_4
+#define NPCX_IRQ4_NOUSED NPCX_IRQ_4
 #else
-#define NPCX_IRQ_PECI			NPCX_IRQ_4
+#define NPCX_IRQ_PECI NPCX_IRQ_4
 #endif
-#define NPCX_IRQ5_NOUSED		NPCX_IRQ_5
-#define NPCX_IRQ_PORT80			NPCX_IRQ_6
-#define NPCX_IRQ_MTC_WKINTAD_0		NPCX_IRQ_7
-#define NPCX_IRQ_MTC			NPCX_IRQ_MTC_WKINTAD_0
-#define NPCX_IRQ_SMB8			NPCX_IRQ_8
-#define NPCX_IRQ_MFT_1			NPCX_IRQ_9
-#define NPCX_IRQ_ADC			NPCX_IRQ_10
-#define NPCX_IRQ_WKINTEFGH_0		NPCX_IRQ_11
-#define NPCX_IRQ_GDMA			NPCX_IRQ_12
-#define NPCX_IRQ_SMB1			NPCX_IRQ_13
-#define NPCX_IRQ_SMB2			NPCX_IRQ_14
-#define NPCX_IRQ_WKINTC_0		NPCX_IRQ_15
-#define NPCX_IRQ_SMB7			NPCX_IRQ_16
-#define NPCX_IRQ_ITIM16_3		NPCX_IRQ_17
-#define NPCX_IRQ_SHI			NPCX_IRQ_18
-#define NPCX_IRQ_ESPI			NPCX_IRQ_18
-#define NPCX_IRQ_SMB5			NPCX_IRQ_19
-#define NPCX_IRQ_SMB6			NPCX_IRQ_20
-#define NPCX_IRQ_PS2			NPCX_IRQ_21
+#define NPCX_IRQ5_NOUSED NPCX_IRQ_5
+#define NPCX_IRQ_PORT80 NPCX_IRQ_6
+#define NPCX_IRQ_MTC_WKINTAD_0 NPCX_IRQ_7
+#define NPCX_IRQ_MTC NPCX_IRQ_MTC_WKINTAD_0
+#define NPCX_IRQ_SMB8 NPCX_IRQ_8
+#define NPCX_IRQ_MFT_1 NPCX_IRQ_9
+#define NPCX_IRQ_ADC NPCX_IRQ_10
+#define NPCX_IRQ_WKINTEFGH_0 NPCX_IRQ_11
+#define NPCX_IRQ_GDMA NPCX_IRQ_12
+#define NPCX_IRQ_SMB1 NPCX_IRQ_13
+#define NPCX_IRQ_SMB2 NPCX_IRQ_14
+#define NPCX_IRQ_WKINTC_0 NPCX_IRQ_15
+#define NPCX_IRQ_SMB7 NPCX_IRQ_16
+#define NPCX_IRQ_ITIM16_3 NPCX_IRQ_17
+#define NPCX_IRQ_SHI NPCX_IRQ_18
+#define NPCX_IRQ_ESPI NPCX_IRQ_18
+#define NPCX_IRQ_SMB5 NPCX_IRQ_19
+#define NPCX_IRQ_SMB6 NPCX_IRQ_20
+#define NPCX_IRQ_PS2 NPCX_IRQ_21
 #ifdef NPCX_WOV_SUPPORT
-#define NPCX_IRQ_WOV			NPCX_IRQ_22
+#define NPCX_IRQ_WOV NPCX_IRQ_22
 #else
-#define NPCX_IRQ22_NOUSED		NPCX_IRQ_22
+#define NPCX_IRQ22_NOUSED NPCX_IRQ_22
 #endif
-#define NPCX_IRQ_MFT_2			NPCX_IRQ_23
-#define NPCX_IRQ_SHM			NPCX_IRQ_24
-#define NPCX_IRQ_KBC_IBF		NPCX_IRQ_25
-#define NPCX_IRQ_PM_CHAN_IBF		NPCX_IRQ_26
-#define NPCX_IRQ_ITIM16_2		NPCX_IRQ_27
-#define NPCX_IRQ_ITIM16_1		NPCX_IRQ_28
-#define NPCX_IRQ29_NOUSED		NPCX_IRQ_29
-#define NPCX_IRQ30_NOUSED		NPCX_IRQ_30
-#define NPCX_IRQ_TWD_WKINTB_0		NPCX_IRQ_31
-#define NPCX_IRQ_UART2			NPCX_IRQ_32
-#define NPCX_IRQ_UART			NPCX_IRQ_33
-#define NPCX_IRQ34_NOUSED		NPCX_IRQ_34
-#define NPCX_IRQ35_NOUSED		NPCX_IRQ_35
-#define NPCX_IRQ_SMB3			NPCX_IRQ_36
-#define NPCX_IRQ_SMB4			NPCX_IRQ_37
-#define NPCX_IRQ38_NOUSED		NPCX_IRQ_38
-#define NPCX_IRQ39_NOUSED		NPCX_IRQ_39
-#define NPCX_IRQ40_NOUSED		NPCX_IRQ_40
-#define NPCX_IRQ_MFT_3			NPCX_IRQ_41
-#define NPCX_IRQ42_NOUSED		NPCX_IRQ_42
-#define NPCX_IRQ_ITIM16_4		NPCX_IRQ_43
-#define NPCX_IRQ_ITIM16_5		NPCX_IRQ_44
-#define NPCX_IRQ_ITIM16_6		NPCX_IRQ_45
-#define NPCX_IRQ_ITIM32			NPCX_IRQ_46
-#define NPCX_IRQ_WKINTA_1		NPCX_IRQ_47
-#define NPCX_IRQ_WKINTB_1		NPCX_IRQ_48
-#define NPCX_IRQ_KSI_WKINTC_1		NPCX_IRQ_49
-#define NPCX_IRQ_WKINTD_1		NPCX_IRQ_50
-#define NPCX_IRQ_WKINTE_1		NPCX_IRQ_51
-#define NPCX_IRQ_WKINTF_1		NPCX_IRQ_52
-#define NPCX_IRQ_WKINTG_1		NPCX_IRQ_53
-#define NPCX_IRQ_WKINTH_1		NPCX_IRQ_54
-#define NPCX_IRQ55_NOUSED		NPCX_IRQ_55
-#define NPCX_IRQ_KBC_OBE		NPCX_IRQ_56
-#define NPCX_IRQ_SPI			NPCX_IRQ_57
+#define NPCX_IRQ_MFT_2 NPCX_IRQ_23
+#define NPCX_IRQ_SHM NPCX_IRQ_24
+#define NPCX_IRQ_KBC_IBF NPCX_IRQ_25
+#define NPCX_IRQ_PM_CHAN_IBF NPCX_IRQ_26
+#define NPCX_IRQ_ITIM16_2 NPCX_IRQ_27
+#define NPCX_IRQ_ITIM16_1 NPCX_IRQ_28
+#define NPCX_IRQ29_NOUSED NPCX_IRQ_29
+#define NPCX_IRQ30_NOUSED NPCX_IRQ_30
+#define NPCX_IRQ_TWD_WKINTB_0 NPCX_IRQ_31
+#define NPCX_IRQ_UART2 NPCX_IRQ_32
+#define NPCX_IRQ_UART NPCX_IRQ_33
+#define NPCX_IRQ34_NOUSED NPCX_IRQ_34
+#define NPCX_IRQ35_NOUSED NPCX_IRQ_35
+#define NPCX_IRQ_SMB3 NPCX_IRQ_36
+#define NPCX_IRQ_SMB4 NPCX_IRQ_37
+#define NPCX_IRQ38_NOUSED NPCX_IRQ_38
+#define NPCX_IRQ39_NOUSED NPCX_IRQ_39
+#define NPCX_IRQ40_NOUSED NPCX_IRQ_40
+#define NPCX_IRQ_MFT_3 NPCX_IRQ_41
+#define NPCX_IRQ42_NOUSED NPCX_IRQ_42
+#define NPCX_IRQ_ITIM16_4 NPCX_IRQ_43
+#define NPCX_IRQ_ITIM16_5 NPCX_IRQ_44
+#define NPCX_IRQ_ITIM16_6 NPCX_IRQ_45
+#define NPCX_IRQ_ITIM32 NPCX_IRQ_46
+#define NPCX_IRQ_WKINTA_1 NPCX_IRQ_47
+#define NPCX_IRQ_WKINTB_1 NPCX_IRQ_48
+#define NPCX_IRQ_KSI_WKINTC_1 NPCX_IRQ_49
+#define NPCX_IRQ_WKINTD_1 NPCX_IRQ_50
+#define NPCX_IRQ_WKINTE_1 NPCX_IRQ_51
+#define NPCX_IRQ_WKINTF_1 NPCX_IRQ_52
+#define NPCX_IRQ_WKINTG_1 NPCX_IRQ_53
+#define NPCX_IRQ_WKINTH_1 NPCX_IRQ_54
+#define NPCX_IRQ55_NOUSED NPCX_IRQ_55
+#define NPCX_IRQ_KBC_OBE NPCX_IRQ_56
+#define NPCX_IRQ_SPI NPCX_IRQ_57
 #ifdef NPCX_ITIM64_SUPPORT
-#define NPCX_IRQ_ITIM64			NPCX_IRQ_58
+#define NPCX_IRQ_ITIM64 NPCX_IRQ_58
 #else
-#define NPCX_IRQ58_NOUSED		NPCX_IRQ_58
+#define NPCX_IRQ58_NOUSED NPCX_IRQ_58
 #endif
-#define NPCX_IRQ_WKINTFG_2		NPCX_IRQ_59
-#define NPCX_IRQ_WKINTA_2		NPCX_IRQ_60
-#define NPCX_IRQ_WKINTB_2		NPCX_IRQ_61
-#define NPCX_IRQ_WKINTC_2		NPCX_IRQ_62
-#define NPCX_IRQ_WKINTD_2		NPCX_IRQ_63
+#define NPCX_IRQ_WKINTFG_2 NPCX_IRQ_59
+#define NPCX_IRQ_WKINTA_2 NPCX_IRQ_60
+#define NPCX_IRQ_WKINTB_2 NPCX_IRQ_61
+#define NPCX_IRQ_WKINTC_2 NPCX_IRQ_62
+#define NPCX_IRQ_WKINTD_2 NPCX_IRQ_63
 
 /* Modules Map */
-#define NPCX_ITIM32_BASE_ADDR		0x400BC000
-#define NPCX_CR_UART_BASE_ADDR(mdl)	(0x400C4000 + ((mdl) * 0x2000L))
-#define NPCX_SMB_BASE_ADDR(mdl)		(((mdl) < 2) ? \
-				(0x40009000 +	((mdl) * 0x2000L)) : \
-				((mdl) < 4) ? \
-				(0x400C0000 + (((mdl) - 2) * 0x2000L)) : \
-				((mdl) == 4) ? \
-				(0x40008000) : \
-				(0x40017000 + (((mdl) - 5) * 0x1000L)))
-
-#define NPCX_HFCBCD1			REG8(NPCX_HFCG_BASE_ADDR + 0x012)
-#define NPCX_HFCBCD2			REG8(NPCX_HFCG_BASE_ADDR + 0x014)
+
+/* Miscellaneous Device Control (MDC) registers */
+#define NPCX_FWCTRL REG8(NPCX_MDC_BASE_ADDR + 0x007)
+
+/* MDC register fields */
+#define NPCX_FWCTRL_RO_REGION 0
+#define NPCX_FWCTRL_FW_SLOT 1
+
+#define NPCX_ITIM32_BASE_ADDR 0x400BC000
+#define NPCX_CR_UART_BASE_ADDR(mdl) (0x400C4000 + ((mdl)*0x2000L))
+#define NPCX_SMB_BASE_ADDR(mdl)                                \
+	(((mdl) < 2)  ? (0x40009000 + ((mdl)*0x2000L)) :       \
+	 ((mdl) < 4)  ? (0x400C0000 + (((mdl)-2) * 0x2000L)) : \
+	 ((mdl) == 4) ? (0x40008000) :                         \
+			(0x40017000 + (((mdl)-5) * 0x1000L)))
+
+#define NPCX_HFCBCD1 REG8(NPCX_HFCG_BASE_ADDR + 0x012)
+#define NPCX_HFCBCD2 REG8(NPCX_HFCG_BASE_ADDR + 0x014)
 
 enum {
 	NPCX_UART_PORT0 = 0, /* UART port 0 */
@@ -127,44 +133,44 @@ enum {
 
 #ifdef NPCX_UART_FIFO_SUPPORT
 /* UART registers only used for FIFO mode */
-#define NPCX_UFTSTS(n)			REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x020)
-#define NPCX_UFRSTS(n)			REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x022)
-#define NPCX_UFTCTL(n)			REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x024)
-#define NPCX_UFRCTL(n)			REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x026)
+#define NPCX_UFTSTS(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x020)
+#define NPCX_UFRSTS(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x022)
+#define NPCX_UFTCTL(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x024)
+#define NPCX_UFRCTL(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x026)
 
 /* UART FIFO register fields */
-#define NPCX_UMDSL_FIFO_MD		0
-
-#define NPCX_UFTSTS_TEMPTY_LVL		FIELD(0, 5)
-#define NPCX_UFTSTS_TEMPTY_LVL_STS	5
-#define NPCX_UFTSTS_TFIFO_EMPTY_STS	6
-#define NPCX_UFTSTS_NXMIP		7
-
-#define NPCX_UFRSTS_RFULL_LVL_STS	5
-#define NPCX_UFRSTS_RFIFO_NEMPTY_STS	6
-#define NPCX_UFRSTS_ERR			7
-
-#define NPCX_UFTCTL_TEMPTY_LVL_SEL	FIELD(0, 5)
-#define NPCX_UFTCTL_TEMPTY_LVL_EN	5
-#define NPCX_UFTCTL_TEMPTY_EN		6
-#define NPCX_UFTCTL_NXMIPEN		7
-
-#define NPCX_UFRCTL_RFULL_LVL_SEL	FIELD(0, 5)
-#define NPCX_UFRCTL_RFULL_LVL_EN	5
-#define NPCX_UFRCTL_RNEMPTY_EN		6
-#define NPCX_UFRCTL_ERR_EN		7
+#define NPCX_UMDSL_FIFO_MD 0
+
+#define NPCX_UFTSTS_TEMPTY_LVL FIELD(0, 5)
+#define NPCX_UFTSTS_TEMPTY_LVL_STS 5
+#define NPCX_UFTSTS_TFIFO_EMPTY_STS 6
+#define NPCX_UFTSTS_NXMIP 7
+
+#define NPCX_UFRSTS_RFULL_LVL_STS 5
+#define NPCX_UFRSTS_RFIFO_NEMPTY_STS 6
+#define NPCX_UFRSTS_ERR 7
+
+#define NPCX_UFTCTL_TEMPTY_LVL_SEL FIELD(0, 5)
+#define NPCX_UFTCTL_TEMPTY_LVL_EN 5
+#define NPCX_UFTCTL_TEMPTY_EN 6
+#define NPCX_UFTCTL_NXMIPEN 7
+
+#define NPCX_UFRCTL_RFULL_LVL_SEL FIELD(0, 5)
+#define NPCX_UFRCTL_RFULL_LVL_EN 5
+#define NPCX_UFRCTL_RNEMPTY_EN 6
+#define NPCX_UFRCTL_ERR_EN 7
 #endif
 
 /* KBSCAN register fields */
-#define NPCX_KBHDRV_FIELD		FIELD(6, 2)
+#define NPCX_KBHDRV_FIELD FIELD(6, 2)
 
 /* GLUE registers */
 #ifdef NPCX_PSL_MODE_SUPPORT
-#define NPCX_GLUE_PSL_CTS		REG8(NPCX_GLUE_REGS_BASE + 0x027)
+#define NPCX_GLUE_PSL_CTS REG8(NPCX_GLUE_REGS_BASE + 0x027)
 #endif
 
 /* GPIO registers */
-#define NPCX_PLOCK_CTL(n)		REG8(NPCX_GPIO_BASE_ADDR(n) + 0x007)
+#define NPCX_PLOCK_CTL(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x007)
 
 /* System Configuration (SCFG) Registers */
 
@@ -189,108 +195,112 @@ enum {
 	ALT_GROUP_COUNT
 };
 
-#define NPCX_DEVALT(n)			REG8(NPCX_SCFG_BASE_ADDR + 0x010 + (n))
+#define NPCX_DEVALT(n) REG8(NPCX_SCFG_BASE_ADDR + 0x010 + (n))
 
-#define NPCX_LV_GPIO_CTL_ADDR(n)	(((n) < 5) ? \
-					(NPCX_SCFG_BASE_ADDR + 0x02A + (n)) :\
-					(NPCX_SCFG_BASE_ADDR + 0x026))
-#define NPCX_LV_GPIO_CTL(n)		REG8(NPCX_LV_GPIO_CTL_ADDR(n))
+#define NPCX_LV_GPIO_CTL_ADDR(n)                           \
+	(((n) < 5) ? (NPCX_SCFG_BASE_ADDR + 0x02A + (n)) : \
+		     (NPCX_SCFG_BASE_ADDR + 0x026))
+#define NPCX_LV_GPIO_CTL(n) REG8(NPCX_LV_GPIO_CTL_ADDR(n))
 
 /* pin-mux for I2C */
-#define NPCX_DEVALT2_I2C0_0_SL		0
-#define NPCX_DEVALT2_I2C7_0_SL		1
-#define NPCX_DEVALT2_I2C1_0_SL		2
-#define NPCX_DEVALT2_I2C6_0_SL		3
-#define NPCX_DEVALT2_I2C2_0_SL		4
-#define NPCX_DEVALT2_I2C5_0_SL		5
-#define NPCX_DEVALT2_I2C3_0_SL		6
-#define NPCX_DEVALT2_I2C4_0_SL		7
-#define NPCX_DEVALT6_I2C6_1_SL		5
-#define NPCX_DEVALT6_I2C5_1_SL		6
-#define NPCX_DEVALT6_I2C4_1_SL		7
+#define NPCX_DEVALT2_I2C0_0_SL 0
+#define NPCX_DEVALT2_I2C7_0_SL 1
+#define NPCX_DEVALT2_I2C1_0_SL 2
+#define NPCX_DEVALT2_I2C6_0_SL 3
+#define NPCX_DEVALT2_I2C2_0_SL 4
+#define NPCX_DEVALT2_I2C5_0_SL 5
+#define NPCX_DEVALT2_I2C3_0_SL 6
+#define NPCX_DEVALT2_I2C4_0_SL 7
+#define NPCX_DEVALT6_I2C6_1_SL 5
+#define NPCX_DEVALT6_I2C5_1_SL 6
+#define NPCX_DEVALT6_I2C4_1_SL 7
+
+/* pin-mux for JTAG */
+#define NPCX_DEVALT5_NJEN1_EN 1
+#define NPCX_DEVALT5_NJEN0_EN 2
 
 /* pin-mux for ADC */
-#define NPCX_DEVALTF_ADC5_SL		0
-#define NPCX_DEVALTF_ADC6_SL		1
-#define NPCX_DEVALTF_ADC7_SL		2
-#define NPCX_DEVALTF_ADC8_SL		3
-#define NPCX_DEVALTF_ADC9_SL		4
+#define NPCX_DEVALTF_ADC5_SL 0
+#define NPCX_DEVALTF_ADC6_SL 1
+#define NPCX_DEVALTF_ADC7_SL 2
+#define NPCX_DEVALTF_ADC8_SL 3
+#define NPCX_DEVALTF_ADC9_SL 4
 
 /* pin-mux for PSL */
 #ifdef NPCX_PSL_MODE_SUPPORT
-#define NPCX_DEVALTD_PSL_IN1_AHI	0
-#define NPCX_DEVALTD_NPSL_IN1_SL	1
-#define NPCX_DEVALTD_PSL_IN2_AHI	2
-#define NPCX_DEVALTD_NPSL_IN2_SL	3
-#define NPCX_DEVALTD_PSL_IN3_AHI	4
-#define NPCX_DEVALTD_PSL_IN3_SL		5
-#define NPCX_DEVALTD_PSL_IN4_AHI	6
-#define NPCX_DEVALTD_PSL_IN4_SL		7
+#define NPCX_DEVALTD_PSL_IN1_AHI 0
+#define NPCX_DEVALTD_NPSL_IN1_SL 1
+#define NPCX_DEVALTD_PSL_IN2_AHI 2
+#define NPCX_DEVALTD_NPSL_IN2_SL 3
+#define NPCX_DEVALTD_PSL_IN3_AHI 4
+#define NPCX_DEVALTD_PSL_IN3_SL 5
+#define NPCX_DEVALTD_PSL_IN4_AHI 6
+#define NPCX_DEVALTD_PSL_IN4_SL 7
 #endif
 
 #ifdef CHIP_VARIANT_NPCX7M6G
 /* External 32KHz crytal osc. input support */
-#define NPCX_DEVALTA_32KCLKIN_SL	3
+#define NPCX_DEVALTA_32KCLKIN_SL 3
 #endif
 
 /* pin-mux for UART */
-#define NPCX_DEVALTA_UART_SL1		7
-#define NPCX_DEVALTC_UART_SL2		0
+#define NPCX_DEVALTA_UART_SL1 7
+#define NPCX_DEVALTC_UART_SL2 0
 #ifdef NPCX_SECOND_UART
 /* Secondary UART selection */
-#define NPCX_DEVALTA_UART2_SL		5
+#define NPCX_DEVALTA_UART2_SL 5
 #endif
 
 /* SHI module version 2 enable bit */
-#define NPCX_DEVALTF_SHI_NEW		7
+#define NPCX_DEVALTF_SHI_NEW 7
 
 #ifdef NPCX_WOV_SUPPORT
 /* pin-mux for WoV */
-#define NPCX_DEVALTE_WOV_SL		0
-#define NPCX_DEVALTE_I2S_SL		1
-#define NPCX_DEVALTE_DMCLK_FAST		2
+#define NPCX_DEVALTE_WOV_SL 0
+#define NPCX_DEVALTE_I2S_SL 1
+#define NPCX_DEVALTE_DMCLK_FAST 2
 #endif
 
 /* SMBus register fields */
-#define NPCX_SMBSEL_SMB4SEL		4
-#define NPCX_SMBSEL_SMB5SEL		5
-#define NPCX_SMBSEL_SMB6SEL		6
+#define NPCX_SMBSEL_SMB4SEL 4
+#define NPCX_SMBSEL_SMB5SEL 5
+#define NPCX_SMBSEL_SMB6SEL 6
 
-/* SMB enumeration: I2C port definitions. */
+/* SMB enumeration: I2C port definitions */
 enum {
-	NPCX_I2C_PORT0_0 = 0,	/* I2C port 0, bus 0 */
-	NPCX_I2C_PORT1_0,	/* I2C port 1, bus 0 */
-	NPCX_I2C_PORT2_0,	/* I2C port 2, bus 0 */
-	NPCX_I2C_PORT3_0,	/* I2C port 3, bus 0 */
+	NPCX_I2C_PORT0_0 = 0, /* I2C port 0, bus 0 */
+	NPCX_I2C_PORT1_0, /* I2C port 1, bus 0 */
+	NPCX_I2C_PORT2_0, /* I2C port 2, bus 0 */
+	NPCX_I2C_PORT3_0, /* I2C port 3, bus 0 */
 #ifdef CHIP_VARIANT_NPCX7M6G
-	NPCX_I2C_PORT4_0,	/* I2C port 4, bus 0 */
+	NPCX_I2C_PORT4_0, /* I2C port 4, bus 0 */
 #endif
-	NPCX_I2C_PORT4_1,	/* I2C port 4, bus 1 */
-	NPCX_I2C_PORT5_0,	/* I2C port 5, bus 0 */
-	NPCX_I2C_PORT5_1,	/* I2C port 5, bus 1 */
-	NPCX_I2C_PORT6_0,	/* I2C port 6, bus 0 */
-	NPCX_I2C_PORT6_1,	/* I2C port 6, bus 1 */
-	NPCX_I2C_PORT7_0,	/* I2C port 7, bus 0 */
+	NPCX_I2C_PORT4_1, /* I2C port 4, bus 1 */
+	NPCX_I2C_PORT5_0, /* I2C port 5, bus 0 */
+	NPCX_I2C_PORT5_1, /* I2C port 5, bus 1 */
+	NPCX_I2C_PORT6_0, /* I2C port 6, bus 0 */
+	NPCX_I2C_PORT6_1, /* I2C port 6, bus 1 */
+	NPCX_I2C_PORT7_0, /* I2C port 7, bus 0 */
 	NPCX_I2C_COUNT,
 };
 
 /* Power Management Controller (PMC) Registers */
-#define NPCX_FMUL_WIN_DLY	REG8(NPCX_PMC_BASE_ADDR + 0x010)
-#define NPCX_RAM_PD(offset)	REG8(NPCX_PMC_BASE_ADDR + 0x020 + (offset))
+#define NPCX_FMUL_WIN_DLY REG8(NPCX_PMC_BASE_ADDR + 0x010)
+#define NPCX_RAM_PD(offset) REG8(NPCX_PMC_BASE_ADDR + 0x020 + (offset))
 
 /* PMC register fields */
-#define NPCX_PWDWN_CTL3_SMB4_PD		4
-#define NPCX_PWDWN_CTL7_SMB5_PD		0
-#define NPCX_PWDWN_CTL7_SMB6_PD		1
-#define NPCX_PWDWN_CTL7_SMB7_PD		2
+#define NPCX_PWDWN_CTL3_SMB4_PD 4
+#define NPCX_PWDWN_CTL7_SMB5_PD 0
+#define NPCX_PWDWN_CTL7_SMB6_PD 1
+#define NPCX_PWDWN_CTL7_SMB7_PD 2
 #ifdef NPCX_ITIM64_SUPPORT
-#define NPCX_PWDWN_CTL7_ITIM64_PD	5
+#define NPCX_PWDWN_CTL7_ITIM64_PD 5
 #endif
 #ifdef NPCX_SECOND_UART
-#define NPCX_PWDWN_CTL7_UART2_PD	6
+#define NPCX_PWDWN_CTL7_UART2_PD 6
 #endif
 #ifdef NPCX_WOV_SUPPORT
-#define NPCX_PWDWN_CTL7_WOV_PD		7
+#define NPCX_PWDWN_CTL7_WOV_PD 7
 #endif
 
 /*
@@ -316,7 +326,7 @@ enum {
 	CGC_OFFSET_UART2 = 6,
 #endif
 #ifdef NPCX_WOV_SUPPORT
-	CGC_OFFSET_WOV	= 6,
+	CGC_OFFSET_WOV = 6,
 #endif
 };
 
@@ -331,53 +341,52 @@ enum NPCX_PMC_PWDWN_CTL_T {
 	NPCX_PMC_PWDWN_CNT,
 };
 
-#define CGC_I2C_MASK			(BIT(NPCX_PWDWN_CTL3_SMB0_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB1_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB2_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB3_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB4_PD))
-#define CGC_I2C_MASK2			(BIT(NPCX_PWDWN_CTL7_SMB5_PD) | \
-					BIT(NPCX_PWDWN_CTL7_SMB6_PD) | \
-					BIT(NPCX_PWDWN_CTL7_SMB7_PD))
+#define CGC_I2C_MASK                                                   \
+	(BIT(NPCX_PWDWN_CTL3_SMB0_PD) | BIT(NPCX_PWDWN_CTL3_SMB1_PD) | \
+	 BIT(NPCX_PWDWN_CTL3_SMB2_PD) | BIT(NPCX_PWDWN_CTL3_SMB3_PD) | \
+	 BIT(NPCX_PWDWN_CTL3_SMB4_PD))
+#define CGC_I2C_MASK2                                                  \
+	(BIT(NPCX_PWDWN_CTL7_SMB5_PD) | BIT(NPCX_PWDWN_CTL7_SMB6_PD) | \
+	 BIT(NPCX_PWDWN_CTL7_SMB7_PD))
 #ifdef NPCX_SECOND_UART
-#define CGC_UART2_MASK			BIT(NPCX_PWDWN_CTL7_UART2_PD)
+#define CGC_UART2_MASK BIT(NPCX_PWDWN_CTL7_UART2_PD)
 #endif
 #ifdef NPCX_WOV_SUPPORT
-#define CGC_WOV_MASK			BIT(NPCX_PWDWN_CTL7_WOV_PD)
+#define CGC_WOV_MASK BIT(NPCX_PWDWN_CTL7_WOV_PD)
 #endif
 
 /* BBRAM register fields */
-#if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) || \
+#if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) ||     \
 	defined(CHIP_VARIANT_NPCX7M7FC) || defined(CHIP_VARIANT_NPCX7M7WB) || \
 	defined(CHIP_VARIANT_NPCX7M7WC)
-#define NPCX_BKUP_STS_VSBY_STS		1
-#define NPCX_BKUP_STS_VCC1_STS		0
-#define NPCX_BKUP_STS_ALL_MASK \
+#define NPCX_BKUP_STS_VSBY_STS 1
+#define NPCX_BKUP_STS_VCC1_STS 0
+#define NPCX_BKUP_STS_ALL_MASK                                   \
 	(BIT(NPCX_BKUP_STS_IBBR) | BIT(NPCX_BKUP_STS_VSBY_STS) | \
-	BIT(NPCX_BKUP_STS_VCC1_STS))
-#define NPCX_BBRAM_SIZE			128 /* Size of BBRAM */
+	 BIT(NPCX_BKUP_STS_VCC1_STS))
+#define NPCX_BBRAM_SIZE 128 /* Size of BBRAM */
 #else
 #define NPCX_BKUP_STS_ALL_MASK BIT(NPCX_BKUP_STS_IBBR)
-#define NPCX_BBRAM_SIZE			64 /* Size of BBRAM */
+#define NPCX_BBRAM_SIZE 64 /* Size of BBRAM */
 #endif
 
 /* ITIM16 registers */
-#define NPCX_ITCNT8(n)			REG8(NPCX_ITIM_BASE_ADDR(n) + 0x000)
-#define NPCX_ITCNT16(n)			REG16(NPCX_ITIM_BASE_ADDR(n) + 0x002)
+#define NPCX_ITCNT8(n) REG8(NPCX_ITIM_BASE_ADDR(n) + 0x000)
+#define NPCX_ITCNT16(n) REG16(NPCX_ITIM_BASE_ADDR(n) + 0x002)
 /* ITIM32 registers */
-#define NPCX_ITCNT32			REG32(NPCX_ITIM32_BASE_ADDR + 0x008)
+#define NPCX_ITCNT32 REG32(NPCX_ITIM32_BASE_ADDR + 0x008)
 
 /* Timer counter register used for 1 micro-second system tick */
-#define NPCX_ITCNT_SYSTEM		NPCX_ITCNT32
+#define NPCX_ITCNT_SYSTEM NPCX_ITCNT32
 /* Timer counter register used for others */
-#define NPCX_ITCNT			NPCX_ITCNT16
+#define NPCX_ITCNT NPCX_ITCNT16
 
 /* ITIM module No. used for event */
-#define ITIM_EVENT_NO			ITIM16_1
+#define ITIM_EVENT_NO ITIM16_1
 /* ITIM module No. used for watchdog */
-#define ITIM_WDG_NO			ITIM16_5
+#define ITIM_WDG_NO ITIM16_5
 /* ITIM module No. used for 1 micro-second system tick */
-#define ITIM_SYSTEM_NO			ITIM32
+#define ITIM_SYSTEM_NO ITIM32
 
 /* ITIM enumeration */
 enum ITIM_MODULE_T {
@@ -392,56 +401,56 @@ enum ITIM_MODULE_T {
 };
 
 /* Serial Host Interface (SHI) Registers - only available on SHI Version 2 */
-#define NPCX_SHICFG3			REG8(NPCX_SHI_BASE_ADDR + 0x00C)
-#define NPCX_SHICFG4			REG8(NPCX_SHI_BASE_ADDR + 0x00D)
-#define NPCX_SHICFG5			REG8(NPCX_SHI_BASE_ADDR + 0x00E)
-#define NPCX_EVSTAT2			REG8(NPCX_SHI_BASE_ADDR + 0x00F)
-#define NPCX_EVENABLE2			REG8(NPCX_SHI_BASE_ADDR + 0x010)
-#define NPCX_OBUF(n)			REG8(NPCX_SHI_BASE_ADDR + 0x020 + (n))
-#define NPCX_IBUF(n)			REG8(NPCX_SHI_BASE_ADDR + 0x0A0 + (n))
+#define NPCX_SHICFG3 REG8(NPCX_SHI_BASE_ADDR + 0x00C)
+#define NPCX_SHICFG4 REG8(NPCX_SHI_BASE_ADDR + 0x00D)
+#define NPCX_SHICFG5 REG8(NPCX_SHI_BASE_ADDR + 0x00E)
+#define NPCX_EVSTAT2 REG8(NPCX_SHI_BASE_ADDR + 0x00F)
+#define NPCX_EVENABLE2 REG8(NPCX_SHI_BASE_ADDR + 0x010)
+#define NPCX_OBUF(n) REG8(NPCX_SHI_BASE_ADDR + 0x020 + (n))
+#define NPCX_IBUF(n) REG8(NPCX_SHI_BASE_ADDR + 0x0A0 + (n))
 
 /* SHI register fields */
-#define NPCX_SHICFG3_OBUFLVLDIS		7
-#define NPCX_SHICFG4_IBUFLVLDIS		7
-#define NPCX_SHICFG5_IBUFLVL2		FIELD(0, 6)
-#define NPCX_SHICFG5_IBUFLVL2DIS	7
-#define NPCX_EVSTAT2_IBHF2		0
-#define NPCX_EVSTAT2_CSNRE		1
-#define NPCX_EVSTAT2_CSNFE		2
-#define NPCX_EVENABLE2_IBHF2EN		0
-#define NPCX_EVENABLE2_CSNREEN		1
-#define NPCX_EVENABLE2_CSNFEEN		2
+#define NPCX_SHICFG3_OBUFLVLDIS 7
+#define NPCX_SHICFG4_IBUFLVLDIS 7
+#define NPCX_SHICFG5_IBUFLVL2 FIELD(0, 6)
+#define NPCX_SHICFG5_IBUFLVL2DIS 7
+#define NPCX_EVSTAT2_IBHF2 0
+#define NPCX_EVSTAT2_CSNRE 1
+#define NPCX_EVSTAT2_CSNFE 2
+#define NPCX_EVENABLE2_IBHF2EN 0
+#define NPCX_EVENABLE2_CSNREEN 1
+#define NPCX_EVENABLE2_CSNFEEN 2
 
 /* eSPI register fields */
-#define NPCX_ESPIIE_BMTXDONEIE		19
-#define NPCX_ESPIIE_PBMRXIE		20
-#define NPCX_ESPIIE_PMSGRXIE		21
-#define NPCX_ESPIIE_BMBURSTERRIE	22
-#define NPCX_ESPIIE_BMBURSTDONEIE	23
-
-#define NPCX_ESPIWE_PBMRXWE		20
-#define NPCX_ESPIWE_PMSGRXWE		21
-
-#define NPCX_ESPISTS_VWUPDW		17
-#define NPCX_ESPISTS_BMTXDONE		19
-#define NPCX_ESPISTS_PBMRX		20
-#define NPCX_ESPISTS_PMSGRX		21
-#define NPCX_ESPISTS_BMBURSTERR		22
-#define NPCX_ESPISTS_BMBURSTDONE	23
-#define NPCX_ESPISTS_ESPIRST_LVL	24
-
-#define ESPIIE_BMTXDONE			BIT(NPCX_ESPIIE_BMTXDONEIE)
-#define ESPIIE_PBMRX			BIT(NPCX_ESPIIE_PBMRXIE)
-#define ESPIIE_PMSGRX			BIT(NPCX_ESPIIE_PMSGRXIE)
-#define ESPIIE_BMBURSTERR		BIT(NPCX_ESPIIE_BMBURSTERRIE)
-#define ESPIIE_BMBURSTDONE		BIT(NPCX_ESPIIE_BMBURSTDONEIE)
-
-#define ESPIWE_PBMRX			BIT(NPCX_ESPIWE_PBMRXWE)
-#define ESPIWE_PMSGRX			BIT(NPCX_ESPIWE_PMSGRXWE)
+#define NPCX_ESPIIE_BMTXDONEIE 19
+#define NPCX_ESPIIE_PBMRXIE 20
+#define NPCX_ESPIIE_PMSGRXIE 21
+#define NPCX_ESPIIE_BMBURSTERRIE 22
+#define NPCX_ESPIIE_BMBURSTDONEIE 23
+
+#define NPCX_ESPIWE_PBMRXWE 20
+#define NPCX_ESPIWE_PMSGRXWE 21
+
+#define NPCX_ESPISTS_VWUPDW 17
+#define NPCX_ESPISTS_BMTXDONE 19
+#define NPCX_ESPISTS_PBMRX 20
+#define NPCX_ESPISTS_PMSGRX 21
+#define NPCX_ESPISTS_BMBURSTERR 22
+#define NPCX_ESPISTS_BMBURSTDONE 23
+#define NPCX_ESPISTS_ESPIRST_LVL 24
+
+#define ESPIIE_BMTXDONE BIT(NPCX_ESPIIE_BMTXDONEIE)
+#define ESPIIE_PBMRX BIT(NPCX_ESPIIE_PBMRXIE)
+#define ESPIIE_PMSGRX BIT(NPCX_ESPIIE_PMSGRXIE)
+#define ESPIIE_BMBURSTERR BIT(NPCX_ESPIIE_BMBURSTERRIE)
+#define ESPIIE_BMBURSTDONE BIT(NPCX_ESPIIE_BMBURSTDONEIE)
+
+#define ESPIWE_PBMRX BIT(NPCX_ESPIWE_PBMRXWE)
+#define ESPIWE_PMSGRX BIT(NPCX_ESPIWE_PMSGRXWE)
 
 /* Bit field manipulation for VWEVMS Value */
-#define VWEVMS_WK_EN(e)			(((e)<<20) & 0x00100000)
-#define VWEVMS_INTWK_EN(e)		(VWEVMS_INT_EN(e) | VWEVMS_WK_EN(e))
+#define VWEVMS_WK_EN(e) (((e) << 20) & 0x00100000)
+#define VWEVMS_INTWK_EN(e) (VWEVMS_INT_EN(e) | VWEVMS_WK_EN(e))
 
 /* eSPI max supported frequency */
 enum {
@@ -454,41 +463,41 @@ enum {
 
 /* eSPI max frequency support per FMCLK */
 #if (FMCLK <= 33000000)
-#define NPCX_ESPI_MAXFREQ_MAX		NPCX_ESPI_MAXFREQ_33
+#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_33
 #else
-#define NPCX_ESPI_MAXFREQ_MAX		NPCX_ESPI_MAXFREQ_50
+#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_50
 #endif
 
 /* UART registers */
-#define NPCX_UART_WK_GROUP		MIWU_GROUP_8
-#define NPCX_UART_WK_BIT		7
+#define NPCX_UART_WK_GROUP MIWU_GROUP_8
+#define NPCX_UART_WK_BIT 7
 #ifdef NPCX_SECOND_UART
-#define NPCX_UART2_WK_GROUP		MIWU_GROUP_1
-#define NPCX_UART2_WK_BIT		6
+#define NPCX_UART2_WK_GROUP MIWU_GROUP_1
+#define NPCX_UART2_WK_BIT 6
 #endif
 
 /* MIWU registers */
-#define NPCX_WKEDG_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x00 + \
-					((n) * 2L) + ((n) < 5 ? 0 : 0x1E))
-#define NPCX_WKAEDG_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x01 + \
-					((n) * 2L) + ((n) < 5 ? 0 : 0x1E))
-#define NPCX_WKPND_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x0A + \
-					((n) * 4L) + ((n) < 5 ? 0 : 0x10))
-#define NPCX_WKPCL_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x0C + \
-					((n) * 4L) + ((n) < 5 ? 0 : 0x10))
-#define NPCX_WKEN_ADDR(port, n)		(NPCX_MIWU_BASE_ADDR(port) + 0x1E + \
-					((n) * 2L) + ((n) < 5 ? 0 : 0x12))
-#define NPCX_WKINEN_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x1F + \
-					((n) * 2L) + ((n) < 5 ? 0 : 0x12))
-#define NPCX_WKMOD_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x70 + (n))
-
-#define NPCX_WKEDG(port, n)		REG8(NPCX_WKEDG_ADDR(port, n))
-#define NPCX_WKAEDG(port, n)		REG8(NPCX_WKAEDG_ADDR(port, n))
-#define NPCX_WKPND(port, n)		REG8(NPCX_WKPND_ADDR(port, n))
-#define NPCX_WKPCL(port, n)		REG8(NPCX_WKPCL_ADDR(port, n))
-#define NPCX_WKEN(port, n)		REG8(NPCX_WKEN_ADDR(port, n))
-#define NPCX_WKINEN(port, n)		REG8(NPCX_WKINEN_ADDR(port, n))
-#define NPCX_WKMOD(port, n)		REG8(NPCX_WKMOD_ADDR(port, n))
+#define NPCX_WKEDG_ADDR(port, n) \
+	(NPCX_MIWU_BASE_ADDR(port) + 0x00 + ((n)*2L) + ((n) < 5 ? 0 : 0x1E))
+#define NPCX_WKAEDG_ADDR(port, n) \
+	(NPCX_MIWU_BASE_ADDR(port) + 0x01 + ((n)*2L) + ((n) < 5 ? 0 : 0x1E))
+#define NPCX_WKPND_ADDR(port, n) \
+	(NPCX_MIWU_BASE_ADDR(port) + 0x0A + ((n)*4L) + ((n) < 5 ? 0 : 0x10))
+#define NPCX_WKPCL_ADDR(port, n) \
+	(NPCX_MIWU_BASE_ADDR(port) + 0x0C + ((n)*4L) + ((n) < 5 ? 0 : 0x10))
+#define NPCX_WKEN_ADDR(port, n) \
+	(NPCX_MIWU_BASE_ADDR(port) + 0x1E + ((n)*2L) + ((n) < 5 ? 0 : 0x12))
+#define NPCX_WKINEN_ADDR(port, n) \
+	(NPCX_MIWU_BASE_ADDR(port) + 0x1F + ((n)*2L) + ((n) < 5 ? 0 : 0x12))
+#define NPCX_WKMOD_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x70 + (n))
+
+#define NPCX_WKEDG(port, n) REG8(NPCX_WKEDG_ADDR(port, n))
+#define NPCX_WKAEDG(port, n) REG8(NPCX_WKAEDG_ADDR(port, n))
+#define NPCX_WKPND(port, n) REG8(NPCX_WKPND_ADDR(port, n))
+#define NPCX_WKPCL(port, n) REG8(NPCX_WKPCL_ADDR(port, n))
+#define NPCX_WKEN(port, n) REG8(NPCX_WKEN_ADDR(port, n))
+#define NPCX_WKINEN(port, n) REG8(NPCX_WKINEN_ADDR(port, n))
+#define NPCX_WKMOD(port, n) REG8(NPCX_WKMOD_ADDR(port, n))
 
 /* UART registers and functions */
 #if NPCX_UART_MODULE2
@@ -496,64 +505,64 @@ enum {
  * To be used as 2nd parameter to NPCX_WK*() macro, table (1st parameter) is
  * always 1 == MIWU_TABLE_1.
  */
-#define NPCX_UART_MIWU_IRQ		NPCX_IRQ_WKINTG_1
-#define NPCX_UART_DEVALT		NPCX_DEVALT(0x0C)
-#define NPCX_UART_DEVALT_SL		NPCX_DEVALTC_UART_SL2
-#define NPCX_UART_ALT_DEVALT		NPCX_DEVALT(0x0A)
-#define NPCX_UART_ALT_DEVALT_SL		NPCX_DEVALTA_UART_SL1
+#define NPCX_UART_MIWU_IRQ NPCX_IRQ_WKINTG_1
+#define NPCX_UART_DEVALT NPCX_DEVALT(0x0C)
+#define NPCX_UART_DEVALT_SL NPCX_DEVALTC_UART_SL2
+#define NPCX_UART_ALT_DEVALT NPCX_DEVALT(0x0A)
+#define NPCX_UART_ALT_DEVALT_SL NPCX_DEVALTA_UART_SL1
 #else /* !NPCX_UART_MODULE2 */
-#define NPCX_UART_MIWU_IRQ		NPCX_IRQ_WKINTB_1
-#define NPCX_UART_DEVALT		NPCX_DEVALT(0x0A)
-#define NPCX_UART_DEVALT_SL		NPCX_DEVALTA_UART_SL1
-#define NPCX_UART_ALT_DEVALT		NPCX_DEVALT(0x0C)
-#define NPCX_UART_ALT_DEVALT_SL		NPCX_DEVALTC_UART_SL2
+#define NPCX_UART_MIWU_IRQ NPCX_IRQ_WKINTB_1
+#define NPCX_UART_DEVALT NPCX_DEVALT(0x0A)
+#define NPCX_UART_DEVALT_SL NPCX_DEVALTA_UART_SL1
+#define NPCX_UART_ALT_DEVALT NPCX_DEVALT(0x0C)
+#define NPCX_UART_ALT_DEVALT_SL NPCX_DEVALTC_UART_SL2
 #endif /* NPCX_UART_MODULE2 */
 
 /* ADC Registers */
-#define NPCX_ADCSTS		REG16(NPCX_ADC_BASE_ADDR + 0x000)
-#define NPCX_ADCCNF		REG16(NPCX_ADC_BASE_ADDR + 0x002)
-#define NPCX_ATCTL		REG16(NPCX_ADC_BASE_ADDR + 0x004)
-#define NPCX_ASCADD		REG16(NPCX_ADC_BASE_ADDR + 0x006)
-#define NPCX_ADCCS		REG16(NPCX_ADC_BASE_ADDR + 0x008)
+#define NPCX_ADCSTS REG16(NPCX_ADC_BASE_ADDR + 0x000)
+#define NPCX_ADCCNF REG16(NPCX_ADC_BASE_ADDR + 0x002)
+#define NPCX_ATCTL REG16(NPCX_ADC_BASE_ADDR + 0x004)
+#define NPCX_ASCADD REG16(NPCX_ADC_BASE_ADDR + 0x006)
+#define NPCX_ADCCS REG16(NPCX_ADC_BASE_ADDR + 0x008)
 /* NOTE: These are 1-based for the threshold detectors. */
-#define NPCX_THRCTL(n)		REG16(NPCX_ADC_BASE_ADDR + 0x012 + (2L*(n)))
-#define NPCX_THRCTS		REG16(NPCX_ADC_BASE_ADDR + 0x01A)
-#define NPCX_THR_DCTL(n)	REG16(NPCX_ADC_BASE_ADDR + 0x038 + (2L*(n)))
+#define NPCX_THRCTL(n) REG16(NPCX_ADC_BASE_ADDR + 0x012 + (2L * (n)))
+#define NPCX_THRCTS REG16(NPCX_ADC_BASE_ADDR + 0x01A)
+#define NPCX_THR_DCTL(n) REG16(NPCX_ADC_BASE_ADDR + 0x038 + (2L * (n)))
 /* NOTE: This is 0-based for the ADC channels. */
-#define NPCX_CHNDAT(n)		REG16(NPCX_ADC_BASE_ADDR + 0x040 + (2L*(n)))
-#define NPCX_ADCCNF2		REG16(NPCX_ADC_BASE_ADDR + 0x020)
-#define NPCX_GENDLY		REG16(NPCX_ADC_BASE_ADDR + 0x022)
-#define NPCX_MEAST		REG16(NPCX_ADC_BASE_ADDR + 0x026)
+#define NPCX_CHNDAT(n) REG16(NPCX_ADC_BASE_ADDR + 0x040 + (2L * (n)))
+#define NPCX_ADCCNF2 REG16(NPCX_ADC_BASE_ADDR + 0x020)
+#define NPCX_GENDLY REG16(NPCX_ADC_BASE_ADDR + 0x022)
+#define NPCX_MEAST REG16(NPCX_ADC_BASE_ADDR + 0x026)
 
 /* ADC register fields */
-#define NPCX_ATCTL_SCLKDIV_FIELD	FIELD(0, 6)
-#define NPCX_ATCTL_DLY_FIELD		FIELD(8, 3)
-#define NPCX_ASCADD_SADDR_FIELD		FIELD(0, 5)
-#define NPCX_ADCSTS_EOCEV		0
-#define NPCX_ADCCNF_ADCMD_FIELD		FIELD(1, 2)
-#define NPCX_ADCCNF_ADCRPTC		3
-#define NPCX_ADCCNF_INTECEN		6
-#define NPCX_ADCCNF_START		4
-#define NPCX_ADCCNF_ADCEN		0
-#define NPCX_ADCCNF_STOP		11
-#define NPCX_CHNDAT_CHDAT_FIELD		FIELD(0, 10)
-#define NPCX_CHNDAT_NEW			15
-#define NPCX_THRCTL_THEN		15
-#define NPCX_THRCTL_L_H			14
-#define NPCX_THRCTL_CHNSEL		FIELD(10, 4)
-#define NPCX_THRCTL_THRVAL		FIELD(0, 10)
-#define NPCX_THRCTS_ADC_WKEN		15
-#define NPCX_THRCTS_THR3_IEN		10
-#define NPCX_THRCTS_THR2_IEN		9
-#define NPCX_THRCTS_THR1_IEN		8
-#define NPCX_THRCTS_ADC_EVENT		7
-#define NPCX_THRCTS_THR3_STS		2
-#define NPCX_THRCTS_THR2_STS		1
-#define NPCX_THRCTS_THR1_STS		0
-#define NPCX_THR_DCTL_THRD_EN		15
-#define NPCX_THR_DCTL_THR_DVAL		FIELD(0, 10)
-
-#define NPCX_ADC_THRESH1		1
-#define NPCX_ADC_THRESH2		2
-#define NPCX_ADC_THRESH3		3
-#define NPCX_ADC_THRESH_CNT		3
+#define NPCX_ATCTL_SCLKDIV_FIELD FIELD(0, 6)
+#define NPCX_ATCTL_DLY_FIELD FIELD(8, 3)
+#define NPCX_ASCADD_SADDR_FIELD FIELD(0, 5)
+#define NPCX_ADCSTS_EOCEV 0
+#define NPCX_ADCCNF_ADCMD_FIELD FIELD(1, 2)
+#define NPCX_ADCCNF_ADCRPTC 3
+#define NPCX_ADCCNF_INTECEN 6
+#define NPCX_ADCCNF_START 4
+#define NPCX_ADCCNF_ADCEN 0
+#define NPCX_ADCCNF_STOP 11
+#define NPCX_CHNDAT_CHDAT_FIELD FIELD(0, 10)
+#define NPCX_CHNDAT_NEW 15
+#define NPCX_THRCTL_THEN 15
+#define NPCX_THRCTL_L_H 14
+#define NPCX_THRCTL_CHNSEL FIELD(10, 4)
+#define NPCX_THRCTL_THRVAL FIELD(0, 10)
+#define NPCX_THRCTS_ADC_WKEN 15
+#define NPCX_THRCTS_THR3_IEN 10
+#define NPCX_THRCTS_THR2_IEN 9
+#define NPCX_THRCTS_THR1_IEN 8
+#define NPCX_THRCTS_ADC_EVENT 7
+#define NPCX_THRCTS_THR3_STS 2
+#define NPCX_THRCTS_THR2_STS 1
+#define NPCX_THRCTS_THR1_STS 0
+#define NPCX_THR_DCTL_THRD_EN 15
+#define NPCX_THR_DCTL_THR_DVAL FIELD(0, 10)
+
+#define NPCX_ADC_THRESH1 1
+#define NPCX_ADC_THRESH2 2
+#define NPCX_ADC_THRESH3 3
+#define NPCX_ADC_THRESH_CNT 3
diff --git a/chip/npcx/registers-npcx9.h b/chip/npcx/registers-npcx9.h
index 93236cb977..11cac561d7 100644
--- a/chip/npcx/registers-npcx9.h
+++ b/chip/npcx/registers-npcx9.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,149 +19,155 @@
 #endif
 
 /* NPCX-IRQ numbers */
-#define NPCX_IRQ0_NOUSED		NPCX_IRQ_0
-#define NPCX_IRQ1_NOUSED		NPCX_IRQ_1
-#define NPCX_IRQ_KBSCAN			NPCX_IRQ_2
-#define NPCX_IRQ_PM_CHAN_OBE		NPCX_IRQ_3
-#define NPCX_IRQ_PECI			NPCX_IRQ_4
-#define NPCX_IRQ_MTC_WKINTD_0		NPCX_IRQ_5
-#define NPCX_IRQ_MTC			NPCX_IRQ_MTC_WKINTD_0
-#define NPCX_IRQ_PORT80			NPCX_IRQ_6
-#define NPCX_IRQ_CR_SIN2_WKINTA_0	NPCX_IRQ_7
-#define NPCX_IRQ_SMB8			NPCX_IRQ_8
-#define NPCX_IRQ_MFT_1			NPCX_IRQ_9
-#define NPCX_IRQ_ADC			NPCX_IRQ_10
-#define NPCX_IRQ_WKINTE_0		NPCX_IRQ_11
-#define NPCX_IRQ_GDMA			NPCX_IRQ_12
-#define NPCX_IRQ_SMB1			NPCX_IRQ_13
-#define NPCX_IRQ_SMB2			NPCX_IRQ_14
-#define NPCX_IRQ_WKINTC_0		NPCX_IRQ_15
-#define NPCX_IRQ_SMB7			NPCX_IRQ_16
-#define NPCX_IRQ_ITIM32_3		NPCX_IRQ_17
-#define NPCX_IRQ_SHI			NPCX_IRQ_18
-#define NPCX_IRQ_ESPI			NPCX_IRQ_18
-#define NPCX_IRQ_SMB5			NPCX_IRQ_19
-#define NPCX_IRQ_SMB6			NPCX_IRQ_20
-#define NPCX_IRQ_PS2			NPCX_IRQ_21
-#define NPCX_IRQ22_NOUSED		NPCX_IRQ_22
-#define NPCX_IRQ_MFT_2			NPCX_IRQ_23
-#define NPCX_IRQ_SHM			NPCX_IRQ_24
-#define NPCX_IRQ_KBC_IBF		NPCX_IRQ_25
-#define NPCX_IRQ_PM_CHAN_IBF		NPCX_IRQ_26
-#define NPCX_IRQ_ITIM32_2		NPCX_IRQ_27
-#define NPCX_IRQ_ITIM32_1		NPCX_IRQ_28
-#define NPCX_I3C_MDMA5			NPCX_IRQ_29
-#define NPCX_IRQ30_NOUSED		NPCX_IRQ_30
-#define NPCX_IRQ_TWD_WKINTB_0		NPCX_IRQ_31
-#define NPCX_IRQ_UART2			NPCX_IRQ_32
-#define NPCX_IRQ_UART			NPCX_IRQ_33
-#define NPCX_IRQ34_NOUSED		NPCX_IRQ_34
-#define NPCX_IRQ_WKINTF_0		NPCX_IRQ_35
-#define NPCX_IRQ_SMB3			NPCX_IRQ_36
-#define NPCX_IRQ_SMB4			NPCX_IRQ_37
-#define NPCX_IRQ_UART3			NPCX_IRQ_38
-#define NPCX_IRQ_UART4			NPCX_IRQ_39
-#define NPCX_IRQ40_NOUSED		NPCX_IRQ_40
-#define NPCX_IRQ_MFT_3			NPCX_IRQ_41
-#define NPCX_IRQ_WKINTG_0		NPCX_IRQ_42
-#define NPCX_IRQ_ITIM32_4		NPCX_IRQ_43
-#define NPCX_IRQ_ITIM32_5		NPCX_IRQ_44
-#define NPCX_IRQ_ITIM32_6		NPCX_IRQ_45
-#define NPCX_IRQ_WKINTH_0		NPCX_IRQ_46
-#define NPCX_IRQ_WKINTA_1		NPCX_IRQ_47
-#define NPCX_IRQ_WKINTB_1		NPCX_IRQ_48
-#define NPCX_IRQ_KSI_WKINTC_1		NPCX_IRQ_49
-#define NPCX_IRQ_WKINTD_1		NPCX_IRQ_50
-#define NPCX_IRQ_WKINTE_1		NPCX_IRQ_51
-#define NPCX_IRQ_WKINTF_1		NPCX_IRQ_52
-#define NPCX_IRQ_WKINTG_1		NPCX_IRQ_53
-#define NPCX_IRQ_WKINTH_1		NPCX_IRQ_54
-#define NPCX_WKINTG_2			NPCX_IRQ_55
-#define NPCX_IRQ_KBC_OBE		NPCX_IRQ_56
-#define NPCX_IRQ_SPI			NPCX_IRQ_57
-#define NPCX_IRQ_ITIM64			NPCX_IRQ_58
-#define NPCX_IRQ_LCT_WKINTF_2		NPCX_IRQ_59
-#define NPCX_IRQ_WKINTA_2		NPCX_IRQ_60
-#define NPCX_IRQ_WKINTB_2		NPCX_IRQ_61
-#define NPCX_IRQ_WKINTC_2		NPCX_IRQ_62
-#define NPCX_IRQ_WKINTD_2		NPCX_IRQ_63
+#define NPCX_IRQ0_NOUSED NPCX_IRQ_0
+#define NPCX_IRQ1_NOUSED NPCX_IRQ_1
+#define NPCX_IRQ_KBSCAN NPCX_IRQ_2
+#define NPCX_IRQ_PM_CHAN_OBE NPCX_IRQ_3
+#define NPCX_IRQ_PECI NPCX_IRQ_4
+#define NPCX_IRQ_MTC_WKINTD_0 NPCX_IRQ_5
+#define NPCX_IRQ_MTC NPCX_IRQ_MTC_WKINTD_0
+#define NPCX_IRQ_PORT80 NPCX_IRQ_6
+#define NPCX_IRQ_CR_SIN2_WKINTA_0 NPCX_IRQ_7
+#define NPCX_IRQ_SMB8 NPCX_IRQ_8
+#define NPCX_IRQ_MFT_1 NPCX_IRQ_9
+#define NPCX_IRQ_ADC NPCX_IRQ_10
+#define NPCX_IRQ_WKINTE_0 NPCX_IRQ_11
+#define NPCX_IRQ_GDMA NPCX_IRQ_12
+#define NPCX_IRQ_SMB1 NPCX_IRQ_13
+#define NPCX_IRQ_SMB2 NPCX_IRQ_14
+#define NPCX_IRQ_WKINTC_0 NPCX_IRQ_15
+#define NPCX_IRQ_SMB7 NPCX_IRQ_16
+#define NPCX_IRQ_ITIM32_3 NPCX_IRQ_17
+#define NPCX_IRQ_SHI NPCX_IRQ_18
+#define NPCX_IRQ_ESPI NPCX_IRQ_18
+#define NPCX_IRQ_SMB5 NPCX_IRQ_19
+#define NPCX_IRQ_SMB6 NPCX_IRQ_20
+#define NPCX_IRQ_PS2 NPCX_IRQ_21
+#define NPCX_IRQ22_NOUSED NPCX_IRQ_22
+#define NPCX_IRQ_MFT_2 NPCX_IRQ_23
+#define NPCX_IRQ_SHM NPCX_IRQ_24
+#define NPCX_IRQ_KBC_IBF NPCX_IRQ_25
+#define NPCX_IRQ_PM_CHAN_IBF NPCX_IRQ_26
+#define NPCX_IRQ_ITIM32_2 NPCX_IRQ_27
+#define NPCX_IRQ_ITIM32_1 NPCX_IRQ_28
+#define NPCX_I3C_MDMA5 NPCX_IRQ_29
+#define NPCX_IRQ30_NOUSED NPCX_IRQ_30
+#define NPCX_IRQ_TWD_WKINTB_0 NPCX_IRQ_31
+#define NPCX_IRQ_UART2 NPCX_IRQ_32
+#define NPCX_IRQ_UART NPCX_IRQ_33
+#define NPCX_IRQ34_NOUSED NPCX_IRQ_34
+#define NPCX_IRQ_WKINTF_0 NPCX_IRQ_35
+#define NPCX_IRQ_SMB3 NPCX_IRQ_36
+#define NPCX_IRQ_SMB4 NPCX_IRQ_37
+#define NPCX_IRQ_UART3 NPCX_IRQ_38
+#define NPCX_IRQ_UART4 NPCX_IRQ_39
+#define NPCX_IRQ40_NOUSED NPCX_IRQ_40
+#define NPCX_IRQ_MFT_3 NPCX_IRQ_41
+#define NPCX_IRQ_WKINTG_0 NPCX_IRQ_42
+#define NPCX_IRQ_ITIM32_4 NPCX_IRQ_43
+#define NPCX_IRQ_ITIM32_5 NPCX_IRQ_44
+#define NPCX_IRQ_ITIM32_6 NPCX_IRQ_45
+#define NPCX_IRQ_WKINTH_0 NPCX_IRQ_46
+#define NPCX_IRQ_WKINTA_1 NPCX_IRQ_47
+#define NPCX_IRQ_WKINTB_1 NPCX_IRQ_48
+#define NPCX_IRQ_KSI_WKINTC_1 NPCX_IRQ_49
+#define NPCX_IRQ_WKINTD_1 NPCX_IRQ_50
+#define NPCX_IRQ_WKINTE_1 NPCX_IRQ_51
+#define NPCX_IRQ_WKINTF_1 NPCX_IRQ_52
+#define NPCX_IRQ_WKINTG_1 NPCX_IRQ_53
+#define NPCX_IRQ_WKINTH_1 NPCX_IRQ_54
+#define NPCX_WKINTG_2 NPCX_IRQ_55
+#define NPCX_IRQ_KBC_OBE NPCX_IRQ_56
+#define NPCX_IRQ_SPI NPCX_IRQ_57
+#define NPCX_IRQ_ITIM64 NPCX_IRQ_58
+#define NPCX_IRQ_LCT_WKINTF_2 NPCX_IRQ_59
+#define NPCX_IRQ_WKINTA_2 NPCX_IRQ_60
+#define NPCX_IRQ_WKINTB_2 NPCX_IRQ_61
+#define NPCX_IRQ_WKINTC_2 NPCX_IRQ_62
+#define NPCX_IRQ_WKINTD_2 NPCX_IRQ_63
 /* MIWU definition */
-#define LCT_WUI_GROUP			MIWU_GROUP_6
-#define LCT_WUI_MASK			MASK_PIN7
+#define LCT_WUI_GROUP MIWU_GROUP_6
+#define LCT_WUI_MASK MASK_PIN7
 
 /* Modules Map */
-#define NPCX_CR_UART_BASE_ADDR(mdl)	(0x400E0000 + ((mdl) * 0x2000L))
-#define NPCX_LCT_BASE_ADDR		0x400D7000
-#define NPCX_SMB_BASE_ADDR(mdl)		(((mdl) < 2) ? \
-				(0x40009000 + ((mdl) * 0x2000L)) : \
-				((mdl) < 4) ? \
-				(0x400C0000 + (((mdl) - 2) * 0x2000L)) : \
-				((mdl) == 4) ? \
-				(0x40008000) : \
-				(0x40017000 + (((mdl) - 5) * 0x1000L)))
-
-#define NPCX_HFCBCD1			REG8(NPCX_HFCG_BASE_ADDR + 0x012)
-#define NPCX_HFCBCD2			REG8(NPCX_HFCG_BASE_ADDR + 0x014)
+
+/* Miscellaneous Device Control (MDC) registers */
+#define NPCX_FWCTRL REG8(NPCX_MDC_BASE_ADDR + 0x009)
+
+/* MDC register fields */
+#define NPCX_FWCTRL_RO_REGION 6
+#define NPCX_FWCTRL_FW_SLOT 7
+
+#define NPCX_CR_UART_BASE_ADDR(mdl) (0x400E0000 + ((mdl)*0x2000L))
+#define NPCX_LCT_BASE_ADDR 0x400D7000
+#define NPCX_SMB_BASE_ADDR(mdl)                                \
+	(((mdl) < 2)  ? (0x40009000 + ((mdl)*0x2000L)) :       \
+	 ((mdl) < 4)  ? (0x400C0000 + (((mdl)-2) * 0x2000L)) : \
+	 ((mdl) == 4) ? (0x40008000) :                         \
+			(0x40017000 + (((mdl)-5) * 0x1000L)))
+
+#define NPCX_HFCBCD1 REG8(NPCX_HFCG_BASE_ADDR + 0x012)
+#define NPCX_HFCBCD2 REG8(NPCX_HFCG_BASE_ADDR + 0x014)
 
 enum {
-	NPCX_UART_PORT0 = 0,	/* UART port 0 */
-	NPCX_UART_PORT1 = 1,	/* UART port 1 */
-	NPCX_UART_PORT2 = 2,	/* UART port 2 */
-	NPCX_UART_PORT3 = 3,	/* UART port 3 */
+	NPCX_UART_PORT0 = 0, /* UART port 0 */
+	NPCX_UART_PORT1 = 1, /* UART port 1 */
+	NPCX_UART_PORT2 = 2, /* UART port 2 */
+	NPCX_UART_PORT3 = 3, /* UART port 3 */
 	NPCX_UART_COUNT
 };
 
- /* UART registers only used for FIFO mode */
-#define NPCX_UFTSTS(n)			REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x020)
-#define NPCX_UFRSTS(n)			REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x022)
-#define NPCX_UFTCTL(n)			REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x024)
-#define NPCX_UFRCTL(n)			REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x026)
+/* UART registers only used for FIFO mode */
+#define NPCX_UFTSTS(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x020)
+#define NPCX_UFRSTS(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x022)
+#define NPCX_UFTCTL(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x024)
+#define NPCX_UFRCTL(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x026)
 
 /* UART FIFO register fields */
-#define NPCX_UMDSL_FIFO_MD		0
+#define NPCX_UMDSL_FIFO_MD 0
 
-#define NPCX_UFTSTS_TEMPTY_LVL		FIELD(0, 5)
-#define NPCX_UFTSTS_TEMPTY_LVL_STS	5
-#define NPCX_UFTSTS_TFIFO_EMPTY_STS	6
-#define NPCX_UFTSTS_NXMIP		7
+#define NPCX_UFTSTS_TEMPTY_LVL FIELD(0, 5)
+#define NPCX_UFTSTS_TEMPTY_LVL_STS 5
+#define NPCX_UFTSTS_TFIFO_EMPTY_STS 6
+#define NPCX_UFTSTS_NXMIP 7
 
-#define NPCX_UFRSTS_RFULL_LVL_STS	5
-#define NPCX_UFRSTS_RFIFO_NEMPTY_STS	6
-#define NPCX_UFRSTS_ERR			7
+#define NPCX_UFRSTS_RFULL_LVL_STS 5
+#define NPCX_UFRSTS_RFIFO_NEMPTY_STS 6
+#define NPCX_UFRSTS_ERR 7
 
-#define NPCX_UFTCTL_TEMPTY_LVL_SEL	FIELD(0, 5)
-#define NPCX_UFTCTL_TEMPTY_LVL_EN	5
-#define NPCX_UFTCTL_TEMPTY_EN		6
-#define NPCX_UFTCTL_NXMIPEN		7
+#define NPCX_UFTCTL_TEMPTY_LVL_SEL FIELD(0, 5)
+#define NPCX_UFTCTL_TEMPTY_LVL_EN 5
+#define NPCX_UFTCTL_TEMPTY_EN 6
+#define NPCX_UFTCTL_NXMIPEN 7
 
-#define NPCX_UFRCTL_RFULL_LVL_SEL	FIELD(0, 5)
-#define NPCX_UFRCTL_RFULL_LVL_EN	5
-#define NPCX_UFRCTL_RNEMPTY_EN		6
-#define NPCX_UFRCTL_ERR_EN		7
+#define NPCX_UFRCTL_RFULL_LVL_SEL FIELD(0, 5)
+#define NPCX_UFRCTL_RFULL_LVL_EN 5
+#define NPCX_UFRCTL_RNEMPTY_EN 6
+#define NPCX_UFRCTL_ERR_EN 7
 
 /* KBSCAN register fields */
-#define NPCX_KBHDRV_FIELD		FIELD(6, 2)
+#define NPCX_KBHDRV_FIELD FIELD(6, 2)
 
 /* GLUE registers */
-#define NPCX_GLUE_PSL_CTS		REG8(NPCX_GLUE_REGS_BASE + 0x027)
-#define NPCX_GLUE_PSL_MCTL1		REG8(NPCX_GLUE_REGS_BASE + 0x034)
-#define NPCX_GLUE_PSL_MCTL2		REG8(NPCX_GLUE_REGS_BASE + 0x038)
+#define NPCX_GLUE_PSL_CTS REG8(NPCX_GLUE_REGS_BASE + 0x027)
+#define NPCX_GLUE_PSL_MCTL1 REG8(NPCX_GLUE_REGS_BASE + 0x034)
+#define NPCX_GLUE_PSL_MCTL2 REG8(NPCX_GLUE_REGS_BASE + 0x038)
 
 /* PSL register fields */
-#define NPCX_GLUE_PSL_MCTL1_VCC1_RST_PSL	7
-#define NPCX_GLUE_PSL_MCTL1_PSL_GPO_CTL		6
-#define NPCX_GLUE_PSL_MCTL1_LCT_EV		4
-#define NPCX_GLUE_PSL_MCTL1_VCC1_RST_EV		3
-#define NPCX_GLUE_PSL_MCTL1_PLS_EN		1
-#define NPCX_GLUE_PSL_MCTL1_OD_EN		0
-
-#define NPCX_GLUE_PSL_MCTL2_VCC1_RST_PSL_LK	7
-#define NPCX_GLUE_PSL_MCTL2_PSL_GP_EN		6
-#define NPCX_GLUE_PSL_MCTL2_AC_IN_BLOCK_EN	3
-#define NPCX_GLUE_PSL_MCTL2_AC_IN_SEL		FIELD(0, 1)
+#define NPCX_GLUE_PSL_MCTL1_VCC1_RST_PSL 7
+#define NPCX_GLUE_PSL_MCTL1_PSL_GPO_CTL 6
+#define NPCX_GLUE_PSL_MCTL1_LCT_EV 4
+#define NPCX_GLUE_PSL_MCTL1_VCC1_RST_EV 3
+#define NPCX_GLUE_PSL_MCTL1_PLS_EN 1
+#define NPCX_GLUE_PSL_MCTL1_OD_EN 0
+
+#define NPCX_GLUE_PSL_MCTL2_VCC1_RST_PSL_LK 7
+#define NPCX_GLUE_PSL_MCTL2_PSL_GP_EN 6
+#define NPCX_GLUE_PSL_MCTL2_AC_IN_BLOCK_EN 3
+#define NPCX_GLUE_PSL_MCTL2_AC_IN_SEL FIELD(0, 1)
 
 /* GPIO registers */
-#define NPCX_PLOCK_CTL(n)		REG8(NPCX_GPIO_BASE_ADDR(n) + 0x007)
+#define NPCX_PLOCK_CTL(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x007)
 
 /* System Configuration (SCFG) Registers */
 
@@ -189,99 +195,105 @@ enum {
 	ALT_GROUP_COUNT
 };
 
-#define NPCX_DEVALT(n)			REG8(NPCX_SCFG_BASE_ADDR + 0x010 + (n))
+#define NPCX_DEVALT(n) REG8(NPCX_SCFG_BASE_ADDR + 0x010 + (n))
 
-#define NPCX_LV_GPIO_CTL_ADDR(n)	(((n) < 5) ? \
-					(NPCX_SCFG_BASE_ADDR + 0x02A + (n)) :\
-					(NPCX_SCFG_BASE_ADDR + 0x026))
-#define NPCX_LV_GPIO_CTL(n)		REG8(NPCX_LV_GPIO_CTL_ADDR(n))
+#define NPCX_LV_GPIO_CTL_ADDR(n)                           \
+	(((n) < 5) ? (NPCX_SCFG_BASE_ADDR + 0x02A + (n)) : \
+		     (NPCX_SCFG_BASE_ADDR + 0x026))
+#define NPCX_LV_GPIO_CTL(n) REG8(NPCX_LV_GPIO_CTL_ADDR(n))
 /* Device Alternate Function Lock */
-#define NPCX_DEVALT_LK(n)		REG8(NPCX_SCFG_BASE_ADDR + 0x210 + (n))
+#define NPCX_DEVALT_LK(n) REG8(NPCX_SCFG_BASE_ADDR + 0x210 + (n))
 
 /* pin-mux for I2C */
-#define NPCX_DEVALT2_I2C0_0_SL		0
-#define NPCX_DEVALT2_I2C7_0_SL		1
-#define NPCX_DEVALT2_I2C1_0_SL		2
-#define NPCX_DEVALT2_I2C6_0_SL		3
-#define NPCX_DEVALT2_I2C2_0_SL		4
-#define NPCX_DEVALT2_I2C5_0_SL		5
-#define NPCX_DEVALT2_I2C3_0_SL		6
-#define NPCX_DEVALT6_I2C6_1_SL		5
-#define NPCX_DEVALT6_I2C5_1_SL		6
-#define NPCX_DEVALT6_I2C4_1_SL		7
+#define NPCX_DEVALT2_I2C0_0_SL 0
+#define NPCX_DEVALT2_I2C7_0_SL 1
+#define NPCX_DEVALT2_I2C1_0_SL 2
+#define NPCX_DEVALT2_I2C6_0_SL 3
+#define NPCX_DEVALT2_I2C2_0_SL 4
+#define NPCX_DEVALT2_I2C5_0_SL 5
+#define NPCX_DEVALT2_I2C3_0_SL 6
+#define NPCX_DEVALT6_I2C6_1_SL 5
+#define NPCX_DEVALT6_I2C5_1_SL 6
+#define NPCX_DEVALT6_I2C4_1_SL 7
 
 /* pin-mux for ADC */
-#define NPCX_DEVALTF_ADC5_SL		0
-#define NPCX_DEVALTF_ADC6_SL		1
-#define NPCX_DEVALTF_ADC7_SL		2
-#define NPCX_DEVALTF_ADC8_SL		3
-#define NPCX_DEVALTF_ADC9_SL		4
-#define NPCX_DEVALTF_ADC10_SL		5
-#define NPCX_DEVALTF_ADC11_SL		6
+#define NPCX_DEVALTF_ADC5_SL 0
+#define NPCX_DEVALTF_ADC6_SL 1
+#define NPCX_DEVALTF_ADC7_SL 2
+#define NPCX_DEVALTF_ADC8_SL 3
+#define NPCX_DEVALTF_ADC9_SL 4
+#define NPCX_DEVALTF_ADC10_SL 5
+#define NPCX_DEVALTF_ADC11_SL 6
 
 /* pin-mux for PSL */
-#define NPCX_DEVALTD_PSL_IN1_AHI	0
-#define NPCX_DEVALTD_NPSL_IN1_SL	1
-#define NPCX_DEVALTD_PSL_IN2_AHI	2
-#define NPCX_DEVALTD_NPSL_IN2_SL	3
-#define NPCX_DEVALTD_PSL_IN3_AHI	4
-#define NPCX_DEVALTD_PSL_IN3_SL		5
-#define NPCX_DEVALTD_PSL_IN4_AHI	6
-#define NPCX_DEVALTD_PSL_IN4_SL		7
+#define NPCX_DEVALTD_PSL_IN1_AHI 0
+#define NPCX_DEVALTD_NPSL_IN1_SL 1
+#define NPCX_DEVALTD_PSL_IN2_AHI 2
+#define NPCX_DEVALTD_NPSL_IN2_SL 3
+#define NPCX_DEVALTD_PSL_IN3_AHI 4
+#define NPCX_DEVALTD_PSL_IN3_SL 5
+#define NPCX_DEVALTD_PSL_IN4_AHI 6
+#define NPCX_DEVALTD_PSL_IN4_SL 7
 
 /* pin-mux for Misc. */
 
 /* pin-mux for UART */
-#define NPCX_DEVALTJ_CR_SIN1_SL1	0
-#define NPCX_DEVALTJ_CR_SOUT1_SL1	1
-#define NPCX_DEVALTJ_CR_SIN1_SL2	2
-#define NPCX_DEVALTJ_CR_SOUT1_SL2	3
-#define NPCX_DEVALTJ_CR_SIN2_SL		4
-#define NPCX_DEVALTJ_CR_SOUT2_SL	5
-#define NPCX_DEVALTJ_CR_SIN3_SL		6
-#define NPCX_DEVALTJ_CR_SOUT3_SL	7
-#define NPCX_DEVALTE_CR_SIN4_SL		6
-#define NPCX_DEVALTE_CR_SOUT4_SL	7
+#define NPCX_DEVALTJ_CR_SIN1_SL1 0
+#define NPCX_DEVALTJ_CR_SOUT1_SL1 1
+#define NPCX_DEVALTJ_CR_SIN1_SL2 2
+#define NPCX_DEVALTJ_CR_SOUT1_SL2 3
+#define NPCX_DEVALTJ_CR_SIN2_SL 4
+#define NPCX_DEVALTJ_CR_SOUT2_SL 5
+#define NPCX_DEVALTJ_CR_SIN3_SL 6
+#define NPCX_DEVALTJ_CR_SOUT3_SL 7
+#define NPCX_DEVALTE_CR_SIN4_SL 6
+#define NPCX_DEVALTE_CR_SOUT4_SL 7
 
 /* SHI module version 2 enable bit */
-#define NPCX_DEVALTF_SHI_NEW		7
+#define NPCX_DEVALTF_SHI_NEW 7
 
 /* VCC_RST Pull-Up Disable */
-#define NPCX_DEVALTG_VCC1_RST_PUD	5
-#define NPCX_DEVALTG_PSL_OUT_SL		6
-#define NPCX_DEVALTG_PSL_GPO_SL		7
+#define NPCX_DEVALTG_VCC1_RST_PUD 5
+#define NPCX_DEVALTG_PSL_OUT_SL 6
+#define NPCX_DEVALTG_PSL_GPO_SL 7
 
 /* SMBus register fields */
-#define NPCX_SMBSEL_SMB4SEL		4
-#define NPCX_SMBSEL_SMB5SEL		5
-#define NPCX_SMBSEL_SMB6SEL		6
+#define NPCX_SMBSEL_SMB4SEL 4
+#define NPCX_SMBSEL_SMB5SEL 5
+#define NPCX_SMBSEL_SMB6SEL 6
+
+/* pin-mux for JTAG */
+#define NPCX_JEN_CTL1 REG8(NPCX_SCFG_BASE_ADDR + 0x120)
+#define NPCX_JEN_CTL1_JEN_EN_FIELD FIELD(0, 4)
+#define NPCX_JEN_CTL1_JEN_EN_DIS 0x06
+#define NPCX_JEN_CTL1_JEN_EN_ENA 0x09
 
 /* SMB enumeration: I2C port definitions. */
 enum {
-	NPCX_I2C_PORT0_0 = 0,	/* I2C port 0, bus 0 */
-	NPCX_I2C_PORT1_0,	/* I2C port 1, bus 0 */
-	NPCX_I2C_PORT2_0,	/* I2C port 2, bus 0 */
-	NPCX_I2C_PORT3_0,	/* I2C port 3, bus 0 */
-	NPCX_I2C_PORT4_1,	/* I2C port 4, bus 1 */
-	NPCX_I2C_PORT5_0,	/* I2C port 5, bus 0 */
-	NPCX_I2C_PORT5_1,	/* I2C port 5, bus 1 */
-	NPCX_I2C_PORT6_0,	/* I2C port 6, bus 0 */
-	NPCX_I2C_PORT6_1,	/* I2C port 6, bus 1 */
-	NPCX_I2C_PORT7_0,	/* I2C port 7, bus 0 */
+	NPCX_I2C_PORT0_0 = 0, /* I2C port 0, bus 0 */
+	NPCX_I2C_PORT1_0, /* I2C port 1, bus 0 */
+	NPCX_I2C_PORT2_0, /* I2C port 2, bus 0 */
+	NPCX_I2C_PORT3_0, /* I2C port 3, bus 0 */
+	NPCX_I2C_PORT4_1, /* I2C port 4, bus 1 */
+	NPCX_I2C_PORT5_0, /* I2C port 5, bus 0 */
+	NPCX_I2C_PORT5_1, /* I2C port 5, bus 1 */
+	NPCX_I2C_PORT6_0, /* I2C port 6, bus 0 */
+	NPCX_I2C_PORT6_1, /* I2C port 6, bus 1 */
+	NPCX_I2C_PORT7_0, /* I2C port 7, bus 0 */
 	NPCX_I2C_COUNT,
 };
 
 /* Power Management Controller (PMC) Registers */
-#define NPCX_FMUL_WIN_DLY	REG8(NPCX_PMC_BASE_ADDR + 0x010)
-#define NPCX_RAM_PD(offset)	REG8(NPCX_PMC_BASE_ADDR + 0x020 + (offset))
+#define NPCX_FMUL_WIN_DLY REG8(NPCX_PMC_BASE_ADDR + 0x010)
+#define NPCX_RAM_PD(offset) REG8(NPCX_PMC_BASE_ADDR + 0x020 + (offset))
 
 /* PMC register fields */
-#define NPCX_PWDWN_CTL3_SMB4_PD		4
-#define NPCX_PWDWN_CTL7_SMB5_PD		0
-#define NPCX_PWDWN_CTL7_SMB6_PD		1
-#define NPCX_PWDWN_CTL7_SMB7_PD		2
-#define NPCX_PWDWN_CTL7_ITIM64_PD	5
-#define NPCX_PWDWN_CTL7_UART2_PD	6
+#define NPCX_PWDWN_CTL3_SMB4_PD 4
+#define NPCX_PWDWN_CTL7_SMB5_PD 0
+#define NPCX_PWDWN_CTL7_SMB6_PD 1
+#define NPCX_PWDWN_CTL7_SMB7_PD 2
+#define NPCX_PWDWN_CTL7_ITIM64_PD 5
+#define NPCX_PWDWN_CTL7_UART2_PD 6
 
 /*
  * PMC enumeration:
@@ -313,41 +325,41 @@ enum NPCX_PMC_PWDWN_CTL_T {
 	NPCX_PMC_PWDWN_5 = 4,
 	NPCX_PMC_PWDWN_6 = 5,
 	NPCX_PMC_PWDWN_7 = 6,
+	NPCX_PMC_PWDWN_8 = 7,
 	NPCX_PMC_PWDWN_CNT,
 };
 
-#define CGC_I2C_MASK			(BIT(NPCX_PWDWN_CTL3_SMB0_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB1_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB2_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB3_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB4_PD))
-#define CGC_I2C_MASK2			(BIT(NPCX_PWDWN_CTL7_SMB5_PD) | \
-					BIT(NPCX_PWDWN_CTL7_SMB6_PD) | \
-					BIT(NPCX_PWDWN_CTL7_SMB7_PD))
-#define CGC_UART2_MASK			BIT(NPCX_PWDWN_CTL7_UART2_PD)
+#define CGC_I2C_MASK                                                   \
+	(BIT(NPCX_PWDWN_CTL3_SMB0_PD) | BIT(NPCX_PWDWN_CTL3_SMB1_PD) | \
+	 BIT(NPCX_PWDWN_CTL3_SMB2_PD) | BIT(NPCX_PWDWN_CTL3_SMB3_PD) | \
+	 BIT(NPCX_PWDWN_CTL3_SMB4_PD))
+#define CGC_I2C_MASK2                                                  \
+	(BIT(NPCX_PWDWN_CTL7_SMB5_PD) | BIT(NPCX_PWDWN_CTL7_SMB6_PD) | \
+	 BIT(NPCX_PWDWN_CTL7_SMB7_PD))
+#define CGC_UART2_MASK BIT(NPCX_PWDWN_CTL7_UART2_PD)
 
 /* BBRAM register fields */
-#define NPCX_BKUP_STS_VSBY_STS		1
-#define NPCX_BKUP_STS_VCC1_STS		0
-#define NPCX_BKUP_STS_ALL_MASK \
+#define NPCX_BKUP_STS_VSBY_STS 1
+#define NPCX_BKUP_STS_VCC1_STS 0
+#define NPCX_BKUP_STS_ALL_MASK                                   \
 	(BIT(NPCX_BKUP_STS_IBBR) | BIT(NPCX_BKUP_STS_VSBY_STS) | \
-	BIT(NPCX_BKUP_STS_VCC1_STS))
-#define NPCX_BBRAM_SIZE			128 /* Size of BBRAM */
+	 BIT(NPCX_BKUP_STS_VCC1_STS))
+#define NPCX_BBRAM_SIZE 128 /* Size of BBRAM */
 
 /* ITIM registers */
-#define NPCX_ITCNT32(n)			REG32(NPCX_ITIM_BASE_ADDR(n) + 0x008)
+#define NPCX_ITCNT32(n) REG32(NPCX_ITIM_BASE_ADDR(n) + 0x008)
 
 /* Timer counter register used for 1 micro-second system tick */
-#define NPCX_ITCNT_SYSTEM		NPCX_ITCNT32(ITIM32_6)
+#define NPCX_ITCNT_SYSTEM NPCX_ITCNT32(ITIM32_6)
 /* Timer counter register used for others */
-#define NPCX_ITCNT			NPCX_ITCNT32
+#define NPCX_ITCNT NPCX_ITCNT32
 
 /* ITIM module No. used for event */
-#define ITIM_EVENT_NO			ITIM32_1
+#define ITIM_EVENT_NO ITIM32_1
 /* ITIM module No. used for watchdog */
-#define ITIM_WDG_NO				ITIM32_5
+#define ITIM_WDG_NO ITIM32_5
 /* ITIM module No. used for 1 micro-second system tick */
-#define ITIM_SYSTEM_NO			ITIM32_6
+#define ITIM_SYSTEM_NO ITIM32_6
 
 /* ITIM enumeration */
 enum ITIM_MODULE_T {
@@ -361,56 +373,56 @@ enum ITIM_MODULE_T {
 };
 
 /* Serial Host Interface (SHI) Registers - only available on SHI Version 2 */
-#define NPCX_SHICFG3			REG8(NPCX_SHI_BASE_ADDR + 0x00C)
-#define NPCX_SHICFG4			REG8(NPCX_SHI_BASE_ADDR + 0x00D)
-#define NPCX_SHICFG5			REG8(NPCX_SHI_BASE_ADDR + 0x00E)
-#define NPCX_EVSTAT2			REG8(NPCX_SHI_BASE_ADDR + 0x00F)
-#define NPCX_EVENABLE2			REG8(NPCX_SHI_BASE_ADDR + 0x010)
-#define NPCX_OBUF(n)			REG8(NPCX_SHI_BASE_ADDR + 0x020 + (n))
-#define NPCX_IBUF(n)			REG8(NPCX_SHI_BASE_ADDR + 0x0A0 + (n))
+#define NPCX_SHICFG3 REG8(NPCX_SHI_BASE_ADDR + 0x00C)
+#define NPCX_SHICFG4 REG8(NPCX_SHI_BASE_ADDR + 0x00D)
+#define NPCX_SHICFG5 REG8(NPCX_SHI_BASE_ADDR + 0x00E)
+#define NPCX_EVSTAT2 REG8(NPCX_SHI_BASE_ADDR + 0x00F)
+#define NPCX_EVENABLE2 REG8(NPCX_SHI_BASE_ADDR + 0x010)
+#define NPCX_OBUF(n) REG8(NPCX_SHI_BASE_ADDR + 0x020 + (n))
+#define NPCX_IBUF(n) REG8(NPCX_SHI_BASE_ADDR + 0x0A0 + (n))
 
 /* SHI register fields */
-#define NPCX_SHICFG3_OBUFLVLDIS		7
-#define NPCX_SHICFG4_IBUFLVLDIS		7
-#define NPCX_SHICFG5_IBUFLVL2		FIELD(0, 6)
-#define NPCX_SHICFG5_IBUFLVL2DIS	7
-#define NPCX_EVSTAT2_IBHF2		0
-#define NPCX_EVSTAT2_CSNRE		1
-#define NPCX_EVSTAT2_CSNFE		2
-#define NPCX_EVENABLE2_IBHF2EN		0
-#define NPCX_EVENABLE2_CSNREEN		1
-#define NPCX_EVENABLE2_CSNFEEN		2
+#define NPCX_SHICFG3_OBUFLVLDIS 7
+#define NPCX_SHICFG4_IBUFLVLDIS 7
+#define NPCX_SHICFG5_IBUFLVL2 FIELD(0, 6)
+#define NPCX_SHICFG5_IBUFLVL2DIS 7
+#define NPCX_EVSTAT2_IBHF2 0
+#define NPCX_EVSTAT2_CSNRE 1
+#define NPCX_EVSTAT2_CSNFE 2
+#define NPCX_EVENABLE2_IBHF2EN 0
+#define NPCX_EVENABLE2_CSNREEN 1
+#define NPCX_EVENABLE2_CSNFEEN 2
 
 /* eSPI register fields */
-#define NPCX_ESPIIE_BMTXDONEIE		19
-#define NPCX_ESPIIE_PBMRXIE		20
-#define NPCX_ESPIIE_PMSGRXIE		21
-#define NPCX_ESPIIE_BMBURSTERRIE	22
-#define NPCX_ESPIIE_BMBURSTDONEIE	23
-
-#define NPCX_ESPIWE_PBMRXWE		20
-#define NPCX_ESPIWE_PMSGRXWE		21
-
-#define NPCX_ESPISTS_VWUPDW		17
-#define NPCX_ESPISTS_BMTXDONE		19
-#define NPCX_ESPISTS_PBMRX		20
-#define NPCX_ESPISTS_PMSGRX		21
-#define NPCX_ESPISTS_BMBURSTERR		22
-#define NPCX_ESPISTS_BMBURSTDONE	23
-#define NPCX_ESPISTS_ESPIRST_LVL	24
-
-#define ESPIIE_BMTXDONE			BIT(NPCX_ESPIIE_BMTXDONEIE)
-#define ESPIIE_PBMRX			BIT(NPCX_ESPIIE_PBMRXIE)
-#define ESPIIE_PMSGRX			BIT(NPCX_ESPIIE_PMSGRXIE)
-#define ESPIIE_BMBURSTERR		BIT(NPCX_ESPIIE_BMBURSTERRIE)
-#define ESPIIE_BMBURSTDONE		BIT(NPCX_ESPIIE_BMBURSTDONEIE)
-
-#define ESPIWE_PBMRX			BIT(NPCX_ESPIWE_PBMRXWE)
-#define ESPIWE_PMSGRX			BIT(NPCX_ESPIWE_PMSGRXWE)
+#define NPCX_ESPIIE_BMTXDONEIE 19
+#define NPCX_ESPIIE_PBMRXIE 20
+#define NPCX_ESPIIE_PMSGRXIE 21
+#define NPCX_ESPIIE_BMBURSTERRIE 22
+#define NPCX_ESPIIE_BMBURSTDONEIE 23
+
+#define NPCX_ESPIWE_PBMRXWE 20
+#define NPCX_ESPIWE_PMSGRXWE 21
+
+#define NPCX_ESPISTS_VWUPDW 17
+#define NPCX_ESPISTS_BMTXDONE 19
+#define NPCX_ESPISTS_PBMRX 20
+#define NPCX_ESPISTS_PMSGRX 21
+#define NPCX_ESPISTS_BMBURSTERR 22
+#define NPCX_ESPISTS_BMBURSTDONE 23
+#define NPCX_ESPISTS_ESPIRST_LVL 24
+
+#define ESPIIE_BMTXDONE BIT(NPCX_ESPIIE_BMTXDONEIE)
+#define ESPIIE_PBMRX BIT(NPCX_ESPIIE_PBMRXIE)
+#define ESPIIE_PMSGRX BIT(NPCX_ESPIIE_PMSGRXIE)
+#define ESPIIE_BMBURSTERR BIT(NPCX_ESPIIE_BMBURSTERRIE)
+#define ESPIIE_BMBURSTDONE BIT(NPCX_ESPIIE_BMBURSTDONEIE)
+
+#define ESPIWE_PBMRX BIT(NPCX_ESPIWE_PBMRXWE)
+#define ESPIWE_PMSGRX BIT(NPCX_ESPIWE_PMSGRXWE)
 
 /* Bit field manipulation for VWEVMS Value */
-#define VWEVMS_WK_EN(e)			(((e)<<20) & 0x00100000)
-#define VWEVMS_INTWK_EN(e)		(VWEVMS_INT_EN(e) | VWEVMS_WK_EN(e))
+#define VWEVMS_WK_EN(e) (((e) << 20) & 0x00100000)
+#define VWEVMS_INTWK_EN(e) (VWEVMS_INT_EN(e) | VWEVMS_WK_EN(e))
 
 /* eSPI max supported frequency */
 enum {
@@ -418,66 +430,71 @@ enum {
 	NPCX_ESPI_MAXFREQ_25 = 1,
 	NPCX_ESPI_MAXFREQ_33 = 2,
 	NPCX_ESPI_MAXFREQ_50 = 3,
+	NPCX_ESPI_MAXFREQ_66 = 4,
 	NPCX_ESPI_MAXFREQ_NONE = 0xFF
 };
 
+/* eSPI Operating Frequency */
+enum {
+	NPCX_ESPI_OPFREQ_20 = 0,
+	NPCX_ESPI_OPFREQ_25 = 1,
+	NPCX_ESPI_OPFREQ_33 = 2,
+	NPCX_ESPI_OPFREQ_50 = 3,
+	NPCX_ESPI_OPFREQ_66 = 4,
+	NPCX_ESPI_OPFREQ_NONE = 0xFF
+};
+
 /* eSPI max frequency support per FMCLK */
 #if (FMCLK <= 33000000)
-#define NPCX_ESPI_MAXFREQ_MAX		NPCX_ESPI_MAXFREQ_33
+#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_33
 #else
-#define NPCX_ESPI_MAXFREQ_MAX		NPCX_ESPI_MAXFREQ_50
+#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_50
 #endif
 
 /* UART registers */
-#define NPCX_UART_WK_GROUP		MIWU_GROUP_8
-#define NPCX_UART_WK_BIT		7
-#define NPCX_UART2_WK_GROUP		MIWU_GROUP_1
-#define NPCX_UART2_WK_BIT		6
+#define NPCX_UART_WK_GROUP MIWU_GROUP_8
+#define NPCX_UART_WK_BIT 7
+#define NPCX_UART2_WK_GROUP MIWU_GROUP_1
+#define NPCX_UART2_WK_BIT 6
 
 /* MIWU registers */
-#define NPCX_WKEDG_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x00 + \
-					((n) * 0x10))
-#define NPCX_WKAEDG_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x01 + \
-					((n) * 0x10))
-#define NPCX_WKMOD_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x02 + \
-					((n) * 0x10))
-#define NPCX_WKPND_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x03 + \
-					((n) * 0x10))
-#define NPCX_WKPCL_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x04 + \
-					((n) * 0x10))
-#define NPCX_WKEN_ADDR(port, n)		(NPCX_MIWU_BASE_ADDR(port) + 0x05 + \
-					((n) * 0x10))
-#define NPCX_WKST_ADDR(port, n)		(NPCX_MIWU_BASE_ADDR(port) + 0x06 + \
-					((n) * 0x10))
-#define NPCX_WKINEN_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x07 + \
-					((n) * 0x10))
-
-#define NPCX_WKEDG(port, n)		REG8(NPCX_WKEDG_ADDR(port, n))
-#define NPCX_WKAEDG(port, n)		REG8(NPCX_WKAEDG_ADDR(port, n))
-#define NPCX_WKPND(port, n)		REG8(NPCX_WKPND_ADDR(port, n))
-#define NPCX_WKPCL(port, n)		REG8(NPCX_WKPCL_ADDR(port, n))
-#define NPCX_WKEN(port, n)		REG8(NPCX_WKEN_ADDR(port, n))
-#define NPCX_WKST(port, n)		REG8(NPCX_WKST_ADDR(port, n))
-#define NPCX_WKINEN(port, n)		REG8(NPCX_WKINEN_ADDR(port, n))
-#define NPCX_WKMOD(port, n)		REG8(NPCX_WKMOD_ADDR(port, n))
+#define NPCX_WKEDG_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x00 + ((n)*0x10))
+#define NPCX_WKAEDG_ADDR(port, n) \
+	(NPCX_MIWU_BASE_ADDR(port) + 0x01 + ((n)*0x10))
+#define NPCX_WKMOD_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x02 + ((n)*0x10))
+#define NPCX_WKPND_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x03 + ((n)*0x10))
+#define NPCX_WKPCL_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x04 + ((n)*0x10))
+#define NPCX_WKEN_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x05 + ((n)*0x10))
+#define NPCX_WKST_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x06 + ((n)*0x10))
+#define NPCX_WKINEN_ADDR(port, n) \
+	(NPCX_MIWU_BASE_ADDR(port) + 0x07 + ((n)*0x10))
+
+#define NPCX_WKEDG(port, n) REG8(NPCX_WKEDG_ADDR(port, n))
+#define NPCX_WKAEDG(port, n) REG8(NPCX_WKAEDG_ADDR(port, n))
+#define NPCX_WKPND(port, n) REG8(NPCX_WKPND_ADDR(port, n))
+#define NPCX_WKPCL(port, n) REG8(NPCX_WKPCL_ADDR(port, n))
+#define NPCX_WKEN(port, n) REG8(NPCX_WKEN_ADDR(port, n))
+#define NPCX_WKST(port, n) REG8(NPCX_WKST_ADDR(port, n))
+#define NPCX_WKINEN(port, n) REG8(NPCX_WKINEN_ADDR(port, n))
+#define NPCX_WKMOD(port, n) REG8(NPCX_WKMOD_ADDR(port, n))
 
 /* LCT register */
-#define NPCX_LCTCONT			REG8(NPCX_LCT_BASE_ADDR + 0x002)
-#define NPCX_LCTSTAT			REG8(NPCX_LCT_BASE_ADDR + 0x004)
-#define NPCX_LCTSECOND			REG8(NPCX_LCT_BASE_ADDR + 0x005)
-#define NPCX_LCTMINUTE			REG8(NPCX_LCT_BASE_ADDR + 0x006)
-#define NPCX_LCTHOUR			REG8(NPCX_LCT_BASE_ADDR + 0x008)
-#define NPCX_LCTDAY			REG8(NPCX_LCT_BASE_ADDR + 0x00A)
-#define NPCX_LCTWEEK			REG8(NPCX_LCT_BASE_ADDR + 0x00C)
+#define NPCX_LCTCONT REG8(NPCX_LCT_BASE_ADDR + 0x002)
+#define NPCX_LCTSTAT REG8(NPCX_LCT_BASE_ADDR + 0x004)
+#define NPCX_LCTSECOND REG8(NPCX_LCT_BASE_ADDR + 0x005)
+#define NPCX_LCTMINUTE REG8(NPCX_LCT_BASE_ADDR + 0x006)
+#define NPCX_LCTHOUR REG8(NPCX_LCT_BASE_ADDR + 0x008)
+#define NPCX_LCTDAY REG8(NPCX_LCT_BASE_ADDR + 0x00A)
+#define NPCX_LCTWEEK REG8(NPCX_LCT_BASE_ADDR + 0x00C)
 /* LCTCONT fields */
-#define NPCX_LCTCONT_EN			0
-#define NPCX_LCTCONT_EN_FIELD		FIELD(0, 1)
-#define NPCX_LCTCONT_EVEN		1
-#define NPCX_LCTCONT_PSL_EN		2
-#define NPCX_LCTCONT_CLK_EN		6
-#define NPCX_LCTCONT_VSBY_PWR		7
+#define NPCX_LCTCONT_EN 0
+#define NPCX_LCTCONT_EN_FIELD FIELD(0, 1)
+#define NPCX_LCTCONT_EVEN 1
+#define NPCX_LCTCONT_PSL_EN 2
+#define NPCX_LCTCONT_CLK_EN 6
+#define NPCX_LCTCONT_VSBY_PWR 7
 /* LCTSTAT fields */
-#define NPCX_LCTSTAT_EVST		0
+#define NPCX_LCTSTAT_EVST 0
 
 /* UART registers and functions */
 #if NPCX_UART_MODULE2
@@ -486,73 +503,73 @@ enum {
  * always 1 == MIWU_TABLE_1.
  */
 #define NPCX_UART_MIWU_IRQ NPCX_IRQ_WKINTG_1
-#define NPCX_UART_DEVALT		NPCX_DEVALT(ALT_GROUP_J)
-#define NPCX_UART_DEVALT_SIN_SL		NPCX_DEVALTJ_CR_SIN1_SL2
-#define NPCX_UART_DEVALT_SOUT_SL	NPCX_DEVALTJ_CR_SOUT1_SL2
-#define NPCX_UART_ALT_DEVALT		NPCX_DEVALT(ALT_GROUP_J)
-#define NPCX_UART_ALT_DEVALT_SIN_SL	NPCX_DEVALTJ_CR_SIN1_SL1
-#define NPCX_UART_ALT_DEVALT_SOUT_SL	NPCX_DEVALTJ_CR_SOUT1_SL1
+#define NPCX_UART_DEVALT NPCX_DEVALT(ALT_GROUP_J)
+#define NPCX_UART_DEVALT_SIN_SL NPCX_DEVALTJ_CR_SIN1_SL2
+#define NPCX_UART_DEVALT_SOUT_SL NPCX_DEVALTJ_CR_SOUT1_SL2
+#define NPCX_UART_ALT_DEVALT NPCX_DEVALT(ALT_GROUP_J)
+#define NPCX_UART_ALT_DEVALT_SIN_SL NPCX_DEVALTJ_CR_SIN1_SL1
+#define NPCX_UART_ALT_DEVALT_SOUT_SL NPCX_DEVALTJ_CR_SOUT1_SL1
 #else /* !NPCX_UART_MODULE2 */
-#define NPCX_UART_MIWU_IRQ		NPCX_IRQ_WKINTB_1
-#define NPCX_UART_DEVALT		NPCX_DEVALT(ALT_GROUP_J)
-#define NPCX_UART_DEVALT_SIN_SL		NPCX_DEVALTJ_CR_SIN1_SL1
-#define NPCX_UART_DEVALT_SOUT_SL	NPCX_DEVALTJ_CR_SOUT1_SL1
-#define NPCX_UART_ALT_DEVALT		NPCX_DEVALT(ALT_GROUP_J)
-#define NPCX_UART_ALT_DEVALT_SIN_SL	NPCX_DEVALTJ_CR_SIN1_SL2
-#define NPCX_UART_ALT_DEVALT_SOUT_SL	NPCX_DEVALTJ_CR_SOUT1_SL2
+#define NPCX_UART_MIWU_IRQ NPCX_IRQ_WKINTB_1
+#define NPCX_UART_DEVALT NPCX_DEVALT(ALT_GROUP_J)
+#define NPCX_UART_DEVALT_SIN_SL NPCX_DEVALTJ_CR_SIN1_SL1
+#define NPCX_UART_DEVALT_SOUT_SL NPCX_DEVALTJ_CR_SOUT1_SL1
+#define NPCX_UART_ALT_DEVALT NPCX_DEVALT(ALT_GROUP_J)
+#define NPCX_UART_ALT_DEVALT_SIN_SL NPCX_DEVALTJ_CR_SIN1_SL2
+#define NPCX_UART_ALT_DEVALT_SOUT_SL NPCX_DEVALTJ_CR_SOUT1_SL2
 #endif /* NPCX_UART_MODULE2 */
 
 /* ADC register */
-#define NPCX_ADCSTS		REG16(NPCX_ADC_BASE_ADDR + 0x000)
-#define NPCX_ADCCNF		REG16(NPCX_ADC_BASE_ADDR + 0x002)
-#define NPCX_ATCTL		REG16(NPCX_ADC_BASE_ADDR + 0x004)
-#define NPCX_ASCADD		REG16(NPCX_ADC_BASE_ADDR + 0x006)
-#define NPCX_ADCCS		REG16(NPCX_ADC_BASE_ADDR + 0x008)
-#define NPCX_THRCTS		REG16(NPCX_ADC_BASE_ADDR + 0x01A)
-#define NPCX_ADCCNF2		REG16(NPCX_ADC_BASE_ADDR + 0x020)
-#define NPCX_GENDLY		REG16(NPCX_ADC_BASE_ADDR + 0x022)
-#define NPCX_MEAST		REG16(NPCX_ADC_BASE_ADDR + 0x026)
+#define NPCX_ADCSTS REG16(NPCX_ADC_BASE_ADDR + 0x000)
+#define NPCX_ADCCNF REG16(NPCX_ADC_BASE_ADDR + 0x002)
+#define NPCX_ATCTL REG16(NPCX_ADC_BASE_ADDR + 0x004)
+#define NPCX_ASCADD REG16(NPCX_ADC_BASE_ADDR + 0x006)
+#define NPCX_ADCCS REG16(NPCX_ADC_BASE_ADDR + 0x008)
+#define NPCX_THRCTS REG16(NPCX_ADC_BASE_ADDR + 0x01A)
+#define NPCX_ADCCNF2 REG16(NPCX_ADC_BASE_ADDR + 0x020)
+#define NPCX_GENDLY REG16(NPCX_ADC_BASE_ADDR + 0x022)
+#define NPCX_MEAST REG16(NPCX_ADC_BASE_ADDR + 0x026)
 /* NOTE: This is 0-based for the ADC channels. */
-#define NPCX_CHNDAT(n)		REG16(NPCX_ADC_BASE_ADDR + 0x040 + (2L*(n)))
+#define NPCX_CHNDAT(n) REG16(NPCX_ADC_BASE_ADDR + 0x040 + (2L * (n)))
 /* NOTE: These are 1-based for the threshold detectors. */
-#define NPCX_THRCTL(n)		REG16(NPCX_ADC_BASE_ADDR + 0x05E + (2L*(n)))
+#define NPCX_THRCTL(n) REG16(NPCX_ADC_BASE_ADDR + 0x05E + (2L * (n)))
 
 /* ADC register fields */
-#define NPCX_ADCSTS_EOCEV		0
-#define NPCX_ADCCNF_ADCMD_FIELD		FIELD(1, 2)
-#define NPCX_ADCCNF_ADCRPTC		3
-#define NPCX_ADCCNF_INTECEN		6
-#define NPCX_ADCCNF_START		4
-#define NPCX_ADCCNF_ADCEN		0
-#define NPCX_ADCCNF_STOP		11
-#define NPCX_ATCTL_SCLKDIV_FIELD	FIELD(0, 6)
-#define NPCX_ATCTL_DLY_FIELD		FIELD(8, 3)
-#define NPCX_ASCADD_SADDR_FIELD		FIELD(0, 5)
-#define NPCX_THRCTS_ADC_WKEN		15
-#define NPCX_THRCTS_THR6_IEN		13
-#define NPCX_THRCTS_THR5_IEN		12
-#define NPCX_THRCTS_THR4_IEN		11
-#define NPCX_THRCTS_THR3_IEN		10
-#define NPCX_THRCTS_THR2_IEN		9
-#define NPCX_THRCTS_THR1_IEN		8
-#define NPCX_THRCTS_ADC_EVENT		7
-#define NPCX_THRCTS_THR6_STS		5
-#define NPCX_THRCTS_THR5_STS		4
-#define NPCX_THRCTS_THR4_STS		3
-#define NPCX_THRCTS_THR3_STS		2
-#define NPCX_THRCTS_THR2_STS		1
-#define NPCX_THRCTS_THR1_STS		0
-#define NPCX_CHNDAT_CHDAT_FIELD		FIELD(0, 10)
-#define NPCX_CHNDAT_NEW			15
-#define NPCX_THRCTL_THEN		15
-#define NPCX_THRCTL_L_H			14
-#define NPCX_THRCTL_CHNSEL		FIELD(10, 4)
-#define NPCX_THRCTL_THRVAL		FIELD(0, 10)
-
-#define NPCX_ADC_THRESH1		1
-#define NPCX_ADC_THRESH2		2
-#define NPCX_ADC_THRESH3		3
-#define NPCX_ADC_THRESH4		4
-#define NPCX_ADC_THRESH5		5
-#define NPCX_ADC_THRESH6		6
-#define NPCX_ADC_THRESH_CNT		6
+#define NPCX_ADCSTS_EOCEV 0
+#define NPCX_ADCCNF_ADCMD_FIELD FIELD(1, 2)
+#define NPCX_ADCCNF_ADCRPTC 3
+#define NPCX_ADCCNF_INTECEN 6
+#define NPCX_ADCCNF_START 4
+#define NPCX_ADCCNF_ADCEN 0
+#define NPCX_ADCCNF_STOP 11
+#define NPCX_ATCTL_SCLKDIV_FIELD FIELD(0, 6)
+#define NPCX_ATCTL_DLY_FIELD FIELD(8, 3)
+#define NPCX_ASCADD_SADDR_FIELD FIELD(0, 5)
+#define NPCX_THRCTS_ADC_WKEN 15
+#define NPCX_THRCTS_THR6_IEN 13
+#define NPCX_THRCTS_THR5_IEN 12
+#define NPCX_THRCTS_THR4_IEN 11
+#define NPCX_THRCTS_THR3_IEN 10
+#define NPCX_THRCTS_THR2_IEN 9
+#define NPCX_THRCTS_THR1_IEN 8
+#define NPCX_THRCTS_ADC_EVENT 7
+#define NPCX_THRCTS_THR6_STS 5
+#define NPCX_THRCTS_THR5_STS 4
+#define NPCX_THRCTS_THR4_STS 3
+#define NPCX_THRCTS_THR3_STS 2
+#define NPCX_THRCTS_THR2_STS 1
+#define NPCX_THRCTS_THR1_STS 0
+#define NPCX_CHNDAT_CHDAT_FIELD FIELD(0, 10)
+#define NPCX_CHNDAT_NEW 15
+#define NPCX_THRCTL_THEN 15
+#define NPCX_THRCTL_L_H 14
+#define NPCX_THRCTL_CHNSEL FIELD(10, 4)
+#define NPCX_THRCTL_THRVAL FIELD(0, 10)
+
+#define NPCX_ADC_THRESH1 1
+#define NPCX_ADC_THRESH2 2
+#define NPCX_ADC_THRESH3 3
+#define NPCX_ADC_THRESH4 4
+#define NPCX_ADC_THRESH5 5
+#define NPCX_ADC_THRESH6 6
+#define NPCX_ADC_THRESH_CNT 6
diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h
index 403d40b4a3..c99fb76bf3 100644
--- a/chip/npcx/registers.h
+++ b/chip/npcx/registers.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,37 +8,41 @@
 #ifndef __CROS_EC_REGISTERS_H
 #define __CROS_EC_REGISTERS_H
 
+#include "clock_chip.h"
 #include "common.h"
 #include "compile_time_macros.h"
-#include "clock_chip.h"
 
 /******************************************************************************/
 /*
  * Macro Functions
  */
 /* Bit functions */
-#define SET_BIT(reg, bit)           ((reg) |= (0x1 << (bit)))
-#define CLEAR_BIT(reg, bit)         ((reg) &= (~(0x1 << (bit))))
-#define IS_BIT_SET(reg, bit)        (((reg) >> (bit)) & (0x1))
-#define UPDATE_BIT(reg, bit, cond)  {	if (cond) \
-						SET_BIT(reg, bit); \
-					else \
-						CLEAR_BIT(reg, bit); }
+#define SET_BIT(reg, bit) ((reg) |= (0x1 << (bit)))
+#define CLEAR_BIT(reg, bit) ((reg) &= (~(0x1 << (bit))))
+#define IS_BIT_SET(reg, bit) (((reg) >> (bit)) & (0x1))
+#define UPDATE_BIT(reg, bit, cond)           \
+	{                                    \
+		if (cond)                    \
+			SET_BIT(reg, bit);   \
+		else                         \
+			CLEAR_BIT(reg, bit); \
+	}
 /* Field functions */
-#define GET_POS_FIELD(pos, size)    pos
-#define GET_SIZE_FIELD(pos, size)   size
-#define FIELD_POS(field)            GET_POS_##field
-#define FIELD_SIZE(field)           GET_SIZE_##field
+#define GET_POS_FIELD(pos, size) pos
+#define GET_SIZE_FIELD(pos, size) size
+#define FIELD_POS(field) GET_POS_##field
+#define FIELD_SIZE(field) GET_SIZE_##field
 /* Read field functions */
 #define GET_FIELD(reg, field) \
 	_GET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field))
-#define _GET_FIELD_(reg, f_pos, f_size) (((reg)>>(f_pos)) & ((1<<(f_size))-1))
+#define _GET_FIELD_(reg, f_pos, f_size) \
+	(((reg) >> (f_pos)) & ((1 << (f_size)) - 1))
 /* Write field functions */
 #define SET_FIELD(reg, field, value) \
 	_SET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field), value)
-#define _SET_FIELD_(reg, f_pos, f_size, value) \
-	((reg) = ((reg) & (~(((1 << (f_size))-1) << (f_pos)))) \
-			| ((value) << (f_pos)))
+#define _SET_FIELD_(reg, f_pos, f_size, value)                     \
+	((reg) = ((reg) & (~(((1 << (f_size)) - 1) << (f_pos)))) | \
+		 ((value) << (f_pos)))
 
 /******************************************************************************/
 /*
@@ -46,224 +50,212 @@
  */
 
 /* Global Definition */
-#define I2C_7BITS_ADDR                   0
+#define I2C_7BITS_ADDR 0
 /* Switcher of features */
-#define SUPPORT_LCT                      1
-#define SUPPORT_WDG                      1
-#define SUPPORT_P80_SEG                  0 /* Note: it uses KSO10 & KSO11 */
+#define SUPPORT_LCT 1
+#define SUPPORT_WDG 1
+#define SUPPORT_P80_SEG 0 /* Note: it uses KSO10 & KSO11 */
 /* Switcher of debugging */
-#define DEBUG_GPIO                       0
-#define DEBUG_I2C                        0
-#define DEBUG_TMR                        0
-#define DEBUG_WDG                        0
-#define DEBUG_FAN                        0
-#define DEBUG_PWM                        0
-#define DEBUG_SPI                        0
-#define DEBUG_FLH                        0
-#define DEBUG_PECI                       0
-#define DEBUG_SHI                        0
-#define DEBUG_CLK                        0
-#define DEBUG_LPC                        0
-#define DEBUG_ESPI                       0
-#define DEBUG_CEC                        0
-#define DEBUG_SIB                        0
-#define DEBUG_PS2                        0
+#define DEBUG_GPIO 0
+#define DEBUG_I2C 0
+#define DEBUG_TMR 0
+#define DEBUG_WDG 0
+#define DEBUG_FAN 0
+#define DEBUG_PWM 0
+#define DEBUG_SPI 0
+#define DEBUG_FLH 0
+#define DEBUG_PECI 0
+#define DEBUG_SHI 0
+#define DEBUG_CLK 0
+#define DEBUG_LPC 0
+#define DEBUG_ESPI 0
+#define DEBUG_CEC 0
+#define DEBUG_SIB 0
+#define DEBUG_PS2 0
 
 /* Modules Map */
-#define NPCX_ESPI_BASE_ADDR              0x4000A000
-#define NPCX_MDC_BASE_ADDR               0x4000C000
-#define NPCX_PMC_BASE_ADDR               0x4000D000
-#define NPCX_SIB_BASE_ADDR               0x4000E000
-#define NPCX_SHI_BASE_ADDR               0x4000F000
-#define NPCX_SHM_BASE_ADDR               0x40010000
-#define NPCX_GDMA_BASE_ADDR              0x40011000
-#define NPCX_FIU_BASE_ADDR               0x40020000
-#define NPCX_KBSCAN_REGS_BASE            0x400A3000
-#define NPCX_WOV_BASE_ADDR               0x400A4000
-#define NPCX_APM_BASE_ADDR               0x400A4800
-#define NPCX_GLUE_REGS_BASE              0x400A5000
-#define NPCX_BBRAM_BASE_ADDR             0x400AF000
-#define NPCX_PS2_BASE_ADDR               0x400B1000
-#define NPCX_HFCG_BASE_ADDR              0x400B5000
-#define NPCX_LFCG_BASE_ADDR              0x400B5100
-#define NPCX_FMUL2_BASE_ADDR             0x400B5200
-#define NPCX_MTC_BASE_ADDR               0x400B7000
-#define NPCX_MSWC_BASE_ADDR              0x400C1000
-#define NPCX_SCFG_BASE_ADDR              0x400C3000
-#define NPCX_KBC_BASE_ADDR               0x400C7000
-#define NPCX_ADC_BASE_ADDR               0x400D1000
-#define NPCX_SPI_BASE_ADDR               0x400D2000
-#define NPCX_PECI_BASE_ADDR              0x400D4000
-#define NPCX_TWD_BASE_ADDR               0x400D8000
+#define NPCX_ESPI_BASE_ADDR 0x4000A000
+#define NPCX_MDC_BASE_ADDR 0x4000C000
+#define NPCX_PMC_BASE_ADDR 0x4000D000
+#define NPCX_SIB_BASE_ADDR 0x4000E000
+#define NPCX_SHI_BASE_ADDR 0x4000F000
+#define NPCX_SHM_BASE_ADDR 0x40010000
+#define NPCX_GDMA_BASE_ADDR 0x40011000
+#define NPCX_FIU_BASE_ADDR 0x40020000
+#define NPCX_KBSCAN_REGS_BASE 0x400A3000
+#define NPCX_WOV_BASE_ADDR 0x400A4000
+#define NPCX_APM_BASE_ADDR 0x400A4800
+#define NPCX_GLUE_REGS_BASE 0x400A5000
+#define NPCX_BBRAM_BASE_ADDR 0x400AF000
+#define NPCX_PS2_BASE_ADDR 0x400B1000
+#define NPCX_HFCG_BASE_ADDR 0x400B5000
+#define NPCX_LFCG_BASE_ADDR 0x400B5100
+#define NPCX_FMUL2_BASE_ADDR 0x400B5200
+#define NPCX_MTC_BASE_ADDR 0x400B7000
+#define NPCX_MSWC_BASE_ADDR 0x400C1000
+#define NPCX_SCFG_BASE_ADDR 0x400C3000
+#define NPCX_KBC_BASE_ADDR 0x400C7000
+#define NPCX_ADC_BASE_ADDR 0x400D1000
+#define NPCX_SPI_BASE_ADDR 0x400D2000
+#define NPCX_PECI_BASE_ADDR 0x400D4000
+#define NPCX_TWD_BASE_ADDR 0x400D8000
 
 /* Multi-Modules Map */
-#define NPCX_PWM_BASE_ADDR(mdl)          (0x40080000 + ((mdl) * 0x2000L))
-#define NPCX_GPIO_BASE_ADDR(mdl)         (0x40081000 + ((mdl) * 0x2000L))
-#define NPCX_ITIM_BASE_ADDR(mdl)         (0x400B0000 + ((mdl) * 0x2000L))
-#define NPCX_MIWU_BASE_ADDR(mdl)         (0x400BB000 + ((mdl) * 0x2000L))
-#define NPCX_MFT_BASE_ADDR(mdl)          (0x400E1000 + ((mdl) * 0x2000L))
-#define NPCX_PM_CH_BASE_ADDR(mdl)        (0x400C9000 + ((mdl) * 0x2000L))
+#define NPCX_PWM_BASE_ADDR(mdl) (0x40080000 + ((mdl)*0x2000L))
+#define NPCX_GPIO_BASE_ADDR(mdl) (0x40081000 + ((mdl)*0x2000L))
+#define NPCX_ITIM_BASE_ADDR(mdl) (0x400B0000 + ((mdl)*0x2000L))
+#define NPCX_MIWU_BASE_ADDR(mdl) (0x400BB000 + ((mdl)*0x2000L))
+#define NPCX_MFT_BASE_ADDR(mdl) (0x400E1000 + ((mdl)*0x2000L))
+#define NPCX_PM_CH_BASE_ADDR(mdl) (0x400C9000 + ((mdl)*0x2000L))
 
 /*
  * NPCX-IRQ numbers
  */
-#define NPCX_IRQ_0                       0
-#define NPCX_IRQ_1                       1
-#define NPCX_IRQ_2                       2
-#define NPCX_IRQ_3                       3
-#define NPCX_IRQ_4                       4
-#define NPCX_IRQ_5                       5
-#define NPCX_IRQ_6                       6
-#define NPCX_IRQ_7                       7
-#define NPCX_IRQ_8                       8
-#define NPCX_IRQ_9                       9
-#define NPCX_IRQ_10                      10
-#define NPCX_IRQ_11                      11
-#define NPCX_IRQ_12                      12
-#define NPCX_IRQ_13                      13
-#define NPCX_IRQ_14                      14
-#define NPCX_IRQ_15                      15
-#define NPCX_IRQ_16                      16
-#define NPCX_IRQ_17                      17
-#define NPCX_IRQ_18                      18
-#define NPCX_IRQ_19                      19
-#define NPCX_IRQ_20                      20
-#define NPCX_IRQ_21                      21
-#define NPCX_IRQ_22                      22
-#define NPCX_IRQ_23                      23
-#define NPCX_IRQ_24                      24
-#define NPCX_IRQ_25                      25
-#define NPCX_IRQ_26                      26
-#define NPCX_IRQ_27                      27
-#define NPCX_IRQ_28                      28
-#define NPCX_IRQ_29                      29
-#define NPCX_IRQ_30                      30
-#define NPCX_IRQ_31                      31
-#define NPCX_IRQ_32                      32
-#define NPCX_IRQ_33                      33
-#define NPCX_IRQ_34                      34
-#define NPCX_IRQ_35                      35
-#define NPCX_IRQ_36                      36
-#define NPCX_IRQ_37                      37
-#define NPCX_IRQ_38                      38
-#define NPCX_IRQ_39                      39
-#define NPCX_IRQ_40                      40
-#define NPCX_IRQ_41                      41
-#define NPCX_IRQ_42                      42
-#define NPCX_IRQ_43                      43
-#define NPCX_IRQ_44                      44
-#define NPCX_IRQ_45                      45
-#define NPCX_IRQ_46                      46
-#define NPCX_IRQ_47                      47
-#define NPCX_IRQ_48                      48
-#define NPCX_IRQ_49                      49
-#define NPCX_IRQ_50                      50
-#define NPCX_IRQ_51                      51
-#define NPCX_IRQ_52                      52
-#define NPCX_IRQ_53                      53
-#define NPCX_IRQ_54                      54
-#define NPCX_IRQ_55                      55
-#define NPCX_IRQ_56                      56
-#define NPCX_IRQ_57                      57
-#define NPCX_IRQ_58                      58
-#define NPCX_IRQ_59                      59
-#define NPCX_IRQ_60                      60
-#define NPCX_IRQ_61                      61
-#define NPCX_IRQ_62                      62
-#define NPCX_IRQ_63                      63
-
-#define NPCX_IRQ_COUNT                   64
-
-/******************************************************************************/
-/* Miscellaneous Device Control (MDC) registers */
-#define NPCX_FWCTRL                       REG8(NPCX_MDC_BASE_ADDR + 0x007)
-
-/* MDC register fields */
-#define NPCX_FWCTRL_RO_REGION            0
-#define NPCX_FWCTRL_FW_SLOT              1
+#define NPCX_IRQ_0 0
+#define NPCX_IRQ_1 1
+#define NPCX_IRQ_2 2
+#define NPCX_IRQ_3 3
+#define NPCX_IRQ_4 4
+#define NPCX_IRQ_5 5
+#define NPCX_IRQ_6 6
+#define NPCX_IRQ_7 7
+#define NPCX_IRQ_8 8
+#define NPCX_IRQ_9 9
+#define NPCX_IRQ_10 10
+#define NPCX_IRQ_11 11
+#define NPCX_IRQ_12 12
+#define NPCX_IRQ_13 13
+#define NPCX_IRQ_14 14
+#define NPCX_IRQ_15 15
+#define NPCX_IRQ_16 16
+#define NPCX_IRQ_17 17
+#define NPCX_IRQ_18 18
+#define NPCX_IRQ_19 19
+#define NPCX_IRQ_20 20
+#define NPCX_IRQ_21 21
+#define NPCX_IRQ_22 22
+#define NPCX_IRQ_23 23
+#define NPCX_IRQ_24 24
+#define NPCX_IRQ_25 25
+#define NPCX_IRQ_26 26
+#define NPCX_IRQ_27 27
+#define NPCX_IRQ_28 28
+#define NPCX_IRQ_29 29
+#define NPCX_IRQ_30 30
+#define NPCX_IRQ_31 31
+#define NPCX_IRQ_32 32
+#define NPCX_IRQ_33 33
+#define NPCX_IRQ_34 34
+#define NPCX_IRQ_35 35
+#define NPCX_IRQ_36 36
+#define NPCX_IRQ_37 37
+#define NPCX_IRQ_38 38
+#define NPCX_IRQ_39 39
+#define NPCX_IRQ_40 40
+#define NPCX_IRQ_41 41
+#define NPCX_IRQ_42 42
+#define NPCX_IRQ_43 43
+#define NPCX_IRQ_44 44
+#define NPCX_IRQ_45 45
+#define NPCX_IRQ_46 46
+#define NPCX_IRQ_47 47
+#define NPCX_IRQ_48 48
+#define NPCX_IRQ_49 49
+#define NPCX_IRQ_50 50
+#define NPCX_IRQ_51 51
+#define NPCX_IRQ_52 52
+#define NPCX_IRQ_53 53
+#define NPCX_IRQ_54 54
+#define NPCX_IRQ_55 55
+#define NPCX_IRQ_56 56
+#define NPCX_IRQ_57 57
+#define NPCX_IRQ_58 58
+#define NPCX_IRQ_59 59
+#define NPCX_IRQ_60 60
+#define NPCX_IRQ_61 61
+#define NPCX_IRQ_62 62
+#define NPCX_IRQ_63 63
+
+#define NPCX_IRQ_COUNT 64
 
 /******************************************************************************/
 /* High Frequency Clock Generator (HFCG) registers */
-#define NPCX_HFCGCTRL                     REG8(NPCX_HFCG_BASE_ADDR + 0x000)
-#define NPCX_HFCGML                       REG8(NPCX_HFCG_BASE_ADDR + 0x002)
-#define NPCX_HFCGMH                       REG8(NPCX_HFCG_BASE_ADDR + 0x004)
-#define NPCX_HFCGN                        REG8(NPCX_HFCG_BASE_ADDR + 0x006)
-#define NPCX_HFCGP                        REG8(NPCX_HFCG_BASE_ADDR + 0x008)
-#define NPCX_HFCBCD                       REG8(NPCX_HFCG_BASE_ADDR + 0x010)
+#define NPCX_HFCGCTRL REG8(NPCX_HFCG_BASE_ADDR + 0x000)
+#define NPCX_HFCGML REG8(NPCX_HFCG_BASE_ADDR + 0x002)
+#define NPCX_HFCGMH REG8(NPCX_HFCG_BASE_ADDR + 0x004)
+#define NPCX_HFCGN REG8(NPCX_HFCG_BASE_ADDR + 0x006)
+#define NPCX_HFCGP REG8(NPCX_HFCG_BASE_ADDR + 0x008)
+#define NPCX_HFCBCD REG8(NPCX_HFCG_BASE_ADDR + 0x010)
 
 /* HFCG register fields */
-#define NPCX_HFCGCTRL_LOAD               0
-#define NPCX_HFCGCTRL_LOCK               2
-#define NPCX_HFCGCTRL_CLK_CHNG           7
+#define NPCX_HFCGCTRL_LOAD 0
+#define NPCX_HFCGCTRL_LOCK 2
+#define NPCX_HFCGCTRL_CLK_CHNG 7
 
 /******************************************************************************/
 /* Low Frequency Clock Generator (LFCG) registers */
-#define NPCX_LFCGCTL                      REG8(NPCX_LFCG_BASE_ADDR + 0x000)
-#define NPCX_HFRDI                       REG16(NPCX_LFCG_BASE_ADDR + 0x002)
-#define NPCX_HFRDF                       REG16(NPCX_LFCG_BASE_ADDR + 0x004)
-#define NPCX_FRCDIV                      REG16(NPCX_LFCG_BASE_ADDR + 0x006)
-#define NPCX_DIVCOR1                     REG16(NPCX_LFCG_BASE_ADDR + 0x008)
-#define NPCX_DIVCOR2                     REG16(NPCX_LFCG_BASE_ADDR + 0x00A)
-#define NPCX_LFCGCTL2                     REG8(NPCX_LFCG_BASE_ADDR + 0x014)
+#define NPCX_LFCGCTL REG8(NPCX_LFCG_BASE_ADDR + 0x000)
+#define NPCX_HFRDI REG16(NPCX_LFCG_BASE_ADDR + 0x002)
+#define NPCX_HFRDF REG16(NPCX_LFCG_BASE_ADDR + 0x004)
+#define NPCX_FRCDIV REG16(NPCX_LFCG_BASE_ADDR + 0x006)
+#define NPCX_DIVCOR1 REG16(NPCX_LFCG_BASE_ADDR + 0x008)
+#define NPCX_DIVCOR2 REG16(NPCX_LFCG_BASE_ADDR + 0x00A)
+#define NPCX_LFCGCTL2 REG8(NPCX_LFCG_BASE_ADDR + 0x014)
 
 /* LFCG register fields */
-#define NPCX_LFCGCTL_XTCLK_VAL            7
-#define NPCX_LFCGCTL2_XT_OSC_SL_EN        6
+#define NPCX_LFCGCTL_XTCLK_VAL 7
+#define NPCX_LFCGCTL2_XT_OSC_SL_EN 6
 
 /******************************************************************************/
 /* CR UART Register */
-#define NPCX_UTBUF(n)                    REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x000)
-#define NPCX_URBUF(n)                    REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x002)
-#define NPCX_UICTRL(n)                   REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x004)
-#define NPCX_USTAT(n)                    REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x006)
-#define NPCX_UFRS(n)                     REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x008)
-#define NPCX_UMDSL(n)                    REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x00A)
-#define NPCX_UBAUD(n)                    REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x00C)
-#define NPCX_UPSR(n)                     REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x00E)
+#define NPCX_UTBUF(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x000)
+#define NPCX_URBUF(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x002)
+#define NPCX_UICTRL(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x004)
+#define NPCX_USTAT(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x006)
+#define NPCX_UFRS(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x008)
+#define NPCX_UMDSL(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x00A)
+#define NPCX_UBAUD(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x00C)
+#define NPCX_UPSR(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x00E)
 
 /******************************************************************************/
 /* KBSCAN registers */
-#define NPCX_KBSIN                        REG8(NPCX_KBSCAN_REGS_BASE + 0x04)
-#define NPCX_KBSINPU                      REG8(NPCX_KBSCAN_REGS_BASE + 0x05)
-#define NPCX_KBSOUT0                     REG16(NPCX_KBSCAN_REGS_BASE + 0x06)
-#define NPCX_KBSOUT1                     REG16(NPCX_KBSCAN_REGS_BASE + 0x08)
-#define NPCX_KBS_BUF_INDX                 REG8(NPCX_KBSCAN_REGS_BASE + 0x0A)
-#define NPCX_KBS_BUF_DATA                 REG8(NPCX_KBSCAN_REGS_BASE + 0x0B)
-#define NPCX_KBSEVT                       REG8(NPCX_KBSCAN_REGS_BASE + 0x0C)
-#define NPCX_KBSCTL                       REG8(NPCX_KBSCAN_REGS_BASE + 0x0D)
-#define NPCX_KBS_CFG_INDX                 REG8(NPCX_KBSCAN_REGS_BASE + 0x0E)
-#define NPCX_KBS_CFG_DATA                 REG8(NPCX_KBSCAN_REGS_BASE + 0x0F)
+#define NPCX_KBSIN REG8(NPCX_KBSCAN_REGS_BASE + 0x04)
+#define NPCX_KBSINPU REG8(NPCX_KBSCAN_REGS_BASE + 0x05)
+#define NPCX_KBSOUT0 REG16(NPCX_KBSCAN_REGS_BASE + 0x06)
+#define NPCX_KBSOUT1 REG16(NPCX_KBSCAN_REGS_BASE + 0x08)
+#define NPCX_KBS_BUF_INDX REG8(NPCX_KBSCAN_REGS_BASE + 0x0A)
+#define NPCX_KBS_BUF_DATA REG8(NPCX_KBSCAN_REGS_BASE + 0x0B)
+#define NPCX_KBSEVT REG8(NPCX_KBSCAN_REGS_BASE + 0x0C)
+#define NPCX_KBSCTL REG8(NPCX_KBSCAN_REGS_BASE + 0x0D)
+#define NPCX_KBS_CFG_INDX REG8(NPCX_KBSCAN_REGS_BASE + 0x0E)
+#define NPCX_KBS_CFG_DATA REG8(NPCX_KBSCAN_REGS_BASE + 0x0F)
 
 /* KBSCAN register fields */
-#define NPCX_KBSBUFINDX                  0
-#define NPCX_KBSDONE                     0
-#define NPCX_KBSERR                      1
-#define NPCX_KBSSTART                    0
-#define NPCX_KBSMODE                     1
-#define NPCX_KBSIEN                      2
-#define NPCX_KBSINC                      3
-#define NPCX_KBSCFGINDX                  0
+#define NPCX_KBSBUFINDX 0
+#define NPCX_KBSDONE 0
+#define NPCX_KBSERR 1
+#define NPCX_KBSSTART 0
+#define NPCX_KBSMODE 1
+#define NPCX_KBSIEN 2
+#define NPCX_KBSINC 3
+#define NPCX_KBSCFGINDX 0
 
 /* KBSCAN definitions */
-#define KB_ROW_NUM  8  /* Rows numbers of keyboard matrix */
-#define KB_COL_NUM  18 /* Columns numbers of keyboard matrix */
-#define KB_ROW_MASK ((1<<KB_ROW_NUM) - 1) /* Mask of rows of keyboard matrix */
+#define KB_ROW_NUM 8 /* Rows numbers of keyboard matrix */
+#define KB_COL_NUM 18 /* Columns numbers of keyboard matrix */
+#define KB_ROW_MASK \
+	((1 << KB_ROW_NUM) - 1) /* Mask of rows of keyboard matrix */
 
 /******************************************************************************/
 /* GLUE registers */
-#define NPCX_GLUE_SDPD0                   REG8(NPCX_GLUE_REGS_BASE + 0x010)
-#define NPCX_GLUE_SDPD1                   REG8(NPCX_GLUE_REGS_BASE + 0x012)
-#define NPCX_GLUE_SDP_CTS                 REG8(NPCX_GLUE_REGS_BASE + 0x014)
-#define NPCX_GLUE_SMBSEL                  REG8(NPCX_GLUE_REGS_BASE + 0x021)
+#define NPCX_GLUE_SDPD0 REG8(NPCX_GLUE_REGS_BASE + 0x010)
+#define NPCX_GLUE_SDPD1 REG8(NPCX_GLUE_REGS_BASE + 0x012)
+#define NPCX_GLUE_SDP_CTS REG8(NPCX_GLUE_REGS_BASE + 0x014)
+#define NPCX_GLUE_SMBSEL REG8(NPCX_GLUE_REGS_BASE + 0x021)
 /******************************************************************************/
 
 /* MIWU enumeration */
-enum {
-	MIWU_TABLE_0,
-	MIWU_TABLE_1,
-	MIWU_TABLE_2,
-	MIWU_TABLE_COUNT
-};
+enum { MIWU_TABLE_0, MIWU_TABLE_1, MIWU_TABLE_2, MIWU_TABLE_COUNT };
 
 enum {
 	MIWU_GROUP_1,
@@ -283,19 +275,69 @@ enum {
 	MIWU_EDGE_ANYING,
 };
 
+#define NPCX_MIWU_DEFAULT_PRIORITY 3
+#ifndef NPCX_MIWU0_GROUP_A
+#define NPCX_MIWU0_GROUP_A NPCX_MIWU_DEFAULT_PRIORITY
+#endif
+#ifndef NPCX_MIWU0_GROUP_B
+#define NPCX_MIWU0_GROUP_B NPCX_MIWU_DEFAULT_PRIORITY
+#endif
+#ifndef NPCX_MIWU0_GROUP_C
+#define NPCX_MIWU0_GROUP_C NPCX_MIWU_DEFAULT_PRIORITY
+#endif
+#ifndef NPCX_MIWU0_GROUP_D
+#define NPCX_MIWU0_GROUP_D NPCX_MIWU_DEFAULT_PRIORITY
+#endif
+#ifndef NPCX_MIWU0_GROUP_E
+#define NPCX_MIWU0_GROUP_E NPCX_MIWU_DEFAULT_PRIORITY
+#endif
+#ifndef NPCX_MIWU0_GROUP_F
+#define NPCX_MIWU0_GROUP_F NPCX_MIWU_DEFAULT_PRIORITY
+#endif
+#ifndef NPCX_MIWU0_GROUP_G
+#define NPCX_MIWU0_GROUP_G NPCX_MIWU_DEFAULT_PRIORITY
+#endif
+#ifndef NPCX_MIWU0_GROUP_H
+#define NPCX_MIWU0_GROUP_H NPCX_MIWU_DEFAULT_PRIORITY
+#endif
+#ifndef NPCX_MIWU1_GROUP_A
+#define NPCX_MIWU1_GROUP_A NPCX_MIWU_DEFAULT_PRIORITY
+#endif
+#ifndef NPCX_MIWU1_GROUP_B
+#define NPCX_MIWU1_GROUP_B NPCX_MIWU_DEFAULT_PRIORITY
+#endif
+#ifndef NPCX_MIWU1_GROUP_C
+#define NPCX_MIWU1_GROUP_C NPCX_MIWU_DEFAULT_PRIORITY
+#endif
+#ifndef NPCX_MIWU1_GROUP_D
+#define NPCX_MIWU1_GROUP_D NPCX_MIWU_DEFAULT_PRIORITY
+#endif
+#ifndef NPCX_MIWU1_GROUP_E
+#define NPCX_MIWU1_GROUP_E NPCX_MIWU_DEFAULT_PRIORITY
+#endif
+#ifndef NPCX_MIWU1_GROUP_F
+#define NPCX_MIWU1_GROUP_F NPCX_MIWU_DEFAULT_PRIORITY
+#endif
+#ifndef NPCX_MIWU1_GROUP_G
+#define NPCX_MIWU1_GROUP_G NPCX_MIWU_DEFAULT_PRIORITY
+#endif
+#ifndef NPCX_MIWU1_GROUP_H
+#define NPCX_MIWU1_GROUP_H NPCX_MIWU_DEFAULT_PRIORITY
+#endif
+
 /* MIWU utilities */
 #define MIWU_TABLE_WKKEY MIWU_TABLE_1
 #define MIWU_GROUP_WKKEY MIWU_GROUP_3
 
 /******************************************************************************/
 /* GPIO registers */
-#define NPCX_PDOUT(n)                     REG8(NPCX_GPIO_BASE_ADDR(n) + 0x000)
-#define NPCX_PDIN(n)                      REG8(NPCX_GPIO_BASE_ADDR(n) + 0x001)
-#define NPCX_PDIR(n)                      REG8(NPCX_GPIO_BASE_ADDR(n) + 0x002)
-#define NPCX_PPULL(n)                     REG8(NPCX_GPIO_BASE_ADDR(n) + 0x003)
-#define NPCX_PPUD(n)                      REG8(NPCX_GPIO_BASE_ADDR(n) + 0x004)
-#define NPCX_PENVDD(n)                    REG8(NPCX_GPIO_BASE_ADDR(n) + 0x005)
-#define NPCX_PTYPE(n)                     REG8(NPCX_GPIO_BASE_ADDR(n) + 0x006)
+#define NPCX_PDOUT(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x000)
+#define NPCX_PDIN(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x001)
+#define NPCX_PDIR(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x002)
+#define NPCX_PPULL(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x003)
+#define NPCX_PPUD(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x004)
+#define NPCX_PENVDD(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x005)
+#define NPCX_PTYPE(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x006)
 
 /* GPIO enumeration */
 enum {
@@ -350,927 +392,949 @@ enum {
 
 /******************************************************************************/
 /* MSWC Registers */
-#define NPCX_MSWCTL1                      REG8(NPCX_MSWC_BASE_ADDR + 0x000)
-#define NPCX_MSWCTL2                      REG8(NPCX_MSWC_BASE_ADDR + 0x002)
-#define NPCX_HCBAL                        REG8(NPCX_MSWC_BASE_ADDR + 0x008)
-#define NPCX_HCBAH                        REG8(NPCX_MSWC_BASE_ADDR + 0x00A)
-#define NPCX_SRID_CR                      REG8(NPCX_MSWC_BASE_ADDR + 0x01C)
-#define NPCX_SID_CR                       REG8(NPCX_MSWC_BASE_ADDR + 0x020)
-#define NPCX_DEVICE_ID_CR                 REG8(NPCX_MSWC_BASE_ADDR + 0x022)
+#define NPCX_MSWCTL1 REG8(NPCX_MSWC_BASE_ADDR + 0x000)
+#define NPCX_MSWCTL2 REG8(NPCX_MSWC_BASE_ADDR + 0x002)
+#define NPCX_HCBAL REG8(NPCX_MSWC_BASE_ADDR + 0x008)
+#define NPCX_HCBAH REG8(NPCX_MSWC_BASE_ADDR + 0x00A)
+#define NPCX_SRID_CR REG8(NPCX_MSWC_BASE_ADDR + 0x01C)
+#define NPCX_SID_CR REG8(NPCX_MSWC_BASE_ADDR + 0x020)
+#define NPCX_DEVICE_ID_CR REG8(NPCX_MSWC_BASE_ADDR + 0x022)
 
 /* MSWC register fields */
-#define NPCX_MSWCTL1_HRSTOB              0
-#define NPCS_MSWCTL1_HWPRON              1
-#define NPCX_MSWCTL1_PLTRST_ACT          2
-#define NPCX_MSWCTL1_VHCFGA              3
-#define NPCX_MSWCTL1_HCFGLK              4
-#define NPCX_MSWCTL1_PWROFFB             6
-#define NPCX_MSWCTL1_A20MB               7
+#define NPCX_MSWCTL1_HRSTOB 0
+#define NPCS_MSWCTL1_HWPRON 1
+#define NPCX_MSWCTL1_PLTRST_ACT 2
+#define NPCX_MSWCTL1_VHCFGA 3
+#define NPCX_MSWCTL1_HCFGLK 4
+#define NPCX_MSWCTL1_PWROFFB 6
+#define NPCX_MSWCTL1_A20MB 7
 
 /******************************************************************************/
 /* System Configuration (SCFG) Registers */
-#define NPCX_DEVCNT                       REG8(NPCX_SCFG_BASE_ADDR + 0x000)
-#define NPCX_STRPST                       REG8(NPCX_SCFG_BASE_ADDR + 0x001)
-#define NPCX_RSTCTL                       REG8(NPCX_SCFG_BASE_ADDR + 0x002)
-#define NPCX_DEV_CTL4                     REG8(NPCX_SCFG_BASE_ADDR + 0x006)
-#define NPCX_LFCGCALCNT                   REG8(NPCX_SCFG_BASE_ADDR + 0x021)
-#define NPCX_PUPD_EN0                     REG8(NPCX_SCFG_BASE_ADDR + 0x028)
-#define NPCX_PUPD_EN1                     REG8(NPCX_SCFG_BASE_ADDR + 0x029)
-#define NPCX_SCFG_VER                     REG8(NPCX_SCFG_BASE_ADDR + 0x02F)
-
-#define TEST_BKSL                         REG8(NPCX_SCFG_BASE_ADDR + 0x037)
-#define TEST0                             REG8(NPCX_SCFG_BASE_ADDR + 0x038)
-#define BLKSEL                           0
+#define NPCX_DEVCNT REG8(NPCX_SCFG_BASE_ADDR + 0x000)
+#define NPCX_STRPST REG8(NPCX_SCFG_BASE_ADDR + 0x001)
+#define NPCX_RSTCTL REG8(NPCX_SCFG_BASE_ADDR + 0x002)
+#define NPCX_DEV_CTL4 REG8(NPCX_SCFG_BASE_ADDR + 0x006)
+#define NPCX_LFCGCALCNT REG8(NPCX_SCFG_BASE_ADDR + 0x021)
+#define NPCX_PUPD_EN0 REG8(NPCX_SCFG_BASE_ADDR + 0x028)
+#define NPCX_PUPD_EN1 REG8(NPCX_SCFG_BASE_ADDR + 0x029)
+#define NPCX_SCFG_VER REG8(NPCX_SCFG_BASE_ADDR + 0x02F)
+
+#define TEST_BKSL REG8(NPCX_SCFG_BASE_ADDR + 0x037)
+#define TEST0 REG8(NPCX_SCFG_BASE_ADDR + 0x038)
+#define BLKSEL 0
 
 /* SCFG register fields */
-#define NPCX_DEVCNT_F_SPI_TRIS           6
-#define NPCX_DEVCNT_HIF_TYP_SEL_FIELD    FIELD(2, 2)
-#define NPCX_DEVCNT_JEN1_HEN             5
-#define NPCX_DEVCNT_JEN0_HEN             4
-#define NPCX_STRPST_TRIST                1
-#define NPCX_STRPST_TEST                 2
-#define NPCX_STRPST_JEN1                 4
-#define NPCX_STRPST_JEN0                 5
-#define NPCX_STRPST_SPI_COMP             7
-#define NPCX_RSTCTL_VCC1_RST_STS         0
-#define NPCX_RSTCTL_DBGRST_STS           1
-#define NPCX_RSTCTL_VCC1_RST_SCRATCH     3
-#define NPCX_RSTCTL_LRESET_PLTRST_MODE   5
-#define NPCX_RSTCTL_HIPRST_MODE          6
-#define NPCX_DEV_CTL4_F_SPI_SLLK         2
-#define NPCX_DEV_CTL4_SPI_SP_SEL         4
-#define NPCX_DEV_CTL4_WP_IF              5
-#define NPCX_DEV_CTL4_VCC1_RST_LK        6
-#define NPCX_DEVPU0_I2C0_0_PUE           0
-#define NPCX_DEVPU0_I2C0_1_PUE           1
-#define NPCX_DEVPU0_I2C1_0_PUE           2
-#define NPCX_DEVPU0_I2C2_0_PUE           4
-#define NPCX_DEVPU0_I2C3_0_PUE           6
-#define NPCX_DEVPU1_F_SPI_PUD_EN         7
+#define NPCX_DEVCNT_F_SPI_TRIS 6
+#define NPCX_DEVCNT_HIF_TYP_SEL_FIELD FIELD(2, 2)
+#define NPCX_DEVCNT_JEN1_HEN 5
+#define NPCX_DEVCNT_JEN0_HEN 4
+#define NPCX_STRPST_TRIST 1
+#define NPCX_STRPST_TEST 2
+#define NPCX_STRPST_JEN1 4
+#define NPCX_STRPST_JEN0 5
+#define NPCX_STRPST_SPI_COMP 7
+#define NPCX_RSTCTL_VCC1_RST_STS 0
+#define NPCX_RSTCTL_DBGRST_STS 1
+#define NPCX_RSTCTL_VCC1_RST_SCRATCH 3
+#define NPCX_RSTCTL_LRESET_PLTRST_MODE 5
+#define NPCX_RSTCTL_HIPRST_MODE 6
+#define NPCX_DEV_CTL4_F_SPI_SLLK 2
+#define NPCX_DEV_CTL4_SPI_SP_SEL 4
+#define NPCX_DEV_CTL4_WP_IF 5
+#define NPCX_DEV_CTL4_VCC1_RST_LK 6
+#define NPCX_DEVPU0_I2C0_0_PUE 0
+#define NPCX_DEVPU0_I2C0_1_PUE 1
+#define NPCX_DEVPU0_I2C1_0_PUE 2
+#define NPCX_DEVPU0_I2C2_0_PUE 4
+#define NPCX_DEVPU0_I2C3_0_PUE 6
+#define NPCX_DEVPU1_F_SPI_PUD_EN 7
 
 /* DEVALT */
 /* pin-mux for SPI/FIU */
-#define NPCX_DEVALT0_SPIP_SL             0
-#define NPCX_DEVALT0_GPIO_NO_SPIP        3
-#define NPCX_DEVALT0_F_SPI_CS1_2         4
-#define NPCX_DEVALT0_F_SPI_CS1_1         5
-#define NPCX_DEVALT0_F_SPI_QUAD          6
-#define NPCX_DEVALT0_NO_F_SPI            7
+#define NPCX_DEVALT0_SPIP_SL 0
+#define NPCX_DEVALT0_GPIO_NO_SPIP 3
+#define NPCX_DEVALT0_F_SPI_CS1_2 4
+#define NPCX_DEVALT0_F_SPI_CS1_1 5
+#define NPCX_DEVALT0_F_SPI_QUAD 6
+#define NPCX_DEVALT0_NO_F_SPI 7
 
 /* pin-mux for LPC/eSPI */
-#define NPCX_DEVALT1_KBRST_SL            0
-#define NPCX_DEVALT1_A20M_SL             1
-#define NPCX_DEVALT1_SMI_SL              2
-#define NPCX_DEVALT1_EC_SCI_SL           3
-#define NPCX_DEVALT1_NO_PWRGD            4
-#define NPCX_DEVALT1_RST_OUT_SL          5
-#define NPCX_DEVALT1_CLKRN_SL            6
-#define NPCX_DEVALT1_NO_LPC_ESPI         7
+#define NPCX_DEVALT1_KBRST_SL 0
+#define NPCX_DEVALT1_A20M_SL 1
+#define NPCX_DEVALT1_SMI_SL 2
+#define NPCX_DEVALT1_EC_SCI_SL 3
+#define NPCX_DEVALT1_NO_PWRGD 4
+#define NPCX_DEVALT1_RST_OUT_SL 5
+#define NPCX_DEVALT1_CLKRN_SL 6
+#define NPCX_DEVALT1_NO_LPC_ESPI 7
 
 /* pin-mux for PS2 */
-#define NPCX_DEVALT3_PS2_0_SL            0
-#define NPCX_DEVALT3_PS2_1_SL            1
-#define NPCX_DEVALT3_PS2_2_SL            2
-#define NPCX_DEVALT3_PS2_3_SL            3
-#define NPCX_DEVALTC_PS2_3_SL2           3
+#define NPCX_DEVALT3_PS2_0_SL 0
+#define NPCX_DEVALT3_PS2_1_SL 1
+#define NPCX_DEVALT3_PS2_2_SL 2
+#define NPCX_DEVALT3_PS2_3_SL 3
+#define NPCX_DEVALTC_PS2_3_SL2 3
 
 /* pin-mux for Tacho */
-#define NPCX_DEVALT3_TA1_SL1             4
-#define NPCX_DEVALT3_TB1_SL1             5
-#define NPCX_DEVALT3_TA2_SL1             6
-#define NPCX_DEVALT3_TB2_SL1             7
-#define NPCX_DEVALTC_TA1_SL2             4
-#define NPCX_DEVALTC_TB1_SL2             5
-#define NPCX_DEVALTC_TA2_SL2             6
-#define NPCX_DEVALTC_TB2_SL2             7
+#define NPCX_DEVALT3_TA1_SL1 4
+#define NPCX_DEVALT3_TB1_SL1 5
+#define NPCX_DEVALT3_TA2_SL1 6
+#define NPCX_DEVALT3_TB2_SL1 7
+#define NPCX_DEVALTC_TA1_SL2 4
+#define NPCX_DEVALTC_TB1_SL2 5
+#define NPCX_DEVALTC_TA2_SL2 6
+#define NPCX_DEVALTC_TB2_SL2 7
 
 /* pin-mux for PWM */
-#define NPCX_DEVALT4_PWM0_SL             0
-#define NPCX_DEVALT4_PWM1_SL             1
-#define NPCX_DEVALT4_PWM2_SL             2
-#define NPCX_DEVALT4_PWM3_SL             3
-#define NPCX_DEVALT4_PWM4_SL             4
-#define NPCX_DEVALT4_PWM5_SL             5
-#define NPCX_DEVALT4_PWM6_SL             6
-#define NPCX_DEVALT4_PWM7_SL             7
+#define NPCX_DEVALT4_PWM0_SL 0
+#define NPCX_DEVALT4_PWM1_SL 1
+#define NPCX_DEVALT4_PWM2_SL 2
+#define NPCX_DEVALT4_PWM3_SL 3
+#define NPCX_DEVALT4_PWM4_SL 4
+#define NPCX_DEVALT4_PWM5_SL 5
+#define NPCX_DEVALT4_PWM6_SL 6
+#define NPCX_DEVALT4_PWM7_SL 7
 
 /* pin-mux for JTAG */
-#define NPCX_DEVALT5_TRACE_EN            0
-#define NPCX_DEVALT5_NJEN1_EN            1
-#define NPCX_DEVALT5_NJEN0_EN            2
+#define NPCX_DEVALT5_TRACE_EN 0
 
 /* pin-mux for ADC */
-#define NPCX_DEVALT6_ADC0_SL             0
-#define NPCX_DEVALT6_ADC1_SL             1
-#define NPCX_DEVALT6_ADC2_SL             2
-#define NPCX_DEVALT6_ADC3_SL             3
-#define NPCX_DEVALT6_ADC4_SL             4
+#define NPCX_DEVALT6_ADC0_SL 0
+#define NPCX_DEVALT6_ADC1_SL 1
+#define NPCX_DEVALT6_ADC2_SL 2
+#define NPCX_DEVALT6_ADC3_SL 3
+#define NPCX_DEVALT6_ADC4_SL 4
 
 /* pin-mux for Keyboard */
-#define NPCX_DEVALT7_NO_KSI0_SL          0
-#define NPCX_DEVALT7_NO_KSI1_SL          1
-#define NPCX_DEVALT7_NO_KSI2_SL          2
-#define NPCX_DEVALT7_NO_KSI3_SL          3
-#define NPCX_DEVALT7_NO_KSI4_SL          4
-#define NPCX_DEVALT7_NO_KSI5_SL          5
-#define NPCX_DEVALT7_NO_KSI6_SL          6
-#define NPCX_DEVALT7_NO_KSI7_SL          7
-#define NPCX_DEVALT8_NO_KSO00_SL         0
-#define NPCX_DEVALT8_NO_KSO01_SL         1
-#define NPCX_DEVALT8_NO_KSO02_SL         2
-#define NPCX_DEVALT8_NO_KSO03_SL         3
-#define NPCX_DEVALT8_NO_KSO04_SL         4
-#define NPCX_DEVALT8_NO_KSO05_SL         5
-#define NPCX_DEVALT8_NO_KSO06_SL         6
-#define NPCX_DEVALT8_NO_KSO07_SL         7
-#define NPCX_DEVALT9_NO_KSO08_SL         0
-#define NPCX_DEVALT9_NO_KSO09_SL         1
-#define NPCX_DEVALT9_NO_KSO10_SL         2
-#define NPCX_DEVALT9_NO_KSO11_SL         3
-#define NPCX_DEVALT9_NO_KSO12_SL         4
-#define NPCX_DEVALT9_NO_KSO13_SL         5
-#define NPCX_DEVALT9_NO_KSO14_SL         6
-#define NPCX_DEVALT9_NO_KSO15_SL         7
-#define NPCX_DEVALTA_NO_KSO16_SL         0
-#define NPCX_DEVALTA_NO_KSO17_SL         1
+#define NPCX_DEVALT7_NO_KSI0_SL 0
+#define NPCX_DEVALT7_NO_KSI1_SL 1
+#define NPCX_DEVALT7_NO_KSI2_SL 2
+#define NPCX_DEVALT7_NO_KSI3_SL 3
+#define NPCX_DEVALT7_NO_KSI4_SL 4
+#define NPCX_DEVALT7_NO_KSI5_SL 5
+#define NPCX_DEVALT7_NO_KSI6_SL 6
+#define NPCX_DEVALT7_NO_KSI7_SL 7
+#define NPCX_DEVALT8_NO_KSO00_SL 0
+#define NPCX_DEVALT8_NO_KSO01_SL 1
+#define NPCX_DEVALT8_NO_KSO02_SL 2
+#define NPCX_DEVALT8_NO_KSO03_SL 3
+#define NPCX_DEVALT8_NO_KSO04_SL 4
+#define NPCX_DEVALT8_NO_KSO05_SL 5
+#define NPCX_DEVALT8_NO_KSO06_SL 6
+#define NPCX_DEVALT8_NO_KSO07_SL 7
+#define NPCX_DEVALT9_NO_KSO08_SL 0
+#define NPCX_DEVALT9_NO_KSO09_SL 1
+#define NPCX_DEVALT9_NO_KSO10_SL 2
+#define NPCX_DEVALT9_NO_KSO11_SL 3
+#define NPCX_DEVALT9_NO_KSO12_SL 4
+#define NPCX_DEVALT9_NO_KSO13_SL 5
+#define NPCX_DEVALT9_NO_KSO14_SL 6
+#define NPCX_DEVALT9_NO_KSO15_SL 7
+#define NPCX_DEVALTA_NO_KSO16_SL 0
+#define NPCX_DEVALTA_NO_KSO17_SL 1
 
 /* pin-mux for Others */
-#define NPCX_DEVALTA_32K_OUT_SL          2
-#define NPCX_DEVALTA_NO_VCC1_RST         4
-#define NPCX_DEVALTA_NO_PECI_EN          6
-#define NPCX_DEVALTC_SHI_SL              1
+#define NPCX_DEVALTA_32K_OUT_SL 2
+#define NPCX_DEVALTA_NO_VCC1_RST 4
+#define NPCX_DEVALTA_NO_PECI_EN 6
+#define NPCX_DEVALTC_SHI_SL 1
 
 /* Others bit definitions */
-#define NPCX_LFCGCALCNT_LPREG_CTL_EN     1
+#define NPCX_LFCGCALCNT_LPREG_CTL_EN 1
 
 /******************************************************************************/
 /* Development and Debug Support (DBG) Registers */
-#define NPCX_DBGCTRL                      REG8(NPCX_SCFG_BASE_ADDR + 0x074)
-#define NPCX_DBGFRZEN1                    REG8(NPCX_SCFG_BASE_ADDR + 0x076)
-#define NPCX_DBGFRZEN2                    REG8(NPCX_SCFG_BASE_ADDR + 0x077)
-#define NPCX_DBGFRZEN3                    REG8(NPCX_SCFG_BASE_ADDR + 0x078)
+#define NPCX_DBGCTRL REG8(NPCX_SCFG_BASE_ADDR + 0x074)
+#define NPCX_DBGFRZEN1 REG8(NPCX_SCFG_BASE_ADDR + 0x076)
+#define NPCX_DBGFRZEN2 REG8(NPCX_SCFG_BASE_ADDR + 0x077)
+#define NPCX_DBGFRZEN3 REG8(NPCX_SCFG_BASE_ADDR + 0x078)
 /* DBG register fields */
-#define NPCX_DBGFRZEN3_GLBL_FRZ_DIS      7
+#define NPCX_DBGFRZEN3_GLBL_FRZ_DIS 7
 
 /******************************************************************************/
 /* SMBus Registers */
-#define NPCX_SMBSDA(n)                    REG8(NPCX_SMB_BASE_ADDR(n) + 0x000)
-#define NPCX_SMBST(n)                     REG8(NPCX_SMB_BASE_ADDR(n) + 0x002)
-#define NPCX_SMBCST(n)                    REG8(NPCX_SMB_BASE_ADDR(n) + 0x004)
-#define NPCX_SMBCTL1(n)                   REG8(NPCX_SMB_BASE_ADDR(n) + 0x006)
-#define NPCX_SMBADDR1(n)                  REG8(NPCX_SMB_BASE_ADDR(n) + 0x008)
-#define NPCX_SMBTMR_ST(n)                 REG8(NPCX_SMB_BASE_ADDR(n) + 0x009)
-#define NPCX_SMBCTL2(n)                   REG8(NPCX_SMB_BASE_ADDR(n) + 0x00A)
-#define NPCX_SMBTMR_EN(n)                 REG8(NPCX_SMB_BASE_ADDR(n) + 0x00B)
-#define NPCX_SMBADDR2(n)                  REG8(NPCX_SMB_BASE_ADDR(n) + 0x00C)
-#define NPCX_SMBCTL3(n)                   REG8(NPCX_SMB_BASE_ADDR(n) + 0x00E)
+#define NPCX_SMBSDA(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x000)
+#define NPCX_SMBST(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x002)
+#define NPCX_SMBCST(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x004)
+#define NPCX_SMBCTL1(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x006)
+#define NPCX_SMBADDR1(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x008)
+#define NPCX_SMBTMR_ST(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x009)
+#define NPCX_SMBCTL2(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x00A)
+#define NPCX_SMBTMR_EN(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x00B)
+#define NPCX_SMBADDR2(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x00C)
+#define NPCX_SMBCTL3(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x00E)
 /* SMB Registers in bank 0 */
-#define NPCX_SMBADDR3(n)                  REG8(NPCX_SMB_BASE_ADDR(n) + 0x010)
-#define NPCX_SMBADDR7(n)                  REG8(NPCX_SMB_BASE_ADDR(n) + 0x011)
-#define NPCX_SMBADDR4(n)                  REG8(NPCX_SMB_BASE_ADDR(n) + 0x012)
-#define NPCX_SMBADDR8(n)                  REG8(NPCX_SMB_BASE_ADDR(n) + 0x013)
-#define NPCX_SMBADDR5(n)                  REG8(NPCX_SMB_BASE_ADDR(n) + 0x014)
-#define NPCX_SMBADDR6(n)                  REG8(NPCX_SMB_BASE_ADDR(n) + 0x016)
-#define NPCX_SMBCST2(n)                   REG8(NPCX_SMB_BASE_ADDR(n) + 0x018)
-#define NPCX_SMBCST3(n)                   REG8(NPCX_SMB_BASE_ADDR(n) + 0x019)
-#define NPCX_SMBCTL4(n)                   REG8(NPCX_SMB_BASE_ADDR(n) + 0x01A)
-#define NPCX_SMBSCLLT(n)                  REG8(NPCX_SMB_BASE_ADDR(n) + 0x01C)
-#define NPCX_SMBFIF_CTL(n)                REG8(NPCX_SMB_BASE_ADDR(n) + 0x01D)
-#define NPCX_SMBSCLHT(n)                  REG8(NPCX_SMB_BASE_ADDR(n) + 0x01E)
+#define NPCX_SMBADDR3(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x010)
+#define NPCX_SMBADDR7(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x011)
+#define NPCX_SMBADDR4(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x012)
+#define NPCX_SMBADDR8(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x013)
+#define NPCX_SMBADDR5(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x014)
+#define NPCX_SMBADDR6(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x016)
+#define NPCX_SMBCST2(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x018)
+#define NPCX_SMBCST3(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x019)
+#define NPCX_SMBCTL4(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x01A)
+#define NPCX_SMBSCLLT(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x01C)
+#define NPCX_SMBFIF_CTL(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x01D)
+#define NPCX_SMBSCLHT(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x01E)
 /* SMB Registers in bank 1 */
-#define NPCX_SMBFIF_CTS(n)                REG8(NPCX_SMB_BASE_ADDR(n) + 0x010)
-#define NPCX_SMBTXF_CTL(n)                REG8(NPCX_SMB_BASE_ADDR(n) + 0x012)
-#define NPCX_SMB_T_OUT(n)                 REG8(NPCX_SMB_BASE_ADDR(n) + 0x014)
+#define NPCX_SMBFIF_CTS(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x010)
+#define NPCX_SMBTXF_CTL(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x012)
+#define NPCX_SMB_T_OUT(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x014)
 /*
  * These two registers are the same as in bank 0
  * #define NPCX_SMBCST2(n)                REG8(NPCX_SMB_BASE_ADDR(n) + 0x018)
  * #define NPCX_SMBCST3(n)                REG8(NPCX_SMB_BASE_ADDR(n) + 0x019)
  */
-#define NPCX_SMBTXF_STS(n)                REG8(NPCX_SMB_BASE_ADDR(n) + 0x01A)
-#define NPCX_SMBRXF_STS(n)                REG8(NPCX_SMB_BASE_ADDR(n) + 0x01C)
-#define NPCX_SMBRXF_CTL(n)                REG8(NPCX_SMB_BASE_ADDR(n) + 0x01E)
+#define NPCX_SMBTXF_STS(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x01A)
+#define NPCX_SMBRXF_STS(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x01C)
+#define NPCX_SMBRXF_CTL(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x01E)
 
 /* SMBus register fields */
-#define NPCX_SMBST_XMIT                  0
-#define NPCX_SMBST_MASTER                1
-#define NPCX_SMBST_NMATCH                2
-#define NPCX_SMBST_STASTR                3
-#define NPCX_SMBST_NEGACK                4
-#define NPCX_SMBST_BER                   5
-#define NPCX_SMBST_SDAST                 6
-#define NPCX_SMBST_SLVSTP                7
-#define NPCX_SMBCST_BUSY                 0
-#define NPCX_SMBCST_BB                   1
-#define NPCX_SMBCST_MATCH                2
-#define NPCX_SMBCST_GCMATCH              3
-#define NPCX_SMBCST_TSDA                 4
-#define NPCX_SMBCST_TGSCL                5
-#define NPCX_SMBCST_MATCHAF              6
-#define NPCX_SMBCST_ARPMATCH             7
-#define NPCX_SMBCST2_MATCHA1F            0
-#define NPCX_SMBCST2_MATCHA2F            1
-#define NPCX_SMBCST2_MATCHA3F            2
-#define NPCX_SMBCST2_MATCHA4F            3
-#define NPCX_SMBCST2_MATCHA5F            4
-#define NPCX_SMBCST2_MATCHA6F            5
-#define NPCX_SMBCST2_MATCHA7F            6
-#define NPCX_SMBCST2_INTSTS              7
-#define NPCX_SMBCST3_MATCHA8F            0
-#define NPCX_SMBCST3_MATCHA9F            1
-#define NPCX_SMBCST3_MATCHA10F           2
-#define NPCX_SMBCTL1_START               0
-#define NPCX_SMBCTL1_STOP                1
-#define NPCX_SMBCTL1_INTEN               2
-#define NPCX_SMBCTL1_ACK                 4
-#define NPCX_SMBCTL1_GCMEN               5
-#define NPCX_SMBCTL1_NMINTE              6
-#define NPCX_SMBCTL1_STASTRE             7
-#define NPCX_SMBCTL2_ENABLE              0
-#define NPCX_SMBCTL2_SCLFRQ7_FIELD       FIELD(1, 7)
-#define NPCX_SMBCTL3_ARPMEN              2
-#define NPCX_SMBCTL3_SCLFRQ2_FIELD       FIELD(0, 2)
-#define NPCX_SMBCTL3_IDL_START           3
-#define NPCX_SMBCTL3_400K                4
-#define NPCX_SMBCTL3_BNK_SEL             5
-#define NPCX_SMBCTL3_SDA_LVL             6
-#define NPCX_SMBCTL3_SCL_LVL             7
-#define NPCX_SMBCTL4_HLDT_FIELD          FIELD(0, 6)
-#define NPCX_SMBCTL4_LVL_WE              7
-#define NPCX_SMBADDR1_SAEN               7
-#define NPCX_SMBADDR2_SAEN               7
-#define NPCX_SMBADDR3_SAEN               7
-#define NPCX_SMBADDR4_SAEN               7
-#define NPCX_SMBADDR5_SAEN               7
-#define NPCX_SMBADDR6_SAEN               7
-#define NPCX_SMBADDR7_SAEN               7
-#define NPCX_SMBADDR8_SAEN               7
-#define NPCX_SMBFIF_CTS_RXF_TXE          1
-#define NPCX_SMBFIF_CTS_CLR_FIFO         6
-
-#define NPCX_SMBFIF_CTL_FIFO_EN          4
-
-#define NPCX_SMBRXF_STS_RX_THST          6
+#define NPCX_SMBST_XMIT 0
+#define NPCX_SMBST_MASTER 1
+#define NPCX_SMBST_NMATCH 2
+#define NPCX_SMBST_STASTR 3
+#define NPCX_SMBST_NEGACK 4
+#define NPCX_SMBST_BER 5
+#define NPCX_SMBST_SDAST 6
+#define NPCX_SMBST_SLVSTP 7
+#define NPCX_SMBCST_BUSY 0
+#define NPCX_SMBCST_BB 1
+#define NPCX_SMBCST_MATCH 2
+#define NPCX_SMBCST_GCMATCH 3
+#define NPCX_SMBCST_TSDA 4
+#define NPCX_SMBCST_TGSCL 5
+#define NPCX_SMBCST_MATCHAF 6
+#define NPCX_SMBCST_ARPMATCH 7
+#define NPCX_SMBCST2_MATCHA1F 0
+#define NPCX_SMBCST2_MATCHA2F 1
+#define NPCX_SMBCST2_MATCHA3F 2
+#define NPCX_SMBCST2_MATCHA4F 3
+#define NPCX_SMBCST2_MATCHA5F 4
+#define NPCX_SMBCST2_MATCHA6F 5
+#define NPCX_SMBCST2_MATCHA7F 6
+#define NPCX_SMBCST2_INTSTS 7
+#define NPCX_SMBCST3_MATCHA8F 0
+#define NPCX_SMBCST3_MATCHA9F 1
+#define NPCX_SMBCST3_MATCHA10F 2
+#define NPCX_SMBCTL1_START 0
+#define NPCX_SMBCTL1_STOP 1
+#define NPCX_SMBCTL1_INTEN 2
+#define NPCX_SMBCTL1_ACK 4
+#define NPCX_SMBCTL1_GCMEN 5
+#define NPCX_SMBCTL1_NMINTE 6
+#define NPCX_SMBCTL1_STASTRE 7
+#define NPCX_SMBCTL2_ENABLE 0
+#define NPCX_SMBCTL2_SCLFRQ7_FIELD FIELD(1, 7)
+#define NPCX_SMBCTL3_ARPMEN 2
+#define NPCX_SMBCTL3_SCLFRQ2_FIELD FIELD(0, 2)
+#define NPCX_SMBCTL3_IDL_START 3
+#define NPCX_SMBCTL3_400K 4
+#define NPCX_SMBCTL3_BNK_SEL 5
+#define NPCX_SMBCTL3_SDA_LVL 6
+#define NPCX_SMBCTL3_SCL_LVL 7
+#define NPCX_SMBCTL4_HLDT_FIELD FIELD(0, 6)
+#define NPCX_SMBCTL4_LVL_WE 7
+#define NPCX_SMBADDR1_SAEN 7
+#define NPCX_SMBADDR2_SAEN 7
+#define NPCX_SMBADDR3_SAEN 7
+#define NPCX_SMBADDR4_SAEN 7
+#define NPCX_SMBADDR5_SAEN 7
+#define NPCX_SMBADDR6_SAEN 7
+#define NPCX_SMBADDR7_SAEN 7
+#define NPCX_SMBADDR8_SAEN 7
+#define NPCX_SMBFIF_CTS_RXF_TXE 1
+#define NPCX_SMBFIF_CTS_CLR_FIFO 6
+
+#define NPCX_SMBFIF_CTL_FIFO_EN 4
+
+#define NPCX_SMBRXF_STS_RX_THST 6
 
 /* RX FIFO threshold */
-#define NPCX_SMBRXF_CTL_RX_THR           FIELD(0, 6)
+#define NPCX_SMBRXF_CTL_RX_THR FIELD(0, 6)
 /*
- * In master receiving mode, last byte in FIFO should send ACK or NACK
+ * In controller receiving mode, last byte in FIFO should send ACK or NACK
  */
-#define NPCX_SMBRXF_CTL_LAST             7
+#define NPCX_SMBRXF_CTL_LAST 7
 
 /******************************************************************************/
 /* Power Management Controller (PMC) Registers */
-#define NPCX_PMCSR                     REG8(NPCX_PMC_BASE_ADDR + 0x000)
-#define NPCX_ENIDL_CTL                 REG8(NPCX_PMC_BASE_ADDR + 0x003)
-#define NPCX_DISIDL_CTL                REG8(NPCX_PMC_BASE_ADDR + 0x004)
-#define NPCX_DISIDL_CTL1               REG8(NPCX_PMC_BASE_ADDR + 0x005)
-#define NPCX_PWDWN_CTL_ADDR(offset)    (((offset) < 6) ? \
-			(NPCX_PMC_BASE_ADDR + 0x008 + (offset)) : \
-			(NPCX_PMC_BASE_ADDR + 0x024))
-#define NPCX_PWDWN_CTL(offset)         REG8(NPCX_PWDWN_CTL_ADDR(offset))
+#define NPCX_PMCSR REG8(NPCX_PMC_BASE_ADDR + 0x000)
+#define NPCX_ENIDL_CTL REG8(NPCX_PMC_BASE_ADDR + 0x003)
+#define NPCX_DISIDL_CTL REG8(NPCX_PMC_BASE_ADDR + 0x004)
+#define NPCX_DISIDL_CTL1 REG8(NPCX_PMC_BASE_ADDR + 0x005)
+#define NPCX_PWDWN_CTL_ADDR(offset)                                 \
+	(((offset) < 6) ? (NPCX_PMC_BASE_ADDR + 0x008 + (offset)) : \
+			  (NPCX_PMC_BASE_ADDR + 0x024 + (offset)-6))
+#define NPCX_PWDWN_CTL(offset) REG8(NPCX_PWDWN_CTL_ADDR(offset))
 
 /* PMC register fields */
-#define NPCX_PMCSR_DI_INSTW              0
-#define NPCX_PMCSR_DHF                   1
-#define NPCX_PMCSR_IDLE                  2
-#define NPCX_PMCSR_NWBI                  3
-#define NPCX_PMCSR_OHFC                  6
-#define NPCX_PMCSR_OLFC                  7
-#define NPCX_DISIDL_CTL_RAM_DID          5
-#define NPCX_ENIDL_CTL_ADC_LFSL          7
-#define NPCX_ENIDL_CTL_LP_WK_CTL         6
-#define NPCX_ENIDL_CTL_PECI_ENI          2
-#define NPCX_ENIDL_CTL_ADC_ACC_DIS       1
-#define NPCX_PWDWN_CTL1_KBS_PD           0
-#define NPCX_PWDWN_CTL1_SDP_PD           1
-#define NPCX_PWDWN_CTL1_FIU_PD           2
-#define NPCX_PWDWN_CTL1_PS2_PD           3
-#define NPCX_PWDWN_CTL1_UART_PD          4
-#define NPCX_PWDWN_CTL1_MFT1_PD          5
-#define NPCX_PWDWN_CTL1_MFT2_PD          6
-#define NPCX_PWDWN_CTL1_MFT3_PD          7
-#define NPCX_PWDWN_CTL2_PWM0_PD          0
-#define NPCX_PWDWN_CTL2_PWM1_PD          1
-#define NPCX_PWDWN_CTL2_PWM2_PD          2
-#define NPCX_PWDWN_CTL2_PWM3_PD          3
-#define NPCX_PWDWN_CTL2_PWM4_PD          4
-#define NPCX_PWDWN_CTL2_PWM5_PD          5
-#define NPCX_PWDWN_CTL2_PWM6_PD          6
-#define NPCX_PWDWN_CTL2_PWM7_PD          7
-#define NPCX_PWDWN_CTL3_SMB0_PD          0
-#define NPCX_PWDWN_CTL3_SMB1_PD          1
-#define NPCX_PWDWN_CTL3_SMB2_PD          2
-#define NPCX_PWDWN_CTL3_SMB3_PD          3
-#define NPCX_PWDWN_CTL3_GMDA_PD          7
-#define NPCX_PWDWN_CTL4_ITIM1_PD         0
-#define NPCX_PWDWN_CTL4_ITIM2_PD         1
-#define NPCX_PWDWN_CTL4_ITIM3_PD         2
-#define NPCX_PWDWN_CTL4_ADC_PD           4
-#define NPCX_PWDWN_CTL4_PECI_PD          5
-#define NPCX_PWDWN_CTL4_PWM6_PD          6
-#define NPCX_PWDWN_CTL4_SPIP_PD          7
-#define NPCX_PWDWN_CTL5_SHI_PD           1
-#define NPCX_PWDWN_CTL5_MRFSH_DIS        2
-#define NPCX_PWDWN_CTL5_C2HACC_PD        3
-#define NPCX_PWDWN_CTL5_SHM_REG_PD       4
-#define NPCX_PWDWN_CTL5_SHM_PD           5
-#define NPCX_PWDWN_CTL5_DP80_PD          6
-#define NPCX_PWDWN_CTL5_MSWC_PD          7
-#define NPCX_PWDWN_CTL6_ITIM4_PD         0
-#define NPCX_PWDWN_CTL6_ITIM5_PD         1
-#define NPCX_PWDWN_CTL6_ITIM6_PD         2
-#define NPCX_PWDWN_CTL6_ESPI_PD          7
+#define NPCX_PMCSR_DI_INSTW 0
+#define NPCX_PMCSR_DHF 1
+#define NPCX_PMCSR_IDLE 2
+#define NPCX_PMCSR_NWBI 3
+#define NPCX_PMCSR_OHFC 6
+#define NPCX_PMCSR_OLFC 7
+#define NPCX_DISIDL_CTL_RAM_DID 5
+#define NPCX_ENIDL_CTL_ADC_LFSL 7
+#define NPCX_ENIDL_CTL_LP_WK_CTL 6
+#define NPCX_ENIDL_CTL_PECI_ENI 2
+#define NPCX_ENIDL_CTL_ADC_ACC_DIS 1
+#define NPCX_PWDWN_CTL1_KBS_PD 0
+#define NPCX_PWDWN_CTL1_SDP_PD 1
+#define NPCX_PWDWN_CTL1_FIU_PD 2
+#define NPCX_PWDWN_CTL1_PS2_PD 3
+#define NPCX_PWDWN_CTL1_UART_PD 4
+#define NPCX_PWDWN_CTL1_MFT1_PD 5
+#define NPCX_PWDWN_CTL1_MFT2_PD 6
+#define NPCX_PWDWN_CTL1_MFT3_PD 7
+#define NPCX_PWDWN_CTL2_PWM0_PD 0
+#define NPCX_PWDWN_CTL2_PWM1_PD 1
+#define NPCX_PWDWN_CTL2_PWM2_PD 2
+#define NPCX_PWDWN_CTL2_PWM3_PD 3
+#define NPCX_PWDWN_CTL2_PWM4_PD 4
+#define NPCX_PWDWN_CTL2_PWM5_PD 5
+#define NPCX_PWDWN_CTL2_PWM6_PD 6
+#define NPCX_PWDWN_CTL2_PWM7_PD 7
+#define NPCX_PWDWN_CTL3_SMB0_PD 0
+#define NPCX_PWDWN_CTL3_SMB1_PD 1
+#define NPCX_PWDWN_CTL3_SMB2_PD 2
+#define NPCX_PWDWN_CTL3_SMB3_PD 3
+#define NPCX_PWDWN_CTL3_GMDA_PD 7
+#define NPCX_PWDWN_CTL4_ITIM1_PD 0
+#define NPCX_PWDWN_CTL4_ITIM2_PD 1
+#define NPCX_PWDWN_CTL4_ITIM3_PD 2
+#define NPCX_PWDWN_CTL4_ADC_PD 4
+#define NPCX_PWDWN_CTL4_PECI_PD 5
+#define NPCX_PWDWN_CTL4_PWM6_PD 6
+#define NPCX_PWDWN_CTL4_SPIP_PD 7
+#define NPCX_PWDWN_CTL5_SHI_PD 1
+#define NPCX_PWDWN_CTL5_MRFSH_DIS 2
+#define NPCX_PWDWN_CTL5_C2HACC_PD 3
+#define NPCX_PWDWN_CTL5_SHM_REG_PD 4
+#define NPCX_PWDWN_CTL5_SHM_PD 5
+#define NPCX_PWDWN_CTL5_DP80_PD 6
+#define NPCX_PWDWN_CTL5_MSWC_PD 7
+#define NPCX_PWDWN_CTL6_ITIM4_PD 0
+#define NPCX_PWDWN_CTL6_ITIM5_PD 1
+#define NPCX_PWDWN_CTL6_ITIM6_PD 2
+#define NPCX_PWDWN_CTL6_ESPI_PD 7
 
 /* TODO: set PD masks based upon actual peripheral usage */
-#define CGC_KBS_MASK     BIT(NPCX_PWDWN_CTL1_KBS_PD)
-#define CGC_UART_MASK    BIT(NPCX_PWDWN_CTL1_UART_PD)
-#define CGC_FAN_MASK     (BIT(NPCX_PWDWN_CTL1_MFT1_PD) | \
-			 BIT(NPCX_PWDWN_CTL1_MFT2_PD))
-#define CGC_FIU_MASK     BIT(NPCX_PWDWN_CTL1_FIU_PD)
-#define CGC_PS2_MASK     BIT(NPCX_PWDWN_CTL1_PS2_PD)
-#define CGC_ADC_MASK     BIT(NPCX_PWDWN_CTL4_ADC_PD)
-#define CGC_PECI_MASK    BIT(NPCX_PWDWN_CTL4_PECI_PD)
-#define CGC_SPI_MASK     BIT(NPCX_PWDWN_CTL4_SPIP_PD)
-#define CGC_TIMER_MASK   (BIT(NPCX_PWDWN_CTL4_ITIM1_PD) | \
-			 BIT(NPCX_PWDWN_CTL4_ITIM2_PD) | \
-			 BIT(NPCX_PWDWN_CTL4_ITIM3_PD))
-#define CGC_LPC_MASK     (BIT(NPCX_PWDWN_CTL5_C2HACC_PD) | \
-			 BIT(NPCX_PWDWN_CTL5_SHM_REG_PD) | \
-			 BIT(NPCX_PWDWN_CTL5_SHM_PD) | \
-			 BIT(NPCX_PWDWN_CTL5_DP80_PD) | \
-			 BIT(NPCX_PWDWN_CTL5_MSWC_PD))
-#define CGC_ESPI_MASK    BIT(NPCX_PWDWN_CTL6_ESPI_PD)
+#define CGC_KBS_MASK BIT(NPCX_PWDWN_CTL1_KBS_PD)
+#define CGC_UART_MASK BIT(NPCX_PWDWN_CTL1_UART_PD)
+#define CGC_FAN_MASK \
+	(BIT(NPCX_PWDWN_CTL1_MFT1_PD) | BIT(NPCX_PWDWN_CTL1_MFT2_PD))
+#define CGC_FIU_MASK BIT(NPCX_PWDWN_CTL1_FIU_PD)
+#define CGC_PS2_MASK BIT(NPCX_PWDWN_CTL1_PS2_PD)
+#define CGC_ADC_MASK BIT(NPCX_PWDWN_CTL4_ADC_PD)
+#define CGC_PECI_MASK BIT(NPCX_PWDWN_CTL4_PECI_PD)
+#define CGC_SPI_MASK BIT(NPCX_PWDWN_CTL4_SPIP_PD)
+#define CGC_TIMER_MASK                                                   \
+	(BIT(NPCX_PWDWN_CTL4_ITIM1_PD) | BIT(NPCX_PWDWN_CTL4_ITIM2_PD) | \
+	 BIT(NPCX_PWDWN_CTL4_ITIM3_PD))
+#define CGC_LPC_MASK                                                        \
+	(BIT(NPCX_PWDWN_CTL5_C2HACC_PD) | BIT(NPCX_PWDWN_CTL5_SHM_REG_PD) | \
+	 BIT(NPCX_PWDWN_CTL5_SHM_PD) | BIT(NPCX_PWDWN_CTL5_DP80_PD) |       \
+	 BIT(NPCX_PWDWN_CTL5_MSWC_PD))
+#define CGC_ESPI_MASK BIT(NPCX_PWDWN_CTL6_ESPI_PD)
 
 /******************************************************************************/
 /* Flash Interface Unit (FIU) Registers */
-#define NPCX_FIU_CFG                      REG8(NPCX_FIU_BASE_ADDR + 0x000)
-#define NPCX_BURST_CFG                    REG8(NPCX_FIU_BASE_ADDR + 0x001)
-#define NPCX_RESP_CFG                     REG8(NPCX_FIU_BASE_ADDR + 0x002)
-#define NPCX_SPI_FL_CFG                   REG8(NPCX_FIU_BASE_ADDR + 0x014)
-#define NPCX_UMA_CODE                     REG8(NPCX_FIU_BASE_ADDR + 0x016)
-#define NPCX_UMA_AB0                      REG8(NPCX_FIU_BASE_ADDR + 0x017)
-#define NPCX_UMA_AB1                      REG8(NPCX_FIU_BASE_ADDR + 0x018)
-#define NPCX_UMA_AB2                      REG8(NPCX_FIU_BASE_ADDR + 0x019)
-#define NPCX_UMA_DB0                      REG8(NPCX_FIU_BASE_ADDR + 0x01A)
-#define NPCX_UMA_DB1                      REG8(NPCX_FIU_BASE_ADDR + 0x01B)
-#define NPCX_UMA_DB2                      REG8(NPCX_FIU_BASE_ADDR + 0x01C)
-#define NPCX_UMA_DB3                      REG8(NPCX_FIU_BASE_ADDR + 0x01D)
-#define NPCX_UMA_CTS                      REG8(NPCX_FIU_BASE_ADDR + 0x01E)
-#define NPCX_UMA_ECTS                     REG8(NPCX_FIU_BASE_ADDR + 0x01F)
-#define NPCX_UMA_DB0_3                   REG32(NPCX_FIU_BASE_ADDR + 0x020)
-#define NPCX_FIU_RD_CMD                   REG8(NPCX_FIU_BASE_ADDR + 0x030)
-#define NPCX_FIU_DMM_CYC                  REG8(NPCX_FIU_BASE_ADDR + 0x032)
-#define NPCX_FIU_EXT_CFG                  REG8(NPCX_FIU_BASE_ADDR + 0x033)
-#define NPCX_FIU_UMA_AB0_3               REG32(NPCX_FIU_BASE_ADDR + 0x034)
+#define NPCX_FIU_CFG REG8(NPCX_FIU_BASE_ADDR + 0x000)
+#define NPCX_BURST_CFG REG8(NPCX_FIU_BASE_ADDR + 0x001)
+#define NPCX_RESP_CFG REG8(NPCX_FIU_BASE_ADDR + 0x002)
+#define NPCX_SPI_FL_CFG REG8(NPCX_FIU_BASE_ADDR + 0x014)
+#define NPCX_UMA_CODE REG8(NPCX_FIU_BASE_ADDR + 0x016)
+#define NPCX_UMA_AB0 REG8(NPCX_FIU_BASE_ADDR + 0x017)
+#define NPCX_UMA_AB1 REG8(NPCX_FIU_BASE_ADDR + 0x018)
+#define NPCX_UMA_AB2 REG8(NPCX_FIU_BASE_ADDR + 0x019)
+#define NPCX_UMA_DB0 REG8(NPCX_FIU_BASE_ADDR + 0x01A)
+#define NPCX_UMA_DB1 REG8(NPCX_FIU_BASE_ADDR + 0x01B)
+#define NPCX_UMA_DB2 REG8(NPCX_FIU_BASE_ADDR + 0x01C)
+#define NPCX_UMA_DB3 REG8(NPCX_FIU_BASE_ADDR + 0x01D)
+#define NPCX_UMA_CTS REG8(NPCX_FIU_BASE_ADDR + 0x01E)
+#define NPCX_UMA_ECTS REG8(NPCX_FIU_BASE_ADDR + 0x01F)
+#define NPCX_UMA_DB0_3 REG32(NPCX_FIU_BASE_ADDR + 0x020)
+#define NPCX_FIU_RD_CMD REG8(NPCX_FIU_BASE_ADDR + 0x030)
+#define NPCX_FIU_DMM_CYC REG8(NPCX_FIU_BASE_ADDR + 0x032)
+#define NPCX_FIU_EXT_CFG REG8(NPCX_FIU_BASE_ADDR + 0x033)
+#define NPCX_FIU_UMA_AB0_3 REG32(NPCX_FIU_BASE_ADDR + 0x034)
 
 /* FIU register fields */
-#define NPCX_RESP_CFG_IAD_EN             0
-#define NPCX_RESP_CFG_DEV_SIZE_EX        2
-#define NPCX_UMA_CTS_A_SIZE              3
-#define NPCX_UMA_CTS_C_SIZE              4
-#define NPCX_UMA_CTS_RD_WR               5
-#define NPCX_UMA_CTS_DEV_NUM             6
-#define NPCX_UMA_CTS_EXEC_DONE           7
-#define NPCX_UMA_ECTS_SW_CS0             0
-#define NPCX_UMA_ECTS_SW_CS1             1
-#define NPCX_UMA_ECTS_SEC_CS             2
-#define NPCX_UMA_ECTS_UMA_LOCK           3
+#define NPCX_RESP_CFG_IAD_EN 0
+#define NPCX_RESP_CFG_DEV_SIZE_EX 2
+#define NPCX_UMA_CTS_A_SIZE 3
+#define NPCX_UMA_CTS_C_SIZE 4
+#define NPCX_UMA_CTS_RD_WR 5
+#define NPCX_UMA_CTS_DEV_NUM 6
+#define NPCX_UMA_CTS_EXEC_DONE 7
+#define NPCX_UMA_ECTS_SW_CS0 0
+#define NPCX_UMA_ECTS_SW_CS1 1
+#define NPCX_UMA_ECTS_SEC_CS 2
+#define NPCX_UMA_ECTS_UMA_LOCK 3
 
 /******************************************************************************/
 /* Shared Memory (SHM) Registers */
-#define NPCX_SMC_STS                REG8(NPCX_SHM_BASE_ADDR + 0x000)
-#define NPCX_SMC_CTL                REG8(NPCX_SHM_BASE_ADDR + 0x001)
-#define NPCX_SHM_CTL                REG8(NPCX_SHM_BASE_ADDR + 0x002)
-#define NPCX_IMA_WIN_SIZE           REG8(NPCX_SHM_BASE_ADDR + 0x005)
-#define NPCX_WIN_SIZE               REG8(NPCX_SHM_BASE_ADDR + 0x007)
-#define NPCX_SHAW_SEM(win)          REG8(NPCX_SHM_BASE_ADDR + 0x008 + (win))
-#define NPCX_IMA_SEM                REG8(NPCX_SHM_BASE_ADDR + 0x00B)
-#define NPCX_SHCFG                  REG8(NPCX_SHM_BASE_ADDR + 0x00E)
-#define NPCX_WIN_WR_PROT(win)       REG8(NPCX_SHM_BASE_ADDR + 0x010 + (win*2L))
-#define NPCX_WIN_RD_PROT(win)       REG8(NPCX_SHM_BASE_ADDR + 0x011 + (win*2L))
-#define NPCX_IMA_WR_PROT            REG8(NPCX_SHM_BASE_ADDR + 0x016)
-#define NPCX_IMA_RD_PROT            REG8(NPCX_SHM_BASE_ADDR + 0x017)
-#define NPCX_WIN_BASE(win)         REG32(NPCX_SHM_BASE_ADDR + 0x020 + (win*4L))
-
-#define NPCX_PWIN_BASEI(win)       REG16(NPCX_SHM_BASE_ADDR + 0x020 + (win*4L))
-#define NPCX_PWIN_SIZEI(win)       REG16(NPCX_SHM_BASE_ADDR + 0x022 + (win*4L))
-
-#define NPCX_IMA_BASE              REG32(NPCX_SHM_BASE_ADDR + 0x02C)
-#define NPCX_RST_CFG                REG8(NPCX_SHM_BASE_ADDR + 0x03A)
-#define NPCX_DP80BUF               REG16(NPCX_SHM_BASE_ADDR + 0x040)
-#define NPCX_DP80STS                REG8(NPCX_SHM_BASE_ADDR + 0x042)
-#define NPCX_DP80CTL                REG8(NPCX_SHM_BASE_ADDR + 0x044)
-#define NPCX_HOFS_STS               REG8(NPCX_SHM_BASE_ADDR + 0x048)
-#define NPCX_HOFS_CTL               REG8(NPCX_SHM_BASE_ADDR + 0x049)
-#define NPCX_COFS2                 REG16(NPCX_SHM_BASE_ADDR + 0x04A)
-#define NPCX_COFS1                 REG16(NPCX_SHM_BASE_ADDR + 0x04C)
-#define NPCX_IHOFS2                REG16(NPCX_SHM_BASE_ADDR + 0x050)
-#define NPCX_IHOFS1                REG16(NPCX_SHM_BASE_ADDR + 0x052)
-#define NPCX_SHM_VER                REG8(NPCX_SHM_BASE_ADDR + 0x07F)
+#define NPCX_SMC_STS REG8(NPCX_SHM_BASE_ADDR + 0x000)
+#define NPCX_SMC_CTL REG8(NPCX_SHM_BASE_ADDR + 0x001)
+#define NPCX_SHM_CTL REG8(NPCX_SHM_BASE_ADDR + 0x002)
+#define NPCX_IMA_WIN_SIZE REG8(NPCX_SHM_BASE_ADDR + 0x005)
+#define NPCX_WIN_SIZE REG8(NPCX_SHM_BASE_ADDR + 0x007)
+#define NPCX_SHAW_SEM(win) REG8(NPCX_SHM_BASE_ADDR + 0x008 + (win))
+#define NPCX_IMA_SEM REG8(NPCX_SHM_BASE_ADDR + 0x00B)
+#define NPCX_SHCFG REG8(NPCX_SHM_BASE_ADDR + 0x00E)
+#define NPCX_WIN_WR_PROT(win) REG8(NPCX_SHM_BASE_ADDR + 0x010 + (win * 2L))
+#define NPCX_WIN_RD_PROT(win) REG8(NPCX_SHM_BASE_ADDR + 0x011 + (win * 2L))
+#define NPCX_IMA_WR_PROT REG8(NPCX_SHM_BASE_ADDR + 0x016)
+#define NPCX_IMA_RD_PROT REG8(NPCX_SHM_BASE_ADDR + 0x017)
+#define NPCX_WIN_BASE(win) REG32(NPCX_SHM_BASE_ADDR + 0x020 + (win * 4L))
+
+#define NPCX_PWIN_BASEI(win) REG16(NPCX_SHM_BASE_ADDR + 0x020 + (win * 4L))
+#define NPCX_PWIN_SIZEI(win) REG16(NPCX_SHM_BASE_ADDR + 0x022 + (win * 4L))
+
+#define NPCX_IMA_BASE REG32(NPCX_SHM_BASE_ADDR + 0x02C)
+#define NPCX_RST_CFG REG8(NPCX_SHM_BASE_ADDR + 0x03A)
+#define NPCX_DP80BUF REG16(NPCX_SHM_BASE_ADDR + 0x040)
+#define NPCX_DP80STS REG8(NPCX_SHM_BASE_ADDR + 0x042)
+#define NPCX_DP80CTL REG8(NPCX_SHM_BASE_ADDR + 0x044)
+#define NPCX_HOFS_STS REG8(NPCX_SHM_BASE_ADDR + 0x048)
+#define NPCX_HOFS_CTL REG8(NPCX_SHM_BASE_ADDR + 0x049)
+#define NPCX_COFS2 REG16(NPCX_SHM_BASE_ADDR + 0x04A)
+#define NPCX_COFS1 REG16(NPCX_SHM_BASE_ADDR + 0x04C)
+#define NPCX_IHOFS2 REG16(NPCX_SHM_BASE_ADDR + 0x050)
+#define NPCX_IHOFS1 REG16(NPCX_SHM_BASE_ADDR + 0x052)
+#define NPCX_SHM_VER REG8(NPCX_SHM_BASE_ADDR + 0x07F)
 
 /* SHM register fields */
-#define NPCX_SMC_STS_HRERR               0
-#define NPCX_SMC_STS_HWERR               1
-#define NPCX_SMC_STS_HSEM1W              4
-#define NPCX_SMC_STS_HSEM2W              5
-#define NPCX_SMC_STS_SHM_ACC             6
-#define NPCX_SMC_CTL_HERR_IE             2
-#define NPCX_SMC_CTL_HSEM1_IE            3
-#define NPCX_SMC_CTL_HSEM2_IE            4
-#define NPCX_SMC_CTL_ACC_IE              5
-#define NPCX_SMC_CTL_PREF_EN             6
-#define NPCX_SMC_CTL_HOSTWAIT            7
-#define NPCX_FLASH_SIZE_STALL_HOST       6
-#define NPCX_FLASH_SIZE_RD_BURST         7
-#define NPCX_WIN_PROT_RW1L_RP            0
-#define NPCX_WIN_PROT_RW1L_WP            1
-#define NPCX_WIN_PROT_RW1H_RP            2
-#define NPCX_WIN_PROT_RW1H_WP            3
-#define NPCX_WIN_PROT_RW2L_RP            4
-#define NPCX_WIN_PROT_RW2L_WP            5
-#define NPCX_WIN_PROT_RW2H_RP            6
-#define NPCX_WIN_PROT_RW2H_WP            7
-#define NPCX_PWIN_SIZEI_RPROT            13
-#define NPCX_PWIN_SIZEI_WPROT            14
-#define NPCX_CSEM2                       6
-#define NPCX_CSEM3                       7
-#define NPCX_DP80STS_FWR                 5
-#define NPCX_DP80STS_FNE                 6
-#define NPCX_DP80STS_FOR                 7
-#define NPCX_DP80CTL_DP80EN              0
-#define NPCX_DP80CTL_SYNCEN              1
-#define NPCX_DP80CTL_RFIFO               4
-#define NPCX_DP80CTL_CIEN                5
+#define NPCX_SMC_STS_HRERR 0
+#define NPCX_SMC_STS_HWERR 1
+#define NPCX_SMC_STS_HSEM1W 4
+#define NPCX_SMC_STS_HSEM2W 5
+#define NPCX_SMC_STS_SHM_ACC 6
+#define NPCX_SMC_CTL_HERR_IE 2
+#define NPCX_SMC_CTL_HSEM1_IE 3
+#define NPCX_SMC_CTL_HSEM2_IE 4
+#define NPCX_SMC_CTL_ACC_IE 5
+#define NPCX_SMC_CTL_PREF_EN 6
+#define NPCX_SMC_CTL_HOSTWAIT 7
+#define NPCX_FLASH_SIZE_STALL_HOST 6
+#define NPCX_FLASH_SIZE_RD_BURST 7
+#define NPCX_WIN_PROT_RW1L_RP 0
+#define NPCX_WIN_PROT_RW1L_WP 1
+#define NPCX_WIN_PROT_RW1H_RP 2
+#define NPCX_WIN_PROT_RW1H_WP 3
+#define NPCX_WIN_PROT_RW2L_RP 4
+#define NPCX_WIN_PROT_RW2L_WP 5
+#define NPCX_WIN_PROT_RW2H_RP 6
+#define NPCX_WIN_PROT_RW2H_WP 7
+#define NPCX_PWIN_SIZEI_RPROT 13
+#define NPCX_PWIN_SIZEI_WPROT 14
+#define NPCX_CSEM2 6
+#define NPCX_CSEM3 7
+#define NPCX_DP80BUF_OFFS_FIELD FIELD(8, 3)
+#define NPCX_DP80STS_FWR 5
+#define NPCX_DP80STS_FNE 6
+#define NPCX_DP80STS_FOR 7
+#define NPCX_DP80CTL_DP80EN 0
+#define NPCX_DP80CTL_SYNCEN 1
+#define NPCX_DP80CTL_RFIFO 4
+#define NPCX_DP80CTL_CIEN 5
 
 /******************************************************************************/
 /* KBC Registers */
-#define NPCX_HICTRL                       REG8(NPCX_KBC_BASE_ADDR + 0x000)
-#define NPCX_HIIRQC                       REG8(NPCX_KBC_BASE_ADDR + 0x002)
-#define NPCX_HIKMST                       REG8(NPCX_KBC_BASE_ADDR + 0x004)
-#define NPCX_HIKDO                        REG8(NPCX_KBC_BASE_ADDR + 0x006)
-#define NPCX_HIMDO                        REG8(NPCX_KBC_BASE_ADDR + 0x008)
-#define NPCX_KBCVER                       REG8(NPCX_KBC_BASE_ADDR + 0x009)
-#define NPCX_HIKMDI                       REG8(NPCX_KBC_BASE_ADDR + 0x00A)
-#define NPCX_SHIKMDI                      REG8(NPCX_KBC_BASE_ADDR + 0x00B)
+#define NPCX_HICTRL REG8(NPCX_KBC_BASE_ADDR + 0x000)
+#define NPCX_HIIRQC REG8(NPCX_KBC_BASE_ADDR + 0x002)
+#define NPCX_HIKMST REG8(NPCX_KBC_BASE_ADDR + 0x004)
+#define NPCX_HIKDO REG8(NPCX_KBC_BASE_ADDR + 0x006)
+#define NPCX_HIMDO REG8(NPCX_KBC_BASE_ADDR + 0x008)
+#define NPCX_KBCVER REG8(NPCX_KBC_BASE_ADDR + 0x009)
+#define NPCX_HIKMDI REG8(NPCX_KBC_BASE_ADDR + 0x00A)
+#define NPCX_SHIKMDI REG8(NPCX_KBC_BASE_ADDR + 0x00B)
 
 /* KBC register field */
-#define NPCX_HICTRL_OBFKIE               0 /* Automatic Serial IRQ1 for KBC */
-#define NPCX_HICTRL_OBFMIE               1 /* Automatic Serial IRQ12 for Mouse*/
-#define NPCX_HICTRL_OBECIE               2 /* KBC OBE interrupt enable */
-#define NPCX_HICTRL_IBFCIE               3 /* KBC IBF interrupt enable */
-#define NPCX_HICTRL_PMIHIE               4 /* Automatic Serial IRQ11 for PMC1 */
-#define NPCX_HICTRL_PMIOCIE              5 /* PMC1 OBE interrupt enable */
-#define NPCX_HICTRL_PMICIE               6 /* PMC1 IBF interrupt enable */
-#define NPCX_HICTRL_FW_OBF               7 /* Firmware control over OBF */
-
-#define NPCX_HIKMST_OBF                  0 /* KB output buffer is full */
+#define NPCX_HICTRL_OBFKIE 0 /* Automatic Serial IRQ1 for KBC */
+#define NPCX_HICTRL_OBFMIE 1 /* Automatic Serial IRQ12 for Mouse*/
+#define NPCX_HICTRL_OBECIE 2 /* KBC OBE interrupt enable */
+#define NPCX_HICTRL_IBFCIE 3 /* KBC IBF interrupt enable */
+#define NPCX_HICTRL_PMIHIE 4 /* Automatic Serial IRQ11 for PMC1 */
+#define NPCX_HICTRL_PMIOCIE 5 /* PMC1 OBE interrupt enable */
+#define NPCX_HICTRL_PMICIE 6 /* PMC1 IBF interrupt enable */
+#define NPCX_HICTRL_FW_OBF 7 /* Firmware control over OBF */
+
+#define NPCX_HIKMST_OBF 0 /* KB output buffer is full */
 /******************************************************************************/
 /* PM Channel Registers */
-#define NPCX_HIPMST(n)                    REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x000)
-#define NPCX_HIPMDO(n)                    REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x002)
-#define NPCX_HIPMDI(n)                    REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x004)
-#define NPCX_SHIPMDI(n)                   REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x005)
-#define NPCX_HIPMDOC(n)                   REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x006)
-#define NPCX_HIPMDOM(n)                   REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x008)
-#define NPCX_HIPMDIC(n)                   REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x00A)
-#define NPCX_HIPMCTL(n)                   REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x00C)
-#define NPCX_HIPMCTL2(n)                  REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x00D)
-#define NPCX_HIPMIC(n)                    REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x00E)
-#define NPCX_HIPMIE(n)                    REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x010)
+#define NPCX_HIPMST(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x000)
+#define NPCX_HIPMDO(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x002)
+#define NPCX_HIPMDI(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x004)
+#define NPCX_SHIPMDI(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x005)
+#define NPCX_HIPMDOC(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x006)
+#define NPCX_HIPMDOM(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x008)
+#define NPCX_HIPMDIC(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x00A)
+#define NPCX_HIPMCTL(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x00C)
+#define NPCX_HIPMCTL2(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x00D)
+#define NPCX_HIPMIC(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x00E)
+#define NPCX_HIPMIE(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x010)
 
 /* PM Channel register field */
 
 /* NPCX_HIPMIE */
-#define NPCX_HIPMIE_SCIE                 1
-#define NPCX_HIPMIE_SMIE                 2
+#define NPCX_HIPMIE_SCIE 1
+#define NPCX_HIPMIE_SMIE 2
 
 /* NPCX_HIPMCTL */
-#define NPCX_HIPMCTL_IBFIE               0
-#define NPCX_HIPMCTL_SCIPOL              6
+#define NPCX_HIPMCTL_IBFIE 0
+#define NPCX_HIPMCTL_SCIPOL 6
 
 /* NPCX_HIPMST */
-#define NPCX_HIPMST_F0                   2 /* EC_LPC_CMDR_BUSY */
-#define NPCX_HIPMST_ST0                  4 /* EC_LPC_CMDR_ACPI_BRST */
-#define NPCX_HIPMST_ST1                  5 /* EC_LPC_CMDR_SCI */
-#define NPCX_HIPMST_ST2                  6 /* EC_LPC_CMDR_SMI */
+#define NPCX_HIPMST_F0 2 /* EC_LPC_CMDR_BUSY */
+#define NPCX_HIPMST_ST0 4 /* EC_LPC_CMDR_ACPI_BRST */
+#define NPCX_HIPMST_ST1 5 /* EC_LPC_CMDR_SCI */
+#define NPCX_HIPMST_ST2 6 /* EC_LPC_CMDR_SMI */
 
 /* NPCX_HIPMIC */
-#define NPCX_HIPMIC_SMIB                 1
-#define NPCX_HIPMIC_SCIB                 2
-#define NPCX_HIPMIC_SMIPOL               6
+#define NPCX_HIPMIC_SMIB 1
+#define NPCX_HIPMIC_SCIB 2
+#define NPCX_HIPMIC_SMIPOL 6
 
 /*
  * PM Channel enumeration
  */
-enum PM_CHANNEL_T {
-	PM_CHAN_1,
-	PM_CHAN_2,
-	PM_CHAN_3,
-	PM_CHAN_4
-};
+enum PM_CHANNEL_T { PM_CHAN_1, PM_CHAN_2, PM_CHAN_3, PM_CHAN_4 };
 
 /******************************************************************************/
 /* SuperI/O Internal Bus (SIB) Registers */
-#define NPCX_IHIOA                       REG16(NPCX_SIB_BASE_ADDR + 0x000)
-#define NPCX_IHD                          REG8(NPCX_SIB_BASE_ADDR + 0x002)
-#define NPCX_LKSIOHA                     REG16(NPCX_SIB_BASE_ADDR + 0x004)
-#define NPCX_SIOLV                       REG16(NPCX_SIB_BASE_ADDR + 0x006)
-#define NPCX_CRSMAE                      REG16(NPCX_SIB_BASE_ADDR + 0x008)
-#define NPCX_SIBCTRL                      REG8(NPCX_SIB_BASE_ADDR + 0x00A)
-#define NPCX_C2H_VER                      REG8(NPCX_SIB_BASE_ADDR + 0x00E)
+#define NPCX_IHIOA REG16(NPCX_SIB_BASE_ADDR + 0x000)
+#define NPCX_IHD REG8(NPCX_SIB_BASE_ADDR + 0x002)
+#define NPCX_LKSIOHA REG16(NPCX_SIB_BASE_ADDR + 0x004)
+#define NPCX_SIOLV REG16(NPCX_SIB_BASE_ADDR + 0x006)
+#define NPCX_CRSMAE REG16(NPCX_SIB_BASE_ADDR + 0x008)
+#define NPCX_SIBCTRL REG8(NPCX_SIB_BASE_ADDR + 0x00A)
+#define NPCX_C2H_VER REG8(NPCX_SIB_BASE_ADDR + 0x00E)
 /* SIB register fields  */
-#define NPCX_SIBCTRL_CSAE                0
-#define NPCX_SIBCTRL_CSRD                1
-#define NPCX_SIBCTRL_CSWR                2
-#define NPCX_LKSIOHA_LKCFG               0
-#define NPCX_LKSIOHA_LKHIKBD            11
-#define NPCX_CRSMAE_CFGAE                0
-#define NPCX_CRSMAE_HIKBDAE             11
+#define NPCX_SIBCTRL_CSAE 0
+#define NPCX_SIBCTRL_CSRD 1
+#define NPCX_SIBCTRL_CSWR 2
+#define NPCX_LKSIOHA_LKCFG 0
+#define NPCX_LKSIOHA_LKHIKBD 11
+#define NPCX_CRSMAE_CFGAE 0
+#define NPCX_CRSMAE_HIKBDAE 11
 
 /******************************************************************************/
 /* Battery-Backed RAM (BBRAM) Registers */
-#define NPCX_BKUP_STS                REG8(NPCX_BBRAM_BASE_ADDR + 0x100)
-#define NPCX_BBRAM(offset)           REG8(NPCX_BBRAM_BASE_ADDR + offset)
+#define NPCX_BKUP_STS REG8(NPCX_BBRAM_BASE_ADDR + 0x100)
+#define NPCX_BBRAM(offset) REG8(NPCX_BBRAM_BASE_ADDR + offset)
 
 /* BBRAM register fields */
-#define NPCX_BKUP_STS_IBBR               7
+#define NPCX_BKUP_STS_IBBR 7
 
 /******************************************************************************/
 /* Timer Watch Dog (TWD) Registers */
-#define NPCX_TWCFG                        REG8(NPCX_TWD_BASE_ADDR + 0x000)
-#define NPCX_TWCP                         REG8(NPCX_TWD_BASE_ADDR + 0x002)
-#define NPCX_TWDT0                       REG16(NPCX_TWD_BASE_ADDR + 0x004)
-#define NPCX_T0CSR                        REG8(NPCX_TWD_BASE_ADDR + 0x006)
-#define NPCX_WDCNT                        REG8(NPCX_TWD_BASE_ADDR + 0x008)
-#define NPCX_WDSDM                        REG8(NPCX_TWD_BASE_ADDR + 0x00A)
-#define NPCX_TWMT0                       REG16(NPCX_TWD_BASE_ADDR + 0x00C)
-#define NPCX_TWMWD                        REG8(NPCX_TWD_BASE_ADDR + 0x00E)
-#define NPCX_WDCP                         REG8(NPCX_TWD_BASE_ADDR + 0x010)
+#define NPCX_TWCFG REG8(NPCX_TWD_BASE_ADDR + 0x000)
+#define NPCX_TWCP REG8(NPCX_TWD_BASE_ADDR + 0x002)
+#define NPCX_TWDT0 REG16(NPCX_TWD_BASE_ADDR + 0x004)
+#define NPCX_T0CSR REG8(NPCX_TWD_BASE_ADDR + 0x006)
+#define NPCX_WDCNT REG8(NPCX_TWD_BASE_ADDR + 0x008)
+#define NPCX_WDSDM REG8(NPCX_TWD_BASE_ADDR + 0x00A)
+#define NPCX_TWMT0 REG16(NPCX_TWD_BASE_ADDR + 0x00C)
+#define NPCX_TWMWD REG8(NPCX_TWD_BASE_ADDR + 0x00E)
+#define NPCX_WDCP REG8(NPCX_TWD_BASE_ADDR + 0x010)
 
 /* TWD register fields */
-#define NPCX_TWCFG_LTWCFG                0
-#define NPCX_TWCFG_LTWCP                 1
-#define NPCX_TWCFG_LTWDT0                2
-#define NPCX_TWCFG_LWDCNT                3
-#define NPCX_TWCFG_WDCT0I                4
-#define NPCX_TWCFG_WDSDME                5
-#define NPCX_TWCFG_WDRST_MODE            6
-#define NPCX_TWCFG_WDC2POR               7
-#define NPCX_T0CSR_RST                   0
-#define NPCX_T0CSR_TC                    1
-#define NPCX_T0CSR_WDLTD                 3
-#define NPCX_T0CSR_WDRST_STS             4
-#define NPCX_T0CSR_WD_RUN                5
-#define NPCX_T0CSR_TESDIS                7
+#define NPCX_TWCFG_LTWCFG 0
+#define NPCX_TWCFG_LTWCP 1
+#define NPCX_TWCFG_LTWDT0 2
+#define NPCX_TWCFG_LWDCNT 3
+#define NPCX_TWCFG_WDCT0I 4
+#define NPCX_TWCFG_WDSDME 5
+#define NPCX_TWCFG_WDRST_MODE 6
+#define NPCX_TWCFG_WDC2POR 7
+#define NPCX_T0CSR_RST 0
+#define NPCX_T0CSR_TC 1
+#define NPCX_T0CSR_WDLTD 3
+#define NPCX_T0CSR_WDRST_STS 4
+#define NPCX_T0CSR_WD_RUN 5
+#define NPCX_T0CSR_TESDIS 7
 
 /******************************************************************************/
 /* SPI Register */
-#define NPCX_SPI_DATA                    REG16(NPCX_SPI_BASE_ADDR + 0x00)
-#define NPCX_SPI_CTL1                    REG16(NPCX_SPI_BASE_ADDR + 0x02)
-#define NPCX_SPI_STAT                     REG8(NPCX_SPI_BASE_ADDR + 0x04)
+#define NPCX_SPI_DATA REG16(NPCX_SPI_BASE_ADDR + 0x00)
+#define NPCX_SPI_CTL1 REG16(NPCX_SPI_BASE_ADDR + 0x02)
+#define NPCX_SPI_STAT REG8(NPCX_SPI_BASE_ADDR + 0x04)
 
 /* SPI register fields */
-#define NPCX_SPI_CTL1_SPIEN              0
-#define NPCX_SPI_CTL1_SNM                1
-#define NPCX_SPI_CTL1_MOD                2
-#define NPCX_SPI_CTL1_EIR                5
-#define NPCX_SPI_CTL1_EIW                6
-#define NPCX_SPI_CTL1_SCM                7
-#define NPCX_SPI_CTL1_SCIDL              8
-#define NPCX_SPI_CTL1_SCDV               9
-#define NPCX_SPI_STAT_BSY                0
-#define NPCX_SPI_STAT_RBF                1
+#define NPCX_SPI_CTL1_SPIEN 0
+#define NPCX_SPI_CTL1_SNM 1
+#define NPCX_SPI_CTL1_MOD 2
+#define NPCX_SPI_CTL1_EIR 5
+#define NPCX_SPI_CTL1_EIW 6
+#define NPCX_SPI_CTL1_SCM 7
+#define NPCX_SPI_CTL1_SCIDL 8
+#define NPCX_SPI_CTL1_SCDV 9
+#define NPCX_SPI_STAT_BSY 0
+#define NPCX_SPI_STAT_RBF 1
 
 /******************************************************************************/
 /* PECI Registers */
 
-#define NPCX_PECI_CTL_STS                REG8(NPCX_PECI_BASE_ADDR + 0x000)
-#define NPCX_PECI_RD_LENGTH              REG8(NPCX_PECI_BASE_ADDR + 0x001)
-#define NPCX_PECI_ADDR                   REG8(NPCX_PECI_BASE_ADDR + 0x002)
-#define NPCX_PECI_CMD                    REG8(NPCX_PECI_BASE_ADDR + 0x003)
-#define NPCX_PECI_CTL2                   REG8(NPCX_PECI_BASE_ADDR + 0x004)
-#define NPCX_PECI_INDEX                  REG8(NPCX_PECI_BASE_ADDR + 0x005)
-#define NPCX_PECI_IDATA                  REG8(NPCX_PECI_BASE_ADDR + 0x006)
-#define NPCX_PECI_WR_LENGTH              REG8(NPCX_PECI_BASE_ADDR + 0x007)
-#define NPCX_PECI_CFG                    REG8(NPCX_PECI_BASE_ADDR + 0x009)
-#define NPCX_PECI_RATE                   REG8(NPCX_PECI_BASE_ADDR + 0x00F)
-#define NPCX_PECI_DATA_IN(i)             REG8(NPCX_PECI_BASE_ADDR + 0x010 + (i))
-#define NPCX_PECI_DATA_OUT(i)            REG8(NPCX_PECI_BASE_ADDR + 0x010 + (i))
+#define NPCX_PECI_CTL_STS REG8(NPCX_PECI_BASE_ADDR + 0x000)
+#define NPCX_PECI_RD_LENGTH REG8(NPCX_PECI_BASE_ADDR + 0x001)
+#define NPCX_PECI_ADDR REG8(NPCX_PECI_BASE_ADDR + 0x002)
+#define NPCX_PECI_CMD REG8(NPCX_PECI_BASE_ADDR + 0x003)
+#define NPCX_PECI_CTL2 REG8(NPCX_PECI_BASE_ADDR + 0x004)
+#define NPCX_PECI_INDEX REG8(NPCX_PECI_BASE_ADDR + 0x005)
+#define NPCX_PECI_IDATA REG8(NPCX_PECI_BASE_ADDR + 0x006)
+#define NPCX_PECI_WR_LENGTH REG8(NPCX_PECI_BASE_ADDR + 0x007)
+#define NPCX_PECI_CFG REG8(NPCX_PECI_BASE_ADDR + 0x009)
+#define NPCX_PECI_RATE REG8(NPCX_PECI_BASE_ADDR + 0x00F)
+#define NPCX_PECI_DATA_IN(i) REG8(NPCX_PECI_BASE_ADDR + 0x010 + (i))
+#define NPCX_PECI_DATA_OUT(i) REG8(NPCX_PECI_BASE_ADDR + 0x010 + (i))
 
 /* PECI register fields */
-#define NPCX_PECI_CTL_STS_START_BUSY     0
-#define NPCX_PECI_CTL_STS_DONE           1
-#define NPCX_PECI_CTL_STS_AVL_ERR        2
-#define NPCX_PECI_CTL_STS_CRC_ERR        3
-#define NPCX_PECI_CTL_STS_ABRT_ERR       4
-#define NPCX_PECI_CTL_STS_AWFCS_EN       5
-#define NPCX_PECI_CTL_STS_DONE_EN        6
-#define NPCX_ESTRPST_PECIST              0
-#define SFT_STRP_CFG_CK50                5
+#define NPCX_PECI_CTL_STS_START_BUSY 0
+#define NPCX_PECI_CTL_STS_DONE 1
+#define NPCX_PECI_CTL_STS_AVL_ERR 2
+#define NPCX_PECI_CTL_STS_CRC_ERR 3
+#define NPCX_PECI_CTL_STS_ABRT_ERR 4
+#define NPCX_PECI_CTL_STS_AWFCS_EN 5
+#define NPCX_PECI_CTL_STS_DONE_EN 6
+#define NPCX_ESTRPST_PECIST 0
+#define SFT_STRP_CFG_CK50 5
 
 /******************************************************************************/
 /* PWM Registers */
-#define NPCX_PRSC(n)                     REG16(NPCX_PWM_BASE_ADDR(n) + 0x000)
-#define NPCX_CTR(n)                      REG16(NPCX_PWM_BASE_ADDR(n) + 0x002)
-#define NPCX_PWMCTL(n)                    REG8(NPCX_PWM_BASE_ADDR(n) + 0x004)
-#define NPCX_DCR(n)                      REG16(NPCX_PWM_BASE_ADDR(n) + 0x006)
-#define NPCX_PWMCTLEX(n)                  REG8(NPCX_PWM_BASE_ADDR(n) + 0x00C)
+#define NPCX_PRSC(n) REG16(NPCX_PWM_BASE_ADDR(n) + 0x000)
+#define NPCX_CTR(n) REG16(NPCX_PWM_BASE_ADDR(n) + 0x002)
+#define NPCX_PWMCTL(n) REG8(NPCX_PWM_BASE_ADDR(n) + 0x004)
+#define NPCX_DCR(n) REG16(NPCX_PWM_BASE_ADDR(n) + 0x006)
+#define NPCX_PWMCTLEX(n) REG8(NPCX_PWM_BASE_ADDR(n) + 0x00C)
 
 /* PWM register fields */
-#define NPCX_PWMCTL_INVP                 0
-#define NPCX_PWMCTL_CKSEL                1
-#define NPCX_PWMCTL_HB_DC_CTL_FIELD      FIELD(2, 2)
-#define NPCX_PWMCTL_PWR                  7
-#define NPCX_PWMCTLEX_FCK_SEL_FIELD      FIELD(4, 2)
-#define NPCX_PWMCTLEX_OD_OUT             7
+#define NPCX_PWMCTL_INVP 0
+#define NPCX_PWMCTL_CKSEL 1
+#define NPCX_PWMCTL_HB_DC_CTL_FIELD FIELD(2, 2)
+#define NPCX_PWMCTL_PWR 7
+#define NPCX_PWMCTLEX_FCK_SEL_FIELD FIELD(4, 2)
+#define NPCX_PWMCTLEX_OD_OUT 7
 /******************************************************************************/
 /* MFT Registers */
-#define NPCX_TCNT1(n)                    REG16(NPCX_MFT_BASE_ADDR(n) + 0x000)
-#define NPCX_TCRA(n)                     REG16(NPCX_MFT_BASE_ADDR(n) + 0x002)
-#define NPCX_TCRB(n)                     REG16(NPCX_MFT_BASE_ADDR(n) + 0x004)
-#define NPCX_TCNT2(n)                    REG16(NPCX_MFT_BASE_ADDR(n) + 0x006)
-#define NPCX_TPRSC(n)                     REG8(NPCX_MFT_BASE_ADDR(n) + 0x008)
-#define NPCX_TCKC(n)                      REG8(NPCX_MFT_BASE_ADDR(n) + 0x00A)
-#define NPCX_TMCTRL(n)                    REG8(NPCX_MFT_BASE_ADDR(n) + 0x00C)
-#define NPCX_TECTRL(n)                    REG8(NPCX_MFT_BASE_ADDR(n) + 0x00E)
-#define NPCX_TECLR(n)                     REG8(NPCX_MFT_BASE_ADDR(n) + 0x010)
-#define NPCX_TIEN(n)                      REG8(NPCX_MFT_BASE_ADDR(n) + 0x012)
-#define NPCX_TWUEN(n)                     REG8(NPCX_MFT_BASE_ADDR(n) + 0x01A)
-#define NPCX_TCFG(n)                      REG8(NPCX_MFT_BASE_ADDR(n) + 0x01C)
+#define NPCX_TCNT1(n) REG16(NPCX_MFT_BASE_ADDR(n) + 0x000)
+#define NPCX_TCRA(n) REG16(NPCX_MFT_BASE_ADDR(n) + 0x002)
+#define NPCX_TCRB(n) REG16(NPCX_MFT_BASE_ADDR(n) + 0x004)
+#define NPCX_TCNT2(n) REG16(NPCX_MFT_BASE_ADDR(n) + 0x006)
+#define NPCX_TPRSC(n) REG8(NPCX_MFT_BASE_ADDR(n) + 0x008)
+#define NPCX_TCKC(n) REG8(NPCX_MFT_BASE_ADDR(n) + 0x00A)
+#define NPCX_TMCTRL(n) REG8(NPCX_MFT_BASE_ADDR(n) + 0x00C)
+#define NPCX_TECTRL(n) REG8(NPCX_MFT_BASE_ADDR(n) + 0x00E)
+#define NPCX_TECLR(n) REG8(NPCX_MFT_BASE_ADDR(n) + 0x010)
+#define NPCX_TIEN(n) REG8(NPCX_MFT_BASE_ADDR(n) + 0x012)
+#define NPCX_TWUEN(n) REG8(NPCX_MFT_BASE_ADDR(n) + 0x01A)
+#define NPCX_TCFG(n) REG8(NPCX_MFT_BASE_ADDR(n) + 0x01C)
 
 /* MFT register fields */
-#define NPCX_TMCTRL_MDSEL_FIELD          FIELD(0, 3)
-#define NPCX_TCKC_LOW_PWR                7
-#define NPCX_TCKC_PLS_ACC_CLK            6
-#define NPCX_TCKC_C1CSEL_FIELD           FIELD(0, 3)
-#define NPCX_TCKC_C2CSEL_FIELD           FIELD(3, 3)
-#define NPCX_TMCTRL_TAEN                 5
-#define NPCX_TMCTRL_TBEN                 6
-#define NPCX_TMCTRL_TAEDG                3
-#define NPCX_TMCTRL_TBEDG                4
-#define NPCX_TCFG_TADBEN                 6
-#define NPCX_TCFG_TBDBEN                 7
-#define NPCX_TECTRL_TAPND                0
-#define NPCX_TECTRL_TBPND                1
-#define NPCX_TECTRL_TCPND                2
-#define NPCX_TECTRL_TDPND                3
-#define NPCX_TECLR_TACLR                 0
-#define NPCX_TECLR_TBCLR                 1
-#define NPCX_TECLR_TCCLR                 2
-#define NPCX_TECLR_TDCLR                 3
-#define NPCX_TIEN_TAIEN                  0
-#define NPCX_TIEN_TBIEN                  1
-#define NPCX_TIEN_TCIEN                  2
-#define NPCX_TIEN_TDIEN                  3
-#define NPCX_TWUEN_TAWEN                 0
-#define NPCX_TWUEN_TBWEN                 1
-#define NPCX_TWUEN_TCWEN                 2
-#define NPCX_TWUEN_TDWEN                 3
+#define NPCX_TMCTRL_MDSEL_FIELD FIELD(0, 3)
+#define NPCX_TCKC_LOW_PWR 7
+#define NPCX_TCKC_PLS_ACC_CLK 6
+#define NPCX_TCKC_C1CSEL_FIELD FIELD(0, 3)
+#define NPCX_TCKC_C2CSEL_FIELD FIELD(3, 3)
+#define NPCX_TMCTRL_TAEN 5
+#define NPCX_TMCTRL_TBEN 6
+#define NPCX_TMCTRL_TAEDG 3
+#define NPCX_TMCTRL_TBEDG 4
+#define NPCX_TCFG_TADBEN 6
+#define NPCX_TCFG_TBDBEN 7
+#define NPCX_TECTRL_TAPND 0
+#define NPCX_TECTRL_TBPND 1
+#define NPCX_TECTRL_TCPND 2
+#define NPCX_TECTRL_TDPND 3
+#define NPCX_TECLR_TACLR 0
+#define NPCX_TECLR_TBCLR 1
+#define NPCX_TECLR_TCCLR 2
+#define NPCX_TECLR_TDCLR 3
+#define NPCX_TIEN_TAIEN 0
+#define NPCX_TIEN_TBIEN 1
+#define NPCX_TIEN_TCIEN 2
+#define NPCX_TIEN_TDIEN 3
+#define NPCX_TWUEN_TAWEN 0
+#define NPCX_TWUEN_TBWEN 1
+#define NPCX_TWUEN_TCWEN 2
+#define NPCX_TWUEN_TDWEN 3
 /******************************************************************************/
 /* ITIM16/32 Define */
-#define ITIM_INT(module)               CONCAT2(NPCX_IRQ_, module)
+#define ITIM_INT(module) CONCAT2(NPCX_IRQ_, module)
 
 /* ITIM16/32 register */
-#define NPCX_ITPRE(n)                    REG8(NPCX_ITIM_BASE_ADDR(n) + 0x001)
-#define NPCX_ITCTS(n)                    REG8(NPCX_ITIM_BASE_ADDR(n) + 0x004)
+#define NPCX_ITPRE(n) REG8(NPCX_ITIM_BASE_ADDR(n) + 0x001)
+#define NPCX_ITCTS(n) REG8(NPCX_ITIM_BASE_ADDR(n) + 0x004)
 
 /* ITIM16 register fields */
-#define NPCX_ITCTS_TO_STS                0
-#define NPCX_ITCTS_TO_IE                 2
-#define NPCX_ITCTS_TO_WUE                3
-#define NPCX_ITCTS_CKSEL                 4
-#define NPCX_ITCTS_ITEN                  7
+#define NPCX_ITCTS_TO_STS 0
+#define NPCX_ITCTS_TO_IE 2
+#define NPCX_ITCTS_TO_WUE 3
+#define NPCX_ITCTS_CKSEL 4
+#define NPCX_ITCTS_ITEN 7
 
 /******************************************************************************/
 /* Serial Host Interface (SHI) Registers */
-#define NPCX_SHICFG1                      REG8(NPCX_SHI_BASE_ADDR + 0x001)
-#define NPCX_SHICFG2                      REG8(NPCX_SHI_BASE_ADDR + 0x002)
-#define NPCX_I2CADDR1                     REG8(NPCX_SHI_BASE_ADDR + 0x003)
-#define NPCX_I2CADDR2                     REG8(NPCX_SHI_BASE_ADDR + 0x004)
-#define NPCX_EVENABLE                     REG8(NPCX_SHI_BASE_ADDR + 0x005)
-#define NPCX_EVSTAT                       REG8(NPCX_SHI_BASE_ADDR + 0x006)
-#define NPCX_SHI_CAPABILITY               REG8(NPCX_SHI_BASE_ADDR + 0x007)
-#define NPCX_STATUS                       REG8(NPCX_SHI_BASE_ADDR + 0x008)
-#define NPCX_IBUFSTAT                     REG8(NPCX_SHI_BASE_ADDR + 0x00A)
-#define NPCX_OBUFSTAT                     REG8(NPCX_SHI_BASE_ADDR + 0x00B)
+#define NPCX_SHICFG1 REG8(NPCX_SHI_BASE_ADDR + 0x001)
+#define NPCX_SHICFG2 REG8(NPCX_SHI_BASE_ADDR + 0x002)
+#define NPCX_I2CADDR1 REG8(NPCX_SHI_BASE_ADDR + 0x003)
+#define NPCX_I2CADDR2 REG8(NPCX_SHI_BASE_ADDR + 0x004)
+#define NPCX_EVENABLE REG8(NPCX_SHI_BASE_ADDR + 0x005)
+#define NPCX_EVSTAT REG8(NPCX_SHI_BASE_ADDR + 0x006)
+#define NPCX_SHI_CAPABILITY REG8(NPCX_SHI_BASE_ADDR + 0x007)
+#define NPCX_STATUS REG8(NPCX_SHI_BASE_ADDR + 0x008)
+#define NPCX_IBUFSTAT REG8(NPCX_SHI_BASE_ADDR + 0x00A)
+#define NPCX_OBUFSTAT REG8(NPCX_SHI_BASE_ADDR + 0x00B)
 
 /* SHI register fields */
-#define NPCX_SHICFG1_EN                  0
-#define NPCX_SHICFG1_MODE                1
-#define NPCX_SHICFG1_WEN                 2
-#define NPCX_SHICFG1_AUTIBF              3
-#define NPCX_SHICFG1_AUTOBE              4
-#define NPCX_SHICFG1_DAS                 5
-#define NPCX_SHICFG1_CPOL                6
-#define NPCX_SHICFG1_IWRAP               7
-#define NPCX_SHICFG2_SIMUL               0
-#define NPCX_SHICFG2_BUSY                1
-#define NPCX_SHICFG2_ONESHOT             2
-#define NPCX_SHICFG2_SLWU                3
-#define NPCX_SHICFG2_REEN                4
-#define NPCX_SHICFG2_RESTART             5
-#define NPCX_SHICFG2_REEVEN              6
-#define NPCX_EVENABLE_OBEEN              0
-#define NPCX_EVENABLE_OBHEEN             1
-#define NPCX_EVENABLE_IBFEN              2
-#define NPCX_EVENABLE_IBHFEN             3
-#define NPCX_EVENABLE_EOREN              4
-#define NPCX_EVENABLE_EOWEN              5
-#define NPCX_EVENABLE_STSREN             6
-#define NPCX_EVENABLE_IBOREN             7
-#define NPCX_EVSTAT_OBE                  0
-#define NPCX_EVSTAT_OBHE                 1
-#define NPCX_EVSTAT_IBF                  2
-#define NPCX_EVSTAT_IBHF                 3
-#define NPCX_EVSTAT_EOR                  4
-#define NPCX_EVSTAT_EOW                  5
-#define NPCX_EVSTAT_STSR                 6
-#define NPCX_EVSTAT_IBOR                 7
-#define NPCX_STATUS_OBES                 6
-#define NPCX_STATUS_IBFS                 7
+#define NPCX_SHICFG1_EN 0
+#define NPCX_SHICFG1_MODE 1
+#define NPCX_SHICFG1_WEN 2
+#define NPCX_SHICFG1_AUTIBF 3
+#define NPCX_SHICFG1_AUTOBE 4
+#define NPCX_SHICFG1_DAS 5
+#define NPCX_SHICFG1_CPOL 6
+#define NPCX_SHICFG1_IWRAP 7
+#define NPCX_SHICFG2_SIMUL 0
+#define NPCX_SHICFG2_BUSY 1
+#define NPCX_SHICFG2_ONESHOT 2
+#define NPCX_SHICFG2_SLWU 3
+#define NPCX_SHICFG2_REEN 4
+#define NPCX_SHICFG2_RESTART 5
+#define NPCX_SHICFG2_REEVEN 6
+#define NPCX_EVENABLE_OBEEN 0
+#define NPCX_EVENABLE_OBHEEN 1
+#define NPCX_EVENABLE_IBFEN 2
+#define NPCX_EVENABLE_IBHFEN 3
+#define NPCX_EVENABLE_EOREN 4
+#define NPCX_EVENABLE_EOWEN 5
+#define NPCX_EVENABLE_STSREN 6
+#define NPCX_EVENABLE_IBOREN 7
+#define NPCX_EVSTAT_OBE 0
+#define NPCX_EVSTAT_OBHE 1
+#define NPCX_EVSTAT_IBF 2
+#define NPCX_EVSTAT_IBHF 3
+#define NPCX_EVSTAT_EOR 4
+#define NPCX_EVSTAT_EOW 5
+#define NPCX_EVSTAT_STSR 6
+#define NPCX_EVSTAT_IBOR 7
+#define NPCX_STATUS_OBES 6
+#define NPCX_STATUS_IBFS 7
 
 /******************************************************************************/
 /* Monotonic Counter (MTC) Registers */
-#define NPCX_TTC                         REG32(NPCX_MTC_BASE_ADDR + 0x000)
-#define NPCX_WTC                         REG32(NPCX_MTC_BASE_ADDR + 0x004)
-#define NPCX_MTCTST                       REG8(NPCX_MTC_BASE_ADDR + 0x008)
-#define NPCX_MTCVER                       REG8(NPCX_MTC_BASE_ADDR + 0x00C)
+#define NPCX_TTC REG32(NPCX_MTC_BASE_ADDR + 0x000)
+#define NPCX_WTC REG32(NPCX_MTC_BASE_ADDR + 0x004)
+#define NPCX_MTCTST REG8(NPCX_MTC_BASE_ADDR + 0x008)
+#define NPCX_MTCVER REG8(NPCX_MTC_BASE_ADDR + 0x00C)
 
 /* MTC register fields */
-#define NPCX_WTC_PTO                     30
-#define NPCX_WTC_WIE                     31
+#define NPCX_WTC_PTO 30
+#define NPCX_WTC_WIE 31
 
 /******************************************************************************/
 /* Low Power RAM definitions */
-#define NPCX_LPRAM_CTRL                  REG32(0x40001044)
+#define NPCX_LPRAM_CTRL REG32(0x40001044)
 
 /******************************************************************************/
 /*  eSPI Registers */
-#define NPCX_ESPIID                 REG32(NPCX_ESPI_BASE_ADDR + 0X00)
-#define NPCX_ESPICFG                REG32(NPCX_ESPI_BASE_ADDR + 0X04)
-#define NPCX_ESPISTS                REG32(NPCX_ESPI_BASE_ADDR + 0X08)
-#define NPCX_ESPIIE                 REG32(NPCX_ESPI_BASE_ADDR + 0X0C)
-#define NPCX_ESPIWE                 REG32(NPCX_ESPI_BASE_ADDR + 0X10)
-#define NPCX_VWREGIDX               REG32(NPCX_ESPI_BASE_ADDR + 0X14)
-#define NPCX_VWREGDATA              REG32(NPCX_ESPI_BASE_ADDR + 0X18)
-#define NPCX_OOBCTL                 REG32(NPCX_ESPI_BASE_ADDR + 0X24)
-#define NPCX_FLASHRXRDHEAD          REG32(NPCX_ESPI_BASE_ADDR + 0X28)
-#define NPCX_FLASHTXWRHEAD          REG32(NPCX_ESPI_BASE_ADDR + 0X2C)
-#define NPCX_FLASHCFG               REG32(NPCX_ESPI_BASE_ADDR + 0X34)
-#define NPCX_FLASHCTL               REG32(NPCX_ESPI_BASE_ADDR + 0X38)
-#define NPCX_ESPIERR                REG32(NPCX_ESPI_BASE_ADDR + 0X3C)
+#define NPCX_ESPIID REG32(NPCX_ESPI_BASE_ADDR + 0X00)
+#define NPCX_ESPICFG REG32(NPCX_ESPI_BASE_ADDR + 0X04)
+#define NPCX_ESPISTS REG32(NPCX_ESPI_BASE_ADDR + 0X08)
+#define NPCX_ESPIIE REG32(NPCX_ESPI_BASE_ADDR + 0X0C)
+#define NPCX_ESPIWE REG32(NPCX_ESPI_BASE_ADDR + 0X10)
+#define NPCX_VWREGIDX REG32(NPCX_ESPI_BASE_ADDR + 0X14)
+#define NPCX_VWREGDATA REG32(NPCX_ESPI_BASE_ADDR + 0X18)
+#define NPCX_OOBCTL REG32(NPCX_ESPI_BASE_ADDR + 0X24)
+#define NPCX_FLASHRXRDHEAD REG32(NPCX_ESPI_BASE_ADDR + 0X28)
+#define NPCX_FLASHTXWRHEAD REG32(NPCX_ESPI_BASE_ADDR + 0X2C)
+#define NPCX_FLASHCFG REG32(NPCX_ESPI_BASE_ADDR + 0X34)
+#define NPCX_FLASHCTL REG32(NPCX_ESPI_BASE_ADDR + 0X38)
+#define NPCX_ESPIERR REG32(NPCX_ESPI_BASE_ADDR + 0X3C)
+
+#define NPCX_ONLY_ESPI_REG1 REG8(NPCX_ESPI_BASE_ADDR + 0XF0)
+#define NPCX_ONLY_ESPI_REG2 REG8(NPCX_ESPI_BASE_ADDR + 0XF1)
+
+#define NPCX_ONLY_ESPI_REG1_UNLOCK_REG2 0x55
+#define NPCX_ONLY_ESPI_REG1_LOCK_REG2 0
+#define NPCX_ONLY_ESPI_REG2_TRANS_END_CONFIG 4
 
 /* eSPI Virtual Wire channel registers */
-#define NPCX_VWEVSM(n)              REG32(NPCX_ESPI_BASE_ADDR + 0x100 + (4*(n)))
-#define NPCX_VWEVMS(n)              REG32(NPCX_ESPI_BASE_ADDR + 0x140 + (4*(n)))
-#define NPCX_VWCTL                  REG32(NPCX_ESPI_BASE_ADDR + 0x2FC)
+#define NPCX_VWEVSM(n) REG32(NPCX_ESPI_BASE_ADDR + 0x100 + (4 * (n)))
+#define NPCX_VWEVMS(n) REG32(NPCX_ESPI_BASE_ADDR + 0x140 + (4 * (n)))
+#define NPCX_VWCTL REG32(NPCX_ESPI_BASE_ADDR + 0x2FC)
 
 /* eSPI register fields */
-#define NPCX_ESPICFG_PCHANEN             0
-#define NPCX_ESPICFG_VWCHANEN            1
-#define NPCX_ESPICFG_OOBCHANEN           2
-#define NPCX_ESPICFG_FLASHCHANEN         3
-#define NPCX_ESPICFG_IOMODE_FIELD        FIELD(8, 9)
-#define NPCX_ESPICFG_MAXFREQ_FIELD       FIELD(10, 12)
-#define NPCX_ESPICFG_PCCHN_SUPP          24
-#define NPCX_ESPICFG_VWCHN_SUPP          25
-#define NPCX_ESPICFG_OOBCHN_SUPP         26
-#define NPCX_ESPICFG_FLASHCHN_SUPP       27
-#define NPCX_ESPIIE_IBRSTIE              0
-#define NPCX_ESPIIE_CFGUPDIE             1
-#define NPCX_ESPIIE_BERRIE               2
-#define NPCX_ESPIIE_OOBRXIE              3
-#define NPCX_ESPIIE_FLASHRXIE            4
-#define NPCX_ESPIIE_SFLASHRDIE           5
-#define NPCX_ESPIIE_PERACCIE             6
-#define NPCX_ESPIIE_DFRDIE               7
-#define NPCX_ESPIIE_VWUPDIE              8
-#define NPCX_ESPIIE_ESPIRSTIE            9
-#define NPCX_ESPIIE_PLTRSTIE             10
-#define NPCX_ESPIIE_AMERRIE              15
-#define NPCX_ESPIIE_AMDONEIE             16
-#define NPCX_ESPIWE_IBRSTWE              0
-#define NPCX_ESPIWE_CFGUPDWE             1
-#define NPCX_ESPIWE_BERRWE               2
-#define NPCX_ESPIWE_OOBRXWE              3
-#define NPCX_ESPIWE_FLASHRXWE            4
-#define NPCX_ESPIWE_PERACCWE             6
-#define NPCX_ESPIWE_DFRDWE               7
-#define NPCX_ESPIWE_VWUPDWE              8
-#define NPCX_ESPIWE_ESPIRSTWE            9
-#define NPCX_ESPISTS_IBRST               0
-#define NPCX_ESPISTS_CFGUPD              1
-#define NPCX_ESPISTS_BERR                2
-#define NPCX_ESPISTS_OOBRX               3
-#define NPCX_ESPISTS_FLASHRX             4
-#define NPCX_ESPISTS_SFLASHRD            5
-#define NPCX_ESPISTS_PERACC              6
-#define NPCX_ESPISTS_DFRD                7
-#define NPCX_ESPISTS_VWUPD               8
-#define NPCX_ESPISTS_ESPIRST             9
-#define NPCX_ESPISTS_PLTRST              10
-#define NPCX_ESPISTS_AMERR               15
-#define NPCX_ESPISTS_AMDONE              16
+#define NPCX_ESPICFG_PCHANEN 0
+#define NPCX_ESPICFG_VWCHANEN 1
+#define NPCX_ESPICFG_OOBCHANEN 2
+#define NPCX_ESPICFG_FLASHCHANEN 3
+#define NPCX_ESPICFG_HPCHANEN 4
+#define NPCX_ESPICFG_HVWCHANEN 5
+#define NPCX_ESPICFG_HOOBCHANEN 6
+#define NPCX_ESPICFG_HFLASHCHANEN 7
+#define NPCX_ESPICFG_IOMODE_FIELD FIELD(8, 2)
+#define NPCX_ESPICFG_MAXFREQ_FIELD FIELD(10, 3)
+#define NPCX_ESPICFG_OPFREQ_FIELD FIELD(17, 3)
+#define NPCX_ESPICFG_IOMODESEL_FIELD FIELD(20, 2)
+#define NPCX_ESPICFG_ALERT_MODE 22
+#define NPCX_ESPICFG_CRC_CHK 23
+#define NPCX_ESPICFG_PCCHN_SUPP 24
+#define NPCX_ESPICFG_VWCHN_SUPP 25
+#define NPCX_ESPICFG_OOBCHN_SUPP 26
+#define NPCX_ESPICFG_FLASHCHN_SUPP 27
+#define NPCX_ESPIERR_INVCMD 0 /* Invalid Command Type */
+#define NPCX_ESPIERR_INVCYC 1 /* Invalid Cycle Type */
+#define NPCX_ESPIERR_CRCERR 2 /* Transaction CRC Error */
+#define NPCX_ESPIERR_ABCOMP 3 /* Abnormal Completion */
+#define NPCX_ESPIERR_PROTERR 4 /* Protocol Error */
+#define NPCX_ESPIERR_BADSIZE 5 /* Bad Size */
+#define NPCX_ESPIERR_NPBADALN 6 /* NPPC Bad Address Alignment */
+#define NPCX_ESPIERR_PCBADALN 7 /* PPC Bad Address Alignment */
+#define NPCX_ESPIERR_UNCMD 9 /* Unsupported Command */
+#define NPCX_ESPIERR_EXTRACYC 10 /* Extra eSPI Clock Cycles */
+#define NPCX_ESPIERR_VWERR 11 /* Virtual Channel Access Error */
+#define NPCX_ESPIERR_UNPBM 14 /* Unsuccessful Bus Completion */
+#define NPCX_ESPIERR_UNFLASH 15 /* Unsuccessful Flash Completion */
+#define NPCX_ESPIIE_IBRSTIE 0
+#define NPCX_ESPIIE_CFGUPDIE 1
+#define NPCX_ESPIIE_BERRIE 2
+#define NPCX_ESPIIE_OOBRXIE 3
+#define NPCX_ESPIIE_FLASHRXIE 4
+#define NPCX_ESPIIE_SFLASHRDIE 5
+#define NPCX_ESPIIE_PERACCIE 6
+#define NPCX_ESPIIE_DFRDIE 7
+#define NPCX_ESPIIE_VWUPDIE 8
+#define NPCX_ESPIIE_ESPIRSTIE 9
+#define NPCX_ESPIIE_PLTRSTIE 10
+#define NPCX_ESPIIE_AMERRIE 15
+#define NPCX_ESPIIE_AMDONEIE 16
+#define NPCX_ESPIWE_IBRSTWE 0
+#define NPCX_ESPIWE_CFGUPDWE 1
+#define NPCX_ESPIWE_BERRWE 2
+#define NPCX_ESPIWE_OOBRXWE 3
+#define NPCX_ESPIWE_FLASHRXWE 4
+#define NPCX_ESPIWE_PERACCWE 6
+#define NPCX_ESPIWE_DFRDWE 7
+#define NPCX_ESPIWE_VWUPDWE 8
+#define NPCX_ESPIWE_ESPIRSTWE 9
+#define NPCX_ESPISTS_IBRST 0
+#define NPCX_ESPISTS_CFGUPD 1
+#define NPCX_ESPISTS_BERR 2
+#define NPCX_ESPISTS_OOBRX 3
+#define NPCX_ESPISTS_FLASHRX 4
+#define NPCX_ESPISTS_SFLASHRD 5
+#define NPCX_ESPISTS_PERACC 6
+#define NPCX_ESPISTS_DFRD 7
+#define NPCX_ESPISTS_VWUPD 8
+#define NPCX_ESPISTS_ESPIRST 9
+#define NPCX_ESPISTS_PLTRST 10
+#define NPCX_ESPISTS_AMERR 15
+#define NPCX_ESPISTS_AMDONE 16
 /* eSPI Virtual Wire channel register fields */
-#define NPCX_VWEVSM_WIRE                 FIELD(0, 4)
-#define NPCX_VWEVMS_WIRE                 FIELD(0, 4)
-#define NPCX_VWEVSM_VALID                FIELD(4, 4)
-#define NPCX_VWEVMS_VALID                FIELD(4, 4)
+#define NPCX_VWEVSM_WIRE FIELD(0, 4)
+#define NPCX_VWEVMS_WIRE FIELD(0, 4)
+#define NPCX_VWEVSM_VALID FIELD(4, 4)
+#define NPCX_VWEVMS_VALID FIELD(4, 4)
 
 /* Macro functions for eSPI CFG & IE */
-#define IS_SLAVE_CHAN_ENABLE(ch)         IS_BIT_SET(NPCX_ESPICFG, ch)
-#define IS_HOST_CHAN_EN(ch)              IS_BIT_SET(NPCX_ESPICFG, (ch+4))
-#define ENABLE_ESPI_CHAN(ch)             SET_BIT(NPCX_ESPICFG, ch)
-#define DISABLE_ESPI_CHAN(ch)            CLEAR_BIT(NPCX_ESPICFG, ch)
-/* ESPI Slave Channel Support Definitions */
-#define ESPI_SUPP_CH_PC                  BIT(NPCX_ESPICFG_PCCHN_SUPP)
-#define ESPI_SUPP_CH_VM                  BIT(NPCX_ESPICFG_VWCHN_SUPP)
-#define ESPI_SUPP_CH_OOB                 BIT(NPCX_ESPICFG_OOBCHN_SUPP)
-#define ESPI_SUPP_CH_FLASH               BIT(NPCX_ESPICFG_FLASHCHN_SUPP)
-#define ESPI_SUPP_CH_ALL                 (ESPI_SUPP_CH_PC | ESPI_SUPP_CH_VM | \
-					  ESPI_SUPP_CH_OOB | ESPI_SUPP_CH_FLASH)
+#define IS_PERIPHERAL_CHAN_ENABLE(ch) IS_BIT_SET(NPCX_ESPICFG, ch)
+#define IS_HOST_CHAN_EN(ch) IS_BIT_SET(NPCX_ESPICFG, (ch + 4))
+#define ENABLE_ESPI_CHAN(ch) SET_BIT(NPCX_ESPICFG, ch)
+#define DISABLE_ESPI_CHAN(ch) CLEAR_BIT(NPCX_ESPICFG, ch)
+/* ESPI Peripheral Channel Support Definitions */
+#define ESPI_SUPP_CH_PC BIT(NPCX_ESPICFG_PCCHN_SUPP)
+#define ESPI_SUPP_CH_VM BIT(NPCX_ESPICFG_VWCHN_SUPP)
+#define ESPI_SUPP_CH_OOB BIT(NPCX_ESPICFG_OOBCHN_SUPP)
+#define ESPI_SUPP_CH_FLASH BIT(NPCX_ESPICFG_FLASHCHN_SUPP)
+#define ESPI_SUPP_CH_ALL                                        \
+	(ESPI_SUPP_CH_PC | ESPI_SUPP_CH_VM | ESPI_SUPP_CH_OOB | \
+	 ESPI_SUPP_CH_FLASH)
 /* ESPI Interrupts Enable Definitions */
-#define ESPIIE_IBRST                     BIT(NPCX_ESPIIE_IBRSTIE)
-#define ESPIIE_CFGUPD                    BIT(NPCX_ESPIIE_CFGUPDIE)
-#define ESPIIE_BERR                      BIT(NPCX_ESPIIE_BERRIE)
-#define ESPIIE_OOBRX                     BIT(NPCX_ESPIIE_OOBRXIE)
-#define ESPIIE_FLASHRX                   BIT(NPCX_ESPIIE_FLASHRXIE)
-#define ESPIIE_SFLASHRD                  BIT(NPCX_ESPIIE_SFLASHRDIE)
-#define ESPIIE_PERACC                    BIT(NPCX_ESPIIE_PERACCIE)
-#define ESPIIE_DFRD                      BIT(NPCX_ESPIIE_DFRDIE)
-#define ESPIIE_VWUPD                     BIT(NPCX_ESPIIE_VWUPDIE)
-#define ESPIIE_ESPIRST                   BIT(NPCX_ESPIIE_ESPIRSTIE)
-#define ESPIIE_PLTRST                    BIT(NPCX_ESPIIE_PLTRSTIE)
-#define ESPIIE_AMERR                     BIT(NPCX_ESPIIE_AMERRIE)
-#define ESPIIE_AMDONE                    BIT(NPCX_ESPIIE_AMDONEIE)
+#define ESPIIE_IBRST BIT(NPCX_ESPIIE_IBRSTIE)
+#define ESPIIE_CFGUPD BIT(NPCX_ESPIIE_CFGUPDIE)
+#define ESPIIE_BERR BIT(NPCX_ESPIIE_BERRIE)
+#define ESPIIE_OOBRX BIT(NPCX_ESPIIE_OOBRXIE)
+#define ESPIIE_FLASHRX BIT(NPCX_ESPIIE_FLASHRXIE)
+#define ESPIIE_SFLASHRD BIT(NPCX_ESPIIE_SFLASHRDIE)
+#define ESPIIE_PERACC BIT(NPCX_ESPIIE_PERACCIE)
+#define ESPIIE_DFRD BIT(NPCX_ESPIIE_DFRDIE)
+#define ESPIIE_VWUPD BIT(NPCX_ESPIIE_VWUPDIE)
+#define ESPIIE_ESPIRST BIT(NPCX_ESPIIE_ESPIRSTIE)
+#define ESPIIE_PLTRST BIT(NPCX_ESPIIE_PLTRSTIE)
+#define ESPIIE_AMERR BIT(NPCX_ESPIIE_AMERRIE)
+#define ESPIIE_AMDONE BIT(NPCX_ESPIIE_AMDONEIE)
 /* eSPI Interrupts for VW */
-#define ESPIIE_VW                        (ESPIIE_VWUPD | ESPIIE_PLTRST)
+#define ESPIIE_VW (ESPIIE_VWUPD | ESPIIE_PLTRST)
 /* eSPI Interrupts for Generic */
-#define ESPIIE_GENERIC                   (ESPIIE_IBRST | ESPIIE_CFGUPD | \
-					  ESPIIE_BERR | ESPIIE_ESPIRST)
+#define ESPIIE_GENERIC \
+	(ESPIIE_IBRST | ESPIIE_CFGUPD | ESPIIE_BERR | ESPIIE_ESPIRST)
 /* ESPI Wake-up Enable Definitions */
-#define ESPIWE_IBRST                     BIT(NPCX_ESPIWE_IBRSTWE)
-#define ESPIWE_CFGUPD                    BIT(NPCX_ESPIWE_CFGUPDWE)
-#define ESPIWE_BERR                      BIT(NPCX_ESPIWE_BERRWE)
-#define ESPIWE_OOBRX                     BIT(NPCX_ESPIWE_OOBRXWE)
-#define ESPIWE_FLASHRX                   BIT(NPCX_ESPIWE_FLASHRXWE)
-#define ESPIWE_PERACC                    BIT(NPCX_ESPIWE_PERACCWE)
-#define ESPIWE_DFRD                      BIT(NPCX_ESPIWE_DFRDWE)
-#define ESPIWE_VWUPD                     BIT(NPCX_ESPIWE_VWUPDWE)
-#define ESPIWE_ESPIRST                   BIT(NPCX_ESPIWE_ESPIRSTWE)
+#define ESPIWE_IBRST BIT(NPCX_ESPIWE_IBRSTWE)
+#define ESPIWE_CFGUPD BIT(NPCX_ESPIWE_CFGUPDWE)
+#define ESPIWE_BERR BIT(NPCX_ESPIWE_BERRWE)
+#define ESPIWE_OOBRX BIT(NPCX_ESPIWE_OOBRXWE)
+#define ESPIWE_FLASHRX BIT(NPCX_ESPIWE_FLASHRXWE)
+#define ESPIWE_PERACC BIT(NPCX_ESPIWE_PERACCWE)
+#define ESPIWE_DFRD BIT(NPCX_ESPIWE_DFRDWE)
+#define ESPIWE_VWUPD BIT(NPCX_ESPIWE_VWUPDWE)
+#define ESPIWE_ESPIRST BIT(NPCX_ESPIWE_ESPIRSTWE)
 /* eSPI  Wake-up enable for VW */
-#define ESPIWE_VW                        ESPIWE_VWUPD
+#define ESPIWE_VW ESPIWE_VWUPD
 /* eSPI  Wake-up enable for Generic */
-#define ESPIWE_GENERIC                   (ESPIWE_IBRST | ESPIWE_CFGUPD | \
-					  ESPIWE_BERR)
+#define ESPIWE_GENERIC (ESPIWE_IBRST | ESPIWE_CFGUPD | ESPIWE_BERR)
 /* Macro functions for eSPI VW */
-#define ESPI_VWEVMS_NUM                  12
-#define ESPI_VWEVSM_NUM                  10
-#define ESPI_VW_IDX_WIRE_NUM             4
+#define ESPI_VWEVMS_NUM 12
+#define ESPI_VWEVSM_NUM 10
+#define ESPI_VW_IDX_WIRE_NUM 4
 /* Determine Virtual Wire type */
-#define VM_TYPE(i)              ((i >= 0   && i <=  1) ? ESPI_VW_TYPE_INT_EV : \
-				 (i >= 2   && i <=  7) ? ESPI_VW_TYPE_SYS_EV : \
-				 (i >= 64  && i <= 127) ? ESPI_VW_TYPE_PLT : \
-				 (i >= 128 && i <= 255) ? ESPI_VW_TYPE_GPIO : \
-							ESPI_VW_TYPE_NONE)
+#define VM_TYPE(i)                                      \
+	((i >= 0 && i <= 1)	? ESPI_VW_TYPE_INT_EV : \
+	 (i >= 2 && i <= 7)	? ESPI_VW_TYPE_SYS_EV : \
+	 (i >= 64 && i <= 127)	? ESPI_VW_TYPE_PLT :    \
+	 (i >= 128 && i <= 255) ? ESPI_VW_TYPE_GPIO :   \
+				  ESPI_VW_TYPE_NONE)
 
 /* Bit field manipulation for VWEVMS Value */
-#define VWEVMS_INX(i)                ((i<<8)  & 0x00007F00)
-#define VWEVMS_INX_EN(n)             ((n<<15) & 0x00008000)
-#define VWEVMS_PLTRST_EN(p)          ((p<<17) & 0x00020000)
-#define VWEVMS_INT_EN(e)             ((e<<18) & 0x00040000)
-#define VWEVMS_ESPIRST_EN(r)         ((r<<19) & 0x00080000)
-#define VWEVMS_FIELD(i, n, p, e, r)  (VWEVMS_INX(i) | VWEVMS_INX_EN(n) | \
-				VWEVMS_PLTRST_EN(p) | VWEVMS_INTWK_EN(e) | \
-				VWEVMS_ESPIRST_EN(r))
-#define VWEVMS_IDX_GET(reg)          (((reg & 0x00007F00)>>8))
+#define VWEVMS_INX(i) ((i << 8) & 0x00007F00)
+#define VWEVMS_INX_EN(n) ((n << 15) & 0x00008000)
+#define VWEVMS_PLTRST_EN(p) ((p << 17) & 0x00020000)
+#define VWEVMS_INT_EN(e) ((e << 18) & 0x00040000)
+#define VWEVMS_ESPIRST_EN(r) ((r << 19) & 0x00080000)
+#define VWEVMS_FIELD(i, n, p, e, r)                               \
+	(VWEVMS_INX(i) | VWEVMS_INX_EN(n) | VWEVMS_PLTRST_EN(p) | \
+	 VWEVMS_INTWK_EN(e) | VWEVMS_ESPIRST_EN(r))
+#define VWEVMS_IDX_GET(reg) (((reg & 0x00007F00) >> 8))
 
 /* Bit field manipulation for VWEVSM Value */
-#define VWEVSM_VALID_N(v)            ((v<<4)  & 0x000000F0)
-#define VWEVSM_INX(i)                ((i<<8)  & 0x00007F00)
-#define VWEVSM_INX_EN(n)             ((n<<15) & 0x00008000)
-#define VWEVSM_DIRTY(d)              ((d<<16) & 0x00010000)
-#define VWEVSM_PLTRST_EN(p)          ((p<<17) & 0x00020000)
-#define VWEVSM_CDRST_EN(c)           ((c<<19) & 0x00080000)
-#define VWEVSM_FIELD(i, n, v, p, c)  (VWEVSM_INX(i) | VWEVSM_INX_EN(n) | \
-				VWEVSM_VALID_N(v) | VWEVSM_PLTRST_EN(p) |\
-				VWEVSM_CDRST_EN(c))
-#define VWEVSM_IDX_GET(reg)          (((reg & 0x00007F00)>>8))
+#define VWEVSM_VALID_N(v) ((v << 4) & 0x000000F0)
+#define VWEVSM_INX(i) ((i << 8) & 0x00007F00)
+#define VWEVSM_INX_EN(n) ((n << 15) & 0x00008000)
+#define VWEVSM_DIRTY(d) ((d << 16) & 0x00010000)
+#define VWEVSM_PLTRST_EN(p) ((p << 17) & 0x00020000)
+#define VWEVSM_CDRST_EN(c) ((c << 19) & 0x00080000)
+#define VWEVSM_FIELD(i, n, v, p, c)                             \
+	(VWEVSM_INX(i) | VWEVSM_INX_EN(n) | VWEVSM_VALID_N(v) | \
+	 VWEVSM_PLTRST_EN(p) | VWEVSM_CDRST_EN(c))
+#define VWEVSM_IDX_GET(reg) (((reg & 0x00007F00) >> 8))
 
 /* define macro to handle SMI/SCI Virtual Wire */
 /* Read SMI VWire status from VWEVSM(offset 2) register. */
-#define SMI_STATUS_MASK    ((uint8_t) (NPCX_VWEVSM(2) & 0x00000002))
+#define SMI_STATUS_MASK ((uint8_t)(NPCX_VWEVSM(2) & 0x00000002))
 /*
  * Read SCI VWire status from VWEVSM(offset 2) register.
  * Left shift 2 to meet the SCIB field in HIPMIC register.
  */
-#define SCI_STATUS_MASK    (((uint8_t) (NPCX_VWEVSM(2) & 0x00000001)) << 2)
-#define SCIB_MASK(v)       (v << NPCX_HIPMIC_SCIB)
-#define SMIB_MASK(v)       (v << NPCX_HIPMIC_SMIB)
-#define NPCX_VW_SCI(level)  ((NPCX_HIPMIC(PM_CHAN_1) & 0xF9) | \
-				SMI_STATUS_MASK | SCIB_MASK(level))
-#define NPCX_VW_SMI(level)  ((NPCX_HIPMIC(PM_CHAN_1) & 0xF9) | \
-				SCI_STATUS_MASK | SMIB_MASK(level))
+#define SCI_STATUS_MASK (((uint8_t)(NPCX_VWEVSM(2) & 0x00000001)) << 2)
+#define SCIB_MASK(v) (v << NPCX_HIPMIC_SCIB)
+#define SMIB_MASK(v) (v << NPCX_HIPMIC_SMIB)
+#define NPCX_VW_SCI(level) \
+	((NPCX_HIPMIC(PM_CHAN_1) & 0xF9) | SMI_STATUS_MASK | SCIB_MASK(level))
+#define NPCX_VW_SMI(level) \
+	((NPCX_HIPMIC(PM_CHAN_1) & 0xF9) | SCI_STATUS_MASK | SMIB_MASK(level))
 
 /* eSPI enumeration */
 /* eSPI channels */
@@ -1287,366 +1351,367 @@ enum {
 /* eSPI IO modes */
 enum {
 	NPCX_ESPI_IO_MODE_SINGLE = 0,
-	NPCX_ESPI_IO_MODE_DUAL   = 1,
-	NPCX_ESPI_IO_MODE_Quad   = 2,
-	NPCX_ESPI_IO_MODE_ALL    = 3,
-	NPCX_ESPI_IO_MODE_NONE   = 0xFF
+	NPCX_ESPI_IO_MODE_DUAL = 1,
+	NPCX_ESPI_IO_MODE_QUAD = 2,
+	NPCX_ESPI_IO_MODE_ALL = 3,
+	NPCX_ESPI_IO_MODE_NONE = 0xFF
+};
+
+/* eSPI IO mode selected */
+enum {
+	NPCX_ESPI_IO_MODE_SEL_SINGLE = 0,
+	NPCX_ESPI_IO_MODE_SEL_DUAL = 1,
+	NPCX_ESPI_IO_MODE_SEL_QUARD = 2,
+	NPCX_ESPI_IO_MODE_SEL_NONE = 0xFF
 };
 
 /* VW types */
 enum {
-	ESPI_VW_TYPE_INT_EV,            /* Interrupt event */
-	ESPI_VW_TYPE_SYS_EV,            /* System Event */
-	ESPI_VW_TYPE_PLT,               /* Platform specific */
-	ESPI_VW_TYPE_GPIO,              /* General Purpose I/O Expander */
+	ESPI_VW_TYPE_INT_EV, /* Interrupt event */
+	ESPI_VW_TYPE_SYS_EV, /* System Event */
+	ESPI_VW_TYPE_PLT, /* Platform specific */
+	ESPI_VW_TYPE_GPIO, /* General Purpose I/O Expander */
 	ESPI_VW_TYPE_NUM,
 	ESPI_VW_TYPE_NONE = 0xFF
 };
 
 /******************************************************************************/
 /* GDMA (General DMA) Registers */
-#define NPCX_GDMA_CTL                    REG32(NPCX_GDMA_BASE_ADDR + 0x000)
-#define NPCX_GDMA_SRCB                   REG32(NPCX_GDMA_BASE_ADDR + 0x004)
-#define NPCX_GDMA_DSTB                   REG32(NPCX_GDMA_BASE_ADDR + 0x008)
-#define NPCX_GDMA_TCNT                   REG32(NPCX_GDMA_BASE_ADDR + 0x00C)
-#define NPCX_GDMA_CSRC                   REG32(NPCX_GDMA_BASE_ADDR + 0x010)
-#define NPCX_GDMA_CDST                   REG32(NPCX_GDMA_BASE_ADDR + 0x014)
-#define NPCX_GDMA_CTCNT                  REG32(NPCX_GDMA_BASE_ADDR + 0x018)
-
+#define NPCX_GDMA_CTL REG32(NPCX_GDMA_BASE_ADDR + 0x000)
+#define NPCX_GDMA_SRCB REG32(NPCX_GDMA_BASE_ADDR + 0x004)
+#define NPCX_GDMA_DSTB REG32(NPCX_GDMA_BASE_ADDR + 0x008)
+#define NPCX_GDMA_TCNT REG32(NPCX_GDMA_BASE_ADDR + 0x00C)
+#define NPCX_GDMA_CSRC REG32(NPCX_GDMA_BASE_ADDR + 0x010)
+#define NPCX_GDMA_CDST REG32(NPCX_GDMA_BASE_ADDR + 0x014)
+#define NPCX_GDMA_CTCNT REG32(NPCX_GDMA_BASE_ADDR + 0x018)
 
 /******************************************************************************/
 /* GDMA register fields */
-#define NPCX_GDMA_CTL_GDMAEN                         0
-#define NPCX_GDMA_CTL_GDMAMS                         FIELD(2,   2)
-#define NPCX_GDMA_CTL_DADIR                          4
-#define NPCX_GDMA_CTL_SADIR                          5
-#define NPCX_GDMA_CTL_SAFIX                          7
-#define NPCX_GDMA_CTL_SIEN                           8
-#define NPCX_GDMA_CTL_BME                            9
-#define NPCX_GDMA_CTL_SBMS                           11
-#define NPCX_GDMA_CTL_TWS                            FIELD(12,  2)
-#define NPCX_GDMA_CTL_DM                             15
-#define NPCX_GDMA_CTL_SOFTREQ                        16
-#define NPCX_GDMA_CTL_TC                             18
-#define NPCX_GDMA_CTL_GDMAERR                        20
-#define NPCX_GDMA_CTL_BLOCK_BUG_CORRECTION_DISABLE   26
+#define NPCX_GDMA_CTL_GDMAEN 0
+#define NPCX_GDMA_CTL_GDMAMS FIELD(2, 2)
+#define NPCX_GDMA_CTL_DADIR 4
+#define NPCX_GDMA_CTL_SADIR 5
+#define NPCX_GDMA_CTL_SAFIX 7
+#define NPCX_GDMA_CTL_SIEN 8
+#define NPCX_GDMA_CTL_BME 9
+#define NPCX_GDMA_CTL_SBMS 11
+#define NPCX_GDMA_CTL_TWS FIELD(12, 2)
+#define NPCX_GDMA_CTL_DM 15
+#define NPCX_GDMA_CTL_SOFTREQ 16
+#define NPCX_GDMA_CTL_TC 18
+#define NPCX_GDMA_CTL_GDMAERR 20
+#define NPCX_GDMA_CTL_BLOCK_BUG_CORRECTION_DISABLE 26
 
 /******************************************************************************/
 /* Nuvoton internal used only registers */
-#define NPCX_INTERNAL_CTRL1               REG8(0x400DB000)
-#define NPCX_INTERNAL_CTRL2               REG8(0x400DD000)
-#define NPCX_INTERNAL_CTRL3               REG8(0x400DF000)
+#define NPCX_INTERNAL_CTRL1 REG8(0x400DB000)
+#define NPCX_INTERNAL_CTRL2 REG8(0x400DD000)
+#define NPCX_INTERNAL_CTRL3 REG8(0x400DF000)
 
 /******************************************************************************/
 /* Optional M4 Registers */
-#define CPU_DHCSR                        REG32(0xE000EDF0)
-#define CPU_MPU_CTRL                     REG32(0xE000ED94)
-#define CPU_MPU_RNR                      REG32(0xE000ED98)
-#define CPU_MPU_RBAR                     REG32(0xE000ED9C)
-#define CPU_MPU_RASR                     REG32(0xE000EDA0)
-
+#define CPU_DHCSR REG32(0xE000EDF0)
+#define CPU_MPU_CTRL REG32(0xE000ED94)
+#define CPU_MPU_RNR REG32(0xE000ED98)
+#define CPU_MPU_RBAR REG32(0xE000ED9C)
+#define CPU_MPU_RASR REG32(0xE000EDA0)
 
 /******************************************************************************/
 /* Flash Utiltiy definition */
 /*
  *  Flash commands for the W25Q16CV SPI flash
  */
-#define CMD_READ_ID                      0x9F
-#define CMD_READ_MAN_DEV_ID              0x90
-#define CMD_WRITE_EN                     0x06
-#define CMD_WRITE_STATUS                 0x50
-#define CMD_READ_STATUS_REG              0x05
-#define CMD_READ_STATUS_REG2             0x35
-#define CMD_WRITE_STATUS_REG             0x01
-#define CMD_FLASH_PROGRAM                0x02
-#define CMD_SECTOR_ERASE                 0x20
-#define CMD_BLOCK_32K_ERASE              0x52
-#define CMD_BLOCK_64K_ERASE              0xd8
-#define CMD_PROGRAM_UINT_SIZE            0x08
-#define CMD_PAGE_SIZE                    0x00
-#define CMD_READ_ID_TYPE                 0x47
-#define CMD_FAST_READ                    0x0B
+#define CMD_READ_ID 0x9F
+#define CMD_READ_MAN_DEV_ID 0x90
+#define CMD_WRITE_EN 0x06
+#define CMD_WRITE_STATUS 0x50
+#define CMD_READ_STATUS_REG 0x05
+#define CMD_READ_STATUS_REG2 0x35
+#define CMD_WRITE_STATUS_REG 0x01
+#define CMD_FLASH_PROGRAM 0x02
+#define CMD_SECTOR_ERASE 0x20
+#define CMD_BLOCK_32K_ERASE 0x52
+#define CMD_BLOCK_64K_ERASE 0xd8
+#define CMD_PROGRAM_UINT_SIZE 0x08
+#define CMD_PAGE_SIZE 0x00
+#define CMD_READ_ID_TYPE 0x47
+#define CMD_FAST_READ 0x0B
 
 /*
  * Status registers for the W25Q16CV SPI flash
  */
-#define SPI_FLASH_SR2_SUS               BIT(7)
-#define SPI_FLASH_SR2_CMP               BIT(6)
-#define SPI_FLASH_SR2_LB3               BIT(5)
-#define SPI_FLASH_SR2_LB2               BIT(4)
-#define SPI_FLASH_SR2_LB1               BIT(3)
-#define SPI_FLASH_SR2_QE                BIT(1)
-#define SPI_FLASH_SR2_SRP1              BIT(0)
-#define SPI_FLASH_SR1_SRP0              BIT(7)
-#define SPI_FLASH_SR1_SEC               BIT(6)
-#define SPI_FLASH_SR1_TB                BIT(5)
-#define SPI_FLASH_SR1_BP2               BIT(4)
-#define SPI_FLASH_SR1_BP1               BIT(3)
-#define SPI_FLASH_SR1_BP0               BIT(2)
-#define SPI_FLASH_SR1_WEL               BIT(1)
-#define SPI_FLASH_SR1_BUSY              BIT(0)
-
+#define SPI_FLASH_SR2_SUS BIT(7)
+#define SPI_FLASH_SR2_CMP BIT(6)
+#define SPI_FLASH_SR2_LB3 BIT(5)
+#define SPI_FLASH_SR2_LB2 BIT(4)
+#define SPI_FLASH_SR2_LB1 BIT(3)
+#define SPI_FLASH_SR2_QE BIT(1)
+#define SPI_FLASH_SR2_SRP1 BIT(0)
+#define SPI_FLASH_SR1_SRP0 BIT(7)
+#define SPI_FLASH_SR1_SEC BIT(6)
+#define SPI_FLASH_SR1_TB BIT(5)
+#define SPI_FLASH_SR1_BP2 BIT(4)
+#define SPI_FLASH_SR1_BP1 BIT(3)
+#define SPI_FLASH_SR1_BP0 BIT(2)
+#define SPI_FLASH_SR1_WEL BIT(1)
+#define SPI_FLASH_SR1_BUSY BIT(0)
 
 /* 0: F_CS0 1: F_CS1_1(GPIO86) 2:F_CS1_2(GPIOA6) */
-#define FIU_CHIP_SELECT		0
+#define FIU_CHIP_SELECT 0
 /* Create UMA control mask */
-#define MASK(bit)       (0x1 << (bit))
-#define A_SIZE          0x03	/* 0: No ADR field 1: 3-bytes ADR field */
-#define C_SIZE          0x04	/* 0: 1-Byte CMD field 1:No CMD field */
-#define RD_WR           0x05	/* 0: Read 1: Write */
-#define DEV_NUM         0x06	/* 0: PVT is used 1: SHD is used */
-#define EXEC_DONE       0x07
-#define D_SIZE_1        0x01
-#define D_SIZE_2        0x02
-#define D_SIZE_3        0x03
-#define D_SIZE_4        0x04
-#define FLASH_SEL       MASK(DEV_NUM)
-
-#define MASK_CMD_ONLY   (MASK(EXEC_DONE) | FLASH_SEL)
-#define MASK_CMD_ADR    (MASK(EXEC_DONE) | FLASH_SEL | MASK(A_SIZE))
-#define MASK_CMD_ADR_WR (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR)  \
-			|MASK(A_SIZE) | D_SIZE_1)
-#define MASK_RD_1BYTE   (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_1)
-#define MASK_RD_2BYTE   (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_2)
-#define MASK_RD_3BYTE   (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_3)
-#define MASK_RD_4BYTE   (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_4)
-#define MASK_CMD_RD_1BYTE       (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_1)
-#define MASK_CMD_RD_2BYTE       (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_2)
-#define MASK_CMD_RD_3BYTE       (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_3)
-#define MASK_CMD_RD_4BYTE       (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_4)
-#define MASK_CMD_WR_ONLY        (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR))
-#define MASK_CMD_WR_1BYTE       (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) \
-				| MASK(C_SIZE) | D_SIZE_1)
-#define MASK_CMD_WR_2BYTE       (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) \
-				| MASK(C_SIZE) | D_SIZE_2)
-#define MASK_CMD_WR_ADR         (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) \
-				| MASK(A_SIZE))
+#define MASK(bit) (0x1 << (bit))
+#define A_SIZE 0x03 /* 0: No ADR field 1: 3-bytes ADR field */
+#define C_SIZE 0x04 /* 0: 1-Byte CMD field 1:No CMD field */
+#define RD_WR 0x05 /* 0: Read 1: Write */
+#define DEV_NUM 0x06 /* 0: PVT is used 1: SHD is used */
+#define EXEC_DONE 0x07
+#define D_SIZE_1 0x01
+#define D_SIZE_2 0x02
+#define D_SIZE_3 0x03
+#define D_SIZE_4 0x04
+#define FLASH_SEL MASK(DEV_NUM)
+
+#define MASK_CMD_ONLY (MASK(EXEC_DONE) | FLASH_SEL)
+#define MASK_CMD_ADR (MASK(EXEC_DONE) | FLASH_SEL | MASK(A_SIZE))
+#define MASK_CMD_ADR_WR \
+	(MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) | MASK(A_SIZE) | D_SIZE_1)
+#define MASK_RD_1BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_1)
+#define MASK_RD_2BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_2)
+#define MASK_RD_3BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_3)
+#define MASK_RD_4BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_4)
+#define MASK_CMD_RD_1BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_1)
+#define MASK_CMD_RD_2BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_2)
+#define MASK_CMD_RD_3BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_3)
+#define MASK_CMD_RD_4BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_4)
+#define MASK_CMD_WR_ONLY (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR))
+#define MASK_CMD_WR_1BYTE \
+	(MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) | MASK(C_SIZE) | D_SIZE_1)
+#define MASK_CMD_WR_2BYTE \
+	(MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) | MASK(C_SIZE) | D_SIZE_2)
+#define MASK_CMD_WR_ADR \
+	(MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) | MASK(A_SIZE))
 
 /******************************************************************************/
 /* APM (Audio Processing Module) Registers */
-#define NPCX_APM_SR                 REG8(NPCX_APM_BASE_ADDR + 0x000)
-#define NPCX_APM_SR2                REG8(NPCX_APM_BASE_ADDR + 0x004)
-#define NPCX_APM_ICR                REG8(NPCX_APM_BASE_ADDR + 0x008)
-#define NPCX_APM_IMR                REG8(NPCX_APM_BASE_ADDR + 0x00C)
-#define NPCX_APM_IFR                REG8(NPCX_APM_BASE_ADDR + 0x010)
-#define NPCX_APM_CR_APM             REG8(NPCX_APM_BASE_ADDR + 0x014)
-#define NPCX_APM_CR_CK              REG8(NPCX_APM_BASE_ADDR + 0x018)
-#define NPCX_APM_AICR_ADC           REG8(NPCX_APM_BASE_ADDR + 0x01C)
-#define NPCX_APM_FCR_ADC            REG8(NPCX_APM_BASE_ADDR + 0x020)
-#define NPCX_APM_CR_DMIC            REG8(NPCX_APM_BASE_ADDR + 0x02C)
-#define NPCX_APM_CR_ADC             REG8(NPCX_APM_BASE_ADDR + 0x030)
-#define NPCX_APM_CR_MIX             REG8(NPCX_APM_BASE_ADDR + 0x034)
-#define NPCX_APM_DR_MIX             REG8(NPCX_APM_BASE_ADDR + 0x038)
-#define NPCX_APM_GCR_ADCL           REG8(NPCX_APM_BASE_ADDR + 0x03C)
-#define NPCX_APM_GCR_ADCR           REG8(NPCX_APM_BASE_ADDR + 0x040)
-#define NPCX_APM_GCR_MIXADCL        REG8(NPCX_APM_BASE_ADDR + 0x044)
-#define NPCX_APM_GCR_MIXADCR        REG8(NPCX_APM_BASE_ADDR + 0x048)
-#define NPCX_APM_CR_ADC_AGC         REG8(NPCX_APM_BASE_ADDR + 0x04C)
-#define NPCX_APM_DR_ADC_AGC         REG8(NPCX_APM_BASE_ADDR + 0x050)
-#define NPCX_APM_SR_ADC_AGCDGL      REG8(NPCX_APM_BASE_ADDR + 0x054)
-#define NPCX_APM_SR_ADC_AGCDGR      REG8(NPCX_APM_BASE_ADDR + 0x058)
-#define NPCX_APM_CR_VAD             REG8(NPCX_APM_BASE_ADDR + 0x05C)
-#define NPCX_APM_DR_VAD             REG8(NPCX_APM_BASE_ADDR + 0x060)
-#define NPCX_APM_CR_VAD_CMD         REG8(NPCX_APM_BASE_ADDR + 0x064)
-#define NPCX_APM_CR_TR              REG8(NPCX_APM_BASE_ADDR + 0x068)
-#define NPCX_APM_DR_TR              REG8(NPCX_APM_BASE_ADDR + 0x06C)
-#define NPCX_APM_SR_TR1             REG8(NPCX_APM_BASE_ADDR + 0x070)
-#define NPCX_APM_SR_TR_SRCADC       REG8(NPCX_APM_BASE_ADDR + 0x074)
+#define NPCX_APM_SR REG8(NPCX_APM_BASE_ADDR + 0x000)
+#define NPCX_APM_SR2 REG8(NPCX_APM_BASE_ADDR + 0x004)
+#define NPCX_APM_ICR REG8(NPCX_APM_BASE_ADDR + 0x008)
+#define NPCX_APM_IMR REG8(NPCX_APM_BASE_ADDR + 0x00C)
+#define NPCX_APM_IFR REG8(NPCX_APM_BASE_ADDR + 0x010)
+#define NPCX_APM_CR_APM REG8(NPCX_APM_BASE_ADDR + 0x014)
+#define NPCX_APM_CR_CK REG8(NPCX_APM_BASE_ADDR + 0x018)
+#define NPCX_APM_AICR_ADC REG8(NPCX_APM_BASE_ADDR + 0x01C)
+#define NPCX_APM_FCR_ADC REG8(NPCX_APM_BASE_ADDR + 0x020)
+#define NPCX_APM_CR_DMIC REG8(NPCX_APM_BASE_ADDR + 0x02C)
+#define NPCX_APM_CR_ADC REG8(NPCX_APM_BASE_ADDR + 0x030)
+#define NPCX_APM_CR_MIX REG8(NPCX_APM_BASE_ADDR + 0x034)
+#define NPCX_APM_DR_MIX REG8(NPCX_APM_BASE_ADDR + 0x038)
+#define NPCX_APM_GCR_ADCL REG8(NPCX_APM_BASE_ADDR + 0x03C)
+#define NPCX_APM_GCR_ADCR REG8(NPCX_APM_BASE_ADDR + 0x040)
+#define NPCX_APM_GCR_MIXADCL REG8(NPCX_APM_BASE_ADDR + 0x044)
+#define NPCX_APM_GCR_MIXADCR REG8(NPCX_APM_BASE_ADDR + 0x048)
+#define NPCX_APM_CR_ADC_AGC REG8(NPCX_APM_BASE_ADDR + 0x04C)
+#define NPCX_APM_DR_ADC_AGC REG8(NPCX_APM_BASE_ADDR + 0x050)
+#define NPCX_APM_SR_ADC_AGCDGL REG8(NPCX_APM_BASE_ADDR + 0x054)
+#define NPCX_APM_SR_ADC_AGCDGR REG8(NPCX_APM_BASE_ADDR + 0x058)
+#define NPCX_APM_CR_VAD REG8(NPCX_APM_BASE_ADDR + 0x05C)
+#define NPCX_APM_DR_VAD REG8(NPCX_APM_BASE_ADDR + 0x060)
+#define NPCX_APM_CR_VAD_CMD REG8(NPCX_APM_BASE_ADDR + 0x064)
+#define NPCX_APM_CR_TR REG8(NPCX_APM_BASE_ADDR + 0x068)
+#define NPCX_APM_DR_TR REG8(NPCX_APM_BASE_ADDR + 0x06C)
+#define NPCX_APM_SR_TR1 REG8(NPCX_APM_BASE_ADDR + 0x070)
+#define NPCX_APM_SR_TR_SRCADC REG8(NPCX_APM_BASE_ADDR + 0x074)
 
 /******************************************************************************/
 /* APM register fields */
-#define NPCX_APM_SR_IRQ_PEND                    6
-#define NPCX_APM_SR2_SMUTEIP                    6
-#define NPCX_APM_ICR_INTR_MODE                  FIELD(6, 2)
-#define NPCX_APM_IMR_VAD_DTC_MASK               6
-#define NPCX_APM_IFR_VAD_DTC                    6
-#define NPCX_APM_CR_APM_PD                      0
-#define NPCX_APM_CR_APM_AGC_DIS                 FIELD(1, 2)
-#define NPCX_APM_CR_CK_MCLK_FREQ                FIELD(0, 2)
-#define NPCX_APM_AICR_ADC_ADC_AUDIOIF           FIELD(0, 2)
-#define NPCX_APM_AICR_ADC_PD_AICR_ADC           4
-#define NPCX_APM_AICR_ADC_ADC_ADWL              FIELD(6, 2)
-#define NPCX_APM_FCR_ADC_ADC_FREQ               FIELD(0, 4)
-#define NPCX_APM_FCR_ADC_ADC_WNF                FIELD(4, 2)
-#define NPCX_APM_FCR_ADC_ADC_HPF                6
-#define NPCX_APM_CR_DMIC_ADC_DMIC_SEL_RIGHT     FIELD(0, 2)
-#define NPCX_APM_CR_DMIC_ADC_DMIC_SEL_LEFT      FIELD(2, 2)
-#define NPCX_APM_CR_DMIC_ADC_DMIC_RATE          FIELD(4, 3)
-#define NPCX_APM_CR_DMIC_PD_DMIC                7
-#define NPCX_APM_CR_ADC_ADC_SOFT_MUTE           7
-#define NPCX_APM_CR_MIX_MIX_ADD                 FIELD(0, 6)
-#define NPCX_APM_CR_MIX_MIX_LOAD                6
-#define NPCX_APM_DR_MIX_MIX_DATA                FIELD(0, 8)
-#define NPCX_APM_MIX_2_AIADCR_SEL               FIELD(4, 2)
-#define NPCX_APM_MIX_2_AIADCL_SEL               FIELD(6, 2)
-#define NPCX_APM_GCR_ADCL_GIDL                  FIELD(0, 6)
-#define NPCX_APM_GCR_ADCL_LRGID                 7
-#define NPCX_APM_GCR_ADCR_GIDR                  FIELD(0, 6)
-#define NPCX_APM_GCR_MIXADCL_GIMIXL             FIELD(0, 6)
-#define NPCX_APM_GCR_MIXADCR_GIMIXR             FIELD(0, 6)
-#define NPCX_APM_CR_ADC_AGC_ADC_AGC_ADD         FIELD(0, 6)
-#define NPCX_APM_CR_ADC_AGC_ADC_AGC_LOAD        6
-#define NPCX_APM_CR_ADC_AGC_ADC_AGC_EN          7
-#define NPCX_APM_DR_ADC_AGC_ADC_AGC_DATA        FIELD(0, 8)
-#define NPCX_ADC_AGC_0_AGC_TARGET               FIELD(2, 4)
-#define NPCX_ADC_AGC_0_AGC_STEREO               6
-#define NPCX_ADC_AGC_1_HOLD                     FIELD(0, 4)
-#define NPCX_ADC_AGC_1_NG_THR                   FIELD(4, 3)
-#define NPCX_ADC_AGC_1_NG_EN                    7
-#define NPCX_ADC_AGC_2_DCY                      FIELD(0, 4)
-#define NPCX_ADC_AGC_2_ATK                      FIELD(4, 4)
-#define NPCX_ADC_AGC_3_AGC_MAX                  FIELD(0, 5)
-#define NPCX_ADC_AGC_4_AGC_MIN                  FIELD(0, 5)
-#define NPCX_APM_CR_VAD_VAD_ADD                 FIELD(0, 6)
-#define NPCX_APM_CR_VAD_VAD_LOAD                6
-#define NPCX_APM_CR_VAD_VAD_EN                  7
-#define NPCX_APM_DR_VAD_VAD_DATA                FIELD(0, 8)
-#define NPCX_APM_CR_VAD_CMD_VAD_RESTART         0
-#define NPCX_APM_CR_TR_FAST_ON                  7
-#define NPCX_VAD_0_VAD_INSEL                    FIELD(0, 2)
-#define NPCX_VAD_0_VAD_DMIC_FREQ                FIELD(2, 3)
-#define NPCX_VAD_0_VAD_ADC_WAKEUP               5
-#define NPCX_VAD_0_ZCD_EN                       6
-#define NPCX_VAD_1_VAD_POWER_SENS               FIELD(0, 5)
-#define NPCX_APM_CONTROL_ADD                    FIELD(0, 6)
-#define NPCX_APM_CONTROL_LOAD                   6
+#define NPCX_APM_SR_IRQ_PEND 6
+#define NPCX_APM_SR2_SMUTEIP 6
+#define NPCX_APM_ICR_INTR_MODE FIELD(6, 2)
+#define NPCX_APM_IMR_VAD_DTC_MASK 6
+#define NPCX_APM_IFR_VAD_DTC 6
+#define NPCX_APM_CR_APM_PD 0
+#define NPCX_APM_CR_APM_AGC_DIS FIELD(1, 2)
+#define NPCX_APM_CR_CK_MCLK_FREQ FIELD(0, 2)
+#define NPCX_APM_AICR_ADC_ADC_AUDIOIF FIELD(0, 2)
+#define NPCX_APM_AICR_ADC_PD_AICR_ADC 4
+#define NPCX_APM_AICR_ADC_ADC_ADWL FIELD(6, 2)
+#define NPCX_APM_FCR_ADC_ADC_FREQ FIELD(0, 4)
+#define NPCX_APM_FCR_ADC_ADC_WNF FIELD(4, 2)
+#define NPCX_APM_FCR_ADC_ADC_HPF 6
+#define NPCX_APM_CR_DMIC_ADC_DMIC_SEL_RIGHT FIELD(0, 2)
+#define NPCX_APM_CR_DMIC_ADC_DMIC_SEL_LEFT FIELD(2, 2)
+#define NPCX_APM_CR_DMIC_ADC_DMIC_RATE FIELD(4, 3)
+#define NPCX_APM_CR_DMIC_PD_DMIC 7
+#define NPCX_APM_CR_ADC_ADC_SOFT_MUTE 7
+#define NPCX_APM_CR_MIX_MIX_ADD FIELD(0, 6)
+#define NPCX_APM_CR_MIX_MIX_LOAD 6
+#define NPCX_APM_DR_MIX_MIX_DATA FIELD(0, 8)
+#define NPCX_APM_MIX_2_AIADCR_SEL FIELD(4, 2)
+#define NPCX_APM_MIX_2_AIADCL_SEL FIELD(6, 2)
+#define NPCX_APM_GCR_ADCL_GIDL FIELD(0, 6)
+#define NPCX_APM_GCR_ADCL_LRGID 7
+#define NPCX_APM_GCR_ADCR_GIDR FIELD(0, 6)
+#define NPCX_APM_GCR_MIXADCL_GIMIXL FIELD(0, 6)
+#define NPCX_APM_GCR_MIXADCR_GIMIXR FIELD(0, 6)
+#define NPCX_APM_CR_ADC_AGC_ADC_AGC_ADD FIELD(0, 6)
+#define NPCX_APM_CR_ADC_AGC_ADC_AGC_LOAD 6
+#define NPCX_APM_CR_ADC_AGC_ADC_AGC_EN 7
+#define NPCX_APM_DR_ADC_AGC_ADC_AGC_DATA FIELD(0, 8)
+#define NPCX_ADC_AGC_0_AGC_TARGET FIELD(2, 4)
+#define NPCX_ADC_AGC_0_AGC_STEREO 6
+#define NPCX_ADC_AGC_1_HOLD FIELD(0, 4)
+#define NPCX_ADC_AGC_1_NG_THR FIELD(4, 3)
+#define NPCX_ADC_AGC_1_NG_EN 7
+#define NPCX_ADC_AGC_2_DCY FIELD(0, 4)
+#define NPCX_ADC_AGC_2_ATK FIELD(4, 4)
+#define NPCX_ADC_AGC_3_AGC_MAX FIELD(0, 5)
+#define NPCX_ADC_AGC_4_AGC_MIN FIELD(0, 5)
+#define NPCX_APM_CR_VAD_VAD_ADD FIELD(0, 6)
+#define NPCX_APM_CR_VAD_VAD_LOAD 6
+#define NPCX_APM_CR_VAD_VAD_EN 7
+#define NPCX_APM_DR_VAD_VAD_DATA FIELD(0, 8)
+#define NPCX_APM_CR_VAD_CMD_VAD_RESTART 0
+#define NPCX_APM_CR_TR_FAST_ON 7
+#define NPCX_VAD_0_VAD_INSEL FIELD(0, 2)
+#define NPCX_VAD_0_VAD_DMIC_FREQ FIELD(2, 3)
+#define NPCX_VAD_0_VAD_ADC_WAKEUP 5
+#define NPCX_VAD_0_ZCD_EN 6
+#define NPCX_VAD_1_VAD_POWER_SENS FIELD(0, 5)
+#define NPCX_APM_CONTROL_ADD FIELD(0, 6)
+#define NPCX_APM_CONTROL_LOAD 6
 
 /******************************************************************************/
 /* FMUL2 (Frequency Multiplier Module 2) Registers */
-#define NPCX_FMUL2_FM2CTRL          REG8(NPCX_FMUL2_BASE_ADDR + 0x000)
-#define NPCX_FMUL2_FM2ML            REG8(NPCX_FMUL2_BASE_ADDR + 0x002)
-#define NPCX_FMUL2_FM2MH            REG8(NPCX_FMUL2_BASE_ADDR + 0x004)
-#define NPCX_FMUL2_FM2N             REG8(NPCX_FMUL2_BASE_ADDR + 0x006)
-#define NPCX_FMUL2_FM2P             REG8(NPCX_FMUL2_BASE_ADDR + 0x008)
-#define NPCX_FMUL2_FM2_VER          REG8(NPCX_FMUL2_BASE_ADDR + 0x00A)
+#define NPCX_FMUL2_FM2CTRL REG8(NPCX_FMUL2_BASE_ADDR + 0x000)
+#define NPCX_FMUL2_FM2ML REG8(NPCX_FMUL2_BASE_ADDR + 0x002)
+#define NPCX_FMUL2_FM2MH REG8(NPCX_FMUL2_BASE_ADDR + 0x004)
+#define NPCX_FMUL2_FM2N REG8(NPCX_FMUL2_BASE_ADDR + 0x006)
+#define NPCX_FMUL2_FM2P REG8(NPCX_FMUL2_BASE_ADDR + 0x008)
+#define NPCX_FMUL2_FM2_VER REG8(NPCX_FMUL2_BASE_ADDR + 0x00A)
 
 /******************************************************************************/
 /* FMUL2 register fields */
-#define NPCX_FMUL2_FM2CTRL_LOAD2                0
-#define NPCX_FMUL2_FM2CTRL_LOCK2                2
-#define NPCX_FMUL2_FM2CTRL_FMUL2_DIS            5
-#define NPCX_FMUL2_FM2CTRL_TUNE_DIS             6
-#define NPCX_FMUL2_FM2CTRL_CLK2_CHNG            7
-#define NPCX_FMUL2_FM2N_FM2N                    FIELD(0, 6)
-#define NPCX_FMUL2_FM2P_WFPRED                  FIELD(4, 4)
+#define NPCX_FMUL2_FM2CTRL_LOAD2 0
+#define NPCX_FMUL2_FM2CTRL_LOCK2 2
+#define NPCX_FMUL2_FM2CTRL_FMUL2_DIS 5
+#define NPCX_FMUL2_FM2CTRL_TUNE_DIS 6
+#define NPCX_FMUL2_FM2CTRL_CLK2_CHNG 7
+#define NPCX_FMUL2_FM2N_FM2N FIELD(0, 6)
+#define NPCX_FMUL2_FM2P_WFPRED FIELD(4, 4)
 
 /******************************************************************************/
 /* WOV (Wake-on-Voice) Registers */
-#define NPCX_WOV_CLOCK_CNTL         REG32(NPCX_WOV_BASE_ADDR + 0x000)
-#define NPCX_WOV_PLL_CNTL1          REG32(NPCX_WOV_BASE_ADDR + 0x004)
-#define NPCX_WOV_PLL_CNTL2          REG32(NPCX_WOV_BASE_ADDR + 0x008)
-#define NPCX_WOV_FIFO_CNT           REG32(NPCX_WOV_BASE_ADDR + 0x00C)
-#define NPCX_WOV_FIFO_OUT           REG32(NPCX_WOV_BASE_ADDR + 0x010)
-#define NPCX_WOV_STATUS             REG32(NPCX_WOV_BASE_ADDR + 0x014)
-#define NPCX_WOV_WOV_INTEN          REG32(NPCX_WOV_BASE_ADDR + 0x018)
-#define NPCX_WOV_APM_CTRL           REG32(NPCX_WOV_BASE_ADDR + 0x01C)
-#define NPCX_WOV_I2S_CNTL(n)        REG32(NPCX_WOV_BASE_ADDR + 0x020 + (4*n))
-#define NPCX_WOV_VERSION            REG32(NPCX_WOV_BASE_ADDR + 0x030)
+#define NPCX_WOV_CLOCK_CNTL REG32(NPCX_WOV_BASE_ADDR + 0x000)
+#define NPCX_WOV_PLL_CNTL1 REG32(NPCX_WOV_BASE_ADDR + 0x004)
+#define NPCX_WOV_PLL_CNTL2 REG32(NPCX_WOV_BASE_ADDR + 0x008)
+#define NPCX_WOV_FIFO_CNT REG32(NPCX_WOV_BASE_ADDR + 0x00C)
+#define NPCX_WOV_FIFO_OUT REG32(NPCX_WOV_BASE_ADDR + 0x010)
+#define NPCX_WOV_STATUS REG32(NPCX_WOV_BASE_ADDR + 0x014)
+#define NPCX_WOV_WOV_INTEN REG32(NPCX_WOV_BASE_ADDR + 0x018)
+#define NPCX_WOV_APM_CTRL REG32(NPCX_WOV_BASE_ADDR + 0x01C)
+#define NPCX_WOV_I2S_CNTL(n) REG32(NPCX_WOV_BASE_ADDR + 0x020 + (4 * n))
+#define NPCX_WOV_VERSION REG32(NPCX_WOV_BASE_ADDR + 0x030)
 
 /******************************************************************************/
 /* WOV register fields */
-#define NPCX_WOV_CLOCK_CNT_CLK_SEL              0
-#define NPCX_WOV_CLOCK_CNT_DMIC_EN              3
-#define NPCX_WOV_CLOCK_CNT_PLL_EDIV_SEL         7
-#define NPCX_WOV_CLOCK_CNT_PLL_EDIV             FIELD(8, 7)
-#define NPCX_WOV_CLOCK_CNT_PLL_EDIV_DC          FIELD(16, 7)
-#define NPCX_WOV_CLOCK_CNT_DMIC_CKDIV_EN        24
-#define NPCX_WOV_CLOCK_CNT_DMIC_CKDIV_SEL       25
-#define NPCX_WOV_FIFO_CNT_FIFO_ITHRSH           FIELD(0, 6)
-#define NPCX_WOV_FIFO_CNT_FIFO_WTHRSH           FIELD(6, 6)
-#define NPCX_WOV_FIFO_CNT_I2S_FFRST             13
-#define NPCX_WOV_FIFO_CNT_CORE_FFRST            14
-#define NPCX_WOV_FIFO_CNT_CFIFO_ISEL            FIELD(16, 3)
-#define NPCX_WOV_STATUS_CFIFO_CNT               FIELD(0, 8)
-#define NPCX_WOV_STATUS_CFIFO_NE                8
-#define NPCX_WOV_STATUS_CFIFO_OIT               9
-#define NPCX_WOV_STATUS_CFIFO_OWT               10
-#define NPCX_WOV_STATUS_CFIFO_OVRN              11
-#define NPCX_WOV_STATUS_I2S_FIFO_OVRN           12
-#define NPCX_WOV_STATUS_I2S_FIFO_UNDRN          13
-#define NPCX_WOV_STATUS_BITS			FIELD(9, 6)
-#define NPCX_WOV_INTEN_VAD_INTEN                0
-#define NPCX_WOV_INTEN_VAD_WKEN                 1
-#define NPCX_WOV_INTEN_CFIFO_NE_IE              8
-#define NPCX_WOV_INTEN_CFIFO_OIT_IE             9
-#define NPCX_WOV_INTEN_CFIFO_OWT_WE             10
-#define NPCX_WOV_INTEN_CFIFO_OVRN_IE            11
-#define NPCX_WOV_INTEN_I2S_FIFO_OVRN_IE         12
-#define NPCX_WOV_INTEN_I2S_FIFO_UNDRN_IE        13
-#define NPCX_WOV_APM_CTRL_APM_RST               0
-#define NPCX_WOV_PLL_CNTL1_PLL_PWDEN            0
-#define NPCX_WOV_PLL_CNTL1_PLL_OTDV1            FIELD(4, 4)
-#define NPCX_WOV_PLL_CNTL1_PLL_OTDV2            FIELD(8, 4)
-#define NPCX_WOV_PLL_CNTL1_PLL_LOCKI            15
-#define NPCX_WOV_PLL_CNTL2_PLL_FBDV             FIELD(0, 12)
-#define NPCX_WOV_PLL_CNTL2_PLL_INDV             FIELD(12, 4)
-#define NPCX_WOV_I2S_CNTL_I2S_BCNT              FIELD(0, 5)
-#define NPCX_WOV_I2S_CNTL_I2S_TRIG              5
-#define NPCX_WOV_I2S_CNTL_I2S_LBHIZ             6
-#define NPCX_WOV_I2S_CNTL_I2S_ST_DEL            FIELD(7, 9)
-#define NPCX_WOV_I2S_CNTL_I2S_CHAN              FIELD(0, 16)
-#define NPCX_WOV_I2S_CNTL0_I2S_HIZD             16
-#define NPCX_WOV_I2S_CNTL0_I2S_HIZ              17
-#define NPCX_WOV_I2S_CNTL0_I2S_SCLK_INV         18
-#define NPCX_WOV_I2S_CNTL0_I2S_OPS              19
-#define NPCX_WOV_I2S_CNTL0_I2S_OPE              20
-#define NPCX_WOV_I2S_CNTL0_I2S_IPS              21
-#define NPCX_WOV_I2S_CNTL0_I2S_IPE              22
-#define NPCX_WOV_I2S_CNTL0_I2S_TST              23
-#define NPCX_WOV_I2S_CNTL1_I2S_CHN1_DIS         24
+#define NPCX_WOV_CLOCK_CNT_CLK_SEL 0
+#define NPCX_WOV_CLOCK_CNT_DMIC_EN 3
+#define NPCX_WOV_CLOCK_CNT_PLL_EDIV_SEL 7
+#define NPCX_WOV_CLOCK_CNT_PLL_EDIV FIELD(8, 7)
+#define NPCX_WOV_CLOCK_CNT_PLL_EDIV_DC FIELD(16, 7)
+#define NPCX_WOV_CLOCK_CNT_DMIC_CKDIV_EN 24
+#define NPCX_WOV_CLOCK_CNT_DMIC_CKDIV_SEL 25
+#define NPCX_WOV_FIFO_CNT_FIFO_ITHRSH FIELD(0, 6)
+#define NPCX_WOV_FIFO_CNT_FIFO_WTHRSH FIELD(6, 6)
+#define NPCX_WOV_FIFO_CNT_I2S_FFRST 13
+#define NPCX_WOV_FIFO_CNT_CORE_FFRST 14
+#define NPCX_WOV_FIFO_CNT_CFIFO_ISEL FIELD(16, 3)
+#define NPCX_WOV_STATUS_CFIFO_CNT FIELD(0, 8)
+#define NPCX_WOV_STATUS_CFIFO_NE 8
+#define NPCX_WOV_STATUS_CFIFO_OIT 9
+#define NPCX_WOV_STATUS_CFIFO_OWT 10
+#define NPCX_WOV_STATUS_CFIFO_OVRN 11
+#define NPCX_WOV_STATUS_I2S_FIFO_OVRN 12
+#define NPCX_WOV_STATUS_I2S_FIFO_UNDRN 13
+#define NPCX_WOV_STATUS_BITS FIELD(9, 6)
+#define NPCX_WOV_INTEN_VAD_INTEN 0
+#define NPCX_WOV_INTEN_VAD_WKEN 1
+#define NPCX_WOV_INTEN_CFIFO_NE_IE 8
+#define NPCX_WOV_INTEN_CFIFO_OIT_IE 9
+#define NPCX_WOV_INTEN_CFIFO_OWT_WE 10
+#define NPCX_WOV_INTEN_CFIFO_OVRN_IE 11
+#define NPCX_WOV_INTEN_I2S_FIFO_OVRN_IE 12
+#define NPCX_WOV_INTEN_I2S_FIFO_UNDRN_IE 13
+#define NPCX_WOV_APM_CTRL_APM_RST 0
+#define NPCX_WOV_PLL_CNTL1_PLL_PWDEN 0
+#define NPCX_WOV_PLL_CNTL1_PLL_OTDV1 FIELD(4, 4)
+#define NPCX_WOV_PLL_CNTL1_PLL_OTDV2 FIELD(8, 4)
+#define NPCX_WOV_PLL_CNTL1_PLL_LOCKI 15
+#define NPCX_WOV_PLL_CNTL2_PLL_FBDV FIELD(0, 12)
+#define NPCX_WOV_PLL_CNTL2_PLL_INDV FIELD(12, 4)
+#define NPCX_WOV_I2S_CNTL_I2S_BCNT FIELD(0, 5)
+#define NPCX_WOV_I2S_CNTL_I2S_TRIG 5
+#define NPCX_WOV_I2S_CNTL_I2S_LBHIZ 6
+#define NPCX_WOV_I2S_CNTL_I2S_ST_DEL FIELD(7, 9)
+#define NPCX_WOV_I2S_CNTL_I2S_CHAN FIELD(0, 16)
+#define NPCX_WOV_I2S_CNTL0_I2S_HIZD 16
+#define NPCX_WOV_I2S_CNTL0_I2S_HIZ 17
+#define NPCX_WOV_I2S_CNTL0_I2S_SCLK_INV 18
+#define NPCX_WOV_I2S_CNTL0_I2S_OPS 19
+#define NPCX_WOV_I2S_CNTL0_I2S_OPE 20
+#define NPCX_WOV_I2S_CNTL0_I2S_IPS 21
+#define NPCX_WOV_I2S_CNTL0_I2S_IPE 22
+#define NPCX_WOV_I2S_CNTL0_I2S_TST 23
+#define NPCX_WOV_I2S_CNTL1_I2S_CHN1_DIS 24
 
 /******************************************************************************/
 /* PS/2 registers */
-#define NPCX_PS2_PSDAT                   REG8(NPCX_PS2_BASE_ADDR + 0x000)
-#define NPCX_PS2_PSTAT                   REG8(NPCX_PS2_BASE_ADDR + 0x002)
-#define NPCX_PS2_PSCON                   REG8(NPCX_PS2_BASE_ADDR + 0x004)
-#define NPCX_PS2_PSOSIG                  REG8(NPCX_PS2_BASE_ADDR + 0x006)
-#define NPCX_PS2_PSISIG                  REG8(NPCX_PS2_BASE_ADDR + 0x008)
-#define NPCX_PS2_PSIEN                   REG8(NPCX_PS2_BASE_ADDR + 0x00A)
+#define NPCX_PS2_PSDAT REG8(NPCX_PS2_BASE_ADDR + 0x000)
+#define NPCX_PS2_PSTAT REG8(NPCX_PS2_BASE_ADDR + 0x002)
+#define NPCX_PS2_PSCON REG8(NPCX_PS2_BASE_ADDR + 0x004)
+#define NPCX_PS2_PSOSIG REG8(NPCX_PS2_BASE_ADDR + 0x006)
+#define NPCX_PS2_PSISIG REG8(NPCX_PS2_BASE_ADDR + 0x008)
+#define NPCX_PS2_PSIEN REG8(NPCX_PS2_BASE_ADDR + 0x00A)
 
 /* PS/2 register field */
-#define NPCX_PS2_PSTAT_SOT               0
-#define NPCX_PS2_PSTAT_EOT               1
-#define NPCX_PS2_PSTAT_PERR              2
-#define NPCX_PS2_PSTAT_ACH               FIELD(3, 3)
-#define NPCX_PS2_PSTAT_RFERR             6
-
-#define NPCX_PS2_PSCON_EN                0
-#define NPCX_PS2_PSCON_XMT               1
-#define NPCX_PS2_PSCON_HDRV              FIELD(2, 2)
-#define NPCX_PS2_PSCON_IDB               FIELD(4, 3)
-#define NPCX_PS2_PSCON_WPUED             7
-
-#define NPCX_PS2_PSOSIG_WDAT0            0
-#define NPCX_PS2_PSOSIG_WDAT1            1
-#define NPCX_PS2_PSOSIG_WDAT2            2
-#define NPCX_PS2_PSOSIG_CLK0             3
-#define NPCX_PS2_PSOSIG_CLK1             4
-#define NPCX_PS2_PSOSIG_CLK2             5
-#define NPCX_PS2_PSOSIG_WDAT3            6
-#define NPCX_PS2_PSOSIG_CLK3             7
-#define NPCX_PS2_PSOSIG_CLK(n)      (((n) < NPCX_PS2_CH3) ? \
-					((n) + 3) : 7)
-#define NPCX_PS2_PSOSIG_WDAT(n)     (((n) < NPCX_PS2_CH3) ? \
-					((n) + 0) : 6)
-#define NPCX_PS2_PSOSIG_CLK_MASK_ALL \
-					(BIT(NPCX_PS2_PSOSIG_CLK0) | \
-					 BIT(NPCX_PS2_PSOSIG_CLK1) | \
-					 BIT(NPCX_PS2_PSOSIG_CLK2) | \
-					 BIT(NPCX_PS2_PSOSIG_CLK3))
-
-#define NPCX_PS2_PSISIG_RDAT0            0
-#define NPCX_PS2_PSISIG_RDAT1            1
-#define NPCX_PS2_PSISIG_RDAT2            2
-#define NPCX_PS2_PSISIG_RCLK0            3
-#define NPCX_PS2_PSISIG_RCLK1            4
-#define NPCX_PS2_PSISIG_RCLK2            5
-#define NPCX_PS2_PSISIG_RDAT3            6
-#define NPCX_PS2_PSISIG_RCLK3            7
-#define NPCX_PS2_PSIEN_SOTIE             0
-#define NPCX_PS2_PSIEN_EOTIE             1
-#define NPCX_PS2_PSIEN_PS2_WUE           4
-#define NPCX_PS2_PSIEN_PS2_CLK_SEL	     7
+#define NPCX_PS2_PSTAT_SOT 0
+#define NPCX_PS2_PSTAT_EOT 1
+#define NPCX_PS2_PSTAT_PERR 2
+#define NPCX_PS2_PSTAT_ACH FIELD(3, 3)
+#define NPCX_PS2_PSTAT_RFERR 6
+
+#define NPCX_PS2_PSCON_EN 0
+#define NPCX_PS2_PSCON_XMT 1
+#define NPCX_PS2_PSCON_HDRV FIELD(2, 2)
+#define NPCX_PS2_PSCON_IDB FIELD(4, 3)
+#define NPCX_PS2_PSCON_WPUED 7
+
+#define NPCX_PS2_PSOSIG_WDAT0 0
+#define NPCX_PS2_PSOSIG_WDAT1 1
+#define NPCX_PS2_PSOSIG_WDAT2 2
+#define NPCX_PS2_PSOSIG_CLK0 3
+#define NPCX_PS2_PSOSIG_CLK1 4
+#define NPCX_PS2_PSOSIG_CLK2 5
+#define NPCX_PS2_PSOSIG_WDAT3 6
+#define NPCX_PS2_PSOSIG_CLK3 7
+#define NPCX_PS2_PSOSIG_CLK(n) (((n) < NPCX_PS2_CH3) ? ((n) + 3) : 7)
+#define NPCX_PS2_PSOSIG_WDAT(n) (((n) < NPCX_PS2_CH3) ? ((n) + 0) : 6)
+#define NPCX_PS2_PSOSIG_CLK_MASK_ALL                             \
+	(BIT(NPCX_PS2_PSOSIG_CLK0) | BIT(NPCX_PS2_PSOSIG_CLK1) | \
+	 BIT(NPCX_PS2_PSOSIG_CLK2) | BIT(NPCX_PS2_PSOSIG_CLK3))
+
+#define NPCX_PS2_PSISIG_RDAT0 0
+#define NPCX_PS2_PSISIG_RDAT1 1
+#define NPCX_PS2_PSISIG_RDAT2 2
+#define NPCX_PS2_PSISIG_RCLK0 3
+#define NPCX_PS2_PSISIG_RCLK1 4
+#define NPCX_PS2_PSISIG_RCLK2 5
+#define NPCX_PS2_PSISIG_RDAT3 6
+#define NPCX_PS2_PSISIG_RCLK3 7
+#define NPCX_PS2_PSIEN_SOTIE 0
+#define NPCX_PS2_PSIEN_EOTIE 1
+#define NPCX_PS2_PSIEN_PS2_WUE 4
+#define NPCX_PS2_PSIEN_PS2_CLK_SEL 7
 
 #ifndef CONFIG_HIBERNATE_WAKE_PINS_DYNAMIC
 extern const enum gpio_signal hibernate_wake_pins[];
@@ -1656,6 +1721,10 @@ extern enum gpio_signal hibernate_wake_pins[];
 extern int hibernate_wake_pins_used;
 #endif
 
+#ifndef NPCX_UART_MODULE2
+#define NPCX_UART_MODULE2 0
+#endif /* NPCX_UART_MODULE2 */
+
 #if defined(CHIP_FAMILY_NPCX5)
 #include "registers-npcx5.h"
 #elif defined(CHIP_FAMILY_NPCX7)
diff --git a/chip/npcx/rom_chip.h b/chip/npcx/rom_chip.h
index bb66f95e88..44c9c1a2a4 100644
--- a/chip/npcx/rom_chip.h
+++ b/chip/npcx/rom_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -42,25 +42,23 @@ enum API_RETURN_STATUS_T {
 /*
  * Macro functions of ROM api functions
  */
-#define ADDR_DOWNLOAD_FROM_FLASH (*(volatile uint32_t *) 0x40)
+#define ADDR_DOWNLOAD_FROM_FLASH (*(volatile uint32_t *)0x40)
 #define download_from_flash(src_offset, dest_addr, size, sign, exe_addr, \
-	status) \
-	(((download_from_flash_ptr) ADDR_DOWNLOAD_FROM_FLASH) \
-	(src_offset, dest_addr, size, sign, exe_addr, status))
+			    status)                                      \
+	(((download_from_flash_ptr)ADDR_DOWNLOAD_FROM_FLASH)(            \
+		src_offset, dest_addr, size, sign, exe_addr, status))
 
 /******************************************************************************/
 /*
  * Declarations of ROM api functions
  */
-typedef void (*download_from_flash_ptr) (
+typedef void (*download_from_flash_ptr)(
 	uint32_t src_offset, /* The offset of the data to be downloaded */
-	uint32_t dest_addr,  /* The address of the downloaded data in the RAM*/
-	uint32_t size,       /* Number of bytes to download */
+	uint32_t dest_addr, /* The address of the downloaded data in the RAM*/
+	uint32_t size, /* Number of bytes to download */
 	enum API_SIGN_OPTIONS_T sign, /* Need CRC check or not */
 	uint32_t exe_addr, /* jump to this address after download if not zero */
 	enum API_RETURN_STATUS_T *status /* Status fo download */
 );
 
-
-
 #endif /* __CROS_EC_ROM_CHIP_H_ */
diff --git a/chip/npcx/sha256_chip.c b/chip/npcx/sha256_chip.c
new file mode 100644
index 0000000000..0f64279c3b
--- /dev/null
+++ b/chip/npcx/sha256_chip.c
@@ -0,0 +1,143 @@
+/*
+ * Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* SHA256 module for Chrome EC */
+#include "builtin/assert.h"
+#include "common.h"
+#include "sha256.h"
+#include "util.h"
+
+enum ncl_status {
+	NCL_STATUS_OK = 0xA5A5,
+	NCL_STATUS_FAIL = 0x5A5A,
+	NCL_STATUS_INVALID_PARAM = 0x02,
+	NCL_STATUS_PARAM_NOT_SUPPORTED,
+	NCL_STATUS_SYSTEM_BUSY,
+	NCL_STATUS_AUTHENTICATION_FAIL,
+	NCL_STATUS_NO_RESPONSE,
+	NCL_STATUS_HARDWARE_ERROR,
+};
+
+enum ncl_sha_type {
+	NCL_SHA_TYPE_2_256 = 0,
+	NCL_SHA_TYPE_2_384 = 1,
+	NCL_SHA_TYPE_2_512 = 2,
+	NCL_SHA_TYPE_NUM
+};
+
+/*
+ * The base address of the table that holds the function pointer for each
+ * SHA256 API in ROM.
+ */
+#define NCL_SHA_BASE_ADDR 0x0000013CUL
+struct ncl_sha {
+	/* Get the SHA context size required by SHA APIs. */
+	uint32_t (*get_context_size)(void);
+	/* Initial SHA context. */
+	enum ncl_status (*init_context)(void *ctx);
+	/* Finalize SHA context. */
+	enum ncl_status (*finalize_context)(void *ctx);
+	/* Initiate the SHA hardware module and setups needed parameters. */
+	enum ncl_status (*init)(void *ctx);
+	/*
+	 * Prepare the context buffer for a SHA calculation -  by loading the
+	 * initial SHA-256/384/512 parameters.
+	 */
+	enum ncl_status (*start)(void *ctx, enum ncl_sha_type type);
+	/*
+	 * Updates the SHA calculation with the additional data. When the
+	 * function returns, the hardware and memory buffer shall be ready to
+	 * accept new data * buffers for SHA calculation and changes to the data
+	 * in data buffer should no longer effect the SHA calculation.
+	 */
+	enum ncl_status (*update)(void *ctx, const uint8_t *data, uint32_t Len);
+	/* Return the SHA result (digest.) */
+	enum ncl_status (*finish)(void *ctx, uint8_t *hashDigest);
+	/* Perform a complete SHA calculation */
+	enum ncl_status (*calc)(void *ctx, enum ncl_sha_type type,
+				const uint8_t *data, uint32_t Len,
+				uint8_t *hashDigest);
+	/* Power on/off the SHA module. */
+	enum ncl_status (*power)(void *ctx, uint8_t enable);
+	/* Reset the SHA hardware and terminate any in-progress operations. */
+	enum ncl_status (*reset)(void *ctx);
+};
+
+#define NCL_SHA ((const struct ncl_sha *)NCL_SHA_BASE_ADDR)
+
+void SHA256_init(struct sha256_ctx *ctx)
+{
+	NCL_SHA->init_context(ctx->handle);
+	NCL_SHA->power(ctx->handle, 1);
+	NCL_SHA->init(ctx->handle);
+	NCL_SHA->reset(ctx->handle);
+	NCL_SHA->start(ctx->handle, NCL_SHA_TYPE_2_256);
+}
+
+void SHA256_update(struct sha256_ctx *ctx, const uint8_t *data, uint32_t len)
+{
+	NCL_SHA->update(ctx->handle, data, len);
+}
+
+void SHA256_abort(struct sha256_ctx *ctx)
+{
+	NCL_SHA->reset(ctx->handle);
+	NCL_SHA->power(ctx->handle, 0);
+	NCL_SHA->finalize_context(ctx->handle);
+}
+
+uint8_t *SHA256_final(struct sha256_ctx *ctx)
+{
+	NCL_SHA->finish(ctx->handle, ctx->buf);
+	NCL_SHA->power(ctx->handle, 0);
+	NCL_SHA->finalize_context(ctx->handle);
+	return ctx->buf;
+}
+
+static void hmac_SHA256_step(uint8_t *output, uint8_t mask, const uint8_t *key,
+			     const int key_len, const uint8_t *data,
+			     const int data_len)
+{
+	struct sha256_ctx hmac_ctx;
+	uint8_t *key_pad = hmac_ctx.buf;
+	uint8_t *tmp;
+	int i;
+
+	memset(key_pad, mask, SHA256_BLOCK_SIZE);
+	for (i = 0; i < key_len; i++)
+		key_pad[i] ^= key[i];
+
+	SHA256_init(&hmac_ctx);
+	SHA256_update(&hmac_ctx, key_pad, SHA256_BLOCK_SIZE);
+	SHA256_update(&hmac_ctx, data, data_len);
+	tmp = SHA256_final(&hmac_ctx);
+	memcpy(output, tmp, SHA256_DIGEST_SIZE);
+}
+/*
+ * Note: When the API is called, it will consume about half of TASK_STACK_SIZE
+ * because a variable of structure sha256_ctx is declared in the function
+ * hmac_SHA256_step.
+ */
+void hmac_SHA256(uint8_t *output, const uint8_t *key, const int key_len,
+		 const uint8_t *message, const int message_len)
+{
+	/* This code does not support key_len > block_size. */
+	ASSERT(key_len <= SHA256_BLOCK_SIZE);
+
+	/*
+	 * i_key_pad = key (zero-padded) ^ 0x36
+	 * output = hash(i_key_pad || message)
+	 * (Use output as temporary buffer)
+	 */
+	hmac_SHA256_step(output, 0x36, key, key_len, message, message_len);
+
+	/*
+	 * o_key_pad = key (zero-padded) ^ 0x5c
+	 * output = hash(o_key_pad || output)
+	 */
+	hmac_SHA256_step(output, 0x5c, key, key_len, output,
+			 SHA256_DIGEST_SIZE);
+}
diff --git a/chip/npcx/sha256_chip.h b/chip/npcx/sha256_chip.h
new file mode 100644
index 0000000000..3c7773d112
--- /dev/null
+++ b/chip/npcx/sha256_chip.h
@@ -0,0 +1,25 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_SHA256_CHIP_H
+#define __CROS_EC_SHA256_CHIP_H
+
+#include "common.h"
+
+#define NPCX_SHA256_HANDLE_SIZE 212
+struct sha256_ctx {
+	/* the context handle required for SHA256 API */
+	uint8_t handle[NPCX_SHA256_HANDLE_SIZE];
+	/*
+	 * This is used to buffer:
+	 *   1. the result (digest) of the SHA256 computation.
+	 *   2. the 1st block input data (the key padding) for hmac_SHA256_step.
+	 */
+	uint8_t buf[SHA256_BLOCK_SIZE];
+} __aligned(4);
+
+void SHA256_abort(struct sha256_ctx *ctx);
+
+#endif /* __CROS_EC_SHA256_CHIP_H */
diff --git a/chip/npcx/shi.c b/chip/npcx/shi.c
index bb2696acae..dde2243462 100644
--- a/chip/npcx/shi.c
+++ b/chip/npcx/shi.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,22 +10,23 @@
  * This uses Input/Output buffer to handle SPI transmission and reception.
  */
 
+#include "builtin/assert.h"
 #include "chipset.h"
 #include "clock.h"
 #include "console.h"
 #include "gpio.h"
-#include "task.h"
 #include "hooks.h"
 #include "host_command.h"
 #include "registers.h"
 #include "spi.h"
 #include "system.h"
+#include "task.h"
 #include "timer.h"
 #include "util.h"
 
 #define CPUTS(outstr) cputs(CC_SPI, outstr)
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SPI, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SPI, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SPI, format, ##args)
 
 #if !(DEBUG_SHI)
 #define DEBUG_CPUTS(...)
@@ -33,48 +34,51 @@
 #define DEBUG_CPRINTF(...)
 #else
 #define DEBUG_CPUTS(outstr) cputs(CC_SPI, outstr)
-#define DEBUG_CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
-#define DEBUG_CPRINTF(format, args...) cprintf(CC_SPI, format, ## args)
+#define DEBUG_CPRINTS(format, args...) cprints(CC_SPI, format, ##args)
+#define DEBUG_CPRINTF(format, args...) cprintf(CC_SPI, format, ##args)
 #endif
 
 /* SHI Bus definition */
 #ifdef NPCX_SHI_V2
-#define SHI_OBUF_FULL_SIZE  128                    /* Full output buffer size */
-#define SHI_IBUF_FULL_SIZE  128                    /* Full input buffer size  */
+#define SHI_OBUF_FULL_SIZE 128 /* Full output buffer size */
+#define SHI_IBUF_FULL_SIZE 128 /* Full input buffer size  */
 /* Configure the IBUFLVL2 = the size of V3 protocol header */
 #define SHI_IBUFLVL2_THRESHOLD (sizeof(struct ec_host_request))
 #else
-#define SHI_OBUF_FULL_SIZE  64                     /* Full output buffer size */
-#define SHI_IBUF_FULL_SIZE  64                     /* Full input buffer size  */
+#define SHI_OBUF_FULL_SIZE 64 /* Full output buffer size */
+#define SHI_IBUF_FULL_SIZE 64 /* Full input buffer size  */
 #endif
-#define SHI_OBUF_HALF_SIZE  (SHI_OBUF_FULL_SIZE/2) /* Half output buffer size */
-#define SHI_IBUF_HALF_SIZE  (SHI_IBUF_FULL_SIZE/2) /* Half input buffer size  */
+#define SHI_OBUF_HALF_SIZE \
+	(SHI_OBUF_FULL_SIZE / 2) /* Half output buffer size */
+#define SHI_IBUF_HALF_SIZE \
+	(SHI_IBUF_FULL_SIZE / 2) /* Half input buffer size  */
 
 /* Start address of SHI output buffer */
-#define SHI_OBUF_START_ADDR  (volatile uint8_t  *)(NPCX_SHI_BASE_ADDR + 0x020)
+#define SHI_OBUF_START_ADDR (volatile uint8_t *)(NPCX_SHI_BASE_ADDR + 0x020)
 /* Middle address of SHI output buffer */
-#define SHI_OBUF_HALF_ADDR   (SHI_OBUF_START_ADDR + SHI_OBUF_HALF_SIZE)
+#define SHI_OBUF_HALF_ADDR (SHI_OBUF_START_ADDR + SHI_OBUF_HALF_SIZE)
 /* Top address of SHI output buffer */
-#define SHI_OBUF_FULL_ADDR   (SHI_OBUF_START_ADDR + SHI_IBUF_FULL_SIZE)
+#define SHI_OBUF_FULL_ADDR (SHI_OBUF_START_ADDR + SHI_IBUF_FULL_SIZE)
 /*
  * Valid offset of SHI output buffer to write.
  * When SIMUL bit is set, IBUFPTR can be used instead of OBUFPTR
  */
-#define SHI_OBUF_VALID_OFFSET ((shi_read_buf_pointer() + \
-			SHI_OUT_PREAMBLE_LENGTH) % SHI_OBUF_FULL_SIZE)
+#define SHI_OBUF_VALID_OFFSET                                 \
+	((shi_read_buf_pointer() + SHI_OUT_PREAMBLE_LENGTH) % \
+	 SHI_OBUF_FULL_SIZE)
 /* Start address of SHI input buffer */
-#define SHI_IBUF_START_ADDR  (&NPCX_IBUF(0))
+#define SHI_IBUF_START_ADDR (&NPCX_IBUF(0))
 /* Current address of SHI input buffer */
-#define SHI_IBUF_CUR_ADDR    (SHI_IBUF_START_ADDR + shi_read_buf_pointer())
+#define SHI_IBUF_CUR_ADDR (SHI_IBUF_START_ADDR + shi_read_buf_pointer())
 
 /*
  * Timeout to wait for SHI request packet
  *
- * This affects the slowest SPI clock we can support.  A delay of 8192 us
- * permits a 512-byte request at 500 KHz, assuming the master starts sending
- * bytes as soon as it asserts chip select.  That's as slow as we would
- * practically want to run the SHI interface, since running it slower
- * significantly impacts firmware update times.
+ * This affects the slowest SPI clock we can support.  A delay of 8192
+ * us permits a 512-byte request at 500 KHz, assuming the controller
+ * starts sending bytes as soon as it asserts chip select.  That's as
+ * slow as we would practically want to run the SHI interface, since
+ * running it slower significantly impacts firmware update times.
  */
 #define SHI_CMD_RX_TIMEOUT_US 8192
 
@@ -106,12 +110,11 @@
  */
 #define SHI_PROTO3_OVERHEAD (EC_SPI_PAST_END_LENGTH + EC_SPI_FRAME_START_LENGTH)
 
-
 #ifdef NPCX_SHI_BYPASS_OVER_256B
 /* The boundary which SHI will output invalid data on MISO. */
 #define SHI_BYPASS_BOUNDARY 256
 /* Increase FRAME_START_LENGTH in case shi outputs invalid FRAME_START byte */
-#undef  EC_SPI_FRAME_START_LENGTH
+#undef EC_SPI_FRAME_START_LENGTH
 #define EC_SPI_FRAME_START_LENGTH 2
 #endif
 
@@ -141,10 +144,9 @@ BUILD_ASSERT(SHI_MAX_RESPONSE_SIZE <= SHI_BYPASS_BOUNDARY);
  */
 #define SHI_OUT_START_PAD (4 * (EC_SPI_FRAME_START_LENGTH / 4 + 1))
 #define SHI_OUT_END_PAD (4 * (EC_SPI_PAST_END_LENGTH / 4 + 1))
-static uint8_t out_msg_padded[SHI_OUT_START_PAD +
-			      SHI_MAX_RESPONSE_SIZE +
+static uint8_t out_msg_padded[SHI_OUT_START_PAD + SHI_MAX_RESPONSE_SIZE +
 			      SHI_OUT_END_PAD] __aligned(4);
-static uint8_t * const out_msg =
+static uint8_t *const out_msg =
 	out_msg_padded + SHI_OUT_START_PAD - EC_SPI_FRAME_START_LENGTH;
 static uint8_t in_msg[SHI_MAX_REQUEST_SIZE] __aligned(4);
 
@@ -176,18 +178,18 @@ volatile enum shi_state state;
 
 /* SHI bus parameters */
 struct shi_bus_parameters {
-	uint8_t *rx_msg;          /* Entry pointer of msg rx buffer   */
-	uint8_t *tx_msg;          /* Entry pointer of msg tx buffer   */
+	uint8_t *rx_msg; /* Entry pointer of msg rx buffer   */
+	uint8_t *tx_msg; /* Entry pointer of msg tx buffer   */
 	volatile uint8_t *rx_buf; /* Entry pointer of receive buffer  */
 	volatile uint8_t *tx_buf; /* Entry pointer of transmit buffer */
-	uint16_t sz_received;     /* Size of received data in bytes   */
-	uint16_t sz_sending;      /* Size of sending data in bytes    */
-	uint16_t sz_request;      /* request bytes need to receive    */
-	uint16_t sz_response;     /* response bytes need to receive   */
-	timestamp_t rx_deadline;  /* deadline of receiving            */
-	uint8_t  pre_ibufstat;    /* Previous IBUFSTAT value          */
+	uint16_t sz_received; /* Size of received data in bytes   */
+	uint16_t sz_sending; /* Size of sending data in bytes    */
+	uint16_t sz_request; /* request bytes need to receive    */
+	uint16_t sz_response; /* response bytes need to receive   */
+	timestamp_t rx_deadline; /* deadline of receiving            */
+	uint8_t pre_ibufstat; /* Previous IBUFSTAT value          */
 #ifdef NPCX_SHI_BYPASS_OVER_256B
-	uint16_t bytes_in_256b;   /* Sent bytes in 256 bytes boundary */
+	uint16_t bytes_in_256b; /* Sent bytes in 256 bytes boundary */
 #endif
 } shi_params;
 
@@ -222,7 +224,7 @@ static void shi_send_response_packet(struct host_packet *pkt)
 	interrupt_disable();
 	if (state == SHI_STATE_PROCESSING) {
 		/* Append our past-end byte, which we reserved space for. */
-		((uint8_t *) pkt->response)[pkt->response_size + 0] =
+		((uint8_t *)pkt->response)[pkt->response_size + 0] =
 			EC_SPI_PAST_END;
 
 		/* Computing sending bytes of response */
@@ -266,8 +268,8 @@ void shi_handle_host_package(void)
 		/* Need to receive data from buffer */
 		return;
 	else {
-		uint16_t remain_bytes = shi_params.sz_request
-					- shi_params.sz_received;
+		uint16_t remain_bytes =
+			shi_params.sz_request - shi_params.sz_received;
 
 		/* Read remaining bytes from input buffer directly */
 		if (!shi_read_inbuf_wait(remain_bytes))
@@ -287,7 +289,6 @@ void shi_handle_host_package(void)
 	shi_packet.request_max = sizeof(in_msg);
 	shi_packet.request_size = shi_params.sz_request;
 
-
 #ifdef NPCX_SHI_BYPASS_OVER_256B
 	/* Move FRAME_START to second byte */
 	out_msg[0] = EC_SPI_PROCESSING;
@@ -324,7 +325,7 @@ static void shi_parse_header(void)
 
 	if (in_msg[0] == EC_HOST_REQUEST_VERSION) {
 		/* Protocol version 3 */
-		struct ec_host_request *r = (struct ec_host_request *) in_msg;
+		struct ec_host_request *r = (struct ec_host_request *)in_msg;
 		int pkt_size;
 		/*
 		 * If request is over 32 bytes,
@@ -357,42 +358,48 @@ static void shi_parse_header(void)
 /* This routine fills out all SHI output buffer with status byte */
 static void shi_fill_out_status(uint8_t status)
 {
-	uint8_t offset;
-	uint8_t *obuf_ptr;
+	uint8_t start, end;
+	uint8_t *fill_ptr;
+	uint8_t *fill_end;
 	uint8_t *obuf_end;
 
 	/* Disable interrupts in case the interfere by the other interrupts */
 	interrupt_disable();
 
-	offset = SHI_OBUF_VALID_OFFSET;
+	/*
+	 * Fill out output buffer with status byte and leave a gap for PREAMBLE.
+	 * The gap guarantees the synchronization. The critical section should
+	 * be done within this gap. No racing happens.
+	 */
+	start = SHI_OBUF_VALID_OFFSET;
+	end = ((start + SHI_OBUF_FULL_SIZE - SHI_OUT_PREAMBLE_LENGTH) %
+	       SHI_OBUF_FULL_SIZE);
 
-	/* Fill out all output buffer with status byte */
-	obuf_ptr = (uint8_t *)SHI_OBUF_START_ADDR + offset;
+	fill_ptr = (uint8_t *)SHI_OBUF_START_ADDR + start;
+	fill_end = (uint8_t *)SHI_OBUF_START_ADDR + end;
 	obuf_end = (uint8_t *)SHI_OBUF_START_ADDR + SHI_OBUF_FULL_SIZE;
-	while (obuf_ptr != obuf_end)
-		*(obuf_ptr++) = status;
-
-	obuf_ptr = (uint8_t *)SHI_OBUF_START_ADDR;
-	obuf_end = (uint8_t *)SHI_OBUF_START_ADDR + offset;
-	while (obuf_ptr != obuf_end)
-		*(obuf_ptr++) = status;
+	while (fill_ptr != fill_end) {
+		*(fill_ptr++) = status;
+		if (fill_ptr == obuf_end)
+			fill_ptr = (uint8_t *)SHI_OBUF_START_ADDR;
+	}
 
 	/* End of critical section */
 	interrupt_enable();
 }
 
 #ifdef NPCX_SHI_V2
- /*
-  * This routine configures at which level the Input Buffer Half Full 2(IBHF2))
-  * event triggers an interrupt to core.
-  */
+/*
+ * This routine configures at which level the Input Buffer Half Full 2(IBHF2))
+ * event triggers an interrupt to core.
+ */
 static void shi_sec_ibf_int_enable(int enable)
 {
 	if (enable) {
 		/* Setup IBUFLVL2 threshold and enable it */
 		SET_BIT(NPCX_SHICFG5, NPCX_SHICFG5_IBUFLVL2DIS);
 		SET_FIELD(NPCX_SHICFG5, NPCX_SHICFG5_IBUFLVL2,
-				SHI_IBUFLVL2_THRESHOLD);
+			  SHI_IBUFLVL2_THRESHOLD);
 		CLEAR_BIT(NPCX_SHICFG5, NPCX_SHICFG5_IBUFLVL2DIS);
 		/* Enable IBHF2 event */
 		SET_BIT(NPCX_EVENABLE2, NPCX_EVENABLE2_IBHF2EN);
@@ -430,9 +437,9 @@ static int shi_is_cs_glitch(void)
  */
 static void shi_write_half_outbuf(void)
 {
-	const uint8_t size = MIN(SHI_OBUF_HALF_SIZE,
-				 shi_params.sz_response -
-				 shi_params.sz_sending);
+	const uint8_t size =
+		MIN(SHI_OBUF_HALF_SIZE,
+		    shi_params.sz_response - shi_params.sz_sending);
 	uint8_t *obuf_ptr = (uint8_t *)shi_params.tx_buf;
 	const uint8_t *obuf_end = obuf_ptr + size;
 	uint8_t *msg_ptr = shi_params.tx_msg;
@@ -462,8 +469,8 @@ static void shi_write_first_pkg_outbuf(uint16_t szbytes)
 	 * If response package is across 256 bytes boundary,
 	 * bypass needs to extend PROCESSING bytes after reaching the boundary.
 	 */
-	if (shi_params.bytes_in_256b + SHI_OBUF_FULL_SIZE + szbytes
-	    > SHI_BYPASS_BOUNDARY) {
+	if (shi_params.bytes_in_256b + SHI_OBUF_FULL_SIZE + szbytes >
+	    SHI_BYPASS_BOUNDARY) {
 		state = SHI_STATE_WAIT_ALIGNMENT;
 		/* Set pointer of output buffer to the start address */
 		shi_params.tx_buf = SHI_OBUF_START_ADDR;
@@ -479,7 +486,7 @@ static void shi_write_first_pkg_outbuf(uint16_t szbytes)
 
 	/* Fill up to OBUF mid point, or OBUF end */
 	size = MIN(SHI_OBUF_HALF_SIZE - (offset % SHI_OBUF_HALF_SIZE),
-					szbytes - shi_params.sz_sending);
+		   szbytes - shi_params.sz_sending);
 	obuf_end = obuf_ptr + size;
 	while (obuf_ptr != obuf_end)
 		*(obuf_ptr++) = *(msg_ptr++);
@@ -514,8 +521,8 @@ static void shi_read_half_inbuf(void)
 		/* Restore data to msg buffer */
 		*(shi_params.rx_msg++) = *(shi_params.rx_buf++);
 		shi_params.sz_received++;
-	} while (shi_params.sz_received % SHI_IBUF_HALF_SIZE
-		&& shi_params.sz_received != shi_params.sz_request);
+	} while (shi_params.sz_received % SHI_IBUF_HALF_SIZE &&
+		 shi_params.sz_received != shi_params.sz_request);
 }
 
 /*
@@ -595,7 +602,7 @@ static void shi_handle_cs_assert(void)
 	if (state == SHI_STATE_DISABLED)
 		return;
 
-	/* SHI V2 module filters cs glitch by hardware automatically */
+		/* SHI V2 module filters cs glitch by hardware automatically */
 #ifndef NPCX_SHI_V2
 	/*
 	 * IBUFSTAT resets on the 7th clock cycle after CS assertion, which
@@ -645,7 +652,7 @@ static void shi_handle_cs_assert(void)
 }
 
 /* This routine handles all interrupts of this module */
-void shi_int_handler(void)
+static void shi_int_handler(void)
 {
 	uint8_t stat_reg;
 #ifdef NPCX_SHI_V2
@@ -719,7 +726,7 @@ void shi_int_handler(void)
 
 			DEBUG_CPRINTF("CNL-");
 			return;
-		/* Next transaction but we're not ready */
+			/* Next transaction but we're not ready */
 		} else if (state == SHI_STATE_CNL_RESP_NOT_RDY)
 			return;
 
@@ -748,8 +755,8 @@ void shi_int_handler(void)
 			return shi_handle_host_package();
 		} else if (state == SHI_STATE_SENDING) {
 			/* Write data from msg buffer to output buffer */
-			if (shi_params.tx_buf == SHI_OBUF_START_ADDR +
-					SHI_OBUF_FULL_SIZE) {
+			if (shi_params.tx_buf ==
+			    SHI_OBUF_START_ADDR + SHI_OBUF_FULL_SIZE) {
 				/* Write data from bottom address again */
 				shi_params.tx_buf = SHI_OBUF_START_ADDR;
 				return shi_write_half_outbuf();
@@ -764,8 +771,8 @@ void shi_int_handler(void)
 			 * If pointer of output buffer will reach 256 bytes
 			 * boundary soon, start to fill response data.
 			 */
-			if (shi_params.bytes_in_256b == SHI_BYPASS_BOUNDARY -
-					SHI_OBUF_FULL_SIZE) {
+			if (shi_params.bytes_in_256b ==
+			    SHI_BYPASS_BOUNDARY - SHI_OBUF_FULL_SIZE) {
 				state = SHI_STATE_SENDING;
 				DEBUG_CPRINTF("SND-");
 				return shi_write_half_outbuf();
@@ -799,8 +806,9 @@ void shi_int_handler(void)
 	if (IS_BIT_SET(stat_reg, NPCX_EVSTAT_IBF)) {
 #ifdef NPCX_SHI_BYPASS_OVER_256B
 		/* Record the sent bytes within 256B boundary */
-		shi_params.bytes_in_256b = (shi_params.bytes_in_256b +
-				SHI_OBUF_FULL_SIZE) % SHI_BYPASS_BOUNDARY;
+		shi_params.bytes_in_256b =
+			(shi_params.bytes_in_256b + SHI_OBUF_FULL_SIZE) %
+			SHI_BYPASS_BOUNDARY;
 #endif
 		if (state == SHI_STATE_RECEIVING) {
 			/* read data from input to msg buffer */
@@ -810,16 +818,16 @@ void shi_int_handler(void)
 			return shi_handle_host_package();
 		} else if (state == SHI_STATE_SENDING)
 			/* Write data from msg buffer to output buffer */
-			if (shi_params.tx_buf == SHI_OBUF_START_ADDR +
-					SHI_OBUF_HALF_SIZE)
+			if (shi_params.tx_buf ==
+			    SHI_OBUF_START_ADDR + SHI_OBUF_HALF_SIZE)
 				return shi_write_half_outbuf();
 			else /* ignore it */
 				return;
 		else if (state == SHI_STATE_PROCESSING
 #ifdef NPCX_SHI_BYPASS_OVER_256B
-				|| state == SHI_STATE_WAIT_ALIGNMENT
+			 || state == SHI_STATE_WAIT_ALIGNMENT
 #endif
-				)
+		)
 			/* Wait for host handles request */
 			return;
 		else
@@ -844,7 +852,6 @@ void shi_cs_event(enum gpio_signal signal)
 #else
 	shi_handle_cs_assert();
 #endif
-
 }
 
 /*****************************************************************************/
@@ -885,7 +892,7 @@ static void shi_reset_prepare(void)
 	 */
 	for (i = 1; i < SHI_OBUF_FULL_SIZE; i++)
 		NPCX_OBUF(i) = EC_SPI_RECEIVING;
-	NPCX_OBUF(0) = EC_SPI_OLD_READY;
+	NPCX_OBUF(0) = EC_SPI_RX_READY;
 
 	/* Enable SHI & WEN functionality */
 	NPCX_SHICFG1 = 0x85;
@@ -954,9 +961,7 @@ static void shi_reenable_on_sysjump(void)
 		shi_enable();
 }
 /* Call hook after chipset sets initial power state */
-DECLARE_HOOK(HOOK_INIT,
-	     shi_reenable_on_sysjump,
-	     HOOK_PRIO_INIT_CHIPSET + 1);
+DECLARE_HOOK(HOOK_INIT, shi_reenable_on_sysjump, HOOK_PRIO_POST_CHIPSET);
 
 /* Disable SHI bus */
 static void shi_disable(void)
@@ -1070,7 +1075,7 @@ static enum ec_status shi_get_protocol_info(struct host_cmd_handler_args *args)
 
 	args->response_size = sizeof(*r);
 
-	return EC_SUCCESS;
+	return EC_RES_SUCCESS;
 }
 DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, shi_get_protocol_info,
-EC_VER_MASK(0));
+		     EC_VER_MASK(0));
diff --git a/chip/npcx/shi_chip.h b/chip/npcx/shi_chip.h
index f701067715..9d41a2dcab 100644
--- a/chip/npcx/shi_chip.h
+++ b/chip/npcx/shi_chip.h
@@ -1,14 +1,13 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* NPCX-specific SHI module for Chrome EC */
 
-#ifndef SHI_CHIP_H_
-#define SHI_CHIP_H_
+#ifndef __CROS_EC_SHI_CHIP_H_
+#define __CROS_EC_SHI_CHIP_H_
 
-#ifdef CONFIG_HOSTCMD_SPS
 /**
  * Called when the NSS level changes, signalling the start of a SHI
  * transaction.
@@ -19,6 +18,5 @@ void shi_cs_event(enum gpio_signal signal);
 #ifdef NPCX_SHI_V2
 void shi_cs_gpio_int(enum gpio_signal signal);
 #endif
-#endif
 
-#endif /* SHI_CHIP_H_ */
+#endif /* __CROS_EC_SHI_CHIP_H_ */
diff --git a/chip/npcx/sib.c b/chip/npcx/sib.c
index b8e2e17955..e8dbd5039d 100644
--- a/chip/npcx/sib.c
+++ b/chip/npcx/sib.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,7 +19,7 @@
  * For eSPI - it is 200 us.
  * For LPC - it is 5 us.
  */
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 #define HOST_TRANSACTION_TIMEOUT_US 200
 #else
 #define HOST_TRANSACTION_TIMEOUT_US 5
@@ -28,7 +28,7 @@
 /* Console output macros */
 #ifdef DEBUG_SIB
 #define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 #else
 #define CPUTS(...)
 #define CPRINTS(...)
@@ -110,8 +110,7 @@ uint8_t sib_read_kbc_reg(uint8_t io_offset)
 }
 
 /* Super-IO read/write function */
-void sib_write_reg(uint8_t io_offset, uint8_t index_value,
-		uint8_t io_data)
+void sib_write_reg(uint8_t io_offset, uint8_t index_value, uint8_t io_data)
 {
 	/* Disable interrupts */
 	interrupt_disable();
@@ -132,7 +131,7 @@ void sib_write_reg(uint8_t io_offset, uint8_t index_value,
 	sib_wait_host_write_done();
 
 	/* Specify the io_offset A0 = 1. the data register is accessed */
-	NPCX_IHIOA = io_offset+1;
+	NPCX_IHIOA = io_offset + 1;
 	/* Write the data. This starts the write access to the host module */
 	NPCX_IHD = io_data;
 	/* Wait while Core write operation is in progress */
@@ -170,7 +169,7 @@ uint8_t sib_read_reg(uint8_t io_offset, uint8_t index_value)
 	sib_wait_host_write_done();
 
 	/* Specify the io_offset A0 = 1. the data register is accessed */
-	NPCX_IHIOA = io_offset+1;
+	NPCX_IHIOA = io_offset + 1;
 	/* Start a Core read from host module */
 	SET_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSRD);
 	/* Wait while Core read operation is in progress */
@@ -188,4 +187,3 @@ uint8_t sib_read_reg(uint8_t io_offset, uint8_t index_value)
 
 	return data_value;
 }
-
diff --git a/chip/npcx/sib_chip.h b/chip/npcx/sib_chip.h
index 2341f219b4..570fe6b0ec 100644
--- a/chip/npcx/sib_chip.h
+++ b/chip/npcx/sib_chip.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,17 +7,15 @@
 /* NPCX-specific SIB module for Chrome EC */
 
 /* Super-IO index and register definitions */
-#define INDEX_SID       0x20
-#define INDEX_CHPREV    0x24
-#define INDEX_SRID      0x27
+#define INDEX_SID 0x20
+#define INDEX_CHPREV 0x24
+#define INDEX_SRID 0x27
 
-#define SIO_OFFSET      0x4E
+#define SIO_OFFSET 0x4E
 
 /* Super-IO register write function */
-void sib_write_reg(uint8_t io_offset, uint8_t index_value,
-		uint8_t io_data);
+void sib_write_reg(uint8_t io_offset, uint8_t index_value, uint8_t io_data);
 /* Super-IO register read function */
 uint8_t sib_read_reg(uint8_t io_offset, uint8_t index_value);
 /* Emulate host to read Keyboard I/O */
 uint8_t sib_read_kbc_reg(uint8_t io_offset);
-
diff --git a/chip/npcx/spi.c b/chip/npcx/spi.c
index 6ac8fe1b9e..f33dfae028 100644
--- a/chip/npcx/spi.c
+++ b/chip/npcx/spi.c
@@ -1,15 +1,15 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* SPI module for Chrome EC */
 
+#include "clock.h"
+#include "clock_chip.h"
 #include "console.h"
 #include "gpio.h"
 #include "hooks.h"
-#include "clock.h"
-#include "clock_chip.h"
 #include "registers.h"
 #include "spi.h"
 #include "task.h"
@@ -22,11 +22,14 @@
 #define CPRINTS(...)
 #else
 #define CPUTS(outstr) cputs(CC_SPI, outstr)
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SPI, format, ##args)
 #endif
 
-/* SPI IP as SPI master */
-#define SPI_CLK         8000000
+/* SPI IP as SPI controller */
+#define SPI_CLK 8000000
+
+static struct mutex spi_lock;
+
 /**
  * Clear SPI data buffer.
  *
@@ -49,32 +52,32 @@ static void clear_databuf(void)
  */
 void spi_freq_changed(void)
 {
-	uint8_t prescaler_divider    = 0;
+	uint8_t prescaler_divider = 0;
 
 	/* Set clock prescaler divider to SPI module*/
-	prescaler_divider = (uint8_t)((uint32_t)clock_get_apb2_freq()
-			/ 2 / SPI_CLK);
+	prescaler_divider =
+		(uint8_t)((uint32_t)clock_get_apb2_freq() / 2 / SPI_CLK);
 	if (prescaler_divider >= 1)
 		prescaler_divider = prescaler_divider - 1;
 	if (prescaler_divider > 0x7F)
 		prescaler_divider = 0x7F;
 
 	/* Set core clock division factor in order to obtain the SPI clock */
-	NPCX_SPI_CTL1 = (NPCX_SPI_CTL1&(~(((1<<7)-1)<<NPCX_SPI_CTL1_SCDV)))
-			|(prescaler_divider<<NPCX_SPI_CTL1_SCDV);
+	NPCX_SPI_CTL1 =
+		(NPCX_SPI_CTL1 & (~(((1 << 7) - 1) << NPCX_SPI_CTL1_SCDV))) |
+		(prescaler_divider << NPCX_SPI_CTL1_SCDV);
 }
 DECLARE_HOOK(HOOK_FREQ_CHANGE, spi_freq_changed, HOOK_PRIO_FIRST);
 
 /**
  * Set SPI enabled.
  *
- * @spi_port port to act on. Only one port supported, one gpio.
+ * @spi_device SPI device to act on.
  * @param   enable enabled flag
  * @return  success
  */
-int spi_enable(int port, int enable)
+int spi_enable(const struct spi_device_t *spi_device, int enable)
 {
-	int i;
 	enum gpio_signal gpio;
 
 	if (enable) {
@@ -83,28 +86,21 @@ int spi_enable(int port, int enable)
 		/* GPIO No SPI Select */
 		CLEAR_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_GPIO_NO_SPIP);
 
-		for (i = 0; i < spi_devices_used; i++) {
-			if (spi_devices[i].port != port)
-				continue;
-			gpio = spi_devices[i].gpio_cs;
-			/* Make sure CS# is a GPIO output mode. */
-			gpio_set_flags(gpio, GPIO_OUTPUT);
-			/* Make sure CS# is deselected */
-			gpio_set_level(gpio, 1);
-		}
+		gpio = spi_device->gpio_cs;
+		/* Make sure CS# is in GPIO output mode. */
+		gpio_set_flags(gpio, GPIO_OUTPUT);
+		/* Make sure CS# is deselected */
+		gpio_set_level(gpio, 1);
+
 		/* Enabling spi module */
 		SET_BIT(NPCX_SPI_CTL1, NPCX_SPI_CTL1_SPIEN);
 	} else {
 		/* Disabling spi module */
 		CLEAR_BIT(NPCX_SPI_CTL1, NPCX_SPI_CTL1_SPIEN);
-		for (i = 0; i < spi_devices_used; i++) {
-			if (spi_devices[i].port != port)
-				continue;
-			gpio = spi_devices[i].gpio_cs;
-			/* Make sure CS# is deselected */
-			gpio_set_level(gpio, 1);
-			gpio_set_flags(gpio, GPIO_ODR_HIGH);
-		}
+		gpio = spi_device->gpio_cs;
+		/* Make sure CS# is deselected */
+		gpio_set_level(gpio, 1);
+		gpio_set_flags(gpio, GPIO_ODR_HIGH);
 		/* Disabling spi module for gpio configuration */
 		gpio_config_module(MODULE_SPI, 0);
 		/* GPIO No SPI Select */
@@ -113,31 +109,13 @@ int spi_enable(int port, int enable)
 	return EC_SUCCESS;
 }
 
-
-/**
- * Flush an SPI transaction and receive data from slave.
- *
- * @param   spi_device  device to talk to
- * @param   txdata  transfer data
- * @param   txlen   transfer length
- * @param   rxdata  receive data
- * @param   rxlen   receive length
- * @return  success
- * @notes   set master transaction mode in npcx chip
- */
-int spi_transaction(const struct spi_device_t *spi_device,
-		const uint8_t *txdata, int txlen,
-		uint8_t *rxdata, int rxlen)
+int spi_transaction_async(const struct spi_device_t *spi_device,
+			  const uint8_t *txdata, int txlen, uint8_t *rxdata,
+			  int rxlen)
 {
 	int i = 0;
 	enum gpio_signal gpio = spi_device->gpio_cs;
-	static struct mutex spi_lock;
 
-	mutex_lock(&spi_lock);
-	/* Make sure CS# is a GPIO output mode. */
-	gpio_set_flags(gpio, GPIO_OUTPUT);
-	/* Make sure CS# is deselected */
-	gpio_set_level(gpio, 1);
 	/* Cleaning junk data in the buffer */
 	clear_databuf();
 	/* Assert CS# to start transaction */
@@ -151,14 +129,24 @@ int spi_transaction(const struct spi_device_t *spi_device,
 		while (IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_BSY))
 			;
 		/* Write the data */
-		NPCX_SPI_DATA =  txdata[i];
+		NPCX_SPI_DATA = txdata[i];
 		CPRINTS("txdata[i]=%x", txdata[i]);
 		/* Waiting till reading is finished */
 		while (!IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_RBF))
 			;
-		/* Reading the (unused) data */
-		clear_databuf();
+
+		if (rxlen == SPI_READBACK_ALL) {
+			rxdata[i] = (uint8_t)NPCX_SPI_DATA;
+			CPRINTS("rxdata[i]=%x", rxdata[i]);
+		} else {
+			/* Reading the (unused) data to empty the read buffer */
+			clear_databuf();
+		}
 	}
+
+	if (rxlen == SPI_READBACK_ALL)
+		return EC_SUCCESS;
+
 	CPRINTS("write end");
 	/* Reading the data */
 	for (i = 0; i < rxlen; ++i) {
@@ -166,7 +154,7 @@ int spi_transaction(const struct spi_device_t *spi_device,
 		while (IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_BSY))
 			;
 		/* Write the (unused) data */
-		NPCX_SPI_DATA =  0;
+		NPCX_SPI_DATA = 0;
 		/* Wait till reading is finished */
 		while (!IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_RBF))
 			;
@@ -174,13 +162,53 @@ int spi_transaction(const struct spi_device_t *spi_device,
 		rxdata[i] = (uint8_t)NPCX_SPI_DATA;
 		CPRINTS("rxdata[i]=%x", rxdata[i]);
 	}
+
+	return EC_SUCCESS;
+}
+
+int spi_transaction_flush(const struct spi_device_t *spi_device)
+{
+	enum gpio_signal gpio = spi_device->gpio_cs;
+
+	/* Making sure if the SPI transaction already finishes */
+	while (IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_BSY))
+		;
 	/* Deassert CS# (high) to end transaction */
 	gpio_set_level(gpio, 1);
-	mutex_unlock(&spi_lock);
 
 	return EC_SUCCESS;
 }
 
+int spi_transaction_wait(const struct spi_device_t *spi_device)
+{
+	return EC_SUCCESS;
+}
+
+/**
+ * Flush an SPI transaction and receive data from peripheral.
+ *
+ * @param   spi_device  device to talk to
+ * @param   txdata  transfer data
+ * @param   txlen   transfer length
+ * @param   rxdata  receive data
+ * @param   rxlen   receive length
+ * @return  success
+ * @notes   set controller transaction mode in npcx chip
+ */
+int spi_transaction(const struct spi_device_t *spi_device,
+		    const uint8_t *txdata, int txlen, uint8_t *rxdata,
+		    int rxlen)
+{
+	int rv;
+
+	mutex_lock(&spi_lock);
+	rv = spi_transaction_async(spi_device, txdata, txlen, rxdata, rxlen);
+	rv |= spi_transaction_flush(spi_device);
+	mutex_unlock(&spi_lock);
+
+	return rv;
+}
+
 /**
  * SPI initial.
  *
@@ -192,11 +220,11 @@ static void spi_init(void)
 	int i;
 	/* Enable clock for SPI peripheral */
 	clock_enable_peripheral(CGC_OFFSET_SPI, CGC_SPI_MASK,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
+				CGC_MODE_RUN | CGC_MODE_SLEEP);
 
 	/* Disabling spi module */
 	for (i = 0; i < spi_devices_used; i++)
-		spi_enable(spi_devices[i].port, 0);
+		spi_enable(&spi_devices[i], 0);
 
 	/* Disabling spi irq */
 	CLEAR_BIT(NPCX_SPI_CTL1, NPCX_SPI_CTL1_EIR);
@@ -213,8 +241,8 @@ static void spi_init(void)
 	CLEAR_BIT(NPCX_SPI_CTL1, NPCX_SPI_CTL1_SCIDL);
 
 	CPRINTS("nSPI_COMP=%x", IS_BIT_SET(NPCX_STRPST, NPCX_STRPST_SPI_COMP));
-	CPRINTS("SPI_SP_SEL=%x", IS_BIT_SET(NPCX_DEV_CTL4,
-			NPCX_DEV_CTL4_SPI_SP_SEL));
+	CPRINTS("SPI_SP_SEL=%x",
+		IS_BIT_SET(NPCX_DEV_CTL4, NPCX_DEV_CTL4_SPI_SP_SEL));
 	/* Cleaning junk data in the buffer */
 	clear_databuf();
 }
@@ -224,7 +252,7 @@ DECLARE_HOOK(HOOK_INIT, spi_init, HOOK_PRIO_INIT_SPI);
 /* Console commands */
 #ifdef CONFIG_CMD_SPI_FLASH
 static int printrx(const char *desc, const uint8_t *txdata, int txlen,
-		int rxlen)
+		   int rxlen)
 {
 	uint8_t rxdata[32];
 	int rv;
@@ -241,15 +269,15 @@ static int printrx(const char *desc, const uint8_t *txdata, int txlen,
 	return EC_SUCCESS;
 }
 
-static int command_spirom(int argc, char **argv)
+static int command_spirom(int argc, const char **argv)
 {
-	uint8_t txmandev[] = {0x90, 0x00, 0x00, 0x00};
-	uint8_t txjedec[] = {0x9f};
-	uint8_t txunique[] = {0x4b, 0x00, 0x00, 0x00, 0x00};
-	uint8_t txsr1[] = {0x05};
-	uint8_t txsr2[] = {0x35};
+	uint8_t txmandev[] = { 0x90, 0x00, 0x00, 0x00 };
+	uint8_t txjedec[] = { 0x9f };
+	uint8_t txunique[] = { 0x4b, 0x00, 0x00, 0x00, 0x00 };
+	uint8_t txsr1[] = { 0x05 };
+	uint8_t txsr2[] = { 0x35 };
 
-	spi_enable(CONFIG_SPI_FLASH_PORT, 1);
+	spi_enable(SPI_FLASH_DEVICE, 1);
 
 	printrx("Man/Dev ID", txmandev, sizeof(txmandev), 2);
 	printrx("JEDEC ID", txjedec, sizeof(txjedec), 3);
@@ -257,11 +285,10 @@ static int command_spirom(int argc, char **argv)
 	printrx("Status reg 1", txsr1, sizeof(txsr1), 1);
 	printrx("Status reg 2", txsr2, sizeof(txsr2), 1);
 
-	spi_enable(CONFIG_SPI_FLASH_PORT, 0);
+	spi_enable(SPI_FLASH_DEVICE, 0);
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(spirom, command_spirom,
-		NULL,
-		"Test reading SPI EEPROM");
+DECLARE_CONSOLE_COMMAND(spirom, command_spirom, NULL,
+			"Test reading SPI EEPROM");
 #endif
diff --git a/chip/npcx/spiflashfw/monitor_hdr.c b/chip/npcx/spiflashfw/monitor_hdr.c
index 219a037d27..09606c4c31 100644
--- a/chip/npcx/spiflashfw/monitor_hdr.c
+++ b/chip/npcx/spiflashfw/monitor_hdr.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -20,7 +20,7 @@ const struct monitor_header_tag monitor_hdr = {
 	 * programed into the SPI flash.
 	 */
 	CONFIG_PROGRAM_MEMORY_BASE,
-	/* 0x0C:The Flash start address to be programmed*/
+/* 0x0C:The Flash start address to be programmed*/
 #ifdef SECTION_IS_RO
 	/* Default: RO image is programed from the start of SPI flash */
 	CONFIG_EC_PROTECTED_STORAGE_OFF,
diff --git a/chip/npcx/spiflashfw/npcx_monitor.c b/chip/npcx/spiflashfw/npcx_monitor.c
index cd52e7a80f..0d8530a456 100644
--- a/chip/npcx/spiflashfw/npcx_monitor.c
+++ b/chip/npcx/spiflashfw/npcx_monitor.c
@@ -1,16 +1,17 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * NPCX SoC spi flash update tool - monitor firmware
  */
 
-#include <stdint.h>
 #include "config.h"
 #include "npcx_monitor.h"
 #include "registers.h"
 #include "util.h"
 
+#include <stdint.h>
+
 /*****************************************************************************/
 /* spi flash internal functions */
 void sspi_flash_pinmux(int enable)
@@ -49,7 +50,7 @@ void sspi_flash_execute_cmd(uint8_t code, uint8_t cts)
 	/* set UMA_CODE */
 	NPCX_UMA_CODE = code;
 	/* execute UMA flash transaction */
-	NPCX_UMA_CTS  = cts;
+	NPCX_UMA_CTS = cts;
 	while (IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE))
 		;
 }
@@ -76,7 +77,7 @@ void sspi_flash_wait_ready(void)
 	sspi_flash_execute_cmd(CMD_READ_STATUS_REG, MASK_CMD_ONLY);
 	do {
 		/* Read status register */
-		NPCX_UMA_CTS  = MASK_RD_1BYTE;
+		NPCX_UMA_CTS = MASK_RD_1BYTE;
 		while (IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE))
 			;
 	} while (NPCX_UMA_DB0 & mask); /* Wait for Busy clear */
@@ -108,7 +109,7 @@ void sspi_flash_set_address(uint32_t dest_addr)
 }
 
 void sspi_flash_burst_write(unsigned int dest_addr, unsigned int bytes,
-		const char *data)
+			    const char *data)
 {
 	unsigned int i;
 	/* Chip Select down. */
@@ -197,7 +198,7 @@ void sspi_flash_physical_erase(int offset, int size)
 
 	/* Alignment has been checked in upper layer */
 	for (; size > 0; size -= NPCX_MONITOR_FLASH_ERASE_SIZE,
-		offset += NPCX_MONITOR_FLASH_ERASE_SIZE) {
+			 offset += NPCX_MONITOR_FLASH_ERASE_SIZE) {
 		/* Enable write */
 		sspi_flash_write_enable();
 		/* Set erase address */
@@ -221,7 +222,7 @@ int sspi_flash_verify(int offset, int size, const char *data)
 	uint8_t cmp_data;
 
 	ptr_flash = (uint8_t *)(CONFIG_MAPPED_STORAGE_BASE + offset);
-	ptr_mram  = (uint8_t *)data;
+	ptr_mram = (uint8_t *)data;
 	result = 1;
 
 	/* Disable tri-state */
@@ -255,12 +256,11 @@ int sspi_flash_get_image_used(const char *fw_base)
 	for (size--; size > 0 && image[size] != 0xea; size--)
 		;
 
-	return size ? size + 1 : 0;  /* 0xea byte IS part of the image */
-
+	return size ? size + 1 : 0; /* 0xea byte IS part of the image */
 }
 
 /* Entry function of spi upload function */
-uint32_t  __attribute__ ((section(".startup_text")))
+uint32_t __attribute__((section(".startup_text")))
 sspi_flash_upload(int spi_offset, int spi_size)
 {
 	/*
@@ -315,7 +315,7 @@ sspi_flash_upload(int spi_offset, int spi_size)
 		/* Start to write */
 		if (image_base != NULL)
 			sspi_flash_physical_write(spi_offset, sz_image,
-						image_base);
+						  image_base);
 		/* Verify data */
 		if (sspi_flash_verify(spi_offset, sz_image, image_base))
 			*flag_upload |= 0x02;
@@ -335,4 +335,3 @@ sspi_flash_upload(int spi_offset, int spi_size)
 	for (;;)
 		;
 }
-
diff --git a/chip/npcx/spiflashfw/npcx_monitor.h b/chip/npcx/spiflashfw/npcx_monitor.h
index f4f30454d2..54303958d6 100644
--- a/chip/npcx/spiflashfw/npcx_monitor.h
+++ b/chip/npcx/spiflashfw/npcx_monitor.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,11 +7,11 @@
 
 #include <stdint.h>
 
-#define NPCX_MONITOR_UUT_TAG      0xA5075001
-#define NPCX_MONITOR_HEADER_ADDR  0x200C3000
+#define NPCX_MONITOR_UUT_TAG 0xA5075001
+#define NPCX_MONITOR_HEADER_ADDR 0x200C3000
 
 /* Flag to record the progress of programming SPI flash */
-#define SPI_PROGRAMMING_FLAG     0x200C4000
+#define SPI_PROGRAMMING_FLAG 0x200C4000
 
 struct monitor_header_tag {
 	/* offset 0x00: TAG NPCX_MONITOR_TAG */
@@ -23,9 +23,9 @@ struct monitor_header_tag {
 	/* offset 0x0C: The Flash address to be programmed (Absolute address) */
 	uint32_t dest_addr;
 	/* offset 0x10: Maximum allowable flash clock frequency */
-	uint8_t  max_clock;
+	uint8_t max_clock;
 	/* offset 0x11: SPI Flash read mode */
-	uint8_t  read_mode;
+	uint8_t read_mode;
 	/* offset 0x12: Reserved */
 	uint16_t reserved;
 } __packed;
diff --git a/chip/npcx/spiflashfw/npcx_monitor.ld b/chip/npcx/spiflashfw/npcx_monitor.ld
index 03e38b0609..434945b04c 100644
--- a/chip/npcx/spiflashfw/npcx_monitor.ld
+++ b/chip/npcx/spiflashfw/npcx_monitor.ld
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -49,4 +49,5 @@ SECTIONS
      */
     _sidata = _etext;
 
+    /DISCARD/ : { *(.ARM.*) }
 }
diff --git a/chip/npcx/system-npcx5.c b/chip/npcx/system-npcx5.c
index 4dd12fbae2..08aafe422d 100644
--- a/chip/npcx/system-npcx5.c
+++ b/chip/npcx/system-npcx5.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,6 +6,7 @@
 #include <stdnoreturn.h>
 
 /* System module driver depends on chip series for Chrome EC */
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
 #include "cpu.h"
@@ -39,9 +40,9 @@ void system_mpu_config(void)
 	CPU_MPU_CTRL = 0x7;
 
 	/* Create a new MPU Region to allow execution from low-power ram */
-	CPU_MPU_RNR  = REGION_CHIP_RESERVED;
+	CPU_MPU_RNR = REGION_CHIP_RESERVED;
 	CPU_MPU_RASR = CPU_MPU_RASR & 0xFFFFFFFE; /* Disable region */
-	CPU_MPU_RBAR = CONFIG_LPRAM_BASE;         /* Set region base address */
+	CPU_MPU_RBAR = CONFIG_LPRAM_BASE; /* Set region base address */
 	/*
 	 * Set region size & attribute and enable region
 	 * [31:29] - Reserved.
@@ -61,7 +62,7 @@ void system_mpu_config(void)
 /**
  * hibernate function in low power ram for npcx5 series.
  */
-noreturn void __keep __attribute__ ((section(".lowpower_ram")))
+noreturn void __keep __attribute__((section(".lowpower_ram")))
 __enter_hibernate_in_lpram(void)
 {
 	/*
@@ -69,10 +70,8 @@ __enter_hibernate_in_lpram(void)
 	 * Our bypass needs stack instructions but FW will turn off main ram
 	 * later for better power consumption.
 	 */
-	asm (
-		"ldr r0, =0x40001800\n"
-		"mov sp, r0\n"
-	);
+	asm("ldr r0, =0x40001800\n"
+	    "mov sp, r0\n");
 
 	/* Disable Code RAM first */
 	SET_BIT(NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_5), NPCX_PWDWN_CTL5_MRFSH_DIS);
@@ -88,13 +87,12 @@ __enter_hibernate_in_lpram(void)
 	 * wake-up from deep idle.
 	 * Workaround: Apply the same bypass of idle but don't enable interrupt.
 	 */
-	asm (
-		"push {r0-r5}\n"        /* Save needed registers */
-		"ldr r0, =0x40001600\n" /* Set r0 to Suspend RAM addr */
-		"wfi\n"                 /* Wait for int to enter idle */
-		"ldm r0, {r0-r5}\n"     /* Add a delay after WFI */
-		"pop {r0-r5}\n"         /* Restore regs before enabling ints */
-		"isb\n"                 /* Flush the cpu pipeline */
+	asm("push {r0-r5}\n" /* Save needed registers */
+	    "ldr r0, =0x40001600\n" /* Set r0 to Suspend RAM addr */
+	    "wfi\n" /* Wait for int to enter idle */
+	    "ldm r0, {r0-r5}\n" /* Add a delay after WFI */
+	    "pop {r0-r5}\n" /* Restore regs before enabling ints */
+	    "isb\n" /* Flush the cpu pipeline */
 	);
 
 	/* RTC wake-up */
@@ -129,7 +127,7 @@ void __hibernate_npcx_series(void)
 {
 	int i;
 	void (*__hibernate_in_lpram)(void) =
-			(void(*)(void))(__lpram_fw_start | 0x01);
+		(void (*)(void))(__lpram_fw_start | 0x01);
 
 	/* Enable power for the Low Power RAM */
 	CLEAR_BIT(NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_6), 6);
@@ -140,7 +138,7 @@ void __hibernate_npcx_series(void)
 	/* Copy the __enter_hibernate_in_lpram instructions to LPRAM */
 	for (i = 0; i < &__flash_lpfw_end - &__flash_lpfw_start; i++)
 		*((uint32_t *)__lpram_fw_start + i) =
-				*(&__flash_lpfw_start + i);
+			*(&__flash_lpfw_start + i);
 
 	/* execute hibernate func in LPRAM */
 	__hibernate_in_lpram();
@@ -148,7 +146,7 @@ void __hibernate_npcx_series(void)
 
 #ifdef CONFIG_EXTERNAL_STORAGE
 /* Sysjump utilities in low power ram for npcx5 series. */
-noreturn void __keep __attribute__ ((section(".lowpower_ram2")))
+noreturn void __keep __attribute__((section(".lowpower_ram2")))
 __start_gdma(uint32_t exeAddr)
 {
 	/* Enable GDMA now */
@@ -159,7 +157,7 @@ __start_gdma(uint32_t exeAddr)
 
 	/* Wait for transfer to complete/fail */
 	while (!IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_TC) &&
-			!IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAERR))
+	       !IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAERR))
 		;
 
 	/* Disable GDMA now */
@@ -186,7 +184,7 @@ __start_gdma(uint32_t exeAddr)
 
 /* Bypass for GMDA issue of ROM api utilities only on npcx5 series. */
 void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr,
-		uint32_t size, uint32_t exeAddr)
+				uint32_t size, uint32_t exeAddr)
 {
 	int i;
 	uint8_t chunkSize = 16; /* 4 data burst mode. ie.16 bytes */
@@ -195,7 +193,7 @@ void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr,
 	 * it's a thumb branch for cortex-m series CPU.
 	 */
 	void (*__start_gdma_in_lpram)(uint32_t) =
-			(void(*)(uint32_t))(__lpram_lfw_start | 0x01);
+		(void (*)(uint32_t))(__lpram_lfw_start | 0x01);
 
 	/*
 	 * Before enabling burst mode for better performance of GDMA, it's
@@ -203,7 +201,7 @@ void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr,
 	 * are 16 bytes aligned in case failure occurs.
 	 */
 	ASSERT((size % chunkSize) == 0 && (srcAddr % chunkSize) == 0 &&
-			(dstAddr % chunkSize) == 0);
+	       (dstAddr % chunkSize) == 0);
 
 	/* Check valid address for jumpiing */
 	ASSERT(exeAddr != 0x0);
@@ -253,7 +251,7 @@ void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr,
 	/* Copy the __start_gdma_in_lpram instructions to LPRAM */
 	for (i = 0; i < &__flash_lplfw_end - &__flash_lplfw_start; i++)
 		*((uint32_t *)__lpram_lfw_start + i) =
-				*(&__flash_lplfw_start + i);
+			*(&__flash_lplfw_start + i);
 
 	/* Start GDMA in Suspend RAM */
 	__start_gdma_in_lpram(exeAddr);
diff --git a/chip/npcx/system-npcx7.c b/chip/npcx/system-npcx7.c
index 89b3e25e9b..386544ed04 100644
--- a/chip/npcx/system-npcx7.c
+++ b/chip/npcx/system-npcx7.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,73 +6,35 @@
 #include <stdnoreturn.h>
 
 /* System module driver depends on chip series for Chrome EC */
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
 #include "cpu.h"
 #include "ec_commands.h"
+#include "gpio.h"
 #include "hooks.h"
+#include "hwtimer_chip.h"
 #include "lct_chip.h"
 #include "registers.h"
+#include "rom_chip.h"
 #include "system.h"
+#include "system_chip.h"
 #include "task.h"
 #include "util.h"
-#include "gpio.h"
-#include "hwtimer_chip.h"
-#include "mpu.h"
-#include "system_chip.h"
-#include "rom_chip.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
 /* Macros for last 32K ram block */
 #define LAST_RAM_BLK ((NPCX_RAM_SIZE / (32 * 1024)) - 1)
 /* Higher bits are reserved and need to be masked */
-#define RAM_PD_MASK  (~BIT(LAST_RAM_BLK))
+#define RAM_PD_MASK (~BIT(LAST_RAM_BLK))
 
-#ifdef CONFIG_WORKAROUND_FLASH_DOWNLOAD_API
-#define LFW_OFFSET 0x160
-/* Begin address of Suspend RAM for little FW (GDMA utilities). */
-uintptr_t __lpram_lfw_start = CONFIG_LPRAM_BASE + LFW_OFFSET;
-#endif
 /*****************************************************************************/
 /* IC specific low-level driver depends on chip series */
 
-/*
- * Configure address 0x40001600 (Low Power RAM) in the the MPU
- * (Memory Protection Unit) as a "regular" memory
- */
 void system_mpu_config(void)
 {
-#ifdef CONFIG_WORKAROUND_FLASH_DOWNLOAD_API
-	/*
-	 * npcx9 Rev.1 has the problem for download_from_flash API.
-	 * Workwaroud it by by the system_download_from_flash function
-	 * in the suspend RAM like npcx5.
-	 * TODO: Remove this when A2 chip is available
-	 */
-	/* Enable MPU */
-	CPU_MPU_CTRL = 0x7;
-
-	/* Create a new MPU Region to allow execution from low-power ram */
-	CPU_MPU_RNR  = REGION_CHIP_RESERVED;
-	CPU_MPU_RASR = CPU_MPU_RASR & 0xFFFFFFFE; /* Disable region */
-	CPU_MPU_RBAR = CONFIG_LPRAM_BASE;         /* Set region base address */
-	/*
-	 * Set region size & attribute and enable region
-	 * [31:29] - Reserved.
-	 * [28]    - XN (Execute Never) = 0
-	 * [27]    - Reserved.
-	 * [26:24] - AP                 = 011 (Full access)
-	 * [23:22] - Reserved.
-	 * [21:19,18,17,16] - TEX,S,C,B = 001000 (Normal memory)
-	 * [15:8]  - SRD                = 0 (Subregions enabled)
-	 * [7:6]   - Reserved.
-	 * [5:1]   - SIZE               = 01001 (1K)
-	 * [0]     - ENABLE             = 1 (enabled)
-	 */
-	CPU_MPU_RASR = 0x03080013;
-#endif
 }
 
 #ifdef CONFIG_HIBERNATE_PSL
@@ -122,11 +84,11 @@ void system_enter_psl_mode(void)
 	NPCX_BBRAM(BBRM_DATA_INDEX_WAKE) = HIBERNATE_WAKE_PSL;
 
 #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
-	 /*
-	  * If pulse mode is enabled, the VCC power is turned off by the
-	  * external component (Ex: PMIC) but PSL_OUT. So we can just return
-	  * here.
-	  */
+	/*
+	 * If pulse mode is enabled, the VCC power is turned off by the
+	 * external component (Ex: PMIC) but PSL_OUT. So we can just return
+	 * here.
+	 */
 	if (IS_BIT_SET(NPCX_GLUE_PSL_MCTL1, NPCX_GLUE_PSL_MCTL1_PLS_EN))
 		return;
 #endif
@@ -152,8 +114,7 @@ static void system_psl_type_sel(enum psl_pin_t psl_pin, uint32_t flags)
 	/* Set PSL input events' type as level or edge trigger */
 	if ((flags & GPIO_INT_F_HIGH) || (flags & GPIO_INT_F_LOW))
 		CLEAR_BIT(NPCX_GLUE_PSL_CTS, psl_pin + 4);
-	else if ((flags & GPIO_INT_F_RISING) ||
-		 (flags & GPIO_INT_F_FALLING))
+	else if ((flags & GPIO_INT_F_RISING) || (flags & GPIO_INT_F_FALLING))
 		SET_BIT(NPCX_GLUE_PSL_CTS, psl_pin + 4);
 
 	/*
@@ -184,7 +145,7 @@ int system_config_psl_mode(enum gpio_signal signal)
  * Hibernate function in last 32K ram block for npcx7 series.
  * Do not use global variable since we also turn off data ram.
  */
-noreturn void __keep __attribute__ ((section(".after_init")))
+noreturn void __keep __attribute__((section(".after_init")))
 __enter_hibernate_in_last_block(void)
 {
 	/*
@@ -203,7 +164,7 @@ __enter_hibernate_in_last_block(void)
 	NPCX_PMCSR = 0x6;
 
 	/* Enter deep idle, wake-up by GPIOs or RTC */
-	asm volatile ("wfi");
+	asm volatile("wfi");
 
 	/* RTC wake-up */
 	if (IS_BIT_SET(NPCX_WTC, NPCX_WTC_PTO))
@@ -247,8 +208,8 @@ void __hibernate_npcx_series(void)
 	__enter_hibernate_in_psl();
 #else
 	/* Make sure this is located in the last 32K code RAM block */
-	ASSERT((uint32_t)(&__after_init_end) - CONFIG_PROGRAM_MEMORY_BASE
-								< (32*1024));
+	ASSERT((uint32_t)(&__after_init_end) - CONFIG_PROGRAM_MEMORY_BASE <
+	       (32 * 1024));
 
 	/* Execute hibernate func in last 32K block */
 	__enter_hibernate_in_last_block();
@@ -268,125 +229,3 @@ static void report_psl_wake_source(void)
 }
 DECLARE_HOOK(HOOK_INIT, report_psl_wake_source, HOOK_PRIO_DEFAULT);
 #endif
-
-/*
- * npcx9 Rev.1 has the problem for download_from_flash API.
- * Workwaroud it by executing the system_download_from_flash function
- * in the suspend RAM like npcx5.
- * TODO: Removing npcx9 when Rev.2 is available.
- */
-#ifdef CONFIG_WORKAROUND_FLASH_DOWNLOAD_API
-#ifdef CONFIG_EXTERNAL_STORAGE
-/* Sysjump utilities in low power ram for npcx9 series. */
-noreturn void __keep __attribute__ ((section(".lowpower_ram2")))
-__start_gdma(uint32_t exeAddr)
-{
-	/* Enable GDMA now */
-	SET_BIT(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAEN);
-
-	/* Start GDMA */
-	SET_BIT(NPCX_GDMA_CTL, NPCX_GDMA_CTL_SOFTREQ);
-
-	/* Wait for transfer to complete/fail */
-	while (!IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_TC) &&
-			!IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAERR))
-		;
-
-	/* Disable GDMA now */
-	CLEAR_BIT(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAEN);
-
-	/*
-	 * Failure occurs during GMDA transaction. Let watchdog issue and
-	 * boot from RO region again.
-	 */
-	if (IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAERR))
-		while (1)
-			;
-
-	/*
-	 * Jump to the exeAddr address if needed. Setting bit 0 of address to
-	 * indicate it's a thumb branch for cortex-m series CPU.
-	 */
-	((void (*)(void))(exeAddr | 0x01))();
-
-	/* Should never get here */
-	while (1)
-		;
-}
-
-/* Bypass for GMDA issue of ROM api utilities only on npcx5 series. */
-void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr,
-		uint32_t size, uint32_t exeAddr)
-{
-	int i;
-	uint8_t chunkSize = 16; /* 4 data burst mode. ie.16 bytes */
-	/*
-	 * GDMA utility in Suspend RAM. Setting bit 0 of address to indicate
-	 * it's a thumb branch for cortex-m series CPU.
-	 */
-	void (*__start_gdma_in_lpram)(uint32_t) =
-			(void(*)(uint32_t))(__lpram_lfw_start | 0x01);
-
-	/*
-	 * Before enabling burst mode for better performance of GDMA, it's
-	 * important to make sure srcAddr, dstAddr and size of transactions
-	 * are 16 bytes aligned in case failure occurs.
-	 */
-	ASSERT((size % chunkSize) == 0 && (srcAddr % chunkSize) == 0 &&
-			(dstAddr % chunkSize) == 0);
-
-	/* Check valid address for jumpiing */
-	ASSERT(exeAddr != 0x0);
-
-	/* Enable power for the Low Power RAM */
-	CLEAR_BIT(NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_6), 6);
-
-	/* Enable Low Power RAM */
-	NPCX_LPRAM_CTRL = 1;
-
-	/*
-	 * Initialize GDMA for flash reading.
-	 * [31:21] - Reserved.
-	 * [20]    - GDMAERR   = 0  (Indicate GMDA transfer error)
-	 * [19]    - Reserved.
-	 * [18]    - TC        = 0  (Terminal Count. Indicate operation is end.)
-	 * [17]    - Reserved.
-	 * [16]    - SOFTREQ   = 0  (Don't trigger here)
-	 * [15]    - DM        = 0  (Set normal demand mode)
-	 * [14]    - Reserved.
-	 * [13:12] - TWS.      = 10 (One double-word for every GDMA transaction)
-	 * [11:10] - Reserved.
-	 * [9]     - BME       = 1  (4-data ie.16 bytes - Burst mode enable)
-	 * [8]     - SIEN      = 0  (Stop interrupt disable)
-	 * [7]     - SAFIX     = 0  (Fixed source address)
-	 * [6]     - Reserved.
-	 * [5]     - SADIR     = 0  (Source address incremented)
-	 * [4]     - DADIR     = 0  (Destination address incremented)
-	 * [3:2]   - GDMAMS    = 00 (Software mode)
-	 * [1]     - Reserved.
-	 * [0]     - ENABLE    = 0  (Don't enable yet)
-	 */
-	NPCX_GDMA_CTL = 0x00002200;
-
-	/* Set source base address */
-	NPCX_GDMA_SRCB = CONFIG_MAPPED_STORAGE_BASE + srcAddr;
-
-	/* Set destination base address */
-	NPCX_GDMA_DSTB = dstAddr;
-
-	/* Set number of transfers */
-	NPCX_GDMA_TCNT = (size / chunkSize);
-
-	/* Clear Transfer Complete event */
-	SET_BIT(NPCX_GDMA_CTL, NPCX_GDMA_CTL_TC);
-
-	/* Copy the __start_gdma_in_lpram instructions to LPRAM */
-	for (i = 0; i < &__flash_lplfw_end - &__flash_lplfw_start; i++)
-		*((uint32_t *)__lpram_lfw_start + i) =
-				*(&__flash_lplfw_start + i);
-
-	/* Start GDMA in Suspend RAM */
-	__start_gdma_in_lpram(exeAddr);
-}
-#endif /* CONFIG_EXTERNAL_STORAGE */
-#endif
diff --git a/chip/npcx/system-npcx9.c b/chip/npcx/system-npcx9.c
deleted file mode 120000
index 48088614a0..0000000000
--- a/chip/npcx/system-npcx9.c
+++ /dev/null
@@ -1 +0,0 @@
-system-npcx7.c
\ No newline at end of file
diff --git a/chip/npcx/system-npcx9.c b/chip/npcx/system-npcx9.c
new file mode 100644
index 0000000000..386544ed04
--- /dev/null
+++ b/chip/npcx/system-npcx9.c
@@ -0,0 +1,231 @@
+/* Copyright 2017 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <stdnoreturn.h>
+
+/* System module driver depends on chip series for Chrome EC */
+#include "builtin/assert.h"
+#include "common.h"
+#include "console.h"
+#include "cpu.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "hwtimer_chip.h"
+#include "lct_chip.h"
+#include "registers.h"
+#include "rom_chip.h"
+#include "system.h"
+#include "system_chip.h"
+#include "task.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+
+/* Macros for last 32K ram block */
+#define LAST_RAM_BLK ((NPCX_RAM_SIZE / (32 * 1024)) - 1)
+/* Higher bits are reserved and need to be masked */
+#define RAM_PD_MASK (~BIT(LAST_RAM_BLK))
+
+/*****************************************************************************/
+/* IC specific low-level driver depends on chip series */
+
+void system_mpu_config(void)
+{
+}
+
+#ifdef CONFIG_HIBERNATE_PSL
+#ifndef NPCX_PSL_MODE_SUPPORT
+#error "Do not enable CONFIG_HIBERNATE_PSL if npcx ec doesn't support PSL mode!"
+#endif
+
+static enum psl_pin_t system_gpio_to_psl(enum gpio_signal signal)
+{
+	enum psl_pin_t psl_no;
+	const struct gpio_info *g = gpio_list + signal;
+
+	if (g->port == GPIO_PORT_D && g->mask == MASK_PIN2) /* GPIOD2 */
+		psl_no = PSL_IN1;
+	else if (g->port == GPIO_PORT_0 && (g->mask & 0x07)) /* GPIO00/01/02 */
+		psl_no = GPIO_MASK_TO_NUM(g->mask) + 1;
+	else
+		psl_no = PSL_NONE;
+
+	return psl_no;
+}
+
+#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
+void system_set_psl_gpo(int level)
+{
+	if (level)
+		SET_BIT(NPCX_GLUE_PSL_MCTL1, NPCX_GLUE_PSL_MCTL1_PSL_GPO_CTL);
+	else
+		CLEAR_BIT(NPCX_GLUE_PSL_MCTL1, NPCX_GLUE_PSL_MCTL1_PSL_GPO_CTL);
+}
+#endif
+
+void system_enter_psl_mode(void)
+{
+	/* Configure pins from GPIOs to PSL which rely on VSBY power rail. */
+	gpio_config_module(MODULE_PMU, 1);
+
+	/*
+	 * In npcx7, only physical PSL_IN pins can pull PSL_OUT to high and
+	 * reboot ec.
+	 * In npcx9, LCT timeout event can also pull PSL_OUT.
+	 * We won't decide the wake cause now but only mark we are entering
+	 * hibernation via PSL.
+	 * The actual wakeup cause will be checked by the PSL input event bits
+	 * when ec reboots.
+	 */
+	NPCX_BBRAM(BBRM_DATA_INDEX_WAKE) = HIBERNATE_WAKE_PSL;
+
+#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
+	/*
+	 * If pulse mode is enabled, the VCC power is turned off by the
+	 * external component (Ex: PMIC) but PSL_OUT. So we can just return
+	 * here.
+	 */
+	if (IS_BIT_SET(NPCX_GLUE_PSL_MCTL1, NPCX_GLUE_PSL_MCTL1_PLS_EN))
+		return;
+#endif
+
+	/*
+	 * Pull PSL_OUT (GPIO85) to low to cut off ec's VCC power rail by
+	 * setting bit 5 of PDOUT(8).
+	 */
+	SET_BIT(NPCX_PDOUT(GPIO_PORT_8), 5);
+}
+
+/* Hibernate function implemented by PSL (Power Switch Logic) mode. */
+noreturn void __keep __enter_hibernate_in_psl(void)
+{
+	system_enter_psl_mode();
+	/* Spin and wait for PSL cuts power; should never return */
+	while (1)
+		;
+}
+
+static void system_psl_type_sel(enum psl_pin_t psl_pin, uint32_t flags)
+{
+	/* Set PSL input events' type as level or edge trigger */
+	if ((flags & GPIO_INT_F_HIGH) || (flags & GPIO_INT_F_LOW))
+		CLEAR_BIT(NPCX_GLUE_PSL_CTS, psl_pin + 4);
+	else if ((flags & GPIO_INT_F_RISING) || (flags & GPIO_INT_F_FALLING))
+		SET_BIT(NPCX_GLUE_PSL_CTS, psl_pin + 4);
+
+	/*
+	 * Set PSL input events' polarity is low (high-to-low) active or
+	 * high (low-to-high) active
+	 */
+	if (flags & GPIO_HIB_WAKE_HIGH)
+		SET_BIT(NPCX_DEVALT(ALT_GROUP_D), 2 * psl_pin);
+	else
+		CLEAR_BIT(NPCX_DEVALT(ALT_GROUP_D), 2 * psl_pin);
+}
+
+int system_config_psl_mode(enum gpio_signal signal)
+{
+	enum psl_pin_t psl_no;
+	const struct gpio_info *g = gpio_list + signal;
+
+	psl_no = system_gpio_to_psl(signal);
+	if (psl_no == PSL_NONE)
+		return 0;
+
+	system_psl_type_sel(psl_no, g->flags);
+	return 1;
+}
+
+#else
+/**
+ * Hibernate function in last 32K ram block for npcx7 series.
+ * Do not use global variable since we also turn off data ram.
+ */
+noreturn void __keep __attribute__((section(".after_init")))
+__enter_hibernate_in_last_block(void)
+{
+	/*
+	 * The hibernate utility is located in the last block of RAM. The size
+	 * of each RAM block is 32KB. We turn off all blocks except last one
+	 * for better power consumption.
+	 */
+	NPCX_RAM_PD(0) = RAM_PD_MASK & 0xFF;
+#if defined(CHIP_FAMILY_NPCX7)
+	NPCX_RAM_PD(1) = (RAM_PD_MASK >> 8) & 0x0F;
+#elif defined(CHIP_FAMILY_NPCX9)
+	NPCX_RAM_PD(1) = (RAM_PD_MASK >> 8) & 0x7F;
+#endif
+
+	/* Set deep idle mode */
+	NPCX_PMCSR = 0x6;
+
+	/* Enter deep idle, wake-up by GPIOs or RTC */
+	asm volatile("wfi");
+
+	/* RTC wake-up */
+	if (IS_BIT_SET(NPCX_WTC, NPCX_WTC_PTO))
+		/*
+		 * Mark wake-up reason for hibernate
+		 * Do not call bbram_data_write directly cause of
+		 * no stack.
+		 */
+		NPCX_BBRAM(BBRM_DATA_INDEX_WAKE) = HIBERNATE_WAKE_MTC;
+#ifdef NPCX_LCT_SUPPORT
+	else if (IS_BIT_SET(NPCX_LCTSTAT, NPCX_LCTSTAT_EVST)) {
+		NPCX_BBRAM(BBRM_DATA_INDEX_WAKE) = HIBERNATE_WAKE_LCT;
+		/* Clear LCT event */
+		NPCX_LCTSTAT = BIT(NPCX_LCTSTAT_EVST);
+	}
+#endif
+	else
+		/* Otherwise, we treat it as GPIOs wake-up */
+		NPCX_BBRAM(BBRM_DATA_INDEX_WAKE) = HIBERNATE_WAKE_PIN;
+
+	/* Start a watchdog reset */
+	NPCX_WDCNT = 0x01;
+	/* Reload and restart Timer 0 */
+	SET_BIT(NPCX_T0CSR, NPCX_T0CSR_RST);
+	/* Wait for timer is loaded and restart */
+	while (IS_BIT_SET(NPCX_T0CSR, NPCX_T0CSR_RST))
+		;
+
+	/* Spin and wait for reboot; should never return */
+	while (1)
+		;
+}
+#endif
+
+/**
+ * Hibernate function for different Nuvoton chip series.
+ */
+void __hibernate_npcx_series(void)
+{
+#ifdef CONFIG_HIBERNATE_PSL
+	__enter_hibernate_in_psl();
+#else
+	/* Make sure this is located in the last 32K code RAM block */
+	ASSERT((uint32_t)(&__after_init_end) - CONFIG_PROGRAM_MEMORY_BASE <
+	       (32 * 1024));
+
+	/* Execute hibernate func in last 32K block */
+	__enter_hibernate_in_last_block();
+#endif
+}
+
+#if defined(CONFIG_HIBERNATE_PSL)
+static void report_psl_wake_source(void)
+{
+	if (!(system_get_reset_flags() & EC_RESET_FLAG_HIBERNATE))
+		return;
+
+	CPRINTS("PSL_CTS: 0x%x", NPCX_GLUE_PSL_CTS & 0xf);
+#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
+	CPRINTS("PSL_MCTL1 event: 0x%x", NPCX_GLUE_PSL_MCTL1 & 0x18);
+#endif
+}
+DECLARE_HOOK(HOOK_INIT, report_psl_wake_source, HOOK_PRIO_DEFAULT);
+#endif
diff --git a/chip/npcx/system.c b/chip/npcx/system.c
index e74ae65d58..9ce043354f 100644
--- a/chip/npcx/system.c
+++ b/chip/npcx/system.c
@@ -1,10 +1,11 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* System module for Chrome EC : NPCX hardware specific implementation */
 
+#include "builtin/assert.h"
 #include "clock.h"
 #include "clock_chip.h"
 #include "common.h"
@@ -15,6 +16,7 @@
 #include "host_command.h"
 #include "hwtimer_chip.h"
 #include "lct_chip.h"
+#include "panic.h"
 #include "registers.h"
 #include "rom_chip.h"
 #include "sib_chip.h"
@@ -27,23 +29,32 @@
 
 /* Delay after writing TTC for value to latch */
 #define MTC_TTC_LOAD_DELAY_US 250
-#define MTC_ALARM_MASK     (BIT(25) - 1)
-#define MTC_WUI_GROUP      MIWU_GROUP_4
-#define MTC_WUI_MASK       MASK_PIN7
+#define MTC_ALARM_MASK (BIT(25) - 1)
+#define MTC_WUI_GROUP MIWU_GROUP_4
+#define MTC_WUI_MASK MASK_PIN7
 
 /* ROM address of chip revision */
 #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
-#define CHIP_REV_ADDR        0x0000FFFC
-#define CHIP_REV_STR_SIZE    12
+#define CHIP_REV_ADDR 0x0000FFFC
+#define CHIP_REV_STR_SIZE 12
+#define PWDWN_8_RESERVED_SET_MASK 0x30
 #else
-#define CHIP_REV_ADDR        0x00007FFC
-#define CHIP_REV_STR_SIZE    6
+#define CHIP_REV_ADDR 0x00007FFC
+#define CHIP_REV_STR_SIZE 6
 #endif
 
+/*  Legacy SuperI/O Configuration D register offset */
+#define SIOCFD_REG_OFFSET 0x2D
+
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+
+#if defined(NPCX_LCT_SUPPORT)
+/* A flag for waking up from hibernate mode by RTC overflow event */
+static int is_rtc_overflow_event;
+#endif
 
 /*****************************************************************************/
 /* Internal functions */
@@ -82,13 +93,9 @@ void system_watchdog_reset(void)
 /* Return true if index is stored as a single byte in bbram */
 static int bbram_is_byte_access(enum bbram_data_index index)
 {
-	return (index >= BBRM_DATA_INDEX_VBNVCNTXT &&
-		index <  BBRM_DATA_INDEX_RAMLOG)
-		|| index == BBRM_DATA_INDEX_PD0
-		|| index == BBRM_DATA_INDEX_PD1
-		|| index == BBRM_DATA_INDEX_PD2
-		|| index == BBRM_DATA_INDEX_PANIC_FLAGS
-	;
+	return index == BBRM_DATA_INDEX_PD0 || index == BBRM_DATA_INDEX_PD1 ||
+	       index == BBRM_DATA_INDEX_PD2 ||
+	       index == BBRM_DATA_INDEX_PANIC_FLAGS;
 }
 
 /* Check and clear BBRAM status on any reset */
@@ -100,7 +107,7 @@ void system_check_bbram_on_reset(void)
 		 * dropped, print a warning message.
 		 */
 		if (IS_BIT_SET(NPCX_RSTCTL, NPCX_RSTCTL_VCC1_RST_SCRATCH) ||
-			IS_BIT_SET(NPCX_RSTCTL, NPCX_RSTCTL_VCC1_RST_STS))
+		    IS_BIT_SET(NPCX_RSTCTL, NPCX_RSTCTL_VCC1_RST_STS))
 			CPRINTF("VBAT drop!\n");
 
 		/*
@@ -171,7 +178,7 @@ static int bbram_data_write(enum bbram_data_index index, uint32_t value)
 	/* Write BBRAM */
 	NPCX_BBRAM(index) = value & 0xFF;
 	if (bytes == 4) {
-		NPCX_BBRAM(index + 1) = (value >> 8)  & 0xFF;
+		NPCX_BBRAM(index + 1) = (value >> 8) & 0xFF;
 		NPCX_BBRAM(index + 2) = (value >> 16) & 0xFF;
 		NPCX_BBRAM(index + 3) = (value >> 24) & 0xFF;
 	}
@@ -183,10 +190,6 @@ static int bbram_data_write(enum bbram_data_index index, uint32_t value)
 /* Map idx to a returned BBRM_DATA_INDEX_*, or return -1 on invalid idx */
 static int bbram_idx_lookup(enum system_bbram_idx idx)
 {
-	if (idx >= SYSTEM_BBRAM_IDX_VBNVBLOCK0 &&
-	    idx <= SYSTEM_BBRAM_IDX_VBNVBLOCK15)
-		return BBRM_DATA_INDEX_VBNVCNTXT +
-		       idx - SYSTEM_BBRAM_IDX_VBNVBLOCK0;
 	if (idx == SYSTEM_BBRAM_IDX_PD0)
 		return BBRM_DATA_INDEX_PD0;
 	if (idx == SYSTEM_BBRAM_IDX_PD1)
@@ -258,14 +261,14 @@ void system_set_rtc(uint32_t seconds)
  * 2. LREG1, LREG3 and LREG4 store exception, reason and info in case of
  * software panic.
  */
-#define BKUP_CFSR		(BBRM_DATA_INDEX_PANIC_BKUP + 0)
-#define BKUP_HFSR		(BBRM_DATA_INDEX_PANIC_BKUP + 4)
-#define BKUP_BFAR		(BBRM_DATA_INDEX_PANIC_BKUP + 8)
-#define BKUP_LREG1		(BBRM_DATA_INDEX_PANIC_BKUP + 12)
-#define BKUP_LREG3		(BBRM_DATA_INDEX_PANIC_BKUP + 16)
-#define BKUP_LREG4		(BBRM_DATA_INDEX_PANIC_BKUP + 20)
+#define BKUP_CFSR (BBRM_DATA_INDEX_PANIC_BKUP + 0)
+#define BKUP_HFSR (BBRM_DATA_INDEX_PANIC_BKUP + 4)
+#define BKUP_BFAR (BBRM_DATA_INDEX_PANIC_BKUP + 8)
+#define BKUP_LREG1 (BBRM_DATA_INDEX_PANIC_BKUP + 12)
+#define BKUP_LREG3 (BBRM_DATA_INDEX_PANIC_BKUP + 16)
+#define BKUP_LREG4 (BBRM_DATA_INDEX_PANIC_BKUP + 20)
 
-#define BKUP_PANIC_DATA_VALID	BIT(0)
+#define BKUP_PANIC_DATA_VALID BIT(0)
 
 void chip_panic_data_backup(void)
 {
@@ -334,27 +337,35 @@ static void chip_set_hib_flag(uint32_t *flags, uint32_t hib_wake_flags)
 #ifdef NPCX_LCT_SUPPORT
 		if (npcx_lct_is_event_set()) {
 			*flags |= EC_RESET_FLAG_RTC_ALARM |
-					  EC_RESET_FLAG_HIBERNATE;
+				  EC_RESET_FLAG_HIBERNATE;
+			/* Is RTC overflow event? */
+			if (bbram_data_read(BBRM_DATA_INDEX_LCT_TIME) ==
+			    NPCX_LCT_MAX) {
+				/*
+				 * Mark it as RTC overflow event and handle it
+				 * in hook init function later for logging info.
+				 */
+				is_rtc_overflow_event = 1;
+			}
 			npcx_lct_clear_event();
 			return;
 		}
 #endif
-		*flags |= EC_RESET_FLAG_WAKE_PIN |
-				  EC_RESET_FLAG_HIBERNATE;
+		*flags |= EC_RESET_FLAG_WAKE_PIN | EC_RESET_FLAG_HIBERNATE;
 	} else { /* Hibernate via non-PSL */
 #ifdef NPCX_LCT_SUPPORT
 		if (hib_wake_flags & HIBERNATE_WAKE_LCT) {
 			*flags |= EC_RESET_FLAG_RTC_ALARM |
-					  EC_RESET_FLAG_HIBERNATE;
+				  EC_RESET_FLAG_HIBERNATE;
 			return;
 		}
 #endif
 		if (hib_wake_flags & HIBERNATE_WAKE_PIN) {
 			*flags |= EC_RESET_FLAG_WAKE_PIN |
-					  EC_RESET_FLAG_HIBERNATE;
+				  EC_RESET_FLAG_HIBERNATE;
 		} else if (hib_wake_flags & HIBERNATE_WAKE_MTC) {
 			*flags |= EC_RESET_FLAG_RTC_ALARM |
-					  EC_RESET_FLAG_HIBERNATE;
+				  EC_RESET_FLAG_HIBERNATE;
 		}
 	}
 }
@@ -378,6 +389,8 @@ static void check_reset_cause(void)
 	/* Clear saved hibernate wake flag in bbram , too */
 	bbram_data_write(BBRM_DATA_INDEX_WAKE, 0);
 
+	chip_set_hib_flag(&flags, hib_wake_flags);
+
 	/* Use scratch bit to check power on reset or VCC1_RST reset */
 	if (!IS_BIT_SET(NPCX_RSTCTL, NPCX_RSTCTL_VCC1_RST_SCRATCH)) {
 #ifdef CONFIG_BOARD_FORCE_RESET_PIN
@@ -407,9 +420,9 @@ static void check_reset_cause(void)
 					 * clear the flag so later code will
 					 * not wait for the second reset.
 					 */
-					flags =
-					  (flags & ~EC_RESET_FLAG_INITIAL_PWR)
-					   | EC_RESET_FLAG_POWER_ON;
+					flags = (flags &
+						 ~EC_RESET_FLAG_INITIAL_PWR) |
+						EC_RESET_FLAG_POWER_ON;
 				else
 					/*
 					 * No previous power-on flag,
@@ -419,23 +432,28 @@ static void check_reset_cause(void)
 					 */
 					flags |= EC_RESET_FLAG_RESET_PIN;
 			} else {
+				flags |= EC_RESET_FLAG_POWER_ON;
+
 				/*
 				 * Power-on restart, so set a flag and save it
 				 * for the next imminent reset. Later code
 				 * will check for this flag and wait for the
-				 * second reset.
+				 * second reset. Waking from PSL hibernate is
+				 * power-on for EC but not for H1, so do not
+				 * wait for the second reset.
 				 */
-				flags |= EC_RESET_FLAG_POWER_ON
-				      | EC_RESET_FLAG_INITIAL_PWR;
-				chip_flags |= EC_RESET_FLAG_INITIAL_PWR;
+				if (!(flags & EC_RESET_FLAG_HIBERNATE)) {
+					flags |= EC_RESET_FLAG_INITIAL_PWR;
+					chip_flags |= EC_RESET_FLAG_INITIAL_PWR;
+				}
 			}
 		} else
 			/*
 			 * No second reset after power-on, so
 			 * set the flags according to the restart reason.
 			 */
-			flags |= reset ? EC_RESET_FLAG_RESET_PIN
-				       : EC_RESET_FLAG_POWER_ON;
+			flags |= reset ? EC_RESET_FLAG_RESET_PIN :
+					 EC_RESET_FLAG_POWER_ON;
 #endif
 	}
 	chip_save_reset_flags(chip_flags);
@@ -454,8 +472,6 @@ static void check_reset_cause(void)
 		SET_BIT(NPCX_RSTCTL, NPCX_RSTCTL_DBGRST_STS);
 	}
 
-	chip_set_hib_flag(&flags, hib_wake_flags);
-
 	/* Watchdog Reset */
 	if (IS_BIT_SET(NPCX_T0CSR, NPCX_T0CSR_WDRST_STS)) {
 		/*
@@ -464,7 +480,7 @@ static void check_reset_cause(void)
 		 * cause is panic reason or not.
 		 */
 		if (!(flags & (EC_RESET_FLAG_SOFT | EC_RESET_FLAG_HARD |
-				EC_RESET_FLAG_HIBERNATE)))
+			       EC_RESET_FLAG_HIBERNATE)))
 			flags |= EC_RESET_FLAG_WATCHDOG;
 
 		/* Clear watchdog reset status initially*/
@@ -483,10 +499,10 @@ static void system_set_gpios_and_wakeup_inputs_hibernate(void)
 	int table, i;
 
 	/* Disable all MIWU inputs before entering hibernate */
-	for (table = MIWU_TABLE_0 ; table < MIWU_TABLE_2 ; table++) {
-		for (i = 0 ; i < 8 ; i++) {
+	for (table = MIWU_TABLE_0; table < MIWU_TABLE_2; table++) {
+		for (i = 0; i < 8; i++) {
 			/* Disable all wake-ups */
-			NPCX_WKEN(table, i)  = 0x00;
+			NPCX_WKEN(table, i) = 0x00;
 			/* Clear all pending bits of wake-ups */
 			NPCX_WKPCL(table, i) = 0xFF;
 			/*
@@ -499,7 +515,7 @@ static void system_set_gpios_and_wakeup_inputs_hibernate(void)
 
 #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
 	/* Disable MIWU 2 group 6 inputs which used for the additional GPIOs */
-	NPCX_WKEN(MIWU_TABLE_2, MIWU_GROUP_6)  = 0x00;
+	NPCX_WKEN(MIWU_TABLE_2, MIWU_GROUP_6) = 0x00;
 	NPCX_WKPCL(MIWU_TABLE_2, MIWU_GROUP_6) = 0xFF;
 	NPCX_WKINEN(MIWU_TABLE_2, MIWU_GROUP_6) = 0x00;
 #endif
@@ -529,14 +545,17 @@ static void system_set_lct_alarm(uint32_t seconds, uint32_t microseconds)
 #ifdef CONFIG_HIBERNATE_PSL
 	/* Enable LCT event to PSL */
 	npcx_lct_config(seconds, 1, 0);
+	/* save the start time of LCT */
+	if (IS_ENABLED(CONFIG_HOSTCMD_RTC) || IS_ENABLED(CONFIG_CMD_RTC))
+		bbram_data_write(BBRM_DATA_INDEX_LCT_TIME, seconds);
 #else
 	/* Enable LCT event interrupt and MIWU */
 	npcx_lct_config(seconds, 0, 1);
 	task_disable_irq(NPCX_IRQ_LCT_WKINTF_2);
 	/* Enable wake-up input sources & clear pending bit */
-	NPCX_WKPCL(MIWU_TABLE_2, LCT_WUI_GROUP)  |= LCT_WUI_MASK;
+	NPCX_WKPCL(MIWU_TABLE_2, LCT_WUI_GROUP) |= LCT_WUI_MASK;
 	NPCX_WKINEN(MIWU_TABLE_2, LCT_WUI_GROUP) |= LCT_WUI_MASK;
-	NPCX_WKEN(MIWU_TABLE_2, LCT_WUI_GROUP)   |= LCT_WUI_MASK;
+	NPCX_WKEN(MIWU_TABLE_2, LCT_WUI_GROUP) |= LCT_WUI_MASK;
 	task_enable_irq(NPCX_IRQ_LCT_WKINTF_2);
 #endif
 	npcx_lct_enable(1);
@@ -609,24 +628,51 @@ void __enter_hibernate(uint32_t seconds, uint32_t microseconds)
 		board_hibernate_late();
 
 	/* Clear all pending IRQ otherwise wfi will have no affect */
-	for (i = NPCX_IRQ_0 ; i < NPCX_IRQ_COUNT ; i++)
+	for (i = NPCX_IRQ_0; i < NPCX_IRQ_COUNT; i++)
 		task_clear_pending_irq(i);
 
-	/*
-	 * Set RTC interrupt in time to wake up before
-	 * next event.
-	 */
-	if (seconds || microseconds)
+		/* Set the timer interrupt for wake up.  */
 #ifdef NPCX_LCT_SUPPORT
+	if (seconds || microseconds) {
 		system_set_lct_alarm(seconds, microseconds);
+	} else if (IS_ENABLED(CONFIG_HIBERNATE_PSL_COMPENSATE_RTC)) {
+		system_set_lct_alarm(NPCX_LCT_MAX, 0);
+	}
 #else
+	if (seconds || microseconds)
 		system_set_rtc_alarm(seconds, microseconds);
 #endif
 
 	/* execute hibernate func depend on chip series */
 	__hibernate_npcx_series();
+}
+
+#ifdef CONFIG_HIBERNATE_PSL_COMPENSATE_RTC
+#ifndef NPCX_LCT_SUPPORT
+#error "Do not enable CONFIG_HIBERNATE_PSL_COMPENSATE_RTC if npcx ec doesn't \
+support LCT!"
+#endif
+/*
+ * The function uses the LCT counter value to compensate for RTC after hibernate
+ * wake-up. Because system_set_rtc() will invoke udelay(), the function should
+ * execute after timer_init(). The function also should execute before
+ * npcx_lct_init() which will clear all LCT register.
+ */
+void system_compensate_rtc(void)
+{
+	uint32_t rtc_time, ltc_start_time;
+
+	ltc_start_time = bbram_data_read(BBRM_DATA_INDEX_LCT_TIME);
+	if (ltc_start_time == 0)
+		return;
 
+	rtc_time = system_get_rtc_sec();
+	rtc_time += ltc_start_time - npcx_lct_get_time();
+	system_set_rtc(rtc_time);
+	/* Clear BBRAM data to avoid compensating again. */
+	bbram_data_write(BBRM_DATA_INDEX_LCT_TIME, 0);
 }
+#endif
 #endif /* CONFIG_SUPPORT_CHIP_HIBERNATION */
 
 static char system_to_hex(uint8_t val)
@@ -680,9 +726,9 @@ void system_set_rtc_alarm(uint32_t seconds, uint32_t microseconds)
 	task_enable_irq(NPCX_IRQ_MTC);
 
 	/* Enable wake-up input sources & clear pending bit */
-	NPCX_WKPCL(MIWU_TABLE_0, MTC_WUI_GROUP)  |= MTC_WUI_MASK;
+	NPCX_WKPCL(MIWU_TABLE_0, MTC_WUI_GROUP) |= MTC_WUI_MASK;
 	NPCX_WKINEN(MIWU_TABLE_0, MTC_WUI_GROUP) |= MTC_WUI_MASK;
-	NPCX_WKEN(MIWU_TABLE_0, MTC_WUI_GROUP)   |= MTC_WUI_MASK;
+	NPCX_WKEN(MIWU_TABLE_0, MTC_WUI_GROUP) |= MTC_WUI_MASK;
 }
 
 void system_reset_rtc_alarm(void)
@@ -739,6 +785,22 @@ void system_hibernate(uint32_t seconds, uint32_t microseconds)
 #endif
 }
 
+#ifndef CONFIG_ENABLE_JTAG_SELECTION
+static void system_disable_host_sel_jtag(void)
+{
+	int data;
+
+	/* Enable Core-to-Host Modules Access */
+	SET_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSAE);
+	/* Clear SIOCFD.JEN0_HSL to disable JTAG0 */
+	data = sib_read_reg(SIO_OFFSET, SIOCFD_REG_OFFSET);
+	data &= ~0x80;
+	sib_write_reg(SIO_OFFSET, SIOCFD_REG_OFFSET, data);
+	/* Disable Core-to-Host Modules Access */
+	CLEAR_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSAE);
+}
+#endif
+
 void chip_pre_init(void)
 {
 	/* Setting for fixing JTAG issue */
@@ -765,21 +827,21 @@ void chip_pre_init(void)
 	 * This is the workaround to disable the JTAG0 which is enabled
 	 * accidentally by a special key combination.
 	 */
+#if NPCX_FAMILY_VERSION < NPCX_FAMILY_NPCX9
 	if (!IS_BIT_SET(NPCX_DEVALT(5), NPCX_DEVALT5_NJEN0_EN)) {
-		int data;
 		/* Set DEVALT5.nJEN0_EN to disable JTAG0 */
 		SET_BIT(NPCX_DEVALT(5), NPCX_DEVALT5_NJEN0_EN);
-		/* Enable Core-to-Host Modules Access */
-		SET_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSAE);
-		/* Clear SIOCFD.JEN0_HSL to disable JTAG0 */
-		data = sib_read_reg(SIO_OFFSET, 0x2D);
-		data &= ~0x80;
-		sib_write_reg(SIO_OFFSET, 0x2D, data);
-		/* Disable Core-to-Host Modules Access */
-		CLEAR_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSAE);
+		system_disable_host_sel_jtag();
+	}
+#else
+	if (GET_FIELD(NPCX_JEN_CTL1, NPCX_JEN_CTL1_JEN_EN_FIELD) ==
+	    NPCX_JEN_CTL1_JEN_EN_ENA) {
+		SET_FIELD(NPCX_JEN_CTL1, NPCX_JEN_CTL1_JEN_EN_FIELD,
+			  NPCX_JEN_CTL1_JEN_EN_DIS);
+		system_disable_host_sel_jtag();
 	}
 #endif
-
+#endif
 }
 
 void system_pre_init(void)
@@ -791,42 +853,52 @@ void system_pre_init(void)
 	 * EC should be initialized in Booter
 	 */
 
-	/* Power-down the modules we don't need */
-	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_1) = 0xF9; /* Skip SDP_PD FIU_PD */
+	/* Power down KBS, SDP, PS2, UART1, and MFT1-3 */
+	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_1) = 0xFB;
+	/* Power down PWM0-7 */
 	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_2) = 0xFF;
 #if defined(CHIP_FAMILY_NPCX5)
-	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_3) = 0x0F; /* Skip GDMA */
+	/* Power down SMB0-3 */
+	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_3) = 0x0F;
 #elif NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_3) = 0x3F; /* Skip GDMA */
+	/* Power down SMB0-4 */
+	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_3) = 0x3F;
 #endif
-	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_4) = 0xF4; /* Skip ITIM2/1_PD */
+	/* Power down ITIM3, ADC, PECI, SPIP */
+	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_4) = 0xF4;
+	/* Power down C2HACC, SHM_REG, SHM, Port80, and MSWC */
 	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_5) = 0xF8;
 
 	pwdwn6 = 0x70 |
 #if NPCX_FAMILY_VERSION <= NPCX_FAMILY_NPCX7
-		/*
-		 * Don't set PD of ITIM6 for NPCX9 and later chips because
-		 * they use it as the system timer.
-		 */
-		BIT(NPCX_PWDWN_CTL6_ITIM6_PD) |
+		 /*
+		  * Don't set PD of ITIM6 for NPCX9 and later chips because
+		  * they use it as the system timer.
+		  */
+		 BIT(NPCX_PWDWN_CTL6_ITIM6_PD) |
 #endif
-		BIT(NPCX_PWDWN_CTL6_ITIM4_PD); /* Skip ITIM5_PD */
-#if !defined(CONFIG_HOSTCMD_ESPI)
+		 BIT(NPCX_PWDWN_CTL6_ITIM4_PD);
+#if !defined(CONFIG_HOST_INTERFACE_ESPI)
 	pwdwn6 |= 1 << NPCX_PWDWN_CTL6_ESPI_PD;
 #endif
 	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_6) = pwdwn6;
 
 #if defined(CHIP_FAMILY_NPCX7)
-#if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) || \
+#if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) ||     \
 	defined(CHIP_VARIANT_NPCX7M7FC) || defined(CHIP_VARIANT_NPCX7M7WB) || \
 	defined(CHIP_VARIANT_NPCX7M7WC)
+	/* Power down UART2, SMB5-7, ITIM64, and WoV */
 	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_7) = 0xE7;
 #else
+	/* Power down SMB5-7 */
 	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_7) = 0x07;
 #endif
 #endif
 #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
+	/* Power down UART2-4, SMB5-7, and ITIM64 */
 	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_7) = 0xFF;
+	/* Power down I3C */
+	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_8) = PWDWN_8_RESERVED_SET_MASK | 0x01;
 #endif
 
 	/* Following modules can be powered down automatically in npcx7 */
@@ -877,34 +949,34 @@ void system_pre_init(void)
 			 * hibernation.
 			 */
 			SET_BIT(NPCX_GLUE_PSL_MCTL1,
-					NPCX_GLUE_PSL_MCTL1_VCC1_RST_PSL);
+				NPCX_GLUE_PSL_MCTL1_VCC1_RST_PSL);
 			/* Disable VCC_RST Pull-Up */
 			SET_BIT(NPCX_DEVALT(ALT_GROUP_G),
-					NPCX_DEVALTG_VCC1_RST_PUD);
+				NPCX_DEVALTG_VCC1_RST_PUD);
 			/*
 			 * Lock this bit itself and VCC1_RST_PSL in the
 			 * PSL_MCTL1 register to read-only.
 			 */
 			SET_BIT(NPCX_GLUE_PSL_MCTL2,
-					NPCX_GLUE_PSL_MCTL2_VCC1_RST_PSL_LK);
+				NPCX_GLUE_PSL_MCTL2_VCC1_RST_PSL_LK);
 		}
 
 		/* Don't set PSL_OUT to open-drain if it is the level mode */
 		ASSERT((opt_flag & NPCX_PSL_CFG_PSL_OUT_PULSE) ||
-			 !(opt_flag & NPCX_PSL_CFG_PSL_OUT_OD));
+		       !(opt_flag & NPCX_PSL_CFG_PSL_OUT_OD));
 
 		if (opt_flag & NPCX_PSL_CFG_PSL_OUT_OD)
 			SET_BIT(NPCX_GLUE_PSL_MCTL1, NPCX_GLUE_PSL_MCTL1_OD_EN);
 		else
 			CLEAR_BIT(NPCX_GLUE_PSL_MCTL1,
-					NPCX_GLUE_PSL_MCTL1_OD_EN);
+				  NPCX_GLUE_PSL_MCTL1_OD_EN);
 
 		if (opt_flag & NPCX_PSL_CFG_PSL_OUT_PULSE)
 			SET_BIT(NPCX_GLUE_PSL_MCTL1,
-					NPCX_GLUE_PSL_MCTL1_PLS_EN);
+				NPCX_GLUE_PSL_MCTL1_PLS_EN);
 		else
 			CLEAR_BIT(NPCX_GLUE_PSL_MCTL1,
-					NPCX_GLUE_PSL_MCTL1_PLS_EN);
+				  NPCX_GLUE_PSL_MCTL1_PLS_EN);
 	}
 #endif
 }
@@ -955,7 +1027,7 @@ const char *system_get_chip_vendor(void)
 	case 0x20:
 		return "Nuvoton";
 	default:
-		*p       = system_to_hex(fam_id >> 4);
+		*p = system_to_hex(fam_id >> 4);
 		*(p + 1) = system_to_hex(fam_id);
 		*(p + 2) = '\0';
 		return str;
@@ -998,7 +1070,7 @@ const char *system_get_chip_name(void)
 		return "NPCX993F";
 #endif
 	default:
-		*p       = system_to_hex(chip_id >> 4);
+		*p = system_to_hex(chip_id >> 4);
 		*(p + 1) = system_to_hex(chip_id);
 		*(p + 2) = '\0';
 		return str;
@@ -1021,6 +1093,7 @@ const char *system_get_chip_revision(void)
 #ifdef CHIP_FAMILY_NPCX7
 	uint8_t chip_id = NPCX_DEVICE_ID_CR;
 #endif
+	int s;
 
 	switch (chip_gen) {
 #if defined(CHIP_FAMILY_NPCX5)
@@ -1033,7 +1106,7 @@ const char *system_get_chip_revision(void)
 		break;
 	case 0x07:
 		if (chip_id == NPCX796F_A_B_CHIP_ID ||
-			chip_id == NPCX797W_B_CHIP_ID)
+		    chip_id == NPCX797W_B_CHIP_ID)
 			*p++ = 'B';
 		else
 			*p++ = 'C';
@@ -1054,7 +1127,7 @@ const char *system_get_chip_revision(void)
 	 * For npcx5/npcx7, the revision number is 1 byte.
 	 * For NPCX9 and later chips, the revision number is 4 bytes.
 	 */
-	for (int s = sizeof(rev_num) - 1; s >= 0; s--) {
+	for (s = sizeof(rev_num) - 1; s >= 0; s--) {
 		uint8_t r = rev_num >> (s * 8);
 
 		*p++ = system_to_hex(r >> 4);
@@ -1065,8 +1138,6 @@ const char *system_get_chip_revision(void)
 	return rev;
 }
 
-BUILD_ASSERT(BBRM_DATA_INDEX_VBNVCNTXT + EC_VBNV_BLOCK_SIZE <= NPCX_BBRAM_SIZE);
-
 /**
  * Set a scratchpad register to the specified value.
  *
@@ -1081,9 +1152,10 @@ int system_set_scratchpad(uint32_t value)
 	return bbram_data_write(BBRM_DATA_INDEX_SCRATCHPAD, value);
 }
 
-uint32_t system_get_scratchpad(void)
+int system_get_scratchpad(uint32_t *value)
 {
-	return bbram_data_read(BBRM_DATA_INDEX_SCRATCHPAD);
+	*value = bbram_data_read(BBRM_DATA_INDEX_SCRATCHPAD);
+	return EC_SUCCESS;
 }
 
 int system_is_reboot_warm(void)
@@ -1108,6 +1180,23 @@ int system_is_reboot_warm(void)
 		return 1;
 }
 
+#if defined(CONFIG_HIBERNATE_PSL) && defined(NPCX_LCT_SUPPORT)
+static void system_init_check_rtc_wakeup_event(void)
+{
+	/*
+	 * If platform uses PSL (Power Switch Logic) for hibernating and RTC is
+	 * also supported, determine whether ec is woken up by RTC with overflow
+	 * event (16 weeks). If so, let it go to hibernate mode immediately.
+	 */
+	if (is_rtc_overflow_event) {
+		CPRINTS("Hibernate due to RTC overflow event");
+		system_hibernate(0, 0);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, system_init_check_rtc_wakeup_event,
+	     HOOK_PRIO_DEFAULT - 1);
+#endif
+
 /*****************************************************************************/
 /* Console commands */
 void print_system_rtc(enum console_channel ch)
@@ -1118,7 +1207,7 @@ void print_system_rtc(enum console_channel ch)
 }
 
 #ifdef CONFIG_CMD_RTC
-static int command_system_rtc(int argc, char **argv)
+static int command_system_rtc(int argc, const char **argv)
 {
 	if (argc == 3 && !strcasecmp(argv[1], "set")) {
 		char *e;
@@ -1135,15 +1224,14 @@ static int command_system_rtc(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(rtc, command_system_rtc,
-		"[set <seconds>]",
-		"Get/set real-time clock");
+DECLARE_CONSOLE_COMMAND(rtc, command_system_rtc, "[set <seconds>]",
+			"Get/set real-time clock");
 
 #ifdef CONFIG_CMD_RTC_ALARM
 /**
  * Test the RTC alarm by setting an interrupt on RTC match.
  */
-static int command_rtc_alarm_test(int argc, char **argv)
+static int command_rtc_alarm_test(int argc, const char **argv)
 {
 	int s = 1, us = 0;
 	char *e;
@@ -1155,13 +1243,11 @@ static int command_rtc_alarm_test(int argc, char **argv)
 		s = strtoi(argv[1], &e, 10);
 		if (*e)
 			return EC_ERROR_PARAM1;
-
 	}
 	if (argc > 2) {
 		us = strtoi(argv[2], &e, 10);
 		if (*e)
 			return EC_ERROR_PARAM2;
-
 	}
 
 	system_set_rtc_alarm(s, us);
@@ -1169,8 +1255,7 @@ static int command_rtc_alarm_test(int argc, char **argv)
 	return EC_SUCCESS;
 }
 DECLARE_CONSOLE_COMMAND(rtc_alarm, command_rtc_alarm_test,
-		"[seconds [microseconds]]",
-		"Test alarm");
+			"[seconds [microseconds]]", "Test alarm");
 #endif /* CONFIG_CMD_RTC_ALARM */
 #endif /* CONFIG_CMD_RTC */
 
@@ -1187,9 +1272,8 @@ static enum ec_status system_rtc_get_value(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_VALUE,
-		system_rtc_get_value,
-		EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_VALUE, system_rtc_get_value,
+		     EC_VER_MASK(0));
 
 static enum ec_status system_rtc_set_value(struct host_cmd_handler_args *args)
 {
@@ -1198,9 +1282,8 @@ static enum ec_status system_rtc_set_value(struct host_cmd_handler_args *args)
 	system_set_rtc(p->time);
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_VALUE,
-		system_rtc_set_value,
-		EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_VALUE, system_rtc_set_value,
+		     EC_VER_MASK(0));
 
 static enum ec_status system_rtc_set_alarm(struct host_cmd_handler_args *args)
 {
@@ -1209,9 +1292,8 @@ static enum ec_status system_rtc_set_alarm(struct host_cmd_handler_args *args)
 	system_set_rtc_alarm(p->time, 0);
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_ALARM,
-		system_rtc_set_alarm,
-		EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_ALARM, system_rtc_set_alarm,
+		     EC_VER_MASK(0));
 
 static enum ec_status system_rtc_get_alarm(struct host_cmd_handler_args *args)
 {
@@ -1222,9 +1304,8 @@ static enum ec_status system_rtc_get_alarm(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_ALARM,
-		system_rtc_get_alarm,
-		EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_ALARM, system_rtc_get_alarm,
+		     EC_VER_MASK(0));
 
 #endif /* CONFIG_HOSTCMD_RTC */
 #ifdef CONFIG_EXTERNAL_STORAGE
@@ -1241,28 +1322,28 @@ void system_jump_to_booter(void)
 	 */
 	switch (system_get_shrspi_image_copy()) {
 	case EC_IMAGE_RW:
-		flash_offset = CONFIG_EC_WRITABLE_STORAGE_OFF +
-				CONFIG_RW_STORAGE_OFF;
+		flash_offset =
+			CONFIG_EC_WRITABLE_STORAGE_OFF + CONFIG_RW_STORAGE_OFF;
 		flash_used = CONFIG_RW_SIZE;
 		break;
 #ifdef CONFIG_RW_B
 	case EC_IMAGE_RW_B:
 		flash_offset = CONFIG_EC_WRITABLE_STORAGE_OFF +
-				CONFIG_RW_B_STORAGE_OFF;
+			       CONFIG_RW_B_STORAGE_OFF;
 		flash_used = CONFIG_RW_SIZE;
 		break;
 #endif
 	case EC_IMAGE_RO:
 	default: /* Jump to RO by default */
-		flash_offset = CONFIG_EC_PROTECTED_STORAGE_OFF +
-				CONFIG_RO_STORAGE_OFF;
+		flash_offset =
+			CONFIG_EC_PROTECTED_STORAGE_OFF + CONFIG_RO_STORAGE_OFF;
 		flash_used = CONFIG_RO_SIZE;
 		break;
 	}
 
 	/* Make sure the reset vector is inside the destination image */
-	addr_entry = *(uintptr_t *)(flash_offset +
-				    CONFIG_MAPPED_STORAGE_BASE + 4);
+	addr_entry =
+		*(uintptr_t *)(flash_offset + CONFIG_MAPPED_STORAGE_BASE + 4);
 
 	/*
 	 * Speed up FW download time by increasing clock freq of EC. It will
@@ -1270,33 +1351,32 @@ void system_jump_to_booter(void)
 	 */
 	clock_turbo();
 
-/*
- * npcx9 Rev.1 has the problem for download_from_flash API.
- * Workwaroud it by executing the system_download_from_flash function
- * in the suspend RAM like npcx5.
- * TODO: Removing npcx9 when Rev.2 is available.
- */
 	/* Bypass for GMDA issue of ROM api utilities */
-#if defined(CHIP_FAMILY_NPCX5) || defined(CONFIG_WORKAROUND_FLASH_DOWNLOAD_API)
-	system_download_from_flash(
-		flash_offset,      /* The offset of the data in spi flash */
-		CONFIG_PROGRAM_MEMORY_BASE, /* RAM Addr of downloaded data */
-		flash_used,        /* Number of bytes to download      */
-		addr_entry         /* jump to this address after download */
+#if defined(CHIP_FAMILY_NPCX5)
+	system_download_from_flash(flash_offset, /* The offset of the data in
+						    spi flash */
+				   CONFIG_PROGRAM_MEMORY_BASE, /* RAM Addr of
+								  downloaded
+								  data */
+				   flash_used, /* Number of bytes to download */
+				   addr_entry /* jump to this address after
+						 download */
 	);
 #else
-	download_from_flash(
-		flash_offset,      /* The offset of the data in spi flash */
-		CONFIG_PROGRAM_MEMORY_BASE, /* RAM Addr of downloaded data */
-		flash_used,        /* Number of bytes to download      */
-		SIGN_NO_CHECK,     /* Need CRC check or not               */
-		addr_entry,        /* jump to this address after download */
-		&status            /* Status fo download */
+	download_from_flash(flash_offset, /* The offset of the data in spi flash
+					   */
+			    CONFIG_PROGRAM_MEMORY_BASE, /* RAM Addr of
+							   downloaded data */
+			    flash_used, /* Number of bytes to download      */
+			    SIGN_NO_CHECK, /* Need CRC check or not */
+			    addr_entry, /* jump to this address after download
+					 */
+			    &status /* Status fo download */
 	);
 #endif
 }
 
-uint32_t system_get_lfw_address()
+uint32_t system_get_lfw_address(void)
 {
 	/*
 	 * In A3 version, we don't use little FW anymore
@@ -1327,8 +1407,10 @@ void system_set_image_copy(enum ec_image copy)
 #endif
 	default:
 		CPRINTS("Invalid copy (%d) is requested as a jump destination. "
-			"Change it to %d.", copy, EC_IMAGE_RO);
+			"Change it to %d.",
+			copy, EC_IMAGE_RO);
 		/* Fall through to EC_IMAGE_RO */
+		__fallthrough;
 	case EC_IMAGE_RO:
 		SET_BIT(NPCX_FWCTRL, NPCX_FWCTRL_RO_REGION);
 		SET_BIT(NPCX_FWCTRL, NPCX_FWCTRL_FW_SLOT);
diff --git a/chip/npcx/system_chip.h b/chip/npcx/system_chip.h
index c084cd04a6..2ee5f8aff0 100644
--- a/chip/npcx/system_chip.h
+++ b/chip/npcx/system_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,32 +9,34 @@
 #define __CROS_EC_SYSTEM_CHIP_H
 
 /* Flags for BBRM_DATA_INDEX_WAKE */
-#define HIBERNATE_WAKE_MTC        BIT(0)  /* MTC alarm */
-#define HIBERNATE_WAKE_PIN        BIT(1)  /* Wake pin */
-#define HIBERNATE_WAKE_LCT        BIT(2)  /* LCT alarm */
+#define HIBERNATE_WAKE_MTC BIT(0) /* MTC alarm */
+#define HIBERNATE_WAKE_PIN BIT(1) /* Wake pin */
+#define HIBERNATE_WAKE_LCT BIT(2) /* LCT alarm */
 /*
  * Indicate that EC enters hibernation via PSL. When EC wakes up from
  * hibernation and this flag is set, it will check the related status bit to
  * know the actual wake up source. (From LCT or physical wakeup pins)
  */
-#define HIBERNATE_WAKE_PSL        BIT(3)
+#define HIBERNATE_WAKE_PSL BIT(3)
 
 /* Indices for battery-backed ram (BBRAM) data position */
 enum bbram_data_index {
-	BBRM_DATA_INDEX_SCRATCHPAD = 0,        /* General-purpose scratchpad */
+	BBRM_DATA_INDEX_SCRATCHPAD = 0, /* General-purpose scratchpad */
 	BBRM_DATA_INDEX_SAVED_RESET_FLAGS = 4, /* Saved reset flags */
-	BBRM_DATA_INDEX_WAKE = 8,	       /* Wake reasons for hibernate */
-	BBRM_DATA_INDEX_PD0 = 12,	       /* USB-PD saved port0 state */
-	BBRM_DATA_INDEX_PD1 = 13,	       /* USB-PD saved port1 state */
-	BBRM_DATA_INDEX_TRY_SLOT = 14,         /* Vboot EC try slot */
-	BBRM_DATA_INDEX_PD2 = 15,	       /* USB-PD saved port2 state */
-	BBRM_DATA_INDEX_VBNVCNTXT = 16,	       /* VbNvContext for ARM arch */
-	BBRM_DATA_INDEX_RAMLOG = 32,	       /* RAM log for Booter */
-	BBRM_DATA_INDEX_PANIC_FLAGS = 35,      /* Flag to indicate validity of
-						* panic data starting at index
-						* 36.
-						*/
-	BBRM_DATA_INDEX_PANIC_BKUP = 36,       /* Panic data (index 35-63)*/
+	BBRM_DATA_INDEX_WAKE = 8, /* Wake reasons for hibernate */
+	BBRM_DATA_INDEX_PD0 = 12, /* USB-PD saved port0 state */
+	BBRM_DATA_INDEX_PD1 = 13, /* USB-PD saved port1 state */
+	BBRM_DATA_INDEX_TRY_SLOT = 14, /* Vboot EC try slot */
+	BBRM_DATA_INDEX_PD2 = 15, /* USB-PD saved port2 state */
+	/* Index 16-31 available for future use */
+	BBRM_DATA_INDEX_RAMLOG = 32, /* RAM log for Booter */
+	BBRM_DATA_INDEX_PANIC_FLAGS = 35, /* Flag to indicate validity of
+					   * panic data starting at index
+					   * 36.
+					   */
+	BBRM_DATA_INDEX_PANIC_BKUP = 36, /* Panic data (index 35-63)*/
+	BBRM_DATA_INDEX_LCT_TIME = 64, /* The start time of LCT(4 bytes)
+					*/
 };
 
 enum psl_pin_t {
@@ -64,10 +66,10 @@ void __hibernate_npcx_series(void);
 void system_check_bbram_on_reset(void);
 
 /* The utilities and variables depend on npcx chip family */
-#if defined(CHIP_FAMILY_NPCX5) || defined(CONFIG_WORKAROUND_FLASH_DOWNLOAD_API)
+#if defined(CHIP_FAMILY_NPCX5)
 /* Bypass for GMDA issue of ROM api utilities only on npcx5 series */
 void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr,
-		uint32_t size, uint32_t exeAddr);
+				uint32_t size, uint32_t exeAddr);
 
 /* Begin address for hibernate utility; defined in linker script */
 extern unsigned int __flash_lpfw_start;
diff --git a/chip/npcx/trng.c b/chip/npcx/trng.c
new file mode 100644
index 0000000000..a2d7920c14
--- /dev/null
+++ b/chip/npcx/trng.c
@@ -0,0 +1,251 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Hardware Random Number Generator */
+
+#include "common.h"
+#include "console.h"
+#include "host_command.h"
+#include "panic.h"
+#include "printf.h"
+#include "registers.h"
+#include "system.h"
+#include "task.h"
+#include "trng.h"
+#include "util.h"
+
+#define DRBG_CONTEXT_SIZE 240
+
+struct drbg_ctx {
+	union {
+		uint8_t buffer[DRBG_CONTEXT_SIZE];
+		uint32_t buffer32[DRBG_CONTEXT_SIZE / 4];
+		uint64_t buffer64[DRBG_CONTEXT_SIZE / 8];
+	};
+} __aligned(16);
+
+struct drbg_ctx ctx;
+struct drbg_ctx *ctx_p = &ctx;
+
+enum ncl_status {
+	NCL_STATUS_OK = 0xA5A5,
+	NCL_STATUS_FAIL = 0x5A5A,
+	NCL_STATUS_INVALID_PARAM = 0x02,
+	NCL_STATUS_PARAM_NOT_SUPPORTED,
+	NCL_STATUS_SYSTEM_BUSY,
+	NCL_STATUS_AUTHENTICATION_FAIL,
+	NCL_STATUS_NO_RESPONSE,
+	NCL_STATUS_HARDWARE_ERROR,
+};
+
+/*
+ * This enum defines the security strengths supported by this DRBG mechanism.
+ * The internally generated entropy and nonce sizes are derived from these
+ * values. The supported actual sizes:
+ *       Security strength (bits)    112 128 192 256 128_Test 256_Test
+ *
+ *       Entropy size (Bytes)        32  48  64  96  111      128
+ *       Nonce size (Bytes)          16  16  24  32  16       0
+ */
+enum ncl_drbg_security_strength {
+	NCL_DRBG_SECURITY_STRENGTH_112b = 0,
+	NCL_DRBG_SECURITY_STRENGTH_128b,
+	NCL_DRBG_SECURITY_STRENGTH_192b,
+	NCL_DRBG_SECURITY_STRENGTH_256b,
+	NCL_DRBG_SECURITY_STRENGTH_128b_TEST,
+	NCL_DRBG_SECURITY_STRENGTH_256b_TEST,
+	NCL_DRBG_MAX_SECURITY_STRENGTH
+};
+
+/* The actual base address is 13C but we only need the SHA power function */
+#define NCL_SHA_BASE_ADDR 0x0000015CUL
+struct ncl_sha {
+	/* Power on/off SHA module. */
+	enum ncl_status (*power)(void *ctx, uint8_t on);
+};
+#define NCL_SHA ((const struct ncl_sha *)NCL_SHA_BASE_ADDR)
+
+/*
+ * The base address of the table that holds the function pointer for each
+ * DRBG API in ROM.
+ */
+#define NCL_DRBG_BASE_ADDR 0x00000110UL
+struct ncl_drbg {
+	/* Get the DRBG context size required by DRBG APIs. */
+	uint32_t (*get_context_size)(void);
+	/* Initialize DRBG context. */
+	enum ncl_status (*init_context)(void *ctx);
+	/* Power on/off DRBG module. */
+	enum ncl_status (*power)(void *ctx, uint8_t on);
+	/* Finalize DRBG context. */
+	enum ncl_status (*finalize_context)(void *ctx);
+	/* Initialize the DRBG hardware module and enable interrupts. */
+	enum ncl_status (*init)(void *ctx, bool int_enable);
+	/*
+	 * Configure DRBG, pres_resistance enables/disables (1/0) prediction
+	 * resistance
+	 */
+	enum ncl_status (*config)(void *ctx, uint32_t reseed_interval,
+				  uint8_t pred_resistance);
+	/*
+	 * This routine creates a first instantiation of the DRBG mechanism
+	 * parameters. The routine pulls an initial seed from the HW RNG module
+	 * and resets the reseed counter. DRBG and SHA modules should be
+	 * activated prior to the this operation.
+	 */
+	enum ncl_status (*instantiate)(
+		void *ctx, enum ncl_drbg_security_strength sec_strength,
+		const uint8_t *pers_string, uint32_t pers_string_len);
+	/* Uninstantiate DRBG module */
+	enum ncl_status (*uninstantiate)(void *ctx);
+	/* Reseeds the internal state of the given instantce */
+	enum ncl_status (*reseed)(void *ctc, uint8_t *add_data,
+				  uint32_t add_data_len);
+	/* Generates a random number from the current internal state. */
+	enum ncl_status (*generate)(void *ctx, const uint8_t *add_data,
+				    uint32_t add_data_len, uint8_t *out_buff,
+				    uint32_t out_buff_len);
+	/* Clear all DRBG SSPs (Sensitive Security Parameters) in HW & driver */
+	enum ncl_status (*clear)(void *ctx);
+};
+#define NCL_DRBG ((const struct ncl_drbg *)NCL_DRBG_BASE_ADDR)
+
+struct npcx_trng_state {
+	enum ncl_status trng_init;
+};
+struct npcx_trng_state trng_state;
+struct npcx_trng_state *state_p = &trng_state;
+
+test_mockable void trng_init(void)
+{
+#ifndef CHIP_VARIANT_NPCX9M8S
+#error "Please add support for CONFIG_RNG on this chip family."
+#endif
+
+	uint32_t context_size = 0;
+
+	state_p->trng_init = NCL_STATUS_FAIL;
+
+	context_size = NCL_DRBG->get_context_size();
+	if (context_size != DRBG_CONTEXT_SIZE)
+		ccprintf("ERROR! Unexpected NCL DRBG context_size = %d\n",
+			 context_size);
+
+	state_p->trng_init = NCL_DRBG->power(ctx_p, true);
+	if (state_p->trng_init != NCL_STATUS_OK) {
+		ccprintf("ERROR! DRBG power returned %x\n", state_p->trng_init);
+		return;
+	}
+
+	state_p->trng_init = NCL_SHA->power(ctx_p, true);
+	if (state_p->trng_init != NCL_STATUS_OK) {
+		ccprintf("ERROR! SHA power returned %x\n", state_p->trng_init);
+		return;
+	}
+
+	state_p->trng_init = NCL_DRBG->init_context(ctx_p);
+	if (state_p->trng_init != NCL_STATUS_OK) {
+		ccprintf("ERROR! DRBG init_context returned %x\r",
+			 state_p->trng_init);
+		return;
+	}
+
+	state_p->trng_init = NCL_DRBG->init(ctx_p, 0);
+	if (state_p->trng_init != NCL_STATUS_OK) {
+		ccprintf("ERROR! DRBG init returned %x\r", state_p->trng_init);
+		return;
+	}
+
+	state_p->trng_init = NCL_DRBG->config(ctx_p, 100, false);
+	if (state_p->trng_init != NCL_STATUS_OK) {
+		ccprintf("ERROR! DRBG config returned %x\r",
+			 state_p->trng_init);
+		return;
+	}
+
+	state_p->trng_init = NCL_DRBG->instantiate(
+		ctx_p, NCL_DRBG_SECURITY_STRENGTH_128b, NULL, 0);
+	if (state_p->trng_init != NCL_STATUS_OK) {
+		ccprintf("ERROR! DRBG instantiate returned %x\r",
+			 state_p->trng_init);
+		return;
+	}
+
+	state_p->trng_init = NCL_DRBG->power(ctx_p, false);
+	if (state_p->trng_init != NCL_STATUS_OK) {
+		ccprintf("ERROR! DRBG power returned %x\n", state_p->trng_init);
+		return;
+	}
+
+	state_p->trng_init = NCL_SHA->power(ctx_p, false);
+	if (state_p->trng_init != NCL_STATUS_OK) {
+		ccprintf("ERROR! SHA power returned %x\n", state_p->trng_init);
+		return;
+	}
+}
+
+uint32_t trng_rand(void)
+{
+	uint32_t return_value;
+	enum ncl_status status = NCL_STATUS_FAIL;
+
+	/* Don't attempt generate and panic if initialization failed */
+	if (state_p->trng_init != NCL_STATUS_OK)
+		software_panic(PANIC_SW_BAD_RNG, task_get_current());
+
+	status = NCL_DRBG->power(ctx_p, true);
+	if (status != NCL_STATUS_OK) {
+		ccprintf("ERROR! DRBG power returned %x\n", status);
+		software_panic(PANIC_SW_BAD_RNG, task_get_current());
+	}
+
+	status = NCL_SHA->power(ctx_p, true);
+	if (status != NCL_STATUS_OK) {
+		ccprintf("ERROR! SHA power returned %x\n", status);
+		software_panic(PANIC_SW_BAD_RNG, task_get_current());
+	}
+
+	status = NCL_DRBG->generate(NULL, NULL, 0, (uint8_t *)&return_value, 4);
+	if (status != NCL_STATUS_OK) {
+		ccprintf("ERROR! DRBG generate returned %x\r", status);
+		software_panic(PANIC_SW_BAD_RNG, task_get_current());
+	}
+
+	/*
+	 * Failing to turn off the blocks has power implications but wouldn't
+	 * result in feeding the caller a bad result, hence no panics enabled
+	 * for failing to turn off the hardware
+	 */
+	status = NCL_DRBG->power(ctx_p, false);
+	if (status != NCL_STATUS_OK)
+		ccprintf("ERROR! DRBG power returned %x\n", status);
+
+	status = NCL_SHA->power(ctx_p, false);
+	if (status != NCL_STATUS_OK)
+		ccprintf("ERROR! SHA power returned %x\n", status);
+
+	return return_value;
+}
+
+test_mockable void trng_exit(void)
+{
+	enum ncl_status status = NCL_STATUS_FAIL;
+
+	status = NCL_DRBG->clear(ctx_p);
+	if (status != NCL_STATUS_OK)
+		ccprintf("ERROR! DRBG clear returned %x\r", status);
+
+	status = NCL_DRBG->uninstantiate(ctx_p);
+	if (status != NCL_STATUS_OK)
+		ccprintf("ERROR! DRBG uninstantiate returned %x\r", status);
+
+	status = NCL_DRBG->power(ctx_p, false);
+	if (status != NCL_STATUS_OK)
+		ccprintf("ERROR! DRBG power returned %x\n", status);
+
+	status = NCL_SHA->power(ctx_p, false);
+	if (status != NCL_STATUS_OK)
+		ccprintf("ERROR! SHA power returned %x\n", status);
+}
diff --git a/chip/npcx/uart.c b/chip/npcx/uart.c
index efe991ec0b..d77c3579c5 100644
--- a/chip/npcx/uart.c
+++ b/chip/npcx/uart.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,6 +6,7 @@
 /* UART module for Chrome EC */
 
 #include "clock.h"
+#include "clock_chip.h"
 #include "common.h"
 #include "console.h"
 #include "gpio.h"
@@ -13,7 +14,6 @@
 #include "hwtimer_chip.h"
 #include "lpc.h"
 #include "registers.h"
-#include "clock_chip.h"
 #include "system.h"
 #include "task.h"
 #include "timer.h"
@@ -21,12 +21,12 @@
 #include "uartn.h"
 #include "util.h"
 
-#define CONSOLE_UART            CONFIG_CONSOLE_UART
+#define CONSOLE_UART CONFIG_CONSOLE_UART
 
 #if CONSOLE_UART
-#define CONSOLE_UART_IRQ        NPCX_IRQ_UART2
+#define CONSOLE_UART_IRQ NPCX_IRQ_UART2
 #else
-#define CONSOLE_UART_IRQ        NPCX_IRQ_UART
+#define CONSOLE_UART_IRQ NPCX_IRQ_UART
 #endif
 
 static int init_done;
@@ -54,7 +54,7 @@ static int altpad_tx_len;
  */
 static timestamp_t last_default_pad_rx_time;
 
-static const uint32_t block_alt_timeout_us = 500*MSEC;
+static const uint32_t block_alt_timeout_us = 500 * MSEC;
 
 #else
 
@@ -197,7 +197,7 @@ int uart_read_char(void)
 }
 
 /* Interrupt handler for Console UART */
-void uart_ec_interrupt(void)
+static void uart_ec_interrupt(void)
 {
 #ifdef CONFIG_UART_PAD_SWITCH
 	if (pad == UART_ALTERNATE_PAD) {
@@ -209,7 +209,8 @@ void uart_ec_interrupt(void)
 		}
 		if (uartn_tx_ready(NPCX_UART_PORT0)) {
 			if (altpad_tx_pos < altpad_tx_len)
-				uartn_write_char(NPCX_UART_PORT0,
+				uartn_write_char(
+					NPCX_UART_PORT0,
 					altpad_tx_buf[altpad_tx_pos++]);
 			else
 				uart_tx_stop();
@@ -319,8 +320,8 @@ int uart_alt_pad_write_read(uint8_t *tx, int tx_len, uint8_t *rx, int rx_len,
 	uint32_t start = __hw_clock_source_read();
 	int ret = 0;
 
-	if ((get_time().val - last_default_pad_rx_time.val)
-			< block_alt_timeout_us)
+	if ((get_time().val - last_default_pad_rx_time.val) <
+	    block_alt_timeout_us)
 		return -EC_ERROR_BUSY;
 
 	cflush();
@@ -381,7 +382,6 @@ int uart_alt_pad_write_read(uint8_t *tx, int tx_len, uint8_t *rx, int rx_len,
 #endif
 void uart_init(void)
 {
-
 	uartn_init(CONSOLE_UART);
 	init_done = 1;
 }
diff --git a/chip/npcx/uartn.c b/chip/npcx/uartn.c
index 2269e11e7c..66cb30062b 100644
--- a/chip/npcx/uartn.c
+++ b/chip/npcx/uartn.c
@@ -1,76 +1,75 @@
 /*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* UART module for Chrome EC */
 
-#include <clock.h>
 #include "common.h"
-#include <gpio.h>
-#include <gpio_chip.h>
 #include "registers.h"
 #include "system.h"
 #include "task.h"
 #include "util.h"
 
+#include <clock.h>
+#include <gpio.h>
+#include <gpio_chip.h>
+
 #ifdef NPCX_UART_FIFO_SUPPORT
 /* Enable UART Tx FIFO empty interrupt */
-#define NPCX_UART_TX_EMPTY_INT_EN(n)      \
-		(SET_BIT(NPCX_UFTCTL(n), NPCX_UFTCTL_TEMPTY_EN))
+#define NPCX_UART_TX_EMPTY_INT_EN(n) \
+	(SET_BIT(NPCX_UFTCTL(n), NPCX_UFTCTL_TEMPTY_EN))
 /* True if UART Tx FIFO empty interrupt is enabled */
-#define NPCX_UART_TX_EMPTY_INT_IS_EN(n)   \
-		(IS_BIT_SET(NPCX_UFTCTL(n), NPCX_UFTCTL_TEMPTY_EN))
+#define NPCX_UART_TX_EMPTY_INT_IS_EN(n) \
+	(IS_BIT_SET(NPCX_UFTCTL(n), NPCX_UFTCTL_TEMPTY_EN))
 /* Disable UART Tx FIFO empty interrupt */
-#define NPCX_UART_TX_EMPTY_INT_DIS(n)     \
-		(CLEAR_BIT(NPCX_UFTCTL(n), NPCX_UFTCTL_TEMPTY_EN))
+#define NPCX_UART_TX_EMPTY_INT_DIS(n) \
+	(CLEAR_BIT(NPCX_UFTCTL(n), NPCX_UFTCTL_TEMPTY_EN))
 /* True if the Tx FIFO is not completely full */
-#define NPCX_UART_TX_IS_READY(n)          \
-		(!(GET_FIELD(NPCX_UFTSTS(n), NPCX_UFTSTS_TEMPTY_LVL) == 0))
+#define NPCX_UART_TX_IS_READY(n) \
+	(!(GET_FIELD(NPCX_UFTSTS(n), NPCX_UFTSTS_TEMPTY_LVL) == 0))
 
 /* Enable UART Tx "not" in transmission interrupt */
-#define NPCX_UART_TX_NXMIP_INT_EN(n)      \
-		(SET_BIT(NPCX_UFTCTL(n), NPCX_UFTCTL_NXMIPEN))
+#define NPCX_UART_TX_NXMIP_INT_EN(n) \
+	(SET_BIT(NPCX_UFTCTL(n), NPCX_UFTCTL_NXMIPEN))
 /* Disable UART Tx "not" in transmission interrupt */
-#define NPCX_UART_TX_NXMIP_INT_DIS(n)      \
-		(CLEAR_BIT(NPCX_UFTCTL(n), NPCX_UFTCTL_NXMIPEN))
+#define NPCX_UART_TX_NXMIP_INT_DIS(n) \
+	(CLEAR_BIT(NPCX_UFTCTL(n), NPCX_UFTCTL_NXMIPEN))
 /*
  * True if Tx is in progress
  * (i.e. FIFO is not empty or last byte in TSFT (Transmit Shift register)
  * is not sent)
  */
-#define NPCX_UART_TX_IN_XMIT(n)           \
-		(!IS_BIT_SET(NPCX_UFTSTS(n), NPCX_UFTSTS_NXMIP))
+#define NPCX_UART_TX_IN_XMIT(n) (!IS_BIT_SET(NPCX_UFTSTS(n), NPCX_UFTSTS_NXMIP))
 
 /*
  * Enable to generate interrupt when there is at least one byte
  * in the receive FIFO
  */
-#define NPCX_UART_RX_INT_EN(n)            \
-		(SET_BIT(NPCX_UFRCTL(n), NPCX_UFRCTL_RNEMPTY_EN))
+#define NPCX_UART_RX_INT_EN(n) (SET_BIT(NPCX_UFRCTL(n), NPCX_UFRCTL_RNEMPTY_EN))
 /* True if at least one byte is in the receive FIFO */
-#define NPCX_UART_RX_IS_AVAILABLE(n)      \
-		(IS_BIT_SET(NPCX_UFRSTS(n), NPCX_UFRSTS_RFIFO_NEMPTY_STS))
+#define NPCX_UART_RX_IS_AVAILABLE(n) \
+	(IS_BIT_SET(NPCX_UFRSTS(n), NPCX_UFRSTS_RFIFO_NEMPTY_STS))
 #else
 /* Enable UART Tx buffer empty interrupt */
-#define NPCX_UART_TX_EMPTY_INT_EN(n)      (NPCX_UICTRL(n) |= 0x20)
+#define NPCX_UART_TX_EMPTY_INT_EN(n) (NPCX_UICTRL(n) |= 0x20)
 /* True if UART Tx buffer empty interrupt is enabled */
-#define NPCX_UART_TX_EMPTY_INT_IS_EN(n)   (NPCX_UICTRL(n) & 0x20)
+#define NPCX_UART_TX_EMPTY_INT_IS_EN(n) (NPCX_UICTRL(n) & 0x20)
 /* Disable UART Tx buffer empty interrupt */
-#define NPCX_UART_TX_EMPTY_INT_DIS(n)     (NPCX_UICTRL(n) &= ~0x20)
+#define NPCX_UART_TX_EMPTY_INT_DIS(n) (NPCX_UICTRL(n) &= ~0x20)
 /* True if 1-byte Tx buffer is empty */
-#define NPCX_UART_TX_IS_READY(n)          (NPCX_UICTRL(n) & 0x01)
+#define NPCX_UART_TX_IS_READY(n) (NPCX_UICTRL(n) & 0x01)
 /*
  * True if Tx is in progress
  * (i.e. Tx buffer is not empty or last byte in TSFT (Transmit Shift register)
  * is not sent)
  */
-#define NPCX_UART_TX_IN_XMIT(n)           (NPCX_USTAT(n) & 0x40)
- /* Enable to generate interrupt when there is data in the receive buffer */
-#define NPCX_UART_RX_INT_EN(n)            (NPCX_UICTRL(n) = 0x40)
+#define NPCX_UART_TX_IN_XMIT(n) (NPCX_USTAT(n) & 0x40)
+/* Enable to generate interrupt when there is data in the receive buffer */
+#define NPCX_UART_RX_INT_EN(n) (NPCX_UICTRL(n) = 0x40)
 /* True if there is data in the 1-byte Receive buffer */
-#define NPCX_UART_RX_IS_AVAILABLE(n)      (NPCX_UICTRL(n) & 0x02)
+#define NPCX_UART_RX_IS_AVAILABLE(n) (NPCX_UICTRL(n) & 0x02)
 #endif
 
 struct uart_configs {
@@ -79,9 +78,9 @@ struct uart_configs {
 	uint32_t clk_en_msk;
 };
 static const struct uart_configs uart_cfg[] = {
-	{NPCX_IRQ_UART, CGC_OFFSET_UART, CGC_UART_MASK},
+	{ NPCX_IRQ_UART, CGC_OFFSET_UART, CGC_UART_MASK },
 #ifdef NPCX_SECOND_UART
-	{NPCX_IRQ_UART2, CGC_OFFSET_UART2, CGC_UART2_MASK},
+	{ NPCX_IRQ_UART2, CGC_OFFSET_UART2, CGC_UART2_MASK },
 #endif
 };
 BUILD_ASSERT(ARRAY_SIZE(uart_cfg) == UART_MODULE_COUNT);
@@ -144,7 +143,7 @@ void uartn_tx_start(uint8_t uart_num)
 void uartn_enable_tx_complete_int(uint8_t uart_num, uint8_t enable)
 {
 	enable ? NPCX_UART_TX_NXMIP_INT_EN(uart_num) :
-		NPCX_UART_TX_NXMIP_INT_DIS(uart_num);
+		 NPCX_UART_TX_NXMIP_INT_DIS(uart_num);
 }
 #endif
 
@@ -198,7 +197,7 @@ int uartn_read_char(uint8_t uart_num)
 
 void uartn_clear_rx_fifo(int channel)
 {
-	int scratch __attribute__ ((unused));
+	int scratch __attribute__((unused));
 
 	/* If '1',  that means there is RX data on the FIFO register */
 	while (NPCX_UART_RX_IS_AVAILABLE(channel))
@@ -211,9 +210,9 @@ static void uartn_set_fifo_mode(uint8_t uart_num)
 	/* Enable the UART FIFO mode */
 	SET_BIT(NPCX_UMDSL(uart_num), NPCX_UMDSL_FIFO_MD);
 	/* Disable all Tx interrupts */
-	NPCX_UFTCTL(uart_num) &= ~(BIT(NPCX_UFTCTL_TEMPTY_LVL_EN) |
-					BIT(NPCX_UFTCTL_TEMPTY_EN) |
-					BIT(NPCX_UFTCTL_NXMIPEN));
+	NPCX_UFTCTL(uart_num) &=
+		~(BIT(NPCX_UFTCTL_TEMPTY_LVL_EN) | BIT(NPCX_UFTCTL_TEMPTY_EN) |
+		  BIT(NPCX_UFTCTL_NXMIPEN));
 }
 
 #endif
diff --git a/chip/npcx/uartn.h b/chip/npcx/uartn.h
index e5326f72b8..ce111f11d9 100644
--- a/chip/npcx/uartn.h
+++ b/chip/npcx/uartn.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,7 +22,7 @@ void uartn_init(uint8_t uart_num);
  */
 void uartn_tx_start(uint8_t uart_num);
 
- /* Disable the UART transmit interrupt. */
+/* Disable the UART transmit interrupt. */
 void uartn_tx_stop(uint8_t uart_num, uint8_t sleep_ena);
 
 /* Flush the transmit FIFO. */
@@ -62,4 +62,4 @@ void uartn_rx_int_en(uint8_t uart_num);
 void uartn_wui_en(uint8_t uart_num);
 /* Enable/disable Tx NXMIP (No Transmit In Progress) interrupt */
 void uartn_enable_tx_complete_int(uint8_t uart_num, uint8_t enable);
-#endif  /* __CROS_EC_UARTN_H */
+#endif /* __CROS_EC_UARTN_H */
diff --git a/chip/npcx/watchdog.c b/chip/npcx/watchdog.c
index ec94babe6d..1172f3ac12 100644
--- a/chip/npcx/watchdog.c
+++ b/chip/npcx/watchdog.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,20 +8,19 @@
 #include "clock.h"
 #include "common.h"
 #include "console.h"
-#include "registers.h"
-#include "hwtimer_chip.h"
 #include "gpio.h"
 #include "hooks.h"
-#include "timer.h"
+#include "hwtimer_chip.h"
+#include "registers.h"
+#include "system_chip.h"
 #include "task.h"
+#include "timer.h"
 #include "util.h"
-#include "system_chip.h"
 #include "watchdog.h"
 
 /* WDCNT value for watchdog period */
-#define WDCNT_VALUE   ((CONFIG_WATCHDOG_PERIOD_MS*INT_32K_CLOCK) / (1024*1000))
-/* Delay time for warning timer to print watchdog info through UART */
-#define WDCNT_DELAY   WDCNT_VALUE
+#define WDCNT_VALUE \
+	((CONFIG_WATCHDOG_PERIOD_MS * INT_32K_CLOCK) / (1024 * 1000))
 
 void watchdog_init_warning_timer(void)
 {
@@ -34,30 +33,19 @@ void watchdog_init_warning_timer(void)
 	 * PRE_8 = (Ttick_unit/T32K) - 1
 	 * Unit: 1 msec
 	 */
-	NPCX_ITPRE(ITIM_WDG_NO)  = DIV_ROUND_NEAREST(1000*INT_32K_CLOCK,
-							 SECOND) - 1;
+	NPCX_ITPRE(ITIM_WDG_NO) =
+		DIV_ROUND_NEAREST(1000 * INT_32K_CLOCK, SECOND) - 1;
 
 	/* Event module disable */
 	CLEAR_BIT(NPCX_ITCTS(ITIM_WDG_NO), NPCX_ITCTS_ITEN);
-	/* ITIM count down : event expired*/
-	NPCX_ITCNT(ITIM_WDG_NO) = CONFIG_AUX_TIMER_PERIOD_MS - 1;
+	/* ITIM count down : event expired */
+	NPCX_ITCNT(ITIM_WDG_NO) = CONFIG_AUX_TIMER_PERIOD_MS;
 	/* Event module enable */
 	SET_BIT(NPCX_ITCTS(ITIM_WDG_NO), NPCX_ITCTS_ITEN);
 	/* Enable interrupt of ITIM */
 	task_enable_irq(ITIM_INT(ITIM_WDG_NO));
 }
 
-static uint8_t watchdog_count(void)
-{
-	uint8_t cnt;
-	/* Wait for two consecutive equal values are read */
-	do {
-		cnt = NPCX_TWMWD;
-	} while (cnt != NPCX_TWMWD);
-
-	return cnt;
-}
-
 static timestamp_t last_watchdog_touch;
 void watchdog_stop_and_unlock(void)
 {
@@ -79,10 +67,26 @@ static void touch_watchdog_count(void)
 	last_watchdog_touch = get_time();
 }
 
-void __keep watchdog_check(uint32_t excep_lr, uint32_t excep_sp)
+static void watchdog_reload_warning_timer(void)
 {
-	int  wd_cnt;
+	/* Disable warning timer module  */
+	CLEAR_BIT(NPCX_ITCTS(ITIM_WDG_NO), NPCX_ITCTS_ITEN);
+	/* Wait for module disable to take effect before updating count */
+	while (IS_BIT_SET(NPCX_ITCTS(ITIM_WDG_NO), NPCX_ITCTS_ITEN))
+		;
 
+	/* Reload the warning timer count */
+	NPCX_ITCNT(ITIM_WDG_NO) = CONFIG_AUX_TIMER_PERIOD_MS;
+
+	/* enable warning timer module  */
+	SET_BIT(NPCX_ITCTS(ITIM_WDG_NO), NPCX_ITCTS_ITEN);
+	/* Wait for module enable */
+	while (!IS_BIT_SET(NPCX_ITCTS(ITIM_WDG_NO), NPCX_ITCTS_ITEN))
+		;
+}
+
+void __keep watchdog_check(uint32_t excep_lr, uint32_t excep_sp)
+{
 #ifdef CONFIG_TASK_PROFILING
 	/*
 	 * Perform IRQ profiling accounting. This is normally done by
@@ -94,25 +98,8 @@ void __keep watchdog_check(uint32_t excep_lr, uint32_t excep_sp)
 	/* Clear timeout status for event */
 	SET_BIT(NPCX_ITCTS(ITIM_WDG_NO), NPCX_ITCTS_TO_STS);
 
-	/* Read watchdog counter from TWMWD */
-	wd_cnt = watchdog_count();
-#if DEBUG_WDG
-	panic_printf("WD (%d)\r\n", wd_cnt);
-#endif
-	if (wd_cnt <= WDCNT_DELAY) {
-		/*
-		 * Touch watchdog to let UART have enough time
-		 * to print panic info
-		 */
-		touch_watchdog_count();
-
-		/* Print panic info */
-		watchdog_trace(excep_lr, excep_sp);
-		cflush();
-
-		/* Trigger watchdog immediately */
-		system_watchdog_reset();
-	}
+	/* Print panic info */
+	watchdog_trace(excep_lr, excep_sp);
 }
 
 /* ISR for watchdog warning naked will keep SP & LR */
@@ -121,18 +108,18 @@ void IRQ_HANDLER(ITIM_INT(ITIM_WDG_NO))(void)
 {
 	/* Naked call so we can extract raw LR and SP */
 	asm volatile("mov r0, lr\n"
-			"mov r1, sp\n"
-			/* Must push registers in pairs to keep 64-bit aligned
-			 * stack for ARM EABI.  This also conveninently saves
-			 * R0=LR so we can pass it to task_resched_if_needed. */
-			"push {r0, lr}\n"
-			"bl watchdog_check\n"
-			"pop {r0, lr}\n"
-			"b task_resched_if_needed\n");
+		     "mov r1, sp\n"
+		     /* Must push registers in pairs to keep 64-bit aligned
+		      * stack for ARM EABI.  This also conveninently saves
+		      * R0=LR so we can pass it to task_resched_if_needed. */
+		     "push {r0, lr}\n"
+		     "bl watchdog_check\n"
+		     "pop {r0, lr}\n"
+		     "b task_resched_if_needed\n");
 }
 const struct irq_priority __keep IRQ_PRIORITY(ITIM_INT(ITIM_WDG_NO))
-__attribute__((section(".rodata.irqprio")))
-= {ITIM_INT(ITIM_WDG_NO), 0};
+	__attribute__((section(".rodata.irqprio"))) = { ITIM_INT(ITIM_WDG_NO),
+							0 };
 /* put the watchdog at the highest priority */
 
 void watchdog_reload(void)
@@ -140,6 +127,8 @@ void watchdog_reload(void)
 	/* Disable watchdog interrupt */
 	task_disable_irq(ITIM_INT(ITIM_WDG_NO));
 
+	watchdog_reload_warning_timer();
+
 #if 1 /* mark this for testing watchdog */
 	/* Touch watchdog & reset software counter */
 	touch_watchdog_count();
@@ -153,14 +142,14 @@ DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT);
 int watchdog_init(void)
 {
 #if SUPPORT_WDG
+	const uint32_t pre_wdcnt = WDCNT_VALUE;
+
 	/* Touch watchdog before init if it is already running */
 	if (IS_BIT_SET(NPCX_T0CSR, NPCX_T0CSR_WD_RUN))
 		touch_watchdog_count();
 
 	/* Keep prescaler ratio timer0 clock to 1:1024 */
 	NPCX_TWCP = 0x0A;
-	/* Keep prescaler ratio watchdog clock to 1:1 */
-	NPCX_WDCP = 0;
 
 	/* Clear watchdog reset status initially*/
 	SET_BIT(NPCX_T0CSR, NPCX_T0CSR_WDRST_STS);
@@ -175,13 +164,30 @@ int watchdog_init(void)
 	SET_BIT(NPCX_T0CSR, NPCX_T0CSR_TESDIS);
 
 	/*
-	 * Set WDCNT initial reload value and T0OUT timeout period
-	 * 1. Watchdog clock source is 32768/1024 Hz and disable T0OUT.
-	 * 2. ITIM16 will be issued to check WDCNT is under WDCNT_DELAY or not
-	 * 3. Set RST to upload TWDT0 & WDCNT
+	 * Calculate and set WDCNT initial reload value and T0OUT timeout
+	 * period
+	 * When WDCNT counts down to 0: generate watchdog reset
 	 */
-	/* Set WDCNT --> WDCNT=0 will generate watchdog reset */
-	NPCX_WDCNT = WDCNT_VALUE + WDCNT_DELAY;
+	if (pre_wdcnt <= 255) {
+		/* Keep prescaler ratio watchdog clock to 1:1 */
+		NPCX_WDCP = 0;
+		NPCX_WDCNT = pre_wdcnt;
+	} else {
+		uint8_t wdcp;
+		uint8_t pre_scal;
+
+		pre_scal = DIV_ROUND_UP(pre_wdcnt, 255);
+
+		/*
+		 * Find the smallest power of 2 greater than or equal to the
+		 * prescaler
+		 */
+		wdcp = __fls(pre_scal - 1) + 1;
+		pre_scal = 1 << wdcp;
+
+		NPCX_WDCP = wdcp;
+		NPCX_WDCNT = pre_wdcnt / pre_scal;
+	}
 
 	/* Disable interrupt */
 	interrupt_disable();
diff --git a/chip/npcx/wov.c b/chip/npcx/wov.c
index c4f68f5369..8616cdd001 100644
--- a/chip/npcx/wov.c
+++ b/chip/npcx/wov.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,7 +26,7 @@
 #define CPRINTS(...)
 #else
 #define CPUTS(outstr) cputs(CC_AUDIO_CODEC, outstr)
-#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ##args)
 #endif
 
 /* WOV FIFO status. */
@@ -64,106 +64,106 @@
 #define WOV_FMUL2_CLK_TUNING_DELAY_TIME (4 * 1000)
 
 /* The size of RAM buffer to store the voice data */
-#define VOICE_BUF_SIZE    16000
+#define VOICE_BUF_SIZE 16000
 
 /* PLL setting options. */
 struct wov_pll_set_options_val {
-	uint8_t pll_indv;     /* Input Divider */
-	uint16_t pll_fbdv;    /* Feedback Divider */
-	uint8_t pll_otdv1;    /* Output devide 1. */
-	uint8_t pll_otdv2;    /* Output devide 2. */
+	uint8_t pll_indv; /* Input Divider */
+	uint16_t pll_fbdv; /* Feedback Divider */
+	uint8_t pll_otdv1; /* Output devide 1. */
+	uint8_t pll_otdv2; /* Output devide 2. */
 	uint32_t pll_ext_div; /* Index for the table pll_ext_div */
 };
 
 /* PLL External Divider Load Values. */
 struct wov_pll_ext_div_val {
-	uint8_t pll_ediv;    /* Required PLL external divider */
+	uint8_t pll_ediv; /* Required PLL external divider */
 	uint8_t pll_ediv_dc; /* Required PLL external divider DC */
 };
 
 static const struct wov_pll_ext_div_val pll_ext_div[] = {
-	{0x2F, 0x78}, /* 12 */
-	{0x57, 0x7C}, /* 13 */
-	{0x2B, 0x7C}, /* 14 */
-	{0x55, 0x7E}, /* 15 */
-	{0x2A, 0x7E}, /* 16 */
-	{0x15, 0x7F}, /* 17 */
-	{0x4A, 0x7F}, /* 18 */
-	{0x65, 0x3F}, /* 19 */
-	{0x32, 0x3F}, /* 20 */
-	{0x19, 0x5F}, /* 21 */
-	{0x4C, 0x5F}, /* 22 */
-	{0x66, 0x2F}, /* 23 */
-	{0x73, 0x2F}, /* 24 */
-	{0x39, 0x57}, /* 25 */
-	{0x5C, 0x57}, /* 26 */
-	{0x6E, 0x2B}, /* 27 */
-	{0x77, 0x2B}, /* 28 */
-	{0x3B, 0x55}, /* 29 */
-	{0x5D, 0x55}, /* 30 */
-	{0x2E, 0x2A}, /* 31 */
-	{0x17, 0x2A}, /* 32 */
-	{0x4B, 0x15}, /* 33 */
-	{0x25, 0x15}, /* 34 */
-	{0x52, 0x4A}, /* 35 */
-	{0x69, 0x4A}, /* 36 */
-	{0x34, 0x65}, /* 37 */
-	{0x1A, 0x65}, /* 38 */
-	{0x0D, 0x32}, /* 39 */
-	{0x46, 0x32}, /* 40 */
-	{0x63, 0x19}, /* 41 */
-	{0x31, 0x19}, /* 42 */
-	{0x58, 0x4C}, /* 43 */
-	{0x6C, 0x4C}, /* 44 */
-	{0x76, 0x66}, /* 45 */
-	{0x7B, 0x66}, /* 46 */
-	{0x3D, 0x73}, /* 47 */
-	{0x5E, 0x73}, /* 48 */
-	{0x6F, 0x39}, /* 49 */
-	{0x37, 0x39}, /* 50 */
-	{0x5B, 0x5C}, /* 51 */
-	{0x2D, 0x5C}, /* 52 */
-	{0x56, 0x6E}, /* 53 */
-	{0x6B, 0x6E}, /* 54 */
-	{0x35, 0x77}, /* 55 */
-	{0x5A, 0x77}, /* 56 */
-	{0x6D, 0x3B}, /* 57 */
-	{0x36, 0x3B}, /* 58 */
-	{0x1B, 0x5D}, /* 59 */
-	{0x4D, 0x5D}, /* 60 */
-	{0x26, 0x2E}, /* 61 */
-	{0x13, 0x2E}, /* 62 */
-	{0x49, 0x17}, /* 63 */
-	{0x24, 0x17}, /* 64 */
-	{0x12, 0x4B}, /* 65 */
-	{0x09, 0x4B}, /* 66 */
-	{0x44, 0x25}  /* 67 */
+	{ 0x2F, 0x78 }, /* 12 */
+	{ 0x57, 0x7C }, /* 13 */
+	{ 0x2B, 0x7C }, /* 14 */
+	{ 0x55, 0x7E }, /* 15 */
+	{ 0x2A, 0x7E }, /* 16 */
+	{ 0x15, 0x7F }, /* 17 */
+	{ 0x4A, 0x7F }, /* 18 */
+	{ 0x65, 0x3F }, /* 19 */
+	{ 0x32, 0x3F }, /* 20 */
+	{ 0x19, 0x5F }, /* 21 */
+	{ 0x4C, 0x5F }, /* 22 */
+	{ 0x66, 0x2F }, /* 23 */
+	{ 0x73, 0x2F }, /* 24 */
+	{ 0x39, 0x57 }, /* 25 */
+	{ 0x5C, 0x57 }, /* 26 */
+	{ 0x6E, 0x2B }, /* 27 */
+	{ 0x77, 0x2B }, /* 28 */
+	{ 0x3B, 0x55 }, /* 29 */
+	{ 0x5D, 0x55 }, /* 30 */
+	{ 0x2E, 0x2A }, /* 31 */
+	{ 0x17, 0x2A }, /* 32 */
+	{ 0x4B, 0x15 }, /* 33 */
+	{ 0x25, 0x15 }, /* 34 */
+	{ 0x52, 0x4A }, /* 35 */
+	{ 0x69, 0x4A }, /* 36 */
+	{ 0x34, 0x65 }, /* 37 */
+	{ 0x1A, 0x65 }, /* 38 */
+	{ 0x0D, 0x32 }, /* 39 */
+	{ 0x46, 0x32 }, /* 40 */
+	{ 0x63, 0x19 }, /* 41 */
+	{ 0x31, 0x19 }, /* 42 */
+	{ 0x58, 0x4C }, /* 43 */
+	{ 0x6C, 0x4C }, /* 44 */
+	{ 0x76, 0x66 }, /* 45 */
+	{ 0x7B, 0x66 }, /* 46 */
+	{ 0x3D, 0x73 }, /* 47 */
+	{ 0x5E, 0x73 }, /* 48 */
+	{ 0x6F, 0x39 }, /* 49 */
+	{ 0x37, 0x39 }, /* 50 */
+	{ 0x5B, 0x5C }, /* 51 */
+	{ 0x2D, 0x5C }, /* 52 */
+	{ 0x56, 0x6E }, /* 53 */
+	{ 0x6B, 0x6E }, /* 54 */
+	{ 0x35, 0x77 }, /* 55 */
+	{ 0x5A, 0x77 }, /* 56 */
+	{ 0x6D, 0x3B }, /* 57 */
+	{ 0x36, 0x3B }, /* 58 */
+	{ 0x1B, 0x5D }, /* 59 */
+	{ 0x4D, 0x5D }, /* 60 */
+	{ 0x26, 0x2E }, /* 61 */
+	{ 0x13, 0x2E }, /* 62 */
+	{ 0x49, 0x17 }, /* 63 */
+	{ 0x24, 0x17 }, /* 64 */
+	{ 0x12, 0x4B }, /* 65 */
+	{ 0x09, 0x4B }, /* 66 */
+	{ 0x44, 0x25 } /* 67 */
 };
 
 /* WOV interrupts */
 static const uint8_t wov_interupts[] = {
-	0,  /* VAD_INTEN */
-	1,  /* VAD_WKEN */
-	8,  /* CFIFO_NE_IE */
-	9,  /* CFIFO_OIT_IE */
+	0, /* VAD_INTEN */
+	1, /* VAD_WKEN */
+	8, /* CFIFO_NE_IE */
+	9, /* CFIFO_OIT_IE */
 	10, /* CFIFO_OWT_WE */
 	11, /* CFIFO_OVRN_IE */
 	12, /* I2S_FIFO_OVRN_IE */
-	13  /* I2S_FIFO_UNDRN_IE */
+	13 /* I2S_FIFO_UNDRN_IE */
 };
 
 struct wov_ppl_divider {
 	uint16_t pll_frame_len; /* PLL frame length. */
-	uint16_t pll_fbdv;      /* PLL feedback divider. */
-	uint8_t pll_indv;       /* PLL Input Divider. */
-	uint8_t pll_otdv1;      /* PLL Output Divider 1. */
-	uint8_t pll_otdv2;      /* PLL Output Divider 2. */
-	uint8_t pll_ediv;       /* PLL External Divide Factor. */
+	uint16_t pll_fbdv; /* PLL feedback divider. */
+	uint8_t pll_indv; /* PLL Input Divider. */
+	uint8_t pll_otdv1; /* PLL Output Divider 1. */
+	uint8_t pll_otdv2; /* PLL Output Divider 2. */
+	uint8_t pll_ediv; /* PLL External Divide Factor. */
 };
 
 struct wov_cfifo_buf {
 	uint32_t *buf; /* Pointer to a buffer. */
-	int size;      /* Buffer size in words. */
+	int size; /* Buffer size in words. */
 };
 
 struct wov_config wov_conf;
@@ -205,11 +205,11 @@ void wov_cfifo_read_handler_l(uint32_t num_elements)
 	cfifo_buf.size -= num_elements;
 }
 
-static enum ec_error_list wov_calc_pll_div_s(int32_t d_in,
-					int32_t total_div, int32_t vco_freq,
-					struct wov_ppl_divider *pll_div)
+static enum ec_error_list wov_calc_pll_div_s(int32_t d_in, int32_t total_div,
+					     int32_t vco_freq,
+					     struct wov_ppl_divider *pll_div)
 {
-	int32_t	 d_1, d_2, d_e;
+	int32_t d_1, d_2, d_e;
 
 	/*
 	 * Please see comments in wov_calc_pll_div_l function below.
@@ -221,10 +221,10 @@ static enum ec_error_list wov_calc_pll_div_s(int32_t d_in,
 					continue;
 
 				if (total_div == (d_in * d_e * d_1 * d_2)) {
-					pll_div->pll_indv  = d_in;
+					pll_div->pll_indv = d_in;
 					pll_div->pll_otdv1 = d_1;
 					pll_div->pll_otdv2 = d_2;
-					pll_div->pll_ediv  = d_e;
+					pll_div->pll_ediv = d_e;
 					return EC_SUCCESS;
 				}
 			}
@@ -243,7 +243,8 @@ static enum ec_error_list wov_calc_pll_div_s(int32_t d_in,
  * @return  None
  */
 static enum ec_error_list wov_calc_pll_div_l(uint32_t i2s_clk_freq,
-			uint32_t sample_rate, struct wov_ppl_divider *pll_div)
+					     uint32_t sample_rate,
+					     struct wov_ppl_divider *pll_div)
 {
 	int32_t d_f;
 	int32_t total_div;
@@ -292,12 +293,11 @@ static enum ec_error_list wov_calc_pll_div_l(uint32_t i2s_clk_freq,
 				if ((vco_freq < 500) || (vco_freq > 1600))
 					continue;
 				if (wov_calc_pll_div_s(d_in, total_div,
-						vco_freq, pll_div) ==
-						EC_SUCCESS) {
-					pll_div->pll_fbdv  = d_f;
+						       vco_freq,
+						       pll_div) == EC_SUCCESS) {
+					pll_div->pll_fbdv = d_f;
 					return EC_SUCCESS;
 				}
-
 			}
 		}
 	}
@@ -340,12 +340,13 @@ static enum ec_error_list wov_set_i2s_config_l(void)
 	int32_t start_delay_0, start_delay_1;
 
 	ret_code = wov_calc_pll_div_l(wov_conf.i2s_clock,
-				wov_conf.sample_per_sec, &pll_div);
+				      wov_conf.sample_per_sec, &pll_div);
 	if (ret_code == EC_SUCCESS) {
 		/* Configure the PLL. */
-		ret_code = wov_pll_clk_div_config(
-			pll_div.pll_otdv1, pll_div.pll_otdv2, pll_div.pll_fbdv,
-			pll_div.pll_indv);
+		ret_code = wov_pll_clk_div_config(pll_div.pll_otdv1,
+						  pll_div.pll_otdv2,
+						  pll_div.pll_fbdv,
+						  pll_div.pll_indv);
 		if (ret_code != EC_SUCCESS)
 			return ret_code;
 
@@ -414,10 +415,10 @@ static enum ec_error_list wov_set_i2s_config_l(void)
 		udelay(100);
 
 		ret_code = wov_i2s_channel_config(0, wov_conf.bit_depth,
-					trigger_0, start_delay_0);
+						  trigger_0, start_delay_0);
 
 		ret_code = wov_i2s_channel_config(1, wov_conf.bit_depth,
-					trigger_1, start_delay_1);
+						  trigger_1, start_delay_1);
 	}
 
 	return EC_SUCCESS;
@@ -471,14 +472,14 @@ static enum ec_error_list wov_set_mic_source_l(void)
 	case WOV_SRC_LEFT:
 		if (wov_conf.bit_depth == 16)
 			SET_FIELD(NPCX_WOV_FIFO_CNT,
-				NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x00);
+				  NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x00);
 		else
 			SET_FIELD(NPCX_WOV_FIFO_CNT,
-				NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x02);
+				  NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x02);
 		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_LEFT,
-				0x01);
+			  0x01);
 		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_RIGHT,
-				0x01);
+			  0x01);
 		apm_digital_mixer_config(APM_OUT_MIX_NORMAL_INPUT,
 					 APM_OUT_MIX_NO_INPUT);
 		apm_set_vad_input_channel(APM_IN_LEFT);
@@ -493,11 +494,11 @@ static enum ec_error_list wov_set_mic_source_l(void)
 			SET_FIELD(NPCX_WOV_FIFO_CNT,
 				  NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x02);
 		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_LEFT,
-				0x01);
+			  0x01);
 		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_RIGHT,
-				0x01);
+			  0x01);
 		apm_digital_mixer_config(APM_OUT_MIX_CROSS_INPUT,
-					APM_OUT_MIX_NO_INPUT);
+					 APM_OUT_MIX_NO_INPUT);
 		apm_set_vad_input_channel(APM_IN_RIGHT);
 		wov_i2s_channel1_disable(1);
 		break;
@@ -505,16 +506,16 @@ static enum ec_error_list wov_set_mic_source_l(void)
 	case WOV_SRC_MONO:
 		if (wov_conf.bit_depth == 16)
 			SET_FIELD(NPCX_WOV_FIFO_CNT,
-				NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x01);
+				  NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x01);
 		else
 			SET_FIELD(NPCX_WOV_FIFO_CNT,
-				NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x03);
+				  NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x03);
 		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_LEFT,
-				0x02);
+			  0x02);
 		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_RIGHT,
-				0x02);
+			  0x02);
 		apm_digital_mixer_config(APM_OUT_MIX_NORMAL_INPUT,
-					APM_OUT_MIX_NORMAL_INPUT);
+					 APM_OUT_MIX_NORMAL_INPUT);
 		apm_set_vad_input_channel(APM_IN_AVERAGE_LEFT_RIGHT);
 		wov_i2s_channel1_disable(0);
 		break;
@@ -522,14 +523,14 @@ static enum ec_error_list wov_set_mic_source_l(void)
 	case WOV_SRC_STEREO:
 		if (wov_conf.bit_depth == 16)
 			SET_FIELD(NPCX_WOV_FIFO_CNT,
-				NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x01);
+				  NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x01);
 		else
 			SET_FIELD(NPCX_WOV_FIFO_CNT,
-				NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x03);
+				  NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x03);
 		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_LEFT,
-				0x01);
+			  0x01);
 		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_RIGHT,
-				0x01);
+			  0x01);
 		apm_digital_mixer_config(APM_OUT_MIX_NORMAL_INPUT,
 					 APM_OUT_MIX_NORMAL_INPUT);
 		wov_i2s_channel1_disable(0);
@@ -579,14 +580,14 @@ static void wov_under_over_error_handler(int *count, uint32_t *last_time)
  *
  * @return  None
  */
-void wov_interrupt_handler(void)
+static void wov_interrupt_handler(void)
 {
 	uint32_t wov_status;
 	uint32_t wov_inten;
 
 	wov_inten = GET_FIELD(NPCX_WOV_WOV_INTEN, NPCX_WOV_STATUS_BITS);
 	wov_status = wov_inten &
-			GET_FIELD(NPCX_WOV_STATUS, NPCX_WOV_STATUS_BITS);
+		     GET_FIELD(NPCX_WOV_STATUS, NPCX_WOV_STATUS_BITS);
 
 	/*
 	 * Voice activity detected.
@@ -602,7 +603,7 @@ void wov_interrupt_handler(void)
 		WOV_CALLBACK(WOV_EVENT_ERROR_CORE_FIFO_OVERRUN);
 		wov_core_fifo_reset();
 	} else if (WOV_IS_CFIFO_INT_THRESHOLD(wov_status) &&
-				(cfifo_buf.buf != NULL)) {
+		   (cfifo_buf.buf != NULL)) {
 		/*
 		 * Core FIFO threshold or FIFO not empty event occurred.
 		 * - Read data from core FIFO to the buffer.
@@ -635,7 +636,6 @@ void wov_interrupt_handler(void)
 		wov_i2s_fifo_reset();
 	}
 
-
 	/* Clear the WoV status register. */
 	SET_FIELD(NPCX_WOV_STATUS, NPCX_WOV_STATUS_BITS, wov_status);
 }
@@ -651,19 +651,17 @@ DECLARE_IRQ(NPCX_IRQ_WOV, wov_interrupt_handler, 4);
 static void wov_fmul2_enable(int enable)
 {
 	if (enable) {
-
 		/* If clock disabled, then enable it. */
 		if (IS_BIT_SET(NPCX_FMUL2_FM2CTRL,
-					NPCX_FMUL2_FM2CTRL_FMUL2_DIS)) {
+			       NPCX_FMUL2_FM2CTRL_FMUL2_DIS)) {
 			/* Enable clock tuning. */
 			CLEAR_BIT(NPCX_FMUL2_FM2CTRL,
-					NPCX_FMUL2_FM2CTRL_TUNE_DIS);
+				  NPCX_FMUL2_FM2CTRL_TUNE_DIS);
 			/* Enable clock. */
 			CLEAR_BIT(NPCX_FMUL2_FM2CTRL,
-					NPCX_FMUL2_FM2CTRL_FMUL2_DIS);
+				  NPCX_FMUL2_FM2CTRL_FMUL2_DIS);
 
 			udelay(WOV_FMUL2_CLK_TUNING_DELAY_TIME);
-
 		}
 	} else
 		SET_BIT(NPCX_FMUL2_FM2CTRL, NPCX_FMUL2_FM2CTRL_FMUL2_DIS);
@@ -688,7 +686,7 @@ void wov_fmul2_conf_tuning(void)
 {
 	/* Check if FMUL2 is enabled, then do nothing. */
 	if (IS_BIT_SET(NPCX_FMUL2_FM2CTRL, NPCX_FMUL2_FM2CTRL_FMUL2_DIS) ==
-			0x00)
+	    0x00)
 		return;
 
 	/* Enable clock tuning. */
@@ -838,6 +836,7 @@ enum ec_error_list wov_set_mode(enum wov_modes wov_mode)
 	case WOV_MODE_RAM_AND_I2S:
 		if ((wov_conf.bit_depth != 16) && (wov_conf.bit_depth != 24))
 			return EC_ERROR_INVAL;
+		__fallthrough;
 	case WOV_MODE_I2S:
 		if (apm_get_adc_i2s_dmic_rate() == APM_DMIC_RATE_0_75)
 			wov_dmic_clk_config(1, WOV_DMIC_DIV_BY_4);
@@ -968,7 +967,6 @@ void wov_set_clk_selection(enum wov_clk_src_sel clk_src)
 		wov_fmul2_enable(0);
 	else
 		wov_pll_enable(0);
-
 }
 
 /**
@@ -981,9 +979,9 @@ void wov_set_clk_selection(enum wov_clk_src_sel clk_src)
  *                                PLL External Divider Load Values table.
  * @return  EC_ERROR_INVAL or EC_SUCCESS
  */
-enum ec_error_list wov_pll_clk_ext_div_config(
-	enum wov_pll_ext_div_sel ext_div_sel,
-	uint32_t div_factor)
+enum ec_error_list
+wov_pll_clk_ext_div_config(enum wov_pll_ext_div_sel ext_div_sel,
+			   uint32_t div_factor)
 {
 	/* Sets the clock division factor for the PLL external divider.
 	 * The divide factor should be in the range of 2 to 67.
@@ -1045,13 +1043,13 @@ void wov_pll_enable(int enable)
  * @return  EC_ERROR_INVAL or EC_SUCCESS
  */
 enum ec_error_list wov_pll_clk_div_config(uint32_t out_div_1,
-					uint32_t out_div_2,
-					uint32_t feedback_div,
-					uint32_t in_div)
+					  uint32_t out_div_2,
+					  uint32_t feedback_div,
+					  uint32_t in_div)
 {
 	/* Parameter check. */
-	if ((out_div_1 < 1) || (out_div_1 > 7) ||
-		(out_div_2 < 1) || (out_div_2 > 7))
+	if ((out_div_1 < 1) || (out_div_1 > 7) || (out_div_2 < 1) ||
+	    (out_div_2 > 7))
 		return EC_ERROR_INVAL;
 
 	/*
@@ -1255,7 +1253,7 @@ int wov_set_buffer(uint32_t *buf, int size_in_words)
 
 	cfifo_threshold = wov_get_cfifo_threshold_l();
 	if (size_in_words !=
-		((size_in_words / cfifo_threshold) * cfifo_threshold))
+	    ((size_in_words / cfifo_threshold) * cfifo_threshold))
 		return EC_ERROR_INVAL;
 
 	cfifo_buf.buf = buf;
@@ -1298,21 +1296,17 @@ void wov_apm_active(int enable)
  * @return  EC_ERROR_INVAL or EC_SUCCESS
  */
 enum ec_error_list wov_i2s_global_config(
-	enum wov_floating_mode i2s_hiz_data,
-	enum wov_floating_mode i2s_hiz,
-	enum wov_clk_inverted_mode clk_invert,
-	int out_pull_en,
-	enum wov_pull_upd_down_sel out_pull_mode,
-	int in_pull_en,
-	enum wov_pull_upd_down_sel in_pull_mode,
-	enum wov_test_mode test_mode)
+	enum wov_floating_mode i2s_hiz_data, enum wov_floating_mode i2s_hiz,
+	enum wov_clk_inverted_mode clk_invert, int out_pull_en,
+	enum wov_pull_upd_down_sel out_pull_mode, int in_pull_en,
+	enum wov_pull_upd_down_sel in_pull_mode, enum wov_test_mode test_mode)
 {
 	/* Check the parameters correctness. */
 	if ((i2s_hiz_data == WOV_FLOATING) &&
-		((GET_FIELD(NPCX_WOV_I2S_CNTL(0),
-				NPCX_WOV_I2S_CNTL_I2S_ST_DEL) == 0) ||
-		(GET_FIELD(NPCX_WOV_I2S_CNTL(1),
-				NPCX_WOV_I2S_CNTL_I2S_ST_DEL) == 0)))
+	    ((GET_FIELD(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL_I2S_ST_DEL) ==
+	      0) ||
+	     (GET_FIELD(NPCX_WOV_I2S_CNTL(1), NPCX_WOV_I2S_CNTL_I2S_ST_DEL) ==
+	      0)))
 		return EC_ERROR_INVAL;
 
 	/* Set the parameters. */
@@ -1375,9 +1369,9 @@ enum ec_error_list wov_i2s_global_config(
  * @return  EC_ERROR_INVAL or EC_SUCCESS
  */
 enum ec_error_list wov_i2s_channel_config(uint32_t channel_num,
-					uint32_t bit_count,
-					enum wov_i2s_chan_trigger trigger,
-					int32_t start_delay)
+					  uint32_t bit_count,
+					  enum wov_i2s_chan_trigger trigger,
+					  int32_t start_delay)
 {
 	/* Check the parameters correctnes. */
 	if ((channel_num != 0) && (channel_num != 1))
@@ -1392,7 +1386,7 @@ enum ec_error_list wov_i2s_channel_config(uint32_t channel_num,
 
 	/* Set the parameters. */
 	SET_FIELD(NPCX_WOV_I2S_CNTL(channel_num), NPCX_WOV_I2S_CNTL_I2S_BCNT,
-			(bit_count - 1));
+		  (bit_count - 1));
 
 	if (trigger == WOV_I2S_SAMPLED_1_AFTER_0)
 		CLEAR_BIT(NPCX_WOV_I2S_CNTL(channel_num),
@@ -1459,8 +1453,8 @@ int wov_set_sample_depth(int bits_num)
 	if (wov_conf.mode != WOV_MODE_OFF)
 		return EC_ERROR_INVALID_CONFIG;
 
-	if ((bits_num != 16) && (bits_num != 18) &&
-		(bits_num != 20) && (bits_num != 24))
+	if ((bits_num != 16) && (bits_num != 18) && (bits_num != 20) &&
+	    (bits_num != 24))
 		return EC_ERROR_INVAL;
 
 	wov_conf.bit_depth = bits_num;
@@ -1529,8 +1523,8 @@ void wov_set_gain(int left_chan_gain, int right_chan_gain)
 	wov_conf.left_chan_gain = left_chan_gain;
 	wov_conf.right_chan_gain = right_chan_gain;
 
-	(void) apm_adc_gain_config(APM_ADC_CHAN_GAINS_INDEPENDENT,
-				left_chan_gain, right_chan_gain);
+	(void)apm_adc_gain_config(APM_ADC_CHAN_GAINS_INDEPENDENT,
+				  left_chan_gain, right_chan_gain);
 }
 
 /**
@@ -1571,10 +1565,10 @@ void wov_enable_agc(int enable)
  * @param min_applied_gain      - Minimum Gain Value to apply to the ADC path.
  * @return  EC_ERROR_INVAL or EC_SUCCESS
  */
-enum ec_error_list wov_set_agc_config(int stereo, float target,
-				int noise_gate_threshold, uint8_t hold_time,
-				uint16_t attack_time, uint16_t decay_time,
-				float max_applied_gain, float min_applied_gain)
+enum ec_error_list
+wov_set_agc_config(int stereo, float target, int noise_gate_threshold,
+		   uint8_t hold_time, uint16_t attack_time, uint16_t decay_time,
+		   float max_applied_gain, float min_applied_gain)
 {
 	int target_code;
 	int ngth_code;
@@ -1607,7 +1601,7 @@ enum ec_error_list wov_set_agc_config(int stereo, float target,
 		return EC_ERROR_INVAL;
 
 	for (attack_time_code = 0; attack_time_code <= 0x0F;
-			attack_time_code++) {
+	     attack_time_code++) {
 		if (((attack_time_code + 1) * 32) == attack_time)
 			break;
 	}
@@ -1622,15 +1616,15 @@ enum ec_error_list wov_set_agc_config(int stereo, float target,
 		return EC_ERROR_INVAL;
 
 	for (max_applied_gain_code = 0; max_applied_gain_code < 16;
-			max_applied_gain_code++) {
+	     max_applied_gain_code++) {
 		if ((max_applied_gain_code * 1.5) == max_applied_gain)
 			break;
 	}
 	if (max_applied_gain_code == 16) {
 		for (max_applied_gain_code = 18; max_applied_gain_code < 32;
-				max_applied_gain_code++) {
+		     max_applied_gain_code++) {
 			if (((max_applied_gain_code * 1.5) - 4) ==
-					max_applied_gain)
+			    max_applied_gain)
 				break;
 		}
 	}
@@ -1638,15 +1632,15 @@ enum ec_error_list wov_set_agc_config(int stereo, float target,
 		return EC_ERROR_INVAL;
 
 	for (min_applied_gain_code = 0; min_applied_gain_code < 16;
-			min_applied_gain_code++) {
+	     min_applied_gain_code++) {
 		if ((min_applied_gain_code * 1.5) == min_applied_gain)
 			break;
 	}
 	if (min_applied_gain_code == 16) {
 		for (min_applied_gain_code = 18; min_applied_gain_code < 32;
-				min_applied_gain_code++) {
+		     min_applied_gain_code++) {
 			if (((min_applied_gain_code * 1.5) - 4) ==
-					min_applied_gain)
+			    min_applied_gain)
 				break;
 		}
 	}
@@ -1654,14 +1648,14 @@ enum ec_error_list wov_set_agc_config(int stereo, float target,
 		return EC_ERROR_INVAL;
 
 	gain_cfg.stereo_enable = stereo,
-	gain_cfg.agc_target = (enum apm_adc_target_out_level) target_code;
+	gain_cfg.agc_target = (enum apm_adc_target_out_level)target_code;
 	gain_cfg.nois_gate_en = (noise_gate_threshold != 0);
-	gain_cfg.nois_gate_thold = (enum apm_noise_gate_threshold) ngth_code;
-	gain_cfg.hold_time = (enum apm_agc_adj_hold_time) hold_time;
-	gain_cfg.attack_time = (enum apm_gain_ramp_time) attack_time_code;
-	gain_cfg.decay_time = (enum apm_gain_ramp_time) decay_time_code;
-	gain_cfg.gain_max = (enum apm_gain_values) max_applied_gain_code;
-	gain_cfg.gain_min = (enum apm_gain_values) min_applied_gain_code;
+	gain_cfg.nois_gate_thold = (enum apm_noise_gate_threshold)ngth_code;
+	gain_cfg.hold_time = (enum apm_agc_adj_hold_time)hold_time;
+	gain_cfg.attack_time = (enum apm_gain_ramp_time)attack_time_code;
+	gain_cfg.decay_time = (enum apm_gain_ramp_time)decay_time_code;
+	gain_cfg.gain_max = (enum apm_gain_values)max_applied_gain_code;
+	gain_cfg.gain_min = (enum apm_gain_values)min_applied_gain_code;
 
 	ret_code = apm_adc_auto_gain_config(&gain_cfg);
 
@@ -1676,7 +1670,6 @@ enum ec_error_list wov_set_agc_config(int stereo, float target,
  */
 int wov_set_vad_sensitivity(int sensitivity_db)
 {
-
 	if ((sensitivity_db < 0) || (sensitivity_db > 31))
 		return EC_ERROR_INVAL;
 
@@ -1752,27 +1745,27 @@ void wov_set_i2s_bclk(uint32_t i2s_clock)
  * @return  EC error code.
  */
 enum ec_error_list wov_set_i2s_tdm_config(int ch0_delay, int ch1_delay,
-				uint32_t flags)
+					  uint32_t flags)
 {
 	if (wov_conf.mode != WOV_MODE_OFF)
 		return EC_ERROR_INVALID_CONFIG;
 
-	if ((ch0_delay < 0) || (ch0_delay > 496) ||
-		(ch1_delay < -1) || (ch1_delay > 496))
+	if ((ch0_delay < 0) || (ch0_delay > 496) || (ch1_delay < -1) ||
+	    (ch1_delay > 496))
 		return EC_ERROR_INVAL;
 
 	wov_conf.i2s_start_delay_0 = ch0_delay;
 	wov_conf.i2s_start_delay_1 = ch1_delay;
 
 	SET_FIELD(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL_I2S_ST_DEL,
-			ch0_delay);
+		  ch0_delay);
 
 	if (ch1_delay == -1)
 		wov_i2s_channel1_disable(1);
 	else {
 		wov_i2s_channel1_disable(0);
 		SET_FIELD(NPCX_WOV_I2S_CNTL(1), NPCX_WOV_I2S_CNTL_I2S_ST_DEL,
-			ch1_delay);
+			  ch1_delay);
 	}
 
 	if (flags & 0x0001)
@@ -1820,10 +1813,10 @@ void wov_handle_event(enum wov_events event)
 }
 
 #ifdef DEBUG_AUDIO_CODEC
-static uint32_t voice_buffer[VOICE_BUF_SIZE] = {0};
+static uint32_t voice_buffer[VOICE_BUF_SIZE] = { 0 };
 
 /* voice data 16Khz 2ch 16bit 1s */
-static int command_wov(int argc, char **argv)
+static int command_wov(int argc, const char **argv)
 {
 	static int bit_clk;
 	static enum wov_dai_format i2s_fmt;
@@ -1845,8 +1838,9 @@ static int command_wov(int argc, char **argv)
 		/* Start to capature voice data and store in RAM buffer */
 		if (strcasecmp(argv[1], "capram") == 0) {
 			if (wov_set_buffer((uint32_t *)voice_buffer,
-				sizeof(voice_buffer) / sizeof(uint32_t))
-					== EC_SUCCESS) {
+					   sizeof(voice_buffer) /
+						   sizeof(uint32_t)) ==
+			    EC_SUCCESS) {
 				CPRINTS("Start RAM Catpure...");
 				wov_start_ram_capture();
 				return EC_SUCCESS;
@@ -1980,8 +1974,9 @@ static int command_wov(int argc, char **argv)
 				wov_set_mode(WOV_MODE_VAD);
 			} else if (strcasecmp(argv[2], "ram") == 0) {
 				if (wov_set_buffer((uint32_t *)voice_buffer,
-					sizeof(voice_buffer) / sizeof(uint32_t))
-						== EC_SUCCESS)
+						   sizeof(voice_buffer) /
+							   sizeof(uint32_t)) ==
+				    EC_SUCCESS)
 					wov_set_mode(WOV_MODE_RAM);
 				else
 					return EC_ERROR_INVAL;
@@ -1989,8 +1984,9 @@ static int command_wov(int argc, char **argv)
 				wov_set_mode(WOV_MODE_I2S);
 			} else if (strcasecmp(argv[2], "rami2s") == 0) {
 				if (wov_set_buffer((uint32_t *)voice_buffer,
-					sizeof(voice_buffer) / sizeof(uint32_t))
-						== EC_SUCCESS)
+						   sizeof(voice_buffer) /
+							   sizeof(uint32_t)) ==
+				    EC_SUCCESS)
 					wov_set_mode(WOV_MODE_RAM_AND_I2S);
 				else
 					return EC_ERROR_INVAL;
@@ -2013,7 +2009,7 @@ static int command_wov(int argc, char **argv)
 		if (strcasecmp(argv[1], "fmul2") == 0) {
 			if (strcasecmp(argv[2], "enable") == 0) {
 				CLEAR_BIT(NPCX_FMUL2_FM2CTRL,
-					NPCX_FMUL2_FM2CTRL_TUNE_DIS);
+					  NPCX_FMUL2_FM2CTRL_TUNE_DIS);
 				return EC_SUCCESS;
 			}
 			if (strcasecmp(argv[2], "disable") == 0) {
@@ -2050,22 +2046,22 @@ static int command_wov(int argc, char **argv)
 }
 
 DECLARE_CONSOLE_COMMAND(wov, command_wov,
-		"init\n"
-		"mute <enable|disable>\n"
-		"capram\n"
-		"cfgsrc <mono|stereo|left|right>\n"
-		"cfgbit <16|18|20|24>\n"
-		"cfgsfs <8000|12000|16000|24000|32000|48000>\n"
-		"cfgbck <32fs|48fs|64fs|128fs|256fs>\n"
-		"cfgfmt <i2s|right|left|pcma|pcmb|tdm>\n"
-		"cfgmod <off|vad|ram|i2s|rami2s>\n"
-		"cfgtdm [0~496 0~496 0~3]>\n"
-		"cfgdckV <0.75|1.0|1.2|2.4|3.0>\n"
-		"cfgdckR <0.75|1.0|1.2|2.4|3.0>\n"
-		"cfgdckI <0.75|1.0|1.2|2.4|3.0>\n"
-		"cfgget\n"
-		"fmul2 <enable|disable>\n"
-		"vadsens <0~31>\n"
-		"gain <0~31>",
-		"wov configuration");
+			"init\n"
+			"mute <enable|disable>\n"
+			"capram\n"
+			"cfgsrc <mono|stereo|left|right>\n"
+			"cfgbit <16|18|20|24>\n"
+			"cfgsfs <8000|12000|16000|24000|32000|48000>\n"
+			"cfgbck <32fs|48fs|64fs|128fs|256fs>\n"
+			"cfgfmt <i2s|right|left|pcma|pcmb|tdm>\n"
+			"cfgmod <off|vad|ram|i2s|rami2s>\n"
+			"cfgtdm [0~496 0~496 0~3]>\n"
+			"cfgdckV <0.75|1.0|1.2|2.4|3.0>\n"
+			"cfgdckR <0.75|1.0|1.2|2.4|3.0>\n"
+			"cfgdckI <0.75|1.0|1.2|2.4|3.0>\n"
+			"cfgget\n"
+			"fmul2 <enable|disable>\n"
+			"vadsens <0~31>\n"
+			"gain <0~31>",
+			"wov configuration");
 #endif
diff --git a/chip/npcx/wov_chip.h b/chip/npcx/wov_chip.h
index dce534c501..b0da9128e1 100644
--- a/chip/npcx/wov_chip.h
+++ b/chip/npcx/wov_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -34,10 +34,7 @@ enum wov_mic_source {
 };
 
 /* Clock source for APM. */
-enum wov_clk_src_sel {
-	WOV_FMUL2_CLK_SRC = 0,
-	WOV_PLL_CLK_SRC = 1
-};
+enum wov_clk_src_sel { WOV_FMUL2_CLK_SRC = 0, WOV_PLL_CLK_SRC = 1 };
 
 /* FMUL clock division factore. */
 enum wov_fmul_div {
@@ -48,10 +45,7 @@ enum wov_fmul_div {
 };
 
 /* Lock state. */
-enum wov_lock_state {
-	WOV_UNLOCK = 0,
-	WOV_LOCK = 1
-};
+enum wov_lock_state { WOV_UNLOCK = 0, WOV_LOCK = 1 };
 
 /* Reference clock source select. */
 enum wov_ref_clk_src_sel {
@@ -60,10 +54,7 @@ enum wov_ref_clk_src_sel {
 };
 
 /* PLL external divider select. */
-enum wov_ext_div_sel {
-	WOV_EXT_DIV_BINARY_CNT = 0,
-	WOV_EXT_DIV_LFSR_DIV = 1
-};
+enum wov_ext_div_sel { WOV_EXT_DIV_BINARY_CNT = 0, WOV_EXT_DIV_LFSR_DIV = 1 };
 
 /* FMUL output frequency. */
 enum wov_fmul_out_freq {
@@ -117,10 +108,7 @@ enum wov_interrupt_index {
 };
 
 /* FIFO DMA request selection. */
-enum wov_dma_req_sel {
-	WOV_DFLT_ESPI_DMA_REQ = 0,
-	WOV_FROM_FIFO_DMA_REQUEST
-};
+enum wov_dma_req_sel { WOV_DFLT_ESPI_DMA_REQ = 0, WOV_FROM_FIFO_DMA_REQUEST };
 
 /* Core FIFO input select. */
 enum wov_core_fifo_in_sel {
@@ -131,10 +119,7 @@ enum wov_core_fifo_in_sel {
 };
 
 /* PLL external divider selector. */
-enum wov_pll_ext_div_sel {
-	WOV_PLL_EXT_DIV_BIN_CNT = 0,
-	WOV_PLL_EXT_DIV_LFSR
-};
+enum wov_pll_ext_div_sel { WOV_PLL_EXT_DIV_BIN_CNT = 0, WOV_PLL_EXT_DIV_LFSR };
 
 /* Code for events for call back function. */
 enum wov_events {
@@ -144,7 +129,7 @@ enum wov_events {
 	 * need to call to wov_set_buffer to update the buffer * pointer
 	 */
 	WOV_EVENT_DATA_READY = 1,
-	WOV_EVENT_VAD,		  /* Voice activity detected */
+	WOV_EVENT_VAD, /* Voice activity detected */
 
 	WOV_EVENT_ERROR_FIRST = 128,
 	WOV_EVENT_ERROR_CORE_FIFO_OVERRUN = 128,
@@ -158,8 +143,8 @@ enum wov_events {
 enum wov_fifo_errors {
 	WOV_FIFO_NO_ERROR = 0,
 	WOV_CORE_FIFO_OVERRUN = 1, /* 2 : I2S FIFO is underrun. */
-	WOV_I2S_FIFO_OVERRUN = 2,  /* 3 : I2S FIFO is overrun.  */
-	WOV_I2S_FIFO_UNDERRUN = 3  /* 4 : I2S FIFO is underrun. */
+	WOV_I2S_FIFO_OVERRUN = 2, /* 3 : I2S FIFO is overrun.  */
+	WOV_I2S_FIFO_UNDERRUN = 3 /* 4 : I2S FIFO is underrun. */
 
 };
 
@@ -191,12 +176,12 @@ enum wov_modes {
 
 /* DAI format. */
 enum wov_dai_format {
-	WOV_DAI_FMT_I2S,     /* I2S mode			*/
+	WOV_DAI_FMT_I2S, /* I2S mode			*/
 	WOV_DAI_FMT_RIGHT_J, /* Right Justified mode		*/
-	WOV_DAI_FMT_LEFT_J,  /* Left Justified mode		*/
-	WOV_DAI_FMT_PCM_A,   /* PCM A Audio			*/
-	WOV_DAI_FMT_PCM_B,   /* PCM B Audio			*/
-	WOV_DAI_FMT_PCM_TDM  /* Time Division Multiplexing	*/
+	WOV_DAI_FMT_LEFT_J, /* Left Justified mode		*/
+	WOV_DAI_FMT_PCM_A, /* PCM A Audio			*/
+	WOV_DAI_FMT_PCM_B, /* PCM B Audio			*/
+	WOV_DAI_FMT_PCM_TDM /* Time Division Multiplexing	*/
 };
 
 struct wov_config {
@@ -375,10 +360,10 @@ void wov_enable_agc(int enable);
  * @param min_applied_gain      - Minimum Gain Value to apply to the ADC path.
  * @return  EC_ERROR_INVAL or EC_SUCCESS
  */
-enum ec_error_list wov_set_agc_config(int stereo, float target,
-		int noise_gate_threshold, uint8_t hold_time,
-		uint16_t attack_time, uint16_t decay_time,
-		float max_applied_gain, float min_applied_gain);
+enum ec_error_list
+wov_set_agc_config(int stereo, float target, int noise_gate_threshold,
+		   uint8_t hold_time, uint16_t attack_time, uint16_t decay_time,
+		   float max_applied_gain, float min_applied_gain);
 
 /**
  * Sets VAD sensitivity.
@@ -438,7 +423,7 @@ void wov_set_i2s_bclk(uint32_t i2s_clock);
  * @return  EC error code.
  */
 enum ec_error_list wov_set_i2s_tdm_config(int ch0_delay, int ch1_delay,
-				uint32_t flags);
+					  uint32_t flags);
 
 /**
  * Configure FMUL2 clock tunning.
@@ -477,8 +462,9 @@ extern void wov_set_clk_selection(enum wov_clk_src_sel clk_src);
  *                                PLL External Divider Load Values table.
  * @return  EC_ERROR_INVAL or EC_SUCCESS
  */
-enum ec_error_list wov_pll_clk_ext_div_config(
-	enum wov_pll_ext_div_sel ext_div_sel, uint32_t div_factor);
+enum ec_error_list
+wov_pll_clk_ext_div_config(enum wov_pll_ext_div_sel ext_div_sel,
+			   uint32_t div_factor);
 
 /**
  * PLL power down.
@@ -498,9 +484,9 @@ void wov_pll_enable(int enable);
  * @return  EC_ERROR_INVAL or EC_SUCCESS
  */
 enum ec_error_list wov_pll_clk_div_config(uint32_t out_div_1,
-			uint32_t out_div_2,
-			uint32_t feedback_div,
-			uint32_t in_div);
+					  uint32_t out_div_2,
+					  uint32_t feedback_div,
+					  uint32_t in_div);
 
 /**
  * Enables/Disables WoV interrupt.
@@ -521,7 +507,7 @@ void wov_interrupt_enable(enum wov_interrupt_index int_index, int enable);
  * @return  None
  */
 void wov_cfifo_config(enum wov_core_fifo_in_sel in_sel,
-			enum wov_fifo_threshold threshold);
+		      enum wov_fifo_threshold threshold);
 
 /**
  * Start the actual capturing of the Voice data to the RAM.
@@ -632,13 +618,10 @@ void wov_handle_event(enum wov_events event);
  * @return  EC_ERROR_INVAL or EC_SUCCESS
  */
 enum ec_error_list wov_i2s_global_config(
-	enum wov_floating_mode i2s_hiz_data,
-	enum wov_floating_mode i2s_hiz,
-	enum wov_clk_inverted_mode clk_invert,
-	int out_pull_en, enum wov_pull_upd_down_sel out_pull_mode,
-	int in_pull_en,
-	enum wov_pull_upd_down_sel in_pull_mode,
-	enum wov_test_mode test_mode);
+	enum wov_floating_mode i2s_hiz_data, enum wov_floating_mode i2s_hiz,
+	enum wov_clk_inverted_mode clk_invert, int out_pull_en,
+	enum wov_pull_upd_down_sel out_pull_mode, int in_pull_en,
+	enum wov_pull_upd_down_sel in_pull_mode, enum wov_test_mode test_mode);
 
 /**
  * I2S channel configuration
@@ -652,7 +635,8 @@ enum ec_error_list wov_i2s_global_config(
  * @return  EC_ERROR_INVAL or EC_SUCCESS
  */
 enum ec_error_list wov_i2s_channel_config(uint32_t channel_num,
-			uint32_t bit_count, enum wov_i2s_chan_trigger trigger,
-			int32_t start_delay);
+					  uint32_t bit_count,
+					  enum wov_i2s_chan_trigger trigger,
+					  int32_t start_delay);
 
 #endif /* __CROS_EC_WOV_CHIP_H */
diff --git a/chip/nrf51/bluetooth_le.c b/chip/nrf51/bluetooth_le.c
deleted file mode 100644
index 89eb117efd..0000000000
--- a/chip/nrf51/bluetooth_le.c
+++ /dev/null
@@ -1,537 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "bluetooth_le.h"
-#include "include/bluetooth_le.h"
-#include "console.h"
-#include "ppi.h"
-#include "radio.h"
-#include "registers.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPUTS(outstr) cputs(CC_BLUETOOTH_LE, outstr)
-#define CPRINTS(format, args...) cprints(CC_BLUETOOTH_LE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_BLUETOOTH_LE, format, ## args)
-
-static void ble2nrf_packet(struct ble_pdu *ble_p,
-		struct nrf51_ble_packet_t *radio_p)
-{
-	if (ble_p->header_type_adv) {
-		radio_p->s0 = ble_p->header.adv.type & 0xf;
-		radio_p->s0 |= (ble_p->header.adv.txaddr ?
-			1 << BLE_ADV_HEADER_TXADD_SHIFT : 0);
-		radio_p->s0 |= (ble_p->header.adv.rxaddr ?
-			1 << BLE_ADV_HEADER_RXADD_SHIFT : 0);
-		radio_p->length = ble_p->header.adv.length & 0x3f; /* 6 bits */
-	} else {
-		radio_p->s0 = ble_p->header.data.llid & 0x3;
-		radio_p->s0 |= (ble_p->header.data.nesn ?
-			1 << BLE_DATA_HEADER_NESN_SHIFT : 0);
-		radio_p->s0 |= (ble_p->header.data.sn ?
-			1 << BLE_DATA_HEADER_SN_SHIFT : 0);
-		radio_p->s0 |= (ble_p->header.data.md ?
-			1 << BLE_DATA_HEADER_MD_SHIFT : 0);
-		radio_p->length = ble_p->header.data.length & 0x1f; /* 5 bits */
-	}
-
-	if (radio_p->length > 0)
-		memcpy(radio_p->payload, ble_p->payload, radio_p->length);
-}
-
-static void nrf2ble_packet(struct ble_pdu *ble_p,
-		struct nrf51_ble_packet_t *radio_p, int type_adv)
-{
-	if (type_adv) {
-		ble_p->header_type_adv = 1;
-		ble_p->header.adv.type = radio_p->s0 & 0xf;
-		ble_p->header.adv.txaddr = (radio_p->s0 &
-			BIT(BLE_ADV_HEADER_TXADD_SHIFT)) != 0;
-		ble_p->header.adv.rxaddr = (radio_p->s0 &
-			BIT(BLE_ADV_HEADER_RXADD_SHIFT)) != 0;
-		/* Length check? 6-37 Bytes */
-		ble_p->header.adv.length = radio_p->length;
-	} else {
-		ble_p->header_type_adv = 0;
-		ble_p->header.data.llid = radio_p->s0 & 0x3;
-		ble_p->header.data.nesn = (radio_p->s0 &
-			BIT(BLE_DATA_HEADER_NESN_SHIFT)) != 0;
-		ble_p->header.data.sn = (radio_p->s0 &
-			BIT(BLE_DATA_HEADER_SN_SHIFT)) != 0;
-		ble_p->header.data.md = (radio_p->s0 &
-			BIT(BLE_DATA_HEADER_MD_SHIFT)) != 0;
-		/* Length check? 0-31 Bytes */
-		ble_p->header.data.length = radio_p->length;
-	}
-
-	if (radio_p->length > 0)
-		memcpy(ble_p->payload, radio_p->payload, radio_p->length);
-}
-
-struct ble_pdu adv_packet;
-struct nrf51_ble_packet_t on_air_packet;
-
-struct ble_pdu rcv_packet;
-
-int ble_radio_init(uint32_t access_address, uint32_t crc_init_val)
-{
-	int rv = radio_init(BLE_1MBIT);
-
-	if (rv)
-		return rv;
-	NRF51_RADIO_CRCCNF = 3 | NRF51_RADIO_CRCCNF_SKIP_ADDR; /* 3-byte CRC */
-	/* x^24 + x^10 + x^9 + x^6 + x^4 + x^3 + x + 1 */
-	/* 0x1_0000_0000_0000_0110_0101_1011 */
-	NRF51_RADIO_CRCPOLY = 0x100065B;
-
-	NRF51_RADIO_CRCINIT = crc_init_val;
-
-	NRF51_RADIO_TXPOWER = NRF51_RADIO_TXPOWER_0_DBM;
-
-	NRF51_RADIO_BASE0 = access_address << 8;
-	NRF51_RADIO_PREFIX0 = access_address >> 24;
-
-	if (access_address != BLE_ADV_ACCESS_ADDRESS)
-		CPRINTF("Initializing radio for data packet.\n");
-
-	NRF51_RADIO_TXADDRESS = 0;
-	NRF51_RADIO_RXADDRESSES = 1;
-	NRF51_RADIO_PCNF0 = NRF51_RADIO_PCNF0_ADV_DATA;
-	NRF51_RADIO_PCNF1 = NRF51_RADIO_PCNF1_ADV_DATA;
-
-	return rv;
-
-}
-
-static struct nrf51_ble_packet_t tx_packet;
-
-static uint32_t tx_end, rsp_end;
-
-void ble_tx(struct ble_pdu *pdu)
-{
-	uint32_t timeout_time;
-
-	ble2nrf_packet(pdu, &tx_packet);
-
-	NRF51_RADIO_PACKETPTR = (uint32_t)&tx_packet;
-	NRF51_RADIO_END = NRF51_RADIO_PAYLOAD = NRF51_RADIO_ADDRESS = 0;
-	NRF51_RADIO_RXEN = 0;
-	NRF51_RADIO_TXEN = 1;
-
-	timeout_time = get_time().val + RADIO_SETUP_TIMEOUT;
-	while (!NRF51_RADIO_READY) {
-		if (get_time().val > timeout_time) {
-			CPRINTF("ERROR DURING RADIO TX SETUP. TRY AGAIN.\n");
-			return;
-		}
-	}
-
-	timeout_time = get_time().val + RADIO_SETUP_TIMEOUT;
-	while (!NRF51_RADIO_END) {
-		if (get_time().val > timeout_time) {
-			CPRINTF("RADIO DID NOT SHUT DOWN AFTER TX. "
-				"RECOMMEND REBOOT.\n");
-			return;
-		}
-	}
-	NRF51_RADIO_DISABLE = 1;
-}
-
-static struct nrf51_ble_packet_t rx_packet;
-int ble_rx(struct ble_pdu *pdu, int timeout, int adv)
-{
-	uint32_t done;
-	uint32_t timeout_time;
-	int ppi_channel_requested;
-
-	/* Prevent illegal wait times */
-	if (timeout <= 0) {
-		NRF51_RADIO_DISABLE = 1;
-		return EC_ERROR_TIMEOUT;
-	}
-
-	NRF51_RADIO_PACKETPTR = (uint32_t)&rx_packet;
-	NRF51_RADIO_END = NRF51_RADIO_PAYLOAD = NRF51_RADIO_ADDRESS = 0;
-	/*
-	 * These shortcuts cause packet transmission 150 microseconds after
-	 * packet receive, as is the BTLE standard. See NRF51 manual:
-	 * section 17.1.12
-	 */
-	NRF51_RADIO_SHORTS = NRF51_RADIO_SHORTS_READY_START |
-			NRF51_RADIO_SHORTS_DISABLED_TXEN |
-			NRF51_RADIO_SHORTS_END_DISABLE;
-
-	/*
-	 * This creates a shortcut that marks the time
-	 * that the payload was received by the radio
-	 * in NRF51_TIMER_CC(0,1)
-	 */
-	ppi_channel_requested = NRF51_PPI_CH_RADIO_ADDR__TIMER0CC1;
-	if (ppi_request_channel(&ppi_channel_requested) == EC_SUCCESS) {
-		NRF51_PPI_CHEN |= BIT(ppi_channel_requested);
-		NRF51_PPI_CHENSET |= BIT(ppi_channel_requested);
-	}
-
-
-	NRF51_RADIO_RXEN = 1;
-
-	timeout_time = get_time().val + RADIO_SETUP_TIMEOUT;
-	while (!NRF51_RADIO_READY) {
-		if (get_time().val > timeout_time) {
-			CPRINTF("RADIO NOT SET UP IN TIME. TIMING OUT.\n");
-			return EC_ERROR_TIMEOUT;
-		}
-	}
-
-	timeout_time = get_time().val + timeout;
-	do {
-		if (get_time().val >= timeout_time) {
-			NRF51_RADIO_DISABLE = 1;
-			return EC_ERROR_TIMEOUT;
-		}
-		done = NRF51_RADIO_END;
-	} while (!done);
-
-	rsp_end = get_time().le.lo;
-
-	if (NRF51_RADIO_CRCSTATUS == 0) {
-		CPRINTF("INVALID CRC\n");
-		return EC_ERROR_CRC;
-	}
-
-	nrf2ble_packet(pdu, &rx_packet, adv);
-
-	/*
-	 * Throw error if radio not yet disabled. Something has
-	 * gone wrong. May be in an unexpected state.
-	 */
-	if (NRF51_RADIO_DISABLED != 1)
-		return EC_ERROR_UNKNOWN;
-
-	return EC_SUCCESS;
-}
-
-/* Allow list handling */
-int ble_radio_clear_allow_list(void)
-{
-	NRF51_RADIO_DACNF = 0;
-	return EC_SUCCESS;
-}
-
-int ble_radio_read_allow_list_size(uint8_t *ret_size)
-{
-	int i, size = 0;
-	uint32_t dacnf = NRF51_RADIO_DACNF;
-
-	/* Count the bits that are set */
-	for (i = 0; i < NRF51_RADIO_DACNF_MAX; i++)
-		if (dacnf & NRF51_RADIO_DACNF_ENA(i))
-			size++;
-
-	*ret_size = size;
-
-	return EC_SUCCESS;
-}
-
-int ble_radio_add_device_to_allow_list(const uint8_t *addr_ptr, uint8_t rand)
-{
-	uint32_t dacnf = NRF51_RADIO_DACNF;
-	int i;
-	uint32_t aligned;
-
-	/* Check for duplicates using ble_radio_remove_device? */
-
-	/* Find a free entry */
-	for (i = 0; i < NRF51_RADIO_DACNF_MAX &&
-		(dacnf & NRF51_RADIO_DACNF_ENA(i)); i++)
-		;
-
-	if (i == NRF51_RADIO_DACNF_MAX)
-		return EC_ERROR_OVERFLOW;
-
-	memcpy(&aligned, addr_ptr, 4);
-	NRF51_RADIO_DAB(i) = aligned;
-	memcpy(&aligned, addr_ptr + 4, 2);
-	NRF51_RADIO_DAP(i) = aligned;
-
-	NRF51_RADIO_DACNF = dacnf | NRF51_RADIO_DACNF_ENA(i) |
-		(rand ? NRF51_RADIO_DACNF_TXADD(i) : 0);
-
-	return EC_SUCCESS;
-}
-
-int ble_radio_remove_device_from_allow_list(const uint8_t *addr_ptr,
-					    uint8_t rand)
-{
-	int i, dacnf = NRF51_RADIO_DACNF;
-
-	/* Find a matching entry */
-	for (i = 0; i < NRF51_RADIO_DACNF_MAX; i++) {
-		uint32_t dab = NRF51_RADIO_DAB(i), dap = NRF51_RADIO_DAP(i);
-
-		if ((dacnf & NRF51_RADIO_DACNF_ENA(i)) && /* Enabled */
-		    /* Rand flag matches */
-		    (rand == ((dacnf & NRF51_RADIO_DACNF_TXADD(i)) != 0)) &&
-		    /* Address matches */
-		    (!memcmp(addr_ptr, &dab, 4)) &&
-		    (!memcmp(addr_ptr + 4, &dap, 2)))
-			break;
-	}
-
-	if (i == NRF51_RADIO_DACNF_MAX) /* Not found is successfully removed */
-		return EC_SUCCESS;
-
-	NRF51_RADIO_DACNF = dacnf & ~((NRF51_RADIO_DACNF_ENA(i)) |
-		(rand ? NRF51_RADIO_DACNF_TXADD(i) : 0));
-
-	return EC_SUCCESS;
-}
-
-
-int ble_adv_packet(struct ble_pdu *adv_packet, int chan)
-{
-	int done;
-	int rv;
-
-	/* Change channel */
-	NRF51_RADIO_FREQUENCY = NRF51_RADIO_FREQUENCY_VAL(chan2freq(chan));
-	NRF51_RADIO_DATAWHITEIV = chan;
-
-	ble_tx(adv_packet);
-
-	do {
-		done = NRF51_RADIO_END;
-	} while (!done);
-
-	tx_end = get_time().le.lo;
-
-	if (adv_packet->header.adv.type ==
-	    BLE_ADV_HEADER_PDU_TYPE_ADV_NONCONN_IND)
-		return EC_SUCCESS;
-
-	rv = ble_rx(&rcv_packet, 16000, 1);
-
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	/* Check for valid responses */
-	switch (rcv_packet.header.adv.type) {
-	case BLE_ADV_HEADER_PDU_TYPE_SCAN_REQ:
-		/* Scan requests are only allowed for ADV_IND and SCAN_IND */
-		if (adv_packet->header.adv.type !=
-		     BLE_ADV_HEADER_PDU_TYPE_ADV_IND &&
-		    adv_packet->header.adv.type !=
-		     BLE_ADV_HEADER_PDU_TYPE_ADV_SCAN_IND)
-			return rv;
-		/* The advertising address needs to match */
-		if (memcmp(&rcv_packet.payload[BLUETOOTH_ADDR_OCTETS],
-		    &adv_packet->payload[0], BLUETOOTH_ADDR_OCTETS))
-			return rv;
-	break;
-	case BLE_ADV_HEADER_PDU_TYPE_CONNECT_REQ:
-		/* Connections are only allowed for two types of advertising */
-		if (adv_packet->header.adv.type !=
-		     BLE_ADV_HEADER_PDU_TYPE_ADV_IND &&
-		    adv_packet->header.adv.type !=
-		     BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND)
-			return rv;
-		/* The advertising address needs to match */
-		if (memcmp(&rcv_packet.payload[BLUETOOTH_ADDR_OCTETS],
-		    &adv_packet->payload[0], BLUETOOTH_ADDR_OCTETS))
-			return rv;
-		/* The InitAddr needs to match for Directed advertising */
-		if (adv_packet->header.adv.type ==
-		     BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND &&
-		    memcmp(&adv_packet->payload[BLUETOOTH_ADDR_OCTETS],
-			   &rcv_packet.payload[0], BLUETOOTH_ADDR_OCTETS))
-			return rv;
-	break;
-	default: /* Unhandled response packet */
-		return rv;
-	break;
-	}
-
-	dump_ble_packet(&rcv_packet);
-	CPRINTF("tx_end %u Response %u\n", tx_end, rsp_end);
-
-	return rv;
-}
-
-int ble_adv_event(struct ble_pdu *adv_packet)
-{
-	int chan;
-	int rv;
-
-	for (chan = 37; chan < 40; chan++) {
-		rv = ble_adv_packet(adv_packet, chan);
-		if (rv != EC_SUCCESS)
-			return rv;
-	}
-
-	return rv;
-}
-
-static void fill_header(struct ble_pdu *adv, int type, int txaddr, int rxaddr)
-{
-	adv->header_type_adv = 1;
-	adv->header.adv.type = type;
-	adv->header.adv.txaddr = txaddr ?
-		BLE_ADV_HEADER_RANDOM_ADDR : BLE_ADV_HEADER_PUBLIC_ADDR;
-	adv->header.adv.rxaddr = rxaddr ?
-		BLE_ADV_HEADER_RANDOM_ADDR : BLE_ADV_HEADER_PUBLIC_ADDR;
-	adv->header.adv.length = 0;
-}
-
-static int fill_payload(uint8_t *payload, uint64_t addr, int name_length)
-{
-	uint8_t *curr;
-
-	curr = pack_adv_addr(payload, addr);
-	curr = pack_adv(curr, name_length, GAP_COMPLETE_NAME,
-		"ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrs");
-	curr = pack_adv_int(curr, 2, GAP_APPEARANCE,
-			    GAP_APPEARANCE_HID_KEYBOARD);
-	curr = pack_adv_int(curr, 1, GAP_FLAGS,
-		GAP_FLAGS_LE_LIM_DISC | GAP_FLAGS_LE_NO_BR_EDR);
-	curr = pack_adv_int(curr, 2, GAP_COMP_16_BIT_UUID,
-			    GATT_SERVICE_HID_UUID);
-
-	return curr - payload;
-}
-
-static void fill_packet(struct ble_pdu *adv, uint64_t addr, int type,
-			int name_length)
-{
-	fill_header(adv, type, BLE_ADV_HEADER_RANDOM_ADDR,
-		    BLE_ADV_HEADER_PUBLIC_ADDR);
-
-	adv->header.adv.length = fill_payload(adv->payload, addr, name_length);
-}
-
-static int command_ble_adv(int argc, char **argv)
-{
-	int type, length, reps, interval;
-	uint64_t addr;
-	char *e;
-	int i;
-	int rv;
-
-	if (argc < 3 || argc > 5)
-		return EC_ERROR_PARAM_COUNT;
-
-	type = strtoi(argv[1], &e, 0);
-	if (*e || type < 0 || (type > 2 && type != 6))
-		return EC_ERROR_PARAM1;
-
-	length = strtoi(argv[2], &e, 0);
-	if (*e || length > 32)
-		return EC_ERROR_PARAM2;
-
-	if (argc >= 4) {
-		reps = strtoi(argv[3], &e, 0);
-		if (*e || reps < 0)
-			return EC_ERROR_PARAM3;
-	} else {
-		reps = 1;
-	}
-
-	if (argc >= 5) {
-		interval = strtoi(argv[4], &e, 0);
-		if (*e || interval < 0)
-			return EC_ERROR_PARAM4;
-	} else {
-		interval = 100000;
-	}
-
-	if (type == BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND && length != 12) {
-		length = 12;
-		CPRINTS("type DIRECT needs to have a length of 12");
-	}
-
-	rv = ble_radio_init(BLE_ADV_ACCESS_ADDRESS, BLE_ADV_CRCINIT);
-
-
-		CPRINTS("ADV @%pP", &adv_packet);
-
-	((uint32_t *)&addr)[0] = 0xA3A2A1A0 | type;
-	((uint32_t *)&addr)[1] = BLE_RANDOM_ADDR_MSBS_STATIC << 8 | 0x5A4;
-
-		fill_packet(&adv_packet, addr, type, length);
-
-	for (i = 0; i < reps; i++) {
-		ble_adv_event(&adv_packet);
-		usleep(interval);
-	}
-
-	return rv;
-}
-DECLARE_CONSOLE_COMMAND(ble_adv, command_ble_adv,
-			"type len [reps] [interval = 100000 (100ms)]",
-			"Send a BLE packet of type type of length len");
-
-static int command_ble_adv_scan(int argc, char **argv)
-{
-	int chan, packets, i;
-	int addr_lsbyte;
-	char *e;
-	int rv;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	chan = strtoi(argv[1], &e, 0);
-	if (*e || chan < 37 || chan > 39)
-		return EC_ERROR_PARAM1;
-
-	chan = strtoi(argv[1], &e, 0);
-	if (*e || chan < 37 || chan > 39)
-		return EC_ERROR_PARAM1;
-
-	if (argc >= 3) {
-		packets = strtoi(argv[2], &e, 0);
-		if (*e || packets < 0)
-			return EC_ERROR_PARAM2;
-	} else {
-		packets = 1;
-	}
-
-	if (argc >= 4) {
-		addr_lsbyte = strtoi(argv[3], &e, 0);
-		if (*e || addr_lsbyte > 255)
-			return EC_ERROR_PARAM3;
-	} else {
-		addr_lsbyte = -1;
-	}
-
-	rv = ble_radio_init(BLE_ADV_ACCESS_ADDRESS, BLE_ADV_CRCINIT);
-
-	/* Change channel */
-	NRF51_RADIO_FREQUENCY = NRF51_RADIO_FREQUENCY_VAL(chan2freq(chan));
-	NRF51_RADIO_DATAWHITEIV = chan;
-
-	CPRINTS("ADV Listen");
-	if (addr_lsbyte != -1)
-		CPRINTS("filtered (%x)", addr_lsbyte);
-
-	for (i = 0; i < packets; i++) {
-		rv = ble_rx(&rcv_packet, 1000000, 1);
-
-		if (rv == EC_ERROR_TIMEOUT)
-			continue;
-
-		if (addr_lsbyte == -1 || rcv_packet.payload[0] == addr_lsbyte)
-			dump_ble_packet(&rcv_packet);
-	}
-
-	rv = radio_disable();
-
-	CPRINTS("on_air payload rcvd %pP", &rx_packet);
-
-	return rv;
-}
-DECLARE_CONSOLE_COMMAND(ble_scan, command_ble_adv_scan,
-			"chan [num] [addr0]",
-			"Scan for [num] BLE packets on channel chan");
-
diff --git a/chip/nrf51/bluetooth_le.h b/chip/nrf51/bluetooth_le.h
deleted file mode 100644
index dbb3bccd6e..0000000000
--- a/chip/nrf51/bluetooth_le.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __NRF51_BLUETOOTH_LE_H
-#define __NRF51_BLUETOOTH_LE_H
-
-#include "common.h"
-#include "include/bluetooth_le.h"
-
-#define NRF51_BLE_LENGTH_BITS 8
-#define NRF51_BLE_S0_BYTES    1
-#define NRF51_BLE_S1_BITS     0 /* no s1 field */
-
-#define BLE_ACCESS_ADDRESS_BYTES 4
-#define EXTRA_RECEIVE_BYTES      0
-#define BLE_ADV_WHITEN           1
-
-#define RADIO_SETUP_TIMEOUT 1000
-
-/* Data and Advertisements have the same PCNF values */
-#define NRF51_RADIO_PCNF0_ADV_DATA \
-			NRF51_RADIO_PCNF0_VAL(NRF51_BLE_LENGTH_BITS, \
-			NRF51_BLE_S0_BYTES, \
-			NRF51_BLE_S1_BITS)
-
-#define NRF51_RADIO_PCNF1_ADV_DATA \
-			NRF51_RADIO_PCNF1_VAL(BLE_MAX_ADV_PAYLOAD_OCTETS, \
-		    EXTRA_RECEIVE_BYTES, \
-		    BLE_ACCESS_ADDRESS_BYTES - 1, \
-		    BLE_ADV_WHITEN)
-
-struct nrf51_ble_packet_t {
-	uint8_t s0; /* First byte */
-	uint8_t length; /* Length field */
-	uint8_t payload[BLE_MAX_DATA_PAYLOAD_OCTETS];
-} __packed;
-
-struct nrf51_ble_config_t {
-	uint8_t channel;
-	uint8_t address;
-	uint32_t crc_init;
-};
-
-/* Initialize the nRF51 radio for BLE */
-int ble_radio_init(uint32_t access_address, uint32_t crc_init_val);
-
-/* Transmit pdu on the radio */
-void ble_tx(struct ble_pdu *pdu);
-
-/* Receive a packet into pdu if one comes before the timeout */
-int ble_rx(struct ble_pdu *pdu, int timeout, int adv);
-
-/* Allow list handling */
-
-/* Clear the allow list */
-int ble_radio_clear_allow_list(void);
-
-/* Read the size of the allow list and assign it to ret_size */
-int ble_radio_read_allow_list_size(uint8_t *ret_size);
-
-/* Add the device with the address specified by addr_ptr and type */
-int ble_radio_add_device_to_allow_list(const uint8_t *addr_ptr, uint8_t type);
-
-/* Remove the device with the address specified by addr_ptr and type */
-int ble_radio_remove_device_from_allow_list(const uint8_t *addr_ptr,
-					    uint8_t type);
-
-#endif  /* __NRF51_BLUETOOTH_LE_H */
diff --git a/chip/nrf51/build.mk b/chip/nrf51/build.mk
deleted file mode 100644
index 7a7a33d402..0000000000
--- a/chip/nrf51/build.mk
+++ /dev/null
@@ -1,26 +0,0 @@
-# -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# nRF51822 chip specific files build
-#
-
-CORE:=cortex-m0
-# Force ARMv6-M ISA used by the Cortex-M0
-# For historical reasons gcc calls it armv6s-m: ARM used to have ARMv6-M
-# without "svc" instruction, but that was short-lived. ARMv6S-M was the option
-# with "svc". GCC kept that naming scheme even though the distinction is long
-# gone.
-CFLAGS_CPU+=-march=armv6s-m -mcpu=cortex-m0
-
-chip-y+=gpio.o system.o uart.o
-chip-y+=watchdog.o ppi.o
-
-chip-$(CONFIG_BLUETOOTH_LE)+=radio.o bluetooth_le.o
-chip-$(CONFIG_BLUETOOTH_LE_RADIO_TEST)+=radio_test.o
-chip-$(CONFIG_COMMON_TIMER)+=hwtimer.o clock.o
-chip-$(CONFIG_I2C)+=i2c.o
-ifndef CONFIG_KEYBOARD_NOT_RAW
-chip-$(HAS_TASK_KEYSCAN)+=keyboard_raw.o
-endif
diff --git a/chip/nrf51/clock.c b/chip/nrf51/clock.c
deleted file mode 100644
index fe56140175..0000000000
--- a/chip/nrf51/clock.c
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks and power management settings */
-
-void clock_init(void)
-{
-}
-
-int clock_get_freq(void)
-{
-	/* constant 16 MHz clock */
-	return 16000000;
-}
diff --git a/chip/nrf51/config_chip.h b/chip/nrf51/config_chip.h
deleted file mode 100644
index 7295ab9360..0000000000
--- a/chip/nrf51/config_chip.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_CHIP_H
-#define __CROS_EC_CONFIG_CHIP_H
-
-#include "core/cortex-m0/config_core.h"
-
-/* System stack size */
-#define CONFIG_STACK_SIZE 1024
-
-/* Idle task stack size */
-#define IDLE_TASK_STACK_SIZE 256
-
-/* Default task stack size */
-#define TASK_STACK_SIZE 512
-
-/* Larger task stack size, for hook task */
-#define LARGER_TASK_STACK_SIZE 640
-
-/* Interval between HOOK_TICK notifications */
-#define HOOK_TICK_INTERVAL_MS 500
-#define HOOK_TICK_INTERVAL    (HOOK_TICK_INTERVAL_MS * MSEC)
-
-/* Number of I2C ports */
-#define I2C_PORT_COUNT 2
-
-/*
- * --- chip variant settings ---
- */
-
-/* RAM mapping */
-#define CONFIG_RAM_BASE         0x20000000
-#define CONFIG_RAM_SIZE         0x00004000
-
-/* Flash mapping */
-#define CONFIG_PROGRAM_MEMORY_BASE 0x00000000
-#define CONFIG_FLASH_SIZE 0x00040000
-#define CONFIG_FLASH_BANK_SIZE  0x1000
-
-/* Memory-mapped internal flash */
-#define CONFIG_INTERNAL_STORAGE
-#define CONFIG_MAPPED_STORAGE
-
-/* Program is run directly from storage */
-#define CONFIG_MAPPED_STORAGE_BASE CONFIG_PROGRAM_MEMORY_BASE
-
-/* Compute the rest of the flash params from these */
-#include "config_std_internal_flash.h"
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT 32
-
-/* Not that much RAM, set to smaller */
-#undef  CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 1024
-
-#define GPIO_PIN(port, index) GPIO_##port, BIT(index)
-#define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m)
-
-#endif /* __CROS_EC_CONFIG_CHIP_H */
-
diff --git a/chip/nrf51/gpio.c b/chip/nrf51/gpio.c
deleted file mode 100644
index 53694b5a74..0000000000
--- a/chip/nrf51/gpio.c
+++ /dev/null
@@ -1,311 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-/*
- * For each interrupt (INT0-INT3, PORT), record which GPIO entry uses it.
- */
-
-static const struct gpio_info *gpio_ints[NRF51_GPIOTE_IN_COUNT];
-static const struct gpio_info *gpio_int_port;
-
-volatile uint32_t * const nrf51_alt_funcs[] = {
-	/* UART */
-	&NRF51_UART_PSELRTS,
-	&NRF51_UART_PSELTXD,
-	&NRF51_UART_PSELCTS,
-	&NRF51_UART_PSELRXD,
-	/* SPI1 (SPI Master) */
-	&NRF51_SPI0_PSELSCK,
-	&NRF51_SPI0_PSELMOSI,
-	&NRF51_SPI0_PSELMISO,
-	/* TWI0 (I2C) */
-	&NRF51_TWI0_PSELSCL,
-	&NRF51_TWI0_PSELSDA,
-	/* SPI1 (SPI Master) */
-	&NRF51_SPI1_PSELSCK,
-	&NRF51_SPI1_PSELMOSI,
-	&NRF51_SPI1_PSELMISO,
-	/* TWI1 (I2C) */
-	&NRF51_TWI1_PSELSCL,
-	&NRF51_TWI1_PSELSDA,
-	/* SPIS1 (SPI SLAVE) */
-	&NRF51_SPIS1_PSELSCK,
-	&NRF51_SPIS1_PSELMISO,
-	&NRF51_SPIS1_PSELMOSI,
-	&NRF51_SPIS1_PSELCSN,
-	/* QDEC (ROTARY DECODER) */
-	&NRF51_QDEC_PSELLED,
-	&NRF51_QDEC_PSELA,
-	&NRF51_QDEC_PSELB,
-	/* LPCOMP (Low Power Comparator) */
-	&NRF51_LPCOMP_PSEL,
-};
-
-const unsigned int nrf51_alt_func_count = ARRAY_SIZE(nrf51_alt_funcs);
-
-/* Make sure the function table and defines stay in sync */
-BUILD_ASSERT(ARRAY_SIZE(nrf51_alt_funcs) == NRF51_MAX_ALT_FUNCS &&
-	NRF51_MAX_ALT_FUNCS <= GPIO_ALT_FUNC_MAX);
-
-void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
-{
-	uint32_t val = 0;
-	uint32_t bit = GPIO_MASK_TO_NUM(mask);
-
-	if (flags & GPIO_OUTPUT)
-		val |= NRF51_PIN_CNF_DIR_OUTPUT;
-	else if (flags & GPIO_INPUT)
-		val |= NRF51_PIN_CNF_DIR_INPUT;
-
-	if (flags & GPIO_PULL_DOWN)
-		val |= NRF51_PIN_CNF_PULLDOWN;
-	else if (flags & GPIO_PULL_UP)
-		val |= NRF51_PIN_CNF_PULLUP;
-
-	/* TODO: Drive strength? H0D1? */
-	if (flags & GPIO_OPEN_DRAIN)
-		val |= NRF51_PIN_CNF_DRIVE_S0D1;
-
-	if (flags & GPIO_OUTPUT) {
-		if (flags & GPIO_HIGH)
-			NRF51_GPIO0_OUTSET = mask;
-		else if (flags & GPIO_LOW)
-			NRF51_GPIO0_OUTCLR = mask;
-	}
-
-	/* Interrupt levels */
-	if (flags & GPIO_INT_SHARED) {
-		/*
-		 * There are no shared edge-triggered interrupts;
-		 * they're either high or low.
-		 */
-		ASSERT((flags & (GPIO_INT_F_RISING | GPIO_INT_F_FALLING)) == 0);
-		ASSERT((flags & GPIO_INT_LEVEL) != GPIO_INT_LEVEL);
-		if (flags & GPIO_INT_F_LOW)
-			val |= NRF51_PIN_CNF_SENSE_LOW;
-		else if (flags & GPIO_INT_F_HIGH)
-			val |= NRF51_PIN_CNF_SENSE_HIGH;
-	}
-
-	NRF51_PIN_CNF(bit) = val;
-}
-
-
-static void gpio_init(void)
-{
-	task_enable_irq(NRF51_PERID_GPIOTE);
-}
-DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
-
-
-test_mockable int gpio_get_level(enum gpio_signal signal)
-{
-	return !!(NRF51_GPIO0_IN & gpio_list[signal].mask);
-}
-
-void gpio_set_level(enum gpio_signal signal, int value)
-{
-	if (value)
-		NRF51_GPIO0_OUTSET = gpio_list[signal].mask;
-	else
-		NRF51_GPIO0_OUTCLR = gpio_list[signal].mask;
-}
-
-
-void gpio_pre_init(void)
-{
-	const struct gpio_info *g = gpio_list;
-	int is_warm = 0;
-	int i;
-
-	if (NRF51_POWER_RESETREAS &
-			(NRF51_POWER_RESETREAS_OFF | /* GPIO Wake */
-			 NRF51_POWER_RESETREAS_LPCOMP)) {
-		/* This is a warm reboot */
-		is_warm = 1;
-	}
-
-	/* Initialize Interrupt configuration */
-	for (i = 0; i < NRF51_GPIOTE_IN_COUNT; i++)
-		gpio_ints[i] = NULL;
-	gpio_int_port = NULL;
-
-	/* Set all GPIOs to defaults */
-	for (i = 0; i < GPIO_COUNT; i++, g++) {
-		int flags = g->flags;
-
-		if (flags & GPIO_DEFAULT)
-			continue;
-
-		/*
-		 * If this is a warm reboot, don't set the output levels again.
-		 */
-		if (is_warm)
-			flags &= ~(GPIO_LOW | GPIO_HIGH);
-
-		/* Set up GPIO based on flags */
-		gpio_set_flags_by_mask(g->port, g->mask, flags);
-	}
-}
-
-/*
- * NRF51 doesn't have an alternate function table.
- * Use the pin select registers in place of the function number.
- */
-void gpio_set_alternate_function(uint32_t port, uint32_t mask,
-				enum gpio_alternate_func func)
-{
-	uint32_t bit = GPIO_MASK_TO_NUM(mask);
-
-	ASSERT((~mask & BIT(bit)) == 0); /* Only one bit set. */
-	ASSERT(port == GPIO_0);
-	ASSERT((func >= GPIO_ALT_FUNC_DEFAULT && func < nrf51_alt_func_count) ||
-		func == GPIO_ALT_FUNC_NONE);
-
-	/* Remove the previous setting(s) */
-	if (func == GPIO_ALT_FUNC_NONE) {
-		int i;
-		for (i = 0; i < nrf51_alt_func_count; i++) {
-			if (*(nrf51_alt_funcs[i]) == bit)
-				*(nrf51_alt_funcs[i]) = 0xffffffff;
-		}
-	} else {
-		*(nrf51_alt_funcs[func]) = bit;
-	}
-}
-
-
-/*
- *  Enable the interrupt associated with the "signal"
- *  The architecture has one general (PORT)
- *  and NRF51_GPIOTE_IN_COUNT single-pin (IN0, IN1, ...) interrupts.
- *
- */
-int gpio_enable_interrupt(enum gpio_signal signal)
-{
-	int pin;
-	const struct gpio_info *g = gpio_list + signal;
-
-	/* Fail if not implemented or no interrupt handler */
-	if (!g->mask || signal >= GPIO_IH_COUNT)
-		return EC_ERROR_INVAL;
-
-	/* If it's not shared, use INT0-INT3, otherwise use PORT. */
-	if (!(g->flags & GPIO_INT_SHARED)) {
-		int int_num, free_slot = -1;
-		uint32_t event_config = 0;
-
-		for (int_num = 0; int_num < NRF51_GPIOTE_IN_COUNT; int_num++) {
-			if (gpio_ints[int_num] == g)
-				return EC_SUCCESS; /* This is already set up. */
-
-			if (gpio_ints[int_num] == NULL && free_slot == -1)
-				free_slot = int_num;
-		}
-
-		ASSERT(free_slot != -1);
-
-		gpio_ints[free_slot] = g;
-		pin = GPIO_MASK_TO_NUM(g->mask);
-		event_config = (pin << NRF51_GPIOTE_PSEL_POS) |
-			NRF51_GPIOTE_MODE_EVENT;
-
-		ASSERT(g->flags & (GPIO_INT_F_RISING | GPIO_INT_F_FALLING));
-
-		/* RISING | FALLING = TOGGLE */
-		if (g->flags & GPIO_INT_F_RISING)
-			event_config |= NRF51_GPIOTE_POLARITY_LOTOHI;
-		if (g->flags & GPIO_INT_F_FALLING)
-			event_config |= NRF51_GPIOTE_POLARITY_HITOLO;
-
-		NRF51_GPIOTE_CONFIG(free_slot) = event_config;
-
-		/* Enable the IN[] interrupt. */
-		NRF51_GPIOTE_INTENSET = 1 << free_slot;
-
-	} else {
-		/* The first handler for the shared interrupt wins. */
-		if (gpio_int_port == NULL) {
-			gpio_int_port = g;
-
-			/* Enable the PORT interrupt. */
-			NRF51_GPIOTE_INTENSET = 1 << NRF51_GPIOTE_PORT_BIT;
-		}
-	}
-
-	return EC_SUCCESS;
-}
-
-/*
- *  Disable the interrupt associated with the "signal"
- *  The architecture has one general (PORT)
- *  and NRF51_GPIOTE_IN_COUNT single-pin (IN0, IN1, ...) interrupts.
- */
-int gpio_disable_interrupt(enum gpio_signal signal)
-{
-	const struct gpio_info *g = gpio_list + signal;
-	int i;
-
-	/* Fail if not implemented or no interrupt handler */
-	if (!g->mask || signal >= GPIO_IH_COUNT)
-		return EC_ERROR_INVAL;
-
-	/* If it's not shared, use INT0-INT3, otherwise use PORT. */
-	if (!(g->flags & GPIO_INT_SHARED)) {
-		for (i = 0; i < NRF51_GPIOTE_IN_COUNT; i++) {
-			/* Remove matching handler. */
-			if (gpio_ints[i] == g) {
-				/* Disable the interrupt */
-				NRF51_GPIOTE_INTENCLR =
-					1 << NRF51_GPIOTE_IN_BIT(i);
-				/* Zero the handler */
-				gpio_ints[i] = NULL;
-			}
-		}
-	} else {
-		/* Disable the interrupt */
-		NRF51_GPIOTE_INTENCLR = 1 << NRF51_GPIOTE_PORT_BIT;
-		/* Zero the shared handler */
-		gpio_int_port = NULL;
-	}
-
-	return EC_SUCCESS;
-}
-
-/*
- * Clear interrupt and run handler.
- */
-void gpio_interrupt(void)
-{
-	const struct gpio_info *g;
-	int i;
-	int signal;
-
-	for (i = 0; i < NRF51_GPIOTE_IN_COUNT; i++) {
-		if (NRF51_GPIOTE_IN(i)) {
-			NRF51_GPIOTE_IN(i) = 0;
-			g = gpio_ints[i];
-			signal = g - gpio_list;
-			if (g && signal < GPIO_IH_COUNT)
-				gpio_irq_handlers[signal](signal);
-		}
-	}
-
-	if (NRF51_GPIOTE_PORT) {
-		NRF51_GPIOTE_PORT = 0;
-		g = gpio_int_port;
-		signal = g - gpio_list;
-		if (g && signal < GPIO_IH_COUNT)
-			gpio_irq_handlers[signal](signal);
-	}
-}
-DECLARE_IRQ(NRF51_PERID_GPIOTE, gpio_interrupt, 1);
diff --git a/chip/nrf51/hwtimer.c b/chip/nrf51/hwtimer.c
deleted file mode 100644
index 980a889657..0000000000
--- a/chip/nrf51/hwtimer.c
+++ /dev/null
@@ -1,179 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Hardware timers driver.
- *
- * nRF51x has one fully functional hardware counter, but 4 stand-alone
- * capture/compare (CC) registers.
- */
-
-#include "common.h"
-#include "console.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
-
-/*
- * capture/compare (CC) registers:
- *   CC_INTERRUPT -- used to interrupt next clock event.
- *   CC_CURRENT -- used to capture the current value.
- *   CC_OVERFLOW -- used to detect overflow on virtual timer (not hardware).
- */
-
-#define CC_INTERRUPT  0
-#define CC_CURRENT    1
-#define CC_OVERFLOW   2
-
-/* The nRF51 has 3 timers, use HWTIMER to specify which one is used here. */
-#define HWTIMER       0
-
-static uint32_t last_deadline;  /* cache of event set */
-
-/*
- * The nRF51x timer cannot be set to a specified value (reset to zero only).
- * Thus, we have to use a variable "shift" to maintain the offset between the
- * hardware value and virtual clock value.
- *
- * Once __hw_clock_source_set(ts) is called, the shift will be like:
- *
- *   virtual time  ------------------------------------------------
- *                  <----------> ^
- *                      shift    | ts
- *               0 |             |
- *   hardware      v
- *   counter time  ------------------------------------------------
- *
- *
- * Below diagram shows what it is when overflow happens.
- *
- *                       | now                                | prev_read
- *                       v                                    v
- *   virtual time  ------------------------------------------------
- *                 ---->                                    <------
- *                 shift                                      shift
- *                                                         |
- *   hardware                                              v
- *   counter time  ------------------------------------------------
- *
- */
-static uint32_t shift;
-
-void __hw_clock_event_set(uint32_t deadline)
-{
-	last_deadline = deadline;
-	NRF51_TIMER_CC(HWTIMER, CC_INTERRUPT) = deadline - shift;
-
-	/* enable interrupt */
-	NRF51_TIMER_INTENSET(HWTIMER) =
-		1 << NRF51_TIMER_COMPARE_BIT(CC_INTERRUPT);
-}
-
-uint32_t __hw_clock_event_get(void)
-{
-	return last_deadline;
-}
-
-void __hw_clock_event_clear(void)
-{
-	/* disable interrupt */
-	NRF51_TIMER_INTENCLR(HWTIMER) =
-		1 << NRF51_TIMER_COMPARE_BIT(CC_INTERRUPT);
-}
-
-uint32_t __hw_clock_source_read(void)
-{
-	/* to capture the current value */
-	NRF51_TIMER_CAPTURE(HWTIMER, CC_CURRENT) = 1;
-	return NRF51_TIMER_CC(HWTIMER, CC_CURRENT) + shift;
-}
-
-void __hw_clock_source_set(uint32_t ts)
-{
-	shift = ts;
-
-	/* reset counter to zero */
-	NRF51_TIMER_STOP(HWTIMER) = 1;
-	NRF51_TIMER_CLEAR(HWTIMER) = 1;
-
-	/* So that no interrupt until next __hw_clock_event_set() */
-	NRF51_TIMER_CC(HWTIMER, CC_INTERRUPT) = ts - 1;
-
-	/* Update the overflow point */
-	NRF51_TIMER_CC(HWTIMER, CC_OVERFLOW) = 0 - shift;
-
-	/* Start the timer again */
-	NRF51_TIMER_START(HWTIMER) = 1;
-}
-
-
-/* Interrupt handler for timer */
-void timer_irq(void)
-{
-	int overflow = 0;
-
-	/* clear status */
-	NRF51_TIMER_COMPARE(HWTIMER, CC_INTERRUPT) = 0;
-
-	if (NRF51_TIMER_COMPARE(HWTIMER, CC_OVERFLOW)) {
-		NRF51_TIMER_COMPARE(HWTIMER, CC_OVERFLOW) = 0;
-		overflow = 1;
-	}
-
-	process_timers(overflow);
-}
-
-/* DECLARE_IRQ doesn't like the NRF51_PERID_TIMER(n) macro */
-BUILD_ASSERT(NRF51_PERID_TIMER(HWTIMER) == NRF51_PERID_TIMER0);
-DECLARE_IRQ(NRF51_PERID_TIMER0, timer_irq, 1);
-
-int __hw_clock_source_init(uint32_t start_t)
-{
-
-	/* Start the high freq crystal oscillator */
-	NRF51_CLOCK_HFCLKSTART = 1;
-	/* TODO: check if the crystal oscillator is running (HFCLKSTAT) */
-
-	/* 32-bit timer mode */
-	NRF51_TIMER_MODE(HWTIMER) = NRF51_TIMER_MODE_TIMER;
-	NRF51_TIMER_BITMODE(HWTIMER) = NRF51_TIMER_BITMODE_32;
-
-	/*
-	 * The external crystal oscillator is 16MHz (HFCLK).
-	 * Set the prescaler to 16 so that the timer counter is increasing
-	 * every micro-second (us).
-	 */
-	NRF51_TIMER_PRESCALER(HWTIMER) = 4;  /* actual value is 2**4 = 16 */
-
-	/* Not to trigger interrupt until __hw_clock_event_set() is called. */
-	NRF51_TIMER_CC(HWTIMER, CC_INTERRUPT) = 0xffffffff;
-
-	/* Set to 0 so that the next overflow can trigger timer_irq(). */
-	NRF51_TIMER_CC(HWTIMER, CC_OVERFLOW) = 0;
-	NRF51_TIMER_INTENSET(HWTIMER) =
-		1 << NRF51_TIMER_COMPARE_BIT(CC_OVERFLOW);
-
-	/* Clear the timer counter */
-	NRF51_TIMER_CLEAR(HWTIMER) = 1;
-
-	/* Override the count with the start value now that counting has
-	 * started. */
-	__hw_clock_source_set(start_t);
-
-	/* Enable interrupt */
-	task_enable_irq(NRF51_PERID_TIMER(HWTIMER));
-
-	/* Start the timer */
-	NRF51_TIMER_START(HWTIMER) = 1;
-
-	return NRF51_PERID_TIMER(HWTIMER);
-}
-
diff --git a/chip/nrf51/i2c.c b/chip/nrf51/i2c.c
deleted file mode 100644
index 09a4a210e6..0000000000
--- a/chip/nrf51/i2c.c
+++ /dev/null
@@ -1,304 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "ppi.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-
-#define I2C_TIMEOUT 20000
-
-/* Keep track of the PPI channel used for each port */
-static int i2c_ppi_chan[] = {-1, -1};
-
-static void i2c_init_port(unsigned int port);
-
-/* board-specific setup for post-I2C module init */
-void __board_i2c_post_init(int port)
-{
-}
-
-void board_i2c_post_init(int port)
-		__attribute__((weak, alias("__board_i2c_post_init")));
-
-static void i2c_init_port(unsigned int port)
-{
-	NRF51_TWI_RXDRDY(port) = 0;
-	NRF51_TWI_TXDSENT(port) = 0;
-
-	NRF51_TWI_PSELSCL(port) = NRF51_TWI_SCL_PIN(port);
-	NRF51_TWI_PSELSDA(port) = NRF51_TWI_SDA_PIN(port);
-	NRF51_TWI_FREQUENCY(port) = NRF51_TWI_FREQ(port);
-
-	NRF51_PPI_CHENCLR = 1 << i2c_ppi_chan[port];
-
-	NRF51_PPI_EEP(i2c_ppi_chan[port]) = (uint32_t)&NRF51_TWI_BB(port);
-	NRF51_PPI_TEP(i2c_ppi_chan[port]) =
-		(uint32_t)&NRF51_TWI_SUSPEND(port);
-
-	/* Master enable */
-	NRF51_TWI_ENABLE(port) = NRF51_TWI_ENABLE_VAL;
-
-	if (!(i2c_raw_get_scl(port) && (i2c_raw_get_sda(port))))
-		CPRINTF("port %d could be wedged\n", port);
-}
-
-void i2c_init(void)
-{
-	int i, rv;
-
-	gpio_config_module(MODULE_I2C, 1);
-
-	for (i = 0; i < i2c_ports_used; i++) {
-		if (i2c_ppi_chan[i] == -1) {
-			rv = ppi_request_channel(&i2c_ppi_chan[i]);
-			ASSERT(rv == EC_SUCCESS);
-
-			i2c_init_port(i);
-		}
-	}
-}
-
-static void dump_i2c_reg(int port)
-{
-#ifdef CONFIG_I2C_DEBUG
-	CPRINTF("port      : %01d\n", port);
-	CPRINTF("Regs :\n");
-	CPRINTF(" 1: INTEN     : %08x\n", NRF51_TWI_INTEN(port));
-	CPRINTF(" 2: ERRORSRC  : %08x\n", NRF51_TWI_ERRORSRC(port));
-	CPRINTF(" 3: ENABLE    : %08x\n", NRF51_TWI_ENABLE(port));
-	CPRINTF(" 4: PSELSCL   : %08x\n", NRF51_TWI_PSELSCL(port));
-	CPRINTF(" 5: PSELSDA   : %08x\n", NRF51_TWI_PSELSDA(port));
-	CPRINTF(" 6: RXD       : %08x\n", NRF51_TWI_RXD(port));
-	CPRINTF(" 7: TXD       : %08x\n", NRF51_TWI_TXD(port));
-	CPRINTF(" 8: FREQUENCY : %08x\n", NRF51_TWI_FREQUENCY(port));
-	CPRINTF(" 9: ADDRESS   : %08x\n", NRF51_TWI_ADDRESS(port));
-	CPRINTF("Events :\n");
-	CPRINTF(" STOPPED   : %08x\n", NRF51_TWI_STOPPED(port));
-	CPRINTF(" RXDRDY    : %08x\n", NRF51_TWI_RXDRDY(port));
-	CPRINTF(" TXDSENT   : %08x\n", NRF51_TWI_TXDSENT(port));
-	CPRINTF(" ERROR     : %08x\n", NRF51_TWI_ERROR(port));
-	CPRINTF(" BB        : %08x\n", NRF51_TWI_BB(port));
-#endif /* CONFIG_I2C_DEBUG */
-}
-
-static void i2c_recover(int port)
-{
-	/*
-	 * Recovery of the TWI peripheral:
-	 * To recover a TWI peripheral that has been locked up you must use
-	 * the following code.
-	 * After the recover function it is important to reconfigure all
-	 * relevant TWI registers explicitly to ensure that it operates
-	 * correctly.
-	 *    TWI0:
-	 *      NRF_TWI0->ENABLE =
-	 *         TWI_ENABLE_ENABLE_Disabled << TWI_ENABLE_ENABLE_Pos;
-	 *      *(uint32_t *)(NRF_TWI0_BASE + 0xFFC) = 0;
-	 *      nrf_delay_us(5);
-	 *      *(uint32_t *)(NRF_TWI0_BASE + 0xFFC) = 1;
-	 *      NRF_TWI0->ENABLE =
-	 *         TWI_ENABLE_ENABLE_Enabled << TWI_ENABLE_ENABLE_Pos;
-	 */
-	NRF51_TWI_ENABLE(port) = NRF51_TWI_DISABLE_VAL;
-	NRF51_TWI_POWER(port) = 0;
-	udelay(5);
-	NRF51_TWI_POWER(port) = 1;
-
-	i2c_init_port(port);
-}
-
-static void handle_i2c_error(int port, int rv)
-{
-	if (rv == EC_SUCCESS)
-		return;
-
-#ifdef CONFIG_I2C_DEBUG
-	if (rv != EC_ERROR_TIMEOUT)
-		CPRINTF("handle_i2c_error %d\n", rv);
-	else
-		CPRINTF("handle_i2c_error: Timeout\n");
-
-	dump_i2c_reg(port);
-#endif
-
-	/* This may be a little too heavy handed. */
-	i2c_recover(port);
-}
-
-static int i2c_master_write(const int port, const uint16_t slave_addr_flags,
-			    const uint8_t *data, int size, int stop)
-{
-	int bytes_sent;
-	int timeout = I2C_TIMEOUT;
-
-	NRF51_TWI_ADDRESS(port) = I2C_GET_ADDR(slave_addr_flags);
-
-	/* Clear the sent bit */
-	NRF51_TWI_TXDSENT(port) = 0;
-
-	for (bytes_sent = 0; bytes_sent < size; bytes_sent++) {
-		/*Send a byte */
-		NRF51_TWI_TXD(port) = data[bytes_sent];
-
-		/* Only send a start for the first byte */
-		if (bytes_sent == 0)
-			NRF51_TWI_STARTTX(port) = 1;
-
-		/* Wait for ACK/NACK */
-		timeout = I2C_TIMEOUT;
-		while (timeout > 0 && NRF51_TWI_TXDSENT(port) == 0 &&
-				NRF51_TWI_ERROR(port) == 0)
-			timeout--;
-
-		if (timeout == 0)
-			return EC_ERROR_TIMEOUT;
-
-		if (NRF51_TWI_ERROR(port))
-			return EC_ERROR_UNKNOWN;
-
-		/* Clear the sent bit */
-		NRF51_TWI_TXDSENT(port) = 0;
-	}
-
-	if (stop) {
-		NRF51_TWI_STOPPED(port) = 0;
-		NRF51_TWI_STOP(port) = 1;
-		timeout = 10;
-		while (NRF51_TWI_STOPPED(port) == 0 && timeout > 0)
-			timeout--;
-	}
-
-	return EC_SUCCESS;
-}
-
-static int i2c_master_read(const int port, const uint16_t slave_addr_flags,
-			   uint8_t *data, int size)
-{
-	int curr_byte;
-	int timeout = I2C_TIMEOUT;
-
-	NRF51_TWI_ADDRESS(port) = I2C_GET_ADDR(slave_addr_flags);
-
-	if (size == 1) /* Last byte: stop after this one. */
-		NRF51_PPI_TEP(i2c_ppi_chan[port]) =
-			(uint32_t)&NRF51_TWI_STOP(port);
-	else
-		NRF51_PPI_TEP(i2c_ppi_chan[port]) =
-			(uint32_t)&NRF51_TWI_SUSPEND(port);
-	NRF51_PPI_CHENSET = 1 << i2c_ppi_chan[port];
-
-	NRF51_TWI_RXDRDY(port) = 0;
-	NRF51_TWI_STARTRX(port) = 1;
-
-	for (curr_byte = 0; curr_byte < size; curr_byte++) {
-
-		/* Wait for data */
-		while (timeout > 0 && NRF51_TWI_RXDRDY(port) == 0 &&
-				NRF51_TWI_ERROR(port) == 0)
-			timeout--;
-
-		if (timeout == 0)
-			return EC_ERROR_TIMEOUT;
-
-		if (NRF51_TWI_ERROR(port))
-			return EC_ERROR_UNKNOWN;
-
-		data[curr_byte] = NRF51_TWI_RXD(port);
-		NRF51_TWI_RXDRDY(port) = 0;
-
-		/* Second to the last byte: stop next time. */
-		if (curr_byte == size-2)
-			NRF51_PPI_TEP(i2c_ppi_chan[port]) =
-				(uint32_t)&NRF51_TWI_STOP(port);
-
-		/*
-		 * According to nRF51822-PAN v2.4 (Product Anomaly Notice),
-		 * the I2C locks up when RESUME is triggered too soon.
-		 * "the firmware should ensure that the time between receiving
-		 * the RXDRDY event and trigging the RESUME task is at least
-		 * two times the TWI clock period (i.e. 20 μs at 100 kbps).
-		 * Provided the TWI slave doesn’t do clock stretching during
-		 * the ACK bit, this will be enough to avoid the RESUME task
-		 * hit the end of the ACK bit. If this fails, a recovery of
-		 * the peripheral will be necessary, see i2c_recover.
-		 */
-		udelay(20);
-		NRF51_TWI_RESUME(port) = 1;
-	}
-
-	timeout = I2C_TIMEOUT;
-	while (NRF51_TWI_STOPPED(port) == 0 && timeout > 0)
-		timeout--;
-
-	NRF51_TWI_STOP(port) = 0;
-
-	NRF51_PPI_CHENCLR = 1 << i2c_ppi_chan[port];
-
-	return EC_SUCCESS;
-}
-
-int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags,
-		  const uint8_t *out, int out_bytes,
-		  uint8_t *in, int in_bytes, int flags)
-{
-	int rv = EC_SUCCESS;
-
-	ASSERT(out || !out_bytes);
-	ASSERT(in || !in_bytes);
-
-	if (out_bytes)
-		rv = i2c_master_write(port, slave_addr_flags,
-				      out, out_bytes,
-				      in_bytes ? 0 : 1);
-	if (rv == EC_SUCCESS && in_bytes)
-		rv = i2c_master_read(port, slave_addr_flags,
-				     in, in_bytes);
-
-	handle_i2c_error(port, rv);
-
-	return rv;
-}
-
-int i2c_raw_get_scl(int port)
-{
-	enum gpio_signal g;
-
-	if (get_scl_from_i2c_port(port, &g) == EC_SUCCESS)
-		return gpio_get_level(g);
-
-	/* If no SCL pin defined for this port, then return 1 to appear idle. */
-	return 1;
-}
-
-int i2c_raw_get_sda(int port)
-{
-	enum gpio_signal g;
-
-	if (get_sda_from_i2c_port(port, &g) == EC_SUCCESS)
-		return gpio_get_level(g);
-
-	/* If no SDA pin defined for this port, then return 1 to appear idle. */
-	return 1;
-}
-
-int i2c_get_line_levels(int port)
-{
-	return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) |
-		(i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
-}
-
diff --git a/chip/nrf51/keyboard_raw.c b/chip/nrf51/keyboard_raw.c
deleted file mode 100644
index 779c68454c..0000000000
--- a/chip/nrf51/keyboard_raw.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Raw keyboard I/O layer for nRF51
- *
- * To make this code portable, we rely heavily on looping over the keyboard
- * input and output entries in the board's gpio_list[]. Each set of inputs or
- * outputs must be listed in consecutive, increasing order so that scan loops
- * can iterate beginning at KB_IN00 or KB_OUT00 for however many GPIOs are
- * utilized (KEYBOARD_ROWS or KEYBOARD_COLS_MAX).
- */
-
-#include "gpio.h"
-#include "keyboard_config.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-/* Mask of output pins for driving. */
-static unsigned int col_mask;
-
-void keyboard_raw_init(void)
-{
-	int i;
-
-	/* Initialize col_mask */
-	col_mask = 0;
-	for (i = 0; i < keyboard_cols; i++)
-		col_mask |= gpio_list[GPIO_KB_OUT00 + i].mask;
-
-	/* Ensure interrupts are disabled */
-	keyboard_raw_enable_interrupt(0);
-}
-
-void keyboard_raw_task_start(void)
-{
-	/*
-	 * Enable the interrupt for keyboard matrix inputs.
-	 * One is enough, since they are shared.
-	 */
-	gpio_enable_interrupt(GPIO_KB_IN00);
-}
-
-test_mockable void keyboard_raw_drive_column(int out)
-{
-	/* tri-state all first */
-	NRF51_GPIO0_OUTSET = col_mask;
-
-	/* drive low for specified pin(s) */
-	if (out == KEYBOARD_COLUMN_ALL)
-		NRF51_GPIO0_OUTCLR = col_mask;
-	else if (out != KEYBOARD_COLUMN_NONE)
-		NRF51_GPIO0_OUTCLR = gpio_list[GPIO_KB_OUT00 + out].mask;
-}
-
-test_mockable int keyboard_raw_read_rows(void)
-{
-	int i;
-	int state = 0;
-
-	for (i = 0; i < KEYBOARD_ROWS; i++) {
-		if (NRF51_GPIO0_IN & gpio_list[GPIO_KB_IN00 + i].mask)
-			state |= 1 << i;
-	}
-
-	/* Invert it so 0=not pressed, 1=pressed */
-	return state ^ 0xff;
-}
-
-void keyboard_raw_enable_interrupt(int enable)
-{
-	if (enable) {
-		/*
-		 * Clear the PORT event before enabling the interrupt.
-		 */
-		NRF51_GPIOTE_PORT = 0;
-		NRF51_GPIOTE_INTENSET = 1 << NRF51_GPIOTE_PORT_BIT;
-	} else {
-		NRF51_GPIOTE_INTENCLR = 1 << NRF51_GPIOTE_PORT_BIT;
-	}
-}
-
-void keyboard_raw_gpio_interrupt(enum gpio_signal signal)
-{
-	task_wake(TASK_ID_KEYSCAN);
-}
diff --git a/chip/nrf51/ppi.c b/chip/nrf51/ppi.c
deleted file mode 100644
index 016cbf3008..0000000000
--- a/chip/nrf51/ppi.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "ppi.h"
-#include "registers.h"
-#include "util.h"
-
-#define NRF51_PPI_FIRST_PP_CH NRF51_PPI_CH_TIMER0_CC0__RADIO_TXEN
-#define NRF51_PPI_LAST_PP_CH  NRF51_PPI_CH_RTC0_COMPARE0__TIMER0_START
-
-static uint32_t channels_in_use;
-static uint32_t channel_groups_in_use;
-
-int ppi_request_pre_programmed_channel(int ppi_chan)
-{
-	ASSERT(ppi_chan >= NRF51_PPI_FIRST_PP_CH &&
-		ppi_chan <= NRF51_PPI_LAST_PP_CH);
-
-	if (channels_in_use & BIT(ppi_chan))
-		return EC_ERROR_BUSY;
-
-	channels_in_use |= BIT(ppi_chan);
-
-	return EC_SUCCESS;
-}
-
-int ppi_request_channel(int *ppi_chan)
-{
-	int chan;
-
-	for (chan = 0; chan < NRF51_PPI_NUM_PROGRAMMABLE_CHANNELS; chan++)
-		if ((channels_in_use & BIT(chan)) == 0)
-			break;
-
-	if (chan == NRF51_PPI_NUM_PROGRAMMABLE_CHANNELS)
-		return EC_ERROR_BUSY;
-
-	channels_in_use |= BIT(chan);
-	*ppi_chan = chan;
-	return EC_SUCCESS;
-}
-
-void ppi_release_channel(int ppi_chan)
-{
-	channels_in_use &= ~BIT(ppi_chan);
-}
-
-void ppi_release_group(int ppi_group)
-{
-	channel_groups_in_use &= ~BIT(ppi_group);
-}
-
-int ppi_request_group(int *ppi_group)
-{
-	int group;
-
-	for (group = 0; group < NRF51_PPI_NUM_GROUPS; group++)
-		if ((channel_groups_in_use & BIT(group)) == 0)
-			break;
-
-	if (group == NRF51_PPI_NUM_GROUPS)
-		return EC_ERROR_BUSY;
-
-	channel_groups_in_use |= BIT(group);
-	*ppi_group = group;
-	return EC_SUCCESS;
-}
diff --git a/chip/nrf51/ppi.h b/chip/nrf51/ppi.h
deleted file mode 100644
index bbb74a2cf0..0000000000
--- a/chip/nrf51/ppi.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * PPI channels are a way to connect NRF51 EVENTs to TASKs without software
- * involvement. They are like SHORTs, except between peripherals.
- *
- * PPI groups are user-defined sets of channels that can be enabled and disabled
- * together.
- */
-
-/*
- * Reserve a pre-programmed PPI channel.
- *
- * Return EC_SUCCESS if ppi_chan is a pre-programmed channel that was not in
- * use, otherwise returns EC_ERROR_BUSY.
- */
-int ppi_request_pre_programmed_channel(int ppi_chan);
-
-/*
- * Reserve an available PPI channel.
- *
- * Return EC_SUCCESS and set the value of ppi_chan to an available PPI
- * channel.  If no channel is available, return EC_ERROR_BUSY.
- */
-int ppi_request_channel(int *ppi_chan);
-
-/* Release a PPI channel which was reserved with ppi_request_*_channel.  */
-void ppi_release_channel(int ppi_chan);
-
-/*
- * Reserve a PPI group.
- *
- * Return EC_SUCCESS and set the value of ppi_group to an available PPI
- * group.  If no group is available, return EC_ERROR_BUSY.
- */
-int ppi_request_group(int *ppi_group);
-
-/* Release a PPI channel which was reserved with ppi_request_*_channel.  */
-void ppi_release_group(int ppi_group);
diff --git a/chip/nrf51/radio.c b/chip/nrf51/radio.c
deleted file mode 100644
index af9d029a0d..0000000000
--- a/chip/nrf51/radio.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "radio.h"
-
-int radio_disable(void)
-{
-	int timeout = 10000;
-
-	NRF51_RADIO_DISABLED = 0;
-	NRF51_RADIO_DISABLE = 1;
-
-	while (!NRF51_RADIO_DISABLED && timeout > 0)
-		timeout--;
-
-	if (timeout == 0)
-		return EC_ERROR_TIMEOUT;
-
-	return EC_SUCCESS;
-}
-
-int radio_init(enum nrf51_radio_mode_t mode)
-{
-	int err_code = radio_disable();
-
-	if (mode == BLE_1MBIT) {
-		NRF51_RADIO_MODE = NRF51_RADIO_MODE_BLE_1MBIT;
-
-		NRF51_RADIO_TIFS = 150;	/* Bluetooth 4.1 Vol 6 pg 58 4.1 */
-
-		/*
-		 * BLE never sends or receives two packets in a row.
-		 * Enabling the radio means we want to transmit or receive.
-		 * After transmission, disable as quickly as possible.
-		 */
-		NRF51_RADIO_SHORTS = NRF51_RADIO_SHORTS_READY_START |
-				NRF51_RADIO_SHORTS_END_DISABLE;
-
-		/* Use factory parameters if available */
-		if (!(NRF51_FICR_OVERRIDEEN & NRF51_FICR_OVERRIDEEN_BLE_BIT_N)
-		    ) {
-			int i;
-
-			for (i = 0; i < 4; i++) {
-				NRF51_RADIO_OVERRIDE(i) =
-					NRF51_FICR_BLE_1MBIT(i);
-			}
-			NRF51_RADIO_OVERRIDE(4) = NRF51_FICR_BLE_1MBIT(4) |
-				NRF51_RADIO_OVERRIDE_EN;
-		}
-	} else {
-		return EC_ERROR_UNIMPLEMENTED;
-	}
-
-	return err_code;
-}
-
diff --git a/chip/nrf51/radio.h b/chip/nrf51/radio.h
deleted file mode 100644
index 5b7e764fb9..0000000000
--- a/chip/nrf51/radio.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Radio interface for Chrome EC */
-
-#ifndef __NRF51_RADIO_H
-#define __NRF51_RADIO_H
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "registers.h"
-
-#ifndef NRF51_RADIO_MAX_PAYLOAD
-	#define NRF51_RADIO_MAX_PAYLOAD 253
-#endif
-
-#define RADIO_DONE (NRF51_RADIO_END == 1)
-
-enum nrf51_radio_mode_t {
-	BLE_1MBIT = NRF51_RADIO_MODE_BLE_1MBIT,
-};
-
-struct nrf51_radio_packet_t {
-	uint8_t s0; /* First byte */
-	uint8_t length; /* Length field */
-	uint8_t s1; /* Bits after length */
-	uint8_t payload[NRF51_RADIO_MAX_PAYLOAD];
-} __packed;
-
-int radio_init(enum nrf51_radio_mode_t mode);
-
-int radio_disable(void);
-
-#endif  /* __NRF51_RADIO_H */
diff --git a/chip/nrf51/radio_test.c b/chip/nrf51/radio_test.c
deleted file mode 100644
index 6c20874f4e..0000000000
--- a/chip/nrf51/radio_test.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "bluetooth_le.h" /* chan2freq */
-#include "btle_hci_int.h"
-#include "console.h"
-#include "radio.h"
-#include "radio_test.h"
-#include "registers.h"
-#include "timer.h"
-#include "util.h"
-
-#define BLE_TEST_TYPE_PRBS9   0
-#define BLE_TEST_TYPE_F0      1
-#define BLE_TEST_TYPE_AA      2
-#define BLE_TEST_TYPE_PRBS15  3
-#define BLE_TEST_TYPE_FF      4
-#define BLE_TEST_TYPE_00      5
-#define BLE_TEST_TYPE_0F      6
-#define BLE_TEST_TYPE_55      7
-
-#define BLE_TEST_TYPES_IMPLEMENTED 0xf6 /* No PRBS yet */
-
-static struct nrf51_ble_packet_t rx_packet;
-static struct nrf51_ble_packet_t tx_packet;
-static uint32_t rx_end;
-
-static int test_in_progress;
-
-void ble_test_stop(void)
-{
-	test_in_progress = 0;
-}
-
-static uint32_t prbs_lfsr;
-static uint32_t prbs_poly;
-
-/*
- * This is a Galois LFSR, the polynomial is the counterpart of the Fibonacci
- * LFSR in the doc.  It requires fewer XORs to implement in software.
- * This also means that the initial value is different.
- */
-static uint8_t prbs_next_byte(void)
-{
-	int i;
-	int lsb;
-	uint8_t rv = 0;
-
-	for (i = 0; i < 8; i++) {
-		lsb = prbs_lfsr & 1;
-		rv |= lsb << i;
-		prbs_lfsr = prbs_lfsr >> 1;
-		if (lsb)
-			prbs_lfsr ^= prbs_poly;
-	}
-	return rv;
-}
-
-void ble_test_fill_tx_packet(int type, int len)
-{
-	int i;
-
-	tx_packet.s0 = type & 0xf;
-	tx_packet.length = len;
-
-	switch (type) {
-	case BLE_TEST_TYPE_PRBS9:
-		prbs_lfsr = 0xf;
-		prbs_poly = 0x108;
-		for (i = 0; i < len; i++)
-			tx_packet.payload[i] = prbs_next_byte();
-		break;
-	case BLE_TEST_TYPE_PRBS15:
-		prbs_lfsr = 0xf;
-		prbs_poly = 0x6000;
-		for (i = 0; i < len; i++)
-			tx_packet.payload[i] = prbs_next_byte();
-		break;
-	case BLE_TEST_TYPE_F0:
-		memset(tx_packet.payload, 0xF0, len);
-		break;
-	case BLE_TEST_TYPE_AA:
-		memset(tx_packet.payload, 0xAA, len);
-		break;
-	case BLE_TEST_TYPE_FF:
-		memset(tx_packet.payload, 0xFF, len);
-		break;
-	case BLE_TEST_TYPE_00:
-		memset(tx_packet.payload, 0x00, len);
-		break;
-	case BLE_TEST_TYPE_0F:
-		memset(tx_packet.payload, 0x0F, len);
-		break;
-	case BLE_TEST_TYPE_55:
-		memset(tx_packet.payload, 0x55, len);
-		break;
-	default:
-		break;
-	}
-}
-
-static int ble_test_init(int chan)
-{
-	int rv = radio_init(BLE_1MBIT);
-
-	if (rv)
-		return HCI_ERR_Hardware_Failure;
-
-	if (chan > BLE_MAX_TEST_CHANNEL || chan < BLE_MIN_TEST_CHANNEL)
-		return HCI_ERR_Invalid_HCI_Command_Parameters;
-
-	NRF51_RADIO_CRCCNF = 3 | BIT(8); /* 3-byte, skip address */
-	/* x^24 + x^10 + x^9 + x^6 + x^4 + x^3 + x + 1 */
-	/* 0x1_0000_0000_0000_0110_0101_1011 */
-	NRF51_RADIO_CRCPOLY = 0x100065B;
-	NRF51_RADIO_CRCINIT = 0x555555;
-
-	NRF51_RADIO_TXPOWER = NRF51_RADIO_TXPOWER_0_DBM;
-
-	/* The testing address is the inverse of the advertising address. */
-	NRF51_RADIO_BASE0 = (~BLE_ADV_ACCESS_ADDRESS) << 8;
-
-	NRF51_RADIO_PREFIX0 = (~BLE_ADV_ACCESS_ADDRESS) >> 24;
-
-	NRF51_RADIO_TXADDRESS = 0;
-	NRF51_RADIO_RXADDRESSES = 1;
-
-	NRF51_RADIO_PCNF0 = NRF51_RADIO_PCNF0_TEST;
-
-	NRF51_RADIO_PCNF1 = NRF51_RADIO_PCNF1_TEST;
-
-	NRF51_RADIO_FREQUENCY = NRF51_RADIO_FREQUENCY_VAL(2*chan + 2402);
-
-	test_in_progress = 1;
-	return rv;
-}
-
-int ble_test_rx_init(int chan)
-{
-	NRF51_RADIO_PACKETPTR = (uint32_t)&rx_packet;
-	return ble_test_init(chan);
-}
-
-int ble_test_tx_init(int chan, int len, int type)
-{
-	if ((BIT(type) & BLE_TEST_TYPES_IMPLEMENTED) == 0 ||
-			(len < 0 || len > BLE_MAX_TEST_PAYLOAD_OCTETS))
-		return HCI_ERR_Invalid_HCI_Command_Parameters;
-
-	ble_test_fill_tx_packet(type, len);
-	NRF51_RADIO_PACKETPTR = (uint32_t)&tx_packet;
-
-	return ble_test_init(chan);
-}
-
-void ble_test_tx(void)
-{
-	NRF51_RADIO_END = 0;
-	NRF51_RADIO_TXEN = 1;
-}
-
-int ble_test_rx(void)
-{
-	int retries = 100;
-
-	NRF51_RADIO_END = 0;
-	NRF51_RADIO_RXEN = 1;
-
-	do {
-		retries--;
-		if (retries <= 0) {
-			radio_disable();
-			return EC_ERROR_TIMEOUT;
-		}
-		usleep(100);
-	} while (!NRF51_RADIO_END);
-
-	rx_end = get_time().le.lo;
-
-	return EC_SUCCESS;
-}
-
diff --git a/chip/nrf51/radio_test.h b/chip/nrf51/radio_test.h
deleted file mode 100644
index 591b78a78c..0000000000
--- a/chip/nrf51/radio_test.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Radio test interface for NRF51
- *
- * These functions implement parts of the Direct Test Mode functionality in
- * the Bluetooth Spec.
- */
-
-#ifndef __NRF51_RADIO_TEST_H
-#define __NRF51_RADIO_TEST_H
-
-#define BLE_MAX_TEST_PAYLOAD_OCTETS       37
-#define BLE_MAX_TEST_CHANNEL              39
-#define BLE_MIN_TEST_CHANNEL              0
-
-#define NRF51_RADIO_PCNF0_TEST NRF51_RADIO_PCNF0_ADV_DATA
-
-#define BLE_TEST_WHITEN           0
-
-#define NRF51_RADIO_PCNF1_TEST \
-	NRF51_RADIO_PCNF1_VAL(BLE_MAX_TEST_PAYLOAD_OCTETS, \
-			      EXTRA_RECEIVE_BYTES, \
-			      BLE_ACCESS_ADDRESS_BYTES - 1, \
-			      BLE_TEST_WHITEN)
-
-/*
- * Prepare the radio for transmitting packets.  The value of chan must be
- * between 0 and 39 inclusive.  The maximum length is 37.
- */
-
-int ble_test_tx_init(int chan, int type, int len);
-int ble_test_rx_init(int chan);
-void ble_test_tx(void);
-int ble_test_rx(void);
-void ble_test_stop(void);
-
-#endif /* __NRF51_RADIO_TEST_H */
diff --git a/chip/nrf51/registers.h b/chip/nrf51/registers.h
deleted file mode 100644
index daf014df72..0000000000
--- a/chip/nrf51/registers.h
+++ /dev/null
@@ -1,720 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Register map for STM32 processor
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#define __CROS_EC_REGISTERS_H
-
-#include "common.h"
-
-/*
- *  Peripheral IDs
- *
- *  nRF51 has very good design that the peripheral IDs is actually the IRQ#.
- *  Thus, the following numbers are used in DECLARE_IRQ(), task_enable_irq()
- *  and task_disable_irq().
- */
-#define NRF51_PERID_POWER   0
-#define NRF51_PERID_CLOCK   0
-#define NRF51_PERID_RADIO   1
-#define NRF51_PERID_USART   2
-#define NRF51_PERID_SPI0    3
-#define NRF51_PERID_TWI0    3
-#define NRF51_PERID_SPI1    4
-#define NRF51_PERID_TWI1    4
-#define NRF51_PERID_SPIS    4
-#define NRF51_PERID_GPIOTE  6
-#define NRF51_PERID_ADC     7
-#define NRF51_PERID_TIMER0  8
-#define NRF51_PERID_TIMER1  9
-#define NRF51_PERID_TIMER2  10
-#define NRF51_PERID_RTC     11
-#define NRF51_PERID_TEMP    12
-#define NRF51_PERID_RNG     13
-#define NRF51_PERID_ECB     14
-#define NRF51_PERID_CCM     15
-#define NRF51_PERID_AAR     16
-#define NRF51_PERID_WDT     17
-#define NRF51_PERID_QDEC    18
-#define NRF51_PERID_LPCOMP  19
-#define NRF51_PERID_NVMC    30
-#define NRF51_PERID_PPI     31
-
-/*
- * The nRF51 allows any pin to be mapped to any function.  This
- * doesn't fit well with the notion of the alternate function table.
- * Implement an alternate function table.  See ./gpio.c.
- */
-
-	/* UART */
-#define NRF51_UART_ALT_FUNC_RTS        0
-#define NRF51_UART_ALT_FUNC_TXD        1
-#define NRF51_UART_ALT_FUNC_CTS        2
-#define NRF51_UART_ALT_FUNC_RXD        3
-	/* SPI1 (SPI Master) */
-#define NRF51_SPI0_ALT_FUNC_SCK        4
-#define NRF51_SPI0_ALT_FUNC_MOSI       5
-#define NRF51_SPI0_ALT_FUNC_MISO       6
-	/* TWI0 (I2C) */
-#define NRF51_TWI0_ALT_FUNC_SCL        7
-#define NRF51_TWI0_ALT_FUNC_SDA        8
-	/* SPI1 (SPI Master) */
-#define NRF51_SPI1_ALT_FUNC_SCK        9
-#define NRF51_SPI1_ALT_FUNC_MOSI       10
-#define NRF51_SPI1_ALT_FUNC_MISO       11
-	/* TWI1 (I2C) */
-#define NRF51_TWI1_ALT_FUNC_SCL        12
-#define NRF51_TWI1_ALT_FUNC_SDA        13
-	/* SPIS1 (SPI SLAVE) */
-#define NRF51_SPIS1_ALT_FUNC_SCK       14
-#define NRF51_SPIS1_ALT_FUNC_MISO      15
-#define NRF51_SPIS1_ALT_FUNC_MOSI      16
-#define NRF51_SPIS1_ALT_FUNC_CSN       17
-	/* QDEC (ROTARY DECODER) */
-#define NRF51_QDEC_ALT_FUNC_LED        18
-#define NRF51_QDEC_ALT_FUNC_A          19
-#define NRF51_QDEC_ALT_FUNC_B          20
-	/* LPCOMP (Low Power Comparator) */
-#define NRF51_LPCOMP_ALT_FUNC          21
-#define NRF51_MAX_ALT_FUNCS            22
-
-/*
- * Configuration Registers
- */
-
-/*
- * FICR
- */
-#define NRF51_FICR_BASE                0x10000000
-#define NRF51_FICR_CODEPAGESIZE        REG32(NRF51_FICR_BASE + 0x010)
-#define NRF51_FICR_CLENR0              REG32(NRF51_FICR_BASE + 0x014)
-#define NRF51_FICR_PPFC                REG32(NRF51_FICR_BASE + 0x028)
-#define NRF51_FICR_NUMRAMBLOCK         REG32(NRF51_FICR_BASE + 0x02C)
-#define NRF51_FICR_SIZERAMBLOCK(n)     REG32(NRF51_FICR_BASE + 0x034 + ((n)*4))
-#define NRF51_FICR_CONFIGID            REG32(NRF51_FICR_BASE + 0x05C)
-#define NRF51_FICR_DEVICEID(n)         REG32(NRF51_FICR_BASE + 0x060 + ((n)*4))
-#define NRF51_FICR_ER(n)               REG32(NRF51_FICR_BASE + 0x080 + ((n)*4))
-#define NRF51_FICR_IR(n)               REG32(NRF51_FICR_BASE + 0x090 + ((n)*4))
-#define NRF51_FICR_DEVICEADDRTYPE      REG32(NRF51_FICR_BASE + 0x0A0)
-#define NRF51_FICR_DEVICEADDR(n)       REG32(NRF51_FICR_BASE + 0x0A4 + ((n)*4))
-#define NRF51_FICR_OVERRIDEEN          REG32(NRF51_FICR_BASE + 0x0AC)
-#define NRF51_FICR_BLE_1MBIT(n)        REG32(NRF51_FICR_BASE + 0x0EC + ((n)*4))
-
-/* DEVICEADDRTYPE */
-#define NRF51_FICR_DEVICEADDRTYPE_RANDOM      1
-
-/* OVERRIDEEN */
-#define NRF51_FICR_OVERRIDEEN_NRF_BIT_N       1
-#define NRF51_FICR_OVERRIDEEN_BLE_BIT_N       8
-
-/*
- * UICR
- */
-#define NRF51_UICR_BASE                0x10001000
-#define NRF51_UICR_CLENR0              REG32(NRF51_UICR_BASE + 0x000)
-#define NRF51_UICR_RBPCONF             REG32(NRF51_UICR_BASE + 0x004)
-#define NRF51_UICR_XTALFREQ            REG32(NRF51_UICR_BASE + 0x008)
-#define NRF51_UICR_FWID                REG32(NRF51_UICR_BASE + 0x010)
-#define NRF51_UICR_FWID_CUSTOMER(n)    REG32(NRF51_UICR_BASE + 0x080 + ((n)*4))
-
-#define NRF51_UICR_XTALFREQ_16MHZ      0xFF
-#define NRF51_UICR_XTALFREQ_32MHZ      0x00
-
-/*
- * Devices
- */
-
-/*
- *  Power
- */
-#define NRF51_POWER_BASE    0x40000000
-/* Tasks */
-#define NRF51_POWER_CONSTLAT  REG32(NRF51_POWER_BASE + 0x078)
-#define NRF51_POWER_LOWPWR    REG32(NRF51_POWER_BASE + 0x07C)
-/* Events */
-#define NRF51_POWER_POFWARN   REG32(NRF51_POWER_BASE + 0x108)
-/* Registers */
-#define NRF51_POWER_INTENSET  REG32(NRF51_POWER_BASE + 0x304)
-#define NRF51_POWER_INTENCLR  REG32(NRF51_POWER_BASE + 0x308)
-#define NRF51_POWER_RESETREAS REG32(NRF51_POWER_BASE + 0x400)
-#define NRF51_POWER_SYSTEMOFF REG32(NRF51_POWER_BASE + 0x500)
-#define NRF51_POWER_POFCON    REG32(NRF51_POWER_BASE + 0x510)
-#define NRF51_POWER_GPREGRET  REG32(NRF51_POWER_BASE + 0x51C)
-#define NRF51_POWER_RAMON     REG32(NRF51_POWER_BASE + 0x524)
-#define NRF51_POWER_RESET     REG32(NRF51_POWER_BASE + 0x544)
-#define NRF51_POWER_DCDCEN    REG32(NRF51_POWER_BASE + 0x578)
-
-#define NRF51_POWER_RESETREAS_RESETPIN          0x00001
-#define NRF51_POWER_RESETREAS_DOG               0x00002
-#define NRF51_POWER_RESETREAS_SREQ              0x00004
-#define NRF51_POWER_RESETREAS_LOCKUP            0x00008
-#define NRF51_POWER_RESETREAS_OFF               0x10000
-#define NRF51_POWER_RESETREAS_LPCOMP            0x20000
-#define NRF51_POWER_RESETREAS_DIF               0x40000
-
-
-/*
- *  Clock
- */
-#define NRF51_CLOCK_BASE    0x40000000
-/* Tasks */
-#define NRF51_CLOCK_HFCLKSTART REG32(NRF51_CLOCK_BASE + 0x000)
-#define NRF51_CLOCK_HFCLKSTOP  REG32(NRF51_CLOCK_BASE + 0x004)
-#define NRF51_CLOCK_LFCLKSTART REG32(NRF51_CLOCK_BASE + 0x008)
-#define NRF51_CLOCK_LFCLKSTOP  REG32(NRF51_CLOCK_BASE + 0x00C)
-#define NRF51_CLOCK_CAL     REG32(NRF51_CLOCK_BASE + 0x010)
-#define NRF51_CLOCK_CTSTART REG32(NRF51_CLOCK_BASE + 0x014)
-#define NRF51_CLOCK_CTSTOP  REG32(NRF51_CLOCK_BASE + 0x018)
-/* Events */
-#define NRF51_CLOCK_HFCLKSTARTED REG32(NRF51_CLOCK_BASE + 0x100)
-#define NRF51_CLOCK_LFCLKSTARTED REG32(NRF51_CLOCK_BASE + 0x104)
-#define NRF51_CLOCK_DONE    REG32(NRF51_CLOCK_BASE + 0x10C)
-#define NRF51_CLOCK_CCTO    REG32(NRF51_CLOCK_BASE + 0x110)
-/* Registers */
-#define NRF51_CLOCK_INTENSET  REG32(NRF51_CLOCK_BASE + 0x304)
-#define NRF51_CLOCK_INTENCLR  REG32(NRF51_CLOCK_BASE + 0x308)
-#define NRF51_CLOCK_HFCLKSTAT REG32(NRF51_CLOCK_BASE + 0x40C)
-#define NRF51_CLOCK_LFCLKSTAT REG32(NRF51_CLOCK_BASE + 0x418)
-#define NRF51_CLOCK_LFCLKSRC  REG32(NRF51_CLOCK_BASE + 0x518)
-#define NRF51_CLOCK_CTIV      REG32(NRF51_CLOCK_BASE + 0x538)
-#define NRF51_CLOCK_XTALFREQ  REG32(NRF51_CLOCK_BASE + 0x550)
-
-/*
- *  Radio
- */
-#define NRF51_RADIO_BASE    0x40001000
-/* Tasks */
-#define NRF51_RADIO_TXEN      REG32(NRF51_RADIO_BASE + 0x000)
-#define NRF51_RADIO_RXEN      REG32(NRF51_RADIO_BASE + 0x004)
-#define NRF51_RADIO_START     REG32(NRF51_RADIO_BASE + 0x008)
-#define NRF51_RADIO_STOP      REG32(NRF51_RADIO_BASE + 0x00C)
-#define NRF51_RADIO_DISABLE   REG32(NRF51_RADIO_BASE + 0x010)
-#define NRF51_RADIO_RSSISTART REG32(NRF51_RADIO_BASE + 0x014)
-#define NRF51_RADIO_RSSISTOP  REG32(NRF51_RADIO_BASE + 0x018)
-#define NRF51_RADIO_BCSTART   REG32(NRF51_RADIO_BASE + 0x01C)
-#define NRF51_RADIO_BCSTOP    REG32(NRF51_RADIO_BASE + 0x020)
-/* Events */
-#define NRF51_RADIO_READY     REG32(NRF51_RADIO_BASE + 0x100)
-#define NRF51_RADIO_ADDRESS   REG32(NRF51_RADIO_BASE + 0x104)
-#define NRF51_RADIO_PAYLOAD   REG32(NRF51_RADIO_BASE + 0x108)
-#define NRF51_RADIO_END       REG32(NRF51_RADIO_BASE + 0x10C)
-#define NRF51_RADIO_DISABLED  REG32(NRF51_RADIO_BASE + 0x110)
-#define NRF51_RADIO_DEVMATCH  REG32(NRF51_RADIO_BASE + 0x114)
-#define NRF51_RADIO_DEVMISS   REG32(NRF51_RADIO_BASE + 0x118)
-#define NRF51_RADIO_RSSIEND   REG32(NRF51_RADIO_BASE + 0x11C)
-#define NRF51_RADIO_BCMATCH   REG32(NRF51_RADIO_BASE + 0x128)
-/* Registers */
-#define NRF51_RADIO_SHORTS      REG32(NRF51_RADIO_BASE + 0x200)
-#define NRF51_RADIO_INTENSET    REG32(NRF51_RADIO_BASE + 0x304)
-#define NRF51_RADIO_INTENCLR    REG32(NRF51_RADIO_BASE + 0x308)
-#define NRF51_RADIO_CRCSTATUS   REG32(NRF51_RADIO_BASE + 0x400)
-#define NRF51_RADIO_RXMATCH     REG32(NRF51_RADIO_BASE + 0x408)
-#define NRF51_RADIO_RXCRC       REG32(NRF51_RADIO_BASE + 0x40C)
-#define NRF51_RADIO_DAI         REG32(NRF51_RADIO_BASE + 0x410)
-#define NRF51_RADIO_PACKETPTR   REG32(NRF51_RADIO_BASE + 0x504)
-#define NRF51_RADIO_FREQUENCY   REG32(NRF51_RADIO_BASE + 0x508)
-#define NRF51_RADIO_TXPOWER     REG32(NRF51_RADIO_BASE + 0x50C)
-#define NRF51_RADIO_MODE        REG32(NRF51_RADIO_BASE + 0x510)
-#define NRF51_RADIO_PCNF0       REG32(NRF51_RADIO_BASE + 0x514)
-#define NRF51_RADIO_PCNF1       REG32(NRF51_RADIO_BASE + 0x518)
-#define NRF51_RADIO_BASE0       REG32(NRF51_RADIO_BASE + 0x51C)
-#define NRF51_RADIO_BASE1       REG32(NRF51_RADIO_BASE + 0x520)
-#define NRF51_RADIO_PREFIX0     REG32(NRF51_RADIO_BASE + 0x524)
-#define NRF51_RADIO_PREFIX1     REG32(NRF51_RADIO_BASE + 0x528)
-#define NRF51_RADIO_TXADDRESS   REG32(NRF51_RADIO_BASE + 0x52C)
-#define NRF51_RADIO_RXADDRESSES REG32(NRF51_RADIO_BASE + 0x530)
-#define NRF51_RADIO_CRCCNF      REG32(NRF51_RADIO_BASE + 0x534)
-#define NRF51_RADIO_CRCPOLY     REG32(NRF51_RADIO_BASE + 0x538)
-#define NRF51_RADIO_CRCINIT     REG32(NRF51_RADIO_BASE + 0x53C)
-#define NRF51_RADIO_TEST        REG32(NRF51_RADIO_BASE + 0x540)
-#define NRF51_RADIO_TIFS        REG32(NRF51_RADIO_BASE + 0x544)
-#define NRF51_RADIO_RSSISAMPLE  REG32(NRF51_RADIO_BASE + 0x548)
-/* NRF51_RADIO_STATE (0x550) is Broken (PAN 2.4) */
-#define NRF51_RADIO_DATAWHITEIV REG32(NRF51_RADIO_BASE + 0x554)
-#define NRF51_RADIO_BCC         REG32(NRF51_RADIO_BASE + 0x560)
-#define NRF51_RADIO_DAB(n)      REG32(NRF51_RADIO_BASE + 0x600 + ((n) * 4))
-#define NRF51_RADIO_DAP(n)      REG32(NRF51_RADIO_BASE + 0x620 + ((n) * 4))
-#define NRF51_RADIO_DACNF       REG32(NRF51_RADIO_BASE + 0x640)
-#define NRF51_RADIO_OVERRIDE(n) REG32(NRF51_RADIO_BASE + 0x724 + ((n) * 4))
-#define NRF51_RADIO_POWER       REG32(NRF51_RADIO_BASE + 0xFFC)
-
-/* Shorts */
-#define NRF51_RADIO_SHORTS_READY_START                0x001
-#define NRF51_RADIO_SHORTS_END_DISABLE                0x002
-#define NRF51_RADIO_SHORTS_DISABLED_TXEN              0x004
-#define NRF51_RADIO_SHORTS_DISABLED_RXEN              0x008
-#define NRF51_RADIO_SHORTS_ADDRESS_RSSISTART          0x010
-/* NRF51_RADIO_SHORTS_END_START (0x20) is Broken (PAN 2.4) */
-#define NRF51_RADIO_SHORTS_ADDRESS_BCSTART            0x040
-#define NRF51_RADIO_SHORTS_DISABLED_RSSISTOP          0x100
-
-/* For RADIO.INTEN bits */
-#define NRF51_RADIO_READY_BIT                         0
-#define NRF51_RADIO_ADDRESS_BIT                       1
-#define NRF51_RADIO_PAYLOAD_BIT                       2
-#define NRF51_RADIO_END_BIT                           3
-#define NRF51_RADIO_DISABLED_BIT                      4
-#define NRF51_RADIO_DEVMATCH_BIT                      5
-#define NRF51_RADIO_DEVMISS_BIT                       6
-#define NRF51_RADIO_RSSIEND_BIT                       7
-#define NRF51_RADIO_BCMATCH_BIT                       10
-
-/* CRC Status */
-#define NRF51_RADIO_CRCSTATUS_OK                      0x1
-
-/* Frequency (in MHz) */
-#define NRF51_RADIO_FREQUENCY_VAL(x)                  ((x) - 2400)
-
-/* TX Power */
-#define NRF51_RADIO_TXPOWER_POS_4_DBM                 0x04
-#define NRF51_RADIO_TXPOWER_0_DBM                     0x00
-#define NRF51_RADIO_TXPOWER_NEG_8_DBM                 0xFC
-#define NRF51_RADIO_TXPOWER_NEG_12_DBM                0xF8
-#define NRF51_RADIO_TXPOWER_NEG_16_DBM                0xF4
-#define NRF51_RADIO_TXPOWER_NEG_20_DBM                0xEC
-#define NRF51_RADIO_TXPOWER_NEG_30_DBM                0xD8
-
-/* TX Mode */
-#define NRF51_RADIO_MODE_BLE_1MBIT                    0x03
-
-/*
- * PCNF0 and PCNF1 Packet Configuration
- *
- * The radio unpacks the packet for you according to these settings.
- *
- * The on-air format is:
- *
- * |_Preamble_|___Base___|_Prefix_|___S0____|_Length_,_S1_|__Payload__|___|
- * 0           <ba_bytes> <1 byte><s0_bytes>   <1 byte>    <max_bytes> <extra>
- *
- * The in-memory format is
- *
- * uint8_t s0[s0_bytes];
- * uint8_t length;
- * uint8_t s1;
- * uint8_t payload[max_bytes];
- *
- * lf_bits is how many bits to store in length
- * s1_bits is how many bits to store in s1
- *
- * If any one of these lengths are set to zero, the field is omitted in memory.
- */
-
-#define NRF51_RADIO_PCNF0_LFLEN_SHIFT                 0
-#define NRF51_RADIO_PCNF0_S0LEN_SHIFT                 8
-#define NRF51_RADIO_PCNF0_S1LEN_SHIFT                 16
-
-#define NRF51_RADIO_PCNF0_VAL(lf_bits, s0_bytes, s1_bits) \
-	((lf_bits) << NRF51_RADIO_PCNF0_LFLEN_SHIFT | \
-	 (s0_bytes) << NRF51_RADIO_PCNF0_S0LEN_SHIFT | \
-	 (s1_bits) << NRF51_RADIO_PCNF0_S1LEN_SHIFT)
-
-#define NRF51_RADIO_PCNF1_MAXLEN_SHIFT                0
-#define NRF51_RADIO_PCNF1_STATLEN_SHIFT               8
-#define NRF51_RADIO_PCNF1_BALEN_SHIFT                 16
-#define NRF51_RADIO_PCNF1_ENDIAN_BIG                  0x1000000
-#define NRF51_RADIO_PCNF1_WHITEEN                     0x2000000
-
-#define NRF51_RADIO_PCNF1_VAL(max_bytes, extra_bytes, ba_bytes, whiten) \
-	((max_bytes) << NRF51_RADIO_PCNF1_MAXLEN_SHIFT | \
-	 (extra_bytes) << NRF51_RADIO_PCNF1_STATLEN_SHIFT | \
-	 (ba_bytes) << NRF51_RADIO_PCNF1_BALEN_SHIFT | \
-	 ((whiten) ? NRF51_RADIO_PCNF1_WHITEEN : 0))
-
-/* PREFIX0 */
-#define NRF51_RADIO_PREFIX0_AP0_SHIFT                 0
-#define NRF51_RADIO_PREFIX0_AP1_SHIFT                 8
-#define NRF51_RADIO_PREFIX0_AP2_SHIFT                 16
-#define NRF51_RADIO_PREFIX0_AP3_SHIFT                 24
-
-/* PREFIX1 */
-#define NRF51_RADIO_PREFIX1_AP4_SHIFT                 0
-#define NRF51_RADIO_PREFIX1_AP5_SHIFT                 8
-#define NRF51_RADIO_PREFIX1_AP6_SHIFT                 16
-#define NRF51_RADIO_PREFIX1_AP7_SHIFT                 24
-
-/* CRCCNF */
-#define NRF51_RADIO_CRCCNF_SKIP_ADDR                  0x100
-
-/* TEST */
-#define NRF51_RADIO_TEST_CONST_CARRIER_EN             0x01
-#define NRF51_RADIO_TEST_PLL_LOCK_EN                  0x02
-
-/* STATE */
-#define NRF51_RADIO_STATE_DISABLED                    0
-#define NRF51_RADIO_STATE_RXRU                        1
-#define NRF51_RADIO_STATE_RXIDLE                      2
-#define NRF51_RADIO_STATE_RX                          3
-#define NRF51_RADIO_STATE_RXDISABLE                   4
-#define NRF51_RADIO_STATE_TXRU                        9
-#define NRF51_RADIO_STATE_TXIDLE                      10
-#define NRF51_RADIO_STATE_TX                          11
-#define NRF51_RADIO_STATE_TXDISABLE                   12
-
-/* DACNF */
-#define NRF51_RADIO_DACNF_ENA(n)                      (1 << (n))
-#define NRF51_RADIO_DACNF_MAX                         8
-#define NRF51_RADIO_DACNF_TXADD(n)                    (1 << ((n)+8))
-#define NRF51_RADIO_TXADD_MAX                         8
-
-/* OVERRIDE4 */
-#define NRF51_RADIO_OVERRIDE_EN                       BIT(31)
-
-
-/*
- *  UART
- */
-#define NRF51_UART_BASE     0x40002000
-/* Tasks */
-#define NRF51_UART_STARTRX  REG32(NRF51_UART_BASE + 0x000)
-#define NRF51_UART_STOPRX   REG32(NRF51_UART_BASE + 0x004)
-#define NRF51_UART_STARTTX  REG32(NRF51_UART_BASE + 0x008)
-#define NRF51_UART_STOPTX   REG32(NRF51_UART_BASE + 0x00C)
-/* Events */
-#define NRF51_UART_RXDRDY   REG32(NRF51_UART_BASE + 0x108)
-#define NRF51_UART_TXDRDY   REG32(NRF51_UART_BASE + 0x11C)
-#define NRF51_UART_ERROR    REG32(NRF51_UART_BASE + 0x124)
-#define NRF51_UART_RXTO     REG32(NRF51_UART_BASE + 0x144)
-/* Registers */
-#define NRF51_UART_INTENSET REG32(NRF51_UART_BASE + 0x304)
-#define NRF51_UART_INTENCLR REG32(NRF51_UART_BASE + 0x308)
-#define NRF51_UART_ERRORSRC REG32(NRF51_UART_BASE + 0x480)
-#define NRF51_UART_ENABLE   REG32(NRF51_UART_BASE + 0x500)
-#define NRF51_UART_PSELRTS  REG32(NRF51_UART_BASE + 0x508)
-#define NRF51_UART_PSELTXD  REG32(NRF51_UART_BASE + 0x50C)
-#define NRF51_UART_PSELCTS  REG32(NRF51_UART_BASE + 0x510)
-#define NRF51_UART_PSELRXD  REG32(NRF51_UART_BASE + 0x514)
-#define NRF51_UART_RXD      REG32(NRF51_UART_BASE + 0x518)
-#define NRF51_UART_TXD      REG32(NRF51_UART_BASE + 0x51C)
-#define NRF51_UART_BAUDRATE REG32(NRF51_UART_BASE + 0x524)
-#define NRF51_UART_CONFIG   REG32(NRF51_UART_BASE + 0x56C)
-/* For UART.INTEN bits */
-#define NRF55_UART_RXDRDY_BIT  ((0x108 - 0x100) / 4)
-#define NRF55_UART_TXDRDY_BIT  ((0x11C - 0x100) / 4)
-
-/*
- *  TWI (I2C) Instances
- */
-#define NRF51_TWI_BASE(port)     (0x40003000 + ((port == 0) ? 0 : 0x1000))
-/* Tasks */
-#define NRF51_TWI_STARTRX(port)   REG32(NRF51_TWI_BASE(port) + 0x000)
-#define NRF51_TWI_STARTTX(port)   REG32(NRF51_TWI_BASE(port) + 0x008)
-#define NRF51_TWI_STOP(port)      REG32(NRF51_TWI_BASE(port) + 0x014)
-#define NRF51_TWI_SUSPEND(port)   REG32(NRF51_TWI_BASE(port) + 0x01C)
-#define NRF51_TWI_RESUME(port)    REG32(NRF51_TWI_BASE(port) + 0x020)
-/* Events */
-#define NRF51_TWI_STOPPED(port)   REG32(NRF51_TWI_BASE(port) + 0x104)
-#define NRF51_TWI_RXDRDY(port)    REG32(NRF51_TWI_BASE(port) + 0x108)
-#define NRF51_TWI_TXDSENT(port)   REG32(NRF51_TWI_BASE(port) + 0x11C)
-#define NRF51_TWI_ERROR(port)     REG32(NRF51_TWI_BASE(port) + 0x124)
-#define NRF51_TWI_BB(port)        REG32(NRF51_TWI_BASE(port) + 0x138)
-/* Registers */
-/* SHORTS not implemented for TWI (See nRF51822-PAN v2.4)  */
-#define NRF51_TWI_INTEN(port)     REG32(NRF51_TWI_BASE(port) + 0x300)
-#define NRF51_TWI_INTENSET(port)  REG32(NRF51_TWI_BASE(port) + 0x304)
-#define NRF51_TWI_INTENCLR(port)  REG32(NRF51_TWI_BASE(port) + 0x308)
-#define NRF51_TWI_ERRORSRC(port)  REG32(NRF51_TWI_BASE(port) + 0x4C4)
-#define NRF51_TWI_ENABLE(port)    REG32(NRF51_TWI_BASE(port) + 0x500)
-#define NRF51_TWI_PSELSCL(port)   REG32(NRF51_TWI_BASE(port) + 0x508)
-#define NRF51_TWI_PSELSDA(port)   REG32(NRF51_TWI_BASE(port) + 0x50C)
-#define NRF51_TWI_RXD(port)       REG32(NRF51_TWI_BASE(port) + 0x518)
-#define NRF51_TWI_TXD(port)       REG32(NRF51_TWI_BASE(port) + 0x51C)
-#define NRF51_TWI_FREQUENCY(port) REG32(NRF51_TWI_BASE(port) + 0x524)
-#define NRF51_TWI_ADDRESS(port)   REG32(NRF51_TWI_BASE(port) + 0x588)
-#define NRF51_TWI_POWER(port)     REG32(NRF51_TWI_BASE(port) + 0xFFC)
-
-#define NRF51_TWI_100KBPS         0x01980000
-#define NRF51_TWI_250KBPS         0x40000000
-#define NRF51_TWI_400KBPS         0x06680000
-
-#define NRF51_TWI_ENABLE_VAL      0x5
-#define NRF51_TWI_DISABLE_VAL     0x0
-
-#define NRF51_TWI_ERRORSRC_ANACK  BIT(1) /* Address NACK */
-#define NRF51_TWI_ERRORSRC_DNACK  BIT(2) /* Data NACK */
-
-/*
- *  TWI (I2C) Instance 0
- */
-#define NRF51_TWI0_BASE     0x40003000
-/* Tasks */
-#define NRF51_TWI0_STARTRX   REG32(NRF51_TWI0_BASE + 0x000)
-#define NRF51_TWI0_STARTTX   REG32(NRF51_TWI0_BASE + 0x008)
-#define NRF51_TWI0_STOP      REG32(NRF51_TWI0_BASE + 0x014)
-#define NRF51_TWI0_SUSPEND   REG32(NRF51_TWI0_BASE + 0x01C)
-#define NRF51_TWI0_RESUME    REG32(NRF51_TWI0_BASE + 0x020)
-/* Events */
-#define NRF51_TWI0_STOPPED   REG32(NRF51_TWI0_BASE + 0x104)
-#define NRF51_TWI0_RXDRDY    REG32(NRF51_TWI0_BASE + 0x108)
-#define NRF51_TWI0_TXDSENT   REG32(NRF51_TWI0_BASE + 0x11C)
-#define NRF51_TWI0_ERROR     REG32(NRF51_TWI0_BASE + 0x124)
-#define NRF51_TWI0_BB        REG32(NRF51_TWI0_BASE + 0x138)
-/* Registers */
-/* SHORTS not implemented for TWI (See nRF51822-PAN v2.4)  */
-#define NRF51_TWI0_INTENSET  REG32(NRF51_TWI0_BASE + 0x304)
-#define NRF51_TWI0_INTENCLR  REG32(NRF51_TWI0_BASE + 0x308)
-#define NRF51_TWI0_ERRORSRC  REG32(NRF51_TWI0_BASE + 0x4C4)
-#define NRF51_TWI0_ENABLE    REG32(NRF51_TWI0_BASE + 0x500)
-#define NRF51_TWI0_PSELSCL   REG32(NRF51_TWI0_BASE + 0x508)
-#define NRF51_TWI0_PSELSDA   REG32(NRF51_TWI0_BASE + 0x50C)
-#define NRF51_TWI0_RXD       REG32(NRF51_TWI0_BASE + 0x518)
-#define NRF51_TWI0_TXD       REG32(NRF51_TWI0_BASE + 0x51C)
-#define NRF51_TWI0_FREQUENCY REG32(NRF51_TWI0_BASE + 0x524)
-#define NRF51_TWI0_ADDRESS   REG32(NRF51_TWI0_BASE + 0x588)
-
-/* For TWI0.INTEN bits */
-#define NRF55_TWI0_RXDRDY_BIT  ((0x108 - 0x100) / 4)
-#define NRF55_TWI0_TXDRDY_BIT  ((0x11C - 0x100) / 4)
-
-/*
- *  TWI (I2C) Instance 1
- */
-#define NRF51_TWI1_BASE     0x40004000
-/* Tasks */
-#define NRF51_TWI1_STARTRX   REG32(NRF51_TWI1_BASE + 0x000)
-#define NRF51_TWI1_STARTTX   REG32(NRF51_TWI1_BASE + 0x008)
-#define NRF51_TWI1_STOP      REG32(NRF51_TWI1_BASE + 0x014)
-#define NRF51_TWI1_SUSPEND   REG32(NRF51_TWI1_BASE + 0x01C)
-#define NRF51_TWI1_RESUME    REG32(NRF51_TWI1_BASE + 0x020)
-/* Events */
-#define NRF51_TWI1_STOPPED   REG32(NRF51_TWI1_BASE + 0x104)
-#define NRF51_TWI1_RXDRDY    REG32(NRF51_TWI1_BASE + 0x108)
-#define NRF51_TWI1_TXDSENT   REG32(NRF51_TWI1_BASE + 0x11C)
-#define NRF51_TWI1_ERROR     REG32(NRF51_TWI1_BASE + 0x124)
-#define NRF51_TWI1_BB        REG32(NRF51_TWI1_BASE + 0x138)
-/* Registers */
-/* SHORTS not implemented for TWI (See nRF51822-PAN v2.4)  */
-#define NRF51_TWI1_INTENSET  REG32(NRF51_TWI1_BASE + 0x304)
-#define NRF51_TWI1_INTENCLR  REG32(NRF51_TWI1_BASE + 0x308)
-#define NRF51_TWI1_ERRORSRC  REG32(NRF51_TWI1_BASE + 0x4C4)
-#define NRF51_TWI1_ENABLE    REG32(NRF51_TWI1_BASE + 0x500)
-#define NRF51_TWI1_PSELSCL   REG32(NRF51_TWI1_BASE + 0x508)
-#define NRF51_TWI1_PSELSDA   REG32(NRF51_TWI1_BASE + 0x50C)
-#define NRF51_TWI1_RXD       REG32(NRF51_TWI1_BASE + 0x518)
-#define NRF51_TWI1_TXD       REG32(NRF51_TWI1_BASE + 0x51C)
-#define NRF51_TWI1_FREQUENCY REG32(NRF51_TWI1_BASE + 0x524)
-#define NRF51_TWI1_ADDRESS   REG32(NRF51_TWI1_BASE + 0x588)
-
-/* For TWI1.INTEN bits */
-#define NRF55_TWI1_RXDRDY_BIT  ((0x108 - 0x100) / 4)
-#define NRF55_TWI1_TXDRDY_BIT  ((0x11C - 0x100) / 4)
-
-/*
- *  GPIOTE - GPIO Tasks and Events
- */
-#define NRF51_GPIOTE_BASE   0x40006000
-/* Tasks */
-#define NRF51_GPIOTE_OUT(n)    REG32(NRF51_GPIOTE_BASE + ((n) * 4))
-/* Events */
-#define NRF51_GPIOTE_IN(n)     REG32(NRF51_GPIOTE_BASE + 0x100 + ((n) * 4))
-#define NRF51_GPIOTE_PORT      REG32(NRF51_GPIOTE_BASE + 0x17C)
-/* Registers */
-#define NRF51_GPIOTE_INTENSET  REG32(NRF51_GPIOTE_BASE + 0x304)
-#define NRF51_GPIOTE_INTENCLR  REG32(NRF51_GPIOTE_BASE + 0x308)
-#define NRF51_GPIOTE_CONFIG(n) REG32(NRF51_GPIOTE_BASE + 0x510 + ((n) * 4))
-#define NRF51_GPIOTE_POWER     REG32(NRF51_GPIOTE_BASE + 0xFFC)
-
-/* Number of IN events */
-#define NRF51_GPIOTE_IN_COUNT  4
-
-/* Bits */
-/* For GPIOTE.INTEN */
-#define NRF51_GPIOTE_IN_BIT(n) (n)
-#define NRF51_GPIOTE_PORT_BIT  31
-/* For GPIOTE.CONFIG */
-#define NRF51_GPIOTE_MODE_DISABLED     (0<<0)
-#define NRF51_GPIOTE_MODE_EVENT        BIT(0)
-#define NRF51_GPIOTE_MODE_TASK         (3<<0)
-#define NRF51_GPIOTE_PSEL_POS          (8)
-#define NRF51_GPIOTE_POLARITY_LOTOHI   BIT(16)
-#define NRF51_GPIOTE_POLARITY_HITOLO   (2<<16)
-#define NRF51_GPIOTE_POLARITY_TOGGLE   (3<<16)
-#define NRF51_GPIOTE_OUTINIT_LOW       (0<<20)
-#define NRF51_GPIOTE_OUTINIT_HIGH      BIT(20)
-
-/*
- *  Timer / Counter
- */
-#define NRF51_TIMER0_BASE   0x40008000
-#define NRF51_TIMER_BASE(n)   (NRF51_TIMER0_BASE + (n) * 0x1000)
-#define NRF51_PERID_TIMER(n)  (NRF51_PERID_TIMER0 + (n))
-/* Tasks */
-#define NRF51_TIMER_START(n)  REG32(NRF51_TIMER_BASE(n) + 0x000)
-#define NRF51_TIMER_STOP(n)   REG32(NRF51_TIMER_BASE(n) + 0x004)
-#define NRF51_TIMER_COUNT(n)  REG32(NRF51_TIMER_BASE(n) + 0x008)
-#define NRF51_TIMER_CLEAR(n)  REG32(NRF51_TIMER_BASE(n) + 0x00C)
-#define NRF51_TIMER_CAPTURE(n, c)  REG32(NRF51_TIMER_BASE(n) + 0x040 + 4 * (c))
-/* Events */
-#define NRF51_TIMER_COMPARE(n, c)  REG32(NRF51_TIMER_BASE(n) + 0x140 + 4 * (c))
-/* Registers */
-#define NRF51_TIMER_SHORTCUT(n)  REG32(NRF51_TIMER_BASE(n) + 0x200)
-#define NRF51_TIMER_INTENSET(n)  REG32(NRF51_TIMER_BASE(n) + 0x304)
-#define NRF51_TIMER_INTENCLR(n)  REG32(NRF51_TIMER_BASE(n) + 0x308)
-#define NRF51_TIMER_MODE(n)      REG32(NRF51_TIMER_BASE(n) + 0x504)
-#define NRF51_TIMER_BITMODE(n)   REG32(NRF51_TIMER_BASE(n) + 0x508)
-#define NRF51_TIMER_PRESCALER(n) REG32(NRF51_TIMER_BASE(n) + 0x510)
-#define NRF51_TIMER_CC(n, c)     REG32(NRF51_TIMER_BASE(n) + 0x540 + 4 * (c))
-/* For Timer.INTEN bits */
-#define NRF51_TIMER_COMPARE_BIT(n)  (((0x140 - 0x100) / 4) + (n))
-/* For Timer Shortcuts */
-#define NRF51_TIMER_COMPARE_CLEAR(n)  (1 << (n))
-#define NRF51_TIMER_COMPARE_STOP(n)   (1 << (8 + (n)))
-/* Timer Mode (NRF51_TIMER_MODE) */
-#define NRF51_TIMER_MODE_TIMER   0  /* reset default */
-#define NRF51_TIMER_MODE_COUNTER 1
-/* Prescaler */
-#define NRF51_TIMER_PRESCALER_MASK (0xf)  /* range: 0-9, reset default: 4 */
-/* Bit length (NRF51_TIMER_BITMODE) */
-#define NRF51_TIMER_BITMODE_16  0  /* reset default */
-#define NRF51_TIMER_BITMODE_8   1
-#define NRF51_TIMER_BITMODE_24  2
-#define NRF51_TIMER_BITMODE_32  3
-
-
-/*
- *  Random Number Generator (RNG)
- */
-#define NRF51_RNG_BASE               0x4000D000
-/* Tasks */
-#define NRF51_RNG_START              REG32(NRF51_RNG_BASE + 0x000)
-#define NRF51_RNG_STOP               REG32(NRF51_RNG_BASE + 0x004)
-/* Events */
-#define NRF51_RNG_VALRDY             REG32(NRF51_RNG_BASE + 0x100)
-/* Registers */
-#define NRF51_RNG_SHORTS             REG32(NRF51_RNG_BASE + 0x200)
-#define NRF51_RNG_INTENSET           REG32(NRF51_RNG_BASE + 0x304)
-#define NRF51_RNG_INTENCLR           REG32(NRF51_RNG_BASE + 0x308)
-#define NRF51_RNG_CONFIG             REG32(NRF51_RNG_BASE + 0x504)
-#define NRF51_RNG_VALUE              REG32(NRF51_RNG_BASE + 0x508)
-/* For RNG Shortcuts */
-#define NRF51_RNG_SHORTS_VALRDY_STOP BIT(0)
-/* For RNG Config */
-#define NRF51_RNG_DERCEN             BIT(0)
-
-
-/*
- *  Watchdog Timer (WDT)
- */
-#define NRF51_WDT_BASE        0x40010000
-/* Tasks */
-#define NRF51_WDT_START       REG32(NRF51_WDT_BASE + 0x000)
-/* Events */
-#define NRF51_WDT_TIMEOUT     REG32(NRF51_WDT_BASE + 0x100)
-/* Registers */
-#define NRF51_WDT_INTENSET    REG32(NRF51_WDT_BASE + 0x304)
-#define NRF51_WDT_INTENCLR    REG32(NRF51_WDT_BASE + 0x308)
-#define NRF51_WDT_RUNSTATUS   REG32(NRF51_WDT_BASE + 0x400)
-#define NRF51_WDT_REQSTATUS   REG32(NRF51_WDT_BASE + 0x404)
-#define NRF51_WDT_CRV         REG32(NRF51_WDT_BASE + 0x504)
-#define NRF51_WDT_RREN        REG32(NRF51_WDT_BASE + 0x508)
-#define NRF51_WDT_CONFIG      REG32(NRF51_WDT_BASE + 0x50C)
-#define NRF51_WDT_RR(n)       REG32(NRF51_WDT_BASE + 0x600 + ((n) * 4))
-#define NRF51_WDT_POWER       REG32(NRF51_WDT_BASE + 0xFFC)
-/* Bitfields */
-#define NRF51_WDT_RUNSTATUS_RUNNING        1
-#define NRF51_WDT_REQSTATUS_BIT(n)        (1<<(n))
-#define NRF51_WDT_RREN_BIT(n)             (1<<(n))
-#define NRF51_WDT_CONFIG_SLEEP_PAUSE       0
-#define NRF51_WDT_CONFIG_SLEEP_RUN         1
-#define NRF51_WDT_CONFIG_HALT_PAUSE       (0<<4)
-#define NRF51_WDT_CONFIG_HALT_RUN         BIT(4)
-
-#define NRF51_WDT_RELOAD_VAL             0x6E524635
-
-
-/*
- *  GPIO
- */
-#define NRF51_GPIO_BASE     0x50000000
-#define NRF51_GPIO0_BASE    (NRF51_GPIO_BASE + 0x500)
-#define NRF51_GPIO0_OUT     REG32(NRF51_GPIO0_BASE + 0x004)
-#define NRF51_GPIO0_OUTSET  REG32(NRF51_GPIO0_BASE + 0x008)
-#define NRF51_GPIO0_OUTCLR  REG32(NRF51_GPIO0_BASE + 0x00C)
-#define NRF51_GPIO0_IN      REG32(NRF51_GPIO0_BASE + 0x010)
-#define NRF51_GPIO0_DIR     REG32(NRF51_GPIO0_BASE + 0x014)  /* 1 for output */
-#define NRF51_GPIO0_DIRSET  REG32(NRF51_GPIO0_BASE + 0x018)
-#define NRF51_GPIO0_DIRCLR  REG32(NRF51_GPIO0_BASE + 0x01C)
-#define NRF51_PIN_BASE      (NRF51_GPIO_BASE + 0x700)
-#define NRF51_PIN_CNF(n)    REG32(NRF51_PIN_BASE + ((n) * 4))
-#define GPIO_0              NRF51_GPIO0_BASE
-
-#define NRF51_PIN_CNF_DIR_INPUT        (0)
-#define NRF51_PIN_CNF_DIR_OUTPUT       (1)
-#define NRF51_PIN_CNF_INPUT_CONNECT    (0<<1)
-#define NRF51_PIN_CNF_INPUT_DISCONNECT BIT(1)
-#define NRF51_PIN_CNF_PULL_DISABLED    (0<<2)
-#define NRF51_PIN_CNF_PULLDOWN         BIT(2)
-#define NRF51_PIN_CNF_PULLUP           (3<<2)
-/*
- * Logic levels 0 and 1, strengths S=Standard, H=High D=Disconnect
- * for example, S0D1 = Standard drive 0, disconnect on 1
- */
-#define NRF51_PIN_CNF_DRIVE_S0S1       (0<<8)
-#define NRF51_PIN_CNF_DRIVE_H0S1       BIT(8)
-#define NRF51_PIN_CNF_DRIVE_S0H1       (2<<8)
-#define NRF51_PIN_CNF_DRIVE_H0H1       (3<<8)
-#define NRF51_PIN_CNF_DRIVE_D0S1       (4<<8)
-#define NRF51_PIN_CNF_DRIVE_D0H1       (5<<8)
-#define NRF51_PIN_CNF_DRIVE_S0D1       (6<<8)
-#define NRF51_PIN_CNF_DRIVE_H0D1       (7<<8)
-
-#define NRF51_PIN_CNF_SENSE_DISABLED   (0<<16)
-#define NRF51_PIN_CNF_SENSE_HIGH       (2<<16)
-#define NRF51_PIN_CNF_SENSE_LOW        (3<<16)
-
-#define UNIMPLEMENTED_GPIO_BANK     GPIO_0  /* for UNIMPLEMENTED() macro */
-
-#define NRF51_PPI_BASE                 0x4001F000
-#define NRF51_PPI_CHEN                 REG32(NRF51_PPI_BASE + 0x500)
-#define NRF51_PPI_CHENSET              REG32(NRF51_PPI_BASE + 0x504)
-#define NRF51_PPI_CHENCLR              REG32(NRF51_PPI_BASE + 0x508)
-#define NRF51_PPI_EEP(channel)         REG32(NRF51_PPI_BASE + 0x510 + channel*8)
-#define NRF51_PPI_TEP(channel)         REG32(NRF51_PPI_BASE + 0x514 + channel*8)
-#define NRF51_PPI_CHG(group)           REG32(NRF51_PPI_BASE + 0x800 + group*4)
-
-#define NRF51_PPI_NUM_PROGRAMMABLE_CHANNELS        16
-#define NRF51_PPI_NUM_GROUPS                       4
-
-#define NRF51_PPI_CH_TIMER0_CC0__RADIO_TXEN        20
-#define NRF51_PPI_CH_TIMER0_CC0__RADIO_RXEN        21
-#define NRF51_PPI_CH_TIMER0_CC1__RADIO_DISABLE     22
-#define NRF51_PPI_CH_RADIO_BCMATCH__AAR_START      23
-#define NRF51_PPI_CH_RADIO_READY__CCM_KSGEN        24
-#define NRF51_PPI_CH_RADIO_ADDR__CCM_CRYPT         25
-#define NRF51_PPI_CH_RADIO_ADDR__TIMER0CC1         26
-#define NRF51_PPI_CH_RADIO_END_TIMER0CC2           27
-#define NRF51_PPI_CH_RTC0_COMPARE0__RADIO_TXEN     28
-#define NRF51_PPI_CH_RTC0_COMPARE0__RADIO_RXEN     29
-#define NRF51_PPI_CH_RTC0_COMPARE0__TIMER0_CLEAR   30
-#define NRF51_PPI_CH_RTC0_COMPARE0__TIMER0_START   31
-
-#define NRF51_PPI_CH_FIRST NRF51_PPI_CH_TIMER0_CC0__RADIO_TXEN
-#define NRF51_PPI_CH_LAST  NRF51_PPI_CH_RTC0_COMPARE0__TIMER0_START
-
-
-/* These will be defined in their respective functions if/when they are used. */
-#define NRF51_SPI0_BASE       0x40003000
-#define NRF51_SPI0_PSELSCK    REG32(NRF51_SPI0_BASE + 0x508)
-#define NRF51_SPI0_PSELMOSI   REG32(NRF51_SPI0_BASE + 0x50C)
-#define NRF51_SPI0_PSELMISO   REG32(NRF51_SPI0_BASE + 0x510)
-#define NRF51_SPI1_BASE       0x40004000
-#define NRF51_SPI1_PSELSCK    REG32(NRF51_SPI1_BASE + 0x508)
-#define NRF51_SPI1_PSELMOSI   REG32(NRF51_SPI1_BASE + 0x50C)
-#define NRF51_SPI1_PSELMISO   REG32(NRF51_SPI1_BASE + 0x510)
-#define NRF51_SPIS1_BASE      0x40004000
-#define NRF51_SPIS1_PSELSCK   REG32(NRF51_SPIS1_BASE + 0x508)
-#define NRF51_SPIS1_PSELMISO  REG32(NRF51_SPIS1_BASE + 0x50C)
-#define NRF51_SPIS1_PSELMOSI  REG32(NRF51_SPIS1_BASE + 0x510)
-#define NRF51_SPIS1_PSELCSN   REG32(NRF51_SPIS1_BASE + 0x514)
-#define NRF51_QDEC_BASE       0x40012000
-#define NRF51_QDEC_PSELLED    REG32(NRF51_QDEC_BASE + 0x51C)
-#define NRF51_QDEC_PSELA      REG32(NRF51_QDEC_BASE + 0x520)
-#define NRF51_QDEC_PSELB      REG32(NRF51_QDEC_BASE + 0x524)
-#define NRF51_LPCOMP_BASE     0x40013000
-#define NRF51_LPCOMP_PSEL     REG32(NRF51_LPCOMP_BASE + 0x504)
-
-#endif /* __CROS_EC_REGISTERS_H */
-
diff --git a/chip/nrf51/system.c b/chip/nrf51/system.c
deleted file mode 100644
index dc7bff2059..0000000000
--- a/chip/nrf51/system.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* System module for Chrome EC : hardware specific implementation */
-
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "cpu.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-const char *system_get_chip_vendor(void)
-{
-	return "nrf";
-}
-
-const char *system_get_chip_name(void)
-{
-	return "nrf51822";
-}
-
-const char *system_get_chip_revision(void)
-{
-	return "";
-}
-
-void system_hibernate(uint32_t seconds, uint32_t microseconds)
-{
-	/* Flush console before hibernating */
-	cflush();
-
-	if (board_hibernate)
-		board_hibernate();
-
-	/* chip specific standby mode */
-	CPRINTS("TODO: implement %s()", __func__);
-}
-
-
-static void check_reset_cause(void)
-{
-	uint32_t flags = 0;
-	uint32_t raw_cause = NRF51_POWER_RESETREAS;
-
-	if (raw_cause & NRF51_POWER_RESETREAS_RESETPIN)
-		flags |= EC_RESET_FLAG_RESET_PIN;
-
-	if (raw_cause & NRF51_POWER_RESETREAS_DOG)
-		flags |= EC_RESET_FLAG_WATCHDOG;
-
-	/* Note that the programmer uses a soft reset in debug mode. */
-	if (raw_cause & NRF51_POWER_RESETREAS_SREQ)
-		flags |= EC_RESET_FLAG_SOFT;
-
-	if (raw_cause & (NRF51_POWER_RESETREAS_OFF |
-			NRF51_POWER_RESETREAS_LPCOMP))
-		flags |= EC_RESET_FLAG_WAKE_PIN;
-
-	if (raw_cause & (NRF51_POWER_RESETREAS_LOCKUP |
-			NRF51_POWER_RESETREAS_DIF))
-		flags |= EC_RESET_FLAG_OTHER;
-
-	system_set_reset_flags(flags);
-
-	/* clear it by writing 1's */
-	NRF51_POWER_RESETREAS = raw_cause;
-}
-
-static void system_watchdog_reset(void)
-{
-	if (NRF51_WDT_TIMEOUT != 0) {
-		/* Hard reset the WDT */
-		NRF51_WDT_POWER = 0;
-		NRF51_WDT_POWER = 1;
-	}
-
-	/* NRF51_WDT_CONFIG_HALT_RUN breaks this */
-	NRF51_WDT_CONFIG = NRF51_WDT_CONFIG_SLEEP_RUN;
-
-	NRF51_WDT_RREN = NRF51_WDT_RREN_BIT(0);
-	NRF51_WDT_CRV = 3; /* @32KHz */
-	NRF51_WDT_START = 1;
-}
-
-void system_reset(int flags)
-{
-	/* Disable interrupts to avoid task swaps during reboot */
-	interrupt_disable();
-
-	if (flags & SYSTEM_RESET_HARD)
-		/* Ask the watchdog to trigger a hard reboot */
-		system_watchdog_reset();
-	else {
-		/* Use SYSRESETREQ to trigger a soft reboot */
-		CPU_NVIC_APINT = 0x05fa0004;
-	}
-
-	/* Spin and wait for reboot; should never return */
-	while (1)
-		;
-}
-
-int system_get_bbram(enum system_bbram_idx idx, uint8_t *value)
-{
-	CPRINTS("TODO: implement %s()", __func__);
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-int system_set_bbram(enum system_bbram_idx idx, uint8_t value)
-{
-	CPRINTS("TODO: implement %s()", __func__);
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-void system_pre_init(void)
-{
-	check_reset_cause();
-}
diff --git a/chip/nrf51/uart.c b/chip/nrf51/uart.c
deleted file mode 100644
index 1f546a2b79..0000000000
--- a/chip/nrf51/uart.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USART driver for Chrome EC */
-
-#include "clock.h"
-#include "console.h"
-#include "common.h"
-#include "dma.h"
-#include "hooks.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "uart.h"
-#include "util.h"
-
-#define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-
-static int ever_sent;    /* if we ever sent byte to TXD? */
-static int init_done;    /* Initialization done? */
-static int should_stop;  /* Last TX control action */
-
-int uart_init_done(void)
-{
-	return init_done;
-}
-
-void uart_tx_start(void)
-{
-	disable_sleep(SLEEP_MASK_UART);
-	should_stop = 0;
-	NRF51_UART_INTENSET = BIT(NRF55_UART_TXDRDY_BIT);
-	task_trigger_irq(NRF51_PERID_USART);
-}
-
-void uart_tx_stop(void)
-{
-	NRF51_UART_INTENCLR = BIT(NRF55_UART_TXDRDY_BIT);
-	should_stop = 1;
-	enable_sleep(SLEEP_MASK_UART);
-}
-
-int uart_tx_ready(void)
-{
-	/*
-	 * nRF51 design is NOT tx-empty style. Instead, it is if a byte is
-	 * ever transmitted from TxD. This means NRF51_UART_TXDRDY is always
-	 * 0 after reset. So, we use 'ever_sent' to send the first byte.
-	 */
-	return NRF51_UART_TXDRDY || (!ever_sent);
-}
-
-int uart_rx_available(void)
-{
-	return NRF51_UART_RXDRDY;
-}
-
-void uart_tx_flush(void)
-{
-	while (!uart_tx_ready())
-		;
-}
-
-void uart_write_char(char c)
-{
-	ever_sent = 1;
-	NRF51_UART_TXDRDY = 0;
-	NRF51_UART_TXD = c;
-	NRF51_UART_STARTTX = 1;
-}
-
-int uart_read_char(void)
-{
-	NRF51_UART_RXDRDY = 0;
-	return NRF51_UART_RXD;
-}
-
-/* Interrupt handler for console USART */
-void uart_interrupt(void)
-{
-#ifndef CONFIG_UART_RX_DMA
-	/*
-	 * Read input FIFO until empty.  DMA-based receive does this from a
-	 * hook in the UART buffering module.
-	 */
-	uart_process_input();
-#endif
-
-	/* Fill output FIFO */
-	uart_process_output();
-
-#ifndef CONFIG_UART_TX_DMA
-	if (!should_stop)
-		NRF51_UART_INTENSET = BIT(NRF55_UART_TXDRDY_BIT);
-#endif  /* CONFIG_UART_TX_DMA */
-
-}
-DECLARE_IRQ(NRF51_PERID_USART, uart_interrupt, 2);
-
-
-void uart_init(void)
-{
-	NRF51_UART_PSELTXD = NRF51_UART_TX_PIN;   /* GPIO Port for Tx */
-	NRF51_UART_PSELRXD = NRF51_UART_RX_PIN;   /* GPIO Port for Rx */
-	NRF51_UART_CONFIG = 0;    /* disable HW flow control, no parity bit */
-	NRF51_UART_BAUDRATE = 0x01d7e000;  /* 115200 */
-	NRF51_UART_ENABLE = 0x4;  /* Enable UART */
-
-	task_enable_irq(NRF51_PERID_USART);
-
-	NRF51_UART_INTENSET = BIT(NRF55_UART_RXDRDY_BIT);
-	NRF51_UART_STARTRX = 1;
-
-	init_done = 1;
-}
diff --git a/chip/nrf51/watchdog.c b/chip/nrf51/watchdog.c
deleted file mode 100644
index da947df48e..0000000000
--- a/chip/nrf51/watchdog.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Watchdog driver */
-
-#include "common.h"
-#include "console.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-
-int watchdog_init(void)
-{
-	CPRINTS("TODO: implement %s()", __func__);
-	return EC_ERROR_UNIMPLEMENTED;
-}
diff --git a/chip/stm32/adc-stm32f0.c b/chip/stm32/adc-stm32f0.c
index d900cbc514..597861cb33 100644
--- a/chip/stm32/adc-stm32f0.c
+++ b/chip/stm32/adc-stm32f0.c
@@ -1,10 +1,9 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "clock.h"
 #include "common.h"
 #include "console.h"
@@ -22,7 +21,7 @@ struct adc_profile_t {
 	/* Register values. */
 	uint32_t cfgr1_reg;
 	uint32_t cfgr2_reg;
-	uint32_t smpr_reg;	/* Default Sampling Rate */
+	uint32_t smpr_reg; /* Default Sampling Rate */
 	uint32_t ier_reg;
 	/* DMA config. */
 	const struct dma_option *dma_option;
@@ -32,7 +31,8 @@ struct adc_profile_t {
 
 #ifdef CONFIG_ADC_PROFILE_SINGLE
 static const struct dma_option dma_single = {
-	STM32_DMAC_ADC, (void *)&STM32_ADC_DR,
+	STM32_DMAC_ADC,
+	(void *)&STM32_ADC_DR,
 	STM32_DMA_CCR_MSIZE_32_BIT | STM32_DMA_CCR_PSIZE_32_BIT,
 };
 
@@ -42,12 +42,9 @@ static const struct dma_option dma_single = {
 
 static const struct adc_profile_t profile = {
 	/* Sample all channels once using DMA */
-	.cfgr1_reg = STM32_ADC_CFGR1_OVRMOD,
-	.cfgr2_reg = 0,
-	.smpr_reg = CONFIG_ADC_SAMPLE_TIME,
-	.ier_reg = 0,
-	.dma_option = &dma_single,
-	.dma_buffer_size = 1,
+	.cfgr1_reg = STM32_ADC_CFGR1_OVRMOD, .cfgr2_reg = 0,
+	.smpr_reg = CONFIG_ADC_SAMPLE_TIME,  .ier_reg = 0,
+	.dma_option = &dma_single,	     .dma_buffer_size = 1,
 };
 #endif
 
@@ -58,15 +55,15 @@ static const struct adc_profile_t profile = {
 #endif
 
 static const struct dma_option dma_continuous = {
-	STM32_DMAC_ADC, (void *)&STM32_ADC_DR,
+	STM32_DMAC_ADC,
+	(void *)&STM32_ADC_DR,
 	STM32_DMA_CCR_MSIZE_32_BIT | STM32_DMA_CCR_PSIZE_32_BIT |
-	STM32_DMA_CCR_CIRC,
+		STM32_DMA_CCR_CIRC,
 };
 
 static const struct adc_profile_t profile = {
 	/* Sample all channels continuously using DMA */
-	.cfgr1_reg = STM32_ADC_CFGR1_OVRMOD |
-		     STM32_ADC_CFGR1_CONT |
+	.cfgr1_reg = STM32_ADC_CFGR1_OVRMOD | STM32_ADC_CFGR1_CONT |
 		     STM32_ADC_CFGR1_DMACFG,
 	.cfgr2_reg = 0,
 	.smpr_reg = CONFIG_ADC_SAMPLE_TIME,
@@ -111,14 +108,14 @@ static void adc_init(const struct adc_t *adc)
 		STM32_ADC_CR = STM32_ADC_CR_ADEN;
 }
 
-static void adc_configure(int ain_id, enum stm32_adc_smpr sample_rate)
+static void adc_configure(int ain_id, enum stm32_adc_smpr sample_time)
 {
 	/* Sampling time */
-	if (sample_rate == STM32_ADC_SMPR_DEFAULT ||
-			sample_rate >= STM32_ADC_SMPR_COUNT)
+	if (sample_time == STM32_ADC_SMPR_DEFAULT ||
+	    sample_time >= STM32_ADC_SMPR_COUNT)
 		STM32_ADC_SMPR = profile.smpr_reg;
 	else
-		STM32_ADC_SMPR = STM32_ADC_SMPR_SMP(sample_rate);
+		STM32_ADC_SMPR = STM32_ADC_SMPR_SMP(sample_time);
 
 	/* Select channel to convert */
 	STM32_ADC_CHSELR = BIT(ain_id);
@@ -161,12 +158,12 @@ static void adc_interval_read(int ain_id, int interval_ms)
 	adc_configure(ain_id, STM32_ADC_SMPR_DEFAULT);
 
 	/* EXTEN=01 -> hardware trigger detection on rising edge */
-	STM32_ADC_CFGR1 = (STM32_ADC_CFGR1 & ~STM32_ADC_CFGR1_EXTEN_MASK)
-		| STM32_ADC_CFGR1_EXTEN_RISE;
+	STM32_ADC_CFGR1 = (STM32_ADC_CFGR1 & ~STM32_ADC_CFGR1_EXTEN_MASK) |
+			  STM32_ADC_CFGR1_EXTEN_RISE;
 
 	/* EXTSEL=TRG3 -> Trigger on TIM3_TRGO */
 	STM32_ADC_CFGR1 = (STM32_ADC_CFGR1 & ~STM32_ADC_CFGR1_TRG_MASK) |
-		STM32_ADC_CFGR1_TRG3;
+			  STM32_ADC_CFGR1_TRG3;
 
 	__hw_timer_enable_clock(TIM_ADC, 1);
 
@@ -294,9 +291,18 @@ int adc_set_watchdog_delay(int delay_ms)
 
 #else /* CONFIG_ADC_WATCHDOG */
 
-static int adc_watchdog_enabled(void) { return 0; }
-static int adc_enable_watchdog_no_lock(void) { return 0; }
-static int adc_disable_watchdog_no_lock(void) { return 0; }
+static int adc_watchdog_enabled(void)
+{
+	return 0;
+}
+static int adc_enable_watchdog_no_lock(void)
+{
+	return 0;
+}
+static int adc_disable_watchdog_no_lock(void)
+{
+	return 0;
+}
 
 #endif /* CONFIG_ADC_WATCHDOG */
 
@@ -315,7 +321,7 @@ int adc_read_channel(enum adc_channel ch)
 		adc_disable_watchdog_no_lock();
 	}
 
-	adc_configure(adc->channel, adc->sample_rate);
+	adc_configure(adc->channel, adc->sample_time);
 
 	/* Clear flags */
 	STM32_ADC_ISR = 0xe;
diff --git a/chip/stm32/adc-stm32f3.c b/chip/stm32/adc-stm32f3.c
index fb3e4604a8..605bb14b69 100644
--- a/chip/stm32/adc-stm32f3.c
+++ b/chip/stm32/adc-stm32f3.c
@@ -1,10 +1,9 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "clock.h"
 #include "common.h"
 #include "console.h"
@@ -17,9 +16,9 @@
 
 #define ADC_SINGLE_READ_TIMEOUT 3000 /* 3 ms */
 
-#define SMPR1_EXPAND(v) ((v) | ((v) << 3) | ((v) << 6) | ((v) << 9) | \
-			 ((v) << 12) | ((v) << 15) | ((v) << 18) | \
-			 ((v) << 21))
+#define SMPR1_EXPAND(v)                                             \
+	((v) | ((v) << 3) | ((v) << 6) | ((v) << 9) | ((v) << 12) | \
+	 ((v) << 15) | ((v) << 18) | ((v) << 21))
 #define SMPR2_EXPAND(v) (SMPR1_EXPAND(v) | ((v) << 24) | ((v) << 27))
 
 /* Default ADC sample time = 13.5 cycles */
@@ -216,8 +215,9 @@ int adc_read_channel(enum adc_channel ch)
 		adc_enable_watchdog_no_lock();
 
 	mutex_unlock(&adc_lock);
-	return (value == ADC_READ_ERROR) ? ADC_READ_ERROR :
-	       value * adc->factor_mul / adc->factor_div + adc->shift;
+	return (value == ADC_READ_ERROR) ?
+		       ADC_READ_ERROR :
+		       value * adc->factor_mul / adc->factor_div + adc->shift;
 }
 
 static void adc_init(void)
diff --git a/chip/stm32/adc-stm32f4.c b/chip/stm32/adc-stm32f4.c
deleted file mode 120000
index 5e375b9dbf..0000000000
--- a/chip/stm32/adc-stm32f4.c
+++ /dev/null
@@ -1 +0,0 @@
-adc-stm32f3.c
\ No newline at end of file
diff --git a/chip/stm32/adc-stm32f4.c b/chip/stm32/adc-stm32f4.c
new file mode 100644
index 0000000000..605bb14b69
--- /dev/null
+++ b/chip/stm32/adc-stm32f4.c
@@ -0,0 +1,260 @@
+/* Copyright 2012 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc.h"
+#include "clock.h"
+#include "common.h"
+#include "console.h"
+#include "dma.h"
+#include "hooks.h"
+#include "registers.h"
+#include "task.h"
+#include "timer.h"
+#include "util.h"
+
+#define ADC_SINGLE_READ_TIMEOUT 3000 /* 3 ms */
+
+#define SMPR1_EXPAND(v)                                             \
+	((v) | ((v) << 3) | ((v) << 6) | ((v) << 9) | ((v) << 12) | \
+	 ((v) << 15) | ((v) << 18) | ((v) << 21))
+#define SMPR2_EXPAND(v) (SMPR1_EXPAND(v) | ((v) << 24) | ((v) << 27))
+
+/* Default ADC sample time = 13.5 cycles */
+#ifndef CONFIG_ADC_SAMPLE_TIME
+#define CONFIG_ADC_SAMPLE_TIME 2
+#endif
+
+struct mutex adc_lock;
+
+static int watchdog_ain_id;
+
+static inline void adc_set_channel(int sample_id, int channel)
+{
+	uint32_t mask, val;
+	volatile uint32_t *sqr_reg;
+
+	if (sample_id < 6) {
+		mask = 0x1f << (sample_id * 5);
+		val = channel << (sample_id * 5);
+		sqr_reg = &STM32_ADC_SQR3;
+	} else if (sample_id < 12) {
+		mask = 0x1f << ((sample_id - 6) * 5);
+		val = channel << ((sample_id - 6) * 5);
+		sqr_reg = &STM32_ADC_SQR2;
+	} else {
+		mask = 0x1f << ((sample_id - 12) * 5);
+		val = channel << ((sample_id - 12) * 5);
+		sqr_reg = &STM32_ADC_SQR1;
+	}
+
+	*sqr_reg = (*sqr_reg & ~mask) | val;
+}
+
+static void adc_configure(int ain_id)
+{
+	/* Set ADC channel */
+	adc_set_channel(0, ain_id);
+
+	/* Disable DMA */
+	STM32_ADC_CR2 &= ~BIT(8);
+
+	/* Disable scan mode */
+	STM32_ADC_CR1 &= ~BIT(8);
+}
+
+static void __attribute__((unused)) adc_configure_all(void)
+{
+	int i;
+
+	/* Set ADC channels */
+	STM32_ADC_SQR1 = (ADC_CH_COUNT - 1) << 20;
+	for (i = 0; i < ADC_CH_COUNT; ++i)
+		adc_set_channel(i, adc_channels[i].channel);
+
+	/* Enable DMA */
+	STM32_ADC_CR2 |= BIT(8);
+
+	/* Enable scan mode */
+	STM32_ADC_CR1 |= BIT(8);
+}
+
+static inline int adc_powered(void)
+{
+	return STM32_ADC_CR2 & BIT(0);
+}
+
+static inline int adc_conversion_ended(void)
+{
+	return STM32_ADC_SR & BIT(1);
+}
+
+static int adc_watchdog_enabled(void)
+{
+	return STM32_ADC_CR1 & BIT(23);
+}
+
+static int adc_enable_watchdog_no_lock(void)
+{
+	/* Fail if watchdog already enabled */
+	if (adc_watchdog_enabled())
+		return EC_ERROR_UNKNOWN;
+
+	/* Set channel */
+	STM32_ADC_SQR3 = watchdog_ain_id;
+	STM32_ADC_SQR1 = 0;
+	STM32_ADC_CR1 = (STM32_ADC_CR1 & ~0x1f) | watchdog_ain_id;
+
+	/* Clear interrupt bit */
+	STM32_ADC_SR &= ~0x1;
+
+	/* AWDSGL=1, SCAN=1, AWDIE=1, AWDEN=1 */
+	STM32_ADC_CR1 |= BIT(9) | BIT(8) | BIT(6) | BIT(23);
+
+	/* Disable DMA */
+	STM32_ADC_CR2 &= ~BIT(8);
+
+	/* CONT=1 */
+	STM32_ADC_CR2 |= BIT(1);
+
+	/* Start conversion */
+	STM32_ADC_CR2 |= BIT(0);
+
+	return EC_SUCCESS;
+}
+
+int adc_enable_watchdog(int ain_id, int high, int low)
+{
+	int ret;
+
+	if (!adc_powered())
+		return EC_ERROR_UNKNOWN;
+
+	mutex_lock(&adc_lock);
+
+	watchdog_ain_id = ain_id;
+
+	/* Set thresholds */
+	STM32_ADC_HTR = high & 0xfff;
+	STM32_ADC_LTR = low & 0xfff;
+
+	ret = adc_enable_watchdog_no_lock();
+	mutex_unlock(&adc_lock);
+	return ret;
+}
+
+static int adc_disable_watchdog_no_lock(void)
+{
+	/* Fail if watchdog not running */
+	if (!adc_watchdog_enabled())
+		return EC_ERROR_UNKNOWN;
+
+	/* AWDEN=0, AWDIE=0 */
+	STM32_ADC_CR1 &= ~BIT(23) & ~BIT(6);
+
+	/* CONT=0 */
+	STM32_ADC_CR2 &= ~BIT(1);
+
+	return EC_SUCCESS;
+}
+
+int adc_disable_watchdog(void)
+{
+	int ret;
+
+	if (!adc_powered())
+		return EC_ERROR_UNKNOWN;
+
+	mutex_lock(&adc_lock);
+	ret = adc_disable_watchdog_no_lock();
+	mutex_unlock(&adc_lock);
+	return ret;
+}
+
+int adc_read_channel(enum adc_channel ch)
+{
+	const struct adc_t *adc = adc_channels + ch;
+	int value;
+	int restore_watchdog = 0;
+	timestamp_t deadline;
+
+	if (!adc_powered())
+		return EC_ERROR_UNKNOWN;
+
+	mutex_lock(&adc_lock);
+
+	if (adc_watchdog_enabled()) {
+		restore_watchdog = 1;
+		adc_disable_watchdog_no_lock();
+	}
+
+	adc_configure(adc->channel);
+
+	/* Clear EOC bit */
+	STM32_ADC_SR &= ~BIT(1);
+
+	/* Start conversion (Note: For now only confirmed on F4) */
+#if defined(CHIP_FAMILY_STM32F4)
+	STM32_ADC_CR2 |= STM32_ADC_CR2_ADON | STM32_ADC_CR2_SWSTART;
+#else
+	STM32_ADC_CR2 |= STM32_ADC_CR2_ADON;
+#endif
+
+	/* Wait for EOC bit set */
+	deadline.val = get_time().val + ADC_SINGLE_READ_TIMEOUT;
+	value = ADC_READ_ERROR;
+	do {
+		if (adc_conversion_ended()) {
+			value = STM32_ADC_DR & ADC_READ_MAX;
+			break;
+		}
+	} while (!timestamp_expired(deadline, NULL));
+
+	if (restore_watchdog)
+		adc_enable_watchdog_no_lock();
+
+	mutex_unlock(&adc_lock);
+	return (value == ADC_READ_ERROR) ?
+		       ADC_READ_ERROR :
+		       value * adc->factor_mul / adc->factor_div + adc->shift;
+}
+
+static void adc_init(void)
+{
+	/*
+	 * Enable ADC clock.
+	 * APB2 clock is 16MHz. ADC clock prescaler is /2.
+	 * So the ADC clock is 8MHz.
+	 */
+	clock_enable_module(MODULE_ADC, 1);
+
+	/*
+	 * ADC clock is divided with respect to AHB, so no delay needed
+	 * here. If ADC clock is the same as AHB, a read on ADC
+	 * register is needed here.
+	 */
+
+	if (!adc_powered()) {
+		/* Power on ADC module */
+		STM32_ADC_CR2 |= STM32_ADC_CR2_ADON;
+
+		/* Reset calibration */
+		STM32_ADC_CR2 |= STM32_ADC_CR2_RSTCAL;
+		while (STM32_ADC_CR2 & STM32_ADC_CR2_RSTCAL)
+			;
+
+		/* A/D Calibrate */
+		STM32_ADC_CR2 |= STM32_ADC_CR2_CAL;
+		while (STM32_ADC_CR2 & STM32_ADC_CR2_CAL)
+			;
+	}
+
+	/* Set right alignment */
+	STM32_ADC_CR2 &= ~STM32_ADC_CR2_ALIGN;
+
+	/* Set sample time of all channels */
+	STM32_ADC_SMPR1 = SMPR1_EXPAND(CONFIG_ADC_SAMPLE_TIME);
+	STM32_ADC_SMPR2 = SMPR2_EXPAND(CONFIG_ADC_SAMPLE_TIME);
+}
+DECLARE_HOOK(HOOK_INIT, adc_init, HOOK_PRIO_INIT_ADC);
diff --git a/chip/stm32/adc-stm32l.c b/chip/stm32/adc-stm32l.c
index 199b64c81f..06b16224f7 100644
--- a/chip/stm32/adc-stm32l.c
+++ b/chip/stm32/adc-stm32l.c
@@ -1,13 +1,12 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "adc.h"
-#include "adc_chip.h"
+#include "clock.h"
 #include "common.h"
 #include "console.h"
-#include "clock.h"
 #include "dma.h"
 #include "hooks.h"
 #include "registers.h"
@@ -92,7 +91,7 @@ static void adc_init(void)
 
 	if (!adc_powered())
 		/* Power on ADC module */
-		STM32_ADC_CR2 |= BIT(0);  /* ADON */
+		STM32_ADC_CR2 |= BIT(0); /* ADON */
 
 	/* Set right alignment */
 	STM32_ADC_CR2 &= ~BIT(11);
@@ -166,6 +165,7 @@ int adc_read_channel(enum adc_channel ch)
 	adc_release();
 
 	mutex_unlock(&adc_lock);
-	return (value == ADC_READ_ERROR) ? ADC_READ_ERROR :
-	       value * adc->factor_mul / adc->factor_div + adc->shift;
+	return (value == ADC_READ_ERROR) ?
+		       ADC_READ_ERROR :
+		       value * adc->factor_mul / adc->factor_div + adc->shift;
 }
diff --git a/chip/stm32/adc-stm32l4.c b/chip/stm32/adc-stm32l4.c
new file mode 100644
index 0000000000..c81978d6ce
--- /dev/null
+++ b/chip/stm32/adc-stm32l4.c
@@ -0,0 +1,245 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* ADC drivers for STM32L4xx as well as STM32L5xx. */
+
+#include "adc.h"
+#include "clock.h"
+#include "common.h"
+#include "console.h"
+#include "dma.h"
+#include "hooks.h"
+#include "hwtimer.h"
+#include "registers.h"
+#include "task.h"
+#include "timer.h"
+#include "util.h"
+
+struct mutex adc_lock;
+
+struct adc_profile_t {
+	/* Register values. */
+	uint32_t cfgr1_reg;
+	uint32_t cfgr2_reg;
+	uint32_t smpr_reg; /* Default Sampling Rate */
+	uint32_t ier_reg;
+	/* DMA config. */
+	const struct dma_option *dma_option;
+	/* Size of DMA buffer, in units of ADC_CH_COUNT. */
+	int dma_buffer_size;
+};
+
+#ifdef CONFIG_ADC_PROFILE_SINGLE
+#ifndef CONFIG_ADC_SAMPLE_TIME
+#define CONFIG_ADC_SAMPLE_TIME STM32_ADC_SMPR_12_5_CY
+#endif
+#endif
+
+#define ADC_CALIBRATION_TIMEOUT_US 100000U
+#define ADC_ENABLE_TIMEOUT_US 200000U
+#define ADC_CONVERSION_TIMEOUT_US 200000U
+
+static uint8_t adc1_initialized;
+
+#ifdef CONFIG_ADC_PROFILE_FAST_CONTINUOUS
+#error "Continuous ADC sampling not implemented for STM32L4/5"
+
+#ifndef CONFIG_ADC_SAMPLE_TIME
+#define CONFIG_ADC_SAMPLE_TIME STM32_ADC_SMPR_1_5_CY
+#endif
+
+static const struct dma_option dma_continuous = {
+	STM32_DMAC_ADC,
+	(void *)&STM32_ADC_DR,
+	STM32_DMA_CCR_MSIZE_32_BIT | STM32_DMA_CCR_PSIZE_32_BIT |
+		STM32_DMA_CCR_CIRC,
+};
+
+static const struct adc_profile_t profile = {
+	/* Sample all channels continuously using DMA */
+	.cfgr1_reg = STM32_ADC_CFGR1_OVRMOD | STM32_ADC_CFGR1_CONT |
+		     STM32_ADC_CFGR1_DMACFG,
+	.cfgr2_reg = 0,
+	.smpr_reg = CONFIG_ADC_SAMPLE_TIME,
+	/* Fire interrupt at end of sequence. */
+	.ier_reg = STM32_ADC_IER_EOSEQIE,
+	.dma_option = &dma_continuous,
+	/* Double-buffer our samples. */
+	.dma_buffer_size = 2,
+};
+#endif
+
+static void adc_init(void)
+{
+	/*
+	 * If clock is already enabled, and ADC module is enabled
+	 * then this is a warm reboot and ADC is already initialized.
+	 */
+
+	if (STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_ADCEN &&
+	    (STM32_ADC1_CR & STM32_ADC1_CR_ADEN))
+		return;
+
+	/* Enable ADC clock */
+	clock_enable_module(MODULE_ADC, 1);
+
+	/* set ADC clock to 20MHz */
+	STM32_ADC1_CCR &= ~0x003C0000;
+	STM32_ADC1_CCR |= 0x00080000;
+
+	STM32_RCC_AHB2ENR |= STM32_RCC_HB2_GPIOA;
+	STM32_RCC_AHB2ENR |= STM32_RCC_HB2_GPIOB;
+
+	/* Set ADC data resolution */
+	STM32_ADC1_CFGR &= ~STM32_ADC1_CFGR_CONT;
+	/* Set ADC conversion data alignment */
+	STM32_ADC1_CFGR &= ~STM32_ADC1_CFGR_ALIGN;
+	/* Set ADC delayed conversion mode */
+	STM32_ADC1_CFGR &= ~STM32_ADC1_CFGR_AUTDLY;
+}
+
+BUILD_ASSERT(CONFIG_ADC_SAMPLE_TIME > 0 && CONFIG_ADC_SAMPLE_TIME <= 8);
+
+static void adc_configure_channel(int ain_id, enum stm32_adc_smpr sample_time)
+{
+	/* Select Sampling time for channel to convert */
+	if (sample_time == STM32_ADC_SMPR_DEFAULT)
+		sample_time = CONFIG_ADC_SAMPLE_TIME;
+
+	if (ain_id <= 10) {
+		STM32_ADC1_SMPR1 &= ~(7 << ((ain_id - 1) * 3));
+		STM32_ADC1_SMPR1 |= ((sample_time - 1) << ((ain_id - 1) * 3));
+	} else {
+		STM32_ADC1_SMPR2 &= ~(7 << ((ain_id - 11) * 3));
+		STM32_ADC1_SMPR2 |= ((sample_time - 1) << ((ain_id - 11) * 3));
+	}
+}
+
+static void adc_select_channel(int ain_id)
+{
+	/* Setup an "injected sequence" consisting of only this one channel. */
+	STM32_ADC1_JSQR = ain_id << 8;
+}
+
+static void stm32_adc1_isr_clear(uint32_t bitmask)
+{
+	/* Write 1 to clear */
+	STM32_ADC1_ISR = bitmask;
+}
+
+int adc_read_channel(enum adc_channel ch)
+{
+	const struct adc_t *adc = adc_channels + ch;
+
+	int value = 0;
+	uint32_t wait_loop_index;
+
+	mutex_lock(&adc_lock);
+
+	if (adc1_initialized == 0) {
+		adc_init();
+
+		/* Configure Channel N */
+		for (uint8_t i = 0; i < ADC_CH_COUNT; i++) {
+			const struct adc_t *adc = adc_channels + i;
+
+			adc_configure_channel(adc->channel, adc->sample_time);
+		}
+
+		/* Disable DMA */
+		STM32_ADC1_CFGR &= ~STM32_ADC1_CFGR_DMAEN;
+
+		if ((STM32_ADC1_CR & STM32_ADC1_CR_ADEN) !=
+		    STM32_ADC1_CR_ADEN) {
+			/* Disable ADC deep power down (enabled by default after
+			 * reset state)
+			 */
+			STM32_ADC1_CR &= ~STM32_ADC1_CR_DEEPPWD;
+			/* Enable ADC internal voltage regulator */
+			STM32_ADC1_CR |= STM32_ADC1_CR_ADVREGEN;
+		}
+
+		/*
+		 * Delay for ADC internal voltage regulator stabilization.
+		 * Compute number of CPU cycles to wait for, from delay in us.
+		 *
+		 * Note: Variable divided by 2 to compensate partially
+		 * CPU processing cycles (depends on compilation optimization).
+		 *
+		 * Note: If system core clock frequency is below 200kHz, wait
+		 * time is only a few CPU processing cycles.
+		 */
+		wait_loop_index = ((20 * (80000000 / (100000 * 2))) / 10);
+		while (wait_loop_index-- != 0)
+			;
+
+		/* Run ADC self calibration */
+		STM32_ADC1_CR |= STM32_ADC1_CR_ADCAL;
+
+		/* wait for the end of calibration */
+		wait_loop_index = ((ADC_CALIBRATION_TIMEOUT_US *
+				    (CPU_CLOCK / (100000 * 2))) /
+				   10);
+		while (STM32_ADC1_CR & STM32_ADC1_CR_ADCAL) {
+			if (wait_loop_index-- == 0)
+				break;
+		}
+
+		/* Enable ADC */
+		stm32_adc1_isr_clear(STM32_ADC1_ISR_ADRDY);
+		STM32_ADC1_CR |= STM32_ADC1_CR_ADEN;
+		wait_loop_index =
+			((ADC_ENABLE_TIMEOUT_US * (CPU_CLOCK / (100000 * 2))) /
+			 10);
+		while (!(STM32_ADC1_ISR & STM32_ADC1_ISR_ADRDY)) {
+			wait_loop_index--;
+			if (wait_loop_index == 0)
+				break;
+		}
+		stm32_adc1_isr_clear(STM32_ADC1_ISR_ADRDY);
+
+		adc1_initialized = 1;
+	}
+
+	/* Configure Injected Channel N */
+	adc_select_channel(adc->channel);
+
+	/* Start injected conversion */
+	STM32_ADC1_CR |= BIT(3); /* JADSTART */
+
+	/* Wait for end of injected conversion */
+	wait_loop_index =
+		((ADC_CONVERSION_TIMEOUT_US * (CPU_CLOCK / (100000 * 2))) / 10);
+	while (!(STM32_ADC1_ISR & BIT(6))) {
+		if (wait_loop_index-- == 0)
+			break;
+	}
+
+	/* Clear JEOS bit */
+	stm32_adc1_isr_clear(BIT(6));
+
+	/* read converted value */
+	value = STM32_ADC1_JDR1;
+
+	mutex_unlock(&adc_lock);
+
+	return value * adc->factor_mul / adc->factor_div + adc->shift;
+}
+
+void adc_disable(void)
+{
+	/* Disable ADC */
+	/* Do not Set ADDIS when ADC is disabled */
+	adc1_initialized = 0;
+
+	if (STM32_ADC1_CR & STM32_ADC1_CR_ADEN)
+		STM32_ADC1_CR |= STM32_ADC1_CR_ADDIS;
+
+	/*
+	 * Note that the ADC is not in OFF state immediately.
+	 * Once the ADC is effectively put into OFF state,
+	 * STM32_ADC_CR_ADDIS bit will be cleared by hardware.
+	 */
+}
diff --git a/chip/stm32/adc-stm32l5.c b/chip/stm32/adc-stm32l5.c
new file mode 100644
index 0000000000..94a85fb70b
--- /dev/null
+++ b/chip/stm32/adc-stm32l5.c
@@ -0,0 +1,6 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc-stm32l4.c"
diff --git a/chip/stm32/adc_chip.h b/chip/stm32/adc_chip.h
index 413653e4d7..2677f1d9cc 100644
--- a/chip/stm32/adc_chip.h
+++ b/chip/stm32/adc_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,8 +8,20 @@
 #ifndef __CROS_EC_ADC_CHIP_H
 #define __CROS_EC_ADC_CHIP_H
 
-#include "stdint.h"
-
+#if defined(CHIP_FAMILY_STM32L4) || defined(CHIP_FAMILY_STM32L5)
+enum stm32_adc_smpr {
+	STM32_ADC_SMPR_DEFAULT = 0,
+	STM32_ADC_SMPR_2_5_CY,
+	STM32_ADC_SMPR_6_5_CY,
+	STM32_ADC_SMPR_12_5_CY,
+	STM32_ADC_SMPR_24_5_CY,
+	STM32_ADC_SMPR_47_5_CY,
+	STM32_ADC_SMPR_92_5_CY,
+	STM32_ADC_SMPR_247_5_CY,
+	STM32_ADC_SMPR_640_5_CY,
+	STM32_ADC_SMPR_COUNT,
+};
+#else
 enum stm32_adc_smpr {
 	STM32_ADC_SMPR_DEFAULT = 0,
 	STM32_ADC_SMPR_1_5_CY,
@@ -22,6 +34,7 @@ enum stm32_adc_smpr {
 	STM32_ADC_SMPR_239_5_CY,
 	STM32_ADC_SMPR_COUNT,
 };
+#endif
 
 /* Data structure to define ADC channels. */
 struct adc_t {
@@ -30,18 +43,13 @@ struct adc_t {
 	int factor_div;
 	int shift;
 	int channel;
-#ifdef CHIP_FAMILY_STM32F0
-	enum stm32_adc_smpr sample_rate;  /* Sampling Rate of the channel */
+
+#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32L4) || \
+	defined(CHIP_FAMILY_STM32L5)
+	enum stm32_adc_smpr sample_time; /* Sampling Time of the channel */
 #endif
 };
 
-/*
- * Boards must provide this list of ADC channel definitions.  This must match
- * the enum adc_channel list provided by the board. Also, for STM32F0, this
- * must be ordered by AIN ID.
- */
-extern const struct adc_t adc_channels[];
-
 /* Disable ADC module when we don't need it anymore. */
 void adc_disable(void);
 
diff --git a/chip/stm32/bkpdata.c b/chip/stm32/bkpdata.c
index 2b26ace7ea..ef5729d118 100644
--- a/chip/stm32/bkpdata.c
+++ b/chip/stm32/bkpdata.c
@@ -1,15 +1,15 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <assert.h>
-
 #include "bkpdata.h"
 #include "registers.h"
 #include "system.h" /* enum system_bbram_idx */
 #include "task.h"
 
+#include <assert.h>
+
 uint16_t bkpdata_read(enum bkpdata_index index)
 {
 	if (index < 0 || index >= STM32_BKP_ENTRIES)
@@ -24,6 +24,7 @@ uint16_t bkpdata_read(enum bkpdata_index index)
 int bkpdata_write(enum bkpdata_index index, uint16_t value)
 {
 	static struct mutex bkpdata_write_mutex;
+	int use_mutex = !in_interrupt_context();
 
 	if (index < 0 || index >= STM32_BKP_ENTRIES)
 		return EC_ERROR_INVAL;
@@ -32,7 +33,8 @@ int bkpdata_write(enum bkpdata_index index, uint16_t value)
 	 * Two entries share a single 32-bit register, lock mutex to prevent
 	 * read/mask/write races.
 	 */
-	mutex_lock(&bkpdata_write_mutex);
+	if (use_mutex)
+		mutex_lock(&bkpdata_write_mutex);
 	if (index & 1) {
 		uint32_t val = STM32_BKP_DATA(index >> 1);
 		val = (val & 0x0000FFFF) | (value << 16);
@@ -42,7 +44,8 @@ int bkpdata_write(enum bkpdata_index index, uint16_t value)
 		val = (val & 0xFFFF0000) | value;
 		STM32_BKP_DATA(index >> 1) = val;
 	}
-	mutex_unlock(&bkpdata_write_mutex);
+	if (use_mutex)
+		mutex_unlock(&bkpdata_write_mutex);
 
 	return EC_SUCCESS;
 }
@@ -51,14 +54,6 @@ int bkpdata_index_lookup(enum system_bbram_idx idx, int *msb)
 {
 	*msb = 0;
 
-#ifdef CONFIG_HOSTCMD_VBNV_CONTEXT
-	if (idx >= SYSTEM_BBRAM_IDX_VBNVBLOCK0 &&
-	    idx <= SYSTEM_BBRAM_IDX_VBNVBLOCK15) {
-		*msb = (idx - SYSTEM_BBRAM_IDX_VBNVBLOCK0) % 2;
-		return BKPDATA_INDEX_VBNV_CONTEXT0 +
-		       (idx - SYSTEM_BBRAM_IDX_VBNVBLOCK0) / 2;
-	}
-#endif
 #ifdef CONFIG_USB_PD_DUAL_ROLE
 	if (idx == SYSTEM_BBRAM_IDX_PD0)
 		return BKPDATA_INDEX_PD0;
@@ -70,24 +65,21 @@ int bkpdata_index_lookup(enum system_bbram_idx idx, int *msb)
 	return -1;
 }
 
-uint32_t bkpdata_read_reset_flags()
+uint32_t bkpdata_read_reset_flags(void)
 {
 	uint32_t flags = bkpdata_read(BKPDATA_INDEX_SAVED_RESET_FLAGS);
-#ifdef CONFIG_STM32_RESET_FLAGS_EXTENDED
+
+#ifdef CONFIG_STM32_EXTENDED_RESET_FLAGS
 	flags |= bkpdata_read(BKPDATA_INDEX_SAVED_RESET_FLAGS_2) << 16;
 #endif
+
 	return flags;
 }
 
-__overridable
-void bkpdata_write_reset_flags(uint32_t save_flags)
+__overridable void bkpdata_write_reset_flags(uint32_t save_flags)
 {
-#ifdef CONFIG_STM32_RESET_FLAGS_EXTENDED
 	bkpdata_write(BKPDATA_INDEX_SAVED_RESET_FLAGS, save_flags & 0xffff);
+#ifdef CONFIG_STM32_EXTENDED_RESET_FLAGS
 	bkpdata_write(BKPDATA_INDEX_SAVED_RESET_FLAGS_2, save_flags >> 16);
-#else
-	/* Reset flags are 32-bits, but BBRAM entry is only 16 bits. */
-	ASSERT(!(save_flags >> 16));
-	bkpdata_write(BKPDATA_INDEX_SAVED_RESET_FLAGS, save_flags);
 #endif
 }
diff --git a/chip/stm32/bkpdata.h b/chip/stm32/bkpdata.h
index 07f20aed49..5b656b16dc 100644
--- a/chip/stm32/bkpdata.h
+++ b/chip/stm32/bkpdata.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,45 +16,28 @@
 #define STM32_BKP_ENTRIES (STM32_BKP_BYTES / 2)
 
 /*
- * Use 32-bit for reset flags, if we have space for it:
- *  - 2 indexes are used unconditionally (SCRATCHPAD and SAVED_RESET_FLAGS)
- *  - VBNV_CONTEXT requires 8 indexes, so a total of 10 (which is the total
- *    number of entries on some STM32 variants).
- *  - Other config options are not a problem (they only take a few entries)
- *
- * Given this, we can only add an extra entry for the top 16-bit of reset flags
- * if VBNV_CONTEXT is not enabled, or if we have more than 10 entries.
+ * Add new entries at the end of the enum. Otherwise you will break RO/RW
+ * compatibility.
  */
-#if !defined(CONFIG_HOSTCMD_VBNV_CONTEXT) || STM32_BKP_ENTRIES > 10
-#define CONFIG_STM32_RESET_FLAGS_EXTENDED
-#endif
-
 enum bkpdata_index {
-	BKPDATA_INDEX_SCRATCHPAD,	     /* General-purpose scratchpad */
-	BKPDATA_INDEX_SAVED_RESET_FLAGS,     /* Saved reset flags */
-#ifdef CONFIG_STM32_RESET_FLAGS_EXTENDED
-	BKPDATA_INDEX_SAVED_RESET_FLAGS_2,   /* Saved reset flags (cont) */
+	BKPDATA_INDEX_SCRATCHPAD, /* General-purpose scratchpad */
+	BKPDATA_INDEX_SAVED_RESET_FLAGS, /* Saved reset flags */
+#ifdef CONFIG_STM32_EXTENDED_RESET_FLAGS
+	BKPDATA_INDEX_SAVED_RESET_FLAGS_2, /* Saved reset flags (cont) */
 #endif
-#ifdef CONFIG_HOSTCMD_VBNV_CONTEXT
-	BKPDATA_INDEX_VBNV_CONTEXT0,
-	BKPDATA_INDEX_VBNV_CONTEXT1,
-	BKPDATA_INDEX_VBNV_CONTEXT2,
-	BKPDATA_INDEX_VBNV_CONTEXT3,
-	BKPDATA_INDEX_VBNV_CONTEXT4,
-	BKPDATA_INDEX_VBNV_CONTEXT5,
-	BKPDATA_INDEX_VBNV_CONTEXT6,
-	BKPDATA_INDEX_VBNV_CONTEXT7,
-#endif
-#ifdef CONFIG_SOFTWARE_PANIC
-	BKPDATA_INDEX_SAVED_PANIC_REASON,    /* Saved panic reason */
-	BKPDATA_INDEX_SAVED_PANIC_INFO,      /* Saved panic data */
+	BKPDATA_INDEX_SAVED_PANIC_REASON, /* Saved panic reason */
+	BKPDATA_INDEX_SAVED_PANIC_INFO, /* Saved panic data */
 	BKPDATA_INDEX_SAVED_PANIC_EXCEPTION, /* Saved panic exception code */
-#endif
 #ifdef CONFIG_USB_PD_DUAL_ROLE
-	BKPDATA_INDEX_PD0,		     /* USB-PD saved port0 state */
-	BKPDATA_INDEX_PD1,		     /* USB-PD saved port1 state */
-	BKPDATA_INDEX_PD2,		     /* USB-PD saved port2 state */
+	BKPDATA_INDEX_PD0, /* USB-PD saved port0 state */
+	BKPDATA_INDEX_PD1, /* USB-PD saved port1 state */
+	BKPDATA_INDEX_PD2, /* USB-PD saved port2 state */
 #endif
+	/**
+	 * Saving the panic flags in case that AP thinks the panic is new
+	 * after a hard reset.
+	 */
+	BKPDATA_INDEX_SAVED_PANIC_FLAGS, /* Saved panic flags */
 	BKPDATA_COUNT
 };
 BUILD_ASSERT(STM32_BKP_ENTRIES >= BKPDATA_COUNT);
diff --git a/chip/stm32/build.mk b/chip/stm32/build.mk
index f2d5720961..41ceaeb12c 100644
--- a/chip/stm32/build.mk
+++ b/chip/stm32/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
+# Copyright 2013 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -9,45 +9,44 @@
 ifeq ($(CHIP_FAMILY),stm32f0)
 # STM32F0xx sub-family has a Cortex-M0 ARM core
 CORE:=cortex-m0
-# Force ARMv6-M ISA used by the Cortex-M0
-# For historical reasons gcc calls it armv6s-m: ARM used to have ARMv6-M
-# without "svc" instruction, but that was short-lived. ARMv6S-M was the option
-# with "svc". GCC kept that naming scheme even though the distinction is long
-# gone.
-CFLAGS_CPU+=-march=armv6s-m -mcpu=cortex-m0
+CFLAGS_CPU+=-mcpu=cortex-m0
 else ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32f3 stm32l4 stm32f4 \
 stm32g4))
 # STM32F3xx and STM32L4xx sub-family has a Cortex-M4 ARM core
 CORE:=cortex-m
 # Allow the full Cortex-M4 instruction set
-CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
+CFLAGS_CPU+=-mcpu=cortex-m4
 else ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32h7))
 # STM32FH7xx family has a Cortex-M7 ARM core
 CORE:=cortex-m
-# Allow the full Cortex-M4 instruction set (identical to M7)
-CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
+# Allow the full Cortex-M7 instruction set.
+CFLAGS_CPU+=-mcpu=cortex-m7
+else ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32l5))
+# STM32FL5xx family has a Cortex-M33 ARM core
+CORE:=cortex-m
+# Allow the full Cortex-M33 instruction set
+CFLAGS_CPU+=-mcpu=cortex-m33
 else
 # other STM32 SoCs have a Cortex-M3 ARM core
 CORE:=cortex-m
 # Force Cortex-M3 subset of instructions
-CFLAGS_CPU+=-march=armv7-m -mcpu=cortex-m3
+CFLAGS_CPU+=-mcpu=cortex-m3
 endif
 
-# Select between 16-bit and 32-bit timer for clock source
-TIMER_TYPE=$(if $(CONFIG_STM_HWTIMER32),32,)
 DMA_TYPE=$(if $(CHIP_FAMILY_STM32F4)$(CHIP_FAMILY_STM32H7),-stm32f4,)
 SPI_TYPE=$(if $(CHIP_FAMILY_STM32H7),-stm32h7,)
 
-chip-$(CONFIG_DMA)+=dma$(DMA_TYPE).o
+chip-$(CONFIG_DMA_CROS)+=dma$(DMA_TYPE).o
 chip-$(CONFIG_COMMON_RUNTIME)+=bkpdata.o system.o
 chip-y+=clock-$(CHIP_FAMILY).o
 ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32f0 stm32f3 stm32f4))
 chip-y+=clock-f.o
 endif
+chip-$(CONFIG_FPU)+=fpu.o
 chip-$(CONFIG_SPI)+=spi.o
-chip-$(CONFIG_SPI_MASTER)+=spi_master$(SPI_TYPE).o
+chip-$(CONFIG_SPI_CONTROLLER)+=spi_controller$(SPI_TYPE).o
 chip-$(CONFIG_COMMON_GPIO)+=gpio.o gpio-$(CHIP_FAMILY).o
-chip-$(CONFIG_COMMON_TIMER)+=hwtimer$(TIMER_TYPE).o
+chip-$(CONFIG_COMMON_TIMER)+=hwtimer32.o
 chip-$(CONFIG_I2C)+=i2c-$(CHIP_FAMILY).o
 chip-$(CONFIG_ITE_FLASH_SUPPORT)+=i2c_ite_flash_support.o
 chip-$(CONFIG_STREAM_USART)+=usart.o usart-$(CHIP_FAMILY).o
@@ -56,15 +55,15 @@ chip-$(CONFIG_STREAM_USART)+=usart_tx_interrupt.o
 chip-$(CONFIG_STREAM_USART)+=usart_rx_dma.o usart_tx_dma.o
 chip-$(CONFIG_USART_HOST_COMMAND)+=usart_host_command.o
 chip-$(CONFIG_CMD_USART_INFO)+=usart_info_command.o
-chip-$(HAS_TASK_CONSOLE)+=host_command_common.o
+chip-$(CONFIG_FINGERPRINT_MCU)+=host_command_common.o
 chip-$(CONFIG_WATCHDOG)+=watchdog.o
 chip-$(HAS_TASK_CONSOLE)+=uart.o
-ifndef CONFIG_KEYBOARD_NOT_RAW
+ifndef CONFIG_KEYBOARD_DISCRETE
 chip-$(HAS_TASK_KEYSCAN)+=keyboard_raw.o
 endif
 chip-$(HAS_TASK_POWERLED)+=power_led.o
-ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32g4 stm32l4))
-# STM32G4 and STM32L4 use the same flash IP block
+ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32g4 stm32l4 stm32l5))
+# STM32G4, STM32L4 and STM32L5 use the same flash IP block
 chip-y+=flash-stm32g4-l4.o
 else
 chip-$(CONFIG_FLASH_PHYSICAL)+=flash-$(CHIP_FAMILY).o
@@ -75,6 +74,9 @@ chip-$(CHIP_FAMILY_STM32F3)+=flash-f.o
 chip-$(CHIP_FAMILY_STM32F4)+=flash-f.o
 endif
 chip-$(CONFIG_ADC)+=adc-$(CHIP_FAMILY).o
+chip-$(CONFIG_DFU_BOOTMANAGER_MAIN)+=dfu_bootmanager_main.o
+chip-$(CONFIG_DFU_BOOTMANAGER_SHARED)+=dfu_bootmanager_shared.o
+chip-$(CONFIG_DFU_RUNTIME)+=usb_dfu_runtime.o
 chip-$(CONFIG_STM32_CHARGER_DETECT)+=charger_detect.o
 chip-$(CONFIG_DEBUG_PRINTF)+=debug_printf.o
 chip-$(CONFIG_OTP)+=otp-$(CHIP_FAMILY).o
diff --git a/chip/stm32/charger_detect.c b/chip/stm32/charger_detect.c
index b32b9f3ac0..c404fc827a 100644
--- a/chip/stm32/charger_detect.c
+++ b/chip/stm32/charger_detect.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -33,7 +33,6 @@ static uint16_t detect_type(uint16_t det_type)
 	return STM32_USB_BCDR;
 }
 
-
 int charger_detect_get_device_type(void)
 {
 	uint16_t pdet_result;
diff --git a/chip/stm32/clock-f.c b/chip/stm32/clock-f.c
index 0be765476d..0aad58ab00 100644
--- a/chip/stm32/clock-f.c
+++ b/chip/stm32/clock-f.c
@@ -1,13 +1,14 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Clocks and power management settings */
 
+#include "builtin/assert.h"
 #include "chipset.h"
-#include "clock.h"
 #include "clock-f.h"
+#include "clock.h"
 #include "common.h"
 #include "console.h"
 #include "cpu.h"
@@ -23,7 +24,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args)
 
 /* Convert decimal to BCD */
 static uint8_t u8_to_bcd(uint8_t val)
@@ -41,8 +42,8 @@ static uint32_t rtc_tr_to_sec(uint32_t rtc_tr)
 	uint32_t sec;
 
 	/* convert the hours field */
-	sec = (((rtc_tr & 0x300000) >> 20) * 10 +
-	       ((rtc_tr & 0xf0000) >> 16)) * 3600;
+	sec = (((rtc_tr & 0x300000) >> 20) * 10 + ((rtc_tr & 0xf0000) >> 16)) *
+	      3600;
 	/* convert the minutes field */
 	sec += (((rtc_tr & 0x7000) >> 12) * 10 + ((rtc_tr & 0xf00) >> 8)) * 60;
 	/* convert the seconds field */
@@ -122,10 +123,9 @@ static uint32_t rtc_dr_to_sec(uint32_t rtc_dr)
 	struct calendar_date time;
 	uint32_t sec;
 
-	time.year = (((rtc_dr & 0xf00000) >> 20) * 10 +
-		    ((rtc_dr & 0xf0000) >> 16));
-	time.month = (((rtc_dr & 0x1000) >> 12) * 10 +
-		     ((rtc_dr & 0xf00) >> 8));
+	time.year =
+		(((rtc_dr & 0xf00000) >> 20) * 10 + ((rtc_dr & 0xf0000) >> 16));
+	time.month = (((rtc_dr & 0x1000) >> 12) * 10 + ((rtc_dr & 0xf00) >> 8));
 	time.day = ((rtc_dr & 0x30) >> 4) * 10 + (rtc_dr & 0xf);
 
 	sec = date_to_sec(time);
@@ -258,8 +258,8 @@ void set_rtc_alarm(uint32_t delay_s, uint32_t delay_us,
 	 * If the caller doesn't specify subsecond delay (e.g. host command),
 	 * just align the alarm time to second.
 	 */
-	STM32_RTC_ALRMASSR = delay_us ?
-			     (us_to_rtcss(alarm_us) | 0x0f000000) : 0;
+	STM32_RTC_ALRMASSR = delay_us ? (us_to_rtcss(alarm_us) | 0x0f000000) :
+					0;
 
 #ifdef CONFIG_HOSTCMD_RTC
 	/*
@@ -321,8 +321,7 @@ static void set_rtc_host_event(void)
 DECLARE_DEFERRED(set_rtc_host_event);
 #endif
 
-test_mockable_static
-void __rtc_alarm_irq(void)
+test_mockable void rtc_alarm_irq(void)
 {
 	struct rtc_time_reg rtc;
 	reset_rtc_alarm(&rtc);
@@ -335,10 +334,14 @@ void __rtc_alarm_irq(void)
 	}
 #endif
 }
+
+static void __rtc_alarm_irq(void)
+{
+	rtc_alarm_irq();
+}
 DECLARE_IRQ(STM32_IRQ_RTC_ALARM, __rtc_alarm_irq, 1);
 
-__attribute__((weak))
-int clock_get_timer_freq(void)
+__attribute__((weak)) int clock_get_timer_freq(void)
 {
 	return clock_get_freq();
 }
@@ -394,7 +397,7 @@ void print_system_rtc(enum console_channel ch)
 }
 
 #ifdef CONFIG_CMD_RTC
-static int command_system_rtc(int argc, char **argv)
+static int command_system_rtc(int argc, const char **argv)
 {
 	char *e;
 	uint32_t t;
@@ -411,12 +414,11 @@ static int command_system_rtc(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(rtc, command_system_rtc,
-		"[set <seconds>]",
-		"Get/set real-time clock");
+DECLARE_CONSOLE_COMMAND(rtc, command_system_rtc, "[set <seconds>]",
+			"Get/set real-time clock");
 
 #ifdef CONFIG_CMD_RTC_ALARM
-static int command_rtc_alarm_test(int argc, char **argv)
+static int command_rtc_alarm_test(int argc, const char **argv)
 {
 	int s = 1, us = 0;
 	struct rtc_time_reg rtc;
@@ -428,7 +430,6 @@ static int command_rtc_alarm_test(int argc, char **argv)
 		s = strtoi(argv[1], &e, 10);
 		if (*e)
 			return EC_ERROR_PARAM1;
-
 	}
 	if (argc > 2) {
 		us = strtoi(argv[2], &e, 10);
@@ -440,8 +441,7 @@ static int command_rtc_alarm_test(int argc, char **argv)
 	return EC_SUCCESS;
 }
 DECLARE_CONSOLE_COMMAND(rtc_alarm, command_rtc_alarm_test,
-			"[seconds [microseconds]]",
-			"Test alarm");
+			"[seconds [microseconds]]", "Test alarm");
 #endif /* CONFIG_CMD_RTC_ALARM */
 #endif /* CONFIG_CMD_RTC */
 
@@ -460,9 +460,8 @@ static enum ec_status system_rtc_get_value(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_VALUE,
-		system_rtc_get_value,
-		EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_VALUE, system_rtc_get_value,
+		     EC_VER_MASK(0));
 
 static enum ec_status system_rtc_set_value(struct host_cmd_handler_args *args)
 {
@@ -471,9 +470,8 @@ static enum ec_status system_rtc_set_value(struct host_cmd_handler_args *args)
 	rtc_set(p->time);
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_VALUE,
-		system_rtc_set_value,
-		EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_VALUE, system_rtc_set_value,
+		     EC_VER_MASK(0));
 
 static enum ec_status system_rtc_set_alarm(struct host_cmd_handler_args *args)
 {
@@ -487,9 +485,8 @@ static enum ec_status system_rtc_set_alarm(struct host_cmd_handler_args *args)
 	set_rtc_alarm(p->time, 0, &rtc, 1);
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_ALARM,
-		system_rtc_set_alarm,
-		EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_ALARM, system_rtc_set_alarm,
+		     EC_VER_MASK(0));
 
 static enum ec_status system_rtc_get_alarm(struct host_cmd_handler_args *args)
 {
@@ -500,8 +497,7 @@ static enum ec_status system_rtc_get_alarm(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_ALARM,
-		system_rtc_get_alarm,
-		EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_ALARM, system_rtc_get_alarm,
+		     EC_VER_MASK(0));
 
 #endif /* CONFIG_HOSTCMD_RTC */
diff --git a/chip/stm32/clock-f.h b/chip/stm32/clock-f.h
index 4662b043cb..5ed302bf78 100644
--- a/chip/stm32/clock-f.h
+++ b/chip/stm32/clock-f.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -100,4 +100,4 @@ int is_host_wake_alarm_expired(timestamp_t ts);
 /* Set RTC wakeup based on the value saved in host_wake_time */
 void restore_host_wake_alarm(void);
 
-#endif  /* __CROS_EC_CLOCK_F_H */
+#endif /* __CROS_EC_CLOCK_F_H */
diff --git a/chip/stm32/clock-l4.h b/chip/stm32/clock-l4.h
new file mode 100644
index 0000000000..975d952b9f
--- /dev/null
+++ b/chip/stm32/clock-l4.h
@@ -0,0 +1,110 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Clocks and power management settings */
+
+#ifndef __CROS_EC_CLOCK_L4_H
+#define __CROS_EC_CLOCK_L4_H
+
+#include "chipset.h"
+#include "clock.h"
+#include "common.h"
+#include "console.h"
+#include "cpu.h"
+#include "hooks.h"
+#include "hwtimer.h"
+#include "registers.h"
+#include "system.h"
+#include "task.h"
+#include "timer.h"
+#include "util.h"
+
+#define STM32L4_RTC_REQ 1000000
+#define STM32L4_LSI_CLOCK 32000
+
+/* Lock and unlock RTC write access */
+static inline void rtc_lock_regs(void)
+{
+	STM32_RTC_WPR = 0xff;
+}
+static inline void rtc_unlock_regs(void)
+{
+	STM32_RTC_WPR = 0xca;
+	STM32_RTC_WPR = 0x53;
+}
+
+struct rtc_time_reg {
+	uint32_t rtc_ssr; /* subseconds */
+	uint32_t rtc_tr; /* hours, minutes, seconds */
+	uint32_t rtc_dr; /* years, months, dates, week days */
+};
+
+/* Save the RTC alarm wake time */
+struct wake_time {
+	timestamp_t ts;
+	uint32_t rtc_alrmar; /* the value of register STM32_RTC_ALRMAR */
+};
+
+/* Convert between RTC regs in BCD and seconds */
+uint32_t rtc_to_sec(const struct rtc_time_reg *rtc);
+
+/* Convert between seconds and RTC regs */
+void sec_to_rtc(uint32_t sec, struct rtc_time_reg *rtc);
+
+/* Calculate microseconds from rtc sub-second register. */
+uint32_t rtcss_to_us(uint32_t rtcss);
+
+/* Calculate rtc sub-second register value from microseconds. */
+uint32_t us_to_rtcss(uint32_t us);
+
+/* Return sub-10-sec time diff between two rtc readings */
+uint32_t get_rtc_diff(const struct rtc_time_reg *rtc0,
+		      const struct rtc_time_reg *rtc1);
+
+/* Read RTC values */
+void rtc_read(struct rtc_time_reg *rtc);
+
+/* Set RTC value */
+void rtc_set(uint32_t sec);
+
+/* Set RTC wakeup, save alarm wakeup time when save_alarm != 0 */
+void set_rtc_alarm(uint32_t delay_s, uint32_t delay_us,
+		   struct rtc_time_reg *rtc, uint8_t save_alarm);
+
+/* Clear RTC wakeup */
+void reset_rtc_alarm(struct rtc_time_reg *rtc);
+
+/*
+ * Return the remaining seconds before the RTC alarm goes off.
+ * Sub-seconds are ignored. Returns 0 if alarm is not set.
+ */
+uint32_t get_rtc_alarm(void);
+
+/* RTC init */
+void rtc_init(void);
+
+/* Init clock blocks and functionality */
+void clock_init(void);
+
+/* Init high speed clock config */
+void config_hispeed_clock(void);
+
+/* Get timer clock frequency (for STM32 only) */
+int clock_get_timer_freq(void);
+
+/*
+ * Return 1 if host_wake_time is nonzero and the saved host_wake_time
+ * is expired at a given time, ts.
+ */
+bool is_host_wake_alarm_expired(timestamp_t ts);
+
+/* Set RTC wakeup based on the value saved in host_wake_time */
+void restore_host_wake_alarm(void);
+
+#ifdef CONFIG_LOW_POWER_IDLE
+void low_power_init(void);
+#endif
+
+#endif /* __CROS_EC_CLOCK_L4_H */
diff --git a/chip/stm32/clock-stm32f0.c b/chip/stm32/clock-stm32f0.c
index 8cfbaef111..64b0b45e50 100644
--- a/chip/stm32/clock-stm32f0.c
+++ b/chip/stm32/clock-stm32f0.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,8 +6,8 @@
 /* Clocks and power management settings */
 
 #include "chipset.h"
-#include "clock.h"
 #include "clock-f.h"
+#include "clock.h"
 #include "common.h"
 #include "console.h"
 #include "cpu.h"
@@ -22,7 +22,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args)
 
 /* use 48Mhz USB-synchronized High-speed oscillator */
 #define HSI48_CLOCK 48000000
@@ -54,13 +54,13 @@ static int dsleep_recovery_margin_us = 1000000;
  * we won't miss the host alarm.
  */
 #ifdef CHIP_VARIANT_STM32F373
-#define STOP_MODE_LATENCY 500  /* us */
+#define STOP_MODE_LATENCY 500 /* us */
 #elif defined(CHIP_VARIANT_STM32F05X)
-#define STOP_MODE_LATENCY 300  /* us */
+#define STOP_MODE_LATENCY 300 /* us */
 #elif (CPU_CLOCK == PLL_CLOCK)
-#define STOP_MODE_LATENCY 300   /* us */
+#define STOP_MODE_LATENCY 300 /* us */
 #else
-#define STOP_MODE_LATENCY 50    /* us */
+#define STOP_MODE_LATENCY 50 /* us */
 #endif
 #define SET_RTC_MATCH_DELAY 200 /* us */
 
@@ -137,9 +137,8 @@ void config_hispeed_clock(void)
 	while ((STM32_RCC_CFGR & 0xc) != 0x8)
 		;
 /* F03X and F05X and F070 don't have HSI48 */
-#elif defined(CHIP_VARIANT_STM32F03X) || \
-defined(CHIP_VARIANT_STM32F05X) || \
-defined(CHIP_VARIANT_STM32F070)
+#elif defined(CHIP_VARIANT_STM32F03X) || defined(CHIP_VARIANT_STM32F05X) || \
+	defined(CHIP_VARIANT_STM32F070)
 	/* If PLL is the clock source, PLL has already been set up. */
 	if ((STM32_RCC_CFGR & 0xc) == 0x8)
 		return;
@@ -259,7 +258,7 @@ void __enter_hibernate(uint32_t seconds, uint32_t microseconds)
 		set_rtc_alarm(seconds, microseconds, &rtc, 0);
 
 	/* interrupts off now */
-	asm volatile("cpsid i");
+	interrupt_disable();
 
 #ifdef CONFIG_HIBERNATE_WAKEUP_PINS
 	/* enable the wake up pins */
@@ -268,7 +267,7 @@ void __enter_hibernate(uint32_t seconds, uint32_t microseconds)
 	STM32_PWR_CR |= 0xe;
 	CPU_SCB_SYSCTRL |= 0x4;
 	/* go to Standby mode */
-	asm("wfi");
+	cpu_enter_suspend_mode();
 
 	/* we should never reach that point */
 	while (1)
@@ -298,7 +297,7 @@ void __idle(void)
 	struct rtc_time_reg rtc0, rtc1;
 
 	while (1) {
-		asm volatile("cpsid i");
+		interrupt_disable();
 
 		t0 = get_time();
 		next_delay = __hw_clock_event_get() - t0.le.lo;
@@ -319,8 +318,8 @@ void __idle(void)
 		     * EC exits deep sleep mode.
 		     */
 		    !is_host_wake_alarm_expired(
-			(timestamp_t)(next_delay + t0.val + SECOND +
-				      RESTORE_HOST_ALARM_LATENCY)) &&
+			    (timestamp_t)(next_delay + t0.val + SECOND +
+					  RESTORE_HOST_ALARM_LATENCY)) &&
 #endif
 		    (next_delay > (STOP_MODE_LATENCY + SET_RTC_MATCH_DELAY))) {
 			/* Deep-sleep in STOP mode */
@@ -331,9 +330,9 @@ void __idle(void)
 			/* Set deep sleep bit */
 			CPU_SCB_SYSCTRL |= 0x4;
 
-			set_rtc_alarm(0, next_delay - STOP_MODE_LATENCY,
-				      &rtc0, 0);
-			asm("wfi");
+			set_rtc_alarm(0, next_delay - STOP_MODE_LATENCY, &rtc0,
+				      0);
+			cpu_enter_suspend_mode();
 
 			CPU_SCB_SYSCTRL &= ~0x4;
 
@@ -371,12 +370,12 @@ void __idle(void)
 			idle_sleep_cnt++;
 
 			/* Normal idle : only CPU clock stopped */
-			asm("wfi");
+			cpu_enter_suspend_mode();
 		}
 #ifdef CONFIG_LOW_POWER_IDLE_LIMITED
-en_int:
+	en_int:
 #endif
-		asm volatile("cpsie i");
+		interrupt_enable();
 	}
 }
 #endif /* CONFIG_LOW_POWER_IDLE */
@@ -399,7 +398,7 @@ void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles)
 	}
 }
 
-void clock_enable_module(enum module_id module, int enable)
+test_mockable void clock_enable_module(enum module_id module, int enable)
 {
 	if (module == MODULE_ADC) {
 		if (enable)
@@ -407,9 +406,23 @@ void clock_enable_module(enum module_id module, int enable)
 		else
 			STM32_RCC_APB2ENR &= ~STM32_RCC_APB2ENR_ADCEN;
 		return;
+	} else if (module == MODULE_USB) {
+		if (enable)
+			STM32_RCC_APB1ENR |= STM32_RCC_PB1_USB;
+		else
+			STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_USB;
 	}
 }
 
+int clock_is_module_enabled(enum module_id module)
+{
+	if (module == MODULE_ADC)
+		return !!(STM32_RCC_APB2ENR & STM32_RCC_APB2ENR_ADCEN);
+	else if (module == MODULE_USB)
+		return !!(STM32_RCC_APB1ENR & STM32_RCC_PB1_USB);
+	return 0;
+}
+
 void rtc_init(void)
 {
 	rtc_unlock_regs();
@@ -468,22 +481,21 @@ void rtc_set(uint32_t sec)
 /**
  * Print low power idle statistics
  */
-static int command_idle_stats(int argc, char **argv)
+static int command_idle_stats(int argc, const char **argv)
 {
 	timestamp_t ts = get_time();
 
 	ccprintf("Num idle calls that sleep:           %d\n", idle_sleep_cnt);
 	ccprintf("Num idle calls that deep-sleep:      %d\n", idle_dsleep_cnt);
 	ccprintf("Time spent in deep-sleep:            %.6llds\n",
-			idle_dsleep_time_us);
+		 idle_dsleep_time_us);
 	ccprintf("Total time on:                       %.6llds\n", ts.val);
 	ccprintf("Deep-sleep closest to wake deadline: %dus\n",
-			dsleep_recovery_margin_us);
+		 dsleep_recovery_margin_us);
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats,
-			"",
+DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, "",
 			"Print last idle stats");
 #endif /* CONFIG_CMD_IDLE_STATS */
 #endif
diff --git a/chip/stm32/clock-stm32f3.c b/chip/stm32/clock-stm32f3.c
deleted file mode 120000
index be91154e52..0000000000
--- a/chip/stm32/clock-stm32f3.c
+++ /dev/null
@@ -1 +0,0 @@
-clock-stm32f0.c
\ No newline at end of file
diff --git a/chip/stm32/clock-stm32f3.c b/chip/stm32/clock-stm32f3.c
new file mode 100644
index 0000000000..0a63b27a06
--- /dev/null
+++ b/chip/stm32/clock-stm32f3.c
@@ -0,0 +1,501 @@
+/* Copyright 2014 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Clocks and power management settings */
+
+#include "chipset.h"
+#include "clock-f.h"
+#include "clock.h"
+#include "common.h"
+#include "console.h"
+#include "cpu.h"
+#include "hooks.h"
+#include "hwtimer.h"
+#include "registers.h"
+#include "system.h"
+#include "task.h"
+#include "timer.h"
+#include "uart.h"
+#include "util.h"
+
+/* Console output macros */
+#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
+#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args)
+
+/* use 48Mhz USB-synchronized High-speed oscillator */
+#define HSI48_CLOCK 48000000
+
+/* use PLL at 38.4MHz as system clock. */
+#define PLL_CLOCK 38400000
+
+/* Low power idle statistics */
+#ifdef CONFIG_LOW_POWER_IDLE
+static int idle_sleep_cnt;
+static int idle_dsleep_cnt;
+static uint64_t idle_dsleep_time_us;
+static int dsleep_recovery_margin_us = 1000000;
+
+/*
+ * minimum delay to enter stop mode
+ *
+ * STOP_MODE_LATENCY: max time to wake up from STOP mode with regulator in low
+ * power mode is 5 us + PLL locking time is 200us.
+ *
+ * SET_RTC_MATCH_DELAY: max time to set RTC match alarm. If we set the alarm
+ * in the past, it will never wake up and cause a watchdog.
+ * For STM32F3, we are using HSE, which requires additional time to start up.
+ * Therefore, the latency for STM32F3 is set longer.
+ *
+ * RESTORE_HOST_ALARM_LATENCY: max latency between the deferred routine is
+ * called and the host alarm is actually restored. In practice, the max latency
+ * is measured as ~600us. 1000us should be conservative enough to guarantee
+ * we won't miss the host alarm.
+ */
+#ifdef CHIP_VARIANT_STM32F373
+#define STOP_MODE_LATENCY 500 /* us */
+#elif defined(CHIP_VARIANT_STM32F05X)
+#define STOP_MODE_LATENCY 300 /* us */
+#elif (CPU_CLOCK == PLL_CLOCK)
+#define STOP_MODE_LATENCY 300 /* us */
+#else
+#define STOP_MODE_LATENCY 50 /* us */
+#endif
+#define SET_RTC_MATCH_DELAY 200 /* us */
+
+#ifdef CONFIG_HOSTCMD_RTC
+#define RESTORE_HOST_ALARM_LATENCY 1000 /* us */
+#endif
+
+#endif /* CONFIG_LOW_POWER_IDLE */
+
+/*
+ * RTC clock frequency (By default connected to LSI clock)
+ *
+ * The LSI on any given chip can be between 30 kHz to 60 kHz.
+ * Without calibration, LSI frequency may be off by as much as 50%.
+ *
+ * Set synchronous clock freq to (RTC clock source / 2) to maximize
+ * subsecond resolution. Set asynchronous clock to 1 Hz.
+ */
+
+#define RTC_PREDIV_A 1
+#ifdef CONFIG_STM32_CLOCK_LSE
+#define RTC_FREQ (32768 / (RTC_PREDIV_A + 1)) /* Hz */
+/* GCD(RTC_FREQ, 1000000) */
+#define RTC_GCD 64
+#else /* LSI clock, 40kHz-ish */
+#define RTC_FREQ (40000 / (RTC_PREDIV_A + 1)) /* Hz */
+/* GCD(RTC_FREQ, 1000000) */
+#define RTC_GCD 20000
+#endif
+#define RTC_PREDIV_S (RTC_FREQ - 1)
+
+/*
+ * There are (1000000 / RTC_FREQ) us per RTC tick, take GCD of both terms
+ * for conversion calculations to fit in 32 bits.
+ */
+#define US_GCD (1000000 / RTC_GCD)
+#define RTC_FREQ_GCD (RTC_FREQ / RTC_GCD)
+
+int32_t rtcss_to_us(uint32_t rtcss)
+{
+	return ((RTC_PREDIV_S - (rtcss & 0x7fff)) * US_GCD) / RTC_FREQ_GCD;
+}
+
+uint32_t us_to_rtcss(int32_t us)
+{
+	return RTC_PREDIV_S - us * RTC_FREQ_GCD / US_GCD;
+}
+
+void config_hispeed_clock(void)
+{
+#ifdef CHIP_FAMILY_STM32F3
+	/* Ensure that HSE is ON */
+	wait_for_ready(&STM32_RCC_CR, BIT(16), BIT(17));
+
+	/*
+	 * HSE = 24MHz, no prescalar, no MCO, with PLL *2 => 48MHz SYSCLK
+	 * HCLK = SYSCLK, PCLK = HCLK / 2 = 24MHz
+	 * ADCCLK = PCLK / 6 = 4MHz
+	 * USB uses SYSCLK = 48MHz
+	 */
+	STM32_RCC_CFGR = 0x0041a400;
+
+	/* Enable the PLL */
+	STM32_RCC_CR |= 0x01000000;
+
+	/* Wait until the PLL is ready */
+	while (!(STM32_RCC_CR & 0x02000000))
+		;
+
+	/* Switch SYSCLK to PLL */
+	STM32_RCC_CFGR |= 0x2;
+
+	/* Wait until the PLL is the clock source */
+	while ((STM32_RCC_CFGR & 0xc) != 0x8)
+		;
+/* F03X and F05X and F070 don't have HSI48 */
+#elif defined(CHIP_VARIANT_STM32F03X) || defined(CHIP_VARIANT_STM32F05X) || \
+	defined(CHIP_VARIANT_STM32F070)
+	/* If PLL is the clock source, PLL has already been set up. */
+	if ((STM32_RCC_CFGR & 0xc) == 0x8)
+		return;
+
+	/* Ensure that HSI is ON */
+	wait_for_ready(&STM32_RCC_CR, BIT(0), BIT(1));
+
+	/*
+	 * HSI = 8MHz, HSI/2 with PLL *12 = ~48 MHz
+	 * therefore PCLK = FCLK = SYSCLK = 48MHz
+	 */
+	/* Switch the PLL source to HSI/2 */
+	STM32_RCC_CFGR &= ~(0x00018000);
+
+	/*
+	 * Specify HSI/2 clock as input clock to PLL and set PLL (*12).
+	 */
+	STM32_RCC_CFGR |= 0x00280000;
+
+	/* Enable the PLL. */
+	STM32_RCC_CR |= 0x01000000;
+
+	/* Wait until PLL is ready. */
+	while (!(STM32_RCC_CR & 0x02000000))
+		;
+
+	/* Switch SYSCLK to PLL. */
+	STM32_RCC_CFGR |= 0x2;
+
+	/* wait until the PLL is the clock source */
+	while ((STM32_RCC_CFGR & 0xc) != 0x8)
+		;
+#else
+	/* Ensure that HSI48 is ON */
+	wait_for_ready(&STM32_RCC_CR2, BIT(16), BIT(17));
+
+#if (CPU_CLOCK == HSI48_CLOCK)
+	/*
+	 * HSI48 = 48MHz, no prescaler, no MCO, no PLL
+	 * therefore PCLK = FCLK = SYSCLK = 48MHz
+	 * USB uses HSI48 = 48MHz
+	 */
+
+#ifdef CONFIG_USB
+	/*
+	 * Configure and enable Clock Recovery System
+	 *
+	 * Since we are running from the internal RC HSI48 clock, the CSR
+	 * is needed to guarantee an accurate 48MHz clock for USB.
+	 *
+	 * The default values configure the CRS to use the periodic USB SOF
+	 * as the SYNC signal for calibrating the HSI48.
+	 *
+	 */
+
+	/* Enable Clock Recovery System */
+	STM32_RCC_APB1ENR |= STM32_RCC_PB1_CRS;
+
+	/* Enable automatic trimming */
+	STM32_CRS_CR |= STM32_CRS_CR_AUTOTRIMEN;
+
+	/* Enable oscillator clock for the frequency error counter */
+	STM32_CRS_CR |= STM32_CRS_CR_CEN;
+#endif
+
+	/* switch SYSCLK to HSI48 */
+	STM32_RCC_CFGR = 0x00000003;
+
+	/* wait until the HSI48 is the clock source */
+	while ((STM32_RCC_CFGR & 0xc) != 0xc)
+		;
+
+#elif (CPU_CLOCK == PLL_CLOCK)
+	/*
+	 * HSI48 = 48MHz, no prescalar, no MCO, with PLL *4/5 => 38.4MHz SYSCLK
+	 * therefore PCLK = FCLK = SYSCLK = 38.4MHz
+	 * USB uses HSI48 = 48MHz
+	 */
+
+	/* If PLL is the clock source, PLL has already been set up. */
+	if ((STM32_RCC_CFGR & 0xc) == 0x8)
+		return;
+
+	/*
+	 * Specify HSI48 clock as input clock to PLL and set PLL multiplier
+	 * and divider.
+	 */
+	STM32_RCC_CFGR = 0x00098000;
+	STM32_RCC_CFGR2 = 0x4;
+
+	/* Enable the PLL. */
+	STM32_RCC_CR |= 0x01000000;
+
+	/* Wait until PLL is ready. */
+	while (!(STM32_RCC_CR & 0x02000000))
+		;
+
+	/* Switch SYSCLK to PLL. */
+	STM32_RCC_CFGR |= 0x2;
+
+	/* wait until the PLL is the clock source */
+	while ((STM32_RCC_CFGR & 0xc) != 0x8)
+		;
+
+#else
+#error "CPU_CLOCK must be either 48MHz or 38.4MHz"
+#endif
+#endif
+}
+
+#ifdef CONFIG_HIBERNATE
+void __enter_hibernate(uint32_t seconds, uint32_t microseconds)
+{
+	struct rtc_time_reg rtc;
+
+	if (seconds || microseconds)
+		set_rtc_alarm(seconds, microseconds, &rtc, 0);
+
+	/* interrupts off now */
+	interrupt_disable();
+
+#ifdef CONFIG_HIBERNATE_WAKEUP_PINS
+	/* enable the wake up pins */
+	STM32_PWR_CSR |= CONFIG_HIBERNATE_WAKEUP_PINS;
+#endif
+	STM32_PWR_CR |= 0xe;
+	CPU_SCB_SYSCTRL |= 0x4;
+	/* go to Standby mode */
+	asm("wfi");
+
+	/* we should never reach that point */
+	while (1)
+		;
+}
+#endif
+
+#ifdef CONFIG_HOSTCMD_RTC
+static void restore_host_wake_alarm_deferred(void)
+{
+	restore_host_wake_alarm();
+}
+DECLARE_DEFERRED(restore_host_wake_alarm_deferred);
+#endif
+
+#ifdef CONFIG_LOW_POWER_IDLE
+
+void clock_refresh_console_in_use(void)
+{
+}
+
+void __idle(void)
+{
+	timestamp_t t0;
+	uint32_t rtc_diff;
+	int next_delay, margin_us;
+	struct rtc_time_reg rtc0, rtc1;
+
+	while (1) {
+		interrupt_disable();
+
+		t0 = get_time();
+		next_delay = __hw_clock_event_get() - t0.le.lo;
+
+#ifdef CONFIG_LOW_POWER_IDLE_LIMITED
+		if (idle_is_disabled())
+			goto en_int;
+#endif
+
+		if (DEEP_SLEEP_ALLOWED &&
+#ifdef CONFIG_HOSTCMD_RTC
+		    /*
+		     * Don't go to deep sleep mode if we might miss the
+		     * wake alarm that the host requested. Note that the
+		     * host alarm always aligns to second. Considering the
+		     * worst case, we have to ensure alarm won't go off
+		     * within RESTORE_HOST_ALARM_LATENCY + 1 second after
+		     * EC exits deep sleep mode.
+		     */
+		    !is_host_wake_alarm_expired(
+			    (timestamp_t)(next_delay + t0.val + SECOND +
+					  RESTORE_HOST_ALARM_LATENCY)) &&
+#endif
+		    (next_delay > (STOP_MODE_LATENCY + SET_RTC_MATCH_DELAY))) {
+			/* Deep-sleep in STOP mode */
+			idle_dsleep_cnt++;
+
+			uart_enable_wakeup(1);
+
+			/* Set deep sleep bit */
+			CPU_SCB_SYSCTRL |= 0x4;
+
+			set_rtc_alarm(0, next_delay - STOP_MODE_LATENCY, &rtc0,
+				      0);
+			asm("wfi");
+
+			CPU_SCB_SYSCTRL &= ~0x4;
+
+			uart_enable_wakeup(0);
+
+			/*
+			 * By default only HSI 8MHz is enabled here. Re-enable
+			 * high-speed clock if in use.
+			 */
+			config_hispeed_clock();
+
+			/* Fast forward timer according to RTC counter */
+			reset_rtc_alarm(&rtc1);
+			rtc_diff = get_rtc_diff(&rtc0, &rtc1);
+			t0.val = t0.val + rtc_diff;
+			force_time(t0);
+
+#ifdef CONFIG_HOSTCMD_RTC
+			hook_call_deferred(
+				&restore_host_wake_alarm_deferred_data, 0);
+#endif
+			/* Record time spent in deep sleep. */
+			idle_dsleep_time_us += rtc_diff;
+
+			/* Calculate how close we were to missing deadline */
+			margin_us = next_delay - rtc_diff;
+			if (margin_us < 0)
+				/* Use CPUTS to save stack space */
+				CPUTS("Idle overslept!\n");
+
+			/* Record the closest to missing a deadline. */
+			if (margin_us < dsleep_recovery_margin_us)
+				dsleep_recovery_margin_us = margin_us;
+		} else {
+			idle_sleep_cnt++;
+
+			/* Normal idle : only CPU clock stopped */
+			asm("wfi");
+		}
+#ifdef CONFIG_LOW_POWER_IDLE_LIMITED
+	en_int:
+#endif
+		interrupt_enable();
+	}
+}
+#endif /* CONFIG_LOW_POWER_IDLE */
+
+int clock_get_freq(void)
+{
+	return CPU_CLOCK;
+}
+
+void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles)
+{
+	volatile uint32_t unused __attribute__((unused));
+
+	if (bus == BUS_AHB) {
+		while (cycles--)
+			unused = STM32_DMA1_REGS->isr;
+	} else { /* APB */
+		while (cycles--)
+			unused = STM32_USART_BRR(STM32_USART1_BASE);
+	}
+}
+
+test_mockable void clock_enable_module(enum module_id module, int enable)
+{
+	if (module == MODULE_ADC) {
+		if (enable)
+			STM32_RCC_APB2ENR |= STM32_RCC_APB2ENR_ADCEN;
+		else
+			STM32_RCC_APB2ENR &= ~STM32_RCC_APB2ENR_ADCEN;
+		return;
+	} else if (module == MODULE_USB) {
+		if (enable)
+			STM32_RCC_APB1ENR |= STM32_RCC_PB1_USB;
+		else
+			STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_USB;
+	}
+}
+
+int clock_is_module_enabled(enum module_id module)
+{
+	if (module == MODULE_ADC)
+		return !!(STM32_RCC_APB2ENR & STM32_RCC_APB2ENR_ADCEN);
+	else if (module == MODULE_USB)
+		return !!(STM32_RCC_APB1ENR & STM32_RCC_PB1_USB);
+	return 0;
+}
+
+void rtc_init(void)
+{
+	rtc_unlock_regs();
+
+	/* Enter RTC initialize mode */
+	STM32_RTC_ISR |= STM32_RTC_ISR_INIT;
+	while (!(STM32_RTC_ISR & STM32_RTC_ISR_INITF))
+		;
+
+	/* Set clock prescalars */
+	STM32_RTC_PRER = (RTC_PREDIV_A << 16) | RTC_PREDIV_S;
+
+	/* Start RTC timer */
+	STM32_RTC_ISR &= ~STM32_RTC_ISR_INIT;
+	while (STM32_RTC_ISR & STM32_RTC_ISR_INITF)
+		;
+
+	/* Enable RTC alarm interrupt */
+	STM32_RTC_CR |= STM32_RTC_CR_ALRAIE | STM32_RTC_CR_BYPSHAD;
+	STM32_EXTI_RTSR |= EXTI_RTC_ALR_EVENT;
+	task_enable_irq(STM32_IRQ_RTC_ALARM);
+
+	rtc_lock_regs();
+}
+
+#if defined(CONFIG_CMD_RTC) || defined(CONFIG_HOSTCMD_RTC)
+void rtc_set(uint32_t sec)
+{
+	struct rtc_time_reg rtc;
+
+	sec_to_rtc(sec, &rtc);
+	rtc_unlock_regs();
+
+	/* Disable alarm */
+	STM32_RTC_CR &= ~STM32_RTC_CR_ALRAE;
+
+	/* Enter RTC initialize mode */
+	STM32_RTC_ISR |= STM32_RTC_ISR_INIT;
+	while (!(STM32_RTC_ISR & STM32_RTC_ISR_INITF))
+		;
+
+	/* Set clock prescalars */
+	STM32_RTC_PRER = (RTC_PREDIV_A << 16) | RTC_PREDIV_S;
+
+	STM32_RTC_TR = rtc.rtc_tr;
+	STM32_RTC_DR = rtc.rtc_dr;
+	/* Start RTC timer */
+	STM32_RTC_ISR &= ~STM32_RTC_ISR_INIT;
+
+	rtc_lock_regs();
+}
+#endif
+
+#if defined(CONFIG_LOW_POWER_IDLE) && defined(CONFIG_COMMON_RUNTIME)
+#ifdef CONFIG_CMD_IDLE_STATS
+/**
+ * Print low power idle statistics
+ */
+static int command_idle_stats(int argc, const char **argv)
+{
+	timestamp_t ts = get_time();
+
+	ccprintf("Num idle calls that sleep:           %d\n", idle_sleep_cnt);
+	ccprintf("Num idle calls that deep-sleep:      %d\n", idle_dsleep_cnt);
+	ccprintf("Time spent in deep-sleep:            %.6llds\n",
+		 idle_dsleep_time_us);
+	ccprintf("Total time on:                       %.6llds\n", ts.val);
+	ccprintf("Deep-sleep closest to wake deadline: %dus\n",
+		 dsleep_recovery_margin_us);
+
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, "",
+			"Print last idle stats");
+#endif /* CONFIG_CMD_IDLE_STATS */
+#endif
diff --git a/chip/stm32/clock-stm32f4.c b/chip/stm32/clock-stm32f4.c
index 7b83b8507e..c64afdd278 100644
--- a/chip/stm32/clock-stm32f4.c
+++ b/chip/stm32/clock-stm32f4.c
@@ -1,13 +1,14 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Clocks and power management settings */
 
+#include "builtin/assert.h"
 #include "chipset.h"
-#include "clock.h"
 #include "clock-f.h"
+#include "clock.h"
 #include "common.h"
 #include "console.h"
 #include "cpu.h"
@@ -21,39 +22,209 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args)
+
+enum clock_osc {
+	OSC_HSI = 0, /* High-speed internal oscillator */
+	OSC_HSE, /* High-speed external oscillator */
+	OSC_PLL, /* PLL */
+};
+
+/*
+ * NOTE: Sweetberry requires MCO2 <- HSE @ 24MHz
+ * MCO outputs are selected here but are not changeable later.
+ * A CONFIG may be needed if other boards have different MCO
+ * requirements.
+ */
+#define RCC_CFGR_MCO_CONFIG             \
+	((2 << 30) | /* MCO2 <- HSE  */ \
+	 (0 << 27) | /* MCO2 div / 4 */ \
+	 (6 << 24) | /* MCO1 div / 4 */ \
+	 (3 << 21)) /* MCO1 <- PLL  */
 
 #ifdef CONFIG_STM32_CLOCK_HSE_HZ
-#define RTC_PREDIV_A 39
-#define RTC_FREQ ((STM32F4_RTC_REQ) / (RTC_PREDIV_A + 1)) /* Hz */
-#else
-/* LSI clock is 40kHz-ish */
-#define RTC_PREDIV_A 1
-#define RTC_FREQ (40000 / (RTC_PREDIV_A + 1)) /* Hz */
-#endif
-#define RTC_PREDIV_S (RTC_FREQ - 1)
-#define US_PER_RTC_TICK (1000000 / RTC_FREQ)
+/* RTC clock must 1 Mhz when derived from HSE */
+#define RTC_DIV DIV_ROUND_NEAREST(CONFIG_STM32_CLOCK_HSE_HZ, STM32F4_RTC_REQ)
+#else /* !CONFIG_STM32_CLOCK_HSE_HZ */
+/* RTC clock not derived from HSE, turn it off */
+#define RTC_DIV 0
+#endif /* CONFIG_STM32_CLOCK_HSE_HZ */
+
+/* Bus clocks dividers depending on the configuration */
+/*
+ * max speed configuration with the PLL ON
+ * as defined in the registers file.
+ * For STM32F446: max 45 MHz
+ * For STM32F412: max AHB 100 MHz / APB2 100 Mhz / APB1 50 Mhz
+ */
+#define RCC_CFGR_DIVIDERS_WITH_PLL                                     \
+	(RCC_CFGR_MCO_CONFIG | CFGR_RTCPRE(RTC_DIV) |                  \
+	 CFGR_PPRE2(STM32F4_APB2_PRE) | CFGR_PPRE1(STM32F4_APB1_PRE) | \
+	 CFGR_HPRE(STM32F4_AHB_PRE))
+/*
+ * lower power configuration without the PLL
+ * the frequency will be low (8-24Mhz), we don't want dividers to the
+ * peripheral clocks, put /1 everywhere.
+ */
+#define RCC_CFGR_DIVIDERS_NO_PLL                                \
+	(RCC_CFGR_MCO_CONFIG | CFGR_RTCPRE(0) | CFGR_PPRE2(0) | \
+	 CFGR_PPRE1(0) | CFGR_HPRE(0))
 
-int32_t rtcss_to_us(uint32_t rtcss)
+/* PLL output frequency */
+#define STM32F4_PLL_CLOCK (STM32F4_VCO_CLOCK / STM32F4_PLLP_DIV)
+
+/* current clock settings (PLL is initialized at startup) */
+static int current_osc = OSC_PLL;
+static int current_io_freq = STM32F4_IO_CLOCK;
+static int current_timer_freq = STM32F4_TIMER_CLOCK;
+
+/* the EC code expects to get the USART/I2C clock frequency here (APB clock) */
+int clock_get_freq(void)
 {
-	return ((RTC_PREDIV_S - rtcss) * US_PER_RTC_TICK);
+	return current_io_freq;
 }
 
-uint32_t us_to_rtcss(int32_t us)
+int clock_get_timer_freq(void)
 {
-	return (RTC_PREDIV_S - (us / US_PER_RTC_TICK));
+	return current_timer_freq;
 }
 
-void config_hispeed_clock(void)
+static void clock_enable_osc(enum clock_osc osc, bool enabled)
+{
+	uint32_t ready;
+	uint32_t on;
+
+	switch (osc) {
+	case OSC_HSI:
+		ready = STM32_RCC_CR_HSIRDY;
+		on = STM32_RCC_CR_HSION;
+		break;
+	case OSC_HSE:
+		ready = STM32_RCC_CR_HSERDY;
+		on = STM32_RCC_CR_HSEON;
+		break;
+	case OSC_PLL:
+		ready = STM32_RCC_CR_PLLRDY;
+		on = STM32_RCC_CR_PLLON;
+		break;
+	default:
+		ASSERT(0);
+		return;
+	}
+
+	/* Turn off the oscillator, but don't wait for shutdown */
+	if (!enabled) {
+		STM32_RCC_CR &= ~on;
+		return;
+	}
+
+	/* Turn on the oscillator if not already on */
+	wait_for_ready(&STM32_RCC_CR, on, ready);
+}
+
+static void clock_switch_osc(enum clock_osc osc)
+{
+	uint32_t sw;
+	uint32_t sws;
+
+	switch (osc) {
+	case OSC_HSI:
+		sw = STM32_RCC_CFGR_SW_HSI | RCC_CFGR_DIVIDERS_NO_PLL;
+		sws = STM32_RCC_CFGR_SWS_HSI;
+		break;
+	case OSC_HSE:
+		sw = STM32_RCC_CFGR_SW_HSE | RCC_CFGR_DIVIDERS_NO_PLL;
+		sws = STM32_RCC_CFGR_SWS_HSE;
+		break;
+	case OSC_PLL:
+		sw = STM32_RCC_CFGR_SW_PLL | RCC_CFGR_DIVIDERS_WITH_PLL;
+		sws = STM32_RCC_CFGR_SWS_PLL;
+		break;
+	default:
+		return;
+	}
+
+	STM32_RCC_CFGR = sw;
+	while ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MASK) != sws)
+		;
+}
+
+void clock_set_osc(enum clock_osc osc)
+{
+	volatile uint32_t unused __attribute__((unused));
+
+	if (osc == current_osc)
+		return;
+
+	hook_notify(HOOK_PRE_FREQ_CHANGE);
+
+	switch (osc) {
+	default:
+	case OSC_HSI:
+		/* new clock settings: no dividers */
+		current_io_freq = STM32F4_HSI_CLOCK;
+		current_timer_freq = STM32F4_HSI_CLOCK;
+		/* Switch to HSI */
+		clock_switch_osc(OSC_HSI);
+		/* optimized flash latency settings for <30Mhz clock (0-WS) */
+		STM32_FLASH_ACR =
+			(STM32_FLASH_ACR & ~STM32_FLASH_ACR_LAT_MASK) |
+			STM32_FLASH_ACR_LATENCY_SLOW;
+		/* read-back the latency as advised by the Reference Manual */
+		unused = STM32_FLASH_ACR;
+		/* Turn off the PLL1 to save power */
+		clock_enable_osc(OSC_PLL, false);
+		break;
+
+#ifdef CONFIG_STM32_CLOCK_HSE_HZ
+	case OSC_HSE:
+		/* new clock settings: no dividers */
+		current_io_freq = CONFIG_STM32_CLOCK_HSE_HZ;
+		current_timer_freq = CONFIG_STM32_CLOCK_HSE_HZ;
+		/* Switch to HSE */
+		clock_switch_osc(OSC_HSE);
+		/* optimized flash latency settings for <30Mhz clock (0-WS) */
+		STM32_FLASH_ACR =
+			(STM32_FLASH_ACR & ~STM32_FLASH_ACR_LAT_MASK) |
+			STM32_FLASH_ACR_LATENCY_SLOW;
+		/* read-back the latency as advised by the Reference Manual */
+		unused = STM32_FLASH_ACR;
+		/* Turn off the PLL1 to save power */
+		clock_enable_osc(OSC_PLL, false);
+		break;
+#endif /* CONFIG_STM32_CLOCK_HSE_HZ */
+
+	case OSC_PLL:
+		/* new clock settings */
+		current_io_freq = STM32F4_IO_CLOCK;
+		current_timer_freq = STM32F4_TIMER_CLOCK;
+		/* turn on PLL and wait until it's ready */
+		clock_enable_osc(OSC_PLL, true);
+		/*
+		 * Increase flash latency before transition the clock
+		 * Use the minimum Wait States value optimized for the platform.
+		 */
+		STM32_FLASH_ACR =
+			(STM32_FLASH_ACR & ~STM32_FLASH_ACR_LAT_MASK) |
+			STM32_FLASH_ACR_LATENCY;
+		/* read-back the latency as advised by the Reference Manual */
+		unused = STM32_FLASH_ACR;
+		/* Switch to PLL */
+		clock_switch_osc(OSC_PLL);
+
+		break;
+	}
+
+	current_osc = osc;
+	hook_notify(HOOK_FREQ_CHANGE);
+}
+
+static void clock_pll_configure(void)
 {
 #ifdef CONFIG_STM32_CLOCK_HSE_HZ
 	int srcclock = CONFIG_STM32_CLOCK_HSE_HZ;
-	int clk_check_mask = STM32_RCC_CR_HSERDY;
-	int clk_enable_mask = STM32_RCC_CR_HSEON;
 #else
 	int srcclock = STM32F4_HSI_CLOCK;
-	int clk_check_mask = STM32_RCC_CR_HSIRDY;
-	int clk_enable_mask = STM32_RCC_CR_HSION;
 #endif
 	int plldiv, pllinputclock;
 	int pllmult, vcoclock;
@@ -61,17 +232,6 @@ void config_hispeed_clock(void)
 	int usbdiv;
 	int i2sdiv;
 
-	int ahbpre, apb1pre, apb2pre;
-	int rtcdiv = 0;
-
-	/* If PLL is the clock source, PLL has already been set up. */
-	if ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MASK) ==
-	    STM32_RCC_CFGR_SWS_PLL)
-		return;
-
-	/* Ensure that HSE/HSI is ON */
-	wait_for_ready(&(STM32_RCC_CR), clk_enable_mask, clk_check_mask);
-
 	/* PLL input must be between 1-2MHz, near 2 */
 	/* Valid values 2-63 */
 	plldiv = (srcclock + STM32F4_PLL_REQ - 1) / STM32F4_PLL_REQ;
@@ -90,86 +250,36 @@ void config_hispeed_clock(void)
 	/* SYSTEM/I2S: same system clock */
 	i2sdiv = (vcoclock + (systemclock / 2)) / systemclock;
 
-	/* All IO clocks at STM32F4_IO_CLOCK
-	 * For STM32F446: max 45 MHz
-	 * For STM32F412: max 50 MHz
-	 */
-	/* AHB Prescalar */
-	ahbpre = STM32F4_AHB_PRE;
-	/* NOTE: If apbXpre is not 0, timers are x2 clocked. RM0390 Fig. 13
-	 * One should define STM32F4_TIMER_CLOCK when apbXpre is not 0.
-	 * STM32F4_TIMER_CLOCK is used for hwtimer in EC. */
-	apb1pre = STM32F4_APB1_PRE;
-	apb2pre = STM32F4_APB2_PRE;
-
-#ifdef CONFIG_STM32_CLOCK_HSE_HZ
-	/* RTC clock = 1MHz */
-	rtcdiv = (CONFIG_STM32_CLOCK_HSE_HZ + (STM32F4_RTC_REQ / 2))
-		/ STM32F4_RTC_REQ;
-#endif
-	/* Switch SYSCLK to PLL, setup prescalars.
-	 * EC codebase doesn't understand multiple clock domains
-	 * so we enforce a clock config that keeps AHB = APB1 = APB2
-	 * allowing ec codebase assumptions about consistent clock
-	 * rates to remain true.
-	 *
-	 * NOTE: Sweetberry requires MCO2 <- HSE @ 24MHz
-	 * MCO outputs are selected here but are not changeable later.
-	 * A CONFIG may be needed if other boards have different MCO
-	 * requirements.
-	 */
-	STM32_RCC_CFGR =
-		(2 << 30) |  /* MCO2 <- HSE */
-		(0 << 27) |  /* MCO2 div / 4 */
-		(6 << 24) |  /* MCO1 div / 4 */
-		(3 << 21) |  /* MCO1 <- PLL */
-		CFGR_RTCPRE(rtcdiv) |
-		CFGR_PPRE2(apb2pre) |
-		CFGR_PPRE1(apb1pre) |
-		CFGR_HPRE(ahbpre) |
-		STM32_RCC_CFGR_SW_PLL;
-
 	/* Set up PLL */
-	STM32_RCC_PLLCFGR =
-		PLLCFGR_PLLM(plldiv) |
-		PLLCFGR_PLLN(pllmult) |
-		PLLCFGR_PLLP(STM32F4_PLLP_DIV / 2 - 1) |
+	STM32_RCC_PLLCFGR = PLLCFGR_PLLM(plldiv) | PLLCFGR_PLLN(pllmult) |
+			    PLLCFGR_PLLP(STM32F4_PLLP_DIV / 2 - 1) |
 #if defined(CONFIG_STM32_CLOCK_HSE_HZ)
-		PLLCFGR_PLLSRC_HSE |
+			    PLLCFGR_PLLSRC_HSE |
 #else
-		PLLCFGR_PLLSRC_HSI |
+			    PLLCFGR_PLLSRC_HSI |
 #endif
-		PLLCFGR_PLLQ(usbdiv) |
-		PLLCFGR_PLLR(i2sdiv);
-
-	wait_for_ready(&(STM32_RCC_CR),
-		STM32_RCC_CR_PLLON, STM32_RCC_CR_PLLRDY);
+			    PLLCFGR_PLLQ(usbdiv) | PLLCFGR_PLLR(i2sdiv);
+}
 
-	/* Wait until the PLL is the clock source */
-	if ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MASK) ==
-	    STM32_RCC_CFGR_SWS_PLL)
-		;
+void low_power_init(void);
 
-	/* Setup RTC Clock input */
+void config_hispeed_clock(void)
+{
 #ifdef CONFIG_STM32_CLOCK_HSE_HZ
-	STM32_RCC_BDCR = STM32_RCC_BDCR_RTCEN | BDCR_RTCSEL(BDCR_SRC_HSE);
-#else
-	/* Ensure that LSI is ON */
-	wait_for_ready(&(STM32_RCC_CSR),
-		STM32_RCC_CSR_LSION, STM32_RCC_CSR_LSIRDY);
-
-	STM32_RCC_BDCR = STM32_RCC_BDCR_RTCEN | BDCR_RTCSEL(BDCR_SRC_LSI);
+	/* Ensure that HSE is ON */
+	clock_enable_osc(OSC_HSE, true);
 #endif
-}
 
-int clock_get_timer_freq(void)
-{
-	return STM32F4_TIMER_CLOCK;
-}
+	/* Put the PLL settings, they are never changing */
+	clock_pll_configure();
+	clock_enable_osc(OSC_PLL, true);
 
-int clock_get_freq(void)
-{
-	return STM32F4_IO_CLOCK;
+	/* Switch SYSCLK to PLL, setup bus prescalers. */
+	clock_switch_osc(OSC_PLL);
+
+#ifdef CONFIG_LOW_POWER_IDLE
+	low_power_init();
+#endif
 }
 
 void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles)
@@ -185,28 +295,29 @@ void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles)
 	}
 }
 
-void clock_enable_module(enum module_id module, int enable)
+test_mockable void clock_enable_module(enum module_id module, int enable)
 {
 	if (module == MODULE_USB) {
 		if (enable) {
 			STM32_RCC_AHB2ENR |= STM32_RCC_AHB2ENR_OTGFSEN;
 			STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_OTGHSEN |
-				STM32_RCC_AHB1ENR_OTGHSULPIEN;
+					     STM32_RCC_AHB1ENR_OTGHSULPIEN;
 		} else {
 			STM32_RCC_AHB2ENR &= ~STM32_RCC_AHB2ENR_OTGFSEN;
 			STM32_RCC_AHB1ENR &= ~STM32_RCC_AHB1ENR_OTGHSEN &
-				     ~STM32_RCC_AHB1ENR_OTGHSULPIEN;
+					     ~STM32_RCC_AHB1ENR_OTGHSULPIEN;
 		}
 		return;
 	} else if (module == MODULE_I2C) {
 		if (enable) {
 			/* Enable clocks to I2C modules if necessary */
 			STM32_RCC_APB1ENR |=
-				STM32_RCC_I2C1EN | STM32_RCC_I2C2EN
-				| STM32_RCC_I2C3EN | STM32_RCC_FMPI2C4EN;
+				STM32_RCC_I2C1EN | STM32_RCC_I2C2EN |
+				STM32_RCC_I2C3EN | STM32_RCC_FMPI2C4EN;
 			STM32_RCC_DCKCFGR2 =
-				(STM32_RCC_DCKCFGR2 & ~DCKCFGR2_FMPI2C1SEL_MASK)
-				| DCKCFGR2_FMPI2C1SEL(FMPI2C1SEL_APB);
+				(STM32_RCC_DCKCFGR2 &
+				 ~DCKCFGR2_FMPI2C1SEL_MASK) |
+				DCKCFGR2_FMPI2C1SEL(FMPI2C1SEL_APB);
 		} else {
 			STM32_RCC_APB1ENR &=
 				~(STM32_RCC_I2C1EN | STM32_RCC_I2C2EN |
@@ -222,8 +333,48 @@ void clock_enable_module(enum module_id module, int enable)
 	}
 }
 
+/* Real Time Clock (RTC) */
+
+#ifdef CONFIG_STM32_CLOCK_HSE_HZ
+#define RTC_PREDIV_A 39
+#define RTC_FREQ ((STM32F4_RTC_REQ) / (RTC_PREDIV_A + 1)) /* Hz */
+#else /* from LSI clock */
+#define RTC_PREDIV_A 1
+#define RTC_FREQ (STM32F4_LSI_CLOCK / (RTC_PREDIV_A + 1)) /* Hz */
+#endif
+#define RTC_PREDIV_S (RTC_FREQ - 1)
+/*
+ * Scaling factor to ensure that the intermediate values computed from/to the
+ * RTC frequency are fitting in a 32-bit integer.
+ */
+#define SCALING 1000
+
+int32_t rtcss_to_us(uint32_t rtcss)
+{
+	return ((RTC_PREDIV_S - rtcss) * (SECOND / SCALING) /
+		(RTC_FREQ / SCALING));
+}
+
+uint32_t us_to_rtcss(int32_t us)
+{
+	return (RTC_PREDIV_S -
+		(us * (RTC_FREQ / SCALING) / (SECOND / SCALING)));
+}
+
 void rtc_init(void)
 {
+	/* Setup RTC Clock input */
+#ifdef CONFIG_STM32_CLOCK_HSE_HZ
+	/* RTC clocked from the HSE */
+	STM32_RCC_BDCR = STM32_RCC_BDCR_RTCEN | BDCR_RTCSEL(BDCR_SRC_HSE);
+#else
+	/* RTC clocked from the LSI, ensure first it is ON */
+	wait_for_ready(&(STM32_RCC_CSR), STM32_RCC_CSR_LSION,
+		       STM32_RCC_CSR_LSIRDY);
+
+	STM32_RCC_BDCR = STM32_RCC_BDCR_RTCEN | BDCR_RTCSEL(BDCR_SRC_LSI);
+#endif
+
 	rtc_unlock_regs();
 
 	/* Enter RTC initialize mode */
@@ -232,11 +383,10 @@ void rtc_init(void)
 		;
 
 	/* Set clock prescalars: Needs two separate writes. */
-	STM32_RTC_PRER =
-		(STM32_RTC_PRER & ~STM32_RTC_PRER_S_MASK) | RTC_PREDIV_S;
-	STM32_RTC_PRER =
-		(STM32_RTC_PRER & ~STM32_RTC_PRER_A_MASK)
-		| (RTC_PREDIV_A << 16);
+	STM32_RTC_PRER = (STM32_RTC_PRER & ~STM32_RTC_PRER_S_MASK) |
+			 RTC_PREDIV_S;
+	STM32_RTC_PRER = (STM32_RTC_PRER & ~STM32_RTC_PRER_A_MASK) |
+			 (RTC_PREDIV_A << 16);
 
 	/* Start RTC timer */
 	STM32_RTC_ISR &= ~STM32_RTC_ISR_INIT;
@@ -278,3 +428,178 @@ void rtc_set(uint32_t sec)
 	rtc_lock_regs();
 }
 #endif
+
+#ifdef CONFIG_LOW_POWER_IDLE
+/* Low power idle statistics */
+static int idle_sleep_cnt;
+static int idle_dsleep_cnt;
+static uint64_t idle_dsleep_time_us;
+static int idle_sleep_prevented_cnt;
+static int dsleep_recovery_margin_us = 1000000;
+
+/* STOP_MODE_LATENCY: delay to wake up from STOP mode with main regulator off */
+#define STOP_MODE_LATENCY 50 /* us */
+/* PLL_LOCK_LATENCY: delay to switch from HSI to PLL */
+#define PLL_LOCK_LATENCY 150 /* us */
+
+void low_power_init(void)
+{
+	/* Turn off the main regulator during stop mode */
+	STM32_PWR_CR |= STM32_PWR_CR_LPSDSR /* aka LPDS */;
+}
+
+void clock_refresh_console_in_use(void)
+{
+}
+
+static bool timer_interrupt_pending(void)
+{
+	return task_is_irq_pending(IRQ_TIM(TIM_CLOCK32));
+}
+
+void __idle(void)
+{
+	timestamp_t t0;
+	uint32_t rtc_diff;
+	int next_delay, margin_us;
+	struct rtc_time_reg rtc0, rtc1, rtc_sleep;
+
+	while (1) {
+		interrupt_disable();
+
+		/*
+		 * Get timestamp with interrupts disabled.
+		 * This value is used as a base to calculate timestamp after
+		 * wake from deep sleep. In combination with next_delay it gives
+		 * information how long the CPU can sleep. The timestamp can
+		 * point to the previous "epoch" when timer overflowed after
+		 * interrupts were disabled, since clksrc_high (which keeps
+		 * higher 32 bits of the timestamp) will not be updated.
+		 */
+		rtc_read(&rtc0);
+		t0 = get_time();
+
+		/*
+		 * Get time to next event.
+		 * After disabling interrupts, event timestamp
+		 * (__hw_clock_event_get()) is frozen, because
+		 * process_timers(), responsible for updating the
+		 * next event value with __hw_clock_event_set(),
+		 * can't be called. There is a risk that timer overflow
+		 * occurred after interrupts were disabled and obtained
+		 * event timestamp points to previous "epoch". We will
+		 * check that later.
+		 */
+		next_delay = __hw_clock_event_get() - t0.le.lo;
+
+		/*
+		 * Repeat idle enter procedure when timer interrupt is pending
+		 * (eg. overflow occurred after disabling interrupts). To work
+		 * properly, this code assumes that timer interrupt is enabled
+		 * in NVIC and interrupt is generated on timer overflow.
+		 */
+		if (timer_interrupt_pending()) {
+			idle_sleep_prevented_cnt++;
+
+			/* Enable interrupts to handle detected overflow. */
+			interrupt_enable();
+
+			/* Repeat idle enter procedure. */
+			continue;
+		}
+
+		if (DEEP_SLEEP_ALLOWED &&
+		    (next_delay > (STOP_MODE_LATENCY + PLL_LOCK_LATENCY +
+				   SET_RTC_MATCH_DELAY))) {
+			/*
+			 * Sleep time MUST be smaller than watchdog period.
+			 * Otherwise watchdog will wake us from deep sleep
+			 * which is not what we want. Please note that this
+			 * assert won't fire if we are already part way through
+			 * the watchdog period.
+			 */
+			ASSERT(next_delay < CONFIG_WATCHDOG_PERIOD_MS * MSEC);
+
+			/* Deep-sleep in STOP mode */
+			idle_dsleep_cnt++;
+
+			/*
+			 * TODO(b/174337385) no support for wake-up on USART
+			 * uart_enable_wakeup(1);
+			 */
+
+			/* Set deep sleep bit */
+			CPU_SCB_SYSCTRL |= 0x4;
+
+			set_rtc_alarm(0,
+				      next_delay - STOP_MODE_LATENCY -
+					      PLL_LOCK_LATENCY,
+				      &rtc_sleep, 0);
+
+			/* Switch to HSI */
+			clock_switch_osc(OSC_HSI);
+			/* Turn off the PLL1 to save power */
+			clock_enable_osc(OSC_PLL, false);
+
+			/* ensure outstanding memory transactions complete */
+			asm volatile("dsb");
+
+			cpu_enter_suspend_mode();
+
+			CPU_SCB_SYSCTRL &= ~0x4;
+
+			/* turn on PLL and wait until it's ready */
+			clock_enable_osc(OSC_PLL, true);
+			/* Switch to PLL */
+			clock_switch_osc(OSC_PLL);
+
+			/*uart_enable_wakeup(0);*/
+
+			/* Fast forward timer according to RTC counter */
+			reset_rtc_alarm(&rtc1);
+			rtc_diff = get_rtc_diff(&rtc0, &rtc1);
+			t0.val = t0.val + rtc_diff;
+			force_time(t0);
+
+			/* Record time spent in deep sleep. */
+			idle_dsleep_time_us += get_rtc_diff(&rtc_sleep, &rtc1);
+
+			/* Calculate how close we were to missing deadline */
+			margin_us = next_delay - rtc_diff;
+			if (margin_us < 0)
+				/* Use CPUTS to save stack space */
+				CPUTS("Idle overslept!\n");
+
+			/* Record the closest to missing a deadline. */
+			if (margin_us < dsleep_recovery_margin_us)
+				dsleep_recovery_margin_us = margin_us;
+		} else {
+			idle_sleep_cnt++;
+
+			/* Normal idle : only CPU clock stopped */
+			cpu_enter_suspend_mode();
+		}
+		interrupt_enable();
+	}
+}
+
+/* Print low power idle statistics. */
+static int command_idle_stats(int argc, const char **argv)
+{
+	timestamp_t ts = get_time();
+
+	ccprintf("Num idle calls that sleep:           %d\n", idle_sleep_cnt);
+	ccprintf("Num idle calls that deep-sleep:      %d\n", idle_dsleep_cnt);
+	ccprintf("Time spent in deep-sleep:            %.6llds\n",
+		 idle_dsleep_time_us);
+	ccprintf("Num of prevented sleep:              %d\n",
+		 idle_sleep_prevented_cnt);
+	ccprintf("Total time on:                       %.6llds\n", ts.val);
+	ccprintf("Deep-sleep closest to wake deadline: %dus\n",
+		 dsleep_recovery_margin_us);
+
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, "",
+			"Print last idle stats");
+#endif /* CONFIG_LOW_POWER_IDLE */
diff --git a/chip/stm32/clock-stm32g4.c b/chip/stm32/clock-stm32g4.c
index 941cb94327..6b186e9c09 100644
--- a/chip/stm32/clock-stm32g4.c
+++ b/chip/stm32/clock-stm32g4.c
@@ -1,13 +1,14 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Clocks configuration routines */
 
+#include "builtin/assert.h"
 #include "chipset.h"
-#include "clock.h"
 #include "clock-f.h"
+#include "clock.h"
 #include "common.h"
 #include "console.h"
 #include "cpu.h"
@@ -21,14 +22,14 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args)
 
-#define MHZ(x) ((x) * 1000000)
-#define WAIT_STATE_FREQ_STEP_HZ	MHZ(20)
+#define MHZ(x) ((x)*1000000)
+#define WAIT_STATE_FREQ_STEP_HZ MHZ(20)
 /* PLL configuration constants */
-#define STM32G4_SYSCLK_MAX_HZ		MHZ(170)
-#define STM32G4_HSI_CLK_HZ		MHZ(16)
-#define STM32G4_PLL_IN_FREQ_HZ		MHZ(4)
+#define STM32G4_SYSCLK_MAX_HZ MHZ(170)
+#define STM32G4_HSI_CLK_HZ MHZ(16)
+#define STM32G4_PLL_IN_FREQ_HZ MHZ(4)
 #define STM32G4_PLL_R 2
 #define STM32G4_AHB_PRE 1
 #define STM32G4_APB1_PRE 1
@@ -42,7 +43,7 @@ enum rcc_clksrc {
 };
 
 static void stm32g4_config_pll(uint32_t hclk_hz, uint32_t pll_src,
-			      uint32_t pll_clk_in_hz)
+			       uint32_t pll_clk_in_hz)
 {
 	/*
 	 * The pll output frequency (Fhclkc) is determined by:
@@ -81,20 +82,16 @@ static void stm32g4_config_pll(uint32_t hclk_hz, uint32_t pll_src,
 	ASSERT(pll_m && (pll_m <= 16));
 	ASSERT((pll_n >= 8) && (pll_n <= 127));
 
-	hclk_freq = pll_clk_in_hz * pll_n / (pll_m *
-					      STM32G4_PLL_R * STM32G4_AHB_PRE);
+	hclk_freq = pll_clk_in_hz * pll_n /
+		    (pll_m * STM32G4_PLL_R * STM32G4_AHB_PRE);
 	/* Ensure that there aren't any integer rounding errors */
 	ASSERT(hclk_freq == hclk_hz);
 
 	/* Program PLL config register */
-	STM32_RCC_PLLCFGR = PLLCFGR_PLLP(0) |
-		PLLCFGR_PLLR(STM32G4_PLL_R / 2 - 1) |
-		PLLCFGR_PLLR_EN |
-		PLLCFGR_PLLQ(0) |
-		PLLCFGR_PLLQ_EN |
-		PLLCFGR_PLLN(pll_n) |
-		PLLCFGR_PLLM(pll_m - 1) |
-		pll_src;
+	STM32_RCC_PLLCFGR =
+		PLLCFGR_PLLP(0) | PLLCFGR_PLLR(STM32G4_PLL_R / 2 - 1) |
+		PLLCFGR_PLLR_EN | PLLCFGR_PLLQ(0) | PLLCFGR_PLLQ_EN |
+		PLLCFGR_PLLN(pll_n) | PLLCFGR_PLLM(pll_m - 1) | pll_src;
 
 	/* Wait until PLL is locked */
 	wait_for_ready(&(STM32_RCC_CR), STM32_RCC_CR_PLLON,
@@ -116,9 +113,11 @@ static void stm32g4_config_pll(uint32_t hclk_hz, uint32_t pll_src,
 static void stm32g4_config_low_speed_clock(void)
 {
 	/* Ensure that LSI is ON */
-	wait_for_ready(&(STM32_RCC_CSR),
-		STM32_RCC_CSR_LSION, STM32_RCC_CSR_LSIRDY);
+	wait_for_ready(&(STM32_RCC_CSR), STM32_RCC_CSR_LSION,
+		       STM32_RCC_CSR_LSIRDY);
 
+	/* Setup RTC Clock input */
+	STM32_RCC_BDCR |= STM32_RCC_BDCR_BDRST;
 	STM32_RCC_BDCR = STM32_RCC_BDCR_RTCEN | BDCR_RTCSEL(BDCR_SRC_LSI);
 }
 
@@ -161,10 +160,10 @@ void stm32g4_set_flash_ws(uint32_t freq_hz)
 	 * found in Table 9 of RM0440 - STM32G4 technical reference manual. A
 	 * table lookup is not required though as WS = HCLK (MHz) / 20
 	 */
-	ws = freq_hz /  WAIT_STATE_FREQ_STEP_HZ;
+	ws = freq_hz / WAIT_STATE_FREQ_STEP_HZ;
 	/* Enable data and instruction cache */
 	STM32_FLASH_ACR |= STM32_FLASH_ACR_DCEN | STM32_FLASH_ACR_ICEN |
-		STM32_FLASH_ACR_PRFTEN | ws;
+			   STM32_FLASH_ACR_PRFTEN | ws;
 }
 
 void clock_init(void)
@@ -240,26 +239,27 @@ void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles)
 	}
 }
 
-void clock_enable_module(enum module_id module, int enable)
+test_mockable void clock_enable_module(enum module_id module, int enable)
 {
 	if (module == MODULE_USB) {
-		if (enable)
+		if (enable) {
+			STM32_RCC_APB1ENR |= STM32_RCC_PB1_USB;
 			STM32_RCC_CRRCR |= RCC_CRRCR_HSI48O;
-		else
+		} else {
 			STM32_RCC_CRRCR &= ~RCC_CRRCR_HSI48O;
+			STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_USB;
+		}
 	} else if (module == MODULE_I2C) {
 		if (enable) {
 			/* Enable clocks to I2C modules if necessary */
-			STM32_RCC_APB1ENR1 |=
-				STM32_RCC_APB1ENR1_I2C1EN |
-				STM32_RCC_APB1ENR1_I2C2EN |
-				STM32_RCC_APB1ENR1_I2C3EN;
+			STM32_RCC_APB1ENR1 |= STM32_RCC_APB1ENR1_I2C1EN |
+					      STM32_RCC_APB1ENR1_I2C2EN |
+					      STM32_RCC_APB1ENR1_I2C3EN;
 			STM32_RCC_APB1ENR2 |= STM32_RCC_APB1ENR2_I2C4EN;
 		} else {
-			STM32_RCC_APB1ENR1 &=
-				~(STM32_RCC_APB1ENR1_I2C1EN |
-				  STM32_RCC_APB1ENR1_I2C2EN |
-				  STM32_RCC_APB1ENR1_I2C3EN);
+			STM32_RCC_APB1ENR1 &= ~(STM32_RCC_APB1ENR1_I2C1EN |
+						STM32_RCC_APB1ENR1_I2C2EN |
+						STM32_RCC_APB1ENR1_I2C3EN);
 			STM32_RCC_APB1ENR2 &= ~STM32_RCC_APB1ENR2_I2C4EN;
 		}
 	} else if (module == MODULE_ADC) {
@@ -269,9 +269,20 @@ void clock_enable_module(enum module_id module, int enable)
 					      STM32_RCC_APB2ENR_ADC345EN);
 		else
 			STM32_RCC_AHB2ENR &= ~(STM32_RCC_AHB2ENR_ADC12EN |
-					      STM32_RCC_APB2ENR_ADC345EN);
+					       STM32_RCC_APB2ENR_ADC345EN);
 	} else {
 		CPRINTS("stm32g4: enable clock module %d not supported",
 			module);
 	}
 }
+
+int clock_is_module_enabled(enum module_id module)
+{
+	if (module == MODULE_USB)
+		return !!(STM32_RCC_APB1ENR & STM32_RCC_PB1_USB);
+	else if (module == MODULE_I2C)
+		return !!(STM32_RCC_APB1ENR1 & STM32_RCC_APB1ENR1_I2C1EN);
+	else if (module == MODULE_ADC)
+		return !!(STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_ADC12EN);
+	return 0;
+}
diff --git a/chip/stm32/clock-stm32h7.c b/chip/stm32/clock-stm32h7.c
index ba233dbd76..1128626e06 100644
--- a/chip/stm32/clock-stm32h7.c
+++ b/chip/stm32/clock-stm32h7.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,9 +13,7 @@
  * but at least yields predictable behavior.
  */
 
-
-#include <stdbool.h>
-
+#include "builtin/assert.h"
 #include "chipset.h"
 #include "clock.h"
 #include "common.h"
@@ -29,9 +27,11 @@
 #include "uart.h"
 #include "util.h"
 
+#include <stdbool.h>
+
 /* Check chip family and variant for compatibility */
 #ifndef CHIP_FAMILY_STM32H7
-#error  Source clock-stm32h7.c does not support this chip family.
+#error Source clock-stm32h7.c does not support this chip family.
 #endif
 #ifndef CHIP_VARIANT_STM32H7X3
 #error Unsupported chip variant.
@@ -39,13 +39,13 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ##args)
 
 enum clock_osc {
-	OSC_HSI = 0,	/* High-speed internal oscillator */
-	OSC_CSI,	/* Multi-speed internal oscillator: NOT IMPLEMENTED */
-	OSC_HSE,	/* High-speed external oscillator: NOT IMPLEMENTED */
-	OSC_PLL,	/* PLL */
+	OSC_HSI = 0, /* High-speed internal oscillator */
+	OSC_CSI, /* Multi-speed internal oscillator: NOT IMPLEMENTED */
+	OSC_HSE, /* High-speed external oscillator: NOT IMPLEMENTED */
+	OSC_PLL, /* PLL */
 };
 
 enum voltage_scale {
@@ -57,12 +57,12 @@ enum voltage_scale {
 };
 
 enum freq {
-	FREQ_1KHZ   = 1000,
-	FREQ_32KHZ  = 32  * FREQ_1KHZ,
-	FREQ_1MHZ   = 1000000,
-	FREQ_2MHZ   = 2   * FREQ_1MHZ,
-	FREQ_16MHZ  = 16  * FREQ_1MHZ,
-	FREQ_64MHZ  = 64  * FREQ_1MHZ,
+	FREQ_1KHZ = 1000,
+	FREQ_32KHZ = 32 * FREQ_1KHZ,
+	FREQ_1MHZ = 1000000,
+	FREQ_2MHZ = 2 * FREQ_1MHZ,
+	FREQ_16MHZ = 16 * FREQ_1MHZ,
+	FREQ_64MHZ = 64 * FREQ_1MHZ,
 	FREQ_140MHZ = 140 * FREQ_1MHZ,
 	FREQ_200MHZ = 200 * FREQ_1MHZ,
 	FREQ_280MHZ = 280 * FREQ_1MHZ,
@@ -144,13 +144,13 @@ static void clock_flash_latency(enum freq axi_freq, enum voltage_scale vos)
  *
  * @param output_freq The target output frequency.
  */
-static void clock_pll1_configure(enum freq output_freq) {
+static void clock_pll1_configure(enum freq output_freq)
+{
 	uint32_t divm = 4; // Input prescaler (16MHz max for PLL -- 64/4 ==> 16)
-	uint32_t divn;     // Pll multiplier
-	uint32_t divp;     // Output 1 prescaler
+	uint32_t divn; // Pll multiplier
+	uint32_t divp; // Output 1 prescaler
 
-	switch (output_freq)
-	{
+	switch (output_freq) {
 	case FREQ_400MHZ:
 		/*
 		 * PLL1 configuration:
@@ -190,8 +190,8 @@ static void clock_pll1_configure(enum freq output_freq) {
 	 * Using VCO wide-range setting, STM32_RCC_PLLCFG_PLL1VCOSEL_WIDE,
 	 * requires input frequency to be between 2MHz and 16MHz.
 	 */
-	ASSERT(FREQ_2MHZ <= (STM32_HSI_CLOCK/divm));
-	ASSERT((STM32_HSI_CLOCK/divm) <= FREQ_16MHZ);
+	ASSERT(FREQ_2MHZ <= (STM32_HSI_CLOCK / divm));
+	ASSERT((STM32_HSI_CLOCK / divm) <= FREQ_16MHZ);
 
 	/*
 	 * Ensure that we actually reach the target frequency.
@@ -199,14 +199,14 @@ static void clock_pll1_configure(enum freq output_freq) {
 	ASSERT((STM32_HSI_CLOCK / divm * divn / divp) == output_freq);
 
 	/* Configure PLL1 using 64 Mhz HSI as input */
-	STM32_RCC_PLLCKSELR = STM32_RCC_PLLCKSEL_PLLSRC_HSI
-			    | STM32_RCC_PLLCKSEL_DIVM1(divm);
+	STM32_RCC_PLLCKSELR = STM32_RCC_PLLCKSEL_PLLSRC_HSI |
+			      STM32_RCC_PLLCKSEL_DIVM1(divm);
 	/* in integer mode, wide range VCO with 16Mhz input, use divP */
-	STM32_RCC_PLLCFGR = STM32_RCC_PLLCFG_PLL1VCOSEL_WIDE
-			  | STM32_RCC_PLLCFG_PLL1RGE_8M_16M
-			  | STM32_RCC_PLLCFG_DIVP1EN;
-	STM32_RCC_PLL1DIVR = STM32_RCC_PLLDIV_DIVP(divp)
-			   | STM32_RCC_PLLDIV_DIVN(divn);
+	STM32_RCC_PLLCFGR = STM32_RCC_PLLCFG_PLL1VCOSEL_WIDE |
+			    STM32_RCC_PLLCFG_PLL1RGE_8M_16M |
+			    STM32_RCC_PLLCFG_DIVP1EN;
+	STM32_RCC_PLL1DIVR = STM32_RCC_PLLDIV_DIVP(divp) |
+			     STM32_RCC_PLLDIV_DIVN(divn);
 }
 
 /**
@@ -215,22 +215,22 @@ static void clock_pll1_configure(enum freq output_freq) {
  * @param sysclk The input system clock, after the system clock prescaler.
  * @return The bus clock speed selected and configured
  */
-static enum freq clock_peripheral_configure(enum freq sysclk) {
-	switch (sysclk)
-	{
+static enum freq clock_peripheral_configure(enum freq sysclk)
+{
+	switch (sysclk) {
 	case FREQ_64MHZ:
 		/* Restore /1 HPRE (AHB prescaler) */
 		/* Disable downstream prescalers */
-		STM32_RCC_D1CFGR = STM32_RCC_D1CFGR_HPRE_DIV1
-				 | STM32_RCC_D1CFGR_D1PPRE_DIV1
-				 | STM32_RCC_D1CFGR_D1CPRE_DIV1;
+		STM32_RCC_D1CFGR = STM32_RCC_D1CFGR_HPRE_DIV1 |
+				   STM32_RCC_D1CFGR_D1PPRE_DIV1 |
+				   STM32_RCC_D1CFGR_D1CPRE_DIV1;
 		/* TODO(b/149512910): Adjust more peripheral prescalers */
 		return FREQ_64MHZ;
 	case FREQ_400MHZ:
 		/* Put /2 on HPRE (AHB prescaler) to keep at the 200MHz max */
-		STM32_RCC_D1CFGR = STM32_RCC_D1CFGR_HPRE_DIV2
-				 | STM32_RCC_D1CFGR_D1PPRE_DIV1
-				 | STM32_RCC_D1CFGR_D1CPRE_DIV1;
+		STM32_RCC_D1CFGR = STM32_RCC_D1CFGR_HPRE_DIV2 |
+				   STM32_RCC_D1CFGR_D1PPRE_DIV1 |
+				   STM32_RCC_D1CFGR_D1CPRE_DIV1;
 		/* TODO(b/149512910): Adjust more peripheral prescalers */
 		return FREQ_200MHZ;
 	default:
@@ -293,16 +293,16 @@ static void clock_switch_osc(enum clock_osc osc)
 
 static void switch_voltage_scale(enum voltage_scale vos)
 {
-	volatile uint32_t *const vos_reg   = &STM32_PWR_D3CR;
-	const uint32_t           vos_ready = STM32_PWR_D3CR_VOSRDY;
-	const uint32_t           vos_mask  = STM32_PWR_D3CR_VOSMASK;
-	const uint32_t           vos_values[] = {
-						/* See note below about VOS0. */
-						STM32_PWR_D3CR_VOS1,
-						STM32_PWR_D3CR_VOS1,
-						STM32_PWR_D3CR_VOS2,
-						STM32_PWR_D3CR_VOS3,
-						};
+	volatile uint32_t *const vos_reg = &STM32_PWR_D3CR;
+	const uint32_t vos_ready = STM32_PWR_D3CR_VOSRDY;
+	const uint32_t vos_mask = STM32_PWR_D3CR_VOSMASK;
+	const uint32_t vos_values[] = {
+		/* See note below about VOS0. */
+		STM32_PWR_D3CR_VOS1,
+		STM32_PWR_D3CR_VOS1,
+		STM32_PWR_D3CR_VOS2,
+		STM32_PWR_D3CR_VOS3,
+	};
 	BUILD_ASSERT(ARRAY_SIZE(vos_values) == VOLTAGE_SCALE_COUNT);
 
 	/*
@@ -344,7 +344,8 @@ static void clock_set_osc(enum clock_osc osc)
 	case OSC_HSI:
 		/* Switch to HSI */
 		clock_switch_osc(osc);
-		current_bus_freq = clock_peripheral_configure(target_sysclk_freq);
+		current_bus_freq =
+			clock_peripheral_configure(target_sysclk_freq);
 		/* Use more optimized flash latency settings for 64-MHz ACLK */
 		clock_flash_latency(current_bus_freq, target_voltage_scale);
 		/* Turn off the PLL1 to save power */
@@ -368,7 +369,8 @@ static void clock_set_osc(enum clock_osc osc)
 		clock_pll1_configure(target_sysclk_freq);
 		/* turn on PLL1 and wait until it's ready */
 		clock_enable_osc(OSC_PLL, true);
-		current_bus_freq = clock_peripheral_configure(target_sysclk_freq);
+		current_bus_freq =
+			clock_peripheral_configure(target_sysclk_freq);
 		/* Increase flash latency before transition the clock */
 		clock_flash_latency(current_bus_freq, target_voltage_scale);
 
@@ -381,7 +383,7 @@ static void clock_set_osc(enum clock_osc osc)
 	hook_notify(HOOK_FREQ_CHANGE);
 }
 
-void clock_enable_module(enum module_id module, int enable)
+test_mockable void clock_enable_module(enum module_id module, int enable)
 {
 	/* Assume we have a single task using MODULE_FAST_CPU */
 	if (module == MODULE_FAST_CPU) {
@@ -399,6 +401,7 @@ void clock_enable_module(enum module_id module, int enable)
 static int idle_sleep_cnt;
 static int idle_dsleep_cnt;
 static uint64_t idle_dsleep_time_us;
+static int idle_sleep_prevented_cnt;
 static int dsleep_recovery_margin_us = 1000000;
 
 /* STOP_MODE_LATENCY: delay to wake up from STOP mode with flash off in SVOS5 */
@@ -407,9 +410,9 @@ static int dsleep_recovery_margin_us = 1000000;
 static void low_power_init(void)
 {
 	/* Clock LPTIM1 on the 32-kHz LSI for STOP mode time keeping */
-	STM32_RCC_D2CCIP2R = (STM32_RCC_D2CCIP2R &
-		~STM32_RCC_D2CCIP2_LPTIM1SEL_MASK)
-		| STM32_RCC_D2CCIP2_LPTIM1SEL_LSI;
+	STM32_RCC_D2CCIP2R =
+		(STM32_RCC_D2CCIP2R & ~STM32_RCC_D2CCIP2_LPTIM1SEL_MASK) |
+		STM32_RCC_D2CCIP2_LPTIM1SEL_LSI;
 
 	/* configure LPTIM1 as our 1-Khz low power timer in STOP mode */
 	STM32_RCC_APB1LENR |= STM32_RCC_PB1_LPTIM1;
@@ -427,16 +430,15 @@ static void low_power_init(void)
 	STM32_EXTI_CPUIMR2 |= BIT(15); /* [15] wkup47: LPTIM1 wake-up */
 
 	/* optimize power vs latency in STOP mode */
-	STM32_PWR_CR = (STM32_PWR_CR & ~STM32_PWR_CR_SVOS_MASK)
-		     | STM32_PWR_CR_SVOS5
-		     | STM32_PWR_CR_FLPS;
+	STM32_PWR_CR = (STM32_PWR_CR & ~STM32_PWR_CR_SVOS_MASK) |
+		       STM32_PWR_CR_SVOS5 | STM32_PWR_CR_FLPS;
 }
 
 void clock_refresh_console_in_use(void)
 {
 }
 
-void lptim_interrupt(void)
+static void lptim_interrupt(void)
 {
 	STM32_LPTIM_ICR(1) = STM32_LPTIM_INT_CMPM;
 }
@@ -463,6 +465,11 @@ static void set_lptim_event(int delay_us, uint16_t *lptim_cnt)
 	*lptim_cnt = cnt;
 }
 
+static bool timer_interrupt_pending(void)
+{
+	return task_is_irq_pending(IRQ_TIM(TIM_CLOCK32));
+}
+
 void __idle(void)
 {
 	timestamp_t t0;
@@ -471,13 +478,59 @@ void __idle(void)
 	uint16_t lptim0;
 
 	while (1) {
-		asm volatile("cpsid i");
+		interrupt_disable();
 
+		/*
+		 * Get timestamp with interrupts disabled.
+		 * This value is used as a base to calculate timestamp after
+		 * wake from deep sleep. In combination with next_delay it gives
+		 * information how long the CPU can sleep. The timestamp can
+		 * point to the previous "epoch" when timer overflowed after
+		 * interrupts were disabled, since clksrc_high (which keeps
+		 * higher 32 bits of the timestamp) will not be updated.
+		 */
 		t0 = get_time();
+
+		/*
+		 * Get time to next event.
+		 * After disabling interrupts, event timestamp
+		 * (__hw_clock_event_get()) is frozen, because
+		 * process_timers(), responsible for updating the
+		 * next event value with __hw_clock_event_set(),
+		 * can't be called. There is a risk that timer overflow
+		 * occurred after interrupts were disabled and obtained
+		 * event timestamp points to previous "epoch". We will
+		 * check that later.
+		 */
 		next_delay = __hw_clock_event_get() - t0.le.lo;
 
+		/*
+		 * Repeat idle enter procedure when timer interrupt is pending
+		 * (eg. overflow occurred after disabling interrupts). To work
+		 * properly, this code assumes that timer interrupt is enabled
+		 * in NVIC and interrupt is generated on timer overflow.
+		 */
+		if (timer_interrupt_pending()) {
+			idle_sleep_prevented_cnt++;
+
+			/* Enable interrupts to handle detected overflow. */
+			interrupt_enable();
+
+			/* Repeat idle enter procedure. */
+			continue;
+		}
+
 		if (DEEP_SLEEP_ALLOWED &&
 		    next_delay > LPTIM_PERIOD_US + STOP_MODE_LATENCY) {
+			/*
+			 * Sleep time MUST be smaller than watchdog period.
+			 * Otherwise watchdog will wake us from deep sleep
+			 * which is not what we want. Please note that this
+			 * assert won't fire if we are already part way through
+			 * the watchdog period.
+			 */
+			ASSERT(next_delay < CONFIG_WATCHDOG_PERIOD_MS * MSEC);
+
 			/* deep-sleep in STOP mode */
 			idle_dsleep_cnt++;
 
@@ -492,7 +545,7 @@ void __idle(void)
 			/* ensure outstanding memory transactions complete */
 			asm volatile("dsb");
 
-			asm("wfi");
+			cpu_enter_suspend_mode();
 
 			CPU_SCB_SYSCTRL &= ~0x4;
 
@@ -527,9 +580,9 @@ void __idle(void)
 			idle_sleep_cnt++;
 
 			/* normal idle : only CPU clock stopped */
-			asm("wfi");
+			cpu_enter_suspend_mode();
 		}
-		asm volatile("cpsie i");
+		interrupt_enable();
 	}
 }
 
@@ -537,22 +590,23 @@ void __idle(void)
 /**
  * Print low power idle statistics
  */
-static int command_idle_stats(int argc, char **argv)
+static int command_idle_stats(int argc, const char **argv)
 {
 	timestamp_t ts = get_time();
 
 	ccprintf("Num idle calls that sleep:           %d\n", idle_sleep_cnt);
 	ccprintf("Num idle calls that deep-sleep:      %d\n", idle_dsleep_cnt);
 	ccprintf("Time spent in deep-sleep:            %.6llds\n",
-			idle_dsleep_time_us);
+		 idle_dsleep_time_us);
+	ccprintf("Num of prevented sleep:              %d\n",
+		 idle_sleep_prevented_cnt);
 	ccprintf("Total time on:                       %.6llds\n", ts.val);
 	ccprintf("Deep-sleep closest to wake deadline: %dus\n",
-			dsleep_recovery_margin_us);
+		 dsleep_recovery_margin_us);
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats,
-			"",
+DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, "",
 			"Print last idle stats");
 #endif /* CONFIG_CMD_IDLE_STATS */
 #endif /* CONFIG_LOW_POWER_IDLE */
@@ -584,11 +638,11 @@ void clock_init(void)
 	 * by putting it on the fixed 64-Mhz HSI clock.
 	 * per_ck is clocked directly by the HSI (as per the default settings).
 	 */
-	STM32_RCC_D2CCIP1R = (STM32_RCC_D2CCIP1R &
-		~(STM32_RCC_D2CCIP1R_SPI123SEL_MASK |
-		  STM32_RCC_D2CCIP1R_SPI45SEL_MASK))
-		| STM32_RCC_D2CCIP1R_SPI123SEL_PERCK
-		| STM32_RCC_D2CCIP1R_SPI45SEL_HSI;
+	STM32_RCC_D2CCIP1R =
+		(STM32_RCC_D2CCIP1R & ~(STM32_RCC_D2CCIP1R_SPI123SEL_MASK |
+					STM32_RCC_D2CCIP1R_SPI45SEL_MASK)) |
+		STM32_RCC_D2CCIP1R_SPI123SEL_PERCK |
+		STM32_RCC_D2CCIP1R_SPI45SEL_HSI;
 
 	/* Use more optimized flash latency settings for ACLK = HSI = 64 Mhz */
 	clock_flash_latency(FREQ_64MHZ, VOLTAGE_SCALE3);
@@ -603,7 +657,7 @@ void clock_init(void)
 #endif
 }
 
-static int command_clock(int argc, char **argv)
+static int command_clock(int argc, const char **argv)
 {
 	if (argc >= 2) {
 		if (!strcasecmp(argv[1], "hsi"))
@@ -616,5 +670,5 @@ static int command_clock(int argc, char **argv)
 	ccprintf("Clock frequency is now %d Hz\n", clock_get_freq());
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(clock, command_clock,
-			"hsi | pll", "Set clock frequency");
+DECLARE_CONSOLE_COMMAND(clock, command_clock, "hsi | pll",
+			"Set clock frequency");
diff --git a/chip/stm32/clock-stm32l.c b/chip/stm32/clock-stm32l.c
index a4e9dd7cdf..f4e69e4dad 100644
--- a/chip/stm32/clock-stm32l.c
+++ b/chip/stm32/clock-stm32l.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -37,9 +37,9 @@ static int fake_hibernate;
 #define MSI_1MHZ_CLOCK BIT(20)
 
 enum clock_osc {
-	OSC_INIT = 0,	/* Uninitialized */
-	OSC_HSI,	/* High-speed oscillator */
-	OSC_MSI,	/* Med-speed oscillator @ 1 MHz */
+	OSC_INIT = 0, /* Uninitialized */
+	OSC_HSI, /* High-speed oscillator */
+	OSC_MSI, /* Med-speed oscillator @ 1 MHz */
 };
 
 static int freq;
@@ -86,8 +86,8 @@ static void clock_set_osc(enum clock_osc osc)
 	switch (osc) {
 	case OSC_HSI:
 		/* Ensure that HSI is ON */
-		wait_for_ready(&STM32_RCC_CR,
-			       STM32_RCC_CR_HSION, STM32_RCC_CR_HSIRDY);
+		wait_for_ready(&STM32_RCC_CR, STM32_RCC_CR_HSION,
+			       STM32_RCC_CR_HSIRDY);
 
 		/* Disable LPSDSR */
 		STM32_PWR_CR &= ~STM32_PWR_CR_LPSDSR;
@@ -122,7 +122,7 @@ static void clock_set_osc(enum clock_osc osc)
 		STM32_RCC_CFGR = STM32_RCC_CFGR_SW_HSI;
 		/* RM says to check SWS bits to make sure HSI is the sysclock */
 		while ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MASK) !=
-			STM32_RCC_CFGR_SWS_HSI)
+		       STM32_RCC_CFGR_SWS_HSI)
 			;
 
 		/* Disable MSI */
@@ -137,14 +137,14 @@ static void clock_set_osc(enum clock_osc osc)
 			(STM32_RCC_ICSCR & ~STM32_RCC_ICSCR_MSIRANGE_MASK) |
 			STM32_RCC_ICSCR_MSIRANGE_1MHZ;
 		/* Ensure that MSI is ON */
-		wait_for_ready(&STM32_RCC_CR,
-			       STM32_RCC_CR_MSION, STM32_RCC_CR_MSIRDY);
+		wait_for_ready(&STM32_RCC_CR, STM32_RCC_CR_MSION,
+			       STM32_RCC_CR_MSIRDY);
 
 		/* Switch to MSI */
 		STM32_RCC_CFGR = STM32_RCC_CFGR_SW_MSI;
 		/* RM says to check SWS bits to make sure MSI is the sysclock */
 		while ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MASK) !=
-			STM32_RCC_CFGR_SWS_MSI)
+		       STM32_RCC_CFGR_SWS_MSI)
 			;
 
 		/*
@@ -195,28 +195,40 @@ static void clock_set_osc(enum clock_osc osc)
 	}
 }
 
-void clock_enable_module(enum module_id module, int enable)
+static uint64_t clock_mask;
+
+test_mockable void clock_enable_module(enum module_id module, int enable)
 {
-	static uint32_t clock_mask;
-	int new_mask;
+	uint64_t new_mask;
 
 	if (enable)
-		new_mask = clock_mask | BIT(module);
+		new_mask = clock_mask | BIT_ULL(module);
 	else
-		new_mask = clock_mask & ~BIT(module);
+		new_mask = clock_mask & ~BIT_ULL(module);
 
 	/* Only change clock if needed */
 	if ((!!new_mask) != (!!clock_mask)) {
-
 		/* Flush UART before switching clock speed */
 		cflush();
 
 		clock_set_osc(new_mask ? OSC_HSI : OSC_MSI);
 	}
 
+	if (module == MODULE_USB) {
+		if (enable)
+			STM32_RCC_APB1ENR |= STM32_RCC_PB1_USB;
+		else
+			STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_USB;
+	}
+
 	clock_mask = new_mask;
 }
 
+int clock_is_module_enabled(enum module_id module)
+{
+	return !!(clock_mask & BIT_ULL(module));
+}
+
 #ifdef CONFIG_STM32L_FAKE_HIBERNATE
 /*
  *  This is for NOT having enough hibernate (more precisely, the stand-by mode)
@@ -301,7 +313,7 @@ static void fake_hibernate_power_button_hook(void)
 	}
 }
 DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, fake_hibernate_power_button_hook,
-	HOOK_PRIO_DEFAULT);
+	     HOOK_PRIO_DEFAULT);
 
 static void fake_hibernate_lid_hook(void)
 {
@@ -352,7 +364,7 @@ static void clock_chipset_shutdown(void)
 DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, clock_chipset_shutdown, HOOK_PRIO_DEFAULT);
 DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, clock_chipset_shutdown, HOOK_PRIO_DEFAULT);
 
-static int command_clock(int argc, char **argv)
+static int command_clock(int argc, const char **argv)
 {
 	if (argc >= 2) {
 		if (!strcasecmp(argv[1], "hsi"))
@@ -366,6 +378,5 @@ static int command_clock(int argc, char **argv)
 	ccprintf("Clock frequency is now %d Hz\n", freq);
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(clock, command_clock,
-			"hsi | msi",
+DECLARE_CONSOLE_COMMAND(clock, command_clock, "hsi | msi",
 			"Set clock frequency");
diff --git a/chip/stm32/clock-stm32l4.c b/chip/stm32/clock-stm32l4.c
index 1bba787779..fd59d2aa3a 100644
--- a/chip/stm32/clock-stm32l4.c
+++ b/chip/stm32/clock-stm32l4.c
@@ -1,32 +1,58 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-/* Clocks and power management settings */
+/* Clocks and power management settings for STM32L4xx as well as STM32L5xx. */
 
+#include "builtin/assert.h"
 #include "chipset.h"
+#include "clock-l4.h"
 #include "clock.h"
 #include "common.h"
 #include "console.h"
 #include "cpu.h"
 #include "hooks.h"
+#include "host_command.h"
 #include "registers.h"
+#include "rtc.h"
+#include "timer.h"
+#include "uart.h"
 #include "util.h"
 
+/* Console output macros */
+#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
+#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args)
+
 /* High-speed oscillator is 16 MHz */
 #define STM32_HSI_CLOCK 16000000
 /* Multi-speed oscillator is 4 MHz by default */
 #define STM32_MSI_CLOCK 4000000
 
+/* Real Time Clock (RTC) */
+
+#ifdef CONFIG_STM32_CLOCK_HSE_HZ
+#define RTC_PREDIV_A 39
+#define RTC_FREQ ((STM32L4_RTC_REQ) / (RTC_PREDIV_A + 1)) /* Hz */
+#else /* from LSI clock */
+#define RTC_PREDIV_A 1
+#define RTC_FREQ (STM32L4_LSI_CLOCK / (RTC_PREDIV_A + 1)) /* Hz */
+#endif
+#define RTC_PREDIV_S (RTC_FREQ - 1)
+/*
+ * Scaling factor to ensure that the intermediate values computed from/to the
+ * RTC frequency are fitting in a 32-bit integer.
+ */
+#define SCALING 1000
+
 enum clock_osc {
-	OSC_INIT = 0,	/* Uninitialized */
-	OSC_HSI,	/* High-speed internal oscillator */
-	OSC_MSI,	/* Multi-speed internal oscillator */
-#ifdef STM32_HSE_CLOCK	/* Allows us to catch absence of HSE at comiple time */
-	OSC_HSE,	/* High-speed external oscillator */
+	OSC_INIT = 0, /* Uninitialized */
+	OSC_HSI, /* High-speed internal oscillator */
+	OSC_MSI, /* Multi-speed internal oscillator */
+#ifdef STM32_HSE_CLOCK /* Allows us to catch absence of HSE at comiple time */
+	OSC_HSE, /* High-speed external oscillator */
 #endif
-	OSC_PLL,	/* PLL */
+	OSC_PLL, /* PLL */
 };
 
 static int freq = STM32_MSI_CLOCK;
@@ -71,6 +97,9 @@ static void clock_enable_osc(enum clock_osc osc)
 		break;
 #ifdef STM32_HSE_CLOCK
 	case OSC_HSE:
+#ifdef STM32_HSE_BYP
+		STM32_RCC_CR |= STM32_RCC_CR_HSEBYP;
+#endif
 		ready = STM32_RCC_CR_HSERDY;
 		on = STM32_RCC_CR_HSEON;
 		break;
@@ -92,6 +121,7 @@ static void clock_switch_osc(enum clock_osc osc)
 {
 	uint32_t sw;
 	uint32_t sws;
+	uint32_t val;
 
 	switch (osc) {
 	case OSC_HSI:
@@ -115,9 +145,11 @@ static void clock_switch_osc(enum clock_osc osc)
 	default:
 		return;
 	}
-
-	STM32_RCC_CFGR = sw;
-	while ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MASK) != sws)
+	val = STM32_RCC_CFGR;
+	val &= ~STM32_RCC_CFGR_SW;
+	val |= sw;
+	STM32_RCC_CFGR = val;
+	while ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MSK) != sws)
 		;
 }
 
@@ -131,12 +163,61 @@ static void clock_switch_osc(enum clock_osc osc)
  * 5. Enable the desired PLL outputs by configuring PLLPEN, PLLQEN, PLLREN
  *    in RCC_PLLCFGR.
  */
-static int stm32_configure_pll(enum clock_osc osc,
-			       uint8_t m, uint8_t n, uint8_t r)
+static int stm32_configure_pll(enum clock_osc osc, uint8_t m, uint8_t n,
+			       uint8_t r)
 {
 	uint32_t val;
+	bool pll_unchanged;
 	int f;
 
+	val = STM32_RCC_PLLCFGR;
+	pll_unchanged = true;
+
+	if (osc == OSC_HSI)
+		if ((val & STM32_RCC_PLLCFGR_PLLSRC_MSK) !=
+		    STM32_RCC_PLLCFGR_PLLSRC_HSI)
+			pll_unchanged = false;
+
+	if (osc == OSC_MSI)
+		if ((val & STM32_RCC_PLLCFGR_PLLSRC_MSK) !=
+		    STM32_RCC_PLLCFGR_PLLSRC_MSI)
+			pll_unchanged = false;
+
+#ifdef STM32_HSE_CLOCK
+	if (osc == OSC_HSE)
+		if ((val & STM32_RCC_PLLCFGR_PLLSRC_MSK) !=
+		    STM32_RCC_PLLCFGR_PLLSRC_HSE)
+			pll_unchanged = false;
+#endif
+
+	if ((val & STM32_RCC_PLLCFGR_PLLM_MSK) !=
+	    ((m - 1) << STM32_RCC_PLLCFGR_PLLM_POS))
+		pll_unchanged = false;
+
+	if ((val & STM32_RCC_PLLCFGR_PLLN_MSK) !=
+	    (n << STM32_RCC_PLLCFGR_PLLN_POS))
+		pll_unchanged = false;
+
+	if ((val & STM32_RCC_PLLCFGR_PLLR_MSK) !=
+	    (((r >> 1) - 1) << STM32_RCC_PLLCFGR_PLLR_POS))
+		pll_unchanged = false;
+
+	if (pll_unchanged == true) {
+		if (osc == OSC_HSI)
+			f = STM32_HSI_CLOCK;
+		else
+			f = STM32_MSI_CLOCK;
+
+		if (!(STM32_RCC_CR & STM32_RCC_CR_PLLRDY)) {
+			STM32_RCC_CR |= STM32_RCC_CR_PLLON;
+			STM32_RCC_PLLCFGR |= STM32_RCC_PLLCFGR_PLLREN;
+
+			while ((STM32_RCC_CR & STM32_RCC_CR_PLLRDY) == 0)
+				;
+		}
+		/* (f * n) shouldn't overflow based on their max values */
+		return (f * n / m / r);
+	}
 	/* 1 */
 	STM32_RCC_CR &= ~STM32_RCC_CR_PLLON;
 
@@ -147,7 +228,7 @@ static int stm32_configure_pll(enum clock_osc osc,
 	/* 3 */
 	val = STM32_RCC_PLLCFGR;
 
-	val &= ~STM32_RCC_PLLCFGR_PLLSRC_MASK;
+	val &= ~STM32_RCC_PLLCFGR_PLLSRC_MSK;
 	switch (osc) {
 	case OSC_HSI:
 		val |= STM32_RCC_PLLCFGR_PLLSRC_HSI;
@@ -168,27 +249,27 @@ static int stm32_configure_pll(enum clock_osc osc,
 	}
 
 	ASSERT(m > 0 && m < 9);
-	val &= ~STM32_RCC_PLLCFGR_PLLM_MASK;
-	val |= (m  - 1) << STM32_RCC_PLLCFGR_PLLM_SHIFT;
+	val &= ~STM32_RCC_PLLCFGR_PLLM_MSK;
+	val |= (m - 1) << STM32_RCC_PLLCFGR_PLLM_POS;
 
 	/* Max and min values are from TRM */
 	ASSERT(n > 7 && n < 87);
-	val &= ~STM32_RCC_PLLCFGR_PLLN_MASK;
-	val |= n << STM32_RCC_PLLCFGR_PLLN_SHIFT;
+	val &= ~STM32_RCC_PLLCFGR_PLLN_MSK;
+	val |= n << STM32_RCC_PLLCFGR_PLLN_POS;
 
-	val &= ~STM32_RCC_PLLCFGR_PLLR_MASK;
+	val &= ~STM32_RCC_PLLCFGR_PLLR_MSK;
 	switch (r) {
 	case 2:
-		val |= 0 << STM32_RCC_PLLCFGR_PLLR_SHIFT;
+		val |= 0 << STM32_RCC_PLLCFGR_PLLR_POS;
 		break;
 	case 4:
-		val |= 1 << STM32_RCC_PLLCFGR_PLLR_SHIFT;
+		val |= 1 << STM32_RCC_PLLCFGR_PLLR_POS;
 		break;
 	case 6:
-		val |= 2 << STM32_RCC_PLLCFGR_PLLR_SHIFT;
+		val |= 2 << STM32_RCC_PLLCFGR_PLLR_POS;
 		break;
 	case 8:
-		val |= 3 << STM32_RCC_PLLCFGR_PLLR_SHIFT;
+		val |= 3 << STM32_RCC_PLLCFGR_PLLR_POS;
 		break;
 	default:
 		return -1;
@@ -201,7 +282,7 @@ static int stm32_configure_pll(enum clock_osc osc,
 
 	/* 5 */
 	val = STM32_RCC_PLLCFGR;
-	val |= 1 << STM32_RCC_PLLCFGR_PLLREN_SHIFT;
+	val |= 1 << STM32_RCC_PLLCFGR_PLLREN_POS;
 	STM32_RCC_PLLCFGR = val;
 
 	/* (f * n) shouldn't overflow based on their max values */
@@ -229,8 +310,8 @@ static void clock_set_osc(enum clock_osc osc, enum clock_osc pll_osc)
 		/* Ensure that HSI is ON */
 		clock_enable_osc(osc);
 
-		/* Disable LPSDSR */
-		STM32_PWR_CR &= ~STM32_PWR_CR_LPSDSR;
+		/* Set HSI as system clock after exiting stop mode */
+		STM32_RCC_CFGR |= STM32_RCC_CFGR_STOPWUCK;
 
 		/* Switch to HSI */
 		clock_switch_osc(osc);
@@ -243,21 +324,22 @@ static void clock_set_osc(enum clock_osc osc, enum clock_osc pll_osc)
 
 	case OSC_MSI:
 		/* Switch to MSI @ 1MHz */
-		STM32_RCC_ICSCR =
-			(STM32_RCC_ICSCR & ~STM32_RCC_ICSCR_MSIRANGE_MASK) |
-			STM32_RCC_ICSCR_MSIRANGE_1MHZ;
+		STM32_RCC_CR = (STM32_RCC_CR & ~STM32_RCC_ICSCR_MSIRANGE_MASK) |
+			       STM32_RCC_ICSCR_MSIRANGE_1MHZ;
 		/* Ensure that MSI is ON */
 		clock_enable_osc(osc);
 
+		/*
+		 * Set MSI as system clock after exiting stop mode
+		 */
+		STM32_RCC_CFGR &= ~STM32_RCC_CFGR_STOPWUCK;
+
 		/* Switch to MSI */
 		clock_switch_osc(osc);
 
 		/* Disable HSI */
 		STM32_RCC_CR &= ~STM32_RCC_CR_HSION;
 
-		/* Enable LPSDSR */
-		STM32_PWR_CR |= STM32_PWR_CR_LPSDSR;
-
 		freq = STM32_MSI_CLOCK;
 		break;
 
@@ -271,7 +353,7 @@ static void clock_set_osc(enum clock_osc osc, enum clock_osc pll_osc)
 
 		/* Disable other clock sources */
 		STM32_RCC_CR &= ~(STM32_RCC_CR_MSION | STM32_RCC_CR_HSION |
-				STM32_RCC_CR_PLLON);
+				  STM32_RCC_CR_PLLON);
 
 		freq = STM32_HSE_CLOCK;
 
@@ -279,20 +361,76 @@ static void clock_set_osc(enum clock_osc osc, enum clock_osc pll_osc)
 #endif
 	case OSC_PLL:
 		/* Ensure that source clock is stable */
-		clock_enable_osc(pll_osc);
-
-		/* Configure PLLCFGR */
-		freq = stm32_configure_pll(pll_osc, STM32_PLLM,
-					   STM32_PLLN, STM32_PLLR);
+		if (pll_osc == OSC_INIT) {
+			if ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MSK) !=
+			    STM32_RCC_CFGR_SWS_PLL) {
+				STM32_RCC_CFGR |= STM32_RCC_CFGR_STOPWUCK;
+				clock_enable_osc(OSC_HSI);
+				freq = stm32_configure_pll(OSC_HSI, STM32_PLLM,
+							   STM32_PLLN,
+							   STM32_PLLR);
+			} else {
+				/* already set PLL, skip */
+				freq = STM32_HSI_CLOCK * STM32_PLLN /
+				       STM32_PLLM / STM32_PLLR;
+				break;
+			}
+		} else {
+			clock_enable_osc(pll_osc);
+			/* Configure PLLCFGR */
+			freq = stm32_configure_pll(pll_osc, STM32_PLLM,
+						   STM32_PLLN, STM32_PLLR);
+		}
 		ASSERT(freq > 0);
 
-		/* Adjust flash latency as instructed in TRM */
-		val = STM32_FLASH_ACR;
-		val &= ~STM32_FLASH_ACR_LATENCY_MASK;
-		/* Flash 4 wait state. TODO: Should depend on freq. */
-		val |= 4 << STM32_FLASH_ACR_LATENCY_SHIFT;
-		STM32_FLASH_ACR = val;
-		while (STM32_FLASH_ACR != val)
+		/* Change to Range 1 if Freq > 26MHz */
+		if (freq > 26000000U) {
+			/* Set VCO range 1 */
+			val = STM32_RCC_CR;
+			val &= ~PWR_CR1_VOS_MSK;
+			val |= PWR_CR1_VOS_0;
+			STM32_RCC_CR = val;
+
+			/*
+			 * Set Flash latency according to frequency
+			 */
+			val = STM32_FLASH_ACR;
+			val &= ~STM32_FLASH_ACR_LATENCY_MASK;
+			if (freq <= 16000000U) {
+				/* nothing */
+			} else if (freq <= 32000000U) {
+				val |= 1;
+			} else if (freq <= 48000000U) {
+				val |= 2;
+			} else if (freq <= 64000000U) {
+				val |= 3;
+			} else if (freq <= 80000000U) {
+				val |= 4;
+			} else {
+				val |= 4;
+				CPUTS("Incorrect Frequency setting in VOS1!\n");
+			}
+			STM32_FLASH_ACR = val;
+		} else {
+			val = STM32_FLASH_ACR;
+			val &= ~STM32_FLASH_ACR_LATENCY_MASK;
+
+			if (freq <= 6000000U) {
+				/* nothing */
+			} else if (freq <= 12000000U) {
+				val |= 1;
+			} else if (freq <= 18000000U) {
+				val |= 2;
+			} else if (freq <= 26000000U) {
+				val |= 3;
+			} else {
+				val |= 4;
+				CPUTS("Incorrect Frequency setting in VOS2!\n");
+			}
+			STM32_FLASH_ACR = val;
+		}
+
+		while (val != STM32_FLASH_ACR)
 			;
 
 		/* Switch to PLL */
@@ -313,35 +451,158 @@ static void clock_set_osc(enum clock_osc osc, enum clock_osc pll_osc)
 	}
 }
 
-void clock_enable_module(enum module_id module, int enable)
+static uint64_t clock_mask;
+
+test_mockable void clock_enable_module(enum module_id module, int enable)
 {
-	static uint32_t clock_mask;
-	int new_mask;
+	uint64_t new_mask;
 
 	if (enable)
-		new_mask = clock_mask | BIT(module);
+		new_mask = clock_mask | BIT_ULL(module);
 	else
-		new_mask = clock_mask & ~BIT(module);
+		new_mask = clock_mask & ~BIT_ULL(module);
 
 	/* Only change clock if needed */
-	if ((!!new_mask) != (!!clock_mask)) {
+	if (new_mask == clock_mask)
+		return;
+
+	if (module == MODULE_ADC) {
+		STM32_RCC_APB2ENR |= STM32_RCC_PB2_SYSCFGEN;
+		STM32_RCC_APB1ENR1 |= STM32_RCC_PB1_PWREN;
+
+		/* ADC select bit 28/29 */
+		STM32_RCC_CCIPR &= ~STM32_RCC_CCIPR_ADCSEL_MSK;
+		STM32_RCC_CCIPR |=
+			(STM32_RCC_CCIPR_ADCSEL_0 | STM32_RCC_CCIPR_ADCSEL_1);
+		/* ADC clock enable */
+		if (enable)
+			STM32_RCC_AHB2ENR |= STM32_RCC_HB2_ADC1;
+		else
+			STM32_RCC_AHB2ENR &= ~STM32_RCC_HB2_ADC1;
+	} else if (module == MODULE_SPI_FLASH) {
+		if (enable)
+			STM32_RCC_APB1ENR1 |= STM32_RCC_PB1_SPI2;
+		else
+			STM32_RCC_APB1ENR1 &= ~STM32_RCC_PB1_SPI2;
+	} else if (module == MODULE_SPI || module == MODULE_SPI_CONTROLLER) {
+		if (enable)
+			STM32_RCC_APB2ENR |= STM32_RCC_APB2ENR_SPI1EN;
+		else if ((new_mask &
+			  (BIT(MODULE_SPI) | BIT(MODULE_SPI_CONTROLLER))) == 0)
+			STM32_RCC_APB2ENR &= ~STM32_RCC_APB2ENR_SPI1EN;
+	} else if (module == MODULE_USB) {
+#ifdef CHIP_FAMILY_STM32L5
+		if (enable) {
+			/* Keep USB subsystem under reset for now. */
+			STM32_RCC_APB1RSTR2 |= STM32_RCC_APB1RSTR2_USBFSRST;
+
+			/* Enable power to the USB domain. */
+			STM32_PWR_CR2 |= STM32_PWR_CR2_USV;
+
+			/* Enable internal 48 MHz RC oscillator. */
+			wait_for_ready(&STM32_RCC_CRRCR,
+				       STM32_RCC_CRRCR_HSI48ON,
+				       STM32_RCC_CRRCR_HSI48RDY);
+
+			/* Enable USB device clock. */
+			STM32_RCC_APB1ENR2 |= STM32_RCC_APB1ENR2_USBFSEN;
 
-		/* Flush UART before switching clock speed */
-		cflush();
+			/* 48 MHz clock is stable, release USB reset. */
+			STM32_RCC_APB1RSTR2 &= ~STM32_RCC_APB1RSTR2_USBFSRST;
 
-		clock_set_osc(new_mask ? OSC_HSI : OSC_MSI, OSC_INIT);
+		} else {
+			STM32_RCC_APB1ENR2 &= ~STM32_RCC_APB1ENR2_USBFSEN;
+			STM32_CRS_CR &=
+				~(STM32_CRS_CR_CEN | STM32_CRS_CR_AUTOTRIMEN);
+			STM32_RCC_CRRCR &= ~STM32_RCC_CRRCR_HSI48ON;
+			STM32_PWR_CR2 &= ~STM32_PWR_CR2_USV;
+		}
+#endif
 	}
 
 	clock_mask = new_mask;
 }
 
+int clock_is_module_enabled(enum module_id module)
+{
+	return !!(clock_mask & BIT_ULL(module));
+}
+
+void rtc_init(void)
+{
+	/* Enable RTC Alarm in EXTI */
+	STM32_EXTI_RTSR |= EXTI_RTC_ALR_EVENT;
+	task_enable_irq(STM32_IRQ_RTC_ALARM);
+
+	/* RTC was initilized, avoid initialization again */
+	if (STM32_RTC_ISR & STM32_RTC_ISR_INITS)
+		return;
+
+	rtc_unlock_regs();
+
+	/* Enter RTC initialize mode */
+	STM32_RTC_ISR |= STM32_RTC_ISR_INIT;
+	while (!(STM32_RTC_ISR & STM32_RTC_ISR_INITF))
+		;
+
+	/* Set clock prescalars */
+	STM32_RTC_PRER = (RTC_PREDIV_A << 16) | RTC_PREDIV_S;
+
+	/* Start RTC timer */
+	STM32_RTC_ISR &= ~STM32_RTC_ISR_INIT;
+	while (STM32_RTC_ISR & STM32_RTC_ISR_INITF)
+		;
+
+	/* Enable RTC alarm interrupt */
+	STM32_RTC_CR |= STM32_RTC_CR_ALRAIE | STM32_RTC_CR_BYPSHAD;
+
+	rtc_lock_regs();
+}
+
+#if defined(CONFIG_CMD_RTC) || defined(CONFIG_HOSTCMD_RTC)
+void rtc_set(uint32_t sec)
+{
+	struct rtc_time_reg rtc;
+
+	sec_to_rtc(sec, &rtc);
+	rtc_unlock_regs();
+
+	/* Disable alarm */
+	STM32_RTC_CR &= ~STM32_RTC_CR_ALRAE;
+
+	/* Enter RTC initialize mode */
+	STM32_RTC_ISR |= STM32_RTC_ISR_INIT;
+	while (!(STM32_RTC_ISR & STM32_RTC_ISR_INITF))
+		;
+
+	/* Set clock prescalars */
+	STM32_RTC_PRER = (RTC_PREDIV_A << 16) | RTC_PREDIV_S;
+
+	STM32_RTC_TR = rtc.rtc_tr;
+	STM32_RTC_DR = rtc.rtc_dr;
+	/* Start RTC timer */
+	STM32_RTC_ISR &= ~STM32_RTC_ISR_INIT;
+
+	rtc_lock_regs();
+}
+#endif
+
 void clock_init(void)
 {
 #ifdef STM32_HSE_CLOCK
 	clock_set_osc(OSC_PLL, OSC_HSE);
+#else
+#ifdef STM32_USE_PLL
+	clock_set_osc(OSC_PLL, OSC_INIT);
 #else
 	clock_set_osc(OSC_HSI, OSC_INIT);
 #endif
+#endif
+
+#ifdef CONFIG_LOW_POWER_IDLE
+	low_power_init();
+	rtc_init();
+#endif
 }
 
 static void clock_chipset_startup(void)
@@ -360,7 +621,7 @@ static void clock_chipset_shutdown(void)
 DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, clock_chipset_shutdown, HOOK_PRIO_DEFAULT);
 DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, clock_chipset_shutdown, HOOK_PRIO_DEFAULT);
 
-static int command_clock(int argc, char **argv)
+static int command_clock(int argc, const char **argv)
 {
 	if (argc >= 2) {
 		if (!strcasecmp(argv[1], "hsi"))
@@ -386,7 +647,491 @@ static int command_clock(int argc, char **argv)
 DECLARE_CONSOLE_COMMAND(clock, command_clock,
 			"hsi | msi"
 #ifdef STM32_HSE_CLOCK
-			" | hse | pll"
+			" | hse"
 #endif
-			,
+			" | pll",
 			"Set clock frequency");
+
+uint32_t rtcss_to_us(uint32_t rtcss)
+{
+	return ((RTC_PREDIV_S - (rtcss & 0x7FFF)) * (SECOND / SCALING) /
+		(RTC_FREQ / SCALING));
+}
+
+uint32_t us_to_rtcss(uint32_t us)
+{
+	return (RTC_PREDIV_S -
+		(us * (RTC_FREQ / SCALING) / (SECOND / SCALING)));
+}
+
+/* Convert decimal to BCD */
+static uint8_t u8_to_bcd(uint8_t val)
+{
+	/* Fast division by 10 (when lacking HW div) */
+	uint32_t quot = ((uint32_t)val * 0xCCCD) >> 19;
+	uint32_t rem = val - quot * 10;
+
+	return rem | (quot << 4);
+}
+
+/* Convert between RTC regs in BCD and seconds */
+static uint32_t rtc_tr_to_sec(uint32_t rtc_tr)
+{
+	uint32_t sec;
+
+	/* convert the hours field */
+	sec = (((rtc_tr & RTC_TR_HT) >> RTC_TR_HT_POS) * 10 +
+	       ((rtc_tr & RTC_TR_HU) >> RTC_TR_HU_POS)) *
+	      3600;
+	/* convert the minutes field */
+	sec += (((rtc_tr & RTC_TR_MNT) >> RTC_TR_MNT_POS) * 10 +
+		((rtc_tr & RTC_TR_MNU) >> RTC_TR_MNU_POS)) *
+	       60;
+	/* convert the seconds field */
+	sec += ((rtc_tr & RTC_TR_ST) >> RTC_TR_ST_POS) * 10 +
+	       (rtc_tr & RTC_TR_SU);
+	return sec;
+}
+
+static uint32_t sec_to_rtc_tr(uint32_t sec)
+{
+	uint32_t rtc_tr;
+	uint8_t hour;
+	uint8_t min;
+
+	sec %= SECS_PER_DAY;
+	/* convert the hours field */
+	hour = sec / 3600;
+	rtc_tr = u8_to_bcd(hour) << 16;
+	/* convert the minutes field */
+	sec -= hour * 3600;
+	min = sec / 60;
+	rtc_tr |= u8_to_bcd(min) << 8;
+	/* convert the seconds field */
+	sec -= min * 60;
+	rtc_tr |= u8_to_bcd(sec);
+
+	return rtc_tr;
+}
+
+/* Register setup before RTC alarm is allowed for update */
+static void pre_work_set_rtc_alarm(void)
+{
+	rtc_unlock_regs();
+
+	/* Make sure alarm is disabled */
+	STM32_RTC_CR &= ~STM32_RTC_CR_ALRAE;
+	while (!(STM32_RTC_ISR & STM32_RTC_ISR_ALRAWF))
+		;
+	STM32_RTC_ISR &= ~STM32_RTC_ISR_ALRAF;
+#ifdef STM32_EXTI_RPR
+	/* Separate rising and falling edge pending registers. */
+	STM32_EXTI_RPR = BIT(18);
+	STM32_EXTI_FPR = BIT(18);
+#else
+	/* One combined rising/falling edge pending registers. */
+	STM32_EXTI_PR = BIT(18);
+#endif
+}
+
+/* Register setup after RTC alarm is updated */
+static void post_work_set_rtc_alarm(void)
+{
+	/* Enable alarm and alarm interrupt */
+	STM32_EXTI_IMR |= BIT(18);
+	STM32_EXTI_RTSR |= BIT(18);
+	STM32_RTC_CR |= (STM32_RTC_CR_ALRAE);
+
+	rtc_lock_regs();
+}
+
+#ifdef CONFIG_HOSTCMD_RTC
+static struct wake_time host_wake_time;
+
+bool is_host_wake_alarm_expired(timestamp_t ts)
+{
+	return host_wake_time.ts.val &&
+	       timestamp_expired(host_wake_time.ts, &ts);
+}
+
+void restore_host_wake_alarm(void)
+{
+	if (!host_wake_time.ts.val)
+		return;
+
+	pre_work_set_rtc_alarm();
+
+	/* Set alarm time */
+	STM32_RTC_ALRMAR = host_wake_time.rtc_alrmar;
+
+	post_work_set_rtc_alarm();
+}
+
+static uint32_t rtc_dr_to_sec(uint32_t rtc_dr)
+{
+	struct calendar_date time;
+	uint32_t sec;
+
+	time.year =
+		(((rtc_dr & 0xf00000) >> 20) * 10 + ((rtc_dr & 0xf0000) >> 16));
+	time.month = (((rtc_dr & 0x1000) >> 12) * 10 + ((rtc_dr & 0xf00) >> 8));
+	time.day = ((rtc_dr & 0x30) >> 4) * 10 + (rtc_dr & 0xf);
+
+	sec = date_to_sec(time);
+
+	return sec;
+}
+
+static uint32_t sec_to_rtc_dr(uint32_t sec)
+{
+	struct calendar_date time;
+	uint32_t rtc_dr;
+
+	time = sec_to_date(sec);
+
+	rtc_dr = u8_to_bcd(time.year) << 16;
+	rtc_dr |= u8_to_bcd(time.month) << 8;
+	rtc_dr |= u8_to_bcd(time.day);
+
+	return rtc_dr;
+}
+#endif
+
+uint32_t rtc_to_sec(const struct rtc_time_reg *rtc)
+{
+	uint32_t sec = 0;
+
+#ifdef CONFIG_HOSTCMD_RTC
+	sec = rtc_dr_to_sec(rtc->rtc_dr);
+#endif
+	return sec + (rtcss_to_us(rtc->rtc_ssr) / SECOND) +
+	       rtc_tr_to_sec(rtc->rtc_tr);
+}
+
+void sec_to_rtc(uint32_t sec, struct rtc_time_reg *rtc)
+{
+	rtc->rtc_dr = 0;
+#ifdef CONFIG_HOSTCMD_RTC
+	rtc->rtc_dr = sec_to_rtc_dr(sec);
+#endif
+	rtc->rtc_tr = sec_to_rtc_tr(sec);
+	rtc->rtc_ssr = 0;
+}
+
+/* Return sub-10-sec time diff between two rtc readings
+ *
+ * Note: this function assumes rtc0 was sampled before rtc1.
+ * Additionally, this function only looks at the difference mod 10
+ * seconds.
+ */
+uint32_t get_rtc_diff(const struct rtc_time_reg *rtc0,
+		      const struct rtc_time_reg *rtc1)
+{
+	uint32_t rtc0_val, rtc1_val, diff;
+
+	rtc0_val = (rtc0->rtc_tr & RTC_TR_SU) * SECOND +
+		   rtcss_to_us(rtc0->rtc_ssr);
+	rtc1_val = (rtc1->rtc_tr & RTC_TR_SU) * SECOND +
+		   rtcss_to_us(rtc1->rtc_ssr);
+	diff = rtc1_val;
+	if (rtc1_val < rtc0_val) {
+		/* rtc_ssr has wrapped, since we assume rtc0 < rtc1, add
+		 * 10 seconds to get the correct value
+		 */
+		diff += 10 * SECOND;
+	}
+	diff -= rtc0_val;
+	return diff;
+}
+
+void rtc_read(struct rtc_time_reg *rtc)
+{
+	/*
+	 * Read current time synchronously. Each register must be read
+	 * twice with identical values because glitches may occur for reads
+	 * close to the RTCCLK edge.
+	 */
+	do {
+		rtc->rtc_dr = STM32_RTC_DR;
+
+		do {
+			rtc->rtc_tr = STM32_RTC_TR;
+
+			do {
+				rtc->rtc_ssr = STM32_RTC_SSR;
+			} while (rtc->rtc_ssr != STM32_RTC_SSR);
+
+		} while (rtc->rtc_tr != STM32_RTC_TR);
+
+	} while (rtc->rtc_dr != STM32_RTC_DR);
+}
+
+void set_rtc_alarm(uint32_t delay_s, uint32_t delay_us,
+		   struct rtc_time_reg *rtc, uint8_t save_alarm)
+{
+	uint32_t alarm_sec = 0;
+	uint32_t alarm_us = 0;
+
+	if (delay_s == EC_RTC_ALARM_CLEAR && !delay_us) {
+		reset_rtc_alarm(rtc);
+		return;
+	}
+
+	/* Alarm timeout must be within 1 day (86400 seconds) */
+	ASSERT((delay_s + delay_us / SECOND) < SECS_PER_DAY);
+
+	pre_work_set_rtc_alarm();
+	rtc_read(rtc);
+
+	/* Calculate alarm time */
+	alarm_sec = rtc_tr_to_sec(rtc->rtc_tr) + delay_s;
+
+	if (delay_us) {
+		alarm_us = rtcss_to_us(rtc->rtc_ssr) + delay_us;
+		alarm_sec = alarm_sec + alarm_us / SECOND;
+		alarm_us = alarm_us % SECOND;
+	}
+
+	/*
+	 * If seconds is greater than 1 day, subtract by 1 day to deal with
+	 * 24-hour rollover.
+	 */
+	if (alarm_sec >= SECS_PER_DAY)
+		alarm_sec -= SECS_PER_DAY;
+
+	/*
+	 * Set alarm time in seconds and check for match on
+	 * hours, minutes, and seconds.
+	 */
+	STM32_RTC_ALRMAR = sec_to_rtc_tr(alarm_sec) | 0xc0000000;
+
+	/*
+	 * Set alarm time in subseconds and check for match on subseconds.
+	 * If the caller doesn't specify subsecond delay (e.g. host command),
+	 * just align the alarm time to second.
+	 */
+	STM32_RTC_ALRMASSR = delay_us ? (us_to_rtcss(alarm_us) | 0x0f000000) :
+					0;
+
+#ifdef CONFIG_HOSTCMD_RTC
+	/*
+	 * If alarm is set by the host, preserve the wake time timestamp
+	 * and alarm registers.
+	 */
+	if (save_alarm) {
+		host_wake_time.ts.val = delay_s * SECOND + get_time().val;
+		host_wake_time.rtc_alrmar = STM32_RTC_ALRMAR;
+	}
+#endif
+	post_work_set_rtc_alarm();
+}
+
+uint32_t get_rtc_alarm(void)
+{
+	struct rtc_time_reg now;
+	uint32_t now_sec;
+	uint32_t alarm_sec;
+
+	if (!(STM32_RTC_CR & STM32_RTC_CR_ALRAE))
+		return 0;
+
+	rtc_read(&now);
+
+	now_sec = rtc_tr_to_sec(now.rtc_tr);
+	alarm_sec = rtc_tr_to_sec(STM32_RTC_ALRMAR & 0x3fffff);
+
+	return ((alarm_sec < now_sec) ? SECS_PER_DAY : 0) +
+	       (alarm_sec - now_sec);
+}
+
+void reset_rtc_alarm(struct rtc_time_reg *rtc)
+{
+	rtc_unlock_regs();
+
+	/* Disable alarm */
+	STM32_RTC_CR &= ~STM32_RTC_CR_ALRAE;
+	STM32_RTC_ISR &= ~STM32_RTC_ISR_ALRAF;
+
+	/* Disable RTC alarm interrupt */
+	STM32_EXTI_IMR &= ~BIT(18);
+#ifdef STM32_EXTI_RPR
+	/* Separate rising and falling edge pending registers. */
+	STM32_EXTI_RPR = BIT(18);
+	STM32_EXTI_FPR = BIT(18);
+#else
+	/* One combined rising/falling edge pending registers. */
+	STM32_EXTI_PR = BIT(18);
+#endif
+
+	/* Clear the pending RTC alarm IRQ in NVIC */
+	task_clear_pending_irq(STM32_IRQ_RTC_ALARM);
+
+	/* Read current time */
+	rtc_read(rtc);
+
+	rtc_lock_regs();
+}
+
+#ifdef CONFIG_HOSTCMD_RTC
+static void set_rtc_host_event(void)
+{
+	host_set_single_event(EC_HOST_EVENT_RTC);
+}
+DECLARE_DEFERRED(set_rtc_host_event);
+#endif
+
+test_mockable_static void __rtc_alarm_irq(void)
+{
+	struct rtc_time_reg rtc;
+
+	reset_rtc_alarm(&rtc);
+
+#ifdef CONFIG_HOSTCMD_RTC
+	/* Wake up the host if there is a saved rtc wake alarm. */
+	if (host_wake_time.ts.val) {
+		host_wake_time.ts.val = 0;
+		hook_call_deferred(&set_rtc_host_event_data, 0);
+	}
+#endif
+}
+DECLARE_IRQ(STM32_IRQ_RTC_ALARM, __rtc_alarm_irq, 1);
+
+void print_system_rtc(enum console_channel ch)
+{
+	uint32_t sec;
+	struct rtc_time_reg rtc;
+
+	rtc_read(&rtc);
+	sec = rtc_to_sec(&rtc);
+
+	cprintf(ch, "RTC: 0x%08x (%d.00 s)\n", sec, sec);
+}
+
+#ifdef CONFIG_LOW_POWER_IDLE
+/* Low power idle statistics */
+static int idle_sleep_cnt;
+static int idle_dsleep_cnt;
+static uint64_t idle_dsleep_time_us;
+static int dsleep_recovery_margin_us = 1000000;
+
+/* STOP_MODE_LATENCY: delay to wake up from STOP mode with main regulator off */
+#define STOP_MODE_LATENCY 50 /* us */
+/* PLL_LOCK_LATENCY: delay to switch from HSI to PLL */
+#define PLL_LOCK_LATENCY 150 /* us */
+/*
+ * SET_RTC_MATCH_DELAY: max time to set RTC match alarm. If we set the alarm
+ * in the past, it will never wake up and cause a watchdog.
+ */
+#define SET_RTC_MATCH_DELAY 120 /* us */
+
+void low_power_init(void)
+{
+	/* Enter stop1 mode */
+	uint32_t val;
+
+	val = STM32_PWR_CR1;
+	val &= ~PWR_CR1_LPMS_MSK;
+	val |= PWR_CR1_LPMS_STOP1;
+	STM32_PWR_CR1 = val;
+}
+
+void clock_refresh_console_in_use(void)
+{
+}
+
+void __idle(void)
+{
+	timestamp_t t0;
+	uint32_t rtc_diff;
+	int next_delay, margin_us;
+	struct rtc_time_reg rtc0, rtc1;
+
+	while (1) {
+		interrupt_disable();
+
+		t0 = get_time();
+		next_delay = __hw_clock_event_get() - t0.le.lo;
+
+		if (DEEP_SLEEP_ALLOWED &&
+		    (next_delay > (STOP_MODE_LATENCY + PLL_LOCK_LATENCY +
+				   SET_RTC_MATCH_DELAY))) {
+			/* Deep-sleep in STOP mode */
+			idle_dsleep_cnt++;
+
+			uart_enable_wakeup(1);
+
+			/* Set deep sleep bit */
+			CPU_SCB_SYSCTRL |= 0x4;
+
+			set_rtc_alarm(0,
+				      next_delay - STOP_MODE_LATENCY -
+					      PLL_LOCK_LATENCY,
+				      &rtc0, 0);
+
+			/* ensure outstanding memory transactions complete */
+			asm volatile("dsb");
+
+			cpu_enter_suspend_mode();
+
+			CPU_SCB_SYSCTRL &= ~0x4;
+
+			/* turn on PLL and wait until it's ready */
+			STM32_RCC_APB1ENR1 |= STM32_RCC_APB1ENR1_PWREN;
+			clock_wait_bus_cycles(BUS_APB, 2);
+
+			stm32_configure_pll(OSC_HSI, STM32_PLLM, STM32_PLLN,
+					    STM32_PLLR);
+
+			/* Switch to PLL */
+			clock_switch_osc(OSC_PLL);
+
+			uart_enable_wakeup(0);
+
+			/* Fast forward timer according to RTC counter */
+			reset_rtc_alarm(&rtc1);
+			rtc_diff = get_rtc_diff(&rtc0, &rtc1);
+			t0.val = t0.val + rtc_diff;
+			force_time(t0);
+
+			/* Record time spent in deep sleep. */
+			idle_dsleep_time_us += rtc_diff;
+
+			/* Calculate how close we were to missing deadline */
+			margin_us = next_delay - rtc_diff;
+			if (margin_us < 0)
+				/* Use CPUTS to save stack space */
+				CPUTS("Idle overslept!\n");
+
+			/* Record the closest to missing a deadline. */
+			if (margin_us < dsleep_recovery_margin_us)
+				dsleep_recovery_margin_us = margin_us;
+		} else {
+			idle_sleep_cnt++;
+
+			/* Normal idle : only CPU clock stopped */
+			cpu_enter_suspend_mode();
+		}
+		interrupt_enable();
+	}
+}
+
+/*****************************************************************************/
+/* Console commands */
+/* Print low power idle statistics. */
+static int command_idle_stats(int argc, const char **argv)
+{
+	timestamp_t ts = get_time();
+
+	ccprintf("Num idle calls that sleep:           %d\n", idle_sleep_cnt);
+	ccprintf("Num idle calls that deep-sleep:      %d\n", idle_dsleep_cnt);
+	ccprintf("Time spent in deep-sleep:            %.6llus\n",
+		 idle_dsleep_time_us);
+	ccprintf("Total time on:                       %.6llus\n", ts.val);
+	ccprintf("Deep-sleep closest to wake deadline: %dus\n",
+		 dsleep_recovery_margin_us);
+
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, "",
+			"Print last idle stats");
+#endif /* CONFIG_LOW_POWER_IDLE */
diff --git a/chip/stm32/clock-stm32l5.c b/chip/stm32/clock-stm32l5.c
new file mode 100644
index 0000000000..a4cf34f7b8
--- /dev/null
+++ b/chip/stm32/clock-stm32l5.c
@@ -0,0 +1,6 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "clock-stm32l4.c"
diff --git a/chip/stm32/config-stm32f03x.h b/chip/stm32/config-stm32f03x.h
index 84266cdbfc..695b16f0b3 100644
--- a/chip/stm32/config-stm32f03x.h
+++ b/chip/stm32/config-stm32f03x.h
@@ -1,25 +1,25 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #ifdef CHIP_VARIANT_STM32F03X8
-#define CONFIG_FLASH_SIZE 0x00010000
-#define CONFIG_RAM_SIZE   0x00002000
+#define CONFIG_FLASH_SIZE_BYTES 0x00010000
+#define CONFIG_RAM_SIZE 0x00002000
 #else
-#define CONFIG_FLASH_SIZE 0x00008000
-#define CONFIG_RAM_SIZE   0x00001000
+#define CONFIG_FLASH_SIZE_BYTES 0x00008000
+#define CONFIG_RAM_SIZE 0x00001000
 #endif
 
 /* Memory mapping */
-#define CONFIG_FLASH_BANK_SIZE  0x1000
-#define CONFIG_FLASH_ERASE_SIZE 0x0400  /* erase bank size */
-#define CONFIG_FLASH_WRITE_SIZE 0x0002  /* minimum write size */
+#define CONFIG_FLASH_BANK_SIZE 0x1000
+#define CONFIG_FLASH_ERASE_SIZE 0x0400 /* erase bank size */
+#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */
 
 /* No page mode on STM32F, so no benefit to larger write sizes */
 #define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002
 
-#define CONFIG_RAM_BASE         0x20000000
+#define CONFIG_RAM_BASE 0x20000000
 
 /* Number of IRQ vectors on the NVIC */
 #define CONFIG_IRQ_COUNT 32
diff --git a/chip/stm32/config-stm32f05x.h b/chip/stm32/config-stm32f05x.h
index cab7b62d50..7f083b0eb2 100644
--- a/chip/stm32/config-stm32f05x.h
+++ b/chip/stm32/config-stm32f05x.h
@@ -1,19 +1,19 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Memory mapping */
-#define CONFIG_FLASH_SIZE (64 * 1024)
-#define CONFIG_FLASH_BANK_SIZE  0x1000
-#define CONFIG_FLASH_ERASE_SIZE 0x0400  /* erase bank size */
-#define CONFIG_FLASH_WRITE_SIZE 0x0002  /* minimum write size */
+#define CONFIG_FLASH_SIZE_BYTES (64 * 1024)
+#define CONFIG_FLASH_BANK_SIZE 0x1000
+#define CONFIG_FLASH_ERASE_SIZE 0x0400 /* erase bank size */
+#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */
 
 /* No page mode on STM32F, so no benefit to larger write sizes */
 #define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002
 
-#define CONFIG_RAM_BASE         0x20000000
-#define CONFIG_RAM_SIZE         0x00002000
+#define CONFIG_RAM_BASE 0x20000000
+#define CONFIG_RAM_SIZE 0x00002000
 
 /* Number of IRQ vectors on the NVIC */
 #define CONFIG_IRQ_COUNT 32
diff --git a/chip/stm32/config-stm32f07x.h b/chip/stm32/config-stm32f07x.h
index 199aef3361..31468f656e 100644
--- a/chip/stm32/config-stm32f07x.h
+++ b/chip/stm32/config-stm32f07x.h
@@ -1,19 +1,19 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Memory mapping */
-#define CONFIG_FLASH_SIZE (128 * 1024)
-#define CONFIG_FLASH_BANK_SIZE  0x1000
-#define CONFIG_FLASH_ERASE_SIZE 0x0800  /* erase bank size */
-#define CONFIG_FLASH_WRITE_SIZE 0x0002  /* minimum write size */
+#define CONFIG_FLASH_SIZE_BYTES (128 * 1024)
+#define CONFIG_FLASH_BANK_SIZE 0x1000
+#define CONFIG_FLASH_ERASE_SIZE 0x0800 /* erase bank size */
+#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */
 
 /* No page mode on STM32F, so no benefit to larger write sizes */
 #define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002
 
-#define CONFIG_RAM_BASE         0x20000000
-#define CONFIG_RAM_SIZE         0x00004000
+#define CONFIG_RAM_BASE 0x20000000
+#define CONFIG_RAM_SIZE 0x00004000
 
 /* Number of IRQ vectors on the NVIC */
 #define CONFIG_IRQ_COUNT 32
@@ -23,7 +23,10 @@
 #define CONFIG_CONSOLE_HISTORY 3
 
 /* USB packet ram config */
-#define CONFIG_USB_RAM_BASE        0x40006000
-#define CONFIG_USB_RAM_SIZE        1024
+#define CONFIG_USB_RAM_BASE 0x40006000
+#define CONFIG_USB_RAM_SIZE 1024
 #define CONFIG_USB_RAM_ACCESS_TYPE uint16_t
 #define CONFIG_USB_RAM_ACCESS_SIZE 2
+
+/* DFU Address */
+#define STM32_DFU_BASE 0x1fffC800
diff --git a/chip/stm32/config-stm32f09x.h b/chip/stm32/config-stm32f09x.h
index 3da8a342f2..405c63f3ec 100644
--- a/chip/stm32/config-stm32f09x.h
+++ b/chip/stm32/config-stm32f09x.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,16 +8,16 @@
  * Flash physical size: 256KB
  * Write protect sectors: 31 4KB sectors, one 132KB sector
  */
-#define CONFIG_FLASH_SIZE 0x00040000
-#define CONFIG_FLASH_BANK_SIZE  0x1000
-#define CONFIG_FLASH_ERASE_SIZE 0x0800  /* erase bank size */
-#define CONFIG_FLASH_WRITE_SIZE 0x0002  /* minimum write size */
+#define CONFIG_FLASH_SIZE_BYTES 0x00040000
+#define CONFIG_FLASH_BANK_SIZE 0x1000
+#define CONFIG_FLASH_ERASE_SIZE 0x0800 /* erase bank size */
+#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */
 
 /* No page mode on STM32F, so no benefit to larger write sizes */
 #define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002
 
-#define CONFIG_RAM_BASE         0x20000000
-#define CONFIG_RAM_SIZE         0x00008000
+#define CONFIG_RAM_BASE 0x20000000
+#define CONFIG_RAM_SIZE 0x00008000
 
 /* Number of IRQ vectors on the NVIC */
 #define CONFIG_IRQ_COUNT 32
@@ -43,34 +43,33 @@
  *
  */
 
-#define _SECTOR_4KB             (4 * 1024)
-#define _SECTOR_132KB           (132 * 1024)
+#define _SECTOR_4KB (4 * 1024)
+#define _SECTOR_132KB (132 * 1024)
 
 /* The EC uses one sector to emulate persistent state */
 #define CONFIG_FLASH_PSTATE
-#define CONFIG_FW_PSTATE_SIZE   _SECTOR_4KB
-#define CONFIG_FW_PSTATE_OFF    (30 * _SECTOR_4KB)
+#define CONFIG_FW_PSTATE_SIZE _SECTOR_4KB
+#define CONFIG_FW_PSTATE_OFF (30 * _SECTOR_4KB)
 
-#define CONFIG_RO_MEM_OFF       0
-#define CONFIG_RO_STORAGE_OFF   0
-#define CONFIG_RO_SIZE          (30 * _SECTOR_4KB)
-#define CONFIG_RW_MEM_OFF       (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE + \
-				 CONFIG_FW_PSTATE_SIZE)
-#define CONFIG_RW_STORAGE_OFF	0
-#define CONFIG_RW_SIZE          _SECTOR_132KB
+#define CONFIG_RO_MEM_OFF 0
+#define CONFIG_RO_STORAGE_OFF 0
+#define CONFIG_RO_SIZE (30 * _SECTOR_4KB)
+#define CONFIG_RW_MEM_OFF \
+	(CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE + CONFIG_FW_PSTATE_SIZE)
+#define CONFIG_RW_STORAGE_OFF 0
+#define CONFIG_RW_SIZE _SECTOR_132KB
 
-#define CONFIG_EC_PROTECTED_STORAGE_OFF  0
+#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
 #define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_OFF   CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE  (CONFIG_FLASH_SIZE - \
-					  CONFIG_EC_WRITABLE_STORAGE_OFF)
+#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE \
+	(CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF)
 
-#define CONFIG_WP_STORAGE_OFF   CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE  CONFIG_EC_PROTECTED_STORAGE_SIZE
+#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
+#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
 
 /* We map each write protect sector to a bank */
-#define PHYSICAL_BANKS          32
-#define WP_BANK_COUNT           31
-#define PSTATE_BANK             30
-#define PSTATE_BANK_COUNT       1
-
+#define PHYSICAL_BANKS 32
+#define WP_BANK_COUNT 31
+#define PSTATE_BANK 30
+#define PSTATE_BANK_COUNT 1
diff --git a/chip/stm32/config-stm32f373.h b/chip/stm32/config-stm32f373.h
index b77b1d98a6..f57350a17c 100644
--- a/chip/stm32/config-stm32f373.h
+++ b/chip/stm32/config-stm32f373.h
@@ -1,25 +1,28 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Memory mapping */
-#define CONFIG_FLASH_SIZE 0x00040000
-#define CONFIG_FLASH_BANK_SIZE  0x2000
-#define CONFIG_FLASH_ERASE_SIZE 0x0800  /* erase bank size */
-#define CONFIG_FLASH_WRITE_SIZE 0x0002  /* minimum write size */
+#define CONFIG_FLASH_SIZE_BYTES 0x00040000
+#define CONFIG_FLASH_BANK_SIZE 0x2000
+#define CONFIG_FLASH_ERASE_SIZE 0x0800 /* erase bank size */
+#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */
 
 /* No page mode on STM32F, so no benefit to larger write sizes */
 #define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002
 
-#define CONFIG_RAM_BASE         0x20000000
-#define CONFIG_RAM_SIZE         0x00008000
+#define CONFIG_RAM_BASE 0x20000000
+#define CONFIG_RAM_SIZE 0x00008000
 
 /* Number of IRQ vectors on the NVIC */
 #define CONFIG_IRQ_COUNT 81
 
 /* STM32F3 uses the older 4 byte aligned access mechanism */
-#define CONFIG_USB_RAM_BASE        0x40006000
-#define CONFIG_USB_RAM_SIZE        512
+#define CONFIG_USB_RAM_BASE 0x40006000
+#define CONFIG_USB_RAM_SIZE 512
 #define CONFIG_USB_RAM_ACCESS_TYPE uint32_t
 #define CONFIG_USB_RAM_ACCESS_SIZE 4
+
+/* DFU Address */
+#define STM32_DFU_BASE 0x1fffd800
diff --git a/chip/stm32/config-stm32f4.h b/chip/stm32/config-stm32f4.h
index c64cc3089a..d7ef668886 100644
--- a/chip/stm32/config-stm32f4.h
+++ b/chip/stm32/config-stm32f4.h
@@ -1,13 +1,13 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Memory mapping */
 #ifdef CHIP_VARIANT_STM32F412
-#	define CONFIG_FLASH_SIZE (1 * 1024 * 1024)
+#define CONFIG_FLASH_SIZE_BYTES (1 * 1024 * 1024)
 #else
-#	define CONFIG_FLASH_SIZE (512 * 1024)
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
 #endif
 
 /* 3 regions type: 16K, 64K and 128K */
@@ -16,7 +16,7 @@
 #define SIZE_128KB (128 * 1024)
 #define CONFIG_FLASH_REGION_TYPE_COUNT 3
 #define CONFIG_FLASH_MULTIPLE_REGION \
-	(5 + (CONFIG_FLASH_SIZE - SIZE_128KB) / SIZE_128KB)
+	(5 + (CONFIG_FLASH_SIZE_BYTES - SIZE_128KB) / SIZE_128KB)
 
 /* Erasing 128K can take up to 2s, need to defer erase. */
 #define CONFIG_FLASH_DEFERRED_ERASE
@@ -31,33 +31,32 @@
 #define CONFIG_FLASH_WRITE_IDEAL_SIZE CONFIG_FLASH_WRITE_SIZE
 
 #ifdef CHIP_VARIANT_STM32F412
-#	define CONFIG_RAM_BASE  0x20000000
-#	define CONFIG_RAM_SIZE  0x00040000 /* 256 KB */
+#define CONFIG_RAM_BASE 0x20000000
+#define CONFIG_RAM_SIZE 0x00040000 /* 256 KB */
 #else
-#	define CONFIG_RAM_BASE  0x20000000
-#	define CONFIG_RAM_SIZE  0x00020000 /* 128 KB */
+#define CONFIG_RAM_BASE 0x20000000
+#define CONFIG_RAM_SIZE 0x00020000 /* 128 KB */
 #endif
 
-#define CONFIG_RO_MEM_OFF	0
-#define CONFIG_RO_SIZE		(256 * 1024)
-#define CONFIG_RW_MEM_OFF	(256 * 1024)
-#define CONFIG_RW_SIZE		(256 * 1024)
+#define CONFIG_RO_MEM_OFF 0
+#define CONFIG_RO_SIZE (256 * 1024)
+#define CONFIG_RW_MEM_OFF (256 * 1024)
+#define CONFIG_RW_SIZE (256 * 1024)
 
-#define CONFIG_RO_STORAGE_OFF	0
-#define CONFIG_RW_STORAGE_OFF	0
+#define CONFIG_RO_STORAGE_OFF 0
+#define CONFIG_RW_STORAGE_OFF 0
 
-#define CONFIG_EC_PROTECTED_STORAGE_OFF		0
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE	CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_OFF		CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE					\
-		 (CONFIG_FLASH_SIZE - CONFIG_EC_WRITABLE_STORAGE_OFF)
-
-#define CONFIG_WP_STORAGE_OFF		CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE		CONFIG_EC_PROTECTED_STORAGE_SIZE
+#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
+#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE \
+	(CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF)
 
+#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
+#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
 
 #undef I2C_PORT_COUNT
-#define I2C_PORT_COUNT	4
+#define I2C_PORT_COUNT 4
 
 /* Use PSTATE embedded in the RO image, not in its own erase block */
 #define CONFIG_FLASH_PSTATE
@@ -67,4 +66,20 @@
 #define CONFIG_OTP
 
 /* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT	97
+#define CONFIG_IRQ_COUNT 97
+
+#undef CONFIG_CMD_CHARGEN
+
+/* DFU Address */
+#define STM32_DFU_BASE 0x1fff0000
+
+/*
+ * SET_RTC_MATCH_DELAY: max time to set RTC match alarm. If we set the alarm
+ * in the past, it will never wake up and cause a watchdog.
+ *
+ * This value is minimal time for which we can set RTC match alarm. It was
+ * obtained by setting the alarm and checking if the alarm interrupt was
+ * triggered. Unit test test_rtc_match_delay is responsible for verifying if
+ * setting the RTC match alarm with this value will generate the interrupt.
+ */
+#define SET_RTC_MATCH_DELAY 200 /* us */
diff --git a/chip/stm32/config-stm32f76x.h b/chip/stm32/config-stm32f76x.h
index 665bec36bf..e7380118f0 100644
--- a/chip/stm32/config-stm32f76x.h
+++ b/chip/stm32/config-stm32f76x.h
@@ -1,10 +1,10 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Memory mapping */
-#define CONFIG_FLASH_SIZE       (2048 * 1024)
+#define CONFIG_FLASH_SIZE_BYTES (2048 * 1024)
 
 /* 3 regions type: 32K, 128K and 256K */
 #define SIZE_32KB (32 * 1024)
@@ -12,7 +12,7 @@
 #define SIZE_256KB (256 * 1024)
 #define CONFIG_FLASH_REGION_TYPE_COUNT 3
 #define CONFIG_FLASH_MULTIPLE_REGION \
-	(5 + (CONFIG_FLASH_SIZE - SIZE_256KB) / SIZE_256KB)
+	(5 + (CONFIG_FLASH_SIZE_BYTES - SIZE_256KB) / SIZE_256KB)
 
 /* Erasing 256K can take up to 2s, need to defer erase. */
 #define CONFIG_FLASH_DEFERRED_ERASE
@@ -29,32 +29,35 @@
 /* DTCM-RAM: 128kB 0x20000000 - 0x2001FFFF*/
 /* SRAM1:    368kB 0x20020000 - 0x2007BFFF */
 /* SRAM2:     16kB 0x2007C000 - 0x2007FFFF */
-#define CONFIG_RAM_BASE		0x20000000
-#define CONFIG_RAM_SIZE		0x00080000
+#define CONFIG_RAM_BASE 0x20000000
+#define CONFIG_RAM_SIZE 0x00080000
 
-#define CONFIG_RO_MEM_OFF	0
-#define CONFIG_RO_SIZE		(1024 * 1024)
-#define CONFIG_RW_MEM_OFF	(1024 * 1024)
-#define CONFIG_RW_SIZE		(1024 * 1024)
+#define CONFIG_RO_MEM_OFF 0
+#define CONFIG_RO_SIZE (1024 * 1024)
+#define CONFIG_RW_MEM_OFF (1024 * 1024)
+#define CONFIG_RW_SIZE (1024 * 1024)
 
-#define CONFIG_RO_STORAGE_OFF	0
-#define CONFIG_RW_STORAGE_OFF	0
+#define CONFIG_RO_STORAGE_OFF 0
+#define CONFIG_RW_STORAGE_OFF 0
 
-#define CONFIG_EC_PROTECTED_STORAGE_OFF		0
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE	CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_OFF		CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE					\
-		 (CONFIG_FLASH_SIZE - CONFIG_EC_WRITABLE_STORAGE_OFF)
+#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
+#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE \
+	(CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF)
 
-#define CONFIG_WP_STORAGE_OFF		CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE		CONFIG_EC_PROTECTED_STORAGE_SIZE
+#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
+#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
 
 #undef I2C_PORT_COUNT
-#define I2C_PORT_COUNT	4
+#define I2C_PORT_COUNT 4
 
 /* Use PSTATE embedded in the RO image, not in its own erase block */
 #define CONFIG_FLASH_PSTATE
 #undef CONFIG_FLASH_PSTATE_BANK
 
 /* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT	109
+#define CONFIG_IRQ_COUNT 109
+
+/* DFU Address */
+#define STM32_DFU_BASE 0x1ff00000
diff --git a/chip/stm32/config-stm32g41xb.h b/chip/stm32/config-stm32g41xb.h
index ab8642b9e6..97e9d21d25 100644
--- a/chip/stm32/config-stm32g41xb.h
+++ b/chip/stm32/config-stm32g41xb.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,17 +16,12 @@
  * The minimum write size for STM32G4 is 8 bytes. Cros-EC does not support
  * PSTATE in single bank memories with a write size > 4 bytes.
  */
-/*
- * TODO(b/167462264): This is a temporary change to allow for platform bringup
- * without being constrained by flash space issue. Currently only using RO image
- * flashed with STM32 debugger.
- */
-#define CONFIG_FLASH_SIZE       (256 * 1024)
+
+#define CONFIG_FLASH_SIZE_BYTES (128 * 1024)
 #define CONFIG_FLASH_WRITE_SIZE 0x0004
 #define CONFIG_FLASH_BANK_SIZE (2 * 1024)
 #define CONFIG_FLASH_ERASE_SIZE CONFIG_FLASH_BANK_SIZE
 
-
 /* Erasing 128K can take up to 2s, need to defer erase. */
 #define CONFIG_FLASH_DEFERRED_ERASE
 
@@ -41,11 +36,11 @@
  * • 10 Kbytes mapped at address 0x1000 0000 (CCM SRAM). It is also aliased
  *   at 0x2000 5800 address to be accessed by all bus controllers.
  */
-#define CONFIG_RAM_BASE		0x20000000
-#define CONFIG_RAM_SIZE		0x00008000
+#define CONFIG_RAM_BASE 0x20000000
+#define CONFIG_RAM_SIZE 0x00008000
 
 #undef I2C_PORT_COUNT
-#define I2C_PORT_COUNT	3
+#define I2C_PORT_COUNT 3
 
 /* Number of DMA channels supported (6 channels each for DMA1 and DMA2) */
 #define DMAC_COUNT 12
@@ -55,4 +50,13 @@
 #undef CONFIG_FLASH_PSTATE_BANK
 
 /* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT	101
+#define CONFIG_IRQ_COUNT 101
+
+/* USB packet ram config */
+#define CONFIG_USB_RAM_BASE 0x40006000
+#define CONFIG_USB_RAM_SIZE 1024
+#define CONFIG_USB_RAM_ACCESS_TYPE uint16_t
+#define CONFIG_USB_RAM_ACCESS_SIZE 2
+
+/* DFU Address */
+#define STM32_DFU_BASE 0x1fff0000
diff --git a/chip/stm32/config-stm32g473xc.h b/chip/stm32/config-stm32g473xc.h
new file mode 100644
index 0000000000..63f4c73ea0
--- /dev/null
+++ b/chip/stm32/config-stm32g473xc.h
@@ -0,0 +1,68 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Memory mapping for STM32G473xc. The STM32G473xc is a category 1 device within
+ * the STM32G4 chip family. Category 1 devices have either 128, 256, or 512 kB
+ * of internal flash. 'xc' indicates 256 kB of internal flash.
+ *
+ * STM32G473xc can be configured via option bytes as either a single bank or
+ * dual bank device. Dual bank is the default selection.
+ * CONFIG_FLASH_BANK_SIZE is consistent with page size as defined in RM0440 TRM
+ * for the STM32G4 chip family. In dual bank mode, the flash is organized in 2
+ * kB pages, with 64 pages per bank for this variant.
+ *
+ * The minimum write size for STM32G4 is 8 bytes. Cros-EC does not support
+ * PSTATE in single bank memories with a write size > 4 bytes.
+ *
+ * TODO(b/181874494): Verify that dual bank mode should be used, or add support
+ * for enabling single bank mode on STM32G473xc.
+ */
+#define CONFIG_FLASH_SIZE_BYTES (256 * 1024)
+#define CONFIG_FLASH_WRITE_SIZE 0x0004
+#define CONFIG_FLASH_BANK_SIZE (2 * 1024)
+#define CONFIG_FLASH_ERASE_SIZE CONFIG_FLASH_BANK_SIZE
+
+/* Dual-bank (DBANK) mode is enabled by default for this chip */
+#define STM32_FLASH_DBANK_MODE
+
+/* Erasing 128K can take up to 2s, need to defer erase. */
+#define CONFIG_FLASH_DEFERRED_ERASE
+
+/* No page mode on STM32G4, so no benefit to larger write sizes */
+#define CONFIG_FLASH_WRITE_IDEAL_SIZE CONFIG_FLASH_WRITE_SIZE
+
+/*
+ * STM32G473xc is a category 3 SRAM device featuring 128 Kbytes of embedded
+ * SRAM. This SRAM is split into three blocks:
+ * • 80 Kbytes mapped at address 0x2000 0000 (SRAM1).
+ * • 16 Kbytes mapped at address 0x2001 4000 (SRAM2).
+ * • 32 Kbytes mapped at address 0x1000 0000 (CCM SRAM). It is also aliased
+ *   at 0x2001 8000 address to be accessed by all bus controllers.
+ */
+#define CONFIG_RAM_BASE 0x20000000
+#define CONFIG_RAM_SIZE 0x00020000
+
+#undef I2C_PORT_COUNT
+#define I2C_PORT_COUNT 4
+
+/* Number of DMA channels supported (6 channels each for DMA1 and DMA2) */
+#define DMAC_COUNT 12
+
+/* Use PSTATE embedded in the RO image, not in its own erase block */
+#define CONFIG_FLASH_PSTATE
+#undef CONFIG_FLASH_PSTATE_BANK
+
+/* Number of IRQ vectors on the NVIC */
+#define CONFIG_IRQ_COUNT 101
+
+/* USB packet ram config */
+#define CONFIG_USB_RAM_BASE 0x40006000
+#define CONFIG_USB_RAM_SIZE 1024
+#define CONFIG_USB_RAM_ACCESS_TYPE uint16_t
+#define CONFIG_USB_RAM_ACCESS_SIZE 2
+
+/* DFU Address */
+#define STM32_DFU_BASE 0x1fff0000
diff --git a/chip/stm32/config-stm32h7x3.h b/chip/stm32/config-stm32h7x3.h
index 399e6a6f1a..31f1d3c720 100644
--- a/chip/stm32/config-stm32h7x3.h
+++ b/chip/stm32/config-stm32h7x3.h
@@ -1,20 +1,20 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Memory mapping */
-#define CONFIG_FLASH_SIZE       (2048 * 1024)
-#define CONFIG_FLASH_ERASE_SIZE (128 * 1024)  /* erase bank size */
+#define CONFIG_FLASH_SIZE_BYTES (2048 * 1024)
+#define CONFIG_FLASH_ERASE_SIZE (128 * 1024) /* erase bank size */
 /* always use 256-bit writes due to ECC */
-#define CONFIG_FLASH_WRITE_SIZE          32   /* minimum write size */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE    32
+#define CONFIG_FLASH_WRITE_SIZE 32 /* minimum write size */
+#define CONFIG_FLASH_WRITE_IDEAL_SIZE 32
 
 /*
  * What the code is calling 'bank' is really the size of the block used for
  * write-protected, here it's 128KB sector (same as erase size).
  */
-#define CONFIG_FLASH_BANK_SIZE  (128 * 1024)
+#define CONFIG_FLASH_BANK_SIZE (128 * 1024)
 
 /* Erasing 128K can take up to 2s, need to defer erase. */
 #define CONFIG_FLASH_DEFERRED_ERASE
@@ -27,28 +27,28 @@
 /* (D2) AHB-SRAM3:  32kB 0x30040000 - 0x30047FFF */
 /* (D3) AHB-SRAM4:  64kB 0x38000000 - 0x3800FFFF */
 /* (D3) backup RAM:  4kB 0x38800000 - 0x38800FFF */
-#define CONFIG_RAM_BASE		0x24000000
-#define CONFIG_RAM_SIZE		0x00080000
+#define CONFIG_RAM_BASE 0x24000000
+#define CONFIG_RAM_SIZE 0x00080000
 
-#define CONFIG_RO_MEM_OFF	0
-#define CONFIG_RO_SIZE		(128 * 1024)
-#define CONFIG_RW_MEM_OFF	(CONFIG_FLASH_SIZE / 2)
-#define CONFIG_RW_SIZE		(512 * 1024)
+#define CONFIG_RO_MEM_OFF 0
+#define CONFIG_RO_SIZE (128 * 1024)
+#define CONFIG_RW_MEM_OFF (CONFIG_FLASH_SIZE_BYTES / 2)
+#define CONFIG_RW_SIZE (512 * 1024)
 
-#define CONFIG_RO_STORAGE_OFF	0
-#define CONFIG_RW_STORAGE_OFF	0
+#define CONFIG_RO_STORAGE_OFF 0
+#define CONFIG_RW_STORAGE_OFF 0
 
-#define CONFIG_EC_PROTECTED_STORAGE_OFF		0
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE	CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_OFF		CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE					\
-		 (CONFIG_FLASH_SIZE - CONFIG_EC_WRITABLE_STORAGE_OFF)
+#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
+#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE \
+	(CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF)
 
-#define CONFIG_WP_STORAGE_OFF		CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE		CONFIG_EC_PROTECTED_STORAGE_SIZE
+#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
+#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
 
 #undef I2C_PORT_COUNT
-#define I2C_PORT_COUNT	4
+#define I2C_PORT_COUNT 4
 
 /*
  * Cannot use PSTATE:
@@ -58,7 +58,7 @@
 #undef CONFIG_FLASH_PSTATE_BANK
 
 /* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT	150
+#define CONFIG_IRQ_COUNT 150
 
 /* the Cortex-M7 core has 'standard' ARMv7-M caches */
 #define CONFIG_ARMV7M_CACHE
@@ -68,6 +68,9 @@
 #define CONFIG_CHIP_UNCACHED_REGION ahb4
 /* Override MPU attribute settings to match the chip requirements */
 /* Code is Normal memory type / non-shareable / write-through */
-#define MPU_ATTR_FLASH_MEMORY  0x02
+#define MPU_ATTR_FLASH_MEMORY 0x02
 /* SRAM Data is Normal memory type / non-shareable / write-back, write-alloc */
 #define MPU_ATTR_INTERNAL_SRAM 0x0B
+
+/* DFU Address */
+#define STM32_DFU_BASE 0x1ff00000
diff --git a/chip/stm32/config-stm32l100.h b/chip/stm32/config-stm32l100.h
index 579e31cb5b..ec28815525 100644
--- a/chip/stm32/config-stm32l100.h
+++ b/chip/stm32/config-stm32l100.h
@@ -1,12 +1,12 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Memory mapping */
-#define CONFIG_FLASH_SIZE 0x00020000
-#define CONFIG_FLASH_BANK_SIZE  0x1000
-#define CONFIG_FLASH_ERASE_SIZE 0x0100  /* erase bank size */
+#define CONFIG_FLASH_SIZE_BYTES 0x00020000
+#define CONFIG_FLASH_BANK_SIZE 0x1000
+#define CONFIG_FLASH_ERASE_SIZE 0x0100 /* erase bank size */
 
 /*
  * TODO(crosbug.com/p/23805): Technically we can write in word-mode (4 bytes at
@@ -21,8 +21,8 @@
 /* Ideal write size in page-mode */
 #define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0080
 
-#define CONFIG_RAM_BASE         0x20000000
-#define CONFIG_RAM_SIZE         0x00002800
+#define CONFIG_RAM_BASE 0x20000000
+#define CONFIG_RAM_SIZE 0x00002800
 
 /* Number of IRQ vectors on the NVIC */
 #define CONFIG_IRQ_COUNT 45
@@ -37,7 +37,10 @@
 #define CONFIG_STM32L_FAKE_HIBERNATE
 
 /* USB packet ram config */
-#define CONFIG_USB_RAM_BASE        0x40006000
-#define CONFIG_USB_RAM_SIZE        512
+#define CONFIG_USB_RAM_BASE 0x40006000
+#define CONFIG_USB_RAM_SIZE 512
 #define CONFIG_USB_RAM_ACCESS_TYPE uint32_t
 #define CONFIG_USB_RAM_ACCESS_SIZE 4
+
+/* DFU Address */
+#define STM32_DFU_BASE 0x1ff00000
diff --git a/chip/stm32/config-stm32l15x.h b/chip/stm32/config-stm32l15x.h
index afdc241e96..d35b3ccbcf 100644
--- a/chip/stm32/config-stm32l15x.h
+++ b/chip/stm32/config-stm32l15x.h
@@ -1,12 +1,12 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Memory mapping */
-#define CONFIG_FLASH_SIZE 0x00020000
-#define CONFIG_FLASH_BANK_SIZE  0x1000
-#define CONFIG_FLASH_ERASE_SIZE 0x0100  /* erase bank size */
+#define CONFIG_FLASH_SIZE_BYTES 0x00020000
+#define CONFIG_FLASH_BANK_SIZE 0x1000
+#define CONFIG_FLASH_ERASE_SIZE 0x0100 /* erase bank size */
 
 /*
  * TODO(crosbug.com/p/23805): Technically we can write in word-mode (4 bytes at
@@ -21,11 +21,22 @@
 /* Ideal write size in page-mode */
 #define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0080
 
-#define CONFIG_RAM_BASE         0x20000000
-#define CONFIG_RAM_SIZE         0x00004000
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT 45
+#define CONFIG_RAM_BASE 0x20000000
+#define CONFIG_RAM_SIZE 0x00004000
+
+/* Number of IRQ vectors on the NVIC
+ *
+ * Section 10.1 "Nested vectored interrupt controller (NVIC)" states:
+ * 45 maskable interrupt channels in Cat.1 and Cat.2 devices (see Table 49)
+ * 54 maskable interrupt channels in Cat.3 devices (see Table 50) and 57
+ * channels in Cat.4, Cat.5 and Cat.6 devices (see Table 51).
+ *
+ * The only STM32L15 that we support is the "discovery" board is a "Category
+ * 3" device. See Section 1.5 "Product Category definition".
+ *
+ * https://www.st.com/resource/en/reference_manual/cd00240193-stm32l100xx-stm32l151xx-stm32l152xx-and-stm32l162xx-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf
+ */
+#define CONFIG_IRQ_COUNT 54
 
 /* Lots of RAM, so use bigger UART buffer */
 #undef CONFIG_UART_TX_BUF_SIZE
@@ -38,7 +49,10 @@
 #define CONFIG_FLASH_ERASED_VALUE32 0
 
 /* USB packet ram config */
-#define CONFIG_USB_RAM_BASE        0x40006000
-#define CONFIG_USB_RAM_SIZE        512
+#define CONFIG_USB_RAM_BASE 0x40006000
+#define CONFIG_USB_RAM_SIZE 512
 #define CONFIG_USB_RAM_ACCESS_TYPE uint32_t
 #define CONFIG_USB_RAM_ACCESS_SIZE 4
+
+/* DFU Address */
+#define STM32_DFU_BASE 0x1ff00000
diff --git a/chip/stm32/config-stm32l431.h b/chip/stm32/config-stm32l431.h
new file mode 100644
index 0000000000..de3204945a
--- /dev/null
+++ b/chip/stm32/config-stm32l431.h
@@ -0,0 +1,78 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Memory mapping */
+#define CONFIG_FLASH_SIZE_BYTES 0x00040000 /* 256 kB */
+#define CONFIG_FLASH_BANK_SIZE \
+	0x800 /* 2 kB. NOTE: BANK in chrome-ec means page */
+#define CONFIG_FLASH_ERASE_SIZE 0x800 /* 2 KB */
+#define CONFIG_FLASH_WRITE_SIZE 0x8 /* 64 bits */
+
+/* Ideal write size in page-mode */
+#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100 /* 256 (32 double words) */
+
+/*
+ * SRAM1 (48kB) at 0x20000000
+ * SRAM2 (16kB) at 0x10000000 (and aliased at 0x2000C000)
+ * so they are contiguous.
+ */
+#define CONFIG_RAM_BASE 0x20000000
+#define CONFIG_RAM_SIZE 0x00010000 /* 64 kB */
+
+/* Number of IRQ vectors on the NVIC */
+#define CONFIG_IRQ_COUNT 82
+
+/*
+ * STM32L431 flash layout:
+ * - RO image starts at the beginning of flash: sector 0 ~ 61
+ * - PSTATE immediately follows the RO image: sector 62
+ * - RW image starts at 0x1f800: sector 63
+ * - Protected region consists of the RO image + PSTATE: sector 0 ~ 62
+ * - Unprotected region consists of second half of RW image
+ *
+ *                            PSTATE(2KB)
+ *                              |
+ *          (126KB)             v            (130KB)
+ * |<-----Protected Region------>|<------Unprotected Region----->|
+ * |<--------RO image--------->| |<----------RW image----------->|
+ * 0        (124KB)            ^ ^
+ *                             | |
+ *                             | 63(2KB sector)
+ *                             |
+ *                             62
+ *
+ */
+
+/* The EC uses one sector to emulate persistent state */
+#define CONFIG_FLASH_PSTATE
+#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE
+#define CONFIG_FW_PSTATE_OFF (62 * CONFIG_FLASH_BANK_SIZE)
+
+#define CONFIG_RO_MEM_OFF 0
+#define CONFIG_RO_STORAGE_OFF 0
+#define CONFIG_RO_SIZE (62 * CONFIG_FLASH_BANK_SIZE)
+#define CONFIG_RW_MEM_OFF \
+	(CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE + CONFIG_FW_PSTATE_SIZE)
+#define CONFIG_RW_STORAGE_OFF 0
+#define CONFIG_RW_SIZE \
+	(CONFIG_FLASH_SIZE_BYTES - CONFIG_RW_MEM_OFF - CONFIG_RW_STORAGE_OFF)
+
+#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
+#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE \
+	(CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF)
+
+#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
+#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
+
+/* We map each write protect sector to a bank */
+#define PHYSICAL_BANKS 128
+#define WP_BANK_COUNT 63
+#define PSTATE_BANK 62
+#define PSTATE_BANK_COUNT 1
+
+/* DFU Address */
+#define STM32_DFU_BASE 0x1fff0000
diff --git a/chip/stm32/config-stm32l442.h b/chip/stm32/config-stm32l442.h
index e9f3e04c53..b85e9b1454 100644
--- a/chip/stm32/config-stm32l442.h
+++ b/chip/stm32/config-stm32l442.h
@@ -1,24 +1,27 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Memory mapping */
-#define CONFIG_FLASH_SIZE  0x00040000   /* 256 kB */
-#define CONFIG_FLASH_BANK_SIZE  0x800   /* 2 kB */
-#define CONFIG_FLASH_ERASE_SIZE 0x800   /* 2 KB */
-#define CONFIG_FLASH_WRITE_SIZE 0x8     /* 64 bits */
+#define CONFIG_FLASH_SIZE_BYTES 0x00040000 /* 256 kB */
+#define CONFIG_FLASH_BANK_SIZE 0x800 /* 2 kB */
+#define CONFIG_FLASH_ERASE_SIZE 0x800 /* 2 KB */
+#define CONFIG_FLASH_WRITE_SIZE 0x8 /* 64 bits */
 
 /* Ideal write size in page-mode */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100     /* 256 (32 double words) */
+#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100 /* 256 (32 double words) */
 
 /*
  * SRAM1 (48kB) at 0x20000000
  * SRAM2 (16kB) at 0x10000000 (and aliased at 0x2000C000)
  * so they are contiguous.
  */
-#define CONFIG_RAM_BASE         0x20000000
-#define CONFIG_RAM_SIZE         0x00010000      /* 64 kB */
+#define CONFIG_RAM_BASE 0x20000000
+#define CONFIG_RAM_SIZE 0x00010000 /* 64 kB */
 
 /* Number of IRQ vectors on the NVIC */
 #define CONFIG_IRQ_COUNT 82
+
+/* DFU Address */
+#define STM32_DFU_BASE 0x1fff0000
diff --git a/chip/stm32/config-stm32l476.h b/chip/stm32/config-stm32l476.h
index 9f6b35b8b1..00a02e0ff9 100644
--- a/chip/stm32/config-stm32l476.h
+++ b/chip/stm32/config-stm32l476.h
@@ -1,20 +1,23 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Memory mapping */
-#define CONFIG_FLASH_SIZE 0x00100000	/* 1 MB */
-#define CONFIG_FLASH_BANK_SIZE  0x800	/* 2 kB */
-#define CONFIG_FLASH_ERASE_SIZE 0x800	/* 2 KB */
-#define CONFIG_FLASH_WRITE_SIZE 0x8	/* 64 bits (without 8 bits ECC) */
+#define CONFIG_FLASH_SIZE_BYTES 0x00100000 /* 1 MB */
+#define CONFIG_FLASH_BANK_SIZE 0x800 /* 2 kB */
+#define CONFIG_FLASH_ERASE_SIZE 0x800 /* 2 KB */
+#define CONFIG_FLASH_WRITE_SIZE 0x8 /* 64 bits (without 8 bits ECC) */
 
 /* Ideal write size in page-mode */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100	/* 256 (32 double words) */
+#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100 /* 256 (32 double words) */
 
-#define CONFIG_RAM_BASE         0x20000000
+#define CONFIG_RAM_BASE 0x20000000
 /* Only using SRAM1. SRAM2 (32 KB) is ignored. */
-#define CONFIG_RAM_SIZE         0x00018000	/* 96 kB */
+#define CONFIG_RAM_SIZE 0x00018000 /* 96 kB */
 
 /* Number of IRQ vectors on the NVIC */
 #define CONFIG_IRQ_COUNT 82
+
+/* DFU Address */
+#define STM32_DFU_BASE 0x1fff0000
diff --git a/chip/stm32/config-stm32l552xe.h b/chip/stm32/config-stm32l552xe.h
new file mode 100644
index 0000000000..ba11b7f098
--- /dev/null
+++ b/chip/stm32/config-stm32l552xe.h
@@ -0,0 +1,39 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Memory mapping */
+#define CONFIG_FLASH_SIZE_BYTES 0x00080000 /* 512 kB */
+#define CONFIG_FLASH_BANK_SIZE 0x800 /* 2 kB */
+#define CONFIG_FLASH_ERASE_SIZE 0x800 /* 2 KB */
+#define CONFIG_FLASH_WRITE_SIZE 0x8 /* 64 bits */
+
+/* Ideal write size in page-mode */
+#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100 /* 256 (32 double words) */
+
+/*
+ * SRAM1 (48kB) at 0x20000000
+ * SRAM2 (16kB) at 0x10000000 (and aliased at 0x2000C000)
+ * so they are contiguous.
+ */
+#define CONFIG_RAM_BASE 0x20000000
+#define CONFIG_RAM_SIZE 0x00010000 /* 64 kB */
+
+/* Number of IRQ vectors on the NVIC */
+#define CONFIG_IRQ_COUNT 109
+
+/* USB packet ram config */
+#define CONFIG_USB_RAM_BASE 0x4000D800
+#define CONFIG_USB_RAM_SIZE 1024
+#define CONFIG_USB_RAM_ACCESS_TYPE uint16_t
+#define CONFIG_USB_RAM_ACCESS_SIZE 2
+
+#undef I2C_PORT_COUNT
+#define I2C_PORT_COUNT 4
+
+/* Number of DMA channels supported (8 channels each for DMA1 and DMA2) */
+#define DMAC_COUNT 16
+
+/* DFU Address */
+#define STM32_DFU_BASE 0x0bf90000
diff --git a/chip/stm32/config_chip.h b/chip/stm32/config_chip.h
index 35acf94c82..f6f211f4a5 100644
--- a/chip/stm32/config_chip.h
+++ b/chip/stm32/config_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,12 +10,19 @@
 /* CPU core BFD configuration */
 #include "core/cortex-m0/config_core.h"
 /* IRQ priorities */
-#define STM32_IRQ_EXT0_1_PRIORITY	1
-#define STM32_IRQ_EXT2_3_PRIORITY	1
-#define STM32_IRQ_EXTI4_15_PRIORITY	1
+#define STM32_IRQ_EXT0_1_PRIORITY 1
+#define STM32_IRQ_EXT2_3_PRIORITY 1
+#define STM32_IRQ_EXTI4_15_PRIORITY 1
 #else
 /* CPU core BFD configuration */
 #include "core/cortex-m/config_core.h"
+#define STM32_IRQ_EXTI0_PRIORITY 1
+#define STM32_IRQ_EXTI1_PRIORITY 1
+#define STM32_IRQ_EXTI2_PRIORITY 1
+#define STM32_IRQ_EXTI3_PRIORITY 1
+#define STM32_IRQ_EXTI4_PRIORITY 1
+#define STM32_IRQ_EXTI9_5_PRIORITY 1
+#define STM32_IRQ_EXTI15_10_PRIORITY 1
 #endif
 
 /* Default to UART 1 for EC console */
@@ -38,6 +45,8 @@
 #include "config-stm32l100.h"
 #elif defined(CHIP_VARIANT_STM32L442)
 #include "config-stm32l442.h"
+#elif defined(CHIP_VARIANT_STM32L552XE)
+#include "config-stm32l552xe.h"
 #elif defined(CHIP_VARIANT_STM32F76X)
 #include "config-stm32f76x.h"
 #elif defined(CHIP_FAMILY_STM32F4)
@@ -61,6 +70,10 @@
 #include "config-stm32h7x3.h"
 #elif defined(CHIP_VARIANT_STM32G431XB)
 #include "config-stm32g41xb.h"
+#elif defined(CHIP_VARIANT_STM32G473XC)
+#include "config-stm32g473xc.h"
+#elif defined(CHIP_VARIANT_STM32L431X)
+#include "config-stm32l431.h"
 #else
 #error "Unsupported chip variant"
 #endif
@@ -74,10 +87,9 @@
 /* Program is run directly from storage */
 #define CONFIG_MAPPED_STORAGE_BASE CONFIG_PROGRAM_MEMORY_BASE
 
-#if !defined(CHIP_FAMILY_STM32F4) && \
-	!defined(CHIP_FAMILY_STM32F7) && \
-	!defined(CHIP_FAMILY_STM32H7) && \
-	!defined(CHIP_VARIANT_STM32F09X)
+#if !defined(CHIP_FAMILY_STM32F4) && !defined(CHIP_FAMILY_STM32F7) &&        \
+	!defined(CHIP_FAMILY_STM32H7) && !defined(CHIP_VARIANT_STM32F09X) && \
+	!defined(CHIP_VARIANT_STM32L431X)
 /* Compute the rest of the flash params from these */
 #include "config_std_internal_flash.h"
 #endif
@@ -118,7 +130,7 @@
 
 /* Interval between HOOK_TICK notifications */
 #define HOOK_TICK_INTERVAL_MS 500
-#define HOOK_TICK_INTERVAL    (HOOK_TICK_INTERVAL_MS * MSEC)
+#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC)
 
 /*
  * Use a timer to print a watchdog warning event before the actual watchdog
@@ -128,13 +140,13 @@
 #define CONFIG_WATCHDOG_HELP
 
 /* Use DMA */
-#define CONFIG_DMA
+#define CONFIG_DMA_CROS
 
 /* STM32 features RTC (optional feature) */
 #define CONFIG_RTC
 
 /* Number of peripheral request signals per DMA channel */
-#define STM32_DMA_PERIPHERALS_PER_CHANNEL	4
+#define STM32_DMA_PERIPHERALS_PER_CHANNEL 4
 
 /*
  * Use DMA for UART transmit for all platforms.  DMA for UART receive is
@@ -151,13 +163,13 @@
 /* Chip needs to do custom pre-init */
 #define CONFIG_CHIP_PRE_INIT
 
-#define GPIO_NAME_BY_PIN(port, index) #port#index
+#define GPIO_NAME_BY_PIN(port, index) #port #index
 #define GPIO_PIN(port, index) GPIO_##port, BIT(index)
 #define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m)
 
-/* Prescaler values for PLL. Currently used only by STM32L476. */
-#define STM32_PLLM	0
-#define STM32_PLLN	0
-#define STM32_PLLR	0
+/* Prescaler values for PLL. Currently used only by STM32L476 and STM32L431. */
+#define STM32_PLLM 1
+#define STM32_PLLN 1
+#define STM32_PLLR 1
 
 #endif /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/chip/stm32/crc_hw.h b/chip/stm32/crc_hw.h
index 2a50d5760e..495af2fb98 100644
--- a/chip/stm32/crc_hw.h
+++ b/chip/stm32/crc_hw.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,8 +17,8 @@ static inline void crc32_init(void)
 	/* Delay 1 AHB clock cycle after the clock is enabled */
 	clock_wait_bus_cycles(BUS_AHB, 1);
 	/* reset CRC state */
-	STM32_CRC_CR = STM32_CRC_CR_RESET | STM32_CRC_CR_REV_OUT
-		     | STM32_CRC_CR_REV_IN_WORD;
+	STM32_CRC_CR = STM32_CRC_CR_RESET | STM32_CRC_CR_REV_OUT |
+		       STM32_CRC_CR_REV_IN_WORD;
 	while (STM32_CRC_CR & 1)
 		;
 }
diff --git a/chip/stm32/debug_printf.c b/chip/stm32/debug_printf.c
index c4e151692c..3713d28d26 100644
--- a/chip/stm32/debug_printf.c
+++ b/chip/stm32/debug_printf.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,8 +27,6 @@ static int debug_txchar(void *context, int c)
 	return 0;
 }
 
-
-
 void debug_printf(const char *format, ...)
 {
 	va_list args;
@@ -102,8 +100,8 @@ void uart_init(void)
 	STM32_USART_BRR(UARTN_BASE) =
 		DIV_ROUND_NEAREST(CPU_CLOCK, CONFIG_UART_BAUD_RATE);
 	/* UART enabled, 8 Data bits, oversampling x16, no parity */
-	STM32_USART_CR1(UARTN_BASE) =
-		STM32_USART_CR1_UE | STM32_USART_CR1_TE | STM32_USART_CR1_RE;
+	STM32_USART_CR1(UARTN_BASE) = STM32_USART_CR1_UE | STM32_USART_CR1_TE |
+				      STM32_USART_CR1_RE;
 	/* 1 stop bit, no fancy stuff */
 	STM32_USART_CR2(UARTN_BASE) = 0x0000;
 	/* DMA disabled, special modes disabled, error interrupt disabled */
diff --git a/chip/stm32/debug_printf.h b/chip/stm32/debug_printf.h
index 6091cfc7fc..efd74d40b9 100644
--- a/chip/stm32/debug_printf.h
+++ b/chip/stm32/debug_printf.h
@@ -1,17 +1,17 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 /* Synchronous UART debug printf */
 
-#ifndef __CROS_EC_DEBUG_H
-#define __CROS_EC_DEBUG_H
+#ifndef __CROS_EC_DEBUG_PRINTF_H
+#define __CROS_EC_DEBUG_PRINTF_H
 
 #ifdef CONFIG_DEBUG_PRINTF
-__attribute__((__format__(__printf__, 1, 2)))
-void debug_printf(const char *format, ...);
+__attribute__((__format__(__printf__, 1, 2))) void
+debug_printf(const char *format, ...);
 #else
 #define debug_printf(...)
 #endif
 
-#endif /* __CROS_EC_DEBUG_H */
+#endif /* __CROS_EC_DEBUG_PRINTF_H */
diff --git a/chip/stm32/dfu_bootmanager_main.c b/chip/stm32/dfu_bootmanager_main.c
new file mode 100644
index 0000000000..cec747e762
--- /dev/null
+++ b/chip/stm32/dfu_bootmanager_main.c
@@ -0,0 +1,212 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * DFU Boot Manager Main for STM32
+ *
+ * When the Boot Manager Main is enabled, the RO application skips the
+ * common runtime and setup. This reduces the flash size and avoids clock,
+ * interrupt, and setup steps which conflict with the built in Boot Loaders
+ * while minimizing the Flash Size.
+ *
+ * The Boot Manager Main will perform self checks of the Flash and backup
+ * memory. Based on these results it will boot into the DFU or RW Application.
+ */
+
+#include "clock.h"
+#include "dfu_bootmanager_shared.h"
+#include "flash.h"
+#include "registers.h"
+#include "task.h"
+
+#ifdef CONFIG_DFU_BOOTMANAGER_MAX_REBOOT_COUNT
+#if CONFIG_DFU_BOOTMANAGER_MAX_REBOOT_COUNT <= 0 || \
+	CONFIG_DFU_BOOTMANAGER_MAX_REBOOT_COUNT > DFU_BOOTMANAGER_VALUE_DFU
+#error "Max reboot count is out of range"
+#endif
+#endif /* CONFIG_DFU_BOOTMANAGER_MAX_REBOOT_COUNT */
+
+/*
+ * Checks if the RW region is valid by reading the first 8 bytes of flash, it
+ * should not start with an erased block.
+ *
+ * The DFU boot manager should not jump into the RW region if it contains
+ * invalid code as the EC is be unstable. A check will be performed to validate
+ * the start of the RW region to verify that it contains valid data.
+ * DFU programmers should erase this section of flash first and at this point,
+ * the EC will no longer be able to jump into the RW application.
+ *
+ * The normal DFU programming sequence programming will work, but by
+ * splitting into the following sequence we can protect against additional
+ * failures.
+ *
+ * 1. Erase the first RW flash section. This will lock the EC out of RW.
+ * 2. Update the remaining flash. Erase, program, and read back flash to
+ *      to verify the operation was successful. Regions of the flash which
+ *      are difficult to repair if an error occurs should be programmed next.
+ * 3. Program the first RW flash section and exit DFU mode if verification is
+ *      successful.
+ *
+ * @return 1 if erased, 0 if not erased
+ */
+static int rw_is_empty(void)
+{
+	if (IS_ENABLED(CONFIG_FLASH_CROS))
+		return crec_flash_is_erased(CONFIG_RW_MEM_OFF, 8);
+	/* No flash support, we cannot tell.  Assume not empty. */
+	return 0;
+}
+
+/*
+ * Reads the backup registers. This will trigger a jump to DFU if either
+ * the application has requested it or if the reboot counter indicates
+ * the device is likely in a bad state. A counter recording the number
+ * of reboots will be incremented.
+ *
+ * @returns True if the backup memory region indicates we should boot into DFU.
+ */
+static bool backup_boot_checks(void)
+{
+	uint8_t value;
+
+	if (dfu_bootmanager_backup_read(&value)) {
+		/* Value stored is not valid, set it to a valid value. */
+		dfu_bootmanager_backup_write(DFU_BOOTMANAGER_VALUE_CLEAR);
+		return false;
+	}
+	if (value == DFU_BOOTMANAGER_VALUE_DFU)
+		return true;
+#ifdef CONFIG_DFU_BOOTMANAGER_MAX_REBOOT_COUNT
+	if (value >= CONFIG_DFU_BOOTMANAGER_MAX_REBOOT_COUNT)
+		return true;
+	/* Increment the reboot loop counter. */
+	value++;
+	dfu_bootmanager_backup_write(value);
+#endif /* CONFIG_DFU_BOOTMANAGER_MAX_REBOOT_COUNT */
+	return false;
+}
+
+/*
+ * Performs the minimal set of initialization required for the boot manager.
+ * The main application region or DFU boot loader have different prerequisites,
+ * any configurations that are enabled either need to be benign with both
+ * images or disabled prior to the jumps.
+ */
+static void dfu_bootmanager_init(void)
+{
+	/* enable clock on Power module */
+#ifndef CHIP_FAMILY_STM32H7
+#if defined(CHIP_FAMILY_STM32L4) || defined(CHIP_FAMILY_STM32L5)
+	STM32_RCC_APB1ENR1 |= STM32_RCC_PWREN;
+#else
+	STM32_RCC_APB1ENR |= STM32_RCC_PWREN;
+#endif
+#endif
+#if defined(CHIP_FAMILY_STM32F4)
+	/* enable backup registers */
+	STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_BKPSRAMEN;
+#elif defined(CHIP_FAMILY_STM32H7)
+	/* enable backup registers */
+	STM32_RCC_AHB4ENR |= BIT(28);
+#elif defined(CHIP_FAMILY_STM32L4) || defined(CHIP_FAMILY_STM32L5)
+	/* enable RTC APB clock */
+	STM32_RCC_APB1ENR1 |= STM32_RCC_APB1ENR1_RTCAPBEN;
+#else
+	/* enable backup registers */
+	STM32_RCC_APB1ENR |= BIT(27);
+#endif
+	/* Delay 1 APB clock cycle after the clock is enabled */
+	clock_wait_bus_cycles(BUS_APB, 1);
+	/* Enable access to RCC CSR register and RTC backup registers */
+	STM32_PWR_CR |= BIT(8);
+}
+
+/*
+ * Load stack pointer and reset vector from an ARM vector table, and jump.
+ */
+static void jump_to_arm_reset_vector(uint32_t addr)
+{
+	/*
+	 * The first 32-bit entry ARM vector table is the initial value of the
+	 * stack pointer, the second entry is the reset vector.
+	 */
+	asm("mov r1, %0\n"
+	    /* Load stack pointer */
+	    "ldr r0, [r1, 0]\n"
+	    "msr msp, r0\n"
+	    /*
+	     * Memory barrier to ensure subsequent instructions uses modified
+	     * stack pointer.
+	     */
+	    "isb\n"
+	    /* Load reset vector */
+	    "ldr r0, [r1, 4]\n"
+	    /* Jump without saving return address (would modify msp) */
+	    "bx r0\n"
+	    : /* no outputs */
+	    : "r"(addr)
+	    :);
+}
+
+static void jump_to_rw(void)
+{
+	jump_to_arm_reset_vector(CONFIG_PROGRAM_MEMORY_BASE +
+				 CONFIG_RW_MEM_OFF);
+}
+
+static void jump_to_dfu(void)
+{
+	/* Clear the scratchpad. */
+	dfu_bootmanager_backup_write(DFU_BOOTMANAGER_VALUE_CLEAR);
+
+	jump_to_arm_reset_vector(STM32_DFU_BASE);
+}
+
+/*
+ * DFU Boot Manager main. It'll check if the RW region is not fully programmed
+ * or if the backup memory indicates we should reboot into DFU.
+ */
+int main(void)
+{
+	dfu_bootmanager_init();
+
+	if (rw_is_empty() || backup_boot_checks())
+		jump_to_dfu();
+	jump_to_rw();
+
+	return 0;
+}
+
+/*
+ * The RW application will replace the vector table and exception handlers
+ * shortly after the jump. If the application is corrupt and fails before
+ * this, the only action that can be done is jumping into DFU mode.
+ */
+void __keep exception_panic(void)
+{
+	dfu_bootmanager_enter_dfu();
+}
+
+/*
+ * Function stubs which are required by bkpdata.c and system.c:
+ * Interrupts are always disabled in the Boot Manager so we do not
+ * need to worry about concurrent access.
+ */
+
+void task_clear_pending_irq(int irq)
+{
+}
+void interrupt_disable(void)
+{
+}
+void mutex_lock(mutex_t *mtx)
+{
+}
+void mutex_unlock(mutex_t *mtx)
+{
+}
+
+bool in_interrupt_context(void)
+{
+	return false;
+}
diff --git a/chip/stm32/dfu_bootmanager_shared.c b/chip/stm32/dfu_bootmanager_shared.c
new file mode 100644
index 0000000000..de8edcff5d
--- /dev/null
+++ b/chip/stm32/dfu_bootmanager_shared.c
@@ -0,0 +1,52 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * DFU Boot Manager shared utilities for STM32
+ */
+
+#include "bkpdata.h"
+#include "clock.h"
+#include "dfu_bootmanager_shared.h"
+#include "flash.h"
+#include "registers.h"
+#include "task.h"
+
+/*
+ * The Servo platforms do not have any free backup regions. The scratchpad
+ * is only with the console command scratchpad and on some of the tests so
+ * we'll use the scratchpad region.
+ */
+#ifdef CONFIG_CMD_SCRATCHPAD
+#error "The scratchpad is used, define a backup region for the DFU fields."
+#endif /* CONFIG_CMD_SCRATCHPAD */
+
+int dfu_bootmanager_enter_dfu(void)
+{
+	dfu_bootmanager_backup_write(DFU_BOOTMANAGER_VALUE_DFU);
+	system_reset(0);
+	return 0;
+}
+
+void dfu_bootmanager_clear(void)
+{
+	dfu_bootmanager_backup_write(DFU_BOOTMANAGER_VALUE_CLEAR);
+}
+
+void dfu_bootmanager_backup_write(uint8_t value)
+{
+	uint16_t data = DFU_BOOTMANAGER_VALID_CHECK | value;
+
+	bkpdata_write(BKPDATA_INDEX_SCRATCHPAD, data);
+}
+
+int dfu_bootmanager_backup_read(uint8_t *value)
+{
+	uint16_t data = bkpdata_read(BKPDATA_INDEX_SCRATCHPAD);
+	uint16_t valid_check = data & DFU_BOOTMANAGER_VALID_MASK;
+
+	*value = (uint8_t)(data & DFU_BOOTMANAGER_VALUE_MASK);
+	if (valid_check != DFU_BOOTMANAGER_VALID_CHECK)
+		return EC_ERROR_UNKNOWN;
+	return EC_SUCCESS;
+}
diff --git a/chip/stm32/dfu_bootmanager_shared.h b/chip/stm32/dfu_bootmanager_shared.h
new file mode 100644
index 0000000000..df920f16a5
--- /dev/null
+++ b/chip/stm32/dfu_bootmanager_shared.h
@@ -0,0 +1,62 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * DFU Boot Manager shared utilities for STM32
+ *
+ * These of utilities required by the Boot Manager Main and RW Application.
+ * These allow the systems to start the sequence to enter DFU, clear the
+ * state, and access the backup registers.
+ */
+
+#ifndef __DFU_BOOTMANAGER_SHARED_H
+#define __DFU_BOOTMANAGER_SHARED_H
+
+#include "common.h"
+
+/* Registers to validate the backup memory region. */
+#define DFU_BOOTMANAGER_VALUE_MASK 0x00FF
+#define DFU_BOOTMANAGER_VALID_MASK 0xFF00
+#define DFU_BOOTMANAGER_VALID_CHECK 0xAA00
+
+#define DFU_BOOTMANAGER_VALUE_CLEAR 0
+#define DFU_BOOTMANAGER_VALUE_DFU UINT8_MAX
+
+/*
+ * Reset and enter the DFU mode.
+ *
+ * The system will set flags to the backup memory to enter DFU and issue
+ * a reset. The Boot Manager will send the system to DFU mode.
+ *
+ * @return           EC_SUCCESS, or non-zero if error.
+ */
+int dfu_bootmanager_enter_dfu(void);
+
+/*
+ * Clear the DFU Boot Manager backup memory state.
+ *
+ * If the CONFIG_DFU_BOOTMANAGER_MAX_REBOOT_COUNT setting is enabled, this
+ * allows the RW application to clear the counter to indicate the application
+ * is working as expected.
+ */
+void dfu_bootmanager_clear(void);
+
+/*
+ * Write the value to the backup registers and sets the bitmasks
+ * indicating the field is valid.
+ *
+ * @param value  New value to store.
+ */
+void dfu_bootmanager_backup_write(uint8_t value);
+
+/*
+ * Reads the backup registers and performs validation. The value stored
+ * within the VALUE_MASK is returned and the status code indicates
+ * if the valid check passed.
+ *
+ * @param value[out] Value stored within the DFU_BOOTMANAGER_VALUE_MASK
+ * @return           EC_SUCCESS, or non-zero if validation failed.
+ */
+int dfu_bootmanager_backup_read(uint8_t *value);
+
+#endif /* __DFU_BOOTMANAGER_SHARED_H */
diff --git a/chip/stm32/dma-stm32f4.c b/chip/stm32/dma-stm32f4.c
index abb33befda..15fb0f28ef 100644
--- a/chip/stm32/dma-stm32f4.c
+++ b/chip/stm32/dma-stm32f4.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,15 +14,15 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_DMA, outstr)
-#define CPRINTF(format, args...) cprintf(CC_DMA, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_DMA, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_DMA, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_DMA, format, ##args)
 
 stm32_dma_regs_t *STM32_DMA_REGS[] = { STM32_DMA1_REGS, STM32_DMA2_REGS };
 
 /* Callback data to use when IRQ fires */
 static struct {
-	void (*cb)(void *);	/* Callback function to call */
-	void *cb_data;		/* Callback data for callback function */
+	void (*cb)(void *); /* Callback function to call */
+	void *cb_data; /* Callback data for callback function */
 } dma_irq[STM32_DMAS_TOTAL_COUNT];
 
 /**
@@ -90,8 +90,8 @@ void dma_disable_all(void)
  * @param memory	Pointer to memory address for receive/transmit
  * @param flags		DMA flags for the control register.
  */
-static void prepare_stream(enum dma_channel stream, unsigned count,
-		void *periph, void *memory, unsigned flags)
+static void prepare_stream(enum dma_channel stream, unsigned int count,
+			   void *periph, void *memory, unsigned int flags)
 {
 	stm32_dma_stream_t *dma_stream = dma_get_channel(stream);
 	uint32_t ccr = STM32_DMA_CCR_PL_VERY_HIGH;
@@ -120,7 +120,7 @@ void dma_go(stm32_dma_stream_t *stream)
 	stream->scr |= STM32_DMA_CCR_EN;
 }
 
-void dma_prepare_tx(const struct dma_option *option, unsigned count,
+void dma_prepare_tx(const struct dma_option *option, unsigned int count,
 		    const void *memory)
 {
 	/*
@@ -128,18 +128,18 @@ void dma_prepare_tx(const struct dma_option *option, unsigned count,
 	 * we're preparing the stream for transmit.
 	 */
 	prepare_stream(option->channel, count, option->periph, (void *)memory,
-			STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR_M2P |
-			option->flags);
+		       STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR_M2P |
+			       option->flags);
 }
 
-void dma_start_rx(const struct dma_option *option, unsigned count,
+void dma_start_rx(const struct dma_option *option, unsigned int count,
 		  void *memory)
 {
 	stm32_dma_stream_t *stream = dma_get_channel(option->channel);
 
 	prepare_stream(option->channel, count, option->periph, memory,
-			STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR_P2M |
-			option->flags);
+		       STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR_P2M |
+			       option->flags);
 	dma_go(stream);
 }
 
@@ -176,10 +176,8 @@ void dma_dump(enum dma_channel stream)
 	CPRINTF("scr=%x, sndtr=%x, spar=%x, sm0ar=%x, sfcr=%x\n",
 		dma_stream->scr, dma_stream->sndtr, dma_stream->spar,
 		dma_stream->sm0ar, dma_stream->sfcr);
-	CPRINTF("stream %d, isr=%x, ifcr=%x\n",
-		stream,
-		STM32_DMA_GET_ISR(stream),
-		STM32_DMA_GET_IFCR(stream));
+	CPRINTF("stream %d, isr=%x, ifcr=%x\n", stream,
+		STM32_DMA_GET_ISR(stream), STM32_DMA_GET_IFCR(stream));
 }
 
 void dma_check(enum dma_channel stream, char *buf)
@@ -206,7 +204,7 @@ void dma_test(enum dma_channel stream)
 	stm32_dma_stream_t *dma_stream = dma_get_channel(stream);
 	uint32_t ctrl;
 	char periph[32], memory[32];
-	unsigned count = sizeof(periph);
+	unsigned int count = sizeof(periph);
 	int i;
 
 	memset(memory, '\0', sizeof(memory));
@@ -218,7 +216,7 @@ void dma_test(enum dma_channel stream)
 	dma_stream->spar = (uint32_t)periph;
 	dma_stream->sm0ar = (uint32_t)memory;
 	dma_stream->sndtr = count;
-	dma_stream->sfcr  &= ~STM32_DMA_SFCR_DMDIS;
+	dma_stream->sfcr &= ~STM32_DMA_SFCR_DMDIS;
 	ctrl = STM32_DMA_CCR_PL_MEDIUM;
 	dma_stream->scr = ctrl;
 
@@ -261,7 +259,7 @@ static inline void _dma_wake_callback(void *cb_data)
 	task_id_t id = (task_id_t)(int)cb_data;
 
 	if (id != TASK_ID_INVALID)
-		task_set_event(id, TASK_EVENT_DMA_TC, 0);
+		task_set_event(id, TASK_EVENT_DMA_TC);
 }
 
 void dma_enable_tc_interrupt(enum dma_channel stream)
@@ -300,17 +298,17 @@ void dma_clear_isr(enum dma_channel stream)
 }
 
 #ifdef CONFIG_DMA_DEFAULT_HANDLERS
-#define STM32_DMA_IDX(dma, x)   CONCAT4(STM32_DMA, dma, _STREAM, x)
-#define STM32_DMA_FCT(dma, x)   CONCAT4(dma_, dma, _event_interrupt_stream_, x)
-#define DECLARE_DMA_IRQ(dma, x) \
-	void STM32_DMA_FCT(dma, x)(void) \
-	{ \
-		dma_clear_isr(STM32_DMA_IDX(dma, x)); \
-		if (dma_irq[STM32_DMA_IDX(dma, x)].cb != NULL) \
-			(*dma_irq[STM32_DMA_IDX(dma, x)].cb) \
-				(dma_irq[STM32_DMA_IDX(dma, x)].cb_data); \
-	} \
-	DECLARE_IRQ(CONCAT4(STM32_IRQ_DMA, dma, _STREAM, x), \
+#define STM32_DMA_IDX(dma, x) CONCAT4(STM32_DMA, dma, _STREAM, x)
+#define STM32_DMA_FCT(dma, x) CONCAT4(dma_, dma, _event_interrupt_stream_, x)
+#define DECLARE_DMA_IRQ(dma, x)                                          \
+	static void STM32_DMA_FCT(dma, x)(void)                          \
+	{                                                                \
+		dma_clear_isr(STM32_DMA_IDX(dma, x));                    \
+		if (dma_irq[STM32_DMA_IDX(dma, x)].cb != NULL)           \
+			(*dma_irq[STM32_DMA_IDX(dma, x)].cb)(            \
+				dma_irq[STM32_DMA_IDX(dma, x)].cb_data); \
+	}                                                                \
+	DECLARE_IRQ(CONCAT4(STM32_IRQ_DMA, dma, _STREAM, x),             \
 		    STM32_DMA_FCT(dma, x), 1);
 
 DECLARE_DMA_IRQ(1, 0);
@@ -331,4 +329,3 @@ DECLARE_DMA_IRQ(2, 6);
 DECLARE_DMA_IRQ(2, 7);
 
 #endif /* CONFIG_DMA_DEFAULT_HANDLERS */
-
diff --git a/chip/stm32/dma.c b/chip/stm32/dma.c
index a2ed6ca3cb..fbf0d59627 100644
--- a/chip/stm32/dma.c
+++ b/chip/stm32/dma.c
@@ -1,8 +1,9 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "builtin/assert.h"
 #include "clock.h"
 #include "common.h"
 #include "console.h"
@@ -15,15 +16,14 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_DMA, outstr)
-#define CPRINTF(format, args...) cprintf(CC_DMA, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_DMA, format, ##args)
 
 /* Callback data to use when IRQ fires */
 static struct {
-	void (*cb)(void *);	/* Callback function to call */
-	void *cb_data;		/* Callback data for callback function */
+	void (*cb)(void *); /* Callback function to call */
+	void *cb_data; /* Callback data for callback function */
 } dma_irq[STM32_DMAC_COUNT];
 
-
 /**
  * Return the IRQ for the DMA channel
  *
@@ -36,15 +36,25 @@ static int dma_get_irq(enum dma_channel channel)
 	if (channel == STM32_DMAC_CH1)
 		return STM32_IRQ_DMA_CHANNEL_1;
 
-	return channel > STM32_DMAC_CH3 ?
-		STM32_IRQ_DMA_CHANNEL_4_7 :
-		STM32_IRQ_DMA_CHANNEL_2_3;
+	return channel > STM32_DMAC_CH3 ? STM32_IRQ_DMA_CHANNEL_4_7 :
+					  STM32_IRQ_DMA_CHANNEL_2_3;
+#elif defined(CHIP_FAMILY_STM32L4)
+	if (channel < STM32_DMAC_PER_CTLR)
+		return STM32_IRQ_DMA_CHANNEL_1 + channel;
+	else {
+		if (channel <= STM32_DMAC_CH13)
+			return STM32_IRQ_DMA2_CHANNEL1 +
+			       (channel - STM32_DMAC_PER_CTLR);
+		else
+			return STM32_IRQ_DMA2_CHANNEL6 +
+			       (channel - STM32_DMAC_PER_CTLR - 5);
+	}
 #else
 	if (channel < STM32_DMAC_PER_CTLR)
 		return STM32_IRQ_DMA_CHANNEL_1 + channel;
 	else
 		return STM32_IRQ_DMA2_CHANNEL1 +
-			(channel - STM32_DMAC_PER_CTLR);
+		       (channel - STM32_DMAC_PER_CTLR);
 #endif
 }
 
@@ -99,6 +109,7 @@ void dma_disable_all(void)
 
 	for (ch = 0; ch < STM32_DMAC_COUNT; ch++) {
 		stm32_dma_chan_t *chan = dma_get_channel(ch);
+
 		chan->ccr &= ~STM32_DMA_CCR_EN;
 	}
 }
@@ -114,8 +125,8 @@ void dma_disable_all(void)
  *				STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR for tx
  *				0 for rx
  */
-static void prepare_channel(enum dma_channel channel, unsigned count,
-		void *periph, void *memory, unsigned flags)
+static void prepare_channel(enum dma_channel channel, unsigned int count,
+			    void *periph, void *memory, unsigned int flags)
 {
 	stm32_dma_chan_t *chan = dma_get_channel(channel);
 	uint32_t ccr = STM32_DMA_CCR_PL_VERY_HIGH;
@@ -141,7 +152,7 @@ void dma_go(stm32_dma_chan_t *chan)
 	chan->ccr |= STM32_DMA_CCR_EN;
 }
 
-void dma_prepare_tx(const struct dma_option *option, unsigned count,
+void dma_prepare_tx(const struct dma_option *option, unsigned int count,
 		    const void *memory)
 {
 	/*
@@ -149,14 +160,14 @@ void dma_prepare_tx(const struct dma_option *option, unsigned count,
 	 * we're preparing the channel for transmit.
 	 */
 	prepare_channel(option->channel, count, option->periph, (void *)memory,
-			STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR |
-			option->flags);
+			STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR | option->flags);
 }
 
-void dma_start_rx(const struct dma_option *option, unsigned count,
+void dma_start_rx(const struct dma_option *option, unsigned int count,
 		  void *memory)
 {
 	stm32_dma_chan_t *chan = dma_get_channel(option->channel);
+
 	prepare_channel(option->channel, count, option->periph, memory,
 			STM32_DMA_CCR_MINC | option->flags);
 	dma_go(chan);
@@ -178,10 +189,9 @@ void dma_dump(enum dma_channel channel)
 	stm32_dma_regs_t *dma = STM32_DMA_REGS(channel);
 	stm32_dma_chan_t *chan = dma_get_channel(channel);
 
-	CPRINTF("ccr=%x, cndtr=%x, cpar=%x, cmar=%x\n", chan->ccr,
-		chan->cndtr, chan->cpar, chan->cmar);
-	CPRINTF("chan %d, isr=%x, ifcr=%x\n",
-		channel,
+	CPRINTF("ccr=%x, cndtr=%x, cpar=%x, cmar=%x\n", chan->ccr, chan->cndtr,
+		chan->cpar, chan->cmar);
+	CPRINTF("chan %d, isr=%x, ifcr=%x\n", channel,
 		(dma->isr >> ((channel % STM32_DMAC_PER_CTLR) * 4)) & 0xf,
 		(dma->ifcr >> ((channel % STM32_DMAC_PER_CTLR) * 4)) & 0xf);
 }
@@ -211,7 +221,7 @@ void dma_test(enum dma_channel channel)
 	stm32_dma_chan_t *chan = dma_get_channel(channel);
 	uint32_t ctrl;
 	char periph[16], memory[16];
-	unsigned count = sizeof(periph);
+	unsigned int count = sizeof(periph);
 	int i;
 
 	memset(memory, '\0', sizeof(memory));
@@ -225,11 +235,12 @@ void dma_test(enum dma_channel channel)
 	ctrl = STM32_DMA_CCR_PL_MEDIUM;
 	chan->ccr = ctrl;
 
-	ctrl |= STM32_DMA_CCR_MINC; /* | STM32_DMA_CCR_DIR */;
+	ctrl |= STM32_DMA_CCR_MINC; /* | STM32_DMA_CCR_DIR */
+	;
 	ctrl |= STM32_DMA_CCR_MEM2MEM;
 	ctrl |= STM32_DMA_CCR_PINC;
-/*	ctrl |= STM32_DMA_CCR_MSIZE_32_BIT; */
-/*	ctrl |= STM32_DMA_CCR_PSIZE_32_BIT; */
+	/*	ctrl |= STM32_DMA_CCR_MSIZE_32_BIT; */
+	/*	ctrl |= STM32_DMA_CCR_PSIZE_32_BIT; */
 	chan->ccr = ctrl;
 	chan->ccr = ctrl | STM32_DMA_CCR_EN;
 
@@ -242,10 +253,12 @@ void dma_test(enum dma_channel channel)
 void dma_init(void)
 {
 #if defined(CHIP_FAMILY_STM32L4)
-	STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_DMA1EN|STM32_RCC_AHB1ENR_DMA2EN;
-#elif defined(CHIP_FAMILY_STM32G4)
-	STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_DMA1EN|STM32_RCC_AHB1ENR_DMA2EN |
-		STM32_RCC_AHB1ENR_DMAMUXEN;
+	STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_DMA1EN |
+			     STM32_RCC_AHB1ENR_DMA2EN;
+#elif defined(CHIP_FAMILY_STM32G4) || defined(CHIP_FAMILY_STM32L5)
+	STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_DMA1EN |
+			     STM32_RCC_AHB1ENR_DMA2EN |
+			     STM32_RCC_AHB1ENR_DMAMUXEN;
 #else
 	STM32_RCC_AHBENR |= STM32_RCC_HB_DMA1;
 #endif
@@ -275,8 +288,9 @@ int dma_wait(enum dma_channel channel)
 static inline void _dma_wake_callback(void *cb_data)
 {
 	task_id_t id = (task_id_t)(int)cb_data;
+
 	if (id != TASK_ID_INVALID)
-		task_set_event(id, TASK_EVENT_DMA_TC, 0);
+		task_set_event(id, TASK_EVENT_DMA_TC);
 }
 
 void dma_enable_tc_interrupt(enum dma_channel channel)
@@ -318,18 +332,18 @@ void dma_clear_isr(enum dma_channel channel)
 
 #ifdef CONFIG_DMA_DEFAULT_HANDLERS
 #ifdef CHIP_FAMILY_STM32F0
-void dma_event_interrupt_channel_1(void)
+static void dma_event_interrupt_channel_1(void)
 {
 	if (STM32_DMA1_REGS->isr & STM32_DMA_ISR_TCIF(STM32_DMAC_CH1)) {
 		dma_clear_isr(STM32_DMAC_CH1);
 		if (dma_irq[STM32_DMAC_CH1].cb != NULL)
-			(*dma_irq[STM32_DMAC_CH1].cb)
-				(dma_irq[STM32_DMAC_CH1].cb_data);
+			(*dma_irq[STM32_DMAC_CH1].cb)(
+				dma_irq[STM32_DMAC_CH1].cb_data);
 	}
 }
 DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_1, dma_event_interrupt_channel_1, 1);
 
-void dma_event_interrupt_channel_2_3(void)
+static void dma_event_interrupt_channel_2_3(void)
 {
 	int i;
 
@@ -343,12 +357,10 @@ void dma_event_interrupt_channel_2_3(void)
 }
 DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_2_3, dma_event_interrupt_channel_2_3, 1);
 
-void dma_event_interrupt_channel_4_7(void)
+static void dma_event_interrupt_channel_4_7(void)
 {
 	int i;
-	const unsigned int max_chan = MIN(STM32_DMAC_CH7, STM32_DMAC_COUNT);
-
-	for (i = STM32_DMAC_CH4; i <= max_chan; i++) {
+	for (i = STM32_DMAC_CH4; i < STM32_DMAC_COUNT; i++) {
 		if (STM32_DMA1_REGS->isr & STM32_DMA_ISR_TCIF(i)) {
 			dma_clear_isr(i);
 			if (dma_irq[i].cb != NULL)
@@ -360,16 +372,16 @@ DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_4_7, dma_event_interrupt_channel_4_7, 1);
 
 #else /* !CHIP_FAMILY_STM32F0 */
 
-#define DECLARE_DMA_IRQ(x) \
-	void CONCAT2(dma_event_interrupt_channel_, x)(void) \
-	{ \
-		dma_clear_isr(CONCAT2(STM32_DMAC_CH, x)); \
-		if (dma_irq[CONCAT2(STM32_DMAC_CH, x)].cb != NULL) \
-			(*dma_irq[CONCAT2(STM32_DMAC_CH, x)].cb) \
-				(dma_irq[CONCAT2(STM32_DMAC_CH, x)].cb_data); \
-	} \
-	DECLARE_IRQ(CONCAT2(STM32_IRQ_DMA_CHANNEL_, x), \
-		    CONCAT2(dma_event_interrupt_channel_, x), 1);
+#define DECLARE_DMA_IRQ(x)                                                   \
+	static void CONCAT2(dma_event_interrupt_channel_, x)(void)           \
+	{                                                                    \
+		dma_clear_isr(CONCAT2(STM32_DMAC_CH, x));                    \
+		if (dma_irq[CONCAT2(STM32_DMAC_CH, x)].cb != NULL)           \
+			(*dma_irq[CONCAT2(STM32_DMAC_CH, x)].cb)(            \
+				dma_irq[CONCAT2(STM32_DMAC_CH, x)].cb_data); \
+	}                                                                    \
+	DECLARE_IRQ(CONCAT2(STM32_IRQ_DMA_CHANNEL_, x),                      \
+		    CONCAT2(dma_event_interrupt_channel_, x), 1)
 
 DECLARE_DMA_IRQ(1);
 DECLARE_DMA_IRQ(2);
@@ -382,6 +394,15 @@ DECLARE_DMA_IRQ(7);
 DECLARE_DMA_IRQ(9);
 DECLARE_DMA_IRQ(10);
 #endif
+#if defined(CHIP_FAMILY_STM32L4) || defined(CHIP_FAMILY_STM32L5)
+DECLARE_DMA_IRQ(9);
+DECLARE_DMA_IRQ(10);
+DECLARE_DMA_IRQ(11);
+DECLARE_DMA_IRQ(12);
+DECLARE_DMA_IRQ(13);
+DECLARE_DMA_IRQ(14);
+DECLARE_DMA_IRQ(15);
+#endif
 
 #endif /* CHIP_FAMILY_STM32F0 */
 #endif /* CONFIG_DMA_DEFAULT_HANDLERS */
diff --git a/chip/stm32/flash-f.c b/chip/stm32/flash-f.c
index b192d44255..2673201472 100644
--- a/chip/stm32/flash-f.c
+++ b/chip/stm32/flash-f.c
@@ -1,27 +1,29 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Common flash memory module for STM32F and STM32F0 */
 
-#include <stdbool.h>
 #include "battery.h"
-#include "console.h"
+#include "builtin/assert.h"
 #include "clock.h"
-#include "flash.h"
+#include "console.h"
 #include "flash-f.h"
+#include "flash.h"
 #include "hooks.h"
-#include "registers.h"
 #include "panic.h"
+#include "registers.h"
 #include "system.h"
 #include "task.h"
 #include "timer.h"
 #include "util.h"
 #include "watchdog.h"
 
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#include <stdbool.h>
+
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 /*
  * Approximate number of CPU cycles per iteration of the loop when polling
@@ -49,14 +51,15 @@
 
 /* Forward declarations */
 #if defined(CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE)
-static enum flash_rdp_level flash_physical_get_rdp_level(void);
+	static enum flash_rdp_level
+	flash_physical_get_rdp_level(void);
 static int flash_physical_set_rdp_level(enum flash_rdp_level level);
 #endif /* CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE */
 
 static inline int calculate_flash_timeout(void)
 {
-	return (FLASH_WRITE_TIMEOUT_US *
-		(clock_get_freq() / SECOND) / CYCLE_PER_FLASH_LOOP);
+	return (FLASH_WRITE_TIMEOUT_US * (clock_get_freq() / SECOND) /
+		CYCLE_PER_FLASH_LOOP);
 }
 
 static int wait_busy(void)
@@ -67,7 +70,6 @@ static int wait_busy(void)
 	return (timeout > 0) ? EC_SUCCESS : EC_ERROR_TIMEOUT;
 }
 
-
 void unlock_flash_control_register(void)
 {
 	STM32_FLASH_KEYR = FLASH_KEYR_KEY1;
@@ -134,7 +136,7 @@ bool flash_control_register_locked(void)
  * We at least unlock the control register lock.
  * We may also unlock other locks.
  */
-enum extra_lock_type  {
+enum extra_lock_type {
 	NO_EXTRA_LOCK = 0,
 	OPT_LOCK = 1,
 };
@@ -341,7 +343,7 @@ bool is_flash_rdp_enabled(void)
 /*****************************************************************************/
 /* Physical layer APIs */
 
-int flash_physical_write(int offset, int size, const char *data)
+int crec_flash_physical_write(int offset, int size, const char *data)
 {
 #if CONFIG_FLASH_WRITE_SIZE == 1
 	uint8_t *address = (uint8_t *)(CONFIG_PROGRAM_MEMORY_BASE + offset);
@@ -382,9 +384,7 @@ int flash_physical_write(int offset, int size, const char *data)
 		watchdog_reload();
 
 		/* wait to be ready  */
-		for (i = 0;
-		     (STM32_FLASH_SR & FLASH_SR_BUSY) &&
-		     (i < timeout);
+		for (i = 0; (STM32_FLASH_SR & FLASH_SR_BUSY) && (i < timeout);
 		     i++)
 			;
 
@@ -392,9 +392,7 @@ int flash_physical_write(int offset, int size, const char *data)
 		*address++ = quantum;
 
 		/* Wait for writes to complete */
-		for (i = 0;
-		     (STM32_FLASH_SR & FLASH_SR_BUSY) &&
-		     (i < timeout);
+		for (i = 0; (STM32_FLASH_SR & FLASH_SR_BUSY) && (i < timeout);
 		     i++)
 			;
 
@@ -420,16 +418,16 @@ int flash_physical_write(int offset, int size, const char *data)
 	return res;
 }
 
-int flash_physical_erase(int offset, int size)
+int crec_flash_physical_erase(int offset, int size)
 {
 	int res = EC_SUCCESS;
 	int sector_size;
 	int timeout_us;
 #ifdef CHIP_FAMILY_STM32F4
-	int sector = flash_bank_index(offset);
+	int sector = crec_flash_bank_index(offset);
 	/* we take advantage of sector_size == erase_size */
-	if ((sector < 0) || (flash_bank_index(offset + size) < 0))
-		return EC_ERROR_INVAL;  /* Invalid range */
+	if ((sector < 0) || (crec_flash_bank_index(offset + size) < 0))
+		return EC_ERROR_INVAL; /* Invalid range */
 #endif
 
 	if (unlock(NO_EXTRA_LOCK) != EC_SUCCESS)
@@ -444,7 +442,7 @@ int flash_physical_erase(int offset, int size)
 	while (size > 0) {
 		timestamp_t deadline;
 #ifdef CHIP_FAMILY_STM32F4
-		sector_size = flash_bank_size(sector);
+		sector_size = crec_flash_bank_size(sector);
 		/* Timeout: from spec, proportional to the size
 		 * inversely proportional to the write size.
 		 */
@@ -454,12 +452,12 @@ int flash_physical_erase(int offset, int size)
 		timeout_us = FLASH_ERASE_TIMEOUT_US;
 #endif
 		/* Do nothing if already erased */
-		if (flash_is_erased(offset, sector_size))
+		if (crec_flash_is_erased(offset, sector_size))
 			goto next_sector;
 #ifdef CHIP_FAMILY_STM32F4
 		/* select page to erase */
 		STM32_FLASH_CR = (STM32_FLASH_CR & ~STM32_FLASH_CR_SNB_MASK) |
-			(sector << STM32_FLASH_CR_SNB_OFFSET);
+				 (sector << STM32_FLASH_CR_SNB_OFFSET);
 #else
 		/* select page to erase */
 		STM32_FLASH_AR = CONFIG_PROGRAM_MEMORY_BASE + offset;
@@ -472,7 +470,7 @@ int flash_physical_erase(int offset, int size)
 		watchdog_reload();
 		while ((STM32_FLASH_SR & FLASH_SR_BUSY) &&
 		       (get_time().val < deadline.val)) {
-			usleep(timeout_us/100);
+			usleep(timeout_us / 100);
 		}
 		if (STM32_FLASH_SR & FLASH_SR_BUSY) {
 			res = EC_ERROR_TIMEOUT;
@@ -487,7 +485,7 @@ int flash_physical_erase(int offset, int size)
 			res = EC_ERROR_UNKNOWN;
 			goto exit_er;
 		}
-next_sector:
+	next_sector:
 		size -= sector_size;
 		offset += sector_size;
 #ifdef CHIP_FAMILY_STM32F4
@@ -533,15 +531,14 @@ static int flash_physical_protect_at_boot_update_rdp_pstate(uint32_t new_flags)
 #endif
 }
 
-int flash_physical_protect_at_boot(uint32_t new_flags)
+int crec_flash_physical_protect_at_boot(uint32_t new_flags)
 {
 	int block;
 	int original_val, val;
 
 	original_val = val = STM32_OPTB_WP & STM32_OPTB_nWRP_ALL;
 
-	for (block = WP_BANK_OFFSET;
-	     block < WP_BANK_OFFSET + PHYSICAL_BANKS;
+	for (block = WP_BANK_OFFSET; block < WP_BANK_OFFSET + PHYSICAL_BANKS;
 	     block++) {
 		int protect = new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT;
 
@@ -573,14 +570,14 @@ static void unprotect_all_blocks(void)
 	write_optb(STM32_FLASH_nWRP_ALL, STM32_FLASH_nWRP_ALL);
 }
 
-#else   /* CHIP_FAMILY_STM32F4 */
+#else /* CHIP_FAMILY_STM32F4 */
 static int flash_physical_get_protect_at_boot(int block)
 {
-	uint8_t val = read_optb(STM32_OPTB_WRP_OFF(block/8));
+	uint8_t val = read_optb(STM32_OPTB_WRP_OFF(block / 8));
 	return (!(val & (1 << (block % 8)))) ? 1 : 0;
 }
 
-int flash_physical_protect_at_boot(uint32_t new_flags)
+int crec_flash_physical_protect_at_boot(uint32_t new_flags)
 {
 	int block;
 	int i;
@@ -589,11 +586,10 @@ int flash_physical_protect_at_boot(uint32_t new_flags)
 	for (i = 0; i < 4; ++i)
 		original_val[i] = val[i] = read_optb(i * 2 + 8);
 
-	for (block = WP_BANK_OFFSET;
-	     block < WP_BANK_OFFSET + PHYSICAL_BANKS;
+	for (block = WP_BANK_OFFSET; block < WP_BANK_OFFSET + PHYSICAL_BANKS;
 	     block++) {
 		int protect = new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT;
-		int byte_off = STM32_OPTB_WRP_OFF(block/8) / 2 - 4;
+		int byte_off = STM32_OPTB_WRP_OFF(block / 8) / 2 - 4;
 
 		if (block >= WP_BANK_OFFSET &&
 		    block < WP_BANK_OFFSET + WP_BANK_COUNT)
@@ -601,7 +597,8 @@ int flash_physical_protect_at_boot(uint32_t new_flags)
 #ifdef CONFIG_ROLLBACK
 		else if (block >= ROLLBACK_BANK_OFFSET &&
 			 block < ROLLBACK_BANK_OFFSET + ROLLBACK_BANK_COUNT)
-			protect |= new_flags & EC_FLASH_PROTECT_ROLLBACK_AT_BOOT;
+			protect |= new_flags &
+				   EC_FLASH_PROTECT_ROLLBACK_AT_BOOT;
 #endif
 #ifdef CONFIG_FLASH_PROTECT_RW
 		else
@@ -646,7 +643,7 @@ static void unprotect_all_blocks(void)
  */
 static int registers_need_reset(void)
 {
-	uint32_t flags = flash_get_protect();
+	uint32_t flags = crec_flash_get_protect();
 	int i;
 	int ro_at_boot = (flags & EC_FLASH_PROTECT_RO_AT_BOOT) ? 1 : 0;
 	int ro_wp_region_start = WP_BANK_OFFSET;
@@ -723,22 +720,21 @@ enum flash_rdp_level flash_physical_get_rdp_level(void)
 /*****************************************************************************/
 /* High-level APIs */
 
-int flash_pre_init(void)
+int crec_flash_pre_init(void)
 {
 	uint32_t reset_flags = system_get_reset_flags();
-	uint32_t prot_flags = flash_get_protect();
+	uint32_t prot_flags = crec_flash_get_protect();
 	int need_reset = 0;
 
-
 #ifdef CHIP_FAMILY_STM32F4
 	unlock(NO_EXTRA_LOCK);
 	/* Set the proper write size */
 	STM32_FLASH_CR = (STM32_FLASH_CR & ~STM32_FLASH_CR_PSIZE_MASK) |
-		 (31 - __builtin_clz(CONFIG_FLASH_WRITE_SIZE)) <<
-		 STM32_FLASH_CR_PSIZE_OFFSET;
+			 (31 - __builtin_clz(CONFIG_FLASH_WRITE_SIZE))
+				 << STM32_FLASH_CR_PSIZE_OFFSET;
 	lock();
 #endif
-	if (flash_physical_restore_state())
+	if (crec_flash_physical_restore_state())
 		return EC_SUCCESS;
 
 	/*
@@ -751,7 +747,7 @@ int flash_pre_init(void)
 	if (prot_flags & EC_FLASH_PROTECT_GPIO_ASSERTED) {
 		if (prot_flags & EC_FLASH_PROTECT_RO_NOW) {
 			/* Enable physical protection for RO (0 means RO). */
-			flash_physical_protect_now(0);
+			crec_flash_physical_protect_now(0);
 		}
 
 		if ((prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT) &&
@@ -762,7 +758,7 @@ int flash_pre_init(void)
 			 * update to the write protect register and reboot so
 			 * it takes effect.
 			 */
-			flash_physical_protect_at_boot(
+			crec_flash_physical_protect_at_boot(
 				EC_FLASH_PROTECT_RO_AT_BOOT);
 			need_reset = 1;
 		}
@@ -776,8 +772,8 @@ int flash_pre_init(void)
 			 * to the check above.  One of them should be able to
 			 * go away.
 			 */
-			flash_protect_at_boot(
-				prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT);
+			crec_flash_protect_at_boot(prot_flags &
+						   EC_FLASH_PROTECT_RO_AT_BOOT);
 			need_reset = 1;
 		}
 	} else {
@@ -791,7 +787,8 @@ int flash_pre_init(void)
 		}
 	}
 
-	if ((flash_physical_get_valid_flags() & EC_FLASH_PROTECT_ALL_AT_BOOT) &&
+	if ((crec_flash_physical_get_valid_flags() &
+	     EC_FLASH_PROTECT_ALL_AT_BOOT) &&
 	    (!!(prot_flags & EC_FLASH_PROTECT_ALL_AT_BOOT) !=
 	     !!(prot_flags & EC_FLASH_PROTECT_ALL_NOW))) {
 		/*
@@ -806,7 +803,8 @@ int flash_pre_init(void)
 	}
 
 #ifdef CONFIG_FLASH_PROTECT_RW
-	if ((flash_physical_get_valid_flags() & EC_FLASH_PROTECT_RW_AT_BOOT) &&
+	if ((crec_flash_physical_get_valid_flags() &
+	     EC_FLASH_PROTECT_RW_AT_BOOT) &&
 	    (!!(prot_flags & EC_FLASH_PROTECT_RW_AT_BOOT) !=
 	     !!(prot_flags & EC_FLASH_PROTECT_RW_NOW))) {
 		/* RW_AT_BOOT and RW_NOW do not match. */
@@ -815,7 +813,8 @@ int flash_pre_init(void)
 #endif
 
 #ifdef CONFIG_ROLLBACK
-	if ((flash_physical_get_valid_flags() & EC_FLASH_PROTECT_ROLLBACK_AT_BOOT) &&
+	if ((crec_flash_physical_get_valid_flags() &
+	     EC_FLASH_PROTECT_ROLLBACK_AT_BOOT) &&
 	    (!!(prot_flags & EC_FLASH_PROTECT_ROLLBACK_AT_BOOT) !=
 	     !!(prot_flags & EC_FLASH_PROTECT_ROLLBACK_NOW))) {
 		/* ROLLBACK_AT_BOOT and ROLLBACK_NOW do not match. */
diff --git a/chip/stm32/flash-f.h b/chip/stm32/flash-f.h
index 8d2b8e1fae..507ded32f1 100644
--- a/chip/stm32/flash-f.h
+++ b/chip/stm32/flash-f.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,108 +9,18 @@
 #include <stdbool.h>
 
 enum flash_rdp_level {
-	FLASH_RDP_LEVEL_INVALID = -1,	/**< Error occurred. */
-	FLASH_RDP_LEVEL_0,		/**< No read protection. */
-	FLASH_RDP_LEVEL_1,		/**< Reading flash is disabled while in
-					 *   bootloader mode or JTAG attached.
-					 *   Changing to Level 0 from this level
-					 *   triggers mass erase.
-					 */
-	FLASH_RDP_LEVEL_2,		/**< Same as Level 1, but is permanent
-					 *   and can never be disabled.
-					 */
+	FLASH_RDP_LEVEL_INVALID = -1, /**< Error occurred. */
+	FLASH_RDP_LEVEL_0, /**< No read protection. */
+	FLASH_RDP_LEVEL_1, /**< Reading flash is disabled while in
+			    *   bootloader mode or JTAG attached.
+			    *   Changing to Level 0 from this level
+			    *   triggers mass erase.
+			    */
+	FLASH_RDP_LEVEL_2, /**< Same as Level 1, but is permanent
+			    *   and can never be disabled.
+			    */
 };
 
 bool is_flash_rdp_enabled(void);
 
-/**
- * Unlock the flash control register using the unlock sequence.
- *
- * If the flash control register has been disabled since the last reset when
- * this function is called, a bus fault will be generated.
- *
- * See "3.5.1 Unlocking the Flash control register" in RM0402.
- */
-void unlock_flash_control_register(void);
-
-/**
- * Unlock the flash option bytes register using the unlock sequence.
- *
- * If the flash option bytes register has been disabled since the last reset
- * when this function is called, a bus fault will be generated.
- *
- * See "3.6.2 Programming user option bytes" in RM0402.
- */
-void unlock_flash_option_bytes(void);
-
-/**
- * Lock the flash control register.
- *
- * If the flash control register has been disabled since the last reset when
- * this function is called, a bus fault will be generated.
- *
- * See "3.5.1 Unlocking the Flash control register" in RM0402.
- */
-void lock_flash_control_register(void);
-
-/**
- * Lock the flash option bytes register.
- *
- * If the flash option bytes register has been disabled since the last reset
- * when this function is called, a bus fault will be generated.
- *
- * See "3.6.2 Programming user option bytes" in RM0402.
- */
-void lock_flash_option_bytes(void);
-
-/**
- * Disable the flash option bytes register.
- *
- * This function expects that bus faults have not already been ignored when
- * called.
- *
- * Once this function is called any attempt at accessing the flash option
- * bytes register will generate a bus fault until the next reset.
- *
- * See "3.6.2 Programming user option bytes" in RM0402.
- */
-void disable_flash_option_bytes(void);
-
-/**
- * Disable the flash control register.
- *
- * This function expects that bus faults have not already been ignored when
- * called.
- *
- * Once this function is called any attempt at accessing the flash control
- * register will generate a bus fault until the next reset.
- *
- * See "3.5.1 Unlocking the Flash control register" in RM0402.
- */
-void disable_flash_control_register(void);
-
-/**
- * Check if the flash option bytes are locked.
- *
- * If the flash option bytes register has been disabled since the last reset
- * when this function is called, a bus fault will be generated.
-
- * See "3.6.2 Programming user option bytes" in RM0402.
- *
- * @return true if option bytes are locked, false otherwise
- */
-bool flash_option_bytes_locked(void);
-
-/**
- * Check if the flash control register is locked.
- *
- * If the flash control register has been disabled since the last reset
- * when this function is called, a bus fault will be generated.
- *
- * See "3.5.1 Unlocking the Flash control register" in RM0402.
- *
- * @return true if register is locked, false otherwise
- */
-bool flash_control_register_locked(void);
-
 #endif /* __CROS_EC_STM32_FLASH_F_H */
diff --git a/chip/stm32/flash-regs.h b/chip/stm32/flash-regs.h
new file mode 100644
index 0000000000..9456c03963
--- /dev/null
+++ b/chip/stm32/flash-regs.h
@@ -0,0 +1,109 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_STM32_FLASH_REGS_H
+#define __CROS_EC_STM32_FLASH_REGS_H
+
+#include <stdbool.h>
+
+/**
+ * Unlock the flash control register using the unlock sequence.
+ *
+ * If the flash control register has been disabled since the last reset when
+ * this function is called, a bus fault will be generated.
+ *
+ * See "3.5.1 Unlocking the Flash control register" in RM0402.
+ * See "4.9.2  FLASH key register for bank 1" in RM0433.
+ */
+void unlock_flash_control_register(void);
+
+/**
+ * Unlock the flash option bytes register using the unlock sequence.
+ *
+ * If the flash option bytes register has been disabled since the last reset
+ * when this function is called, a bus fault will be generated.
+ *
+ * See "3.6.2 Programming user option bytes" in RM0402.
+ * See "4.9.3 FLASH option key register" in RM0433.
+ */
+void unlock_flash_option_bytes(void);
+
+/**
+ * Lock the flash control register.
+ *
+ * If the flash control register has been disabled since the last reset when
+ * this function is called, a bus fault will be generated.
+ *
+ * See "3.5.1 Unlocking the Flash control register" in RM0402.
+ * See "4.9.4 Flash control register for bank 1" in RM0433.
+ */
+void lock_flash_control_register(void);
+
+/**
+ * Lock the flash option bytes register.
+ *
+ * If the flash option bytes register has been disabled since the last reset
+ * when this function is called, a bus fault will be generated.
+ *
+ * See "3.6.2 Programming user option bytes" in RM0402.
+ * See "4.9.7 FLASH option control register" in RM0433.
+ */
+void lock_flash_option_bytes(void);
+
+/**
+ * Disable the flash option bytes register.
+ *
+ * This function expects that bus faults have not already been ignored when
+ * called.
+ *
+ * Once this function is called any attempt at accessing the flash option
+ * bytes register will generate a bus fault until the next reset.
+ *
+ * See "3.6.2 Programming user option bytes" in RM0402.
+ * See "4.9.7 FLASH option control register" in RM0433.
+ */
+void disable_flash_option_bytes(void);
+
+/**
+ * Disable the flash control register.
+ *
+ * This function expects that bus faults have not already been ignored when
+ * called.
+ *
+ * Once this function is called any attempt at accessing the flash control
+ * register will generate a bus fault until the next reset.
+ *
+ * See "3.5.1 Unlocking the Flash control register" in RM0402.
+ * See "4.9.4 Flash control register for bank 1" in RM0433.
+ */
+void disable_flash_control_register(void);
+
+/**
+ * Check if the flash option bytes are locked.
+ *
+ * If the flash option bytes register has been disabled since the last reset
+ * when this function is called, a bus fault will be generated.
+
+ * See "3.6.2 Programming user option bytes" in RM0402.
+ * See "4.9.7 FLASH option control register" in RM0433.
+ *
+ * @return true if option bytes are locked, false otherwise
+ */
+bool flash_option_bytes_locked(void);
+
+/**
+ * Check if the flash control register is locked.
+ *
+ * If the flash control register has been disabled since the last reset
+ * when this function is called, a bus fault will be generated.
+ *
+ * See "3.5.1 Unlocking the Flash control register" in RM0402.
+ * See "4.9.4 Flash control register for bank 1" in RM0433.
+ *
+ * @return true if register is locked, false otherwise
+ */
+bool flash_control_register_locked(void);
+
+#endif /* __CROS_EC_STM32_FLASH_REGS_H */
diff --git a/chip/stm32/flash-stm32f0.c b/chip/stm32/flash-stm32f0.c
index e2ff2c779c..058a8afc46 100644
--- a/chip/stm32/flash-stm32f0.c
+++ b/chip/stm32/flash-stm32f0.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,7 +13,7 @@
 /*****************************************************************************/
 /* Physical layer APIs */
 
-int flash_physical_get_protect(int block)
+int crec_flash_physical_get_protect(int block)
 {
 	return !(STM32_FLASH_WRPR & BIT(block));
 }
@@ -22,11 +22,11 @@ int flash_physical_get_protect(int block)
  * Note: This does not need to update _NOW flags, as get_protect_flags
  * in common code already does so.
  */
-uint32_t flash_physical_get_protect_flags(void)
+uint32_t crec_flash_physical_get_protect_flags(void)
 {
 	uint32_t flags = 0;
 	uint32_t wrp01 = REG32(STM32_OPTB_BASE + STM32_OPTB_WRP01);
-#if CONFIG_FLASH_SIZE > 64 * 1024
+#if CONFIG_FLASH_SIZE_BYTES > 64 * 1024
 	uint32_t wrp23 = REG32(STM32_OPTB_BASE + STM32_OPTB_WRP23);
 #endif
 
@@ -65,8 +65,7 @@ uint32_t flash_physical_get_protect_flags(void)
 		/* Default: RW. */
 		int region = FLASH_REGION_RW;
 
-		if (i >= WP_BANK_OFFSET &&
-		    i < WP_BANK_OFFSET + WP_BANK_COUNT)
+		if (i >= WP_BANK_OFFSET && i < WP_BANK_OFFSET + WP_BANK_COUNT)
 			region = FLASH_REGION_RO;
 #ifdef CONFIG_ROLLBACK
 		if (i >= ROLLBACK_BANK_OFFSET &&
@@ -76,12 +75,12 @@ uint32_t flash_physical_get_protect_flags(void)
 
 		switch (i) {
 		case 8:
-#if CONFIG_FLASH_SIZE > 64 * 1024
+#if CONFIG_FLASH_SIZE_BYTES > 64 * 1024
 		case 24:
 #endif
 			shift += 8;
 			break;
-#if CONFIG_FLASH_SIZE > 64 * 1024
+#if CONFIG_FLASH_SIZE_BYTES > 64 * 1024
 		case 16:
 			reg = 1;
 			shift = 0;
@@ -95,18 +94,18 @@ uint32_t flash_physical_get_protect_flags(void)
 
 	for (i = 0; i < FLASH_REGION_COUNT; i++) {
 		if (!(wrp01 & wrp_mask[i][0]) &&
-			(wrp01 & wrp_mask[i][0] << 8) == (wrp_mask[i][0] << 8))
-#if CONFIG_FLASH_SIZE > 64 * 1024
+		    (wrp01 & wrp_mask[i][0] << 8) == (wrp_mask[i][0] << 8))
+#if CONFIG_FLASH_SIZE_BYTES > 64 * 1024
 			if (!(wrp23 & wrp_mask[i][1]) &&
-			     (wrp23 & wrp_mask[i][1] << 8) ==
-							 (wrp_mask[i][1] << 8))
+			    (wrp23 & wrp_mask[i][1] << 8) ==
+				    (wrp_mask[i][1] << 8))
 #endif
 				flags |= mask_flags[i];
 	}
 #endif /* CONFIG_FLASH_PROTECT_RW || CONFIG_ROLLBACK */
 
 	if (wrp01 == 0xff00ff00)
-#if CONFIG_FLASH_SIZE > 64 * 1024
+#if CONFIG_FLASH_SIZE_BYTES > 64 * 1024
 		if (wrp23 == 0xff00ff00)
 #endif
 			flags |= EC_FLASH_PROTECT_ALL_AT_BOOT;
@@ -114,34 +113,31 @@ uint32_t flash_physical_get_protect_flags(void)
 	return flags;
 }
 
-int flash_physical_protect_now(int all)
+int crec_flash_physical_protect_now(int all)
 {
 	return EC_ERROR_INVAL;
 }
 
-int flash_physical_restore_state(void)
+int crec_flash_physical_restore_state(void)
 {
 	/* Nothing to restore */
 	return 0;
 }
 
-uint32_t flash_physical_get_valid_flags(void)
+uint32_t crec_flash_physical_get_valid_flags(void)
 {
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-	       EC_FLASH_PROTECT_RO_NOW |
+	return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW |
 #ifdef CONFIG_FLASH_PROTECT_RW
-	       EC_FLASH_PROTECT_RW_AT_BOOT |
-	       EC_FLASH_PROTECT_RW_NOW |
+	       EC_FLASH_PROTECT_RW_AT_BOOT | EC_FLASH_PROTECT_RW_NOW |
 #endif
 #ifdef CONFIG_ROLLBACK
 	       EC_FLASH_PROTECT_ROLLBACK_AT_BOOT |
 	       EC_FLASH_PROTECT_ROLLBACK_NOW |
 #endif
-	       EC_FLASH_PROTECT_ALL_AT_BOOT |
-	       EC_FLASH_PROTECT_ALL_NOW;
+	       EC_FLASH_PROTECT_ALL_AT_BOOT | EC_FLASH_PROTECT_ALL_NOW;
 }
 
-uint32_t flash_physical_get_writable_flags(uint32_t cur_flags)
+uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
 {
 	uint32_t ret = 0;
 
@@ -153,13 +149,13 @@ uint32_t flash_physical_get_writable_flags(uint32_t cur_flags)
 	 * ALL/RW at-boot state can be set if WP GPIO is asserted and can always
 	 * be cleared.
 	 */
-	if (cur_flags & (EC_FLASH_PROTECT_ALL_AT_BOOT |
-			 EC_FLASH_PROTECT_GPIO_ASSERTED))
+	if (cur_flags &
+	    (EC_FLASH_PROTECT_ALL_AT_BOOT | EC_FLASH_PROTECT_GPIO_ASSERTED))
 		ret |= EC_FLASH_PROTECT_ALL_AT_BOOT;
 
 #ifdef CONFIG_FLASH_PROTECT_RW
-	if (cur_flags & (EC_FLASH_PROTECT_RW_AT_BOOT |
-			 EC_FLASH_PROTECT_GPIO_ASSERTED))
+	if (cur_flags &
+	    (EC_FLASH_PROTECT_RW_AT_BOOT | EC_FLASH_PROTECT_GPIO_ASSERTED))
 		ret |= EC_FLASH_PROTECT_RW_AT_BOOT;
 #endif
 
diff --git a/chip/stm32/flash-stm32f3.c b/chip/stm32/flash-stm32f3.c
index ea5ba1a1b6..c41f9c526d 100644
--- a/chip/stm32/flash-stm32f3.c
+++ b/chip/stm32/flash-stm32f3.c
@@ -1,18 +1,20 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Flash memory module for stm32f3 and stm32f4 */
 
-#include <stdbool.h>
 #include "common.h"
-#include "flash.h"
 #include "flash-f.h"
+#include "flash-regs.h"
+#include "flash.h"
 #include "hooks.h"
+#include "panic.h"
 #include "registers.h"
 #include "system.h"
-#include "panic.h"
+
+#include <stdbool.h>
 
 /*****************************************************************************/
 /* Physical layer APIs */
@@ -36,7 +38,7 @@ struct ec_flash_bank const flash_bank_array[] = {
 		.protect_size_exp = __fls(SIZE_128KB),
 	},
 	{
-		.count = (CONFIG_FLASH_SIZE - SIZE_256KB) / SIZE_256KB,
+		.count = (CONFIG_FLASH_SIZE_BYTES - SIZE_256KB) / SIZE_256KB,
 		.write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE),
 		.size_exp = __fls(SIZE_256KB),
 		.erase_size_exp = __fls(SIZE_256KB),
@@ -70,7 +72,7 @@ struct ec_flash_bank const flash_bank_array[] = {
 		.protect_size_exp = __fls(SIZE_64KB),
 	},
 	{
-		.count = (CONFIG_FLASH_SIZE - SIZE_128KB) / SIZE_128KB,
+		.count = (CONFIG_FLASH_SIZE_BYTES - SIZE_128KB) / SIZE_128KB,
 		.write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE),
 		.size_exp = __fls(SIZE_128KB),
 		.erase_size_exp = __fls(SIZE_128KB),
@@ -93,7 +95,7 @@ struct flash_wp_state {
 /*****************************************************************************/
 /* Physical layer APIs */
 
-int flash_physical_get_protect(int block)
+int crec_flash_physical_get_protect(int block)
 {
 	return (entire_flash_locked ||
 #if defined(CHIP_FAMILY_STM32F3)
@@ -101,10 +103,10 @@ int flash_physical_get_protect(int block)
 #elif defined(CHIP_FAMILY_STM32F4)
 		!(STM32_OPTB_WP & STM32_OPTB_nWRP(block))
 #endif
-	       );
+	);
 }
 
-uint32_t flash_physical_get_protect_flags(void)
+uint32_t crec_flash_physical_get_protect_flags(void)
 {
 	uint32_t flags = 0;
 
@@ -120,7 +122,7 @@ uint32_t flash_physical_get_protect_flags(void)
 	return flags;
 }
 
-int flash_physical_protect_now(int all)
+int crec_flash_physical_protect_now(int all)
 {
 	if (all) {
 		disable_flash_control_register();
@@ -134,14 +136,13 @@ int flash_physical_protect_now(int all)
 	return EC_SUCCESS;
 }
 
-uint32_t flash_physical_get_valid_flags(void)
+uint32_t crec_flash_physical_get_valid_flags(void)
 {
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-	       EC_FLASH_PROTECT_RO_NOW |
+	return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW |
 	       EC_FLASH_PROTECT_ALL_NOW;
 }
 
-uint32_t flash_physical_get_writable_flags(uint32_t cur_flags)
+uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
 {
 	uint32_t ret = 0;
 
@@ -160,7 +161,7 @@ uint32_t flash_physical_get_writable_flags(uint32_t cur_flags)
 	return ret;
 }
 
-int flash_physical_restore_state(void)
+int crec_flash_physical_restore_state(void)
 {
 	uint32_t reset_flags = system_get_reset_flags();
 	int version, size;
@@ -172,7 +173,7 @@ int flash_physical_restore_state(void)
 	 */
 	if (reset_flags & EC_RESET_FLAG_SYSJUMP) {
 		prev = (const struct flash_wp_state *)system_get_jump_tag(
-				FLASH_SYSJUMP_TAG, &version, &size);
+			FLASH_SYSJUMP_TAG, &version, &size);
 		if (prev && version == FLASH_HOOK_VERSION &&
 		    size == sizeof(*prev))
 			entire_flash_locked = prev->entire_flash_locked;
diff --git a/chip/stm32/flash-stm32f4.c b/chip/stm32/flash-stm32f4.c
deleted file mode 120000
index 6ff8130e17..0000000000
--- a/chip/stm32/flash-stm32f4.c
+++ /dev/null
@@ -1 +0,0 @@
-flash-stm32f3.c
\ No newline at end of file
diff --git a/chip/stm32/flash-stm32f4.c b/chip/stm32/flash-stm32f4.c
new file mode 100644
index 0000000000..c41f9c526d
--- /dev/null
+++ b/chip/stm32/flash-stm32f4.c
@@ -0,0 +1,198 @@
+/* Copyright 2017 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Flash memory module for stm32f3 and stm32f4 */
+
+#include "common.h"
+#include "flash-f.h"
+#include "flash-regs.h"
+#include "flash.h"
+#include "hooks.h"
+#include "panic.h"
+#include "registers.h"
+#include "system.h"
+
+#include <stdbool.h>
+
+/*****************************************************************************/
+/* Physical layer APIs */
+#ifdef CHIP_VARIANT_STM32F76X
+/*
+ * 8 "erase" sectors : 32KB/32KB/32KB/32KB/128KB/256KB/256KB/256KB
+ */
+struct ec_flash_bank const flash_bank_array[] = {
+	{
+		.count = 4,
+		.size_exp = __fls(SIZE_32KB),
+		.write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE),
+		.erase_size_exp = __fls(SIZE_32KB),
+		.protect_size_exp = __fls(SIZE_32KB),
+	},
+	{
+		.count = 1,
+		.size_exp = __fls(SIZE_128KB),
+		.write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE),
+		.erase_size_exp = __fls(SIZE_128KB),
+		.protect_size_exp = __fls(SIZE_128KB),
+	},
+	{
+		.count = (CONFIG_FLASH_SIZE_BYTES - SIZE_256KB) / SIZE_256KB,
+		.write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE),
+		.size_exp = __fls(SIZE_256KB),
+		.erase_size_exp = __fls(SIZE_256KB),
+		.protect_size_exp = __fls(SIZE_256KB),
+	},
+};
+#elif defined(CHIP_FAMILY_STM32F4)
+/*
+ * STM32F412xE has 512 KB flash
+ *   8 "erase" sectors (512 KB) : 16KB/16KB/16KB/16KB/64KB/128KB/128KB/128KB
+ *
+ * STM32F412xG has 1 MB flash
+ *   12 "erase" sectors (1024 KB) :
+ *           16KB/16KB/16KB/16KB/64KB/128KB/128KB/128KB/128KB/128KB/128KB/128KB
+ *
+ * https://www.st.com/resource/en/datasheet/stm32f412cg.pdf
+ */
+struct ec_flash_bank const flash_bank_array[] = {
+	{
+		.count = 4,
+		.size_exp = __fls(SIZE_16KB),
+		.write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE),
+		.erase_size_exp = __fls(SIZE_16KB),
+		.protect_size_exp = __fls(SIZE_16KB),
+	},
+	{
+		.count = 1,
+		.size_exp = __fls(SIZE_64KB),
+		.write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE),
+		.erase_size_exp = __fls(SIZE_64KB),
+		.protect_size_exp = __fls(SIZE_64KB),
+	},
+	{
+		.count = (CONFIG_FLASH_SIZE_BYTES - SIZE_128KB) / SIZE_128KB,
+		.write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE),
+		.size_exp = __fls(SIZE_128KB),
+		.erase_size_exp = __fls(SIZE_128KB),
+		.protect_size_exp = __fls(SIZE_128KB),
+	},
+};
+#endif
+
+/* Flag indicating whether we have locked down entire flash */
+static int entire_flash_locked;
+
+#define FLASH_SYSJUMP_TAG 0x5750 /* "WP" - Write Protect */
+#define FLASH_HOOK_VERSION 1
+
+/* The previous write protect state before sys jump */
+struct flash_wp_state {
+	int entire_flash_locked;
+};
+
+/*****************************************************************************/
+/* Physical layer APIs */
+
+int crec_flash_physical_get_protect(int block)
+{
+	return (entire_flash_locked ||
+#if defined(CHIP_FAMILY_STM32F3)
+		!(STM32_FLASH_WRPR & BIT(block))
+#elif defined(CHIP_FAMILY_STM32F4)
+		!(STM32_OPTB_WP & STM32_OPTB_nWRP(block))
+#endif
+	);
+}
+
+uint32_t crec_flash_physical_get_protect_flags(void)
+{
+	uint32_t flags = 0;
+
+	/* Read all-protected state from our shadow copy */
+	if (entire_flash_locked)
+		flags |= EC_FLASH_PROTECT_ALL_NOW;
+
+#if defined(CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE)
+	if (is_flash_rdp_enabled())
+		flags |= EC_FLASH_PROTECT_RO_AT_BOOT;
+#endif
+
+	return flags;
+}
+
+int crec_flash_physical_protect_now(int all)
+{
+	if (all) {
+		disable_flash_control_register();
+		entire_flash_locked = 1;
+
+		return EC_SUCCESS;
+	}
+
+	disable_flash_option_bytes();
+
+	return EC_SUCCESS;
+}
+
+uint32_t crec_flash_physical_get_valid_flags(void)
+{
+	return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW |
+	       EC_FLASH_PROTECT_ALL_NOW;
+}
+
+uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
+{
+	uint32_t ret = 0;
+
+	/* If RO protection isn't enabled, its at-boot state can be changed. */
+	if (!(cur_flags & EC_FLASH_PROTECT_RO_NOW))
+		ret |= EC_FLASH_PROTECT_RO_AT_BOOT;
+
+	/*
+	 * If entire flash isn't protected at this boot, it can be enabled if
+	 * the WP GPIO is asserted.
+	 */
+	if (!(cur_flags & EC_FLASH_PROTECT_ALL_NOW) &&
+	    (cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED))
+		ret |= EC_FLASH_PROTECT_ALL_NOW;
+
+	return ret;
+}
+
+int crec_flash_physical_restore_state(void)
+{
+	uint32_t reset_flags = system_get_reset_flags();
+	int version, size;
+	const struct flash_wp_state *prev;
+
+	/*
+	 * If we have already jumped between images, an earlier image could
+	 * have applied write protection. Nothing additional needs to be done.
+	 */
+	if (reset_flags & EC_RESET_FLAG_SYSJUMP) {
+		prev = (const struct flash_wp_state *)system_get_jump_tag(
+			FLASH_SYSJUMP_TAG, &version, &size);
+		if (prev && version == FLASH_HOOK_VERSION &&
+		    size == sizeof(*prev))
+			entire_flash_locked = prev->entire_flash_locked;
+		return 1;
+	}
+
+	return 0;
+}
+
+/*****************************************************************************/
+/* Hooks */
+
+static void flash_preserve_state(void)
+{
+	struct flash_wp_state state;
+
+	state.entire_flash_locked = entire_flash_locked;
+
+	system_add_jump_tag(FLASH_SYSJUMP_TAG, FLASH_HOOK_VERSION,
+			    sizeof(state), &state);
+}
+DECLARE_HOOK(HOOK_SYSJUMP, flash_preserve_state, HOOK_PRIO_DEFAULT);
diff --git a/chip/stm32/flash-stm32g4-l4.c b/chip/stm32/flash-stm32g4-l4.c
index 27092a1156..ad08047c23 100644
--- a/chip/stm32/flash-stm32g4-l4.c
+++ b/chip/stm32/flash-stm32g4-l4.c
@@ -1,15 +1,15 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 /* Flash memory module for STM32L4 family */
 
-#include "common.h"
 #include "clock.h"
+#include "common.h"
 #include "flash.h"
 #include "hooks.h"
-#include "registers.h"
 #include "panic.h"
+#include "registers.h"
 #include "system.h"
 #include "task.h"
 #include "timer.h"
@@ -30,47 +30,55 @@
  * used in the STM32 TRMs. Redifining macros here in terms of pages in order to
  * match STM32 documentation for write protect computations in this file.
  *
- * Two write protect (WRP) regions can be defined in the option bytes. The
- * assumption is that 1st WRP area is for RO and the 2nd WRP is for RW if RW WRP
- * config is selected. If RW is being write-protected, it is assume to be the
- * 1st page following the RO section until the last flash page. WRP areas are
- * specified in terms of page indices with a start index and an end index.
- * start == end means a single page is protected.
- *
- *     WRP1a_start = WRP1a_end  --> WRP1a_start page is protected
- *     WRP1a_start > WRP1a_end  --> No WRP area is specified
- *     WRP1a_start < WRP1a_end  --> Pages WRP1a_start to WRP1a_end protected
- *
  * These macros are from the common flash API and mean the following:
  * WP_BANK_OFFSET         -> index of first RO page
  * CONFIG_WP_STORAGE_SIZE -> size of RO region in bytes
  */
 #define FLASH_PAGE_SIZE CONFIG_FLASH_BANK_SIZE
-#define FLASH_PAGE_MAX_COUNT (CONFIG_FLASH_SIZE / FLASH_PAGE_SIZE)
+#define FLASH_PAGE_MAX_COUNT (CONFIG_FLASH_SIZE_BYTES / FLASH_PAGE_SIZE)
 #define FLASH_RO_FIRST_PAGE_IDX WP_BANK_OFFSET
-#define FLASH_RO_LAST_PAGE_IDX ((CONFIG_WP_STORAGE_SIZE / FLASH_PAGE_SIZE) \
-				 + FLASH_RO_FIRST_PAGE_IDX - 1)
+#define FLASH_RO_LAST_PAGE_IDX                        \
+	((CONFIG_WP_STORAGE_SIZE / FLASH_PAGE_SIZE) + \
+	 FLASH_RO_FIRST_PAGE_IDX - 1)
 #define FLASH_RW_FIRST_PAGE_IDX (FLASH_RO_LAST_PAGE_IDX + 1)
 #define FLASH_RW_LAST_PAGE_IDX (FLASH_PAGE_MAX_COUNT - 1)
 
-
 #define FLASH_PAGE_ROLLBACK_COUNT ROLLBACK_BANK_COUNT
 #define FLASH_PAGE_ROLLBACK_FIRST_IDX ROLLBACK_BANK_OFFSET
-#define FLASH_PAGE_ROLLBACK_LAST_IDX (FLASH_PAGE_ROLLBACK_FIRST_IDX +\
-					FLASH_PAGE_ROLLBACK_COUNT -1)
-
-#define FLASH_WRP_MASK              (FLASH_PAGE_MAX_COUNT - 1)
-#define FLASH_WRP_START(val)        ((val) & FLASH_WRP_MASK)
-#define FLASH_WRP_END(val)          (((val) >> 16) & FLASH_WRP_MASK)
-#define FLASH_WRP_RANGE(start, end) (((start) & FLASH_WRP_MASK) | \
-				       (((end) & FLASH_WRP_MASK) << 16))
-#define FLASH_WRP_RANGE_DISABLED    FLASH_WRP_RANGE(FLASH_WRP_MASK, 0x00)
+#define FLASH_PAGE_ROLLBACK_LAST_IDX \
+	(FLASH_PAGE_ROLLBACK_FIRST_IDX + FLASH_PAGE_ROLLBACK_COUNT - 1)
+
+#ifdef STM32_FLASH_DBANK_MODE
+#define FLASH_WRP_MASK (FLASH_PAGE_MAX_COUNT - 1)
+#else
+#ifdef CHIP_FAMILY_STM32L4
+#define FLASH_WRP_MASK 0xFF
+#else
+#define FLASH_WRP_MASK ((FLASH_PAGE_MAX_COUNT) / 2 - 1)
+#endif
+#endif /* CONFIG_FLASH_DBANK_MODE */
+#define FLASH_WRP_START(val) ((val)&FLASH_WRP_MASK)
+#define FLASH_WRP_END(val) (((val) >> 16) & FLASH_WRP_MASK)
+#define FLASH_WRP_RANGE(start, end) \
+	(((start)&FLASH_WRP_MASK) | (((end)&FLASH_WRP_MASK) << 16))
+#define FLASH_WRP_RANGE_DISABLED FLASH_WRP_RANGE(FLASH_WRP_MASK, 0x00)
 #define FLASH_WRP1X_MASK FLASH_WRP_RANGE(FLASH_WRP_MASK, FLASH_WRP_MASK)
 
+enum wrp_region {
+	WRP_RO,
+	WRP_RW,
+};
+
+struct wrp_info {
+	int enable;
+	int start;
+	int end;
+};
+
 static inline int calculate_flash_timeout(void)
 {
-	return (FLASH_TIMEOUT_US *
-		(clock_get_freq() / SECOND) / CYCLE_PER_FLASH_LOOP);
+	return (FLASH_TIMEOUT_US * (clock_get_freq() / SECOND) /
+		CYCLE_PER_FLASH_LOOP);
 }
 
 static int wait_while_busy(void)
@@ -96,8 +104,7 @@ static int unlock(int locks)
 		STM32_FLASH_KEYR = FLASH_KEYR_KEY2;
 	}
 	/* unlock option memory if required */
-	if ((locks & FLASH_CR_OPTLOCK) &&
-	    (STM32_FLASH_CR & FLASH_CR_OPTLOCK)) {
+	if ((locks & FLASH_CR_OPTLOCK) && (STM32_FLASH_CR & FLASH_CR_OPTLOCK)) {
 		STM32_FLASH_OPTKEYR = FLASH_OPTKEYR_KEY1;
 		STM32_FLASH_OPTKEYR = FLASH_OPTKEYR_KEY2;
 	}
@@ -105,13 +112,18 @@ static int unlock(int locks)
 	/* Re-enable bus fault handler */
 	ignore_bus_fault(0);
 
-	return (STM32_FLASH_CR & (locks | FLASH_CR_LOCK)) ? EC_ERROR_UNKNOWN
-							  : EC_SUCCESS;
+	return (STM32_FLASH_CR & (locks | FLASH_CR_LOCK)) ? EC_ERROR_UNKNOWN :
+							    EC_SUCCESS;
 }
 
 static void lock(void)
 {
-	STM32_FLASH_CR = FLASH_CR_LOCK;
+	STM32_FLASH_CR |= FLASH_CR_LOCK;
+}
+
+static void ob_lock(void)
+{
+	STM32_FLASH_CR |= FLASH_CR_OPTLOCK;
 }
 
 /*
@@ -156,41 +168,214 @@ static int commit_optb(void)
 {
 	int rv;
 
+	/*
+	 * Wait for last operation.
+	 */
+	rv = wait_while_busy();
+	if (rv)
+		return rv;
+
 	STM32_FLASH_CR |= FLASH_CR_OPTSTRT;
 
 	rv = wait_while_busy();
 	if (rv)
 		return rv;
+
+	ob_lock();
 	lock();
 
 	return EC_SUCCESS;
 }
 
+/*
+ * There are a minimum of 2 WRP regions that can be set. The STM32G4
+ * family has both category 2, and category 3 devices. Category 2
+ * devices have only 2 WRP regions, but category 3 devices have 4 WRP
+ * regions that can be configured. Category 3 devices also support dual
+ * flash banks, and this mode is the default setting. When DB mode is enabled,
+ * then each WRP register can only protect up to 64 2kB pages. This means that
+ * one WRP register is needed per bank.
+ *
+ *   1. WRP1A -> used always for RO
+ *   2. WRP1B -> used always for RW
+ *   3. WRP2A -> may be used for RW if dual-bank (DB) mode is enabled
+ *   4. WRP2B -> currently never used
+ *
+ * WRP areas are specified in terms of page indices with a start index
+ * and an end index. start == end means a single page is protected.
+ *
+ *   WRPnx_start = WRPnx_end  --> WRPnx_start page is protected
+ *   WRPnx_start > WRPnx_end  --> No WRP area is specified
+ *   WRPnx_start < WRPnx_end  --> Pages WRPnx_start to WRPnx_end
+ */
+static void optb_get_wrp(enum wrp_region region, struct wrp_info *wrp)
+{
+#ifdef STM32_FLASH_DBANK_MODE
+	int start;
+	int end;
+#endif
+	/* Assume WRP regions are not configured */
+	wrp->start = FLASH_WRP_MASK;
+	wrp->end = 0;
+	wrp->enable = 0;
+
+	if (region == WRP_RO) {
+		/*
+		 * RO write protect is fully described by WRP1AR. Get the
+		 * start/end indices. If end >= start, then RO write protect is
+		 * enabled.
+		 */
+		wrp->start = FLASH_WRP_START(STM32_OPTB_WRP1AR);
+		wrp->end = FLASH_WRP_END(STM32_OPTB_WRP1AR);
+		wrp->enable = wrp->end >= wrp->start;
+	} else if (region == WRP_RW) {
+		/*
+		 * RW write always uses WRP1BR. If dual-bank mode is being used,
+		 * then WRP2AR must also be check to determine the full range of
+		 * flash page indices being protected.
+		 */
+		wrp->start = FLASH_WRP_START(STM32_OPTB_WRP1BR);
+		wrp->end = FLASH_WRP_END(STM32_OPTB_WRP1BR);
+		wrp->enable = wrp->end >= wrp->start;
+#ifdef STM32_FLASH_DBANK_MODE
+		start = FLASH_WRP_START(STM32_FLASH_WRP2AR);
+		end = FLASH_WRP_END(STM32_FLASH_WRP2AR);
+		/*
+		 * If WRP2AR protection is enabled, then need to adjust either
+		 * the start, end, or both indices.
+		 */
+		if (end >= start) {
+			if (wrp->enable) {
+				/* WRP1BR is active, only need to adjust end */
+				wrp->end += end;
+			} else {
+				/*
+				 * WRP1BR is not active, so RW protection, if
+				 * enabled, is fully controlled by WRP2AR.
+				 */
+				wrp->start = start;
+				wrp->end = end;
+				wrp->enable = 1;
+			}
+		}
+#endif
+	}
+}
+
+static void optb_set_wrp(enum wrp_region region, struct wrp_info *wrp)
+{
+	int start = wrp->start;
+	int end = wrp->end;
+
+	if (!wrp->enable) {
+		/*
+		 * If enable is not set, then ignore the passed in start/end
+		 * values and set start/end to the default not protected range
+		 * which satisfies start > end
+		 */
+		start = FLASH_WRP_MASK;
+		end = 0;
+	}
+
+	if (region == WRP_RO) {
+		/* For RO can always use start/end directly */
+		STM32_FLASH_WRP1AR = FLASH_WRP_RANGE(start, end);
+	} else if (region == WRP_RW) {
+#ifdef STM32_FLASH_DBANK_MODE
+		/*
+		 * In the dual-bank flash case (STM32G4 Category 3 devices with
+		 * DB bit set), RW write protect can use both WRP1BR and WRP2AR
+		 * registers in order to span the full flash memory range.
+		 */
+		if (wrp->enable) {
+			int rw_end;
+
+			/*
+			 * If the 1st RW flash page is in the 1st half of
+			 * memory, then at least one block will be protected by
+			 * WRP1BR. If the end flash page is in the 2nd half of
+			 * memory, then cap the end for WRP1BR to its max
+			 * value. Otherwise, can use end passed in directly.
+			 */
+			if (start <= FLASH_WRP_MASK) {
+				rw_end = end > FLASH_WRP_MASK ? FLASH_WRP_MASK :
+								end;
+				STM32_FLASH_WRP1BR =
+					FLASH_WRP_RANGE(start, rw_end);
+			}
+			/*
+			 * If the last RW flash page is in the 2nd half of
+			 * memory, then at least one block will be protected by
+			 * WRP2AR. If the start flash page is in the 2nd half of
+			 * memory, can use start directly. Otherwise, start
+			 * needs to be set to 0 here.
+			 */
+			if (end > FLASH_WRP_MASK) {
+				rw_end = end & FLASH_WRP_MASK;
+				STM32_FLASH_WRP2AR = FLASH_WRP_RANGE(0, rw_end);
+			}
+		} else {
+			/*
+			 * RW write protect is being disabled. Set both WRP1BR
+			 * and WRP2AR to default start > end not protected
+			 * state.
+			 */
+			STM32_FLASH_WRP1BR = FLASH_WRP_RANGE(start, end);
+			STM32_FLASH_WRP2AR = FLASH_WRP_RANGE(start, end);
+		}
+#else
+		/* Single bank case, WRP1BR can cover the full memory range */
+		STM32_FLASH_WRP1BR = FLASH_WRP_RANGE(start, end);
+#endif
+	}
+}
+
 static void unprotect_all_blocks(void)
 {
+	struct wrp_info wrp;
+
+	/* Set info values to unprotected */
+	wrp.start = FLASH_WRP_MASK;
+	wrp.end = 0;
+	wrp.enable = 0;
+
 	unlock_optb();
-	STM32_FLASH_WRP1AR = FLASH_WRP_RANGE_DISABLED;
-	STM32_FLASH_WRP1BR = FLASH_WRP_RANGE_DISABLED;
+	/* Disable RO WRP */
+	optb_set_wrp(WRP_RO, &wrp);
+	/* Disable RW WRP */
+	optb_set_wrp(WRP_RW, &wrp);
 	commit_optb();
 }
 
-int flash_physical_protect_at_boot(uint32_t new_flags)
+int crec_flash_physical_protect_at_boot(uint32_t new_flags)
 {
-	uint32_t ro_range = FLASH_WRP_RANGE_DISABLED;
-	uint32_t rb_rw_range = FLASH_WRP_RANGE_DISABLED;
+	struct wrp_info wrp_ro;
+	struct wrp_info wrp_rw;
+
+	wrp_ro.start = FLASH_WRP_MASK;
+	wrp_ro.end = 0;
+	wrp_ro.enable = 0;
+
+	wrp_rw.start = FLASH_WRP_MASK;
+	wrp_rw.end = 0;
+	wrp_rw.enable = 0;
+
 	/*
-	 * WRP1AR is storing the write-protection range for the RO region.
-	 * WRP1BR is storing the write-protection range for the
-	 * rollback and RW regions.
+	 * Default operation for this function is to disable both RO and RW
+	 * write protection in the option bytes. Based on new_flags either RO or
+	 * RW or both regions write protect may be set.
 	 */
-	if (new_flags & (EC_FLASH_PROTECT_ALL_AT_BOOT |
-			 EC_FLASH_PROTECT_RO_AT_BOOT))
-		ro_range = FLASH_WRP_RANGE(FLASH_RO_FIRST_PAGE_IDX,
-					     FLASH_RO_LAST_PAGE_IDX);
+	if (new_flags &
+	    (EC_FLASH_PROTECT_ALL_AT_BOOT | EC_FLASH_PROTECT_RO_AT_BOOT)) {
+		wrp_ro.start = FLASH_RO_FIRST_PAGE_IDX;
+		wrp_ro.end = FLASH_RO_LAST_PAGE_IDX;
+		wrp_ro.enable = 1;
+	}
 
 	if (new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT) {
-		rb_rw_range = FLASH_WRP_RANGE(FLASH_RW_FIRST_PAGE_IDX,
-						FLASH_RW_LAST_PAGE_IDX);
+		wrp_rw.start = FLASH_RW_FIRST_PAGE_IDX;
+		wrp_rw.end = FLASH_RW_LAST_PAGE_IDX;
+		wrp_rw.enable = 1;
 	} else {
 		/*
 		 * Start index will be 1st index following RO region index. The
@@ -199,7 +384,7 @@ int flash_physical_protect_at_boot(uint32_t new_flags)
 		 * the 2nd memory protection area get written in option bytes.
 		 */
 		int start = FLASH_RW_FIRST_PAGE_IDX;
-		int end = FLASH_WRP_END(FLASH_WRP_RANGE_DISABLED);
+		int end = 0;
 #ifdef CONFIG_ROLLBACK
 		if (new_flags & EC_FLASH_PROTECT_ROLLBACK_AT_BOOT) {
 			start = FLASH_PAGE_ROLLBACK_FIRST_IDX;
@@ -213,8 +398,11 @@ int flash_physical_protect_at_boot(uint32_t new_flags)
 			end = FLASH_RW_LAST_PAGE_IDX;
 #endif /* CONFIG_FLASH_PROTECT_RW */
 
-		if (end != FLASH_WRP_END(FLASH_WRP_RANGE_DISABLED))
-			rb_rw_range = FLASH_WRP_RANGE(start, end);
+		if (end) {
+			wrp_rw.start = start;
+			wrp_rw.end = end;
+			wrp_rw.enable = 1;
+		}
 	}
 
 	unlock_optb();
@@ -225,8 +413,8 @@ int flash_physical_protect_at_boot(uint32_t new_flags)
 	 */
 	STM32_FLASH_OPTR = (STM32_FLASH_OPTR & ~0xff) | 0x11;
 #endif
-	STM32_FLASH_WRP1AR = ro_range;
-	STM32_FLASH_WRP1BR = rb_rw_range;
+	optb_set_wrp(WRP_RO, &wrp_ro);
+	optb_set_wrp(WRP_RW, &wrp_rw);
 	commit_optb();
 
 	return EC_SUCCESS;
@@ -240,14 +428,14 @@ int flash_physical_protect_at_boot(uint32_t new_flags)
  */
 static int registers_need_reset(void)
 {
-	uint32_t flags = flash_get_protect();
+	uint32_t flags = crec_flash_get_protect();
 	int ro_at_boot = (flags & EC_FLASH_PROTECT_RO_AT_BOOT) ? 1 : 0;
 	/* The RO region is write-protected by the WRP1AR range. */
 	uint32_t wrp1ar = STM32_OPTB_WRP1AR;
 	uint32_t ro_range = ro_at_boot ?
-		FLASH_WRP_RANGE(FLASH_RO_FIRST_PAGE_IDX,
-				  FLASH_RO_LAST_PAGE_IDX)
-		: FLASH_WRP_RANGE_DISABLED;
+				    FLASH_WRP_RANGE(FLASH_RO_FIRST_PAGE_IDX,
+						    FLASH_RO_LAST_PAGE_IDX) :
+				    FLASH_WRP_RANGE_DISABLED;
 
 	return ro_range != (wrp1ar & FLASH_WRP1X_MASK);
 }
@@ -255,7 +443,7 @@ static int registers_need_reset(void)
 /*****************************************************************************/
 /* Physical layer APIs */
 
-int flash_physical_write(int offset, int size, const char *data)
+int crec_flash_physical_write(int offset, int size, const char *data)
 {
 	uint32_t *address = (void *)(CONFIG_PROGRAM_MEMORY_BASE + offset);
 	int res = EC_SUCCESS;
@@ -264,6 +452,10 @@ int flash_physical_write(int offset, int size, const char *data)
 	int unaligned = (uint32_t)data & (STM32_FLASH_MIN_WRITE_SIZE - 1);
 	uint32_t *data32 = (void *)data;
 
+	/* Check Flash offset */
+	if (offset % STM32_FLASH_MIN_WRITE_SIZE)
+		return EC_ERROR_MEMORY_ALLOCATION;
+
 	if (unlock(FLASH_CR_LOCK) != EC_SUCCESS)
 		return EC_ERROR_UNKNOWN;
 
@@ -291,10 +483,10 @@ int flash_physical_write(int offset, int size, const char *data)
 
 		/* write the 2 words */
 		if (unaligned) {
-			*address++ = (uint32_t)data[0] | (data[1] << 8)
-				   | (data[2] << 16) | (data[3] << 24);
-			*address++ = (uint32_t)data[4] | (data[5] << 8)
-				   | (data[6] << 16) | (data[7] << 24);
+			*address++ = (uint32_t)data[0] | (data[1] << 8) |
+				     (data[2] << 16) | (data[3] << 24);
+			*address++ = (uint32_t)data[4] | (data[5] << 8) |
+				     (data[6] << 16) | (data[7] << 24);
 			data += STM32_FLASH_MIN_WRITE_SIZE;
 		} else {
 			*address++ = *data32++;
@@ -330,7 +522,7 @@ int flash_physical_write(int offset, int size, const char *data)
 	return res;
 }
 
-int flash_physical_erase(int offset, int size)
+int crec_flash_physical_erase(int offset, int size)
 {
 	int res = EC_SUCCESS;
 	int pg;
@@ -347,8 +539,8 @@ int flash_physical_erase(int offset, int size)
 		timestamp_t deadline;
 
 		/* select page to erase and PER bit */
-		STM32_FLASH_CR = (STM32_FLASH_CR & ~FLASH_CR_PNB_MASK)
-				| FLASH_CR_PER | FLASH_CR_PNB(pg);
+		STM32_FLASH_CR = (STM32_FLASH_CR & ~FLASH_CR_PNB_MASK) |
+				 FLASH_CR_PER | FLASH_CR_PNB(pg);
 
 		/* set STRT bit : start erase */
 		STM32_FLASH_CR |= FLASH_CR_STRT;
@@ -389,47 +581,48 @@ int flash_physical_erase(int offset, int size)
 	return res;
 }
 
-int flash_physical_get_protect(int block)
+int crec_flash_physical_get_protect(int block)
 {
-	uint32_t wrp1ar = STM32_FLASH_WRP1AR;
-	uint32_t wrp1br = STM32_FLASH_WRP1BR;
+	struct wrp_info wrp_ro;
+	struct wrp_info wrp_rw;
+
+	optb_get_wrp(WRP_RO, &wrp_ro);
+	optb_get_wrp(WRP_RW, &wrp_rw);
 
-	return ((block >= FLASH_WRP_START(wrp1ar)) &&
-		(block <= FLASH_WRP_END(wrp1ar))) ||
-		((block >= FLASH_WRP_START(wrp1br)) &&
-		(block <= FLASH_WRP_END(wrp1br)));
+	return ((block >= wrp_ro.start) && (block <= wrp_ro.end)) ||
+	       ((block >= wrp_rw.start) && (block <= wrp_rw.end));
 }
 
 /*
  * Note: This does not need to update _NOW flags, as get_protect_flags
  * in common code already does so.
  */
-uint32_t flash_physical_get_protect_flags(void)
+uint32_t crec_flash_physical_get_protect_flags(void)
 {
 	uint32_t flags = 0;
-	uint32_t wrp1ar = STM32_OPTB_WRP1AR;
-	uint32_t wrp1br = STM32_OPTB_WRP1BR;
+	struct wrp_info wrp_ro;
+	struct wrp_info wrp_rw;
 
-	/* RO region protection range is in WRP1AR range */
-	if (wrp1ar == FLASH_WRP_RANGE(FLASH_RO_FIRST_PAGE_IDX,
-					FLASH_RO_LAST_PAGE_IDX))
+	optb_get_wrp(WRP_RO, &wrp_ro);
+	optb_get_wrp(WRP_RW, &wrp_rw);
+
+	/* Check if RO is fully protected */
+	if (wrp_ro.start == FLASH_RO_FIRST_PAGE_IDX &&
+	    wrp_ro.end == FLASH_RO_LAST_PAGE_IDX)
 		flags |= EC_FLASH_PROTECT_RO_AT_BOOT;
-	/* Rollback and RW regions protection range is in WRP1BR range */
-	if (wrp1br != FLASH_WRP_RANGE_DISABLED) {
-		int end = FLASH_WRP_END(wrp1br);
-		int strt = FLASH_WRP_START(wrp1br);
 
+	if (wrp_rw.enable) {
 #ifdef CONFIG_ROLLBACK
-		if (strt <= FLASH_PAGE_ROLLBACK_FIRST_IDX &&
-		    end >= FLASH_PAGE_ROLLBACK_LAST_IDX)
+		if (wrp_rw.start <= FLASH_PAGE_ROLLBACK_FIRST_IDX &&
+		    wrp_rw.end >= FLASH_PAGE_ROLLBACK_LAST_IDX)
 			flags |= EC_FLASH_PROTECT_ROLLBACK_AT_BOOT;
 #endif /* CONFIG_ROLLBACK */
 #ifdef CONFIG_FLASH_PROTECT_RW
-		if (end == PHYSICAL_BANKS)
+		if (wrp_rw.end == PHYSICAL_BANKS)
 			flags |= EC_FLASH_PROTECT_RW_AT_BOOT;
 #endif /* CONFIG_FLASH_PROTECT_RW */
-		if (end == PHYSICAL_BANKS &&
-		    strt == WP_BANK_OFFSET + WP_BANK_COUNT &&
+		if (wrp_rw.end == PHYSICAL_BANKS &&
+		    wrp_rw.start == WP_BANK_OFFSET + WP_BANK_COUNT &&
 		    flags & EC_FLASH_PROTECT_RO_AT_BOOT)
 			flags |= EC_FLASH_PROTECT_ALL_AT_BOOT;
 	}
@@ -437,28 +630,25 @@ uint32_t flash_physical_get_protect_flags(void)
 	return flags;
 }
 
-int flash_physical_protect_now(int all)
+int crec_flash_physical_protect_now(int all)
 {
 	return EC_ERROR_INVAL;
 }
 
-uint32_t flash_physical_get_valid_flags(void)
+uint32_t crec_flash_physical_get_valid_flags(void)
 {
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-	       EC_FLASH_PROTECT_RO_NOW |
+	return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW |
 #ifdef CONFIG_FLASH_PROTECT_RW
-	       EC_FLASH_PROTECT_RW_AT_BOOT |
-	       EC_FLASH_PROTECT_RW_NOW |
+	       EC_FLASH_PROTECT_RW_AT_BOOT | EC_FLASH_PROTECT_RW_NOW |
 #endif
 #ifdef CONFIG_ROLLBACK
 	       EC_FLASH_PROTECT_ROLLBACK_AT_BOOT |
 	       EC_FLASH_PROTECT_ROLLBACK_NOW |
 #endif
-	       EC_FLASH_PROTECT_ALL_AT_BOOT |
-	       EC_FLASH_PROTECT_ALL_NOW;
+	       EC_FLASH_PROTECT_ALL_AT_BOOT | EC_FLASH_PROTECT_ALL_NOW;
 }
 
-uint32_t flash_physical_get_writable_flags(uint32_t cur_flags)
+uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
 {
 	uint32_t ret = 0;
 
@@ -470,13 +660,13 @@ uint32_t flash_physical_get_writable_flags(uint32_t cur_flags)
 	 * ALL/RW at-boot state can be set if WP GPIO is asserted and can always
 	 * be cleared.
 	 */
-	if (cur_flags & (EC_FLASH_PROTECT_ALL_AT_BOOT |
-			 EC_FLASH_PROTECT_GPIO_ASSERTED))
+	if (cur_flags &
+	    (EC_FLASH_PROTECT_ALL_AT_BOOT | EC_FLASH_PROTECT_GPIO_ASSERTED))
 		ret |= EC_FLASH_PROTECT_ALL_AT_BOOT;
 
 #ifdef CONFIG_FLASH_PROTECT_RW
-	if (cur_flags & (EC_FLASH_PROTECT_RW_AT_BOOT |
-			 EC_FLASH_PROTECT_GPIO_ASSERTED))
+	if (cur_flags &
+	    (EC_FLASH_PROTECT_RW_AT_BOOT | EC_FLASH_PROTECT_GPIO_ASSERTED))
 		ret |= EC_FLASH_PROTECT_RW_AT_BOOT;
 #endif
 
@@ -489,10 +679,25 @@ uint32_t flash_physical_get_writable_flags(uint32_t cur_flags)
 	return ret;
 }
 
-int flash_pre_init(void)
+int crec_flash_physical_force_reload(void)
+{
+	int rv = unlock(FLASH_CR_OPTLOCK);
+
+	if (rv)
+		return rv;
+
+	/* Force a reboot; this should never return. */
+	STM32_FLASH_CR = FLASH_CR_OBL_LAUNCH;
+	while (1)
+		;
+
+	return EC_ERROR_UNKNOWN;
+}
+
+int crec_flash_pre_init(void)
 {
 	uint32_t reset_flags = system_get_reset_flags();
-	uint32_t prot_flags = flash_get_protect();
+	uint32_t prot_flags = crec_flash_get_protect();
 	int need_reset = 0;
 
 	/*
@@ -511,7 +716,7 @@ int flash_pre_init(void)
 			 * update to the write protect register and reboot so
 			 * it takes effect.
 			 */
-			flash_physical_protect_at_boot(
+			crec_flash_physical_protect_at_boot(
 				EC_FLASH_PROTECT_RO_AT_BOOT);
 			need_reset = 1;
 		}
@@ -525,8 +730,8 @@ int flash_pre_init(void)
 			 * to the check above.  One of them should be able to
 			 * go away.
 			 */
-			flash_protect_at_boot(
-				prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT);
+			crec_flash_protect_at_boot(prot_flags &
+						   EC_FLASH_PROTECT_RO_AT_BOOT);
 			need_reset = 1;
 		}
 	} else {
@@ -540,7 +745,8 @@ int flash_pre_init(void)
 		}
 	}
 
-	if ((flash_physical_get_valid_flags() & EC_FLASH_PROTECT_ALL_AT_BOOT) &&
+	if ((crec_flash_physical_get_valid_flags() &
+	     EC_FLASH_PROTECT_ALL_AT_BOOT) &&
 	    (!!(prot_flags & EC_FLASH_PROTECT_ALL_AT_BOOT) !=
 	     !!(prot_flags & EC_FLASH_PROTECT_ALL_NOW))) {
 		/*
@@ -555,7 +761,8 @@ int flash_pre_init(void)
 	}
 
 #ifdef CONFIG_FLASH_PROTECT_RW
-	if ((flash_physical_get_valid_flags() & EC_FLASH_PROTECT_RW_AT_BOOT) &&
+	if ((crec_flash_physical_get_valid_flags() &
+	     EC_FLASH_PROTECT_RW_AT_BOOT) &&
 	    (!!(prot_flags & EC_FLASH_PROTECT_RW_AT_BOOT) !=
 	     !!(prot_flags & EC_FLASH_PROTECT_RW_NOW))) {
 		/* RW_AT_BOOT and RW_NOW do not match. */
@@ -564,7 +771,7 @@ int flash_pre_init(void)
 #endif
 
 #ifdef CONFIG_ROLLBACK
-	if ((flash_physical_get_valid_flags() &
+	if ((crec_flash_physical_get_valid_flags() &
 	     EC_FLASH_PROTECT_ROLLBACK_AT_BOOT) &&
 	    (!!(prot_flags & EC_FLASH_PROTECT_ROLLBACK_AT_BOOT) !=
 	     !!(prot_flags & EC_FLASH_PROTECT_ROLLBACK_NOW))) {
diff --git a/chip/stm32/flash-stm32h7.c b/chip/stm32/flash-stm32h7.c
index a541b962d2..2b9b594938 100644
--- a/chip/stm32/flash-stm32h7.c
+++ b/chip/stm32/flash-stm32h7.c
@@ -1,16 +1,17 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 /* Flash memory module for STM32H7 family */
 
-#include "common.h"
 #include "clock.h"
+#include "common.h"
 #include "cpu.h"
+#include "flash-regs.h"
 #include "flash.h"
 #include "hooks.h"
-#include "registers.h"
 #include "panic.h"
+#include "registers.h"
 #include "system.h"
 #include "task.h"
 #include "timer.h"
@@ -44,7 +45,7 @@
  * not what is called 'bank' in the common code (ie Write-Protect sectors)
  * both have the same number of 128KB blocks.
  */
-#define HWBANK_SIZE  (CONFIG_FLASH_SIZE / 2)
+#define HWBANK_SIZE (CONFIG_FLASH_SIZE_BYTES / 2)
 #define BLOCKS_PER_HWBANK (HWBANK_SIZE / CONFIG_FLASH_ERASE_SIZE)
 #define BLOCKS_HWBANK_MASK (BIT(BLOCKS_PER_HWBANK) - 1)
 
@@ -73,8 +74,8 @@ struct flash_wp_state {
 
 static inline int calculate_flash_timeout(void)
 {
-	return (FLASH_TIMEOUT_US *
-		(clock_get_freq() / SECOND) / CYCLE_PER_FLASH_LOOP);
+	return (FLASH_TIMEOUT_US * (clock_get_freq() / SECOND) /
+		CYCLE_PER_FLASH_LOOP);
 }
 
 static int unlock(int bank)
@@ -90,12 +91,11 @@ static int unlock(int bank)
 
 		STM32_FLASH_KEYR(bank) = FLASH_KEYR_KEY1;
 		STM32_FLASH_KEYR(bank) = FLASH_KEYR_KEY2;
-		asm volatile("dsb; isb");
 		ignore_bus_fault(0);
 	}
 
-	return (STM32_FLASH_CR(bank) & FLASH_CR_LOCK) ? EC_ERROR_UNKNOWN
-						      : EC_SUCCESS;
+	return (STM32_FLASH_CR(bank) & FLASH_CR_LOCK) ? EC_ERROR_UNKNOWN :
+							EC_SUCCESS;
 }
 
 static void lock(int bank)
@@ -111,11 +111,7 @@ static int unlock_optb(void)
 	if (unlock(0))
 		return EC_ERROR_UNKNOWN;
 
-	/*
-	 * Always use bank 0 flash controller as there is only one option bytes
-	 * set for both banks.
-	 */
-	if (STM32_FLASH_OPTCR(0) & FLASH_OPTCR_OPTLOCK) {
+	if (flash_option_bytes_locked()) {
 		/*
 		 * We may have already locked the flash module and get a bus
 		 * fault in the attempt to unlock. Need to disable bus fault
@@ -123,28 +119,25 @@ static int unlock_optb(void)
 		 */
 		ignore_bus_fault(1);
 
-		STM32_FLASH_OPTKEYR(0) = FLASH_OPTKEYR_KEY1;
-		STM32_FLASH_OPTKEYR(0) = FLASH_OPTKEYR_KEY2;
-		asm volatile("dsb; isb");
+		unlock_flash_option_bytes();
 		ignore_bus_fault(0);
 	}
 
-	return STM32_FLASH_OPTCR(0) & FLASH_OPTCR_OPTLOCK ? EC_ERROR_UNKNOWN
-							  : EC_SUCCESS;
+	return flash_option_bytes_locked() ? EC_ERROR_UNKNOWN : EC_SUCCESS;
 }
 
 static int commit_optb(void)
 {
 	/* might use this before timer_init, cannot use get_time/usleep */
-	int timeout = (FLASH_OPT_PRG_TIMEOUT_US *
-		(clock_get_freq() / SECOND) / CYCLE_PER_FLASH_LOOP);
+	int timeout = (FLASH_OPT_PRG_TIMEOUT_US * (clock_get_freq() / SECOND) /
+		       CYCLE_PER_FLASH_LOOP);
 
 	STM32_FLASH_OPTCR(0) |= FLASH_OPTCR_OPTSTART;
 
 	while (STM32_FLASH_OPTSR_CUR(0) & FLASH_OPTSR_BUSY && timeout-- > 0)
 		;
 
-	STM32_FLASH_OPTCR(0) |= FLASH_OPTCR_OPTLOCK;
+	lock_flash_option_bytes();
 	lock(0);
 
 	return (timeout > 0) ? EC_SUCCESS : EC_ERROR_TIMEOUT;
@@ -155,11 +148,91 @@ static void protect_blocks(uint32_t blocks)
 	if (unlock_optb())
 		return;
 	STM32_FLASH_WPSN_PRG(0) &= ~(blocks & BLOCKS_HWBANK_MASK);
-	STM32_FLASH_WPSN_PRG(1) &= ~((blocks >> BLOCKS_PER_HWBANK)
-				& BLOCKS_HWBANK_MASK);
+	STM32_FLASH_WPSN_PRG(1) &=
+		~((blocks >> BLOCKS_PER_HWBANK) & BLOCKS_HWBANK_MASK);
 	commit_optb();
 }
 
+/*
+ * Helper function definitions for consistency with F4 to enable flash
+ * physical unitesting
+ */
+void unlock_flash_control_register(void)
+{
+	unlock(0);
+	unlock(1);
+}
+
+void unlock_flash_option_bytes(void)
+{
+	/*
+	 * Always use bank 0 flash controller as there is only one option bytes
+	 * set for both banks. See http://b/181130245
+	 *
+	 * Consecutively program values. Ref: RM0433:4.9.2
+	 */
+	STM32_FLASH_OPTKEYR(0) = FLASH_OPTKEYR_KEY1;
+	STM32_FLASH_OPTKEYR(0) = FLASH_OPTKEYR_KEY2;
+}
+
+void disable_flash_option_bytes(void)
+{
+	ignore_bus_fault(1);
+	/*
+	 * Always use bank 0 flash controller as there is only one option bytes
+	 * set for both banks. See http://b/181130245
+	 *
+	 * Writing anything other than the pre-defined keys to the option key
+	 * register results in a bus fault and the register being locked until
+	 * reboot (even with a further correct key write).
+	 */
+	STM32_FLASH_OPTKEYR(0) = 0xffffffff;
+	ignore_bus_fault(0);
+}
+
+void disable_flash_control_register(void)
+{
+	ignore_bus_fault(1);
+	/*
+	 * Writing anything other than the pre-defined keys to a key
+	 * register results in a bus fault and the register being locked until
+	 * reboot (even with a further correct key write).
+	 */
+	STM32_FLASH_KEYR(0) = 0xffffffff;
+	STM32_FLASH_KEYR(1) = 0xffffffff;
+	ignore_bus_fault(0);
+}
+
+void lock_flash_control_register(void)
+{
+	lock(0);
+	lock(1);
+}
+
+void lock_flash_option_bytes(void)
+{
+	/*
+	 * Always use bank 0 flash controller as there is only one option bytes
+	 * set for both banks. See http://b/181130245
+	 */
+	STM32_FLASH_OPTCR(0) |= FLASH_OPTCR_OPTLOCK;
+}
+
+bool flash_option_bytes_locked(void)
+{
+	/*
+	 * Always use bank 0 flash controller as there is only one option bytes
+	 * set for both banks. See http://b/181130245
+	 */
+	return !!(STM32_FLASH_OPTCR(0) & FLASH_OPTCR_OPTLOCK);
+}
+
+bool flash_control_register_locked(void)
+{
+	return !!(STM32_FLASH_CR(0) & FLASH_CR_LOCK) &&
+	       !!(STM32_FLASH_CR(1) & FLASH_CR_LOCK);
+}
+
 /*
  * If RDP as PSTATE option is defined, use that as 'Write Protect enabled' flag:
  * it makes no sense to be able to unlock RO, as that'd allow flashing
@@ -177,8 +250,8 @@ static void protect_blocks(uint32_t blocks)
 static int is_wp_enabled(void)
 {
 #ifdef CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE
-	return (STM32_FLASH_OPTSR_CUR(0) & FLASH_OPTSR_RDP_MASK)
-		!= FLASH_OPTSR_RDP_LEVEL_0;
+	return (STM32_FLASH_OPTSR_CUR(0) & FLASH_OPTSR_RDP_MASK) !=
+	       FLASH_OPTSR_RDP_LEVEL_0;
 #else
 	return !!(STM32_FLASH_OPTSR_CUR(0) & FLASH_OPTSR_RSS1);
 #endif
@@ -212,7 +285,7 @@ static int set_wp(int enabled)
 /*****************************************************************************/
 /* Physical layer APIs */
 
-int flash_physical_write(int offset, int size, const char *data)
+int crec_flash_physical_write(int offset, int size, const char *data)
 {
 	int res = EC_SUCCESS;
 	int bank = offset / HWBANK_SIZE;
@@ -236,8 +309,8 @@ int flash_physical_write(int offset, int size, const char *data)
 	STM32_FLASH_CCR(bank) = FLASH_CCR_ERR_MASK;
 
 	/* select write parallelism */
-	STM32_FLASH_CR(bank) = (STM32_FLASH_CR(bank) & ~FLASH_CR_PSIZE_MASK)
-			| DEFAULT_PSIZE;
+	STM32_FLASH_CR(bank) = (STM32_FLASH_CR(bank) & ~FLASH_CR_PSIZE_MASK) |
+			       DEFAULT_PSIZE;
 
 	/* set PG bit */
 	STM32_FLASH_CR(bank) |= FLASH_CR_PG;
@@ -251,18 +324,21 @@ int flash_physical_write(int offset, int size, const char *data)
 
 		/* write a 256-bit flash word */
 		if (unaligned) {
-			for (i = 0; i < CONFIG_FLASH_WRITE_SIZE / 4; i++,
-								     data += 4)
-				*address++ = (uint32_t)data[0] | (data[1] << 8)
-					   | (data[2] << 16) | (data[3] << 24);
+			for (i = 0; i < CONFIG_FLASH_WRITE_SIZE / 4;
+			     i++, data += 4)
+				*address++ = (uint32_t)data[0] |
+					     (data[1] << 8) | (data[2] << 16) |
+					     (data[3] << 24);
 		} else {
 			for (i = 0; i < CONFIG_FLASH_WRITE_SIZE / 4; i++)
 				*address++ = *data32++;
 		}
 
 		/* Wait for writes to complete */
-		for (i = 0; (STM32_FLASH_SR(bank) &
-		     (FLASH_SR_WBNE | FLASH_SR_QW)) && (i < timeout); i++)
+		for (i = 0;
+		     (STM32_FLASH_SR(bank) & (FLASH_SR_WBNE | FLASH_SR_QW)) &&
+		     (i < timeout);
+		     i++)
 			;
 
 		if (STM32_FLASH_SR(bank) & (FLASH_SR_WBNE | FLASH_SR_QW)) {
@@ -290,7 +366,7 @@ int flash_physical_write(int offset, int size, const char *data)
 	return res;
 }
 
-int flash_physical_erase(int offset, int size)
+int crec_flash_physical_erase(int offset, int size)
 {
 	int res = EC_SUCCESS;
 	int bank = offset / HWBANK_SIZE;
@@ -311,16 +387,16 @@ int flash_physical_erase(int offset, int size)
 	STM32_FLASH_CCR(bank) = FLASH_CCR_ERR_MASK;
 
 	/* select erase parallelism */
-	STM32_FLASH_CR(bank) = (STM32_FLASH_CR(bank) & ~FLASH_CR_PSIZE_MASK)
-			| DEFAULT_PSIZE;
+	STM32_FLASH_CR(bank) = (STM32_FLASH_CR(bank) & ~FLASH_CR_PSIZE_MASK) |
+			       DEFAULT_PSIZE;
 
 	for (sect = offset / CONFIG_FLASH_ERASE_SIZE; sect < last; sect++) {
 		timestamp_t deadline;
 
 		/* select page to erase and PER bit */
-		STM32_FLASH_CR(bank) = (STM32_FLASH_CR(bank)
-					& ~FLASH_CR_SNB_MASK)
-				| FLASH_CR_SER | FLASH_CR_SNB(sect);
+		STM32_FLASH_CR(bank) =
+			(STM32_FLASH_CR(bank) & ~FLASH_CR_SNB_MASK) |
+			FLASH_CR_SER | FLASH_CR_SNB(sect);
 
 		/* set STRT bit : start erase */
 		STM32_FLASH_CR(bank) |= FLASH_CR_STRT;
@@ -335,7 +411,12 @@ int flash_physical_erase(int offset, int size)
 		/* Wait for erase to complete */
 		while ((STM32_FLASH_SR(bank) & FLASH_SR_BUSY) &&
 		       (get_time().val < deadline.val)) {
-			usleep(5000);
+			/*
+			 * Interrupts may not be enabled, so we are using
+			 * udelay() instead of usleep() which can trigger
+			 * Forced Hard Fault (see b/180761547).
+			 */
+			udelay(5000);
 		}
 		if (STM32_FLASH_SR(bank) & FLASH_SR_BUSY) {
 			res = EC_ERROR_TIMEOUT;
@@ -366,7 +447,7 @@ int flash_physical_erase(int offset, int size)
 	return res;
 }
 
-int flash_physical_get_protect(int block)
+int crec_flash_physical_get_protect(int block)
 {
 	int bank = block / BLOCKS_PER_HWBANK;
 	int index = block % BLOCKS_PER_HWBANK;
@@ -378,7 +459,7 @@ int flash_physical_get_protect(int block)
  * Note: This does not need to update _NOW flags, as flash_get_protect
  * in common code already does so.
  */
-uint32_t flash_physical_get_protect_flags(void)
+uint32_t crec_flash_physical_get_protect_flags(void)
 {
 	uint32_t flags = 0;
 
@@ -398,7 +479,7 @@ uint32_t flash_physical_get_protect_flags(void)
 #define WP_RANGE(start, count) (((1 << (count)) - 1) << (start))
 #define RO_WP_RANGE WP_RANGE(WP_BANK_OFFSET, WP_BANK_COUNT)
 
-int flash_physical_protect_now(int all)
+int crec_flash_physical_protect_now(int all)
 {
 	protect_blocks(RO_WP_RANGE);
 
@@ -411,24 +492,20 @@ int flash_physical_protect_now(int all)
 	 * permanently locked until reset, a correct keyring write
 	 * will not unlock it.
 	 */
-	ignore_bus_fault(1);
 
 	if (all) {
 		/* cannot do any write/erase access until next reboot */
-		STM32_FLASH_KEYR(0) = 0xffffffff;
-		STM32_FLASH_KEYR(1) = 0xffffffff;
+		disable_flash_control_register();
 		access_disabled = 1;
 	}
 	/* cannot modify the WP bits in the option bytes until reboot */
-	STM32_FLASH_OPTKEYR(0) = 0xffffffff;
+	disable_flash_option_bytes();
 	option_disabled = 1;
-	asm volatile("dsb; isb");
-	ignore_bus_fault(0);
 
 	return EC_SUCCESS;
 }
 
-int flash_physical_protect_at_boot(uint32_t new_flags)
+int crec_flash_physical_protect_at_boot(uint32_t new_flags)
 {
 	int new_wp_enable = !!(new_flags & EC_FLASH_PROTECT_RO_AT_BOOT);
 
@@ -438,14 +515,13 @@ int flash_physical_protect_at_boot(uint32_t new_flags)
 	return EC_SUCCESS;
 }
 
-uint32_t flash_physical_get_valid_flags(void)
+uint32_t crec_flash_physical_get_valid_flags(void)
 {
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-	       EC_FLASH_PROTECT_RO_NOW |
+	return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW |
 	       EC_FLASH_PROTECT_ALL_NOW;
 }
 
-uint32_t flash_physical_get_writable_flags(uint32_t cur_flags)
+uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
 {
 	uint32_t ret = 0;
 
@@ -464,7 +540,7 @@ uint32_t flash_physical_get_writable_flags(uint32_t cur_flags)
 	return ret;
 }
 
-int flash_physical_restore_state(void)
+int crec_flash_physical_restore_state(void)
 {
 	uint32_t reset_flags = system_get_reset_flags();
 	int version, size;
@@ -473,11 +549,11 @@ int flash_physical_restore_state(void)
 	/*
 	 * If we have already jumped between images, an earlier image could
 	 * have applied write protection. We simply need to represent these
-         * irreversible flags to other components.
+	 * irreversible flags to other components.
 	 */
 	if (reset_flags & EC_RESET_FLAG_SYSJUMP) {
 		prev = (const struct flash_wp_state *)system_get_jump_tag(
-				FLASH_SYSJUMP_TAG, &version, &size);
+			FLASH_SYSJUMP_TAG, &version, &size);
 		if (prev && version == FLASH_HOOK_VERSION &&
 		    size == sizeof(*prev)) {
 			access_disabled = prev->access_disabled;
@@ -490,14 +566,14 @@ int flash_physical_restore_state(void)
 	return 0;
 }
 
-int flash_pre_init(void)
+int crec_flash_pre_init(void)
 {
 	uint32_t reset_flags = system_get_reset_flags();
-	uint32_t prot_flags = flash_get_protect();
+	uint32_t prot_flags = crec_flash_get_protect();
 	uint32_t unwanted_prot_flags = EC_FLASH_PROTECT_ALL_NOW |
-		EC_FLASH_PROTECT_ERROR_INCONSISTENT;
+				       EC_FLASH_PROTECT_ERROR_INCONSISTENT;
 
-	if (flash_physical_restore_state())
+	if (crec_flash_physical_restore_state())
 		return EC_SUCCESS;
 
 	/*
@@ -516,13 +592,13 @@ int flash_pre_init(void)
 		    !(prot_flags & EC_FLASH_PROTECT_RO_NOW)) {
 			int rv;
 
-			rv = flash_set_protect(EC_FLASH_PROTECT_RO_NOW,
-					       EC_FLASH_PROTECT_RO_NOW);
+			rv = crec_flash_set_protect(EC_FLASH_PROTECT_RO_NOW,
+						    EC_FLASH_PROTECT_RO_NOW);
 			if (rv)
 				return rv;
 
 			/* Re-read flags */
-			prot_flags = flash_get_protect();
+			prot_flags = crec_flash_get_protect();
 		}
 	} else {
 		/* Don't want RO flash protected */
diff --git a/chip/stm32/flash-stm32l.c b/chip/stm32/flash-stm32l.c
index a151a26cf8..b83f8961af 100644
--- a/chip/stm32/flash-stm32l.c
+++ b/chip/stm32/flash-stm32l.c
@@ -1,13 +1,15 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Flash memory module for Chrome EC */
 
+#include "builtin/assert.h"
 #include "clock.h"
 #include "console.h"
 #include "flash.h"
+#include "panic.h"
 #include "registers.h"
 #include "system.h"
 #include "task.h"
@@ -34,7 +36,8 @@ static void lock(void)
 	ignore_bus_fault(1);
 
 	STM32_FLASH_PECR = STM32_FLASH_PECR_PE_LOCK |
-		STM32_FLASH_PECR_PRG_LOCK | STM32_FLASH_PECR_OPT_LOCK;
+			   STM32_FLASH_PECR_PRG_LOCK |
+			   STM32_FLASH_PECR_OPT_LOCK;
 
 	ignore_bus_fault(0);
 }
@@ -105,8 +108,8 @@ static uint16_t read_optb(int offset)
  */
 static void write_optb(int offset, uint16_t value)
 {
-	REG32(STM32_OPTB_BASE + offset) =
-		(uint32_t)value | ((uint32_t)(~value) << 16);
+	REG32(STM32_OPTB_BASE + offset) = (uint32_t)value |
+					  ((uint32_t)(~value) << 16);
 }
 
 /**
@@ -115,7 +118,7 @@ static void write_optb(int offset, uint16_t value)
 static uint32_t read_optb_wrp(void)
 {
 	return read_optb(STM32_OPTB_WRP1L) |
-		((uint32_t)read_optb(STM32_OPTB_WRP1H) << 16);
+	       ((uint32_t)read_optb(STM32_OPTB_WRP1H) << 16);
 }
 
 /**
@@ -133,8 +136,8 @@ static void write_optb_wrp(uint32_t value)
  * This function lives in internal RAM, as we cannot read flash during writing.
  * You must not call other functions from this one or declare it static.
  */
-void  __attribute__((section(".iram.text")))
-	iram_flash_write(uint32_t *addr, uint32_t *data)
+void __attribute__((section(".iram.text")))
+iram_flash_write(uint32_t *addr, uint32_t *data)
 {
 	int i;
 
@@ -158,7 +161,7 @@ void  __attribute__((section(".iram.text")))
 	STM32_FLASH_PECR &= ~(STM32_FLASH_PECR_PROG | STM32_FLASH_PECR_FPRG);
 }
 
-int flash_physical_write(int offset, int size, const char *data)
+int crec_flash_physical_write(int offset, int size, const char *data)
 {
 	uint32_t *data32 = (uint32_t *)data;
 	uint32_t *address = (uint32_t *)(CONFIG_PROGRAM_MEMORY_BASE + offset);
@@ -189,7 +192,7 @@ int flash_physical_write(int offset, int size, const char *data)
 
 	/* Update flash timeout based on current clock speed */
 	flash_timeout_loop = FLASH_TIMEOUT_MS * (clock_get_freq() / MSEC) /
-		CYCLE_PER_FLASH_LOOP;
+			     CYCLE_PER_FLASH_LOOP;
 
 	while (size > 0) {
 		/*
@@ -204,7 +207,8 @@ int flash_physical_write(int offset, int size, const char *data)
 
 			/* Wait for writes to complete */
 			for (i = 0; ((STM32_FLASH_SR & 9) != 8) &&
-				     (i < flash_timeout_loop); i++)
+				    (i < flash_timeout_loop);
+			     i++)
 				;
 
 			size -= sizeof(uint32_t);
@@ -240,7 +244,7 @@ int flash_physical_write(int offset, int size, const char *data)
 	return res;
 }
 
-int flash_physical_erase(int offset, int size)
+int crec_flash_physical_erase(int offset, int size)
 {
 	uint32_t *address;
 	int res = EC_SUCCESS;
@@ -257,13 +261,13 @@ int flash_physical_erase(int offset, int size)
 
 	for (address = (uint32_t *)(CONFIG_PROGRAM_MEMORY_BASE + offset);
 	     size > 0; size -= CONFIG_FLASH_ERASE_SIZE,
-	     address += CONFIG_FLASH_ERASE_SIZE / sizeof(uint32_t)) {
+	    address += CONFIG_FLASH_ERASE_SIZE / sizeof(uint32_t)) {
 		timestamp_t deadline;
 
 		/* Do nothing if already erased */
-		if (flash_is_erased((uint32_t)address -
-				    CONFIG_PROGRAM_MEMORY_BASE,
-				    CONFIG_FLASH_ERASE_SIZE))
+		if (crec_flash_is_erased((uint32_t)address -
+						 CONFIG_PROGRAM_MEMORY_BASE,
+					 CONFIG_FLASH_ERASE_SIZE))
 			continue;
 
 		/* Start erase */
@@ -304,20 +308,20 @@ int flash_physical_erase(int offset, int size)
 	return res;
 }
 
-int flash_physical_get_protect(int block)
+int crec_flash_physical_get_protect(int block)
 {
 	/*
 	 * If the entire flash interface is locked, then all blocks are
 	 * protected until reboot.
 	 */
-	if (flash_physical_get_protect_flags() & EC_FLASH_PROTECT_ALL_NOW)
+	if (crec_flash_physical_get_protect_flags() & EC_FLASH_PROTECT_ALL_NOW)
 		return 1;
 
 	/* Check the active write protect status */
 	return STM32_FLASH_WRPR & BIT(block);
 }
 
-int flash_physical_protect_at_boot(uint32_t new_flags)
+int crec_flash_physical_protect_at_boot(uint32_t new_flags)
 {
 	uint32_t prot;
 	uint32_t mask = (BIT(WP_BANK_COUNT) - 1) << WP_BANK_OFFSET;
@@ -336,7 +340,7 @@ int flash_physical_protect_at_boot(uint32_t new_flags)
 		prot &= ~mask;
 
 	if (prot == read_optb_wrp())
-		return EC_SUCCESS;  /* No bits changed */
+		return EC_SUCCESS; /* No bits changed */
 
 	/* Unlock option bytes */
 	rv = unlock(STM32_FLASH_PECR_OPT_LOCK);
@@ -352,7 +356,7 @@ int flash_physical_protect_at_boot(uint32_t new_flags)
 	return EC_SUCCESS;
 }
 
-int flash_physical_force_reload(void)
+int crec_flash_physical_force_reload(void)
 {
 	int rv = unlock(STM32_FLASH_PECR_OPT_LOCK);
 
@@ -367,7 +371,7 @@ int flash_physical_force_reload(void)
 	return EC_ERROR_UNKNOWN;
 }
 
-uint32_t flash_physical_get_protect_flags(void)
+uint32_t crec_flash_physical_get_protect_flags(void)
 {
 	uint32_t flags = 0;
 
@@ -382,7 +386,7 @@ uint32_t flash_physical_get_protect_flags(void)
 	return flags;
 }
 
-int flash_physical_protect_now(int all)
+int crec_flash_physical_protect_now(int all)
 {
 	if (all) {
 		/* Re-lock the registers if they're unlocked */
@@ -400,14 +404,13 @@ int flash_physical_protect_now(int all)
 	}
 }
 
-uint32_t flash_physical_get_valid_flags(void)
+uint32_t crec_flash_physical_get_valid_flags(void)
 {
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-	       EC_FLASH_PROTECT_RO_NOW |
+	return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW |
 	       EC_FLASH_PROTECT_ALL_NOW;
 }
 
-uint32_t flash_physical_get_writable_flags(uint32_t cur_flags)
+uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
 {
 	uint32_t ret = 0;
 
@@ -426,10 +429,10 @@ uint32_t flash_physical_get_writable_flags(uint32_t cur_flags)
 	return ret;
 }
 
-int flash_pre_init(void)
+int crec_flash_pre_init(void)
 {
 	uint32_t reset_flags = system_get_reset_flags();
-	uint32_t prot_flags = flash_get_protect();
+	uint32_t prot_flags = crec_flash_get_protect();
 	int need_reset = 0;
 
 	/*
@@ -448,7 +451,7 @@ int flash_pre_init(void)
 			 * update to the write protect register and reboot so
 			 * it takes effect.
 			 */
-			flash_protect_at_boot(EC_FLASH_PROTECT_RO_AT_BOOT);
+			crec_flash_protect_at_boot(EC_FLASH_PROTECT_RO_AT_BOOT);
 			need_reset = 1;
 		}
 
@@ -457,8 +460,8 @@ int flash_pre_init(void)
 			 * Write protect register was in an inconsistent state.
 			 * Set it back to a good state and reboot.
 			 */
-			flash_protect_at_boot(prot_flags &
-					EC_FLASH_PROTECT_RO_AT_BOOT);
+			crec_flash_protect_at_boot(prot_flags &
+						   EC_FLASH_PROTECT_RO_AT_BOOT);
 			need_reset = 1;
 		}
 	} else if (prot_flags & (EC_FLASH_PROTECT_RO_NOW |
diff --git a/chip/stm32/fpu.c b/chip/stm32/fpu.c
new file mode 100644
index 0000000000..2bf0a0b803
--- /dev/null
+++ b/chip/stm32/fpu.c
@@ -0,0 +1,43 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "hooks.h"
+#include "registers.h"
+#include "task.h"
+
+static void fpu_init(void)
+{
+	task_enable_irq(STM32_IRQ_FPU);
+}
+DECLARE_HOOK(HOOK_INIT, fpu_init, HOOK_PRIO_DEFAULT);
+
+__attribute__((naked)) void IRQ_HANDLER(STM32_IRQ_FPU)(void)
+{
+	/* Naked call so we can extract raw LR and SP */
+	asm volatile("mov r0, lr\n"
+		     "mov r1, sp\n"
+		     /*
+		      * By default Floating-point context control register
+		      * (FPCCR) have ASPEN and LSPEN bits enabled (see reset
+		      * value in PM0214, 4.6.2 Floating-point context control
+		      * register (FPCCR)). This means that lazy floating-point
+		      * context save and restore is enabled. To save context on
+		      * stack it's necessary to perform read access from FPU
+		      * (see PM0214 4.6.7 Enabling and clearing FPU exception
+		      * interrupts).
+		      */
+		     "vmrs r2, fpscr\n"
+		     /*
+		      * Must push registers in pairs to keep 64-bit aligned
+		      * stack for ARM EABI.
+		      */
+		     "push {r0, lr}\n"
+		     "bl fpu_irq\n"
+		     "pop {r0, pc}\n");
+}
+const struct irq_priority __keep IRQ_PRIORITY(STM32_IRQ_FPU)
+	__attribute__((section(".rodata.irqprio"))) = { STM32_IRQ_FPU,
+							0 }; /* highest priority
+							      */
diff --git a/chip/stm32/gpio-f0-l.c b/chip/stm32/gpio-f0-l.c
index 55628cb6d4..3482a8a552 100644
--- a/chip/stm32/gpio-f0-l.c
+++ b/chip/stm32/gpio-f0-l.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,6 +9,7 @@
  * These functions are shared by the STM32F0 and STM32L variants.
  */
 
+#include "builtin/assert.h"
 #include "common.h"
 #include "gpio_chip.h"
 #include "registers.h"
@@ -62,11 +63,10 @@ int gpio_get_flags_by_mask(uint32_t port, uint32_t mask)
 			flags |= GPIO_LOW;
 	}
 
-
-	if (STM32_EXTI_RTSR & mask)
-		flags |= GPIO_INT_F_RISING;
 	if (STM32_EXTI_RTSR & mask)
 		flags |= GPIO_INT_F_RISING;
+	if (STM32_EXTI_FTSR & mask)
+		flags |= GPIO_INT_F_FALLING;
 
 	return flags;
 }
@@ -80,9 +80,9 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
 	/* Set up pullup / pulldown */
 	val = STM32_GPIO_PUPDR(port) & ~mask2;
 	if (flags & GPIO_PULL_UP)
-		val |= 0x55555555 & mask2;	/* Pull Up = 01 */
+		val |= 0x55555555 & mask2; /* Pull Up = 01 */
 	else if (flags & GPIO_PULL_DOWN)
-		val |= 0xaaaaaaaa & mask2;	/* Pull Down = 10 */
+		val |= 0xaaaaaaaa & mask2; /* Pull Down = 10 */
 	STM32_GPIO_PUPDR(port) = val;
 
 	/*
@@ -133,10 +133,10 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
 }
 
 void gpio_set_alternate_function(uint32_t port, uint32_t mask,
-				enum gpio_alternate_func func)
+				 enum gpio_alternate_func func)
 {
 	/* Ensure that the func parameter isn't overflowed */
-	BUILD_ASSERT((int) MODULE_COUNT <= (int) GPIO_ALT_FUNC_MAX);
+	BUILD_ASSERT((int)MODULE_COUNT <= (int)GPIO_ALT_FUNC_MAX);
 
 	int bit;
 	uint32_t half;
diff --git a/chip/stm32/gpio-stm32f0.c b/chip/stm32/gpio-stm32f0.c
index d7e7aa4391..8fbc77a85c 100644
--- a/chip/stm32/gpio-stm32f0.c
+++ b/chip/stm32/gpio-stm32f0.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/stm32/gpio-stm32f3.c b/chip/stm32/gpio-stm32f3.c
index bfc2631de8..113aadc1e6 100644
--- a/chip/stm32/gpio-stm32f3.c
+++ b/chip/stm32/gpio-stm32f3.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,6 +8,7 @@
 #include "clock.h"
 #include "common.h"
 #include "gpio.h"
+#include "gpio_chip.h"
 #include "hooks.h"
 #include "registers.h"
 #include "task.h"
@@ -40,12 +41,17 @@ static void gpio_init(void)
 }
 DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
 
-DECLARE_IRQ(STM32_IRQ_EXTI0, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI1, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI2, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI3, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI4, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI9_5, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI15_10, gpio_interrupt, 1);
+static void _gpio_interrupt(void)
+{
+	gpio_interrupt();
+}
+
+DECLARE_IRQ(STM32_IRQ_EXTI0, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI1, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI2, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI3, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI4, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI9_5, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI15_10, _gpio_interrupt, 1);
 
 #include "gpio-f0-l.c"
diff --git a/chip/stm32/gpio-stm32f4.c b/chip/stm32/gpio-stm32f4.c
index 4a4e095a71..8e8658b7f9 100644
--- a/chip/stm32/gpio-stm32f4.c
+++ b/chip/stm32/gpio-stm32f4.c
@@ -1,13 +1,15 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* GPIO module for Chrome EC */
 
+#include "builtin/assert.h"
 #include "clock.h"
 #include "common.h"
 #include "gpio.h"
+#include "gpio_chip.h"
 #include "hooks.h"
 #include "registers.h"
 #include "task.h"
@@ -16,12 +18,12 @@
 int gpio_required_clocks(void)
 {
 	const int gpio_ports_used = (0
-#		define GPIO(name, pin, flags) pin
-#		define GPIO_INT(name, pin, flags, signal) pin
-#		define ALTERNATE(pinmask, function, module, flagz) pinmask
-#		define PIN(port, index) | STM32_RCC_AHB1ENR_GPIO_PORT ## port
-#		define PIN_MASK(port, mask) PIN(port, 0)
-#		include "gpio.wrap"
+#define GPIO(name, pin, flags) pin
+#define GPIO_INT(name, pin, flags, signal) pin
+#define ALTERNATE(pinmask, function, module, flagz) pinmask
+#define PIN(port, index) | STM32_RCC_AHB1ENR_GPIO_PORT##port
+#define PIN_MASK(port, mask) PIN(port, 0)
+#include "gpio.wrap"
 	);
 
 	/*
@@ -55,12 +57,17 @@ static void gpio_init(void)
 }
 DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
 
-DECLARE_IRQ(STM32_IRQ_EXTI0, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI1, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI2, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI3, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI4, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI9_5, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI15_10, gpio_interrupt, 1);
+static void _gpio_interrupt(void)
+{
+	gpio_interrupt();
+}
+
+DECLARE_IRQ(STM32_IRQ_EXTI0, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI1, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI2, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI3, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI4, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI9_5, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI15_10, _gpio_interrupt, 1);
 
 #include "gpio-f0-l.c"
diff --git a/chip/stm32/gpio-stm32g4.c b/chip/stm32/gpio-stm32g4.c
index 55b2c11e7b..8d1529a7ad 100644
--- a/chip/stm32/gpio-stm32g4.c
+++ b/chip/stm32/gpio-stm32g4.c
@@ -1,13 +1,15 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* GPIO module for Chrome EC */
 
+#include "builtin/assert.h"
 #include "clock.h"
 #include "common.h"
 #include "gpio.h"
+#include "gpio_chip.h"
 #include "hooks.h"
 #include "registers.h"
 #include "task.h"
@@ -16,12 +18,12 @@
 int gpio_required_clocks(void)
 {
 	const int gpio_ports_used = (0
-#		define GPIO(name, pin, flags) pin
-#		define GPIO_INT(name, pin, flags, signal) pin
-#		define ALTERNATE(pinmask, function, module, flagz) pinmask
-#		define PIN(port, index) | STM32_RCC_AHB2ENR_GPIO_PORT ## port
-#		define PIN_MASK(port, mask) PIN(port, 0)
-#		include "gpio.wrap"
+#define GPIO(name, pin, flags) pin
+#define GPIO_INT(name, pin, flags, signal) pin
+#define ALTERNATE(pinmask, function, module, flagz) pinmask
+#define PIN(port, index) | STM32_RCC_AHB2ENR_GPIO_PORT##port
+#define PIN_MASK(port, mask) PIN(port, 0)
+#include "gpio.wrap"
 	);
 
 	/*
@@ -55,12 +57,17 @@ static void gpio_init(void)
 }
 DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
 
-DECLARE_IRQ(STM32_IRQ_EXTI0, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI1, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI2, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI3, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI4, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI9_5, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI15_10, gpio_interrupt, 1);
+static void _gpio_interrupt(void)
+{
+	gpio_interrupt();
+}
+
+DECLARE_IRQ(STM32_IRQ_EXTI0, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI1, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI2, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI3, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI4, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI9_5, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI15_10, _gpio_interrupt, 1);
 
 #include "gpio-f0-l.c"
diff --git a/chip/stm32/gpio-stm32h7.c b/chip/stm32/gpio-stm32h7.c
index a2fb97225d..66c696e836 100644
--- a/chip/stm32/gpio-stm32h7.c
+++ b/chip/stm32/gpio-stm32h7.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,6 +8,7 @@
 #include "clock.h"
 #include "common.h"
 #include "gpio.h"
+#include "gpio_chip.h"
 #include "hooks.h"
 #include "registers.h"
 #include "task.h"
@@ -32,16 +33,20 @@ static void gpio_init(void)
 	task_enable_irq(STM32_IRQ_EXTI4);
 	task_enable_irq(STM32_IRQ_EXTI9_5);
 	task_enable_irq(STM32_IRQ_EXTI15_10);
-
 }
 DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
 
-DECLARE_IRQ(STM32_IRQ_EXTI0, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI1, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI2, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI3, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI4, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI9_5, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI15_10, gpio_interrupt, 1);
+static void _gpio_interrupt(void)
+{
+	gpio_interrupt();
+}
+
+DECLARE_IRQ(STM32_IRQ_EXTI0, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI1, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI2, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI3, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI4, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI9_5, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI15_10, _gpio_interrupt, 1);
 
 #include "gpio-f0-l.c"
diff --git a/chip/stm32/gpio-stm32l.c b/chip/stm32/gpio-stm32l.c
index 52c424eea0..920cb382b0 100644
--- a/chip/stm32/gpio-stm32l.c
+++ b/chip/stm32/gpio-stm32l.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,6 +8,7 @@
 #include "clock.h"
 #include "common.h"
 #include "gpio.h"
+#include "gpio_chip.h"
 #include "hooks.h"
 #include "registers.h"
 #include "task.h"
@@ -40,12 +41,17 @@ static void gpio_init(void)
 }
 DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
 
-DECLARE_IRQ(STM32_IRQ_EXTI0, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI1, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI2, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI3, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI4, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI9_5, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI15_10, gpio_interrupt, 1);
+static void _gpio_interrupt(void)
+{
+	gpio_interrupt();
+}
+
+DECLARE_IRQ(STM32_IRQ_EXTI0, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI1, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI2, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI3, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI4, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI9_5, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI15_10, _gpio_interrupt, 1);
 
 #include "gpio-f0-l.c"
diff --git a/chip/stm32/gpio-stm32l4.c b/chip/stm32/gpio-stm32l4.c
index b5c4940454..1ef83a188a 100644
--- a/chip/stm32/gpio-stm32l4.c
+++ b/chip/stm32/gpio-stm32l4.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,6 +8,7 @@
 #include "clock.h"
 #include "common.h"
 #include "gpio.h"
+#include "gpio_chip.h"
 #include "hooks.h"
 #include "registers.h"
 #include "task.h"
@@ -37,16 +38,20 @@ static void gpio_init(void)
 	task_enable_irq(STM32_IRQ_EXTI4);
 	task_enable_irq(STM32_IRQ_EXTI9_5);
 	task_enable_irq(STM32_IRQ_EXTI15_10);
-
 }
 DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
 
-DECLARE_IRQ(STM32_IRQ_EXTI0, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI1, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI2, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI3, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI4, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI9_5, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI15_10, gpio_interrupt, 1);
+static void _gpio_interrupt(void)
+{
+	gpio_interrupt();
+}
+
+DECLARE_IRQ(STM32_IRQ_EXTI0, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI1, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI2, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI3, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI4, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI9_5, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI15_10, _gpio_interrupt, 1);
 
 #include "gpio-f0-l.c"
diff --git a/chip/stm32/gpio-stm32l5.c b/chip/stm32/gpio-stm32l5.c
new file mode 100644
index 0000000000..e714164650
--- /dev/null
+++ b/chip/stm32/gpio-stm32l5.c
@@ -0,0 +1,73 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "clock.h"
+#include "common.h"
+#include "gpio.h"
+#include "gpio_chip.h"
+#include "hooks.h"
+#include "registers.h"
+#include "task.h"
+#include "util.h"
+
+void gpio_enable_clocks(void)
+{
+	/*
+	 * Enable all GPIOs clocks
+	 *
+	 * TODO(crosbug.com/p/23770): only enable the banks we need to,
+	 * and support disabling some of them in low-power idle.
+	 */
+	STM32_RCC_AHB2ENR |= STM32_RCC_AHB2ENR_GPIOMASK;
+
+	/* Delay 1 AHB clock cycle after the clock is enabled */
+	clock_wait_bus_cycles(BUS_AHB, 1);
+}
+
+static void gpio_init(void)
+{
+	/* Enable IRQs now that pins are set up */
+	task_enable_irq(STM32_IRQ_EXTI0);
+	task_enable_irq(STM32_IRQ_EXTI1);
+	task_enable_irq(STM32_IRQ_EXTI2);
+	task_enable_irq(STM32_IRQ_EXTI3);
+	task_enable_irq(STM32_IRQ_EXTI4);
+	task_enable_irq(STM32_IRQ_EXTI5);
+	task_enable_irq(STM32_IRQ_EXTI6);
+	task_enable_irq(STM32_IRQ_EXTI7);
+	task_enable_irq(STM32_IRQ_EXTI8);
+	task_enable_irq(STM32_IRQ_EXTI9);
+	task_enable_irq(STM32_IRQ_EXTI10);
+	task_enable_irq(STM32_IRQ_EXTI11);
+	task_enable_irq(STM32_IRQ_EXTI12);
+	task_enable_irq(STM32_IRQ_EXTI13);
+	task_enable_irq(STM32_IRQ_EXTI14);
+	task_enable_irq(STM32_IRQ_EXTI15);
+}
+DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
+
+static void _gpio_interrupt(void)
+{
+	gpio_interrupt();
+}
+
+DECLARE_IRQ(STM32_IRQ_EXTI0, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI1, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI2, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI3, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI4, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI5, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI6, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI7, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI8, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI9, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI10, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI11, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI12, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI13, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI14, _gpio_interrupt, 1);
+DECLARE_IRQ(STM32_IRQ_EXTI15, _gpio_interrupt, 1);
+
+#include "gpio-f0-l.c"
diff --git a/chip/stm32/gpio.c b/chip/stm32/gpio.c
index ccfd3399e2..ade662d9d8 100644
--- a/chip/stm32/gpio.c
+++ b/chip/stm32/gpio.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,7 @@
 #include "util.h"
 
 /* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
 /* For each EXTI bit, record which GPIO entry is using it */
 static uint8_t exti_events[16];
 
@@ -83,8 +83,8 @@ test_mockable int gpio_get_level(enum gpio_signal signal)
 
 void gpio_set_level(enum gpio_signal signal, int value)
 {
-	STM32_GPIO_BSRR(gpio_list[signal].port) =
-			gpio_list[signal].mask << (value ? 0 : 16);
+	STM32_GPIO_BSRR(gpio_list[signal].port) = gpio_list[signal].mask
+						  << (value ? 0 : 16);
 }
 
 int gpio_enable_interrupt(enum gpio_signal signal)
@@ -103,17 +103,26 @@ int gpio_enable_interrupt(enum gpio_signal signal)
 	g_old += exti_events[bit];
 
 	if ((exti_events[bit]) && (exti_events[bit] != signal)) {
-		CPRINTS("Overriding %s with %s on EXTI%d",
-			g_old->name, g->name, bit);
+		CPRINTS("Overriding %s with %s on EXTI%d", g_old->name, g->name,
+			bit);
 	}
 	exti_events[bit] = signal;
 
 	group = bit / 4;
-	shift = (bit % 4) * 4;
+	shift = bit % 4;
 	bank = (g->port - STM32_GPIOA_BASE) / 0x400;
 
-	STM32_SYSCFG_EXTICR(group) = (STM32_SYSCFG_EXTICR(group) &
-				      ~(0xF << shift)) | (bank << shift);
+#ifdef STM32_EXTI_EXTICR
+	/* STM32L5 has 8-bit fields as part of EXTI registers. */
+	STM32_EXTI_EXTICR(group) =
+		(STM32_EXTI_EXTICR(group) & ~(0xFF << (shift * 8))) |
+		(bank << (shift * 8));
+#else
+	/* Other STM chips have 4-bit fields as part of SYSCFG registers. */
+	STM32_SYSCFG_EXTICR(group) =
+		(STM32_SYSCFG_EXTICR(group) & ~(0xF << (shift * 4))) |
+		(bank << (shift * 4));
+#endif
 	STM32_EXTI_IMR |= g->mask;
 
 	return EC_SUCCESS;
@@ -141,11 +150,19 @@ int gpio_clear_pending_interrupt(enum gpio_signal signal)
 {
 	const struct gpio_info *g = gpio_list + signal;
 
-	if (!g->mask || signal >= GPIO_IH_COUNT)
+	if (!g->mask || signal >= GPIO_IH_COUNT) {
 		return EC_ERROR_INVAL;
+	}
 
 	/* Write 1 to clear interrupt */
+#ifdef STM32_EXTI_RPR
+	/* Separate rising and falling edge pending registers. */
+	STM32_EXTI_RPR = g->mask;
+	STM32_EXTI_FPR = g->mask;
+#else
+	/* One combined rising/falling edge pending registers. */
 	STM32_EXTI_PR = g->mask;
+#endif
 
 	return EC_SUCCESS;
 }
@@ -156,12 +173,21 @@ int gpio_clear_pending_interrupt(enum gpio_signal signal)
 void __keep gpio_interrupt(void)
 {
 	int bit;
+	uint8_t signal;
+#ifdef STM32_EXTI_RPR
+	/* process only GPIO EXTINTs (EXTINT0..15) not other EXTINTs */
+	uint32_t pending_r = STM32_EXTI_RPR & 0xFFFF;
+	uint32_t pending_f = STM32_EXTI_FPR & 0xFFFF;
+	uint32_t pending = pending_r | pending_f;
+	/* Write 1 to clear interrupt */
+	STM32_EXTI_RPR = pending_r;
+	STM32_EXTI_FPR = pending_f;
+#else
 	/* process only GPIO EXTINTs (EXTINT0..15) not other EXTINTs */
 	uint32_t pending = STM32_EXTI_PR & 0xFFFF;
-	uint8_t signal;
-
 	/* Write 1 to clear interrupt */
 	STM32_EXTI_PR = pending;
+#endif
 
 	while (pending) {
 		bit = get_next_bit(&pending);
@@ -171,7 +197,11 @@ void __keep gpio_interrupt(void)
 	}
 }
 #ifdef CHIP_FAMILY_STM32F0
-DECLARE_IRQ(STM32_IRQ_EXTI0_1, gpio_interrupt, STM32_IRQ_EXT0_1_PRIORITY);
-DECLARE_IRQ(STM32_IRQ_EXTI2_3, gpio_interrupt, STM32_IRQ_EXT2_3_PRIORITY);
-DECLARE_IRQ(STM32_IRQ_EXTI4_15, gpio_interrupt, STM32_IRQ_EXTI4_15_PRIORITY);
+static void _gpio_interrupt(void)
+{
+	gpio_interrupt();
+}
+DECLARE_IRQ(STM32_IRQ_EXTI0_1, _gpio_interrupt, STM32_IRQ_EXT0_1_PRIORITY);
+DECLARE_IRQ(STM32_IRQ_EXTI2_3, _gpio_interrupt, STM32_IRQ_EXT2_3_PRIORITY);
+DECLARE_IRQ(STM32_IRQ_EXTI4_15, _gpio_interrupt, STM32_IRQ_EXTI4_15_PRIORITY);
 #endif
diff --git a/chip/stm32/gpio_chip.h b/chip/stm32/gpio_chip.h
index a5b642fb05..0a52fe9191 100644
--- a/chip/stm32/gpio_chip.h
+++ b/chip/stm32/gpio_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,4 +19,5 @@ void gpio_enable_clocks(void);
  */
 int gpio_required_clocks(void);
 
-#endif  /* __CROS_EC_CHIP_STM32_GPIO_CHIP_H */
+void __keep gpio_interrupt(void);
+#endif /* __CROS_EC_CHIP_STM32_GPIO_CHIP_H */
diff --git a/chip/stm32/host_command_common.c b/chip/stm32/host_command_common.c
index f1d5a0f103..10653a0711 100644
--- a/chip/stm32/host_command_common.c
+++ b/chip/stm32/host_command_common.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,7 +9,7 @@
 #include "spi.h"
 #include "usart_host_command.h"
 
-#ifndef CONFIG_I2C_SLAVE
+#ifndef CONFIG_I2C_PERIPHERAL
 
 /* Store current transport type */
 static enum fp_transport_type curr_transport_type = FP_TRANSPORT_TYPE_UNKNOWN;
@@ -17,40 +17,29 @@ static enum fp_transport_type curr_transport_type = FP_TRANSPORT_TYPE_UNKNOWN;
 /*
  * Get protocol information
  */
-static enum ec_status host_command_protocol_info(struct host_cmd_handler_args
-						 *args)
+static enum ec_status
+host_command_protocol_info(struct host_cmd_handler_args *args)
 {
 	enum ec_status ret_status = EC_RES_INVALID_COMMAND;
 
 	/*
-	 * If FP sensor task is enabled, read transport type from TRANSPORT_SEL
-	 * bootstrap pin for the first time this function is called.
+	 * Read transport type from TRANSPORT_SEL bootstrap pin the first
+	 * time this function is called.
 	 */
-	if ((IS_ENABLED(HAS_TASK_FPSENSOR)) &&
-	    (curr_transport_type == FP_TRANSPORT_TYPE_UNKNOWN)) {
+	if (IS_ENABLED(CONFIG_FINGERPRINT_MCU) &&
+	    (curr_transport_type == FP_TRANSPORT_TYPE_UNKNOWN))
 		curr_transport_type = get_fp_transport_type();
-	}
 
-	/*
-	 * Transport select is only enabled on boards with fp sensor tasks.
-	 * If fp sensor task is enabled, transport is USART and
-	 * host command layer is present, call usart_get_protocol.
-	 * If fp sensor task is enabled and transport is SPI or else if only
-	 * spi layer is enabled on non fp boards, call spi_get_protocol_info.
-	 */
-	if (IS_ENABLED(HAS_TASK_FPSENSOR) &&
-	    IS_ENABLED(CONFIG_USART_HOST_COMMAND) &&
+	if (IS_ENABLED(CONFIG_USART_HOST_COMMAND) &&
 	    curr_transport_type == FP_TRANSPORT_TYPE_UART)
 		ret_status = usart_get_protocol_info(args);
-	else if (IS_ENABLED(CONFIG_SPI) ||
-		(IS_ENABLED(HAS_TASK_FPSENSOR) &&
-		 curr_transport_type == FP_TRANSPORT_TYPE_SPI))
-			ret_status = spi_get_protocol_info(args);
+	else if (IS_ENABLED(CONFIG_SPI) &&
+		 curr_transport_type == FP_TRANSPORT_TYPE_SPI)
+		ret_status = spi_get_protocol_info(args);
 
 	return ret_status;
 }
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO,
-		     host_command_protocol_info,
+DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, host_command_protocol_info,
 		     EC_VER_MASK(0));
 
-#endif /* CONFIG_I2C_SLAVE */
+#endif /* CONFIG_I2C_PERIPHERAL */
diff --git a/chip/stm32/hwtimer.c b/chip/stm32/hwtimer.c
deleted file mode 100644
index 953110017f..0000000000
--- a/chip/stm32/hwtimer.c
+++ /dev/null
@@ -1,454 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Hardware timers driver */
-
-#include "clock.h"
-#include "clock-f.h"
-#include "common.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "panic.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "watchdog.h"
-
-/*
- * Trigger select mapping for slave timer from master timer.  This is
- * unfortunately not very straightforward; there's no tidy way to do this
- * algorithmically.  To avoid burning memory for a lookup table, use macros to
- * compute the offset.  This also has the benefit that compilation will fail if
- * an unsupported master/slave pairing is used.
- */
-#ifdef CHIP_FAMILY_STM32F0
-/*
- * Slave        Master
- *     1    15  2  3 17
- *     2     1 15  3 14
- *     3     1  2 15 14
- *    15     2  3 16 17
- *     --------------------
- *     ts =  0  1  2  3
- */
-#define STM32_TIM_TS_SLAVE_1_MASTER_15  0
-#define STM32_TIM_TS_SLAVE_1_MASTER_2   1
-#define STM32_TIM_TS_SLAVE_1_MASTER_3   2
-#define STM32_TIM_TS_SLAVE_1_MASTER_17  3
-#define STM32_TIM_TS_SLAVE_2_MASTER_1   0
-#define STM32_TIM_TS_SLAVE_2_MASTER_15  1
-#define STM32_TIM_TS_SLAVE_2_MASTER_3   2
-#define STM32_TIM_TS_SLAVE_2_MASTER_14  3
-#define STM32_TIM_TS_SLAVE_3_MASTER_1   0
-#define STM32_TIM_TS_SLAVE_3_MASTER_2   1
-#define STM32_TIM_TS_SLAVE_3_MASTER_15  2
-#define STM32_TIM_TS_SLAVE_3_MASTER_14  3
-#define STM32_TIM_TS_SLAVE_15_MASTER_2  0
-#define STM32_TIM_TS_SLAVE_15_MASTER_3  1
-#define STM32_TIM_TS_SLAVE_15_MASTER_16 2
-#define STM32_TIM_TS_SLAVE_15_MASTER_17 3
-#elif defined(CHIP_FAMILY_STM32F3)
-/*
- * Slave        Master
- *     2    19 15  3 14
- *     3    19  2  5 14
- *     4    19  2  3 15
- *     5     2  3  4 15
- *    12     4  5 13 14
- *    19     2  3 15 16
- *    ---------------------
- *     ts =  0  1  2  3
- */
-#define STM32_TIM_TS_SLAVE_2_MASTER_19  0
-#define STM32_TIM_TS_SLAVE_2_MASTER_15  1
-#define STM32_TIM_TS_SLAVE_2_MASTER_3   2
-#define STM32_TIM_TS_SLAVE_2_MASTER_14  3
-#define STM32_TIM_TS_SLAVE_3_MASTER_19  0
-#define STM32_TIM_TS_SLAVE_3_MASTER_2   1
-#define STM32_TIM_TS_SLAVE_3_MASTER_5   2
-#define STM32_TIM_TS_SLAVE_3_MASTER_14  3
-#define STM32_TIM_TS_SLAVE_4_MASTER_19  0
-#define STM32_TIM_TS_SLAVE_4_MASTER_2   1
-#define STM32_TIM_TS_SLAVE_4_MASTER_3   2
-#define STM32_TIM_TS_SLAVE_4_MASTER_15  3
-#define STM32_TIM_TS_SLAVE_5_MASTER_2   0
-#define STM32_TIM_TS_SLAVE_5_MASTER_3   1
-#define STM32_TIM_TS_SLAVE_5_MASTER_4   2
-#define STM32_TIM_TS_SLAVE_5_MASTER_15  3
-#define STM32_TIM_TS_SLAVE_12_MASTER_4  0
-#define STM32_TIM_TS_SLAVE_12_MASTER_5  1
-#define STM32_TIM_TS_SLAVE_12_MASTER_13 2
-#define STM32_TIM_TS_SLAVE_12_MASTER_14 3
-#define STM32_TIM_TS_SLAVE_19_MASTER_2  0
-#define STM32_TIM_TS_SLAVE_19_MASTER_3  1
-#define STM32_TIM_TS_SLAVE_19_MASTER_15 2
-#define STM32_TIM_TS_SLAVE_19_MASTER_16 3
-#else /* !CHIP_FAMILY_STM32F0 && !CHIP_FAMILY_STM32F3 */
-/*
- * Slave        Master
- *     1    15  2  3  4  (STM32F100 only)
- *     2     9 10  3  4
- *     3     9  2 11  4
- *     4    10  2  3  9
- *     9     2  3 10 11  (STM32L15x only)
- *     --------------------
- *     ts =  0  1  2  3
- */
-#define STM32_TIM_TS_SLAVE_1_MASTER_15 0
-#define STM32_TIM_TS_SLAVE_1_MASTER_2  1
-#define STM32_TIM_TS_SLAVE_1_MASTER_3  2
-#define STM32_TIM_TS_SLAVE_1_MASTER_4  3
-#define STM32_TIM_TS_SLAVE_2_MASTER_9  0
-#define STM32_TIM_TS_SLAVE_2_MASTER_10 1
-#define STM32_TIM_TS_SLAVE_2_MASTER_3  2
-#define STM32_TIM_TS_SLAVE_2_MASTER_4  3
-#define STM32_TIM_TS_SLAVE_3_MASTER_9  0
-#define STM32_TIM_TS_SLAVE_3_MASTER_2  1
-#define STM32_TIM_TS_SLAVE_3_MASTER_11 2
-#define STM32_TIM_TS_SLAVE_3_MASTER_4  3
-#define STM32_TIM_TS_SLAVE_4_MASTER_10 0
-#define STM32_TIM_TS_SLAVE_4_MASTER_2  1
-#define STM32_TIM_TS_SLAVE_4_MASTER_3  2
-#define STM32_TIM_TS_SLAVE_4_MASTER_9  3
-#define STM32_TIM_TS_SLAVE_9_MASTER_2  0
-#define STM32_TIM_TS_SLAVE_9_MASTER_3  1
-#define STM32_TIM_TS_SLAVE_9_MASTER_10 2
-#define STM32_TIM_TS_SLAVE_9_MASTER_11 3
-#endif /* !CHIP_FAMILY_STM32F0 */
-#define TSMAP(slave, master) \
-	CONCAT4(STM32_TIM_TS_SLAVE_, slave, _MASTER_, master)
-
-/*
- * Timers are defined per board.  This gives us flexibility to work around
- * timers which are dedicated to board-specific PWM sources.
- */
-#define IRQ_TIM(n) CONCAT2(STM32_IRQ_TIM, n)
-#define IRQ_MSB IRQ_TIM(TIM_CLOCK_MSB)
-#define IRQ_LSB IRQ_TIM(TIM_CLOCK_LSB)
-#define IRQ_WD  IRQ_TIM(TIM_WATCHDOG)
-
-/* TIM1 has fancy names for its IRQs; remap count-up IRQ for the macro above */
-#if defined TIM_WATCHDOG && (TIM_WATCHDOG == 1)
-#define STM32_IRQ_TIM1 STM32_IRQ_TIM1_BRK_UP_TRG
-#else /* !(TIM_WATCHDOG == 1) */
-#define STM32_IRQ_TIM1 STM32_IRQ_TIM1_CC
-#endif /* !(TIM_WATCHDOG == 1) */
-
-#define TIM_BASE(n) CONCAT3(STM32_TIM, n, _BASE)
-#define TIM_WD_BASE TIM_BASE(TIM_WATCHDOG)
-
-static uint32_t last_deadline;
-
-void __hw_clock_event_set(uint32_t deadline)
-{
-	last_deadline = deadline;
-
-	if ((deadline >> 16) > STM32_TIM_CNT(TIM_CLOCK_MSB)) {
-		/* first set a match on the MSB */
-		STM32_TIM_CCR1(TIM_CLOCK_MSB) = deadline >> 16;
-		/* disable LSB match */
-		STM32_TIM_DIER(TIM_CLOCK_LSB) &= ~2;
-		/* Clear the match flags */
-		STM32_TIM_SR(TIM_CLOCK_MSB) = ~2;
-		STM32_TIM_SR(TIM_CLOCK_LSB) = ~2;
-		/* Set the match interrupt */
-		STM32_TIM_DIER(TIM_CLOCK_MSB) |= 2;
-	}
-	/*
-	 * In the unlikely case where the MSB has increased and matched
-	 * the deadline MSB before we set the match interrupt, as the STM
-	 * hardware timer won't trigger an interrupt, we fall back to the
-	 * following LSB event code to set another interrupt.
-	 */
-	if ((deadline >> 16) == STM32_TIM_CNT(TIM_CLOCK_MSB)) {
-		/* we can set a match on the LSB only */
-		STM32_TIM_CCR1(TIM_CLOCK_LSB) = deadline & 0xffff;
-		/* disable MSB match */
-		STM32_TIM_DIER(TIM_CLOCK_MSB) &= ~2;
-		/* Clear the match flags */
-		STM32_TIM_SR(TIM_CLOCK_MSB) = ~2;
-		STM32_TIM_SR(TIM_CLOCK_LSB) = ~2;
-		/* Set the match interrupt */
-		STM32_TIM_DIER(TIM_CLOCK_LSB) |= 2;
-	}
-	/*
-	 * If the LSB deadline is already in the past and won't trigger an
-	 * interrupt, the common code in process_timers will deal with the
-	 * expired timer and automatically set the next deadline, we don't need
-	 * to do anything here.
-	 */
-}
-
-uint32_t __hw_clock_event_get(void)
-{
-	return last_deadline;
-}
-
-void __hw_clock_event_clear(void)
-{
-	/* Disable the match interrupts */
-	STM32_TIM_DIER(TIM_CLOCK_LSB) &= ~2;
-	STM32_TIM_DIER(TIM_CLOCK_MSB) &= ~2;
-}
-
-uint32_t __hw_clock_source_read(void)
-{
-	uint32_t hi;
-	uint32_t lo;
-
-	/* Ensure the two half-words are coherent */
-	do {
-		hi = STM32_TIM_CNT(TIM_CLOCK_MSB);
-		lo = STM32_TIM_CNT(TIM_CLOCK_LSB);
-	} while (hi != STM32_TIM_CNT(TIM_CLOCK_MSB));
-
-	return (hi << 16) | lo;
-}
-
-void __hw_clock_source_set(uint32_t ts)
-{
-	STM32_TIM_CNT(TIM_CLOCK_MSB) = ts >> 16;
-	STM32_TIM_CNT(TIM_CLOCK_LSB) = ts & 0xffff;
-}
-
-void __hw_clock_source_irq(void)
-{
-	uint32_t stat_tim_msb = STM32_TIM_SR(TIM_CLOCK_MSB);
-
-	/* Clear status */
-	STM32_TIM_SR(TIM_CLOCK_LSB) = 0;
-	STM32_TIM_SR(TIM_CLOCK_MSB) = 0;
-
-	/*
-	 * Find expired timers and set the new timer deadline
-	 * signal overflow if the 16-bit MSB counter has overflowed.
-	 */
-	process_timers(stat_tim_msb & 0x01);
-}
-DECLARE_IRQ(IRQ_MSB, __hw_clock_source_irq, 1);
-DECLARE_IRQ(IRQ_LSB, __hw_clock_source_irq, 1);
-
-void __hw_timer_enable_clock(int n, int enable)
-{
-	volatile uint32_t *reg;
-	uint32_t mask = 0;
-
-	/*
-	 * Mapping of timers to reg/mask is split into a few different ranges,
-	 * some specific to individual chips.
-	 */
-#if defined(CHIP_FAMILY_STM32F0)
-	if (n == 1) {
-		reg = &STM32_RCC_APB2ENR;
-		mask = STM32_RCC_PB2_TIM1;
-	}
-#elif defined(CHIP_FAMILY_STM32L) || defined(CHIP_FAMILY_STM32F4)
-	if (n >= 9 && n <= 11) {
-		reg = &STM32_RCC_APB2ENR;
-		mask = STM32_RCC_PB2_TIM9 << (n - 9);
-	}
-#endif
-
-#if defined(CHIP_FAMILY_STM32F0)
-	if (n >= 15 && n <= 17) {
-		reg = &STM32_RCC_APB2ENR;
-		mask = STM32_RCC_PB2_TIM15 << (n - 15);
-	}
-#endif
-
-#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3)
-	if (n == 14) {
-		reg = &STM32_RCC_APB1ENR;
-		mask = STM32_RCC_PB1_TIM14;
-	}
-#endif
-
-#if defined(CHIP_FAMILY_STM32F3)
-	if (n == 12 || n == 13) {
-		reg = &STM32_RCC_APB1ENR;
-		mask = STM32_RCC_PB1_TIM12 << (n - 12);
-	}
-	if (n == 18) {
-		reg = &STM32_RCC_APB1ENR;
-		mask = STM32_RCC_PB1_TIM18;
-	}
-	if (n == 19) {
-		reg = &STM32_RCC_APB2ENR;
-		mask = STM32_RCC_PB2_TIM19;
-	}
-#endif
-
-	if (n >= 2 && n <= 7) {
-		reg = &STM32_RCC_APB1ENR;
-		mask = STM32_RCC_PB1_TIM2 << (n - 2);
-	}
-
-	if (!mask)
-		return;
-
-	if (enable)
-		*reg |= mask;
-	else
-		*reg &= ~mask;
-}
-
-static void update_prescaler(void)
-{
-	/*
-	 * Pre-scaler value :
-	 * TIM_CLOCK_LSB is counting microseconds;
-	 * TIM_CLOCK_MSB is counting every TIM_CLOCK_LSB overflow.
-	 *
-	 * This will take effect at the next update event (when the current
-	 * prescaler counter ticks down, or if forced via EGR).
-	 */
-	STM32_TIM_PSC(TIM_CLOCK_MSB) = 0;
-	STM32_TIM_PSC(TIM_CLOCK_LSB) = (clock_get_timer_freq() / SECOND) - 1;
-}
-DECLARE_HOOK(HOOK_FREQ_CHANGE, update_prescaler, HOOK_PRIO_DEFAULT);
-
-int __hw_clock_source_init(uint32_t start_t)
-{
-	/*
-	 * we use 2 chained 16-bit counters to emulate a 32-bit one :
-	 * TIM_CLOCK_MSB is the MSB (Slave)
-	 * TIM_CLOCK_LSB is the LSB (Master)
-	 */
-
-	/* Enable TIM_CLOCK_MSB and TIM_CLOCK_LSB clocks */
-	__hw_timer_enable_clock(TIM_CLOCK_MSB, 1);
-	__hw_timer_enable_clock(TIM_CLOCK_LSB, 1);
-
-	/* Delay 1 APB clock cycle after the clock is enabled */
-	clock_wait_bus_cycles(BUS_APB, 1);
-
-	/*
-	 * Timer configuration : Upcounter, counter disabled, update event only
-	 * on overflow.
-	 */
-	STM32_TIM_CR1(TIM_CLOCK_MSB) = 0x0004;
-	STM32_TIM_CR1(TIM_CLOCK_LSB) = 0x0004;
-	/*
-	 * TIM_CLOCK_LSB (master mode) generates a periodic trigger signal on
-	 * each UEV
-	 */
-	STM32_TIM_CR2(TIM_CLOCK_MSB) = 0x0000;
-	STM32_TIM_CR2(TIM_CLOCK_LSB) = 0x0020;
-
-	STM32_TIM_SMCR(TIM_CLOCK_MSB) = 0x0007 |
-		(TSMAP(TIM_CLOCK_MSB, TIM_CLOCK_LSB) << 4);
-	STM32_TIM_SMCR(TIM_CLOCK_LSB) = 0x0000;
-
-	/* Auto-reload value : 16-bit free-running counters */
-	STM32_TIM_ARR(TIM_CLOCK_MSB) = 0xffff;
-	STM32_TIM_ARR(TIM_CLOCK_LSB) = 0xffff;
-
-	/* Update prescaler */
-	update_prescaler();
-
-	/* Reload the pre-scaler */
-	STM32_TIM_EGR(TIM_CLOCK_MSB) = 0x0001;
-	STM32_TIM_EGR(TIM_CLOCK_LSB) = 0x0001;
-
-	/* Set up the overflow interrupt on TIM_CLOCK_MSB */
-	STM32_TIM_DIER(TIM_CLOCK_MSB) = 0x0001;
-	STM32_TIM_DIER(TIM_CLOCK_LSB) = 0x0000;
-
-	/* Start counting */
-	STM32_TIM_CR1(TIM_CLOCK_MSB) |= 1;
-	STM32_TIM_CR1(TIM_CLOCK_LSB) |= 1;
-
-	/* Override the count with the start value now that counting has
-	 * started. */
-	__hw_clock_source_set(start_t);
-
-	/* Enable timer interrupts */
-	task_enable_irq(IRQ_MSB);
-	task_enable_irq(IRQ_LSB);
-
-	return IRQ_LSB;
-}
-
-#ifdef CONFIG_WATCHDOG_HELP
-
-void __keep watchdog_check(uint32_t excep_lr, uint32_t excep_sp)
-{
-	struct timer_ctlr *timer = (struct timer_ctlr *)TIM_WD_BASE;
-
-	/* clear status */
-	timer->sr = 0;
-
-	watchdog_trace(excep_lr, excep_sp);
-}
-
-void IRQ_HANDLER(IRQ_WD)(void) __attribute__((naked));
-void IRQ_HANDLER(IRQ_WD)(void)
-{
-	/* Naked call so we can extract raw LR and SP */
-	asm volatile("mov r0, lr\n"
-		     "mov r1, sp\n"
-		     /* Must push registers in pairs to keep 64-bit aligned
-		      * stack for ARM EABI. */
-		     "push {r0, lr}\n"
-		     "bl watchdog_check\n"
-		     "pop {r0,pc}\n");
-}
-const struct irq_priority __keep IRQ_PRIORITY(IRQ_WD)
-	__attribute__((section(".rodata.irqprio")))
-		= {IRQ_WD, 0}; /* put the watchdog at the highest
-					    priority */
-
-void hwtimer_setup_watchdog(void)
-{
-	struct timer_ctlr *timer = (struct timer_ctlr *)TIM_WD_BASE;
-
-	/* Enable clock */
-	__hw_timer_enable_clock(TIM_WATCHDOG, 1);
-
-	/* Delay 1 APB clock cycle after the clock is enabled */
-	clock_wait_bus_cycles(BUS_APB, 1);
-
-	/*
-	 * Timer configuration : Down counter, counter disabled, update
-	 * event only on overflow.
-	 */
-	timer->cr1 = 0x0014 | BIT(7);
-
-	/* TIM (slave mode) uses TIM_CLOCK_LSB as internal trigger */
-	timer->smcr = 0x0007 | (TSMAP(TIM_WATCHDOG, TIM_CLOCK_LSB) << 4);
-
-	/*
-	 * The auto-reload value is based on the period between rollovers for
-	 * TIM_CLOCK_LSB. Since TIM_CLOCK_LSB runs at 1MHz, it will overflow
-	 * in 65.536ms. We divide our required watchdog period by this amount
-	 * to obtain the number of times TIM_CLOCK_LSB can overflow before we
-	 * generate an interrupt.
-	 */
-	timer->arr = timer->cnt = CONFIG_AUX_TIMER_PERIOD_MS * MSEC / BIT(16);
-
-	/* count on every TIM_CLOCK_LSB overflow */
-	timer->psc = 0;
-
-	/* Reload the pre-scaler from arr when it goes below zero */
-	timer->egr = 0x0000;
-
-	/* setup the overflow interrupt */
-	timer->dier = 0x0001;
-
-	/* Start counting */
-	timer->cr1 |= 1;
-
-	/* Enable timer interrupts */
-	task_enable_irq(IRQ_WD);
-}
-
-void hwtimer_reset_watchdog(void)
-{
-	struct timer_ctlr *timer = (struct timer_ctlr *)TIM_WD_BASE;
-
-	timer->cnt = timer->arr;
-}
-
-#endif  /* defined(CONFIG_WATCHDOG_HELP) */
diff --git a/chip/stm32/hwtimer32.c b/chip/stm32/hwtimer32.c
index 12057ad762..ebe46d8316 100644
--- a/chip/stm32/hwtimer32.c
+++ b/chip/stm32/hwtimer32.c
@@ -1,12 +1,13 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Hardware 32-bit timer driver */
 
-#include "clock.h"
+#include "builtin/assert.h"
 #include "clock-f.h"
+#include "clock.h"
 #include "common.h"
 #include "hooks.h"
 #include "hwtimer.h"
@@ -16,8 +17,6 @@
 #include "timer.h"
 #include "watchdog.h"
 
-#define IRQ_TIM(n) CONCAT2(STM32_IRQ_TIM, n)
-
 void __hw_clock_event_set(uint32_t deadline)
 {
 	/* set the match on the deadline */
@@ -46,10 +45,34 @@ uint32_t __hw_clock_source_read(void)
 
 void __hw_clock_source_set(uint32_t ts)
 {
+	ASSERT(!is_interrupt_enabled());
+
+	/*
+	 * Stop counter to avoid race between setting counter value
+	 * and clearing status.
+	 */
+	STM32_TIM_CR1(TIM_CLOCK32) &= ~1;
+
+	/* Set counter value */
 	STM32_TIM32_CNT(TIM_CLOCK32) = ts;
+
+	/*
+	 * Clear status. We may clear information other than timer overflow
+	 * (eg. event timestamp was matched) but:
+	 * - Bits other than overflow are unused (see __hw_clock_source_irq())
+	 * - After setting timestamp software will trigger timer interrupt using
+	 *   task_trigger_irq() (see force_time() in common/timer.c).
+	 *   process_timers() is called from timer interrupt, so if "match" bit
+	 *   was present in status (think: some task timers are expired)
+	 *   process_timers() will handle that correctly.
+	 */
+	STM32_TIM_SR(TIM_CLOCK32) = 0;
+
+	/* Start counting */
+	STM32_TIM_CR1(TIM_CLOCK32) |= 1;
 }
 
-void __hw_clock_source_irq(void)
+static void __hw_clock_source_irq(void)
 {
 	uint32_t stat_tim = STM32_TIM_SR(TIM_CLOCK32);
 
@@ -93,7 +116,7 @@ void __hw_timer_enable_clock(int n, int enable)
 #endif
 
 #if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \
-defined(CHIP_FAMILY_STM32H7)
+	defined(CHIP_FAMILY_STM32H7)
 	if (n == 14) {
 		reg = &STM32_RCC_APB1ENR;
 		mask = STM32_RCC_PB1_TIM14;
@@ -127,10 +150,22 @@ defined(CHIP_FAMILY_STM32H7)
 	else if (n >= 15 && n <= 17)
 		mask = STM32_RCC_APB2ENR_TIM15 << (n - 15);
 #endif
+#if defined(CHIP_FAMILY_STM32L4)
+	if (n >= 2 && n <= 7) {
+		reg = &STM32_RCC_APB1ENR1;
+		mask = STM32_RCC_PB1_TIM2 << (n - 2);
+	} else if (n == 1 || n == 15 || n == 16) {
+		reg = &STM32_RCC_APB2ENR;
+		mask = (n == 1)	 ? STM32_RCC_APB2ENR_TIM1EN :
+		       (n == 15) ? STM32_RCC_APB2ENR_TIM15EN :
+				   STM32_RCC_APB2ENR_TIM16EN;
+	}
+#else
 	if (n >= 2 && n <= 7) {
 		reg = &STM32_RCC_APB1ENR;
 		mask = STM32_RCC_PB1_TIM2 << (n - 2);
 	}
+#endif
 
 	if (!mask)
 		return;
@@ -142,7 +177,7 @@ defined(CHIP_FAMILY_STM32H7)
 }
 
 #if defined(CHIP_FAMILY_STM32L) || defined(CHIP_FAMILY_STM32L4) || \
-	defined(CHIP_FAMILY_STM32H7)
+	defined(CHIP_FAMILY_STM32F4) || defined(CHIP_FAMILY_STM32H7)
 /* for families using a variable clock feeding the timer */
 static void update_prescaler(void)
 {
@@ -179,11 +214,12 @@ static void update_prescaler(void)
 #ifdef CONFIG_WATCHDOG_HELP
 	/* Watchdog timer runs at 1KHz */
 	STM32_TIM_PSC(TIM_WATCHDOG) =
-		(clock_get_timer_freq()  / SECOND * MSEC)- 1;
-#endif  /* CONFIG_WATCHDOG_HELP */
+		(clock_get_timer_freq() / SECOND * MSEC) - 1;
+#endif /* CONFIG_WATCHDOG_HELP */
 }
 DECLARE_HOOK(HOOK_FREQ_CHANGE, update_prescaler, HOOK_PRIO_DEFAULT);
-#endif /* CHIP_FAMILY_STM32L || CHIP_FAMILY_STM32L4 || CHIP_FAMILY_STM32H7 */
+#endif /* CHIP_FAMILY_STM32L  || CHIP_FAMILY_STM32L4 || */
+/*  CHIP_FAMILY_STM32F4 || CHIP_FAMILY_STM32H7 */
 
 int __hw_clock_source_init(uint32_t start_t)
 {
@@ -213,13 +249,12 @@ int __hw_clock_source_init(uint32_t start_t)
 	/* Set up the overflow interrupt */
 	STM32_TIM_DIER(TIM_CLOCK32) = 0x0001;
 
+	/* Override the count with the start value */
+	STM32_TIM32_CNT(TIM_CLOCK32) = start_t;
+
 	/* Start counting */
 	STM32_TIM_CR1(TIM_CLOCK32) |= 1;
 
-	/* Override the count with the start value now that counting has
-	 * started. */
-	__hw_clock_source_set(start_t);
-
 	/* Enable timer interrupts */
 	task_enable_irq(IRQ_TIM(TIM_CLOCK32));
 
@@ -251,12 +286,17 @@ void IRQ_HANDLER(IRQ_WD)(void)
 		     "pop {r0,pc}\n");
 }
 const struct irq_priority __keep IRQ_PRIORITY(IRQ_WD)
-	__attribute__((section(".rodata.irqprio")))
-		= {IRQ_WD, 0}; /* put the watchdog at the highest
-					    priority */
+	__attribute__((section(".rodata.irqprio"))) = {
+		IRQ_WD, 0
+	}; /* put the watchdog
+	      at the highest
+			priority
+	    */
 
 void hwtimer_setup_watchdog(void)
 {
+	int freq;
+
 	/* Enable clock */
 	__hw_timer_enable_clock(TIM_WATCHDOG, 1);
 	/* Delay 1 APB clock cycle after the clock is enabled */
@@ -271,13 +311,30 @@ void hwtimer_setup_watchdog(void)
 	STM32_TIM_CR2(TIM_WATCHDOG) = 0x0000;
 	STM32_TIM_SMCR(TIM_WATCHDOG) = 0x0000;
 
-	/* AUto-reload value */
-	STM32_TIM_ARR(TIM_WATCHDOG) = CONFIG_AUX_TIMER_PERIOD_MS;
+	/*
+	 * all timers has 16-bit prescale.
+	 * For clock freq > 64MHz, 16bit prescale cannot meet 1KHz.
+	 * set prescale as 10KHz and 10 times arr value instead.
+	 * For clock freq < 64MHz, timer runs at 1KHz.
+	 */
+	freq = clock_get_timer_freq();
 
-	/* Update prescaler: watchdog timer runs at 1KHz */
-	STM32_TIM_PSC(TIM_WATCHDOG) =
-		(clock_get_timer_freq() / SECOND * MSEC) - 1;
+	if (freq <= 64000000 || !IS_ENABLED(CHIP_FAMILY_STM32L4)) {
+		/* AUto-reload value */
+		STM32_TIM_ARR(TIM_WATCHDOG) = CONFIG_AUX_TIMER_PERIOD_MS;
 
+		/* Update prescaler: watchdog timer runs at 1KHz */
+		STM32_TIM_PSC(TIM_WATCHDOG) = (freq / SECOND * MSEC) - 1;
+	}
+#ifdef CHIP_FAMILY_STM32L4
+	else {
+		/* 10 times ARR value with 10KHz timer */
+		STM32_TIM_ARR(TIM_WATCHDOG) = CONFIG_AUX_TIMER_PERIOD_MS * 10;
+
+		/* Update prescaler: watchdog timer runs at 10KHz */
+		STM32_TIM_PSC(TIM_WATCHDOG) = (freq / SECOND / 10 * MSEC) - 1;
+	}
+#endif
 	/* Reload the pre-scaler */
 	STM32_TIM_EGR(TIM_WATCHDOG) = 0x0001;
 
@@ -297,4 +354,4 @@ void hwtimer_reset_watchdog(void)
 	STM32_TIM_CNT(TIM_WATCHDOG) = 0x0000;
 }
 
-#endif  /* CONFIG_WATCHDOG_HELP */
+#endif /* CONFIG_WATCHDOG_HELP */
diff --git a/chip/stm32/i2c-stm32f0.c b/chip/stm32/i2c-stm32f0.c
index f722de2b54..acd4d3aca6 100644
--- a/chip/stm32/i2c-stm32f0.c
+++ b/chip/stm32/i2c-stm32f0.c
@@ -1,8 +1,9 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "builtin/assert.h"
 #include "chipset.h"
 #include "clock.h"
 #include "common.h"
@@ -23,37 +24,36 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
 
 /* Transmit timeout in microseconds */
-#define I2C_TX_TIMEOUT_MASTER	(10 * MSEC)
+#define I2C_TX_TIMEOUT_CONTROLLER (10 * MSEC)
 
-#ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS
+#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
 #if (I2C_PORT_EC == STM32_I2C1_PORT)
-#define IRQ_SLAVE STM32_IRQ_I2C1
+#define IRQ_PERIPHERAL STM32_IRQ_I2C1
 #else
-#define IRQ_SLAVE STM32_IRQ_I2C2
+#define IRQ_PERIPHERAL STM32_IRQ_I2C2
 #endif
 #endif
 
-
 /* I2C port state data */
 struct i2c_port_data {
-	uint32_t timeout_us;    /* Transaction timeout, or 0 to use default */
-	enum i2c_freq freq;	/* Port clock speed */
+	uint32_t timeout_us; /* Transaction timeout, or 0 to use default */
+	enum i2c_freq freq; /* Port clock speed */
 };
 static struct i2c_port_data pdata[I2C_PORT_COUNT];
 
 void i2c_set_timeout(int port, uint32_t timeout)
 {
-	pdata[port].timeout_us = timeout ? timeout : I2C_TX_TIMEOUT_MASTER;
+	pdata[port].timeout_us = timeout ? timeout : I2C_TX_TIMEOUT_CONTROLLER;
 }
 
 /* timingr register values for supported input clks / i2c clk rates */
 static const uint32_t busyloop_us[I2C_FREQ_COUNT] = {
 	[I2C_FREQ_1000KHZ] = 16, /* Enough for 2 bytes */
-	[I2C_FREQ_400KHZ] = 40,  /* Enough for 2 bytes */
-	[I2C_FREQ_100KHZ] = 0,   /* No busy looping at 100kHz (bus is slow) */
+	[I2C_FREQ_400KHZ] = 40, /* Enough for 2 bytes */
+	[I2C_FREQ_100KHZ] = 0, /* No busy looping at 100kHz (bus is slow) */
 };
 
 /**
@@ -72,7 +72,7 @@ static int wait_isr(int port, int mask)
 
 		/* Check for errors */
 		if (isr & (STM32_I2C_ISR_ARLO | STM32_I2C_ISR_BERR |
-			STM32_I2C_ISR_NACK))
+			   STM32_I2C_ISR_NACK))
 			return EC_ERROR_UNKNOWN;
 
 		/* Check for desired mask */
@@ -117,9 +117,8 @@ int chip_i2c_set_freq(int port, enum i2c_freq freq)
 {
 	enum stm32_i2c_clk_src src = I2C_CLK_SRC_48MHZ;
 
-#if defined(CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS) && \
-	defined(CONFIG_LOW_POWER_IDLE) && \
-	(I2C_PORT_EC == STM32_I2C1_PORT)
+#if defined(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) && \
+	defined(CONFIG_LOW_POWER_IDLE) && (I2C_PORT_EC == STM32_I2C1_PORT)
 	if (port == STM32_I2C1_PORT) {
 		/*
 		 * Use HSI (8MHz) for i2c clock. This allows smooth wakeup
@@ -164,9 +163,8 @@ static int i2c_init_port(const struct i2c_port_t *p)
 		STM32_RCC_APB1ENR |= 1 << (21 + port);
 
 	if (port == STM32_I2C1_PORT) {
-#if defined(CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS) && \
-	defined(CONFIG_LOW_POWER_IDLE) && \
-	(I2C_PORT_EC == STM32_I2C1_PORT)
+#if defined(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) && \
+	defined(CONFIG_LOW_POWER_IDLE) && (I2C_PORT_EC == STM32_I2C1_PORT)
 		/*
 		 * Use HSI (8MHz) for i2c clock. This allows smooth wakeup
 		 * from STOP mode since HSI is only clock running immediately
@@ -209,8 +207,8 @@ static int i2c_init_port(const struct i2c_port_t *p)
 }
 
 /*****************************************************************************/
-#ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS
-/* Host command slave */
+#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
+/* Host command peripheral */
 /*
  * Buffer for received host command packets (including prefix byte on request,
  * and result/size on response).  After any protocol-specific headers, the
@@ -218,7 +216,7 @@ static int i2c_init_port(const struct i2c_port_t *p)
  */
 static uint8_t host_buffer_padded[I2C_MAX_HOST_PACKET_SIZE + 4 +
 				  CONFIG_I2C_EXTRA_PACKET_SIZE] __aligned(4);
-static uint8_t * const host_buffer = host_buffer_padded + 2;
+static uint8_t *const host_buffer = host_buffer_padded + 2;
 static uint8_t params_copy[I2C_MAX_HOST_PACKET_SIZE] __aligned(4);
 static int host_i2c_resp_port;
 static int tx_pending;
@@ -244,7 +242,7 @@ static void i2c_send_response_packet(struct host_packet *pkt)
 
 	/*
 	 * Set the transmitter to be in 'not full' state to keep sending
-	 * '0xec' in the event loop. Because of this, the master i2c
+	 * '0xec' in the event loop. Because of this, the controller i2c
 	 * doesn't need to snoop the response stream to abort transaction.
 	 */
 	STM32_I2C_CR1(host_i2c_resp_port) |= STM32_I2C_CR1_TXIE;
@@ -288,7 +286,7 @@ static void i2c_process_command(void)
 	host_packet_receive(&i2c_packet);
 }
 
-#ifdef TCPCI_I2C_SLAVE
+#ifdef TCPCI_I2C_PERIPHERAL
 static void i2c_send_tcpc_response(int len)
 {
 	/* host_buffer data range, beyond this length, will return 0xec */
@@ -310,7 +308,7 @@ static void i2c_event_handler(int port)
 {
 	int i2c_isr;
 	static int rx_pending, buf_idx;
-#ifdef TCPCI_I2C_SLAVE
+#ifdef TCPCI_I2C_PERIPHERAL
 	int addr;
 #endif
 
@@ -318,7 +316,7 @@ static void i2c_event_handler(int port)
 
 	/*
 	 * Check for error conditions. Note, arbitration loss and bus error
-	 * are the only two errors we can get as a slave allowing clock
+	 * are the only two errors we can get as a peripheral allowing clock
 	 * stretching and in non-SMBus mode.
 	 */
 	if (i2c_isr & (STM32_I2C_ISR_ARLO | STM32_I2C_ISR_BERR)) {
@@ -330,20 +328,20 @@ static void i2c_event_handler(int port)
 
 		/* Clear error status bits */
 		STM32_I2C_ICR(port) |= STM32_I2C_ICR_BERRCF |
-				STM32_I2C_ICR_ARLOCF;
+				       STM32_I2C_ICR_ARLOCF;
 	}
 
-	/* Transfer matched our slave address */
+	/* Transfer matched our peripheral address */
 	if (i2c_isr & STM32_I2C_ISR_ADDR) {
 		if (i2c_isr & STM32_I2C_ISR_DIR) {
-			/* Transmitter slave */
+			/* Transmitter peripheral */
 			/* Clear transmit buffer */
 			STM32_I2C_ISR(port) |= STM32_I2C_ISR_TXE;
 
 			/* Enable txis interrupt to start response */
 			STM32_I2C_CR1(port) |= STM32_I2C_CR1_TXIE;
 		} else {
-			/* Receiver slave */
+			/* Receiver peripheral */
 			buf_idx = 0;
 			rx_pending = 1;
 		}
@@ -351,7 +349,7 @@ static void i2c_event_handler(int port)
 		/* Clear ADDR bit by writing to ADDRCF bit */
 		STM32_I2C_ICR(port) |= STM32_I2C_ICR_ADDRCF;
 		/* Inhibit sleep mode when addressed until STOPF flag is set */
-		disable_sleep(SLEEP_MASK_I2C_SLAVE);
+		disable_sleep(SLEEP_MASK_I2C_PERIPHERAL);
 	}
 
 	/* Receiver full event */
@@ -360,7 +358,7 @@ static void i2c_event_handler(int port)
 
 	/* Stop condition on bus */
 	if (i2c_isr & STM32_I2C_ISR_STOP) {
-#ifdef TCPCI_I2C_SLAVE
+#ifdef TCPCI_I2C_PERIPHERAL
 		/*
 		 * if tcpc is being addressed, and we received a stop
 		 * while rx is pending, then this is a write only to
@@ -380,10 +378,10 @@ static void i2c_event_handler(int port)
 		STM32_I2C_ICR(port) |= STM32_I2C_ICR_STOPCF;
 
 		/* No longer inhibit deep sleep after stop condition */
-		enable_sleep(SLEEP_MASK_I2C_SLAVE);
+		enable_sleep(SLEEP_MASK_I2C_PERIPHERAL);
 	}
 
-	/* Master requested STOP or RESTART */
+	/* Controller requested STOP or RESTART */
 	if (i2c_isr & STM32_I2C_ISR_NACK) {
 		/* Make sure TXIS interrupt is disabled */
 		STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE;
@@ -420,7 +418,7 @@ static void i2c_event_handler(int port)
 				 */
 				STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE;
 
-#ifdef TCPCI_I2C_SLAVE
+#ifdef TCPCI_I2C_PERIPHERAL
 				addr = STM32_I2C_ISR_ADDCODE(
 					STM32_I2C_ISR(port));
 				if (ADDR_IS_TCPC(addr))
@@ -439,18 +437,20 @@ static void i2c_event_handler(int port)
 		}
 	}
 }
-void i2c2_event_interrupt(void) { i2c_event_handler(I2C_PORT_EC); }
-DECLARE_IRQ(IRQ_SLAVE, i2c2_event_interrupt, 2);
+static void i2c2_event_interrupt(void)
+{
+	i2c_event_handler(I2C_PORT_EC);
+}
+DECLARE_IRQ(IRQ_PERIPHERAL, i2c2_event_interrupt, 2);
 #endif
 
 /*****************************************************************************/
 /* Interface */
 
-int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags,
-		  const uint8_t *out, int out_bytes,
-		  uint8_t *in, int in_bytes, int flags)
+int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out,
+		  int out_bytes, uint8_t *in, int in_bytes, int flags)
 {
-	int addr_8bit = I2C_GET_ADDR(slave_addr_flags) << 1;
+	int addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1;
 	int rv = EC_SUCCESS;
 	int i;
 	int xfer_start = flags & I2C_XFER_START;
@@ -458,7 +458,7 @@ int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags,
 
 #if defined(CONFIG_I2C_SCL_GATE_ADDR) && defined(CONFIG_I2C_SCL_GATE_PORT)
 	if (port == CONFIG_I2C_SCL_GATE_PORT &&
-	    slave_addr_flags == CONFIG_I2C_SCL_GATE_ADDR_FLAGS)
+	    addr_flags == CONFIG_I2C_SCL_GATE_ADDR_FLAGS)
 		gpio_set_level(CONFIG_I2C_SCL_GATE_GPIO, 1);
 #endif
 
@@ -495,13 +495,13 @@ int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags,
 		 * if we are not stopping, set RELOAD bit so that we can load
 		 * NBYTES again. if we are starting, then set START bit.
 		 */
-		STM32_I2C_CR2(port) =  ((out_bytes & 0xFF) << 16)
-			| addr_8bit
-			| ((in_bytes == 0 && xfer_stop) ?
-				STM32_I2C_CR2_AUTOEND : 0)
-			| ((in_bytes == 0 && !xfer_stop) ?
-				STM32_I2C_CR2_RELOAD : 0)
-			| (xfer_start ? STM32_I2C_CR2_START : 0);
+		STM32_I2C_CR2(port) =
+			((out_bytes & 0xFF) << 16) | addr_8bit |
+			((in_bytes == 0 && xfer_stop) ? STM32_I2C_CR2_AUTOEND :
+							0) |
+			((in_bytes == 0 && !xfer_stop) ? STM32_I2C_CR2_RELOAD :
+							 0) |
+			(xfer_start ? STM32_I2C_CR2_START : 0);
 
 		for (i = 0; i < out_bytes; i++) {
 			rv = wait_isr(port, STM32_I2C_ISR_TXIS);
@@ -524,11 +524,11 @@ int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags,
 		 * NBYTES again. if we were just transmitting, we need to
 		 * set START bit to send (re)start and begin read transaction.
 		 */
-		STM32_I2C_CR2(port) = ((in_bytes & 0xFF) << 16)
-			| STM32_I2C_CR2_RD_WRN | addr_8bit
-			| (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0)
-			| (!xfer_stop ? STM32_I2C_CR2_RELOAD : 0)
-			| (out_bytes || xfer_start ? STM32_I2C_CR2_START : 0);
+		STM32_I2C_CR2(port) =
+			((in_bytes & 0xFF) << 16) | STM32_I2C_CR2_RD_WRN |
+			addr_8bit | (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0) |
+			(!xfer_stop ? STM32_I2C_CR2_RELOAD : 0) |
+			(out_bytes || xfer_start ? STM32_I2C_CR2_START : 0);
 
 		for (i = 0; i < in_bytes; i++) {
 			/* Wait for receive buffer not empty */
@@ -569,7 +569,7 @@ int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags,
 
 		/*
 		 * Allow bus to idle for at least one 100KHz clock = 10 us.
-		 * This allows slaves on the bus to detect bus-idle before
+		 * This allows peripherals on the bus to detect bus-idle before
 		 * the next start condition.
 		 */
 		udelay(10);
@@ -582,7 +582,7 @@ int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags,
 
 #ifdef CONFIG_I2C_SCL_GATE_ADDR
 	if (port == CONFIG_I2C_SCL_GATE_PORT &&
-	    slave_addr_flags == CONFIG_I2C_SCL_GATE_ADDR_FLAGS)
+	    addr_flags == CONFIG_I2C_SCL_GATE_ADDR_FLAGS)
 		gpio_set_level(CONFIG_I2C_SCL_GATE_GPIO, 0);
 #endif
 
@@ -614,7 +614,7 @@ int i2c_raw_get_sda(int port)
 int i2c_get_line_levels(int port)
 {
 	return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) |
-		(i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
+	       (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
 }
 
 void i2c_init(void)
@@ -625,10 +625,11 @@ void i2c_init(void)
 	for (i = 0; i < i2c_ports_used; i++, p++)
 		i2c_init_port(p);
 
-#ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS
-	STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_RXIE | STM32_I2C_CR1_ERRIE
-			| STM32_I2C_CR1_ADDRIE | STM32_I2C_CR1_STOPIE
-			| STM32_I2C_CR1_NACKIE;
+#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
+	STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_RXIE | STM32_I2C_CR1_ERRIE |
+				      STM32_I2C_CR1_ADDRIE |
+				      STM32_I2C_CR1_STOPIE |
+				      STM32_I2C_CR1_NACKIE;
 #if defined(CONFIG_LOW_POWER_IDLE) && (I2C_PORT_EC == STM32_I2C1_PORT)
 	/*
 	 * If using low power idle and EC port is I2C1, then set I2C1 to wake
@@ -637,17 +638,17 @@ void i2c_init(void)
 	 */
 	STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_WUPEN;
 #endif
-	STM32_I2C_OAR1(I2C_PORT_EC) = 0x8000
-		| (I2C_GET_ADDR(CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS) << 1);
-#ifdef TCPCI_I2C_SLAVE
+	STM32_I2C_OAR1(I2C_PORT_EC) =
+		0x8000 | (I2C_STRIP_FLAGS(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) << 1);
+#ifdef TCPCI_I2C_PERIPHERAL
 	/*
 	 * Configure TCPC address with OA2[1] masked so that we respond
 	 * to CONFIG_TCPC_I2C_BASE_ADDR and CONFIG_TCPC_I2C_BASE_ADDR + 2.
 	 */
-	STM32_I2C_OAR2(I2C_PORT_EC) = 0x8100
-		| (I2C_GET_ADDR(CONFIG_TCPC_I2C_BASE_ADDR_FLAGS) << 1);
+	STM32_I2C_OAR2(I2C_PORT_EC) =
+		0x8100 |
+		(I2C_STRIP_FLAGS(CONFIG_TCPC_I2C_BASE_ADDR_FLAGS) << 1);
 #endif
-	task_enable_irq(IRQ_SLAVE);
+	task_enable_irq(IRQ_PERIPHERAL);
 #endif
 }
-
diff --git a/chip/stm32/i2c-stm32f3.c b/chip/stm32/i2c-stm32f3.c
deleted file mode 120000
index ce8523ea90..0000000000
--- a/chip/stm32/i2c-stm32f3.c
+++ /dev/null
@@ -1 +0,0 @@
-i2c-stm32f0.c
\ No newline at end of file
diff --git a/chip/stm32/i2c-stm32f3.c b/chip/stm32/i2c-stm32f3.c
new file mode 100644
index 0000000000..acd4d3aca6
--- /dev/null
+++ b/chip/stm32/i2c-stm32f3.c
@@ -0,0 +1,654 @@
+/* Copyright 2013 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "builtin/assert.h"
+#include "chipset.h"
+#include "clock.h"
+#include "common.h"
+#include "console.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "hwtimer.h"
+#include "i2c.h"
+#include "i2c_private.h"
+#include "registers.h"
+#include "system.h"
+#include "task.h"
+#include "timer.h"
+#include "usb_pd_tcpc.h"
+#include "usb_pd_tcpm.h"
+#include "util.h"
+
+/* Console output macros */
+#define CPUTS(outstr) cputs(CC_I2C, outstr)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
+
+/* Transmit timeout in microseconds */
+#define I2C_TX_TIMEOUT_CONTROLLER (10 * MSEC)
+
+#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
+#if (I2C_PORT_EC == STM32_I2C1_PORT)
+#define IRQ_PERIPHERAL STM32_IRQ_I2C1
+#else
+#define IRQ_PERIPHERAL STM32_IRQ_I2C2
+#endif
+#endif
+
+/* I2C port state data */
+struct i2c_port_data {
+	uint32_t timeout_us; /* Transaction timeout, or 0 to use default */
+	enum i2c_freq freq; /* Port clock speed */
+};
+static struct i2c_port_data pdata[I2C_PORT_COUNT];
+
+void i2c_set_timeout(int port, uint32_t timeout)
+{
+	pdata[port].timeout_us = timeout ? timeout : I2C_TX_TIMEOUT_CONTROLLER;
+}
+
+/* timingr register values for supported input clks / i2c clk rates */
+static const uint32_t busyloop_us[I2C_FREQ_COUNT] = {
+	[I2C_FREQ_1000KHZ] = 16, /* Enough for 2 bytes */
+	[I2C_FREQ_400KHZ] = 40, /* Enough for 2 bytes */
+	[I2C_FREQ_100KHZ] = 0, /* No busy looping at 100kHz (bus is slow) */
+};
+
+/**
+ * Wait for ISR register to contain the specified mask.
+ *
+ * Returns EC_SUCCESS, EC_ERROR_TIMEOUT if timed out waiting, or
+ * EC_ERROR_UNKNOWN if an error bit appeared in the status register.
+ */
+static int wait_isr(int port, int mask)
+{
+	uint32_t start = __hw_clock_source_read();
+	uint32_t delta = 0;
+
+	do {
+		int isr = STM32_I2C_ISR(port);
+
+		/* Check for errors */
+		if (isr & (STM32_I2C_ISR_ARLO | STM32_I2C_ISR_BERR |
+			   STM32_I2C_ISR_NACK))
+			return EC_ERROR_UNKNOWN;
+
+		/* Check for desired mask */
+		if ((isr & mask) == mask)
+			return EC_SUCCESS;
+
+		delta = __hw_clock_source_read() - start;
+
+		/**
+		 * Depending on the bus speed, busy loop for a while before
+		 * sleeping and letting other things run.
+		 */
+		if (delta >= busyloop_us[pdata[port].freq])
+			usleep(100);
+	} while (delta < pdata[port].timeout_us);
+
+	return EC_ERROR_TIMEOUT;
+}
+
+/* Supported i2c input clocks */
+enum stm32_i2c_clk_src {
+	I2C_CLK_SRC_48MHZ = 0,
+	I2C_CLK_SRC_8MHZ = 1,
+	I2C_CLK_SRC_COUNT,
+};
+
+/* timingr register values for supported input clks / i2c clk rates */
+static const uint32_t timingr_regs[I2C_CLK_SRC_COUNT][I2C_FREQ_COUNT] = {
+	[I2C_CLK_SRC_48MHZ] = {
+		[I2C_FREQ_1000KHZ] = 0x50100103,
+		[I2C_FREQ_400KHZ] = 0x50330609,
+		[I2C_FREQ_100KHZ] = 0xB0421214,
+	},
+	[I2C_CLK_SRC_8MHZ] = {
+		[I2C_FREQ_1000KHZ] = 0x00100306,
+		[I2C_FREQ_400KHZ] = 0x00310309,
+		[I2C_FREQ_100KHZ] = 0x10420f13,
+	},
+};
+
+int chip_i2c_set_freq(int port, enum i2c_freq freq)
+{
+	enum stm32_i2c_clk_src src = I2C_CLK_SRC_48MHZ;
+
+#if defined(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) && \
+	defined(CONFIG_LOW_POWER_IDLE) && (I2C_PORT_EC == STM32_I2C1_PORT)
+	if (port == STM32_I2C1_PORT) {
+		/*
+		 * Use HSI (8MHz) for i2c clock. This allows smooth wakeup
+		 * from STOP mode since HSI is only clock running immediately
+		 * upon exit from STOP mode.
+		 */
+		src = I2C_CLK_SRC_8MHZ;
+	}
+#endif
+
+	/* Disable port */
+	STM32_I2C_CR1(port) = 0;
+	STM32_I2C_CR2(port) = 0;
+	/* Set clock frequency */
+	STM32_I2C_TIMINGR(port) = timingr_regs[src][freq];
+	/* Enable port */
+	STM32_I2C_CR1(port) = STM32_I2C_CR1_PE;
+
+	pdata[port].freq = freq;
+
+	return EC_SUCCESS;
+}
+
+enum i2c_freq chip_i2c_get_freq(int port)
+{
+	return pdata[port].freq;
+}
+
+/**
+ * Initialize on the specified I2C port.
+ *
+ * @param p		the I2c port
+ */
+static int i2c_init_port(const struct i2c_port_t *p)
+{
+	int port = p->port;
+	int ret = EC_SUCCESS;
+	enum i2c_freq freq;
+
+	/* Enable clocks to I2C modules if necessary */
+	if (!(STM32_RCC_APB1ENR & (1 << (21 + port))))
+		STM32_RCC_APB1ENR |= 1 << (21 + port);
+
+	if (port == STM32_I2C1_PORT) {
+#if defined(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) && \
+	defined(CONFIG_LOW_POWER_IDLE) && (I2C_PORT_EC == STM32_I2C1_PORT)
+		/*
+		 * Use HSI (8MHz) for i2c clock. This allows smooth wakeup
+		 * from STOP mode since HSI is only clock running immediately
+		 * upon exit from STOP mode.
+		 */
+		STM32_RCC_CFGR3 &= ~0x10;
+#else
+		/* Use SYSCLK for i2c clock. */
+		STM32_RCC_CFGR3 |= 0x10;
+#endif
+	}
+
+	/* Configure GPIOs */
+	gpio_config_module(MODULE_I2C, 1);
+
+	/* Set clock frequency */
+	switch (p->kbps) {
+	case 1000:
+		freq = I2C_FREQ_1000KHZ;
+		break;
+	case 400:
+		freq = I2C_FREQ_400KHZ;
+		break;
+	case 100:
+		freq = I2C_FREQ_100KHZ;
+		break;
+	default: /* unknown speed, defaults to 100kBps */
+		CPRINTS("I2C bad speed %d kBps", p->kbps);
+		freq = I2C_FREQ_100KHZ;
+		ret = EC_ERROR_INVAL;
+	}
+
+	/* Set up initial bus frequencies */
+	chip_i2c_set_freq(p->port, freq);
+
+	/* Set up default timeout */
+	i2c_set_timeout(port, 0);
+
+	return ret;
+}
+
+/*****************************************************************************/
+#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
+/* Host command peripheral */
+/*
+ * Buffer for received host command packets (including prefix byte on request,
+ * and result/size on response).  After any protocol-specific headers, the
+ * buffers must be 32-bit aligned.
+ */
+static uint8_t host_buffer_padded[I2C_MAX_HOST_PACKET_SIZE + 4 +
+				  CONFIG_I2C_EXTRA_PACKET_SIZE] __aligned(4);
+static uint8_t *const host_buffer = host_buffer_padded + 2;
+static uint8_t params_copy[I2C_MAX_HOST_PACKET_SIZE] __aligned(4);
+static int host_i2c_resp_port;
+static int tx_pending;
+static int tx_index, tx_end;
+static struct host_packet i2c_packet;
+
+static void i2c_send_response_packet(struct host_packet *pkt)
+{
+	int size = pkt->response_size;
+	uint8_t *out = host_buffer;
+
+	/* Ignore host command in-progress */
+	if (pkt->driver_result == EC_RES_IN_PROGRESS)
+		return;
+
+	/* Write result and size to first two bytes. */
+	*out++ = pkt->driver_result;
+	*out++ = size;
+
+	/* host_buffer data range */
+	tx_index = 0;
+	tx_end = size + 2;
+
+	/*
+	 * Set the transmitter to be in 'not full' state to keep sending
+	 * '0xec' in the event loop. Because of this, the controller i2c
+	 * doesn't need to snoop the response stream to abort transaction.
+	 */
+	STM32_I2C_CR1(host_i2c_resp_port) |= STM32_I2C_CR1_TXIE;
+}
+
+/* Process the command in the i2c host buffer */
+static void i2c_process_command(void)
+{
+	char *buff = host_buffer;
+
+	/*
+	 * TODO(crosbug.com/p/29241): Combine this functionality with the
+	 * i2c_process_command function in chip/stm32/i2c-stm32f.c to make one
+	 * host command i2c process function which handles all protocol
+	 * versions.
+	 */
+	i2c_packet.send_response = i2c_send_response_packet;
+
+	i2c_packet.request = (const void *)(&buff[1]);
+	i2c_packet.request_temp = params_copy;
+	i2c_packet.request_max = sizeof(params_copy);
+	/* Don't know the request size so pass in the entire buffer */
+	i2c_packet.request_size = I2C_MAX_HOST_PACKET_SIZE;
+
+	/*
+	 * Stuff response at buff[2] to leave the first two bytes of
+	 * buffer available for the result and size to send over i2c.  Note
+	 * that this 2-byte offset and the 2-byte offset from host_buffer
+	 * add up to make the response buffer 32-bit aligned.
+	 */
+	i2c_packet.response = (void *)(&buff[2]);
+	i2c_packet.response_max = I2C_MAX_HOST_PACKET_SIZE;
+	i2c_packet.response_size = 0;
+
+	if (*buff >= EC_COMMAND_PROTOCOL_3) {
+		i2c_packet.driver_result = EC_RES_SUCCESS;
+	} else {
+		/* Only host command protocol 3 is supported. */
+		i2c_packet.driver_result = EC_RES_INVALID_HEADER;
+	}
+	host_packet_receive(&i2c_packet);
+}
+
+#ifdef TCPCI_I2C_PERIPHERAL
+static void i2c_send_tcpc_response(int len)
+{
+	/* host_buffer data range, beyond this length, will return 0xec */
+	tx_index = 0;
+	tx_end = len;
+
+	/* enable transmit interrupt and use irq to send data back */
+	STM32_I2C_CR1(host_i2c_resp_port) |= STM32_I2C_CR1_TXIE;
+}
+
+static void i2c_process_tcpc_command(int read, int addr, int len)
+{
+	tcpc_i2c_process(read, TCPC_ADDR_TO_PORT(addr), len, &host_buffer[0],
+			 i2c_send_tcpc_response);
+}
+#endif
+
+static void i2c_event_handler(int port)
+{
+	int i2c_isr;
+	static int rx_pending, buf_idx;
+#ifdef TCPCI_I2C_PERIPHERAL
+	int addr;
+#endif
+
+	i2c_isr = STM32_I2C_ISR(port);
+
+	/*
+	 * Check for error conditions. Note, arbitration loss and bus error
+	 * are the only two errors we can get as a peripheral allowing clock
+	 * stretching and in non-SMBus mode.
+	 */
+	if (i2c_isr & (STM32_I2C_ISR_ARLO | STM32_I2C_ISR_BERR)) {
+		rx_pending = 0;
+		tx_pending = 0;
+
+		/* Make sure TXIS interrupt is disabled */
+		STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE;
+
+		/* Clear error status bits */
+		STM32_I2C_ICR(port) |= STM32_I2C_ICR_BERRCF |
+				       STM32_I2C_ICR_ARLOCF;
+	}
+
+	/* Transfer matched our peripheral address */
+	if (i2c_isr & STM32_I2C_ISR_ADDR) {
+		if (i2c_isr & STM32_I2C_ISR_DIR) {
+			/* Transmitter peripheral */
+			/* Clear transmit buffer */
+			STM32_I2C_ISR(port) |= STM32_I2C_ISR_TXE;
+
+			/* Enable txis interrupt to start response */
+			STM32_I2C_CR1(port) |= STM32_I2C_CR1_TXIE;
+		} else {
+			/* Receiver peripheral */
+			buf_idx = 0;
+			rx_pending = 1;
+		}
+
+		/* Clear ADDR bit by writing to ADDRCF bit */
+		STM32_I2C_ICR(port) |= STM32_I2C_ICR_ADDRCF;
+		/* Inhibit sleep mode when addressed until STOPF flag is set */
+		disable_sleep(SLEEP_MASK_I2C_PERIPHERAL);
+	}
+
+	/* Receiver full event */
+	if (i2c_isr & STM32_I2C_ISR_RXNE)
+		host_buffer[buf_idx++] = STM32_I2C_RXDR(port);
+
+	/* Stop condition on bus */
+	if (i2c_isr & STM32_I2C_ISR_STOP) {
+#ifdef TCPCI_I2C_PERIPHERAL
+		/*
+		 * if tcpc is being addressed, and we received a stop
+		 * while rx is pending, then this is a write only to
+		 * the tcpc.
+		 */
+		addr = STM32_I2C_ISR_ADDCODE(STM32_I2C_ISR(port));
+		if (rx_pending && ADDR_IS_TCPC(addr))
+			i2c_process_tcpc_command(0, addr, buf_idx);
+#endif
+		rx_pending = 0;
+		tx_pending = 0;
+
+		/* Make sure TXIS interrupt is disabled */
+		STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE;
+
+		/* Clear STOPF bit by writing to STOPCF bit */
+		STM32_I2C_ICR(port) |= STM32_I2C_ICR_STOPCF;
+
+		/* No longer inhibit deep sleep after stop condition */
+		enable_sleep(SLEEP_MASK_I2C_PERIPHERAL);
+	}
+
+	/* Controller requested STOP or RESTART */
+	if (i2c_isr & STM32_I2C_ISR_NACK) {
+		/* Make sure TXIS interrupt is disabled */
+		STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE;
+		/* Clear NACK */
+		STM32_I2C_ICR(port) |= STM32_I2C_ICR_NACKCF;
+		/* Resend last byte on RESTART */
+		if (port == I2C_PORT_EC && tx_index)
+			tx_index--;
+	}
+
+	/* Transmitter empty event */
+	if (i2c_isr & STM32_I2C_ISR_TXIS) {
+		if (port == I2C_PORT_EC) { /* host is waiting for PD response */
+			if (tx_pending) {
+				if (tx_index < tx_end) {
+					STM32_I2C_TXDR(port) =
+						host_buffer[tx_index++];
+				} else {
+					STM32_I2C_TXDR(port) = 0xec;
+					/*
+					 * Set tx_index = 0 to prevent NACK
+					 * handler resending last buffer byte.
+					 */
+					tx_index = 0;
+					tx_end = 0;
+					/* No pending data */
+					tx_pending = 0;
+				}
+			} else if (rx_pending) {
+				host_i2c_resp_port = port;
+				/*
+				 * Disable TXIS interrupt, transmission will
+				 * be prepared by host command task.
+				 */
+				STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE;
+
+#ifdef TCPCI_I2C_PERIPHERAL
+				addr = STM32_I2C_ISR_ADDCODE(
+					STM32_I2C_ISR(port));
+				if (ADDR_IS_TCPC(addr))
+					i2c_process_tcpc_command(1, addr,
+								 buf_idx);
+				else
+#endif
+					i2c_process_command();
+
+				/* Reset host buffer after end of transfer */
+				rx_pending = 0;
+				tx_pending = 1;
+			} else {
+				STM32_I2C_TXDR(port) = 0xec;
+			}
+		}
+	}
+}
+static void i2c2_event_interrupt(void)
+{
+	i2c_event_handler(I2C_PORT_EC);
+}
+DECLARE_IRQ(IRQ_PERIPHERAL, i2c2_event_interrupt, 2);
+#endif
+
+/*****************************************************************************/
+/* Interface */
+
+int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out,
+		  int out_bytes, uint8_t *in, int in_bytes, int flags)
+{
+	int addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1;
+	int rv = EC_SUCCESS;
+	int i;
+	int xfer_start = flags & I2C_XFER_START;
+	int xfer_stop = flags & I2C_XFER_STOP;
+
+#if defined(CONFIG_I2C_SCL_GATE_ADDR) && defined(CONFIG_I2C_SCL_GATE_PORT)
+	if (port == CONFIG_I2C_SCL_GATE_PORT &&
+	    addr_flags == CONFIG_I2C_SCL_GATE_ADDR_FLAGS)
+		gpio_set_level(CONFIG_I2C_SCL_GATE_GPIO, 1);
+#endif
+
+	ASSERT(out || !out_bytes);
+	ASSERT(in || !in_bytes);
+
+	/* Clear status */
+	if (xfer_start) {
+		uint32_t cr2 = STM32_I2C_CR2(port);
+
+		STM32_I2C_ICR(port) = STM32_I2C_ICR_ALL;
+		STM32_I2C_CR2(port) = 0;
+		if (cr2 & STM32_I2C_CR2_RELOAD) {
+			/*
+			 * If I2C_XFER_START flag is on and we've set RELOAD=1
+			 * in previous chip_i2c_xfer() call. Then we are
+			 * probably in the middle of an i2c transaction.
+			 *
+			 * In this case, we need to clear the RELOAD bit and
+			 * wait for Transfer Complete (TC) flag, to make sure
+			 * the chip is not expecting another NBYTES data, And
+			 * send repeated-start correctly.
+			 */
+			rv = wait_isr(port, STM32_I2C_ISR_TC);
+			if (rv)
+				goto xfer_exit;
+		}
+	}
+
+	if (out_bytes || !in_bytes) {
+		/*
+		 * Configure the write transfer: if we are stopping then set
+		 * AUTOEND bit to automatically set STOP bit after NBYTES.
+		 * if we are not stopping, set RELOAD bit so that we can load
+		 * NBYTES again. if we are starting, then set START bit.
+		 */
+		STM32_I2C_CR2(port) =
+			((out_bytes & 0xFF) << 16) | addr_8bit |
+			((in_bytes == 0 && xfer_stop) ? STM32_I2C_CR2_AUTOEND :
+							0) |
+			((in_bytes == 0 && !xfer_stop) ? STM32_I2C_CR2_RELOAD :
+							 0) |
+			(xfer_start ? STM32_I2C_CR2_START : 0);
+
+		for (i = 0; i < out_bytes; i++) {
+			rv = wait_isr(port, STM32_I2C_ISR_TXIS);
+			if (rv)
+				goto xfer_exit;
+			/* Write next data byte */
+			STM32_I2C_TXDR(port) = out[i];
+		}
+	}
+	if (in_bytes) {
+		if (out_bytes) { /* wait for completion of the write */
+			rv = wait_isr(port, STM32_I2C_ISR_TC);
+			if (rv)
+				goto xfer_exit;
+		}
+		/*
+		 * Configure the read transfer: if we are stopping then set
+		 * AUTOEND bit to automatically set STOP bit after NBYTES.
+		 * if we are not stopping, set RELOAD bit so that we can load
+		 * NBYTES again. if we were just transmitting, we need to
+		 * set START bit to send (re)start and begin read transaction.
+		 */
+		STM32_I2C_CR2(port) =
+			((in_bytes & 0xFF) << 16) | STM32_I2C_CR2_RD_WRN |
+			addr_8bit | (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0) |
+			(!xfer_stop ? STM32_I2C_CR2_RELOAD : 0) |
+			(out_bytes || xfer_start ? STM32_I2C_CR2_START : 0);
+
+		for (i = 0; i < in_bytes; i++) {
+			/* Wait for receive buffer not empty */
+			rv = wait_isr(port, STM32_I2C_ISR_RXNE);
+			if (rv)
+				goto xfer_exit;
+
+			in[i] = STM32_I2C_RXDR(port);
+		}
+	}
+
+	/*
+	 * If we are stopping, then we already set AUTOEND and we should
+	 * wait for the stop bit to be transmitted. Otherwise, we set
+	 * the RELOAD bit and we should wait for transfer complete
+	 * reload (TCR).
+	 */
+	rv = wait_isr(port, xfer_stop ? STM32_I2C_ISR_STOP : STM32_I2C_ISR_TCR);
+	if (rv)
+		goto xfer_exit;
+
+xfer_exit:
+	/* clear status */
+	if (xfer_stop)
+		STM32_I2C_ICR(port) = STM32_I2C_ICR_ALL;
+
+	/* On error, queue a stop condition */
+	if (rv) {
+		/* queue a STOP condition */
+		STM32_I2C_CR2(port) |= STM32_I2C_CR2_STOP;
+		/* wait for it to take effect */
+		/* Wait up to 100 us for bus idle */
+		for (i = 0; i < 10; i++) {
+			if (!(STM32_I2C_ISR(port) & STM32_I2C_ISR_BUSY))
+				break;
+			udelay(10);
+		}
+
+		/*
+		 * Allow bus to idle for at least one 100KHz clock = 10 us.
+		 * This allows peripherals on the bus to detect bus-idle before
+		 * the next start condition.
+		 */
+		udelay(10);
+		/* re-initialize the controller */
+		STM32_I2C_CR2(port) = 0;
+		STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_PE;
+		udelay(10);
+		STM32_I2C_CR1(port) |= STM32_I2C_CR1_PE;
+	}
+
+#ifdef CONFIG_I2C_SCL_GATE_ADDR
+	if (port == CONFIG_I2C_SCL_GATE_PORT &&
+	    addr_flags == CONFIG_I2C_SCL_GATE_ADDR_FLAGS)
+		gpio_set_level(CONFIG_I2C_SCL_GATE_GPIO, 0);
+#endif
+
+	return rv;
+}
+
+int i2c_raw_get_scl(int port)
+{
+	enum gpio_signal g;
+
+	if (get_scl_from_i2c_port(port, &g) == EC_SUCCESS)
+		return gpio_get_level(g);
+
+	/* If no SCL pin defined for this port, then return 1 to appear idle. */
+	return 1;
+}
+
+int i2c_raw_get_sda(int port)
+{
+	enum gpio_signal g;
+
+	if (get_sda_from_i2c_port(port, &g) == EC_SUCCESS)
+		return gpio_get_level(g);
+
+	/* If no SCL pin defined for this port, then return 1 to appear idle. */
+	return 1;
+}
+
+int i2c_get_line_levels(int port)
+{
+	return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) |
+	       (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
+}
+
+void i2c_init(void)
+{
+	const struct i2c_port_t *p = i2c_ports;
+	int i;
+
+	for (i = 0; i < i2c_ports_used; i++, p++)
+		i2c_init_port(p);
+
+#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
+	STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_RXIE | STM32_I2C_CR1_ERRIE |
+				      STM32_I2C_CR1_ADDRIE |
+				      STM32_I2C_CR1_STOPIE |
+				      STM32_I2C_CR1_NACKIE;
+#if defined(CONFIG_LOW_POWER_IDLE) && (I2C_PORT_EC == STM32_I2C1_PORT)
+	/*
+	 * If using low power idle and EC port is I2C1, then set I2C1 to wake
+	 * from STOP mode on address match. Note, this only works on I2C1 and
+	 * only if the clock to I2C1 is HSI 8MHz.
+	 */
+	STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_WUPEN;
+#endif
+	STM32_I2C_OAR1(I2C_PORT_EC) =
+		0x8000 | (I2C_STRIP_FLAGS(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) << 1);
+#ifdef TCPCI_I2C_PERIPHERAL
+	/*
+	 * Configure TCPC address with OA2[1] masked so that we respond
+	 * to CONFIG_TCPC_I2C_BASE_ADDR and CONFIG_TCPC_I2C_BASE_ADDR + 2.
+	 */
+	STM32_I2C_OAR2(I2C_PORT_EC) =
+		0x8100 |
+		(I2C_STRIP_FLAGS(CONFIG_TCPC_I2C_BASE_ADDR_FLAGS) << 1);
+#endif
+	task_enable_irq(IRQ_PERIPHERAL);
+#endif
+}
diff --git a/chip/stm32/i2c-stm32f4.c b/chip/stm32/i2c-stm32f4.c
index 515aed20eb..9f4d799912 100644
--- a/chip/stm32/i2c-stm32f4.c
+++ b/chip/stm32/i2c-stm32f4.c
@@ -1,13 +1,16 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "builtin/assert.h"
 #include "chipset.h"
 #include "clock.h"
 #include "common.h"
 #include "console.h"
 #include "dma.h"
+#include "gpio.h"
 #include "hooks.h"
 #include "i2c.h"
 #include "registers.h"
@@ -18,20 +21,20 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
 
 #define I2C_ERROR_FAILED_START EC_ERROR_INTERNAL_FIRST
 
 /* Transmit timeout in microseconds */
-#define I2C_TX_TIMEOUT_MASTER   (10 * MSEC)
+#define I2C_TX_TIMEOUT_CONTROLLER (10 * MSEC)
 
-#ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS
+#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
 #if (I2C_PORT_EC == STM32_I2C1_PORT)
-#define IRQ_SLAVE_EV STM32_IRQ_I2C1_EV
-#define IRQ_SLAVE_ER STM32_IRQ_I2C1_ER
+#define IRQ_PERIPHERAL_EV STM32_IRQ_I2C1_EV
+#define IRQ_PERIPHERAL_ER STM32_IRQ_I2C1_ER
 #else
-#define IRQ_SLAVE_EV STM32_IRQ_I2C2_EV
-#define IRQ_SLAVE_ER STM32_IRQ_I2C2_ER
+#define IRQ_PERIPHERAL_EV STM32_IRQ_I2C2_EV
+#define IRQ_PERIPHERAL_ER STM32_IRQ_I2C2_ER
 #endif
 #endif
 
@@ -41,36 +44,36 @@
  * two sets of functions to handle this for stm32f4. In stm32f446, we
  * only have one FMP block so we'll hardcode its port number.
  */
-#define STM32F4_FMPI2C_PORT	3
+#define STM32F4_FMPI2C_PORT 3
 
 static const __unused struct dma_option dma_tx_option[I2C_PORT_COUNT] = {
-	{STM32_DMAC_I2C1_TX, (void *)&STM32_I2C_DR(STM32_I2C1_PORT),
-	 STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
-	 STM32_DMA_CCR_CHANNEL(STM32_I2C1_TX_REQ_CH)},
-	{STM32_DMAC_I2C2_TX, (void *)&STM32_I2C_DR(STM32_I2C2_PORT),
-	 STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
-	 STM32_DMA_CCR_CHANNEL(STM32_I2C2_TX_REQ_CH)},
-	{STM32_DMAC_I2C3_TX, (void *)&STM32_I2C_DR(STM32_I2C3_PORT),
-	 STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
-	 STM32_DMA_CCR_CHANNEL(STM32_I2C3_TX_REQ_CH)},
-	{STM32_DMAC_FMPI2C4_TX, (void *)&STM32_FMPI2C_TXDR(STM32_FMPI2C4_PORT),
-	 STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
-	 STM32_DMA_CCR_CHANNEL(STM32_FMPI2C4_TX_REQ_CH)},
+	{ STM32_DMAC_I2C1_TX, (void *)&STM32_I2C_DR(STM32_I2C1_PORT),
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
+		  STM32_DMA_CCR_CHANNEL(STM32_I2C1_TX_REQ_CH) },
+	{ STM32_DMAC_I2C2_TX, (void *)&STM32_I2C_DR(STM32_I2C2_PORT),
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
+		  STM32_DMA_CCR_CHANNEL(STM32_I2C2_TX_REQ_CH) },
+	{ STM32_DMAC_I2C3_TX, (void *)&STM32_I2C_DR(STM32_I2C3_PORT),
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
+		  STM32_DMA_CCR_CHANNEL(STM32_I2C3_TX_REQ_CH) },
+	{ STM32_DMAC_FMPI2C4_TX, (void *)&STM32_FMPI2C_TXDR(STM32_FMPI2C4_PORT),
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
+		  STM32_DMA_CCR_CHANNEL(STM32_FMPI2C4_TX_REQ_CH) },
 };
 
 static const struct dma_option dma_rx_option[I2C_PORT_COUNT] = {
-	{STM32_DMAC_I2C1_RX, (void *)&STM32_I2C_DR(STM32_I2C1_PORT),
-	 STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
-	 STM32_DMA_CCR_CHANNEL(STM32_I2C1_RX_REQ_CH)},
-	{STM32_DMAC_I2C2_RX, (void *)&STM32_I2C_DR(STM32_I2C2_PORT),
-	 STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
-	 STM32_DMA_CCR_CHANNEL(STM32_I2C2_RX_REQ_CH)},
-	{STM32_DMAC_I2C3_RX, (void *)&STM32_I2C_DR(STM32_I2C3_PORT),
-	 STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
-	 STM32_DMA_CCR_CHANNEL(STM32_I2C3_RX_REQ_CH)},
-	{STM32_DMAC_FMPI2C4_RX, (void *)&STM32_FMPI2C_RXDR(STM32_FMPI2C4_PORT),
-	 STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
-	 STM32_DMA_CCR_CHANNEL(STM32_FMPI2C4_RX_REQ_CH)},
+	{ STM32_DMAC_I2C1_RX, (void *)&STM32_I2C_DR(STM32_I2C1_PORT),
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
+		  STM32_DMA_CCR_CHANNEL(STM32_I2C1_RX_REQ_CH) },
+	{ STM32_DMAC_I2C2_RX, (void *)&STM32_I2C_DR(STM32_I2C2_PORT),
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
+		  STM32_DMA_CCR_CHANNEL(STM32_I2C2_RX_REQ_CH) },
+	{ STM32_DMAC_I2C3_RX, (void *)&STM32_I2C_DR(STM32_I2C3_PORT),
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
+		  STM32_DMA_CCR_CHANNEL(STM32_I2C3_RX_REQ_CH) },
+	{ STM32_DMAC_FMPI2C4_RX, (void *)&STM32_FMPI2C_RXDR(STM32_FMPI2C4_PORT),
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
+		  STM32_DMA_CCR_CHANNEL(STM32_FMPI2C4_RX_REQ_CH) },
 };
 
 /* Callback for ISR to wake task on DMA complete. */
@@ -79,7 +82,7 @@ static inline void _i2c_dma_wake_callback(void *cb_data, int port)
 	task_id_t id = (task_id_t)(int)cb_data;
 
 	if (id != TASK_ID_INVALID)
-		task_set_event(id, TASK_EVENT_I2C_COMPLETION(port), 0);
+		task_set_event(id, TASK_EVENT_I2C_COMPLETION(port));
 }
 
 /* Each callback is hardcoded to an I2C channel. */
@@ -133,7 +136,7 @@ void i2c_dma_enable_tc_interrupt(enum dma_channel stream, int port)
 #define UNSET 0
 static int wait_sr1_poll(int port, int mask, int val, int poll)
 {
-	uint64_t timeout = get_time().val + I2C_TX_TIMEOUT_MASTER;
+	uint64_t timeout = get_time().val + I2C_TX_TIMEOUT_CONTROLLER;
 
 	while (get_time().val < timeout) {
 		int sr1 = STM32_I2C_SR1(port);
@@ -162,16 +165,15 @@ static int wait_sr1(int port, int mask)
 	return wait_sr1_poll(port, mask, SET, 100);
 }
 
-
 /**
- * Send a start condition and slave address on the specified port.
+ * Send a start condition and peripheral address on the specified port.
  *
  * @param port		I2C port
- * @param slave_addr	Slave address, with LSB set for receive-mode
+ * @param addr_8bit	I2C address, with LSB set for receive-mode
  *
  * @return Non-zero if error.
  */
-static int send_start(const int port, const uint16_t slave_addr_8bit)
+static int send_start(const int port, const uint16_t addr_8bit)
 {
 	int rv;
 
@@ -181,8 +183,8 @@ static int send_start(const int port, const uint16_t slave_addr_8bit)
 	if (rv)
 		return I2C_ERROR_FAILED_START;
 
-	/* Write slave address */
-	STM32_I2C_DR(port) = slave_addr_8bit;
+	/* Write peripheral address */
+	STM32_I2C_DR(port) = addr_8bit;
 	rv = wait_sr1_poll(port, STM32_I2C_SR1_ADDR, SET, 1);
 	if (rv)
 		return rv;
@@ -224,14 +226,14 @@ static const struct i2c_port_t *find_port(int port)
  */
 static int wait_fmpi2c_isr_poll(int port, int mask, int val, int poll)
 {
-	uint64_t timeout = get_time().val + I2C_TX_TIMEOUT_MASTER;
+	uint64_t timeout = get_time().val + I2C_TX_TIMEOUT_CONTROLLER;
 
 	while (get_time().val < timeout) {
 		int isr = STM32_FMPI2C_ISR(port);
 
 		/* Check for errors */
-		if (isr & (FMPI2C_ISR_ARLO | FMPI2C_ISR_BERR |
-			   FMPI2C_ISR_NACKF)) {
+		if (isr &
+		    (FMPI2C_ISR_ARLO | FMPI2C_ISR_BERR | FMPI2C_ISR_NACKF)) {
 			return EC_ERROR_UNKNOWN;
 		}
 
@@ -254,28 +256,27 @@ static int wait_fmpi2c_isr(int port, int mask)
 }
 
 /**
- * Send a start condition and slave address on the specified port.
+ * Send a start condition and peripheral address on the specified port.
  *
  * @param port		I2C port
- * @param slave_addr	Slave address
+ * @param addr_8bit	I2C address
  * @param size		bytes to transfer
  * @param is_read	read, or write?
  *
  * @return Non-zero if error.
  */
-static int send_fmpi2c_start(const int port, const uint16_t slave_addr_8bit,
-			     int size, int is_read)
+static int send_fmpi2c_start(const int port, const uint16_t addr_8bit, int size,
+			     int is_read)
 {
 	uint32_t reg;
 
 	/* Send start bit */
 	reg = STM32_FMPI2C_CR2(port);
 	reg &= ~(FMPI2C_CR2_SADD_MASK | FMPI2C_CR2_SIZE_MASK |
-		FMPI2C_CR2_RELOAD | FMPI2C_CR2_AUTOEND |
-		FMPI2C_CR2_RD_WRN | FMPI2C_CR2_START | FMPI2C_CR2_STOP);
-	reg |= FMPI2C_CR2_START | FMPI2C_CR2_AUTOEND |
-		slave_addr_8bit | FMPI2C_CR2_SIZE(size) |
-		(is_read ? FMPI2C_CR2_RD_WRN : 0);
+		 FMPI2C_CR2_RELOAD | FMPI2C_CR2_AUTOEND | FMPI2C_CR2_RD_WRN |
+		 FMPI2C_CR2_START | FMPI2C_CR2_STOP);
+	reg |= FMPI2C_CR2_START | FMPI2C_CR2_AUTOEND | addr_8bit |
+	       FMPI2C_CR2_SIZE(size) | (is_read ? FMPI2C_CR2_RD_WRN : 0);
 	STM32_FMPI2C_CR2(port) = reg;
 
 	return EC_SUCCESS;
@@ -298,17 +299,17 @@ static void i2c_set_freq_port(const struct i2c_port_t *p)
 
 		/* FMP I2C clock set. */
 		STM32_FMPI2C_CR1(port) &= ~FMPI2C_CR1_PE;
-		prescalar = (freq / (p->kbps * 1000 *
-			     (0x12 + 1 + 0xe + 1 + 1))) - 1;
+		prescalar =
+			(freq / (p->kbps * 1000 * (0x12 + 1 + 0xe + 1 + 1))) -
+			1;
 		actual = freq / ((prescalar + 1) * (0x12 + 1 + 0xe + 1 + 1));
 
-		reg = FMPI2C_TIMINGR_SCLL(0x12) |
-			FMPI2C_TIMINGR_SCLH(0xe) |
-			FMPI2C_TIMINGR_PRESC(prescalar);
+		reg = FMPI2C_TIMINGR_SCLL(0x12) | FMPI2C_TIMINGR_SCLH(0xe) |
+		      FMPI2C_TIMINGR_PRESC(prescalar);
 		STM32_FMPI2C_TIMINGR(port) = reg;
 
-		CPRINTS("port %d target %d, pre %d, act %d, reg 0x%08x",
-			port, p->kbps, prescalar, actual, reg);
+		CPRINTS("port %d target %d, pre %d, act %d, reg 0x%08x", port,
+			p->kbps, prescalar, actual, reg);
 
 		STM32_FMPI2C_CR1(port) |= FMPI2C_CR1_PE;
 		udelay(10);
@@ -321,9 +322,9 @@ static void i2c_set_freq_port(const struct i2c_port_t *p)
 		if (p->kbps > 100) {
 			STM32_I2C_CCR(port) = freq / (2 * MSEC * p->kbps);
 		} else {
-			STM32_I2C_CCR(port) = STM32_I2C_CCR_FM
-				| STM32_I2C_CCR_DUTY
-				| (freq / (16 + 9 * MSEC * p->kbps));
+			STM32_I2C_CCR(port) =
+				STM32_I2C_CCR_FM | STM32_I2C_CCR_DUTY |
+				(freq / (16 + 9 * MSEC * p->kbps));
 		}
 		STM32_I2C_CR2(port) = freq / SECOND;
 		STM32_I2C_TRISE(port) = freq / SECOND + 1;
@@ -382,17 +383,17 @@ static void fmpi2c_clear_regs(int port)
 	STM32_FMPI2C_ICR(port) = 0xffffffff;
 
 	/* Clear start, stop, NACK, etc. bits to get us in a known state */
-	STM32_FMPI2C_CR2(port) &= ~(FMPI2C_CR2_START | FMPI2C_CR2_STOP |
-				FMPI2C_CR2_RD_WRN | FMPI2C_CR2_NACK |
-				FMPI2C_CR2_AUTOEND |
-				FMPI2C_CR2_SADD_MASK | FMPI2C_CR2_SIZE_MASK);
+	STM32_FMPI2C_CR2(port) &=
+		~(FMPI2C_CR2_START | FMPI2C_CR2_STOP | FMPI2C_CR2_RD_WRN |
+		  FMPI2C_CR2_NACK | FMPI2C_CR2_AUTOEND | FMPI2C_CR2_SADD_MASK |
+		  FMPI2C_CR2_SIZE_MASK);
 }
 
 /**
  * Perform an i2c transaction
  *
  * @param port		i2c port to use
- * @param slave_addr	the i2c slave addr
+ * @param addr_8bit	the i2c address
  * @param out		source buffer for data
  * @param out_bytes	bytes of data to write
  * @param in		destination buffer for data
@@ -401,9 +402,9 @@ static void fmpi2c_clear_regs(int port)
  *
  * @return		EC_SUCCESS on success.
  */
-static int chip_fmpi2c_xfer(const int port, const uint16_t slave_addr_8bit,
-			    const uint8_t *out, int out_bytes,
-			    uint8_t *in, int in_bytes, int flags)
+static int chip_fmpi2c_xfer(const int port, const uint16_t addr_8bit,
+			    const uint8_t *out, int out_bytes, uint8_t *in,
+			    int in_bytes, int flags)
 {
 	int started = (flags & I2C_XFER_START) ? 0 : 1;
 	int rv = EC_SUCCESS;
@@ -422,8 +423,8 @@ static int chip_fmpi2c_xfer(const int port, const uint16_t slave_addr_8bit,
 
 	/* No out bytes and no in bytes means just check for active */
 	if (out_bytes || !in_bytes) {
-		rv = send_fmpi2c_start(
-			port, slave_addr_8bit, out_bytes, FMPI2C_WRITE);
+		rv = send_fmpi2c_start(port, addr_8bit, out_bytes,
+				       FMPI2C_WRITE);
 		if (rv)
 			goto xfer_exit;
 
@@ -448,8 +449,8 @@ static int chip_fmpi2c_xfer(const int port, const uint16_t slave_addr_8bit,
 		dma_start_rx(dma, in_bytes, in);
 		i2c_dma_enable_tc_interrupt(dma->channel, port);
 
-		rv_start = send_fmpi2c_start(
-				port, slave_addr_8bit, in_bytes, FMPI2C_READ);
+		rv_start = send_fmpi2c_start(port, addr_8bit, in_bytes,
+					     FMPI2C_READ);
 		if (rv_start)
 			goto xfer_exit;
 
@@ -458,9 +459,8 @@ static int chip_fmpi2c_xfer(const int port, const uint16_t slave_addr_8bit,
 			goto xfer_exit;
 		STM32_FMPI2C_CR1(port) |= FMPI2C_CR1_RXDMAEN;
 
-		rv = task_wait_event_mask(
-				TASK_EVENT_I2C_COMPLETION(port),
-				DMA_TRANSFER_TIMEOUT_US);
+		rv = task_wait_event_mask(TASK_EVENT_I2C_COMPLETION(port),
+					  DMA_TRANSFER_TIMEOUT_US);
 		if (rv & TASK_EVENT_I2C_COMPLETION(port))
 			rv = EC_SUCCESS;
 		else
@@ -476,7 +476,7 @@ static int chip_fmpi2c_xfer(const int port, const uint16_t slave_addr_8bit,
 		STM32_FMPI2C_CR1(port) &= ~FMPI2C_CR1_RXDMAEN;
 	}
 
- xfer_exit:
+xfer_exit:
 	/* On error, queue a stop condition */
 	if (rv) {
 		flags |= I2C_XFER_STOP;
@@ -490,7 +490,8 @@ static int chip_fmpi2c_xfer(const int port, const uint16_t slave_addr_8bit,
 			const struct i2c_port_t *p;
 
 			CPRINTS("chip_fmpi2c_xfer start error; "
-				"unwedging and resetting i2c %d", port);
+				"unwedging and resetting i2c %d",
+				port);
 
 			p = find_port(port);
 			i2c_unwedge(port);
@@ -509,7 +510,7 @@ static int chip_fmpi2c_xfer(const int port, const uint16_t slave_addr_8bit,
 
 		/*
 		 * Allow bus to idle for at least one 100KHz clock = 10 us.
-		 * This allows slaves on the bus to detect bus-idle before
+		 * This allows peripherals on the bus to detect bus-idle before
 		 * the next start condition.
 		 */
 		STM32_FMPI2C_CR1(port) &= ~FMPI2C_CR1_PE;
@@ -520,7 +521,6 @@ static int chip_fmpi2c_xfer(const int port, const uint16_t slave_addr_8bit,
 	return rv;
 }
 
-
 /**
  * Clear status regs on the specified I2C port.
  *
@@ -537,10 +537,8 @@ static void i2c_clear_regs(int port)
 	STM32_I2C_SR1(port) = 0;
 
 	/* Clear start, stop, POS, ACK bits to get us in a known state */
-	STM32_I2C_CR1(port) &= ~(STM32_I2C_CR1_START |
-				 STM32_I2C_CR1_STOP |
-				 STM32_I2C_CR1_POS |
-				 STM32_I2C_CR1_ACK);
+	STM32_I2C_CR1(port) &= ~(STM32_I2C_CR1_START | STM32_I2C_CR1_STOP |
+				 STM32_I2C_CR1_POS | STM32_I2C_CR1_ACK);
 }
 
 /*****************************************************************************
@@ -548,11 +546,10 @@ static void i2c_clear_regs(int port)
  */
 
 /* Perform an i2c transaction. */
-int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags,
-		  const uint8_t *out, int out_bytes,
-		  uint8_t *in, int in_bytes, int flags)
+int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out,
+		  int out_bytes, uint8_t *in, int in_bytes, int flags)
 {
-	int addr_8bit = I2C_GET_ADDR(slave_addr_flags) << 1;
+	int addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1;
 	int started = (flags & I2C_XFER_START) ? 0 : 1;
 	int rv = EC_SUCCESS;
 	int i;
@@ -563,9 +560,8 @@ int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags,
 	ASSERT(!started);
 
 	if (p->port == STM32F4_FMPI2C_PORT) {
-		return chip_fmpi2c_xfer(port, addr_8bit,
-					out, out_bytes,
-					in, in_bytes, flags);
+		return chip_fmpi2c_xfer(port, addr_8bit, out, out_bytes, in,
+					in_bytes, flags);
 	}
 
 	i2c_clear_regs(port);
@@ -642,7 +638,7 @@ int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags,
 		STM32_I2C_CR2(port) &= ~STM32_I2C_CR2_DMAEN;
 	}
 
- xfer_exit:
+xfer_exit:
 	/* On error, queue a stop condition */
 	if (rv) {
 		flags |= I2C_XFER_STOP;
@@ -656,7 +652,8 @@ int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags,
 			const struct i2c_port_t *p;
 
 			CPRINTS("chip_i2c_xfer start error; "
-				"unwedging and resetting i2c %d", port);
+				"unwedging and resetting i2c %d",
+				port);
 
 			p = find_port(port);
 			i2c_unwedge(port);
@@ -675,7 +672,7 @@ int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags,
 
 		/*
 		 * Allow bus to idle for at least one 100KHz clock = 10 us.
-		 * This allows slaves on the bus to detect bus-idle before
+		 * This allows peripherals on the bus to detect bus-idle before
 		 * the next start condition.
 		 */
 		usleep(10);
@@ -709,13 +706,13 @@ int i2c_raw_get_sda(int port)
 int i2c_get_line_levels(int port)
 {
 	return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) |
-		(i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
+	       (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
 }
 
 /*****************************************************************************/
 /* Hooks */
 
-#ifdef CONFIG_I2C_MASTER
+#ifdef CONFIG_I2C_CONTROLLER
 /* Handle CPU clock changing frequency */
 static void i2c_freq_change(void)
 {
@@ -754,9 +751,9 @@ DECLARE_HOOK(HOOK_FREQ_CHANGE, i2c_freq_change_hook, HOOK_PRIO_DEFAULT);
 #endif
 
 /*****************************************************************************/
-/* Slave */
-#ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS
-/* Host command slave */
+/* Peripheral */
+#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
+/* Host command peripheral */
 /*
  * Buffer for received host command packets (including prefix byte on request,
  * and result/size on response).  After any protocol-specific headers, the
@@ -764,7 +761,7 @@ DECLARE_HOOK(HOOK_FREQ_CHANGE, i2c_freq_change_hook, HOOK_PRIO_DEFAULT);
  */
 static uint8_t host_buffer_padded[I2C_MAX_HOST_PACKET_SIZE + 4 +
 				  CONFIG_I2C_EXTRA_PACKET_SIZE] __aligned(4);
-static uint8_t * const host_buffer = host_buffer_padded + 2;
+static uint8_t *const host_buffer = host_buffer_padded + 2;
 static uint8_t params_copy[I2C_MAX_HOST_PACKET_SIZE] __aligned(4);
 static int host_i2c_resp_port;
 static int tx_pending;
@@ -790,7 +787,7 @@ static void i2c_send_response_packet(struct host_packet *pkt)
 
 	/*
 	 * Set the transmitter to be in 'not full' state to keep sending
-	 * '0xec' in the event loop. Because of this, the master i2c
+	 * '0xec' in the event loop. Because of this, the controller i2c
 	 * doesn't need to snoop the response stream to abort transaction.
 	 */
 	STM32_I2C_CR2(host_i2c_resp_port) |= STM32_I2C_CR2_ITBUFEN;
@@ -834,7 +831,7 @@ static void i2c_process_command(void)
 	host_packet_receive(&i2c_packet);
 }
 
-#ifdef CONFIG_BOARD_I2C_SLAVE_ADDR_FLAGS
+#ifdef CONFIG_BOARD_I2C_ADDR_FLAGS
 static void i2c_send_board_response(int len)
 {
 	/* host_buffer data range, beyond this length, will return 0xec */
@@ -868,7 +865,7 @@ static void i2c_event_handler(int port)
 
 	/*
 	 * Check for error conditions. Note, arbitration loss and bus error
-	 * are the only two errors we can get as a slave allowing clock
+	 * are the only two errors we can get as a peripheral allowing clock
 	 * stretching and in non-SMBus mode.
 	 */
 	if (i2c_sr1 & (STM32_I2C_SR1_ARLO | STM32_I2C_SR1_BERR)) {
@@ -877,25 +874,27 @@ static void i2c_event_handler(int port)
 		/* Disable buffer interrupt */
 		STM32_I2C_CR2(port) &= ~STM32_I2C_CR2_ITBUFEN;
 		/* Clear error status bits */
-		STM32_I2C_SR1(port) &= ~(STM32_I2C_SR1_ARLO |
-					 STM32_I2C_SR1_BERR);
+		STM32_I2C_SR1(port) &=
+			~(STM32_I2C_SR1_ARLO | STM32_I2C_SR1_BERR);
 	}
 
-	/* Transfer matched our slave address */
+	/* Transfer matched our peripheral address */
 	if (i2c_sr1 & STM32_I2C_SR1_ADDR) {
 		addr_8bit = ((i2c_sr2 & STM32_I2C_SR2_DUALF) ?
-			STM32_I2C_OAR2(port) : STM32_I2C_OAR1(port)) & 0xfe;
+				     STM32_I2C_OAR2(port) :
+				     STM32_I2C_OAR1(port)) &
+			    0xfe;
 		if (i2c_sr2 & STM32_I2C_SR2_TRA) {
-			/* Transmitter slave */
+			/* Transmitter peripheral */
 			i2c_sr1 |= STM32_I2C_SR1_TXE;
-#ifdef CONFIG_BOARD_I2C_SLAVE_ADDR_FLAGS
+#ifdef CONFIG_BOARD_I2C_ADDR_FLAGS
 			if (!rx_pending && !tx_pending) {
 				tx_pending = 1;
 				i2c_process_board_command(1, addr_8bit, 0);
 			}
 #endif
 		} else {
-			/* Receiver slave */
+			/* Receiver peripheral */
 			buf_idx = 0;
 			rx_pending = 1;
 		}
@@ -906,10 +905,10 @@ static void i2c_event_handler(int port)
 		unused = STM32_I2C_SR1(port);
 		unused = STM32_I2C_SR2(port);
 		/* Inhibit stop mode when addressed until STOPF flag is set */
-		disable_sleep(SLEEP_MASK_I2C_SLAVE);
+		disable_sleep(SLEEP_MASK_I2C_PERIPHERAL);
 	}
 
-	/* I2C in slave transmitter */
+	/* I2C in peripheral transmitter */
 	if (i2c_sr2 & STM32_I2C_SR2_TRA) {
 		if (i2c_sr1 & (STM32_I2C_SR1_BTF | STM32_I2C_SR1_TXE)) {
 			if (tx_pending) {
@@ -926,10 +925,10 @@ static void i2c_event_handler(int port)
 				host_i2c_resp_port = port;
 				/* Disable buffer interrupt */
 				STM32_I2C_CR2(port) &= ~STM32_I2C_CR2_ITBUFEN;
-#ifdef CONFIG_BOARD_I2C_SLAVE_ADDR_FLAGS
+#ifdef CONFIG_BOARD_I2C_ADDR_FLAGS
 				if ((addr_8bit >> 1) ==
-				    I2C_GET_ADDR(
-					    CONFIG_BOARD_I2C_SLAVE_ADDR_FLAGS))
+				    I2C_STRIP_FLAGS(
+					    CONFIG_BOARD_I2C_ADDR_FLAGS))
 					i2c_process_board_command(1, addr_8bit,
 								  buf_idx);
 				else
@@ -942,7 +941,7 @@ static void i2c_event_handler(int port)
 				STM32_I2C_DR(port) = 0xec;
 			}
 		}
-	} else { /* I2C in slave receiver */
+	} else { /* I2C in peripheral receiver */
 		if (i2c_sr1 & (STM32_I2C_SR1_BTF | STM32_I2C_SR1_RXNE))
 			host_buffer[buf_idx++] = STM32_I2C_DR(port);
 	}
@@ -952,10 +951,10 @@ static void i2c_event_handler(int port)
 		/* Disable buffer interrupt */
 		STM32_I2C_CR2(port) &= ~STM32_I2C_CR2_ITBUFEN;
 
-#ifdef CONFIG_BOARD_I2C_SLAVE_ADDR_FLAGS
+#ifdef CONFIG_BOARD_I2C_ADDR_FLAGS
 		if (rx_pending &&
 		    (addr_8b >> 1) ==
-		    I2C_GET_ADDR(CONFIG_BOARD_I2C_SLAVE_ADDR_FLAGS))
+			    I2C_STRIP_FLAGS(CONFIG_BOARD_I2C_ADDR_FLAGS))
 			i2c_process_board_command(0, addr_8bit, buf_idx);
 #endif
 		rx_pending = 0;
@@ -968,19 +967,21 @@ static void i2c_event_handler(int port)
 		STM32_I2C_CR1(port) = i2c_cr1 | STM32_I2C_CR1_PE;
 
 		/* No longer inhibit deep sleep after stop condition */
-		enable_sleep(SLEEP_MASK_I2C_SLAVE);
+		enable_sleep(SLEEP_MASK_I2C_PERIPHERAL);
 	}
 
 	/* Enable again */
 	if (!(i2c_cr1 & STM32_I2C_CR1_PE))
 		STM32_I2C_CR1(port) |= STM32_I2C_CR1_PE;
 }
-void i2c_event_interrupt(void) { i2c_event_handler(I2C_PORT_EC); }
-DECLARE_IRQ(IRQ_SLAVE_EV, i2c_event_interrupt, 2);
-DECLARE_IRQ(IRQ_SLAVE_ER, i2c_event_interrupt, 2);
+static void i2c_event_interrupt(void)
+{
+	i2c_event_handler(I2C_PORT_EC);
+}
+DECLARE_IRQ(IRQ_PERIPHERAL_EV, i2c_event_interrupt, 2);
+DECLARE_IRQ(IRQ_PERIPHERAL_ER, i2c_event_interrupt, 2);
 #endif
 
-
 /* Init all available i2c ports */
 void i2c_init(void)
 {
@@ -990,21 +991,22 @@ void i2c_init(void)
 	for (i = 0; i < i2c_ports_used; i++, p++)
 		i2c_init_port(p);
 
-
-#ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS
+#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
 	/* Enable ACK */
 	STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_ACK;
 	/* Enable interrupts */
-	STM32_I2C_CR2(I2C_PORT_EC) |= STM32_I2C_CR2_ITEVTEN
-			| STM32_I2C_CR2_ITERREN;
-	/* Setup host command slave */
-	STM32_I2C_OAR1(I2C_PORT_EC) = STM32_I2C_OAR1_B14
-		| (I2C_GET_ADDR(CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS) << 1);
-#ifdef CONFIG_BOARD_I2C_SLAVE_ADDR_FLAGS
-	STM32_I2C_OAR2(I2C_PORT_EC) = STM32_I2C_OAR2_ENDUAL
-		| (I2C_GET_ADDR(CONFIG_BOARD_I2C_SLAVE_ADDR_FLAGS) << 1);
+	STM32_I2C_CR2(I2C_PORT_EC) |= STM32_I2C_CR2_ITEVTEN |
+				      STM32_I2C_CR2_ITERREN;
+	/* Setup host command peripheral */
+	STM32_I2C_OAR1(I2C_PORT_EC) =
+		STM32_I2C_OAR1_B14 |
+		(I2C_STRIP_ADDR(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) << 1);
+#ifdef CONFIG_BOARD_I2C_ADDR_FLAGS
+	STM32_I2C_OAR2(I2C_PORT_EC) =
+		STM32_I2C_OAR2_ENDUAL |
+		(I2C_STRIP_FLAGS(CONFIG_BOARD_I2C_ADDR_FLAGS) << 1);
 #endif
-	task_enable_irq(IRQ_SLAVE_EV);
-	task_enable_irq(IRQ_SLAVE_ER);
+	task_enable_irq(IRQ_PERIPHERAL_EV);
+	task_enable_irq(IRQ_PERIPHERAL_ER);
 #endif
 }
diff --git a/chip/stm32/i2c-stm32g4.c b/chip/stm32/i2c-stm32g4.c
index de6937ab28..66ec8173d8 100644
--- a/chip/stm32/i2c-stm32g4.c
+++ b/chip/stm32/i2c-stm32g4.c
@@ -1,8 +1,9 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "builtin/assert.h"
 #include "chipset.h"
 #include "clock.h"
 #include "common.h"
@@ -20,12 +21,12 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
 
 #define I2C_ERROR_FAILED_START EC_ERROR_INTERNAL_FIRST
 
 /* Transmit timeout in microseconds */
-#define I2C_TX_TIMEOUT_MASTER   (10 * MSEC)
+#define I2C_TX_TIMEOUT_MASTER (10 * MSEC)
 
 enum i2c_freq_khz {
 	freq_100 = 100,
@@ -44,8 +45,8 @@ struct i2c_timing {
 /* timing register values for supported input clks / i2c clk rates */
 static const uint32_t busyloop_us[I2C_FREQ_COUNT] = {
 	[I2C_FREQ_1000KHZ] = 16, /* Enough for 2 bytes */
-	[I2C_FREQ_400KHZ] = 40,  /* Enough for 2 bytes */
-	[I2C_FREQ_100KHZ] = 0,   /* No busy looping at 100kHz (bus is slow) */
+	[I2C_FREQ_400KHZ] = 40, /* Enough for 2 bytes */
+	[I2C_FREQ_100KHZ] = 0, /* No busy looping at 100kHz (bus is slow) */
 };
 
 /*
@@ -94,8 +95,8 @@ static const uint32_t i2c_regs_base[] = {
 
 /* I2C port state data */
 struct i2c_port_data {
-	uint32_t timeout_us;    /* Transaction timeout, or 0 to use default */
-	enum i2c_freq freq;	/* Port clock speed */
+	uint32_t timeout_us; /* Transaction timeout, or 0 to use default */
+	enum i2c_freq freq; /* Port clock speed */
 };
 static struct i2c_port_data pdata[I2C_PORT_COUNT];
 
@@ -145,10 +146,10 @@ static void i2c_set_timingr_port(const struct i2c_port_t *p)
 	}
 	/* Assemble write value for timingr register */
 	timingr = (i2c_timingr[index].scll << STM32_I2C_TIMINGR_SCLL_OFF) |
-		(i2c_timingr[index].sclh << STM32_I2C_TIMINGR_SCLH_OFF) |
-		(i2c_timingr[index].sdadel << STM32_I2C_TIMINGR_SDADEL_OFF) |
-		(i2c_timingr[index].scldel << STM32_I2C_TIMINGR_SCLDEL_OFF) |
-		(i2c_timingr[index].presc << STM32_I2C_TIMINGR_PRESC_OFF);
+		  (i2c_timingr[index].sclh << STM32_I2C_TIMINGR_SCLH_OFF) |
+		  (i2c_timingr[index].sdadel << STM32_I2C_TIMINGR_SDADEL_OFF) |
+		  (i2c_timingr[index].scldel << STM32_I2C_TIMINGR_SCLDEL_OFF) |
+		  (i2c_timingr[index].presc << STM32_I2C_TIMINGR_PRESC_OFF);
 
 	/* Write timingr value */
 	STM32_I2C_TIMINGR(base) = timingr;
@@ -189,8 +190,8 @@ static void i2c_init_port(const struct i2c_port_t *p)
 		mask = STM32_RCC_CCIPR_I2CNSEL_MASK << shift;
 		clksel = STM32_RCC_CCIPR;
 		clksel &= ~mask;
-		STM32_RCC_CCIPR = clksel | (STM32_RCC_CCIPR_I2CNSEL_HSI
-					    << shift);
+		STM32_RCC_CCIPR = clksel |
+				  (STM32_RCC_CCIPR_I2CNSEL_HSI << shift);
 	} else if (port == 3) {
 		/* i2c4sel is bits 1:0, no shift required */
 		STM32_RCC_CCIPR2 &= ~STM32_RCC_CCIPR2_I2C4SEL_MASK;
@@ -260,11 +261,10 @@ static int wait_isr(int port, int mask)
  * Exported functions declared in i2c.h
  */
 /* Perform an i2c transaction. */
-int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags,
-		  const uint8_t *out, int out_bytes,
-		  uint8_t *in, int in_bytes, int flags)
+int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out,
+		  int out_bytes, uint8_t *in, int in_bytes, int flags)
 {
-	int addr_8bit = I2C_GET_ADDR(slave_addr_flags) << 1;
+	int addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1;
 	int rv = EC_SUCCESS;
 	int i;
 	int xfer_start = flags & I2C_XFER_START;
@@ -290,13 +290,13 @@ int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags,
 		 * if we are not stopping, set RELOAD bit so that we can load
 		 * NBYTES again. if we are starting, then set START bit.
 		 */
-		STM32_I2C_CR2(base) = ((out_bytes & 0xFF) << 16)
-			| addr_8bit
-			| ((in_bytes == 0 && xfer_stop) ?
-				STM32_I2C_CR2_AUTOEND : 0)
-			| ((in_bytes == 0 && !xfer_stop) ?
-				STM32_I2C_CR2_RELOAD : 0)
-			| (xfer_start ? STM32_I2C_CR2_START : 0);
+		STM32_I2C_CR2(base) =
+			((out_bytes & 0xFF) << 16) | addr_8bit |
+			((in_bytes == 0 && xfer_stop) ? STM32_I2C_CR2_AUTOEND :
+							0) |
+			((in_bytes == 0 && !xfer_stop) ? STM32_I2C_CR2_RELOAD :
+							 0) |
+			(xfer_start ? STM32_I2C_CR2_START : 0);
 
 		for (i = 0; i < out_bytes; i++) {
 			rv = wait_isr(port, STM32_I2C_ISR_TXIS);
@@ -319,11 +319,11 @@ int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags,
 		 * NBYTES again. if we were just transmitting, we need to
 		 * set START bit to send (re)start and begin read transaction.
 		 */
-		STM32_I2C_CR2(base) = ((in_bytes & 0xFF) << 16)
-			| STM32_I2C_CR2_RD_WRN | addr_8bit
-			| (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0)
-			| (!xfer_stop ? STM32_I2C_CR2_RELOAD : 0)
-			| (out_bytes || xfer_start ? STM32_I2C_CR2_START : 0);
+		STM32_I2C_CR2(base) =
+			((in_bytes & 0xFF) << 16) | STM32_I2C_CR2_RD_WRN |
+			addr_8bit | (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0) |
+			(!xfer_stop ? STM32_I2C_CR2_RELOAD : 0) |
+			(out_bytes || xfer_start ? STM32_I2C_CR2_START : 0);
 
 		for (i = 0; i < in_bytes; i++) {
 			/* Wait for receive buffer not empty */
@@ -402,13 +402,13 @@ int i2c_raw_get_sda(int port)
 int i2c_get_line_levels(int port)
 {
 	return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) |
-		(i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
+	       (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
 }
 
 /*****************************************************************************/
 /* Hooks */
 
-#ifdef CONFIG_I2C_MASTER
+#ifdef CONFIG_I2C_CONTROLLER
 /* Handle an upcoming frequency change. */
 static void i2c_pre_freq_change_hook(void)
 {
diff --git a/chip/stm32/i2c-stm32l.c b/chip/stm32/i2c-stm32l.c
index 80d3434c74..f18374281a 100644
--- a/chip/stm32/i2c-stm32l.c
+++ b/chip/stm32/i2c-stm32l.c
@@ -1,8 +1,9 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "builtin/assert.h"
 #include "chipset.h"
 #include "clock.h"
 #include "common.h"
@@ -19,7 +20,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
 
 #define I2C_ERROR_FAILED_START EC_ERROR_INTERNAL_FIRST
 
@@ -35,23 +36,20 @@
  * flips out.  The battery may flip out and hold lines low for up to
  * 25ms.  If we just wait it will eventually let them go.
  */
-#define I2C_TX_TIMEOUT_MASTER	(30 * MSEC)
+#define I2C_TX_TIMEOUT_MASTER (30 * MSEC)
 
 /*
  * Delay 5us in bitbang mode.  That gives us roughly 5us low and 5us high or
  * a frequency of 100kHz.
  */
-#define I2C_BITBANG_HALF_CYCLE_US    5
+#define I2C_BITBANG_HALF_CYCLE_US 5
 
 #ifdef CONFIG_I2C_DEBUG
 static void dump_i2c_reg(int port, const char *what)
 {
 	CPRINTS("i2c CR1=%04x CR2=%04x SR1=%04x SR2=%04x %s",
-		STM32_I2C_CR1(port),
-		STM32_I2C_CR2(port),
-		STM32_I2C_SR1(port),
-		STM32_I2C_SR2(port),
-		what);
+		STM32_I2C_CR1(port), STM32_I2C_CR2(port), STM32_I2C_SR1(port),
+		STM32_I2C_SR2(port), what);
 }
 #else
 static inline void dump_i2c_reg(int port, const char *what)
@@ -164,12 +162,10 @@ static void i2c_init_port(const struct i2c_port_t *p)
 /*****************************************************************************/
 /* Interface */
 
-int chip_i2c_xfer(const int port,
-		  const uint16_t slave_addr_flags,
-		  const uint8_t *out, int out_bytes,
-		  uint8_t *in, int in_bytes, int flags)
+int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out,
+		  int out_bytes, uint8_t *in, int in_bytes, int flags)
 {
-	int addr_8bit = I2C_GET_ADDR(slave_addr_flags) << 1;
+	int addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1;
 	int started = (flags & I2C_XFER_START) ? 0 : 1;
 	int rv = EC_SUCCESS;
 	int i;
@@ -188,10 +184,8 @@ int chip_i2c_xfer(const int port,
 	STM32_I2C_SR1(port) = 0;
 
 	/* Clear start, stop, POS, ACK bits to get us in a known state */
-	STM32_I2C_CR1(port) &= ~(STM32_I2C_CR1_START |
-				 STM32_I2C_CR1_STOP |
-				 STM32_I2C_CR1_POS |
-				 STM32_I2C_CR1_ACK);
+	STM32_I2C_CR1(port) &= ~(STM32_I2C_CR1_START | STM32_I2C_CR1_STOP |
+				 STM32_I2C_CR1_POS | STM32_I2C_CR1_ACK);
 
 	/* No out bytes and no in bytes means just check for active */
 	if (out_bytes || !in_bytes) {
@@ -291,7 +285,7 @@ int chip_i2c_xfer(const int port,
 		}
 	}
 
- xfer_exit:
+xfer_exit:
 	/* On error, queue a stop condition */
 	if (rv) {
 		flags |= I2C_XFER_STOP;
@@ -305,7 +299,8 @@ int chip_i2c_xfer(const int port,
 		if (rv == I2C_ERROR_FAILED_START) {
 			const struct i2c_port_t *p = i2c_ports;
 			CPRINTS("chip_i2c_xfer start error; "
-				"unwedging and resetting i2c %d", port);
+				"unwedging and resetting i2c %d",
+				port);
 
 			i2c_unwedge(port);
 
@@ -363,7 +358,7 @@ int i2c_raw_get_sda(int port)
 int i2c_get_line_levels(int port)
 {
 	return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) |
-		(i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
+	       (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
 }
 
 /*****************************************************************************/
@@ -414,11 +409,9 @@ void i2c_init(void)
 /*****************************************************************************/
 /* Console commands */
 
-static int command_i2cdump(int argc, char **argv)
+static int command_i2cdump(int argc, const char **argv)
 {
 	dump_i2c_reg(I2C_PORT_MASTER, "dump");
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(i2cdump, command_i2cdump,
-			NULL,
-			"Dump I2C regs");
+DECLARE_CONSOLE_COMMAND(i2cdump, command_i2cdump, NULL, "Dump I2C regs");
diff --git a/chip/stm32/i2c-stm32l4.c b/chip/stm32/i2c-stm32l4.c
index 66bd063499..5d4e51e92e 100644
--- a/chip/stm32/i2c-stm32l4.c
+++ b/chip/stm32/i2c-stm32l4.c
@@ -1,9 +1,11 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include "printf.h"
+/* I2C drivers for STM32L4xx as well as STM32L5xx. */
+
+#include "builtin/assert.h"
 #include "chipset.h"
 #include "clock.h"
 #include "common.h"
@@ -12,8 +14,8 @@
 #include "hooks.h"
 #include "hwtimer.h"
 #include "i2c.h"
+#include "printf.h"
 #include "registers.h"
-
 #include "system.h"
 #include "task.h"
 #include "timer.h"
@@ -21,13 +23,13 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
 
 /* Transmit timeout in microseconds */
-#define I2C_TX_TIMEOUT_MASTER	(10 * MSEC)
+#define I2C_TX_TIMEOUT_MASTER (10 * MSEC)
 
-#ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS
-#define I2C_SLAVE_ERROR_CODE	0xec
+#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
+#define I2C_SLAVE_ERROR_CODE 0xec
 #if (I2C_PORT_EC == STM32_I2C1_PORT)
 #define IRQ_SLAVE STM32_IRQ_I2C1
 #else
@@ -37,8 +39,8 @@
 
 /* I2C port state data */
 struct i2c_port_data {
-	uint32_t timeout_us;    /* Transaction timeout, or 0 to use default */
-	enum i2c_freq freq;	/* Port clock speed */
+	uint32_t timeout_us; /* Transaction timeout, or 0 to use default */
+	enum i2c_freq freq; /* Port clock speed */
 };
 static struct i2c_port_data pdata[I2C_PORT_COUNT];
 
@@ -50,8 +52,8 @@ void i2c_set_timeout(int port, uint32_t timeout)
 /* timing register values for supported input clks / i2c clk rates */
 static const uint32_t busyloop_us[I2C_FREQ_COUNT] = {
 	[I2C_FREQ_1000KHZ] = 16, /* Enough for 2 bytes */
-	[I2C_FREQ_400KHZ] = 40,  /* Enough for 2 bytes */
-	[I2C_FREQ_100KHZ] = 0,   /* No busy looping at 100kHz (bus is slow) */
+	[I2C_FREQ_400KHZ] = 40, /* Enough for 2 bytes */
+	[I2C_FREQ_100KHZ] = 0, /* No busy looping at 100kHz (bus is slow) */
 };
 
 /**
@@ -70,7 +72,7 @@ static int wait_isr(int port, int mask)
 
 		/* Check for errors */
 		if (isr & (STM32_I2C_ISR_ARLO | STM32_I2C_ISR_BERR |
-			STM32_I2C_ISR_NACK))
+			   STM32_I2C_ISR_NACK))
 			return EC_ERROR_UNKNOWN;
 
 		/* Check for desired mask */
@@ -90,9 +92,10 @@ static int wait_isr(int port, int mask)
 	return EC_ERROR_TIMEOUT;
 }
 
-/* We are only using sysclk, which is 40MHZ */
+/* Supported i2c input clocks */
 enum stm32_i2c_clk_src {
-	I2C_CLK_SRC_40MHZ = 0,
+	I2C_CLK_SRC_48MHZ = 0,
+	I2C_CLK_SRC_16MHZ = 1,
 	I2C_CLK_SRC_COUNT,
 };
 
@@ -101,29 +104,38 @@ enum stm32_i2c_clk_src {
  * These values are calculated using ST's STM32cubeMX tool
  */
 static const uint32_t timingr_regs[I2C_CLK_SRC_COUNT][I2C_FREQ_COUNT] = {
-	[I2C_CLK_SRC_40MHZ] = {
-		[I2C_FREQ_1000KHZ] = 0x00100618,
-		[I2C_FREQ_400KHZ] = 0x00301347,
-		[I2C_FREQ_100KHZ] = 0x003087FF,
+	[I2C_CLK_SRC_48MHZ] = {
+		[I2C_FREQ_1000KHZ] = 0x20000209,
+		[I2C_FREQ_400KHZ] = 0x2010091A,
+		[I2C_FREQ_100KHZ] = 0x20303E5D,
+	},
+	[I2C_CLK_SRC_16MHZ] = {
+		[I2C_FREQ_1000KHZ] = 0x00000107,
+		[I2C_FREQ_400KHZ] = 0x00100B15,
+		[I2C_FREQ_100KHZ] = 0x00303D5B,
 	},
 };
 
-static void i2c_set_freq_port(const struct i2c_port_t *p,
-			      enum stm32_i2c_clk_src src,
-			      enum i2c_freq freq)
+int chip_i2c_set_freq(int port, enum i2c_freq freq)
 {
-	int port = p->port;
-	const uint32_t *regs = timingr_regs[src];
+	enum stm32_i2c_clk_src src = I2C_CLK_SRC_16MHZ;
 
 	/* Disable port */
 	STM32_I2C_CR1(port) = 0;
 	STM32_I2C_CR2(port) = 0;
 	/* Set clock frequency */
-	STM32_I2C_TIMINGR(port) = regs[freq];
+	STM32_I2C_TIMINGR(port) = timingr_regs[src][freq];
 	/* Enable port */
 	STM32_I2C_CR1(port) = STM32_I2C_CR1_PE;
 
 	pdata[port].freq = freq;
+
+	return EC_SUCCESS;
+}
+
+enum i2c_freq chip_i2c_get_freq(int port)
+{
+	return pdata[port].freq;
 }
 
 /**
@@ -134,20 +146,30 @@ static void i2c_set_freq_port(const struct i2c_port_t *p,
 static void i2c_init_port(const struct i2c_port_t *p)
 {
 	int port = p->port;
-	uint32_t mask;
-	uint8_t shift;
-	enum stm32_i2c_clk_src src = I2C_CLK_SRC_40MHZ;
+	uint32_t val;
 	enum i2c_freq freq;
 
-	/* Enable clocks to I2C modules if necessary */
-	if (!(STM32_RCC_APB1ENR & (1 << (21 + port))))
-		STM32_RCC_APB1ENR |= 1 << (21 + port);
+	/* Enable I2C clock */
+	if (port == 3) {
+		STM32_RCC_APB1ENR2 |= STM32_RCC_APB1ENR2_I2C4EN;
+	} else {
+		STM32_RCC_APB1ENR1 |= 1 << (21 + port);
+	}
 
-	/* Select sysclk as source */
-	mask = STM32_RCC_CCIPR_I2C1SEL_MASK << (port * 2);
-	shift = STM32_RCC_CCIPR_I2C1SEL_SHIFT + (port * 2);
-	STM32_RCC_CCIPR &= ~mask;
-	STM32_RCC_CCIPR |= STM32_RCC_CCIPR_I2C_SYSCLK << shift;
+	/*	Select HSI 16MHz as I2C clock source	*/
+	if (port == 3) {
+		val = STM32_RCC_CCIPR2;
+		val &= ~STM32_RCC_CCIPR2_I2C4SEL_MSK;
+		val |= STM32_RCC_CCIPR_I2C_HSI16
+		       << STM32_RCC_CCIPR2_I2C4SEL_POS;
+		STM32_RCC_CCIPR2 = val;
+	} else {
+		val = STM32_RCC_CCIPR;
+		val &= ~(STM32_RCC_CCIPR_I2C1SEL_MASK << (port * 2));
+		val |= STM32_RCC_CCIPR_I2C_HSI16
+		       << (STM32_RCC_CCIPR_I2C1SEL_SHIFT + port * 2);
+		STM32_RCC_CCIPR = val;
+	}
 
 	/* Configure GPIOs */
 	gpio_config_module(MODULE_I2C, 1);
@@ -155,6 +177,7 @@ static void i2c_init_port(const struct i2c_port_t *p)
 	/* Set clock frequency */
 	switch (p->kbps) {
 	case 1000:
+		STM32_SYSCFG_CFGR1 |= STM32_SYSCFG_I2CFMP(port);
 		freq = I2C_FREQ_1000KHZ;
 		break;
 	case 400:
@@ -169,7 +192,7 @@ static void i2c_init_port(const struct i2c_port_t *p)
 	}
 
 	/* Set up initial bus frequencies */
-	i2c_set_freq_port(p, src, freq);
+	chip_i2c_set_freq(p->port, freq);
 
 	/* Set up default timeout */
 	i2c_set_timeout(port, 0);
@@ -177,7 +200,7 @@ static void i2c_init_port(const struct i2c_port_t *p)
 
 /*****************************************************************************/
 
-#ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS
+#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
 
 static void i2c_event_handler(int port)
 {
@@ -203,8 +226,8 @@ static void i2c_event_handler(int port)
 		STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE;
 
 		/* Clear error status bits */
-		STM32_I2C_ICR(port) |= STM32_I2C_ICR_BERRCF
-				| STM32_I2C_ICR_ARLOCF;
+		STM32_I2C_ICR(port) |= STM32_I2C_ICR_BERRCF |
+				       STM32_I2C_ICR_ARLOCF;
 	}
 
 	/* Transfer matched our slave address */
@@ -234,7 +257,7 @@ static void i2c_event_handler(int port)
 		/* Clear ADDR bit by writing to ADDRCF bit */
 		STM32_I2C_ICR(port) |= STM32_I2C_ICR_ADDRCF;
 		/* Inhibit stop mode when addressed until STOPF flag is set */
-		disable_sleep(SLEEP_MASK_I2C_SLAVE);
+		disable_sleep(SLEEP_MASK_I2C_PERIPHERAL);
 	}
 
 	/*
@@ -262,7 +285,7 @@ static void i2c_event_handler(int port)
 		STM32_I2C_ICR(port) |= STM32_I2C_ICR_STOPCF;
 
 		/* No longer inhibit deep sleep after stop condition */
-		enable_sleep(SLEEP_MASK_I2C_SLAVE);
+		enable_sleep(SLEEP_MASK_I2C_PERIPHERAL);
 	}
 
 	if (isr & STM32_I2C_ISR_NACK) {
@@ -280,8 +303,8 @@ static void i2c_event_handler(int port)
 					STM32_I2C_TXDR(port) =
 						slave_buffer[tx_idx++];
 				} else {
-					STM32_I2C_TXDR(port)
-						= I2C_SLAVE_ERROR_CODE;
+					STM32_I2C_TXDR(port) =
+						I2C_SLAVE_ERROR_CODE;
 					tx_idx = 0;
 					tx_end = 0;
 					tx_pending = 0;
@@ -293,7 +316,7 @@ static void i2c_event_handler(int port)
 	}
 }
 
-void i2c_event_interrupt(void)
+static void i2c_event_interrupt(void)
 {
 	i2c_event_handler(I2C_PORT_EC);
 }
@@ -303,11 +326,10 @@ DECLARE_IRQ(IRQ_SLAVE, i2c_event_interrupt, 2);
 /*****************************************************************************/
 /* Interface */
 
-int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags,
-		  const uint8_t *out, int out_bytes,
-		  uint8_t *in, int in_bytes, int flags)
+int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out,
+		  int out_bytes, uint8_t *in, int in_bytes, int flags)
 {
-	int addr_8bit = I2C_GET_ADDR(slave_addr_flags) << 1;
+	int addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1;
 	int rv = EC_SUCCESS;
 	int i;
 	int xfer_start = flags & I2C_XFER_START;
@@ -329,13 +351,13 @@ int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags,
 		 * if we are not stopping, set RELOAD bit so that we can load
 		 * NBYTES again. if we are starting, then set START bit.
 		 */
-		STM32_I2C_CR2(port) =  ((out_bytes & 0xFF) << 16)
-			| addr_8bit
-			| ((in_bytes == 0 && xfer_stop) ?
-				STM32_I2C_CR2_AUTOEND : 0)
-			| ((in_bytes == 0 && !xfer_stop) ?
-				STM32_I2C_CR2_RELOAD : 0)
-			| (xfer_start ? STM32_I2C_CR2_START : 0);
+		STM32_I2C_CR2(port) =
+			((out_bytes & 0xFF) << 16) | addr_8bit |
+			((in_bytes == 0 && xfer_stop) ? STM32_I2C_CR2_AUTOEND :
+							0) |
+			((in_bytes == 0 && !xfer_stop) ? STM32_I2C_CR2_RELOAD :
+							 0) |
+			(xfer_start ? STM32_I2C_CR2_START : 0);
 
 		for (i = 0; i < out_bytes; i++) {
 			rv = wait_isr(port, STM32_I2C_ISR_TXIS);
@@ -358,11 +380,11 @@ int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags,
 		 * NBYTES again. if we were just transmitting, we need to
 		 * set START bit to send (re)start and begin read transaction.
 		 */
-		STM32_I2C_CR2(port) = ((in_bytes & 0xFF) << 16)
-			| STM32_I2C_CR2_RD_WRN | addr_8bit
-			| (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0)
-			| (!xfer_stop ? STM32_I2C_CR2_RELOAD : 0)
-			| (out_bytes || xfer_start ? STM32_I2C_CR2_START : 0);
+		STM32_I2C_CR2(port) =
+			((in_bytes & 0xFF) << 16) | STM32_I2C_CR2_RD_WRN |
+			addr_8bit | (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0) |
+			(!xfer_stop ? STM32_I2C_CR2_RELOAD : 0) |
+			(out_bytes || xfer_start ? STM32_I2C_CR2_START : 0);
 
 		for (i = 0; i < in_bytes; i++) {
 			/* Wait for receive buffer not empty */
@@ -442,7 +464,7 @@ int i2c_raw_get_sda(int port)
 int i2c_get_line_levels(int port)
 {
 	return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) |
-		(i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
+	       (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
 }
 
 void i2c_init(void)
@@ -453,12 +475,13 @@ void i2c_init(void)
 	for (i = 0; i < i2c_ports_used; i++, p++)
 		i2c_init_port(p);
 
-#ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS
-	STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_RXIE | STM32_I2C_CR1_ERRIE
-			| STM32_I2C_CR1_ADDRIE | STM32_I2C_CR1_STOPIE
-			| STM32_I2C_CR1_NACKIE;
-	STM32_I2C_OAR1(I2C_PORT_EC) = 0x8000
-		| (I2C_GET_ADDR(CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS) << 1);
+#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
+	STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_RXIE | STM32_I2C_CR1_ERRIE |
+				      STM32_I2C_CR1_ADDRIE |
+				      STM32_I2C_CR1_STOPIE |
+				      STM32_I2C_CR1_NACKIE;
+	STM32_I2C_OAR1(I2C_PORT_EC) =
+		0x8000 | (I2C_STRIP_FLAGS(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) << 1);
 	task_enable_irq(IRQ_SLAVE);
 #endif
 }
diff --git a/chip/stm32/i2c-stm32l5.c b/chip/stm32/i2c-stm32l5.c
new file mode 100644
index 0000000000..3c7cb170bc
--- /dev/null
+++ b/chip/stm32/i2c-stm32l5.c
@@ -0,0 +1,6 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "i2c-stm32l4.c"
diff --git a/chip/stm32/i2c_ite_flash_support.c b/chip/stm32/i2c_ite_flash_support.c
index eca3c999af..335064572b 100644
--- a/chip/stm32/i2c_ite_flash_support.c
+++ b/chip/stm32/i2c_ite_flash_support.c
@@ -1,11 +1,11 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 /* STM implementation for flashing ITE-based ECs over i2c */
 
-#include "i2c_ite_flash_support.h"
 #include "i2c.h"
+#include "i2c_ite_flash_support.h"
 #include "registers.h"
 #include "time.h"
 
@@ -33,20 +33,20 @@
  * (1<<9)-6 reads, leaving 6012 bytes of RAM available, down from 7356 bytes of
  * RAM available with the default 60 byte limits.
  */
-#if CONFIG_USB_I2C_MAX_WRITE_COUNT != ((1<<9) - 4)
+#if CONFIG_USB_I2C_MAX_WRITE_COUNT != ((1 << 9) - 4)
 #error Must set CONFIG_USB_I2C_MAX_WRITE_COUNT to ((1<<9) - 4)
 #endif
-#if CONFIG_USB_I2C_MAX_READ_COUNT != ((1<<9) - 6)
+#if CONFIG_USB_I2C_MAX_READ_COUNT != ((1 << 9) - 6)
 #error Must set CONFIG_USB_I2C_MAX_WRITE_COUNT to ((1<<9) - 6)
 #endif
 
 /*
  * iteflash requires 256 byte reads for verifying ITE EC firmware.  Without this
- * the limit is CONFIG_I2C_CHIP_MAX_READ_SIZE which is 255 for STM32F0 due to an
- * 8 bit field, per src/platform/ec/include/config.h comment.
+ * the limit is CONFIG_I2C_CHIP_MAX_TRANSFER_SIZE which is 255 for STM32F0 due
+ * to an 8 bit field, per src/platform/ec/include/config.h comment.
  */
-#ifndef CONFIG_I2C_XFER_LARGE_READ
-#error Must define CONFIG_I2C_XFER_LARGE_READ
+#ifndef CONFIG_I2C_XFER_LARGE_TRANSFER
+#error Must define CONFIG_I2C_XFER_LARGE_TRANSFER
 #endif
 
 #define KHz 1000
@@ -97,16 +97,15 @@ static int ite_i2c_read_register(uint8_t register_offset, uint8_t *output)
 	int ret;
 	/* Tell the ITE EC which register we want to read. */
 	ret = i2c_xfer_unlocked(ite_dfu_config.i2c_port,
-				ITE_DFU_I2C_CMD_ADDR_FLAGS,
-				&register_offset, sizeof(register_offset),
-				NULL, 0, I2C_XFER_SINGLE);
+				ITE_DFU_I2C_CMD_ADDR_FLAGS, &register_offset,
+				sizeof(register_offset), NULL, 0,
+				I2C_XFER_SINGLE);
 	if (ret != EC_SUCCESS)
 		return ret;
 	/* Read in the 1 byte register value. */
 	ret = i2c_xfer_unlocked(ite_dfu_config.i2c_port,
-				ITE_DFU_I2C_DATA_ADDR_FLAGS,
-				NULL, 0,
-				output, sizeof(*output), I2C_XFER_SINGLE);
+				ITE_DFU_I2C_DATA_ADDR_FLAGS, NULL, 0, output,
+				sizeof(*output), I2C_XFER_SINGLE);
 	return ret;
 }
 
@@ -212,7 +211,7 @@ static int cprint_ite_chip_id(void)
 	}
 
 	ccprintf("ITE EC info: CHIPID1=0x%02X CHIPID2=0x%02X CHIPVER=0x%02X ",
-		chipid1[0], chipid2[0], chipver[0]);
+		 chipid1[0], chipid2[0], chipver[0]);
 	ccprintf("version=%d flash_bytes=%d\n", chip_version, flash_kb << 10);
 
 	/*
@@ -226,7 +225,7 @@ static int cprint_ite_chip_id(void)
 }
 
 /* Enable ITE direct firmware update (DFU) mode. */
-static int command_enable_ite_dfu(int argc, char **argv)
+static int command_enable_ite_dfu(int argc, const char **argv)
 {
 	if (argc > 1)
 		return EC_ERROR_PARAM_COUNT;
@@ -236,8 +235,8 @@ static int command_enable_ite_dfu(int argc, char **argv)
 		return EC_ERROR_ACCESS_DENIED;
 
 	/* Enable peripheral clocks. */
-	STM32_RCC_APB2ENR |=
-		STM32_RCC_APB2ENR_TIM16EN | STM32_RCC_APB2ENR_TIM17EN;
+	STM32_RCC_APB2ENR |= STM32_RCC_APB2ENR_TIM16EN |
+			     STM32_RCC_APB2ENR_TIM17EN;
 
 	/* Reset timer registers which are not otherwise set below. */
 	STM32_TIM_CR2(16) = 0x0000;
@@ -265,10 +264,10 @@ static int command_enable_ite_dfu(int argc, char **argv)
 	STM32_TIM_ARR(17) = (MHz / SMDAT_WAVEFORM_PERIOD_HZ) - 1;
 
 	/* Set output compare 1 mode to PWM mode 1 and enable preload. */
-	STM32_TIM_CCMR1(16) =
-		STM32_TIM_CCMR1_OC1M_PWM_MODE_1 | STM32_TIM_CCMR1_OC1PE;
-	STM32_TIM_CCMR1(17) =
-		STM32_TIM_CCMR1_OC1M_PWM_MODE_1 | STM32_TIM_CCMR1_OC1PE;
+	STM32_TIM_CCMR1(16) = STM32_TIM_CCMR1_OC1M_PWM_MODE_1 |
+			      STM32_TIM_CCMR1_OC1PE;
+	STM32_TIM_CCMR1(17) = STM32_TIM_CCMR1_OC1M_PWM_MODE_1 |
+			      STM32_TIM_CCMR1_OC1PE;
 
 	/*
 	 * Enable output compare 1 (or its N counterpart). Note that if only
@@ -335,12 +334,11 @@ static int command_enable_ite_dfu(int argc, char **argv)
 
 	return cprint_ite_chip_id();
 }
-DECLARE_CONSOLE_COMMAND(
-	enable_ite_dfu, command_enable_ite_dfu, "",
-	"Enable ITE Direct Firmware Update (DFU) mode");
+DECLARE_CONSOLE_COMMAND(enable_ite_dfu, command_enable_ite_dfu, "",
+			"Enable ITE Direct Firmware Update (DFU) mode");
 
 /* Read ITE chip ID.  Can be used to verify ITE DFU mode. */
-static int command_get_ite_chipid(int argc, char **argv)
+static int command_get_ite_chipid(int argc, const char **argv)
 {
 	if (argc > 1)
 		return EC_ERROR_PARAM_COUNT;
diff --git a/chip/stm32/keyboard_raw.c b/chip/stm32/keyboard_raw.c
index 219676968a..c3244c19f7 100644
--- a/chip/stm32/keyboard_raw.c
+++ b/chip/stm32/keyboard_raw.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -86,12 +86,12 @@ test_mockable void keyboard_raw_drive_column(int out)
 			}
 		}
 
-	#ifdef CONFIG_KEYBOARD_COL2_INVERTED
+#ifdef CONFIG_KEYBOARD_COL2_INVERTED
 		if (bsrr & (gpio_list[GPIO_KB_OUT02].mask << 16 |
-				 gpio_list[GPIO_KB_OUT02].mask))
+			    gpio_list[GPIO_KB_OUT02].mask))
 			bsrr ^= (gpio_list[GPIO_KB_OUT02].mask << 16 |
 				 gpio_list[GPIO_KB_OUT02].mask);
-	#endif
+#endif
 
 		if (bsrr)
 			STM32_GPIO_BSRR(kb_out_ports[i]) = bsrr;
@@ -131,9 +131,9 @@ void keyboard_raw_enable_interrupt(int enable)
 		 * Clear them before enable interrupt.
 		 */
 		STM32_EXTI_PR |= irq_mask;
-		STM32_EXTI_IMR |= irq_mask;	/* 1: unmask interrupt */
+		STM32_EXTI_IMR |= irq_mask; /* 1: unmask interrupt */
 	} else {
-		STM32_EXTI_IMR &= ~irq_mask;	/* 0: mask interrupts */
+		STM32_EXTI_IMR &= ~irq_mask; /* 0: mask interrupts */
 	}
 }
 
diff --git a/chip/stm32/memory_regions.inc b/chip/stm32/memory_regions.inc
index 2381c511f2..8c8e666f71 100644
--- a/chip/stm32/memory_regions.inc
+++ b/chip/stm32/memory_regions.inc
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/stm32/otp-stm32f4.c b/chip/stm32/otp-stm32f4.c
index a993af7042..ff6280ed20 100644
--- a/chip/stm32/otp-stm32f4.c
+++ b/chip/stm32/otp-stm32f4.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,8 +18,7 @@
 #ifdef CONFIG_SERIALNO_LEN
 /* Which block to use */
 #define OTP_SERIAL_BLOCK 0
-#define OTP_SERIAL_ADDR \
-	REG32_ADDR(STM32_OTP_BLOCK_DATA(OTP_SERIAL_BLOCK, 0))
+#define OTP_SERIAL_ADDR REG32_ADDR(STM32_OTP_BLOCK_DATA(OTP_SERIAL_BLOCK, 0))
 
 /* Number of word used in the block */
 #define OTP_SERIAL_BLOCK_SIZE (CONFIG_SERIALNO_LEN / sizeof(uint32_t))
@@ -39,9 +38,9 @@ static int otp_write(uint8_t block, int size, const char *data)
 		return EC_ERROR_PARAM1;
 	if (size >= STM32_OTP_BLOCK_SIZE)
 		return EC_ERROR_PARAM2;
-	return flash_physical_write(STM32_OTP_BLOCK_DATA(block, 0) -
-				    CONFIG_PROGRAM_MEMORY_BASE,
-				    size * sizeof(uint32_t), data);
+	return crec_flash_physical_write(STM32_OTP_BLOCK_DATA(block, 0) -
+						 CONFIG_PROGRAM_MEMORY_BASE,
+					 size * sizeof(uint32_t), data);
 }
 
 /*
@@ -73,9 +72,9 @@ static int otp_set_protect(uint8_t block)
 
 	lock = REG32(STM32_OTP_LOCK(block));
 	lock &= ~STM32_OPT_LOCK_MASK(block);
-	rv = flash_physical_write(STM32_OTP_LOCK(block) -
-				  CONFIG_PROGRAM_MEMORY_BASE,
-				  sizeof(uint32_t), (char *)&lock);
+	rv = crec_flash_physical_write(STM32_OTP_LOCK(block) -
+					       CONFIG_PROGRAM_MEMORY_BASE,
+				       sizeof(uint32_t), (char *)&lock);
 	if (rv)
 		return rv;
 	else
diff --git a/chip/stm32/power_led.c b/chip/stm32/power_led.c
index 508745199f..579925fff9 100644
--- a/chip/stm32/power_led.c
+++ b/chip/stm32/power_led.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,6 +15,7 @@
  * results in a breathing effect. It takes about 2sec for a full cycle.
  */
 
+#include "builtin/assert.h"
 #include "clock.h"
 #include "console.h"
 #include "gpio.h"
@@ -28,9 +29,9 @@
 #include "timer.h"
 #include "util.h"
 
-#define LED_STATE_TIMEOUT_MIN	(15 * MSEC)  /* Minimum of 15ms per step */
-#define LED_HOLD_TIME		(330 * MSEC) /* Hold for 330ms at min/max */
-#define LED_STEP_PERCENT	4	/* Incremental value of each step */
+#define LED_STATE_TIMEOUT_MIN (15 * MSEC) /* Minimum of 15ms per step */
+#define LED_HOLD_TIME (330 * MSEC) /* Hold for 330ms at min/max */
+#define LED_STEP_PERCENT 4 /* Incremental value of each step */
 
 static enum powerled_state led_state = POWERLED_STATE_ON;
 static int power_led_percent = 100;
@@ -86,7 +87,8 @@ static int power_led_step(void)
 		 * Decreases timeout as duty cycle percentage approaches
 		 * 0%, increase as it approaches 100%.
 		 */
-		state_timeout = LED_STATE_TIMEOUT_MIN +
+		state_timeout =
+			LED_STATE_TIMEOUT_MIN +
 			LED_STATE_TIMEOUT_MIN * (power_led_percent / 33);
 	}
 
@@ -137,7 +139,7 @@ void power_led_task(void)
 
 #define CONFIG_CMD_POWERLED
 #ifdef CONFIG_CMD_POWERLED
-static int command_powerled(int argc, char **argv)
+static int command_powerled(int argc, const char **argv)
 {
 	enum powerled_state state;
 
@@ -156,7 +158,6 @@ static int command_powerled(int argc, char **argv)
 	powerled_set_state(state);
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(powerled, command_powerled,
-		"[off | on | suspend]",
-		"Change power LED state");
+DECLARE_CONSOLE_COMMAND(powerled, command_powerled, "[off | on | suspend]",
+			"Change power LED state");
 #endif
diff --git a/chip/stm32/pwm.c b/chip/stm32/pwm.c
index ce9c4ae04b..bf32793c64 100644
--- a/chip/stm32/pwm.c
+++ b/chip/stm32/pwm.c
@@ -1,12 +1,13 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* PWM control module for STM32 */
 
-#include "clock.h"
+#include "builtin/assert.h"
 #include "clock-f.h"
+#include "clock.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "hwtimer.h"
@@ -17,7 +18,7 @@
 #include "util.h"
 
 /* Bitmap of currently active PWM channels. 1 bit per channel. */
-static uint32_t using_pwm;
+static atomic_t using_pwm;
 
 void pwm_set_duty(enum pwm_channel ch, int percent)
 {
@@ -39,7 +40,7 @@ static void pwm_configure(enum pwm_channel ch)
 {
 	const struct pwm_t *pwm = pwm_channels + ch;
 	timer_ctlr_t *tim = (timer_ctlr_t *)(pwm->tim.base);
-	volatile unsigned *ccmr = NULL;
+	volatile unsigned int *ccmr = NULL;
 	/* Default frequency = 100 Hz */
 	int frequency = pwm->frequency ? pwm->frequency : 100;
 	uint16_t ccer;
@@ -99,7 +100,7 @@ static void pwm_configure(enum pwm_channel ch)
 	/* Enable auto-reload preload, start counting */
 	tim->cr1 |= BIT(7) | BIT(0);
 
-	deprecated_atomic_or(&using_pwm, 1 << ch);
+	atomic_or(&using_pwm, 1 << ch);
 
 	/* Prevent sleep */
 	disable_sleep(SLEEP_MASK_PWM);
@@ -125,7 +126,7 @@ static void pwm_disable(enum pwm_channel ch)
 	/* Allow sleep */
 	enable_sleep(SLEEP_MASK_PWM);
 
-	deprecated_atomic_clear_bits(&using_pwm, 1 << ch);
+	atomic_clear_bits(&using_pwm, 1 << ch);
 
 	/* Unless another PWM is active... Then prevent sleep */
 	if (using_pwm)
@@ -147,7 +148,7 @@ int pwm_get_enabled(enum pwm_channel ch)
 
 static void pwm_reconfigure(enum pwm_channel ch)
 {
-	deprecated_atomic_clear_bits(&using_pwm, 1 << ch);
+	atomic_clear_bits(&using_pwm, 1 << ch);
 	pwm_configure(ch);
 }
 
diff --git a/chip/stm32/pwm_chip.h b/chip/stm32/pwm_chip.h
index baa793090a..7269072ac2 100644
--- a/chip/stm32/pwm_chip.h
+++ b/chip/stm32/pwm_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -29,7 +29,10 @@ struct pwm_t {
 extern const struct pwm_t pwm_channels[];
 
 /* Macro to fill in both timer ID and register base */
-#define STM32_TIM(x) {x, STM32_TIM_BASE(x)}
+#define STM32_TIM(x)                 \
+	{                            \
+		x, STM32_TIM_BASE(x) \
+	}
 
 /* Plain ID mapping for readability */
 #define STM32_TIM_CH(x) (x)
diff --git a/chip/stm32/registers-stm32f0.h b/chip/stm32/registers-stm32f0.h
index 442edaed9a..6d1907e48a 100644
--- a/chip/stm32/registers-stm32f0.h
+++ b/chip/stm32/registers-stm32f0.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,407 +23,402 @@
 #endif
 
 /* --- IRQ numbers --- */
-#define STM32_IRQ_WWDG             0
-#define STM32_IRQ_PVD              1
-#define STM32_IRQ_RTC_WAKEUP       2
-#define STM32_IRQ_RTC_ALARM        2
-#define STM32_IRQ_FLASH            3
-#define STM32_IRQ_RCC              4
-#define STM32_IRQ_EXTI0_1          5
-#define STM32_IRQ_EXTI2_3          6
-#define STM32_IRQ_EXTI4_15         7
-#define STM32_IRQ_TSC              8
-#define STM32_IRQ_DMA_CHANNEL_1    9
+#define STM32_IRQ_WWDG 0
+#define STM32_IRQ_PVD 1
+#define STM32_IRQ_RTC_WAKEUP 2
+#define STM32_IRQ_RTC_ALARM 2
+#define STM32_IRQ_FLASH 3
+#define STM32_IRQ_RCC 4
+#define STM32_IRQ_EXTI0_1 5
+#define STM32_IRQ_EXTI2_3 6
+#define STM32_IRQ_EXTI4_15 7
+#define STM32_IRQ_TSC 8
+#define STM32_IRQ_DMA_CHANNEL_1 9
 #define STM32_IRQ_DMA_CHANNEL_2_3 10
 #define STM32_IRQ_DMA_CHANNEL_4_7 11
-#define STM32_IRQ_ADC_COMP        12
+#define STM32_IRQ_ADC_COMP 12
 #define STM32_IRQ_TIM1_BRK_UP_TRG 13
-#define STM32_IRQ_TIM1_CC         14
-#define STM32_IRQ_TIM2            15
-#define STM32_IRQ_TIM3            16
-#define STM32_IRQ_TIM6_DAC        17
-#define STM32_IRQ_TIM7            18
-#define STM32_IRQ_TIM14           19
-#define STM32_IRQ_TIM15           20
-#define STM32_IRQ_TIM16           21
-#define STM32_IRQ_TIM17           22
-#define STM32_IRQ_I2C1            23
-#define STM32_IRQ_I2C2            24
-#define STM32_IRQ_SPI1            25
-#define STM32_IRQ_SPI2            26
-#define STM32_IRQ_USART1          27
-#define STM32_IRQ_USART2          28
-#define STM32_IRQ_USART3_4        29
-#define STM32_IRQ_CEC_CAN         30
-#define STM32_IRQ_USB             31
+#define STM32_IRQ_TIM1_CC 14
+#define STM32_IRQ_TIM2 15
+#define STM32_IRQ_TIM3 16
+#define STM32_IRQ_TIM6_DAC 17
+#define STM32_IRQ_TIM7 18
+#define STM32_IRQ_TIM14 19
+#define STM32_IRQ_TIM15 20
+#define STM32_IRQ_TIM16 21
+#define STM32_IRQ_TIM17 22
+#define STM32_IRQ_I2C1 23
+#define STM32_IRQ_I2C2 24
+#define STM32_IRQ_SPI1 25
+#define STM32_IRQ_SPI2 26
+#define STM32_IRQ_USART1 27
+#define STM32_IRQ_USART2 28
+#define STM32_IRQ_USART3_4 29
+#define STM32_IRQ_CEC_CAN 30
+#define STM32_IRQ_USB 31
 /* aliases for easier code sharing */
 #define STM32_IRQ_COMP STM32_IRQ_ADC_COMP
 #define STM32_IRQ_USB_LP STM32_IRQ_USB
 
-
-
 /* Peripheral base addresses */
-#define STM32_ADC1_BASE             0x40012400
-#define STM32_ADC_BASE              0x40012700 /* STM32L15X only */
+#define STM32_ADC1_BASE 0x40012400
+#define STM32_ADC_BASE 0x40012700 /* STM32L15X only */
 
-#define STM32_CEC_BASE              0x40007800 /* STM32F373 */
-#define STM32_CRC_BASE              0x40023000
-#define STM32_CRS_BASE              0x40006c00 /* STM32F0XX */
-#define STM32_DAC_BASE              0x40007400
+#define STM32_CEC_BASE 0x40007800 /* STM32F373 */
+#define STM32_CRC_BASE 0x40023000
+#define STM32_CRS_BASE 0x40006c00 /* STM32F0XX */
+#define STM32_DAC_BASE 0x40007400
 
-#define STM32_COMP_BASE             0x40010000
+#define STM32_COMP_BASE 0x40010000
 
-#define STM32_DBGMCU_BASE           0x40015800
+#define STM32_DBGMCU_BASE 0x40015800
 
-#define STM32_DMA1_BASE             0x40020000
-#define STM32_DMA2_BASE             0x40020400
+#define STM32_DMA1_BASE 0x40020000
+#define STM32_DMA2_BASE 0x40020400
 
-#define STM32_EXTI_BASE             0x40010400
+#define STM32_EXTI_BASE 0x40010400
 
-#define STM32_FLASH_REGS_BASE       0x40022000
+#define STM32_FLASH_REGS_BASE 0x40022000
 
-#define STM32_GPIOA_BASE            0x48000000
-#define STM32_GPIOB_BASE            0x48000400
-#define STM32_GPIOC_BASE            0x48000800
-#define STM32_GPIOD_BASE            0x48000C00
-#define STM32_GPIOE_BASE            0x48001000
-#define STM32_GPIOF_BASE            0x48001400
-#define STM32_GPIOG_BASE            0x48001800 /* only for stm32l4x6 */
-#define STM32_GPIOH_BASE            0x48001C00 /* only for stm32l4 */
+#define STM32_GPIOA_BASE 0x48000000
+#define STM32_GPIOB_BASE 0x48000400
+#define STM32_GPIOC_BASE 0x48000800
+#define STM32_GPIOD_BASE 0x48000C00
+#define STM32_GPIOE_BASE 0x48001000
+#define STM32_GPIOF_BASE 0x48001400
+#define STM32_GPIOG_BASE 0x48001800 /* only for stm32l4x6 */
+#define STM32_GPIOH_BASE 0x48001C00 /* only for stm32l4 */
 
-#define STM32_I2C1_BASE             0x40005400
-#define STM32_I2C2_BASE             0x40005800
-#define STM32_I2C3_BASE             0x40005C00
-#define STM32_I2C4_BASE             0x40006000
+#define STM32_I2C1_BASE 0x40005400
+#define STM32_I2C2_BASE 0x40005800
+#define STM32_I2C3_BASE 0x40005C00
+#define STM32_I2C4_BASE 0x40006000
 
-#define STM32_IWDG_BASE             0x40003000
-#define STM32_LCD_BASE              0x40002400
+#define STM32_IWDG_BASE 0x40003000
+#define STM32_LCD_BASE 0x40002400
 
-#define STM32_OPTB_BASE             0x1FFFF800
+#define STM32_OPTB_BASE 0x1FFFF800
 
-#define STM32_PMSE_BASE             0x40013400
-#define STM32_PWR_BASE              0x40007000
+#define STM32_PMSE_BASE 0x40013400
+#define STM32_PWR_BASE 0x40007000
 
-#define STM32_RCC_BASE              0x40021000
+#define STM32_RCC_BASE 0x40021000
 
-#define STM32_RI_BASE               0x40007C00 /* STM32L1xx only */
-#define STM32_RNG_BASE              0x50060800 /* STM32L4 */
-#define STM32_RTC_BASE              0x40002800
+#define STM32_RI_BASE 0x40007C00 /* STM32L1xx only */
+#define STM32_RNG_BASE 0x50060800 /* STM32L4 */
+#define STM32_RTC_BASE 0x40002800
 
-#define STM32_SPI1_BASE             0x40013000
-#define STM32_SPI2_BASE             0x40003800
-#define STM32_SPI3_BASE             0x40003c00 /* STM32F373, STM32L4, STM32F7 */
+#define STM32_SPI1_BASE 0x40013000
+#define STM32_SPI2_BASE 0x40003800
+#define STM32_SPI3_BASE 0x40003c00 /* STM32F373, STM32L4, STM32F7 */
 
-#define STM32_SYSCFG_BASE           0x40010000
+#define STM32_SYSCFG_BASE 0x40010000
 
-#define STM32_TIM1_BASE             0x40012c00 /* STM32F373 */
-#define STM32_TIM2_BASE             0x40000000
-#define STM32_TIM3_BASE             0x40000400
-#define STM32_TIM4_BASE             0x40000800
-#define STM32_TIM5_BASE             0x40000c00 /* STM32F373 */
-#define STM32_TIM6_BASE             0x40001000
-#define STM32_TIM7_BASE             0x40001400
-#define STM32_TIM12_BASE            0x40001800 /* STM32F373 */
-#define STM32_TIM13_BASE            0x40001c00 /* STM32F373 */
-#define STM32_TIM14_BASE            0x40002000 /* STM32F373 */
-#define STM32_TIM15_BASE            0x40014000
-#define STM32_TIM16_BASE            0x40014400
-#define STM32_TIM17_BASE            0x40014800
-#define STM32_TIM18_BASE            0x40009c00 /* STM32F373 only */
-#define STM32_TIM19_BASE            0x40015c00 /* STM32F373 only */
+#define STM32_TIM1_BASE 0x40012c00 /* STM32F373 */
+#define STM32_TIM2_BASE 0x40000000
+#define STM32_TIM3_BASE 0x40000400
+#define STM32_TIM4_BASE 0x40000800
+#define STM32_TIM5_BASE 0x40000c00 /* STM32F373 */
+#define STM32_TIM6_BASE 0x40001000
+#define STM32_TIM7_BASE 0x40001400
+#define STM32_TIM12_BASE 0x40001800 /* STM32F373 */
+#define STM32_TIM13_BASE 0x40001c00 /* STM32F373 */
+#define STM32_TIM14_BASE 0x40002000 /* STM32F373 */
+#define STM32_TIM15_BASE 0x40014000
+#define STM32_TIM16_BASE 0x40014400
+#define STM32_TIM17_BASE 0x40014800
+#define STM32_TIM18_BASE 0x40009c00 /* STM32F373 only */
+#define STM32_TIM19_BASE 0x40015c00 /* STM32F373 only */
 
-#define STM32_UNIQUE_ID_BASE        0x1ffff7ac
+#define STM32_UNIQUE_ID_BASE 0x1ffff7ac
 
-#define STM32_USART1_BASE           0x40013800
-#define STM32_USART2_BASE           0x40004400
-#define STM32_USART3_BASE           0x40004800
-#define STM32_USART4_BASE           0x40004c00
-#define STM32_USART9_BASE           0x40008000 /* LPUART */
+#define STM32_USART1_BASE 0x40013800
+#define STM32_USART2_BASE 0x40004400
+#define STM32_USART3_BASE 0x40004800
+#define STM32_USART4_BASE 0x40004c00
+#define STM32_USART9_BASE 0x40008000 /* LPUART */
 
-#define STM32_USB_CAN_SRAM_BASE     0x40006000
-#define STM32_USB_FS_BASE           0x40005C00
-
-#define STM32_WWDG_BASE             0x40002C00
+#define STM32_USB_CAN_SRAM_BASE 0x40006000
+#define STM32_USB_FS_BASE 0x40005C00
 
+#define STM32_WWDG_BASE 0x40002C00
 
 #ifndef __ASSEMBLER__
 
 /* Register definitions */
 
 /* --- USART --- */
-#define STM32_USART_CR1(base)      STM32_USART_REG(base, 0x00)
-#define STM32_USART_CR1_UE		BIT(0)
-#define STM32_USART_CR1_UESM            BIT(1)
-#define STM32_USART_CR1_RE		BIT(2)
-#define STM32_USART_CR1_TE		BIT(3)
-#define STM32_USART_CR1_RXNEIE		BIT(5)
-#define STM32_USART_CR1_TCIE		BIT(6)
-#define STM32_USART_CR1_TXEIE		BIT(7)
-#define STM32_USART_CR1_PS		BIT(9)
-#define STM32_USART_CR1_PCE		BIT(10)
-#define STM32_USART_CR1_M		BIT(12)
-#define STM32_USART_CR1_OVER8		BIT(15)
-#define STM32_USART_CR2(base)      STM32_USART_REG(base, 0x04)
-#define STM32_USART_CR2_SWAP		BIT(15)
-#define STM32_USART_CR3(base)      STM32_USART_REG(base, 0x08)
-#define STM32_USART_CR3_EIE		BIT(0)
-#define STM32_USART_CR3_DMAR		BIT(6)
-#define STM32_USART_CR3_DMAT		BIT(7)
-#define STM32_USART_CR3_ONEBIT		BIT(11)
-#define STM32_USART_CR3_OVRDIS		BIT(12)
-#define STM32_USART_CR3_WUS_START_BIT	(2 << 20)
-#define STM32_USART_CR3_WUFIE		BIT(22)
-#define STM32_USART_BRR(base)      STM32_USART_REG(base, 0x0C)
-#define STM32_USART_GTPR(base)     STM32_USART_REG(base, 0x10)
-#define STM32_USART_RTOR(base)     STM32_USART_REG(base, 0x14)
-#define STM32_USART_RQR(base)      STM32_USART_REG(base, 0x18)
-#define STM32_USART_ISR(base)      STM32_USART_REG(base, 0x1C)
-#define STM32_USART_ICR(base)      STM32_USART_REG(base, 0x20)
-#define STM32_USART_ICR_ORECF		BIT(3)
-#define STM32_USART_ICR_TCCF		BIT(6)
-#define STM32_USART_RDR(base)      STM32_USART_REG(base, 0x24)
-#define STM32_USART_TDR(base)      STM32_USART_REG(base, 0x28)
-#define STM32_USART_PRESC(base)    STM32_USART_REG(base, 0x2C)
+#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00)
+#define STM32_USART_CR1_UE BIT(0)
+#define STM32_USART_CR1_UESM BIT(1)
+#define STM32_USART_CR1_RE BIT(2)
+#define STM32_USART_CR1_TE BIT(3)
+#define STM32_USART_CR1_RXNEIE BIT(5)
+#define STM32_USART_CR1_TCIE BIT(6)
+#define STM32_USART_CR1_TXEIE BIT(7)
+#define STM32_USART_CR1_PS BIT(9)
+#define STM32_USART_CR1_PCE BIT(10)
+#define STM32_USART_CR1_M BIT(12)
+#define STM32_USART_CR1_OVER8 BIT(15)
+#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04)
+#define STM32_USART_CR2_SWAP BIT(15)
+#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08)
+#define STM32_USART_CR3_EIE BIT(0)
+#define STM32_USART_CR3_DMAR BIT(6)
+#define STM32_USART_CR3_DMAT BIT(7)
+#define STM32_USART_CR3_ONEBIT BIT(11)
+#define STM32_USART_CR3_OVRDIS BIT(12)
+#define STM32_USART_CR3_WUS_START_BIT (2 << 20)
+#define STM32_USART_CR3_WUFIE BIT(22)
+#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C)
+#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10)
+#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14)
+#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18)
+#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C)
+#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20)
+#define STM32_USART_ICR_ORECF BIT(3)
+#define STM32_USART_ICR_TCCF BIT(6)
+#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24)
+#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28)
+#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C)
 /* register alias */
-#define STM32_USART_SR(base)       STM32_USART_ISR(base)
-#define STM32_USART_SR_ORE		BIT(3)
-#define STM32_USART_SR_RXNE		BIT(5)
-#define STM32_USART_SR_TC		BIT(6)
-#define STM32_USART_SR_TXE		BIT(7)
+#define STM32_USART_SR(base) STM32_USART_ISR(base)
+#define STM32_USART_SR_ORE BIT(3)
+#define STM32_USART_SR_RXNE BIT(5)
+#define STM32_USART_SR_TC BIT(6)
+#define STM32_USART_SR_TXE BIT(7)
 
 /* --- GPIO --- */
 
-#define STM32_GPIO_MODER(b)     REG32((b) + 0x00)
-#define STM32_GPIO_OTYPER(b)    REG16((b) + 0x04)
-#define STM32_GPIO_OSPEEDR(b)   REG32((b) + 0x08)
-#define STM32_GPIO_PUPDR(b)     REG32((b) + 0x0C)
-#define STM32_GPIO_IDR(b)       REG16((b) + 0x10)
-#define STM32_GPIO_ODR(b)       REG16((b) + 0x14)
-#define STM32_GPIO_BSRR(b)      REG32((b) + 0x18)
-#define STM32_GPIO_LCKR(b)      REG32((b) + 0x1C)
-#define STM32_GPIO_AFRL(b)      REG32((b) + 0x20)
-#define STM32_GPIO_AFRH(b)      REG32((b) + 0x24)
-#define STM32_GPIO_BRR(b)       REG32((b) + 0x28)
-#define STM32_GPIO_ASCR(b)      REG32((b) + 0x2C) /* only for stm32l4 */
-
-#define GPIO_ALT_F0		0x0
-#define GPIO_ALT_F1		0x1
-#define GPIO_ALT_F2		0x2
-#define GPIO_ALT_F3		0x3
-#define GPIO_ALT_F4		0x4
-#define GPIO_ALT_F5		0x5
-#define GPIO_ALT_F6		0x6
-#define GPIO_ALT_F7		0x7
-#define GPIO_ALT_F8		0x8
-#define GPIO_ALT_F9		0x9
-#define GPIO_ALT_FA		0xA
-#define GPIO_ALT_FB		0xB
-#define GPIO_ALT_FC		0xC
-#define GPIO_ALT_FD		0xD
-#define GPIO_ALT_FE		0xE
-#define GPIO_ALT_FF		0xF
+#define STM32_GPIO_MODER(b) REG32((b) + 0x00)
+#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04)
+#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08)
+#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C)
+#define STM32_GPIO_IDR(b) REG16((b) + 0x10)
+#define STM32_GPIO_ODR(b) REG16((b) + 0x14)
+#define STM32_GPIO_BSRR(b) REG32((b) + 0x18)
+#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C)
+#define STM32_GPIO_AFRL(b) REG32((b) + 0x20)
+#define STM32_GPIO_AFRH(b) REG32((b) + 0x24)
+#define STM32_GPIO_BRR(b) REG32((b) + 0x28)
+#define STM32_GPIO_ASCR(b) REG32((b) + 0x2C) /* only for stm32l4 */
+
+#define GPIO_ALT_F0 0x0
+#define GPIO_ALT_F1 0x1
+#define GPIO_ALT_F2 0x2
+#define GPIO_ALT_F3 0x3
+#define GPIO_ALT_F4 0x4
+#define GPIO_ALT_F5 0x5
+#define GPIO_ALT_F6 0x6
+#define GPIO_ALT_F7 0x7
+#define GPIO_ALT_F8 0x8
+#define GPIO_ALT_F9 0x9
+#define GPIO_ALT_FA 0xA
+#define GPIO_ALT_FB 0xB
+#define GPIO_ALT_FC 0xC
+#define GPIO_ALT_FD 0xD
+#define GPIO_ALT_FE 0xE
+#define GPIO_ALT_FF 0xF
 
 /* --- I2C --- */
-#define STM32_I2C_CR1(n)            REG32(stm32_i2c_reg(n, 0x00))
-#define STM32_I2C_CR1_PE            BIT(0)
-#define STM32_I2C_CR1_TXIE          BIT(1)
-#define STM32_I2C_CR1_RXIE          BIT(2)
-#define STM32_I2C_CR1_ADDRIE        BIT(3)
-#define STM32_I2C_CR1_NACKIE        BIT(4)
-#define STM32_I2C_CR1_STOPIE        BIT(5)
-#define STM32_I2C_CR1_ERRIE         BIT(7)
-#define STM32_I2C_CR1_WUPEN         BIT(18)
-#define STM32_I2C_CR2(n)            REG32(stm32_i2c_reg(n, 0x04))
-#define STM32_I2C_CR2_RD_WRN        BIT(10)
-#define STM32_I2C_CR2_START         BIT(13)
-#define STM32_I2C_CR2_STOP          BIT(14)
-#define STM32_I2C_CR2_NACK          BIT(15)
-#define STM32_I2C_CR2_RELOAD        BIT(24)
-#define STM32_I2C_CR2_AUTOEND       BIT(25)
-#define STM32_I2C_OAR1(n)           REG32(stm32_i2c_reg(n, 0x08))
-#define STM32_I2C_OAR2(n)           REG32(stm32_i2c_reg(n, 0x0C))
-#define STM32_I2C_TIMINGR(n)        REG32(stm32_i2c_reg(n, 0x10))
-#define STM32_I2C_TIMEOUTR(n)       REG32(stm32_i2c_reg(n, 0x14))
-#define STM32_I2C_ISR(n)            REG32(stm32_i2c_reg(n, 0x18))
-#define STM32_I2C_ISR_TXE           BIT(0)
-#define STM32_I2C_ISR_TXIS          BIT(1)
-#define STM32_I2C_ISR_RXNE          BIT(2)
-#define STM32_I2C_ISR_ADDR          BIT(3)
-#define STM32_I2C_ISR_NACK          BIT(4)
-#define STM32_I2C_ISR_STOP          BIT(5)
-#define STM32_I2C_ISR_TC            BIT(6)
-#define STM32_I2C_ISR_TCR           BIT(7)
-#define STM32_I2C_ISR_BERR          BIT(8)
-#define STM32_I2C_ISR_ARLO          BIT(9)
-#define STM32_I2C_ISR_OVR           BIT(10)
-#define STM32_I2C_ISR_PECERR        BIT(11)
-#define STM32_I2C_ISR_TIMEOUT       BIT(12)
-#define STM32_I2C_ISR_ALERT         BIT(13)
-#define STM32_I2C_ISR_BUSY          BIT(15)
-#define STM32_I2C_ISR_DIR           BIT(16)
-#define STM32_I2C_ISR_ADDCODE(isr)  (((isr) >> 16) & 0xfe)
-#define STM32_I2C_ICR(n)            REG32(stm32_i2c_reg(n, 0x1C))
-#define STM32_I2C_ICR_ADDRCF        BIT(3)
-#define STM32_I2C_ICR_NACKCF        BIT(4)
-#define STM32_I2C_ICR_STOPCF        BIT(5)
-#define STM32_I2C_ICR_BERRCF        BIT(8)
-#define STM32_I2C_ICR_ARLOCF        BIT(9)
-#define STM32_I2C_ICR_OVRCF         BIT(10)
-#define STM32_I2C_ICR_TIMEOUTCF     BIT(12)
-#define STM32_I2C_ICR_ALL           0x3F38
-#define STM32_I2C_PECR(n)           REG32(stm32_i2c_reg(n, 0x20))
-#define STM32_I2C_RXDR(n)           REG32(stm32_i2c_reg(n, 0x24))
-#define STM32_I2C_TXDR(n)           REG32(stm32_i2c_reg(n, 0x28))
-
+#define STM32_I2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00))
+#define STM32_I2C_CR1_PE BIT(0)
+#define STM32_I2C_CR1_TXIE BIT(1)
+#define STM32_I2C_CR1_RXIE BIT(2)
+#define STM32_I2C_CR1_ADDRIE BIT(3)
+#define STM32_I2C_CR1_NACKIE BIT(4)
+#define STM32_I2C_CR1_STOPIE BIT(5)
+#define STM32_I2C_CR1_ERRIE BIT(7)
+#define STM32_I2C_CR1_WUPEN BIT(18)
+#define STM32_I2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04))
+#define STM32_I2C_CR2_RD_WRN BIT(10)
+#define STM32_I2C_CR2_START BIT(13)
+#define STM32_I2C_CR2_STOP BIT(14)
+#define STM32_I2C_CR2_NACK BIT(15)
+#define STM32_I2C_CR2_RELOAD BIT(24)
+#define STM32_I2C_CR2_AUTOEND BIT(25)
+#define STM32_I2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08))
+#define STM32_I2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C))
+#define STM32_I2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10))
+#define STM32_I2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14))
+#define STM32_I2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18))
+#define STM32_I2C_ISR_TXE BIT(0)
+#define STM32_I2C_ISR_TXIS BIT(1)
+#define STM32_I2C_ISR_RXNE BIT(2)
+#define STM32_I2C_ISR_ADDR BIT(3)
+#define STM32_I2C_ISR_NACK BIT(4)
+#define STM32_I2C_ISR_STOP BIT(5)
+#define STM32_I2C_ISR_TC BIT(6)
+#define STM32_I2C_ISR_TCR BIT(7)
+#define STM32_I2C_ISR_BERR BIT(8)
+#define STM32_I2C_ISR_ARLO BIT(9)
+#define STM32_I2C_ISR_OVR BIT(10)
+#define STM32_I2C_ISR_PECERR BIT(11)
+#define STM32_I2C_ISR_TIMEOUT BIT(12)
+#define STM32_I2C_ISR_ALERT BIT(13)
+#define STM32_I2C_ISR_BUSY BIT(15)
+#define STM32_I2C_ISR_DIR BIT(16)
+#define STM32_I2C_ISR_ADDCODE(isr) (((isr) >> 16) & 0xfe)
+#define STM32_I2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C))
+#define STM32_I2C_ICR_ADDRCF BIT(3)
+#define STM32_I2C_ICR_NACKCF BIT(4)
+#define STM32_I2C_ICR_STOPCF BIT(5)
+#define STM32_I2C_ICR_BERRCF BIT(8)
+#define STM32_I2C_ICR_ARLOCF BIT(9)
+#define STM32_I2C_ICR_OVRCF BIT(10)
+#define STM32_I2C_ICR_TIMEOUTCF BIT(12)
+#define STM32_I2C_ICR_ALL 0x3F38
+#define STM32_I2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20))
+#define STM32_I2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24))
+#define STM32_I2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28))
 
 /* --- Power / Reset / Clocks --- */
-#define STM32_PWR_CR                REG32(STM32_PWR_BASE + 0x00)
-#define STM32_PWD_PVD_LS_MASK       (0x07 << 5)
-#define STM32_PWD_PVD_LS(n)         ((n & 0x07) << 5)
-#define STM32_PWR_PVDE              BIT(4)
-
-#define STM32_PWR_CSR               REG32(STM32_PWR_BASE + 0x04)
-
-#define STM32_PWR_CSR_EWUP1         BIT(8)
-#define STM32_PWR_CSR_EWUP2         BIT(9)
-#define STM32_PWR_CSR_EWUP3         BIT(10)
-#define STM32_PWR_CSR_EWUP4         BIT(11) /* STM32F0xx only */
-#define STM32_PWR_CSR_EWUP5         BIT(12) /* STM32F0xx only */
-#define STM32_PWR_CSR_EWUP6         BIT(13) /* STM32F0xx only */
-#define STM32_PWR_CSR_EWUP7         BIT(14) /* STM32F0xx only */
-#define STM32_PWR_CSR_EWUP8         BIT(15) /* STM32F0xx only */
-
-#define STM32_CRS_CR                REG32(STM32_CRS_BASE + 0x00) /* STM32F0XX */
-#define STM32_CRS_CR_SYNCOKIE           BIT(0)
-#define STM32_CRS_CR_SYNCWARNIE         BIT(1)
-#define STM32_CRS_CR_ERRIE              BIT(2)
-#define STM32_CRS_CR_ESYNCIE            BIT(3)
-#define STM32_CRS_CR_CEN                BIT(5)
-#define STM32_CRS_CR_AUTOTRIMEN         BIT(6)
-#define STM32_CRS_CR_SWSYNC             BIT(7)
-#define STM32_CRS_CR_TRIM(n)		(((n) & 0x3f) << 8)
-
-#define STM32_CRS_CFGR              REG32(STM32_CRS_BASE + 0x04) /* STM32F0XX */
-#define STM32_CRS_CFGR_RELOAD(n)	(((n) & 0xffff) << 0)
-#define STM32_CRS_CFGR_FELIM(n)		(((n) & 0xff) << 16)
-#define STM32_CRS_CFGR_SYNCDIV(n)	(((n) & 7) << 24)
-#define STM32_CRS_CFGR_SYNCSRC(n)	(((n) & 3) << 28)
-#define STM32_CRS_CFGR_SYNCPOL		BIT(31)
-
-#define STM32_CRS_ISR               REG32(STM32_CRS_BASE + 0x08) /* STM32F0XX */
-#define STM32_CRS_ISR_SYNCOKF		BIT(0)
-#define STM32_CRS_ISR_SYNCWARNF		BIT(1)
-#define STM32_CRS_ISR_ERRF		BIT(2)
-#define STM32_CRS_ISR_ESYNCF		BIT(3)
-#define STM32_CRS_ISR_SYNCERR		BIT(8)
-#define STM32_CRS_ISR_SYNCMISS		BIT(9)
-#define STM32_CRS_ISR_TRIMOVF		BIT(10)
-#define STM32_CRS_ISR_FEDIR		BIT(15)
-#define STM32_CRS_ISR_FECAP		(0xffff << 16)
-
-#define STM32_CRS_ICR               REG32(STM32_CRS_BASE + 0x0c) /* STM32F0XX */
-#define STM32_CRS_ICR_SYNCOKC		BIT(0)
-#define STM32_CRS_ICR_SYNCWARINC	BIT(1)
-#define STM32_CRS_ICR_ERRC		BIT(2)
-#define STM32_CRS_ICR_ESYNCC		BIT(3)
-
-#define STM32_RCC_CR                REG32(STM32_RCC_BASE + 0x00)
-#define STM32_RCC_CFGR              REG32(STM32_RCC_BASE + 0x04)
-#define STM32_RCC_CIR               REG32(STM32_RCC_BASE + 0x08)
-#define STM32_RCC_APB2RSTR          REG32(STM32_RCC_BASE + 0x0c)
-#define STM32_RCC_APB1RSTR          REG32(STM32_RCC_BASE + 0x10)
-#define STM32_RCC_AHBENR            REG32(STM32_RCC_BASE + 0x14)
-#define STM32_RCC_APB2ENR           REG32(STM32_RCC_BASE + 0x18)
-#define STM32_RCC_APB2ENR_ADCEN     BIT(9) /* STM32F3/F0 */
-#define STM32_RCC_APB2ENR_TIM16EN   BIT(17)
-#define STM32_RCC_APB2ENR_TIM17EN   BIT(18)
-#define STM32_RCC_DBGMCUEN          BIT(22)
-#define STM32_RCC_SYSCFGEN          BIT(0)
-
-#define STM32_RCC_APB1ENR           REG32(STM32_RCC_BASE + 0x1c)
-#define STM32_RCC_DACEN                 BIT(29)
-#define STM32_RCC_PWREN                 BIT(28)
-
-#define STM32_RCC_BDCR              REG32(STM32_RCC_BASE + 0x20)
-#define STM32_RCC_CSR               REG32(STM32_RCC_BASE + 0x24)
+#define STM32_PWR_CR REG32(STM32_PWR_BASE + 0x00)
+#define STM32_PWD_PVD_LS_MASK (0x07 << 5)
+#define STM32_PWD_PVD_LS(n) ((n & 0x07) << 5)
+#define STM32_PWR_PVDE BIT(4)
+
+#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04)
+
+#define STM32_PWR_CSR_EWUP1 BIT(8)
+#define STM32_PWR_CSR_EWUP2 BIT(9)
+#define STM32_PWR_CSR_EWUP3 BIT(10)
+#define STM32_PWR_CSR_EWUP4 BIT(11) /* STM32F0xx only */
+#define STM32_PWR_CSR_EWUP5 BIT(12) /* STM32F0xx only */
+#define STM32_PWR_CSR_EWUP6 BIT(13) /* STM32F0xx only */
+#define STM32_PWR_CSR_EWUP7 BIT(14) /* STM32F0xx only */
+#define STM32_PWR_CSR_EWUP8 BIT(15) /* STM32F0xx only */
+
+#define STM32_CRS_CR REG32(STM32_CRS_BASE + 0x00) /* STM32F0XX */
+#define STM32_CRS_CR_SYNCOKIE BIT(0)
+#define STM32_CRS_CR_SYNCWARNIE BIT(1)
+#define STM32_CRS_CR_ERRIE BIT(2)
+#define STM32_CRS_CR_ESYNCIE BIT(3)
+#define STM32_CRS_CR_CEN BIT(5)
+#define STM32_CRS_CR_AUTOTRIMEN BIT(6)
+#define STM32_CRS_CR_SWSYNC BIT(7)
+#define STM32_CRS_CR_TRIM(n) (((n)&0x3f) << 8)
+
+#define STM32_CRS_CFGR REG32(STM32_CRS_BASE + 0x04) /* STM32F0XX */
+#define STM32_CRS_CFGR_RELOAD(n) (((n)&0xffff) << 0)
+#define STM32_CRS_CFGR_FELIM(n) (((n)&0xff) << 16)
+#define STM32_CRS_CFGR_SYNCDIV(n) (((n)&7) << 24)
+#define STM32_CRS_CFGR_SYNCSRC(n) (((n)&3) << 28)
+#define STM32_CRS_CFGR_SYNCPOL BIT(31)
+
+#define STM32_CRS_ISR REG32(STM32_CRS_BASE + 0x08) /* STM32F0XX */
+#define STM32_CRS_ISR_SYNCOKF BIT(0)
+#define STM32_CRS_ISR_SYNCWARNF BIT(1)
+#define STM32_CRS_ISR_ERRF BIT(2)
+#define STM32_CRS_ISR_ESYNCF BIT(3)
+#define STM32_CRS_ISR_SYNCERR BIT(8)
+#define STM32_CRS_ISR_SYNCMISS BIT(9)
+#define STM32_CRS_ISR_TRIMOVF BIT(10)
+#define STM32_CRS_ISR_FEDIR BIT(15)
+#define STM32_CRS_ISR_FECAP (0xffff << 16)
+
+#define STM32_CRS_ICR REG32(STM32_CRS_BASE + 0x0c) /* STM32F0XX */
+#define STM32_CRS_ICR_SYNCOKC BIT(0)
+#define STM32_CRS_ICR_SYNCWARINC BIT(1)
+#define STM32_CRS_ICR_ERRC BIT(2)
+#define STM32_CRS_ICR_ESYNCC BIT(3)
+
+#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00)
+#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x04)
+#define STM32_RCC_CIR REG32(STM32_RCC_BASE + 0x08)
+#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x0c)
+#define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x10)
+#define STM32_RCC_AHBENR REG32(STM32_RCC_BASE + 0x14)
+#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x18)
+#define STM32_RCC_APB2ENR_ADCEN BIT(9) /* STM32F3/F0 */
+#define STM32_RCC_APB2ENR_TIM16EN BIT(17)
+#define STM32_RCC_APB2ENR_TIM17EN BIT(18)
+#define STM32_RCC_DBGMCUEN BIT(22)
+#define STM32_RCC_SYSCFGEN BIT(0)
+
+#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x1c)
+#define STM32_RCC_DACEN BIT(29)
+#define STM32_RCC_PWREN BIT(28)
+
+#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x20)
+#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x24)
 /* STM32F373 */
-#define STM32_RCC_CFGR2             REG32(STM32_RCC_BASE + 0x2c)
+#define STM32_RCC_CFGR2 REG32(STM32_RCC_BASE + 0x2c)
 /* STM32F0XX and STM32F373 */
-#define STM32_RCC_CFGR3             REG32(STM32_RCC_BASE + 0x30)
-#define STM32_RCC_CR2               REG32(STM32_RCC_BASE + 0x34) /* STM32F0XX */
+#define STM32_RCC_CFGR3 REG32(STM32_RCC_BASE + 0x30)
+#define STM32_RCC_CR2 REG32(STM32_RCC_BASE + 0x34) /* STM32F0XX */
 
-#define STM32_RCC_HB_DMA1		BIT(0)
+#define STM32_RCC_HB_DMA1 BIT(0)
 /* STM32F373 */
-#define STM32_RCC_HB_DMA2		BIT(1)
-#define STM32_RCC_PB2_TIM1		BIT(11) /* Except STM32F373 */
-#define STM32_RCC_PB2_TIM15		BIT(16) /* STM32F0XX and STM32F373 */
-#define STM32_RCC_PB2_TIM16		BIT(17) /* STM32F0XX and STM32F373 */
-#define STM32_RCC_PB2_TIM17		BIT(18) /* STM32F0XX and STM32F373 */
-#define STM32_RCC_PB2_TIM19		BIT(19) /* STM32F373 */
-#define STM32_RCC_PB2_PMAD		BIT(11) /* STM32TS */
-#define STM32_RCC_PB2_PMSE		BIT(13) /* STM32TS */
-#define STM32_RCC_PB1_TIM12		BIT(6)  /* STM32F373 */
-#define STM32_RCC_PB1_TIM13		BIT(7)  /* STM32F373 */
-#define STM32_RCC_PB1_TIM14		BIT(8)  /* STM32F0XX and STM32F373 */
-#define STM32_RCC_PB1_TIM18		BIT(9)  /* STM32F373 */
-#define STM32_RCC_PB1_USB		BIT(23)
-#define STM32_RCC_PB1_CRS		BIT(27)
-
-#define STM32_SYSCFG_CFGR1          REG32(STM32_SYSCFG_BASE + 0x00)
-#define STM32_SYSCFG_EXTICR(n)      REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
-#define STM32_SYSCFG_CFGR2          REG32(STM32_SYSCFG_BASE + 0x18)
-
+#define STM32_RCC_HB_DMA2 BIT(1)
+#define STM32_RCC_PB2_TIM1 BIT(11) /* Except STM32F373 */
+#define STM32_RCC_PB2_TIM15 BIT(16) /* STM32F0XX and STM32F373 */
+#define STM32_RCC_PB2_TIM16 BIT(17) /* STM32F0XX and STM32F373 */
+#define STM32_RCC_PB2_TIM17 BIT(18) /* STM32F0XX and STM32F373 */
+#define STM32_RCC_PB2_TIM19 BIT(19) /* STM32F373 */
+#define STM32_RCC_PB2_PMAD BIT(11) /* STM32TS */
+#define STM32_RCC_PB2_PMSE BIT(13) /* STM32TS */
+#define STM32_RCC_PB1_TIM12 BIT(6) /* STM32F373 */
+#define STM32_RCC_PB1_TIM13 BIT(7) /* STM32F373 */
+#define STM32_RCC_PB1_TIM14 BIT(8) /* STM32F0XX and STM32F373 */
+#define STM32_RCC_PB1_TIM18 BIT(9) /* STM32F373 */
+#define STM32_RCC_PB1_USB BIT(23)
+#define STM32_RCC_PB1_CRS BIT(27)
+
+#define STM32_SYSCFG_CFGR1 REG32(STM32_SYSCFG_BASE + 0x00)
+#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
+#define STM32_SYSCFG_CFGR2 REG32(STM32_SYSCFG_BASE + 0x18)
 
 /* Peripheral bits for RCC_APB/AHB and DBGMCU regs */
-#define STM32_RCC_PB2_USART1		BIT(14)
+#define STM32_RCC_PB2_USART1 BIT(14)
 
 /* Reset causes definitions */
 /* Reset causes in RCC CSR register */
 #define STM32_RCC_RESET_CAUSE STM32_RCC_CSR
-#define  RESET_CAUSE_WDG                0x60000000
-#define  RESET_CAUSE_SFT                0x10000000
-#define  RESET_CAUSE_POR                0x08000000
-#define  RESET_CAUSE_PIN                0x04000000
-#define  RESET_CAUSE_OTHER              0xfe000000
-#define  RESET_CAUSE_RMVF               0x01000000
+#define RESET_CAUSE_WDG 0x60000000
+#define RESET_CAUSE_SFT 0x10000000
+#define RESET_CAUSE_POR 0x08000000
+#define RESET_CAUSE_PIN 0x04000000
+#define RESET_CAUSE_OTHER 0xfe000000
+#define RESET_CAUSE_RMVF 0x01000000
 /* Power cause in PWR CSR register */
-#define STM32_PWR_RESET_CAUSE           STM32_PWR_CSR
-#define STM32_PWR_RESET_CAUSE_CLR       STM32_PWR_CR
-#define  RESET_CAUSE_SBF                0x00000002
-#define  RESET_CAUSE_SBF_CLR            0x00000004
+#define STM32_PWR_RESET_CAUSE STM32_PWR_CSR
+#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR
+#define RESET_CAUSE_SBF 0x00000002
+#define RESET_CAUSE_SBF_CLR 0x00000004
 
 /* --- Watchdogs --- */
 
 /* --- Real-Time Clock --- */
-#define STM32_RTC_TR                REG32(STM32_RTC_BASE + 0x00)
-#define STM32_RTC_DR                REG32(STM32_RTC_BASE + 0x04)
-#define STM32_RTC_CR                REG32(STM32_RTC_BASE + 0x08)
-#define STM32_RTC_CR_BYPSHAD        BIT(5)
-#define STM32_RTC_CR_ALRAE          BIT(8)
-#define STM32_RTC_CR_ALRAIE         BIT(12)
-#define STM32_RTC_ISR               REG32(STM32_RTC_BASE + 0x0C)
-#define STM32_RTC_ISR_ALRAWF        BIT(0)
-#define STM32_RTC_ISR_RSF           BIT(5)
-#define STM32_RTC_ISR_INITF         BIT(6)
-#define STM32_RTC_ISR_INIT          BIT(7)
-#define STM32_RTC_ISR_ALRAF         BIT(8)
-#define STM32_RTC_PRER              REG32(STM32_RTC_BASE + 0x10)
-#define STM32_RTC_PRER_A_MASK       (0x7f << 16)
-#define STM32_RTC_PRER_S_MASK       (0x7fff << 0)
-#define STM32_RTC_WUTR              REG32(STM32_RTC_BASE + 0x14)
-#define STM32_RTC_CALIBR            REG32(STM32_RTC_BASE + 0x18)
-#define STM32_RTC_ALRMAR            REG32(STM32_RTC_BASE + 0x1C)
-#define STM32_RTC_ALRMBR            REG32(STM32_RTC_BASE + 0x20)
-#define STM32_RTC_WPR               REG32(STM32_RTC_BASE + 0x24)
-#define STM32_RTC_SSR               REG32(STM32_RTC_BASE + 0x28)
-#define STM32_RTC_TSTR              REG32(STM32_RTC_BASE + 0x30)
-#define STM32_RTC_TSDR              REG32(STM32_RTC_BASE + 0x34)
-#define STM32_RTC_TAFCR             REG32(STM32_RTC_BASE + 0x40)
-#define STM32_RTC_ALRMASSR          REG32(STM32_RTC_BASE + 0x44)
-#define STM32_RTC_BACKUP(n)         REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
-
-#define STM32_BKP_DATA(n)           STM32_RTC_BACKUP(n)
-#define STM32_BKP_BYTES             20
+#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00)
+#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04)
+#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08)
+#define STM32_RTC_CR_BYPSHAD BIT(5)
+#define STM32_RTC_CR_ALRAE BIT(8)
+#define STM32_RTC_CR_ALRAIE BIT(12)
+#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C)
+#define STM32_RTC_ISR_ALRAWF BIT(0)
+#define STM32_RTC_ISR_RSF BIT(5)
+#define STM32_RTC_ISR_INITF BIT(6)
+#define STM32_RTC_ISR_INIT BIT(7)
+#define STM32_RTC_ISR_ALRAF BIT(8)
+#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10)
+#define STM32_RTC_PRER_A_MASK (0x7f << 16)
+#define STM32_RTC_PRER_S_MASK (0x7fff << 0)
+#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14)
+#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18)
+#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C)
+#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20)
+#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24)
+#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28)
+#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30)
+#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34)
+#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40)
+#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44)
+#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
+
+#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n)
+#define STM32_BKP_BYTES 20
 
 /* --- SPI --- */
 
@@ -433,15 +428,15 @@ struct stm32_spi_regs {
 	uint16_t _pad0;
 	uint16_t cr2;
 	uint16_t _pad1;
-	unsigned sr;
+	unsigned int sr;
 	uint8_t dr;
 	uint8_t _pad2;
 	uint16_t _pad3;
-	unsigned crcpr;
-	unsigned rxcrcr;
-	unsigned txcrcr;
-	unsigned i2scfgr;	/* STM32L only */
-	unsigned i2spr;		/* STM32L only */
+	unsigned int crcpr;
+	unsigned int rxcrcr;
+	unsigned int txcrcr;
+	unsigned int i2scfgr; /* STM32L only */
+	unsigned int i2spr; /* STM32L only */
 };
 /* Must be volatile, or compiler optimizes out repeated accesses */
 typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
@@ -451,155 +446,154 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
 #define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE)
 #define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE)
 
-#define STM32_SPI_CR1_BIDIMODE		BIT(15)
-#define STM32_SPI_CR1_BIDIOE		BIT(14)
-#define STM32_SPI_CR1_CRCEN		BIT(13)
-#define STM32_SPI_CR1_SSM		BIT(9)
-#define STM32_SPI_CR1_SSI		BIT(8)
-#define STM32_SPI_CR1_LSBFIRST		BIT(7)
-#define STM32_SPI_CR1_SPE		BIT(6)
-#define STM32_SPI_CR1_BR_DIV64R		(5 << 3)
-#define STM32_SPI_CR1_BR_DIV4R		BIT(3)
-#define STM32_SPI_CR1_MSTR		BIT(2)
-#define STM32_SPI_CR1_CPOL		BIT(1)
-#define STM32_SPI_CR1_CPHA		BIT(0)
-#define STM32_SPI_CR2_FRXTH		BIT(12)
-#define STM32_SPI_CR2_DATASIZE(n)	(((n) - 1) << 8)
-#define STM32_SPI_CR2_TXEIE		BIT(7)
-#define STM32_SPI_CR2_RXNEIE		BIT(6)
-#define STM32_SPI_CR2_NSSP		BIT(3)
-#define STM32_SPI_CR2_SSOE		BIT(2)
-#define STM32_SPI_CR2_TXDMAEN		BIT(1)
-#define STM32_SPI_CR2_RXDMAEN		BIT(0)
-
-#define STM32_SPI_SR_RXNE		BIT(0)
-#define STM32_SPI_SR_TXE		BIT(1)
-#define STM32_SPI_SR_CRCERR		BIT(4)
-#define STM32_SPI_SR_BSY		BIT(7)
-#define STM32_SPI_SR_FRLVL		(3 << 9)
-#define STM32_SPI_SR_FTLVL		(3 << 11)
+#define STM32_SPI_CR1_BIDIMODE BIT(15)
+#define STM32_SPI_CR1_BIDIOE BIT(14)
+#define STM32_SPI_CR1_CRCEN BIT(13)
+#define STM32_SPI_CR1_SSM BIT(9)
+#define STM32_SPI_CR1_SSI BIT(8)
+#define STM32_SPI_CR1_LSBFIRST BIT(7)
+#define STM32_SPI_CR1_SPE BIT(6)
+#define STM32_SPI_CR1_BR_DIV64R (5 << 3)
+#define STM32_SPI_CR1_BR_DIV4R BIT(3)
+#define STM32_SPI_CR1_MSTR BIT(2)
+#define STM32_SPI_CR1_CPOL BIT(1)
+#define STM32_SPI_CR1_CPHA BIT(0)
+#define STM32_SPI_CR2_FRXTH BIT(12)
+#define STM32_SPI_CR2_DATASIZE(n) (((n)-1) << 8)
+#define STM32_SPI_CR2_TXEIE BIT(7)
+#define STM32_SPI_CR2_RXNEIE BIT(6)
+#define STM32_SPI_CR2_NSSP BIT(3)
+#define STM32_SPI_CR2_SSOE BIT(2)
+#define STM32_SPI_CR2_TXDMAEN BIT(1)
+#define STM32_SPI_CR2_RXDMAEN BIT(0)
+
+#define STM32_SPI_SR_RXNE BIT(0)
+#define STM32_SPI_SR_TXE BIT(1)
+#define STM32_SPI_SR_CRCERR BIT(4)
+#define STM32_SPI_SR_BSY BIT(7)
+#define STM32_SPI_SR_FRLVL (3 << 9)
+#define STM32_SPI_SR_FTLVL (3 << 11)
 /* --- Debug --- */
-#define STM32_DBGMCU_APB1FZ         REG32(STM32_DBGMCU_BASE + 0x08)
-#define STM32_DBGMCU_APB2FZ         REG32(STM32_DBGMCU_BASE + 0x0C)
+#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08)
+#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C)
 
 /* --- Flash --- */
-#define STM32_FLASH_ACR             REG32(STM32_FLASH_REGS_BASE + 0x00)
+#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00)
 #define STM32_FLASH_ACR_LATENCY_SHIFT (0)
-#define STM32_FLASH_ACR_LATENCY_MASK  (7 << STM32_FLASH_ACR_LATENCY_SHIFT)
-#define STM32_FLASH_ACR_LATENCY     BIT(0)
-#define STM32_FLASH_ACR_PRFTEN      BIT(4)
-#define STM32_FLASH_KEYR            REG32(STM32_FLASH_REGS_BASE + 0x04)
-#define  FLASH_KEYR_KEY1                0x45670123
-#define  FLASH_KEYR_KEY2                0xCDEF89AB
-
-#define STM32_FLASH_OPTKEYR         REG32(STM32_FLASH_REGS_BASE + 0x08)
-#define  FLASH_OPTKEYR_KEY1             FLASH_KEYR_KEY1
-#define  FLASH_OPTKEYR_KEY2             FLASH_KEYR_KEY2
-#define STM32_FLASH_SR              REG32(STM32_FLASH_REGS_BASE + 0x0c)
-#define  FLASH_SR_BUSY                  BIT(0)
-#define  FLASH_SR_PGERR                 BIT(2)
-#define  FLASH_SR_WRPRTERR              BIT(4)
-#define  FLASH_SR_ALL_ERR \
-	(FLASH_SR_PGERR | FLASH_SR_WRPRTERR)
-#define  FLASH_SR_EOP                   BIT(5)
-#define STM32_FLASH_CR              REG32(STM32_FLASH_REGS_BASE + 0x10)
-#define  FLASH_CR_PG                    BIT(0)
-#define  FLASH_CR_PER                   BIT(1)
-#define  FLASH_CR_OPTPG                 BIT(4)
-#define  FLASH_CR_OPTER                 BIT(5)
-#define  FLASH_CR_STRT                  BIT(6)
-#define  FLASH_CR_LOCK                  BIT(7)
-#define  FLASH_CR_OPTWRE                BIT(9)
-#define  FLASH_CR_OBL_LAUNCH            BIT(13)
-#define STM32_FLASH_OPT_LOCKED      (!(STM32_FLASH_CR & FLASH_CR_OPTWRE))
-#define STM32_FLASH_AR              REG32(STM32_FLASH_REGS_BASE + 0x14)
-#define STM32_FLASH_OBR             REG32(STM32_FLASH_REGS_BASE + 0x1c)
-#define STM32_FLASH_OBR_RDP_MASK        (3 << 1)
-#define STM32_FLASH_WRPR            REG32(STM32_FLASH_REGS_BASE + 0x20)
-
-#define STM32_OPTB_RDP_OFF              0x00
-#define STM32_OPTB_USER_OFF             0x02
-#define STM32_OPTB_WRP_OFF(n)           (0x08 + (n&3) * 2)
-#define STM32_OPTB_WRP01                0x08
-#define STM32_OPTB_WRP23                0x0c
-
-#define STM32_OPTB_COMPL_SHIFT      8
+#define STM32_FLASH_ACR_LATENCY_MASK (7 << STM32_FLASH_ACR_LATENCY_SHIFT)
+#define STM32_FLASH_ACR_LATENCY BIT(0)
+#define STM32_FLASH_ACR_PRFTEN BIT(4)
+#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x04)
+#define FLASH_KEYR_KEY1 0x45670123
+#define FLASH_KEYR_KEY2 0xCDEF89AB
+
+#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x08)
+#define FLASH_OPTKEYR_KEY1 FLASH_KEYR_KEY1
+#define FLASH_OPTKEYR_KEY2 FLASH_KEYR_KEY2
+#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x0c)
+#define FLASH_SR_BUSY BIT(0)
+#define FLASH_SR_PGERR BIT(2)
+#define FLASH_SR_WRPRTERR BIT(4)
+#define FLASH_SR_ALL_ERR (FLASH_SR_PGERR | FLASH_SR_WRPRTERR)
+#define FLASH_SR_EOP BIT(5)
+#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x10)
+#define FLASH_CR_PG BIT(0)
+#define FLASH_CR_PER BIT(1)
+#define FLASH_CR_OPTPG BIT(4)
+#define FLASH_CR_OPTER BIT(5)
+#define FLASH_CR_STRT BIT(6)
+#define FLASH_CR_LOCK BIT(7)
+#define FLASH_CR_OPTWRE BIT(9)
+#define FLASH_CR_OBL_LAUNCH BIT(13)
+#define STM32_FLASH_OPT_LOCKED (!(STM32_FLASH_CR & FLASH_CR_OPTWRE))
+#define STM32_FLASH_AR REG32(STM32_FLASH_REGS_BASE + 0x14)
+#define STM32_FLASH_OBR REG32(STM32_FLASH_REGS_BASE + 0x1c)
+#define STM32_FLASH_OBR_RDP_MASK (3 << 1)
+#define STM32_FLASH_WRPR REG32(STM32_FLASH_REGS_BASE + 0x20)
+
+#define STM32_OPTB_RDP_OFF 0x00
+#define STM32_OPTB_USER_OFF 0x02
+#define STM32_OPTB_WRP_OFF(n) (0x08 + (n & 3) * 2)
+#define STM32_OPTB_WRP01 0x08
+#define STM32_OPTB_WRP23 0x0c
+
+#define STM32_OPTB_COMPL_SHIFT 8
 
 /* --- External Interrupts --- */
-#define STM32_EXTI_IMR              REG32(STM32_EXTI_BASE + 0x00)
-#define STM32_EXTI_EMR              REG32(STM32_EXTI_BASE + 0x04)
-#define STM32_EXTI_RTSR             REG32(STM32_EXTI_BASE + 0x08)
-#define STM32_EXTI_FTSR             REG32(STM32_EXTI_BASE + 0x0c)
-#define STM32_EXTI_SWIER            REG32(STM32_EXTI_BASE + 0x10)
-#define STM32_EXTI_PR               REG32(STM32_EXTI_BASE + 0x14)
+#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00)
+#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04)
+#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08)
+#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c)
+#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10)
+#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14)
 
-#define EXTI_PVD_EVENT              BIT(16)
-#define EXTI_RTC_ALR_EVENT          BIT(17)
-#define EXTI_COMP2_EVENT            BIT(22)
+#define EXTI_PVD_EVENT BIT(16)
+#define EXTI_RTC_ALR_EVENT BIT(17)
+#define EXTI_COMP2_EVENT BIT(22)
 
 /* --- ADC --- */
-#define STM32_ADC_ISR              REG32(STM32_ADC1_BASE + 0x00)
-#define STM32_ADC_ISR_ADRDY        BIT(0)
-#define STM32_ADC_IER              REG32(STM32_ADC1_BASE + 0x04)
-#define STM32_ADC_IER_AWDIE        BIT(7)
-#define STM32_ADC_IER_OVRIE        BIT(4)
-#define STM32_ADC_IER_EOSEQIE      BIT(3)
-#define STM32_ADC_IER_EOCIE        BIT(2)
-#define STM32_ADC_IER_EOSMPIE      BIT(1)
-#define STM32_ADC_IER_ADRDYIE      BIT(0)
-
-#define STM32_ADC_CR               REG32(STM32_ADC1_BASE + 0x08)
-#define STM32_ADC_CR_ADEN          BIT(0)
-#define STM32_ADC_CR_ADDIS         BIT(1)
-#define STM32_ADC_CR_ADCAL         BIT(31)
-#define STM32_ADC_CFGR1            REG32(STM32_ADC1_BASE + 0x0C)
+#define STM32_ADC_ISR REG32(STM32_ADC1_BASE + 0x00)
+#define STM32_ADC_ISR_ADRDY BIT(0)
+#define STM32_ADC_IER REG32(STM32_ADC1_BASE + 0x04)
+#define STM32_ADC_IER_AWDIE BIT(7)
+#define STM32_ADC_IER_OVRIE BIT(4)
+#define STM32_ADC_IER_EOSEQIE BIT(3)
+#define STM32_ADC_IER_EOCIE BIT(2)
+#define STM32_ADC_IER_EOSMPIE BIT(1)
+#define STM32_ADC_IER_ADRDYIE BIT(0)
+
+#define STM32_ADC_CR REG32(STM32_ADC1_BASE + 0x08)
+#define STM32_ADC_CR_ADEN BIT(0)
+#define STM32_ADC_CR_ADDIS BIT(1)
+#define STM32_ADC_CR_ADCAL BIT(31)
+#define STM32_ADC_CFGR1 REG32(STM32_ADC1_BASE + 0x0C)
 /* Analog watchdog channel selection */
 #define STM32_ADC_CFGR1_AWDCH_MASK (0x1f << 26)
-#define STM32_ADC_CFGR1_AWDEN      BIT(23)
-#define STM32_ADC_CFGR1_AWDSGL     BIT(22)
+#define STM32_ADC_CFGR1_AWDEN BIT(23)
+#define STM32_ADC_CFGR1_AWDSGL BIT(22)
 /* Selects single vs continuous */
-#define STM32_ADC_CFGR1_CONT       BIT(13)
+#define STM32_ADC_CFGR1_CONT BIT(13)
 /* Selects ADC_DR overwrite vs preserve */
-#define STM32_ADC_CFGR1_OVRMOD     BIT(12)
+#define STM32_ADC_CFGR1_OVRMOD BIT(12)
 /* External trigger polarity selection */
-#define STM32_ADC_CFGR1_EXTEN_DIS  (0 << 10)
+#define STM32_ADC_CFGR1_EXTEN_DIS (0 << 10)
 #define STM32_ADC_CFGR1_EXTEN_RISE (1 << 10)
 #define STM32_ADC_CFGR1_EXTEN_FALL (2 << 10)
 #define STM32_ADC_CFGR1_EXTEN_BOTH (3 << 10)
 #define STM32_ADC_CFGR1_EXTEN_MASK (3 << 10)
 /* External trigger selection */
-#define STM32_ADC_CFGR1_TRG0	   (0 << 6)
-#define STM32_ADC_CFGR1_TRG1	   (1 << 6)
-#define STM32_ADC_CFGR1_TRG2	   (2 << 6)
-#define STM32_ADC_CFGR1_TRG3	   (3 << 6)
-#define STM32_ADC_CFGR1_TRG4	   (4 << 6)
-#define STM32_ADC_CFGR1_TRG5	   (5 << 6)
-#define STM32_ADC_CFGR1_TRG6	   (6 << 6)
-#define STM32_ADC_CFGR1_TRG7	   (7 << 6)
-#define STM32_ADC_CFGR1_TRG_MASK   (7 << 6)
+#define STM32_ADC_CFGR1_TRG0 (0 << 6)
+#define STM32_ADC_CFGR1_TRG1 (1 << 6)
+#define STM32_ADC_CFGR1_TRG2 (2 << 6)
+#define STM32_ADC_CFGR1_TRG3 (3 << 6)
+#define STM32_ADC_CFGR1_TRG4 (4 << 6)
+#define STM32_ADC_CFGR1_TRG5 (5 << 6)
+#define STM32_ADC_CFGR1_TRG6 (6 << 6)
+#define STM32_ADC_CFGR1_TRG7 (7 << 6)
+#define STM32_ADC_CFGR1_TRG_MASK (7 << 6)
 /* Selects circular vs one-shot */
-#define STM32_ADC_CFGR1_DMACFG     BIT(1)
-#define STM32_ADC_CFGR1_DMAEN      BIT(0)
-#define STM32_ADC_CFGR2            REG32(STM32_ADC1_BASE + 0x10)
+#define STM32_ADC_CFGR1_DMACFG BIT(1)
+#define STM32_ADC_CFGR1_DMAEN BIT(0)
+#define STM32_ADC_CFGR2 REG32(STM32_ADC1_BASE + 0x10)
 /* Sampling time selection - 1.5 ADC cycles min, 239.5 cycles max */
-#define STM32_ADC_SMPR             REG32(STM32_ADC1_BASE + 0x14)
+#define STM32_ADC_SMPR REG32(STM32_ADC1_BASE + 0x14)
 /* Macro to convert enum stm32_adc_smpr to SMP bits of the ADC_SMPR register */
-#define STM32_ADC_SMPR_SMP(s)      ((s) - 1)
-#define STM32_ADC_TR               REG32(STM32_ADC1_BASE + 0x20)
-#define STM32_ADC_CHSELR           REG32(STM32_ADC1_BASE + 0x28)
-#define STM32_ADC_DR               REG32(STM32_ADC1_BASE + 0x40)
-#define STM32_ADC_CCR              REG32(STM32_ADC1_BASE + 0x308)
+#define STM32_ADC_SMPR_SMP(s) ((s)-1)
+#define STM32_ADC_TR REG32(STM32_ADC1_BASE + 0x20)
+#define STM32_ADC_CHSELR REG32(STM32_ADC1_BASE + 0x28)
+#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x40)
+#define STM32_ADC_CCR REG32(STM32_ADC1_BASE + 0x308)
 
 /* --- Comparators --- */
-#define STM32_COMP_CSR              REG32(STM32_COMP_BASE + 0x1C)
+#define STM32_COMP_CSR REG32(STM32_COMP_BASE + 0x1C)
 
-#define STM32_COMP_CMP2LOCK            BIT(31)
-#define STM32_COMP_CMP2OUT             BIT(30)
-#define STM32_COMP_CMP2HYST_HI         (3 << 28)
-#define STM32_COMP_CMP2HYST_MED        (2 << 28)
-#define STM32_COMP_CMP2HYST_LOW        (1 << 28)
-#define STM32_COMP_CMP2HYST_NO         (0 << 28)
-#define STM32_COMP_CMP2POL             BIT(27)
+#define STM32_COMP_CMP2LOCK BIT(31)
+#define STM32_COMP_CMP2OUT BIT(30)
+#define STM32_COMP_CMP2HYST_HI (3 << 28)
+#define STM32_COMP_CMP2HYST_MED (2 << 28)
+#define STM32_COMP_CMP2HYST_LOW (1 << 28)
+#define STM32_COMP_CMP2HYST_NO (0 << 28)
+#define STM32_COMP_CMP2POL BIT(27)
 
 #define STM32_COMP_CMP2OUTSEL_TIM3_OCR (7 << 24)
 #define STM32_COMP_CMP2OUTSEL_TIM3_IC1 (6 << 24)
@@ -608,32 +602,32 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
 #define STM32_COMP_CMP2OUTSEL_TIM1_OCR (3 << 24)
 #define STM32_COMP_CMP2OUTSEL_TIM1_IC1 (2 << 24)
 #define STM32_COMP_CMP2OUTSEL_TIM1_BRK (1 << 24)
-#define STM32_COMP_CMP2OUTSEL_NONE     (0 << 24)
-#define STM32_COMP_WNDWEN              BIT(23)
-
-#define STM32_COMP_CMP2INSEL_MASK      (7 << 20)
-#define STM32_COMP_CMP2INSEL_INM7      (6 << 20) /* STM32F373 only */
-#define STM32_COMP_CMP2INSEL_INM6      (6 << 20)
-#define STM32_COMP_CMP2INSEL_INM5      (5 << 20)
-#define STM32_COMP_CMP2INSEL_INM4      (4 << 20)
-#define STM32_COMP_CMP2INSEL_VREF      (3 << 20)
-#define STM32_COMP_CMP2INSEL_VREF34    (2 << 20)
-#define STM32_COMP_CMP2INSEL_VREF12    (1 << 20)
-#define STM32_COMP_CMP2INSEL_VREF14    (0 << 20)
-
-#define STM32_COMP_CMP2MODE_VLSPEED    (3 << 18)
-#define STM32_COMP_CMP2MODE_LSPEED     (2 << 18)
-#define STM32_COMP_CMP2MODE_MSPEED     (1 << 18)
-#define STM32_COMP_CMP2MODE_HSPEED     (0 << 18)
-#define STM32_COMP_CMP2EN              BIT(16)
-
-#define STM32_COMP_CMP1LOCK            BIT(15)
-#define STM32_COMP_CMP1OUT             BIT(14)
-#define STM32_COMP_CMP1HYST_HI         (3 << 12)
-#define STM32_COMP_CMP1HYST_MED        (2 << 12)
-#define STM32_COMP_CMP1HYST_LOW        (1 << 12)
-#define STM32_COMP_CMP1HYST_NO         (0 << 12)
-#define STM32_COMP_CMP1POL             BIT(11)
+#define STM32_COMP_CMP2OUTSEL_NONE (0 << 24)
+#define STM32_COMP_WNDWEN BIT(23)
+
+#define STM32_COMP_CMP2INSEL_MASK (7 << 20)
+#define STM32_COMP_CMP2INSEL_INM7 (6 << 20) /* STM32F373 only */
+#define STM32_COMP_CMP2INSEL_INM6 (6 << 20)
+#define STM32_COMP_CMP2INSEL_INM5 (5 << 20)
+#define STM32_COMP_CMP2INSEL_INM4 (4 << 20)
+#define STM32_COMP_CMP2INSEL_VREF (3 << 20)
+#define STM32_COMP_CMP2INSEL_VREF34 (2 << 20)
+#define STM32_COMP_CMP2INSEL_VREF12 (1 << 20)
+#define STM32_COMP_CMP2INSEL_VREF14 (0 << 20)
+
+#define STM32_COMP_CMP2MODE_VLSPEED (3 << 18)
+#define STM32_COMP_CMP2MODE_LSPEED (2 << 18)
+#define STM32_COMP_CMP2MODE_MSPEED (1 << 18)
+#define STM32_COMP_CMP2MODE_HSPEED (0 << 18)
+#define STM32_COMP_CMP2EN BIT(16)
+
+#define STM32_COMP_CMP1LOCK BIT(15)
+#define STM32_COMP_CMP1OUT BIT(14)
+#define STM32_COMP_CMP1HYST_HI (3 << 12)
+#define STM32_COMP_CMP1HYST_MED (2 << 12)
+#define STM32_COMP_CMP1HYST_LOW (1 << 12)
+#define STM32_COMP_CMP1HYST_NO (0 << 12)
+#define STM32_COMP_CMP1POL BIT(11)
 
 #define STM32_COMP_CMP1OUTSEL_TIM3_OCR (7 << 8)
 #define STM32_COMP_CMP1OUTSEL_TIM3_IC1 (6 << 8)
@@ -642,25 +636,24 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
 #define STM32_COMP_CMP1OUTSEL_TIM1_OCR (3 << 8)
 #define STM32_COMP_CMP1OUTSEL_TIM1_IC1 (2 << 8)
 #define STM32_COMP_CMP1OUTSEL_TIM1_BRK (1 << 8)
-#define STM32_COMP_CMP1OUTSEL_NONE     (0 << 8)
-
-#define STM32_COMP_CMP1INSEL_MASK      (7 << 4)
-#define STM32_COMP_CMP1INSEL_INM7      (7 << 4) /* STM32F373 only */
-#define STM32_COMP_CMP1INSEL_INM6      (6 << 4)
-#define STM32_COMP_CMP1INSEL_INM5      (5 << 4)
-#define STM32_COMP_CMP1INSEL_INM4      (4 << 4)
-#define STM32_COMP_CMP1INSEL_VREF      (3 << 4)
-#define STM32_COMP_CMP1INSEL_VREF34    (2 << 4)
-#define STM32_COMP_CMP1INSEL_VREF12    (1 << 4)
-#define STM32_COMP_CMP1INSEL_VREF14    (0 << 4)
-
-#define STM32_COMP_CMP1MODE_VLSPEED    (3 << 2)
-#define STM32_COMP_CMP1MODE_LSPEED     (2 << 2)
-#define STM32_COMP_CMP1MODE_MSPEED     (1 << 2)
-#define STM32_COMP_CMP1MODE_HSPEED     (0 << 2)
-#define STM32_COMP_CMP1SW1             BIT(1)
-#define STM32_COMP_CMP1EN              BIT(0)
-
+#define STM32_COMP_CMP1OUTSEL_NONE (0 << 8)
+
+#define STM32_COMP_CMP1INSEL_MASK (7 << 4)
+#define STM32_COMP_CMP1INSEL_INM7 (7 << 4) /* STM32F373 only */
+#define STM32_COMP_CMP1INSEL_INM6 (6 << 4)
+#define STM32_COMP_CMP1INSEL_INM5 (5 << 4)
+#define STM32_COMP_CMP1INSEL_INM4 (4 << 4)
+#define STM32_COMP_CMP1INSEL_VREF (3 << 4)
+#define STM32_COMP_CMP1INSEL_VREF34 (2 << 4)
+#define STM32_COMP_CMP1INSEL_VREF12 (1 << 4)
+#define STM32_COMP_CMP1INSEL_VREF14 (0 << 4)
+
+#define STM32_COMP_CMP1MODE_VLSPEED (3 << 2)
+#define STM32_COMP_CMP1MODE_LSPEED (2 << 2)
+#define STM32_COMP_CMP1MODE_MSPEED (1 << 2)
+#define STM32_COMP_CMP1MODE_HSPEED (0 << 2)
+#define STM32_COMP_CMP1SW1 BIT(1)
+#define STM32_COMP_CMP1EN BIT(0)
 
 /* --- DMA --- */
 
@@ -682,19 +675,19 @@ enum dma_channel {
 	STM32_DMAC_CH3 = 2,
 	STM32_DMAC_CH4 = 3,
 	STM32_DMAC_CH5 = 4,
+#if defined(CHIP_VARIANT_STM32F07X) || defined(CHIP_VARIANT_STM32F09X)
 	STM32_DMAC_CH6 = 5,
 	STM32_DMAC_CH7 = 6,
-	/*
-	 * Skip CH8, it should belong to DMA engine 1.
-	 * Sharing code with STM32s that have 16 engines will be easier.
-	 */
+#endif
+/* STM32F09 has two DMAs with 7 & 5 channels, respectively */
+#ifdef CHIP_VARIANT_STM32F09X
 	STM32_DMAC_CH9 = 8,
 	STM32_DMAC_CH10 = 9,
 	STM32_DMAC_CH11 = 10,
 	STM32_DMAC_CH12 = 11,
 	STM32_DMAC_CH13 = 12,
 	STM32_DMAC_CH14 = 13,
-
+#endif
 	/* Channel functions */
 	STM32_DMAC_ADC = STM32_DMAC_CH1,
 	STM32_DMAC_SPI1_RX = STM32_DMAC_CH2,
@@ -722,16 +715,19 @@ enum dma_channel {
 	STM32_DMAC_COUNT = 5,
 #endif
 };
-
+/*
+ * TODO(b/233369173): This file was originally shared by many MCUs,
+ *  8 is assumed to be the max number of channels for all chips.
+ */
 #define STM32_DMAC_PER_CTLR 8
 
 /* Registers for a single channel of the DMA controller */
 struct stm32_dma_chan {
-	uint32_t	ccr;		/* Control */
-	uint32_t	cndtr;		/* Number of data to transfer */
-	uint32_t	cpar;		/* Peripheral address */
-	uint32_t	cmar;		/* Memory address */
-	uint32_t	reserved;
+	uint32_t ccr; /* Control */
+	uint32_t cndtr; /* Number of data to transfer */
+	uint32_t cpar; /* Peripheral address */
+	uint32_t cmar; /* Memory address */
+	uint32_t reserved;
 };
 
 /* Always use stm32_dma_chan_t so volatile keyword is included! */
@@ -742,8 +738,8 @@ typedef stm32_dma_chan_t dma_chan_t;
 
 /* Registers for the DMA controller */
 struct stm32_dma_regs {
-	uint32_t	isr;
-	uint32_t	ifcr;
+	uint32_t isr;
+	uint32_t ifcr;
 	stm32_dma_chan_t chan[STM32_DMAC_COUNT];
 };
 
@@ -752,183 +748,106 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
 
 #define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE)
 
-
-#define STM32_DMA_CCR_CHANNEL(channel)		 (0)
+#define STM32_DMA_CCR_CHANNEL(channel) (0)
 
 #ifdef CHIP_VARIANT_STM32F09X
 #define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE)
 #define STM32_DMA_REGS(channel) \
 	((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_REGS : STM32_DMA2_REGS)
-#define STM32_DMA_CSELR(channel) \
-	REG32(((channel) < STM32_DMAC_PER_CTLR ? \
-			STM32_DMA1_BASE : STM32_DMA2_BASE)  + 0xA8)
+#define STM32_DMA_CSELR(channel)                                    \
+	REG32(((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_BASE :  \
+						 STM32_DMA2_BASE) + \
+	      0xA8)
 #else
 #define STM32_DMA_REGS(channel) STM32_DMA1_REGS
 #endif
 
 /* Bits for DMA controller regs (isr and ifcr) */
-#define STM32_DMA_CH_OFFSET(channel)   (4 * ((channel) % STM32_DMAC_PER_CTLR))
+#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR))
 #define STM32_DMA_ISR_MASK(channel, mask) \
 	((mask) << STM32_DMA_CH_OFFSET(channel))
-#define STM32_DMA_ISR_GIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(0))
-#define STM32_DMA_ISR_TCIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(1))
-#define STM32_DMA_ISR_HTIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(2))
-#define STM32_DMA_ISR_TEIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(3))
-#define STM32_DMA_ISR_ALL(channel)	STM32_DMA_ISR_MASK(channel, 0x0f)
-
-#define STM32_DMA_GIF                   BIT(0)
-#define STM32_DMA_TCIF                  BIT(1)
-#define STM32_DMA_HTIF                  BIT(2)
-#define STM32_DMA_TEIF                  BIT(3)
-#define STM32_DMA_ALL                   0xf
-
-#define STM32_DMA_GET_ISR(channel)      \
-	((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_ISR(channel, val) \
-	(STM32_DMA_REGS(channel)->isr = \
-	((STM32_DMA_REGS(channel)->isr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-#define STM32_DMA_GET_IFCR(channel)      \
-	((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_IFCR(channel, val) \
-	(STM32_DMA_REGS(channel)->ifcr = \
-	((STM32_DMA_REGS(channel)->ifcr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-
+#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0))
+#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1))
+#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2))
+#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3))
+#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f)
+
+#define STM32_DMA_GIF BIT(0)
+#define STM32_DMA_TCIF BIT(1)
+#define STM32_DMA_HTIF BIT(2)
+#define STM32_DMA_TEIF BIT(3)
+#define STM32_DMA_ALL 0xf
+
+#define STM32_DMA_GET_ISR(channel)                                        \
+	((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) & \
+	 STM32_DMA_ALL)
+#define STM32_DMA_SET_ISR(channel, val)                                \
+	(STM32_DMA_REGS(channel)->isr =                                \
+		 ((STM32_DMA_REGS(channel)->isr &                      \
+		   ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
+		  (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
+#define STM32_DMA_GET_IFCR(channel)                                        \
+	((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) & \
+	 STM32_DMA_ALL)
+#define STM32_DMA_SET_IFCR(channel, val)                               \
+	(STM32_DMA_REGS(channel)->ifcr =                               \
+		 ((STM32_DMA_REGS(channel)->ifcr &                     \
+		   ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
+		  (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
 
 /* Bits for DMA channel regs */
-#define STM32_DMA_CCR_EN		BIT(0)
-#define STM32_DMA_CCR_TCIE		BIT(1)
-#define STM32_DMA_CCR_HTIE		BIT(2)
-#define STM32_DMA_CCR_TEIE		BIT(3)
-#define STM32_DMA_CCR_DIR		BIT(4)
-#define STM32_DMA_CCR_CIRC		BIT(5)
-#define STM32_DMA_CCR_PINC		BIT(6)
-#define STM32_DMA_CCR_MINC		BIT(7)
-#define STM32_DMA_CCR_PSIZE_8_BIT	(0 << 8)
-#define STM32_DMA_CCR_PSIZE_16_BIT	(1 << 8)
-#define STM32_DMA_CCR_PSIZE_32_BIT	(2 << 8)
-#define STM32_DMA_CCR_MSIZE_8_BIT	(0 << 10)
-#define STM32_DMA_CCR_MSIZE_16_BIT	(1 << 10)
-#define STM32_DMA_CCR_MSIZE_32_BIT	(2 << 10)
-#define STM32_DMA_CCR_PL_LOW		(0 << 12)
-#define STM32_DMA_CCR_PL_MEDIUM		(1 << 12)
-#define STM32_DMA_CCR_PL_HIGH		(2 << 12)
-#define STM32_DMA_CCR_PL_VERY_HIGH	(3 << 12)
-#define STM32_DMA_CCR_MEM2MEM		BIT(14)
-
+#define STM32_DMA_CCR_EN BIT(0)
+#define STM32_DMA_CCR_TCIE BIT(1)
+#define STM32_DMA_CCR_HTIE BIT(2)
+#define STM32_DMA_CCR_TEIE BIT(3)
+#define STM32_DMA_CCR_DIR BIT(4)
+#define STM32_DMA_CCR_CIRC BIT(5)
+#define STM32_DMA_CCR_PINC BIT(6)
+#define STM32_DMA_CCR_MINC BIT(7)
+#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8)
+#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8)
+#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8)
+#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10)
+#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10)
+#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10)
+#define STM32_DMA_CCR_PL_LOW (0 << 12)
+#define STM32_DMA_CCR_PL_MEDIUM (1 << 12)
+#define STM32_DMA_CCR_PL_HIGH (2 << 12)
+#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12)
+#define STM32_DMA_CCR_MEM2MEM BIT(14)
 
 /* --- CRC --- */
-#define STM32_CRC_DR                REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR32              REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR16              REG16(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR8               REG8(STM32_CRC_BASE + 0x0)
-
-#define STM32_CRC_IDR               REG32(STM32_CRC_BASE + 0x4)
-#define STM32_CRC_CR                REG32(STM32_CRC_BASE + 0x8)
-#define STM32_CRC_INIT              REG32(STM32_CRC_BASE + 0x10)
-#define STM32_CRC_POL               REG32(STM32_CRC_BASE + 0x14)
-
-#define STM32_CRC_CR_RESET          BIT(0)
-#define STM32_CRC_CR_POLYSIZE_32    (0 << 3)
-#define STM32_CRC_CR_POLYSIZE_16    (1 << 3)
-#define STM32_CRC_CR_POLYSIZE_8     (2 << 3)
-#define STM32_CRC_CR_POLYSIZE_7     (3 << 3)
-#define STM32_CRC_CR_REV_IN_BYTE    (1 << 5)
-#define STM32_CRC_CR_REV_IN_HWORD   (2 << 5)
-#define STM32_CRC_CR_REV_IN_WORD    (3 << 5)
-#define STM32_CRC_CR_REV_OUT        BIT(7)
-
-/* --- PMSE --- */
-#define STM32_PMSE_ARCR             REG32(STM32_PMSE_BASE + 0x0)
-#define STM32_PMSE_ACCR             REG32(STM32_PMSE_BASE + 0x4)
-#define STM32_PMSE_CR               REG32(STM32_PMSE_BASE + 0x8)
-#define STM32_PMSE_CRTDR            REG32(STM32_PMSE_BASE + 0x14)
-#define STM32_PMSE_IER              REG32(STM32_PMSE_BASE + 0x18)
-#define STM32_PMSE_SR               REG32(STM32_PMSE_BASE + 0x1c)
-#define STM32_PMSE_IFCR             REG32(STM32_PMSE_BASE + 0x20)
-#define STM32_PMSE_PxPMR(x)         REG32(STM32_PMSE_BASE + 0x2c + (x) * 4)
-#define STM32_PMSE_PAPMR            REG32(STM32_PMSE_BASE + 0x2c)
-#define STM32_PMSE_PBPMR            REG32(STM32_PMSE_BASE + 0x30)
-#define STM32_PMSE_PCPMR            REG32(STM32_PMSE_BASE + 0x34)
-#define STM32_PMSE_PDPMR            REG32(STM32_PMSE_BASE + 0x38)
-#define STM32_PMSE_PEPMR            REG32(STM32_PMSE_BASE + 0x3c)
-#define STM32_PMSE_PFPMR            REG32(STM32_PMSE_BASE + 0x40)
-#define STM32_PMSE_PGPMR            REG32(STM32_PMSE_BASE + 0x44)
-#define STM32_PMSE_PHPMR            REG32(STM32_PMSE_BASE + 0x48)
-#define STM32_PMSE_PIPMR            REG32(STM32_PMSE_BASE + 0x4c)
-#define STM32_PMSE_MRCR             REG32(STM32_PMSE_BASE + 0x100)
-#define STM32_PMSE_MCCR             REG32(STM32_PMSE_BASE + 0x104)
-
-/* --- USB --- */
-#define STM32_USB_EP(n)            REG16(STM32_USB_FS_BASE + (n) * 4)
-
-#define STM32_USB_CNTR             REG16(STM32_USB_FS_BASE + 0x40)
-
-#define STM32_USB_CNTR_FRES	    BIT(0)
-#define STM32_USB_CNTR_PDWN	    BIT(1)
-#define STM32_USB_CNTR_LP_MODE	    BIT(2)
-#define STM32_USB_CNTR_FSUSP	    BIT(3)
-#define STM32_USB_CNTR_RESUME	    BIT(4)
-#define STM32_USB_CNTR_L1RESUME	    BIT(5)
-#define STM32_USB_CNTR_L1REQM	    BIT(7)
-#define STM32_USB_CNTR_ESOFM	    BIT(8)
-#define STM32_USB_CNTR_SOFM	    BIT(9)
-#define STM32_USB_CNTR_RESETM	    BIT(10)
-#define STM32_USB_CNTR_SUSPM	    BIT(11)
-#define STM32_USB_CNTR_WKUPM	    BIT(12)
-#define STM32_USB_CNTR_ERRM	    BIT(13)
-#define STM32_USB_CNTR_PMAOVRM	    BIT(14)
-#define STM32_USB_CNTR_CTRM	    BIT(15)
-
-#define STM32_USB_ISTR             REG16(STM32_USB_FS_BASE + 0x44)
-
-#define STM32_USB_ISTR_EP_ID_MASK   (0x000f)
-#define STM32_USB_ISTR_DIR	    BIT(4)
-#define STM32_USB_ISTR_L1REQ	    BIT(7)
-#define STM32_USB_ISTR_ESOF	    BIT(8)
-#define STM32_USB_ISTR_SOF	    BIT(9)
-#define STM32_USB_ISTR_RESET	    BIT(10)
-#define STM32_USB_ISTR_SUSP	    BIT(11)
-#define STM32_USB_ISTR_WKUP	    BIT(12)
-#define STM32_USB_ISTR_ERR	    BIT(13)
-#define STM32_USB_ISTR_PMAOVR	    BIT(14)
-#define STM32_USB_ISTR_CTR	    BIT(15)
-
-#define STM32_USB_FNR              REG16(STM32_USB_FS_BASE + 0x48)
-
-#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14)
-#define STM32_USB_FNR_RXDP_RXDM_MASK  (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT)
-
-#define STM32_USB_DADDR            REG16(STM32_USB_FS_BASE + 0x4C)
-#define STM32_USB_BTABLE           REG16(STM32_USB_FS_BASE + 0x50)
-#define STM32_USB_LPMCSR           REG16(STM32_USB_FS_BASE + 0x54)
-#define STM32_USB_BCDR             REG16(STM32_USB_FS_BASE + 0x58)
-
-#define STM32_USB_BCDR_BCDEN	    BIT(0)
-#define STM32_USB_BCDR_DCDEN	    BIT(1)
-#define STM32_USB_BCDR_PDEN	    BIT(2)
-#define STM32_USB_BCDR_SDEN	    BIT(3)
-#define STM32_USB_BCDR_DCDET	    BIT(4)
-#define STM32_USB_BCDR_PDET	    BIT(5)
-#define STM32_USB_BCDR_SDET	    BIT(6)
-#define STM32_USB_BCDR_PS2DET	    BIT(7)
-
-#define EP_MASK     0x0F0F
-#define EP_TX_DTOG  0x0040
-#define EP_TX_MASK  0x0030
+#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0)
+
+#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4)
+#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8)
+#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10)
+#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14)
+
+#define STM32_CRC_CR_RESET BIT(0)
+#define STM32_CRC_CR_POLYSIZE_32 (0 << 3)
+#define STM32_CRC_CR_POLYSIZE_16 (1 << 3)
+#define STM32_CRC_CR_POLYSIZE_8 (2 << 3)
+#define STM32_CRC_CR_POLYSIZE_7 (3 << 3)
+#define STM32_CRC_CR_REV_IN_BYTE (1 << 5)
+#define STM32_CRC_CR_REV_IN_HWORD (2 << 5)
+#define STM32_CRC_CR_REV_IN_WORD (3 << 5)
+#define STM32_CRC_CR_REV_OUT BIT(7)
+
+#define EP_MASK 0x0F0F
+#define EP_TX_DTOG 0x0040
+#define EP_TX_MASK 0x0030
 #define EP_TX_VALID 0x0030
-#define EP_TX_NAK   0x0020
+#define EP_TX_NAK 0x0020
 #define EP_TX_STALL 0x0010
 #define EP_TX_DISAB 0x0000
-#define EP_RX_DTOG  0x4000
-#define EP_RX_MASK  0x3000
+#define EP_RX_DTOG 0x4000
+#define EP_RX_MASK 0x3000
 #define EP_RX_VALID 0x3000
-#define EP_RX_NAK   0x2000
+#define EP_RX_NAK 0x2000
 #define EP_RX_STALL 0x1000
 #define EP_RX_DISAB 0x0000
 
@@ -938,28 +857,27 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
 #define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID)
 
 #define STM32_TOGGLE_EP(n, mask, val, flags) \
-	STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \
-			^ (val)) | (flags))
+	STM32_USB_EP(n) =                    \
+		(((STM32_USB_EP(n) & (EP_MASK | (mask))) ^ (val)) | (flags))
 
 /* --- TRNG --- */
-#define STM32_RNG_CR                REG32(STM32_RNG_BASE + 0x0)
-#define STM32_RNG_CR_RNGEN          BIT(2)
-#define STM32_RNG_CR_IE             BIT(3)
-#define STM32_RNG_CR_CED            BIT(5)
-#define STM32_RNG_SR                REG32(STM32_RNG_BASE + 0x4)
-#define STM32_RNG_SR_DRDY           BIT(0)
-#define STM32_RNG_DR                REG32(STM32_RNG_BASE + 0x8)
+#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0)
+#define STM32_RNG_CR_RNGEN BIT(2)
+#define STM32_RNG_CR_IE BIT(3)
+#define STM32_RNG_CR_CED BIT(5)
+#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4)
+#define STM32_RNG_SR_DRDY BIT(0)
+#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8)
 
 /* --- AXI interconnect --- */
 
 /* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */
-#define STM32_AXI_TARG_FN_MOD(x)    REG32(STM32_GPV_BASE + 0x1108 + \
-					  0x1000 * (x))
-#define  WRITE_ISS_OVERRIDE         BIT(1)
-#define  READ_ISS_OVERRIDE          BIT(0)
+#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + 0x1000 * (x))
+#define WRITE_ISS_OVERRIDE BIT(1)
+#define READ_ISS_OVERRIDE BIT(0)
 
 /* --- MISC --- */
-#define STM32_UNIQUE_ID_ADDRESS     REG32_ADDR(STM32_UNIQUE_ID_BASE)
-#define STM32_UNIQUE_ID_LENGTH      (3 * 4)
+#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE)
+#define STM32_UNIQUE_ID_LENGTH (3 * 4)
 
 #endif /* !__ASSEMBLER__ */
diff --git a/chip/stm32/registers-stm32f3.h b/chip/stm32/registers-stm32f3.h
index b7e3cfc8af..82880accdc 100644
--- a/chip/stm32/registers-stm32f3.h
+++ b/chip/stm32/registers-stm32f3.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,473 +19,467 @@
 #endif
 
 /* --- IRQ numbers --- */
-#define STM32_IRQ_WWDG             0
-#define STM32_IRQ_PVD              1
-#define STM32_IRQ_TAMPER_STAMP     2
-#define STM32_IRQ_RTC_WAKEUP       3
-#define STM32_IRQ_FLASH            4
-#define STM32_IRQ_RCC              5
-#define STM32_IRQ_EXTI0            6
-#define STM32_IRQ_EXTI1            7
-#define STM32_IRQ_EXTI2            8
-#define STM32_IRQ_EXTI3            9
-#define STM32_IRQ_EXTI4           10
-#define STM32_IRQ_DMA_CHANNEL_1   11
-#define STM32_IRQ_DMA_CHANNEL_2   12
-#define STM32_IRQ_DMA_CHANNEL_3   13
-#define STM32_IRQ_DMA_CHANNEL_4   14
-#define STM32_IRQ_DMA_CHANNEL_5   15
-#define STM32_IRQ_DMA_CHANNEL_6   16
-#define STM32_IRQ_DMA_CHANNEL_7   17
+#define STM32_IRQ_WWDG 0
+#define STM32_IRQ_PVD 1
+#define STM32_IRQ_TAMPER_STAMP 2
+#define STM32_IRQ_RTC_WAKEUP 3
+#define STM32_IRQ_FLASH 4
+#define STM32_IRQ_RCC 5
+#define STM32_IRQ_EXTI0 6
+#define STM32_IRQ_EXTI1 7
+#define STM32_IRQ_EXTI2 8
+#define STM32_IRQ_EXTI3 9
+#define STM32_IRQ_EXTI4 10
+#define STM32_IRQ_DMA_CHANNEL_1 11
+#define STM32_IRQ_DMA_CHANNEL_2 12
+#define STM32_IRQ_DMA_CHANNEL_3 13
+#define STM32_IRQ_DMA_CHANNEL_4 14
+#define STM32_IRQ_DMA_CHANNEL_5 15
+#define STM32_IRQ_DMA_CHANNEL_6 16
+#define STM32_IRQ_DMA_CHANNEL_7 17
 #ifdef CHIP_VARIANT_STM32F373
-#define STM32_IRQ_USB_HP          74
-#define STM32_IRQ_USB_LP          75
+#define STM32_IRQ_USB_HP 74
+#define STM32_IRQ_USB_LP 75
 #else
-#define STM32_IRQ_USB_HP          19
-#define STM32_IRQ_USB_LP          20
+#define STM32_IRQ_USB_HP 19
+#define STM32_IRQ_USB_LP 20
 #endif
 
-#define STM32_IRQ_ADC1            18 /* STM32L4 only */
-#define STM32_IRQ_CAN_TX          19 /* STM32F373 only */
-#define STM32_IRQ_USB_LP_CAN_RX   20 /* STM32F373 only */
-#define STM32_IRQ_DAC             21
-#define STM32_IRQ_CAN_RX1         21 /* STM32F373 only */
+#define STM32_IRQ_ADC1 18 /* STM32L4 only */
+#define STM32_IRQ_CAN_TX 19 /* STM32F373 only */
+#define STM32_IRQ_USB_LP_CAN_RX 20 /* STM32F373 only */
+#define STM32_IRQ_DAC 21
+#define STM32_IRQ_CAN_RX1 21 /* STM32F373 only */
 
 #ifdef CHIP_VARIANT_STM32F373
-#define STM32_IRQ_COMP            64
+#define STM32_IRQ_COMP 64
 #else
-#define STM32_IRQ_COMP            22
+#define STM32_IRQ_COMP 22
 #endif
 
-#define STM32_IRQ_CAN_SCE         22 /* STM32F373 only */
-#define STM32_IRQ_EXTI9_5         23
-#define STM32_IRQ_LCD             24 /* STM32L15X only */
-#define STM32_IRQ_TIM15           24 /* STM32F373 only */
-#define STM32_IRQ_TIM9            25 /* STM32L15X only */
-#define STM32_IRQ_TIM16           25 /* STM32F373 only */
-#define STM32_IRQ_TIM10           26 /* STM32L15X only */
-#define STM32_IRQ_TIM17           26 /* STM32F373 only */
-#define STM32_IRQ_TIM11           27 /* STM32L15X only */
-#define STM32_IRQ_TIM18_DAC2      27 /* STM32F373 only */
-#define STM32_IRQ_TIM2            28
-#define STM32_IRQ_TIM3            29
-#define STM32_IRQ_TIM4            30
-#define STM32_IRQ_I2C1_EV         31
-#define STM32_IRQ_I2C1_ER         32
-#define STM32_IRQ_I2C2_EV         33
-#define STM32_IRQ_I2C2_ER         34
-#define STM32_IRQ_SPI1            35
-#define STM32_IRQ_SPI2            36
-#define STM32_IRQ_USART1          37
-#define STM32_IRQ_USART2          38
-#define STM32_IRQ_USART3          39
-#define STM32_IRQ_EXTI15_10       40
-#define STM32_IRQ_RTC_ALARM       41
-#define STM32_IRQ_USB_FS_WAKEUP   42 /* STM32L15X */
-#define STM32_IRQ_CEC             42 /* STM32F373 only */
-#define STM32_IRQ_TIM6_BASIC      43 /* STM32L15X only */
-#define STM32_IRQ_TIM12           43 /* STM32F373 only */
-#define STM32_IRQ_TIM7_BASIC      44 /* STM32L15X only */
-#define STM32_IRQ_TIM13           44 /* STM32F373 only */
-#define STM32_IRQ_TIM14           45 /* STM32F373 only */
-#define STM32_IRQ_TIM5            50 /* STM32F373 */
-#define STM32_IRQ_SPI3            51 /* STM32F373 */
-#define STM32_IRQ_USART4          52 /* STM32F446 only */
-#define STM32_IRQ_USART5          53 /* STM32F446 only */
-#define STM32_IRQ_TIM6_DAC        54 /* STM32F373 */
-#define STM32_IRQ_TIM7            55 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL1   56 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL2   57 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL3   58 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL4   59 /* STM32F373 only */
+#define STM32_IRQ_CAN_SCE 22 /* STM32F373 only */
+#define STM32_IRQ_EXTI9_5 23
+#define STM32_IRQ_LCD 24 /* STM32L15X only */
+#define STM32_IRQ_TIM15 24 /* STM32F373 only */
+#define STM32_IRQ_TIM9 25 /* STM32L15X only */
+#define STM32_IRQ_TIM16 25 /* STM32F373 only */
+#define STM32_IRQ_TIM10 26 /* STM32L15X only */
+#define STM32_IRQ_TIM17 26 /* STM32F373 only */
+#define STM32_IRQ_TIM11 27 /* STM32L15X only */
+#define STM32_IRQ_TIM18_DAC2 27 /* STM32F373 only */
+#define STM32_IRQ_TIM2 28
+#define STM32_IRQ_TIM3 29
+#define STM32_IRQ_TIM4 30
+#define STM32_IRQ_I2C1_EV 31
+#define STM32_IRQ_I2C1_ER 32
+#define STM32_IRQ_I2C2_EV 33
+#define STM32_IRQ_I2C2_ER 34
+#define STM32_IRQ_SPI1 35
+#define STM32_IRQ_SPI2 36
+#define STM32_IRQ_USART1 37
+#define STM32_IRQ_USART2 38
+#define STM32_IRQ_USART3 39
+#define STM32_IRQ_EXTI15_10 40
+#define STM32_IRQ_RTC_ALARM 41
+#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X */
+#define STM32_IRQ_CEC 42 /* STM32F373 only */
+#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */
+#define STM32_IRQ_TIM12 43 /* STM32F373 only */
+#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */
+#define STM32_IRQ_TIM13 44 /* STM32F373 only */
+#define STM32_IRQ_TIM14 45 /* STM32F373 only */
+#define STM32_IRQ_TIM5 50 /* STM32F373 */
+#define STM32_IRQ_SPI3 51 /* STM32F373 */
+#define STM32_IRQ_USART4 52 /* STM32F446 only */
+#define STM32_IRQ_USART5 53 /* STM32F446 only */
+#define STM32_IRQ_TIM6_DAC 54 /* STM32F373 */
+#define STM32_IRQ_TIM7 55 /* STM32F373 */
+#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F373 */
+#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F373 */
+#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F373 */
+#define STM32_IRQ_DMA2_CHANNEL4 59 /* STM32F373 only */
 /* if MISC_REMAP bits are set */
-#define STM32_IRQ_DMA2_CHANNEL5   60 /* STM32F373 */
-#define STM32_IRQ_SDADC1          61 /* STM32F373 only */
-#define STM32_IRQ_SDADC2          62 /* STM32F373 only */
-#define STM32_IRQ_SDADC3          63 /* STM32F373 only */
-#define STM32_IRQ_DMA2_CHANNEL6   68 /* STM32L4 only */
-#define STM32_IRQ_DMA2_CHANNEL7   69 /* STM32L4 only */
-#define STM32_IRQ_LPUART          70 /* STM32L4 only */
-#define STM32_IRQ_USART9          70 /* STM32L4 only */
-#define STM32_IRQ_USART6          71 /* STM32F446 only */
-#define STM32_IRQ_I2C3_EV         72 /* STM32F446 only */
-#define STM32_IRQ_I2C3_ER         73 /* STM32F446 only */
-#define STM32_IRQ_USB_WAKEUP      76 /* STM32F373 only */
-#define STM32_IRQ_TIM19           78 /* STM32F373 only */
-#define STM32_IRQ_AES             79 /* STM32L4 only */
-#define STM32_IRQ_RNG             80 /* STM32L4 only */
-#define STM32_IRQ_FPU             81 /* STM32F373 only */
-
+#define STM32_IRQ_DMA2_CHANNEL5 60 /* STM32F373 */
+#define STM32_IRQ_SDADC1 61 /* STM32F373 only */
+#define STM32_IRQ_SDADC2 62 /* STM32F373 only */
+#define STM32_IRQ_SDADC3 63 /* STM32F373 only */
+#define STM32_IRQ_DMA2_CHANNEL6 68 /* STM32L4 only */
+#define STM32_IRQ_DMA2_CHANNEL7 69 /* STM32L4 only */
+#define STM32_IRQ_LPUART 70 /* STM32L4 only */
+#define STM32_IRQ_USART9 70 /* STM32L4 only */
+#define STM32_IRQ_USART6 71 /* STM32F446 only */
+#define STM32_IRQ_I2C3_EV 72 /* STM32F446 only */
+#define STM32_IRQ_I2C3_ER 73 /* STM32F446 only */
+#define STM32_IRQ_USB_WAKEUP 76 /* STM32F373 only */
+#define STM32_IRQ_TIM19 78 /* STM32F373 only */
+#define STM32_IRQ_AES 79 /* STM32L4 only */
+#define STM32_IRQ_RNG 80 /* STM32L4 only */
+#define STM32_IRQ_FPU 81 /* STM32F373 only */
 
 /* To simplify code generation, define DMA channel 9..10 */
-#define STM32_IRQ_DMA_CHANNEL_9    STM32_IRQ_DMA2_CHANNEL1
-#define STM32_IRQ_DMA_CHANNEL_10   STM32_IRQ_DMA2_CHANNEL2
-#define STM32_IRQ_DMA_CHANNEL_13   STM32_IRQ_DMA2_CHANNEL6
-#define STM32_IRQ_DMA_CHANNEL_14   STM32_IRQ_DMA2_CHANNEL7
+#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1
+#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2
+#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6
+#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7
 
 /* aliases for easier code sharing */
 #define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV
 #define STM32_IRQ_I2C2 STM32_IRQ_I2C2_EV
 #define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV
 
-
-
 /* Peripheral base addresses */
-#define STM32_ADC1_BASE             0x40012400
-#define STM32_ADC_BASE              0x40012700 /* STM32L15X only */
+#define STM32_ADC1_BASE 0x40012400
+#define STM32_ADC_BASE 0x40012700 /* STM32L15X only */
 
-#define STM32_CEC_BASE              0x40007800 /* STM32F373 */
-#define STM32_CRC_BASE              0x40023000
-#define STM32_CRS_BASE              0x40006c00 /* STM32F0XX */
-#define STM32_DAC_BASE              0x40007400
+#define STM32_CEC_BASE 0x40007800 /* STM32F373 */
+#define STM32_CRC_BASE 0x40023000
+#define STM32_CRS_BASE 0x40006c00 /* STM32F0XX */
+#define STM32_DAC_BASE 0x40007400
 
-#define STM32_COMP_BASE             0x40010000
+#define STM32_COMP_BASE 0x40010000
 
-#define STM32_DBGMCU_BASE           0xE0042000
+#define STM32_DBGMCU_BASE 0xE0042000
 
-#define STM32_DMA1_BASE             0x40020000
-#define STM32_DMA2_BASE             0x40020400
+#define STM32_DMA1_BASE 0x40020000
+#define STM32_DMA2_BASE 0x40020400
 
-#define STM32_EXTI_BASE             0x40010400
+#define STM32_EXTI_BASE 0x40010400
 
-#define STM32_FLASH_REGS_BASE       0x40022000
+#define STM32_FLASH_REGS_BASE 0x40022000
 
-#define STM32_GPIOA_BASE            0x48000000
-#define STM32_GPIOB_BASE            0x48000400
-#define STM32_GPIOC_BASE            0x48000800
-#define STM32_GPIOD_BASE            0x48000C00
-#define STM32_GPIOE_BASE            0x48001000
-#define STM32_GPIOF_BASE            0x48001400
-#define STM32_GPIOG_BASE            0x48001800 /* only for stm32l4x6 */
-#define STM32_GPIOH_BASE            0x48001C00 /* only for stm32l4 */
+#define STM32_GPIOA_BASE 0x48000000
+#define STM32_GPIOB_BASE 0x48000400
+#define STM32_GPIOC_BASE 0x48000800
+#define STM32_GPIOD_BASE 0x48000C00
+#define STM32_GPIOE_BASE 0x48001000
+#define STM32_GPIOF_BASE 0x48001400
+#define STM32_GPIOG_BASE 0x48001800 /* only for stm32l4x6 */
+#define STM32_GPIOH_BASE 0x48001C00 /* only for stm32l4 */
 
-#define STM32_I2C1_BASE             0x40005400
-#define STM32_I2C2_BASE             0x40005800
-#define STM32_I2C3_BASE             0x40005C00
-#define STM32_I2C4_BASE             0x40006000
+#define STM32_I2C1_BASE 0x40005400
+#define STM32_I2C2_BASE 0x40005800
+#define STM32_I2C3_BASE 0x40005C00
+#define STM32_I2C4_BASE 0x40006000
 
-#define STM32_IWDG_BASE             0x40003000
-#define STM32_LCD_BASE              0x40002400
+#define STM32_IWDG_BASE 0x40003000
+#define STM32_LCD_BASE 0x40002400
 
-#define STM32_OPTB_BASE             0x1FFFF800
+#define STM32_OPTB_BASE 0x1FFFF800
 
-#define STM32_PMSE_BASE             0x40013400
-#define STM32_PWR_BASE              0x40007000
+#define STM32_PMSE_BASE 0x40013400
+#define STM32_PWR_BASE 0x40007000
 
-#define STM32_RCC_BASE              0x40021000
+#define STM32_RCC_BASE 0x40021000
 
-#define STM32_RI_BASE               0x40007C00 /* STM32L1xx only */
-#define STM32_RNG_BASE              0x50060800 /* STM32L4 */
-#define STM32_RTC_BASE              0x40002800
+#define STM32_RI_BASE 0x40007C00 /* STM32L1xx only */
+#define STM32_RNG_BASE 0x50060800 /* STM32L4 */
+#define STM32_RTC_BASE 0x40002800
 
-#define STM32_SPI1_BASE             0x40013000
-#define STM32_SPI2_BASE             0x40003800
-#define STM32_SPI3_BASE             0x40003c00 /* STM32F373, STM32L4, STM32F7 */
+#define STM32_SPI1_BASE 0x40013000
+#define STM32_SPI2_BASE 0x40003800
+#define STM32_SPI3_BASE 0x40003c00 /* STM32F373, STM32L4, STM32F7 */
 
-#define STM32_SYSCFG_BASE           0x40010000
+#define STM32_SYSCFG_BASE 0x40010000
 
-#define STM32_TIM1_BASE             0x40012c00 /* STM32F373 */
-#define STM32_TIM2_BASE             0x40000000
-#define STM32_TIM3_BASE             0x40000400
-#define STM32_TIM4_BASE             0x40000800
-#define STM32_TIM5_BASE             0x40000c00 /* STM32F373 */
-#define STM32_TIM6_BASE             0x40001000
-#define STM32_TIM7_BASE             0x40001400
-#define STM32_TIM12_BASE            0x40001800 /* STM32F373 */
-#define STM32_TIM13_BASE            0x40001c00 /* STM32F373 */
-#define STM32_TIM14_BASE            0x40002000 /* STM32F373 */
-#define STM32_TIM15_BASE            0x40014000
-#define STM32_TIM16_BASE            0x40014400
-#define STM32_TIM17_BASE            0x40014800
-#define STM32_TIM18_BASE            0x40009c00 /* STM32F373 only */
-#define STM32_TIM19_BASE            0x40015c00 /* STM32F373 only */
+#define STM32_TIM1_BASE 0x40012c00 /* STM32F373 */
+#define STM32_TIM2_BASE 0x40000000
+#define STM32_TIM3_BASE 0x40000400
+#define STM32_TIM4_BASE 0x40000800
+#define STM32_TIM5_BASE 0x40000c00 /* STM32F373 */
+#define STM32_TIM6_BASE 0x40001000
+#define STM32_TIM7_BASE 0x40001400
+#define STM32_TIM12_BASE 0x40001800 /* STM32F373 */
+#define STM32_TIM13_BASE 0x40001c00 /* STM32F373 */
+#define STM32_TIM14_BASE 0x40002000 /* STM32F373 */
+#define STM32_TIM15_BASE 0x40014000
+#define STM32_TIM16_BASE 0x40014400
+#define STM32_TIM17_BASE 0x40014800
+#define STM32_TIM18_BASE 0x40009c00 /* STM32F373 only */
+#define STM32_TIM19_BASE 0x40015c00 /* STM32F373 only */
 
-#define STM32_UNIQUE_ID_BASE        0x1ffff7ac
+#define STM32_UNIQUE_ID_BASE 0x1ffff7ac
 
-#define STM32_USART1_BASE           0x40013800
-#define STM32_USART2_BASE           0x40004400
-#define STM32_USART3_BASE           0x40004800
-#define STM32_USART4_BASE           0x40004c00
-#define STM32_USART9_BASE           0x40008000 /* LPUART */
+#define STM32_USART1_BASE 0x40013800
+#define STM32_USART2_BASE 0x40004400
+#define STM32_USART3_BASE 0x40004800
+#define STM32_USART4_BASE 0x40004c00
+#define STM32_USART9_BASE 0x40008000 /* LPUART */
 
-#define STM32_USB_CAN_SRAM_BASE     0x40006000
-#define STM32_USB_FS_BASE           0x40005C00
-
-#define STM32_WWDG_BASE             0x40002C00
+#define STM32_USB_CAN_SRAM_BASE 0x40006000
+#define STM32_USB_FS_BASE 0x40005C00
 
+#define STM32_WWDG_BASE 0x40002C00
 
 #ifndef __ASSEMBLER__
 
 /* Register definitions */
 
 /* --- USART --- */
-#define STM32_USART_CR1(base)      STM32_USART_REG(base, 0x00)
-#define STM32_USART_CR1_UE		BIT(0)
-#define STM32_USART_CR1_UESM            BIT(1)
-#define STM32_USART_CR1_RE		BIT(2)
-#define STM32_USART_CR1_TE		BIT(3)
-#define STM32_USART_CR1_RXNEIE		BIT(5)
-#define STM32_USART_CR1_TCIE		BIT(6)
-#define STM32_USART_CR1_TXEIE		BIT(7)
-#define STM32_USART_CR1_PS		BIT(9)
-#define STM32_USART_CR1_PCE		BIT(10)
-#define STM32_USART_CR1_M		BIT(12)
-#define STM32_USART_CR1_OVER8		BIT(15)
-#define STM32_USART_CR2(base)      STM32_USART_REG(base, 0x04)
-#define STM32_USART_CR2_SWAP		BIT(15)
-#define STM32_USART_CR3(base)      STM32_USART_REG(base, 0x08)
-#define STM32_USART_CR3_EIE		BIT(0)
-#define STM32_USART_CR3_DMAR		BIT(6)
-#define STM32_USART_CR3_DMAT		BIT(7)
-#define STM32_USART_CR3_ONEBIT		BIT(11)
-#define STM32_USART_CR3_OVRDIS		BIT(12)
-#define STM32_USART_CR3_WUS_START_BIT	(2 << 20)
-#define STM32_USART_CR3_WUFIE		BIT(22)
-#define STM32_USART_BRR(base)      STM32_USART_REG(base, 0x0C)
-#define STM32_USART_GTPR(base)     STM32_USART_REG(base, 0x10)
-#define STM32_USART_RTOR(base)     STM32_USART_REG(base, 0x14)
-#define STM32_USART_RQR(base)      STM32_USART_REG(base, 0x18)
-#define STM32_USART_ISR(base)      STM32_USART_REG(base, 0x1C)
-#define STM32_USART_ICR(base)      STM32_USART_REG(base, 0x20)
-#define STM32_USART_ICR_ORECF		BIT(3)
-#define STM32_USART_ICR_TCCF		BIT(6)
-#define STM32_USART_RDR(base)      STM32_USART_REG(base, 0x24)
-#define STM32_USART_TDR(base)      STM32_USART_REG(base, 0x28)
-#define STM32_USART_PRESC(base)    STM32_USART_REG(base, 0x2C)
+#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00)
+#define STM32_USART_CR1_UE BIT(0)
+#define STM32_USART_CR1_UESM BIT(1)
+#define STM32_USART_CR1_RE BIT(2)
+#define STM32_USART_CR1_TE BIT(3)
+#define STM32_USART_CR1_RXNEIE BIT(5)
+#define STM32_USART_CR1_TCIE BIT(6)
+#define STM32_USART_CR1_TXEIE BIT(7)
+#define STM32_USART_CR1_PS BIT(9)
+#define STM32_USART_CR1_PCE BIT(10)
+#define STM32_USART_CR1_M BIT(12)
+#define STM32_USART_CR1_OVER8 BIT(15)
+#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04)
+#define STM32_USART_CR2_SWAP BIT(15)
+#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08)
+#define STM32_USART_CR3_EIE BIT(0)
+#define STM32_USART_CR3_DMAR BIT(6)
+#define STM32_USART_CR3_DMAT BIT(7)
+#define STM32_USART_CR3_ONEBIT BIT(11)
+#define STM32_USART_CR3_OVRDIS BIT(12)
+#define STM32_USART_CR3_WUS_START_BIT (2 << 20)
+#define STM32_USART_CR3_WUFIE BIT(22)
+#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C)
+#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10)
+#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14)
+#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18)
+#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C)
+#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20)
+#define STM32_USART_ICR_ORECF BIT(3)
+#define STM32_USART_ICR_TCCF BIT(6)
+#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24)
+#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28)
+#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C)
 /* register alias */
-#define STM32_USART_SR(base)       STM32_USART_ISR(base)
-#define STM32_USART_SR_ORE		BIT(3)
-#define STM32_USART_SR_RXNE		BIT(5)
-#define STM32_USART_SR_TC		BIT(6)
-#define STM32_USART_SR_TXE		BIT(7)
+#define STM32_USART_SR(base) STM32_USART_ISR(base)
+#define STM32_USART_SR_ORE BIT(3)
+#define STM32_USART_SR_RXNE BIT(5)
+#define STM32_USART_SR_TC BIT(6)
+#define STM32_USART_SR_TXE BIT(7)
 
 /* --- GPIO --- */
 
-#define STM32_GPIO_MODER(b)     REG32((b) + 0x00)
-#define STM32_GPIO_OTYPER(b)    REG16((b) + 0x04)
-#define STM32_GPIO_OSPEEDR(b)   REG32((b) + 0x08)
-#define STM32_GPIO_PUPDR(b)     REG32((b) + 0x0C)
-#define STM32_GPIO_IDR(b)       REG16((b) + 0x10)
-#define STM32_GPIO_ODR(b)       REG16((b) + 0x14)
-#define STM32_GPIO_BSRR(b)      REG32((b) + 0x18)
-#define STM32_GPIO_LCKR(b)      REG32((b) + 0x1C)
-#define STM32_GPIO_AFRL(b)      REG32((b) + 0x20)
-#define STM32_GPIO_AFRH(b)      REG32((b) + 0x24)
-#define STM32_GPIO_BRR(b)       REG32((b) + 0x28)
-#define STM32_GPIO_ASCR(b)      REG32((b) + 0x2C) /* only for stm32l4 */
-
-#define GPIO_ALT_F0		0x0
-#define GPIO_ALT_F1		0x1
-#define GPIO_ALT_F2		0x2
-#define GPIO_ALT_F3		0x3
-#define GPIO_ALT_F4		0x4
-#define GPIO_ALT_F5		0x5
-#define GPIO_ALT_F6		0x6
-#define GPIO_ALT_F7		0x7
-#define GPIO_ALT_F8		0x8
-#define GPIO_ALT_F9		0x9
-#define GPIO_ALT_FA		0xA
-#define GPIO_ALT_FB		0xB
-#define GPIO_ALT_FC		0xC
-#define GPIO_ALT_FD		0xD
-#define GPIO_ALT_FE		0xE
-#define GPIO_ALT_FF		0xF
+#define STM32_GPIO_MODER(b) REG32((b) + 0x00)
+#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04)
+#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08)
+#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C)
+#define STM32_GPIO_IDR(b) REG16((b) + 0x10)
+#define STM32_GPIO_ODR(b) REG16((b) + 0x14)
+#define STM32_GPIO_BSRR(b) REG32((b) + 0x18)
+#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C)
+#define STM32_GPIO_AFRL(b) REG32((b) + 0x20)
+#define STM32_GPIO_AFRH(b) REG32((b) + 0x24)
+#define STM32_GPIO_BRR(b) REG32((b) + 0x28)
+#define STM32_GPIO_ASCR(b) REG32((b) + 0x2C) /* only for stm32l4 */
+
+#define GPIO_ALT_F0 0x0
+#define GPIO_ALT_F1 0x1
+#define GPIO_ALT_F2 0x2
+#define GPIO_ALT_F3 0x3
+#define GPIO_ALT_F4 0x4
+#define GPIO_ALT_F5 0x5
+#define GPIO_ALT_F6 0x6
+#define GPIO_ALT_F7 0x7
+#define GPIO_ALT_F8 0x8
+#define GPIO_ALT_F9 0x9
+#define GPIO_ALT_FA 0xA
+#define GPIO_ALT_FB 0xB
+#define GPIO_ALT_FC 0xC
+#define GPIO_ALT_FD 0xD
+#define GPIO_ALT_FE 0xE
+#define GPIO_ALT_FF 0xF
 
 /* --- I2C --- */
-#define STM32_I2C_CR1(n)            REG32(stm32_i2c_reg(n, 0x00))
-#define STM32_I2C_CR1_PE            BIT(0)
-#define STM32_I2C_CR1_TXIE          BIT(1)
-#define STM32_I2C_CR1_RXIE          BIT(2)
-#define STM32_I2C_CR1_ADDRIE        BIT(3)
-#define STM32_I2C_CR1_NACKIE        BIT(4)
-#define STM32_I2C_CR1_STOPIE        BIT(5)
-#define STM32_I2C_CR1_ERRIE         BIT(7)
-#define STM32_I2C_CR1_WUPEN         BIT(18)
-#define STM32_I2C_CR2(n)            REG32(stm32_i2c_reg(n, 0x04))
-#define STM32_I2C_CR2_RD_WRN        BIT(10)
-#define STM32_I2C_CR2_START         BIT(13)
-#define STM32_I2C_CR2_STOP          BIT(14)
-#define STM32_I2C_CR2_NACK          BIT(15)
-#define STM32_I2C_CR2_RELOAD        BIT(24)
-#define STM32_I2C_CR2_AUTOEND       BIT(25)
-#define STM32_I2C_OAR1(n)           REG32(stm32_i2c_reg(n, 0x08))
-#define STM32_I2C_OAR2(n)           REG32(stm32_i2c_reg(n, 0x0C))
-#define STM32_I2C_TIMINGR(n)        REG32(stm32_i2c_reg(n, 0x10))
-#define STM32_I2C_TIMEOUTR(n)       REG32(stm32_i2c_reg(n, 0x14))
-#define STM32_I2C_ISR(n)            REG32(stm32_i2c_reg(n, 0x18))
-#define STM32_I2C_ISR_TXE           BIT(0)
-#define STM32_I2C_ISR_TXIS          BIT(1)
-#define STM32_I2C_ISR_RXNE          BIT(2)
-#define STM32_I2C_ISR_ADDR          BIT(3)
-#define STM32_I2C_ISR_NACK          BIT(4)
-#define STM32_I2C_ISR_STOP          BIT(5)
-#define STM32_I2C_ISR_TC            BIT(6)
-#define STM32_I2C_ISR_TCR           BIT(7)
-#define STM32_I2C_ISR_BERR          BIT(8)
-#define STM32_I2C_ISR_ARLO          BIT(9)
-#define STM32_I2C_ISR_OVR           BIT(10)
-#define STM32_I2C_ISR_PECERR        BIT(11)
-#define STM32_I2C_ISR_TIMEOUT       BIT(12)
-#define STM32_I2C_ISR_ALERT         BIT(13)
-#define STM32_I2C_ISR_BUSY          BIT(15)
-#define STM32_I2C_ISR_DIR           BIT(16)
-#define STM32_I2C_ISR_ADDCODE(isr)  (((isr) >> 16) & 0xfe)
-#define STM32_I2C_ICR(n)            REG32(stm32_i2c_reg(n, 0x1C))
-#define STM32_I2C_ICR_ADDRCF        BIT(3)
-#define STM32_I2C_ICR_NACKCF        BIT(4)
-#define STM32_I2C_ICR_STOPCF        BIT(5)
-#define STM32_I2C_ICR_BERRCF        BIT(8)
-#define STM32_I2C_ICR_ARLOCF        BIT(9)
-#define STM32_I2C_ICR_OVRCF         BIT(10)
-#define STM32_I2C_ICR_TIMEOUTCF     BIT(12)
-#define STM32_I2C_ICR_ALL           0x3F38
-#define STM32_I2C_PECR(n)           REG32(stm32_i2c_reg(n, 0x20))
-#define STM32_I2C_RXDR(n)           REG32(stm32_i2c_reg(n, 0x24))
-#define STM32_I2C_TXDR(n)           REG32(stm32_i2c_reg(n, 0x28))
-
+#define STM32_I2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00))
+#define STM32_I2C_CR1_PE BIT(0)
+#define STM32_I2C_CR1_TXIE BIT(1)
+#define STM32_I2C_CR1_RXIE BIT(2)
+#define STM32_I2C_CR1_ADDRIE BIT(3)
+#define STM32_I2C_CR1_NACKIE BIT(4)
+#define STM32_I2C_CR1_STOPIE BIT(5)
+#define STM32_I2C_CR1_ERRIE BIT(7)
+#define STM32_I2C_CR1_WUPEN BIT(18)
+#define STM32_I2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04))
+#define STM32_I2C_CR2_RD_WRN BIT(10)
+#define STM32_I2C_CR2_START BIT(13)
+#define STM32_I2C_CR2_STOP BIT(14)
+#define STM32_I2C_CR2_NACK BIT(15)
+#define STM32_I2C_CR2_RELOAD BIT(24)
+#define STM32_I2C_CR2_AUTOEND BIT(25)
+#define STM32_I2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08))
+#define STM32_I2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C))
+#define STM32_I2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10))
+#define STM32_I2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14))
+#define STM32_I2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18))
+#define STM32_I2C_ISR_TXE BIT(0)
+#define STM32_I2C_ISR_TXIS BIT(1)
+#define STM32_I2C_ISR_RXNE BIT(2)
+#define STM32_I2C_ISR_ADDR BIT(3)
+#define STM32_I2C_ISR_NACK BIT(4)
+#define STM32_I2C_ISR_STOP BIT(5)
+#define STM32_I2C_ISR_TC BIT(6)
+#define STM32_I2C_ISR_TCR BIT(7)
+#define STM32_I2C_ISR_BERR BIT(8)
+#define STM32_I2C_ISR_ARLO BIT(9)
+#define STM32_I2C_ISR_OVR BIT(10)
+#define STM32_I2C_ISR_PECERR BIT(11)
+#define STM32_I2C_ISR_TIMEOUT BIT(12)
+#define STM32_I2C_ISR_ALERT BIT(13)
+#define STM32_I2C_ISR_BUSY BIT(15)
+#define STM32_I2C_ISR_DIR BIT(16)
+#define STM32_I2C_ISR_ADDCODE(isr) (((isr) >> 16) & 0xfe)
+#define STM32_I2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C))
+#define STM32_I2C_ICR_ADDRCF BIT(3)
+#define STM32_I2C_ICR_NACKCF BIT(4)
+#define STM32_I2C_ICR_STOPCF BIT(5)
+#define STM32_I2C_ICR_BERRCF BIT(8)
+#define STM32_I2C_ICR_ARLOCF BIT(9)
+#define STM32_I2C_ICR_OVRCF BIT(10)
+#define STM32_I2C_ICR_TIMEOUTCF BIT(12)
+#define STM32_I2C_ICR_ALL 0x3F38
+#define STM32_I2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20))
+#define STM32_I2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24))
+#define STM32_I2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28))
 
 /* --- Power / Reset / Clocks --- */
-#define STM32_PWR_CSR               REG32(STM32_PWR_BASE + 0x04)
-
-#define STM32_PWR_CSR_EWUP1         BIT(8)
-#define STM32_PWR_CSR_EWUP2         BIT(9)
-#define STM32_PWR_CSR_EWUP3         BIT(10)
-#define STM32_PWR_CSR_EWUP4         BIT(11) /* STM32F0xx only */
-#define STM32_PWR_CSR_EWUP5         BIT(12) /* STM32F0xx only */
-#define STM32_PWR_CSR_EWUP6         BIT(13) /* STM32F0xx only */
-#define STM32_PWR_CSR_EWUP7         BIT(14) /* STM32F0xx only */
-#define STM32_PWR_CSR_EWUP8         BIT(15) /* STM32F0xx only */
-
-#define STM32_CRS_CR                REG32(STM32_CRS_BASE + 0x00) /* STM32F0XX */
-#define STM32_CRS_CR_SYNCOKIE           BIT(0)
-#define STM32_CRS_CR_SYNCWARNIE         BIT(1)
-#define STM32_CRS_CR_ERRIE              BIT(2)
-#define STM32_CRS_CR_ESYNCIE            BIT(3)
-#define STM32_CRS_CR_CEN                BIT(5)
-#define STM32_CRS_CR_AUTOTRIMEN         BIT(6)
-#define STM32_CRS_CR_SWSYNC             BIT(7)
-#define STM32_CRS_CR_TRIM(n)		(((n) & 0x3f) << 8)
-
-#define STM32_CRS_CFGR              REG32(STM32_CRS_BASE + 0x04) /* STM32F0XX */
-#define STM32_CRS_CFGR_RELOAD(n)	(((n) & 0xffff) << 0)
-#define STM32_CRS_CFGR_FELIM(n)		(((n) & 0xff) << 16)
-#define STM32_CRS_CFGR_SYNCDIV(n)	(((n) & 7) << 24)
-#define STM32_CRS_CFGR_SYNCSRC(n)	(((n) & 3) << 28)
-#define STM32_CRS_CFGR_SYNCPOL		BIT(31)
-
-#define STM32_CRS_ISR               REG32(STM32_CRS_BASE + 0x08) /* STM32F0XX */
-#define STM32_CRS_ISR_SYNCOKF		BIT(0)
-#define STM32_CRS_ISR_SYNCWARNF		BIT(1)
-#define STM32_CRS_ISR_ERRF		BIT(2)
-#define STM32_CRS_ISR_ESYNCF		BIT(3)
-#define STM32_CRS_ISR_SYNCERR		BIT(8)
-#define STM32_CRS_ISR_SYNCMISS		BIT(9)
-#define STM32_CRS_ISR_TRIMOVF		BIT(10)
-#define STM32_CRS_ISR_FEDIR		BIT(15)
-#define STM32_CRS_ISR_FECAP		(0xffff << 16)
-
-#define STM32_CRS_ICR               REG32(STM32_CRS_BASE + 0x0c) /* STM32F0XX */
-#define STM32_CRS_ICR_SYNCOKC		BIT(0)
-#define STM32_CRS_ICR_SYNCWARINC	BIT(1)
-#define STM32_CRS_ICR_ERRC		BIT(2)
-#define STM32_CRS_ICR_ESYNCC		BIT(3)
-
-#define STM32_RCC_CR                REG32(STM32_RCC_BASE + 0x00)
-#define STM32_RCC_CFGR              REG32(STM32_RCC_BASE + 0x04)
-#define STM32_RCC_CIR               REG32(STM32_RCC_BASE + 0x08)
-#define STM32_RCC_APB2RSTR          REG32(STM32_RCC_BASE + 0x0c)
-#define STM32_RCC_APB1RSTR          REG32(STM32_RCC_BASE + 0x10)
-#define STM32_RCC_AHBENR            REG32(STM32_RCC_BASE + 0x14)
-#define STM32_RCC_APB2ENR           REG32(STM32_RCC_BASE + 0x18)
-#define STM32_RCC_APB2ENR_ADCEN     BIT(9) /* STM32F3/F0 */
-#define STM32_RCC_APB2ENR_TIM16EN   BIT(17)
-#define STM32_RCC_APB2ENR_TIM17EN   BIT(18)
-#define STM32_RCC_DBGMCUEN          BIT(22)
-#define STM32_RCC_SYSCFGEN          BIT(0)
-
-#define STM32_RCC_APB1ENR           REG32(STM32_RCC_BASE + 0x1c)
-#define STM32_RCC_PWREN                 BIT(28)
-
-#define STM32_RCC_BDCR              REG32(STM32_RCC_BASE + 0x20)
-#define STM32_RCC_CSR               REG32(STM32_RCC_BASE + 0x24)
+#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04)
+
+#define STM32_PWR_CSR_EWUP1 BIT(8)
+#define STM32_PWR_CSR_EWUP2 BIT(9)
+#define STM32_PWR_CSR_EWUP3 BIT(10)
+#define STM32_PWR_CSR_EWUP4 BIT(11) /* STM32F0xx only */
+#define STM32_PWR_CSR_EWUP5 BIT(12) /* STM32F0xx only */
+#define STM32_PWR_CSR_EWUP6 BIT(13) /* STM32F0xx only */
+#define STM32_PWR_CSR_EWUP7 BIT(14) /* STM32F0xx only */
+#define STM32_PWR_CSR_EWUP8 BIT(15) /* STM32F0xx only */
+
+#define STM32_CRS_CR REG32(STM32_CRS_BASE + 0x00) /* STM32F0XX */
+#define STM32_CRS_CR_SYNCOKIE BIT(0)
+#define STM32_CRS_CR_SYNCWARNIE BIT(1)
+#define STM32_CRS_CR_ERRIE BIT(2)
+#define STM32_CRS_CR_ESYNCIE BIT(3)
+#define STM32_CRS_CR_CEN BIT(5)
+#define STM32_CRS_CR_AUTOTRIMEN BIT(6)
+#define STM32_CRS_CR_SWSYNC BIT(7)
+#define STM32_CRS_CR_TRIM(n) (((n)&0x3f) << 8)
+
+#define STM32_CRS_CFGR REG32(STM32_CRS_BASE + 0x04) /* STM32F0XX */
+#define STM32_CRS_CFGR_RELOAD(n) (((n)&0xffff) << 0)
+#define STM32_CRS_CFGR_FELIM(n) (((n)&0xff) << 16)
+#define STM32_CRS_CFGR_SYNCDIV(n) (((n)&7) << 24)
+#define STM32_CRS_CFGR_SYNCSRC(n) (((n)&3) << 28)
+#define STM32_CRS_CFGR_SYNCPOL BIT(31)
+
+#define STM32_CRS_ISR REG32(STM32_CRS_BASE + 0x08) /* STM32F0XX */
+#define STM32_CRS_ISR_SYNCOKF BIT(0)
+#define STM32_CRS_ISR_SYNCWARNF BIT(1)
+#define STM32_CRS_ISR_ERRF BIT(2)
+#define STM32_CRS_ISR_ESYNCF BIT(3)
+#define STM32_CRS_ISR_SYNCERR BIT(8)
+#define STM32_CRS_ISR_SYNCMISS BIT(9)
+#define STM32_CRS_ISR_TRIMOVF BIT(10)
+#define STM32_CRS_ISR_FEDIR BIT(15)
+#define STM32_CRS_ISR_FECAP (0xffff << 16)
+
+#define STM32_CRS_ICR REG32(STM32_CRS_BASE + 0x0c) /* STM32F0XX */
+#define STM32_CRS_ICR_SYNCOKC BIT(0)
+#define STM32_CRS_ICR_SYNCWARINC BIT(1)
+#define STM32_CRS_ICR_ERRC BIT(2)
+#define STM32_CRS_ICR_ESYNCC BIT(3)
+
+#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00)
+#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x04)
+#define STM32_RCC_CIR REG32(STM32_RCC_BASE + 0x08)
+#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x0c)
+#define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x10)
+#define STM32_RCC_AHBENR REG32(STM32_RCC_BASE + 0x14)
+#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x18)
+#define STM32_RCC_APB2ENR_ADCEN BIT(9) /* STM32F3/F0 */
+#define STM32_RCC_APB2ENR_TIM16EN BIT(17)
+#define STM32_RCC_APB2ENR_TIM17EN BIT(18)
+#define STM32_RCC_DBGMCUEN BIT(22)
+#define STM32_RCC_SYSCFGEN BIT(0)
+
+#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x1c)
+#define STM32_RCC_PWREN BIT(28)
+
+#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x20)
+#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x24)
 /* STM32F373 */
-#define STM32_RCC_CFGR2             REG32(STM32_RCC_BASE + 0x2c)
+#define STM32_RCC_CFGR2 REG32(STM32_RCC_BASE + 0x2c)
 /* STM32F0XX and STM32F373 */
-#define STM32_RCC_CFGR3             REG32(STM32_RCC_BASE + 0x30)
-#define STM32_RCC_CR2               REG32(STM32_RCC_BASE + 0x34) /* STM32F0XX */
+#define STM32_RCC_CFGR3 REG32(STM32_RCC_BASE + 0x30)
+#define STM32_RCC_CR2 REG32(STM32_RCC_BASE + 0x34) /* STM32F0XX */
 
-#define STM32_RCC_HB_DMA1		BIT(0)
+#define STM32_RCC_HB_DMA1 BIT(0)
 /* STM32F373 */
-#define STM32_RCC_HB_DMA2		BIT(1)
-#define STM32_RCC_PB2_TIM1		BIT(11) /* Except STM32F373 */
-#define STM32_RCC_PB2_TIM15		BIT(16) /* STM32F0XX and STM32F373 */
-#define STM32_RCC_PB2_TIM16		BIT(17) /* STM32F0XX and STM32F373 */
-#define STM32_RCC_PB2_TIM17		BIT(18) /* STM32F0XX and STM32F373 */
-#define STM32_RCC_PB2_TIM19		BIT(19) /* STM32F373 */
-#define STM32_RCC_PB2_PMAD		BIT(11) /* STM32TS */
-#define STM32_RCC_PB2_PMSE		BIT(13) /* STM32TS */
-#define STM32_RCC_PB1_TIM12		BIT(6)  /* STM32F373 */
-#define STM32_RCC_PB1_TIM13		BIT(7)  /* STM32F373 */
-#define STM32_RCC_PB1_TIM14		BIT(8)  /* STM32F0XX and STM32F373 */
-#define STM32_RCC_PB1_TIM18		BIT(9)  /* STM32F373 */
-#define STM32_RCC_PB1_USB		BIT(23)
-#define STM32_RCC_PB1_CRS		BIT(27)
-
-#define STM32_SYSCFG_CFGR1          REG32(STM32_SYSCFG_BASE + 0x00)
-#define STM32_SYSCFG_EXTICR(n)      REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
-#define STM32_SYSCFG_CFGR2          REG32(STM32_SYSCFG_BASE + 0x18)
-
+#define STM32_RCC_HB_DMA2 BIT(1)
+#define STM32_RCC_PB2_TIM1 BIT(11) /* Except STM32F373 */
+#define STM32_RCC_PB2_TIM15 BIT(16) /* STM32F0XX and STM32F373 */
+#define STM32_RCC_PB2_TIM16 BIT(17) /* STM32F0XX and STM32F373 */
+#define STM32_RCC_PB2_TIM17 BIT(18) /* STM32F0XX and STM32F373 */
+#define STM32_RCC_PB2_TIM19 BIT(19) /* STM32F373 */
+#define STM32_RCC_PB2_PMAD BIT(11) /* STM32TS */
+#define STM32_RCC_PB2_PMSE BIT(13) /* STM32TS */
+#define STM32_RCC_PB1_TIM12 BIT(6) /* STM32F373 */
+#define STM32_RCC_PB1_TIM13 BIT(7) /* STM32F373 */
+#define STM32_RCC_PB1_TIM14 BIT(8) /* STM32F0XX and STM32F373 */
+#define STM32_RCC_PB1_TIM18 BIT(9) /* STM32F373 */
+#define STM32_RCC_PB1_USB BIT(23)
+#define STM32_RCC_PB1_CRS BIT(27)
+
+#define STM32_SYSCFG_CFGR1 REG32(STM32_SYSCFG_BASE + 0x00)
+#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
+#define STM32_SYSCFG_CFGR2 REG32(STM32_SYSCFG_BASE + 0x18)
 
 /* Peripheral bits for RCC_APB/AHB and DBGMCU regs */
-#define STM32_RCC_PB2_USART1		BIT(14)
+#define STM32_RCC_PB2_USART1 BIT(14)
 
 /* Reset causes definitions */
 /* Reset causes in RCC CSR register */
 #define STM32_RCC_RESET_CAUSE STM32_RCC_CSR
-#define  RESET_CAUSE_WDG                0x60000000
-#define  RESET_CAUSE_SFT                0x10000000
-#define  RESET_CAUSE_POR                0x08000000
-#define  RESET_CAUSE_PIN                0x04000000
-#define  RESET_CAUSE_OTHER              0xfe000000
-#define  RESET_CAUSE_RMVF               0x01000000
+#define RESET_CAUSE_WDG 0x60000000
+#define RESET_CAUSE_SFT 0x10000000
+#define RESET_CAUSE_POR 0x08000000
+#define RESET_CAUSE_PIN 0x04000000
+#define RESET_CAUSE_OTHER 0xfe000000
+#define RESET_CAUSE_RMVF 0x01000000
 /* Power cause in PWR CSR register */
 #define STM32_PWR_RESET_CAUSE STM32_PWR_CSR
 #define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR
-#define  RESET_CAUSE_SBF                0x00000002
-#define  RESET_CAUSE_SBF_CLR            0x00000004
+#define RESET_CAUSE_SBF 0x00000002
+#define RESET_CAUSE_SBF_CLR 0x00000004
 
 /* --- Watchdogs --- */
 
 /* --- Real-Time Clock --- */
-#define STM32_RTC_TR                REG32(STM32_RTC_BASE + 0x00)
-#define STM32_RTC_DR                REG32(STM32_RTC_BASE + 0x04)
-#define STM32_RTC_CR                REG32(STM32_RTC_BASE + 0x08)
-#define STM32_RTC_CR_BYPSHAD        BIT(5)
-#define STM32_RTC_CR_ALRAE          BIT(8)
-#define STM32_RTC_CR_ALRAIE         BIT(12)
-#define STM32_RTC_ISR               REG32(STM32_RTC_BASE + 0x0C)
-#define STM32_RTC_ISR_ALRAWF        BIT(0)
-#define STM32_RTC_ISR_RSF           BIT(5)
-#define STM32_RTC_ISR_INITF         BIT(6)
-#define STM32_RTC_ISR_INIT          BIT(7)
-#define STM32_RTC_ISR_ALRAF         BIT(8)
-#define STM32_RTC_PRER              REG32(STM32_RTC_BASE + 0x10)
-#define STM32_RTC_PRER_A_MASK       (0x7f << 16)
-#define STM32_RTC_PRER_S_MASK       (0x7fff << 0)
-#define STM32_RTC_WUTR              REG32(STM32_RTC_BASE + 0x14)
-#define STM32_RTC_CALIBR            REG32(STM32_RTC_BASE + 0x18)
-#define STM32_RTC_ALRMAR            REG32(STM32_RTC_BASE + 0x1C)
-#define STM32_RTC_ALRMBR            REG32(STM32_RTC_BASE + 0x20)
-#define STM32_RTC_WPR               REG32(STM32_RTC_BASE + 0x24)
-#define STM32_RTC_SSR               REG32(STM32_RTC_BASE + 0x28)
-#define STM32_RTC_TSTR              REG32(STM32_RTC_BASE + 0x30)
-#define STM32_RTC_TSDR              REG32(STM32_RTC_BASE + 0x34)
-#define STM32_RTC_TAFCR             REG32(STM32_RTC_BASE + 0x40)
-#define STM32_RTC_ALRMASSR          REG32(STM32_RTC_BASE + 0x44)
-#define STM32_RTC_BACKUP(n)         REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
-
-#define STM32_BKP_DATA(n)           STM32_RTC_BACKUP(n)
-#define STM32_BKP_BYTES             64
+#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00)
+#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04)
+#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08)
+#define STM32_RTC_CR_BYPSHAD BIT(5)
+#define STM32_RTC_CR_ALRAE BIT(8)
+#define STM32_RTC_CR_ALRAIE BIT(12)
+#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C)
+#define STM32_RTC_ISR_ALRAWF BIT(0)
+#define STM32_RTC_ISR_RSF BIT(5)
+#define STM32_RTC_ISR_INITF BIT(6)
+#define STM32_RTC_ISR_INIT BIT(7)
+#define STM32_RTC_ISR_ALRAF BIT(8)
+#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10)
+#define STM32_RTC_PRER_A_MASK (0x7f << 16)
+#define STM32_RTC_PRER_S_MASK (0x7fff << 0)
+#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14)
+#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18)
+#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C)
+#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20)
+#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24)
+#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28)
+#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30)
+#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34)
+#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40)
+#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44)
+#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
+
+#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n)
+#define STM32_BKP_BYTES 64
 
 /* --- SPI --- */
 
@@ -495,15 +489,15 @@ struct stm32_spi_regs {
 	uint16_t _pad0;
 	uint16_t cr2;
 	uint16_t _pad1;
-	unsigned sr;
+	unsigned int sr;
 	uint8_t dr;
 	uint8_t _pad2;
 	uint16_t _pad3;
-	unsigned crcpr;
-	unsigned rxcrcr;
-	unsigned txcrcr;
-	unsigned i2scfgr;	/* STM32L only */
-	unsigned i2spr;		/* STM32L only */
+	unsigned int crcpr;
+	unsigned int rxcrcr;
+	unsigned int txcrcr;
+	unsigned int i2scfgr; /* STM32L only */
+	unsigned int i2spr; /* STM32L only */
 };
 /* Must be volatile, or compiler optimizes out repeated accesses */
 typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
@@ -513,125 +507,124 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
 #define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE)
 #define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE)
 
-#define STM32_SPI_CR1_BIDIMODE		BIT(15)
-#define STM32_SPI_CR1_BIDIOE		BIT(14)
-#define STM32_SPI_CR1_CRCEN		BIT(13)
-#define STM32_SPI_CR1_SSM		BIT(9)
-#define STM32_SPI_CR1_SSI		BIT(8)
-#define STM32_SPI_CR1_LSBFIRST		BIT(7)
-#define STM32_SPI_CR1_SPE		BIT(6)
-#define STM32_SPI_CR1_BR_DIV64R		(5 << 3)
-#define STM32_SPI_CR1_BR_DIV4R		BIT(3)
-#define STM32_SPI_CR1_MSTR		BIT(2)
-#define STM32_SPI_CR1_CPOL		BIT(1)
-#define STM32_SPI_CR1_CPHA		BIT(0)
-#define STM32_SPI_CR2_FRXTH		BIT(12)
-#define STM32_SPI_CR2_DATASIZE(n)	(((n) - 1) << 8)
-#define STM32_SPI_CR2_TXEIE		BIT(7)
-#define STM32_SPI_CR2_RXNEIE		BIT(6)
-#define STM32_SPI_CR2_NSSP		BIT(3)
-#define STM32_SPI_CR2_SSOE		BIT(2)
-#define STM32_SPI_CR2_TXDMAEN		BIT(1)
-#define STM32_SPI_CR2_RXDMAEN		BIT(0)
-
-#define STM32_SPI_SR_RXNE		BIT(0)
-#define STM32_SPI_SR_TXE		BIT(1)
-#define STM32_SPI_SR_CRCERR		BIT(4)
-#define STM32_SPI_SR_BSY		BIT(7)
-#define STM32_SPI_SR_FRLVL		(3 << 9)
-#define STM32_SPI_SR_FTLVL		(3 << 11)
+#define STM32_SPI_CR1_BIDIMODE BIT(15)
+#define STM32_SPI_CR1_BIDIOE BIT(14)
+#define STM32_SPI_CR1_CRCEN BIT(13)
+#define STM32_SPI_CR1_SSM BIT(9)
+#define STM32_SPI_CR1_SSI BIT(8)
+#define STM32_SPI_CR1_LSBFIRST BIT(7)
+#define STM32_SPI_CR1_SPE BIT(6)
+#define STM32_SPI_CR1_BR_DIV64R (5 << 3)
+#define STM32_SPI_CR1_BR_DIV4R BIT(3)
+#define STM32_SPI_CR1_MSTR BIT(2)
+#define STM32_SPI_CR1_CPOL BIT(1)
+#define STM32_SPI_CR1_CPHA BIT(0)
+#define STM32_SPI_CR2_FRXTH BIT(12)
+#define STM32_SPI_CR2_DATASIZE(n) (((n)-1) << 8)
+#define STM32_SPI_CR2_TXEIE BIT(7)
+#define STM32_SPI_CR2_RXNEIE BIT(6)
+#define STM32_SPI_CR2_NSSP BIT(3)
+#define STM32_SPI_CR2_SSOE BIT(2)
+#define STM32_SPI_CR2_TXDMAEN BIT(1)
+#define STM32_SPI_CR2_RXDMAEN BIT(0)
+
+#define STM32_SPI_SR_RXNE BIT(0)
+#define STM32_SPI_SR_TXE BIT(1)
+#define STM32_SPI_SR_CRCERR BIT(4)
+#define STM32_SPI_SR_BSY BIT(7)
+#define STM32_SPI_SR_FRLVL (3 << 9)
+#define STM32_SPI_SR_FTLVL (3 << 11)
 /* --- Debug --- */
-#define STM32_DBGMCU_APB1FZ         REG32(STM32_DBGMCU_BASE + 0x08)
-#define STM32_DBGMCU_APB2FZ         REG32(STM32_DBGMCU_BASE + 0x0C)
+#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08)
+#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C)
 
 /* --- Flash --- */
-#define STM32_FLASH_ACR             REG32(STM32_FLASH_REGS_BASE + 0x00)
+#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00)
 #define STM32_FLASH_ACR_LATENCY_SHIFT (0)
-#define STM32_FLASH_ACR_LATENCY_MASK  (7 << STM32_FLASH_ACR_LATENCY_SHIFT)
-#define STM32_FLASH_ACR_LATENCY     BIT(0)
-#define STM32_FLASH_ACR_PRFTEN      BIT(4)
-#define STM32_FLASH_KEYR            REG32(STM32_FLASH_REGS_BASE + 0x04)
-#define  FLASH_KEYR_KEY1                0x45670123
-#define  FLASH_KEYR_KEY2                0xCDEF89AB
-
-#define STM32_FLASH_OPTKEYR         REG32(STM32_FLASH_REGS_BASE + 0x08)
-#define  FLASH_OPTKEYR_KEY1             FLASH_KEYR_KEY1
-#define  FLASH_OPTKEYR_KEY2             FLASH_KEYR_KEY2
-#define STM32_FLASH_SR              REG32(STM32_FLASH_REGS_BASE + 0x0c)
-#define  FLASH_SR_BUSY                  BIT(0)
-#define  FLASH_SR_PGERR                 BIT(2)
-#define  FLASH_SR_WRPRTERR              BIT(4)
-#define  FLASH_SR_ALL_ERR \
-	(FLASH_SR_PGERR | FLASH_SR_WRPRTERR)
-#define  FLASH_SR_EOP                   BIT(5)
-#define STM32_FLASH_CR              REG32(STM32_FLASH_REGS_BASE + 0x10)
-#define  FLASH_CR_PG                    BIT(0)
-#define  FLASH_CR_PER                   BIT(1)
-#define  FLASH_CR_OPTPG                 BIT(4)
-#define  FLASH_CR_OPTER                 BIT(5)
-#define  FLASH_CR_STRT                  BIT(6)
-#define  FLASH_CR_LOCK                  BIT(7)
-#define  FLASH_CR_OPTWRE                BIT(9)
-#define  FLASH_CR_OBL_LAUNCH            BIT(13)
-#define STM32_FLASH_OPT_LOCKED      (!(STM32_FLASH_CR & FLASH_CR_OPTWRE))
-#define STM32_FLASH_AR              REG32(STM32_FLASH_REGS_BASE + 0x14)
-#define STM32_FLASH_OBR             REG32(STM32_FLASH_REGS_BASE + 0x1c)
-#define STM32_FLASH_OBR_RDP_MASK        (3 << 1)
-#define STM32_FLASH_WRPR            REG32(STM32_FLASH_REGS_BASE + 0x20)
-
-#define STM32_OPTB_RDP_OFF              0x00
-#define STM32_OPTB_USER_OFF             0x02
-#define STM32_OPTB_WRP_OFF(n)           (0x08 + (n&3) * 2)
-#define STM32_OPTB_WRP01                0x08
-#define STM32_OPTB_WRP23                0x0c
-
-#define STM32_OPTB_COMPL_SHIFT      8
+#define STM32_FLASH_ACR_LATENCY_MASK (7 << STM32_FLASH_ACR_LATENCY_SHIFT)
+#define STM32_FLASH_ACR_LATENCY BIT(0)
+#define STM32_FLASH_ACR_PRFTEN BIT(4)
+#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x04)
+#define FLASH_KEYR_KEY1 0x45670123
+#define FLASH_KEYR_KEY2 0xCDEF89AB
+
+#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x08)
+#define FLASH_OPTKEYR_KEY1 FLASH_KEYR_KEY1
+#define FLASH_OPTKEYR_KEY2 FLASH_KEYR_KEY2
+#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x0c)
+#define FLASH_SR_BUSY BIT(0)
+#define FLASH_SR_PGERR BIT(2)
+#define FLASH_SR_WRPRTERR BIT(4)
+#define FLASH_SR_ALL_ERR (FLASH_SR_PGERR | FLASH_SR_WRPRTERR)
+#define FLASH_SR_EOP BIT(5)
+#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x10)
+#define FLASH_CR_PG BIT(0)
+#define FLASH_CR_PER BIT(1)
+#define FLASH_CR_OPTPG BIT(4)
+#define FLASH_CR_OPTER BIT(5)
+#define FLASH_CR_STRT BIT(6)
+#define FLASH_CR_LOCK BIT(7)
+#define FLASH_CR_OPTWRE BIT(9)
+#define FLASH_CR_OBL_LAUNCH BIT(13)
+#define STM32_FLASH_OPT_LOCKED (!(STM32_FLASH_CR & FLASH_CR_OPTWRE))
+#define STM32_FLASH_AR REG32(STM32_FLASH_REGS_BASE + 0x14)
+#define STM32_FLASH_OBR REG32(STM32_FLASH_REGS_BASE + 0x1c)
+#define STM32_FLASH_OBR_RDP_MASK (3 << 1)
+#define STM32_FLASH_WRPR REG32(STM32_FLASH_REGS_BASE + 0x20)
+
+#define STM32_OPTB_RDP_OFF 0x00
+#define STM32_OPTB_USER_OFF 0x02
+#define STM32_OPTB_WRP_OFF(n) (0x08 + (n & 3) * 2)
+#define STM32_OPTB_WRP01 0x08
+#define STM32_OPTB_WRP23 0x0c
+
+#define STM32_OPTB_COMPL_SHIFT 8
 
 /* --- External Interrupts --- */
-#define STM32_EXTI_IMR              REG32(STM32_EXTI_BASE + 0x00)
-#define STM32_EXTI_EMR              REG32(STM32_EXTI_BASE + 0x04)
-#define STM32_EXTI_RTSR             REG32(STM32_EXTI_BASE + 0x08)
-#define STM32_EXTI_FTSR             REG32(STM32_EXTI_BASE + 0x0c)
-#define STM32_EXTI_SWIER            REG32(STM32_EXTI_BASE + 0x10)
-#define STM32_EXTI_PR               REG32(STM32_EXTI_BASE + 0x14)
+#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00)
+#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04)
+#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08)
+#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c)
+#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10)
+#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14)
 
 #define EXTI_RTC_ALR_EVENT BIT(17)
 
 /* --- ADC --- */
 #ifdef CHIP_VARIANT_STM32F373
-#define STM32_ADC_SR               REG32(STM32_ADC1_BASE + 0x00)
-#define STM32_ADC_CR1              REG32(STM32_ADC1_BASE + 0x04)
-#define STM32_ADC_CR2              REG32(STM32_ADC1_BASE + 0x08)
-#define STM32_ADC_CR2_ADON         BIT(0)
-#define STM32_ADC_CR2_CONT         BIT(1)
-#define STM32_ADC_CR2_CAL          BIT(2)
-#define STM32_ADC_CR2_RSTCAL       BIT(3)
-#define STM32_ADC_CR2_ALIGN        BIT(11)
-#define STM32_ADC_CR2_SWSTART      BIT(30)
-#define STM32_ADC_SMPR1            REG32(STM32_ADC1_BASE + 0x0C)
-#define STM32_ADC_SMPR2            REG32(STM32_ADC1_BASE + 0x10)
-#define STM32_ADC_JOFR(n)          REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4)
-#define STM32_ADC_HTR              REG32(STM32_ADC1_BASE + 0x24)
-#define STM32_ADC_LTR              REG32(STM32_ADC1_BASE + 0x28)
-#define STM32_ADC_SQR(n)           REG32(STM32_ADC1_BASE + 0x28 + ((n)&3) * 4)
-#define STM32_ADC_SQR1             REG32(STM32_ADC1_BASE + 0x2C)
-#define STM32_ADC_SQR2             REG32(STM32_ADC1_BASE + 0x30)
-#define STM32_ADC_SQR3             REG32(STM32_ADC1_BASE + 0x34)
-#define STM32_ADC_JSQR             REG32(STM32_ADC1_BASE + 0x38)
-#define STM32_ADC_JDR(n)           REG32(STM32_ADC1_BASE + 0x3C + ((n)&3) * 4)
-#define STM32_ADC_DR               REG32(STM32_ADC1_BASE + 0x4C)
+#define STM32_ADC_SR REG32(STM32_ADC1_BASE + 0x00)
+#define STM32_ADC_CR1 REG32(STM32_ADC1_BASE + 0x04)
+#define STM32_ADC_CR2 REG32(STM32_ADC1_BASE + 0x08)
+#define STM32_ADC_CR2_ADON BIT(0)
+#define STM32_ADC_CR2_CONT BIT(1)
+#define STM32_ADC_CR2_CAL BIT(2)
+#define STM32_ADC_CR2_RSTCAL BIT(3)
+#define STM32_ADC_CR2_ALIGN BIT(11)
+#define STM32_ADC_CR2_SWSTART BIT(30)
+#define STM32_ADC_SMPR1 REG32(STM32_ADC1_BASE + 0x0C)
+#define STM32_ADC_SMPR2 REG32(STM32_ADC1_BASE + 0x10)
+#define STM32_ADC_JOFR(n) REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4)
+#define STM32_ADC_HTR REG32(STM32_ADC1_BASE + 0x24)
+#define STM32_ADC_LTR REG32(STM32_ADC1_BASE + 0x28)
+#define STM32_ADC_SQR(n) REG32(STM32_ADC1_BASE + 0x28 + ((n)&3) * 4)
+#define STM32_ADC_SQR1 REG32(STM32_ADC1_BASE + 0x2C)
+#define STM32_ADC_SQR2 REG32(STM32_ADC1_BASE + 0x30)
+#define STM32_ADC_SQR3 REG32(STM32_ADC1_BASE + 0x34)
+#define STM32_ADC_JSQR REG32(STM32_ADC1_BASE + 0x38)
+#define STM32_ADC_JDR(n) REG32(STM32_ADC1_BASE + 0x3C + ((n)&3) * 4)
+#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x4C)
 #endif
 
 /* --- Comparators --- */
-#define STM32_COMP_CSR              REG32(STM32_COMP_BASE + 0x1C)
+#define STM32_COMP_CSR REG32(STM32_COMP_BASE + 0x1C)
 
-#define STM32_COMP_CMP2LOCK            BIT(31)
-#define STM32_COMP_CMP2OUT             BIT(30)
-#define STM32_COMP_CMP2HYST_HI         (3 << 28)
-#define STM32_COMP_CMP2HYST_MED        (2 << 28)
-#define STM32_COMP_CMP2HYST_LOW        (1 << 28)
-#define STM32_COMP_CMP2HYST_NO         (0 << 28)
-#define STM32_COMP_CMP2POL             BIT(27)
+#define STM32_COMP_CMP2LOCK BIT(31)
+#define STM32_COMP_CMP2OUT BIT(30)
+#define STM32_COMP_CMP2HYST_HI (3 << 28)
+#define STM32_COMP_CMP2HYST_MED (2 << 28)
+#define STM32_COMP_CMP2HYST_LOW (1 << 28)
+#define STM32_COMP_CMP2HYST_NO (0 << 28)
+#define STM32_COMP_CMP2POL BIT(27)
 
 #define STM32_COMP_CMP2OUTSEL_TIM3_OCR (7 << 24)
 #define STM32_COMP_CMP2OUTSEL_TIM3_IC1 (6 << 24)
@@ -646,32 +639,32 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
 #define STM32_COMP_CMP2OUTSEL_TIM1_IC1 (2 << 24)
 #define STM32_COMP_CMP2OUTSEL_TIM1_BRK (1 << 24)
 #endif
-#define STM32_COMP_CMP2OUTSEL_NONE     (0 << 24)
-#define STM32_COMP_WNDWEN              BIT(23)
-
-#define STM32_COMP_CMP2INSEL_MASK      (7 << 20)
-#define STM32_COMP_CMP2INSEL_INM7      (6 << 20) /* STM32F373 only */
-#define STM32_COMP_CMP2INSEL_INM6      (6 << 20)
-#define STM32_COMP_CMP2INSEL_INM5      (5 << 20)
-#define STM32_COMP_CMP2INSEL_INM4      (4 << 20)
-#define STM32_COMP_CMP2INSEL_VREF      (3 << 20)
-#define STM32_COMP_CMP2INSEL_VREF34    (2 << 20)
-#define STM32_COMP_CMP2INSEL_VREF12    (1 << 20)
-#define STM32_COMP_CMP2INSEL_VREF14    (0 << 20)
-
-#define STM32_COMP_CMP2MODE_VLSPEED    (3 << 18)
-#define STM32_COMP_CMP2MODE_LSPEED     (2 << 18)
-#define STM32_COMP_CMP2MODE_MSPEED     (1 << 18)
-#define STM32_COMP_CMP2MODE_HSPEED     (0 << 18)
-#define STM32_COMP_CMP2EN              BIT(16)
-
-#define STM32_COMP_CMP1LOCK            BIT(15)
-#define STM32_COMP_CMP1OUT             BIT(14)
-#define STM32_COMP_CMP1HYST_HI         (3 << 12)
-#define STM32_COMP_CMP1HYST_MED        (2 << 12)
-#define STM32_COMP_CMP1HYST_LOW        (1 << 12)
-#define STM32_COMP_CMP1HYST_NO         (0 << 12)
-#define STM32_COMP_CMP1POL             BIT(11)
+#define STM32_COMP_CMP2OUTSEL_NONE (0 << 24)
+#define STM32_COMP_WNDWEN BIT(23)
+
+#define STM32_COMP_CMP2INSEL_MASK (7 << 20)
+#define STM32_COMP_CMP2INSEL_INM7 (6 << 20) /* STM32F373 only */
+#define STM32_COMP_CMP2INSEL_INM6 (6 << 20)
+#define STM32_COMP_CMP2INSEL_INM5 (5 << 20)
+#define STM32_COMP_CMP2INSEL_INM4 (4 << 20)
+#define STM32_COMP_CMP2INSEL_VREF (3 << 20)
+#define STM32_COMP_CMP2INSEL_VREF34 (2 << 20)
+#define STM32_COMP_CMP2INSEL_VREF12 (1 << 20)
+#define STM32_COMP_CMP2INSEL_VREF14 (0 << 20)
+
+#define STM32_COMP_CMP2MODE_VLSPEED (3 << 18)
+#define STM32_COMP_CMP2MODE_LSPEED (2 << 18)
+#define STM32_COMP_CMP2MODE_MSPEED (1 << 18)
+#define STM32_COMP_CMP2MODE_HSPEED (0 << 18)
+#define STM32_COMP_CMP2EN BIT(16)
+
+#define STM32_COMP_CMP1LOCK BIT(15)
+#define STM32_COMP_CMP1OUT BIT(14)
+#define STM32_COMP_CMP1HYST_HI (3 << 12)
+#define STM32_COMP_CMP1HYST_MED (2 << 12)
+#define STM32_COMP_CMP1HYST_LOW (1 << 12)
+#define STM32_COMP_CMP1HYST_NO (0 << 12)
+#define STM32_COMP_CMP1POL BIT(11)
 
 #ifdef CHIP_VARIANT_STM32F373
 #define STM32_COMP_CMP1OUTSEL_TIM5_OCR (7 << 8)
@@ -690,25 +683,24 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
 #define STM32_COMP_CMP1OUTSEL_TIM1_IC1 (2 << 8)
 #define STM32_COMP_CMP1OUTSEL_TIM1_BRK (1 << 8)
 #endif
-#define STM32_COMP_CMP1OUTSEL_NONE     (0 << 8)
-
-#define STM32_COMP_CMP1INSEL_MASK      (7 << 4)
-#define STM32_COMP_CMP1INSEL_INM7      (7 << 4) /* STM32F373 only */
-#define STM32_COMP_CMP1INSEL_INM6      (6 << 4)
-#define STM32_COMP_CMP1INSEL_INM5      (5 << 4)
-#define STM32_COMP_CMP1INSEL_INM4      (4 << 4)
-#define STM32_COMP_CMP1INSEL_VREF      (3 << 4)
-#define STM32_COMP_CMP1INSEL_VREF34    (2 << 4)
-#define STM32_COMP_CMP1INSEL_VREF12    (1 << 4)
-#define STM32_COMP_CMP1INSEL_VREF14    (0 << 4)
-
-#define STM32_COMP_CMP1MODE_VLSPEED    (3 << 2)
-#define STM32_COMP_CMP1MODE_LSPEED     (2 << 2)
-#define STM32_COMP_CMP1MODE_MSPEED     (1 << 2)
-#define STM32_COMP_CMP1MODE_HSPEED     (0 << 2)
-#define STM32_COMP_CMP1SW1             BIT(1)
-#define STM32_COMP_CMP1EN              BIT(0)
-
+#define STM32_COMP_CMP1OUTSEL_NONE (0 << 8)
+
+#define STM32_COMP_CMP1INSEL_MASK (7 << 4)
+#define STM32_COMP_CMP1INSEL_INM7 (7 << 4) /* STM32F373 only */
+#define STM32_COMP_CMP1INSEL_INM6 (6 << 4)
+#define STM32_COMP_CMP1INSEL_INM5 (5 << 4)
+#define STM32_COMP_CMP1INSEL_INM4 (4 << 4)
+#define STM32_COMP_CMP1INSEL_VREF (3 << 4)
+#define STM32_COMP_CMP1INSEL_VREF34 (2 << 4)
+#define STM32_COMP_CMP1INSEL_VREF12 (1 << 4)
+#define STM32_COMP_CMP1INSEL_VREF14 (0 << 4)
+
+#define STM32_COMP_CMP1MODE_VLSPEED (3 << 2)
+#define STM32_COMP_CMP1MODE_LSPEED (2 << 2)
+#define STM32_COMP_CMP1MODE_MSPEED (1 << 2)
+#define STM32_COMP_CMP1MODE_HSPEED (0 << 2)
+#define STM32_COMP_CMP1SW1 BIT(1)
+#define STM32_COMP_CMP1EN BIT(0)
 
 /* --- DMA --- */
 
@@ -779,11 +771,11 @@ enum dma_channel {
 
 /* Registers for a single channel of the DMA controller */
 struct stm32_dma_chan {
-	uint32_t	ccr;		/* Control */
-	uint32_t	cndtr;		/* Number of data to transfer */
-	uint32_t	cpar;		/* Peripheral address */
-	uint32_t	cmar;		/* Memory address */
-	uint32_t	reserved;
+	uint32_t ccr; /* Control */
+	uint32_t cndtr; /* Number of data to transfer */
+	uint32_t cpar; /* Peripheral address */
+	uint32_t cmar; /* Memory address */
+	uint32_t reserved;
 };
 
 /* Always use stm32_dma_chan_t so volatile keyword is included! */
@@ -794,8 +786,8 @@ typedef stm32_dma_chan_t dma_chan_t;
 
 /* Registers for the DMA controller */
 struct stm32_dma_regs {
-	uint32_t	isr;
-	uint32_t	ifcr;
+	uint32_t isr;
+	uint32_t ifcr;
 	stm32_dma_chan_t chan[STM32_DMAC_COUNT];
 };
 
@@ -804,210 +796,130 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
 
 #define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE)
 
-
-#define STM32_DMA_CCR_CHANNEL(channel)		 (0)
+#define STM32_DMA_CCR_CHANNEL(channel) (0)
 
 #define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE)
 #define STM32_DMA_REGS(channel) \
 	((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_REGS : STM32_DMA2_REGS)
-#define STM32_DMA_CSELR(channel) \
-	REG32(((channel) < STM32_DMAC_PER_CTLR ? \
-			STM32_DMA1_BASE : STM32_DMA2_BASE)  + 0xA8)
+#define STM32_DMA_CSELR(channel)                                    \
+	REG32(((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_BASE :  \
+						 STM32_DMA2_BASE) + \
+	      0xA8)
 
 /* Bits for DMA controller regs (isr and ifcr) */
-#define STM32_DMA_CH_OFFSET(channel)   (4 * ((channel) % STM32_DMAC_PER_CTLR))
+#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR))
 #define STM32_DMA_ISR_MASK(channel, mask) \
 	((mask) << STM32_DMA_CH_OFFSET(channel))
-#define STM32_DMA_ISR_GIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(0))
-#define STM32_DMA_ISR_TCIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(1))
-#define STM32_DMA_ISR_HTIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(2))
-#define STM32_DMA_ISR_TEIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(3))
-#define STM32_DMA_ISR_ALL(channel)	STM32_DMA_ISR_MASK(channel, 0x0f)
-
-#define STM32_DMA_GIF                   BIT(0)
-#define STM32_DMA_TCIF                  BIT(1)
-#define STM32_DMA_HTIF                  BIT(2)
-#define STM32_DMA_TEIF                  BIT(3)
-#define STM32_DMA_ALL                   0xf
-
-#define STM32_DMA_GET_ISR(channel)      \
-	((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_ISR(channel, val) \
-	(STM32_DMA_REGS(channel)->isr = \
-	((STM32_DMA_REGS(channel)->isr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-#define STM32_DMA_GET_IFCR(channel)      \
-	((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_IFCR(channel, val) \
-	(STM32_DMA_REGS(channel)->ifcr = \
-	((STM32_DMA_REGS(channel)->ifcr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-
+#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0))
+#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1))
+#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2))
+#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3))
+#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f)
+
+#define STM32_DMA_GIF BIT(0)
+#define STM32_DMA_TCIF BIT(1)
+#define STM32_DMA_HTIF BIT(2)
+#define STM32_DMA_TEIF BIT(3)
+#define STM32_DMA_ALL 0xf
+
+#define STM32_DMA_GET_ISR(channel)                                        \
+	((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) & \
+	 STM32_DMA_ALL)
+#define STM32_DMA_SET_ISR(channel, val)                                \
+	(STM32_DMA_REGS(channel)->isr =                                \
+		 ((STM32_DMA_REGS(channel)->isr &                      \
+		   ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
+		  (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
+#define STM32_DMA_GET_IFCR(channel)                                        \
+	((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) & \
+	 STM32_DMA_ALL)
+#define STM32_DMA_SET_IFCR(channel, val)                               \
+	(STM32_DMA_REGS(channel)->ifcr =                               \
+		 ((STM32_DMA_REGS(channel)->ifcr &                     \
+		   ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
+		  (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
 
 /* Bits for DMA channel regs */
-#define STM32_DMA_CCR_EN		BIT(0)
-#define STM32_DMA_CCR_TCIE		BIT(1)
-#define STM32_DMA_CCR_HTIE		BIT(2)
-#define STM32_DMA_CCR_TEIE		BIT(3)
-#define STM32_DMA_CCR_DIR		BIT(4)
-#define STM32_DMA_CCR_CIRC		BIT(5)
-#define STM32_DMA_CCR_PINC		BIT(6)
-#define STM32_DMA_CCR_MINC		BIT(7)
-#define STM32_DMA_CCR_PSIZE_8_BIT	(0 << 8)
-#define STM32_DMA_CCR_PSIZE_16_BIT	(1 << 8)
-#define STM32_DMA_CCR_PSIZE_32_BIT	(2 << 8)
-#define STM32_DMA_CCR_MSIZE_8_BIT	(0 << 10)
-#define STM32_DMA_CCR_MSIZE_16_BIT	(1 << 10)
-#define STM32_DMA_CCR_MSIZE_32_BIT	(2 << 10)
-#define STM32_DMA_CCR_PL_LOW		(0 << 12)
-#define STM32_DMA_CCR_PL_MEDIUM		(1 << 12)
-#define STM32_DMA_CCR_PL_HIGH		(2 << 12)
-#define STM32_DMA_CCR_PL_VERY_HIGH	(3 << 12)
-#define STM32_DMA_CCR_MEM2MEM		BIT(14)
-
+#define STM32_DMA_CCR_EN BIT(0)
+#define STM32_DMA_CCR_TCIE BIT(1)
+#define STM32_DMA_CCR_HTIE BIT(2)
+#define STM32_DMA_CCR_TEIE BIT(3)
+#define STM32_DMA_CCR_DIR BIT(4)
+#define STM32_DMA_CCR_CIRC BIT(5)
+#define STM32_DMA_CCR_PINC BIT(6)
+#define STM32_DMA_CCR_MINC BIT(7)
+#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8)
+#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8)
+#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8)
+#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10)
+#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10)
+#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10)
+#define STM32_DMA_CCR_PL_LOW (0 << 12)
+#define STM32_DMA_CCR_PL_MEDIUM (1 << 12)
+#define STM32_DMA_CCR_PL_HIGH (2 << 12)
+#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12)
+#define STM32_DMA_CCR_MEM2MEM BIT(14)
 
 /* --- CRC --- */
-#define STM32_CRC_DR                REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR32              REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR16              REG16(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR8               REG8(STM32_CRC_BASE + 0x0)
-
-#define STM32_CRC_IDR               REG32(STM32_CRC_BASE + 0x4)
-#define STM32_CRC_CR                REG32(STM32_CRC_BASE + 0x8)
-#define STM32_CRC_INIT              REG32(STM32_CRC_BASE + 0x10)
-#define STM32_CRC_POL               REG32(STM32_CRC_BASE + 0x14)
-
-#define STM32_CRC_CR_RESET          BIT(0)
-#define STM32_CRC_CR_POLYSIZE_32    (0 << 3)
-#define STM32_CRC_CR_POLYSIZE_16    (1 << 3)
-#define STM32_CRC_CR_POLYSIZE_8     (2 << 3)
-#define STM32_CRC_CR_POLYSIZE_7     (3 << 3)
-#define STM32_CRC_CR_REV_IN_BYTE    (1 << 5)
-#define STM32_CRC_CR_REV_IN_HWORD   (2 << 5)
-#define STM32_CRC_CR_REV_IN_WORD    (3 << 5)
-#define STM32_CRC_CR_REV_OUT        BIT(7)
+#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0)
+
+#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4)
+#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8)
+#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10)
+#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14)
+
+#define STM32_CRC_CR_RESET BIT(0)
+#define STM32_CRC_CR_POLYSIZE_32 (0 << 3)
+#define STM32_CRC_CR_POLYSIZE_16 (1 << 3)
+#define STM32_CRC_CR_POLYSIZE_8 (2 << 3)
+#define STM32_CRC_CR_POLYSIZE_7 (3 << 3)
+#define STM32_CRC_CR_REV_IN_BYTE (1 << 5)
+#define STM32_CRC_CR_REV_IN_HWORD (2 << 5)
+#define STM32_CRC_CR_REV_IN_WORD (3 << 5)
+#define STM32_CRC_CR_REV_OUT BIT(7)
 
 /* --- PMSE --- */
-#define STM32_PMSE_ARCR             REG32(STM32_PMSE_BASE + 0x0)
-#define STM32_PMSE_ACCR             REG32(STM32_PMSE_BASE + 0x4)
-#define STM32_PMSE_CR               REG32(STM32_PMSE_BASE + 0x8)
-#define STM32_PMSE_CRTDR            REG32(STM32_PMSE_BASE + 0x14)
-#define STM32_PMSE_IER              REG32(STM32_PMSE_BASE + 0x18)
-#define STM32_PMSE_SR               REG32(STM32_PMSE_BASE + 0x1c)
-#define STM32_PMSE_IFCR             REG32(STM32_PMSE_BASE + 0x20)
-#define STM32_PMSE_PxPMR(x)         REG32(STM32_PMSE_BASE + 0x2c + (x) * 4)
-#define STM32_PMSE_PAPMR            REG32(STM32_PMSE_BASE + 0x2c)
-#define STM32_PMSE_PBPMR            REG32(STM32_PMSE_BASE + 0x30)
-#define STM32_PMSE_PCPMR            REG32(STM32_PMSE_BASE + 0x34)
-#define STM32_PMSE_PDPMR            REG32(STM32_PMSE_BASE + 0x38)
-#define STM32_PMSE_PEPMR            REG32(STM32_PMSE_BASE + 0x3c)
-#define STM32_PMSE_PFPMR            REG32(STM32_PMSE_BASE + 0x40)
-#define STM32_PMSE_PGPMR            REG32(STM32_PMSE_BASE + 0x44)
-#define STM32_PMSE_PHPMR            REG32(STM32_PMSE_BASE + 0x48)
-#define STM32_PMSE_PIPMR            REG32(STM32_PMSE_BASE + 0x4c)
-#define STM32_PMSE_MRCR             REG32(STM32_PMSE_BASE + 0x100)
-#define STM32_PMSE_MCCR             REG32(STM32_PMSE_BASE + 0x104)
-
-/* --- USB --- */
-#define STM32_USB_EP(n)            REG16(STM32_USB_FS_BASE + (n) * 4)
-
-#define STM32_USB_CNTR             REG16(STM32_USB_FS_BASE + 0x40)
-
-#define STM32_USB_CNTR_FRES	    BIT(0)
-#define STM32_USB_CNTR_PDWN	    BIT(1)
-#define STM32_USB_CNTR_LP_MODE	    BIT(2)
-#define STM32_USB_CNTR_FSUSP	    BIT(3)
-#define STM32_USB_CNTR_RESUME	    BIT(4)
-#define STM32_USB_CNTR_L1RESUME	    BIT(5)
-#define STM32_USB_CNTR_L1REQM	    BIT(7)
-#define STM32_USB_CNTR_ESOFM	    BIT(8)
-#define STM32_USB_CNTR_SOFM	    BIT(9)
-#define STM32_USB_CNTR_RESETM	    BIT(10)
-#define STM32_USB_CNTR_SUSPM	    BIT(11)
-#define STM32_USB_CNTR_WKUPM	    BIT(12)
-#define STM32_USB_CNTR_ERRM	    BIT(13)
-#define STM32_USB_CNTR_PMAOVRM	    BIT(14)
-#define STM32_USB_CNTR_CTRM	    BIT(15)
-
-#define STM32_USB_ISTR             REG16(STM32_USB_FS_BASE + 0x44)
-
-#define STM32_USB_ISTR_EP_ID_MASK   (0x000f)
-#define STM32_USB_ISTR_DIR	    BIT(4)
-#define STM32_USB_ISTR_L1REQ	    BIT(7)
-#define STM32_USB_ISTR_ESOF	    BIT(8)
-#define STM32_USB_ISTR_SOF	    BIT(9)
-#define STM32_USB_ISTR_RESET	    BIT(10)
-#define STM32_USB_ISTR_SUSP	    BIT(11)
-#define STM32_USB_ISTR_WKUP	    BIT(12)
-#define STM32_USB_ISTR_ERR	    BIT(13)
-#define STM32_USB_ISTR_PMAOVR	    BIT(14)
-#define STM32_USB_ISTR_CTR	    BIT(15)
-
-#define STM32_USB_FNR              REG16(STM32_USB_FS_BASE + 0x48)
-
-#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14)
-#define STM32_USB_FNR_RXDP_RXDM_MASK  (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT)
-
-#define STM32_USB_DADDR            REG16(STM32_USB_FS_BASE + 0x4C)
-#define STM32_USB_BTABLE           REG16(STM32_USB_FS_BASE + 0x50)
-#define STM32_USB_LPMCSR           REG16(STM32_USB_FS_BASE + 0x54)
-#define STM32_USB_BCDR             REG16(STM32_USB_FS_BASE + 0x58)
-
-#define STM32_USB_BCDR_BCDEN	    BIT(0)
-#define STM32_USB_BCDR_DCDEN	    BIT(1)
-#define STM32_USB_BCDR_PDEN	    BIT(2)
-#define STM32_USB_BCDR_SDEN	    BIT(3)
-#define STM32_USB_BCDR_DCDET	    BIT(4)
-#define STM32_USB_BCDR_PDET	    BIT(5)
-#define STM32_USB_BCDR_SDET	    BIT(6)
-#define STM32_USB_BCDR_PS2DET	    BIT(7)
-
-#define EP_MASK     0x0F0F
-#define EP_TX_DTOG  0x0040
-#define EP_TX_MASK  0x0030
-#define EP_TX_VALID 0x0030
-#define EP_TX_NAK   0x0020
-#define EP_TX_STALL 0x0010
-#define EP_TX_DISAB 0x0000
-#define EP_RX_DTOG  0x4000
-#define EP_RX_MASK  0x3000
-#define EP_RX_VALID 0x3000
-#define EP_RX_NAK   0x2000
-#define EP_RX_STALL 0x1000
-#define EP_RX_DISAB 0x0000
-
-#define EP_STATUS_OUT 0x0100
-
-#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK)
-#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID)
-
-#define STM32_TOGGLE_EP(n, mask, val, flags) \
-	STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \
-			^ (val)) | (flags))
+#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0)
+#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4)
+#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8)
+#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14)
+#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18)
+#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c)
+#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20)
+#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x)*4)
+#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c)
+#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30)
+#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34)
+#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38)
+#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c)
+#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40)
+#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44)
+#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48)
+#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c)
+#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100)
+#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104)
 
 /* --- TRNG --- */
-#define STM32_RNG_CR                REG32(STM32_RNG_BASE + 0x0)
-#define STM32_RNG_CR_RNGEN          BIT(2)
-#define STM32_RNG_CR_IE             BIT(3)
-#define STM32_RNG_CR_CED            BIT(5)
-#define STM32_RNG_SR                REG32(STM32_RNG_BASE + 0x4)
-#define STM32_RNG_SR_DRDY           BIT(0)
-#define STM32_RNG_DR                REG32(STM32_RNG_BASE + 0x8)
+#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0)
+#define STM32_RNG_CR_RNGEN BIT(2)
+#define STM32_RNG_CR_IE BIT(3)
+#define STM32_RNG_CR_CED BIT(5)
+#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4)
+#define STM32_RNG_SR_DRDY BIT(0)
+#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8)
 
 /* --- AXI interconnect --- */
 
 /* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */
-#define STM32_AXI_TARG_FN_MOD(x)    REG32(STM32_GPV_BASE + 0x1108 + \
-					  0x1000 * (x))
-#define  WRITE_ISS_OVERRIDE         BIT(1)
-#define  READ_ISS_OVERRIDE          BIT(0)
+#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + 0x1000 * (x))
+#define WRITE_ISS_OVERRIDE BIT(1)
+#define READ_ISS_OVERRIDE BIT(0)
 
 /* --- MISC --- */
-#define STM32_UNIQUE_ID_ADDRESS     REG32_ADDR(STM32_UNIQUE_ID_BASE)
-#define STM32_UNIQUE_ID_LENGTH      (3 * 4)
+#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE)
+#define STM32_UNIQUE_ID_LENGTH (3 * 4)
 
 #endif /* !__ASSEMBLER__ */
diff --git a/chip/stm32/registers-stm32f4.h b/chip/stm32/registers-stm32f4.h
index 4e81c11226..5db9b5b9e6 100644
--- a/chip/stm32/registers-stm32f4.h
+++ b/chip/stm32/registers-stm32f4.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,104 +22,103 @@
 #endif
 
 /* --- IRQ numbers --- */
-#define STM32_IRQ_WWDG             0
-#define STM32_IRQ_PVD              1
-#define STM32_IRQ_TAMPER_STAMP     2
-#define STM32_IRQ_RTC_WAKEUP       3
-#define STM32_IRQ_FLASH            4
-#define STM32_IRQ_RCC              5
-#define STM32_IRQ_EXTI0            6
-#define STM32_IRQ_EXTI1            7
-#define STM32_IRQ_EXTI2            8
-#define STM32_IRQ_EXTI3            9
-#define STM32_IRQ_EXTI4           10
-#define STM32_IRQ_DMA_CHANNEL_1   11
-#define STM32_IRQ_DMA_CHANNEL_2   12
-#define STM32_IRQ_DMA_CHANNEL_3   13
-#define STM32_IRQ_DMA_CHANNEL_4   14
-#define STM32_IRQ_DMA_CHANNEL_5   15
-#define STM32_IRQ_DMA_CHANNEL_6   16
-#define STM32_IRQ_DMA_CHANNEL_7   17
-#define STM32_IRQ_USB_HP          19
-#define STM32_IRQ_USB_LP          20
-
-#define STM32_IRQ_ADC1            18 /* STM32L4 only */
-#define STM32_IRQ_CAN_TX          19 /* STM32F373 only */
-#define STM32_IRQ_USB_LP_CAN_RX   20 /* STM32F373 only */
-#define STM32_IRQ_DAC             21
-#define STM32_IRQ_CAN_RX1         21 /* STM32F373 only */
-
-#define STM32_IRQ_COMP            22
-
-#define STM32_IRQ_CAN_SCE         22 /* STM32F373 only */
-#define STM32_IRQ_EXTI9_5         23
-#define STM32_IRQ_LCD             24 /* STM32L15X only */
-#define STM32_IRQ_TIM15           24 /* STM32F373 only */
+#define STM32_IRQ_WWDG 0
+#define STM32_IRQ_PVD 1
+#define STM32_IRQ_TAMPER_STAMP 2
+#define STM32_IRQ_RTC_WAKEUP 3
+#define STM32_IRQ_FLASH 4
+#define STM32_IRQ_RCC 5
+#define STM32_IRQ_EXTI0 6
+#define STM32_IRQ_EXTI1 7
+#define STM32_IRQ_EXTI2 8
+#define STM32_IRQ_EXTI3 9
+#define STM32_IRQ_EXTI4 10
+#define STM32_IRQ_DMA_CHANNEL_1 11
+#define STM32_IRQ_DMA_CHANNEL_2 12
+#define STM32_IRQ_DMA_CHANNEL_3 13
+#define STM32_IRQ_DMA_CHANNEL_4 14
+#define STM32_IRQ_DMA_CHANNEL_5 15
+#define STM32_IRQ_DMA_CHANNEL_6 16
+#define STM32_IRQ_DMA_CHANNEL_7 17
+#define STM32_IRQ_USB_HP 19
+#define STM32_IRQ_USB_LP 20
+
+#define STM32_IRQ_ADC1 18 /* STM32L4 only */
+#define STM32_IRQ_CAN_TX 19 /* STM32F373 only */
+#define STM32_IRQ_USB_LP_CAN_RX 20 /* STM32F373 only */
+#define STM32_IRQ_DAC 21
+#define STM32_IRQ_CAN_RX1 21 /* STM32F373 only */
+
+#define STM32_IRQ_COMP 22
+
+#define STM32_IRQ_CAN_SCE 22 /* STM32F373 only */
+#define STM32_IRQ_EXTI9_5 23
+#define STM32_IRQ_LCD 24 /* STM32L15X only */
+#define STM32_IRQ_TIM15 24 /* STM32F373 only */
 #if defined(CHIP_VARIANT_STM32F412)
-#define STM32_IRQ_TIM9            24 /* STM32F412 only */
+#define STM32_IRQ_TIM9 24 /* STM32F412 only */
 #else
-#define STM32_IRQ_TIM9            25 /* STM32L15X only */
+#define STM32_IRQ_TIM9 25 /* STM32L15X only */
 #endif
-#define STM32_IRQ_TIM16           25 /* STM32F373 only */
-#define STM32_IRQ_TIM10           26 /* STM32L15X only */
-#define STM32_IRQ_TIM17           26 /* STM32F373 only */
-#define STM32_IRQ_TIM11           27 /* STM32L15X only */
-#define STM32_IRQ_TIM18_DAC2      27 /* STM32F373 only */
-#define STM32_IRQ_TIM2            28
-#define STM32_IRQ_TIM3            29
-#define STM32_IRQ_TIM4            30
-#define STM32_IRQ_I2C1_EV         31
-#define STM32_IRQ_I2C1_ER         32
-#define STM32_IRQ_I2C2_EV         33
-#define STM32_IRQ_I2C2_ER         34
-#define STM32_IRQ_SPI1            35
-#define STM32_IRQ_SPI2            36
-#define STM32_IRQ_USART1          37
-#define STM32_IRQ_USART2          38
-#define STM32_IRQ_USART3          39
-#define STM32_IRQ_EXTI15_10       40
-#define STM32_IRQ_RTC_ALARM       41
-#define STM32_IRQ_USB_FS_WAKEUP   42 /* STM32L15X */
-#define STM32_IRQ_CEC             42 /* STM32F373 only */
-#define STM32_IRQ_TIM6_BASIC      43 /* STM32L15X only */
-#define STM32_IRQ_TIM12           43 /* STM32F373 only */
-#define STM32_IRQ_TIM7_BASIC      44 /* STM32L15X only */
-#define STM32_IRQ_TIM13           44 /* STM32F373 only */
-#define STM32_IRQ_TIM14           45 /* STM32F373 only */
-#define STM32_IRQ_TIM5            50 /* STM32F373 */
-#define STM32_IRQ_SPI3            51 /* STM32F373 */
-#define STM32_IRQ_USART4          52 /* STM32F446 only */
-#define STM32_IRQ_USART5          53 /* STM32F446 only */
-#define STM32_IRQ_TIM6_DAC        54 /* STM32F373 */
-#define STM32_IRQ_TIM7            55 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL1   56 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL2   57 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL3   58 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL4   59 /* STM32F373 only */
+#define STM32_IRQ_TIM16 25 /* STM32F373 only */
+#define STM32_IRQ_TIM10 26 /* STM32L15X only */
+#define STM32_IRQ_TIM17 26 /* STM32F373 only */
+#define STM32_IRQ_TIM11 27 /* STM32L15X only */
+#define STM32_IRQ_TIM18_DAC2 27 /* STM32F373 only */
+#define STM32_IRQ_TIM2 28
+#define STM32_IRQ_TIM3 29
+#define STM32_IRQ_TIM4 30
+#define STM32_IRQ_I2C1_EV 31
+#define STM32_IRQ_I2C1_ER 32
+#define STM32_IRQ_I2C2_EV 33
+#define STM32_IRQ_I2C2_ER 34
+#define STM32_IRQ_SPI1 35
+#define STM32_IRQ_SPI2 36
+#define STM32_IRQ_USART1 37
+#define STM32_IRQ_USART2 38
+#define STM32_IRQ_USART3 39
+#define STM32_IRQ_EXTI15_10 40
+#define STM32_IRQ_RTC_ALARM 41
+#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X */
+#define STM32_IRQ_CEC 42 /* STM32F373 only */
+#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */
+#define STM32_IRQ_TIM12 43 /* STM32F373 only */
+#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */
+#define STM32_IRQ_TIM13 44 /* STM32F373 only */
+#define STM32_IRQ_TIM14 45 /* STM32F373 only */
+#define STM32_IRQ_TIM5 50 /* STM32F373 */
+#define STM32_IRQ_SPI3 51 /* STM32F373 */
+#define STM32_IRQ_USART4 52 /* STM32F446 only */
+#define STM32_IRQ_USART5 53 /* STM32F446 only */
+#define STM32_IRQ_TIM6_DAC 54 /* STM32F373 */
+#define STM32_IRQ_TIM7 55 /* STM32F373 */
+#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F373 */
+#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F373 */
+#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F373 */
+#define STM32_IRQ_DMA2_CHANNEL4 59 /* STM32F373 only */
 /* if MISC_REMAP bits are set */
-#define STM32_IRQ_DMA2_CHANNEL5   60 /* STM32F373 */
-#define STM32_IRQ_SDADC1          61 /* STM32F373 only */
-#define STM32_IRQ_SDADC2          62 /* STM32F373 only */
-#define STM32_IRQ_SDADC3          63 /* STM32F373 only */
-#define STM32_IRQ_DMA2_CHANNEL6   68 /* STM32L4 only */
-#define STM32_IRQ_DMA2_CHANNEL7   69 /* STM32L4 only */
-#define STM32_IRQ_LPUART          70 /* STM32L4 only */
-#define STM32_IRQ_USART9          70 /* STM32L4 only */
-#define STM32_IRQ_USART6          71 /* STM32F446 only */
-#define STM32_IRQ_I2C3_EV         72 /* STM32F446 only */
-#define STM32_IRQ_I2C3_ER         73 /* STM32F446 only */
-#define STM32_IRQ_USB_WAKEUP      76 /* STM32F373 only */
-#define STM32_IRQ_TIM19           78 /* STM32F373 only */
-#define STM32_IRQ_AES             79 /* STM32L4 only */
-#define STM32_IRQ_RNG             80 /* STM32L4 only */
-#define STM32_IRQ_FPU             81 /* STM32F373 only */
-
+#define STM32_IRQ_DMA2_CHANNEL5 60 /* STM32F373 */
+#define STM32_IRQ_SDADC1 61 /* STM32F373 only */
+#define STM32_IRQ_SDADC2 62 /* STM32F373 only */
+#define STM32_IRQ_SDADC3 63 /* STM32F373 only */
+#define STM32_IRQ_DMA2_CHANNEL6 68 /* STM32L4 only */
+#define STM32_IRQ_DMA2_CHANNEL7 69 /* STM32L4 only */
+#define STM32_IRQ_LPUART 70 /* STM32L4 only */
+#define STM32_IRQ_USART9 70 /* STM32L4 only */
+#define STM32_IRQ_USART6 71 /* STM32F446 only */
+#define STM32_IRQ_I2C3_EV 72 /* STM32F446 only */
+#define STM32_IRQ_I2C3_ER 73 /* STM32F446 only */
+#define STM32_IRQ_USB_WAKEUP 76 /* STM32F373 only */
+#define STM32_IRQ_TIM19 78 /* STM32F373 only */
+#define STM32_IRQ_AES 79 /* STM32L4 only */
+#define STM32_IRQ_RNG 80 /* STM32L4 only */
+#define STM32_IRQ_FPU 81 /* STM32F373 only */
 
 /* To simplify code generation, define DMA channel 9..10 */
-#define STM32_IRQ_DMA_CHANNEL_9    STM32_IRQ_DMA2_CHANNEL1
-#define STM32_IRQ_DMA_CHANNEL_10   STM32_IRQ_DMA2_CHANNEL2
-#define STM32_IRQ_DMA_CHANNEL_13   STM32_IRQ_DMA2_CHANNEL6
-#define STM32_IRQ_DMA_CHANNEL_14   STM32_IRQ_DMA2_CHANNEL7
+#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1
+#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2
+#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6
+#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7
 
 /* aliases for easier code sharing */
 #define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV
@@ -134,279 +133,276 @@
  * STM32F4 introduces a concept of DMA stream to allow
  * fine allocation of a stream to a channel.
  */
-#define STM32_IRQ_DMA1_STREAM0    11
-#define STM32_IRQ_DMA1_STREAM1    12
-#define STM32_IRQ_DMA1_STREAM2    13
-#define STM32_IRQ_DMA1_STREAM3    14
-#define STM32_IRQ_DMA1_STREAM4    15
-#define STM32_IRQ_DMA1_STREAM5    16
-#define STM32_IRQ_DMA1_STREAM6    17
-#define STM32_IRQ_DMA1_STREAM7    47
-#define STM32_IRQ_DMA2_STREAM0    56
-#define STM32_IRQ_DMA2_STREAM1    57
-#define STM32_IRQ_DMA2_STREAM2    58
-#define STM32_IRQ_DMA2_STREAM3    59
-#define STM32_IRQ_DMA2_STREAM4    60
-#define STM32_IRQ_DMA2_STREAM5    68
-#define STM32_IRQ_DMA2_STREAM6    69
-#define STM32_IRQ_DMA2_STREAM7    70
-
-#define STM32_IRQ_OTG_HS_WKUP     76
-#define STM32_IRQ_OTG_HS_EP1_IN   75
-#define STM32_IRQ_OTG_HS_EP1_OUT  74
-#define STM32_IRQ_OTG_HS          77
-#define STM32_IRQ_OTG_FS          67
-#define STM32_IRQ_OTG_FS_WKUP     42
+#define STM32_IRQ_DMA1_STREAM0 11
+#define STM32_IRQ_DMA1_STREAM1 12
+#define STM32_IRQ_DMA1_STREAM2 13
+#define STM32_IRQ_DMA1_STREAM3 14
+#define STM32_IRQ_DMA1_STREAM4 15
+#define STM32_IRQ_DMA1_STREAM5 16
+#define STM32_IRQ_DMA1_STREAM6 17
+#define STM32_IRQ_DMA1_STREAM7 47
+#define STM32_IRQ_DMA2_STREAM0 56
+#define STM32_IRQ_DMA2_STREAM1 57
+#define STM32_IRQ_DMA2_STREAM2 58
+#define STM32_IRQ_DMA2_STREAM3 59
+#define STM32_IRQ_DMA2_STREAM4 60
+#define STM32_IRQ_DMA2_STREAM5 68
+#define STM32_IRQ_DMA2_STREAM6 69
+#define STM32_IRQ_DMA2_STREAM7 70
+
+#define STM32_IRQ_OTG_HS_WKUP 76
+#define STM32_IRQ_OTG_HS_EP1_IN 75
+#define STM32_IRQ_OTG_HS_EP1_OUT 74
+#define STM32_IRQ_OTG_HS 77
+#define STM32_IRQ_OTG_FS 67
+#define STM32_IRQ_OTG_FS_WKUP 42
 
 /* Peripheral base addresses */
-#define STM32_ADC1_BASE             0x40012000
-#define STM32_ADC_BASE              0x40012300
-
-#define STM32_CEC_BASE              0x40007800 /* STM32F373 */
-#define STM32_CRC_BASE              0x40023000
-#define STM32_CRS_BASE              0x40006c00 /* STM32F0XX */
-#define STM32_DAC_BASE              0x40007400
-
-
-#define STM32_DBGMCU_BASE           0xE0042000
-
-#define STM32_DMA1_BASE             0x40026000
-#define STM32_DMA2_BASE             0x40026400
-
-#define STM32_EXTI_BASE             0x40013C00
-
-#define STM32_FLASH_REGS_BASE       0x40023c00
-
-#define STM32_GPIOA_BASE            0x40020000
-#define STM32_GPIOB_BASE            0x40020400
-#define STM32_GPIOC_BASE            0x40020800
-#define STM32_GPIOD_BASE            0x40020C00
-#define STM32_GPIOE_BASE            0x40021000
-#define STM32_GPIOF_BASE            0x40021400 /* see RM0402/0390 table 1 */
-#define STM32_GPIOG_BASE            0x40021800
-#define STM32_GPIOH_BASE            0x40021C00
-
-#define STM32_I2C1_BASE             0x40005400
-#define STM32_I2C2_BASE             0x40005800
-#define STM32_I2C3_BASE             0x40005C00
-#define STM32_I2C4_BASE             0x40006000
-
-#define STM32_IWDG_BASE             0x40003000
-#define STM32_LCD_BASE              0x40002400
-
-#define STM32_OPTB_BASE             0x1FFFC000
-#define STM32_OTP_BASE              0x1FFF7800
-
-#define STM32_PMSE_BASE             0x40013400
-#define STM32_PWR_BASE              0x40007000
-
-#define STM32_RCC_BASE              0x40023800
-
-#define STM32_RI_BASE               0x40007C00 /* STM32L1xx only */
-#define STM32_RNG_BASE              0x50060800 /* STM32L4 */
-#define STM32_RTC_BASE              0x40002800
-
-#define STM32_SPI1_BASE             0x40013000
-#define STM32_SPI2_BASE             0x40003800
-#define STM32_SPI3_BASE             0x40003c00 /* STM32F373, STM32L4, STM32F7 */
-
-#define STM32_SYSCFG_BASE           0x40013800
-
-#define STM32_TIM1_BASE             0x40012c00 /* STM32F373 */
-#define STM32_TIM2_BASE             0x40000000
-#define STM32_TIM3_BASE             0x40000400
-#define STM32_TIM4_BASE             0x40000800
-#define STM32_TIM5_BASE             0x40000c00 /* STM32F373 */
-#define STM32_TIM6_BASE             0x40001000
-#define STM32_TIM7_BASE             0x40001400
-#define STM32_TIM9_BASE             0x40014000 /* STM32F41x only */
-#define STM32_TIM10_BASE            0x40014400 /* STM32F41x only */
-#define STM32_TIM11_BASE            0x40014800 /* STM32F41x only */
-#define STM32_TIM12_BASE            0x40001800 /* STM32F373 */
-#define STM32_TIM13_BASE            0x40001c00 /* STM32F373 */
-#define STM32_TIM14_BASE            0x40002000 /* STM32F373 */
-#define STM32_TIM15_BASE            0x40014000
-#define STM32_TIM16_BASE            0x40014400
-#define STM32_TIM17_BASE            0x40014800
-#define STM32_TIM18_BASE            0x40009c00 /* STM32F373 only */
-#define STM32_TIM19_BASE            0x40015c00 /* STM32F373 only */
-
-#define STM32_UNIQUE_ID_BASE        0x1fff7a10
-
-#define STM32_USART1_BASE           0x40011000
-#define STM32_USART2_BASE           0x40004400
-#define STM32_USART3_BASE           0x40004800
-#define STM32_USART4_BASE           0x40004c00
-#define STM32_USART5_BASE           0x40005000
-#define STM32_USART6_BASE           0x40011400
-
-#define STM32_USB_CAN_SRAM_BASE     0x40006000
-#define STM32_USB_FS_BASE           0x40005C00
-
-#define STM32_WWDG_BASE             0x40002C00
-
+#define STM32_ADC1_BASE 0x40012000
+#define STM32_ADC_BASE 0x40012300
+
+#define STM32_CEC_BASE 0x40007800 /* STM32F373 */
+#define STM32_CRC_BASE 0x40023000
+#define STM32_CRS_BASE 0x40006c00 /* STM32F0XX */
+#define STM32_DAC_BASE 0x40007400
+
+#define STM32_DBGMCU_BASE 0xE0042000
+
+#define STM32_DMA1_BASE 0x40026000
+#define STM32_DMA2_BASE 0x40026400
+
+#define STM32_EXTI_BASE 0x40013C00
+
+#define STM32_FLASH_REGS_BASE 0x40023c00
+
+#define STM32_GPIOA_BASE 0x40020000
+#define STM32_GPIOB_BASE 0x40020400
+#define STM32_GPIOC_BASE 0x40020800
+#define STM32_GPIOD_BASE 0x40020C00
+#define STM32_GPIOE_BASE 0x40021000
+#define STM32_GPIOF_BASE 0x40021400 /* see RM0402/0390 table 1 */
+#define STM32_GPIOG_BASE 0x40021800
+#define STM32_GPIOH_BASE 0x40021C00
+
+#define STM32_I2C1_BASE 0x40005400
+#define STM32_I2C2_BASE 0x40005800
+#define STM32_I2C3_BASE 0x40005C00
+#define STM32_I2C4_BASE 0x40006000
+
+#define STM32_IWDG_BASE 0x40003000
+#define STM32_LCD_BASE 0x40002400
+
+#define STM32_OPTB_BASE 0x1FFFC000
+#define STM32_OTP_BASE 0x1FFF7800
+
+#define STM32_PMSE_BASE 0x40013400
+#define STM32_PWR_BASE 0x40007000
+
+#define STM32_RCC_BASE 0x40023800
+
+#define STM32_RI_BASE 0x40007C00 /* STM32L1xx only */
+#define STM32_RNG_BASE 0x50060800 /* STM32L4 */
+#define STM32_RTC_BASE 0x40002800
+
+#define STM32_SPI1_BASE 0x40013000
+#define STM32_SPI2_BASE 0x40003800
+#define STM32_SPI3_BASE 0x40003c00 /* STM32F373, STM32L4, STM32F7 */
+
+#define STM32_SYSCFG_BASE 0x40013800
+
+#define STM32_TIM1_BASE 0x40012c00 /* STM32F373 */
+#define STM32_TIM2_BASE 0x40000000
+#define STM32_TIM3_BASE 0x40000400
+#define STM32_TIM4_BASE 0x40000800
+#define STM32_TIM5_BASE 0x40000c00 /* STM32F373 */
+#define STM32_TIM6_BASE 0x40001000
+#define STM32_TIM7_BASE 0x40001400
+#define STM32_TIM9_BASE 0x40014000 /* STM32F41x only */
+#define STM32_TIM10_BASE 0x40014400 /* STM32F41x only */
+#define STM32_TIM11_BASE 0x40014800 /* STM32F41x only */
+#define STM32_TIM12_BASE 0x40001800 /* STM32F373 */
+#define STM32_TIM13_BASE 0x40001c00 /* STM32F373 */
+#define STM32_TIM14_BASE 0x40002000 /* STM32F373 */
+#define STM32_TIM15_BASE 0x40014000
+#define STM32_TIM16_BASE 0x40014400
+#define STM32_TIM17_BASE 0x40014800
+#define STM32_TIM18_BASE 0x40009c00 /* STM32F373 only */
+#define STM32_TIM19_BASE 0x40015c00 /* STM32F373 only */
+
+#define STM32_UNIQUE_ID_BASE 0x1fff7a10
+
+#define STM32_USART1_BASE 0x40011000
+#define STM32_USART2_BASE 0x40004400
+#define STM32_USART3_BASE 0x40004800
+#define STM32_USART4_BASE 0x40004c00
+#define STM32_USART5_BASE 0x40005000
+#define STM32_USART6_BASE 0x40011400
+
+#define STM32_USB_CAN_SRAM_BASE 0x40006000
+#define STM32_USB_FS_BASE 0x40005C00
+
+#define STM32_WWDG_BASE 0x40002C00
 
 #ifndef __ASSEMBLER__
 
 /* Register definitions */
 
 /* --- USART --- */
-#define STM32_USART_SR(base)       STM32_USART_REG(base, 0x00)
-#define STM32_USART_SR_ORE		BIT(3)
-#define STM32_USART_SR_RXNE		BIT(5)
-#define STM32_USART_SR_TC		BIT(6)
-#define STM32_USART_SR_TXE		BIT(7)
-#define STM32_USART_DR(base)       STM32_USART_REG(base, 0x04)
-#define STM32_USART_BRR(base)      STM32_USART_REG(base, 0x08)
-#define STM32_USART_CR1(base)      STM32_USART_REG(base, 0x0C)
-#define STM32_USART_CR1_RE		BIT(2)
-#define STM32_USART_CR1_TE		BIT(3)
-#define STM32_USART_CR1_RXNEIE		BIT(5)
-#define STM32_USART_CR1_TCIE		BIT(6)
-#define STM32_USART_CR1_TXEIE		BIT(7)
-#define STM32_USART_CR1_PS		BIT(9)
-#define STM32_USART_CR1_PCE		BIT(10)
-#define STM32_USART_CR1_M		BIT(12)
-#define STM32_USART_CR1_UE		BIT(13)
-#define STM32_USART_CR1_OVER8		BIT(15) /* STM32L only */
-#define STM32_USART_CR2(base)      STM32_USART_REG(base, 0x10)
-#define STM32_USART_CR3(base)      STM32_USART_REG(base, 0x14)
-#define STM32_USART_CR3_EIE		BIT(0)
-#define STM32_USART_CR3_DMAR		BIT(6)
-#define STM32_USART_CR3_DMAT		BIT(7)
-#define STM32_USART_CR3_ONEBIT		BIT(11) /* STM32L only */
-#define STM32_USART_GTPR(base)     STM32_USART_REG(base, 0x18)
+#define STM32_USART_SR(base) STM32_USART_REG(base, 0x00)
+#define STM32_USART_SR_ORE BIT(3)
+#define STM32_USART_SR_RXNE BIT(5)
+#define STM32_USART_SR_TC BIT(6)
+#define STM32_USART_SR_TXE BIT(7)
+#define STM32_USART_DR(base) STM32_USART_REG(base, 0x04)
+#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x08)
+#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x0C)
+#define STM32_USART_CR1_RE BIT(2)
+#define STM32_USART_CR1_TE BIT(3)
+#define STM32_USART_CR1_RXNEIE BIT(5)
+#define STM32_USART_CR1_TCIE BIT(6)
+#define STM32_USART_CR1_TXEIE BIT(7)
+#define STM32_USART_CR1_PS BIT(9)
+#define STM32_USART_CR1_PCE BIT(10)
+#define STM32_USART_CR1_M BIT(12)
+#define STM32_USART_CR1_UE BIT(13)
+#define STM32_USART_CR1_OVER8 BIT(15) /* STM32L only */
+#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x10)
+#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x14)
+#define STM32_USART_CR3_EIE BIT(0)
+#define STM32_USART_CR3_DMAR BIT(6)
+#define STM32_USART_CR3_DMAT BIT(7)
+#define STM32_USART_CR3_ONEBIT BIT(11) /* STM32L only */
+#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x18)
 /* register aliases */
-#define STM32_USART_TDR(base)      STM32_USART_DR(base)
-#define STM32_USART_RDR(base)      STM32_USART_DR(base)
+#define STM32_USART_TDR(base) STM32_USART_DR(base)
+#define STM32_USART_RDR(base) STM32_USART_DR(base)
 
 /* --- GPIO --- */
-#define STM32_GPIO_MODER(b)     REG32((b) + 0x00)
-#define STM32_GPIO_OTYPER(b)    REG16((b) + 0x04)
-#define STM32_GPIO_OSPEEDR(b)   REG32((b) + 0x08)
-#define STM32_GPIO_PUPDR(b)     REG32((b) + 0x0C)
-#define STM32_GPIO_IDR(b)       REG16((b) + 0x10)
-#define STM32_GPIO_ODR(b)       REG16((b) + 0x14)
-#define STM32_GPIO_BSRR(b)      REG32((b) + 0x18)
-#define STM32_GPIO_LCKR(b)      REG32((b) + 0x1C)
-#define STM32_GPIO_AFRL(b)      REG32((b) + 0x20)
-#define STM32_GPIO_AFRH(b)      REG32((b) + 0x24)
-
-#define GPIO_ALT_SYS                 0x0
-#define GPIO_ALT_TIM2                0x1
-#define GPIO_ALT_TIM3_4              0x2
-#define GPIO_ALT_TIM9_11             0x3
-#define GPIO_ALT_I2C                 0x4
-#define GPIO_ALT_SPI                 0x5
-#define GPIO_ALT_SPI3                0x6
-#define GPIO_ALT_USART               0x7
-#define GPIO_ALT_I2C_23              0x9
-#define GPIO_ALT_USB                 0xA
-#define GPIO_ALT_LCD                 0xB
-#define GPIO_ALT_RI                  0xE
-#define GPIO_ALT_EVENTOUT            0xF
+#define STM32_GPIO_MODER(b) REG32((b) + 0x00)
+#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04)
+#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08)
+#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C)
+#define STM32_GPIO_IDR(b) REG16((b) + 0x10)
+#define STM32_GPIO_ODR(b) REG16((b) + 0x14)
+#define STM32_GPIO_BSRR(b) REG32((b) + 0x18)
+#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C)
+#define STM32_GPIO_AFRL(b) REG32((b) + 0x20)
+#define STM32_GPIO_AFRH(b) REG32((b) + 0x24)
+
+#define GPIO_ALT_SYS 0x0
+#define GPIO_ALT_TIM2 0x1
+#define GPIO_ALT_TIM3_4 0x2
+#define GPIO_ALT_TIM9_11 0x3
+#define GPIO_ALT_I2C 0x4
+#define GPIO_ALT_SPI 0x5
+#define GPIO_ALT_SPI3 0x6
+#define GPIO_ALT_USART 0x7
+#define GPIO_ALT_I2C_23 0x9
+#define GPIO_ALT_USB 0xA
+#define GPIO_ALT_LCD 0xB
+#define GPIO_ALT_RI 0xE
+#define GPIO_ALT_EVENTOUT 0xF
 
 /* --- I2C --- */
-#define STM32_I2C_CR1(n)            REG16(stm32_i2c_reg(n, 0x00))
-#define STM32_I2C_CR1_PE	BIT(0)
-#define STM32_I2C_CR1_START	BIT(8)
-#define STM32_I2C_CR1_STOP	BIT(9)
-#define STM32_I2C_CR1_ACK	BIT(10)
-#define STM32_I2C_CR1_POS	BIT(11)
-#define STM32_I2C_CR1_SWRST	BIT(15)
-#define STM32_I2C_CR2(n)            REG16(stm32_i2c_reg(n, 0x04))
-#define STM32_I2C_CR2_ITERREN	BIT(8)
-#define STM32_I2C_CR2_ITEVTEN	BIT(9)
-#define STM32_I2C_CR2_ITBUFEN	BIT(10)
-#define STM32_I2C_CR2_DMAEN	BIT(11)
-#define STM32_I2C_CR2_LAST	BIT(12)
-#define STM32_I2C_OAR1(n)           REG16(stm32_i2c_reg(n, 0x08))
-#define STM32_I2C_OAR1_B14	BIT(14)
-#define STM32_I2C_OAR2(n)           REG16(stm32_i2c_reg(n, 0x0C))
-#define STM32_I2C_OAR2_ENDUAL	BIT(0)
-#define STM32_I2C_DR(n)             REG16(stm32_i2c_reg(n, 0x10))
-#define STM32_I2C_SR1(n)            REG16(stm32_i2c_reg(n, 0x14))
-#define STM32_I2C_SR1_SB	BIT(0)
-#define STM32_I2C_SR1_ADDR	BIT(1)
-#define STM32_I2C_SR1_BTF	BIT(2)
-#define STM32_I2C_SR1_STOPF	BIT(4)
-#define STM32_I2C_SR1_RXNE	BIT(6)
-#define STM32_I2C_SR1_TXE	BIT(7)
-#define STM32_I2C_SR1_BERR	BIT(8)
-#define STM32_I2C_SR1_ARLO	BIT(9)
-#define STM32_I2C_SR1_AF	BIT(10)
-
-#define STM32_I2C_SR2(n)            REG16(stm32_i2c_reg(n, 0x18))
-#define STM32_I2C_SR2_BUSY	BIT(1)
-#define STM32_I2C_SR2_TRA	BIT(2)
-#define STM32_I2C_SR2_DUALF	BIT(7)
-
-#define STM32_I2C_CCR(n)            REG16(stm32_i2c_reg(n, 0x1C))
-#define STM32_I2C_CCR_DUTY	BIT(14)
-#define STM32_I2C_CCR_FM	BIT(15)
-#define STM32_I2C_TRISE(n)          REG16(stm32_i2c_reg(n, 0x20))
-
-#define STM32_FMPI2C_CR1(n)        REG32(stm32_i2c_reg(n, 0x00))
-#define  FMPI2C_CR1_PE             BIT(0)
-#define  FMPI2C_CR1_TXDMAEN        BIT(14)
-#define  FMPI2C_CR1_RXDMAEN        BIT(15)
-#define STM32_FMPI2C_CR2(n)        REG32(stm32_i2c_reg(n, 0x04))
-#define  FMPI2C_CR2_RD_WRN         BIT(10)
-#define  FMPI2C_READ               1
-#define  FMPI2C_WRITE              0
-#define  FMPI2C_CR2_START          BIT(13)
-#define  FMPI2C_CR2_STOP           BIT(14)
-#define  FMPI2C_CR2_NACK           BIT(15)
-#define  FMPI2C_CR2_RELOAD         BIT(24)
-#define  FMPI2C_CR2_AUTOEND        BIT(25)
-#define  FMPI2C_CR2_SADD(addr)     ((addr) & 0x3ff)
-#define  FMPI2C_CR2_SADD_MASK      FMPI2C_CR2_SADD(0x3ff)
-#define  FMPI2C_CR2_SIZE(size)     (((size) & 0xff) << 16)
-#define  FMPI2C_CR2_SIZE_MASK      FMPI2C_CR2_SIZE(0xf)
-#define STM32_FMPI2C_OAR1(n)       REG32(stm32_i2c_reg(n, 0x08))
-#define STM32_FMPI2C_OAR2(n)       REG32(stm32_i2c_reg(n, 0x0C))
-#define STM32_FMPI2C_TIMINGR(n)    REG32(stm32_i2c_reg(n, 0x10))
-#define  TIMINGR_THE_RIGHT_VALUE   0xC0000E12
-#define  FMPI2C_TIMINGR_PRESC(val) (((val) & 0xf) << 28)
-#define  FMPI2C_TIMINGR_SCLDEL(val) (((val) & 0xf) << 20)
-#define  FMPI2C_TIMINGR_SDADEL(val) (((val) & 0xf) << 16)
-#define  FMPI2C_TIMINGR_SCLH(val)  (((val) & 0xff) << 8)
-#define  FMPI2C_TIMINGR_SCLL(val)  (((val) & 0xff) << 0)
-#define STM32_FMPI2C_TIMEOUTR(n)   REG32(stm32_i2c_reg(n, 0x14))
-
-#define STM32_FMPI2C_ISR(n)        REG32(stm32_i2c_reg(n, 0x18))
-#define  FMPI2C_ISR_TXE            BIT(0)
-#define  FMPI2C_ISR_TXIS           BIT(1)
-#define  FMPI2C_ISR_RXNE           BIT(2)
-#define  FMPI2C_ISR_ADDR           BIT(3)
-#define  FMPI2C_ISR_NACKF          BIT(4)
-#define  FMPI2C_ISR_STOPF          BIT(5)
-#define  FMPI2C_ISR_BERR           BIT(8)
-#define  FMPI2C_ISR_ARLO           BIT(9)
-#define  FMPI2C_ISR_BUSY           BIT(15)
-#define STM32_FMPI2C_ICR(n)        REG32(stm32_i2c_reg(n, 0x1C))
-
-#define STM32_FMPI2C_PECR(n)       REG32(stm32_i2c_reg(n, 0x20))
-#define STM32_FMPI2C_RXDR(n)       REG32(stm32_i2c_reg(n, 0x24))
-#define STM32_FMPI2C_TXDR(n)       REG32(stm32_i2c_reg(n, 0x28))
+#define STM32_I2C_CR1(n) REG16(stm32_i2c_reg(n, 0x00))
+#define STM32_I2C_CR1_PE BIT(0)
+#define STM32_I2C_CR1_START BIT(8)
+#define STM32_I2C_CR1_STOP BIT(9)
+#define STM32_I2C_CR1_ACK BIT(10)
+#define STM32_I2C_CR1_POS BIT(11)
+#define STM32_I2C_CR1_SWRST BIT(15)
+#define STM32_I2C_CR2(n) REG16(stm32_i2c_reg(n, 0x04))
+#define STM32_I2C_CR2_ITERREN BIT(8)
+#define STM32_I2C_CR2_ITEVTEN BIT(9)
+#define STM32_I2C_CR2_ITBUFEN BIT(10)
+#define STM32_I2C_CR2_DMAEN BIT(11)
+#define STM32_I2C_CR2_LAST BIT(12)
+#define STM32_I2C_OAR1(n) REG16(stm32_i2c_reg(n, 0x08))
+#define STM32_I2C_OAR1_B14 BIT(14)
+#define STM32_I2C_OAR2(n) REG16(stm32_i2c_reg(n, 0x0C))
+#define STM32_I2C_OAR2_ENDUAL BIT(0)
+#define STM32_I2C_DR(n) REG16(stm32_i2c_reg(n, 0x10))
+#define STM32_I2C_SR1(n) REG16(stm32_i2c_reg(n, 0x14))
+#define STM32_I2C_SR1_SB BIT(0)
+#define STM32_I2C_SR1_ADDR BIT(1)
+#define STM32_I2C_SR1_BTF BIT(2)
+#define STM32_I2C_SR1_STOPF BIT(4)
+#define STM32_I2C_SR1_RXNE BIT(6)
+#define STM32_I2C_SR1_TXE BIT(7)
+#define STM32_I2C_SR1_BERR BIT(8)
+#define STM32_I2C_SR1_ARLO BIT(9)
+#define STM32_I2C_SR1_AF BIT(10)
+
+#define STM32_I2C_SR2(n) REG16(stm32_i2c_reg(n, 0x18))
+#define STM32_I2C_SR2_BUSY BIT(1)
+#define STM32_I2C_SR2_TRA BIT(2)
+#define STM32_I2C_SR2_DUALF BIT(7)
+
+#define STM32_I2C_CCR(n) REG16(stm32_i2c_reg(n, 0x1C))
+#define STM32_I2C_CCR_DUTY BIT(14)
+#define STM32_I2C_CCR_FM BIT(15)
+#define STM32_I2C_TRISE(n) REG16(stm32_i2c_reg(n, 0x20))
+
+#define STM32_FMPI2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00))
+#define FMPI2C_CR1_PE BIT(0)
+#define FMPI2C_CR1_TXDMAEN BIT(14)
+#define FMPI2C_CR1_RXDMAEN BIT(15)
+#define STM32_FMPI2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04))
+#define FMPI2C_CR2_RD_WRN BIT(10)
+#define FMPI2C_READ 1
+#define FMPI2C_WRITE 0
+#define FMPI2C_CR2_START BIT(13)
+#define FMPI2C_CR2_STOP BIT(14)
+#define FMPI2C_CR2_NACK BIT(15)
+#define FMPI2C_CR2_RELOAD BIT(24)
+#define FMPI2C_CR2_AUTOEND BIT(25)
+#define FMPI2C_CR2_SADD(addr) ((addr)&0x3ff)
+#define FMPI2C_CR2_SADD_MASK FMPI2C_CR2_SADD(0x3ff)
+#define FMPI2C_CR2_SIZE(size) (((size)&0xff) << 16)
+#define FMPI2C_CR2_SIZE_MASK FMPI2C_CR2_SIZE(0xf)
+#define STM32_FMPI2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08))
+#define STM32_FMPI2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C))
+#define STM32_FMPI2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10))
+#define TIMINGR_THE_RIGHT_VALUE 0xC0000E12
+#define FMPI2C_TIMINGR_PRESC(val) (((val)&0xf) << 28)
+#define FMPI2C_TIMINGR_SCLDEL(val) (((val)&0xf) << 20)
+#define FMPI2C_TIMINGR_SDADEL(val) (((val)&0xf) << 16)
+#define FMPI2C_TIMINGR_SCLH(val) (((val)&0xff) << 8)
+#define FMPI2C_TIMINGR_SCLL(val) (((val)&0xff) << 0)
+#define STM32_FMPI2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14))
+
+#define STM32_FMPI2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18))
+#define FMPI2C_ISR_TXE BIT(0)
+#define FMPI2C_ISR_TXIS BIT(1)
+#define FMPI2C_ISR_RXNE BIT(2)
+#define FMPI2C_ISR_ADDR BIT(3)
+#define FMPI2C_ISR_NACKF BIT(4)
+#define FMPI2C_ISR_STOPF BIT(5)
+#define FMPI2C_ISR_BERR BIT(8)
+#define FMPI2C_ISR_ARLO BIT(9)
+#define FMPI2C_ISR_BUSY BIT(15)
+#define STM32_FMPI2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C))
+
+#define STM32_FMPI2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20))
+#define STM32_FMPI2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24))
+#define STM32_FMPI2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28))
 
 /* --- Power / Reset / Clocks --- */
-#define STM32_PWR_CSR               REG32(STM32_PWR_BASE + 0x04)
-
+#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04)
 
-#define STM32_RCC_CR                    REG32(STM32_RCC_BASE + 0x00)
-#define STM32_RCC_CR_HSION		BIT(0)
-#define STM32_RCC_CR_HSIRDY		BIT(1)
-#define STM32_RCC_CR_HSEON		BIT(16)
-#define STM32_RCC_CR_HSERDY		BIT(17)
-#define STM32_RCC_CR_PLLON		BIT(24)
-#define STM32_RCC_CR_PLLRDY		BIT(25)
+#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00)
+#define STM32_RCC_CR_HSION BIT(0)
+#define STM32_RCC_CR_HSIRDY BIT(1)
+#define STM32_RCC_CR_HSEON BIT(16)
+#define STM32_RCC_CR_HSERDY BIT(17)
+#define STM32_RCC_CR_PLLON BIT(24)
+#define STM32_RCC_CR_PLLRDY BIT(25)
 
 #if defined(CHIP_VARIANT_STM32F446)
 /* Required or recommended clocks for stm32f446 */
 #define STM32F4_PLL_REQ 2000000
 #define STM32F4_RTC_REQ 1000000
-#define STM32F4_IO_CLOCK  42000000
+#define STM32F4_IO_CLOCK 42000000
 #define STM32F4_USB_REQ 48000000
 #define STM32F4_VCO_CLOCK 336000000
 #define STM32F4_HSI_CLOCK 16000000
@@ -416,13 +412,15 @@
 #define STM32F4_AHB_PRE 0x8
 #define STM32F4_APB1_PRE 0x0
 #define STM32F4_APB2_PRE 0x0
-#define STM32_FLASH_ACR_LATENCY     BIT(0)
+#define STM32_FLASH_ACR_LATENCY BIT(0)
+/* optimized flash latency for < 30Mhz clock (0-WS) e.g. HSI/HSE */
+#define STM32_FLASH_ACR_LATENCY_SLOW 0
 
 #elif defined(CHIP_VARIANT_STM32F412)
 /* Required or recommended clocks for stm32f412 */
 #define STM32F4_PLL_REQ 2000000
 #define STM32F4_RTC_REQ 1000000
-#define STM32F4_IO_CLOCK  48000000
+#define STM32F4_IO_CLOCK 48000000
 #define STM32F4_USB_REQ 48000000
 #define STM32F4_VCO_CLOCK 384000000
 #define STM32F4_HSI_CLOCK 16000000
@@ -432,13 +430,15 @@
 #define STM32F4_AHB_PRE 0x0
 #define STM32F4_APB1_PRE 0x4
 #define STM32F4_APB2_PRE 0x4
-#define STM32_FLASH_ACR_LATENCY     (3 << 0)
+#define STM32_FLASH_ACR_LATENCY (3 << 0)
+/* optimized flash latency for < 30Mhz clock (0-WS) e.g. HSI/HSE */
+#define STM32_FLASH_ACR_LATENCY_SLOW 0
 
 #elif defined(CHIP_VARIANT_STM32F411)
 /* Required or recommended clocks for stm32f411 */
 #define STM32F4_PLL_REQ 2000000
 #define STM32F4_RTC_REQ 1000000
-#define STM32F4_IO_CLOCK  48000000
+#define STM32F4_IO_CLOCK 48000000
 #define STM32F4_USB_REQ 48000000
 #define STM32F4_VCO_CLOCK 384000000
 #define STM32F4_HSI_CLOCK 16000000
@@ -448,200 +448,205 @@
 #define STM32F4_AHB_PRE 0x8
 #define STM32F4_APB1_PRE 0x0
 #define STM32F4_APB2_PRE 0x0
-#define STM32_FLASH_ACR_LATENCY     BIT(0)
+#define STM32_FLASH_ACR_LATENCY BIT(0)
+/* optimized flash latency for < 30Mhz clock (0-WS) e.g. HSI/HSE */
+#define STM32_FLASH_ACR_LATENCY_SLOW 0
 
 #elif defined(CHIP_VARIANT_STM32F76X)
 /* Required or recommended clocks for stm32f767/769 */
 #define STM32F4_PLL_REQ 2000000
 #define STM32F4_RTC_REQ 1000000
 #define STM32F4_IO_CLOCK 45000000
-#define STM32F4_USB_REQ 45000000 /* not compatible with USB, will use PLLSAI */
+#define STM32F4_USB_REQ                                      \
+	45000000 /* not compatible with USB, will use PLLSAI \
+		  */
 #define STM32F4_VCO_CLOCK 360000000
 #define STM32F4_HSI_CLOCK 16000000
 #define STM32F4_LSI_CLOCK 32000
 #define STM32F4_TIMER_CLOCK (STM32F4_IO_CLOCK * 2)
-#define STM32F4_PLLP_DIV 2   /* sys = VCO/2  = 180 Mhz */
-#define STM32F4_AHB_PRE 0x0  /* AHB = sysclk = 180 Mhz */
+#define STM32F4_PLLP_DIV 2 /* sys = VCO/2  = 180 Mhz */
+#define STM32F4_AHB_PRE 0x0 /* AHB = sysclk = 180 Mhz */
 #define STM32F4_APB1_PRE 0x5 /* APB1 = AHB /4 = 45 Mhz */
 #define STM32F4_APB2_PRE 0x5 /* APB2 = AHB /4 = 45 Mhz */
-#define STM32_FLASH_ACR_LATENCY     (5 << 0)
+#define STM32_FLASH_ACR_LATENCY (5 << 0)
+/* optimized flash latency for < 30Mhz clock (0-WS) e.g. HSI/HSE */
+#define STM32_FLASH_ACR_LATENCY_SLOW 0
 
 #else
 #error "No valid clocks defined"
 #endif
 
-#define STM32_RCC_PLLCFGR               REG32(STM32_RCC_BASE + 0x04)
+#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x04)
 /* PLL Division factor */
-#define  PLLCFGR_PLLM_OFF		0
-#define  PLLCFGR_PLLM(val)		(((val) & 0x1f) << PLLCFGR_PLLM_OFF)
+#define PLLCFGR_PLLM_OFF 0
+#define PLLCFGR_PLLM(val) (((val)&0x1f) << PLLCFGR_PLLM_OFF)
 /* PLL Multiplication factor */
-#define  PLLCFGR_PLLN_OFF		6
-#define  PLLCFGR_PLLN(val)		(((val) & 0x1ff) << PLLCFGR_PLLN_OFF)
+#define PLLCFGR_PLLN_OFF 6
+#define PLLCFGR_PLLN(val) (((val)&0x1ff) << PLLCFGR_PLLN_OFF)
 /* Main CPU Clock */
-#define  PLLCFGR_PLLP_OFF		16
-#define  PLLCFGR_PLLP(val)		(((val) & 0x3) << PLLCFGR_PLLP_OFF)
+#define PLLCFGR_PLLP_OFF 16
+#define PLLCFGR_PLLP(val) (((val)&0x3) << PLLCFGR_PLLP_OFF)
 
-#define  PLLCFGR_PLLSRC_HSI		(0 << 22)
-#define  PLLCFGR_PLLSRC_HSE		BIT(22)
+#define PLLCFGR_PLLSRC_HSI (0 << 22)
+#define PLLCFGR_PLLSRC_HSE BIT(22)
 /* USB OTG FS: Must equal 48MHz */
-#define  PLLCFGR_PLLQ_OFF		24
-#define  PLLCFGR_PLLQ(val)		(((val) & 0xf) << PLLCFGR_PLLQ_OFF)
+#define PLLCFGR_PLLQ_OFF 24
+#define PLLCFGR_PLLQ(val) (((val)&0xf) << PLLCFGR_PLLQ_OFF)
 /* SYSTEM */
-#define  PLLCFGR_PLLR_OFF		28
-#define  PLLCFGR_PLLR(val)		(((val) & 0x7) << PLLCFGR_PLLR_OFF)
-
-#define STM32_RCC_CFGR                  REG32(STM32_RCC_BASE + 0x08)
-#define STM32_RCC_CFGR_SW_HSI		(0 << 0)
-#define STM32_RCC_CFGR_SW_HSE		(1 << 0)
-#define STM32_RCC_CFGR_SW_PLL		(2 << 0)
-#define STM32_RCC_CFGR_SW_PLL_R		(3 << 0)
-#define STM32_RCC_CFGR_SW_MASK		(3 << 0)
-#define STM32_RCC_CFGR_SWS_HSI		(0 << 2)
-#define STM32_RCC_CFGR_SWS_HSE		(1 << 2)
-#define STM32_RCC_CFGR_SWS_PLL		(2 << 2)
-#define STM32_RCC_CFGR_SWS_PLL_R	(3 << 2)
-#define STM32_RCC_CFGR_SWS_MASK		(3 << 2)
+#define PLLCFGR_PLLR_OFF 28
+#define PLLCFGR_PLLR(val) (((val)&0x7) << PLLCFGR_PLLR_OFF)
+
+#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08)
+#define STM32_RCC_CFGR_SW_HSI (0 << 0)
+#define STM32_RCC_CFGR_SW_HSE (1 << 0)
+#define STM32_RCC_CFGR_SW_PLL (2 << 0)
+#define STM32_RCC_CFGR_SW_PLL_R (3 << 0)
+#define STM32_RCC_CFGR_SW_MASK (3 << 0)
+#define STM32_RCC_CFGR_SWS_HSI (0 << 2)
+#define STM32_RCC_CFGR_SWS_HSE (1 << 2)
+#define STM32_RCC_CFGR_SWS_PLL (2 << 2)
+#define STM32_RCC_CFGR_SWS_PLL_R (3 << 2)
+#define STM32_RCC_CFGR_SWS_MASK (3 << 2)
 /* AHB Prescalar: nonlinear values, look up in RM0390 */
-#define  CFGR_HPRE_OFF			4
-#define  CFGR_HPRE(val)			(((val) & 0xf) << CFGR_HPRE_OFF)
+#define CFGR_HPRE_OFF 4
+#define CFGR_HPRE(val) (((val)&0xf) << CFGR_HPRE_OFF)
 /* APB1 Low Speed Prescalar < 45MHz */
-#define  CFGR_PPRE1_OFF			10
-#define  CFGR_PPRE1(val)		(((val) & 0x7) << CFGR_PPRE1_OFF)
+#define CFGR_PPRE1_OFF 10
+#define CFGR_PPRE1(val) (((val)&0x7) << CFGR_PPRE1_OFF)
 /* APB2 High Speed Prescalar < 90MHz */
-#define  CFGR_PPRE2_OFF			13
-#define  CFGR_PPRE2(val)		(((val) & 0x7) << CFGR_PPRE2_OFF)
+#define CFGR_PPRE2_OFF 13
+#define CFGR_PPRE2(val) (((val)&0x7) << CFGR_PPRE2_OFF)
 /* RTC CLock: Must equal 1MHz */
-#define  CFGR_RTCPRE_OFF		16
-#define  CFGR_RTCPRE(val)		(((val) & 0x1f) << CFGR_RTCPRE_OFF)
-
-#define STM32_RCC_CIR                   REG32(STM32_RCC_BASE + 0x0C)
-#define STM32_RCC_AHB1RSTR              REG32(STM32_RCC_BASE + 0x10)
-#define  RCC_AHB1RSTR_OTGHSRST		BIT(29)
-
-#define STM32_RCC_AHB2RSTR              REG32(STM32_RCC_BASE + 0x14)
-#define STM32_RCC_AHB3RSTR              REG32(STM32_RCC_BASE + 0x18)
-
-#define STM32_RCC_APB1RSTR              REG32(STM32_RCC_BASE + 0x20)
-#define STM32_RCC_APB2RSTR              REG32(STM32_RCC_BASE + 0x24)
-
-#define STM32_RCC_AHB1ENR               REG32(STM32_RCC_BASE + 0x30)
-#define STM32_RCC_AHB1ENR_GPIO_PORTA	BIT(0)
-#define STM32_RCC_AHB1ENR_GPIO_PORTB	BIT(1)
-#define STM32_RCC_AHB1ENR_GPIO_PORTC	BIT(2)
-#define STM32_RCC_AHB1ENR_GPIO_PORTD	BIT(3)
-#define STM32_RCC_AHB1ENR_GPIO_PORTE	BIT(4)
-#define STM32_RCC_AHB1ENR_GPIO_PORTF	BIT(5)
-#define STM32_RCC_AHB1ENR_GPIO_PORTG	BIT(6)
-#define STM32_RCC_AHB1ENR_GPIO_PORTH	BIT(7)
-#define STM32_RCC_AHB1ENR_GPIOMASK	(0xff << 0)
-#define STM32_RCC_AHB1ENR_BKPSRAMEN	BIT(18)
-#define STM32_RCC_AHB1ENR_DMA1EN	BIT(21)
-#define STM32_RCC_AHB1ENR_DMA2EN	BIT(22)
+#define CFGR_RTCPRE_OFF 16
+#define CFGR_RTCPRE(val) (((val)&0x1f) << CFGR_RTCPRE_OFF)
+
+#define STM32_RCC_CIR REG32(STM32_RCC_BASE + 0x0C)
+#define STM32_RCC_AHB1RSTR REG32(STM32_RCC_BASE + 0x10)
+#define RCC_AHB1RSTR_OTGHSRST BIT(29)
+
+#define STM32_RCC_AHB2RSTR REG32(STM32_RCC_BASE + 0x14)
+#define STM32_RCC_AHB3RSTR REG32(STM32_RCC_BASE + 0x18)
+
+#define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x20)
+#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x24)
+
+#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x30)
+#define STM32_RCC_AHB1ENR_GPIO_PORTA BIT(0)
+#define STM32_RCC_AHB1ENR_GPIO_PORTB BIT(1)
+#define STM32_RCC_AHB1ENR_GPIO_PORTC BIT(2)
+#define STM32_RCC_AHB1ENR_GPIO_PORTD BIT(3)
+#define STM32_RCC_AHB1ENR_GPIO_PORTE BIT(4)
+#define STM32_RCC_AHB1ENR_GPIO_PORTF BIT(5)
+#define STM32_RCC_AHB1ENR_GPIO_PORTG BIT(6)
+#define STM32_RCC_AHB1ENR_GPIO_PORTH BIT(7)
+#define STM32_RCC_AHB1ENR_GPIOMASK (0xff << 0)
+#define STM32_RCC_AHB1ENR_BKPSRAMEN BIT(18)
+#define STM32_RCC_AHB1ENR_DMA1EN BIT(21)
+#define STM32_RCC_AHB1ENR_DMA2EN BIT(22)
 
 /* TODO(nsanders): normalize naming.*/
-#define STM32_RCC_HB1_DMA1		BIT(21)
-#define STM32_RCC_HB1_DMA2		BIT(22)
-#define STM32_RCC_AHB1ENR_OTGHSEN	BIT(29)
-#define STM32_RCC_AHB1ENR_OTGHSULPIEN	BIT(30)
-
-#define STM32_RCC_AHB2ENR               REG32(STM32_RCC_BASE + 0x34)
-#define STM32_RCC_AHB2ENR_RNGEN		BIT(6)
-#define STM32_RCC_AHB2ENR_OTGFSEN	BIT(7)
-#define STM32_RCC_AHB3ENR               REG32(STM32_RCC_BASE + 0x38)
-
-#define STM32_RCC_APB1ENR               REG32(STM32_RCC_BASE + 0x40)
-#define STM32_RCC_PWREN                 BIT(28)
-#define STM32_RCC_I2C1EN                BIT(21)
-#define STM32_RCC_I2C2EN                BIT(22)
-#define STM32_RCC_I2C3EN                BIT(23)
-#define STM32_RCC_FMPI2C4EN             BIT(24)
-
-#define STM32_RCC_APB2ENR               REG32(STM32_RCC_BASE + 0x44)
-#define STM32_RCC_APB2ENR_ADC1EN        BIT(8) /* STM32F4 */
-
-#define STM32_RCC_PB2_USART6            BIT(5)
-#define STM32_RCC_SYSCFGEN		BIT(14)
-
-#define STM32_RCC_AHB1LPENR             REG32(STM32_RCC_BASE + 0x50)
-#define STM32_RCC_AHB2LPENR             REG32(STM32_RCC_BASE + 0x54)
-#define STM32_RCC_AHB3LPENR             REG32(STM32_RCC_BASE + 0x58)
-#define STM32_RCC_APB1LPENR             REG32(STM32_RCC_BASE + 0x60)
-#define STM32_RCC_APB2LPENR             REG32(STM32_RCC_BASE + 0x64)
-
-#define STM32_RCC_BDCR                  REG32(STM32_RCC_BASE + 0x70)
-#define STM32_RCC_CSR                   REG32(STM32_RCC_BASE + 0x74)
-#define STM32_RCC_CSR_LSION		BIT(0)
-#define STM32_RCC_CSR_LSIRDY		BIT(1)
-
-#define STM32_RCC_PB2_TIM1		BIT(0)
-#define STM32_RCC_PB2_TIM8		BIT(1)
-#define STM32_RCC_PB2_TIM9		BIT(16)
-#define STM32_RCC_PB2_TIM10		BIT(17)
-#define STM32_RCC_PB2_TIM11		BIT(18)
-
-#define STM32_RCC_DCKCFGR2              REG32(STM32_RCC_BASE + 0x94)
-#define  DCKCFGR2_FMPI2C1SEL(val)       (((val) & 0x3) << 22)
-#define  DCKCFGR2_FMPI2C1SEL_MASK       (0x3 << 22)
-#define  FMPI2C1SEL_APB                 0x0
-
-#define STM32_SYSCFG_MEMRMP             REG32(STM32_SYSCFG_BASE + 0x00)
-#define STM32_SYSCFG_PMC                REG32(STM32_SYSCFG_BASE + 0x04)
-#define STM32_SYSCFG_EXTICR(n)          REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
-#define STM32_SYSCFG_CMPCR              REG32(STM32_SYSCFG_BASE + 0x20)
-#define STM32_SYSCFG_CFGR               REG32(STM32_SYSCFG_BASE + 0x2C)
-
+#define STM32_RCC_HB1_DMA1 BIT(21)
+#define STM32_RCC_HB1_DMA2 BIT(22)
+#define STM32_RCC_AHB1ENR_OTGHSEN BIT(29)
+#define STM32_RCC_AHB1ENR_OTGHSULPIEN BIT(30)
+
+#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x34)
+#define STM32_RCC_AHB2ENR_RNGEN BIT(6)
+#define STM32_RCC_AHB2ENR_OTGFSEN BIT(7)
+#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x38)
+
+#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x40)
+#define STM32_RCC_PWREN BIT(28)
+#define STM32_RCC_I2C1EN BIT(21)
+#define STM32_RCC_I2C2EN BIT(22)
+#define STM32_RCC_I2C3EN BIT(23)
+#define STM32_RCC_FMPI2C4EN BIT(24)
+
+#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x44)
+#define STM32_RCC_APB2ENR_ADC1EN BIT(8) /* STM32F4 */
+
+#define STM32_RCC_PB2_USART6 BIT(5)
+#define STM32_RCC_SYSCFGEN BIT(14)
+
+#define STM32_RCC_AHB1LPENR REG32(STM32_RCC_BASE + 0x50)
+#define STM32_RCC_AHB2LPENR REG32(STM32_RCC_BASE + 0x54)
+#define STM32_RCC_AHB3LPENR REG32(STM32_RCC_BASE + 0x58)
+#define STM32_RCC_APB1LPENR REG32(STM32_RCC_BASE + 0x60)
+#define STM32_RCC_APB2LPENR REG32(STM32_RCC_BASE + 0x64)
+
+#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x70)
+#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x74)
+#define STM32_RCC_CSR_LSION BIT(0)
+#define STM32_RCC_CSR_LSIRDY BIT(1)
+
+#define STM32_RCC_PB2_TIM1 BIT(0)
+#define STM32_RCC_PB2_TIM8 BIT(1)
+#define STM32_RCC_PB2_TIM9 BIT(16)
+#define STM32_RCC_PB2_TIM10 BIT(17)
+#define STM32_RCC_PB2_TIM11 BIT(18)
+
+#define STM32_RCC_DCKCFGR2 REG32(STM32_RCC_BASE + 0x94)
+#define DCKCFGR2_FMPI2C1SEL(val) (((val)&0x3) << 22)
+#define DCKCFGR2_FMPI2C1SEL_MASK (0x3 << 22)
+#define FMPI2C1SEL_APB 0x0
+
+#define STM32_SYSCFG_MEMRMP REG32(STM32_SYSCFG_BASE + 0x00)
+#define STM32_SYSCFG_PMC REG32(STM32_SYSCFG_BASE + 0x04)
+#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
+#define STM32_SYSCFG_CMPCR REG32(STM32_SYSCFG_BASE + 0x20)
+#define STM32_SYSCFG_CFGR REG32(STM32_SYSCFG_BASE + 0x2C)
 
 /* Peripheral bits for RCC_APB/AHB regs */
-#define STM32_RCC_PB2_USART1		BIT(4)
+#define STM32_RCC_PB2_USART1 BIT(4)
 
 /* Reset causes definitions */
 /* Reset causes in RCC CSR register */
 #define STM32_RCC_RESET_CAUSE STM32_RCC_CSR
-#define  RESET_CAUSE_WDG                (BIT(30)|BIT(29))
-#define  RESET_CAUSE_SFT                BIT(28)
-#define  RESET_CAUSE_POR                BIT(27)
-#define  RESET_CAUSE_PIN                BIT(26)
-#define  RESET_CAUSE_OTHER              (BIT(31)|BIT(30)|BIT(29)|BIT(28)| \
-					 BIT(27)|BIT(26)|BIT(25))
-#define  RESET_CAUSE_RMVF                BIT(24)
+#define RESET_CAUSE_WDG (BIT(30) | BIT(29))
+#define RESET_CAUSE_SFT BIT(28)
+#define RESET_CAUSE_POR BIT(27)
+#define RESET_CAUSE_PIN BIT(26)
+#define RESET_CAUSE_OTHER \
+	(BIT(31) | BIT(30) | BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25))
+#define RESET_CAUSE_RMVF BIT(24)
 /* Power cause in PWR CSR register */
 #define STM32_PWR_RESET_CAUSE STM32_PWR_CSR
-#define  RESET_CAUSE_SBF                BIT(1)
+#define RESET_CAUSE_SBF BIT(1)
 #define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR
-#define  RESET_CAUSE_SBF_CLR            BIT(3)
+#define RESET_CAUSE_SBF_CLR BIT(3)
 
 /* --- Watchdogs --- */
 
 /* --- Real-Time Clock --- */
-#define STM32_RTC_TR                REG32(STM32_RTC_BASE + 0x00)
-#define STM32_RTC_DR                REG32(STM32_RTC_BASE + 0x04)
-#define STM32_RTC_CR                REG32(STM32_RTC_BASE + 0x08)
-#define STM32_RTC_CR_BYPSHAD        BIT(5)
-#define STM32_RTC_CR_ALRAE          BIT(8)
-#define STM32_RTC_CR_ALRAIE         BIT(12)
-#define STM32_RTC_ISR               REG32(STM32_RTC_BASE + 0x0C)
-#define STM32_RTC_ISR_ALRAWF        BIT(0)
-#define STM32_RTC_ISR_RSF           BIT(5)
-#define STM32_RTC_ISR_INITF         BIT(6)
-#define STM32_RTC_ISR_INIT          BIT(7)
-#define STM32_RTC_ISR_ALRAF         BIT(8)
-#define STM32_RTC_PRER              REG32(STM32_RTC_BASE + 0x10)
-#define STM32_RTC_PRER_A_MASK       (0x7f << 16)
-#define STM32_RTC_PRER_S_MASK       (0x7fff << 0)
-#define STM32_RTC_WUTR              REG32(STM32_RTC_BASE + 0x14)
-#define STM32_RTC_CALIBR            REG32(STM32_RTC_BASE + 0x18)
-#define STM32_RTC_ALRMAR            REG32(STM32_RTC_BASE + 0x1C)
-#define STM32_RTC_ALRMBR            REG32(STM32_RTC_BASE + 0x20)
-#define STM32_RTC_WPR               REG32(STM32_RTC_BASE + 0x24)
-#define STM32_RTC_SSR               REG32(STM32_RTC_BASE + 0x28)
-#define STM32_RTC_TSTR              REG32(STM32_RTC_BASE + 0x30)
-#define STM32_RTC_TSDR              REG32(STM32_RTC_BASE + 0x34)
-#define STM32_RTC_TAFCR             REG32(STM32_RTC_BASE + 0x40)
-#define STM32_RTC_ALRMASSR          REG32(STM32_RTC_BASE + 0x44)
-#define STM32_RTC_BACKUP(n)         REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
-
-#define STM32_BKP_DATA(n)           STM32_RTC_BACKUP(n)
-#define STM32_BKP_BYTES             80
+#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00)
+#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04)
+#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08)
+#define STM32_RTC_CR_BYPSHAD BIT(5)
+#define STM32_RTC_CR_ALRAE BIT(8)
+#define STM32_RTC_CR_ALRAIE BIT(12)
+#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C)
+#define STM32_RTC_ISR_ALRAWF BIT(0)
+#define STM32_RTC_ISR_RSF BIT(5)
+#define STM32_RTC_ISR_INITF BIT(6)
+#define STM32_RTC_ISR_INIT BIT(7)
+#define STM32_RTC_ISR_ALRAF BIT(8)
+#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10)
+#define STM32_RTC_PRER_A_MASK (0x7f << 16)
+#define STM32_RTC_PRER_S_MASK (0x7fff << 0)
+#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14)
+#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18)
+#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C)
+#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20)
+#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24)
+#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28)
+#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30)
+#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34)
+#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40)
+#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44)
+#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
+
+#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n)
+#define STM32_BKP_BYTES 80
 
 /* --- SPI --- */
 
@@ -651,15 +656,15 @@ struct stm32_spi_regs {
 	uint16_t _pad0;
 	uint16_t cr2;
 	uint16_t _pad1;
-	unsigned sr;
+	unsigned int sr;
 	uint8_t dr;
 	uint8_t _pad2;
 	uint16_t _pad3;
-	unsigned crcpr;
-	unsigned rxcrcr;
-	unsigned txcrcr;
-	unsigned i2scfgr;	/* STM32L only */
-	unsigned i2spr;		/* STM32L only */
+	unsigned int crcpr;
+	unsigned int rxcrcr;
+	unsigned int txcrcr;
+	unsigned int i2scfgr; /* STM32L only */
+	unsigned int i2spr; /* STM32L only */
 };
 /* Must be volatile, or compiler optimizes out repeated accesses */
 typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
@@ -669,185 +674,181 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
 #define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE)
 #define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE)
 
-#define STM32_SPI_CR1_BIDIMODE		BIT(15)
-#define STM32_SPI_CR1_BIDIOE		BIT(14)
-#define STM32_SPI_CR1_CRCEN		BIT(13)
-#define STM32_SPI_CR1_SSM		BIT(9)
-#define STM32_SPI_CR1_SSI		BIT(8)
-#define STM32_SPI_CR1_LSBFIRST		BIT(7)
-#define STM32_SPI_CR1_SPE		BIT(6)
-#define STM32_SPI_CR1_BR_DIV64R		(5 << 3)
-#define STM32_SPI_CR1_BR_DIV4R		BIT(3)
-#define STM32_SPI_CR1_MSTR		BIT(2)
-#define STM32_SPI_CR1_CPOL		BIT(1)
-#define STM32_SPI_CR1_CPHA		BIT(0)
-#define STM32_SPI_CR2_FRXTH		BIT(12)
-#define STM32_SPI_CR2_DATASIZE(n)	(((n) - 1) << 8)
-#define STM32_SPI_CR2_TXEIE		BIT(7)
-#define STM32_SPI_CR2_RXNEIE		BIT(6)
-#define STM32_SPI_CR2_NSSP		BIT(3)
-#define STM32_SPI_CR2_SSOE		BIT(2)
-#define STM32_SPI_CR2_TXDMAEN		BIT(1)
-#define STM32_SPI_CR2_RXDMAEN		BIT(0)
-
-#define STM32_SPI_SR_RXNE		BIT(0)
-#define STM32_SPI_SR_TXE		BIT(1)
-#define STM32_SPI_SR_CRCERR		BIT(4)
-#define STM32_SPI_SR_BSY		BIT(7)
-#define STM32_SPI_SR_FRLVL		(3 << 9)
-#define STM32_SPI_SR_FTLVL		(3 << 11)
+#define STM32_SPI_CR1_BIDIMODE BIT(15)
+#define STM32_SPI_CR1_BIDIOE BIT(14)
+#define STM32_SPI_CR1_CRCEN BIT(13)
+#define STM32_SPI_CR1_SSM BIT(9)
+#define STM32_SPI_CR1_SSI BIT(8)
+#define STM32_SPI_CR1_LSBFIRST BIT(7)
+#define STM32_SPI_CR1_SPE BIT(6)
+#define STM32_SPI_CR1_BR_DIV64R (5 << 3)
+#define STM32_SPI_CR1_BR_DIV4R BIT(3)
+#define STM32_SPI_CR1_MSTR BIT(2)
+#define STM32_SPI_CR1_CPOL BIT(1)
+#define STM32_SPI_CR1_CPHA BIT(0)
+#define STM32_SPI_CR2_FRXTH BIT(12)
+#define STM32_SPI_CR2_DATASIZE(n) (((n)-1) << 8)
+#define STM32_SPI_CR2_TXEIE BIT(7)
+#define STM32_SPI_CR2_RXNEIE BIT(6)
+#define STM32_SPI_CR2_NSSP BIT(3)
+#define STM32_SPI_CR2_SSOE BIT(2)
+#define STM32_SPI_CR2_TXDMAEN BIT(1)
+#define STM32_SPI_CR2_RXDMAEN BIT(0)
+
+#define STM32_SPI_SR_RXNE BIT(0)
+#define STM32_SPI_SR_TXE BIT(1)
+#define STM32_SPI_SR_CRCERR BIT(4)
+#define STM32_SPI_SR_BSY BIT(7)
+#define STM32_SPI_SR_FRLVL (3 << 9)
+#define STM32_SPI_SR_FTLVL (3 << 11)
 
 /* --- Debug --- */
 
-#define  STM32_DBGMCU_CR_SLEEP                      BIT(0)
-#define  STM32_DBGMCU_CR_STOP                       BIT(1)
-#define  STM32_DBGMCU_CR_STBY                       BIT(2)
-#define  STM32_DBGMCU_CR_TRACE_MASK                 (BIT(5)|BIT(6)|BIT(7))
-#define   STM32_DBGMCU_CR_TRACE_EN                   BIT(5)
-#define   STM32_DBGMCU_CR_TRACE_MODE_ASYNC           0
-#define   STM32_DBGMCU_CR_TRACE_MODE_SYNC1           BIT(6)
-#define   STM32_DBGMCU_CR_TRACE_MODE_SYNC2           BIT(7)
-#define   STM32_DBGMCU_CR_TRACE_MODE_SYNC4           (BIT(6)|BIT(7))
-#define STM32_DBGMCU_APB1FZ         REG32(STM32_DBGMCU_BASE + 0x08)
-#define  STM32_DBGMCU_APB1FZ_TIM2                   BIT(0)
-#define  STM32_DBGMCU_APB1FZ_TIM3                   BIT(1)
-#define  STM32_DBGMCU_APB1FZ_TIM4                   BIT(2)
-#define  STM32_DBGMCU_APB1FZ_TIM5                   BIT(3)
-#define  STM32_DBGMCU_APB1FZ_TIM6                   BIT(4)
-#define  STM32_DBGMCU_APB1FZ_TIM7                   BIT(5)
-#define  STM32_DBGMCU_APB1FZ_TIM12                  BIT(6)
-#define  STM32_DBGMCU_APB1FZ_TIM13                  BIT(7)
-#define  STM32_DBGMCU_APB1FZ_TIM14                  BIT(8)
-#define  STM32_DBGMCU_APB1FZ_RTC                    BIT(10)
-#define  STM32_DBGMCU_APB1FZ_WWDG                   BIT(11)
-#define  STM32_DBGMCU_APB1FZ_IWDG                   BIT(12)
-#define  STM32_DBGMCU_APB1FZ_I2C1_SMBUS_TIMEOUT     BIT(21)
-#define  STM32_DBGMCU_APB1FZ_I2C2_SMBUS_TIMEOUT     BIT(22)
-#define  STM32_DBGMCU_APB1FZ_I2C3_SMBUS_TIMEOUT     BIT(23)
-#define  STM32_DBGMCU_APB1FZ_I2CFMP_SMBUS_TIMEOUT   BIT(24)
-#define  STM32_DBGMCU_APB1FZ_CAN1                   BIT(25)
-#define  STM32_DBGMCU_APB1FZ_CAN2                   BIT(26)
-#define STM32_DBGMCU_APB2FZ         REG32(STM32_DBGMCU_BASE + 0x0C)
-#define  STM32_DBGMCU_APB2FZ_TIM1                   BIT(0)
-#define  STM32_DBGMCU_APB2FZ_TIM8                   BIT(1)
-#define  STM32_DBGMCU_APB2FZ_TIM9                   BIT(16)
-#define  STM32_DBGMCU_APB2FZ_TIM10                  BIT(17)
-#define  STM32_DBGMCU_APB2FZ_TIM11                  BIT(18)
+#define STM32_DBGMCU_CR_SLEEP BIT(0)
+#define STM32_DBGMCU_CR_STOP BIT(1)
+#define STM32_DBGMCU_CR_STBY BIT(2)
+#define STM32_DBGMCU_CR_TRACE_MASK (BIT(5) | BIT(6) | BIT(7))
+#define STM32_DBGMCU_CR_TRACE_EN BIT(5)
+#define STM32_DBGMCU_CR_TRACE_MODE_ASYNC 0
+#define STM32_DBGMCU_CR_TRACE_MODE_SYNC1 BIT(6)
+#define STM32_DBGMCU_CR_TRACE_MODE_SYNC2 BIT(7)
+#define STM32_DBGMCU_CR_TRACE_MODE_SYNC4 (BIT(6) | BIT(7))
+#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08)
+#define STM32_DBGMCU_APB1FZ_TIM2 BIT(0)
+#define STM32_DBGMCU_APB1FZ_TIM3 BIT(1)
+#define STM32_DBGMCU_APB1FZ_TIM4 BIT(2)
+#define STM32_DBGMCU_APB1FZ_TIM5 BIT(3)
+#define STM32_DBGMCU_APB1FZ_TIM6 BIT(4)
+#define STM32_DBGMCU_APB1FZ_TIM7 BIT(5)
+#define STM32_DBGMCU_APB1FZ_TIM12 BIT(6)
+#define STM32_DBGMCU_APB1FZ_TIM13 BIT(7)
+#define STM32_DBGMCU_APB1FZ_TIM14 BIT(8)
+#define STM32_DBGMCU_APB1FZ_RTC BIT(10)
+#define STM32_DBGMCU_APB1FZ_WWDG BIT(11)
+#define STM32_DBGMCU_APB1FZ_IWDG BIT(12)
+#define STM32_DBGMCU_APB1FZ_I2C1_SMBUS_TIMEOUT BIT(21)
+#define STM32_DBGMCU_APB1FZ_I2C2_SMBUS_TIMEOUT BIT(22)
+#define STM32_DBGMCU_APB1FZ_I2C3_SMBUS_TIMEOUT BIT(23)
+#define STM32_DBGMCU_APB1FZ_I2CFMP_SMBUS_TIMEOUT BIT(24)
+#define STM32_DBGMCU_APB1FZ_CAN1 BIT(25)
+#define STM32_DBGMCU_APB1FZ_CAN2 BIT(26)
+#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C)
+#define STM32_DBGMCU_APB2FZ_TIM1 BIT(0)
+#define STM32_DBGMCU_APB2FZ_TIM8 BIT(1)
+#define STM32_DBGMCU_APB2FZ_TIM9 BIT(16)
+#define STM32_DBGMCU_APB2FZ_TIM10 BIT(17)
+#define STM32_DBGMCU_APB2FZ_TIM11 BIT(18)
 
 /* --- Flash --- */
-#define STM32_FLASH_ACR             REG32(STM32_FLASH_REGS_BASE + 0x00)
-#define STM32_FLASH_ACR_SHIFT           0
-#define STM32_FLASH_ACR_LAT_MASK        0xf
-#define STM32_FLASH_ACR_PRFTEN          BIT(8)
-#define STM32_FLASH_ACR_ICEN            BIT(9)
-#define STM32_FLASH_ACR_DCEN            BIT(10)
-#define STM32_FLASH_ACR_ICRST           BIT(11)
-#define STM32_FLASH_ACR_DCRST           BIT(12)
-#define STM32_FLASH_KEYR            REG32(STM32_FLASH_REGS_BASE + 0x04)
-#define  FLASH_KEYR_KEY1                0x45670123
-#define  FLASH_KEYR_KEY2                0xCDEF89AB
-#define STM32_FLASH_OPTKEYR         REG32(STM32_FLASH_REGS_BASE + 0x08)
-#define  FLASH_OPTKEYR_KEY1             0x08192A3B
-#define  FLASH_OPTKEYR_KEY2             0x4C5D6E7F
-#define STM32_FLASH_SR              REG32(STM32_FLASH_REGS_BASE + 0x0c)
-#define  FLASH_SR_EOP                   BIT(0)
-#define  FLASH_SR_OPERR                 BIT(1)
-#define  FLASH_SR_WRPERR                BIT(4)
-#define  FLASH_SR_PGAERR                BIT(5)
-#define  FLASH_SR_PGPERR                BIT(6)
-#define  FLASH_SR_PGSERR                BIT(7)
-#define  FLASH_SR_RDERR                 BIT(8)
-#define  FLASH_SR_ALL_ERR \
+#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00)
+#define STM32_FLASH_ACR_SHIFT 0
+#define STM32_FLASH_ACR_LAT_MASK 0xf
+#define STM32_FLASH_ACR_PRFTEN BIT(8)
+#define STM32_FLASH_ACR_ICEN BIT(9)
+#define STM32_FLASH_ACR_DCEN BIT(10)
+#define STM32_FLASH_ACR_ICRST BIT(11)
+#define STM32_FLASH_ACR_DCRST BIT(12)
+#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x04)
+#define FLASH_KEYR_KEY1 0x45670123
+#define FLASH_KEYR_KEY2 0xCDEF89AB
+#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x08)
+#define FLASH_OPTKEYR_KEY1 0x08192A3B
+#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F
+#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x0c)
+#define FLASH_SR_EOP BIT(0)
+#define FLASH_SR_OPERR BIT(1)
+#define FLASH_SR_WRPERR BIT(4)
+#define FLASH_SR_PGAERR BIT(5)
+#define FLASH_SR_PGPERR BIT(6)
+#define FLASH_SR_PGSERR BIT(7)
+#define FLASH_SR_RDERR BIT(8)
+#define FLASH_SR_ALL_ERR                                      \
 	(FLASH_SR_OPERR | FLASH_SR_WRPERR | FLASH_SR_PGAERR | \
 	 FLASH_SR_PGPERR | FLASH_SR_PGSERR | FLASH_SR_RDERR)
-#define  FLASH_SR_BUSY                   BIT(16)
-#define STM32_FLASH_CR              REG32(STM32_FLASH_REGS_BASE + 0x10)
-#define  FLASH_CR_PG                    BIT(0)
-#define  FLASH_CR_PER                   BIT(1)
-#define  FLASH_CR_MER                   BIT(2)
-#define STM32_FLASH_CR_SNB_OFFSET       (3)
-#define STM32_FLASH_CR_SNB(sec) \
-	(((sec) & 0xf) << STM32_FLASH_CR_SNB_OFFSET)
-#define STM32_FLASH_CR_SNB_MASK         (STM32_FLASH_CR_SNB(0xf))
-#define STM32_FLASH_CR_PSIZE_OFFSET     (8)
-#define STM32_FLASH_CR_PSIZE(size) \
-	(((size) & 0x3) << STM32_FLASH_CR_PSIZE_OFFSET)
-#define STM32_FLASH_CR_PSIZE_MASK       (STM32_FLASH_CR_PSIZE(0x3))
-#define  FLASH_CR_STRT                  BIT(16)
-#define  FLASH_CR_LOCK                  BIT(31)
-#define STM32_FLASH_OPTCR           REG32(STM32_FLASH_REGS_BASE + 0x14)
-#define  FLASH_OPTLOCK                  BIT(0)
-#define  FLASH_OPTSTRT                  BIT(1)
-#define STM32_FLASH_BOR_LEV_OFFSET      (2)
-#define  FLASH_OPTCR_RDP_SHIFT		(8)
-#define  FLASH_OPTCR_RDP_MASK		(0xFF << FLASH_OPTCR_RDP_SHIFT)
-#define  FLASH_OPTCR_RDP_LEVEL_0		(0xAA << FLASH_OPTCR_RDP_SHIFT)
+#define FLASH_SR_BUSY BIT(16)
+#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x10)
+#define FLASH_CR_PG BIT(0)
+#define FLASH_CR_PER BIT(1)
+#define FLASH_CR_MER BIT(2)
+#define STM32_FLASH_CR_SNB_OFFSET (3)
+#define STM32_FLASH_CR_SNB(sec) (((sec)&0xf) << STM32_FLASH_CR_SNB_OFFSET)
+#define STM32_FLASH_CR_SNB_MASK (STM32_FLASH_CR_SNB(0xf))
+#define STM32_FLASH_CR_PSIZE_OFFSET (8)
+#define STM32_FLASH_CR_PSIZE(size) (((size)&0x3) << STM32_FLASH_CR_PSIZE_OFFSET)
+#define STM32_FLASH_CR_PSIZE_MASK (STM32_FLASH_CR_PSIZE(0x3))
+#define FLASH_CR_STRT BIT(16)
+#define FLASH_CR_LOCK BIT(31)
+#define STM32_FLASH_OPTCR REG32(STM32_FLASH_REGS_BASE + 0x14)
+#define FLASH_OPTLOCK BIT(0)
+#define FLASH_OPTSTRT BIT(1)
+#define STM32_FLASH_BOR_LEV_OFFSET (2)
+#define FLASH_OPTCR_RDP_SHIFT (8)
+#define FLASH_OPTCR_RDP_MASK (0xFF << FLASH_OPTCR_RDP_SHIFT)
+#define FLASH_OPTCR_RDP_LEVEL_0 (0xAA << FLASH_OPTCR_RDP_SHIFT)
 /* RDP Level 1: Anything but 0xAA/0xCC */
-#define  FLASH_OPTCR_RDP_LEVEL_1		(0x00 << FLASH_OPTCR_RDP_SHIFT)
-#define  FLASH_OPTCR_RDP_LEVEL_2		(0xCC << FLASH_OPTCR_RDP_SHIFT)
-#define STM32_FLASH_nWRP_OFFSET         (16)
-#define STM32_FLASH_nWRP(_bank)         BIT(_bank + STM32_FLASH_nWRP_OFFSET)
-#define STM32_FLASH_nWRP_ALL            (0xFF << STM32_FLASH_nWRP_OFFSET)
-#define STM32_FLASH_OPT_LOCKED      (STM32_FLASH_OPTCR & FLASH_OPTLOCK)
-
-#define STM32_OPTB_RDP_USER         REG32(STM32_OPTB_BASE + 0x00)
-#define STM32_OPTB_RDP_OFF              0x00
-#define STM32_OPTB_USER_OFF             0x02
-#define STM32_OPTB_WRP_OFF(n)       (0x08 + (n&3) * 2)
-#define STM32_OPTB_WP               REG32(STM32_OPTB_BASE + 0x08)
-#define STM32_OPTB_nWRP(_bank)          BIT(_bank)
-#define STM32_OPTB_nWRP_ALL             (0xFF)
-
-#define STM32_OPTB_COMPL_SHIFT      8
-
-#define STM32_OTP_BLOCK_NB              16
-#define STM32_OTP_BLOCK_SIZE            32
+#define FLASH_OPTCR_RDP_LEVEL_1 (0x00 << FLASH_OPTCR_RDP_SHIFT)
+#define FLASH_OPTCR_RDP_LEVEL_2 (0xCC << FLASH_OPTCR_RDP_SHIFT)
+#define STM32_FLASH_nWRP_OFFSET (16)
+#define STM32_FLASH_nWRP(_bank) BIT(_bank + STM32_FLASH_nWRP_OFFSET)
+#define STM32_FLASH_nWRP_ALL (0xFF << STM32_FLASH_nWRP_OFFSET)
+#define STM32_FLASH_OPT_LOCKED (STM32_FLASH_OPTCR & FLASH_OPTLOCK)
+
+#define STM32_OPTB_RDP_USER REG32(STM32_OPTB_BASE + 0x00)
+#define STM32_OPTB_RDP_OFF 0x00
+#define STM32_OPTB_USER_OFF 0x02
+#define STM32_OPTB_WRP_OFF(n) (0x08 + (n & 3) * 2)
+#define STM32_OPTB_WP REG32(STM32_OPTB_BASE + 0x08)
+#define STM32_OPTB_nWRP(_bank) BIT(_bank)
+#define STM32_OPTB_nWRP_ALL (0xFF)
+
+#define STM32_OPTB_COMPL_SHIFT 8
+
+#define STM32_OTP_BLOCK_NB 16
+#define STM32_OTP_BLOCK_SIZE 32
 #define STM32_OTP_BLOCK_DATA(_block, _offset) \
-	(STM32_OTP_BASE + STM32_OTP_BLOCK_SIZE * (_block) + (_offset) * 4)
-#define STM32_OTP_UNLOCK_BYTE           0x00
-#define STM32_OTP_LOCK_BYTE             0xFF
-#define STM32_OTP_LOCK_BASE         \
+	(STM32_OTP_BASE + STM32_OTP_BLOCK_SIZE * (_block) + (_offset)*4)
+#define STM32_OTP_UNLOCK_BYTE 0x00
+#define STM32_OTP_LOCK_BYTE 0xFF
+#define STM32_OTP_LOCK_BASE \
 	(STM32_OTP_BASE + STM32_OTP_BLOCK_NB * STM32_OTP_BLOCK_SIZE)
-#define STM32_OTP_LOCK(_block) \
-	(STM32_OTP_LOCK_BASE + ((_block) / 4) * 4)
-#define STM32_OPT_LOCK_MASK(_block)    ((0xFF << ((_block) % 4) * 8))
+#define STM32_OTP_LOCK(_block) (STM32_OTP_LOCK_BASE + ((_block) / 4) * 4)
+#define STM32_OPT_LOCK_MASK(_block) ((0xFF << ((_block) % 4) * 8))
 
 /* --- External Interrupts --- */
-#define STM32_EXTI_IMR              REG32(STM32_EXTI_BASE + 0x00)
-#define STM32_EXTI_EMR              REG32(STM32_EXTI_BASE + 0x04)
-#define STM32_EXTI_RTSR             REG32(STM32_EXTI_BASE + 0x08)
-#define STM32_EXTI_FTSR             REG32(STM32_EXTI_BASE + 0x0c)
-#define STM32_EXTI_SWIER            REG32(STM32_EXTI_BASE + 0x10)
-#define STM32_EXTI_PR               REG32(STM32_EXTI_BASE + 0x14)
+#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00)
+#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04)
+#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08)
+#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c)
+#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10)
+#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14)
 
 #define EXTI_RTC_ALR_EVENT BIT(17)
 
 /* --- ADC --- */
-#define STM32_ADC_SR               REG32(STM32_ADC1_BASE + 0x00)
-#define STM32_ADC_CR1              REG32(STM32_ADC1_BASE + 0x04)
-#define STM32_ADC_CR2              REG32(STM32_ADC1_BASE + 0x08)
-#define STM32_ADC_CR2_ADON         BIT(0)
-#define STM32_ADC_CR2_CONT         BIT(1)
-#define STM32_ADC_CR2_CAL          BIT(2)
-#define STM32_ADC_CR2_RSTCAL       BIT(3)
-#define STM32_ADC_CR2_ALIGN        BIT(11)
-#define STM32_ADC_CR2_SWSTART      BIT(30)
-#define STM32_ADC_SMPR1            REG32(STM32_ADC1_BASE + 0x0C)
-#define STM32_ADC_SMPR2            REG32(STM32_ADC1_BASE + 0x10)
-#define STM32_ADC_JOFR(n)          REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4)
-#define STM32_ADC_HTR              REG32(STM32_ADC1_BASE + 0x24)
-#define STM32_ADC_LTR              REG32(STM32_ADC1_BASE + 0x28)
-#define STM32_ADC_SQR(n)           REG32(STM32_ADC1_BASE + 0x28 + ((n)&3) * 4)
-#define STM32_ADC_SQR1             REG32(STM32_ADC1_BASE + 0x2C)
-#define STM32_ADC_SQR2             REG32(STM32_ADC1_BASE + 0x30)
-#define STM32_ADC_SQR3             REG32(STM32_ADC1_BASE + 0x34)
-#define STM32_ADC_JSQR             REG32(STM32_ADC1_BASE + 0x38)
-#define STM32_ADC_JDR(n)           REG32(STM32_ADC1_BASE + 0x3C + ((n)&3) * 4)
-#define STM32_ADC_DR               REG32(STM32_ADC1_BASE + 0x4C)
+#define STM32_ADC_SR REG32(STM32_ADC1_BASE + 0x00)
+#define STM32_ADC_CR1 REG32(STM32_ADC1_BASE + 0x04)
+#define STM32_ADC_CR2 REG32(STM32_ADC1_BASE + 0x08)
+#define STM32_ADC_CR2_ADON BIT(0)
+#define STM32_ADC_CR2_CONT BIT(1)
+#define STM32_ADC_CR2_CAL BIT(2)
+#define STM32_ADC_CR2_RSTCAL BIT(3)
+#define STM32_ADC_CR2_ALIGN BIT(11)
+#define STM32_ADC_CR2_SWSTART BIT(30)
+#define STM32_ADC_SMPR1 REG32(STM32_ADC1_BASE + 0x0C)
+#define STM32_ADC_SMPR2 REG32(STM32_ADC1_BASE + 0x10)
+#define STM32_ADC_JOFR(n) REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4)
+#define STM32_ADC_HTR REG32(STM32_ADC1_BASE + 0x24)
+#define STM32_ADC_LTR REG32(STM32_ADC1_BASE + 0x28)
+#define STM32_ADC_SQR(n) REG32(STM32_ADC1_BASE + 0x28 + ((n)&3) * 4)
+#define STM32_ADC_SQR1 REG32(STM32_ADC1_BASE + 0x2C)
+#define STM32_ADC_SQR2 REG32(STM32_ADC1_BASE + 0x30)
+#define STM32_ADC_SQR3 REG32(STM32_ADC1_BASE + 0x34)
+#define STM32_ADC_JSQR REG32(STM32_ADC1_BASE + 0x38)
+#define STM32_ADC_JDR(n) REG32(STM32_ADC1_BASE + 0x3C + ((n)&3) * 4)
+#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x4C)
 
 /* --- Comparators --- */
 
-
 /* --- DMA --- */
 /*
  * Available DMA streams, numbered from 0.
@@ -915,7 +916,7 @@ enum dma_channel {
 	STM32_DMAC_FMPI2C4_TX = STM32_DMA1_STREAM5,
 	STM32_DMAC_FMPI2C4_RX = STM32_DMA1_STREAM2,
 
-	/* Legacy naming for spi_master.c */
+	/* Legacy naming for spi_controller.c */
 	STM32_DMAC_SPI1_TX = STM32_DMA2_STREAM3, /* REQ 3 */
 	STM32_DMAC_SPI1_RX = STM32_DMA2_STREAM0, /* REQ 3 */
 	STM32_DMAC_SPI2_TX = STM32_DMA1_STREAM4, /* REQ 0 */
@@ -955,12 +956,12 @@ enum dma_channel {
 
 /* Registers for a single stream of a DMA controller */
 struct stm32_dma_stream {
-	uint32_t	scr;		/* Control */
-	uint32_t	sndtr;		/* Number of data to transfer */
-	uint32_t	spar;		/* Peripheral address */
-	uint32_t	sm0ar;		/* Memory address 0 */
-	uint32_t	sm1ar;		/*  address 1 for double buffer */
-	uint32_t	sfcr;		/* FIFO control */
+	uint32_t scr; /* Control */
+	uint32_t sndtr; /* Number of data to transfer */
+	uint32_t spar; /* Peripheral address */
+	uint32_t sm0ar; /* Memory address 0 */
+	uint32_t sm1ar; /*  address 1 for double buffer */
+	uint32_t sfcr; /* FIFO control */
 };
 
 /* Always use stm32_dma_stream_t so volatile keyword is included! */
@@ -969,12 +970,11 @@ typedef volatile struct stm32_dma_stream stm32_dma_stream_t;
 /* Common code and header file must use this */
 typedef stm32_dma_stream_t dma_chan_t;
 struct stm32_dma_regs {
-	uint32_t	isr[2];
-	uint32_t	ifcr[2];
+	uint32_t isr[2];
+	uint32_t ifcr[2];
 	stm32_dma_stream_t stream[STM32_DMAS_COUNT];
 };
 
-
 /* Always use stm32_dma_regs_t so volatile keyword is included! */
 typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
 
@@ -985,184 +985,106 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
 #define STM32_DMA_REGS(channel) \
 	((channel) < STM32_DMAS_COUNT ? STM32_DMA1_REGS : STM32_DMA2_REGS)
 
-#define STM32_DMA_CCR_EN                BIT(0)
-#define STM32_DMA_CCR_DMEIE             BIT(1)
-#define STM32_DMA_CCR_TEIE              BIT(2)
-#define STM32_DMA_CCR_HTIE              BIT(3)
-#define STM32_DMA_CCR_TCIE              BIT(4)
-#define STM32_DMA_CCR_PFCTRL            BIT(5)
-#define STM32_DMA_CCR_DIR_P2M		(0 << 6)
-#define STM32_DMA_CCR_DIR_M2P		(1 << 6)
-#define STM32_DMA_CCR_DIR_M2M		(2 << 6)
-#define STM32_DMA_CCR_CIRC              BIT(8)
-#define STM32_DMA_CCR_PINC              BIT(9)
-#define STM32_DMA_CCR_MINC              BIT(10)
-#define STM32_DMA_CCR_PSIZE_8_BIT       (0 << 11)
-#define STM32_DMA_CCR_PSIZE_16_BIT      (1 << 11)
-#define STM32_DMA_CCR_PSIZE_32_BIT      (2 << 11)
-#define STM32_DMA_CCR_MSIZE_8_BIT       (0 << 13)
-#define STM32_DMA_CCR_MSIZE_16_BIT      (1 << 13)
-#define STM32_DMA_CCR_MSIZE_32_BIT      (2 << 13)
-#define STM32_DMA_CCR_PINCOS            BIT(15)
-#define STM32_DMA_CCR_PL_LOW            (0 << 16)
-#define STM32_DMA_CCR_PL_MEDIUM         (1 << 16)
-#define STM32_DMA_CCR_PL_HIGH           (2 << 16)
-#define STM32_DMA_CCR_PL_VERY_HIGH      (3 << 16)
-#define STM32_DMA_CCR_DBM               BIT(18)
-#define STM32_DMA_CCR_CT                BIT(19)
-#define STM32_DMA_CCR_PBURST(b_len)		 ((((b_len) - 4) / 4) << 21)
-#define STM32_DMA_CCR_MBURST(b_len)		 ((((b_len) - 4) / 4) << 21)
-#define STM32_DMA_CCR_CHANNEL_MASK		 (0x7 << 25)
-#define STM32_DMA_CCR_CHANNEL(channel)		 ((channel) << 25)
-#define STM32_DMA_CCR_RSVD_MASK		(0xF0100000)
-
-
-#define STM32_DMA_SFCR_DMDIS		BIT(2)
-#define STM32_DMA_SFCR_FTH(level)	(((level) - 1) << 0)
-
-
-#define STM32_DMA_CH_LOCAL(channel)     ((channel) % STM32_DMAS_COUNT)
-#define STM32_DMA_CH_LH(channel)        \
-	((STM32_DMA_CH_LOCAL(channel) < 4) ? 0 : 1)
-#define STM32_DMA_CH_OFFSET(channel)    \
+#define STM32_DMA_CCR_EN BIT(0)
+#define STM32_DMA_CCR_DMEIE BIT(1)
+#define STM32_DMA_CCR_TEIE BIT(2)
+#define STM32_DMA_CCR_HTIE BIT(3)
+#define STM32_DMA_CCR_TCIE BIT(4)
+#define STM32_DMA_CCR_PFCTRL BIT(5)
+#define STM32_DMA_CCR_DIR_P2M (0 << 6)
+#define STM32_DMA_CCR_DIR_M2P (1 << 6)
+#define STM32_DMA_CCR_DIR_M2M (2 << 6)
+#define STM32_DMA_CCR_CIRC BIT(8)
+#define STM32_DMA_CCR_PINC BIT(9)
+#define STM32_DMA_CCR_MINC BIT(10)
+#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 11)
+#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 11)
+#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 11)
+#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 13)
+#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 13)
+#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 13)
+#define STM32_DMA_CCR_PINCOS BIT(15)
+#define STM32_DMA_CCR_PL_LOW (0 << 16)
+#define STM32_DMA_CCR_PL_MEDIUM (1 << 16)
+#define STM32_DMA_CCR_PL_HIGH (2 << 16)
+#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 16)
+#define STM32_DMA_CCR_DBM BIT(18)
+#define STM32_DMA_CCR_CT BIT(19)
+#define STM32_DMA_CCR_PBURST(b_len) ((((b_len)-4) / 4) << 21)
+#define STM32_DMA_CCR_MBURST(b_len) ((((b_len)-4) / 4) << 21)
+#define STM32_DMA_CCR_CHANNEL_MASK (0x7 << 25)
+#define STM32_DMA_CCR_CHANNEL(channel) ((channel) << 25)
+#define STM32_DMA_CCR_RSVD_MASK (0xF0100000)
+
+#define STM32_DMA_SFCR_DMDIS BIT(2)
+#define STM32_DMA_SFCR_FTH(level) (((level)-1) << 0)
+
+#define STM32_DMA_CH_LOCAL(channel) ((channel) % STM32_DMAS_COUNT)
+#define STM32_DMA_CH_LH(channel) ((STM32_DMA_CH_LOCAL(channel) < 4) ? 0 : 1)
+#define STM32_DMA_CH_OFFSET(channel)               \
 	(((STM32_DMA_CH_LOCAL(channel) % 4) * 6) + \
-	(((STM32_DMA_CH_LOCAL(channel) % 4) >= 2) ? 4 : 0))
+	 (((STM32_DMA_CH_LOCAL(channel) % 4) >= 2) ? 4 : 0))
 #define STM32_DMA_CH_GETBITS(channel, val) \
 	(((val) >> STM32_DMA_CH_OFFSET(channel)) & 0x3f)
-#define STM32_DMA_GET_IFCR(channel)      \
-	(STM32_DMA_CH_GETBITS(channel,   \
-	STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)]))
-#define STM32_DMA_GET_ISR(channel)       \
-	(STM32_DMA_CH_GETBITS(channel,   \
-	STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)]))
-
-#define STM32_DMA_SET_IFCR(channel, val) \
-	(STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] = \
-	(STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] & \
-	~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel)))
-#define STM32_DMA_SET_ISR(channel, val) \
-	(STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] = \
-	(STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] & \
-	~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel)))
-
-#define STM32_DMA_FEIF                  BIT(0)
-#define STM32_DMA_DMEIF                 BIT(2)
-#define STM32_DMA_TEIF                  BIT(3)
-#define STM32_DMA_HTIF                  BIT(4)
-#define STM32_DMA_TCIF                  BIT(5)
-#define STM32_DMA_ALL                   0x3d
-
-
+#define STM32_DMA_GET_IFCR(channel) \
+	(STM32_DMA_CH_GETBITS(      \
+		channel,            \
+		STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)]))
+#define STM32_DMA_GET_ISR(channel) \
+	(STM32_DMA_CH_GETBITS(     \
+		channel,           \
+		STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)]))
+
+#define STM32_DMA_SET_IFCR(channel, val)                                    \
+	(STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] =          \
+		 (STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] & \
+		  ~(0x3f << STM32_DMA_CH_OFFSET(channel))) |                \
+		 (((val)&0x3f) << STM32_DMA_CH_OFFSET(channel)))
+#define STM32_DMA_SET_ISR(channel, val)                                    \
+	(STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] =          \
+		 (STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] & \
+		  ~(0x3f << STM32_DMA_CH_OFFSET(channel))) |               \
+		 (((val)&0x3f) << STM32_DMA_CH_OFFSET(channel)))
+
+#define STM32_DMA_FEIF BIT(0)
+#define STM32_DMA_DMEIF BIT(2)
+#define STM32_DMA_TEIF BIT(3)
+#define STM32_DMA_HTIF BIT(4)
+#define STM32_DMA_TCIF BIT(5)
+#define STM32_DMA_ALL 0x3d
 
 /* --- CRC --- */
-#define STM32_CRC_DR                REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR32              REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR16              REG16(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR8               REG8(STM32_CRC_BASE + 0x0)
-
-#define STM32_CRC_IDR               REG32(STM32_CRC_BASE + 0x4)
-#define STM32_CRC_CR                REG32(STM32_CRC_BASE + 0x8)
-#define STM32_CRC_INIT              REG32(STM32_CRC_BASE + 0x10)
-#define STM32_CRC_POL               REG32(STM32_CRC_BASE + 0x14)
-
-#define STM32_CRC_CR_RESET          BIT(0)
-#define STM32_CRC_CR_POLYSIZE_32    (0 << 3)
-#define STM32_CRC_CR_POLYSIZE_16    (1 << 3)
-#define STM32_CRC_CR_POLYSIZE_8     (2 << 3)
-#define STM32_CRC_CR_POLYSIZE_7     (3 << 3)
-#define STM32_CRC_CR_REV_IN_BYTE    (1 << 5)
-#define STM32_CRC_CR_REV_IN_HWORD   (2 << 5)
-#define STM32_CRC_CR_REV_IN_WORD    (3 << 5)
-#define STM32_CRC_CR_REV_OUT        BIT(7)
-
-/* --- PMSE --- */
-#define STM32_PMSE_ARCR             REG32(STM32_PMSE_BASE + 0x0)
-#define STM32_PMSE_ACCR             REG32(STM32_PMSE_BASE + 0x4)
-#define STM32_PMSE_CR               REG32(STM32_PMSE_BASE + 0x8)
-#define STM32_PMSE_CRTDR            REG32(STM32_PMSE_BASE + 0x14)
-#define STM32_PMSE_IER              REG32(STM32_PMSE_BASE + 0x18)
-#define STM32_PMSE_SR               REG32(STM32_PMSE_BASE + 0x1c)
-#define STM32_PMSE_IFCR             REG32(STM32_PMSE_BASE + 0x20)
-#define STM32_PMSE_PxPMR(x)         REG32(STM32_PMSE_BASE + 0x2c + (x) * 4)
-#define STM32_PMSE_PAPMR            REG32(STM32_PMSE_BASE + 0x2c)
-#define STM32_PMSE_PBPMR            REG32(STM32_PMSE_BASE + 0x30)
-#define STM32_PMSE_PCPMR            REG32(STM32_PMSE_BASE + 0x34)
-#define STM32_PMSE_PDPMR            REG32(STM32_PMSE_BASE + 0x38)
-#define STM32_PMSE_PEPMR            REG32(STM32_PMSE_BASE + 0x3c)
-#define STM32_PMSE_PFPMR            REG32(STM32_PMSE_BASE + 0x40)
-#define STM32_PMSE_PGPMR            REG32(STM32_PMSE_BASE + 0x44)
-#define STM32_PMSE_PHPMR            REG32(STM32_PMSE_BASE + 0x48)
-#define STM32_PMSE_PIPMR            REG32(STM32_PMSE_BASE + 0x4c)
-#define STM32_PMSE_MRCR             REG32(STM32_PMSE_BASE + 0x100)
-#define STM32_PMSE_MCCR             REG32(STM32_PMSE_BASE + 0x104)
-
-/* --- USB --- */
-#define STM32_USB_EP(n)            REG16(STM32_USB_FS_BASE + (n) * 4)
-
-#define STM32_USB_CNTR             REG16(STM32_USB_FS_BASE + 0x40)
-
-#define STM32_USB_CNTR_FRES	    BIT(0)
-#define STM32_USB_CNTR_PDWN	    BIT(1)
-#define STM32_USB_CNTR_LP_MODE	    BIT(2)
-#define STM32_USB_CNTR_FSUSP	    BIT(3)
-#define STM32_USB_CNTR_RESUME	    BIT(4)
-#define STM32_USB_CNTR_L1RESUME	    BIT(5)
-#define STM32_USB_CNTR_L1REQM	    BIT(7)
-#define STM32_USB_CNTR_ESOFM	    BIT(8)
-#define STM32_USB_CNTR_SOFM	    BIT(9)
-#define STM32_USB_CNTR_RESETM	    BIT(10)
-#define STM32_USB_CNTR_SUSPM	    BIT(11)
-#define STM32_USB_CNTR_WKUPM	    BIT(12)
-#define STM32_USB_CNTR_ERRM	    BIT(13)
-#define STM32_USB_CNTR_PMAOVRM	    BIT(14)
-#define STM32_USB_CNTR_CTRM	    BIT(15)
-
-#define STM32_USB_ISTR             REG16(STM32_USB_FS_BASE + 0x44)
-
-#define STM32_USB_ISTR_EP_ID_MASK   (0x000f)
-#define STM32_USB_ISTR_DIR	    BIT(4)
-#define STM32_USB_ISTR_L1REQ	    BIT(7)
-#define STM32_USB_ISTR_ESOF	    BIT(8)
-#define STM32_USB_ISTR_SOF	    BIT(9)
-#define STM32_USB_ISTR_RESET	    BIT(10)
-#define STM32_USB_ISTR_SUSP	    BIT(11)
-#define STM32_USB_ISTR_WKUP	    BIT(12)
-#define STM32_USB_ISTR_ERR	    BIT(13)
-#define STM32_USB_ISTR_PMAOVR	    BIT(14)
-#define STM32_USB_ISTR_CTR	    BIT(15)
-
-#define STM32_USB_FNR              REG16(STM32_USB_FS_BASE + 0x48)
-
-#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14)
-#define STM32_USB_FNR_RXDP_RXDM_MASK  (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT)
-
-#define STM32_USB_DADDR            REG16(STM32_USB_FS_BASE + 0x4C)
-#define STM32_USB_BTABLE           REG16(STM32_USB_FS_BASE + 0x50)
-#define STM32_USB_LPMCSR           REG16(STM32_USB_FS_BASE + 0x54)
-#define STM32_USB_BCDR             REG16(STM32_USB_FS_BASE + 0x58)
-
-#define STM32_USB_BCDR_BCDEN	    BIT(0)
-#define STM32_USB_BCDR_DCDEN	    BIT(1)
-#define STM32_USB_BCDR_PDEN	    BIT(2)
-#define STM32_USB_BCDR_SDEN	    BIT(3)
-#define STM32_USB_BCDR_DCDET	    BIT(4)
-#define STM32_USB_BCDR_PDET	    BIT(5)
-#define STM32_USB_BCDR_SDET	    BIT(6)
-#define STM32_USB_BCDR_PS2DET	    BIT(7)
-
-#define EP_MASK     0x0F0F
-#define EP_TX_DTOG  0x0040
-#define EP_TX_MASK  0x0030
+#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0)
+
+#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4)
+#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8)
+#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10)
+#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14)
+
+#define STM32_CRC_CR_RESET BIT(0)
+#define STM32_CRC_CR_POLYSIZE_32 (0 << 3)
+#define STM32_CRC_CR_POLYSIZE_16 (1 << 3)
+#define STM32_CRC_CR_POLYSIZE_8 (2 << 3)
+#define STM32_CRC_CR_POLYSIZE_7 (3 << 3)
+#define STM32_CRC_CR_REV_IN_BYTE (1 << 5)
+#define STM32_CRC_CR_REV_IN_HWORD (2 << 5)
+#define STM32_CRC_CR_REV_IN_WORD (3 << 5)
+#define STM32_CRC_CR_REV_OUT BIT(7)
+
+#define EP_MASK 0x0F0F
+#define EP_TX_DTOG 0x0040
+#define EP_TX_MASK 0x0030
 #define EP_TX_VALID 0x0030
-#define EP_TX_NAK   0x0020
+#define EP_TX_NAK 0x0020
 #define EP_TX_STALL 0x0010
 #define EP_TX_DISAB 0x0000
-#define EP_RX_DTOG  0x4000
-#define EP_RX_MASK  0x3000
+#define EP_RX_DTOG 0x4000
+#define EP_RX_MASK 0x3000
 #define EP_RX_VALID 0x3000
-#define EP_RX_NAK   0x2000
+#define EP_RX_NAK 0x2000
 #define EP_RX_STALL 0x1000
 #define EP_RX_DISAB 0x0000
 
@@ -1172,28 +1094,27 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
 #define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID)
 
 #define STM32_TOGGLE_EP(n, mask, val, flags) \
-	STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \
-			^ (val)) | (flags))
+	STM32_USB_EP(n) =                    \
+		(((STM32_USB_EP(n) & (EP_MASK | (mask))) ^ (val)) | (flags))
 
 /* --- TRNG --- */
-#define STM32_RNG_CR                REG32(STM32_RNG_BASE + 0x0)
-#define STM32_RNG_CR_RNGEN          BIT(2)
-#define STM32_RNG_CR_IE             BIT(3)
-#define STM32_RNG_CR_CED            BIT(5)
-#define STM32_RNG_SR                REG32(STM32_RNG_BASE + 0x4)
-#define STM32_RNG_SR_DRDY           BIT(0)
-#define STM32_RNG_DR                REG32(STM32_RNG_BASE + 0x8)
+#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0)
+#define STM32_RNG_CR_RNGEN BIT(2)
+#define STM32_RNG_CR_IE BIT(3)
+#define STM32_RNG_CR_CED BIT(5)
+#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4)
+#define STM32_RNG_SR_DRDY BIT(0)
+#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8)
 
 /* --- AXI interconnect --- */
 
 /* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */
-#define STM32_AXI_TARG_FN_MOD(x)    REG32(STM32_GPV_BASE + 0x1108 + \
-					  0x1000 * (x))
-#define  WRITE_ISS_OVERRIDE         BIT(1)
-#define  READ_ISS_OVERRIDE          BIT(0)
+#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + 0x1000 * (x))
+#define WRITE_ISS_OVERRIDE BIT(1)
+#define READ_ISS_OVERRIDE BIT(0)
 
 /* --- MISC --- */
-#define STM32_UNIQUE_ID_ADDRESS     REG32_ADDR(STM32_UNIQUE_ID_BASE)
-#define STM32_UNIQUE_ID_LENGTH      (3 * 4)
+#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE)
+#define STM32_UNIQUE_ID_LENGTH (3 * 4)
 
 #endif /* !__ASSEMBLER__ */
diff --git a/chip/stm32/registers-stm32f7.h b/chip/stm32/registers-stm32f7.h
index 2245d6775f..37c89bbe07 100644
--- a/chip/stm32/registers-stm32f7.h
+++ b/chip/stm32/registers-stm32f7.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,100 +19,99 @@
 #endif
 
 /* --- IRQ numbers --- */
-#define STM32_IRQ_WWDG             0
-#define STM32_IRQ_PVD              1
-#define STM32_IRQ_TAMPER_STAMP     2
-#define STM32_IRQ_RTC_WAKEUP       3
-#define STM32_IRQ_FLASH            4
-#define STM32_IRQ_RCC              5
-#define STM32_IRQ_EXTI0            6
-#define STM32_IRQ_EXTI1            7
-#define STM32_IRQ_EXTI2            8
-#define STM32_IRQ_EXTI3            9
-#define STM32_IRQ_EXTI4           10
-#define STM32_IRQ_DMA_CHANNEL_1   11
-#define STM32_IRQ_DMA_CHANNEL_2   12
-#define STM32_IRQ_DMA_CHANNEL_3   13
-#define STM32_IRQ_DMA_CHANNEL_4   14
-#define STM32_IRQ_DMA_CHANNEL_5   15
-#define STM32_IRQ_DMA_CHANNEL_6   16
-#define STM32_IRQ_DMA_CHANNEL_7   17
-#define STM32_IRQ_USB_HP          19
-#define STM32_IRQ_USB_LP          20
-
-#define STM32_IRQ_ADC1            18 /* STM32L4 only */
-#define STM32_IRQ_CAN_TX          19 /* STM32F373 only */
-#define STM32_IRQ_USB_LP_CAN_RX   20 /* STM32F373 only */
-#define STM32_IRQ_DAC             21
-#define STM32_IRQ_CAN_RX1         21 /* STM32F373 only */
-
-#define STM32_IRQ_COMP            22
-
-#define STM32_IRQ_CAN_SCE         22 /* STM32F373 only */
-#define STM32_IRQ_EXTI9_5         23
-#define STM32_IRQ_LCD             24 /* STM32L15X only */
-#define STM32_IRQ_TIM15           24 /* STM32F373 only */
-#define STM32_IRQ_TIM9            25 /* STM32L15X only */
-#define STM32_IRQ_TIM16           25 /* STM32F373 only */
-#define STM32_IRQ_TIM10           26 /* STM32L15X only */
-#define STM32_IRQ_TIM17           26 /* STM32F373 only */
-#define STM32_IRQ_TIM11           27 /* STM32L15X only */
-#define STM32_IRQ_TIM18_DAC2      27 /* STM32F373 only */
-#define STM32_IRQ_TIM2            28
-#define STM32_IRQ_TIM3            29
-#define STM32_IRQ_TIM4            30
-#define STM32_IRQ_I2C1_EV         31
-#define STM32_IRQ_I2C1_ER         32
-#define STM32_IRQ_I2C2_EV         33
-#define STM32_IRQ_I2C2_ER         34
-#define STM32_IRQ_SPI1            35
-#define STM32_IRQ_SPI2            36
-#define STM32_IRQ_USART1          37
-#define STM32_IRQ_USART2          38
-#define STM32_IRQ_USART3          39
-#define STM32_IRQ_EXTI15_10       40
-#define STM32_IRQ_RTC_ALARM       41
-#define STM32_IRQ_USB_FS_WAKEUP   42 /* STM32L15X */
-#define STM32_IRQ_CEC             42 /* STM32F373 only */
-#define STM32_IRQ_TIM6_BASIC      43 /* STM32L15X only */
-#define STM32_IRQ_TIM12           43 /* STM32F373 only */
-#define STM32_IRQ_TIM7_BASIC      44 /* STM32L15X only */
-#define STM32_IRQ_TIM13           44 /* STM32F373 only */
-#define STM32_IRQ_TIM14           45 /* STM32F373 only */
-#define STM32_IRQ_TIM5            50 /* STM32F373 */
-#define STM32_IRQ_SPI3            51 /* STM32F373 */
-#define STM32_IRQ_USART4          52 /* STM32F446 only */
-#define STM32_IRQ_USART5          53 /* STM32F446 only */
-#define STM32_IRQ_TIM6_DAC        54 /* STM32F373 */
-#define STM32_IRQ_TIM7            55 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL1   56 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL2   57 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL3   58 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL4   59 /* STM32F373 only */
+#define STM32_IRQ_WWDG 0
+#define STM32_IRQ_PVD 1
+#define STM32_IRQ_TAMPER_STAMP 2
+#define STM32_IRQ_RTC_WAKEUP 3
+#define STM32_IRQ_FLASH 4
+#define STM32_IRQ_RCC 5
+#define STM32_IRQ_EXTI0 6
+#define STM32_IRQ_EXTI1 7
+#define STM32_IRQ_EXTI2 8
+#define STM32_IRQ_EXTI3 9
+#define STM32_IRQ_EXTI4 10
+#define STM32_IRQ_DMA_CHANNEL_1 11
+#define STM32_IRQ_DMA_CHANNEL_2 12
+#define STM32_IRQ_DMA_CHANNEL_3 13
+#define STM32_IRQ_DMA_CHANNEL_4 14
+#define STM32_IRQ_DMA_CHANNEL_5 15
+#define STM32_IRQ_DMA_CHANNEL_6 16
+#define STM32_IRQ_DMA_CHANNEL_7 17
+#define STM32_IRQ_USB_HP 19
+#define STM32_IRQ_USB_LP 20
+
+#define STM32_IRQ_ADC1 18 /* STM32L4 only */
+#define STM32_IRQ_CAN_TX 19 /* STM32F373 only */
+#define STM32_IRQ_USB_LP_CAN_RX 20 /* STM32F373 only */
+#define STM32_IRQ_DAC 21
+#define STM32_IRQ_CAN_RX1 21 /* STM32F373 only */
+
+#define STM32_IRQ_COMP 22
+
+#define STM32_IRQ_CAN_SCE 22 /* STM32F373 only */
+#define STM32_IRQ_EXTI9_5 23
+#define STM32_IRQ_LCD 24 /* STM32L15X only */
+#define STM32_IRQ_TIM15 24 /* STM32F373 only */
+#define STM32_IRQ_TIM9 25 /* STM32L15X only */
+#define STM32_IRQ_TIM16 25 /* STM32F373 only */
+#define STM32_IRQ_TIM10 26 /* STM32L15X only */
+#define STM32_IRQ_TIM17 26 /* STM32F373 only */
+#define STM32_IRQ_TIM11 27 /* STM32L15X only */
+#define STM32_IRQ_TIM18_DAC2 27 /* STM32F373 only */
+#define STM32_IRQ_TIM2 28
+#define STM32_IRQ_TIM3 29
+#define STM32_IRQ_TIM4 30
+#define STM32_IRQ_I2C1_EV 31
+#define STM32_IRQ_I2C1_ER 32
+#define STM32_IRQ_I2C2_EV 33
+#define STM32_IRQ_I2C2_ER 34
+#define STM32_IRQ_SPI1 35
+#define STM32_IRQ_SPI2 36
+#define STM32_IRQ_USART1 37
+#define STM32_IRQ_USART2 38
+#define STM32_IRQ_USART3 39
+#define STM32_IRQ_EXTI15_10 40
+#define STM32_IRQ_RTC_ALARM 41
+#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X */
+#define STM32_IRQ_CEC 42 /* STM32F373 only */
+#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */
+#define STM32_IRQ_TIM12 43 /* STM32F373 only */
+#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */
+#define STM32_IRQ_TIM13 44 /* STM32F373 only */
+#define STM32_IRQ_TIM14 45 /* STM32F373 only */
+#define STM32_IRQ_TIM5 50 /* STM32F373 */
+#define STM32_IRQ_SPI3 51 /* STM32F373 */
+#define STM32_IRQ_USART4 52 /* STM32F446 only */
+#define STM32_IRQ_USART5 53 /* STM32F446 only */
+#define STM32_IRQ_TIM6_DAC 54 /* STM32F373 */
+#define STM32_IRQ_TIM7 55 /* STM32F373 */
+#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F373 */
+#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F373 */
+#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F373 */
+#define STM32_IRQ_DMA2_CHANNEL4 59 /* STM32F373 only */
 /* if MISC_REMAP bits are set */
-#define STM32_IRQ_DMA2_CHANNEL5   60 /* STM32F373 */
-#define STM32_IRQ_SDADC1          61 /* STM32F373 only */
-#define STM32_IRQ_SDADC2          62 /* STM32F373 only */
-#define STM32_IRQ_SDADC3          63 /* STM32F373 only */
-#define STM32_IRQ_DMA2_CHANNEL6   68 /* STM32L4 only */
-#define STM32_IRQ_DMA2_CHANNEL7   69 /* STM32L4 only */
-#define STM32_IRQ_LPUART          70 /* STM32L4 only */
-#define STM32_IRQ_USART9          70 /* STM32L4 only */
-#define STM32_IRQ_USART6          71 /* STM32F446 only */
-#define STM32_IRQ_I2C3_EV         72 /* STM32F446 only */
-#define STM32_IRQ_I2C3_ER         73 /* STM32F446 only */
-#define STM32_IRQ_USB_WAKEUP      76 /* STM32F373 only */
-#define STM32_IRQ_TIM19           78 /* STM32F373 only */
-#define STM32_IRQ_AES             79 /* STM32L4 only */
-#define STM32_IRQ_RNG             80 /* STM32L4 only */
-#define STM32_IRQ_FPU             81 /* STM32F373 only */
-
+#define STM32_IRQ_DMA2_CHANNEL5 60 /* STM32F373 */
+#define STM32_IRQ_SDADC1 61 /* STM32F373 only */
+#define STM32_IRQ_SDADC2 62 /* STM32F373 only */
+#define STM32_IRQ_SDADC3 63 /* STM32F373 only */
+#define STM32_IRQ_DMA2_CHANNEL6 68 /* STM32L4 only */
+#define STM32_IRQ_DMA2_CHANNEL7 69 /* STM32L4 only */
+#define STM32_IRQ_LPUART 70 /* STM32L4 only */
+#define STM32_IRQ_USART9 70 /* STM32L4 only */
+#define STM32_IRQ_USART6 71 /* STM32F446 only */
+#define STM32_IRQ_I2C3_EV 72 /* STM32F446 only */
+#define STM32_IRQ_I2C3_ER 73 /* STM32F446 only */
+#define STM32_IRQ_USB_WAKEUP 76 /* STM32F373 only */
+#define STM32_IRQ_TIM19 78 /* STM32F373 only */
+#define STM32_IRQ_AES 79 /* STM32L4 only */
+#define STM32_IRQ_RNG 80 /* STM32L4 only */
+#define STM32_IRQ_FPU 81 /* STM32F373 only */
 
 /* To simplify code generation, define DMA channel 9..10 */
-#define STM32_IRQ_DMA_CHANNEL_9    STM32_IRQ_DMA2_CHANNEL1
-#define STM32_IRQ_DMA_CHANNEL_10   STM32_IRQ_DMA2_CHANNEL2
-#define STM32_IRQ_DMA_CHANNEL_13   STM32_IRQ_DMA2_CHANNEL6
-#define STM32_IRQ_DMA_CHANNEL_14   STM32_IRQ_DMA2_CHANNEL7
+#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1
+#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2
+#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6
+#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7
 
 /* aliases for easier code sharing */
 #define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV
@@ -123,464 +122,462 @@
  * STM32F4 introduces a concept of DMA stream to allow
  * fine allocation of a stream to a channel.
  */
-#define STM32_IRQ_DMA1_STREAM0    11
-#define STM32_IRQ_DMA1_STREAM1    12
-#define STM32_IRQ_DMA1_STREAM2    13
-#define STM32_IRQ_DMA1_STREAM3    14
-#define STM32_IRQ_DMA1_STREAM4    15
-#define STM32_IRQ_DMA1_STREAM5    16
-#define STM32_IRQ_DMA1_STREAM6    17
-#define STM32_IRQ_DMA1_STREAM7    47
-#define STM32_IRQ_DMA2_STREAM0    56
-#define STM32_IRQ_DMA2_STREAM1    57
-#define STM32_IRQ_DMA2_STREAM2    58
-#define STM32_IRQ_DMA2_STREAM3    59
-#define STM32_IRQ_DMA2_STREAM4    60
-#define STM32_IRQ_DMA2_STREAM5    68
-#define STM32_IRQ_DMA2_STREAM6    69
-#define STM32_IRQ_DMA2_STREAM7    70
-
-#define STM32_IRQ_OTG_HS_WKUP     76
-#define STM32_IRQ_OTG_HS_EP1_IN   75
-#define STM32_IRQ_OTG_HS_EP1_OUT  74
-#define STM32_IRQ_OTG_HS          77
-#define STM32_IRQ_OTG_FS          67
-#define STM32_IRQ_OTG_FS_WKUP     42
+#define STM32_IRQ_DMA1_STREAM0 11
+#define STM32_IRQ_DMA1_STREAM1 12
+#define STM32_IRQ_DMA1_STREAM2 13
+#define STM32_IRQ_DMA1_STREAM3 14
+#define STM32_IRQ_DMA1_STREAM4 15
+#define STM32_IRQ_DMA1_STREAM5 16
+#define STM32_IRQ_DMA1_STREAM6 17
+#define STM32_IRQ_DMA1_STREAM7 47
+#define STM32_IRQ_DMA2_STREAM0 56
+#define STM32_IRQ_DMA2_STREAM1 57
+#define STM32_IRQ_DMA2_STREAM2 58
+#define STM32_IRQ_DMA2_STREAM3 59
+#define STM32_IRQ_DMA2_STREAM4 60
+#define STM32_IRQ_DMA2_STREAM5 68
+#define STM32_IRQ_DMA2_STREAM6 69
+#define STM32_IRQ_DMA2_STREAM7 70
+
+#define STM32_IRQ_OTG_HS_WKUP 76
+#define STM32_IRQ_OTG_HS_EP1_IN 75
+#define STM32_IRQ_OTG_HS_EP1_OUT 74
+#define STM32_IRQ_OTG_HS 77
+#define STM32_IRQ_OTG_FS 67
+#define STM32_IRQ_OTG_FS_WKUP 42
 
 /* Peripheral base addresses */
-#define STM32_ADC1_BASE             0x40012000
-#define STM32_ADC_BASE              0x40012300
-
-#define STM32_CEC_BASE              0x40007800 /* STM32F373 */
-#define STM32_CRC_BASE              0x40023000
-#define STM32_CRS_BASE              0x40006c00 /* STM32F0XX */
-#define STM32_DAC_BASE              0x40007400
-
-
-#define STM32_DBGMCU_BASE           0xE0042000
-
-#define STM32_DMA1_BASE             0x40026000
-#define STM32_DMA2_BASE             0x40026400
-
-#define STM32_EXTI_BASE             0x40013C00
-
-#define STM32_FLASH_REGS_BASE       0x40023c00
-
-#define STM32_GPIOA_BASE            0x40020000
-#define STM32_GPIOB_BASE            0x40020400
-#define STM32_GPIOC_BASE            0x40020800
-#define STM32_GPIOD_BASE            0x40020C00
-#define STM32_GPIOE_BASE            0x40021000
-#define STM32_GPIOF_BASE            0x40021400 /* see RM0402/0390 table 1 */
-#define STM32_GPIOG_BASE            0x40021800
-#define STM32_GPIOH_BASE            0x40021C00
-
-#define STM32_I2C1_BASE             0x40005400
-#define STM32_I2C2_BASE             0x40005800
-#define STM32_I2C3_BASE             0x40005C00
-#define STM32_I2C4_BASE             0x40006000
-
-#define STM32_IWDG_BASE             0x40003000
-#define STM32_LCD_BASE              0x40002400
-
-#define STM32_OPTB_BASE             0x1FFFC000
-#define STM32_OTP_BASE              0x1FFF7800
-
-#define STM32_PMSE_BASE             0x40013400
-#define STM32_PWR_BASE              0x40007000
-
-#define STM32_RCC_BASE              0x40023800
-
-#define STM32_RI_BASE               0x40007C00 /* STM32L1xx only */
-#define STM32_RNG_BASE              0x50060800 /* STM32L4 */
-#define STM32_RTC_BASE              0x40002800
-
-#define STM32_SPI1_BASE             0x40013000
-#define STM32_SPI2_BASE             0x40003800
-#define STM32_SPI3_BASE             0x40003c00 /* STM32F373, STM32L4, STM32F7 */
-
-#define STM32_SYSCFG_BASE           0x40013800
-
-#define STM32_TIM1_BASE             0x40012c00 /* STM32F373 */
-#define STM32_TIM2_BASE             0x40000000
-#define STM32_TIM3_BASE             0x40000400
-#define STM32_TIM4_BASE             0x40000800
-#define STM32_TIM5_BASE             0x40000c00 /* STM32F373 */
-#define STM32_TIM6_BASE             0x40001000
-#define STM32_TIM7_BASE             0x40001400
-#define STM32_TIM9_BASE             0x40014000 /* STM32F41x only */
-#define STM32_TIM10_BASE            0x40014400 /* STM32F41x only */
-#define STM32_TIM11_BASE            0x40014800 /* STM32F41x only */
-#define STM32_TIM12_BASE            0x40001800 /* STM32F373 */
-#define STM32_TIM13_BASE            0x40001c00 /* STM32F373 */
-#define STM32_TIM14_BASE            0x40002000 /* STM32F373 */
-#define STM32_TIM15_BASE            0x40014000
-#define STM32_TIM16_BASE            0x40014400
-#define STM32_TIM17_BASE            0x40014800
-#define STM32_TIM18_BASE            0x40009c00 /* STM32F373 only */
-#define STM32_TIM19_BASE            0x40015c00 /* STM32F373 only */
-
-#define STM32_UNIQUE_ID_BASE        0x1fff7a10
-
-#define STM32_USART1_BASE           0x40011000
-#define STM32_USART2_BASE           0x40004400
-#define STM32_USART3_BASE           0x40004800
-#define STM32_USART4_BASE           0x40004c00
-#define STM32_USART5_BASE           0x40005000
-#define STM32_USART6_BASE           0x40011400
-
-#define STM32_USB_CAN_SRAM_BASE     0x40006000
-#define STM32_USB_FS_BASE           0x40005C00
-
-#define STM32_WWDG_BASE             0x40002C00
-
+#define STM32_ADC1_BASE 0x40012000
+#define STM32_ADC_BASE 0x40012300
+
+#define STM32_CEC_BASE 0x40007800 /* STM32F373 */
+#define STM32_CRC_BASE 0x40023000
+#define STM32_CRS_BASE 0x40006c00 /* STM32F0XX */
+#define STM32_DAC_BASE 0x40007400
+
+#define STM32_DBGMCU_BASE 0xE0042000
+
+#define STM32_DMA1_BASE 0x40026000
+#define STM32_DMA2_BASE 0x40026400
+
+#define STM32_EXTI_BASE 0x40013C00
+
+#define STM32_FLASH_REGS_BASE 0x40023c00
+
+#define STM32_GPIOA_BASE 0x40020000
+#define STM32_GPIOB_BASE 0x40020400
+#define STM32_GPIOC_BASE 0x40020800
+#define STM32_GPIOD_BASE 0x40020C00
+#define STM32_GPIOE_BASE 0x40021000
+#define STM32_GPIOF_BASE 0x40021400 /* see RM0402/0390 table 1 */
+#define STM32_GPIOG_BASE 0x40021800
+#define STM32_GPIOH_BASE 0x40021C00
+
+#define STM32_I2C1_BASE 0x40005400
+#define STM32_I2C2_BASE 0x40005800
+#define STM32_I2C3_BASE 0x40005C00
+#define STM32_I2C4_BASE 0x40006000
+
+#define STM32_IWDG_BASE 0x40003000
+#define STM32_LCD_BASE 0x40002400
+
+#define STM32_OPTB_BASE 0x1FFFC000
+#define STM32_OTP_BASE 0x1FFF7800
+
+#define STM32_PMSE_BASE 0x40013400
+#define STM32_PWR_BASE 0x40007000
+
+#define STM32_RCC_BASE 0x40023800
+
+#define STM32_RI_BASE 0x40007C00 /* STM32L1xx only */
+#define STM32_RNG_BASE 0x50060800 /* STM32L4 */
+#define STM32_RTC_BASE 0x40002800
+
+#define STM32_SPI1_BASE 0x40013000
+#define STM32_SPI2_BASE 0x40003800
+#define STM32_SPI3_BASE 0x40003c00 /* STM32F373, STM32L4, STM32F7 */
+
+#define STM32_SYSCFG_BASE 0x40013800
+
+#define STM32_TIM1_BASE 0x40012c00 /* STM32F373 */
+#define STM32_TIM2_BASE 0x40000000
+#define STM32_TIM3_BASE 0x40000400
+#define STM32_TIM4_BASE 0x40000800
+#define STM32_TIM5_BASE 0x40000c00 /* STM32F373 */
+#define STM32_TIM6_BASE 0x40001000
+#define STM32_TIM7_BASE 0x40001400
+#define STM32_TIM9_BASE 0x40014000 /* STM32F41x only */
+#define STM32_TIM10_BASE 0x40014400 /* STM32F41x only */
+#define STM32_TIM11_BASE 0x40014800 /* STM32F41x only */
+#define STM32_TIM12_BASE 0x40001800 /* STM32F373 */
+#define STM32_TIM13_BASE 0x40001c00 /* STM32F373 */
+#define STM32_TIM14_BASE 0x40002000 /* STM32F373 */
+#define STM32_TIM15_BASE 0x40014000
+#define STM32_TIM16_BASE 0x40014400
+#define STM32_TIM17_BASE 0x40014800
+#define STM32_TIM18_BASE 0x40009c00 /* STM32F373 only */
+#define STM32_TIM19_BASE 0x40015c00 /* STM32F373 only */
+
+#define STM32_UNIQUE_ID_BASE 0x1fff7a10
+
+#define STM32_USART1_BASE 0x40011000
+#define STM32_USART2_BASE 0x40004400
+#define STM32_USART3_BASE 0x40004800
+#define STM32_USART4_BASE 0x40004c00
+#define STM32_USART5_BASE 0x40005000
+#define STM32_USART6_BASE 0x40011400
+
+#define STM32_USB_CAN_SRAM_BASE 0x40006000
+#define STM32_USB_FS_BASE 0x40005C00
+
+#define STM32_WWDG_BASE 0x40002C00
 
 #ifndef __ASSEMBLER__
 
 /* Register definitions */
 
 /* --- USART --- */
-#define STM32_USART_CR1(base)      STM32_USART_REG(base, 0x00)
-#define STM32_USART_CR1_UE		BIT(0)
-#define STM32_USART_CR1_UESM            BIT(1)
-#define STM32_USART_CR1_RE		BIT(2)
-#define STM32_USART_CR1_TE		BIT(3)
-#define STM32_USART_CR1_RXNEIE		BIT(5)
-#define STM32_USART_CR1_TCIE		BIT(6)
-#define STM32_USART_CR1_TXEIE		BIT(7)
-#define STM32_USART_CR1_PS		BIT(9)
-#define STM32_USART_CR1_PCE		BIT(10)
-#define STM32_USART_CR1_M		BIT(12)
-#define STM32_USART_CR1_OVER8		BIT(15)
-#define STM32_USART_CR2(base)      STM32_USART_REG(base, 0x04)
-#define STM32_USART_CR2_SWAP		BIT(15)
-#define STM32_USART_CR3(base)      STM32_USART_REG(base, 0x08)
-#define STM32_USART_CR3_EIE		BIT(0)
-#define STM32_USART_CR3_DMAR		BIT(6)
-#define STM32_USART_CR3_DMAT		BIT(7)
-#define STM32_USART_CR3_ONEBIT		BIT(11)
-#define STM32_USART_CR3_OVRDIS		BIT(12)
-#define STM32_USART_CR3_WUS_START_BIT	(2 << 20)
-#define STM32_USART_CR3_WUFIE		BIT(22)
-#define STM32_USART_BRR(base)      STM32_USART_REG(base, 0x0C)
-#define STM32_USART_GTPR(base)     STM32_USART_REG(base, 0x10)
-#define STM32_USART_RTOR(base)     STM32_USART_REG(base, 0x14)
-#define STM32_USART_RQR(base)      STM32_USART_REG(base, 0x18)
-#define STM32_USART_ISR(base)      STM32_USART_REG(base, 0x1C)
-#define STM32_USART_ICR(base)      STM32_USART_REG(base, 0x20)
-#define STM32_USART_ICR_ORECF		BIT(3)
-#define STM32_USART_ICR_TCCF		BIT(6)
-#define STM32_USART_RDR(base)      STM32_USART_REG(base, 0x24)
-#define STM32_USART_TDR(base)      STM32_USART_REG(base, 0x28)
-#define STM32_USART_PRESC(base)    STM32_USART_REG(base, 0x2C)
+#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00)
+#define STM32_USART_CR1_UE BIT(0)
+#define STM32_USART_CR1_UESM BIT(1)
+#define STM32_USART_CR1_RE BIT(2)
+#define STM32_USART_CR1_TE BIT(3)
+#define STM32_USART_CR1_RXNEIE BIT(5)
+#define STM32_USART_CR1_TCIE BIT(6)
+#define STM32_USART_CR1_TXEIE BIT(7)
+#define STM32_USART_CR1_PS BIT(9)
+#define STM32_USART_CR1_PCE BIT(10)
+#define STM32_USART_CR1_M BIT(12)
+#define STM32_USART_CR1_OVER8 BIT(15)
+#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04)
+#define STM32_USART_CR2_SWAP BIT(15)
+#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08)
+#define STM32_USART_CR3_EIE BIT(0)
+#define STM32_USART_CR3_DMAR BIT(6)
+#define STM32_USART_CR3_DMAT BIT(7)
+#define STM32_USART_CR3_ONEBIT BIT(11)
+#define STM32_USART_CR3_OVRDIS BIT(12)
+#define STM32_USART_CR3_WUS_START_BIT (2 << 20)
+#define STM32_USART_CR3_WUFIE BIT(22)
+#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C)
+#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10)
+#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14)
+#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18)
+#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C)
+#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20)
+#define STM32_USART_ICR_ORECF BIT(3)
+#define STM32_USART_ICR_TCCF BIT(6)
+#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24)
+#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28)
+#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C)
 /* register alias */
-#define STM32_USART_SR(base)       STM32_USART_ISR(base)
-#define STM32_USART_SR_ORE		BIT(3)
-#define STM32_USART_SR_RXNE		BIT(5)
-#define STM32_USART_SR_TC		BIT(6)
-#define STM32_USART_SR_TXE		BIT(7)
+#define STM32_USART_SR(base) STM32_USART_ISR(base)
+#define STM32_USART_SR_ORE BIT(3)
+#define STM32_USART_SR_RXNE BIT(5)
+#define STM32_USART_SR_TC BIT(6)
+#define STM32_USART_SR_TXE BIT(7)
 
 /* --- GPIO --- */
-#define STM32_GPIO_MODER(b)     REG32((b) + 0x00)
-#define STM32_GPIO_OTYPER(b)    REG16((b) + 0x04)
-#define STM32_GPIO_OSPEEDR(b)   REG32((b) + 0x08)
-#define STM32_GPIO_PUPDR(b)     REG32((b) + 0x0C)
-#define STM32_GPIO_IDR(b)       REG16((b) + 0x10)
-#define STM32_GPIO_ODR(b)       REG16((b) + 0x14)
-#define STM32_GPIO_BSRR(b)      REG32((b) + 0x18)
-#define STM32_GPIO_LCKR(b)      REG32((b) + 0x1C)
-#define STM32_GPIO_AFRL(b)      REG32((b) + 0x20)
-#define STM32_GPIO_AFRH(b)      REG32((b) + 0x24)
-
-#define GPIO_ALT_SYS                 0x0
-#define GPIO_ALT_TIM2                0x1
-#define GPIO_ALT_TIM3_4              0x2
-#define GPIO_ALT_TIM9_11             0x3
-#define GPIO_ALT_I2C                 0x4
-#define GPIO_ALT_SPI                 0x5
-#define GPIO_ALT_SPI3                0x6
-#define GPIO_ALT_USART               0x7
-#define GPIO_ALT_I2C_23              0x9
-#define GPIO_ALT_USB                 0xA
-#define GPIO_ALT_LCD                 0xB
-#define GPIO_ALT_RI                  0xE
-#define GPIO_ALT_EVENTOUT            0xF
+#define STM32_GPIO_MODER(b) REG32((b) + 0x00)
+#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04)
+#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08)
+#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C)
+#define STM32_GPIO_IDR(b) REG16((b) + 0x10)
+#define STM32_GPIO_ODR(b) REG16((b) + 0x14)
+#define STM32_GPIO_BSRR(b) REG32((b) + 0x18)
+#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C)
+#define STM32_GPIO_AFRL(b) REG32((b) + 0x20)
+#define STM32_GPIO_AFRH(b) REG32((b) + 0x24)
+
+#define GPIO_ALT_SYS 0x0
+#define GPIO_ALT_TIM2 0x1
+#define GPIO_ALT_TIM3_4 0x2
+#define GPIO_ALT_TIM9_11 0x3
+#define GPIO_ALT_I2C 0x4
+#define GPIO_ALT_SPI 0x5
+#define GPIO_ALT_SPI3 0x6
+#define GPIO_ALT_USART 0x7
+#define GPIO_ALT_I2C_23 0x9
+#define GPIO_ALT_USB 0xA
+#define GPIO_ALT_LCD 0xB
+#define GPIO_ALT_RI 0xE
+#define GPIO_ALT_EVENTOUT 0xF
 
 /* --- I2C --- */
-#define STM32_I2C_CR1(n)            REG16(stm32_i2c_reg(n, 0x00))
-#define STM32_I2C_CR1_PE	BIT(0)
-#define STM32_I2C_CR1_START	BIT(8)
-#define STM32_I2C_CR1_STOP	BIT(9)
-#define STM32_I2C_CR1_ACK	BIT(10)
-#define STM32_I2C_CR1_POS	BIT(11)
-#define STM32_I2C_CR1_SWRST	BIT(15)
-#define STM32_I2C_CR2(n)            REG16(stm32_i2c_reg(n, 0x04))
-#define STM32_I2C_CR2_ITERREN	BIT(8)
-#define STM32_I2C_CR2_ITEVTEN	BIT(9)
-#define STM32_I2C_CR2_ITBUFEN	BIT(10)
-#define STM32_I2C_CR2_DMAEN	BIT(11)
-#define STM32_I2C_CR2_LAST	BIT(12)
-#define STM32_I2C_OAR1(n)           REG16(stm32_i2c_reg(n, 0x08))
-#define STM32_I2C_OAR1_B14	BIT(14)
-#define STM32_I2C_OAR2(n)           REG16(stm32_i2c_reg(n, 0x0C))
-#define STM32_I2C_OAR2_ENDUAL	BIT(0)
-#define STM32_I2C_DR(n)             REG16(stm32_i2c_reg(n, 0x10))
-#define STM32_I2C_SR1(n)            REG16(stm32_i2c_reg(n, 0x14))
-#define STM32_I2C_SR1_SB	BIT(0)
-#define STM32_I2C_SR1_ADDR	BIT(1)
-#define STM32_I2C_SR1_BTF	BIT(2)
-#define STM32_I2C_SR1_STOPF	BIT(4)
-#define STM32_I2C_SR1_RXNE	BIT(6)
-#define STM32_I2C_SR1_TXE	BIT(7)
-#define STM32_I2C_SR1_BERR	BIT(8)
-#define STM32_I2C_SR1_ARLO	BIT(9)
-#define STM32_I2C_SR1_AF	BIT(10)
-
-#define STM32_I2C_SR2(n)            REG16(stm32_i2c_reg(n, 0x18))
-#define STM32_I2C_SR2_BUSY	BIT(1)
-#define STM32_I2C_SR2_TRA	BIT(2)
-#define STM32_I2C_SR2_DUALF	BIT(7)
-
-#define STM32_I2C_CCR(n)            REG16(stm32_i2c_reg(n, 0x1C))
-#define STM32_I2C_CCR_DUTY	BIT(14)
-#define STM32_I2C_CCR_FM	BIT(15)
-#define STM32_I2C_TRISE(n)          REG16(stm32_i2c_reg(n, 0x20))
-
-#define STM32_FMPI2C_CR1(n)        REG32(stm32_i2c_reg(n, 0x00))
-#define  FMPI2C_CR1_PE             BIT(0)
-#define  FMPI2C_CR1_TXDMAEN        BIT(14)
-#define  FMPI2C_CR1_RXDMAEN        BIT(15)
-#define STM32_FMPI2C_CR2(n)        REG32(stm32_i2c_reg(n, 0x04))
-#define  FMPI2C_CR2_RD_WRN         BIT(10)
-#define  FMPI2C_READ               1
-#define  FMPI2C_WRITE              0
-#define  FMPI2C_CR2_START          BIT(13)
-#define  FMPI2C_CR2_STOP           BIT(14)
-#define  FMPI2C_CR2_NACK           BIT(15)
-#define  FMPI2C_CR2_RELOAD         BIT(24)
-#define  FMPI2C_CR2_AUTOEND        BIT(25)
-#define  FMPI2C_CR2_SADD(addr)     ((addr) & 0x3ff)
-#define  FMPI2C_CR2_SADD_MASK      FMPI2C_CR2_SADD(0x3ff)
-#define  FMPI2C_CR2_SIZE(size)     (((size) & 0xff) << 16)
-#define  FMPI2C_CR2_SIZE_MASK      FMPI2C_CR2_SIZE(0xf)
-#define STM32_FMPI2C_OAR1(n)       REG32(stm32_i2c_reg(n, 0x08))
-#define STM32_FMPI2C_OAR2(n)       REG32(stm32_i2c_reg(n, 0x0C))
-#define STM32_FMPI2C_TIMINGR(n)    REG32(stm32_i2c_reg(n, 0x10))
-#define  TIMINGR_THE_RIGHT_VALUE   0xC0000E12
-#define  FMPI2C_TIMINGR_PRESC(val) (((val) & 0xf) << 28)
-#define  FMPI2C_TIMINGR_SCLDEL(val) (((val) & 0xf) << 20)
-#define  FMPI2C_TIMINGR_SDADEL(val) (((val) & 0xf) << 16)
-#define  FMPI2C_TIMINGR_SCLH(val)  (((val) & 0xff) << 8)
-#define  FMPI2C_TIMINGR_SCLL(val)  (((val) & 0xff) << 0)
-#define STM32_FMPI2C_TIMEOUTR(n)   REG32(stm32_i2c_reg(n, 0x14))
-
-#define STM32_FMPI2C_ISR(n)        REG32(stm32_i2c_reg(n, 0x18))
-#define  FMPI2C_ISR_TXE            BIT(0)
-#define  FMPI2C_ISR_TXIS           BIT(1)
-#define  FMPI2C_ISR_RXNE           BIT(2)
-#define  FMPI2C_ISR_ADDR           BIT(3)
-#define  FMPI2C_ISR_NACKF          BIT(4)
-#define  FMPI2C_ISR_STOPF          BIT(5)
-#define  FMPI2C_ISR_BERR           BIT(8)
-#define  FMPI2C_ISR_ARLO           BIT(9)
-#define  FMPI2C_ISR_BUSY           BIT(15)
-#define STM32_FMPI2C_ICR(n)        REG32(stm32_i2c_reg(n, 0x1C))
-
-#define STM32_FMPI2C_PECR(n)       REG32(stm32_i2c_reg(n, 0x20))
-#define STM32_FMPI2C_RXDR(n)       REG32(stm32_i2c_reg(n, 0x24))
-#define STM32_FMPI2C_TXDR(n)       REG32(stm32_i2c_reg(n, 0x28))
+#define STM32_I2C_CR1(n) REG16(stm32_i2c_reg(n, 0x00))
+#define STM32_I2C_CR1_PE BIT(0)
+#define STM32_I2C_CR1_START BIT(8)
+#define STM32_I2C_CR1_STOP BIT(9)
+#define STM32_I2C_CR1_ACK BIT(10)
+#define STM32_I2C_CR1_POS BIT(11)
+#define STM32_I2C_CR1_SWRST BIT(15)
+#define STM32_I2C_CR2(n) REG16(stm32_i2c_reg(n, 0x04))
+#define STM32_I2C_CR2_ITERREN BIT(8)
+#define STM32_I2C_CR2_ITEVTEN BIT(9)
+#define STM32_I2C_CR2_ITBUFEN BIT(10)
+#define STM32_I2C_CR2_DMAEN BIT(11)
+#define STM32_I2C_CR2_LAST BIT(12)
+#define STM32_I2C_OAR1(n) REG16(stm32_i2c_reg(n, 0x08))
+#define STM32_I2C_OAR1_B14 BIT(14)
+#define STM32_I2C_OAR2(n) REG16(stm32_i2c_reg(n, 0x0C))
+#define STM32_I2C_OAR2_ENDUAL BIT(0)
+#define STM32_I2C_DR(n) REG16(stm32_i2c_reg(n, 0x10))
+#define STM32_I2C_SR1(n) REG16(stm32_i2c_reg(n, 0x14))
+#define STM32_I2C_SR1_SB BIT(0)
+#define STM32_I2C_SR1_ADDR BIT(1)
+#define STM32_I2C_SR1_BTF BIT(2)
+#define STM32_I2C_SR1_STOPF BIT(4)
+#define STM32_I2C_SR1_RXNE BIT(6)
+#define STM32_I2C_SR1_TXE BIT(7)
+#define STM32_I2C_SR1_BERR BIT(8)
+#define STM32_I2C_SR1_ARLO BIT(9)
+#define STM32_I2C_SR1_AF BIT(10)
+
+#define STM32_I2C_SR2(n) REG16(stm32_i2c_reg(n, 0x18))
+#define STM32_I2C_SR2_BUSY BIT(1)
+#define STM32_I2C_SR2_TRA BIT(2)
+#define STM32_I2C_SR2_DUALF BIT(7)
+
+#define STM32_I2C_CCR(n) REG16(stm32_i2c_reg(n, 0x1C))
+#define STM32_I2C_CCR_DUTY BIT(14)
+#define STM32_I2C_CCR_FM BIT(15)
+#define STM32_I2C_TRISE(n) REG16(stm32_i2c_reg(n, 0x20))
+
+#define STM32_FMPI2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00))
+#define FMPI2C_CR1_PE BIT(0)
+#define FMPI2C_CR1_TXDMAEN BIT(14)
+#define FMPI2C_CR1_RXDMAEN BIT(15)
+#define STM32_FMPI2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04))
+#define FMPI2C_CR2_RD_WRN BIT(10)
+#define FMPI2C_READ 1
+#define FMPI2C_WRITE 0
+#define FMPI2C_CR2_START BIT(13)
+#define FMPI2C_CR2_STOP BIT(14)
+#define FMPI2C_CR2_NACK BIT(15)
+#define FMPI2C_CR2_RELOAD BIT(24)
+#define FMPI2C_CR2_AUTOEND BIT(25)
+#define FMPI2C_CR2_SADD(addr) ((addr)&0x3ff)
+#define FMPI2C_CR2_SADD_MASK FMPI2C_CR2_SADD(0x3ff)
+#define FMPI2C_CR2_SIZE(size) (((size)&0xff) << 16)
+#define FMPI2C_CR2_SIZE_MASK FMPI2C_CR2_SIZE(0xf)
+#define STM32_FMPI2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08))
+#define STM32_FMPI2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C))
+#define STM32_FMPI2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10))
+#define TIMINGR_THE_RIGHT_VALUE 0xC0000E12
+#define FMPI2C_TIMINGR_PRESC(val) (((val)&0xf) << 28)
+#define FMPI2C_TIMINGR_SCLDEL(val) (((val)&0xf) << 20)
+#define FMPI2C_TIMINGR_SDADEL(val) (((val)&0xf) << 16)
+#define FMPI2C_TIMINGR_SCLH(val) (((val)&0xff) << 8)
+#define FMPI2C_TIMINGR_SCLL(val) (((val)&0xff) << 0)
+#define STM32_FMPI2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14))
+
+#define STM32_FMPI2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18))
+#define FMPI2C_ISR_TXE BIT(0)
+#define FMPI2C_ISR_TXIS BIT(1)
+#define FMPI2C_ISR_RXNE BIT(2)
+#define FMPI2C_ISR_ADDR BIT(3)
+#define FMPI2C_ISR_NACKF BIT(4)
+#define FMPI2C_ISR_STOPF BIT(5)
+#define FMPI2C_ISR_BERR BIT(8)
+#define FMPI2C_ISR_ARLO BIT(9)
+#define FMPI2C_ISR_BUSY BIT(15)
+#define STM32_FMPI2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C))
+
+#define STM32_FMPI2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20))
+#define STM32_FMPI2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24))
+#define STM32_FMPI2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28))
 
 /* --- Power / Reset / Clocks --- */
-#define STM32_PWR_CSR               REG32(STM32_PWR_BASE + 0x04)
-
+#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04)
 
-#define STM32_RCC_CR                    REG32(STM32_RCC_BASE + 0x00)
-#define STM32_RCC_CR_HSION		BIT(0)
-#define STM32_RCC_CR_HSIRDY		BIT(1)
-#define STM32_RCC_CR_HSEON		BIT(16)
-#define STM32_RCC_CR_HSERDY		BIT(17)
-#define STM32_RCC_CR_PLLON		BIT(24)
-#define STM32_RCC_CR_PLLRDY		BIT(25)
+#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00)
+#define STM32_RCC_CR_HSION BIT(0)
+#define STM32_RCC_CR_HSIRDY BIT(1)
+#define STM32_RCC_CR_HSEON BIT(16)
+#define STM32_RCC_CR_HSERDY BIT(17)
+#define STM32_RCC_CR_PLLON BIT(24)
+#define STM32_RCC_CR_PLLRDY BIT(25)
 
 #ifdef CHIP_VARIANT_STM32F76X
 /* Required or recommended clocks for stm32f767/769 */
 #define STM32F4_PLL_REQ 2000000
 #define STM32F4_RTC_REQ 1000000
 #define STM32F4_IO_CLOCK 45000000
-#define STM32F4_USB_REQ 45000000 /* not compatible with USB, will use PLLSAI */
+#define STM32F4_USB_REQ                                      \
+	45000000 /* not compatible with USB, will use PLLSAI \
+		  */
 #define STM32F4_VCO_CLOCK 360000000
 #define STM32F4_HSI_CLOCK 16000000
 #define STM32F4_LSI_CLOCK 32000
 #define STM32F4_TIMER_CLOCK (STM32F4_IO_CLOCK * 2)
-#define STM32F4_PLLP_DIV 2   /* sys = VCO/2  = 180 Mhz */
-#define STM32F4_AHB_PRE 0x0  /* AHB = sysclk = 180 Mhz */
+#define STM32F4_PLLP_DIV 2 /* sys = VCO/2  = 180 Mhz */
+#define STM32F4_AHB_PRE 0x0 /* AHB = sysclk = 180 Mhz */
 #define STM32F4_APB1_PRE 0x5 /* APB1 = AHB /4 = 45 Mhz */
 #define STM32F4_APB2_PRE 0x5 /* APB2 = AHB /4 = 45 Mhz */
-#define STM32_FLASH_ACR_LATENCY     (5 << 0)
+#define STM32_FLASH_ACR_LATENCY (5 << 0)
 #else
 #error "No valid clocks defined"
 #endif
 
-#define STM32_RCC_PLLCFGR               REG32(STM32_RCC_BASE + 0x04)
+#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x04)
 /* PLL Division factor */
-#define  PLLCFGR_PLLM_OFF		0
-#define  PLLCFGR_PLLM(val)		(((val) & 0x1f) << PLLCFGR_PLLM_OFF)
+#define PLLCFGR_PLLM_OFF 0
+#define PLLCFGR_PLLM(val) (((val)&0x1f) << PLLCFGR_PLLM_OFF)
 /* PLL Multiplication factor */
-#define  PLLCFGR_PLLN_OFF		6
-#define  PLLCFGR_PLLN(val)		(((val) & 0x1ff) << PLLCFGR_PLLN_OFF)
+#define PLLCFGR_PLLN_OFF 6
+#define PLLCFGR_PLLN(val) (((val)&0x1ff) << PLLCFGR_PLLN_OFF)
 /* Main CPU Clock */
-#define  PLLCFGR_PLLP_OFF		16
-#define  PLLCFGR_PLLP(val)		(((val) & 0x3) << PLLCFGR_PLLP_OFF)
+#define PLLCFGR_PLLP_OFF 16
+#define PLLCFGR_PLLP(val) (((val)&0x3) << PLLCFGR_PLLP_OFF)
 
-#define  PLLCFGR_PLLSRC_HSI		(0 << 22)
-#define  PLLCFGR_PLLSRC_HSE		BIT(22)
+#define PLLCFGR_PLLSRC_HSI (0 << 22)
+#define PLLCFGR_PLLSRC_HSE BIT(22)
 /* USB OTG FS: Must equal 48MHz */
-#define  PLLCFGR_PLLQ_OFF		24
-#define  PLLCFGR_PLLQ(val)		(((val) & 0xf) << PLLCFGR_PLLQ_OFF)
+#define PLLCFGR_PLLQ_OFF 24
+#define PLLCFGR_PLLQ(val) (((val)&0xf) << PLLCFGR_PLLQ_OFF)
 /* SYSTEM */
-#define  PLLCFGR_PLLR_OFF		28
-#define  PLLCFGR_PLLR(val)		(((val) & 0x7) << PLLCFGR_PLLR_OFF)
-
-#define STM32_RCC_CFGR                  REG32(STM32_RCC_BASE + 0x08)
-#define STM32_RCC_CFGR_SW_HSI		(0 << 0)
-#define STM32_RCC_CFGR_SW_HSE		(1 << 0)
-#define STM32_RCC_CFGR_SW_PLL		(2 << 0)
-#define STM32_RCC_CFGR_SW_PLL_R		(3 << 0)
-#define STM32_RCC_CFGR_SW_MASK		(3 << 0)
-#define STM32_RCC_CFGR_SWS_HSI		(0 << 2)
-#define STM32_RCC_CFGR_SWS_HSE		(1 << 2)
-#define STM32_RCC_CFGR_SWS_PLL		(2 << 2)
-#define STM32_RCC_CFGR_SWS_PLL_R	(3 << 2)
-#define STM32_RCC_CFGR_SWS_MASK		(3 << 2)
+#define PLLCFGR_PLLR_OFF 28
+#define PLLCFGR_PLLR(val) (((val)&0x7) << PLLCFGR_PLLR_OFF)
+
+#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08)
+#define STM32_RCC_CFGR_SW_HSI (0 << 0)
+#define STM32_RCC_CFGR_SW_HSE (1 << 0)
+#define STM32_RCC_CFGR_SW_PLL (2 << 0)
+#define STM32_RCC_CFGR_SW_PLL_R (3 << 0)
+#define STM32_RCC_CFGR_SW_MASK (3 << 0)
+#define STM32_RCC_CFGR_SWS_HSI (0 << 2)
+#define STM32_RCC_CFGR_SWS_HSE (1 << 2)
+#define STM32_RCC_CFGR_SWS_PLL (2 << 2)
+#define STM32_RCC_CFGR_SWS_PLL_R (3 << 2)
+#define STM32_RCC_CFGR_SWS_MASK (3 << 2)
 /* AHB Prescalar: nonlinear values, look up in RM0390 */
-#define  CFGR_HPRE_OFF			4
-#define  CFGR_HPRE(val)			(((val) & 0xf) << CFGR_HPRE_OFF)
+#define CFGR_HPRE_OFF 4
+#define CFGR_HPRE(val) (((val)&0xf) << CFGR_HPRE_OFF)
 /* APB1 Low Speed Prescalar < 45MHz */
-#define  CFGR_PPRE1_OFF			10
-#define  CFGR_PPRE1(val)		(((val) & 0x7) << CFGR_PPRE1_OFF)
+#define CFGR_PPRE1_OFF 10
+#define CFGR_PPRE1(val) (((val)&0x7) << CFGR_PPRE1_OFF)
 /* APB2 High Speed Prescalar < 90MHz */
-#define  CFGR_PPRE2_OFF			13
-#define  CFGR_PPRE2(val)		(((val) & 0x7) << CFGR_PPRE2_OFF)
+#define CFGR_PPRE2_OFF 13
+#define CFGR_PPRE2(val) (((val)&0x7) << CFGR_PPRE2_OFF)
 /* RTC CLock: Must equal 1MHz */
-#define  CFGR_RTCPRE_OFF		16
-#define  CFGR_RTCPRE(val)		(((val) & 0x1f) << CFGR_RTCPRE_OFF)
+#define CFGR_RTCPRE_OFF 16
+#define CFGR_RTCPRE(val) (((val)&0x1f) << CFGR_RTCPRE_OFF)
 
-#define STM32_RCC_CIR                   REG32(STM32_RCC_BASE + 0x0C)
-#define STM32_RCC_AHB1RSTR              REG32(STM32_RCC_BASE + 0x10)
-#define  RCC_AHB1RSTR_OTGHSRST		BIT(29)
+#define STM32_RCC_CIR REG32(STM32_RCC_BASE + 0x0C)
+#define STM32_RCC_AHB1RSTR REG32(STM32_RCC_BASE + 0x10)
+#define RCC_AHB1RSTR_OTGHSRST BIT(29)
 
-#define STM32_RCC_AHB2RSTR              REG32(STM32_RCC_BASE + 0x14)
-#define STM32_RCC_AHB3RSTR              REG32(STM32_RCC_BASE + 0x18)
+#define STM32_RCC_AHB2RSTR REG32(STM32_RCC_BASE + 0x14)
+#define STM32_RCC_AHB3RSTR REG32(STM32_RCC_BASE + 0x18)
 
-#define STM32_RCC_APB1RSTR              REG32(STM32_RCC_BASE + 0x20)
-#define STM32_RCC_APB2RSTR              REG32(STM32_RCC_BASE + 0x24)
+#define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x20)
+#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x24)
 
-#define STM32_RCC_AHB1ENR               REG32(STM32_RCC_BASE + 0x30)
-#define STM32_RCC_AHB1ENR_GPIOMASK	(0xff << 0)
-#define STM32_RCC_AHB1ENR_BKPSRAMEN	BIT(18)
-#define STM32_RCC_AHB1ENR_DMA1EN	BIT(21)
-#define STM32_RCC_AHB1ENR_DMA2EN	BIT(22)
+#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x30)
+#define STM32_RCC_AHB1ENR_GPIOMASK (0xff << 0)
+#define STM32_RCC_AHB1ENR_BKPSRAMEN BIT(18)
+#define STM32_RCC_AHB1ENR_DMA1EN BIT(21)
+#define STM32_RCC_AHB1ENR_DMA2EN BIT(22)
 /* TODO(nsanders): normalize naming.*/
-#define STM32_RCC_HB1_DMA1		BIT(21)
-#define STM32_RCC_HB1_DMA2		BIT(22)
-#define STM32_RCC_AHB1ENR_OTGHSEN	BIT(29)
-#define STM32_RCC_AHB1ENR_OTGHSULPIEN	BIT(30)
-
-#define STM32_RCC_AHB2ENR               REG32(STM32_RCC_BASE + 0x34)
-#define STM32_RCC_AHB2ENR_RNGEN		BIT(6)
-#define STM32_RCC_AHB2ENR_OTGFSEN	BIT(7)
-#define STM32_RCC_AHB3ENR               REG32(STM32_RCC_BASE + 0x38)
-
-#define STM32_RCC_APB1ENR               REG32(STM32_RCC_BASE + 0x40)
-#define STM32_RCC_PWREN                 BIT(28)
-#define STM32_RCC_I2C1EN                BIT(21)
-#define STM32_RCC_I2C2EN                BIT(22)
-#define STM32_RCC_I2C3EN                BIT(23)
-#define STM32_RCC_FMPI2C4EN             BIT(24)
-
-#define STM32_RCC_APB2ENR               REG32(STM32_RCC_BASE + 0x44)
-#define STM32_RCC_APB2ENR_ADC1EN        BIT(8) /* STM32F4 */
-
-#define STM32_RCC_PB2_USART6            BIT(5)
-#define STM32_RCC_SYSCFGEN		BIT(14)
-
-#define STM32_RCC_AHB1LPENR             REG32(STM32_RCC_BASE + 0x50)
-#define STM32_RCC_AHB2LPENR             REG32(STM32_RCC_BASE + 0x54)
-#define STM32_RCC_AHB3LPENR             REG32(STM32_RCC_BASE + 0x58)
-#define STM32_RCC_APB1LPENR             REG32(STM32_RCC_BASE + 0x60)
-#define STM32_RCC_APB2LPENR             REG32(STM32_RCC_BASE + 0x64)
-
-#define STM32_RCC_BDCR                  REG32(STM32_RCC_BASE + 0x70)
-#define STM32_RCC_CSR                   REG32(STM32_RCC_BASE + 0x74)
-#define STM32_RCC_CSR_LSION		BIT(0)
-#define STM32_RCC_CSR_LSIRDY		BIT(1)
-
-#define STM32_RCC_PB2_TIM9		BIT(16)
-#define STM32_RCC_PB2_TIM10		BIT(17)
-#define STM32_RCC_PB2_TIM11		BIT(18)
-
-#define STM32_RCC_DCKCFGR2              REG32(STM32_RCC_BASE + 0x94)
-#define  DCKCFGR2_FMPI2C1SEL(val)       (((val) & 0x3) << 22)
-#define  DCKCFGR2_FMPI2C1SEL_MASK       (0x3 << 22)
-#define  FMPI2C1SEL_APB                 0x0
-
-#define STM32_SYSCFG_MEMRMP             REG32(STM32_SYSCFG_BASE + 0x00)
-#define STM32_SYSCFG_PMC                REG32(STM32_SYSCFG_BASE + 0x04)
-#define STM32_SYSCFG_EXTICR(n)          REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
-#define STM32_SYSCFG_CMPCR              REG32(STM32_SYSCFG_BASE + 0x20)
-#define STM32_SYSCFG_CFGR               REG32(STM32_SYSCFG_BASE + 0x2C)
-
+#define STM32_RCC_HB1_DMA1 BIT(21)
+#define STM32_RCC_HB1_DMA2 BIT(22)
+#define STM32_RCC_AHB1ENR_OTGHSEN BIT(29)
+#define STM32_RCC_AHB1ENR_OTGHSULPIEN BIT(30)
+
+#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x34)
+#define STM32_RCC_AHB2ENR_RNGEN BIT(6)
+#define STM32_RCC_AHB2ENR_OTGFSEN BIT(7)
+#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x38)
+
+#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x40)
+#define STM32_RCC_PWREN BIT(28)
+#define STM32_RCC_I2C1EN BIT(21)
+#define STM32_RCC_I2C2EN BIT(22)
+#define STM32_RCC_I2C3EN BIT(23)
+#define STM32_RCC_FMPI2C4EN BIT(24)
+
+#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x44)
+#define STM32_RCC_APB2ENR_ADC1EN BIT(8) /* STM32F4 */
+
+#define STM32_RCC_PB2_USART6 BIT(5)
+#define STM32_RCC_SYSCFGEN BIT(14)
+
+#define STM32_RCC_AHB1LPENR REG32(STM32_RCC_BASE + 0x50)
+#define STM32_RCC_AHB2LPENR REG32(STM32_RCC_BASE + 0x54)
+#define STM32_RCC_AHB3LPENR REG32(STM32_RCC_BASE + 0x58)
+#define STM32_RCC_APB1LPENR REG32(STM32_RCC_BASE + 0x60)
+#define STM32_RCC_APB2LPENR REG32(STM32_RCC_BASE + 0x64)
+
+#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x70)
+#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x74)
+#define STM32_RCC_CSR_LSION BIT(0)
+#define STM32_RCC_CSR_LSIRDY BIT(1)
+
+#define STM32_RCC_PB2_TIM9 BIT(16)
+#define STM32_RCC_PB2_TIM10 BIT(17)
+#define STM32_RCC_PB2_TIM11 BIT(18)
+
+#define STM32_RCC_DCKCFGR2 REG32(STM32_RCC_BASE + 0x94)
+#define DCKCFGR2_FMPI2C1SEL(val) (((val)&0x3) << 22)
+#define DCKCFGR2_FMPI2C1SEL_MASK (0x3 << 22)
+#define FMPI2C1SEL_APB 0x0
+
+#define STM32_SYSCFG_MEMRMP REG32(STM32_SYSCFG_BASE + 0x00)
+#define STM32_SYSCFG_PMC REG32(STM32_SYSCFG_BASE + 0x04)
+#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
+#define STM32_SYSCFG_CMPCR REG32(STM32_SYSCFG_BASE + 0x20)
+#define STM32_SYSCFG_CFGR REG32(STM32_SYSCFG_BASE + 0x2C)
 
 /* Peripheral bits for RCC_APB/AHB and DBGMCU regs */
-#define STM32_RCC_PB2_USART1		BIT(4)
+#define STM32_RCC_PB2_USART1 BIT(4)
 
 /* Reset causes definitions */
 /* Reset causes in RCC CSR register */
 #define STM32_RCC_RESET_CAUSE STM32_RCC_CSR
-#define  RESET_CAUSE_WDG                0x60000000
-#define  RESET_CAUSE_SFT                0x10000000
-#define  RESET_CAUSE_POR                0x08000000
-#define  RESET_CAUSE_PIN                0x04000000
-#define  RESET_CAUSE_OTHER              0xfe000000
-#define  RESET_CAUSE_RMVF               0x01000000
+#define RESET_CAUSE_WDG 0x60000000
+#define RESET_CAUSE_SFT 0x10000000
+#define RESET_CAUSE_POR 0x08000000
+#define RESET_CAUSE_PIN 0x04000000
+#define RESET_CAUSE_OTHER 0xfe000000
+#define RESET_CAUSE_RMVF 0x01000000
 /* Power cause in PWR CSR register */
 #define STM32_PWR_RESET_CAUSE STM32_PWR_CSR
 #define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR
-#define  RESET_CAUSE_SBF                0x00000002
-#define  RESET_CAUSE_SBF_CLR            0x00000004
+#define RESET_CAUSE_SBF 0x00000002
+#define RESET_CAUSE_SBF_CLR 0x00000004
 
 /* --- Watchdogs --- */
 
 /* --- Real-Time Clock --- */
-#define STM32_RTC_TR                REG32(STM32_RTC_BASE + 0x00)
-#define STM32_RTC_DR                REG32(STM32_RTC_BASE + 0x04)
-#define STM32_RTC_CR                REG32(STM32_RTC_BASE + 0x08)
-#define STM32_RTC_CR_BYPSHAD        BIT(5)
-#define STM32_RTC_CR_ALRAE          BIT(8)
-#define STM32_RTC_CR_ALRAIE         BIT(12)
-#define STM32_RTC_ISR               REG32(STM32_RTC_BASE + 0x0C)
-#define STM32_RTC_ISR_ALRAWF        BIT(0)
-#define STM32_RTC_ISR_RSF           BIT(5)
-#define STM32_RTC_ISR_INITF         BIT(6)
-#define STM32_RTC_ISR_INIT          BIT(7)
-#define STM32_RTC_ISR_ALRAF         BIT(8)
-#define STM32_RTC_PRER              REG32(STM32_RTC_BASE + 0x10)
-#define STM32_RTC_PRER_A_MASK       (0x7f << 16)
-#define STM32_RTC_PRER_S_MASK       (0x7fff << 0)
-#define STM32_RTC_WUTR              REG32(STM32_RTC_BASE + 0x14)
-#define STM32_RTC_CALIBR            REG32(STM32_RTC_BASE + 0x18)
-#define STM32_RTC_ALRMAR            REG32(STM32_RTC_BASE + 0x1C)
-#define STM32_RTC_ALRMBR            REG32(STM32_RTC_BASE + 0x20)
-#define STM32_RTC_WPR               REG32(STM32_RTC_BASE + 0x24)
-#define STM32_RTC_SSR               REG32(STM32_RTC_BASE + 0x28)
-#define STM32_RTC_TSTR              REG32(STM32_RTC_BASE + 0x30)
-#define STM32_RTC_TSDR              REG32(STM32_RTC_BASE + 0x34)
-#define STM32_RTC_TAFCR             REG32(STM32_RTC_BASE + 0x40)
-#define STM32_RTC_ALRMASSR          REG32(STM32_RTC_BASE + 0x44)
-#define STM32_RTC_BACKUP(n)         REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
-
-#define STM32_BKP_DATA(n)           STM32_RTC_BACKUP(n)
-#define STM32_BKP_BYTES             80
+#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00)
+#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04)
+#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08)
+#define STM32_RTC_CR_BYPSHAD BIT(5)
+#define STM32_RTC_CR_ALRAE BIT(8)
+#define STM32_RTC_CR_ALRAIE BIT(12)
+#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C)
+#define STM32_RTC_ISR_ALRAWF BIT(0)
+#define STM32_RTC_ISR_RSF BIT(5)
+#define STM32_RTC_ISR_INITF BIT(6)
+#define STM32_RTC_ISR_INIT BIT(7)
+#define STM32_RTC_ISR_ALRAF BIT(8)
+#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10)
+#define STM32_RTC_PRER_A_MASK (0x7f << 16)
+#define STM32_RTC_PRER_S_MASK (0x7fff << 0)
+#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14)
+#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18)
+#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C)
+#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20)
+#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24)
+#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28)
+#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30)
+#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34)
+#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40)
+#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44)
+#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
+
+#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n)
+#define STM32_BKP_BYTES 80
 
 /* --- SPI --- */
 
@@ -590,15 +587,15 @@ struct stm32_spi_regs {
 	uint16_t _pad0;
 	uint16_t cr2;
 	uint16_t _pad1;
-	unsigned sr;
+	unsigned int sr;
 	uint8_t dr;
 	uint8_t _pad2;
 	uint16_t _pad3;
-	unsigned crcpr;
-	unsigned rxcrcr;
-	unsigned txcrcr;
-	unsigned i2scfgr;	/* STM32L only */
-	unsigned i2spr;		/* STM32L only */
+	unsigned int crcpr;
+	unsigned int rxcrcr;
+	unsigned int txcrcr;
+	unsigned int i2scfgr; /* STM32L only */
+	unsigned int i2spr; /* STM32L only */
 };
 /* Must be volatile, or compiler optimizes out repeated accesses */
 typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
@@ -608,146 +605,142 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
 #define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE)
 #define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE)
 
-#define STM32_SPI_CR1_BIDIMODE		BIT(15)
-#define STM32_SPI_CR1_BIDIOE		BIT(14)
-#define STM32_SPI_CR1_CRCEN		BIT(13)
-#define STM32_SPI_CR1_SSM		BIT(9)
-#define STM32_SPI_CR1_SSI		BIT(8)
-#define STM32_SPI_CR1_LSBFIRST		BIT(7)
-#define STM32_SPI_CR1_SPE		BIT(6)
-#define STM32_SPI_CR1_BR_DIV64R		(5 << 3)
-#define STM32_SPI_CR1_BR_DIV4R		BIT(3)
-#define STM32_SPI_CR1_MSTR		BIT(2)
-#define STM32_SPI_CR1_CPOL		BIT(1)
-#define STM32_SPI_CR1_CPHA		BIT(0)
-#define STM32_SPI_CR2_FRXTH		BIT(12)
-#define STM32_SPI_CR2_DATASIZE(n)	(((n) - 1) << 8)
-#define STM32_SPI_CR2_TXEIE		BIT(7)
-#define STM32_SPI_CR2_RXNEIE		BIT(6)
-#define STM32_SPI_CR2_NSSP		BIT(3)
-#define STM32_SPI_CR2_SSOE		BIT(2)
-#define STM32_SPI_CR2_TXDMAEN		BIT(1)
-#define STM32_SPI_CR2_RXDMAEN		BIT(0)
-
-#define STM32_SPI_SR_RXNE		BIT(0)
-#define STM32_SPI_SR_TXE		BIT(1)
-#define STM32_SPI_SR_CRCERR		BIT(4)
-#define STM32_SPI_SR_BSY		BIT(7)
-#define STM32_SPI_SR_FRLVL		(3 << 9)
-#define STM32_SPI_SR_FTLVL		(3 << 11)
+#define STM32_SPI_CR1_BIDIMODE BIT(15)
+#define STM32_SPI_CR1_BIDIOE BIT(14)
+#define STM32_SPI_CR1_CRCEN BIT(13)
+#define STM32_SPI_CR1_SSM BIT(9)
+#define STM32_SPI_CR1_SSI BIT(8)
+#define STM32_SPI_CR1_LSBFIRST BIT(7)
+#define STM32_SPI_CR1_SPE BIT(6)
+#define STM32_SPI_CR1_BR_DIV64R (5 << 3)
+#define STM32_SPI_CR1_BR_DIV4R BIT(3)
+#define STM32_SPI_CR1_MSTR BIT(2)
+#define STM32_SPI_CR1_CPOL BIT(1)
+#define STM32_SPI_CR1_CPHA BIT(0)
+#define STM32_SPI_CR2_FRXTH BIT(12)
+#define STM32_SPI_CR2_DATASIZE(n) (((n)-1) << 8)
+#define STM32_SPI_CR2_TXEIE BIT(7)
+#define STM32_SPI_CR2_RXNEIE BIT(6)
+#define STM32_SPI_CR2_NSSP BIT(3)
+#define STM32_SPI_CR2_SSOE BIT(2)
+#define STM32_SPI_CR2_TXDMAEN BIT(1)
+#define STM32_SPI_CR2_RXDMAEN BIT(0)
+
+#define STM32_SPI_SR_RXNE BIT(0)
+#define STM32_SPI_SR_TXE BIT(1)
+#define STM32_SPI_SR_CRCERR BIT(4)
+#define STM32_SPI_SR_BSY BIT(7)
+#define STM32_SPI_SR_FRLVL (3 << 9)
+#define STM32_SPI_SR_FTLVL (3 << 11)
 /* --- Debug --- */
-#define STM32_DBGMCU_APB1FZ         REG32(STM32_DBGMCU_BASE + 0x08)
-#define STM32_DBGMCU_APB2FZ         REG32(STM32_DBGMCU_BASE + 0x0C)
+#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08)
+#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C)
 
 /* --- Flash --- */
-#define STM32_FLASH_ACR             REG32(STM32_FLASH_REGS_BASE + 0x00)
-#define STM32_FLASH_ACR_SHIFT           0
-#define STM32_FLASH_ACR_LAT_MASK        0xf
-#define STM32_FLASH_ACR_PRFTEN          BIT(8)
-#define STM32_FLASH_ACR_ICEN            BIT(9)
-#define STM32_FLASH_ACR_DCEN            BIT(10)
-#define STM32_FLASH_ACR_ICRST           BIT(11)
-#define STM32_FLASH_ACR_DCRST           BIT(12)
-#define STM32_FLASH_KEYR            REG32(STM32_FLASH_REGS_BASE + 0x04)
-#define  FLASH_KEYR_KEY1                0x45670123
-#define  FLASH_KEYR_KEY2                0xCDEF89AB
-#define STM32_FLASH_OPTKEYR         REG32(STM32_FLASH_REGS_BASE + 0x08)
-#define  FLASH_OPTKEYR_KEY1             0x08192A3B
-#define  FLASH_OPTKEYR_KEY2             0x4C5D6E7F
-#define STM32_FLASH_SR              REG32(STM32_FLASH_REGS_BASE + 0x0c)
-#define  FLASH_SR_EOP                   BIT(0)
-#define  FLASH_SR_OPERR                 BIT(1)
-#define  FLASH_SR_WRPERR                BIT(4)
-#define  FLASH_SR_PGAERR                BIT(5)
-#define  FLASH_SR_PGPERR                BIT(6)
-#define  FLASH_SR_PGSERR                BIT(7)
-#define  FLASH_SR_RDERR                 BIT(8)
-#define  FLASH_SR_ALL_ERR \
+#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00)
+#define STM32_FLASH_ACR_SHIFT 0
+#define STM32_FLASH_ACR_LAT_MASK 0xf
+#define STM32_FLASH_ACR_PRFTEN BIT(8)
+#define STM32_FLASH_ACR_ICEN BIT(9)
+#define STM32_FLASH_ACR_DCEN BIT(10)
+#define STM32_FLASH_ACR_ICRST BIT(11)
+#define STM32_FLASH_ACR_DCRST BIT(12)
+#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x04)
+#define FLASH_KEYR_KEY1 0x45670123
+#define FLASH_KEYR_KEY2 0xCDEF89AB
+#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x08)
+#define FLASH_OPTKEYR_KEY1 0x08192A3B
+#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F
+#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x0c)
+#define FLASH_SR_EOP BIT(0)
+#define FLASH_SR_OPERR BIT(1)
+#define FLASH_SR_WRPERR BIT(4)
+#define FLASH_SR_PGAERR BIT(5)
+#define FLASH_SR_PGPERR BIT(6)
+#define FLASH_SR_PGSERR BIT(7)
+#define FLASH_SR_RDERR BIT(8)
+#define FLASH_SR_ALL_ERR                                      \
 	(FLASH_SR_OPERR | FLASH_SR_WRPERR | FLASH_SR_PGAERR | \
 	 FLASH_SR_PGPERR | FLASH_SR_PGSERR | FLASH_SR_RDERR)
-#define  FLASH_SR_BUSY                   BIT(16)
-#define STM32_FLASH_CR              REG32(STM32_FLASH_REGS_BASE + 0x10)
-#define  FLASH_CR_PG                    BIT(0)
-#define  FLASH_CR_PER                   BIT(1)
-#define  FLASH_CR_MER                   BIT(2)
-#define STM32_FLASH_CR_SNB_OFFSET       (3)
-#define STM32_FLASH_CR_SNB(sec) \
-	(((sec) & 0xf) << STM32_FLASH_CR_SNB_OFFSET)
-#define STM32_FLASH_CR_SNB_MASK         (STM32_FLASH_CR_SNB(0xf))
-#define STM32_FLASH_CR_PSIZE_OFFSET     (8)
-#define STM32_FLASH_CR_PSIZE(size) \
-	(((size) & 0x3) << STM32_FLASH_CR_PSIZE_OFFSET)
-#define STM32_FLASH_CR_PSIZE_MASK       (STM32_FLASH_CR_PSIZE(0x3))
-#define  FLASH_CR_STRT                  BIT(16)
-#define  FLASH_CR_LOCK                  BIT(31)
-#define STM32_FLASH_OPTCR           REG32(STM32_FLASH_REGS_BASE + 0x14)
-#define  FLASH_OPTLOCK                  BIT(0)
-#define  FLASH_OPTSTRT                  BIT(1)
-#define STM32_FLASH_BOR_LEV_OFFSET      (2)
-#define STM32_FLASH_RDP_MASK            (0xFF << 8)
-#define STM32_FLASH_nWRP_OFFSET         (16)
-#define STM32_FLASH_nWRP(_bank)         BIT(_bank + STM32_FLASH_nWRP_OFFSET)
-#define STM32_FLASH_nWRP_ALL            (0xFF << STM32_FLASH_nWRP_OFFSET)
-#define STM32_FLASH_OPT_LOCKED      (STM32_FLASH_OPTCR & FLASH_OPTLOCK)
-
-#define STM32_OPTB_RDP_USER         REG32(STM32_OPTB_BASE + 0x00)
-#define STM32_OPTB_RDP_OFF              0x00
-#define STM32_OPTB_USER_OFF             0x02
-#define STM32_OPTB_WRP_OFF(n)       (0x08 + (n&3) * 2)
-#define STM32_OPTB_WP               REG32(STM32_OPTB_BASE + 0x08)
-#define STM32_OPTB_nWRP(_bank)          BIT(_bank)
-#define STM32_OPTB_nWRP_ALL             (0xFF)
-
-#define STM32_OPTB_COMPL_SHIFT      8
-
-#define STM32_OTP_BLOCK_NB              16
-#define STM32_OTP_BLOCK_SIZE            32
+#define FLASH_SR_BUSY BIT(16)
+#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x10)
+#define FLASH_CR_PG BIT(0)
+#define FLASH_CR_PER BIT(1)
+#define FLASH_CR_MER BIT(2)
+#define STM32_FLASH_CR_SNB_OFFSET (3)
+#define STM32_FLASH_CR_SNB(sec) (((sec)&0xf) << STM32_FLASH_CR_SNB_OFFSET)
+#define STM32_FLASH_CR_SNB_MASK (STM32_FLASH_CR_SNB(0xf))
+#define STM32_FLASH_CR_PSIZE_OFFSET (8)
+#define STM32_FLASH_CR_PSIZE(size) (((size)&0x3) << STM32_FLASH_CR_PSIZE_OFFSET)
+#define STM32_FLASH_CR_PSIZE_MASK (STM32_FLASH_CR_PSIZE(0x3))
+#define FLASH_CR_STRT BIT(16)
+#define FLASH_CR_LOCK BIT(31)
+#define STM32_FLASH_OPTCR REG32(STM32_FLASH_REGS_BASE + 0x14)
+#define FLASH_OPTLOCK BIT(0)
+#define FLASH_OPTSTRT BIT(1)
+#define STM32_FLASH_BOR_LEV_OFFSET (2)
+#define STM32_FLASH_RDP_MASK (0xFF << 8)
+#define STM32_FLASH_nWRP_OFFSET (16)
+#define STM32_FLASH_nWRP(_bank) BIT(_bank + STM32_FLASH_nWRP_OFFSET)
+#define STM32_FLASH_nWRP_ALL (0xFF << STM32_FLASH_nWRP_OFFSET)
+#define STM32_FLASH_OPT_LOCKED (STM32_FLASH_OPTCR & FLASH_OPTLOCK)
+
+#define STM32_OPTB_RDP_USER REG32(STM32_OPTB_BASE + 0x00)
+#define STM32_OPTB_RDP_OFF 0x00
+#define STM32_OPTB_USER_OFF 0x02
+#define STM32_OPTB_WRP_OFF(n) (0x08 + (n & 3) * 2)
+#define STM32_OPTB_WP REG32(STM32_OPTB_BASE + 0x08)
+#define STM32_OPTB_nWRP(_bank) BIT(_bank)
+#define STM32_OPTB_nWRP_ALL (0xFF)
+
+#define STM32_OPTB_COMPL_SHIFT 8
+
+#define STM32_OTP_BLOCK_NB 16
+#define STM32_OTP_BLOCK_SIZE 32
 #define STM32_OTP_BLOCK_DATA(_block, _offset) \
-	(STM32_OTP_BASE + STM32_OTP_BLOCK_SIZE * (_block) + (_offset) * 4)
-#define STM32_OTP_UNLOCK_BYTE           0x00
-#define STM32_OTP_LOCK_BYTE             0xFF
-#define STM32_OTP_LOCK_BASE         \
+	(STM32_OTP_BASE + STM32_OTP_BLOCK_SIZE * (_block) + (_offset)*4)
+#define STM32_OTP_UNLOCK_BYTE 0x00
+#define STM32_OTP_LOCK_BYTE 0xFF
+#define STM32_OTP_LOCK_BASE \
 	(STM32_OTP_BASE + STM32_OTP_BLOCK_NB * STM32_OTP_BLOCK_SIZE)
-#define STM32_OTP_LOCK(_block) \
-	(STM32_OTP_LOCK_BASE + ((_block) / 4) * 4)
-#define STM32_OPT_LOCK_MASK(_block)    ((0xFF << ((_block) % 4) * 8))
+#define STM32_OTP_LOCK(_block) (STM32_OTP_LOCK_BASE + ((_block) / 4) * 4)
+#define STM32_OPT_LOCK_MASK(_block) ((0xFF << ((_block) % 4) * 8))
 
 /* --- External Interrupts --- */
-#define STM32_EXTI_IMR              REG32(STM32_EXTI_BASE + 0x00)
-#define STM32_EXTI_EMR              REG32(STM32_EXTI_BASE + 0x04)
-#define STM32_EXTI_RTSR             REG32(STM32_EXTI_BASE + 0x08)
-#define STM32_EXTI_FTSR             REG32(STM32_EXTI_BASE + 0x0c)
-#define STM32_EXTI_SWIER            REG32(STM32_EXTI_BASE + 0x10)
-#define STM32_EXTI_PR               REG32(STM32_EXTI_BASE + 0x14)
+#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00)
+#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04)
+#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08)
+#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c)
+#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10)
+#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14)
 
 #define EXTI_RTC_ALR_EVENT BIT(17)
 
 /* --- ADC --- */
-#define STM32_ADC_SR               REG32(STM32_ADC1_BASE + 0x00)
-#define STM32_ADC_CR1              REG32(STM32_ADC1_BASE + 0x04)
-#define STM32_ADC_CR2              REG32(STM32_ADC1_BASE + 0x08)
-#define STM32_ADC_CR2_ADON         BIT(0)
-#define STM32_ADC_CR2_CONT         BIT(1)
-#define STM32_ADC_CR2_CAL          BIT(2)
-#define STM32_ADC_CR2_RSTCAL       BIT(3)
-#define STM32_ADC_CR2_ALIGN        BIT(11)
-#define STM32_ADC_CR2_SWSTART      BIT(30)
-#define STM32_ADC_SMPR1            REG32(STM32_ADC1_BASE + 0x0C)
-#define STM32_ADC_SMPR2            REG32(STM32_ADC1_BASE + 0x10)
-#define STM32_ADC_JOFR(n)          REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4)
-#define STM32_ADC_HTR              REG32(STM32_ADC1_BASE + 0x24)
-#define STM32_ADC_LTR              REG32(STM32_ADC1_BASE + 0x28)
-#define STM32_ADC_SQR(n)           REG32(STM32_ADC1_BASE + 0x28 + ((n)&3) * 4)
-#define STM32_ADC_SQR1             REG32(STM32_ADC1_BASE + 0x2C)
-#define STM32_ADC_SQR2             REG32(STM32_ADC1_BASE + 0x30)
-#define STM32_ADC_SQR3             REG32(STM32_ADC1_BASE + 0x34)
-#define STM32_ADC_JSQR             REG32(STM32_ADC1_BASE + 0x38)
-#define STM32_ADC_JDR(n)           REG32(STM32_ADC1_BASE + 0x3C + ((n)&3) * 4)
-#define STM32_ADC_DR               REG32(STM32_ADC1_BASE + 0x4C)
+#define STM32_ADC_SR REG32(STM32_ADC1_BASE + 0x00)
+#define STM32_ADC_CR1 REG32(STM32_ADC1_BASE + 0x04)
+#define STM32_ADC_CR2 REG32(STM32_ADC1_BASE + 0x08)
+#define STM32_ADC_CR2_ADON BIT(0)
+#define STM32_ADC_CR2_CONT BIT(1)
+#define STM32_ADC_CR2_CAL BIT(2)
+#define STM32_ADC_CR2_RSTCAL BIT(3)
+#define STM32_ADC_CR2_ALIGN BIT(11)
+#define STM32_ADC_CR2_SWSTART BIT(30)
+#define STM32_ADC_SMPR1 REG32(STM32_ADC1_BASE + 0x0C)
+#define STM32_ADC_SMPR2 REG32(STM32_ADC1_BASE + 0x10)
+#define STM32_ADC_JOFR(n) REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4)
+#define STM32_ADC_HTR REG32(STM32_ADC1_BASE + 0x24)
+#define STM32_ADC_LTR REG32(STM32_ADC1_BASE + 0x28)
+#define STM32_ADC_SQR(n) REG32(STM32_ADC1_BASE + 0x28 + ((n)&3) * 4)
+#define STM32_ADC_SQR1 REG32(STM32_ADC1_BASE + 0x2C)
+#define STM32_ADC_SQR2 REG32(STM32_ADC1_BASE + 0x30)
+#define STM32_ADC_SQR3 REG32(STM32_ADC1_BASE + 0x34)
+#define STM32_ADC_JSQR REG32(STM32_ADC1_BASE + 0x38)
+#define STM32_ADC_JDR(n) REG32(STM32_ADC1_BASE + 0x3C + ((n)&3) * 4)
+#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x4C)
 
 /* --- Comparators --- */
 
-
 /* --- DMA --- */
 /*
  * Available DMA streams, numbered from 0.
@@ -798,7 +791,7 @@ enum dma_channel {
 	STM32_DMAC_FMPI2C4_TX = STM32_DMA1_STREAM5,
 	STM32_DMAC_FMPI2C4_RX = STM32_DMA1_STREAM2,
 
-	/* Legacy naming for spi_master.c */
+	/* Legacy naming for spi_controller.c */
 	STM32_DMAC_SPI1_TX = STM32_DMA2_STREAM3, /* REQ 3 */
 	STM32_DMAC_SPI1_RX = STM32_DMA2_STREAM0, /* REQ 3 */
 	STM32_DMAC_SPI2_TX = STM32_DMA1_STREAM4, /* REQ 0 */
@@ -838,12 +831,12 @@ enum dma_channel {
 
 /* Registers for a single stream of a DMA controller */
 struct stm32_dma_stream {
-	uint32_t	scr;		/* Control */
-	uint32_t	sndtr;		/* Number of data to transfer */
-	uint32_t	spar;		/* Peripheral address */
-	uint32_t	sm0ar;		/* Memory address 0 */
-	uint32_t	sm1ar;		/*  address 1 for double buffer */
-	uint32_t	sfcr;		/* FIFO control */
+	uint32_t scr; /* Control */
+	uint32_t sndtr; /* Number of data to transfer */
+	uint32_t spar; /* Peripheral address */
+	uint32_t sm0ar; /* Memory address 0 */
+	uint32_t sm1ar; /*  address 1 for double buffer */
+	uint32_t sfcr; /* FIFO control */
 };
 
 /* Always use stm32_dma_stream_t so volatile keyword is included! */
@@ -852,12 +845,11 @@ typedef volatile struct stm32_dma_stream stm32_dma_stream_t;
 /* Common code and header file must use this */
 typedef stm32_dma_stream_t dma_chan_t;
 struct stm32_dma_regs {
-	uint32_t	isr[2];
-	uint32_t	ifcr[2];
+	uint32_t isr[2];
+	uint32_t ifcr[2];
 	stm32_dma_stream_t stream[STM32_DMAS_COUNT];
 };
 
-
 /* Always use stm32_dma_regs_t so volatile keyword is included! */
 typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
 
@@ -868,215 +860,134 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
 #define STM32_DMA_REGS(channel) \
 	((channel) < STM32_DMAS_COUNT ? STM32_DMA1_REGS : STM32_DMA2_REGS)
 
-#define STM32_DMA_CCR_EN                BIT(0)
-#define STM32_DMA_CCR_DMEIE             BIT(1)
-#define STM32_DMA_CCR_TEIE              BIT(2)
-#define STM32_DMA_CCR_HTIE              BIT(3)
-#define STM32_DMA_CCR_TCIE              BIT(4)
-#define STM32_DMA_CCR_PFCTRL            BIT(5)
-#define STM32_DMA_CCR_DIR_P2M		(0 << 6)
-#define STM32_DMA_CCR_DIR_M2P		(1 << 6)
-#define STM32_DMA_CCR_DIR_M2M		(2 << 6)
-#define STM32_DMA_CCR_CIRC              BIT(8)
-#define STM32_DMA_CCR_PINC              BIT(9)
-#define STM32_DMA_CCR_MINC              BIT(10)
-#define STM32_DMA_CCR_PSIZE_8_BIT       (0 << 11)
-#define STM32_DMA_CCR_PSIZE_16_BIT      (1 << 11)
-#define STM32_DMA_CCR_PSIZE_32_BIT      (2 << 11)
-#define STM32_DMA_CCR_MSIZE_8_BIT       (0 << 13)
-#define STM32_DMA_CCR_MSIZE_16_BIT      (1 << 13)
-#define STM32_DMA_CCR_MSIZE_32_BIT      (2 << 13)
-#define STM32_DMA_CCR_PINCOS            BIT(15)
-#define STM32_DMA_CCR_PL_LOW            (0 << 16)
-#define STM32_DMA_CCR_PL_MEDIUM         (1 << 16)
-#define STM32_DMA_CCR_PL_HIGH           (2 << 16)
-#define STM32_DMA_CCR_PL_VERY_HIGH      (3 << 16)
-#define STM32_DMA_CCR_DBM               BIT(18)
-#define STM32_DMA_CCR_CT                BIT(19)
-#define STM32_DMA_CCR_PBURST(b_len)		 ((((b_len) - 4) / 4) << 21)
-#define STM32_DMA_CCR_MBURST(b_len)		 ((((b_len) - 4) / 4) << 21)
-#define STM32_DMA_CCR_CHANNEL_MASK		 (0x7 << 25)
-#define STM32_DMA_CCR_CHANNEL(channel)		 ((channel) << 25)
-#define STM32_DMA_CCR_RSVD_MASK		(0xF0100000)
-
-
-#define STM32_DMA_SFCR_DMDIS		BIT(2)
-#define STM32_DMA_SFCR_FTH(level)	(((level) - 1) << 0)
-
-
-#define STM32_DMA_CH_LOCAL(channel)     ((channel) % STM32_DMAS_COUNT)
-#define STM32_DMA_CH_LH(channel)        \
-	((STM32_DMA_CH_LOCAL(channel) < 4) ? 0 : 1)
-#define STM32_DMA_CH_OFFSET(channel)    \
+#define STM32_DMA_CCR_EN BIT(0)
+#define STM32_DMA_CCR_DMEIE BIT(1)
+#define STM32_DMA_CCR_TEIE BIT(2)
+#define STM32_DMA_CCR_HTIE BIT(3)
+#define STM32_DMA_CCR_TCIE BIT(4)
+#define STM32_DMA_CCR_PFCTRL BIT(5)
+#define STM32_DMA_CCR_DIR_P2M (0 << 6)
+#define STM32_DMA_CCR_DIR_M2P (1 << 6)
+#define STM32_DMA_CCR_DIR_M2M (2 << 6)
+#define STM32_DMA_CCR_CIRC BIT(8)
+#define STM32_DMA_CCR_PINC BIT(9)
+#define STM32_DMA_CCR_MINC BIT(10)
+#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 11)
+#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 11)
+#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 11)
+#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 13)
+#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 13)
+#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 13)
+#define STM32_DMA_CCR_PINCOS BIT(15)
+#define STM32_DMA_CCR_PL_LOW (0 << 16)
+#define STM32_DMA_CCR_PL_MEDIUM (1 << 16)
+#define STM32_DMA_CCR_PL_HIGH (2 << 16)
+#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 16)
+#define STM32_DMA_CCR_DBM BIT(18)
+#define STM32_DMA_CCR_CT BIT(19)
+#define STM32_DMA_CCR_PBURST(b_len) ((((b_len)-4) / 4) << 21)
+#define STM32_DMA_CCR_MBURST(b_len) ((((b_len)-4) / 4) << 21)
+#define STM32_DMA_CCR_CHANNEL_MASK (0x7 << 25)
+#define STM32_DMA_CCR_CHANNEL(channel) ((channel) << 25)
+#define STM32_DMA_CCR_RSVD_MASK (0xF0100000)
+
+#define STM32_DMA_SFCR_DMDIS BIT(2)
+#define STM32_DMA_SFCR_FTH(level) (((level)-1) << 0)
+
+#define STM32_DMA_CH_LOCAL(channel) ((channel) % STM32_DMAS_COUNT)
+#define STM32_DMA_CH_LH(channel) ((STM32_DMA_CH_LOCAL(channel) < 4) ? 0 : 1)
+#define STM32_DMA_CH_OFFSET(channel)               \
 	(((STM32_DMA_CH_LOCAL(channel) % 4) * 6) + \
-	(((STM32_DMA_CH_LOCAL(channel) % 4) >= 2) ? 4 : 0))
+	 (((STM32_DMA_CH_LOCAL(channel) % 4) >= 2) ? 4 : 0))
 #define STM32_DMA_CH_GETBITS(channel, val) \
 	(((val) >> STM32_DMA_CH_OFFSET(channel)) & 0x3f)
-#define STM32_DMA_GET_IFCR(channel)      \
-	(STM32_DMA_CH_GETBITS(channel,   \
-	STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)]))
-#define STM32_DMA_GET_ISR(channel)       \
-	(STM32_DMA_CH_GETBITS(channel,   \
-	STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)]))
-
-#define STM32_DMA_SET_IFCR(channel, val) \
-	(STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] = \
-	(STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] & \
-	~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel)))
-#define STM32_DMA_SET_ISR(channel, val) \
-	(STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] = \
-	(STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] & \
-	~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel)))
-
-#define STM32_DMA_FEIF                  BIT(0)
-#define STM32_DMA_DMEIF                 BIT(2)
-#define STM32_DMA_TEIF                  BIT(3)
-#define STM32_DMA_HTIF                  BIT(4)
-#define STM32_DMA_TCIF                  BIT(5)
-#define STM32_DMA_ALL                   0x3d
-
-
+#define STM32_DMA_GET_IFCR(channel) \
+	(STM32_DMA_CH_GETBITS(      \
+		channel,            \
+		STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)]))
+#define STM32_DMA_GET_ISR(channel) \
+	(STM32_DMA_CH_GETBITS(     \
+		channel,           \
+		STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)]))
+
+#define STM32_DMA_SET_IFCR(channel, val)                                    \
+	(STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] =          \
+		 (STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] & \
+		  ~(0x3f << STM32_DMA_CH_OFFSET(channel))) |                \
+		 (((val)&0x3f) << STM32_DMA_CH_OFFSET(channel)))
+#define STM32_DMA_SET_ISR(channel, val)                                    \
+	(STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] =          \
+		 (STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] & \
+		  ~(0x3f << STM32_DMA_CH_OFFSET(channel))) |               \
+		 (((val)&0x3f) << STM32_DMA_CH_OFFSET(channel)))
+
+#define STM32_DMA_FEIF BIT(0)
+#define STM32_DMA_DMEIF BIT(2)
+#define STM32_DMA_TEIF BIT(3)
+#define STM32_DMA_HTIF BIT(4)
+#define STM32_DMA_TCIF BIT(5)
+#define STM32_DMA_ALL 0x3d
 
 /* --- CRC --- */
-#define STM32_CRC_DR                REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR32              REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR16              REG16(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR8               REG8(STM32_CRC_BASE + 0x0)
-
-#define STM32_CRC_IDR               REG32(STM32_CRC_BASE + 0x4)
-#define STM32_CRC_CR                REG32(STM32_CRC_BASE + 0x8)
-#define STM32_CRC_INIT              REG32(STM32_CRC_BASE + 0x10)
-#define STM32_CRC_POL               REG32(STM32_CRC_BASE + 0x14)
-
-#define STM32_CRC_CR_RESET          BIT(0)
-#define STM32_CRC_CR_POLYSIZE_32    (0 << 3)
-#define STM32_CRC_CR_POLYSIZE_16    (1 << 3)
-#define STM32_CRC_CR_POLYSIZE_8     (2 << 3)
-#define STM32_CRC_CR_POLYSIZE_7     (3 << 3)
-#define STM32_CRC_CR_REV_IN_BYTE    (1 << 5)
-#define STM32_CRC_CR_REV_IN_HWORD   (2 << 5)
-#define STM32_CRC_CR_REV_IN_WORD    (3 << 5)
-#define STM32_CRC_CR_REV_OUT        BIT(7)
+#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0)
+
+#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4)
+#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8)
+#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10)
+#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14)
+
+#define STM32_CRC_CR_RESET BIT(0)
+#define STM32_CRC_CR_POLYSIZE_32 (0 << 3)
+#define STM32_CRC_CR_POLYSIZE_16 (1 << 3)
+#define STM32_CRC_CR_POLYSIZE_8 (2 << 3)
+#define STM32_CRC_CR_POLYSIZE_7 (3 << 3)
+#define STM32_CRC_CR_REV_IN_BYTE (1 << 5)
+#define STM32_CRC_CR_REV_IN_HWORD (2 << 5)
+#define STM32_CRC_CR_REV_IN_WORD (3 << 5)
+#define STM32_CRC_CR_REV_OUT BIT(7)
 
 /* --- PMSE --- */
-#define STM32_PMSE_ARCR             REG32(STM32_PMSE_BASE + 0x0)
-#define STM32_PMSE_ACCR             REG32(STM32_PMSE_BASE + 0x4)
-#define STM32_PMSE_CR               REG32(STM32_PMSE_BASE + 0x8)
-#define STM32_PMSE_CRTDR            REG32(STM32_PMSE_BASE + 0x14)
-#define STM32_PMSE_IER              REG32(STM32_PMSE_BASE + 0x18)
-#define STM32_PMSE_SR               REG32(STM32_PMSE_BASE + 0x1c)
-#define STM32_PMSE_IFCR             REG32(STM32_PMSE_BASE + 0x20)
-#define STM32_PMSE_PxPMR(x)         REG32(STM32_PMSE_BASE + 0x2c + (x) * 4)
-#define STM32_PMSE_PAPMR            REG32(STM32_PMSE_BASE + 0x2c)
-#define STM32_PMSE_PBPMR            REG32(STM32_PMSE_BASE + 0x30)
-#define STM32_PMSE_PCPMR            REG32(STM32_PMSE_BASE + 0x34)
-#define STM32_PMSE_PDPMR            REG32(STM32_PMSE_BASE + 0x38)
-#define STM32_PMSE_PEPMR            REG32(STM32_PMSE_BASE + 0x3c)
-#define STM32_PMSE_PFPMR            REG32(STM32_PMSE_BASE + 0x40)
-#define STM32_PMSE_PGPMR            REG32(STM32_PMSE_BASE + 0x44)
-#define STM32_PMSE_PHPMR            REG32(STM32_PMSE_BASE + 0x48)
-#define STM32_PMSE_PIPMR            REG32(STM32_PMSE_BASE + 0x4c)
-#define STM32_PMSE_MRCR             REG32(STM32_PMSE_BASE + 0x100)
-#define STM32_PMSE_MCCR             REG32(STM32_PMSE_BASE + 0x104)
-
-/* --- USB --- */
-#define STM32_USB_EP(n)            REG16(STM32_USB_FS_BASE + (n) * 4)
-
-#define STM32_USB_CNTR             REG16(STM32_USB_FS_BASE + 0x40)
-
-#define STM32_USB_CNTR_FRES	    BIT(0)
-#define STM32_USB_CNTR_PDWN	    BIT(1)
-#define STM32_USB_CNTR_LP_MODE	    BIT(2)
-#define STM32_USB_CNTR_FSUSP	    BIT(3)
-#define STM32_USB_CNTR_RESUME	    BIT(4)
-#define STM32_USB_CNTR_L1RESUME	    BIT(5)
-#define STM32_USB_CNTR_L1REQM	    BIT(7)
-#define STM32_USB_CNTR_ESOFM	    BIT(8)
-#define STM32_USB_CNTR_SOFM	    BIT(9)
-#define STM32_USB_CNTR_RESETM	    BIT(10)
-#define STM32_USB_CNTR_SUSPM	    BIT(11)
-#define STM32_USB_CNTR_WKUPM	    BIT(12)
-#define STM32_USB_CNTR_ERRM	    BIT(13)
-#define STM32_USB_CNTR_PMAOVRM	    BIT(14)
-#define STM32_USB_CNTR_CTRM	    BIT(15)
-
-#define STM32_USB_ISTR             REG16(STM32_USB_FS_BASE + 0x44)
-
-#define STM32_USB_ISTR_EP_ID_MASK   (0x000f)
-#define STM32_USB_ISTR_DIR	    BIT(4)
-#define STM32_USB_ISTR_L1REQ	    BIT(7)
-#define STM32_USB_ISTR_ESOF	    BIT(8)
-#define STM32_USB_ISTR_SOF	    BIT(9)
-#define STM32_USB_ISTR_RESET	    BIT(10)
-#define STM32_USB_ISTR_SUSP	    BIT(11)
-#define STM32_USB_ISTR_WKUP	    BIT(12)
-#define STM32_USB_ISTR_ERR	    BIT(13)
-#define STM32_USB_ISTR_PMAOVR	    BIT(14)
-#define STM32_USB_ISTR_CTR	    BIT(15)
-
-#define STM32_USB_FNR              REG16(STM32_USB_FS_BASE + 0x48)
-
-#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14)
-#define STM32_USB_FNR_RXDP_RXDM_MASK  (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT)
-
-#define STM32_USB_DADDR            REG16(STM32_USB_FS_BASE + 0x4C)
-#define STM32_USB_BTABLE           REG16(STM32_USB_FS_BASE + 0x50)
-#define STM32_USB_LPMCSR           REG16(STM32_USB_FS_BASE + 0x54)
-#define STM32_USB_BCDR             REG16(STM32_USB_FS_BASE + 0x58)
-
-#define STM32_USB_BCDR_BCDEN	    BIT(0)
-#define STM32_USB_BCDR_DCDEN	    BIT(1)
-#define STM32_USB_BCDR_PDEN	    BIT(2)
-#define STM32_USB_BCDR_SDEN	    BIT(3)
-#define STM32_USB_BCDR_DCDET	    BIT(4)
-#define STM32_USB_BCDR_PDET	    BIT(5)
-#define STM32_USB_BCDR_SDET	    BIT(6)
-#define STM32_USB_BCDR_PS2DET	    BIT(7)
-
-#define EP_MASK     0x0F0F
-#define EP_TX_DTOG  0x0040
-#define EP_TX_MASK  0x0030
-#define EP_TX_VALID 0x0030
-#define EP_TX_NAK   0x0020
-#define EP_TX_STALL 0x0010
-#define EP_TX_DISAB 0x0000
-#define EP_RX_DTOG  0x4000
-#define EP_RX_MASK  0x3000
-#define EP_RX_VALID 0x3000
-#define EP_RX_NAK   0x2000
-#define EP_RX_STALL 0x1000
-#define EP_RX_DISAB 0x0000
-
-#define EP_STATUS_OUT 0x0100
-
-#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK)
-#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID)
-
-#define STM32_TOGGLE_EP(n, mask, val, flags) \
-	STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \
-			^ (val)) | (flags))
+#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0)
+#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4)
+#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8)
+#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14)
+#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18)
+#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c)
+#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20)
+#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x)*4)
+#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c)
+#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30)
+#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34)
+#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38)
+#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c)
+#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40)
+#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44)
+#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48)
+#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c)
+#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100)
+#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104)
 
 /* --- TRNG --- */
-#define STM32_RNG_CR                REG32(STM32_RNG_BASE + 0x0)
-#define STM32_RNG_CR_RNGEN          BIT(2)
-#define STM32_RNG_CR_IE             BIT(3)
-#define STM32_RNG_CR_CED            BIT(5)
-#define STM32_RNG_SR                REG32(STM32_RNG_BASE + 0x4)
-#define STM32_RNG_SR_DRDY           BIT(0)
-#define STM32_RNG_DR                REG32(STM32_RNG_BASE + 0x8)
+#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0)
+#define STM32_RNG_CR_RNGEN BIT(2)
+#define STM32_RNG_CR_IE BIT(3)
+#define STM32_RNG_CR_CED BIT(5)
+#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4)
+#define STM32_RNG_SR_DRDY BIT(0)
+#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8)
 
 /* --- AXI interconnect --- */
 
 /* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */
-#define STM32_AXI_TARG_FN_MOD(x)    REG32(STM32_GPV_BASE + 0x1108 + \
-					  0x1000 * (x))
-#define  WRITE_ISS_OVERRIDE         BIT(1)
-#define  READ_ISS_OVERRIDE          BIT(0)
+#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + 0x1000 * (x))
+#define WRITE_ISS_OVERRIDE BIT(1)
+#define READ_ISS_OVERRIDE BIT(0)
 
 /* --- MISC --- */
-#define STM32_UNIQUE_ID_ADDRESS     REG32_ADDR(STM32_UNIQUE_ID_BASE)
-#define STM32_UNIQUE_ID_LENGTH      (3 * 4)
+#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE)
+#define STM32_UNIQUE_ID_LENGTH (3 * 4)
 
 #endif /* !__ASSEMBLER__ */
diff --git a/chip/stm32/registers-stm32g4.h b/chip/stm32/registers-stm32g4.h
index 4fe97e4c29..a19aa942b0 100644
--- a/chip/stm32/registers-stm32g4.h
+++ b/chip/stm32/registers-stm32g4.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,87 +19,87 @@
 #endif
 
 /* --- IRQ numbers --- */
-#define STM32_IRQ_WWDG             0
-#define STM32_IRQ_PVD              1
-#define STM32_IRQ_TAMPER_STAMP     2
-#define STM32_IRQ_RTC_WAKEUP       3
-#define STM32_IRQ_FLASH            4
-#define STM32_IRQ_RCC              5
-#define STM32_IRQ_EXTI0            6
-#define STM32_IRQ_EXTI1            7
-#define STM32_IRQ_EXTI2            8
-#define STM32_IRQ_EXTI3            9
-#define STM32_IRQ_EXTI4           10
-#define STM32_IRQ_DMA_CHANNEL_1   11
-#define STM32_IRQ_DMA_CHANNEL_2   12
-#define STM32_IRQ_DMA_CHANNEL_3   13
-#define STM32_IRQ_DMA_CHANNEL_4   14
-#define STM32_IRQ_DMA_CHANNEL_5   15
-#define STM32_IRQ_DMA_CHANNEL_6   16
-#define STM32_IRQ_DMA_CHANNEL_7   17
-#define STM32_IRQ_ADC1            18
-#define STM32_IRQ_USB_HP          19
-#define STM32_IRQ_USB_LP          20
-#define STM32_IRQ_FDCAN_IT0       21
-#define STM32_IRQ_FDCAN_IT1       22
-#define STM32_IRQ_EXTI9_5         23
-#define STM32_IRQ_TIM15           24
-#define STM32_IRQ_TIM16           25
-#define STM32_IRQ_TIM17           26
-#define STM32_IRQ_TIM1_CC         27
-#define STM32_IRQ_TIM2            28
-#define STM32_IRQ_TIM3            29
-#define STM32_IRQ_TIM4            30
-#define STM32_IRQ_I2C1_EV         31
-#define STM32_IRQ_I2C1_ER         32
-#define STM32_IRQ_I2C2_EV         33
-#define STM32_IRQ_I2C2_ER         34
-#define STM32_IRQ_SPI1            35
-#define STM32_IRQ_SPI2            36
-#define STM32_IRQ_USART1          37
-#define STM32_IRQ_USART2          38
-#define STM32_IRQ_USART3          39
-#define STM32_IRQ_EXTI15_10       40
-#define STM32_IRQ_RTC_ALARM       41
-#define STM32_IRQ_USB_FS_WAKEUP   42
-#define STM32_IRQ_TIM8_BREAK      43
-#define STM32_IRQ_TIM8_UP         44
-#define STM32_IRQ_TIM8_TRG_COM    45
-#define STM32_IRQ_TIM8_CC         46
-#define STM32_IRQ_LPTIM1          49
-#define STM32_IRQ_SPI3            51
-#define STM32_IRQ_USART4          52
-#define STM32_IRQ_TIM6_DAC        54
-#define STM32_IRQ_TIM7            55
-#define STM32_IRQ_DMA2_CHANNEL1   56
-#define STM32_IRQ_DMA2_CHANNEL2   57
-#define STM32_IRQ_DMA2_CHANNEL3   58
-#define STM32_IRQ_DMA2_CHANNEL4   59
-#define STM32_IRQ_DMA2_CHANNEL5   60
-#define STM32_IRQ_UCPD1           63
-#define STM32_IRQ_COMP_1_2_3      64
-#define STM32_IRQ_COMP_4          65
-#define STM32_IRQ_CRS             75
-#define STM32_IRQ_SAI1            76
-#define STM32_IRQ_FPU             81
-#define STM32_IRQ_RNG             90
-#define STM32_IRQ_LPUART          91
-#define STM32_IRQ_I2C3_EV         92
-#define STM32_IRQ_I2C3_ER         93
-#define STM32_IRQ_DMAMUX_OVR      94
-#define STM32_IRQ_DMA1_CHANNEL8   96
-#define STM32_IRQ_DMA2_CHANNEL6   97
-#define STM32_IRQ_DMA2_CHANNEL7   98
-#define STM32_IRQ_DMA2_CHANNEL8   99
-#define STM32_IRQ_CORDIC          100
-#define STM32_IRQ_FMAC            101
+#define STM32_IRQ_WWDG 0
+#define STM32_IRQ_PVD 1
+#define STM32_IRQ_TAMPER_STAMP 2
+#define STM32_IRQ_RTC_WAKEUP 3
+#define STM32_IRQ_FLASH 4
+#define STM32_IRQ_RCC 5
+#define STM32_IRQ_EXTI0 6
+#define STM32_IRQ_EXTI1 7
+#define STM32_IRQ_EXTI2 8
+#define STM32_IRQ_EXTI3 9
+#define STM32_IRQ_EXTI4 10
+#define STM32_IRQ_DMA_CHANNEL_1 11
+#define STM32_IRQ_DMA_CHANNEL_2 12
+#define STM32_IRQ_DMA_CHANNEL_3 13
+#define STM32_IRQ_DMA_CHANNEL_4 14
+#define STM32_IRQ_DMA_CHANNEL_5 15
+#define STM32_IRQ_DMA_CHANNEL_6 16
+#define STM32_IRQ_DMA_CHANNEL_7 17
+#define STM32_IRQ_ADC1 18
+#define STM32_IRQ_USB_HP 19
+#define STM32_IRQ_USB_LP 20
+#define STM32_IRQ_FDCAN_IT0 21
+#define STM32_IRQ_FDCAN_IT1 22
+#define STM32_IRQ_EXTI9_5 23
+#define STM32_IRQ_TIM15 24
+#define STM32_IRQ_TIM16 25
+#define STM32_IRQ_TIM17 26
+#define STM32_IRQ_TIM1_CC 27
+#define STM32_IRQ_TIM2 28
+#define STM32_IRQ_TIM3 29
+#define STM32_IRQ_TIM4 30
+#define STM32_IRQ_I2C1_EV 31
+#define STM32_IRQ_I2C1_ER 32
+#define STM32_IRQ_I2C2_EV 33
+#define STM32_IRQ_I2C2_ER 34
+#define STM32_IRQ_SPI1 35
+#define STM32_IRQ_SPI2 36
+#define STM32_IRQ_USART1 37
+#define STM32_IRQ_USART2 38
+#define STM32_IRQ_USART3 39
+#define STM32_IRQ_EXTI15_10 40
+#define STM32_IRQ_RTC_ALARM 41
+#define STM32_IRQ_USB_FS_WAKEUP 42
+#define STM32_IRQ_TIM8_BREAK 43
+#define STM32_IRQ_TIM8_UP 44
+#define STM32_IRQ_TIM8_TRG_COM 45
+#define STM32_IRQ_TIM8_CC 46
+#define STM32_IRQ_LPTIM1 49
+#define STM32_IRQ_SPI3 51
+#define STM32_IRQ_USART4 52
+#define STM32_IRQ_TIM6_DAC 54
+#define STM32_IRQ_TIM7 55
+#define STM32_IRQ_DMA2_CHANNEL1 56
+#define STM32_IRQ_DMA2_CHANNEL2 57
+#define STM32_IRQ_DMA2_CHANNEL3 58
+#define STM32_IRQ_DMA2_CHANNEL4 59
+#define STM32_IRQ_DMA2_CHANNEL5 60
+#define STM32_IRQ_UCPD1 63
+#define STM32_IRQ_COMP_1_2_3 64
+#define STM32_IRQ_COMP_4 65
+#define STM32_IRQ_CRS 75
+#define STM32_IRQ_SAI1 76
+#define STM32_IRQ_FPU 81
+#define STM32_IRQ_RNG 90
+#define STM32_IRQ_LPUART 91
+#define STM32_IRQ_I2C3_EV 92
+#define STM32_IRQ_I2C3_ER 93
+#define STM32_IRQ_DMAMUX_OVR 94
+#define STM32_IRQ_DMA1_CHANNEL8 96
+#define STM32_IRQ_DMA2_CHANNEL6 97
+#define STM32_IRQ_DMA2_CHANNEL7 98
+#define STM32_IRQ_DMA2_CHANNEL8 99
+#define STM32_IRQ_CORDIC 100
+#define STM32_IRQ_FMAC 101
 
 /* LPUART gets accessed as UART9 in STM32 uart driver */
 #define STM32_IRQ_USART9 STM32_IRQ_LPUART
 
 /* To simplify code generation, define DMA channel 13 - 14 */
-#define STM32_IRQ_DMA_CHANNEL_13   STM32_IRQ_DMA2_CHANNEL6
-#define STM32_IRQ_DMA_CHANNEL_14   STM32_IRQ_DMA2_CHANNEL7
+#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6
+#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7
 
 /* aliases for easier code sharing */
 #define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV
@@ -111,142 +111,144 @@
 #endif
 
 /* Embedded flash option bytes base address */
-#define STM32_OPTB_BASE             0x1FFF7800
+#define STM32_OPTB_BANK1_BASE 0x1FFF7800UL
+#define STM32_OPTB_BANK2_BASE 0x1FFF8000UL
 
 /* Peripheral base addresses */
-#define STM32_PERIPH_BASE           (0x40000000UL)
+#define STM32_PERIPH_BASE (0x40000000UL)
 /* Peripheral memory map */
-#define STM32_APB1PERIPH_BASE       (STM32_PERIPH_BASE + 0x00000000UL)
-#define STM32_APB2PERIPH_BASE       (STM32_PERIPH_BASE + 0x00010000UL)
-#define STM32_AHB1PERIPH_BASE       (STM32_PERIPH_BASE + 0x00020000UL)
-#define STM32_AHB2PERIPH_BASE       (STM32_PERIPH_BASE + 0x08000000UL)
+#define STM32_APB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00000000UL)
+#define STM32_APB2PERIPH_BASE (STM32_PERIPH_BASE + 0x00010000UL)
+#define STM32_AHB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00020000UL)
+#define STM32_AHB2PERIPH_BASE (STM32_PERIPH_BASE + 0x08000000UL)
 
 /* APB1 peripherals */
-#define STM32_APB1PERIPH(offset)    (STM32_APB1PERIPH_BASE + offset)
-#define STM32_TIM2_BASE             STM32_APB1PERIPH(0x0000UL)
-#define STM32_TIM3_BASE             STM32_APB1PERIPH(0x0400UL)
-#define STM32_TIM4_BASE             STM32_APB1PERIPH(0x0800UL)
-#define STM32_TIM6_BASE             STM32_APB1PERIPH(0x1000UL)
-#define STM32_TIM7_BASE             STM32_APB1PERIPH(0x1400UL)
-#define STM32_CRS_BASE              STM32_APB1PERIPH(0x2000UL)
-#define STM32_TAMP_BASE             STM32_APB1PERIPH(0x2400UL)
-#define STM32_RTC_BASE              STM32_APB1PERIPH(0x2800UL)
-#define STM32_WWDG_BASE             STM32_APB1PERIPH(0x2C00UL)
-#define STM32_IWDG_BASE             STM32_APB1PERIPH(0x3000UL)
-#define STM32_SPI2_BASE             STM32_APB1PERIPH(0x3800UL)
-#define STM32_SPI3_BASE             STM32_APB1PERIPH(0x3C00UL)
-#define STM32_USART2_BASE           STM32_APB1PERIPH(0x4400UL)
-#define STM32_USART3_BASE           STM32_APB1PERIPH(0x4800UL)
-#define STM32_UART4_BASE            STM32_APB1PERIPH(0x4C00UL)
-#define STM32_I2C1_BASE             STM32_APB1PERIPH(0x5400UL)
-#define STM32_I2C2_BASE             STM32_APB1PERIPH(0x5800UL)
+#define STM32_APB1PERIPH(offset) (STM32_APB1PERIPH_BASE + offset)
+#define STM32_TIM2_BASE STM32_APB1PERIPH(0x0000UL)
+#define STM32_TIM3_BASE STM32_APB1PERIPH(0x0400UL)
+#define STM32_TIM4_BASE STM32_APB1PERIPH(0x0800UL)
+#define STM32_TIM6_BASE STM32_APB1PERIPH(0x1000UL)
+#define STM32_TIM7_BASE STM32_APB1PERIPH(0x1400UL)
+#define STM32_CRS_BASE STM32_APB1PERIPH(0x2000UL)
+#define STM32_TAMP_BASE STM32_APB1PERIPH(0x2400UL)
+#define STM32_RTC_BASE STM32_APB1PERIPH(0x2800UL)
+#define STM32_WWDG_BASE STM32_APB1PERIPH(0x2C00UL)
+#define STM32_IWDG_BASE STM32_APB1PERIPH(0x3000UL)
+#define STM32_SPI2_BASE STM32_APB1PERIPH(0x3800UL)
+#define STM32_SPI3_BASE STM32_APB1PERIPH(0x3C00UL)
+#define STM32_USART2_BASE STM32_APB1PERIPH(0x4400UL)
+#define STM32_USART3_BASE STM32_APB1PERIPH(0x4800UL)
+#define STM32_UART4_BASE STM32_APB1PERIPH(0x4C00UL)
+#define STM32_I2C1_BASE STM32_APB1PERIPH(0x5400UL)
+#define STM32_I2C2_BASE STM32_APB1PERIPH(0x5800UL)
 /* USB_IP Peripheral Registers base address */
-#define STM32_USB_BASE              STM32_APB1PERIPH(0x5C00UL)
+#define STM32_USB_FS_BASE STM32_APB1PERIPH(0x5C00UL)
 /* USB_IP Packet Memory Area base address */
-#define STM32_USB_PMAADDR           STM32_APB1PERIPH(0x6000UL)
-#define STM32_FDCAN1_BASE           STM32_APB1PERIPH(0x6400UL)
+#define STM32_USB_PMAADDR STM32_APB1PERIPH(0x6000UL)
+#define STM32_FDCAN1_BASE STM32_APB1PERIPH(0x6400UL)
 /* FDCAN configuration registers base address */
-#define STM32_FDCAN_CONFIG_BASE     STM32_APB1PERIPH(0x6500UL)
-#define STM32_PWR_BASE              STM32_APB1PERIPH(0x7000UL)
-#define STM32_I2C3_BASE             STM32_APB1PERIPH(0x7800UL)
-#define STM32_LPTIM1_BASE           STM32_APB1PERIPH(0x7C00UL)
-#define STM32_LPUART1_BASE          STM32_APB1PERIPH(0x8000UL)
-#define STM32_I2C4_BASE             STM32_APB1PERIPH(0x8400UL)
+#define STM32_FDCAN_CONFIG_BASE STM32_APB1PERIPH(0x6500UL)
+#define STM32_PWR_BASE STM32_APB1PERIPH(0x7000UL)
+#define STM32_I2C3_BASE STM32_APB1PERIPH(0x7800UL)
+#define STM32_LPTIM1_BASE STM32_APB1PERIPH(0x7C00UL)
+#define STM32_LPUART1_BASE STM32_APB1PERIPH(0x8000UL)
+#define STM32_I2C4_BASE STM32_APB1PERIPH(0x8400UL)
 /* UART9 is used as link to LPUART in STM32 uart.c implementation */
-#define STM32_USART9_BASE           STM32_APB1PERIPH(0x8000UL)
-#define STM32_UCPD1_BASE            STM32_APB1PERIPH(0xA000UL)
-#define STM32_SRAMCAN_BASE          STM32_APB1PERIPH(0xA400UL)
+#define STM32_USART9_BASE STM32_APB1PERIPH(0x8000UL)
+#define STM32_I2C4_BASE STM32_APB1PERIPH(0x8400UL)
+#define STM32_UCPD1_BASE STM32_APB1PERIPH(0xA000UL)
+#define STM32_SRAMCAN_BASE STM32_APB1PERIPH(0xA400UL)
 
 /* APB2 peripherals */
-#define STM32_APB2PERIPH(offset)    (STM32_APB2PERIPH_BASE + offset)
-#define STM32_SYSCFG_BASE           STM32_APB2PERIPH(0x0000UL)
-#define STM32_VREFBUF_BASE          STM32_APB2PERIPH(0x0030UL)
-#define STM32_COMP1_BASE            STM32_APB2PERIPH(0x0200UL)
-#define STM32_COMP2_BASE            STM32_APB2PERIPH(0x0204UL)
-#define STM32_COMP3_BASE            STM32_APB2PERIPH(0x0208UL)
-#define STM32_COMP4_BASE            STM32_APB2PERIPH(0x020CUL)
-#define STM32_OPAMP_BASE            STM32_APB2PERIPH(0x0300UL)
-#define STM32_OPAMP1_BASE           STM32_APB2PERIPH(0x0300UL)
-#define STM32_OPAMP2_BASE           STM32_APB2PERIPH(0x0304UL)
-#define STM32_OPAMP3_BASE           STM32_APB2PERIPH(0x0308UL)
-#define STM32_EXTI_BASE             STM32_APB2PERIPH(0x0400UL)
-#define STM32_TIM1_BASE             STM32_APB2PERIPH(0x2C00UL)
-#define STM32_SPI1_BASE             STM32_APB2PERIPH(0x3000UL)
-#define STM32_TIM8_BASE             STM32_APB2PERIPH(0x3400UL)
-#define STM32_USART1_BASE           STM32_APB2PERIPH(0x3800UL)
-#define STM32_TIM15_BASE            STM32_APB2PERIPH(0x4000UL)
-#define STM32_TIM16_BASE            STM32_APB2PERIPH(0x4400UL)
-#define STM32_TIM17_BASE            STM32_APB2PERIPH(0x4800UL)
-#define STM32_SAI1_BASE             STM32_APB2PERIPH(0x5400UL)
-#define STM32_SAI1_Block_A_BASE     (SAI1_BASE + 0x0004UL)
-#define STM32_SAI1_Block_B_BASE     (SAI1_BASE + 0x0024UL)
+#define STM32_APB2PERIPH(offset) (STM32_APB2PERIPH_BASE + offset)
+#define STM32_SYSCFG_BASE STM32_APB2PERIPH(0x0000UL)
+#define STM32_VREFBUF_BASE STM32_APB2PERIPH(0x0030UL)
+#define STM32_COMP1_BASE STM32_APB2PERIPH(0x0200UL)
+#define STM32_COMP2_BASE STM32_APB2PERIPH(0x0204UL)
+#define STM32_COMP3_BASE STM32_APB2PERIPH(0x0208UL)
+#define STM32_COMP4_BASE STM32_APB2PERIPH(0x020CUL)
+#define STM32_OPAMP_BASE STM32_APB2PERIPH(0x0300UL)
+#define STM32_OPAMP1_BASE STM32_APB2PERIPH(0x0300UL)
+#define STM32_OPAMP2_BASE STM32_APB2PERIPH(0x0304UL)
+#define STM32_OPAMP3_BASE STM32_APB2PERIPH(0x0308UL)
+#define STM32_EXTI_BASE STM32_APB2PERIPH(0x0400UL)
+#define STM32_TIM1_BASE STM32_APB2PERIPH(0x2C00UL)
+#define STM32_SPI1_BASE STM32_APB2PERIPH(0x3000UL)
+#define STM32_TIM8_BASE STM32_APB2PERIPH(0x3400UL)
+#define STM32_USART1_BASE STM32_APB2PERIPH(0x3800UL)
+#define STM32_TIM15_BASE STM32_APB2PERIPH(0x4000UL)
+#define STM32_TIM16_BASE STM32_APB2PERIPH(0x4400UL)
+#define STM32_TIM17_BASE STM32_APB2PERIPH(0x4800UL)
+#define STM32_SAI1_BASE STM32_APB2PERIPH(0x5400UL)
+#define STM32_SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL)
+#define STM32_SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL)
 
 /* AHB1 peripherals */
-#define STM32_AHB1PERIPH(offset)    (STM32_AHB1PERIPH_BASE + offset)
-#define STM32_DMA1_BASE             STM32_AHB1PERIPH(0x0000UL)
-#define STM32_DMA2_BASE             STM32_AHB1PERIPH(0x0400UL)
-#define STM32_DMAMUX_BASE           STM32_AHB1PERIPH(0x0800UL)
-#define STM32_CORDIC_BASE           STM32_AHB1PERIPH(0x0C00UL)
-#define STM32_RCC_BASE              STM32_AHB1PERIPH(0x1000UL)
-#define STM32_FMAC_BASE             STM32_AHB1PERIPH(0x1400UL)
-#define STM32_FLASH_REGS_BASE       STM32_AHB1PERIPH(0x2000UL)
-#define STM32_CRC_BASE              STM32_AHB1PERIPH(0x3000UL)
-
-#define STM32_DMA1_CHAN(offset)     (STM32_DMA1_BASE + offset)
-#define STM32_DMA1_Channel1_BASE    STM32_DMA1_CHAN(0x0008UL)
-#define STM32_DMA1_Channel2_BASE    STM32_DMA1_CHAN(0x001CUL)
-#define STM32_DMA1_Channel3_BASE    STM32_DMA1_CHAN(0x0030UL)
-#define STM32_DMA1_Channel4_BASE    STM32_DMA1_CHAN(0x0044UL)
-#define STM32_DMA1_Channel5_BASE    STM32_DMA1_CHAN(0x0058UL)
-#define STM32_DMA1_Channel6_BASE    STM32_DMA1_CHAN(0x006CUL)
-
-#define STM32_DMA2_CHAN(offset)     (STM32_DMA2_BASE + offset)
-#define STM32_DMA2_Channel1_BASE    STM32_DMA2_CHAN(0x0008UL)
-#define STM32_DMA2_Channel2_BASE    STM32_DMA2_CHAN(0x001CUL)
-#define STM32_DMA2_Channel3_BASE    STM32_DMA2_CHAN(0x0030UL)
-#define STM32_DMA2_Channel4_BASE    STM32_DMA2_CHAN(0x0044UL)
-#define STM32_DMA2_Channel5_BASE    STM32_DMA2_CHAN(0x0058UL)
-#define STM32_DMA2_Channel6_BASE    STM32_DMA2_CHAN(0x006CUL)
-
-#define STM32_DMAMUX(offset)          (STM32_DMAMUX_BASE + offset)
-#define STM32_DMAMUX_Channel0_BASE    STM32_DMAMUX(0x0000UL)
-#define STM32_DMAMUX_Channel1_BASE    STM32_DMAMUX(0x0004UL)
-#define STM32_DMAMUX_Channel2_BASE    STM32_DMAMUX(0x0008UL)
-#define STM32_DMAMUX_Channel3_BASE    STM32_DMAMUX(0x000CUL)
-#define STM32_DMAMUX_Channel4_BASE    STM32_DMAMUX(0x0010UL)
-#define STM32_DMAMUX_Channel5_BASE    STM32_DMAMUX(0x0014UL)
-#define STM32_DMAMUX_Channel6_BASE    STM32_DMAMUX(0x0020UL)
-#define STM32_DMAMUX_Channel7_BASE    STM32_DMAMUX(0x0024UL)
-#define STM32_DMAMUX_Channel8_BASE    STM32_DMAMUX(0x0028UL)
-#define STM32_DMAMUX_Channel9_BASE    STM32_DMAMUX(0x002CUL)
-#define STM32_DMAMUX_Channel10_BASE   STM32_DMAMUX(0x0030UL)
-#define STM32_DMAMUX_Channel11_BASE   STM32_DMAMUX(0x0034UL)
-#define STM32_DMAMUX_RequestGenerator0_BASE  STM32_DMAMUX(0x0100UL)
-#define STM32_DMAMUX_RequestGenerator1_BASE  STM32_DMAMUX(0x0104UL)
-#define STM32_DMAMUX_RequestGenerator2_BASE  STM32_DMAMUX(0x0108UL)
-#define STM32_DMAMUX_RequestGenerator3_BASE  STM32_DMAMUX(0x010CUL)
-#define STM32_DMAMUX_ChannelStatus_BASE      STM32_DMAMUX(0x0080UL)
-#define STM32_DMAMUX_RequestGenStatus_BASE   STM32_DMAMUX(0x0140UL)
+#define STM32_AHB1PERIPH(offset) (STM32_AHB1PERIPH_BASE + offset)
+#define STM32_DMA1_BASE STM32_AHB1PERIPH(0x0000UL)
+#define STM32_DMA2_BASE STM32_AHB1PERIPH(0x0400UL)
+#define STM32_DMAMUX_BASE STM32_AHB1PERIPH(0x0800UL)
+#define STM32_CORDIC_BASE STM32_AHB1PERIPH(0x0C00UL)
+#define STM32_RCC_BASE STM32_AHB1PERIPH(0x1000UL)
+#define STM32_FMAC_BASE STM32_AHB1PERIPH(0x1400UL)
+#define STM32_FLASH_REGS_BASE STM32_AHB1PERIPH(0x2000UL)
+#define STM32_CRC_BASE STM32_AHB1PERIPH(0x3000UL)
+
+#define STM32_DMA1_CHAN(offset) (STM32_DMA1_BASE + offset)
+#define STM32_DMA1_Channel1_BASE STM32_DMA1_CHAN(0x0008UL)
+#define STM32_DMA1_Channel2_BASE STM32_DMA1_CHAN(0x001CUL)
+#define STM32_DMA1_Channel3_BASE STM32_DMA1_CHAN(0x0030UL)
+#define STM32_DMA1_Channel4_BASE STM32_DMA1_CHAN(0x0044UL)
+#define STM32_DMA1_Channel5_BASE STM32_DMA1_CHAN(0x0058UL)
+#define STM32_DMA1_Channel6_BASE STM32_DMA1_CHAN(0x006CUL)
+
+#define STM32_DMA2_CHAN(offset) (STM32_DMA2_BASE + offset)
+#define STM32_DMA2_Channel1_BASE STM32_DMA2_CHAN(0x0008UL)
+#define STM32_DMA2_Channel2_BASE STM32_DMA2_CHAN(0x001CUL)
+#define STM32_DMA2_Channel3_BASE STM32_DMA2_CHAN(0x0030UL)
+#define STM32_DMA2_Channel4_BASE STM32_DMA2_CHAN(0x0044UL)
+#define STM32_DMA2_Channel5_BASE STM32_DMA2_CHAN(0x0058UL)
+#define STM32_DMA2_Channel6_BASE STM32_DMA2_CHAN(0x006CUL)
+
+#define STM32_DMAMUX(offset) (STM32_DMAMUX_BASE + offset)
+#define STM32_DMAMUX_Channel0_BASE STM32_DMAMUX(0x0000UL)
+#define STM32_DMAMUX_Channel1_BASE STM32_DMAMUX(0x0004UL)
+#define STM32_DMAMUX_Channel2_BASE STM32_DMAMUX(0x0008UL)
+#define STM32_DMAMUX_Channel3_BASE STM32_DMAMUX(0x000CUL)
+#define STM32_DMAMUX_Channel4_BASE STM32_DMAMUX(0x0010UL)
+#define STM32_DMAMUX_Channel5_BASE STM32_DMAMUX(0x0014UL)
+#define STM32_DMAMUX_Channel6_BASE STM32_DMAMUX(0x0020UL)
+#define STM32_DMAMUX_Channel7_BASE STM32_DMAMUX(0x0024UL)
+#define STM32_DMAMUX_Channel8_BASE STM32_DMAMUX(0x0028UL)
+#define STM32_DMAMUX_Channel9_BASE STM32_DMAMUX(0x002CUL)
+#define STM32_DMAMUX_Channel10_BASE STM32_DMAMUX(0x0030UL)
+#define STM32_DMAMUX_Channel11_BASE STM32_DMAMUX(0x0034UL)
+#define STM32_DMAMUX_RequestGenerator0_BASE STM32_DMAMUX(0x0100UL)
+#define STM32_DMAMUX_RequestGenerator1_BASE STM32_DMAMUX(0x0104UL)
+#define STM32_DMAMUX_RequestGenerator2_BASE STM32_DMAMUX(0x0108UL)
+#define STM32_DMAMUX_RequestGenerator3_BASE STM32_DMAMUX(0x010CUL)
+#define STM32_DMAMUX_ChannelStatus_BASE STM32_DMAMUX(0x0080UL)
+#define STM32_DMAMUX_RequestGenStatus_BASE STM32_DMAMUX(0x0140UL)
 
 /* AHB2 peripherals */
-#define STM32_AHB2PERIPH(offset)    (STM32_AHB2PERIPH_BASE + offset)
-#define STM32_GPIOA_BASE            STM32_AHB2PERIPH(0x0000UL)
-#define STM32_GPIOB_BASE            STM32_AHB2PERIPH(0x0400UL)
-#define STM32_GPIOC_BASE            STM32_AHB2PERIPH(0x0800UL)
-#define STM32_GPIOD_BASE            STM32_AHB2PERIPH(0x0C00UL)
-#define STM32_GPIOE_BASE            STM32_AHB2PERIPH(0x1000UL)
-#define STM32_GPIOF_BASE            STM32_AHB2PERIPH(0x1400UL)
-#define STM32_GPIOG_BASE            STM32_AHB2PERIPH(0x1800UL)
-#define STM32_ADC1_BASE             STM32_AHB2PERIPH(0x08000000UL)
-#define STM32_ADC2_BASE             STM32_AHB2PERIPH(0x08000100UL)
-#define STM32_ADC12_COMMON_BASE     STM32_AHB2PERIPH(0x08000300UL)
-#define STM32_DAC_BASE              STM32_AHB2PERIPH(0x08000800UL)
-#define STM32_DAC1_BASE             STM32_AHB2PERIPH(0x08000800UL)
-#define STM32_DAC3_BASE             STM32_AHB2PERIPH(0x08001000UL)
-#define STM32_RNG_BASE              STM32_AHB2PERIPH(0x08060800UL)
-
-#define STM32_UNIQUE_ID_BASE        0x1FFF7590
-#define STM32_DBGMCU_BASE           0xE0042000
+#define STM32_AHB2PERIPH(offset) (STM32_AHB2PERIPH_BASE + offset)
+#define STM32_GPIOA_BASE STM32_AHB2PERIPH(0x0000UL)
+#define STM32_GPIOB_BASE STM32_AHB2PERIPH(0x0400UL)
+#define STM32_GPIOC_BASE STM32_AHB2PERIPH(0x0800UL)
+#define STM32_GPIOD_BASE STM32_AHB2PERIPH(0x0C00UL)
+#define STM32_GPIOE_BASE STM32_AHB2PERIPH(0x1000UL)
+#define STM32_GPIOF_BASE STM32_AHB2PERIPH(0x1400UL)
+#define STM32_GPIOG_BASE STM32_AHB2PERIPH(0x1800UL)
+#define STM32_ADC1_BASE STM32_AHB2PERIPH(0x08000000UL)
+#define STM32_ADC2_BASE STM32_AHB2PERIPH(0x08000100UL)
+#define STM32_ADC12_COMMON_BASE STM32_AHB2PERIPH(0x08000300UL)
+#define STM32_DAC_BASE STM32_AHB2PERIPH(0x08000800UL)
+#define STM32_DAC1_BASE STM32_AHB2PERIPH(0x08000800UL)
+#define STM32_DAC3_BASE STM32_AHB2PERIPH(0x08001000UL)
+#define STM32_RNG_BASE STM32_AHB2PERIPH(0x08060800UL)
+
+#define STM32_UNIQUE_ID_BASE 0x1FFF7590
+#define STM32_DBGMCU_BASE 0xE0042000
 
 #ifndef __ASSEMBLER__
 
@@ -254,314 +256,299 @@
 
 /* --- UCPD --- */
 #define STM32_UCPD_REG(port, offset) \
-	REG32(((STM32_UCPD1_BASE + ((port) * 0x400)) + (offset)))
-
-#define STM32_UCPD_CFGR1(port)              STM32_UCPD_REG(port, 0x00)
-#define STM32_UCPD_CFGR2(port)              STM32_UCPD_REG(port, 0x04)
-#define STM32_UCPD_CR(port)                 STM32_UCPD_REG(port, 0x0c)
-#define STM32_UCPD_IMR(port)                STM32_UCPD_REG(port, 0x10)
-#define STM32_UCPD_SR(port)                 STM32_UCPD_REG(port, 0x14)
-#define STM32_UCPD_ICR(port)                STM32_UCPD_REG(port, 0x18)
-#define STM32_UCPD_TX_ORDSETR(port)         STM32_UCPD_REG(port, 0x1c)
-#define STM32_UCPD_TX_PAYSZR(port)          STM32_UCPD_REG(port, 0x20)
-#define STM32_UCPD_TXDR(port)               STM32_UCPD_REG(port, 0x24)
-#define STM32_UCPD_RX_ORDSETR(port)         STM32_UCPD_REG(port, 0x28)
-#define STM32_UCPD_RX_PAYSZR(port)          STM32_UCPD_REG(port, 0x2c)
-#define STM32_UCPD_RXDR(port)               STM32_UCPD_REG(port, 0x30)
-#define STM32_UCPD_RX_ORDEXTR1(port)        STM32_UCPD_REG(port, 0x34)
-#define STM32_UCPD_RX_ORDEXTR2(port)        STM32_UCPD_REG(port, 0x38)
+	REG32(((STM32_UCPD1_BASE + ((port)*0x400)) + (offset)))
+
+#define STM32_UCPD_CFGR1(port) STM32_UCPD_REG(port, 0x00)
+#define STM32_UCPD_CFGR2(port) STM32_UCPD_REG(port, 0x04)
+#define STM32_UCPD_CR(port) STM32_UCPD_REG(port, 0x0c)
+#define STM32_UCPD_IMR(port) STM32_UCPD_REG(port, 0x10)
+#define STM32_UCPD_SR(port) STM32_UCPD_REG(port, 0x14)
+#define STM32_UCPD_ICR(port) STM32_UCPD_REG(port, 0x18)
+#define STM32_UCPD_TX_ORDSETR(port) STM32_UCPD_REG(port, 0x1c)
+#define STM32_UCPD_TX_PAYSZR(port) STM32_UCPD_REG(port, 0x20)
+#define STM32_UCPD_TXDR(port) STM32_UCPD_REG(port, 0x24)
+#define STM32_UCPD_RX_ORDSETR(port) STM32_UCPD_REG(port, 0x28)
+#define STM32_UCPD_RX_PAYSZR(port) STM32_UCPD_REG(port, 0x2c)
+#define STM32_UCPD_RXDR(port) STM32_UCPD_REG(port, 0x30)
+#define STM32_UCPD_RX_ORDEXTR1(port) STM32_UCPD_REG(port, 0x34)
+#define STM32_UCPD_RX_ORDEXTR2(port) STM32_UCPD_REG(port, 0x38)
 
 /* --- UCPD CFGR1 Bit Definitions --- */
-#define STM32_UCPD_CFGR1_HBITCLKD_SHIFT     0
-#define STM32_UCPD_CFGR1_HBITCLKD_MASK      ((0x3f) << \
-					     (STM32_UCPD_CFGR1_HBITCLKD_SHIFT))
-#define STM32_UCPD_CFGR1_HBITCLKD_VAL(x)    ((x) << \
-					     STM32_UCPD_CFGR1_HBITCLKD_SHIFT)
-#define STM32_UCPD_CFGR1_IFRGAP_SHIFT       6
-#define STM32_UCPD_CFGR1_IFRGAP_MASK        ((0x1f) << \
-					     (STM32_UCPD_CFGR1_IFRGAP_SHIFT))
-#define STM32_UCPD_CFGR1_IFRGAP_VAL(x)      ((x) << \
-					     STM32_UCPD_CFGR1_IFRGAP_SHIFT)
-#define STM32_UCPD_CFGR1_TRANSWIN_SHIFT     11
-#define STM32_UCPD_CFGR1_TRANSWIN_MASK      ((0x1f) << \
-					     (STM32_UCPD_CFGR1_TRANSWIN_SHIFT))
-#define STM32_UCPD_CFGR1_TRANSWIN_VAL(x)    ((x) << \
-					     STM32_UCPD_CFGR1_TRANSWIN_SHIFT)
-#define STM32_UCPD_CFGR1_PSC_CLK_SHIFT      17
-#define STM32_UCPD_CFGR1_PSC_CLK_MASK       ((0x7) << \
-					     STM32_UCPD_CFGR1_PSC_CLK_SHIFT)
-#define STM32_UCPD_CFGR1_PSC_CLK_VAL(x)     ((x) << \
-					     STM32_UCPD_CFGR1_PSC_CLK_SHIFT)
-#define STM32_UCPD_CFGR1_RXORDSETEN_SHIFT   20
-#define STM32_UCPD_CFGR1_RXORDSETEN_MASK    ((0x1ff) << \
-					     STM32_UCPD_CFGR1_RXORDSETEN_SHIFT)
-#define STM32_UCPD_CFGR1_RXORDSETEN_VAL(x)  ((x) << \
-					     STM32_UCPD_CFGR1_RXORDSETEN_SHIFT)
-#define STM32_UCPD_CFGR1_TXDMAEN            BIT(29)
-#define STM32_UCPD_CFGR1_RXDMAEN            BIT(30)
-#define STM32_UCPD_CFGR1_UCPDEN             BIT(31)
+#define STM32_UCPD_CFGR1_HBITCLKD_SHIFT 0
+#define STM32_UCPD_CFGR1_HBITCLKD_MASK \
+	((0x3f) << (STM32_UCPD_CFGR1_HBITCLKD_SHIFT))
+#define STM32_UCPD_CFGR1_HBITCLKD_VAL(x) \
+	((x) << STM32_UCPD_CFGR1_HBITCLKD_SHIFT)
+#define STM32_UCPD_CFGR1_IFRGAP_SHIFT 6
+#define STM32_UCPD_CFGR1_IFRGAP_MASK ((0x1f) << (STM32_UCPD_CFGR1_IFRGAP_SHIFT))
+#define STM32_UCPD_CFGR1_IFRGAP_VAL(x) ((x) << STM32_UCPD_CFGR1_IFRGAP_SHIFT)
+#define STM32_UCPD_CFGR1_TRANSWIN_SHIFT 11
+#define STM32_UCPD_CFGR1_TRANSWIN_MASK \
+	((0x1f) << (STM32_UCPD_CFGR1_TRANSWIN_SHIFT))
+#define STM32_UCPD_CFGR1_TRANSWIN_VAL(x) \
+	((x) << STM32_UCPD_CFGR1_TRANSWIN_SHIFT)
+#define STM32_UCPD_CFGR1_PSC_CLK_SHIFT 17
+#define STM32_UCPD_CFGR1_PSC_CLK_MASK ((0x7) << STM32_UCPD_CFGR1_PSC_CLK_SHIFT)
+#define STM32_UCPD_CFGR1_PSC_CLK_VAL(x) ((x) << STM32_UCPD_CFGR1_PSC_CLK_SHIFT)
+#define STM32_UCPD_CFGR1_RXORDSETEN_SHIFT 20
+#define STM32_UCPD_CFGR1_RXORDSETEN_MASK \
+	((0x1ff) << STM32_UCPD_CFGR1_RXORDSETEN_SHIFT)
+#define STM32_UCPD_CFGR1_RXORDSETEN_VAL(x) \
+	((x) << STM32_UCPD_CFGR1_RXORDSETEN_SHIFT)
+#define STM32_UCPD_CFGR1_TXDMAEN BIT(29)
+#define STM32_UCPD_CFGR1_RXDMAEN BIT(30)
+#define STM32_UCPD_CFGR1_UCPDEN BIT(31)
 
 /* --- UCPD CFGR2 Bit Definitions --- */
-#define STM32_UCPD_CFGR2_RXFILTDIS          BIT(0)
-#define STM32_UCPD_CFGR2_RXFILT2N3          BIT(1)
-#define STM32_UCPD_CFGR2_FORCECLK           BIT(2)
-#define STM32_UCPD_CFGR2_WUPEN              BIT(3)
+#define STM32_UCPD_CFGR2_RXFILTDIS BIT(0)
+#define STM32_UCPD_CFGR2_RXFILT2N3 BIT(1)
+#define STM32_UCPD_CFGR2_FORCECLK BIT(2)
+#define STM32_UCPD_CFGR2_WUPEN BIT(3)
 
 /* --- UCPD CR Bit Definitions --- */
-#define STM32_UCPD_CR_TXMODE_SHIFT          0
-#define STM32_UCPD_CR_TXMODE_MASK           ((0x3) << \
-					     (STM32_UCPD_CR_TXMODE_SHIFT))
-#define STM32_UCPD_CR_TXMODE_VAL(x)         ((x) << STM32_UCPD_CR_TXMODE_SHIFT)
-#define STM32_UCPD_CR_TXSEND                BIT(2)
-#define STM32_UCPD_CR_TXHRST                BIT(3)
-#define STM32_UCPD_CR_RXMODE                BIT(4)
-#define STM32_UCPD_CR_PHYRXEN               BIT(5)
-#define STM32_UCPD_CR_PHYCCSEL              BIT(6)
-#define STM32_UCPD_CR_ANASUBMODE_SHIFT      7
-#define STM32_UCPD_CR_ANASUBMODE_MASK       ((0x3) << \
-					     (STM32_UCPD_CR_ANASUBMODE_SHIFT))
-#define STM32_UCPD_CR_ANASUBMODE_VAL(x)     ((x) << \
-					     STM32_UCPD_CR_ANASUBMODE_SHIFT)
-#define STM32_UCPD_CR_ANAMODE               BIT(9)
-#define STM32_UCPD_CR_CCENABLE_SHIFT        10
-#define STM32_UCPD_CR_CCENABLE_MASK         ((0x3) << \
-					     (STM32_UCPD_CR_CCENABLE_SHIFT))
-#define STM32_UCPD_CR_CCENABLE_VAL(x)       ((x) << \
-					     STM32_UCPD_CR_CCENABLE_SHIFT)
-#define STM32_UCPD_CR_FRSRXEN               BIT(16)
-#define STM32_UCPD_CR_FRSTX                 BIT(17)
-#define STM32_UCPD_CR_RDCH                  BIT(18)
-#define STM32_UCPD_CR_CC1TCDIS              BIT(20)
-#define STM32_UCPD_CR_CC2TCDIS              BIT(21)
+#define STM32_UCPD_CR_TXMODE_SHIFT 0
+#define STM32_UCPD_CR_TXMODE_MASK ((0x3) << (STM32_UCPD_CR_TXMODE_SHIFT))
+#define STM32_UCPD_CR_TXMODE_VAL(x) ((x) << STM32_UCPD_CR_TXMODE_SHIFT)
+#define STM32_UCPD_CR_TXSEND BIT(2)
+#define STM32_UCPD_CR_TXHRST BIT(3)
+#define STM32_UCPD_CR_RXMODE BIT(4)
+#define STM32_UCPD_CR_PHYRXEN BIT(5)
+#define STM32_UCPD_CR_PHYCCSEL BIT(6)
+#define STM32_UCPD_CR_ANASUBMODE_SHIFT 7
+#define STM32_UCPD_CR_ANASUBMODE_MASK \
+	((0x3) << (STM32_UCPD_CR_ANASUBMODE_SHIFT))
+#define STM32_UCPD_CR_ANASUBMODE_VAL(x) ((x) << STM32_UCPD_CR_ANASUBMODE_SHIFT)
+#define STM32_UCPD_CR_ANAMODE BIT(9)
+#define STM32_UCPD_CR_CCENABLE_SHIFT 10
+#define STM32_UCPD_CR_CCENABLE_MASK ((0x3) << (STM32_UCPD_CR_CCENABLE_SHIFT))
+#define STM32_UCPD_CR_CCENABLE_VAL(x) ((x) << STM32_UCPD_CR_CCENABLE_SHIFT)
+#define STM32_UCPD_CR_FRSRXEN BIT(16)
+#define STM32_UCPD_CR_FRSTX BIT(17)
+#define STM32_UCPD_CR_RDCH BIT(18)
+#define STM32_UCPD_CR_CC1TCDIS BIT(20)
+#define STM32_UCPD_CR_CC2TCDIS BIT(21)
+
+/* TX mode message types */
+#define STM32_UCPD_CR_TXMODE_DEF 0
+#define STM32_UCPD_CR_TXMODE_CBL_RST 1
+#define STM32_UCPD_CR_TXMODE_BIST 2
 
 /* --- UCPD IMR Bit Definitions --- */
-#define STM32_UCPD_IMR_TXISIE               BIT(0)
-#define STM32_UCPD_IMR_TXMSGDISCIE          BIT(1)
-#define STM32_UCPD_IMR_TXMSGSENTIE          BIT(2)
-#define STM32_UCPD_IMR_TXMSGABTIE           BIT(3)
-#define STM32_UCPD_IMR_HRSTDISCIE           BIT(4)
-#define STM32_UCPD_IMR_HRSTSENTIE           BIT(5)
-#define STM32_UCPD_IMR_TXUNDIE              BIT(6)
-#define STM32_UCPD_IMR_RXNEIE               BIT(8)
-#define STM32_UCPD_IMR_RXORDDETIE           BIT(9)
-#define STM32_UCPD_IMR_RXHRSTDETIE          BIT(10)
-#define STM32_UCPD_IMR_RXOVRIE              BIT(11)
-#define STM32_UCPD_IMR_RXMSGENDIE           BIT(12)
-#define STM32_UCPD_IMR_TYPECEVT1IE          BIT(14)
-#define STM32_UCPD_IMR_TYPECEVT2IE          BIT(15)
-#define STM32_UCPD_IMR_FRSEVTIE             BIT(20)
+#define STM32_UCPD_IMR_TXISIE BIT(0)
+#define STM32_UCPD_IMR_TXMSGDISCIE BIT(1)
+#define STM32_UCPD_IMR_TXMSGSENTIE BIT(2)
+#define STM32_UCPD_IMR_TXMSGABTIE BIT(3)
+#define STM32_UCPD_IMR_HRSTDISCIE BIT(4)
+#define STM32_UCPD_IMR_HRSTSENTIE BIT(5)
+#define STM32_UCPD_IMR_TXUNDIE BIT(6)
+#define STM32_UCPD_IMR_RXNEIE BIT(8)
+#define STM32_UCPD_IMR_RXORDDETIE BIT(9)
+#define STM32_UCPD_IMR_RXHRSTDETIE BIT(10)
+#define STM32_UCPD_IMR_RXOVRIE BIT(11)
+#define STM32_UCPD_IMR_RXMSGENDIE BIT(12)
+#define STM32_UCPD_IMR_TYPECEVT1IE BIT(14)
+#define STM32_UCPD_IMR_TYPECEVT2IE BIT(15)
+#define STM32_UCPD_IMR_FRSEVTIE BIT(20)
 
 /* --- UCPD SR Bit Definitions --- */
-#define STM32_UCPD_SR_TXIS                  BIT(0)
-#define STM32_UCPD_SR_TXMSGDISC             BIT(1)
-#define STM32_UCPD_SR_TXMSGSENT             BIT(2)
-#define STM32_UCPD_SR_TXMSGABT              BIT(3)
-#define STM32_UCPD_SR_HRSTDISC              BIT(4)
-#define STM32_UCPD_SR_HRSTSENT              BIT(5)
-#define STM32_UCPD_SR_TXUND                 BIT(6)
-#define STM32_UCPD_SR_RXNE                  BIT(8)
-#define STM32_UCPD_SR_RXORDDET              BIT(9)
-#define STM32_UCPD_SR_RXHRSTDET             BIT(10)
-#define STM32_UCPD_SR_RXOVR                 BIT(11)
-#define STM32_UCPD_SR_RXMSGEND              BIT(12)
-#define STM32_UCPD_SR_RXERR                 BIT(13)
-#define STM32_UCPD_SR_TYPECEVT1             BIT(14)
-#define STM32_UCPD_SR_TYPECEVT2             BIT(15)
-#define STM32_UCPD_SR_VSTATE_CC1_SHIFT      16
-#define STM32_UCPD_SR_VSTATE_CC1_MASK       ((0x3) << \
-					       (STM32_UCPD_SR_VSTATE_CC1_SHIFT))
-#define STM32_UCPD_SR_VSTATE_CC1_VAL(x)     ((x) << \
-					     STM32_UCPD_SR_VSTATE_CC1_SHIFT)
-#define STM32_UCPD_SR_VSTATE_CC2_SHIFT      18
-#define STM32_UCPD_SR_VSTATE_CC2_MASK       ((0x3) << \
-					     (STM32_UCPD_SR_VSTATE_CC2_SHIFT))
-#define STM32_UCPD_SR_VSTATE_CC2_VAL(x)     ((x) << \
-					     STM32_UCPD_SR_VSTATE_CC2_SHIFT)
-#define STM32_UCPD_SR_FRSEVT                BIT(20)
-
-#define STM32_UCPD_SR_VSTATE_OPEN           3
-#define STM32_UCPD_SR_VSTATE_RA             0
+#define STM32_UCPD_SR_TXIS BIT(0)
+#define STM32_UCPD_SR_TXMSGDISC BIT(1)
+#define STM32_UCPD_SR_TXMSGSENT BIT(2)
+#define STM32_UCPD_SR_TXMSGABT BIT(3)
+#define STM32_UCPD_SR_HRSTDISC BIT(4)
+#define STM32_UCPD_SR_HRSTSENT BIT(5)
+#define STM32_UCPD_SR_TXUND BIT(6)
+#define STM32_UCPD_SR_RXNE BIT(8)
+#define STM32_UCPD_SR_RXORDDET BIT(9)
+#define STM32_UCPD_SR_RXHRSTDET BIT(10)
+#define STM32_UCPD_SR_RXOVR BIT(11)
+#define STM32_UCPD_SR_RXMSGEND BIT(12)
+#define STM32_UCPD_SR_RXERR BIT(13)
+#define STM32_UCPD_SR_TYPECEVT1 BIT(14)
+#define STM32_UCPD_SR_TYPECEVT2 BIT(15)
+#define STM32_UCPD_SR_VSTATE_CC1_SHIFT 16
+#define STM32_UCPD_SR_VSTATE_CC1_MASK \
+	((0x3) << (STM32_UCPD_SR_VSTATE_CC1_SHIFT))
+#define STM32_UCPD_SR_VSTATE_CC1_VAL(x) ((x) << STM32_UCPD_SR_VSTATE_CC1_SHIFT)
+#define STM32_UCPD_SR_VSTATE_CC2_SHIFT 18
+#define STM32_UCPD_SR_VSTATE_CC2_MASK \
+	((0x3) << (STM32_UCPD_SR_VSTATE_CC2_SHIFT))
+#define STM32_UCPD_SR_VSTATE_CC2_VAL(x) ((x) << STM32_UCPD_SR_VSTATE_CC2_SHIFT)
+#define STM32_UCPD_SR_FRSEVT BIT(20)
+
+#define STM32_UCPD_SR_VSTATE_OPEN 3
+#define STM32_UCPD_SR_VSTATE_RA 0
 
 /* --- UCPD ICR Bit Definitions --- */
-#define STM32_UCPD_ICR_TXMSGDISCCF          BIT(1)
-#define STM32_UCPD_ICR_TXMSGSENTCF          BIT(2)
-#define STM32_UCPD_ICR_TXMSGABTCF           BIT(3)
-#define STM32_UCPD_ICR_HRSTDISCCF           BIT(4)
-#define STM32_UCPD_ICR_HRSTSENTCF           BIT(5)
-#define STM32_UCPD_ICR_TXUNDCF              BIT(6)
-#define STM32_UCPD_ICR_RXORDDETCF           BIT(9)
-#define STM32_UCPD_ICR_RXHRSTDETCF          BIT(10)
-#define STM32_UCPD_ICR_RXOVRCF              BIT(11)
-#define STM32_UCPD_ICR_RXMSGENDCF           BIT(12)
-#define STM32_UCPD_ICR_TYPECEVT1CF          BIT(14)
-#define STM32_UCPD_ICR_TYPECEVT2CF          BIT(15)
-#define STM32_UCPD_ICR_FRSEVTCF             BIT(20)
-
+#define STM32_UCPD_ICR_TXMSGDISCCF BIT(1)
+#define STM32_UCPD_ICR_TXMSGSENTCF BIT(2)
+#define STM32_UCPD_ICR_TXMSGABTCF BIT(3)
+#define STM32_UCPD_ICR_HRSTDISCCF BIT(4)
+#define STM32_UCPD_ICR_HRSTSENTCF BIT(5)
+#define STM32_UCPD_ICR_TXUNDCF BIT(6)
+#define STM32_UCPD_ICR_RXORDDETCF BIT(9)
+#define STM32_UCPD_ICR_RXHRSTDETCF BIT(10)
+#define STM32_UCPD_ICR_RXOVRCF BIT(11)
+#define STM32_UCPD_ICR_RXMSGENDCF BIT(12)
+#define STM32_UCPD_ICR_TYPECEVT1CF BIT(14)
+#define STM32_UCPD_ICR_TYPECEVT2CF BIT(15)
+#define STM32_UCPD_ICR_FRSEVTCF BIT(20)
 
 /* --- UCPD TX_ORDSETR Bit Definitions --- */
-#define STM32_UCPD_TX_ORDSETR_SHIFT        0
-#define STM32_UCPD_TX_ORDSETR_MASK         ((0xfffff) << \
-					    (STM32_UCPD_TX_ORDSETR_SHIFT))
-#define STM32_UCPD_TX_ORDSETR_VAL(x)       ((x) << STM32_UCPD_TX_ORDSETR_SHIFT)
+#define STM32_UCPD_TX_ORDSETR_SHIFT 0
+#define STM32_UCPD_TX_ORDSETR_MASK ((0xfffff) << (STM32_UCPD_TX_ORDSETR_SHIFT))
+#define STM32_UCPD_TX_ORDSETR_VAL(x) ((x) << STM32_UCPD_TX_ORDSETR_SHIFT)
 
 /* --- UCPD TX_PAYSZR Bit Definitions --- */
-#define STM32_UCPD_TX_PAYSZR_SHIFT        0
-#define STM32_UCPD_TX_PAYSZR_MASK         ((0x3ff) << \
-					   (STM32_UCPD_TX_PAYSZR_SHIFT))
-#define STM32_UCPD_TX_PAYSZR_VAL(x)       ((x) << STM32_UCPD_TX_PAYSZR_SHIFT)
+#define STM32_UCPD_TX_PAYSZR_SHIFT 0
+#define STM32_UCPD_TX_PAYSZR_MASK ((0x3ff) << (STM32_UCPD_TX_PAYSZR_SHIFT))
+#define STM32_UCPD_TX_PAYSZR_VAL(x) ((x) << STM32_UCPD_TX_PAYSZR_SHIFT)
 
 /* --- UCPD TXDR Bit Definitions --- */
-#define STM32_UCPD_TXDR_SHIFT             0
-#define STM32_UCPD_TXDR_MASK              ((0xff) << \
-					   (STM32_UCPD_TXDR_SHIFT))
-#define STM32_UCPD_TXDR_VAL(x)            ((x) << STM32_UCPD_TXDR_SHIFT)
+#define STM32_UCPD_TXDR_SHIFT 0
+#define STM32_UCPD_TXDR_MASK ((0xff) << (STM32_UCPD_TXDR_SHIFT))
+#define STM32_UCPD_TXDR_VAL(x) ((x) << STM32_UCPD_TXDR_SHIFT)
 
 /* --- UCPD RX_ORDSETR Bit Definitions --- */
-#define STM32_UCPD_RXORDSETR_SHIFT        0
-#define STM32_UCPD_RXORDSETR_MASK         ((0x7) << \
-					   (STM32_UCPD_RXORDSETR_SHIFT))
-#define STM32_UCPD_RXORDSETR_VAL(x)       ((x) << STM32_UCPD_RXORDSETR_SHIFT)
-#define STM32_UCPD_RXSOP3OF4              BIT(3)
-#define STM32_UCPD_RXSOPKINVALID_SHIFT    4
-#define STM32_UCPD_RXSOPKINVALID_MASK     ((0x7) << \
-					   (STM32_UCPD_RXSOPKINVALID_SHIFT))
-#define STM32_UCPD_RXSOPKINVALID_VAL(x)   ((x) << \
-					   STM32_UCPD_RXSOPKINVALID_SHIFT)
+#define STM32_UCPD_RXORDSETR_SHIFT 0
+#define STM32_UCPD_RXORDSETR_MASK ((0x7) << (STM32_UCPD_RXORDSETR_SHIFT))
+#define STM32_UCPD_RXORDSETR_VAL(x) ((x) << STM32_UCPD_RXORDSETR_SHIFT)
+#define STM32_UCPD_RXSOP3OF4 BIT(3)
+#define STM32_UCPD_RXSOPKINVALID_SHIFT 4
+#define STM32_UCPD_RXSOPKINVALID_MASK \
+	((0x7) << (STM32_UCPD_RXSOPKINVALID_SHIFT))
+#define STM32_UCPD_RXSOPKINVALID_VAL(x) ((x) << STM32_UCPD_RXSOPKINVALID_SHIFT)
 
 /* --- UCPD RX_PAYSZR Bit Definitions --- */
-#define STM32_UCPD_RX_PAYSZR_SHIFT        0
-#define STM32_UCPD_RX_PAYSZR_MASK         ((0x3ff) << \
-					   (STM32_UCPD_RX_PAYSZR_SHIFT))
-#define STM32_UCPD_RX_PAYSZR_VAL(x)       ((x) << STM32_UCPD_RX_PAYSZR_SHIFT)
+#define STM32_UCPD_RX_PAYSZR_SHIFT 0
+#define STM32_UCPD_RX_PAYSZR_MASK ((0x3ff) << (STM32_UCPD_RX_PAYSZR_SHIFT))
+#define STM32_UCPD_RX_PAYSZR_VAL(x) ((x) << STM32_UCPD_RX_PAYSZR_SHIFT)
 
 /* --- UCPD TXDR Bit Definitions --- */
-#define STM32_UCPD_RXDR_SHIFT             0
-#define STM32_UCPD_RXDR_MASK              ((0xff) << \
-					   (STM32_UCPD_RXDR_SHIFT))
-#define STM32_UCPD_RXDR_VAL(x)            ((x) << STM32_UCPD_RXDR_SHIFT)
-
+#define STM32_UCPD_RXDR_SHIFT 0
+#define STM32_UCPD_RXDR_MASK ((0xff) << (STM32_UCPD_RXDR_SHIFT))
+#define STM32_UCPD_RXDR_VAL(x) ((x) << STM32_UCPD_RXDR_SHIFT)
 
 /* --- USART --- */
-#define STM32_USART_CR1(base)      STM32_USART_REG(base, 0x00)
-#define STM32_USART_CR2(base)      STM32_USART_REG(base, 0x04)
-#define STM32_USART_CR3(base)      STM32_USART_REG(base, 0x08)
-#define STM32_USART_BRR(base)      STM32_USART_REG(base, 0x0C)
-#define STM32_USART_GTPR(base)     STM32_USART_REG(base, 0x10)
-#define STM32_USART_SR(base)       STM32_USART_REG(base, 0x1C)
-#define STM32_USART_RDR(base)      STM32_USART_REG(base, 0x24)
-#define STM32_USART_TDR(base)      STM32_USART_REG(base, 0x28)
+#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00)
+#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04)
+#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08)
+#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C)
+#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10)
+#define STM32_USART_SR(base) STM32_USART_REG(base, 0x1C)
+#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24)
+#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28)
 
 /* --- USART bit definitions -- */
-#define STM32_USART_SR_ORE		BIT(3)
-#define STM32_USART_SR_RXNE		BIT(5)
-#define STM32_USART_SR_TC		BIT(6)
-#define STM32_USART_SR_TXE		BIT(7)
-
-#define STM32_USART_CR1_UE		BIT(0)
-#define STM32_USART_CR1_RE		BIT(2)
-#define STM32_USART_CR1_TE		BIT(3)
-#define STM32_USART_CR1_RXNEIE		BIT(5)
-#define STM32_USART_CR1_TCIE		BIT(6)
-#define STM32_USART_CR1_TXEIE		BIT(7)
-#define STM32_USART_CR1_PS		BIT(9)
-#define STM32_USART_CR1_PCE		BIT(10)
-#define STM32_USART_CR1_M		BIT(12)
-#define STM32_USART_CR1_OVER8		BIT(15)
-
-#define STM32_USART_CR3_EIE		BIT(0)
-#define STM32_USART_CR3_DMAR		BIT(6)
-#define STM32_USART_CR3_DMAT		BIT(7)
-#define STM32_USART_CR3_ONEBIT		BIT(11)
-
+#define STM32_USART_SR_ORE BIT(3)
+#define STM32_USART_SR_RXNE BIT(5)
+#define STM32_USART_SR_TC BIT(6)
+#define STM32_USART_SR_TXE BIT(7)
+
+#define STM32_USART_CR1_UE BIT(0)
+#define STM32_USART_CR1_RE BIT(2)
+#define STM32_USART_CR1_TE BIT(3)
+#define STM32_USART_CR1_RXNEIE BIT(5)
+#define STM32_USART_CR1_TCIE BIT(6)
+#define STM32_USART_CR1_TXEIE BIT(7)
+#define STM32_USART_CR1_PS BIT(9)
+#define STM32_USART_CR1_PCE BIT(10)
+#define STM32_USART_CR1_M BIT(12)
+#define STM32_USART_CR1_OVER8 BIT(15)
+
+#define STM32_USART_CR3_EIE BIT(0)
+#define STM32_USART_CR3_DMAR BIT(6)
+#define STM32_USART_CR3_DMAT BIT(7)
+#define STM32_USART_CR3_ONEBIT BIT(11)
 
 /* --- GPIO --- */
-#define STM32_GPIO_MODER(b)     REG32((b) + 0x00)
-#define STM32_GPIO_OTYPER(b)    REG16((b) + 0x04)
-#define STM32_GPIO_OSPEEDR(b)   REG32((b) + 0x08)
-#define STM32_GPIO_PUPDR(b)     REG32((b) + 0x0C)
-#define STM32_GPIO_IDR(b)       REG16((b) + 0x10)
-#define STM32_GPIO_ODR(b)       REG16((b) + 0x14)
-#define STM32_GPIO_BSRR(b)      REG32((b) + 0x18)
-#define STM32_GPIO_LCKR(b)      REG32((b) + 0x1C)
-#define STM32_GPIO_AFRL(b)      REG32((b) + 0x20)
-#define STM32_GPIO_AFRH(b)      REG32((b) + 0x24)
-
-#define GPIO_ALT_SYS                 0x0
-#define GPIO_ALT_TIM2                0x1
-#define GPIO_ALT_I2C3                0x2
-#define GPIO_ALT_TIM9_11             0x3
-#define GPIO_ALT_I2C                 0x4
-#define GPIO_ALT_SPI                 0x5
-#define GPIO_ALT_SPI3                0x6
-#define GPIO_ALT_USART               0x7
-#define GPIO_ALT_I2C_23              0x9
-#define GPIO_ALT_USB                 0xA
-#define GPIO_ALT_LCD                 0xB
-#define GPIO_ALT_LPUART              0xC
-#define GPIO_ALT_SAI1                0xD
-#define GPIO_ALT_RI                  0xE
-#define GPIO_ALT_EVENTOUT            0xF
+#define STM32_GPIO_MODER(b) REG32((b) + 0x00)
+#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04)
+#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08)
+#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C)
+#define STM32_GPIO_IDR(b) REG16((b) + 0x10)
+#define STM32_GPIO_ODR(b) REG16((b) + 0x14)
+#define STM32_GPIO_BSRR(b) REG32((b) + 0x18)
+#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C)
+#define STM32_GPIO_AFRL(b) REG32((b) + 0x20)
+#define STM32_GPIO_AFRH(b) REG32((b) + 0x24)
+
+#define GPIO_ALT_SYS 0x0
+#define GPIO_ALT_TIM2 0x1
+#define GPIO_ALT_I2C3 0x2
+#define GPIO_ALT_TIM9_11 0x3
+#define GPIO_ALT_I2C 0x4
+#define GPIO_ALT_SPI 0x5
+#define GPIO_ALT_SPI3 0x6
+#define GPIO_ALT_USART 0x7
+#define GPIO_ALT_I2C_23 0x9
+#define GPIO_ALT_USB 0xA
+#define GPIO_ALT_LCD 0xB
+#define GPIO_ALT_LPUART 0xC
+#define GPIO_ALT_SAI1 0xD
+#define GPIO_ALT_RI 0xE
+#define GPIO_ALT_EVENTOUT 0xF
 
 /* --- I2C --- */
 #define stm32g4_i2c_reg(base, offset) ((uint16_t *)((base) + (offset)))
 
-#define STM32_I2C_CR1(base)            REG32(stm32g4_i2c_reg(base, 0x00))
-#define STM32_I2C_CR2(base)            REG32(stm32g4_i2c_reg(base, 0x04))
-#define STM32_I2C_OAR1(base)           REG16(stm32g4_i2c_reg(base, 0x08))
-#define STM32_I2C_OAR2(base)           REG16(stm32g4_i2c_reg(base, 0x0C))
-#define STM32_I2C_TIMINGR(base)        REG32(stm32g4_i2c_reg(base, 0x10))
-#define STM32_I2C_TIMEOUTR(base)       REG32(stm32g4_i2c_reg(base, 0x14))
-#define STM32_I2C_ISR(base)            REG32(stm32g4_i2c_reg(base, 0x18))
-#define STM32_I2C_ICR(base)            REG32(stm32g4_i2c_reg(base, 0x1C))
-#define STM32_I2C_PECR(base)           REG32(stm32g4_i2c_reg(base, 0x20))
-#define STM32_I2C_RXDR(base)           REG32(stm32g4_i2c_reg(base, 0x24))
-#define STM32_I2C_TXDR(base)           REG32(stm32g4_i2c_reg(base, 0x28))
+#define STM32_I2C_CR1(base) REG32(stm32g4_i2c_reg(base, 0x00))
+#define STM32_I2C_CR2(base) REG32(stm32g4_i2c_reg(base, 0x04))
+#define STM32_I2C_OAR1(base) REG16(stm32g4_i2c_reg(base, 0x08))
+#define STM32_I2C_OAR2(base) REG16(stm32g4_i2c_reg(base, 0x0C))
+#define STM32_I2C_TIMINGR(base) REG32(stm32g4_i2c_reg(base, 0x10))
+#define STM32_I2C_TIMEOUTR(base) REG32(stm32g4_i2c_reg(base, 0x14))
+#define STM32_I2C_ISR(base) REG32(stm32g4_i2c_reg(base, 0x18))
+#define STM32_I2C_ICR(base) REG32(stm32g4_i2c_reg(base, 0x1C))
+#define STM32_I2C_PECR(base) REG32(stm32g4_i2c_reg(base, 0x20))
+#define STM32_I2C_RXDR(base) REG32(stm32g4_i2c_reg(base, 0x24))
+#define STM32_I2C_TXDR(base) REG32(stm32g4_i2c_reg(base, 0x28))
 
 /* --- I2C CR1 Bit Definitions --- */
-#define STM32_I2C_CR1_PE            BIT(0)
-#define STM32_I2C_CR1_TXIE          BIT(1)
-#define STM32_I2C_CR1_RXIE          BIT(2)
-#define STM32_I2C_CR1_ADDRIE        BIT(3)
-#define STM32_I2C_CR1_NACKIE        BIT(4)
-#define STM32_I2C_CR1_STOPIE        BIT(5)
-#define STM32_I2C_CR1_ERRIE         BIT(7)
-#define STM32_I2C_CR1_WUPEN         BIT(18)
+#define STM32_I2C_CR1_PE BIT(0)
+#define STM32_I2C_CR1_TXIE BIT(1)
+#define STM32_I2C_CR1_RXIE BIT(2)
+#define STM32_I2C_CR1_ADDRIE BIT(3)
+#define STM32_I2C_CR1_NACKIE BIT(4)
+#define STM32_I2C_CR1_STOPIE BIT(5)
+#define STM32_I2C_CR1_ERRIE BIT(7)
+#define STM32_I2C_CR1_WUPEN BIT(18)
 
 /* --- I2C CR2 Bit Definitions --- */
-#define STM32_I2C_CR2_RD_WRN        BIT(10)
-#define STM32_I2C_CR2_START         BIT(13)
-#define STM32_I2C_CR2_STOP          BIT(14)
-#define STM32_I2C_CR2_NACK          BIT(15)
-#define STM32_I2C_CR2_RELOAD        BIT(24)
-#define STM32_I2C_CR2_AUTOEND       BIT(25)
+#define STM32_I2C_CR2_RD_WRN BIT(10)
+#define STM32_I2C_CR2_START BIT(13)
+#define STM32_I2C_CR2_STOP BIT(14)
+#define STM32_I2C_CR2_NACK BIT(15)
+#define STM32_I2C_CR2_RELOAD BIT(24)
+#define STM32_I2C_CR2_AUTOEND BIT(25)
 
 /* --- I2C ISR Bit Definitions --- */
-#define STM32_I2C_ISR_TXE           BIT(0)
-#define STM32_I2C_ISR_TXIS          BIT(1)
-#define STM32_I2C_ISR_RXNE          BIT(2)
-#define STM32_I2C_ISR_ADDR          BIT(3)
-#define STM32_I2C_ISR_NACK          BIT(4)
-#define STM32_I2C_ISR_STOP          BIT(5)
-#define STM32_I2C_ISR_TC            BIT(6)
-#define STM32_I2C_ISR_TCR           BIT(7)
-#define STM32_I2C_ISR_BERR          BIT(8)
-#define STM32_I2C_ISR_ARLO          BIT(9)
-#define STM32_I2C_ISR_OVR           BIT(10)
-#define STM32_I2C_ISR_PECERR        BIT(11)
-#define STM32_I2C_ISR_TIMEOUT       BIT(12)
-#define STM32_I2C_ISR_ALERT         BIT(13)
-#define STM32_I2C_ISR_BUSY          BIT(15)
-#define STM32_I2C_ISR_DIR           BIT(16)
+#define STM32_I2C_ISR_TXE BIT(0)
+#define STM32_I2C_ISR_TXIS BIT(1)
+#define STM32_I2C_ISR_RXNE BIT(2)
+#define STM32_I2C_ISR_ADDR BIT(3)
+#define STM32_I2C_ISR_NACK BIT(4)
+#define STM32_I2C_ISR_STOP BIT(5)
+#define STM32_I2C_ISR_TC BIT(6)
+#define STM32_I2C_ISR_TCR BIT(7)
+#define STM32_I2C_ISR_BERR BIT(8)
+#define STM32_I2C_ISR_ARLO BIT(9)
+#define STM32_I2C_ISR_OVR BIT(10)
+#define STM32_I2C_ISR_PECERR BIT(11)
+#define STM32_I2C_ISR_TIMEOUT BIT(12)
+#define STM32_I2C_ISR_ALERT BIT(13)
+#define STM32_I2C_ISR_BUSY BIT(15)
+#define STM32_I2C_ISR_DIR BIT(16)
 
 /* --- I2C ICR Bit Definitions --- */
-#define STM32_I2C_ICR_ADDRCF        BIT(3)
-#define STM32_I2C_ICR_NACKCF        BIT(4)
-#define STM32_I2C_ICR_STOPCF        BIT(5)
-#define STM32_I2C_ICR_BERRCF        BIT(8)
-#define STM32_I2C_ICR_ARLOCF        BIT(9)
-#define STM32_I2C_ICR_OVRCF         BIT(10)
-#define STM32_I2C_ICR_TIMEOUTCF     BIT(12)
-#define STM32_I2C_ICR_ALL           0x3F38
+#define STM32_I2C_ICR_ADDRCF BIT(3)
+#define STM32_I2C_ICR_NACKCF BIT(4)
+#define STM32_I2C_ICR_STOPCF BIT(5)
+#define STM32_I2C_ICR_BERRCF BIT(8)
+#define STM32_I2C_ICR_ARLOCF BIT(9)
+#define STM32_I2C_ICR_OVRCF BIT(10)
+#define STM32_I2C_ICR_TIMEOUTCF BIT(12)
+#define STM32_I2C_ICR_ALL 0x3F38
 
 /* --- I2C TIMINGR bit Definitions --- */
 #define STM32_I2C_TIMINGR_SCLL_OFF 0
@@ -572,269 +559,271 @@
 
 /* --- Power / Reset / Clocks --- */
 
-#define STM32_RCC_CR                    REG32(STM32_RCC_BASE + 0x00)
-#define STM32_RCC_ICSCR                 REG32(STM32_RCC_BASE + 0x04)
-#define STM32_RCC_CFGR                  REG32(STM32_RCC_BASE + 0x08)
-#define STM32_RCC_PLLCFGR               REG32(STM32_RCC_BASE + 0x0C)
-#define STM32_RCC_CIER                  REG32(STM32_RCC_BASE + 0x18)
-#define STM32_RCC_CIFR                  REG32(STM32_RCC_BASE + 0x1C)
-#define STM32_RCC_CICR                  REG32(STM32_RCC_BASE + 0x20)
-#define STM32_RCC_AHB1RSTR              REG32(STM32_RCC_BASE + 0x28)
-#define STM32_RCC_AHB2RSTR              REG32(STM32_RCC_BASE + 0x2C)
-#define STM32_RCC_AHB3RSTR              REG32(STM32_RCC_BASE + 0x30)
-#define STM32_RCC_APB1RSTR              REG32(STM32_RCC_BASE + 0x38)
-#define STM32_RCC_APB2RSTR              REG32(STM32_RCC_BASE + 0x40)
-#define STM32_RCC_AHB1ENR               REG32(STM32_RCC_BASE + 0x48)
-#define STM32_RCC_AHB2ENR               REG32(STM32_RCC_BASE + 0x4C)
-#define STM32_RCC_AHB3ENR               REG32(STM32_RCC_BASE + 0x50)
-#define STM32_RCC_APB1ENR1              REG32(STM32_RCC_BASE + 0x58)
-#define STM32_RCC_APB1ENR2              REG32(STM32_RCC_BASE + 0x5C)
-#define STM32_RCC_APB2ENR               REG32(STM32_RCC_BASE + 0x60)
-#define STM32_RCC_AHB1SMENR             REG32(STM32_RCC_BASE + 0x68)
-#define STM32_RCC_AHB2SMENR             REG32(STM32_RCC_BASE + 0x6C)
-#define STM32_RCC_AHB3SMENR             REG32(STM32_RCC_BASE + 0x70)
-#define STM32_RCC_APB1SMENR1            REG32(STM32_RCC_BASE + 0x78)
-#define STM32_RCC_APB1SMENR2            REG32(STM32_RCC_BASE + 0x7C)
-#define STM32_RCC_APB2SMENR             REG32(STM32_RCC_BASE + 0x80)
-#define STM32_RCC_CCIPR                 REG32(STM32_RCC_BASE + 0x88)
-#define STM32_RCC_BDCR                  REG32(STM32_RCC_BASE + 0x90)
-#define STM32_RCC_CSR                   REG32(STM32_RCC_BASE + 0x94)
-#define STM32_RCC_CRRCR                 REG32(STM32_RCC_BASE + 0x98)
-#define STM32_RCC_CCIPR2                REG32(STM32_RCC_BASE + 0x9C)
+#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00)
+#define STM32_RCC_ICSCR REG32(STM32_RCC_BASE + 0x04)
+#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08)
+#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x0C)
+#define STM32_RCC_CIER REG32(STM32_RCC_BASE + 0x18)
+#define STM32_RCC_CIFR REG32(STM32_RCC_BASE + 0x1C)
+#define STM32_RCC_CICR REG32(STM32_RCC_BASE + 0x20)
+#define STM32_RCC_AHB1RSTR REG32(STM32_RCC_BASE + 0x28)
+#define STM32_RCC_AHB2RSTR REG32(STM32_RCC_BASE + 0x2C)
+#define STM32_RCC_AHB3RSTR REG32(STM32_RCC_BASE + 0x30)
+#define STM32_RCC_APB1RSTR1 REG32(STM32_RCC_BASE + 0x38)
+#define STM32_RCC_APB1RSTR2 REG32(STM32_RCC_BASE + 0x3C)
+#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x40)
+#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x48)
+#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x4C)
+#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x50)
+#define STM32_RCC_APB1ENR1 REG32(STM32_RCC_BASE + 0x58)
+#define STM32_RCC_APB1ENR2 REG32(STM32_RCC_BASE + 0x5C)
+#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x60)
+#define STM32_RCC_AHB1SMENR REG32(STM32_RCC_BASE + 0x68)
+#define STM32_RCC_AHB2SMENR REG32(STM32_RCC_BASE + 0x6C)
+#define STM32_RCC_AHB3SMENR REG32(STM32_RCC_BASE + 0x70)
+#define STM32_RCC_APB1SMENR1 REG32(STM32_RCC_BASE + 0x78)
+#define STM32_RCC_APB1SMENR2 REG32(STM32_RCC_BASE + 0x7C)
+#define STM32_RCC_APB2SMENR REG32(STM32_RCC_BASE + 0x80)
+#define STM32_RCC_CCIPR REG32(STM32_RCC_BASE + 0x88)
+#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x90)
+#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x94)
+#define STM32_RCC_CRRCR REG32(STM32_RCC_BASE + 0x98)
+#define STM32_RCC_CCIPR2 REG32(STM32_RCC_BASE + 0x9C)
 
 #define STM32_RCC_APB1ENR STM32_RCC_APB1ENR1
 #define STM32_RCC_AHBENR STM32_RCC_APB1ENR
 
 /* --- RCC CR Bit Definitions --- */
-#define STM32_RCC_CR_HSION		BIT(8)
-#define STM32_RCC_CR_HSIRDY		BIT(10)
-#define STM32_RCC_CR_HSEON		BIT(16)
-#define STM32_RCC_CR_HSERDY		BIT(17)
-#define STM32_RCC_CR_PLLON		BIT(24)
-#define STM32_RCC_CR_PLLRDY		BIT(25)
+#define STM32_RCC_CR_HSION BIT(8)
+#define STM32_RCC_CR_HSIRDY BIT(10)
+#define STM32_RCC_CR_HSEON BIT(16)
+#define STM32_RCC_CR_HSERDY BIT(17)
+#define STM32_RCC_CR_PLLON BIT(24)
+#define STM32_RCC_CR_PLLRDY BIT(25)
 
 /* --- RCC PLLCFGR Bit Definitions --- */
-#define  PLLCFGR_PLLSRC_OFF		0
-#define  PLLCFGR_PLLSRC(val)		(((val) & 0x3) << PLLCFGR_PLLSRC_OFF)
-#define  PLLCFGR_PLLSRC_HSI		2
-#define  PLLCFGR_PLLSRC_HSE		3
+#define PLLCFGR_PLLSRC_OFF 0
+#define PLLCFGR_PLLSRC(val) (((val)&0x3) << PLLCFGR_PLLSRC_OFF)
+#define PLLCFGR_PLLSRC_HSI 2
+#define PLLCFGR_PLLSRC_HSE 3
 /* PLL Division factor */
-#define  PLLCFGR_PLLM_OFF		4
-#define  PLLCFGR_PLLM(val)		(((val) & 0x1f) << PLLCFGR_PLLM_OFF)
+#define PLLCFGR_PLLM_OFF 4
+#define PLLCFGR_PLLM(val) (((val)&0x1f) << PLLCFGR_PLLM_OFF)
 /* PLL Multiplication factor */
-#define  PLLCFGR_PLLN_OFF		8
-#define  PLLCFGR_PLLN(val)		(((val) & 0x7f) << PLLCFGR_PLLN_OFF)
-#define  PLLCFGR_PLLQ_EN		BIT(20)
-#define  PLLCFGR_PLLQ_OFF		21
-#define  PLLCFGR_PLLQ(val)		(((val) & 0x3) << PLLCFGR_PLLQ_OFF)
+#define PLLCFGR_PLLN_OFF 8
+#define PLLCFGR_PLLN(val) (((val)&0x7f) << PLLCFGR_PLLN_OFF)
+#define PLLCFGR_PLLQ_EN BIT(20)
+#define PLLCFGR_PLLQ_OFF 21
+#define PLLCFGR_PLLQ(val) (((val)&0x3) << PLLCFGR_PLLQ_OFF)
 /* System and main CPU clock */
-#define  PLLCFGR_PLLR_EN		BIT(24)
-#define  PLLCFGR_PLLR_OFF		25
-#define  PLLCFGR_PLLR(val)		(((val) & 0x3) << PLLCFGR_PLLR_OFF)
-#define  PLLCFGR_PLLP_OFF		27
-#define  PLLCFGR_PLLP(val)		(((val) & 0x1f) << PLLCFGR_PLLP_OFF)
+#define PLLCFGR_PLLR_EN BIT(24)
+#define PLLCFGR_PLLR_OFF 25
+#define PLLCFGR_PLLR(val) (((val)&0x3) << PLLCFGR_PLLR_OFF)
+#define PLLCFGR_PLLP_OFF 27
+#define PLLCFGR_PLLP(val) (((val)&0x1f) << PLLCFGR_PLLP_OFF)
 
 /* --- RCC CFGR Bit Definitions --- */
-#define STM32_RCC_CFGR_SW_HSI		(1 << 0)
-#define STM32_RCC_CFGR_SW_HSE		(2 << 0)
-#define STM32_RCC_CFGR_SW_PLL		(3 << 0)
-#define STM32_RCC_CFGR_SW_MASK		(3 << 0)
-#define STM32_RCC_CFGR_SWS_HSI		(1 << 2)
-#define STM32_RCC_CFGR_SWS_HSE		(2 << 2)
-#define STM32_RCC_CFGR_SWS_PLL		(3 << 2)
-#define STM32_RCC_CFGR_SWS_MASK		(3 << 2)
+#define STM32_RCC_CFGR_SW_HSI (1 << 0)
+#define STM32_RCC_CFGR_SW_HSE (2 << 0)
+#define STM32_RCC_CFGR_SW_PLL (3 << 0)
+#define STM32_RCC_CFGR_SW_MASK (3 << 0)
+#define STM32_RCC_CFGR_SWS_HSI (1 << 2)
+#define STM32_RCC_CFGR_SWS_HSE (2 << 2)
+#define STM32_RCC_CFGR_SWS_PLL (3 << 2)
+#define STM32_RCC_CFGR_SWS_MASK (3 << 2)
 /* AHB Prescalar: */
-#define  CFGR_HPRE_OFF			4
-#define  CFGR_HPRE(val)			(((val) & 0xf) << CFGR_HPRE_OFF)
+#define CFGR_HPRE_OFF 4
+#define CFGR_HPRE(val) (((val)&0xf) << CFGR_HPRE_OFF)
 /* APB1 Low Speed Prescalar < 45MHz */
-#define  CFGR_PPRE1_OFF			8
-#define  CFGR_PPRE1(val)		(((val) & 0x7) << CFGR_PPRE1_OFF)
+#define CFGR_PPRE1_OFF 8
+#define CFGR_PPRE1(val) (((val)&0x7) << CFGR_PPRE1_OFF)
 /* APB2 High Speed Prescalar < 90MHz */
-#define  CFGR_PPRE2_OFF			11
-#define  CFGR_PPRE2(val)		(((val) & 0x7) << CFGR_PPRE2_OFF)
+#define CFGR_PPRE2_OFF 11
+#define CFGR_PPRE2(val) (((val)&0x7) << CFGR_PPRE2_OFF)
 /* RTC CLock: Must equal 1MHz */
-#define  CFGR_RTCPRE_OFF		16
-#define  CFGR_RTCPRE(val)		(((val) & 0x1f) << CFGR_RTCPRE_OFF)
+#define CFGR_RTCPRE_OFF 16
+#define CFGR_RTCPRE(val) (((val)&0x1f) << CFGR_RTCPRE_OFF)
 
 /* --- RCC AHB1ENR Bit Definitions --- */
-#define STM32_RCC_AHB1ENR_DMA1EN	BIT(0)
-#define STM32_RCC_AHB1ENR_DMA2EN	BIT(1)
-#define STM32_RCC_AHB1ENR_DMAMUXEN	BIT(2)
+#define STM32_RCC_AHB1ENR_DMA1EN BIT(0)
+#define STM32_RCC_AHB1ENR_DMA2EN BIT(1)
+#define STM32_RCC_AHB1ENR_DMAMUXEN BIT(2)
 
 /* --- RCC AHB2ENR Bit Definitions --- */
-#define STM32_RCC_AHB2ENR_GPIO_PORTA	BIT(0)
-#define STM32_RCC_AHB2ENR_GPIO_PORTB	BIT(1)
-#define STM32_RCC_AHB2ENR_GPIO_PORTC	BIT(2)
-#define STM32_RCC_AHB2ENR_GPIO_PORTD	BIT(3)
-#define STM32_RCC_AHB2ENR_GPIO_PORTE	BIT(4)
-#define STM32_RCC_AHB2ENR_GPIO_PORTF	BIT(5)
-#define STM32_RCC_AHB2ENR_GPIO_PORTG	BIT(6)
-#define STM32_RCC_AHB2ENR_GPIOMASK	(0x7f << 0)
-#define STM32_RCC_AHB2ENR_ADC12EN	BIT(13)
-#define STM32_RCC_APB2ENR_ADC345EN	BIT(14)
-#define STM32_RCC_AHB2ENR_RNGEN		BIT(26)
+#define STM32_RCC_AHB2ENR_GPIO_PORTA BIT(0)
+#define STM32_RCC_AHB2ENR_GPIO_PORTB BIT(1)
+#define STM32_RCC_AHB2ENR_GPIO_PORTC BIT(2)
+#define STM32_RCC_AHB2ENR_GPIO_PORTD BIT(3)
+#define STM32_RCC_AHB2ENR_GPIO_PORTE BIT(4)
+#define STM32_RCC_AHB2ENR_GPIO_PORTF BIT(5)
+#define STM32_RCC_AHB2ENR_GPIO_PORTG BIT(6)
+#define STM32_RCC_AHB2ENR_GPIOMASK (0x7f << 0)
+#define STM32_RCC_AHB2ENR_ADC12EN BIT(13)
+#define STM32_RCC_APB2ENR_ADC345EN BIT(14)
+#define STM32_RCC_AHB2ENR_RNGEN BIT(26)
 
 /* --- RCC APB1ENR1 Bit Definitions --- */
-#define STM32_RCC_APB1ENR1_TIM2EN                BIT(0)
-#define STM32_RCC_APB1ENR1_TIM3EN                BIT(1)
-#define STM32_RCC_APB1ENR1_TIM4EN                BIT(2)
-#define STM32_RCC_APB1ENR1_TIM5EN                BIT(3)
-#define STM32_RCC_APB1ENR1_TIM6EN                BIT(4)
-#define STM32_RCC_APB1ENR1_TIM7EN                BIT(5)
-#define STM32_RCC_APB1ENR1_WWDGEN                BIT(11)
-#define STM32_RCC_APB1ENR1_USART2                BIT(17)
-#define STM32_RCC_APB1ENR1_USART3                BIT(18)
-#define STM32_RCC_APB1ENR1_UART4                 BIT(19)
-#define STM32_RCC_APB1ENR1_UART5                 BIT(20)
-#define STM32_RCC_APB1ENR1_I2C1EN                BIT(21)
-#define STM32_RCC_APB1ENR1_I2C2EN                BIT(22)
-#define STM32_RCC_APB1ENR1_USBEN                 BIT(23)
-#define STM32_RCC_APB1ENR1_PWREN                 BIT(28)
-#define STM32_RCC_APB1ENR1_I2C3EN                BIT(30)
+#define STM32_RCC_APB1ENR1_TIM2EN BIT(0)
+#define STM32_RCC_APB1ENR1_TIM3EN BIT(1)
+#define STM32_RCC_APB1ENR1_TIM4EN BIT(2)
+#define STM32_RCC_APB1ENR1_TIM5EN BIT(3)
+#define STM32_RCC_APB1ENR1_TIM6EN BIT(4)
+#define STM32_RCC_APB1ENR1_TIM7EN BIT(5)
+#define STM32_RCC_APB1ENR1_WWDGEN BIT(11)
+#define STM32_RCC_APB1ENR1_USART2 BIT(17)
+#define STM32_RCC_APB1ENR1_USART3 BIT(18)
+#define STM32_RCC_APB1ENR1_UART4 BIT(19)
+#define STM32_RCC_APB1ENR1_UART5 BIT(20)
+#define STM32_RCC_APB1ENR1_I2C1EN BIT(21)
+#define STM32_RCC_APB1ENR1_I2C2EN BIT(22)
+#define STM32_RCC_APB1ENR1_USBEN BIT(23)
+#define STM32_RCC_APB1ENR1_PWREN BIT(28)
+#define STM32_RCC_APB1ENR1_I2C3EN BIT(30)
 
 #define STM32_RCC_PWREN STM32_RCC_APB1ENR1_PWREN
 
 /* --- RCC APB1ENR2 Bit Definitions --- */
-#define STM32_RCC_APB1ENR2_LPUART1EN             BIT(0)
-#define STM32_RCC_APB1ENR2_I2C4EN                BIT(1)
-#define STM32_RCC_APB1ENR2_UPCD1EN               BIT(8)
+#define STM32_RCC_APB1ENR2_LPUART1EN BIT(0)
+#define STM32_RCC_APB1ENR2_I2C4EN BIT(1)
+#define STM32_RCC_APB1ENR2_UPCD1EN BIT(8)
 
 /* --- RCC APB2ENR Bit Definitions --- */
-#define STM32_RCC_APB2ENR_SYSCFGEN	BIT(0)
-#define STM32_RCC_APB2ENR_TIM1		BIT(11)
-#define STM32_RCC_APB2ENR_SPI1EN	BIT(12)
-#define STM32_RCC_APB2ENR_TIM8		BIT(13)
-#define STM32_RCC_APB2ENR_USART1        BIT(14)
-#define STM32_RCC_APB2ENR_SPI4EN	BIT(15)
-#define STM32_RCC_APB2ENR_TIM15	BIT(16)
-#define STM32_RCC_APB2ENR_TIM16	BIT(17)
-#define STM32_RCC_APB2ENR_TIM17	BIT(18)
-#define STM32_RCC_APB2ENR_TIM20	BIT(20)
-
-#define STM32_RCC_PB2_USART1		STM32_RCC_APB2ENR_USART1
+#define STM32_RCC_APB2ENR_SYSCFGEN BIT(0)
+#define STM32_RCC_APB2ENR_TIM1 BIT(11)
+#define STM32_RCC_APB2ENR_SPI1EN BIT(12)
+#define STM32_RCC_APB2ENR_TIM8 BIT(13)
+#define STM32_RCC_APB2ENR_USART1 BIT(14)
+#define STM32_RCC_APB2ENR_SPI4EN BIT(15)
+#define STM32_RCC_APB2ENR_TIM15 BIT(16)
+#define STM32_RCC_APB2ENR_TIM16 BIT(17)
+#define STM32_RCC_APB2ENR_TIM17 BIT(18)
+#define STM32_RCC_APB2ENR_TIM20 BIT(20)
+
+#define STM32_RCC_PB2_USART1 STM32_RCC_APB2ENR_USART1
 
 /* gpio.c needs STM32_RCC_SYSCFGEN */
 #define STM32_RCC_SYSCFGEN STM32_RCC_APB2ENR_SYSCFGEN
 
+/* --- RCC APB1RSTR1 Bit Definitions --- */
+#define STM32_RCC_APB1RSTR1_USB_RST BIT(23)
+#define STM32_RCC_APB1RSTR STM32_RCC_APB1RSTR1
+#define STM32_RCC_PB1_USB STM32_RCC_APB1RSTR1_USB_RST
+
 /* --- RCC CSR Bit Definitions --- */
-#define STM32_RCC_CSR_LSION		BIT(0)
-#define STM32_RCC_CSR_LSIRDY		BIT(1)
+#define STM32_RCC_CSR_LSION BIT(0)
+#define STM32_RCC_CSR_LSIRDY BIT(1)
 
 /* --- RCC CCIPR Bit Definitions --- */
-#define STM32_RCC_CCIPR_UART_SYSCLK      0x1
-#define STM32_RCC_CCIPR_USART1SEL_MASK   0x3
-#define STM32_RCC_CCIPR_USART1SEL_SHIFT  0
-#define STM32_RCC_CCIPR_LPUART1SEL_MASK  0x3
+#define STM32_RCC_CCIPR_UART_SYSCLK 0x1
+#define STM32_RCC_CCIPR_USART1SEL_MASK 0x3
+#define STM32_RCC_CCIPR_USART1SEL_SHIFT 0
+#define STM32_RCC_CCIPR_LPUART1SEL_MASK 0x3
 #define STM32_RCC_CCIPR_LPUART1SEL_SHIFT 10
-#define STM32_RCC_CCIPR_I2C1SEL_MASK     0x3
-#define STM32_RCC_CCIPR_I2C1SEL_SHIFT    12
-#define STM32_RCC_CCIPR_I2C2SEL_MASK     0x3
-#define STM32_RCC_CCIPR_I2C2SEL_SHIFT    14
-#define STM32_RCC_CCIPR_I2C3SEL_MASK     0x3
-#define STM32_RCC_CCIPR_I2C3SEL_SHIFT    16
+#define STM32_RCC_CCIPR_I2C1SEL_MASK 0x3
+#define STM32_RCC_CCIPR_I2C1SEL_SHIFT 12
+#define STM32_RCC_CCIPR_I2C2SEL_MASK 0x3
+#define STM32_RCC_CCIPR_I2C2SEL_SHIFT 14
+#define STM32_RCC_CCIPR_I2C3SEL_MASK 0x3
+#define STM32_RCC_CCIPR_I2C3SEL_SHIFT 16
 
-#define STM32_RCC_CCIPR2_I2C4SEL_MASK    0x3
+#define STM32_RCC_CCIPR2_I2C4SEL_MASK 0x3
 
-#define STM32_RCC_CCIPR_I2CNSEL_MASK     0x3
+#define STM32_RCC_CCIPR_I2CNSEL_MASK 0x3
 #define STM32_RCC_CCIPR_I2CNSEL_SHIFT(n) (STM32_RCC_CCIPR_I2C1SEL_SHIFT + n * 2)
-#define STM32_RCC_CCIPR_I2CNSEL_HSI      0x2
+#define STM32_RCC_CCIPR_I2CNSEL_HSI 0x2
 /* --- RCC CRRCR Bit Definitions */
-#define RCC_CRRCR_HSI48O               BIT(0)
-#define RCC_CRRCR_HSIRDY               BIT(1)
+#define RCC_CRRCR_HSI48O BIT(0)
+#define RCC_CRRCR_HSIRDY BIT(1)
 
 /* Reset causes definitions */
 /*
  * Reset causes in RCC CSR register. The generic names are required
  */
 #define STM32_RCC_RESET_CAUSE STM32_RCC_CSR
-#define STM32_RCC_CSR_RMVF              BIT(24)
-#define STM32_RCC_CSR_BORRS             BIT(25)
-#define STM32_RCC_CSR_PIN               BIT(26)
-#define STM32_RCC_CSR_POR               BIT(27)
-#define STM32_RCC_CSR_SFT               BIT(28)
-#define STM32_RCC_CSR_IWDG              BIT(29)
-#define STM32_RCC_CSR_WWDG              BIT(30)
-#define STM32_RCC_CSR_LPWR              BIT(31)
-
-
-#define  RESET_CAUSE_WDG                (STM32_RCC_CSR_WWDG | \
-					 STM32_RCC_CSR_IWDG)
-#define  RESET_CAUSE_SFT                STM32_RCC_CSR_SFT
-#define  RESET_CAUSE_POR                STM32_RCC_CSR_POR
-#define  RESET_CAUSE_PIN                STM32_RCC_CSR_PIN
-#define  RESET_CAUSE_RMVF               STM32_RCC_CSR_RMVF
-#define  RESET_CAUSE_OTHER              (STM32_RCC_CSR_LPWR | \
-					 STM32_RCC_CSR_BORRS)
+#define STM32_RCC_CSR_RMVF BIT(24)
+#define STM32_RCC_CSR_BORRS BIT(25)
+#define STM32_RCC_CSR_PIN BIT(26)
+#define STM32_RCC_CSR_POR BIT(27)
+#define STM32_RCC_CSR_SFT BIT(28)
+#define STM32_RCC_CSR_IWDG BIT(29)
+#define STM32_RCC_CSR_WWDG BIT(30)
+#define STM32_RCC_CSR_LPWR BIT(31)
+
+#define RESET_CAUSE_WDG (STM32_RCC_CSR_WWDG | STM32_RCC_CSR_IWDG)
+#define RESET_CAUSE_SFT STM32_RCC_CSR_SFT
+#define RESET_CAUSE_POR STM32_RCC_CSR_POR
+#define RESET_CAUSE_PIN STM32_RCC_CSR_PIN
+#define RESET_CAUSE_RMVF STM32_RCC_CSR_RMVF
+#define RESET_CAUSE_OTHER (STM32_RCC_CSR_LPWR | STM32_RCC_CSR_BORRS)
 /* Power cause in PWR CSR register */
-#define STM32_PWR_CR1                   REG32(STM32_PWR_BASE + 0x00)
-#define STM32_PWR_CR2                   REG32(STM32_PWR_BASE + 0x04)
-#define STM32_PWR_CR3                   REG32(STM32_PWR_BASE + 0x08)
-#define STM32_PWR_CR4                   REG32(STM32_PWR_BASE + 0x0C)
-#define STM32_PWR_SR1                   REG32(STM32_PWR_BASE + 0x10)
-#define STM32_PWR_SR2                   REG32(STM32_PWR_BASE + 0x14)
-#define STM32_PWR_SCR                   REG32(STM32_PWR_BASE + 0x18)
-#define STM32_PWR_SCR_CSBF              BIT(8)
-#define STM32_PWR_SR1_SBF               BIT(8)
+#define STM32_PWR_CR1 REG32(STM32_PWR_BASE + 0x00)
+#define STM32_PWR_CR2 REG32(STM32_PWR_BASE + 0x04)
+#define STM32_PWR_CR3 REG32(STM32_PWR_BASE + 0x08)
+#define STM32_PWR_CR4 REG32(STM32_PWR_BASE + 0x0C)
+#define STM32_PWR_SR1 REG32(STM32_PWR_BASE + 0x10)
+#define STM32_PWR_SR2 REG32(STM32_PWR_BASE + 0x14)
+#define STM32_PWR_SCR REG32(STM32_PWR_BASE + 0x18)
+#define STM32_PWR_SCR_CSBF BIT(8)
+#define STM32_PWR_SR1_SBF BIT(8)
 
 #define STM32_PWR_RESET_CAUSE STM32_PWR_SR1
-#define  RESET_CAUSE_SBF                STM32_PWR_SR1_SBF
+#define RESET_CAUSE_SBF STM32_PWR_SR1_SBF
 #define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_SCR
-#define  RESET_CAUSE_SBF_CLR            STM32_PWR_SCR_CSBF
+#define RESET_CAUSE_SBF_CLR STM32_PWR_SCR_CSBF
+
+#define STM32_PWR_CR1_DBP BIT(8)
 
-#define STM32_PWR_CR3_UCPD1_STDBY       BIT(13)
-#define STM32_PWR_CR3_UCPD1_DBDIS       BIT(14)
+#define STM32_PWR_CR3_UCPD1_STDBY BIT(13)
+#define STM32_PWR_CR3_UCPD1_DBDIS BIT(14)
 
 /* --- System Config Registers --- */
-#define STM32_SYSCFG_MEMRMP             REG32(STM32_SYSCFG_BASE + 0x00)
-#define STM32_SYSCFG_PMC                REG32(STM32_SYSCFG_BASE + 0x04)
-#define STM32_SYSCFG_EXTICR(n)          REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
-#define STM32_SYSCFG_CMPCR              REG32(STM32_SYSCFG_BASE + 0x20)
-#define STM32_SYSCFG_CFGR               REG32(STM32_SYSCFG_BASE + 0x2C)
+#define STM32_SYSCFG_MEMRMP REG32(STM32_SYSCFG_BASE + 0x00)
+#define STM32_SYSCFG_PMC REG32(STM32_SYSCFG_BASE + 0x04)
+#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
+#define STM32_SYSCFG_CMPCR REG32(STM32_SYSCFG_BASE + 0x20)
+#define STM32_SYSCFG_CFGR REG32(STM32_SYSCFG_BASE + 0x2C)
 
 /* --- Watchdogs --- */
 
 /* --- Real-Time Clock --- */
-#define STM32_RTC_TR                REG32(STM32_RTC_BASE + 0x00)
-#define STM32_RTC_DR                REG32(STM32_RTC_BASE + 0x04)
-#define STM32_RTC_SSR               REG32(STM32_RTC_BASE + 0x08)
-#define STM32_RTC_ISR               REG32(STM32_RTC_BASE + 0x0C)
-#define STM32_RTC_PRER              REG32(STM32_RTC_BASE + 0x10)
-#define STM32_RTC_WUTR              REG32(STM32_RTC_BASE + 0x14)
-#define STM32_RTC_CR                REG32(STM32_RTC_BASE + 0x18)
-
-
-#define STM32_RTC_WPR               REG32(STM32_RTC_BASE + 0x24)
-#define STM32_RTC_CALR              REG32(STM32_RTC_BASE + 0x28)
-#define STM32_RTC_SHIFTR            REG32(STM32_RTC_BASE + 0x2C)
-#define STM32_RTC_TSTR              REG32(STM32_RTC_BASE + 0x30)
-#define STM32_RTC_TSDR              REG32(STM32_RTC_BASE + 0x34)
-#define STM32_RTC_TSSSR             REG32(STM32_RTC_BASE + 0x38)
-
-#define STM32_RTC_ALRMAR            REG32(STM32_RTC_BASE + 0x40)
-#define STM32_RTC_ALRMASSR          REG32(STM32_RTC_BASE + 0x44)
-#define STM32_RTC_ALRMBR            REG32(STM32_RTC_BASE + 0x48)
-#define STM32_RTC_ALRMBSSR          REG32(STM32_RTC_BASE + 0x44)
+#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00)
+#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04)
+#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x08)
+#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C)
+#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10)
+#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14)
+#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x18)
+
+#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24)
+#define STM32_RTC_CALR REG32(STM32_RTC_BASE + 0x28)
+#define STM32_RTC_SHIFTR REG32(STM32_RTC_BASE + 0x2C)
+#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30)
+#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34)
+#define STM32_RTC_TSSSR REG32(STM32_RTC_BASE + 0x38)
+
+#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x40)
+#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44)
+#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x48)
+#define STM32_RTC_ALRMBSSR REG32(STM32_RTC_BASE + 0x44)
 
 /* --- RTC CR Bit Definitions --- */
-#define STM32_RTC_CR_BYPSHAD        BIT(5)
-#define STM32_RTC_CR_ALRAE          BIT(8)
-#define STM32_RTC_CR_ALRAIE         BIT(12)
+#define STM32_RTC_CR_BYPSHAD BIT(5)
+#define STM32_RTC_CR_ALRAE BIT(8)
+#define STM32_RTC_CR_ALRAIE BIT(12)
 /* --- RTC ICSR Bit Definitions --- */
-#define STM32_RTC_ISR_ALRAWF        BIT(0)
-#define STM32_RTC_ISR_RSF           BIT(5)
-#define STM32_RTC_ISR_INITF         BIT(6)
-#define STM32_RTC_ISR_INIT          BIT(7)
-#define STM32_RTC_ISR_ALRAF         BIT(8)
+#define STM32_RTC_ISR_ALRAWF BIT(0)
+#define STM32_RTC_ISR_RSF BIT(5)
+#define STM32_RTC_ISR_INITF BIT(6)
+#define STM32_RTC_ISR_INIT BIT(7)
+#define STM32_RTC_ISR_ALRAF BIT(8)
 /* --- RTC PRER Bit Definitions --- */
-#define STM32_RTC_PRER_A_MASK       (0x7f << 16)
-#define STM32_RTC_PRER_S_MASK       (0x7fff << 0)
-
+#define STM32_RTC_PRER_A_MASK (0x7f << 16)
+#define STM32_RTC_PRER_S_MASK (0x7fff << 0)
 
 /* --- Tamper and Backup --- */
-#define STM32_TAMP_BKPxR(n)         REG32(STM32_TAMP_BASE + 0x100 + 4 * (n))
-#define STM32_BKP_DATA(n)           STM32_TAMP_BKPxR(n)
-#define STM32_BKP_BYTES             128
-
+#define STM32_TAMP_BKPxR(n) REG32(STM32_TAMP_BASE + 0x100 + 4 * (n))
+#define STM32_BKP_DATA(n) STM32_TAMP_BKPxR(n)
+#define STM32_BKP_BYTES 64
 
 /* --- SPI --- */
 
@@ -844,7 +833,7 @@ struct stm32_spi_regs {
 	uint16_t _pad0;
 	uint16_t cr2;
 	uint16_t _pad1;
-	unsigned sr;
+	unsigned int sr;
 	uint8_t dr;
 	uint8_t _pad2;
 	uint16_t _pad3;
@@ -862,196 +851,222 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
 #define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE)
 #define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE)
 
-#define STM32_SPI_CR1_BIDIMODE		BIT(15)
-#define STM32_SPI_CR1_BIDIOE		BIT(14)
-#define STM32_SPI_CR1_CRCEN		BIT(13)
-#define STM32_SPI_CR1_SSM		BIT(9)
-#define STM32_SPI_CR1_SSI		BIT(8)
-#define STM32_SPI_CR1_LSBFIRST		BIT(7)
-#define STM32_SPI_CR1_SPE		BIT(6)
-#define STM32_SPI_CR1_BR_DIV64R		(5 << 3)
-#define STM32_SPI_CR1_BR_DIV4R		BIT(3)
-#define STM32_SPI_CR1_MSTR		BIT(2)
-#define STM32_SPI_CR1_CPOL		BIT(1)
-#define STM32_SPI_CR1_CPHA		BIT(0)
-#define STM32_SPI_CR2_FRXTH		BIT(12)
-#define STM32_SPI_CR2_DATASIZE(n)	(((n) - 1) << 8)
-#define STM32_SPI_CR2_TXEIE		BIT(7)
-#define STM32_SPI_CR2_RXNEIE		BIT(6)
-#define STM32_SPI_CR2_NSSP		BIT(3)
-#define STM32_SPI_CR2_SSOE		BIT(2)
-#define STM32_SPI_CR2_TXDMAEN		BIT(1)
-#define STM32_SPI_CR2_RXDMAEN		BIT(0)
-
-#define STM32_SPI_SR_RXNE		BIT(0)
-#define STM32_SPI_SR_TXE		BIT(1)
-#define STM32_SPI_SR_CRCERR		BIT(4)
-#define STM32_SPI_SR_BSY		BIT(7)
-#define STM32_SPI_SR_FRLVL		(3 << 9)
-#define STM32_SPI_SR_FTLVL		(3 << 11)
+#define STM32_SPI_CR1_BIDIMODE BIT(15)
+#define STM32_SPI_CR1_BIDIOE BIT(14)
+#define STM32_SPI_CR1_CRCEN BIT(13)
+#define STM32_SPI_CR1_SSM BIT(9)
+#define STM32_SPI_CR1_SSI BIT(8)
+#define STM32_SPI_CR1_LSBFIRST BIT(7)
+#define STM32_SPI_CR1_SPE BIT(6)
+#define STM32_SPI_CR1_BR_DIV64R (5 << 3)
+#define STM32_SPI_CR1_BR_DIV4R BIT(3)
+#define STM32_SPI_CR1_MSTR BIT(2)
+#define STM32_SPI_CR1_CPOL BIT(1)
+#define STM32_SPI_CR1_CPHA BIT(0)
+#define STM32_SPI_CR2_FRXTH BIT(12)
+#define STM32_SPI_CR2_DATASIZE(n) (((n)-1) << 8)
+#define STM32_SPI_CR2_TXEIE BIT(7)
+#define STM32_SPI_CR2_RXNEIE BIT(6)
+#define STM32_SPI_CR2_NSSP BIT(3)
+#define STM32_SPI_CR2_SSOE BIT(2)
+#define STM32_SPI_CR2_TXDMAEN BIT(1)
+#define STM32_SPI_CR2_RXDMAEN BIT(0)
+
+#define STM32_SPI_SR_RXNE BIT(0)
+#define STM32_SPI_SR_TXE BIT(1)
+#define STM32_SPI_SR_CRCERR BIT(4)
+#define STM32_SPI_SR_BSY BIT(7)
+#define STM32_SPI_SR_FRLVL (3 << 9)
+#define STM32_SPI_SR_FTLVL (3 << 11)
 
 /* --- Debug --- */
-#define STM32_DBGMCU_CR             REG32(STM32_DBGMCU_BASE + 0x04)
-#define STM32_DBGMCU_APB1FZ         REG32(STM32_DBGMCU_BASE + 0x08)
-#define STM32_DBGMCU_APB2FZ         REG32(STM32_DBGMCU_BASE + 0x0C)
+#define STM32_DBGMCU_IDCODE REG32(STM32_DBGMCU_BASE + 0x00)
+#define STM32_DBGMCU_CR REG32(STM32_DBGMCU_BASE + 0x04)
+#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08)
+#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C)
 
 /* --- DBGMCU CR Bit Definitions --- */
-#define  STM32_DBGMCU_CR_SLEEP                      BIT(0)
-#define  STM32_DBGMCU_CR_STOP                       BIT(1)
-#define  STM32_DBGMCU_CR_STBY                       BIT(2)
-#define  STM32_DBGMCU_CR_TRACE_MASK                 (BIT(5)|BIT(6)|BIT(7))
-#define   STM32_DBGMCU_CR_TRACE_EN                   BIT(5)
-#define   STM32_DBGMCU_CR_TRACE_MODE_ASYNC           0
-#define   STM32_DBGMCU_CR_TRACE_MODE_SYNC1           BIT(6)
-#define   STM32_DBGMCU_CR_TRACE_MODE_SYNC2           BIT(7)
-#define   STM32_DBGMCU_CR_TRACE_MODE_SYNC4           (BIT(6)|BIT(7))
+#define STM32_DBGMCU_CR_SLEEP BIT(0)
+#define STM32_DBGMCU_CR_STOP BIT(1)
+#define STM32_DBGMCU_CR_STBY BIT(2)
+#define STM32_DBGMCU_CR_TRACE_MASK (BIT(5) | BIT(6) | BIT(7))
+#define STM32_DBGMCU_CR_TRACE_EN BIT(5)
+#define STM32_DBGMCU_CR_TRACE_MODE_ASYNC 0
+#define STM32_DBGMCU_CR_TRACE_MODE_SYNC1 BIT(6)
+#define STM32_DBGMCU_CR_TRACE_MODE_SYNC2 BIT(7)
+#define STM32_DBGMCU_CR_TRACE_MODE_SYNC4 (BIT(6) | BIT(7))
 /* --- DBGMCU APB1FZ Bit Definitions --- */
-#define  STM32_DBGMCU_APB1FZ_TIM2                   BIT(0)
-#define  STM32_DBGMCU_APB1FZ_TIM3                   BIT(1)
-#define  STM32_DBGMCU_APB1FZ_TIM4                   BIT(2)
-#define  STM32_DBGMCU_APB1FZ_TIM5                   BIT(3)
-#define  STM32_DBGMCU_APB1FZ_TIM6                   BIT(4)
-#define  STM32_DBGMCU_APB1FZ_TIM7                   BIT(5)
-#define  STM32_DBGMCU_APB1FZ_RTC                    BIT(10)
-#define  STM32_DBGMCU_APB1FZ_WWDG                   BIT(11)
-#define  STM32_DBGMCU_APB1FZ_IWDG                   BIT(12)
-#define  STM32_DBGMCU_APB1FZ_I2C1_SMBUS_TIMEOUT     BIT(21)
-#define  STM32_DBGMCU_APB1FZ_I2C2_SMBUS_TIMEOUT     BIT(22)
-#define  STM32_DBGMCU_APB1FZ_I2C3_SMBUS_TIMEOUT     BIT(30)
+#define STM32_DBGMCU_APB1FZ_TIM2 BIT(0)
+#define STM32_DBGMCU_APB1FZ_TIM3 BIT(1)
+#define STM32_DBGMCU_APB1FZ_TIM4 BIT(2)
+#define STM32_DBGMCU_APB1FZ_TIM5 BIT(3)
+#define STM32_DBGMCU_APB1FZ_TIM6 BIT(4)
+#define STM32_DBGMCU_APB1FZ_TIM7 BIT(5)
+#define STM32_DBGMCU_APB1FZ_RTC BIT(10)
+#define STM32_DBGMCU_APB1FZ_WWDG BIT(11)
+#define STM32_DBGMCU_APB1FZ_IWDG BIT(12)
+#define STM32_DBGMCU_APB1FZ_I2C1_SMBUS_TIMEOUT BIT(21)
+#define STM32_DBGMCU_APB1FZ_I2C2_SMBUS_TIMEOUT BIT(22)
+#define STM32_DBGMCU_APB1FZ_I2C3_SMBUS_TIMEOUT BIT(30)
 /* --- DBGMCU  APB2FZ Bit Definitions --- */
-#define  STM32_DBGMCU_APB2FZ_TIM1                   BIT(11)
-#define  STM32_DBGMCU_APB2FZ_TIM8                   BIT(13)
-#define  STM32_DBGMCU_APB2FZ_TIM15                  BIT(16)
-#define  STM32_DBGMCU_APB2FZ_TIM16                  BIT(17)
-#define  STM32_DBGMCU_APB2FZ_TIM17                  BIT(18)
-#define  STM32_DBGMCU_APB2FZ_TIM20                  BIT(20)
+#define STM32_DBGMCU_APB2FZ_TIM1 BIT(11)
+#define STM32_DBGMCU_APB2FZ_TIM8 BIT(13)
+#define STM32_DBGMCU_APB2FZ_TIM15 BIT(16)
+#define STM32_DBGMCU_APB2FZ_TIM16 BIT(17)
+#define STM32_DBGMCU_APB2FZ_TIM17 BIT(18)
+#define STM32_DBGMCU_APB2FZ_TIM20 BIT(20)
 
 /* --- Flash --- */
-#define STM32_FLASH_REG(off)        REG32(STM32_FLASH_REGS_BASE + (off))
-#define STM32_FLASH_ACR             STM32_FLASH_REG(0x00)
-#define STM32_FLASH_PDKEYR          STM32_FLASH_REG(0x04)
-#define STM32_FLASH_KEYR            STM32_FLASH_REG(0x08)
-#define STM32_FLASH_OPTKEYR         STM32_FLASH_REG(0x0c)
-#define STM32_FLASH_SR              STM32_FLASH_REG(0x10)
-#define STM32_FLASH_CR              STM32_FLASH_REG(0x14)
-#define STM32_FLASH_ECCR            STM32_FLASH_REG(0x18)
-#define STM32_FLASH_OPTR            STM32_FLASH_REG(0x20)
-#define STM32_FLASH_PCROP1SR        STM32_FLASH_REG(0x24)
-#define STM32_FLASH_PCROP1ER        STM32_FLASH_REG(0x28)
-#define STM32_FLASH_WRP1AR          STM32_FLASH_REG(0x2C)
-#define STM32_FLASH_WRP1BR          STM32_FLASH_REG(0x30)
+#define STM32_FLASH_REG(off) REG32(STM32_FLASH_REGS_BASE + (off))
+#define STM32_FLASH_ACR STM32_FLASH_REG(0x00)
+#define STM32_FLASH_PDKEYR STM32_FLASH_REG(0x04)
+#define STM32_FLASH_KEYR STM32_FLASH_REG(0x08)
+#define STM32_FLASH_OPTKEYR STM32_FLASH_REG(0x0c)
+#define STM32_FLASH_SR STM32_FLASH_REG(0x10)
+#define STM32_FLASH_CR STM32_FLASH_REG(0x14)
+#define STM32_FLASH_ECCR STM32_FLASH_REG(0x18)
+/*
+ * Bank 1 Option Byte Copy Registers. These registers are loaded from the option
+ * bytes location in flash at reset, assuming that option byte loading has not
+ * been disabled.
+ */
+#define STM32_FLASH_OPTR STM32_FLASH_REG(0x20)
+#define STM32_FLASH_PCROP1SR STM32_FLASH_REG(0x24)
+#define STM32_FLASH_PCROP1ER STM32_FLASH_REG(0x28)
+#define STM32_FLASH_WRP1AR STM32_FLASH_REG(0x2C)
+#define STM32_FLASH_WRP1BR STM32_FLASH_REG(0x30)
+/*
+ * Bank 2 Option Byte Copy Registers. These will only exist for category 3
+ * devices.
+ */
+#define STM32_FLASH_PCROP2SR STM32_FLASH_REG(0x44)
+#define STM32_FLASH_PCROP2ER STM32_FLASH_REG(0x48)
+#define STM32_FLASH_WRP2AR STM32_FLASH_REG(0x4C)
+#define STM32_FLASH_WRP2BR STM32_FLASH_REG(0x50)
+
+#define STM32_FLASH_SEC_SIZE1 STM32_FLASH_REG(0x70)
+#define STM32_FLASH_SEC_SIZE2 STM32_FLASH_REG(0x74)
 
 /* --- FLASH CR Bit Definitions --- */
 #define STM32_FLASH_ACR_LATENCY_SHIFT (0)
-#define STM32_FLASH_ACR_LATENCY_MASK  (0xf << STM32_FLASH_ACR_LATENCY_SHIFT)
-#define STM32_FLASH_ACR_PRFTEN      BIT(8)
-#define STM32_FLASH_ACR_ICEN        BIT(9)
-#define STM32_FLASH_ACR_DCEN        BIT(10)
-#define STM32_FLASH_ACR_ICRST       BIT(11)
-#define STM32_FLASH_ACR_DCRST       BIT(12)
+#define STM32_FLASH_ACR_LATENCY_MASK (0xf << STM32_FLASH_ACR_LATENCY_SHIFT)
+#define STM32_FLASH_ACR_PRFTEN BIT(8)
+#define STM32_FLASH_ACR_ICEN BIT(9)
+#define STM32_FLASH_ACR_DCEN BIT(10)
+#define STM32_FLASH_ACR_ICRST BIT(11)
+#define STM32_FLASH_ACR_DCRST BIT(12)
 
 /* --- FLASH KEYR Bit Definitions --- */
-#define  FLASH_KEYR_KEY1            0x45670123
-#define  FLASH_KEYR_KEY2            0xCDEF89AB
+#define FLASH_KEYR_KEY1 0x45670123
+#define FLASH_KEYR_KEY2 0xCDEF89AB
 
 /* --- FLASH OPTKEYR Bit Definitions --- */
-#define  FLASH_OPTKEYR_KEY1         0x08192A3B
-#define  FLASH_OPTKEYR_KEY2         0x4C5D6E7F
+#define FLASH_OPTKEYR_KEY1 0x08192A3B
+#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F
 
 /* --- FLASH SR Bit Definitions --- */
-#define  FLASH_SR_BUSY              BIT(16)
-#define  FLASH_SR_OPTVERR           BIT(15)
-#define  FLASH_SR_RDERR             BIT(14)
-#define  FLASH_SR_FASTERR           BIT(9)
-#define  FLASH_SR_MISERR            BIT(8)
-#define  FLASH_SR_PGSERR            BIT(7)
-#define  FLASH_SR_SIZERR            BIT(6)
-#define  FLASH_SR_PGAERR            BIT(5)
-#define  FLASH_SR_WRPERR            BIT(4)
-#define  FLASH_SR_PROGERR           BIT(3)
-#define  FLASH_SR_OPERR             BIT(1)
-#define  FLASH_SR_ERR_MASK          (FLASH_SR_OPTVERR | FLASH_SR_RDERR | \
-				     FLASH_SR_FASTERR | FLASH_SR_PGSERR | \
-				     FLASH_SR_SIZERR | FLASH_SR_PGAERR |  \
-				     FLASH_SR_WRPERR |  FLASH_SR_PROGERR | \
-				     FLASH_SR_OPERR)
+#define FLASH_SR_BUSY BIT(16)
+#define FLASH_SR_OPTVERR BIT(15)
+#define FLASH_SR_RDERR BIT(14)
+#define FLASH_SR_FASTERR BIT(9)
+#define FLASH_SR_MISERR BIT(8)
+#define FLASH_SR_PGSERR BIT(7)
+#define FLASH_SR_SIZERR BIT(6)
+#define FLASH_SR_PGAERR BIT(5)
+#define FLASH_SR_WRPERR BIT(4)
+#define FLASH_SR_PROGERR BIT(3)
+#define FLASH_SR_OPERR BIT(1)
+#define FLASH_SR_ERR_MASK                                       \
+	(FLASH_SR_OPTVERR | FLASH_SR_RDERR | FLASH_SR_FASTERR | \
+	 FLASH_SR_PGSERR | FLASH_SR_SIZERR | FLASH_SR_PGAERR |  \
+	 FLASH_SR_WRPERR | FLASH_SR_PROGERR | FLASH_SR_OPERR)
 
 /* --- FLASH CR Bit Definitions --- */
-#define  FLASH_CR_PG                BIT(0)
-#define  FLASH_CR_PER               BIT(1)
-#define  FLASH_CR_STRT              BIT(16)
-#define  FLASH_CR_OPTSTRT           BIT(17)
-#define  FLASH_CR_OBL_LAUNCH        BIT(27)
-#define  FLASH_CR_OPTLOCK           BIT(30)
-#define  FLASH_CR_LOCK              BIT(31)
-#define  FLASH_CR_PNB(sec)          (((sec) & 0x7f) << 3)
-#define  FLASH_CR_PNB_MASK          FLASH_CR_PNB(0x7f)
-
-#define STM32_FLASH_MIN_WRITE_SIZE  (CONFIG_FLASH_WRITE_SIZE * 2)
+#define FLASH_CR_PG BIT(0)
+#define FLASH_CR_PER BIT(1)
+#define FLASH_CR_STRT BIT(16)
+#define FLASH_CR_OPTSTRT BIT(17)
+#define FLASH_CR_OBL_LAUNCH BIT(27)
+#define FLASH_CR_OPTLOCK BIT(30)
+#define FLASH_CR_LOCK BIT(31)
+#define FLASH_CR_PNB(sec) (((sec)&0x7f) << 3)
+#define FLASH_CR_PNB_MASK FLASH_CR_PNB(0x7f)
+
+#define STM32_FLASH_MIN_WRITE_SIZE (CONFIG_FLASH_WRITE_SIZE * 2)
 
 /* --- FLASH Option bytes --- */
-#define STM32_OPTB_USER_RDP         REG32(STM32_OPTB_BASE + 0x00)
-#define STM32_OPTB_PCROP1_START     REG32(STM32_OPTB_BASE + 0x08)
-#define STM32_OPTB_PCROP1_END       REG32(STM32_OPTB_BASE + 0x10)
-#define STM32_OPTB_WRP1AR           REG32(STM32_OPTB_BASE + 0x18)
-#define STM32_OPTB_WRP1BR           REG32(STM32_OPTB_BASE + 0x20)
-#define STM32_OPTB_SECURE_MEM       REG32(STM32_OPTB_BASE + 0x28)
-
-#define STM32_OPTB_REG_READ(n)  REG32(STM32_FLASH_REG(0x20) + (n * 4))
-#define STM32_OPTB_READ(n)      REG32(STM32_OPTB_BASE + ((n) * 8))
-#define STM32_OPTB_COMP_READ(n) REG32(STM32_OPTB_BASE + ((n) * 8) + 0x4)
-
-#define STM32_OPTB_USER_nBOOT1      BIT(23)
-#define STM32_OPTB_USER_nSWBOOT0    BIT(26)
-#define STM32_OPTB_USER_nBOOT0      BIT(27)
+#define STM32_OPTB_USER_RDP REG32(STM32_OPTB_BANK1_BASE + 0x00)
+#define STM32_OPTB_PCROP1_START REG32(STM32_OPTB_BANK1_BASE + 0x08)
+#define STM32_OPTB_PCROP1_END REG32(STM32_OPTB_BANK1_BASE + 0x10)
+#define STM32_OPTB_WRP1AR REG32(STM32_OPTB_BANK1_BASE + 0x18)
+#define STM32_OPTB_WRP1BR REG32(STM32_OPTB_BANK1_BASE + 0x20)
+#define STM32_OPTB_SECURE1_MEM REG32(STM32_OPTB_BANK1_BASE + 0x28)
+
+#define STM32_OPTB_UNUSED REG32(STM32_OPTB_BANK2_BASE + 0x00)
+#define STM32_OPTB_PCROP2_START REG32(STM32_OPTB_BANK2_BASE + 0x08)
+#define STM32_OPTB_PCROP2_END REG32(STM32_OPTB_BANK2_BASE + 0x10)
+#define STM32_OPTB_WRP2AR REG32(STM32_OPTB_BANK2_BASE + 0x18)
+#define STM32_OPTB_WRP2BR REG32(STM32_OPTB_BANK2_BASE + 0x20)
+#define STM32_OPTB_SECURE2_MEM REG32(STM32_OPTB_BANK2_BASE + 0x28)
+
+/* Read option bytes from flash memory for Bank 1 */
+#define STM32_OPTB_BANK1_READ(n) REG32(STM32_OPTB_BANK1_BASE + ((n)*8))
+#define STM32_OPTB_BANK1_COMP_READ(n) \
+	REG32(STM32_OPTB_BANK1_BASE + ((n)*8) + 0x4)
+#define STM32_OPTB_BANK2_READ(n) REG32(STM32_OPTB_BANK2_BASE + ((n)*8))
+#define STM32_OPTB_BANK2_COMP_READ(n) \
+	REG32(STM32_OPTB_BANK2_BASE + ((n)*8) + 0x4)
+
+#define STM32_OPTB_USER_DBANK BIT(22)
+#define STM32_OPTB_USER_nBOOT1 BIT(23)
+#define STM32_OPTB_USER_nSWBOOT0 BIT(26)
+#define STM32_OPTB_USER_nBOOT0 BIT(27)
 #define STM32_OPTB_ENTRY_NUM 6
 
 /* --- External Interrupts --- */
-#define STM32_EXTI_IMR              REG32(STM32_EXTI_BASE + 0x00)
-#define STM32_EXTI_EMR              REG32(STM32_EXTI_BASE + 0x04)
-#define STM32_EXTI_RTSR             REG32(STM32_EXTI_BASE + 0x08)
-#define STM32_EXTI_FTSR             REG32(STM32_EXTI_BASE + 0x0c)
-#define STM32_EXTI_SWIER            REG32(STM32_EXTI_BASE + 0x10)
-#define STM32_EXTI_PR               REG32(STM32_EXTI_BASE + 0x14)
+#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00)
+#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04)
+#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08)
+#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c)
+#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10)
+#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14)
 
 #define EXTI_RTC_ALR_EVENT BIT(17)
 
 /* --- ADC --- */
-#define STM32_ADC_ISR              REG32(STM32_ADC1_BASE + 0x00)
-#define STM32_ADC_IER              REG32(STM32_ADC1_BASE + 0x04)
-#define STM32_ADC_CR               REG32(STM32_ADC1_BASE + 0x08)
-#define STM32_ADC_CFGR             REG32(STM32_ADC1_BASE + 0x0C)
-#define STM32_ADC_CFGR2            REG32(STM32_ADC1_BASE + 0x10)
-#define STM32_ADC_SMPR1            REG32(STM32_ADC1_BASE + 0x14)
-#define STM32_ADC_SMPR2            REG32(STM32_ADC1_BASE + 0x18)
-#define STM32_ADC_TR1              REG32(STM32_ADC1_BASE + 0x20)
-#define STM32_ADC_TR2              REG32(STM32_ADC1_BASE + 0x24)
-#define STM32_ADC_TR3              REG32(STM32_ADC1_BASE + 0x28)
-#define STM32_ADC_JOFR(n)          REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4)
-#define STM32_ADC_HTR              REG32(STM32_ADC1_BASE + 0x24)
-#define STM32_ADC_LTR              REG32(STM32_ADC1_BASE + 0x28)
-#define STM32_ADC_SQR(n)           REG32(STM32_ADC1_BASE + 0x30 + ((n)&3) * 4)
-#define STM32_ADC_SQR1             REG32(STM32_ADC1_BASE + 0x30)
-#define STM32_ADC_SQR2             REG32(STM32_ADC1_BASE + 0x34)
-#define STM32_ADC_SQR3             REG32(STM32_ADC1_BASE + 0x38)
-#define STM32_ADC_SQR4             REG32(STM32_ADC1_BASE + 0x3C)
-#define STM32_ADC_DR               REG32(STM32_ADC1_BASE + 0x40)
-#define STM32_ADC_JSQR             REG32(STM32_ADC1_BASE + 0x4C)
-#define STM32_ADC_JDR(n)           REG32(STM32_ADC1_BASE + 0x80 + ((n)&3) * 4)
-
+#define STM32_ADC_ISR REG32(STM32_ADC1_BASE + 0x00)
+#define STM32_ADC_IER REG32(STM32_ADC1_BASE + 0x04)
+#define STM32_ADC_CR REG32(STM32_ADC1_BASE + 0x08)
+#define STM32_ADC_CFGR REG32(STM32_ADC1_BASE + 0x0C)
+#define STM32_ADC_CFGR2 REG32(STM32_ADC1_BASE + 0x10)
+#define STM32_ADC_SMPR1 REG32(STM32_ADC1_BASE + 0x14)
+#define STM32_ADC_SMPR2 REG32(STM32_ADC1_BASE + 0x18)
+#define STM32_ADC_TR1 REG32(STM32_ADC1_BASE + 0x20)
+#define STM32_ADC_TR2 REG32(STM32_ADC1_BASE + 0x24)
+#define STM32_ADC_TR3 REG32(STM32_ADC1_BASE + 0x28)
+#define STM32_ADC_JOFR(n) REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4)
+#define STM32_ADC_HTR REG32(STM32_ADC1_BASE + 0x24)
+#define STM32_ADC_LTR REG32(STM32_ADC1_BASE + 0x28)
+#define STM32_ADC_SQR(n) REG32(STM32_ADC1_BASE + 0x30 + ((n)&3) * 4)
+#define STM32_ADC_SQR1 REG32(STM32_ADC1_BASE + 0x30)
+#define STM32_ADC_SQR2 REG32(STM32_ADC1_BASE + 0x34)
+#define STM32_ADC_SQR3 REG32(STM32_ADC1_BASE + 0x38)
+#define STM32_ADC_SQR4 REG32(STM32_ADC1_BASE + 0x3C)
+#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x40)
+#define STM32_ADC_JSQR REG32(STM32_ADC1_BASE + 0x4C)
+#define STM32_ADC_JDR(n) REG32(STM32_ADC1_BASE + 0x80 + ((n)&3) * 4)
 
 /* --- ADC CR Bit Definitions --- */
-#define STM32_ADC_CR_ADEN          BIT(0)
-#define STM32_ADC_CR_ADSTART       BIT(2)
-#define STM32_ADC_CR_ADVREGEN      BIT(28)
-#define STM32_ADC_CR_CAL           BIT(31)
+#define STM32_ADC_CR_ADEN BIT(0)
+#define STM32_ADC_CR_ADSTART BIT(2)
+#define STM32_ADC_CR_ADVREGEN BIT(28)
+#define STM32_ADC_CR_CAL BIT(31)
 
-#define STM32_ADC_CFGR_CONT        BIT(13)
-#define STM32_ADC_CR2_ALIGN        BIT(15)
+#define STM32_ADC_CFGR_CONT BIT(13)
+#define STM32_ADC_CR2_ALIGN BIT(15)
 
 /* --- Comparators --- */
 
-
 /* --- DMA --- */
 /*
  * Available DMA streams, numbered from 0.
@@ -1133,11 +1148,11 @@ enum dma_channel {
 
 /* Registers for a single channel of the DMA controller */
 struct stm32_dma_chan {
-	uint32_t	ccr;		/* Control */
-	uint32_t	cndtr;		/* Number of data to transfer */
-	uint32_t	cpar;		/* Peripheral address */
-	uint32_t	cmar;		/* Memory address */
-	uint32_t	reserved;
+	uint32_t ccr; /* Control */
+	uint32_t cndtr; /* Number of data to transfer */
+	uint32_t cpar; /* Peripheral address */
+	uint32_t cmar; /* Memory address */
+	uint32_t reserved;
 };
 
 /* Always use stm32_dma_chan_t so volatile keyword is included! */
@@ -1148,8 +1163,8 @@ typedef stm32_dma_chan_t dma_chan_t;
 
 /* Registers for the DMA controller */
 struct stm32_dma_regs {
-	uint32_t	isr;
-	uint32_t	ifcr;
+	uint32_t isr;
+	uint32_t ifcr;
 	stm32_dma_chan_t chan[STM32_DMAC_COUNT];
 };
 
@@ -1158,78 +1173,77 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
 
 #define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE)
 
-
-#define STM32_DMA_CCR_CHANNEL(channel)		 (0)
+#define STM32_DMA_CCR_CHANNEL(channel) (0)
 #define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE)
 #define STM32_DMA_REGS(channel) \
 	((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_REGS : STM32_DMA2_REGS)
-#define STM32_DMA_CSELR(channel) \
-	REG32(((channel) < STM32_DMAC_PER_CTLR ? \
-			STM32_DMA1_BASE : STM32_DMA2_BASE)  + 0xA8)
+#define STM32_DMA_CSELR(channel)                                    \
+	REG32(((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_BASE :  \
+						 STM32_DMA2_BASE) + \
+	      0xA8)
 
 /* Bits for DMA controller regs (isr and ifcr) */
-#define STM32_DMA_CH_OFFSET(channel)   (4 * ((channel) % STM32_DMAC_PER_CTLR))
+#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR))
 #define STM32_DMA_ISR_MASK(channel, mask) \
 	((mask) << STM32_DMA_CH_OFFSET(channel))
-#define STM32_DMA_ISR_GIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(0))
-#define STM32_DMA_ISR_TCIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(1))
-#define STM32_DMA_ISR_HTIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(2))
-#define STM32_DMA_ISR_TEIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(3))
-#define STM32_DMA_ISR_ALL(channel)	STM32_DMA_ISR_MASK(channel, 0x0f)
-
-#define STM32_DMA_GIF                   BIT(0)
-#define STM32_DMA_TCIF                  BIT(1)
-#define STM32_DMA_HTIF                  BIT(2)
-#define STM32_DMA_TEIF                  BIT(3)
-#define STM32_DMA_ALL                   0xf
-
-#define STM32_DMA_GET_ISR(channel)      \
-	((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_ISR(channel, val) \
-	(STM32_DMA_REGS(channel)->isr = \
-	((STM32_DMA_REGS(channel)->isr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-#define STM32_DMA_GET_IFCR(channel)      \
-	((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_IFCR(channel, val) \
-	(STM32_DMA_REGS(channel)->ifcr = \
-	((STM32_DMA_REGS(channel)->ifcr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-
+#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0))
+#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1))
+#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2))
+#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3))
+#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f)
+
+#define STM32_DMA_GIF BIT(0)
+#define STM32_DMA_TCIF BIT(1)
+#define STM32_DMA_HTIF BIT(2)
+#define STM32_DMA_TEIF BIT(3)
+#define STM32_DMA_ALL 0xf
+
+#define STM32_DMA_GET_ISR(channel)                                        \
+	((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) & \
+	 STM32_DMA_ALL)
+#define STM32_DMA_SET_ISR(channel, val)                                \
+	(STM32_DMA_REGS(channel)->isr =                                \
+		 ((STM32_DMA_REGS(channel)->isr &                      \
+		   ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
+		  (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
+#define STM32_DMA_GET_IFCR(channel)                                        \
+	((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) & \
+	 STM32_DMA_ALL)
+#define STM32_DMA_SET_IFCR(channel, val)                               \
+	(STM32_DMA_REGS(channel)->ifcr =                               \
+		 ((STM32_DMA_REGS(channel)->ifcr &                     \
+		   ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
+		  (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
 
 /* Bits for DMA channel regs */
-#define STM32_DMA_CCR_EN		BIT(0)
-#define STM32_DMA_CCR_TCIE		BIT(1)
-#define STM32_DMA_CCR_HTIE		BIT(2)
-#define STM32_DMA_CCR_TEIE		BIT(3)
-#define STM32_DMA_CCR_DIR		BIT(4)
-#define STM32_DMA_CCR_CIRC		BIT(5)
-#define STM32_DMA_CCR_PINC		BIT(6)
-#define STM32_DMA_CCR_MINC		BIT(7)
-#define STM32_DMA_CCR_PSIZE_8_BIT	(0 << 8)
-#define STM32_DMA_CCR_PSIZE_16_BIT	(1 << 8)
-#define STM32_DMA_CCR_PSIZE_32_BIT	(2 << 8)
-#define STM32_DMA_CCR_MSIZE_8_BIT	(0 << 10)
-#define STM32_DMA_CCR_MSIZE_16_BIT	(1 << 10)
-#define STM32_DMA_CCR_MSIZE_32_BIT	(2 << 10)
-#define STM32_DMA_CCR_PL_LOW		(0 << 12)
-#define STM32_DMA_CCR_PL_MEDIUM		(1 << 12)
-#define STM32_DMA_CCR_PL_HIGH		(2 << 12)
-#define STM32_DMA_CCR_PL_VERY_HIGH	(3 << 12)
-#define STM32_DMA_CCR_MEM2MEM		BIT(14)
+#define STM32_DMA_CCR_EN BIT(0)
+#define STM32_DMA_CCR_TCIE BIT(1)
+#define STM32_DMA_CCR_HTIE BIT(2)
+#define STM32_DMA_CCR_TEIE BIT(3)
+#define STM32_DMA_CCR_DIR BIT(4)
+#define STM32_DMA_CCR_CIRC BIT(5)
+#define STM32_DMA_CCR_PINC BIT(6)
+#define STM32_DMA_CCR_MINC BIT(7)
+#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8)
+#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8)
+#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8)
+#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10)
+#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10)
+#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10)
+#define STM32_DMA_CCR_PL_LOW (0 << 12)
+#define STM32_DMA_CCR_PL_MEDIUM (1 << 12)
+#define STM32_DMA_CCR_PL_HIGH (2 << 12)
+#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12)
+#define STM32_DMA_CCR_MEM2MEM BIT(14)
 
 /* The requests for the DMA1/DMA2 controllers are routed through DMAMUX. */
 /* DMAMUX registers */
-#define STM32_DMAMUX_CxCR(x)      REG32(STM32_DMAMUX_BASE + 4 * (x))
-#define STM32_DMAMUX_CSR          REG32(STM32_DMAMUX_BASE + 0x80)
-#define STM32_DMAMUX_CFR          REG32(STM32_DMAMUX_BASE + 0x84)
-#define STM32_DMAMUX_RGxCR(x)     REG32(STM32_DMAMUX_BASE + 0x100 + 4 * (x))
-#define STM32_DMAMUX_RGSR         REG32(STM32_DMAMUX_BASE + 0x140)
-#define STM32_DMAMUX_RGCFR        REG32(STM32_DMAMUX_BASE + 0x144)
+#define STM32_DMAMUX_CxCR(x) REG32(STM32_DMAMUX_BASE + 4 * (x))
+#define STM32_DMAMUX_CSR REG32(STM32_DMAMUX_BASE + 0x80)
+#define STM32_DMAMUX_CFR REG32(STM32_DMAMUX_BASE + 0x84)
+#define STM32_DMAMUX_RGxCR(x) REG32(STM32_DMAMUX_BASE + 0x100 + 4 * (x))
+#define STM32_DMAMUX_RGSR REG32(STM32_DMAMUX_BASE + 0x140)
+#define STM32_DMAMUX_RGCFR REG32(STM32_DMAMUX_BASE + 0x144)
 
 enum dmamux1_request {
 	DMAMUX_REQ_ADC1 = 5,
@@ -1336,93 +1350,41 @@ enum dmamux1_request {
 #define DMAMUX_REQ_UART9_TX DMAMUX_REQ_LPUART1_TX
 
 /* --- CRC --- */
-#define STM32_CRC_DR                REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR32              REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR16              REG16(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR8               REG8(STM32_CRC_BASE + 0x0)
-
-#define STM32_CRC_IDR               REG32(STM32_CRC_BASE + 0x4)
-#define STM32_CRC_CR                REG32(STM32_CRC_BASE + 0x8)
-#define STM32_CRC_INIT              REG32(STM32_CRC_BASE + 0x10)
-#define STM32_CRC_POL               REG32(STM32_CRC_BASE + 0x14)
-
-#define STM32_CRC_CR_RESET          BIT(0)
-#define STM32_CRC_CR_POLYSIZE_32    (0 << 3)
-#define STM32_CRC_CR_POLYSIZE_16    (1 << 3)
-#define STM32_CRC_CR_POLYSIZE_8     (2 << 3)
-#define STM32_CRC_CR_POLYSIZE_7     (3 << 3)
-#define STM32_CRC_CR_REV_IN_BYTE    (1 << 5)
-#define STM32_CRC_CR_REV_IN_HWORD   (2 << 5)
-#define STM32_CRC_CR_REV_IN_WORD    (3 << 5)
-#define STM32_CRC_CR_REV_OUT        BIT(7)
-
+#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0)
+
+#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4)
+#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8)
+#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10)
+#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14)
+
+#define STM32_CRC_CR_RESET BIT(0)
+#define STM32_CRC_CR_POLYSIZE_32 (0 << 3)
+#define STM32_CRC_CR_POLYSIZE_16 (1 << 3)
+#define STM32_CRC_CR_POLYSIZE_8 (2 << 3)
+#define STM32_CRC_CR_POLYSIZE_7 (3 << 3)
+#define STM32_CRC_CR_REV_IN_BYTE (1 << 5)
+#define STM32_CRC_CR_REV_IN_HWORD (2 << 5)
+#define STM32_CRC_CR_REV_IN_WORD (3 << 5)
+#define STM32_CRC_CR_REV_OUT BIT(7)
 
 /* --- USB --- */
-#define STM32_USB_EP(n)            REG16(STM32_USB_FS_BASE + (n) * 4)
-
-#define STM32_USB_CNTR             REG16(STM32_USB_FS_BASE + 0x40)
-
-#define STM32_USB_CNTR_FRES	    BIT(0)
-#define STM32_USB_CNTR_PDWN	    BIT(1)
-#define STM32_USB_CNTR_LP_MODE	    BIT(2)
-#define STM32_USB_CNTR_FSUSP	    BIT(3)
-#define STM32_USB_CNTR_RESUME	    BIT(4)
-#define STM32_USB_CNTR_L1RESUME	    BIT(5)
-#define STM32_USB_CNTR_L1REQM	    BIT(7)
-#define STM32_USB_CNTR_ESOFM	    BIT(8)
-#define STM32_USB_CNTR_SOFM	    BIT(9)
-#define STM32_USB_CNTR_RESETM	    BIT(10)
-#define STM32_USB_CNTR_SUSPM	    BIT(11)
-#define STM32_USB_CNTR_WKUPM	    BIT(12)
-#define STM32_USB_CNTR_ERRM	    BIT(13)
-#define STM32_USB_CNTR_PMAOVRM	    BIT(14)
-#define STM32_USB_CNTR_CTRM	    BIT(15)
-
-#define STM32_USB_ISTR             REG16(STM32_USB_FS_BASE + 0x44)
-
-#define STM32_USB_ISTR_EP_ID_MASK   (0x000f)
-#define STM32_USB_ISTR_DIR	    BIT(4)
-#define STM32_USB_ISTR_L1REQ	    BIT(7)
-#define STM32_USB_ISTR_ESOF	    BIT(8)
-#define STM32_USB_ISTR_SOF	    BIT(9)
-#define STM32_USB_ISTR_RESET	    BIT(10)
-#define STM32_USB_ISTR_SUSP	    BIT(11)
-#define STM32_USB_ISTR_WKUP	    BIT(12)
-#define STM32_USB_ISTR_ERR	    BIT(13)
-#define STM32_USB_ISTR_PMAOVR	    BIT(14)
-#define STM32_USB_ISTR_CTR	    BIT(15)
-
-#define STM32_USB_FNR              REG16(STM32_USB_FS_BASE + 0x48)
-
-#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14)
-#define STM32_USB_FNR_RXDP_RXDM_MASK  (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT)
-
-#define STM32_USB_DADDR            REG16(STM32_USB_FS_BASE + 0x4C)
-#define STM32_USB_BTABLE           REG16(STM32_USB_FS_BASE + 0x50)
-#define STM32_USB_LPMCSR           REG16(STM32_USB_FS_BASE + 0x54)
-#define STM32_USB_BCDR             REG16(STM32_USB_FS_BASE + 0x58)
-
-#define STM32_USB_BCDR_BCDEN	    BIT(0)
-#define STM32_USB_BCDR_DCDEN	    BIT(1)
-#define STM32_USB_BCDR_PDEN	    BIT(2)
-#define STM32_USB_BCDR_SDEN	    BIT(3)
-#define STM32_USB_BCDR_DCDET	    BIT(4)
-#define STM32_USB_BCDR_PDET	    BIT(5)
-#define STM32_USB_BCDR_SDET	    BIT(6)
-#define STM32_USB_BCDR_PS2DET	    BIT(7)
+#define STM32_USB_BCDR_DPPU BIT(15)
 
 /* --- USB Endpoint bit definitions  --- */
-#define EP_MASK     0x0F0F
-#define EP_TX_DTOG  0x0040
-#define EP_TX_MASK  0x0030
+#define EP_MASK 0x0F0F
+#define EP_TX_DTOG 0x0040
+#define EP_TX_MASK 0x0030
 #define EP_TX_VALID 0x0030
-#define EP_TX_NAK   0x0020
+#define EP_TX_NAK 0x0020
 #define EP_TX_STALL 0x0010
 #define EP_TX_DISAB 0x0000
-#define EP_RX_DTOG  0x4000
-#define EP_RX_MASK  0x3000
+#define EP_RX_DTOG 0x4000
+#define EP_RX_MASK 0x3000
 #define EP_RX_VALID 0x3000
-#define EP_RX_NAK   0x2000
+#define EP_RX_NAK 0x2000
 #define EP_RX_STALL 0x1000
 #define EP_RX_DISAB 0x0000
 
@@ -1432,32 +1394,30 @@ enum dmamux1_request {
 #define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID)
 
 #define STM32_TOGGLE_EP(n, mask, val, flags) \
-	STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \
-			^ (val)) | (flags))
+	STM32_USB_EP(n) =                    \
+		(((STM32_USB_EP(n) & (EP_MASK | (mask))) ^ (val)) | (flags))
 
 /* --- TRNG --- */
-#define STM32_RNG_CR                REG32(STM32_RNG_BASE + 0x0)
-#define STM32_RNG_SR                REG32(STM32_RNG_BASE + 0x4)
-#define STM32_RNG_DR                REG32(STM32_RNG_BASE + 0x8)
+#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0)
+#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4)
+#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8)
 
 /* --- RNG CR Bit Definitions --- */
-#define STM32_RNG_CR_RNGEN          BIT(2)
-#define STM32_RNG_CR_IE             BIT(3)
-#define STM32_RNG_CR_CED            BIT(5)
+#define STM32_RNG_CR_RNGEN BIT(2)
+#define STM32_RNG_CR_IE BIT(3)
+#define STM32_RNG_CR_CED BIT(5)
 /* --- RNG SR_DRDY Bit Definitions --- */
-#define STM32_RNG_SR_DRDY           BIT(0)
+#define STM32_RNG_SR_DRDY BIT(0)
 
 /* --- AXI interconnect --- */
 
 /* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */
-#define STM32_AXI_TARG_FN_MOD(x)    REG32(STM32_GPV_BASE + 0x1108 + \
-					  0x1000 * (x))
-#define  WRITE_ISS_OVERRIDE         BIT(1)
-#define  READ_ISS_OVERRIDE          BIT(0)
+#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + 0x1000 * (x))
+#define WRITE_ISS_OVERRIDE BIT(1)
+#define READ_ISS_OVERRIDE BIT(0)
 
 /* --- MISC --- */
-#define STM32_UNIQUE_ID_ADDRESS     REG32_ADDR(STM32_UNIQUE_ID_BASE)
-#define STM32_UNIQUE_ID_LENGTH      (3 * 4)
+#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE)
+#define STM32_UNIQUE_ID_LENGTH (3 * 4)
 
 #endif /* !__ASSEMBLER__ */
-
diff --git a/chip/stm32/registers-stm32h7.h b/chip/stm32/registers-stm32h7.h
index d02aaf1249..f4178d17f0 100644
--- a/chip/stm32/registers-stm32h7.h
+++ b/chip/stm32/registers-stm32h7.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,591 +19,586 @@
 #endif
 
 /* --- IRQ numbers --- */
-#define STM32_IRQ_WWDG             0
-#define STM32_IRQ_PVD              1
-#define STM32_IRQ_TAMPER_STAMP     2
-#define STM32_IRQ_RTC_WAKEUP       3
-#define STM32_IRQ_FLASH            4
-#define STM32_IRQ_RCC              5
-#define STM32_IRQ_EXTI0            6
-#define STM32_IRQ_EXTI1            7
-#define STM32_IRQ_EXTI2            8
-#define STM32_IRQ_EXTI3            9
-#define STM32_IRQ_EXTI4           10
-#define STM32_IRQ_DMA_CHANNEL_1   11
-#define STM32_IRQ_DMA_CHANNEL_2   12
-#define STM32_IRQ_DMA_CHANNEL_3   13
-#define STM32_IRQ_DMA_CHANNEL_4   14
-#define STM32_IRQ_DMA_CHANNEL_5   15
-#define STM32_IRQ_DMA_CHANNEL_6   16
-#define STM32_IRQ_DMA_CHANNEL_7   17
-#define STM32_IRQ_USB_HP          19
-#define STM32_IRQ_USB_LP          20
-
-#define STM32_IRQ_ADC1            18 /* STM32L4 only */
-#define STM32_IRQ_CAN_TX          19 /* STM32F373 only */
-#define STM32_IRQ_USB_LP_CAN_RX   20 /* STM32F373 only */
-#define STM32_IRQ_DAC             21
-#define STM32_IRQ_CAN_RX1         21 /* STM32F373 only */
-
-#define STM32_IRQ_COMP            22
-
-#define STM32_IRQ_CAN_SCE         22 /* STM32F373 only */
-#define STM32_IRQ_EXTI9_5         23
-#define STM32_IRQ_TIM2            28
-#define STM32_IRQ_TIM3            29
-#define STM32_IRQ_TIM4            30
-#define STM32_IRQ_I2C1_EV         31
-#define STM32_IRQ_I2C1_ER         32
-#define STM32_IRQ_I2C2_EV         33
-#define STM32_IRQ_I2C2_ER         34
-#define STM32_IRQ_SPI1            35
-#define STM32_IRQ_SPI2            36
-#define STM32_IRQ_USART1          37
-#define STM32_IRQ_USART2          38
-#define STM32_IRQ_USART3          39
-#define STM32_IRQ_EXTI15_10       40
-#define STM32_IRQ_RTC_ALARM       41
-#define STM32_IRQ_USB_FS_WAKEUP   42 /* STM32L15X */
-#define STM32_IRQ_CEC             42 /* STM32F373 only */
-#define STM32_IRQ_TIM6_BASIC      43 /* STM32L15X only */
-#define STM32_IRQ_TIM12           43 /* STM32F373 only */
-#define STM32_IRQ_TIM7_BASIC      44 /* STM32L15X only */
-#define STM32_IRQ_TIM13           44 /* STM32F373 only */
-#define STM32_IRQ_TIM14           45 /* STM32F373 only */
-#define STM32_IRQ_TIM5            50 /* STM32F373 */
-#define STM32_IRQ_SPI3            51 /* STM32F373 */
-#define STM32_IRQ_USART4          52 /* STM32F446 only */
-#define STM32_IRQ_USART5          53 /* STM32F446 only */
-#define STM32_IRQ_TIM6_DAC        54 /* STM32F373 */
-#define STM32_IRQ_TIM7            55 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL1   56 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL2   57 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL3   58 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL4   59 /* STM32F373 only */
+#define STM32_IRQ_WWDG 0
+#define STM32_IRQ_PVD 1
+#define STM32_IRQ_TAMPER_STAMP 2
+#define STM32_IRQ_RTC_WAKEUP 3
+#define STM32_IRQ_FLASH 4
+#define STM32_IRQ_RCC 5
+#define STM32_IRQ_EXTI0 6
+#define STM32_IRQ_EXTI1 7
+#define STM32_IRQ_EXTI2 8
+#define STM32_IRQ_EXTI3 9
+#define STM32_IRQ_EXTI4 10
+#define STM32_IRQ_DMA_CHANNEL_1 11
+#define STM32_IRQ_DMA_CHANNEL_2 12
+#define STM32_IRQ_DMA_CHANNEL_3 13
+#define STM32_IRQ_DMA_CHANNEL_4 14
+#define STM32_IRQ_DMA_CHANNEL_5 15
+#define STM32_IRQ_DMA_CHANNEL_6 16
+#define STM32_IRQ_DMA_CHANNEL_7 17
+#define STM32_IRQ_USB_HP 19
+#define STM32_IRQ_USB_LP 20
+
+#define STM32_IRQ_ADC1 18 /* STM32L4 only */
+#define STM32_IRQ_CAN_TX 19 /* STM32F373 only */
+#define STM32_IRQ_USB_LP_CAN_RX 20 /* STM32F373 only */
+#define STM32_IRQ_DAC 21
+#define STM32_IRQ_CAN_RX1 21 /* STM32F373 only */
+
+#define STM32_IRQ_COMP 22
+
+#define STM32_IRQ_CAN_SCE 22 /* STM32F373 only */
+#define STM32_IRQ_EXTI9_5 23
+#define STM32_IRQ_TIM2 28
+#define STM32_IRQ_TIM3 29
+#define STM32_IRQ_TIM4 30
+#define STM32_IRQ_I2C1_EV 31
+#define STM32_IRQ_I2C1_ER 32
+#define STM32_IRQ_I2C2_EV 33
+#define STM32_IRQ_I2C2_ER 34
+#define STM32_IRQ_SPI1 35
+#define STM32_IRQ_SPI2 36
+#define STM32_IRQ_USART1 37
+#define STM32_IRQ_USART2 38
+#define STM32_IRQ_USART3 39
+#define STM32_IRQ_EXTI15_10 40
+#define STM32_IRQ_RTC_ALARM 41
+#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X */
+#define STM32_IRQ_CEC 42 /* STM32F373 only */
+#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */
+#define STM32_IRQ_TIM12 43 /* STM32F373 only */
+#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */
+#define STM32_IRQ_TIM13 44 /* STM32F373 only */
+#define STM32_IRQ_TIM14 45 /* STM32F373 only */
+#define STM32_IRQ_TIM5 50 /* STM32F373 */
+#define STM32_IRQ_SPI3 51 /* STM32F373 */
+#define STM32_IRQ_USART4 52 /* STM32F446 only */
+#define STM32_IRQ_USART5 53 /* STM32F446 only */
+#define STM32_IRQ_TIM6_DAC 54 /* STM32F373 */
+#define STM32_IRQ_TIM7 55 /* STM32F373 */
+#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F373 */
+#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F373 */
+#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F373 */
+#define STM32_IRQ_DMA2_CHANNEL4 59 /* STM32F373 only */
 /* if MISC_REMAP bits are set */
-#define STM32_IRQ_DMA2_CHANNEL5   60 /* STM32F373 */
-#define STM32_IRQ_SDADC1          61 /* STM32F373 only */
-#define STM32_IRQ_SDADC2          62 /* STM32F373 only */
-#define STM32_IRQ_SDADC3          63 /* STM32F373 only */
-#define STM32_IRQ_DMA2_CHANNEL6   68 /* STM32L4 only */
-#define STM32_IRQ_DMA2_CHANNEL7   69 /* STM32L4 only */
-#define STM32_IRQ_LPUART          70 /* STM32L4 only */
-#define STM32_IRQ_USART9          70 /* STM32L4 only */
-#define STM32_IRQ_USART6          71 /* STM32F446 only */
-#define STM32_IRQ_I2C3_EV         72 /* STM32F446 only */
-#define STM32_IRQ_I2C3_ER         73 /* STM32F446 only */
-#define STM32_IRQ_USB_WAKEUP      76 /* STM32F373 only */
-#define STM32_IRQ_TIM19           78 /* STM32F373 only */
-#define STM32_IRQ_AES             79 /* STM32L4 only */
-#define STM32_IRQ_RNG             80 /* STM32L4 only */
-#define STM32_IRQ_FPU             81 /* STM32F373 only */
-
-#define STM32_IRQ_LPTIM1         93
-#define STM32_IRQ_TIM15         116
-#define STM32_IRQ_TIM16         117
-#define STM32_IRQ_TIM17         118
-#define STM32_IRQ_LPTIM2        138
-#define STM32_IRQ_LPTIM3        139
-#define STM32_IRQ_LPTIM4        140
-#define STM32_IRQ_LPTIM5        141
+#define STM32_IRQ_DMA2_CHANNEL5 60 /* STM32F373 */
+#define STM32_IRQ_SDADC1 61 /* STM32F373 only */
+#define STM32_IRQ_SDADC2 62 /* STM32F373 only */
+#define STM32_IRQ_SDADC3 63 /* STM32F373 only */
+#define STM32_IRQ_DMA2_CHANNEL6 68 /* STM32L4 only */
+#define STM32_IRQ_DMA2_CHANNEL7 69 /* STM32L4 only */
+#define STM32_IRQ_LPUART 70 /* STM32L4 only */
+#define STM32_IRQ_USART9 70 /* STM32L4 only */
+#define STM32_IRQ_USART6 71 /* STM32F446 only */
+#define STM32_IRQ_I2C3_EV 72 /* STM32F446 only */
+#define STM32_IRQ_I2C3_ER 73 /* STM32F446 only */
+#define STM32_IRQ_USB_WAKEUP 76 /* STM32F373 only */
+#define STM32_IRQ_TIM19 78 /* STM32F373 only */
+#define STM32_IRQ_AES 79 /* STM32L4 only */
+#define STM32_IRQ_RNG 80 /* STM32L4 only */
+#define STM32_IRQ_FPU 81 /* STM32F373 only */
+
+#define STM32_IRQ_LPTIM1 93
+#define STM32_IRQ_TIM15 116
+#define STM32_IRQ_TIM16 117
+#define STM32_IRQ_TIM17 118
+#define STM32_IRQ_LPTIM2 138
+#define STM32_IRQ_LPTIM3 139
+#define STM32_IRQ_LPTIM4 140
+#define STM32_IRQ_LPTIM5 141
 
 /* To simplify code generation, define DMA channel 9..10 */
-#define STM32_IRQ_DMA_CHANNEL_9    STM32_IRQ_DMA2_CHANNEL1
-#define STM32_IRQ_DMA_CHANNEL_10   STM32_IRQ_DMA2_CHANNEL2
-#define STM32_IRQ_DMA_CHANNEL_13   STM32_IRQ_DMA2_CHANNEL6
-#define STM32_IRQ_DMA_CHANNEL_14   STM32_IRQ_DMA2_CHANNEL7
+#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1
+#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2
+#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6
+#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7
 
 /* aliases for easier code sharing */
 #define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV
 #define STM32_IRQ_I2C2 STM32_IRQ_I2C2_EV
 #define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV
 
-
 /*
  * STM32F4 introduces a concept of DMA stream to allow
  * fine allocation of a stream to a channel.
  */
-#define STM32_IRQ_DMA1_STREAM0    11
-#define STM32_IRQ_DMA1_STREAM1    12
-#define STM32_IRQ_DMA1_STREAM2    13
-#define STM32_IRQ_DMA1_STREAM3    14
-#define STM32_IRQ_DMA1_STREAM4    15
-#define STM32_IRQ_DMA1_STREAM5    16
-#define STM32_IRQ_DMA1_STREAM6    17
-#define STM32_IRQ_DMA1_STREAM7    47
-#define STM32_IRQ_DMA2_STREAM0    56
-#define STM32_IRQ_DMA2_STREAM1    57
-#define STM32_IRQ_DMA2_STREAM2    58
-#define STM32_IRQ_DMA2_STREAM3    59
-#define STM32_IRQ_DMA2_STREAM4    60
-#define STM32_IRQ_DMA2_STREAM5    68
-#define STM32_IRQ_DMA2_STREAM6    69
-#define STM32_IRQ_DMA2_STREAM7    70
-
-#define STM32_IRQ_OTG_HS_WKUP     76
-#define STM32_IRQ_OTG_HS_EP1_IN   75
-#define STM32_IRQ_OTG_HS_EP1_OUT  74
-#define STM32_IRQ_OTG_HS          77
-#define STM32_IRQ_OTG_FS          67
-#define STM32_IRQ_OTG_FS_WKUP     42
+#define STM32_IRQ_DMA1_STREAM0 11
+#define STM32_IRQ_DMA1_STREAM1 12
+#define STM32_IRQ_DMA1_STREAM2 13
+#define STM32_IRQ_DMA1_STREAM3 14
+#define STM32_IRQ_DMA1_STREAM4 15
+#define STM32_IRQ_DMA1_STREAM5 16
+#define STM32_IRQ_DMA1_STREAM6 17
+#define STM32_IRQ_DMA1_STREAM7 47
+#define STM32_IRQ_DMA2_STREAM0 56
+#define STM32_IRQ_DMA2_STREAM1 57
+#define STM32_IRQ_DMA2_STREAM2 58
+#define STM32_IRQ_DMA2_STREAM3 59
+#define STM32_IRQ_DMA2_STREAM4 60
+#define STM32_IRQ_DMA2_STREAM5 68
+#define STM32_IRQ_DMA2_STREAM6 69
+#define STM32_IRQ_DMA2_STREAM7 70
+
+#define STM32_IRQ_OTG_HS_WKUP 76
+#define STM32_IRQ_OTG_HS_EP1_IN 75
+#define STM32_IRQ_OTG_HS_EP1_OUT 74
+#define STM32_IRQ_OTG_HS 77
+#define STM32_IRQ_OTG_FS 67
+#define STM32_IRQ_OTG_FS_WKUP 42
 
 /* Peripheral base addresses */
 
-#define STM32_GPV_BASE              0x51000000
-
-#define STM32_DBGMCU_BASE           0x5C001000
-
-#define STM32_BDMA_BASE             0x58025400
-#define STM32_DMA1_BASE             0x40020000
-#define STM32_DMA2_BASE             0x40020400
-#define STM32_DMA2D_BASE            0x52001000
-#define STM32_DMAMUX1_BASE          0x40020800
-#define STM32_DMAMUX2_BASE          0x58025800
-#define STM32_MDMA_BASE             0x52000000
-
-#define STM32_EXTI_BASE             0x58000000
-
-#define STM32_FLASH_REGS_BASE       0x52002000
-
-#define STM32_GPIOA_BASE            0x58020000
-#define STM32_GPIOB_BASE            0x58020400
-#define STM32_GPIOC_BASE            0x58020800
-#define STM32_GPIOD_BASE            0x58020C00
-#define STM32_GPIOE_BASE            0x58021000
-#define STM32_GPIOF_BASE            0x58021400
-#define STM32_GPIOG_BASE            0x58021800
-#define STM32_GPIOH_BASE            0x58021C00
-#define STM32_GPIOI_BASE            0x58022000
-#define STM32_GPIOJ_BASE            0x58022400
-#define STM32_GPIOK_BASE            0x58022800
-
-#define STM32_IWDG_BASE             0x58004800
-
-#define STM32_LPTIM1_BASE           0x40002400
-#define STM32_LPTIM2_BASE           0x58002400
-#define STM32_LPTIM3_BASE           0x58002800
-#define STM32_LPTIM4_BASE           0x58002C00
-#define STM32_LPTIM5_BASE           0x58003000
-
-#define STM32_PWR_BASE              0x58024800
-#define STM32_RCC_BASE              0x58024400
-#define STM32_RNG_BASE              0x48021800
-#define STM32_RTC_BASE              0x58004000
-
-#define STM32_SYSCFG_BASE           0x58000400
-
-#define STM32_SPI1_BASE             0x40013000
-#define STM32_SPI2_BASE             0x40003800
-#define STM32_SPI3_BASE             0x40003c00
-#define STM32_SPI4_BASE             0x40013400
-#define STM32_SPI5_BASE             0x40015000
-
-#define STM32_TIM1_BASE             0x40010000
-#define STM32_TIM2_BASE             0x40000000
-#define STM32_TIM3_BASE             0x40000400
-#define STM32_TIM4_BASE             0x40000800
-#define STM32_TIM5_BASE             0x40000c00
-#define STM32_TIM6_BASE             0x40001000
-#define STM32_TIM7_BASE             0x40001400
-#define STM32_TIM8_BASE             0x40010400
-#define STM32_TIM12_BASE            0x40001800
-#define STM32_TIM13_BASE            0x40001c00
-#define STM32_TIM14_BASE            0x40002000
-#define STM32_TIM15_BASE            0x40014000
-#define STM32_TIM16_BASE            0x40014400
-#define STM32_TIM17_BASE            0x40014800
-
-#define STM32_UNIQUE_ID_BASE        0x1ff1e800
-
-#define STM32_USART1_BASE           0x40011000
-#define STM32_USART2_BASE           0x40004400
-#define STM32_USART3_BASE           0x40004800
-#define STM32_USART4_BASE           0x40004c00
-#define STM32_USART5_BASE           0x40005000
-#define STM32_USART6_BASE           0x40011400
-#define STM32_USART7_BASE           0x40007800
-#define STM32_USART8_BASE           0x40007C00
+#define STM32_GPV_BASE 0x51000000
+
+#define STM32_DBGMCU_BASE 0x5C001000
+
+#define STM32_BDMA_BASE 0x58025400
+#define STM32_DMA1_BASE 0x40020000
+#define STM32_DMA2_BASE 0x40020400
+#define STM32_DMA2D_BASE 0x52001000
+#define STM32_DMAMUX1_BASE 0x40020800
+#define STM32_DMAMUX2_BASE 0x58025800
+#define STM32_MDMA_BASE 0x52000000
+
+#define STM32_EXTI_BASE 0x58000000
+
+#define STM32_FLASH_REGS_BASE 0x52002000
+
+#define STM32_GPIOA_BASE 0x58020000
+#define STM32_GPIOB_BASE 0x58020400
+#define STM32_GPIOC_BASE 0x58020800
+#define STM32_GPIOD_BASE 0x58020C00
+#define STM32_GPIOE_BASE 0x58021000
+#define STM32_GPIOF_BASE 0x58021400
+#define STM32_GPIOG_BASE 0x58021800
+#define STM32_GPIOH_BASE 0x58021C00
+#define STM32_GPIOI_BASE 0x58022000
+#define STM32_GPIOJ_BASE 0x58022400
+#define STM32_GPIOK_BASE 0x58022800
+
+#define STM32_IWDG_BASE 0x58004800
+
+#define STM32_LPTIM1_BASE 0x40002400
+#define STM32_LPTIM2_BASE 0x58002400
+#define STM32_LPTIM3_BASE 0x58002800
+#define STM32_LPTIM4_BASE 0x58002C00
+#define STM32_LPTIM5_BASE 0x58003000
+
+#define STM32_PWR_BASE 0x58024800
+#define STM32_RCC_BASE 0x58024400
+#define STM32_RNG_BASE 0x48021800
+#define STM32_RTC_BASE 0x58004000
+
+#define STM32_SYSCFG_BASE 0x58000400
+
+#define STM32_SPI1_BASE 0x40013000
+#define STM32_SPI2_BASE 0x40003800
+#define STM32_SPI3_BASE 0x40003c00
+#define STM32_SPI4_BASE 0x40013400
+#define STM32_SPI5_BASE 0x40015000
+
+#define STM32_TIM1_BASE 0x40010000
+#define STM32_TIM2_BASE 0x40000000
+#define STM32_TIM3_BASE 0x40000400
+#define STM32_TIM4_BASE 0x40000800
+#define STM32_TIM5_BASE 0x40000c00
+#define STM32_TIM6_BASE 0x40001000
+#define STM32_TIM7_BASE 0x40001400
+#define STM32_TIM8_BASE 0x40010400
+#define STM32_TIM12_BASE 0x40001800
+#define STM32_TIM13_BASE 0x40001c00
+#define STM32_TIM14_BASE 0x40002000
+#define STM32_TIM15_BASE 0x40014000
+#define STM32_TIM16_BASE 0x40014400
+#define STM32_TIM17_BASE 0x40014800
+
+#define STM32_UNIQUE_ID_BASE 0x1ff1e800
+
+#define STM32_USART1_BASE 0x40011000
+#define STM32_USART2_BASE 0x40004400
+#define STM32_USART3_BASE 0x40004800
+#define STM32_USART4_BASE 0x40004c00
+#define STM32_USART5_BASE 0x40005000
+#define STM32_USART6_BASE 0x40011400
+#define STM32_USART7_BASE 0x40007800
+#define STM32_USART8_BASE 0x40007C00
 
 #ifndef __ASSEMBLER__
 
 /* Register definitions */
 
 /* --- USART --- */
-#define STM32_USART_CR1(base)         STM32_USART_REG(base, 0x00)
-#define  STM32_USART_CR1_UE            BIT(0)
-#define  STM32_USART_CR1_UESM          BIT(1)
-#define  STM32_USART_CR1_RE            BIT(2)
-#define  STM32_USART_CR1_TE            BIT(3)
-#define  STM32_USART_CR1_RXNEIE        BIT(5)
-#define  STM32_USART_CR1_TCIE          BIT(6)
-#define  STM32_USART_CR1_TXEIE         BIT(7)
-#define  STM32_USART_CR1_PS            BIT(9)
-#define  STM32_USART_CR1_PCE           BIT(10)
-#define  STM32_USART_CR1_M             BIT(12)
-#define  STM32_USART_CR1_OVER8         BIT(15)
-#define STM32_USART_CR2(base)         STM32_USART_REG(base, 0x04)
-#define  STM32_USART_CR2_SWAP          BIT(15)
-#define STM32_USART_CR3(base)         STM32_USART_REG(base, 0x08)
-#define  STM32_USART_CR3_EIE           BIT(0)
-#define  STM32_USART_CR3_DMAR          BIT(6)
-#define  STM32_USART_CR3_DMAT          BIT(7)
-#define  STM32_USART_CR3_ONEBIT        BIT(11)
-#define  STM32_USART_CR3_OVRDIS        BIT(12)
-#define  STM32_USART_CR3_WUS_START_BIT (2 << 20)
-#define  STM32_USART_CR3_WUFIE         BIT(22)
-#define STM32_USART_BRR(base)         STM32_USART_REG(base, 0x0C)
-#define STM32_USART_GTPR(base)        STM32_USART_REG(base, 0x10)
-#define STM32_USART_RTOR(base)        STM32_USART_REG(base, 0x14)
-#define STM32_USART_RQR(base)         STM32_USART_REG(base, 0x18)
-#define STM32_USART_ISR(base)         STM32_USART_REG(base, 0x1C)
-#define STM32_USART_ICR(base)         STM32_USART_REG(base, 0x20)
-#define  STM32_USART_ICR_ORECF         BIT(3)
-#define  STM32_USART_ICR_TCCF          BIT(6)
-#define STM32_USART_RDR(base)         STM32_USART_REG(base, 0x24)
-#define STM32_USART_TDR(base)         STM32_USART_REG(base, 0x28)
-#define STM32_USART_PRESC(base)       STM32_USART_REG(base, 0x2C)
+#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00)
+#define STM32_USART_CR1_UE BIT(0)
+#define STM32_USART_CR1_UESM BIT(1)
+#define STM32_USART_CR1_RE BIT(2)
+#define STM32_USART_CR1_TE BIT(3)
+#define STM32_USART_CR1_RXNEIE BIT(5)
+#define STM32_USART_CR1_TCIE BIT(6)
+#define STM32_USART_CR1_TXEIE BIT(7)
+#define STM32_USART_CR1_PS BIT(9)
+#define STM32_USART_CR1_PCE BIT(10)
+#define STM32_USART_CR1_M BIT(12)
+#define STM32_USART_CR1_OVER8 BIT(15)
+#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04)
+#define STM32_USART_CR2_SWAP BIT(15)
+#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08)
+#define STM32_USART_CR3_EIE BIT(0)
+#define STM32_USART_CR3_DMAR BIT(6)
+#define STM32_USART_CR3_DMAT BIT(7)
+#define STM32_USART_CR3_ONEBIT BIT(11)
+#define STM32_USART_CR3_OVRDIS BIT(12)
+#define STM32_USART_CR3_WUS_START_BIT (2 << 20)
+#define STM32_USART_CR3_WUFIE BIT(22)
+#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C)
+#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10)
+#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14)
+#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18)
+#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C)
+#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20)
+#define STM32_USART_ICR_ORECF BIT(3)
+#define STM32_USART_ICR_TCCF BIT(6)
+#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24)
+#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28)
+#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C)
 /* register alias */
-#define STM32_USART_SR(base)          STM32_USART_ISR(base)
-#define  STM32_USART_SR_ORE            BIT(3)
-#define  STM32_USART_SR_RXNE           BIT(5)
-#define  STM32_USART_SR_TC             BIT(6)
-#define  STM32_USART_SR_TXE            BIT(7)
+#define STM32_USART_SR(base) STM32_USART_ISR(base)
+#define STM32_USART_SR_ORE BIT(3)
+#define STM32_USART_SR_RXNE BIT(5)
+#define STM32_USART_SR_TC BIT(6)
+#define STM32_USART_SR_TXE BIT(7)
 
 /* --- GPIO --- */
 
-
-#define STM32_GPIO_MODER(b)           REG32((b) + 0x00)
-#define STM32_GPIO_OTYPER(b)          REG16((b) + 0x04)
-#define STM32_GPIO_OSPEEDR(b)         REG32((b) + 0x08)
-#define STM32_GPIO_PUPDR(b)           REG32((b) + 0x0C)
-#define STM32_GPIO_IDR(b)             REG16((b) + 0x10)
-#define STM32_GPIO_ODR(b)             REG16((b) + 0x14)
-#define STM32_GPIO_BSRR(b)            REG32((b) + 0x18)
-#define STM32_GPIO_LCKR(b)            REG32((b) + 0x1C)
-#define STM32_GPIO_AFRL(b)            REG32((b) + 0x20)
-#define STM32_GPIO_AFRH(b)            REG32((b) + 0x24)
-
-#define GPIO_ALT_SYS                 0x0
-#define GPIO_ALT_TIM2                0x1
-#define GPIO_ALT_TIM3_4              0x2
-#define GPIO_ALT_TIM9_11             0x3
-#define GPIO_ALT_I2C                 0x4
-#define GPIO_ALT_SPI                 0x5
-#define GPIO_ALT_SPI3                0x6
-#define GPIO_ALT_USART               0x7
-#define GPIO_ALT_I2C_23              0x9
-#define GPIO_ALT_USB                 0xA
-#define GPIO_ALT_LCD                 0xB
-#define GPIO_ALT_RI                  0xE
-#define GPIO_ALT_EVENTOUT            0xF
+#define STM32_GPIO_MODER(b) REG32((b) + 0x00)
+#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04)
+#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08)
+#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C)
+#define STM32_GPIO_IDR(b) REG16((b) + 0x10)
+#define STM32_GPIO_ODR(b) REG16((b) + 0x14)
+#define STM32_GPIO_BSRR(b) REG32((b) + 0x18)
+#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C)
+#define STM32_GPIO_AFRL(b) REG32((b) + 0x20)
+#define STM32_GPIO_AFRH(b) REG32((b) + 0x24)
+
+#define GPIO_ALT_SYS 0x0
+#define GPIO_ALT_TIM2 0x1
+#define GPIO_ALT_TIM3_4 0x2
+#define GPIO_ALT_TIM9_11 0x3
+#define GPIO_ALT_I2C 0x4
+#define GPIO_ALT_SPI 0x5
+#define GPIO_ALT_SPI3 0x6
+#define GPIO_ALT_USART 0x7
+#define GPIO_ALT_I2C_23 0x9
+#define GPIO_ALT_USB 0xA
+#define GPIO_ALT_LCD 0xB
+#define GPIO_ALT_RI 0xE
+#define GPIO_ALT_EVENTOUT 0xF
 
 /* --- I2C --- */
-#define STM32_I2C_CR1(n)              REG16(stm32_i2c_reg(n, 0x00))
-#define  STM32_I2C_CR1_PE              BIT(0)
-#define  STM32_I2C_CR1_START           BIT(8)
-#define  STM32_I2C_CR1_STOP            BIT(9)
-#define  STM32_I2C_CR1_ACK             BIT(10)
-#define  STM32_I2C_CR1_POS             BIT(11)
-#define  STM32_I2C_CR1_SWRST           BIT(15)
-#define STM32_I2C_CR2(n)              REG16(stm32_i2c_reg(n, 0x04))
-#define  STM32_I2C_CR2_ITERREN         BIT(8)
-#define  STM32_I2C_CR2_ITEVTEN         BIT(9)
-#define  STM32_I2C_CR2_ITBUFEN         BIT(10)
-#define  STM32_I2C_CR2_DMAEN           BIT(11)
-#define  STM32_I2C_CR2_LAST            BIT(12)
-#define STM32_I2C_OAR1(n)             REG16(stm32_i2c_reg(n, 0x08))
-#define  STM32_I2C_OAR1_B14            BIT(14)
-#define STM32_I2C_OAR2(n)             REG16(stm32_i2c_reg(n, 0x0C))
-#define  STM32_I2C_OAR2_ENDUAL         BIT(0)
-#define STM32_I2C_DR(n)               REG16(stm32_i2c_reg(n, 0x10))
-#define STM32_I2C_SR1(n)              REG16(stm32_i2c_reg(n, 0x14))
-#define  STM32_I2C_SR1_SB              BIT(0)
-#define  STM32_I2C_SR1_ADDR            BIT(1)
-#define  STM32_I2C_SR1_BTF             BIT(2)
-#define  STM32_I2C_SR1_STOPF           BIT(4)
-#define  STM32_I2C_SR1_RXNE            BIT(6)
-#define  STM32_I2C_SR1_TXE             BIT(7)
-#define  STM32_I2C_SR1_BERR            BIT(8)
-#define  STM32_I2C_SR1_ARLO            BIT(9)
-#define  STM32_I2C_SR1_AF              BIT(10)
-
-#define STM32_I2C_SR2(n)              REG16(stm32_i2c_reg(n, 0x18))
-#define  STM32_I2C_SR2_BUSY            BIT(1)
-#define  STM32_I2C_SR2_TRA             BIT(2)
-#define  STM32_I2C_SR2_DUALF           BIT(7)
-
-#define STM32_I2C_CCR(n)              REG16(stm32_i2c_reg(n, 0x1C))
-#define  STM32_I2C_CCR_DUTY            BIT(14)
-#define  STM32_I2C_CCR_FM              BIT(15)
-#define STM32_I2C_TRISE(n)            REG16(stm32_i2c_reg(n, 0x20))
-
+#define STM32_I2C_CR1(n) REG16(stm32_i2c_reg(n, 0x00))
+#define STM32_I2C_CR1_PE BIT(0)
+#define STM32_I2C_CR1_START BIT(8)
+#define STM32_I2C_CR1_STOP BIT(9)
+#define STM32_I2C_CR1_ACK BIT(10)
+#define STM32_I2C_CR1_POS BIT(11)
+#define STM32_I2C_CR1_SWRST BIT(15)
+#define STM32_I2C_CR2(n) REG16(stm32_i2c_reg(n, 0x04))
+#define STM32_I2C_CR2_ITERREN BIT(8)
+#define STM32_I2C_CR2_ITEVTEN BIT(9)
+#define STM32_I2C_CR2_ITBUFEN BIT(10)
+#define STM32_I2C_CR2_DMAEN BIT(11)
+#define STM32_I2C_CR2_LAST BIT(12)
+#define STM32_I2C_OAR1(n) REG16(stm32_i2c_reg(n, 0x08))
+#define STM32_I2C_OAR1_B14 BIT(14)
+#define STM32_I2C_OAR2(n) REG16(stm32_i2c_reg(n, 0x0C))
+#define STM32_I2C_OAR2_ENDUAL BIT(0)
+#define STM32_I2C_DR(n) REG16(stm32_i2c_reg(n, 0x10))
+#define STM32_I2C_SR1(n) REG16(stm32_i2c_reg(n, 0x14))
+#define STM32_I2C_SR1_SB BIT(0)
+#define STM32_I2C_SR1_ADDR BIT(1)
+#define STM32_I2C_SR1_BTF BIT(2)
+#define STM32_I2C_SR1_STOPF BIT(4)
+#define STM32_I2C_SR1_RXNE BIT(6)
+#define STM32_I2C_SR1_TXE BIT(7)
+#define STM32_I2C_SR1_BERR BIT(8)
+#define STM32_I2C_SR1_ARLO BIT(9)
+#define STM32_I2C_SR1_AF BIT(10)
+
+#define STM32_I2C_SR2(n) REG16(stm32_i2c_reg(n, 0x18))
+#define STM32_I2C_SR2_BUSY BIT(1)
+#define STM32_I2C_SR2_TRA BIT(2)
+#define STM32_I2C_SR2_DUALF BIT(7)
+
+#define STM32_I2C_CCR(n) REG16(stm32_i2c_reg(n, 0x1C))
+#define STM32_I2C_CCR_DUTY BIT(14)
+#define STM32_I2C_CCR_FM BIT(15)
+#define STM32_I2C_TRISE(n) REG16(stm32_i2c_reg(n, 0x20))
 
 /* --- Power / Reset / Clocks --- */
-#define STM32_PWR_CSR               REG32(STM32_PWR_BASE + 0x04)
-#define STM32_PWR_CR2               REG32(STM32_PWR_BASE + 0x08)
-#define STM32_PWR_CR3               REG32(STM32_PWR_BASE + 0x0C)
-#define  STM32_PWR_CR3_BYPASS        BIT(0)
-#define  STM32_PWR_CR3_LDOEN         BIT(1)
-#define  STM32_PWR_CR3_SCUEN         BIT(2)
-#define  STM32_PWR_CR3_VBE           BIT(8)
-#define  STM32_PWR_CR3_VBRS          BIT(9)
-#define  STM32_PWR_CR3_USB33DEN      BIT(24)
-#define  STM32_PWR_CR3_USBREGEN      BIT(25)
-#define  STM32_PWR_CR3_USB33RDY      BIT(26)
-#define STM32_PWR_CPUCR             REG32(STM32_PWR_BASE + 0x10)
-#define  STM32_PWR_CPUCR_PDDS_D1     BIT(0)
-#define  STM32_PWR_CPUCR_PDDS_D2     BIT(1)
-#define  STM32_PWR_CPUCR_PDDS_D3     BIT(2)
-#define  STM32_PWR_CPUCR_STOPF       BIT(5)
-#define  STM32_PWR_CPUCR_SBF         BIT(6)
-#define  STM32_PWR_CPUCR_SBF_D1      BIT(7)
-#define  STM32_PWR_CPUCR_SBF_D2      BIT(8)
-#define  STM32_PWR_CPUCR_CSSF        BIT(9)
-#define  STM32_PWR_CPUCR_RUN_D3      BIT(11)
-#define STM32_PWR_D3CR              REG32(STM32_PWR_BASE + 0x18)
-#define  STM32_PWR_D3CR_VOS1         (3 << 14)
-#define  STM32_PWR_D3CR_VOS2         (2 << 14)
-#define  STM32_PWR_D3CR_VOS3         (1 << 14)
-#define  STM32_PWR_D3CR_VOSMASK      (3 << 14)
-#define  STM32_PWR_D3CR_VOSRDY       (1 << 13)
-#define STM32_PWR_WKUPCR            REG32(STM32_PWR_BASE + 0x20)
-#define STM32_PWR_WKUPFR            REG32(STM32_PWR_BASE + 0x24)
-#define STM32_PWR_WKUPEPR           REG32(STM32_PWR_BASE + 0x28)
-
-
-#define STM32_RCC_CR                REG32(STM32_RCC_BASE + 0x000)
-#define STM32_RCC_ICSCR             REG32(STM32_RCC_BASE + 0x004)
-#define STM32_RCC_CRRCR             REG32(STM32_RCC_BASE + 0x008)
-#define STM32_RCC_CFGR              REG32(STM32_RCC_BASE + 0x010)
-#define STM32_RCC_D1CFGR            REG32(STM32_RCC_BASE + 0x018)
-#define STM32_RCC_D2CFGR            REG32(STM32_RCC_BASE + 0x01C)
-#define STM32_RCC_D3CFGR            REG32(STM32_RCC_BASE + 0x020)
-#define STM32_RCC_PLLCKSELR         REG32(STM32_RCC_BASE + 0x028)
-#define STM32_RCC_PLLCFGR           REG32(STM32_RCC_BASE + 0x02C)
-#define STM32_RCC_PLL1DIVR          REG32(STM32_RCC_BASE + 0x030)
-#define STM32_RCC_PLL1FRACR         REG32(STM32_RCC_BASE + 0x034)
-#define STM32_RCC_PLL2DIVR          REG32(STM32_RCC_BASE + 0x038)
-#define STM32_RCC_PLL2FRACR         REG32(STM32_RCC_BASE + 0x03C)
-#define STM32_RCC_PLL3DIVR          REG32(STM32_RCC_BASE + 0x040)
-#define STM32_RCC_PLL3FRACR         REG32(STM32_RCC_BASE + 0x044)
-#define STM32_RCC_D1CCIPR           REG32(STM32_RCC_BASE + 0x04C)
-#define STM32_RCC_D2CCIP1R          REG32(STM32_RCC_BASE + 0x050)
-#define STM32_RCC_D2CCIP2R          REG32(STM32_RCC_BASE + 0x054)
-#define STM32_RCC_D3CCIPR           REG32(STM32_RCC_BASE + 0x058)
-#define STM32_RCC_CIER              REG32(STM32_RCC_BASE + 0x060)
-#define STM32_RCC_CIFR              REG32(STM32_RCC_BASE + 0x064)
-#define STM32_RCC_CICR              REG32(STM32_RCC_BASE + 0x068)
-#define STM32_RCC_BDCR              REG32(STM32_RCC_BASE + 0x070)
-#define STM32_RCC_CSR               REG32(STM32_RCC_BASE + 0x074)
-
-#define STM32_RCC_APB2RSTR          REG32(STM32_RCC_BASE + 0x098)
-
-#define STM32_RCC_RSR               REG32(STM32_RCC_BASE + 0x0D0)
-#define STM32_RCC_AHB3ENR           REG32(STM32_RCC_BASE + 0x0D4)
-#define STM32_RCC_AHB1ENR           REG32(STM32_RCC_BASE + 0x0D8)
-#define STM32_RCC_AHB2ENR           REG32(STM32_RCC_BASE + 0x0DC)
-#define STM32_RCC_AHB2ENR_RNGEN     BIT(6)
-#define STM32_RCC_AHB2ENR_HASHEN    BIT(5)
-#define STM32_RCC_AHB2ENR_CRYPTEN   BIT(4)
-#define STM32_RCC_AHB4ENR           REG32(STM32_RCC_BASE + 0x0E0)
-#define STM32_RCC_AHB4ENR_GPIOMASK  0x3ff
-#define STM32_RCC_APB3ENR           REG32(STM32_RCC_BASE + 0x0E4)
-#define STM32_RCC_APB1LENR          REG32(STM32_RCC_BASE + 0x0E8)
-#define STM32_RCC_APB1HENR          REG32(STM32_RCC_BASE + 0x0EC)
-#define STM32_RCC_APB2ENR           REG32(STM32_RCC_BASE + 0x0F0)
-#define STM32_RCC_APB4ENR           REG32(STM32_RCC_BASE + 0x0F4)
-#define STM32_RCC_SYSCFGEN          BIT(1)
-#define STM32_RCC_AHB3LPENR         REG32(STM32_RCC_BASE + 0x0FC)
-#define STM32_RCC_AHB1LPENR         REG32(STM32_RCC_BASE + 0x100)
-#define STM32_RCC_AHB2LPENR         REG32(STM32_RCC_BASE + 0x104)
-#define STM32_RCC_AHB4LPENR         REG32(STM32_RCC_BASE + 0x108)
-#define STM32_RCC_APB3LPENR         REG32(STM32_RCC_BASE + 0x10C)
-#define STM32_RCC_APB1LLPENR        REG32(STM32_RCC_BASE + 0x110)
-#define STM32_RCC_APB1HLPENR        REG32(STM32_RCC_BASE + 0x114)
-#define STM32_RCC_APB2LPENR         REG32(STM32_RCC_BASE + 0x118)
-#define STM32_RCC_APB4LPENR         REG32(STM32_RCC_BASE + 0x11C)
+#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04)
+#define STM32_PWR_CR2 REG32(STM32_PWR_BASE + 0x08)
+#define STM32_PWR_CR3 REG32(STM32_PWR_BASE + 0x0C)
+#define STM32_PWR_CR3_BYPASS BIT(0)
+#define STM32_PWR_CR3_LDOEN BIT(1)
+#define STM32_PWR_CR3_SCUEN BIT(2)
+#define STM32_PWR_CR3_VBE BIT(8)
+#define STM32_PWR_CR3_VBRS BIT(9)
+#define STM32_PWR_CR3_USB33DEN BIT(24)
+#define STM32_PWR_CR3_USBREGEN BIT(25)
+#define STM32_PWR_CR3_USB33RDY BIT(26)
+#define STM32_PWR_CPUCR REG32(STM32_PWR_BASE + 0x10)
+#define STM32_PWR_CPUCR_PDDS_D1 BIT(0)
+#define STM32_PWR_CPUCR_PDDS_D2 BIT(1)
+#define STM32_PWR_CPUCR_PDDS_D3 BIT(2)
+#define STM32_PWR_CPUCR_STOPF BIT(5)
+#define STM32_PWR_CPUCR_SBF BIT(6)
+#define STM32_PWR_CPUCR_SBF_D1 BIT(7)
+#define STM32_PWR_CPUCR_SBF_D2 BIT(8)
+#define STM32_PWR_CPUCR_CSSF BIT(9)
+#define STM32_PWR_CPUCR_RUN_D3 BIT(11)
+#define STM32_PWR_D3CR REG32(STM32_PWR_BASE + 0x18)
+#define STM32_PWR_D3CR_VOS1 (3 << 14)
+#define STM32_PWR_D3CR_VOS2 (2 << 14)
+#define STM32_PWR_D3CR_VOS3 (1 << 14)
+#define STM32_PWR_D3CR_VOSMASK (3 << 14)
+#define STM32_PWR_D3CR_VOSRDY (1 << 13)
+#define STM32_PWR_WKUPCR REG32(STM32_PWR_BASE + 0x20)
+#define STM32_PWR_WKUPFR REG32(STM32_PWR_BASE + 0x24)
+#define STM32_PWR_WKUPEPR REG32(STM32_PWR_BASE + 0x28)
+
+#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x000)
+#define STM32_RCC_ICSCR REG32(STM32_RCC_BASE + 0x004)
+#define STM32_RCC_CRRCR REG32(STM32_RCC_BASE + 0x008)
+#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x010)
+#define STM32_RCC_D1CFGR REG32(STM32_RCC_BASE + 0x018)
+#define STM32_RCC_D2CFGR REG32(STM32_RCC_BASE + 0x01C)
+#define STM32_RCC_D3CFGR REG32(STM32_RCC_BASE + 0x020)
+#define STM32_RCC_PLLCKSELR REG32(STM32_RCC_BASE + 0x028)
+#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x02C)
+#define STM32_RCC_PLL1DIVR REG32(STM32_RCC_BASE + 0x030)
+#define STM32_RCC_PLL1FRACR REG32(STM32_RCC_BASE + 0x034)
+#define STM32_RCC_PLL2DIVR REG32(STM32_RCC_BASE + 0x038)
+#define STM32_RCC_PLL2FRACR REG32(STM32_RCC_BASE + 0x03C)
+#define STM32_RCC_PLL3DIVR REG32(STM32_RCC_BASE + 0x040)
+#define STM32_RCC_PLL3FRACR REG32(STM32_RCC_BASE + 0x044)
+#define STM32_RCC_D1CCIPR REG32(STM32_RCC_BASE + 0x04C)
+#define STM32_RCC_D2CCIP1R REG32(STM32_RCC_BASE + 0x050)
+#define STM32_RCC_D2CCIP2R REG32(STM32_RCC_BASE + 0x054)
+#define STM32_RCC_D3CCIPR REG32(STM32_RCC_BASE + 0x058)
+#define STM32_RCC_CIER REG32(STM32_RCC_BASE + 0x060)
+#define STM32_RCC_CIFR REG32(STM32_RCC_BASE + 0x064)
+#define STM32_RCC_CICR REG32(STM32_RCC_BASE + 0x068)
+#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x070)
+#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x074)
+
+#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x098)
+
+#define STM32_RCC_RSR REG32(STM32_RCC_BASE + 0x0D0)
+#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x0D4)
+#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x0D8)
+#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x0DC)
+#define STM32_RCC_AHB2ENR_RNGEN BIT(6)
+#define STM32_RCC_AHB2ENR_HASHEN BIT(5)
+#define STM32_RCC_AHB2ENR_CRYPTEN BIT(4)
+#define STM32_RCC_AHB4ENR REG32(STM32_RCC_BASE + 0x0E0)
+#define STM32_RCC_AHB4ENR_GPIOMASK 0x3ff
+#define STM32_RCC_APB3ENR REG32(STM32_RCC_BASE + 0x0E4)
+#define STM32_RCC_APB1LENR REG32(STM32_RCC_BASE + 0x0E8)
+#define STM32_RCC_APB1HENR REG32(STM32_RCC_BASE + 0x0EC)
+#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x0F0)
+#define STM32_RCC_APB4ENR REG32(STM32_RCC_BASE + 0x0F4)
+#define STM32_RCC_SYSCFGEN BIT(1)
+#define STM32_RCC_AHB3LPENR REG32(STM32_RCC_BASE + 0x0FC)
+#define STM32_RCC_AHB1LPENR REG32(STM32_RCC_BASE + 0x100)
+#define STM32_RCC_AHB2LPENR REG32(STM32_RCC_BASE + 0x104)
+#define STM32_RCC_AHB4LPENR REG32(STM32_RCC_BASE + 0x108)
+#define STM32_RCC_APB3LPENR REG32(STM32_RCC_BASE + 0x10C)
+#define STM32_RCC_APB1LLPENR REG32(STM32_RCC_BASE + 0x110)
+#define STM32_RCC_APB1HLPENR REG32(STM32_RCC_BASE + 0x114)
+#define STM32_RCC_APB2LPENR REG32(STM32_RCC_BASE + 0x118)
+#define STM32_RCC_APB4LPENR REG32(STM32_RCC_BASE + 0x11C)
 /* Aliases */
-#define STM32_RCC_APB1ENR           STM32_RCC_APB1LENR
-
-#define STM32_RCC_CR_HSION                     BIT(0)
-#define STM32_RCC_CR_HSIRDY                    BIT(2)
-#define STM32_RCC_CR_CSION                     BIT(7)
-#define STM32_RCC_CR_CSIRDY                    BIT(8)
-#define STM32_RCC_CR_HSI48ON                   BIT(12)
-#define STM32_RCC_CR_HSI48RDY                  BIT(13)
-#define STM32_RCC_CR_PLL1ON                    BIT(24)
-#define STM32_RCC_CR_PLL1RDY                   BIT(25)
-#define STM32_RCC_CR_PLL2ON                    BIT(26)
-#define STM32_RCC_CR_PLL2RDY                   BIT(27)
-#define STM32_RCC_CR_PLL3ON                    BIT(28)
-#define STM32_RCC_CR_PLL3RDY                   BIT(29)
-#define STM32_RCC_CFGR_SW_HSI                  (0 << 0)
-#define STM32_RCC_CFGR_SW_CSI                  (1 << 0)
-#define STM32_RCC_CFGR_SW_HSE                  (2 << 0)
-#define STM32_RCC_CFGR_SW_PLL1                 (3 << 0)
-#define STM32_RCC_CFGR_SW_MASK                 (3 << 0)
-#define STM32_RCC_CFGR_SWS_HSI                 (0 << 3)
-#define STM32_RCC_CFGR_SWS_CSI                 (1 << 3)
-#define STM32_RCC_CFGR_SWS_HSE                 (2 << 3)
-#define STM32_RCC_CFGR_SWS_PLL1                (3 << 3)
-#define STM32_RCC_CFGR_SWS_MASK                (3 << 3)
-#define STM32_RCC_D1CFGR_HPRE_DIV1             (0 << 0)
-#define STM32_RCC_D1CFGR_HPRE_DIV2             (8 << 0)
-#define STM32_RCC_D1CFGR_HPRE_DIV4             (9 << 0)
-#define STM32_RCC_D1CFGR_HPRE_DIV8            (10 << 0)
-#define STM32_RCC_D1CFGR_HPRE_DIV16           (11 << 0)
-#define STM32_RCC_D1CFGR_D1PPRE_DIV1           (0 << 4)
-#define STM32_RCC_D1CFGR_D1PPRE_DIV2           (4 << 4)
-#define STM32_RCC_D1CFGR_D1PPRE_DIV4           (5 << 4)
-#define STM32_RCC_D1CFGR_D1PPRE_DIV8           (6 << 4)
-#define STM32_RCC_D1CFGR_D1PPRE_DIV16          (7 << 4)
-#define STM32_RCC_D1CFGR_D1CPRE_DIV1           (0 << 8)
-#define STM32_RCC_D1CFGR_D1CPRE_DIV2           (8 << 8)
-#define STM32_RCC_D1CFGR_D1CPRE_DIV4           (9 << 8)
-#define STM32_RCC_D1CFGR_D1CPRE_DIV8          (10 << 8)
-#define STM32_RCC_D1CFGR_D1CPRE_DIV16         (1BIT(8))
-#define STM32_RCC_PLLCKSEL_PLLSRC_HSI          (0 << 0)
-#define STM32_RCC_PLLCKSEL_PLLSRC_CSI          (1 << 0)
-#define STM32_RCC_PLLCKSEL_PLLSRC_HSE          (2 << 0)
-#define STM32_RCC_PLLCKSEL_PLLSRC_NONE         (3 << 0)
-#define STM32_RCC_PLLCKSEL_PLLSRC_MASK         (3 << 0)
-#define STM32_RCC_PLLCKSEL_DIVM1(m)            ((m) << 4)
-#define STM32_RCC_PLLCKSEL_DIVM2(m)            ((m) << 12)
-#define STM32_RCC_PLLCKSEL_DIVM3(m)            ((m) << 20)
-#define STM32_RCC_PLLCFG_PLL1VCOSEL_FRACEN     BIT(0)
-#define STM32_RCC_PLLCFG_PLL1VCOSEL_WIDE       (0 << 1)
-#define STM32_RCC_PLLCFG_PLL1VCOSEL_MEDIUM     BIT(1)
-#define STM32_RCC_PLLCFG_PLL1RGE_1M_2M         (0 << 2)
-#define STM32_RCC_PLLCFG_PLL1RGE_2M_4M         (1 << 2)
-#define STM32_RCC_PLLCFG_PLL1RGE_4M_8M         (2 << 2)
-#define STM32_RCC_PLLCFG_PLL1RGE_8M_16M        (3 << 2)
-#define STM32_RCC_PLLCFG_DIVP1EN               BIT(16)
-#define STM32_RCC_PLLCFG_DIVQ1EN               BIT(17)
-#define STM32_RCC_PLLCFG_DIVR1EN               BIT(18)
-#define STM32_RCC_PLLDIV_DIVN(n)               (((n) - 1) << 0)
-#define STM32_RCC_PLLDIV_DIVP(p)               (((p) - 1) << 9)
-#define STM32_RCC_PLLDIV_DIVQ(q)               (((q) - 1) << 16)
-#define STM32_RCC_PLLDIV_DIVR(r)               (((r) - 1) << 24)
-#define STM32_RCC_PLLFRAC(n)                   ((n) << 3)
-#define STM32_RCC_D2CCIP1R_SPI123SEL_PLL1Q     (0 << 12)
-#define STM32_RCC_D2CCIP1R_SPI123SEL_PLL2P     (1 << 12)
-#define STM32_RCC_D2CCIP1R_SPI123SEL_PLL3P     (2 << 12)
-#define STM32_RCC_D2CCIP1R_SPI123SEL_I2SCKIN   (3 << 12)
-#define STM32_RCC_D2CCIP1R_SPI123SEL_PERCK     (4 << 12)
-#define STM32_RCC_D2CCIP1R_SPI123SEL_MASK      (7 << 12)
-#define STM32_RCC_D2CCIP1R_SPI45SEL_APB        (0 << 16)
-#define STM32_RCC_D2CCIP1R_SPI45SEL_PLL2Q      (1 << 16)
-#define STM32_RCC_D2CCIP1R_SPI45SEL_PLL3Q      (2 << 16)
-#define STM32_RCC_D2CCIP1R_SPI45SEL_HSI        (3 << 16)
-#define STM32_RCC_D2CCIP1R_SPI45SEL_CSI        (4 << 16)
-#define STM32_RCC_D2CCIP1R_SPI45SEL_HSE        (5 << 16)
-#define STM32_RCC_D2CCIP1R_SPI45SEL_MASK       (7 << 16)
-#define STM32_RCC_D2CCIP2_USART234578SEL_PCLK  (0 << 0)
+#define STM32_RCC_APB1ENR STM32_RCC_APB1LENR
+
+#define STM32_RCC_CR_HSION BIT(0)
+#define STM32_RCC_CR_HSIRDY BIT(2)
+#define STM32_RCC_CR_CSION BIT(7)
+#define STM32_RCC_CR_CSIRDY BIT(8)
+#define STM32_RCC_CR_HSI48ON BIT(12)
+#define STM32_RCC_CR_HSI48RDY BIT(13)
+#define STM32_RCC_CR_PLL1ON BIT(24)
+#define STM32_RCC_CR_PLL1RDY BIT(25)
+#define STM32_RCC_CR_PLL2ON BIT(26)
+#define STM32_RCC_CR_PLL2RDY BIT(27)
+#define STM32_RCC_CR_PLL3ON BIT(28)
+#define STM32_RCC_CR_PLL3RDY BIT(29)
+#define STM32_RCC_CFGR_SW_HSI (0 << 0)
+#define STM32_RCC_CFGR_SW_CSI (1 << 0)
+#define STM32_RCC_CFGR_SW_HSE (2 << 0)
+#define STM32_RCC_CFGR_SW_PLL1 (3 << 0)
+#define STM32_RCC_CFGR_SW_MASK (3 << 0)
+#define STM32_RCC_CFGR_SWS_HSI (0 << 3)
+#define STM32_RCC_CFGR_SWS_CSI (1 << 3)
+#define STM32_RCC_CFGR_SWS_HSE (2 << 3)
+#define STM32_RCC_CFGR_SWS_PLL1 (3 << 3)
+#define STM32_RCC_CFGR_SWS_MASK (3 << 3)
+#define STM32_RCC_D1CFGR_HPRE_DIV1 (0 << 0)
+#define STM32_RCC_D1CFGR_HPRE_DIV2 (8 << 0)
+#define STM32_RCC_D1CFGR_HPRE_DIV4 (9 << 0)
+#define STM32_RCC_D1CFGR_HPRE_DIV8 (10 << 0)
+#define STM32_RCC_D1CFGR_HPRE_DIV16 (11 << 0)
+#define STM32_RCC_D1CFGR_D1PPRE_DIV1 (0 << 4)
+#define STM32_RCC_D1CFGR_D1PPRE_DIV2 (4 << 4)
+#define STM32_RCC_D1CFGR_D1PPRE_DIV4 (5 << 4)
+#define STM32_RCC_D1CFGR_D1PPRE_DIV8 (6 << 4)
+#define STM32_RCC_D1CFGR_D1PPRE_DIV16 (7 << 4)
+#define STM32_RCC_D1CFGR_D1CPRE_DIV1 (0 << 8)
+#define STM32_RCC_D1CFGR_D1CPRE_DIV2 (8 << 8)
+#define STM32_RCC_D1CFGR_D1CPRE_DIV4 (9 << 8)
+#define STM32_RCC_D1CFGR_D1CPRE_DIV8 (10 << 8)
+#define STM32_RCC_D1CFGR_D1CPRE_DIV16 (1BIT(8))
+#define STM32_RCC_PLLCKSEL_PLLSRC_HSI (0 << 0)
+#define STM32_RCC_PLLCKSEL_PLLSRC_CSI (1 << 0)
+#define STM32_RCC_PLLCKSEL_PLLSRC_HSE (2 << 0)
+#define STM32_RCC_PLLCKSEL_PLLSRC_NONE (3 << 0)
+#define STM32_RCC_PLLCKSEL_PLLSRC_MASK (3 << 0)
+#define STM32_RCC_PLLCKSEL_DIVM1(m) ((m) << 4)
+#define STM32_RCC_PLLCKSEL_DIVM2(m) ((m) << 12)
+#define STM32_RCC_PLLCKSEL_DIVM3(m) ((m) << 20)
+#define STM32_RCC_PLLCFG_PLL1VCOSEL_FRACEN BIT(0)
+#define STM32_RCC_PLLCFG_PLL1VCOSEL_WIDE (0 << 1)
+#define STM32_RCC_PLLCFG_PLL1VCOSEL_MEDIUM BIT(1)
+#define STM32_RCC_PLLCFG_PLL1RGE_1M_2M (0 << 2)
+#define STM32_RCC_PLLCFG_PLL1RGE_2M_4M (1 << 2)
+#define STM32_RCC_PLLCFG_PLL1RGE_4M_8M (2 << 2)
+#define STM32_RCC_PLLCFG_PLL1RGE_8M_16M (3 << 2)
+#define STM32_RCC_PLLCFG_DIVP1EN BIT(16)
+#define STM32_RCC_PLLCFG_DIVQ1EN BIT(17)
+#define STM32_RCC_PLLCFG_DIVR1EN BIT(18)
+#define STM32_RCC_PLLDIV_DIVN(n) (((n)-1) << 0)
+#define STM32_RCC_PLLDIV_DIVP(p) (((p)-1) << 9)
+#define STM32_RCC_PLLDIV_DIVQ(q) (((q)-1) << 16)
+#define STM32_RCC_PLLDIV_DIVR(r) (((r)-1) << 24)
+#define STM32_RCC_PLLFRAC(n) ((n) << 3)
+#define STM32_RCC_D2CCIP1R_SPI123SEL_PLL1Q (0 << 12)
+#define STM32_RCC_D2CCIP1R_SPI123SEL_PLL2P (1 << 12)
+#define STM32_RCC_D2CCIP1R_SPI123SEL_PLL3P (2 << 12)
+#define STM32_RCC_D2CCIP1R_SPI123SEL_I2SCKIN (3 << 12)
+#define STM32_RCC_D2CCIP1R_SPI123SEL_PERCK (4 << 12)
+#define STM32_RCC_D2CCIP1R_SPI123SEL_MASK (7 << 12)
+#define STM32_RCC_D2CCIP1R_SPI45SEL_APB (0 << 16)
+#define STM32_RCC_D2CCIP1R_SPI45SEL_PLL2Q (1 << 16)
+#define STM32_RCC_D2CCIP1R_SPI45SEL_PLL3Q (2 << 16)
+#define STM32_RCC_D2CCIP1R_SPI45SEL_HSI (3 << 16)
+#define STM32_RCC_D2CCIP1R_SPI45SEL_CSI (4 << 16)
+#define STM32_RCC_D2CCIP1R_SPI45SEL_HSE (5 << 16)
+#define STM32_RCC_D2CCIP1R_SPI45SEL_MASK (7 << 16)
+#define STM32_RCC_D2CCIP2_USART234578SEL_PCLK (0 << 0)
 #define STM32_RCC_D2CCIP2_USART234578SEL_PLL2Q (1 << 0)
 #define STM32_RCC_D2CCIP2_USART234578SEL_PLL3Q (2 << 0)
-#define STM32_RCC_D2CCIP2_USART234578SEL_HSI   (3 << 0)
-#define STM32_RCC_D2CCIP2_USART234578SEL_CSI   (4 << 0)
-#define STM32_RCC_D2CCIP2_USART234578SEL_LSE   (5 << 0)
-#define STM32_RCC_D2CCIP2_USART234578SEL_MASK  (7 << 0)
-#define STM32_RCC_D2CCIP2_USART16SEL_PCLK      (0 << 3)
-#define STM32_RCC_D2CCIP2_USART16SEL_PLL2Q     (1 << 3)
-#define STM32_RCC_D2CCIP2_USART16SEL_PLL3Q     (2 << 3)
-#define STM32_RCC_D2CCIP2_USART16SEL_HSI       (3 << 3)
-#define STM32_RCC_D2CCIP2_USART16SEL_CSI       (4 << 3)
-#define STM32_RCC_D2CCIP2_USART16SEL_LSE       (5 << 3)
-#define STM32_RCC_D2CCIP2_USART16SEL_MASK      (7 << 3)
-#define STM32_RCC_D2CCIP2_RNGSEL_HSI48         (0 << 8)
-#define STM32_RCC_D2CCIP2_RNGSEL_PLL1Q         (1 << 8)
-#define STM32_RCC_D2CCIP2_RNGSEL_LSE           (2 << 8)
-#define STM32_RCC_D2CCIP2_RNGSEL_LSI           (3 << 8)
-#define STM32_RCC_D2CCIP2_RNGSEL_MASK          (3 << 8)
-#define STM32_RCC_D2CCIP2_LPTIM1SEL_PCLK       (0 << 28)
-#define STM32_RCC_D2CCIP2_LPTIM1SEL_PLL2       (1 << 28)
-#define STM32_RCC_D2CCIP2_LPTIM1SEL_PLL3       (2 << 28)
-#define STM32_RCC_D2CCIP2_LPTIM1SEL_LSE        (3 << 28)
-#define STM32_RCC_D2CCIP2_LPTIM1SEL_LSI        (4 << 28)
-#define STM32_RCC_D2CCIP2_LPTIM1SEL_PER        (5 << 28)
-#define STM32_RCC_D2CCIP2_LPTIM1SEL_MASK       (7 << 28)
-#define STM32_RCC_CSR_LSION                    BIT(0)
-#define STM32_RCC_CSR_LSIRDY                   BIT(1)
-
-#define STM32_SYSCFG_PMCR           REG32(STM32_SYSCFG_BASE + 0x04)
-#define STM32_SYSCFG_EXTICR(n)      REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
+#define STM32_RCC_D2CCIP2_USART234578SEL_HSI (3 << 0)
+#define STM32_RCC_D2CCIP2_USART234578SEL_CSI (4 << 0)
+#define STM32_RCC_D2CCIP2_USART234578SEL_LSE (5 << 0)
+#define STM32_RCC_D2CCIP2_USART234578SEL_MASK (7 << 0)
+#define STM32_RCC_D2CCIP2_USART16SEL_PCLK (0 << 3)
+#define STM32_RCC_D2CCIP2_USART16SEL_PLL2Q (1 << 3)
+#define STM32_RCC_D2CCIP2_USART16SEL_PLL3Q (2 << 3)
+#define STM32_RCC_D2CCIP2_USART16SEL_HSI (3 << 3)
+#define STM32_RCC_D2CCIP2_USART16SEL_CSI (4 << 3)
+#define STM32_RCC_D2CCIP2_USART16SEL_LSE (5 << 3)
+#define STM32_RCC_D2CCIP2_USART16SEL_MASK (7 << 3)
+#define STM32_RCC_D2CCIP2_RNGSEL_HSI48 (0 << 8)
+#define STM32_RCC_D2CCIP2_RNGSEL_PLL1Q (1 << 8)
+#define STM32_RCC_D2CCIP2_RNGSEL_LSE (2 << 8)
+#define STM32_RCC_D2CCIP2_RNGSEL_LSI (3 << 8)
+#define STM32_RCC_D2CCIP2_RNGSEL_MASK (3 << 8)
+#define STM32_RCC_D2CCIP2_LPTIM1SEL_PCLK (0 << 28)
+#define STM32_RCC_D2CCIP2_LPTIM1SEL_PLL2 (1 << 28)
+#define STM32_RCC_D2CCIP2_LPTIM1SEL_PLL3 (2 << 28)
+#define STM32_RCC_D2CCIP2_LPTIM1SEL_LSE (3 << 28)
+#define STM32_RCC_D2CCIP2_LPTIM1SEL_LSI (4 << 28)
+#define STM32_RCC_D2CCIP2_LPTIM1SEL_PER (5 << 28)
+#define STM32_RCC_D2CCIP2_LPTIM1SEL_MASK (7 << 28)
+#define STM32_RCC_CSR_LSION BIT(0)
+#define STM32_RCC_CSR_LSIRDY BIT(1)
+
+#define STM32_SYSCFG_PMCR REG32(STM32_SYSCFG_BASE + 0x04)
+#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
 
 /* Peripheral bits for APB1ENR regs */
-#define STM32_RCC_PB1_LPTIM1            BIT(9)
+#define STM32_RCC_PB1_LPTIM1 BIT(9)
 
 /* Peripheral bits for APB2ENR regs */
-#define STM32_RCC_PB2_TIM1              BIT(0)
-#define STM32_RCC_PB2_TIM2              BIT(1)
-#define STM32_RCC_PB2_USART1            BIT(4)
-#define STM32_RCC_PB2_SPI1              BIT(12)
-#define STM32_RCC_PB2_SPI4              BIT(13)
-#define STM32_RCC_PB2_TIM15             BIT(16)
-#define STM32_RCC_PB2_TIM16             BIT(17)
-#define STM32_RCC_PB2_TIM17             BIT(18)
+#define STM32_RCC_PB2_TIM1 BIT(0)
+#define STM32_RCC_PB2_TIM2 BIT(1)
+#define STM32_RCC_PB2_USART1 BIT(4)
+#define STM32_RCC_PB2_SPI1 BIT(12)
+#define STM32_RCC_PB2_SPI4 BIT(13)
+#define STM32_RCC_PB2_TIM15 BIT(16)
+#define STM32_RCC_PB2_TIM16 BIT(17)
+#define STM32_RCC_PB2_TIM17 BIT(18)
 
 /* Peripheral bits for AHB1/2/3/4ENR regs */
-#define STM32_RCC_HB1_DMA1              BIT(0)
-#define STM32_RCC_HB1_DMA2              BIT(1)
-#define STM32_RCC_HB3_MDMA              BIT(0)
-#define STM32_RCC_HB4_BDMA              BIT(21)
-
+#define STM32_RCC_HB1_DMA1 BIT(0)
+#define STM32_RCC_HB1_DMA2 BIT(1)
+#define STM32_RCC_HB3_MDMA BIT(0)
+#define STM32_RCC_HB4_BDMA BIT(21)
 
 /* Peripheral bits for RCC_APB/AHB and DBGMCU regs */
-#define STM32_RCC_PB2_USART1           BIT(4)
+#define STM32_RCC_PB2_USART1 BIT(4)
 
 /* Reset causes definitions */
 #define STM32_RCC_RESET_CAUSE STM32_RCC_RSR
-#define  RESET_CAUSE_WDG                (BIT(28)|BIT(26))
-#define  RESET_CAUSE_SFT                BIT(24)
-#define  RESET_CAUSE_POR                BIT(23)
-#define  RESET_CAUSE_PIN                BIT(22)
-#define  RESET_CAUSE_OTHER              (BIT(31)|BIT(30)|BIT(29)|BIT(28)| \
-					 BIT(27)|BIT(26)|BIT(25)|BIT(24)| \
-					 BIT(23)|BIT(22)|BIT(21)|BIT(20)| \
-					 BIT(19)|BIT(18)|BIT(17))
-#define  RESET_CAUSE_RMVF               BIT(16)
+#define RESET_CAUSE_WDG (BIT(28) | BIT(26))
+#define RESET_CAUSE_SFT BIT(24)
+#define RESET_CAUSE_POR BIT(23)
+#define RESET_CAUSE_PIN BIT(22)
+#define RESET_CAUSE_OTHER                                                      \
+	(BIT(31) | BIT(30) | BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25) | \
+	 BIT(24) | BIT(23) | BIT(22) | BIT(21) | BIT(20) | BIT(19) | BIT(18) | \
+	 BIT(17))
+#define RESET_CAUSE_RMVF BIT(16)
 
 /* Power cause in PWR CPUCR register (Standby&Stop modes) */
 #define STM32_PWR_RESET_CAUSE STM32_PWR_CPUCR
 #define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CPUCR
-#define  RESET_CAUSE_SBF                BIT(6)
-#define  RESET_CAUSE_SBF_CLR            BIT(9)
+#define RESET_CAUSE_SBF BIT(6)
+#define RESET_CAUSE_SBF_CLR BIT(9)
 
 /* --- Watchdogs --- */
 
 /* --- Real-Time Clock --- */
-#define STM32_RTC_TR                REG32(STM32_RTC_BASE + 0x00)
-#define STM32_RTC_DR                REG32(STM32_RTC_BASE + 0x04)
-#define STM32_RTC_CR                REG32(STM32_RTC_BASE + 0x08)
-#define  STM32_RTC_CR_BYPSHAD        BIT(5)
-#define  STM32_RTC_CR_ALRAE          BIT(8)
-#define  STM32_RTC_CR_ALRAIE         BIT(12)
-#define STM32_RTC_ISR               REG32(STM32_RTC_BASE + 0x0C)
-#define  STM32_RTC_ISR_ALRAWF        BIT(0)
-#define  STM32_RTC_ISR_RSF           BIT(5)
-#define  STM32_RTC_ISR_INITF         BIT(6)
-#define  STM32_RTC_ISR_INIT          BIT(7)
-#define  STM32_RTC_ISR_ALRAF         BIT(8)
-#define STM32_RTC_PRER              REG32(STM32_RTC_BASE + 0x10)
-#define  STM32_RTC_PRER_A_MASK       (0x7f << 16)
-#define  STM32_RTC_PRER_S_MASK       (0x7fff << 0)
-#define STM32_RTC_WUTR              REG32(STM32_RTC_BASE + 0x14)
-#define STM32_RTC_CALIBR            REG32(STM32_RTC_BASE + 0x18)
-#define STM32_RTC_ALRMAR            REG32(STM32_RTC_BASE + 0x1C)
-#define STM32_RTC_ALRMBR            REG32(STM32_RTC_BASE + 0x20)
-#define STM32_RTC_WPR               REG32(STM32_RTC_BASE + 0x24)
-#define STM32_RTC_SSR               REG32(STM32_RTC_BASE + 0x28)
-#define STM32_RTC_TSTR              REG32(STM32_RTC_BASE + 0x30)
-#define STM32_RTC_TSDR              REG32(STM32_RTC_BASE + 0x34)
-#define STM32_RTC_TAFCR             REG32(STM32_RTC_BASE + 0x40)
-#define STM32_RTC_ALRMASSR          REG32(STM32_RTC_BASE + 0x44)
-#define STM32_RTC_BACKUP(n)         REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
-
-#define STM32_BKP_DATA(n)           STM32_RTC_BACKUP(n)
-#define STM32_BKP_BYTES             128
+#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00)
+#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04)
+#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08)
+#define STM32_RTC_CR_BYPSHAD BIT(5)
+#define STM32_RTC_CR_ALRAE BIT(8)
+#define STM32_RTC_CR_ALRAIE BIT(12)
+#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C)
+#define STM32_RTC_ISR_ALRAWF BIT(0)
+#define STM32_RTC_ISR_RSF BIT(5)
+#define STM32_RTC_ISR_INITF BIT(6)
+#define STM32_RTC_ISR_INIT BIT(7)
+#define STM32_RTC_ISR_ALRAF BIT(8)
+#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10)
+#define STM32_RTC_PRER_A_MASK (0x7f << 16)
+#define STM32_RTC_PRER_S_MASK (0x7fff << 0)
+#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14)
+#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18)
+#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C)
+#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20)
+#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24)
+#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28)
+#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30)
+#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34)
+#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40)
+#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44)
+#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
+
+#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n)
+#define STM32_BKP_BYTES 128
 
 /* --- SPI --- */
 
@@ -634,163 +629,160 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
 #define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE)
 #define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE)
 
-#define STM32_SPI_CR1_SPE                      BIT(0)
-#define STM32_SPI_CR1_CSTART                   BIT(9)
-#define STM32_SPI_CR1_SSI                      BIT(12)
-#define STM32_SPI_CR1_DIV(div)                 ((div) << 28)
-#define STM32_SPI_CFG1_DATASIZE(n)             (((n) - 1) << 0)
-#define STM32_SPI_CFG1_FTHLV(n)                (((n) - 1) << 5)
-#define STM32_SPI_CFG1_UDRCFG_CONST            (0 << 9)
-#define STM32_SPI_CFG1_UDRCFG_LAST_RX          (1 << 9)
-#define STM32_SPI_CFG1_UDRCFG_LAST_TX          (2 << 9)
-#define STM32_SPI_CFG1_UDRDET_BEGIN_FRM        (0 << 11)
-#define STM32_SPI_CFG1_UDRDET_END_FRM          (1 << 11)
-#define STM32_SPI_CFG1_UDRDET_BEGIN_SS         (2 << 11)
-#define STM32_SPI_CFG1_RXDMAEN                 BIT(14)
-#define STM32_SPI_CFG1_TXDMAEN                 BIT(15)
-#define STM32_SPI_CFG1_CRCSIZE(n)              (((n) - 1) << 16)
-#define  STM32_SPI_CFG2_MSTR                   BIT(22)
-#define  STM32_SPI_CFG2_SSM                    BIT(26)
-#define  STM32_SPI_CFG2_AFCNTR                 BIT(31)
-
-#define STM32_SPI_SR_RXNE                      BIT(0)
-#define STM32_SPI_SR_UDR                       BIT(5)
-#define STM32_SPI_SR_FRLVL                     (3 << 13)
-#define STM32_SPI_SR_TXC                       BIT(12)
+#define STM32_SPI_CR1_SPE BIT(0)
+#define STM32_SPI_CR1_CSTART BIT(9)
+#define STM32_SPI_CR1_SSI BIT(12)
+#define STM32_SPI_CR1_DIV(div) ((div) << 28)
+#define STM32_SPI_CFG1_DATASIZE(n) (((n)-1) << 0)
+#define STM32_SPI_CFG1_FTHLV(n) (((n)-1) << 5)
+#define STM32_SPI_CFG1_UDRCFG_CONST (0 << 9)
+#define STM32_SPI_CFG1_UDRCFG_LAST_RX (1 << 9)
+#define STM32_SPI_CFG1_UDRCFG_LAST_TX (2 << 9)
+#define STM32_SPI_CFG1_UDRDET_BEGIN_FRM (0 << 11)
+#define STM32_SPI_CFG1_UDRDET_END_FRM (1 << 11)
+#define STM32_SPI_CFG1_UDRDET_BEGIN_SS (2 << 11)
+#define STM32_SPI_CFG1_RXDMAEN BIT(14)
+#define STM32_SPI_CFG1_TXDMAEN BIT(15)
+#define STM32_SPI_CFG1_CRCSIZE(n) (((n)-1) << 16)
+#define STM32_SPI_CFG2_MSTR BIT(22)
+#define STM32_SPI_CFG2_SSM BIT(26)
+#define STM32_SPI_CFG2_AFCNTR BIT(31)
+
+#define STM32_SPI_SR_RXNE BIT(0)
+#define STM32_SPI_SR_UDR BIT(5)
+#define STM32_SPI_SR_FRLVL (3 << 13)
+#define STM32_SPI_SR_TXC BIT(12)
 
 /* --- Debug --- */
-#define STM32_DBGMCU_APB3FZ         REG32(STM32_DBGMCU_BASE + 0x34)
-#define STM32_DBGMCU_APB1LFZ        REG32(STM32_DBGMCU_BASE + 0x3C)
-#define STM32_DBGMCU_APB1HFZ        REG32(STM32_DBGMCU_BASE + 0x44)
-#define STM32_DBGMCU_APB2FZ         REG32(STM32_DBGMCU_BASE + 0x4C)
-#define STM32_DBGMCU_APB4FZ         REG32(STM32_DBGMCU_BASE + 0x54)
+#define STM32_DBGMCU_APB3FZ REG32(STM32_DBGMCU_BASE + 0x34)
+#define STM32_DBGMCU_APB1LFZ REG32(STM32_DBGMCU_BASE + 0x3C)
+#define STM32_DBGMCU_APB1HFZ REG32(STM32_DBGMCU_BASE + 0x44)
+#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x4C)
+#define STM32_DBGMCU_APB4FZ REG32(STM32_DBGMCU_BASE + 0x54)
 /* Alias */
-#define STM32_DBGMCU_APB1FZ         STM32_DBGMCU_APB1LFZ
+#define STM32_DBGMCU_APB1FZ STM32_DBGMCU_APB1LFZ
 
 /* --- Flash --- */
-#define STM32_FLASH_REG(bank, offset)     REG32(((bank) ? 0x100 : 0) + \
-					  STM32_FLASH_REGS_BASE + (offset))
+#define STM32_FLASH_REG(bank, offset) \
+	REG32(((bank) ? 0x100 : 0) + STM32_FLASH_REGS_BASE + (offset))
 
-#define STM32_FLASH_ACR(bank)             STM32_FLASH_REG(bank, 0x00)
+#define STM32_FLASH_ACR(bank) STM32_FLASH_REG(bank, 0x00)
 #define STM32_FLASH_ACR_LATENCY_SHIFT (0)
-#define STM32_FLASH_ACR_LATENCY_MASK  (7 << STM32_FLASH_ACR_LATENCY_SHIFT)
-#define STM32_FLASH_ACR_WRHIGHFREQ_85MHZ  (0 << 4)
+#define STM32_FLASH_ACR_LATENCY_MASK (7 << STM32_FLASH_ACR_LATENCY_SHIFT)
+#define STM32_FLASH_ACR_WRHIGHFREQ_85MHZ (0 << 4)
 #define STM32_FLASH_ACR_WRHIGHFREQ_185MHZ (1 << 4)
 #define STM32_FLASH_ACR_WRHIGHFREQ_285MHZ (2 << 4)
 #define STM32_FLASH_ACR_WRHIGHFREQ_385MHZ (3 << 4)
 
-#define STM32_FLASH_KEYR(bank)            STM32_FLASH_REG(bank, 0x04)
-#define  FLASH_KEYR_KEY1                   0x45670123
-#define  FLASH_KEYR_KEY2                   0xCDEF89AB
-#define STM32_FLASH_OPTKEYR(bank)         STM32_FLASH_REG(bank, 0x08)
-#define  FLASH_OPTKEYR_KEY1                0x08192A3B
-#define  FLASH_OPTKEYR_KEY2                0x4C5D6E7F
-#define STM32_FLASH_CR(bank)              STM32_FLASH_REG(bank, 0x0C)
-#define  FLASH_CR_LOCK                     BIT(0)
-#define  FLASH_CR_PG                       BIT(1)
-#define  FLASH_CR_SER                      BIT(2)
-#define  FLASH_CR_BER                      BIT(3)
-#define  FLASH_CR_PSIZE_BYTE               (0 << 4)
-#define  FLASH_CR_PSIZE_HWORD              (1 << 4)
-#define  FLASH_CR_PSIZE_WORD               (2 << 4)
-#define  FLASH_CR_PSIZE_DWORD              (3 << 4)
-#define  FLASH_CR_PSIZE_MASK               (3 << 4)
-#define  FLASH_CR_FW                       BIT(6)
-#define  FLASH_CR_STRT                     BIT(7)
-#define  FLASH_CR_SNB(sec)                 (((sec) & 0x7) << 8)
-#define  FLASH_CR_SNB_MASK                FLASH_CR_SNB(0x7)
-#define STM32_FLASH_SR(bank)              STM32_FLASH_REG(bank, 0x10)
-#define  FLASH_SR_BUSY                     BIT(0)
-#define  FLASH_SR_WBNE                     BIT(1)
-#define  FLASH_SR_QW                       BIT(2)
-#define  FLASH_SR_CRC_BUSY                 BIT(3)
-#define  FLASH_SR_EOP                      BIT(16)
-#define  FLASH_SR_WRPERR                   BIT(17)
-#define  FLASH_SR_PGSERR                   BIT(18)
-#define  FLASH_SR_STRBERR                  BIT(19)
-#define  FLASH_SR_INCERR                   BIT(21)
-#define  FLASH_SR_OPERR                    BIT(22)
-#define  FLASH_SR_RDPERR                   BIT(23)
-#define  FLASH_SR_RDSERR                   BIT(24)
-#define  FLASH_SR_SNECCERR                 BIT(25)
-#define  FLASH_SR_DBECCERR                 BIT(26)
-#define  FLASH_SR_CRCEND                   BIT(27)
-#define STM32_FLASH_CCR(bank)             STM32_FLASH_REG(bank, 0x14)
-#define  FLASH_CCR_ERR_MASK              (FLASH_SR_WRPERR | FLASH_SR_PGSERR \
-					| FLASH_SR_STRBERR | FLASH_SR_INCERR \
-					| FLASH_SR_OPERR | FLASH_SR_RDPERR \
-					| FLASH_SR_RDSERR | FLASH_SR_SNECCERR \
-					| FLASH_SR_DBECCERR)
-#define STM32_FLASH_OPTCR(bank)           STM32_FLASH_REG(bank, 0x18)
-#define  FLASH_OPTCR_OPTLOCK              BIT(0)
-#define  FLASH_OPTCR_OPTSTART             BIT(1)
-#define STM32_FLASH_OPTSR_CUR(bank)       STM32_FLASH_REG(bank, 0x1C)
-#define STM32_FLASH_OPTSR_PRG(bank)       STM32_FLASH_REG(bank, 0x20)
-#define  FLASH_OPTSR_BUSY                 BIT(0)   /* only in OPTSR_CUR */
-#define  FLASH_OPTSR_RDP_MASK             (0xFF << 8)
-#define  FLASH_OPTSR_RDP_LEVEL_0          (0xAA << 8)
+#define STM32_FLASH_KEYR(bank) STM32_FLASH_REG(bank, 0x04)
+#define FLASH_KEYR_KEY1 0x45670123
+#define FLASH_KEYR_KEY2 0xCDEF89AB
+#define STM32_FLASH_OPTKEYR(bank) STM32_FLASH_REG(bank, 0x08)
+#define FLASH_OPTKEYR_KEY1 0x08192A3B
+#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F
+#define STM32_FLASH_CR(bank) STM32_FLASH_REG(bank, 0x0C)
+#define FLASH_CR_LOCK BIT(0)
+#define FLASH_CR_PG BIT(1)
+#define FLASH_CR_SER BIT(2)
+#define FLASH_CR_BER BIT(3)
+#define FLASH_CR_PSIZE_BYTE (0 << 4)
+#define FLASH_CR_PSIZE_HWORD (1 << 4)
+#define FLASH_CR_PSIZE_WORD (2 << 4)
+#define FLASH_CR_PSIZE_DWORD (3 << 4)
+#define FLASH_CR_PSIZE_MASK (3 << 4)
+#define FLASH_CR_FW BIT(6)
+#define FLASH_CR_STRT BIT(7)
+#define FLASH_CR_SNB(sec) (((sec)&0x7) << 8)
+#define FLASH_CR_SNB_MASK FLASH_CR_SNB(0x7)
+#define STM32_FLASH_SR(bank) STM32_FLASH_REG(bank, 0x10)
+#define FLASH_SR_BUSY BIT(0)
+#define FLASH_SR_WBNE BIT(1)
+#define FLASH_SR_QW BIT(2)
+#define FLASH_SR_CRC_BUSY BIT(3)
+#define FLASH_SR_EOP BIT(16)
+#define FLASH_SR_WRPERR BIT(17)
+#define FLASH_SR_PGSERR BIT(18)
+#define FLASH_SR_STRBERR BIT(19)
+#define FLASH_SR_INCERR BIT(21)
+#define FLASH_SR_OPERR BIT(22)
+#define FLASH_SR_RDPERR BIT(23)
+#define FLASH_SR_RDSERR BIT(24)
+#define FLASH_SR_SNECCERR BIT(25)
+#define FLASH_SR_DBECCERR BIT(26)
+#define FLASH_SR_CRCEND BIT(27)
+#define STM32_FLASH_CCR(bank) STM32_FLASH_REG(bank, 0x14)
+#define FLASH_CCR_ERR_MASK                                      \
+	(FLASH_SR_WRPERR | FLASH_SR_PGSERR | FLASH_SR_STRBERR | \
+	 FLASH_SR_INCERR | FLASH_SR_OPERR | FLASH_SR_RDPERR |   \
+	 FLASH_SR_RDSERR | FLASH_SR_SNECCERR | FLASH_SR_DBECCERR)
+#define STM32_FLASH_OPTCR(bank) STM32_FLASH_REG(bank, 0x18)
+#define FLASH_OPTCR_OPTLOCK BIT(0)
+#define FLASH_OPTCR_OPTSTART BIT(1)
+#define STM32_FLASH_OPTSR_CUR(bank) STM32_FLASH_REG(bank, 0x1C)
+#define STM32_FLASH_OPTSR_PRG(bank) STM32_FLASH_REG(bank, 0x20)
+#define FLASH_OPTSR_BUSY BIT(0) /* only in OPTSR_CUR */
+#define FLASH_OPTSR_RDP_MASK (0xFF << 8)
+#define FLASH_OPTSR_RDP_LEVEL_0 (0xAA << 8)
 /* RDP Level 1: Anything but 0xAA/0xCC */
-#define  FLASH_OPTSR_RDP_LEVEL_1          (0x00 << 8)
-#define  FLASH_OPTSR_RDP_LEVEL_2          (0xCC << 8)
-#define  FLASH_OPTSR_RSS1                 BIT(26)
-#define  FLASH_OPTSR_RSS2                 BIT(27)
-#define STM32_FLASH_OPTCCR(bank)          STM32_FLASH_REG(bank, 0x24)
-#define STM32_FLASH_PRAR_CUR(bank)        STM32_FLASH_REG(bank, 0x28)
-#define STM32_FLASH_PRAR_PRG(bank)        STM32_FLASH_REG(bank, 0x2C)
-#define STM32_FLASH_SCAR_CUR(bank)        STM32_FLASH_REG(bank, 0x30)
-#define STM32_FLASH_SCAR_PRG(bank)        STM32_FLASH_REG(bank, 0x34)
-#define STM32_FLASH_WPSN_CUR(bank)        STM32_FLASH_REG(bank, 0x38)
-#define STM32_FLASH_WPSN_PRG(bank)        STM32_FLASH_REG(bank, 0x3C)
-#define STM32_FLASH_BOOT_CUR(bank)        STM32_FLASH_REG(bank, 0x40)
-#define STM32_FLASH_BOOT_PRG(bank)        STM32_FLASH_REG(bank, 0x44)
-#define STM32_FLASH_CRC_CR(bank)          STM32_FLASH_REG(bank, 0x50)
-#define STM32_FLASH_CRC_SADDR(bank)       STM32_FLASH_REG(bank, 0x54)
-#define STM32_FLASH_CRC_EADDR(bank)       STM32_FLASH_REG(bank, 0x58)
-#define STM32_FLASH_CRC_DATA(bank)        STM32_FLASH_REG(bank, 0x5C)
-#define STM32_FLASH_ECC_FA(bank)          STM32_FLASH_REG(bank, 0x60)
+#define FLASH_OPTSR_RDP_LEVEL_1 (0x00 << 8)
+#define FLASH_OPTSR_RDP_LEVEL_2 (0xCC << 8)
+#define FLASH_OPTSR_RSS1 BIT(26)
+#define FLASH_OPTSR_RSS2 BIT(27)
+#define STM32_FLASH_OPTCCR(bank) STM32_FLASH_REG(bank, 0x24)
+#define STM32_FLASH_PRAR_CUR(bank) STM32_FLASH_REG(bank, 0x28)
+#define STM32_FLASH_PRAR_PRG(bank) STM32_FLASH_REG(bank, 0x2C)
+#define STM32_FLASH_SCAR_CUR(bank) STM32_FLASH_REG(bank, 0x30)
+#define STM32_FLASH_SCAR_PRG(bank) STM32_FLASH_REG(bank, 0x34)
+#define STM32_FLASH_WPSN_CUR(bank) STM32_FLASH_REG(bank, 0x38)
+#define STM32_FLASH_WPSN_PRG(bank) STM32_FLASH_REG(bank, 0x3C)
+#define STM32_FLASH_BOOT_CUR(bank) STM32_FLASH_REG(bank, 0x40)
+#define STM32_FLASH_BOOT_PRG(bank) STM32_FLASH_REG(bank, 0x44)
+#define STM32_FLASH_CRC_CR(bank) STM32_FLASH_REG(bank, 0x50)
+#define STM32_FLASH_CRC_SADDR(bank) STM32_FLASH_REG(bank, 0x54)
+#define STM32_FLASH_CRC_EADDR(bank) STM32_FLASH_REG(bank, 0x58)
+#define STM32_FLASH_CRC_DATA(bank) STM32_FLASH_REG(bank, 0x5C)
+#define STM32_FLASH_ECC_FA(bank) STM32_FLASH_REG(bank, 0x60)
 
 /* --- External Interrupts --- */
-#define STM32_EXTI_RTSR1            REG32(STM32_EXTI_BASE + 0x00)
-#define STM32_EXTI_FTSR1            REG32(STM32_EXTI_BASE + 0x04)
-#define STM32_EXTI_SWIER1           REG32(STM32_EXTI_BASE + 0x08)
-#define STM32_EXTI_D3PMR1           REG32(STM32_EXTI_BASE + 0x0C)
-#define STM32_EXTI_D3PCR1L          REG32(STM32_EXTI_BASE + 0x10)
-#define STM32_EXTI_D3PCR1H          REG32(STM32_EXTI_BASE + 0x14)
-#define STM32_EXTI_RTSR2            REG32(STM32_EXTI_BASE + 0x20)
-#define STM32_EXTI_FTSR2            REG32(STM32_EXTI_BASE + 0x24)
-#define STM32_EXTI_SWIER2           REG32(STM32_EXTI_BASE + 0x28)
-#define STM32_EXTI_D3PMR2           REG32(STM32_EXTI_BASE + 0x2C)
-#define STM32_EXTI_D3PCR2L          REG32(STM32_EXTI_BASE + 0x30)
-#define STM32_EXTI_D3PCR2H          REG32(STM32_EXTI_BASE + 0x34)
-#define STM32_EXTI_RTSR3            REG32(STM32_EXTI_BASE + 0x40)
-#define STM32_EXTI_FTSR3            REG32(STM32_EXTI_BASE + 0x44)
-#define STM32_EXTI_SWIER3           REG32(STM32_EXTI_BASE + 0x48)
-#define STM32_EXTI_D3PMR3           REG32(STM32_EXTI_BASE + 0x4C)
-#define STM32_EXTI_D3PCR3L          REG32(STM32_EXTI_BASE + 0x50)
-#define STM32_EXTI_D3PCR3H          REG32(STM32_EXTI_BASE + 0x54)
-#define STM32_EXTI_CPUIMR1          REG32(STM32_EXTI_BASE + 0x80)
-#define STM32_EXTI_CPUIER1          REG32(STM32_EXTI_BASE + 0x84)
-#define STM32_EXTI_CPUPR1           REG32(STM32_EXTI_BASE + 0x88)
-#define STM32_EXTI_CPUIMR2          REG32(STM32_EXTI_BASE + 0x90)
-#define STM32_EXTI_CPUIER2          REG32(STM32_EXTI_BASE + 0x94)
-#define STM32_EXTI_CPUPR2           REG32(STM32_EXTI_BASE + 0x98)
-#define STM32_EXTI_CPUIMR3          REG32(STM32_EXTI_BASE + 0xA0)
-#define STM32_EXTI_CPUIER3          REG32(STM32_EXTI_BASE + 0xA4)
-#define STM32_EXTI_CPUPR3           REG32(STM32_EXTI_BASE + 0xA8)
+#define STM32_EXTI_RTSR1 REG32(STM32_EXTI_BASE + 0x00)
+#define STM32_EXTI_FTSR1 REG32(STM32_EXTI_BASE + 0x04)
+#define STM32_EXTI_SWIER1 REG32(STM32_EXTI_BASE + 0x08)
+#define STM32_EXTI_D3PMR1 REG32(STM32_EXTI_BASE + 0x0C)
+#define STM32_EXTI_D3PCR1L REG32(STM32_EXTI_BASE + 0x10)
+#define STM32_EXTI_D3PCR1H REG32(STM32_EXTI_BASE + 0x14)
+#define STM32_EXTI_RTSR2 REG32(STM32_EXTI_BASE + 0x20)
+#define STM32_EXTI_FTSR2 REG32(STM32_EXTI_BASE + 0x24)
+#define STM32_EXTI_SWIER2 REG32(STM32_EXTI_BASE + 0x28)
+#define STM32_EXTI_D3PMR2 REG32(STM32_EXTI_BASE + 0x2C)
+#define STM32_EXTI_D3PCR2L REG32(STM32_EXTI_BASE + 0x30)
+#define STM32_EXTI_D3PCR2H REG32(STM32_EXTI_BASE + 0x34)
+#define STM32_EXTI_RTSR3 REG32(STM32_EXTI_BASE + 0x40)
+#define STM32_EXTI_FTSR3 REG32(STM32_EXTI_BASE + 0x44)
+#define STM32_EXTI_SWIER3 REG32(STM32_EXTI_BASE + 0x48)
+#define STM32_EXTI_D3PMR3 REG32(STM32_EXTI_BASE + 0x4C)
+#define STM32_EXTI_D3PCR3L REG32(STM32_EXTI_BASE + 0x50)
+#define STM32_EXTI_D3PCR3H REG32(STM32_EXTI_BASE + 0x54)
+#define STM32_EXTI_CPUIMR1 REG32(STM32_EXTI_BASE + 0x80)
+#define STM32_EXTI_CPUIER1 REG32(STM32_EXTI_BASE + 0x84)
+#define STM32_EXTI_CPUPR1 REG32(STM32_EXTI_BASE + 0x88)
+#define STM32_EXTI_CPUIMR2 REG32(STM32_EXTI_BASE + 0x90)
+#define STM32_EXTI_CPUIER2 REG32(STM32_EXTI_BASE + 0x94)
+#define STM32_EXTI_CPUPR2 REG32(STM32_EXTI_BASE + 0x98)
+#define STM32_EXTI_CPUIMR3 REG32(STM32_EXTI_BASE + 0xA0)
+#define STM32_EXTI_CPUIER3 REG32(STM32_EXTI_BASE + 0xA4)
+#define STM32_EXTI_CPUPR3 REG32(STM32_EXTI_BASE + 0xA8)
 /* Aliases */
-#define STM32_EXTI_IMR              STM32_EXTI_CPUIMR1
-#define STM32_EXTI_EMR              STM32_EXTI_CPUIMR1
-#define STM32_EXTI_RTSR             STM32_EXTI_RTSR1
-#define STM32_EXTI_FTSR             STM32_EXTI_FTSR1
-#define STM32_EXTI_SWIER            STM32_EXTI_SWIER1
-#define STM32_EXTI_PR               STM32_EXTI_CPUPR1
-
+#define STM32_EXTI_IMR STM32_EXTI_CPUIMR1
+#define STM32_EXTI_EMR STM32_EXTI_CPUIMR1
+#define STM32_EXTI_RTSR STM32_EXTI_RTSR1
+#define STM32_EXTI_FTSR STM32_EXTI_FTSR1
+#define STM32_EXTI_SWIER STM32_EXTI_SWIER1
+#define STM32_EXTI_PR STM32_EXTI_CPUPR1
 
 /* --- ADC --- */
 
 /* --- Comparators --- */
 
-
 /* --- DMA --- */
 /*
  * Available DMA streams, numbered from 0.
@@ -839,7 +831,7 @@ enum dma_channel {
 	STM32_DMAC_FMPI2C4_TX = STM32_DMA1_STREAM5,
 	STM32_DMAC_FMPI2C4_RX = STM32_DMA1_STREAM2,
 
-	/* Legacy naming for spi_master.c */
+	/* Legacy naming for spi_controller.c */
 	STM32_DMAC_SPI1_TX = STM32_DMA2_STREAM3, /* REQ 3 */
 	STM32_DMAC_SPI1_RX = STM32_DMA2_STREAM0, /* REQ 3 */
 	STM32_DMAC_SPI2_TX = STM32_DMA1_STREAM4, /* REQ 0 */
@@ -879,12 +871,12 @@ enum dma_channel {
 
 /* Registers for a single stream of a DMA controller */
 struct stm32_dma_stream {
-	uint32_t	scr;		/* Control */
-	uint32_t	sndtr;		/* Number of data to transfer */
-	uint32_t	spar;		/* Peripheral address */
-	uint32_t	sm0ar;		/* Memory address 0 */
-	uint32_t	sm1ar;		/*  address 1 for double buffer */
-	uint32_t	sfcr;		/* FIFO control */
+	uint32_t scr; /* Control */
+	uint32_t sndtr; /* Number of data to transfer */
+	uint32_t spar; /* Peripheral address */
+	uint32_t sm0ar; /* Memory address 0 */
+	uint32_t sm1ar; /*  address 1 for double buffer */
+	uint32_t sfcr; /* FIFO control */
 };
 
 /* Always use stm32_dma_stream_t so volatile keyword is included! */
@@ -893,12 +885,11 @@ typedef volatile struct stm32_dma_stream stm32_dma_stream_t;
 /* Common code and header file must use this */
 typedef stm32_dma_stream_t dma_chan_t;
 struct stm32_dma_regs {
-	uint32_t	isr[2];
-	uint32_t	ifcr[2];
+	uint32_t isr[2];
+	uint32_t ifcr[2];
 	stm32_dma_stream_t stream[STM32_DMAS_COUNT];
 };
 
-
 /* Always use stm32_dma_regs_t so volatile keyword is included! */
 typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
 
@@ -909,87 +900,85 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
 #define STM32_DMA_REGS(channel) \
 	((channel) < STM32_DMAS_COUNT ? STM32_DMA1_REGS : STM32_DMA2_REGS)
 
-#define STM32_DMA_CCR_EN                BIT(0)
-#define STM32_DMA_CCR_DMEIE             BIT(1)
-#define STM32_DMA_CCR_TEIE              BIT(2)
-#define STM32_DMA_CCR_HTIE              BIT(3)
-#define STM32_DMA_CCR_TCIE              BIT(4)
-#define STM32_DMA_CCR_PFCTRL            BIT(5)
-#define STM32_DMA_CCR_DIR_P2M           (0 << 6)
-#define STM32_DMA_CCR_DIR_M2P           (1 << 6)
-#define STM32_DMA_CCR_DIR_M2M           (2 << 6)
-#define STM32_DMA_CCR_CIRC              BIT(8)
-#define STM32_DMA_CCR_PINC              BIT(9)
-#define STM32_DMA_CCR_MINC              BIT(10)
-#define STM32_DMA_CCR_PSIZE_8_BIT       (0 << 11)
-#define STM32_DMA_CCR_PSIZE_16_BIT      (1 << 11)
-#define STM32_DMA_CCR_PSIZE_32_BIT      (2 << 11)
-#define STM32_DMA_CCR_MSIZE_8_BIT       (0 << 13)
-#define STM32_DMA_CCR_MSIZE_16_BIT      (1 << 13)
-#define STM32_DMA_CCR_MSIZE_32_BIT      (2 << 13)
-#define STM32_DMA_CCR_PINCOS            BIT(15)
-#define STM32_DMA_CCR_PL_LOW            (0 << 16)
-#define STM32_DMA_CCR_PL_MEDIUM         (1 << 16)
-#define STM32_DMA_CCR_PL_HIGH           (2 << 16)
-#define STM32_DMA_CCR_PL_VERY_HIGH      (3 << 16)
-#define STM32_DMA_CCR_DBM               BIT(18)
-#define STM32_DMA_CCR_CT                BIT(19)
-#define STM32_DMA_CCR_PBURST(b_len)     ((((b_len) - 4) / 4) << 21)
-#define STM32_DMA_CCR_MBURST(b_len)     ((((b_len) - 4) / 4) << 21)
-#define STM32_DMA_CCR_CHANNEL_MASK      (0 << 25)
-#define STM32_DMA_CCR_CHANNEL(channel)  (0)
-#define STM32_DMA_CCR_RSVD_MASK         (0xF0100000)
-#define STM32_DMA_SFCR_DMDIS            BIT(2)
-#define STM32_DMA_SFCR_FTH(level)       (((level) - 1) << 0)
-
-
-#define STM32_DMA_CH_LOCAL(channel)     ((channel) % STM32_DMAS_COUNT)
-#define STM32_DMA_CH_LH(channel)        \
-	((STM32_DMA_CH_LOCAL(channel) < 4) ? 0 : 1)
-#define STM32_DMA_CH_OFFSET(channel)    \
+#define STM32_DMA_CCR_EN BIT(0)
+#define STM32_DMA_CCR_DMEIE BIT(1)
+#define STM32_DMA_CCR_TEIE BIT(2)
+#define STM32_DMA_CCR_HTIE BIT(3)
+#define STM32_DMA_CCR_TCIE BIT(4)
+#define STM32_DMA_CCR_PFCTRL BIT(5)
+#define STM32_DMA_CCR_DIR_P2M (0 << 6)
+#define STM32_DMA_CCR_DIR_M2P (1 << 6)
+#define STM32_DMA_CCR_DIR_M2M (2 << 6)
+#define STM32_DMA_CCR_CIRC BIT(8)
+#define STM32_DMA_CCR_PINC BIT(9)
+#define STM32_DMA_CCR_MINC BIT(10)
+#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 11)
+#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 11)
+#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 11)
+#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 13)
+#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 13)
+#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 13)
+#define STM32_DMA_CCR_PINCOS BIT(15)
+#define STM32_DMA_CCR_PL_LOW (0 << 16)
+#define STM32_DMA_CCR_PL_MEDIUM (1 << 16)
+#define STM32_DMA_CCR_PL_HIGH (2 << 16)
+#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 16)
+#define STM32_DMA_CCR_DBM BIT(18)
+#define STM32_DMA_CCR_CT BIT(19)
+#define STM32_DMA_CCR_PBURST(b_len) ((((b_len)-4) / 4) << 21)
+#define STM32_DMA_CCR_MBURST(b_len) ((((b_len)-4) / 4) << 21)
+#define STM32_DMA_CCR_CHANNEL_MASK (0 << 25)
+#define STM32_DMA_CCR_CHANNEL(channel) (0)
+#define STM32_DMA_CCR_RSVD_MASK (0xF0100000)
+#define STM32_DMA_SFCR_DMDIS BIT(2)
+#define STM32_DMA_SFCR_FTH(level) (((level)-1) << 0)
+
+#define STM32_DMA_CH_LOCAL(channel) ((channel) % STM32_DMAS_COUNT)
+#define STM32_DMA_CH_LH(channel) ((STM32_DMA_CH_LOCAL(channel) < 4) ? 0 : 1)
+#define STM32_DMA_CH_OFFSET(channel)               \
 	(((STM32_DMA_CH_LOCAL(channel) % 4) * 6) + \
-	(((STM32_DMA_CH_LOCAL(channel) % 4) >= 2) ? 4 : 0))
+	 (((STM32_DMA_CH_LOCAL(channel) % 4) >= 2) ? 4 : 0))
 #define STM32_DMA_CH_GETBITS(channel, val) \
 	(((val) >> STM32_DMA_CH_OFFSET(channel)) & 0x3f)
-#define STM32_DMA_GET_IFCR(channel)      \
-	(STM32_DMA_CH_GETBITS(channel,   \
-	STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)]))
-#define STM32_DMA_GET_ISR(channel)       \
-	(STM32_DMA_CH_GETBITS(channel,   \
-	STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)]))
-
-#define STM32_DMA_SET_IFCR(channel, val) \
-	(STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] = \
-	(STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] & \
-	~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel)))
-#define STM32_DMA_SET_ISR(channel, val) \
-	(STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] = \
-	(STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] & \
-	~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel)))
-
-#define STM32_DMA_FEIF                  BIT(0)
-#define STM32_DMA_DMEIF                 BIT(2)
-#define STM32_DMA_TEIF                  BIT(3)
-#define STM32_DMA_HTIF                  BIT(4)
-#define STM32_DMA_TCIF                  BIT(5)
-#define STM32_DMA_ALL                   0x3d
-
+#define STM32_DMA_GET_IFCR(channel) \
+	(STM32_DMA_CH_GETBITS(      \
+		channel,            \
+		STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)]))
+#define STM32_DMA_GET_ISR(channel) \
+	(STM32_DMA_CH_GETBITS(     \
+		channel,           \
+		STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)]))
+
+#define STM32_DMA_SET_IFCR(channel, val)                                    \
+	(STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] =          \
+		 (STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] & \
+		  ~(0x3f << STM32_DMA_CH_OFFSET(channel))) |                \
+		 (((val)&0x3f) << STM32_DMA_CH_OFFSET(channel)))
+#define STM32_DMA_SET_ISR(channel, val)                                    \
+	(STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] =          \
+		 (STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] & \
+		  ~(0x3f << STM32_DMA_CH_OFFSET(channel))) |               \
+		 (((val)&0x3f) << STM32_DMA_CH_OFFSET(channel)))
+
+#define STM32_DMA_FEIF BIT(0)
+#define STM32_DMA_DMEIF BIT(2)
+#define STM32_DMA_TEIF BIT(3)
+#define STM32_DMA_HTIF BIT(4)
+#define STM32_DMA_TCIF BIT(5)
+#define STM32_DMA_ALL 0x3d
 
 /* The requests for the DMA1/DMA2 controllers are routed through DMAMUX1. */
 /* DMAMUX1/2 registers */
 #define DMAMUX1 0
 #define DMAMUX2 1
-#define STM32_DMAMUX_BASE(n)        ((n) ? STM32_DMAMUX2_BASE \
-					 : STM32_DMAMUX1_BASE)
-#define STM32_DMAMUX_REG32(n, off)  REG32(STM32_DMAMUX_BASE(n) + (off))
-#define STM2_DMAMUX_CxCR(n, x)      STM32_DMAMUX_REG32(n, 4 * (x))
-#define STM2_DMAMUX_CSR(n)          STM32_DMAMUX_REG32(n, 0x80)
-#define STM2_DMAMUX_CFR(n)          STM32_DMAMUX_REG32(n, 0x84)
-#define STM2_DMAMUX_RGxCR(n, x)     STM32_DMAMUX_REG32(n, 0x100 + 4 * (x))
-#define STM2_DMAMUX_RGSR(n)         STM32_DMAMUX_REG32(n, 0x140)
-#define STM2_DMAMUX_RGCFR(n)        STM32_DMAMUX_REG32(n, 0x144)
+#define STM32_DMAMUX_BASE(n) ((n) ? STM32_DMAMUX2_BASE : STM32_DMAMUX1_BASE)
+#define STM32_DMAMUX_REG32(n, off) REG32(STM32_DMAMUX_BASE(n) + (off))
+#define STM2_DMAMUX_CxCR(n, x) STM32_DMAMUX_REG32(n, 4 * (x))
+#define STM2_DMAMUX_CSR(n) STM32_DMAMUX_REG32(n, 0x80)
+#define STM2_DMAMUX_CFR(n) STM32_DMAMUX_REG32(n, 0x84)
+#define STM2_DMAMUX_RGxCR(n, x) STM32_DMAMUX_REG32(n, 0x100 + 4 * (x))
+#define STM2_DMAMUX_RGSR(n) STM32_DMAMUX_REG32(n, 0x140)
+#define STM2_DMAMUX_RGCFR(n) STM32_DMAMUX_REG32(n, 0x144)
 
 enum dmamux1_request {
 	DMAMUX1_REQ_ADC1 = 9,
@@ -1091,138 +1080,63 @@ enum dmamux1_request {
 };
 
 /* --- CRC --- */
-#define STM32_CRC_DR                REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR32              REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR16              REG16(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR8               REG8(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_IDR               REG32(STM32_CRC_BASE + 0x4)
-#define STM32_CRC_CR                REG32(STM32_CRC_BASE + 0x8)
-#define  STM32_CRC_CR_RESET          BIT(0)
-#define  STM32_CRC_CR_POLYSIZE_32    (0 << 3)
-#define  STM32_CRC_CR_POLYSIZE_16    (1 << 3)
-#define  STM32_CRC_CR_POLYSIZE_8     (2 << 3)
-#define  STM32_CRC_CR_POLYSIZE_7     (3 << 3)
-#define  STM32_CRC_CR_REV_IN_BYTE    (1 << 5)
-#define  STM32_CRC_CR_REV_IN_HWORD   (2 << 5)
-#define  STM32_CRC_CR_REV_IN_WORD    (3 << 5)
-#define  STM32_CRC_CR_REV_OUT        BIT(7)
-#define STM32_CRC_INIT              REG32(STM32_CRC_BASE + 0x10)
-#define STM32_CRC_POL               REG32(STM32_CRC_BASE + 0x14)
+#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4)
+#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8)
+#define STM32_CRC_CR_RESET BIT(0)
+#define STM32_CRC_CR_POLYSIZE_32 (0 << 3)
+#define STM32_CRC_CR_POLYSIZE_16 (1 << 3)
+#define STM32_CRC_CR_POLYSIZE_8 (2 << 3)
+#define STM32_CRC_CR_POLYSIZE_7 (3 << 3)
+#define STM32_CRC_CR_REV_IN_BYTE (1 << 5)
+#define STM32_CRC_CR_REV_IN_HWORD (2 << 5)
+#define STM32_CRC_CR_REV_IN_WORD (3 << 5)
+#define STM32_CRC_CR_REV_OUT BIT(7)
+#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10)
+#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14)
 
 /* --- PMSE --- */
-#define STM32_PMSE_ARCR             REG32(STM32_PMSE_BASE + 0x0)
-#define STM32_PMSE_ACCR             REG32(STM32_PMSE_BASE + 0x4)
-#define STM32_PMSE_CR               REG32(STM32_PMSE_BASE + 0x8)
-#define STM32_PMSE_CRTDR            REG32(STM32_PMSE_BASE + 0x14)
-#define STM32_PMSE_IER              REG32(STM32_PMSE_BASE + 0x18)
-#define STM32_PMSE_SR               REG32(STM32_PMSE_BASE + 0x1c)
-#define STM32_PMSE_IFCR             REG32(STM32_PMSE_BASE + 0x20)
-#define STM32_PMSE_PxPMR(x)         REG32(STM32_PMSE_BASE + 0x2c + (x) * 4)
-#define STM32_PMSE_PAPMR            REG32(STM32_PMSE_BASE + 0x2c)
-#define STM32_PMSE_PBPMR            REG32(STM32_PMSE_BASE + 0x30)
-#define STM32_PMSE_PCPMR            REG32(STM32_PMSE_BASE + 0x34)
-#define STM32_PMSE_PDPMR            REG32(STM32_PMSE_BASE + 0x38)
-#define STM32_PMSE_PEPMR            REG32(STM32_PMSE_BASE + 0x3c)
-#define STM32_PMSE_PFPMR            REG32(STM32_PMSE_BASE + 0x40)
-#define STM32_PMSE_PGPMR            REG32(STM32_PMSE_BASE + 0x44)
-#define STM32_PMSE_PHPMR            REG32(STM32_PMSE_BASE + 0x48)
-#define STM32_PMSE_PIPMR            REG32(STM32_PMSE_BASE + 0x4c)
-#define STM32_PMSE_MRCR             REG32(STM32_PMSE_BASE + 0x100)
-#define STM32_PMSE_MCCR             REG32(STM32_PMSE_BASE + 0x104)
-
-/* --- USB --- */
-#define STM32_USB_EP(n)            REG16(STM32_USB_FS_BASE + (n) * 4)
-
-#define STM32_USB_CNTR             REG16(STM32_USB_FS_BASE + 0x40)
-#define  STM32_USB_CNTR_FRES        BIT(0)
-#define  STM32_USB_CNTR_PDWN        BIT(1)
-#define  STM32_USB_CNTR_LP_MODE     BIT(2)
-#define  STM32_USB_CNTR_FSUSP       BIT(3)
-#define  STM32_USB_CNTR_RESUME      BIT(4)
-#define  STM32_USB_CNTR_L1RESUME    BIT(5)
-#define  STM32_USB_CNTR_L1REQM      BIT(7)
-#define  STM32_USB_CNTR_ESOFM       BIT(8)
-#define  STM32_USB_CNTR_SOFM        BIT(9)
-#define  STM32_USB_CNTR_RESETM      BIT(10)
-#define  STM32_USB_CNTR_SUSPM       BIT(11)
-#define  STM32_USB_CNTR_WKUPM       BIT(12)
-#define  STM32_USB_CNTR_ERRM        BIT(13)
-#define  STM32_USB_CNTR_PMAOVRM     BIT(14)
-#define  STM32_USB_CNTR_CTRM        BIT(15)
-
-#define STM32_USB_ISTR             REG16(STM32_USB_FS_BASE + 0x44)
-#define  STM32_USB_ISTR_EP_ID_MASK  (0x000f)
-#define  STM32_USB_ISTR_DIR         BIT(4)
-#define  STM32_USB_ISTR_L1REQ       BIT(7)
-#define  STM32_USB_ISTR_ESOF        BIT(8)
-#define  STM32_USB_ISTR_SOF         BIT(9)
-#define  STM32_USB_ISTR_RESET       BIT(10)
-#define  STM32_USB_ISTR_SUSP        BIT(11)
-#define  STM32_USB_ISTR_WKUP        BIT(12)
-#define  STM32_USB_ISTR_ERR         BIT(13)
-#define  STM32_USB_ISTR_PMAOVR      BIT(14)
-#define  STM32_USB_ISTR_CTR         BIT(15)
-
-#define STM32_USB_FNR              REG16(STM32_USB_FS_BASE + 0x48)
-
-#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14)
-#define STM32_USB_FNR_RXDP_RXDM_MASK  (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT)
-
-#define STM32_USB_DADDR            REG16(STM32_USB_FS_BASE + 0x4C)
-#define STM32_USB_BTABLE           REG16(STM32_USB_FS_BASE + 0x50)
-#define STM32_USB_LPMCSR           REG16(STM32_USB_FS_BASE + 0x54)
-#define STM32_USB_BCDR             REG16(STM32_USB_FS_BASE + 0x58)
-#define  STM32_USB_BCDR_BCDEN       BIT(0)
-#define  STM32_USB_BCDR_DCDEN       BIT(1)
-#define  STM32_USB_BCDR_PDEN        BIT(2)
-#define  STM32_USB_BCDR_SDEN        BIT(3)
-#define  STM32_USB_BCDR_DCDET       BIT(4)
-#define  STM32_USB_BCDR_PDET        BIT(5)
-#define  STM32_USB_BCDR_SDET        BIT(6)
-#define  STM32_USB_BCDR_PS2DET      BIT(7)
-
-#define EP_MASK     0x0F0F
-#define EP_TX_DTOG  0x0040
-#define EP_TX_MASK  0x0030
-#define EP_TX_VALID 0x0030
-#define EP_TX_NAK   0x0020
-#define EP_TX_STALL 0x0010
-#define EP_TX_DISAB 0x0000
-#define EP_RX_DTOG  0x4000
-#define EP_RX_MASK  0x3000
-#define EP_RX_VALID 0x3000
-#define EP_RX_NAK   0x2000
-#define EP_RX_STALL 0x1000
-#define EP_RX_DISAB 0x0000
-
-#define EP_STATUS_OUT 0x0100
-
-#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK)
-#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID)
-
-#define STM32_TOGGLE_EP(n, mask, val, flags) \
-	STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \
-			^ (val)) | (flags))
+#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0)
+#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4)
+#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8)
+#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14)
+#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18)
+#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c)
+#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20)
+#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x)*4)
+#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c)
+#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30)
+#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34)
+#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38)
+#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c)
+#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40)
+#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44)
+#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48)
+#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c)
+#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100)
+#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104)
 
 /* --- TRNG --- */
-#define STM32_RNG_CR                REG32(STM32_RNG_BASE + 0x0)
-#define  STM32_RNG_CR_RNGEN          BIT(2)
-#define  STM32_RNG_CR_IE             BIT(3)
-#define  STM32_RNG_CR_CED            BIT(5)
-#define STM32_RNG_SR                REG32(STM32_RNG_BASE + 0x4)
-#define  STM32_RNG_SR_DRDY           BIT(0)
-#define STM32_RNG_DR                REG32(STM32_RNG_BASE + 0x8)
+#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0)
+#define STM32_RNG_CR_RNGEN BIT(2)
+#define STM32_RNG_CR_IE BIT(3)
+#define STM32_RNG_CR_CED BIT(5)
+#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4)
+#define STM32_RNG_SR_DRDY BIT(0)
+#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8)
 
 /* --- AXI interconnect --- */
 
 /* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */
-#define STM32_AXI_TARG_FN_MOD(x)    REG32(STM32_GPV_BASE + 0x1108 + \
-					  0x1000 * (x))
-#define  WRITE_ISS_OVERRIDE          BIT(1)
-#define  READ_ISS_OVERRIDE           BIT(0)
+#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + 0x1000 * (x))
+#define WRITE_ISS_OVERRIDE BIT(1)
+#define READ_ISS_OVERRIDE BIT(0)
 
 /* --- MISC --- */
-#define STM32_UNIQUE_ID_ADDRESS     REG32_ADDR(STM32_UNIQUE_ID_BASE)
-#define STM32_UNIQUE_ID_LENGTH      (3 * 4)
+#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE)
+#define STM32_UNIQUE_ID_LENGTH (3 * 4)
 
 #endif /* !__ASSEMBLER__ */
diff --git a/chip/stm32/registers-stm32l.h b/chip/stm32/registers-stm32l.h
index 37b31ac302..57302a9d8d 100644
--- a/chip/stm32/registers-stm32l.h
+++ b/chip/stm32/registers-stm32l.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,401 +20,393 @@
 #endif
 
 /* --- IRQ numbers --- */
-#define STM32_IRQ_WWDG             0
-#define STM32_IRQ_PVD              1
-#define STM32_IRQ_TAMPER_STAMP     2
-#define STM32_IRQ_RTC_WAKEUP       3
-#define STM32_IRQ_FLASH            4
-#define STM32_IRQ_RCC              5
-#define STM32_IRQ_EXTI0            6
-#define STM32_IRQ_EXTI1            7
-#define STM32_IRQ_EXTI2            8
-#define STM32_IRQ_EXTI3            9
-#define STM32_IRQ_EXTI4           10
-#define STM32_IRQ_DMA_CHANNEL_1   11
-#define STM32_IRQ_DMA_CHANNEL_2   12
-#define STM32_IRQ_DMA_CHANNEL_3   13
-#define STM32_IRQ_DMA_CHANNEL_4   14
-#define STM32_IRQ_DMA_CHANNEL_5   15
-#define STM32_IRQ_DMA_CHANNEL_6   16
-#define STM32_IRQ_DMA_CHANNEL_7   17
-#define STM32_IRQ_USB_HP          19
-#define STM32_IRQ_USB_LP          20
-
-#define STM32_IRQ_ADC1            18 /* STM32L4 only */
-#define STM32_IRQ_CAN_TX          19 /* STM32F373 only */
-#define STM32_IRQ_USB_LP_CAN_RX   20 /* STM32F373 only */
-#define STM32_IRQ_DAC             21
-#define STM32_IRQ_CAN_RX1         21 /* STM32F373 only */
-
-#define STM32_IRQ_COMP            22
-
-#define STM32_IRQ_CAN_SCE         22 /* STM32F373 only */
-#define STM32_IRQ_EXTI9_5         23
-#define STM32_IRQ_LCD             24 /* STM32L15X only */
-#define STM32_IRQ_TIM15           24 /* STM32F373 only */
-#define STM32_IRQ_TIM9            25 /* STM32L15X only */
-#define STM32_IRQ_TIM16           25 /* STM32F373 only */
-#define STM32_IRQ_TIM10           26 /* STM32L15X only */
-#define STM32_IRQ_TIM17           26 /* STM32F373 only */
-#define STM32_IRQ_TIM11           27 /* STM32L15X only */
-#define STM32_IRQ_TIM18_DAC2      27 /* STM32F373 only */
-#define STM32_IRQ_TIM2            28
-#define STM32_IRQ_TIM3            29
-#define STM32_IRQ_TIM4            30
-#define STM32_IRQ_I2C1_EV         31
-#define STM32_IRQ_I2C1_ER         32
-#define STM32_IRQ_I2C2_EV         33
-#define STM32_IRQ_I2C2_ER         34
-#define STM32_IRQ_SPI1            35
-#define STM32_IRQ_SPI2            36
-#define STM32_IRQ_USART1          37
-#define STM32_IRQ_USART2          38
-#define STM32_IRQ_USART3          39
-#define STM32_IRQ_EXTI15_10       40
-#define STM32_IRQ_RTC_ALARM       41
-#define STM32_IRQ_USB_FS_WAKEUP   42 /* STM32L15X */
-#define STM32_IRQ_CEC             42 /* STM32F373 only */
-#define STM32_IRQ_TIM6_BASIC      43 /* STM32L15X only */
-#define STM32_IRQ_TIM12           43 /* STM32F373 only */
-#define STM32_IRQ_TIM7_BASIC      44 /* STM32L15X only */
-#define STM32_IRQ_TIM13           44 /* STM32F373 only */
-#define STM32_IRQ_TIM14           45 /* STM32F373 only */
-#define STM32_IRQ_TIM5            50 /* STM32F373 */
-#define STM32_IRQ_SPI3            51 /* STM32F373 */
-#define STM32_IRQ_USART4          52 /* STM32F446 only */
-#define STM32_IRQ_USART5          53 /* STM32F446 only */
-#define STM32_IRQ_TIM6_DAC        54 /* STM32F373 */
-#define STM32_IRQ_TIM7            55 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL1   56 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL2   57 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL3   58 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL4   59 /* STM32F373 only */
+#define STM32_IRQ_WWDG 0
+#define STM32_IRQ_PVD 1
+#define STM32_IRQ_TAMPER_STAMP 2
+#define STM32_IRQ_RTC_WAKEUP 3
+#define STM32_IRQ_FLASH 4
+#define STM32_IRQ_RCC 5
+#define STM32_IRQ_EXTI0 6
+#define STM32_IRQ_EXTI1 7
+#define STM32_IRQ_EXTI2 8
+#define STM32_IRQ_EXTI3 9
+#define STM32_IRQ_EXTI4 10
+#define STM32_IRQ_DMA_CHANNEL_1 11
+#define STM32_IRQ_DMA_CHANNEL_2 12
+#define STM32_IRQ_DMA_CHANNEL_3 13
+#define STM32_IRQ_DMA_CHANNEL_4 14
+#define STM32_IRQ_DMA_CHANNEL_5 15
+#define STM32_IRQ_DMA_CHANNEL_6 16
+#define STM32_IRQ_DMA_CHANNEL_7 17
+#define STM32_IRQ_USB_HP 19
+#define STM32_IRQ_USB_LP 20
+
+#define STM32_IRQ_ADC1 18 /* STM32L4 only */
+#define STM32_IRQ_CAN_TX 19 /* STM32F373 only */
+#define STM32_IRQ_USB_LP_CAN_RX 20 /* STM32F373 only */
+#define STM32_IRQ_DAC 21
+#define STM32_IRQ_CAN_RX1 21 /* STM32F373 only */
+
+#define STM32_IRQ_COMP 22
+
+#define STM32_IRQ_CAN_SCE 22 /* STM32F373 only */
+#define STM32_IRQ_EXTI9_5 23
+#define STM32_IRQ_LCD 24 /* STM32L15X only */
+#define STM32_IRQ_TIM15 24 /* STM32F373 only */
+#define STM32_IRQ_TIM9 25 /* STM32L15X only */
+#define STM32_IRQ_TIM16 25 /* STM32F373 only */
+#define STM32_IRQ_TIM10 26 /* STM32L15X only */
+#define STM32_IRQ_TIM17 26 /* STM32F373 only */
+#define STM32_IRQ_TIM11 27 /* STM32L15X only */
+#define STM32_IRQ_TIM18_DAC2 27 /* STM32F373 only */
+#define STM32_IRQ_TIM2 28
+#define STM32_IRQ_TIM3 29
+#define STM32_IRQ_TIM4 30
+#define STM32_IRQ_I2C1_EV 31
+#define STM32_IRQ_I2C1_ER 32
+#define STM32_IRQ_I2C2_EV 33
+#define STM32_IRQ_I2C2_ER 34
+#define STM32_IRQ_SPI1 35
+#define STM32_IRQ_SPI2 36
+#define STM32_IRQ_USART1 37
+#define STM32_IRQ_USART2 38
+#define STM32_IRQ_USART3 39
+#define STM32_IRQ_EXTI15_10 40
+#define STM32_IRQ_RTC_ALARM 41
+#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X */
+#define STM32_IRQ_CEC 42 /* STM32F373 only */
+#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */
+#define STM32_IRQ_TIM12 43 /* STM32F373 only */
+#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */
+#define STM32_IRQ_TIM13 44 /* STM32F373 only */
+#define STM32_IRQ_TIM14 45 /* STM32F373 only */
+#define STM32_IRQ_TIM5 50 /* STM32F373 */
+#define STM32_IRQ_SPI3 51 /* STM32F373 */
+#define STM32_IRQ_USART4 52 /* STM32F446 only */
+#define STM32_IRQ_USART5 53 /* STM32F446 only */
+#define STM32_IRQ_TIM6_DAC 54 /* STM32F373 */
+#define STM32_IRQ_TIM7 55 /* STM32F373 */
+#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F373 */
+#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F373 */
+#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F373 */
+#define STM32_IRQ_DMA2_CHANNEL4 59 /* STM32F373 only */
 /* if MISC_REMAP bits are set */
-#define STM32_IRQ_DMA2_CHANNEL5   60 /* STM32F373 */
-#define STM32_IRQ_SDADC1          61 /* STM32F373 only */
-#define STM32_IRQ_SDADC2          62 /* STM32F373 only */
-#define STM32_IRQ_SDADC3          63 /* STM32F373 only */
-#define STM32_IRQ_DMA2_CHANNEL6   68 /* STM32L4 only */
-#define STM32_IRQ_DMA2_CHANNEL7   69 /* STM32L4 only */
-#define STM32_IRQ_LPUART          70 /* STM32L4 only */
-#define STM32_IRQ_USART9          70 /* STM32L4 only */
-#define STM32_IRQ_USART6          71 /* STM32F446 only */
-#define STM32_IRQ_I2C3_EV         72 /* STM32F446 only */
-#define STM32_IRQ_I2C3_ER         73 /* STM32F446 only */
-#define STM32_IRQ_USB_WAKEUP      76 /* STM32F373 only */
-#define STM32_IRQ_TIM19           78 /* STM32F373 only */
-#define STM32_IRQ_AES             79 /* STM32L4 only */
-#define STM32_IRQ_RNG             80 /* STM32L4 only */
-#define STM32_IRQ_FPU             81 /* STM32F373 only */
-
+#define STM32_IRQ_DMA2_CHANNEL5 60 /* STM32F373 */
+#define STM32_IRQ_SDADC1 61 /* STM32F373 only */
+#define STM32_IRQ_SDADC2 62 /* STM32F373 only */
+#define STM32_IRQ_SDADC3 63 /* STM32F373 only */
+#define STM32_IRQ_DMA2_CHANNEL6 68 /* STM32L4 only */
+#define STM32_IRQ_DMA2_CHANNEL7 69 /* STM32L4 only */
+#define STM32_IRQ_LPUART 70 /* STM32L4 only */
+#define STM32_IRQ_USART9 70 /* STM32L4 only */
+#define STM32_IRQ_USART6 71 /* STM32F446 only */
+#define STM32_IRQ_I2C3_EV 72 /* STM32F446 only */
+#define STM32_IRQ_I2C3_ER 73 /* STM32F446 only */
+#define STM32_IRQ_USB_WAKEUP 76 /* STM32F373 only */
+#define STM32_IRQ_TIM19 78 /* STM32F373 only */
+#define STM32_IRQ_AES 79 /* STM32L4 only */
+#define STM32_IRQ_RNG 80 /* STM32L4 only */
+#define STM32_IRQ_FPU 81 /* STM32F373 only */
 
 /* To simplify code generation, define DMA channel 9..10 */
-#define STM32_IRQ_DMA_CHANNEL_9    STM32_IRQ_DMA2_CHANNEL1
-#define STM32_IRQ_DMA_CHANNEL_10   STM32_IRQ_DMA2_CHANNEL2
-#define STM32_IRQ_DMA_CHANNEL_13   STM32_IRQ_DMA2_CHANNEL6
-#define STM32_IRQ_DMA_CHANNEL_14   STM32_IRQ_DMA2_CHANNEL7
+#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1
+#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2
+#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6
+#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7
 
 /* aliases for easier code sharing */
 #define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV
 #define STM32_IRQ_I2C2 STM32_IRQ_I2C2_EV
 #define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV
 
-
-
 /* Peripheral base addresses */
-#define STM32_ADC1_BASE             0x40012400
-#define STM32_ADC_BASE              0x40012700 /* STM32L15X only */
-
-#define STM32_CEC_BASE              0x40007800 /* STM32F373 */
-#define STM32_CRC_BASE              0x40023000
-#define STM32_CRS_BASE              0x40006c00 /* STM32F0XX */
-#define STM32_DAC_BASE              0x40007400
+#define STM32_ADC1_BASE 0x40012400
+#define STM32_ADC_BASE 0x40012700 /* STM32L15X only */
 
-#define STM32_COMP_BASE             0x40007C00
+#define STM32_CEC_BASE 0x40007800 /* STM32F373 */
+#define STM32_CRC_BASE 0x40023000
+#define STM32_CRS_BASE 0x40006c00 /* STM32F0XX */
+#define STM32_DAC_BASE 0x40007400
 
-#define STM32_DBGMCU_BASE           0xE0042000
+#define STM32_COMP_BASE 0x40007C00
 
-#define STM32_DMA1_BASE             0x40026000
+#define STM32_DBGMCU_BASE 0xE0042000
 
-#define STM32_EXTI_BASE             0x40010400
+#define STM32_DMA1_BASE 0x40026000
 
-#define STM32_FLASH_REGS_BASE       0x40023c00
+#define STM32_EXTI_BASE 0x40010400
 
-#define STM32_GPIOA_BASE            0x40020000
-#define STM32_GPIOB_BASE            0x40020400
-#define STM32_GPIOC_BASE            0x40020800
-#define STM32_GPIOD_BASE            0x40020C00
-#define STM32_GPIOE_BASE            0x40021000
-#define STM32_GPIOF_BASE            0x40021800 /* see RM0038 table 5 */
-#define STM32_GPIOG_BASE            0x40021C00
-#define STM32_GPIOH_BASE            0x40021400
+#define STM32_FLASH_REGS_BASE 0x40023c00
 
-#define STM32_I2C1_BASE             0x40005400
-#define STM32_I2C2_BASE             0x40005800
-#define STM32_I2C3_BASE             0x40005C00
-#define STM32_I2C4_BASE             0x40006000
+#define STM32_GPIOA_BASE 0x40020000
+#define STM32_GPIOB_BASE 0x40020400
+#define STM32_GPIOC_BASE 0x40020800
+#define STM32_GPIOD_BASE 0x40020C00
+#define STM32_GPIOE_BASE 0x40021000
+#define STM32_GPIOF_BASE 0x40021800 /* see RM0038 table 5 */
+#define STM32_GPIOG_BASE 0x40021C00
+#define STM32_GPIOH_BASE 0x40021400
 
-#define STM32_IWDG_BASE             0x40003000
-#define STM32_LCD_BASE              0x40002400
+#define STM32_I2C1_BASE 0x40005400
+#define STM32_I2C2_BASE 0x40005800
+#define STM32_I2C3_BASE 0x40005C00
+#define STM32_I2C4_BASE 0x40006000
 
-#define STM32_OPTB_BASE             0x1ff80000
+#define STM32_IWDG_BASE 0x40003000
+#define STM32_LCD_BASE 0x40002400
 
-#define STM32_PMSE_BASE             0x40013400
-#define STM32_PWR_BASE              0x40007000
+#define STM32_OPTB_BASE 0x1ff80000
 
-#define STM32_RCC_BASE              0x40023800
+#define STM32_PMSE_BASE 0x40013400
+#define STM32_PWR_BASE 0x40007000
 
-#define STM32_RI_BASE               0x40007C00 /* STM32L1xx only */
-#define STM32_RNG_BASE              0x50060800 /* STM32L4 */
-#define STM32_RTC_BASE              0x40002800
+#define STM32_RCC_BASE 0x40023800
 
-#define STM32_SPI1_BASE             0x40013000
-#define STM32_SPI2_BASE             0x40003800
-#define STM32_SPI3_BASE             0x40003c00 /* STM32F373, STM32L4, STM32F7 */
+#define STM32_RI_BASE 0x40007C00 /* STM32L1xx only */
+#define STM32_RNG_BASE 0x50060800 /* STM32L4 */
+#define STM32_RTC_BASE 0x40002800
 
-#define STM32_SYSCFG_BASE           0x40010000
+#define STM32_SPI1_BASE 0x40013000
+#define STM32_SPI2_BASE 0x40003800
+#define STM32_SPI3_BASE 0x40003c00 /* STM32F373, STM32L4, STM32F7 */
 
-#define STM32_TIM1_BASE             0x40012c00 /* STM32F373 */
-#define STM32_TIM2_BASE             0x40000000
-#define STM32_TIM3_BASE             0x40000400
-#define STM32_TIM4_BASE             0x40000800
-#define STM32_TIM5_BASE             0x40000c00 /* STM32F373 */
-#define STM32_TIM6_BASE             0x40001000
-#define STM32_TIM7_BASE             0x40001400
-#define STM32_TIM9_BASE             0x40010800 /* STM32L15X only */
-#define STM32_TIM10_BASE            0x40010C00 /* STM32L15X only */
-#define STM32_TIM11_BASE            0x40011000 /* STM32L15X only */
-#define STM32_TIM12_BASE            0x40001800 /* STM32F373 */
-#define STM32_TIM13_BASE            0x40001c00 /* STM32F373 */
-#define STM32_TIM14_BASE            0x40002000 /* STM32F373 */
-#define STM32_TIM15_BASE            0x40014000
-#define STM32_TIM16_BASE            0x40014400
-#define STM32_TIM17_BASE            0x40014800
-#define STM32_TIM18_BASE            0x40009c00 /* STM32F373 only */
-#define STM32_TIM19_BASE            0x40015c00 /* STM32F373 only */
+#define STM32_SYSCFG_BASE 0x40010000
 
-#define STM32_UNIQUE_ID_BASE        0x1ffff7ac
+#define STM32_TIM1_BASE 0x40012c00 /* STM32F373 */
+#define STM32_TIM2_BASE 0x40000000
+#define STM32_TIM3_BASE 0x40000400
+#define STM32_TIM4_BASE 0x40000800
+#define STM32_TIM5_BASE 0x40000c00 /* STM32F373 */
+#define STM32_TIM6_BASE 0x40001000
+#define STM32_TIM7_BASE 0x40001400
+#define STM32_TIM9_BASE 0x40010800 /* STM32L15X only */
+#define STM32_TIM10_BASE 0x40010C00 /* STM32L15X only */
+#define STM32_TIM11_BASE 0x40011000 /* STM32L15X only */
+#define STM32_TIM12_BASE 0x40001800 /* STM32F373 */
+#define STM32_TIM13_BASE 0x40001c00 /* STM32F373 */
+#define STM32_TIM14_BASE 0x40002000 /* STM32F373 */
+#define STM32_TIM15_BASE 0x40014000
+#define STM32_TIM16_BASE 0x40014400
+#define STM32_TIM17_BASE 0x40014800
+#define STM32_TIM18_BASE 0x40009c00 /* STM32F373 only */
+#define STM32_TIM19_BASE 0x40015c00 /* STM32F373 only */
 
-#define STM32_USART1_BASE           0x40013800
-#define STM32_USART2_BASE           0x40004400
-#define STM32_USART3_BASE           0x40004800
-#define STM32_USART4_BASE           0x40004c00
-#define STM32_USART9_BASE           0x40008000 /* LPUART */
+#define STM32_UNIQUE_ID_BASE 0x1ffff7ac
 
-#define STM32_USB_CAN_SRAM_BASE     0x40006000
-#define STM32_USB_FS_BASE           0x40005C00
+#define STM32_USART1_BASE 0x40013800
+#define STM32_USART2_BASE 0x40004400
+#define STM32_USART3_BASE 0x40004800
+#define STM32_USART4_BASE 0x40004c00
+#define STM32_USART9_BASE 0x40008000 /* LPUART */
 
-#define STM32_WWDG_BASE             0x40002C00
+#define STM32_USB_CAN_SRAM_BASE 0x40006000
+#define STM32_USB_FS_BASE 0x40005C00
 
+#define STM32_WWDG_BASE 0x40002C00
 
 #ifndef __ASSEMBLER__
 
 /* Register definitions */
 
 /* --- USART --- */
-#define STM32_USART_SR(base)       STM32_USART_REG(base, 0x00)
-#define STM32_USART_SR_ORE		BIT(3)
-#define STM32_USART_SR_RXNE		BIT(5)
-#define STM32_USART_SR_TC		BIT(6)
-#define STM32_USART_SR_TXE		BIT(7)
-#define STM32_USART_DR(base)       STM32_USART_REG(base, 0x04)
-#define STM32_USART_BRR(base)      STM32_USART_REG(base, 0x08)
-#define STM32_USART_CR1(base)      STM32_USART_REG(base, 0x0C)
-#define STM32_USART_CR1_RE		BIT(2)
-#define STM32_USART_CR1_TE		BIT(3)
-#define STM32_USART_CR1_RXNEIE		BIT(5)
-#define STM32_USART_CR1_TCIE		BIT(6)
-#define STM32_USART_CR1_TXEIE		BIT(7)
-#define STM32_USART_CR1_PS		BIT(9)
-#define STM32_USART_CR1_PCE		BIT(10)
-#define STM32_USART_CR1_M		BIT(12)
-#define STM32_USART_CR1_UE		BIT(13)
-#define STM32_USART_CR1_OVER8		BIT(15) /* STM32L only */
-#define STM32_USART_CR2(base)      STM32_USART_REG(base, 0x10)
-#define STM32_USART_CR3(base)      STM32_USART_REG(base, 0x14)
-#define STM32_USART_CR3_EIE		BIT(0)
-#define STM32_USART_CR3_DMAR		BIT(6)
-#define STM32_USART_CR3_DMAT		BIT(7)
-#define STM32_USART_CR3_ONEBIT		BIT(11) /* STM32L only */
-#define STM32_USART_GTPR(base)     STM32_USART_REG(base, 0x18)
+#define STM32_USART_SR(base) STM32_USART_REG(base, 0x00)
+#define STM32_USART_SR_ORE BIT(3)
+#define STM32_USART_SR_RXNE BIT(5)
+#define STM32_USART_SR_TC BIT(6)
+#define STM32_USART_SR_TXE BIT(7)
+#define STM32_USART_DR(base) STM32_USART_REG(base, 0x04)
+#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x08)
+#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x0C)
+#define STM32_USART_CR1_RE BIT(2)
+#define STM32_USART_CR1_TE BIT(3)
+#define STM32_USART_CR1_RXNEIE BIT(5)
+#define STM32_USART_CR1_TCIE BIT(6)
+#define STM32_USART_CR1_TXEIE BIT(7)
+#define STM32_USART_CR1_PS BIT(9)
+#define STM32_USART_CR1_PCE BIT(10)
+#define STM32_USART_CR1_M BIT(12)
+#define STM32_USART_CR1_UE BIT(13)
+#define STM32_USART_CR1_OVER8 BIT(15) /* STM32L only */
+#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x10)
+#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x14)
+#define STM32_USART_CR3_EIE BIT(0)
+#define STM32_USART_CR3_DMAR BIT(6)
+#define STM32_USART_CR3_DMAT BIT(7)
+#define STM32_USART_CR3_ONEBIT BIT(11) /* STM32L only */
+#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x18)
 /* register aliases */
-#define STM32_USART_TDR(base)      STM32_USART_DR(base)
-#define STM32_USART_RDR(base)      STM32_USART_DR(base)
+#define STM32_USART_TDR(base) STM32_USART_DR(base)
+#define STM32_USART_RDR(base) STM32_USART_DR(base)
 
 /* --- GPIO --- */
 
-
-#define STM32_GPIO_MODER(b)     REG32((b) + 0x00)
-#define STM32_GPIO_OTYPER(b)    REG16((b) + 0x04)
-#define STM32_GPIO_OSPEEDR(b)   REG32((b) + 0x08)
-#define STM32_GPIO_PUPDR(b)     REG32((b) + 0x0C)
-#define STM32_GPIO_IDR(b)       REG16((b) + 0x10)
-#define STM32_GPIO_ODR(b)       REG16((b) + 0x14)
-#define STM32_GPIO_BSRR(b)      REG32((b) + 0x18)
-#define STM32_GPIO_LCKR(b)      REG32((b) + 0x1C)
-#define STM32_GPIO_AFRL(b)      REG32((b) + 0x20)
-#define STM32_GPIO_AFRH(b)      REG32((b) + 0x24)
-
-#define GPIO_ALT_SYS                 0x0
-#define GPIO_ALT_TIM2                0x1
-#define GPIO_ALT_TIM3_4              0x2
-#define GPIO_ALT_TIM9_11             0x3
-#define GPIO_ALT_I2C                 0x4
-#define GPIO_ALT_SPI                 0x5
-#define GPIO_ALT_SPI3                0x6
-#define GPIO_ALT_USART               0x7
-#define GPIO_ALT_I2C_23              0x9
-#define GPIO_ALT_USB                 0xA
-#define GPIO_ALT_LCD                 0xB
-#define GPIO_ALT_RI                  0xE
-#define GPIO_ALT_EVENTOUT            0xF
+#define STM32_GPIO_MODER(b) REG32((b) + 0x00)
+#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04)
+#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08)
+#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C)
+#define STM32_GPIO_IDR(b) REG16((b) + 0x10)
+#define STM32_GPIO_ODR(b) REG16((b) + 0x14)
+#define STM32_GPIO_BSRR(b) REG32((b) + 0x18)
+#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C)
+#define STM32_GPIO_AFRL(b) REG32((b) + 0x20)
+#define STM32_GPIO_AFRH(b) REG32((b) + 0x24)
+
+#define GPIO_ALT_SYS 0x0
+#define GPIO_ALT_TIM2 0x1
+#define GPIO_ALT_TIM3_4 0x2
+#define GPIO_ALT_TIM9_11 0x3
+#define GPIO_ALT_I2C 0x4
+#define GPIO_ALT_SPI 0x5
+#define GPIO_ALT_SPI3 0x6
+#define GPIO_ALT_USART 0x7
+#define GPIO_ALT_I2C_23 0x9
+#define GPIO_ALT_USB 0xA
+#define GPIO_ALT_LCD 0xB
+#define GPIO_ALT_RI 0xE
+#define GPIO_ALT_EVENTOUT 0xF
 
 /* --- I2C --- */
-#define STM32_I2C_CR1(n)            REG16(stm32_i2c_reg(n, 0x00))
-#define STM32_I2C_CR1_PE	BIT(0)
-#define STM32_I2C_CR1_START	BIT(8)
-#define STM32_I2C_CR1_STOP	BIT(9)
-#define STM32_I2C_CR1_ACK	BIT(10)
-#define STM32_I2C_CR1_POS	BIT(11)
-#define STM32_I2C_CR1_SWRST	BIT(15)
-#define STM32_I2C_CR2(n)            REG16(stm32_i2c_reg(n, 0x04))
-#define STM32_I2C_CR2_ITERREN	BIT(8)
-#define STM32_I2C_CR2_ITEVTEN	BIT(9)
-#define STM32_I2C_CR2_ITBUFEN	BIT(10)
-#define STM32_I2C_CR2_DMAEN	BIT(11)
-#define STM32_I2C_CR2_LAST	BIT(12)
-#define STM32_I2C_OAR1(n)           REG16(stm32_i2c_reg(n, 0x08))
-#define STM32_I2C_OAR1_B14	BIT(14)
-#define STM32_I2C_OAR2(n)           REG16(stm32_i2c_reg(n, 0x0C))
-#define STM32_I2C_OAR2_ENDUAL	BIT(0)
-#define STM32_I2C_DR(n)             REG16(stm32_i2c_reg(n, 0x10))
-#define STM32_I2C_SR1(n)            REG16(stm32_i2c_reg(n, 0x14))
-#define STM32_I2C_SR1_SB	BIT(0)
-#define STM32_I2C_SR1_ADDR	BIT(1)
-#define STM32_I2C_SR1_BTF	BIT(2)
-#define STM32_I2C_SR1_STOPF	BIT(4)
-#define STM32_I2C_SR1_RXNE	BIT(6)
-#define STM32_I2C_SR1_TXE	BIT(7)
-#define STM32_I2C_SR1_BERR	BIT(8)
-#define STM32_I2C_SR1_ARLO	BIT(9)
-#define STM32_I2C_SR1_AF	BIT(10)
-
-#define STM32_I2C_SR2(n)            REG16(stm32_i2c_reg(n, 0x18))
-#define STM32_I2C_SR2_BUSY	BIT(1)
-#define STM32_I2C_SR2_TRA	BIT(2)
-#define STM32_I2C_SR2_DUALF	BIT(7)
-
-#define STM32_I2C_CCR(n)            REG16(stm32_i2c_reg(n, 0x1C))
-#define STM32_I2C_CCR_DUTY	BIT(14)
-#define STM32_I2C_CCR_FM	BIT(15)
-#define STM32_I2C_TRISE(n)          REG16(stm32_i2c_reg(n, 0x20))
-
+#define STM32_I2C_CR1(n) REG16(stm32_i2c_reg(n, 0x00))
+#define STM32_I2C_CR1_PE BIT(0)
+#define STM32_I2C_CR1_START BIT(8)
+#define STM32_I2C_CR1_STOP BIT(9)
+#define STM32_I2C_CR1_ACK BIT(10)
+#define STM32_I2C_CR1_POS BIT(11)
+#define STM32_I2C_CR1_SWRST BIT(15)
+#define STM32_I2C_CR2(n) REG16(stm32_i2c_reg(n, 0x04))
+#define STM32_I2C_CR2_ITERREN BIT(8)
+#define STM32_I2C_CR2_ITEVTEN BIT(9)
+#define STM32_I2C_CR2_ITBUFEN BIT(10)
+#define STM32_I2C_CR2_DMAEN BIT(11)
+#define STM32_I2C_CR2_LAST BIT(12)
+#define STM32_I2C_OAR1(n) REG16(stm32_i2c_reg(n, 0x08))
+#define STM32_I2C_OAR1_B14 BIT(14)
+#define STM32_I2C_OAR2(n) REG16(stm32_i2c_reg(n, 0x0C))
+#define STM32_I2C_OAR2_ENDUAL BIT(0)
+#define STM32_I2C_DR(n) REG16(stm32_i2c_reg(n, 0x10))
+#define STM32_I2C_SR1(n) REG16(stm32_i2c_reg(n, 0x14))
+#define STM32_I2C_SR1_SB BIT(0)
+#define STM32_I2C_SR1_ADDR BIT(1)
+#define STM32_I2C_SR1_BTF BIT(2)
+#define STM32_I2C_SR1_STOPF BIT(4)
+#define STM32_I2C_SR1_RXNE BIT(6)
+#define STM32_I2C_SR1_TXE BIT(7)
+#define STM32_I2C_SR1_BERR BIT(8)
+#define STM32_I2C_SR1_ARLO BIT(9)
+#define STM32_I2C_SR1_AF BIT(10)
+
+#define STM32_I2C_SR2(n) REG16(stm32_i2c_reg(n, 0x18))
+#define STM32_I2C_SR2_BUSY BIT(1)
+#define STM32_I2C_SR2_TRA BIT(2)
+#define STM32_I2C_SR2_DUALF BIT(7)
+
+#define STM32_I2C_CCR(n) REG16(stm32_i2c_reg(n, 0x1C))
+#define STM32_I2C_CCR_DUTY BIT(14)
+#define STM32_I2C_CCR_FM BIT(15)
+#define STM32_I2C_TRISE(n) REG16(stm32_i2c_reg(n, 0x20))
 
 /* --- Power / Reset / Clocks --- */
-#define STM32_PWR_CSR               REG32(STM32_PWR_BASE + 0x04)
-
-
-#define STM32_RCC_CR                REG32(STM32_RCC_BASE + 0x00)
-#define STM32_RCC_CR_HSION		BIT(0)
-#define STM32_RCC_CR_HSIRDY		BIT(1)
-#define STM32_RCC_CR_MSION		BIT(8)
-#define STM32_RCC_CR_MSIRDY		BIT(9)
-#define STM32_RCC_CR_PLLON		BIT(24)
-#define STM32_RCC_CR_PLLRDY		BIT(25)
-#define STM32_RCC_ICSCR             REG32(STM32_RCC_BASE + 0x04)
-#define STM32_RCC_ICSCR_MSIRANGE(n)	((n) << 13)
-#define STM32_RCC_ICSCR_MSIRANGE_1MHZ	STM32_RCC_ICSCR_MSIRANGE(4)
-#define STM32_RCC_ICSCR_MSIRANGE_2MHZ	STM32_RCC_ICSCR_MSIRANGE(5)
-#define STM32_RCC_ICSCR_MSIRANGE_MASK	STM32_RCC_ICSCR_MSIRANGE(7)
-#define STM32_RCC_CFGR              REG32(STM32_RCC_BASE + 0x08)
-#define STM32_RCC_CFGR_SW_MSI		(0 << 0)
-#define STM32_RCC_CFGR_SW_HSI		(1 << 0)
-#define STM32_RCC_CFGR_SW_HSE		(2 << 0)
-#define STM32_RCC_CFGR_SW_PLL		(3 << 0)
-#define STM32_RCC_CFGR_SW_MASK		(3 << 0)
-#define STM32_RCC_CFGR_SWS_MSI		(0 << 2)
-#define STM32_RCC_CFGR_SWS_HSI		(1 << 2)
-#define STM32_RCC_CFGR_SWS_HSE		(2 << 2)
-#define STM32_RCC_CFGR_SWS_PLL		(3 << 2)
-#define STM32_RCC_CFGR_SWS_MASK		(3 << 2)
-#define STM32_RCC_CIR               REG32(STM32_RCC_BASE + 0x0C)
-#define STM32_RCC_AHBRSTR           REG32(STM32_RCC_BASE + 0x10)
-#define STM32_RCC_APB2RSTR          REG32(STM32_RCC_BASE + 0x14)
-#define STM32_RCC_APB1RSTR          REG32(STM32_RCC_BASE + 0x18)
-#define STM32_RCC_AHBENR            REG32(STM32_RCC_BASE + 0x1C)
-#define STM32_RCC_APB2ENR           REG32(STM32_RCC_BASE + 0x20)
-#define STM32_RCC_SYSCFGEN		BIT(0)
-
-#define STM32_RCC_APB1ENR           REG32(STM32_RCC_BASE + 0x24)
-#define STM32_RCC_PWREN                 BIT(28)
-
-#define STM32_RCC_AHBLPENR          REG32(STM32_RCC_BASE + 0x28)
-#define STM32_RCC_APB2LPENR         REG32(STM32_RCC_BASE + 0x2C)
-#define STM32_RCC_APB1LPENR         REG32(STM32_RCC_BASE + 0x30)
-#define STM32_RCC_CSR               REG32(STM32_RCC_BASE + 0x34)
-
-#define STM32_RCC_HB_DMA1		BIT(24)
-#define STM32_RCC_PB2_TIM9		BIT(2)
-#define STM32_RCC_PB2_TIM10		BIT(3)
-#define STM32_RCC_PB2_TIM11		BIT(4)
-#define STM32_RCC_PB1_USB		BIT(23)
-
-#define STM32_SYSCFG_MEMRMP         REG32(STM32_SYSCFG_BASE + 0x00)
-#define STM32_SYSCFG_PMC            REG32(STM32_SYSCFG_BASE + 0x04)
-#define STM32_SYSCFG_EXTICR(n)      REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
-
+#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04)
+
+#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00)
+#define STM32_RCC_CR_HSION BIT(0)
+#define STM32_RCC_CR_HSIRDY BIT(1)
+#define STM32_RCC_CR_MSION BIT(8)
+#define STM32_RCC_CR_MSIRDY BIT(9)
+#define STM32_RCC_CR_PLLON BIT(24)
+#define STM32_RCC_CR_PLLRDY BIT(25)
+#define STM32_RCC_ICSCR REG32(STM32_RCC_BASE + 0x04)
+#define STM32_RCC_ICSCR_MSIRANGE(n) ((n) << 13)
+#define STM32_RCC_ICSCR_MSIRANGE_1MHZ STM32_RCC_ICSCR_MSIRANGE(4)
+#define STM32_RCC_ICSCR_MSIRANGE_2MHZ STM32_RCC_ICSCR_MSIRANGE(5)
+#define STM32_RCC_ICSCR_MSIRANGE_MASK STM32_RCC_ICSCR_MSIRANGE(7)
+#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08)
+#define STM32_RCC_CFGR_SW_MSI (0 << 0)
+#define STM32_RCC_CFGR_SW_HSI (1 << 0)
+#define STM32_RCC_CFGR_SW_HSE (2 << 0)
+#define STM32_RCC_CFGR_SW_PLL (3 << 0)
+#define STM32_RCC_CFGR_SW_MASK (3 << 0)
+#define STM32_RCC_CFGR_SWS_MSI (0 << 2)
+#define STM32_RCC_CFGR_SWS_HSI (1 << 2)
+#define STM32_RCC_CFGR_SWS_HSE (2 << 2)
+#define STM32_RCC_CFGR_SWS_PLL (3 << 2)
+#define STM32_RCC_CFGR_SWS_MASK (3 << 2)
+#define STM32_RCC_CIR REG32(STM32_RCC_BASE + 0x0C)
+#define STM32_RCC_AHBRSTR REG32(STM32_RCC_BASE + 0x10)
+#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x14)
+#define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x18)
+#define STM32_RCC_AHBENR REG32(STM32_RCC_BASE + 0x1C)
+#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x20)
+#define STM32_RCC_SYSCFGEN BIT(0)
+
+#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x24)
+#define STM32_RCC_PWREN BIT(28)
+
+#define STM32_RCC_AHBLPENR REG32(STM32_RCC_BASE + 0x28)
+#define STM32_RCC_APB2LPENR REG32(STM32_RCC_BASE + 0x2C)
+#define STM32_RCC_APB1LPENR REG32(STM32_RCC_BASE + 0x30)
+#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x34)
+
+#define STM32_RCC_HB_DMA1 BIT(24)
+#define STM32_RCC_PB2_TIM9 BIT(2)
+#define STM32_RCC_PB2_TIM10 BIT(3)
+#define STM32_RCC_PB2_TIM11 BIT(4)
+#define STM32_RCC_PB1_USB BIT(23)
+
+#define STM32_SYSCFG_MEMRMP REG32(STM32_SYSCFG_BASE + 0x00)
+#define STM32_SYSCFG_PMC REG32(STM32_SYSCFG_BASE + 0x04)
+#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
 
 /* Peripheral bits for RCC_APB/AHB and DBGMCU regs */
-#define STM32_RCC_PB2_USART1		BIT(14)
+#define STM32_RCC_PB2_USART1 BIT(14)
 
 /* Reset causes definitions */
 /* Reset causes in RCC CSR register */
 #define STM32_RCC_RESET_CAUSE STM32_RCC_CSR
-#define  RESET_CAUSE_WDG                0x60000000
-#define  RESET_CAUSE_SFT                0x10000000
-#define  RESET_CAUSE_POR                0x08000000
-#define  RESET_CAUSE_PIN                0x04000000
-#define  RESET_CAUSE_OTHER              0xfe000000
-#define  RESET_CAUSE_RMVF               0x01000000
+#define RESET_CAUSE_WDG 0x60000000
+#define RESET_CAUSE_SFT 0x10000000
+#define RESET_CAUSE_POR 0x08000000
+#define RESET_CAUSE_PIN 0x04000000
+#define RESET_CAUSE_OTHER 0xfe000000
+#define RESET_CAUSE_RMVF 0x01000000
 /* Power cause in PWR CSR register */
 #define STM32_PWR_RESET_CAUSE STM32_PWR_CSR
 #define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR
-#define  RESET_CAUSE_SBF                0x00000002
-#define  RESET_CAUSE_SBF_CLR            0x00000004
+#define RESET_CAUSE_SBF 0x00000002
+#define RESET_CAUSE_SBF_CLR 0x00000004
 
 /* --- Watchdogs --- */
 
 /* --- Real-Time Clock --- */
-#define STM32_RTC_TR                REG32(STM32_RTC_BASE + 0x00)
-#define STM32_RTC_DR                REG32(STM32_RTC_BASE + 0x04)
-#define STM32_RTC_CR                REG32(STM32_RTC_BASE + 0x08)
-#define STM32_RTC_CR_BYPSHAD        BIT(5)
-#define STM32_RTC_CR_ALRAE          BIT(8)
-#define STM32_RTC_CR_ALRAIE         BIT(12)
-#define STM32_RTC_ISR               REG32(STM32_RTC_BASE + 0x0C)
-#define STM32_RTC_ISR_ALRAWF        BIT(0)
-#define STM32_RTC_ISR_RSF           BIT(5)
-#define STM32_RTC_ISR_INITF         BIT(6)
-#define STM32_RTC_ISR_INIT          BIT(7)
-#define STM32_RTC_ISR_ALRAF         BIT(8)
-#define STM32_RTC_PRER              REG32(STM32_RTC_BASE + 0x10)
-#define STM32_RTC_PRER_A_MASK       (0x7f << 16)
-#define STM32_RTC_PRER_S_MASK       (0x7fff << 0)
-#define STM32_RTC_WUTR              REG32(STM32_RTC_BASE + 0x14)
-#define STM32_RTC_CALIBR            REG32(STM32_RTC_BASE + 0x18)
-#define STM32_RTC_ALRMAR            REG32(STM32_RTC_BASE + 0x1C)
-#define STM32_RTC_ALRMBR            REG32(STM32_RTC_BASE + 0x20)
-#define STM32_RTC_WPR               REG32(STM32_RTC_BASE + 0x24)
-#define STM32_RTC_SSR               REG32(STM32_RTC_BASE + 0x28)
-#define STM32_RTC_TSTR              REG32(STM32_RTC_BASE + 0x30)
-#define STM32_RTC_TSDR              REG32(STM32_RTC_BASE + 0x34)
-#define STM32_RTC_TAFCR             REG32(STM32_RTC_BASE + 0x40)
-#define STM32_RTC_ALRMASSR          REG32(STM32_RTC_BASE + 0x44)
-#define STM32_RTC_BACKUP(n)         REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
-
-#define STM32_BKP_DATA(n)           STM32_RTC_BACKUP(n)
-#define STM32_BKP_BYTES             80
+#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00)
+#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04)
+#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08)
+#define STM32_RTC_CR_BYPSHAD BIT(5)
+#define STM32_RTC_CR_ALRAE BIT(8)
+#define STM32_RTC_CR_ALRAIE BIT(12)
+#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C)
+#define STM32_RTC_ISR_ALRAWF BIT(0)
+#define STM32_RTC_ISR_RSF BIT(5)
+#define STM32_RTC_ISR_INITF BIT(6)
+#define STM32_RTC_ISR_INIT BIT(7)
+#define STM32_RTC_ISR_ALRAF BIT(8)
+#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10)
+#define STM32_RTC_PRER_A_MASK (0x7f << 16)
+#define STM32_RTC_PRER_S_MASK (0x7fff << 0)
+#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14)
+#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18)
+#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C)
+#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20)
+#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24)
+#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28)
+#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30)
+#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34)
+#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40)
+#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44)
+#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
+
+#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n)
+#define STM32_BKP_BYTES 80
 
 /* --- SPI --- */
 
@@ -424,15 +416,15 @@ struct stm32_spi_regs {
 	uint16_t _pad0;
 	uint16_t cr2;
 	uint16_t _pad1;
-	unsigned sr;
+	unsigned int sr;
 	uint8_t dr;
 	uint8_t _pad2;
 	uint16_t _pad3;
-	unsigned crcpr;
-	unsigned rxcrcr;
-	unsigned txcrcr;
-	unsigned i2scfgr;	/* STM32L only */
-	unsigned i2spr;		/* STM32L only */
+	unsigned int crcpr;
+	unsigned int rxcrcr;
+	unsigned int txcrcr;
+	unsigned int i2scfgr; /* STM32L only */
+	unsigned int i2spr; /* STM32L only */
 };
 /* Must be volatile, or compiler optimizes out repeated accesses */
 typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
@@ -442,146 +434,144 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
 #define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE)
 #define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE)
 
-#define STM32_SPI_CR1_BIDIMODE		BIT(15)
-#define STM32_SPI_CR1_BIDIOE		BIT(14)
-#define STM32_SPI_CR1_CRCEN		BIT(13)
-#define STM32_SPI_CR1_SSM		BIT(9)
-#define STM32_SPI_CR1_SSI		BIT(8)
-#define STM32_SPI_CR1_LSBFIRST		BIT(7)
-#define STM32_SPI_CR1_SPE		BIT(6)
-#define STM32_SPI_CR1_BR_DIV64R		(5 << 3)
-#define STM32_SPI_CR1_BR_DIV4R		BIT(3)
-#define STM32_SPI_CR1_MSTR		BIT(2)
-#define STM32_SPI_CR1_CPOL		BIT(1)
-#define STM32_SPI_CR1_CPHA		BIT(0)
-#define STM32_SPI_CR2_FRXTH		BIT(12)
-#define STM32_SPI_CR2_DATASIZE(n)	(((n) - 1) << 8)
-#define STM32_SPI_CR2_TXEIE		BIT(7)
-#define STM32_SPI_CR2_RXNEIE		BIT(6)
-#define STM32_SPI_CR2_NSSP		BIT(3)
-#define STM32_SPI_CR2_SSOE		BIT(2)
-#define STM32_SPI_CR2_TXDMAEN		BIT(1)
-#define STM32_SPI_CR2_RXDMAEN		BIT(0)
-
-#define STM32_SPI_SR_RXNE		BIT(0)
-#define STM32_SPI_SR_TXE		BIT(1)
-#define STM32_SPI_SR_CRCERR		BIT(4)
-#define STM32_SPI_SR_BSY		BIT(7)
-#define STM32_SPI_SR_FRLVL		(3 << 9)
-#define STM32_SPI_SR_FTLVL		(3 << 11)
+#define STM32_SPI_CR1_BIDIMODE BIT(15)
+#define STM32_SPI_CR1_BIDIOE BIT(14)
+#define STM32_SPI_CR1_CRCEN BIT(13)
+#define STM32_SPI_CR1_SSM BIT(9)
+#define STM32_SPI_CR1_SSI BIT(8)
+#define STM32_SPI_CR1_LSBFIRST BIT(7)
+#define STM32_SPI_CR1_SPE BIT(6)
+#define STM32_SPI_CR1_BR_DIV64R (5 << 3)
+#define STM32_SPI_CR1_BR_DIV4R BIT(3)
+#define STM32_SPI_CR1_MSTR BIT(2)
+#define STM32_SPI_CR1_CPOL BIT(1)
+#define STM32_SPI_CR1_CPHA BIT(0)
+#define STM32_SPI_CR2_FRXTH BIT(12)
+#define STM32_SPI_CR2_DATASIZE(n) (((n)-1) << 8)
+#define STM32_SPI_CR2_TXEIE BIT(7)
+#define STM32_SPI_CR2_RXNEIE BIT(6)
+#define STM32_SPI_CR2_NSSP BIT(3)
+#define STM32_SPI_CR2_SSOE BIT(2)
+#define STM32_SPI_CR2_TXDMAEN BIT(1)
+#define STM32_SPI_CR2_RXDMAEN BIT(0)
+
+#define STM32_SPI_SR_RXNE BIT(0)
+#define STM32_SPI_SR_TXE BIT(1)
+#define STM32_SPI_SR_CRCERR BIT(4)
+#define STM32_SPI_SR_BSY BIT(7)
+#define STM32_SPI_SR_FRLVL (3 << 9)
+#define STM32_SPI_SR_FTLVL (3 << 11)
 /* --- Debug --- */
-#define STM32_DBGMCU_APB1FZ         REG32(STM32_DBGMCU_BASE + 0x08)
-#define STM32_DBGMCU_APB2FZ         REG32(STM32_DBGMCU_BASE + 0x0C)
+#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08)
+#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C)
 
 /* --- Flash --- */
-#define STM32_FLASH_ACR             REG32(STM32_FLASH_REGS_BASE + 0x00)
-#define STM32_FLASH_ACR_LATENCY		BIT(0)
-#define STM32_FLASH_ACR_PRFTEN		BIT(1)
-#define STM32_FLASH_ACR_ACC64		BIT(2)
-#define STM32_FLASH_PECR            REG32(STM32_FLASH_REGS_BASE + 0x04)
-#define STM32_FLASH_PECR_PE_LOCK	BIT(0)
-#define STM32_FLASH_PECR_PRG_LOCK	BIT(1)
-#define STM32_FLASH_PECR_OPT_LOCK	BIT(2)
-#define STM32_FLASH_PECR_PROG		BIT(3)
-#define STM32_FLASH_PECR_ERASE		BIT(9)
-#define STM32_FLASH_PECR_FPRG		BIT(10)
-#define STM32_FLASH_PECR_OBL_LAUNCH	BIT(18)
-#define STM32_FLASH_PDKEYR          REG32(STM32_FLASH_REGS_BASE + 0x08)
-#define STM32_FLASH_PEKEYR          REG32(STM32_FLASH_REGS_BASE + 0x0c)
-#define STM32_FLASH_PEKEYR_KEY1		0x89ABCDEF
-#define STM32_FLASH_PEKEYR_KEY2		0x02030405
-#define STM32_FLASH_PRGKEYR         REG32(STM32_FLASH_REGS_BASE + 0x10)
-#define STM32_FLASH_PRGKEYR_KEY1	0x8C9DAEBF
-#define STM32_FLASH_PRGKEYR_KEY2	0x13141516
-#define STM32_FLASH_OPTKEYR         REG32(STM32_FLASH_REGS_BASE + 0x14)
-#define STM32_FLASH_OPTKEYR_KEY1	0xFBEAD9C8
-#define STM32_FLASH_OPTKEYR_KEY2	0x24252627
-#define STM32_FLASH_SR              REG32(STM32_FLASH_REGS_BASE + 0x18)
-#define STM32_FLASH_OBR             REG32(STM32_FLASH_REGS_BASE + 0x1c)
-#define STM32_FLASH_WRPR            REG32(STM32_FLASH_REGS_BASE + 0x20)
-
-#define STM32_OPTB_RDP                  0x00
-#define STM32_OPTB_USER                 0x04
-#define STM32_OPTB_WRP1L                0x08
-#define STM32_OPTB_WRP1H                0x0c
-#define STM32_OPTB_WRP2L                0x10
-#define STM32_OPTB_WRP2H                0x14
-#define STM32_OPTB_WRP3L                0x18
-#define STM32_OPTB_WRP3H                0x1c
+#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00)
+#define STM32_FLASH_ACR_LATENCY BIT(0)
+#define STM32_FLASH_ACR_PRFTEN BIT(1)
+#define STM32_FLASH_ACR_ACC64 BIT(2)
+#define STM32_FLASH_PECR REG32(STM32_FLASH_REGS_BASE + 0x04)
+#define STM32_FLASH_PECR_PE_LOCK BIT(0)
+#define STM32_FLASH_PECR_PRG_LOCK BIT(1)
+#define STM32_FLASH_PECR_OPT_LOCK BIT(2)
+#define STM32_FLASH_PECR_PROG BIT(3)
+#define STM32_FLASH_PECR_ERASE BIT(9)
+#define STM32_FLASH_PECR_FPRG BIT(10)
+#define STM32_FLASH_PECR_OBL_LAUNCH BIT(18)
+#define STM32_FLASH_PDKEYR REG32(STM32_FLASH_REGS_BASE + 0x08)
+#define STM32_FLASH_PEKEYR REG32(STM32_FLASH_REGS_BASE + 0x0c)
+#define STM32_FLASH_PEKEYR_KEY1 0x89ABCDEF
+#define STM32_FLASH_PEKEYR_KEY2 0x02030405
+#define STM32_FLASH_PRGKEYR REG32(STM32_FLASH_REGS_BASE + 0x10)
+#define STM32_FLASH_PRGKEYR_KEY1 0x8C9DAEBF
+#define STM32_FLASH_PRGKEYR_KEY2 0x13141516
+#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x14)
+#define STM32_FLASH_OPTKEYR_KEY1 0xFBEAD9C8
+#define STM32_FLASH_OPTKEYR_KEY2 0x24252627
+#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x18)
+#define STM32_FLASH_OBR REG32(STM32_FLASH_REGS_BASE + 0x1c)
+#define STM32_FLASH_WRPR REG32(STM32_FLASH_REGS_BASE + 0x20)
+
+#define STM32_OPTB_RDP 0x00
+#define STM32_OPTB_USER 0x04
+#define STM32_OPTB_WRP1L 0x08
+#define STM32_OPTB_WRP1H 0x0c
+#define STM32_OPTB_WRP2L 0x10
+#define STM32_OPTB_WRP2H 0x14
+#define STM32_OPTB_WRP3L 0x18
+#define STM32_OPTB_WRP3H 0x1c
 
 /* --- External Interrupts --- */
-#define STM32_EXTI_IMR              REG32(STM32_EXTI_BASE + 0x00)
-#define STM32_EXTI_EMR              REG32(STM32_EXTI_BASE + 0x04)
-#define STM32_EXTI_RTSR             REG32(STM32_EXTI_BASE + 0x08)
-#define STM32_EXTI_FTSR             REG32(STM32_EXTI_BASE + 0x0c)
-#define STM32_EXTI_SWIER            REG32(STM32_EXTI_BASE + 0x10)
-#define STM32_EXTI_PR               REG32(STM32_EXTI_BASE + 0x14)
-
+#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00)
+#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04)
+#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08)
+#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c)
+#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10)
+#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14)
 
 /* --- ADC --- */
-#define STM32_ADC_SR               REG32(STM32_ADC1_BASE + 0x00)
-#define STM32_ADC_CR1              REG32(STM32_ADC1_BASE + 0x04)
-#define STM32_ADC_CR2              REG32(STM32_ADC1_BASE + 0x08)
-#define STM32_ADC_SMPR1            REG32(STM32_ADC1_BASE + 0x0C)
-#define STM32_ADC_SMPR2            REG32(STM32_ADC1_BASE + 0x10)
-#define STM32_ADC_SMPR3            REG32(STM32_ADC1_BASE + 0x14)
-#define STM32_ADC_JOFR1            REG32(STM32_ADC1_BASE + 0x18)
-#define STM32_ADC_JOFR2            REG32(STM32_ADC1_BASE + 0x1C)
-#define STM32_ADC_JOFR3            REG32(STM32_ADC1_BASE + 0x20)
-#define STM32_ADC_JOFR4            REG32(STM32_ADC1_BASE + 0x24)
-#define STM32_ADC_HTR              REG32(STM32_ADC1_BASE + 0x28)
-#define STM32_ADC_LTR              REG32(STM32_ADC1_BASE + 0x2C)
-#define STM32_ADC_SQR(n)           REG32(STM32_ADC1_BASE + 0x2C + (n) * 4)
-#define STM32_ADC_SQR1             REG32(STM32_ADC1_BASE + 0x30)
-#define STM32_ADC_SQR2             REG32(STM32_ADC1_BASE + 0x34)
-#define STM32_ADC_SQR3             REG32(STM32_ADC1_BASE + 0x38)
-#define STM32_ADC_SQR4             REG32(STM32_ADC1_BASE + 0x3C)
-#define STM32_ADC_SQR5             REG32(STM32_ADC1_BASE + 0x40)
-#define STM32_ADC_JSQR             REG32(STM32_ADC1_BASE + 0x44)
-#define STM32_ADC_JDR1             REG32(STM32_ADC1_BASE + 0x48)
-#define STM32_ADC_JDR2             REG32(STM32_ADC1_BASE + 0x4C)
-#define STM32_ADC_JDR3             REG32(STM32_ADC1_BASE + 0x50)
-#define STM32_ADC_JDR3             REG32(STM32_ADC1_BASE + 0x50)
-#define STM32_ADC_JDR4             REG32(STM32_ADC1_BASE + 0x54)
-#define STM32_ADC_DR               REG32(STM32_ADC1_BASE + 0x58)
-#define STM32_ADC_SMPR0            REG32(STM32_ADC1_BASE + 0x5C)
-
-#define STM32_ADC_CCR              REG32(STM32_ADC_BASE + 0x04)
+#define STM32_ADC_SR REG32(STM32_ADC1_BASE + 0x00)
+#define STM32_ADC_CR1 REG32(STM32_ADC1_BASE + 0x04)
+#define STM32_ADC_CR2 REG32(STM32_ADC1_BASE + 0x08)
+#define STM32_ADC_SMPR1 REG32(STM32_ADC1_BASE + 0x0C)
+#define STM32_ADC_SMPR2 REG32(STM32_ADC1_BASE + 0x10)
+#define STM32_ADC_SMPR3 REG32(STM32_ADC1_BASE + 0x14)
+#define STM32_ADC_JOFR1 REG32(STM32_ADC1_BASE + 0x18)
+#define STM32_ADC_JOFR2 REG32(STM32_ADC1_BASE + 0x1C)
+#define STM32_ADC_JOFR3 REG32(STM32_ADC1_BASE + 0x20)
+#define STM32_ADC_JOFR4 REG32(STM32_ADC1_BASE + 0x24)
+#define STM32_ADC_HTR REG32(STM32_ADC1_BASE + 0x28)
+#define STM32_ADC_LTR REG32(STM32_ADC1_BASE + 0x2C)
+#define STM32_ADC_SQR(n) REG32(STM32_ADC1_BASE + 0x2C + (n)*4)
+#define STM32_ADC_SQR1 REG32(STM32_ADC1_BASE + 0x30)
+#define STM32_ADC_SQR2 REG32(STM32_ADC1_BASE + 0x34)
+#define STM32_ADC_SQR3 REG32(STM32_ADC1_BASE + 0x38)
+#define STM32_ADC_SQR4 REG32(STM32_ADC1_BASE + 0x3C)
+#define STM32_ADC_SQR5 REG32(STM32_ADC1_BASE + 0x40)
+#define STM32_ADC_JSQR REG32(STM32_ADC1_BASE + 0x44)
+#define STM32_ADC_JDR1 REG32(STM32_ADC1_BASE + 0x48)
+#define STM32_ADC_JDR2 REG32(STM32_ADC1_BASE + 0x4C)
+#define STM32_ADC_JDR3 REG32(STM32_ADC1_BASE + 0x50)
+#define STM32_ADC_JDR3 REG32(STM32_ADC1_BASE + 0x50)
+#define STM32_ADC_JDR4 REG32(STM32_ADC1_BASE + 0x54)
+#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x58)
+#define STM32_ADC_SMPR0 REG32(STM32_ADC1_BASE + 0x5C)
+
+#define STM32_ADC_CCR REG32(STM32_ADC_BASE + 0x04)
 
 /* --- Comparators --- */
-#define STM32_COMP_CSR              REG32(STM32_COMP_BASE + 0x00)
-
-#define STM32_COMP_OUTSEL_TIM2_IC4  (0 << 21)
-#define STM32_COMP_OUTSEL_TIM2_OCR  (1 << 21)
-#define STM32_COMP_OUTSEL_TIM3_IC4  (2 << 21)
-#define STM32_COMP_OUTSEL_TIM3_OCR  (3 << 21)
-#define STM32_COMP_OUTSEL_TIM4_IC4  (4 << 21)
-#define STM32_COMP_OUTSEL_TIM4_OCR  (5 << 21)
+#define STM32_COMP_CSR REG32(STM32_COMP_BASE + 0x00)
+
+#define STM32_COMP_OUTSEL_TIM2_IC4 (0 << 21)
+#define STM32_COMP_OUTSEL_TIM2_OCR (1 << 21)
+#define STM32_COMP_OUTSEL_TIM3_IC4 (2 << 21)
+#define STM32_COMP_OUTSEL_TIM3_OCR (3 << 21)
+#define STM32_COMP_OUTSEL_TIM4_IC4 (4 << 21)
+#define STM32_COMP_OUTSEL_TIM4_OCR (5 << 21)
 #define STM32_COMP_OUTSEL_TIM10_IC1 (6 << 21)
-#define STM32_COMP_OUTSEL_NONE      (7 << 21)
-
-#define STM32_COMP_INSEL_NONE       (0 << 18)
-#define STM32_COMP_INSEL_PB3        (1 << 18)
-#define STM32_COMP_INSEL_VREF       (2 << 18)
-#define STM32_COMP_INSEL_VREF34     (3 << 18)
-#define STM32_COMP_INSEL_VREF12     (4 << 18)
-#define STM32_COMP_INSEL_VREF14     (5 << 18)
-#define STM32_COMP_INSEL_DAC_OUT1   (6 << 18)
-#define STM32_COMP_INSEL_DAC_OUT2   (7 << 18)
-
-#define STM32_COMP_WNDWE            BIT(17)
-#define STM32_COMP_VREFOUTEN        BIT(16)
-#define STM32_COMP_CMP2OUT          BIT(13)
-#define STM32_COMP_SPEED_FAST       BIT(12)
-
-#define STM32_COMP_CMP1OUT          BIT(7)
-#define STM32_COMP_CMP1EN           BIT(4)
-
-#define STM32_COMP_400KPD           BIT(3)
-#define STM32_COMP_10KPD            BIT(2)
-#define STM32_COMP_400KPU           BIT(1)
-#define STM32_COMP_10KPU            BIT(0)
-
+#define STM32_COMP_OUTSEL_NONE (7 << 21)
+
+#define STM32_COMP_INSEL_NONE (0 << 18)
+#define STM32_COMP_INSEL_PB3 (1 << 18)
+#define STM32_COMP_INSEL_VREF (2 << 18)
+#define STM32_COMP_INSEL_VREF34 (3 << 18)
+#define STM32_COMP_INSEL_VREF12 (4 << 18)
+#define STM32_COMP_INSEL_VREF14 (5 << 18)
+#define STM32_COMP_INSEL_DAC_OUT1 (6 << 18)
+#define STM32_COMP_INSEL_DAC_OUT2 (7 << 18)
+
+#define STM32_COMP_WNDWE BIT(17)
+#define STM32_COMP_VREFOUTEN BIT(16)
+#define STM32_COMP_CMP2OUT BIT(13)
+#define STM32_COMP_SPEED_FAST BIT(12)
+
+#define STM32_COMP_CMP1OUT BIT(7)
+#define STM32_COMP_CMP1EN BIT(4)
+
+#define STM32_COMP_400KPD BIT(3)
+#define STM32_COMP_10KPD BIT(2)
+#define STM32_COMP_400KPU BIT(1)
+#define STM32_COMP_10KPU BIT(0)
 
 /* --- DMA --- */
 
@@ -642,11 +632,11 @@ enum dma_channel {
 
 /* Registers for a single channel of the DMA controller */
 struct stm32_dma_chan {
-	uint32_t	ccr;		/* Control */
-	uint32_t	cndtr;		/* Number of data to transfer */
-	uint32_t	cpar;		/* Peripheral address */
-	uint32_t	cmar;		/* Memory address */
-	uint32_t	reserved;
+	uint32_t ccr; /* Control */
+	uint32_t cndtr; /* Number of data to transfer */
+	uint32_t cpar; /* Peripheral address */
+	uint32_t cmar; /* Memory address */
+	uint32_t reserved;
 };
 
 /* Always use stm32_dma_chan_t so volatile keyword is included! */
@@ -657,8 +647,8 @@ typedef stm32_dma_chan_t dma_chan_t;
 
 /* Registers for the DMA controller */
 struct stm32_dma_regs {
-	uint32_t	isr;
-	uint32_t	ifcr;
+	uint32_t isr;
+	uint32_t ifcr;
 	stm32_dma_chan_t chan[STM32_DMAC_COUNT];
 };
 
@@ -667,205 +657,124 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
 
 #define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE)
 
-
-#define STM32_DMA_CCR_CHANNEL(channel)		 (0)
+#define STM32_DMA_CCR_CHANNEL(channel) (0)
 
 #define STM32_DMA_REGS(channel) STM32_DMA1_REGS
 
 /* Bits for DMA controller regs (isr and ifcr) */
-#define STM32_DMA_CH_OFFSET(channel)   (4 * ((channel) % STM32_DMAC_PER_CTLR))
+#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR))
 #define STM32_DMA_ISR_MASK(channel, mask) \
 	((mask) << STM32_DMA_CH_OFFSET(channel))
-#define STM32_DMA_ISR_GIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(0))
-#define STM32_DMA_ISR_TCIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(1))
-#define STM32_DMA_ISR_HTIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(2))
-#define STM32_DMA_ISR_TEIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(3))
-#define STM32_DMA_ISR_ALL(channel)	STM32_DMA_ISR_MASK(channel, 0x0f)
-
-#define STM32_DMA_GIF                   BIT(0)
-#define STM32_DMA_TCIF                  BIT(1)
-#define STM32_DMA_HTIF                  BIT(2)
-#define STM32_DMA_TEIF                  BIT(3)
-#define STM32_DMA_ALL                   0xf
-
-#define STM32_DMA_GET_ISR(channel)      \
-	((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_ISR(channel, val) \
-	(STM32_DMA_REGS(channel)->isr = \
-	((STM32_DMA_REGS(channel)->isr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-#define STM32_DMA_GET_IFCR(channel)      \
-	((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_IFCR(channel, val) \
-	(STM32_DMA_REGS(channel)->ifcr = \
-	((STM32_DMA_REGS(channel)->ifcr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-
+#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0))
+#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1))
+#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2))
+#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3))
+#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f)
+
+#define STM32_DMA_GIF BIT(0)
+#define STM32_DMA_TCIF BIT(1)
+#define STM32_DMA_HTIF BIT(2)
+#define STM32_DMA_TEIF BIT(3)
+#define STM32_DMA_ALL 0xf
+
+#define STM32_DMA_GET_ISR(channel)                                        \
+	((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) & \
+	 STM32_DMA_ALL)
+#define STM32_DMA_SET_ISR(channel, val)                                \
+	(STM32_DMA_REGS(channel)->isr =                                \
+		 ((STM32_DMA_REGS(channel)->isr &                      \
+		   ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
+		  (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
+#define STM32_DMA_GET_IFCR(channel)                                        \
+	((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) & \
+	 STM32_DMA_ALL)
+#define STM32_DMA_SET_IFCR(channel, val)                               \
+	(STM32_DMA_REGS(channel)->ifcr =                               \
+		 ((STM32_DMA_REGS(channel)->ifcr &                     \
+		   ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
+		  (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
 
 /* Bits for DMA channel regs */
-#define STM32_DMA_CCR_EN		BIT(0)
-#define STM32_DMA_CCR_TCIE		BIT(1)
-#define STM32_DMA_CCR_HTIE		BIT(2)
-#define STM32_DMA_CCR_TEIE		BIT(3)
-#define STM32_DMA_CCR_DIR		BIT(4)
-#define STM32_DMA_CCR_CIRC		BIT(5)
-#define STM32_DMA_CCR_PINC		BIT(6)
-#define STM32_DMA_CCR_MINC		BIT(7)
-#define STM32_DMA_CCR_PSIZE_8_BIT	(0 << 8)
-#define STM32_DMA_CCR_PSIZE_16_BIT	(1 << 8)
-#define STM32_DMA_CCR_PSIZE_32_BIT	(2 << 8)
-#define STM32_DMA_CCR_MSIZE_8_BIT	(0 << 10)
-#define STM32_DMA_CCR_MSIZE_16_BIT	(1 << 10)
-#define STM32_DMA_CCR_MSIZE_32_BIT	(2 << 10)
-#define STM32_DMA_CCR_PL_LOW		(0 << 12)
-#define STM32_DMA_CCR_PL_MEDIUM		(1 << 12)
-#define STM32_DMA_CCR_PL_HIGH		(2 << 12)
-#define STM32_DMA_CCR_PL_VERY_HIGH	(3 << 12)
-#define STM32_DMA_CCR_MEM2MEM		BIT(14)
-
+#define STM32_DMA_CCR_EN BIT(0)
+#define STM32_DMA_CCR_TCIE BIT(1)
+#define STM32_DMA_CCR_HTIE BIT(2)
+#define STM32_DMA_CCR_TEIE BIT(3)
+#define STM32_DMA_CCR_DIR BIT(4)
+#define STM32_DMA_CCR_CIRC BIT(5)
+#define STM32_DMA_CCR_PINC BIT(6)
+#define STM32_DMA_CCR_MINC BIT(7)
+#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8)
+#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8)
+#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8)
+#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10)
+#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10)
+#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10)
+#define STM32_DMA_CCR_PL_LOW (0 << 12)
+#define STM32_DMA_CCR_PL_MEDIUM (1 << 12)
+#define STM32_DMA_CCR_PL_HIGH (2 << 12)
+#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12)
+#define STM32_DMA_CCR_MEM2MEM BIT(14)
 
 /* --- CRC --- */
-#define STM32_CRC_DR                REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR32              REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR16              REG16(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR8               REG8(STM32_CRC_BASE + 0x0)
-
-#define STM32_CRC_IDR               REG32(STM32_CRC_BASE + 0x4)
-#define STM32_CRC_CR                REG32(STM32_CRC_BASE + 0x8)
-#define STM32_CRC_INIT              REG32(STM32_CRC_BASE + 0x10)
-#define STM32_CRC_POL               REG32(STM32_CRC_BASE + 0x14)
-
-#define STM32_CRC_CR_RESET          BIT(0)
-#define STM32_CRC_CR_POLYSIZE_32    (0 << 3)
-#define STM32_CRC_CR_POLYSIZE_16    (1 << 3)
-#define STM32_CRC_CR_POLYSIZE_8     (2 << 3)
-#define STM32_CRC_CR_POLYSIZE_7     (3 << 3)
-#define STM32_CRC_CR_REV_IN_BYTE    (1 << 5)
-#define STM32_CRC_CR_REV_IN_HWORD   (2 << 5)
-#define STM32_CRC_CR_REV_IN_WORD    (3 << 5)
-#define STM32_CRC_CR_REV_OUT        BIT(7)
+#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0)
+
+#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4)
+#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8)
+#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10)
+#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14)
+
+#define STM32_CRC_CR_RESET BIT(0)
+#define STM32_CRC_CR_POLYSIZE_32 (0 << 3)
+#define STM32_CRC_CR_POLYSIZE_16 (1 << 3)
+#define STM32_CRC_CR_POLYSIZE_8 (2 << 3)
+#define STM32_CRC_CR_POLYSIZE_7 (3 << 3)
+#define STM32_CRC_CR_REV_IN_BYTE (1 << 5)
+#define STM32_CRC_CR_REV_IN_HWORD (2 << 5)
+#define STM32_CRC_CR_REV_IN_WORD (3 << 5)
+#define STM32_CRC_CR_REV_OUT BIT(7)
 
 /* --- PMSE --- */
-#define STM32_PMSE_ARCR             REG32(STM32_PMSE_BASE + 0x0)
-#define STM32_PMSE_ACCR             REG32(STM32_PMSE_BASE + 0x4)
-#define STM32_PMSE_CR               REG32(STM32_PMSE_BASE + 0x8)
-#define STM32_PMSE_CRTDR            REG32(STM32_PMSE_BASE + 0x14)
-#define STM32_PMSE_IER              REG32(STM32_PMSE_BASE + 0x18)
-#define STM32_PMSE_SR               REG32(STM32_PMSE_BASE + 0x1c)
-#define STM32_PMSE_IFCR             REG32(STM32_PMSE_BASE + 0x20)
-#define STM32_PMSE_PxPMR(x)         REG32(STM32_PMSE_BASE + 0x2c + (x) * 4)
-#define STM32_PMSE_PAPMR            REG32(STM32_PMSE_BASE + 0x2c)
-#define STM32_PMSE_PBPMR            REG32(STM32_PMSE_BASE + 0x30)
-#define STM32_PMSE_PCPMR            REG32(STM32_PMSE_BASE + 0x34)
-#define STM32_PMSE_PDPMR            REG32(STM32_PMSE_BASE + 0x38)
-#define STM32_PMSE_PEPMR            REG32(STM32_PMSE_BASE + 0x3c)
-#define STM32_PMSE_PFPMR            REG32(STM32_PMSE_BASE + 0x40)
-#define STM32_PMSE_PGPMR            REG32(STM32_PMSE_BASE + 0x44)
-#define STM32_PMSE_PHPMR            REG32(STM32_PMSE_BASE + 0x48)
-#define STM32_PMSE_PIPMR            REG32(STM32_PMSE_BASE + 0x4c)
-#define STM32_PMSE_MRCR             REG32(STM32_PMSE_BASE + 0x100)
-#define STM32_PMSE_MCCR             REG32(STM32_PMSE_BASE + 0x104)
-
-/* --- USB --- */
-#define STM32_USB_EP(n)            REG16(STM32_USB_FS_BASE + (n) * 4)
-
-#define STM32_USB_CNTR             REG16(STM32_USB_FS_BASE + 0x40)
-
-#define STM32_USB_CNTR_FRES	    BIT(0)
-#define STM32_USB_CNTR_PDWN	    BIT(1)
-#define STM32_USB_CNTR_LP_MODE	    BIT(2)
-#define STM32_USB_CNTR_FSUSP	    BIT(3)
-#define STM32_USB_CNTR_RESUME	    BIT(4)
-#define STM32_USB_CNTR_L1RESUME	    BIT(5)
-#define STM32_USB_CNTR_L1REQM	    BIT(7)
-#define STM32_USB_CNTR_ESOFM	    BIT(8)
-#define STM32_USB_CNTR_SOFM	    BIT(9)
-#define STM32_USB_CNTR_RESETM	    BIT(10)
-#define STM32_USB_CNTR_SUSPM	    BIT(11)
-#define STM32_USB_CNTR_WKUPM	    BIT(12)
-#define STM32_USB_CNTR_ERRM	    BIT(13)
-#define STM32_USB_CNTR_PMAOVRM	    BIT(14)
-#define STM32_USB_CNTR_CTRM	    BIT(15)
-
-#define STM32_USB_ISTR             REG16(STM32_USB_FS_BASE + 0x44)
-
-#define STM32_USB_ISTR_EP_ID_MASK   (0x000f)
-#define STM32_USB_ISTR_DIR	    BIT(4)
-#define STM32_USB_ISTR_L1REQ	    BIT(7)
-#define STM32_USB_ISTR_ESOF	    BIT(8)
-#define STM32_USB_ISTR_SOF	    BIT(9)
-#define STM32_USB_ISTR_RESET	    BIT(10)
-#define STM32_USB_ISTR_SUSP	    BIT(11)
-#define STM32_USB_ISTR_WKUP	    BIT(12)
-#define STM32_USB_ISTR_ERR	    BIT(13)
-#define STM32_USB_ISTR_PMAOVR	    BIT(14)
-#define STM32_USB_ISTR_CTR	    BIT(15)
-
-#define STM32_USB_FNR              REG16(STM32_USB_FS_BASE + 0x48)
-
-#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14)
-#define STM32_USB_FNR_RXDP_RXDM_MASK  (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT)
-
-#define STM32_USB_DADDR            REG16(STM32_USB_FS_BASE + 0x4C)
-#define STM32_USB_BTABLE           REG16(STM32_USB_FS_BASE + 0x50)
-#define STM32_USB_LPMCSR           REG16(STM32_USB_FS_BASE + 0x54)
-#define STM32_USB_BCDR             REG16(STM32_USB_FS_BASE + 0x58)
-
-#define STM32_USB_BCDR_BCDEN	    BIT(0)
-#define STM32_USB_BCDR_DCDEN	    BIT(1)
-#define STM32_USB_BCDR_PDEN	    BIT(2)
-#define STM32_USB_BCDR_SDEN	    BIT(3)
-#define STM32_USB_BCDR_DCDET	    BIT(4)
-#define STM32_USB_BCDR_PDET	    BIT(5)
-#define STM32_USB_BCDR_SDET	    BIT(6)
-#define STM32_USB_BCDR_PS2DET	    BIT(7)
-
-#define EP_MASK     0x0F0F
-#define EP_TX_DTOG  0x0040
-#define EP_TX_MASK  0x0030
-#define EP_TX_VALID 0x0030
-#define EP_TX_NAK   0x0020
-#define EP_TX_STALL 0x0010
-#define EP_TX_DISAB 0x0000
-#define EP_RX_DTOG  0x4000
-#define EP_RX_MASK  0x3000
-#define EP_RX_VALID 0x3000
-#define EP_RX_NAK   0x2000
-#define EP_RX_STALL 0x1000
-#define EP_RX_DISAB 0x0000
-
-#define EP_STATUS_OUT 0x0100
-
-#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK)
-#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID)
-
-#define STM32_TOGGLE_EP(n, mask, val, flags) \
-	STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \
-			^ (val)) | (flags))
+#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0)
+#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4)
+#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8)
+#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14)
+#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18)
+#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c)
+#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20)
+#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x)*4)
+#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c)
+#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30)
+#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34)
+#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38)
+#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c)
+#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40)
+#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44)
+#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48)
+#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c)
+#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100)
+#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104)
 
 /* --- TRNG --- */
-#define STM32_RNG_CR                REG32(STM32_RNG_BASE + 0x0)
-#define STM32_RNG_CR_RNGEN          BIT(2)
-#define STM32_RNG_CR_IE             BIT(3)
-#define STM32_RNG_CR_CED            BIT(5)
-#define STM32_RNG_SR                REG32(STM32_RNG_BASE + 0x4)
-#define STM32_RNG_SR_DRDY           BIT(0)
-#define STM32_RNG_DR                REG32(STM32_RNG_BASE + 0x8)
+#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0)
+#define STM32_RNG_CR_RNGEN BIT(2)
+#define STM32_RNG_CR_IE BIT(3)
+#define STM32_RNG_CR_CED BIT(5)
+#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4)
+#define STM32_RNG_SR_DRDY BIT(0)
+#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8)
 
 /* --- AXI interconnect --- */
 
 /* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */
-#define STM32_AXI_TARG_FN_MOD(x)    REG32(STM32_GPV_BASE + 0x1108 + \
-					  0x1000 * (x))
-#define  WRITE_ISS_OVERRIDE         BIT(1)
-#define  READ_ISS_OVERRIDE          BIT(0)
+#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + 0x1000 * (x))
+#define WRITE_ISS_OVERRIDE BIT(1)
+#define READ_ISS_OVERRIDE BIT(0)
 
 /* --- MISC --- */
-#define STM32_UNIQUE_ID_ADDRESS     REG32_ADDR(STM32_UNIQUE_ID_BASE)
-#define STM32_UNIQUE_ID_LENGTH      (3 * 4)
+#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE)
+#define STM32_UNIQUE_ID_LENGTH (3 * 4)
 
 #endif /* !__ASSEMBLER__ */
diff --git a/chip/stm32/registers-stm32l4.h b/chip/stm32/registers-stm32l4.h
index 9fd6302f49..583f0a688a 100644
--- a/chip/stm32/registers-stm32l4.h
+++ b/chip/stm32/registers-stm32l4.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,533 +19,1792 @@
 #error "This header file should not be included directly."
 #endif
 
-/* --- IRQ numbers --- */
-#define STM32_IRQ_WWDG             0
-#define STM32_IRQ_PVD              1
-#define STM32_IRQ_TAMPER_STAMP     2
-#define STM32_IRQ_RTC_WAKEUP       3
-#define STM32_IRQ_FLASH            4
-#define STM32_IRQ_RCC              5
-#define STM32_IRQ_EXTI0            6
-#define STM32_IRQ_EXTI1            7
-#define STM32_IRQ_EXTI2            8
-#define STM32_IRQ_EXTI3            9
-#define STM32_IRQ_EXTI4           10
-#define STM32_IRQ_DMA_CHANNEL_1   11
-#define STM32_IRQ_DMA_CHANNEL_2   12
-#define STM32_IRQ_DMA_CHANNEL_3   13
-#define STM32_IRQ_DMA_CHANNEL_4   14
-#define STM32_IRQ_DMA_CHANNEL_5   15
-#define STM32_IRQ_DMA_CHANNEL_6   16
-#define STM32_IRQ_DMA_CHANNEL_7   17
-#define STM32_IRQ_USB_HP          19
-#define STM32_IRQ_USB_LP          20
-
-#define STM32_IRQ_ADC1            18 /* STM32L4 only */
-#define STM32_IRQ_CAN_TX          19 /* STM32F373 only */
-#define STM32_IRQ_USB_LP_CAN_RX   20 /* STM32F373 only */
-#define STM32_IRQ_DAC             21
-#define STM32_IRQ_CAN_RX1         21 /* STM32F373 only */
-
-#define STM32_IRQ_COMP            22
-
-#define STM32_IRQ_CAN_SCE         22 /* STM32F373 only */
-#define STM32_IRQ_EXTI9_5         23
-#define STM32_IRQ_LCD             24 /* STM32L15X only */
-#define STM32_IRQ_TIM15           24 /* STM32F373 only */
-#define STM32_IRQ_TIM9            25 /* STM32L15X only */
-#define STM32_IRQ_TIM16           25 /* STM32F373 only */
-#define STM32_IRQ_TIM10           26 /* STM32L15X only */
-#define STM32_IRQ_TIM17           26 /* STM32F373 only */
-#define STM32_IRQ_TIM11           27 /* STM32L15X only */
-#define STM32_IRQ_TIM18_DAC2      27 /* STM32F373 only */
-#define STM32_IRQ_TIM2            28
-#define STM32_IRQ_TIM3            29
-#define STM32_IRQ_TIM4            30
-#define STM32_IRQ_I2C1_EV         31
-#define STM32_IRQ_I2C1_ER         32
-#define STM32_IRQ_I2C2_EV         33
-#define STM32_IRQ_I2C2_ER         34
-#define STM32_IRQ_SPI1            35
-#define STM32_IRQ_SPI2            36
-#define STM32_IRQ_USART1          37
-#define STM32_IRQ_USART2          38
-#define STM32_IRQ_USART3          39
-#define STM32_IRQ_EXTI15_10       40
-#define STM32_IRQ_RTC_ALARM       41
-#define STM32_IRQ_USB_FS_WAKEUP   42 /* STM32L15X */
-#define STM32_IRQ_CEC             42 /* STM32F373 only */
-#define STM32_IRQ_TIM6_BASIC      43 /* STM32L15X only */
-#define STM32_IRQ_TIM12           43 /* STM32F373 only */
-#define STM32_IRQ_TIM7_BASIC      44 /* STM32L15X only */
-#define STM32_IRQ_TIM13           44 /* STM32F373 only */
-#define STM32_IRQ_TIM14           45 /* STM32F373 only */
-#define STM32_IRQ_TIM5            50 /* STM32F373 */
-#define STM32_IRQ_SPI3            51 /* STM32F373 */
-#define STM32_IRQ_USART4          52 /* STM32F446 only */
-#define STM32_IRQ_USART5          53 /* STM32F446 only */
-#define STM32_IRQ_TIM6_DAC        54 /* STM32F373 */
-#define STM32_IRQ_TIM7            55 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL1   56 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL2   57 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL3   58 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL4   59 /* STM32F373 only */
-/* if MISC_REMAP bits are set */
-#define STM32_IRQ_DMA2_CHANNEL5   60 /* STM32F373 */
-#define STM32_IRQ_SDADC1          61 /* STM32F373 only */
-#define STM32_IRQ_SDADC2          62 /* STM32F373 only */
-#define STM32_IRQ_SDADC3          63 /* STM32F373 only */
-#define STM32_IRQ_DMA2_CHANNEL6   68 /* STM32L4 only */
-#define STM32_IRQ_DMA2_CHANNEL7   69 /* STM32L4 only */
-#define STM32_IRQ_LPUART          70 /* STM32L4 only */
-#define STM32_IRQ_USART9          70 /* STM32L4 only */
-#define STM32_IRQ_USART6          71 /* STM32F446 only */
-#define STM32_IRQ_I2C3_EV         72 /* STM32F446 only */
-#define STM32_IRQ_I2C3_ER         73 /* STM32F446 only */
-#define STM32_IRQ_USB_WAKEUP      76 /* STM32F373 only */
-#define STM32_IRQ_TIM19           78 /* STM32F373 only */
-#define STM32_IRQ_AES             79 /* STM32L4 only */
-#define STM32_IRQ_RNG             80 /* STM32L4 only */
-#define STM32_IRQ_FPU             81 /* STM32F373 only */
-
+/******  STM32 specific Interrupt Numbers ********/
+#define STM32_IRQ_WWDG 0
+#define STM32_IRQ_PVD_PVM 1
+#define STM32_IRQ_TAMP_STAMP 2
+#define STM32_IRQ_RTC_WKUP 3
+#define STM32_IRQ_FLASH 4
+#define STM32_IRQ_RCC 5
+#define STM32_IRQ_EXTI0 6
+#define STM32_IRQ_EXTI1 7
+#define STM32_IRQ_EXTI2 8
+#define STM32_IRQ_EXTI3 9
+#define STM32_IRQ_EXTI4 10
+#define STM32_IRQ_DMA_CHANNEL_1 11
+#define STM32_IRQ_DMA_CHANNEL_2 12
+#define STM32_IRQ_DMA_CHANNEL_3 13
+#define STM32_IRQ_DMA_CHANNEL_4 14
+#define STM32_IRQ_DMA_CHANNEL_5 15
+#define STM32_IRQ_DMA_CHANNEL_6 16
+#define STM32_IRQ_DMA_CHANNEL_7 17
+#define STM32_IRQ_ADC1 18
+#define STM32_IRQ_CAN1_TX 19
+#define STM32_IRQ_CAN1_RX0 20
+#define STM32_IRQ_CAN1_RX1 21
+#define STM32_IRQ_CAN1_SCE 22
+#define STM32_IRQ_EXTI9_5 23
+#define STM32_IRQ_TIM1_BRK_TIM15 24
+#define STM32_IRQ_TIM1_UP_TIM16 25
+#define STM32_IRQ_TIM1_TRG_COM 26
+#define STM32_IRQ_TIM1_CC 27
+#define STM32_IRQ_TIM2 28
+#define STM32_IRQ_I2C1_EV 31
+#define STM32_IRQ_I2C1_ER 32
+#define STM32_IRQ_I2C2_EV 33
+#define STM32_IRQ_I2C2_ER 34
+#define STM32_IRQ_SPI1 35
+#define STM32_IRQ_SPI2 36
+#define STM32_IRQ_USART1 37
+#define STM32_IRQ_USART2 38
+#define STM32_IRQ_USART3 39
+#define STM32_IRQ_EXTI15_10 40
+#define STM32_IRQ_RTC_ALARM 41
+#define STM32_IRQ_SDMMC1 49
+#define STM32_IRQ_TIM5 50
+#define STM32_IRQ_SPI3 51
+#define STM32_IRQ_TIM6_DAC 54
+#define STM32_IRQ_TIM7 55
+#define STM32_IRQ_DMA2_CHANNEL1 56
+#define STM32_IRQ_DMA2_CHANNEL2 57
+#define STM32_IRQ_DMA2_CHANNEL3 58
+#define STM32_IRQ_DMA2_CHANNEL4 59
+#define STM32_IRQ_DMA2_CHANNEL5 60
+#define STM32_IRQ_COMP 64
+#define LSTM32_IRQ_PTIM1 65
+#define STM32_IRQ_LPTIM2 66
+#define STM32_IRQ_DMA2_CHANNEL6 68
+#define STM32_IRQ_DMA2_CHANNEL7 69
+#define STM32_IRQ_LPUART1 70
+#define STM32_IRQ_QUADSPI 71
+#define STM32_IRQ_I2C3_EV 72
+#define STM32_IRQ_I2C3_ER 73
+#define STM32_IRQ_SAI1 74
+#define STM32_IRQ_SWPMI1 76
+#define STM32_IRQ_TSC 77
+#define STM32_IRQ_RNG 80
+#define STM32_IRQ_FPU 81
+#define STM32_IRQ_CRS 82
 
 /* To simplify code generation, define DMA channel 9..10 */
-#define STM32_IRQ_DMA_CHANNEL_9    STM32_IRQ_DMA2_CHANNEL1
-#define STM32_IRQ_DMA_CHANNEL_10   STM32_IRQ_DMA2_CHANNEL2
-#define STM32_IRQ_DMA_CHANNEL_13   STM32_IRQ_DMA2_CHANNEL6
-#define STM32_IRQ_DMA_CHANNEL_14   STM32_IRQ_DMA2_CHANNEL7
-
-/* aliases for easier code sharing */
-#define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV
-#define STM32_IRQ_I2C2 STM32_IRQ_I2C2_EV
-#define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV
-
-
+#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1
+#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2
+#define STM32_IRQ_DMA_CHANNEL_11 STM32_IRQ_DMA2_CHANNEL3
+#define STM32_IRQ_DMA_CHANNEL_12 STM32_IRQ_DMA2_CHANNEL4
+#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL5
+#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL6
+#define STM32_IRQ_DMA_CHANNEL_15 STM32_IRQ_DMA2_CHANNEL7
+#define STM32_IRQ_USART9 STM32_IRQ_LPUART1
 
 /* Peripheral base addresses */
-#define STM32_ADC1_BASE             0x40012400
-#define STM32_ADC_BASE              0x40012700 /* STM32L15X only */
-
-#define STM32_CEC_BASE              0x40007800 /* STM32F373 */
-#define STM32_CRC_BASE              0x40023000
-#define STM32_CRS_BASE              0x40006c00 /* STM32F0XX */
-#define STM32_DAC_BASE              0x40007400
-
-
-#define STM32_DBGMCU_BASE           0xE0042000
-
-#define STM32_DMA1_BASE             0x40020000
-#define STM32_DMA2_BASE             0x40020400
-
-#define STM32_EXTI_BASE             0x40010400
-
-#define STM32_FLASH_REGS_BASE       0x40022000
-
-#define STM32_GPIOA_BASE            0x48000000
-#define STM32_GPIOB_BASE            0x48000400
-#define STM32_GPIOC_BASE            0x48000800
-#define STM32_GPIOD_BASE            0x48000C00
-#define STM32_GPIOE_BASE            0x48001000
-#define STM32_GPIOF_BASE            0x48001400
-#define STM32_GPIOG_BASE            0x48001800 /* only for stm32l4x6 */
-#define STM32_GPIOH_BASE            0x48001C00 /* only for stm32l4 */
-
-#define STM32_I2C1_BASE             0x40005400
-#define STM32_I2C2_BASE             0x40005800
-#define STM32_I2C3_BASE             0x40005C00
-#define STM32_I2C4_BASE             0x40006000
-
-#define STM32_IWDG_BASE             0x40003000
-#define STM32_LCD_BASE              0x40002400
-
-#define STM32_OPTB_BASE             0x1FFF7800
-
-#define STM32_PMSE_BASE             0x40013400
-#define STM32_PWR_BASE              0x40007000
-
-#define STM32_RCC_BASE              0x40021000
-
-#define STM32_RI_BASE               0x40007C00 /* STM32L1xx only */
-#define STM32_RNG_BASE              0x50060800 /* STM32L4 */
-#define STM32_RTC_BASE              0x40002800
-
-#define STM32_SPI1_BASE             0x40013000
-#define STM32_SPI2_BASE             0x40003800
-#define STM32_SPI3_BASE             0x40003c00 /* STM32F373, STM32L4, STM32F7 */
-
-#define STM32_SYSCFG_BASE           0x40010000
-
-#define STM32_TIM1_BASE             0x40012c00 /* STM32F373 */
-#define STM32_TIM2_BASE             0x40000000
-#define STM32_TIM3_BASE             0x40000400
-#define STM32_TIM4_BASE             0x40000800
-#define STM32_TIM5_BASE             0x40000c00 /* STM32F373 */
-#define STM32_TIM6_BASE             0x40001000
-#define STM32_TIM7_BASE             0x40001400
-#define STM32_TIM12_BASE            0x40001800 /* STM32F373 */
-#define STM32_TIM13_BASE            0x40001c00 /* STM32F373 */
-#define STM32_TIM14_BASE            0x40002000 /* STM32F373 */
-#define STM32_TIM15_BASE            0x40014000
-#define STM32_TIM16_BASE            0x40014400
-#define STM32_TIM17_BASE            0x40014800
-#define STM32_TIM18_BASE            0x40009c00 /* STM32F373 only */
-#define STM32_TIM19_BASE            0x40015c00 /* STM32F373 only */
-
-#define STM32_UNIQUE_ID_BASE        0x1ffff7ac
-
-#define STM32_USART1_BASE           0x40013800
-#define STM32_USART2_BASE           0x40004400
-#define STM32_USART3_BASE           0x40004800
-#define STM32_USART4_BASE           0x40004c00
-#define STM32_USART9_BASE           0x40008000 /* LPUART */
-
-#define STM32_USB_CAN_SRAM_BASE     0x40006000
-#define STM32_USB_FS_BASE           0x40005C00
-
-#define STM32_WWDG_BASE             0x40002C00
-
+#define FLASH_BASE 0x08000000UL
+#define FLASH_END 0x0803FFFFUL
+#define FLASH_BANK1_END 0x0803FFFFUL
+#define SRAM1_BASE 0x20000000UL
+#define SRAM2_BASE 0x10000000UL
+#define PERIPH_BASE 0x40000000UL
+#define QSPI_BASE 0x90000000UL
+#define QSPI_R_BASE 0xA0001000UL
+#define SRAM1_BB_BASE 0x22000000UL
+#define PERIPH_BB_BASE 0x42000000UL
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+#define SRAM1_SIZE_MAX 0x0000C000UL
+#define SRAM2_SIZE 0x00004000UL
+#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0)
+#define FLASH_SIZE                                                            \
+	(((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) ==     \
+	   0x0000FFFFU)) ?                                                    \
+		 (0x100U << 10U) :                                            \
+		 (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) \
+		  << 10U))
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)
+
+/*!< APB1 peripherals */
+#define STM32_TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
+#define STM32_TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
+#define STM32_TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
+#define STM32_TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
+#define STM32_RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
+#define STM32_WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
+#define STM32_IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
+#define STM32_SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
+#define STM32_SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
+#define STM32_USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
+#define STM32_USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
+#define STM32_I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
+#define STM32_I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
+#define STM32_I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)
+#define STM32_CRS_BASE (APB1PERIPH_BASE + 0x6000UL)
+#define STM32_CAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
+#define STM32_PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
+#define STM32_DAC_BASE (APB1PERIPH_BASE + 0x7400UL)
+#define STM32_DAC1_BASE (APB1PERIPH_BASE + 0x7400UL)
+#define STM32_OPAMP_BASE (APB1PERIPH_BASE + 0x7800UL)
+#define STM32_OPAMP1_BASE (APB1PERIPH_BASE + 0x7800UL)
+#define STM32_LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL)
+#define STM32_LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL)
+#define STM32_I2C4_BASE (APB1PERIPH_BASE + 0x8400UL)
+#define STM32_SWPMI1_BASE (APB1PERIPH_BASE + 0x8800UL)
+#define STM32_LPTIM2_BASE (APB1PERIPH_BASE + 0x9400UL)
+
+#define STM32_USART9_BASE STM32_LPUART1_BASE
+
+/*!< APB2 peripherals */
+#define STM32_SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL)
+#define STM32_VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL)
+#define STM32_OMP1_BASE (APB2PERIPH_BASE + 0x0200UL)
+#define STM32_COMP2_BASE (APB2PERIPH_BASE + 0x0204UL)
+#define STM32_EXTI_BASE (APB2PERIPH_BASE + 0x0400UL)
+#define STM32_FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00UL)
+#define STM32_SDMMC1_BASE (APB2PERIPH_BASE + 0x2800UL)
+#define STM32_TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL)
+#define STM32_SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
+#define STM32_USART1_BASE (APB2PERIPH_BASE + 0x3800UL)
+#define STM32_TIM15_BASE (APB2PERIPH_BASE + 0x4000UL)
+#define STM32_TIM16_BASE (APB2PERIPH_BASE + 0x4400UL)
+#define STM32_SAI1_BASE (APB2PERIPH_BASE + 0x5400UL)
+#define STM32_SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL)
+#define STM32_SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL)
+
+/*!< AHB1 peripherals */
+#define STM32_DMA1_BASE (AHB1PERIPH_BASE)
+#define STM32_DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL)
+#define STM32_RCC_BASE (AHB1PERIPH_BASE + 0x1000UL)
+#define STM32_FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL)
+#define STM32_CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
+#define STM32_TSC_BASE (AHB1PERIPH_BASE + 0x4000UL)
+#define STM32_DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL)
+#define STM32_DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL)
+#define STM32_DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL)
+#define STM32_DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL)
+#define STM32_DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL)
+#define STM32_DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL)
+#define STM32_DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL)
+#define STM32_DMA1_CSELR_BASE (DMA1_BASE + 0x00A8UL)
+#define STM32_DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL)
+#define STM32_DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL)
+#define STM32_DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL)
+#define STM32_DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL)
+#define STM32_DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL)
+#define STM32_DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL)
+#define STM32_DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL)
+#define STM32_DMA2_CSELR_BASE (DMA2_BASE + 0x00A8UL)
+
+/*!< AHB2 peripherals */
+#define STM32_GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL)
+#define STM32_GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL)
+#define STM32_GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL)
+#define STM32_GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL)
+#define STM32_GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL)
+#define STM32_GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL)
+#define STM32_GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL) /* stm32l4x6 */
+#define STM32_GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00UL)
+#define STM32_ADC1_BASE (AHB2PERIPH_BASE + 0x08040000UL)
+#define STM32_ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300UL)
+#define STM32_RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL)
+
+/* Debug MCU registers base address */
+#define STM32_DBGMCU_BASE 0xE0042000UL
+#define STM32_PACKAGE_BASE 0x1FFF7500UL
+#define STM32_UID_BASE 0x1FFF7590UL
+#define STM32_FLASHSIZE_BASE 0x1FFF75E0UL
+
+#define STM32_FLASH_REGS_BASE STM32_FLASH_R_BASE
+#define STM32_UNIQUE_ID_BASE STM32_UID_BASE
+#define STM32_OPTB_BASE 0x1FFF7800
 
 #ifndef __ASSEMBLER__
 
 /* Register definitions */
 
 /* --- USART --- */
-#define STM32_USART_CR1(base)      STM32_USART_REG(base, 0x00)
-#define STM32_USART_CR1_UE		BIT(0)
-#define STM32_USART_CR1_UESM            BIT(1)
-#define STM32_USART_CR1_RE		BIT(2)
-#define STM32_USART_CR1_TE		BIT(3)
-#define STM32_USART_CR1_RXNEIE		BIT(5)
-#define STM32_USART_CR1_TCIE		BIT(6)
-#define STM32_USART_CR1_TXEIE		BIT(7)
-#define STM32_USART_CR1_PS		BIT(9)
-#define STM32_USART_CR1_PCE		BIT(10)
-#define STM32_USART_CR1_M		BIT(12)
-#define STM32_USART_CR1_OVER8		BIT(15)
-#define STM32_USART_CR2(base)      STM32_USART_REG(base, 0x04)
-#define STM32_USART_CR2_SWAP		BIT(15)
-#define STM32_USART_CR3(base)      STM32_USART_REG(base, 0x08)
-#define STM32_USART_CR3_EIE		BIT(0)
-#define STM32_USART_CR3_DMAR		BIT(6)
-#define STM32_USART_CR3_DMAT		BIT(7)
-#define STM32_USART_CR3_ONEBIT		BIT(11)
-#define STM32_USART_CR3_OVRDIS		BIT(12)
-#define STM32_USART_CR3_WUS_START_BIT	(2 << 20)
-#define STM32_USART_CR3_WUFIE		BIT(22)
-#define STM32_USART_BRR(base)      STM32_USART_REG(base, 0x0C)
-#define STM32_USART_GTPR(base)     STM32_USART_REG(base, 0x10)
-#define STM32_USART_RTOR(base)     STM32_USART_REG(base, 0x14)
-#define STM32_USART_RQR(base)      STM32_USART_REG(base, 0x18)
-#define STM32_USART_ISR(base)      STM32_USART_REG(base, 0x1C)
-#define STM32_USART_ICR(base)      STM32_USART_REG(base, 0x20)
-#define STM32_USART_ICR_ORECF		BIT(3)
-#define STM32_USART_ICR_TCCF		BIT(6)
-#define STM32_USART_RDR(base)      STM32_USART_REG(base, 0x24)
-#define STM32_USART_TDR(base)      STM32_USART_REG(base, 0x28)
-#define STM32_USART_PRESC(base)    STM32_USART_REG(base, 0x2C)
+#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00)
+#define STM32_USART_CR1_UE BIT(0)
+#define STM32_USART_CR1_UESM BIT(1)
+#define STM32_USART_CR1_RE BIT(2)
+#define STM32_USART_CR1_TE BIT(3)
+#define STM32_USART_CR1_RXNEIE BIT(5)
+#define STM32_USART_CR1_TCIE BIT(6)
+#define STM32_USART_CR1_TXEIE BIT(7)
+#define STM32_USART_CR1_PS BIT(9)
+#define STM32_USART_CR1_PCE BIT(10)
+#define STM32_USART_CR1_M BIT(12)
+#define STM32_USART_CR1_OVER8 BIT(15)
+
+#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04)
+#define STM32_USART_CR2_SWAP BIT(15)
+
+#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08)
+#define STM32_USART_CR3_EIE BIT(0)
+#define STM32_USART_CR3_DMAR BIT(6)
+#define STM32_USART_CR3_DMAT BIT(7)
+#define STM32_USART_CR3_ONEBIT BIT(11)
+#define STM32_USART_CR3_OVRDIS BIT(12)
+#define STM32_USART_CR3_WUS_START_BIT (2 << 20)
+#define STM32_USART_CR3_WUFIE BIT(22)
+
+#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C)
+#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10)
+#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14)
+#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18)
+#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C)
+#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20)
+#define STM32_USART_ICR_ORECF BIT(3)
+#define STM32_USART_ICR_TCCF BIT(6)
+#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24)
+#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28)
+#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C)
 /* register alias */
-#define STM32_USART_SR(base)       STM32_USART_ISR(base)
-#define STM32_USART_SR_ORE		BIT(3)
-#define STM32_USART_SR_RXNE		BIT(5)
-#define STM32_USART_SR_TC		BIT(6)
-#define STM32_USART_SR_TXE		BIT(7)
+#define STM32_USART_SR(base) STM32_USART_ISR(base)
+#define STM32_USART_SR_ORE BIT(3)
+#define STM32_USART_SR_RXNE BIT(5)
+#define STM32_USART_SR_TC BIT(6)
+#define STM32_USART_SR_TXE BIT(7)
 
 /* --- GPIO --- */
-
-#define STM32_GPIO_MODER(b)     REG32((b) + 0x00)
-#define STM32_GPIO_OTYPER(b)    REG16((b) + 0x04)
-#define STM32_GPIO_OSPEEDR(b)   REG32((b) + 0x08)
-#define STM32_GPIO_PUPDR(b)     REG32((b) + 0x0C)
-#define STM32_GPIO_IDR(b)       REG16((b) + 0x10)
-#define STM32_GPIO_ODR(b)       REG16((b) + 0x14)
-#define STM32_GPIO_BSRR(b)      REG32((b) + 0x18)
-#define STM32_GPIO_LCKR(b)      REG32((b) + 0x1C)
-#define STM32_GPIO_AFRL(b)      REG32((b) + 0x20)
-#define STM32_GPIO_AFRH(b)      REG32((b) + 0x24)
-#define STM32_GPIO_BRR(b)       REG32((b) + 0x28)
-#define STM32_GPIO_ASCR(b)      REG32((b) + 0x2C) /* only for stm32l4 */
-
-#define GPIO_ALT_F0		0x0
-#define GPIO_ALT_F1		0x1
-#define GPIO_ALT_F2		0x2
-#define GPIO_ALT_F3		0x3
-#define GPIO_ALT_F4		0x4
-#define GPIO_ALT_F5		0x5
-#define GPIO_ALT_F6		0x6
-#define GPIO_ALT_F7		0x7
-#define GPIO_ALT_F8		0x8
-#define GPIO_ALT_F9		0x9
-#define GPIO_ALT_FA		0xA
-#define GPIO_ALT_FB		0xB
-#define GPIO_ALT_FC		0xC
-#define GPIO_ALT_FD		0xD
-#define GPIO_ALT_FE		0xE
-#define GPIO_ALT_FF		0xF
+#define STM32_GPIO_MODER(b) REG32((b) + 0x00)
+#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04)
+#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08)
+#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C)
+#define STM32_GPIO_IDR(b) REG16((b) + 0x10)
+#define STM32_GPIO_ODR(b) REG16((b) + 0x14)
+#define STM32_GPIO_BSRR(b) REG32((b) + 0x18)
+#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C)
+#define STM32_GPIO_AFRL(b) REG32((b) + 0x20)
+#define STM32_GPIO_AFRH(b) REG32((b) + 0x24)
+#define STM32_GPIO_BRR(b) REG32((b) + 0x28)
+#define STM32_GPIO_ASCR(b) REG32((b) + 0x2C) /* only for stm32l4x6 */
+
+#define GPIO_ALT_F0 0x0
+#define GPIO_ALT_F1 0x1
+#define GPIO_ALT_F2 0x2
+#define GPIO_ALT_F3 0x3
+#define GPIO_ALT_F4 0x4
+#define GPIO_ALT_F5 0x5
+#define GPIO_ALT_F6 0x6
+#define GPIO_ALT_F7 0x7
+#define GPIO_ALT_F8 0x8
+#define GPIO_ALT_F9 0x9
+#define GPIO_ALT_FA 0xA
+#define GPIO_ALT_FB 0xB
+#define GPIO_ALT_FC 0xC
+#define GPIO_ALT_FD 0xD
+#define GPIO_ALT_FE 0xE
+#define GPIO_ALT_FF 0xF
 
 /* --- I2C --- */
-#define STM32_I2C_CR1(n)            REG32(stm32_i2c_reg(n, 0x00))
-#define STM32_I2C_CR1_PE            BIT(0)
-#define STM32_I2C_CR1_TXIE          BIT(1)
-#define STM32_I2C_CR1_RXIE          BIT(2)
-#define STM32_I2C_CR1_ADDRIE        BIT(3)
-#define STM32_I2C_CR1_NACKIE        BIT(4)
-#define STM32_I2C_CR1_STOPIE        BIT(5)
-#define STM32_I2C_CR1_ERRIE         BIT(7)
-#define STM32_I2C_CR1_WUPEN         BIT(18)
-#define STM32_I2C_CR2(n)            REG32(stm32_i2c_reg(n, 0x04))
-#define STM32_I2C_CR2_RD_WRN        BIT(10)
-#define STM32_I2C_CR2_START         BIT(13)
-#define STM32_I2C_CR2_STOP          BIT(14)
-#define STM32_I2C_CR2_NACK          BIT(15)
-#define STM32_I2C_CR2_RELOAD        BIT(24)
-#define STM32_I2C_CR2_AUTOEND       BIT(25)
-#define STM32_I2C_OAR1(n)           REG32(stm32_i2c_reg(n, 0x08))
-#define STM32_I2C_OAR2(n)           REG32(stm32_i2c_reg(n, 0x0C))
-#define STM32_I2C_TIMINGR(n)        REG32(stm32_i2c_reg(n, 0x10))
-#define STM32_I2C_TIMEOUTR(n)       REG32(stm32_i2c_reg(n, 0x14))
-#define STM32_I2C_ISR(n)            REG32(stm32_i2c_reg(n, 0x18))
-#define STM32_I2C_ISR_TXE           BIT(0)
-#define STM32_I2C_ISR_TXIS          BIT(1)
-#define STM32_I2C_ISR_RXNE          BIT(2)
-#define STM32_I2C_ISR_ADDR          BIT(3)
-#define STM32_I2C_ISR_NACK          BIT(4)
-#define STM32_I2C_ISR_STOP          BIT(5)
-#define STM32_I2C_ISR_TC            BIT(6)
-#define STM32_I2C_ISR_TCR           BIT(7)
-#define STM32_I2C_ISR_BERR          BIT(8)
-#define STM32_I2C_ISR_ARLO          BIT(9)
-#define STM32_I2C_ISR_OVR           BIT(10)
-#define STM32_I2C_ISR_PECERR        BIT(11)
-#define STM32_I2C_ISR_TIMEOUT       BIT(12)
-#define STM32_I2C_ISR_ALERT         BIT(13)
-#define STM32_I2C_ISR_BUSY          BIT(15)
-#define STM32_I2C_ISR_DIR           BIT(16)
-#define STM32_I2C_ISR_ADDCODE(isr)  (((isr) >> 16) & 0xfe)
-#define STM32_I2C_ICR(n)            REG32(stm32_i2c_reg(n, 0x1C))
-#define STM32_I2C_ICR_ADDRCF        BIT(3)
-#define STM32_I2C_ICR_NACKCF        BIT(4)
-#define STM32_I2C_ICR_STOPCF        BIT(5)
-#define STM32_I2C_ICR_BERRCF        BIT(8)
-#define STM32_I2C_ICR_ARLOCF        BIT(9)
-#define STM32_I2C_ICR_OVRCF         BIT(10)
-#define STM32_I2C_ICR_TIMEOUTCF     BIT(12)
-#define STM32_I2C_ICR_ALL           0x3F38
-#define STM32_I2C_PECR(n)           REG32(stm32_i2c_reg(n, 0x20))
-#define STM32_I2C_RXDR(n)           REG32(stm32_i2c_reg(n, 0x24))
-#define STM32_I2C_TXDR(n)           REG32(stm32_i2c_reg(n, 0x28))
-
+#define STM32_I2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00))
+#define STM32_I2C_CR1_PE BIT(0)
+#define STM32_I2C_CR1_TXIE BIT(1)
+#define STM32_I2C_CR1_RXIE BIT(2)
+#define STM32_I2C_CR1_ADDRIE BIT(3)
+#define STM32_I2C_CR1_NACKIE BIT(4)
+#define STM32_I2C_CR1_STOPIE BIT(5)
+#define STM32_I2C_CR1_ERRIE BIT(7)
+#define STM32_I2C_CR1_WUPEN BIT(18)
+#define STM32_I2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04))
+#define STM32_I2C_CR2_RD_WRN BIT(10)
+#define STM32_I2C_CR2_START BIT(13)
+#define STM32_I2C_CR2_STOP BIT(14)
+#define STM32_I2C_CR2_NACK BIT(15)
+#define STM32_I2C_CR2_RELOAD BIT(24)
+#define STM32_I2C_CR2_AUTOEND BIT(25)
+#define STM32_I2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08))
+#define STM32_I2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C))
+#define STM32_I2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10))
+#define STM32_I2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14))
+#define STM32_I2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18))
+#define STM32_I2C_ISR_TXE BIT(0)
+#define STM32_I2C_ISR_TXIS BIT(1)
+#define STM32_I2C_ISR_RXNE BIT(2)
+#define STM32_I2C_ISR_ADDR BIT(3)
+#define STM32_I2C_ISR_NACK BIT(4)
+#define STM32_I2C_ISR_STOP BIT(5)
+#define STM32_I2C_ISR_TC BIT(6)
+#define STM32_I2C_ISR_TCR BIT(7)
+#define STM32_I2C_ISR_BERR BIT(8)
+#define STM32_I2C_ISR_ARLO BIT(9)
+#define STM32_I2C_ISR_OVR BIT(10)
+#define STM32_I2C_ISR_PECERR BIT(11)
+#define STM32_I2C_ISR_TIMEOUT BIT(12)
+#define STM32_I2C_ISR_ALERT BIT(13)
+#define STM32_I2C_ISR_BUSY BIT(15)
+#define STM32_I2C_ISR_DIR BIT(16)
+#define STM32_I2C_ISR_ADDCODE(isr) (((isr) >> 16) & 0xfe)
+#define STM32_I2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C))
+#define STM32_I2C_ICR_ADDRCF BIT(3)
+#define STM32_I2C_ICR_NACKCF BIT(4)
+#define STM32_I2C_ICR_STOPCF BIT(5)
+#define STM32_I2C_ICR_BERRCF BIT(8)
+#define STM32_I2C_ICR_ARLOCF BIT(9)
+#define STM32_I2C_ICR_OVRCF BIT(10)
+#define STM32_I2C_ICR_TIMEOUTCF BIT(12)
+#define STM32_I2C_ICR_ALL 0x3F38
+#define STM32_I2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20))
+#define STM32_I2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24))
+#define STM32_I2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28))
 
 /* --- Power / Reset / Clocks --- */
-#define STM32_PWR_CR2               REG32(STM32_PWR_BASE + 0x04)
-#define STM32_PWR_CSR               REG32(STM32_PWR_BASE + 0x10)
-
-
-#define STM32_RCC_CR			REG32(STM32_RCC_BASE + 0x00)
-#define STM32_RCC_CR_MSION		BIT(0)
-#define STM32_RCC_CR_MSIRDY		BIT(1)
-#define STM32_RCC_CR_HSION		BIT(8)
-#define STM32_RCC_CR_HSIRDY		BIT(10)
-#define STM32_RCC_CR_HSEON		BIT(16)
-#define STM32_RCC_CR_HSERDY		BIT(17)
-#define STM32_RCC_CR_PLLON		BIT(24)
-#define STM32_RCC_CR_PLLRDY		BIT(25)
-
-#define STM32_RCC_ICSCR			REG32(STM32_RCC_BASE + 0x04)
-#define STM32_RCC_ICSCR_MSIRANGE(n)	((n) << 13)
-#define STM32_RCC_ICSCR_MSIRANGE_1MHZ	STM32_RCC_ICSCR_MSIRANGE(4)
-#define STM32_RCC_ICSCR_MSIRANGE_2MHZ	STM32_RCC_ICSCR_MSIRANGE(5)
-#define STM32_RCC_ICSCR_MSIRANGE_MASK	STM32_RCC_ICSCR_MSIRANGE(7)
-
-#define STM32_RCC_CFGR			REG32(STM32_RCC_BASE + 0x08)
-#define STM32_RCC_CFGR_SW_MSI		(0 << 0)
-#define STM32_RCC_CFGR_SW_HSI		(1 << 0)
-#define STM32_RCC_CFGR_SW_HSE		(2 << 0)
-#define STM32_RCC_CFGR_SW_PLL		(3 << 0)
-#define STM32_RCC_CFGR_SW_MASK		(3 << 0)
-#define STM32_RCC_CFGR_SWS_MSI		(0 << 2)
-#define STM32_RCC_CFGR_SWS_HSI		(1 << 2)
-#define STM32_RCC_CFGR_SWS_HSE		(2 << 2)
-#define STM32_RCC_CFGR_SWS_PLL		(3 << 2)
-#define STM32_RCC_CFGR_SWS_MASK		(3 << 2)
-
-#define STM32_RCC_PLLCFGR		REG32(STM32_RCC_BASE + 0x0C)
-#define STM32_RCC_PLLCFGR_PLLSRC_SHIFT	(0)
-#define STM32_RCC_PLLCFGR_PLLSRC_NONE	(0 << STM32_RCC_PLLCFGR_PLLSRC_SHIFT)
-#define STM32_RCC_PLLCFGR_PLLSRC_MSI	(1 << STM32_RCC_PLLCFGR_PLLSRC_SHIFT)
-#define STM32_RCC_PLLCFGR_PLLSRC_HSI	(2 << STM32_RCC_PLLCFGR_PLLSRC_SHIFT)
-#define STM32_RCC_PLLCFGR_PLLSRC_HSE	(3 << STM32_RCC_PLLCFGR_PLLSRC_SHIFT)
-#define STM32_RCC_PLLCFGR_PLLSRC_MASK	(3 << STM32_RCC_PLLCFGR_PLLSRC_SHIFT)
-#define STM32_RCC_PLLCFGR_PLLM_SHIFT	(4)
-#define STM32_RCC_PLLCFGR_PLLM_MASK	(0x7 << STM32_RCC_PLLCFGR_PLLM_SHIFT)
-#define STM32_RCC_PLLCFGR_PLLN_SHIFT	(8)
-#define STM32_RCC_PLLCFGR_PLLN_MASK	(0x7f << STM32_RCC_PLLCFGR_PLLN_SHIFT)
-#define STM32_RCC_PLLCFGR_PLLREN_SHIFT	(24)
-#define STM32_RCC_PLLCFGR_PLLREN_MASK	(1 << STM32_RCC_PLLCFGR_PLLREN_SHIFT)
-#define STM32_RCC_PLLCFGR_PLLR_SHIFT	(25)
-#define STM32_RCC_PLLCFGR_PLLR_MASK	(3 << STM32_RCC_PLLCFGR_PLLR_SHIFT)
-
-#define STM32_RCC_AHB1RSTR              REG32(STM32_RCC_BASE + 0x28)
-#define STM32_RCC_AHB2RSTR              REG32(STM32_RCC_BASE + 0x2C)
-#define STM32_RCC_AHB3RSTR              REG32(STM32_RCC_BASE + 0x30)
-#define STM32_RCC_APB1RSTR1             REG32(STM32_RCC_BASE + 0x38)
-#define STM32_RCC_APB1RSTR2             REG32(STM32_RCC_BASE + 0x3C)
-#define STM32_RCC_APB2RSTR              REG32(STM32_RCC_BASE + 0x40)
-
-#define STM32_RCC_AHB1ENR		REG32(STM32_RCC_BASE + 0x48)
-#define STM32_RCC_AHB1ENR_DMA1EN	BIT(0)
-#define STM32_RCC_AHB1ENR_DMA2EN	BIT(1)
-
-#define STM32_RCC_AHB2ENR		REG32(STM32_RCC_BASE + 0x4C)
-#define STM32_RCC_AHB2ENR_GPIOMASK	(0xff << 0)
-#define STM32_RCC_AHB2ENR_RNGEN		BIT(18)
-
-#define STM32_RCC_APB1ENR		REG32(STM32_RCC_BASE + 0x58)
-#define STM32_RCC_PWREN                 BIT(28)
-
-#define STM32_RCC_APB1ENR2		REG32(STM32_RCC_BASE + 0x5C)
-#define STM32_RCC_APB1ENR2_LPUART1EN	BIT(0)
-
-#define STM32_RCC_APB2ENR		REG32(STM32_RCC_BASE + 0x60)
-#define STM32_RCC_SYSCFGEN		BIT(0)
-
-#define STM32_RCC_CCIPR			REG32(STM32_RCC_BASE + 0x88)
+#define STM32_PWR_CR1 REG32(STM32_PWR_BASE + 0x00)
+#define STM32_PWR_CR2 REG32(STM32_PWR_BASE + 0x04)
+#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x10)
+#define STM32_PWR_SCR REG32(STM32_PWR_BASE + 0x18)
+
+#define PWR_CR1_LPMS_POS 0U
+#define PWR_CR1_LPMS_MSK (0x7UL << PWR_CR1_LPMS_POS)
+#define PWR_CR1_LPMS PWR_CR1_LPMS_MSK
+#define PWR_CR1_LPMS_STOP0 (0x00000000UL)
+#define PWR_CR1_LPMS_STOP1_POS 0U
+#define PWR_CR1_LPMS_STOP1_MSK (0x1UL << PWR_CR1_LPMS_STOP1_POS)
+#define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_MSK
+#define PWR_CR1_LPMS_STOP2_POS 1U
+#define PWR_CR1_LPMS_STOP2_MSK (0x1UL << PWR_CR1_LPMS_STOP2_POS)
+#define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_MSK
+#define PWR_CR1_LPMS_STANDBY_POS 0U
+#define PWR_CR1_LPMS_STANDBY_MSK (0x3UL << PWR_CR1_LPMS_STANDBY_POS)
+#define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_MSK
+#define PWR_CR1_LPMS_SHUTDOWN_POS 2U
+#define PWR_CR1_LPMS_SHUTDOWN_MSK (0x1UL << PWR_CR1_LPMS_SHUTDOWN_POS)
+#define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_MSK
+#define PWR_CR1_VOS_POS 9U
+#define PWR_CR1_VOS_MSK (0x3UL << PWR_CR1_VOS_POS)
+#define PWR_CR1_VOS PWR_CR1_VOS_MSK
+#define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_POS)
+#define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_POS)
+
+/* --- Macro usage in ec code --- */
+#define STM32_RCC_AHB2ENR_GPIOMASK                               \
+	(STM32_RCC_AHB2ENR_GPIOAEN | STM32_RCC_AHB2ENR_GPIOBEN | \
+	 STM32_RCC_AHB2ENR_GPIOCEN | STM32_RCC_AHB2ENR_GPIODEN | \
+	 STM32_RCC_AHB2ENR_GPIOEEN | STM32_RCC_AHB2ENR_GPIOHEN)
+#define STM32_RCC_ICSCR_MSIRANGE(n) ((n) << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_ICSCR_MSIRANGE_1MHZ STM32_RCC_ICSCR_MSIRANGE(4)
+#define STM32_RCC_ICSCR_MSIRANGE_2MHZ STM32_RCC_ICSCR_MSIRANGE(5)
+#define STM32_RCC_ICSCR_MSIRANGE_MASK STM32_RCC_CR_MSIRANGE_MSK
+#define STM32_RCC_SYSCFGEN STM32_RCC_APB2ENR_SYSCFGEN
+
+#define STM32_RCC_PB2_TIM1 STM32_RCC_APB2ENR_TIM1EN
+#define STM32_RCC_PB2_TIM15 STM32_RCC_APB2ENR_TIM15EN
+#define STM32_RCC_PB2_TIM16 STM32_RCC_APB2ENR_TIM16EN
+#ifndef CHIP_VARIANT_STM32L431X
+#define STM32_RCC_PB2_TIM8 BIT(13)
+#endif
+#define STM32_RCC_PWREN STM32_RCC_APB1ENR1_PWREN
+
+#define STM32_RCC_AHB2ENR_GPIO_PORTA BIT(0)
+#define STM32_RCC_AHB2ENR_GPIO_PORTB BIT(1)
+#define STM32_RCC_AHB2ENR_GPIO_PORTC BIT(2)
+#define STM32_RCC_AHB2ENR_GPIO_PORTD BIT(3)
+#define STM32_RCC_AHB2ENR_GPIO_PORTE BIT(4)
+#define STM32_RCC_AHB2ENR_GPIO_PORTH BIT(7)
 #define STM32_RCC_CCIPR_USART1SEL_SHIFT (0)
-#define STM32_RCC_CCIPR_USART1SEL_MASK  (3 << STM32_RCC_CCIPR_USART1SEL_SHIFT)
+#define STM32_RCC_CCIPR_USART1SEL_MASK (3 << STM32_RCC_CCIPR_USART1SEL_SHIFT)
 #define STM32_RCC_CCIPR_USART2SEL_SHIFT (2)
-#define STM32_RCC_CCIPR_USART2SEL_MASK  (3 << STM32_RCC_CCIPR_USART2SEL_SHIFT)
+#define STM32_RCC_CCIPR_USART2SEL_MASK (3 << STM32_RCC_CCIPR_USART2SEL_SHIFT)
 #define STM32_RCC_CCIPR_USART3SEL_SHIFT (4)
-#define STM32_RCC_CCIPR_USART3SEL_MASK  (3 << STM32_RCC_CCIPR_USART3SEL_SHIFT)
+#define STM32_RCC_CCIPR_USART3SEL_MASK (3 << STM32_RCC_CCIPR_USART3SEL_SHIFT)
 #define STM32_RCC_CCIPR_UART4SEL_SHIFT (6)
-#define STM32_RCC_CCIPR_UART4SEL_MASK  (3 << STM32_RCC_CCIPR_UART4SEL_SHIFT)
+#define STM32_RCC_CCIPR_UART4SEL_MASK (3 << STM32_RCC_CCIPR_UART4SEL_SHIFT)
 #define STM32_RCC_CCIPR_UART5SEL_SHIFT (8)
-#define STM32_RCC_CCIPR_UART5SEL_MASK  (3 << STM32_RCC_CCIPR_UART5SEL_SHIFT)
+#define STM32_RCC_CCIPR_UART5SEL_MASK (3 << STM32_RCC_CCIPR_UART5SEL_SHIFT)
 #define STM32_RCC_CCIPR_LPUART1SEL_SHIFT (10)
-#define STM32_RCC_CCIPR_LPUART1SEL_MASK  (3 << STM32_RCC_CCIPR_LPUART1SEL_SHIFT)
+#define STM32_RCC_CCIPR_LPUART1SEL_MASK (3 << STM32_RCC_CCIPR_LPUART1SEL_SHIFT)
 #define STM32_RCC_CCIPR_I2C1SEL_SHIFT (12)
-#define STM32_RCC_CCIPR_I2C1SEL_MASK  (3 << STM32_RCC_CCIPR_I2C1SEL_SHIFT)
+#define STM32_RCC_CCIPR_I2C1SEL_MASK (3 << STM32_RCC_CCIPR_I2C1SEL_SHIFT)
 #define STM32_RCC_CCIPR_I2C2SEL_SHIFT (14)
-#define STM32_RCC_CCIPR_I2C2SEL_MASK  (3 << STM32_RCC_CCIPR_I2C2SEL_SHIFT)
+#define STM32_RCC_CCIPR_I2C2SEL_MASK (3 << STM32_RCC_CCIPR_I2C2SEL_SHIFT)
 #define STM32_RCC_CCIPR_I2C3SEL_SHIFT (16)
-#define STM32_RCC_CCIPR_I2C3SEL_MASK  (3 << STM32_RCC_CCIPR_I2C3SEL_SHIFT)
+#define STM32_RCC_CCIPR_I2C3SEL_MASK (3 << STM32_RCC_CCIPR_I2C3SEL_SHIFT)
 #define STM32_RCC_CCIPR_LPTIM1SEL_SHIFT (18)
-#define STM32_RCC_CCIPR_LPTIM1SEL_MASK  (3 << STM32_RCC_CCIPR_LPTIM1SEL_SHIFT)
+#define STM32_RCC_CCIPR_LPTIM1SEL_MASK (3 << STM32_RCC_CCIPR_LPTIM1SEL_SHIFT)
 #define STM32_RCC_CCIPR_LPTIM2SEL_SHIFT (20)
-#define STM32_RCC_CCIPR_LPTIM2SEL_MASK  (3 << STM32_RCC_CCIPR_LPTIM2SEL_SHIFT)
+#define STM32_RCC_CCIPR_LPTIM2SEL_MASK (3 << STM32_RCC_CCIPR_LPTIM2SEL_SHIFT)
 #define STM32_RCC_CCIPR_SAI1SEL_SHIFT (22)
-#define STM32_RCC_CCIPR_SAI1SEL_MASK  (3 << STM32_RCC_CCIPR_SAI1SEL_SHIFT)
+#define STM32_RCC_CCIPR_SAI1SEL_MASK (3 << STM32_RCC_CCIPR_SAI1SEL_SHIFT)
 #define STM32_RCC_CCIPR_SAI2SEL_SHIFT (24)
-#define STM32_RCC_CCIPR_SAI2SEL_MASK  (3 << STM32_RCC_CCIPR_SAI2SEL_SHIFT)
+#define STM32_RCC_CCIPR_SAI2SEL_MASK (3 << STM32_RCC_CCIPR_SAI2SEL_SHIFT)
 #define STM32_RCC_CCIPR_CLK48SEL_SHIFT (26)
-#define STM32_RCC_CCIPR_CLK48SEL_MASK  (3 << STM32_RCC_CCIPR_CLK48SEL_SHIFT)
+#define STM32_RCC_CCIPR_CLK48SEL_MASK (3 << STM32_RCC_CCIPR_CLK48SEL_SHIFT)
 #define STM32_RCC_CCIPR_ADCSEL_SHIFT (28)
-#define STM32_RCC_CCIPR_ADCSEL_MASK  (3 << STM32_RCC_CCIPR_ADCSEL_SHIFT)
+#define STM32_RCC_CCIPR_ADCSEL_MASK (3 << STM32_RCC_CCIPR_ADCSEL_SHIFT)
 #define STM32_RCC_CCIPR_SWPMI1SEL_SHIFT (30)
-#define STM32_RCC_CCIPR_SWPMI1SEL_MASK  BIT(STM32_RCC_CCIPR_SWPMI1SEL_SHIFT)
+#define STM32_RCC_CCIPR_SWPMI1SEL_MASK BIT(STM32_RCC_CCIPR_SWPMI1SEL_SHIFT)
 #define STM32_RCC_CCIPR_DFSDM1SEL_SHIFT (31)
-#define STM32_RCC_CCIPR_DFSDM1SEL_MASK  BIT(STM32_RCC_CCIPR_DFSDM1SEL_SHIFT)
-
+#define STM32_RCC_CCIPR_DFSDM1SEL_MASK BIT(STM32_RCC_CCIPR_DFSDM1SEL_SHIFT)
 /* Possible clock sources for each peripheral */
-#define STM32_RCC_CCIPR_UART_PCLK 	0
-#define STM32_RCC_CCIPR_UART_SYSCLK	1
-#define STM32_RCC_CCIPR_UART_HSI16	2
-#define STM32_RCC_CCIPR_UART_LSE	3
-
-#define STM32_RCC_CCIPR_I2C_PCLK	0
-#define STM32_RCC_CCIPR_I2C_SYSCLK	1
-#define STM32_RCC_CCIPR_I2C_HSI16	2
-
-#define STM32_RCC_CCIPR_LPTIM_PCLK	0
-#define STM32_RCC_CCIPR_LPTIM_LSI	1
-#define STM32_RCC_CCIPR_LPTIM_HSI16	2
-#define STM32_RCC_CCIPR_LPTIM_LSE	3
-
-#define STM32_RCC_CCIPR_SAI_PLLSAI1CLK	0
-#define STM32_RCC_CCIPR_SAI_PLLSAI2CLK	1
-#define STM32_RCC_CCIPR_SAI_PLLSAI3CLK	2
-#define STM32_RCC_CCIPR_SAI_EXTCLK		3
-
-#define STM32_RCC_CCIPR_CLK48_NONE			0
-#define STM32_RCC_CCIPR_CLK48_PLL48M2CLK	1
-#define STM32_RCC_CCIPR_CLK48_PLL48M1CLK	2
-#define STM32_RCC_CCIPR_CLK48_MSI			3
-
-#define STM32_RCC_CCIPR_ADC_NONE		0
-#define STM32_RCC_CCIPR_ADC_PLLADC1CLK	1
-#define STM32_RCC_CCIPR_ADC_PLLADC2CLK	2
-#define STM32_RCC_CCIPR_ADC_SYSCLK	3
-
-#define STM32_RCC_CCIPR_SWPMI_PCLK	0
-#define STM32_RCC_CCIPR_SWPMI_HSI16	1
-
-#define STM32_RCC_CCIPR_DFSDM_PCLK		0
-#define STM32_RCC_CCIPR_DFSDM_SYSCLK	1
-
-#define STM32_RCC_BDCR			REG32(STM32_RCC_BASE + 0x90)
-
-#define STM32_RCC_CSR			REG32(STM32_RCC_BASE + 0x94)
-
-#define STM32_RCC_CRRCR			REG32(STM32_RCC_BASE + 0x98)
-
-#define STM32_RCC_CRRCR_HSI48ON         BIT(0)
-#define STM32_RCC_CRRCR_HSI48RDY        BIT(1)
-#define STM32_RCC_CRRCR_HSI48CAL_MASK   (0x1ff << 7)
-
-#define STM32_RCC_PB2_TIM1		BIT(11)
-#define STM32_RCC_PB2_TIM8		BIT(13)
-
-#define STM32_SYSCFG_EXTICR(n)		REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
-
-
-/* Peripheral bits for RCC_APB/AHB and DBGMCU regs */
-#define STM32_RCC_PB2_USART1		BIT(14)
+#define STM32_RCC_CCIPR_UART_PCLK 0
+#define STM32_RCC_CCIPR_UART_SYSCLK 1
+#define STM32_RCC_CCIPR_UART_HSI16 2
+#define STM32_RCC_CCIPR_UART_LSE 3
+
+#define STM32_RCC_CCIPR_I2C_PCLK 0
+#define STM32_RCC_CCIPR_I2C_SYSCLK 1
+#define STM32_RCC_CCIPR_I2C_HSI16 2
+
+#define STM32_RCC_CCIPR_LPTIM_PCLK 0
+#define STM32_RCC_CCIPR_LPTIM_LSI 1
+#define STM32_RCC_CCIPR_LPTIM_HSI16 2
+#define STM32_RCC_CCIPR_LPTIM_LSE 3
+
+#define STM32_RCC_CCIPR_SAI_PLLSAI1CLK 0
+#define STM32_RCC_CCIPR_SAI_PLLSAI2CLK 1
+#define STM32_RCC_CCIPR_SAI_PLLSAI3CLK 2
+#define STM32_RCC_CCIPR_SAI_EXTCLK 3
+
+#define STM32_RCC_CCIPR_CLK48_NONE 0
+#define STM32_RCC_CCIPR_CLK48_PLL48M2CLK 1
+#define STM32_RCC_CCIPR_CLK48_PLL48M1CLK 2
+#define STM32_RCC_CCIPR_CLK48_MSI 3
+
+#define STM32_RCC_CCIPR_ADC_NONE 0
+#define STM32_RCC_CCIPR_ADC_PLLADC1CLK 1
+#define STM32_RCC_CCIPR_ADC_PLLADC2CLK 2
+#define STM32_RCC_CCIPR_ADC_SYSCLK 3
+
+#define STM32_RCC_CCIPR_SWPMI_PCLK 0
+#define STM32_RCC_CCIPR_SWPMI_HSI16 1
+
+#define STM32_RCC_CCIPR_DFSDM_PCLK 0
+#define STM32_RCC_CCIPR_DFSDM_SYSCLK 1
+
+#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00)
+#define STM32_RCC_ICSCR REG32(STM32_RCC_BASE + 0x04)
+#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08)
+#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x0C)
+#define STM32_RCC_PLLSAI1CFGR REG32(STM32_RCC_BASE + 0x10)
+#define STM32_RCC_RESERVED REG32(STM32_RCC_BASE + 0x14)
+#define STM32_RCC_CIER REG32(STM32_RCC_BASE + 0x18)
+#define STM32_RCC_CIFR REG32(STM32_RCC_BASE + 0x1C)
+#define STM32_RCC_CICR REG32(STM32_RCC_BASE + 0x20)
+#define STM32_RCC_RESERVED0 REG32(STM32_RCC_BASE + 0x24)
+#define STM32_RCC_AHB1RSTR REG32(STM32_RCC_BASE + 0x28)
+#define STM32_RCC_AHB2RSTR REG32(STM32_RCC_BASE + 0x2C)
+#define STM32_RCC_AHB3RSTR REG32(STM32_RCC_BASE + 0x30)
+#define STM32_RCC_RESERVED1 REG32(STM32_RCC_BASE + 0x34)
+#define STM32_RCC_APB1RSTR1 REG32(STM32_RCC_BASE + 0x38)
+#define STM32_RCC_APB1RSTR2 REG32(STM32_RCC_BASE + 0x3C)
+#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x40)
+#define STM32_RCC_RESERVED2 REG32(STM32_RCC_BASE + 0x44)
+#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x48)
+#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x4C)
+#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x50)
+#define STM32_RCC_RESERVED3 REG32(STM32_RCC_BASE + 0x54)
+#define STM32_RCC_APB1ENR1 REG32(STM32_RCC_BASE + 0x58)
+#define STM32_RCC_APB1ENR2 REG32(STM32_RCC_BASE + 0x5C)
+#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x60)
+#define STM32_RCC_RESERVED4 REG32(STM32_RCC_BASE + 0x64)
+#define STM32_RCC_AHB1SMENR REG32(STM32_RCC_BASE + 0x68)
+#define STM32_RCC_AHB2SMENR REG32(STM32_RCC_BASE + 0x6C)
+#define STM32_RCC_AHB3SMENR REG32(STM32_RCC_BASE + 0x70)
+#define STM32_RCC_RESERVED5 REG32(STM32_RCC_BASE + 0x74)
+#define STM32_RCC_APB1SMENR1 REG32(STM32_RCC_BASE + 0x78)
+#define STM32_RCC_APB1SMENR2 REG32(STM32_RCC_BASE + 0x7C)
+#define STM32_RCC_APB2SMENR REG32(STM32_RCC_BASE + 0x80)
+#define STM32_RCC_RESERVED6 REG32(STM32_RCC_BASE + 0x84)
+#define STM32_RCC_CCIPR REG32(STM32_RCC_BASE + 0x88)
+#define STM32_RCC_RESERVED7 REG32(STM32_RCC_BASE + 0x8C)
+#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x90)
+#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x94)
+#define STM32_RCC_CRRCR REG32(STM32_RCC_BASE + 0x98)
+#define STM32_RCC_CCIPR2 REG32(STM32_RCC_BASE + 0x9C)
+
+#define STM32_RCC_PLLSAI1_SUPPORT
+#define STM32_RCC_PLLP_SUPPORT
+#define STM32_RCC_HSI48_SUPPORT
+#define STM32_RCC_PLLP_DIV_2_31_SUPPORT
+#define STM32_RCC_PLLSAI1P_DIV_2_31_SUPPORT
+
+#define STM32_RCC_APB1ENR STM32_RCC_APB1ENR1
+
+/********************  BIT DEFINITION FOR STM32_RCC_CR REGISTER  **************/
+#define STM32_RCC_CR_MSION_POS 0U
+#define STM32_RCC_CR_MSION_MSK (0x1UL << STM32_RCC_CR_MSION_POS)
+#define STM32_RCC_CR_MSION STM32_RCC_CR_MSION_MSK
+#define STM32_RCC_CR_MSIRDY_POS 1U
+#define STM32_RCC_CR_MSIRDY_MSK (0x1UL << STM32_RCC_CR_MSIRDY_POS)
+#define STM32_RCC_CR_MSIRDY STM32_RCC_CR_MSIRDY_MSK
+#define STM32_RCC_CR_MSIPLLEN_POS 2U
+#define STM32_RCC_CR_MSIPLLEN_MSK (0x1UL << STM32_RCC_CR_MSIPLLEN_POS)
+#define STM32_RCC_CR_MSIPLLEN STM32_RCC_CR_MSIPLLEN_MSK
+#define STM32_RCC_CR_MSIRGSEL_POS 3U
+#define STM32_RCC_CR_MSIRGSEL_MSK (0x1UL << STM32_RCC_CR_MSIRGSEL_POS)
+#define STM32_RCC_CR_MSIRGSEL STM32_RCC_CR_MSIRGSEL_MSK
+
+/*!< MSIRANGE CONFIGURATION : 12 FREQUENCY RANGES AVAILABLE */
+#define STM32_RCC_CR_MSIRANGE_POS 4U
+#define STM32_RCC_CR_MSIRANGE_MSK (0xFUL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE STM32_RCC_CR_MSIRANGE_MSK
+#define STM32_RCC_CR_MSIRANGE_0 (0x0UL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_1 (0x1UL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_2 (0x2UL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_3 (0x3UL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_4 (0x4UL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_5 (0x5UL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_6 (0x6UL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_7 (0x7UL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_8 (0x8UL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_9 (0x9UL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_10 (0xAUL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_11 (0xBUL << STM32_RCC_CR_MSIRANGE_POS)
+
+#define STM32_RCC_CR_HSION_POS 8U
+#define STM32_RCC_CR_HSION_MSK (0x1UL << STM32_RCC_CR_HSION_POS)
+#define STM32_RCC_CR_HSION STM32_RCC_CR_HSION_MSK
+#define STM32_RCC_CR_HSIKERON_POS 9U
+#define STM32_RCC_CR_HSIKERON_MSK (0x1UL << STM32_RCC_CR_HSIKERON_POS)
+#define STM32_RCC_CR_HSIKERON STM32_RCC_CR_HSIKERON_MSK
+#define STM32_RCC_CR_HSIRDY_POS 10U
+#define STM32_RCC_CR_HSIRDY_MSK (0x1UL << STM32_RCC_CR_HSIRDY_POS)
+#define STM32_RCC_CR_HSIRDY STM32_RCC_CR_HSIRDY_MSK
+#define STM32_RCC_CR_HSIASFS_POS 11U
+#define STM32_RCC_CR_HSIASFS_MSK (0x1UL << STM32_RCC_CR_HSIASFS_POS)
+#define STM32_RCC_CR_HSIASFS STM32_RCC_CR_HSIASFS_MSK
+
+#define STM32_RCC_CR_HSEON_POS 16U
+#define STM32_RCC_CR_HSEON_MSK (0x1UL << STM32_RCC_CR_HSEON_POS)
+#define STM32_RCC_CR_HSEON STM32_RCC_CR_HSEON_MSK
+#define STM32_RCC_CR_HSERDY_POS 17U
+#define STM32_RCC_CR_HSERDY_MSK (0x1UL << STM32_RCC_CR_HSERDY_POS)
+#define STM32_RCC_CR_HSERDY STM32_RCC_CR_HSERDY_MSK
+#define STM32_RCC_CR_HSEBYP_POS 18U
+#define STM32_RCC_CR_HSEBYP_MSK (0x1UL << STM32_RCC_CR_HSEBYP_POS)
+#define STM32_RCC_CR_HSEBYP STM32_RCC_CR_HSEBYP_MSK
+#define STM32_RCC_CR_CSSON_POS 19U
+#define STM32_RCC_CR_CSSON_MSK (0x1UL << STM32_RCC_CR_CSSON_POS)
+#define STM32_RCC_CR_CSSON STM32_RCC_CR_CSSON_MSK
+
+#define STM32_RCC_CR_PLLON_POS 24U
+#define STM32_RCC_CR_PLLON_MSK (0x1UL << STM32_RCC_CR_PLLON_POS)
+#define STM32_RCC_CR_PLLON STM32_RCC_CR_PLLON_MSK
+#define STM32_RCC_CR_PLLRDY_POS 25U
+#define STM32_RCC_CR_PLLRDY_MSK (0x1UL << STM32_RCC_CR_PLLRDY_POS)
+#define STM32_RCC_CR_PLLRDY STM32_RCC_CR_PLLRDY_MSK
+#define STM32_RCC_CR_PLLSAI1ON_POS 26U
+#define STM32_RCC_CR_PLLSAI1ON_MSK (0x1UL << STM32_RCC_CR_PLLSAI1ON_POS)
+#define STM32_RCC_CR_PLLSAI1ON STM32_RCC_CR_PLLSAI1ON_MSK
+#define STM32_RCC_CR_PLLSAI1RDY_POS 27U
+#define STM32_RCC_CR_PLLSAI1RDY_MSK (0x1UL << STM32_RCC_CR_PLLSAI1RDY_POS)
+#define STM32_RCC_CR_PLLSAI1RDY STM32_RCC_CR_PLLSAI1RDY_MSK
+
+/********************  BIT DEFINITION FOR STM32_RCC_ICSCR REGISTER  ***********/
+/*!< MSICAL CONFIGURATION */
+#define STM32_RCC_ICSCR_MSICAL_POS 0U
+#define STM32_RCC_ICSCR_MSICAL_MSK (0xFFUL << STM32_RCC_ICSCR_MSICAL_POS)
+#define STM32_RCC_ICSCR_MSICAL STM32_RCC_ICSCR_MSICAL_MSK
+#define STM32_RCC_ICSCR_MSICAL_0 (0x01UL << STM32_RCC_ICSCR_MSICAL_POS)
+#define STM32_RCC_ICSCR_MSICAL_1 (0x02UL << STM32_RCC_ICSCR_MSICAL_POS)
+#define STM32_RCC_ICSCR_MSICAL_2 (0x04UL << STM32_RCC_ICSCR_MSICAL_POS)
+#define STM32_RCC_ICSCR_MSICAL_3 (0x08UL << STM32_RCC_ICSCR_MSICAL_POS)
+#define STM32_RCC_ICSCR_MSICAL_4 (0x10UL << STM32_RCC_ICSCR_MSICAL_POS)
+#define STM32_RCC_ICSCR_MSICAL_5 (0x20UL << STM32_RCC_ICSCR_MSICAL_POS)
+#define STM32_RCC_ICSCR_MSICAL_6 (0x40UL << STM32_RCC_ICSCR_MSICAL_POS)
+#define STM32_RCC_ICSCR_MSICAL_7 (0x80UL << STM32_RCC_ICSCR_MSICAL_POS)
+
+/*!< MSITRIM CONFIGURATION */
+#define STM32_RCC_ICSCR_MSITRIM_POS 8U
+#define STM32_RCC_ICSCR_MSITRIM_MSK (0xFFUL << STM32_RCC_ICSCR_MSITRIM_POS)
+#define STM32_RCC_ICSCR_MSITRIM STM32_RCC_ICSCR_MSITRIM_MSK
+#define STM32_RCC_ICSCR_MSITRIM_0 (0x01UL << STM32_RCC_ICSCR_MSITRIM_POS)
+#define STM32_RCC_ICSCR_MSITRIM_1 (0x02UL << STM32_RCC_ICSCR_MSITRIM_POS)
+#define STM32_RCC_ICSCR_MSITRIM_2 (0x04UL << STM32_RCC_ICSCR_MSITRIM_POS)
+#define STM32_RCC_ICSCR_MSITRIM_3 (0x08UL << STM32_RCC_ICSCR_MSITRIM_POS)
+#define STM32_RCC_ICSCR_MSITRIM_4 (0x10UL << STM32_RCC_ICSCR_MSITRIM_POS)
+#define STM32_RCC_ICSCR_MSITRIM_5 (0x20UL << STM32_RCC_ICSCR_MSITRIM_POS)
+#define STM32_RCC_ICSCR_MSITRIM_6 (0x40UL << STM32_RCC_ICSCR_MSITRIM_POS)
+#define STM32_RCC_ICSCR_MSITRIM_7 (0x80UL << STM32_RCC_ICSCR_MSITRIM_POS)
+
+/*!< HSICAL CONFIGURATION */
+#define STM32_RCC_ICSCR_HSICAL_POS 16U
+#define STM32_RCC_ICSCR_HSICAL_MSK (0xFFUL << STM32_RCC_ICSCR_HSICAL_POS)
+#define STM32_RCC_ICSCR_HSICAL STM32_RCC_ICSCR_HSICAL_MSK
+#define STM32_RCC_ICSCR_HSICAL_0 (0x01UL << STM32_RCC_ICSCR_HSICAL_POS)
+#define STM32_RCC_ICSCR_HSICAL_1 (0x02UL << STM32_RCC_ICSCR_HSICAL_POS)
+#define STM32_RCC_ICSCR_HSICAL_2 (0x04UL << STM32_RCC_ICSCR_HSICAL_POS)
+#define STM32_RCC_ICSCR_HSICAL_3 (0x08UL << STM32_RCC_ICSCR_HSICAL_POS)
+#define STM32_RCC_ICSCR_HSICAL_4 (0x10UL << STM32_RCC_ICSCR_HSICAL_POS)
+#define STM32_RCC_ICSCR_HSICAL_5 (0x20UL << STM32_RCC_ICSCR_HSICAL_POS)
+#define STM32_RCC_ICSCR_HSICAL_6 (0x40UL << STM32_RCC_ICSCR_HSICAL_POS)
+#define STM32_RCC_ICSCR_HSICAL_7 (0x80UL << STM32_RCC_ICSCR_HSICAL_POS)
+
+/*!< HSITRIM CONFIGURATION */
+#define STM32_RCC_ICSCR_HSITRIM_POS 24U
+#define STM32_RCC_ICSCR_HSITRIM_MSK (0x1FUL << STM32_RCC_ICSCR_HSITRIM_POS)
+#define STM32_RCC_ICSCR_HSITRIM STM32_RCC_ICSCR_HSITRIM_MSK
+#define STM32_RCC_ICSCR_HSITRIM_0 (0x01UL << STM32_RCC_ICSCR_HSITRIM_POS)
+#define STM32_RCC_ICSCR_HSITRIM_1 (0x02UL << STM32_RCC_ICSCR_HSITRIM_POS)
+#define STM32_RCC_ICSCR_HSITRIM_2 (0x04UL << STM32_RCC_ICSCR_HSITRIM_POS)
+#define STM32_RCC_ICSCR_HSITRIM_3 (0x08UL << STM32_RCC_ICSCR_HSITRIM_POS)
+#define STM32_RCC_ICSCR_HSITRIM_4 (0x10UL << STM32_RCC_ICSCR_HSITRIM_POS)
+
+/****************  BIT DEFINITION FOR STM32_RCC_CFGR REGISTER  **************/
+/*!< SW CONFIGURATION */
+#define STM32_RCC_CFGR_SW_POS 0U
+#define STM32_RCC_CFGR_SW_MSK (0x3UL << STM32_RCC_CFGR_SW_POS)
+#define STM32_RCC_CFGR_SW STM32_RCC_CFGR_SW_MSK
+#define STM32_RCC_CFGR_SW_0 (0x1UL << STM32_RCC_CFGR_SW_POS)
+#define STM32_RCC_CFGR_SW_1 (0x2UL << STM32_RCC_CFGR_SW_POS)
+
+#define STM32_RCC_CFGR_SW_MSI (0x00000000UL)
+#define STM32_RCC_CFGR_SW_HSI (0x00000001UL)
+#define STM32_RCC_CFGR_SW_HSE (0x00000002UL)
+#define STM32_RCC_CFGR_SW_PLL (0x00000003UL)
+
+/*!< SWS CONFIGURATION */
+#define STM32_RCC_CFGR_SWS_POS 2U
+#define STM32_RCC_CFGR_SWS_MSK (0x3UL << STM32_RCC_CFGR_SWS_POS)
+#define STM32_RCC_CFGR_SWS STM32_RCC_CFGR_SWS_MSK
+#define STM32_RCC_CFGR_SWS_0 (0x1UL << STM32_RCC_CFGR_SWS_POS)
+#define STM32_RCC_CFGR_SWS_1 (0x2UL << STM32_RCC_CFGR_SWS_POS)
+
+#define STM32_RCC_CFGR_SWS_MSI (0x00000000UL)
+#define STM32_RCC_CFGR_SWS_HSI (0x00000004UL)
+#define STM32_RCC_CFGR_SWS_HSE (0x00000008UL)
+#define STM32_RCC_CFGR_SWS_PLL (0x0000000CUL)
+
+/*!< HPRE CONFIGURATION */
+#define STM32_RCC_CFGR_HPRE_POS 4U
+#define STM32_RCC_CFGR_HPRE_MSK (0xFUL << STM32_RCC_CFGR_HPRE_POS)
+#define STM32_RCC_CFGR_HPRE STM32_RCC_CFGR_HPRE_MSK
+#define STM32_RCC_CFGR_HPRE_0 (0x1UL << STM32_RCC_CFGR_HPRE_POS)
+#define STM32_RCC_CFGR_HPRE_1 (0x2UL << STM32_RCC_CFGR_HPRE_POS)
+#define STM32_RCC_CFGR_HPRE_2 (0x4UL << STM32_RCC_CFGR_HPRE_POS)
+#define STM32_RCC_CFGR_HPRE_3 (0x8UL << STM32_RCC_CFGR_HPRE_POS)
+
+#define STM32_RCC_CFGR_HPRE_DIV1 (0x00000000UL)
+#define STM32_RCC_CFGR_HPRE_DIV2 (0x00000080UL)
+#define STM32_RCC_CFGR_HPRE_DIV4 (0x00000090UL)
+#define STM32_RCC_CFGR_HPRE_DIV8 (0x000000A0UL)
+#define STM32_RCC_CFGR_HPRE_DIV16 (0x000000B0UL)
+#define STM32_RCC_CFGR_HPRE_DIV64 (0x000000C0UL)
+#define STM32_RCC_CFGR_HPRE_DIV128 (0x000000D0UL)
+#define STM32_RCC_CFGR_HPRE_DIV256 (0x000000E0UL)
+#define STM32_RCC_CFGR_HPRE_DIV512 (0x000000F0UL)
+
+/*!< PPRE1 CONFIGURATION */
+#define STM32_RCC_CFGR_PPRE1_POS 8U
+#define STM32_RCC_CFGR_PPRE1_MSK (0x7UL << STM32_RCC_CFGR_PPRE1_POS)
+#define STM32_RCC_CFGR_PPRE1 STM32_RCC_CFGR_PPRE1_MSK
+#define STM32_RCC_CFGR_PPRE1_0 (0x1UL << STM32_RCC_CFGR_PPRE1_POS)
+#define STM32_RCC_CFGR_PPRE1_1 (0x2UL << STM32_RCC_CFGR_PPRE1_POS)
+#define STM32_RCC_CFGR_PPRE1_2 (0x4UL << STM32_RCC_CFGR_PPRE1_POS)
+
+#define STM32_RCC_CFGR_PPRE1_DIV1 (0x00000000UL)
+#define STM32_RCC_CFGR_PPRE1_DIV2 (0x00000400UL)
+#define STM32_RCC_CFGR_PPRE1_DIV4 (0x00000500UL)
+#define STM32_RCC_CFGR_PPRE1_DIV8 (0x00000600UL)
+#define STM32_RCC_CFGR_PPRE1_DIV16 (0x00000700UL)
+
+/*!< PPRE2 CONFIGURATION */
+#define STM32_RCC_CFGR_PPRE2_POS 11U
+#define STM32_RCC_CFGR_PPRE2_MSK (0x7UL << STM32_RCC_CFGR_PPRE2_POS)
+#define STM32_RCC_CFGR_PPRE2 STM32_RCC_CFGR_PPRE2_MSK
+#define STM32_RCC_CFGR_PPRE2_0 (0x1UL << STM32_RCC_CFGR_PPRE2_POS)
+#define STM32_RCC_CFGR_PPRE2_1 (0x2UL << STM32_RCC_CFGR_PPRE2_POS)
+#define STM32_RCC_CFGR_PPRE2_2 (0x4UL << STM32_RCC_CFGR_PPRE2_POS)
+
+#define STM32_RCC_CFGR_PPRE2_DIV1 (0x00000000UL)
+#define STM32_RCC_CFGR_PPRE2_DIV2 (0x00002000UL)
+#define STM32_RCC_CFGR_PPRE2_DIV4 (0x00002800UL)
+#define STM32_RCC_CFGR_PPRE2_DIV8 (0x00003000UL)
+#define STM32_RCC_CFGR_PPRE2_DIV16 (0x00003800UL)
+
+#define STM32_RCC_CFGR_STOPWUCK_POS 15U
+#define STM32_RCC_CFGR_STOPWUCK_MSK (0x1UL << STM32_RCC_CFGR_STOPWUCK_POS)
+#define STM32_RCC_CFGR_STOPWUCK STM32_RCC_CFGR_STOPWUCK_MSK
+
+/*!< MCOSEL CONFIGURATION */
+#define STM32_RCC_CFGR_MCOSEL_POS 24U
+#define STM32_RCC_CFGR_MCOSEL_MSK (0xFUL << STM32_RCC_CFGR_MCOSEL_POS)
+#define STM32_RCC_CFGR_MCOSEL STM32_RCC_CFGR_MCOSEL_MSK
+#define STM32_RCC_CFGR_MCOSEL_0 (0x1UL << STM32_RCC_CFGR_MCOSEL_POS)
+#define STM32_RCC_CFGR_MCOSEL_1 (0x2UL << STM32_RCC_CFGR_MCOSEL_POS)
+#define STM32_RCC_CFGR_MCOSEL_2 (0x4UL << STM32_RCC_CFGR_MCOSEL_POS)
+#define STM32_RCC_CFGR_MCOSEL_3 (0x8UL << STM32_RCC_CFGR_MCOSEL_POS)
+
+#define STM32_RCC_CFGR_MCOPRE_POS 28U
+#define STM32_RCC_CFGR_MCOPRE_MSK (0x7UL << STM32_RCC_CFGR_MCOPRE_POS)
+#define STM32_RCC_CFGR_MCOPRE STM32_RCC_CFGR_MCOPRE_MSK
+#define STM32_RCC_CFGR_MCOPRE_0 (0x1UL << STM32_RCC_CFGR_MCOPRE_POS)
+#define STM32_RCC_CFGR_MCOPRE_1 (0x2UL << STM32_RCC_CFGR_MCOPRE_POS)
+#define STM32_RCC_CFGR_MCOPRE_2 (0x4UL << STM32_RCC_CFGR_MCOPRE_POS)
+
+#define STM32_RCC_CFGR_MCOPRE_DIV1 (0x00000000UL)
+#define STM32_RCC_CFGR_MCOPRE_DIV2 (0x10000000UL)
+#define STM32_RCC_CFGR_MCOPRE_DIV4 (0x20000000UL)
+#define STM32_RCC_CFGR_MCOPRE_DIV8 (0x30000000UL)
+#define STM32_RCC_CFGR_MCOPRE_DIV16 (0x40000000UL)
+
+/* LEGACY ALIASES */
+#define STM32_RCC_CFGR_MCO_PRE STM32_RCC_CFGR_MCOPRE
+#define STM32_RCC_CFGR_MCO_PRE_1 STM32_RCC_CFGR_MCOPRE_DIV1
+#define STM32_RCC_CFGR_MCO_PRE_2 STM32_RCC_CFGR_MCOPRE_DIV2
+#define STM32_RCC_CFGR_MCO_PRE_4 STM32_RCC_CFGR_MCOPRE_DIV4
+#define STM32_RCC_CFGR_MCO_PRE_8 STM32_RCC_CFGR_MCOPRE_DIV8
+#define STM32_RCC_CFGR_MCO_PRE_16 STM32_RCC_CFGR_MCOPRE_DIV16
+
+/****************  BIT DEFINITION FOR STM32_RCC_PLLCFGR REGISTER  ***********/
+#define STM32_RCC_PLLCFGR_PLLSRC_POS 0U
+#define STM32_RCC_PLLCFGR_PLLSRC_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLSRC_POS)
+#define STM32_RCC_PLLCFGR_PLLSRC STM32_RCC_PLLCFGR_PLLSRC_MSK
+
+#define STM32_RCC_PLLCFGR_PLLSRC_MSI_POS 0U
+#define STM32_RCC_PLLCFGR_PLLSRC_MSI_MSK \
+	(0x1UL << STM32_RCC_PLLCFGR_PLLSRC_MSI_POS)
+#define STM32_RCC_PLLCFGR_PLLSRC_MSI STM32_RCC_PLLCFGR_PLLSRC_MSI_MSK
+#define STM32_RCC_PLLCFGR_PLLSRC_HSI_POS 1U
+#define STM32_RCC_PLLCFGR_PLLSRC_HSI_MSK \
+	(0x1UL << STM32_RCC_PLLCFGR_PLLSRC_HSI_POS)
+#define STM32_RCC_PLLCFGR_PLLSRC_HSI STM32_RCC_PLLCFGR_PLLSRC_HSI_MSK
+#define STM32_RCC_PLLCFGR_PLLSRC_HSE_POS 0U
+#define STM32_RCC_PLLCFGR_PLLSRC_HSE_MSK \
+	(0x3UL << STM32_RCC_PLLCFGR_PLLSRC_HSE_POS)
+#define STM32_RCC_PLLCFGR_PLLSRC_HSE STM32_RCC_PLLCFGR_PLLSRC_HSE_MSK
+
+#define STM32_RCC_PLLCFGR_PLLM_POS 4U
+#define STM32_RCC_PLLCFGR_PLLM_MSK (0x7UL << STM32_RCC_PLLCFGR_PLLM_POS)
+#define STM32_RCC_PLLCFGR_PLLM STM32_RCC_PLLCFGR_PLLM_MSK
+#define STM32_RCC_PLLCFGR_PLLM_0 (0x1UL << STM32_RCC_PLLCFGR_PLLM_POS)
+#define STM32_RCC_PLLCFGR_PLLM_1 (0x2UL << STM32_RCC_PLLCFGR_PLLM_POS)
+#define STM32_RCC_PLLCFGR_PLLM_2 (0x4UL << STM32_RCC_PLLCFGR_PLLM_POS)
+
+#define STM32_RCC_PLLCFGR_PLLN_POS 8U
+#define STM32_RCC_PLLCFGR_PLLN_MSK (0x7FUL << STM32_RCC_PLLCFGR_PLLN_POS)
+#define STM32_RCC_PLLCFGR_PLLN STM32_RCC_PLLCFGR_PLLN_MSK
+#define STM32_RCC_PLLCFGR_PLLN_0 (0x01UL << STM32_RCC_PLLCFGR_PLLN_POS)
+#define STM32_RCC_PLLCFGR_PLLN_1 (0x02UL << STM32_RCC_PLLCFGR_PLLN_POS)
+#define STM32_RCC_PLLCFGR_PLLN_2 (0x04UL << STM32_RCC_PLLCFGR_PLLN_POS)
+#define STM32_RCC_PLLCFGR_PLLN_3 (0x08UL << STM32_RCC_PLLCFGR_PLLN_POS)
+#define STM32_RCC_PLLCFGR_PLLN_4 (0x10UL << STM32_RCC_PLLCFGR_PLLN_POS)
+#define STM32_RCC_PLLCFGR_PLLN_5 (0x20UL << STM32_RCC_PLLCFGR_PLLN_POS)
+#define STM32_RCC_PLLCFGR_PLLN_6 (0x40UL << STM32_RCC_PLLCFGR_PLLN_POS)
+
+#define STM32_RCC_PLLCFGR_PLLPEN_POS 16U
+#define STM32_RCC_PLLCFGR_PLLPEN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLPEN_POS)
+#define STM32_RCC_PLLCFGR_PLLPEN STM32_RCC_PLLCFGR_PLLPEN_MSK
+#define STM32_RCC_PLLCFGR_PLLP_POS 17U
+#define STM32_RCC_PLLCFGR_PLLP_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLP_POS)
+#define STM32_RCC_PLLCFGR_PLLP STM32_RCC_PLLCFGR_PLLP_MSK
+#define STM32_RCC_PLLCFGR_PLLQEN_POS 20U
+#define STM32_RCC_PLLCFGR_PLLQEN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLQEN_POS)
+#define STM32_RCC_PLLCFGR_PLLQEN STM32_RCC_PLLCFGR_PLLQEN_MSK
+
+#define STM32_RCC_PLLCFGR_PLLQ_POS 21U
+#define STM32_RCC_PLLCFGR_PLLQ_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLQ_POS)
+#define STM32_RCC_PLLCFGR_PLLQ STM32_RCC_PLLCFGR_PLLQ_MSK
+#define STM32_RCC_PLLCFGR_PLLQ_0 (0x1UL << STM32_RCC_PLLCFGR_PLLQ_POS)
+#define STM32_RCC_PLLCFGR_PLLQ_1 (0x2UL << STM32_RCC_PLLCFGR_PLLQ_POS)
+
+#define STM32_RCC_PLLCFGR_PLLREN_POS 24U
+#define STM32_RCC_PLLCFGR_PLLREN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLREN_POS)
+#define STM32_RCC_PLLCFGR_PLLREN STM32_RCC_PLLCFGR_PLLREN_MSK
+#define STM32_RCC_PLLCFGR_PLLR_POS 25U
+#define STM32_RCC_PLLCFGR_PLLR_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLR_POS)
+#define STM32_RCC_PLLCFGR_PLLR STM32_RCC_PLLCFGR_PLLR_MSK
+#define STM32_RCC_PLLCFGR_PLLR_0 (0x1UL << STM32_RCC_PLLCFGR_PLLR_POS)
+#define STM32_RCC_PLLCFGR_PLLR_1 (0x2UL << STM32_RCC_PLLCFGR_PLLR_POS)
+
+#define STM32_RCC_PLLCFGR_PLLPDIV_POS 27U
+#define STM32_RCC_PLLCFGR_PLLPDIV_MSK (0x1FUL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
+#define STM32_RCC_PLLCFGR_PLLPDIV STM32_RCC_PLLCFGR_PLLPDIV_MSK
+#define STM32_RCC_PLLCFGR_PLLPDIV_0 (0x01UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
+#define STM32_RCC_PLLCFGR_PLLPDIV_1 (0x02UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
+#define STM32_RCC_PLLCFGR_PLLPDIV_2 (0x04UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
+#define STM32_RCC_PLLCFGR_PLLPDIV_3 (0x08UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
+#define STM32_RCC_PLLCFGR_PLLPDIV_4 (0x10UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
+
+/****************  BIT DEFINITION FOR STM32_RCC_PLLSAI1CFGR REGISTER  ********/
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS 8U
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_MSK \
+	(0x7FUL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N STM32_RCC_PLLSAI1CFGR_PLLSAI1N_MSK
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_0 \
+	(0x01UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_1 \
+	(0x02UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_2 \
+	(0x04UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_3 \
+	(0x08UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_4 \
+	(0x10UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_5 \
+	(0x20UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_6 \
+	(0x40UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
+
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_POS 16U
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_MSK \
+	(0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_POS)
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_MSK
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1P_POS 17U
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1P_MSK \
+	(0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1P_POS)
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1P STM32_RCC_PLLSAI1CFGR_PLLSAI1P_MSK
+
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN_POS 20U
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN_MSK \
+	(0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN_POS)
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN_MSK
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_POS 21U
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_MSK \
+	(0x3UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_POS)
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_MSK
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_0 \
+	(0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_POS)
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_1 \
+	(0x2UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_POS)
+
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1REN_POS 24U
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1REN_MSK \
+	(0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1REN_POS)
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1REN STM32_RCC_PLLSAI1CFGR_PLLSAI1REN_MSK
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R_POS 25U
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R_MSK \
+	(0x3UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1R_POS)
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R STM32_RCC_PLLSAI1CFGR_PLLSAI1R_MSK
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R_0 \
+	(0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1R_POS)
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R_1 \
+	(0x2UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1R_POS)
+
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS 27U
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_MSK \
+	(0x1FUL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS)
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_MSK
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_0 \
+	(0x01UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS)
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_1 \
+	(0x02UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS)
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_2 \
+	(0x04UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS)
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_3 \
+	(0x08UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS)
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_4 \
+	(0x10UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS)
+
+/**************  BIT DEFINITION FOR STM32_RCC_CIER REGISTER  ******************/
+#define STM32_RCC_CIER_LSIRDYIE_POS 0U
+#define STM32_RCC_CIER_LSIRDYIE_MSK (0x1UL << STM32_RCC_CIER_LSIRDYIE_POS)
+#define STM32_RCC_CIER_LSIRDYIE STM32_RCC_CIER_LSIRDYIE_MSK
+#define STM32_RCC_CIER_LSERDYIE_POS 1U
+#define STM32_RCC_CIER_LSERDYIE_MSK (0x1UL << STM32_RCC_CIER_LSERDYIE_POS)
+#define STM32_RCC_CIER_LSERDYIE STM32_RCC_CIER_LSERDYIE_MSK
+#define STM32_RCC_CIER_MSIRDYIE_POS 2U
+#define STM32_RCC_CIER_MSIRDYIE_MSK (0x1UL << STM32_RCC_CIER_MSIRDYIE_POS)
+#define STM32_RCC_CIER_MSIRDYIE STM32_RCC_CIER_MSIRDYIE_MSK
+#define STM32_RCC_CIER_HSIRDYIE_POS 3U
+#define STM32_RCC_CIER_HSIRDYIE_MSK (0x1UL << STM32_RCC_CIER_HSIRDYIE_POS)
+#define STM32_RCC_CIER_HSIRDYIE STM32_RCC_CIER_HSIRDYIE_MSK
+#define STM32_RCC_CIER_HSERDYIE_POS 4U
+#define STM32_RCC_CIER_HSERDYIE_MSK (0x1UL << STM32_RCC_CIER_HSERDYIE_POS)
+#define STM32_RCC_CIER_HSERDYIE STM32_RCC_CIER_HSERDYIE_MSK
+#define STM32_RCC_CIER_PLLRDYIE_POS 5U
+#define STM32_RCC_CIER_PLLRDYIE_MSK (0x1UL << STM32_RCC_CIER_PLLRDYIE_POS)
+#define STM32_RCC_CIER_PLLRDYIE STM32_RCC_CIER_PLLRDYIE_MSK
+#define STM32_RCC_CIER_PLLSAI1RDYIE_POS 6U
+#define STM32_RCC_CIER_PLLSAI1RDYIE_MSK \
+	(0x1UL << STM32_RCC_CIER_PLLSAI1RDYIE_POS)
+#define STM32_RCC_CIER_PLLSAI1RDYIE STM32_RCC_CIER_PLLSAI1RDYIE_MSK
+#define STM32_RCC_CIER_LSECSSIE_POS 9U
+#define STM32_RCC_CIER_LSECSSIE_MSK (0x1UL << STM32_RCC_CIER_LSECSSIE_POS)
+#define STM32_RCC_CIER_LSECSSIE STM32_RCC_CIER_LSECSSIE_MSK
+#define STM32_RCC_CIER_HSI48RDYIE_POS 10U
+#define STM32_RCC_CIER_HSI48RDYIE_MSK (0x1UL << STM32_RCC_CIER_HSI48RDYIE_POS)
+#define STM32_RCC_CIER_HSI48RDYIE STM32_RCC_CIER_HSI48RDYIE_MSK
+
+/**************  BIT DEFINITION FOR STM32_RCC_CIFR REGISTER  ******************/
+#define STM32_RCC_CIFR_LSIRDYF_POS 0U
+#define STM32_RCC_CIFR_LSIRDYF_MSK (0x1UL << STM32_RCC_CIFR_LSIRDYF_POS)
+#define STM32_RCC_CIFR_LSIRDYF STM32_RCC_CIFR_LSIRDYF_MSK
+#define STM32_RCC_CIFR_LSERDYF_POS 1U
+#define STM32_RCC_CIFR_LSERDYF_MSK (0x1UL << STM32_RCC_CIFR_LSERDYF_POS)
+#define STM32_RCC_CIFR_LSERDYF STM32_RCC_CIFR_LSERDYF_MSK
+#define STM32_RCC_CIFR_MSIRDYF_POS 2U
+#define STM32_RCC_CIFR_MSIRDYF_MSK (0x1UL << STM32_RCC_CIFR_MSIRDYF_POS)
+#define STM32_RCC_CIFR_MSIRDYF STM32_RCC_CIFR_MSIRDYF_MSK
+#define STM32_RCC_CIFR_HSIRDYF_POS 3U
+#define STM32_RCC_CIFR_HSIRDYF_MSK (0x1UL << STM32_RCC_CIFR_HSIRDYF_POS)
+#define STM32_RCC_CIFR_HSIRDYF STM32_RCC_CIFR_HSIRDYF_MSK
+#define STM32_RCC_CIFR_HSERDYF_POS 4U
+#define STM32_RCC_CIFR_HSERDYF_MSK (0x1UL << STM32_RCC_CIFR_HSERDYF_POS)
+#define STM32_RCC_CIFR_HSERDYF STM32_RCC_CIFR_HSERDYF_MSK
+#define STM32_RCC_CIFR_PLLRDYF_POS 5U
+#define STM32_RCC_CIFR_PLLRDYF_MSK (0x1UL << STM32_RCC_CIFR_PLLRDYF_POS)
+#define STM32_RCC_CIFR_PLLRDYF STM32_RCC_CIFR_PLLRDYF_MSK
+#define STM32_RCC_CIFR_PLLSAI1RDYF_POS 6U
+#define STM32_RCC_CIFR_PLLSAI1RDYF_MSK (0x1UL << STM32_RCC_CIFR_PLLSAI1RDYF_POS)
+#define STM32_RCC_CIFR_PLLSAI1RDYF STM32_RCC_CIFR_PLLSAI1RDYF_MSK
+#define STM32_RCC_CIFR_CSSF_POS 8U
+#define STM32_RCC_CIFR_CSSF_MSK (0x1UL << STM32_RCC_CIFR_CSSF_POS)
+#define STM32_RCC_CIFR_CSSF STM32_RCC_CIFR_CSSF_MSK
+#define STM32_RCC_CIFR_LSECSSF_POS 9U
+#define STM32_RCC_CIFR_LSECSSF_MSK (0x1UL << STM32_RCC_CIFR_LSECSSF_POS)
+#define STM32_RCC_CIFR_LSECSSF STM32_RCC_CIFR_LSECSSF_MSK
+#define STM32_RCC_CIFR_HSI48RDYF_POS 10U
+#define STM32_RCC_CIFR_HSI48RDYF_MSK (0x1UL << STM32_RCC_CIFR_HSI48RDYF_POS)
+#define STM32_RCC_CIFR_HSI48RDYF STM32_RCC_CIFR_HSI48RDYF_MSK
+
+/**************  BIT DEFINITION FOR STM32_RCC_CICR REGISTER  ******************/
+#define STM32_RCC_CICR_LSIRDYC_POS 0U
+#define STM32_RCC_CICR_LSIRDYC_MSK (0x1UL << STM32_RCC_CICR_LSIRDYC_POS)
+#define STM32_RCC_CICR_LSIRDYC STM32_RCC_CICR_LSIRDYC_MSK
+#define STM32_RCC_CICR_LSERDYC_POS 1U
+#define STM32_RCC_CICR_LSERDYC_MSK (0x1UL << STM32_RCC_CICR_LSERDYC_POS)
+#define STM32_RCC_CICR_LSERDYC STM32_RCC_CICR_LSERDYC_MSK
+#define STM32_RCC_CICR_MSIRDYC_POS 2U
+#define STM32_RCC_CICR_MSIRDYC_MSK (0x1UL << STM32_RCC_CICR_MSIRDYC_POS)
+#define STM32_RCC_CICR_MSIRDYC STM32_RCC_CICR_MSIRDYC_MSK
+#define STM32_RCC_CICR_HSIRDYC_POS 3U
+#define STM32_RCC_CICR_HSIRDYC_MSK (0x1UL << STM32_RCC_CICR_HSIRDYC_POS)
+#define STM32_RCC_CICR_HSIRDYC STM32_RCC_CICR_HSIRDYC_MSK
+#define STM32_RCC_CICR_HSERDYC_POS 4U
+#define STM32_RCC_CICR_HSERDYC_MSK (0x1UL << STM32_RCC_CICR_HSERDYC_POS)
+#define STM32_RCC_CICR_HSERDYC STM32_RCC_CICR_HSERDYC_MSK
+#define STM32_RCC_CICR_PLLRDYC_POS 5U
+#define STM32_RCC_CICR_PLLRDYC_MSK (0x1UL << STM32_RCC_CICR_PLLRDYC_POS)
+#define STM32_RCC_CICR_PLLRDYC STM32_RCC_CICR_PLLRDYC_MSK
+#define STM32_RCC_CICR_PLLSAI1RDYC_POS 6U
+#define STM32_RCC_CICR_PLLSAI1RDYC_MSK (0x1UL << STM32_RCC_CICR_PLLSAI1RDYC_POS)
+#define STM32_RCC_CICR_PLLSAI1RDYC STM32_RCC_CICR_PLLSAI1RDYC_MSK
+#define STM32_RCC_CICR_CSSC_POS 8U
+#define STM32_RCC_CICR_CSSC_MSK (0x1UL << STM32_RCC_CICR_CSSC_POS)
+#define STM32_RCC_CICR_CSSC STM32_RCC_CICR_CSSC_MSK
+#define STM32_RCC_CICR_LSECSSC_POS 9U
+#define STM32_RCC_CICR_LSECSSC_MSK (0x1UL << STM32_RCC_CICR_LSECSSC_POS)
+#define STM32_RCC_CICR_LSECSSC STM32_RCC_CICR_LSECSSC_MSK
+#define STM32_RCC_CICR_HSI48RDYC_POS 10U
+#define STM32_RCC_CICR_HSI48RDYC_MSK (0x1UL << STM32_RCC_CICR_HSI48RDYC_POS)
+#define STM32_RCC_CICR_HSI48RDYC STM32_RCC_CICR_HSI48RDYC_MSK
+
+/**************  BIT DEFINITION FOR STM32_RCC_AHB1RSTR REGISTER  **************/
+#define STM32_RCC_AHB1RSTR_DMA1RST_POS 0U
+#define STM32_RCC_AHB1RSTR_DMA1RST_MSK (0x1UL << STM32_RCC_AHB1RSTR_DMA1RST_POS)
+#define STM32_RCC_AHB1RSTR_DMA1RST STM32_RCC_AHB1RSTR_DMA1RST_MSK
+#define STM32_RCC_AHB1RSTR_DMA2RST_POS 1U
+#define STM32_RCC_AHB1RSTR_DMA2RST_MSK (0x1UL << STM32_RCC_AHB1RSTR_DMA2RST_POS)
+#define STM32_RCC_AHB1RSTR_DMA2RST STM32_RCC_AHB1RSTR_DMA2RST_MSK
+#define STM32_RCC_AHB1RSTR_FLASHRST_POS 8U
+#define STM32_RCC_AHB1RSTR_FLASHRST_MSK \
+	(0x1UL << STM32_RCC_AHB1RSTR_FLASHRST_POS)
+#define STM32_RCC_AHB1RSTR_FLASHRST STM32_RCC_AHB1RSTR_FLASHRST_MSK
+#define STM32_RCC_AHB1RSTR_CRCRST_POS 12U
+#define STM32_RCC_AHB1RSTR_CRCRST_MSK (0x1UL << STM32_RCC_AHB1RSTR_CRCRST_POS)
+#define STM32_RCC_AHB1RSTR_CRCRST STM32_RCC_AHB1RSTR_CRCRST_MSK
+#define STM32_RCC_AHB1RSTR_TSCRST_POS 16U
+#define STM32_RCC_AHB1RSTR_TSCRST_MSK (0x1UL << STM32_RCC_AHB1RSTR_TSCRST_POS)
+#define STM32_RCC_AHB1RSTR_TSCRST STM32_RCC_AHB1RSTR_TSCRST_MSK
+
+/**************  BIT DEFINITION FOR STM32_RCC_AHB2RSTR REGISTER  **************/
+#define STM32_RCC_AHB2RSTR_GPIOARST_POS 0U
+#define STM32_RCC_AHB2RSTR_GPIOARST_MSK \
+	(0x1UL << STM32_RCC_AHB2RSTR_GPIOARST_POS)
+#define STM32_RCC_AHB2RSTR_GPIOARST STM32_RCC_AHB2RSTR_GPIOARST_MSK
+#define STM32_RCC_AHB2RSTR_GPIOBRST_POS 1U
+#define STM32_RCC_AHB2RSTR_GPIOBRST_MSK \
+	(0x1UL << STM32_RCC_AHB2RSTR_GPIOBRST_POS)
+#define STM32_RCC_AHB2RSTR_GPIOBRST STM32_RCC_AHB2RSTR_GPIOBRST_MSK
+#define STM32_RCC_AHB2RSTR_GPIOCRST_POS 2U
+#define STM32_RCC_AHB2RSTR_GPIOCRST_MSK \
+	(0x1UL << STM32_RCC_AHB2RSTR_GPIOCRST_POS)
+#define STM32_RCC_AHB2RSTR_GPIOCRST STM32_RCC_AHB2RSTR_GPIOCRST_MSK
+#define STM32_RCC_AHB2RSTR_GPIODRST_POS 3U
+#define STM32_RCC_AHB2RSTR_GPIODRST_MSK \
+	(0x1UL << STM32_RCC_AHB2RSTR_GPIODRST_POS)
+#define STM32_RCC_AHB2RSTR_GPIODRST STM32_RCC_AHB2RSTR_GPIODRST_MSK
+#define STM32_RCC_AHB2RSTR_GPIOERST_POS 4U
+#define STM32_RCC_AHB2RSTR_GPIOERST_MSK \
+	(0x1UL << STM32_RCC_AHB2RSTR_GPIOERST_POS)
+#define STM32_RCC_AHB2RSTR_GPIOERST STM32_RCC_AHB2RSTR_GPIOERST_MSK
+#define STM32_RCC_AHB2RSTR_GPIOHRST_POS 7U
+#define STM32_RCC_AHB2RSTR_GPIOHRST_MSK \
+	(0x1UL << STM32_RCC_AHB2RSTR_GPIOHRST_POS)
+#define STM32_RCC_AHB2RSTR_GPIOHRST STM32_RCC_AHB2RSTR_GPIOHRST_MSK
+#define STM32_RCC_AHB2RSTR_ADCRST_POS 13U
+#define STM32_RCC_AHB2RSTR_ADCRST_MSK (0x1UL << STM32_RCC_AHB2RSTR_ADCRST_POS)
+#define STM32_RCC_AHB2RSTR_ADCRST STM32_RCC_AHB2RSTR_ADCRST_MSK
+#define STM32_RCC_AHB2RSTR_AESRST_POS 16U
+#define STM32_RCC_AHB2RSTR_AESRST_MSK (0x1UL << STM32_RCC_AHB2RSTR_AESRST_POS)
+#define STM32_RCC_AHB2RSTR_AESRST STM32_RCC_AHB2RSTR_AESRST_MSK
+#define STM32_RCC_AHB2RSTR_RNGRST_POS 18U
+#define STM32_RCC_AHB2RSTR_RNGRST_MSK (0x1UL << STM32_RCC_AHB2RSTR_RNGRST_POS)
+#define STM32_RCC_AHB2RSTR_RNGRST STM32_RCC_AHB2RSTR_RNGRST_MSK
+
+/*************  BIT DEFINITION FOR STM32_RCC_AHB3RSTR REGISTER  **************/
+#define STM32_RCC_AHB3RSTR_QSPIRST_POS 8U
+#define STM32_RCC_AHB3RSTR_QSPIRST_MSK (0x1UL << STM32_RCC_AHB3RSTR_QSPIRST_POS)
+#define STM32_RCC_AHB3RSTR_QSPIRST STM32_RCC_AHB3RSTR_QSPIRST_MSK
+
+/*************  BIT DEFINITION FOR STM32_RCC_APB1RSTR1 REGISTER  **************/
+#define STM32_RCC_APB1RSTR1_TIM2RST_POS 0U
+#define STM32_RCC_APB1RSTR1_TIM2RST_MSK \
+	(0x1UL << STM32_RCC_APB1RSTR1_TIM2RST_POS)
+#define STM32_RCC_APB1RSTR1_TIM2RST STM32_RCC_APB1RSTR1_TIM2RST_MSK
+#define STM32_RCC_APB1RSTR1_TIM6RST_POS 4U
+#define STM32_RCC_APB1RSTR1_TIM6RST_MSK \
+	(0x1UL << STM32_RCC_APB1RSTR1_TIM6RST_POS)
+#define STM32_RCC_APB1RSTR1_TIM6RST STM32_RCC_APB1RSTR1_TIM6RST_MSK
+#define STM32_RCC_APB1RSTR1_TIM7RST_POS 5U
+#define STM32_RCC_APB1RSTR1_TIM7RST_MSK \
+	(0x1UL << STM32_RCC_APB1RSTR1_TIM7RST_POS)
+#define STM32_RCC_APB1RSTR1_TIM7RST STM32_RCC_APB1RSTR1_TIM7RST_MSK
+#define STM32_RCC_APB1RSTR1_LCDRST_POS 9U
+#define STM32_RCC_APB1RSTR1_LCDRST_MSK (0x1UL << STM32_RCC_APB1RSTR1_LCDRST_POS)
+#define STM32_RCC_APB1RSTR1_LCDRST STM32_RCC_APB1RSTR1_LCDRST_MSK
+#define STM32_RCC_APB1RSTR1_SPI2RST_POS 14U
+#define STM32_RCC_APB1RSTR1_SPI2RST_MSK \
+	(0x1UL << STM32_RCC_APB1RSTR1_SPI2RST_POS)
+#define STM32_RCC_APB1RSTR1_SPI2RST STM32_RCC_APB1RSTR1_SPI2RST_MSK
+#define STM32_RCC_APB1RSTR1_SPI3RST_POS 15U
+#define STM32_RCC_APB1RSTR1_SPI3RST_MSK \
+	(0x1UL << STM32_RCC_APB1RSTR1_SPI3RST_POS)
+#define STM32_RCC_APB1RSTR1_SPI3RST STM32_RCC_APB1RSTR1_SPI3RST_MSK
+#define STM32_RCC_APB1RSTR1_USART2RST_POS 17U
+#define STM32_RCC_APB1RSTR1_USART2RST_MSK \
+	(0x1UL << STM32_RCC_APB1RSTR1_USART2RST_POS)
+#define STM32_RCC_APB1RSTR1_USART2RST STM32_RCC_APB1RSTR1_USART2RST_MSK
+#define STM32_RCC_APB1RSTR1_USART3RST_POS 18U
+#define STM32_RCC_APB1RSTR1_USART3RST_MSK \
+	(0x1UL << STM32_RCC_APB1RSTR1_USART3RST_POS)
+#define STM32_RCC_APB1RSTR1_USART3RST STM32_RCC_APB1RSTR1_USART3RST_MSK
+#define STM32_RCC_APB1RSTR1_I2C1RST_POS 21U
+#define STM32_RCC_APB1RSTR1_I2C1RST_MSK \
+	(0x1UL << STM32_RCC_APB1RSTR1_I2C1RST_POS)
+#define STM32_RCC_APB1RSTR1_I2C1RST STM32_RCC_APB1RSTR1_I2C1RST_MSK
+#define STM32_RCC_APB1RSTR1_I2C2RST_POS 22U
+#define STM32_RCC_APB1RSTR1_I2C2RST_MSK \
+	(0x1UL << STM32_RCC_APB1RSTR1_I2C2RST_POS)
+#define STM32_RCC_APB1RSTR1_I2C2RST STM32_RCC_APB1RSTR1_I2C2RST_MSK
+#define STM32_RCC_APB1RSTR1_I2C3RST_POS 23U
+#define STM32_RCC_APB1RSTR1_I2C3RST_MSK \
+	(0x1UL << STM32_RCC_APB1RSTR1_I2C3RST_POS)
+#define STM32_RCC_APB1RSTR1_I2C3RST STM32_RCC_APB1RSTR1_I2C3RST_MSK
+#define STM32_RCC_APB1RSTR1_CRSRST_POS 24U
+#define STM32_RCC_APB1RSTR1_CRSRST_MSK (0x1UL << STM32_RCC_APB1RSTR1_CRSRST_POS)
+#define STM32_RCC_APB1RSTR1_CRSRST STM32_RCC_APB1RSTR1_CRSRST_MSK
+#define STM32_RCC_APB1RSTR1_CAN1RST_POS 25U
+#define STM32_RCC_APB1RSTR1_CAN1RST_MSK \
+	(0x1UL << STM32_RCC_APB1RSTR1_CAN1RST_POS)
+#define STM32_RCC_APB1RSTR1_CAN1RST STM32_RCC_APB1RSTR1_CAN1RST_MSK
+#define STM32_RCC_APB1RSTR1_USBFSRST_POS 26U
+#define STM32_RCC_APB1RSTR1_USBFSRST_MSK \
+	(0x1UL << STM32_RCC_APB1RSTR1_USBFSRST_POS)
+#define STM32_RCC_APB1RSTR1_USBFSRST STM32_RCC_APB1RSTR1_USBFSRST_MSK
+#define STM32_RCC_APB1RSTR1_PWRRST_POS 28U
+#define STM32_RCC_APB1RSTR1_PWRRST_MSK (0x1UL << STM32_RCC_APB1RSTR1_PWRRST_POS)
+#define STM32_RCC_APB1RSTR1_PWRRST STM32_RCC_APB1RSTR1_PWRRST_MSK
+#define STM32_RCC_APB1RSTR1_DAC1RST_POS 29U
+#define STM32_RCC_APB1RSTR1_DAC1RST_MSK \
+	(0x1UL << STM32_RCC_APB1RSTR1_DAC1RST_POS)
+#define STM32_RCC_APB1RSTR1_DAC1RST STM32_RCC_APB1RSTR1_DAC1RST_MSK
+#define STM32_RCC_APB1RSTR1_OPAMPRST_POS 30U
+#define STM32_RCC_APB1RSTR1_OPAMPRST_MSK \
+	(0x1UL << STM32_RCC_APB1RSTR1_OPAMPRST_POS)
+#define STM32_RCC_APB1RSTR1_OPAMPRST STM32_RCC_APB1RSTR1_OPAMPRST_MSK
+#define STM32_RCC_APB1RSTR1_LPTIM1RST_POS 31U
+#define STM32_RCC_APB1RSTR1_LPTIM1RST_MSK \
+	(0x1UL << STM32_RCC_APB1RSTR1_LPTIM1RST_POS)
+#define STM32_RCC_APB1RSTR1_LPTIM1RST STM32_RCC_APB1RSTR1_LPTIM1RST_MSK
+
+/*************  BIT DEFINITION FOR STM32_RCC_APB1RSTR2 REGISTER  **************/
+#define STM32_RCC_APB1RSTR2_LPUART1RST_POS 0U
+#define STM32_RCC_APB1RSTR2_LPUART1RST_MSK \
+	(0x1UL << STM32_RCC_APB1RSTR2_LPUART1RST_POS)
+#define STM32_RCC_APB1RSTR2_LPUART1RST STM32_RCC_APB1RSTR2_LPUART1RST_MSK
+#define STM32_RCC_APB1RSTR2_SWPMI1RST_POS 2U
+#define STM32_RCC_APB1RSTR2_SWPMI1RST_MSK \
+	(0x1UL << STM32_RCC_APB1RSTR2_SWPMI1RST_POS)
+#define STM32_RCC_APB1RSTR2_SWPMI1RST STM32_RCC_APB1RSTR2_SWPMI1RST_MSK
+#define STM32_RCC_APB1RSTR2_LPTIM2RST_POS 5U
+#define STM32_RCC_APB1RSTR2_LPTIM2RST_MSK \
+	(0x1UL << STM32_RCC_APB1RSTR2_LPTIM2RST_POS)
+#define STM32_RCC_APB1RSTR2_LPTIM2RST STM32_RCC_APB1RSTR2_LPTIM2RST_MSK
+
+/**************  BIT DEFINITION FOR STM32_RCC_APB2RSTR REGISTER  **************/
+#define STM32_RCC_APB2RSTR_SYSCFGRST_POS 0U
+#define STM32_RCC_APB2RSTR_SYSCFGRST_MSK \
+	(0x1UL << STM32_RCC_APB2RSTR_SYSCFGRST_POS)
+#define STM32_RCC_APB2RSTR_SYSCFGRST STM32_RCC_APB2RSTR_SYSCFGRST_MSK
+#define STM32_RCC_APB2RSTR_SDMMC1RST_POS 10U
+#define STM32_RCC_APB2RSTR_SDMMC1RST_MSK \
+	(0x1UL << STM32_RCC_APB2RSTR_SDMMC1RST_POS)
+#define STM32_RCC_APB2RSTR_SDMMC1RST STM32_RCC_APB2RSTR_SDMMC1RST_MSK
+#define STM32_RCC_APB2RSTR_TIM1RST_POS 11U
+#define STM32_RCC_APB2RSTR_TIM1RST_MSK (0x1UL << STM32_RCC_APB2RSTR_TIM1RST_POS)
+#define STM32_RCC_APB2RSTR_TIM1RST STM32_RCC_APB2RSTR_TIM1RST_MSK
+#define STM32_RCC_APB2RSTR_SPI1RST_POS 12U
+#define STM32_RCC_APB2RSTR_SPI1RST_MSK (0x1UL << STM32_RCC_APB2RSTR_SPI1RST_POS)
+#define STM32_RCC_APB2RSTR_SPI1RST STM32_RCC_APB2RSTR_SPI1RST_MSK
+#define STM32_RCC_APB2RSTR_USART1RST_POS 14U
+#define STM32_RCC_APB2RSTR_USART1RST_MSK \
+	(0x1UL << STM32_RCC_APB2RSTR_USART1RST_POS)
+#define STM32_RCC_APB2RSTR_USART1RST STM32_RCC_APB2RSTR_USART1RST_MSK
+#define STM32_RCC_APB2RSTR_TIM15RST_POS 16U
+#define STM32_RCC_APB2RSTR_TIM15RST_MSK \
+	(0x1UL << STM32_RCC_APB2RSTR_TIM15RST_POS)
+#define STM32_RCC_APB2RSTR_TIM15RST STM32_RCC_APB2RSTR_TIM15RST_MSK
+#define STM32_RCC_APB2RSTR_TIM16RST_POS 17U
+#define STM32_RCC_APB2RSTR_TIM16RST_MSK \
+	(0x1UL << STM32_RCC_APB2RSTR_TIM16RST_POS)
+#define STM32_RCC_APB2RSTR_TIM16RST STM32_RCC_APB2RSTR_TIM16RST_MSK
+#define STM32_RCC_APB2RSTR_SAI1RST_POS 21U
+#define STM32_RCC_APB2RSTR_SAI1RST_MSK (0x1UL << STM32_RCC_APB2RSTR_SAI1RST_POS)
+#define STM32_RCC_APB2RSTR_SAI1RST STM32_RCC_APB2RSTR_SAI1RST_MSK
+
+/**************  BIT DEFINITION FOR STM32_RCC_AHB1ENR REGISTER  ***************/
+#define STM32_RCC_AHB1ENR_DMA1EN_POS 0U
+#define STM32_RCC_AHB1ENR_DMA1EN_MSK (0x1UL << STM32_RCC_AHB1ENR_DMA1EN_POS)
+#define STM32_RCC_AHB1ENR_DMA1EN STM32_RCC_AHB1ENR_DMA1EN_MSK
+#define STM32_RCC_AHB1ENR_DMA2EN_POS 1U
+#define STM32_RCC_AHB1ENR_DMA2EN_MSK (0x1UL << STM32_RCC_AHB1ENR_DMA2EN_POS)
+#define STM32_RCC_AHB1ENR_DMA2EN STM32_RCC_AHB1ENR_DMA2EN_MSK
+#define STM32_RCC_AHB1ENR_FLASHEN_POS 8U
+#define STM32_RCC_AHB1ENR_FLASHEN_MSK (0x1UL << STM32_RCC_AHB1ENR_FLASHEN_POS)
+#define STM32_RCC_AHB1ENR_FLASHEN STM32_RCC_AHB1ENR_FLASHEN_MSK
+#define STM32_RCC_AHB1ENR_CRCEN_POS 12U
+#define STM32_RCC_AHB1ENR_CRCEN_MSK (0x1UL << STM32_RCC_AHB1ENR_CRCEN_POS)
+#define STM32_RCC_AHB1ENR_CRCEN STM32_RCC_AHB1ENR_CRCEN_MSK
+#define STM32_RCC_AHB1ENR_TSCEN_POS 16U
+#define STM32_RCC_AHB1ENR_TSCEN_MSK (0x1UL << STM32_RCC_AHB1ENR_TSCEN_POS)
+#define STM32_RCC_AHB1ENR_TSCEN STM32_RCC_AHB1ENR_TSCEN_MSK
+
+/***************  BIT DEFINITION FOR STM32_RCC_AHB2ENR REGISTER  *********/
+#define STM32_RCC_AHB2ENR_GPIOAEN_POS 0U
+#define STM32_RCC_AHB2ENR_GPIOAEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOAEN_POS)
+#define STM32_RCC_AHB2ENR_GPIOAEN STM32_RCC_AHB2ENR_GPIOAEN_MSK
+#define STM32_RCC_AHB2ENR_GPIOBEN_POS 1U
+#define STM32_RCC_AHB2ENR_GPIOBEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOBEN_POS)
+#define STM32_RCC_AHB2ENR_GPIOBEN STM32_RCC_AHB2ENR_GPIOBEN_MSK
+#define STM32_RCC_AHB2ENR_GPIOCEN_POS 2U
+#define STM32_RCC_AHB2ENR_GPIOCEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOCEN_POS)
+#define STM32_RCC_AHB2ENR_GPIOCEN STM32_RCC_AHB2ENR_GPIOCEN_MSK
+#define STM32_RCC_AHB2ENR_GPIODEN_POS 3U
+#define STM32_RCC_AHB2ENR_GPIODEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIODEN_POS)
+#define STM32_RCC_AHB2ENR_GPIODEN STM32_RCC_AHB2ENR_GPIODEN_MSK
+#define STM32_RCC_AHB2ENR_GPIOEEN_POS 4U
+#define STM32_RCC_AHB2ENR_GPIOEEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOEEN_POS)
+#define STM32_RCC_AHB2ENR_GPIOEEN STM32_RCC_AHB2ENR_GPIOEEN_MSK
+#define STM32_RCC_AHB2ENR_GPIOHEN_POS 7U
+#define STM32_RCC_AHB2ENR_GPIOHEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOHEN_POS)
+#define STM32_RCC_AHB2ENR_GPIOHEN STM32_RCC_AHB2ENR_GPIOHEN_MSK
+#define STM32_RCC_AHB2ENR_ADCEN_POS 13U
+#define STM32_RCC_AHB2ENR_ADCEN_MSK (0x1UL << STM32_RCC_AHB2ENR_ADCEN_POS)
+#define STM32_RCC_AHB2ENR_ADCEN STM32_RCC_AHB2ENR_ADCEN_MSK
+#define STM32_RCC_AHB2ENR_AESEN_POS 16U
+#define STM32_RCC_AHB2ENR_AESEN_MSK (0x1UL << STM32_RCC_AHB2ENR_AESEN_POS)
+#define STM32_RCC_AHB2ENR_AESEN STM32_RCC_AHB2ENR_AESEN_MSK
+#define STM32_RCC_AHB2ENR_RNGEN_POS 18U
+#define STM32_RCC_AHB2ENR_RNGEN_MSK (0x1UL << STM32_RCC_AHB2ENR_RNGEN_POS)
+#define STM32_RCC_AHB2ENR_RNGEN STM32_RCC_AHB2ENR_RNGEN_MSK
+
+/**************  BIT DEFINITION FOR STM32_RCC_AHB3ENR REGISTER  ***************/
+#define STM32_RCC_AHB3ENR_QSPIEN_POS 8U
+#define STM32_RCC_AHB3ENR_QSPIEN_MSK (0x1UL << STM32_RCC_AHB3ENR_QSPIEN_POS)
+#define STM32_RCC_AHB3ENR_QSPIEN STM32_RCC_AHB3ENR_QSPIEN_MSK
+
+/**************  BIT DEFINITION FOR STM32_RCC_APB1ENR1 REGISTER  **************/
+#define STM32_RCC_APB1ENR1_TIM2EN_POS 0U
+#define STM32_RCC_APB1ENR1_TIM2EN_MSK (0x1UL << STM32_RCC_APB1ENR1_TIM2EN_POS)
+#define STM32_RCC_APB1ENR1_TIM2EN STM32_RCC_APB1ENR1_TIM2EN_MSK
+#define STM32_RCC_APB1ENR1_TIM6EN_POS 4U
+#define STM32_RCC_APB1ENR1_TIM6EN_MSK (0x1UL << STM32_RCC_APB1ENR1_TIM6EN_POS)
+#define STM32_RCC_APB1ENR1_TIM6EN STM32_RCC_APB1ENR1_TIM6EN_MSK
+#define STM32_RCC_APB1ENR1_TIM7EN_POS 5U
+#define STM32_RCC_APB1ENR1_TIM7EN_MSK (0x1UL << STM32_RCC_APB1ENR1_TIM7EN_POS)
+#define STM32_RCC_APB1ENR1_TIM7EN STM32_RCC_APB1ENR1_TIM7EN_MSK
+#define STM32_RCC_APB1ENR1_LCDEN_POS 9U
+#define STM32_RCC_APB1ENR1_LCDEN_MSK (0x1UL << STM32_RCC_APB1ENR1_LCDEN_POS)
+#define STM32_RCC_APB1ENR1_LCDEN STM32_RCC_APB1ENR1_LCDEN_MSK
+#define STM32_RCC_APB1ENR1_RTCAPBEN_POS 10U
+#define STM32_RCC_APB1ENR1_RTCAPBEN_MSK \
+	(0x1UL << STM32_RCC_APB1ENR1_RTCAPBEN_POS)
+#define STM32_RCC_APB1ENR1_RTCAPBEN STM32_RCC_APB1ENR1_RTCAPBEN_MSK
+#define STM32_RCC_APB1ENR1_WWDGEN_POS 11U
+#define STM32_RCC_APB1ENR1_WWDGEN_MSK (0x1UL << STM32_RCC_APB1ENR1_WWDGEN_POS)
+#define STM32_RCC_APB1ENR1_WWDGEN STM32_RCC_APB1ENR1_WWDGEN_MSK
+#define STM32_RCC_APB1ENR1_SPI2EN_POS 14U
+#define STM32_RCC_APB1ENR1_SPI2EN_MSK (0x1UL << STM32_RCC_APB1ENR1_SPI2EN_POS)
+#define STM32_RCC_APB1ENR1_SPI2EN STM32_RCC_APB1ENR1_SPI2EN_MSK
+#define STM32_RCC_APB1ENR1_SPI3EN_POS 15U
+#define STM32_RCC_APB1ENR1_SPI3EN_MSK (0x1UL << STM32_RCC_APB1ENR1_SPI3EN_POS)
+#define STM32_RCC_APB1ENR1_SPI3EN STM32_RCC_APB1ENR1_SPI3EN_MSK
+#define STM32_RCC_APB1ENR1_USART2EN_POS 17U
+#define STM32_RCC_APB1ENR1_USART2EN_MSK \
+	(0x1UL << STM32_RCC_APB1ENR1_USART2EN_POS)
+#define STM32_RCC_APB1ENR1_USART2EN STM32_RCC_APB1ENR1_USART2EN_MSK
+#define STM32_RCC_APB1ENR1_USART3EN_POS 18U
+#define STM32_RCC_APB1ENR1_USART3EN_MSK \
+	(0x1UL << STM32_RCC_APB1ENR1_USART3EN_POS)
+#define STM32_RCC_APB1ENR1_USART3EN STM32_RCC_APB1ENR1_USART3EN_MSK
+#define STM32_RCC_APB1ENR1_I2C1EN_POS 21U
+#define STM32_RCC_APB1ENR1_I2C1EN_MSK (0x1UL << STM32_RCC_APB1ENR1_I2C1EN_POS)
+#define STM32_RCC_APB1ENR1_I2C1EN STM32_RCC_APB1ENR1_I2C1EN_MSK
+#define STM32_RCC_APB1ENR1_I2C2EN_POS 22U
+#define STM32_RCC_APB1ENR1_I2C2EN_MSK (0x1UL << STM32_RCC_APB1ENR1_I2C2EN_POS)
+#define STM32_RCC_APB1ENR1_I2C2EN STM32_RCC_APB1ENR1_I2C2EN_MSK
+#define STM32_RCC_APB1ENR1_I2C3EN_POS 23U
+#define STM32_RCC_APB1ENR1_I2C3EN_MSK (0x1UL << STM32_RCC_APB1ENR1_I2C3EN_POS)
+#define STM32_RCC_APB1ENR1_I2C3EN STM32_RCC_APB1ENR1_I2C3EN_MSK
+#define STM32_RCC_APB1ENR1_CRSEN_POS 24U
+#define STM32_RCC_APB1ENR1_CRSEN_MSK (0x1UL << STM32_RCC_APB1ENR1_CRSEN_POS)
+#define STM32_RCC_APB1ENR1_CRSEN STM32_RCC_APB1ENR1_CRSEN_MSK
+#define STM32_RCC_APB1ENR1_CAN1EN_POS 25U
+#define STM32_RCC_APB1ENR1_CAN1EN_MSK (0x1UL << STM32_RCC_APB1ENR1_CAN1EN_POS)
+#define STM32_RCC_APB1ENR1_CAN1EN STM32_RCC_APB1ENR1_CAN1EN_MSK
+#define STM32_RCC_APB1ENR1_USBFSEN_POS 26U
+#define STM32_RCC_APB1ENR1_USBFSEN_MSK (0x1UL << STM32_RCC_APB1ENR1_USBFSEN_POS)
+#define STM32_RCC_APB1ENR1_USBFSEN STM32_RCC_APB1ENR1_USBFSEN_MSK
+#define STM32_RCC_APB1ENR1_PWREN_POS 28U
+#define STM32_RCC_APB1ENR1_PWREN_MSK (0x1UL << STM32_RCC_APB1ENR1_PWREN_POS)
+#define STM32_RCC_APB1ENR1_PWREN STM32_RCC_APB1ENR1_PWREN_MSK
+#define STM32_RCC_APB1ENR1_DAC1EN_POS 29U
+#define STM32_RCC_APB1ENR1_DAC1EN_MSK (0x1UL << STM32_RCC_APB1ENR1_DAC1EN_POS)
+#define STM32_RCC_APB1ENR1_DAC1EN STM32_RCC_APB1ENR1_DAC1EN_MSK
+#define STM32_RCC_APB1ENR1_OPAMPEN_POS 30U
+#define STM32_RCC_APB1ENR1_OPAMPEN_MSK (0x1UL << STM32_RCC_APB1ENR1_OPAMPEN_POS)
+#define STM32_RCC_APB1ENR1_OPAMPEN STM32_RCC_APB1ENR1_OPAMPEN_MSK
+#define STM32_RCC_APB1ENR1_LPTIM1EN_POS 31U
+#define STM32_RCC_APB1ENR1_LPTIM1EN_MSK \
+	(0x1UL << STM32_RCC_APB1ENR1_LPTIM1EN_POS)
+#define STM32_RCC_APB1ENR1_LPTIM1EN STM32_RCC_APB1ENR1_LPTIM1EN_MSK
+
+/************  BIT DEFINITION FOR STM32_RCC_APB1RSTR2 REGISTER  **************/
+#define STM32_RCC_APB1ENR2_LPUART1EN_POS 0U
+#define STM32_RCC_APB1ENR2_LPUART1EN_MSK \
+	(0x1UL << STM32_RCC_APB1ENR2_LPUART1EN_POS)
+#define STM32_RCC_APB1ENR2_LPUART1EN STM32_RCC_APB1ENR2_LPUART1EN_MSK
+#define STM32_RCC_APB1ENR2_I2C4EN_POS 1U
+#define STM32_RCC_APB1ENR2_I2C4EN_MSK (0x1UL << STM32_RCC_APB1ENR2_I2C4EN_POS)
+#define STM32_RCC_APB1ENR2_I2C4EN STM32_RCC_APB1ENR2_I2C4EN_MSK
+#define STM32_RCC_APB1ENR2_SWPMI1EN_POS 2U
+#define STM32_RCC_APB1ENR2_SWPMI1EN_MSK \
+	(0x1UL << STM32_RCC_APB1ENR2_SWPMI1EN_POS)
+#define STM32_RCC_APB1ENR2_SWPMI1EN STM32_RCC_APB1ENR2_SWPMI1EN_MSK
+#define STM32_RCC_APB1ENR2_LPTIM2EN_POS 5U
+#define STM32_RCC_APB1ENR2_LPTIM2EN_MSK \
+	(0x1UL << STM32_RCC_APB1ENR2_LPTIM2EN_POS)
+#define STM32_RCC_APB1ENR2_LPTIM2EN STM32_RCC_APB1ENR2_LPTIM2EN_MSK
+
+/**************  BIT DEFINITION FOR STM32_RCC_APB2ENR REGISTER  ***************/
+#define STM32_RCC_APB2ENR_SYSCFGEN_POS 0U
+#define STM32_RCC_APB2ENR_SYSCFGEN_MSK (0x1UL << STM32_RCC_APB2ENR_SYSCFGEN_POS)
+#define STM32_RCC_APB2ENR_SYSCFGEN STM32_RCC_APB2ENR_SYSCFGEN_MSK
+#define STM32_RCC_APB2ENR_FWEN_POS 7U
+#define STM32_RCC_APB2ENR_FWEN_MSK (0x1UL << STM32_RCC_APB2ENR_FWEN_POS)
+#define STM32_RCC_APB2ENR_FWEN STM32_RCC_APB2ENR_FWEN_MSK
+#define STM32_RCC_APB2ENR_SDMMC1EN_POS 10U
+#define STM32_RCC_APB2ENR_SDMMC1EN_MSK (0x1UL << STM32_RCC_APB2ENR_SDMMC1EN_POS)
+#define STM32_RCC_APB2ENR_SDMMC1EN STM32_RCC_APB2ENR_SDMMC1EN_MSK
+#define STM32_RCC_APB2ENR_TIM1EN_POS 11U
+#define STM32_RCC_APB2ENR_TIM1EN_MSK (0x1UL << STM32_RCC_APB2ENR_TIM1EN_POS)
+#define STM32_RCC_APB2ENR_TIM1EN STM32_RCC_APB2ENR_TIM1EN_MSK
+#define STM32_RCC_APB2ENR_SPI1EN_POS 12U
+#define STM32_RCC_APB2ENR_SPI1EN_MSK (0x1UL << STM32_RCC_APB2ENR_SPI1EN_POS)
+#define STM32_RCC_APB2ENR_SPI1EN STM32_RCC_APB2ENR_SPI1EN_MSK
+#define STM32_RCC_APB2ENR_USART1EN_POS 14U
+#define STM32_RCC_APB2ENR_USART1EN_MSK (0x1UL << STM32_RCC_APB2ENR_USART1EN_POS)
+#define STM32_RCC_APB2ENR_USART1EN STM32_RCC_APB2ENR_USART1EN_MSK
+#define STM32_RCC_APB2ENR_TIM15EN_POS 16U
+#define STM32_RCC_APB2ENR_TIM15EN_MSK (0x1UL << STM32_RCC_APB2ENR_TIM15EN_POS)
+#define STM32_RCC_APB2ENR_TIM15EN STM32_RCC_APB2ENR_TIM15EN_MSK
+#define STM32_RCC_APB2ENR_TIM16EN_POS 17U
+#define STM32_RCC_APB2ENR_TIM16EN_MSK (0x1UL << STM32_RCC_APB2ENR_TIM16EN_POS)
+#define STM32_RCC_APB2ENR_TIM16EN STM32_RCC_APB2ENR_TIM16EN_MSK
+#define STM32_RCC_APB2ENR_SAI1EN_POS 21U
+#define STM32_RCC_APB2ENR_SAI1EN_MSK (0x1UL << STM32_RCC_APB2ENR_SAI1EN_POS)
+#define STM32_RCC_APB2ENR_SAI1EN STM32_RCC_APB2ENR_SAI1EN_MSK
+
+/************  BIT DEFINITION FOR STM32_RCC_AHB1SMENR REGISTER  ***************/
+#define STM32_RCC_AHB1SMENR_DMA1SMEN_POS 0U
+#define STM32_RCC_AHB1SMENR_DMA1SMEN_MSK \
+	(0x1UL << STM32_RCC_AHB1SMENR_DMA1SMEN_POS)
+#define STM32_RCC_AHB1SMENR_DMA1SMEN STM32_RCC_AHB1SMENR_DMA1SMEN_MSK
+#define STM32_RCC_AHB1SMENR_DMA2SMEN_POS 1U
+#define STM32_RCC_AHB1SMENR_DMA2SMEN_MSK \
+	(0x1UL << STM32_RCC_AHB1SMENR_DMA2SMEN_POS)
+#define STM32_RCC_AHB1SMENR_DMA2SMEN STM32_RCC_AHB1SMENR_DMA2SMEN_MSK
+#define STM32_RCC_AHB1SMENR_FLASHSMEN_POS 8U
+#define STM32_RCC_AHB1SMENR_FLASHSMEN_MSK \
+	(0x1UL << STM32_RCC_AHB1SMENR_FLASHSMEN_POS)
+#define STM32_RCC_AHB1SMENR_FLASHSMEN STM32_RCC_AHB1SMENR_FLASHSMEN_MSK
+#define STM32_RCC_AHB1SMENR_SRAM1SMEN_POS 9U
+#define STM32_RCC_AHB1SMENR_SRAM1SMEN_MSK \
+	(0x1UL << STM32_RCC_AHB1SMENR_SRAM1SMEN_POS)
+#define STM32_RCC_AHB1SMENR_SRAM1SMEN STM32_RCC_AHB1SMENR_SRAM1SMEN_MSK
+#define STM32_RCC_AHB1SMENR_CRCSMEN_POS 12U
+#define STM32_RCC_AHB1SMENR_CRCSMEN_MSK \
+	(0x1UL << STM32_RCC_AHB1SMENR_CRCSMEN_POS)
+#define STM32_RCC_AHB1SMENR_CRCSMEN STM32_RCC_AHB1SMENR_CRCSMEN_MSK
+#define STM32_RCC_AHB1SMENR_TSCSMEN_POS 16U
+#define STM32_RCC_AHB1SMENR_TSCSMEN_MSK \
+	(0x1UL << STM32_RCC_AHB1SMENR_TSCSMEN_POS)
+#define STM32_RCC_AHB1SMENR_TSCSMEN STM32_RCC_AHB1SMENR_TSCSMEN_MSK
+
+/**************  BIT DEFINITION FOR STM32_RCC_AHB2SMENR REGISTER  *************/
+#define STM32_RCC_AHB2SMENR_GPIOASMEN_POS 0U
+#define STM32_RCC_AHB2SMENR_GPIOASMEN_MSK \
+	(0x1UL << STM32_RCC_AHB2SMENR_GPIOASMEN_POS)
+#define STM32_RCC_AHB2SMENR_GPIOASMEN STM32_RCC_AHB2SMENR_GPIOASMEN_MSK
+#define STM32_RCC_AHB2SMENR_GPIOBSMEN_POS 1U
+#define STM32_RCC_AHB2SMENR_GPIOBSMEN_MSK \
+	(0x1UL << STM32_RCC_AHB2SMENR_GPIOBSMEN_POS)
+#define STM32_RCC_AHB2SMENR_GPIOBSMEN STM32_RCC_AHB2SMENR_GPIOBSMEN_MSK
+#define STM32_RCC_AHB2SMENR_GPIOCSMEN_POS 2U
+#define STM32_RCC_AHB2SMENR_GPIOCSMEN_MSK \
+	(0x1UL << STM32_RCC_AHB2SMENR_GPIOCSMEN_POS)
+#define STM32_RCC_AHB2SMENR_GPIOCSMEN STM32_RCC_AHB2SMENR_GPIOCSMEN_MSK
+#define STM32_RCC_AHB2SMENR_GPIODSMEN_POS 3U
+#define STM32_RCC_AHB2SMENR_GPIODSMEN_MSK \
+	(0x1UL << STM32_RCC_AHB2SMENR_GPIODSMEN_POS)
+#define STM32_RCC_AHB2SMENR_GPIODSMEN STM32_RCC_AHB2SMENR_GPIODSMEN_MSK
+#define STM32_RCC_AHB2SMENR_GPIOESMEN_POS 4U
+#define STM32_RCC_AHB2SMENR_GPIOESMEN_MSK \
+	(0x1UL << STM32_RCC_AHB2SMENR_GPIOESMEN_POS)
+#define STM32_RCC_AHB2SMENR_GPIOESMEN STM32_RCC_AHB2SMENR_GPIOESMEN_MSK
+#define STM32_RCC_AHB2SMENR_GPIOHSMEN_POS 7U
+#define STM32_RCC_AHB2SMENR_GPIOHSMEN_MSK \
+	(0x1UL << STM32_RCC_AHB2SMENR_GPIOHSMEN_POS)
+#define STM32_RCC_AHB2SMENR_GPIOHSMEN STM32_RCC_AHB2SMENR_GPIOHSMEN_MSK
+#define STM32_RCC_AHB2SMENR_SRAM2SMEN_POS 9U
+#define STM32_RCC_AHB2SMENR_SRAM2SMEN_MSK \
+	(0x1UL << STM32_RCC_AHB2SMENR_SRAM2SMEN_POS)
+#define STM32_RCC_AHB2SMENR_SRAM2SMEN STM32_RCC_AHB2SMENR_SRAM2SMEN_MSK
+#define STM32_RCC_AHB2SMENR_ADCSMEN_POS 13U
+#define STM32_RCC_AHB2SMENR_ADCSMEN_MSK \
+	(0x1UL << STM32_RCC_AHB2SMENR_ADCSMEN_POS)
+#define STM32_RCC_AHB2SMENR_ADCSMEN STM32_RCC_AHB2SMENR_ADCSMEN_MSK
+#define STM32_RCC_AHB2SMENR_AESSMEN_POS 16U
+#define STM32_RCC_AHB2SMENR_AESSMEN_MSK \
+	(0x1UL << STM32_RCC_AHB2SMENR_AESSMEN_POS)
+#define STM32_RCC_AHB2SMENR_AESSMEN STM32_RCC_AHB2SMENR_AESSMEN_MSK
+#define STM32_RCC_AHB2SMENR_RNGSMEN_POS 18U
+#define STM32_RCC_AHB2SMENR_RNGSMEN_MSK \
+	(0x1UL << STM32_RCC_AHB2SMENR_RNGSMEN_POS)
+#define STM32_RCC_AHB2SMENR_RNGSMEN STM32_RCC_AHB2SMENR_RNGSMEN_MSK
+
+/**************  BIT DEFINITION FOR STM32_RCC_AHB3SMENR REGISTER  *************/
+#define STM32_RCC_AHB3SMENR_QSPISMEN_POS 8U
+#define STM32_RCC_AHB3SMENR_QSPISMEN_MSK \
+	(0x1UL << STM32_RCC_AHB3SMENR_QSPISMEN_POS)
+#define STM32_RCC_AHB3SMENR_QSPISMEN STM32_RCC_AHB3SMENR_QSPISMEN_MSK
+
+/*************  BIT DEFINITION FOR STM32_RCC_APB1SMENR1 REGISTER  *************/
+#define STM32_RCC_APB1SMENR1_TIM2SMEN_POS 0U
+#define STM32_RCC_APB1SMENR1_TIM2SMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR1_TIM2SMEN_POS)
+#define STM32_RCC_APB1SMENR1_TIM2SMEN STM32_RCC_APB1SMENR1_TIM2SMEN_MSK
+#define STM32_RCC_APB1SMENR1_TIM6SMEN_POS 4U
+#define STM32_RCC_APB1SMENR1_TIM6SMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR1_TIM6SMEN_POS)
+#define STM32_RCC_APB1SMENR1_TIM6SMEN STM32_RCC_APB1SMENR1_TIM6SMEN_MSK
+#define STM32_RCC_APB1SMENR1_TIM7SMEN_POS 5U
+#define STM32_RCC_APB1SMENR1_TIM7SMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR1_TIM7SMEN_POS)
+#define STM32_RCC_APB1SMENR1_TIM7SMEN STM32_RCC_APB1SMENR1_TIM7SMEN_MSK
+#define STM32_RCC_APB1SMENR1_LCDSMEN_POS 9U
+#define STM32_RCC_APB1SMENR1_LCDSMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR1_LCDSMEN_POS)
+#define STM32_RCC_APB1SMENR1_LCDSMEN STM32_RCC_APB1SMENR1_LCDSMEN_MSK
+#define STM32_RCC_APB1SMENR1_RTCAPBSMEN_POS 10U
+#define STM32_RCC_APB1SMENR1_RTCAPBSMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR1_RTCAPBSMEN_POS)
+#define STM32_RCC_APB1SMENR1_RTCAPBSMEN STM32_RCC_APB1SMENR1_RTCAPBSMEN_MSK
+#define STM32_RCC_APB1SMENR1_WWDGSMEN_POS 11U
+#define STM32_RCC_APB1SMENR1_WWDGSMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR1_WWDGSMEN_POS)
+#define STM32_RCC_APB1SMENR1_WWDGSMEN STM32_RCC_APB1SMENR1_WWDGSMEN_MSK
+#define STM32_RCC_APB1SMENR1_SPI2SMEN_POS 14U
+#define STM32_RCC_APB1SMENR1_SPI2SMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR1_SPI2SMEN_POS)
+#define STM32_RCC_APB1SMENR1_SPI2SMEN STM32_RCC_APB1SMENR1_SPI2SMEN_MSK
+#define STM32_RCC_APB1SMENR1_SPI3SMEN_POS 15U
+#define STM32_RCC_APB1SMENR1_SPI3SMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR1_SPI3SMEN_POS)
+#define STM32_RCC_APB1SMENR1_SPI3SMEN STM32_RCC_APB1SMENR1_SPI3SMEN_MSK
+#define STM32_RCC_APB1SMENR1_USART2SMEN_POS 17U
+#define STM32_RCC_APB1SMENR1_USART2SMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR1_USART2SMEN_POS)
+#define STM32_RCC_APB1SMENR1_USART2SMEN STM32_RCC_APB1SMENR1_USART2SMEN_MSK
+#define STM32_RCC_APB1SMENR1_USART3SMEN_POS 18U
+#define STM32_RCC_APB1SMENR1_USART3SMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR1_USART3SMEN_POS)
+#define STM32_RCC_APB1SMENR1_USART3SMEN STM32_RCC_APB1SMENR1_USART3SMEN_MSK
+#define STM32_RCC_APB1SMENR1_I2C1SMEN_POS 21U
+#define STM32_RCC_APB1SMENR1_I2C1SMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR1_I2C1SMEN_POS)
+#define STM32_RCC_APB1SMENR1_I2C1SMEN STM32_RCC_APB1SMENR1_I2C1SMEN_MSK
+#define STM32_RCC_APB1SMENR1_I2C2SMEN_POS 22U
+#define STM32_RCC_APB1SMENR1_I2C2SMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR1_I2C2SMEN_POS)
+#define STM32_RCC_APB1SMENR1_I2C2SMEN STM32_RCC_APB1SMENR1_I2C2SMEN_MSK
+#define STM32_RCC_APB1SMENR1_I2C3SMEN_POS 23U
+#define STM32_RCC_APB1SMENR1_I2C3SMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR1_I2C3SMEN_POS)
+#define STM32_RCC_APB1SMENR1_I2C3SMEN STM32_RCC_APB1SMENR1_I2C3SMEN_MSK
+#define STM32_RCC_APB1SMENR1_CRSSMEN_POS 24U
+#define STM32_RCC_APB1SMENR1_CRSSMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR1_CRSSMEN_POS)
+#define STM32_RCC_APB1SMENR1_CRSSMEN STM32_RCC_APB1SMENR1_CRSSMEN_MSK
+#define STM32_RCC_APB1SMENR1_CAN1SMEN_POS 25U
+#define STM32_RCC_APB1SMENR1_CAN1SMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR1_CAN1SMEN_POS)
+#define STM32_RCC_APB1SMENR1_CAN1SMEN STM32_RCC_APB1SMENR1_CAN1SMEN_MSK
+#define STM32_RCC_APB1SMENR1_USBFSSMEN_POS 26U
+#define STM32_RCC_APB1SMENR1_USBFSSMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR1_USBFSSMEN_POS)
+#define STM32_RCC_APB1SMENR1_USBFSSMEN STM32_RCC_APB1SMENR1_USBFSSMEN_MSK
+#define STM32_RCC_APB1SMENR1_PWRSMEN_POS 28U
+#define STM32_RCC_APB1SMENR1_PWRSMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR1_PWRSMEN_POS)
+#define STM32_RCC_APB1SMENR1_PWRSMEN STM32_RCC_APB1SMENR1_PWRSMEN_MSK
+#define STM32_RCC_APB1SMENR1_DAC1SMEN_POS 29U
+#define STM32_RCC_APB1SMENR1_DAC1SMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR1_DAC1SMEN_POS)
+#define STM32_RCC_APB1SMENR1_DAC1SMEN STM32_RCC_APB1SMENR1_DAC1SMEN_MSK
+#define STM32_RCC_APB1SMENR1_OPAMPSMEN_POS 30U
+#define STM32_RCC_APB1SMENR1_OPAMPSMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR1_OPAMPSMEN_POS)
+#define STM32_RCC_APB1SMENR1_OPAMPSMEN STM32_RCC_APB1SMENR1_OPAMPSMEN_MSK
+#define STM32_RCC_APB1SMENR1_LPTIM1SMEN_POS 31U
+#define STM32_RCC_APB1SMENR1_LPTIM1SMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR1_LPTIM1SMEN_POS)
+#define STM32_RCC_APB1SMENR1_LPTIM1SMEN STM32_RCC_APB1SMENR1_LPTIM1SMEN_MSK
+
+/*************  BIT DEFINITION FOR STM32_RCC_APB1SMENR2 REGISTER  *************/
+#define STM32_RCC_APB1SMENR2_LPUART1SMEN_POS 0U
+#define STM32_RCC_APB1SMENR2_LPUART1SMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR2_LPUART1SMEN_POS)
+#define STM32_RCC_APB1SMENR2_LPUART1SMEN STM32_RCC_APB1SMENR2_LPUART1SMEN_MSK
+#define STM32_RCC_APB1SMENR2_SWPMI1SMEN_POS 2U
+#define STM32_RCC_APB1SMENR2_SWPMI1SMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR2_SWPMI1SMEN_POS)
+#define STM32_RCC_APB1SMENR2_SWPMI1SMEN STM32_RCC_APB1SMENR2_SWPMI1SMEN_MSK
+#define STM32_RCC_APB1SMENR2_LPTIM2SMEN_POS 5U
+#define STM32_RCC_APB1SMENR2_LPTIM2SMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR2_LPTIM2SMEN_POS)
+#define STM32_RCC_APB1SMENR2_LPTIM2SMEN STM32_RCC_APB1SMENR2_LPTIM2SMEN_MSK
+
+/************  BIT DEFINITION FOR STM32_RCC_APB2SMENR REGISTER  *************/
+#define STM32_RCC_APB2SMENR_SYSCFGSMEN_POS 0U
+#define STM32_RCC_APB2SMENR_SYSCFGSMEN_MSK \
+	(0x1UL << STM32_RCC_APB2SMENR_SYSCFGSMEN_POS)
+#define STM32_RCC_APB2SMENR_SYSCFGSMEN STM32_RCC_APB2SMENR_SYSCFGSMEN_MSK
+#define STM32_RCC_APB2SMENR_SDMMC1SMEN_POS 10U
+#define STM32_RCC_APB2SMENR_SDMMC1SMEN_MSK \
+	(0x1UL << STM32_RCC_APB2SMENR_SDMMC1SMEN_POS)
+#define STM32_RCC_APB2SMENR_SDMMC1SMEN STM32_RCC_APB2SMENR_SDMMC1SMEN_MSK
+#define STM32_RCC_APB2SMENR_TIM1SMEN_POS 11U
+#define STM32_RCC_APB2SMENR_TIM1SMEN_MSK \
+	(0x1UL << STM32_RCC_APB2SMENR_TIM1SMEN_POS)
+#define STM32_RCC_APB2SMENR_TIM1SMEN STM32_RCC_APB2SMENR_TIM1SMEN_MSK
+#define STM32_RCC_APB2SMENR_SPI1SMEN_POS 12U
+#define STM32_RCC_APB2SMENR_SPI1SMEN_MSK \
+	(0x1UL << STM32_RCC_APB2SMENR_SPI1SMEN_POS)
+#define STM32_RCC_APB2SMENR_SPI1SMEN STM32_RCC_APB2SMENR_SPI1SMEN_MSK
+#define STM32_RCC_APB2SMENR_USART1SMEN_POS 14U
+#define STM32_RCC_APB2SMENR_USART1SMEN_MSK \
+	(0x1UL << STM32_RCC_APB2SMENR_USART1SMEN_POS)
+#define STM32_RCC_APB2SMENR_USART1SMEN STM32_RCC_APB2SMENR_USART1SMEN_MSK
+#define STM32_RCC_APB2SMENR_TIM15SMEN_POS 16U
+#define STM32_RCC_APB2SMENR_TIM15SMEN_MSK \
+	(0x1UL << STM32_RCC_APB2SMENR_TIM15SMEN_POS)
+#define STM32_RCC_APB2SMENR_TIM15SMEN STM32_RCC_APB2SMENR_TIM15SMEN_MSK
+#define STM32_RCC_APB2SMENR_TIM16SMEN_POS 17U
+#define STM32_RCC_APB2SMENR_TIM16SMEN_MSK \
+	(0x1UL << STM32_RCC_APB2SMENR_TIM16SMEN_POS)
+#define STM32_RCC_APB2SMENR_TIM16SMEN STM32_RCC_APB2SMENR_TIM16SMEN_MSK
+#define STM32_RCC_APB2SMENR_SAI1SMEN_POS 21U
+#define STM32_RCC_APB2SMENR_SAI1SMEN_MSK \
+	(0x1UL << STM32_RCC_APB2SMENR_SAI1SMEN_POS)
+#define STM32_RCC_APB2SMENR_SAI1SMEN STM32_RCC_APB2SMENR_SAI1SMEN_MSK
+
+/*************  BIT DEFINITION FOR STM32_RCC_CCIPR REGISTER  ******************/
+#define STM32_RCC_CCIPR_USART1SEL_POS 0U
+#define STM32_RCC_CCIPR_USART1SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART1SEL_POS)
+#define STM32_RCC_CCIPR_USART1SEL STM32_RCC_CCIPR_USART1SEL_MSK
+#define STM32_RCC_CCIPR_USART1SEL_0 (0x1UL << STM32_RCC_CCIPR_USART1SEL_POS)
+#define STM32_RCC_CCIPR_USART1SEL_1 (0x2UL << STM32_RCC_CCIPR_USART1SEL_POS)
+
+#define STM32_RCC_CCIPR_USART2SEL_POS 2U
+#define STM32_RCC_CCIPR_USART2SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART2SEL_POS)
+#define STM32_RCC_CCIPR_USART2SEL STM32_RCC_CCIPR_USART2SEL_MSK
+#define STM32_RCC_CCIPR_USART2SEL_0 (0x1UL << STM32_RCC_CCIPR_USART2SEL_POS)
+#define STM32_RCC_CCIPR_USART2SEL_1 (0x2UL << STM32_RCC_CCIPR_USART2SEL_POS)
+
+#define STM32_RCC_CCIPR_USART3SEL_POS 4U
+#define STM32_RCC_CCIPR_USART3SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART3SEL_POS)
+#define STM32_RCC_CCIPR_USART3SEL STM32_RCC_CCIPR_USART3SEL_MSK
+#define STM32_RCC_CCIPR_USART3SEL_0 (0x1UL << STM32_RCC_CCIPR_USART3SEL_POS)
+#define STM32_RCC_CCIPR_USART3SEL_1 (0x2UL << STM32_RCC_CCIPR_USART3SEL_POS)
+
+#define STM32_RCC_CCIPR_LPUART1SEL_POS 10U
+#define STM32_RCC_CCIPR_LPUART1SEL_MSK (0x3UL << STM32_RCC_CCIPR_LPUART1SEL_POS)
+#define STM32_RCC_CCIPR_LPUART1SEL STM32_RCC_CCIPR_LPUART1SEL_MSK
+#define STM32_RCC_CCIPR_LPUART1SEL_0 (0x1UL << STM32_RCC_CCIPR_LPUART1SEL_POS)
+#define STM32_RCC_CCIPR_LPUART1SEL_1 (0x2UL << STM32_RCC_CCIPR_LPUART1SEL_POS)
+
+#define STM32_RCC_CCIPR_I2C1SEL_POS 12U
+#define STM32_RCC_CCIPR_I2C1SEL_MSK (0x3UL << STM32_RCC_CCIPR_I2C1SEL_POS)
+#define STM32_RCC_CCIPR_I2C1SEL STM32_RCC_CCIPR_I2C1SEL_MSK
+#define STM32_RCC_CCIPR_I2C1SEL_0 (0x1UL << STM32_RCC_CCIPR_I2C1SEL_POS)
+#define STM32_RCC_CCIPR_I2C1SEL_1 (0x2UL << STM32_RCC_CCIPR_I2C1SEL_POS)
+
+#define STM32_RCC_CCIPR_I2C2SEL_POS 14U
+#define STM32_RCC_CCIPR_I2C2SEL_MSK (0x3UL << STM32_RCC_CCIPR_I2C2SEL_POS)
+#define STM32_RCC_CCIPR_I2C2SEL STM32_RCC_CCIPR_I2C2SEL_MSK
+#define STM32_RCC_CCIPR_I2C2SEL_0 (0x1UL << STM32_RCC_CCIPR_I2C2SEL_POS)
+#define STM32_RCC_CCIPR_I2C2SEL_1 (0x2UL << STM32_RCC_CCIPR_I2C2SEL_POS)
+
+#define STM32_RCC_CCIPR_I2C3SEL_POS 16U
+#define STM32_RCC_CCIPR_I2C3SEL_MSK (0x3UL << STM32_RCC_CCIPR_I2C3SEL_POS)
+#define STM32_RCC_CCIPR_I2C3SEL STM32_RCC_CCIPR_I2C3SEL_MSK
+#define STM32_RCC_CCIPR_I2C3SEL_0 (0x1UL << STM32_RCC_CCIPR_I2C3SEL_POS)
+#define STM32_RCC_CCIPR_I2C3SEL_1 (0x2UL << STM32_RCC_CCIPR_I2C3SEL_POS)
+
+#define STM32_RCC_CCIPR_LPTIM1SEL_POS 18U
+#define STM32_RCC_CCIPR_LPTIM1SEL_MSK (0x3UL << STM32_RCC_CCIPR_LPTIM1SEL_POS)
+#define STM32_RCC_CCIPR_LPTIM1SEL STM32_RCC_CCIPR_LPTIM1SEL_MSK
+#define STM32_RCC_CCIPR_LPTIM1SEL_0 (0x1UL << STM32_RCC_CCIPR_LPTIM1SEL_POS)
+#define STM32_RCC_CCIPR_LPTIM1SEL_1 (0x2UL << STM32_RCC_CCIPR_LPTIM1SEL_POS)
+
+#define STM32_RCC_CCIPR_LPTIM2SEL_POS 20U
+#define STM32_RCC_CCIPR_LPTIM2SEL_MSK (0x3UL << STM32_RCC_CCIPR_LPTIM2SEL_POS)
+#define STM32_RCC_CCIPR_LPTIM2SEL STM32_RCC_CCIPR_LPTIM2SEL_MSK
+#define STM32_RCC_CCIPR_LPTIM2SEL_0 (0x1UL << STM32_RCC_CCIPR_LPTIM2SEL_POS)
+#define STM32_RCC_CCIPR_LPTIM2SEL_1 (0x2UL << STM32_RCC_CCIPR_LPTIM2SEL_POS)
+
+#define STM32_RCC_CCIPR_SAI1SEL_POS 22U
+#define STM32_RCC_CCIPR_SAI1SEL_MSK (0x3UL << STM32_RCC_CCIPR_SAI1SEL_POS)
+#define STM32_RCC_CCIPR_SAI1SEL STM32_RCC_CCIPR_SAI1SEL_MSK
+#define STM32_RCC_CCIPR_SAI1SEL_0 (0x1UL << STM32_RCC_CCIPR_SAI1SEL_POS)
+#define STM32_RCC_CCIPR_SAI1SEL_1 (0x2UL << STM32_RCC_CCIPR_SAI1SEL_POS)
+
+#define STM32_RCC_CCIPR_CLK48SEL_POS 26U
+#define STM32_RCC_CCIPR_CLK48SEL_MSK (0x3UL << STM32_RCC_CCIPR_CLK48SEL_POS)
+#define STM32_RCC_CCIPR_CLK48SEL STM32_RCC_CCIPR_CLK48SEL_MSK
+#define STM32_RCC_CCIPR_CLK48SEL_0 (0x1UL << STM32_RCC_CCIPR_CLK48SEL_POS)
+#define STM32_RCC_CCIPR_CLK48SEL_1 (0x2UL << STM32_RCC_CCIPR_CLK48SEL_POS)
+
+#define STM32_RCC_CCIPR_ADCSEL_POS 28U
+#define STM32_RCC_CCIPR_ADCSEL_MSK (0x3UL << STM32_RCC_CCIPR_ADCSEL_POS)
+#define STM32_RCC_CCIPR_ADCSEL STM32_RCC_CCIPR_ADCSEL_MSK
+#define STM32_RCC_CCIPR_ADCSEL_0 (0x1UL << STM32_RCC_CCIPR_ADCSEL_POS)
+#define STM32_RCC_CCIPR_ADCSEL_1 (0x2UL << STM32_RCC_CCIPR_ADCSEL_POS)
+
+#define STM32_RCC_CCIPR_SWPMI1SEL_POS 30U
+#define STM32_RCC_CCIPR_SWPMI1SEL_MSK (0x1UL << STM32_RCC_CCIPR_SWPMI1SEL_POS)
+#define STM32_RCC_CCIPR_SWPMI1SEL STM32_RCC_CCIPR_SWPMI1SEL_MSK
+
+/**************  Bit definition for STM32_RCC_CCIPR2 register  ****************/
+#define STM32_RCC_CCIPR2_I2C4SEL_POS 0U
+#define STM32_RCC_CCIPR2_I2C4SEL_MSK (0x3UL << STM32_RCC_CCIPR2_I2C4SEL_POS)
+#define STM32_RCC_CCIPR2_I2C4SEL STM32_RCC_CCIPR2_I2C4SEL_MSK
+#define STM32_RCC_CCIPR2_I2C4SEL_0 (0x1UL << STM32_RCC_CCIPR2_I2C4SEL_POS)
+#define STM32_RCC_CCIPR2_I2C4SEL_1 (0x2UL << STM32_RCC_CCIPR2_I2C4SEL_POS)
+
+/**************  BIT DEFINITION FOR STM32_RCC_BDCR REGISTER  ******************/
+#define STM32_RCC_BDCR_LSEBYP_POS 2U
+#define STM32_RCC_BDCR_LSEBYP_MSK (0x1UL << STM32_RCC_BDCR_LSEBYP_POS)
+#define STM32_RCC_BDCR_LSEBYP STM32_RCC_BDCR_LSEBYP_MSK
+
+#define STM32_RCC_BDCR_LSEDRV_POS 3U
+#define STM32_RCC_BDCR_LSEDRV_MSK (0x3UL << STM32_RCC_BDCR_LSEDRV_POS)
+#define STM32_RCC_BDCR_LSEDRV STM32_RCC_BDCR_LSEDRV_MSK
+#define STM32_RCC_BDCR_LSEDRV_0 (0x1UL << STM32_RCC_BDCR_LSEDRV_POS)
+#define STM32_RCC_BDCR_LSEDRV_1 (0x2UL << STM32_RCC_BDCR_LSEDRV_POS)
+
+#define STM32_RCC_BDCR_LSECSSON_POS 5U
+#define STM32_RCC_BDCR_LSECSSON_MSK (0x1UL << STM32_RCC_BDCR_LSECSSON_POS)
+#define STM32_RCC_BDCR_LSECSSON STM32_RCC_BDCR_LSECSSON_MSK
+#define STM32_RCC_BDCR_LSECSSD_POS 6U
+#define STM32_RCC_BDCR_LSECSSD_MSK (0x1UL << STM32_RCC_BDCR_LSECSSD_POS)
+#define STM32_RCC_BDCR_LSECSSD STM32_RCC_BDCR_LSECSSD_MSK
+
+#define STM32_RCC_BDCR_RTCSEL_POS 8U
+#define STM32_RCC_BDCR_RTCSEL_MSK (0x3UL << STM32_RCC_BDCR_RTCSEL_POS)
+#define STM32_RCC_BDCR_RTCSEL STM32_RCC_BDCR_RTCSEL_MSK
+#define STM32_RCC_BDCR_RTCSEL_0 (0x1UL << STM32_RCC_BDCR_RTCSEL_POS)
+#define STM32_RCC_BDCR_RTCSEL_1 (0x2UL << STM32_RCC_BDCR_RTCSEL_POS)
+
+#define STM32_RCC_BDCR_LSCOEN_POS 24U
+#define STM32_RCC_BDCR_LSCOEN_MSK (0x1UL << STM32_RCC_BDCR_LSCOEN_POS)
+#define STM32_RCC_BDCR_LSCOEN STM32_RCC_BDCR_LSCOEN_MSK
+#define STM32_RCC_BDCR_LSCOSEL_POS 25U
+#define STM32_RCC_BDCR_LSCOSEL_MSK (0x1UL << STM32_RCC_BDCR_LSCOSEL_POS)
+#define STM32_RCC_BDCR_LSCOSEL STM32_RCC_BDCR_LSCOSEL_MSK
+
+/**************  BIT DEFINITION FOR STM32_RCC_CSR REGISTER  *******************/
+#define STM32_RCC_CSR_LSION_POS 0U
+#define STM32_RCC_CSR_LSION_MSK (0x1UL << STM32_RCC_CSR_LSION_POS)
+#define STM32_RCC_CSR_LSION STM32_RCC_CSR_LSION_MSK
+#define STM32_RCC_CSR_LSIRDY_POS 1U
+#define STM32_RCC_CSR_LSIRDY_MSK (0x1UL << STM32_RCC_CSR_LSIRDY_POS)
+#define STM32_RCC_CSR_LSIRDY STM32_RCC_CSR_LSIRDY_MSK
+
+#define STM32_RCC_CSR_MSISRANGE_POS 8U
+#define STM32_RCC_CSR_MSISRANGE_MSK (0xFUL << STM32_RCC_CSR_MSISRANGE_POS)
+#define STM32_RCC_CSR_MSISRANGE STM32_RCC_CSR_MSISRANGE_MSK
+#define STM32_RCC_CSR_MSISRANGE_1 (0x4UL << STM32_RCC_CSR_MSISRANGE_POS)
+#define STM32_RCC_CSR_MSISRANGE_2 (0x5UL << STM32_RCC_CSR_MSISRANGE_POS)
+#define STM32_RCC_CSR_MSISRANGE_4 (0x6UL << STM32_RCC_CSR_MSISRANGE_POS)
+#define STM32_RCC_CSR_MSISRANGE_8 (0x7UL << STM32_RCC_CSR_MSISRANGE_POS)
+
+#define STM32_RCC_CSR_RMVF_POS 23U
+#define STM32_RCC_CSR_RMVF_MSK (0x1UL << STM32_RCC_CSR_RMVF_POS)
+#define STM32_RCC_CSR_RMVF STM32_RCC_CSR_RMVF_MSK
+#define STM32_RCC_CSR_FWRSTF_POS 24U
+#define STM32_RCC_CSR_FWRSTF_MSK (0x1UL << STM32_RCC_CSR_FWRSTF_POS)
+#define STM32_RCC_CSR_FWRSTF STM32_RCC_CSR_FWRSTF_MSK
+#define STM32_RCC_CSR_OBLRSTF_POS 25U
+#define STM32_RCC_CSR_OBLRSTF_MSK (0x1UL << STM32_RCC_CSR_OBLRSTF_POS)
+#define STM32_RCC_CSR_OBLRSTF STM32_RCC_CSR_OBLRSTF_MSK
+#define STM32_RCC_CSR_PINRSTF_POS 26U
+#define STM32_RCC_CSR_PINRSTF_MSK (0x1UL << STM32_RCC_CSR_PINRSTF_POS)
+#define STM32_RCC_CSR_PINRSTF STM32_RCC_CSR_PINRSTF_MSK
+#define STM32_RCC_CSR_BORRSTF_POS 27U
+#define STM32_RCC_CSR_BORRSTF_MSK (0x1UL << STM32_RCC_CSR_BORRSTF_POS)
+#define STM32_RCC_CSR_BORRSTF STM32_RCC_CSR_BORRSTF_MSK
+#define STM32_RCC_CSR_SFTRSTF_POS 28U
+#define STM32_RCC_CSR_SFTRSTF_MSK (0x1UL << STM32_RCC_CSR_SFTRSTF_POS)
+#define STM32_RCC_CSR_SFTRSTF STM32_RCC_CSR_SFTRSTF_MSK
+#define STM32_RCC_CSR_IWDGRSTF_POS 29U
+#define STM32_RCC_CSR_IWDGRSTF_MSK (0x1UL << STM32_RCC_CSR_IWDGRSTF_POS)
+#define STM32_RCC_CSR_IWDGRSTF STM32_RCC_CSR_IWDGRSTF_MSK
+#define STM32_RCC_CSR_WWDGRSTF_POS 30U
+#define STM32_RCC_CSR_WWDGRSTF_MSK (0x1UL << STM32_RCC_CSR_WWDGRSTF_POS)
+#define STM32_RCC_CSR_WWDGRSTF STM32_RCC_CSR_WWDGRSTF_MSK
+#define STM32_RCC_CSR_LPWRRSTF_POS 31U
+#define STM32_RCC_CSR_LPWRRSTF_MSK (0x1UL << STM32_RCC_CSR_LPWRRSTF_POS)
+#define STM32_RCC_CSR_LPWRRSTF STM32_RCC_CSR_LPWRRSTF_MSK
+
+/**************  Bit definition for STM32_RCC_CRRCR register  *****************/
+#define STM32_RCC_CRRCR_HSI48ON_POS 0U
+#define STM32_RCC_CRRCR_HSI48ON_MSK (0x1UL << STM32_RCC_CRRCR_HSI48ON_POS)
+#define STM32_RCC_CRRCR_HSI48ON STM32_RCC_CRRCR_HSI48ON_MSK
+#define STM32_RCC_CRRCR_HSI48RDY_POS 1U
+#define STM32_RCC_CRRCR_HSI48RDY_MSK (0x1UL << STM32_RCC_CRRCR_HSI48RDY_POS)
+#define STM32_RCC_CRRCR_HSI48RDY STM32_RCC_CRRCR_HSI48RDY_MSK
+
+/*!< HSI48CAL configuration */
+#define STM32_RCC_CRRCR_HSI48CAL_POS 7U
+#define STM32_RCC_CRRCR_HSI48CAL_MSK (0x1FFUL << STM32_RCC_CRRCR_HSI48CAL_POS)
+#define STM32_RCC_CRRCR_HSI48CAL STM32_RCC_CRRCR_HSI48CAL_MSK
+#define STM32_RCC_CRRCR_HSI48CAL_0 (0x001UL << STM32_RCC_CRRCR_HSI48CAL_POS)
+#define STM32_RCC_CRRCR_HSI48CAL_1 (0x002UL << STM32_RCC_CRRCR_HSI48CAL_POS)
+#define STM32_RCC_CRRCR_HSI48CAL_2 (0x004UL << STM32_RCC_CRRCR_HSI48CAL_POS)
+#define STM32_RCC_CRRCR_HSI48CAL_3 (0x008UL << STM32_RCC_CRRCR_HSI48CAL_POS)
+#define STM32_RCC_CRRCR_HSI48CAL_4 (0x010UL << STM32_RCC_CRRCR_HSI48CAL_POS)
+#define STM32_RCC_CRRCR_HSI48CAL_5 (0x020UL << STM32_RCC_CRRCR_HSI48CAL_POS)
+#define STM32_RCC_CRRCR_HSI48CAL_6 (0x040UL << STM32_RCC_CRRCR_HSI48CAL_POS)
+#define STM32_RCC_CRRCR_HSI48CAL_7 (0x080UL << STM32_RCC_CRRCR_HSI48CAL_POS)
+#define STM32_RCC_CRRCR_HSI48CAL_8 (0x100UL << STM32_RCC_CRRCR_HSI48CAL_POS)
+
+#define STM32_SYSCFG_CFGR1 REG32(STM32_SYSCFG_BASE + 0x04)
+#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
+#define STM32_SYSCFG_I2CFMP(n) BIT(n + 21)
+
+/* Peripheral bits for STM32_RCC_APB/AHB and DBGMCU regs */
+#define STM32_RCC_PB1_PWREN BIT(28)
+
+#define STM32_RCC_PB2_SYSCFGEN BIT(0)
+#define STM32_RCC_PB2_USART1 BIT(14)
+
+#define STM32_RCC_HB1_DMA1 BIT(0)
+#define STM32_RCC_HB1_DMA2 BIT(1)
+
+#define STM32_RCC_HB2_GPIOA BIT(0)
+#define STM32_RCC_HB2_GPIOB BIT(1)
+#define STM32_RCC_HB2_GPIOC BIT(2)
+#define STM32_RCC_HB2_GPIOD BIT(3)
+#define STM32_RCC_HB2_GPIOE BIT(4)
+#define STM32_RCC_HB2_GPIOH BIT(7)
+#define STM32_RCC_HB2_ADC1 BIT(13)
 
 /* Reset causes definitions */
 /* Reset causes in RCC CSR register */
 #define STM32_RCC_RESET_CAUSE STM32_RCC_CSR
-#define  RESET_CAUSE_WDG                0x60000000
-#define  RESET_CAUSE_SFT                0x10000000
-#define  RESET_CAUSE_POR                0x08000000
-#define  RESET_CAUSE_PIN                0x04000000
-#define  RESET_CAUSE_OTHER              0xfe000000
-#define  RESET_CAUSE_RMVF               0x01000000
+#define RESET_CAUSE_WDG 0x60000000
+#define RESET_CAUSE_SFT 0x10000000
+#define RESET_CAUSE_POR 0x08000000
+#define RESET_CAUSE_PIN 0x04000000
+#define RESET_CAUSE_OTHER 0xff000000
+#define RESET_CAUSE_RMVF BIT(23)
 /* Power cause in PWR CSR register */
 #define STM32_PWR_RESET_CAUSE STM32_PWR_CSR
-#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR
-#define  RESET_CAUSE_SBF                0x00000002
-#define  RESET_CAUSE_SBF_CLR            0x00000004
+#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_SCR
+#define RESET_CAUSE_SBF BIT(8)
+#define RESET_CAUSE_SBF_CLR BIT(8)
 
 /* --- Watchdogs --- */
 
 /* --- Real-Time Clock --- */
-#define STM32_RTC_TR                REG32(STM32_RTC_BASE + 0x00)
-#define STM32_RTC_DR                REG32(STM32_RTC_BASE + 0x04)
-#define STM32_RTC_CR                REG32(STM32_RTC_BASE + 0x08)
-#define STM32_RTC_CR_BYPSHAD        BIT(5)
-#define STM32_RTC_CR_ALRAE          BIT(8)
-#define STM32_RTC_CR_ALRAIE         BIT(12)
-#define STM32_RTC_ISR               REG32(STM32_RTC_BASE + 0x0C)
-#define STM32_RTC_ISR_ALRAWF        BIT(0)
-#define STM32_RTC_ISR_RSF           BIT(5)
-#define STM32_RTC_ISR_INITF         BIT(6)
-#define STM32_RTC_ISR_INIT          BIT(7)
-#define STM32_RTC_ISR_ALRAF         BIT(8)
-#define STM32_RTC_PRER              REG32(STM32_RTC_BASE + 0x10)
-#define STM32_RTC_PRER_A_MASK       (0x7f << 16)
-#define STM32_RTC_PRER_S_MASK       (0x7fff << 0)
-#define STM32_RTC_WUTR              REG32(STM32_RTC_BASE + 0x14)
-#define STM32_RTC_CALIBR            REG32(STM32_RTC_BASE + 0x18)
-#define STM32_RTC_ALRMAR            REG32(STM32_RTC_BASE + 0x1C)
-#define STM32_RTC_ALRMBR            REG32(STM32_RTC_BASE + 0x20)
-#define STM32_RTC_WPR               REG32(STM32_RTC_BASE + 0x24)
-#define STM32_RTC_SSR               REG32(STM32_RTC_BASE + 0x28)
-#define STM32_RTC_TSTR              REG32(STM32_RTC_BASE + 0x30)
-#define STM32_RTC_TSDR              REG32(STM32_RTC_BASE + 0x34)
-#define STM32_RTC_TAFCR             REG32(STM32_RTC_BASE + 0x40)
-#define STM32_RTC_ALRMASSR          REG32(STM32_RTC_BASE + 0x44)
-#define STM32_RTC_BACKUP(n)         REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
-
-#define STM32_BKP_DATA(n)           STM32_RTC_BACKUP(n)
-#define STM32_BKP_BYTES             128
+#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00)
+#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04)
+#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08)
+#define STM32_RTC_CR_BYPSHAD BIT(5)
+#define STM32_RTC_CR_ALRAE BIT(8)
+#define STM32_RTC_CR_WUTE BIT(10)
+#define STM32_RTC_CR_ALRAIE BIT(12)
+#define STM32_RTC_CR_WUTIE BIT(14)
+#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C)
+#define STM32_RTC_ISR_ALRAWF BIT(0)
+#define STM32_RTC_ISR_WUTWF BIT(2)
+#define STM32_RTC_ISR_INITS BIT(4)
+#define STM32_RTC_ISR_RSF BIT(5)
+#define STM32_RTC_ISR_INITF BIT(6)
+#define STM32_RTC_ISR_INIT BIT(7)
+#define STM32_RTC_ISR_ALRAF BIT(8)
+#define STM32_RTC_ISR_WUTF BIT(9)
+#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10)
+#define STM32_RTC_PRER_A_MASK (0x7f << 16)
+#define STM32_RTC_PRER_S_MASK (0x7fff << 0)
+#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14)
+#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18)
+#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C)
+#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20)
+#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24)
+#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28)
+#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30)
+#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34)
+#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40)
+#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44)
+#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
+
+#define STM32_RTC_CLEAR_FLAG(x)                         \
+	(STM32_RTC_ISR = (~((x) | STM32_RTC_ISR_INIT) | \
+			  (STM32_RTC_ISR & STM32_RTC_ISR_INIT)))
+
+#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n)
+#define STM32_BKP_BYTES 128
+
+#define RTC_TR_PM_POS 22U
+#define RTC_TR_PM_MSK (0x1UL << RTC_TR_PM_POS)
+#define RTC_TR_PM RTC_TR_PM_MSK
+#define RTC_TR_HT_POS 20U
+#define RTC_TR_HT_MSK (0x3UL << RTC_TR_HT_POS)
+#define RTC_TR_HT RTC_TR_HT_MSK
+#define RTC_TR_HU_POS 16U
+#define RTC_TR_HU_MSK (0xFUL << RTC_TR_HU_POS)
+#define RTC_TR_HU RTC_TR_HU_MSK
+#define RTC_TR_MNT_POS 12U
+#define RTC_TR_MNT_MSK (0x7UL << RTC_TR_MNT_POS)
+#define RTC_TR_MNT RTC_TR_MNT_MSK
+#define RTC_TR_MNU_POS 8U
+#define RTC_TR_MNU_MSK (0xFUL << RTC_TR_MNU_POS)
+#define RTC_TR_MNU RTC_TR_MNU_MSK
+#define RTC_TR_ST_POS 4U
+#define RTC_TR_ST_MSK (0x7UL << RTC_TR_ST_POS)
+#define RTC_TR_ST RTC_TR_ST_MSK
+#define RTC_TR_SU_POS 0U
+#define RTC_TR_SU_MSK (0xFUL << RTC_TR_SU_POS)
+#define RTC_TR_SU RTC_TR_SU_MSK
 
 /* --- SPI --- */
 
@@ -555,15 +1814,15 @@ struct stm32_spi_regs {
 	uint16_t _pad0;
 	uint16_t cr2;
 	uint16_t _pad1;
-	unsigned sr;
+	unsigned int sr;
 	uint8_t dr;
 	uint8_t _pad2;
 	uint16_t _pad3;
-	unsigned crcpr;
-	unsigned rxcrcr;
-	unsigned txcrcr;
-	unsigned i2scfgr;	/* STM32L only */
-	unsigned i2spr;		/* STM32L only */
+	unsigned int crcpr;
+	unsigned int rxcrcr;
+	unsigned int txcrcr;
+	unsigned int i2scfgr; /* STM32L only */
+	unsigned int i2spr; /* STM32L only */
 };
 /* Must be volatile, or compiler optimizes out repeated accesses */
 typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
@@ -573,92 +1832,152 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
 #define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE)
 #define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE)
 
-#define STM32_SPI_CR1_BIDIMODE		BIT(15)
-#define STM32_SPI_CR1_BIDIOE		BIT(14)
-#define STM32_SPI_CR1_CRCEN		BIT(13)
-#define STM32_SPI_CR1_SSM		BIT(9)
-#define STM32_SPI_CR1_SSI		BIT(8)
-#define STM32_SPI_CR1_LSBFIRST		BIT(7)
-#define STM32_SPI_CR1_SPE		BIT(6)
-#define STM32_SPI_CR1_BR_DIV64R		(5 << 3)
-#define STM32_SPI_CR1_BR_DIV4R		BIT(3)
-#define STM32_SPI_CR1_MSTR		BIT(2)
-#define STM32_SPI_CR1_CPOL		BIT(1)
-#define STM32_SPI_CR1_CPHA		BIT(0)
-#define STM32_SPI_CR2_FRXTH		BIT(12)
-#define STM32_SPI_CR2_DATASIZE(n)	(((n) - 1) << 8)
-#define STM32_SPI_CR2_TXEIE		BIT(7)
-#define STM32_SPI_CR2_RXNEIE		BIT(6)
-#define STM32_SPI_CR2_NSSP		BIT(3)
-#define STM32_SPI_CR2_SSOE		BIT(2)
-#define STM32_SPI_CR2_TXDMAEN		BIT(1)
-#define STM32_SPI_CR2_RXDMAEN		BIT(0)
-
-#define STM32_SPI_SR_RXNE		BIT(0)
-#define STM32_SPI_SR_TXE		BIT(1)
-#define STM32_SPI_SR_CRCERR		BIT(4)
-#define STM32_SPI_SR_BSY		BIT(7)
-#define STM32_SPI_SR_FRLVL		(3 << 9)
-#define STM32_SPI_SR_FTLVL		(3 << 11)
+#define STM32_SPI_CR1_BIDIMODE BIT(15)
+#define STM32_SPI_CR1_BIDIOE BIT(14)
+#define STM32_SPI_CR1_CRCEN BIT(13)
+#define STM32_SPI_CR1_SSM BIT(9)
+#define STM32_SPI_CR1_SSI BIT(8)
+#define STM32_SPI_CR1_LSBFIRST BIT(7)
+#define STM32_SPI_CR1_SPE BIT(6)
+#define STM32_SPI_CR1_BR_DIV64R (5 << 3)
+#define STM32_SPI_CR1_BR_DIV4R BIT(3)
+#define STM32_SPI_CR1_MSTR BIT(2)
+#define STM32_SPI_CR1_CPOL BIT(1)
+#define STM32_SPI_CR1_CPHA BIT(0)
+#define STM32_SPI_CR2_FRXTH BIT(12)
+#define STM32_SPI_CR2_DATASIZE(n) (((n)-1) << 8)
+#define STM32_SPI_CR2_TXEIE BIT(7)
+#define STM32_SPI_CR2_RXNEIE BIT(6)
+#define STM32_SPI_CR2_NSSP BIT(3)
+#define STM32_SPI_CR2_SSOE BIT(2)
+#define STM32_SPI_CR2_TXDMAEN BIT(1)
+#define STM32_SPI_CR2_RXDMAEN BIT(0)
+
+#define STM32_SPI_SR_RXNE BIT(0)
+#define STM32_SPI_SR_TXE BIT(1)
+#define STM32_SPI_SR_CRCERR BIT(4)
+#define STM32_SPI_SR_BSY BIT(7)
+#define STM32_SPI_SR_FRLVL (3 << 9)
+#define STM32_SPI_SR_FTLVL (3 << 11)
 /* --- Debug --- */
-#define STM32_DBGMCU_APB1FZ         REG32(STM32_DBGMCU_BASE + 0x08)
-#define STM32_DBGMCU_APB2FZ         REG32(STM32_DBGMCU_BASE + 0x0C)
+#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08)
+#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C)
 
 /* --- Flash --- */
-#define STM32_FLASH_ACR             REG32(STM32_FLASH_REGS_BASE + 0x00)
+#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00)
 #define STM32_FLASH_ACR_LATENCY_SHIFT (0)
-#define STM32_FLASH_ACR_LATENCY_MASK  (7 << STM32_FLASH_ACR_LATENCY_SHIFT)
-#define STM32_FLASH_ACR_PRFTEN      BIT(8)
-#define STM32_FLASH_ACR_ICEN        BIT(9)
-#define STM32_FLASH_ACR_DCEN        BIT(10)
-#define STM32_FLASH_ACR_ICRST       BIT(11)
-#define STM32_FLASH_ACR_DCRST       BIT(12)
-#define STM32_FLASH_PDKEYR          REG32(STM32_FLASH_REGS_BASE + 0x04)
-#define STM32_FLASH_KEYR            REG32(STM32_FLASH_REGS_BASE + 0x08)
-#define  FLASH_KEYR_KEY1            0x45670123
-#define  FLASH_KEYR_KEY2            0xCDEF89AB
-#define STM32_FLASH_OPTKEYR         REG32(STM32_FLASH_REGS_BASE + 0x0c)
-#define  FLASH_OPTKEYR_KEY1         0x08192A3B
-#define  FLASH_OPTKEYR_KEY2         0x4C5D6E7F
-#define STM32_FLASH_SR              REG32(STM32_FLASH_REGS_BASE + 0x10)
-#define  FLASH_SR_BUSY              BIT(16)
-#define  FLASH_SR_ERR_MASK          (0xc3fa)
-#define STM32_FLASH_CR              REG32(STM32_FLASH_REGS_BASE + 0x14)
-#define  FLASH_CR_PG                BIT(0)
-#define  FLASH_CR_PER               BIT(1)
-#define  FLASH_CR_STRT              BIT(16)
-#define  FLASH_CR_OPTSTRT           BIT(17)
-#define  FLASH_CR_OBL_LAUNCH        BIT(27)
-#define  FLASH_CR_OPTLOCK           BIT(30)
-#define  FLASH_CR_LOCK              BIT(31)
-#define  FLASH_CR_PNB(sec)          (((sec) & 0xff) << 3)
-#define  FLASH_CR_PNB_MASK          FLASH_CR_PNB(0xff)
-#define STM32_FLASH_ECCR            REG32(STM32_FLASH_REGS_BASE + 0x18)
-#define STM32_FLASH_OPTR            REG32(STM32_FLASH_REGS_BASE + 0x20)
-#define STM32_FLASH_PCROP1SR        REG32(STM32_FLASH_REGS_BASE + 0x24)
-#define STM32_FLASH_PCROP1ER        REG32(STM32_FLASH_REGS_BASE + 0x28)
-#define STM32_FLASH_WRP1AR          REG32(STM32_FLASH_REGS_BASE + 0x2C)
-#define STM32_FLASH_WRP1BR          REG32(STM32_FLASH_REGS_BASE + 0x30)
+#define STM32_FLASH_ACR_LATENCY_MASK (7 << STM32_FLASH_ACR_LATENCY_SHIFT)
+#define STM32_FLASH_ACR_PRFTEN BIT(8)
+#define STM32_FLASH_ACR_ICEN BIT(9)
+#define STM32_FLASH_ACR_DCEN BIT(10)
+#define STM32_FLASH_ACR_ICRST BIT(11)
+#define STM32_FLASH_ACR_DCRST BIT(12)
+#define STM32_FLASH_PDKEYR REG32(STM32_FLASH_REGS_BASE + 0x04)
+#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x08)
+#define FLASH_KEYR_KEY1 0x45670123
+#define FLASH_KEYR_KEY2 0xCDEF89AB
+#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x0c)
+#define FLASH_OPTKEYR_KEY1 0x08192A3B
+#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F
+#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x10)
+#define FLASH_SR_BUSY BIT(16)
+#define FLASH_SR_ERR_MASK (0xc3fa)
+#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x14)
+#define FLASH_CR_PG BIT(0)
+#define FLASH_CR_PER BIT(1)
+#define FLASH_CR_STRT BIT(16)
+#define FLASH_CR_OPTSTRT BIT(17)
+#define FLASH_CR_OBL_LAUNCH BIT(27)
+#define FLASH_CR_OPTLOCK BIT(30)
+#define FLASH_CR_LOCK BIT(31)
+#define FLASH_CR_PNB(sec) (((sec)&0xff) << 3)
+#define FLASH_CR_PNB_MASK FLASH_CR_PNB(0xff)
+#define STM32_FLASH_ECCR REG32(STM32_FLASH_REGS_BASE + 0x18)
+#define STM32_FLASH_OPTR REG32(STM32_FLASH_REGS_BASE + 0x20)
+#define STM32_FLASH_PCROP1SR REG32(STM32_FLASH_REGS_BASE + 0x24)
+#define STM32_FLASH_PCROP1ER REG32(STM32_FLASH_REGS_BASE + 0x28)
+#define STM32_FLASH_WRP1AR REG32(STM32_FLASH_REGS_BASE + 0x2C)
+#define STM32_FLASH_WRP1BR REG32(STM32_FLASH_REGS_BASE + 0x30)
 /* Minimum number of bytes that can be written to flash */
-#define STM32_FLASH_MIN_WRITE_SIZE  CONFIG_FLASH_WRITE_SIZE
+#define STM32_FLASH_MIN_WRITE_SIZE CONFIG_FLASH_WRITE_SIZE
 
-#define STM32_OPTB_USER_RDP         REG32(STM32_OPTB_BASE + 0x00)
-#define STM32_OPTB_WRP1AR           REG32(STM32_OPTB_BASE + 0x18)
-#define STM32_OPTB_WRP1BR           REG32(STM32_OPTB_BASE + 0x20)
+#define STM32_OPTB_USER_RDP REG32(STM32_OPTB_BASE + 0x00)
+#define STM32_OPTB_WRP1AR REG32(STM32_OPTB_BASE + 0x18)
+#define STM32_OPTB_WRP1BR REG32(STM32_OPTB_BASE + 0x20)
 
 /* --- External Interrupts --- */
-#define STM32_EXTI_IMR              REG32(STM32_EXTI_BASE + 0x00)
-#define STM32_EXTI_EMR              REG32(STM32_EXTI_BASE + 0x04)
-#define STM32_EXTI_RTSR             REG32(STM32_EXTI_BASE + 0x08)
-#define STM32_EXTI_FTSR             REG32(STM32_EXTI_BASE + 0x0c)
-#define STM32_EXTI_SWIER            REG32(STM32_EXTI_BASE + 0x10)
-#define STM32_EXTI_PR               REG32(STM32_EXTI_BASE + 0x14)
+#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00)
+#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04)
+#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08)
+#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c)
+#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10)
+#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14)
 
+#define EXTI_RTC_ALR_EVENT BIT(18)
 
 /* --- ADC --- */
-
-/* --- Comparators --- */
-
+#define STM32_ADC1_ISR REG32(STM32_ADC1_BASE + 0x00)
+#define STM32_ADC1_ISR_ADRDY BIT(0)
+#define STM32_ADC1_IER REG32(STM32_ADC1_BASE + 0x04)
+#define STM32_ADC1_IER_AWDIE BIT(7)
+#define STM32_ADC1_IER_OVRIE BIT(4)
+#define STM32_ADC1_IER_EOSEQIE BIT(3)
+#define STM32_ADC1_IER_EOCIE BIT(2)
+#define STM32_ADC1_IER_EOSMPIE BIT(1)
+#define STM32_ADC1_IER_ADRDYIE BIT(0)
+
+#define STM32_ADC1_CR REG32(STM32_ADC1_BASE + 0x08)
+#define STM32_ADC1_CR_ADEN BIT(0)
+#define STM32_ADC1_CR_ADDIS BIT(1)
+#define STM32_ADC1_CR_ADSTP BIT(4)
+#define STM32_ADC1_CR_ADVREGEN BIT(28)
+#define STM32_ADC1_CR_DEEPPWD BIT(29)
+#define STM32_ADC1_CR_ADCAL BIT(31)
+#define STM32_ADC1_CFGR REG32(STM32_ADC1_BASE + 0x0C)
+/* Analog watchdog channel selection */
+#define STM32_ADC1_CFGR_AWDCH_MASK (0x1f << 26)
+#define STM32_ADC1_CFGR_AWDEN BIT(23)
+#define STM32_ADC1_CFGR_AWDSGL BIT(22)
+#define STM32_ADC1_CFGR_AUTDLY BIT(14)
+/* Selects single vs continuous */
+#define STM32_ADC1_CFGR_CONT BIT(13)
+/* Selects ADC_DR overwrite vs preserve */
+#define STM32_ADC1_CFGR_OVRMOD BIT(12)
+/* External trigger polarity selection */
+#define STM32_ADC1_CFGR_EXTEN_DIS (0 << 10)
+#define STM32_ADC1_CFGR_EXTEN_RISE (1 << 10)
+#define STM32_ADC1_CFGR_EXTEN_FALL (2 << 10)
+#define STM32_ADC1_CFGR_EXTEN_BOTH (3 << 10)
+#define STM32_ADC1_CFGR_EXTEN_MASK (3 << 10)
+#define STM32_ADC1_CFGR_ALIGN BIT(5)
+/* External trigger selection */
+#define STM32_ADC1_CFGR_TRG0 (0 << 6)
+#define STM32_ADC1_CFGR_TRG1 (1 << 6)
+#define STM32_ADC1_CFGR_TRG2 (2 << 6)
+#define STM32_ADC1_CFGR_TRG3 (3 << 6)
+#define STM32_ADC1_CFGR_TRG4 (4 << 6)
+#define STM32_ADC1_CFGR_TRG5 (5 << 6)
+#define STM32_ADC1_CFGR_TRG6 (6 << 6)
+#define STM32_ADC1_CFGR_TRG7 (7 << 6)
+#define STM32_ADC1_CFGR_TRG_MASK (7 << 6)
+/* Selects circular vs one-shot */
+#define STM32_ADC1_CFGR_DMACFG BIT(1)
+#define STM32_ADC1_CFGR_DMAEN BIT(0)
+#define STM32_ADC1_CFGR2 REG32(STM32_ADC1_BASE + 0x10)
+/* Sampling time selection - 1.5 ADC cycles min, 239.5 cycles max */
+#define STM32_ADC1_SMPR1 REG32(STM32_ADC1_BASE + 0x14)
+#define STM32_ADC1_SMPR2 REG32(STM32_ADC1_BASE + 0x18)
+/* Macro to convert enum stm32_adc_smpr to SMP bits of the ADC_SMPR register */
+#define STM32_ADC1_SMPR_SMP(s) ((s)-1)
+#define STM32_ADC1_TR REG32(STM32_ADC1_BASE + 0x20)
+#define STM32_ADC1_CHSELR REG32(STM32_ADC1_BASE + 0x28)
+#define STM32_ADC1_DR REG32(STM32_ADC1_BASE + 0x40)
+#define STM32_ADC1_JSQR REG32(STM32_ADC1_BASE + 0x4C)
+#define STM32_ADC1_JDR1 REG32(STM32_ADC1_BASE + 0x80)
+#define STM32_ADC1_JDR2 REG32(STM32_ADC1_BASE + 0x84)
+#define STM32_ADC1_JDR3 REG32(STM32_ADC1_BASE + 0x88)
+#define STM32_ADC1_JDR4 REG32(STM32_ADC1_BASE + 0x8C)
+#define STM32_ADC1_CCR REG32(STM32_ADC1_BASE + 0x308)
 
 /* --- DMA --- */
 
@@ -692,39 +2011,29 @@ enum dma_channel {
 	STM32_DMAC_CH12 = 11,
 	STM32_DMAC_CH13 = 12,
 	STM32_DMAC_CH14 = 13,
+	STM32_DMAC_CH15 = 14,
 
 	/* Channel functions */
-	STM32_DMAC_ADC = STM32_DMAC_CH1,
 	STM32_DMAC_SPI1_RX = STM32_DMAC_CH2,
 	STM32_DMAC_SPI1_TX = STM32_DMAC_CH3,
-	STM32_DMAC_DAC_CH1 = STM32_DMAC_CH2,
-	STM32_DMAC_DAC_CH2 = STM32_DMAC_CH3,
-	STM32_DMAC_I2C2_TX = STM32_DMAC_CH4,
-	STM32_DMAC_I2C2_RX = STM32_DMAC_CH5,
-	STM32_DMAC_USART1_TX = STM32_DMAC_CH4,
-	STM32_DMAC_USART1_RX = STM32_DMAC_CH5,
-	STM32_DMAC_USART2_RX = STM32_DMAC_CH6,
-	STM32_DMAC_USART2_TX = STM32_DMAC_CH7,
-	STM32_DMAC_I2C1_TX = STM32_DMAC_CH6,
-	STM32_DMAC_I2C1_RX = STM32_DMAC_CH7,
-	STM32_DMAC_PMSE_ROW = STM32_DMAC_CH6,
-	STM32_DMAC_PMSE_COL = STM32_DMAC_CH7,
+	STM32_DMAC_USART1_TX = STM32_DMAC_CH14,
+	STM32_DMAC_USART1_RX = STM32_DMAC_CH15,
 	STM32_DMAC_SPI2_RX = STM32_DMAC_CH4,
 	STM32_DMAC_SPI2_TX = STM32_DMAC_CH5,
 	STM32_DMAC_SPI3_RX = STM32_DMAC_CH9,
 	STM32_DMAC_SPI3_TX = STM32_DMAC_CH10,
-	STM32_DMAC_COUNT = 14,
+	STM32_DMAC_COUNT = 15,
 };
 
 #define STM32_DMAC_PER_CTLR 8
 
 /* Registers for a single channel of the DMA controller */
 struct stm32_dma_chan {
-	uint32_t	ccr;		/* Control */
-	uint32_t	cndtr;		/* Number of data to transfer */
-	uint32_t	cpar;		/* Peripheral address */
-	uint32_t	cmar;		/* Memory address */
-	uint32_t	reserved;
+	uint32_t ccr; /* Control */
+	uint32_t cndtr; /* Number of data to transfer */
+	uint32_t cpar; /* Peripheral address */
+	uint32_t cmar; /* Memory address */
+	uint32_t reserved;
 };
 
 /* Always use stm32_dma_chan_t so volatile keyword is included! */
@@ -735,8 +2044,8 @@ typedef stm32_dma_chan_t dma_chan_t;
 
 /* Registers for the DMA controller */
 struct stm32_dma_regs {
-	uint32_t	isr;
-	uint32_t	ifcr;
+	uint32_t isr;
+	uint32_t ifcr;
 	stm32_dma_chan_t chan[STM32_DMAC_COUNT];
 };
 
@@ -745,209 +2054,67 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
 
 #define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE)
 
-
-#define STM32_DMA_CCR_CHANNEL(channel)		 (0)
+#define STM32_DMA_CCR_CHANNEL(channel) (0)
 #define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE)
 #define STM32_DMA_REGS(channel) \
 	((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_REGS : STM32_DMA2_REGS)
-#define STM32_DMA_CSELR(channel) \
-	REG32(((channel) < STM32_DMAC_PER_CTLR ? \
-			STM32_DMA1_BASE : STM32_DMA2_BASE)  + 0xA8)
+#define STM32_DMA_CSELR(channel)                                    \
+	REG32(((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_BASE :  \
+						 STM32_DMA2_BASE) + \
+	      0xA8)
 
 /* Bits for DMA controller regs (isr and ifcr) */
-#define STM32_DMA_CH_OFFSET(channel)   (4 * ((channel) % STM32_DMAC_PER_CTLR))
+#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR))
 #define STM32_DMA_ISR_MASK(channel, mask) \
 	((mask) << STM32_DMA_CH_OFFSET(channel))
-#define STM32_DMA_ISR_GIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(0))
-#define STM32_DMA_ISR_TCIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(1))
-#define STM32_DMA_ISR_HTIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(2))
-#define STM32_DMA_ISR_TEIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(3))
-#define STM32_DMA_ISR_ALL(channel)	STM32_DMA_ISR_MASK(channel, 0x0f)
-
-#define STM32_DMA_GIF                   BIT(0)
-#define STM32_DMA_TCIF                  BIT(1)
-#define STM32_DMA_HTIF                  BIT(2)
-#define STM32_DMA_TEIF                  BIT(3)
-#define STM32_DMA_ALL                   0xf
-
-#define STM32_DMA_GET_ISR(channel)      \
-	((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_ISR(channel, val) \
-	(STM32_DMA_REGS(channel)->isr = \
-	((STM32_DMA_REGS(channel)->isr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-#define STM32_DMA_GET_IFCR(channel)      \
-	((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_IFCR(channel, val) \
-	(STM32_DMA_REGS(channel)->ifcr = \
-	((STM32_DMA_REGS(channel)->ifcr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-
+#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0))
+#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1))
+#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2))
+#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3))
+#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f)
+
+#define STM32_DMA_GIF BIT(0)
+#define STM32_DMA_TCIF BIT(1)
+#define STM32_DMA_HTIF BIT(2)
+#define STM32_DMA_TEIF BIT(3)
+#define STM32_DMA_ALL 0xf
+
+#define STM32_DMA_GET_ISR(channel)                                        \
+	((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) & \
+	 STM32_DMA_ALL)
+#define STM32_DMA_SET_ISR(channel, val)                                \
+	(STM32_DMA_REGS(channel)->isr =                                \
+		 ((STM32_DMA_REGS(channel)->isr &                      \
+		   ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
+		  (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
+#define STM32_DMA_GET_IFCR(channel)                                        \
+	((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) & \
+	 STM32_DMA_ALL)
+#define STM32_DMA_SET_IFCR(channel, val)                               \
+	(STM32_DMA_REGS(channel)->ifcr =                               \
+		 ((STM32_DMA_REGS(channel)->ifcr &                     \
+		   ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
+		  (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
 
 /* Bits for DMA channel regs */
-#define STM32_DMA_CCR_EN		BIT(0)
-#define STM32_DMA_CCR_TCIE		BIT(1)
-#define STM32_DMA_CCR_HTIE		BIT(2)
-#define STM32_DMA_CCR_TEIE		BIT(3)
-#define STM32_DMA_CCR_DIR		BIT(4)
-#define STM32_DMA_CCR_CIRC		BIT(5)
-#define STM32_DMA_CCR_PINC		BIT(6)
-#define STM32_DMA_CCR_MINC		BIT(7)
-#define STM32_DMA_CCR_PSIZE_8_BIT	(0 << 8)
-#define STM32_DMA_CCR_PSIZE_16_BIT	(1 << 8)
-#define STM32_DMA_CCR_PSIZE_32_BIT	(2 << 8)
-#define STM32_DMA_CCR_MSIZE_8_BIT	(0 << 10)
-#define STM32_DMA_CCR_MSIZE_16_BIT	(1 << 10)
-#define STM32_DMA_CCR_MSIZE_32_BIT	(2 << 10)
-#define STM32_DMA_CCR_PL_LOW		(0 << 12)
-#define STM32_DMA_CCR_PL_MEDIUM		(1 << 12)
-#define STM32_DMA_CCR_PL_HIGH		(2 << 12)
-#define STM32_DMA_CCR_PL_VERY_HIGH	(3 << 12)
-#define STM32_DMA_CCR_MEM2MEM		BIT(14)
-
-
-/* --- CRC --- */
-#define STM32_CRC_DR                REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR32              REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR16              REG16(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR8               REG8(STM32_CRC_BASE + 0x0)
-
-#define STM32_CRC_IDR               REG32(STM32_CRC_BASE + 0x4)
-#define STM32_CRC_CR                REG32(STM32_CRC_BASE + 0x8)
-#define STM32_CRC_INIT              REG32(STM32_CRC_BASE + 0x10)
-#define STM32_CRC_POL               REG32(STM32_CRC_BASE + 0x14)
-
-#define STM32_CRC_CR_RESET          BIT(0)
-#define STM32_CRC_CR_POLYSIZE_32    (0 << 3)
-#define STM32_CRC_CR_POLYSIZE_16    (1 << 3)
-#define STM32_CRC_CR_POLYSIZE_8     (2 << 3)
-#define STM32_CRC_CR_POLYSIZE_7     (3 << 3)
-#define STM32_CRC_CR_REV_IN_BYTE    (1 << 5)
-#define STM32_CRC_CR_REV_IN_HWORD   (2 << 5)
-#define STM32_CRC_CR_REV_IN_WORD    (3 << 5)
-#define STM32_CRC_CR_REV_OUT        BIT(7)
-
-/* --- PMSE --- */
-#define STM32_PMSE_ARCR             REG32(STM32_PMSE_BASE + 0x0)
-#define STM32_PMSE_ACCR             REG32(STM32_PMSE_BASE + 0x4)
-#define STM32_PMSE_CR               REG32(STM32_PMSE_BASE + 0x8)
-#define STM32_PMSE_CRTDR            REG32(STM32_PMSE_BASE + 0x14)
-#define STM32_PMSE_IER              REG32(STM32_PMSE_BASE + 0x18)
-#define STM32_PMSE_SR               REG32(STM32_PMSE_BASE + 0x1c)
-#define STM32_PMSE_IFCR             REG32(STM32_PMSE_BASE + 0x20)
-#define STM32_PMSE_PxPMR(x)         REG32(STM32_PMSE_BASE + 0x2c + (x) * 4)
-#define STM32_PMSE_PAPMR            REG32(STM32_PMSE_BASE + 0x2c)
-#define STM32_PMSE_PBPMR            REG32(STM32_PMSE_BASE + 0x30)
-#define STM32_PMSE_PCPMR            REG32(STM32_PMSE_BASE + 0x34)
-#define STM32_PMSE_PDPMR            REG32(STM32_PMSE_BASE + 0x38)
-#define STM32_PMSE_PEPMR            REG32(STM32_PMSE_BASE + 0x3c)
-#define STM32_PMSE_PFPMR            REG32(STM32_PMSE_BASE + 0x40)
-#define STM32_PMSE_PGPMR            REG32(STM32_PMSE_BASE + 0x44)
-#define STM32_PMSE_PHPMR            REG32(STM32_PMSE_BASE + 0x48)
-#define STM32_PMSE_PIPMR            REG32(STM32_PMSE_BASE + 0x4c)
-#define STM32_PMSE_MRCR             REG32(STM32_PMSE_BASE + 0x100)
-#define STM32_PMSE_MCCR             REG32(STM32_PMSE_BASE + 0x104)
-
-/* --- USB --- */
-#define STM32_USB_EP(n)            REG16(STM32_USB_FS_BASE + (n) * 4)
-
-#define STM32_USB_CNTR             REG16(STM32_USB_FS_BASE + 0x40)
-
-#define STM32_USB_CNTR_FRES	    BIT(0)
-#define STM32_USB_CNTR_PDWN	    BIT(1)
-#define STM32_USB_CNTR_LP_MODE	    BIT(2)
-#define STM32_USB_CNTR_FSUSP	    BIT(3)
-#define STM32_USB_CNTR_RESUME	    BIT(4)
-#define STM32_USB_CNTR_L1RESUME	    BIT(5)
-#define STM32_USB_CNTR_L1REQM	    BIT(7)
-#define STM32_USB_CNTR_ESOFM	    BIT(8)
-#define STM32_USB_CNTR_SOFM	    BIT(9)
-#define STM32_USB_CNTR_RESETM	    BIT(10)
-#define STM32_USB_CNTR_SUSPM	    BIT(11)
-#define STM32_USB_CNTR_WKUPM	    BIT(12)
-#define STM32_USB_CNTR_ERRM	    BIT(13)
-#define STM32_USB_CNTR_PMAOVRM	    BIT(14)
-#define STM32_USB_CNTR_CTRM	    BIT(15)
-
-#define STM32_USB_ISTR             REG16(STM32_USB_FS_BASE + 0x44)
-
-#define STM32_USB_ISTR_EP_ID_MASK   (0x000f)
-#define STM32_USB_ISTR_DIR	    BIT(4)
-#define STM32_USB_ISTR_L1REQ	    BIT(7)
-#define STM32_USB_ISTR_ESOF	    BIT(8)
-#define STM32_USB_ISTR_SOF	    BIT(9)
-#define STM32_USB_ISTR_RESET	    BIT(10)
-#define STM32_USB_ISTR_SUSP	    BIT(11)
-#define STM32_USB_ISTR_WKUP	    BIT(12)
-#define STM32_USB_ISTR_ERR	    BIT(13)
-#define STM32_USB_ISTR_PMAOVR	    BIT(14)
-#define STM32_USB_ISTR_CTR	    BIT(15)
-
-#define STM32_USB_FNR              REG16(STM32_USB_FS_BASE + 0x48)
-
-#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14)
-#define STM32_USB_FNR_RXDP_RXDM_MASK  (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT)
-
-#define STM32_USB_DADDR            REG16(STM32_USB_FS_BASE + 0x4C)
-#define STM32_USB_BTABLE           REG16(STM32_USB_FS_BASE + 0x50)
-#define STM32_USB_LPMCSR           REG16(STM32_USB_FS_BASE + 0x54)
-#define STM32_USB_BCDR             REG16(STM32_USB_FS_BASE + 0x58)
-
-#define STM32_USB_BCDR_BCDEN	    BIT(0)
-#define STM32_USB_BCDR_DCDEN	    BIT(1)
-#define STM32_USB_BCDR_PDEN	    BIT(2)
-#define STM32_USB_BCDR_SDEN	    BIT(3)
-#define STM32_USB_BCDR_DCDET	    BIT(4)
-#define STM32_USB_BCDR_PDET	    BIT(5)
-#define STM32_USB_BCDR_SDET	    BIT(6)
-#define STM32_USB_BCDR_PS2DET	    BIT(7)
-
-#define EP_MASK     0x0F0F
-#define EP_TX_DTOG  0x0040
-#define EP_TX_MASK  0x0030
-#define EP_TX_VALID 0x0030
-#define EP_TX_NAK   0x0020
-#define EP_TX_STALL 0x0010
-#define EP_TX_DISAB 0x0000
-#define EP_RX_DTOG  0x4000
-#define EP_RX_MASK  0x3000
-#define EP_RX_VALID 0x3000
-#define EP_RX_NAK   0x2000
-#define EP_RX_STALL 0x1000
-#define EP_RX_DISAB 0x0000
-
-#define EP_STATUS_OUT 0x0100
-
-#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK)
-#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID)
-
-#define STM32_TOGGLE_EP(n, mask, val, flags) \
-	STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \
-			^ (val)) | (flags))
-
-/* --- TRNG --- */
-#define STM32_RNG_CR                REG32(STM32_RNG_BASE + 0x0)
-#define STM32_RNG_CR_RNGEN          BIT(2)
-#define STM32_RNG_CR_IE             BIT(3)
-#define STM32_RNG_CR_CED            BIT(5)
-#define STM32_RNG_SR                REG32(STM32_RNG_BASE + 0x4)
-#define STM32_RNG_SR_DRDY           BIT(0)
-#define STM32_RNG_DR                REG32(STM32_RNG_BASE + 0x8)
-
-/* --- AXI interconnect --- */
-
-/* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */
-#define STM32_AXI_TARG_FN_MOD(x)    REG32(STM32_GPV_BASE + 0x1108 + \
-					  0x1000 * (x))
-#define  WRITE_ISS_OVERRIDE         BIT(1)
-#define  READ_ISS_OVERRIDE          BIT(0)
-
-/* --- MISC --- */
-#define STM32_UNIQUE_ID_ADDRESS     REG32_ADDR(STM32_UNIQUE_ID_BASE)
-#define STM32_UNIQUE_ID_LENGTH      (3 * 4)
+#define STM32_DMA_CCR_EN BIT(0)
+#define STM32_DMA_CCR_TCIE BIT(1)
+#define STM32_DMA_CCR_HTIE BIT(2)
+#define STM32_DMA_CCR_TEIE BIT(3)
+#define STM32_DMA_CCR_DIR BIT(4)
+#define STM32_DMA_CCR_CIRC BIT(5)
+#define STM32_DMA_CCR_PINC BIT(6)
+#define STM32_DMA_CCR_MINC BIT(7)
+#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8)
+#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8)
+#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8)
+#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10)
+#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10)
+#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10)
+#define STM32_DMA_CCR_PL_LOW (0 << 12)
+#define STM32_DMA_CCR_PL_MEDIUM (1 << 12)
+#define STM32_DMA_CCR_PL_HIGH (2 << 12)
+#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12)
+#define STM32_DMA_CCR_MEM2MEM BIT(14)
 
 #endif /* !__ASSEMBLER__ */
diff --git a/chip/stm32/registers-stm32l5.h b/chip/stm32/registers-stm32l5.h
new file mode 100644
index 0000000000..f83802cf5f
--- /dev/null
+++ b/chip/stm32/registers-stm32l5.h
@@ -0,0 +1,2782 @@
+/* Copyright 2019 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ * @brief Register map for the STM32L5 family of chips
+ *
+ * This header file should not be included directly.
+ * Please include registers.h instead.
+ *
+ * Known Chip Variants
+ * - STM32L552
+ */
+
+#ifndef __CROS_EC_REGISTERS_H
+#error "This header file should not be included directly."
+#endif
+
+/******  STM32 specific Interrupt Numbers ********/
+#define STM32_IRQ_WWDG 0
+#define STM32_IRQ_PVD 1
+#define STM32_IRQ_RTC_ALARM 2
+#define STM32_IRQ_FLASH 6
+#define STM32_IRQ_FLASH_S 7
+#define STM32_IRQ_RCC 9
+#define STM32_IRQ_RCC_S 10
+#define STM32_IRQ_EXTI0 11
+#define STM32_IRQ_EXTI1 12
+#define STM32_IRQ_EXTI2 13
+#define STM32_IRQ_EXTI3 14
+#define STM32_IRQ_EXTI4 15
+#define STM32_IRQ_EXTI5 16
+#define STM32_IRQ_EXTI6 17
+#define STM32_IRQ_EXTI7 18
+#define STM32_IRQ_EXTI8 19
+#define STM32_IRQ_EXTI9 20
+#define STM32_IRQ_EXTI10 21
+#define STM32_IRQ_EXTI11 22
+#define STM32_IRQ_EXTI12 23
+#define STM32_IRQ_EXTI13 24
+#define STM32_IRQ_EXTI14 25
+#define STM32_IRQ_EXTI15 26
+#define STM32_IRQ_DMAMUX_OVR 27
+#define STM32_IRQ_DMAMUX_OVR_S 28
+#define STM32_IRQ_DMA_CHANNEL_1 29
+#define STM32_IRQ_DMA_CHANNEL_2 30
+#define STM32_IRQ_DMA_CHANNEL_3 31
+#define STM32_IRQ_DMA_CHANNEL_4 32
+#define STM32_IRQ_DMA_CHANNEL_5 33
+#define STM32_IRQ_DMA_CHANNEL_6 34
+#define STM32_IRQ_DMA_CHANNEL_7 35
+#define STM32_IRQ_DMA_CHANNEL_8 36
+#define STM32_IRQ_ADC1 37
+#define STM32_IRQ_TIM1_BRK 41
+#define STM32_IRQ_TIM1_UP 42
+#define STM32_IRQ_TIM1_TRG_COM 43
+#define STM32_IRQ_TIM1_CC 44
+#define STM32_IRQ_TIM2 45
+#define STM32_IRQ_TIM3 46
+#define STM32_IRQ_TIM4 47
+#define STM32_IRQ_TIM5 48
+#define STM32_IRQ_TIM6 49
+#define STM32_IRQ_TIM7 50
+#define STM32_IRQ_TIM8_BRK 51
+#define STM32_IRQ_TIM8_UP 52
+#define STM32_IRQ_TIM8_TRG_COM 53
+#define STM32_IRQ_TIM8_CC 54
+#define STM32_IRQ_I2C1_EV 55
+#define STM32_IRQ_I2C1_ER 56
+#define STM32_IRQ_I2C2_EV 57
+#define STM32_IRQ_I2C2_ER 58
+#define STM32_IRQ_SPI1 59
+#define STM32_IRQ_SPI2 60
+#define STM32_IRQ_USART1 61
+#define STM32_IRQ_USART2 62
+#define STM32_IRQ_USART3 63
+#define STM32_IRQ_USART4 64
+#define STM32_IRQ_USART5 65
+#define STM32_IRQ_LPUART1 66
+#define STM32_IRQ_LPTIM1 67
+#define STM32_IRQ_LPTIM2 68
+#define STM32_IRQ_TIM15 69
+#define STM32_IRQ_TIM16 70
+#define STM32_IRQ_TIM17 71
+#define STM32_IRQ_COMP 72
+#define STM32_IRQ_USB_FS 73
+#define STM32_IRQ_CRS 74
+#define STM32_IRQ_FMC 75
+#define STM32_IRQ_DMA2_CHANNEL1 80
+#define STM32_IRQ_DMA2_CHANNEL2 81
+#define STM32_IRQ_DMA2_CHANNEL3 82
+#define STM32_IRQ_DMA2_CHANNEL4 83
+#define STM32_IRQ_DMA2_CHANNEL5 84
+#define STM32_IRQ_DMA2_CHANNEL6 85
+#define STM32_IRQ_DMA2_CHANNEL7 86
+#define STM32_IRQ_DMA2_CHANNEL8 87
+
+/* To simplify code generation, define DMA channel 9..16 */
+#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1
+#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2
+#define STM32_IRQ_DMA_CHANNEL_11 STM32_IRQ_DMA2_CHANNEL3
+#define STM32_IRQ_DMA_CHANNEL_12 STM32_IRQ_DMA2_CHANNEL4
+#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL5
+#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL6
+#define STM32_IRQ_DMA_CHANNEL_15 STM32_IRQ_DMA2_CHANNEL7
+#define STM32_IRQ_DMA_CHANNEL_16 STM32_IRQ_DMA2_CHANNEL8
+
+/* aliases for easier code sharing */
+#define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV
+#define STM32_IRQ_I2C2 STM32_IRQ_I2C2_EV
+#define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV
+#define STM32_IRQ_USB_LP STM32_IRQ_USB_FS
+
+#define PERIPH_BASE 0x40000000UL
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x02000000UL)
+#define AHB3PERIPH_BASE (PERIPH_BASE + 0x04000000UL)
+
+/*!< APB1 peripherals */
+#define STM32_TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
+#define STM32_TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
+#define STM32_TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
+#define STM32_TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
+#define STM32_TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
+#define STM32_TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
+#define STM32_RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
+#define STM32_WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
+#define STM32_IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
+#define STM32_TAMP_BASE (APB1PERIPH_BASE + 0x3400UL)
+#define STM32_SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
+#define STM32_SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
+#define STM32_USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
+#define STM32_USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
+#define STM32_USART4_BASE (APB1PERIPH_BASE + 0x4c00UL)
+#define STM32_USART5_BASE (APB1PERIPH_BASE + 0x5000UL)
+#define STM32_I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
+#define STM32_I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
+#define STM32_I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)
+#define STM32_CRS_BASE (APB1PERIPH_BASE + 0x6000UL)
+#define STM32_PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
+#define STM32_DAC_BASE (APB1PERIPH_BASE + 0x7400UL)
+#define STM32_DAC1_BASE (APB1PERIPH_BASE + 0x7400UL)
+#define STM32_OPAMP_BASE (APB1PERIPH_BASE + 0x7800UL)
+#define STM32_LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL)
+#define STM32_LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL)
+#define STM32_I2C4_BASE (APB1PERIPH_BASE + 0x8400UL)
+#define STM32_LPTIM2_BASE (APB1PERIPH_BASE + 0x9400UL)
+#define STM32_LPTIM3_BASE (APB1PERIPH_BASE + 0x9800UL)
+#define STM32_FDCAN_RAM_BASE (APB1PERIPH_BASE + 0xA400UL)
+#define STM32_CAN_RAM_BASE (APB1PERIPH_BASE + 0xAC00UL)
+#define STM32_USB_FS_BASE (APB1PERIPH_BASE + 0xD400UL)
+#define STM32_USB_CAN_SRAM_BASE (APB1PERIPH_BASE + 0xD800UL)
+#define STM32_UCPD1_BASE (APB1PERIPH_BASE + 0xDC00UL)
+
+/*!< APB2 peripherals */
+#define STM32_SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL)
+#define STM32_EXTI_BASE (AHB1PERIPH_BASE + 0xf400UL)
+#define STM32_TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL)
+#define STM32_SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
+#define STM32_TIM8_BASE (APB2PERIPH_BASE + 0x3400UL)
+#define STM32_USART1_BASE (APB2PERIPH_BASE + 0x3800UL)
+#define STM32_TIM15_BASE (APB2PERIPH_BASE + 0x4000UL)
+#define STM32_TIM16_BASE (APB2PERIPH_BASE + 0x4400UL)
+#define STM32_TIM17_BASE (APB2PERIPH_BASE + 0x4800UL)
+
+/*!< AHB1 peripherals */
+#define STM32_DMA1_BASE (AHB1PERIPH_BASE + 0x0000UL)
+#define STM32_DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL)
+#define STM32_DMAMUX_BASE (AHB1PERIPH_BASE + 0x0800UL)
+#define STM32_RCC_BASE (AHB1PERIPH_BASE + 0x1000UL)
+#define STM32_FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL)
+#define STM32_CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
+#define STM32_DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL)
+#define STM32_DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL)
+#define STM32_DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL)
+#define STM32_DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL)
+#define STM32_DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL)
+#define STM32_DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL)
+#define STM32_DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL)
+#define STM32_DMA1_CSELR_BASE (DMA1_BASE + 0x00A8UL)
+#define STM32_DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL)
+#define STM32_DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL)
+#define STM32_DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL)
+#define STM32_DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL)
+#define STM32_DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL)
+#define STM32_DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL)
+#define STM32_DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL)
+#define STM32_DMA2_CSELR_BASE (DMA2_BASE + 0x00A8UL)
+
+/*!< AHB2 peripherals */
+#define STM32_GPIOA_BASE (AHB2PERIPH_BASE + 0x20000UL)
+#define STM32_GPIOB_BASE (AHB2PERIPH_BASE + 0x20400UL)
+#define STM32_GPIOC_BASE (AHB2PERIPH_BASE + 0x20800UL)
+#define STM32_GPIOD_BASE (AHB2PERIPH_BASE + 0x20C00UL)
+#define STM32_GPIOE_BASE (AHB2PERIPH_BASE + 0x21000UL)
+#define STM32_GPIOF_BASE (AHB2PERIPH_BASE + 0x21400UL)
+#define STM32_GPIOG_BASE (AHB2PERIPH_BASE + 0x21800UL)
+#define STM32_GPIOH_BASE (AHB2PERIPH_BASE + 0x21C00UL)
+#define STM32_ADC1_BASE (AHB2PERIPH_BASE + 0x28000UL)
+#define STM32_RNG_BASE (AHB2PERIPH_BASE + 0xC4000UL)
+
+/*!< AHB3 peripherals */
+#define STM32_OCTOSPI_BASE (AHB3PERIPH_BASE + 0x21000UL)
+
+/* Debug MCU registers base address */
+#define STM32_PACKAGE_BASE 0x0BFA0500UL
+#define STM32_UID_BASE 0x0BFA0590UL
+#define STM32_FLASHSIZE_BASE 0x0BFA05E0UL
+
+#define STM32_FLASH_REGS_BASE STM32_FLASH_R_BASE
+#define STM32_UNIQUE_ID_BASE STM32_UID_BASE
+
+#ifndef __ASSEMBLER__
+
+/* Register definitions */
+
+/* --- USART --- */
+#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00)
+#define STM32_USART_CR1_UE BIT(0)
+#define STM32_USART_CR1_UESM BIT(1)
+#define STM32_USART_CR1_RE BIT(2)
+#define STM32_USART_CR1_TE BIT(3)
+#define STM32_USART_CR1_RXNEIE BIT(5)
+#define STM32_USART_CR1_TCIE BIT(6)
+#define STM32_USART_CR1_TXEIE BIT(7)
+#define STM32_USART_CR1_PS BIT(9)
+#define STM32_USART_CR1_PCE BIT(10)
+#define STM32_USART_CR1_M BIT(12)
+#define STM32_USART_CR1_OVER8 BIT(15)
+
+#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04)
+#define STM32_USART_CR2_SWAP BIT(15)
+
+#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08)
+#define STM32_USART_CR3_EIE BIT(0)
+#define STM32_USART_CR3_DMAR BIT(6)
+#define STM32_USART_CR3_DMAT BIT(7)
+#define STM32_USART_CR3_ONEBIT BIT(11)
+#define STM32_USART_CR3_OVRDIS BIT(12)
+#define STM32_USART_CR3_WUS_START_BIT (2 << 20)
+#define STM32_USART_CR3_WUFIE BIT(22)
+
+#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C)
+#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10)
+#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14)
+#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18)
+#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C)
+#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20)
+#define STM32_USART_ICR_ORECF BIT(3)
+#define STM32_USART_ICR_TCCF BIT(6)
+#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24)
+#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28)
+#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C)
+/* register alias */
+#define STM32_USART_SR(base) STM32_USART_ISR(base)
+#define STM32_USART_SR_ORE BIT(3)
+#define STM32_USART_SR_RXNE BIT(5)
+#define STM32_USART_SR_TC BIT(6)
+#define STM32_USART_SR_TXE BIT(7)
+
+/* --- GPIO --- */
+#define STM32_GPIO_MODER(b) REG32((b) + 0x00)
+#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04)
+#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08)
+#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C)
+#define STM32_GPIO_IDR(b) REG16((b) + 0x10)
+#define STM32_GPIO_ODR(b) REG16((b) + 0x14)
+#define STM32_GPIO_BSRR(b) REG32((b) + 0x18)
+#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C)
+#define STM32_GPIO_AFRL(b) REG32((b) + 0x20)
+#define STM32_GPIO_AFRH(b) REG32((b) + 0x24)
+#define STM32_GPIO_BRR(b) REG32((b) + 0x28)
+#define STM32_GPIO_ASCR(b) REG32((b) + 0x2C) /* only for stm32l4x6 */
+
+#define GPIO_ALT_F0 0x0
+#define GPIO_ALT_F1 0x1
+#define GPIO_ALT_F2 0x2
+#define GPIO_ALT_F3 0x3
+#define GPIO_ALT_F4 0x4
+#define GPIO_ALT_F5 0x5
+#define GPIO_ALT_F6 0x6
+#define GPIO_ALT_F7 0x7
+#define GPIO_ALT_F8 0x8
+#define GPIO_ALT_F9 0x9
+#define GPIO_ALT_FA 0xA
+#define GPIO_ALT_FB 0xB
+#define GPIO_ALT_FC 0xC
+#define GPIO_ALT_FD 0xD
+#define GPIO_ALT_FE 0xE
+#define GPIO_ALT_FF 0xF
+
+/* --- I2C --- */
+#define STM32_I2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00))
+#define STM32_I2C_CR1_PE BIT(0)
+#define STM32_I2C_CR1_TXIE BIT(1)
+#define STM32_I2C_CR1_RXIE BIT(2)
+#define STM32_I2C_CR1_ADDRIE BIT(3)
+#define STM32_I2C_CR1_NACKIE BIT(4)
+#define STM32_I2C_CR1_STOPIE BIT(5)
+#define STM32_I2C_CR1_ERRIE BIT(7)
+#define STM32_I2C_CR1_WUPEN BIT(18)
+#define STM32_I2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04))
+#define STM32_I2C_CR2_RD_WRN BIT(10)
+#define STM32_I2C_CR2_START BIT(13)
+#define STM32_I2C_CR2_STOP BIT(14)
+#define STM32_I2C_CR2_NACK BIT(15)
+#define STM32_I2C_CR2_RELOAD BIT(24)
+#define STM32_I2C_CR2_AUTOEND BIT(25)
+#define STM32_I2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08))
+#define STM32_I2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C))
+#define STM32_I2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10))
+#define STM32_I2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14))
+#define STM32_I2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18))
+#define STM32_I2C_ISR_TXE BIT(0)
+#define STM32_I2C_ISR_TXIS BIT(1)
+#define STM32_I2C_ISR_RXNE BIT(2)
+#define STM32_I2C_ISR_ADDR BIT(3)
+#define STM32_I2C_ISR_NACK BIT(4)
+#define STM32_I2C_ISR_STOP BIT(5)
+#define STM32_I2C_ISR_TC BIT(6)
+#define STM32_I2C_ISR_TCR BIT(7)
+#define STM32_I2C_ISR_BERR BIT(8)
+#define STM32_I2C_ISR_ARLO BIT(9)
+#define STM32_I2C_ISR_OVR BIT(10)
+#define STM32_I2C_ISR_PECERR BIT(11)
+#define STM32_I2C_ISR_TIMEOUT BIT(12)
+#define STM32_I2C_ISR_ALERT BIT(13)
+#define STM32_I2C_ISR_BUSY BIT(15)
+#define STM32_I2C_ISR_DIR BIT(16)
+#define STM32_I2C_ISR_ADDCODE(isr) (((isr) >> 16) & 0xfe)
+#define STM32_I2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C))
+#define STM32_I2C_ICR_ADDRCF BIT(3)
+#define STM32_I2C_ICR_NACKCF BIT(4)
+#define STM32_I2C_ICR_STOPCF BIT(5)
+#define STM32_I2C_ICR_BERRCF BIT(8)
+#define STM32_I2C_ICR_ARLOCF BIT(9)
+#define STM32_I2C_ICR_OVRCF BIT(10)
+#define STM32_I2C_ICR_TIMEOUTCF BIT(12)
+#define STM32_I2C_ICR_ALL 0x3F38
+#define STM32_I2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20))
+#define STM32_I2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24))
+#define STM32_I2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28))
+
+/* --- Power / Reset / Clocks --- */
+#define STM32_PWR_CR1 REG32(STM32_PWR_BASE + 0x00)
+#define STM32_PWR_CR2 REG32(STM32_PWR_BASE + 0x04)
+#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x10)
+#define STM32_PWR_SCR REG32(STM32_PWR_BASE + 0x18)
+
+#define PWR_CR1_LPMS_POS 0U
+#define PWR_CR1_LPMS_MSK (0x7UL << PWR_CR1_LPMS_POS)
+#define PWR_CR1_LPMS PWR_CR1_LPMS_MSK
+#define PWR_CR1_LPMS_STOP0 (0x00000000UL)
+#define PWR_CR1_LPMS_STOP1_POS 0U
+#define PWR_CR1_LPMS_STOP1_MSK (0x1UL << PWR_CR1_LPMS_STOP1_POS)
+#define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_MSK
+#define PWR_CR1_LPMS_STOP2_POS 1U
+#define PWR_CR1_LPMS_STOP2_MSK (0x1UL << PWR_CR1_LPMS_STOP2_POS)
+#define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_MSK
+#define PWR_CR1_LPMS_STANDBY_POS 0U
+#define PWR_CR1_LPMS_STANDBY_MSK (0x3UL << PWR_CR1_LPMS_STANDBY_POS)
+#define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_MSK
+#define PWR_CR1_LPMS_SHUTDOWN_POS 2U
+#define PWR_CR1_LPMS_SHUTDOWN_MSK (0x1UL << PWR_CR1_LPMS_SHUTDOWN_POS)
+#define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_MSK
+#define PWR_CR1_VOS_POS 9U
+#define PWR_CR1_VOS_MSK (0x3UL << PWR_CR1_VOS_POS)
+#define PWR_CR1_VOS PWR_CR1_VOS_MSK
+#define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_POS)
+#define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_POS)
+
+#define STM32_PWR_CR2_IOSV_POS 9U
+#define STM32_PWR_CR2_IOSV_MASK BIT(STM32_PWR_CR2_IOSV_POS)
+#define STM32_PWR_CR2_IOSV STM32_PWR_CR2_IOSV_MASK
+#define STM32_PWR_CR2_USV_POS 10U
+#define STM32_PWR_CR2_USV_MASK BIT(STM32_PWR_CR2_USV_POS)
+#define STM32_PWR_CR2_USV STM32_PWR_CR2_USV_MASK
+
+/* --- Macro usage in ec code --- */
+#define STM32_RCC_AHB2ENR_GPIOMASK                               \
+	(STM32_RCC_AHB2ENR_GPIOAEN | STM32_RCC_AHB2ENR_GPIOBEN | \
+	 STM32_RCC_AHB2ENR_GPIOCEN | STM32_RCC_AHB2ENR_GPIODEN | \
+	 STM32_RCC_AHB2ENR_GPIOEEN | STM32_RCC_AHB2ENR_GPIOFEN | \
+	 STM32_RCC_AHB2ENR_GPIOGEN | STM32_RCC_AHB2ENR_GPIOHEN)
+#define STM32_RCC_ICSCR_MSIRANGE(n) ((n) << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_ICSCR_MSIRANGE_1MHZ STM32_RCC_ICSCR_MSIRANGE(4)
+#define STM32_RCC_ICSCR_MSIRANGE_2MHZ STM32_RCC_ICSCR_MSIRANGE(5)
+#define STM32_RCC_ICSCR_MSIRANGE_MASK STM32_RCC_CR_MSIRANGE_MSK
+#define STM32_RCC_SYSCFGEN STM32_RCC_APB2ENR_SYSCFGEN
+
+#define STM32_RCC_PB2_TIM1 STM32_RCC_APB2ENR_TIM1EN
+#define STM32_RCC_PB2_TIM15 STM32_RCC_APB2ENR_TIM15EN
+#define STM32_RCC_PB2_TIM16 STM32_RCC_APB2ENR_TIM16EN
+#ifndef CHIP_VARIANT_STM32L431X
+#define STM32_RCC_PB2_TIM8 BIT(13)
+#endif
+#define STM32_RCC_PWREN STM32_RCC_APB1ENR1_PWREN
+
+#define STM32_RCC_AHB2ENR_GPIO_PORTA BIT(0)
+#define STM32_RCC_AHB2ENR_GPIO_PORTB BIT(1)
+#define STM32_RCC_AHB2ENR_GPIO_PORTC BIT(2)
+#define STM32_RCC_AHB2ENR_GPIO_PORTD BIT(3)
+#define STM32_RCC_AHB2ENR_GPIO_PORTE BIT(4)
+#define STM32_RCC_AHB2ENR_GPIO_PORTH BIT(7)
+#define STM32_RCC_CCIPR_USART1SEL_SHIFT (0)
+#define STM32_RCC_CCIPR_USART1SEL_MASK (3 << STM32_RCC_CCIPR_USART1SEL_SHIFT)
+#define STM32_RCC_CCIPR_USART2SEL_SHIFT (2)
+#define STM32_RCC_CCIPR_USART2SEL_MASK (3 << STM32_RCC_CCIPR_USART2SEL_SHIFT)
+#define STM32_RCC_CCIPR_USART3SEL_SHIFT (4)
+#define STM32_RCC_CCIPR_USART3SEL_MASK (3 << STM32_RCC_CCIPR_USART3SEL_SHIFT)
+#define STM32_RCC_CCIPR_UART4SEL_SHIFT (6)
+#define STM32_RCC_CCIPR_UART4SEL_MASK (3 << STM32_RCC_CCIPR_UART4SEL_SHIFT)
+#define STM32_RCC_CCIPR_UART5SEL_SHIFT (8)
+#define STM32_RCC_CCIPR_UART5SEL_MASK (3 << STM32_RCC_CCIPR_UART5SEL_SHIFT)
+#define STM32_RCC_CCIPR_LPUART1SEL_SHIFT (10)
+#define STM32_RCC_CCIPR_LPUART1SEL_MASK (3 << STM32_RCC_CCIPR_LPUART1SEL_SHIFT)
+#define STM32_RCC_CCIPR_I2C1SEL_SHIFT (12)
+#define STM32_RCC_CCIPR_I2C1SEL_MASK (3 << STM32_RCC_CCIPR_I2C1SEL_SHIFT)
+#define STM32_RCC_CCIPR_I2C2SEL_SHIFT (14)
+#define STM32_RCC_CCIPR_I2C2SEL_MASK (3 << STM32_RCC_CCIPR_I2C2SEL_SHIFT)
+#define STM32_RCC_CCIPR_I2C3SEL_SHIFT (16)
+#define STM32_RCC_CCIPR_I2C3SEL_MASK (3 << STM32_RCC_CCIPR_I2C3SEL_SHIFT)
+#define STM32_RCC_CCIPR_LPTIM1SEL_SHIFT (18)
+#define STM32_RCC_CCIPR_LPTIM1SEL_MASK (3 << STM32_RCC_CCIPR_LPTIM1SEL_SHIFT)
+#define STM32_RCC_CCIPR_LPTIM2SEL_SHIFT (20)
+#define STM32_RCC_CCIPR_LPTIM2SEL_MASK (3 << STM32_RCC_CCIPR_LPTIM2SEL_SHIFT)
+#define STM32_RCC_CCIPR_SAI1SEL_SHIFT (22)
+#define STM32_RCC_CCIPR_SAI1SEL_MASK (3 << STM32_RCC_CCIPR_SAI1SEL_SHIFT)
+#define STM32_RCC_CCIPR_SAI2SEL_SHIFT (24)
+#define STM32_RCC_CCIPR_SAI2SEL_MASK (3 << STM32_RCC_CCIPR_SAI2SEL_SHIFT)
+#define STM32_RCC_CCIPR_CLK48SEL_SHIFT (26)
+#define STM32_RCC_CCIPR_CLK48SEL_MASK (3 << STM32_RCC_CCIPR_CLK48SEL_SHIFT)
+#define STM32_RCC_CCIPR_ADCSEL_SHIFT (28)
+#define STM32_RCC_CCIPR_ADCSEL_MASK (3 << STM32_RCC_CCIPR_ADCSEL_SHIFT)
+#define STM32_RCC_CCIPR_SWPMI1SEL_SHIFT (30)
+#define STM32_RCC_CCIPR_SWPMI1SEL_MASK BIT(STM32_RCC_CCIPR_SWPMI1SEL_SHIFT)
+#define STM32_RCC_CCIPR_DFSDM1SEL_SHIFT (31)
+#define STM32_RCC_CCIPR_DFSDM1SEL_MASK BIT(STM32_RCC_CCIPR_DFSDM1SEL_SHIFT)
+/* Possible clock sources for each peripheral */
+#define STM32_RCC_CCIPR_UART_PCLK 0
+#define STM32_RCC_CCIPR_UART_SYSCLK 1
+#define STM32_RCC_CCIPR_UART_HSI16 2
+#define STM32_RCC_CCIPR_UART_LSE 3
+
+#define STM32_RCC_CCIPR_I2C_PCLK 0
+#define STM32_RCC_CCIPR_I2C_SYSCLK 1
+#define STM32_RCC_CCIPR_I2C_HSI16 2
+
+#define STM32_RCC_CCIPR_LPTIM_PCLK 0
+#define STM32_RCC_CCIPR_LPTIM_LSI 1
+#define STM32_RCC_CCIPR_LPTIM_HSI16 2
+#define STM32_RCC_CCIPR_LPTIM_LSE 3
+
+#define STM32_RCC_CCIPR_SAI_PLLSAI1CLK 0
+#define STM32_RCC_CCIPR_SAI_PLLSAI2CLK 1
+#define STM32_RCC_CCIPR_SAI_PLLSAI3CLK 2
+#define STM32_RCC_CCIPR_SAI_EXTCLK 3
+
+#define STM32_RCC_CCIPR_CLK48_NONE 0
+#define STM32_RCC_CCIPR_CLK48_PLL48M2CLK 1
+#define STM32_RCC_CCIPR_CLK48_PLL48M1CLK 2
+#define STM32_RCC_CCIPR_CLK48_MSI 3
+
+#define STM32_RCC_CCIPR_ADC_NONE 0
+#define STM32_RCC_CCIPR_ADC_PLLADC1CLK 1
+#define STM32_RCC_CCIPR_ADC_PLLADC2CLK 2
+#define STM32_RCC_CCIPR_ADC_SYSCLK 3
+
+#define STM32_RCC_CCIPR_SWPMI_PCLK 0
+#define STM32_RCC_CCIPR_SWPMI_HSI16 1
+
+#define STM32_RCC_CCIPR_DFSDM_PCLK 0
+#define STM32_RCC_CCIPR_DFSDM_SYSCLK 1
+
+#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00)
+#define STM32_RCC_ICSCR REG32(STM32_RCC_BASE + 0x04)
+#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08)
+#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x0C)
+#define STM32_RCC_PLLSAI1CFGR REG32(STM32_RCC_BASE + 0x10)
+#define STM32_RCC_RESERVED REG32(STM32_RCC_BASE + 0x14)
+#define STM32_RCC_CIER REG32(STM32_RCC_BASE + 0x18)
+#define STM32_RCC_CIFR REG32(STM32_RCC_BASE + 0x1C)
+#define STM32_RCC_CICR REG32(STM32_RCC_BASE + 0x20)
+#define STM32_RCC_RESERVED0 REG32(STM32_RCC_BASE + 0x24)
+#define STM32_RCC_AHB1RSTR REG32(STM32_RCC_BASE + 0x28)
+#define STM32_RCC_AHB2RSTR REG32(STM32_RCC_BASE + 0x2C)
+#define STM32_RCC_AHB3RSTR REG32(STM32_RCC_BASE + 0x30)
+#define STM32_RCC_RESERVED1 REG32(STM32_RCC_BASE + 0x34)
+#define STM32_RCC_APB1RSTR1 REG32(STM32_RCC_BASE + 0x38)
+#define STM32_RCC_APB1RSTR2 REG32(STM32_RCC_BASE + 0x3C)
+#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x40)
+#define STM32_RCC_RESERVED2 REG32(STM32_RCC_BASE + 0x44)
+#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x48)
+#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x4C)
+#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x50)
+#define STM32_RCC_RESERVED3 REG32(STM32_RCC_BASE + 0x54)
+#define STM32_RCC_APB1ENR1 REG32(STM32_RCC_BASE + 0x58)
+#define STM32_RCC_APB1ENR2 REG32(STM32_RCC_BASE + 0x5C)
+#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x60)
+#define STM32_RCC_RESERVED4 REG32(STM32_RCC_BASE + 0x64)
+#define STM32_RCC_AHB1SMENR REG32(STM32_RCC_BASE + 0x68)
+#define STM32_RCC_AHB2SMENR REG32(STM32_RCC_BASE + 0x6C)
+#define STM32_RCC_AHB3SMENR REG32(STM32_RCC_BASE + 0x70)
+#define STM32_RCC_RESERVED5 REG32(STM32_RCC_BASE + 0x74)
+#define STM32_RCC_APB1SMENR1 REG32(STM32_RCC_BASE + 0x78)
+#define STM32_RCC_APB1SMENR2 REG32(STM32_RCC_BASE + 0x7C)
+#define STM32_RCC_APB2SMENR REG32(STM32_RCC_BASE + 0x80)
+#define STM32_RCC_RESERVED6 REG32(STM32_RCC_BASE + 0x84)
+#define STM32_RCC_CCIPR1 REG32(STM32_RCC_BASE + 0x88)
+#define STM32_RCC_CCIPR STM32_RCC_CCIPR1
+#define STM32_RCC_RESERVED7 REG32(STM32_RCC_BASE + 0x8C)
+#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x90)
+#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x94)
+#define STM32_RCC_CRRCR REG32(STM32_RCC_BASE + 0x98)
+#define STM32_RCC_CCIPR2 REG32(STM32_RCC_BASE + 0x9C)
+#define STM32_CRS_CR REG32(STM32_CRS_BASE + 0x00)
+#define STM32_CRS_CFGR REG32(STM32_CRS_BASE + 0x04)
+#define STM32_CRS_ISR REG32(STM32_CRS_BASE + 0x08)
+#define STM32_CRS_ICR REG32(STM32_CRS_BASE + 0x0C)
+
+#define STM32_RCC_PLLSAI1_SUPPORT
+#define STM32_RCC_PLLP_SUPPORT
+#define STM32_RCC_HSI48_SUPPORT
+#define STM32_RCC_PLLP_DIV_2_31_SUPPORT
+#define STM32_RCC_PLLSAI1P_DIV_2_31_SUPPORT
+
+#define STM32_RCC_APB1ENR STM32_RCC_APB1ENR1
+
+/********************  BIT DEFINITION FOR STM32_RCC_CR REGISTER  **************/
+#define STM32_RCC_CR_MSION_POS 0U
+#define STM32_RCC_CR_MSION_MSK (0x1UL << STM32_RCC_CR_MSION_POS)
+#define STM32_RCC_CR_MSION STM32_RCC_CR_MSION_MSK
+#define STM32_RCC_CR_MSIRDY_POS 1U
+#define STM32_RCC_CR_MSIRDY_MSK (0x1UL << STM32_RCC_CR_MSIRDY_POS)
+#define STM32_RCC_CR_MSIRDY STM32_RCC_CR_MSIRDY_MSK
+#define STM32_RCC_CR_MSIPLLEN_POS 2U
+#define STM32_RCC_CR_MSIPLLEN_MSK (0x1UL << STM32_RCC_CR_MSIPLLEN_POS)
+#define STM32_RCC_CR_MSIPLLEN STM32_RCC_CR_MSIPLLEN_MSK
+#define STM32_RCC_CR_MSIRGSEL_POS 3U
+#define STM32_RCC_CR_MSIRGSEL_MSK (0x1UL << STM32_RCC_CR_MSIRGSEL_POS)
+#define STM32_RCC_CR_MSIRGSEL STM32_RCC_CR_MSIRGSEL_MSK
+
+/*!< MSIRANGE CONFIGURATION : 12 FREQUENCY RANGES AVAILABLE */
+#define STM32_RCC_CR_MSIRANGE_POS 4U
+#define STM32_RCC_CR_MSIRANGE_MSK (0xFUL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE STM32_RCC_CR_MSIRANGE_MSK
+#define STM32_RCC_CR_MSIRANGE_0 (0x0UL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_1 (0x1UL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_2 (0x2UL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_3 (0x3UL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_4 (0x4UL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_5 (0x5UL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_6 (0x6UL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_7 (0x7UL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_8 (0x8UL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_9 (0x9UL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_10 (0xAUL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_11 (0xBUL << STM32_RCC_CR_MSIRANGE_POS)
+
+#define STM32_RCC_CR_HSION_POS 8U
+#define STM32_RCC_CR_HSION_MSK (0x1UL << STM32_RCC_CR_HSION_POS)
+#define STM32_RCC_CR_HSION STM32_RCC_CR_HSION_MSK
+#define STM32_RCC_CR_HSIKERON_POS 9U
+#define STM32_RCC_CR_HSIKERON_MSK (0x1UL << STM32_RCC_CR_HSIKERON_POS)
+#define STM32_RCC_CR_HSIKERON STM32_RCC_CR_HSIKERON_MSK
+#define STM32_RCC_CR_HSIRDY_POS 10U
+#define STM32_RCC_CR_HSIRDY_MSK (0x1UL << STM32_RCC_CR_HSIRDY_POS)
+#define STM32_RCC_CR_HSIRDY STM32_RCC_CR_HSIRDY_MSK
+#define STM32_RCC_CR_HSIASFS_POS 11U
+#define STM32_RCC_CR_HSIASFS_MSK (0x1UL << STM32_RCC_CR_HSIASFS_POS)
+#define STM32_RCC_CR_HSIASFS STM32_RCC_CR_HSIASFS_MSK
+
+#define STM32_RCC_CR_HSEON_POS 16U
+#define STM32_RCC_CR_HSEON_MSK (0x1UL << STM32_RCC_CR_HSEON_POS)
+#define STM32_RCC_CR_HSEON STM32_RCC_CR_HSEON_MSK
+#define STM32_RCC_CR_HSERDY_POS 17U
+#define STM32_RCC_CR_HSERDY_MSK (0x1UL << STM32_RCC_CR_HSERDY_POS)
+#define STM32_RCC_CR_HSERDY STM32_RCC_CR_HSERDY_MSK
+#define STM32_RCC_CR_HSEBYP_POS 18U
+#define STM32_RCC_CR_HSEBYP_MSK (0x1UL << STM32_RCC_CR_HSEBYP_POS)
+#define STM32_RCC_CR_HSEBYP STM32_RCC_CR_HSEBYP_MSK
+#define STM32_RCC_CR_CSSON_POS 19U
+#define STM32_RCC_CR_CSSON_MSK (0x1UL << STM32_RCC_CR_CSSON_POS)
+#define STM32_RCC_CR_CSSON STM32_RCC_CR_CSSON_MSK
+
+#define STM32_RCC_CR_PLLON_POS 24U
+#define STM32_RCC_CR_PLLON_MSK (0x1UL << STM32_RCC_CR_PLLON_POS)
+#define STM32_RCC_CR_PLLON STM32_RCC_CR_PLLON_MSK
+#define STM32_RCC_CR_PLLRDY_POS 25U
+#define STM32_RCC_CR_PLLRDY_MSK (0x1UL << STM32_RCC_CR_PLLRDY_POS)
+#define STM32_RCC_CR_PLLRDY STM32_RCC_CR_PLLRDY_MSK
+#define STM32_RCC_CR_PLLSAI1ON_POS 26U
+#define STM32_RCC_CR_PLLSAI1ON_MSK (0x1UL << STM32_RCC_CR_PLLSAI1ON_POS)
+#define STM32_RCC_CR_PLLSAI1ON STM32_RCC_CR_PLLSAI1ON_MSK
+#define STM32_RCC_CR_PLLSAI1RDY_POS 27U
+#define STM32_RCC_CR_PLLSAI1RDY_MSK (0x1UL << STM32_RCC_CR_PLLSAI1RDY_POS)
+#define STM32_RCC_CR_PLLSAI1RDY STM32_RCC_CR_PLLSAI1RDY_MSK
+
+/********************  BIT DEFINITION FOR STM32_RCC_ICSCR REGISTER  ***********/
+/*!< MSICAL CONFIGURATION */
+#define STM32_RCC_ICSCR_MSICAL_POS 0U
+#define STM32_RCC_ICSCR_MSICAL_MSK (0xFFUL << STM32_RCC_ICSCR_MSICAL_POS)
+#define STM32_RCC_ICSCR_MSICAL STM32_RCC_ICSCR_MSICAL_MSK
+#define STM32_RCC_ICSCR_MSICAL_0 (0x01UL << STM32_RCC_ICSCR_MSICAL_POS)
+#define STM32_RCC_ICSCR_MSICAL_1 (0x02UL << STM32_RCC_ICSCR_MSICAL_POS)
+#define STM32_RCC_ICSCR_MSICAL_2 (0x04UL << STM32_RCC_ICSCR_MSICAL_POS)
+#define STM32_RCC_ICSCR_MSICAL_3 (0x08UL << STM32_RCC_ICSCR_MSICAL_POS)
+#define STM32_RCC_ICSCR_MSICAL_4 (0x10UL << STM32_RCC_ICSCR_MSICAL_POS)
+#define STM32_RCC_ICSCR_MSICAL_5 (0x20UL << STM32_RCC_ICSCR_MSICAL_POS)
+#define STM32_RCC_ICSCR_MSICAL_6 (0x40UL << STM32_RCC_ICSCR_MSICAL_POS)
+#define STM32_RCC_ICSCR_MSICAL_7 (0x80UL << STM32_RCC_ICSCR_MSICAL_POS)
+
+/*!< MSITRIM CONFIGURATION */
+#define STM32_RCC_ICSCR_MSITRIM_POS 8U
+#define STM32_RCC_ICSCR_MSITRIM_MSK (0xFFUL << STM32_RCC_ICSCR_MSITRIM_POS)
+#define STM32_RCC_ICSCR_MSITRIM STM32_RCC_ICSCR_MSITRIM_MSK
+#define STM32_RCC_ICSCR_MSITRIM_0 (0x01UL << STM32_RCC_ICSCR_MSITRIM_POS)
+#define STM32_RCC_ICSCR_MSITRIM_1 (0x02UL << STM32_RCC_ICSCR_MSITRIM_POS)
+#define STM32_RCC_ICSCR_MSITRIM_2 (0x04UL << STM32_RCC_ICSCR_MSITRIM_POS)
+#define STM32_RCC_ICSCR_MSITRIM_3 (0x08UL << STM32_RCC_ICSCR_MSITRIM_POS)
+#define STM32_RCC_ICSCR_MSITRIM_4 (0x10UL << STM32_RCC_ICSCR_MSITRIM_POS)
+#define STM32_RCC_ICSCR_MSITRIM_5 (0x20UL << STM32_RCC_ICSCR_MSITRIM_POS)
+#define STM32_RCC_ICSCR_MSITRIM_6 (0x40UL << STM32_RCC_ICSCR_MSITRIM_POS)
+#define STM32_RCC_ICSCR_MSITRIM_7 (0x80UL << STM32_RCC_ICSCR_MSITRIM_POS)
+
+/*!< HSICAL CONFIGURATION */
+#define STM32_RCC_ICSCR_HSICAL_POS 16U
+#define STM32_RCC_ICSCR_HSICAL_MSK (0xFFUL << STM32_RCC_ICSCR_HSICAL_POS)
+#define STM32_RCC_ICSCR_HSICAL STM32_RCC_ICSCR_HSICAL_MSK
+#define STM32_RCC_ICSCR_HSICAL_0 (0x01UL << STM32_RCC_ICSCR_HSICAL_POS)
+#define STM32_RCC_ICSCR_HSICAL_1 (0x02UL << STM32_RCC_ICSCR_HSICAL_POS)
+#define STM32_RCC_ICSCR_HSICAL_2 (0x04UL << STM32_RCC_ICSCR_HSICAL_POS)
+#define STM32_RCC_ICSCR_HSICAL_3 (0x08UL << STM32_RCC_ICSCR_HSICAL_POS)
+#define STM32_RCC_ICSCR_HSICAL_4 (0x10UL << STM32_RCC_ICSCR_HSICAL_POS)
+#define STM32_RCC_ICSCR_HSICAL_5 (0x20UL << STM32_RCC_ICSCR_HSICAL_POS)
+#define STM32_RCC_ICSCR_HSICAL_6 (0x40UL << STM32_RCC_ICSCR_HSICAL_POS)
+#define STM32_RCC_ICSCR_HSICAL_7 (0x80UL << STM32_RCC_ICSCR_HSICAL_POS)
+
+/*!< HSITRIM CONFIGURATION */
+#define STM32_RCC_ICSCR_HSITRIM_POS 24U
+#define STM32_RCC_ICSCR_HSITRIM_MSK (0x1FUL << STM32_RCC_ICSCR_HSITRIM_POS)
+#define STM32_RCC_ICSCR_HSITRIM STM32_RCC_ICSCR_HSITRIM_MSK
+#define STM32_RCC_ICSCR_HSITRIM_0 (0x01UL << STM32_RCC_ICSCR_HSITRIM_POS)
+#define STM32_RCC_ICSCR_HSITRIM_1 (0x02UL << STM32_RCC_ICSCR_HSITRIM_POS)
+#define STM32_RCC_ICSCR_HSITRIM_2 (0x04UL << STM32_RCC_ICSCR_HSITRIM_POS)
+#define STM32_RCC_ICSCR_HSITRIM_3 (0x08UL << STM32_RCC_ICSCR_HSITRIM_POS)
+#define STM32_RCC_ICSCR_HSITRIM_4 (0x10UL << STM32_RCC_ICSCR_HSITRIM_POS)
+
+/****************  BIT DEFINITION FOR STM32_RCC_CFGR REGISTER  **************/
+/*!< SW CONFIGURATION */
+#define STM32_RCC_CFGR_SW_POS 0U
+#define STM32_RCC_CFGR_SW_MSK (0x3UL << STM32_RCC_CFGR_SW_POS)
+#define STM32_RCC_CFGR_SW STM32_RCC_CFGR_SW_MSK
+#define STM32_RCC_CFGR_SW_0 (0x1UL << STM32_RCC_CFGR_SW_POS)
+#define STM32_RCC_CFGR_SW_1 (0x2UL << STM32_RCC_CFGR_SW_POS)
+
+#define STM32_RCC_CFGR_SW_MSI (0x00000000UL)
+#define STM32_RCC_CFGR_SW_HSI (0x00000001UL)
+#define STM32_RCC_CFGR_SW_HSE (0x00000002UL)
+#define STM32_RCC_CFGR_SW_PLL (0x00000003UL)
+
+/*!< SWS CONFIGURATION */
+#define STM32_RCC_CFGR_SWS_POS 2U
+#define STM32_RCC_CFGR_SWS_MSK (0x3UL << STM32_RCC_CFGR_SWS_POS)
+#define STM32_RCC_CFGR_SWS STM32_RCC_CFGR_SWS_MSK
+#define STM32_RCC_CFGR_SWS_0 (0x1UL << STM32_RCC_CFGR_SWS_POS)
+#define STM32_RCC_CFGR_SWS_1 (0x2UL << STM32_RCC_CFGR_SWS_POS)
+
+#define STM32_RCC_CFGR_SWS_MSI (0x00000000UL)
+#define STM32_RCC_CFGR_SWS_HSI (0x00000004UL)
+#define STM32_RCC_CFGR_SWS_HSE (0x00000008UL)
+#define STM32_RCC_CFGR_SWS_PLL (0x0000000CUL)
+
+/*!< HPRE CONFIGURATION */
+#define STM32_RCC_CFGR_HPRE_POS 4U
+#define STM32_RCC_CFGR_HPRE_MSK (0xFUL << STM32_RCC_CFGR_HPRE_POS)
+#define STM32_RCC_CFGR_HPRE STM32_RCC_CFGR_HPRE_MSK
+#define STM32_RCC_CFGR_HPRE_0 (0x1UL << STM32_RCC_CFGR_HPRE_POS)
+#define STM32_RCC_CFGR_HPRE_1 (0x2UL << STM32_RCC_CFGR_HPRE_POS)
+#define STM32_RCC_CFGR_HPRE_2 (0x4UL << STM32_RCC_CFGR_HPRE_POS)
+#define STM32_RCC_CFGR_HPRE_3 (0x8UL << STM32_RCC_CFGR_HPRE_POS)
+
+#define STM32_RCC_CFGR_HPRE_DIV1 (0x00000000UL)
+#define STM32_RCC_CFGR_HPRE_DIV2 (0x00000080UL)
+#define STM32_RCC_CFGR_HPRE_DIV4 (0x00000090UL)
+#define STM32_RCC_CFGR_HPRE_DIV8 (0x000000A0UL)
+#define STM32_RCC_CFGR_HPRE_DIV16 (0x000000B0UL)
+#define STM32_RCC_CFGR_HPRE_DIV64 (0x000000C0UL)
+#define STM32_RCC_CFGR_HPRE_DIV128 (0x000000D0UL)
+#define STM32_RCC_CFGR_HPRE_DIV256 (0x000000E0UL)
+#define STM32_RCC_CFGR_HPRE_DIV512 (0x000000F0UL)
+
+/*!< PPRE1 CONFIGURATION */
+#define STM32_RCC_CFGR_PPRE1_POS 8U
+#define STM32_RCC_CFGR_PPRE1_MSK (0x7UL << STM32_RCC_CFGR_PPRE1_POS)
+#define STM32_RCC_CFGR_PPRE1 STM32_RCC_CFGR_PPRE1_MSK
+#define STM32_RCC_CFGR_PPRE1_0 (0x1UL << STM32_RCC_CFGR_PPRE1_POS)
+#define STM32_RCC_CFGR_PPRE1_1 (0x2UL << STM32_RCC_CFGR_PPRE1_POS)
+#define STM32_RCC_CFGR_PPRE1_2 (0x4UL << STM32_RCC_CFGR_PPRE1_POS)
+
+#define STM32_RCC_CFGR_PPRE1_DIV1 (0x00000000UL)
+#define STM32_RCC_CFGR_PPRE1_DIV2 (0x00000400UL)
+#define STM32_RCC_CFGR_PPRE1_DIV4 (0x00000500UL)
+#define STM32_RCC_CFGR_PPRE1_DIV8 (0x00000600UL)
+#define STM32_RCC_CFGR_PPRE1_DIV16 (0x00000700UL)
+
+/*!< PPRE2 CONFIGURATION */
+#define STM32_RCC_CFGR_PPRE2_POS 11U
+#define STM32_RCC_CFGR_PPRE2_MSK (0x7UL << STM32_RCC_CFGR_PPRE2_POS)
+#define STM32_RCC_CFGR_PPRE2 STM32_RCC_CFGR_PPRE2_MSK
+#define STM32_RCC_CFGR_PPRE2_0 (0x1UL << STM32_RCC_CFGR_PPRE2_POS)
+#define STM32_RCC_CFGR_PPRE2_1 (0x2UL << STM32_RCC_CFGR_PPRE2_POS)
+#define STM32_RCC_CFGR_PPRE2_2 (0x4UL << STM32_RCC_CFGR_PPRE2_POS)
+
+#define STM32_RCC_CFGR_PPRE2_DIV1 (0x00000000UL)
+#define STM32_RCC_CFGR_PPRE2_DIV2 (0x00002000UL)
+#define STM32_RCC_CFGR_PPRE2_DIV4 (0x00002800UL)
+#define STM32_RCC_CFGR_PPRE2_DIV8 (0x00003000UL)
+#define STM32_RCC_CFGR_PPRE2_DIV16 (0x00003800UL)
+
+#define STM32_RCC_CFGR_STOPWUCK_POS 15U
+#define STM32_RCC_CFGR_STOPWUCK_MSK (0x1UL << STM32_RCC_CFGR_STOPWUCK_POS)
+#define STM32_RCC_CFGR_STOPWUCK STM32_RCC_CFGR_STOPWUCK_MSK
+
+/*!< MCOSEL CONFIGURATION */
+#define STM32_RCC_CFGR_MCOSEL_POS 24U
+#define STM32_RCC_CFGR_MCOSEL_MSK (0xFUL << STM32_RCC_CFGR_MCOSEL_POS)
+#define STM32_RCC_CFGR_MCOSEL STM32_RCC_CFGR_MCOSEL_MSK
+#define STM32_RCC_CFGR_MCOSEL_0 (0x1UL << STM32_RCC_CFGR_MCOSEL_POS)
+#define STM32_RCC_CFGR_MCOSEL_1 (0x2UL << STM32_RCC_CFGR_MCOSEL_POS)
+#define STM32_RCC_CFGR_MCOSEL_2 (0x4UL << STM32_RCC_CFGR_MCOSEL_POS)
+#define STM32_RCC_CFGR_MCOSEL_3 (0x8UL << STM32_RCC_CFGR_MCOSEL_POS)
+
+#define STM32_RCC_CFGR_MCOPRE_POS 28U
+#define STM32_RCC_CFGR_MCOPRE_MSK (0x7UL << STM32_RCC_CFGR_MCOPRE_POS)
+#define STM32_RCC_CFGR_MCOPRE STM32_RCC_CFGR_MCOPRE_MSK
+#define STM32_RCC_CFGR_MCOPRE_0 (0x1UL << STM32_RCC_CFGR_MCOPRE_POS)
+#define STM32_RCC_CFGR_MCOPRE_1 (0x2UL << STM32_RCC_CFGR_MCOPRE_POS)
+#define STM32_RCC_CFGR_MCOPRE_2 (0x4UL << STM32_RCC_CFGR_MCOPRE_POS)
+
+#define STM32_RCC_CFGR_MCOPRE_DIV1 (0x00000000UL)
+#define STM32_RCC_CFGR_MCOPRE_DIV2 (0x10000000UL)
+#define STM32_RCC_CFGR_MCOPRE_DIV4 (0x20000000UL)
+#define STM32_RCC_CFGR_MCOPRE_DIV8 (0x30000000UL)
+#define STM32_RCC_CFGR_MCOPRE_DIV16 (0x40000000UL)
+
+/* LEGACY ALIASES */
+#define STM32_RCC_CFGR_MCO_PRE STM32_RCC_CFGR_MCOPRE
+#define STM32_RCC_CFGR_MCO_PRE_1 STM32_RCC_CFGR_MCOPRE_DIV1
+#define STM32_RCC_CFGR_MCO_PRE_2 STM32_RCC_CFGR_MCOPRE_DIV2
+#define STM32_RCC_CFGR_MCO_PRE_4 STM32_RCC_CFGR_MCOPRE_DIV4
+#define STM32_RCC_CFGR_MCO_PRE_8 STM32_RCC_CFGR_MCOPRE_DIV8
+#define STM32_RCC_CFGR_MCO_PRE_16 STM32_RCC_CFGR_MCOPRE_DIV16
+
+/****************  BIT DEFINITION FOR STM32_RCC_PLLCFGR REGISTER  ***********/
+#define STM32_RCC_PLLCFGR_PLLSRC_POS 0U
+#define STM32_RCC_PLLCFGR_PLLSRC_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLSRC_POS)
+#define STM32_RCC_PLLCFGR_PLLSRC STM32_RCC_PLLCFGR_PLLSRC_MSK
+
+#define STM32_RCC_PLLCFGR_PLLSRC_MSI_POS 0U
+#define STM32_RCC_PLLCFGR_PLLSRC_MSI_MSK \
+	(0x1UL << STM32_RCC_PLLCFGR_PLLSRC_MSI_POS)
+#define STM32_RCC_PLLCFGR_PLLSRC_MSI STM32_RCC_PLLCFGR_PLLSRC_MSI_MSK
+#define STM32_RCC_PLLCFGR_PLLSRC_HSI_POS 1U
+#define STM32_RCC_PLLCFGR_PLLSRC_HSI_MSK \
+	(0x1UL << STM32_RCC_PLLCFGR_PLLSRC_HSI_POS)
+#define STM32_RCC_PLLCFGR_PLLSRC_HSI STM32_RCC_PLLCFGR_PLLSRC_HSI_MSK
+#define STM32_RCC_PLLCFGR_PLLSRC_HSE_POS 0U
+#define STM32_RCC_PLLCFGR_PLLSRC_HSE_MSK \
+	(0x3UL << STM32_RCC_PLLCFGR_PLLSRC_HSE_POS)
+#define STM32_RCC_PLLCFGR_PLLSRC_HSE STM32_RCC_PLLCFGR_PLLSRC_HSE_MSK
+
+#define STM32_RCC_PLLCFGR_PLLM_POS 4U
+#define STM32_RCC_PLLCFGR_PLLM_MSK (0x7UL << STM32_RCC_PLLCFGR_PLLM_POS)
+#define STM32_RCC_PLLCFGR_PLLM STM32_RCC_PLLCFGR_PLLM_MSK
+#define STM32_RCC_PLLCFGR_PLLM_0 (0x1UL << STM32_RCC_PLLCFGR_PLLM_POS)
+#define STM32_RCC_PLLCFGR_PLLM_1 (0x2UL << STM32_RCC_PLLCFGR_PLLM_POS)
+#define STM32_RCC_PLLCFGR_PLLM_2 (0x4UL << STM32_RCC_PLLCFGR_PLLM_POS)
+
+#define STM32_RCC_PLLCFGR_PLLN_POS 8U
+#define STM32_RCC_PLLCFGR_PLLN_MSK (0x7FUL << STM32_RCC_PLLCFGR_PLLN_POS)
+#define STM32_RCC_PLLCFGR_PLLN STM32_RCC_PLLCFGR_PLLN_MSK
+#define STM32_RCC_PLLCFGR_PLLN_0 (0x01UL << STM32_RCC_PLLCFGR_PLLN_POS)
+#define STM32_RCC_PLLCFGR_PLLN_1 (0x02UL << STM32_RCC_PLLCFGR_PLLN_POS)
+#define STM32_RCC_PLLCFGR_PLLN_2 (0x04UL << STM32_RCC_PLLCFGR_PLLN_POS)
+#define STM32_RCC_PLLCFGR_PLLN_3 (0x08UL << STM32_RCC_PLLCFGR_PLLN_POS)
+#define STM32_RCC_PLLCFGR_PLLN_4 (0x10UL << STM32_RCC_PLLCFGR_PLLN_POS)
+#define STM32_RCC_PLLCFGR_PLLN_5 (0x20UL << STM32_RCC_PLLCFGR_PLLN_POS)
+#define STM32_RCC_PLLCFGR_PLLN_6 (0x40UL << STM32_RCC_PLLCFGR_PLLN_POS)
+
+#define STM32_RCC_PLLCFGR_PLLPEN_POS 16U
+#define STM32_RCC_PLLCFGR_PLLPEN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLPEN_POS)
+#define STM32_RCC_PLLCFGR_PLLPEN STM32_RCC_PLLCFGR_PLLPEN_MSK
+#define STM32_RCC_PLLCFGR_PLLP_POS 17U
+#define STM32_RCC_PLLCFGR_PLLP_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLP_POS)
+#define STM32_RCC_PLLCFGR_PLLP STM32_RCC_PLLCFGR_PLLP_MSK
+#define STM32_RCC_PLLCFGR_PLLQEN_POS 20U
+#define STM32_RCC_PLLCFGR_PLLQEN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLQEN_POS)
+#define STM32_RCC_PLLCFGR_PLLQEN STM32_RCC_PLLCFGR_PLLQEN_MSK
+
+#define STM32_RCC_PLLCFGR_PLLQ_POS 21U
+#define STM32_RCC_PLLCFGR_PLLQ_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLQ_POS)
+#define STM32_RCC_PLLCFGR_PLLQ STM32_RCC_PLLCFGR_PLLQ_MSK
+#define STM32_RCC_PLLCFGR_PLLQ_0 (0x1UL << STM32_RCC_PLLCFGR_PLLQ_POS)
+#define STM32_RCC_PLLCFGR_PLLQ_1 (0x2UL << STM32_RCC_PLLCFGR_PLLQ_POS)
+
+#define STM32_RCC_PLLCFGR_PLLREN_POS 24U
+#define STM32_RCC_PLLCFGR_PLLREN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLREN_POS)
+#define STM32_RCC_PLLCFGR_PLLREN STM32_RCC_PLLCFGR_PLLREN_MSK
+#define STM32_RCC_PLLCFGR_PLLR_POS 25U
+#define STM32_RCC_PLLCFGR_PLLR_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLR_POS)
+#define STM32_RCC_PLLCFGR_PLLR STM32_RCC_PLLCFGR_PLLR_MSK
+#define STM32_RCC_PLLCFGR_PLLR_0 (0x1UL << STM32_RCC_PLLCFGR_PLLR_POS)
+#define STM32_RCC_PLLCFGR_PLLR_1 (0x2UL << STM32_RCC_PLLCFGR_PLLR_POS)
+
+#define STM32_RCC_PLLCFGR_PLLPDIV_POS 27U
+#define STM32_RCC_PLLCFGR_PLLPDIV_MSK (0x1FUL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
+#define STM32_RCC_PLLCFGR_PLLPDIV STM32_RCC_PLLCFGR_PLLPDIV_MSK
+#define STM32_RCC_PLLCFGR_PLLPDIV_0 (0x01UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
+#define STM32_RCC_PLLCFGR_PLLPDIV_1 (0x02UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
+#define STM32_RCC_PLLCFGR_PLLPDIV_2 (0x04UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
+#define STM32_RCC_PLLCFGR_PLLPDIV_3 (0x08UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
+#define STM32_RCC_PLLCFGR_PLLPDIV_4 (0x10UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
+
+/****************  BIT DEFINITION FOR STM32_RCC_PLLSAI1CFGR REGISTER  ********/
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS 8U
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_MSK \
+	(0x7FUL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N STM32_RCC_PLLSAI1CFGR_PLLSAI1N_MSK
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_0 \
+	(0x01UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_1 \
+	(0x02UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_2 \
+	(0x04UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_3 \
+	(0x08UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_4 \
+	(0x10UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_5 \
+	(0x20UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_6 \
+	(0x40UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
+
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_POS 16U
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_MSK \
+	(0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_POS)
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_MSK
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1P_POS 17U
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1P_MSK \
+	(0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1P_POS)
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1P STM32_RCC_PLLSAI1CFGR_PLLSAI1P_MSK
+
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN_POS 20U
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN_MSK \
+	(0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN_POS)
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN_MSK
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_POS 21U
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_MSK \
+	(0x3UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_POS)
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_MSK
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_0 \
+	(0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_POS)
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_1 \
+	(0x2UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_POS)
+
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1REN_POS 24U
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1REN_MSK \
+	(0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1REN_POS)
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1REN STM32_RCC_PLLSAI1CFGR_PLLSAI1REN_MSK
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R_POS 25U
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R_MSK \
+	(0x3UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1R_POS)
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R STM32_RCC_PLLSAI1CFGR_PLLSAI1R_MSK
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R_0 \
+	(0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1R_POS)
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R_1 \
+	(0x2UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1R_POS)
+
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS 27U
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_MSK \
+	(0x1FUL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS)
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_MSK
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_0 \
+	(0x01UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS)
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_1 \
+	(0x02UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS)
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_2 \
+	(0x04UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS)
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_3 \
+	(0x08UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS)
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_4 \
+	(0x10UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS)
+
+/**************  BIT DEFINITION FOR STM32_RCC_CIER REGISTER  ******************/
+#define STM32_RCC_CIER_LSIRDYIE_POS 0U
+#define STM32_RCC_CIER_LSIRDYIE_MSK (0x1UL << STM32_RCC_CIER_LSIRDYIE_POS)
+#define STM32_RCC_CIER_LSIRDYIE STM32_RCC_CIER_LSIRDYIE_MSK
+#define STM32_RCC_CIER_LSERDYIE_POS 1U
+#define STM32_RCC_CIER_LSERDYIE_MSK (0x1UL << STM32_RCC_CIER_LSERDYIE_POS)
+#define STM32_RCC_CIER_LSERDYIE STM32_RCC_CIER_LSERDYIE_MSK
+#define STM32_RCC_CIER_MSIRDYIE_POS 2U
+#define STM32_RCC_CIER_MSIRDYIE_MSK (0x1UL << STM32_RCC_CIER_MSIRDYIE_POS)
+#define STM32_RCC_CIER_MSIRDYIE STM32_RCC_CIER_MSIRDYIE_MSK
+#define STM32_RCC_CIER_HSIRDYIE_POS 3U
+#define STM32_RCC_CIER_HSIRDYIE_MSK (0x1UL << STM32_RCC_CIER_HSIRDYIE_POS)
+#define STM32_RCC_CIER_HSIRDYIE STM32_RCC_CIER_HSIRDYIE_MSK
+#define STM32_RCC_CIER_HSERDYIE_POS 4U
+#define STM32_RCC_CIER_HSERDYIE_MSK (0x1UL << STM32_RCC_CIER_HSERDYIE_POS)
+#define STM32_RCC_CIER_HSERDYIE STM32_RCC_CIER_HSERDYIE_MSK
+#define STM32_RCC_CIER_PLLRDYIE_POS 5U
+#define STM32_RCC_CIER_PLLRDYIE_MSK (0x1UL << STM32_RCC_CIER_PLLRDYIE_POS)
+#define STM32_RCC_CIER_PLLRDYIE STM32_RCC_CIER_PLLRDYIE_MSK
+#define STM32_RCC_CIER_PLLSAI1RDYIE_POS 6U
+#define STM32_RCC_CIER_PLLSAI1RDYIE_MSK \
+	(0x1UL << STM32_RCC_CIER_PLLSAI1RDYIE_POS)
+#define STM32_RCC_CIER_PLLSAI1RDYIE STM32_RCC_CIER_PLLSAI1RDYIE_MSK
+#define STM32_RCC_CIER_PLLSAI2RDYIE_POS 7U
+#define STM32_RCC_CIER_PLLSAI2RDYIE_MSK \
+	(0x1UL << STM32_RCC_CIER_PLLSAI2RDYIE_POS)
+#define STM32_RCC_CIER_PLLSAI2RDYIE STM32_RCC_CIER_PLLSAI2RDYIE_MSK
+#define STM32_RCC_CIER_HSI48RDYIE_POS 10U
+#define STM32_RCC_CIER_HSI48RDYIE_MSK (0x1UL << STM32_RCC_CIER_HSI48RDYIE_POS)
+#define STM32_RCC_CIER_HSI48RDYIE STM32_RCC_CIER_HSI48RDYIE_MSK
+
+/**************  BIT DEFINITION FOR STM32_RCC_CIFR REGISTER  ******************/
+#define STM32_RCC_CIFR_LSIRDYF_POS 0U
+#define STM32_RCC_CIFR_LSIRDYF_MSK (0x1UL << STM32_RCC_CIFR_LSIRDYF_POS)
+#define STM32_RCC_CIFR_LSIRDYF STM32_RCC_CIFR_LSIRDYF_MSK
+#define STM32_RCC_CIFR_LSERDYF_POS 1U
+#define STM32_RCC_CIFR_LSERDYF_MSK (0x1UL << STM32_RCC_CIFR_LSERDYF_POS)
+#define STM32_RCC_CIFR_LSERDYF STM32_RCC_CIFR_LSERDYF_MSK
+#define STM32_RCC_CIFR_MSIRDYF_POS 2U
+#define STM32_RCC_CIFR_MSIRDYF_MSK (0x1UL << STM32_RCC_CIFR_MSIRDYF_POS)
+#define STM32_RCC_CIFR_MSIRDYF STM32_RCC_CIFR_MSIRDYF_MSK
+#define STM32_RCC_CIFR_HSIRDYF_POS 3U
+#define STM32_RCC_CIFR_HSIRDYF_MSK (0x1UL << STM32_RCC_CIFR_HSIRDYF_POS)
+#define STM32_RCC_CIFR_HSIRDYF STM32_RCC_CIFR_HSIRDYF_MSK
+#define STM32_RCC_CIFR_HSERDYF_POS 4U
+#define STM32_RCC_CIFR_HSERDYF_MSK (0x1UL << STM32_RCC_CIFR_HSERDYF_POS)
+#define STM32_RCC_CIFR_HSERDYF STM32_RCC_CIFR_HSERDYF_MSK
+#define STM32_RCC_CIFR_PLLRDYF_POS 5U
+#define STM32_RCC_CIFR_PLLRDYF_MSK (0x1UL << STM32_RCC_CIFR_PLLRDYF_POS)
+#define STM32_RCC_CIFR_PLLRDYF STM32_RCC_CIFR_PLLRDYF_MSK
+#define STM32_RCC_CIFR_PLLSAI1RDYF_POS 6U
+#define STM32_RCC_CIFR_PLLSAI1RDYF_MSK (0x1UL << STM32_RCC_CIFR_PLLSAI1RDYF_POS)
+#define STM32_RCC_CIFR_PLLSAI1RDYF STM32_RCC_CIFR_PLLSAI1RDYF_MSK
+#define STM32_RCC_CIFR_PLLSAI2RDYF_POS 7U
+#define STM32_RCC_CIFR_PLLSAI2RDYF_MSK (0x1UL << STM32_RCC_CIFR_PLLSAI2RDYF_POS)
+#define STM32_RCC_CIFR_PLLSAI2RDYF STM32_RCC_CIFR_PLLSAI2RDYF_MSK
+#define STM32_RCC_CIFR_CSSF_POS 8U
+#define STM32_RCC_CIFR_CSSF_MSK (0x1UL << STM32_RCC_CIFR_CSSF_POS)
+#define STM32_RCC_CIFR_CSSF STM32_RCC_CIFR_CSSF_MSK
+#define STM32_RCC_CIFR_HSI48RDYF_POS 10U
+#define STM32_RCC_CIFR_HSI48RDYF_MSK (0x1UL << STM32_RCC_CIFR_HSI48RDYF_POS)
+#define STM32_RCC_CIFR_HSI48RDYF STM32_RCC_CIFR_HSI48RDYF_MSK
+
+/**************  BIT DEFINITION FOR STM32_RCC_CICR REGISTER  ******************/
+#define STM32_RCC_CICR_LSIRDYC_POS 0U
+#define STM32_RCC_CICR_LSIRDYC_MSK (0x1UL << STM32_RCC_CICR_LSIRDYC_POS)
+#define STM32_RCC_CICR_LSIRDYC STM32_RCC_CICR_LSIRDYC_MSK
+#define STM32_RCC_CICR_LSERDYC_POS 1U
+#define STM32_RCC_CICR_LSERDYC_MSK (0x1UL << STM32_RCC_CICR_LSERDYC_POS)
+#define STM32_RCC_CICR_LSERDYC STM32_RCC_CICR_LSERDYC_MSK
+#define STM32_RCC_CICR_MSIRDYC_POS 2U
+#define STM32_RCC_CICR_MSIRDYC_MSK (0x1UL << STM32_RCC_CICR_MSIRDYC_POS)
+#define STM32_RCC_CICR_MSIRDYC STM32_RCC_CICR_MSIRDYC_MSK
+#define STM32_RCC_CICR_HSIRDYC_POS 3U
+#define STM32_RCC_CICR_HSIRDYC_MSK (0x1UL << STM32_RCC_CICR_HSIRDYC_POS)
+#define STM32_RCC_CICR_HSIRDYC STM32_RCC_CICR_HSIRDYC_MSK
+#define STM32_RCC_CICR_HSERDYC_POS 4U
+#define STM32_RCC_CICR_HSERDYC_MSK (0x1UL << STM32_RCC_CICR_HSERDYC_POS)
+#define STM32_RCC_CICR_HSERDYC STM32_RCC_CICR_HSERDYC_MSK
+#define STM32_RCC_CICR_PLLRDYC_POS 5U
+#define STM32_RCC_CICR_PLLRDYC_MSK (0x1UL << STM32_RCC_CICR_PLLRDYC_POS)
+#define STM32_RCC_CICR_PLLRDYC STM32_RCC_CICR_PLLRDYC_MSK
+#define STM32_RCC_CICR_PLLSAI1RDYC_POS 6U
+#define STM32_RCC_CICR_PLLSAI1RDYC_MSK (0x1UL << STM32_RCC_CICR_PLLSAI1RDYC_POS)
+#define STM32_RCC_CICR_PLLSAI1RDYC STM32_RCC_CICR_PLLSAI1RDYC_MSK
+#define STM32_RCC_CICR_PLLSAI2RDYC_POS 7U
+#define STM32_RCC_CICR_PLLSAI2RDYC_MSK (0x1UL << STM32_RCC_CICR_PLLSAI2RDYC_POS)
+#define STM32_RCC_CICR_PLLSAI2RDYC STM32_RCC_CICR_PLLSAI2RDYC_MSK
+#define STM32_RCC_CICR_CSSC_POS 8U
+#define STM32_RCC_CICR_CSSC_MSK (0x1UL << STM32_RCC_CICR_CSSC_POS)
+#define STM32_RCC_CICR_CSSC STM32_RCC_CICR_CSSC_MSK
+#define STM32_RCC_CICR_HSI48RDYC_POS 10U
+#define STM32_RCC_CICR_HSI48RDYC_MSK (0x1UL << STM32_RCC_CICR_HSI48RDYC_POS)
+#define STM32_RCC_CICR_HSI48RDYC STM32_RCC_CICR_HSI48RDYC_MSK
+
+/**************  BIT DEFINITION FOR STM32_RCC_AHB1RSTR REGISTER  **************/
+#define STM32_RCC_AHB1RSTR_DMA1RST_POS 0U
+#define STM32_RCC_AHB1RSTR_DMA1RST_MSK (0x1UL << STM32_RCC_AHB1RSTR_DMA1RST_POS)
+#define STM32_RCC_AHB1RSTR_DMA1RST STM32_RCC_AHB1RSTR_DMA1RST_MSK
+#define STM32_RCC_AHB1RSTR_DMA2RST_POS 1U
+#define STM32_RCC_AHB1RSTR_DMA2RST_MSK (0x1UL << STM32_RCC_AHB1RSTR_DMA2RST_POS)
+#define STM32_RCC_AHB1RSTR_DMA2RST STM32_RCC_AHB1RSTR_DMA2RST_MSK
+#define STM32_RCC_AHB1RSTR_DMAMUX1RST_POS 2U
+#define STM32_RCC_AHB1RSTR_DMAMUX1RST_MSK \
+	(0x1UL << STM32_RCC_AHB1RSTR_DMAMUX1RST_POS)
+#define STM32_RCC_AHB1RSTR_DMAMUX1RST STM32_RCC_AHB1RSTR_DMAMUX1RST_MSK
+#define STM32_RCC_AHB1RSTR_FLASHRST_POS 8U
+#define STM32_RCC_AHB1RSTR_FLASHRST_MSK \
+	(0x1UL << STM32_RCC_AHB1RSTR_FLASHRST_POS)
+#define STM32_RCC_AHB1RSTR_FLASHRST STM32_RCC_AHB1RSTR_FLASHRST_MSK
+#define STM32_RCC_AHB1RSTR_CRCRST_POS 12U
+#define STM32_RCC_AHB1RSTR_CRCRST_MSK (0x1UL << STM32_RCC_AHB1RSTR_CRCRST_POS)
+#define STM32_RCC_AHB1RSTR_CRCRST STM32_RCC_AHB1RSTR_CRCRST_MSK
+#define STM32_RCC_AHB1RSTR_TSCRST_POS 16U
+#define STM32_RCC_AHB1RSTR_TSCRST_MSK (0x1UL << STM32_RCC_AHB1RSTR_TSCRST_POS)
+#define STM32_RCC_AHB1RSTR_TSCRST STM32_RCC_AHB1RSTR_TSCRST_MSK
+
+/**************  BIT DEFINITION FOR STM32_RCC_AHB2RSTR REGISTER  **************/
+#define STM32_RCC_AHB2RSTR_GPIOARST_POS 0U
+#define STM32_RCC_AHB2RSTR_GPIOARST_MSK \
+	(0x1UL << STM32_RCC_AHB2RSTR_GPIOARST_POS)
+#define STM32_RCC_AHB2RSTR_GPIOARST STM32_RCC_AHB2RSTR_GPIOARST_MSK
+#define STM32_RCC_AHB2RSTR_GPIOBRST_POS 1U
+#define STM32_RCC_AHB2RSTR_GPIOBRST_MSK \
+	(0x1UL << STM32_RCC_AHB2RSTR_GPIOBRST_POS)
+#define STM32_RCC_AHB2RSTR_GPIOBRST STM32_RCC_AHB2RSTR_GPIOBRST_MSK
+#define STM32_RCC_AHB2RSTR_GPIOCRST_POS 2U
+#define STM32_RCC_AHB2RSTR_GPIOCRST_MSK \
+	(0x1UL << STM32_RCC_AHB2RSTR_GPIOCRST_POS)
+#define STM32_RCC_AHB2RSTR_GPIOCRST STM32_RCC_AHB2RSTR_GPIOCRST_MSK
+#define STM32_RCC_AHB2RSTR_GPIODRST_POS 3U
+#define STM32_RCC_AHB2RSTR_GPIODRST_MSK \
+	(0x1UL << STM32_RCC_AHB2RSTR_GPIODRST_POS)
+#define STM32_RCC_AHB2RSTR_GPIODRST STM32_RCC_AHB2RSTR_GPIODRST_MSK
+#define STM32_RCC_AHB2RSTR_GPIOERST_POS 4U
+#define STM32_RCC_AHB2RSTR_GPIOERST_MSK \
+	(0x1UL << STM32_RCC_AHB2RSTR_GPIOERST_POS)
+#define STM32_RCC_AHB2RSTR_GPIOERST STM32_RCC_AHB2RSTR_GPIOERST_MSK
+#define STM32_RCC_AHB2RSTR_GPIOFRST_POS 5U
+#define STM32_RCC_AHB2RSTR_GPIOFRST_MSK \
+	(0x1UL << STM32_RCC_AHB2RSTR_GPIOFRST_POS)
+#define STM32_RCC_AHB2RSTR_GPIOFRST STM32_RCC_AHB2RSTR_GPIOFRST_MSK
+#define STM32_RCC_AHB2RSTR_GPIOGRST_POS 6U
+#define STM32_RCC_AHB2RSTR_GPIOGRST_MSK \
+	(0x1UL << STM32_RCC_AHB2RSTR_GPIOGRST_POS)
+#define STM32_RCC_AHB2RSTR_GPIOGRST STM32_RCC_AHB2RSTR_GPIOGRST_MSK
+#define STM32_RCC_AHB2RSTR_GPIOHRST_POS 7U
+#define STM32_RCC_AHB2RSTR_GPIOHRST_MSK \
+	(0x1UL << STM32_RCC_AHB2RSTR_GPIOHRST_POS)
+#define STM32_RCC_AHB2RSTR_GPIOHRST STM32_RCC_AHB2RSTR_GPIOHRST_MSK
+#define STM32_RCC_AHB2RSTR_ADCRST_POS 13U
+#define STM32_RCC_AHB2RSTR_ADCRST_MSK (0x1UL << STM32_RCC_AHB2RSTR_ADCRST_POS)
+#define STM32_RCC_AHB2RSTR_ADCRST STM32_RCC_AHB2RSTR_ADCRST_MSK
+#define STM32_RCC_AHB2RSTR_AESRST_POS 16U
+#define STM32_RCC_AHB2RSTR_AESRST_MSK (0x1UL << STM32_RCC_AHB2RSTR_AESRST_POS)
+#define STM32_RCC_AHB2RSTR_AESRST STM32_RCC_AHB2RSTR_AESRST_MSK
+#define STM32_RCC_AHB2RSTR_HASHRST_POS 17U
+#define STM32_RCC_AHB2RSTR_HASHRST_MSK (0x1UL << STM32_RCC_AHB2RSTR_HASHRST_POS)
+#define STM32_RCC_AHB2RSTR_HASHRST STM32_RCC_AHB2RSTR_HASHRST_MSK
+#define STM32_RCC_AHB2RSTR_RNGRST_POS 18U
+#define STM32_RCC_AHB2RSTR_RNGRST_MSK (0x1UL << STM32_RCC_AHB2RSTR_RNGRST_POS)
+#define STM32_RCC_AHB2RSTR_RNGRST STM32_RCC_AHB2RSTR_RNGRST_MSK
+
+/*************  BIT DEFINITION FOR STM32_RCC_AHB3RSTR REGISTER  **************/
+#define STM32_RCC_AHB3RSTR_FMCRST_POS 0U
+#define STM32_RCC_AHB3RSTR_FMCRST_MSK (0x1UL << STM32_RCC_AHB3RSTR_FMCRST_POS)
+#define STM32_RCC_AHB3RSTR_FMCRST STM32_RCC_AHB3RSTR_FMCRST_MSK
+#define STM32_RCC_AHB3RSTR_QSPIRST_POS 8U
+#define STM32_RCC_AHB3RSTR_QSPIRST_MSK (0x1UL << STM32_RCC_AHB3RSTR_QSPIRST_POS)
+#define STM32_RCC_AHB3RSTR_QSPIRST STM32_RCC_AHB3RSTR_QSPIRST_MSK
+
+/*************  BIT DEFINITION FOR STM32_RCC_APB1RSTR1 REGISTER  **************/
+#define STM32_RCC_APB1RSTR1_TIM2RST_POS 0U
+#define STM32_RCC_APB1RSTR1_TIM2RST_MSK \
+	(0x1UL << STM32_RCC_APB1RSTR1_TIM2RST_POS)
+#define STM32_RCC_APB1RSTR1_TIM2RST STM32_RCC_APB1RSTR1_TIM2RST_MSK
+#define STM32_RCC_APB1RSTR1_TIM3RST_POS 1U
+#define STM32_RCC_APB1RSTR1_TIM3RST_MSK \
+	(0x1UL << STM32_RCC_APB1RSTR1_TIM3RST_POS)
+#define STM32_RCC_APB1RSTR1_TIM3RST STM32_RCC_APB1RSTR1_TIM3RST_MSK
+#define STM32_RCC_APB1RSTR1_TIM4RST_POS 2U
+#define STM32_RCC_APB1RSTR1_TIM4RST_MSK \
+	(0x1UL << STM32_RCC_APB1RSTR1_TIM4RST_POS)
+#define STM32_RCC_APB1RSTR1_TIM4RST STM32_RCC_APB1RSTR1_TIM4RST_MSK
+#define STM32_RCC_APB1RSTR1_TIM5RST_POS 3U
+#define STM32_RCC_APB1RSTR1_TIM5RST_MSK \
+	(0x1UL << STM32_RCC_APB1RSTR1_TIM5RST_POS)
+#define STM32_RCC_APB1RSTR1_TIM5RST STM32_RCC_APB1RSTR1_TIM5RST_MSK
+#define STM32_RCC_APB1RSTR1_TIM6RST_POS 4U
+#define STM32_RCC_APB1RSTR1_TIM6RST_MSK \
+	(0x1UL << STM32_RCC_APB1RSTR1_TIM6RST_POS)
+#define STM32_RCC_APB1RSTR1_TIM6RST STM32_RCC_APB1RSTR1_TIM6RST_MSK
+#define STM32_RCC_APB1RSTR1_TIM7RST_POS 5U
+#define STM32_RCC_APB1RSTR1_TIM7RST_MSK \
+	(0x1UL << STM32_RCC_APB1RSTR1_TIM7RST_POS)
+#define STM32_RCC_APB1RSTR1_TIM7RST STM32_RCC_APB1RSTR1_TIM7RST_MSK
+#define STM32_RCC_APB1RSTR1_SPI2RST_POS 14U
+#define STM32_RCC_APB1RSTR1_SPI2RST_MSK \
+	(0x1UL << STM32_RCC_APB1RSTR1_SPI2RST_POS)
+#define STM32_RCC_APB1RSTR1_SPI2RST STM32_RCC_APB1RSTR1_SPI2RST_MSK
+#define STM32_RCC_APB1RSTR1_SPI3RST_POS 15U
+#define STM32_RCC_APB1RSTR1_SPI3RST_MSK \
+	(0x1UL << STM32_RCC_APB1RSTR1_SPI3RST_POS)
+#define STM32_RCC_APB1RSTR1_SPI3RST STM32_RCC_APB1RSTR1_SPI3RST_MSK
+#define STM32_RCC_APB1RSTR1_USART2RST_POS 17U
+#define STM32_RCC_APB1RSTR1_USART2RST_MSK \
+	(0x1UL << STM32_RCC_APB1RSTR1_USART2RST_POS)
+#define STM32_RCC_APB1RSTR1_USART2RST STM32_RCC_APB1RSTR1_USART2RST_MSK
+#define STM32_RCC_APB1RSTR1_USART3RST_POS 18U
+#define STM32_RCC_APB1RSTR1_USART3RST_MSK \
+	(0x1UL << STM32_RCC_APB1RSTR1_USART3RST_POS)
+#define STM32_RCC_APB1RSTR1_USART3RST STM32_RCC_APB1RSTR1_USART3RST_MSK
+#define STM32_RCC_APB1RSTR1_USART4RST_POS 19U
+#define STM32_RCC_APB1RSTR1_USART4RST_MSK \
+	(0x1UL << STM32_RCC_APB1RSTR1_USART4RST_POS)
+#define STM32_RCC_APB1RSTR1_USART4RST STM32_RCC_APB1RSTR1_USART4RST_MSK
+#define STM32_RCC_APB1RSTR1_USART5RST_POS 20U
+#define STM32_RCC_APB1RSTR1_USART5RST_MSK \
+	(0x1UL << STM32_RCC_APB1RSTR1_USART5RST_POS)
+#define STM32_RCC_APB1RSTR1_USART5RST STM32_RCC_APB1RSTR1_USART5RST_MSK
+#define STM32_RCC_APB1RSTR1_I2C1RST_POS 21U
+#define STM32_RCC_APB1RSTR1_I2C1RST_MSK \
+	(0x1UL << STM32_RCC_APB1RSTR1_I2C1RST_POS)
+#define STM32_RCC_APB1RSTR1_I2C1RST STM32_RCC_APB1RSTR1_I2C1RST_MSK
+#define STM32_RCC_APB1RSTR1_I2C2RST_POS 22U
+#define STM32_RCC_APB1RSTR1_I2C2RST_MSK \
+	(0x1UL << STM32_RCC_APB1RSTR1_I2C2RST_POS)
+#define STM32_RCC_APB1RSTR1_I2C2RST STM32_RCC_APB1RSTR1_I2C2RST_MSK
+#define STM32_RCC_APB1RSTR1_I2C3RST_POS 23U
+#define STM32_RCC_APB1RSTR1_I2C3RST_MSK \
+	(0x1UL << STM32_RCC_APB1RSTR1_I2C3RST_POS)
+#define STM32_RCC_APB1RSTR1_I2C3RST STM32_RCC_APB1RSTR1_I2C3RST_MSK
+#define STM32_RCC_APB1RSTR1_CRSRST_POS 24U
+#define STM32_RCC_APB1RSTR1_CRSRST_MSK (0x1UL << STM32_RCC_APB1RSTR1_CRSRST_POS)
+#define STM32_RCC_APB1RSTR1_CRSRST STM32_RCC_APB1RSTR1_CRSRST_MSK
+#define STM32_RCC_APB1RSTR1_PWRRST_POS 28U
+#define STM32_RCC_APB1RSTR1_PWRRST_MSK (0x1UL << STM32_RCC_APB1RSTR1_PWRRST_POS)
+#define STM32_RCC_APB1RSTR1_PWRRST STM32_RCC_APB1RSTR1_PWRRST_MSK
+#define STM32_RCC_APB1RSTR1_DAC1RST_POS 29U
+#define STM32_RCC_APB1RSTR1_DAC1RST_MSK \
+	(0x1UL << STM32_RCC_APB1RSTR1_DAC1RST_POS)
+#define STM32_RCC_APB1RSTR1_DAC1RST STM32_RCC_APB1RSTR1_DAC1RST_MSK
+#define STM32_RCC_APB1RSTR1_OPAMPRST_POS 30U
+#define STM32_RCC_APB1RSTR1_OPAMPRST_MSK \
+	(0x1UL << STM32_RCC_APB1RSTR1_OPAMPRST_POS)
+#define STM32_RCC_APB1RSTR1_OPAMPRST STM32_RCC_APB1RSTR1_OPAMPRST_MSK
+#define STM32_RCC_APB1RSTR1_LPTIM1RST_POS 31U
+#define STM32_RCC_APB1RSTR1_LPTIM1RST_MSK \
+	(0x1UL << STM32_RCC_APB1RSTR1_LPTIM1RST_POS)
+#define STM32_RCC_APB1RSTR1_LPTIM1RST STM32_RCC_APB1RSTR1_LPTIM1RST_MSK
+
+/*************  BIT DEFINITION FOR STM32_RCC_APB1RSTR2 REGISTER  **************/
+#define STM32_RCC_APB1RSTR2_LPUART1RST_POS 0U
+#define STM32_RCC_APB1RSTR2_LPUART1RST_MSK \
+	(0x1UL << STM32_RCC_APB1RSTR2_LPUART1RST_POS)
+#define STM32_RCC_APB1RSTR2_LPUART1RST STM32_RCC_APB1RSTR2_LPUART1RST_MSK
+#define STM32_RCC_APB1RSTR2_I2C4RST_POS 1U
+#define STM32_RCC_APB1RSTR2_I2C4RST_MSK \
+	(0x1UL << STM32_RCC_APB1RSTR2_I2C4RST_POS)
+#define STM32_RCC_APB1RSTR2_I2C4RST STM32_RCC_APB1RSTR2_I2C4RST_MSK
+#define STM32_RCC_APB1RSTR2_LPTIM2RST_POS 5U
+#define STM32_RCC_APB1RSTR2_LPTIM2RST_MSK \
+	(0x1UL << STM32_RCC_APB1RSTR2_LPTIM2RST_POS)
+#define STM32_RCC_APB1RSTR2_LPTIM2RST STM32_RCC_APB1RSTR2_LPTIM2RST_MSK
+#define STM32_RCC_APB1RSTR2_LPTIM3RST_POS 6U
+#define STM32_RCC_APB1RSTR2_LPTIM3RST_MSK \
+	(0x1UL << STM32_RCC_APB1RSTR2_LPTIM3RST_POS)
+#define STM32_RCC_APB1RSTR2_LPTIM3RST STM32_RCC_APB1RSTR2_LPTIM3RST_MSK
+#define STM32_RCC_APB1RSTR2_FDCAN1RST_POS 9U
+#define STM32_RCC_APB1RSTR2_FDCAN1RST_MSK \
+	(0x1UL << STM32_RCC_APB1RSTR2_FDCAN1RST_POS)
+#define STM32_RCC_APB1RSTR2_FDCAN1RST STM32_RCC_APB1RSTR2_FDCAN1RST_MSK
+#define STM32_RCC_APB1RSTR2_USBFSRST_POS 21U
+#define STM32_RCC_APB1RSTR2_USBFSRST_MSK \
+	(0x1UL << STM32_RCC_APB1RSTR2_USBFSRST_POS)
+#define STM32_RCC_APB1RSTR2_USBFSRST STM32_RCC_APB1RSTR2_USBFSRST_MSK
+#define STM32_RCC_APB1RSTR2_UCPD1RST_POS 23U
+#define STM32_RCC_APB1RSTR2_UCPD1RST_MSK \
+	(0x1UL << STM32_RCC_APB1RSTR2_UCPD1RST_POS)
+#define STM32_RCC_APB1RSTR2_UCPD1RST STM32_RCC_APB1RSTR2_UCPD1RST_MSK
+
+/**************  BIT DEFINITION FOR STM32_RCC_APB2RSTR REGISTER  **************/
+#define STM32_RCC_APB2RSTR_SYSCFGRST_POS 0U
+#define STM32_RCC_APB2RSTR_SYSCFGRST_MSK \
+	(0x1UL << STM32_RCC_APB2RSTR_SYSCFGRST_POS)
+#define STM32_RCC_APB2RSTR_SYSCFGRST STM32_RCC_APB2RSTR_SYSCFGRST_MSK
+#define STM32_RCC_APB2RSTR_TIM1RST_POS 11U
+#define STM32_RCC_APB2RSTR_TIM1RST_MSK (0x1UL << STM32_RCC_APB2RSTR_TIM1RST_POS)
+#define STM32_RCC_APB2RSTR_TIM1RST STM32_RCC_APB2RSTR_TIM1RST_MSK
+#define STM32_RCC_APB2RSTR_SPI1RST_POS 12U
+#define STM32_RCC_APB2RSTR_SPI1RST_MSK (0x1UL << STM32_RCC_APB2RSTR_SPI1RST_POS)
+#define STM32_RCC_APB2RSTR_SPI1RST STM32_RCC_APB2RSTR_SPI1RST_MSK
+#define STM32_RCC_APB2RSTR_TIM8RST_POS 13U
+#define STM32_RCC_APB2RSTR_TIM8RST_MSK (0x1UL << STM32_RCC_APB2RSTR_TIM8RST_POS)
+#define STM32_RCC_APB2RSTR_TIM8RST STM32_RCC_APB2RSTR_TIM8RST_MSK
+#define STM32_RCC_APB2RSTR_USART1RST_POS 14U
+#define STM32_RCC_APB2RSTR_USART1RST_MSK \
+	(0x1UL << STM32_RCC_APB2RSTR_USART1RST_POS)
+#define STM32_RCC_APB2RSTR_USART1RST STM32_RCC_APB2RSTR_USART1RST_MSK
+#define STM32_RCC_APB2RSTR_TIM15RST_POS 16U
+#define STM32_RCC_APB2RSTR_TIM15RST_MSK \
+	(0x1UL << STM32_RCC_APB2RSTR_TIM15RST_POS)
+#define STM32_RCC_APB2RSTR_TIM15RST STM32_RCC_APB2RSTR_TIM15RST_MSK
+#define STM32_RCC_APB2RSTR_TIM16RST_POS 17U
+#define STM32_RCC_APB2RSTR_TIM16RST_MSK \
+	(0x1UL << STM32_RCC_APB2RSTR_TIM16RST_POS)
+#define STM32_RCC_APB2RSTR_TIM16RST STM32_RCC_APB2RSTR_TIM16RST_MSK
+#define STM32_RCC_APB2RSTR_TIM17RST_POS 18U
+#define STM32_RCC_APB2RSTR_TIM17RST_MSK \
+	(0x1UL << STM32_RCC_APB2RSTR_TIM17RST_POS)
+#define STM32_RCC_APB2RSTR_TIM17RST STM32_RCC_APB2RSTR_TIM17RST_MSK
+#define STM32_RCC_APB2RSTR_SAI1RST_POS 21U
+#define STM32_RCC_APB2RSTR_SAI1RST_MSK (0x1UL << STM32_RCC_APB2RSTR_SAI1RST_POS)
+#define STM32_RCC_APB2RSTR_SAI1RST STM32_RCC_APB2RSTR_SAI1RST_MSK
+#define STM32_RCC_APB2RSTR_SAI2RST_POS 22U
+#define STM32_RCC_APB2RSTR_SAI2RST_MSK (0x1UL << STM32_RCC_APB2RSTR_SAI2RST_POS)
+#define STM32_RCC_APB2RSTR_SAI2RST STM32_RCC_APB2RSTR_SAI2RST_MSK
+#define STM32_RCC_APB2RSTR_DFSDM1RST_POS 24U
+#define STM32_RCC_APB2RSTR_DFSDM1RST_MSK \
+	(0x1UL << STM32_RCC_APB2RSTR_DFSDM1RST_POS)
+#define STM32_RCC_APB2RSTR_DFSDM1RST STM32_RCC_APB2RSTR_DFSDM1RST_MSK
+
+/**************  BIT DEFINITION FOR STM32_RCC_AHB1ENR REGISTER  ***************/
+#define STM32_RCC_AHB1ENR_DMA1EN_POS 0U
+#define STM32_RCC_AHB1ENR_DMA1EN_MSK (0x1UL << STM32_RCC_AHB1ENR_DMA1EN_POS)
+#define STM32_RCC_AHB1ENR_DMA1EN STM32_RCC_AHB1ENR_DMA1EN_MSK
+#define STM32_RCC_AHB1ENR_DMA2EN_POS 1U
+#define STM32_RCC_AHB1ENR_DMA2EN_MSK (0x1UL << STM32_RCC_AHB1ENR_DMA2EN_POS)
+#define STM32_RCC_AHB1ENR_DMA2EN STM32_RCC_AHB1ENR_DMA2EN_MSK
+#define STM32_RCC_AHB1ENR_DMAMUX1EN_POS 2U
+#define STM32_RCC_AHB1ENR_DMAMUX1EN_MSK \
+	(0x1UL << STM32_RCC_AHB1ENR_DMAMUX1EN_POS)
+#define STM32_RCC_AHB1ENR_DMAMUX1EN STM32_RCC_AHB1ENR_DMAMUX1EN_MSK
+#define STM32_RCC_AHB1ENR_DMAMUXEN STM32_RCC_AHB1ENR_DMAMUX1EN_MSK
+#define STM32_RCC_AHB1ENR_FLASHEN_POS 8U
+#define STM32_RCC_AHB1ENR_FLASHEN_MSK (0x1UL << STM32_RCC_AHB1ENR_FLASHEN_POS)
+#define STM32_RCC_AHB1ENR_FLASHEN STM32_RCC_AHB1ENR_FLASHEN_MSK
+#define STM32_RCC_AHB1ENR_CRCEN_POS 12U
+#define STM32_RCC_AHB1ENR_CRCEN_MSK (0x1UL << STM32_RCC_AHB1ENR_CRCEN_POS)
+#define STM32_RCC_AHB1ENR_CRCEN STM32_RCC_AHB1ENR_CRCEN_MSK
+#define STM32_RCC_AHB1ENR_TSCEN_POS 16U
+#define STM32_RCC_AHB1ENR_TSCEN_MSK (0x1UL << STM32_RCC_AHB1ENR_TSCEN_POS)
+#define STM32_RCC_AHB1ENR_TSCEN STM32_RCC_AHB1ENR_TSCEN_MSK
+#define STM32_RCC_AHB1ENR_GTZCEN_POS 22U
+#define STM32_RCC_AHB1ENR_GTZCEN_MSK (0x1UL << STM32_RCC_AHB1ENR_GTZCEN_POS)
+#define STM32_RCC_AHB1ENR_GTZCEN STM32_RCC_AHB1ENR_GTZCEN_MSK
+
+/***************  BIT DEFINITION FOR STM32_RCC_AHB2ENR REGISTER  *********/
+#define STM32_RCC_AHB2ENR_GPIOAEN_POS 0U
+#define STM32_RCC_AHB2ENR_GPIOAEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOAEN_POS)
+#define STM32_RCC_AHB2ENR_GPIOAEN STM32_RCC_AHB2ENR_GPIOAEN_MSK
+#define STM32_RCC_AHB2ENR_GPIOBEN_POS 1U
+#define STM32_RCC_AHB2ENR_GPIOBEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOBEN_POS)
+#define STM32_RCC_AHB2ENR_GPIOBEN STM32_RCC_AHB2ENR_GPIOBEN_MSK
+#define STM32_RCC_AHB2ENR_GPIOCEN_POS 2U
+#define STM32_RCC_AHB2ENR_GPIOCEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOCEN_POS)
+#define STM32_RCC_AHB2ENR_GPIOCEN STM32_RCC_AHB2ENR_GPIOCEN_MSK
+#define STM32_RCC_AHB2ENR_GPIODEN_POS 3U
+#define STM32_RCC_AHB2ENR_GPIODEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIODEN_POS)
+#define STM32_RCC_AHB2ENR_GPIODEN STM32_RCC_AHB2ENR_GPIODEN_MSK
+#define STM32_RCC_AHB2ENR_GPIOEEN_POS 4U
+#define STM32_RCC_AHB2ENR_GPIOEEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOEEN_POS)
+#define STM32_RCC_AHB2ENR_GPIOEEN STM32_RCC_AHB2ENR_GPIOEEN_MSK
+#define STM32_RCC_AHB2ENR_GPIOFEN_POS 5U
+#define STM32_RCC_AHB2ENR_GPIOFEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOFEN_POS)
+#define STM32_RCC_AHB2ENR_GPIOFEN STM32_RCC_AHB2ENR_GPIOFEN_MSK
+#define STM32_RCC_AHB2ENR_GPIOGEN_POS 6U
+#define STM32_RCC_AHB2ENR_GPIOGEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOGEN_POS)
+#define STM32_RCC_AHB2ENR_GPIOGEN STM32_RCC_AHB2ENR_GPIOGEN_MSK
+#define STM32_RCC_AHB2ENR_GPIOHEN_POS 7U
+#define STM32_RCC_AHB2ENR_GPIOHEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOHEN_POS)
+#define STM32_RCC_AHB2ENR_GPIOHEN STM32_RCC_AHB2ENR_GPIOHEN_MSK
+#define STM32_RCC_AHB2ENR_ADCEN_POS 13U
+#define STM32_RCC_AHB2ENR_ADCEN_MSK (0x1UL << STM32_RCC_AHB2ENR_ADCEN_POS)
+#define STM32_RCC_AHB2ENR_ADCEN STM32_RCC_AHB2ENR_ADCEN_MSK
+#define STM32_RCC_AHB2ENR_AESEN_POS 16U
+#define STM32_RCC_AHB2ENR_AESEN_MSK (0x1UL << STM32_RCC_AHB2ENR_AESEN_POS)
+#define STM32_RCC_AHB2ENR_AESEN STM32_RCC_AHB2ENR_AESEN_MSK
+#define STM32_RCC_AHB2ENR_HASHEN_POS 17U
+#define STM32_RCC_AHB2ENR_HASHEN_MSK (0x1UL << STM32_RCC_AHB2ENR_HASHEN_POS)
+#define STM32_RCC_AHB2ENR_HASHEN STM32_RCC_AHB2ENR_HASHEN_MSK
+#define STM32_RCC_AHB2ENR_RNGEN_POS 18U
+#define STM32_RCC_AHB2ENR_RNGEN_MSK (0x1UL << STM32_RCC_AHB2ENR_RNGEN_POS)
+#define STM32_RCC_AHB2ENR_RNGEN STM32_RCC_AHB2ENR_RNGEN_MSK
+#define STM32_RCC_AHB2ENR_PKAEN_POS 19U
+#define STM32_RCC_AHB2ENR_PKAEN_MSK (0x1UL << STM32_RCC_AHB2ENR_PKAEN_POS)
+#define STM32_RCC_AHB2ENR_PKAEN STM32_RCC_AHB2ENR_PKAEN_MSK
+#define STM32_RCC_AHB2ENR_OTFDEC1EN_POS 21U
+#define STM32_RCC_AHB2ENR_OTFDEC1EN_MSK \
+	(0x1UL << STM32_RCC_AHB2ENR_OTFDEC1EN_POS)
+#define STM32_RCC_AHB2ENR_OTFDEC1EN STM32_RCC_AHB2ENR_OTFDEC1EN_MSK
+#define STM32_RCC_AHB2ENR_SDMMC1EN_POS 22U
+#define STM32_RCC_AHB2ENR_SDMMC1EN_MSK (0x1UL << STM32_RCC_AHB2ENR_SDMMC1EN_POS)
+#define STM32_RCC_AHB2ENR_SDMMC1EN STM32_RCC_AHB2ENR_SDMMC1EN_MSK
+
+/**************  BIT DEFINITION FOR STM32_RCC_AHB3ENR REGISTER  ***************/
+#define STM32_RCC_AHB3ENR_FMCEN_POS 0U
+#define STM32_RCC_AHB3ENR_FMCEN_MSK (0x1UL << STM32_RCC_AHB3ENR_FMCEN_POS)
+#define STM32_RCC_AHB3ENR_FMCEN STM32_RCC_AHB3ENR_FMCEN_MSK
+#define STM32_RCC_AHB3ENR_QSPIEN_POS 8U
+#define STM32_RCC_AHB3ENR_QSPIEN_MSK (0x1UL << STM32_RCC_AHB3ENR_QSPIEN_POS)
+#define STM32_RCC_AHB3ENR_QSPIEN STM32_RCC_AHB3ENR_QSPIEN_MSK
+
+/**************  BIT DEFINITION FOR STM32_RCC_APB1ENR1 REGISTER  **************/
+#define STM32_RCC_APB1ENR1_TIM2EN_POS 0U
+#define STM32_RCC_APB1ENR1_TIM2EN_MSK (0x1UL << STM32_RCC_APB1ENR1_TIM2EN_POS)
+#define STM32_RCC_APB1ENR1_TIM2EN STM32_RCC_APB1ENR1_TIM2EN_MSK
+#define STM32_RCC_APB1ENR1_TIM3EN_POS 1U
+#define STM32_RCC_APB1ENR1_TIM3EN_MSK (0x1UL << STM32_RCC_APB1ENR1_TIM3EN_POS)
+#define STM32_RCC_APB1ENR1_TIM3EN STM32_RCC_APB1ENR1_TIM3EN_MSK
+#define STM32_RCC_APB1ENR1_TIM4EN_POS 2U
+#define STM32_RCC_APB1ENR1_TIM4EN_MSK (0x1UL << STM32_RCC_APB1ENR1_TIM4EN_POS)
+#define STM32_RCC_APB1ENR1_TIM4EN STM32_RCC_APB1ENR1_TIM4EN_MSK
+#define STM32_RCC_APB1ENR1_TIM5EN_POS 3U
+#define STM32_RCC_APB1ENR1_TIM5EN_MSK (0x1UL << STM32_RCC_APB1ENR1_TIM5EN_POS)
+#define STM32_RCC_APB1ENR1_TIM5EN STM32_RCC_APB1ENR1_TIM5EN_MSK
+#define STM32_RCC_APB1ENR1_TIM6EN_POS 4U
+#define STM32_RCC_APB1ENR1_TIM6EN_MSK (0x1UL << STM32_RCC_APB1ENR1_TIM6EN_POS)
+#define STM32_RCC_APB1ENR1_TIM6EN STM32_RCC_APB1ENR1_TIM6EN_MSK
+#define STM32_RCC_APB1ENR1_TIM7EN_POS 5U
+#define STM32_RCC_APB1ENR1_TIM7EN_MSK (0x1UL << STM32_RCC_APB1ENR1_TIM7EN_POS)
+#define STM32_RCC_APB1ENR1_TIM7EN STM32_RCC_APB1ENR1_TIM7EN_MSK
+#define STM32_RCC_APB1ENR1_RTCAPBEN_POS 10U
+#define STM32_RCC_APB1ENR1_RTCAPBEN_MSK \
+	(0x1UL << STM32_RCC_APB1ENR1_RTCAPBEN_POS)
+#define STM32_RCC_APB1ENR1_RTCAPBEN STM32_RCC_APB1ENR1_RTCAPBEN_MSK
+#define STM32_RCC_APB1ENR1_WWDGEN_POS 11U
+#define STM32_RCC_APB1ENR1_WWDGEN_MSK (0x1UL << STM32_RCC_APB1ENR1_WWDGEN_POS)
+#define STM32_RCC_APB1ENR1_WWDGEN STM32_RCC_APB1ENR1_WWDGEN_MSK
+#define STM32_RCC_APB1ENR1_SPI2EN_POS 14U
+#define STM32_RCC_APB1ENR1_SPI2EN_MSK (0x1UL << STM32_RCC_APB1ENR1_SPI2EN_POS)
+#define STM32_RCC_APB1ENR1_SPI2EN STM32_RCC_APB1ENR1_SPI2EN_MSK
+#define STM32_RCC_APB1ENR1_SPI3EN_POS 15U
+#define STM32_RCC_APB1ENR1_SPI3EN_MSK (0x1UL << STM32_RCC_APB1ENR1_SPI3EN_POS)
+#define STM32_RCC_APB1ENR1_SPI3EN STM32_RCC_APB1ENR1_SPI3EN_MSK
+#define STM32_RCC_APB1ENR1_USART2EN_POS 17U
+#define STM32_RCC_APB1ENR1_USART2EN_MSK \
+	(0x1UL << STM32_RCC_APB1ENR1_USART2EN_POS)
+#define STM32_RCC_APB1ENR1_USART2EN STM32_RCC_APB1ENR1_USART2EN_MSK
+#define STM32_RCC_APB1ENR1_USART3EN_POS 18U
+#define STM32_RCC_APB1ENR1_USART3EN_MSK \
+	(0x1UL << STM32_RCC_APB1ENR1_USART3EN_POS)
+#define STM32_RCC_APB1ENR1_USART3EN STM32_RCC_APB1ENR1_USART3EN_MSK
+#define STM32_RCC_APB1ENR1_UART4EN_POS 19U
+#define STM32_RCC_APB1ENR1_UART4EN_MSK (0x1UL << STM32_RCC_APB1ENR1_UART4EN_POS)
+#define STM32_RCC_APB1ENR1_UART4EN STM32_RCC_APB1ENR1_UART4EN_MSK
+#define STM32_RCC_APB1ENR1_UART5EN_POS 20U
+#define STM32_RCC_APB1ENR1_UART5EN_MSK (0x1UL << STM32_RCC_APB1ENR1_UART5EN_POS)
+#define STM32_RCC_APB1ENR1_UART5EN STM32_RCC_APB1ENR1_UART5EN_MSK
+#define STM32_RCC_APB1ENR1_I2C1EN_POS 21U
+#define STM32_RCC_APB1ENR1_I2C1EN_MSK (0x1UL << STM32_RCC_APB1ENR1_I2C1EN_POS)
+#define STM32_RCC_APB1ENR1_I2C1EN STM32_RCC_APB1ENR1_I2C1EN_MSK
+#define STM32_RCC_APB1ENR1_I2C2EN_POS 22U
+#define STM32_RCC_APB1ENR1_I2C2EN_MSK (0x1UL << STM32_RCC_APB1ENR1_I2C2EN_POS)
+#define STM32_RCC_APB1ENR1_I2C2EN STM32_RCC_APB1ENR1_I2C2EN_MSK
+#define STM32_RCC_APB1ENR1_I2C3EN_POS 23U
+#define STM32_RCC_APB1ENR1_I2C3EN_MSK (0x1UL << STM32_RCC_APB1ENR1_I2C3EN_POS)
+#define STM32_RCC_APB1ENR1_I2C3EN STM32_RCC_APB1ENR1_I2C3EN_MSK
+#define STM32_RCC_APB1ENR1_CRSEN_POS 24U
+#define STM32_RCC_APB1ENR1_CRSEN_MSK (0x1UL << STM32_RCC_APB1ENR1_CRSEN_POS)
+#define STM32_RCC_APB1ENR1_CRSEN STM32_RCC_APB1ENR1_CRSEN_MSK
+#define STM32_RCC_APB1ENR1_PWREN_POS 28U
+#define STM32_RCC_APB1ENR1_PWREN_MSK (0x1UL << STM32_RCC_APB1ENR1_PWREN_POS)
+#define STM32_RCC_APB1ENR1_PWREN STM32_RCC_APB1ENR1_PWREN_MSK
+#define STM32_RCC_APB1ENR1_DAC1EN_POS 29U
+#define STM32_RCC_APB1ENR1_DAC1EN_MSK (0x1UL << STM32_RCC_APB1ENR1_DAC1EN_POS)
+#define STM32_RCC_APB1ENR1_DAC1EN STM32_RCC_APB1ENR1_DAC1EN_MSK
+#define STM32_RCC_APB1ENR1_OPAMPEN_POS 30U
+#define STM32_RCC_APB1ENR1_OPAMPEN_MSK (0x1UL << STM32_RCC_APB1ENR1_OPAMPEN_POS)
+#define STM32_RCC_APB1ENR1_OPAMPEN STM32_RCC_APB1ENR1_OPAMPEN_MSK
+#define STM32_RCC_APB1ENR1_LPTIM1EN_POS 31U
+#define STM32_RCC_APB1ENR1_LPTIM1EN_MSK \
+	(0x1UL << STM32_RCC_APB1ENR1_LPTIM1EN_POS)
+#define STM32_RCC_APB1ENR1_LPTIM1EN STM32_RCC_APB1ENR1_LPTIM1EN_MSK
+
+/************  BIT DEFINITION FOR STM32_RCC_APB1RSTR2 REGISTER  **************/
+#define STM32_RCC_APB1ENR2_LPUART1EN_POS 0U
+#define STM32_RCC_APB1ENR2_LPUART1EN_MSK \
+	(0x1UL << STM32_RCC_APB1ENR2_LPUART1EN_POS)
+#define STM32_RCC_APB1ENR2_LPUART1EN STM32_RCC_APB1ENR2_LPUART1EN_MSK
+#define STM32_RCC_APB1ENR2_I2C4EN_POS 1U
+#define STM32_RCC_APB1ENR2_I2C4EN_MSK (0x1UL << STM32_RCC_APB1ENR2_I2C4EN_POS)
+#define STM32_RCC_APB1ENR2_I2C4EN STM32_RCC_APB1ENR2_I2C4EN_MSK
+#define STM32_RCC_APB1ENR2_LPTIM2EN_POS 5U
+#define STM32_RCC_APB1ENR2_LPTIM2EN_MSK \
+	(0x1UL << STM32_RCC_APB1ENR2_LPTIM2EN_POS)
+#define STM32_RCC_APB1ENR2_LPTIM2EN STM32_RCC_APB1ENR2_LPTIM2EN_MSK
+#define STM32_RCC_APB1ENR2_LPTIM3EN_POS 6U
+#define STM32_RCC_APB1ENR2_LPTIM3EN_MSK \
+	(0x1UL << STM32_RCC_APB1ENR2_LPTIM3EN_POS)
+#define STM32_RCC_APB1ENR2_LPTIM3EN STM32_RCC_APB1ENR2_LPTIM3EN_MSK
+#define STM32_RCC_APB1ENR2_FDCAN1EN_POS 9U
+#define STM32_RCC_APB1ENR2_FDCAN1EN_MSK \
+	(0x1UL << STM32_RCC_APB1ENR2_FDCAN1EN_POS)
+#define STM32_RCC_APB1ENR2_FDCAN1EN STM32_RCC_APB1ENR2_FDCAN1EN_MSK
+#define STM32_RCC_APB1ENR2_USBFSEN_POS 21U
+#define STM32_RCC_APB1ENR2_USBFSEN_MSK (0x1UL << STM32_RCC_APB1ENR2_USBFSEN_POS)
+#define STM32_RCC_APB1ENR2_USBFSEN STM32_RCC_APB1ENR2_USBFSEN_MSK
+#define STM32_RCC_APB1ENR2_UCPD1EN_POS 23U
+#define STM32_RCC_APB1ENR2_UCPD1EN_MSK (0x1UL << STM32_RCC_APB1ENR2_UCPD1EN_POS)
+#define STM32_RCC_APB1ENR2_UCPD1EN STM32_RCC_APB1ENR2_UCPD1EN_MSK
+
+/**************  BIT DEFINITION FOR STM32_RCC_APB2ENR REGISTER  ***************/
+#define STM32_RCC_APB2ENR_SYSCFGEN_POS 0U
+#define STM32_RCC_APB2ENR_SYSCFGEN_MSK (0x1UL << STM32_RCC_APB2ENR_SYSCFGEN_POS)
+#define STM32_RCC_APB2ENR_SYSCFGEN STM32_RCC_APB2ENR_SYSCFGEN_MSK
+#define STM32_RCC_APB2ENR_TIM1EN_POS 11U
+#define STM32_RCC_APB2ENR_TIM1EN_MSK (0x1UL << STM32_RCC_APB2ENR_TIM1EN_POS)
+#define STM32_RCC_APB2ENR_TIM1EN STM32_RCC_APB2ENR_TIM1EN_MSK
+#define STM32_RCC_APB2ENR_SPI1EN_POS 12U
+#define STM32_RCC_APB2ENR_SPI1EN_MSK (0x1UL << STM32_RCC_APB2ENR_SPI1EN_POS)
+#define STM32_RCC_APB2ENR_SPI1EN STM32_RCC_APB2ENR_SPI1EN_MSK
+#define STM32_RCC_APB2ENR_TIM8EN_POS 13U
+#define STM32_RCC_APB2ENR_TIM8EN_MSK (0x1UL << STM32_RCC_APB2ENR_TIM8EN_POS)
+#define STM32_RCC_APB2ENR_TIM8EN STM32_RCC_APB2ENR_TIM8EN_MSK
+#define STM32_RCC_APB2ENR_USART1EN_POS 14U
+#define STM32_RCC_APB2ENR_USART1EN_MSK (0x1UL << STM32_RCC_APB2ENR_USART1EN_POS)
+#define STM32_RCC_APB2ENR_USART1EN STM32_RCC_APB2ENR_USART1EN_MSK
+#define STM32_RCC_APB2ENR_TIM15EN_POS 16U
+#define STM32_RCC_APB2ENR_TIM15EN_MSK (0x1UL << STM32_RCC_APB2ENR_TIM15EN_POS)
+#define STM32_RCC_APB2ENR_TIM15EN STM32_RCC_APB2ENR_TIM15EN_MSK
+#define STM32_RCC_APB2ENR_TIM16EN_POS 17U
+#define STM32_RCC_APB2ENR_TIM16EN_MSK (0x1UL << STM32_RCC_APB2ENR_TIM16EN_POS)
+#define STM32_RCC_APB2ENR_TIM16EN STM32_RCC_APB2ENR_TIM16EN_MSK
+#define STM32_RCC_APB2ENR_TIM17EN_POS 18U
+#define STM32_RCC_APB2ENR_TIM17EN_MSK (0x1UL << STM32_RCC_APB2ENR_TIM17EN_POS)
+#define STM32_RCC_APB2ENR_TIM17EN STM32_RCC_APB2ENR_TIM17EN_MSK
+#define STM32_RCC_APB2ENR_SAI1EN_POS 21U
+#define STM32_RCC_APB2ENR_SAI1EN_MSK (0x1UL << STM32_RCC_APB2ENR_SAI1EN_POS)
+#define STM32_RCC_APB2ENR_SAI1EN STM32_RCC_APB2ENR_SAI1EN_MSK
+#define STM32_RCC_APB2ENR_SAI2EN_POS 22U
+#define STM32_RCC_APB2ENR_SAI2EN_MSK (0x1UL << STM32_RCC_APB2ENR_SAI2EN_POS)
+#define STM32_RCC_APB2ENR_SAI2EN STM32_RCC_APB2ENR_SAI2EN_MSK
+#define STM32_RCC_APB2ENR_DFSDM1EN_POS 24U
+#define STM32_RCC_APB2ENR_DFSDM1EN_MSK (0x1UL << STM32_RCC_APB2ENR_DFSDM1EN_POS)
+#define STM32_RCC_APB2ENR_DFSDM1EN STM32_RCC_APB2ENR_DFSDM1EN_MSK
+
+/************  BIT DEFINITION FOR STM32_RCC_AHB1SMENR REGISTER  ***************/
+#define STM32_RCC_AHB1SMENR_DMA1SMEN_POS 0U
+#define STM32_RCC_AHB1SMENR_DMA1SMEN_MSK \
+	(0x1UL << STM32_RCC_AHB1SMENR_DMA1SMEN_POS)
+#define STM32_RCC_AHB1SMENR_DMA1SMEN STM32_RCC_AHB1SMENR_DMA1SMEN_MSK
+#define STM32_RCC_AHB1SMENR_DMA2SMEN_POS 1U
+#define STM32_RCC_AHB1SMENR_DMA2SMEN_MSK \
+	(0x1UL << STM32_RCC_AHB1SMENR_DMA2SMEN_POS)
+#define STM32_RCC_AHB1SMENR_DMA2SMEN STM32_RCC_AHB1SMENR_DMA2SMEN_MSK
+#define STM32_RCC_AHB1SMENR_DMAMUX1SMEN_POS 2U
+#define STM32_RCC_AHB1SMENR_DMAMUX1SMEN_MSK \
+	(0x1UL << STM32_RCC_AHB1SMENR_DMAMUX1SMEN_POS)
+#define STM32_RCC_AHB1SMENR_DMAMUX1SMEN STM32_RCC_AHB1SMENR_DMAMUX1SMEN_MSK
+#define STM32_RCC_AHB1SMENR_FLASHSMEN_POS 8U
+#define STM32_RCC_AHB1SMENR_FLASHSMEN_MSK \
+	(0x1UL << STM32_RCC_AHB1SMENR_FLASHSMEN_POS)
+#define STM32_RCC_AHB1SMENR_FLASHSMEN STM32_RCC_AHB1SMENR_FLASHSMEN_MSK
+#define STM32_RCC_AHB1SMENR_SRAM1SMEN_POS 9U
+#define STM32_RCC_AHB1SMENR_SRAM1SMEN_MSK \
+	(0x1UL << STM32_RCC_AHB1SMENR_SRAM1SMEN_POS)
+#define STM32_RCC_AHB1SMENR_SRAM1SMEN STM32_RCC_AHB1SMENR_SRAM1SMEN_MSK
+#define STM32_RCC_AHB1SMENR_CRCSMEN_POS 12U
+#define STM32_RCC_AHB1SMENR_CRCSMEN_MSK \
+	(0x1UL << STM32_RCC_AHB1SMENR_CRCSMEN_POS)
+#define STM32_RCC_AHB1SMENR_CRCSMEN STM32_RCC_AHB1SMENR_CRCSMEN_MSK
+#define STM32_RCC_AHB1SMENR_TSCSMEN_POS 16U
+#define STM32_RCC_AHB1SMENR_TSCSMEN_MSK \
+	(0x1UL << STM32_RCC_AHB1SMENR_TSCSMEN_POS)
+#define STM32_RCC_AHB1SMENR_TSCSMEN STM32_RCC_AHB1SMENR_TSCSMEN_MSK
+#define STM32_RCC_AHB1SMENR_GTZCSMEN_POS 22U
+#define STM32_RCC_AHB1SMENR_GTZCSMEN_MSK \
+	(0x1UL << STM32_RCC_AHB1SMENR_GTZCSMEN_POS)
+#define STM32_RCC_AHB1SMENR_GTZCSMEN STM32_RCC_AHB1SMENR_GTZCSMEN_MSK
+#define STM32_RCC_AHB1SMENR_ICACHESMEN_POS 23U
+#define STM32_RCC_AHB1SMENR_ICACHESMEN_MSK \
+	(0x1UL << STM32_RCC_AHB1SMENR_ICACHESMEN_POS)
+#define STM32_RCC_AHB1SMENR_ICACHESMEN STM32_RCC_AHB1SMENR_ICACHESMEN_MSK
+
+/**************  BIT DEFINITION FOR STM32_RCC_AHB2SMENR REGISTER  *************/
+#define STM32_RCC_AHB2SMENR_GPIOASMEN_POS 0U
+#define STM32_RCC_AHB2SMENR_GPIOASMEN_MSK \
+	(0x1UL << STM32_RCC_AHB2SMENR_GPIOASMEN_POS)
+#define STM32_RCC_AHB2SMENR_GPIOASMEN STM32_RCC_AHB2SMENR_GPIOASMEN_MSK
+#define STM32_RCC_AHB2SMENR_GPIOBSMEN_POS 1U
+#define STM32_RCC_AHB2SMENR_GPIOBSMEN_MSK \
+	(0x1UL << STM32_RCC_AHB2SMENR_GPIOBSMEN_POS)
+#define STM32_RCC_AHB2SMENR_GPIOBSMEN STM32_RCC_AHB2SMENR_GPIOBSMEN_MSK
+#define STM32_RCC_AHB2SMENR_GPIOCSMEN_POS 2U
+#define STM32_RCC_AHB2SMENR_GPIOCSMEN_MSK \
+	(0x1UL << STM32_RCC_AHB2SMENR_GPIOCSMEN_POS)
+#define STM32_RCC_AHB2SMENR_GPIOCSMEN STM32_RCC_AHB2SMENR_GPIOCSMEN_MSK
+#define STM32_RCC_AHB2SMENR_GPIODSMEN_POS 3U
+#define STM32_RCC_AHB2SMENR_GPIODSMEN_MSK \
+	(0x1UL << STM32_RCC_AHB2SMENR_GPIODSMEN_POS)
+#define STM32_RCC_AHB2SMENR_GPIODSMEN STM32_RCC_AHB2SMENR_GPIODSMEN_MSK
+#define STM32_RCC_AHB2SMENR_GPIOESMEN_POS 4U
+#define STM32_RCC_AHB2SMENR_GPIOESMEN_MSK \
+	(0x1UL << STM32_RCC_AHB2SMENR_GPIOESMEN_POS)
+#define STM32_RCC_AHB2SMENR_GPIOESMEN STM32_RCC_AHB2SMENR_GPIOESMEN_MSK
+#define STM32_RCC_AHB2SMENR_GPIOFSMEN_POS 5U
+#define STM32_RCC_AHB2SMENR_GPIOFSMEN_MSK \
+	(0x1UL << STM32_RCC_AHB2SMENR_GPIOFSMEN_POS)
+#define STM32_RCC_AHB2SMENR_GPIOFSMEN STM32_RCC_AHB2SMENR_GPIOFSMEN_MSK
+#define STM32_RCC_AHB2SMENR_GPIOGSMEN_POS 6U
+#define STM32_RCC_AHB2SMENR_GPIOGSMEN_MSK \
+	(0x1UL << STM32_RCC_AHB2SMENR_GPIOGSMEN_POS)
+#define STM32_RCC_AHB2SMENR_GPIOGSMEN STM32_RCC_AHB2SMENR_GPIOGSMEN_MSK
+#define STM32_RCC_AHB2SMENR_GPIOHSMEN_POS 7U
+#define STM32_RCC_AHB2SMENR_GPIOHSMEN_MSK \
+	(0x1UL << STM32_RCC_AHB2SMENR_GPIOHSMEN_POS)
+#define STM32_RCC_AHB2SMENR_GPIOHSMEN STM32_RCC_AHB2SMENR_GPIOHSMEN_MSK
+#define STM32_RCC_AHB2SMENR_SRAM2SMEN_POS 9U
+#define STM32_RCC_AHB2SMENR_SRAM2SMEN_MSK \
+	(0x1UL << STM32_RCC_AHB2SMENR_SRAM2SMEN_POS)
+#define STM32_RCC_AHB2SMENR_SRAM2SMEN STM32_RCC_AHB2SMENR_SRAM2SMEN_MSK
+#define STM32_RCC_AHB2SMENR_ADCSMEN_POS 13U
+#define STM32_RCC_AHB2SMENR_ADCSMEN_MSK \
+	(0x1UL << STM32_RCC_AHB2SMENR_ADCSMEN_POS)
+#define STM32_RCC_AHB2SMENR_ADCSMEN STM32_RCC_AHB2SMENR_ADCSMEN_MSK
+#define STM32_RCC_AHB2SMENR_AESSMEN_POS 16U
+#define STM32_RCC_AHB2SMENR_AESSMEN_MSK \
+	(0x1UL << STM32_RCC_AHB2SMENR_AESSMEN_POS)
+#define STM32_RCC_AHB2SMENR_AESSMEN STM32_RCC_AHB2SMENR_AESSMEN_MSK
+#define STM32_RCC_AHB2SMENR_HASHSMEN_POS 17U
+#define STM32_RCC_AHB2SMENR_HASHSMEN_MSK \
+	(0x1UL << STM32_RCC_AHB2SMENR_HASHSMEN_POS)
+#define STM32_RCC_AHB2SMENR_HASHSMEN STM32_RCC_AHB2SMENR_HASHSMEN_MSK
+#define STM32_RCC_AHB2SMENR_RNGSMEN_POS 18U
+#define STM32_RCC_AHB2SMENR_RNGSMEN_MSK \
+	(0x1UL << STM32_RCC_AHB2SMENR_RNGSMEN_POS)
+#define STM32_RCC_AHB2SMENR_RNGSMEN STM32_RCC_AHB2SMENR_RNGSMEN_MSK
+#define STM32_RCC_AHB2SMENR_PKASMEN_POS 19U
+#define STM32_RCC_AHB2SMENR_PKASMEN_MSK \
+	(0x1UL << STM32_RCC_AHB2SMENR_PKASMEN_POS)
+#define STM32_RCC_AHB2SMENR_PKASMEN STM32_RCC_AHB2SMENR_PKASMEN_MSK
+#define STM32_RCC_AHB2SMENR_OTFDEC1SMEN_POS 21U
+#define STM32_RCC_AHB2SMENR_OTFDEC1SMEN_MSK \
+	(0x1UL << STM32_RCC_AHB2SMENR_OTFDEC1SMEN_POS)
+#define STM32_RCC_AHB2SMENR_OTFDEC1SMEN STM32_RCC_AHB2SMENR_OTFDEC1SMEN_MSK
+#define STM32_RCC_AHB2SMENR_SDMMC1SMEN_POS 22U
+#define STM32_RCC_AHB2SMENR_SDMMC1SMEN_MSK \
+	(0x1UL << STM32_RCC_AHB2SMENR_SDMMC1SMEN_POS)
+#define STM32_RCC_AHB2SMENR_SDMMC1SMEN STM32_RCC_AHB2SMENR_SDMMC1SMEN_MSK
+
+/**************  BIT DEFINITION FOR STM32_RCC_AHB3SMENR REGISTER  *************/
+#define STM32_RCC_AHB3SMENR_FMCSMEN_POS 0U
+#define STM32_RCC_AHB3SMENR_FMCSMEN_MSK \
+	(0x1UL << STM32_RCC_AHB3SMENR_FMCSMEN_POS)
+#define STM32_RCC_AHB3SMENR_FMCSMEN STM32_RCC_AHB3SMENR_FMCSMEN_MSK
+#define STM32_RCC_AHB3SMENR_QSPISMEN_POS 8U
+#define STM32_RCC_AHB3SMENR_QSPISMEN_MSK \
+	(0x1UL << STM32_RCC_AHB3SMENR_QSPISMEN_POS)
+#define STM32_RCC_AHB3SMENR_QSPISMEN STM32_RCC_AHB3SMENR_QSPISMEN_MSK
+
+/*************  BIT DEFINITION FOR STM32_RCC_APB1SMENR1 REGISTER  *************/
+#define STM32_RCC_APB1SMENR1_TIM2SMEN_POS 0U
+#define STM32_RCC_APB1SMENR1_TIM2SMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR1_TIM2SMEN_POS)
+#define STM32_RCC_APB1SMENR1_TIM2SMEN STM32_RCC_APB1SMENR1_TIM2SMEN_MSK
+#define STM32_RCC_APB1SMENR1_TIM3SMEN_POS 1U
+#define STM32_RCC_APB1SMENR1_TIM3SMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR1_TIM3SMEN_POS)
+#define STM32_RCC_APB1SMENR1_TIM3SMEN STM32_RCC_APB1SMENR1_TIM3SMEN_MSK
+#define STM32_RCC_APB1SMENR1_TIM4SMEN_POS 2U
+#define STM32_RCC_APB1SMENR1_TIM4SMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR1_TIM4SMEN_POS)
+#define STM32_RCC_APB1SMENR1_TIM4SMEN STM32_RCC_APB1SMENR1_TIM4SMEN_MSK
+#define STM32_RCC_APB1SMENR1_TIM5SMEN_POS 3U
+#define STM32_RCC_APB1SMENR1_TIM5SMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR1_TIM5SMEN_POS)
+#define STM32_RCC_APB1SMENR1_TIM5SMEN STM32_RCC_APB1SMENR1_TIM5SMEN_MSK
+#define STM32_RCC_APB1SMENR1_TIM6SMEN_POS 4U
+#define STM32_RCC_APB1SMENR1_TIM6SMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR1_TIM6SMEN_POS)
+#define STM32_RCC_APB1SMENR1_TIM6SMEN STM32_RCC_APB1SMENR1_TIM6SMEN_MSK
+#define STM32_RCC_APB1SMENR1_TIM7SMEN_POS 5U
+#define STM32_RCC_APB1SMENR1_TIM7SMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR1_TIM7SMEN_POS)
+#define STM32_RCC_APB1SMENR1_TIM7SMEN STM32_RCC_APB1SMENR1_TIM7SMEN_MSK
+#define STM32_RCC_APB1SMENR1_RTCAPBSMEN_POS 10U
+#define STM32_RCC_APB1SMENR1_RTCAPBSMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR1_RTCAPBSMEN_POS)
+#define STM32_RCC_APB1SMENR1_RTCAPBSMEN STM32_RCC_APB1SMENR1_RTCAPBSMEN_MSK
+#define STM32_RCC_APB1SMENR1_WWDGSMEN_POS 11U
+#define STM32_RCC_APB1SMENR1_WWDGSMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR1_WWDGSMEN_POS)
+#define STM32_RCC_APB1SMENR1_WWDGSMEN STM32_RCC_APB1SMENR1_WWDGSMEN_MSK
+#define STM32_RCC_APB1SMENR1_SPI2SMEN_POS 14U
+#define STM32_RCC_APB1SMENR1_SPI2SMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR1_SPI2SMEN_POS)
+#define STM32_RCC_APB1SMENR1_SPI2SMEN STM32_RCC_APB1SMENR1_SPI2SMEN_MSK
+#define STM32_RCC_APB1SMENR1_SPI3SMEN_POS 15U
+#define STM32_RCC_APB1SMENR1_SPI3SMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR1_SPI3SMEN_POS)
+#define STM32_RCC_APB1SMENR1_SPI3SMEN STM32_RCC_APB1SMENR1_SPI3SMEN_MSK
+#define STM32_RCC_APB1SMENR1_USART2SMEN_POS 17U
+#define STM32_RCC_APB1SMENR1_USART2SMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR1_USART2SMEN_POS)
+#define STM32_RCC_APB1SMENR1_USART2SMEN STM32_RCC_APB1SMENR1_USART2SMEN_MSK
+#define STM32_RCC_APB1SMENR1_USART3SMEN_POS 18U
+#define STM32_RCC_APB1SMENR1_USART3SMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR1_USART3SMEN_POS)
+#define STM32_RCC_APB1SMENR1_USART3SMEN STM32_RCC_APB1SMENR1_USART3SMEN_MSK
+#define STM32_RCC_APB1SMENR1_USART4SMEN_POS 19U
+#define STM32_RCC_APB1SMENR1_USART4SMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR1_USART4SMEN_POS)
+#define STM32_RCC_APB1SMENR1_USART4SMEN STM32_RCC_APB1SMENR1_USART4SMEN_MSK
+#define STM32_RCC_APB1SMENR1_USART5SMEN_POS 20U
+#define STM32_RCC_APB1SMENR1_USART5SMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR1_USART5SMEN_POS)
+#define STM32_RCC_APB1SMENR1_USART5SMEN STM32_RCC_APB1SMENR1_USART5SMEN_MSK
+#define STM32_RCC_APB1SMENR1_I2C1SMEN_POS 21U
+#define STM32_RCC_APB1SMENR1_I2C1SMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR1_I2C1SMEN_POS)
+#define STM32_RCC_APB1SMENR1_I2C1SMEN STM32_RCC_APB1SMENR1_I2C1SMEN_MSK
+#define STM32_RCC_APB1SMENR1_I2C2SMEN_POS 22U
+#define STM32_RCC_APB1SMENR1_I2C2SMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR1_I2C2SMEN_POS)
+#define STM32_RCC_APB1SMENR1_I2C2SMEN STM32_RCC_APB1SMENR1_I2C2SMEN_MSK
+#define STM32_RCC_APB1SMENR1_I2C3SMEN_POS 23U
+#define STM32_RCC_APB1SMENR1_I2C3SMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR1_I2C3SMEN_POS)
+#define STM32_RCC_APB1SMENR1_I2C3SMEN STM32_RCC_APB1SMENR1_I2C3SMEN_MSK
+#define STM32_RCC_APB1SMENR1_CRSSMEN_POS 24U
+#define STM32_RCC_APB1SMENR1_CRSSMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR1_CRSSMEN_POS)
+#define STM32_RCC_APB1SMENR1_CRSSMEN STM32_RCC_APB1SMENR1_CRSSMEN_MSK
+#define STM32_RCC_APB1SMENR1_PWRSMEN_POS 28U
+#define STM32_RCC_APB1SMENR1_PWRSMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR1_PWRSMEN_POS)
+#define STM32_RCC_APB1SMENR1_PWRSMEN STM32_RCC_APB1SMENR1_PWRSMEN_MSK
+#define STM32_RCC_APB1SMENR1_DAC1SMEN_POS 29U
+#define STM32_RCC_APB1SMENR1_DAC1SMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR1_DAC1SMEN_POS)
+#define STM32_RCC_APB1SMENR1_DAC1SMEN STM32_RCC_APB1SMENR1_DAC1SMEN_MSK
+#define STM32_RCC_APB1SMENR1_OPAMPSMEN_POS 30U
+#define STM32_RCC_APB1SMENR1_OPAMPSMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR1_OPAMPSMEN_POS)
+#define STM32_RCC_APB1SMENR1_OPAMPSMEN STM32_RCC_APB1SMENR1_OPAMPSMEN_MSK
+#define STM32_RCC_APB1SMENR1_LPTIM1SMEN_POS 31U
+#define STM32_RCC_APB1SMENR1_LPTIM1SMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR1_LPTIM1SMEN_POS)
+#define STM32_RCC_APB1SMENR1_LPTIM1SMEN STM32_RCC_APB1SMENR1_LPTIM1SMEN_MSK
+
+/*************  BIT DEFINITION FOR STM32_RCC_APB1SMENR2 REGISTER  *************/
+#define STM32_RCC_APB1SMENR2_LPUART1SMEN_POS 0U
+#define STM32_RCC_APB1SMENR2_LPUART1SMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR2_LPUART1SMEN_POS)
+#define STM32_RCC_APB1SMENR2_LPUART1SMEN STM32_RCC_APB1SMENR2_LPUART1SMEN_MSK
+#define STM32_RCC_APB1SMENR2_I2C4SMEN_POS 1U
+#define STM32_RCC_APB1SMENR2_I2C4SMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR2_I2C4SMEN_POS)
+#define STM32_RCC_APB1SMENR2_I2C4SMEN STM32_RCC_APB1SMENR2_I2C4SMEN_MSK
+#define STM32_RCC_APB1SMENR2_LPTIM2SMEN_POS 5U
+#define STM32_RCC_APB1SMENR2_LPTIM2SMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR2_LPTIM2SMEN_POS)
+#define STM32_RCC_APB1SMENR2_LPTIM2SMEN STM32_RCC_APB1SMENR2_LPTIM2SMEN_MSK
+#define STM32_RCC_APB1SMENR2_LPTIM3SMEN_POS 6U
+#define STM32_RCC_APB1SMENR2_LPTIM3SMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR2_LPTIM3SMEN_POS)
+#define STM32_RCC_APB1SMENR2_LPTIM3SMEN STM32_RCC_APB1SMENR2_LPTIM3SMEN_MSK
+#define STM32_RCC_APB1SMENR2_FDCAN1SMEN_POS 9U
+#define STM32_RCC_APB1SMENR2_FDCAN1SMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR2_FDCAN1SMEN_POS)
+#define STM32_RCC_APB1SMENR2_FDCAN1SMEN STM32_RCC_APB1SMENR2_FDCAN1SMEN_MSK
+#define STM32_RCC_APB1SMENR2_USBFSSMEN_POS 21U
+#define STM32_RCC_APB1SMENR2_USBFSSMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR2_USBFSSMEN_POS)
+#define STM32_RCC_APB1SMENR2_USBFSSMEN STM32_RCC_APB1SMENR2_USBFSSMEN_MSK
+#define STM32_RCC_APB1SMENR2_UCPD1SMEN_POS 23U
+#define STM32_RCC_APB1SMENR2_UCPD1SMEN_MSK \
+	(0x1UL << STM32_RCC_APB1SMENR2_UCPD1SMEN_POS)
+#define STM32_RCC_APB1SMENR2_UCPD1SMEN STM32_RCC_APB1SMENR2_UCPD1SMEN_MSK
+
+/************  BIT DEFINITION FOR STM32_RCC_APB2SMENR REGISTER  *************/
+#define STM32_RCC_APB2SMENR_SYSCFGSMEN_POS 0U
+#define STM32_RCC_APB2SMENR_SYSCFGSMEN_MSK \
+	(0x1UL << STM32_RCC_APB2SMENR_SYSCFGSMEN_POS)
+#define STM32_RCC_APB2SMENR_SYSCFGSMEN STM32_RCC_APB2SMENR_SYSCFGSMEN_MSK
+#define STM32_RCC_APB2SMENR_TIM1SMEN_POS 11U
+#define STM32_RCC_APB2SMENR_TIM1SMEN_MSK \
+	(0x1UL << STM32_RCC_APB2SMENR_TIM1SMEN_POS)
+#define STM32_RCC_APB2SMENR_TIM1SMEN STM32_RCC_APB2SMENR_TIM1SMEN_MSK
+#define STM32_RCC_APB2SMENR_SPI1SMEN_POS 12U
+#define STM32_RCC_APB2SMENR_SPI1SMEN_MSK \
+	(0x1UL << STM32_RCC_APB2SMENR_SPI1SMEN_POS)
+#define STM32_RCC_APB2SMENR_SPI1SMEN STM32_RCC_APB2SMENR_SPI1SMEN_MSK
+#define STM32_RCC_APB2SMENR_TIM8SMEN_POS 13U
+#define STM32_RCC_APB2SMENR_TIM8SMEN_MSK \
+	(0x1UL << STM32_RCC_APB2SMENR_TIM8SMEN_POS)
+#define STM32_RCC_APB2SMENR_TIM8SMEN STM32_RCC_APB2SMENR_TIM8SMEN_MSK
+#define STM32_RCC_APB2SMENR_USART1SMEN_POS 14U
+#define STM32_RCC_APB2SMENR_USART1SMEN_MSK \
+	(0x1UL << STM32_RCC_APB2SMENR_USART1SMEN_POS)
+#define STM32_RCC_APB2SMENR_USART1SMEN STM32_RCC_APB2SMENR_USART1SMEN_MSK
+#define STM32_RCC_APB2SMENR_TIM15SMEN_POS 16U
+#define STM32_RCC_APB2SMENR_TIM15SMEN_MSK \
+	(0x1UL << STM32_RCC_APB2SMENR_TIM15SMEN_POS)
+#define STM32_RCC_APB2SMENR_TIM15SMEN STM32_RCC_APB2SMENR_TIM15SMEN_MSK
+#define STM32_RCC_APB2SMENR_TIM16SMEN_POS 17U
+#define STM32_RCC_APB2SMENR_TIM16SMEN_MSK \
+	(0x1UL << STM32_RCC_APB2SMENR_TIM16SMEN_POS)
+#define STM32_RCC_APB2SMENR_TIM16SMEN STM32_RCC_APB2SMENR_TIM16SMEN_MSK
+#define STM32_RCC_APB2SMENR_TIM17SMEN_POS 18U
+#define STM32_RCC_APB2SMENR_TIM17SMEN_MSK \
+	(0x1UL << STM32_RCC_APB2SMENR_TIM17SMEN_POS)
+#define STM32_RCC_APB2SMENR_TIM17SMEN STM32_RCC_APB2SMENR_TIM17SMEN_MSK
+#define STM32_RCC_APB2SMENR_SAI1SMEN_POS 21U
+#define STM32_RCC_APB2SMENR_SAI1SMEN_MSK \
+	(0x1UL << STM32_RCC_APB2SMENR_SAI1SMEN_POS)
+#define STM32_RCC_APB2SMENR_SAI1SMEN STM32_RCC_APB2SMENR_SAI1SMEN_MSK
+#define STM32_RCC_APB2SMENR_SAI2SMEN_POS 22U
+#define STM32_RCC_APB2SMENR_SAI2SMEN_MSK \
+	(0x1UL << STM32_RCC_APB2SMENR_SAI2SMEN_POS)
+#define STM32_RCC_APB2SMENR_SAI2SMEN STM32_RCC_APB2SMENR_SAI2SMEN_MSK
+#define STM32_RCC_APB2SMENR_DFSDM1SMEN_POS 24U
+#define STM32_RCC_APB2SMENR_DFSDM1SMEN_MSK \
+	(0x1UL << STM32_RCC_APB2SMENR_DFSDM1SMEN_POS)
+#define STM32_RCC_APB2SMENR_DFSDM1SMEN STM32_RCC_APB2SMENR_DFSDM1SMEN_MSK
+
+/*************  BIT DEFINITION FOR STM32_RCC_CCIPR1 REGISTER  *****************/
+#define STM32_RCC_CCIPR1_USART1SEL_POS 0U
+#define STM32_RCC_CCIPR1_USART1SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART1SEL_POS)
+#define STM32_RCC_CCIPR1_USART1SEL STM32_RCC_CCIPR_USART1SEL_MSK
+#define STM32_RCC_CCIPR1_USART1SEL_0 (0x1UL << STM32_RCC_CCIPR_USART1SEL_POS)
+#define STM32_RCC_CCIPR1_USART1SEL_1 (0x2UL << STM32_RCC_CCIPR_USART1SEL_POS)
+
+#define STM32_RCC_CCIPR1_USART2SEL_POS 2U
+#define STM32_RCC_CCIPR1_USART2SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART2SEL_POS)
+#define STM32_RCC_CCIPR1_USART2SEL STM32_RCC_CCIPR_USART2SEL_MSK
+#define STM32_RCC_CCIPR1_USART2SEL_0 (0x1UL << STM32_RCC_CCIPR_USART2SEL_POS)
+#define STM32_RCC_CCIPR1_USART2SEL_1 (0x2UL << STM32_RCC_CCIPR_USART2SEL_POS)
+
+#define STM32_RCC_CCIPR1_USART3SEL_POS 4U
+#define STM32_RCC_CCIPR1_USART3SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART3SEL_POS)
+#define STM32_RCC_CCIPR1_USART3SEL STM32_RCC_CCIPR_USART3SEL_MSK
+#define STM32_RCC_CCIPR1_USART3SEL_0 (0x1UL << STM32_RCC_CCIPR_USART3SEL_POS)
+#define STM32_RCC_CCIPR1_USART3SEL_1 (0x2UL << STM32_RCC_CCIPR_USART3SEL_POS)
+
+#define STM32_RCC_CCIPR1_USART4SEL_POS 6U
+#define STM32_RCC_CCIPR1_USART4SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART4SEL_POS)
+#define STM32_RCC_CCIPR1_USART4SEL STM32_RCC_CCIPR_USART4SEL_MSK
+#define STM32_RCC_CCIPR1_USART4SEL_0 (0x1UL << STM32_RCC_CCIPR_USART4SEL_POS)
+#define STM32_RCC_CCIPR1_USART4SEL_1 (0x2UL << STM32_RCC_CCIPR_USART4SEL_POS)
+
+#define STM32_RCC_CCIPR1_USART5SEL_POS 8U
+#define STM32_RCC_CCIPR1_USART5SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART5SEL_POS)
+#define STM32_RCC_CCIPR1_USART5SEL STM32_RCC_CCIPR_USART5SEL_MSK
+#define STM32_RCC_CCIPR1_USART5SEL_0 (0x1UL << STM32_RCC_CCIPR_USART5SEL_POS)
+#define STM32_RCC_CCIPR1_USART5SEL_1 (0x2UL << STM32_RCC_CCIPR_USART5SEL_POS)
+
+#define STM32_RCC_CCIPR1_LPUART1SEL_POS 10U
+#define STM32_RCC_CCIPR1_LPUART1SEL_MSK \
+	(0x3UL << STM32_RCC_CCIPR_LPUART1SEL_POS)
+#define STM32_RCC_CCIPR1_LPUART1SEL STM32_RCC_CCIPR_LPUART1SEL_MSK
+#define STM32_RCC_CCIPR1_LPUART1SEL_0 (0x1UL << STM32_RCC_CCIPR_LPUART1SEL_POS)
+#define STM32_RCC_CCIPR1_LPUART1SEL_1 (0x2UL << STM32_RCC_CCIPR_LPUART1SEL_POS)
+
+#define STM32_RCC_CCIPR1_I2C1SEL_POS 12U
+#define STM32_RCC_CCIPR1_I2C1SEL_MSK (0x3UL << STM32_RCC_CCIPR_I2C1SEL_POS)
+#define STM32_RCC_CCIPR1_I2C1SEL STM32_RCC_CCIPR_I2C1SEL_MSK
+#define STM32_RCC_CCIPR1_I2C1SEL_0 (0x1UL << STM32_RCC_CCIPR_I2C1SEL_POS)
+#define STM32_RCC_CCIPR1_I2C1SEL_1 (0x2UL << STM32_RCC_CCIPR_I2C1SEL_POS)
+
+#define STM32_RCC_CCIPR1_I2C2SEL_POS 14U
+#define STM32_RCC_CCIPR1_I2C2SEL_MSK (0x3UL << STM32_RCC_CCIPR_I2C2SEL_POS)
+#define STM32_RCC_CCIPR1_I2C2SEL STM32_RCC_CCIPR_I2C2SEL_MSK
+#define STM32_RCC_CCIPR1_I2C2SEL_0 (0x1UL << STM32_RCC_CCIPR_I2C2SEL_POS)
+#define STM32_RCC_CCIPR1_I2C2SEL_1 (0x2UL << STM32_RCC_CCIPR_I2C2SEL_POS)
+
+#define STM32_RCC_CCIPR1_I2C3SEL_POS 16U
+#define STM32_RCC_CCIPR1_I2C3SEL_MSK (0x3UL << STM32_RCC_CCIPR_I2C3SEL_POS)
+#define STM32_RCC_CCIPR1_I2C3SEL STM32_RCC_CCIPR_I2C3SEL_MSK
+#define STM32_RCC_CCIPR1_I2C3SEL_0 (0x1UL << STM32_RCC_CCIPR_I2C3SEL_POS)
+#define STM32_RCC_CCIPR1_I2C3SEL_1 (0x2UL << STM32_RCC_CCIPR_I2C3SEL_POS)
+
+#define STM32_RCC_CCIPR1_LPTIM1SEL_POS 18U
+#define STM32_RCC_CCIPR1_LPTIM1SEL_MSK (0x3UL << STM32_RCC_CCIPR_LPTIM1SEL_POS)
+#define STM32_RCC_CCIPR1_LPTIM1SEL STM32_RCC_CCIPR_LPTIM1SEL_MSK
+#define STM32_RCC_CCIPR1_LPTIM1SEL_0 (0x1UL << STM32_RCC_CCIPR_LPTIM1SEL_POS)
+#define STM32_RCC_CCIPR1_LPTIM1SEL_1 (0x2UL << STM32_RCC_CCIPR_LPTIM1SEL_POS)
+
+#define STM32_RCC_CCIPR1_LPTIM2SEL_POS 20U
+#define STM32_RCC_CCIPR1_LPTIM2SEL_MSK (0x3UL << STM32_RCC_CCIPR_LPTIM2SEL_POS)
+#define STM32_RCC_CCIPR1_LPTIM2SEL STM32_RCC_CCIPR_LPTIM2SEL_MSK
+#define STM32_RCC_CCIPR1_LPTIM2SEL_0 (0x1UL << STM32_RCC_CCIPR_LPTIM2SEL_POS)
+#define STM32_RCC_CCIPR1_LPTIM2SEL_1 (0x2UL << STM32_RCC_CCIPR_LPTIM2SEL_POS)
+
+#define STM32_RCC_CCIPR1_LPTIM3SEL_POS 22U
+#define STM32_RCC_CCIPR1_LPTIM3SEL_MSK (0x3UL << STM32_RCC_CCIPR_LPTIM3SEL_POS)
+#define STM32_RCC_CCIPR1_LPTIM3SEL STM32_RCC_CCIPR_LPTIM3SEL_MSK
+#define STM32_RCC_CCIPR1_LPTIM3SEL_0 (0x1UL << STM32_RCC_CCIPR_LPTIM3SEL_POS)
+#define STM32_RCC_CCIPR1_LPTIM3SEL_1 (0x2UL << STM32_RCC_CCIPR_LPTIM3SEL_POS)
+
+#define STM32_RCC_CCIPR1_FDCANSEL_POS 24U
+#define STM32_RCC_CCIPR1_FDCANSEL_MSK (0x3UL << STM32_RCC_CCIPR_FDCANSEL_POS)
+#define STM32_RCC_CCIPR1_FDCANSEL STM32_RCC_CCIPR_FDCANSEL_MSK
+#define STM32_RCC_CCIPR1_FDCANSEL_0 (0x1UL << STM32_RCC_CCIPR_FDCANSEL_POS)
+#define STM32_RCC_CCIPR1_FDCANSEL_1 (0x2UL << STM32_RCC_CCIPR_FDCANSEL_POS)
+
+#define STM32_RCC_CCIPR1_CLK48SEL_POS 26U
+#define STM32_RCC_CCIPR1_CLK48SEL_MSK (0x3UL << STM32_RCC_CCIPR_CLK48SEL_POS)
+#define STM32_RCC_CCIPR1_CLK48SEL STM32_RCC_CCIPR_CLK48SEL_MSK
+#define STM32_RCC_CCIPR1_CLK48SEL_0 (0x1UL << STM32_RCC_CCIPR_CLK48SEL_POS)
+#define STM32_RCC_CCIPR1_CLK48SEL_1 (0x2UL << STM32_RCC_CCIPR_CLK48SEL_POS)
+
+#define STM32_RCC_CCIPR_ADCSEL_POS 28U
+#define STM32_RCC_CCIPR_ADCSEL_MSK (0x3UL << STM32_RCC_CCIPR_ADCSEL_POS)
+#define STM32_RCC_CCIPR_ADCSEL STM32_RCC_CCIPR_ADCSEL_MSK
+#define STM32_RCC_CCIPR_ADCSEL_0 (0x1UL << STM32_RCC_CCIPR_ADCSEL_POS)
+#define STM32_RCC_CCIPR_ADCSEL_1 (0x2UL << STM32_RCC_CCIPR_ADCSEL_POS)
+
+/**************  BIT DEFINITION FOR STM32_RCC_BDCR REGISTER  ******************/
+#define STM32_RCC_BDCR_LSEBYP_POS 2U
+#define STM32_RCC_BDCR_LSEBYP_MSK (0x1UL << STM32_RCC_BDCR_LSEBYP_POS)
+#define STM32_RCC_BDCR_LSEBYP STM32_RCC_BDCR_LSEBYP_MSK
+
+#define STM32_RCC_BDCR_LSEDRV_POS 3U
+#define STM32_RCC_BDCR_LSEDRV_MSK (0x3UL << STM32_RCC_BDCR_LSEDRV_POS)
+#define STM32_RCC_BDCR_LSEDRV STM32_RCC_BDCR_LSEDRV_MSK
+#define STM32_RCC_BDCR_LSEDRV_0 (0x1UL << STM32_RCC_BDCR_LSEDRV_POS)
+#define STM32_RCC_BDCR_LSEDRV_1 (0x2UL << STM32_RCC_BDCR_LSEDRV_POS)
+
+#define STM32_RCC_BDCR_LSECSSON_POS 5U
+#define STM32_RCC_BDCR_LSECSSON_MSK (0x1UL << STM32_RCC_BDCR_LSECSSON_POS)
+#define STM32_RCC_BDCR_LSECSSON STM32_RCC_BDCR_LSECSSON_MSK
+#define STM32_RCC_BDCR_LSECSSD_POS 6U
+#define STM32_RCC_BDCR_LSECSSD_MSK (0x1UL << STM32_RCC_BDCR_LSECSSD_POS)
+#define STM32_RCC_BDCR_LSECSSD STM32_RCC_BDCR_LSECSSD_MSK
+#define STM32_RCC_BDCR_LSESYSEN_POS 7U
+#define STM32_RCC_BDCR_LSESYSEN_MSK (0x1UL << STM32_RCC_BDCR_LSESYSEN_POS)
+#define STM32_RCC_BDCR_LSESYSEN STM32_RCC_BDCR_LSESYSEN_MSK
+
+#define STM32_RCC_BDCR_RTCSEL_POS 8U
+#define STM32_RCC_BDCR_RTCSEL_MSK (0x3UL << STM32_RCC_BDCR_RTCSEL_POS)
+#define STM32_RCC_BDCR_RTCSEL STM32_RCC_BDCR_RTCSEL_MSK
+#define STM32_RCC_BDCR_RTCSEL_0 (0x1UL << STM32_RCC_BDCR_RTCSEL_POS)
+#define STM32_RCC_BDCR_RTCSEL_1 (0x2UL << STM32_RCC_BDCR_RTCSEL_POS)
+
+#define STM32_RCC_BDCR_LSESYSRDY_POS 11U
+#define STM32_RCC_BDCR_LSESYSRDY_MSK (0x1UL << STM32_RCC_BDCR_LSESYSRDY_POS)
+#define STM32_RCC_BDCR_LSESYSRDY STM32_RCC_BDCR_LSESYSRDY_MSK
+#define STM32_RCC_BDCR_LSCOEN_POS 24U
+#define STM32_RCC_BDCR_LSCOEN_MSK (0x1UL << STM32_RCC_BDCR_LSCOEN_POS)
+#define STM32_RCC_BDCR_LSCOEN STM32_RCC_BDCR_LSCOEN_MSK
+#define STM32_RCC_BDCR_LSCOSEL_POS 25U
+#define STM32_RCC_BDCR_LSCOSEL_MSK (0x1UL << STM32_RCC_BDCR_LSCOSEL_POS)
+#define STM32_RCC_BDCR_LSCOSEL STM32_RCC_BDCR_LSCOSEL_MSK
+
+/**************  BIT DEFINITION FOR STM32_RCC_CSR REGISTER  *******************/
+#define STM32_RCC_CSR_LSION_POS 0U
+#define STM32_RCC_CSR_LSION_MSK (0x1UL << STM32_RCC_CSR_LSION_POS)
+#define STM32_RCC_CSR_LSION STM32_RCC_CSR_LSION_MSK
+#define STM32_RCC_CSR_LSIRDY_POS 1U
+#define STM32_RCC_CSR_LSIRDY_MSK (0x1UL << STM32_RCC_CSR_LSIRDY_POS)
+#define STM32_RCC_CSR_LSIRDY STM32_RCC_CSR_LSIRDY_MSK
+#define STM32_RCC_CSR_LSIPRE_POS 4U
+#define STM32_RCC_CSR_LSIPRE_MSK (0x1UL << STM32_RCC_CSR_LSIPRE_POS)
+#define STM32_RCC_CSR_LSIPRE STM32_RCC_CSR_LSIPRE_MSK
+
+#define STM32_RCC_CSR_MSISRANGE_POS 8U
+#define STM32_RCC_CSR_MSISRANGE_MSK (0xFUL << STM32_RCC_CSR_MSISRANGE_POS)
+#define STM32_RCC_CSR_MSISRANGE STM32_RCC_CSR_MSISRANGE_MSK
+#define STM32_RCC_CSR_MSISRANGE_1 (0x4UL << STM32_RCC_CSR_MSISRANGE_POS)
+#define STM32_RCC_CSR_MSISRANGE_2 (0x5UL << STM32_RCC_CSR_MSISRANGE_POS)
+#define STM32_RCC_CSR_MSISRANGE_4 (0x6UL << STM32_RCC_CSR_MSISRANGE_POS)
+#define STM32_RCC_CSR_MSISRANGE_8 (0x7UL << STM32_RCC_CSR_MSISRANGE_POS)
+
+#define STM32_RCC_CSR_RMVF_POS 23U
+#define STM32_RCC_CSR_RMVF_MSK (0x1UL << STM32_RCC_CSR_RMVF_POS)
+#define STM32_RCC_CSR_RMVF STM32_RCC_CSR_RMVF_MSK
+#define STM32_RCC_CSR_OBLRSTF_POS 25U
+#define STM32_RCC_CSR_OBLRSTF_MSK (0x1UL << STM32_RCC_CSR_OBLRSTF_POS)
+#define STM32_RCC_CSR_OBLRSTF STM32_RCC_CSR_OBLRSTF_MSK
+#define STM32_RCC_CSR_PINRSTF_POS 26U
+#define STM32_RCC_CSR_PINRSTF_MSK (0x1UL << STM32_RCC_CSR_PINRSTF_POS)
+#define STM32_RCC_CSR_PINRSTF STM32_RCC_CSR_PINRSTF_MSK
+#define STM32_RCC_CSR_BORRSTF_POS 27U
+#define STM32_RCC_CSR_BORRSTF_MSK (0x1UL << STM32_RCC_CSR_BORRSTF_POS)
+#define STM32_RCC_CSR_BORRSTF STM32_RCC_CSR_BORRSTF_MSK
+#define STM32_RCC_CSR_SFTRSTF_POS 28U
+#define STM32_RCC_CSR_SFTRSTF_MSK (0x1UL << STM32_RCC_CSR_SFTRSTF_POS)
+#define STM32_RCC_CSR_SFTRSTF STM32_RCC_CSR_SFTRSTF_MSK
+#define STM32_RCC_CSR_IWDGRSTF_POS 29U
+#define STM32_RCC_CSR_IWDGRSTF_MSK (0x1UL << STM32_RCC_CSR_IWDGRSTF_POS)
+#define STM32_RCC_CSR_IWDGRSTF STM32_RCC_CSR_IWDGRSTF_MSK
+#define STM32_RCC_CSR_WWDGRSTF_POS 30U
+#define STM32_RCC_CSR_WWDGRSTF_MSK (0x1UL << STM32_RCC_CSR_WWDGRSTF_POS)
+#define STM32_RCC_CSR_WWDGRSTF STM32_RCC_CSR_WWDGRSTF_MSK
+#define STM32_RCC_CSR_LPWRRSTF_POS 31U
+#define STM32_RCC_CSR_LPWRRSTF_MSK (0x1UL << STM32_RCC_CSR_LPWRRSTF_POS)
+#define STM32_RCC_CSR_LPWRRSTF STM32_RCC_CSR_LPWRRSTF_MSK
+
+/**************  Bit definition for STM32_RCC_CRRCR register  *****************/
+#define STM32_RCC_CRRCR_HSI48ON_POS 0U
+#define STM32_RCC_CRRCR_HSI48ON_MSK (0x1UL << STM32_RCC_CRRCR_HSI48ON_POS)
+#define STM32_RCC_CRRCR_HSI48ON STM32_RCC_CRRCR_HSI48ON_MSK
+#define STM32_RCC_CRRCR_HSI48RDY_POS 1U
+#define STM32_RCC_CRRCR_HSI48RDY_MSK (0x1UL << STM32_RCC_CRRCR_HSI48RDY_POS)
+#define STM32_RCC_CRRCR_HSI48RDY STM32_RCC_CRRCR_HSI48RDY_MSK
+
+/**************  Bit definition for STM32_RCC_CRRCR2 register  ****************/
+/* TODO */
+
+/**************  Bit definition for STM32_RCC_DLYCFGR register  ***************/
+/* TODO */
+
+/**************  Bit definition for STM32_RCC_CCIPR2 register  ****************/
+#define STM32_RCC_CCIPR2_I2C4SEL_POS 0U
+#define STM32_RCC_CCIPR2_I2C4SEL_MSK (0x3UL << STM32_RCC_CCIPR2_I2C4SEL_POS)
+#define STM32_RCC_CCIPR2_I2C4SEL STM32_RCC_CCIPR2_I2C4SEL_MSK
+#define STM32_RCC_CCIPR2_I2C4SEL_0 (0x1UL << STM32_RCC_CCIPR2_I2C4SEL_POS)
+#define STM32_RCC_CCIPR2_I2C4SEL_1 (0x2UL << STM32_RCC_CCIPR2_I2C4SEL_POS)
+
+/**************  Bit definition for STM32_CRS_CR register  ********************/
+#define STM32_CRS_CR_SYNCOKIE_POS 0U
+#define STM32_CRS_CR_SYNCOKIE_MSK (0x1UL << STM32_CRS_CR_SYNCOKIE_POS)
+#define STM32_CRS_CR_SYNCOKIE STM32_CRS_CR_SYNCOKIE_MSK
+#define STM32_CRS_CR_SYNCWARNIE_POS 1U
+#define STM32_CRS_CR_SYNCWARNIE_MSK (0x1UL << STM32_CRS_CR_SYNCWARNIE_POS)
+#define STM32_CRS_CR_SYNCWARNIE STM32_CRS_CR_SYNCWARNIE_MSK
+#define STM32_CRS_CR_SYNCERRIE_POS 2U
+#define STM32_CRS_CR_SYNCERRIE_MSK (0x1UL << STM32_CRS_CR_SYNCERRIE_POS)
+#define STM32_CRS_CR_SYNCERRIE STM32_CRS_CR_SYNCERRIE_MSK
+#define STM32_CRS_CR_SYNCIE_POS 3U
+#define STM32_CRS_CR_SYNCIE_MSK (0x1UL << STM32_CRS_CR_SYNCIE_POS)
+#define STM32_CRS_CR_SYNCIE STM32_CRS_CR_SYNCIE_MSK
+#define STM32_CRS_CR_CEN_POS 5U
+#define STM32_CRS_CR_CEN_MSK (0x1UL << STM32_CRS_CR_CEN_POS)
+#define STM32_CRS_CR_CEN STM32_CRS_CR_CEN_MSK
+#define STM32_CRS_CR_AUTOTRIMEN_POS 6U
+#define STM32_CRS_CR_AUTOTRIMEN_MSK (0x1UL << STM32_CRS_CR_AUTOTRIMEN_POS)
+#define STM32_CRS_CR_AUTOTRIMEN STM32_CRS_CR_AUTOTRIMEN_MSK
+#define STM32_CRS_CR_SWSYNC_POS 7U
+#define STM32_CRS_CR_SWSYNC_MSK (0x1UL << STM32_CRS_CR_SWSYNC_POS)
+#define STM32_CRS_CR_SWSYNC STM32_CRS_CR_SWSYNC_MSK
+
+/*!< HSI48CAL configuration */
+#define STM32_RCC_CRRCR_HSI48CAL_POS 7U
+#define STM32_RCC_CRRCR_HSI48CAL_MSK (0x1FFUL << STM32_RCC_CRRCR_HSI48CAL_POS)
+#define STM32_RCC_CRRCR_HSI48CAL STM32_RCC_CRRCR_HSI48CAL_MSK
+#define STM32_RCC_CRRCR_HSI48CAL_0 (0x001UL << STM32_RCC_CRRCR_HSI48CAL_POS)
+#define STM32_RCC_CRRCR_HSI48CAL_1 (0x002UL << STM32_RCC_CRRCR_HSI48CAL_POS)
+#define STM32_RCC_CRRCR_HSI48CAL_2 (0x004UL << STM32_RCC_CRRCR_HSI48CAL_POS)
+#define STM32_RCC_CRRCR_HSI48CAL_3 (0x008UL << STM32_RCC_CRRCR_HSI48CAL_POS)
+#define STM32_RCC_CRRCR_HSI48CAL_4 (0x010UL << STM32_RCC_CRRCR_HSI48CAL_POS)
+#define STM32_RCC_CRRCR_HSI48CAL_5 (0x020UL << STM32_RCC_CRRCR_HSI48CAL_POS)
+#define STM32_RCC_CRRCR_HSI48CAL_6 (0x040UL << STM32_RCC_CRRCR_HSI48CAL_POS)
+#define STM32_RCC_CRRCR_HSI48CAL_7 (0x080UL << STM32_RCC_CRRCR_HSI48CAL_POS)
+#define STM32_RCC_CRRCR_HSI48CAL_8 (0x100UL << STM32_RCC_CRRCR_HSI48CAL_POS)
+
+#define STM32_SYSCFG_CFGR1 REG32(STM32_SYSCFG_BASE + 0x04)
+#define STM32_SYSCFG_I2CFMP(n) BIT(n + 21)
+
+/* Peripheral bits for STM32_RCC_APB/AHB and DBGMCU regs */
+#define STM32_RCC_PB1_PWREN BIT(28)
+
+#define STM32_RCC_PB2_SYSCFGEN BIT(0)
+#define STM32_RCC_PB2_USART1 BIT(14)
+
+#define STM32_RCC_HB1_DMA1 BIT(0)
+#define STM32_RCC_HB1_DMA2 BIT(1)
+
+#define STM32_RCC_HB2_GPIOA BIT(0)
+#define STM32_RCC_HB2_GPIOB BIT(1)
+#define STM32_RCC_HB2_GPIOC BIT(2)
+#define STM32_RCC_HB2_GPIOD BIT(3)
+#define STM32_RCC_HB2_GPIOE BIT(4)
+#define STM32_RCC_HB2_GPIOH BIT(7)
+#define STM32_RCC_HB2_ADC1 BIT(13)
+
+/* Reset causes definitions */
+/* Reset causes in RCC CSR register */
+#define STM32_RCC_RESET_CAUSE STM32_RCC_CSR
+#define RESET_CAUSE_WDG 0x60000000
+#define RESET_CAUSE_SFT 0x10000000
+#define RESET_CAUSE_POR 0x08000000
+#define RESET_CAUSE_PIN 0x04000000
+#define RESET_CAUSE_OTHER 0xff000000
+#define RESET_CAUSE_RMVF BIT(23)
+/* Power cause in PWR CSR register */
+#define STM32_PWR_RESET_CAUSE STM32_PWR_CSR
+#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_SCR
+#define RESET_CAUSE_SBF BIT(8)
+#define RESET_CAUSE_SBF_CLR BIT(8)
+
+/* --- Watchdogs --- */
+
+/* --- Real-Time Clock --- */
+#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00)
+#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04)
+#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08)
+#define STM32_RTC_CR_BYPSHAD BIT(5)
+#define STM32_RTC_CR_ALRAE BIT(8)
+#define STM32_RTC_CR_WUTE BIT(10)
+#define STM32_RTC_CR_ALRAIE BIT(12)
+#define STM32_RTC_CR_WUTIE BIT(14)
+#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C)
+#define STM32_RTC_ISR_ALRAWF BIT(0)
+#define STM32_RTC_ISR_WUTWF BIT(2)
+#define STM32_RTC_ISR_INITS BIT(4)
+#define STM32_RTC_ISR_RSF BIT(5)
+#define STM32_RTC_ISR_INITF BIT(6)
+#define STM32_RTC_ISR_INIT BIT(7)
+#define STM32_RTC_ISR_ALRAF BIT(8)
+#define STM32_RTC_ISR_WUTF BIT(9)
+#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10)
+#define STM32_RTC_PRER_A_MASK (0x7f << 16)
+#define STM32_RTC_PRER_S_MASK (0x7fff << 0)
+#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14)
+#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18)
+#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C)
+#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20)
+#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24)
+#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28)
+#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30)
+#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34)
+#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40)
+#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44)
+
+#define STM32_RTC_CLEAR_FLAG(x)                         \
+	(STM32_RTC_ISR = (~((x) | STM32_RTC_ISR_INIT) | \
+			  (STM32_RTC_ISR & STM32_RTC_ISR_INIT)))
+
+/* --- Tamper and backup registers --- */
+#define STM32_TAMP_CR1 REG32(STM32_TAMP_BASE)
+#define STM32_TAMP_CR2 REG32(STM32_TAMP_BASE + 0x04)
+#define STM32_TAMP_CR3 REG32(STM32_TAMP_BASE + 0x08)
+#define STM32_TAMP_FLTCR REG32(STM32_TAMP_BASE + 0x0C)
+#define STM32_TAMP_ATCR1 REG32(STM32_TAMP_BASE + 0x10)
+#define STM32_TAMP_ATSEEDR REG32(STM32_TAMP_BASE + 0x14)
+#define STM32_TAMP_ATOR REG32(STM32_TAMP_BASE + 0x18)
+#define STM32_TAMP_ATOCR2 REG32(STM32_TAMP_BASE + 0x1C)
+#define STM32_TAMP_ATSMCR REG32(STM32_TAMP_BASE + 0x20)
+#define STM32_TAMP_PRIVCR REG32(STM32_TAMP_BASE + 0x24)
+#define STM32_TAMP_IER REG32(STM32_TAMP_BASE + 0x2C)
+#define STM32_TAMP_SR REG32(STM32_TAMP_BASE + 0x30)
+#define STM32_TAMP_MISR REG32(STM32_TAMP_BASE + 0x34)
+#define STM32_TAMP_SMISR REG32(STM32_TAMP_BASE + 0x38)
+#define STM32_TAMP_SCR REG32(STM32_TAMP_BASE + 0x3C)
+#define STM32_TAMP_COUNTR REG32(STM32_TAMP_BASE + 0x40)
+#define STM32_TAMP_CFGR REG32(STM32_TAMP_BASE + 0x50)
+#define STM32_TAMP_BACKUP(n) REG32(STM32_TAMP_BASE + 0x100 + 4 * (n))
+
+#define STM32_BKP_DATA(n) STM32_TAMP_BACKUP(n)
+#define STM32_BKP_BYTES 128
+
+#define RTC_TR_PM_POS 22U
+#define RTC_TR_PM_MSK (0x1UL << RTC_TR_PM_POS)
+#define RTC_TR_PM RTC_TR_PM_MSK
+#define RTC_TR_HT_POS 20U
+#define RTC_TR_HT_MSK (0x3UL << RTC_TR_HT_POS)
+#define RTC_TR_HT RTC_TR_HT_MSK
+#define RTC_TR_HU_POS 16U
+#define RTC_TR_HU_MSK (0xFUL << RTC_TR_HU_POS)
+#define RTC_TR_HU RTC_TR_HU_MSK
+#define RTC_TR_MNT_POS 12U
+#define RTC_TR_MNT_MSK (0x7UL << RTC_TR_MNT_POS)
+#define RTC_TR_MNT RTC_TR_MNT_MSK
+#define RTC_TR_MNU_POS 8U
+#define RTC_TR_MNU_MSK (0xFUL << RTC_TR_MNU_POS)
+#define RTC_TR_MNU RTC_TR_MNU_MSK
+#define RTC_TR_ST_POS 4U
+#define RTC_TR_ST_MSK (0x7UL << RTC_TR_ST_POS)
+#define RTC_TR_ST RTC_TR_ST_MSK
+#define RTC_TR_SU_POS 0U
+#define RTC_TR_SU_MSK (0xFUL << RTC_TR_SU_POS)
+#define RTC_TR_SU RTC_TR_SU_MSK
+
+/* --- SPI --- */
+
+/* The SPI controller registers */
+struct stm32_spi_regs {
+	uint16_t cr1;
+	uint16_t _pad0;
+	uint16_t cr2;
+	uint16_t _pad1;
+	unsigned int sr;
+	uint8_t dr;
+	uint8_t _pad2;
+	uint16_t _pad3;
+	unsigned int crcpr;
+	unsigned int rxcrcr;
+	unsigned int txcrcr;
+	unsigned int i2scfgr; /* STM32L only */
+	unsigned int i2spr; /* STM32L only */
+};
+/* Must be volatile, or compiler optimizes out repeated accesses */
+typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
+
+#define STM32_SPI1_REGS ((stm32_spi_regs_t *)STM32_SPI1_BASE)
+#define STM32_SPI2_REGS ((stm32_spi_regs_t *)STM32_SPI2_BASE)
+#define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE)
+#define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE)
+
+#define STM32_SPI_CR1_BIDIMODE BIT(15)
+#define STM32_SPI_CR1_BIDIOE BIT(14)
+#define STM32_SPI_CR1_CRCEN BIT(13)
+#define STM32_SPI_CR1_SSM BIT(9)
+#define STM32_SPI_CR1_SSI BIT(8)
+#define STM32_SPI_CR1_LSBFIRST BIT(7)
+#define STM32_SPI_CR1_SPE BIT(6)
+#define STM32_SPI_CR1_BR_DIV64R (5 << 3)
+#define STM32_SPI_CR1_BR_DIV4R BIT(3)
+#define STM32_SPI_CR1_MSTR BIT(2)
+#define STM32_SPI_CR1_CPOL BIT(1)
+#define STM32_SPI_CR1_CPHA BIT(0)
+#define STM32_SPI_CR2_FRXTH BIT(12)
+#define STM32_SPI_CR2_DATASIZE(n) (((n)-1) << 8)
+#define STM32_SPI_CR2_TXEIE BIT(7)
+#define STM32_SPI_CR2_RXNEIE BIT(6)
+#define STM32_SPI_CR2_NSSP BIT(3)
+#define STM32_SPI_CR2_SSOE BIT(2)
+#define STM32_SPI_CR2_TXDMAEN BIT(1)
+#define STM32_SPI_CR2_RXDMAEN BIT(0)
+
+#define STM32_SPI_SR_RXNE BIT(0)
+#define STM32_SPI_SR_TXE BIT(1)
+#define STM32_SPI_SR_CRCERR BIT(4)
+#define STM32_SPI_SR_BSY BIT(7)
+#define STM32_SPI_SR_FRLVL (3 << 9)
+#define STM32_SPI_SR_FTLVL (3 << 11)
+/* --- Debug --- */
+#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08)
+#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C)
+
+/* --- Flash --- */
+#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00)
+#define STM32_FLASH_ACR_LATENCY_SHIFT (0)
+#define STM32_FLASH_ACR_LATENCY_MASK (7 << STM32_FLASH_ACR_LATENCY_SHIFT)
+#define STM32_FLASH_ACR_PRFTEN BIT(8)
+#define STM32_FLASH_ACR_ICEN BIT(9)
+#define STM32_FLASH_ACR_DCEN BIT(10)
+#define STM32_FLASH_ACR_ICRST BIT(11)
+#define STM32_FLASH_ACR_DCRST BIT(12)
+#define STM32_FLASH_PDKEYR REG32(STM32_FLASH_REGS_BASE + 0x04)
+#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x08)
+#define FLASH_KEYR_KEY1 0x45670123
+#define FLASH_KEYR_KEY2 0xCDEF89AB
+#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x10)
+#define FLASH_OPTKEYR_KEY1 0x08192A3B
+#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F
+#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x20)
+#define FLASH_SR_BUSY BIT(16)
+#define FLASH_SR_ERR_MASK (0xc3fa)
+#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x28)
+#define FLASH_CR_PG BIT(0)
+#define FLASH_CR_PER BIT(1)
+#define FLASH_CR_STRT BIT(16)
+#define FLASH_CR_OPTSTRT BIT(17)
+#define FLASH_CR_OBL_LAUNCH BIT(27)
+#define FLASH_CR_OPTLOCK BIT(30)
+#define FLASH_CR_LOCK BIT(31)
+#define FLASH_CR_PNB(sec) (((sec)&0xff) << 3)
+#define FLASH_CR_PNB_MASK FLASH_CR_PNB(0xff)
+#define STM32_FLASH_ECCR REG32(STM32_FLASH_REGS_BASE + 0x30)
+#define STM32_FLASH_OPTR REG32(STM32_FLASH_REGS_BASE + 0x40)
+#define STM32_FLASH_WRP1AR REG32(STM32_FLASH_REGS_BASE + 0x58)
+#define STM32_FLASH_WRP1BR REG32(STM32_FLASH_REGS_BASE + 0x5C)
+/* Minimum number of bytes that can be written to flash */
+#define STM32_FLASH_MIN_WRITE_SIZE CONFIG_FLASH_WRITE_SIZE
+
+#define STM32_OPTB_WRP1AR STM32_FLASH_WRP1AR
+#define STM32_OPTB_WRP1BR STM32_FLASH_WRP1BR
+
+/* --- External Interrupts --- */
+#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x00)
+#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x04)
+#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x08)
+#define STM32_EXTI_RPR REG32(STM32_EXTI_BASE + 0x0C)
+#define STM32_EXTI_FPR REG32(STM32_EXTI_BASE + 0x10)
+#define STM32_EXTI_RTSR2 REG32(STM32_EXTI_BASE + 0x20)
+#define STM32_EXTI_FTSR2 REG32(STM32_EXTI_BASE + 0x24)
+#define STM32_EXTI_SWIER2 REG32(STM32_EXTI_BASE + 0x28)
+#define STM32_EXTI_RPR2 REG32(STM32_EXTI_BASE + 0x2C)
+#define STM32_EXTI_FPR2 REG32(STM32_EXTI_BASE + 0x30)
+#define STM32_EXTI_EXTICR(n) REG32(STM32_EXTI_BASE + 0x60 + 4 * (n))
+#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x80)
+#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x84)
+#define STM32_EXTI_IMR2 REG32(STM32_EXTI_BASE + 0x80)
+#define STM32_EXTI_EMR2 REG32(STM32_EXTI_BASE + 0x84)
+
+#define EXTI_RTC_ALR_EVENT BIT(18)
+
+/* --- ADC --- */
+#define STM32_ADC1_ISR REG32(STM32_ADC1_BASE + 0x00)
+#define STM32_ADC1_ISR_ADRDY BIT(0)
+#define STM32_ADC1_IER REG32(STM32_ADC1_BASE + 0x04)
+#define STM32_ADC1_IER_AWDIE BIT(7)
+#define STM32_ADC1_IER_OVRIE BIT(4)
+#define STM32_ADC1_IER_EOSEQIE BIT(3)
+#define STM32_ADC1_IER_EOCIE BIT(2)
+#define STM32_ADC1_IER_EOSMPIE BIT(1)
+#define STM32_ADC1_IER_ADRDYIE BIT(0)
+
+#define STM32_ADC1_CR REG32(STM32_ADC1_BASE + 0x08)
+#define STM32_ADC1_CR_ADEN BIT(0)
+#define STM32_ADC1_CR_ADDIS BIT(1)
+#define STM32_ADC1_CR_ADSTP BIT(4)
+#define STM32_ADC1_CR_ADVREGEN BIT(28)
+#define STM32_ADC1_CR_DEEPPWD BIT(29)
+#define STM32_ADC1_CR_ADCAL BIT(31)
+#define STM32_ADC1_CFGR REG32(STM32_ADC1_BASE + 0x0C)
+/* Analog watchdog channel selection */
+#define STM32_ADC1_CFGR_AWDCH_MASK (0x1f << 26)
+#define STM32_ADC1_CFGR_AWDEN BIT(23)
+#define STM32_ADC1_CFGR_AWDSGL BIT(22)
+#define STM32_ADC1_CFGR_AUTDLY BIT(14)
+/* Selects single vs continuous */
+#define STM32_ADC1_CFGR_CONT BIT(13)
+/* Selects ADC_DR overwrite vs preserve */
+#define STM32_ADC1_CFGR_OVRMOD BIT(12)
+/* External trigger polarity selection */
+#define STM32_ADC1_CFGR_EXTEN_DIS (0 << 10)
+#define STM32_ADC1_CFGR_EXTEN_RISE (1 << 10)
+#define STM32_ADC1_CFGR_EXTEN_FALL (2 << 10)
+#define STM32_ADC1_CFGR_EXTEN_BOTH (3 << 10)
+#define STM32_ADC1_CFGR_EXTEN_MASK (3 << 10)
+#define STM32_ADC1_CFGR_ALIGN BIT(5)
+/* External trigger selection */
+#define STM32_ADC1_CFGR_TRG0 (0 << 6)
+#define STM32_ADC1_CFGR_TRG1 (1 << 6)
+#define STM32_ADC1_CFGR_TRG2 (2 << 6)
+#define STM32_ADC1_CFGR_TRG3 (3 << 6)
+#define STM32_ADC1_CFGR_TRG4 (4 << 6)
+#define STM32_ADC1_CFGR_TRG5 (5 << 6)
+#define STM32_ADC1_CFGR_TRG6 (6 << 6)
+#define STM32_ADC1_CFGR_TRG7 (7 << 6)
+#define STM32_ADC1_CFGR_TRG_MASK (7 << 6)
+/* Selects circular vs one-shot */
+#define STM32_ADC1_CFGR_DMACFG BIT(1)
+#define STM32_ADC1_CFGR_DMAEN BIT(0)
+#define STM32_ADC1_CFGR2 REG32(STM32_ADC1_BASE + 0x10)
+/* Sampling time selection - 1.5 ADC cycles min, 239.5 cycles max */
+#define STM32_ADC1_SMPR1 REG32(STM32_ADC1_BASE + 0x14)
+#define STM32_ADC1_SMPR2 REG32(STM32_ADC1_BASE + 0x18)
+/* Macro to convert enum stm32_adc_smpr to SMP bits of the ADC_SMPR register */
+#define STM32_ADC1_SMPR_SMP(s) ((s)-1)
+#define STM32_ADC1_TR REG32(STM32_ADC1_BASE + 0x20)
+#define STM32_ADC1_CHSELR REG32(STM32_ADC1_BASE + 0x28)
+#define STM32_ADC1_DR REG32(STM32_ADC1_BASE + 0x40)
+#define STM32_ADC1_JSQR REG32(STM32_ADC1_BASE + 0x4C)
+#define STM32_ADC1_JDR1 REG32(STM32_ADC1_BASE + 0x80)
+#define STM32_ADC1_JDR2 REG32(STM32_ADC1_BASE + 0x84)
+#define STM32_ADC1_JDR3 REG32(STM32_ADC1_BASE + 0x88)
+#define STM32_ADC1_JDR4 REG32(STM32_ADC1_BASE + 0x8C)
+#define STM32_ADC1_CCR REG32(STM32_ADC1_BASE + 0x308)
+
+/* --- USB --- */
+#define STM32_USB_BCDR_DPPU BIT(15)
+
+/* --- DMA --- */
+
+/*
+ * Available DMA channels, numbered from 0.
+ *
+ * Note: The STM datasheet tends to number things from 1. We should ask
+ * the European elevator engineers to talk to MCU engineer counterparts
+ * about this.  This means that if the datasheet refers to channel n,
+ * you need to use STM32_DMAC_CHn (=n-1) in the code.
+ *
+ * Also note that channels are overloaded; obviously you can only use one
+ * function on each channel at a time.
+ */
+enum dma_channel {
+	/* Channel numbers */
+	STM32_DMAC_CH1 = 0,
+	STM32_DMAC_CH2 = 1,
+	STM32_DMAC_CH3 = 2,
+	STM32_DMAC_CH4 = 3,
+	STM32_DMAC_CH5 = 4,
+	STM32_DMAC_CH6 = 5,
+	STM32_DMAC_CH7 = 6,
+	/*
+	 * Skip CH8, it should belong to DMA engine 1.
+	 * Sharing code with STM32s that have 16 engines will be easier.
+	 */
+	STM32_DMAC_CH9 = 8,
+	STM32_DMAC_CH10 = 9,
+	STM32_DMAC_CH11 = 10,
+	STM32_DMAC_CH12 = 11,
+	STM32_DMAC_CH13 = 12,
+	STM32_DMAC_CH14 = 13,
+	STM32_DMAC_CH15 = 14,
+
+	/* Channel functions */
+	STM32_DMAC_SPI1_RX = STM32_DMAC_CH2,
+	STM32_DMAC_SPI1_TX = STM32_DMAC_CH3,
+	STM32_DMAC_USART1_TX = STM32_DMAC_CH14,
+	STM32_DMAC_USART1_RX = STM32_DMAC_CH15,
+	STM32_DMAC_SPI2_RX = STM32_DMAC_CH4,
+	STM32_DMAC_SPI2_TX = STM32_DMAC_CH5,
+	STM32_DMAC_SPI3_RX = STM32_DMAC_CH9,
+	STM32_DMAC_SPI3_TX = STM32_DMAC_CH10,
+	STM32_DMAC_COUNT = 15,
+};
+
+#define STM32_DMAC_PER_CTLR 8
+
+/* Registers for a single channel of the DMA controller */
+struct stm32_dma_chan {
+	uint32_t ccr; /* Control */
+	uint32_t cndtr; /* Number of data to transfer */
+	uint32_t cpar; /* Peripheral address */
+	uint32_t cmar; /* Memory address */
+	uint32_t reserved;
+};
+
+/* Always use stm32_dma_chan_t so volatile keyword is included! */
+typedef volatile struct stm32_dma_chan stm32_dma_chan_t;
+
+/* Common code and header file must use this */
+typedef stm32_dma_chan_t dma_chan_t;
+
+/* Registers for the DMA controller */
+struct stm32_dma_regs {
+	uint32_t isr;
+	uint32_t ifcr;
+	stm32_dma_chan_t chan[STM32_DMAC_COUNT];
+};
+
+/* Always use stm32_dma_regs_t so volatile keyword is included! */
+typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
+
+#define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE)
+
+#define STM32_DMA_CCR_CHANNEL(channel) (0)
+#define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE)
+#define STM32_DMA_REGS(channel) \
+	((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_REGS : STM32_DMA2_REGS)
+#define STM32_DMA_CSELR(channel)                                    \
+	REG32(((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_BASE :  \
+						 STM32_DMA2_BASE) + \
+	      0xA8)
+
+/* Bits for DMA controller regs (isr and ifcr) */
+#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR))
+#define STM32_DMA_ISR_MASK(channel, mask) \
+	((mask) << STM32_DMA_CH_OFFSET(channel))
+#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0))
+#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1))
+#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2))
+#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3))
+#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f)
+
+#define STM32_DMA_GIF BIT(0)
+#define STM32_DMA_TCIF BIT(1)
+#define STM32_DMA_HTIF BIT(2)
+#define STM32_DMA_TEIF BIT(3)
+#define STM32_DMA_ALL 0xf
+
+#define STM32_DMA_GET_ISR(channel)                                        \
+	((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) & \
+	 STM32_DMA_ALL)
+#define STM32_DMA_SET_ISR(channel, val)                                \
+	(STM32_DMA_REGS(channel)->isr =                                \
+		 ((STM32_DMA_REGS(channel)->isr &                      \
+		   ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
+		  (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
+#define STM32_DMA_GET_IFCR(channel)                                        \
+	((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) & \
+	 STM32_DMA_ALL)
+#define STM32_DMA_SET_IFCR(channel, val)                               \
+	(STM32_DMA_REGS(channel)->ifcr =                               \
+		 ((STM32_DMA_REGS(channel)->ifcr &                     \
+		   ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
+		  (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
+
+/* Bits for DMA channel regs */
+#define STM32_DMA_CCR_EN BIT(0)
+#define STM32_DMA_CCR_TCIE BIT(1)
+#define STM32_DMA_CCR_HTIE BIT(2)
+#define STM32_DMA_CCR_TEIE BIT(3)
+#define STM32_DMA_CCR_DIR BIT(4)
+#define STM32_DMA_CCR_CIRC BIT(5)
+#define STM32_DMA_CCR_PINC BIT(6)
+#define STM32_DMA_CCR_MINC BIT(7)
+#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8)
+#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8)
+#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8)
+#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10)
+#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10)
+#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10)
+#define STM32_DMA_CCR_PL_LOW (0 << 12)
+#define STM32_DMA_CCR_PL_MEDIUM (1 << 12)
+#define STM32_DMA_CCR_PL_HIGH (2 << 12)
+#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12)
+#define STM32_DMA_CCR_MEM2MEM BIT(14)
+
+/* The requests for the DMA1/DMA2 controllers are routed through DMAMUX. */
+/* DMAMUX registers */
+#define STM32_DMAMUX_CxCR(x) REG32(STM32_DMAMUX_BASE + 4 * (x))
+#define STM32_DMAMUX_CSR REG32(STM32_DMAMUX_BASE + 0x80)
+#define STM32_DMAMUX_CFR REG32(STM32_DMAMUX_BASE + 0x84)
+#define STM32_DMAMUX_RGxCR(x) REG32(STM32_DMAMUX_BASE + 0x100 + 4 * (x))
+#define STM32_DMAMUX_RGSR REG32(STM32_DMAMUX_BASE + 0x140)
+#define STM32_DMAMUX_RGCFR REG32(STM32_DMAMUX_BASE + 0x144)
+
+enum dmamux1_request {
+	DMAMUX_REQ_ADC1 = 5,
+	DMAMUX_REQ_ADC2 = 6,
+	DMAMUX_REQ_DAC1 = 7,
+	DMAMUX_REQ_DAC2 = 8,
+	DMAMUX_REQ_TIM6_UP = 9,
+	DMAMUX_REQ_TIM7_UP = 10,
+	DMAMUX_REQ_SPI1_RX = 11,
+	DMAMUX_REQ_SPI1_TX = 12,
+	DMAMUX_REQ_SPI2_RX = 13,
+	DMAMUX_REQ_SPI2_TX = 14,
+	DMAMUX_REQ_SPI3_RX = 15,
+	DMAMUX_REQ_SPI3_TX = 16,
+	DMAMUX_REQ_I2C1_RX = 17,
+	DMAMUX_REQ_I2C1_TX = 18,
+	DMAMUX_REQ_I2C2_RX = 19,
+	DMAMUX_REQ_I2C2_TX = 20,
+	DMAMUX_REQ_I2C3_RX = 21,
+	DMAMUX_REQ_I2C3_TX = 22,
+	DMAMUX_REQ_I2C4_RX = 23,
+	DMAMUX_REQ_I2C4_TX = 24,
+	DMAMUX_REQ_USART1_RX = 25,
+	DMAMUX_REQ_USART1_TX = 26,
+	DMAMUX_REQ_USART2_RX = 27,
+	DMAMUX_REQ_USART2_TX = 28,
+	DMAMUX_REQ_USART3_RX = 29,
+	DMAMUX_REQ_USART3_TX = 30,
+	DMAMUX_REQ_UART4_RX = 31,
+	DMAMUX_REQ_UART4_TX = 32,
+	DMAMUX_REQ_UART5_RX = 33,
+	DMAMUX_REQ_UART5_TX = 34,
+	DMAMUX_REQ_LPUART1_RX = 35,
+	DMAMUX_REQ_LPUART1_TX = 36,
+	DMAMUX_REQ_SAI1_A = 37,
+	DMAMUX_REQ_SAI1_B = 38,
+	DMAMUX_REQ_SAI2_A = 39,
+	DMAMUX_REQ_SAI2_B = 40,
+	DMAMUX_REQ_OCTOSPI1 = 41,
+	DMAMUX_REQ_TIM1_CH1 = 42,
+	DMAMUX_REQ_TIM1_CH2 = 43,
+	DMAMUX_REQ_TIM1_CH3 = 44,
+	DMAMUX_REQ_TIM1_CH4 = 45,
+	DMAMUX_REQ_TIM1_UP = 46,
+	DMAMUX_REQ_TIM1_TRIG = 47,
+	DMAMUX_REQ_TIM1_COM = 48,
+	DMAMUX_REQ_TIM8_CH1 = 49,
+	DMAMUX_REQ_TIM8_CH2 = 50,
+	DMAMUX_REQ_TIM8_CH3 = 51,
+	DMAMUX_REQ_TIM8_CH4 = 52,
+	DMAMUX_REQ_TIM8_UP = 53,
+	DMAMUX_REQ_TIM8_TRIG = 54,
+	DMAMUX_REQ_TIM8_COM = 55,
+	DMAMUX_REQ_TIM2_CH1 = 56,
+	DMAMUX_REQ_TIM2_CH2 = 57,
+	DMAMUX_REQ_TIM2_CH3 = 58,
+	DMAMUX_REQ_TIM2_CH4 = 59,
+	DMAMUX_REQ_TIM2_UP = 60,
+	DMAMUX_REQ_TIM3_CH1 = 61,
+	DMAMUX_REQ_TIM3_CH2 = 62,
+	DMAMUX_REQ_TIM3_CH3 = 63,
+	DMAMUX_REQ_TIM3_CH4 = 64,
+	DMAMUX_REQ_TIM3_UP = 65,
+	DMAMUX_REQ_TIM3_TRIG = 66,
+	DMAMUX_REQ_TIM4_CH1 = 67,
+	DMAMUX_REQ_TIM4_CH2 = 68,
+	DMAMUX_REQ_TIM4_CH3 = 69,
+	DMAMUX_REQ_TIM4_CH4 = 70,
+	DMAMUX_REQ_TIM4_UP = 71,
+	DMAMUX_REQ_TIM5_CH1 = 72,
+	DMAMUX_REQ_TIM5_CH2 = 73,
+	DMAMUX_REQ_TIM5_CH3 = 74,
+	DMAMUX_REQ_TIM5_CH4 = 75,
+	DMAMUX_REQ_TIM5_UP = 76,
+	DMAMUX_REQ_TIM5_TRIG = 77,
+	DMAMUX_REQ_TIM15_CH1 = 78,
+	DMAMUX_REQ_TIM15_UP = 79,
+	DMAMUX_REQ_TIM15_TRIG = 80,
+	DMAMUX_REQ_TIM15_COM = 81,
+	DMAMUX_REQ_TIM16_CH1 = 82,
+	DMAMUX_REQ_TIM16_UP = 83,
+	DMAMUX_REQ_TIM17_CH1 = 84,
+	DMAMUX_REQ_TIM17_UP = 85,
+	DMAMUX_REQ_DFSDM1_FLT0 = 86,
+	DMAMUX_REQ_DFSDM1_FLT1 = 87,
+	DMAMUX_REQ_DFSDM1_FLT2 = 88,
+	DMAMUX_REQ_DFSDM1_FLT3 = 89,
+	DMAMUX_REQ_AES_IN = 90,
+	DMAMUX_REQ_AES_OUT = 91,
+	DMAMUX_REQ_HASH_IN = 92,
+	DMAMUX_REQ_USBPD_TX = 93,
+	DMAMUX_REQ_USBPD_RX = 94,
+};
+
+/* LPUART gets accessed as UART9 in STM32 uart module */
+#define STM32_USART9_BASE STM32_LPUART1_BASE
+#define STM32_IRQ_USART9 STM32_IRQ_LPUART1
+#define DMAMUX_REQ_UART9_RX DMAMUX_REQ_LPUART1_RX
+#define DMAMUX_REQ_UART9_TX DMAMUX_REQ_LPUART1_TX
+
+/* --- OCTOSPI --- */
+
+#define STM32_OCTOSPI_CR REG32(STM32_OCTOSPI_BASE + 0x00)
+#define STM32_OCTOSPI_DCR1 REG32(STM32_OCTOSPI_BASE + 0x08)
+#define STM32_OCTOSPI_DCR2 REG32(STM32_OCTOSPI_BASE + 0x0C)
+#define STM32_OCTOSPI_DCR3 REG32(STM32_OCTOSPI_BASE + 0x10)
+#define STM32_OCTOSPI_DCR4 REG32(STM32_OCTOSPI_BASE + 0x14)
+#define STM32_OCTOSPI_SR REG32(STM32_OCTOSPI_BASE + 0x20)
+#define STM32_OCTOSPI_FCR REG32(STM32_OCTOSPI_BASE + 0x24)
+#define STM32_OCTOSPI_DLR REG32(STM32_OCTOSPI_BASE + 0x40)
+#define STM32_OCTOSPI_AR REG32(STM32_OCTOSPI_BASE + 0x48)
+#define STM32_OCTOSPI_DR REG32(STM32_OCTOSPI_BASE + 0x50)
+#define STM32_OCTOSPI_PSMKR REG32(STM32_OCTOSPI_BASE + 0x80)
+#define STM32_OCTOSPI_PSMAR REG32(STM32_OCTOSPI_BASE + 0x88)
+#define STM32_OCTOSPI_PIR REG32(STM32_OCTOSPI_BASE + 0x90)
+#define STM32_OCTOSPI_CCR REG32(STM32_OCTOSPI_BASE + 0x100)
+#define STM32_OCTOSPI_TCR REG32(STM32_OCTOSPI_BASE + 0x108)
+#define STM32_OCTOSPI_IR REG32(STM32_OCTOSPI_BASE + 0x110)
+#define STM32_OCTOSPI_ABR REG32(STM32_OCTOSPI_BASE + 0x120)
+#define STM32_OCTOSPI_LPTR REG32(STM32_OCTOSPI_BASE + 0x130)
+#define STM32_OCTOSPI_WPCCR REG32(STM32_OCTOSPI_BASE + 0x140)
+#define STM32_OCTOSPI_WPTCR REG32(STM32_OCTOSPI_BASE + 0x148)
+#define STM32_OCTOSPI_WPIR REG32(STM32_OCTOSPI_BASE + 0x150)
+#define STM32_OCTOSPI_WPABR REG32(STM32_OCTOSPI_BASE + 0x160)
+#define STM32_OCTOSPI_WCCR REG32(STM32_OCTOSPI_BASE + 0x180)
+#define STM32_OCTOSPI_WTCR REG32(STM32_OCTOSPI_BASE + 0x188)
+#define STM32_OCTOSPI_WIR REG32(STM32_OCTOSPI_BASE + 0x190)
+#define STM32_OCTOSPI_WABR REG32(STM32_OCTOSPI_BASE + 0x1A0)
+#define STM32_OCTOSPI_HLCR REG32(STM32_OCTOSPI_BASE + 0x200)
+
+/* Bit values for STM32_OCTOSPI_CR */
+#define STM32_OCTOSPI_CR_FMODE_POS 28U
+#define STM32_OCTOSPI_CR_FMODE_MSK (0x3UL << STM32_OCTOSPI_CR_FMODE_POS)
+#define STM32_OCTOSPI_CR_FMODE STM32_OCTOSPI_FMODE_MSK
+#define STM32_OCTOSPI_CR_FMODE_IND_WRITE (0x0UL << STM32_OCTOSPI_CR_FMODE_POS)
+#define STM32_OCTOSPI_CR_FMODE_IND_READ (0x1UL << STM32_OCTOSPI_CR_FMODE_POS)
+#define STM32_OCTOSPI_CR_FMODE_AUTO_POLL (0x2UL << STM32_OCTOSPI_CR_FMODE_POS)
+#define STM32_OCTOSPI_CR_FMODE_MEM_MAPPED (0x3UL << STM32_OCTOSPI_CR_FMODE_POS)
+
+#define STM32_OCTOSPI_CR_PMM_POS 23U
+#define STM32_OCTOSPI_CR_PMM_MSK (0x1UL << STM32_OCTOSPI_CR_PMM_POS)
+#define STM32_OCTOSPI_CR_PMM_AND 0
+#define STM32_OCTOSPI_CR_PMM_OR STM32_OCTOSPI_CR_PMM_MSK
+
+#define STM32_OCTOSPI_CR_APMS_POS 22U
+#define STM32_OCTOSPI_CR_APMS_MSK (0x1UL << STM32_OCTOSPI_CR_APMS_POS)
+#define STM32_OCTOSPI_CR_APMS STM32_OCTOSPI_CR_APMS_MSK
+
+#define STM32_OCTOSPI_CR_TOIE_POS 20U
+#define STM32_OCTOSPI_CR_TOIE_MSK (0x1UL << STM32_OCTOSPI_CR_TOIE_POS)
+#define STM32_OCTOSPI_CR_TOIE STM32_OCTOSPI_CR_TOIE_MSK
+
+#define STM32_OCTOSPI_CR_SMIE_POS 19U
+#define STM32_OCTOSPI_CR_SMIE_MSK (0x1UL << STM32_OCTOSPI_CR_SMIE_POS)
+#define STM32_OCTOSPI_CR_SMIE STM32_OCTOSPI_CR_SMIE_MSK
+
+#define STM32_OCTOSPI_CR_FTIE_POS 18U
+#define STM32_OCTOSPI_CR_FTIE_MSK (0x1UL << STM32_OCTOSPI_CR_FTIE_POS)
+#define STM32_OCTOSPI_CR_FTIE STM32_OCTOSPI_CR_FTIE_MSK
+
+#define STM32_OCTOSPI_CR_TCIE_POS 17U
+#define STM32_OCTOSPI_CR_TCIE_MSK (0x1UL << STM32_OCTOSPI_CR_TCIE_POS)
+#define STM32_OCTOSPI_CR_TCIE STM32_OCTOSPI_CR_TCIE_MSK
+
+#define STM32_OCTOSPI_CR_TEIE_POS 16U
+#define STM32_OCTOSPI_CR_TEIE_MSK (0x1UL << STM32_OCTOSPI_CR_TEIE_POS)
+#define STM32_OCTOSPI_CR_TEIE STM32_OCTOSPI_CR_TEIE_MSK
+
+#define STM32_OCTOSPI_CR_FTHRES_POS 8U
+#define STM32_OCTOSPI_CR_FTHRES_MSK (0x1FUL << STM32_OCTOSPI_CR_FTHRES_POS)
+
+#define STM32_OCTOSPI_CR_MSEL_POS 7U
+#define STM32_OCTOSPI_CR_MSEL_MSK (0x1UL << STM32_OCTOSPI_CR_MSEL_POS)
+#define STM32_OCTOSPI_CR_MSEL_FLASH1 0
+#define STM32_OCTOSPI_CR_MSEL_FLASH2 STM32_OCTOSPI_CR_MSEL_MSK
+
+#define STM32_OCTOSPI_CR_DMM_POS 6U
+#define STM32_OCTOSPI_CR_DMM_MSK (0x1UL << STM32_OCTOSPI_CR_DMM_POS)
+#define STM32_OCTOSPI_CR_DMM STM32_OCTOSPI_CR_DMM_MSK
+
+#define STM32_OCTOSPI_CR_TCEN_POS 3U
+#define STM32_OCTOSPI_CR_TCEN_MSK (0x1UL << STM32_OCTOSPI_CR_TCEN_POS)
+#define STM32_OCTOSPI_CR_TCEN STM32_OCTOSPI_CR_TCEN_MSK
+
+#define STM32_OCTOSPI_CR_DMAEN_POS 2U
+#define STM32_OCTOSPI_CR_DMAEN_MSK (0x1UL << STM32_OCTOSPI_CR_DMAEN_POS)
+#define STM32_OCTOSPI_CR_DMAEN STM32_OCTOSPI_CR_DMAEN_MSK
+
+#define STM32_OCTOSPI_CR_ABORT_POS 1U
+#define STM32_OCTOSPI_CR_ABORT_MSK (0x1UL << STM32_OCTOSPI_CR_ABORT_POS)
+#define STM32_OCTOSPI_CR_ABORT STM32_OCTOSPI_CR_ABORT_MSK
+
+#define STM32_OCTOSPI_CR_EN_POS 0U
+#define STM32_OCTOSPI_CR_EN_MSK (0x1UL << STM32_OCTOSPI_CR_EN_POS)
+#define STM32_OCTOSPI_CR_EN STM32_OCTOSPI_CR_EN_MSK
+
+/* Bit values for STM32_OCTOSPI_DCR1 */
+#define STM32_OCTOSPI_DCR1_MTYP_POS 24U
+#define STM32_OCTOSPI_DCR1_MTYP_MSK (0x7UL << STM32_OCTOSPI_DCR1_MTYP_POS)
+#define STM32_OCTOSPI_DCR1_MTYP_MICROS (0x0UL << STM32_OCTOSPI_DCR1_MTYP_POS)
+#define STM32_OCTOSPI_DCR1_MTYP_MACRONIX (0x1UL << STM32_OCTOSPI_DCR1_MTYP_POS)
+#define STM32_OCTOSPI_DCR1_MTYP_STANDARD (0x2UL << STM32_OCTOSPI_DCR1_MTYP_POS)
+#define STM32_OCTOSPI_DCR1_MTYP_MACRONIX_RAM \
+	(0x3UL << STM32_OCTOSPI_DCR1_MTYP_POS)
+#define STM32_OCTOSPI_DCR1_MTYP_HYPERBUS_MEM \
+	(0x4UL << STM32_OCTOSPI_DCR1_MTYP_POS)
+#define STM32_OCTOSPI_DCR1_MTYP_HYPERBUS_REG \
+	(0x5UL << STM32_OCTOSPI_DCR1_MTYP_POS)
+
+#define STM32_OCTOSPI_DCR1_DEVSIZE_POS 16U
+#define STM32_OCTOSPI_DCR1_DEVSIZE_MSK \
+	(0x1FUL << STM32_OCTOSPI_DCR1_DEVSIZE_POS)
+
+#define STM32_OCTOSPI_DCR1_CSHT_POS 8U
+#define STM32_OCTOSPI_DCR1_CSHT_MSK (0x1UL << STM32_OCTOSPI_DCR1_CSHT_POS)
+#define STM32_OCTOSPI_DCR1_CSHT_1 (0x0UL << STM32_OCTOSPI_DCR1_CSHT_POS)
+#define STM32_OCTOSPI_DCR1_CSHT_2 (0x1UL << STM32_OCTOSPI_DCR1_CSHT_POS)
+#define STM32_OCTOSPI_DCR1_CSHT_3 (0x2UL << STM32_OCTOSPI_DCR1_CSHT_POS)
+#define STM32_OCTOSPI_DCR1_CSHT_4 (0x3UL << STM32_OCTOSPI_DCR1_CSHT_POS)
+#define STM32_OCTOSPI_DCR1_CSHT_5 (0x4UL << STM32_OCTOSPI_DCR1_CSHT_POS)
+#define STM32_OCTOSPI_DCR1_CSHT_6 (0x5UL << STM32_OCTOSPI_DCR1_CSHT_POS)
+#define STM32_OCTOSPI_DCR1_CSHT_7 (0x6UL << STM32_OCTOSPI_DCR1_CSHT_POS)
+#define STM32_OCTOSPI_DCR1_CSHT_8 (0x7UL << STM32_OCTOSPI_DCR1_CSHT_POS)
+
+#define STM32_OCTOSPI_DCR1_DLYBYP_POS 3U
+#define STM32_OCTOSPI_DCR1_DLYBYP_MSK (0x1UL << STM32_OCTOSPI_DCR1_DLYBYP_POS)
+#define STM32_OCTOSPI_DCR1_DLYBYP STM32_OCTOSPI_DCR1_DLYBYP_MSK
+
+#define STM32_OCTOSPI_DCR1_FRCK_POS 1U
+#define STM32_OCTOSPI_DCR1_FRCK_MSK (0x1UL << STM32_OCTOSPI_DCR1_FRCK_POS)
+#define STM32_OCTOSPI_DCR1_FRCK STM32_OCTOSPI_DCR1_FRCK_MSK
+
+#define STM32_OCTOSPI_DCR1_CKMODE_POS 0U
+#define STM32_OCTOSPI_DCR1_CKMODE_MSK (0x1UL << STM32_OCTOSPI_DCR1_CKMODE_POS)
+#define STM32_OCTOSPI_DCR1_CKMODE_LOW 0
+#define STM32_OCTOSPI_DCR1_CKMODE_HIGH STM32_OCTOSPI_DCR1_CKMODE_MSK
+
+/* Bit values for STM32_OCTOSPI_DCR2 */
+#define STM32_OCTOSPI_DCR2_WRAPSIZE_POS 16U
+#define STM32_OCTOSPI_DCR2_WRAPSIZE_MSK \
+	(0x7UL << STM32_OCTOSPI_DCR2_WRAPSIZE_POS)
+
+#define STM32_OCTOSPI_DCR2_PRESCALER_POS 0U
+#define STM32_OCTOSPI_DCR2_PRESCALER_MSK \
+	(0xFFUL << STM32_OCTOSPI_DCR2_PRESCALER_POS)
+
+/* Bit values for STM32_OCTOSPI_DCR3 */
+#define STM32_OCTOSPI_DCR3_CSBOUND_POS 16U
+#define STM32_OCTOSPI_DCR3_CSBOUND_MSK \
+	(0x1FUL << STM32_OCTOSPI_DCR3_CSBOUND_POS)
+#define STM32_OCTOSPI_DCR3_CSBOUND_DISABLED 0
+
+/* Bit values for STM32_OCTOSPI_SR */
+#define STM32_OCTOSPI_SR_FLEVEL_POS 8U
+#define STM32_OCTOSPI_SR_FLEVEL_MSK (0x3FUL << STM32_OCTOSPI_SR_FLEVEL_POS)
+
+#define STM32_OCTOSPI_SR_BUSY_POS 5U
+#define STM32_OCTOSPI_SR_BUSY_MSK (0x1UL << STM32_OCTOSPI_SR_BUSY_POS)
+#define STM32_OCTOSPI_SR_BUSY STM32_OCTOSPI_SR_BUSY_MSK
+
+#define STM32_OCTOSPI_SR_TOF_POS 4U
+#define STM32_OCTOSPI_SR_TOF_MSK (0x1UL << STM32_OCTOSPI_SR_TOF_POS)
+#define STM32_OCTOSPI_SR_TOF STM32_OCTOSPI_SR_TOF_MSK
+
+#define STM32_OCTOSPI_SR_SMF_POS 3U
+#define STM32_OCTOSPI_SR_SMF_MSK (0x1UL << STM32_OCTOSPI_SR_SMF_POS)
+#define STM32_OCTOSPI_SR_SMF STM32_OCTOSPI_SR_SMF_MSK
+
+#define STM32_OCTOSPI_SR_FTF_POS 2U
+#define STM32_OCTOSPI_SR_FTF_MSK (0x1UL << STM32_OCTOSPI_SR_FTF_POS)
+#define STM32_OCTOSPI_SR_FTF STM32_OCTOSPI_SR_FTF_MSK
+
+#define STM32_OCTOSPI_SR_TCF_POS 1U
+#define STM32_OCTOSPI_SR_TCF_MSK (0x1UL << STM32_OCTOSPI_SR_TCF_POS)
+#define STM32_OCTOSPI_SR_TCF STM32_OCTOSPI_SR_TCF_MSK
+
+#define STM32_OCTOSPI_SR_TEF_POS 0U
+#define STM32_OCTOSPI_SR_TEF_MSK (0x1UL << STM32_OCTOSPI_SR_TEF_POS)
+#define STM32_OCTOSPI_SR_TEF STM32_OCTOSPI_SR_TEF_MSK
+
+/* Bit values for STM32_OCTOSPI_FCR */
+#define STM32_OCTOSPI_FCR_CTOF_POS 4U
+#define STM32_OCTOSPI_FCR_CTOF_MSK (0x1UL << STM32_OCTOSPI_FCR_CTOF_POS)
+#define STM32_OCTOSPI_FCR_CTOF STM32_OCTOSPI_FCR_CTOF_MSK
+
+#define STM32_OCTOSPI_FCR_CSMF_POS 3U
+#define STM32_OCTOSPI_FCR_CSMF_MSK (0x1UL << STM32_OCTOSPI_FCR_CSMF_POS)
+#define STM32_OCTOSPI_FCR_CSMF STM32_OCTOSPI_FCR_CSMF_MSK
+
+#define STM32_OCTOSPI_FCR_CTCF_POS 1U
+#define STM32_OCTOSPI_FCR_CTCF_MSK (0x1UL << STM32_OCTOSPI_FCR_CTCF_POS)
+#define STM32_OCTOSPI_FCR_CTCF STM32_OCTOSPI_FCR_CTCF_MSK
+
+#define STM32_OCTOSPI_FCR_CTEF_POS 0U
+#define STM32_OCTOSPI_FCR_CTEF_MSK (0x1UL << STM32_OCTOSPI_FCR_CTEF_POS)
+#define STM32_OCTOSPI_FCR_CTEF STM32_OCTOSPI_FCR_CTEF_MSK
+
+/* Bit values for STM32_OCTOSPI_CCR */
+#define STM32_OCTOSPI_CCR_SIOO_POS 31U
+#define STM32_OCTOSPI_CCR_SIOO_MSK (0x1UL << STM32_OCTOSPI_FCR_SIOO_POS)
+#define STM32_OCTOSPI_CCR_SIOO STM32_OCTOSPI_FCR_SIOO_MSK
+
+#define STM32_OCTOSPI_CCR_DQSE_POS 29U
+#define STM32_OCTOSPI_CCR_DQSE_MSK (0x1UL << STM32_OCTOSPI_FCR_DQSE_POS)
+#define STM32_OCTOSPI_CCR_DQSE STM32_OCTOSPI_FCR_DQSE_MSK
+
+#define STM32_OCTOSPI_CCR_DDTR_POS 27U
+#define STM32_OCTOSPI_CCR_DDTR_MSK (0x1UL << STM32_OCTOSPI_CCR_DDTR_POS)
+#define STM32_OCTOSPI_CCR_DDTR STM32_OCTOSPI_CCR_DDTR_MSK
+
+#define STM32_OCTOSPI_CCR_DMODE_POS 24U
+#define STM32_OCTOSPI_CCR_DMODE_MSK (0x1UL << STM32_OCTOSPI_CCR_DMODE_POS)
+#define STM32_OCTOSPI_CCR_DMODE_NONE (0UL << STM32_OCTOSPI_CCR_DMODE_POS)
+#define STM32_OCTOSPI_CCR_DMODE_1WIRE (1UL << STM32_OCTOSPI_CCR_DMODE_POS)
+#define STM32_OCTOSPI_CCR_DMODE_2WIRE (2UL << STM32_OCTOSPI_CCR_DMODE_POS)
+#define STM32_OCTOSPI_CCR_DMODE_4WIRE (3UL << STM32_OCTOSPI_CCR_DMODE_POS)
+#define STM32_OCTOSPI_CCR_DMODE_8WIRE (4UL << STM32_OCTOSPI_CCR_DMODE_POS)
+
+#define STM32_OCTOSPI_CCR_ABSIZE_POS 20U
+#define STM32_OCTOSPI_CCR_ABSIZE_MSK (0x1UL << STM32_OCTOSPI_CCR_ABSIZE_POS)
+#define STM32_OCTOSPI_CCR_ABSIZE_1BYTE (0UL << STM32_OCTOSPI_CCR_ABSIZE_POS)
+#define STM32_OCTOSPI_CCR_ABSIZE_2BYTES (1UL << STM32_OCTOSPI_CCR_ABSIZE_POS)
+#define STM32_OCTOSPI_CCR_ABSIZE_3BYTES (2UL << STM32_OCTOSPI_CCR_ABSIZE_POS)
+#define STM32_OCTOSPI_CCR_ABSIZE_4BYTES (3UL << STM32_OCTOSPI_CCR_ABSIZE_POS)
+
+#define STM32_OCTOSPI_CCR_ABDTR_POS 19U
+#define STM32_OCTOSPI_CCR_ABDTR_MSK (0x1UL << STM32_OCTOSPI_CCR_ABDTR_POS)
+#define STM32_OCTOSPI_CCR_ABDTR STM32_OCTOSPI_CCR_ABDTR_MSK
+
+#define STM32_OCTOSPI_CCR_ABMODE_POS 16U
+#define STM32_OCTOSPI_CCR_ABMODE_MSK (0x1UL << STM32_OCTOSPI_CCR_ABMODE_POS)
+#define STM32_OCTOSPI_CCR_ABMODE_NONE (0UL << STM32_OCTOSPI_CCR_ABMODE_POS)
+#define STM32_OCTOSPI_CCR_ABMODE_1WIRE (1UL << STM32_OCTOSPI_CCR_ABMODE_POS)
+#define STM32_OCTOSPI_CCR_ABMODE_2WIRE (2UL << STM32_OCTOSPI_CCR_ABMODE_POS)
+#define STM32_OCTOSPI_CCR_ABMODE_4WIRE (3UL << STM32_OCTOSPI_CCR_ABMODE_POS)
+#define STM32_OCTOSPI_CCR_ABMODE_8WIRE (4UL << STM32_OCTOSPI_CCR_ABMODE_POS)
+
+#define STM32_OCTOSPI_CCR_ADSIZE_POS 12U
+#define STM32_OCTOSPI_CCR_ADSIZE_MSK (0x1UL << STM32_OCTOSPI_CCR_ADSIZE_POS)
+#define STM32_OCTOSPI_CCR_ADSIZE_1BYTE (0UL << STM32_OCTOSPI_CCR_ADSIZE_POS)
+#define STM32_OCTOSPI_CCR_ADSIZE_2BYTES (1UL << STM32_OCTOSPI_CCR_ADSIZE_POS)
+#define STM32_OCTOSPI_CCR_ADSIZE_3BYTES (2UL << STM32_OCTOSPI_CCR_ADSIZE_POS)
+#define STM32_OCTOSPI_CCR_ADSIZE_4BYTES (3UL << STM32_OCTOSPI_CCR_ADSIZE_POS)
+
+#define STM32_OCTOSPI_CCR_ADDTR_POS 11U
+#define STM32_OCTOSPI_CCR_ADDTR_MSK (0x1UL << STM32_OCTOSPI_CCR_ADDTR_POS)
+#define STM32_OCTOSPI_CCR_ADDTR STM32_OCTOSPI_CCR_ADDTR_MSK
+
+#define STM32_OCTOSPI_CCR_ADMODE_POS 8U
+#define STM32_OCTOSPI_CCR_ADMODE_MSK (0x1UL << STM32_OCTOSPI_CCR_ADMODE_POS)
+#define STM32_OCTOSPI_CCR_ADMODE_NONE (0UL << STM32_OCTOSPI_CCR_ADMODE_POS)
+#define STM32_OCTOSPI_CCR_ADMODE_1WIRE (1UL << STM32_OCTOSPI_CCR_ADMODE_POS)
+#define STM32_OCTOSPI_CCR_ADMODE_2WIRE (2UL << STM32_OCTOSPI_CCR_ADMODE_POS)
+#define STM32_OCTOSPI_CCR_ADMODE_4WIRE (3UL << STM32_OCTOSPI_CCR_ADMODE_POS)
+#define STM32_OCTOSPI_CCR_ADMODE_8WIRE (4UL << STM32_OCTOSPI_CCR_ADMODE_POS)
+
+#define STM32_OCTOSPI_CCR_ISIZE_POS 4U
+#define STM32_OCTOSPI_CCR_ISIZE_MSK (0x1UL << STM32_OCTOSPI_CCR_ISIZE_POS)
+#define STM32_OCTOSPI_CCR_ISIZE_1BYTE (0UL << STM32_OCTOSPI_CCR_ISIZE_POS)
+#define STM32_OCTOSPI_CCR_ISIZE_2BYTES (1UL << STM32_OCTOSPI_CCR_ISIZE_POS)
+#define STM32_OCTOSPI_CCR_ISIZE_3BYTES (2UL << STM32_OCTOSPI_CCR_ISIZE_POS)
+#define STM32_OCTOSPI_CCR_ISIZE_4BYTES (3UL << STM32_OCTOSPI_CCR_ISIZE_POS)
+
+#define STM32_OCTOSPI_CCR_IDTR_POS 3U
+#define STM32_OCTOSPI_CCR_IDTR_MSK (0x1UL << STM32_OCTOSPI_CCR_IDTR_POS)
+#define STM32_OCTOSPI_CCR_IDTR STM32_OCTOSPI_CCR_IDTR_MSK
+
+#define STM32_OCTOSPI_CCR_IMODE_POS 0U
+#define STM32_OCTOSPI_CCR_IMODE_MSK (0x1UL << STM32_OCTOSPI_CCR_IMODE_POS)
+#define STM32_OCTOSPI_CCR_IMODE_NONE (0UL << STM32_OCTOSPI_CCR_IMODE_POS)
+#define STM32_OCTOSPI_CCR_IMODE_1WIRE (1UL << STM32_OCTOSPI_CCR_IMODE_POS)
+#define STM32_OCTOSPI_CCR_IMODE_2WIRE (2UL << STM32_OCTOSPI_CCR_IMODE_POS)
+#define STM32_OCTOSPI_CCR_IMODE_4WIRE (3UL << STM32_OCTOSPI_CCR_IMODE_POS)
+#define STM32_OCTOSPI_CCR_IMODE_8WIRE (4UL << STM32_OCTOSPI_CCR_IMODE_POS)
+
+/* Bit values for STM32_OCTOSPI_TCR */
+#define STM32_OCTOSPI_TCR_SSHIFT_POS 30U
+#define STM32_OCTOSPI_TCR_SSHIFT_MSK (0x1UL << STM32_OCTOSPI_TCR_SSHIFT_POS)
+#define STM32_OCTOSPI_TCR_SSHIFT STM32_OCTOSPI_TCR_SSHIFT_MSK
+
+#define STM32_OCTOSPI_TCR_DHQC_POS 28U
+#define STM32_OCTOSPI_TCR_DHQC_MSK (0x1UL << STM32_OCTOSPI_TCR_DHQC_POS)
+#define STM32_OCTOSPI_TCR_DHQC STM32_OCTOSPI_TCR_DHQC_MSK
+
+#define STM32_OCTOSPI_TCR_DCYC_POS 0U
+#define STM32_OCTOSPI_TCR_DCYC_MSK (0x1FUL << STM32_OCTOSPI_TCR_DCYC_POS)
+
+#endif /* !__ASSEMBLER__ */
diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h
index 574921c63e..1ec4370ef1 100644
--- a/chip/stm32/registers.h
+++ b/chip/stm32/registers.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -46,424 +46,429 @@
 #include "common.h"
 #include "compile_time_macros.h"
 
-
 #ifndef __ASSEMBLER__
 
 /* Register definitions */
 
 /* --- USART --- */
-#define STM32_USART_BASE(n)           CONCAT3(STM32_USART, n, _BASE)
+#define STM32_USART_BASE(n) CONCAT3(STM32_USART, n, _BASE)
 #define STM32_USART_REG(base, offset) REG32((base) + (offset))
 
-#define STM32_IRQ_USART(n)         CONCAT2(STM32_IRQ_USART, n)
+#define STM32_IRQ_USART(n) CONCAT2(STM32_IRQ_USART, n)
 
 /* --- TIMERS --- */
-#define STM32_TIM_BASE(n)          CONCAT3(STM32_TIM, n, _BASE)
-
-#define STM32_TIM_REG(n, offset) \
-		REG16(STM32_TIM_BASE(n) + (offset))
-#define STM32_TIM_REG32(n, offset) \
-		REG32(STM32_TIM_BASE(n) + (offset))
-
-#define STM32_TIM_CR1(n)           STM32_TIM_REG(n, 0x00)
-#define STM32_TIM_CR1_CEN		BIT(0)
-#define STM32_TIM_CR2(n)           STM32_TIM_REG(n, 0x04)
-#define STM32_TIM_SMCR(n)          STM32_TIM_REG(n, 0x08)
-#define STM32_TIM_DIER(n)          STM32_TIM_REG(n, 0x0C)
-#define STM32_TIM_SR(n)            STM32_TIM_REG(n, 0x10)
-#define STM32_TIM_EGR(n)           STM32_TIM_REG(n, 0x14)
-#define STM32_TIM_EGR_UG		BIT(0)
-#define STM32_TIM_CCMR1(n)         STM32_TIM_REG(n, 0x18)
-#define STM32_TIM_CCMR1_OC1PE		BIT(2)
+#define STM32_TIM_BASE(n) CONCAT3(STM32_TIM, n, _BASE)
+
+#define STM32_TIM_REG(n, offset) REG16(STM32_TIM_BASE(n) + (offset))
+#define STM32_TIM_REG32(n, offset) REG32(STM32_TIM_BASE(n) + (offset))
+
+#define STM32_TIM_CR1(n) STM32_TIM_REG(n, 0x00)
+#define STM32_TIM_CR1_CEN BIT(0)
+#define STM32_TIM_CR2(n) STM32_TIM_REG(n, 0x04)
+#define STM32_TIM_SMCR(n) STM32_TIM_REG(n, 0x08)
+#define STM32_TIM_DIER(n) STM32_TIM_REG(n, 0x0C)
+#define STM32_TIM_SR(n) STM32_TIM_REG(n, 0x10)
+#define STM32_TIM_EGR(n) STM32_TIM_REG(n, 0x14)
+#define STM32_TIM_EGR_UG BIT(0)
+#define STM32_TIM_CCMR1(n) STM32_TIM_REG(n, 0x18)
+#define STM32_TIM_CCMR1_OC1PE BIT(2)
 /* Use in place of TIM_CCMR1_OC1M_0 through 2 from STM documentation. */
-#define STM32_TIM_CCMR1_OC1M(n)    (((n) & 0x7) << 4)
-#define STM32_TIM_CCMR1_OC1M_MASK              STM32_TIM_CCMR1_OC1M(~0)
-#define STM32_TIM_CCMR1_OC1M_FROZEN            STM32_TIM_CCMR1_OC1M(0x0)
-#define STM32_TIM_CCMR1_OC1M_ACTIVE_ON_MATCH   STM32_TIM_CCMR1_OC1M(0x1)
+#define STM32_TIM_CCMR1_OC1M(n) (((n)&0x7) << 4)
+#define STM32_TIM_CCMR1_OC1M_MASK STM32_TIM_CCMR1_OC1M(~0)
+#define STM32_TIM_CCMR1_OC1M_FROZEN STM32_TIM_CCMR1_OC1M(0x0)
+#define STM32_TIM_CCMR1_OC1M_ACTIVE_ON_MATCH STM32_TIM_CCMR1_OC1M(0x1)
 #define STM32_TIM_CCMR1_OC1M_INACTIVE_ON_MATCH STM32_TIM_CCMR1_OC1M(0x2)
-#define STM32_TIM_CCMR1_OC1M_TOGGLE            STM32_TIM_CCMR1_OC1M(0x3)
-#define STM32_TIM_CCMR1_OC1M_FORCE_INACTIVE    STM32_TIM_CCMR1_OC1M(0x4)
-#define STM32_TIM_CCMR1_OC1M_FORCE_ACTIVE      STM32_TIM_CCMR1_OC1M(0x5)
-#define STM32_TIM_CCMR1_OC1M_PWM_MODE_1        STM32_TIM_CCMR1_OC1M(0x6)
-#define STM32_TIM_CCMR1_OC1M_PWM_MODE_2        STM32_TIM_CCMR1_OC1M(0x7)
-#define STM32_TIM_CCMR2(n)         STM32_TIM_REG(n, 0x1C)
-#define STM32_TIM_CCER(n)          STM32_TIM_REG(n, 0x20)
-#define STM32_TIM_CCER_CC1E		BIT(0)
-#define STM32_TIM_CCER_CC1P		BIT(1)
-#define STM32_TIM_CCER_CC1NE		BIT(2)
-#define STM32_TIM_CCER_CC1NP		BIT(3)
-#define STM32_TIM_CNT(n)           STM32_TIM_REG(n, 0x24)
-#define STM32_TIM_PSC(n)           STM32_TIM_REG(n, 0x28)
-#define STM32_TIM_ARR(n)           STM32_TIM_REG(n, 0x2C)
-#define STM32_TIM_RCR(n)           STM32_TIM_REG(n, 0x30)
-#define STM32_TIM_CCR1(n)          STM32_TIM_REG(n, 0x34)
-#define STM32_TIM_CCR2(n)          STM32_TIM_REG(n, 0x38)
-#define STM32_TIM_CCR3(n)          STM32_TIM_REG(n, 0x3C)
-#define STM32_TIM_CCR4(n)          STM32_TIM_REG(n, 0x40)
-#define STM32_TIM_BDTR(n)          STM32_TIM_REG(n, 0x44)
-#define STM32_TIM_BDTR_MOE		BIT(15)
-#define STM32_TIM_DCR(n)           STM32_TIM_REG(n, 0x48)
-#define STM32_TIM_DMAR(n)          STM32_TIM_REG(n, 0x4C)
-#define STM32_TIM_OR(n)            STM32_TIM_REG(n, 0x50)
-
-#define STM32_TIM_CCRx(n, x)       STM32_TIM_REG(n, 0x34 + ((x) - 1) * 4)
-
-#define STM32_TIM32_CNT(n)         STM32_TIM_REG32(n, 0x24)
-#define STM32_TIM32_ARR(n)         STM32_TIM_REG32(n, 0x2C)
-#define STM32_TIM32_CCR1(n)        STM32_TIM_REG32(n, 0x34)
-#define STM32_TIM32_CCR2(n)        STM32_TIM_REG32(n, 0x38)
-#define STM32_TIM32_CCR3(n)        STM32_TIM_REG32(n, 0x3C)
-#define STM32_TIM32_CCR4(n)        STM32_TIM_REG32(n, 0x40)
+#define STM32_TIM_CCMR1_OC1M_TOGGLE STM32_TIM_CCMR1_OC1M(0x3)
+#define STM32_TIM_CCMR1_OC1M_FORCE_INACTIVE STM32_TIM_CCMR1_OC1M(0x4)
+#define STM32_TIM_CCMR1_OC1M_FORCE_ACTIVE STM32_TIM_CCMR1_OC1M(0x5)
+#define STM32_TIM_CCMR1_OC1M_PWM_MODE_1 STM32_TIM_CCMR1_OC1M(0x6)
+#define STM32_TIM_CCMR1_OC1M_PWM_MODE_2 STM32_TIM_CCMR1_OC1M(0x7)
+#define STM32_TIM_CCMR2(n) STM32_TIM_REG(n, 0x1C)
+#define STM32_TIM_CCER(n) STM32_TIM_REG(n, 0x20)
+#define STM32_TIM_CCER_CC1E BIT(0)
+#define STM32_TIM_CCER_CC1P BIT(1)
+#define STM32_TIM_CCER_CC1NE BIT(2)
+#define STM32_TIM_CCER_CC1NP BIT(3)
+#define STM32_TIM_CNT(n) STM32_TIM_REG(n, 0x24)
+#define STM32_TIM_PSC(n) STM32_TIM_REG(n, 0x28)
+#define STM32_TIM_ARR(n) STM32_TIM_REG(n, 0x2C)
+#define STM32_TIM_RCR(n) STM32_TIM_REG(n, 0x30)
+#define STM32_TIM_CCR1(n) STM32_TIM_REG(n, 0x34)
+#define STM32_TIM_CCR2(n) STM32_TIM_REG(n, 0x38)
+#define STM32_TIM_CCR3(n) STM32_TIM_REG(n, 0x3C)
+#define STM32_TIM_CCR4(n) STM32_TIM_REG(n, 0x40)
+#define STM32_TIM_BDTR(n) STM32_TIM_REG(n, 0x44)
+#define STM32_TIM_BDTR_MOE BIT(15)
+#define STM32_TIM_DCR(n) STM32_TIM_REG(n, 0x48)
+#define STM32_TIM_DMAR(n) STM32_TIM_REG(n, 0x4C)
+#define STM32_TIM_OR(n) STM32_TIM_REG(n, 0x50)
+
+#define STM32_TIM_CCRx(n, x) STM32_TIM_REG(n, 0x34 + ((x)-1) * 4)
+
+#define STM32_TIM32_CNT(n) STM32_TIM_REG32(n, 0x24)
+#define STM32_TIM32_ARR(n) STM32_TIM_REG32(n, 0x2C)
+#define STM32_TIM32_CCR1(n) STM32_TIM_REG32(n, 0x34)
+#define STM32_TIM32_CCR2(n) STM32_TIM_REG32(n, 0x38)
+#define STM32_TIM32_CCR3(n) STM32_TIM_REG32(n, 0x3C)
+#define STM32_TIM32_CCR4(n) STM32_TIM_REG32(n, 0x40)
 /* Timer registers as struct */
 struct timer_ctlr {
-	unsigned cr1;
-	unsigned cr2;
-	unsigned smcr;
-	unsigned dier;
+	unsigned int cr1;
+	unsigned int cr2;
+	unsigned int smcr;
+	unsigned int dier;
 
-	unsigned sr;
-	unsigned egr;
-	unsigned ccmr1;
-	unsigned ccmr2;
+	unsigned int sr;
+	unsigned int egr;
+	unsigned int ccmr1;
+	unsigned int ccmr2;
 
-	unsigned ccer;
-	unsigned cnt;
-	unsigned psc;
-	unsigned arr;
+	unsigned int ccer;
+	unsigned int cnt;
+	unsigned int psc;
+	unsigned int arr;
 
-	unsigned ccr[5]; /* ccr[0] = reserved30 */
+	unsigned int ccr[5]; /* ccr[0] = reserved30 */
 
-	unsigned bdtr;
-	unsigned dcr;
-	unsigned dmar;
+	unsigned int bdtr;
+	unsigned int dcr;
+	unsigned int dmar;
 
-	unsigned or;
+	unsigned int option_register;
 };
 /* Must be volatile, or compiler optimizes out repeated accesses */
 typedef volatile struct timer_ctlr timer_ctlr_t;
 
+#define IRQ_TIM(n) CONCAT2(STM32_IRQ_TIM, n)
+
 /* --- Low power timers --- */
-#define STM32_LPTIM_BASE(n)          CONCAT3(STM32_LPTIM, n, _BASE)
-
-#define STM32_LPTIM_REG(n, offset)   REG32(STM32_LPTIM_BASE(n) + (offset))
-
-#define STM32_LPTIM_ISR(n)           STM32_LPTIM_REG(n, 0x00)
-#define STM32_LPTIM_ICR(n)           STM32_LPTIM_REG(n, 0x04)
-#define STM32_LPTIM_IER(n)           STM32_LPTIM_REG(n, 0x08)
-#define STM32_LPTIM_INT_DOWN		BIT(6)
-#define STM32_LPTIM_INT_UP		BIT(5)
-#define STM32_LPTIM_INT_ARROK		BIT(4)
-#define STM32_LPTIM_INT_CMPOK		BIT(3)
-#define STM32_LPTIM_INT_EXTTRIG		BIT(2)
-#define STM32_LPTIM_INT_ARRM		BIT(1)
-#define STM32_LPTIM_INT_CMPM		BIT(0)
-#define STM32_LPTIM_CFGR(n)          STM32_LPTIM_REG(n, 0x0C)
-#define STM32_LPTIM_CR(n)            STM32_LPTIM_REG(n, 0x10)
-#define STM32_LPTIM_CR_RSTARE		BIT(4)
-#define STM32_LPTIM_CR_COUNTRST		BIT(3)
-#define STM32_LPTIM_CR_CNTSTRT		BIT(2)
-#define STM32_LPTIM_CR_SNGSTRT		BIT(1)
-#define STM32_LPTIM_CR_ENABLE		BIT(0)
-#define STM32_LPTIM_CMP(n)           STM32_LPTIM_REG(n, 0x14)
-#define STM32_LPTIM_ARR(n)           STM32_LPTIM_REG(n, 0x18)
-#define STM32_LPTIM_CNT(n)           STM32_LPTIM_REG(n, 0x1C)
-#define STM32_LPTIM_CFGR2(n)         STM32_LPTIM_REG(n, 0x24)
+#define STM32_LPTIM_BASE(n) CONCAT3(STM32_LPTIM, n, _BASE)
+
+#define STM32_LPTIM_REG(n, offset) REG32(STM32_LPTIM_BASE(n) + (offset))
+
+#define STM32_LPTIM_ISR(n) STM32_LPTIM_REG(n, 0x00)
+#define STM32_LPTIM_ICR(n) STM32_LPTIM_REG(n, 0x04)
+#define STM32_LPTIM_IER(n) STM32_LPTIM_REG(n, 0x08)
+#define STM32_LPTIM_INT_DOWN BIT(6)
+#define STM32_LPTIM_INT_UP BIT(5)
+#define STM32_LPTIM_INT_ARROK BIT(4)
+#define STM32_LPTIM_INT_CMPOK BIT(3)
+#define STM32_LPTIM_INT_EXTTRIG BIT(2)
+#define STM32_LPTIM_INT_ARRM BIT(1)
+#define STM32_LPTIM_INT_CMPM BIT(0)
+#define STM32_LPTIM_CFGR(n) STM32_LPTIM_REG(n, 0x0C)
+#define STM32_LPTIM_CR(n) STM32_LPTIM_REG(n, 0x10)
+#define STM32_LPTIM_CR_RSTARE BIT(4)
+#define STM32_LPTIM_CR_COUNTRST BIT(3)
+#define STM32_LPTIM_CR_CNTSTRT BIT(2)
+#define STM32_LPTIM_CR_SNGSTRT BIT(1)
+#define STM32_LPTIM_CR_ENABLE BIT(0)
+#define STM32_LPTIM_CMP(n) STM32_LPTIM_REG(n, 0x14)
+#define STM32_LPTIM_ARR(n) STM32_LPTIM_REG(n, 0x18)
+#define STM32_LPTIM_CNT(n) STM32_LPTIM_REG(n, 0x1C)
+#define STM32_LPTIM_CFGR2(n) STM32_LPTIM_REG(n, 0x24)
 
 /* --- GPIO --- */
 
-#define GPIO_A                       STM32_GPIOA_BASE
-#define GPIO_B                       STM32_GPIOB_BASE
-#define GPIO_C                       STM32_GPIOC_BASE
-#define GPIO_D                       STM32_GPIOD_BASE
-#define GPIO_E                       STM32_GPIOE_BASE
-#define GPIO_F                       STM32_GPIOF_BASE
-#define GPIO_G                       STM32_GPIOG_BASE
-#define GPIO_H                       STM32_GPIOH_BASE
-#define GPIO_I                       STM32_GPIOI_BASE
-#define GPIO_J                       STM32_GPIOJ_BASE
-#define GPIO_K                       STM32_GPIOK_BASE
+#define GPIO_A STM32_GPIOA_BASE
+#define GPIO_B STM32_GPIOB_BASE
+#define GPIO_C STM32_GPIOC_BASE
+#define GPIO_D STM32_GPIOD_BASE
+#define GPIO_E STM32_GPIOE_BASE
+#define GPIO_F STM32_GPIOF_BASE
+#define GPIO_G STM32_GPIOG_BASE
+#define GPIO_H STM32_GPIOH_BASE
+#define GPIO_I STM32_GPIOI_BASE
+#define GPIO_J STM32_GPIOJ_BASE
+#define GPIO_K STM32_GPIOK_BASE
 
 #define UNIMPLEMENTED_GPIO_BANK GPIO_A
 
-
 /* --- I2C --- */
-#define STM32_I2C1_PORT             0
-#define STM32_I2C2_PORT             1
-#define STM32_I2C3_PORT             2
-#define STM32_FMPI2C4_PORT          3
-
+#define STM32_I2C1_PORT 0
+#define STM32_I2C2_PORT 1
+#define STM32_I2C3_PORT 2
+#define STM32_FMPI2C4_PORT 3
+
+#if defined(CHIP_FAMILY_STM32L4) || defined(CHIP_FAMILY_STM32L5)
+#define stm32_i2c_reg(port, offset)                                        \
+	((uint16_t *)(((port) == 3 ? STM32_I2C4_BASE :                     \
+				     (STM32_I2C1_BASE + ((port)*0x400))) + \
+		      (offset)))
+#else
 #define stm32_i2c_reg(port, offset) \
-	((uint16_t *)((STM32_I2C1_BASE + ((port) * 0x400)) + (offset)))
+	((uint16_t *)((STM32_I2C1_BASE + ((port)*0x400)) + (offset)))
+#endif
+
 /* --- Power / Reset / Clocks --- */
-#define STM32_PWR_CR                REG32(STM32_PWR_BASE + 0x00)
-#define STM32_PWR_CR_LPSDSR		(1 << 0)
-#define STM32_PWR_CR_FLPS		(1 << 9)
-#define STM32_PWR_CR_SVOS5		(1 << 14)
-#define STM32_PWR_CR_SVOS4		(2 << 14)
-#define STM32_PWR_CR_SVOS3		(3 << 14)
-#define STM32_PWR_CR_SVOS_MASK		(3 << 14)
+#define STM32_PWR_CR REG32(STM32_PWR_BASE + 0x00)
+#define STM32_PWR_CR_LPSDSR (1 << 0)
+#define STM32_PWR_CR_FLPS (1 << 9)
+#define STM32_PWR_CR_SVOS5 (1 << 14)
+#define STM32_PWR_CR_SVOS4 (2 << 14)
+#define STM32_PWR_CR_SVOS3 (3 << 14)
+#define STM32_PWR_CR_SVOS_MASK (3 << 14)
 
 /* RTC domain control register */
-#define STM32_RCC_BDCR_BDRST		BIT(16)
-#define STM32_RCC_BDCR_RTCEN		BIT(15)
-#define STM32_RCC_BDCR_LSERDY		BIT(1)
-#define STM32_RCC_BDCR_LSEON		BIT(0)
-#define  BDCR_RTCSEL_MASK		((0x3) << 8)
-#define  BDCR_RTCSEL(source)		(((source) << 8) & BDCR_RTCSEL_MASK)
-#define  BDCR_SRC_LSE			0x1
-#define  BDCR_SRC_LSI			0x2
-#define  BDCR_SRC_HSE			0x3
+#define STM32_RCC_BDCR_BDRST BIT(16)
+#define STM32_RCC_BDCR_RTCEN BIT(15)
+#define STM32_RCC_BDCR_LSERDY BIT(1)
+#define STM32_RCC_BDCR_LSEON BIT(0)
+#define BDCR_RTCSEL_MASK ((0x3) << 8)
+#define BDCR_RTCSEL(source) (((source) << 8) & BDCR_RTCSEL_MASK)
+#define BDCR_SRC_LSE 0x1
+#define BDCR_SRC_LSI 0x2
+#define BDCR_SRC_HSE 0x3
 /* Peripheral bits for RCC_APB/AHB and DBGMCU regs */
-#define STM32_RCC_PB1_TIM2		BIT(0)
-#define STM32_RCC_PB1_TIM3		BIT(1)
-#define STM32_RCC_PB1_TIM4		BIT(2)
-#define STM32_RCC_PB1_TIM5		BIT(3)
-#define STM32_RCC_PB1_TIM6		BIT(4)
-#define STM32_RCC_PB1_TIM7		BIT(5)
-#define STM32_RCC_PB1_TIM12             BIT(6) /* STM32H7 */
-#define STM32_RCC_PB1_TIM13             BIT(7) /* STM32H7 */
-#define STM32_RCC_PB1_TIM14             BIT(8) /* STM32H7 */
-#define STM32_RCC_PB1_RTC		BIT(10) /* DBGMCU only */
-#define STM32_RCC_PB1_WWDG		BIT(11)
-#define STM32_RCC_PB1_IWDG		BIT(12) /* DBGMCU only */
-#define STM32_RCC_PB1_SPI2		BIT(14)
-#define STM32_RCC_PB1_SPI3		BIT(15)
-#define STM32_RCC_PB1_USART2		BIT(17)
-#define STM32_RCC_PB1_USART3		BIT(18)
-#define STM32_RCC_PB1_USART4		BIT(19)
-#define STM32_RCC_PB1_USART5		BIT(20)
-#define STM32_RCC_PB1_PWREN		BIT(28)
-#define STM32_RCC_PB2_SPI1		BIT(12)
+#define STM32_RCC_PB1_TIM2 BIT(0)
+#define STM32_RCC_PB1_TIM3 BIT(1)
+#define STM32_RCC_PB1_TIM4 BIT(2)
+#define STM32_RCC_PB1_TIM5 BIT(3)
+#define STM32_RCC_PB1_TIM6 BIT(4)
+#define STM32_RCC_PB1_TIM7 BIT(5)
+#define STM32_RCC_PB1_TIM12 BIT(6) /* STM32H7 */
+#define STM32_RCC_PB1_TIM13 BIT(7) /* STM32H7 */
+#define STM32_RCC_PB1_TIM14 BIT(8) /* STM32H7 */
+#define STM32_RCC_PB1_RTC BIT(10) /* DBGMCU only */
+#define STM32_RCC_PB1_WWDG BIT(11)
+#define STM32_RCC_PB1_IWDG BIT(12) /* DBGMCU only */
+#define STM32_RCC_PB1_SPI2 BIT(14)
+#define STM32_RCC_PB1_SPI3 BIT(15)
+#define STM32_RCC_PB1_USART2 BIT(17)
+#define STM32_RCC_PB1_USART3 BIT(18)
+#define STM32_RCC_PB1_USART4 BIT(19)
+#define STM32_RCC_PB1_USART5 BIT(20)
+#define STM32_RCC_PB1_PWREN BIT(28)
+#define STM32_RCC_PB2_SPI1 BIT(12)
 /* Reset causes definitions */
 
 /* --- Watchdogs --- */
 
-#define STM32_WWDG_CR               REG32(STM32_WWDG_BASE + 0x00)
-#define STM32_WWDG_CFR              REG32(STM32_WWDG_BASE + 0x04)
-#define STM32_WWDG_SR               REG32(STM32_WWDG_BASE + 0x08)
-
-#define STM32_WWDG_TB_8             (3 << 7)
-#define STM32_WWDG_EWI              BIT(9)
-
-#define STM32_IWDG_KR               REG32(STM32_IWDG_BASE + 0x00)
-#define STM32_IWDG_KR_UNLOCK		0x5555
-#define STM32_IWDG_KR_RELOAD		0xaaaa
-#define STM32_IWDG_KR_START		0xcccc
-#define STM32_IWDG_PR               REG32(STM32_IWDG_BASE + 0x04)
-#define STM32_IWDG_RLR              REG32(STM32_IWDG_BASE + 0x08)
-#define STM32_IWDG_RLR_MAX		0x0fff
-#define STM32_IWDG_SR               REG32(STM32_IWDG_BASE + 0x0C)
-#define STM32_IWDG_SR_WVU		BIT(2)
-#define STM32_IWDG_SR_RVU		BIT(1)
-#define STM32_IWDG_SR_PVU		BIT(0)
-#define STM32_IWDG_WINR             REG32(STM32_IWDG_BASE + 0x10)
+#define STM32_WWDG_CR REG32(STM32_WWDG_BASE + 0x00)
+#define STM32_WWDG_CFR REG32(STM32_WWDG_BASE + 0x04)
+#define STM32_WWDG_SR REG32(STM32_WWDG_BASE + 0x08)
+
+#define STM32_WWDG_TB_8 (3 << 7)
+#define STM32_WWDG_EWI BIT(9)
+
+#define STM32_IWDG_KR REG32(STM32_IWDG_BASE + 0x00)
+#define STM32_IWDG_KR_UNLOCK 0x5555
+#define STM32_IWDG_KR_RELOAD 0xaaaa
+#define STM32_IWDG_KR_START 0xcccc
+#define STM32_IWDG_PR REG32(STM32_IWDG_BASE + 0x04)
+#define STM32_IWDG_RLR REG32(STM32_IWDG_BASE + 0x08)
+#define STM32_IWDG_RLR_MAX 0x0fff
+#define STM32_IWDG_SR REG32(STM32_IWDG_BASE + 0x0C)
+#define STM32_IWDG_SR_WVU BIT(2)
+#define STM32_IWDG_SR_RVU BIT(1)
+#define STM32_IWDG_SR_PVU BIT(0)
+#define STM32_IWDG_WINR REG32(STM32_IWDG_BASE + 0x10)
 
 /* --- Real-Time Clock --- */
 /* --- Debug --- */
-#define STM32_DBGMCU_IDCODE         REG32(STM32_DBGMCU_BASE + 0x00)
-#define STM32_DBGMCU_CR             REG32(STM32_DBGMCU_BASE + 0x04)
+#define STM32_DBGMCU_IDCODE REG32(STM32_DBGMCU_BASE + 0x00)
+#define STM32_DBGMCU_CR REG32(STM32_DBGMCU_BASE + 0x04)
 /* --- Routing interface --- */
 /* STM32L1xx only */
-#define STM32_RI_ICR                REG32(STM32_COMP_BASE + 0x04)
-#define STM32_RI_ASCR1              REG32(STM32_COMP_BASE + 0x08)
-#define STM32_RI_ASCR2              REG32(STM32_COMP_BASE + 0x0C)
-#define STM32_RI_HYSCR1             REG32(STM32_COMP_BASE + 0x10)
-#define STM32_RI_HYSCR2             REG32(STM32_COMP_BASE + 0x14)
-#define STM32_RI_HYSCR3             REG32(STM32_COMP_BASE + 0x18)
-#define STM32_RI_AMSR1              REG32(STM32_COMP_BASE + 0x1C)
-#define STM32_RI_CMR1               REG32(STM32_COMP_BASE + 0x20)
-#define STM32_RI_CICR1              REG32(STM32_COMP_BASE + 0x24)
-#define STM32_RI_AMSR2              REG32(STM32_COMP_BASE + 0x28)
-#define STM32_RI_CMR2               REG32(STM32_COMP_BASE + 0x30)
-#define STM32_RI_CICR2              REG32(STM32_COMP_BASE + 0x34)
-#define STM32_RI_AMSR3              REG32(STM32_COMP_BASE + 0x38)
-#define STM32_RI_CMR3               REG32(STM32_COMP_BASE + 0x3C)
-#define STM32_RI_CICR3              REG32(STM32_COMP_BASE + 0x40)
-#define STM32_RI_AMSR4              REG32(STM32_COMP_BASE + 0x44)
-#define STM32_RI_CMR4               REG32(STM32_COMP_BASE + 0x48)
-#define STM32_RI_CICR4              REG32(STM32_COMP_BASE + 0x4C)
-#define STM32_RI_AMSR5              REG32(STM32_COMP_BASE + 0x50)
-#define STM32_RI_CMR5               REG32(STM32_COMP_BASE + 0x54)
-#define STM32_RI_CICR5              REG32(STM32_COMP_BASE + 0x58)
+#define STM32_RI_ICR REG32(STM32_COMP_BASE + 0x04)
+#define STM32_RI_ASCR1 REG32(STM32_COMP_BASE + 0x08)
+#define STM32_RI_ASCR2 REG32(STM32_COMP_BASE + 0x0C)
+#define STM32_RI_HYSCR1 REG32(STM32_COMP_BASE + 0x10)
+#define STM32_RI_HYSCR2 REG32(STM32_COMP_BASE + 0x14)
+#define STM32_RI_HYSCR3 REG32(STM32_COMP_BASE + 0x18)
+#define STM32_RI_AMSR1 REG32(STM32_COMP_BASE + 0x1C)
+#define STM32_RI_CMR1 REG32(STM32_COMP_BASE + 0x20)
+#define STM32_RI_CICR1 REG32(STM32_COMP_BASE + 0x24)
+#define STM32_RI_AMSR2 REG32(STM32_COMP_BASE + 0x28)
+#define STM32_RI_CMR2 REG32(STM32_COMP_BASE + 0x30)
+#define STM32_RI_CICR2 REG32(STM32_COMP_BASE + 0x34)
+#define STM32_RI_AMSR3 REG32(STM32_COMP_BASE + 0x38)
+#define STM32_RI_CMR3 REG32(STM32_COMP_BASE + 0x3C)
+#define STM32_RI_CICR3 REG32(STM32_COMP_BASE + 0x40)
+#define STM32_RI_AMSR4 REG32(STM32_COMP_BASE + 0x44)
+#define STM32_RI_CMR4 REG32(STM32_COMP_BASE + 0x48)
+#define STM32_RI_CICR4 REG32(STM32_COMP_BASE + 0x4C)
+#define STM32_RI_AMSR5 REG32(STM32_COMP_BASE + 0x50)
+#define STM32_RI_CMR5 REG32(STM32_COMP_BASE + 0x54)
+#define STM32_RI_CICR5 REG32(STM32_COMP_BASE + 0x58)
 
 /* --- DAC --- */
-#define STM32_DAC_CR               REG32(STM32_DAC_BASE + 0x00)
-#define STM32_DAC_SWTRIGR          REG32(STM32_DAC_BASE + 0x04)
-#define STM32_DAC_DHR12R1          REG32(STM32_DAC_BASE + 0x08)
-#define STM32_DAC_DHR12L1          REG32(STM32_DAC_BASE + 0x0C)
-#define STM32_DAC_DHR8R1           REG32(STM32_DAC_BASE + 0x10)
-#define STM32_DAC_DHR12R2          REG32(STM32_DAC_BASE + 0x14)
-#define STM32_DAC_DHR12L2          REG32(STM32_DAC_BASE + 0x18)
-#define STM32_DAC_DHR8R2           REG32(STM32_DAC_BASE + 0x1C)
-#define STM32_DAC_DHR12RD          REG32(STM32_DAC_BASE + 0x20)
-#define STM32_DAC_DHR12LD          REG32(STM32_DAC_BASE + 0x24)
-#define STM32_DAC_DHR8RD           REG32(STM32_DAC_BASE + 0x28)
-#define STM32_DAC_DOR1             REG32(STM32_DAC_BASE + 0x2C)
-#define STM32_DAC_DOR2             REG32(STM32_DAC_BASE + 0x30)
-#define STM32_DAC_SR               REG32(STM32_DAC_BASE + 0x34)
-
-#define STM32_DAC_CR_DMAEN2        BIT(28)
-#define STM32_DAC_CR_TSEL2_SWTRG   (7 << 19)
-#define STM32_DAC_CR_TSEL2_TMR4    (5 << 19)
-#define STM32_DAC_CR_TSEL2_TMR2    (4 << 19)
-#define STM32_DAC_CR_TSEL2_TMR9    (3 << 19)
-#define STM32_DAC_CR_TSEL2_TMR7    (2 << 19)
-#define STM32_DAC_CR_TSEL2_TMR6    (0 << 19)
-#define STM32_DAC_CR_TSEL2_MASK    (7 << 19)
-#define STM32_DAC_CR_TEN2          BIT(18)
-#define STM32_DAC_CR_BOFF2         BIT(17)
-#define STM32_DAC_CR_EN2           BIT(16)
-#define STM32_DAC_CR_DMAEN1        BIT(12)
-#define STM32_DAC_CR_TSEL1_SWTRG   (7 << 3)
-#define STM32_DAC_CR_TSEL1_TMR4    (5 << 3)
-#define STM32_DAC_CR_TSEL1_TMR2    (4 << 3)
-#define STM32_DAC_CR_TSEL1_TMR9    (3 << 3)
-#define STM32_DAC_CR_TSEL1_TMR7    (2 << 3)
-#define STM32_DAC_CR_TSEL1_TMR6    (0 << 3)
-#define STM32_DAC_CR_TSEL1_MASK    (7 << 3)
-#define STM32_DAC_CR_TEN1          BIT(2)
-#define STM32_DAC_CR_BOFF1         BIT(1)
-#define STM32_DAC_CR_EN1           BIT(0)
+#define STM32_DAC_CR REG32(STM32_DAC_BASE + 0x00)
+#define STM32_DAC_SWTRIGR REG32(STM32_DAC_BASE + 0x04)
+#define STM32_DAC_DHR12R1 REG32(STM32_DAC_BASE + 0x08)
+#define STM32_DAC_DHR12L1 REG32(STM32_DAC_BASE + 0x0C)
+#define STM32_DAC_DHR8R1 REG32(STM32_DAC_BASE + 0x10)
+#define STM32_DAC_DHR12R2 REG32(STM32_DAC_BASE + 0x14)
+#define STM32_DAC_DHR12L2 REG32(STM32_DAC_BASE + 0x18)
+#define STM32_DAC_DHR8R2 REG32(STM32_DAC_BASE + 0x1C)
+#define STM32_DAC_DHR12RD REG32(STM32_DAC_BASE + 0x20)
+#define STM32_DAC_DHR12LD REG32(STM32_DAC_BASE + 0x24)
+#define STM32_DAC_DHR8RD REG32(STM32_DAC_BASE + 0x28)
+#define STM32_DAC_DOR1 REG32(STM32_DAC_BASE + 0x2C)
+#define STM32_DAC_DOR2 REG32(STM32_DAC_BASE + 0x30)
+#define STM32_DAC_SR REG32(STM32_DAC_BASE + 0x34)
+
+#define STM32_DAC_CR_DMAEN2 BIT(28)
+#define STM32_DAC_CR_TSEL2_SWTRG (7 << 19)
+#define STM32_DAC_CR_TSEL2_TMR4 (5 << 19)
+#define STM32_DAC_CR_TSEL2_TMR2 (4 << 19)
+#define STM32_DAC_CR_TSEL2_TMR9 (3 << 19)
+#define STM32_DAC_CR_TSEL2_TMR7 (2 << 19)
+#define STM32_DAC_CR_TSEL2_TMR6 (0 << 19)
+#define STM32_DAC_CR_TSEL2_MASK (7 << 19)
+#define STM32_DAC_CR_TEN2 BIT(18)
+#define STM32_DAC_CR_BOFF2 BIT(17)
+#define STM32_DAC_CR_EN2 BIT(16)
+#define STM32_DAC_CR_DMAEN1 BIT(12)
+#define STM32_DAC_CR_TSEL1_SWTRG (7 << 3)
+#define STM32_DAC_CR_TSEL1_TMR4 (5 << 3)
+#define STM32_DAC_CR_TSEL1_TMR2 (4 << 3)
+#define STM32_DAC_CR_TSEL1_TMR9 (3 << 3)
+#define STM32_DAC_CR_TSEL1_TMR7 (2 << 3)
+#define STM32_DAC_CR_TSEL1_TMR6 (0 << 3)
+#define STM32_DAC_CR_TSEL1_MASK (7 << 3)
+#define STM32_DAC_CR_TEN1 BIT(2)
+#define STM32_DAC_CR_BOFF1 BIT(1)
+#define STM32_DAC_CR_EN1 BIT(0)
 /* --- CRC --- */
-#define STM32_CRC_DR                REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR32              REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR16              REG16(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR8               REG8(STM32_CRC_BASE + 0x0)
-
-#define STM32_CRC_IDR               REG32(STM32_CRC_BASE + 0x4)
-#define STM32_CRC_CR                REG32(STM32_CRC_BASE + 0x8)
-#define STM32_CRC_INIT              REG32(STM32_CRC_BASE + 0x10)
-#define STM32_CRC_POL               REG32(STM32_CRC_BASE + 0x14)
-
-#define STM32_CRC_CR_RESET          BIT(0)
-#define STM32_CRC_CR_POLYSIZE_32    (0 << 3)
-#define STM32_CRC_CR_POLYSIZE_16    (1 << 3)
-#define STM32_CRC_CR_POLYSIZE_8     (2 << 3)
-#define STM32_CRC_CR_POLYSIZE_7     (3 << 3)
-#define STM32_CRC_CR_REV_IN_BYTE    (1 << 5)
-#define STM32_CRC_CR_REV_IN_HWORD   (2 << 5)
-#define STM32_CRC_CR_REV_IN_WORD    (3 << 5)
-#define STM32_CRC_CR_REV_OUT        BIT(7)
+#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0)
+
+#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4)
+#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8)
+#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10)
+#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14)
+
+#define STM32_CRC_CR_RESET BIT(0)
+#define STM32_CRC_CR_POLYSIZE_32 (0 << 3)
+#define STM32_CRC_CR_POLYSIZE_16 (1 << 3)
+#define STM32_CRC_CR_POLYSIZE_8 (2 << 3)
+#define STM32_CRC_CR_POLYSIZE_7 (3 << 3)
+#define STM32_CRC_CR_REV_IN_BYTE (1 << 5)
+#define STM32_CRC_CR_REV_IN_HWORD (2 << 5)
+#define STM32_CRC_CR_REV_IN_WORD (3 << 5)
+#define STM32_CRC_CR_REV_OUT BIT(7)
 
 /* --- PMSE --- */
-#define STM32_PMSE_ARCR             REG32(STM32_PMSE_BASE + 0x0)
-#define STM32_PMSE_ACCR             REG32(STM32_PMSE_BASE + 0x4)
-#define STM32_PMSE_CR               REG32(STM32_PMSE_BASE + 0x8)
-#define STM32_PMSE_CRTDR            REG32(STM32_PMSE_BASE + 0x14)
-#define STM32_PMSE_IER              REG32(STM32_PMSE_BASE + 0x18)
-#define STM32_PMSE_SR               REG32(STM32_PMSE_BASE + 0x1c)
-#define STM32_PMSE_IFCR             REG32(STM32_PMSE_BASE + 0x20)
-#define STM32_PMSE_PxPMR(x)         REG32(STM32_PMSE_BASE + 0x2c + (x) * 4)
-#define STM32_PMSE_PAPMR            REG32(STM32_PMSE_BASE + 0x2c)
-#define STM32_PMSE_PBPMR            REG32(STM32_PMSE_BASE + 0x30)
-#define STM32_PMSE_PCPMR            REG32(STM32_PMSE_BASE + 0x34)
-#define STM32_PMSE_PDPMR            REG32(STM32_PMSE_BASE + 0x38)
-#define STM32_PMSE_PEPMR            REG32(STM32_PMSE_BASE + 0x3c)
-#define STM32_PMSE_PFPMR            REG32(STM32_PMSE_BASE + 0x40)
-#define STM32_PMSE_PGPMR            REG32(STM32_PMSE_BASE + 0x44)
-#define STM32_PMSE_PHPMR            REG32(STM32_PMSE_BASE + 0x48)
-#define STM32_PMSE_PIPMR            REG32(STM32_PMSE_BASE + 0x4c)
-#define STM32_PMSE_MRCR             REG32(STM32_PMSE_BASE + 0x100)
-#define STM32_PMSE_MCCR             REG32(STM32_PMSE_BASE + 0x104)
+#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0)
+#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4)
+#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8)
+#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14)
+#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18)
+#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c)
+#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20)
+#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x)*4)
+#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c)
+#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30)
+#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34)
+#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38)
+#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c)
+#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40)
+#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44)
+#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48)
+#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c)
+#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100)
+#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104)
 
 /* --- USB --- */
-#define STM32_USB_EP(n)            REG16(STM32_USB_FS_BASE + (n) * 4)
-
-#define STM32_USB_CNTR             REG16(STM32_USB_FS_BASE + 0x40)
-
-#define STM32_USB_CNTR_FRES	    BIT(0)
-#define STM32_USB_CNTR_PDWN	    BIT(1)
-#define STM32_USB_CNTR_LP_MODE	    BIT(2)
-#define STM32_USB_CNTR_FSUSP	    BIT(3)
-#define STM32_USB_CNTR_RESUME	    BIT(4)
-#define STM32_USB_CNTR_L1RESUME	    BIT(5)
-#define STM32_USB_CNTR_L1REQM	    BIT(7)
-#define STM32_USB_CNTR_ESOFM	    BIT(8)
-#define STM32_USB_CNTR_SOFM	    BIT(9)
-#define STM32_USB_CNTR_RESETM	    BIT(10)
-#define STM32_USB_CNTR_SUSPM	    BIT(11)
-#define STM32_USB_CNTR_WKUPM	    BIT(12)
-#define STM32_USB_CNTR_ERRM	    BIT(13)
-#define STM32_USB_CNTR_PMAOVRM	    BIT(14)
-#define STM32_USB_CNTR_CTRM	    BIT(15)
-
-#define STM32_USB_ISTR             REG16(STM32_USB_FS_BASE + 0x44)
-
-#define STM32_USB_ISTR_EP_ID_MASK   (0x000f)
-#define STM32_USB_ISTR_DIR	    BIT(4)
-#define STM32_USB_ISTR_L1REQ	    BIT(7)
-#define STM32_USB_ISTR_ESOF	    BIT(8)
-#define STM32_USB_ISTR_SOF	    BIT(9)
-#define STM32_USB_ISTR_RESET	    BIT(10)
-#define STM32_USB_ISTR_SUSP	    BIT(11)
-#define STM32_USB_ISTR_WKUP	    BIT(12)
-#define STM32_USB_ISTR_ERR	    BIT(13)
-#define STM32_USB_ISTR_PMAOVR	    BIT(14)
-#define STM32_USB_ISTR_CTR	    BIT(15)
-
-#define STM32_USB_FNR              REG16(STM32_USB_FS_BASE + 0x48)
+#define STM32_USB_EP(n) REG16(STM32_USB_FS_BASE + (n)*4)
+
+#define STM32_USB_CNTR REG16(STM32_USB_FS_BASE + 0x40)
+
+#define STM32_USB_CNTR_FRES BIT(0)
+#define STM32_USB_CNTR_PDWN BIT(1)
+#define STM32_USB_CNTR_LP_MODE BIT(2)
+#define STM32_USB_CNTR_FSUSP BIT(3)
+#define STM32_USB_CNTR_RESUME BIT(4)
+#define STM32_USB_CNTR_L1RESUME BIT(5)
+#define STM32_USB_CNTR_L1REQM BIT(7)
+#define STM32_USB_CNTR_ESOFM BIT(8)
+#define STM32_USB_CNTR_SOFM BIT(9)
+#define STM32_USB_CNTR_RESETM BIT(10)
+#define STM32_USB_CNTR_SUSPM BIT(11)
+#define STM32_USB_CNTR_WKUPM BIT(12)
+#define STM32_USB_CNTR_ERRM BIT(13)
+#define STM32_USB_CNTR_PMAOVRM BIT(14)
+#define STM32_USB_CNTR_CTRM BIT(15)
+
+#define STM32_USB_ISTR REG16(STM32_USB_FS_BASE + 0x44)
+
+#define STM32_USB_ISTR_EP_ID_MASK (0x000f)
+#define STM32_USB_ISTR_DIR BIT(4)
+#define STM32_USB_ISTR_L1REQ BIT(7)
+#define STM32_USB_ISTR_ESOF BIT(8)
+#define STM32_USB_ISTR_SOF BIT(9)
+#define STM32_USB_ISTR_RESET BIT(10)
+#define STM32_USB_ISTR_SUSP BIT(11)
+#define STM32_USB_ISTR_WKUP BIT(12)
+#define STM32_USB_ISTR_ERR BIT(13)
+#define STM32_USB_ISTR_PMAOVR BIT(14)
+#define STM32_USB_ISTR_CTR BIT(15)
+
+#define STM32_USB_FNR REG16(STM32_USB_FS_BASE + 0x48)
 
 #define STM32_USB_FNR_RXDP_RXDM_SHIFT (14)
-#define STM32_USB_FNR_RXDP_RXDM_MASK  (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT)
-
-#define STM32_USB_DADDR            REG16(STM32_USB_FS_BASE + 0x4C)
-#define STM32_USB_BTABLE           REG16(STM32_USB_FS_BASE + 0x50)
-#define STM32_USB_LPMCSR           REG16(STM32_USB_FS_BASE + 0x54)
-#define STM32_USB_BCDR             REG16(STM32_USB_FS_BASE + 0x58)
-
-#define STM32_USB_BCDR_BCDEN	    BIT(0)
-#define STM32_USB_BCDR_DCDEN	    BIT(1)
-#define STM32_USB_BCDR_PDEN	    BIT(2)
-#define STM32_USB_BCDR_SDEN	    BIT(3)
-#define STM32_USB_BCDR_DCDET	    BIT(4)
-#define STM32_USB_BCDR_PDET	    BIT(5)
-#define STM32_USB_BCDR_SDET	    BIT(6)
-#define STM32_USB_BCDR_PS2DET	    BIT(7)
-
-#define EP_MASK     0x0F0F
-#define EP_TX_DTOG  0x0040
-#define EP_TX_MASK  0x0030
+#define STM32_USB_FNR_RXDP_RXDM_MASK (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT)
+
+#define STM32_USB_DADDR REG16(STM32_USB_FS_BASE + 0x4C)
+#define STM32_USB_BTABLE REG16(STM32_USB_FS_BASE + 0x50)
+#define STM32_USB_LPMCSR REG16(STM32_USB_FS_BASE + 0x54)
+#define STM32_USB_BCDR REG16(STM32_USB_FS_BASE + 0x58)
+
+#define STM32_USB_BCDR_BCDEN BIT(0)
+#define STM32_USB_BCDR_DCDEN BIT(1)
+#define STM32_USB_BCDR_PDEN BIT(2)
+#define STM32_USB_BCDR_SDEN BIT(3)
+#define STM32_USB_BCDR_DCDET BIT(4)
+#define STM32_USB_BCDR_PDET BIT(5)
+#define STM32_USB_BCDR_SDET BIT(6)
+#define STM32_USB_BCDR_PS2DET BIT(7)
+
+#define EP_MASK 0x0F0F
+#define EP_TX_DTOG 0x0040
+#define EP_TX_MASK 0x0030
 #define EP_TX_VALID 0x0030
-#define EP_TX_NAK   0x0020
+#define EP_TX_NAK 0x0020
 #define EP_TX_STALL 0x0010
 #define EP_TX_DISAB 0x0000
-#define EP_RX_DTOG  0x4000
-#define EP_RX_MASK  0x3000
+#define EP_RX_DTOG 0x4000
+#define EP_RX_MASK 0x3000
 #define EP_RX_VALID 0x3000
-#define EP_RX_NAK   0x2000
+#define EP_RX_NAK 0x2000
 #define EP_RX_STALL 0x1000
 #define EP_RX_DISAB 0x0000
 
 #define EP_STATUS_OUT 0x0100
 
-#define EP_TX_RX_MASK  (EP_TX_MASK | EP_RX_MASK)
+#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK)
 #define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID)
-#define EP_TX_RX_NAK   (EP_TX_NAK | EP_RX_NAK)
+#define EP_TX_RX_NAK (EP_TX_NAK | EP_RX_NAK)
 
 #define STM32_TOGGLE_EP(n, mask, val, flags) \
-	STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \
-			^ (val)) | (flags))
+	STM32_USB_EP(n) =                    \
+		(((STM32_USB_EP(n) & (EP_MASK | (mask))) ^ (val)) | (flags))
 
 /* --- TRNG --- */
-#define STM32_RNG_CR                REG32(STM32_RNG_BASE + 0x0)
-#define STM32_RNG_CR_RNGEN		BIT(2)
-#define STM32_RNG_CR_IE			BIT(3)
-#define STM32_RNG_CR_CED		BIT(5)
-#define STM32_RNG_SR                REG32(STM32_RNG_BASE + 0x4)
-#define STM32_RNG_SR_DRDY		BIT(0)
-#define STM32_RNG_DR                REG32(STM32_RNG_BASE + 0x8)
+#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0)
+#define STM32_RNG_CR_RNGEN BIT(2)
+#define STM32_RNG_CR_IE BIT(3)
+#define STM32_RNG_CR_CED BIT(5)
+#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4)
+#define STM32_RNG_SR_DRDY BIT(0)
+#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8)
 
 /* --- AXI interconnect --- */
 
 /* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */
-#define STM32_AXI_TARG_FN_MOD(x)    REG32(STM32_GPV_BASE + 0x1108 + \
-					  0x1000 * (x))
-#define  WRITE_ISS_OVERRIDE         BIT(1)
-#define  READ_ISS_OVERRIDE          BIT(0)
+#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + 0x1000 * (x))
+#define WRITE_ISS_OVERRIDE BIT(1)
+#define READ_ISS_OVERRIDE BIT(0)
 
 /* --- MISC --- */
-#define STM32_UNIQUE_ID_ADDRESS     REG32_ADDR(STM32_UNIQUE_ID_BASE)
-#define STM32_UNIQUE_ID_LENGTH      (3 * 4)
+#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE)
+#define STM32_UNIQUE_ID_LENGTH (3 * 4)
 
 #endif /* !__ASSEMBLER__ */
 
@@ -483,6 +488,8 @@ typedef volatile struct timer_ctlr timer_ctlr_t;
 #include "registers-stm32l.h"
 #elif defined(CHIP_FAMILY_STM32L4)
 #include "registers-stm32l4.h"
+#elif defined(CHIP_FAMILY_STM32L5)
+#include "registers-stm32l5.h"
 #else
 #error "Unsupported chip family"
 #endif
diff --git a/chip/stm32/spi.c b/chip/stm32/spi.c
index 3dbbbc4fa9..e6be946113 100644
--- a/chip/stm32/spi.c
+++ b/chip/stm32/spi.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2013 The Chromium OS Authors. All rights reserved.
+ * Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,6 +8,7 @@
  * This uses DMA to handle transmission and reception.
  */
 
+#include "builtin/assert.h"
 #include "chipset.h"
 #include "clock.h"
 #include "console.h"
@@ -24,8 +25,8 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_SPI, outstr)
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SPI, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SPI, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SPI, format, ##args)
 
 /* SPI FIFO registers */
 #ifdef CHIP_FAMILY_STM32H7
@@ -41,7 +42,7 @@ static const struct dma_option dma_tx_option = {
 	STM32_DMAC_SPI1_TX, (void *)&SPI_TXDR,
 	STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
 #ifdef CHIP_FAMILY_STM32F4
-	| STM32_DMA_CCR_CHANNEL(STM32_SPI1_TX_REQ_CH)
+		| STM32_DMA_CCR_CHANNEL(STM32_SPI1_TX_REQ_CH)
 #endif
 };
 
@@ -49,7 +50,7 @@ static const struct dma_option dma_rx_option = {
 	STM32_DMAC_SPI1_RX, (void *)&SPI_RXDR,
 	STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
 #ifdef CHIP_FAMILY_STM32F4
-	| STM32_DMA_CCR_CHANNEL(STM32_SPI1_RX_REQ_CH)
+		| STM32_DMA_CCR_CHANNEL(STM32_SPI1_RX_REQ_CH)
 #endif
 };
 
@@ -71,8 +72,8 @@ static const struct dma_option dma_rx_option = {
  * the AP will have a known and identifiable value.
  */
 #define SPI_PROTO2_OFFSET (EC_PROTO2_RESPONSE_HEADER_BYTES + 2)
-#define SPI_PROTO2_OVERHEAD (SPI_PROTO2_OFFSET +		\
-			     EC_PROTO2_RESPONSE_TRAILER_BYTES + 1)
+#define SPI_PROTO2_OVERHEAD \
+	(SPI_PROTO2_OFFSET + EC_PROTO2_RESPONSE_TRAILER_BYTES + 1)
 #endif /* defined(CONFIG_SPI_PROTOCOL_V2) */
 /*
  * Max data size for a version 3 request/response packet.  This is big enough
@@ -92,10 +93,8 @@ static const struct dma_option dma_rx_option = {
  * 32-bit aligned.
  */
 static const uint8_t out_preamble[4] = {
-	EC_SPI_PROCESSING,
-	EC_SPI_PROCESSING,
-	EC_SPI_PROCESSING,
-	EC_SPI_FRAME_START,  /* This is the byte which matters */
+	EC_SPI_PROCESSING, EC_SPI_PROCESSING, EC_SPI_PROCESSING,
+	EC_SPI_FRAME_START, /* This is the byte which matters */
 };
 
 /*
@@ -117,7 +116,7 @@ static const uint8_t out_preamble[4] = {
  * message, including protocol overhead, and must be 32-bit aligned.
  */
 static uint8_t out_msg[SPI_MAX_RESPONSE_SIZE + sizeof(out_preamble) +
-	EC_SPI_PAST_END_LENGTH] __aligned(4) __uncached;
+		       EC_SPI_PAST_END_LENGTH] __aligned(4) __uncached;
 static uint8_t in_msg[SPI_MAX_REQUEST_SIZE] __aligned(4) __uncached;
 static uint8_t enabled;
 #ifdef CONFIG_SPI_PROTOCOL_V2
@@ -172,8 +171,7 @@ enum spi_state {
  * @param nss		GPIO signal for NSS control line
  * @return 0 if bytes received, -1 if we hit a timeout or NSS went high
  */
-static int wait_for_bytes(dma_chan_t *rxdma, int needed,
-			  enum gpio_signal nss)
+static int wait_for_bytes(dma_chan_t *rxdma, int needed, enum gpio_signal nss)
 {
 	timestamp_t deadline;
 
@@ -230,8 +228,8 @@ static int wait_for_bytes(dma_chan_t *rxdma, int needed,
  *			SPI_PROTO2_OFFSET bytes into out_msg
  * @param msg_len	Number of message bytes to send
  */
-static void reply(dma_chan_t *txdma,
-		  enum ec_status status, char *msg_ptr, int msg_len)
+static void reply(dma_chan_t *txdma, enum ec_status status, char *msg_ptr,
+		  int msg_len)
 {
 	char *msg = out_msg;
 	int need_copy = msg_ptr != msg + SPI_PROTO2_OFFSET;
@@ -341,7 +339,7 @@ static void setup_for_transaction(void)
 
 	/* Ready to receive */
 	state = SPI_STATE_READY_TO_RX;
-	tx_status(EC_SPI_OLD_READY);
+	tx_status(EC_SPI_RX_READY);
 
 #ifdef CHIP_FAMILY_STM32H7
 	spi->cr1 |= STM32_SPI_CR1_SPE;
@@ -438,8 +436,10 @@ static void spi_send_response_packet(struct host_packet *pkt)
 
 	/* Transmit the reply */
 	txdma = dma_get_channel(STM32_DMAC_SPI1_TX);
-	dma_prepare_tx(&dma_tx_option, sizeof(out_preamble) + pkt->response_size
-		+ EC_SPI_PAST_END_LENGTH, out_msg);
+	dma_prepare_tx(&dma_tx_option,
+		       sizeof(out_preamble) + pkt->response_size +
+			       EC_SPI_PAST_END_LENGTH,
+		       out_msg);
 	dma_go(txdma);
 #ifdef CHIP_FAMILY_STM32H7
 	/* clear any previous underrun */
@@ -544,8 +544,9 @@ void spi_event(enum gpio_signal signal)
 		memcpy(out_msg, out_preamble, sizeof(out_preamble));
 		spi_packet.response = out_msg + sizeof(out_preamble);
 		/* Reserve space for the preamble and trailing past-end byte */
-		spi_packet.response_max = sizeof(out_msg)
-			- sizeof(out_preamble) - EC_SPI_PAST_END_LENGTH;
+		spi_packet.response_max = sizeof(out_msg) -
+					  sizeof(out_preamble) -
+					  EC_SPI_PAST_END_LENGTH;
 		spi_packet.response_size = 0;
 
 		spi_packet.driver_result = EC_RES_SUCCESS;
@@ -608,7 +609,7 @@ void spi_event(enum gpio_signal signal)
 #endif /* defined(CONFIG_SPI_PROTOCOL_V2) */
 	}
 
- spi_event_error:
+spi_event_error:
 	/* Error, timeout, or protocol we can't handle.  Ignore data. */
 	tx_status(EC_SPI_RX_BAD_DATA);
 	state = SPI_STATE_RX_BAD;
@@ -701,14 +702,13 @@ static void spi_init(void)
 #ifdef CHIP_FAMILY_STM32H7
 	spi->cfg2 = 0;
 	spi->cfg1 = STM32_SPI_CFG1_DATASIZE(8) | STM32_SPI_CFG1_FTHLV(4) |
-			STM32_SPI_CFG1_CRCSIZE(8) |
-			STM32_SPI_CFG1_TXDMAEN | STM32_SPI_CFG1_RXDMAEN |
-			STM32_SPI_CFG1_UDRCFG_CONST |
-			STM32_SPI_CFG1_UDRDET_BEGIN_FRM;
+		    STM32_SPI_CFG1_CRCSIZE(8) | STM32_SPI_CFG1_TXDMAEN |
+		    STM32_SPI_CFG1_RXDMAEN | STM32_SPI_CFG1_UDRCFG_CONST |
+		    STM32_SPI_CFG1_UDRDET_BEGIN_FRM;
 	spi->cr1 = 0;
 #else /* !CHIP_FAMILY_STM32H7 */
 	spi->cr2 = STM32_SPI_CR2_RXDMAEN | STM32_SPI_CR2_TXDMAEN |
-		STM32_SPI_CR2_FRXTH | STM32_SPI_CR2_DATASIZE(8);
+		   STM32_SPI_CR2_FRXTH | STM32_SPI_CR2_DATASIZE(8);
 
 	/* Enable the SPI peripheral */
 	spi->cr1 |= STM32_SPI_CR1_SPE;
diff --git a/chip/stm32/spi_controller-stm32h7.c b/chip/stm32/spi_controller-stm32h7.c
new file mode 100644
index 0000000000..705bf4e607
--- /dev/null
+++ b/chip/stm32/spi_controller-stm32h7.c
@@ -0,0 +1,313 @@
+/*
+ * Copyright 2017 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * SPI controller driver.
+ */
+
+#include "common.h"
+#include "dma.h"
+#include "gpio.h"
+#include "shared_mem.h"
+#include "spi.h"
+#include "stm32-dma.h"
+#include "task.h"
+#include "timer.h"
+#include "util.h"
+
+/* SPI ports are used as controller */
+static stm32_spi_regs_t *SPI_REGS[] = {
+#ifdef CONFIG_STM32_SPI1_CONTROLLER
+	STM32_SPI1_REGS,
+#endif
+	STM32_SPI2_REGS,
+	STM32_SPI3_REGS,
+	STM32_SPI4_REGS,
+};
+
+/* DMA request mapping on channels */
+static uint8_t dma_req_tx[ARRAY_SIZE(SPI_REGS)] = {
+#ifdef CONFIG_STM32_SPI1_CONTROLLER
+	DMAMUX1_REQ_SPI1_TX,
+#endif
+	DMAMUX1_REQ_SPI2_TX,
+	DMAMUX1_REQ_SPI3_TX,
+	DMAMUX1_REQ_SPI4_TX,
+};
+static uint8_t dma_req_rx[ARRAY_SIZE(SPI_REGS)] = {
+#ifdef CONFIG_STM32_SPI1_CONTROLLER
+	DMAMUX1_REQ_SPI1_RX,
+#endif
+	DMAMUX1_REQ_SPI2_RX,
+	DMAMUX1_REQ_SPI3_RX,
+	DMAMUX1_REQ_SPI4_RX,
+};
+
+static struct mutex spi_mutex[ARRAY_SIZE(SPI_REGS)];
+
+#define SPI_TRANSACTION_TIMEOUT_USEC (800 * MSEC)
+
+static const struct dma_option dma_tx_option[] = {
+#ifdef CONFIG_STM32_SPI1_CONTROLLER
+	{ STM32_DMAC_SPI1_TX, (void *)&STM32_SPI1_REGS->txdr,
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT },
+#endif
+	{ STM32_DMAC_SPI2_TX, (void *)&STM32_SPI2_REGS->txdr,
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT },
+	{ STM32_DMAC_SPI3_TX, (void *)&STM32_SPI3_REGS->txdr,
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT },
+	{ STM32_DMAC_SPI4_TX, (void *)&STM32_SPI4_REGS->txdr,
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT },
+};
+
+static const struct dma_option dma_rx_option[] = {
+#ifdef CONFIG_STM32_SPI1_CONTROLLER
+	{ STM32_DMAC_SPI1_RX, (void *)&STM32_SPI1_REGS->rxdr,
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT },
+#endif
+	{ STM32_DMAC_SPI2_RX, (void *)&STM32_SPI2_REGS->rxdr,
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT },
+	{ STM32_DMAC_SPI3_RX, (void *)&STM32_SPI3_REGS->rxdr,
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT },
+	{ STM32_DMAC_SPI4_RX, (void *)&STM32_SPI4_REGS->rxdr,
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT },
+};
+
+static uint8_t spi_enabled[ARRAY_SIZE(SPI_REGS)];
+
+/**
+ * Initialize SPI module, registers, and clocks
+ * @param spi_device  device to initialize.
+ */
+static void spi_controller_config(const struct spi_device_t *spi_device)
+{
+	int port = spi_device->port;
+
+	stm32_spi_regs_t *spi = SPI_REGS[port];
+
+	/*
+	 * Set SPI controller, baud rate, and software peripheral control.
+	 */
+	spi->cr1 = STM32_SPI_CR1_SSI;
+	spi->cfg2 = STM32_SPI_CFG2_MSTR | STM32_SPI_CFG2_SSM |
+		    STM32_SPI_CFG2_AFCNTR;
+	spi->cfg1 = STM32_SPI_CFG1_DATASIZE(8) | STM32_SPI_CFG1_FTHLV(4) |
+		    STM32_SPI_CFG1_CRCSIZE(8) |
+		    STM32_SPI_CR1_DIV(spi_device->div);
+
+	dma_select_channel(dma_tx_option[port].channel, dma_req_tx[port]);
+	dma_select_channel(dma_rx_option[port].channel, dma_req_rx[port]);
+}
+
+static int spi_controller_initialize(const struct spi_device_t *spi_device)
+{
+	spi_controller_config(spi_device);
+
+	gpio_set_level(spi_device->gpio_cs, 1);
+
+	/* Set flag */
+	spi_enabled[spi_device->port] = 1;
+
+	return EC_SUCCESS;
+}
+
+/**
+ * Shutdown SPI module
+ */
+static int spi_controller_shutdown(const struct spi_device_t *spi_device)
+{
+	int rv = EC_SUCCESS;
+	int port = spi_device->port;
+	stm32_spi_regs_t *spi = SPI_REGS[port];
+
+	/* Set flag */
+	spi_enabled[port] = 0;
+
+	/* Disable DMA streams */
+	dma_disable(dma_tx_option[port].channel);
+	dma_disable(dma_rx_option[port].channel);
+
+	/* Disable SPI */
+	spi->cr1 &= ~STM32_SPI_CR1_SPE;
+
+	/* Disable DMA buffers */
+	spi->cfg1 &= ~(STM32_SPI_CFG1_TXDMAEN | STM32_SPI_CFG1_RXDMAEN);
+
+	return rv;
+}
+
+int spi_enable(const struct spi_device_t *spi_device, int enable)
+{
+	int port = spi_device->port;
+	if (enable == spi_enabled[port])
+		return EC_SUCCESS;
+	if (enable)
+		return spi_controller_initialize(spi_device);
+	else
+		return spi_controller_shutdown(spi_device);
+}
+
+static int spi_dma_start(const struct spi_device_t *spi_device,
+			 const uint8_t *txdata, uint8_t *rxdata, int len)
+{
+	dma_chan_t *txdma;
+	int port = spi_device->port;
+	stm32_spi_regs_t *spi = SPI_REGS[port];
+
+	/*
+	 * Workaround for STM32H7 errata: without resetting the SPI controller,
+	 * the RX DMA requests will happen too early on the 2nd transfer.
+	 */
+	STM32_RCC_APB2RSTR = STM32_RCC_PB2_SPI4;
+	STM32_RCC_APB2RSTR = 0;
+	dma_clear_isr(dma_tx_option[port].channel);
+	dma_clear_isr(dma_rx_option[port].channel);
+	/* restore proper SPI configuration registers. */
+	spi_controller_config(spi_device);
+
+	spi->cr2 = len;
+	spi->cfg1 |= STM32_SPI_CFG1_RXDMAEN;
+	/* Set up RX DMA */
+	if (rxdata)
+		dma_start_rx(&dma_rx_option[port], len, rxdata);
+
+	/* Set up TX DMA */
+	if (txdata) {
+		txdma = dma_get_channel(dma_tx_option[port].channel);
+		dma_prepare_tx(&dma_tx_option[port], len, txdata);
+		dma_go(txdma);
+	}
+
+	spi->cfg1 |= STM32_SPI_CFG1_TXDMAEN;
+	spi->cr1 |= STM32_SPI_CR1_SPE;
+	spi->cr1 |= STM32_SPI_CR1_CSTART;
+
+	return EC_SUCCESS;
+}
+
+static inline bool dma_is_enabled_(const struct dma_option *option)
+{
+	return dma_is_enabled(dma_get_channel(option->channel));
+}
+
+static int spi_dma_wait(int port)
+{
+	timestamp_t timeout;
+	stm32_spi_regs_t *spi = SPI_REGS[port];
+	int rv = EC_SUCCESS;
+
+	/* Wait for DMA transmission to complete */
+	if (dma_is_enabled_(&dma_tx_option[port])) {
+		rv = dma_wait(dma_tx_option[port].channel);
+		if (rv)
+			return rv;
+
+		timeout.val = get_time().val + SPI_TRANSACTION_TIMEOUT_USEC;
+		/* Wait for FIFO empty and BSY bit clear */
+		while (!(spi->sr & (STM32_SPI_SR_TXC)))
+			if (get_time().val > timeout.val)
+				return EC_ERROR_TIMEOUT;
+
+		/* Disable TX DMA */
+		dma_disable(dma_tx_option[port].channel);
+	}
+
+	/* Wait for DMA reception to complete */
+	if (dma_is_enabled_(&dma_rx_option[port])) {
+		rv = dma_wait(dma_rx_option[port].channel);
+		if (rv)
+			return rv;
+
+		timeout.val = get_time().val + SPI_TRANSACTION_TIMEOUT_USEC;
+		/* Wait for FRLVL[1:0] to indicate FIFO empty */
+		while (spi->sr & (STM32_SPI_SR_FRLVL | STM32_SPI_SR_RXNE))
+			if (get_time().val > timeout.val)
+				return EC_ERROR_TIMEOUT;
+
+		/* Disable RX DMA */
+		dma_disable(dma_rx_option[port].channel);
+	}
+
+	spi->cr1 &= ~STM32_SPI_CR1_SPE;
+	spi->cfg1 &= ~(STM32_SPI_CFG1_TXDMAEN | STM32_SPI_CFG1_RXDMAEN);
+
+	return rv;
+}
+
+int spi_transaction_async(const struct spi_device_t *spi_device,
+			  const uint8_t *txdata, int txlen, uint8_t *rxdata,
+			  int rxlen)
+{
+	int rv = EC_SUCCESS;
+	int port = spi_device->port;
+	int full_readback = 0;
+
+	char *buf = NULL;
+
+#ifndef CONFIG_SPI_HALFDUPLEX
+	if (rxlen == SPI_READBACK_ALL) {
+		buf = rxdata;
+		full_readback = 1;
+	} else {
+		rv = shared_mem_acquire(MAX(txlen, rxlen), &buf);
+		if (rv != EC_SUCCESS)
+			return rv;
+	}
+#endif
+
+	/* Drive SS low */
+	gpio_set_level(spi_device->gpio_cs, 0);
+
+	rv = spi_dma_start(spi_device, txdata, buf, txlen);
+	if (rv != EC_SUCCESS)
+		goto err_free;
+
+	if (full_readback)
+		return EC_SUCCESS;
+
+	if (rxlen) {
+		rv = spi_dma_wait(port);
+		if (rv != EC_SUCCESS)
+			goto err_free;
+
+		rv = spi_dma_start(spi_device, buf, rxdata, rxlen);
+		if (rv != EC_SUCCESS)
+			goto err_free;
+	}
+
+err_free:
+	if (!full_readback)
+		shared_mem_release(buf);
+	return rv;
+}
+
+int spi_transaction_flush(const struct spi_device_t *spi_device)
+{
+	int rv = spi_dma_wait(spi_device->port);
+
+	/* Drive SS high */
+	gpio_set_level(spi_device->gpio_cs, 1);
+
+	return rv;
+}
+
+int spi_transaction_wait(const struct spi_device_t *spi_device)
+{
+	return spi_dma_wait(spi_device->port);
+}
+
+int spi_transaction(const struct spi_device_t *spi_device,
+		    const uint8_t *txdata, int txlen, uint8_t *rxdata,
+		    int rxlen)
+{
+	int rv;
+	int port = spi_device->port;
+
+	mutex_lock(spi_mutex + port);
+	rv = spi_transaction_async(spi_device, txdata, txlen, rxdata, rxlen);
+	rv |= spi_transaction_flush(spi_device);
+	mutex_unlock(spi_mutex + port);
+
+	return rv;
+}
diff --git a/chip/stm32/spi_controller.c b/chip/stm32/spi_controller.c
new file mode 100644
index 0000000000..2802c35e90
--- /dev/null
+++ b/chip/stm32/spi_controller.c
@@ -0,0 +1,464 @@
+/*
+ * Copyright 2014 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * SPI controller driver.
+ */
+
+#include "common.h"
+#include "dma.h"
+#include "gpio.h"
+#include "hwtimer.h"
+#include "shared_mem.h"
+#include "spi.h"
+#include "stm32-dma.h"
+#include "task.h"
+#include "timer.h"
+#include "util.h"
+
+#if defined(CHIP_VARIANT_STM32F373) || defined(CHIP_FAMILY_STM32L4) || \
+	defined(CHIP_FAMILY_STM32L5) || defined(CHIP_VARIANT_STM32F76X)
+#define HAS_SPI3
+#else
+#undef HAS_SPI3
+#endif
+
+/* The second (and third if available) SPI port are used as controller */
+static stm32_spi_regs_t *SPI_REGS[] = {
+#ifdef CONFIG_STM32_SPI1_CONTROLLER
+	STM32_SPI1_REGS,
+#endif
+	STM32_SPI2_REGS,
+#ifdef HAS_SPI3
+	STM32_SPI3_REGS,
+#endif
+};
+
+/* DMA request mapping on channels */
+struct dma_req_t {
+	uint8_t tx_req;
+	uint8_t rx_req;
+};
+#ifdef CHIP_FAMILY_STM32L4
+static struct dma_req_t dma_req[ARRAY_SIZE(SPI_REGS)] = {
+#ifdef CONFIG_STM32_SPI1_CONTROLLER
+	/* SPI1 */ { 1, 1 },
+#endif
+	/* SPI2 */ { 1, 1 },
+	/* SPI3 */ { 3, 3 },
+};
+#elif defined(CHIP_FAMILY_STM32L5)
+static struct dma_req_t dma_req[ARRAY_SIZE(SPI_REGS)] = {
+#ifdef CONFIG_STM32_SPI1_CONTROLLER
+	/* SPI1 */ { DMAMUX_REQ_SPI1_TX, DMAMUX_REQ_SPI1_RX },
+#endif
+	/* SPI2 */ { DMAMUX_REQ_SPI2_TX, DMAMUX_REQ_SPI2_RX },
+	/* SPI3 */ { DMAMUX_REQ_SPI3_TX, DMAMUX_REQ_SPI3_RX },
+};
+#endif
+
+static struct mutex spi_mutex[ARRAY_SIZE(SPI_REGS)];
+
+#define SPI_TRANSACTION_TIMEOUT_USEC (800 * MSEC)
+
+/* Default DMA channel options */
+#ifdef CHIP_FAMILY_STM32F4
+#define F4_CHANNEL(ch) STM32_DMA_CCR_CHANNEL(ch)
+#else
+#define F4_CHANNEL(ch) 0
+#endif
+
+static const struct dma_option dma_tx_option[] = {
+#ifdef CONFIG_STM32_SPI1_CONTROLLER
+	{ STM32_DMAC_SPI1_TX, (void *)&STM32_SPI1_REGS->dr,
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
+		  F4_CHANNEL(STM32_SPI1_TX_REQ_CH) },
+#endif
+	{ STM32_DMAC_SPI2_TX, (void *)&STM32_SPI2_REGS->dr,
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
+		  F4_CHANNEL(STM32_SPI2_TX_REQ_CH) },
+#ifdef HAS_SPI3
+	{ STM32_DMAC_SPI3_TX, (void *)&STM32_SPI3_REGS->dr,
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
+		  F4_CHANNEL(STM32_SPI3_TX_REQ_CH) },
+#endif
+};
+
+static const struct dma_option dma_rx_option[] = {
+#ifdef CONFIG_STM32_SPI1_CONTROLLER
+	{ STM32_DMAC_SPI1_RX, (void *)&STM32_SPI1_REGS->dr,
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
+		  F4_CHANNEL(STM32_SPI1_RX_REQ_CH) },
+#endif
+	{ STM32_DMAC_SPI2_RX, (void *)&STM32_SPI2_REGS->dr,
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
+		  F4_CHANNEL(STM32_SPI2_RX_REQ_CH) },
+#ifdef HAS_SPI3
+	{ STM32_DMAC_SPI3_RX, (void *)&STM32_SPI3_REGS->dr,
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
+		  F4_CHANNEL(STM32_SPI3_RX_REQ_CH) },
+#endif
+};
+
+static uint8_t spi_enabled[ARRAY_SIZE(SPI_REGS)];
+
+static int spi_tx_done(stm32_spi_regs_t *spi)
+{
+	return !(spi->sr & (STM32_SPI_SR_FTLVL | STM32_SPI_SR_BSY));
+}
+
+static int spi_rx_done(stm32_spi_regs_t *spi)
+{
+	return !(spi->sr & (STM32_SPI_SR_FRLVL | STM32_SPI_SR_RXNE));
+}
+
+/* Read until RX FIFO is empty (i.e. RX done) */
+static int spi_clear_rx_fifo(stm32_spi_regs_t *spi)
+{
+	uint8_t unused __attribute__((unused));
+	uint32_t start = __hw_clock_source_read(), delta;
+
+	while (!spi_rx_done(spi)) {
+		unused = spi->dr; /* Read one byte from FIFO */
+		delta = __hw_clock_source_read() - start;
+		if (delta >= SPI_TRANSACTION_TIMEOUT_USEC)
+			return EC_ERROR_TIMEOUT;
+	}
+	return EC_SUCCESS;
+}
+
+/* Wait until TX FIFO is empty (i.e. TX done) */
+static int spi_clear_tx_fifo(stm32_spi_regs_t *spi)
+{
+	uint32_t start = __hw_clock_source_read(), delta;
+
+	while (!spi_tx_done(spi)) {
+		/* wait for TX complete */
+		delta = __hw_clock_source_read() - start;
+		if (delta >= SPI_TRANSACTION_TIMEOUT_USEC)
+			return EC_ERROR_TIMEOUT;
+	}
+	return EC_SUCCESS;
+}
+
+/**
+ * Initialize SPI module, registers, and clocks
+ *
+ * - port: which port to initialize.
+ */
+static int spi_controller_initialize(const struct spi_device_t *spi_device)
+{
+	int port = spi_device->port;
+
+	stm32_spi_regs_t *spi = SPI_REGS[port];
+
+	/*
+	 * Set SPI controller, baud rate, and software peripheral control.
+	 * */
+
+	/*
+	 * STM32F412
+	 * Section 26.3.5 Chip select (NSS) pin management and Figure 276
+	 * https://www.st.com/resource/en/reference_manual/dm00180369.pdf#page=817
+	 *
+	 * The documentation in this section is a bit confusing, so here's a
+	 * summary based on discussion with ST:
+	 *
+	 * Software NSS management (SSM = 1):
+	 *   - In controller mode, the NSS output is deactivated. You need to
+	 *     use a GPIO in output mode for chip select. This is generally used
+	 *     for multi-peripheral operation, but you can also use it for
+	 *     single peripheral operation. In this case, you should make sure
+	 *     to configure a GPIO for NSS, but *not* activate the SPI alternate
+	 *     function on that same pin since that will enable hardware NSS
+	 *     management (see below).
+	 *   - In peripheral mode, the NSS input level is equal to the SSI bit
+	 *     value.
+	 *
+	 * Hardware NSS management (SSM = 0):
+	 *   - In peripheral mode, when NSS pin is detected low the peripheral
+	 *     (MCU) is selected.
+	 *   - In controller mode, there are two configurations, depending on
+	 *     the SSOE bit in register SPIx_CR1.
+	 *       - NSS output enable (SSM=0, SSOE=1):
+	 *         The MCU (controller) drives NSS low as soon as SPI is enabled
+	 *         (SPE=1) and releases it when SPI is disabled (SPE=0).
+	 *
+	 *       - NSS output disable (SSM=0, SSOE=0):
+	 *         Allows multi-controller capability. The MCU (controller)
+	 *         drives NSS low. If another controller tries to takes control
+	 *         of the bus and NSS is pulled low, a mode fault is generated
+	 *         and the MCU changes to peripheral mode.
+	 *
+	 *   - NSS output disable (SSM=0, SSOE=0): if the MCU is acting as
+	 *     controller on the bus, this config allows multi-controller
+	 *     capability. If the NSS pin is pulled low in this mode, the SPI
+	 *     enters controller mode fault state and the device is
+	 *     automatically reconfigured in peripheral mode. In peripheral
+	 *     mode, the NSS pin works as a standard "chip select" input and the
+	 *     peripheral is selected while NSS lin is at low level.
+	 */
+	spi->cr1 = STM32_SPI_CR1_MSTR | STM32_SPI_CR1_SSM | STM32_SPI_CR1_SSI |
+		   (spi_device->div << 3);
+
+#if defined(CHIP_FAMILY_STM32L4) || defined(CHIP_FAMILY_STM32L5)
+	dma_select_channel(dma_tx_option[port].channel, dma_req[port].tx_req);
+	dma_select_channel(dma_rx_option[port].channel, dma_req[port].rx_req);
+#endif
+	/*
+	 * Configure 8-bit datasize, set FRXTH, enable DMA,
+	 * and set data size (applies to STM32F0 only).
+	 *
+	 * STM32F412:
+	 * https://www.st.com/resource/en/reference_manual/dm00180369.pdf#page=852
+	 *
+	 *
+	 * STM32F0:
+	 * https://www.st.com/resource/en/reference_manual/dm00031936.pdf#page=803
+	 */
+	spi->cr2 = STM32_SPI_CR2_TXDMAEN | STM32_SPI_CR2_RXDMAEN |
+		   STM32_SPI_CR2_FRXTH | STM32_SPI_CR2_DATASIZE(8);
+
+#ifdef CONFIG_SPI_HALFDUPLEX
+	spi->cr1 |= STM32_SPI_CR1_BIDIMODE | STM32_SPI_CR1_BIDIOE;
+#endif
+
+	/* Drive Chip Select high before turning on SPI module */
+	gpio_set_level(spi_device->gpio_cs, 1);
+
+	/* Enable SPI hardware module. This will actively drive the CLK pin */
+	spi->cr1 |= STM32_SPI_CR1_SPE;
+
+	/* Set flag */
+	spi_enabled[port] = 1;
+
+	return EC_SUCCESS;
+}
+
+/**
+ * Shutdown SPI module
+ */
+static int spi_controller_shutdown(const struct spi_device_t *spi_device)
+{
+	int rv = EC_SUCCESS;
+	int port = spi_device->port;
+	stm32_spi_regs_t *spi = SPI_REGS[port];
+
+	/* Set flag */
+	spi_enabled[port] = 0;
+
+	/* Disable DMA streams */
+	dma_disable(dma_tx_option[port].channel);
+	dma_disable(dma_rx_option[port].channel);
+
+	/* Disable SPI. Let the CLK pin float. */
+	spi->cr1 &= ~STM32_SPI_CR1_SPE;
+
+	spi_clear_rx_fifo(spi);
+
+	/* Disable DMA buffers */
+	spi->cr2 &= ~(STM32_SPI_CR2_TXDMAEN | STM32_SPI_CR2_RXDMAEN);
+
+	return rv;
+}
+
+int spi_enable(const struct spi_device_t *spi_device, int enable)
+{
+	if (enable == spi_enabled[spi_device->port])
+		return EC_SUCCESS;
+	if (enable)
+		return spi_controller_initialize(spi_device);
+	else
+		return spi_controller_shutdown(spi_device);
+}
+
+static int spi_dma_start(int port, const uint8_t *txdata, uint8_t *rxdata,
+			 int len)
+{
+	dma_chan_t *txdma;
+
+	/* Set up RX DMA */
+	if (rxdata)
+		dma_start_rx(&dma_rx_option[port], len, rxdata);
+
+	/* Set up TX DMA */
+	if (txdata) {
+		txdma = dma_get_channel(dma_tx_option[port].channel);
+		dma_prepare_tx(&dma_tx_option[port], len, txdata);
+		dma_go(txdma);
+	}
+
+	return EC_SUCCESS;
+}
+
+static bool dma_is_enabled_(const struct dma_option *option)
+{
+	return dma_is_enabled(dma_get_channel(option->channel));
+}
+
+static int spi_dma_wait(int port)
+{
+	int rv = EC_SUCCESS;
+
+	/* Wait for DMA transmission to complete */
+	if (dma_is_enabled_(&dma_tx_option[port])) {
+		/*
+		 * In TX mode, SPI only generates clock when we write to FIFO.
+		 * Therefore, even though `dma_wait` polls with interval 0.1ms,
+		 * we won't send extra bytes.
+		 */
+		rv = dma_wait(dma_tx_option[port].channel);
+		if (rv)
+			return rv;
+		/* Disable TX DMA */
+		dma_disable(dma_tx_option[port].channel);
+	}
+
+	/* Wait for DMA reception to complete */
+	if (dma_is_enabled_(&dma_rx_option[port])) {
+		/*
+		 * Because `dma_wait` polls with interval 0.1ms, we will read at
+		 * least ~100 bytes (with 8MHz clock).  If you don't want this
+		 * overhead, you can use interrupt handler
+		 * (`dma_enable_tc_interrupt_callback`) and disable SPI
+		 * interface in callback function.
+		 */
+		rv = dma_wait(dma_rx_option[port].channel);
+		if (rv)
+			return rv;
+		/* Disable RX DMA */
+		dma_disable(dma_rx_option[port].channel);
+	}
+	return rv;
+}
+
+static uint8_t spi_chip_select_already_asserted[ARRAY_SIZE(SPI_REGS)];
+
+int spi_transaction_async(const struct spi_device_t *spi_device,
+			  const uint8_t *txdata, int txlen, uint8_t *rxdata,
+			  int rxlen)
+{
+	int rv = EC_SUCCESS;
+	int port = spi_device->port;
+	int full_readback = 0;
+
+	stm32_spi_regs_t *spi = SPI_REGS[port];
+	char *buf = NULL;
+
+	/* We should not ever be called when disabled, but fail early if so. */
+	if (!spi_enabled[port])
+		return EC_ERROR_BUSY;
+
+#ifndef CONFIG_SPI_HALFDUPLEX
+	if (rxlen == SPI_READBACK_ALL) {
+		buf = rxdata;
+		full_readback = 1;
+	} else {
+		rv = shared_mem_acquire(MAX(txlen, rxlen), &buf);
+		if (rv != EC_SUCCESS)
+			return rv;
+	}
+#endif
+
+	if (IS_ENABLED(CONFIG_USB_SPI)) {
+		spi_chip_select_already_asserted[port] =
+			!gpio_get_level(spi_device->gpio_cs);
+	}
+
+	/* Drive SS low */
+	gpio_set_level(spi_device->gpio_cs, 0);
+
+	spi_clear_rx_fifo(spi);
+
+	/* Initiate write part of the transaction, non-blocking. */
+	if (txlen) {
+		rv = spi_dma_start(port, txdata, buf, txlen);
+		if (rv != EC_SUCCESS)
+			goto err_free;
+#ifdef CONFIG_SPI_HALFDUPLEX
+		spi->cr1 |= STM32_SPI_CR1_BIDIOE;
+#endif
+	}
+
+	if (full_readback)
+		return EC_SUCCESS;
+
+	if (rxlen) {
+		/*
+		 * If "write then read" was requested, then we have to wait for
+		 * the write to complete, before we can initiate read.
+		 */
+		if (txlen) {
+			rv = spi_dma_wait(port);
+			if (rv != EC_SUCCESS)
+				goto err_free;
+
+			spi_clear_tx_fifo(spi);
+		}
+
+		/* Initiate read part of the transaction, non-blocking. */
+		rv = spi_dma_start(port, buf, rxdata, rxlen);
+		if (rv != EC_SUCCESS)
+			goto err_free;
+#ifdef CONFIG_SPI_HALFDUPLEX
+		spi->cr1 &= ~STM32_SPI_CR1_BIDIOE;
+#endif
+	}
+
+	/*
+	 * At this point, there is EITHER a pending non-blocking write OR a
+	 * pending non-blocking read.  In either case, spi_transaction_flush()
+	 * will wait for completion of the DMA transfer, and also make sure
+	 * that any last bits in the transmit shift register is flushed.
+	 */
+
+err_free:
+#ifndef CONFIG_SPI_HALFDUPLEX
+	if (!full_readback)
+		shared_mem_release(buf);
+#endif
+	return rv;
+}
+
+int spi_transaction_flush(const struct spi_device_t *spi_device)
+{
+	int rv = spi_dma_wait(spi_device->port);
+	int port = spi_device->port;
+	stm32_spi_regs_t *spi = SPI_REGS[port];
+
+	/*
+	 * For the case that the DMA transfer just finished was for SPI
+	 * transfer, ensure that the last bits are fully transmitted before
+	 * releasing CS.
+	 */
+	spi_clear_tx_fifo(spi);
+
+	if (!IS_ENABLED(CONFIG_USB_SPI) ||
+	    !spi_chip_select_already_asserted[spi_device->port]) {
+		/* Drive SS high */
+		gpio_set_level(spi_device->gpio_cs, 1);
+	}
+
+	return rv;
+}
+
+int spi_transaction_wait(const struct spi_device_t *spi_device)
+{
+	return spi_dma_wait(spi_device->port);
+}
+
+int spi_transaction(const struct spi_device_t *spi_device,
+		    const uint8_t *txdata, int txlen, uint8_t *rxdata,
+		    int rxlen)
+{
+	int rv;
+	int port = spi_device->port;
+
+	mutex_lock(spi_mutex + port);
+	rv = spi_transaction_async(spi_device, txdata, txlen, rxdata, rxlen);
+	rv |= spi_transaction_flush(spi_device);
+	mutex_unlock(spi_mutex + port);
+
+	return rv;
+}
diff --git a/chip/stm32/spi_master-stm32h7.c b/chip/stm32/spi_master-stm32h7.c
deleted file mode 100644
index 6f661b72bf..0000000000
--- a/chip/stm32/spi_master-stm32h7.c
+++ /dev/null
@@ -1,338 +0,0 @@
-/*
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * SPI master driver.
- */
-
-#include "common.h"
-#include "dma.h"
-#include "gpio.h"
-#include "shared_mem.h"
-#include "spi.h"
-#include "stm32-dma.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* SPI ports are used as master */
-static stm32_spi_regs_t *SPI_REGS[] = {
-#ifdef CONFIG_STM32_SPI1_MASTER
-	STM32_SPI1_REGS,
-#endif
-	STM32_SPI2_REGS,
-	STM32_SPI3_REGS,
-	STM32_SPI4_REGS,
-};
-
-/* DMA request mapping on channels */
-static uint8_t dma_req_tx[ARRAY_SIZE(SPI_REGS)] = {
-#ifdef CONFIG_STM32_SPI1_MASTER
-	DMAMUX1_REQ_SPI1_TX,
-#endif
-	DMAMUX1_REQ_SPI2_TX,
-	DMAMUX1_REQ_SPI3_TX,
-	DMAMUX1_REQ_SPI4_TX,
-};
-static uint8_t dma_req_rx[ARRAY_SIZE(SPI_REGS)] = {
-#ifdef CONFIG_STM32_SPI1_MASTER
-	DMAMUX1_REQ_SPI1_RX,
-#endif
-	DMAMUX1_REQ_SPI2_RX,
-	DMAMUX1_REQ_SPI3_RX,
-	DMAMUX1_REQ_SPI4_RX,
-};
-
-static struct mutex spi_mutex[ARRAY_SIZE(SPI_REGS)];
-
-#define SPI_TRANSACTION_TIMEOUT_USEC (800 * MSEC)
-
-static const struct dma_option dma_tx_option[] = {
-#ifdef CONFIG_STM32_SPI1_MASTER
-	{
-		STM32_DMAC_SPI1_TX, (void *)&STM32_SPI1_REGS->txdr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-	},
-#endif
-	{
-		STM32_DMAC_SPI2_TX, (void *)&STM32_SPI2_REGS->txdr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-	},
-	{
-		STM32_DMAC_SPI3_TX, (void *)&STM32_SPI3_REGS->txdr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-	},
-	{
-		STM32_DMAC_SPI4_TX, (void *)&STM32_SPI4_REGS->txdr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-	},
-};
-
-static const struct dma_option dma_rx_option[] = {
-#ifdef CONFIG_STM32_SPI1_MASTER
-	{
-		STM32_DMAC_SPI1_RX, (void *)&STM32_SPI1_REGS->rxdr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-	},
-#endif
-	{
-		STM32_DMAC_SPI2_RX, (void *)&STM32_SPI2_REGS->rxdr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-	},
-	{
-		STM32_DMAC_SPI3_RX, (void *)&STM32_SPI3_REGS->rxdr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-	},
-	{
-		STM32_DMAC_SPI4_RX, (void *)&STM32_SPI4_REGS->rxdr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-	},
-};
-
-static uint8_t spi_enabled[ARRAY_SIZE(SPI_REGS)];
-
-/**
- * Initialize SPI module, registers, and clocks
- *
- * - port: which port to initialize.
- */
-static void spi_master_config(int port)
-{
-	int i, div = 0;
-
-	stm32_spi_regs_t *spi = SPI_REGS[port];
-
-	/*
-	 * Set SPI master, baud rate, and software slave control.
-	 */
-	for (i = 0; i < spi_devices_used; i++)
-		if ((spi_devices[i].port == port) &&
-		    (div < spi_devices[i].div))
-			div = spi_devices[i].div;
-
-	spi->cr1 = STM32_SPI_CR1_SSI;
-	spi->cfg2 = STM32_SPI_CFG2_MSTR | STM32_SPI_CFG2_SSM
-			| STM32_SPI_CFG2_AFCNTR;
-	spi->cfg1 = STM32_SPI_CFG1_DATASIZE(8) | STM32_SPI_CFG1_FTHLV(4)
-			| STM32_SPI_CFG1_CRCSIZE(8) | STM32_SPI_CR1_DIV(div);
-
-	dma_select_channel(dma_tx_option[port].channel, dma_req_tx[port]);
-	dma_select_channel(dma_rx_option[port].channel, dma_req_rx[port]);
-}
-
-static int spi_master_initialize(int port)
-{
-	int i;
-
-	spi_master_config(port);
-
-	for (i = 0; i < spi_devices_used; i++) {
-		if (spi_devices[i].port != port)
-			continue;
-		/* Drive SS high */
-		gpio_set_level(spi_devices[i].gpio_cs, 1);
-	}
-
-	/* Set flag */
-	spi_enabled[port] = 1;
-
-	return EC_SUCCESS;
-}
-
-/**
- * Shutdown SPI module
- */
-static int spi_master_shutdown(int port)
-{
-	int rv = EC_SUCCESS;
-	stm32_spi_regs_t *spi = SPI_REGS[port];
-
-	/* Set flag */
-	spi_enabled[port] = 0;
-
-	/* Disable DMA streams */
-	dma_disable(dma_tx_option[port].channel);
-	dma_disable(dma_rx_option[port].channel);
-
-	/* Disable SPI */
-	spi->cr1 &= ~STM32_SPI_CR1_SPE;
-
-	/* Disable DMA buffers */
-	spi->cfg1 &= ~(STM32_SPI_CFG1_TXDMAEN | STM32_SPI_CFG1_RXDMAEN);
-
-	return rv;
-}
-
-int spi_enable(int port, int enable)
-{
-	if (enable == spi_enabled[port])
-		return EC_SUCCESS;
-	if (enable)
-		return spi_master_initialize(port);
-	else
-		return spi_master_shutdown(port);
-}
-
-static int spi_dma_start(int port, const uint8_t *txdata,
-		uint8_t *rxdata, int len)
-{
-	dma_chan_t *txdma;
-	stm32_spi_regs_t *spi = SPI_REGS[port];
-
-	/*
-	 * Workaround for STM32H7 errata: without resetting the SPI controller,
-	 * the RX DMA requests will happen too early on the 2nd transfer.
-	 */
-	STM32_RCC_APB2RSTR = STM32_RCC_PB2_SPI4;
-	STM32_RCC_APB2RSTR = 0;
-	dma_clear_isr(dma_tx_option[port].channel);
-	dma_clear_isr(dma_rx_option[port].channel);
-	/* restore proper SPI configuration registers. */
-	spi_master_config(port);
-
-	spi->cr2 = len;
-	spi->cfg1 |= STM32_SPI_CFG1_RXDMAEN;
-	/* Set up RX DMA */
-	if (rxdata)
-		dma_start_rx(&dma_rx_option[port], len, rxdata);
-
-	/* Set up TX DMA */
-	if (txdata) {
-		txdma = dma_get_channel(dma_tx_option[port].channel);
-		dma_prepare_tx(&dma_tx_option[port], len, txdata);
-		dma_go(txdma);
-	}
-
-	spi->cfg1 |= STM32_SPI_CFG1_TXDMAEN;
-	spi->cr1 |= STM32_SPI_CR1_SPE;
-	spi->cr1 |= STM32_SPI_CR1_CSTART;
-
-	return EC_SUCCESS;
-}
-
-static inline bool dma_is_enabled_(const struct dma_option *option)
-{
-	return dma_is_enabled(dma_get_channel(option->channel));
-}
-
-static int spi_dma_wait(int port)
-{
-	timestamp_t timeout;
-	stm32_spi_regs_t *spi = SPI_REGS[port];
-	int rv = EC_SUCCESS;
-
-	/* Wait for DMA transmission to complete */
-	if (dma_is_enabled_(&dma_tx_option[port])) {
-		rv = dma_wait(dma_tx_option[port].channel);
-		if (rv)
-			return rv;
-
-		timeout.val = get_time().val + SPI_TRANSACTION_TIMEOUT_USEC;
-		/* Wait for FIFO empty and BSY bit clear */
-		while (!(spi->sr & (STM32_SPI_SR_TXC)))
-			if (get_time().val > timeout.val)
-				return EC_ERROR_TIMEOUT;
-
-		/* Disable TX DMA */
-		dma_disable(dma_tx_option[port].channel);
-	}
-
-	/* Wait for DMA reception to complete */
-	if (dma_is_enabled_(&dma_rx_option[port])) {
-		rv = dma_wait(dma_rx_option[port].channel);
-		if (rv)
-			return rv;
-
-		timeout.val = get_time().val + SPI_TRANSACTION_TIMEOUT_USEC;
-		/* Wait for FRLVL[1:0] to indicate FIFO empty */
-		while (spi->sr & (STM32_SPI_SR_FRLVL | STM32_SPI_SR_RXNE))
-			if (get_time().val > timeout.val)
-				return EC_ERROR_TIMEOUT;
-
-		/* Disable RX DMA */
-		dma_disable(dma_rx_option[port].channel);
-	}
-
-	spi->cr1 &= ~STM32_SPI_CR1_SPE;
-	spi->cfg1 &= ~(STM32_SPI_CFG1_TXDMAEN | STM32_SPI_CFG1_RXDMAEN);
-
-	return rv;
-}
-
-int spi_transaction_async(const struct spi_device_t *spi_device,
-			  const uint8_t *txdata, int txlen,
-			  uint8_t *rxdata, int rxlen)
-{
-	int rv = EC_SUCCESS;
-	int port = spi_device->port;
-	int full_readback = 0;
-
-	char *buf = NULL;
-
-#ifndef CONFIG_SPI_HALFDUPLEX
-	if (rxlen == SPI_READBACK_ALL) {
-		buf = rxdata;
-		full_readback = 1;
-	} else {
-		rv = shared_mem_acquire(MAX(txlen, rxlen), &buf);
-		if (rv != EC_SUCCESS)
-			return rv;
-	}
-#endif
-
-	/* Drive SS low */
-	gpio_set_level(spi_device->gpio_cs, 0);
-
-	rv = spi_dma_start(port, txdata, buf, txlen);
-	if (rv != EC_SUCCESS)
-		goto err_free;
-
-	if (full_readback)
-		return EC_SUCCESS;
-
-	if (rxlen) {
-		rv = spi_dma_wait(port);
-		if (rv != EC_SUCCESS)
-			goto err_free;
-
-		rv = spi_dma_start(port, buf, rxdata, rxlen);
-		if (rv != EC_SUCCESS)
-			goto err_free;
-	}
-
-err_free:
-	if (!full_readback)
-		shared_mem_release(buf);
-	return rv;
-}
-
-int spi_transaction_flush(const struct spi_device_t *spi_device)
-{
-	int rv = spi_dma_wait(spi_device->port);
-
-	/* Drive SS high */
-	gpio_set_level(spi_device->gpio_cs, 1);
-
-	return rv;
-}
-
-int spi_transaction_wait(const struct spi_device_t *spi_device)
-{
-	return spi_dma_wait(spi_device->port);
-}
-
-int spi_transaction(const struct spi_device_t *spi_device,
-		    const uint8_t *txdata, int txlen,
-		    uint8_t *rxdata, int rxlen)
-{
-	int rv;
-	int port = spi_device->port;
-
-	mutex_lock(spi_mutex + port);
-	rv = spi_transaction_async(spi_device, txdata, txlen, rxdata, rxlen);
-	rv |= spi_transaction_flush(spi_device);
-	mutex_unlock(spi_mutex + port);
-
-	return rv;
-}
diff --git a/chip/stm32/spi_master.c b/chip/stm32/spi_master.c
deleted file mode 100644
index c2d36bb4d9..0000000000
--- a/chip/stm32/spi_master.c
+++ /dev/null
@@ -1,437 +0,0 @@
-/*
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * SPI master driver.
- */
-
-#include "common.h"
-#include "dma.h"
-#include "gpio.h"
-#include "hwtimer.h"
-#include "shared_mem.h"
-#include "spi.h"
-#include "stm32-dma.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#if defined(CHIP_VARIANT_STM32F373)  || \
-	defined(CHIP_FAMILY_STM32L4) || \
-	defined(CHIP_VARIANT_STM32F76X)
-#define HAS_SPI3
-#else
-#undef  HAS_SPI3
-#endif
-
-/* The second (and third if available) SPI port are used as master */
-static stm32_spi_regs_t *SPI_REGS[] = {
-#ifdef CONFIG_STM32_SPI1_MASTER
-	STM32_SPI1_REGS,
-#endif
-	STM32_SPI2_REGS,
-#ifdef HAS_SPI3
-	STM32_SPI3_REGS,
-#endif
-};
-
-#ifdef CHIP_FAMILY_STM32L4
-/* DMA request mapping on channels */
-static uint8_t dma_req[ARRAY_SIZE(SPI_REGS)] = {
-#ifdef CONFIG_STM32_SPI1_MASTER
-	/* SPI1 */ 1,
-#endif
-	/* SPI2 */ 1,
-	/* SPI3 */ 3,
-};
-#endif
-
-static struct mutex spi_mutex[ARRAY_SIZE(SPI_REGS)];
-
-#define SPI_TRANSACTION_TIMEOUT_USEC (800 * MSEC)
-
-/* Default DMA channel options */
-#ifdef CHIP_FAMILY_STM32F4
-#define F4_CHANNEL(ch)	STM32_DMA_CCR_CHANNEL(ch)
-#else
-#define F4_CHANNEL(ch)	0
-#endif
-
-static const struct dma_option dma_tx_option[] = {
-#ifdef CONFIG_STM32_SPI1_MASTER
-	{
-		STM32_DMAC_SPI1_TX, (void *)&STM32_SPI1_REGS->dr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-		| F4_CHANNEL(STM32_SPI1_TX_REQ_CH)
-	},
-#endif
-	{
-		STM32_DMAC_SPI2_TX, (void *)&STM32_SPI2_REGS->dr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-		| F4_CHANNEL(STM32_SPI2_TX_REQ_CH)
-	},
-#ifdef HAS_SPI3
-	{
-		STM32_DMAC_SPI3_TX, (void *)&STM32_SPI3_REGS->dr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-		| F4_CHANNEL(STM32_SPI3_TX_REQ_CH)
-	},
-#endif
-};
-
-static const struct dma_option dma_rx_option[] = {
-#ifdef CONFIG_STM32_SPI1_MASTER
-	{
-		STM32_DMAC_SPI1_RX, (void *)&STM32_SPI1_REGS->dr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-		| F4_CHANNEL(STM32_SPI1_RX_REQ_CH)
-	},
-#endif
-	{
-		STM32_DMAC_SPI2_RX, (void *)&STM32_SPI2_REGS->dr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-		| F4_CHANNEL(STM32_SPI2_RX_REQ_CH)
-	},
-#ifdef HAS_SPI3
-	{
-		STM32_DMAC_SPI3_RX, (void *)&STM32_SPI3_REGS->dr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-		| F4_CHANNEL(STM32_SPI3_RX_REQ_CH)
-	},
-#endif
-};
-
-static uint8_t spi_enabled[ARRAY_SIZE(SPI_REGS)];
-
-static int spi_tx_done(stm32_spi_regs_t *spi)
-{
-	return !(spi->sr & (STM32_SPI_SR_FTLVL | STM32_SPI_SR_BSY));
-}
-
-static int spi_rx_done(stm32_spi_regs_t *spi)
-{
-	return !(spi->sr & (STM32_SPI_SR_FRLVL | STM32_SPI_SR_RXNE));
-}
-
-/* Read until RX FIFO is empty (i.e. RX done) */
-static int spi_clear_rx_fifo(stm32_spi_regs_t *spi)
-{
-	uint8_t unused __attribute__((unused));
-	uint32_t start = __hw_clock_source_read(), delta;
-
-	while (!spi_rx_done(spi)) {
-		unused = spi->dr;  /* Read one byte from FIFO */
-		delta = __hw_clock_source_read() - start;
-		if (delta >= SPI_TRANSACTION_TIMEOUT_USEC)
-			return EC_ERROR_TIMEOUT;
-	}
-	return EC_SUCCESS;
-}
-
-/* Wait until TX FIFO is empty (i.e. TX done) */
-static int spi_clear_tx_fifo(stm32_spi_regs_t *spi)
-{
-	uint32_t start = __hw_clock_source_read(), delta;
-
-	while (!spi_tx_done(spi)) {
-		/* wait for TX complete */
-		delta = __hw_clock_source_read() - start;
-		if (delta >= SPI_TRANSACTION_TIMEOUT_USEC)
-			return EC_ERROR_TIMEOUT;
-	}
-	return EC_SUCCESS;
-}
-
-/**
- * Initialize SPI module, registers, and clocks
- *
- * - port: which port to initialize.
- */
-static int spi_master_initialize(int port)
-{
-	int i, div = 0;
-
-	stm32_spi_regs_t *spi = SPI_REGS[port];
-
-	/*
-	 * Set SPI master, baud rate, and software slave control.
-	 * */
-	for (i = 0; i < spi_devices_used; i++)
-		if ((spi_devices[i].port == port) &&
-		    (div < spi_devices[i].div))
-			div = spi_devices[i].div;
-
-	/*
-	 * STM32F412
-	 * Section 26.3.5 Slave select (NSS) pin management and Figure 276
-	 * https://www.st.com/resource/en/reference_manual/dm00180369.pdf#page=817
-	 *
-	 * The documentation in this section is a bit confusing, so here's a
-	 * summary based on discussion with ST:
-	 *
-	 * Software NSS management (SSM = 1):
-	 *   - In master mode, the NSS output is deactivated. You need to use a
-	 *     GPIO in output mode for slave select. This is generally used for
-	 *     multi-slave operation, but you can also use it for single slave
-	 *     operation. In this case, you should make sure to configure a GPIO
-	 *     for NSS, but *not* activate the SPI alternate function on that
-	 *     same pin since that will enable hardware NSS management (see
-	 *     below).
-	 *   - In slave mode, the NSS input level is equal to the SSI bit value.
-	 *
-	 * Hardware NSS management (SSM = 0):
-	 *   - In slave mode, when NSS pin is detected low the slave (MCU) is
-	 *     selected.
-	 *   - In master mode, there are two configurations, depending on the
-	 *     SSOE bit in register SPIx_CR1.
-	 *       - NSS output enable (SSM=0, SSOE=1):
-	 *         The MCU (master) drives NSS low as soon as SPI is enabled
-	 *         (SPE=1) and releases it when SPI is disabled (SPE=0).
-	 *
-	 *       - NSS output disable (SSM=0, SSOE=0):
-	 *         Allows multimaster capability. The MCU (master) drives NSS
-	 *         low.  If another master tries to takes control of the bus and
-	 *         NSS is pulled low, a mode fault is generated and the MCU
-	 *         changes to slave mode.
-	 *
-	 *   - NSS output disable (SSM=0, SSOE=0): if the MCU is acting as
-	 *     master on the bus, this config allows multimaster capability. If
-	 *     the NSS pin is pulled low in this mode, the SPI enters master
-	 *     mode fault state and the device is automatically reconfigured in
-	 *     slave mode.  In slave mode, the NSS pin works as a standard "chip
-	 *     select" input and the slave is selected while NSS lin is at low
-	 *     level.
-	 */
-	spi->cr1 = STM32_SPI_CR1_MSTR | STM32_SPI_CR1_SSM | STM32_SPI_CR1_SSI |
-		(div << 3);
-
-#ifdef CHIP_FAMILY_STM32L4
-	dma_select_channel(dma_tx_option[port].channel, dma_req[port]);
-	dma_select_channel(dma_rx_option[port].channel, dma_req[port]);
-#endif
-	/*
-	 * Configure 8-bit datasize, set FRXTH, enable DMA,
-	 * and set data size (applies to STM32F0 only).
-	 *
-	 * STM32F412:
-	 * https://www.st.com/resource/en/reference_manual/dm00180369.pdf#page=852
-	 *
-	 *
-	 * STM32F0:
-	 * https://www.st.com/resource/en/reference_manual/dm00031936.pdf#page=803
-	 */
-	spi->cr2 = STM32_SPI_CR2_TXDMAEN | STM32_SPI_CR2_RXDMAEN |
-			STM32_SPI_CR2_FRXTH | STM32_SPI_CR2_DATASIZE(8);
-
-#ifdef CONFIG_SPI_HALFDUPLEX
-	spi->cr1 |= STM32_SPI_CR1_BIDIMODE | STM32_SPI_CR1_BIDIOE;
-#endif
-
-	/* Drive Chip Select high for all ports before turning on SPI module */
-	for (i = 0; i < spi_devices_used; i++) {
-		if (spi_devices[i].port != port)
-			continue;
-		gpio_set_level(spi_devices[i].gpio_cs, 1);
-	}
-
-	/* Enable SPI hardware module. This will actively drive the CLK pin */
-	spi->cr1 |= STM32_SPI_CR1_SPE;
-
-	/* Set flag */
-	spi_enabled[port] = 1;
-
-	return EC_SUCCESS;
-}
-
-/**
- * Shutdown SPI module
- */
-static int spi_master_shutdown(int port)
-{
-	int rv = EC_SUCCESS;
-
-	stm32_spi_regs_t *spi = SPI_REGS[port];
-
-	/* Set flag */
-	spi_enabled[port] = 0;
-
-	/* Disable DMA streams */
-	dma_disable(dma_tx_option[port].channel);
-	dma_disable(dma_rx_option[port].channel);
-
-	/* Disable SPI. Let the CLK pin float. */
-	spi->cr1 &= ~STM32_SPI_CR1_SPE;
-
-	spi_clear_rx_fifo(spi);
-
-	/* Disable DMA buffers */
-	spi->cr2 &= ~(STM32_SPI_CR2_TXDMAEN | STM32_SPI_CR2_RXDMAEN);
-
-	return rv;
-}
-
-int spi_enable(int port, int enable)
-{
-	if (enable == spi_enabled[port])
-		return EC_SUCCESS;
-	if (enable)
-		return spi_master_initialize(port);
-	else
-		return spi_master_shutdown(port);
-}
-
-static int spi_dma_start(int port, const uint8_t *txdata,
-			 uint8_t *rxdata, int len)
-{
-	dma_chan_t *txdma;
-
-	/* Set up RX DMA */
-	if (rxdata)
-		dma_start_rx(&dma_rx_option[port], len, rxdata);
-
-	/* Set up TX DMA */
-	if (txdata) {
-		txdma = dma_get_channel(dma_tx_option[port].channel);
-		dma_prepare_tx(&dma_tx_option[port], len, txdata);
-		dma_go(txdma);
-	}
-
-	return EC_SUCCESS;
-}
-
-static bool dma_is_enabled_(const struct dma_option *option)
-{
-	return dma_is_enabled(dma_get_channel(option->channel));
-}
-
-static int spi_dma_wait(int port)
-{
-	int rv = EC_SUCCESS;
-
-	/* Wait for DMA transmission to complete */
-	if (dma_is_enabled_(&dma_tx_option[port])) {
-		/*
-		 * In TX mode, SPI only generates clock when we write to FIFO.
-		 * Therefore, even though `dma_wait` polls with interval 0.1ms,
-		 * we won't send extra bytes.
-		 */
-		rv = dma_wait(dma_tx_option[port].channel);
-		if (rv)
-			return rv;
-		/* Disable TX DMA */
-		dma_disable(dma_tx_option[port].channel);
-	}
-
-	/* Wait for DMA reception to complete */
-	if (dma_is_enabled_(&dma_rx_option[port])) {
-		/*
-		 * Because `dma_wait` polls with interval 0.1ms, we will read at
-		 * least ~100 bytes (with 8MHz clock).  If you don't want this
-		 * overhead, you can use interrupt handler
-		 * (`dma_enable_tc_interrupt_callback`) and disable SPI
-		 * interface in callback function.
-		 */
-		rv = dma_wait(dma_rx_option[port].channel);
-		if (rv)
-			return rv;
-		/* Disable RX DMA */
-		dma_disable(dma_rx_option[port].channel);
-	}
-	return rv;
-}
-
-int spi_transaction_async(const struct spi_device_t *spi_device,
-			  const uint8_t *txdata, int txlen,
-			  uint8_t *rxdata, int rxlen)
-{
-	int rv = EC_SUCCESS;
-	int port = spi_device->port;
-	int full_readback = 0;
-
-	stm32_spi_regs_t *spi = SPI_REGS[port];
-	char *buf = NULL;
-
-	/* We should not ever be called when disabled, but fail early if so. */
-	if (!spi_enabled[port])
-		return EC_ERROR_BUSY;
-
-#ifndef CONFIG_SPI_HALFDUPLEX
-	if (rxlen == SPI_READBACK_ALL) {
-		buf = rxdata;
-		full_readback = 1;
-	} else {
-		rv = shared_mem_acquire(MAX(txlen, rxlen), &buf);
-		if (rv != EC_SUCCESS)
-			return rv;
-	}
-#endif
-
-	/* Drive SS low */
-	gpio_set_level(spi_device->gpio_cs, 0);
-
-	spi_clear_rx_fifo(spi);
-
-	rv = spi_dma_start(port, txdata, buf, txlen);
-	if (rv != EC_SUCCESS)
-		goto err_free;
-
-#ifdef CONFIG_SPI_HALFDUPLEX
-	spi->cr1 |= STM32_SPI_CR1_BIDIOE;
-#endif
-
-	if (full_readback)
-		return EC_SUCCESS;
-
-	rv = spi_dma_wait(port);
-	if (rv != EC_SUCCESS)
-		goto err_free;
-
-	spi_clear_tx_fifo(spi);
-
-	if (rxlen) {
-		rv = spi_dma_start(port, buf, rxdata, rxlen);
-		if (rv != EC_SUCCESS)
-			goto err_free;
-#ifdef CONFIG_SPI_HALFDUPLEX
-		spi->cr1 &= ~STM32_SPI_CR1_BIDIOE;
-#endif
-	}
-
-err_free:
-#ifndef CONFIG_SPI_HALFDUPLEX
-	if (!full_readback)
-		shared_mem_release(buf);
-#endif
-	return rv;
-}
-
-int spi_transaction_flush(const struct spi_device_t *spi_device)
-{
-	int rv = spi_dma_wait(spi_device->port);
-
-	/* Drive SS high */
-	gpio_set_level(spi_device->gpio_cs, 1);
-
-	return rv;
-}
-
-int spi_transaction_wait(const struct spi_device_t *spi_device)
-{
-	return spi_dma_wait(spi_device->port);
-}
-
-int spi_transaction(const struct spi_device_t *spi_device,
-		    const uint8_t *txdata, int txlen,
-		    uint8_t *rxdata, int rxlen)
-{
-	int rv;
-	int port = spi_device->port;
-
-	mutex_lock(spi_mutex + port);
-	rv = spi_transaction_async(spi_device, txdata, txlen, rxdata, rxlen);
-	rv |= spi_transaction_flush(spi_device);
-	mutex_unlock(spi_mutex + port);
-
-	return rv;
-}
diff --git a/chip/stm32/stm32-dma.h b/chip/stm32/stm32-dma.h
index 06233b9c93..3bda9ec41d 100644
--- a/chip/stm32/stm32-dma.h
+++ b/chip/stm32/stm32-dma.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/stm32/system.c b/chip/stm32/system.c
index aad35820c7..6d7c4b624a 100644
--- a/chip/stm32/system.c
+++ b/chip/stm32/system.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,6 +9,7 @@
 #include "clock.h"
 #include "console.h"
 #include "cpu.h"
+#include "cros_version.h"
 #include "flash.h"
 #include "gpio_chip.h"
 #include "hooks.h"
@@ -18,7 +19,6 @@
 #include "system.h"
 #include "task.h"
 #include "util.h"
-#include "version.h"
 #include "watchdog.h"
 
 #ifdef CONFIG_STM32_CLOCK_LSE
@@ -28,10 +28,10 @@
 #define BDCR_SRC BDCR_SRC_LSI
 #define BDCR_RDY 0
 #endif
-#define BDCR_ENABLE_VALUE (STM32_RCC_BDCR_RTCEN | BDCR_RTCSEL(BDCR_SRC) | \
-			BDCR_RDY)
-#define BDCR_ENABLE_MASK (BDCR_ENABLE_VALUE | BDCR_RTCSEL_MASK | \
-			STM32_RCC_BDCR_BDRST)
+#define BDCR_ENABLE_VALUE \
+	(STM32_RCC_BDCR_RTCEN | BDCR_RTCSEL(BDCR_SRC) | BDCR_RDY)
+#define BDCR_ENABLE_MASK \
+	(BDCR_ENABLE_VALUE | BDCR_RTCSEL_MASK | STM32_RCC_BDCR_BDRST)
 
 #ifdef CONFIG_USB_PD_DUAL_ROLE
 BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT <= 3);
@@ -87,12 +87,16 @@ static void check_reset_cause(void)
 {
 	uint32_t flags = chip_read_reset_flags();
 	uint32_t raw_cause = STM32_RCC_RESET_CAUSE;
+#ifdef STM32_PWR_RESET_CAUSE
 	uint32_t pwr_status = STM32_PWR_RESET_CAUSE;
+#endif
 
 	/* Clear the hardware reset cause by setting the RMVF bit */
 	STM32_RCC_RESET_CAUSE |= RESET_CAUSE_RMVF;
+#ifdef STM32_PWR_RESET_CAUSE
 	/* Clear SBF in PWR_CSR */
 	STM32_PWR_RESET_CAUSE_CLR |= RESET_CAUSE_SBF_CLR;
+#endif
 	/* Clear saved reset flags */
 	chip_save_reset_flags(0);
 
@@ -114,9 +118,11 @@ static void check_reset_cause(void)
 	if (raw_cause & RESET_CAUSE_PIN)
 		flags |= EC_RESET_FLAG_RESET_PIN;
 
+#ifdef STM32_PWR_RESET_CAUSE
 	if (pwr_status & RESET_CAUSE_SBF)
 		/* Hibernated and subsequently awakened */
 		flags |= EC_RESET_FLAG_HIBERNATE;
+#endif
 
 	if (!flags && (raw_cause & RESET_CAUSE_OTHER))
 		flags |= EC_RESET_FLAG_OTHER;
@@ -143,61 +149,73 @@ void chip_pre_init(void)
 	uint32_t apb2fz_reg = 0;
 
 #if defined(CHIP_FAMILY_STM32F0)
-	apb1fz_reg =
-		STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM6 |
-		STM32_RCC_PB1_TIM7 | STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG;
+	apb1fz_reg = STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 |
+		     STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_TIM7 |
+		     STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG;
 	apb2fz_reg = STM32_RCC_PB2_TIM15 | STM32_RCC_PB2_TIM16 |
-		STM32_RCC_PB2_TIM17 | STM32_RCC_PB2_TIM1;
+		     STM32_RCC_PB2_TIM17 | STM32_RCC_PB2_TIM1;
 
 	/* enable clock to debug module before writing */
 	STM32_RCC_APB2ENR |= STM32_RCC_DBGMCUEN;
 #elif defined(CHIP_FAMILY_STM32F3)
-	apb1fz_reg =
-		STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM4 |
-		STM32_RCC_PB1_TIM5 | STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_TIM7 |
-		STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG;
-	apb2fz_reg =
-		STM32_RCC_PB2_TIM15 | STM32_RCC_PB2_TIM16 | STM32_RCC_PB2_TIM17;
+	apb1fz_reg = STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 |
+		     STM32_RCC_PB1_TIM4 | STM32_RCC_PB1_TIM5 |
+		     STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_TIM7 |
+		     STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG;
+	apb2fz_reg = STM32_RCC_PB2_TIM15 | STM32_RCC_PB2_TIM16 |
+		     STM32_RCC_PB2_TIM17;
 #elif defined(CHIP_FAMILY_STM32F4)
-	apb1fz_reg =
-		STM32_RCC_PB1_TIM2  | STM32_RCC_PB1_TIM3  | STM32_RCC_PB1_TIM4 |
-		STM32_RCC_PB1_TIM5  | STM32_RCC_PB1_TIM6  | STM32_RCC_PB1_TIM7 |
-		STM32_RCC_PB1_TIM12 | STM32_RCC_PB1_TIM13 | STM32_RCC_PB1_TIM14|
-		STM32_RCC_PB1_RTC   | STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG;
-	apb2fz_reg =
-		STM32_RCC_PB2_TIM1  | STM32_RCC_PB2_TIM8  | STM32_RCC_PB2_TIM9 |
-		STM32_RCC_PB2_TIM10 | STM32_RCC_PB2_TIM11;
+	apb1fz_reg = STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 |
+		     STM32_RCC_PB1_TIM4 | STM32_RCC_PB1_TIM5 |
+		     STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_TIM7 |
+		     STM32_RCC_PB1_TIM12 | STM32_RCC_PB1_TIM13 |
+		     STM32_RCC_PB1_TIM14 | STM32_RCC_PB1_RTC |
+		     STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG;
+	apb2fz_reg = STM32_RCC_PB2_TIM1 | STM32_RCC_PB2_TIM8 |
+		     STM32_RCC_PB2_TIM9 | STM32_RCC_PB2_TIM10 |
+		     STM32_RCC_PB2_TIM11;
 #elif defined(CHIP_FAMILY_STM32L4)
-	apb1fz_reg =
-		STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM4 |
-		STM32_RCC_PB1_TIM5 | STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_TIM7 |
-		STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG;
+
+#ifdef CHIP_VARIANT_STM32L431X
+	apb1fz_reg = STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM7 |
+		     STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_WWDG |
+		     STM32_RCC_PB1_IWDG;
+	apb2fz_reg = STM32_RCC_PB2_TIM1 | STM32_RCC_PB2_TIM15 |
+		     STM32_RCC_PB2_TIM16;
+#else
+	apb1fz_reg = STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 |
+		     STM32_RCC_PB1_TIM4 | STM32_RCC_PB1_TIM5 |
+		     STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_TIM7 |
+		     STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG;
 	apb2fz_reg = STM32_RCC_PB2_TIM1 | STM32_RCC_PB2_TIM8;
+#endif
 #elif defined(CHIP_FAMILY_STM32L)
-	apb1fz_reg =
-		STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM4 |
-		STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG;
+	apb1fz_reg = STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 |
+		     STM32_RCC_PB1_TIM4 | STM32_RCC_PB1_WWDG |
+		     STM32_RCC_PB1_IWDG;
 	apb2fz_reg = STM32_RCC_PB2_TIM9 | STM32_RCC_PB2_TIM10 |
-		STM32_RCC_PB2_TIM11;
+		     STM32_RCC_PB2_TIM11;
 #elif defined(CHIP_FAMILY_STM32G4)
-	apb1fz_reg =
-		STM32_DBGMCU_APB1FZ_TIM2 | STM32_DBGMCU_APB1FZ_TIM3 |
-		STM32_DBGMCU_APB1FZ_TIM4 | STM32_DBGMCU_APB1FZ_TIM5 |
-		STM32_DBGMCU_APB1FZ_TIM6 | STM32_DBGMCU_APB1FZ_TIM7 |
-		STM32_DBGMCU_APB1FZ_RTC  | STM32_DBGMCU_APB1FZ_WWDG |
-		STM32_DBGMCU_APB1FZ_IWDG;
-	apb2fz_reg =
-		STM32_DBGMCU_APB2FZ_TIM1 | STM32_DBGMCU_APB2FZ_TIM8 |
-		STM32_DBGMCU_APB2FZ_TIM15 | STM32_DBGMCU_APB2FZ_TIM16 |
-		STM32_DBGMCU_APB2FZ_TIM17 | STM32_DBGMCU_APB2FZ_TIM20;
+	apb1fz_reg = STM32_DBGMCU_APB1FZ_TIM2 | STM32_DBGMCU_APB1FZ_TIM3 |
+		     STM32_DBGMCU_APB1FZ_TIM4 | STM32_DBGMCU_APB1FZ_TIM5 |
+		     STM32_DBGMCU_APB1FZ_TIM6 | STM32_DBGMCU_APB1FZ_TIM7 |
+		     STM32_DBGMCU_APB1FZ_RTC | STM32_DBGMCU_APB1FZ_WWDG |
+		     STM32_DBGMCU_APB1FZ_IWDG;
+	apb2fz_reg = STM32_DBGMCU_APB2FZ_TIM1 | STM32_DBGMCU_APB2FZ_TIM8 |
+		     STM32_DBGMCU_APB2FZ_TIM15 | STM32_DBGMCU_APB2FZ_TIM16 |
+		     STM32_DBGMCU_APB2FZ_TIM17 | STM32_DBGMCU_APB2FZ_TIM20;
 #elif defined(CHIP_FAMILY_STM32H7)
 	/* TODO(b/67081508) */
 #endif
-
+#if defined(CHIP_FAMILY_STM32L5)
+	(void)apb1fz_reg;
+	(void)apb2fz_reg;
+#else
 	if (apb1fz_reg)
 		STM32_DBGMCU_APB1FZ |= apb1fz_reg;
 	if (apb2fz_reg)
 		STM32_DBGMCU_APB2FZ |= apb2fz_reg;
+#endif
 }
 
 #ifdef CONFIG_PVD
@@ -234,7 +252,7 @@ static void configure_pvd(void)
 	STM32_PWR_CR |= STM32_PWR_PVDE;
 }
 
-void pvd_interrupt(void)
+static void pvd_interrupt(void)
 {
 	/* Clear Pending Register */
 	STM32_EXTI_PR = EXTI_PVD_EVENT;
@@ -247,21 +265,27 @@ DECLARE_IRQ(STM32_IRQ_PVD, pvd_interrupt, HOOK_PRIO_FIRST);
 
 void system_pre_init(void)
 {
-#ifdef CONFIG_SOFTWARE_PANIC
 	uint16_t reason, info;
-	uint8_t exception;
-#endif
+	uint8_t exception, panic_flags;
+	struct panic_data *pdata;
 
 	/* enable clock on Power module */
 #ifndef CHIP_FAMILY_STM32H7
+#if defined(CHIP_FAMILY_STM32L4) || defined(CHIP_FAMILY_STM32L5)
+	STM32_RCC_APB1ENR1 |= STM32_RCC_PWREN;
+#else
 	STM32_RCC_APB1ENR |= STM32_RCC_PWREN;
 #endif
+#endif
 #if defined(CHIP_FAMILY_STM32F4)
 	/* enable backup registers */
 	STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_BKPSRAMEN;
 #elif defined(CHIP_FAMILY_STM32H7)
 	/* enable backup registers */
 	STM32_RCC_AHB4ENR |= BIT(28);
+#elif defined(CHIP_FAMILY_STM32L4) || defined(CHIP_FAMILY_STM32L5)
+	/* enable RTC APB clock */
+	STM32_RCC_APB1ENR1 |= STM32_RCC_APB1ENR1_RTCAPBEN;
 #else
 	/* enable backup registers */
 	STM32_RCC_APB1ENR |= BIT(27);
@@ -280,6 +304,13 @@ void system_pre_init(void)
 	/* Wait for LSI to be ready */
 	while (!(STM32_RCC_CSR & BIT(1)))
 		;
+
+#if defined(CHIP_FAMILY_STM32G4)
+	/* Make sure PWR clock is enabled */
+	STM32_RCC_APB1ENR1 |= STM32_RCC_APB1ENR1_PWREN;
+	/* Enable access to backup domain registers */
+	STM32_PWR_CR1 |= STM32_PWR_CR1_DBP;
+#endif
 	/* re-configure RTC if needed */
 #ifdef CHIP_FAMILY_STM32L
 	if ((STM32_RCC_CSR & 0x00C30000) != 0x00420000) {
@@ -288,9 +319,10 @@ void system_pre_init(void)
 		/* Enable RTC and use LSI as clock source */
 		STM32_RCC_CSR = (STM32_RCC_CSR & ~0x00C30000) | 0x00420000;
 	}
-#elif defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \
-	defined(CHIP_FAMILY_STM32L4) || defined(CHIP_FAMILY_STM32F4) || \
-	defined(CHIP_FAMILY_STM32H7) || defined(CHIP_FAMILY_STM32G4)
+#elif defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) ||   \
+	defined(CHIP_FAMILY_STM32L4) || defined(CHIP_FAMILY_STM32L5) || \
+	defined(CHIP_FAMILY_STM32F4) || defined(CHIP_FAMILY_STM32H7) || \
+	defined(CHIP_FAMILY_STM32G4)
 	if ((STM32_RCC_BDCR & BDCR_ENABLE_MASK) != BDCR_ENABLE_VALUE) {
 		/* The RTC settings are bad, we need to reset it */
 		STM32_RCC_BDCR |= STM32_RCC_BDCR_BDRST;
@@ -311,7 +343,6 @@ void system_pre_init(void)
 
 	check_reset_cause();
 
-#ifdef CONFIG_SOFTWARE_PANIC
 	/* Restore then clear saved panic reason */
 	reason = bkpdata_read(BKPDATA_INDEX_SAVED_PANIC_REASON);
 	info = bkpdata_read(BKPDATA_INDEX_SAVED_PANIC_INFO);
@@ -322,7 +353,20 @@ void system_pre_init(void)
 		bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_INFO, 0);
 		bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_EXCEPTION, 0);
 	}
-#endif
+
+	/*
+	 * Older ROs restore reason, info, and exception, but do not support
+	 * the saved panic flags. In that case, we will let RW handle restoring
+	 * the panic flags. If we get to this point in the code and the panic
+	 * data does not exist, it doesn't make sense to try to only restore
+	 * the panic flags, the information was lost.
+	 */
+	pdata = panic_get_data();
+	panic_flags = bkpdata_read(BKPDATA_INDEX_SAVED_PANIC_FLAGS);
+	if (pdata && panic_flags) {
+		pdata->flags = panic_flags;
+		bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_FLAGS, 0);
+	}
 
 #ifdef CONFIG_PVD
 	configure_pvd();
@@ -358,32 +402,47 @@ void system_reset(int flags)
 	if (flags & SYSTEM_RESET_STAY_IN_RO)
 		save_flags |= EC_RESET_FLAG_STAY_IN_RO;
 
-#ifdef CONFIG_STM32_RESET_FLAGS_EXTENDED
 	if (flags & SYSTEM_RESET_AP_WATCHDOG)
 		save_flags |= EC_RESET_FLAG_AP_WATCHDOG;
-#endif
 
 	chip_save_reset_flags(save_flags);
 
-	if (flags & SYSTEM_RESET_HARD) {
-#ifdef CONFIG_SOFTWARE_PANIC
-		uint32_t reason, info;
-		uint8_t exception;
+#ifdef CONFIG_ARMV7M_CACHE
+	/*
+	 * Disable caches (D-cache is also flushed and invalidated)
+	 * so changes that lives in cache are saved in memory now.
+	 * Any subsequent writes will be done immediately.
+	 */
+	cpu_disable_caches();
+#endif
 
+	if (flags & SYSTEM_RESET_HARD) {
 		/* Panic data will be wiped by hard reset, so save it */
-		panic_get_reason(&reason, &info, &exception);
-		/* 16 bits stored - upper 16 bits of reason / info are lost */
-		bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_REASON, reason);
-		bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_INFO, info);
-		bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_EXCEPTION, exception);
-#endif
+		uint32_t reason, info;
+		uint8_t exception, panic_flags;
+		struct panic_data *pdata = panic_get_data();
+
+		if (pdata) {
+			panic_flags = pdata->flags;
+			panic_get_reason(&reason, &info, &exception);
+			/*
+			 * 16 bits stored - upper 16 bits of reason / info
+			 * are lost.
+			 */
+			bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_REASON, reason);
+			bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_INFO, info);
+			bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_EXCEPTION,
+				      exception);
+			bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_FLAGS,
+				      panic_flags);
+		}
 
-#ifdef CHIP_FAMILY_STM32L
+#if defined(CHIP_FAMILY_STM32L) || defined(CHIP_FAMILY_STM32L4)
 		/*
 		 * Ask the flash module to reboot, so that we reload the
 		 * option bytes.
 		 */
-		flash_physical_force_reload();
+		crec_flash_physical_force_reload();
 
 		/* Fall through to watchdog if that fails */
 #endif
@@ -396,7 +455,7 @@ void system_reset(int flags)
 		 * use this for hard reset.
 		 */
 		STM32_FLASH_CR |= FLASH_CR_OBL_LAUNCH;
-#elif defined(CHIP_FAMILY_STM32L4)
+#elif defined(CHIP_FAMILY_STM32G4)
 		STM32_FLASH_KEYR = FLASH_KEYR_KEY1;
 		STM32_FLASH_KEYR = FLASH_KEYR_KEY2;
 		STM32_FLASH_OPTKEYR = FLASH_OPTKEYR_KEY1;
@@ -424,6 +483,23 @@ void system_reset(int flags)
 		 *    (IWDG_KR = 0x0000 AAAA)
 		 */
 
+		/*
+		 * RM0433 Rev 7
+		 * Section 45.4.4 Page 1920
+		 * https://www.st.com/resource/en/reference_manual/dm00314099.pdf
+		 * If several reload, prescaler, or window values are used by
+		 * the application, it is mandatory to wait until RVU bit is
+		 * reset before changing the reload value, to wait until PVU bit
+		 * is reset before changing the prescaler value, and to wait
+		 * until WVU bit is reset before changing the window value.
+		 *
+		 * Here we should wait to finish previous IWDG_RLR register
+		 * update (see watchdog_init()) before starting next update,
+		 * otherwise new IWDG_RLR value will be lost.
+		 */
+		while (STM32_IWDG_SR & STM32_IWDG_SR_RVU)
+			;
+
 		/*
 		 * Enable IWDG, which shouldn't be necessary since the IWDG
 		 * only needs to be started once, but STM32F412 hangs unless
@@ -436,9 +512,11 @@ void system_reset(int flags)
 		/* Ask the watchdog to trigger a hard reboot */
 		STM32_IWDG_KR = STM32_IWDG_KR_UNLOCK;
 		STM32_IWDG_RLR = 0x1;
-		/* Wait for value to be reloaded. */
+		/* Wait for value to be updated. */
 		while (STM32_IWDG_SR & STM32_IWDG_SR_RVU)
 			;
+
+		/* Reload IWDG counter, it also locks registers */
 		STM32_IWDG_KR = STM32_IWDG_KR_RELOAD;
 #endif
 		/* wait for the chip to reboot */
@@ -472,9 +550,10 @@ int system_set_scratchpad(uint32_t value)
 	return bkpdata_write(BKPDATA_INDEX_SCRATCHPAD, (uint16_t)value);
 }
 
-uint32_t system_get_scratchpad(void)
+int system_get_scratchpad(uint32_t *value)
 {
-	return (uint32_t)bkpdata_read(BKPDATA_INDEX_SCRATCHPAD);
+	*value = (uint32_t)bkpdata_read(BKPDATA_INDEX_SCRATCHPAD);
+	return EC_SUCCESS;
 }
 
 const char *system_get_chip_vendor(void)
@@ -547,16 +626,19 @@ int system_is_reboot_warm(void)
 #elif defined(CHIP_FAMILY_STM32L)
 	return ((STM32_RCC_AHBENR & 0x3f) == 0x3f);
 #elif defined(CHIP_FAMILY_STM32L4)
-	return ((STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_GPIOMASK)
-			== STM32_RCC_AHB2ENR_GPIOMASK);
+	return ((STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_GPIOMASK) ==
+		STM32_RCC_AHB2ENR_GPIOMASK);
+#elif defined(CHIP_FAMILY_STM32L5)
+	return ((STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_GPIOMASK) ==
+		STM32_RCC_AHB2ENR_GPIOMASK);
 #elif defined(CHIP_FAMILY_STM32F4)
-	return ((STM32_RCC_AHB1ENR & STM32_RCC_AHB1ENR_GPIOMASK)
-			== gpio_required_clocks());
+	return ((STM32_RCC_AHB1ENR & STM32_RCC_AHB1ENR_GPIOMASK) ==
+		gpio_required_clocks());
 #elif defined(CHIP_FAMILY_STM32G4)
-	return ((STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_GPIOMASK)
-			== gpio_required_clocks());
+	return ((STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_GPIOMASK) ==
+		gpio_required_clocks());
 #elif defined(CHIP_FAMILY_STM32H7)
-	return ((STM32_RCC_AHB4ENR & STM32_RCC_AHB4ENR_GPIOMASK)
-			== STM32_RCC_AHB4ENR_GPIOMASK);
+	return ((STM32_RCC_AHB4ENR & STM32_RCC_AHB4ENR_GPIOMASK) ==
+		STM32_RCC_AHB4ENR_GPIOMASK);
 #endif
 }
diff --git a/chip/stm32/trng.c b/chip/stm32/trng.c
index 48d5335c53..63641741d3 100644
--- a/chip/stm32/trng.c
+++ b/chip/stm32/trng.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,13 +9,14 @@
 #include "console.h"
 #include "host_command.h"
 #include "panic.h"
+#include "printf.h"
 #include "registers.h"
 #include "system.h"
 #include "task.h"
 #include "trng.h"
 #include "util.h"
 
-uint32_t rand(void)
+uint32_t trng_rand(void)
 {
 	int tries = 300;
 	/* Wait for a valid random number */
@@ -28,26 +29,7 @@ uint32_t rand(void)
 	return STM32_RNG_DR;
 }
 
-test_mockable void rand_bytes(void *buffer, size_t len)
-{
-	while (len) {
-		uint32_t number = rand();
-		size_t cnt = 4;
-		/* deal with the lack of alignment guarantee in the API */
-		uintptr_t align = (uintptr_t)buffer & 3;
-
-		if (len < 4 || align) {
-			cnt = MIN(4 - align, len);
-			memcpy(buffer, &number, cnt);
-		} else {
-			*(uint32_t *)buffer = number;
-		}
-		len -= cnt;
-		buffer += cnt;
-	}
-}
-
-test_mockable void init_trng(void)
+test_mockable void trng_init(void)
 {
 #ifdef CHIP_FAMILY_STM32L4
 	/* Enable the 48Mhz internal RC oscillator */
@@ -57,8 +39,8 @@ test_mockable void init_trng(void)
 		;
 
 	/* Clock the TRNG using the HSI48 */
-	STM32_RCC_CCIPR = (STM32_RCC_CCIPR & ~STM32_RCC_CCIPR_CLK48SEL_MASK)
-			| (0 << STM32_RCC_CCIPR_CLK48SEL_SHIFT);
+	STM32_RCC_CCIPR = (STM32_RCC_CCIPR & ~STM32_RCC_CCIPR_CLK48SEL_MASK) |
+			  (0 << STM32_RCC_CCIPR_CLK48SEL_SHIFT);
 #elif defined(CHIP_FAMILY_STM32H7)
 	/* Enable the 48Mhz internal RC oscillator */
 	STM32_RCC_CR |= STM32_RCC_CR_HSI48ON;
@@ -68,8 +50,8 @@ test_mockable void init_trng(void)
 
 	/* Clock the TRNG using the HSI48 */
 	STM32_RCC_D2CCIP2R =
-		(STM32_RCC_D2CCIP2R & ~STM32_RCC_D2CCIP2_RNGSEL_MASK)
-			| STM32_RCC_D2CCIP2_RNGSEL_HSI48;
+		(STM32_RCC_D2CCIP2R & ~STM32_RCC_D2CCIP2_RNGSEL_MASK) |
+		STM32_RCC_D2CCIP2_RNGSEL_HSI48;
 #elif defined(CHIP_FAMILY_STM32F4)
 	/*
 	 * The RNG clock is the same as the SDIO/USB OTG clock, already set at
@@ -84,7 +66,7 @@ test_mockable void init_trng(void)
 	STM32_RNG_CR |= STM32_RNG_CR_RNGEN;
 }
 
-test_mockable void exit_trng(void)
+test_mockable void trng_exit(void)
 {
 	STM32_RNG_CR &= ~STM32_RNG_CR_RNGEN;
 	STM32_RCC_AHB2ENR &= ~STM32_RCC_AHB2ENR_RNGEN;
@@ -96,50 +78,3 @@ test_mockable void exit_trng(void)
 	/* Nothing to do */
 #endif
 }
-
-#if defined(CONFIG_CMD_RAND)
-/*
- * We want to avoid accidentally exposing debug commands in RO since we can't
- * update RO once in production.
- */
-#if defined(SECTION_IS_RW)
-static int command_rand(int argc, char **argv)
-{
-	uint8_t data[32];
-
-	init_trng();
-	rand_bytes(data, sizeof(data));
-	exit_trng();
-
-	ccprintf("rand %ph\n", HEX_BUF(data, sizeof(data)));
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(rand, command_rand,
-			NULL, "Output random bytes to console.");
-
-static enum ec_status host_command_rand(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_rand_num *p = args->params;
-	struct ec_response_rand_num *r = args->response;
-	uint16_t num_rand_bytes = p->num_rand_bytes;
-
-	if (system_is_locked())
-		return EC_RES_ACCESS_DENIED;
-
-	if (num_rand_bytes > args->response_max)
-		return EC_RES_OVERFLOW;
-
-	init_trng();
-	rand_bytes(r->rand, num_rand_bytes);
-	exit_trng();
-
-	args->response_size = num_rand_bytes;
-
-	return EC_SUCCESS;
-}
-
-DECLARE_HOST_COMMAND(EC_CMD_RAND_NUM, host_command_rand,
-		     EC_VER_MASK(EC_VER_RAND_NUM));
-#endif /* SECTION_IS_RW */
-#endif /* CONFIG_CMD_RAND */
diff --git a/chip/stm32/uart.c b/chip/stm32/uart.c
index 39727d71f1..916cb2257a 100644
--- a/chip/stm32/uart.c
+++ b/chip/stm32/uart.c
@@ -1,24 +1,24 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* USART driver for Chrome EC */
 
-#include "common.h"
 #include "clock.h"
+#include "common.h"
 #include "dma.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "registers.h"
+#include "stm32-dma.h"
 #include "system.h"
 #include "task.h"
 #include "uart.h"
 #include "util.h"
-#include "stm32-dma.h"
 
 /* Console USART index */
-#define UARTN      CONFIG_UART_CONSOLE
+#define UARTN CONFIG_UART_CONSOLE
 #define UARTN_BASE STM32_USART_BASE(CONFIG_UART_CONSOLE)
 
 #ifdef CONFIG_UART_TX_DMA
@@ -33,7 +33,7 @@ static const struct dma_option dma_tx_option = {
 	CONFIG_UART_TX_DMA_CH, (void *)&STM32_USART_TDR(UARTN_BASE),
 	STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
 #ifdef CHIP_FAMILY_STM32F4
-	| STM32_DMA_CCR_CHANNEL(CONFIG_UART_TX_REQ_CH)
+		| STM32_DMA_CCR_CHANNEL(CONFIG_UART_TX_REQ_CH)
 #endif
 };
 
@@ -51,16 +51,16 @@ static const struct dma_option dma_rx_option = {
 	CONFIG_UART_RX_DMA_CH, (void *)&STM32_USART_RDR(UARTN_BASE),
 	STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
 #ifdef CHIP_FAMILY_STM32F4
-	STM32_DMA_CCR_CHANNEL(CONFIG_UART_RX_REQ_CH) |
+		STM32_DMA_CCR_CHANNEL(CONFIG_UART_RX_REQ_CH) |
 #endif
-	STM32_DMA_CCR_CIRC
+		STM32_DMA_CCR_CIRC
 };
 
-static int dma_rx_len;   /* Size of receive DMA circular buffer */
+static int dma_rx_len; /* Size of receive DMA circular buffer */
 #endif
 
-static int init_done;    /* Initialization done? */
-static int should_stop;  /* Last TX control action */
+static int init_done; /* Initialization done? */
+static int should_stop; /* Last TX control action */
 
 int uart_init_done(void)
 {
@@ -161,7 +161,7 @@ int uart_read_char(void)
 }
 
 /* Interrupt handler for console USART */
-void uart_interrupt(void)
+static void uart_interrupt(void)
 {
 #ifndef CONFIG_UART_TX_DMA
 	/*
@@ -176,7 +176,14 @@ void uart_interrupt(void)
 #if defined(CHIP_FAMILY_STM32F4)
 		STM32_USART_SR(UARTN_BASE) &= ~STM32_USART_SR_TC;
 #else
-		STM32_USART_ICR(UARTN_BASE) |= STM32_USART_SR_TC;
+		/*
+		 * ST reference code does blind write to this register, as is
+		 * usual with the "write 1 to clear" convention, despite the
+		 * datasheet listing the bits as "keep at reset value", (which
+		 * we assume is due to copying from the description of
+		 * reserved bits in read/write registers.)
+		 */
+		STM32_USART_ICR(UARTN_BASE) = STM32_USART_SR_TC;
 #endif
 		if (!(STM32_USART_SR(UARTN_BASE) & ~STM32_USART_SR_TC))
 			return;
@@ -234,18 +241,21 @@ static void uart_freq_change(void)
 	freq = 8000000;
 #elif defined(CHIP_FAMILY_STM32H7)
 	freq = 64000000; /* from 64 Mhz HSI */
+#elif defined(CHIP_FAMILY_STM32L4)
+	/* UART clocked from HSI 16 */
+	freq = 16000000;
 #else
 	/* UART clocked from the main clock */
 	freq = clock_get_freq();
 #endif
 
-#if (UARTN == 9)	/* LPUART */
+#if (UARTN == 9) /* LPUART */
 	div = DIV_ROUND_NEAREST(freq, CONFIG_UART_BAUD_RATE) * 256;
 #else
 	div = DIV_ROUND_NEAREST(freq, CONFIG_UART_BAUD_RATE);
 #endif
 
-#if defined(CHIP_FAMILY_STM32L) || defined(CHIP_FAMILY_STM32F0) || \
+#if defined(CHIP_FAMILY_STM32L) || defined(CHIP_FAMILY_STM32F0) ||      \
 	defined(CHIP_FAMILY_STM32F3) || defined(CHIP_FAMILY_STM32L4) || \
 	defined(CHIP_FAMILY_STM32F4) || defined(CHIP_FAMILY_STM32G4)
 	if (div / 16 > 0) {
@@ -267,7 +277,6 @@ static void uart_freq_change(void)
 	/* STM32F only supports x16 oversampling */
 	STM32_USART_BRR(UARTN_BASE) = div;
 #endif
-
 }
 DECLARE_HOOK(HOOK_FREQ_CHANGE, uart_freq_change, HOOK_PRIO_DEFAULT);
 
@@ -276,7 +285,7 @@ void uart_init(void)
 	/* Select clock source */
 #if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3)
 #if (UARTN == 1)
-	STM32_RCC_CFGR3 |= 0x0003;   /* USART1 clock source from HSI(8MHz) */
+	STM32_RCC_CFGR3 |= 0x0003; /* USART1 clock source from HSI(8MHz) */
 #elif (UARTN == 2)
 	STM32_RCC_CFGR3 |= 0x030000; /* USART2 clock source from HSI(8MHz) */
 #endif /* UARTN */
@@ -289,17 +298,29 @@ void uart_init(void)
 #elif defined(CHIP_FAMILY_STM32L4) || defined(CHIP_FAMILY_STM32G4)
 	/* USART1 clock source from SYSCLK */
 	STM32_RCC_CCIPR &= ~STM32_RCC_CCIPR_USART1SEL_MASK;
+#ifdef CHIP_FAMILY_STM32L4
+	/* For STM32L4, use HSI for UART, to wake up from low power mode */
 	STM32_RCC_CCIPR |=
-		(STM32_RCC_CCIPR_UART_SYSCLK << STM32_RCC_CCIPR_USART1SEL_SHIFT);
+		(STM32_RCC_CCIPR_UART_HSI16 << STM32_RCC_CCIPR_USART1SEL_SHIFT);
+#else
+	STM32_RCC_CCIPR |= (STM32_RCC_CCIPR_UART_SYSCLK
+			    << STM32_RCC_CCIPR_USART1SEL_SHIFT);
+#endif
 	/* LPUART1 clock source from SYSCLK */
 	STM32_RCC_CCIPR &= ~STM32_RCC_CCIPR_LPUART1SEL_MASK;
-	STM32_RCC_CCIPR |=
-		(STM32_RCC_CCIPR_UART_SYSCLK << STM32_RCC_CCIPR_LPUART1SEL_SHIFT);
+	STM32_RCC_CCIPR |= (STM32_RCC_CCIPR_UART_SYSCLK
+			    << STM32_RCC_CCIPR_LPUART1SEL_SHIFT);
 #endif /* CHIP_FAMILY_STM32F0 || CHIP_FAMILY_STM32F3 */
 
 	/* Enable USART clock */
 #if (UARTN == 1)
 	STM32_RCC_APB2ENR |= STM32_RCC_PB2_USART1;
+#ifdef CHIP_FAMILY_STM32L4
+#if defined(CONFIG_UART_RX_DMA) || defined(CONFIG_UART_TX_DMA)
+	STM32_RCC_AHB1ENR |= STM32_RCC_HB1_DMA1;
+	STM32_RCC_AHB1ENR |= STM32_RCC_HB1_DMA2;
+#endif
+#endif
 #elif (UARTN == 6)
 	STM32_RCC_APB2ENR |= STM32_RCC_PB2_USART6;
 #elif (UARTN == 9)
@@ -317,8 +338,8 @@ void uart_init(void)
 	/* Configure GPIOs */
 	gpio_config_module(MODULE_UART, 1);
 
-#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) \
-|| defined(CHIP_FAMILY_STM32H7)
+#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \
+	defined(CHIP_FAMILY_STM32H7) || defined(CHIP_FAMILY_STM32L4)
 	/*
 	 * Wake up on start bit detection. WUS can only be written when UE=0,
 	 * so clear UE first.
@@ -330,15 +351,19 @@ void uart_init(void)
 	 * and we don't want to clear an extra flag in the interrupt
 	 */
 	STM32_USART_CR3(UARTN_BASE) |= STM32_USART_CR3_WUS_START_BIT |
-	                               STM32_USART_CR3_OVRDIS;
+				       STM32_USART_CR3_OVRDIS;
 #endif
 
 	/*
 	 * UART enabled, 8 Data bits, oversampling x16, no parity,
 	 * TX and RX enabled.
 	 */
-	STM32_USART_CR1(UARTN_BASE) =
-		STM32_USART_CR1_UE | STM32_USART_CR1_TE | STM32_USART_CR1_RE;
+#ifdef CHIP_FAMILY_STM32L4
+	STM32_USART_CR1(UARTN_BASE) = STM32_USART_CR1_TE | STM32_USART_CR1_RE;
+#else
+	STM32_USART_CR1(UARTN_BASE) = STM32_USART_CR1_UE | STM32_USART_CR1_TE |
+				      STM32_USART_CR1_RE;
+#endif
 
 	/* 1 stop bit, no fancy stuff */
 	STM32_USART_CR2(UARTN_BASE) = 0x0000;
@@ -375,6 +400,10 @@ void uart_init(void)
 	/* Enable interrupts */
 	task_enable_irq(STM32_IRQ_USART(UARTN));
 
+#ifdef CHIP_FAMILY_STM32L4
+	STM32_USART_CR1(UARTN_BASE) |= STM32_USART_CR1_UE;
+#endif
+
 	init_done = 1;
 }
 
diff --git a/chip/stm32/ucpd-stm32gx.c b/chip/stm32/ucpd-stm32gx.c
index 1355d9f042..424792c5d0 100644
--- a/chip/stm32/ucpd-stm32gx.c
+++ b/chip/stm32/ucpd-stm32gx.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,46 +7,348 @@
 
 #include "clock.h"
 #include "common.h"
+#include "console.h"
+#include "driver/tcpm/tcpm.h"
 #include "gpio.h"
 #include "hooks.h"
+#include "hwtimer.h"
 #include "registers.h"
 #include "task.h"
+#include "timer.h"
 #include "ucpd-stm32gx.h"
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+#define USB_VID_STM32 0x0483
 
 /*
- * UCPD is fed directly from HSI which is @ 16MHz. The ucpd_clk goes to
- * a prescaler who's output feeds the 'half-bit' divider which is used
- * to generate clock for delay counters and BMC Rx/Tx blocks. The rx is
- * designed to work in freq ranges of 6 <--> 18 MHz, however recommended
- * range is 9 <--> 18 MHz.
- *
- *          ------- @ 16 MHz ---------   @ ~600 kHz   -------------
- * HSI ---->| /psc |-------->| /hbit |--------------->| trans_cnt |
- *          -------          ---------    |           -------------
- *                                        |           -------------
- *                                        |---------->| ifrgap_cnt|
- *                                                    -------------
- * Requirements:
- *   1. hbit_clk ~= 600 kHz: 16 MHz / 600 kHz = 26.67
- *   2. tTransitionWindow - 12 to 20 uSec
- *   3. tInterframGap - uSec
- *
- * hbit_clk = HSI_clk / 26 = 615,385 kHz = 1.625 uSec period
- * tTransitionWindow = 1.625 uS * 8 = 13 uS
- * tInterFrameGap = 1.625 uS * 17 = 27.625 uS
+ * USB PD message buffer length. Absent extended messages, the longest PD
+ * message will be 7 objects (4 bytes each) plus a 2 byte header. TCPMv2
+ * suports extended messages via chunking so the data buffer length is
+ * set assumign that extended messages are chunked.
  */
-#define UCPD_PSC_DIV 1
-#define UCPD_HBIT_DIV 26
-#define UCPD_TRANSWIN_HBIT_CNT 8
-#define UCPD_IFRGAP_HBIT_CNT 17
+#define UCPD_BUF_LEN 30
+
+#define UCPD_IMR_RX_INT_MASK                                   \
+	(STM32_UCPD_IMR_RXNEIE | STM32_UCPD_IMR_RXORDDETIE |   \
+	 STM32_UCPD_IMR_RXHRSTDETIE | STM32_UCPD_IMR_RXOVRIE | \
+	 STM32_UCPD_IMR_RXMSGENDIE)
+
+#define UCPD_IMR_TX_INT_MASK                                      \
+	(STM32_UCPD_IMR_TXISIE | STM32_UCPD_IMR_TXMSGDISCIE |     \
+	 STM32_UCPD_IMR_TXMSGSENTIE | STM32_UCPD_IMR_TXMSGABTIE | \
+	 STM32_UCPD_IMR_TXUNDIE)
+
+#define UCPD_ICR_TX_INT_MASK                                       \
+	(STM32_UCPD_ICR_TXMSGDISCCF | STM32_UCPD_ICR_TXMSGSENTCF | \
+	 STM32_UCPD_ICR_TXMSGABTCF | STM32_UCPD_ICR_TXUNDCF)
 
 #define UCPD_ANASUB_TO_RP(r) ((r - 1) & 0x3)
 #define UCPD_RP_TO_ANASUB(r) ((r + 1) & 0x3)
 
+struct msg_header_info {
+	enum pd_power_role pr;
+	enum pd_data_role dr;
+};
+static struct msg_header_info msg_header;
+
+/* States for managing tx messages in ucpd task */
+enum ucpd_state {
+	STATE_IDLE,
+	STATE_ACTIVE_TCPM,
+	STATE_ACTIVE_CRC,
+	STATE_HARD_RESET,
+	STATE_WAIT_CRC_ACK,
+};
+
+/* Events for pd_interrupt_handler_task */
+#define UCPD_EVT_GOOD_CRC_REQ BIT(0)
+#define UCPD_EVT_TCPM_MSG_REQ BIT(1)
+#define UCPD_EVT_HR_REQ BIT(2)
+#define UCPD_EVT_TX_MSG_FAIL BIT(3)
+#define UCPD_EVT_TX_MSG_DISC BIT(4)
+#define UCPD_EVT_TX_MSG_SUCCESS BIT(5)
+#define UCPD_EVT_HR_DONE BIT(6)
+#define UCPD_EVT_HR_FAIL BIT(7)
+#define UCPD_EVT_RX_GOOD_CRC BIT(8)
+#define UCPD_EVT_RX_MSG BIT(9)
+
+#define UCPD_T_RECEIVE_US (1 * MSEC)
+
+#define UCPD_N_RETRY_COUNT_REV20 3
+#define UCPD_N_RETRY_COUNT_REV30 2
+
+/*
+ * Tx messages are iniated either by TCPM/PRL layer or from ucpd when a GoodCRC
+ * ack message needs to be sent.
+ */
+enum ucpd_tx_msg {
+	TX_MSG_NONE = -1,
+	TX_MSG_TCPM = 0,
+	TX_MSG_GOOD_CRC = 1,
+	TX_MSG_TOTAL = 2,
+};
+
+#define MSG_TCPM_MASK BIT(TX_MSG_TCPM)
+#define MSG_GOOD_CRC_MASK BIT(TX_MSG_GOOD_CRC)
+
+union buffer {
+	uint16_t header;
+	uint8_t msg[UCPD_BUF_LEN];
+};
+
+struct ucpd_tx_desc {
+	enum tcpci_msg_type type;
+	int msg_len;
+	int msg_index;
+	union buffer data;
+};
+
+/* Track VCONN on/off state */
+static int ucpd_vconn_enable;
+
+/* Tx message variables */
+struct ucpd_tx_desc ucpd_tx_buffers[TX_MSG_TOTAL];
+struct ucpd_tx_desc *ucpd_tx_active_buffer;
+static int ucpd_tx_request;
+static int ucpd_timeout_us;
+static enum ucpd_state ucpd_tx_state;
+static int msg_id_match;
+static int tx_retry_count;
+static int tx_retry_max;
+
+static int ucpd_txorderset[] = {
+	TX_ORDERSET_SOP,
+	TX_ORDERSET_SOP_PRIME,
+	TX_ORDERSET_SOP_PRIME_PRIME,
+	TX_ORDERSET_SOP_PRIME_DEBUG,
+	TX_ORDERSET_SOP_PRIME_PRIME_DEBUG,
+	TX_ORDERSET_HARD_RESET,
+	TX_ORDERSET_CABLE_RESET,
+};
+
+/* PD Rx variables */
+static int ucpd_rx_byte_count;
+static uint8_t ucpd_rx_buffer[UCPD_BUF_LEN];
+static int ucpd_crc_id;
+static bool ucpd_rx_sop_prime_enabled;
+static int ucpd_rx_msg_active;
+static bool ucpd_rx_bist_mode;
+
+#ifdef CONFIG_STM32G4_UCPD_DEBUG
+/* Defines and macros for ucpd state logging */
+#define TX_STATE_LOG_LEN BIT(5)
+#define TX_STATE_LOG_MASK (TX_STATE_LOG_LEN - 1)
+
+struct ucpd_tx_state {
+	uint32_t ts;
+	int tx_request;
+	int timeout_us;
+	enum ucpd_state enter_state;
+	enum ucpd_state exit_state;
+	uint32_t evt;
+};
+
+struct ucpd_tx_state ucpd_tx_statelog[TX_STATE_LOG_LEN];
+int ucpd_tx_state_log_idx;
+int ucpd_tx_state_log_freeze;
+
+static char ucpd_names[][12] = {
+	"TX_IDLE", "ACT_TCPM", "ACT_CRC", "HARD_RST", "WAIT_CRC",
+};
+/* Defines and macros used for ucpd pd message logging */
+#define MSG_LOG_LEN 64
+#define MSG_BUF_LEN 10
+
+struct msg_info {
+	uint8_t dir;
+	uint8_t comp;
+	uint8_t crc;
+	uint16_t header;
+	uint32_t ts;
+	uint8_t buf[MSG_BUF_LEN];
+};
+static int msg_log_cnt;
+static int msg_log_idx;
+static struct msg_info msg_log[MSG_LOG_LEN];
+
+#define UCPD_CC_STRING_LEN 5
+
+static char ccx[4][UCPD_CC_STRING_LEN] = {
+	"Ra",
+	"Rp",
+	"Rd",
+	"Open",
+};
+static char rp_string[][8] = {
+	"Rp_usb",
+	"Rp_1.5",
+	"Rp_3.0",
+	"Open",
+};
+static int ucpd_sr_cc_event;
+static int ucpd_cc_set_save;
+static int ucpd_cc_change_log;
+
+static int ucpd_is_cc_pull_active(int port, enum usbpd_cc_pin cc_line);
+
+static void ucpd_log_add_msg(uint16_t header, int dir)
+{
+	uint32_t ts = __hw_clock_source_read();
+	int idx = msg_log_idx;
+	uint8_t *buf = dir ? ucpd_rx_buffer : ucpd_tx_active_buffer->data.msg;
+
+	/*
+	 * Add a msg entry in the history log. The log is currently designed to
+	 * be from reset until MSG_LOG_LEN messages have been added.
+	 * ts -> lower 32 bits of 1 uSec running clock
+	 * dir -> 0 = tx message, 1 = rx message
+	 * comp -> ucpd transmit success
+	 * crc -> GoodCrc received following tx message
+	 */
+	if (msg_log_cnt++ < MSG_LOG_LEN) {
+		int msg_bytes =
+			MIN((PD_HEADER_CNT(header) << 2) + 2, MSG_BUF_LEN);
+
+		msg_log[idx].header = header;
+		msg_log[idx].ts = ts;
+		msg_log[idx].dir = dir;
+		msg_log[idx].comp = 0;
+		msg_log[idx].crc = 0;
+		msg_log_idx++;
+		memcpy(msg_log[idx].buf, buf, msg_bytes);
+	}
+}
+
+static void ucpd_log_mark_tx_comp(void)
+{
+	/*
+	 * This msg logging utility function is used to mark when a message was
+	 * successfully transmitted when transmit interrupt occurs and the tx
+	 * message sent status was set. Because the transmit message is added
+	 * before it's sent by ucpd, the index has to back up one to mark the
+	 * correct log entry.
+	 */
+	if (msg_log_cnt < MSG_LOG_LEN) {
+		if (msg_log_idx > 0)
+			msg_log[msg_log_idx - 1].comp = 1;
+	}
+}
+
+static void ucpd_log_mark_crc(void)
+{
+	/*
+	 * This msg logging utility function is used to mark when a GoodCRC
+	 * message is received following a tx message. This status is displayed
+	 * in column s2. Because this indication follows both transmit message
+	 * and GoodCRC rx, the index must be back up 2 rows to mark the correct
+	 * tx message entry.
+	 */
+	if (msg_log_cnt < MSG_LOG_LEN) {
+		if (msg_log_idx >= 2)
+			msg_log[msg_log_idx - 2].crc = 1;
+	}
+}
+
+static void ucpd_cc_status(int port)
+{
+	int rc = stm32gx_ucpd_get_role_control(port);
+	int cc1_pull, cc2_pull;
+	enum tcpc_cc_voltage_status v_cc1, v_cc2;
+	int rv;
+	char *rp_name;
+
+	cc1_pull = rc & 0x3;
+	cc2_pull = (rc >> 2) & 0x3;
+
+	/*
+	 * This function is used to display CC settings, including pull type,
+	 * and if Rp, what the Rp value is set to. In addition, the current
+	 * values of CC voltage detector, polarity, and PD enable status are
+	 * displayed.
+	 */
+	rv = stm32gx_ucpd_get_cc(port, &v_cc1, &v_cc2);
+	rp_name = rp_string[(rc >> 4) % 0x3];
+	ccprintf("\tcc1\t = %s\n\tcc2\t = %s\n\tRp\t = %s\n", ccx[cc1_pull],
+		 ccx[cc2_pull], rp_name);
+	if (!rv)
+		ccprintf("\tcc1_v\t = %d\n\tcc2_v\t = %d\n", v_cc1, v_cc2);
+}
+
+void ucpd_cc_detect_notify_enable(int enable)
+{
+	/*
+	 * This variable is used to control when a CC detach detector is
+	 * active.
+	 */
+	ucpd_cc_change_log = enable;
+}
+
+static void ucpd_log_invalidate_entry(void)
+{
+	/*
+	 * This is a msg log utility function which is triggered when an
+	 * unexpected detach event is detected.
+	 */
+	if (msg_log_idx < (MSG_LOG_LEN - 1)) {
+		int idx = msg_log_idx;
+
+		msg_log[idx].header = 0xabcd;
+		msg_log[idx].ts = __hw_clock_source_read();
+		msg_log[idx].dir = 0;
+		msg_log[idx].comp = 0;
+		msg_log[idx].crc = 0;
+		msg_log_cnt++;
+		msg_log_idx++;
+	}
+}
+
+/*
+ * This function will mark in the msg log when a detach event occurs. It will
+ * only be active if ucpd_cc_change_log is set which can be controlled via the
+ * ucpd console command.
+ */
+static void ucpd_cc_change_notify(void)
+{
+	if (ucpd_cc_change_log) {
+		uint32_t sr = ucpd_sr_cc_event;
+
+		ucpd_log_invalidate_entry();
+
+		ccprintf("vstate: cc1 = %x, cc2 = %x, Rp = %d\n",
+			 (sr >> STM32_UCPD_SR_VSTATE_CC1_SHIFT) & 0x3,
+			 (sr >> STM32_UCPD_SR_VSTATE_CC2_SHIFT) & 0x3,
+			 (ucpd_cc_set_save >> STM32_UCPD_CR_ANASUBMODE_SHIFT) &
+				 0x3);
+		/* Display CC status on EC console */
+		ucpd_cc_status(0);
+	}
+}
+DECLARE_DEFERRED(ucpd_cc_change_notify);
+#endif /* CONFIG_STM32G4_UCPD_DEBUG */
+
+static int ucpd_msg_is_good_crc(uint16_t header)
+{
+	/*
+	 * Good CRC is a control message (no data objects) with GOOD_CRC message
+	 * type in the header.
+	 */
+	return ((PD_HEADER_CNT(header) == 0) && (PD_HEADER_EXT(header) == 0) &&
+		(PD_HEADER_TYPE(header) == PD_CTRL_GOOD_CRC)) ?
+		       1 :
+		       0;
+}
+
+static void ucpd_hard_reset_rx_log(void)
+{
+	CPRINTS("ucpd: hard reset recieved");
+}
+DECLARE_DEFERRED(ucpd_hard_reset_rx_log);
+
 static void ucpd_port_enable(int port, int enable)
 {
 	if (enable)
@@ -57,40 +359,80 @@ static void ucpd_port_enable(int port, int enable)
 
 static int ucpd_is_cc_pull_active(int port, enum usbpd_cc_pin cc_line)
 {
-	int cc_enable = STM32_UCPD_CR(port) & STM32_UCPD_CR_CCENABLE_MASK >>
-		STM32_UCPD_CR_CCENABLE_SHIFT;
+	int cc_enable = (STM32_UCPD_CR(port) & STM32_UCPD_CR_CCENABLE_MASK) >>
+			STM32_UCPD_CR_CCENABLE_SHIFT;
 
 	return ((cc_enable >> cc_line) & 0x1);
 }
 
-void stm32gx_ucpd1_irq(void)
+static void ucpd_tx_data_byte(int port)
 {
-	/* STM32_IRQ_UCPD indicates this is from UCPD1, so port = 0 */
-	int port = 0;
-	uint32_t sr = STM32_UCPD_SR(port);
+	int index = ucpd_tx_active_buffer->msg_index++;
 
-	if (sr & (STM32_UCPD_SR_TYPECEVT1 | STM32_UCPD_SR_TYPECEVT2)) {
-		task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_CC, 0);
+	STM32_UCPD_TXDR(port) = ucpd_tx_active_buffer->data.msg[index];
+}
+
+static void ucpd_rx_data_byte(int port)
+{
+	if (ucpd_rx_byte_count < UCPD_BUF_LEN)
+		ucpd_rx_buffer[ucpd_rx_byte_count++] = STM32_UCPD_RXDR(port);
+}
+
+static void ucpd_tx_interrupts_enable(int port, int enable)
+{
+	if (enable) {
+		STM32_UCPD_ICR(port) = UCPD_ICR_TX_INT_MASK;
+		STM32_UCPD_IMR(port) |= UCPD_IMR_TX_INT_MASK;
+	} else {
+		STM32_UCPD_IMR(port) &= ~UCPD_IMR_TX_INT_MASK;
 	}
-	/* Clear interrupts now that PD events have been set */
-	STM32_UCPD_ICR(port) = sr;
 }
-DECLARE_IRQ(STM32_IRQ_UCPD1, stm32gx_ucpd1_irq, 1);
+
+static void ucpd_rx_enque_error(void)
+{
+	CPRINTS("ucpd: TCPM Enque Error!!");
+}
+DECLARE_DEFERRED(ucpd_rx_enque_error);
+
+static void stm32gx_ucpd_state_init(int port)
+{
+	/* Init variables used to manage tx process */
+	ucpd_tx_request = 0;
+	tx_retry_count = 0;
+	ucpd_tx_state = STATE_IDLE;
+	ucpd_timeout_us = -1;
+
+	/* Init variables used to manage rx */
+	ucpd_rx_sop_prime_enabled = 0;
+	ucpd_rx_msg_active = 0;
+	ucpd_rx_bist_mode = 0;
+
+	/* Vconn tracking variable */
+	ucpd_vconn_enable = 0;
+}
 
 int stm32gx_ucpd_init(int port)
 {
 	uint32_t cfgr1_reg;
+	uint32_t moder_reg;
+
+	/* Disable UCPD interrupts */
+	task_disable_irq(STM32_IRQ_UCPD1);
 
 	/*
-	* After exiting reset, stm32gx will have dead battery mode enabled by
-	* default which connects Rd to CC1/CC2. This should be disabled when EC
-	* is powered up.
-	*/
+	 * After exiting reset, stm32gx will have dead battery mode enabled by
+	 * default which connects Rd to CC1/CC2. This should be disabled when EC
+	 * is powered up.
+	 */
 	STM32_PWR_CR3 |= STM32_PWR_CR3_UCPD1_DBDIS;
 
 	/* Ensure that clock to UCPD is enabled */
 	STM32_RCC_APB1ENR2 |= STM32_RCC_APB1ENR2_UPCD1EN;
 
+	/* Make sure CC1/CC2 pins PB4/PB6 are set for analog mode */
+	moder_reg = STM32_GPIO_MODER(GPIO_B);
+	moder_reg |= 0x3300;
+	STM32_GPIO_MODER(GPIO_B) = moder_reg;
 	/*
 	 * CFGR1 must be written when UCPD peripheral is disabled. Note that
 	 * disabling ucpd causes the peripheral to quit any ongoing activity and
@@ -99,19 +441,31 @@ int stm32gx_ucpd_init(int port)
 	ucpd_port_enable(port, 0);
 
 	cfgr1_reg = STM32_UCPD_CFGR1_PSC_CLK_VAL(UCPD_PSC_DIV - 1) |
-		STM32_UCPD_CFGR1_TRANSWIN_VAL(UCPD_TRANSWIN_CNT - 1) |
-		STM32_UCPD_CFGR1_IFRGAP_VAL(UCPD_IFRGAP_CNT - 1) |
-		STM32_UCPD_CFGR1_HBITCLKD_VAL(UCPD_HBIT_DIV - 1);
+		    STM32_UCPD_CFGR1_TRANSWIN_VAL(UCPD_TRANSWIN_CNT - 1) |
+		    STM32_UCPD_CFGR1_IFRGAP_VAL(UCPD_IFRGAP_CNT - 1) |
+		    STM32_UCPD_CFGR1_HBITCLKD_VAL(UCPD_HBIT_DIV - 1);
 	STM32_UCPD_CFGR1(port) = cfgr1_reg;
 
+	/*
+	 * Set RXORDSETEN field to control which types of ordered sets the PD
+	 * receiver must receive.
+	 * SOP, SOP', Hard Reset Det, Cable Reset Det enabled
+	 */
+	STM32_UCPD_CFGR1(port) |= STM32_UCPD_CFGR1_RXORDSETEN_VAL(0x1B);
+
 	/* Enable ucpd  */
 	ucpd_port_enable(port, 1);
 
 	/* Configure CC change interrupts */
 	STM32_UCPD_IMR(port) = STM32_UCPD_IMR_TYPECEVT1IE |
-		STM32_UCPD_IMR_TYPECEVT2IE;
+			       STM32_UCPD_IMR_TYPECEVT2IE;
 	STM32_UCPD_ICR(port) = STM32_UCPD_ICR_TYPECEVT1CF |
-		STM32_UCPD_ICR_TYPECEVT2CF;
+			       STM32_UCPD_ICR_TYPECEVT2CF;
+
+	/* SOP'/SOP'' must be enabled via TCPCI call */
+	ucpd_rx_sop_prime_enabled = false;
+
+	stm32gx_ucpd_state_init(port);
 
 	/* Enable UCPD interrupts */
 	task_enable_irq(STM32_IRQ_UCPD1);
@@ -127,7 +481,7 @@ int stm32gx_ucpd_release(int port)
 }
 
 int stm32gx_ucpd_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2)
+			enum tcpc_cc_voltage_status *cc2)
 {
 	int vstate_cc1;
 	int vstate_cc2;
@@ -141,7 +495,7 @@ int stm32gx_ucpd_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
 	 *
 	 * vstate_cc maps directly to cc_state from tcpci spec when ANAMODE = 1,
 	 * but needs to be modified slightly for case ANAMODE = 0.
-         *
+	 *
 	 * If presenting Rp (source), then need to to a circular shift of
 	 * vstate_ccx value:
 	 *     vstate_cc | cc_state
@@ -156,9 +510,9 @@ int stm32gx_ucpd_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
 	/* Get Rp or Rd active */
 	anamode = !!(STM32_UCPD_CR(port) & STM32_UCPD_CR_ANAMODE);
 	vstate_cc1 = (sr & STM32_UCPD_SR_VSTATE_CC1_MASK) >>
-		STM32_UCPD_SR_VSTATE_CC1_SHIFT;
+		     STM32_UCPD_SR_VSTATE_CC1_SHIFT;
 	vstate_cc2 = (sr & STM32_UCPD_SR_VSTATE_CC2_MASK) >>
-		STM32_UCPD_SR_VSTATE_CC2_SHIFT;
+		     STM32_UCPD_SR_VSTATE_CC2_SHIFT;
 
 	/* Do circular shift if port == source */
 	if (anamode) {
@@ -185,8 +539,9 @@ int stm32gx_ucpd_get_role_control(int port)
 	int cc1;
 	int cc2;
 	int anamode = !!(STM32_UCPD_CR(port) & STM32_UCPD_CR_ANAMODE);
-	int anasubmode = (STM32_UCPD_CR(port) & STM32_UCPD_CR_ANASUBMODE_MASK)
-		>> STM32_UCPD_CR_ANASUBMODE_SHIFT;
+	int anasubmode =
+		(STM32_UCPD_CR(port) & STM32_UCPD_CR_ANASUBMODE_MASK) >>
+		STM32_UCPD_CR_ANASUBMODE_SHIFT;
 
 	/*
 	 * Role control register is defined as:
@@ -216,9 +571,9 @@ int stm32gx_ucpd_get_role_control(int port)
 	 *   Rp  = (ANASUBMODE - 1) & 0x3
 	 */
 	cc1 = ucpd_is_cc_pull_active(port, USBPD_CC_PIN_1) ? anamode + 1 :
-		TYPEC_CC_OPEN;
+							     TYPEC_CC_OPEN;
 	cc2 = ucpd_is_cc_pull_active(port, USBPD_CC_PIN_2) ? anamode + 1 :
-		TYPEC_CC_OPEN;
+							     TYPEC_CC_OPEN;
 	role_control = cc1 | (cc2 << 2);
 	/* Circular shift anasubmode to convert to Rp range */
 	role_control |= (UCPD_ANASUB_TO_RP(anasubmode) << 4);
@@ -226,6 +581,37 @@ int stm32gx_ucpd_get_role_control(int port)
 	return role_control;
 }
 
+static uint32_t ucpd_get_cc_enable_mask(int port)
+{
+	uint32_t mask = STM32_UCPD_CR_CCENABLE_MASK;
+
+	if (ucpd_vconn_enable) {
+		uint32_t cr = STM32_UCPD_CR(port);
+		int pol = !!(cr & STM32_UCPD_CR_PHYCCSEL);
+
+		mask &= ~(1 << (STM32_UCPD_CR_CCENABLE_SHIFT + !pol));
+	}
+
+	return mask;
+}
+
+int stm32gx_ucpd_vconn_disc_rp(int port, int enable)
+{
+	int cr;
+
+	/* Update VCONN on/off status. Do this before getting cc enable mask */
+	ucpd_vconn_enable = enable;
+
+	cr = STM32_UCPD_CR(port);
+	cr &= ~STM32_UCPD_CR_CCENABLE_MASK;
+	cr |= ucpd_get_cc_enable_mask(port);
+
+	/* Apply cc pull resistor change */
+	STM32_UCPD_CR(port) = cr;
+
+	return EC_SUCCESS;
+}
+
 int stm32gx_ucpd_set_cc(int port, int cc_pull, int rp)
 {
 	uint32_t cr = STM32_UCPD_CR(port);
@@ -238,21 +624,25 @@ int stm32gx_ucpd_set_cc(int port, int cc_pull, int rp)
 	cr &= ~STM32_UCPD_CR_ANASUBMODE_MASK;
 	cr |= STM32_UCPD_CR_ANASUBMODE_VAL(UCPD_RP_TO_ANASUB(rp));
 
-	/* Disconnect both pull from both CC lines by default */
+	/* Disconnect both pull from both CC lines for R_open case */
 	cr &= ~STM32_UCPD_CR_CCENABLE_MASK;
 	/* Set ANAMODE if cc_pull is Rd */
 	if (cc_pull == TYPEC_CC_RD) {
 		cr |= STM32_UCPD_CR_ANAMODE | STM32_UCPD_CR_CCENABLE_MASK;
-	/* Clear ANAMODE if cc_pull is Rp */
+		/* Clear ANAMODE if cc_pull is Rp */
 	} else if (cc_pull == TYPEC_CC_RP) {
 		cr &= ~(STM32_UCPD_CR_ANAMODE);
-		cr |= STM32_UCPD_CR_CCENABLE_MASK;
+		cr |= ucpd_get_cc_enable_mask(port);
 	}
 
+#ifdef CONFIG_STM32G4_UCPD_DEBUG
+	if (ucpd_cc_change_log) {
+		CPRINTS("ucpd: set_cc: pull = %d, rp = %d", cc_pull, rp);
+	}
+#endif
 	/* Update pull values */
 	STM32_UCPD_CR(port) = cr;
 
-	/* TODO(b/): Should this return error if cc_pull == Ra */
 	return EC_SUCCESS;
 }
 
@@ -272,6 +662,909 @@ int stm32gx_ucpd_set_polarity(int port, enum tcpc_cc_polarity polarity)
 	else if (polarity == POLARITY_CC2)
 		STM32_UCPD_CR(port) |= STM32_UCPD_CR_PHYCCSEL;
 
+#ifdef CONFIG_STM32G4_UCPD_DEBUG
+	ucpd_cc_set_save = STM32_UCPD_CR(port);
+#endif
+
+	return EC_SUCCESS;
+}
+
+int stm32gx_ucpd_set_rx_enable(int port, int enable)
+{
+	/*
+	 * USB PD receiver enable is controlled by the bit PHYRXEN in
+	 * UCPD_CR. Enable Rx interrupts when RX PD decoder is active.
+	 */
+	if (enable) {
+		STM32_UCPD_ICR(port) = UCPD_IMR_RX_INT_MASK;
+		STM32_UCPD_IMR(port) |= UCPD_IMR_RX_INT_MASK;
+		STM32_UCPD_CR(port) |= STM32_UCPD_CR_PHYRXEN;
+	} else {
+		STM32_UCPD_CR(port) &= ~STM32_UCPD_CR_PHYRXEN;
+		STM32_UCPD_IMR(port) &= ~UCPD_IMR_RX_INT_MASK;
+	}
+
 	return EC_SUCCESS;
 }
 
+int stm32gx_ucpd_set_msg_header(int port, int power_role, int data_role)
+{
+	msg_header.pr = power_role;
+	msg_header.dr = data_role;
+
+	return EC_SUCCESS;
+}
+
+int stm32gx_ucpd_sop_prime_enable(int port, bool enable)
+{
+	/* Update static varialbe used to filter SOP//SOP'' messages */
+	ucpd_rx_sop_prime_enabled = enable;
+
+	return EC_SUCCESS;
+}
+
+int stm32gx_ucpd_get_chip_info(int port, int live,
+			       struct ec_response_pd_chip_info_v1 *chip_info)
+{
+	chip_info->vendor_id = USB_VID_STM32;
+	chip_info->product_id = 0;
+	chip_info->device_id = STM32_DBGMCU_IDCODE & 0xfff;
+	chip_info->fw_version_number = 0xEC;
+
+	return EC_SUCCESS;
+}
+
+static int stm32gx_ucpd_start_transmit(int port, enum ucpd_tx_msg msg_type)
+{
+	enum tcpci_msg_type type;
+
+	/* Select the correct tx desciptor */
+	ucpd_tx_active_buffer = &ucpd_tx_buffers[msg_type];
+	type = ucpd_tx_active_buffer->type;
+
+	if (type == TCPCI_MSG_TX_HARD_RESET) {
+		/*
+		 * From RM0440 45.4.4:
+		 * In order to facilitate generation of a Hard Reset, a special
+		 * code of TXMODE field is used. No other fields need to be
+		 * written. On writing the correct code, the hardware forces
+		 * Hard Reset Tx under the correct (optimal) timings with
+		 * respect to an on-going Tx message, which (if still in
+		 * progress) is cleanly terminated by truncating the current
+		 * sequence and directly appending an EOP K-code sequence. No
+		 * specific interrupt is generated relating to this truncation
+		 * event.
+		 *
+		 * Because Hard Reset can interrupt ongoing Tx operations, it is
+		 * started differently than all other tx messages. Only need to
+		 * enable hard reset interrupts, and then set a bit in the CR
+		 * register to initiate.
+		 */
+		/* Enable interrupt for Hard Reset sent/discarded */
+		STM32_UCPD_ICR(port) = STM32_UCPD_ICR_HRSTDISCCF |
+				       STM32_UCPD_ICR_HRSTSENTCF;
+		STM32_UCPD_IMR(port) |= STM32_UCPD_IMR_HRSTDISCIE |
+					STM32_UCPD_IMR_HRSTSENTIE;
+		/* Initiate Hard Reset */
+		STM32_UCPD_CR(port) |= STM32_UCPD_CR_TXHRST;
+	} else if (type != TCPCI_MSG_INVALID) {
+		int msg_len = 0;
+		int mode;
+
+		/*
+		 * These types are normal transmission, TXMODE = 0. To transmit
+		 * regular message, control or data, requires the following:
+		 *     1. Set TXMODE:
+		 *          Normal -> 0
+		 *          Cable Reset -> 1
+		 *          Bist -> 2
+		 *     2. Set TX_ORDSETR based on message type
+		 *     3. Set TX_PAYSZR which must account for 2 bytes of header
+		 *     4. Configure DMA (optional if DMA is desired)
+		 *     5. Enable transmit interrupts
+		 *     6. Start TX by setting TXSEND in CR
+		 *
+		 */
+
+		/*
+		 * Set tx length parameter (in bytes). Note the count field in
+		 * the header is number of 32 bit objects. Also, the length
+		 * field must account for the 2 header bytes.
+		 */
+		if (type == TCPCI_MSG_TX_BIST_MODE_2) {
+			mode = STM32_UCPD_CR_TXMODE_BIST;
+		} else if (type == TCPCI_MSG_CABLE_RESET) {
+			mode = STM32_UCPD_CR_TXMODE_CBL_RST;
+		} else {
+			mode = STM32_UCPD_CR_TXMODE_DEF;
+			msg_len = ucpd_tx_active_buffer->msg_len;
+		}
+
+		STM32_UCPD_TX_PAYSZR(port) = msg_len;
+
+		/* Set tx mode */
+		STM32_UCPD_CR(port) &= ~STM32_UCPD_CR_TXMODE_MASK;
+		STM32_UCPD_CR(port) |= STM32_UCPD_CR_TXMODE_VAL(mode);
+
+		/* Index into ordset enum for start of packet */
+		if (type <= TCPCI_MSG_CABLE_RESET)
+			STM32_UCPD_TX_ORDSETR(port) = ucpd_txorderset[type];
+
+		/* Reset msg byte index */
+		ucpd_tx_active_buffer->msg_index = 0;
+
+		/* Enable interrupts */
+		ucpd_tx_interrupts_enable(port, 1);
+
+		/* Trigger ucpd peripheral to start pd message transmit */
+		STM32_UCPD_CR(port) |= STM32_UCPD_CR_TXSEND;
+
+#ifdef CONFIG_STM32G4_UCPD_DEBUG
+		ucpd_log_add_msg(ucpd_tx_active_buffer->data.header, 0);
+#endif
+	}
+
+	return EC_SUCCESS;
+}
+
+static void ucpd_set_tx_state(enum ucpd_state state)
+{
+	ucpd_tx_state = state;
+}
+
+#ifdef CONFIG_STM32G4_UCPD_DEBUG
+static void ucpd_task_log(int timeout, enum ucpd_state enter,
+			  enum ucpd_state exit, int req, uint32_t evt)
+{
+	static int same_count = 0;
+	int idx = ucpd_tx_state_log_idx;
+
+	if (ucpd_tx_state_log_freeze)
+		return;
+
+	ucpd_tx_statelog[idx].ts = get_time().le.lo;
+	ucpd_tx_statelog[idx].tx_request = req;
+	ucpd_tx_statelog[idx].timeout_us = timeout;
+	ucpd_tx_statelog[idx].enter_state = enter;
+	ucpd_tx_statelog[idx].exit_state = exit;
+	ucpd_tx_statelog[idx].evt = evt;
+
+	ucpd_tx_state_log_idx = (idx + 1) & TX_STATE_LOG_MASK;
+
+	if (enter == exit) {
+		same_count++;
+	} else {
+		same_count = 0;
+	}
+
+	/*
+	 * Should not have same enter/exit states. If this happens, then freeze
+	 * state log to help in debugging.
+	 */
+	if (same_count > 5)
+		ucpd_tx_state_log_freeze = 1;
+}
+
+static void ucpd_task_log_dump(void)
+{
+	int n;
+	int idx;
+
+	ucpd_tx_state_log_freeze = 1;
+
+	/* current index will be oldest entry in the log */
+	idx = ucpd_tx_state_log_idx;
+
+	ccprintf("\n\t UCDP Task Log\n");
+	for (n = 0; n < TX_STATE_LOG_LEN; n++) {
+		ccprintf("[%d]:\t\%8s\t%8s\t%02x\t%08x\t%09d\t%d\n", n,
+			 ucpd_names[ucpd_tx_statelog[idx].enter_state],
+			 ucpd_names[ucpd_tx_statelog[idx].exit_state],
+			 ucpd_tx_statelog[idx].tx_request,
+			 ucpd_tx_statelog[idx].evt, ucpd_tx_statelog[idx].ts,
+			 ucpd_tx_statelog[idx].timeout_us);
+
+		idx = (idx + 1) & TX_STATE_LOG_MASK;
+		msleep(5);
+	}
+
+	ucpd_tx_state_log_freeze = 0;
+}
+#endif
+
+static void ucpd_manage_tx(int port, int evt)
+{
+	enum ucpd_tx_msg msg_src = TX_MSG_NONE;
+	uint16_t hdr;
+#ifdef CONFIG_STM32G4_UCPD_DEBUG
+	enum ucpd_state enter = ucpd_tx_state;
+	int req = ucpd_tx_request;
+#endif
+
+	if (evt & UCPD_EVT_HR_REQ) {
+		/*
+		 * Hard reset control messages are treated as a priority. The
+		 * control message will already be set up as it comes from the
+		 * PRL layer like any other PD ctrl/data message. So just need
+		 * to indicate the correct message source and set the state to
+		 * hard reset here.
+		 */
+		ucpd_set_tx_state(STATE_HARD_RESET);
+		msg_src = TX_MSG_TCPM;
+		ucpd_tx_request &= ~(1 << msg_src);
+	}
+
+	switch (ucpd_tx_state) {
+	case STATE_IDLE:
+		if (ucpd_tx_request & MSG_GOOD_CRC_MASK) {
+			ucpd_set_tx_state(STATE_ACTIVE_CRC);
+			msg_src = TX_MSG_GOOD_CRC;
+		} else if (ucpd_tx_request & MSG_TCPM_MASK) {
+			if (evt & UCPD_EVT_RX_MSG) {
+				/*
+				 * USB-PD Specification rev 3.0, section 6.10
+				 * On receiving a received message, the protocol
+				 * layer shall discard any pending message.
+				 *
+				 * Since the pending message from the PRL has
+				 * not been sent yet, it needs to be discarded
+				 * based on the received message event.
+				 */
+				pd_transmit_complete(
+					port, TCPC_TX_COMPLETE_DISCARDED);
+				ucpd_tx_request &= ~MSG_TCPM_MASK;
+			} else if (!ucpd_rx_msg_active) {
+				ucpd_set_tx_state(STATE_ACTIVE_TCPM);
+				msg_src = TX_MSG_TCPM;
+				/* Save msgID required for GoodCRC check */
+				hdr = ucpd_tx_buffers[TX_MSG_TCPM].data.header;
+				msg_id_match = PD_HEADER_ID(hdr);
+				tx_retry_max =
+					PD_HEADER_REV(hdr) == PD_REV30 ?
+						UCPD_N_RETRY_COUNT_REV30 :
+						UCPD_N_RETRY_COUNT_REV20;
+			}
+		}
+
+		/* If state is not idle, then start tx message */
+		if (ucpd_tx_state != STATE_IDLE) {
+			ucpd_tx_request &= ~(1 << msg_src);
+			tx_retry_count = 0;
+		}
+		break;
+
+	case STATE_ACTIVE_TCPM:
+		/*
+		 * Check if tx msg has finsihed. For TCPM messages
+		 * transmit is not complete until a GoodCRC message
+		 * matching the msgID just sent is received. But, a tx
+		 * message can fail due to collision or underrun,
+		 * etc. If that failure occurs, dont' wait for GoodCrc
+		 * and just go to failure path.
+		 */
+		if (evt & UCPD_EVT_TX_MSG_SUCCESS) {
+			ucpd_set_tx_state(STATE_WAIT_CRC_ACK);
+			ucpd_timeout_us = UCPD_T_RECEIVE_US;
+		} else if (evt & UCPD_EVT_TX_MSG_DISC ||
+			   evt & UCPD_EVT_TX_MSG_FAIL) {
+			if (tx_retry_count < tx_retry_max) {
+				if (evt & UCPD_EVT_RX_MSG) {
+					/*
+					 * A message was received so there is no
+					 * need to retry this tx message which
+					 * had failed to send previously.
+					 * Likely, due to the wire
+					 * being active from the message that
+					 * was just received.
+					 */
+					ucpd_set_tx_state(STATE_IDLE);
+					pd_transmit_complete(
+						port,
+						TCPC_TX_COMPLETE_DISCARDED);
+					ucpd_set_tx_state(STATE_IDLE);
+				} else {
+					/*
+					 * Tx attempt failed. Remain in this
+					 * state, but trigger new tx attempt.
+					 */
+					msg_src = TX_MSG_TCPM;
+					tx_retry_count++;
+				}
+			} else {
+				enum tcpc_transmit_complete status;
+
+				status = (evt & UCPD_EVT_TX_MSG_FAIL) ?
+						 TCPC_TX_COMPLETE_FAILED :
+						 TCPC_TX_COMPLETE_DISCARDED;
+				ucpd_set_tx_state(STATE_IDLE);
+				pd_transmit_complete(port, status);
+			}
+		}
+		break;
+
+	case STATE_ACTIVE_CRC:
+		if (evt & (UCPD_EVT_TX_MSG_SUCCESS | UCPD_EVT_TX_MSG_FAIL |
+			   UCPD_EVT_TX_MSG_DISC)) {
+			ucpd_set_tx_state(STATE_IDLE);
+			if (evt & UCPD_EVT_TX_MSG_FAIL)
+				CPRINTS("ucpd: Failed to send GoodCRC!");
+			else if (evt & UCPD_EVT_TX_MSG_DISC)
+				CPRINTS("ucpd: GoodCRC message discarded!");
+		}
+		break;
+
+	case STATE_WAIT_CRC_ACK:
+		if (evt & UCPD_EVT_RX_GOOD_CRC && ucpd_crc_id == msg_id_match) {
+			/* GoodCRC with matching ID was received */
+			pd_transmit_complete(port, TCPC_TX_COMPLETE_SUCCESS);
+			ucpd_set_tx_state(STATE_IDLE);
+#ifdef CONFIG_STM32G4_UCPD_DEBUG
+			ucpd_log_mark_crc();
+#endif
+		} else if ((evt & UCPD_EVT_RX_GOOD_CRC) ||
+			   (evt & TASK_EVENT_TIMER)) {
+			/* GoodCRC w/out match or timeout waiting */
+			if (tx_retry_count < tx_retry_max) {
+				ucpd_set_tx_state(STATE_ACTIVE_TCPM);
+				msg_src = TX_MSG_TCPM;
+				tx_retry_count++;
+			} else {
+				ucpd_set_tx_state(STATE_IDLE);
+				pd_transmit_complete(port,
+						     TCPC_TX_COMPLETE_FAILED);
+			}
+		} else if (evt & UCPD_EVT_RX_MSG) {
+			/*
+			 * In the case of a collsion, it's possible the port
+			 * partner may not send a GoodCRC and instead send the
+			 * message that was colliding. If a message is received
+			 * in this state, then treat it as a discard from an
+			 * incoming message.
+			 */
+			pd_transmit_complete(port, TCPC_TX_COMPLETE_DISCARDED);
+			ucpd_set_tx_state(STATE_IDLE);
+		}
+		break;
+
+	case STATE_HARD_RESET:
+		if (evt & UCPD_EVT_HR_DONE) {
+			/* HR complete, reset tx state values */
+			ucpd_set_tx_state(STATE_IDLE);
+			ucpd_tx_request = 0;
+			tx_retry_count = 0;
+		} else if (evt & UCPD_EVT_HR_FAIL) {
+			ucpd_set_tx_state(STATE_IDLE);
+			ucpd_tx_request = 0;
+			tx_retry_count = 0;
+		}
+		break;
+	}
+
+	/* If msg_src is valid, then start transmit */
+	if (msg_src > TX_MSG_NONE) {
+		stm32gx_ucpd_start_transmit(port, msg_src);
+	}
+
+#ifdef CONFIG_STM32G4_UCPD_DEBUG
+	ucpd_task_log(ucpd_timeout_us, enter, ucpd_tx_state, req, evt);
+#endif
+}
+
+/*
+ * Main task entry point for UCPD task
+ *
+ * @param p The PD port number for which to handle interrupts (pointer is
+ * reinterpreted as an integer directly).
+ */
+void ucpd_task(void *p)
+{
+	const int port = (int)((intptr_t)p);
+
+	/* Init variables used to manage tx process */
+	stm32gx_ucpd_state_init(port);
+
+	while (1) {
+		/*
+		 * Note that ucpd_timeout_us is file scope and may be modified
+		 * in the tx state machine when entering the STATE_WAIT_CRC_ACK
+		 * state. Otherwise, the expectation is that the task is woken
+		 * only upon non-timer events.
+		 */
+		int evt = task_wait_event(ucpd_timeout_us);
+
+		/*
+		 * USB-PD messages are intiated in TCPM stack (PRL
+		 * layer). However, GoodCRC messages are initiated within the
+		 * UCPD driver based on USB-PD rx messages. These 2 types of
+		 * transmit paths are managed via task events.
+		 *
+		 * UCPD generated GoodCRC messages, are the priority path as
+		 * they must be sent immediately following a successful USB-PD
+		 * rx message. As long as a transmit operation is not underway,
+		 * then a transmit message will be started upon request. The ISR
+		 * routine sets the event to indicate that the transmit
+		 * operation is complete.
+		 *
+		 * Hard reset requests are sent as a TCPM message, but in terms
+		 * of the ucpd transmitter, they are treated as a 3rd tx msg
+		 * source since they can interrupt an ongoing tx msg, and there
+		 * is no requirement to wait for a GoodCRC reply message.
+		 */
+
+		/* Assume there is no timer for next task wake */
+		ucpd_timeout_us = -1;
+
+		if (evt & UCPD_EVT_GOOD_CRC_REQ)
+			ucpd_tx_request |= MSG_GOOD_CRC_MASK;
+
+		if (evt & UCPD_EVT_TCPM_MSG_REQ)
+			ucpd_tx_request |= MSG_TCPM_MASK;
+
+		/*
+		 * Manage PD tx messages. The state machine may need to be
+		 * called more than once when the task wakes. For instance, if
+		 * the task is woken at the completion of sending a GoodCRC,
+		 * there may be a TCPM message request pending and just changing
+		 * the state back to idle would not trigger start of transmit.
+		 */
+		do {
+			ucpd_manage_tx(port, evt);
+			/* Look at task events only once. */
+			evt = 0;
+		} while (ucpd_tx_request && ucpd_tx_state == STATE_IDLE &&
+			 !ucpd_rx_msg_active);
+	}
+}
+
+static void ucpd_send_good_crc(int port, uint16_t rx_header)
+{
+	int msg_id;
+	int rev_id;
+	uint16_t tx_header;
+	enum tcpci_msg_type tx_type;
+	enum pd_power_role pr = 0;
+	enum pd_data_role dr = 0;
+
+	/*
+	 * A GoodCRC message shall be sent by receiver to ack that the previous
+	 * message was correctly received. The GoodCRC message shall return the
+	 * rx message's msg_id field. The one exception is for GoodCRC messages,
+	 * which do not generate a GoodCRC response
+	 */
+	if (ucpd_msg_is_good_crc(rx_header)) {
+		return;
+	}
+
+	/*
+	 * Get the rx ordered set code just detected. SOP -> SOP''_Debug are in
+	 * the same order as enum tcpci_msg_type and so can be used
+	 * directly.
+	 */
+	tx_type = STM32_UCPD_RX_ORDSETR(port) & STM32_UCPD_RXORDSETR_MASK;
+
+	/*
+	 * PD Header(SOP):
+	 *   Extended   b15    -> set to 0 for control messages
+	 *   Count      b14:12 -> number of 32 bit data objects = 0 for ctrl msg
+	 *   MsgID      b11:9  -> running byte counter (extracted from rx msg)
+	 *   Power Role b8     -> stored in static, from set_msg_header()
+	 *   Spec Rev   b7:b6  -> PD spec revision (extracted from rx msg)
+	 *   Data Role  b5     -> stored in static, from set_msg_header
+	 *   Msg Type   b4:b0  -> data or ctrl type = PD_CTRL_GOOD_CRC
+	 */
+	/* construct header message */
+	msg_id = PD_HEADER_ID(rx_header);
+	rev_id = PD_HEADER_REV(rx_header);
+	if (tx_type == TCPCI_MSG_SOP) {
+		pr = msg_header.pr;
+		dr = msg_header.dr;
+	}
+	tx_header = PD_HEADER(PD_CTRL_GOOD_CRC, pr, dr, msg_id, 0, rev_id, 0);
+
+	/* Good CRC is header with no other objects */
+	ucpd_tx_buffers[TX_MSG_GOOD_CRC].msg_len = 2;
+	ucpd_tx_buffers[TX_MSG_GOOD_CRC].data.header = tx_header;
+	ucpd_tx_buffers[TX_MSG_GOOD_CRC].type = tx_type;
+
+	/* Notify ucpd task that a GoodCRC message tx request is pending */
+	task_set_event(TASK_ID_UCPD, UCPD_EVT_GOOD_CRC_REQ);
+}
+
+int stm32gx_ucpd_transmit(int port, enum tcpci_msg_type type, uint16_t header,
+			  const uint32_t *data)
+{
+	/* Length in bytes = (4 * object len) + 2 header byes */
+	int len = (PD_HEADER_CNT(header) << 2) + 2;
+
+	if (len > UCPD_BUF_LEN)
+		return EC_ERROR_OVERFLOW;
+
+	/* Store tx msg info in TCPM msg descriptor */
+	ucpd_tx_buffers[TX_MSG_TCPM].msg_len = len;
+	ucpd_tx_buffers[TX_MSG_TCPM].type = type;
+	ucpd_tx_buffers[TX_MSG_TCPM].data.header = header;
+	/* Copy msg objects to ucpd data buffer, after 2 header bytes */
+	memcpy(ucpd_tx_buffers[TX_MSG_TCPM].data.msg + 2, (uint8_t *)data,
+	       len - 2);
+
+	/*
+	 * Check for hard reset message here. A different event is used for hard
+	 * resets as they are able to interrupt ongoing transmit, and should
+	 * have priority over any pending message.
+	 */
+	if (type == TCPCI_MSG_TX_HARD_RESET)
+		task_set_event(TASK_ID_UCPD, UCPD_EVT_HR_REQ);
+	else
+		task_set_event(TASK_ID_UCPD, UCPD_EVT_TCPM_MSG_REQ);
+
+	return EC_SUCCESS;
+}
+
+int stm32gx_ucpd_get_message_raw(int port, uint32_t *payload, int *head)
+{
+	uint16_t *rx_header = (uint16_t *)ucpd_rx_buffer;
+	int rxpaysz;
+#ifdef CONFIG_USB_PD_DECODE_SOP
+	int sop;
+#endif
+
+	/* First 2 bytes of data buffer are the header */
+	*head = *rx_header;
+
+#ifdef CONFIG_USB_PD_DECODE_SOP
+	/*
+	 * The message header is a 16-bit value that's stored in a 32-bit data
+	 * type. SOP* is encoded in bits 31 to 28 of the 32-bit data type. NOTE:
+	 * The 4 byte header is not part of the PD spec.
+	 */
+	/* Get SOP value */
+	sop = STM32_UCPD_RX_ORDSETR(port) & STM32_UCPD_RXORDSETR_MASK;
+	/* Put SOP in bits 31:28 of 32 bit header */
+	*head |= PD_HEADER_SOP(sop);
+#endif
+	rxpaysz = STM32_UCPD_RX_PAYSZR(port) & STM32_UCPD_RX_PAYSZR_MASK;
+	/* This size includes 2 bytes for message header */
+	rxpaysz -= 2;
+	/* Copy payload (src/dst are both 32 bit aligned) */
+	memcpy(payload, ucpd_rx_buffer + 2, rxpaysz);
+
+	return EC_SUCCESS;
+}
+
+enum ec_error_list stm32gx_ucpd_set_bist_test_mode(const int port,
+						   const bool enable)
+{
+	ucpd_rx_bist_mode = enable;
+	CPRINTS("ucpd: Bist test mode = %d", enable);
+
+	return EC_SUCCESS;
+}
+
+static void stm32gx_ucpd1_irq(void)
+{
+	/* STM32_IRQ_UCPD indicates this is from UCPD1, so port = 0 */
+	int port = 0;
+	uint32_t sr = STM32_UCPD_SR(port);
+	uint32_t tx_done_mask = STM32_UCPD_SR_TXMSGSENT |
+				STM32_UCPD_SR_TXMSGABT |
+				STM32_UCPD_SR_TXMSGDISC |
+				STM32_UCPD_SR_HRSTSENT | STM32_UCPD_SR_HRSTDISC;
+
+	/* Check for CC events, set event to wake PD task */
+	if (sr & (STM32_UCPD_SR_TYPECEVT1 | STM32_UCPD_SR_TYPECEVT2)) {
+		task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_CC);
+#ifdef CONFIG_STM32G4_UCPD_DEBUG
+		ucpd_sr_cc_event = sr;
+		hook_call_deferred(&ucpd_cc_change_notify_data, 0);
+#endif
+	}
+
+	/*
+	 * Check for Tx events. tx_mask includes all status bits related to the
+	 * end of a USB-PD tx message. If any of these bits are set, the
+	 * transmit attempt is completed. Set an event to notify ucpd tx state
+	 * machine that transmit operation is complete.
+	 */
+	if (sr & tx_done_mask) {
+		/* Check for tx message complete */
+		if (sr & STM32_UCPD_SR_TXMSGSENT) {
+			task_set_event(TASK_ID_UCPD, UCPD_EVT_TX_MSG_SUCCESS);
+#ifdef CONFIG_STM32G4_UCPD_DEBUG
+			ucpd_log_mark_tx_comp();
+#endif
+		} else if (sr &
+			   (STM32_UCPD_SR_TXMSGABT | STM32_UCPD_SR_TXUND)) {
+			task_set_event(TASK_ID_UCPD, UCPD_EVT_TX_MSG_FAIL);
+		} else if (sr & STM32_UCPD_SR_TXMSGDISC) {
+			task_set_event(TASK_ID_UCPD, UCPD_EVT_TX_MSG_DISC);
+#ifdef CONFIG_STM32G4_UCPD_DEBUG
+			ucpd_log_mark_tx_comp();
+#endif
+		} else if (sr & STM32_UCPD_SR_HRSTSENT) {
+			task_set_event(TASK_ID_UCPD, UCPD_EVT_HR_DONE);
+		} else if (sr & STM32_UCPD_SR_HRSTDISC) {
+			task_set_event(TASK_ID_UCPD, UCPD_EVT_HR_FAIL);
+		}
+		/* Disable Tx interrupts */
+		ucpd_tx_interrupts_enable(port, 0);
+	}
+
+	/* Check for data register empty */
+	if (sr & STM32_UCPD_SR_TXIS)
+		ucpd_tx_data_byte(port);
+
+	/* Check for Rx Events */
+	/* Check first for start of new message */
+	if (sr & STM32_UCPD_SR_RXORDDET) {
+		ucpd_rx_byte_count = 0;
+		ucpd_rx_msg_active = 1;
+	}
+	/* Check for byte received */
+	if (sr & STM32_UCPD_SR_RXNE)
+		ucpd_rx_data_byte(port);
+
+	/* Check for end of message */
+	if (sr & STM32_UCPD_SR_RXMSGEND) {
+		ucpd_rx_msg_active = 0;
+		/* Check for errors */
+		if (!(sr & STM32_UCPD_SR_RXERR)) {
+			uint16_t *rx_header = (uint16_t *)ucpd_rx_buffer;
+			enum tcpci_msg_type type;
+			int good_crc = 0;
+
+			type = STM32_UCPD_RX_ORDSETR(port) &
+			       STM32_UCPD_RXORDSETR_MASK;
+
+			good_crc = ucpd_msg_is_good_crc(*rx_header);
+
+#ifdef CONFIG_STM32G4_UCPD_DEBUG
+			ucpd_log_add_msg(*rx_header, 1);
+#endif
+			/*
+			 * Don't pass GoodCRC control messages to the TCPM
+			 * layer. In addition, need to filter for SOP'/SOP''
+			 * packets if those are not enabled. SOP'/SOP''
+			 * reception is controlled by a static variable. The
+			 * hardware orderset detection pattern can't be changed
+			 * without disabling the ucpd peripheral.
+			 */
+			if (!good_crc && (ucpd_rx_sop_prime_enabled ||
+					  type == TCPCI_MSG_SOP)) {
+				/*
+				 * If BIST test mode is active, then still need
+				 * to send GoodCRC reply, but there is no need
+				 * to send the message up to the tcpm layer.
+				 */
+				if (!ucpd_rx_bist_mode) {
+					if (tcpm_enqueue_message(port))
+						hook_call_deferred(
+							&ucpd_rx_enque_error_data,
+							0);
+				}
+
+				task_set_event(TASK_ID_UCPD, UCPD_EVT_RX_MSG);
+
+				/* Send GoodCRC message (if required) */
+				ucpd_send_good_crc(port, *rx_header);
+			} else if (good_crc) {
+				task_set_event(TASK_ID_UCPD,
+					       UCPD_EVT_RX_GOOD_CRC);
+				ucpd_crc_id = PD_HEADER_ID(*rx_header);
+			}
+		} else {
+			/* Rx message is complete, but there were bit errors */
+			CPRINTS("ucpd: rx message error");
+		}
+	}
+	/* Check for fault conditions */
+	if (sr & STM32_UCPD_SR_RXHRSTDET) {
+		/* hard reset received */
+		pd_execute_hard_reset(port);
+		task_set_event(PD_PORT_TO_TASK_ID(port), TASK_EVENT_WAKE);
+		hook_call_deferred(&ucpd_hard_reset_rx_log_data, 0);
+	}
+
+	/* Clear interrupts now that PD events have been set */
+	STM32_UCPD_ICR(port) = sr;
+}
+DECLARE_IRQ(STM32_IRQ_UCPD1, stm32gx_ucpd1_irq, 1);
+
+#ifdef CONFIG_STM32G4_UCPD_DEBUG
+static char ctrl_names[][12] = {
+	"rsvd",	   "GoodCRC",	"Goto Min",    "Accept",     "Reject",
+	"Ping",	   "PS_Rdy",	"Get_SRC",     "Get_SNK",    "DR_Swap",
+	"PR_Swap", "VCONN_Swp", "Wait",	       "Soft_Rst",   "RSVD",
+	"RSVD",	   "Not_Sup",	"Get_SRC_Ext", "Get_Status",
+};
+
+static char data_names[][10] = {
+	"RSVD",	 "SRC_CAP",  "REQUEST",	  "BIST", "SINK_CAP", "BATTERY",
+	"ALERT", "GET_INFO", "ENTER_USB", "RSVD", "RSVD",     "RSVD",
+	"RSVD",	 "RSVD",     "RSVD",	  "VDM",
+};
+
+static void ucpd_dump_msg_log(void)
+{
+	int i;
+	int type;
+	int len;
+	int dir;
+	uint16_t header;
+	char *name;
+
+	ccprintf("ucpd: msg_total = %d\n", msg_log_cnt);
+	ccprintf("Idx\t  Delta(us)\tDir\t   Type\t\tLen\t s1  s2   PR\t DR\n");
+	ccprintf("-----------------------------------------------------------"
+		 "-----------------\n");
+
+	for (i = 0; i < msg_log_idx; i++) {
+		uint32_t delta_ts = 0;
+		int j;
+
+		header = msg_log[i].header;
+
+		if (header != 0xabcd) {
+			type = PD_HEADER_TYPE(header);
+			len = PD_HEADER_CNT(header);
+			name = len ? data_names[type] : ctrl_names[type];
+			dir = msg_log[i].dir;
+			if (i) {
+				delta_ts = msg_log[i].ts - msg_log[i - 1].ts;
+			}
+
+			ccprintf("msg[%02d]: %08d\t %s\t %8s\t %02d\t %d  %d\t"
+				 "%s\t %s",
+				 i, delta_ts, dir ? "Rx" : "Tx", name, len,
+				 msg_log[i].comp, msg_log[i].crc,
+				 PD_HEADER_PROLE(header) ? "SRC" : "SNK",
+				 PD_HEADER_DROLE(header) ? "DFP" : "UFP");
+			len = MIN((len * 4) + 2, MSG_BUF_LEN);
+			for (j = 0; j < len; j++)
+				ccprintf(" %02x", msg_log[i].buf[j]);
+		} else {
+			if (i) {
+				delta_ts = msg_log[i].ts - msg_log[i - 1].ts;
+			}
+			ccprintf("msg[%02d]: %08d\t CC Voltage Change!", i,
+				 delta_ts);
+		}
+		ccprintf("\n");
+		msleep(5);
+	}
+}
+
+static void stm32gx_ucpd_set_cc_debug(int port, int cc_mask, int pull, int rp)
+{
+	int cc_enable;
+	uint32_t cr = STM32_UCPD_CR(port);
+
+	/*
+	 * Only update ANASUBMODE if specified pull type is Rp.
+	 */
+	if (pull == TYPEC_CC_RP) {
+		cr &= ~STM32_UCPD_CR_ANASUBMODE_MASK;
+		cr |= STM32_UCPD_CR_ANASUBMODE_VAL(UCPD_RP_TO_ANASUB(rp));
+	}
+
+	/*
+	 * Can't independently set pull value for CC1 from CC2. But, can
+	 * independently connect or disconnect pull for CC1 and CC2. Enable here
+	 * the CC lines specified by cc_mask. If desired pull is TYPEC_CC_OPEN,
+	 * then the CC lines specified in cc_mask will be disabled.
+	 */
+	/* Get existing cc enable value */
+	cc_enable = (cr & STM32_UCPD_CR_CCENABLE_MASK) >>
+		    STM32_UCPD_CR_CCENABLE_SHIFT;
+	/* Apply cc_mask (enable CC line specified) */
+	cc_enable |= cc_mask;
+
+	/* Set ANAMODE if cc_pull is Rd */
+	if (pull == TYPEC_CC_RD)
+		cr |= STM32_UCPD_CR_ANAMODE;
+	/* Clear ANAMODE if cc_pull is Rp */
+	else if (pull == TYPEC_CC_RP)
+		cr &= ~(STM32_UCPD_CR_ANAMODE);
+	else if (pull == TYPEC_CC_OPEN)
+		cc_enable &= ~cc_mask;
+
+	/* The value for this field needs to be OR'd in */
+	cr &= ~STM32_UCPD_CR_CCENABLE_MASK;
+	cr |= STM32_UCPD_CR_CCENABLE_VAL(cc_enable);
+	/* Update pull values */
+	STM32_UCPD_CR(port) = cr;
+	/* Display updated settings */
+	ucpd_cc_status(port);
+}
+
+void ucpd_info(int port)
+{
+	ucpd_cc_status(port);
+	ccprintf("\trx_en\t = %d\n\tpol\t = %d\n",
+		 !!(STM32_UCPD_CR(port) & STM32_UCPD_CR_PHYRXEN),
+		 !!(STM32_UCPD_CR(port) & STM32_UCPD_CR_PHYCCSEL));
+
+	/* Dump ucpd task state info */
+	ccprintf("ucpd: tx_state = %s, tx_req = %02x, timeout_us = %d\n",
+		 ucpd_names[ucpd_tx_state], ucpd_tx_request, ucpd_timeout_us);
+
+	ucpd_task_log_dump();
+}
+
+static int command_ucpd(int argc, const char **argv)
+{
+	uint32_t tx_data = 0;
+	char *e;
+	int val;
+	int port = 0;
+
+	if (argc < 2)
+		return EC_ERROR_PARAM_COUNT;
+
+	if (!strcasecmp(argv[1], "rst")) {
+		/* Force reset of ucpd peripheral */
+		stm32gx_ucpd_init(port);
+		pd_execute_hard_reset(port);
+		task_set_event(PD_PORT_TO_TASK_ID(port), TASK_EVENT_WAKE);
+	} else if (!strcasecmp(argv[1], "info")) {
+		ucpd_info(port);
+	} else if (!strcasecmp(argv[1], "bist")) {
+		/* Need to initiate via DPM to have a timer */
+		/* TODO(b/182861002): uncomment when Gingerbread has
+		 * full PD support landed.
+		 * pd_dpm_request(port, DPM_REQUEST_BIST_TX);
+		 */
+	} else if (!strcasecmp(argv[1], "hard")) {
+		stm32gx_ucpd_transmit(port, TCPCI_MSG_TX_HARD_RESET, 0,
+				      &tx_data);
+	} else if (!strcasecmp(argv[1], "pol")) {
+		if (argc < 3)
+			return EC_ERROR_PARAM_COUNT;
+		val = strtoi(argv[2], &e, 10);
+		if (val > 1)
+			val = 0;
+		stm32gx_ucpd_set_polarity(port, val);
+		stm32gx_ucpd_set_rx_enable(port, 1);
+		ccprintf("ucpd: set pol = %d, PHYRXEN = 1\n", val);
+	} else if (!strcasecmp(argv[1], "cc")) {
+		int cc_mask;
+		int pull;
+		int rp = 0; /* needs to be initialized */
+
+		if (argc < 3) {
+			ucpd_cc_status(port);
+			return EC_SUCCESS;
+		}
+		cc_mask = strtoi(argv[2], &e, 10);
+		if (cc_mask < 1 || cc_mask > 3)
+			return EC_ERROR_PARAM2;
+		/* cc_mask has determines which cc setting to apply */
+		if (!strcasecmp(argv[3], "rd")) {
+			pull = TYPEC_CC_RD;
+		} else if (!strcasecmp(argv[3], "rp")) {
+			pull = TYPEC_CC_RP;
+			rp = strtoi(argv[4], &e, 10);
+			if (rp < 0 || rp > 2)
+				return EC_ERROR_PARAM4;
+		} else if (!strcasecmp(argv[3], "open")) {
+			pull = TYPEC_CC_OPEN;
+		} else {
+			return EC_ERROR_PARAM3;
+		}
+		stm32gx_ucpd_set_cc_debug(port, cc_mask, pull, rp);
+
+	} else if (!strcasecmp(argv[1], "log")) {
+		if (argc < 3) {
+			ucpd_dump_msg_log();
+		} else if (!strcasecmp(argv[2], "clr")) {
+			msg_log_cnt = 0;
+			msg_log_idx = 0;
+		}
+	} else {
+		return EC_ERROR_PARAM1;
+	}
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(ucpd, command_ucpd,
+			"[rst|info|bist|hard|pol <0|1>|cc xx <rd|rp|open>|log",
+			"ucpd peripheral debug and control options");
+#endif
diff --git a/chip/stm32/ucpd-stm32gx.h b/chip/stm32/ucpd-stm32gx.h
index f0a73cb29e..d41503f9ef 100644
--- a/chip/stm32/ucpd-stm32gx.h
+++ b/chip/stm32/ucpd-stm32gx.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,6 +9,34 @@
 
 #include "usb_pd_tcpm.h"
 
+/*
+ * UCPD is fed directly from HSI which is @ 16MHz. The ucpd_clk goes to
+ * a prescaler who's output feeds the 'half-bit' divider which is used
+ * to generate clock for delay counters and BMC Rx/Tx blocks. The rx is
+ * designed to work in freq ranges of 6 <--> 18 MHz, however recommended
+ * range is 9 <--> 18 MHz.
+ *
+ *          ------- @ 16 MHz ---------   @ ~600 kHz   -------------
+ * HSI ---->| /psc |-------->| /hbit |--------------->| trans_cnt |
+ *          -------          ---------    |           -------------
+ *                                        |           -------------
+ *                                        |---------->| ifrgap_cnt|
+ *                                                    -------------
+ * Requirements:
+ *   1. hbit_clk ~= 600 kHz: 16 MHz / 600 kHz = 26.67
+ *   2. tTransitionWindow - 12 to 20 uSec
+ *   3. tInterframGap - uSec
+ *
+ * hbit_clk = HSI_clk / 27 = 592.6 kHz = 1.687 uSec period
+ * tTransitionWindow = 1.687 uS * 8 = 13.5 uS
+ * tInterFrameGap = 1.687 uS * 17 = 28.68 uS
+ */
+
+#define UCPD_PSC_DIV 1
+#define UCPD_HBIT_DIV 27
+#define UCPD_TRANSWIN_CNT 8
+#define UCPD_IFRGAP_CNT 17
+
 /*
  * K-codes and ordered set defines. These codes and sets are used to encode
  * which type of USB-PD message is being sent. This information can be found in
@@ -18,40 +46,35 @@
 #define UCPD_SYNC1 0x18u
 #define UCPD_SYNC2 0x11u
 #define UCPD_SYNC3 0x06u
-#define UCPD_RST1  0x07u
-#define UCPD_RST2  0x19u
-#define UCPD_EOP   0x0Du
+#define UCPD_RST1 0x07u
+#define UCPD_RST2 0x19u
+#define UCPD_EOP 0x0Du
 
+/* This order of this enum matches tcpm_sop_type */
 enum ucpd_tx_ordset {
-	TX_ORDERSET_SOP =	(UCPD_SYNC1 |
-				(UCPD_SYNC1<<5u) |
-				(UCPD_SYNC1<<10u) |
-				(UCPD_SYNC2<<15u)),
-	TX_ORDERSET_SOP1 =	(UCPD_SYNC1 |
-				(UCPD_SYNC1<<5u) |
-				(UCPD_SYNC3<<10u) |
-				(UCPD_SYNC3<<15u)),
-	TX_ORDERSET_SOP2 =	(UCPD_SYNC1 |
-				(UCPD_SYNC3<<5u) |
-				(UCPD_SYNC1<<10u) |
-				(UCPD_SYNC3<<15u)),
-	TX_ORDERSET_HARD_RESET =	(UCPD_RST1  |
-					(UCPD_RST1<<5u) |
-					(UCPD_RST1<<10u)  |
-					(UCPD_RST2<<15u)),
-	TX_ORDERSET_CABLE_RESET =
-					(UCPD_RST1 |
-					(UCPD_SYNC1<<5u) |
-					(UCPD_RST1<<10u)  |
-					(UCPD_SYNC3<<15u)),
-	TX_ORDERSET_SOP1_DEBUG =	(UCPD_SYNC1 |
-					(UCPD_RST2<<5u) |
-					(UCPD_RST2<<10u) |
-					(UCPD_SYNC3<<15u)),
-	TX_ORDERSET_SOP2_DEBUG =	(UCPD_SYNC1 |
-					(UCPD_RST2<<5u) |
-					(UCPD_SYNC3<<10u) |
-					(UCPD_SYNC2<<15u)),
+	TX_ORDERSET_SOP = (UCPD_SYNC1 | (UCPD_SYNC1 << 5u) |
+			   (UCPD_SYNC1 << 10u) | (UCPD_SYNC2 << 15u)),
+
+	TX_ORDERSET_SOP_PRIME = (UCPD_SYNC1 | (UCPD_SYNC1 << 5u) |
+				 (UCPD_SYNC3 << 10u) | (UCPD_SYNC3 << 15u)),
+
+	TX_ORDERSET_SOP_PRIME_PRIME =
+		(UCPD_SYNC1 | (UCPD_SYNC3 << 5u) | (UCPD_SYNC1 << 10u) |
+		 (UCPD_SYNC3 << 15u)),
+
+	TX_ORDERSET_SOP_PRIME_DEBUG =
+		(UCPD_SYNC1 | (UCPD_RST2 << 5u) | (UCPD_RST2 << 10u) |
+		 (UCPD_SYNC3 << 15u)),
+
+	TX_ORDERSET_SOP_PRIME_PRIME_DEBUG =
+		(UCPD_SYNC1 | (UCPD_RST2 << 5u) | (UCPD_SYNC3 << 10u) |
+		 (UCPD_SYNC2 << 15u)),
+
+	TX_ORDERSET_HARD_RESET = (UCPD_RST1 | (UCPD_RST1 << 5u) |
+				  (UCPD_RST1 << 10u) | (UCPD_RST2 << 15u)),
+
+	TX_ORDERSET_CABLE_RESET = (UCPD_RST1 | (UCPD_SYNC1 << 5u) |
+				   (UCPD_RST1 << 10u) | (UCPD_SYNC3 << 15u)),
 };
 
 /**
@@ -108,4 +131,86 @@ int stm32gx_ucpd_set_cc(int usbc_port, int cc_pull, int rp);
  */
 int stm32gx_ucpd_set_polarity(int usbc_port, enum tcpc_cc_polarity polarity);
 
+/**
+ * STM32Gx UCPD implementation of tcpci .set_rx_enable method
+ *
+ * @param usbc_port -> USB-C Port number
+ * @param enable -> on/off for USB-PD messages
+ * @return EC_SUCCESS
+ */
+int stm32gx_ucpd_set_rx_enable(int port, int enable);
+
+/**
+ * STM32Gx UCPD implementation of tcpci .set_msg_header method
+ *
+ * @param usbc_port -> USB-C Port number
+ * @param power_role -> port's current power role
+ * @param data_role -> port's current data role
+ * @return EC_SUCCESS
+ */
+int stm32gx_ucpd_set_msg_header(int port, int power_role, int data_role);
+
+/**
+ * STM32Gx UCPD implementation of tcpci .transmit method
+ *
+ * @param usbc_port -> USB-C Port number
+ * @param type -> SOP/SOP'/SOP'' etc
+ * @param header -> usb pd message header
+ * @param *data -> pointer to message contents
+ * @return EC_SUCCESS
+ */
+int stm32gx_ucpd_transmit(int port, enum tcpci_msg_type type, uint16_t header,
+			  const uint32_t *data);
+
+/**
+ * STM32Gx UCPD implementation of tcpci .get_message_raw method
+ *
+ * @param usbc_port -> USB-C Port number
+ * @param *payload -> pointer to where message should be written
+ * @param *head -> pointer to message header
+ * @return EC_SUCCESS
+ */
+int stm32gx_ucpd_get_message_raw(int port, uint32_t *payload, int *head);
+
+/**
+ * STM32Gx method to remove Rp when VCONN is being supplied
+ *
+ * @param usbc_port -> USB-C Port number
+ * @param enable -> connect/disc Rp
+ * @return EC_SUCCESS
+ */
+int stm32gx_ucpd_vconn_disc_rp(int port, int enable);
+
+/**
+ * STM32Gx UCPD implementation of tcpci .sop_prime_enable method
+ *
+ * @param usbc_port -> USB-C Port number
+ * @param enable -> control of SOP'/SOP'' messages
+ * @return EC_SUCCESS
+ */
+int stm32gx_ucpd_sop_prime_enable(int port, bool enable);
+
+int stm32gx_ucpd_get_chip_info(int port, int live,
+			       struct ec_response_pd_chip_info_v1 *chip_info);
+
+/**
+ * This function is used to enable/disable a ucpd debug feature that is used to
+ * mark the ucpd message log when there is a usbc detach event.
+ *
+ * @param enable -> on/off control for debug feature
+ */
+void ucpd_cc_detect_notify_enable(int enable);
+
+/**
+ * This function is used to enable/disable rx bist test mode in the ucpd
+ * driver. This mode is controlled at the PE layer. When this mode is enabled,
+ * the ucpd receiver will not pass BIST data messages to the protocol layer and
+ * only send GoodCRC replies.
+ *
+ * @param usbc_port -> USB-C Port number
+ * @param enable -> on/off control for rx bist mode
+ */
+enum ec_error_list stm32gx_ucpd_set_bist_test_mode(const int port,
+						   const bool enable);
+
 #endif /* __CROS_EC_UCPD_STM32GX_H */
diff --git a/chip/stm32/usart-stm32f0.c b/chip/stm32/usart-stm32f0.c
index 908542146f..debb062473 100644
--- a/chip/stm32/usart-stm32f0.c
+++ b/chip/stm32/usart-stm32f0.c
@@ -1,15 +1,14 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
-#include "usart-stm32f0.h"
-
 #include "clock.h"
 #include "common.h"
 #include "compile_time_macros.h"
 #include "hooks.h"
 #include "registers.h"
 #include "task.h"
+#include "usart-stm32f0.h"
 #include "util.h"
 
 /*
@@ -23,7 +22,7 @@ static struct usart_config const *configs[STM32_USARTS_MAX];
 
 struct usart_configs usart_get_configs(void)
 {
-	return (struct usart_configs) {configs, ARRAY_SIZE(configs)};
+	return (struct usart_configs){ configs, ARRAY_SIZE(configs) };
 }
 
 static void usart_variant_enable(struct usart_config const *config)
@@ -54,8 +53,7 @@ static void usart_variant_disable(struct usart_config const *config)
 	 * Only disable the shared interrupt for USART3/4 if both USARTs are
 	 * now disabled.
 	 */
-	if ((index == 0) ||
-	    (index == 1) ||
+	if ((index == 0) || (index == 1) ||
 	    (index == 2 && configs[3] == NULL) ||
 	    (index == 3 && configs[2] == NULL))
 		task_disable_irq(config->hw->irq);
@@ -64,25 +62,32 @@ static void usart_variant_disable(struct usart_config const *config)
 }
 
 static struct usart_hw_ops const usart_variant_hw_ops = {
-	.enable  = usart_variant_enable,
+	.enable = usart_variant_enable,
 	.disable = usart_variant_disable,
 };
 
 static void freq_change(void)
 {
-	size_t	i;
+	size_t i;
 
 	for (i = 0; i < ARRAY_SIZE(configs); ++i)
 		if (configs[i])
 			usart_set_baud_f0_l(configs[i], configs[i]->baud,
-					clock_get_freq());
+					    clock_get_freq());
 }
 
 DECLARE_HOOK(HOOK_FREQ_CHANGE, freq_change, HOOK_PRIO_DEFAULT);
 
 void usart_clear_tc(struct usart_config const *config)
 {
-	STM32_USART_ICR(config->hw->base) |= STM32_USART_ICR_TCCF;
+	/*
+	 * ST reference code does blind write to this register, as is usual
+	 * with the "write 1 to clear" convention, despite the datasheet
+	 * listing the bits as "keep at reset value", (which we assume is due
+	 * to copying from the description of reserved bits in read/write
+	 * registers.)
+	 */
+	STM32_USART_ICR(config->hw->base) = STM32_USART_ICR_TCCF;
 }
 
 /*
@@ -91,15 +96,15 @@ void usart_clear_tc(struct usart_config const *config)
  */
 #if defined(CONFIG_STREAM_USART1)
 struct usart_hw_config const usart1_hw = {
-	.index          = 0,
-	.base           = STM32_USART1_BASE,
-	.irq            = STM32_IRQ_USART1,
+	.index = 0,
+	.base = STM32_USART1_BASE,
+	.irq = STM32_IRQ_USART1,
 	.clock_register = &STM32_RCC_APB2ENR,
-	.clock_enable   = STM32_RCC_PB2_USART1,
-	.ops            = &usart_variant_hw_ops,
+	.clock_enable = STM32_RCC_PB2_USART1,
+	.ops = &usart_variant_hw_ops,
 };
 
-void usart1_interrupt(void)
+static void usart1_interrupt(void)
 {
 	usart_interrupt(configs[0]);
 }
@@ -109,15 +114,15 @@ DECLARE_IRQ(STM32_IRQ_USART1, usart1_interrupt, 2);
 
 #if defined(CONFIG_STREAM_USART2)
 struct usart_hw_config const usart2_hw = {
-	.index          = 1,
-	.base           = STM32_USART2_BASE,
-	.irq            = STM32_IRQ_USART2,
+	.index = 1,
+	.base = STM32_USART2_BASE,
+	.irq = STM32_IRQ_USART2,
 	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART2,
-	.ops            = &usart_variant_hw_ops,
+	.clock_enable = STM32_RCC_PB1_USART2,
+	.ops = &usart_variant_hw_ops,
 };
 
-void usart2_interrupt(void)
+static void usart2_interrupt(void)
 {
 	usart_interrupt(configs[1]);
 }
@@ -127,28 +132,28 @@ DECLARE_IRQ(STM32_IRQ_USART2, usart2_interrupt, 2);
 
 #if defined(CONFIG_STREAM_USART3)
 struct usart_hw_config const usart3_hw = {
-	.index          = 2,
-	.base           = STM32_USART3_BASE,
-	.irq            = STM32_IRQ_USART3_4,
+	.index = 2,
+	.base = STM32_USART3_BASE,
+	.irq = STM32_IRQ_USART3_4,
 	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART3,
-	.ops            = &usart_variant_hw_ops,
+	.clock_enable = STM32_RCC_PB1_USART3,
+	.ops = &usart_variant_hw_ops,
 };
 #endif
 
 #if defined(CONFIG_STREAM_USART4)
 struct usart_hw_config const usart4_hw = {
-	.index          = 3,
-	.base           = STM32_USART4_BASE,
-	.irq            = STM32_IRQ_USART3_4,
+	.index = 3,
+	.base = STM32_USART4_BASE,
+	.irq = STM32_IRQ_USART3_4,
 	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART4,
-	.ops            = &usart_variant_hw_ops,
+	.clock_enable = STM32_RCC_PB1_USART4,
+	.ops = &usart_variant_hw_ops,
 };
 #endif
 
 #if defined(CONFIG_STREAM_USART3) || defined(CONFIG_STREAM_USART4)
-void usart3_4_interrupt(void)
+static void usart3_4_interrupt(void)
 {
 	/*
 	 * This interrupt handler could be called with one of these configs
diff --git a/chip/stm32/usart-stm32f0.h b/chip/stm32/usart-stm32f0.h
index 1b7eee95a7..72c88fba9c 100644
--- a/chip/stm32/usart-stm32f0.h
+++ b/chip/stm32/usart-stm32f0.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/stm32/usart-stm32f3.c b/chip/stm32/usart-stm32f3.c
index 42a0cf310e..b46ac2ed8f 100644
--- a/chip/stm32/usart-stm32f3.c
+++ b/chip/stm32/usart-stm32f3.c
@@ -1,14 +1,13 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
-#include "usart-stm32f3.h"
-
 #include "common.h"
 #include "compile_time_macros.h"
 #include "hooks.h"
 #include "registers.h"
 #include "task.h"
+#include "usart-stm32f3.h"
 #include "util.h"
 
 /*
@@ -22,7 +21,7 @@ static struct usart_config const *configs[STM32_USARTS_MAX];
 
 struct usart_configs usart_get_configs(void)
 {
-	return (struct usart_configs) {configs, ARRAY_SIZE(configs)};
+	return (struct usart_configs){ configs, ARRAY_SIZE(configs) };
 }
 
 static void usart_variant_enable(struct usart_config const *config)
@@ -50,13 +49,20 @@ static void usart_variant_disable(struct usart_config const *config)
 }
 
 static struct usart_hw_ops const usart_variant_hw_ops = {
-	.enable  = usart_variant_enable,
+	.enable = usart_variant_enable,
 	.disable = usart_variant_disable,
 };
 
 void usart_clear_tc(struct usart_config const *config)
 {
-	STM32_USART_ICR(config->hw->base) |= STM32_USART_ICR_TCCF;
+	/*
+	 * ST reference code does blind write to this register, as is usual
+	 * with the "write 1 to clear" convention, despite the datasheet
+	 * listing the bits as "keep at reset value", (which we assume is due
+	 * to copying from the description of reserved bits in read/write
+	 * registers.)
+	 */
+	STM32_USART_ICR(config->hw->base) = STM32_USART_ICR_TCCF;
 }
 
 /*
@@ -65,15 +71,15 @@ void usart_clear_tc(struct usart_config const *config)
  */
 #if defined(CONFIG_STREAM_USART1)
 struct usart_hw_config const usart1_hw = {
-	.index          = 0,
-	.base           = STM32_USART1_BASE,
-	.irq            = STM32_IRQ_USART1,
+	.index = 0,
+	.base = STM32_USART1_BASE,
+	.irq = STM32_IRQ_USART1,
 	.clock_register = &STM32_RCC_APB2ENR,
-	.clock_enable   = STM32_RCC_PB2_USART1,
-	.ops            = &usart_variant_hw_ops,
+	.clock_enable = STM32_RCC_PB2_USART1,
+	.ops = &usart_variant_hw_ops,
 };
 
-void usart1_interrupt(void)
+static void usart1_interrupt(void)
 {
 	usart_interrupt(configs[0]);
 }
@@ -83,15 +89,15 @@ DECLARE_IRQ(STM32_IRQ_USART1, usart1_interrupt, 2);
 
 #if defined(CONFIG_STREAM_USART2)
 struct usart_hw_config const usart2_hw = {
-	.index          = 1,
-	.base           = STM32_USART2_BASE,
-	.irq            = STM32_IRQ_USART2,
+	.index = 1,
+	.base = STM32_USART2_BASE,
+	.irq = STM32_IRQ_USART2,
 	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART2,
-	.ops            = &usart_variant_hw_ops,
+	.clock_enable = STM32_RCC_PB1_USART2,
+	.ops = &usart_variant_hw_ops,
 };
 
-void usart2_interrupt(void)
+static void usart2_interrupt(void)
 {
 	usart_interrupt(configs[1]);
 }
@@ -101,17 +107,17 @@ DECLARE_IRQ(STM32_IRQ_USART2, usart2_interrupt, 2);
 
 #if defined(CONFIG_STREAM_USART3)
 struct usart_hw_config const usart3_hw = {
-	.index          = 2,
-	.base           = STM32_USART3_BASE,
-	.irq            = STM32_IRQ_USART3,
+	.index = 2,
+	.base = STM32_USART3_BASE,
+	.irq = STM32_IRQ_USART3,
 	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART3,
-	.ops            = &usart_variant_hw_ops,
+	.clock_enable = STM32_RCC_PB1_USART3,
+	.ops = &usart_variant_hw_ops,
 };
 #endif
 
 #if defined(CONFIG_STREAM_USART3)
-void usart3_interrupt(void)
+static void usart3_interrupt(void)
 {
 	usart_interrupt(configs[2]);
 }
diff --git a/chip/stm32/usart-stm32f3.h b/chip/stm32/usart-stm32f3.h
index 09f1ba608c..e1c391183d 100644
--- a/chip/stm32/usart-stm32f3.h
+++ b/chip/stm32/usart-stm32f3.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/stm32/usart-stm32f4.c b/chip/stm32/usart-stm32f4.c
index a554da147a..0806cab062 100644
--- a/chip/stm32/usart-stm32f4.c
+++ b/chip/stm32/usart-stm32f4.c
@@ -1,16 +1,15 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include "usart-stm32f4.h"
-
 #include "clock.h"
 #include "common.h"
 #include "compile_time_macros.h"
 #include "hooks.h"
 #include "registers.h"
 #include "task.h"
+#include "usart-stm32f4.h"
 #include "util.h"
 
 /*
@@ -24,14 +23,13 @@ static struct usart_config const *configs[STM32_USARTS_MAX];
 
 struct usart_configs usart_get_configs(void)
 {
-	return (struct usart_configs) {configs, ARRAY_SIZE(configs)};
+	return (struct usart_configs){ configs, ARRAY_SIZE(configs) };
 }
 
 static void usart_variant_enable(struct usart_config const *config)
 {
 	configs[config->hw->index] = config;
 
-
 	/* Use single-bit sampling */
 	STM32_USART_CR3(config->hw->base) |= STM32_USART_CR3_ONEBIT;
 
@@ -48,7 +46,7 @@ static void usart_variant_disable(struct usart_config const *config)
 }
 
 static struct usart_hw_ops const usart_variant_hw_ops = {
-	.enable  = usart_variant_enable,
+	.enable = usart_variant_enable,
 	.disable = usart_variant_disable,
 };
 
@@ -58,15 +56,15 @@ static struct usart_hw_ops const usart_variant_hw_ops = {
  */
 #if defined(CONFIG_STREAM_USART1)
 struct usart_hw_config const usart1_hw = {
-	.index          = 0,
-	.base           = STM32_USART1_BASE,
-	.irq            = STM32_IRQ_USART1,
+	.index = 0,
+	.base = STM32_USART1_BASE,
+	.irq = STM32_IRQ_USART1,
 	.clock_register = &STM32_RCC_APB2ENR,
-	.clock_enable   = STM32_RCC_PB2_USART1,
-	.ops            = &usart_variant_hw_ops,
+	.clock_enable = STM32_RCC_PB2_USART1,
+	.ops = &usart_variant_hw_ops,
 };
 
-void usart1_interrupt(void)
+static void usart1_interrupt(void)
 {
 	usart_interrupt(configs[0]);
 }
@@ -76,15 +74,15 @@ DECLARE_IRQ(STM32_IRQ_USART1, usart1_interrupt, 2);
 
 #if defined(CONFIG_STREAM_USART2)
 struct usart_hw_config const usart2_hw = {
-	.index          = 1,
-	.base           = STM32_USART2_BASE,
-	.irq            = STM32_IRQ_USART2,
+	.index = 1,
+	.base = STM32_USART2_BASE,
+	.irq = STM32_IRQ_USART2,
 	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART2,
-	.ops            = &usart_variant_hw_ops,
+	.clock_enable = STM32_RCC_PB1_USART2,
+	.ops = &usart_variant_hw_ops,
 };
 
-void usart2_interrupt(void)
+static void usart2_interrupt(void)
 {
 	usart_interrupt(configs[1]);
 }
@@ -94,17 +92,17 @@ DECLARE_IRQ(STM32_IRQ_USART2, usart2_interrupt, 2);
 
 #if defined(CONFIG_STREAM_USART3)
 struct usart_hw_config const usart3_hw = {
-	.index          = 2,
-	.base           = STM32_USART3_BASE,
-	.irq            = STM32_IRQ_USART3,
+	.index = 2,
+	.base = STM32_USART3_BASE,
+	.irq = STM32_IRQ_USART3,
 	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART3,
-	.ops            = &usart_variant_hw_ops,
+	.clock_enable = STM32_RCC_PB1_USART3,
+	.ops = &usart_variant_hw_ops,
 };
 #endif
 
 #if defined(CONFIG_STREAM_USART3)
-void usart3_interrupt(void)
+static void usart3_interrupt(void)
 {
 	usart_interrupt(configs[2]);
 }
diff --git a/chip/stm32/usart-stm32f4.h b/chip/stm32/usart-stm32f4.h
index 49af2af405..5ecb4d62e1 100644
--- a/chip/stm32/usart-stm32f4.h
+++ b/chip/stm32/usart-stm32f4.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/stm32/usart-stm32l.c b/chip/stm32/usart-stm32l.c
index 2b7406a0a4..b6c9e21595 100644
--- a/chip/stm32/usart-stm32l.c
+++ b/chip/stm32/usart-stm32l.c
@@ -1,15 +1,14 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
-#include "usart-stm32l.h"
-
 #include "clock.h"
 #include "common.h"
 #include "compile_time_macros.h"
 #include "hooks.h"
 #include "registers.h"
 #include "task.h"
+#include "usart-stm32l.h"
 #include "util.h"
 
 /*
@@ -23,7 +22,7 @@ static struct usart_config const *configs[STM32_USARTS_MAX];
 
 struct usart_configs usart_get_configs(void)
 {
-	return (struct usart_configs) {configs, ARRAY_SIZE(configs)};
+	return (struct usart_configs){ configs, ARRAY_SIZE(configs) };
 }
 
 static void usart_variant_enable(struct usart_config const *config)
@@ -52,18 +51,18 @@ static void usart_variant_disable(struct usart_config const *config)
 }
 
 static struct usart_hw_ops const usart_variant_hw_ops = {
-	.enable  = usart_variant_enable,
+	.enable = usart_variant_enable,
 	.disable = usart_variant_disable,
 };
 
 static void freq_change(void)
 {
-	size_t	i;
+	size_t i;
 
 	for (i = 0; i < ARRAY_SIZE(configs); ++i)
 		if (configs[i])
 			usart_set_baud_f0_l(configs[i], configs[i]->baud,
-					clock_get_freq());
+					    clock_get_freq());
 }
 
 DECLARE_HOOK(HOOK_FREQ_CHANGE, freq_change, HOOK_PRIO_DEFAULT);
@@ -79,15 +78,15 @@ void usart_clear_tc(struct usart_config const *config)
  */
 #if defined(CONFIG_STREAM_USART1)
 struct usart_hw_config const usart1_hw = {
-	.index          = 0,
-	.base           = STM32_USART1_BASE,
-	.irq            = STM32_IRQ_USART1,
+	.index = 0,
+	.base = STM32_USART1_BASE,
+	.irq = STM32_IRQ_USART1,
 	.clock_register = &STM32_RCC_APB2ENR,
-	.clock_enable   = STM32_RCC_PB2_USART1,
-	.ops            = &usart_variant_hw_ops,
+	.clock_enable = STM32_RCC_PB2_USART1,
+	.ops = &usart_variant_hw_ops,
 };
 
-void usart1_interrupt(void)
+static void usart1_interrupt(void)
 {
 	usart_interrupt(configs[0]);
 }
@@ -97,15 +96,15 @@ DECLARE_IRQ(STM32_IRQ_USART1, usart1_interrupt, 2);
 
 #if defined(CONFIG_STREAM_USART2)
 struct usart_hw_config const usart2_hw = {
-	.index          = 1,
-	.base           = STM32_USART2_BASE,
-	.irq            = STM32_IRQ_USART2,
+	.index = 1,
+	.base = STM32_USART2_BASE,
+	.irq = STM32_IRQ_USART2,
 	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART2,
-	.ops            = &usart_variant_hw_ops,
+	.clock_enable = STM32_RCC_PB1_USART2,
+	.ops = &usart_variant_hw_ops,
 };
 
-void usart2_interrupt(void)
+static void usart2_interrupt(void)
 {
 	usart_interrupt(configs[1]);
 }
@@ -115,15 +114,15 @@ DECLARE_IRQ(STM32_IRQ_USART2, usart2_interrupt, 2);
 
 #if defined(CONFIG_STREAM_USART3)
 struct usart_hw_config const usart3_hw = {
-	.index          = 2,
-	.base           = STM32_USART3_BASE,
-	.irq            = STM32_IRQ_USART3,
+	.index = 2,
+	.base = STM32_USART3_BASE,
+	.irq = STM32_IRQ_USART3,
 	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART3,
-	.ops            = &usart_variant_hw_ops,
+	.clock_enable = STM32_RCC_PB1_USART3,
+	.ops = &usart_variant_hw_ops,
 };
 
-void usart3_interrupt(void)
+static void usart3_interrupt(void)
 {
 	usart_interrupt(configs[2]);
 }
diff --git a/chip/stm32/usart-stm32l.h b/chip/stm32/usart-stm32l.h
index eb1ae9db1d..2bb92fe1c7 100644
--- a/chip/stm32/usart-stm32l.h
+++ b/chip/stm32/usart-stm32l.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/stm32/usart-stm32l5.c b/chip/stm32/usart-stm32l5.c
new file mode 100644
index 0000000000..5f34c37bc4
--- /dev/null
+++ b/chip/stm32/usart-stm32l5.c
@@ -0,0 +1,185 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "clock.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "hooks.h"
+#include "registers.h"
+#include "task.h"
+#include "usart-stm32l.h"
+#include "util.h"
+
+/*
+ * This configs array stores the currently active usart_config structure for
+ * each USART, an entry will be NULL if no USART driver is initialized for the
+ * corresponding hardware instance.
+ */
+#define STM32_USARTS_MAX 6
+
+static struct usart_config const *configs[STM32_USARTS_MAX];
+
+struct usart_configs usart_get_configs(void)
+{
+	return (struct usart_configs){ configs, ARRAY_SIZE(configs) };
+}
+
+static void usart_variant_enable(struct usart_config const *config)
+{
+	/* Use single-bit sampling */
+	STM32_USART_CR3(config->hw->base) |= STM32_USART_CR3_ONEBIT;
+
+	/*
+	 * Make sure we register this config before enabling the HW.
+	 * If we did it the other way around the FREQ_CHANGE hook could be
+	 * called before we update the configs array and we would miss the
+	 * clock frequency change event, leaving our baud rate divisor wrong.
+	 */
+	configs[config->hw->index] = config;
+
+	usart_set_baud_f0_l(config, config->baud, clock_get_freq());
+
+	task_enable_irq(config->hw->irq);
+}
+
+static void usart_variant_disable(struct usart_config const *config)
+{
+	task_disable_irq(config->hw->irq);
+
+	configs[config->hw->index] = NULL;
+}
+
+static struct usart_hw_ops const usart_variant_hw_ops = {
+	.enable = usart_variant_enable,
+	.disable = usart_variant_disable,
+};
+
+static void freq_change(void)
+{
+	size_t i;
+
+	for (i = 0; i < ARRAY_SIZE(configs); ++i)
+		if (configs[i])
+			usart_set_baud_f0_l(configs[i], configs[i]->baud,
+					    clock_get_freq());
+}
+
+DECLARE_HOOK(HOOK_FREQ_CHANGE, freq_change, HOOK_PRIO_DEFAULT);
+
+void usart_clear_tc(struct usart_config const *config)
+{
+	STM32_USART_SR(config->hw->base) &= ~STM32_USART_SR_TC;
+}
+
+/*
+ * USART interrupt bindings.  These functions can not be defined as static or
+ * they will be removed by the linker because of the way that DECLARE_IRQ works.
+ */
+#if defined(CONFIG_STREAM_USART1)
+struct usart_hw_config const usart1_hw = {
+	.index = 0,
+	.base = STM32_USART1_BASE,
+	.irq = STM32_IRQ_USART1,
+	.clock_register = &STM32_RCC_APB2ENR,
+	.clock_enable = STM32_RCC_PB2_USART1,
+	.ops = &usart_variant_hw_ops,
+};
+
+static void usart1_interrupt(void)
+{
+	usart_interrupt(configs[0]);
+}
+
+DECLARE_IRQ(STM32_IRQ_USART1, usart1_interrupt, 2);
+#endif
+
+#if defined(CONFIG_STREAM_USART2)
+struct usart_hw_config const usart2_hw = {
+	.index = 1,
+	.base = STM32_USART2_BASE,
+	.irq = STM32_IRQ_USART2,
+	.clock_register = &STM32_RCC_APB1ENR,
+	.clock_enable = STM32_RCC_PB1_USART2,
+	.ops = &usart_variant_hw_ops,
+};
+
+static void usart2_interrupt(void)
+{
+	usart_interrupt(configs[1]);
+}
+
+DECLARE_IRQ(STM32_IRQ_USART2, usart2_interrupt, 2);
+#endif
+
+#if defined(CONFIG_STREAM_USART3)
+struct usart_hw_config const usart3_hw = {
+	.index = 2,
+	.base = STM32_USART3_BASE,
+	.irq = STM32_IRQ_USART3,
+	.clock_register = &STM32_RCC_APB1ENR,
+	.clock_enable = STM32_RCC_PB1_USART3,
+	.ops = &usart_variant_hw_ops,
+};
+
+static void usart3_interrupt(void)
+{
+	usart_interrupt(configs[2]);
+}
+
+DECLARE_IRQ(STM32_IRQ_USART3, usart3_interrupt, 2);
+#endif
+
+#if defined(CONFIG_STREAM_USART4)
+struct usart_hw_config const usart4_hw = {
+	.index = 3,
+	.base = STM32_USART4_BASE,
+	.irq = STM32_IRQ_USART4,
+	.clock_register = &STM32_RCC_APB1ENR,
+	.clock_enable = STM32_RCC_PB1_USART4,
+	.ops = &usart_variant_hw_ops,
+};
+
+static void usart4_interrupt(void)
+{
+	usart_interrupt(configs[3]);
+}
+
+DECLARE_IRQ(STM32_IRQ_USART4, usart4_interrupt, 2);
+#endif
+
+#if defined(CONFIG_STREAM_USART5)
+struct usart_hw_config const usart5_hw = {
+	.index = 4,
+	.base = STM32_USART5_BASE,
+	.irq = STM32_IRQ_USART5,
+	.clock_register = &STM32_RCC_APB1ENR,
+	.clock_enable = STM32_RCC_PB1_USART5,
+	.ops = &usart_variant_hw_ops,
+};
+
+static void usart5_interrupt(void)
+{
+	usart_interrupt(configs[4]);
+}
+
+DECLARE_IRQ(STM32_IRQ_USART5, usart5_interrupt, 2);
+#endif
+
+#if defined(CONFIG_STREAM_USART9)
+struct usart_hw_config const usart9_hw = {
+	.index = 5,
+	.base = STM32_USART9_BASE,
+	.irq = STM32_IRQ_USART9,
+	.clock_register = &STM32_RCC_APB1ENR2,
+	.clock_enable = STM32_RCC_APB1ENR2_LPUART1EN,
+	.ops = &usart_variant_hw_ops,
+};
+
+static void usart9_interrupt(void)
+{
+	usart_interrupt(configs[5]);
+}
+
+DECLARE_IRQ(STM32_IRQ_USART9, usart9_interrupt, 2);
+#endif
diff --git a/chip/stm32/usart-stm32l5.h b/chip/stm32/usart-stm32l5.h
new file mode 100644
index 0000000000..ccc0985bda
--- /dev/null
+++ b/chip/stm32/usart-stm32l5.h
@@ -0,0 +1,21 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#ifndef __CROS_EC_USART_STM32L5_H
+#define __CROS_EC_USART_STM32L5_H
+
+#include "usart.h"
+
+/*
+ * The STM32L5 series can have as many as five UARTS.  These are the HW configs
+ * for those UARTS.  They can be used to initialize STM32 generic UART configs.
+ */
+extern struct usart_hw_config const usart1_hw;
+extern struct usart_hw_config const usart2_hw;
+extern struct usart_hw_config const usart3_hw;
+extern struct usart_hw_config const usart4_hw;
+extern struct usart_hw_config const usart5_hw;
+extern struct usart_hw_config const usart9_hw; /* LPUART1 */
+
+#endif /* __CROS_EC_USART_STM32L5_H */
diff --git a/chip/stm32/usart.c b/chip/stm32/usart.c
index 7f8c55aaa6..be9d0a4571 100644
--- a/chip/stm32/usart.c
+++ b/chip/stm32/usart.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -45,7 +45,7 @@ void usart_init(struct usart_config const *config)
 	cr2 = 0x0000;
 	cr3 = 0x0000;
 #if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \
-    defined(CHIP_FAMILY_STM32L4)
+	defined(CHIP_FAMILY_STM32L4)
 	if (config->flags & USART_CONFIG_FLAG_RX_INV)
 		cr2 |= BIT(16);
 	if (config->flags & USART_CONFIG_FLAG_TX_INV)
@@ -87,11 +87,16 @@ void usart_shutdown(struct usart_config const *config)
 }
 
 void usart_set_baud_f0_l(struct usart_config const *config, int baud,
-			int frequency_hz)
+			 int frequency_hz)
 {
-	int      div  = DIV_ROUND_NEAREST(frequency_hz, baud);
+	int div = DIV_ROUND_NEAREST(frequency_hz, baud);
 	intptr_t base = config->hw->base;
 
+#ifdef STM32_USART9_BASE
+	if (config->hw->base == STM32_USART9_BASE) /* LPUART */
+		div *= 256;
+#endif
+
 	if (div / 16 > 0) {
 		/*
 		 * CPU clock is high enough to support x16 oversampling.
@@ -110,10 +115,15 @@ void usart_set_baud_f0_l(struct usart_config const *config, int baud,
 }
 
 void usart_set_baud_f(struct usart_config const *config, int baud,
-		int frequency_hz)
+		      int frequency_hz)
 {
 	int div = DIV_ROUND_NEAREST(frequency_hz, baud);
 
+#ifdef STM32_USART9_BASE
+	if (config->hw->base == STM32_USART9_BASE) /* LPUART */
+		div *= 256;
+#endif
+
 	/* STM32F only supports x16 oversampling */
 	STM32_USART_BRR(config->hw->base) = div;
 }
diff --git a/chip/stm32/usart.h b/chip/stm32/usart.h
index 491bd66a04..9067fd4b6a 100644
--- a/chip/stm32/usart.h
+++ b/chip/stm32/usart.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -97,12 +97,12 @@ extern struct usart_tx const usart_tx_interrupt;
  * structure are provided by each variants driver, one per physical USART.
  */
 struct usart_hw_config {
-	int      index;
+	int index;
 	intptr_t base;
-	int      irq;
+	int irq;
 
 	uint32_t volatile *clock_register;
-	uint32_t           clock_enable;
+	uint32_t clock_enable;
 
 	struct usart_hw_ops const *ops;
 };
@@ -160,7 +160,7 @@ struct usart_config {
  * BUILD_ASSERT(RX_QUEUE.unit_bytes == 1);
  * BUILD_ASSERT(TX_QUEUE.unit_bytes == 1);
  */
-#define USART_CONFIG(HW, RX, TX, BAUD, FLAGS, RX_QUEUE, TX_QUEUE)	\
+#define USART_CONFIG(HW, RX, TX, BAUD, FLAGS, RX_QUEUE, TX_QUEUE) \
 	((struct usart_config const) {					\
 		.hw       = &HW,					\
 		.rx       = &RX,					\
@@ -208,9 +208,9 @@ void usart_tx_start(struct usart_config const *config);
  * change.  The baud rate divisor input frequency is passed in Hertz.
  */
 void usart_set_baud_f0_l(struct usart_config const *config, int baud,
-			int frequency_hz);
+			 int frequency_hz);
 void usart_set_baud_f(struct usart_config const *config, int baud,
-		int frequency_hz);
+		      int frequency_hz);
 
 /*
  * Allow specification of parity for this usart.
@@ -249,7 +249,7 @@ struct usart_configs {
 	 *
 	 * configs[i]->hw->index == i;
 	 */
-	struct usart_config const * const *configs;
+	struct usart_config const *const *configs;
 
 	/*
 	 * The total possible number of configs that this family supports.
diff --git a/chip/stm32/usart_host_command.c b/chip/stm32/usart_host_command.c
index f4d6a65fc4..817343df98 100644
--- a/chip/stm32/usart_host_command.c
+++ b/chip/stm32/usart_host_command.c
@@ -1,10 +1,10 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include "common.h"
 #include "clock.h"
+#include "common.h"
 #include "dma.h"
 #include "gpio.h"
 #include "hooks.h"
@@ -13,14 +13,14 @@
 #include "registers.h"
 #include "system.h"
 #include "task.h"
-#include "usart_rx_dma.h"
-#include "usart_host_command.h"
 #include "usart-stm32f4.h"
+#include "usart_host_command.h"
+#include "usart_rx_dma.h"
 #include "util.h"
 
 /* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_HOSTCMD, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_HOSTCMD, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_HOSTCMD, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_HOSTCMD, format, ##args)
 
 /*
  * Timeout to wait for complete request packet
@@ -51,7 +51,7 @@
 
 /*
  * Max data size for a version 3 request/response packet.  This is big enough
- * to handle a request/response header, flash write offset/size and 512 bytes 
+ * to handle a request/response header, flash write offset/size and 512 bytes
  * of request payload or 224 bytes of response payload.
  */
 #define USART_MAX_REQUEST_SIZE 0x220
@@ -271,12 +271,12 @@ static struct usart_rx_dma const usart_host_command_rx_dma = {
  * Configure USART structure with hardware, interrupt handlers, baudrate.
  */
 static struct usart_config const tl_usart = {
-	.hw	= &CONFIG_UART_HOST_COMMAND_HW,
-	.rx	= &usart_host_command_rx_dma.usart_rx,
-	.tx	= &usart_host_command_tx_interrupt,
-	.state	= &((struct usart_state){}),
-	.baud	= CONFIG_UART_HOST_COMMAND_BAUD_RATE,
-	.flags	= 0,
+	.hw = &CONFIG_UART_HOST_COMMAND_HW,
+	.rx = &usart_host_command_rx_dma.usart_rx,
+	.tx = &usart_host_command_tx_interrupt,
+	.state = &((struct usart_state){}),
+	.baud = CONFIG_UART_HOST_COMMAND_BAUD_RATE,
+	.flags = 0,
 };
 
 /*
@@ -327,7 +327,7 @@ static void usart_host_command_process_request(void)
 {
 	/* Handle usart_in_buffer as ec_host_request */
 	struct ec_host_request *ec_request =
-			(struct ec_host_request *)usart_in_buffer;
+		(struct ec_host_request *)usart_in_buffer;
 
 	/* Prepare host_packet for host command task */
 	static struct host_packet uart_packet;
@@ -362,16 +362,13 @@ static void usart_host_command_process_request(void)
 	 * Cancel deferred call to timeout handler as request
 	 * received was good.
 	 */
-	hook_call_deferred(
-		&usart_host_command_request_timeout_data,
-		-1);
+	hook_call_deferred(&usart_host_command_request_timeout_data, -1);
 
 	uart_packet.send_response = usart_host_command_process_response;
 	uart_packet.request = usart_in_buffer;
 	uart_packet.request_temp = NULL;
 	uart_packet.request_max = sizeof(usart_in_buffer);
-	uart_packet.request_size =
-			host_request_expected_size(ec_request);
+	uart_packet.request_size = host_request_expected_size(ec_request);
 	uart_packet.response = usart_out_buffer;
 	uart_packet.response_max = sizeof(usart_out_buffer);
 	uart_packet.response_size = 0;
@@ -427,14 +424,10 @@ static void usart_host_command_process_response(struct host_packet *pkt)
 static void usart_host_command_reset(void)
 {
 	/* Cancel deferred call to process_request. */
-	hook_call_deferred(
-		&usart_host_command_process_request_data,
-		-1);
+	hook_call_deferred(&usart_host_command_process_request_data, -1);
 
 	/* Cancel deferred call to timeout handler. */
-	hook_call_deferred(
-		&usart_host_command_request_timeout_data,
-		-1);
+	hook_call_deferred(&usart_host_command_request_timeout_data, -1);
 
 	/*
 	 * Disable interrupts before entering critical region
@@ -491,7 +484,7 @@ size_t usart_host_command_rx_append_data(struct usart_config const *config,
 {
 	/* Define ec_host_request pointer to process in bytes later*/
 	struct ec_host_request *ec_request =
-			(struct ec_host_request *) usart_in_buffer;
+		(struct ec_host_request *)usart_in_buffer;
 
 	/* Once the header is received, store the datalen */
 	static int usart_in_datalen;
@@ -504,8 +497,7 @@ size_t usart_host_command_rx_append_data(struct usart_config const *config,
 	    current_state == USART_HOST_CMD_RECEIVING ||
 	    (usart_in_head + count) < USART_MAX_REQUEST_SIZE) {
 		/* Copy all the bytes from DMA FIFO */
-		memcpy(usart_in_buffer + usart_in_head,
-			src, count);
+		memcpy(usart_in_buffer + usart_in_head, src, count);
 	}
 
 	/*
@@ -519,7 +511,7 @@ size_t usart_host_command_rx_append_data(struct usart_config const *config,
 	if (current_state == USART_HOST_CMD_READY_TO_RX) {
 		/* Kick deferred call to request timeout handler */
 		hook_call_deferred(&usart_host_command_request_timeout_data,
-			USART_REQ_RX_TIMEOUT);
+				   USART_REQ_RX_TIMEOUT);
 
 		/* Move current state to receiving */
 		current_state = USART_HOST_CMD_RECEIVING;
@@ -551,8 +543,7 @@ size_t usart_host_command_rx_append_data(struct usart_config const *config,
 		} else if (usart_in_head > usart_in_datalen) {
 			/* Cancel deferred call to process_request */
 			hook_call_deferred(
-				&usart_host_command_process_request_data,
-				-1);
+				&usart_host_command_process_request_data, -1);
 
 			/* Move state to overrun*/
 			current_state = USART_HOST_CMD_RX_OVERRUN;
@@ -579,13 +570,12 @@ size_t usart_host_command_tx_remove_data(struct usart_config const *config,
 {
 	size_t bytes_remaining = 0;
 
-	if (current_state == USART_HOST_CMD_SENDING &&
-	    usart_out_datalen != 0) {
+	if (current_state == USART_HOST_CMD_SENDING && usart_out_datalen != 0) {
 		/* Calculate byte_remaining in out_buffer */
 		bytes_remaining = usart_out_datalen - usart_out_head;
 
 		/* Get char on the head */
-		*((uint8_t *) dest) = usart_out_buffer[usart_out_head++];
+		*((uint8_t *)dest) = usart_out_buffer[usart_out_head++];
 
 		/* If no bytes remaining, reset layer to accept next
 		 * request.
diff --git a/chip/stm32/usart_host_command.h b/chip/stm32/usart_host_command.h
index ee41d8a59b..ddbd5c5c99 100644
--- a/chip/stm32/usart_host_command.h
+++ b/chip/stm32/usart_host_command.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,12 +6,13 @@
 #ifndef __CROS_EC_USART_HOST_COMMAND_H
 #define __CROS_EC_USART_HOST_COMMAND_H
 
-#include <stdarg.h>  /* For va_list */
 #include "common.h"
 #include "gpio.h"
 #include "host_command.h"
 #include "usart.h"
 
+#include <stdarg.h> /* For va_list */
+
 /*
  * Add data to host command layer buffer.
  */
diff --git a/chip/stm32/usart_info_command.c b/chip/stm32/usart_info_command.c
index 16d5e5747e..ca73b51210 100644
--- a/chip/stm32/usart_info_command.c
+++ b/chip/stm32/usart_info_command.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -9,7 +9,7 @@
 #include "console.h"
 #include "usart.h"
 
-static int command_usart_info(int argc, char **argv)
+static int command_usart_info(int argc, const char **argv)
 {
 	struct usart_configs configs = usart_get_configs();
 	size_t i;
@@ -24,10 +24,10 @@ static int command_usart_info(int argc, char **argv)
 			 "    dropped %d bytes\n"
 			 "    overran %d times\n",
 			 config->hw->index + 1,
-			 deprecated_atomic_read_clear(
-				 &(config->state->rx_dropped)),
-			 deprecated_atomic_read_clear(
-				 &(config->state->rx_overrun)));
+			 (int)atomic_clear(
+				 (atomic_t *)&(config->state->rx_dropped)),
+			 (int)atomic_clear(
+				 (atomic_t *)&(config->state->rx_overrun)));
 
 		if (config->rx->info)
 			config->rx->info(config);
@@ -39,7 +39,5 @@ static int command_usart_info(int argc, char **argv)
 	return EC_SUCCESS;
 }
 
-DECLARE_CONSOLE_COMMAND(usart_info,
-			command_usart_info,
-			NULL,
+DECLARE_CONSOLE_COMMAND(usart_info, command_usart_info, NULL,
 			"Display USART info");
diff --git a/chip/stm32/usart_rx_dma.c b/chip/stm32/usart_rx_dma.c
index 1867c0a310..8997617ff3 100644
--- a/chip/stm32/usart_rx_dma.c
+++ b/chip/stm32/usart_rx_dma.c
@@ -1,20 +1,19 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include "usart_rx_dma.h"
-
 #include "atomic.h"
 #include "common.h"
 #include "console.h"
 #include "registers.h"
 #include "system.h"
 #include "usart_host_command.h"
+#include "usart_rx_dma.h"
 #include "util.h"
 
 typedef size_t (*add_data_t)(struct usart_config const *config,
-	const uint8_t *src, size_t count);
+			     const uint8_t *src, size_t count);
 
 void usart_rx_dma_init(struct usart_config const *config)
 {
@@ -25,10 +24,9 @@ void usart_rx_dma_init(struct usart_config const *config)
 
 	struct dma_option options = {
 		.channel = dma_config->channel,
-		.periph  = (void *)&STM32_USART_RDR(base),
-		.flags   = (STM32_DMA_CCR_MSIZE_8_BIT |
-			    STM32_DMA_CCR_PSIZE_8_BIT |
-			    STM32_DMA_CCR_CIRC),
+		.periph = (void *)&STM32_USART_RDR(base),
+		.flags = (STM32_DMA_CCR_MSIZE_8_BIT |
+			  STM32_DMA_CCR_PSIZE_8_BIT | STM32_DMA_CCR_CIRC),
 	};
 
 	if (IS_ENABLED(CHIP_FAMILY_STM32F4))
@@ -38,31 +36,29 @@ void usart_rx_dma_init(struct usart_config const *config)
 	STM32_USART_CR1(base) |= STM32_USART_CR1_RE;
 	STM32_USART_CR3(base) |= STM32_USART_CR3_DMAR;
 
-	dma_config->state->index     = 0;
+	dma_config->state->index = 0;
 	dma_config->state->max_bytes = 0;
 
 	dma_start_rx(&options, dma_config->fifo_size, dma_config->fifo_buffer);
 }
 
-static void usart_rx_dma_interrupt_common(
-		struct usart_config const *config,
-		add_data_t add_data)
+static void usart_rx_dma_interrupt_common(struct usart_config const *config,
+					  add_data_t add_data)
 {
 	struct usart_rx_dma const *dma_config =
 		DOWNCAST(config->rx, struct usart_rx_dma const, usart_rx);
 
-	dma_chan_t *channel  = dma_get_channel(dma_config->channel);
-	size_t     new_index = dma_bytes_done(channel, dma_config->fifo_size);
-	size_t     old_index = dma_config->state->index;
-	size_t     new_bytes = 0;
-	size_t     added     = 0;
+	dma_chan_t *channel = dma_get_channel(dma_config->channel);
+	size_t new_index = dma_bytes_done(channel, dma_config->fifo_size);
+	size_t old_index = dma_config->state->index;
+	size_t new_bytes = 0;
+	size_t added = 0;
 
 	if (new_index > old_index) {
 		new_bytes = new_index - old_index;
 
-		added = add_data(config,
-				dma_config->fifo_buffer + old_index,
-				new_bytes);
+		added = add_data(config, dma_config->fifo_buffer + old_index,
+				 new_bytes);
 	} else if (new_index < old_index) {
 		/*
 		 * Handle the case where the received bytes are not contiguous
@@ -71,17 +67,14 @@ static void usart_rx_dma_interrupt_common(
 		 */
 		new_bytes = dma_config->fifo_size - (old_index - new_index);
 
-		added = add_data(config,
-				dma_config->fifo_buffer + old_index,
-				dma_config->fifo_size - old_index) +
-			add_data(config,
-				dma_config->fifo_buffer,
-				new_index);
+		added = add_data(config, dma_config->fifo_buffer + old_index,
+				 dma_config->fifo_size - old_index) +
+			add_data(config, dma_config->fifo_buffer, new_index);
 	} else {
 		/* (new_index == old_index): nothing to add to the queue. */
 	}
 
-	deprecated_atomic_add(&config->state->rx_dropped, new_bytes - added);
+	atomic_add((atomic_t *)&(config->state->rx_dropped), new_bytes - added);
 
 	if (dma_config->state->max_bytes < new_bytes)
 		dma_config->state->max_bytes = new_bytes;
@@ -89,8 +82,8 @@ static void usart_rx_dma_interrupt_common(
 	dma_config->state->index = new_index;
 }
 
-static size_t queue_add(struct usart_config const *config,
-			const uint8_t *src, size_t count)
+static size_t queue_add(struct usart_config const *config, const uint8_t *src,
+			size_t count)
 {
 	return queue_add_units(config->producer.queue, (void *)src, count);
 }
@@ -100,7 +93,6 @@ void usart_rx_dma_interrupt(struct usart_config const *config)
 	usart_rx_dma_interrupt_common(config, &queue_add);
 }
 
-
 #if defined(CONFIG_USART_HOST_COMMAND)
 void usart_host_command_rx_dma_interrupt(struct usart_config const *config)
 {
@@ -115,5 +107,5 @@ void usart_rx_dma_info(struct usart_config const *config)
 		DOWNCAST(config->rx, struct usart_rx_dma const, usart_rx);
 
 	ccprintf("    DMA RX max_bytes %d\n",
-		 deprecated_atomic_read_clear(&dma_config->state->max_bytes));
+		 (int)atomic_clear((atomic_t *)&dma_config->state->max_bytes));
 }
diff --git a/chip/stm32/usart_rx_dma.h b/chip/stm32/usart_rx_dma.h
index 064ab8046c..191ccc8c7f 100644
--- a/chip/stm32/usart_rx_dma.h
+++ b/chip/stm32/usart_rx_dma.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -7,8 +7,8 @@
 #ifndef __CROS_EC_USART_RX_DMA_H
 #define __CROS_EC_USART_RX_DMA_H
 
-#include "producer.h"
 #include "dma.h"
+#include "producer.h"
 #include "queue.h"
 #include "usart.h"
 
@@ -44,7 +44,7 @@
  * reasonable stress test the "DMA RX max_bytes" value will be a reasonable
  * size for the FIFO (perhaps +10% for safety).
  */
-#define USART_RX_DMA(CHANNEL, FIFO_SIZE)				\
+#define USART_RX_DMA(CHANNEL, FIFO_SIZE) \
 	((struct usart_rx_dma const) {					\
 		.usart_rx = {						\
 			.producer_ops = {				\
@@ -88,7 +88,7 @@ struct usart_rx_dma {
 	struct usart_rx_dma_state volatile *state;
 
 	uint8_t *fifo_buffer;
-	size_t  fifo_size;
+	size_t fifo_size;
 
 	enum dma_channel channel;
 };
diff --git a/chip/stm32/usart_rx_interrupt-stm32f0.c b/chip/stm32/usart_rx_interrupt-stm32f0.c
deleted file mode 120000
index a756455f9b..0000000000
--- a/chip/stm32/usart_rx_interrupt-stm32f0.c
+++ /dev/null
@@ -1 +0,0 @@
-usart_rx_interrupt.c
\ No newline at end of file
diff --git a/chip/stm32/usart_rx_interrupt-stm32f0.c b/chip/stm32/usart_rx_interrupt-stm32f0.c
new file mode 100644
index 0000000000..a142bcd436
--- /dev/null
+++ b/chip/stm32/usart_rx_interrupt-stm32f0.c
@@ -0,0 +1,48 @@
+/* Copyright 2014 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Interrupt based USART RX driver for STM32F0 and STM32F3 */
+
+#include "atomic.h"
+#include "common.h"
+#include "queue.h"
+#include "registers.h"
+#include "usart.h"
+
+static void usart_rx_init(struct usart_config const *config)
+{
+	intptr_t base = config->hw->base;
+
+	STM32_USART_CR1(base) |= STM32_USART_CR1_RXNEIE;
+	STM32_USART_CR1(base) |= STM32_USART_CR1_RE;
+	STM32_USART_CR3(base) |= STM32_USART_CR3_OVRDIS;
+}
+
+static void usart_rx_interrupt_handler(struct usart_config const *config)
+{
+	intptr_t base = config->hw->base;
+	int32_t status = STM32_USART_SR(base);
+
+	if (status & STM32_USART_SR_RXNE) {
+		uint8_t byte = STM32_USART_RDR(base);
+
+		if (!queue_add_unit(config->producer.queue, &byte))
+			atomic_add((atomic_t *)&(config->state->rx_dropped), 1);
+	}
+}
+
+struct usart_rx const usart_rx_interrupt = {
+	.producer_ops = {
+		/*
+		 * Nothing to do here, we either had enough space in the queue
+		 * when a character came in or we dropped it already.
+		 */
+		.read = NULL,
+	},
+
+	.init      = usart_rx_init,
+	.interrupt = usart_rx_interrupt_handler,
+	.info      = NULL,
+};
diff --git a/chip/stm32/usart_rx_interrupt-stm32f3.c b/chip/stm32/usart_rx_interrupt-stm32f3.c
deleted file mode 120000
index a756455f9b..0000000000
--- a/chip/stm32/usart_rx_interrupt-stm32f3.c
+++ /dev/null
@@ -1 +0,0 @@
-usart_rx_interrupt.c
\ No newline at end of file
diff --git a/chip/stm32/usart_rx_interrupt-stm32f3.c b/chip/stm32/usart_rx_interrupt-stm32f3.c
new file mode 100644
index 0000000000..a142bcd436
--- /dev/null
+++ b/chip/stm32/usart_rx_interrupt-stm32f3.c
@@ -0,0 +1,48 @@
+/* Copyright 2014 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Interrupt based USART RX driver for STM32F0 and STM32F3 */
+
+#include "atomic.h"
+#include "common.h"
+#include "queue.h"
+#include "registers.h"
+#include "usart.h"
+
+static void usart_rx_init(struct usart_config const *config)
+{
+	intptr_t base = config->hw->base;
+
+	STM32_USART_CR1(base) |= STM32_USART_CR1_RXNEIE;
+	STM32_USART_CR1(base) |= STM32_USART_CR1_RE;
+	STM32_USART_CR3(base) |= STM32_USART_CR3_OVRDIS;
+}
+
+static void usart_rx_interrupt_handler(struct usart_config const *config)
+{
+	intptr_t base = config->hw->base;
+	int32_t status = STM32_USART_SR(base);
+
+	if (status & STM32_USART_SR_RXNE) {
+		uint8_t byte = STM32_USART_RDR(base);
+
+		if (!queue_add_unit(config->producer.queue, &byte))
+			atomic_add((atomic_t *)&(config->state->rx_dropped), 1);
+	}
+}
+
+struct usart_rx const usart_rx_interrupt = {
+	.producer_ops = {
+		/*
+		 * Nothing to do here, we either had enough space in the queue
+		 * when a character came in or we dropped it already.
+		 */
+		.read = NULL,
+	},
+
+	.init      = usart_rx_init,
+	.interrupt = usart_rx_interrupt_handler,
+	.info      = NULL,
+};
diff --git a/chip/stm32/usart_rx_interrupt-stm32f4.c b/chip/stm32/usart_rx_interrupt-stm32f4.c
index 44e711327d..80ba37e88f 100644
--- a/chip/stm32/usart_rx_interrupt-stm32f4.c
+++ b/chip/stm32/usart_rx_interrupt-stm32f4.c
@@ -1,16 +1,15 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Interrupt based USART RX driver for STM32F0 and STM32F4 */
 
-#include "usart.h"
-
 #include "atomic.h"
 #include "common.h"
 #include "queue.h"
 #include "registers.h"
+#include "usart.h"
 
 static void usart_rx_init(struct usart_config const *config)
 {
@@ -26,14 +25,14 @@ static void usart_rx_init(struct usart_config const *config)
 
 static void usart_rx_interrupt_handler(struct usart_config const *config)
 {
-	intptr_t base   = config->hw->base;
-	int32_t  status = STM32_USART_SR(base);
+	intptr_t base = config->hw->base;
+	int32_t status = STM32_USART_SR(base);
 
 	if (status & STM32_USART_SR_RXNE) {
 		uint8_t byte = STM32_USART_RDR(base);
 
 		if (!queue_add_unit(config->producer.queue, &byte))
-			deprecated_atomic_add(&config->state->rx_dropped, 1);
+			atomic_add((atomic_t *)&(config->state->rx_dropped), 1);
 	}
 }
 
diff --git a/chip/stm32/usart_rx_interrupt-stm32l.c b/chip/stm32/usart_rx_interrupt-stm32l.c
index c0cd03d8c9..2c74d7dbd1 100644
--- a/chip/stm32/usart_rx_interrupt-stm32l.c
+++ b/chip/stm32/usart_rx_interrupt-stm32l.c
@@ -1,16 +1,15 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Interrupt based USART RX driver for STM32L */
 
-#include "usart.h"
-
 #include "atomic.h"
 #include "common.h"
 #include "queue.h"
 #include "registers.h"
+#include "usart.h"
 
 static void usart_rx_init(struct usart_config const *config)
 {
@@ -22,15 +21,32 @@ static void usart_rx_init(struct usart_config const *config)
 
 static void usart_rx_interrupt_handler(struct usart_config const *config)
 {
-	intptr_t base   = config->hw->base;
-	int32_t  status = STM32_USART_SR(base);
+	intptr_t base = config->hw->base;
+	int32_t status = STM32_USART_SR(base);
 
 	/*
 	 * We have to check and clear the overrun error flag on STM32L because
 	 * we can't disable it.
 	 */
 	if (status & STM32_USART_SR_ORE) {
+#ifdef STM32_USART_ICR_ORECF
+		/*
+		 * Newer series (STM32L4xx and STM32L5xx) have an explicit
+		 * "interrupt clear" register.
+		 *
+		 * ST reference code does blind write to this register, as is
+		 * usual with the "write 1 to clear" convention, despite the
+		 * datasheet listing the bits as "keep at reset value", (which
+		 * we assume is due to copying from the description of
+		 * reserved bits in read/write registers.)
+		 */
+		STM32_USART_ICR(config->hw->base) = STM32_USART_ICR_ORECF;
+#else
 		/*
+		 * On the older series STM32L1xx, the overrun bit is cleared
+		 * by a read of the status register, followed by a read of the
+		 * data register.
+		 *
 		 * In the unlikely event that the overrun error bit was set but
 		 * the RXNE bit was not (possibly because a read was done from
 		 * RDR without first reading the status register) we do a read
@@ -38,15 +54,16 @@ static void usart_rx_interrupt_handler(struct usart_config const *config)
 		 */
 		if (!(status & STM32_USART_SR_RXNE))
 			(void)STM32_USART_RDR(config->hw->base);
+#endif
 
-		deprecated_atomic_add(&config->state->rx_overrun, 1);
+		atomic_add((atomic_t *)&(config->state->rx_overrun), 1);
 	}
 
 	if (status & STM32_USART_SR_RXNE) {
 		uint8_t byte = STM32_USART_RDR(base);
 
 		if (!queue_add_unit(config->producer.queue, &byte))
-			deprecated_atomic_add(&config->state->rx_dropped, 1);
+			atomic_add((atomic_t *)&(config->state->rx_dropped), 1);
 	}
 }
 
diff --git a/chip/stm32/usart_rx_interrupt-stm32l5.c b/chip/stm32/usart_rx_interrupt-stm32l5.c
new file mode 100644
index 0000000000..45c2ecca9f
--- /dev/null
+++ b/chip/stm32/usart_rx_interrupt-stm32l5.c
@@ -0,0 +1,6 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "usart_rx_interrupt-stm32l.c"
diff --git a/chip/stm32/usart_rx_interrupt.c b/chip/stm32/usart_rx_interrupt.c
index 3cbf1f49f4..a142bcd436 100644
--- a/chip/stm32/usart_rx_interrupt.c
+++ b/chip/stm32/usart_rx_interrupt.c
@@ -1,16 +1,15 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Interrupt based USART RX driver for STM32F0 and STM32F3 */
 
-#include "usart.h"
-
 #include "atomic.h"
 #include "common.h"
 #include "queue.h"
 #include "registers.h"
+#include "usart.h"
 
 static void usart_rx_init(struct usart_config const *config)
 {
@@ -23,14 +22,14 @@ static void usart_rx_init(struct usart_config const *config)
 
 static void usart_rx_interrupt_handler(struct usart_config const *config)
 {
-	intptr_t base   = config->hw->base;
-	int32_t  status = STM32_USART_SR(base);
+	intptr_t base = config->hw->base;
+	int32_t status = STM32_USART_SR(base);
 
 	if (status & STM32_USART_SR_RXNE) {
 		uint8_t byte = STM32_USART_RDR(base);
 
 		if (!queue_add_unit(config->producer.queue, &byte))
-			deprecated_atomic_add(&config->state->rx_dropped, 1);
+			atomic_add((atomic_t *)&(config->state->rx_dropped), 1);
 	}
 }
 
diff --git a/chip/stm32/usart_tx_dma.c b/chip/stm32/usart_tx_dma.c
index 0c8e2c73d6..d6469aa9e6 100644
--- a/chip/stm32/usart_tx_dma.c
+++ b/chip/stm32/usart_tx_dma.c
@@ -1,14 +1,13 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
-#include "usart_tx_dma.h"
-
-#include "usart.h"
 #include "common.h"
 #include "registers.h"
 #include "system.h"
 #include "task.h"
+#include "usart.h"
+#include "usart_tx_dma.h"
 #include "util.h"
 
 void usart_tx_dma_written(struct consumer const *consumer, size_t count)
@@ -36,13 +35,13 @@ static void usart_tx_dma_start(struct usart_config const *config,
 			       struct usart_tx_dma const *dma_config)
 {
 	struct usart_tx_dma_state volatile *state = dma_config->state;
-	intptr_t                           base   = config->hw->base;
+	intptr_t base = config->hw->base;
 
 	struct dma_option options = {
 		.channel = dma_config->channel,
-		.periph  = (void *)&STM32_USART_TDR(base),
-		.flags   = (STM32_DMA_CCR_MSIZE_8_BIT |
-			    STM32_DMA_CCR_PSIZE_8_BIT),
+		.periph = (void *)&STM32_USART_TDR(base),
+		.flags =
+			(STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT),
 	};
 
 	/*
diff --git a/chip/stm32/usart_tx_dma.h b/chip/stm32/usart_tx_dma.h
index c17164e04a..f1028e3a9e 100644
--- a/chip/stm32/usart_tx_dma.h
+++ b/chip/stm32/usart_tx_dma.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -29,7 +29,7 @@
  * required because the queue isn't notified that it has been read from until
  * after the DMA transfer completes.
  */
-#define USART_TX_DMA(CHANNEL, MAX_BYTES)			\
+#define USART_TX_DMA(CHANNEL, MAX_BYTES) \
 	((struct usart_tx_dma const) {				\
 		.usart_tx = {					\
 			.consumer_ops = {			\
diff --git a/chip/stm32/usart_tx_interrupt.c b/chip/stm32/usart_tx_interrupt.c
index 6a6aaf65f7..7c99840e26 100644
--- a/chip/stm32/usart_tx_interrupt.c
+++ b/chip/stm32/usart_tx_interrupt.c
@@ -1,16 +1,15 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Interrupt based USART TX driver for STM32 */
 
-#include "usart.h"
-
 #include "common.h"
 #include "registers.h"
 #include "system.h"
 #include "task.h"
+#include "usart.h"
 #include "usart_host_command.h"
 #include "util.h"
 
@@ -37,12 +36,11 @@ static void usart_written(struct consumer const *consumer, size_t count)
 		STM32_USART_CR1(config->hw->base) |= STM32_USART_CR1_TXEIE;
 }
 
-static void usart_tx_interrupt_handler_common(
-		struct usart_config const *config,
-		remove_data_t remove_data)
+static void usart_tx_interrupt_handler_common(struct usart_config const *config,
+					      remove_data_t remove_data)
 {
 	intptr_t base = config->hw->base;
-	uint8_t  byte;
+	uint8_t byte;
 
 	if (!(STM32_USART_SR(base) & STM32_USART_SR_TXE))
 		return;
@@ -73,7 +71,7 @@ static void usart_tx_interrupt_handler_common(
 
 static size_t queue_remove(struct usart_config const *config, uint8_t *dest)
 {
-	return queue_remove_unit(config->producer.queue, (void *) dest);
+	return queue_remove_unit(config->consumer.queue, (void *)dest);
 }
 
 static void usart_tx_interrupt_handler(struct usart_config const *config)
@@ -107,11 +105,11 @@ struct usart_tx const usart_tx_interrupt = {
 
 #if defined(CONFIG_USART_HOST_COMMAND)
 
-static void usart_host_command_tx_interrupt_handler(
-		struct usart_config const *config)
+static void
+usart_host_command_tx_interrupt_handler(struct usart_config const *config)
 {
 	usart_tx_interrupt_handler_common(config,
-		&usart_host_command_tx_remove_data);
+					  &usart_host_command_tx_remove_data);
 }
 
 struct usart_tx const usart_host_command_tx_interrupt = {
diff --git a/chip/stm32/usb-stm32f0.c b/chip/stm32/usb-stm32f0.c
index 08c0a17455..227842f549 100644
--- a/chip/stm32/usb-stm32f0.c
+++ b/chip/stm32/usb-stm32f0.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/chip/stm32/usb-stm32f3.c b/chip/stm32/usb-stm32f3.c
index 2376d00b41..bef15db566 100644
--- a/chip/stm32/usb-stm32f3.c
+++ b/chip/stm32/usb-stm32f3.c
@@ -1,13 +1,12 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * STM32F3 Family specific USB functionality
  */
 
-#include "usb-stm32f3.h"
-
 #include "system.h"
+#include "usb-stm32f3.h"
 #include "usb_api.h"
 
 void usb_connect(void)
diff --git a/chip/stm32/usb-stm32f3.h b/chip/stm32/usb-stm32f3.h
index 196c43a53a..62921fe491 100644
--- a/chip/stm32/usb-stm32f3.h
+++ b/chip/stm32/usb-stm32f3.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/chip/stm32/usb-stm32g4.c b/chip/stm32/usb-stm32g4.c
new file mode 100644
index 0000000000..acd758584b
--- /dev/null
+++ b/chip/stm32/usb-stm32g4.c
@@ -0,0 +1,27 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * STM32G4 Family specific USB functionality
+ */
+
+#include "registers.h"
+#include "system.h"
+#include "usb_api.h"
+
+void usb_connect(void)
+{
+	/* USB is in use */
+	disable_sleep(SLEEP_MASK_USB_DEVICE);
+
+	STM32_USB_BCDR |= STM32_USB_BCDR_DPPU;
+}
+
+void usb_disconnect(void)
+{
+	/* disable pull-up on DP to disconnect */
+	STM32_USB_BCDR &= ~STM32_USB_BCDR_DPPU;
+
+	/* USB is off, so sleep whenever */
+	enable_sleep(SLEEP_MASK_USB_DEVICE);
+}
diff --git a/chip/stm32/usb-stm32l.c b/chip/stm32/usb-stm32l.c
index bb9838531b..3780dfed10 100644
--- a/chip/stm32/usb-stm32l.c
+++ b/chip/stm32/usb-stm32l.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/chip/stm32/usb-stm32l5.c b/chip/stm32/usb-stm32l5.c
new file mode 100644
index 0000000000..a286ab488e
--- /dev/null
+++ b/chip/stm32/usb-stm32l5.c
@@ -0,0 +1,25 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "registers.h"
+#include "system.h"
+#include "usb_api.h"
+
+void usb_connect(void)
+{
+	/* USB is in use */
+	disable_sleep(SLEEP_MASK_USB_DEVICE);
+
+	STM32_USB_BCDR |= STM32_USB_BCDR_DPPU;
+}
+
+void usb_disconnect(void)
+{
+	/* disable pull-up on DP to disconnect */
+	STM32_USB_BCDR &= ~STM32_USB_BCDR_DPPU;
+
+	/* USB is off, so sleep whenever */
+	enable_sleep(SLEEP_MASK_USB_DEVICE);
+}
diff --git a/chip/stm32/usb-stream.c b/chip/stm32/usb-stream.c
index 7429832f10..f9cd2687bf 100644
--- a/chip/stm32/usb-stream.c
+++ b/chip/stm32/usb-stream.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,10 +11,10 @@
 #include "registers.h"
 #include "task.h"
 #include "timer.h"
-#include "util.h"
 #include "usart.h"
-#include "usb_hw.h"
 #include "usb-stream.h"
+#include "usb_hw.h"
+#include "util.h"
 
 static size_t rx_read(struct usb_stream_config const *config)
 {
@@ -28,19 +28,16 @@ static size_t rx_read(struct usb_stream_config const *config)
 	if (count > queue_space(config->producer.queue))
 		return 0;
 
-	return queue_add_memcpy(config->producer.queue,
-				(void *) address,
-				count,
+	return queue_add_memcpy(config->producer.queue, (void *)address, count,
 				memcpy_from_usbram);
 }
 
 static size_t tx_write(struct usb_stream_config const *config)
 {
 	uintptr_t address = btable_ep[config->endpoint].tx_addr;
-	size_t    count   = queue_remove_memcpy(config->consumer.queue,
-						(void *) address,
-						config->tx_size,
-						memcpy_to_usbram);
+	size_t count = queue_remove_memcpy(config->consumer.queue,
+					   (void *)address, config->tx_size,
+					   memcpy_to_usbram);
 
 	btable_ep[config->endpoint].tx_count = count;
 
@@ -127,36 +124,33 @@ void usb_stream_event(struct usb_stream_config const *config,
 
 	i = config->endpoint;
 
-	btable_ep[i].tx_addr  = usb_sram_addr(config->tx_ram);
+	btable_ep[i].tx_addr = usb_sram_addr(config->tx_ram);
 	btable_ep[i].tx_count = 0;
 
-	btable_ep[i].rx_addr  = usb_sram_addr(config->rx_ram);
+	btable_ep[i].rx_addr = usb_sram_addr(config->rx_ram);
 	btable_ep[i].rx_count = usb_ep_rx_size(config->rx_size);
 
 	config->state->rx_waiting = 0;
 
-	STM32_USB_EP(i) = ((i <<  0) | /* Endpoint Addr*/
-			   (2 <<  4) | /* TX NAK */
-			   (0 <<  9) | /* Bulk EP */
+	STM32_USB_EP(i) = ((i << 0) | /* Endpoint Addr*/
+			   (2 << 4) | /* TX NAK */
+			   (0 << 9) | /* Bulk EP */
 			   (rx_disabled(config) ? EP_RX_NAK : EP_RX_VALID));
 }
 
 int usb_usart_interface(struct usb_stream_config const *config,
-			struct usart_config const *usart,
-			int interface,
+			struct usart_config const *usart, int interface,
 			usb_uint *rx_buf, usb_uint *tx_buf)
 {
 	struct usb_setup_packet req;
 
 	usb_read_setup_packet(rx_buf, &req);
 
-	if (req.bmRequestType != (USB_DIR_OUT |
-				  USB_TYPE_VENDOR |
-				  USB_RECIP_INTERFACE))
+	if (req.bmRequestType !=
+	    (USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_INTERFACE))
 		return -1;
 
-	if (req.wIndex  != interface ||
-	    req.wLength != 0)
+	if (req.wIndex != interface || req.wLength != 0)
 		return -1;
 
 	switch (req.bRequest) {
diff --git a/chip/stm32/usb-stream.h b/chip/stm32/usb-stream.h
index 915d8905cd..b22ee56620 100644
--- a/chip/stm32/usb-stream.h
+++ b/chip/stm32/usb-stream.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -118,32 +118,25 @@ extern struct producer_ops const usb_stream_producer_ops;
  * BUILD_ASSERT(RX_QUEUE.unit_bytes == 1);
  * BUILD_ASSERT(TX_QUEUE.unit_bytes == 1);
  */
-#define USB_STREAM_CONFIG_FULL(NAME,					\
-			       INTERFACE,				\
-			       INTERFACE_CLASS,				\
-			       INTERFACE_SUBCLASS,			\
-			       INTERFACE_PROTOCOL,			\
-			       INTERFACE_NAME,				\
-			       ENDPOINT,				\
-			       RX_SIZE,					\
-			       TX_SIZE,					\
-			       RX_QUEUE,				\
-			       TX_QUEUE)				\
-									\
-	BUILD_ASSERT(RX_SIZE <= USB_MAX_PACKET_SIZE);			\
-	BUILD_ASSERT(TX_SIZE <= USB_MAX_PACKET_SIZE);			\
-	BUILD_ASSERT(RX_SIZE > 0);					\
-	BUILD_ASSERT(TX_SIZE > 0);					\
-	BUILD_ASSERT((RX_SIZE <   64 && (RX_SIZE & 0x01) == 0) ||	\
-		     (RX_SIZE < 1024 && (RX_SIZE & 0x1f) == 0));	\
-	BUILD_ASSERT((TX_SIZE <   64 && (TX_SIZE & 0x01) == 0) ||	\
-		     (TX_SIZE < 1024 && (TX_SIZE & 0x1f) == 0));	\
-									\
-	static usb_uint CONCAT2(NAME, _ep_rx_buffer)[RX_SIZE / 2] __usb_ram; \
-	static usb_uint CONCAT2(NAME, _ep_tx_buffer)[TX_SIZE / 2] __usb_ram; \
-	static struct usb_stream_state CONCAT2(NAME, _state);		\
-	static void CONCAT2(NAME, _deferred_)(void);			\
-	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_));			\
+#define USB_STREAM_CONFIG_FULL(NAME, INTERFACE, INTERFACE_CLASS,               \
+			       INTERFACE_SUBCLASS, INTERFACE_PROTOCOL,         \
+			       INTERFACE_NAME, ENDPOINT, RX_SIZE, TX_SIZE,     \
+			       RX_QUEUE, TX_QUEUE)                             \
+                                                                               \
+	BUILD_ASSERT(RX_SIZE <= USB_MAX_PACKET_SIZE);                          \
+	BUILD_ASSERT(TX_SIZE <= USB_MAX_PACKET_SIZE);                          \
+	BUILD_ASSERT(RX_SIZE > 0);                                             \
+	BUILD_ASSERT(TX_SIZE > 0);                                             \
+	BUILD_ASSERT((RX_SIZE < 64 && (RX_SIZE & 0x01) == 0) ||                \
+		     (RX_SIZE < 1024 && (RX_SIZE & 0x1f) == 0));               \
+	BUILD_ASSERT((TX_SIZE < 64 && (TX_SIZE & 0x01) == 0) ||                \
+		     (TX_SIZE < 1024 && (TX_SIZE & 0x1f) == 0));               \
+                                                                               \
+	static usb_uint CONCAT2(NAME, _ep_rx_buffer)[RX_SIZE / 2] __usb_ram;   \
+	static usb_uint CONCAT2(NAME, _ep_tx_buffer)[TX_SIZE / 2] __usb_ram;   \
+	static struct usb_stream_state CONCAT2(NAME, _state);                  \
+	static void CONCAT2(NAME, _deferred_)(void);                           \
+	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_));                           \
 	struct usb_stream_config const NAME = {				\
 		.state     = &CONCAT2(NAME, _state),			\
 		.endpoint  = ENDPOINT,					\
@@ -160,107 +153,80 @@ extern struct producer_ops const usb_stream_producer_ops;
 			.queue = &RX_QUEUE,				\
 			.ops   = &usb_stream_producer_ops,		\
 		},							\
-	};								\
-	const struct usb_interface_descriptor				\
-	USB_IFACE_DESC(INTERFACE) = {					\
-		.bLength            = USB_DT_INTERFACE_SIZE,		\
-		.bDescriptorType    = USB_DT_INTERFACE,			\
-		.bInterfaceNumber   = INTERFACE,			\
-		.bAlternateSetting  = 0,				\
-		.bNumEndpoints      = 2,				\
-		.bInterfaceClass    = INTERFACE_CLASS,			\
-		.bInterfaceSubClass = INTERFACE_SUBCLASS,		\
-		.bInterfaceProtocol = INTERFACE_PROTOCOL,		\
-		.iInterface         = INTERFACE_NAME,			\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 0) = {					\
-		.bLength          = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = 0x80 | ENDPOINT,			\
-		.bmAttributes     = 0x02 /* Bulk IN */,			\
-		.wMaxPacketSize   = TX_SIZE,				\
-		.bInterval        = 10,					\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 1) = {					\
-		.bLength          = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = ENDPOINT,				\
-		.bmAttributes     = 0x02 /* Bulk OUT */,		\
-		.wMaxPacketSize   = RX_SIZE,				\
-		.bInterval        = 0,					\
-	};								\
-	static void CONCAT2(NAME, _ep_tx)(void)				\
-	{								\
-		usb_stream_tx(&NAME);					\
-	}								\
-	static void CONCAT2(NAME, _ep_rx)(void)				\
-	{								\
-		usb_stream_rx(&NAME);					\
-	}								\
-	static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt)	\
-	{								\
-		usb_stream_event(&NAME, evt);				\
-	}								\
-	USB_DECLARE_EP(ENDPOINT,					\
-		       CONCAT2(NAME, _ep_tx),				\
-		       CONCAT2(NAME, _ep_rx),				\
-		       CONCAT2(NAME, _ep_event));			\
-	static void CONCAT2(NAME, _deferred_)(void)			\
-	{ usb_stream_deferred(&NAME); }
+	};                           \
+	const struct usb_interface_descriptor USB_IFACE_DESC(INTERFACE) = {    \
+		.bLength = USB_DT_INTERFACE_SIZE,                              \
+		.bDescriptorType = USB_DT_INTERFACE,                           \
+		.bInterfaceNumber = INTERFACE,                                 \
+		.bAlternateSetting = 0,                                        \
+		.bNumEndpoints = 2,                                            \
+		.bInterfaceClass = INTERFACE_CLASS,                            \
+		.bInterfaceSubClass = INTERFACE_SUBCLASS,                      \
+		.bInterfaceProtocol = INTERFACE_PROTOCOL,                      \
+		.iInterface = INTERFACE_NAME,                                  \
+	};                                                                     \
+	const struct usb_endpoint_descriptor USB_EP_DESC(INTERFACE, 0) = {     \
+		.bLength = USB_DT_ENDPOINT_SIZE,                               \
+		.bDescriptorType = USB_DT_ENDPOINT,                            \
+		.bEndpointAddress = 0x80 | ENDPOINT,                           \
+		.bmAttributes = 0x02 /* Bulk IN */,                            \
+		.wMaxPacketSize = TX_SIZE,                                     \
+		.bInterval = 10,                                               \
+	};                                                                     \
+	const struct usb_endpoint_descriptor USB_EP_DESC(INTERFACE, 1) = {     \
+		.bLength = USB_DT_ENDPOINT_SIZE,                               \
+		.bDescriptorType = USB_DT_ENDPOINT,                            \
+		.bEndpointAddress = ENDPOINT,                                  \
+		.bmAttributes = 0x02 /* Bulk OUT */,                           \
+		.wMaxPacketSize = RX_SIZE,                                     \
+		.bInterval = 0,                                                \
+	};                                                                     \
+	static void CONCAT2(NAME, _ep_tx)(void)                                \
+	{                                                                      \
+		usb_stream_tx(&NAME);                                          \
+	}                                                                      \
+	static void CONCAT2(NAME, _ep_rx)(void)                                \
+	{                                                                      \
+		usb_stream_rx(&NAME);                                          \
+	}                                                                      \
+	static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt)            \
+	{                                                                      \
+		usb_stream_event(&NAME, evt);                                  \
+	}                                                                      \
+	USB_DECLARE_EP(ENDPOINT, CONCAT2(NAME, _ep_tx), CONCAT2(NAME, _ep_rx), \
+		       CONCAT2(NAME, _ep_event));                              \
+	static void CONCAT2(NAME, _deferred_)(void)                            \
+	{                                                                      \
+		usb_stream_deferred(&NAME);                                    \
+	}
 
 /* This is a short version for declaring Google serial endpoints */
-#define USB_STREAM_CONFIG(NAME,						\
-			  INTERFACE,					\
-			  INTERFACE_NAME,				\
-			  ENDPOINT,					\
-			  RX_SIZE,					\
-			  TX_SIZE,					\
-			  RX_QUEUE,					\
-			  TX_QUEUE)					\
-	USB_STREAM_CONFIG_FULL(NAME,					\
-			       INTERFACE,				\
-			       USB_CLASS_VENDOR_SPEC,			\
-			       USB_SUBCLASS_GOOGLE_SERIAL,		\
-			       USB_PROTOCOL_GOOGLE_SERIAL,		\
-			       INTERFACE_NAME,				\
-			       ENDPOINT,				\
-			       RX_SIZE,					\
-			       TX_SIZE,					\
-			       RX_QUEUE,				\
-			       TX_QUEUE)
+#define USB_STREAM_CONFIG(NAME, INTERFACE, INTERFACE_NAME, ENDPOINT, RX_SIZE, \
+			  TX_SIZE, RX_QUEUE, TX_QUEUE)                        \
+	USB_STREAM_CONFIG_FULL(NAME, INTERFACE, USB_CLASS_VENDOR_SPEC,        \
+			       USB_SUBCLASS_GOOGLE_SERIAL,                    \
+			       USB_PROTOCOL_GOOGLE_SERIAL, INTERFACE_NAME,    \
+			       ENDPOINT, RX_SIZE, TX_SIZE, RX_QUEUE, TX_QUEUE)
 
 /* Declare a utility interface for setting parity/baud. */
-#define USB_USART_IFACE(NAME, INTERFACE, USART_CFG)			\
-	static int CONCAT2(NAME,  _interface_)(usb_uint *rx_buf,	\
-					      usb_uint *tx_buf)		\
-	{ return usb_usart_interface(&NAME, &USART_CFG, INTERFACE,	\
-					rx_buf, tx_buf); }		\
-	USB_DECLARE_IFACE(INTERFACE,					\
-			  CONCAT2(NAME, _interface_))
+#define USB_USART_IFACE(NAME, INTERFACE, USART_CFG)                      \
+	static int CONCAT2(NAME, _interface_)(usb_uint * rx_buf,         \
+					      usb_uint * tx_buf)         \
+	{                                                                \
+		return usb_usart_interface(&NAME, &USART_CFG, INTERFACE, \
+					   rx_buf, tx_buf);              \
+	}                                                                \
+	USB_DECLARE_IFACE(INTERFACE, CONCAT2(NAME, _interface_))
 
 /* This is a medium version for declaring Google serial endpoints */
-#define USB_STREAM_CONFIG_USART_IFACE(NAME,				\
-				      INTERFACE,			\
-				      INTERFACE_NAME,			\
-				      ENDPOINT,				\
-				      RX_SIZE,				\
-				      TX_SIZE,				\
-				      RX_QUEUE,				\
-				      TX_QUEUE,				\
-				      USART_CFG)			\
-	USB_STREAM_CONFIG_FULL(NAME,					\
-			       INTERFACE,				\
-			       USB_CLASS_VENDOR_SPEC,			\
-			       USB_SUBCLASS_GOOGLE_SERIAL,		\
-			       USB_PROTOCOL_GOOGLE_SERIAL,		\
-			       INTERFACE_NAME,				\
-			       ENDPOINT,				\
-			       RX_SIZE,					\
-			       TX_SIZE,					\
-			       RX_QUEUE,				\
-			       TX_QUEUE);				\
+#define USB_STREAM_CONFIG_USART_IFACE(NAME, INTERFACE, INTERFACE_NAME,      \
+				      ENDPOINT, RX_SIZE, TX_SIZE, RX_QUEUE, \
+				      TX_QUEUE, USART_CFG)                  \
+	USB_STREAM_CONFIG_FULL(NAME, INTERFACE, USB_CLASS_VENDOR_SPEC,      \
+			       USB_SUBCLASS_GOOGLE_SERIAL,                  \
+			       USB_PROTOCOL_GOOGLE_SERIAL, INTERFACE_NAME,  \
+			       ENDPOINT, RX_SIZE, TX_SIZE, RX_QUEUE,        \
+			       TX_QUEUE);                                   \
 	USB_USART_IFACE(NAME, INTERFACE, USART_CFG)
 
 /*
@@ -285,8 +251,8 @@ enum usb_usart {
 #define USB_USART_BAUD_MULTIPLIER 100
 
 int usb_usart_interface(struct usb_stream_config const *config,
-		    struct usart_config const *usart,
-		    int interface, usb_uint *rx_buf, usb_uint *tx_buf);
+			struct usart_config const *usart, int interface,
+			usb_uint *rx_buf, usb_uint *tx_buf);
 
 /*
  * These functions are used by the trampoline functions defined above to
diff --git a/chip/stm32/usb.c b/chip/stm32/usb.c
index 1711480d53..06cf12cb5a 100644
--- a/chip/stm32/usb.c
+++ b/chip/stm32/usb.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,13 +15,13 @@
 #include "system.h"
 #include "task.h"
 #include "timer.h"
-#include "util.h"
 #include "usb_api.h"
 #include "usb_descriptor.h"
 #include "usb_hw.h"
+#include "util.h"
 
 /* Console output macro */
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args)
 
 #ifdef CONFIG_USB_BOS
 /* v2.10 (vs 2.00) BOS Descriptor provided */
@@ -55,7 +55,7 @@ static const struct usb_device_descriptor dev_desc = {
 	.bDeviceSubClass = 0x00,
 	.bDeviceProtocol = 0x00,
 	.bMaxPacketSize0 = USB_MAX_PACKET_SIZE,
-	.idVendor = USB_VID_GOOGLE,
+	.idVendor = CONFIG_USB_VID,
 	.idProduct = CONFIG_USB_PID,
 	.bcdDevice = CONFIG_USB_BCD_DEV,
 	.iManufacturer = USB_STR_VENDOR,
@@ -73,11 +73,11 @@ const struct usb_config_descriptor USB_CONF_DESC(conf) = {
 	.bConfigurationValue = 1,
 	.iConfiguration = USB_STR_VERSION,
 	.bmAttributes = 0x80 /* Reserved bit */
-#ifdef CONFIG_USB_SELF_POWERED  /* bus or self powered */
-		      | 0x40
+#ifdef CONFIG_USB_SELF_POWERED /* bus or self powered */
+			| 0x40
 #endif
 #ifdef CONFIG_USB_REMOTE_WAKEUP
-		      | 0x20
+			| 0x20
 #endif
 	,
 	.bMaxPower = (CONFIG_USB_MAXPOWER_MA / 2),
@@ -85,17 +85,47 @@ const struct usb_config_descriptor USB_CONF_DESC(conf) = {
 
 const uint8_t usb_string_desc[] = {
 	4, /* Descriptor size */
-	USB_DT_STRING,
-	0x09, 0x04 /* LangID = 0x0409: U.S. English */
+	USB_DT_STRING, 0x09, 0x04 /* LangID = 0x0409: U.S. English */
 };
 
+#ifdef CONFIG_USB_MS_EXTENDED_COMPAT_ID_DESCRIPTOR
+/*
+ * String descriptor for Windows Compatible ID OS Descriptor. This string
+ * descriptor is used by Windows OS to know to request a Windows Compatible ID
+ * OS Descriptor so that Windows will load the proper WINUSB driver.
+ */
+const void *const usb_ms_os_string_descriptor = { USB_MS_STRING_DESC(
+	"MSFT100") };
+
+/*
+ * Extended Compat ID OS Feature descriptor. This descriptor is used by Windows
+ * OS to know which type of driver is required so the USB-EP device gets
+ * registered properly. This type of descriptor may contain more than one
+ * function interface, but this instantiation only uses one function interface
+ * to communicate the WINUSB compatible ID.
+ */
+const struct usb_ms_ext_compat_id_desc winusb_desc = {
+	.dwLength = sizeof(struct usb_ms_ext_compat_id_desc),
+	.bcdVersion = 0x100, /* Windows Compat ID Desc v1.0 */
+	.wIndex = USB_MS_EXT_COMPATIBLE_ID_INDEX,
+	.bCount = USB_MS_COMPAT_ID_FUNCTION,
+	.function = {
+		[0] = {
+			.bFirstInterfaceNumber = 0,
+			.reserved_1 = 1,
+			.compatible_id = {USB_MS_COMPAT_ID}, /* WINUSB */
+		},
+	},
+};
+#endif
+
 /* Endpoint table in USB controller RAM */
 struct stm32_endpoint btable_ep[USB_EP_COUNT] __aligned(8) __usb_btable;
 /* Control endpoint (EP0) buffers */
 static usb_uint ep0_buf_tx[USB_MAX_PACKET_SIZE / 2] __usb_ram;
 static usb_uint ep0_buf_rx[USB_MAX_PACKET_SIZE / 2] __usb_ram;
 
-#define EP0_BUF_TX_SRAM_ADDR ((void *) usb_sram_addr(ep0_buf_tx))
+#define EP0_BUF_TX_SRAM_ADDR ((void *)usb_sram_addr(ep0_buf_tx))
 
 static int set_addr;
 /* remaining size of descriptor data to transfer */
@@ -112,10 +142,10 @@ static int remote_wakeup_enabled;
 void usb_read_setup_packet(usb_uint *buffer, struct usb_setup_packet *packet)
 {
 	packet->bmRequestType = buffer[0] & 0xff;
-	packet->bRequest      = buffer[0] >> 8;
-	packet->wValue        = buffer[1];
-	packet->wIndex        = buffer[2];
-	packet->wLength       = buffer[3];
+	packet->bRequest = buffer[0] >> 8;
+	packet->wValue = buffer[1];
+	packet->wIndex = buffer[2];
+	packet->wLength = buffer[3];
 }
 
 struct usb_descriptor_patch {
@@ -125,8 +155,8 @@ struct usb_descriptor_patch {
 
 static struct usb_descriptor_patch desc_patches[USB_DESC_PATCH_COUNT];
 
-void set_descriptor_patch(enum usb_desc_patch_type type,
-			  const void *address, uint16_t data)
+void set_descriptor_patch(enum usb_desc_patch_type type, const void *address,
+			  uint16_t data)
 {
 	desc_patches[type].address = address;
 	desc_patches[type].data = data;
@@ -146,7 +176,8 @@ void *memcpy_to_usbram_ep0_patch(const void *src, size_t n)
 			continue;
 
 		memcpy_to_usbram((void *)(usb_sram_addr(ep0_buf_tx) + offset),
-			&desc_patches[i].data, sizeof(desc_patches[i].data));
+				 &desc_patches[i].data,
+				 sizeof(desc_patches[i].data));
 	}
 
 	return ret;
@@ -200,17 +231,30 @@ static void ep0_rx(void)
 	}
 	/* vendor specific request */
 	if ((req & USB_TYPE_MASK) == USB_TYPE_VENDOR) {
-#ifdef CONFIG_WEBUSB_URL
+#if defined(CONFIG_WEBUSB_URL) || \
+	defined(CONFIG_USB_MS_EXTENDED_COMPAT_ID_DESCRIPTOR)
 		uint8_t b_req = req >> 8; /* bRequest in the transfer */
-		uint16_t idx = ep0_buf_rx[2]; /* wIndex in the transfer */
+		uint16_t w_index = ep0_buf_rx[2]; /* wIndex in the transfer */
 
-		if (b_req == 0x01 && idx == WEBUSB_REQ_GET_URL) {
+#ifdef CONFIG_WEBUSB_URL
+		if (b_req == 0x01 && w_index == WEBUSB_REQ_GET_URL) {
 			int len = *(uint8_t *)webusb_url;
 
 			ep0_send_descriptor(webusb_url, len, 0);
 			return;
 		}
-#endif
+#endif /* CONFIG_WEBUSB_URL */
+
+#ifdef CONFIG_USB_MS_EXTENDED_COMPAT_ID_DESCRIPTOR
+		if (b_req == USB_MS_STRING_DESC_VENDOR_CODE &&
+		    w_index == USB_MS_EXT_COMPATIBLE_ID_INDEX) {
+			ep0_send_descriptor((uint8_t *)&winusb_desc,
+					    winusb_desc.dwLength, 0);
+			return;
+		}
+#endif /* CONFIG_USB_MS_EXTENDED_COMPAT_ID_DESCRIPTOR */
+
+#endif /* CONFIG_WEBUSB_URL || CONFIG_USB_MS_EXTENDED_COMPAT_ID_DESCRIPTOR */
 		goto unknown_req;
 	}
 
@@ -237,6 +281,19 @@ static void ep0_rx(void)
 			break;
 #endif
 		case USB_DT_STRING: /* Setup : Get string descriptor */
+
+#ifdef CONFIG_USB_MS_EXTENDED_COMPAT_ID_DESCRIPTOR
+			/*
+			 * String descriptor request at index == 0xEE is used by
+			 * Windows OS to know how to retrieve an Extended Compat
+			 * ID OS Feature descriptor.
+			 */
+			if (idx == USB_GET_MS_DESCRIPTOR) {
+				desc = (uint8_t *)usb_ms_os_string_descriptor;
+				len = desc[0];
+				break;
+			}
+#endif
 			if (idx >= USB_STR_COUNT)
 				/* The string does not exist : STALL */
 				goto unknown_req;
@@ -254,8 +311,9 @@ static void ep0_rx(void)
 		default: /* unhandled descriptor */
 			goto unknown_req;
 		}
-		ep0_send_descriptor(desc, len, type == USB_DT_CONFIGURATION ?
-						USB_DESC_SIZE : 0);
+		ep0_send_descriptor(
+			desc, len,
+			type == USB_DT_CONFIGURATION ? USB_DESC_SIZE : 0);
 	} else if (req == (USB_DIR_IN | (USB_REQ_GET_STATUS << 8))) {
 		uint16_t data = 0;
 		/* Get status */
@@ -269,14 +327,14 @@ static void ep0_rx(void)
 		memcpy_to_usbram(EP0_BUF_TX_SRAM_ADDR, (void *)&data, 2);
 		btable_ep[0].tx_count = 2;
 		STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID,
-			  EP_STATUS_OUT /*null OUT transaction */);
+				EP_STATUS_OUT /*null OUT transaction */);
 	} else if ((req & 0xff) == USB_DIR_OUT) {
 		switch (req >> 8) {
 		case USB_REQ_SET_FEATURE:
 		case USB_REQ_CLEAR_FEATURE:
 #ifdef CONFIG_USB_REMOTE_WAKEUP
 			if (ep0_buf_rx[1] ==
-					USB_REQ_FEATURE_DEVICE_REMOTE_WAKEUP) {
+			    USB_REQ_FEATURE_DEVICE_REMOTE_WAKEUP) {
 				remote_wakeup_enabled =
 					((req >> 8) == USB_REQ_SET_FEATURE);
 				btable_ep[0].tx_count = 0;
@@ -351,13 +409,12 @@ static void ep0_event(enum usb_ep_event evt)
 	if (evt != USB_EVENT_RESET)
 		return;
 
-	STM32_USB_EP(0) = BIT(9) /* control EP */ |
-			  (2 << 4) /* TX NAK */ |
+	STM32_USB_EP(0) = BIT(9) /* control EP */ | (2 << 4) /* TX NAK */ |
 			  (3 << 12) /* RX VALID */;
 
 	btable_ep[0].tx_addr = usb_sram_addr(ep0_buf_tx);
 	btable_ep[0].rx_addr = usb_sram_addr(ep0_buf_rx);
-	btable_ep[0].rx_count = 0x8000 | ((USB_MAX_PACKET_SIZE/32-1) << 10);
+	btable_ep[0].rx_count = 0x8000 | ((USB_MAX_PACKET_SIZE / 32 - 1) << 10);
 	btable_ep[0].tx_count = 0;
 }
 USB_DECLARE_EP(0, ep0_tx, ep0_rx, ep0_event);
@@ -401,7 +458,9 @@ static void usb_suspend(void)
 	STM32_USB_CNTR |= STM32_USB_CNTR_LP_MODE;
 	interrupt_enable();
 
+#if !defined(CHIP_FAMILY_STM32F0)
 	clock_enable_module(MODULE_USB, 0);
+#endif
 
 	/* USB is not in use anymore, we can (hopefully) sleep now. */
 	enable_sleep(SLEEP_MASK_USB_DEVICE);
@@ -417,8 +476,8 @@ static volatile int sof_received;
 
 static void usb_resume_deferred(void)
 {
-	uint32_t state = (STM32_USB_FNR & STM32_USB_FNR_RXDP_RXDM_MASK)
-		>> STM32_USB_FNR_RXDP_RXDM_SHIFT;
+	uint32_t state = (STM32_USB_FNR & STM32_USB_FNR_RXDP_RXDM_MASK) >>
+			 STM32_USB_FNR_RXDP_RXDM_SHIFT;
 
 	CPRINTF("RSMd %d %04x %d\n", state, STM32_USB_CNTR, sof_received);
 	if (sof_received == 0 && (state == 2 || state == 3))
@@ -432,7 +491,9 @@ static void usb_resume(void)
 {
 	uint32_t state;
 
+#if !defined(CHIP_FAMILY_STM32F0)
 	clock_enable_module(MODULE_USB, 1);
+#endif
 
 	/* Clear FSUSP bit to exit suspend mode */
 	STM32_USB_CNTR &= ~STM32_USB_CNTR_FSUSP;
@@ -440,8 +501,8 @@ static void usb_resume(void)
 	/* USB is in use again */
 	disable_sleep(SLEEP_MASK_USB_DEVICE);
 
-	state = (STM32_USB_FNR & STM32_USB_FNR_RXDP_RXDM_MASK)
-		>> STM32_USB_FNR_RXDP_RXDM_SHIFT;
+	state = (STM32_USB_FNR & STM32_USB_FNR_RXDP_RXDM_MASK) >>
+		STM32_USB_FNR_RXDP_RXDM_SHIFT;
 
 	CPRINTF("RSM %d %04x\n", state, STM32_USB_CNTR);
 
@@ -478,8 +539,7 @@ static volatile int usb_wake_done = 1;
  */
 static volatile int esof_count;
 
-__attribute__((weak))
-void board_usb_wake(void)
+__attribute__((weak)) void board_usb_wake(void)
 {
 	/* Side-band USB wake, do nothing by default. */
 }
@@ -498,8 +558,13 @@ static void usb_wake_deferred(void)
 		 * interface.
 		 */
 		CPRINTF("USB stuck\n");
+#if defined(STM32_RCC_APB1RSTR2_USBFSRST)
+		STM32_RCC_APB1RSTR2 |= STM32_RCC_APB1RSTR2_USBFSRST;
+		STM32_RCC_APB1RSTR2 &= STM32_RCC_APB1RSTR2_USBFSRST;
+#else
 		STM32_RCC_APB1RSTR |= STM32_RCC_PB1_USB;
 		STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_USB;
+#endif
 		usb_init();
 	}
 }
@@ -517,7 +582,7 @@ void usb_wake(void)
 	}
 
 	/* Only allow one caller at a time. */
-	if (!deprecated_atomic_read_clear(&usb_wake_done))
+	if (!atomic_clear((atomic_t *)&usb_wake_done))
 		return;
 
 	CPRINTF("WAKE\n");
@@ -537,8 +602,8 @@ void usb_wake(void)
 
 	/* STM32_USB_CNTR can also be updated from interrupt context. */
 	interrupt_disable();
-	STM32_USB_CNTR |= STM32_USB_CNTR_RESUME |
-		STM32_USB_CNTR_ESOFM | STM32_USB_CNTR_SOFM;
+	STM32_USB_CNTR |= STM32_USB_CNTR_RESUME | STM32_USB_CNTR_ESOFM |
+			  STM32_USB_CNTR_SOFM;
 	interrupt_enable();
 
 	/* Try side-band wake as well. */
@@ -593,8 +658,8 @@ static void usb_interrupt_handle_wake(uint16_t status)
 		STM32_USB_CNTR &= ~STM32_USB_CNTR_RESUME;
 
 	/* Then count down until state is resumed. */
-	state = (STM32_USB_FNR & STM32_USB_FNR_RXDP_RXDM_MASK)
-				>> STM32_USB_FNR_RXDP_RXDM_SHIFT;
+	state = (STM32_USB_FNR & STM32_USB_FNR_RXDP_RXDM_MASK) >>
+		STM32_USB_FNR_RXDP_RXDM_SHIFT;
 
 	/*
 	 * state 2, or receiving an SOF, means resume
@@ -609,13 +674,13 @@ static void usb_interrupt_handle_wake(uint16_t status)
 		STM32_USB_CNTR &= ~STM32_USB_CNTR_ESOFM;
 		usb_wake_done = 1;
 		if (!good) {
-			CPRINTF("wake error: cnt=%d state=%d\n",
-				esof_count, state);
+			CPRINTF("wake error: cnt=%d state=%d\n", esof_count,
+				state);
 			usb_suspend();
 			return;
 		}
 
-		CPRINTF("RSMOK%d %d\n",	-esof_count, state);
+		CPRINTF("RSMOK%d %d\n", -esof_count, state);
 
 		for (ep = 1; ep < USB_EP_COUNT; ep++)
 			usb_ep_event[ep](USB_EVENT_DEVICE_RESUME);
@@ -623,7 +688,7 @@ static void usb_interrupt_handle_wake(uint16_t status)
 }
 #endif /* CONFIG_USB_SUSPEND && CONFIG_USB_REMOTE_WAKEUP */
 
-void usb_interrupt(void)
+static void usb_interrupt(void)
 {
 	uint16_t status = STM32_USB_ISTR;
 
@@ -642,7 +707,7 @@ void usb_interrupt(void)
 
 #ifdef CONFIG_USB_REMOTE_WAKEUP
 	if (status & (STM32_USB_ISTR_ESOF | STM32_USB_ISTR_SOF) &&
-			!usb_wake_done)
+	    !usb_wake_done)
 		usb_interrupt_handle_wake(status);
 #endif
 
@@ -672,10 +737,7 @@ DECLARE_IRQ(STM32_IRQ_USB_LP, usb_interrupt, 1);
 
 void usb_init(void)
 {
-	/* Enable USB device clock. */
-	STM32_RCC_APB1ENR |= STM32_RCC_PB1_USB;
-
-	/* we need a proper 48MHz clock */
+	/* Enable USB device clock, possibly increasing system clock to 48MHz */
 	clock_enable_module(MODULE_USB, 1);
 
 	/* configure the pinmux */
@@ -701,12 +763,10 @@ void usb_init(void)
 	/* Enable interrupt handlers */
 	task_enable_irq(STM32_IRQ_USB_LP);
 	/* set interrupts mask : reset/correct transfer/errors */
-	STM32_USB_CNTR = STM32_USB_CNTR_CTRM |
-			 STM32_USB_CNTR_PMAOVRM |
+	STM32_USB_CNTR = STM32_USB_CNTR_CTRM | STM32_USB_CNTR_PMAOVRM |
 			 STM32_USB_CNTR_ERRM |
 #ifdef CONFIG_USB_SUSPEND
-			 STM32_USB_CNTR_WKUPM |
-			 STM32_USB_CNTR_SUSPM |
+			 STM32_USB_CNTR_WKUPM | STM32_USB_CNTR_SUSPM |
 #endif
 			 STM32_USB_CNTR_RESETM;
 
@@ -738,26 +798,23 @@ void usb_release(void)
 	/* unset pinmux */
 	gpio_config_module(MODULE_USB, 0);
 
-	/* disable 48MHz clock */
+	/* disable USB device clock, possibly slowing down system clock */
 	clock_enable_module(MODULE_USB, 0);
-
-	/* disable USB device clock */
-	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_USB;
 }
 /* ensure the host disconnects and reconnects over a sysjump */
 DECLARE_HOOK(HOOK_SYSJUMP, usb_release, HOOK_PRIO_DEFAULT);
 
 int usb_is_enabled(void)
 {
-	return (STM32_RCC_APB1ENR & STM32_RCC_PB1_USB) ? 1 : 0;
+	return clock_is_module_enabled(MODULE_USB);
 }
 
 void *memcpy_to_usbram(void *dest, const void *src, size_t n)
 {
-	int       unaligned =                 (((uintptr_t) dest) & 1);
-	usb_uint *d         = &__usb_ram_start[((uintptr_t) dest) / 2];
-	uint8_t  *s         = (uint8_t *) src;
-	int       i;
+	int unaligned = (((uintptr_t)dest) & 1);
+	usb_uint *d = &__usb_ram_start[((uintptr_t)dest) / 2];
+	uint8_t *s = (uint8_t *)src;
+	int i;
 
 	/*
 	 * Handle unaligned leading byte via read/modify/write.
@@ -784,10 +841,10 @@ void *memcpy_to_usbram(void *dest, const void *src, size_t n)
 
 void *memcpy_from_usbram(void *dest, const void *src, size_t n)
 {
-	int             unaligned =                 (((uintptr_t) src) & 1);
-	usb_uint const *s         = &__usb_ram_start[((uintptr_t) src) / 2];
-	uint8_t        *d         = (uint8_t *) dest;
-	int             i;
+	int unaligned = (((uintptr_t)src) & 1);
+	usb_uint const *s = &__usb_ram_start[((uintptr_t)src) / 2];
+	uint8_t *d = (uint8_t *)dest;
+	int i;
 
 	if (unaligned && n) {
 		*d = *s >> 8;
@@ -868,7 +925,7 @@ static int usb_save_serial(const char *serialno)
 	return rv;
 }
 
-static int command_serialno(int argc, char **argv)
+static int command_serialno(int argc, const char **argv)
 {
 	struct usb_string_desc *sd = usb_serialno_desc;
 	char buf[CONFIG_SERIALNO_LEN];
@@ -876,12 +933,10 @@ static int command_serialno(int argc, char **argv)
 	int i;
 
 	if (argc != 1) {
-		if ((strcasecmp(argv[1], "set") == 0) &&
-		    (argc == 3)) {
+		if ((strcasecmp(argv[1], "set") == 0) && (argc == 3)) {
 			ccprintf("Saving serial number\n");
 			rv = usb_save_serial(argv[2]);
-		} else if ((strcasecmp(argv[1], "load") == 0) &&
-			   (argc == 2)) {
+		} else if ((strcasecmp(argv[1], "load") == 0) && (argc == 2)) {
 			ccprintf("Loading serial number\n");
 			rv = usb_load_serial();
 		} else
@@ -894,11 +949,10 @@ static int command_serialno(int argc, char **argv)
 	return rv;
 }
 
-DECLARE_CONSOLE_COMMAND(serialno, command_serialno,
-	"load/set [value]",
-	"Read and write USB serial number");
+DECLARE_CONSOLE_COMMAND(serialno, command_serialno, "load/set [value]",
+			"Read and write USB serial number");
 
-#endif  /* CONFIG_USB_SERIALNO */
+#endif /* CONFIG_USB_SERIALNO */
 
 #ifdef CONFIG_MAC_ADDR
 
@@ -925,18 +979,16 @@ static int usb_save_mac_addr(const char *mac_addr)
 	}
 }
 
-static int command_macaddr(int argc, char **argv)
+static int command_macaddr(int argc, const char **argv)
 {
-	const char* buf;
+	const char *buf;
 	int rv = EC_SUCCESS;
 
 	if (argc != 1) {
-		if ((strcasecmp(argv[1], "set") == 0) &&
-		    (argc == 3)) {
+		if ((strcasecmp(argv[1], "set") == 0) && (argc == 3)) {
 			ccprintf("Saving MAC address\n");
 			rv = usb_save_mac_addr(argv[2]);
-		} else if ((strcasecmp(argv[1], "load") == 0) &&
-			   (argc == 2)) {
+		} else if ((strcasecmp(argv[1], "load") == 0) && (argc == 2)) {
 			ccprintf("Loading MAC address\n");
 		} else {
 			return EC_ERROR_INVAL;
@@ -951,8 +1003,7 @@ static int command_macaddr(int argc, char **argv)
 	return rv;
 }
 
-DECLARE_CONSOLE_COMMAND(macaddr, command_macaddr,
-	"load/set [value]",
-	"Read and write MAC address");
+DECLARE_CONSOLE_COMMAND(macaddr, command_macaddr, "load/set [value]",
+			"Read and write MAC address");
 
-#endif  /* CONFIG_MAC_ADDR */
+#endif /* CONFIG_MAC_ADDR */
diff --git a/chip/stm32/usb_console.c b/chip/stm32/usb_console.c
index b5666c8fbf..062ce2f484 100644
--- a/chip/stm32/usb_console.c
+++ b/chip/stm32/usb_console.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,17 +12,17 @@
 #include "registers.h"
 #include "task.h"
 #include "timer.h"
-#include "util.h"
 #include "usb_api.h"
 #include "usb_descriptor.h"
 #include "usb_hw.h"
+#include "util.h"
 
 /* Console output macro */
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args)
 #define USB_CONSOLE_TIMEOUT_US (30 * MSEC)
 
-static struct queue const tx_q = QUEUE_NULL(CONFIG_USB_CONSOLE_TX_BUF_SIZE,
-					    uint8_t);
+static struct queue const tx_q =
+	QUEUE_NULL(CONFIG_USB_CONSOLE_TX_BUF_SIZE, uint8_t);
 static struct queue const rx_q = QUEUE_NULL(USB_MAX_PACKET_SIZE, uint8_t);
 
 static int last_tx_ok = 1;
@@ -33,31 +33,31 @@ static int is_readonly;
 
 /* USB-Serial descriptors */
 const struct usb_interface_descriptor USB_IFACE_DESC(USB_IFACE_CONSOLE) = {
-	.bLength            = USB_DT_INTERFACE_SIZE,
-	.bDescriptorType    = USB_DT_INTERFACE,
-	.bInterfaceNumber   = USB_IFACE_CONSOLE,
-	.bAlternateSetting  = 0,
-	.bNumEndpoints      = 2,
-	.bInterfaceClass    = USB_CLASS_VENDOR_SPEC,
+	.bLength = USB_DT_INTERFACE_SIZE,
+	.bDescriptorType = USB_DT_INTERFACE,
+	.bInterfaceNumber = USB_IFACE_CONSOLE,
+	.bAlternateSetting = 0,
+	.bNumEndpoints = 2,
+	.bInterfaceClass = USB_CLASS_VENDOR_SPEC,
 	.bInterfaceSubClass = USB_SUBCLASS_GOOGLE_SERIAL,
 	.bInterfaceProtocol = USB_PROTOCOL_GOOGLE_SERIAL,
-	.iInterface         = USB_STR_CONSOLE_NAME,
+	.iInterface = USB_STR_CONSOLE_NAME,
 };
 const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_CONSOLE, 0) = {
-	.bLength            = USB_DT_ENDPOINT_SIZE,
-	.bDescriptorType    = USB_DT_ENDPOINT,
-	.bEndpointAddress   = 0x80 | USB_EP_CONSOLE,
-	.bmAttributes       = 0x02 /* Bulk IN */,
-	.wMaxPacketSize     = USB_MAX_PACKET_SIZE,
-	.bInterval          = 10
+	.bLength = USB_DT_ENDPOINT_SIZE,
+	.bDescriptorType = USB_DT_ENDPOINT,
+	.bEndpointAddress = 0x80 | USB_EP_CONSOLE,
+	.bmAttributes = 0x02 /* Bulk IN */,
+	.wMaxPacketSize = USB_MAX_PACKET_SIZE,
+	.bInterval = 10
 };
 const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_CONSOLE, 1) = {
-	.bLength            = USB_DT_ENDPOINT_SIZE,
-	.bDescriptorType    = USB_DT_ENDPOINT,
-	.bEndpointAddress   = USB_EP_CONSOLE,
-	.bmAttributes       = 0x02 /* Bulk OUT */,
-	.wMaxPacketSize     = USB_MAX_PACKET_SIZE,
-	.bInterval          = 0
+	.bLength = USB_DT_ENDPOINT_SIZE,
+	.bDescriptorType = USB_DT_ENDPOINT,
+	.bEndpointAddress = USB_EP_CONSOLE,
+	.bmAttributes = 0x02 /* Bulk OUT */,
+	.wMaxPacketSize = USB_MAX_PACKET_SIZE,
+	.bInterval = 0
 };
 
 static usb_uint ep_buf_tx[USB_MAX_PACKET_SIZE / 2] __usb_ram;
@@ -81,9 +81,8 @@ static void con_ep_rx(void)
 
 	for (i = 0; i < (btable_ep[USB_EP_CONSOLE].rx_count & RX_COUNT_MASK);
 	     i++) {
-		int val = ((i & 1) ?
-			   (ep_buf_rx[i >> 1] >> 8) :
-			   (ep_buf_rx[i >> 1] & 0xff));
+		int val = ((i & 1) ? (ep_buf_rx[i >> 1] >> 8) :
+				     (ep_buf_rx[i >> 1] & 0xff));
 
 		QUEUE_ADD_UNITS(&rx_q, &val, 1);
 	}
@@ -100,18 +99,18 @@ static void ep_event(enum usb_ep_event evt)
 	if (evt != USB_EVENT_RESET)
 		return;
 
-	btable_ep[USB_EP_CONSOLE].tx_addr  = usb_sram_addr(ep_buf_tx);
+	btable_ep[USB_EP_CONSOLE].tx_addr = usb_sram_addr(ep_buf_tx);
 	btable_ep[USB_EP_CONSOLE].tx_count = 0;
 
-	btable_ep[USB_EP_CONSOLE].rx_addr  = usb_sram_addr(ep_buf_rx);
+	btable_ep[USB_EP_CONSOLE].rx_addr = usb_sram_addr(ep_buf_rx);
 	btable_ep[USB_EP_CONSOLE].rx_count =
 		0x8000 | ((USB_MAX_PACKET_SIZE / 32 - 1) << 10);
 
-	STM32_USB_EP(USB_EP_CONSOLE) = (USB_EP_CONSOLE | /* Endpoint Addr */
-					(2 << 4)       | /* TX NAK        */
-					(0 << 9)       | /* Bulk EP       */
-					(is_readonly ? EP_RX_NAK
-						     : EP_RX_VALID));
+	STM32_USB_EP(USB_EP_CONSOLE) =
+		(USB_EP_CONSOLE | /* Endpoint Addr */
+		 (2 << 4) | /* TX NAK        */
+		 (0 << 9) | /* Bulk EP       */
+		 (is_readonly ? EP_RX_NAK : EP_RX_VALID));
 
 	is_reset = 1;
 }
@@ -201,9 +200,9 @@ static void tx_fifo_handler(void)
 			break;
 
 		if (!(count & 1))
-			buf[count/2] = val;
+			buf[count / 2] = val;
 		else
-			buf[count/2] |= val << 8;
+			buf[count / 2] |= val << 8;
 		count++;
 	}
 
diff --git a/chip/stm32/usb_dfu_runtime.c b/chip/stm32/usb_dfu_runtime.c
new file mode 100644
index 0000000000..92e152078b
--- /dev/null
+++ b/chip/stm32/usb_dfu_runtime.c
@@ -0,0 +1,92 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "dfu_bootmanager_shared.h"
+#include "registers.h"
+#include "usb_descriptor.h"
+#include "usb_dfu_runtime.h"
+#include "usb_hw.h"
+
+/* DFU Run-Time Descriptor Set. */
+const struct usb_interface_descriptor USB_IFACE_DESC(USB_IFACE_DFU) = {
+	.bLength = USB_DT_INTERFACE_SIZE,
+	.bDescriptorType = USB_DT_INTERFACE,
+	.bInterfaceNumber = USB_IFACE_DFU,
+	.bAlternateSetting = 0,
+	.bNumEndpoints = 0,
+	.bInterfaceClass = USB_CLASS_APP_SPEC,
+	.bInterfaceSubClass = USB_DFU_RUNTIME_SUBCLASS,
+	.bInterfaceProtocol = USB_DFU_RUNTIME_PROTOCOL,
+	.iInterface = USB_STR_DFU_NAME,
+};
+
+/* DFU Functional Descriptor. */
+const struct usb_runtime_dfu_functional_desc
+	USB_CUSTOM_DESC_VAR(USB_IFACE_DFU, dfu, dfu_func_desc) = {
+		.bLength = USB_DFU_RUNTIME_DESC_SIZE,
+		.bDescriptorType = USB_DFU_RUNTIME_DESC_FUNCTIONAL,
+		.bmAttributes = USB_DFU_RUNTIME_DESC_ATTRS,
+		.wDetachTimeOut = USB_DFU_RUNTIME_DESC_DETACH_TIMEOUT,
+		.wTransferSize = USB_DFU_RUNTIME_DESC_TRANSFER_SIZE,
+		.bcdDFUVersion = USB_DFU_RUNTIME_DESC_DFU_VERSION,
+	};
+
+static int dfu_runtime_request(usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx)
+{
+	struct usb_setup_packet packet;
+
+	usb_read_setup_packet(ep0_buf_rx, &packet);
+	btable_ep[0].tx_count = 0;
+	if ((packet.bmRequestType ==
+	     (USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE)) &&
+	    (packet.bRequest == USB_REQ_SET_INTERFACE)) {
+		/* ACK the change alternative mode request. */
+
+		STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0);
+		return 0;
+	} else if ((packet.bmRequestType ==
+		    (USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_INTERFACE)) &&
+		   (packet.bRequest == USB_DFU_RUNTIME_REQ_DETACH)) {
+		/* Host is requesting a jump from application to DFU mode. */
+
+		STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0);
+		return dfu_bootmanager_enter_dfu();
+	} else if (packet.bmRequestType ==
+		   (USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_INTERFACE)) {
+		if (packet.bRequest == USB_DFU_RUNTIME_REQ_GET_STATUS) {
+			/* Return the Get Status response. */
+
+			struct usb_runtime_dfu_get_status_resp response = {
+				.bStatus = USB_DFU_RUNTIME_STATUS_OK,
+				.bState = USB_DFU_RUNTIME_STATE_APP_IDLE,
+			};
+
+			memcpy_to_usbram((void *)usb_sram_addr(ep0_buf_tx),
+					 &response, sizeof(response));
+			btable_ep[0].tx_count = sizeof(response);
+			STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0);
+			return 0;
+		}
+		if (packet.bRequest == USB_DFU_RUNTIME_REQ_GET_STATE) {
+			/* Return the Get State response. */
+
+			struct usb_runtime_dfu_get_state_resp response = {
+				.bState = USB_DFU_RUNTIME_STATE_APP_IDLE,
+			};
+
+			memcpy_to_usbram((void *)usb_sram_addr(ep0_buf_tx),
+					 &response, sizeof(response));
+			btable_ep[0].tx_count = sizeof(response);
+			STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0);
+			return 0;
+		}
+	}
+	/* Return a stall response for any unhandled packets. */
+
+	STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_RX_VALID | EP_TX_STALL, 0);
+	return 0;
+}
+
+USB_DECLARE_IFACE(USB_IFACE_DFU, dfu_runtime_request)
diff --git a/chip/stm32/usb_dfu_runtime.h b/chip/stm32/usb_dfu_runtime.h
new file mode 100644
index 0000000000..8b0bbbe219
--- /dev/null
+++ b/chip/stm32/usb_dfu_runtime.h
@@ -0,0 +1,72 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#ifndef __USB_DFU_H
+#define __USB_DFU_H
+
+#include "common.h"
+
+/* Universal Serial Bus Device Class Specification for Device Firmware Upgrade
+ * Version 1.1
+ * https://www.usb.org/sites/default/files/DFU_1.1.pdf
+ */
+
+#define USB_DFU_RUNTIME_SUBCLASS 0x01
+#define USB_DFU_RUNTIME_PROTOCOL 0x01
+
+#define USB_DFU_RUNTIME_DESC_ATTR_CAN_DOWNLOAD BIT(0)
+#define USB_DFU_RUNTIME_DESC_ATTR_CAN_UPLOAD BIT(1)
+#define USB_DFU_RUNTIME_DESC_ATTR_MANIFEST_TOLERANT BIT(2)
+#define USB_DFU_RUNTIME_DESC_ATTR_WILL_DETACH BIT(3)
+
+#define USB_DFU_RUNTIME_DESC_ATTRS                \
+	(USB_DFU_RUNTIME_DESC_ATTR_CAN_DOWNLOAD | \
+	 USB_DFU_RUNTIME_DESC_ATTR_CAN_UPLOAD |   \
+	 USB_DFU_RUNTIME_DESC_ATTR_WILL_DETACH)
+
+#define USB_DFU_RUNTIME_DESC_SIZE 9
+#define USB_DFU_RUNTIME_DESC_FUNCTIONAL 0x21
+#define USB_DFU_RUNTIME_DESC_DETACH_TIMEOUT 0xffff
+#define USB_DFU_RUNTIME_DESC_TRANSFER_SIZE 64
+#define USB_DFU_RUNTIME_DESC_DFU_VERSION 0x0022
+
+/* DFU states */
+#define USB_DFU_RUNTIME_STATE_APP_IDLE 0
+#define USB_DFU_RUNTIME_STATE_APP_DETACH 1
+
+/* DFU status */
+#define USB_DFU_RUNTIME_STATUS_OK 0
+
+/* DFU Request types */
+#define USB_DFU_RUNTIME_REQ_DETACH 0
+#define USB_DFU_RUNTIME_REQ_DNLOAD 1
+#define USB_DFU_RUNTIME_REQ_UPLOAD 2
+#define USB_DFU_RUNTIME_REQ_GET_STATUS 3
+#define USB_DFU_RUNTIME_REQ_CLR_STATUS 4
+#define USB_DFU_RUNTIME_REQ_GET_STATE 5
+#define USB_DFU_RUNTIME_REQ_ABORT 6
+
+/* DFU Functional Descriptor  */
+struct usb_runtime_dfu_functional_desc {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	uint8_t bmAttributes;
+	uint16_t wDetachTimeOut;
+	uint16_t wTransferSize;
+	uint16_t bcdDFUVersion;
+} __packed;
+
+/* DFU response packets */
+struct usb_runtime_dfu_get_status_resp {
+	uint8_t bStatus;
+	uint8_t bwPollTimeout[3];
+	uint8_t bState;
+	uint8_t iString;
+} __packed;
+
+struct usb_runtime_dfu_get_state_resp {
+	uint8_t bState;
+} __packed;
+
+#endif /* __USB_DFU_H */
diff --git a/chip/stm32/usb_dwc.c b/chip/stm32/usb_dwc.c
index f4ee89f1f0..15ce4bff7f 100644
--- a/chip/stm32/usb_dwc.c
+++ b/chip/stm32/usb_dwc.c
@@ -1,8 +1,9 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "builtin/assert.h"
 #include "clock.h"
 #include "common.h"
 #include "config.h"
@@ -12,27 +13,25 @@
 #include "hooks.h"
 #include "link_defs.h"
 #include "registers.h"
-#include "usb_hw.h"
 #include "system.h"
 #include "task.h"
 #include "timer.h"
-#include "util.h"
 #include "usb_descriptor.h"
+#include "usb_hw.h"
+#include "util.h"
 #include "watchdog.h"
 
-
 /****************************************************************************/
 /* Debug output */
 
 /* Console output macro */
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USB, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args)
 
 /* TODO: Something unexpected happened. Figure out how to report & fix it. */
-#define report_error(val)						\
-	CPRINTS("Unhandled USB event at %s line %d: 0x%x",		\
-		__FILE__, __LINE__, val)
-
+#define report_error(val)                                                      \
+	CPRINTS("Unhandled USB event at %s line %d: 0x%x", __FILE__, __LINE__, \
+		val)
 
 /****************************************************************************/
 /* Standard USB stuff */
@@ -49,7 +48,7 @@
 #endif
 
 #ifndef CONFIG_USB_BCD_DEV
-#define CONFIG_USB_BCD_DEV 0x0100		/* 1.00 */
+#define CONFIG_USB_BCD_DEV 0x0100 /* 1.00 */
 #endif
 
 #ifndef CONFIG_USB_SERIALNO
@@ -58,7 +57,6 @@
 static int usb_load_serial(void);
 #endif
 
-
 /* USB Standard Device Descriptor */
 static const struct usb_device_descriptor dev_desc = {
 	.bLength = USB_DT_DEVICE_SIZE,
@@ -81,25 +79,24 @@ static const struct usb_device_descriptor dev_desc = {
 const struct usb_config_descriptor USB_CONF_DESC(conf) = {
 	.bLength = USB_DT_CONFIG_SIZE,
 	.bDescriptorType = USB_DT_CONFIGURATION,
-	.wTotalLength = 0x0BAD,	 /* number of returned bytes, set at runtime */
+	.wTotalLength = 0x0BAD, /* number of returned bytes, set at runtime */
 	.bNumInterfaces = USB_IFACE_COUNT,
-	.bConfigurationValue = 1,		/* Caution: hard-coded value */
+	.bConfigurationValue = 1, /* Caution: hard-coded value */
 	.iConfiguration = USB_STR_VERSION,
 	.bmAttributes = 0x80 /* Reserved bit */
-#ifdef CONFIG_USB_SELF_POWERED  /* bus or self powered */
-		      | 0x40
+#ifdef CONFIG_USB_SELF_POWERED /* bus or self powered */
+			| 0x40
 #endif
 #ifdef CONFIG_USB_REMOTE_WAKEUP
-		      | 0x20
+			| 0x20
 #endif
 	,
 	.bMaxPower = (CONFIG_USB_MAXPOWER_MA / 2),
 };
 
 const uint8_t usb_string_desc[] = {
-	4,					/* Descriptor size */
-	USB_DT_STRING,
-	0x09, 0x04			    /* LangID = 0x0409: U.S. English */
+	4, /* Descriptor size */
+	USB_DT_STRING, 0x09, 0x04 /* LangID = 0x0409: U.S. English */
 };
 
 /****************************************************************************/
@@ -113,7 +110,7 @@ static enum {
 } what_am_i_doing;
 
 #ifdef DEBUG_ME
-static const char * const wat[3] = {
+static const char *const wat[3] = {
 	[WAITING_FOR_SETUP_PACKET] = "wait_for_setup",
 	[DATA_STAGE_IN] = "data_in",
 	[NO_DATA_STAGE] = "no_data",
@@ -182,7 +179,6 @@ static enum {
 } device_state;
 static uint8_t configuration_value;
 
-
 /* True if the HW Rx/OUT FIFO is currently listening. */
 int rx_ep_is_active(uint32_t ep_num)
 {
@@ -326,10 +322,9 @@ void usb_epN_rx(uint32_t ep_num)
 	/* Bytes received decrement DOEPTSIZ XFERSIZE */
 	if (GR_USB_DOEPINT(ep_num) & DOEPINT_XFERCOMPL) {
 		if (ep->out_expected > 0) {
-			ep->out_pending =
-				ep->out_expected -
-				(GR_USB_DOEPTSIZ(ep_num) &
-				 GC_USB_DOEPTSIZ1_XFERSIZE_MASK);
+			ep->out_pending = ep->out_expected -
+					  (GR_USB_DOEPTSIZ(ep_num) &
+					   GC_USB_DOEPTSIZ1_XFERSIZE_MASK);
 		} else {
 			CPRINTF("usb_ep%d_rx: unexpected RX DOEPTSIZ %08x\n",
 				ep_num, GR_USB_DOEPTSIZ(ep_num));
@@ -350,25 +345,22 @@ void usb_epN_rx(uint32_t ep_num)
 void epN_reset(uint32_t ep_num)
 {
 	GR_USB_DOEPCTL(ep_num) = DXEPCTL_MPS(USB_MAX_PACKET_SIZE) |
-		DXEPCTL_USBACTEP | DXEPCTL_EPTYPE_BULK;
+				 DXEPCTL_USBACTEP | DXEPCTL_EPTYPE_BULK;
 	GR_USB_DIEPCTL(ep_num) = DXEPCTL_MPS(USB_MAX_PACKET_SIZE) |
-		DXEPCTL_USBACTEP | DXEPCTL_EPTYPE_BULK |
-		DXEPCTL_TXFNUM(ep_num);
-	GR_USB_DAINTMSK |= DAINT_INEP(ep_num) |
-			   DAINT_OUTEP(ep_num);
+				 DXEPCTL_USBACTEP | DXEPCTL_EPTYPE_BULK |
+				 DXEPCTL_TXFNUM(ep_num);
+	GR_USB_DAINTMSK |= DAINT_INEP(ep_num) | DAINT_OUTEP(ep_num);
 }
 
-
 /******************************************************************************
  * Internal and EP0 functions.
  */
 
-
 static void flush_all_fifos(void)
 {
 	/* Flush all FIFOs according to Section 2.1.1.2 */
-	GR_USB_GRSTCTL = GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH
-		| GRSTCTL_RXFFLSH;
+	GR_USB_GRSTCTL = GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
+			 GRSTCTL_RXFFLSH;
 	while (GR_USB_GRSTCTL & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH))
 		;
 }
@@ -390,7 +382,6 @@ int send_in_packet(uint32_t ep_num)
 	GR_USB_DIEPTSIZ(0) |= DXEPTSIZ_XFERSIZE(len);
 	GR_USB_DIEPDMA(0) = (uint32_t)ep->in_data;
 
-
 	/* We're sending this much. */
 	ep->in_pending -= len;
 	ep->in_packets -= 1;
@@ -400,7 +391,6 @@ int send_in_packet(uint32_t ep_num)
 	return len;
 }
 
-
 /* Load the EP0 IN FIFO buffer with some data (zero-length works too). Returns
  * len, or negative on error.
  */
@@ -418,7 +408,7 @@ int initialize_in_transfer(const void *source, uint32_t len)
 #else
 	/* HS OTG port requires an external phy to support HS */
 	ASSERT(!((usb->phy_type == USB_PHY_INTERNAL) &&
-		(usb->speed == USB_SPEED_HS)));
+		 (usb->speed == USB_SPEED_HS)));
 	ASSERT(usb->irq == STM32_IRQ_OTG_HS);
 #endif
 
@@ -435,7 +425,7 @@ int initialize_in_transfer(const void *source, uint32_t len)
 	/* We will send as many packets as necessary, including a final
 	 * packet of < USB_MAX_PACKET_SIZE (maybe zero length)
 	 */
-	ep->in_packets = (len + USB_MAX_PACKET_SIZE)/USB_MAX_PACKET_SIZE;
+	ep->in_packets = (len + USB_MAX_PACKET_SIZE) / USB_MAX_PACKET_SIZE;
 	ep->in_pending = len;
 
 	send_in_packet(0);
@@ -495,8 +485,8 @@ static void expect_data_phase_in(enum table_case tc)
 
 	/* Send the reply (data phase in) */
 	if (tc == TABLE_CASE_SETUP)
-		GR_USB_DIEPCTL(0) |= DXEPCTL_USBACTEP |
-					DXEPCTL_CNAK | DXEPCTL_EPENA;
+		GR_USB_DIEPCTL(0) |= DXEPCTL_USBACTEP | DXEPCTL_CNAK |
+				     DXEPCTL_EPENA;
 	else
 		GR_USB_DIEPCTL(0) |= DXEPCTL_EPENA;
 
@@ -508,7 +498,6 @@ static void expect_data_phase_in(enum table_case tc)
 
 	/* Get an interrupt when either IN or OUT arrives */
 	GR_USB_DAINTMSK |= (DAINT_OUTEP(0) | DAINT_INEP(0));
-
 }
 
 static void expect_data_phase_out(enum table_case tc)
@@ -524,12 +513,12 @@ static void expect_status_phase_in(enum table_case tc)
 	what_am_i_doing = NO_DATA_STAGE;
 
 	/* Expect a zero-length IN for the Status phase */
-	(void) initialize_in_transfer(0, 0);
+	(void)initialize_in_transfer(0, 0);
 
 	/* Blindly following instructions here, too. */
 	if (tc == TABLE_CASE_SETUP)
-		GR_USB_DIEPCTL(0) |= DXEPCTL_USBACTEP
-			| DXEPCTL_CNAK | DXEPCTL_EPENA;
+		GR_USB_DIEPCTL(0) |= DXEPCTL_USBACTEP | DXEPCTL_CNAK |
+				     DXEPCTL_EPENA;
 	else
 		GR_USB_DIEPCTL(0) |= DXEPCTL_EPENA;
 
@@ -549,7 +538,7 @@ static int handle_setup_with_in_stage(enum table_case tc,
 	const void *data = 0;
 	uint32_t len = 0;
 	int ugly_hack = 0;
-	static const uint16_t zero;		/* == 0 */
+	static const uint16_t zero; /* == 0 */
 
 	switch (req->bRequest) {
 	case USB_REQ_GET_DESCRIPTOR: {
@@ -564,7 +553,7 @@ static int handle_setup_with_in_stage(enum table_case tc,
 		case USB_DT_CONFIGURATION:
 			data = __usb_desc;
 			len = USB_DESC_SIZE;
-			ugly_hack = 1;		/* see below */
+			ugly_hack = 1; /* see below */
 			break;
 #ifdef CONFIG_USB_BOS
 		case USB_DT_BOS:
@@ -657,7 +646,7 @@ static int handle_setup_with_in_stage(enum table_case tc,
 
 /* Handle a Setup that comes with additional data for us. */
 static int handle_setup_with_out_stage(enum table_case tc,
-					struct usb_setup_packet *req)
+				       struct usb_setup_packet *req)
 {
 	/* TODO: We don't support any of these. We should. */
 	report_error(-1);
@@ -720,7 +709,7 @@ static int handle_setup_with_no_data_stage(enum table_case tc,
 			configuration_value = req->wValue;
 			device_state = DS_ADDRESS;
 			break;
-		case 1:	    /* Caution: Only one config descriptor TODAY */
+		case 1: /* Caution: Only one config descriptor TODAY */
 			/* TODO: All endpoints set to DATA0 toggle state */
 			configuration_value = req->wValue;
 			device_state = DS_CONFIGURED;
@@ -756,7 +745,7 @@ static void handle_setup(enum table_case tc)
 		(struct usb_setup_packet *)ep->out_databuffer;
 	int data_phase_in = req->bmRequestType & USB_DIR_IN;
 	int data_phase_out = !data_phase_in && req->wLength;
-	int bytes = -1;				/* default is to stall */
+	int bytes = -1; /* default is to stall */
 
 	if (0 == (req->bmRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))) {
 		/* Standard Device requests */
@@ -900,20 +889,20 @@ static void ep0_interrupt(uint32_t intr_on_out, uint32_t intr_on_in)
  * We support up to 3 control EPs, no periodic IN EPs, up to 16 TX EPs. Max
  * data packet size is 64 bytes. Total SPRAM available is 1024 slots.
  */
-#define MAX_CONTROL_EPS   3
-#define MAX_NORMAL_EPS    16
-#define FIFO_RAM_DEPTH    1024
+#define MAX_CONTROL_EPS 3
+#define MAX_NORMAL_EPS 16
+#define FIFO_RAM_DEPTH 1024
 /*
  * Device RX FIFO size is thus:
  *   (4 * 3 + 6) + 2 * ((64 / 4) + 1) + (2 * 16) + 1 == 85
  */
-#define RXFIFO_SIZE  ((4 * MAX_CONTROL_EPS + 6) + \
-		      2 * ((USB_MAX_PACKET_SIZE / 4) + 1) + \
-		      (2 * MAX_NORMAL_EPS) + 1)
+#define RXFIFO_SIZE                                                        \
+	((4 * MAX_CONTROL_EPS + 6) + 2 * ((USB_MAX_PACKET_SIZE / 4) + 1) + \
+	 (2 * MAX_NORMAL_EPS) + 1)
 /*
  * Device TX FIFO size is 2 * (64 / 4) == 32 for each IN EP (Page 46).
  */
-#define TXFIFO_SIZE  (2 * (USB_MAX_PACKET_SIZE / 4))
+#define TXFIFO_SIZE (2 * (USB_MAX_PACKET_SIZE / 4))
 /*
  * We need 4 slots per endpoint direction for endpoint status stuff (Table 2-1,
  * unconfigurable).
@@ -925,20 +914,19 @@ static void ep0_interrupt(uint32_t intr_on_out, uint32_t intr_on_in)
 BUILD_ASSERT(RXFIFO_SIZE + TXFIFO_SIZE * MAX_NORMAL_EPS + EP_STATUS_SIZE <
 	     FIFO_RAM_DEPTH);
 
-
 /* Now put those constants into the correct registers */
 static void setup_data_fifos(void)
 {
 	int i;
 
 	/* Programmer's Guide, p31 */
-	GR_USB_GRXFSIZ = RXFIFO_SIZE;			      /* RXFIFO */
+	GR_USB_GRXFSIZ = RXFIFO_SIZE; /* RXFIFO */
 	GR_USB_GNPTXFSIZ = (TXFIFO_SIZE << 16) | RXFIFO_SIZE; /* TXFIFO 0 */
 
 	/* TXFIFO 1..15 */
 	for (i = 1; i < MAX_NORMAL_EPS; i++)
-		GR_USB_DIEPTXF(i) = ((TXFIFO_SIZE << 16) |
-				     (RXFIFO_SIZE + i * TXFIFO_SIZE));
+		GR_USB_DIEPTXF(i) =
+			((TXFIFO_SIZE << 16) | (RXFIFO_SIZE + i * TXFIFO_SIZE));
 
 	/*
 	 * TODO: The Programmer's Guide is confusing about when or whether to
@@ -953,10 +941,10 @@ static void setup_data_fifos(void)
 	 */
 
 	/* Flush all FIFOs according to Section 2.1.1.2 */
-	GR_USB_GRSTCTL = GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH
-		| GRSTCTL_RXFFLSH;
+	GR_USB_GRSTCTL = GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
+			 GRSTCTL_RXFFLSH;
 	while (GR_USB_GRSTCTL & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH))
-		;				/* TODO: timeout 100ms */
+		; /* TODO: timeout 100ms */
 }
 
 static void usb_init_endpoints(void)
@@ -998,8 +986,7 @@ static void usb_enumdone(void)
 	GR_USB_DCTL |= DCTL_CGOUTNAK;
 }
 
-
-void usb_interrupt(void)
+static void usb_interrupt(void)
 {
 	uint32_t status = GR_USB_GINTSTS & GR_USB_GINTMSK;
 	uint32_t oepint = status & GINTSTS(OEPINT);
@@ -1027,10 +1014,10 @@ void usb_interrupt(void)
 		 * let it know which direction(s) had an interrupt.
 		 */
 		if (daint & (DAINT_OUTEP(0) | DAINT_INEP(0))) {
-			uint32_t intr_on_out = (oepint &&
-						(daint & DAINT_OUTEP(0)));
-			uint32_t intr_on_in = (iepint &&
-						(daint & DAINT_INEP(0)));
+			uint32_t intr_on_out =
+				(oepint && (daint & DAINT_OUTEP(0)));
+			uint32_t intr_on_in =
+				(iepint && (daint & DAINT_INEP(0)));
 			ep0_interrupt(intr_on_out, intr_on_in);
 		}
 
@@ -1103,8 +1090,8 @@ void usb_reset_init_phy(void)
 
 	if (usb->phy_type == USB_PHY_ULPI) {
 		GR_USB_GCCFG &= ~GCCFG_PWRDWN;
-		GR_USB_GUSBCFG &= ~(GUSBCFG_TSDPS |
-			GUSBCFG_ULPIFSLS | GUSBCFG_PHYSEL);
+		GR_USB_GUSBCFG &=
+			~(GUSBCFG_TSDPS | GUSBCFG_ULPIFSLS | GUSBCFG_PHYSEL);
 		GR_USB_GUSBCFG &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI);
 		/* No suspend */
 		GR_USB_GUSBCFG |= GUSBCFG_ULPICSM | GUSBCFG_ULPIAR;
@@ -1168,11 +1155,11 @@ void usb_init(void)
 		 * GR_USB_DCFG = (GR_USB_DCFG & ~GC_USB_DCFG_DEVSPD_MASK)
 		 * | DCFG_DEVSPD_HSULPI;
 		 */
-		GR_USB_DCFG = (GR_USB_DCFG & ~GC_USB_DCFG_DEVSPD_MASK)
-			| DCFG_DEVSPD_FSULPI;
+		GR_USB_DCFG = (GR_USB_DCFG & ~GC_USB_DCFG_DEVSPD_MASK) |
+			      DCFG_DEVSPD_FSULPI;
 	} else {
-		GR_USB_DCFG = (GR_USB_DCFG & ~GC_USB_DCFG_DEVSPD_MASK)
-			| DCFG_DEVSPD_FS48;
+		GR_USB_DCFG = (GR_USB_DCFG & ~GC_USB_DCFG_DEVSPD_MASK) |
+			      DCFG_DEVSPD_FS48;
 	}
 
 	GR_USB_DCFG |= DCFG_NZLSOHSK;
@@ -1190,10 +1177,11 @@ void usb_init(void)
 	GR_USB_GAHBCFG |= GAHBCFG_TXFELVL | GAHBCFG_PTXFELVL;
 
 	/* Device only, no SRP */
-	GR_USB_GUSBCFG |= GUSBCFG_FDMOD
-		| GUSBCFG_TOUTCAL(7)
-		/* FIXME: Magic number! 14 is for 15MHz! Use 9 for 30MHz */
-		| GUSBCFG_USBTRDTIM(14);
+	GR_USB_GUSBCFG |= GUSBCFG_FDMOD |
+			  GUSBCFG_TOUTCAL(7)
+			  /* FIXME: Magic number! 14 is for 15MHz! Use 9 for
+			     30MHz */
+			  | GUSBCFG_USBTRDTIM(14);
 
 	/* Be in disconnected state until we are ready */
 	usb_disconnect();
@@ -1225,15 +1213,15 @@ void usb_init(void)
 
 	if (usb->dma_en) {
 		GR_USB_DTHRCTL = DTHRCTL_TXTHRLEN_6 | DTHRCTL_RXTHRLEN_6;
-		GR_USB_DTHRCTL |= DTHRCTL_RXTHREN | DTHRCTL_ISOTHREN
-			| DTHRCTL_NONISOTHREN;
+		GR_USB_DTHRCTL |= DTHRCTL_RXTHREN | DTHRCTL_ISOTHREN |
+				  DTHRCTL_NONISOTHREN;
 		i = GR_USB_DTHRCTL;
 	}
 
 	GR_USB_GINTSTS = 0xFFFFFFFF;
 
-	GR_USB_GAHBCFG |= GAHBCFG_GLB_INTR_EN | GAHBCFG_TXFELVL
-		| GAHBCFG_PTXFELVL;
+	GR_USB_GAHBCFG |= GAHBCFG_GLB_INTR_EN | GAHBCFG_TXFELVL |
+			  GAHBCFG_PTXFELVL;
 
 	if (!(usb->dma_en))
 		GR_USB_GINTMSK |= GINTMSK(RXFLVL);
@@ -1241,7 +1229,7 @@ void usb_init(void)
 	/* Unmask some endpoint interrupt causes */
 	GR_USB_DIEPMSK = DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK;
 	GR_USB_DOEPMSK = DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK |
-		DOEPMSK_SETUPMSK;
+			 DOEPMSK_SETUPMSK;
 
 	/* Enable interrupt handlers */
 	task_enable_irq(usb->irq);
@@ -1253,7 +1241,7 @@ void usb_init(void)
 		/* Initialization events */
 		GINTMSK(USBRST) | GINTMSK(ENUMDONE) |
 		/* Reset detected while suspended. Need to wake up. */
-		GINTMSK(RESETDET) |		/* TODO: Do we need this? */
+		GINTMSK(RESETDET) | /* TODO: Do we need this? */
 		/* Idle, Suspend detected. Should go to sleep. */
 		GINTMSK(ERLYSUSP) | GINTMSK(USBSUSP);
 
@@ -1314,7 +1302,7 @@ static void usb_info(void)
 	}
 }
 
-static int command_usb(int argc, char **argv)
+static int command_usb(int argc, const char **argv)
 {
 	if (argc > 1) {
 		if (!strcasecmp("on", argv[1]))
@@ -1328,8 +1316,7 @@ static int command_usb(int argc, char **argv)
 
 	return EC_ERROR_PARAM1;
 }
-DECLARE_CONSOLE_COMMAND(usb, command_usb,
-			"[on|off|info]",
+DECLARE_CONSOLE_COMMAND(usb, command_usb, "[on|off|info]",
 			"Get/set the USB connection state and PHY selection");
 
 #ifdef CONFIG_USB_SERIALNO
@@ -1391,7 +1378,7 @@ static int usb_save_serial(const char *serialno)
 	return rv;
 }
 
-static int command_serialno(int argc, char **argv)
+static int command_serialno(int argc, const char **argv)
 {
 	struct usb_string_desc *sd = usb_serialno_desc;
 	char buf[CONFIG_SERIALNO_LEN];
@@ -1399,12 +1386,10 @@ static int command_serialno(int argc, char **argv)
 	int i;
 
 	if (argc != 1) {
-		if ((strcasecmp(argv[1], "set") == 0) &&
-		    (argc == 3)) {
+		if ((strcasecmp(argv[1], "set") == 0) && (argc == 3)) {
 			ccprintf("Saving serial number\n");
 			rv = usb_save_serial(argv[2]);
-		} else if ((strcasecmp(argv[1], "load") == 0) &&
-			   (argc == 2)) {
+		} else if ((strcasecmp(argv[1], "load") == 0) && (argc == 2)) {
 			ccprintf("Loading serial number\n");
 			rv = usb_load_serial();
 		} else
@@ -1417,7 +1402,6 @@ static int command_serialno(int argc, char **argv)
 	return rv;
 }
 
-DECLARE_CONSOLE_COMMAND(serialno, command_serialno,
-	"load/set [value]",
-	"Read and write USB serial number");
-#endif  /* CONFIG_USB_SERIALNO */
+DECLARE_CONSOLE_COMMAND(serialno, command_serialno, "load/set [value]",
+			"Read and write USB serial number");
+#endif /* CONFIG_USB_SERIALNO */
diff --git a/chip/stm32/usb_dwc_console.c b/chip/stm32/usb_dwc_console.c
index 0d1340fb83..ff3c0817b6 100644
--- a/chip/stm32/usb_dwc_console.c
+++ b/chip/stm32/usb_dwc_console.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,12 +12,12 @@
 #include "registers.h"
 #include "task.h"
 #include "timer.h"
-#include "util.h"
 #include "usb_descriptor.h"
 #include "usb_hw.h"
+#include "util.h"
 
 /* Console output macro */
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args)
 #define USB_CONSOLE_TIMEOUT_US (30 * MSEC)
 
 static int last_tx_ok = 1;
@@ -28,31 +28,31 @@ static int is_readonly;
 
 /* USB-Serial descriptors */
 const struct usb_interface_descriptor USB_IFACE_DESC(USB_IFACE_CONSOLE) = {
-	.bLength		= USB_DT_INTERFACE_SIZE,
-	.bDescriptorType	= USB_DT_INTERFACE,
-	.bInterfaceNumber	= USB_IFACE_CONSOLE,
-	.bAlternateSetting	= 0,
-	.bNumEndpoints		= 2,
-	.bInterfaceClass	= USB_CLASS_VENDOR_SPEC,
-	.bInterfaceSubClass	= USB_SUBCLASS_GOOGLE_SERIAL,
-	.bInterfaceProtocol	= USB_PROTOCOL_GOOGLE_SERIAL,
-	.iInterface		= USB_STR_CONSOLE_NAME,
+	.bLength = USB_DT_INTERFACE_SIZE,
+	.bDescriptorType = USB_DT_INTERFACE,
+	.bInterfaceNumber = USB_IFACE_CONSOLE,
+	.bAlternateSetting = 0,
+	.bNumEndpoints = 2,
+	.bInterfaceClass = USB_CLASS_VENDOR_SPEC,
+	.bInterfaceSubClass = USB_SUBCLASS_GOOGLE_SERIAL,
+	.bInterfaceProtocol = USB_PROTOCOL_GOOGLE_SERIAL,
+	.iInterface = USB_STR_CONSOLE_NAME,
 };
 const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_CONSOLE, 0) = {
-	.bLength		= USB_DT_ENDPOINT_SIZE,
-	.bDescriptorType	= USB_DT_ENDPOINT,
-	.bEndpointAddress	= 0x80 | USB_EP_CONSOLE,
-	.bmAttributes		= 0x02 /* Bulk IN */,
-	.wMaxPacketSize		= USB_MAX_PACKET_SIZE,
-	.bInterval		 = 10,
+	.bLength = USB_DT_ENDPOINT_SIZE,
+	.bDescriptorType = USB_DT_ENDPOINT,
+	.bEndpointAddress = 0x80 | USB_EP_CONSOLE,
+	.bmAttributes = 0x02 /* Bulk IN */,
+	.wMaxPacketSize = USB_MAX_PACKET_SIZE,
+	.bInterval = 10,
 };
 const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_CONSOLE, 1) = {
-	.bLength	    = USB_DT_ENDPOINT_SIZE,
-	.bDescriptorType    = USB_DT_ENDPOINT,
-	.bEndpointAddress   = USB_EP_CONSOLE,
-	.bmAttributes       = 0x02 /* Bulk OUT */,
-	.wMaxPacketSize     = USB_MAX_PACKET_SIZE,
-	.bInterval	  = 0
+	.bLength = USB_DT_ENDPOINT_SIZE,
+	.bDescriptorType = USB_DT_ENDPOINT,
+	.bEndpointAddress = USB_EP_CONSOLE,
+	.bmAttributes = 0x02 /* Bulk OUT */,
+	.wMaxPacketSize = USB_MAX_PACKET_SIZE,
+	.bInterval = 0
 };
 
 static uint8_t ep_buf_tx[USB_MAX_PACKET_SIZE];
@@ -61,7 +61,6 @@ static uint8_t ep_buf_rx[USB_MAX_PACKET_SIZE];
 static struct queue const tx_q = QUEUE_NULL(256, uint8_t);
 static struct queue const rx_q = QUEUE_NULL(USB_MAX_PACKET_SIZE, uint8_t);
 
-
 struct dwc_usb_ep ep_console_ctl = {
 	.max_packet = USB_MAX_PACKET_SIZE,
 	.tx_fifo = USB_EP_CONSOLE,
@@ -76,8 +75,6 @@ struct dwc_usb_ep ep_console_ctl = {
 	.in_databuffer_max = sizeof(ep_buf_rx),
 };
 
-
-
 /* Let the USB HW IN-to-host FIFO transmit some bytes */
 static void usb_enable_tx(int len)
 {
@@ -162,9 +159,8 @@ static void con_ep_rx(void)
 	/* Bytes received decrement DOEPTSIZ XFERSIZE */
 	if (GR_USB_DOEPINT(USB_EP_CONSOLE) & DOEPINT_XFERCOMPL) {
 		ep->out_pending =
-			ep->max_packet -
-			(GR_USB_DOEPTSIZ(USB_EP_CONSOLE) &
-			 GC_USB_DOEPTSIZ1_XFERSIZE_MASK);
+			ep->max_packet - (GR_USB_DOEPTSIZ(USB_EP_CONSOLE) &
+					  GC_USB_DOEPTSIZ1_XFERSIZE_MASK);
 	}
 
 	/* Wake up the Rx FIFO handler */
@@ -193,8 +189,8 @@ static void tx_fifo_handler(void)
 	if (!tx_fifo_is_ready())
 		return;
 
-	count = QUEUE_REMOVE_UNITS(&tx_q,
-		ep->in_databuffer, USB_MAX_PACKET_SIZE);
+	count = QUEUE_REMOVE_UNITS(&tx_q, ep->in_databuffer,
+				   USB_MAX_PACKET_SIZE);
 	if (count)
 		usb_enable_tx(count);
 }
@@ -232,7 +228,6 @@ static void ep_event(enum usb_ep_event evt)
 	usb_enable_rx(USB_MAX_PACKET_SIZE);
 }
 
-
 USB_DECLARE_EP(USB_EP_CONSOLE, con_ep_tx, con_ep_rx, ep_event);
 
 static int usb_wait_console(void)
@@ -274,8 +269,7 @@ static int usb_wait_console(void)
 }
 static int __tx_char(void *context, int c)
 {
-	struct queue *state =
-			(struct queue *) context;
+	struct queue *state = (struct queue *)context;
 
 	if (c == '\n' && __tx_char(state, '\r'))
 		return 1;
@@ -308,7 +302,7 @@ int usb_puts(const char *outstr)
 	if (is_readonly)
 		return EC_SUCCESS;
 
-	ret  = usb_wait_console();
+	ret = usb_wait_console();
 	if (ret)
 		return ret;
 
diff --git a/chip/stm32/usb_dwc_console.h b/chip/stm32/usb_dwc_console.h
index ab2206d359..f0a0732c7d 100644
--- a/chip/stm32/usb_dwc_console.h
+++ b/chip/stm32/usb_dwc_console.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,4 +10,4 @@
 
 extern struct dwc_usb_ep ep_console_ctl;
 
-#endif  /* __CHIP_STM32_USB_DWC_CONSOLE_H */
+#endif /* __CHIP_STM32_USB_DWC_CONSOLE_H */
diff --git a/chip/stm32/usb_dwc_hw.h b/chip/stm32/usb_dwc_hw.h
index d1fe07cb87..ea87869257 100644
--- a/chip/stm32/usb_dwc_hw.h
+++ b/chip/stm32/usb_dwc_hw.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,29 +18,27 @@
 #define _EP_RX_HANDLER_TYPECHECK(num) _EP_HANDLER2(num, _rx_typecheck)
 #define _EP_EVENT_HANDLER_TYPECHECK(num) _EP_HANDLER2(num, _evt_typecheck)
 
-#define USB_DECLARE_EP(num, tx_handler, rx_handler, evt_handler)  \
-	void _EP_TX_HANDLER(num)(void)				  \
-		__attribute__ ((alias(STRINGIFY(tx_handler))));	  \
-	void _EP_RX_HANDLER(num)(void)                            \
-		__attribute__ ((alias(STRINGIFY(rx_handler))));	  \
-	void _EP_EVENT_HANDLER(num)(enum usb_ep_event evt)	  \
-		__attribute__ ((alias(STRINGIFY(evt_handler))));  \
-	static __unused void					  \
-	(*_EP_TX_HANDLER_TYPECHECK(num))(void) = tx_handler;	  \
-	static __unused void					  \
-	(*_EP_RX_HANDLER_TYPECHECK(num))(void) = rx_handler;	  \
-	static __unused void					  \
-	(*_EP_EVENT_HANDLER_TYPECHECK(num))(enum usb_ep_event evt)\
-			= evt_handler
+#define USB_DECLARE_EP(num, tx_handler, rx_handler, evt_handler)      \
+	void _EP_TX_HANDLER(num)(void)                                \
+		__attribute__((alias(STRINGIFY(tx_handler))));        \
+	void _EP_RX_HANDLER(num)(void)                                \
+		__attribute__((alias(STRINGIFY(rx_handler))));        \
+	void _EP_EVENT_HANDLER(num)(enum usb_ep_event evt)            \
+		__attribute__((alias(STRINGIFY(evt_handler))));       \
+	static __unused void (*_EP_TX_HANDLER_TYPECHECK(num))(void) = \
+		tx_handler;                                           \
+	static __unused void (*_EP_RX_HANDLER_TYPECHECK(num))(void) = \
+		rx_handler;                                           \
+	static __unused void (*_EP_EVENT_HANDLER_TYPECHECK(num))(     \
+		enum usb_ep_event evt) = evt_handler
 
 /* Endpoint callbacks */
-extern void (*usb_ep_tx[]) (void);
-extern void (*usb_ep_rx[]) (void);
-extern void (*usb_ep_event[]) (enum usb_ep_event evt);
+extern void (*usb_ep_tx[])(void);
+extern void (*usb_ep_rx[])(void);
+extern void (*usb_ep_event[])(enum usb_ep_event evt);
 struct usb_setup_packet;
 /* EP0 Interface handler callbacks */
-extern int (*usb_iface_request[]) (struct usb_setup_packet *req);
-
+extern int (*usb_iface_request[])(struct usb_setup_packet *req);
 
 /* True if the HW Rx/OUT FIFO is currently listening. */
 int rx_ep_is_active(uint32_t ep_num);
@@ -99,8 +97,8 @@ void epN_reset(uint32_t ep_num);
  * (and thus indicate error to the host).
  */
 #define _IFACE_HANDLER(num) CONCAT3(iface_, num, _request)
-#define USB_DECLARE_IFACE(num, handler)				\
-	int _IFACE_HANDLER(num)(struct usb_setup_packet *req)	\
-		__attribute__ ((alias(STRINGIFY(handler))))
+#define USB_DECLARE_IFACE(num, handler)                        \
+	int _IFACE_HANDLER(num)(struct usb_setup_packet * req) \
+		__attribute__((alias(STRINGIFY(handler))))
 
-#endif	/* __CROS_EC_USB_DWC_HW_H */
+#endif /* __CROS_EC_USB_DWC_HW_H */
diff --git a/chip/stm32/usb_dwc_i2c.h b/chip/stm32/usb_dwc_i2c.h
index e44002268a..6e6c72e22c 100644
--- a/chip/stm32/usb_dwc_i2c.h
+++ b/chip/stm32/usb_dwc_i2c.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/stm32/usb_dwc_registers.h b/chip/stm32/usb_dwc_registers.h
index faac9ca775..b5ada2ce65 100644
--- a/chip/stm32/usb_dwc_registers.h
+++ b/chip/stm32/usb_dwc_registers.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -55,7479 +55,7467 @@ extern struct dwc_usb usb_ctl;
  * Added Alias Module Family Base Address to 0-instance Module Base Address
  * Simplify GBASE(mname) macro
  */
-#define GC_MODULE_OFFSET         0x10000
+#define GC_MODULE_OFFSET 0x10000
 
-#define GBASE(mname)      \
-	GC_ ## mname ## _BASE_ADDR
-#define GOFFSET(mname, rname)  \
-	GC_ ## mname ## _ ## rname ## _OFFSET
+#define GBASE(mname) GC_##mname##_BASE_ADDR
+#define GOFFSET(mname, rname) GC_##mname##_##rname##_OFFSET
 
-#define GREG8(mname, rname) \
-	REG8(GBASE(mname) + GOFFSET(mname, rname))
-#define GREG32(mname, rname) \
-	REG32(GBASE(mname) + GOFFSET(mname, rname))
+#define GREG8(mname, rname) REG8(GBASE(mname) + GOFFSET(mname, rname))
+#define GREG32(mname, rname) REG32(GBASE(mname) + GOFFSET(mname, rname))
 #define GREG32_ADDR(mname, rname) \
 	REG32_ADDR(GBASE(mname) + GOFFSET(mname, rname))
 #define GWRITE(mname, rname, value) (GREG32(mname, rname) = (value))
-#define GREAD(mname, rname)	    GREG32(mname, rname)
+#define GREAD(mname, rname) GREG32(mname, rname)
 
-#define GFIELD_MASK(mname, rname, fname) \
-	GC_ ## mname ## _ ## rname ## _ ## fname ## _MASK
+#define GFIELD_MASK(mname, rname, fname) GC_##mname##_##rname##_##fname##_MASK
 
-#define GFIELD_LSB(mname, rname, fname)  \
-	GC_ ## mname ## _ ## rname ## _ ## fname ## _LSB
+#define GFIELD_LSB(mname, rname, fname) GC_##mname##_##rname##_##fname##_LSB
 
-#define GREAD_FIELD(mname, rname, fname) \
-	((GREG32(mname, rname) & GFIELD_MASK(mname, rname, fname)) \
-		>> GFIELD_LSB(mname, rname, fname))
+#define GREAD_FIELD(mname, rname, fname)                              \
+	((GREG32(mname, rname) & GFIELD_MASK(mname, rname, fname)) >> \
+	 GFIELD_LSB(mname, rname, fname))
 
-#define GWRITE_FIELD(mname, rname, fname, fval) \
-	(GREG32(mname, rname) = \
-	((GREG32(mname, rname) & (~GFIELD_MASK(mname, rname, fname))) | \
-	(((fval) << GFIELD_LSB(mname, rname, fname)) & \
-		GFIELD_MASK(mname, rname, fname))))
+#define GWRITE_FIELD(mname, rname, fname, fval)                  \
+	(GREG32(mname, rname) =                                  \
+		 ((GREG32(mname, rname) &                        \
+		   (~GFIELD_MASK(mname, rname, fname))) |        \
+		  (((fval) << GFIELD_LSB(mname, rname, fname)) & \
+		   GFIELD_MASK(mname, rname, fname))))
 
-
-#define GBASE_I(mname, i)     (GBASE(mname) + i*GC_MODULE_OFFSET)
+#define GBASE_I(mname, i) (GBASE(mname) + i * GC_MODULE_OFFSET)
 
 #define GREG32_I(mname, i, rname) \
-		REG32(GBASE_I(mname, i) + GOFFSET(mname, rname))
+	REG32(GBASE_I(mname, i) + GOFFSET(mname, rname))
 
 #define GREG32_ADDR_I(mname, i, rname) \
-		REG32_ADDR(GBASE_I(mname, i) + GOFFSET(mname, rname))
+	REG32_ADDR(GBASE_I(mname, i) + GOFFSET(mname, rname))
 
 #define GWRITE_I(mname, i, rname, value) (GREG32_I(mname, i, rname) = (value))
-#define GREAD_I(mname, i, rname)	        GREG32_I(mname, i, rname)
+#define GREAD_I(mname, i, rname) GREG32_I(mname, i, rname)
 
-#define GREAD_FIELD_I(mname, i, rname, fname) \
-	((GREG32_I(mname, i, rname) & GFIELD_MASK(mname, rname, fname)) \
-		>> GFIELD_LSB(mname, rname, fname))
+#define GREAD_FIELD_I(mname, i, rname, fname)                              \
+	((GREG32_I(mname, i, rname) & GFIELD_MASK(mname, rname, fname)) >> \
+	 GFIELD_LSB(mname, rname, fname))
 
-#define GWRITE_FIELD_I(mname, i, rname, fname, fval) \
-	(GREG32_I(mname, i, rname) = \
-	((GREG32_I(mname, i, rname) & (~GFIELD_MASK(mname, rname, fname))) | \
-	(((fval) << GFIELD_LSB(mname, rname, fname)) & \
-		GFIELD_MASK(mname, rname, fname))))
+#define GWRITE_FIELD_I(mname, i, rname, fname, fval)             \
+	(GREG32_I(mname, i, rname) =                             \
+		 ((GREG32_I(mname, i, rname) &                   \
+		   (~GFIELD_MASK(mname, rname, fname))) |        \
+		  (((fval) << GFIELD_LSB(mname, rname, fname)) & \
+		   GFIELD_MASK(mname, rname, fname))))
 
 /* Replace masked bits with val << lsb */
 #define REG_WRITE_MLV(reg, mask, lsb, val) \
-		(reg = ((reg & ~mask) | ((val << lsb) & mask)))
-
+	(reg = ((reg & ~mask) | ((val << lsb) & mask)))
 
 /* USB device controller */
-#define GR_USB_REG(off)               REG32(GC_USB_BASE_ADDR + (off))
-#define GR_USB_GOTGCTL                GR_USB_REG(GC_USB_GOTGCTL_OFFSET)
-#define GR_USB_GOTGINT                GR_USB_REG(GC_USB_GOTGINT_OFFSET)
-#define GR_USB_GAHBCFG                GR_USB_REG(GC_USB_GAHBCFG_OFFSET)
-#define GR_USB_GUSBCFG                GR_USB_REG(GC_USB_GUSBCFG_OFFSET)
-#define GR_USB_GRSTCTL                GR_USB_REG(GC_USB_GRSTCTL_OFFSET)
-#define GR_USB_GINTSTS                GR_USB_REG(GC_USB_GINTSTS_OFFSET)
-#define   GINTSTS(bit)                (1 << GC_USB_GINTSTS_ ## bit ## _LSB)
-#define GR_USB_GINTMSK                GR_USB_REG(GC_USB_GINTMSK_OFFSET)
-#define   GINTMSK(bit)                (1 << GC_USB_GINTMSK_ ## bit ## MSK_LSB)
-#define GR_USB_GRXSTSR                GR_USB_REG(GC_USB_GRXSTSR_OFFSET)
-#define GR_USB_GRXSTSP                GR_USB_REG(GC_USB_GRXSTSP_OFFSET)
-#define GR_USB_GRXFSIZ                GR_USB_REG(GC_USB_GRXFSIZ_OFFSET)
-#define GR_USB_GNPTXFSIZ              GR_USB_REG(GC_USB_GNPTXFSIZ_OFFSET)
+#define GR_USB_REG(off) REG32(GC_USB_BASE_ADDR + (off))
+#define GR_USB_GOTGCTL GR_USB_REG(GC_USB_GOTGCTL_OFFSET)
+#define GR_USB_GOTGINT GR_USB_REG(GC_USB_GOTGINT_OFFSET)
+#define GR_USB_GAHBCFG GR_USB_REG(GC_USB_GAHBCFG_OFFSET)
+#define GR_USB_GUSBCFG GR_USB_REG(GC_USB_GUSBCFG_OFFSET)
+#define GR_USB_GRSTCTL GR_USB_REG(GC_USB_GRSTCTL_OFFSET)
+#define GR_USB_GINTSTS GR_USB_REG(GC_USB_GINTSTS_OFFSET)
+#define GINTSTS(bit) (1 << GC_USB_GINTSTS_##bit##_LSB)
+#define GR_USB_GINTMSK GR_USB_REG(GC_USB_GINTMSK_OFFSET)
+#define GINTMSK(bit) (1 << GC_USB_GINTMSK_##bit##MSK_LSB)
+#define GR_USB_GRXSTSR GR_USB_REG(GC_USB_GRXSTSR_OFFSET)
+#define GR_USB_GRXSTSP GR_USB_REG(GC_USB_GRXSTSP_OFFSET)
+#define GR_USB_GRXFSIZ GR_USB_REG(GC_USB_GRXFSIZ_OFFSET)
+#define GR_USB_GNPTXFSIZ GR_USB_REG(GC_USB_GNPTXFSIZ_OFFSET)
 /*#define GR_USB_GGPIO                  GR_USB_REG(GC_USB_GGPIO_OFFSET)*/
-#define GR_USB_GCCFG                  GR_USB_REG(GC_USB_GCCFG_OFFSET)
-#define  GCCFG_VBDEN            BIT(21)
-#define  GCCFG_PWRDWN           BIT(16)
-#define GR_USB_PCGCCTL                GR_USB_REG(GC_USB_PCGCCTL_OFFSET)
+#define GR_USB_GCCFG GR_USB_REG(GC_USB_GCCFG_OFFSET)
+#define GCCFG_VBDEN BIT(21)
+#define GCCFG_PWRDWN BIT(16)
+#define GR_USB_PCGCCTL GR_USB_REG(GC_USB_PCGCCTL_OFFSET)
 
-#define GR_USB_GSNPSID                GR_USB_REG(GC_USB_GSNPSID_OFFSET)
-#define GR_USB_GHWCFG1                GR_USB_REG(GC_USB_GHWCFG1_OFFSET)
-#define GR_USB_GHWCFG2                GR_USB_REG(GC_USB_GHWCFG2_OFFSET)
-#define GR_USB_GHWCFG3                GR_USB_REG(GC_USB_GHWCFG3_OFFSET)
-#define GR_USB_GHWCFG4                GR_USB_REG(GC_USB_GHWCFG4_OFFSET)
-#define GR_USB_GDFIFOCFG              GR_USB_REG(GC_USB_GDFIFOCFG_OFFSET)
-#define GR_USB_DIEPTXF(n)	\
-	GR_USB_REG(GC_USB_DIEPTXF1_OFFSET - 4 + (n)*4)
-#define GR_USB_DCFG                   GR_USB_REG(GC_USB_DCFG_OFFSET)
-#define GR_USB_DCTL                   GR_USB_REG(GC_USB_DCTL_OFFSET)
-#define GR_USB_DSTS                   GR_USB_REG(GC_USB_DSTS_OFFSET)
-#define GR_USB_DIEPMSK                GR_USB_REG(GC_USB_DIEPMSK_OFFSET)
-#define GR_USB_DOEPMSK                GR_USB_REG(GC_USB_DOEPMSK_OFFSET)
-#define GR_USB_DAINT                  GR_USB_REG(GC_USB_DAINT_OFFSET)
-#define GR_USB_DAINTMSK               GR_USB_REG(GC_USB_DAINTMSK_OFFSET)
-#define  DAINT_INEP(ep)               (1 << (ep + GC_USB_DAINTMSK_INEPMSK0_LSB))
-#define  DAINT_OUTEP(ep)	\
-	(1 << (ep + GC_USB_DAINTMSK_OUTEPMSK0_LSB))
-#define GR_USB_DTHRCTL                GR_USB_REG(GC_USB_DTHRCTL_OFFSET)
-#define  DTHRCTL_TXTHRLEN_6           (0x40 << 2)
-#define  DTHRCTL_RXTHRLEN_6           (0x40 << 17)
-#define  DTHRCTL_RXTHREN              BIT(16)
-#define  DTHRCTL_ISOTHREN             BIT(1)
-#define  DTHRCTL_NONISOTHREN          BIT(0)
-#define GR_USB_DIEPEMPMSK             GR_USB_REG(GC_USB_DIEPEMPMSK_OFFSET)
+#define GR_USB_GSNPSID GR_USB_REG(GC_USB_GSNPSID_OFFSET)
+#define GR_USB_GHWCFG1 GR_USB_REG(GC_USB_GHWCFG1_OFFSET)
+#define GR_USB_GHWCFG2 GR_USB_REG(GC_USB_GHWCFG2_OFFSET)
+#define GR_USB_GHWCFG3 GR_USB_REG(GC_USB_GHWCFG3_OFFSET)
+#define GR_USB_GHWCFG4 GR_USB_REG(GC_USB_GHWCFG4_OFFSET)
+#define GR_USB_GDFIFOCFG GR_USB_REG(GC_USB_GDFIFOCFG_OFFSET)
+#define GR_USB_DIEPTXF(n) GR_USB_REG(GC_USB_DIEPTXF1_OFFSET - 4 + (n)*4)
+#define GR_USB_DCFG GR_USB_REG(GC_USB_DCFG_OFFSET)
+#define GR_USB_DCTL GR_USB_REG(GC_USB_DCTL_OFFSET)
+#define GR_USB_DSTS GR_USB_REG(GC_USB_DSTS_OFFSET)
+#define GR_USB_DIEPMSK GR_USB_REG(GC_USB_DIEPMSK_OFFSET)
+#define GR_USB_DOEPMSK GR_USB_REG(GC_USB_DOEPMSK_OFFSET)
+#define GR_USB_DAINT GR_USB_REG(GC_USB_DAINT_OFFSET)
+#define GR_USB_DAINTMSK GR_USB_REG(GC_USB_DAINTMSK_OFFSET)
+#define DAINT_INEP(ep) (1 << (ep + GC_USB_DAINTMSK_INEPMSK0_LSB))
+#define DAINT_OUTEP(ep) (1 << (ep + GC_USB_DAINTMSK_OUTEPMSK0_LSB))
+#define GR_USB_DTHRCTL GR_USB_REG(GC_USB_DTHRCTL_OFFSET)
+#define DTHRCTL_TXTHRLEN_6 (0x40 << 2)
+#define DTHRCTL_RXTHRLEN_6 (0x40 << 17)
+#define DTHRCTL_RXTHREN BIT(16)
+#define DTHRCTL_ISOTHREN BIT(1)
+#define DTHRCTL_NONISOTHREN BIT(0)
+#define GR_USB_DIEPEMPMSK GR_USB_REG(GC_USB_DIEPEMPMSK_OFFSET)
 
-#define GR_USB_EPIREG(off, n)         GR_USB_REG(0x900 + (n) * 0x20 + (off))
-#define GR_USB_EPOREG(off, n)         GR_USB_REG(0xb00 + (n) * 0x20 + (off))
-#define GR_USB_DIEPCTL(n)             GR_USB_EPIREG(0x00, n)
-#define GR_USB_DIEPINT(n)             GR_USB_EPIREG(0x08, n)
-#define GR_USB_DIEPTSIZ(n)            GR_USB_EPIREG(0x10, n)
-#define GR_USB_DIEPDMA(n)             GR_USB_EPIREG(0x14, n)
-#define GR_USB_DTXFSTS(n)             GR_USB_EPIREG(0x18, n)
-#define GR_USB_DIEPDMAB(n)            GR_USB_EPIREG(0x1c, n)
-#define GR_USB_DOEPCTL(n)             GR_USB_EPOREG(0x00, n)
-#define GR_USB_DOEPINT(n)             GR_USB_EPOREG(0x08, n)
-#define GR_USB_DOEPTSIZ(n)            GR_USB_EPOREG(0x10, n)
-#define GR_USB_DOEPDMA(n)             GR_USB_EPOREG(0x14, n)
-#define GR_USB_DOEPDMAB(n)            GR_USB_EPOREG(0x1c, n)
+#define GR_USB_EPIREG(off, n) GR_USB_REG(0x900 + (n)*0x20 + (off))
+#define GR_USB_EPOREG(off, n) GR_USB_REG(0xb00 + (n)*0x20 + (off))
+#define GR_USB_DIEPCTL(n) GR_USB_EPIREG(0x00, n)
+#define GR_USB_DIEPINT(n) GR_USB_EPIREG(0x08, n)
+#define GR_USB_DIEPTSIZ(n) GR_USB_EPIREG(0x10, n)
+#define GR_USB_DIEPDMA(n) GR_USB_EPIREG(0x14, n)
+#define GR_USB_DTXFSTS(n) GR_USB_EPIREG(0x18, n)
+#define GR_USB_DIEPDMAB(n) GR_USB_EPIREG(0x1c, n)
+#define GR_USB_DOEPCTL(n) GR_USB_EPOREG(0x00, n)
+#define GR_USB_DOEPINT(n) GR_USB_EPOREG(0x08, n)
+#define GR_USB_DOEPTSIZ(n) GR_USB_EPOREG(0x10, n)
+#define GR_USB_DOEPDMA(n) GR_USB_EPOREG(0x14, n)
+#define GR_USB_DOEPDMAB(n) GR_USB_EPOREG(0x1c, n)
 
-#define GOTGCTL_BVALOEN               BIT(GC_USB_GOTGCTL_BVALIDOVEN_LSB)
-#define GOTGCTL_BVALOVAL              BIT(7)
+#define GOTGCTL_BVALOEN BIT(GC_USB_GOTGCTL_BVALIDOVEN_LSB)
+#define GOTGCTL_BVALOVAL BIT(7)
 
 /* Bit 5 */
-#define GAHBCFG_DMA_EN                BIT(GC_USB_GAHBCFG_DMAEN_LSB)
+#define GAHBCFG_DMA_EN BIT(GC_USB_GAHBCFG_DMAEN_LSB)
 /* Bit 1 */
-#define GAHBCFG_GLB_INTR_EN           BIT(GC_USB_GAHBCFG_GLBLINTRMSK_LSB)
+#define GAHBCFG_GLB_INTR_EN BIT(GC_USB_GAHBCFG_GLBLINTRMSK_LSB)
 /* HS Burst Len */
-#define GAHBCFG_HBSTLEN_INCR4         (3 << GC_USB_GAHBCFG_HBSTLEN_LSB)
+#define GAHBCFG_HBSTLEN_INCR4 (3 << GC_USB_GAHBCFG_HBSTLEN_LSB)
 /* Bit 7 */
-#define GAHBCFG_NP_TXF_EMP_LVL        (1 <<  GC_USB_GAHBCFG_NPTXFEMPLVL_LSB)
-#define GAHBCFG_TXFELVL               GAHBCFG_NP_TXF_EMP_LVL
-#define GAHBCFG_PTXFELVL              BIT(8)
+#define GAHBCFG_NP_TXF_EMP_LVL (1 << GC_USB_GAHBCFG_NPTXFEMPLVL_LSB)
+#define GAHBCFG_TXFELVL GAHBCFG_NP_TXF_EMP_LVL
+#define GAHBCFG_PTXFELVL BIT(8)
 
-#define GUSBCFG_TOUTCAL(n)            (((n) << GC_USB_GUSBCFG_TOUTCAL_LSB) \
-				       & GC_USB_GUSBCFG_TOUTCAL_MASK)
-#define GUSBCFG_USBTRDTIM(n)          (((n) << GC_USB_GUSBCFG_USBTRDTIM_LSB) \
-				       & GC_USB_GUSBCFG_USBTRDTIM_MASK)
+#define GUSBCFG_TOUTCAL(n) \
+	(((n) << GC_USB_GUSBCFG_TOUTCAL_LSB) & GC_USB_GUSBCFG_TOUTCAL_MASK)
+#define GUSBCFG_USBTRDTIM(n) \
+	(((n) << GC_USB_GUSBCFG_USBTRDTIM_LSB) & GC_USB_GUSBCFG_USBTRDTIM_MASK)
 /* Force device mode */
-#define GUSBCFG_FDMOD                 BIT(GC_USB_GUSBCFG_FDMOD_LSB)
-#define GUSBCFG_PHYSEL                BIT(6)
-#define GUSBCFG_SRPCAP                BIT(8)
-#define GUSBCFG_HNPCAP                BIT(9)
-#define GUSBCFG_ULPIFSLS              BIT(17)
-#define GUSBCFG_ULPIAR                BIT(18)
-#define GUSBCFG_ULPICSM               BIT(19)
-#define GUSBCFG_ULPIEVBUSD            BIT(20)
-#define GUSBCFG_ULPIEVBUSI            BIT(21)
-#define GUSBCFG_TSDPS                 BIT(22)
-#define GUSBCFG_PCCI                  BIT(23)
-#define GUSBCFG_PTCI                  BIT(24)
-#define GUSBCFG_ULPIIPD               BIT(25)
-#define GUSBCFG_TSDPS                 BIT(22)
-
+#define GUSBCFG_FDMOD BIT(GC_USB_GUSBCFG_FDMOD_LSB)
+#define GUSBCFG_PHYSEL BIT(6)
+#define GUSBCFG_SRPCAP BIT(8)
+#define GUSBCFG_HNPCAP BIT(9)
+#define GUSBCFG_ULPIFSLS BIT(17)
+#define GUSBCFG_ULPIAR BIT(18)
+#define GUSBCFG_ULPICSM BIT(19)
+#define GUSBCFG_ULPIEVBUSD BIT(20)
+#define GUSBCFG_ULPIEVBUSI BIT(21)
+#define GUSBCFG_TSDPS BIT(22)
+#define GUSBCFG_PCCI BIT(23)
+#define GUSBCFG_PTCI BIT(24)
+#define GUSBCFG_ULPIIPD BIT(25)
+#define GUSBCFG_TSDPS BIT(22)
 
-#define GRSTCTL_CSFTRST               BIT(GC_USB_GRSTCTL_CSFTRST_LSB)
-#define GRSTCTL_AHBIDLE               BIT(GC_USB_GRSTCTL_AHBIDLE_LSB)
-#define GRSTCTL_TXFFLSH               BIT(GC_USB_GRSTCTL_TXFFLSH_LSB)
-#define GRSTCTL_RXFFLSH               BIT(GC_USB_GRSTCTL_RXFFLSH_LSB)
-#define GRSTCTL_TXFNUM(n)	\
+#define GRSTCTL_CSFTRST BIT(GC_USB_GRSTCTL_CSFTRST_LSB)
+#define GRSTCTL_AHBIDLE BIT(GC_USB_GRSTCTL_AHBIDLE_LSB)
+#define GRSTCTL_TXFFLSH BIT(GC_USB_GRSTCTL_TXFFLSH_LSB)
+#define GRSTCTL_RXFFLSH BIT(GC_USB_GRSTCTL_RXFFLSH_LSB)
+#define GRSTCTL_TXFNUM(n) \
 	(((n) << GC_USB_GRSTCTL_TXFNUM_LSB) & GC_USB_GRSTCTL_TXFNUM_MASK)
 
-#define DCFG_DEVSPD_HSULPI            (0 << GC_USB_DCFG_DEVSPD_LSB)
-#define DCFG_DEVSPD_FSULPI            BIT(GC_USB_DCFG_DEVSPD_LSB)
-#define DCFG_DEVSPD_FS48              (3 << GC_USB_DCFG_DEVSPD_LSB)
-#define DCFG_DEVADDR(a)	\
+#define DCFG_DEVSPD_HSULPI (0 << GC_USB_DCFG_DEVSPD_LSB)
+#define DCFG_DEVSPD_FSULPI BIT(GC_USB_DCFG_DEVSPD_LSB)
+#define DCFG_DEVSPD_FS48 (3 << GC_USB_DCFG_DEVSPD_LSB)
+#define DCFG_DEVADDR(a) \
 	(((a) << GC_USB_DCFG_DEVADDR_LSB) & GC_USB_DCFG_DEVADDR_MASK)
-#define DCFG_NZLSOHSK                 BIT(GC_USB_DCFG_NZSTSOUTHSHK_LSB)
+#define DCFG_NZLSOHSK BIT(GC_USB_DCFG_NZSTSOUTHSHK_LSB)
 
-#define DCTL_SFTDISCON                BIT(GC_USB_DCTL_SFTDISCON_LSB)
-#define DCTL_CGOUTNAK                 BIT(GC_USB_DCTL_CGOUTNAK_LSB)
-#define DCTL_CGNPINNAK                BIT(GC_USB_DCTL_CGNPINNAK_LSB)
-#define DCTL_PWRONPRGDONE             BIT(GC_USB_DCTL_PWRONPRGDONE_LSB)
+#define DCTL_SFTDISCON BIT(GC_USB_DCTL_SFTDISCON_LSB)
+#define DCTL_CGOUTNAK BIT(GC_USB_DCTL_CGOUTNAK_LSB)
+#define DCTL_CGNPINNAK BIT(GC_USB_DCTL_CGNPINNAK_LSB)
+#define DCTL_PWRONPRGDONE BIT(GC_USB_DCTL_PWRONPRGDONE_LSB)
 
 /* Device Endpoint Common IN Interrupt Mask bits */
-#define DIEPMSK_AHBERRMSK             BIT(GC_USB_DIEPMSK_AHBERRMSK_LSB)
-#define DIEPMSK_BNAININTRMSK          BIT(GC_USB_DIEPMSK_BNAININTRMSK_LSB)
-#define DIEPMSK_EPDISBLDMSK           BIT(GC_USB_DIEPMSK_EPDISBLDMSK_LSB)
-#define DIEPMSK_INEPNAKEFFMSK         BIT(GC_USB_DIEPMSK_INEPNAKEFFMSK_LSB)
-#define DIEPMSK_INTKNEPMISMSK         BIT(GC_USB_DIEPMSK_INTKNEPMISMSK_LSB)
-#define DIEPMSK_INTKNTXFEMPMSK        BIT(GC_USB_DIEPMSK_INTKNTXFEMPMSK_LSB)
-#define DIEPMSK_NAKMSK                BIT(GC_USB_DIEPMSK_NAKMSK_LSB)
-#define DIEPMSK_TIMEOUTMSK            BIT(GC_USB_DIEPMSK_TIMEOUTMSK_LSB)
-#define DIEPMSK_TXFIFOUNDRNMSK        BIT(GC_USB_DIEPMSK_TXFIFOUNDRNMSK_LSB)
-#define DIEPMSK_XFERCOMPLMSK          BIT(GC_USB_DIEPMSK_XFERCOMPLMSK_LSB)
+#define DIEPMSK_AHBERRMSK BIT(GC_USB_DIEPMSK_AHBERRMSK_LSB)
+#define DIEPMSK_BNAININTRMSK BIT(GC_USB_DIEPMSK_BNAININTRMSK_LSB)
+#define DIEPMSK_EPDISBLDMSK BIT(GC_USB_DIEPMSK_EPDISBLDMSK_LSB)
+#define DIEPMSK_INEPNAKEFFMSK BIT(GC_USB_DIEPMSK_INEPNAKEFFMSK_LSB)
+#define DIEPMSK_INTKNEPMISMSK BIT(GC_USB_DIEPMSK_INTKNEPMISMSK_LSB)
+#define DIEPMSK_INTKNTXFEMPMSK BIT(GC_USB_DIEPMSK_INTKNTXFEMPMSK_LSB)
+#define DIEPMSK_NAKMSK BIT(GC_USB_DIEPMSK_NAKMSK_LSB)
+#define DIEPMSK_TIMEOUTMSK BIT(GC_USB_DIEPMSK_TIMEOUTMSK_LSB)
+#define DIEPMSK_TXFIFOUNDRNMSK BIT(GC_USB_DIEPMSK_TXFIFOUNDRNMSK_LSB)
+#define DIEPMSK_XFERCOMPLMSK BIT(GC_USB_DIEPMSK_XFERCOMPLMSK_LSB)
 
 /* Device Endpoint Common OUT Interrupt Mask bits */
-#define DOEPMSK_AHBERRMSK             BIT(GC_USB_DOEPMSK_AHBERRMSK_LSB)
-#define DOEPMSK_BBLEERRMSK            BIT(GC_USB_DOEPMSK_BBLEERRMSK_LSB)
-#define DOEPMSK_BNAOUTINTRMSK         BIT(GC_USB_DOEPMSK_BNAOUTINTRMSK_LSB)
-#define DOEPMSK_EPDISBLDMSK           BIT(GC_USB_DOEPMSK_EPDISBLDMSK_LSB)
-#define DOEPMSK_NAKMSK                BIT(GC_USB_DOEPMSK_NAKMSK_LSB)
-#define DOEPMSK_NYETMSK               BIT(GC_USB_DOEPMSK_NYETMSK_LSB)
-#define DOEPMSK_OUTPKTERRMSK          BIT(GC_USB_DOEPMSK_OUTPKTERRMSK_LSB)
-#define DOEPMSK_OUTTKNEPDISMSK        BIT(GC_USB_DOEPMSK_OUTTKNEPDISMSK_LSB)
-#define DOEPMSK_SETUPMSK              BIT(GC_USB_DOEPMSK_SETUPMSK_LSB)
-#define DOEPMSK_STSPHSERCVDMSK        BIT(GC_USB_DOEPMSK_STSPHSERCVDMSK_LSB)
-#define DOEPMSK_XFERCOMPLMSK          BIT(GC_USB_DOEPMSK_XFERCOMPLMSK_LSB)
+#define DOEPMSK_AHBERRMSK BIT(GC_USB_DOEPMSK_AHBERRMSK_LSB)
+#define DOEPMSK_BBLEERRMSK BIT(GC_USB_DOEPMSK_BBLEERRMSK_LSB)
+#define DOEPMSK_BNAOUTINTRMSK BIT(GC_USB_DOEPMSK_BNAOUTINTRMSK_LSB)
+#define DOEPMSK_EPDISBLDMSK BIT(GC_USB_DOEPMSK_EPDISBLDMSK_LSB)
+#define DOEPMSK_NAKMSK BIT(GC_USB_DOEPMSK_NAKMSK_LSB)
+#define DOEPMSK_NYETMSK BIT(GC_USB_DOEPMSK_NYETMSK_LSB)
+#define DOEPMSK_OUTPKTERRMSK BIT(GC_USB_DOEPMSK_OUTPKTERRMSK_LSB)
+#define DOEPMSK_OUTTKNEPDISMSK BIT(GC_USB_DOEPMSK_OUTTKNEPDISMSK_LSB)
+#define DOEPMSK_SETUPMSK BIT(GC_USB_DOEPMSK_SETUPMSK_LSB)
+#define DOEPMSK_STSPHSERCVDMSK BIT(GC_USB_DOEPMSK_STSPHSERCVDMSK_LSB)
+#define DOEPMSK_XFERCOMPLMSK BIT(GC_USB_DOEPMSK_XFERCOMPLMSK_LSB)
 
 /* Device Endpoint-n IN Interrupt Register bits */
-#define DIEPINT_AHBERR             BIT(GC_USB_DIEPINT0_AHBERR_LSB)
-#define DIEPINT_BBLEERR            BIT(GC_USB_DIEPINT0_BBLEERR_LSB)
-#define DIEPINT_BNAINTR            BIT(GC_USB_DIEPINT0_BNAINTR_LSB)
-#define DIEPINT_EPDISBLD           BIT(GC_USB_DIEPINT0_EPDISBLD_LSB)
-#define DIEPINT_INEPNAKEFF         BIT(GC_USB_DIEPINT0_INEPNAKEFF_LSB)
-#define DIEPINT_INTKNEPMIS         BIT(GC_USB_DIEPINT0_INTKNEPMIS_LSB)
-#define DIEPINT_INTKNTXFEMP        BIT(GC_USB_DIEPINT0_INTKNTXFEMP_LSB)
-#define DIEPINT_NAKINTRPT          BIT(GC_USB_DIEPINT0_NAKINTRPT_LSB)
-#define DIEPINT_NYETINTRPT         BIT(GC_USB_DIEPINT0_NYETINTRPT_LSB)
-#define DIEPINT_PKTDRPSTS          BIT(GC_USB_DIEPINT0_PKTDRPSTS_LSB)
-#define DIEPINT_TIMEOUT            BIT(GC_USB_DIEPINT0_TIMEOUT_LSB)
-#define DIEPINT_TXFEMP             BIT(GC_USB_DIEPINT0_TXFEMP_LSB)
-#define DIEPINT_TXFIFOUNDRN        BIT(GC_USB_DIEPINT0_TXFIFOUNDRN_LSB)
-#define DIEPINT_XFERCOMPL          BIT(GC_USB_DIEPINT0_XFERCOMPL_LSB)
+#define DIEPINT_AHBERR BIT(GC_USB_DIEPINT0_AHBERR_LSB)
+#define DIEPINT_BBLEERR BIT(GC_USB_DIEPINT0_BBLEERR_LSB)
+#define DIEPINT_BNAINTR BIT(GC_USB_DIEPINT0_BNAINTR_LSB)
+#define DIEPINT_EPDISBLD BIT(GC_USB_DIEPINT0_EPDISBLD_LSB)
+#define DIEPINT_INEPNAKEFF BIT(GC_USB_DIEPINT0_INEPNAKEFF_LSB)
+#define DIEPINT_INTKNEPMIS BIT(GC_USB_DIEPINT0_INTKNEPMIS_LSB)
+#define DIEPINT_INTKNTXFEMP BIT(GC_USB_DIEPINT0_INTKNTXFEMP_LSB)
+#define DIEPINT_NAKINTRPT BIT(GC_USB_DIEPINT0_NAKINTRPT_LSB)
+#define DIEPINT_NYETINTRPT BIT(GC_USB_DIEPINT0_NYETINTRPT_LSB)
+#define DIEPINT_PKTDRPSTS BIT(GC_USB_DIEPINT0_PKTDRPSTS_LSB)
+#define DIEPINT_TIMEOUT BIT(GC_USB_DIEPINT0_TIMEOUT_LSB)
+#define DIEPINT_TXFEMP BIT(GC_USB_DIEPINT0_TXFEMP_LSB)
+#define DIEPINT_TXFIFOUNDRN BIT(GC_USB_DIEPINT0_TXFIFOUNDRN_LSB)
+#define DIEPINT_XFERCOMPL BIT(GC_USB_DIEPINT0_XFERCOMPL_LSB)
 
 /* Device Endpoint-n OUT Interrupt Register bits */
-#define DOEPINT_AHBERR             BIT(GC_USB_DOEPINT0_AHBERR_LSB)
-#define DOEPINT_BACK2BACKSETUP     BIT(GC_USB_DOEPINT0_BACK2BACKSETUP_LSB)
-#define DOEPINT_BBLEERR            BIT(GC_USB_DOEPINT0_BBLEERR_LSB)
-#define DOEPINT_BNAINTR            BIT(GC_USB_DOEPINT0_BNAINTR_LSB)
-#define DOEPINT_EPDISBLD           BIT(GC_USB_DOEPINT0_EPDISBLD_LSB)
-#define DOEPINT_NAKINTRPT          BIT(GC_USB_DOEPINT0_NAKINTRPT_LSB)
-#define DOEPINT_NYETINTRPT         BIT(GC_USB_DOEPINT0_NYETINTRPT_LSB)
-#define DOEPINT_OUTPKTERR          BIT(GC_USB_DOEPINT0_OUTPKTERR_LSB)
-#define DOEPINT_OUTTKNEPDIS        BIT(GC_USB_DOEPINT0_OUTTKNEPDIS_LSB)
-#define DOEPINT_PKTDRPSTS          BIT(GC_USB_DOEPINT0_PKTDRPSTS_LSB)
-#define DOEPINT_SETUP              BIT(GC_USB_DOEPINT0_SETUP_LSB)
-#define DOEPINT_STSPHSERCVD        BIT(GC_USB_DOEPINT0_STSPHSERCVD_LSB)
-#define DOEPINT_STUPPKTRCVD        BIT(GC_USB_DOEPINT0_STUPPKTRCVD_LSB)
-#define DOEPINT_XFERCOMPL          BIT(GC_USB_DOEPINT0_XFERCOMPL_LSB)
+#define DOEPINT_AHBERR BIT(GC_USB_DOEPINT0_AHBERR_LSB)
+#define DOEPINT_BACK2BACKSETUP BIT(GC_USB_DOEPINT0_BACK2BACKSETUP_LSB)
+#define DOEPINT_BBLEERR BIT(GC_USB_DOEPINT0_BBLEERR_LSB)
+#define DOEPINT_BNAINTR BIT(GC_USB_DOEPINT0_BNAINTR_LSB)
+#define DOEPINT_EPDISBLD BIT(GC_USB_DOEPINT0_EPDISBLD_LSB)
+#define DOEPINT_NAKINTRPT BIT(GC_USB_DOEPINT0_NAKINTRPT_LSB)
+#define DOEPINT_NYETINTRPT BIT(GC_USB_DOEPINT0_NYETINTRPT_LSB)
+#define DOEPINT_OUTPKTERR BIT(GC_USB_DOEPINT0_OUTPKTERR_LSB)
+#define DOEPINT_OUTTKNEPDIS BIT(GC_USB_DOEPINT0_OUTTKNEPDIS_LSB)
+#define DOEPINT_PKTDRPSTS BIT(GC_USB_DOEPINT0_PKTDRPSTS_LSB)
+#define DOEPINT_SETUP BIT(GC_USB_DOEPINT0_SETUP_LSB)
+#define DOEPINT_STSPHSERCVD BIT(GC_USB_DOEPINT0_STSPHSERCVD_LSB)
+#define DOEPINT_STUPPKTRCVD BIT(GC_USB_DOEPINT0_STUPPKTRCVD_LSB)
+#define DOEPINT_XFERCOMPL BIT(GC_USB_DOEPINT0_XFERCOMPL_LSB)
 
-#define DXEPCTL_EPTYPE_CTRL           (0 << GC_USB_DIEPCTL0_EPTYPE_LSB)
-#define DXEPCTL_EPTYPE_ISO            (1 << GC_USB_DIEPCTL0_EPTYPE_LSB)
-#define DXEPCTL_EPTYPE_BULK           (2 << GC_USB_DIEPCTL0_EPTYPE_LSB)
-#define DXEPCTL_EPTYPE_INT            (3 << GC_USB_DIEPCTL0_EPTYPE_LSB)
-#define DXEPCTL_EPTYPE_MASK           GC_USB_DIEPCTL0_EPTYPE_MASK
-#define DXEPCTL_TXFNUM(n)             ((n) << GC_USB_DIEPCTL1_TXFNUM_LSB)
-#define DXEPCTL_STALL                 BIT(GC_USB_DIEPCTL0_STALL_LSB)
-#define DXEPCTL_CNAK                  BIT(GC_USB_DIEPCTL0_CNAK_LSB)
-#define DXEPCTL_DPID                  BIT(GC_USB_DIEPCTL0_DPID_LSB)
-#define DXEPCTL_SNAK                  BIT(GC_USB_DIEPCTL0_SNAK_LSB)
-#define DXEPCTL_NAKSTS                BIT(GC_USB_DIEPCTL0_NAKSTS_LSB)
-#define DXEPCTL_EPENA                 BIT(GC_USB_DIEPCTL0_EPENA_LSB)
-#define DXEPCTL_EPDIS                 BIT(GC_USB_DIEPCTL0_EPDIS_LSB)
-#define DXEPCTL_USBACTEP              BIT(GC_USB_DIEPCTL0_USBACTEP_LSB)
-#define DXEPCTL_MPS64                 (0 << GC_USB_DIEPCTL0_MPS_LSB)
-#define DXEPCTL_MPS(cnt)              ((cnt) << GC_USB_DIEPCTL1_MPS_LSB)
+#define DXEPCTL_EPTYPE_CTRL (0 << GC_USB_DIEPCTL0_EPTYPE_LSB)
+#define DXEPCTL_EPTYPE_ISO (1 << GC_USB_DIEPCTL0_EPTYPE_LSB)
+#define DXEPCTL_EPTYPE_BULK (2 << GC_USB_DIEPCTL0_EPTYPE_LSB)
+#define DXEPCTL_EPTYPE_INT (3 << GC_USB_DIEPCTL0_EPTYPE_LSB)
+#define DXEPCTL_EPTYPE_MASK GC_USB_DIEPCTL0_EPTYPE_MASK
+#define DXEPCTL_TXFNUM(n) ((n) << GC_USB_DIEPCTL1_TXFNUM_LSB)
+#define DXEPCTL_STALL BIT(GC_USB_DIEPCTL0_STALL_LSB)
+#define DXEPCTL_CNAK BIT(GC_USB_DIEPCTL0_CNAK_LSB)
+#define DXEPCTL_DPID BIT(GC_USB_DIEPCTL0_DPID_LSB)
+#define DXEPCTL_SNAK BIT(GC_USB_DIEPCTL0_SNAK_LSB)
+#define DXEPCTL_NAKSTS BIT(GC_USB_DIEPCTL0_NAKSTS_LSB)
+#define DXEPCTL_EPENA BIT(GC_USB_DIEPCTL0_EPENA_LSB)
+#define DXEPCTL_EPDIS BIT(GC_USB_DIEPCTL0_EPDIS_LSB)
+#define DXEPCTL_USBACTEP BIT(GC_USB_DIEPCTL0_USBACTEP_LSB)
+#define DXEPCTL_MPS64 (0 << GC_USB_DIEPCTL0_MPS_LSB)
+#define DXEPCTL_MPS(cnt) ((cnt) << GC_USB_DIEPCTL1_MPS_LSB)
 
-#define DXEPTSIZ_SUPCNT(n)            ((n) << GC_USB_DOEPTSIZ0_SUPCNT_LSB)
-#define DXEPTSIZ_PKTCNT(n)            ((n) << GC_USB_DIEPTSIZ0_PKTCNT_LSB)
-#define DXEPTSIZ_XFERSIZE(n)          ((n) << GC_USB_DIEPTSIZ0_XFERSIZE_LSB)
-
-#define DOEPDMA_BS_HOST_RDY           (0 << 30)
-#define DOEPDMA_BS_DMA_BSY            (1 << 30)
-#define DOEPDMA_BS_DMA_DONE           (2 << 30)
-#define DOEPDMA_BS_HOST_BSY           (3 << 30)
-#define DOEPDMA_BS_MASK               (3 << 30)
-#define DOEPDMA_RXSTS_MASK            (3 << 28)
-#define DOEPDMA_LAST                  BIT(27)
-#define DOEPDMA_SP                    BIT(26)
-#define DOEPDMA_IOC                   BIT(25)
-#define DOEPDMA_SR                    BIT(24)
-#define DOEPDMA_MTRF                  BIT(23)
-#define DOEPDMA_NAK                   BIT(16)
-#define DOEPDMA_RXBYTES(n)            (((n) & 0xFFFF) << 0)
-#define DOEPDMA_RXBYTES_MASK          (0xFFFF << 0)
-
-#define DIEPDMA_BS_HOST_RDY           (0 << 30)
-#define DIEPDMA_BS_DMA_BSY            (1 << 30)
-#define DIEPDMA_BS_DMA_DONE           (2 << 30)
-#define DIEPDMA_BS_HOST_BSY           (3 << 30)
-#define DIEPDMA_BS_MASK               (3 << 30)
-#define DIEPDMA_TXSTS_MASK            (3 << 28)
-#define DIEPDMA_LAST                  BIT(27)
-#define DIEPDMA_SP                    BIT(26)
-#define DIEPDMA_IOC                   BIT(25)
-#define DIEPDMA_TXBYTES(n)            (((n) & 0xFFFF) << 0)
-#define DIEPDMA_TXBYTES_MASK          (0xFFFF << 0)
+#define DXEPTSIZ_SUPCNT(n) ((n) << GC_USB_DOEPTSIZ0_SUPCNT_LSB)
+#define DXEPTSIZ_PKTCNT(n) ((n) << GC_USB_DIEPTSIZ0_PKTCNT_LSB)
+#define DXEPTSIZ_XFERSIZE(n) ((n) << GC_USB_DIEPTSIZ0_XFERSIZE_LSB)
 
+#define DOEPDMA_BS_HOST_RDY (0 << 30)
+#define DOEPDMA_BS_DMA_BSY (1 << 30)
+#define DOEPDMA_BS_DMA_DONE (2 << 30)
+#define DOEPDMA_BS_HOST_BSY (3 << 30)
+#define DOEPDMA_BS_MASK (3 << 30)
+#define DOEPDMA_RXSTS_MASK (3 << 28)
+#define DOEPDMA_LAST BIT(27)
+#define DOEPDMA_SP BIT(26)
+#define DOEPDMA_IOC BIT(25)
+#define DOEPDMA_SR BIT(24)
+#define DOEPDMA_MTRF BIT(23)
+#define DOEPDMA_NAK BIT(16)
+#define DOEPDMA_RXBYTES(n) (((n)&0xFFFF) << 0)
+#define DOEPDMA_RXBYTES_MASK (0xFFFF << 0)
 
+#define DIEPDMA_BS_HOST_RDY (0 << 30)
+#define DIEPDMA_BS_DMA_BSY (1 << 30)
+#define DIEPDMA_BS_DMA_DONE (2 << 30)
+#define DIEPDMA_BS_HOST_BSY (3 << 30)
+#define DIEPDMA_BS_MASK (3 << 30)
+#define DIEPDMA_TXSTS_MASK (3 << 28)
+#define DIEPDMA_LAST BIT(27)
+#define DIEPDMA_SP BIT(26)
+#define DIEPDMA_IOC BIT(25)
+#define DIEPDMA_TXBYTES(n) (((n)&0xFFFF) << 0)
+#define DIEPDMA_TXBYTES_MASK (0xFFFF << 0)
 
 /* Register defs referenced from DWC block in CR50. This is not a native
  * ST block, so we'll use this modified regdefs list.
  */
 
-#define GC_USB_FS_BASE_ADDR                        0x50000000
-#define GC_USB_HS_BASE_ADDR                        0x40040000
+#define GC_USB_FS_BASE_ADDR 0x50000000
+#define GC_USB_HS_BASE_ADDR 0x40040000
 #ifdef CONFIG_USB_DWC_FS
-#define GC_USB_BASE_ADDR                         GC_USB_FS_BASE_ADDR
+#define GC_USB_BASE_ADDR GC_USB_FS_BASE_ADDR
 #else
-#define GC_USB_BASE_ADDR                         GC_USB_HS_BASE_ADDR
+#define GC_USB_BASE_ADDR GC_USB_HS_BASE_ADDR
 #endif
 
-#define GC_USB_GOTGCTL_OFFSET                    0x0
-#define GC_USB_GOTGCTL_DEFAULT                   0x0
-#define GC_USB_GOTGINT_OFFSET                    0x4
-#define GC_USB_GOTGINT_DEFAULT                   0x0
-#define GC_USB_GAHBCFG_OFFSET                    0x8
-#define GC_USB_GAHBCFG_DEFAULT                   0x0
-#define GC_USB_GUSBCFG_OFFSET                    0xc
-#define GC_USB_GUSBCFG_DEFAULT                   0x0
-#define GC_USB_GRSTCTL_OFFSET                    0x10
-#define GC_USB_GRSTCTL_DEFAULT                   0x0
-#define GC_USB_GINTSTS_OFFSET                    0x14
-#define GC_USB_GINTSTS_DEFAULT                   0x0
-#define GC_USB_GINTMSK_OFFSET                    0x18
-#define GC_USB_GINTMSK_DEFAULT                   0x0
-#define GC_USB_GRXSTSR_OFFSET                    0x1c
-#define GC_USB_GRXSTSR_DEFAULT                   0x0
-#define GC_USB_GRXSTSP_OFFSET                    0x20
-#define GC_USB_GRXSTSP_DEFAULT                   0x0
-#define GC_USB_GRXFSIZ_OFFSET                    0x24
-#define GC_USB_GRXFSIZ_DEFAULT                   0x0
-#define GC_USB_GNPTXFSIZ_OFFSET                  0x28
-#define GC_USB_GNPTXFSIZ_DEFAULT                 0x0
+#define GC_USB_GOTGCTL_OFFSET 0x0
+#define GC_USB_GOTGCTL_DEFAULT 0x0
+#define GC_USB_GOTGINT_OFFSET 0x4
+#define GC_USB_GOTGINT_DEFAULT 0x0
+#define GC_USB_GAHBCFG_OFFSET 0x8
+#define GC_USB_GAHBCFG_DEFAULT 0x0
+#define GC_USB_GUSBCFG_OFFSET 0xc
+#define GC_USB_GUSBCFG_DEFAULT 0x0
+#define GC_USB_GRSTCTL_OFFSET 0x10
+#define GC_USB_GRSTCTL_DEFAULT 0x0
+#define GC_USB_GINTSTS_OFFSET 0x14
+#define GC_USB_GINTSTS_DEFAULT 0x0
+#define GC_USB_GINTMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_DEFAULT 0x0
+#define GC_USB_GRXSTSR_OFFSET 0x1c
+#define GC_USB_GRXSTSR_DEFAULT 0x0
+#define GC_USB_GRXSTSP_OFFSET 0x20
+#define GC_USB_GRXSTSP_DEFAULT 0x0
+#define GC_USB_GRXFSIZ_OFFSET 0x24
+#define GC_USB_GRXFSIZ_DEFAULT 0x0
+#define GC_USB_GNPTXFSIZ_OFFSET 0x28
+#define GC_USB_GNPTXFSIZ_DEFAULT 0x0
 
-#define GC_USB_GCCFG_OFFSET                      0x38
-#define GC_USB_GCCFG_DEFAULT                     0x0
-#define GC_USB_GUID_OFFSET                       0x3c
-#define GC_USB_GUID_DEFAULT                      0x0
-#define GC_USB_GSNPSID_OFFSET                    0x40
-#define GC_USB_GSNPSID_DEFAULT                   0x0
-#define GC_USB_GHWCFG1_OFFSET                    0x44
-#define GC_USB_GHWCFG1_DEFAULT                   0x0
-#define GC_USB_GHWCFG2_OFFSET                    0x48
-#define GC_USB_GHWCFG2_DEFAULT                   0x0
-#define GC_USB_GHWCFG3_OFFSET                    0x4c
-#define GC_USB_GHWCFG3_DEFAULT                   0x0
-#define GC_USB_GHWCFG4_OFFSET                    0x50
-#define GC_USB_GHWCFG4_DEFAULT                   0x0
-#define GC_USB_GDFIFOCFG_OFFSET                  0x5c
-#define GC_USB_GDFIFOCFG_DEFAULT                 0x0
-#define GC_USB_DIEPTXF1_OFFSET                   0x104
-#define GC_USB_DIEPTXF1_DEFAULT                  0x1000
-#define GC_USB_DIEPTXF2_OFFSET                   0x108
-#define GC_USB_DIEPTXF2_DEFAULT                  0x0
-#define GC_USB_DIEPTXF3_OFFSET                   0x10c
-#define GC_USB_DIEPTXF3_DEFAULT                  0x0
-#define GC_USB_DIEPTXF4_OFFSET                   0x110
-#define GC_USB_DIEPTXF4_DEFAULT                  0x0
-#define GC_USB_DIEPTXF5_OFFSET                   0x114
-#define GC_USB_DIEPTXF5_DEFAULT                  0x0
-#define GC_USB_DIEPTXF6_OFFSET                   0x118
-#define GC_USB_DIEPTXF6_DEFAULT                  0x0
-#define GC_USB_DIEPTXF7_OFFSET                   0x11c
-#define GC_USB_DIEPTXF7_DEFAULT                  0x0
-#define GC_USB_DIEPTXF8_OFFSET                   0x120
-#define GC_USB_DIEPTXF8_DEFAULT                  0x0
-#define GC_USB_DIEPTXF9_OFFSET                   0x124
-#define GC_USB_DIEPTXF9_DEFAULT                  0x0
-#define GC_USB_DIEPTXF10_OFFSET                  0x128
-#define GC_USB_DIEPTXF10_DEFAULT                 0x0
-#define GC_USB_DIEPTXF11_OFFSET                  0x12c
-#define GC_USB_DIEPTXF11_DEFAULT                 0x0
-#define GC_USB_DIEPTXF12_OFFSET                  0x130
-#define GC_USB_DIEPTXF12_DEFAULT                 0x0
-#define GC_USB_DIEPTXF13_OFFSET                  0x134
-#define GC_USB_DIEPTXF13_DEFAULT                 0x0
-#define GC_USB_DIEPTXF14_OFFSET                  0x138
-#define GC_USB_DIEPTXF14_DEFAULT                 0x0
-#define GC_USB_DIEPTXF15_OFFSET                  0x13c
-#define GC_USB_DIEPTXF15_DEFAULT                 0x0
-#define GC_USB_DCFG_OFFSET                       0x800
-#define GC_USB_DCFG_DEFAULT                      0x8000000
-#define GC_USB_DCTL_OFFSET                       0x804
-#define GC_USB_DCTL_DEFAULT                      0x0
-#define GC_USB_DSTS_OFFSET                       0x808
-#define GC_USB_DSTS_DEFAULT                      0x0
-#define GC_USB_DIEPMSK_OFFSET                    0x810
-#define GC_USB_DIEPMSK_DEFAULT                   0x80
-#define GC_USB_DOEPMSK_OFFSET                    0x814
-#define GC_USB_DOEPMSK_DEFAULT                   0x0
-#define GC_USB_DAINT_OFFSET                      0x818
-#define GC_USB_DAINT_DEFAULT                     0x0
-#define GC_USB_DAINTMSK_OFFSET                   0x81c
-#define GC_USB_DAINTMSK_DEFAULT                  0x0
-#define GC_USB_DVBUSDIS_OFFSET                   0x828
-#define GC_USB_DVBUSDIS_DEFAULT                  0x0
-#define GC_USB_DVBUSPULSE_OFFSET                 0x82c
-#define GC_USB_DVBUSPULSE_DEFAULT                0x0
-#define GC_USB_DTHRCTL_OFFSET                    0x830
-#define GC_USB_DTHRCTL_DEFAULT                   0x0
-#define GC_USB_DIEPEMPMSK_OFFSET                 0x834
-#define GC_USB_DIEPEMPMSK_DEFAULT                0x0
-#define GC_USB_DIEPCTL0_OFFSET                   0x900
-#define GC_USB_DIEPCTL0_DEFAULT                  0x0
-#define GC_USB_DIEPINT0_OFFSET                   0x908
-#define GC_USB_DIEPINT0_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ0_OFFSET                  0x910
-#define GC_USB_DIEPTSIZ0_DEFAULT                 0x0
-#define GC_USB_DIEPDMA0_OFFSET                   0x914
-#define GC_USB_DIEPDMA0_DEFAULT                  0x0
-#define GC_USB_DTXFSTS0_OFFSET                   0x918
-#define GC_USB_DTXFSTS0_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB0_OFFSET                  0x91c
-#define GC_USB_DIEPDMAB0_DEFAULT                 0x0
-#define GC_USB_DIEPCTL1_OFFSET                   0x920
-#define GC_USB_DIEPCTL1_DEFAULT                  0x0
-#define GC_USB_DIEPINT1_OFFSET                   0x928
-#define GC_USB_DIEPINT1_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ1_OFFSET                  0x930
-#define GC_USB_DIEPTSIZ1_DEFAULT                 0x0
-#define GC_USB_DIEPDMA1_OFFSET                   0x934
-#define GC_USB_DIEPDMA1_DEFAULT                  0x0
-#define GC_USB_DTXFSTS1_OFFSET                   0x938
-#define GC_USB_DTXFSTS1_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB1_OFFSET                  0x93c
-#define GC_USB_DIEPDMAB1_DEFAULT                 0x0
-#define GC_USB_DIEPCTL2_OFFSET                   0x940
-#define GC_USB_DIEPCTL2_DEFAULT                  0x0
-#define GC_USB_DIEPINT2_OFFSET                   0x948
-#define GC_USB_DIEPINT2_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ2_OFFSET                  0x950
-#define GC_USB_DIEPTSIZ2_DEFAULT                 0x0
-#define GC_USB_DIEPDMA2_OFFSET                   0x954
-#define GC_USB_DIEPDMA2_DEFAULT                  0x0
-#define GC_USB_DTXFSTS2_OFFSET                   0x958
-#define GC_USB_DTXFSTS2_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB2_OFFSET                  0x95c
-#define GC_USB_DIEPDMAB2_DEFAULT                 0x0
-#define GC_USB_DIEPCTL3_OFFSET                   0x960
-#define GC_USB_DIEPCTL3_DEFAULT                  0x0
-#define GC_USB_DIEPINT3_OFFSET                   0x968
-#define GC_USB_DIEPINT3_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ3_OFFSET                  0x970
-#define GC_USB_DIEPTSIZ3_DEFAULT                 0x0
-#define GC_USB_DIEPDMA3_OFFSET                   0x974
-#define GC_USB_DIEPDMA3_DEFAULT                  0x0
-#define GC_USB_DTXFSTS3_OFFSET                   0x978
-#define GC_USB_DTXFSTS3_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB3_OFFSET                  0x97c
-#define GC_USB_DIEPDMAB3_DEFAULT                 0x0
-#define GC_USB_DIEPCTL4_OFFSET                   0x980
-#define GC_USB_DIEPCTL4_DEFAULT                  0x0
-#define GC_USB_DIEPINT4_OFFSET                   0x988
-#define GC_USB_DIEPINT4_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ4_OFFSET                  0x990
-#define GC_USB_DIEPTSIZ4_DEFAULT                 0x0
-#define GC_USB_DIEPDMA4_OFFSET                   0x994
-#define GC_USB_DIEPDMA4_DEFAULT                  0x0
-#define GC_USB_DTXFSTS4_OFFSET                   0x998
-#define GC_USB_DTXFSTS4_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB4_OFFSET                  0x99c
-#define GC_USB_DIEPDMAB4_DEFAULT                 0x0
-#define GC_USB_DIEPCTL5_OFFSET                   0x9a0
-#define GC_USB_DIEPCTL5_DEFAULT                  0x0
-#define GC_USB_DIEPINT5_OFFSET                   0x9a8
-#define GC_USB_DIEPINT5_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ5_OFFSET                  0x9b0
-#define GC_USB_DIEPTSIZ5_DEFAULT                 0x0
-#define GC_USB_DIEPDMA5_OFFSET                   0x9b4
-#define GC_USB_DIEPDMA5_DEFAULT                  0x0
-#define GC_USB_DTXFSTS5_OFFSET                   0x9b8
-#define GC_USB_DTXFSTS5_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB5_OFFSET                  0x9bc
-#define GC_USB_DIEPDMAB5_DEFAULT                 0x0
-#define GC_USB_DIEPCTL6_OFFSET                   0x9c0
-#define GC_USB_DIEPCTL6_DEFAULT                  0x0
-#define GC_USB_DIEPINT6_OFFSET                   0x9c8
-#define GC_USB_DIEPINT6_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ6_OFFSET                  0x9d0
-#define GC_USB_DIEPTSIZ6_DEFAULT                 0x0
-#define GC_USB_DIEPDMA6_OFFSET                   0x9d4
-#define GC_USB_DIEPDMA6_DEFAULT                  0x0
-#define GC_USB_DTXFSTS6_OFFSET                   0x9d8
-#define GC_USB_DTXFSTS6_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB6_OFFSET                  0x9dc
-#define GC_USB_DIEPDMAB6_DEFAULT                 0x0
-#define GC_USB_DIEPCTL7_OFFSET                   0x9e0
-#define GC_USB_DIEPCTL7_DEFAULT                  0x0
-#define GC_USB_DIEPINT7_OFFSET                   0x9e8
-#define GC_USB_DIEPINT7_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ7_OFFSET                  0x9f0
-#define GC_USB_DIEPTSIZ7_DEFAULT                 0x0
-#define GC_USB_DIEPDMA7_OFFSET                   0x9f4
-#define GC_USB_DIEPDMA7_DEFAULT                  0x0
-#define GC_USB_DTXFSTS7_OFFSET                   0x9f8
-#define GC_USB_DTXFSTS7_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB7_OFFSET                  0x9fc
-#define GC_USB_DIEPDMAB7_DEFAULT                 0x0
-#define GC_USB_DIEPCTL8_OFFSET                   0xa00
-#define GC_USB_DIEPCTL8_DEFAULT                  0x0
-#define GC_USB_DIEPINT8_OFFSET                   0xa08
-#define GC_USB_DIEPINT8_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ8_OFFSET                  0xa10
-#define GC_USB_DIEPTSIZ8_DEFAULT                 0x0
-#define GC_USB_DIEPDMA8_OFFSET                   0xa14
-#define GC_USB_DIEPDMA8_DEFAULT                  0x0
-#define GC_USB_DTXFSTS8_OFFSET                   0xa18
-#define GC_USB_DTXFSTS8_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB8_OFFSET                  0xa1c
-#define GC_USB_DIEPDMAB8_DEFAULT                 0x0
-#define GC_USB_DIEPCTL9_OFFSET                   0xa20
-#define GC_USB_DIEPCTL9_DEFAULT                  0x0
-#define GC_USB_DIEPINT9_OFFSET                   0xa28
-#define GC_USB_DIEPINT9_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ9_OFFSET                  0xa30
-#define GC_USB_DIEPTSIZ9_DEFAULT                 0x0
-#define GC_USB_DIEPDMA9_OFFSET                   0xa34
-#define GC_USB_DIEPDMA9_DEFAULT                  0x0
-#define GC_USB_DTXFSTS9_OFFSET                   0xa38
-#define GC_USB_DTXFSTS9_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB9_OFFSET                  0xa3c
-#define GC_USB_DIEPDMAB9_DEFAULT                 0x0
-#define GC_USB_DIEPCTL10_OFFSET                  0xa40
-#define GC_USB_DIEPCTL10_DEFAULT                 0x0
-#define GC_USB_DIEPINT10_OFFSET                  0xa48
-#define GC_USB_DIEPINT10_DEFAULT                 0x0
-#define GC_USB_DIEPTSIZ10_OFFSET                 0xa50
-#define GC_USB_DIEPTSIZ10_DEFAULT                0x0
-#define GC_USB_DIEPDMA10_OFFSET                  0xa54
-#define GC_USB_DIEPDMA10_DEFAULT                 0x0
-#define GC_USB_DTXFSTS10_OFFSET                  0xa58
-#define GC_USB_DTXFSTS10_DEFAULT                 0x0
-#define GC_USB_DIEPDMAB10_OFFSET                 0xa5c
-#define GC_USB_DIEPDMAB10_DEFAULT                0x0
-#define GC_USB_DIEPCTL11_OFFSET                  0xa60
-#define GC_USB_DIEPCTL11_DEFAULT                 0x0
-#define GC_USB_DIEPINT11_OFFSET                  0xa68
-#define GC_USB_DIEPINT11_DEFAULT                 0x0
-#define GC_USB_DIEPTSIZ11_OFFSET                 0xa70
-#define GC_USB_DIEPTSIZ11_DEFAULT                0x0
-#define GC_USB_DIEPDMA11_OFFSET                  0xa74
-#define GC_USB_DIEPDMA11_DEFAULT                 0x0
-#define GC_USB_DTXFSTS11_OFFSET                  0xa78
-#define GC_USB_DTXFSTS11_DEFAULT                 0x0
-#define GC_USB_DIEPDMAB11_OFFSET                 0xa7c
-#define GC_USB_DIEPDMAB11_DEFAULT                0x0
-#define GC_USB_DIEPCTL12_OFFSET                  0xa80
-#define GC_USB_DIEPCTL12_DEFAULT                 0x0
-#define GC_USB_DIEPINT12_OFFSET                  0xa88
-#define GC_USB_DIEPINT12_DEFAULT                 0x0
-#define GC_USB_DIEPTSIZ12_OFFSET                 0xa90
-#define GC_USB_DIEPTSIZ12_DEFAULT                0x0
-#define GC_USB_DIEPDMA12_OFFSET                  0xa94
-#define GC_USB_DIEPDMA12_DEFAULT                 0x0
-#define GC_USB_DTXFSTS12_OFFSET                  0xa98
-#define GC_USB_DTXFSTS12_DEFAULT                 0x0
-#define GC_USB_DIEPDMAB12_OFFSET                 0xa9c
-#define GC_USB_DIEPDMAB12_DEFAULT                0x0
-#define GC_USB_DIEPCTL13_OFFSET                  0xaa0
-#define GC_USB_DIEPCTL13_DEFAULT                 0x0
-#define GC_USB_DIEPINT13_OFFSET                  0xaa8
-#define GC_USB_DIEPINT13_DEFAULT                 0x0
-#define GC_USB_DIEPTSIZ13_OFFSET                 0xab0
-#define GC_USB_DIEPTSIZ13_DEFAULT                0x0
-#define GC_USB_DIEPDMA13_OFFSET                  0xab4
-#define GC_USB_DIEPDMA13_DEFAULT                 0x0
-#define GC_USB_DTXFSTS13_OFFSET                  0xab8
-#define GC_USB_DTXFSTS13_DEFAULT                 0x0
-#define GC_USB_DIEPDMAB13_OFFSET                 0xabc
-#define GC_USB_DIEPDMAB13_DEFAULT                0x0
-#define GC_USB_DIEPCTL14_OFFSET                  0xac0
-#define GC_USB_DIEPCTL14_DEFAULT                 0x0
-#define GC_USB_DIEPINT14_OFFSET                  0xac8
-#define GC_USB_DIEPINT14_DEFAULT                 0x0
-#define GC_USB_DIEPTSIZ14_OFFSET                 0xad0
-#define GC_USB_DIEPTSIZ14_DEFAULT                0x0
-#define GC_USB_DIEPDMA14_OFFSET                  0xad4
-#define GC_USB_DIEPDMA14_DEFAULT                 0x0
-#define GC_USB_DTXFSTS14_OFFSET                  0xad8
-#define GC_USB_DTXFSTS14_DEFAULT                 0x0
-#define GC_USB_DIEPDMAB14_OFFSET                 0xadc
-#define GC_USB_DIEPDMAB14_DEFAULT                0x0
-#define GC_USB_DIEPCTL15_OFFSET                  0xae0
-#define GC_USB_DIEPCTL15_DEFAULT                 0x0
-#define GC_USB_DIEPINT15_OFFSET                  0xae8
-#define GC_USB_DIEPINT15_DEFAULT                 0x0
-#define GC_USB_DIEPTSIZ15_OFFSET                 0xaf0
-#define GC_USB_DIEPTSIZ15_DEFAULT                0x0
-#define GC_USB_DIEPDMA15_OFFSET                  0xaf4
-#define GC_USB_DIEPDMA15_DEFAULT                 0x0
-#define GC_USB_DTXFSTS15_OFFSET                  0xaf8
-#define GC_USB_DTXFSTS15_DEFAULT                 0x0
-#define GC_USB_DIEPDMAB15_OFFSET                 0xafc
-#define GC_USB_DIEPDMAB15_DEFAULT                0x0
-#define GC_USB_DOEPCTL0_OFFSET                   0xb00
-#define GC_USB_DOEPCTL0_DEFAULT                  0x0
-#define GC_USB_DOEPINT0_OFFSET                   0xb08
-#define GC_USB_DOEPINT0_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ0_OFFSET                  0xb10
-#define GC_USB_DOEPTSIZ0_DEFAULT                 0x0
-#define GC_USB_DOEPDMA0_OFFSET                   0xb14
-#define GC_USB_DOEPDMA0_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB0_OFFSET                  0xb1c
-#define GC_USB_DOEPDMAB0_DEFAULT                 0x0
-#define GC_USB_DOEPCTL1_OFFSET                   0xb20
-#define GC_USB_DOEPCTL1_DEFAULT                  0x0
-#define GC_USB_DOEPINT1_OFFSET                   0xb28
-#define GC_USB_DOEPINT1_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ1_OFFSET                  0xb30
-#define GC_USB_DOEPTSIZ1_DEFAULT                 0x0
-#define GC_USB_DOEPDMA1_OFFSET                   0xb34
-#define GC_USB_DOEPDMA1_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB1_OFFSET                  0xb3c
-#define GC_USB_DOEPDMAB1_DEFAULT                 0x0
-#define GC_USB_DOEPCTL2_OFFSET                   0xb40
-#define GC_USB_DOEPCTL2_DEFAULT                  0x0
-#define GC_USB_DOEPINT2_OFFSET                   0xb48
-#define GC_USB_DOEPINT2_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ2_OFFSET                  0xb50
-#define GC_USB_DOEPTSIZ2_DEFAULT                 0x0
-#define GC_USB_DOEPDMA2_OFFSET                   0xb54
-#define GC_USB_DOEPDMA2_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB2_OFFSET                  0xb5c
-#define GC_USB_DOEPDMAB2_DEFAULT                 0x0
-#define GC_USB_DOEPCTL3_OFFSET                   0xb60
-#define GC_USB_DOEPCTL3_DEFAULT                  0x0
-#define GC_USB_DOEPINT3_OFFSET                   0xb68
-#define GC_USB_DOEPINT3_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ3_OFFSET                  0xb70
-#define GC_USB_DOEPTSIZ3_DEFAULT                 0x0
-#define GC_USB_DOEPDMA3_OFFSET                   0xb74
-#define GC_USB_DOEPDMA3_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB3_OFFSET                  0xb7c
-#define GC_USB_DOEPDMAB3_DEFAULT                 0x0
-#define GC_USB_DOEPCTL4_OFFSET                   0xb80
-#define GC_USB_DOEPCTL4_DEFAULT                  0x0
-#define GC_USB_DOEPINT4_OFFSET                   0xb88
-#define GC_USB_DOEPINT4_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ4_OFFSET                  0xb90
-#define GC_USB_DOEPTSIZ4_DEFAULT                 0x0
-#define GC_USB_DOEPDMA4_OFFSET                   0xb94
-#define GC_USB_DOEPDMA4_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB4_OFFSET                  0xb9c
-#define GC_USB_DOEPDMAB4_DEFAULT                 0x0
-#define GC_USB_DOEPCTL5_OFFSET                   0xba0
-#define GC_USB_DOEPCTL5_DEFAULT                  0x0
-#define GC_USB_DOEPINT5_OFFSET                   0xba8
-#define GC_USB_DOEPINT5_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ5_OFFSET                  0xbb0
-#define GC_USB_DOEPTSIZ5_DEFAULT                 0x0
-#define GC_USB_DOEPDMA5_OFFSET                   0xbb4
-#define GC_USB_DOEPDMA5_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB5_OFFSET                  0xbbc
-#define GC_USB_DOEPDMAB5_DEFAULT                 0x0
-#define GC_USB_DOEPCTL6_OFFSET                   0xbc0
-#define GC_USB_DOEPCTL6_DEFAULT                  0x0
-#define GC_USB_DOEPINT6_OFFSET                   0xbc8
-#define GC_USB_DOEPINT6_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ6_OFFSET                  0xbd0
-#define GC_USB_DOEPTSIZ6_DEFAULT                 0x0
-#define GC_USB_DOEPDMA6_OFFSET                   0xbd4
-#define GC_USB_DOEPDMA6_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB6_OFFSET                  0xbdc
-#define GC_USB_DOEPDMAB6_DEFAULT                 0x0
-#define GC_USB_DOEPCTL7_OFFSET                   0xbe0
-#define GC_USB_DOEPCTL7_DEFAULT                  0x0
-#define GC_USB_DOEPINT7_OFFSET                   0xbe8
-#define GC_USB_DOEPINT7_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ7_OFFSET                  0xbf0
-#define GC_USB_DOEPTSIZ7_DEFAULT                 0x0
-#define GC_USB_DOEPDMA7_OFFSET                   0xbf4
-#define GC_USB_DOEPDMA7_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB7_OFFSET                  0xbfc
-#define GC_USB_DOEPDMAB7_DEFAULT                 0x0
-#define GC_USB_DOEPCTL8_OFFSET                   0xc00
-#define GC_USB_DOEPCTL8_DEFAULT                  0x0
-#define GC_USB_DOEPINT8_OFFSET                   0xc08
-#define GC_USB_DOEPINT8_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ8_OFFSET                  0xc10
-#define GC_USB_DOEPTSIZ8_DEFAULT                 0x0
-#define GC_USB_DOEPDMA8_OFFSET                   0xc14
-#define GC_USB_DOEPDMA8_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB8_OFFSET                  0xc1c
-#define GC_USB_DOEPDMAB8_DEFAULT                 0x0
-#define GC_USB_DOEPCTL9_OFFSET                   0xc20
-#define GC_USB_DOEPCTL9_DEFAULT                  0x0
-#define GC_USB_DOEPINT9_OFFSET                   0xc28
-#define GC_USB_DOEPINT9_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ9_OFFSET                  0xc30
-#define GC_USB_DOEPTSIZ9_DEFAULT                 0x0
-#define GC_USB_DOEPDMA9_OFFSET                   0xc34
-#define GC_USB_DOEPDMA9_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB9_OFFSET                  0xc3c
-#define GC_USB_DOEPDMAB9_DEFAULT                 0x0
-#define GC_USB_DOEPCTL10_OFFSET                  0xc40
-#define GC_USB_DOEPCTL10_DEFAULT                 0x0
-#define GC_USB_DOEPINT10_OFFSET                  0xc48
-#define GC_USB_DOEPINT10_DEFAULT                 0x0
-#define GC_USB_DOEPTSIZ10_OFFSET                 0xc50
-#define GC_USB_DOEPTSIZ10_DEFAULT                0x0
-#define GC_USB_DOEPDMA10_OFFSET                  0xc54
-#define GC_USB_DOEPDMA10_DEFAULT                 0x0
-#define GC_USB_DOEPDMAB10_OFFSET                 0xc5c
-#define GC_USB_DOEPDMAB10_DEFAULT                0x0
-#define GC_USB_DOEPCTL11_OFFSET                  0xc60
-#define GC_USB_DOEPCTL11_DEFAULT                 0x0
-#define GC_USB_DOEPINT11_OFFSET                  0xc68
-#define GC_USB_DOEPINT11_DEFAULT                 0x0
-#define GC_USB_DOEPTSIZ11_OFFSET                 0xc70
-#define GC_USB_DOEPTSIZ11_DEFAULT                0x0
-#define GC_USB_DOEPDMA11_OFFSET                  0xc74
-#define GC_USB_DOEPDMA11_DEFAULT                 0x0
-#define GC_USB_DOEPDMAB11_OFFSET                 0xc7c
-#define GC_USB_DOEPDMAB11_DEFAULT                0x0
-#define GC_USB_DOEPCTL12_OFFSET                  0xc80
-#define GC_USB_DOEPCTL12_DEFAULT                 0x0
-#define GC_USB_DOEPINT12_OFFSET                  0xc88
-#define GC_USB_DOEPINT12_DEFAULT                 0x0
-#define GC_USB_DOEPTSIZ12_OFFSET                 0xc90
-#define GC_USB_DOEPTSIZ12_DEFAULT                0x0
-#define GC_USB_DOEPDMA12_OFFSET                  0xc94
-#define GC_USB_DOEPDMA12_DEFAULT                 0x0
-#define GC_USB_DOEPDMAB12_OFFSET                 0xc9c
-#define GC_USB_DOEPDMAB12_DEFAULT                0x0
-#define GC_USB_DOEPCTL13_OFFSET                  0xca0
-#define GC_USB_DOEPCTL13_DEFAULT                 0x0
-#define GC_USB_DOEPINT13_OFFSET                  0xca8
-#define GC_USB_DOEPINT13_DEFAULT                 0x0
-#define GC_USB_DOEPTSIZ13_OFFSET                 0xcb0
-#define GC_USB_DOEPTSIZ13_DEFAULT                0x0
-#define GC_USB_DOEPDMA13_OFFSET                  0xcb4
-#define GC_USB_DOEPDMA13_DEFAULT                 0x0
-#define GC_USB_DOEPDMAB13_OFFSET                 0xcbc
-#define GC_USB_DOEPDMAB13_DEFAULT                0x0
-#define GC_USB_DOEPCTL14_OFFSET                  0xcc0
-#define GC_USB_DOEPCTL14_DEFAULT                 0x0
-#define GC_USB_DOEPINT14_OFFSET                  0xcc8
-#define GC_USB_DOEPINT14_DEFAULT                 0x0
-#define GC_USB_DOEPTSIZ14_OFFSET                 0xcd0
-#define GC_USB_DOEPTSIZ14_DEFAULT                0x0
-#define GC_USB_DOEPDMA14_OFFSET                  0xcd4
-#define GC_USB_DOEPDMA14_DEFAULT                 0x0
-#define GC_USB_DOEPDMAB14_OFFSET                 0xcdc
-#define GC_USB_DOEPDMAB14_DEFAULT                0x0
-#define GC_USB_DOEPCTL15_OFFSET                  0xce0
-#define GC_USB_DOEPCTL15_DEFAULT                 0x0
-#define GC_USB_DOEPINT15_OFFSET                  0xce8
-#define GC_USB_DOEPINT15_DEFAULT                 0x0
-#define GC_USB_DOEPTSIZ15_OFFSET                 0xcf0
-#define GC_USB_DOEPTSIZ15_DEFAULT                0x0
-#define GC_USB_DOEPDMA15_OFFSET                  0xcf4
-#define GC_USB_DOEPDMA15_DEFAULT                 0x0
-#define GC_USB_DOEPDMAB15_OFFSET                 0xcfc
-#define GC_USB_DOEPDMAB15_DEFAULT                0x0
-#define GC_USB_PCGCCTL_OFFSET                    0xe00
-#define GC_USB_PCGCCTL_DEFAULT                   0x0
-#define GC_USB_DFIFO_OFFSET                      0x20000
-#define GC_USB_GOTGCTL_BVALIDOVEN_LSB            0x6
-#define GC_USB_GOTGCTL_BVALIDOVEN_MASK           0x40
-#define GC_USB_GOTGCTL_BVALIDOVEN_SIZE           0x1
-#define GC_USB_GOTGCTL_BVALIDOVEN_DEFAULT        0x0
-#define GC_USB_GOTGCTL_BVALIDOVEN_OFFSET         0x0
-#define GC_USB_GOTGCTL_BVALIDOVVAL_LSB           0x7
-#define GC_USB_GOTGCTL_BVALIDOVVAL_MASK          0x80
-#define GC_USB_GOTGCTL_BVALIDOVVAL_SIZE          0x1
-#define GC_USB_GOTGCTL_BVALIDOVVAL_DEFAULT       0x0
-#define GC_USB_GOTGCTL_BVALIDOVVAL_OFFSET        0x0
-#define GC_USB_GOTGCTL_CONIDSTS_LSB              0x10
-#define GC_USB_GOTGCTL_CONIDSTS_MASK             0x10000
-#define GC_USB_GOTGCTL_CONIDSTS_SIZE             0x1
-#define GC_USB_GOTGCTL_CONIDSTS_DEFAULT          0x0
-#define GC_USB_GOTGCTL_CONIDSTS_OFFSET           0x0
-#define GC_USB_GOTGCTL_BSESVLD_LSB               0x13
-#define GC_USB_GOTGCTL_BSESVLD_MASK              0x80000
-#define GC_USB_GOTGCTL_BSESVLD_SIZE              0x1
-#define GC_USB_GOTGCTL_BSESVLD_DEFAULT           0x0
-#define GC_USB_GOTGCTL_BSESVLD_OFFSET            0x0
-#define GC_USB_GOTGCTL_OTGVER_LSB                0x14
-#define GC_USB_GOTGCTL_OTGVER_MASK               0x100000
-#define GC_USB_GOTGCTL_OTGVER_SIZE               0x1
-#define GC_USB_GOTGCTL_OTGVER_DEFAULT            0x0
-#define GC_USB_GOTGCTL_OTGVER_OFFSET             0x0
-#define GC_USB_GOTGCTL_CURMOD_LSB                0x15
-#define GC_USB_GOTGCTL_CURMOD_MASK               0x200000
-#define GC_USB_GOTGCTL_CURMOD_SIZE               0x1
-#define GC_USB_GOTGCTL_CURMOD_DEFAULT            0x0
-#define GC_USB_GOTGCTL_CURMOD_OFFSET             0x0
-#define GC_USB_GOTGINT_SESENDDET_LSB             0x2
-#define GC_USB_GOTGINT_SESENDDET_MASK            0x4
-#define GC_USB_GOTGINT_SESENDDET_SIZE            0x1
-#define GC_USB_GOTGINT_SESENDDET_DEFAULT         0x0
-#define GC_USB_GOTGINT_SESENDDET_OFFSET          0x4
-#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_LSB      0x8
-#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_MASK     0x100
-#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_SIZE     0x1
-#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_DEFAULT  0x0
-#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_OFFSET   0x4
-#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_LSB      0x9
-#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_MASK     0x200
-#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_SIZE     0x1
-#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_DEFAULT  0x0
-#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_OFFSET   0x4
-#define GC_USB_GOTGINT_HSTNEGDET_LSB             0x11
-#define GC_USB_GOTGINT_HSTNEGDET_MASK            0x20000
-#define GC_USB_GOTGINT_HSTNEGDET_SIZE            0x1
-#define GC_USB_GOTGINT_HSTNEGDET_DEFAULT         0x0
-#define GC_USB_GOTGINT_HSTNEGDET_OFFSET          0x4
-#define GC_USB_GOTGINT_ADEVTOUTCHG_LSB           0x12
-#define GC_USB_GOTGINT_ADEVTOUTCHG_MASK          0x40000
-#define GC_USB_GOTGINT_ADEVTOUTCHG_SIZE          0x1
-#define GC_USB_GOTGINT_ADEVTOUTCHG_DEFAULT       0x0
-#define GC_USB_GOTGINT_ADEVTOUTCHG_OFFSET        0x4
-#define GC_USB_GAHBCFG_GLBLINTRMSK_LSB           0x0
-#define GC_USB_GAHBCFG_GLBLINTRMSK_MASK          0x1
-#define GC_USB_GAHBCFG_GLBLINTRMSK_SIZE          0x1
-#define GC_USB_GAHBCFG_GLBLINTRMSK_DEFAULT       0x0
-#define GC_USB_GAHBCFG_GLBLINTRMSK_OFFSET        0x8
-#define GC_USB_GAHBCFG_HBSTLEN_LSB               0x1
-#define GC_USB_GAHBCFG_HBSTLEN_MASK              0x1e
-#define GC_USB_GAHBCFG_HBSTLEN_SIZE              0x4
-#define GC_USB_GAHBCFG_HBSTLEN_DEFAULT           0x0
-#define GC_USB_GAHBCFG_HBSTLEN_OFFSET            0x8
-#define GC_USB_GAHBCFG_DMAEN_LSB                 0x5
-#define GC_USB_GAHBCFG_DMAEN_MASK                0x20
-#define GC_USB_GAHBCFG_DMAEN_SIZE                0x1
-#define GC_USB_GAHBCFG_DMAEN_DEFAULT             0x0
-#define GC_USB_GAHBCFG_DMAEN_OFFSET              0x8
+#define GC_USB_GCCFG_OFFSET 0x38
+#define GC_USB_GCCFG_DEFAULT 0x0
+#define GC_USB_GUID_OFFSET 0x3c
+#define GC_USB_GUID_DEFAULT 0x0
+#define GC_USB_GSNPSID_OFFSET 0x40
+#define GC_USB_GSNPSID_DEFAULT 0x0
+#define GC_USB_GHWCFG1_OFFSET 0x44
+#define GC_USB_GHWCFG1_DEFAULT 0x0
+#define GC_USB_GHWCFG2_OFFSET 0x48
+#define GC_USB_GHWCFG2_DEFAULT 0x0
+#define GC_USB_GHWCFG3_OFFSET 0x4c
+#define GC_USB_GHWCFG3_DEFAULT 0x0
+#define GC_USB_GHWCFG4_OFFSET 0x50
+#define GC_USB_GHWCFG4_DEFAULT 0x0
+#define GC_USB_GDFIFOCFG_OFFSET 0x5c
+#define GC_USB_GDFIFOCFG_DEFAULT 0x0
+#define GC_USB_DIEPTXF1_OFFSET 0x104
+#define GC_USB_DIEPTXF1_DEFAULT 0x1000
+#define GC_USB_DIEPTXF2_OFFSET 0x108
+#define GC_USB_DIEPTXF2_DEFAULT 0x0
+#define GC_USB_DIEPTXF3_OFFSET 0x10c
+#define GC_USB_DIEPTXF3_DEFAULT 0x0
+#define GC_USB_DIEPTXF4_OFFSET 0x110
+#define GC_USB_DIEPTXF4_DEFAULT 0x0
+#define GC_USB_DIEPTXF5_OFFSET 0x114
+#define GC_USB_DIEPTXF5_DEFAULT 0x0
+#define GC_USB_DIEPTXF6_OFFSET 0x118
+#define GC_USB_DIEPTXF6_DEFAULT 0x0
+#define GC_USB_DIEPTXF7_OFFSET 0x11c
+#define GC_USB_DIEPTXF7_DEFAULT 0x0
+#define GC_USB_DIEPTXF8_OFFSET 0x120
+#define GC_USB_DIEPTXF8_DEFAULT 0x0
+#define GC_USB_DIEPTXF9_OFFSET 0x124
+#define GC_USB_DIEPTXF9_DEFAULT 0x0
+#define GC_USB_DIEPTXF10_OFFSET 0x128
+#define GC_USB_DIEPTXF10_DEFAULT 0x0
+#define GC_USB_DIEPTXF11_OFFSET 0x12c
+#define GC_USB_DIEPTXF11_DEFAULT 0x0
+#define GC_USB_DIEPTXF12_OFFSET 0x130
+#define GC_USB_DIEPTXF12_DEFAULT 0x0
+#define GC_USB_DIEPTXF13_OFFSET 0x134
+#define GC_USB_DIEPTXF13_DEFAULT 0x0
+#define GC_USB_DIEPTXF14_OFFSET 0x138
+#define GC_USB_DIEPTXF14_DEFAULT 0x0
+#define GC_USB_DIEPTXF15_OFFSET 0x13c
+#define GC_USB_DIEPTXF15_DEFAULT 0x0
+#define GC_USB_DCFG_OFFSET 0x800
+#define GC_USB_DCFG_DEFAULT 0x8000000
+#define GC_USB_DCTL_OFFSET 0x804
+#define GC_USB_DCTL_DEFAULT 0x0
+#define GC_USB_DSTS_OFFSET 0x808
+#define GC_USB_DSTS_DEFAULT 0x0
+#define GC_USB_DIEPMSK_OFFSET 0x810
+#define GC_USB_DIEPMSK_DEFAULT 0x80
+#define GC_USB_DOEPMSK_OFFSET 0x814
+#define GC_USB_DOEPMSK_DEFAULT 0x0
+#define GC_USB_DAINT_OFFSET 0x818
+#define GC_USB_DAINT_DEFAULT 0x0
+#define GC_USB_DAINTMSK_OFFSET 0x81c
+#define GC_USB_DAINTMSK_DEFAULT 0x0
+#define GC_USB_DVBUSDIS_OFFSET 0x828
+#define GC_USB_DVBUSDIS_DEFAULT 0x0
+#define GC_USB_DVBUSPULSE_OFFSET 0x82c
+#define GC_USB_DVBUSPULSE_DEFAULT 0x0
+#define GC_USB_DTHRCTL_OFFSET 0x830
+#define GC_USB_DTHRCTL_DEFAULT 0x0
+#define GC_USB_DIEPEMPMSK_OFFSET 0x834
+#define GC_USB_DIEPEMPMSK_DEFAULT 0x0
+#define GC_USB_DIEPCTL0_OFFSET 0x900
+#define GC_USB_DIEPCTL0_DEFAULT 0x0
+#define GC_USB_DIEPINT0_OFFSET 0x908
+#define GC_USB_DIEPINT0_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ0_OFFSET 0x910
+#define GC_USB_DIEPTSIZ0_DEFAULT 0x0
+#define GC_USB_DIEPDMA0_OFFSET 0x914
+#define GC_USB_DIEPDMA0_DEFAULT 0x0
+#define GC_USB_DTXFSTS0_OFFSET 0x918
+#define GC_USB_DTXFSTS0_DEFAULT 0x0
+#define GC_USB_DIEPDMAB0_OFFSET 0x91c
+#define GC_USB_DIEPDMAB0_DEFAULT 0x0
+#define GC_USB_DIEPCTL1_OFFSET 0x920
+#define GC_USB_DIEPCTL1_DEFAULT 0x0
+#define GC_USB_DIEPINT1_OFFSET 0x928
+#define GC_USB_DIEPINT1_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ1_OFFSET 0x930
+#define GC_USB_DIEPTSIZ1_DEFAULT 0x0
+#define GC_USB_DIEPDMA1_OFFSET 0x934
+#define GC_USB_DIEPDMA1_DEFAULT 0x0
+#define GC_USB_DTXFSTS1_OFFSET 0x938
+#define GC_USB_DTXFSTS1_DEFAULT 0x0
+#define GC_USB_DIEPDMAB1_OFFSET 0x93c
+#define GC_USB_DIEPDMAB1_DEFAULT 0x0
+#define GC_USB_DIEPCTL2_OFFSET 0x940
+#define GC_USB_DIEPCTL2_DEFAULT 0x0
+#define GC_USB_DIEPINT2_OFFSET 0x948
+#define GC_USB_DIEPINT2_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ2_OFFSET 0x950
+#define GC_USB_DIEPTSIZ2_DEFAULT 0x0
+#define GC_USB_DIEPDMA2_OFFSET 0x954
+#define GC_USB_DIEPDMA2_DEFAULT 0x0
+#define GC_USB_DTXFSTS2_OFFSET 0x958
+#define GC_USB_DTXFSTS2_DEFAULT 0x0
+#define GC_USB_DIEPDMAB2_OFFSET 0x95c
+#define GC_USB_DIEPDMAB2_DEFAULT 0x0
+#define GC_USB_DIEPCTL3_OFFSET 0x960
+#define GC_USB_DIEPCTL3_DEFAULT 0x0
+#define GC_USB_DIEPINT3_OFFSET 0x968
+#define GC_USB_DIEPINT3_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ3_OFFSET 0x970
+#define GC_USB_DIEPTSIZ3_DEFAULT 0x0
+#define GC_USB_DIEPDMA3_OFFSET 0x974
+#define GC_USB_DIEPDMA3_DEFAULT 0x0
+#define GC_USB_DTXFSTS3_OFFSET 0x978
+#define GC_USB_DTXFSTS3_DEFAULT 0x0
+#define GC_USB_DIEPDMAB3_OFFSET 0x97c
+#define GC_USB_DIEPDMAB3_DEFAULT 0x0
+#define GC_USB_DIEPCTL4_OFFSET 0x980
+#define GC_USB_DIEPCTL4_DEFAULT 0x0
+#define GC_USB_DIEPINT4_OFFSET 0x988
+#define GC_USB_DIEPINT4_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ4_OFFSET 0x990
+#define GC_USB_DIEPTSIZ4_DEFAULT 0x0
+#define GC_USB_DIEPDMA4_OFFSET 0x994
+#define GC_USB_DIEPDMA4_DEFAULT 0x0
+#define GC_USB_DTXFSTS4_OFFSET 0x998
+#define GC_USB_DTXFSTS4_DEFAULT 0x0
+#define GC_USB_DIEPDMAB4_OFFSET 0x99c
+#define GC_USB_DIEPDMAB4_DEFAULT 0x0
+#define GC_USB_DIEPCTL5_OFFSET 0x9a0
+#define GC_USB_DIEPCTL5_DEFAULT 0x0
+#define GC_USB_DIEPINT5_OFFSET 0x9a8
+#define GC_USB_DIEPINT5_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ5_OFFSET 0x9b0
+#define GC_USB_DIEPTSIZ5_DEFAULT 0x0
+#define GC_USB_DIEPDMA5_OFFSET 0x9b4
+#define GC_USB_DIEPDMA5_DEFAULT 0x0
+#define GC_USB_DTXFSTS5_OFFSET 0x9b8
+#define GC_USB_DTXFSTS5_DEFAULT 0x0
+#define GC_USB_DIEPDMAB5_OFFSET 0x9bc
+#define GC_USB_DIEPDMAB5_DEFAULT 0x0
+#define GC_USB_DIEPCTL6_OFFSET 0x9c0
+#define GC_USB_DIEPCTL6_DEFAULT 0x0
+#define GC_USB_DIEPINT6_OFFSET 0x9c8
+#define GC_USB_DIEPINT6_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ6_OFFSET 0x9d0
+#define GC_USB_DIEPTSIZ6_DEFAULT 0x0
+#define GC_USB_DIEPDMA6_OFFSET 0x9d4
+#define GC_USB_DIEPDMA6_DEFAULT 0x0
+#define GC_USB_DTXFSTS6_OFFSET 0x9d8
+#define GC_USB_DTXFSTS6_DEFAULT 0x0
+#define GC_USB_DIEPDMAB6_OFFSET 0x9dc
+#define GC_USB_DIEPDMAB6_DEFAULT 0x0
+#define GC_USB_DIEPCTL7_OFFSET 0x9e0
+#define GC_USB_DIEPCTL7_DEFAULT 0x0
+#define GC_USB_DIEPINT7_OFFSET 0x9e8
+#define GC_USB_DIEPINT7_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ7_OFFSET 0x9f0
+#define GC_USB_DIEPTSIZ7_DEFAULT 0x0
+#define GC_USB_DIEPDMA7_OFFSET 0x9f4
+#define GC_USB_DIEPDMA7_DEFAULT 0x0
+#define GC_USB_DTXFSTS7_OFFSET 0x9f8
+#define GC_USB_DTXFSTS7_DEFAULT 0x0
+#define GC_USB_DIEPDMAB7_OFFSET 0x9fc
+#define GC_USB_DIEPDMAB7_DEFAULT 0x0
+#define GC_USB_DIEPCTL8_OFFSET 0xa00
+#define GC_USB_DIEPCTL8_DEFAULT 0x0
+#define GC_USB_DIEPINT8_OFFSET 0xa08
+#define GC_USB_DIEPINT8_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ8_OFFSET 0xa10
+#define GC_USB_DIEPTSIZ8_DEFAULT 0x0
+#define GC_USB_DIEPDMA8_OFFSET 0xa14
+#define GC_USB_DIEPDMA8_DEFAULT 0x0
+#define GC_USB_DTXFSTS8_OFFSET 0xa18
+#define GC_USB_DTXFSTS8_DEFAULT 0x0
+#define GC_USB_DIEPDMAB8_OFFSET 0xa1c
+#define GC_USB_DIEPDMAB8_DEFAULT 0x0
+#define GC_USB_DIEPCTL9_OFFSET 0xa20
+#define GC_USB_DIEPCTL9_DEFAULT 0x0
+#define GC_USB_DIEPINT9_OFFSET 0xa28
+#define GC_USB_DIEPINT9_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ9_OFFSET 0xa30
+#define GC_USB_DIEPTSIZ9_DEFAULT 0x0
+#define GC_USB_DIEPDMA9_OFFSET 0xa34
+#define GC_USB_DIEPDMA9_DEFAULT 0x0
+#define GC_USB_DTXFSTS9_OFFSET 0xa38
+#define GC_USB_DTXFSTS9_DEFAULT 0x0
+#define GC_USB_DIEPDMAB9_OFFSET 0xa3c
+#define GC_USB_DIEPDMAB9_DEFAULT 0x0
+#define GC_USB_DIEPCTL10_OFFSET 0xa40
+#define GC_USB_DIEPCTL10_DEFAULT 0x0
+#define GC_USB_DIEPINT10_OFFSET 0xa48
+#define GC_USB_DIEPINT10_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ10_OFFSET 0xa50
+#define GC_USB_DIEPTSIZ10_DEFAULT 0x0
+#define GC_USB_DIEPDMA10_OFFSET 0xa54
+#define GC_USB_DIEPDMA10_DEFAULT 0x0
+#define GC_USB_DTXFSTS10_OFFSET 0xa58
+#define GC_USB_DTXFSTS10_DEFAULT 0x0
+#define GC_USB_DIEPDMAB10_OFFSET 0xa5c
+#define GC_USB_DIEPDMAB10_DEFAULT 0x0
+#define GC_USB_DIEPCTL11_OFFSET 0xa60
+#define GC_USB_DIEPCTL11_DEFAULT 0x0
+#define GC_USB_DIEPINT11_OFFSET 0xa68
+#define GC_USB_DIEPINT11_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ11_OFFSET 0xa70
+#define GC_USB_DIEPTSIZ11_DEFAULT 0x0
+#define GC_USB_DIEPDMA11_OFFSET 0xa74
+#define GC_USB_DIEPDMA11_DEFAULT 0x0
+#define GC_USB_DTXFSTS11_OFFSET 0xa78
+#define GC_USB_DTXFSTS11_DEFAULT 0x0
+#define GC_USB_DIEPDMAB11_OFFSET 0xa7c
+#define GC_USB_DIEPDMAB11_DEFAULT 0x0
+#define GC_USB_DIEPCTL12_OFFSET 0xa80
+#define GC_USB_DIEPCTL12_DEFAULT 0x0
+#define GC_USB_DIEPINT12_OFFSET 0xa88
+#define GC_USB_DIEPINT12_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ12_OFFSET 0xa90
+#define GC_USB_DIEPTSIZ12_DEFAULT 0x0
+#define GC_USB_DIEPDMA12_OFFSET 0xa94
+#define GC_USB_DIEPDMA12_DEFAULT 0x0
+#define GC_USB_DTXFSTS12_OFFSET 0xa98
+#define GC_USB_DTXFSTS12_DEFAULT 0x0
+#define GC_USB_DIEPDMAB12_OFFSET 0xa9c
+#define GC_USB_DIEPDMAB12_DEFAULT 0x0
+#define GC_USB_DIEPCTL13_OFFSET 0xaa0
+#define GC_USB_DIEPCTL13_DEFAULT 0x0
+#define GC_USB_DIEPINT13_OFFSET 0xaa8
+#define GC_USB_DIEPINT13_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ13_OFFSET 0xab0
+#define GC_USB_DIEPTSIZ13_DEFAULT 0x0
+#define GC_USB_DIEPDMA13_OFFSET 0xab4
+#define GC_USB_DIEPDMA13_DEFAULT 0x0
+#define GC_USB_DTXFSTS13_OFFSET 0xab8
+#define GC_USB_DTXFSTS13_DEFAULT 0x0
+#define GC_USB_DIEPDMAB13_OFFSET 0xabc
+#define GC_USB_DIEPDMAB13_DEFAULT 0x0
+#define GC_USB_DIEPCTL14_OFFSET 0xac0
+#define GC_USB_DIEPCTL14_DEFAULT 0x0
+#define GC_USB_DIEPINT14_OFFSET 0xac8
+#define GC_USB_DIEPINT14_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ14_OFFSET 0xad0
+#define GC_USB_DIEPTSIZ14_DEFAULT 0x0
+#define GC_USB_DIEPDMA14_OFFSET 0xad4
+#define GC_USB_DIEPDMA14_DEFAULT 0x0
+#define GC_USB_DTXFSTS14_OFFSET 0xad8
+#define GC_USB_DTXFSTS14_DEFAULT 0x0
+#define GC_USB_DIEPDMAB14_OFFSET 0xadc
+#define GC_USB_DIEPDMAB14_DEFAULT 0x0
+#define GC_USB_DIEPCTL15_OFFSET 0xae0
+#define GC_USB_DIEPCTL15_DEFAULT 0x0
+#define GC_USB_DIEPINT15_OFFSET 0xae8
+#define GC_USB_DIEPINT15_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ15_OFFSET 0xaf0
+#define GC_USB_DIEPTSIZ15_DEFAULT 0x0
+#define GC_USB_DIEPDMA15_OFFSET 0xaf4
+#define GC_USB_DIEPDMA15_DEFAULT 0x0
+#define GC_USB_DTXFSTS15_OFFSET 0xaf8
+#define GC_USB_DTXFSTS15_DEFAULT 0x0
+#define GC_USB_DIEPDMAB15_OFFSET 0xafc
+#define GC_USB_DIEPDMAB15_DEFAULT 0x0
+#define GC_USB_DOEPCTL0_OFFSET 0xb00
+#define GC_USB_DOEPCTL0_DEFAULT 0x0
+#define GC_USB_DOEPINT0_OFFSET 0xb08
+#define GC_USB_DOEPINT0_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ0_OFFSET 0xb10
+#define GC_USB_DOEPTSIZ0_DEFAULT 0x0
+#define GC_USB_DOEPDMA0_OFFSET 0xb14
+#define GC_USB_DOEPDMA0_DEFAULT 0x0
+#define GC_USB_DOEPDMAB0_OFFSET 0xb1c
+#define GC_USB_DOEPDMAB0_DEFAULT 0x0
+#define GC_USB_DOEPCTL1_OFFSET 0xb20
+#define GC_USB_DOEPCTL1_DEFAULT 0x0
+#define GC_USB_DOEPINT1_OFFSET 0xb28
+#define GC_USB_DOEPINT1_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ1_OFFSET 0xb30
+#define GC_USB_DOEPTSIZ1_DEFAULT 0x0
+#define GC_USB_DOEPDMA1_OFFSET 0xb34
+#define GC_USB_DOEPDMA1_DEFAULT 0x0
+#define GC_USB_DOEPDMAB1_OFFSET 0xb3c
+#define GC_USB_DOEPDMAB1_DEFAULT 0x0
+#define GC_USB_DOEPCTL2_OFFSET 0xb40
+#define GC_USB_DOEPCTL2_DEFAULT 0x0
+#define GC_USB_DOEPINT2_OFFSET 0xb48
+#define GC_USB_DOEPINT2_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ2_OFFSET 0xb50
+#define GC_USB_DOEPTSIZ2_DEFAULT 0x0
+#define GC_USB_DOEPDMA2_OFFSET 0xb54
+#define GC_USB_DOEPDMA2_DEFAULT 0x0
+#define GC_USB_DOEPDMAB2_OFFSET 0xb5c
+#define GC_USB_DOEPDMAB2_DEFAULT 0x0
+#define GC_USB_DOEPCTL3_OFFSET 0xb60
+#define GC_USB_DOEPCTL3_DEFAULT 0x0
+#define GC_USB_DOEPINT3_OFFSET 0xb68
+#define GC_USB_DOEPINT3_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ3_OFFSET 0xb70
+#define GC_USB_DOEPTSIZ3_DEFAULT 0x0
+#define GC_USB_DOEPDMA3_OFFSET 0xb74
+#define GC_USB_DOEPDMA3_DEFAULT 0x0
+#define GC_USB_DOEPDMAB3_OFFSET 0xb7c
+#define GC_USB_DOEPDMAB3_DEFAULT 0x0
+#define GC_USB_DOEPCTL4_OFFSET 0xb80
+#define GC_USB_DOEPCTL4_DEFAULT 0x0
+#define GC_USB_DOEPINT4_OFFSET 0xb88
+#define GC_USB_DOEPINT4_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ4_OFFSET 0xb90
+#define GC_USB_DOEPTSIZ4_DEFAULT 0x0
+#define GC_USB_DOEPDMA4_OFFSET 0xb94
+#define GC_USB_DOEPDMA4_DEFAULT 0x0
+#define GC_USB_DOEPDMAB4_OFFSET 0xb9c
+#define GC_USB_DOEPDMAB4_DEFAULT 0x0
+#define GC_USB_DOEPCTL5_OFFSET 0xba0
+#define GC_USB_DOEPCTL5_DEFAULT 0x0
+#define GC_USB_DOEPINT5_OFFSET 0xba8
+#define GC_USB_DOEPINT5_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ5_OFFSET 0xbb0
+#define GC_USB_DOEPTSIZ5_DEFAULT 0x0
+#define GC_USB_DOEPDMA5_OFFSET 0xbb4
+#define GC_USB_DOEPDMA5_DEFAULT 0x0
+#define GC_USB_DOEPDMAB5_OFFSET 0xbbc
+#define GC_USB_DOEPDMAB5_DEFAULT 0x0
+#define GC_USB_DOEPCTL6_OFFSET 0xbc0
+#define GC_USB_DOEPCTL6_DEFAULT 0x0
+#define GC_USB_DOEPINT6_OFFSET 0xbc8
+#define GC_USB_DOEPINT6_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ6_OFFSET 0xbd0
+#define GC_USB_DOEPTSIZ6_DEFAULT 0x0
+#define GC_USB_DOEPDMA6_OFFSET 0xbd4
+#define GC_USB_DOEPDMA6_DEFAULT 0x0
+#define GC_USB_DOEPDMAB6_OFFSET 0xbdc
+#define GC_USB_DOEPDMAB6_DEFAULT 0x0
+#define GC_USB_DOEPCTL7_OFFSET 0xbe0
+#define GC_USB_DOEPCTL7_DEFAULT 0x0
+#define GC_USB_DOEPINT7_OFFSET 0xbe8
+#define GC_USB_DOEPINT7_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ7_OFFSET 0xbf0
+#define GC_USB_DOEPTSIZ7_DEFAULT 0x0
+#define GC_USB_DOEPDMA7_OFFSET 0xbf4
+#define GC_USB_DOEPDMA7_DEFAULT 0x0
+#define GC_USB_DOEPDMAB7_OFFSET 0xbfc
+#define GC_USB_DOEPDMAB7_DEFAULT 0x0
+#define GC_USB_DOEPCTL8_OFFSET 0xc00
+#define GC_USB_DOEPCTL8_DEFAULT 0x0
+#define GC_USB_DOEPINT8_OFFSET 0xc08
+#define GC_USB_DOEPINT8_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ8_OFFSET 0xc10
+#define GC_USB_DOEPTSIZ8_DEFAULT 0x0
+#define GC_USB_DOEPDMA8_OFFSET 0xc14
+#define GC_USB_DOEPDMA8_DEFAULT 0x0
+#define GC_USB_DOEPDMAB8_OFFSET 0xc1c
+#define GC_USB_DOEPDMAB8_DEFAULT 0x0
+#define GC_USB_DOEPCTL9_OFFSET 0xc20
+#define GC_USB_DOEPCTL9_DEFAULT 0x0
+#define GC_USB_DOEPINT9_OFFSET 0xc28
+#define GC_USB_DOEPINT9_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ9_OFFSET 0xc30
+#define GC_USB_DOEPTSIZ9_DEFAULT 0x0
+#define GC_USB_DOEPDMA9_OFFSET 0xc34
+#define GC_USB_DOEPDMA9_DEFAULT 0x0
+#define GC_USB_DOEPDMAB9_OFFSET 0xc3c
+#define GC_USB_DOEPDMAB9_DEFAULT 0x0
+#define GC_USB_DOEPCTL10_OFFSET 0xc40
+#define GC_USB_DOEPCTL10_DEFAULT 0x0
+#define GC_USB_DOEPINT10_OFFSET 0xc48
+#define GC_USB_DOEPINT10_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ10_OFFSET 0xc50
+#define GC_USB_DOEPTSIZ10_DEFAULT 0x0
+#define GC_USB_DOEPDMA10_OFFSET 0xc54
+#define GC_USB_DOEPDMA10_DEFAULT 0x0
+#define GC_USB_DOEPDMAB10_OFFSET 0xc5c
+#define GC_USB_DOEPDMAB10_DEFAULT 0x0
+#define GC_USB_DOEPCTL11_OFFSET 0xc60
+#define GC_USB_DOEPCTL11_DEFAULT 0x0
+#define GC_USB_DOEPINT11_OFFSET 0xc68
+#define GC_USB_DOEPINT11_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ11_OFFSET 0xc70
+#define GC_USB_DOEPTSIZ11_DEFAULT 0x0
+#define GC_USB_DOEPDMA11_OFFSET 0xc74
+#define GC_USB_DOEPDMA11_DEFAULT 0x0
+#define GC_USB_DOEPDMAB11_OFFSET 0xc7c
+#define GC_USB_DOEPDMAB11_DEFAULT 0x0
+#define GC_USB_DOEPCTL12_OFFSET 0xc80
+#define GC_USB_DOEPCTL12_DEFAULT 0x0
+#define GC_USB_DOEPINT12_OFFSET 0xc88
+#define GC_USB_DOEPINT12_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ12_OFFSET 0xc90
+#define GC_USB_DOEPTSIZ12_DEFAULT 0x0
+#define GC_USB_DOEPDMA12_OFFSET 0xc94
+#define GC_USB_DOEPDMA12_DEFAULT 0x0
+#define GC_USB_DOEPDMAB12_OFFSET 0xc9c
+#define GC_USB_DOEPDMAB12_DEFAULT 0x0
+#define GC_USB_DOEPCTL13_OFFSET 0xca0
+#define GC_USB_DOEPCTL13_DEFAULT 0x0
+#define GC_USB_DOEPINT13_OFFSET 0xca8
+#define GC_USB_DOEPINT13_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ13_OFFSET 0xcb0
+#define GC_USB_DOEPTSIZ13_DEFAULT 0x0
+#define GC_USB_DOEPDMA13_OFFSET 0xcb4
+#define GC_USB_DOEPDMA13_DEFAULT 0x0
+#define GC_USB_DOEPDMAB13_OFFSET 0xcbc
+#define GC_USB_DOEPDMAB13_DEFAULT 0x0
+#define GC_USB_DOEPCTL14_OFFSET 0xcc0
+#define GC_USB_DOEPCTL14_DEFAULT 0x0
+#define GC_USB_DOEPINT14_OFFSET 0xcc8
+#define GC_USB_DOEPINT14_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ14_OFFSET 0xcd0
+#define GC_USB_DOEPTSIZ14_DEFAULT 0x0
+#define GC_USB_DOEPDMA14_OFFSET 0xcd4
+#define GC_USB_DOEPDMA14_DEFAULT 0x0
+#define GC_USB_DOEPDMAB14_OFFSET 0xcdc
+#define GC_USB_DOEPDMAB14_DEFAULT 0x0
+#define GC_USB_DOEPCTL15_OFFSET 0xce0
+#define GC_USB_DOEPCTL15_DEFAULT 0x0
+#define GC_USB_DOEPINT15_OFFSET 0xce8
+#define GC_USB_DOEPINT15_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ15_OFFSET 0xcf0
+#define GC_USB_DOEPTSIZ15_DEFAULT 0x0
+#define GC_USB_DOEPDMA15_OFFSET 0xcf4
+#define GC_USB_DOEPDMA15_DEFAULT 0x0
+#define GC_USB_DOEPDMAB15_OFFSET 0xcfc
+#define GC_USB_DOEPDMAB15_DEFAULT 0x0
+#define GC_USB_PCGCCTL_OFFSET 0xe00
+#define GC_USB_PCGCCTL_DEFAULT 0x0
+#define GC_USB_DFIFO_OFFSET 0x20000
+#define GC_USB_GOTGCTL_BVALIDOVEN_LSB 0x6
+#define GC_USB_GOTGCTL_BVALIDOVEN_MASK 0x40
+#define GC_USB_GOTGCTL_BVALIDOVEN_SIZE 0x1
+#define GC_USB_GOTGCTL_BVALIDOVEN_DEFAULT 0x0
+#define GC_USB_GOTGCTL_BVALIDOVEN_OFFSET 0x0
+#define GC_USB_GOTGCTL_BVALIDOVVAL_LSB 0x7
+#define GC_USB_GOTGCTL_BVALIDOVVAL_MASK 0x80
+#define GC_USB_GOTGCTL_BVALIDOVVAL_SIZE 0x1
+#define GC_USB_GOTGCTL_BVALIDOVVAL_DEFAULT 0x0
+#define GC_USB_GOTGCTL_BVALIDOVVAL_OFFSET 0x0
+#define GC_USB_GOTGCTL_CONIDSTS_LSB 0x10
+#define GC_USB_GOTGCTL_CONIDSTS_MASK 0x10000
+#define GC_USB_GOTGCTL_CONIDSTS_SIZE 0x1
+#define GC_USB_GOTGCTL_CONIDSTS_DEFAULT 0x0
+#define GC_USB_GOTGCTL_CONIDSTS_OFFSET 0x0
+#define GC_USB_GOTGCTL_BSESVLD_LSB 0x13
+#define GC_USB_GOTGCTL_BSESVLD_MASK 0x80000
+#define GC_USB_GOTGCTL_BSESVLD_SIZE 0x1
+#define GC_USB_GOTGCTL_BSESVLD_DEFAULT 0x0
+#define GC_USB_GOTGCTL_BSESVLD_OFFSET 0x0
+#define GC_USB_GOTGCTL_OTGVER_LSB 0x14
+#define GC_USB_GOTGCTL_OTGVER_MASK 0x100000
+#define GC_USB_GOTGCTL_OTGVER_SIZE 0x1
+#define GC_USB_GOTGCTL_OTGVER_DEFAULT 0x0
+#define GC_USB_GOTGCTL_OTGVER_OFFSET 0x0
+#define GC_USB_GOTGCTL_CURMOD_LSB 0x15
+#define GC_USB_GOTGCTL_CURMOD_MASK 0x200000
+#define GC_USB_GOTGCTL_CURMOD_SIZE 0x1
+#define GC_USB_GOTGCTL_CURMOD_DEFAULT 0x0
+#define GC_USB_GOTGCTL_CURMOD_OFFSET 0x0
+#define GC_USB_GOTGINT_SESENDDET_LSB 0x2
+#define GC_USB_GOTGINT_SESENDDET_MASK 0x4
+#define GC_USB_GOTGINT_SESENDDET_SIZE 0x1
+#define GC_USB_GOTGINT_SESENDDET_DEFAULT 0x0
+#define GC_USB_GOTGINT_SESENDDET_OFFSET 0x4
+#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_LSB 0x8
+#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_MASK 0x100
+#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_SIZE 0x1
+#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_DEFAULT 0x0
+#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_OFFSET 0x4
+#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_LSB 0x9
+#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_MASK 0x200
+#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_SIZE 0x1
+#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_DEFAULT 0x0
+#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_OFFSET 0x4
+#define GC_USB_GOTGINT_HSTNEGDET_LSB 0x11
+#define GC_USB_GOTGINT_HSTNEGDET_MASK 0x20000
+#define GC_USB_GOTGINT_HSTNEGDET_SIZE 0x1
+#define GC_USB_GOTGINT_HSTNEGDET_DEFAULT 0x0
+#define GC_USB_GOTGINT_HSTNEGDET_OFFSET 0x4
+#define GC_USB_GOTGINT_ADEVTOUTCHG_LSB 0x12
+#define GC_USB_GOTGINT_ADEVTOUTCHG_MASK 0x40000
+#define GC_USB_GOTGINT_ADEVTOUTCHG_SIZE 0x1
+#define GC_USB_GOTGINT_ADEVTOUTCHG_DEFAULT 0x0
+#define GC_USB_GOTGINT_ADEVTOUTCHG_OFFSET 0x4
+#define GC_USB_GAHBCFG_GLBLINTRMSK_LSB 0x0
+#define GC_USB_GAHBCFG_GLBLINTRMSK_MASK 0x1
+#define GC_USB_GAHBCFG_GLBLINTRMSK_SIZE 0x1
+#define GC_USB_GAHBCFG_GLBLINTRMSK_DEFAULT 0x0
+#define GC_USB_GAHBCFG_GLBLINTRMSK_OFFSET 0x8
+#define GC_USB_GAHBCFG_HBSTLEN_LSB 0x1
+#define GC_USB_GAHBCFG_HBSTLEN_MASK 0x1e
+#define GC_USB_GAHBCFG_HBSTLEN_SIZE 0x4
+#define GC_USB_GAHBCFG_HBSTLEN_DEFAULT 0x0
+#define GC_USB_GAHBCFG_HBSTLEN_OFFSET 0x8
+#define GC_USB_GAHBCFG_DMAEN_LSB 0x5
+#define GC_USB_GAHBCFG_DMAEN_MASK 0x20
+#define GC_USB_GAHBCFG_DMAEN_SIZE 0x1
+#define GC_USB_GAHBCFG_DMAEN_DEFAULT 0x0
+#define GC_USB_GAHBCFG_DMAEN_OFFSET 0x8
 
-#define GC_USB_GAHBCFG_NPTXFEMPLVL_LSB           0x7
-#define GC_USB_GAHBCFG_NPTXFEMPLVL_MASK          0x80
-#define GC_USB_GAHBCFG_NPTXFEMPLVL_SIZE          0x1
-#define GC_USB_GAHBCFG_NPTXFEMPLVL_DEFAULT       0x0
-#define GC_USB_GAHBCFG_NPTXFEMPLVL_OFFSET        0x8
+#define GC_USB_GAHBCFG_NPTXFEMPLVL_LSB 0x7
+#define GC_USB_GAHBCFG_NPTXFEMPLVL_MASK 0x80
+#define GC_USB_GAHBCFG_NPTXFEMPLVL_SIZE 0x1
+#define GC_USB_GAHBCFG_NPTXFEMPLVL_DEFAULT 0x0
+#define GC_USB_GAHBCFG_NPTXFEMPLVL_OFFSET 0x8
 
-#define GC_USB_GAHBCFG_REMMEMSUPP_LSB            0x15
-#define GC_USB_GAHBCFG_REMMEMSUPP_MASK           0x200000
-#define GC_USB_GAHBCFG_REMMEMSUPP_SIZE           0x1
-#define GC_USB_GAHBCFG_REMMEMSUPP_DEFAULT        0x0
-#define GC_USB_GAHBCFG_REMMEMSUPP_OFFSET         0x8
-#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_LSB        0x16
-#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_MASK       0x400000
-#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_SIZE       0x1
-#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_DEFAULT    0x0
-#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_OFFSET     0x8
-#define GC_USB_GAHBCFG_AHBSINGLE_LSB             0x17
-#define GC_USB_GAHBCFG_AHBSINGLE_MASK            0x800000
-#define GC_USB_GAHBCFG_AHBSINGLE_SIZE            0x1
-#define GC_USB_GAHBCFG_AHBSINGLE_DEFAULT         0x0
-#define GC_USB_GAHBCFG_AHBSINGLE_OFFSET          0x8
-#define GC_USB_GAHBCFG_INVDESCENDIANESS_LSB      0x18
-#define GC_USB_GAHBCFG_INVDESCENDIANESS_MASK     0x1000000
-#define GC_USB_GAHBCFG_INVDESCENDIANESS_SIZE     0x1
-#define GC_USB_GAHBCFG_INVDESCENDIANESS_DEFAULT  0x0
-#define GC_USB_GAHBCFG_INVDESCENDIANESS_OFFSET   0x8
-#define GC_USB_GUSBCFG_TOUTCAL_LSB               0x0
-#define GC_USB_GUSBCFG_TOUTCAL_MASK              0x7
-#define GC_USB_GUSBCFG_TOUTCAL_SIZE              0x3
-#define GC_USB_GUSBCFG_TOUTCAL_DEFAULT           0x0
-#define GC_USB_GUSBCFG_TOUTCAL_OFFSET            0xc
+#define GC_USB_GAHBCFG_REMMEMSUPP_LSB 0x15
+#define GC_USB_GAHBCFG_REMMEMSUPP_MASK 0x200000
+#define GC_USB_GAHBCFG_REMMEMSUPP_SIZE 0x1
+#define GC_USB_GAHBCFG_REMMEMSUPP_DEFAULT 0x0
+#define GC_USB_GAHBCFG_REMMEMSUPP_OFFSET 0x8
+#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_LSB 0x16
+#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_MASK 0x400000
+#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_SIZE 0x1
+#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_DEFAULT 0x0
+#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_OFFSET 0x8
+#define GC_USB_GAHBCFG_AHBSINGLE_LSB 0x17
+#define GC_USB_GAHBCFG_AHBSINGLE_MASK 0x800000
+#define GC_USB_GAHBCFG_AHBSINGLE_SIZE 0x1
+#define GC_USB_GAHBCFG_AHBSINGLE_DEFAULT 0x0
+#define GC_USB_GAHBCFG_AHBSINGLE_OFFSET 0x8
+#define GC_USB_GAHBCFG_INVDESCENDIANESS_LSB 0x18
+#define GC_USB_GAHBCFG_INVDESCENDIANESS_MASK 0x1000000
+#define GC_USB_GAHBCFG_INVDESCENDIANESS_SIZE 0x1
+#define GC_USB_GAHBCFG_INVDESCENDIANESS_DEFAULT 0x0
+#define GC_USB_GAHBCFG_INVDESCENDIANESS_OFFSET 0x8
+#define GC_USB_GUSBCFG_TOUTCAL_LSB 0x0
+#define GC_USB_GUSBCFG_TOUTCAL_MASK 0x7
+#define GC_USB_GUSBCFG_TOUTCAL_SIZE 0x3
+#define GC_USB_GUSBCFG_TOUTCAL_DEFAULT 0x0
+#define GC_USB_GUSBCFG_TOUTCAL_OFFSET 0xc
 
-#define GC_USB_GUSBCFG_USBTRDTIM_LSB             0xa
-#define GC_USB_GUSBCFG_USBTRDTIM_MASK            0x3c00
-#define GC_USB_GUSBCFG_USBTRDTIM_SIZE            0x4
-#define GC_USB_GUSBCFG_USBTRDTIM_DEFAULT         0x0
-#define GC_USB_GUSBCFG_USBTRDTIM_OFFSET          0xc
-#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_LSB         15
-#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_MASK        0x8000
-#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_SIZE        0x1
-#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_DEFAULT     0x0
-#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_OFFSET      0xc
-#define GC_USB_GUSBCFG_ULPIFSLS_LSB              17
-#define GC_USB_GUSBCFG_ULPIFSLS_MASK             0x20000
-#define GC_USB_GUSBCFG_ULPIFSLS_SIZE             0x1
-#define GC_USB_GUSBCFG_ULPIFSLS_DEFAULT          0x0
-#define GC_USB_GUSBCFG_ULPIFSLS_OFFSET           0xc
-#define GC_USB_GUSBCFG_ULPIAUTORES_LSB           18
-#define GC_USB_GUSBCFG_ULPIAUTORES_MASK          0x40000
-#define GC_USB_GUSBCFG_ULPIAUTORES_SIZE          0x1
-#define GC_USB_GUSBCFG_ULPIAUTORES_DEFAULT       0x0
-#define GC_USB_GUSBCFG_ULPIAUTORES_OFFSET        0xc
-#define GC_USB_GUSBCFG_ULPICLKSUSM_LSB           19
-#define GC_USB_GUSBCFG_ULPICLKSUSM_MASK          0x80000
-#define GC_USB_GUSBCFG_ULPICLKSUSM_SIZE          0x1
-#define GC_USB_GUSBCFG_ULPICLKSUSM_DEFAULT       0x0
-#define GC_USB_GUSBCFG_ULPICLKSUSM_OFFSET        0xc
+#define GC_USB_GUSBCFG_USBTRDTIM_LSB 0xa
+#define GC_USB_GUSBCFG_USBTRDTIM_MASK 0x3c00
+#define GC_USB_GUSBCFG_USBTRDTIM_SIZE 0x4
+#define GC_USB_GUSBCFG_USBTRDTIM_DEFAULT 0x0
+#define GC_USB_GUSBCFG_USBTRDTIM_OFFSET 0xc
+#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_LSB 15
+#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_MASK 0x8000
+#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_SIZE 0x1
+#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_DEFAULT 0x0
+#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_OFFSET 0xc
+#define GC_USB_GUSBCFG_ULPIFSLS_LSB 17
+#define GC_USB_GUSBCFG_ULPIFSLS_MASK 0x20000
+#define GC_USB_GUSBCFG_ULPIFSLS_SIZE 0x1
+#define GC_USB_GUSBCFG_ULPIFSLS_DEFAULT 0x0
+#define GC_USB_GUSBCFG_ULPIFSLS_OFFSET 0xc
+#define GC_USB_GUSBCFG_ULPIAUTORES_LSB 18
+#define GC_USB_GUSBCFG_ULPIAUTORES_MASK 0x40000
+#define GC_USB_GUSBCFG_ULPIAUTORES_SIZE 0x1
+#define GC_USB_GUSBCFG_ULPIAUTORES_DEFAULT 0x0
+#define GC_USB_GUSBCFG_ULPIAUTORES_OFFSET 0xc
+#define GC_USB_GUSBCFG_ULPICLKSUSM_LSB 19
+#define GC_USB_GUSBCFG_ULPICLKSUSM_MASK 0x80000
+#define GC_USB_GUSBCFG_ULPICLKSUSM_SIZE 0x1
+#define GC_USB_GUSBCFG_ULPICLKSUSM_DEFAULT 0x0
+#define GC_USB_GUSBCFG_ULPICLKSUSM_OFFSET 0xc
 
-#define GC_USB_GUSBCFG_ULPIEVBUSD_LSB            20
-#define GC_USB_GUSBCFG_ULPIEVBUSD_MASK           0x100000
-#define GC_USB_GUSBCFG_ULPIEVBUSD_SIZE           0x1
-#define GC_USB_GUSBCFG_ULPIEVBUSD_DEFAULT        0x0
-#define GC_USB_GUSBCFG_ULPIEVBUSD_OFFSET         0xc
+#define GC_USB_GUSBCFG_ULPIEVBUSD_LSB 20
+#define GC_USB_GUSBCFG_ULPIEVBUSD_MASK 0x100000
+#define GC_USB_GUSBCFG_ULPIEVBUSD_SIZE 0x1
+#define GC_USB_GUSBCFG_ULPIEVBUSD_DEFAULT 0x0
+#define GC_USB_GUSBCFG_ULPIEVBUSD_OFFSET 0xc
 
-#define GC_USB_GUSBCFG_ULPIEVBUSI_LSB            21
-#define GC_USB_GUSBCFG_ULPIEVBUSI_MASK           0x200000
-#define GC_USB_GUSBCFG_ULPIEVBUSI_SIZE           0x1
-#define GC_USB_GUSBCFG_ULPIEVBUSI_DEFAULT        0x0
-#define GC_USB_GUSBCFG_ULPIEVBUSI_OFFSET         0xc
+#define GC_USB_GUSBCFG_ULPIEVBUSI_LSB 21
+#define GC_USB_GUSBCFG_ULPIEVBUSI_MASK 0x200000
+#define GC_USB_GUSBCFG_ULPIEVBUSI_SIZE 0x1
+#define GC_USB_GUSBCFG_ULPIEVBUSI_DEFAULT 0x0
+#define GC_USB_GUSBCFG_ULPIEVBUSI_OFFSET 0xc
 
-#define GC_USB_GUSBCFG_TERMSELDLPULSE_LSB        22
-#define GC_USB_GUSBCFG_TERMSELDLPULSE_MASK       0x400000
-#define GC_USB_GUSBCFG_TERMSELDLPULSE_SIZE       0x1
-#define GC_USB_GUSBCFG_TERMSELDLPULSE_DEFAULT    0x0
-#define GC_USB_GUSBCFG_TERMSELDLPULSE_OFFSET     0xc
+#define GC_USB_GUSBCFG_TERMSELDLPULSE_LSB 22
+#define GC_USB_GUSBCFG_TERMSELDLPULSE_MASK 0x400000
+#define GC_USB_GUSBCFG_TERMSELDLPULSE_SIZE 0x1
+#define GC_USB_GUSBCFG_TERMSELDLPULSE_DEFAULT 0x0
+#define GC_USB_GUSBCFG_TERMSELDLPULSE_OFFSET 0xc
 
-#define GC_USB_GUSBCFG_PCCI_LSB                  23
-#define GC_USB_GUSBCFG_PCCI_MASK                 BIT(23)
-#define GC_USB_GUSBCFG_PCCI_SIZE                 0x1
-#define GC_USB_GUSBCFG_PCCI_DEFAULT              0x0
-#define GC_USB_GUSBCFG_PCCI_OFFSET               0xc
+#define GC_USB_GUSBCFG_PCCI_LSB 23
+#define GC_USB_GUSBCFG_PCCI_MASK BIT(23)
+#define GC_USB_GUSBCFG_PCCI_SIZE 0x1
+#define GC_USB_GUSBCFG_PCCI_DEFAULT 0x0
+#define GC_USB_GUSBCFG_PCCI_OFFSET 0xc
 
-#define GC_USB_GUSBCFG_PTCI_LSB                  24
-#define GC_USB_GUSBCFG_PTCI_MASK                 BIT(24)
-#define GC_USB_GUSBCFG_PTCI_SIZE                 0x1
-#define GC_USB_GUSBCFG_PTCI_DEFAULT              0x0
-#define GC_USB_GUSBCFG_PTCI_OFFSET               0xc
+#define GC_USB_GUSBCFG_PTCI_LSB 24
+#define GC_USB_GUSBCFG_PTCI_MASK BIT(24)
+#define GC_USB_GUSBCFG_PTCI_SIZE 0x1
+#define GC_USB_GUSBCFG_PTCI_DEFAULT 0x0
+#define GC_USB_GUSBCFG_PTCI_OFFSET 0xc
 
-#define GC_USB_GUSBCFG_ULPIIPD_LSB               25
-#define GC_USB_GUSBCFG_ULPIIPD_MASK              BIT(25)
-#define GC_USB_GUSBCFG_ULPIIPD_SIZE              0x1
-#define GC_USB_GUSBCFG_ULPIIPD_DEFAULT           0x0
-#define GC_USB_GUSBCFG_ULPIIPD_OFFSET            0xc
+#define GC_USB_GUSBCFG_ULPIIPD_LSB 25
+#define GC_USB_GUSBCFG_ULPIIPD_MASK BIT(25)
+#define GC_USB_GUSBCFG_ULPIIPD_SIZE 0x1
+#define GC_USB_GUSBCFG_ULPIIPD_DEFAULT 0x0
+#define GC_USB_GUSBCFG_ULPIIPD_OFFSET 0xc
 
-#define GC_USB_GUSBCFG_FHMOD_LSB                 29
-#define GC_USB_GUSBCFG_FHMOD_MASK                BIT(29)
-#define GC_USB_GUSBCFG_FHMOD_SIZE                0x1
-#define GC_USB_GUSBCFG_FHMOD_DEFAULT             0x0
-#define GC_USB_GUSBCFG_FHMOD_OFFSET              0xc
+#define GC_USB_GUSBCFG_FHMOD_LSB 29
+#define GC_USB_GUSBCFG_FHMOD_MASK BIT(29)
+#define GC_USB_GUSBCFG_FHMOD_SIZE 0x1
+#define GC_USB_GUSBCFG_FHMOD_DEFAULT 0x0
+#define GC_USB_GUSBCFG_FHMOD_OFFSET 0xc
 
-#define GC_USB_GUSBCFG_FDMOD_LSB                 30
-#define GC_USB_GUSBCFG_FDMOD_MASK                BIT(30)
-#define GC_USB_GUSBCFG_FDMOD_SIZE                0x1
-#define GC_USB_GUSBCFG_FDMOD_DEFAULT             0x0
-#define GC_USB_GUSBCFG_FDMOD_OFFSET              0xc
+#define GC_USB_GUSBCFG_FDMOD_LSB 30
+#define GC_USB_GUSBCFG_FDMOD_MASK BIT(30)
+#define GC_USB_GUSBCFG_FDMOD_SIZE 0x1
+#define GC_USB_GUSBCFG_FDMOD_DEFAULT 0x0
+#define GC_USB_GUSBCFG_FDMOD_OFFSET 0xc
 
-#define GC_USB_GRSTCTL_CSFTRST_LSB               0x0
-#define GC_USB_GRSTCTL_CSFTRST_MASK              0x1
-#define GC_USB_GRSTCTL_CSFTRST_SIZE              0x1
-#define GC_USB_GRSTCTL_CSFTRST_DEFAULT           0x0
-#define GC_USB_GRSTCTL_CSFTRST_OFFSET            0x10
-#define GC_USB_GRSTCTL_PIUFSSFTRST_LSB           0x1
-#define GC_USB_GRSTCTL_PIUFSSFTRST_MASK          0x2
-#define GC_USB_GRSTCTL_PIUFSSFTRST_SIZE          0x1
-#define GC_USB_GRSTCTL_PIUFSSFTRST_DEFAULT       0x0
-#define GC_USB_GRSTCTL_PIUFSSFTRST_OFFSET        0x10
-#define GC_USB_GRSTCTL_RXFFLSH_LSB               0x4
-#define GC_USB_GRSTCTL_RXFFLSH_MASK              0x10
-#define GC_USB_GRSTCTL_RXFFLSH_SIZE              0x1
-#define GC_USB_GRSTCTL_RXFFLSH_DEFAULT           0x0
-#define GC_USB_GRSTCTL_RXFFLSH_OFFSET            0x10
-#define GC_USB_GRSTCTL_TXFFLSH_LSB               0x5
-#define GC_USB_GRSTCTL_TXFFLSH_MASK              0x20
-#define GC_USB_GRSTCTL_TXFFLSH_SIZE              0x1
-#define GC_USB_GRSTCTL_TXFFLSH_DEFAULT           0x0
-#define GC_USB_GRSTCTL_TXFFLSH_OFFSET            0x10
-#define GC_USB_GRSTCTL_TXFNUM_LSB                0x6
-#define GC_USB_GRSTCTL_TXFNUM_MASK               0x7c0
-#define GC_USB_GRSTCTL_TXFNUM_SIZE               0x5
-#define GC_USB_GRSTCTL_TXFNUM_DEFAULT            0x0
-#define GC_USB_GRSTCTL_TXFNUM_OFFSET             0x10
-#define GC_USB_GRSTCTL_DMAREQ_LSB                0x1e
-#define GC_USB_GRSTCTL_DMAREQ_MASK               0x40000000
-#define GC_USB_GRSTCTL_DMAREQ_SIZE               0x1
-#define GC_USB_GRSTCTL_DMAREQ_DEFAULT            0x0
-#define GC_USB_GRSTCTL_DMAREQ_OFFSET             0x10
-#define GC_USB_GRSTCTL_AHBIDLE_LSB               0x1f
-#define GC_USB_GRSTCTL_AHBIDLE_MASK              0x80000000
-#define GC_USB_GRSTCTL_AHBIDLE_SIZE              0x1
-#define GC_USB_GRSTCTL_AHBIDLE_DEFAULT           0x0
-#define GC_USB_GRSTCTL_AHBIDLE_OFFSET            0x10
-#define GC_USB_GINTSTS_CURMOD_LSB                0x0
-#define GC_USB_GINTSTS_CURMOD_MASK               0x1
-#define GC_USB_GINTSTS_CURMOD_SIZE               0x1
-#define GC_USB_GINTSTS_CURMOD_DEFAULT            0x0
-#define GC_USB_GINTSTS_CURMOD_OFFSET             0x14
-#define GC_USB_GINTSTS_MODEMIS_LSB               0x1
-#define GC_USB_GINTSTS_MODEMIS_MASK              0x2
-#define GC_USB_GINTSTS_MODEMIS_SIZE              0x1
-#define GC_USB_GINTSTS_MODEMIS_DEFAULT           0x0
-#define GC_USB_GINTSTS_MODEMIS_OFFSET            0x14
-#define GC_USB_GINTSTS_OTGINT_LSB                0x2
-#define GC_USB_GINTSTS_OTGINT_MASK               0x4
-#define GC_USB_GINTSTS_OTGINT_SIZE               0x1
-#define GC_USB_GINTSTS_OTGINT_DEFAULT            0x0
-#define GC_USB_GINTSTS_OTGINT_OFFSET             0x14
-#define GC_USB_GINTSTS_SOF_LSB                   0x3
-#define GC_USB_GINTSTS_SOF_MASK                  0x8
-#define GC_USB_GINTSTS_SOF_SIZE                  0x1
-#define GC_USB_GINTSTS_SOF_DEFAULT               0x0
-#define GC_USB_GINTSTS_SOF_OFFSET                0x14
-#define GC_USB_GINTSTS_RXFLVL_LSB                0x4
-#define GC_USB_GINTSTS_RXFLVL_MASK               0x10
-#define GC_USB_GINTSTS_RXFLVL_SIZE               0x1
-#define GC_USB_GINTSTS_RXFLVL_DEFAULT            0x0
-#define GC_USB_GINTSTS_RXFLVL_OFFSET             0x14
-#define GC_USB_GINTSTS_GINNAKEFF_LSB             0x6
-#define GC_USB_GINTSTS_GINNAKEFF_MASK            0x40
-#define GC_USB_GINTSTS_GINNAKEFF_SIZE            0x1
-#define GC_USB_GINTSTS_GINNAKEFF_DEFAULT         0x0
-#define GC_USB_GINTSTS_GINNAKEFF_OFFSET          0x14
-#define GC_USB_GINTSTS_GOUTNAKEFF_LSB            0x7
-#define GC_USB_GINTSTS_GOUTNAKEFF_MASK           0x80
-#define GC_USB_GINTSTS_GOUTNAKEFF_SIZE           0x1
-#define GC_USB_GINTSTS_GOUTNAKEFF_DEFAULT        0x0
-#define GC_USB_GINTSTS_GOUTNAKEFF_OFFSET         0x14
-#define GC_USB_GINTSTS_ERLYSUSP_LSB              0xa
-#define GC_USB_GINTSTS_ERLYSUSP_MASK             0x400
-#define GC_USB_GINTSTS_ERLYSUSP_SIZE             0x1
-#define GC_USB_GINTSTS_ERLYSUSP_DEFAULT          0x0
-#define GC_USB_GINTSTS_ERLYSUSP_OFFSET           0x14
-#define GC_USB_GINTSTS_USBSUSP_LSB               0xb
-#define GC_USB_GINTSTS_USBSUSP_MASK              0x800
-#define GC_USB_GINTSTS_USBSUSP_SIZE              0x1
-#define GC_USB_GINTSTS_USBSUSP_DEFAULT           0x0
-#define GC_USB_GINTSTS_USBSUSP_OFFSET            0x14
-#define GC_USB_GINTSTS_USBRST_LSB                0xc
-#define GC_USB_GINTSTS_USBRST_MASK               0x1000
-#define GC_USB_GINTSTS_USBRST_SIZE               0x1
-#define GC_USB_GINTSTS_USBRST_DEFAULT            0x0
-#define GC_USB_GINTSTS_USBRST_OFFSET             0x14
-#define GC_USB_GINTSTS_ENUMDONE_LSB              0xd
-#define GC_USB_GINTSTS_ENUMDONE_MASK             0x2000
-#define GC_USB_GINTSTS_ENUMDONE_SIZE             0x1
-#define GC_USB_GINTSTS_ENUMDONE_DEFAULT          0x0
-#define GC_USB_GINTSTS_ENUMDONE_OFFSET           0x14
-#define GC_USB_GINTSTS_ISOOUTDROP_LSB            0xe
-#define GC_USB_GINTSTS_ISOOUTDROP_MASK           0x4000
-#define GC_USB_GINTSTS_ISOOUTDROP_SIZE           0x1
-#define GC_USB_GINTSTS_ISOOUTDROP_DEFAULT        0x0
-#define GC_USB_GINTSTS_ISOOUTDROP_OFFSET         0x14
-#define GC_USB_GINTSTS_EOPF_LSB                  0xf
-#define GC_USB_GINTSTS_EOPF_MASK                 0x8000
-#define GC_USB_GINTSTS_EOPF_SIZE                 0x1
-#define GC_USB_GINTSTS_EOPF_DEFAULT              0x0
-#define GC_USB_GINTSTS_EOPF_OFFSET               0x14
-#define GC_USB_GINTSTS_EPMIS_LSB                 0x11
-#define GC_USB_GINTSTS_EPMIS_MASK                0x20000
-#define GC_USB_GINTSTS_EPMIS_SIZE                0x1
-#define GC_USB_GINTSTS_EPMIS_DEFAULT             0x0
-#define GC_USB_GINTSTS_EPMIS_OFFSET              0x14
-#define GC_USB_GINTSTS_IEPINT_LSB                0x12
-#define GC_USB_GINTSTS_IEPINT_MASK               0x40000
-#define GC_USB_GINTSTS_IEPINT_SIZE               0x1
-#define GC_USB_GINTSTS_IEPINT_DEFAULT            0x0
-#define GC_USB_GINTSTS_IEPINT_OFFSET             0x14
-#define GC_USB_GINTSTS_OEPINT_LSB                0x13
-#define GC_USB_GINTSTS_OEPINT_MASK               0x80000
-#define GC_USB_GINTSTS_OEPINT_SIZE               0x1
-#define GC_USB_GINTSTS_OEPINT_DEFAULT            0x0
-#define GC_USB_GINTSTS_OEPINT_OFFSET             0x14
-#define GC_USB_GINTSTS_INCOMPISOIN_LSB           0x14
-#define GC_USB_GINTSTS_INCOMPISOIN_MASK          0x100000
-#define GC_USB_GINTSTS_INCOMPISOIN_SIZE          0x1
-#define GC_USB_GINTSTS_INCOMPISOIN_DEFAULT       0x0
-#define GC_USB_GINTSTS_INCOMPISOIN_OFFSET        0x14
-#define GC_USB_GINTSTS_INCOMPLP_LSB              0x15
-#define GC_USB_GINTSTS_INCOMPLP_MASK             0x200000
-#define GC_USB_GINTSTS_INCOMPLP_SIZE             0x1
-#define GC_USB_GINTSTS_INCOMPLP_DEFAULT          0x0
-#define GC_USB_GINTSTS_INCOMPLP_OFFSET           0x14
-#define GC_USB_GINTSTS_FETSUSP_LSB               0x16
-#define GC_USB_GINTSTS_FETSUSP_MASK              0x400000
-#define GC_USB_GINTSTS_FETSUSP_SIZE              0x1
-#define GC_USB_GINTSTS_FETSUSP_DEFAULT           0x0
-#define GC_USB_GINTSTS_FETSUSP_OFFSET            0x14
-#define GC_USB_GINTSTS_RESETDET_LSB              0x17
-#define GC_USB_GINTSTS_RESETDET_MASK             0x800000
-#define GC_USB_GINTSTS_RESETDET_SIZE             0x1
-#define GC_USB_GINTSTS_RESETDET_DEFAULT          0x0
-#define GC_USB_GINTSTS_RESETDET_OFFSET           0x14
-#define GC_USB_GINTSTS_CONIDSTSCHNG_LSB          0x1c
-#define GC_USB_GINTSTS_CONIDSTSCHNG_MASK         0x10000000
-#define GC_USB_GINTSTS_CONIDSTSCHNG_SIZE         0x1
-#define GC_USB_GINTSTS_CONIDSTSCHNG_DEFAULT      0x0
-#define GC_USB_GINTSTS_CONIDSTSCHNG_OFFSET       0x14
-#define GC_USB_GINTSTS_SESSREQINT_LSB            0x1e
-#define GC_USB_GINTSTS_SESSREQINT_MASK           0x40000000
-#define GC_USB_GINTSTS_SESSREQINT_SIZE           0x1
-#define GC_USB_GINTSTS_SESSREQINT_DEFAULT        0x0
-#define GC_USB_GINTSTS_SESSREQINT_OFFSET         0x14
-#define GC_USB_GINTSTS_WKUPINT_LSB               0x1f
-#define GC_USB_GINTSTS_WKUPINT_MASK              0x80000000
-#define GC_USB_GINTSTS_WKUPINT_SIZE              0x1
-#define GC_USB_GINTSTS_WKUPINT_DEFAULT           0x0
-#define GC_USB_GINTSTS_WKUPINT_OFFSET            0x14
-#define GC_USB_GINTMSK_MODEMISMSK_LSB            0x1
-#define GC_USB_GINTMSK_MODEMISMSK_MASK           0x2
-#define GC_USB_GINTMSK_MODEMISMSK_SIZE           0x1
-#define GC_USB_GINTMSK_MODEMISMSK_DEFAULT        0x0
-#define GC_USB_GINTMSK_MODEMISMSK_OFFSET         0x18
-#define GC_USB_GINTMSK_OTGINTMSK_LSB             0x2
-#define GC_USB_GINTMSK_OTGINTMSK_MASK            0x4
-#define GC_USB_GINTMSK_OTGINTMSK_SIZE            0x1
-#define GC_USB_GINTMSK_OTGINTMSK_DEFAULT         0x0
-#define GC_USB_GINTMSK_OTGINTMSK_OFFSET          0x18
-#define GC_USB_GINTMSK_SOFMSK_LSB                0x3
-#define GC_USB_GINTMSK_SOFMSK_MASK               0x8
-#define GC_USB_GINTMSK_SOFMSK_SIZE               0x1
-#define GC_USB_GINTMSK_SOFMSK_DEFAULT            0x0
-#define GC_USB_GINTMSK_SOFMSK_OFFSET             0x18
-#define GC_USB_GINTMSK_RXFLVLMSK_LSB             0x4
-#define GC_USB_GINTMSK_RXFLVLMSK_MASK            0x10
-#define GC_USB_GINTMSK_RXFLVLMSK_SIZE            0x1
-#define GC_USB_GINTMSK_RXFLVLMSK_DEFAULT         0x0
-#define GC_USB_GINTMSK_RXFLVLMSK_OFFSET          0x18
-#define GC_USB_GINTMSK_UNKNOWN5_LSB              0x5
-#define GC_USB_GINTMSK_UNKNOWN5_MASK             0x20
-#define GC_USB_GINTMSK_UNKNOWN5_SIZE             0x1
-#define GC_USB_GINTMSK_UNKNOWN5_DEFAULT          0x0
-#define GC_USB_GINTMSK_UNKNOWN5_OFFSET           0x18
-#define GC_USB_GINTMSK_GINNAKEFFMSK_LSB          0x6
-#define GC_USB_GINTMSK_GINNAKEFFMSK_MASK         0x40
-#define GC_USB_GINTMSK_GINNAKEFFMSK_SIZE         0x1
-#define GC_USB_GINTMSK_GINNAKEFFMSK_DEFAULT      0x0
-#define GC_USB_GINTMSK_GINNAKEFFMSK_OFFSET       0x18
-#define GC_USB_GINTMSK_GOUTNAKEFFMSK_LSB         0x7
-#define GC_USB_GINTMSK_GOUTNAKEFFMSK_MASK        0x80
-#define GC_USB_GINTMSK_GOUTNAKEFFMSK_SIZE        0x1
-#define GC_USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT     0x0
-#define GC_USB_GINTMSK_GOUTNAKEFFMSK_OFFSET      0x18
-#define GC_USB_GINTMSK_ERLYSUSPMSK_LSB           0xa
-#define GC_USB_GINTMSK_ERLYSUSPMSK_MASK          0x400
-#define GC_USB_GINTMSK_ERLYSUSPMSK_SIZE          0x1
-#define GC_USB_GINTMSK_ERLYSUSPMSK_DEFAULT       0x0
-#define GC_USB_GINTMSK_ERLYSUSPMSK_OFFSET        0x18
-#define GC_USB_GINTMSK_USBSUSPMSK_LSB            0xb
-#define GC_USB_GINTMSK_USBSUSPMSK_MASK           0x800
-#define GC_USB_GINTMSK_USBSUSPMSK_SIZE           0x1
-#define GC_USB_GINTMSK_USBSUSPMSK_DEFAULT        0x0
-#define GC_USB_GINTMSK_USBSUSPMSK_OFFSET         0x18
-#define GC_USB_GINTMSK_USBRSTMSK_LSB             0xc
-#define GC_USB_GINTMSK_USBRSTMSK_MASK            0x1000
-#define GC_USB_GINTMSK_USBRSTMSK_SIZE            0x1
-#define GC_USB_GINTMSK_USBRSTMSK_DEFAULT         0x0
-#define GC_USB_GINTMSK_USBRSTMSK_OFFSET          0x18
-#define GC_USB_GINTMSK_ENUMDONEMSK_LSB           0xd
-#define GC_USB_GINTMSK_ENUMDONEMSK_MASK          0x2000
-#define GC_USB_GINTMSK_ENUMDONEMSK_SIZE          0x1
-#define GC_USB_GINTMSK_ENUMDONEMSK_DEFAULT       0x0
-#define GC_USB_GINTMSK_ENUMDONEMSK_OFFSET        0x18
-#define GC_USB_GINTMSK_ISOOUTDROPMSK_LSB         0xe
-#define GC_USB_GINTMSK_ISOOUTDROPMSK_MASK        0x4000
-#define GC_USB_GINTMSK_ISOOUTDROPMSK_SIZE        0x1
-#define GC_USB_GINTMSK_ISOOUTDROPMSK_DEFAULT     0x0
-#define GC_USB_GINTMSK_ISOOUTDROPMSK_OFFSET      0x18
-#define GC_USB_GINTMSK_EOPFMSK_LSB               0xf
-#define GC_USB_GINTMSK_EOPFMSK_MASK              0x8000
-#define GC_USB_GINTMSK_EOPFMSK_SIZE              0x1
-#define GC_USB_GINTMSK_EOPFMSK_DEFAULT           0x0
-#define GC_USB_GINTMSK_EOPFMSK_OFFSET            0x18
-#define GC_USB_GINTMSK_UNKNOWN16_LSB             0x10
-#define GC_USB_GINTMSK_UNKNOWN16_MASK            0x10000
-#define GC_USB_GINTMSK_UNKNOWN16_SIZE            0x1
-#define GC_USB_GINTMSK_UNKNOWN16_DEFAULT         0x0
-#define GC_USB_GINTMSK_UNKNOWN16_OFFSET          0x18
-#define GC_USB_GINTMSK_EPMISMSK_LSB              0x11
-#define GC_USB_GINTMSK_EPMISMSK_MASK             0x20000
-#define GC_USB_GINTMSK_EPMISMSK_SIZE             0x1
-#define GC_USB_GINTMSK_EPMISMSK_DEFAULT          0x0
-#define GC_USB_GINTMSK_EPMISMSK_OFFSET           0x18
-#define GC_USB_GINTMSK_IEPINTMSK_LSB             0x12
-#define GC_USB_GINTMSK_IEPINTMSK_MASK            0x40000
-#define GC_USB_GINTMSK_IEPINTMSK_SIZE            0x1
-#define GC_USB_GINTMSK_IEPINTMSK_DEFAULT         0x0
-#define GC_USB_GINTMSK_IEPINTMSK_OFFSET          0x18
-#define GC_USB_GINTMSK_OEPINTMSK_LSB             0x13
-#define GC_USB_GINTMSK_OEPINTMSK_MASK            0x80000
-#define GC_USB_GINTMSK_OEPINTMSK_SIZE            0x1
-#define GC_USB_GINTMSK_OEPINTMSK_DEFAULT         0x0
-#define GC_USB_GINTMSK_OEPINTMSK_OFFSET          0x18
-#define GC_USB_GINTMSK_INCOMPISOINMSK_LSB        0x14
-#define GC_USB_GINTMSK_INCOMPISOINMSK_MASK       0x100000
-#define GC_USB_GINTMSK_INCOMPISOINMSK_SIZE       0x1
-#define GC_USB_GINTMSK_INCOMPISOINMSK_DEFAULT    0x0
-#define GC_USB_GINTMSK_INCOMPISOINMSK_OFFSET     0x18
-#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_LSB      0x15
-#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_MASK     0x200000
-#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_SIZE     0x1
-#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_DEFAULT  0x0
-#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_OFFSET   0x18
-#define GC_USB_GINTMSK_FETSUSPMSK_LSB            0x16
-#define GC_USB_GINTMSK_FETSUSPMSK_MASK           0x400000
-#define GC_USB_GINTMSK_FETSUSPMSK_SIZE           0x1
-#define GC_USB_GINTMSK_FETSUSPMSK_DEFAULT        0x0
-#define GC_USB_GINTMSK_FETSUSPMSK_OFFSET         0x18
-#define GC_USB_GINTMSK_RESETDETMSK_LSB           0x17
-#define GC_USB_GINTMSK_RESETDETMSK_MASK          0x800000
-#define GC_USB_GINTMSK_RESETDETMSK_SIZE          0x1
-#define GC_USB_GINTMSK_RESETDETMSK_DEFAULT       0x0
-#define GC_USB_GINTMSK_RESETDETMSK_OFFSET        0x18
-#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_LSB       0x1c
-#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_MASK      0x10000000
-#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_SIZE      0x1
-#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_DEFAULT   0x0
-#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_OFFSET    0x18
-#define GC_USB_GINTMSK_DISCONNINTMSK_LSB         0x1d
-#define GC_USB_GINTMSK_DISCONNINTMSK_MASK        0x20000000
-#define GC_USB_GINTMSK_DISCONNINTMSK_SIZE        0x1
-#define GC_USB_GINTMSK_DISCONNINTMSK_DEFAULT     0x0
-#define GC_USB_GINTMSK_DISCONNINTMSK_OFFSET      0x18
-#define GC_USB_GINTMSK_SESSREQINTMSK_LSB         0x1e
-#define GC_USB_GINTMSK_SESSREQINTMSK_MASK        0x40000000
-#define GC_USB_GINTMSK_SESSREQINTMSK_SIZE        0x1
-#define GC_USB_GINTMSK_SESSREQINTMSK_DEFAULT     0x0
-#define GC_USB_GINTMSK_SESSREQINTMSK_OFFSET      0x18
-#define GC_USB_GINTMSK_WKUPINTMSK_LSB            0x1f
-#define GC_USB_GINTMSK_WKUPINTMSK_MASK           0x80000000
-#define GC_USB_GINTMSK_WKUPINTMSK_SIZE           0x1
-#define GC_USB_GINTMSK_WKUPINTMSK_DEFAULT        0x0
-#define GC_USB_GINTMSK_WKUPINTMSK_OFFSET         0x18
-#define GC_USB_GRXSTSR_CHNUM_LSB                 0x0
-#define GC_USB_GRXSTSR_CHNUM_MASK                0xf
-#define GC_USB_GRXSTSR_CHNUM_SIZE                0x4
-#define GC_USB_GRXSTSR_CHNUM_DEFAULT             0x0
-#define GC_USB_GRXSTSR_CHNUM_OFFSET              0x1c
-#define GC_USB_GRXSTSR_BCNT_LSB                  0x4
-#define GC_USB_GRXSTSR_BCNT_MASK                 0x7ff0
-#define GC_USB_GRXSTSR_BCNT_SIZE                 0xb
-#define GC_USB_GRXSTSR_BCNT_DEFAULT              0x0
-#define GC_USB_GRXSTSR_BCNT_OFFSET               0x1c
-#define GC_USB_GRXSTSR_DPID_LSB                  0xf
-#define GC_USB_GRXSTSR_DPID_MASK                 0x18000
-#define GC_USB_GRXSTSR_DPID_SIZE                 0x2
-#define GC_USB_GRXSTSR_DPID_DEFAULT              0x0
-#define GC_USB_GRXSTSR_DPID_OFFSET               0x1c
-#define GC_USB_GRXSTSR_PKTSTS_LSB                0x11
-#define GC_USB_GRXSTSR_PKTSTS_MASK               0x1e0000
-#define GC_USB_GRXSTSR_PKTSTS_SIZE               0x4
-#define GC_USB_GRXSTSR_PKTSTS_DEFAULT            0x0
-#define GC_USB_GRXSTSR_PKTSTS_OFFSET             0x1c
-#define GC_USB_GRXSTSR_FN_LSB                    0x15
-#define GC_USB_GRXSTSR_FN_MASK                   0x1e00000
-#define GC_USB_GRXSTSR_FN_SIZE                   0x4
-#define GC_USB_GRXSTSR_FN_DEFAULT                0x0
-#define GC_USB_GRXSTSR_FN_OFFSET                 0x1c
-#define GC_USB_GRXSTSP_CHNUM_LSB                 0x0
-#define GC_USB_GRXSTSP_CHNUM_MASK                0xf
-#define GC_USB_GRXSTSP_CHNUM_SIZE                0x4
-#define GC_USB_GRXSTSP_CHNUM_DEFAULT             0x0
-#define GC_USB_GRXSTSP_CHNUM_OFFSET              0x20
-#define GC_USB_GRXSTSP_BCNT_LSB                  0x4
-#define GC_USB_GRXSTSP_BCNT_MASK                 0x7ff0
-#define GC_USB_GRXSTSP_BCNT_SIZE                 0xb
-#define GC_USB_GRXSTSP_BCNT_DEFAULT              0x0
-#define GC_USB_GRXSTSP_BCNT_OFFSET               0x20
-#define GC_USB_GRXSTSP_DPID_LSB                  0xf
-#define GC_USB_GRXSTSP_DPID_MASK                 0x18000
-#define GC_USB_GRXSTSP_DPID_SIZE                 0x2
-#define GC_USB_GRXSTSP_DPID_DEFAULT              0x0
-#define GC_USB_GRXSTSP_DPID_OFFSET               0x20
-#define GC_USB_GRXSTSP_PKTSTS_LSB                0x11
-#define GC_USB_GRXSTSP_PKTSTS_MASK               0x1e0000
-#define GC_USB_GRXSTSP_PKTSTS_SIZE               0x4
-#define GC_USB_GRXSTSP_PKTSTS_DEFAULT            0x0
-#define GC_USB_GRXSTSP_PKTSTS_OFFSET             0x20
-#define GC_USB_GRXSTSP_FN_LSB                    0x15
-#define GC_USB_GRXSTSP_FN_MASK                   0x1e00000
-#define GC_USB_GRXSTSP_FN_SIZE                   0x4
-#define GC_USB_GRXSTSP_FN_DEFAULT                0x0
-#define GC_USB_GRXSTSP_FN_OFFSET                 0x20
-#define GC_USB_GRXFSIZ_RXFDEP_LSB                0x0
-#define GC_USB_GRXFSIZ_RXFDEP_MASK               0x7ff
-#define GC_USB_GRXFSIZ_RXFDEP_SIZE               0xb
-#define GC_USB_GRXFSIZ_RXFDEP_DEFAULT            0x0
-#define GC_USB_GRXFSIZ_RXFDEP_OFFSET             0x24
-#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_LSB      0x0
-#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_MASK     0xffff
-#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_SIZE     0x10
-#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_DEFAULT  0x0
-#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_OFFSET   0x28
-#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_LSB         0x10
-#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_MASK        0xffff0000
-#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_SIZE        0x10
-#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_DEFAULT     0x0
-#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_OFFSET      0x28
+#define GC_USB_GRSTCTL_CSFTRST_LSB 0x0
+#define GC_USB_GRSTCTL_CSFTRST_MASK 0x1
+#define GC_USB_GRSTCTL_CSFTRST_SIZE 0x1
+#define GC_USB_GRSTCTL_CSFTRST_DEFAULT 0x0
+#define GC_USB_GRSTCTL_CSFTRST_OFFSET 0x10
+#define GC_USB_GRSTCTL_PIUFSSFTRST_LSB 0x1
+#define GC_USB_GRSTCTL_PIUFSSFTRST_MASK 0x2
+#define GC_USB_GRSTCTL_PIUFSSFTRST_SIZE 0x1
+#define GC_USB_GRSTCTL_PIUFSSFTRST_DEFAULT 0x0
+#define GC_USB_GRSTCTL_PIUFSSFTRST_OFFSET 0x10
+#define GC_USB_GRSTCTL_RXFFLSH_LSB 0x4
+#define GC_USB_GRSTCTL_RXFFLSH_MASK 0x10
+#define GC_USB_GRSTCTL_RXFFLSH_SIZE 0x1
+#define GC_USB_GRSTCTL_RXFFLSH_DEFAULT 0x0
+#define GC_USB_GRSTCTL_RXFFLSH_OFFSET 0x10
+#define GC_USB_GRSTCTL_TXFFLSH_LSB 0x5
+#define GC_USB_GRSTCTL_TXFFLSH_MASK 0x20
+#define GC_USB_GRSTCTL_TXFFLSH_SIZE 0x1
+#define GC_USB_GRSTCTL_TXFFLSH_DEFAULT 0x0
+#define GC_USB_GRSTCTL_TXFFLSH_OFFSET 0x10
+#define GC_USB_GRSTCTL_TXFNUM_LSB 0x6
+#define GC_USB_GRSTCTL_TXFNUM_MASK 0x7c0
+#define GC_USB_GRSTCTL_TXFNUM_SIZE 0x5
+#define GC_USB_GRSTCTL_TXFNUM_DEFAULT 0x0
+#define GC_USB_GRSTCTL_TXFNUM_OFFSET 0x10
+#define GC_USB_GRSTCTL_DMAREQ_LSB 0x1e
+#define GC_USB_GRSTCTL_DMAREQ_MASK 0x40000000
+#define GC_USB_GRSTCTL_DMAREQ_SIZE 0x1
+#define GC_USB_GRSTCTL_DMAREQ_DEFAULT 0x0
+#define GC_USB_GRSTCTL_DMAREQ_OFFSET 0x10
+#define GC_USB_GRSTCTL_AHBIDLE_LSB 0x1f
+#define GC_USB_GRSTCTL_AHBIDLE_MASK 0x80000000
+#define GC_USB_GRSTCTL_AHBIDLE_SIZE 0x1
+#define GC_USB_GRSTCTL_AHBIDLE_DEFAULT 0x0
+#define GC_USB_GRSTCTL_AHBIDLE_OFFSET 0x10
+#define GC_USB_GINTSTS_CURMOD_LSB 0x0
+#define GC_USB_GINTSTS_CURMOD_MASK 0x1
+#define GC_USB_GINTSTS_CURMOD_SIZE 0x1
+#define GC_USB_GINTSTS_CURMOD_DEFAULT 0x0
+#define GC_USB_GINTSTS_CURMOD_OFFSET 0x14
+#define GC_USB_GINTSTS_MODEMIS_LSB 0x1
+#define GC_USB_GINTSTS_MODEMIS_MASK 0x2
+#define GC_USB_GINTSTS_MODEMIS_SIZE 0x1
+#define GC_USB_GINTSTS_MODEMIS_DEFAULT 0x0
+#define GC_USB_GINTSTS_MODEMIS_OFFSET 0x14
+#define GC_USB_GINTSTS_OTGINT_LSB 0x2
+#define GC_USB_GINTSTS_OTGINT_MASK 0x4
+#define GC_USB_GINTSTS_OTGINT_SIZE 0x1
+#define GC_USB_GINTSTS_OTGINT_DEFAULT 0x0
+#define GC_USB_GINTSTS_OTGINT_OFFSET 0x14
+#define GC_USB_GINTSTS_SOF_LSB 0x3
+#define GC_USB_GINTSTS_SOF_MASK 0x8
+#define GC_USB_GINTSTS_SOF_SIZE 0x1
+#define GC_USB_GINTSTS_SOF_DEFAULT 0x0
+#define GC_USB_GINTSTS_SOF_OFFSET 0x14
+#define GC_USB_GINTSTS_RXFLVL_LSB 0x4
+#define GC_USB_GINTSTS_RXFLVL_MASK 0x10
+#define GC_USB_GINTSTS_RXFLVL_SIZE 0x1
+#define GC_USB_GINTSTS_RXFLVL_DEFAULT 0x0
+#define GC_USB_GINTSTS_RXFLVL_OFFSET 0x14
+#define GC_USB_GINTSTS_GINNAKEFF_LSB 0x6
+#define GC_USB_GINTSTS_GINNAKEFF_MASK 0x40
+#define GC_USB_GINTSTS_GINNAKEFF_SIZE 0x1
+#define GC_USB_GINTSTS_GINNAKEFF_DEFAULT 0x0
+#define GC_USB_GINTSTS_GINNAKEFF_OFFSET 0x14
+#define GC_USB_GINTSTS_GOUTNAKEFF_LSB 0x7
+#define GC_USB_GINTSTS_GOUTNAKEFF_MASK 0x80
+#define GC_USB_GINTSTS_GOUTNAKEFF_SIZE 0x1
+#define GC_USB_GINTSTS_GOUTNAKEFF_DEFAULT 0x0
+#define GC_USB_GINTSTS_GOUTNAKEFF_OFFSET 0x14
+#define GC_USB_GINTSTS_ERLYSUSP_LSB 0xa
+#define GC_USB_GINTSTS_ERLYSUSP_MASK 0x400
+#define GC_USB_GINTSTS_ERLYSUSP_SIZE 0x1
+#define GC_USB_GINTSTS_ERLYSUSP_DEFAULT 0x0
+#define GC_USB_GINTSTS_ERLYSUSP_OFFSET 0x14
+#define GC_USB_GINTSTS_USBSUSP_LSB 0xb
+#define GC_USB_GINTSTS_USBSUSP_MASK 0x800
+#define GC_USB_GINTSTS_USBSUSP_SIZE 0x1
+#define GC_USB_GINTSTS_USBSUSP_DEFAULT 0x0
+#define GC_USB_GINTSTS_USBSUSP_OFFSET 0x14
+#define GC_USB_GINTSTS_USBRST_LSB 0xc
+#define GC_USB_GINTSTS_USBRST_MASK 0x1000
+#define GC_USB_GINTSTS_USBRST_SIZE 0x1
+#define GC_USB_GINTSTS_USBRST_DEFAULT 0x0
+#define GC_USB_GINTSTS_USBRST_OFFSET 0x14
+#define GC_USB_GINTSTS_ENUMDONE_LSB 0xd
+#define GC_USB_GINTSTS_ENUMDONE_MASK 0x2000
+#define GC_USB_GINTSTS_ENUMDONE_SIZE 0x1
+#define GC_USB_GINTSTS_ENUMDONE_DEFAULT 0x0
+#define GC_USB_GINTSTS_ENUMDONE_OFFSET 0x14
+#define GC_USB_GINTSTS_ISOOUTDROP_LSB 0xe
+#define GC_USB_GINTSTS_ISOOUTDROP_MASK 0x4000
+#define GC_USB_GINTSTS_ISOOUTDROP_SIZE 0x1
+#define GC_USB_GINTSTS_ISOOUTDROP_DEFAULT 0x0
+#define GC_USB_GINTSTS_ISOOUTDROP_OFFSET 0x14
+#define GC_USB_GINTSTS_EOPF_LSB 0xf
+#define GC_USB_GINTSTS_EOPF_MASK 0x8000
+#define GC_USB_GINTSTS_EOPF_SIZE 0x1
+#define GC_USB_GINTSTS_EOPF_DEFAULT 0x0
+#define GC_USB_GINTSTS_EOPF_OFFSET 0x14
+#define GC_USB_GINTSTS_EPMIS_LSB 0x11
+#define GC_USB_GINTSTS_EPMIS_MASK 0x20000
+#define GC_USB_GINTSTS_EPMIS_SIZE 0x1
+#define GC_USB_GINTSTS_EPMIS_DEFAULT 0x0
+#define GC_USB_GINTSTS_EPMIS_OFFSET 0x14
+#define GC_USB_GINTSTS_IEPINT_LSB 0x12
+#define GC_USB_GINTSTS_IEPINT_MASK 0x40000
+#define GC_USB_GINTSTS_IEPINT_SIZE 0x1
+#define GC_USB_GINTSTS_IEPINT_DEFAULT 0x0
+#define GC_USB_GINTSTS_IEPINT_OFFSET 0x14
+#define GC_USB_GINTSTS_OEPINT_LSB 0x13
+#define GC_USB_GINTSTS_OEPINT_MASK 0x80000
+#define GC_USB_GINTSTS_OEPINT_SIZE 0x1
+#define GC_USB_GINTSTS_OEPINT_DEFAULT 0x0
+#define GC_USB_GINTSTS_OEPINT_OFFSET 0x14
+#define GC_USB_GINTSTS_INCOMPISOIN_LSB 0x14
+#define GC_USB_GINTSTS_INCOMPISOIN_MASK 0x100000
+#define GC_USB_GINTSTS_INCOMPISOIN_SIZE 0x1
+#define GC_USB_GINTSTS_INCOMPISOIN_DEFAULT 0x0
+#define GC_USB_GINTSTS_INCOMPISOIN_OFFSET 0x14
+#define GC_USB_GINTSTS_INCOMPLP_LSB 0x15
+#define GC_USB_GINTSTS_INCOMPLP_MASK 0x200000
+#define GC_USB_GINTSTS_INCOMPLP_SIZE 0x1
+#define GC_USB_GINTSTS_INCOMPLP_DEFAULT 0x0
+#define GC_USB_GINTSTS_INCOMPLP_OFFSET 0x14
+#define GC_USB_GINTSTS_FETSUSP_LSB 0x16
+#define GC_USB_GINTSTS_FETSUSP_MASK 0x400000
+#define GC_USB_GINTSTS_FETSUSP_SIZE 0x1
+#define GC_USB_GINTSTS_FETSUSP_DEFAULT 0x0
+#define GC_USB_GINTSTS_FETSUSP_OFFSET 0x14
+#define GC_USB_GINTSTS_RESETDET_LSB 0x17
+#define GC_USB_GINTSTS_RESETDET_MASK 0x800000
+#define GC_USB_GINTSTS_RESETDET_SIZE 0x1
+#define GC_USB_GINTSTS_RESETDET_DEFAULT 0x0
+#define GC_USB_GINTSTS_RESETDET_OFFSET 0x14
+#define GC_USB_GINTSTS_CONIDSTSCHNG_LSB 0x1c
+#define GC_USB_GINTSTS_CONIDSTSCHNG_MASK 0x10000000
+#define GC_USB_GINTSTS_CONIDSTSCHNG_SIZE 0x1
+#define GC_USB_GINTSTS_CONIDSTSCHNG_DEFAULT 0x0
+#define GC_USB_GINTSTS_CONIDSTSCHNG_OFFSET 0x14
+#define GC_USB_GINTSTS_SESSREQINT_LSB 0x1e
+#define GC_USB_GINTSTS_SESSREQINT_MASK 0x40000000
+#define GC_USB_GINTSTS_SESSREQINT_SIZE 0x1
+#define GC_USB_GINTSTS_SESSREQINT_DEFAULT 0x0
+#define GC_USB_GINTSTS_SESSREQINT_OFFSET 0x14
+#define GC_USB_GINTSTS_WKUPINT_LSB 0x1f
+#define GC_USB_GINTSTS_WKUPINT_MASK 0x80000000
+#define GC_USB_GINTSTS_WKUPINT_SIZE 0x1
+#define GC_USB_GINTSTS_WKUPINT_DEFAULT 0x0
+#define GC_USB_GINTSTS_WKUPINT_OFFSET 0x14
+#define GC_USB_GINTMSK_MODEMISMSK_LSB 0x1
+#define GC_USB_GINTMSK_MODEMISMSK_MASK 0x2
+#define GC_USB_GINTMSK_MODEMISMSK_SIZE 0x1
+#define GC_USB_GINTMSK_MODEMISMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_MODEMISMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_OTGINTMSK_LSB 0x2
+#define GC_USB_GINTMSK_OTGINTMSK_MASK 0x4
+#define GC_USB_GINTMSK_OTGINTMSK_SIZE 0x1
+#define GC_USB_GINTMSK_OTGINTMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_OTGINTMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_SOFMSK_LSB 0x3
+#define GC_USB_GINTMSK_SOFMSK_MASK 0x8
+#define GC_USB_GINTMSK_SOFMSK_SIZE 0x1
+#define GC_USB_GINTMSK_SOFMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_SOFMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_RXFLVLMSK_LSB 0x4
+#define GC_USB_GINTMSK_RXFLVLMSK_MASK 0x10
+#define GC_USB_GINTMSK_RXFLVLMSK_SIZE 0x1
+#define GC_USB_GINTMSK_RXFLVLMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_RXFLVLMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_UNKNOWN5_LSB 0x5
+#define GC_USB_GINTMSK_UNKNOWN5_MASK 0x20
+#define GC_USB_GINTMSK_UNKNOWN5_SIZE 0x1
+#define GC_USB_GINTMSK_UNKNOWN5_DEFAULT 0x0
+#define GC_USB_GINTMSK_UNKNOWN5_OFFSET 0x18
+#define GC_USB_GINTMSK_GINNAKEFFMSK_LSB 0x6
+#define GC_USB_GINTMSK_GINNAKEFFMSK_MASK 0x40
+#define GC_USB_GINTMSK_GINNAKEFFMSK_SIZE 0x1
+#define GC_USB_GINTMSK_GINNAKEFFMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_GINNAKEFFMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_GOUTNAKEFFMSK_LSB 0x7
+#define GC_USB_GINTMSK_GOUTNAKEFFMSK_MASK 0x80
+#define GC_USB_GINTMSK_GOUTNAKEFFMSK_SIZE 0x1
+#define GC_USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_GOUTNAKEFFMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_ERLYSUSPMSK_LSB 0xa
+#define GC_USB_GINTMSK_ERLYSUSPMSK_MASK 0x400
+#define GC_USB_GINTMSK_ERLYSUSPMSK_SIZE 0x1
+#define GC_USB_GINTMSK_ERLYSUSPMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_ERLYSUSPMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_USBSUSPMSK_LSB 0xb
+#define GC_USB_GINTMSK_USBSUSPMSK_MASK 0x800
+#define GC_USB_GINTMSK_USBSUSPMSK_SIZE 0x1
+#define GC_USB_GINTMSK_USBSUSPMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_USBSUSPMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_USBRSTMSK_LSB 0xc
+#define GC_USB_GINTMSK_USBRSTMSK_MASK 0x1000
+#define GC_USB_GINTMSK_USBRSTMSK_SIZE 0x1
+#define GC_USB_GINTMSK_USBRSTMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_USBRSTMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_ENUMDONEMSK_LSB 0xd
+#define GC_USB_GINTMSK_ENUMDONEMSK_MASK 0x2000
+#define GC_USB_GINTMSK_ENUMDONEMSK_SIZE 0x1
+#define GC_USB_GINTMSK_ENUMDONEMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_ENUMDONEMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_ISOOUTDROPMSK_LSB 0xe
+#define GC_USB_GINTMSK_ISOOUTDROPMSK_MASK 0x4000
+#define GC_USB_GINTMSK_ISOOUTDROPMSK_SIZE 0x1
+#define GC_USB_GINTMSK_ISOOUTDROPMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_ISOOUTDROPMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_EOPFMSK_LSB 0xf
+#define GC_USB_GINTMSK_EOPFMSK_MASK 0x8000
+#define GC_USB_GINTMSK_EOPFMSK_SIZE 0x1
+#define GC_USB_GINTMSK_EOPFMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_EOPFMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_UNKNOWN16_LSB 0x10
+#define GC_USB_GINTMSK_UNKNOWN16_MASK 0x10000
+#define GC_USB_GINTMSK_UNKNOWN16_SIZE 0x1
+#define GC_USB_GINTMSK_UNKNOWN16_DEFAULT 0x0
+#define GC_USB_GINTMSK_UNKNOWN16_OFFSET 0x18
+#define GC_USB_GINTMSK_EPMISMSK_LSB 0x11
+#define GC_USB_GINTMSK_EPMISMSK_MASK 0x20000
+#define GC_USB_GINTMSK_EPMISMSK_SIZE 0x1
+#define GC_USB_GINTMSK_EPMISMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_EPMISMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_IEPINTMSK_LSB 0x12
+#define GC_USB_GINTMSK_IEPINTMSK_MASK 0x40000
+#define GC_USB_GINTMSK_IEPINTMSK_SIZE 0x1
+#define GC_USB_GINTMSK_IEPINTMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_IEPINTMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_OEPINTMSK_LSB 0x13
+#define GC_USB_GINTMSK_OEPINTMSK_MASK 0x80000
+#define GC_USB_GINTMSK_OEPINTMSK_SIZE 0x1
+#define GC_USB_GINTMSK_OEPINTMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_OEPINTMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_INCOMPISOINMSK_LSB 0x14
+#define GC_USB_GINTMSK_INCOMPISOINMSK_MASK 0x100000
+#define GC_USB_GINTMSK_INCOMPISOINMSK_SIZE 0x1
+#define GC_USB_GINTMSK_INCOMPISOINMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_INCOMPISOINMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_LSB 0x15
+#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_MASK 0x200000
+#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_SIZE 0x1
+#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_FETSUSPMSK_LSB 0x16
+#define GC_USB_GINTMSK_FETSUSPMSK_MASK 0x400000
+#define GC_USB_GINTMSK_FETSUSPMSK_SIZE 0x1
+#define GC_USB_GINTMSK_FETSUSPMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_FETSUSPMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_RESETDETMSK_LSB 0x17
+#define GC_USB_GINTMSK_RESETDETMSK_MASK 0x800000
+#define GC_USB_GINTMSK_RESETDETMSK_SIZE 0x1
+#define GC_USB_GINTMSK_RESETDETMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_RESETDETMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_LSB 0x1c
+#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_MASK 0x10000000
+#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_SIZE 0x1
+#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_DISCONNINTMSK_LSB 0x1d
+#define GC_USB_GINTMSK_DISCONNINTMSK_MASK 0x20000000
+#define GC_USB_GINTMSK_DISCONNINTMSK_SIZE 0x1
+#define GC_USB_GINTMSK_DISCONNINTMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_DISCONNINTMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_SESSREQINTMSK_LSB 0x1e
+#define GC_USB_GINTMSK_SESSREQINTMSK_MASK 0x40000000
+#define GC_USB_GINTMSK_SESSREQINTMSK_SIZE 0x1
+#define GC_USB_GINTMSK_SESSREQINTMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_SESSREQINTMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_WKUPINTMSK_LSB 0x1f
+#define GC_USB_GINTMSK_WKUPINTMSK_MASK 0x80000000
+#define GC_USB_GINTMSK_WKUPINTMSK_SIZE 0x1
+#define GC_USB_GINTMSK_WKUPINTMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_WKUPINTMSK_OFFSET 0x18
+#define GC_USB_GRXSTSR_CHNUM_LSB 0x0
+#define GC_USB_GRXSTSR_CHNUM_MASK 0xf
+#define GC_USB_GRXSTSR_CHNUM_SIZE 0x4
+#define GC_USB_GRXSTSR_CHNUM_DEFAULT 0x0
+#define GC_USB_GRXSTSR_CHNUM_OFFSET 0x1c
+#define GC_USB_GRXSTSR_BCNT_LSB 0x4
+#define GC_USB_GRXSTSR_BCNT_MASK 0x7ff0
+#define GC_USB_GRXSTSR_BCNT_SIZE 0xb
+#define GC_USB_GRXSTSR_BCNT_DEFAULT 0x0
+#define GC_USB_GRXSTSR_BCNT_OFFSET 0x1c
+#define GC_USB_GRXSTSR_DPID_LSB 0xf
+#define GC_USB_GRXSTSR_DPID_MASK 0x18000
+#define GC_USB_GRXSTSR_DPID_SIZE 0x2
+#define GC_USB_GRXSTSR_DPID_DEFAULT 0x0
+#define GC_USB_GRXSTSR_DPID_OFFSET 0x1c
+#define GC_USB_GRXSTSR_PKTSTS_LSB 0x11
+#define GC_USB_GRXSTSR_PKTSTS_MASK 0x1e0000
+#define GC_USB_GRXSTSR_PKTSTS_SIZE 0x4
+#define GC_USB_GRXSTSR_PKTSTS_DEFAULT 0x0
+#define GC_USB_GRXSTSR_PKTSTS_OFFSET 0x1c
+#define GC_USB_GRXSTSR_FN_LSB 0x15
+#define GC_USB_GRXSTSR_FN_MASK 0x1e00000
+#define GC_USB_GRXSTSR_FN_SIZE 0x4
+#define GC_USB_GRXSTSR_FN_DEFAULT 0x0
+#define GC_USB_GRXSTSR_FN_OFFSET 0x1c
+#define GC_USB_GRXSTSP_CHNUM_LSB 0x0
+#define GC_USB_GRXSTSP_CHNUM_MASK 0xf
+#define GC_USB_GRXSTSP_CHNUM_SIZE 0x4
+#define GC_USB_GRXSTSP_CHNUM_DEFAULT 0x0
+#define GC_USB_GRXSTSP_CHNUM_OFFSET 0x20
+#define GC_USB_GRXSTSP_BCNT_LSB 0x4
+#define GC_USB_GRXSTSP_BCNT_MASK 0x7ff0
+#define GC_USB_GRXSTSP_BCNT_SIZE 0xb
+#define GC_USB_GRXSTSP_BCNT_DEFAULT 0x0
+#define GC_USB_GRXSTSP_BCNT_OFFSET 0x20
+#define GC_USB_GRXSTSP_DPID_LSB 0xf
+#define GC_USB_GRXSTSP_DPID_MASK 0x18000
+#define GC_USB_GRXSTSP_DPID_SIZE 0x2
+#define GC_USB_GRXSTSP_DPID_DEFAULT 0x0
+#define GC_USB_GRXSTSP_DPID_OFFSET 0x20
+#define GC_USB_GRXSTSP_PKTSTS_LSB 0x11
+#define GC_USB_GRXSTSP_PKTSTS_MASK 0x1e0000
+#define GC_USB_GRXSTSP_PKTSTS_SIZE 0x4
+#define GC_USB_GRXSTSP_PKTSTS_DEFAULT 0x0
+#define GC_USB_GRXSTSP_PKTSTS_OFFSET 0x20
+#define GC_USB_GRXSTSP_FN_LSB 0x15
+#define GC_USB_GRXSTSP_FN_MASK 0x1e00000
+#define GC_USB_GRXSTSP_FN_SIZE 0x4
+#define GC_USB_GRXSTSP_FN_DEFAULT 0x0
+#define GC_USB_GRXSTSP_FN_OFFSET 0x20
+#define GC_USB_GRXFSIZ_RXFDEP_LSB 0x0
+#define GC_USB_GRXFSIZ_RXFDEP_MASK 0x7ff
+#define GC_USB_GRXFSIZ_RXFDEP_SIZE 0xb
+#define GC_USB_GRXFSIZ_RXFDEP_DEFAULT 0x0
+#define GC_USB_GRXFSIZ_RXFDEP_OFFSET 0x24
+#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_LSB 0x0
+#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_MASK 0xffff
+#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_SIZE 0x10
+#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_DEFAULT 0x0
+#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_OFFSET 0x28
+#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_LSB 0x10
+#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_MASK 0xffff0000
+#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_SIZE 0x10
+#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_DEFAULT 0x0
+#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_OFFSET 0x28
 
-#define GC_USB_GUID_GUID_LSB                     0x0
-#define GC_USB_GUID_GUID_MASK                    0xffffffff
-#define GC_USB_GUID_GUID_SIZE                    0x20
-#define GC_USB_GUID_GUID_DEFAULT                 0x0
-#define GC_USB_GUID_GUID_OFFSET                  0x3c
-#define GC_USB_GSNPSID_SYNOPSYSID_LSB            0x0
-#define GC_USB_GSNPSID_SYNOPSYSID_MASK           0xffffffff
-#define GC_USB_GSNPSID_SYNOPSYSID_SIZE           0x20
-#define GC_USB_GSNPSID_SYNOPSYSID_DEFAULT        0x0
-#define GC_USB_GSNPSID_SYNOPSYSID_OFFSET         0x40
-#define GC_USB_GHWCFG1_EPDIR_LSB                 0x0
-#define GC_USB_GHWCFG1_EPDIR_MASK                0xffffffff
-#define GC_USB_GHWCFG1_EPDIR_SIZE                0x20
-#define GC_USB_GHWCFG1_EPDIR_DEFAULT             0x0
-#define GC_USB_GHWCFG1_EPDIR_OFFSET              0x44
-#define GC_USB_GHWCFG2_OTGMODE_LSB               0x0
-#define GC_USB_GHWCFG2_OTGMODE_MASK              0x7
-#define GC_USB_GHWCFG2_OTGMODE_SIZE              0x3
-#define GC_USB_GHWCFG2_OTGMODE_DEFAULT           0x0
-#define GC_USB_GHWCFG2_OTGMODE_OFFSET            0x48
-#define GC_USB_GHWCFG2_OTGARCH_LSB               0x3
-#define GC_USB_GHWCFG2_OTGARCH_MASK              0x18
-#define GC_USB_GHWCFG2_OTGARCH_SIZE              0x2
-#define GC_USB_GHWCFG2_OTGARCH_DEFAULT           0x0
-#define GC_USB_GHWCFG2_OTGARCH_OFFSET            0x48
-#define GC_USB_GHWCFG2_SINGPNT_LSB               0x5
-#define GC_USB_GHWCFG2_SINGPNT_MASK              0x20
-#define GC_USB_GHWCFG2_SINGPNT_SIZE              0x1
-#define GC_USB_GHWCFG2_SINGPNT_DEFAULT           0x0
-#define GC_USB_GHWCFG2_SINGPNT_OFFSET            0x48
-#define GC_USB_GHWCFG2_HSPHYTYPE_LSB             0x6
-#define GC_USB_GHWCFG2_HSPHYTYPE_MASK            0xc0
-#define GC_USB_GHWCFG2_HSPHYTYPE_SIZE            0x2
-#define GC_USB_GHWCFG2_HSPHYTYPE_DEFAULT         0x0
-#define GC_USB_GHWCFG2_HSPHYTYPE_OFFSET          0x48
-#define GC_USB_GHWCFG2_FSPHYTYPE_LSB             0x8
-#define GC_USB_GHWCFG2_FSPHYTYPE_MASK            0x300
-#define GC_USB_GHWCFG2_FSPHYTYPE_SIZE            0x2
-#define GC_USB_GHWCFG2_FSPHYTYPE_DEFAULT         0x0
-#define GC_USB_GHWCFG2_FSPHYTYPE_OFFSET          0x48
-#define GC_USB_GHWCFG2_NUMDEVEPS_LSB             0xa
-#define GC_USB_GHWCFG2_NUMDEVEPS_MASK            0x3c00
-#define GC_USB_GHWCFG2_NUMDEVEPS_SIZE            0x4
-#define GC_USB_GHWCFG2_NUMDEVEPS_DEFAULT         0x0
-#define GC_USB_GHWCFG2_NUMDEVEPS_OFFSET          0x48
-#define GC_USB_GHWCFG2_NUMHSTCHNL_LSB            0xe
-#define GC_USB_GHWCFG2_NUMHSTCHNL_MASK           0x3c000
-#define GC_USB_GHWCFG2_NUMHSTCHNL_SIZE           0x4
-#define GC_USB_GHWCFG2_NUMHSTCHNL_DEFAULT        0x0
-#define GC_USB_GHWCFG2_NUMHSTCHNL_OFFSET         0x48
-#define GC_USB_GHWCFG2_PERIOSUPPORT_LSB          0x12
-#define GC_USB_GHWCFG2_PERIOSUPPORT_MASK         0x40000
-#define GC_USB_GHWCFG2_PERIOSUPPORT_SIZE         0x1
-#define GC_USB_GHWCFG2_PERIOSUPPORT_DEFAULT      0x0
-#define GC_USB_GHWCFG2_PERIOSUPPORT_OFFSET       0x48
-#define GC_USB_GHWCFG2_DYNFIFOSIZING_LSB         0x13
-#define GC_USB_GHWCFG2_DYNFIFOSIZING_MASK        0x80000
-#define GC_USB_GHWCFG2_DYNFIFOSIZING_SIZE        0x1
-#define GC_USB_GHWCFG2_DYNFIFOSIZING_DEFAULT     0x0
-#define GC_USB_GHWCFG2_DYNFIFOSIZING_OFFSET      0x48
-#define GC_USB_GHWCFG2_MULTIPROCINTRPT_LSB       0x14
-#define GC_USB_GHWCFG2_MULTIPROCINTRPT_MASK      0x100000
-#define GC_USB_GHWCFG2_MULTIPROCINTRPT_SIZE      0x1
-#define GC_USB_GHWCFG2_MULTIPROCINTRPT_DEFAULT   0x0
-#define GC_USB_GHWCFG2_MULTIPROCINTRPT_OFFSET    0x48
-#define GC_USB_GHWCFG2_NPTXQDEPTH_LSB            0x16
-#define GC_USB_GHWCFG2_NPTXQDEPTH_MASK           0xc00000
-#define GC_USB_GHWCFG2_NPTXQDEPTH_SIZE           0x2
-#define GC_USB_GHWCFG2_NPTXQDEPTH_DEFAULT        0x0
-#define GC_USB_GHWCFG2_NPTXQDEPTH_OFFSET         0x48
-#define GC_USB_GHWCFG2_PTXQDEPTH_LSB             0x18
-#define GC_USB_GHWCFG2_PTXQDEPTH_MASK            0x3000000
-#define GC_USB_GHWCFG2_PTXQDEPTH_SIZE            0x2
-#define GC_USB_GHWCFG2_PTXQDEPTH_DEFAULT         0x0
-#define GC_USB_GHWCFG2_PTXQDEPTH_OFFSET          0x48
-#define GC_USB_GHWCFG2_TKNQDEPTH_LSB             0x1a
-#define GC_USB_GHWCFG2_TKNQDEPTH_MASK            0x7c000000
-#define GC_USB_GHWCFG2_TKNQDEPTH_SIZE            0x5
-#define GC_USB_GHWCFG2_TKNQDEPTH_DEFAULT         0x0
-#define GC_USB_GHWCFG2_TKNQDEPTH_OFFSET          0x48
-#define GC_USB_GHWCFG3_XFERSIZEWIDTH_LSB         0x0
-#define GC_USB_GHWCFG3_XFERSIZEWIDTH_MASK        0xf
-#define GC_USB_GHWCFG3_XFERSIZEWIDTH_SIZE        0x4
-#define GC_USB_GHWCFG3_XFERSIZEWIDTH_DEFAULT     0x0
-#define GC_USB_GHWCFG3_XFERSIZEWIDTH_OFFSET      0x4c
-#define GC_USB_GHWCFG3_PKTSIZEWIDTH_LSB          0x4
-#define GC_USB_GHWCFG3_PKTSIZEWIDTH_MASK         0x70
-#define GC_USB_GHWCFG3_PKTSIZEWIDTH_SIZE         0x3
-#define GC_USB_GHWCFG3_PKTSIZEWIDTH_DEFAULT      0x0
-#define GC_USB_GHWCFG3_PKTSIZEWIDTH_OFFSET       0x4c
-#define GC_USB_GHWCFG3_OTGEN_LSB                 0x7
-#define GC_USB_GHWCFG3_OTGEN_MASK                0x80
-#define GC_USB_GHWCFG3_OTGEN_SIZE                0x1
-#define GC_USB_GHWCFG3_OTGEN_DEFAULT             0x0
-#define GC_USB_GHWCFG3_OTGEN_OFFSET              0x4c
-#define GC_USB_GHWCFG3_I2CINTSEL_LSB             0x8
-#define GC_USB_GHWCFG3_I2CINTSEL_MASK            0x100
-#define GC_USB_GHWCFG3_I2CINTSEL_SIZE            0x1
-#define GC_USB_GHWCFG3_I2CINTSEL_DEFAULT         0x0
-#define GC_USB_GHWCFG3_I2CINTSEL_OFFSET          0x4c
-#define GC_USB_GHWCFG3_VNDCTLSUPT_LSB            0x9
-#define GC_USB_GHWCFG3_VNDCTLSUPT_MASK           0x200
-#define GC_USB_GHWCFG3_VNDCTLSUPT_SIZE           0x1
-#define GC_USB_GHWCFG3_VNDCTLSUPT_DEFAULT        0x0
-#define GC_USB_GHWCFG3_VNDCTLSUPT_OFFSET         0x4c
-#define GC_USB_GHWCFG3_OPTFEATURE_LSB            0xa
-#define GC_USB_GHWCFG3_OPTFEATURE_MASK           0x400
-#define GC_USB_GHWCFG3_OPTFEATURE_SIZE           0x1
-#define GC_USB_GHWCFG3_OPTFEATURE_DEFAULT        0x0
-#define GC_USB_GHWCFG3_OPTFEATURE_OFFSET         0x4c
-#define GC_USB_GHWCFG3_RSTTYPE_LSB               0xb
-#define GC_USB_GHWCFG3_RSTTYPE_MASK              0x800
-#define GC_USB_GHWCFG3_RSTTYPE_SIZE              0x1
-#define GC_USB_GHWCFG3_RSTTYPE_DEFAULT           0x0
-#define GC_USB_GHWCFG3_RSTTYPE_OFFSET            0x4c
-#define GC_USB_GHWCFG3_ADPSUPPORT_LSB            0xc
-#define GC_USB_GHWCFG3_ADPSUPPORT_MASK           0x1000
-#define GC_USB_GHWCFG3_ADPSUPPORT_SIZE           0x1
-#define GC_USB_GHWCFG3_ADPSUPPORT_DEFAULT        0x0
-#define GC_USB_GHWCFG3_ADPSUPPORT_OFFSET         0x4c
-#define GC_USB_GHWCFG3_HSICMODE_LSB              0xd
-#define GC_USB_GHWCFG3_HSICMODE_MASK             0x2000
-#define GC_USB_GHWCFG3_HSICMODE_SIZE             0x1
-#define GC_USB_GHWCFG3_HSICMODE_DEFAULT          0x0
-#define GC_USB_GHWCFG3_HSICMODE_OFFSET           0x4c
-#define GC_USB_GHWCFG3_BCSUPPORT_LSB             0xe
-#define GC_USB_GHWCFG3_BCSUPPORT_MASK            0x4000
-#define GC_USB_GHWCFG3_BCSUPPORT_SIZE            0x1
-#define GC_USB_GHWCFG3_BCSUPPORT_DEFAULT         0x0
-#define GC_USB_GHWCFG3_BCSUPPORT_OFFSET          0x4c
-#define GC_USB_GHWCFG3_LPMMODE_LSB               0xf
-#define GC_USB_GHWCFG3_LPMMODE_MASK              0x8000
-#define GC_USB_GHWCFG3_LPMMODE_SIZE              0x1
-#define GC_USB_GHWCFG3_LPMMODE_DEFAULT           0x0
-#define GC_USB_GHWCFG3_LPMMODE_OFFSET            0x4c
-#define GC_USB_GHWCFG3_DFIFODEPTH_LSB            0x10
-#define GC_USB_GHWCFG3_DFIFODEPTH_MASK           0xffff0000
-#define GC_USB_GHWCFG3_DFIFODEPTH_SIZE           0x10
-#define GC_USB_GHWCFG3_DFIFODEPTH_DEFAULT        0x0
-#define GC_USB_GHWCFG3_DFIFODEPTH_OFFSET         0x4c
-#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_LSB        0x0
-#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_MASK       0xf
-#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_SIZE       0x4
-#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_DEFAULT    0x0
-#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_OFFSET     0x50
-#define GC_USB_GHWCFG4_PARTIALPWRDN_LSB          0x4
-#define GC_USB_GHWCFG4_PARTIALPWRDN_MASK         0x10
-#define GC_USB_GHWCFG4_PARTIALPWRDN_SIZE         0x1
-#define GC_USB_GHWCFG4_PARTIALPWRDN_DEFAULT      0x0
-#define GC_USB_GHWCFG4_PARTIALPWRDN_OFFSET       0x50
-#define GC_USB_GHWCFG4_AHBFREQ_LSB               0x5
-#define GC_USB_GHWCFG4_AHBFREQ_MASK              0x20
-#define GC_USB_GHWCFG4_AHBFREQ_SIZE              0x1
-#define GC_USB_GHWCFG4_AHBFREQ_DEFAULT           0x0
-#define GC_USB_GHWCFG4_AHBFREQ_OFFSET            0x50
-#define GC_USB_GHWCFG4_HIBERNATION_LSB           0x6
-#define GC_USB_GHWCFG4_HIBERNATION_MASK          0x40
-#define GC_USB_GHWCFG4_HIBERNATION_SIZE          0x1
-#define GC_USB_GHWCFG4_HIBERNATION_DEFAULT       0x0
-#define GC_USB_GHWCFG4_HIBERNATION_OFFSET        0x50
-#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_LSB   0x7
-#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_MASK  0x80
-#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_SIZE  0x1
+#define GC_USB_GUID_GUID_LSB 0x0
+#define GC_USB_GUID_GUID_MASK 0xffffffff
+#define GC_USB_GUID_GUID_SIZE 0x20
+#define GC_USB_GUID_GUID_DEFAULT 0x0
+#define GC_USB_GUID_GUID_OFFSET 0x3c
+#define GC_USB_GSNPSID_SYNOPSYSID_LSB 0x0
+#define GC_USB_GSNPSID_SYNOPSYSID_MASK 0xffffffff
+#define GC_USB_GSNPSID_SYNOPSYSID_SIZE 0x20
+#define GC_USB_GSNPSID_SYNOPSYSID_DEFAULT 0x0
+#define GC_USB_GSNPSID_SYNOPSYSID_OFFSET 0x40
+#define GC_USB_GHWCFG1_EPDIR_LSB 0x0
+#define GC_USB_GHWCFG1_EPDIR_MASK 0xffffffff
+#define GC_USB_GHWCFG1_EPDIR_SIZE 0x20
+#define GC_USB_GHWCFG1_EPDIR_DEFAULT 0x0
+#define GC_USB_GHWCFG1_EPDIR_OFFSET 0x44
+#define GC_USB_GHWCFG2_OTGMODE_LSB 0x0
+#define GC_USB_GHWCFG2_OTGMODE_MASK 0x7
+#define GC_USB_GHWCFG2_OTGMODE_SIZE 0x3
+#define GC_USB_GHWCFG2_OTGMODE_DEFAULT 0x0
+#define GC_USB_GHWCFG2_OTGMODE_OFFSET 0x48
+#define GC_USB_GHWCFG2_OTGARCH_LSB 0x3
+#define GC_USB_GHWCFG2_OTGARCH_MASK 0x18
+#define GC_USB_GHWCFG2_OTGARCH_SIZE 0x2
+#define GC_USB_GHWCFG2_OTGARCH_DEFAULT 0x0
+#define GC_USB_GHWCFG2_OTGARCH_OFFSET 0x48
+#define GC_USB_GHWCFG2_SINGPNT_LSB 0x5
+#define GC_USB_GHWCFG2_SINGPNT_MASK 0x20
+#define GC_USB_GHWCFG2_SINGPNT_SIZE 0x1
+#define GC_USB_GHWCFG2_SINGPNT_DEFAULT 0x0
+#define GC_USB_GHWCFG2_SINGPNT_OFFSET 0x48
+#define GC_USB_GHWCFG2_HSPHYTYPE_LSB 0x6
+#define GC_USB_GHWCFG2_HSPHYTYPE_MASK 0xc0
+#define GC_USB_GHWCFG2_HSPHYTYPE_SIZE 0x2
+#define GC_USB_GHWCFG2_HSPHYTYPE_DEFAULT 0x0
+#define GC_USB_GHWCFG2_HSPHYTYPE_OFFSET 0x48
+#define GC_USB_GHWCFG2_FSPHYTYPE_LSB 0x8
+#define GC_USB_GHWCFG2_FSPHYTYPE_MASK 0x300
+#define GC_USB_GHWCFG2_FSPHYTYPE_SIZE 0x2
+#define GC_USB_GHWCFG2_FSPHYTYPE_DEFAULT 0x0
+#define GC_USB_GHWCFG2_FSPHYTYPE_OFFSET 0x48
+#define GC_USB_GHWCFG2_NUMDEVEPS_LSB 0xa
+#define GC_USB_GHWCFG2_NUMDEVEPS_MASK 0x3c00
+#define GC_USB_GHWCFG2_NUMDEVEPS_SIZE 0x4
+#define GC_USB_GHWCFG2_NUMDEVEPS_DEFAULT 0x0
+#define GC_USB_GHWCFG2_NUMDEVEPS_OFFSET 0x48
+#define GC_USB_GHWCFG2_NUMHSTCHNL_LSB 0xe
+#define GC_USB_GHWCFG2_NUMHSTCHNL_MASK 0x3c000
+#define GC_USB_GHWCFG2_NUMHSTCHNL_SIZE 0x4
+#define GC_USB_GHWCFG2_NUMHSTCHNL_DEFAULT 0x0
+#define GC_USB_GHWCFG2_NUMHSTCHNL_OFFSET 0x48
+#define GC_USB_GHWCFG2_PERIOSUPPORT_LSB 0x12
+#define GC_USB_GHWCFG2_PERIOSUPPORT_MASK 0x40000
+#define GC_USB_GHWCFG2_PERIOSUPPORT_SIZE 0x1
+#define GC_USB_GHWCFG2_PERIOSUPPORT_DEFAULT 0x0
+#define GC_USB_GHWCFG2_PERIOSUPPORT_OFFSET 0x48
+#define GC_USB_GHWCFG2_DYNFIFOSIZING_LSB 0x13
+#define GC_USB_GHWCFG2_DYNFIFOSIZING_MASK 0x80000
+#define GC_USB_GHWCFG2_DYNFIFOSIZING_SIZE 0x1
+#define GC_USB_GHWCFG2_DYNFIFOSIZING_DEFAULT 0x0
+#define GC_USB_GHWCFG2_DYNFIFOSIZING_OFFSET 0x48
+#define GC_USB_GHWCFG2_MULTIPROCINTRPT_LSB 0x14
+#define GC_USB_GHWCFG2_MULTIPROCINTRPT_MASK 0x100000
+#define GC_USB_GHWCFG2_MULTIPROCINTRPT_SIZE 0x1
+#define GC_USB_GHWCFG2_MULTIPROCINTRPT_DEFAULT 0x0
+#define GC_USB_GHWCFG2_MULTIPROCINTRPT_OFFSET 0x48
+#define GC_USB_GHWCFG2_NPTXQDEPTH_LSB 0x16
+#define GC_USB_GHWCFG2_NPTXQDEPTH_MASK 0xc00000
+#define GC_USB_GHWCFG2_NPTXQDEPTH_SIZE 0x2
+#define GC_USB_GHWCFG2_NPTXQDEPTH_DEFAULT 0x0
+#define GC_USB_GHWCFG2_NPTXQDEPTH_OFFSET 0x48
+#define GC_USB_GHWCFG2_PTXQDEPTH_LSB 0x18
+#define GC_USB_GHWCFG2_PTXQDEPTH_MASK 0x3000000
+#define GC_USB_GHWCFG2_PTXQDEPTH_SIZE 0x2
+#define GC_USB_GHWCFG2_PTXQDEPTH_DEFAULT 0x0
+#define GC_USB_GHWCFG2_PTXQDEPTH_OFFSET 0x48
+#define GC_USB_GHWCFG2_TKNQDEPTH_LSB 0x1a
+#define GC_USB_GHWCFG2_TKNQDEPTH_MASK 0x7c000000
+#define GC_USB_GHWCFG2_TKNQDEPTH_SIZE 0x5
+#define GC_USB_GHWCFG2_TKNQDEPTH_DEFAULT 0x0
+#define GC_USB_GHWCFG2_TKNQDEPTH_OFFSET 0x48
+#define GC_USB_GHWCFG3_XFERSIZEWIDTH_LSB 0x0
+#define GC_USB_GHWCFG3_XFERSIZEWIDTH_MASK 0xf
+#define GC_USB_GHWCFG3_XFERSIZEWIDTH_SIZE 0x4
+#define GC_USB_GHWCFG3_XFERSIZEWIDTH_DEFAULT 0x0
+#define GC_USB_GHWCFG3_XFERSIZEWIDTH_OFFSET 0x4c
+#define GC_USB_GHWCFG3_PKTSIZEWIDTH_LSB 0x4
+#define GC_USB_GHWCFG3_PKTSIZEWIDTH_MASK 0x70
+#define GC_USB_GHWCFG3_PKTSIZEWIDTH_SIZE 0x3
+#define GC_USB_GHWCFG3_PKTSIZEWIDTH_DEFAULT 0x0
+#define GC_USB_GHWCFG3_PKTSIZEWIDTH_OFFSET 0x4c
+#define GC_USB_GHWCFG3_OTGEN_LSB 0x7
+#define GC_USB_GHWCFG3_OTGEN_MASK 0x80
+#define GC_USB_GHWCFG3_OTGEN_SIZE 0x1
+#define GC_USB_GHWCFG3_OTGEN_DEFAULT 0x0
+#define GC_USB_GHWCFG3_OTGEN_OFFSET 0x4c
+#define GC_USB_GHWCFG3_I2CINTSEL_LSB 0x8
+#define GC_USB_GHWCFG3_I2CINTSEL_MASK 0x100
+#define GC_USB_GHWCFG3_I2CINTSEL_SIZE 0x1
+#define GC_USB_GHWCFG3_I2CINTSEL_DEFAULT 0x0
+#define GC_USB_GHWCFG3_I2CINTSEL_OFFSET 0x4c
+#define GC_USB_GHWCFG3_VNDCTLSUPT_LSB 0x9
+#define GC_USB_GHWCFG3_VNDCTLSUPT_MASK 0x200
+#define GC_USB_GHWCFG3_VNDCTLSUPT_SIZE 0x1
+#define GC_USB_GHWCFG3_VNDCTLSUPT_DEFAULT 0x0
+#define GC_USB_GHWCFG3_VNDCTLSUPT_OFFSET 0x4c
+#define GC_USB_GHWCFG3_OPTFEATURE_LSB 0xa
+#define GC_USB_GHWCFG3_OPTFEATURE_MASK 0x400
+#define GC_USB_GHWCFG3_OPTFEATURE_SIZE 0x1
+#define GC_USB_GHWCFG3_OPTFEATURE_DEFAULT 0x0
+#define GC_USB_GHWCFG3_OPTFEATURE_OFFSET 0x4c
+#define GC_USB_GHWCFG3_RSTTYPE_LSB 0xb
+#define GC_USB_GHWCFG3_RSTTYPE_MASK 0x800
+#define GC_USB_GHWCFG3_RSTTYPE_SIZE 0x1
+#define GC_USB_GHWCFG3_RSTTYPE_DEFAULT 0x0
+#define GC_USB_GHWCFG3_RSTTYPE_OFFSET 0x4c
+#define GC_USB_GHWCFG3_ADPSUPPORT_LSB 0xc
+#define GC_USB_GHWCFG3_ADPSUPPORT_MASK 0x1000
+#define GC_USB_GHWCFG3_ADPSUPPORT_SIZE 0x1
+#define GC_USB_GHWCFG3_ADPSUPPORT_DEFAULT 0x0
+#define GC_USB_GHWCFG3_ADPSUPPORT_OFFSET 0x4c
+#define GC_USB_GHWCFG3_HSICMODE_LSB 0xd
+#define GC_USB_GHWCFG3_HSICMODE_MASK 0x2000
+#define GC_USB_GHWCFG3_HSICMODE_SIZE 0x1
+#define GC_USB_GHWCFG3_HSICMODE_DEFAULT 0x0
+#define GC_USB_GHWCFG3_HSICMODE_OFFSET 0x4c
+#define GC_USB_GHWCFG3_BCSUPPORT_LSB 0xe
+#define GC_USB_GHWCFG3_BCSUPPORT_MASK 0x4000
+#define GC_USB_GHWCFG3_BCSUPPORT_SIZE 0x1
+#define GC_USB_GHWCFG3_BCSUPPORT_DEFAULT 0x0
+#define GC_USB_GHWCFG3_BCSUPPORT_OFFSET 0x4c
+#define GC_USB_GHWCFG3_LPMMODE_LSB 0xf
+#define GC_USB_GHWCFG3_LPMMODE_MASK 0x8000
+#define GC_USB_GHWCFG3_LPMMODE_SIZE 0x1
+#define GC_USB_GHWCFG3_LPMMODE_DEFAULT 0x0
+#define GC_USB_GHWCFG3_LPMMODE_OFFSET 0x4c
+#define GC_USB_GHWCFG3_DFIFODEPTH_LSB 0x10
+#define GC_USB_GHWCFG3_DFIFODEPTH_MASK 0xffff0000
+#define GC_USB_GHWCFG3_DFIFODEPTH_SIZE 0x10
+#define GC_USB_GHWCFG3_DFIFODEPTH_DEFAULT 0x0
+#define GC_USB_GHWCFG3_DFIFODEPTH_OFFSET 0x4c
+#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_LSB 0x0
+#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_MASK 0xf
+#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_SIZE 0x4
+#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_DEFAULT 0x0
+#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_OFFSET 0x50
+#define GC_USB_GHWCFG4_PARTIALPWRDN_LSB 0x4
+#define GC_USB_GHWCFG4_PARTIALPWRDN_MASK 0x10
+#define GC_USB_GHWCFG4_PARTIALPWRDN_SIZE 0x1
+#define GC_USB_GHWCFG4_PARTIALPWRDN_DEFAULT 0x0
+#define GC_USB_GHWCFG4_PARTIALPWRDN_OFFSET 0x50
+#define GC_USB_GHWCFG4_AHBFREQ_LSB 0x5
+#define GC_USB_GHWCFG4_AHBFREQ_MASK 0x20
+#define GC_USB_GHWCFG4_AHBFREQ_SIZE 0x1
+#define GC_USB_GHWCFG4_AHBFREQ_DEFAULT 0x0
+#define GC_USB_GHWCFG4_AHBFREQ_OFFSET 0x50
+#define GC_USB_GHWCFG4_HIBERNATION_LSB 0x6
+#define GC_USB_GHWCFG4_HIBERNATION_MASK 0x40
+#define GC_USB_GHWCFG4_HIBERNATION_SIZE 0x1
+#define GC_USB_GHWCFG4_HIBERNATION_DEFAULT 0x0
+#define GC_USB_GHWCFG4_HIBERNATION_OFFSET 0x50
+#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_LSB 0x7
+#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_MASK 0x80
+#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_SIZE 0x1
 #define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_DEFAULT 0x0
 #define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_OFFSET 0x50
-#define GC_USB_GHWCFG4_PHYDATAWIDTH_LSB          0xe
-#define GC_USB_GHWCFG4_PHYDATAWIDTH_MASK         0xc000
-#define GC_USB_GHWCFG4_PHYDATAWIDTH_SIZE         0x2
-#define GC_USB_GHWCFG4_PHYDATAWIDTH_DEFAULT      0x0
-#define GC_USB_GHWCFG4_PHYDATAWIDTH_OFFSET       0x50
-#define GC_USB_GHWCFG4_NUMCTLEPS_LSB             0x10
-#define GC_USB_GHWCFG4_NUMCTLEPS_MASK            0xf0000
-#define GC_USB_GHWCFG4_NUMCTLEPS_SIZE            0x4
-#define GC_USB_GHWCFG4_NUMCTLEPS_DEFAULT         0x0
-#define GC_USB_GHWCFG4_NUMCTLEPS_OFFSET          0x50
-#define GC_USB_GHWCFG4_IDDGFLTR_LSB              0x14
-#define GC_USB_GHWCFG4_IDDGFLTR_MASK             0x100000
-#define GC_USB_GHWCFG4_IDDGFLTR_SIZE             0x1
-#define GC_USB_GHWCFG4_IDDGFLTR_DEFAULT          0x0
-#define GC_USB_GHWCFG4_IDDGFLTR_OFFSET           0x50
-#define GC_USB_GHWCFG4_VBUSVALIDFLTR_LSB         0x15
-#define GC_USB_GHWCFG4_VBUSVALIDFLTR_MASK        0x200000
-#define GC_USB_GHWCFG4_VBUSVALIDFLTR_SIZE        0x1
-#define GC_USB_GHWCFG4_VBUSVALIDFLTR_DEFAULT     0x0
-#define GC_USB_GHWCFG4_VBUSVALIDFLTR_OFFSET      0x50
-#define GC_USB_GHWCFG4_AVALIDFLTR_LSB            0x16
-#define GC_USB_GHWCFG4_AVALIDFLTR_MASK           0x400000
-#define GC_USB_GHWCFG4_AVALIDFLTR_SIZE           0x1
-#define GC_USB_GHWCFG4_AVALIDFLTR_DEFAULT        0x0
-#define GC_USB_GHWCFG4_AVALIDFLTR_OFFSET         0x50
-#define GC_USB_GHWCFG4_BVALIDFLTR_LSB            0x17
-#define GC_USB_GHWCFG4_BVALIDFLTR_MASK           0x800000
-#define GC_USB_GHWCFG4_BVALIDFLTR_SIZE           0x1
-#define GC_USB_GHWCFG4_BVALIDFLTR_DEFAULT        0x0
-#define GC_USB_GHWCFG4_BVALIDFLTR_OFFSET         0x50
-#define GC_USB_GHWCFG4_SESSENDFLTR_LSB           0x18
-#define GC_USB_GHWCFG4_SESSENDFLTR_MASK          0x1000000
-#define GC_USB_GHWCFG4_SESSENDFLTR_SIZE          0x1
-#define GC_USB_GHWCFG4_SESSENDFLTR_DEFAULT       0x0
-#define GC_USB_GHWCFG4_SESSENDFLTR_OFFSET        0x50
-#define GC_USB_GHWCFG4_DEDFIFOMODE_LSB           0x19
-#define GC_USB_GHWCFG4_DEDFIFOMODE_MASK          0x2000000
-#define GC_USB_GHWCFG4_DEDFIFOMODE_SIZE          0x1
-#define GC_USB_GHWCFG4_DEDFIFOMODE_DEFAULT       0x0
-#define GC_USB_GHWCFG4_DEDFIFOMODE_OFFSET        0x50
-#define GC_USB_GHWCFG4_INEPS_LSB                 0x1a
-#define GC_USB_GHWCFG4_INEPS_MASK                0x3c000000
-#define GC_USB_GHWCFG4_INEPS_SIZE                0x4
-#define GC_USB_GHWCFG4_INEPS_DEFAULT             0x0
-#define GC_USB_GHWCFG4_INEPS_OFFSET              0x50
-#define GC_USB_GHWCFG4_DESCDMAENABLED_LSB        0x1e
-#define GC_USB_GHWCFG4_DESCDMAENABLED_MASK       0x40000000
-#define GC_USB_GHWCFG4_DESCDMAENABLED_SIZE       0x1
-#define GC_USB_GHWCFG4_DESCDMAENABLED_DEFAULT    0x0
-#define GC_USB_GHWCFG4_DESCDMAENABLED_OFFSET     0x50
-#define GC_USB_GHWCFG4_DESCDMA_LSB               0x1f
-#define GC_USB_GHWCFG4_DESCDMA_MASK              0x80000000
-#define GC_USB_GHWCFG4_DESCDMA_SIZE              0x1
-#define GC_USB_GHWCFG4_DESCDMA_DEFAULT           0x0
-#define GC_USB_GHWCFG4_DESCDMA_OFFSET            0x50
-#define GC_USB_GDFIFOCFG_GDFIFOCFG_LSB           0x0
-#define GC_USB_GDFIFOCFG_GDFIFOCFG_MASK          0xffff
-#define GC_USB_GDFIFOCFG_GDFIFOCFG_SIZE          0x10
-#define GC_USB_GDFIFOCFG_GDFIFOCFG_DEFAULT       0x0
-#define GC_USB_GDFIFOCFG_GDFIFOCFG_OFFSET        0x5c
-#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_LSB      0x10
-#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_MASK     0xffff0000
-#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_SIZE     0x10
-#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_DEFAULT  0x0
-#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_OFFSET   0x5c
-#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_OFFSET    0x104
-#define GC_USB_DIEPTXF1_RESERVED11_LSB           0xc
-#define GC_USB_DIEPTXF1_RESERVED11_MASK          0x1000
-#define GC_USB_DIEPTXF1_RESERVED11_SIZE          0x1
-#define GC_USB_DIEPTXF1_RESERVED11_DEFAULT       0x1
-#define GC_USB_DIEPTXF1_RESERVED11_OFFSET        0x104
-#define GC_USB_DIEPTXF1_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF1_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF1_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF1_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF1_INEPNTXFDEP_OFFSET       0x104
-#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_OFFSET    0x108
-#define GC_USB_DIEPTXF2_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF2_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF2_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF2_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF2_INEPNTXFDEP_OFFSET       0x108
-#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_OFFSET    0x10c
-#define GC_USB_DIEPTXF3_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF3_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF3_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF3_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF3_INEPNTXFDEP_OFFSET       0x10c
-#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_OFFSET    0x110
-#define GC_USB_DIEPTXF4_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF4_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF4_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF4_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF4_INEPNTXFDEP_OFFSET       0x110
-#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_OFFSET    0x114
-#define GC_USB_DIEPTXF5_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF5_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF5_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF5_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF5_INEPNTXFDEP_OFFSET       0x114
-#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_OFFSET    0x118
-#define GC_USB_DIEPTXF6_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF6_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF6_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF6_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF6_INEPNTXFDEP_OFFSET       0x118
-#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_OFFSET    0x11c
-#define GC_USB_DIEPTXF7_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF7_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF7_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF7_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF7_INEPNTXFDEP_OFFSET       0x11c
-#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_OFFSET    0x120
-#define GC_USB_DIEPTXF8_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF8_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF8_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF8_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF8_INEPNTXFDEP_OFFSET       0x120
-#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_OFFSET    0x124
-#define GC_USB_DIEPTXF9_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF9_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF9_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF9_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF9_INEPNTXFDEP_OFFSET       0x124
-#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_LSB      0x0
-#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_MASK     0x7ff
-#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_SIZE     0xb
-#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_DEFAULT  0x0
-#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_OFFSET   0x128
-#define GC_USB_DIEPTXF10_INEPNTXFDEP_LSB         0x10
-#define GC_USB_DIEPTXF10_INEPNTXFDEP_MASK        0x3f0000
-#define GC_USB_DIEPTXF10_INEPNTXFDEP_SIZE        0x6
-#define GC_USB_DIEPTXF10_INEPNTXFDEP_DEFAULT     0x0
-#define GC_USB_DIEPTXF10_INEPNTXFDEP_OFFSET      0x128
-#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_LSB      0x0
-#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_MASK     0x7ff
-#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_SIZE     0xb
-#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_DEFAULT  0x0
-#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_OFFSET   0x12c
-#define GC_USB_DIEPTXF11_INEPNTXFDEP_LSB         0x10
-#define GC_USB_DIEPTXF11_INEPNTXFDEP_MASK        0x3f0000
-#define GC_USB_DIEPTXF11_INEPNTXFDEP_SIZE        0x6
-#define GC_USB_DIEPTXF11_INEPNTXFDEP_DEFAULT     0x0
-#define GC_USB_DIEPTXF11_INEPNTXFDEP_OFFSET      0x12c
-#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_LSB      0x0
-#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_MASK     0x7ff
-#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_SIZE     0xb
-#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_DEFAULT  0x0
-#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_OFFSET   0x130
-#define GC_USB_DIEPTXF12_INEPNTXFDEP_LSB         0x10
-#define GC_USB_DIEPTXF12_INEPNTXFDEP_MASK        0x3f0000
-#define GC_USB_DIEPTXF12_INEPNTXFDEP_SIZE        0x6
-#define GC_USB_DIEPTXF12_INEPNTXFDEP_DEFAULT     0x0
-#define GC_USB_DIEPTXF12_INEPNTXFDEP_OFFSET      0x130
-#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_LSB      0x0
-#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_MASK     0x7ff
-#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_SIZE     0xb
-#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_DEFAULT  0x0
-#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_OFFSET   0x134
-#define GC_USB_DIEPTXF13_INEPNTXFDEP_LSB         0x10
-#define GC_USB_DIEPTXF13_INEPNTXFDEP_MASK        0x3f0000
-#define GC_USB_DIEPTXF13_INEPNTXFDEP_SIZE        0x6
-#define GC_USB_DIEPTXF13_INEPNTXFDEP_DEFAULT     0x0
-#define GC_USB_DIEPTXF13_INEPNTXFDEP_OFFSET      0x134
-#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_LSB      0x0
-#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_MASK     0x7ff
-#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_SIZE     0xb
-#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_DEFAULT  0x0
-#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_OFFSET   0x138
-#define GC_USB_DIEPTXF14_INEPNTXFDEP_LSB         0x10
-#define GC_USB_DIEPTXF14_INEPNTXFDEP_MASK        0x3f0000
-#define GC_USB_DIEPTXF14_INEPNTXFDEP_SIZE        0x6
-#define GC_USB_DIEPTXF14_INEPNTXFDEP_DEFAULT     0x0
-#define GC_USB_DIEPTXF14_INEPNTXFDEP_OFFSET      0x138
-#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_LSB      0x0
-#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_MASK     0x7ff
-#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_SIZE     0xb
-#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_DEFAULT  0x0
-#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_OFFSET   0x13c
-#define GC_USB_DIEPTXF15_INEPNTXFDEP_LSB         0x10
-#define GC_USB_DIEPTXF15_INEPNTXFDEP_MASK        0x3f0000
-#define GC_USB_DIEPTXF15_INEPNTXFDEP_SIZE        0x6
-#define GC_USB_DIEPTXF15_INEPNTXFDEP_DEFAULT     0x0
-#define GC_USB_DIEPTXF15_INEPNTXFDEP_OFFSET      0x13c
-#define GC_USB_DCFG_DEVSPD_LSB                   0x0
-#define GC_USB_DCFG_DEVSPD_MASK                  0x3
-#define GC_USB_DCFG_DEVSPD_SIZE                  0x2
-#define GC_USB_DCFG_DEVSPD_DEFAULT               0x0
-#define GC_USB_DCFG_DEVSPD_OFFSET                0x800
-#define GC_USB_DCFG_NZSTSOUTHSHK_LSB             0x2
-#define GC_USB_DCFG_NZSTSOUTHSHK_MASK            0x4
-#define GC_USB_DCFG_NZSTSOUTHSHK_SIZE            0x1
-#define GC_USB_DCFG_NZSTSOUTHSHK_DEFAULT         0x0
-#define GC_USB_DCFG_NZSTSOUTHSHK_OFFSET          0x800
-#define GC_USB_DCFG_ENA32KHZSUSP_LSB             0x3
-#define GC_USB_DCFG_ENA32KHZSUSP_MASK            0x8
-#define GC_USB_DCFG_ENA32KHZSUSP_SIZE            0x1
-#define GC_USB_DCFG_ENA32KHZSUSP_DEFAULT         0x0
-#define GC_USB_DCFG_ENA32KHZSUSP_OFFSET          0x800
-#define GC_USB_DCFG_DEVADDR_LSB                  0x4
-#define GC_USB_DCFG_DEVADDR_MASK                 0x7f0
-#define GC_USB_DCFG_DEVADDR_SIZE                 0x7
-#define GC_USB_DCFG_DEVADDR_DEFAULT              0x0
-#define GC_USB_DCFG_DEVADDR_OFFSET               0x800
-#define GC_USB_DCFG_PERFRINT_LSB                 0xb
-#define GC_USB_DCFG_PERFRINT_MASK                0x1800
-#define GC_USB_DCFG_PERFRINT_SIZE                0x2
-#define GC_USB_DCFG_PERFRINT_DEFAULT             0x0
-#define GC_USB_DCFG_PERFRINT_OFFSET              0x800
-#define GC_USB_DCFG_ENDEVOUTNAK_LSB              0xd
-#define GC_USB_DCFG_ENDEVOUTNAK_MASK             0x2000
-#define GC_USB_DCFG_ENDEVOUTNAK_SIZE             0x1
-#define GC_USB_DCFG_ENDEVOUTNAK_DEFAULT          0x0
-#define GC_USB_DCFG_ENDEVOUTNAK_OFFSET           0x800
-#define GC_USB_DCFG_XCVRDLY_LSB                  0xe
-#define GC_USB_DCFG_XCVRDLY_MASK                 0x4000
-#define GC_USB_DCFG_XCVRDLY_SIZE                 0x1
-#define GC_USB_DCFG_XCVRDLY_DEFAULT              0x0
-#define GC_USB_DCFG_XCVRDLY_OFFSET               0x800
-#define GC_USB_DCFG_ERRATICINTMSK_LSB            0xf
-#define GC_USB_DCFG_ERRATICINTMSK_MASK           0x8000
-#define GC_USB_DCFG_ERRATICINTMSK_SIZE           0x1
-#define GC_USB_DCFG_ERRATICINTMSK_DEFAULT        0x0
-#define GC_USB_DCFG_ERRATICINTMSK_OFFSET         0x800
-#define GC_USB_DCFG_DESCDMA_LSB                  0x17
-#define GC_USB_DCFG_DESCDMA_MASK                 0x800000
-#define GC_USB_DCFG_DESCDMA_SIZE                 0x1
-#define GC_USB_DCFG_DESCDMA_DEFAULT              0x0
-#define GC_USB_DCFG_DESCDMA_OFFSET               0x800
-#define GC_USB_DCFG_PERSCHINTVL_LSB              0x18
-#define GC_USB_DCFG_PERSCHINTVL_MASK             0x3000000
-#define GC_USB_DCFG_PERSCHINTVL_SIZE             0x2
-#define GC_USB_DCFG_PERSCHINTVL_DEFAULT          0x0
-#define GC_USB_DCFG_PERSCHINTVL_OFFSET           0x800
-#define GC_USB_DCFG_RESVALID_LSB                 0x1a
-#define GC_USB_DCFG_RESVALID_MASK                0xfc000000
-#define GC_USB_DCFG_RESVALID_SIZE                0x6
-#define GC_USB_DCFG_RESVALID_DEFAULT             0x2
-#define GC_USB_DCFG_RESVALID_OFFSET              0x800
-#define GC_USB_DCTL_RMTWKUPSIG_LSB               0x0
-#define GC_USB_DCTL_RMTWKUPSIG_MASK              0x1
-#define GC_USB_DCTL_RMTWKUPSIG_SIZE              0x1
-#define GC_USB_DCTL_RMTWKUPSIG_DEFAULT           0x0
-#define GC_USB_DCTL_RMTWKUPSIG_OFFSET            0x804
-#define GC_USB_DCTL_SFTDISCON_LSB                0x1
-#define GC_USB_DCTL_SFTDISCON_MASK               0x2
-#define GC_USB_DCTL_SFTDISCON_SIZE               0x1
-#define GC_USB_DCTL_SFTDISCON_DEFAULT            0x0
-#define GC_USB_DCTL_SFTDISCON_OFFSET             0x804
-#define GC_USB_DCTL_GNPINNAKSTS_LSB              0x2
-#define GC_USB_DCTL_GNPINNAKSTS_MASK             0x4
-#define GC_USB_DCTL_GNPINNAKSTS_SIZE             0x1
-#define GC_USB_DCTL_GNPINNAKSTS_DEFAULT          0x0
-#define GC_USB_DCTL_GNPINNAKSTS_OFFSET           0x804
-#define GC_USB_DCTL_GOUTNAKSTS_LSB               0x3
-#define GC_USB_DCTL_GOUTNAKSTS_MASK              0x8
-#define GC_USB_DCTL_GOUTNAKSTS_SIZE              0x1
-#define GC_USB_DCTL_GOUTNAKSTS_DEFAULT           0x0
-#define GC_USB_DCTL_GOUTNAKSTS_OFFSET            0x804
-#define GC_USB_DCTL_TSTCTL_LSB                   0x4
-#define GC_USB_DCTL_TSTCTL_MASK                  0x70
-#define GC_USB_DCTL_TSTCTL_SIZE                  0x3
-#define GC_USB_DCTL_TSTCTL_DEFAULT               0x0
-#define GC_USB_DCTL_TSTCTL_OFFSET                0x804
-#define GC_USB_DCTL_SGNPINNAK_LSB                0x7
-#define GC_USB_DCTL_SGNPINNAK_MASK               0x80
-#define GC_USB_DCTL_SGNPINNAK_SIZE               0x1
-#define GC_USB_DCTL_SGNPINNAK_DEFAULT            0x0
-#define GC_USB_DCTL_SGNPINNAK_OFFSET             0x804
-#define GC_USB_DCTL_CGNPINNAK_LSB                0x8
-#define GC_USB_DCTL_CGNPINNAK_MASK               0x100
-#define GC_USB_DCTL_CGNPINNAK_SIZE               0x1
-#define GC_USB_DCTL_CGNPINNAK_DEFAULT            0x0
-#define GC_USB_DCTL_CGNPINNAK_OFFSET             0x804
-#define GC_USB_DCTL_SGOUTNAK_LSB                 0x9
-#define GC_USB_DCTL_SGOUTNAK_MASK                0x200
-#define GC_USB_DCTL_SGOUTNAK_SIZE                0x1
-#define GC_USB_DCTL_SGOUTNAK_DEFAULT             0x0
-#define GC_USB_DCTL_SGOUTNAK_OFFSET              0x804
-#define GC_USB_DCTL_CGOUTNAK_LSB                 0xa
-#define GC_USB_DCTL_CGOUTNAK_MASK                0x400
-#define GC_USB_DCTL_CGOUTNAK_SIZE                0x1
-#define GC_USB_DCTL_CGOUTNAK_DEFAULT             0x0
-#define GC_USB_DCTL_CGOUTNAK_OFFSET              0x804
-#define GC_USB_DCTL_PWRONPRGDONE_LSB             0xb
-#define GC_USB_DCTL_PWRONPRGDONE_MASK            0x800
-#define GC_USB_DCTL_PWRONPRGDONE_SIZE            0x1
-#define GC_USB_DCTL_PWRONPRGDONE_DEFAULT         0x0
-#define GC_USB_DCTL_PWRONPRGDONE_OFFSET          0x804
-#define GC_USB_DCTL_GMC_LSB                      0xd
-#define GC_USB_DCTL_GMC_MASK                     0x6000
-#define GC_USB_DCTL_GMC_SIZE                     0x2
-#define GC_USB_DCTL_GMC_DEFAULT                  0x0
-#define GC_USB_DCTL_GMC_OFFSET                   0x804
-#define GC_USB_DCTL_IGNRFRMNUM_LSB               0xf
-#define GC_USB_DCTL_IGNRFRMNUM_MASK              0x8000
-#define GC_USB_DCTL_IGNRFRMNUM_SIZE              0x1
-#define GC_USB_DCTL_IGNRFRMNUM_DEFAULT           0x0
-#define GC_USB_DCTL_IGNRFRMNUM_OFFSET            0x804
-#define GC_USB_DCTL_NAKONBBLE_LSB                0x10
-#define GC_USB_DCTL_NAKONBBLE_MASK               0x10000
-#define GC_USB_DCTL_NAKONBBLE_SIZE               0x1
-#define GC_USB_DCTL_NAKONBBLE_DEFAULT            0x0
-#define GC_USB_DCTL_NAKONBBLE_OFFSET             0x804
-#define GC_USB_DCTL_ENCONTONBNA_LSB              0x11
-#define GC_USB_DCTL_ENCONTONBNA_MASK             0x20000
-#define GC_USB_DCTL_ENCONTONBNA_SIZE             0x1
-#define GC_USB_DCTL_ENCONTONBNA_DEFAULT          0x0
-#define GC_USB_DCTL_ENCONTONBNA_OFFSET           0x804
-#define GC_USB_DSTS_SUSPSTS_LSB                  0x0
-#define GC_USB_DSTS_SUSPSTS_MASK                 0x1
-#define GC_USB_DSTS_SUSPSTS_SIZE                 0x1
-#define GC_USB_DSTS_SUSPSTS_DEFAULT              0x0
-#define GC_USB_DSTS_SUSPSTS_OFFSET               0x808
-#define GC_USB_DSTS_ENUMSPD_LSB                  0x1
-#define GC_USB_DSTS_ENUMSPD_MASK                 0x6
-#define GC_USB_DSTS_ENUMSPD_SIZE                 0x2
-#define GC_USB_DSTS_ENUMSPD_DEFAULT              0x0
-#define GC_USB_DSTS_ENUMSPD_OFFSET               0x808
-#define GC_USB_DSTS_ERRTICERR_LSB                0x3
-#define GC_USB_DSTS_ERRTICERR_MASK               0x8
-#define GC_USB_DSTS_ERRTICERR_SIZE               0x1
-#define GC_USB_DSTS_ERRTICERR_DEFAULT            0x0
-#define GC_USB_DSTS_ERRTICERR_OFFSET             0x808
-#define GC_USB_DSTS_SOFFN_LSB                    0x8
-#define GC_USB_DSTS_SOFFN_MASK                   0x3fff00
-#define GC_USB_DSTS_SOFFN_SIZE                   0xe
-#define GC_USB_DSTS_SOFFN_DEFAULT                0x0
-#define GC_USB_DSTS_SOFFN_OFFSET                 0x808
-#define GC_USB_DSTS_DEVLNSTS_LSB                 0x16
-#define GC_USB_DSTS_DEVLNSTS_MASK                0xc00000
-#define GC_USB_DSTS_DEVLNSTS_SIZE                0x2
-#define GC_USB_DSTS_DEVLNSTS_DEFAULT             0x0
-#define GC_USB_DSTS_DEVLNSTS_OFFSET              0x808
-#define GC_USB_DIEPMSK_XFERCOMPLMSK_LSB          0x0
-#define GC_USB_DIEPMSK_XFERCOMPLMSK_MASK         0x1
-#define GC_USB_DIEPMSK_XFERCOMPLMSK_SIZE         0x1
-#define GC_USB_DIEPMSK_XFERCOMPLMSK_DEFAULT      0x0
-#define GC_USB_DIEPMSK_XFERCOMPLMSK_OFFSET       0x810
-#define GC_USB_DIEPMSK_EPDISBLDMSK_LSB           0x1
-#define GC_USB_DIEPMSK_EPDISBLDMSK_MASK          0x2
-#define GC_USB_DIEPMSK_EPDISBLDMSK_SIZE          0x1
-#define GC_USB_DIEPMSK_EPDISBLDMSK_DEFAULT       0x0
-#define GC_USB_DIEPMSK_EPDISBLDMSK_OFFSET        0x810
-#define GC_USB_DIEPMSK_AHBERRMSK_LSB             0x2
-#define GC_USB_DIEPMSK_AHBERRMSK_MASK            0x4
-#define GC_USB_DIEPMSK_AHBERRMSK_SIZE            0x1
-#define GC_USB_DIEPMSK_AHBERRMSK_DEFAULT         0x0
-#define GC_USB_DIEPMSK_AHBERRMSK_OFFSET          0x810
-#define GC_USB_DIEPMSK_TIMEOUTMSK_LSB            0x3
-#define GC_USB_DIEPMSK_TIMEOUTMSK_MASK           0x8
-#define GC_USB_DIEPMSK_TIMEOUTMSK_SIZE           0x1
-#define GC_USB_DIEPMSK_TIMEOUTMSK_DEFAULT        0x0
-#define GC_USB_DIEPMSK_TIMEOUTMSK_OFFSET         0x810
-#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_LSB        0x4
-#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_MASK       0x10
-#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_SIZE       0x1
-#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_DEFAULT    0x0
-#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_OFFSET     0x810
-#define GC_USB_DIEPMSK_INTKNEPMISMSK_LSB         0x5
-#define GC_USB_DIEPMSK_INTKNEPMISMSK_MASK        0x20
-#define GC_USB_DIEPMSK_INTKNEPMISMSK_SIZE        0x1
-#define GC_USB_DIEPMSK_INTKNEPMISMSK_DEFAULT     0x0
-#define GC_USB_DIEPMSK_INTKNEPMISMSK_OFFSET      0x810
-#define GC_USB_DIEPMSK_INEPNAKEFFMSK_LSB         0x6
-#define GC_USB_DIEPMSK_INEPNAKEFFMSK_MASK        0x40
-#define GC_USB_DIEPMSK_INEPNAKEFFMSK_SIZE        0x1
-#define GC_USB_DIEPMSK_INEPNAKEFFMSK_DEFAULT     0x0
-#define GC_USB_DIEPMSK_INEPNAKEFFMSK_OFFSET      0x810
-#define GC_USB_DIEPMSK_RESERVED7_LSB             0x7
-#define GC_USB_DIEPMSK_RESERVED7_MASK            0x80
-#define GC_USB_DIEPMSK_RESERVED7_SIZE            0x1
-#define GC_USB_DIEPMSK_RESERVED7_DEFAULT         0x1
-#define GC_USB_DIEPMSK_RESERVED7_OFFSET          0x810
-#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_LSB        0x8
-#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_MASK       0x100
-#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_SIZE       0x1
-#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_DEFAULT    0x0
-#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_OFFSET     0x810
-#define GC_USB_DIEPMSK_BNAININTRMSK_LSB          0x9
-#define GC_USB_DIEPMSK_BNAININTRMSK_MASK         0x200
-#define GC_USB_DIEPMSK_BNAININTRMSK_SIZE         0x1
-#define GC_USB_DIEPMSK_BNAININTRMSK_DEFAULT      0x0
-#define GC_USB_DIEPMSK_BNAININTRMSK_OFFSET       0x810
-#define GC_USB_DIEPMSK_NAKMSK_LSB                0xd
-#define GC_USB_DIEPMSK_NAKMSK_MASK               0x2000
-#define GC_USB_DIEPMSK_NAKMSK_SIZE               0x1
-#define GC_USB_DIEPMSK_NAKMSK_DEFAULT            0x0
-#define GC_USB_DIEPMSK_NAKMSK_OFFSET             0x810
-#define GC_USB_DOEPMSK_XFERCOMPLMSK_LSB          0x0
-#define GC_USB_DOEPMSK_XFERCOMPLMSK_MASK         0x1
-#define GC_USB_DOEPMSK_XFERCOMPLMSK_SIZE         0x1
-#define GC_USB_DOEPMSK_XFERCOMPLMSK_DEFAULT      0x0
-#define GC_USB_DOEPMSK_XFERCOMPLMSK_OFFSET       0x814
-#define GC_USB_DOEPMSK_EPDISBLDMSK_LSB           0x1
-#define GC_USB_DOEPMSK_EPDISBLDMSK_MASK          0x2
-#define GC_USB_DOEPMSK_EPDISBLDMSK_SIZE          0x1
-#define GC_USB_DOEPMSK_EPDISBLDMSK_DEFAULT       0x0
-#define GC_USB_DOEPMSK_EPDISBLDMSK_OFFSET        0x814
-#define GC_USB_DOEPMSK_AHBERRMSK_LSB             0x2
-#define GC_USB_DOEPMSK_AHBERRMSK_MASK            0x4
-#define GC_USB_DOEPMSK_AHBERRMSK_SIZE            0x1
-#define GC_USB_DOEPMSK_AHBERRMSK_DEFAULT         0x0
-#define GC_USB_DOEPMSK_AHBERRMSK_OFFSET          0x814
-#define GC_USB_DOEPMSK_SETUPMSK_LSB              0x3
-#define GC_USB_DOEPMSK_SETUPMSK_MASK             0x8
-#define GC_USB_DOEPMSK_SETUPMSK_SIZE             0x1
-#define GC_USB_DOEPMSK_SETUPMSK_DEFAULT          0x0
-#define GC_USB_DOEPMSK_SETUPMSK_OFFSET           0x814
-#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_LSB        0x4
-#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_MASK       0x10
-#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_SIZE       0x1
-#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_DEFAULT    0x0
-#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_OFFSET     0x814
-#define GC_USB_DOEPMSK_STSPHSERCVDMSK_LSB        0x5
-#define GC_USB_DOEPMSK_STSPHSERCVDMSK_MASK       0x20
-#define GC_USB_DOEPMSK_STSPHSERCVDMSK_SIZE       0x1
-#define GC_USB_DOEPMSK_STSPHSERCVDMSK_DEFAULT    0x0
-#define GC_USB_DOEPMSK_STSPHSERCVDMSK_OFFSET     0x814
-#define GC_USB_DOEPMSK_BACK2BACKSETUP_LSB        0x6
-#define GC_USB_DOEPMSK_BACK2BACKSETUP_MASK       0x40
-#define GC_USB_DOEPMSK_BACK2BACKSETUP_SIZE       0x1
-#define GC_USB_DOEPMSK_BACK2BACKSETUP_DEFAULT    0x0
-#define GC_USB_DOEPMSK_BACK2BACKSETUP_OFFSET     0x814
-#define GC_USB_DOEPMSK_OUTPKTERRMSK_LSB          0x8
-#define GC_USB_DOEPMSK_OUTPKTERRMSK_MASK         0x100
-#define GC_USB_DOEPMSK_OUTPKTERRMSK_SIZE         0x1
-#define GC_USB_DOEPMSK_OUTPKTERRMSK_DEFAULT      0x0
-#define GC_USB_DOEPMSK_OUTPKTERRMSK_OFFSET       0x814
-#define GC_USB_DOEPMSK_BNAOUTINTRMSK_LSB         0x9
-#define GC_USB_DOEPMSK_BNAOUTINTRMSK_MASK        0x200
-#define GC_USB_DOEPMSK_BNAOUTINTRMSK_SIZE        0x1
-#define GC_USB_DOEPMSK_BNAOUTINTRMSK_DEFAULT     0x0
-#define GC_USB_DOEPMSK_BNAOUTINTRMSK_OFFSET      0x814
-#define GC_USB_DOEPMSK_BBLEERRMSK_LSB            0xc
-#define GC_USB_DOEPMSK_BBLEERRMSK_MASK           0x1000
-#define GC_USB_DOEPMSK_BBLEERRMSK_SIZE           0x1
-#define GC_USB_DOEPMSK_BBLEERRMSK_DEFAULT        0x0
-#define GC_USB_DOEPMSK_BBLEERRMSK_OFFSET         0x814
-#define GC_USB_DOEPMSK_NAKMSK_LSB                0xd
-#define GC_USB_DOEPMSK_NAKMSK_MASK               0x2000
-#define GC_USB_DOEPMSK_NAKMSK_SIZE               0x1
-#define GC_USB_DOEPMSK_NAKMSK_DEFAULT            0x0
-#define GC_USB_DOEPMSK_NAKMSK_OFFSET             0x814
-#define GC_USB_DOEPMSK_NYETMSK_LSB               0xe
-#define GC_USB_DOEPMSK_NYETMSK_MASK              0x4000
-#define GC_USB_DOEPMSK_NYETMSK_SIZE              0x1
-#define GC_USB_DOEPMSK_NYETMSK_DEFAULT           0x0
-#define GC_USB_DOEPMSK_NYETMSK_OFFSET            0x814
-#define GC_USB_DAINT_INEPINT0_LSB                0x0
-#define GC_USB_DAINT_INEPINT0_MASK               0x1
-#define GC_USB_DAINT_INEPINT0_SIZE               0x1
-#define GC_USB_DAINT_INEPINT0_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT0_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT1_LSB                0x1
-#define GC_USB_DAINT_INEPINT1_MASK               0x2
-#define GC_USB_DAINT_INEPINT1_SIZE               0x1
-#define GC_USB_DAINT_INEPINT1_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT1_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT2_LSB                0x2
-#define GC_USB_DAINT_INEPINT2_MASK               0x4
-#define GC_USB_DAINT_INEPINT2_SIZE               0x1
-#define GC_USB_DAINT_INEPINT2_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT2_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT3_LSB                0x3
-#define GC_USB_DAINT_INEPINT3_MASK               0x8
-#define GC_USB_DAINT_INEPINT3_SIZE               0x1
-#define GC_USB_DAINT_INEPINT3_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT3_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT4_LSB                0x4
-#define GC_USB_DAINT_INEPINT4_MASK               0x10
-#define GC_USB_DAINT_INEPINT4_SIZE               0x1
-#define GC_USB_DAINT_INEPINT4_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT4_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT5_LSB                0x5
-#define GC_USB_DAINT_INEPINT5_MASK               0x20
-#define GC_USB_DAINT_INEPINT5_SIZE               0x1
-#define GC_USB_DAINT_INEPINT5_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT5_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT6_LSB                0x6
-#define GC_USB_DAINT_INEPINT6_MASK               0x40
-#define GC_USB_DAINT_INEPINT6_SIZE               0x1
-#define GC_USB_DAINT_INEPINT6_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT6_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT7_LSB                0x7
-#define GC_USB_DAINT_INEPINT7_MASK               0x80
-#define GC_USB_DAINT_INEPINT7_SIZE               0x1
-#define GC_USB_DAINT_INEPINT7_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT7_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT8_LSB                0x8
-#define GC_USB_DAINT_INEPINT8_MASK               0x100
-#define GC_USB_DAINT_INEPINT8_SIZE               0x1
-#define GC_USB_DAINT_INEPINT8_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT8_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT9_LSB                0x9
-#define GC_USB_DAINT_INEPINT9_MASK               0x200
-#define GC_USB_DAINT_INEPINT9_SIZE               0x1
-#define GC_USB_DAINT_INEPINT9_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT9_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT10_LSB               0xa
-#define GC_USB_DAINT_INEPINT10_MASK              0x400
-#define GC_USB_DAINT_INEPINT10_SIZE              0x1
-#define GC_USB_DAINT_INEPINT10_DEFAULT           0x0
-#define GC_USB_DAINT_INEPINT10_OFFSET            0x818
-#define GC_USB_DAINT_INEPINT11_LSB               0xb
-#define GC_USB_DAINT_INEPINT11_MASK              0x800
-#define GC_USB_DAINT_INEPINT11_SIZE              0x1
-#define GC_USB_DAINT_INEPINT11_DEFAULT           0x0
-#define GC_USB_DAINT_INEPINT11_OFFSET            0x818
-#define GC_USB_DAINT_INEPINT12_LSB               0xc
-#define GC_USB_DAINT_INEPINT12_MASK              0x1000
-#define GC_USB_DAINT_INEPINT12_SIZE              0x1
-#define GC_USB_DAINT_INEPINT12_DEFAULT           0x0
-#define GC_USB_DAINT_INEPINT12_OFFSET            0x818
-#define GC_USB_DAINT_INEPINT13_LSB               0xd
-#define GC_USB_DAINT_INEPINT13_MASK              0x2000
-#define GC_USB_DAINT_INEPINT13_SIZE              0x1
-#define GC_USB_DAINT_INEPINT13_DEFAULT           0x0
-#define GC_USB_DAINT_INEPINT13_OFFSET            0x818
-#define GC_USB_DAINT_INEPINT14_LSB               0xe
-#define GC_USB_DAINT_INEPINT14_MASK              0x4000
-#define GC_USB_DAINT_INEPINT14_SIZE              0x1
-#define GC_USB_DAINT_INEPINT14_DEFAULT           0x0
-#define GC_USB_DAINT_INEPINT14_OFFSET            0x818
-#define GC_USB_DAINT_INEPINT15_LSB               0xf
-#define GC_USB_DAINT_INEPINT15_MASK              0x8000
-#define GC_USB_DAINT_INEPINT15_SIZE              0x1
-#define GC_USB_DAINT_INEPINT15_DEFAULT           0x0
-#define GC_USB_DAINT_INEPINT15_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT0_LSB               0x10
-#define GC_USB_DAINT_OUTEPINT0_MASK              0x10000
-#define GC_USB_DAINT_OUTEPINT0_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT0_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT0_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT1_LSB               0x11
-#define GC_USB_DAINT_OUTEPINT1_MASK              0x20000
-#define GC_USB_DAINT_OUTEPINT1_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT1_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT1_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT2_LSB               0x12
-#define GC_USB_DAINT_OUTEPINT2_MASK              0x40000
-#define GC_USB_DAINT_OUTEPINT2_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT2_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT2_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT3_LSB               0x13
-#define GC_USB_DAINT_OUTEPINT3_MASK              0x80000
-#define GC_USB_DAINT_OUTEPINT3_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT3_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT3_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT4_LSB               0x14
-#define GC_USB_DAINT_OUTEPINT4_MASK              0x100000
-#define GC_USB_DAINT_OUTEPINT4_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT4_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT4_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT5_LSB               0x15
-#define GC_USB_DAINT_OUTEPINT5_MASK              0x200000
-#define GC_USB_DAINT_OUTEPINT5_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT5_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT5_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT6_LSB               0x16
-#define GC_USB_DAINT_OUTEPINT6_MASK              0x400000
-#define GC_USB_DAINT_OUTEPINT6_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT6_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT6_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT7_LSB               0x17
-#define GC_USB_DAINT_OUTEPINT7_MASK              0x800000
-#define GC_USB_DAINT_OUTEPINT7_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT7_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT7_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT8_LSB               0x18
-#define GC_USB_DAINT_OUTEPINT8_MASK              0x1000000
-#define GC_USB_DAINT_OUTEPINT8_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT8_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT8_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT9_LSB               0x19
-#define GC_USB_DAINT_OUTEPINT9_MASK              0x2000000
-#define GC_USB_DAINT_OUTEPINT9_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT9_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT9_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT10_LSB              0x1a
-#define GC_USB_DAINT_OUTEPINT10_MASK             0x4000000
-#define GC_USB_DAINT_OUTEPINT10_SIZE             0x1
-#define GC_USB_DAINT_OUTEPINT10_DEFAULT          0x0
-#define GC_USB_DAINT_OUTEPINT10_OFFSET           0x818
-#define GC_USB_DAINT_OUTEPINT11_LSB              0x1b
-#define GC_USB_DAINT_OUTEPINT11_MASK             0x8000000
-#define GC_USB_DAINT_OUTEPINT11_SIZE             0x1
-#define GC_USB_DAINT_OUTEPINT11_DEFAULT          0x0
-#define GC_USB_DAINT_OUTEPINT11_OFFSET           0x818
-#define GC_USB_DAINT_OUTEPINT12_LSB              0x1c
-#define GC_USB_DAINT_OUTEPINT12_MASK             0x10000000
-#define GC_USB_DAINT_OUTEPINT12_SIZE             0x1
-#define GC_USB_DAINT_OUTEPINT12_DEFAULT          0x0
-#define GC_USB_DAINT_OUTEPINT12_OFFSET           0x818
-#define GC_USB_DAINT_OUTEPINT13_LSB              0x1d
-#define GC_USB_DAINT_OUTEPINT13_MASK             0x20000000
-#define GC_USB_DAINT_OUTEPINT13_SIZE             0x1
-#define GC_USB_DAINT_OUTEPINT13_DEFAULT          0x0
-#define GC_USB_DAINT_OUTEPINT13_OFFSET           0x818
-#define GC_USB_DAINT_OUTEPINT14_LSB              0x1e
-#define GC_USB_DAINT_OUTEPINT14_MASK             0x40000000
-#define GC_USB_DAINT_OUTEPINT14_SIZE             0x1
-#define GC_USB_DAINT_OUTEPINT14_DEFAULT          0x0
-#define GC_USB_DAINT_OUTEPINT14_OFFSET           0x818
-#define GC_USB_DAINT_OUTEPINT15_LSB              0x1f
-#define GC_USB_DAINT_OUTEPINT15_MASK             0x80000000
-#define GC_USB_DAINT_OUTEPINT15_SIZE             0x1
-#define GC_USB_DAINT_OUTEPINT15_DEFAULT          0x0
-#define GC_USB_DAINT_OUTEPINT15_OFFSET           0x818
-#define GC_USB_DAINTMSK_INEPMSK0_LSB             0x0
-#define GC_USB_DAINTMSK_INEPMSK0_MASK            0x1
-#define GC_USB_DAINTMSK_INEPMSK0_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK0_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK0_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK1_LSB             0x1
-#define GC_USB_DAINTMSK_INEPMSK1_MASK            0x2
-#define GC_USB_DAINTMSK_INEPMSK1_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK1_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK1_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK2_LSB             0x2
-#define GC_USB_DAINTMSK_INEPMSK2_MASK            0x4
-#define GC_USB_DAINTMSK_INEPMSK2_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK2_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK2_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK3_LSB             0x3
-#define GC_USB_DAINTMSK_INEPMSK3_MASK            0x8
-#define GC_USB_DAINTMSK_INEPMSK3_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK3_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK3_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK4_LSB             0x4
-#define GC_USB_DAINTMSK_INEPMSK4_MASK            0x10
-#define GC_USB_DAINTMSK_INEPMSK4_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK4_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK4_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK5_LSB             0x5
-#define GC_USB_DAINTMSK_INEPMSK5_MASK            0x20
-#define GC_USB_DAINTMSK_INEPMSK5_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK5_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK5_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK6_LSB             0x6
-#define GC_USB_DAINTMSK_INEPMSK6_MASK            0x40
-#define GC_USB_DAINTMSK_INEPMSK6_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK6_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK6_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK7_LSB             0x7
-#define GC_USB_DAINTMSK_INEPMSK7_MASK            0x80
-#define GC_USB_DAINTMSK_INEPMSK7_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK7_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK7_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK8_LSB             0x8
-#define GC_USB_DAINTMSK_INEPMSK8_MASK            0x100
-#define GC_USB_DAINTMSK_INEPMSK8_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK8_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK8_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK9_LSB             0x9
-#define GC_USB_DAINTMSK_INEPMSK9_MASK            0x200
-#define GC_USB_DAINTMSK_INEPMSK9_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK9_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK9_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK10_LSB            0xa
-#define GC_USB_DAINTMSK_INEPMSK10_MASK           0x400
-#define GC_USB_DAINTMSK_INEPMSK10_SIZE           0x1
-#define GC_USB_DAINTMSK_INEPMSK10_DEFAULT        0x0
-#define GC_USB_DAINTMSK_INEPMSK10_OFFSET         0x81c
-#define GC_USB_DAINTMSK_INEPMSK11_LSB            0xb
-#define GC_USB_DAINTMSK_INEPMSK11_MASK           0x800
-#define GC_USB_DAINTMSK_INEPMSK11_SIZE           0x1
-#define GC_USB_DAINTMSK_INEPMSK11_DEFAULT        0x0
-#define GC_USB_DAINTMSK_INEPMSK11_OFFSET         0x81c
-#define GC_USB_DAINTMSK_INEPMSK12_LSB            0xc
-#define GC_USB_DAINTMSK_INEPMSK12_MASK           0x1000
-#define GC_USB_DAINTMSK_INEPMSK12_SIZE           0x1
-#define GC_USB_DAINTMSK_INEPMSK12_DEFAULT        0x0
-#define GC_USB_DAINTMSK_INEPMSK12_OFFSET         0x81c
-#define GC_USB_DAINTMSK_INEPMSK13_LSB            0xd
-#define GC_USB_DAINTMSK_INEPMSK13_MASK           0x2000
-#define GC_USB_DAINTMSK_INEPMSK13_SIZE           0x1
-#define GC_USB_DAINTMSK_INEPMSK13_DEFAULT        0x0
-#define GC_USB_DAINTMSK_INEPMSK13_OFFSET         0x81c
-#define GC_USB_DAINTMSK_INEPMSK14_LSB            0xe
-#define GC_USB_DAINTMSK_INEPMSK14_MASK           0x4000
-#define GC_USB_DAINTMSK_INEPMSK14_SIZE           0x1
-#define GC_USB_DAINTMSK_INEPMSK14_DEFAULT        0x0
-#define GC_USB_DAINTMSK_INEPMSK14_OFFSET         0x81c
-#define GC_USB_DAINTMSK_INEPMSK15_LSB            0xf
-#define GC_USB_DAINTMSK_INEPMSK15_MASK           0x8000
-#define GC_USB_DAINTMSK_INEPMSK15_SIZE           0x1
-#define GC_USB_DAINTMSK_INEPMSK15_DEFAULT        0x0
-#define GC_USB_DAINTMSK_INEPMSK15_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK0_LSB            0x10
-#define GC_USB_DAINTMSK_OUTEPMSK0_MASK           0x10000
-#define GC_USB_DAINTMSK_OUTEPMSK0_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK0_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK0_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK1_LSB            0x11
-#define GC_USB_DAINTMSK_OUTEPMSK1_MASK           0x20000
-#define GC_USB_DAINTMSK_OUTEPMSK1_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK1_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK1_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK2_LSB            0x12
-#define GC_USB_DAINTMSK_OUTEPMSK2_MASK           0x40000
-#define GC_USB_DAINTMSK_OUTEPMSK2_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK2_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK2_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK3_LSB            0x13
-#define GC_USB_DAINTMSK_OUTEPMSK3_MASK           0x80000
-#define GC_USB_DAINTMSK_OUTEPMSK3_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK3_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK3_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK4_LSB            0x14
-#define GC_USB_DAINTMSK_OUTEPMSK4_MASK           0x100000
-#define GC_USB_DAINTMSK_OUTEPMSK4_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK4_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK4_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK5_LSB            0x15
-#define GC_USB_DAINTMSK_OUTEPMSK5_MASK           0x200000
-#define GC_USB_DAINTMSK_OUTEPMSK5_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK5_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK5_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK6_LSB            0x16
-#define GC_USB_DAINTMSK_OUTEPMSK6_MASK           0x400000
-#define GC_USB_DAINTMSK_OUTEPMSK6_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK6_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK6_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK7_LSB            0x17
-#define GC_USB_DAINTMSK_OUTEPMSK7_MASK           0x800000
-#define GC_USB_DAINTMSK_OUTEPMSK7_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK7_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK7_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK8_LSB            0x18
-#define GC_USB_DAINTMSK_OUTEPMSK8_MASK           0x1000000
-#define GC_USB_DAINTMSK_OUTEPMSK8_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK8_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK8_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK9_LSB            0x19
-#define GC_USB_DAINTMSK_OUTEPMSK9_MASK           0x2000000
-#define GC_USB_DAINTMSK_OUTEPMSK9_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK9_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK9_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK10_LSB           0x1a
-#define GC_USB_DAINTMSK_OUTEPMSK10_MASK          0x4000000
-#define GC_USB_DAINTMSK_OUTEPMSK10_SIZE          0x1
-#define GC_USB_DAINTMSK_OUTEPMSK10_DEFAULT       0x0
-#define GC_USB_DAINTMSK_OUTEPMSK10_OFFSET        0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK11_LSB           0x1b
-#define GC_USB_DAINTMSK_OUTEPMSK11_MASK          0x8000000
-#define GC_USB_DAINTMSK_OUTEPMSK11_SIZE          0x1
-#define GC_USB_DAINTMSK_OUTEPMSK11_DEFAULT       0x0
-#define GC_USB_DAINTMSK_OUTEPMSK11_OFFSET        0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK12_LSB           0x1c
-#define GC_USB_DAINTMSK_OUTEPMSK12_MASK          0x10000000
-#define GC_USB_DAINTMSK_OUTEPMSK12_SIZE          0x1
-#define GC_USB_DAINTMSK_OUTEPMSK12_DEFAULT       0x0
-#define GC_USB_DAINTMSK_OUTEPMSK12_OFFSET        0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK13_LSB           0x1d
-#define GC_USB_DAINTMSK_OUTEPMSK13_MASK          0x20000000
-#define GC_USB_DAINTMSK_OUTEPMSK13_SIZE          0x1
-#define GC_USB_DAINTMSK_OUTEPMSK13_DEFAULT       0x0
-#define GC_USB_DAINTMSK_OUTEPMSK13_OFFSET        0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK14_LSB           0x1e
-#define GC_USB_DAINTMSK_OUTEPMSK14_MASK          0x40000000
-#define GC_USB_DAINTMSK_OUTEPMSK14_SIZE          0x1
-#define GC_USB_DAINTMSK_OUTEPMSK14_DEFAULT       0x0
-#define GC_USB_DAINTMSK_OUTEPMSK14_OFFSET        0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK15_LSB           0x1f
-#define GC_USB_DAINTMSK_OUTEPMSK15_MASK          0x80000000
-#define GC_USB_DAINTMSK_OUTEPMSK15_SIZE          0x1
-#define GC_USB_DAINTMSK_OUTEPMSK15_DEFAULT       0x0
-#define GC_USB_DAINTMSK_OUTEPMSK15_OFFSET        0x81c
-#define GC_USB_DVBUSDIS_DVBUSDIS_LSB             0x0
-#define GC_USB_DVBUSDIS_DVBUSDIS_MASK            0xffff
-#define GC_USB_DVBUSDIS_DVBUSDIS_SIZE            0x10
-#define GC_USB_DVBUSDIS_DVBUSDIS_DEFAULT         0x0
-#define GC_USB_DVBUSDIS_DVBUSDIS_OFFSET          0x828
-#define GC_USB_DVBUSPULSE_DVBUSPULSE_LSB         0x0
-#define GC_USB_DVBUSPULSE_DVBUSPULSE_MASK        0xfff
-#define GC_USB_DVBUSPULSE_DVBUSPULSE_SIZE        0xc
-#define GC_USB_DVBUSPULSE_DVBUSPULSE_DEFAULT     0x0
-#define GC_USB_DVBUSPULSE_DVBUSPULSE_OFFSET      0x82c
-#define GC_USB_DTHRCTL_NONISOTHREN_LSB           0x0
-#define GC_USB_DTHRCTL_NONISOTHREN_MASK          0x1
-#define GC_USB_DTHRCTL_NONISOTHREN_SIZE          0x1
-#define GC_USB_DTHRCTL_NONISOTHREN_DEFAULT       0x0
-#define GC_USB_DTHRCTL_NONISOTHREN_OFFSET        0x830
-#define GC_USB_DTHRCTL_ISOTHREN_LSB              0x1
-#define GC_USB_DTHRCTL_ISOTHREN_MASK             0x2
-#define GC_USB_DTHRCTL_ISOTHREN_SIZE             0x1
-#define GC_USB_DTHRCTL_ISOTHREN_DEFAULT          0x0
-#define GC_USB_DTHRCTL_ISOTHREN_OFFSET           0x830
-#define GC_USB_DTHRCTL_TXTHRLEN_LSB              0x2
-#define GC_USB_DTHRCTL_TXTHRLEN_MASK             0x7fc
-#define GC_USB_DTHRCTL_TXTHRLEN_SIZE             0x9
-#define GC_USB_DTHRCTL_TXTHRLEN_DEFAULT          0x0
-#define GC_USB_DTHRCTL_TXTHRLEN_OFFSET           0x830
-#define GC_USB_DTHRCTL_AHBTHRRATIO_LSB           0xb
-#define GC_USB_DTHRCTL_AHBTHRRATIO_MASK          0x1800
-#define GC_USB_DTHRCTL_AHBTHRRATIO_SIZE          0x2
-#define GC_USB_DTHRCTL_AHBTHRRATIO_DEFAULT       0x0
-#define GC_USB_DTHRCTL_AHBTHRRATIO_OFFSET        0x830
-#define GC_USB_DTHRCTL_RXTHREN_LSB               0x10
-#define GC_USB_DTHRCTL_RXTHREN_MASK              0x10000
-#define GC_USB_DTHRCTL_RXTHREN_SIZE              0x1
-#define GC_USB_DTHRCTL_RXTHREN_DEFAULT           0x0
-#define GC_USB_DTHRCTL_RXTHREN_OFFSET            0x830
-#define GC_USB_DTHRCTL_RXTHRLEN_LSB              0x11
-#define GC_USB_DTHRCTL_RXTHRLEN_MASK             0x3fe0000
-#define GC_USB_DTHRCTL_RXTHRLEN_SIZE             0x9
-#define GC_USB_DTHRCTL_RXTHRLEN_DEFAULT          0x0
-#define GC_USB_DTHRCTL_RXTHRLEN_OFFSET           0x830
-#define GC_USB_DTHRCTL_ARBPRKEN_LSB              0x1b
-#define GC_USB_DTHRCTL_ARBPRKEN_MASK             0x8000000
-#define GC_USB_DTHRCTL_ARBPRKEN_SIZE             0x1
-#define GC_USB_DTHRCTL_ARBPRKEN_DEFAULT          0x0
-#define GC_USB_DTHRCTL_ARBPRKEN_OFFSET           0x830
-#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_LSB      0x0
-#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_MASK     0xffff
-#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_SIZE     0x10
-#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_DEFAULT  0x0
-#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_OFFSET   0x834
-#define GC_USB_DIEPCTL0_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL0_MPS_MASK                 0x3
-#define GC_USB_DIEPCTL0_MPS_SIZE                 0x2
-#define GC_USB_DIEPCTL0_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL0_MPS_OFFSET               0x900
-#define GC_USB_DIEPCTL0_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL0_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL0_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL0_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL0_USBACTEP_OFFSET          0x900
-#define GC_USB_DIEPCTL0_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL0_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL0_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL0_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL0_NAKSTS_OFFSET            0x900
-#define GC_USB_DIEPCTL0_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL0_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL0_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL0_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL0_EPTYPE_OFFSET            0x900
-#define GC_USB_DIEPCTL0_STALL_LSB                0x15
-#define GC_USB_DIEPCTL0_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL0_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL0_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL0_STALL_OFFSET             0x900
-#define GC_USB_DIEPCTL0_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL0_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL0_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL0_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL0_TXFNUM_OFFSET            0x900
-#define GC_USB_DIEPCTL0_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL0_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL0_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL0_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL0_CNAK_OFFSET              0x900
-#define GC_USB_DIEPCTL0_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL0_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL0_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL0_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL0_SNAK_OFFSET              0x900
-#define GC_USB_DIEPCTL0_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL0_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL0_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL0_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL0_EPDIS_OFFSET             0x900
-#define GC_USB_DIEPCTL0_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL0_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL0_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL0_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL0_EPENA_OFFSET             0x900
-#define GC_USB_DIEPINT0_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT0_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT0_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT0_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT0_XFERCOMPL_OFFSET         0x908
-#define GC_USB_DIEPINT0_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT0_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT0_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT0_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT0_EPDISBLD_OFFSET          0x908
-#define GC_USB_DIEPINT0_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT0_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT0_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT0_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT0_AHBERR_OFFSET            0x908
-#define GC_USB_DIEPINT0_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT0_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT0_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT0_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT0_TIMEOUT_OFFSET           0x908
-#define GC_USB_DIEPINT0_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT0_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT0_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT0_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT0_INTKNTXFEMP_OFFSET       0x908
-#define GC_USB_DIEPINT0_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT0_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT0_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT0_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT0_INTKNEPMIS_OFFSET        0x908
-#define GC_USB_DIEPINT0_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT0_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT0_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT0_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT0_INEPNAKEFF_OFFSET        0x908
-#define GC_USB_DIEPINT0_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT0_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT0_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT0_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT0_TXFEMP_OFFSET            0x908
-#define GC_USB_DIEPINT0_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT0_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT0_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT0_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT0_TXFIFOUNDRN_OFFSET       0x908
-#define GC_USB_DIEPINT0_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT0_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT0_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT0_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT0_BNAINTR_OFFSET           0x908
-#define GC_USB_DIEPINT0_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT0_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT0_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT0_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT0_PKTDRPSTS_OFFSET         0x908
-#define GC_USB_DIEPINT0_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT0_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT0_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT0_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT0_BBLEERR_OFFSET           0x908
-#define GC_USB_DIEPINT0_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT0_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT0_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT0_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT0_NAKINTRPT_OFFSET         0x908
-#define GC_USB_DIEPINT0_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT0_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT0_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT0_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT0_NYETINTRPT_OFFSET        0x908
-#define GC_USB_DIEPTSIZ0_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ0_XFERSIZE_MASK           0x7f
-#define GC_USB_DIEPTSIZ0_XFERSIZE_SIZE           0x7
-#define GC_USB_DIEPTSIZ0_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ0_XFERSIZE_OFFSET         0x910
-#define GC_USB_DIEPTSIZ0_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ0_PKTCNT_MASK             0x180000
-#define GC_USB_DIEPTSIZ0_PKTCNT_SIZE             0x2
-#define GC_USB_DIEPTSIZ0_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ0_PKTCNT_OFFSET           0x910
-#define GC_USB_DIEPDMA0_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA0_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA0_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA0_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA0_DMAADDR_OFFSET           0x914
-#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_OFFSET   0x918
-#define GC_USB_DIEPDMAB0_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB0_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB0_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB0_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB0_DMABUFFERADDR_OFFSET    0x91c
-#define GC_USB_DIEPCTL1_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL1_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL1_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL1_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL1_MPS_OFFSET               0x920
-#define GC_USB_DIEPCTL1_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL1_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL1_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL1_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL1_USBACTEP_OFFSET          0x920
-#define GC_USB_DIEPCTL1_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL1_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL1_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL1_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL1_DPID_OFFSET              0x920
-#define GC_USB_DIEPCTL1_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL1_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL1_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL1_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL1_NAKSTS_OFFSET            0x920
-#define GC_USB_DIEPCTL1_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL1_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL1_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL1_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL1_EPTYPE_OFFSET            0x920
-#define GC_USB_DIEPCTL1_STALL_LSB                0x15
-#define GC_USB_DIEPCTL1_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL1_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL1_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL1_STALL_OFFSET             0x920
-#define GC_USB_DIEPCTL1_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL1_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL1_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL1_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL1_TXFNUM_OFFSET            0x920
-#define GC_USB_DIEPCTL1_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL1_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL1_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL1_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL1_CNAK_OFFSET              0x920
-#define GC_USB_DIEPCTL1_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL1_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL1_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL1_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL1_SNAK_OFFSET              0x920
-#define GC_USB_DIEPCTL1_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL1_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL1_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL1_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL1_SETD0PID_OFFSET          0x920
-#define GC_USB_DIEPCTL1_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL1_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL1_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL1_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL1_SETD1PID_OFFSET          0x920
-#define GC_USB_DIEPCTL1_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL1_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL1_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL1_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL1_EPDIS_OFFSET             0x920
-#define GC_USB_DIEPCTL1_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL1_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL1_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL1_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL1_EPENA_OFFSET             0x920
-#define GC_USB_DIEPINT1_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT1_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT1_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT1_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT1_XFERCOMPL_OFFSET         0x928
-#define GC_USB_DIEPINT1_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT1_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT1_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT1_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT1_EPDISBLD_OFFSET          0x928
-#define GC_USB_DIEPINT1_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT1_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT1_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT1_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT1_AHBERR_OFFSET            0x928
-#define GC_USB_DIEPINT1_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT1_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT1_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT1_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT1_TIMEOUT_OFFSET           0x928
-#define GC_USB_DIEPINT1_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT1_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT1_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT1_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT1_INTKNTXFEMP_OFFSET       0x928
-#define GC_USB_DIEPINT1_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT1_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT1_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT1_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT1_INTKNEPMIS_OFFSET        0x928
-#define GC_USB_DIEPINT1_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT1_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT1_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT1_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT1_INEPNAKEFF_OFFSET        0x928
-#define GC_USB_DIEPINT1_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT1_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT1_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT1_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT1_TXFEMP_OFFSET            0x928
-#define GC_USB_DIEPINT1_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT1_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT1_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT1_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT1_TXFIFOUNDRN_OFFSET       0x928
-#define GC_USB_DIEPINT1_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT1_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT1_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT1_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT1_BNAINTR_OFFSET           0x928
-#define GC_USB_DIEPINT1_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT1_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT1_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT1_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT1_PKTDRPSTS_OFFSET         0x928
-#define GC_USB_DIEPINT1_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT1_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT1_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT1_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT1_BBLEERR_OFFSET           0x928
-#define GC_USB_DIEPINT1_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT1_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT1_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT1_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT1_NAKINTRPT_OFFSET         0x928
-#define GC_USB_DIEPINT1_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT1_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT1_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT1_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT1_NYETINTRPT_OFFSET        0x928
-#define GC_USB_DIEPTSIZ1_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ1_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ1_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ1_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ1_XFERSIZE_OFFSET         0x930
-#define GC_USB_DIEPTSIZ1_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ1_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ1_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ1_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ1_PKTCNT_OFFSET           0x930
-#define GC_USB_DIEPTSIZ1_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ1_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ1_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ1_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ1_MC_OFFSET               0x930
-#define GC_USB_DIEPDMA1_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA1_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA1_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA1_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA1_DMAADDR_OFFSET           0x934
-#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_OFFSET   0x938
-#define GC_USB_DIEPDMAB1_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB1_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB1_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB1_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB1_DMABUFFERADDR_OFFSET    0x93c
-#define GC_USB_DIEPCTL2_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL2_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL2_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL2_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL2_MPS_OFFSET               0x940
-#define GC_USB_DIEPCTL2_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL2_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL2_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL2_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL2_USBACTEP_OFFSET          0x940
-#define GC_USB_DIEPCTL2_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL2_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL2_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL2_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL2_DPID_OFFSET              0x940
-#define GC_USB_DIEPCTL2_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL2_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL2_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL2_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL2_NAKSTS_OFFSET            0x940
-#define GC_USB_DIEPCTL2_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL2_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL2_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL2_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL2_EPTYPE_OFFSET            0x940
-#define GC_USB_DIEPCTL2_STALL_LSB                0x15
-#define GC_USB_DIEPCTL2_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL2_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL2_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL2_STALL_OFFSET             0x940
-#define GC_USB_DIEPCTL2_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL2_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL2_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL2_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL2_TXFNUM_OFFSET            0x940
-#define GC_USB_DIEPCTL2_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL2_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL2_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL2_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL2_CNAK_OFFSET              0x940
-#define GC_USB_DIEPCTL2_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL2_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL2_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL2_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL2_SNAK_OFFSET              0x940
-#define GC_USB_DIEPCTL2_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL2_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL2_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL2_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL2_SETD0PID_OFFSET          0x940
-#define GC_USB_DIEPCTL2_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL2_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL2_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL2_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL2_SETD1PID_OFFSET          0x940
-#define GC_USB_DIEPCTL2_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL2_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL2_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL2_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL2_EPDIS_OFFSET             0x940
-#define GC_USB_DIEPCTL2_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL2_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL2_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL2_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL2_EPENA_OFFSET             0x940
-#define GC_USB_DIEPINT2_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT2_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT2_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT2_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT2_XFERCOMPL_OFFSET         0x948
-#define GC_USB_DIEPINT2_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT2_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT2_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT2_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT2_EPDISBLD_OFFSET          0x948
-#define GC_USB_DIEPINT2_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT2_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT2_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT2_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT2_AHBERR_OFFSET            0x948
-#define GC_USB_DIEPINT2_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT2_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT2_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT2_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT2_TIMEOUT_OFFSET           0x948
-#define GC_USB_DIEPINT2_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT2_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT2_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT2_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT2_INTKNTXFEMP_OFFSET       0x948
-#define GC_USB_DIEPINT2_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT2_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT2_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT2_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT2_INTKNEPMIS_OFFSET        0x948
-#define GC_USB_DIEPINT2_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT2_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT2_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT2_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT2_INEPNAKEFF_OFFSET        0x948
-#define GC_USB_DIEPINT2_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT2_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT2_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT2_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT2_TXFEMP_OFFSET            0x948
-#define GC_USB_DIEPINT2_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT2_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT2_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT2_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT2_TXFIFOUNDRN_OFFSET       0x948
-#define GC_USB_DIEPINT2_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT2_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT2_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT2_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT2_BNAINTR_OFFSET           0x948
-#define GC_USB_DIEPINT2_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT2_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT2_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT2_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT2_PKTDRPSTS_OFFSET         0x948
-#define GC_USB_DIEPINT2_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT2_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT2_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT2_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT2_BBLEERR_OFFSET           0x948
-#define GC_USB_DIEPINT2_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT2_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT2_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT2_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT2_NAKINTRPT_OFFSET         0x948
-#define GC_USB_DIEPINT2_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT2_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT2_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT2_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT2_NYETINTRPT_OFFSET        0x948
-#define GC_USB_DIEPTSIZ2_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ2_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ2_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ2_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ2_XFERSIZE_OFFSET         0x950
-#define GC_USB_DIEPTSIZ2_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ2_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ2_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ2_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ2_PKTCNT_OFFSET           0x950
-#define GC_USB_DIEPTSIZ2_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ2_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ2_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ2_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ2_MC_OFFSET               0x950
-#define GC_USB_DIEPDMA2_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA2_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA2_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA2_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA2_DMAADDR_OFFSET           0x954
-#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_OFFSET   0x958
-#define GC_USB_DIEPDMAB2_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB2_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB2_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB2_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB2_DMABUFFERADDR_OFFSET    0x95c
-#define GC_USB_DIEPCTL3_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL3_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL3_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL3_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL3_MPS_OFFSET               0x960
-#define GC_USB_DIEPCTL3_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL3_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL3_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL3_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL3_USBACTEP_OFFSET          0x960
-#define GC_USB_DIEPCTL3_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL3_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL3_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL3_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL3_DPID_OFFSET              0x960
-#define GC_USB_DIEPCTL3_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL3_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL3_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL3_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL3_NAKSTS_OFFSET            0x960
-#define GC_USB_DIEPCTL3_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL3_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL3_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL3_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL3_EPTYPE_OFFSET            0x960
-#define GC_USB_DIEPCTL3_STALL_LSB                0x15
-#define GC_USB_DIEPCTL3_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL3_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL3_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL3_STALL_OFFSET             0x960
-#define GC_USB_DIEPCTL3_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL3_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL3_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL3_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL3_TXFNUM_OFFSET            0x960
-#define GC_USB_DIEPCTL3_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL3_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL3_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL3_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL3_CNAK_OFFSET              0x960
-#define GC_USB_DIEPCTL3_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL3_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL3_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL3_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL3_SNAK_OFFSET              0x960
-#define GC_USB_DIEPCTL3_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL3_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL3_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL3_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL3_SETD0PID_OFFSET          0x960
-#define GC_USB_DIEPCTL3_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL3_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL3_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL3_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL3_SETD1PID_OFFSET          0x960
-#define GC_USB_DIEPCTL3_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL3_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL3_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL3_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL3_EPDIS_OFFSET             0x960
-#define GC_USB_DIEPCTL3_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL3_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL3_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL3_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL3_EPENA_OFFSET             0x960
-#define GC_USB_DIEPINT3_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT3_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT3_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT3_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT3_XFERCOMPL_OFFSET         0x968
-#define GC_USB_DIEPINT3_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT3_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT3_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT3_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT3_EPDISBLD_OFFSET          0x968
-#define GC_USB_DIEPINT3_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT3_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT3_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT3_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT3_AHBERR_OFFSET            0x968
-#define GC_USB_DIEPINT3_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT3_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT3_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT3_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT3_TIMEOUT_OFFSET           0x968
-#define GC_USB_DIEPINT3_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT3_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT3_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT3_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT3_INTKNTXFEMP_OFFSET       0x968
-#define GC_USB_DIEPINT3_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT3_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT3_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT3_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT3_INTKNEPMIS_OFFSET        0x968
-#define GC_USB_DIEPINT3_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT3_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT3_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT3_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT3_INEPNAKEFF_OFFSET        0x968
-#define GC_USB_DIEPINT3_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT3_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT3_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT3_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT3_TXFEMP_OFFSET            0x968
-#define GC_USB_DIEPINT3_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT3_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT3_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT3_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT3_TXFIFOUNDRN_OFFSET       0x968
-#define GC_USB_DIEPINT3_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT3_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT3_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT3_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT3_BNAINTR_OFFSET           0x968
-#define GC_USB_DIEPINT3_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT3_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT3_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT3_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT3_PKTDRPSTS_OFFSET         0x968
-#define GC_USB_DIEPINT3_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT3_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT3_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT3_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT3_BBLEERR_OFFSET           0x968
-#define GC_USB_DIEPINT3_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT3_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT3_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT3_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT3_NAKINTRPT_OFFSET         0x968
-#define GC_USB_DIEPINT3_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT3_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT3_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT3_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT3_NYETINTRPT_OFFSET        0x968
-#define GC_USB_DIEPTSIZ3_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ3_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ3_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ3_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ3_XFERSIZE_OFFSET         0x970
-#define GC_USB_DIEPTSIZ3_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ3_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ3_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ3_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ3_PKTCNT_OFFSET           0x970
-#define GC_USB_DIEPTSIZ3_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ3_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ3_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ3_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ3_MC_OFFSET               0x970
-#define GC_USB_DIEPDMA3_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA3_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA3_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA3_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA3_DMAADDR_OFFSET           0x974
-#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_OFFSET   0x978
-#define GC_USB_DIEPDMAB3_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB3_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB3_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB3_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB3_DMABUFFERADDR_OFFSET    0x97c
-#define GC_USB_DIEPCTL4_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL4_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL4_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL4_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL4_MPS_OFFSET               0x980
-#define GC_USB_DIEPCTL4_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL4_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL4_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL4_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL4_USBACTEP_OFFSET          0x980
-#define GC_USB_DIEPCTL4_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL4_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL4_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL4_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL4_DPID_OFFSET              0x980
-#define GC_USB_DIEPCTL4_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL4_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL4_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL4_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL4_NAKSTS_OFFSET            0x980
-#define GC_USB_DIEPCTL4_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL4_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL4_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL4_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL4_EPTYPE_OFFSET            0x980
-#define GC_USB_DIEPCTL4_STALL_LSB                0x15
-#define GC_USB_DIEPCTL4_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL4_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL4_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL4_STALL_OFFSET             0x980
-#define GC_USB_DIEPCTL4_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL4_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL4_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL4_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL4_TXFNUM_OFFSET            0x980
-#define GC_USB_DIEPCTL4_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL4_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL4_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL4_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL4_CNAK_OFFSET              0x980
-#define GC_USB_DIEPCTL4_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL4_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL4_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL4_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL4_SNAK_OFFSET              0x980
-#define GC_USB_DIEPCTL4_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL4_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL4_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL4_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL4_SETD0PID_OFFSET          0x980
-#define GC_USB_DIEPCTL4_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL4_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL4_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL4_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL4_SETD1PID_OFFSET          0x980
-#define GC_USB_DIEPCTL4_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL4_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL4_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL4_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL4_EPDIS_OFFSET             0x980
-#define GC_USB_DIEPCTL4_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL4_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL4_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL4_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL4_EPENA_OFFSET             0x980
-#define GC_USB_DIEPINT4_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT4_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT4_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT4_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT4_XFERCOMPL_OFFSET         0x988
-#define GC_USB_DIEPINT4_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT4_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT4_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT4_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT4_EPDISBLD_OFFSET          0x988
-#define GC_USB_DIEPINT4_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT4_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT4_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT4_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT4_AHBERR_OFFSET            0x988
-#define GC_USB_DIEPINT4_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT4_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT4_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT4_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT4_TIMEOUT_OFFSET           0x988
-#define GC_USB_DIEPINT4_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT4_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT4_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT4_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT4_INTKNTXFEMP_OFFSET       0x988
-#define GC_USB_DIEPINT4_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT4_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT4_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT4_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT4_INTKNEPMIS_OFFSET        0x988
-#define GC_USB_DIEPINT4_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT4_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT4_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT4_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT4_INEPNAKEFF_OFFSET        0x988
-#define GC_USB_DIEPINT4_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT4_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT4_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT4_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT4_TXFEMP_OFFSET            0x988
-#define GC_USB_DIEPINT4_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT4_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT4_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT4_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT4_TXFIFOUNDRN_OFFSET       0x988
-#define GC_USB_DIEPINT4_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT4_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT4_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT4_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT4_BNAINTR_OFFSET           0x988
-#define GC_USB_DIEPINT4_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT4_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT4_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT4_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT4_PKTDRPSTS_OFFSET         0x988
-#define GC_USB_DIEPINT4_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT4_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT4_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT4_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT4_BBLEERR_OFFSET           0x988
-#define GC_USB_DIEPINT4_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT4_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT4_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT4_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT4_NAKINTRPT_OFFSET         0x988
-#define GC_USB_DIEPINT4_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT4_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT4_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT4_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT4_NYETINTRPT_OFFSET        0x988
-#define GC_USB_DIEPTSIZ4_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ4_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ4_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ4_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ4_XFERSIZE_OFFSET         0x990
-#define GC_USB_DIEPTSIZ4_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ4_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ4_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ4_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ4_PKTCNT_OFFSET           0x990
-#define GC_USB_DIEPTSIZ4_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ4_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ4_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ4_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ4_MC_OFFSET               0x990
-#define GC_USB_DIEPDMA4_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA4_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA4_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA4_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA4_DMAADDR_OFFSET           0x994
-#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_OFFSET   0x998
-#define GC_USB_DIEPDMAB4_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB4_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB4_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB4_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB4_DMABUFFERADDR_OFFSET    0x99c
-#define GC_USB_DIEPCTL5_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL5_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL5_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL5_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL5_MPS_OFFSET               0x9a0
-#define GC_USB_DIEPCTL5_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL5_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL5_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL5_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL5_USBACTEP_OFFSET          0x9a0
-#define GC_USB_DIEPCTL5_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL5_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL5_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL5_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL5_DPID_OFFSET              0x9a0
-#define GC_USB_DIEPCTL5_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL5_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL5_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL5_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL5_NAKSTS_OFFSET            0x9a0
-#define GC_USB_DIEPCTL5_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL5_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL5_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL5_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL5_EPTYPE_OFFSET            0x9a0
-#define GC_USB_DIEPCTL5_STALL_LSB                0x15
-#define GC_USB_DIEPCTL5_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL5_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL5_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL5_STALL_OFFSET             0x9a0
-#define GC_USB_DIEPCTL5_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL5_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL5_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL5_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL5_TXFNUM_OFFSET            0x9a0
-#define GC_USB_DIEPCTL5_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL5_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL5_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL5_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL5_CNAK_OFFSET              0x9a0
-#define GC_USB_DIEPCTL5_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL5_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL5_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL5_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL5_SNAK_OFFSET              0x9a0
-#define GC_USB_DIEPCTL5_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL5_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL5_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL5_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL5_SETD0PID_OFFSET          0x9a0
-#define GC_USB_DIEPCTL5_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL5_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL5_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL5_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL5_SETD1PID_OFFSET          0x9a0
-#define GC_USB_DIEPCTL5_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL5_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL5_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL5_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL5_EPDIS_OFFSET             0x9a0
-#define GC_USB_DIEPCTL5_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL5_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL5_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL5_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL5_EPENA_OFFSET             0x9a0
-#define GC_USB_DIEPINT5_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT5_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT5_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT5_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT5_XFERCOMPL_OFFSET         0x9a8
-#define GC_USB_DIEPINT5_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT5_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT5_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT5_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT5_EPDISBLD_OFFSET          0x9a8
-#define GC_USB_DIEPINT5_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT5_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT5_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT5_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT5_AHBERR_OFFSET            0x9a8
-#define GC_USB_DIEPINT5_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT5_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT5_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT5_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT5_TIMEOUT_OFFSET           0x9a8
-#define GC_USB_DIEPINT5_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT5_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT5_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT5_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT5_INTKNTXFEMP_OFFSET       0x9a8
-#define GC_USB_DIEPINT5_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT5_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT5_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT5_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT5_INTKNEPMIS_OFFSET        0x9a8
-#define GC_USB_DIEPINT5_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT5_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT5_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT5_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT5_INEPNAKEFF_OFFSET        0x9a8
-#define GC_USB_DIEPINT5_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT5_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT5_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT5_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT5_TXFEMP_OFFSET            0x9a8
-#define GC_USB_DIEPINT5_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT5_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT5_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT5_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT5_TXFIFOUNDRN_OFFSET       0x9a8
-#define GC_USB_DIEPINT5_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT5_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT5_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT5_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT5_BNAINTR_OFFSET           0x9a8
-#define GC_USB_DIEPINT5_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT5_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT5_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT5_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT5_PKTDRPSTS_OFFSET         0x9a8
-#define GC_USB_DIEPINT5_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT5_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT5_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT5_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT5_BBLEERR_OFFSET           0x9a8
-#define GC_USB_DIEPINT5_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT5_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT5_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT5_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT5_NAKINTRPT_OFFSET         0x9a8
-#define GC_USB_DIEPINT5_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT5_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT5_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT5_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT5_NYETINTRPT_OFFSET        0x9a8
-#define GC_USB_DIEPTSIZ5_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ5_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ5_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ5_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ5_XFERSIZE_OFFSET         0x9b0
-#define GC_USB_DIEPTSIZ5_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ5_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ5_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ5_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ5_PKTCNT_OFFSET           0x9b0
-#define GC_USB_DIEPTSIZ5_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ5_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ5_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ5_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ5_MC_OFFSET               0x9b0
-#define GC_USB_DIEPDMA5_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA5_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA5_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA5_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA5_DMAADDR_OFFSET           0x9b4
-#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_OFFSET   0x9b8
-#define GC_USB_DIEPDMAB5_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB5_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB5_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB5_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB5_DMABUFFERADDR_OFFSET    0x9bc
-#define GC_USB_DIEPCTL6_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL6_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL6_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL6_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL6_MPS_OFFSET               0x9c0
-#define GC_USB_DIEPCTL6_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL6_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL6_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL6_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL6_USBACTEP_OFFSET          0x9c0
-#define GC_USB_DIEPCTL6_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL6_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL6_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL6_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL6_DPID_OFFSET              0x9c0
-#define GC_USB_DIEPCTL6_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL6_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL6_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL6_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL6_NAKSTS_OFFSET            0x9c0
-#define GC_USB_DIEPCTL6_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL6_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL6_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL6_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL6_EPTYPE_OFFSET            0x9c0
-#define GC_USB_DIEPCTL6_STALL_LSB                0x15
-#define GC_USB_DIEPCTL6_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL6_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL6_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL6_STALL_OFFSET             0x9c0
-#define GC_USB_DIEPCTL6_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL6_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL6_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL6_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL6_TXFNUM_OFFSET            0x9c0
-#define GC_USB_DIEPCTL6_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL6_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL6_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL6_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL6_CNAK_OFFSET              0x9c0
-#define GC_USB_DIEPCTL6_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL6_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL6_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL6_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL6_SNAK_OFFSET              0x9c0
-#define GC_USB_DIEPCTL6_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL6_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL6_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL6_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL6_SETD0PID_OFFSET          0x9c0
-#define GC_USB_DIEPCTL6_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL6_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL6_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL6_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL6_SETD1PID_OFFSET          0x9c0
-#define GC_USB_DIEPCTL6_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL6_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL6_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL6_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL6_EPDIS_OFFSET             0x9c0
-#define GC_USB_DIEPCTL6_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL6_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL6_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL6_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL6_EPENA_OFFSET             0x9c0
-#define GC_USB_DIEPINT6_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT6_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT6_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT6_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT6_XFERCOMPL_OFFSET         0x9c8
-#define GC_USB_DIEPINT6_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT6_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT6_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT6_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT6_EPDISBLD_OFFSET          0x9c8
-#define GC_USB_DIEPINT6_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT6_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT6_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT6_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT6_AHBERR_OFFSET            0x9c8
-#define GC_USB_DIEPINT6_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT6_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT6_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT6_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT6_TIMEOUT_OFFSET           0x9c8
-#define GC_USB_DIEPINT6_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT6_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT6_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT6_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT6_INTKNTXFEMP_OFFSET       0x9c8
-#define GC_USB_DIEPINT6_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT6_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT6_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT6_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT6_INTKNEPMIS_OFFSET        0x9c8
-#define GC_USB_DIEPINT6_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT6_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT6_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT6_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT6_INEPNAKEFF_OFFSET        0x9c8
-#define GC_USB_DIEPINT6_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT6_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT6_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT6_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT6_TXFEMP_OFFSET            0x9c8
-#define GC_USB_DIEPINT6_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT6_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT6_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT6_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT6_TXFIFOUNDRN_OFFSET       0x9c8
-#define GC_USB_DIEPINT6_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT6_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT6_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT6_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT6_BNAINTR_OFFSET           0x9c8
-#define GC_USB_DIEPINT6_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT6_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT6_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT6_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT6_PKTDRPSTS_OFFSET         0x9c8
-#define GC_USB_DIEPINT6_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT6_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT6_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT6_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT6_BBLEERR_OFFSET           0x9c8
-#define GC_USB_DIEPINT6_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT6_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT6_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT6_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT6_NAKINTRPT_OFFSET         0x9c8
-#define GC_USB_DIEPINT6_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT6_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT6_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT6_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT6_NYETINTRPT_OFFSET        0x9c8
-#define GC_USB_DIEPTSIZ6_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ6_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ6_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ6_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ6_XFERSIZE_OFFSET         0x9d0
-#define GC_USB_DIEPTSIZ6_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ6_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ6_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ6_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ6_PKTCNT_OFFSET           0x9d0
-#define GC_USB_DIEPTSIZ6_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ6_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ6_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ6_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ6_MC_OFFSET               0x9d0
-#define GC_USB_DIEPDMA6_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA6_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA6_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA6_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA6_DMAADDR_OFFSET           0x9d4
-#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_OFFSET   0x9d8
-#define GC_USB_DIEPDMAB6_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB6_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB6_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB6_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB6_DMABUFFERADDR_OFFSET    0x9dc
-#define GC_USB_DIEPCTL7_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL7_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL7_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL7_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL7_MPS_OFFSET               0x9e0
-#define GC_USB_DIEPCTL7_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL7_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL7_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL7_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL7_USBACTEP_OFFSET          0x9e0
-#define GC_USB_DIEPCTL7_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL7_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL7_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL7_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL7_DPID_OFFSET              0x9e0
-#define GC_USB_DIEPCTL7_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL7_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL7_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL7_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL7_NAKSTS_OFFSET            0x9e0
-#define GC_USB_DIEPCTL7_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL7_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL7_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL7_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL7_EPTYPE_OFFSET            0x9e0
-#define GC_USB_DIEPCTL7_STALL_LSB                0x15
-#define GC_USB_DIEPCTL7_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL7_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL7_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL7_STALL_OFFSET             0x9e0
-#define GC_USB_DIEPCTL7_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL7_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL7_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL7_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL7_TXFNUM_OFFSET            0x9e0
-#define GC_USB_DIEPCTL7_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL7_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL7_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL7_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL7_CNAK_OFFSET              0x9e0
-#define GC_USB_DIEPCTL7_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL7_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL7_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL7_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL7_SNAK_OFFSET              0x9e0
-#define GC_USB_DIEPCTL7_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL7_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL7_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL7_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL7_SETD0PID_OFFSET          0x9e0
-#define GC_USB_DIEPCTL7_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL7_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL7_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL7_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL7_SETD1PID_OFFSET          0x9e0
-#define GC_USB_DIEPCTL7_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL7_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL7_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL7_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL7_EPDIS_OFFSET             0x9e0
-#define GC_USB_DIEPCTL7_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL7_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL7_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL7_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL7_EPENA_OFFSET             0x9e0
-#define GC_USB_DIEPINT7_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT7_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT7_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT7_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT7_XFERCOMPL_OFFSET         0x9e8
-#define GC_USB_DIEPINT7_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT7_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT7_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT7_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT7_EPDISBLD_OFFSET          0x9e8
-#define GC_USB_DIEPINT7_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT7_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT7_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT7_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT7_AHBERR_OFFSET            0x9e8
-#define GC_USB_DIEPINT7_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT7_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT7_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT7_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT7_TIMEOUT_OFFSET           0x9e8
-#define GC_USB_DIEPINT7_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT7_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT7_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT7_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT7_INTKNTXFEMP_OFFSET       0x9e8
-#define GC_USB_DIEPINT7_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT7_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT7_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT7_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT7_INTKNEPMIS_OFFSET        0x9e8
-#define GC_USB_DIEPINT7_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT7_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT7_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT7_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT7_INEPNAKEFF_OFFSET        0x9e8
-#define GC_USB_DIEPINT7_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT7_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT7_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT7_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT7_TXFEMP_OFFSET            0x9e8
-#define GC_USB_DIEPINT7_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT7_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT7_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT7_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT7_TXFIFOUNDRN_OFFSET       0x9e8
-#define GC_USB_DIEPINT7_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT7_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT7_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT7_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT7_BNAINTR_OFFSET           0x9e8
-#define GC_USB_DIEPINT7_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT7_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT7_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT7_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT7_PKTDRPSTS_OFFSET         0x9e8
-#define GC_USB_DIEPINT7_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT7_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT7_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT7_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT7_BBLEERR_OFFSET           0x9e8
-#define GC_USB_DIEPINT7_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT7_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT7_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT7_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT7_NAKINTRPT_OFFSET         0x9e8
-#define GC_USB_DIEPINT7_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT7_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT7_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT7_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT7_NYETINTRPT_OFFSET        0x9e8
-#define GC_USB_DIEPTSIZ7_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ7_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ7_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ7_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ7_XFERSIZE_OFFSET         0x9f0
-#define GC_USB_DIEPTSIZ7_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ7_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ7_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ7_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ7_PKTCNT_OFFSET           0x9f0
-#define GC_USB_DIEPTSIZ7_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ7_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ7_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ7_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ7_MC_OFFSET               0x9f0
-#define GC_USB_DIEPDMA7_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA7_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA7_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA7_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA7_DMAADDR_OFFSET           0x9f4
-#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_OFFSET   0x9f8
-#define GC_USB_DIEPDMAB7_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB7_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB7_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB7_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB7_DMABUFFERADDR_OFFSET    0x9fc
-#define GC_USB_DIEPCTL8_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL8_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL8_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL8_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL8_MPS_OFFSET               0xa00
-#define GC_USB_DIEPCTL8_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL8_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL8_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL8_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL8_USBACTEP_OFFSET          0xa00
-#define GC_USB_DIEPCTL8_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL8_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL8_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL8_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL8_DPID_OFFSET              0xa00
-#define GC_USB_DIEPCTL8_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL8_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL8_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL8_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL8_NAKSTS_OFFSET            0xa00
-#define GC_USB_DIEPCTL8_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL8_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL8_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL8_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL8_EPTYPE_OFFSET            0xa00
-#define GC_USB_DIEPCTL8_STALL_LSB                0x15
-#define GC_USB_DIEPCTL8_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL8_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL8_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL8_STALL_OFFSET             0xa00
-#define GC_USB_DIEPCTL8_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL8_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL8_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL8_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL8_TXFNUM_OFFSET            0xa00
-#define GC_USB_DIEPCTL8_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL8_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL8_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL8_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL8_CNAK_OFFSET              0xa00
-#define GC_USB_DIEPCTL8_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL8_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL8_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL8_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL8_SNAK_OFFSET              0xa00
-#define GC_USB_DIEPCTL8_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL8_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL8_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL8_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL8_SETD0PID_OFFSET          0xa00
-#define GC_USB_DIEPCTL8_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL8_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL8_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL8_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL8_SETD1PID_OFFSET          0xa00
-#define GC_USB_DIEPCTL8_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL8_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL8_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL8_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL8_EPDIS_OFFSET             0xa00
-#define GC_USB_DIEPCTL8_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL8_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL8_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL8_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL8_EPENA_OFFSET             0xa00
-#define GC_USB_DIEPINT8_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT8_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT8_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT8_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT8_XFERCOMPL_OFFSET         0xa08
-#define GC_USB_DIEPINT8_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT8_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT8_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT8_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT8_EPDISBLD_OFFSET          0xa08
-#define GC_USB_DIEPINT8_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT8_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT8_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT8_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT8_AHBERR_OFFSET            0xa08
-#define GC_USB_DIEPINT8_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT8_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT8_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT8_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT8_TIMEOUT_OFFSET           0xa08
-#define GC_USB_DIEPINT8_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT8_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT8_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT8_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT8_INTKNTXFEMP_OFFSET       0xa08
-#define GC_USB_DIEPINT8_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT8_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT8_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT8_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT8_INTKNEPMIS_OFFSET        0xa08
-#define GC_USB_DIEPINT8_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT8_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT8_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT8_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT8_INEPNAKEFF_OFFSET        0xa08
-#define GC_USB_DIEPINT8_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT8_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT8_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT8_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT8_TXFEMP_OFFSET            0xa08
-#define GC_USB_DIEPINT8_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT8_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT8_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT8_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT8_TXFIFOUNDRN_OFFSET       0xa08
-#define GC_USB_DIEPINT8_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT8_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT8_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT8_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT8_BNAINTR_OFFSET           0xa08
-#define GC_USB_DIEPINT8_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT8_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT8_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT8_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT8_PKTDRPSTS_OFFSET         0xa08
-#define GC_USB_DIEPINT8_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT8_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT8_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT8_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT8_BBLEERR_OFFSET           0xa08
-#define GC_USB_DIEPINT8_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT8_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT8_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT8_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT8_NAKINTRPT_OFFSET         0xa08
-#define GC_USB_DIEPINT8_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT8_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT8_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT8_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT8_NYETINTRPT_OFFSET        0xa08
-#define GC_USB_DIEPTSIZ8_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ8_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ8_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ8_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ8_XFERSIZE_OFFSET         0xa10
-#define GC_USB_DIEPTSIZ8_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ8_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ8_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ8_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ8_PKTCNT_OFFSET           0xa10
-#define GC_USB_DIEPTSIZ8_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ8_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ8_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ8_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ8_MC_OFFSET               0xa10
-#define GC_USB_DIEPDMA8_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA8_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA8_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA8_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA8_DMAADDR_OFFSET           0xa14
-#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_OFFSET   0xa18
-#define GC_USB_DIEPDMAB8_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB8_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB8_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB8_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB8_DMABUFFERADDR_OFFSET    0xa1c
-#define GC_USB_DIEPCTL9_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL9_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL9_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL9_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL9_MPS_OFFSET               0xa20
-#define GC_USB_DIEPCTL9_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL9_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL9_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL9_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL9_USBACTEP_OFFSET          0xa20
-#define GC_USB_DIEPCTL9_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL9_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL9_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL9_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL9_DPID_OFFSET              0xa20
-#define GC_USB_DIEPCTL9_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL9_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL9_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL9_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL9_NAKSTS_OFFSET            0xa20
-#define GC_USB_DIEPCTL9_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL9_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL9_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL9_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL9_EPTYPE_OFFSET            0xa20
-#define GC_USB_DIEPCTL9_STALL_LSB                0x15
-#define GC_USB_DIEPCTL9_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL9_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL9_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL9_STALL_OFFSET             0xa20
-#define GC_USB_DIEPCTL9_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL9_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL9_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL9_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL9_TXFNUM_OFFSET            0xa20
-#define GC_USB_DIEPCTL9_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL9_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL9_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL9_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL9_CNAK_OFFSET              0xa20
-#define GC_USB_DIEPCTL9_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL9_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL9_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL9_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL9_SNAK_OFFSET              0xa20
-#define GC_USB_DIEPCTL9_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL9_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL9_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL9_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL9_SETD0PID_OFFSET          0xa20
-#define GC_USB_DIEPCTL9_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL9_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL9_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL9_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL9_SETD1PID_OFFSET          0xa20
-#define GC_USB_DIEPCTL9_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL9_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL9_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL9_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL9_EPDIS_OFFSET             0xa20
-#define GC_USB_DIEPCTL9_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL9_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL9_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL9_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL9_EPENA_OFFSET             0xa20
-#define GC_USB_DIEPINT9_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT9_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT9_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT9_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT9_XFERCOMPL_OFFSET         0xa28
-#define GC_USB_DIEPINT9_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT9_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT9_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT9_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT9_EPDISBLD_OFFSET          0xa28
-#define GC_USB_DIEPINT9_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT9_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT9_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT9_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT9_AHBERR_OFFSET            0xa28
-#define GC_USB_DIEPINT9_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT9_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT9_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT9_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT9_TIMEOUT_OFFSET           0xa28
-#define GC_USB_DIEPINT9_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT9_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT9_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT9_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT9_INTKNTXFEMP_OFFSET       0xa28
-#define GC_USB_DIEPINT9_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT9_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT9_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT9_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT9_INTKNEPMIS_OFFSET        0xa28
-#define GC_USB_DIEPINT9_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT9_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT9_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT9_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT9_INEPNAKEFF_OFFSET        0xa28
-#define GC_USB_DIEPINT9_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT9_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT9_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT9_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT9_TXFEMP_OFFSET            0xa28
-#define GC_USB_DIEPINT9_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT9_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT9_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT9_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT9_TXFIFOUNDRN_OFFSET       0xa28
-#define GC_USB_DIEPINT9_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT9_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT9_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT9_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT9_BNAINTR_OFFSET           0xa28
-#define GC_USB_DIEPINT9_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT9_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT9_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT9_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT9_PKTDRPSTS_OFFSET         0xa28
-#define GC_USB_DIEPINT9_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT9_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT9_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT9_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT9_BBLEERR_OFFSET           0xa28
-#define GC_USB_DIEPINT9_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT9_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT9_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT9_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT9_NAKINTRPT_OFFSET         0xa28
-#define GC_USB_DIEPINT9_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT9_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT9_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT9_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT9_NYETINTRPT_OFFSET        0xa28
-#define GC_USB_DIEPTSIZ9_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ9_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ9_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ9_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ9_XFERSIZE_OFFSET         0xa30
-#define GC_USB_DIEPTSIZ9_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ9_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ9_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ9_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ9_PKTCNT_OFFSET           0xa30
-#define GC_USB_DIEPTSIZ9_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ9_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ9_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ9_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ9_MC_OFFSET               0xa30
-#define GC_USB_DIEPDMA9_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA9_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA9_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA9_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA9_DMAADDR_OFFSET           0xa34
-#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_OFFSET   0xa38
-#define GC_USB_DIEPDMAB9_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB9_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB9_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB9_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB9_DMABUFFERADDR_OFFSET    0xa3c
-#define GC_USB_DIEPCTL10_MPS_LSB                 0x0
-#define GC_USB_DIEPCTL10_MPS_MASK                0x7ff
-#define GC_USB_DIEPCTL10_MPS_SIZE                0xb
-#define GC_USB_DIEPCTL10_MPS_DEFAULT             0x0
-#define GC_USB_DIEPCTL10_MPS_OFFSET              0xa40
-#define GC_USB_DIEPCTL10_USBACTEP_LSB            0xf
-#define GC_USB_DIEPCTL10_USBACTEP_MASK           0x8000
-#define GC_USB_DIEPCTL10_USBACTEP_SIZE           0x1
-#define GC_USB_DIEPCTL10_USBACTEP_DEFAULT        0x0
-#define GC_USB_DIEPCTL10_USBACTEP_OFFSET         0xa40
-#define GC_USB_DIEPCTL10_DPID_LSB                0x10
-#define GC_USB_DIEPCTL10_DPID_MASK               0x10000
-#define GC_USB_DIEPCTL10_DPID_SIZE               0x1
-#define GC_USB_DIEPCTL10_DPID_DEFAULT            0x0
-#define GC_USB_DIEPCTL10_DPID_OFFSET             0xa40
-#define GC_USB_DIEPCTL10_NAKSTS_LSB              0x11
-#define GC_USB_DIEPCTL10_NAKSTS_MASK             0x20000
-#define GC_USB_DIEPCTL10_NAKSTS_SIZE             0x1
-#define GC_USB_DIEPCTL10_NAKSTS_DEFAULT          0x0
-#define GC_USB_DIEPCTL10_NAKSTS_OFFSET           0xa40
-#define GC_USB_DIEPCTL10_EPTYPE_LSB              0x12
-#define GC_USB_DIEPCTL10_EPTYPE_MASK             0xc0000
-#define GC_USB_DIEPCTL10_EPTYPE_SIZE             0x2
-#define GC_USB_DIEPCTL10_EPTYPE_DEFAULT          0x0
-#define GC_USB_DIEPCTL10_EPTYPE_OFFSET           0xa40
-#define GC_USB_DIEPCTL10_STALL_LSB               0x15
-#define GC_USB_DIEPCTL10_STALL_MASK              0x200000
-#define GC_USB_DIEPCTL10_STALL_SIZE              0x1
-#define GC_USB_DIEPCTL10_STALL_DEFAULT           0x0
-#define GC_USB_DIEPCTL10_STALL_OFFSET            0xa40
-#define GC_USB_DIEPCTL10_TXFNUM_LSB              0x16
-#define GC_USB_DIEPCTL10_TXFNUM_MASK             0x3c00000
-#define GC_USB_DIEPCTL10_TXFNUM_SIZE             0x4
-#define GC_USB_DIEPCTL10_TXFNUM_DEFAULT          0x0
-#define GC_USB_DIEPCTL10_TXFNUM_OFFSET           0xa40
-#define GC_USB_DIEPCTL10_CNAK_LSB                0x1a
-#define GC_USB_DIEPCTL10_CNAK_MASK               0x4000000
-#define GC_USB_DIEPCTL10_CNAK_SIZE               0x1
-#define GC_USB_DIEPCTL10_CNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL10_CNAK_OFFSET             0xa40
-#define GC_USB_DIEPCTL10_SNAK_LSB                0x1b
-#define GC_USB_DIEPCTL10_SNAK_MASK               0x8000000
-#define GC_USB_DIEPCTL10_SNAK_SIZE               0x1
-#define GC_USB_DIEPCTL10_SNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL10_SNAK_OFFSET             0xa40
-#define GC_USB_DIEPCTL10_SETD0PID_LSB            0x1c
-#define GC_USB_DIEPCTL10_SETD0PID_MASK           0x10000000
-#define GC_USB_DIEPCTL10_SETD0PID_SIZE           0x1
-#define GC_USB_DIEPCTL10_SETD0PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL10_SETD0PID_OFFSET         0xa40
-#define GC_USB_DIEPCTL10_SETD1PID_LSB            0x1d
-#define GC_USB_DIEPCTL10_SETD1PID_MASK           0x20000000
-#define GC_USB_DIEPCTL10_SETD1PID_SIZE           0x1
-#define GC_USB_DIEPCTL10_SETD1PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL10_SETD1PID_OFFSET         0xa40
-#define GC_USB_DIEPCTL10_EPDIS_LSB               0x1e
-#define GC_USB_DIEPCTL10_EPDIS_MASK              0x40000000
-#define GC_USB_DIEPCTL10_EPDIS_SIZE              0x1
-#define GC_USB_DIEPCTL10_EPDIS_DEFAULT           0x0
-#define GC_USB_DIEPCTL10_EPDIS_OFFSET            0xa40
-#define GC_USB_DIEPCTL10_EPENA_LSB               0x1f
-#define GC_USB_DIEPCTL10_EPENA_MASK              0x80000000
-#define GC_USB_DIEPCTL10_EPENA_SIZE              0x1
-#define GC_USB_DIEPCTL10_EPENA_DEFAULT           0x0
-#define GC_USB_DIEPCTL10_EPENA_OFFSET            0xa40
-#define GC_USB_DIEPINT10_XFERCOMPL_LSB           0x0
-#define GC_USB_DIEPINT10_XFERCOMPL_MASK          0x1
-#define GC_USB_DIEPINT10_XFERCOMPL_SIZE          0x1
-#define GC_USB_DIEPINT10_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DIEPINT10_XFERCOMPL_OFFSET        0xa48
-#define GC_USB_DIEPINT10_EPDISBLD_LSB            0x1
-#define GC_USB_DIEPINT10_EPDISBLD_MASK           0x2
-#define GC_USB_DIEPINT10_EPDISBLD_SIZE           0x1
-#define GC_USB_DIEPINT10_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DIEPINT10_EPDISBLD_OFFSET         0xa48
-#define GC_USB_DIEPINT10_AHBERR_LSB              0x2
-#define GC_USB_DIEPINT10_AHBERR_MASK             0x4
-#define GC_USB_DIEPINT10_AHBERR_SIZE             0x1
-#define GC_USB_DIEPINT10_AHBERR_DEFAULT          0x0
-#define GC_USB_DIEPINT10_AHBERR_OFFSET           0xa48
-#define GC_USB_DIEPINT10_TIMEOUT_LSB             0x3
-#define GC_USB_DIEPINT10_TIMEOUT_MASK            0x8
-#define GC_USB_DIEPINT10_TIMEOUT_SIZE            0x1
-#define GC_USB_DIEPINT10_TIMEOUT_DEFAULT         0x0
-#define GC_USB_DIEPINT10_TIMEOUT_OFFSET          0xa48
-#define GC_USB_DIEPINT10_INTKNTXFEMP_LSB         0x4
-#define GC_USB_DIEPINT10_INTKNTXFEMP_MASK        0x10
-#define GC_USB_DIEPINT10_INTKNTXFEMP_SIZE        0x1
-#define GC_USB_DIEPINT10_INTKNTXFEMP_DEFAULT     0x0
-#define GC_USB_DIEPINT10_INTKNTXFEMP_OFFSET      0xa48
-#define GC_USB_DIEPINT10_INTKNEPMIS_LSB          0x5
-#define GC_USB_DIEPINT10_INTKNEPMIS_MASK         0x20
-#define GC_USB_DIEPINT10_INTKNEPMIS_SIZE         0x1
-#define GC_USB_DIEPINT10_INTKNEPMIS_DEFAULT      0x0
-#define GC_USB_DIEPINT10_INTKNEPMIS_OFFSET       0xa48
-#define GC_USB_DIEPINT10_INEPNAKEFF_LSB          0x6
-#define GC_USB_DIEPINT10_INEPNAKEFF_MASK         0x40
-#define GC_USB_DIEPINT10_INEPNAKEFF_SIZE         0x1
-#define GC_USB_DIEPINT10_INEPNAKEFF_DEFAULT      0x0
-#define GC_USB_DIEPINT10_INEPNAKEFF_OFFSET       0xa48
-#define GC_USB_DIEPINT10_TXFEMP_LSB              0x7
-#define GC_USB_DIEPINT10_TXFEMP_MASK             0x80
-#define GC_USB_DIEPINT10_TXFEMP_SIZE             0x1
-#define GC_USB_DIEPINT10_TXFEMP_DEFAULT          0x0
-#define GC_USB_DIEPINT10_TXFEMP_OFFSET           0xa48
-#define GC_USB_DIEPINT10_TXFIFOUNDRN_LSB         0x8
-#define GC_USB_DIEPINT10_TXFIFOUNDRN_MASK        0x100
-#define GC_USB_DIEPINT10_TXFIFOUNDRN_SIZE        0x1
-#define GC_USB_DIEPINT10_TXFIFOUNDRN_DEFAULT     0x0
-#define GC_USB_DIEPINT10_TXFIFOUNDRN_OFFSET      0xa48
-#define GC_USB_DIEPINT10_BNAINTR_LSB             0x9
-#define GC_USB_DIEPINT10_BNAINTR_MASK            0x200
-#define GC_USB_DIEPINT10_BNAINTR_SIZE            0x1
-#define GC_USB_DIEPINT10_BNAINTR_DEFAULT         0x0
-#define GC_USB_DIEPINT10_BNAINTR_OFFSET          0xa48
-#define GC_USB_DIEPINT10_PKTDRPSTS_LSB           0xb
-#define GC_USB_DIEPINT10_PKTDRPSTS_MASK          0x800
-#define GC_USB_DIEPINT10_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DIEPINT10_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DIEPINT10_PKTDRPSTS_OFFSET        0xa48
-#define GC_USB_DIEPINT10_BBLEERR_LSB             0xc
-#define GC_USB_DIEPINT10_BBLEERR_MASK            0x1000
-#define GC_USB_DIEPINT10_BBLEERR_SIZE            0x1
-#define GC_USB_DIEPINT10_BBLEERR_DEFAULT         0x0
-#define GC_USB_DIEPINT10_BBLEERR_OFFSET          0xa48
-#define GC_USB_DIEPINT10_NAKINTRPT_LSB           0xd
-#define GC_USB_DIEPINT10_NAKINTRPT_MASK          0x2000
-#define GC_USB_DIEPINT10_NAKINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT10_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT10_NAKINTRPT_OFFSET        0xa48
-#define GC_USB_DIEPINT10_NYETINTRPT_LSB          0xe
-#define GC_USB_DIEPINT10_NYETINTRPT_MASK         0x4000
-#define GC_USB_DIEPINT10_NYETINTRPT_SIZE         0x1
-#define GC_USB_DIEPINT10_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DIEPINT10_NYETINTRPT_OFFSET       0xa48
-#define GC_USB_DIEPTSIZ10_XFERSIZE_LSB           0x0
-#define GC_USB_DIEPTSIZ10_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DIEPTSIZ10_XFERSIZE_SIZE          0x13
-#define GC_USB_DIEPTSIZ10_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DIEPTSIZ10_XFERSIZE_OFFSET        0xa50
-#define GC_USB_DIEPTSIZ10_PKTCNT_LSB             0x13
-#define GC_USB_DIEPTSIZ10_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DIEPTSIZ10_PKTCNT_SIZE            0xa
-#define GC_USB_DIEPTSIZ10_PKTCNT_DEFAULT         0x0
-#define GC_USB_DIEPTSIZ10_PKTCNT_OFFSET          0xa50
-#define GC_USB_DIEPTSIZ10_MC_LSB                 0x1d
-#define GC_USB_DIEPTSIZ10_MC_MASK                0x60000000
-#define GC_USB_DIEPTSIZ10_MC_SIZE                0x2
-#define GC_USB_DIEPTSIZ10_MC_DEFAULT             0x0
-#define GC_USB_DIEPTSIZ10_MC_OFFSET              0xa50
-#define GC_USB_DIEPDMA10_DMAADDR_LSB             0x0
-#define GC_USB_DIEPDMA10_DMAADDR_MASK            0xffffffff
-#define GC_USB_DIEPDMA10_DMAADDR_SIZE            0x20
-#define GC_USB_DIEPDMA10_DMAADDR_DEFAULT         0x0
-#define GC_USB_DIEPDMA10_DMAADDR_OFFSET          0xa54
-#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_LSB     0x0
-#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_MASK    0xffff
-#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_SIZE    0x10
+#define GC_USB_GHWCFG4_PHYDATAWIDTH_LSB 0xe
+#define GC_USB_GHWCFG4_PHYDATAWIDTH_MASK 0xc000
+#define GC_USB_GHWCFG4_PHYDATAWIDTH_SIZE 0x2
+#define GC_USB_GHWCFG4_PHYDATAWIDTH_DEFAULT 0x0
+#define GC_USB_GHWCFG4_PHYDATAWIDTH_OFFSET 0x50
+#define GC_USB_GHWCFG4_NUMCTLEPS_LSB 0x10
+#define GC_USB_GHWCFG4_NUMCTLEPS_MASK 0xf0000
+#define GC_USB_GHWCFG4_NUMCTLEPS_SIZE 0x4
+#define GC_USB_GHWCFG4_NUMCTLEPS_DEFAULT 0x0
+#define GC_USB_GHWCFG4_NUMCTLEPS_OFFSET 0x50
+#define GC_USB_GHWCFG4_IDDGFLTR_LSB 0x14
+#define GC_USB_GHWCFG4_IDDGFLTR_MASK 0x100000
+#define GC_USB_GHWCFG4_IDDGFLTR_SIZE 0x1
+#define GC_USB_GHWCFG4_IDDGFLTR_DEFAULT 0x0
+#define GC_USB_GHWCFG4_IDDGFLTR_OFFSET 0x50
+#define GC_USB_GHWCFG4_VBUSVALIDFLTR_LSB 0x15
+#define GC_USB_GHWCFG4_VBUSVALIDFLTR_MASK 0x200000
+#define GC_USB_GHWCFG4_VBUSVALIDFLTR_SIZE 0x1
+#define GC_USB_GHWCFG4_VBUSVALIDFLTR_DEFAULT 0x0
+#define GC_USB_GHWCFG4_VBUSVALIDFLTR_OFFSET 0x50
+#define GC_USB_GHWCFG4_AVALIDFLTR_LSB 0x16
+#define GC_USB_GHWCFG4_AVALIDFLTR_MASK 0x400000
+#define GC_USB_GHWCFG4_AVALIDFLTR_SIZE 0x1
+#define GC_USB_GHWCFG4_AVALIDFLTR_DEFAULT 0x0
+#define GC_USB_GHWCFG4_AVALIDFLTR_OFFSET 0x50
+#define GC_USB_GHWCFG4_BVALIDFLTR_LSB 0x17
+#define GC_USB_GHWCFG4_BVALIDFLTR_MASK 0x800000
+#define GC_USB_GHWCFG4_BVALIDFLTR_SIZE 0x1
+#define GC_USB_GHWCFG4_BVALIDFLTR_DEFAULT 0x0
+#define GC_USB_GHWCFG4_BVALIDFLTR_OFFSET 0x50
+#define GC_USB_GHWCFG4_SESSENDFLTR_LSB 0x18
+#define GC_USB_GHWCFG4_SESSENDFLTR_MASK 0x1000000
+#define GC_USB_GHWCFG4_SESSENDFLTR_SIZE 0x1
+#define GC_USB_GHWCFG4_SESSENDFLTR_DEFAULT 0x0
+#define GC_USB_GHWCFG4_SESSENDFLTR_OFFSET 0x50
+#define GC_USB_GHWCFG4_DEDFIFOMODE_LSB 0x19
+#define GC_USB_GHWCFG4_DEDFIFOMODE_MASK 0x2000000
+#define GC_USB_GHWCFG4_DEDFIFOMODE_SIZE 0x1
+#define GC_USB_GHWCFG4_DEDFIFOMODE_DEFAULT 0x0
+#define GC_USB_GHWCFG4_DEDFIFOMODE_OFFSET 0x50
+#define GC_USB_GHWCFG4_INEPS_LSB 0x1a
+#define GC_USB_GHWCFG4_INEPS_MASK 0x3c000000
+#define GC_USB_GHWCFG4_INEPS_SIZE 0x4
+#define GC_USB_GHWCFG4_INEPS_DEFAULT 0x0
+#define GC_USB_GHWCFG4_INEPS_OFFSET 0x50
+#define GC_USB_GHWCFG4_DESCDMAENABLED_LSB 0x1e
+#define GC_USB_GHWCFG4_DESCDMAENABLED_MASK 0x40000000
+#define GC_USB_GHWCFG4_DESCDMAENABLED_SIZE 0x1
+#define GC_USB_GHWCFG4_DESCDMAENABLED_DEFAULT 0x0
+#define GC_USB_GHWCFG4_DESCDMAENABLED_OFFSET 0x50
+#define GC_USB_GHWCFG4_DESCDMA_LSB 0x1f
+#define GC_USB_GHWCFG4_DESCDMA_MASK 0x80000000
+#define GC_USB_GHWCFG4_DESCDMA_SIZE 0x1
+#define GC_USB_GHWCFG4_DESCDMA_DEFAULT 0x0
+#define GC_USB_GHWCFG4_DESCDMA_OFFSET 0x50
+#define GC_USB_GDFIFOCFG_GDFIFOCFG_LSB 0x0
+#define GC_USB_GDFIFOCFG_GDFIFOCFG_MASK 0xffff
+#define GC_USB_GDFIFOCFG_GDFIFOCFG_SIZE 0x10
+#define GC_USB_GDFIFOCFG_GDFIFOCFG_DEFAULT 0x0
+#define GC_USB_GDFIFOCFG_GDFIFOCFG_OFFSET 0x5c
+#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_LSB 0x10
+#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_MASK 0xffff0000
+#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_SIZE 0x10
+#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_DEFAULT 0x0
+#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_OFFSET 0x5c
+#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_LSB 0x0
+#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_MASK 0x7ff
+#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_SIZE 0xb
+#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_DEFAULT 0x0
+#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_OFFSET 0x104
+#define GC_USB_DIEPTXF1_RESERVED11_LSB 0xc
+#define GC_USB_DIEPTXF1_RESERVED11_MASK 0x1000
+#define GC_USB_DIEPTXF1_RESERVED11_SIZE 0x1
+#define GC_USB_DIEPTXF1_RESERVED11_DEFAULT 0x1
+#define GC_USB_DIEPTXF1_RESERVED11_OFFSET 0x104
+#define GC_USB_DIEPTXF1_INEPNTXFDEP_LSB 0x10
+#define GC_USB_DIEPTXF1_INEPNTXFDEP_MASK 0x3f0000
+#define GC_USB_DIEPTXF1_INEPNTXFDEP_SIZE 0x6
+#define GC_USB_DIEPTXF1_INEPNTXFDEP_DEFAULT 0x0
+#define GC_USB_DIEPTXF1_INEPNTXFDEP_OFFSET 0x104
+#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_LSB 0x0
+#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_MASK 0x7ff
+#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_SIZE 0xb
+#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_DEFAULT 0x0
+#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_OFFSET 0x108
+#define GC_USB_DIEPTXF2_INEPNTXFDEP_LSB 0x10
+#define GC_USB_DIEPTXF2_INEPNTXFDEP_MASK 0x3f0000
+#define GC_USB_DIEPTXF2_INEPNTXFDEP_SIZE 0x6
+#define GC_USB_DIEPTXF2_INEPNTXFDEP_DEFAULT 0x0
+#define GC_USB_DIEPTXF2_INEPNTXFDEP_OFFSET 0x108
+#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_LSB 0x0
+#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_MASK 0x7ff
+#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_SIZE 0xb
+#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_DEFAULT 0x0
+#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_OFFSET 0x10c
+#define GC_USB_DIEPTXF3_INEPNTXFDEP_LSB 0x10
+#define GC_USB_DIEPTXF3_INEPNTXFDEP_MASK 0x3f0000
+#define GC_USB_DIEPTXF3_INEPNTXFDEP_SIZE 0x6
+#define GC_USB_DIEPTXF3_INEPNTXFDEP_DEFAULT 0x0
+#define GC_USB_DIEPTXF3_INEPNTXFDEP_OFFSET 0x10c
+#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_LSB 0x0
+#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_MASK 0x7ff
+#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_SIZE 0xb
+#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_DEFAULT 0x0
+#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_OFFSET 0x110
+#define GC_USB_DIEPTXF4_INEPNTXFDEP_LSB 0x10
+#define GC_USB_DIEPTXF4_INEPNTXFDEP_MASK 0x3f0000
+#define GC_USB_DIEPTXF4_INEPNTXFDEP_SIZE 0x6
+#define GC_USB_DIEPTXF4_INEPNTXFDEP_DEFAULT 0x0
+#define GC_USB_DIEPTXF4_INEPNTXFDEP_OFFSET 0x110
+#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_LSB 0x0
+#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_MASK 0x7ff
+#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_SIZE 0xb
+#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_DEFAULT 0x0
+#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_OFFSET 0x114
+#define GC_USB_DIEPTXF5_INEPNTXFDEP_LSB 0x10
+#define GC_USB_DIEPTXF5_INEPNTXFDEP_MASK 0x3f0000
+#define GC_USB_DIEPTXF5_INEPNTXFDEP_SIZE 0x6
+#define GC_USB_DIEPTXF5_INEPNTXFDEP_DEFAULT 0x0
+#define GC_USB_DIEPTXF5_INEPNTXFDEP_OFFSET 0x114
+#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_LSB 0x0
+#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_MASK 0x7ff
+#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_SIZE 0xb
+#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_DEFAULT 0x0
+#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_OFFSET 0x118
+#define GC_USB_DIEPTXF6_INEPNTXFDEP_LSB 0x10
+#define GC_USB_DIEPTXF6_INEPNTXFDEP_MASK 0x3f0000
+#define GC_USB_DIEPTXF6_INEPNTXFDEP_SIZE 0x6
+#define GC_USB_DIEPTXF6_INEPNTXFDEP_DEFAULT 0x0
+#define GC_USB_DIEPTXF6_INEPNTXFDEP_OFFSET 0x118
+#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_LSB 0x0
+#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_MASK 0x7ff
+#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_SIZE 0xb
+#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_DEFAULT 0x0
+#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_OFFSET 0x11c
+#define GC_USB_DIEPTXF7_INEPNTXFDEP_LSB 0x10
+#define GC_USB_DIEPTXF7_INEPNTXFDEP_MASK 0x3f0000
+#define GC_USB_DIEPTXF7_INEPNTXFDEP_SIZE 0x6
+#define GC_USB_DIEPTXF7_INEPNTXFDEP_DEFAULT 0x0
+#define GC_USB_DIEPTXF7_INEPNTXFDEP_OFFSET 0x11c
+#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_LSB 0x0
+#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_MASK 0x7ff
+#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_SIZE 0xb
+#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_DEFAULT 0x0
+#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_OFFSET 0x120
+#define GC_USB_DIEPTXF8_INEPNTXFDEP_LSB 0x10
+#define GC_USB_DIEPTXF8_INEPNTXFDEP_MASK 0x3f0000
+#define GC_USB_DIEPTXF8_INEPNTXFDEP_SIZE 0x6
+#define GC_USB_DIEPTXF8_INEPNTXFDEP_DEFAULT 0x0
+#define GC_USB_DIEPTXF8_INEPNTXFDEP_OFFSET 0x120
+#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_LSB 0x0
+#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_MASK 0x7ff
+#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_SIZE 0xb
+#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_DEFAULT 0x0
+#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_OFFSET 0x124
+#define GC_USB_DIEPTXF9_INEPNTXFDEP_LSB 0x10
+#define GC_USB_DIEPTXF9_INEPNTXFDEP_MASK 0x3f0000
+#define GC_USB_DIEPTXF9_INEPNTXFDEP_SIZE 0x6
+#define GC_USB_DIEPTXF9_INEPNTXFDEP_DEFAULT 0x0
+#define GC_USB_DIEPTXF9_INEPNTXFDEP_OFFSET 0x124
+#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_LSB 0x0
+#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_MASK 0x7ff
+#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_SIZE 0xb
+#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_DEFAULT 0x0
+#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_OFFSET 0x128
+#define GC_USB_DIEPTXF10_INEPNTXFDEP_LSB 0x10
+#define GC_USB_DIEPTXF10_INEPNTXFDEP_MASK 0x3f0000
+#define GC_USB_DIEPTXF10_INEPNTXFDEP_SIZE 0x6
+#define GC_USB_DIEPTXF10_INEPNTXFDEP_DEFAULT 0x0
+#define GC_USB_DIEPTXF10_INEPNTXFDEP_OFFSET 0x128
+#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_LSB 0x0
+#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_MASK 0x7ff
+#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_SIZE 0xb
+#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_DEFAULT 0x0
+#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_OFFSET 0x12c
+#define GC_USB_DIEPTXF11_INEPNTXFDEP_LSB 0x10
+#define GC_USB_DIEPTXF11_INEPNTXFDEP_MASK 0x3f0000
+#define GC_USB_DIEPTXF11_INEPNTXFDEP_SIZE 0x6
+#define GC_USB_DIEPTXF11_INEPNTXFDEP_DEFAULT 0x0
+#define GC_USB_DIEPTXF11_INEPNTXFDEP_OFFSET 0x12c
+#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_LSB 0x0
+#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_MASK 0x7ff
+#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_SIZE 0xb
+#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_DEFAULT 0x0
+#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_OFFSET 0x130
+#define GC_USB_DIEPTXF12_INEPNTXFDEP_LSB 0x10
+#define GC_USB_DIEPTXF12_INEPNTXFDEP_MASK 0x3f0000
+#define GC_USB_DIEPTXF12_INEPNTXFDEP_SIZE 0x6
+#define GC_USB_DIEPTXF12_INEPNTXFDEP_DEFAULT 0x0
+#define GC_USB_DIEPTXF12_INEPNTXFDEP_OFFSET 0x130
+#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_LSB 0x0
+#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_MASK 0x7ff
+#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_SIZE 0xb
+#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_DEFAULT 0x0
+#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_OFFSET 0x134
+#define GC_USB_DIEPTXF13_INEPNTXFDEP_LSB 0x10
+#define GC_USB_DIEPTXF13_INEPNTXFDEP_MASK 0x3f0000
+#define GC_USB_DIEPTXF13_INEPNTXFDEP_SIZE 0x6
+#define GC_USB_DIEPTXF13_INEPNTXFDEP_DEFAULT 0x0
+#define GC_USB_DIEPTXF13_INEPNTXFDEP_OFFSET 0x134
+#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_LSB 0x0
+#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_MASK 0x7ff
+#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_SIZE 0xb
+#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_DEFAULT 0x0
+#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_OFFSET 0x138
+#define GC_USB_DIEPTXF14_INEPNTXFDEP_LSB 0x10
+#define GC_USB_DIEPTXF14_INEPNTXFDEP_MASK 0x3f0000
+#define GC_USB_DIEPTXF14_INEPNTXFDEP_SIZE 0x6
+#define GC_USB_DIEPTXF14_INEPNTXFDEP_DEFAULT 0x0
+#define GC_USB_DIEPTXF14_INEPNTXFDEP_OFFSET 0x138
+#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_LSB 0x0
+#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_MASK 0x7ff
+#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_SIZE 0xb
+#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_DEFAULT 0x0
+#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_OFFSET 0x13c
+#define GC_USB_DIEPTXF15_INEPNTXFDEP_LSB 0x10
+#define GC_USB_DIEPTXF15_INEPNTXFDEP_MASK 0x3f0000
+#define GC_USB_DIEPTXF15_INEPNTXFDEP_SIZE 0x6
+#define GC_USB_DIEPTXF15_INEPNTXFDEP_DEFAULT 0x0
+#define GC_USB_DIEPTXF15_INEPNTXFDEP_OFFSET 0x13c
+#define GC_USB_DCFG_DEVSPD_LSB 0x0
+#define GC_USB_DCFG_DEVSPD_MASK 0x3
+#define GC_USB_DCFG_DEVSPD_SIZE 0x2
+#define GC_USB_DCFG_DEVSPD_DEFAULT 0x0
+#define GC_USB_DCFG_DEVSPD_OFFSET 0x800
+#define GC_USB_DCFG_NZSTSOUTHSHK_LSB 0x2
+#define GC_USB_DCFG_NZSTSOUTHSHK_MASK 0x4
+#define GC_USB_DCFG_NZSTSOUTHSHK_SIZE 0x1
+#define GC_USB_DCFG_NZSTSOUTHSHK_DEFAULT 0x0
+#define GC_USB_DCFG_NZSTSOUTHSHK_OFFSET 0x800
+#define GC_USB_DCFG_ENA32KHZSUSP_LSB 0x3
+#define GC_USB_DCFG_ENA32KHZSUSP_MASK 0x8
+#define GC_USB_DCFG_ENA32KHZSUSP_SIZE 0x1
+#define GC_USB_DCFG_ENA32KHZSUSP_DEFAULT 0x0
+#define GC_USB_DCFG_ENA32KHZSUSP_OFFSET 0x800
+#define GC_USB_DCFG_DEVADDR_LSB 0x4
+#define GC_USB_DCFG_DEVADDR_MASK 0x7f0
+#define GC_USB_DCFG_DEVADDR_SIZE 0x7
+#define GC_USB_DCFG_DEVADDR_DEFAULT 0x0
+#define GC_USB_DCFG_DEVADDR_OFFSET 0x800
+#define GC_USB_DCFG_PERFRINT_LSB 0xb
+#define GC_USB_DCFG_PERFRINT_MASK 0x1800
+#define GC_USB_DCFG_PERFRINT_SIZE 0x2
+#define GC_USB_DCFG_PERFRINT_DEFAULT 0x0
+#define GC_USB_DCFG_PERFRINT_OFFSET 0x800
+#define GC_USB_DCFG_ENDEVOUTNAK_LSB 0xd
+#define GC_USB_DCFG_ENDEVOUTNAK_MASK 0x2000
+#define GC_USB_DCFG_ENDEVOUTNAK_SIZE 0x1
+#define GC_USB_DCFG_ENDEVOUTNAK_DEFAULT 0x0
+#define GC_USB_DCFG_ENDEVOUTNAK_OFFSET 0x800
+#define GC_USB_DCFG_XCVRDLY_LSB 0xe
+#define GC_USB_DCFG_XCVRDLY_MASK 0x4000
+#define GC_USB_DCFG_XCVRDLY_SIZE 0x1
+#define GC_USB_DCFG_XCVRDLY_DEFAULT 0x0
+#define GC_USB_DCFG_XCVRDLY_OFFSET 0x800
+#define GC_USB_DCFG_ERRATICINTMSK_LSB 0xf
+#define GC_USB_DCFG_ERRATICINTMSK_MASK 0x8000
+#define GC_USB_DCFG_ERRATICINTMSK_SIZE 0x1
+#define GC_USB_DCFG_ERRATICINTMSK_DEFAULT 0x0
+#define GC_USB_DCFG_ERRATICINTMSK_OFFSET 0x800
+#define GC_USB_DCFG_DESCDMA_LSB 0x17
+#define GC_USB_DCFG_DESCDMA_MASK 0x800000
+#define GC_USB_DCFG_DESCDMA_SIZE 0x1
+#define GC_USB_DCFG_DESCDMA_DEFAULT 0x0
+#define GC_USB_DCFG_DESCDMA_OFFSET 0x800
+#define GC_USB_DCFG_PERSCHINTVL_LSB 0x18
+#define GC_USB_DCFG_PERSCHINTVL_MASK 0x3000000
+#define GC_USB_DCFG_PERSCHINTVL_SIZE 0x2
+#define GC_USB_DCFG_PERSCHINTVL_DEFAULT 0x0
+#define GC_USB_DCFG_PERSCHINTVL_OFFSET 0x800
+#define GC_USB_DCFG_RESVALID_LSB 0x1a
+#define GC_USB_DCFG_RESVALID_MASK 0xfc000000
+#define GC_USB_DCFG_RESVALID_SIZE 0x6
+#define GC_USB_DCFG_RESVALID_DEFAULT 0x2
+#define GC_USB_DCFG_RESVALID_OFFSET 0x800
+#define GC_USB_DCTL_RMTWKUPSIG_LSB 0x0
+#define GC_USB_DCTL_RMTWKUPSIG_MASK 0x1
+#define GC_USB_DCTL_RMTWKUPSIG_SIZE 0x1
+#define GC_USB_DCTL_RMTWKUPSIG_DEFAULT 0x0
+#define GC_USB_DCTL_RMTWKUPSIG_OFFSET 0x804
+#define GC_USB_DCTL_SFTDISCON_LSB 0x1
+#define GC_USB_DCTL_SFTDISCON_MASK 0x2
+#define GC_USB_DCTL_SFTDISCON_SIZE 0x1
+#define GC_USB_DCTL_SFTDISCON_DEFAULT 0x0
+#define GC_USB_DCTL_SFTDISCON_OFFSET 0x804
+#define GC_USB_DCTL_GNPINNAKSTS_LSB 0x2
+#define GC_USB_DCTL_GNPINNAKSTS_MASK 0x4
+#define GC_USB_DCTL_GNPINNAKSTS_SIZE 0x1
+#define GC_USB_DCTL_GNPINNAKSTS_DEFAULT 0x0
+#define GC_USB_DCTL_GNPINNAKSTS_OFFSET 0x804
+#define GC_USB_DCTL_GOUTNAKSTS_LSB 0x3
+#define GC_USB_DCTL_GOUTNAKSTS_MASK 0x8
+#define GC_USB_DCTL_GOUTNAKSTS_SIZE 0x1
+#define GC_USB_DCTL_GOUTNAKSTS_DEFAULT 0x0
+#define GC_USB_DCTL_GOUTNAKSTS_OFFSET 0x804
+#define GC_USB_DCTL_TSTCTL_LSB 0x4
+#define GC_USB_DCTL_TSTCTL_MASK 0x70
+#define GC_USB_DCTL_TSTCTL_SIZE 0x3
+#define GC_USB_DCTL_TSTCTL_DEFAULT 0x0
+#define GC_USB_DCTL_TSTCTL_OFFSET 0x804
+#define GC_USB_DCTL_SGNPINNAK_LSB 0x7
+#define GC_USB_DCTL_SGNPINNAK_MASK 0x80
+#define GC_USB_DCTL_SGNPINNAK_SIZE 0x1
+#define GC_USB_DCTL_SGNPINNAK_DEFAULT 0x0
+#define GC_USB_DCTL_SGNPINNAK_OFFSET 0x804
+#define GC_USB_DCTL_CGNPINNAK_LSB 0x8
+#define GC_USB_DCTL_CGNPINNAK_MASK 0x100
+#define GC_USB_DCTL_CGNPINNAK_SIZE 0x1
+#define GC_USB_DCTL_CGNPINNAK_DEFAULT 0x0
+#define GC_USB_DCTL_CGNPINNAK_OFFSET 0x804
+#define GC_USB_DCTL_SGOUTNAK_LSB 0x9
+#define GC_USB_DCTL_SGOUTNAK_MASK 0x200
+#define GC_USB_DCTL_SGOUTNAK_SIZE 0x1
+#define GC_USB_DCTL_SGOUTNAK_DEFAULT 0x0
+#define GC_USB_DCTL_SGOUTNAK_OFFSET 0x804
+#define GC_USB_DCTL_CGOUTNAK_LSB 0xa
+#define GC_USB_DCTL_CGOUTNAK_MASK 0x400
+#define GC_USB_DCTL_CGOUTNAK_SIZE 0x1
+#define GC_USB_DCTL_CGOUTNAK_DEFAULT 0x0
+#define GC_USB_DCTL_CGOUTNAK_OFFSET 0x804
+#define GC_USB_DCTL_PWRONPRGDONE_LSB 0xb
+#define GC_USB_DCTL_PWRONPRGDONE_MASK 0x800
+#define GC_USB_DCTL_PWRONPRGDONE_SIZE 0x1
+#define GC_USB_DCTL_PWRONPRGDONE_DEFAULT 0x0
+#define GC_USB_DCTL_PWRONPRGDONE_OFFSET 0x804
+#define GC_USB_DCTL_GMC_LSB 0xd
+#define GC_USB_DCTL_GMC_MASK 0x6000
+#define GC_USB_DCTL_GMC_SIZE 0x2
+#define GC_USB_DCTL_GMC_DEFAULT 0x0
+#define GC_USB_DCTL_GMC_OFFSET 0x804
+#define GC_USB_DCTL_IGNRFRMNUM_LSB 0xf
+#define GC_USB_DCTL_IGNRFRMNUM_MASK 0x8000
+#define GC_USB_DCTL_IGNRFRMNUM_SIZE 0x1
+#define GC_USB_DCTL_IGNRFRMNUM_DEFAULT 0x0
+#define GC_USB_DCTL_IGNRFRMNUM_OFFSET 0x804
+#define GC_USB_DCTL_NAKONBBLE_LSB 0x10
+#define GC_USB_DCTL_NAKONBBLE_MASK 0x10000
+#define GC_USB_DCTL_NAKONBBLE_SIZE 0x1
+#define GC_USB_DCTL_NAKONBBLE_DEFAULT 0x0
+#define GC_USB_DCTL_NAKONBBLE_OFFSET 0x804
+#define GC_USB_DCTL_ENCONTONBNA_LSB 0x11
+#define GC_USB_DCTL_ENCONTONBNA_MASK 0x20000
+#define GC_USB_DCTL_ENCONTONBNA_SIZE 0x1
+#define GC_USB_DCTL_ENCONTONBNA_DEFAULT 0x0
+#define GC_USB_DCTL_ENCONTONBNA_OFFSET 0x804
+#define GC_USB_DSTS_SUSPSTS_LSB 0x0
+#define GC_USB_DSTS_SUSPSTS_MASK 0x1
+#define GC_USB_DSTS_SUSPSTS_SIZE 0x1
+#define GC_USB_DSTS_SUSPSTS_DEFAULT 0x0
+#define GC_USB_DSTS_SUSPSTS_OFFSET 0x808
+#define GC_USB_DSTS_ENUMSPD_LSB 0x1
+#define GC_USB_DSTS_ENUMSPD_MASK 0x6
+#define GC_USB_DSTS_ENUMSPD_SIZE 0x2
+#define GC_USB_DSTS_ENUMSPD_DEFAULT 0x0
+#define GC_USB_DSTS_ENUMSPD_OFFSET 0x808
+#define GC_USB_DSTS_ERRTICERR_LSB 0x3
+#define GC_USB_DSTS_ERRTICERR_MASK 0x8
+#define GC_USB_DSTS_ERRTICERR_SIZE 0x1
+#define GC_USB_DSTS_ERRTICERR_DEFAULT 0x0
+#define GC_USB_DSTS_ERRTICERR_OFFSET 0x808
+#define GC_USB_DSTS_SOFFN_LSB 0x8
+#define GC_USB_DSTS_SOFFN_MASK 0x3fff00
+#define GC_USB_DSTS_SOFFN_SIZE 0xe
+#define GC_USB_DSTS_SOFFN_DEFAULT 0x0
+#define GC_USB_DSTS_SOFFN_OFFSET 0x808
+#define GC_USB_DSTS_DEVLNSTS_LSB 0x16
+#define GC_USB_DSTS_DEVLNSTS_MASK 0xc00000
+#define GC_USB_DSTS_DEVLNSTS_SIZE 0x2
+#define GC_USB_DSTS_DEVLNSTS_DEFAULT 0x0
+#define GC_USB_DSTS_DEVLNSTS_OFFSET 0x808
+#define GC_USB_DIEPMSK_XFERCOMPLMSK_LSB 0x0
+#define GC_USB_DIEPMSK_XFERCOMPLMSK_MASK 0x1
+#define GC_USB_DIEPMSK_XFERCOMPLMSK_SIZE 0x1
+#define GC_USB_DIEPMSK_XFERCOMPLMSK_DEFAULT 0x0
+#define GC_USB_DIEPMSK_XFERCOMPLMSK_OFFSET 0x810
+#define GC_USB_DIEPMSK_EPDISBLDMSK_LSB 0x1
+#define GC_USB_DIEPMSK_EPDISBLDMSK_MASK 0x2
+#define GC_USB_DIEPMSK_EPDISBLDMSK_SIZE 0x1
+#define GC_USB_DIEPMSK_EPDISBLDMSK_DEFAULT 0x0
+#define GC_USB_DIEPMSK_EPDISBLDMSK_OFFSET 0x810
+#define GC_USB_DIEPMSK_AHBERRMSK_LSB 0x2
+#define GC_USB_DIEPMSK_AHBERRMSK_MASK 0x4
+#define GC_USB_DIEPMSK_AHBERRMSK_SIZE 0x1
+#define GC_USB_DIEPMSK_AHBERRMSK_DEFAULT 0x0
+#define GC_USB_DIEPMSK_AHBERRMSK_OFFSET 0x810
+#define GC_USB_DIEPMSK_TIMEOUTMSK_LSB 0x3
+#define GC_USB_DIEPMSK_TIMEOUTMSK_MASK 0x8
+#define GC_USB_DIEPMSK_TIMEOUTMSK_SIZE 0x1
+#define GC_USB_DIEPMSK_TIMEOUTMSK_DEFAULT 0x0
+#define GC_USB_DIEPMSK_TIMEOUTMSK_OFFSET 0x810
+#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_LSB 0x4
+#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_MASK 0x10
+#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_SIZE 0x1
+#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_DEFAULT 0x0
+#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_OFFSET 0x810
+#define GC_USB_DIEPMSK_INTKNEPMISMSK_LSB 0x5
+#define GC_USB_DIEPMSK_INTKNEPMISMSK_MASK 0x20
+#define GC_USB_DIEPMSK_INTKNEPMISMSK_SIZE 0x1
+#define GC_USB_DIEPMSK_INTKNEPMISMSK_DEFAULT 0x0
+#define GC_USB_DIEPMSK_INTKNEPMISMSK_OFFSET 0x810
+#define GC_USB_DIEPMSK_INEPNAKEFFMSK_LSB 0x6
+#define GC_USB_DIEPMSK_INEPNAKEFFMSK_MASK 0x40
+#define GC_USB_DIEPMSK_INEPNAKEFFMSK_SIZE 0x1
+#define GC_USB_DIEPMSK_INEPNAKEFFMSK_DEFAULT 0x0
+#define GC_USB_DIEPMSK_INEPNAKEFFMSK_OFFSET 0x810
+#define GC_USB_DIEPMSK_RESERVED7_LSB 0x7
+#define GC_USB_DIEPMSK_RESERVED7_MASK 0x80
+#define GC_USB_DIEPMSK_RESERVED7_SIZE 0x1
+#define GC_USB_DIEPMSK_RESERVED7_DEFAULT 0x1
+#define GC_USB_DIEPMSK_RESERVED7_OFFSET 0x810
+#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_LSB 0x8
+#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_MASK 0x100
+#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_SIZE 0x1
+#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_DEFAULT 0x0
+#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_OFFSET 0x810
+#define GC_USB_DIEPMSK_BNAININTRMSK_LSB 0x9
+#define GC_USB_DIEPMSK_BNAININTRMSK_MASK 0x200
+#define GC_USB_DIEPMSK_BNAININTRMSK_SIZE 0x1
+#define GC_USB_DIEPMSK_BNAININTRMSK_DEFAULT 0x0
+#define GC_USB_DIEPMSK_BNAININTRMSK_OFFSET 0x810
+#define GC_USB_DIEPMSK_NAKMSK_LSB 0xd
+#define GC_USB_DIEPMSK_NAKMSK_MASK 0x2000
+#define GC_USB_DIEPMSK_NAKMSK_SIZE 0x1
+#define GC_USB_DIEPMSK_NAKMSK_DEFAULT 0x0
+#define GC_USB_DIEPMSK_NAKMSK_OFFSET 0x810
+#define GC_USB_DOEPMSK_XFERCOMPLMSK_LSB 0x0
+#define GC_USB_DOEPMSK_XFERCOMPLMSK_MASK 0x1
+#define GC_USB_DOEPMSK_XFERCOMPLMSK_SIZE 0x1
+#define GC_USB_DOEPMSK_XFERCOMPLMSK_DEFAULT 0x0
+#define GC_USB_DOEPMSK_XFERCOMPLMSK_OFFSET 0x814
+#define GC_USB_DOEPMSK_EPDISBLDMSK_LSB 0x1
+#define GC_USB_DOEPMSK_EPDISBLDMSK_MASK 0x2
+#define GC_USB_DOEPMSK_EPDISBLDMSK_SIZE 0x1
+#define GC_USB_DOEPMSK_EPDISBLDMSK_DEFAULT 0x0
+#define GC_USB_DOEPMSK_EPDISBLDMSK_OFFSET 0x814
+#define GC_USB_DOEPMSK_AHBERRMSK_LSB 0x2
+#define GC_USB_DOEPMSK_AHBERRMSK_MASK 0x4
+#define GC_USB_DOEPMSK_AHBERRMSK_SIZE 0x1
+#define GC_USB_DOEPMSK_AHBERRMSK_DEFAULT 0x0
+#define GC_USB_DOEPMSK_AHBERRMSK_OFFSET 0x814
+#define GC_USB_DOEPMSK_SETUPMSK_LSB 0x3
+#define GC_USB_DOEPMSK_SETUPMSK_MASK 0x8
+#define GC_USB_DOEPMSK_SETUPMSK_SIZE 0x1
+#define GC_USB_DOEPMSK_SETUPMSK_DEFAULT 0x0
+#define GC_USB_DOEPMSK_SETUPMSK_OFFSET 0x814
+#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_LSB 0x4
+#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_MASK 0x10
+#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_SIZE 0x1
+#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_DEFAULT 0x0
+#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_OFFSET 0x814
+#define GC_USB_DOEPMSK_STSPHSERCVDMSK_LSB 0x5
+#define GC_USB_DOEPMSK_STSPHSERCVDMSK_MASK 0x20
+#define GC_USB_DOEPMSK_STSPHSERCVDMSK_SIZE 0x1
+#define GC_USB_DOEPMSK_STSPHSERCVDMSK_DEFAULT 0x0
+#define GC_USB_DOEPMSK_STSPHSERCVDMSK_OFFSET 0x814
+#define GC_USB_DOEPMSK_BACK2BACKSETUP_LSB 0x6
+#define GC_USB_DOEPMSK_BACK2BACKSETUP_MASK 0x40
+#define GC_USB_DOEPMSK_BACK2BACKSETUP_SIZE 0x1
+#define GC_USB_DOEPMSK_BACK2BACKSETUP_DEFAULT 0x0
+#define GC_USB_DOEPMSK_BACK2BACKSETUP_OFFSET 0x814
+#define GC_USB_DOEPMSK_OUTPKTERRMSK_LSB 0x8
+#define GC_USB_DOEPMSK_OUTPKTERRMSK_MASK 0x100
+#define GC_USB_DOEPMSK_OUTPKTERRMSK_SIZE 0x1
+#define GC_USB_DOEPMSK_OUTPKTERRMSK_DEFAULT 0x0
+#define GC_USB_DOEPMSK_OUTPKTERRMSK_OFFSET 0x814
+#define GC_USB_DOEPMSK_BNAOUTINTRMSK_LSB 0x9
+#define GC_USB_DOEPMSK_BNAOUTINTRMSK_MASK 0x200
+#define GC_USB_DOEPMSK_BNAOUTINTRMSK_SIZE 0x1
+#define GC_USB_DOEPMSK_BNAOUTINTRMSK_DEFAULT 0x0
+#define GC_USB_DOEPMSK_BNAOUTINTRMSK_OFFSET 0x814
+#define GC_USB_DOEPMSK_BBLEERRMSK_LSB 0xc
+#define GC_USB_DOEPMSK_BBLEERRMSK_MASK 0x1000
+#define GC_USB_DOEPMSK_BBLEERRMSK_SIZE 0x1
+#define GC_USB_DOEPMSK_BBLEERRMSK_DEFAULT 0x0
+#define GC_USB_DOEPMSK_BBLEERRMSK_OFFSET 0x814
+#define GC_USB_DOEPMSK_NAKMSK_LSB 0xd
+#define GC_USB_DOEPMSK_NAKMSK_MASK 0x2000
+#define GC_USB_DOEPMSK_NAKMSK_SIZE 0x1
+#define GC_USB_DOEPMSK_NAKMSK_DEFAULT 0x0
+#define GC_USB_DOEPMSK_NAKMSK_OFFSET 0x814
+#define GC_USB_DOEPMSK_NYETMSK_LSB 0xe
+#define GC_USB_DOEPMSK_NYETMSK_MASK 0x4000
+#define GC_USB_DOEPMSK_NYETMSK_SIZE 0x1
+#define GC_USB_DOEPMSK_NYETMSK_DEFAULT 0x0
+#define GC_USB_DOEPMSK_NYETMSK_OFFSET 0x814
+#define GC_USB_DAINT_INEPINT0_LSB 0x0
+#define GC_USB_DAINT_INEPINT0_MASK 0x1
+#define GC_USB_DAINT_INEPINT0_SIZE 0x1
+#define GC_USB_DAINT_INEPINT0_DEFAULT 0x0
+#define GC_USB_DAINT_INEPINT0_OFFSET 0x818
+#define GC_USB_DAINT_INEPINT1_LSB 0x1
+#define GC_USB_DAINT_INEPINT1_MASK 0x2
+#define GC_USB_DAINT_INEPINT1_SIZE 0x1
+#define GC_USB_DAINT_INEPINT1_DEFAULT 0x0
+#define GC_USB_DAINT_INEPINT1_OFFSET 0x818
+#define GC_USB_DAINT_INEPINT2_LSB 0x2
+#define GC_USB_DAINT_INEPINT2_MASK 0x4
+#define GC_USB_DAINT_INEPINT2_SIZE 0x1
+#define GC_USB_DAINT_INEPINT2_DEFAULT 0x0
+#define GC_USB_DAINT_INEPINT2_OFFSET 0x818
+#define GC_USB_DAINT_INEPINT3_LSB 0x3
+#define GC_USB_DAINT_INEPINT3_MASK 0x8
+#define GC_USB_DAINT_INEPINT3_SIZE 0x1
+#define GC_USB_DAINT_INEPINT3_DEFAULT 0x0
+#define GC_USB_DAINT_INEPINT3_OFFSET 0x818
+#define GC_USB_DAINT_INEPINT4_LSB 0x4
+#define GC_USB_DAINT_INEPINT4_MASK 0x10
+#define GC_USB_DAINT_INEPINT4_SIZE 0x1
+#define GC_USB_DAINT_INEPINT4_DEFAULT 0x0
+#define GC_USB_DAINT_INEPINT4_OFFSET 0x818
+#define GC_USB_DAINT_INEPINT5_LSB 0x5
+#define GC_USB_DAINT_INEPINT5_MASK 0x20
+#define GC_USB_DAINT_INEPINT5_SIZE 0x1
+#define GC_USB_DAINT_INEPINT5_DEFAULT 0x0
+#define GC_USB_DAINT_INEPINT5_OFFSET 0x818
+#define GC_USB_DAINT_INEPINT6_LSB 0x6
+#define GC_USB_DAINT_INEPINT6_MASK 0x40
+#define GC_USB_DAINT_INEPINT6_SIZE 0x1
+#define GC_USB_DAINT_INEPINT6_DEFAULT 0x0
+#define GC_USB_DAINT_INEPINT6_OFFSET 0x818
+#define GC_USB_DAINT_INEPINT7_LSB 0x7
+#define GC_USB_DAINT_INEPINT7_MASK 0x80
+#define GC_USB_DAINT_INEPINT7_SIZE 0x1
+#define GC_USB_DAINT_INEPINT7_DEFAULT 0x0
+#define GC_USB_DAINT_INEPINT7_OFFSET 0x818
+#define GC_USB_DAINT_INEPINT8_LSB 0x8
+#define GC_USB_DAINT_INEPINT8_MASK 0x100
+#define GC_USB_DAINT_INEPINT8_SIZE 0x1
+#define GC_USB_DAINT_INEPINT8_DEFAULT 0x0
+#define GC_USB_DAINT_INEPINT8_OFFSET 0x818
+#define GC_USB_DAINT_INEPINT9_LSB 0x9
+#define GC_USB_DAINT_INEPINT9_MASK 0x200
+#define GC_USB_DAINT_INEPINT9_SIZE 0x1
+#define GC_USB_DAINT_INEPINT9_DEFAULT 0x0
+#define GC_USB_DAINT_INEPINT9_OFFSET 0x818
+#define GC_USB_DAINT_INEPINT10_LSB 0xa
+#define GC_USB_DAINT_INEPINT10_MASK 0x400
+#define GC_USB_DAINT_INEPINT10_SIZE 0x1
+#define GC_USB_DAINT_INEPINT10_DEFAULT 0x0
+#define GC_USB_DAINT_INEPINT10_OFFSET 0x818
+#define GC_USB_DAINT_INEPINT11_LSB 0xb
+#define GC_USB_DAINT_INEPINT11_MASK 0x800
+#define GC_USB_DAINT_INEPINT11_SIZE 0x1
+#define GC_USB_DAINT_INEPINT11_DEFAULT 0x0
+#define GC_USB_DAINT_INEPINT11_OFFSET 0x818
+#define GC_USB_DAINT_INEPINT12_LSB 0xc
+#define GC_USB_DAINT_INEPINT12_MASK 0x1000
+#define GC_USB_DAINT_INEPINT12_SIZE 0x1
+#define GC_USB_DAINT_INEPINT12_DEFAULT 0x0
+#define GC_USB_DAINT_INEPINT12_OFFSET 0x818
+#define GC_USB_DAINT_INEPINT13_LSB 0xd
+#define GC_USB_DAINT_INEPINT13_MASK 0x2000
+#define GC_USB_DAINT_INEPINT13_SIZE 0x1
+#define GC_USB_DAINT_INEPINT13_DEFAULT 0x0
+#define GC_USB_DAINT_INEPINT13_OFFSET 0x818
+#define GC_USB_DAINT_INEPINT14_LSB 0xe
+#define GC_USB_DAINT_INEPINT14_MASK 0x4000
+#define GC_USB_DAINT_INEPINT14_SIZE 0x1
+#define GC_USB_DAINT_INEPINT14_DEFAULT 0x0
+#define GC_USB_DAINT_INEPINT14_OFFSET 0x818
+#define GC_USB_DAINT_INEPINT15_LSB 0xf
+#define GC_USB_DAINT_INEPINT15_MASK 0x8000
+#define GC_USB_DAINT_INEPINT15_SIZE 0x1
+#define GC_USB_DAINT_INEPINT15_DEFAULT 0x0
+#define GC_USB_DAINT_INEPINT15_OFFSET 0x818
+#define GC_USB_DAINT_OUTEPINT0_LSB 0x10
+#define GC_USB_DAINT_OUTEPINT0_MASK 0x10000
+#define GC_USB_DAINT_OUTEPINT0_SIZE 0x1
+#define GC_USB_DAINT_OUTEPINT0_DEFAULT 0x0
+#define GC_USB_DAINT_OUTEPINT0_OFFSET 0x818
+#define GC_USB_DAINT_OUTEPINT1_LSB 0x11
+#define GC_USB_DAINT_OUTEPINT1_MASK 0x20000
+#define GC_USB_DAINT_OUTEPINT1_SIZE 0x1
+#define GC_USB_DAINT_OUTEPINT1_DEFAULT 0x0
+#define GC_USB_DAINT_OUTEPINT1_OFFSET 0x818
+#define GC_USB_DAINT_OUTEPINT2_LSB 0x12
+#define GC_USB_DAINT_OUTEPINT2_MASK 0x40000
+#define GC_USB_DAINT_OUTEPINT2_SIZE 0x1
+#define GC_USB_DAINT_OUTEPINT2_DEFAULT 0x0
+#define GC_USB_DAINT_OUTEPINT2_OFFSET 0x818
+#define GC_USB_DAINT_OUTEPINT3_LSB 0x13
+#define GC_USB_DAINT_OUTEPINT3_MASK 0x80000
+#define GC_USB_DAINT_OUTEPINT3_SIZE 0x1
+#define GC_USB_DAINT_OUTEPINT3_DEFAULT 0x0
+#define GC_USB_DAINT_OUTEPINT3_OFFSET 0x818
+#define GC_USB_DAINT_OUTEPINT4_LSB 0x14
+#define GC_USB_DAINT_OUTEPINT4_MASK 0x100000
+#define GC_USB_DAINT_OUTEPINT4_SIZE 0x1
+#define GC_USB_DAINT_OUTEPINT4_DEFAULT 0x0
+#define GC_USB_DAINT_OUTEPINT4_OFFSET 0x818
+#define GC_USB_DAINT_OUTEPINT5_LSB 0x15
+#define GC_USB_DAINT_OUTEPINT5_MASK 0x200000
+#define GC_USB_DAINT_OUTEPINT5_SIZE 0x1
+#define GC_USB_DAINT_OUTEPINT5_DEFAULT 0x0
+#define GC_USB_DAINT_OUTEPINT5_OFFSET 0x818
+#define GC_USB_DAINT_OUTEPINT6_LSB 0x16
+#define GC_USB_DAINT_OUTEPINT6_MASK 0x400000
+#define GC_USB_DAINT_OUTEPINT6_SIZE 0x1
+#define GC_USB_DAINT_OUTEPINT6_DEFAULT 0x0
+#define GC_USB_DAINT_OUTEPINT6_OFFSET 0x818
+#define GC_USB_DAINT_OUTEPINT7_LSB 0x17
+#define GC_USB_DAINT_OUTEPINT7_MASK 0x800000
+#define GC_USB_DAINT_OUTEPINT7_SIZE 0x1
+#define GC_USB_DAINT_OUTEPINT7_DEFAULT 0x0
+#define GC_USB_DAINT_OUTEPINT7_OFFSET 0x818
+#define GC_USB_DAINT_OUTEPINT8_LSB 0x18
+#define GC_USB_DAINT_OUTEPINT8_MASK 0x1000000
+#define GC_USB_DAINT_OUTEPINT8_SIZE 0x1
+#define GC_USB_DAINT_OUTEPINT8_DEFAULT 0x0
+#define GC_USB_DAINT_OUTEPINT8_OFFSET 0x818
+#define GC_USB_DAINT_OUTEPINT9_LSB 0x19
+#define GC_USB_DAINT_OUTEPINT9_MASK 0x2000000
+#define GC_USB_DAINT_OUTEPINT9_SIZE 0x1
+#define GC_USB_DAINT_OUTEPINT9_DEFAULT 0x0
+#define GC_USB_DAINT_OUTEPINT9_OFFSET 0x818
+#define GC_USB_DAINT_OUTEPINT10_LSB 0x1a
+#define GC_USB_DAINT_OUTEPINT10_MASK 0x4000000
+#define GC_USB_DAINT_OUTEPINT10_SIZE 0x1
+#define GC_USB_DAINT_OUTEPINT10_DEFAULT 0x0
+#define GC_USB_DAINT_OUTEPINT10_OFFSET 0x818
+#define GC_USB_DAINT_OUTEPINT11_LSB 0x1b
+#define GC_USB_DAINT_OUTEPINT11_MASK 0x8000000
+#define GC_USB_DAINT_OUTEPINT11_SIZE 0x1
+#define GC_USB_DAINT_OUTEPINT11_DEFAULT 0x0
+#define GC_USB_DAINT_OUTEPINT11_OFFSET 0x818
+#define GC_USB_DAINT_OUTEPINT12_LSB 0x1c
+#define GC_USB_DAINT_OUTEPINT12_MASK 0x10000000
+#define GC_USB_DAINT_OUTEPINT12_SIZE 0x1
+#define GC_USB_DAINT_OUTEPINT12_DEFAULT 0x0
+#define GC_USB_DAINT_OUTEPINT12_OFFSET 0x818
+#define GC_USB_DAINT_OUTEPINT13_LSB 0x1d
+#define GC_USB_DAINT_OUTEPINT13_MASK 0x20000000
+#define GC_USB_DAINT_OUTEPINT13_SIZE 0x1
+#define GC_USB_DAINT_OUTEPINT13_DEFAULT 0x0
+#define GC_USB_DAINT_OUTEPINT13_OFFSET 0x818
+#define GC_USB_DAINT_OUTEPINT14_LSB 0x1e
+#define GC_USB_DAINT_OUTEPINT14_MASK 0x40000000
+#define GC_USB_DAINT_OUTEPINT14_SIZE 0x1
+#define GC_USB_DAINT_OUTEPINT14_DEFAULT 0x0
+#define GC_USB_DAINT_OUTEPINT14_OFFSET 0x818
+#define GC_USB_DAINT_OUTEPINT15_LSB 0x1f
+#define GC_USB_DAINT_OUTEPINT15_MASK 0x80000000
+#define GC_USB_DAINT_OUTEPINT15_SIZE 0x1
+#define GC_USB_DAINT_OUTEPINT15_DEFAULT 0x0
+#define GC_USB_DAINT_OUTEPINT15_OFFSET 0x818
+#define GC_USB_DAINTMSK_INEPMSK0_LSB 0x0
+#define GC_USB_DAINTMSK_INEPMSK0_MASK 0x1
+#define GC_USB_DAINTMSK_INEPMSK0_SIZE 0x1
+#define GC_USB_DAINTMSK_INEPMSK0_DEFAULT 0x0
+#define GC_USB_DAINTMSK_INEPMSK0_OFFSET 0x81c
+#define GC_USB_DAINTMSK_INEPMSK1_LSB 0x1
+#define GC_USB_DAINTMSK_INEPMSK1_MASK 0x2
+#define GC_USB_DAINTMSK_INEPMSK1_SIZE 0x1
+#define GC_USB_DAINTMSK_INEPMSK1_DEFAULT 0x0
+#define GC_USB_DAINTMSK_INEPMSK1_OFFSET 0x81c
+#define GC_USB_DAINTMSK_INEPMSK2_LSB 0x2
+#define GC_USB_DAINTMSK_INEPMSK2_MASK 0x4
+#define GC_USB_DAINTMSK_INEPMSK2_SIZE 0x1
+#define GC_USB_DAINTMSK_INEPMSK2_DEFAULT 0x0
+#define GC_USB_DAINTMSK_INEPMSK2_OFFSET 0x81c
+#define GC_USB_DAINTMSK_INEPMSK3_LSB 0x3
+#define GC_USB_DAINTMSK_INEPMSK3_MASK 0x8
+#define GC_USB_DAINTMSK_INEPMSK3_SIZE 0x1
+#define GC_USB_DAINTMSK_INEPMSK3_DEFAULT 0x0
+#define GC_USB_DAINTMSK_INEPMSK3_OFFSET 0x81c
+#define GC_USB_DAINTMSK_INEPMSK4_LSB 0x4
+#define GC_USB_DAINTMSK_INEPMSK4_MASK 0x10
+#define GC_USB_DAINTMSK_INEPMSK4_SIZE 0x1
+#define GC_USB_DAINTMSK_INEPMSK4_DEFAULT 0x0
+#define GC_USB_DAINTMSK_INEPMSK4_OFFSET 0x81c
+#define GC_USB_DAINTMSK_INEPMSK5_LSB 0x5
+#define GC_USB_DAINTMSK_INEPMSK5_MASK 0x20
+#define GC_USB_DAINTMSK_INEPMSK5_SIZE 0x1
+#define GC_USB_DAINTMSK_INEPMSK5_DEFAULT 0x0
+#define GC_USB_DAINTMSK_INEPMSK5_OFFSET 0x81c
+#define GC_USB_DAINTMSK_INEPMSK6_LSB 0x6
+#define GC_USB_DAINTMSK_INEPMSK6_MASK 0x40
+#define GC_USB_DAINTMSK_INEPMSK6_SIZE 0x1
+#define GC_USB_DAINTMSK_INEPMSK6_DEFAULT 0x0
+#define GC_USB_DAINTMSK_INEPMSK6_OFFSET 0x81c
+#define GC_USB_DAINTMSK_INEPMSK7_LSB 0x7
+#define GC_USB_DAINTMSK_INEPMSK7_MASK 0x80
+#define GC_USB_DAINTMSK_INEPMSK7_SIZE 0x1
+#define GC_USB_DAINTMSK_INEPMSK7_DEFAULT 0x0
+#define GC_USB_DAINTMSK_INEPMSK7_OFFSET 0x81c
+#define GC_USB_DAINTMSK_INEPMSK8_LSB 0x8
+#define GC_USB_DAINTMSK_INEPMSK8_MASK 0x100
+#define GC_USB_DAINTMSK_INEPMSK8_SIZE 0x1
+#define GC_USB_DAINTMSK_INEPMSK8_DEFAULT 0x0
+#define GC_USB_DAINTMSK_INEPMSK8_OFFSET 0x81c
+#define GC_USB_DAINTMSK_INEPMSK9_LSB 0x9
+#define GC_USB_DAINTMSK_INEPMSK9_MASK 0x200
+#define GC_USB_DAINTMSK_INEPMSK9_SIZE 0x1
+#define GC_USB_DAINTMSK_INEPMSK9_DEFAULT 0x0
+#define GC_USB_DAINTMSK_INEPMSK9_OFFSET 0x81c
+#define GC_USB_DAINTMSK_INEPMSK10_LSB 0xa
+#define GC_USB_DAINTMSK_INEPMSK10_MASK 0x400
+#define GC_USB_DAINTMSK_INEPMSK10_SIZE 0x1
+#define GC_USB_DAINTMSK_INEPMSK10_DEFAULT 0x0
+#define GC_USB_DAINTMSK_INEPMSK10_OFFSET 0x81c
+#define GC_USB_DAINTMSK_INEPMSK11_LSB 0xb
+#define GC_USB_DAINTMSK_INEPMSK11_MASK 0x800
+#define GC_USB_DAINTMSK_INEPMSK11_SIZE 0x1
+#define GC_USB_DAINTMSK_INEPMSK11_DEFAULT 0x0
+#define GC_USB_DAINTMSK_INEPMSK11_OFFSET 0x81c
+#define GC_USB_DAINTMSK_INEPMSK12_LSB 0xc
+#define GC_USB_DAINTMSK_INEPMSK12_MASK 0x1000
+#define GC_USB_DAINTMSK_INEPMSK12_SIZE 0x1
+#define GC_USB_DAINTMSK_INEPMSK12_DEFAULT 0x0
+#define GC_USB_DAINTMSK_INEPMSK12_OFFSET 0x81c
+#define GC_USB_DAINTMSK_INEPMSK13_LSB 0xd
+#define GC_USB_DAINTMSK_INEPMSK13_MASK 0x2000
+#define GC_USB_DAINTMSK_INEPMSK13_SIZE 0x1
+#define GC_USB_DAINTMSK_INEPMSK13_DEFAULT 0x0
+#define GC_USB_DAINTMSK_INEPMSK13_OFFSET 0x81c
+#define GC_USB_DAINTMSK_INEPMSK14_LSB 0xe
+#define GC_USB_DAINTMSK_INEPMSK14_MASK 0x4000
+#define GC_USB_DAINTMSK_INEPMSK14_SIZE 0x1
+#define GC_USB_DAINTMSK_INEPMSK14_DEFAULT 0x0
+#define GC_USB_DAINTMSK_INEPMSK14_OFFSET 0x81c
+#define GC_USB_DAINTMSK_INEPMSK15_LSB 0xf
+#define GC_USB_DAINTMSK_INEPMSK15_MASK 0x8000
+#define GC_USB_DAINTMSK_INEPMSK15_SIZE 0x1
+#define GC_USB_DAINTMSK_INEPMSK15_DEFAULT 0x0
+#define GC_USB_DAINTMSK_INEPMSK15_OFFSET 0x81c
+#define GC_USB_DAINTMSK_OUTEPMSK0_LSB 0x10
+#define GC_USB_DAINTMSK_OUTEPMSK0_MASK 0x10000
+#define GC_USB_DAINTMSK_OUTEPMSK0_SIZE 0x1
+#define GC_USB_DAINTMSK_OUTEPMSK0_DEFAULT 0x0
+#define GC_USB_DAINTMSK_OUTEPMSK0_OFFSET 0x81c
+#define GC_USB_DAINTMSK_OUTEPMSK1_LSB 0x11
+#define GC_USB_DAINTMSK_OUTEPMSK1_MASK 0x20000
+#define GC_USB_DAINTMSK_OUTEPMSK1_SIZE 0x1
+#define GC_USB_DAINTMSK_OUTEPMSK1_DEFAULT 0x0
+#define GC_USB_DAINTMSK_OUTEPMSK1_OFFSET 0x81c
+#define GC_USB_DAINTMSK_OUTEPMSK2_LSB 0x12
+#define GC_USB_DAINTMSK_OUTEPMSK2_MASK 0x40000
+#define GC_USB_DAINTMSK_OUTEPMSK2_SIZE 0x1
+#define GC_USB_DAINTMSK_OUTEPMSK2_DEFAULT 0x0
+#define GC_USB_DAINTMSK_OUTEPMSK2_OFFSET 0x81c
+#define GC_USB_DAINTMSK_OUTEPMSK3_LSB 0x13
+#define GC_USB_DAINTMSK_OUTEPMSK3_MASK 0x80000
+#define GC_USB_DAINTMSK_OUTEPMSK3_SIZE 0x1
+#define GC_USB_DAINTMSK_OUTEPMSK3_DEFAULT 0x0
+#define GC_USB_DAINTMSK_OUTEPMSK3_OFFSET 0x81c
+#define GC_USB_DAINTMSK_OUTEPMSK4_LSB 0x14
+#define GC_USB_DAINTMSK_OUTEPMSK4_MASK 0x100000
+#define GC_USB_DAINTMSK_OUTEPMSK4_SIZE 0x1
+#define GC_USB_DAINTMSK_OUTEPMSK4_DEFAULT 0x0
+#define GC_USB_DAINTMSK_OUTEPMSK4_OFFSET 0x81c
+#define GC_USB_DAINTMSK_OUTEPMSK5_LSB 0x15
+#define GC_USB_DAINTMSK_OUTEPMSK5_MASK 0x200000
+#define GC_USB_DAINTMSK_OUTEPMSK5_SIZE 0x1
+#define GC_USB_DAINTMSK_OUTEPMSK5_DEFAULT 0x0
+#define GC_USB_DAINTMSK_OUTEPMSK5_OFFSET 0x81c
+#define GC_USB_DAINTMSK_OUTEPMSK6_LSB 0x16
+#define GC_USB_DAINTMSK_OUTEPMSK6_MASK 0x400000
+#define GC_USB_DAINTMSK_OUTEPMSK6_SIZE 0x1
+#define GC_USB_DAINTMSK_OUTEPMSK6_DEFAULT 0x0
+#define GC_USB_DAINTMSK_OUTEPMSK6_OFFSET 0x81c
+#define GC_USB_DAINTMSK_OUTEPMSK7_LSB 0x17
+#define GC_USB_DAINTMSK_OUTEPMSK7_MASK 0x800000
+#define GC_USB_DAINTMSK_OUTEPMSK7_SIZE 0x1
+#define GC_USB_DAINTMSK_OUTEPMSK7_DEFAULT 0x0
+#define GC_USB_DAINTMSK_OUTEPMSK7_OFFSET 0x81c
+#define GC_USB_DAINTMSK_OUTEPMSK8_LSB 0x18
+#define GC_USB_DAINTMSK_OUTEPMSK8_MASK 0x1000000
+#define GC_USB_DAINTMSK_OUTEPMSK8_SIZE 0x1
+#define GC_USB_DAINTMSK_OUTEPMSK8_DEFAULT 0x0
+#define GC_USB_DAINTMSK_OUTEPMSK8_OFFSET 0x81c
+#define GC_USB_DAINTMSK_OUTEPMSK9_LSB 0x19
+#define GC_USB_DAINTMSK_OUTEPMSK9_MASK 0x2000000
+#define GC_USB_DAINTMSK_OUTEPMSK9_SIZE 0x1
+#define GC_USB_DAINTMSK_OUTEPMSK9_DEFAULT 0x0
+#define GC_USB_DAINTMSK_OUTEPMSK9_OFFSET 0x81c
+#define GC_USB_DAINTMSK_OUTEPMSK10_LSB 0x1a
+#define GC_USB_DAINTMSK_OUTEPMSK10_MASK 0x4000000
+#define GC_USB_DAINTMSK_OUTEPMSK10_SIZE 0x1
+#define GC_USB_DAINTMSK_OUTEPMSK10_DEFAULT 0x0
+#define GC_USB_DAINTMSK_OUTEPMSK10_OFFSET 0x81c
+#define GC_USB_DAINTMSK_OUTEPMSK11_LSB 0x1b
+#define GC_USB_DAINTMSK_OUTEPMSK11_MASK 0x8000000
+#define GC_USB_DAINTMSK_OUTEPMSK11_SIZE 0x1
+#define GC_USB_DAINTMSK_OUTEPMSK11_DEFAULT 0x0
+#define GC_USB_DAINTMSK_OUTEPMSK11_OFFSET 0x81c
+#define GC_USB_DAINTMSK_OUTEPMSK12_LSB 0x1c
+#define GC_USB_DAINTMSK_OUTEPMSK12_MASK 0x10000000
+#define GC_USB_DAINTMSK_OUTEPMSK12_SIZE 0x1
+#define GC_USB_DAINTMSK_OUTEPMSK12_DEFAULT 0x0
+#define GC_USB_DAINTMSK_OUTEPMSK12_OFFSET 0x81c
+#define GC_USB_DAINTMSK_OUTEPMSK13_LSB 0x1d
+#define GC_USB_DAINTMSK_OUTEPMSK13_MASK 0x20000000
+#define GC_USB_DAINTMSK_OUTEPMSK13_SIZE 0x1
+#define GC_USB_DAINTMSK_OUTEPMSK13_DEFAULT 0x0
+#define GC_USB_DAINTMSK_OUTEPMSK13_OFFSET 0x81c
+#define GC_USB_DAINTMSK_OUTEPMSK14_LSB 0x1e
+#define GC_USB_DAINTMSK_OUTEPMSK14_MASK 0x40000000
+#define GC_USB_DAINTMSK_OUTEPMSK14_SIZE 0x1
+#define GC_USB_DAINTMSK_OUTEPMSK14_DEFAULT 0x0
+#define GC_USB_DAINTMSK_OUTEPMSK14_OFFSET 0x81c
+#define GC_USB_DAINTMSK_OUTEPMSK15_LSB 0x1f
+#define GC_USB_DAINTMSK_OUTEPMSK15_MASK 0x80000000
+#define GC_USB_DAINTMSK_OUTEPMSK15_SIZE 0x1
+#define GC_USB_DAINTMSK_OUTEPMSK15_DEFAULT 0x0
+#define GC_USB_DAINTMSK_OUTEPMSK15_OFFSET 0x81c
+#define GC_USB_DVBUSDIS_DVBUSDIS_LSB 0x0
+#define GC_USB_DVBUSDIS_DVBUSDIS_MASK 0xffff
+#define GC_USB_DVBUSDIS_DVBUSDIS_SIZE 0x10
+#define GC_USB_DVBUSDIS_DVBUSDIS_DEFAULT 0x0
+#define GC_USB_DVBUSDIS_DVBUSDIS_OFFSET 0x828
+#define GC_USB_DVBUSPULSE_DVBUSPULSE_LSB 0x0
+#define GC_USB_DVBUSPULSE_DVBUSPULSE_MASK 0xfff
+#define GC_USB_DVBUSPULSE_DVBUSPULSE_SIZE 0xc
+#define GC_USB_DVBUSPULSE_DVBUSPULSE_DEFAULT 0x0
+#define GC_USB_DVBUSPULSE_DVBUSPULSE_OFFSET 0x82c
+#define GC_USB_DTHRCTL_NONISOTHREN_LSB 0x0
+#define GC_USB_DTHRCTL_NONISOTHREN_MASK 0x1
+#define GC_USB_DTHRCTL_NONISOTHREN_SIZE 0x1
+#define GC_USB_DTHRCTL_NONISOTHREN_DEFAULT 0x0
+#define GC_USB_DTHRCTL_NONISOTHREN_OFFSET 0x830
+#define GC_USB_DTHRCTL_ISOTHREN_LSB 0x1
+#define GC_USB_DTHRCTL_ISOTHREN_MASK 0x2
+#define GC_USB_DTHRCTL_ISOTHREN_SIZE 0x1
+#define GC_USB_DTHRCTL_ISOTHREN_DEFAULT 0x0
+#define GC_USB_DTHRCTL_ISOTHREN_OFFSET 0x830
+#define GC_USB_DTHRCTL_TXTHRLEN_LSB 0x2
+#define GC_USB_DTHRCTL_TXTHRLEN_MASK 0x7fc
+#define GC_USB_DTHRCTL_TXTHRLEN_SIZE 0x9
+#define GC_USB_DTHRCTL_TXTHRLEN_DEFAULT 0x0
+#define GC_USB_DTHRCTL_TXTHRLEN_OFFSET 0x830
+#define GC_USB_DTHRCTL_AHBTHRRATIO_LSB 0xb
+#define GC_USB_DTHRCTL_AHBTHRRATIO_MASK 0x1800
+#define GC_USB_DTHRCTL_AHBTHRRATIO_SIZE 0x2
+#define GC_USB_DTHRCTL_AHBTHRRATIO_DEFAULT 0x0
+#define GC_USB_DTHRCTL_AHBTHRRATIO_OFFSET 0x830
+#define GC_USB_DTHRCTL_RXTHREN_LSB 0x10
+#define GC_USB_DTHRCTL_RXTHREN_MASK 0x10000
+#define GC_USB_DTHRCTL_RXTHREN_SIZE 0x1
+#define GC_USB_DTHRCTL_RXTHREN_DEFAULT 0x0
+#define GC_USB_DTHRCTL_RXTHREN_OFFSET 0x830
+#define GC_USB_DTHRCTL_RXTHRLEN_LSB 0x11
+#define GC_USB_DTHRCTL_RXTHRLEN_MASK 0x3fe0000
+#define GC_USB_DTHRCTL_RXTHRLEN_SIZE 0x9
+#define GC_USB_DTHRCTL_RXTHRLEN_DEFAULT 0x0
+#define GC_USB_DTHRCTL_RXTHRLEN_OFFSET 0x830
+#define GC_USB_DTHRCTL_ARBPRKEN_LSB 0x1b
+#define GC_USB_DTHRCTL_ARBPRKEN_MASK 0x8000000
+#define GC_USB_DTHRCTL_ARBPRKEN_SIZE 0x1
+#define GC_USB_DTHRCTL_ARBPRKEN_DEFAULT 0x0
+#define GC_USB_DTHRCTL_ARBPRKEN_OFFSET 0x830
+#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_LSB 0x0
+#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_MASK 0xffff
+#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_SIZE 0x10
+#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_DEFAULT 0x0
+#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_OFFSET 0x834
+#define GC_USB_DIEPCTL0_MPS_LSB 0x0
+#define GC_USB_DIEPCTL0_MPS_MASK 0x3
+#define GC_USB_DIEPCTL0_MPS_SIZE 0x2
+#define GC_USB_DIEPCTL0_MPS_DEFAULT 0x0
+#define GC_USB_DIEPCTL0_MPS_OFFSET 0x900
+#define GC_USB_DIEPCTL0_USBACTEP_LSB 0xf
+#define GC_USB_DIEPCTL0_USBACTEP_MASK 0x8000
+#define GC_USB_DIEPCTL0_USBACTEP_SIZE 0x1
+#define GC_USB_DIEPCTL0_USBACTEP_DEFAULT 0x0
+#define GC_USB_DIEPCTL0_USBACTEP_OFFSET 0x900
+#define GC_USB_DIEPCTL0_NAKSTS_LSB 0x11
+#define GC_USB_DIEPCTL0_NAKSTS_MASK 0x20000
+#define GC_USB_DIEPCTL0_NAKSTS_SIZE 0x1
+#define GC_USB_DIEPCTL0_NAKSTS_DEFAULT 0x0
+#define GC_USB_DIEPCTL0_NAKSTS_OFFSET 0x900
+#define GC_USB_DIEPCTL0_EPTYPE_LSB 0x12
+#define GC_USB_DIEPCTL0_EPTYPE_MASK 0xc0000
+#define GC_USB_DIEPCTL0_EPTYPE_SIZE 0x2
+#define GC_USB_DIEPCTL0_EPTYPE_DEFAULT 0x0
+#define GC_USB_DIEPCTL0_EPTYPE_OFFSET 0x900
+#define GC_USB_DIEPCTL0_STALL_LSB 0x15
+#define GC_USB_DIEPCTL0_STALL_MASK 0x200000
+#define GC_USB_DIEPCTL0_STALL_SIZE 0x1
+#define GC_USB_DIEPCTL0_STALL_DEFAULT 0x0
+#define GC_USB_DIEPCTL0_STALL_OFFSET 0x900
+#define GC_USB_DIEPCTL0_TXFNUM_LSB 0x16
+#define GC_USB_DIEPCTL0_TXFNUM_MASK 0x3c00000
+#define GC_USB_DIEPCTL0_TXFNUM_SIZE 0x4
+#define GC_USB_DIEPCTL0_TXFNUM_DEFAULT 0x0
+#define GC_USB_DIEPCTL0_TXFNUM_OFFSET 0x900
+#define GC_USB_DIEPCTL0_CNAK_LSB 0x1a
+#define GC_USB_DIEPCTL0_CNAK_MASK 0x4000000
+#define GC_USB_DIEPCTL0_CNAK_SIZE 0x1
+#define GC_USB_DIEPCTL0_CNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL0_CNAK_OFFSET 0x900
+#define GC_USB_DIEPCTL0_SNAK_LSB 0x1b
+#define GC_USB_DIEPCTL0_SNAK_MASK 0x8000000
+#define GC_USB_DIEPCTL0_SNAK_SIZE 0x1
+#define GC_USB_DIEPCTL0_SNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL0_SNAK_OFFSET 0x900
+#define GC_USB_DIEPCTL0_EPDIS_LSB 0x1e
+#define GC_USB_DIEPCTL0_EPDIS_MASK 0x40000000
+#define GC_USB_DIEPCTL0_EPDIS_SIZE 0x1
+#define GC_USB_DIEPCTL0_EPDIS_DEFAULT 0x0
+#define GC_USB_DIEPCTL0_EPDIS_OFFSET 0x900
+#define GC_USB_DIEPCTL0_EPENA_LSB 0x1f
+#define GC_USB_DIEPCTL0_EPENA_MASK 0x80000000
+#define GC_USB_DIEPCTL0_EPENA_SIZE 0x1
+#define GC_USB_DIEPCTL0_EPENA_DEFAULT 0x0
+#define GC_USB_DIEPCTL0_EPENA_OFFSET 0x900
+#define GC_USB_DIEPINT0_XFERCOMPL_LSB 0x0
+#define GC_USB_DIEPINT0_XFERCOMPL_MASK 0x1
+#define GC_USB_DIEPINT0_XFERCOMPL_SIZE 0x1
+#define GC_USB_DIEPINT0_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DIEPINT0_XFERCOMPL_OFFSET 0x908
+#define GC_USB_DIEPINT0_EPDISBLD_LSB 0x1
+#define GC_USB_DIEPINT0_EPDISBLD_MASK 0x2
+#define GC_USB_DIEPINT0_EPDISBLD_SIZE 0x1
+#define GC_USB_DIEPINT0_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DIEPINT0_EPDISBLD_OFFSET 0x908
+#define GC_USB_DIEPINT0_AHBERR_LSB 0x2
+#define GC_USB_DIEPINT0_AHBERR_MASK 0x4
+#define GC_USB_DIEPINT0_AHBERR_SIZE 0x1
+#define GC_USB_DIEPINT0_AHBERR_DEFAULT 0x0
+#define GC_USB_DIEPINT0_AHBERR_OFFSET 0x908
+#define GC_USB_DIEPINT0_TIMEOUT_LSB 0x3
+#define GC_USB_DIEPINT0_TIMEOUT_MASK 0x8
+#define GC_USB_DIEPINT0_TIMEOUT_SIZE 0x1
+#define GC_USB_DIEPINT0_TIMEOUT_DEFAULT 0x0
+#define GC_USB_DIEPINT0_TIMEOUT_OFFSET 0x908
+#define GC_USB_DIEPINT0_INTKNTXFEMP_LSB 0x4
+#define GC_USB_DIEPINT0_INTKNTXFEMP_MASK 0x10
+#define GC_USB_DIEPINT0_INTKNTXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT0_INTKNTXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT0_INTKNTXFEMP_OFFSET 0x908
+#define GC_USB_DIEPINT0_INTKNEPMIS_LSB 0x5
+#define GC_USB_DIEPINT0_INTKNEPMIS_MASK 0x20
+#define GC_USB_DIEPINT0_INTKNEPMIS_SIZE 0x1
+#define GC_USB_DIEPINT0_INTKNEPMIS_DEFAULT 0x0
+#define GC_USB_DIEPINT0_INTKNEPMIS_OFFSET 0x908
+#define GC_USB_DIEPINT0_INEPNAKEFF_LSB 0x6
+#define GC_USB_DIEPINT0_INEPNAKEFF_MASK 0x40
+#define GC_USB_DIEPINT0_INEPNAKEFF_SIZE 0x1
+#define GC_USB_DIEPINT0_INEPNAKEFF_DEFAULT 0x0
+#define GC_USB_DIEPINT0_INEPNAKEFF_OFFSET 0x908
+#define GC_USB_DIEPINT0_TXFEMP_LSB 0x7
+#define GC_USB_DIEPINT0_TXFEMP_MASK 0x80
+#define GC_USB_DIEPINT0_TXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT0_TXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT0_TXFEMP_OFFSET 0x908
+#define GC_USB_DIEPINT0_TXFIFOUNDRN_LSB 0x8
+#define GC_USB_DIEPINT0_TXFIFOUNDRN_MASK 0x100
+#define GC_USB_DIEPINT0_TXFIFOUNDRN_SIZE 0x1
+#define GC_USB_DIEPINT0_TXFIFOUNDRN_DEFAULT 0x0
+#define GC_USB_DIEPINT0_TXFIFOUNDRN_OFFSET 0x908
+#define GC_USB_DIEPINT0_BNAINTR_LSB 0x9
+#define GC_USB_DIEPINT0_BNAINTR_MASK 0x200
+#define GC_USB_DIEPINT0_BNAINTR_SIZE 0x1
+#define GC_USB_DIEPINT0_BNAINTR_DEFAULT 0x0
+#define GC_USB_DIEPINT0_BNAINTR_OFFSET 0x908
+#define GC_USB_DIEPINT0_PKTDRPSTS_LSB 0xb
+#define GC_USB_DIEPINT0_PKTDRPSTS_MASK 0x800
+#define GC_USB_DIEPINT0_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DIEPINT0_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DIEPINT0_PKTDRPSTS_OFFSET 0x908
+#define GC_USB_DIEPINT0_BBLEERR_LSB 0xc
+#define GC_USB_DIEPINT0_BBLEERR_MASK 0x1000
+#define GC_USB_DIEPINT0_BBLEERR_SIZE 0x1
+#define GC_USB_DIEPINT0_BBLEERR_DEFAULT 0x0
+#define GC_USB_DIEPINT0_BBLEERR_OFFSET 0x908
+#define GC_USB_DIEPINT0_NAKINTRPT_LSB 0xd
+#define GC_USB_DIEPINT0_NAKINTRPT_MASK 0x2000
+#define GC_USB_DIEPINT0_NAKINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT0_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT0_NAKINTRPT_OFFSET 0x908
+#define GC_USB_DIEPINT0_NYETINTRPT_LSB 0xe
+#define GC_USB_DIEPINT0_NYETINTRPT_MASK 0x4000
+#define GC_USB_DIEPINT0_NYETINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT0_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT0_NYETINTRPT_OFFSET 0x908
+#define GC_USB_DIEPTSIZ0_XFERSIZE_LSB 0x0
+#define GC_USB_DIEPTSIZ0_XFERSIZE_MASK 0x7f
+#define GC_USB_DIEPTSIZ0_XFERSIZE_SIZE 0x7
+#define GC_USB_DIEPTSIZ0_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ0_XFERSIZE_OFFSET 0x910
+#define GC_USB_DIEPTSIZ0_PKTCNT_LSB 0x13
+#define GC_USB_DIEPTSIZ0_PKTCNT_MASK 0x180000
+#define GC_USB_DIEPTSIZ0_PKTCNT_SIZE 0x2
+#define GC_USB_DIEPTSIZ0_PKTCNT_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ0_PKTCNT_OFFSET 0x910
+#define GC_USB_DIEPDMA0_DMAADDR_LSB 0x0
+#define GC_USB_DIEPDMA0_DMAADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMA0_DMAADDR_SIZE 0x20
+#define GC_USB_DIEPDMA0_DMAADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMA0_DMAADDR_OFFSET 0x914
+#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_LSB 0x0
+#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_MASK 0xffff
+#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_SIZE 0x10
+#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_DEFAULT 0x0
+#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_OFFSET 0x918
+#define GC_USB_DIEPDMAB0_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DIEPDMAB0_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMAB0_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DIEPDMAB0_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMAB0_DMABUFFERADDR_OFFSET 0x91c
+#define GC_USB_DIEPCTL1_MPS_LSB 0x0
+#define GC_USB_DIEPCTL1_MPS_MASK 0x7ff
+#define GC_USB_DIEPCTL1_MPS_SIZE 0xb
+#define GC_USB_DIEPCTL1_MPS_DEFAULT 0x0
+#define GC_USB_DIEPCTL1_MPS_OFFSET 0x920
+#define GC_USB_DIEPCTL1_USBACTEP_LSB 0xf
+#define GC_USB_DIEPCTL1_USBACTEP_MASK 0x8000
+#define GC_USB_DIEPCTL1_USBACTEP_SIZE 0x1
+#define GC_USB_DIEPCTL1_USBACTEP_DEFAULT 0x0
+#define GC_USB_DIEPCTL1_USBACTEP_OFFSET 0x920
+#define GC_USB_DIEPCTL1_DPID_LSB 0x10
+#define GC_USB_DIEPCTL1_DPID_MASK 0x10000
+#define GC_USB_DIEPCTL1_DPID_SIZE 0x1
+#define GC_USB_DIEPCTL1_DPID_DEFAULT 0x0
+#define GC_USB_DIEPCTL1_DPID_OFFSET 0x920
+#define GC_USB_DIEPCTL1_NAKSTS_LSB 0x11
+#define GC_USB_DIEPCTL1_NAKSTS_MASK 0x20000
+#define GC_USB_DIEPCTL1_NAKSTS_SIZE 0x1
+#define GC_USB_DIEPCTL1_NAKSTS_DEFAULT 0x0
+#define GC_USB_DIEPCTL1_NAKSTS_OFFSET 0x920
+#define GC_USB_DIEPCTL1_EPTYPE_LSB 0x12
+#define GC_USB_DIEPCTL1_EPTYPE_MASK 0xc0000
+#define GC_USB_DIEPCTL1_EPTYPE_SIZE 0x2
+#define GC_USB_DIEPCTL1_EPTYPE_DEFAULT 0x0
+#define GC_USB_DIEPCTL1_EPTYPE_OFFSET 0x920
+#define GC_USB_DIEPCTL1_STALL_LSB 0x15
+#define GC_USB_DIEPCTL1_STALL_MASK 0x200000
+#define GC_USB_DIEPCTL1_STALL_SIZE 0x1
+#define GC_USB_DIEPCTL1_STALL_DEFAULT 0x0
+#define GC_USB_DIEPCTL1_STALL_OFFSET 0x920
+#define GC_USB_DIEPCTL1_TXFNUM_LSB 0x16
+#define GC_USB_DIEPCTL1_TXFNUM_MASK 0x3c00000
+#define GC_USB_DIEPCTL1_TXFNUM_SIZE 0x4
+#define GC_USB_DIEPCTL1_TXFNUM_DEFAULT 0x0
+#define GC_USB_DIEPCTL1_TXFNUM_OFFSET 0x920
+#define GC_USB_DIEPCTL1_CNAK_LSB 0x1a
+#define GC_USB_DIEPCTL1_CNAK_MASK 0x4000000
+#define GC_USB_DIEPCTL1_CNAK_SIZE 0x1
+#define GC_USB_DIEPCTL1_CNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL1_CNAK_OFFSET 0x920
+#define GC_USB_DIEPCTL1_SNAK_LSB 0x1b
+#define GC_USB_DIEPCTL1_SNAK_MASK 0x8000000
+#define GC_USB_DIEPCTL1_SNAK_SIZE 0x1
+#define GC_USB_DIEPCTL1_SNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL1_SNAK_OFFSET 0x920
+#define GC_USB_DIEPCTL1_SETD0PID_LSB 0x1c
+#define GC_USB_DIEPCTL1_SETD0PID_MASK 0x10000000
+#define GC_USB_DIEPCTL1_SETD0PID_SIZE 0x1
+#define GC_USB_DIEPCTL1_SETD0PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL1_SETD0PID_OFFSET 0x920
+#define GC_USB_DIEPCTL1_SETD1PID_LSB 0x1d
+#define GC_USB_DIEPCTL1_SETD1PID_MASK 0x20000000
+#define GC_USB_DIEPCTL1_SETD1PID_SIZE 0x1
+#define GC_USB_DIEPCTL1_SETD1PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL1_SETD1PID_OFFSET 0x920
+#define GC_USB_DIEPCTL1_EPDIS_LSB 0x1e
+#define GC_USB_DIEPCTL1_EPDIS_MASK 0x40000000
+#define GC_USB_DIEPCTL1_EPDIS_SIZE 0x1
+#define GC_USB_DIEPCTL1_EPDIS_DEFAULT 0x0
+#define GC_USB_DIEPCTL1_EPDIS_OFFSET 0x920
+#define GC_USB_DIEPCTL1_EPENA_LSB 0x1f
+#define GC_USB_DIEPCTL1_EPENA_MASK 0x80000000
+#define GC_USB_DIEPCTL1_EPENA_SIZE 0x1
+#define GC_USB_DIEPCTL1_EPENA_DEFAULT 0x0
+#define GC_USB_DIEPCTL1_EPENA_OFFSET 0x920
+#define GC_USB_DIEPINT1_XFERCOMPL_LSB 0x0
+#define GC_USB_DIEPINT1_XFERCOMPL_MASK 0x1
+#define GC_USB_DIEPINT1_XFERCOMPL_SIZE 0x1
+#define GC_USB_DIEPINT1_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DIEPINT1_XFERCOMPL_OFFSET 0x928
+#define GC_USB_DIEPINT1_EPDISBLD_LSB 0x1
+#define GC_USB_DIEPINT1_EPDISBLD_MASK 0x2
+#define GC_USB_DIEPINT1_EPDISBLD_SIZE 0x1
+#define GC_USB_DIEPINT1_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DIEPINT1_EPDISBLD_OFFSET 0x928
+#define GC_USB_DIEPINT1_AHBERR_LSB 0x2
+#define GC_USB_DIEPINT1_AHBERR_MASK 0x4
+#define GC_USB_DIEPINT1_AHBERR_SIZE 0x1
+#define GC_USB_DIEPINT1_AHBERR_DEFAULT 0x0
+#define GC_USB_DIEPINT1_AHBERR_OFFSET 0x928
+#define GC_USB_DIEPINT1_TIMEOUT_LSB 0x3
+#define GC_USB_DIEPINT1_TIMEOUT_MASK 0x8
+#define GC_USB_DIEPINT1_TIMEOUT_SIZE 0x1
+#define GC_USB_DIEPINT1_TIMEOUT_DEFAULT 0x0
+#define GC_USB_DIEPINT1_TIMEOUT_OFFSET 0x928
+#define GC_USB_DIEPINT1_INTKNTXFEMP_LSB 0x4
+#define GC_USB_DIEPINT1_INTKNTXFEMP_MASK 0x10
+#define GC_USB_DIEPINT1_INTKNTXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT1_INTKNTXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT1_INTKNTXFEMP_OFFSET 0x928
+#define GC_USB_DIEPINT1_INTKNEPMIS_LSB 0x5
+#define GC_USB_DIEPINT1_INTKNEPMIS_MASK 0x20
+#define GC_USB_DIEPINT1_INTKNEPMIS_SIZE 0x1
+#define GC_USB_DIEPINT1_INTKNEPMIS_DEFAULT 0x0
+#define GC_USB_DIEPINT1_INTKNEPMIS_OFFSET 0x928
+#define GC_USB_DIEPINT1_INEPNAKEFF_LSB 0x6
+#define GC_USB_DIEPINT1_INEPNAKEFF_MASK 0x40
+#define GC_USB_DIEPINT1_INEPNAKEFF_SIZE 0x1
+#define GC_USB_DIEPINT1_INEPNAKEFF_DEFAULT 0x0
+#define GC_USB_DIEPINT1_INEPNAKEFF_OFFSET 0x928
+#define GC_USB_DIEPINT1_TXFEMP_LSB 0x7
+#define GC_USB_DIEPINT1_TXFEMP_MASK 0x80
+#define GC_USB_DIEPINT1_TXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT1_TXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT1_TXFEMP_OFFSET 0x928
+#define GC_USB_DIEPINT1_TXFIFOUNDRN_LSB 0x8
+#define GC_USB_DIEPINT1_TXFIFOUNDRN_MASK 0x100
+#define GC_USB_DIEPINT1_TXFIFOUNDRN_SIZE 0x1
+#define GC_USB_DIEPINT1_TXFIFOUNDRN_DEFAULT 0x0
+#define GC_USB_DIEPINT1_TXFIFOUNDRN_OFFSET 0x928
+#define GC_USB_DIEPINT1_BNAINTR_LSB 0x9
+#define GC_USB_DIEPINT1_BNAINTR_MASK 0x200
+#define GC_USB_DIEPINT1_BNAINTR_SIZE 0x1
+#define GC_USB_DIEPINT1_BNAINTR_DEFAULT 0x0
+#define GC_USB_DIEPINT1_BNAINTR_OFFSET 0x928
+#define GC_USB_DIEPINT1_PKTDRPSTS_LSB 0xb
+#define GC_USB_DIEPINT1_PKTDRPSTS_MASK 0x800
+#define GC_USB_DIEPINT1_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DIEPINT1_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DIEPINT1_PKTDRPSTS_OFFSET 0x928
+#define GC_USB_DIEPINT1_BBLEERR_LSB 0xc
+#define GC_USB_DIEPINT1_BBLEERR_MASK 0x1000
+#define GC_USB_DIEPINT1_BBLEERR_SIZE 0x1
+#define GC_USB_DIEPINT1_BBLEERR_DEFAULT 0x0
+#define GC_USB_DIEPINT1_BBLEERR_OFFSET 0x928
+#define GC_USB_DIEPINT1_NAKINTRPT_LSB 0xd
+#define GC_USB_DIEPINT1_NAKINTRPT_MASK 0x2000
+#define GC_USB_DIEPINT1_NAKINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT1_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT1_NAKINTRPT_OFFSET 0x928
+#define GC_USB_DIEPINT1_NYETINTRPT_LSB 0xe
+#define GC_USB_DIEPINT1_NYETINTRPT_MASK 0x4000
+#define GC_USB_DIEPINT1_NYETINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT1_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT1_NYETINTRPT_OFFSET 0x928
+#define GC_USB_DIEPTSIZ1_XFERSIZE_LSB 0x0
+#define GC_USB_DIEPTSIZ1_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DIEPTSIZ1_XFERSIZE_SIZE 0x13
+#define GC_USB_DIEPTSIZ1_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ1_XFERSIZE_OFFSET 0x930
+#define GC_USB_DIEPTSIZ1_PKTCNT_LSB 0x13
+#define GC_USB_DIEPTSIZ1_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DIEPTSIZ1_PKTCNT_SIZE 0xa
+#define GC_USB_DIEPTSIZ1_PKTCNT_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ1_PKTCNT_OFFSET 0x930
+#define GC_USB_DIEPTSIZ1_MC_LSB 0x1d
+#define GC_USB_DIEPTSIZ1_MC_MASK 0x60000000
+#define GC_USB_DIEPTSIZ1_MC_SIZE 0x2
+#define GC_USB_DIEPTSIZ1_MC_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ1_MC_OFFSET 0x930
+#define GC_USB_DIEPDMA1_DMAADDR_LSB 0x0
+#define GC_USB_DIEPDMA1_DMAADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMA1_DMAADDR_SIZE 0x20
+#define GC_USB_DIEPDMA1_DMAADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMA1_DMAADDR_OFFSET 0x934
+#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_LSB 0x0
+#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_MASK 0xffff
+#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_SIZE 0x10
+#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_DEFAULT 0x0
+#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_OFFSET 0x938
+#define GC_USB_DIEPDMAB1_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DIEPDMAB1_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMAB1_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DIEPDMAB1_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMAB1_DMABUFFERADDR_OFFSET 0x93c
+#define GC_USB_DIEPCTL2_MPS_LSB 0x0
+#define GC_USB_DIEPCTL2_MPS_MASK 0x7ff
+#define GC_USB_DIEPCTL2_MPS_SIZE 0xb
+#define GC_USB_DIEPCTL2_MPS_DEFAULT 0x0
+#define GC_USB_DIEPCTL2_MPS_OFFSET 0x940
+#define GC_USB_DIEPCTL2_USBACTEP_LSB 0xf
+#define GC_USB_DIEPCTL2_USBACTEP_MASK 0x8000
+#define GC_USB_DIEPCTL2_USBACTEP_SIZE 0x1
+#define GC_USB_DIEPCTL2_USBACTEP_DEFAULT 0x0
+#define GC_USB_DIEPCTL2_USBACTEP_OFFSET 0x940
+#define GC_USB_DIEPCTL2_DPID_LSB 0x10
+#define GC_USB_DIEPCTL2_DPID_MASK 0x10000
+#define GC_USB_DIEPCTL2_DPID_SIZE 0x1
+#define GC_USB_DIEPCTL2_DPID_DEFAULT 0x0
+#define GC_USB_DIEPCTL2_DPID_OFFSET 0x940
+#define GC_USB_DIEPCTL2_NAKSTS_LSB 0x11
+#define GC_USB_DIEPCTL2_NAKSTS_MASK 0x20000
+#define GC_USB_DIEPCTL2_NAKSTS_SIZE 0x1
+#define GC_USB_DIEPCTL2_NAKSTS_DEFAULT 0x0
+#define GC_USB_DIEPCTL2_NAKSTS_OFFSET 0x940
+#define GC_USB_DIEPCTL2_EPTYPE_LSB 0x12
+#define GC_USB_DIEPCTL2_EPTYPE_MASK 0xc0000
+#define GC_USB_DIEPCTL2_EPTYPE_SIZE 0x2
+#define GC_USB_DIEPCTL2_EPTYPE_DEFAULT 0x0
+#define GC_USB_DIEPCTL2_EPTYPE_OFFSET 0x940
+#define GC_USB_DIEPCTL2_STALL_LSB 0x15
+#define GC_USB_DIEPCTL2_STALL_MASK 0x200000
+#define GC_USB_DIEPCTL2_STALL_SIZE 0x1
+#define GC_USB_DIEPCTL2_STALL_DEFAULT 0x0
+#define GC_USB_DIEPCTL2_STALL_OFFSET 0x940
+#define GC_USB_DIEPCTL2_TXFNUM_LSB 0x16
+#define GC_USB_DIEPCTL2_TXFNUM_MASK 0x3c00000
+#define GC_USB_DIEPCTL2_TXFNUM_SIZE 0x4
+#define GC_USB_DIEPCTL2_TXFNUM_DEFAULT 0x0
+#define GC_USB_DIEPCTL2_TXFNUM_OFFSET 0x940
+#define GC_USB_DIEPCTL2_CNAK_LSB 0x1a
+#define GC_USB_DIEPCTL2_CNAK_MASK 0x4000000
+#define GC_USB_DIEPCTL2_CNAK_SIZE 0x1
+#define GC_USB_DIEPCTL2_CNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL2_CNAK_OFFSET 0x940
+#define GC_USB_DIEPCTL2_SNAK_LSB 0x1b
+#define GC_USB_DIEPCTL2_SNAK_MASK 0x8000000
+#define GC_USB_DIEPCTL2_SNAK_SIZE 0x1
+#define GC_USB_DIEPCTL2_SNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL2_SNAK_OFFSET 0x940
+#define GC_USB_DIEPCTL2_SETD0PID_LSB 0x1c
+#define GC_USB_DIEPCTL2_SETD0PID_MASK 0x10000000
+#define GC_USB_DIEPCTL2_SETD0PID_SIZE 0x1
+#define GC_USB_DIEPCTL2_SETD0PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL2_SETD0PID_OFFSET 0x940
+#define GC_USB_DIEPCTL2_SETD1PID_LSB 0x1d
+#define GC_USB_DIEPCTL2_SETD1PID_MASK 0x20000000
+#define GC_USB_DIEPCTL2_SETD1PID_SIZE 0x1
+#define GC_USB_DIEPCTL2_SETD1PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL2_SETD1PID_OFFSET 0x940
+#define GC_USB_DIEPCTL2_EPDIS_LSB 0x1e
+#define GC_USB_DIEPCTL2_EPDIS_MASK 0x40000000
+#define GC_USB_DIEPCTL2_EPDIS_SIZE 0x1
+#define GC_USB_DIEPCTL2_EPDIS_DEFAULT 0x0
+#define GC_USB_DIEPCTL2_EPDIS_OFFSET 0x940
+#define GC_USB_DIEPCTL2_EPENA_LSB 0x1f
+#define GC_USB_DIEPCTL2_EPENA_MASK 0x80000000
+#define GC_USB_DIEPCTL2_EPENA_SIZE 0x1
+#define GC_USB_DIEPCTL2_EPENA_DEFAULT 0x0
+#define GC_USB_DIEPCTL2_EPENA_OFFSET 0x940
+#define GC_USB_DIEPINT2_XFERCOMPL_LSB 0x0
+#define GC_USB_DIEPINT2_XFERCOMPL_MASK 0x1
+#define GC_USB_DIEPINT2_XFERCOMPL_SIZE 0x1
+#define GC_USB_DIEPINT2_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DIEPINT2_XFERCOMPL_OFFSET 0x948
+#define GC_USB_DIEPINT2_EPDISBLD_LSB 0x1
+#define GC_USB_DIEPINT2_EPDISBLD_MASK 0x2
+#define GC_USB_DIEPINT2_EPDISBLD_SIZE 0x1
+#define GC_USB_DIEPINT2_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DIEPINT2_EPDISBLD_OFFSET 0x948
+#define GC_USB_DIEPINT2_AHBERR_LSB 0x2
+#define GC_USB_DIEPINT2_AHBERR_MASK 0x4
+#define GC_USB_DIEPINT2_AHBERR_SIZE 0x1
+#define GC_USB_DIEPINT2_AHBERR_DEFAULT 0x0
+#define GC_USB_DIEPINT2_AHBERR_OFFSET 0x948
+#define GC_USB_DIEPINT2_TIMEOUT_LSB 0x3
+#define GC_USB_DIEPINT2_TIMEOUT_MASK 0x8
+#define GC_USB_DIEPINT2_TIMEOUT_SIZE 0x1
+#define GC_USB_DIEPINT2_TIMEOUT_DEFAULT 0x0
+#define GC_USB_DIEPINT2_TIMEOUT_OFFSET 0x948
+#define GC_USB_DIEPINT2_INTKNTXFEMP_LSB 0x4
+#define GC_USB_DIEPINT2_INTKNTXFEMP_MASK 0x10
+#define GC_USB_DIEPINT2_INTKNTXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT2_INTKNTXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT2_INTKNTXFEMP_OFFSET 0x948
+#define GC_USB_DIEPINT2_INTKNEPMIS_LSB 0x5
+#define GC_USB_DIEPINT2_INTKNEPMIS_MASK 0x20
+#define GC_USB_DIEPINT2_INTKNEPMIS_SIZE 0x1
+#define GC_USB_DIEPINT2_INTKNEPMIS_DEFAULT 0x0
+#define GC_USB_DIEPINT2_INTKNEPMIS_OFFSET 0x948
+#define GC_USB_DIEPINT2_INEPNAKEFF_LSB 0x6
+#define GC_USB_DIEPINT2_INEPNAKEFF_MASK 0x40
+#define GC_USB_DIEPINT2_INEPNAKEFF_SIZE 0x1
+#define GC_USB_DIEPINT2_INEPNAKEFF_DEFAULT 0x0
+#define GC_USB_DIEPINT2_INEPNAKEFF_OFFSET 0x948
+#define GC_USB_DIEPINT2_TXFEMP_LSB 0x7
+#define GC_USB_DIEPINT2_TXFEMP_MASK 0x80
+#define GC_USB_DIEPINT2_TXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT2_TXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT2_TXFEMP_OFFSET 0x948
+#define GC_USB_DIEPINT2_TXFIFOUNDRN_LSB 0x8
+#define GC_USB_DIEPINT2_TXFIFOUNDRN_MASK 0x100
+#define GC_USB_DIEPINT2_TXFIFOUNDRN_SIZE 0x1
+#define GC_USB_DIEPINT2_TXFIFOUNDRN_DEFAULT 0x0
+#define GC_USB_DIEPINT2_TXFIFOUNDRN_OFFSET 0x948
+#define GC_USB_DIEPINT2_BNAINTR_LSB 0x9
+#define GC_USB_DIEPINT2_BNAINTR_MASK 0x200
+#define GC_USB_DIEPINT2_BNAINTR_SIZE 0x1
+#define GC_USB_DIEPINT2_BNAINTR_DEFAULT 0x0
+#define GC_USB_DIEPINT2_BNAINTR_OFFSET 0x948
+#define GC_USB_DIEPINT2_PKTDRPSTS_LSB 0xb
+#define GC_USB_DIEPINT2_PKTDRPSTS_MASK 0x800
+#define GC_USB_DIEPINT2_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DIEPINT2_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DIEPINT2_PKTDRPSTS_OFFSET 0x948
+#define GC_USB_DIEPINT2_BBLEERR_LSB 0xc
+#define GC_USB_DIEPINT2_BBLEERR_MASK 0x1000
+#define GC_USB_DIEPINT2_BBLEERR_SIZE 0x1
+#define GC_USB_DIEPINT2_BBLEERR_DEFAULT 0x0
+#define GC_USB_DIEPINT2_BBLEERR_OFFSET 0x948
+#define GC_USB_DIEPINT2_NAKINTRPT_LSB 0xd
+#define GC_USB_DIEPINT2_NAKINTRPT_MASK 0x2000
+#define GC_USB_DIEPINT2_NAKINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT2_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT2_NAKINTRPT_OFFSET 0x948
+#define GC_USB_DIEPINT2_NYETINTRPT_LSB 0xe
+#define GC_USB_DIEPINT2_NYETINTRPT_MASK 0x4000
+#define GC_USB_DIEPINT2_NYETINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT2_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT2_NYETINTRPT_OFFSET 0x948
+#define GC_USB_DIEPTSIZ2_XFERSIZE_LSB 0x0
+#define GC_USB_DIEPTSIZ2_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DIEPTSIZ2_XFERSIZE_SIZE 0x13
+#define GC_USB_DIEPTSIZ2_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ2_XFERSIZE_OFFSET 0x950
+#define GC_USB_DIEPTSIZ2_PKTCNT_LSB 0x13
+#define GC_USB_DIEPTSIZ2_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DIEPTSIZ2_PKTCNT_SIZE 0xa
+#define GC_USB_DIEPTSIZ2_PKTCNT_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ2_PKTCNT_OFFSET 0x950
+#define GC_USB_DIEPTSIZ2_MC_LSB 0x1d
+#define GC_USB_DIEPTSIZ2_MC_MASK 0x60000000
+#define GC_USB_DIEPTSIZ2_MC_SIZE 0x2
+#define GC_USB_DIEPTSIZ2_MC_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ2_MC_OFFSET 0x950
+#define GC_USB_DIEPDMA2_DMAADDR_LSB 0x0
+#define GC_USB_DIEPDMA2_DMAADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMA2_DMAADDR_SIZE 0x20
+#define GC_USB_DIEPDMA2_DMAADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMA2_DMAADDR_OFFSET 0x954
+#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_LSB 0x0
+#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_MASK 0xffff
+#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_SIZE 0x10
+#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_DEFAULT 0x0
+#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_OFFSET 0x958
+#define GC_USB_DIEPDMAB2_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DIEPDMAB2_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMAB2_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DIEPDMAB2_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMAB2_DMABUFFERADDR_OFFSET 0x95c
+#define GC_USB_DIEPCTL3_MPS_LSB 0x0
+#define GC_USB_DIEPCTL3_MPS_MASK 0x7ff
+#define GC_USB_DIEPCTL3_MPS_SIZE 0xb
+#define GC_USB_DIEPCTL3_MPS_DEFAULT 0x0
+#define GC_USB_DIEPCTL3_MPS_OFFSET 0x960
+#define GC_USB_DIEPCTL3_USBACTEP_LSB 0xf
+#define GC_USB_DIEPCTL3_USBACTEP_MASK 0x8000
+#define GC_USB_DIEPCTL3_USBACTEP_SIZE 0x1
+#define GC_USB_DIEPCTL3_USBACTEP_DEFAULT 0x0
+#define GC_USB_DIEPCTL3_USBACTEP_OFFSET 0x960
+#define GC_USB_DIEPCTL3_DPID_LSB 0x10
+#define GC_USB_DIEPCTL3_DPID_MASK 0x10000
+#define GC_USB_DIEPCTL3_DPID_SIZE 0x1
+#define GC_USB_DIEPCTL3_DPID_DEFAULT 0x0
+#define GC_USB_DIEPCTL3_DPID_OFFSET 0x960
+#define GC_USB_DIEPCTL3_NAKSTS_LSB 0x11
+#define GC_USB_DIEPCTL3_NAKSTS_MASK 0x20000
+#define GC_USB_DIEPCTL3_NAKSTS_SIZE 0x1
+#define GC_USB_DIEPCTL3_NAKSTS_DEFAULT 0x0
+#define GC_USB_DIEPCTL3_NAKSTS_OFFSET 0x960
+#define GC_USB_DIEPCTL3_EPTYPE_LSB 0x12
+#define GC_USB_DIEPCTL3_EPTYPE_MASK 0xc0000
+#define GC_USB_DIEPCTL3_EPTYPE_SIZE 0x2
+#define GC_USB_DIEPCTL3_EPTYPE_DEFAULT 0x0
+#define GC_USB_DIEPCTL3_EPTYPE_OFFSET 0x960
+#define GC_USB_DIEPCTL3_STALL_LSB 0x15
+#define GC_USB_DIEPCTL3_STALL_MASK 0x200000
+#define GC_USB_DIEPCTL3_STALL_SIZE 0x1
+#define GC_USB_DIEPCTL3_STALL_DEFAULT 0x0
+#define GC_USB_DIEPCTL3_STALL_OFFSET 0x960
+#define GC_USB_DIEPCTL3_TXFNUM_LSB 0x16
+#define GC_USB_DIEPCTL3_TXFNUM_MASK 0x3c00000
+#define GC_USB_DIEPCTL3_TXFNUM_SIZE 0x4
+#define GC_USB_DIEPCTL3_TXFNUM_DEFAULT 0x0
+#define GC_USB_DIEPCTL3_TXFNUM_OFFSET 0x960
+#define GC_USB_DIEPCTL3_CNAK_LSB 0x1a
+#define GC_USB_DIEPCTL3_CNAK_MASK 0x4000000
+#define GC_USB_DIEPCTL3_CNAK_SIZE 0x1
+#define GC_USB_DIEPCTL3_CNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL3_CNAK_OFFSET 0x960
+#define GC_USB_DIEPCTL3_SNAK_LSB 0x1b
+#define GC_USB_DIEPCTL3_SNAK_MASK 0x8000000
+#define GC_USB_DIEPCTL3_SNAK_SIZE 0x1
+#define GC_USB_DIEPCTL3_SNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL3_SNAK_OFFSET 0x960
+#define GC_USB_DIEPCTL3_SETD0PID_LSB 0x1c
+#define GC_USB_DIEPCTL3_SETD0PID_MASK 0x10000000
+#define GC_USB_DIEPCTL3_SETD0PID_SIZE 0x1
+#define GC_USB_DIEPCTL3_SETD0PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL3_SETD0PID_OFFSET 0x960
+#define GC_USB_DIEPCTL3_SETD1PID_LSB 0x1d
+#define GC_USB_DIEPCTL3_SETD1PID_MASK 0x20000000
+#define GC_USB_DIEPCTL3_SETD1PID_SIZE 0x1
+#define GC_USB_DIEPCTL3_SETD1PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL3_SETD1PID_OFFSET 0x960
+#define GC_USB_DIEPCTL3_EPDIS_LSB 0x1e
+#define GC_USB_DIEPCTL3_EPDIS_MASK 0x40000000
+#define GC_USB_DIEPCTL3_EPDIS_SIZE 0x1
+#define GC_USB_DIEPCTL3_EPDIS_DEFAULT 0x0
+#define GC_USB_DIEPCTL3_EPDIS_OFFSET 0x960
+#define GC_USB_DIEPCTL3_EPENA_LSB 0x1f
+#define GC_USB_DIEPCTL3_EPENA_MASK 0x80000000
+#define GC_USB_DIEPCTL3_EPENA_SIZE 0x1
+#define GC_USB_DIEPCTL3_EPENA_DEFAULT 0x0
+#define GC_USB_DIEPCTL3_EPENA_OFFSET 0x960
+#define GC_USB_DIEPINT3_XFERCOMPL_LSB 0x0
+#define GC_USB_DIEPINT3_XFERCOMPL_MASK 0x1
+#define GC_USB_DIEPINT3_XFERCOMPL_SIZE 0x1
+#define GC_USB_DIEPINT3_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DIEPINT3_XFERCOMPL_OFFSET 0x968
+#define GC_USB_DIEPINT3_EPDISBLD_LSB 0x1
+#define GC_USB_DIEPINT3_EPDISBLD_MASK 0x2
+#define GC_USB_DIEPINT3_EPDISBLD_SIZE 0x1
+#define GC_USB_DIEPINT3_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DIEPINT3_EPDISBLD_OFFSET 0x968
+#define GC_USB_DIEPINT3_AHBERR_LSB 0x2
+#define GC_USB_DIEPINT3_AHBERR_MASK 0x4
+#define GC_USB_DIEPINT3_AHBERR_SIZE 0x1
+#define GC_USB_DIEPINT3_AHBERR_DEFAULT 0x0
+#define GC_USB_DIEPINT3_AHBERR_OFFSET 0x968
+#define GC_USB_DIEPINT3_TIMEOUT_LSB 0x3
+#define GC_USB_DIEPINT3_TIMEOUT_MASK 0x8
+#define GC_USB_DIEPINT3_TIMEOUT_SIZE 0x1
+#define GC_USB_DIEPINT3_TIMEOUT_DEFAULT 0x0
+#define GC_USB_DIEPINT3_TIMEOUT_OFFSET 0x968
+#define GC_USB_DIEPINT3_INTKNTXFEMP_LSB 0x4
+#define GC_USB_DIEPINT3_INTKNTXFEMP_MASK 0x10
+#define GC_USB_DIEPINT3_INTKNTXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT3_INTKNTXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT3_INTKNTXFEMP_OFFSET 0x968
+#define GC_USB_DIEPINT3_INTKNEPMIS_LSB 0x5
+#define GC_USB_DIEPINT3_INTKNEPMIS_MASK 0x20
+#define GC_USB_DIEPINT3_INTKNEPMIS_SIZE 0x1
+#define GC_USB_DIEPINT3_INTKNEPMIS_DEFAULT 0x0
+#define GC_USB_DIEPINT3_INTKNEPMIS_OFFSET 0x968
+#define GC_USB_DIEPINT3_INEPNAKEFF_LSB 0x6
+#define GC_USB_DIEPINT3_INEPNAKEFF_MASK 0x40
+#define GC_USB_DIEPINT3_INEPNAKEFF_SIZE 0x1
+#define GC_USB_DIEPINT3_INEPNAKEFF_DEFAULT 0x0
+#define GC_USB_DIEPINT3_INEPNAKEFF_OFFSET 0x968
+#define GC_USB_DIEPINT3_TXFEMP_LSB 0x7
+#define GC_USB_DIEPINT3_TXFEMP_MASK 0x80
+#define GC_USB_DIEPINT3_TXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT3_TXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT3_TXFEMP_OFFSET 0x968
+#define GC_USB_DIEPINT3_TXFIFOUNDRN_LSB 0x8
+#define GC_USB_DIEPINT3_TXFIFOUNDRN_MASK 0x100
+#define GC_USB_DIEPINT3_TXFIFOUNDRN_SIZE 0x1
+#define GC_USB_DIEPINT3_TXFIFOUNDRN_DEFAULT 0x0
+#define GC_USB_DIEPINT3_TXFIFOUNDRN_OFFSET 0x968
+#define GC_USB_DIEPINT3_BNAINTR_LSB 0x9
+#define GC_USB_DIEPINT3_BNAINTR_MASK 0x200
+#define GC_USB_DIEPINT3_BNAINTR_SIZE 0x1
+#define GC_USB_DIEPINT3_BNAINTR_DEFAULT 0x0
+#define GC_USB_DIEPINT3_BNAINTR_OFFSET 0x968
+#define GC_USB_DIEPINT3_PKTDRPSTS_LSB 0xb
+#define GC_USB_DIEPINT3_PKTDRPSTS_MASK 0x800
+#define GC_USB_DIEPINT3_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DIEPINT3_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DIEPINT3_PKTDRPSTS_OFFSET 0x968
+#define GC_USB_DIEPINT3_BBLEERR_LSB 0xc
+#define GC_USB_DIEPINT3_BBLEERR_MASK 0x1000
+#define GC_USB_DIEPINT3_BBLEERR_SIZE 0x1
+#define GC_USB_DIEPINT3_BBLEERR_DEFAULT 0x0
+#define GC_USB_DIEPINT3_BBLEERR_OFFSET 0x968
+#define GC_USB_DIEPINT3_NAKINTRPT_LSB 0xd
+#define GC_USB_DIEPINT3_NAKINTRPT_MASK 0x2000
+#define GC_USB_DIEPINT3_NAKINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT3_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT3_NAKINTRPT_OFFSET 0x968
+#define GC_USB_DIEPINT3_NYETINTRPT_LSB 0xe
+#define GC_USB_DIEPINT3_NYETINTRPT_MASK 0x4000
+#define GC_USB_DIEPINT3_NYETINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT3_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT3_NYETINTRPT_OFFSET 0x968
+#define GC_USB_DIEPTSIZ3_XFERSIZE_LSB 0x0
+#define GC_USB_DIEPTSIZ3_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DIEPTSIZ3_XFERSIZE_SIZE 0x13
+#define GC_USB_DIEPTSIZ3_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ3_XFERSIZE_OFFSET 0x970
+#define GC_USB_DIEPTSIZ3_PKTCNT_LSB 0x13
+#define GC_USB_DIEPTSIZ3_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DIEPTSIZ3_PKTCNT_SIZE 0xa
+#define GC_USB_DIEPTSIZ3_PKTCNT_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ3_PKTCNT_OFFSET 0x970
+#define GC_USB_DIEPTSIZ3_MC_LSB 0x1d
+#define GC_USB_DIEPTSIZ3_MC_MASK 0x60000000
+#define GC_USB_DIEPTSIZ3_MC_SIZE 0x2
+#define GC_USB_DIEPTSIZ3_MC_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ3_MC_OFFSET 0x970
+#define GC_USB_DIEPDMA3_DMAADDR_LSB 0x0
+#define GC_USB_DIEPDMA3_DMAADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMA3_DMAADDR_SIZE 0x20
+#define GC_USB_DIEPDMA3_DMAADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMA3_DMAADDR_OFFSET 0x974
+#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_LSB 0x0
+#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_MASK 0xffff
+#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_SIZE 0x10
+#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_DEFAULT 0x0
+#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_OFFSET 0x978
+#define GC_USB_DIEPDMAB3_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DIEPDMAB3_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMAB3_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DIEPDMAB3_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMAB3_DMABUFFERADDR_OFFSET 0x97c
+#define GC_USB_DIEPCTL4_MPS_LSB 0x0
+#define GC_USB_DIEPCTL4_MPS_MASK 0x7ff
+#define GC_USB_DIEPCTL4_MPS_SIZE 0xb
+#define GC_USB_DIEPCTL4_MPS_DEFAULT 0x0
+#define GC_USB_DIEPCTL4_MPS_OFFSET 0x980
+#define GC_USB_DIEPCTL4_USBACTEP_LSB 0xf
+#define GC_USB_DIEPCTL4_USBACTEP_MASK 0x8000
+#define GC_USB_DIEPCTL4_USBACTEP_SIZE 0x1
+#define GC_USB_DIEPCTL4_USBACTEP_DEFAULT 0x0
+#define GC_USB_DIEPCTL4_USBACTEP_OFFSET 0x980
+#define GC_USB_DIEPCTL4_DPID_LSB 0x10
+#define GC_USB_DIEPCTL4_DPID_MASK 0x10000
+#define GC_USB_DIEPCTL4_DPID_SIZE 0x1
+#define GC_USB_DIEPCTL4_DPID_DEFAULT 0x0
+#define GC_USB_DIEPCTL4_DPID_OFFSET 0x980
+#define GC_USB_DIEPCTL4_NAKSTS_LSB 0x11
+#define GC_USB_DIEPCTL4_NAKSTS_MASK 0x20000
+#define GC_USB_DIEPCTL4_NAKSTS_SIZE 0x1
+#define GC_USB_DIEPCTL4_NAKSTS_DEFAULT 0x0
+#define GC_USB_DIEPCTL4_NAKSTS_OFFSET 0x980
+#define GC_USB_DIEPCTL4_EPTYPE_LSB 0x12
+#define GC_USB_DIEPCTL4_EPTYPE_MASK 0xc0000
+#define GC_USB_DIEPCTL4_EPTYPE_SIZE 0x2
+#define GC_USB_DIEPCTL4_EPTYPE_DEFAULT 0x0
+#define GC_USB_DIEPCTL4_EPTYPE_OFFSET 0x980
+#define GC_USB_DIEPCTL4_STALL_LSB 0x15
+#define GC_USB_DIEPCTL4_STALL_MASK 0x200000
+#define GC_USB_DIEPCTL4_STALL_SIZE 0x1
+#define GC_USB_DIEPCTL4_STALL_DEFAULT 0x0
+#define GC_USB_DIEPCTL4_STALL_OFFSET 0x980
+#define GC_USB_DIEPCTL4_TXFNUM_LSB 0x16
+#define GC_USB_DIEPCTL4_TXFNUM_MASK 0x3c00000
+#define GC_USB_DIEPCTL4_TXFNUM_SIZE 0x4
+#define GC_USB_DIEPCTL4_TXFNUM_DEFAULT 0x0
+#define GC_USB_DIEPCTL4_TXFNUM_OFFSET 0x980
+#define GC_USB_DIEPCTL4_CNAK_LSB 0x1a
+#define GC_USB_DIEPCTL4_CNAK_MASK 0x4000000
+#define GC_USB_DIEPCTL4_CNAK_SIZE 0x1
+#define GC_USB_DIEPCTL4_CNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL4_CNAK_OFFSET 0x980
+#define GC_USB_DIEPCTL4_SNAK_LSB 0x1b
+#define GC_USB_DIEPCTL4_SNAK_MASK 0x8000000
+#define GC_USB_DIEPCTL4_SNAK_SIZE 0x1
+#define GC_USB_DIEPCTL4_SNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL4_SNAK_OFFSET 0x980
+#define GC_USB_DIEPCTL4_SETD0PID_LSB 0x1c
+#define GC_USB_DIEPCTL4_SETD0PID_MASK 0x10000000
+#define GC_USB_DIEPCTL4_SETD0PID_SIZE 0x1
+#define GC_USB_DIEPCTL4_SETD0PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL4_SETD0PID_OFFSET 0x980
+#define GC_USB_DIEPCTL4_SETD1PID_LSB 0x1d
+#define GC_USB_DIEPCTL4_SETD1PID_MASK 0x20000000
+#define GC_USB_DIEPCTL4_SETD1PID_SIZE 0x1
+#define GC_USB_DIEPCTL4_SETD1PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL4_SETD1PID_OFFSET 0x980
+#define GC_USB_DIEPCTL4_EPDIS_LSB 0x1e
+#define GC_USB_DIEPCTL4_EPDIS_MASK 0x40000000
+#define GC_USB_DIEPCTL4_EPDIS_SIZE 0x1
+#define GC_USB_DIEPCTL4_EPDIS_DEFAULT 0x0
+#define GC_USB_DIEPCTL4_EPDIS_OFFSET 0x980
+#define GC_USB_DIEPCTL4_EPENA_LSB 0x1f
+#define GC_USB_DIEPCTL4_EPENA_MASK 0x80000000
+#define GC_USB_DIEPCTL4_EPENA_SIZE 0x1
+#define GC_USB_DIEPCTL4_EPENA_DEFAULT 0x0
+#define GC_USB_DIEPCTL4_EPENA_OFFSET 0x980
+#define GC_USB_DIEPINT4_XFERCOMPL_LSB 0x0
+#define GC_USB_DIEPINT4_XFERCOMPL_MASK 0x1
+#define GC_USB_DIEPINT4_XFERCOMPL_SIZE 0x1
+#define GC_USB_DIEPINT4_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DIEPINT4_XFERCOMPL_OFFSET 0x988
+#define GC_USB_DIEPINT4_EPDISBLD_LSB 0x1
+#define GC_USB_DIEPINT4_EPDISBLD_MASK 0x2
+#define GC_USB_DIEPINT4_EPDISBLD_SIZE 0x1
+#define GC_USB_DIEPINT4_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DIEPINT4_EPDISBLD_OFFSET 0x988
+#define GC_USB_DIEPINT4_AHBERR_LSB 0x2
+#define GC_USB_DIEPINT4_AHBERR_MASK 0x4
+#define GC_USB_DIEPINT4_AHBERR_SIZE 0x1
+#define GC_USB_DIEPINT4_AHBERR_DEFAULT 0x0
+#define GC_USB_DIEPINT4_AHBERR_OFFSET 0x988
+#define GC_USB_DIEPINT4_TIMEOUT_LSB 0x3
+#define GC_USB_DIEPINT4_TIMEOUT_MASK 0x8
+#define GC_USB_DIEPINT4_TIMEOUT_SIZE 0x1
+#define GC_USB_DIEPINT4_TIMEOUT_DEFAULT 0x0
+#define GC_USB_DIEPINT4_TIMEOUT_OFFSET 0x988
+#define GC_USB_DIEPINT4_INTKNTXFEMP_LSB 0x4
+#define GC_USB_DIEPINT4_INTKNTXFEMP_MASK 0x10
+#define GC_USB_DIEPINT4_INTKNTXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT4_INTKNTXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT4_INTKNTXFEMP_OFFSET 0x988
+#define GC_USB_DIEPINT4_INTKNEPMIS_LSB 0x5
+#define GC_USB_DIEPINT4_INTKNEPMIS_MASK 0x20
+#define GC_USB_DIEPINT4_INTKNEPMIS_SIZE 0x1
+#define GC_USB_DIEPINT4_INTKNEPMIS_DEFAULT 0x0
+#define GC_USB_DIEPINT4_INTKNEPMIS_OFFSET 0x988
+#define GC_USB_DIEPINT4_INEPNAKEFF_LSB 0x6
+#define GC_USB_DIEPINT4_INEPNAKEFF_MASK 0x40
+#define GC_USB_DIEPINT4_INEPNAKEFF_SIZE 0x1
+#define GC_USB_DIEPINT4_INEPNAKEFF_DEFAULT 0x0
+#define GC_USB_DIEPINT4_INEPNAKEFF_OFFSET 0x988
+#define GC_USB_DIEPINT4_TXFEMP_LSB 0x7
+#define GC_USB_DIEPINT4_TXFEMP_MASK 0x80
+#define GC_USB_DIEPINT4_TXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT4_TXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT4_TXFEMP_OFFSET 0x988
+#define GC_USB_DIEPINT4_TXFIFOUNDRN_LSB 0x8
+#define GC_USB_DIEPINT4_TXFIFOUNDRN_MASK 0x100
+#define GC_USB_DIEPINT4_TXFIFOUNDRN_SIZE 0x1
+#define GC_USB_DIEPINT4_TXFIFOUNDRN_DEFAULT 0x0
+#define GC_USB_DIEPINT4_TXFIFOUNDRN_OFFSET 0x988
+#define GC_USB_DIEPINT4_BNAINTR_LSB 0x9
+#define GC_USB_DIEPINT4_BNAINTR_MASK 0x200
+#define GC_USB_DIEPINT4_BNAINTR_SIZE 0x1
+#define GC_USB_DIEPINT4_BNAINTR_DEFAULT 0x0
+#define GC_USB_DIEPINT4_BNAINTR_OFFSET 0x988
+#define GC_USB_DIEPINT4_PKTDRPSTS_LSB 0xb
+#define GC_USB_DIEPINT4_PKTDRPSTS_MASK 0x800
+#define GC_USB_DIEPINT4_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DIEPINT4_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DIEPINT4_PKTDRPSTS_OFFSET 0x988
+#define GC_USB_DIEPINT4_BBLEERR_LSB 0xc
+#define GC_USB_DIEPINT4_BBLEERR_MASK 0x1000
+#define GC_USB_DIEPINT4_BBLEERR_SIZE 0x1
+#define GC_USB_DIEPINT4_BBLEERR_DEFAULT 0x0
+#define GC_USB_DIEPINT4_BBLEERR_OFFSET 0x988
+#define GC_USB_DIEPINT4_NAKINTRPT_LSB 0xd
+#define GC_USB_DIEPINT4_NAKINTRPT_MASK 0x2000
+#define GC_USB_DIEPINT4_NAKINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT4_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT4_NAKINTRPT_OFFSET 0x988
+#define GC_USB_DIEPINT4_NYETINTRPT_LSB 0xe
+#define GC_USB_DIEPINT4_NYETINTRPT_MASK 0x4000
+#define GC_USB_DIEPINT4_NYETINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT4_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT4_NYETINTRPT_OFFSET 0x988
+#define GC_USB_DIEPTSIZ4_XFERSIZE_LSB 0x0
+#define GC_USB_DIEPTSIZ4_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DIEPTSIZ4_XFERSIZE_SIZE 0x13
+#define GC_USB_DIEPTSIZ4_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ4_XFERSIZE_OFFSET 0x990
+#define GC_USB_DIEPTSIZ4_PKTCNT_LSB 0x13
+#define GC_USB_DIEPTSIZ4_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DIEPTSIZ4_PKTCNT_SIZE 0xa
+#define GC_USB_DIEPTSIZ4_PKTCNT_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ4_PKTCNT_OFFSET 0x990
+#define GC_USB_DIEPTSIZ4_MC_LSB 0x1d
+#define GC_USB_DIEPTSIZ4_MC_MASK 0x60000000
+#define GC_USB_DIEPTSIZ4_MC_SIZE 0x2
+#define GC_USB_DIEPTSIZ4_MC_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ4_MC_OFFSET 0x990
+#define GC_USB_DIEPDMA4_DMAADDR_LSB 0x0
+#define GC_USB_DIEPDMA4_DMAADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMA4_DMAADDR_SIZE 0x20
+#define GC_USB_DIEPDMA4_DMAADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMA4_DMAADDR_OFFSET 0x994
+#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_LSB 0x0
+#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_MASK 0xffff
+#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_SIZE 0x10
+#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_DEFAULT 0x0
+#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_OFFSET 0x998
+#define GC_USB_DIEPDMAB4_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DIEPDMAB4_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMAB4_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DIEPDMAB4_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMAB4_DMABUFFERADDR_OFFSET 0x99c
+#define GC_USB_DIEPCTL5_MPS_LSB 0x0
+#define GC_USB_DIEPCTL5_MPS_MASK 0x7ff
+#define GC_USB_DIEPCTL5_MPS_SIZE 0xb
+#define GC_USB_DIEPCTL5_MPS_DEFAULT 0x0
+#define GC_USB_DIEPCTL5_MPS_OFFSET 0x9a0
+#define GC_USB_DIEPCTL5_USBACTEP_LSB 0xf
+#define GC_USB_DIEPCTL5_USBACTEP_MASK 0x8000
+#define GC_USB_DIEPCTL5_USBACTEP_SIZE 0x1
+#define GC_USB_DIEPCTL5_USBACTEP_DEFAULT 0x0
+#define GC_USB_DIEPCTL5_USBACTEP_OFFSET 0x9a0
+#define GC_USB_DIEPCTL5_DPID_LSB 0x10
+#define GC_USB_DIEPCTL5_DPID_MASK 0x10000
+#define GC_USB_DIEPCTL5_DPID_SIZE 0x1
+#define GC_USB_DIEPCTL5_DPID_DEFAULT 0x0
+#define GC_USB_DIEPCTL5_DPID_OFFSET 0x9a0
+#define GC_USB_DIEPCTL5_NAKSTS_LSB 0x11
+#define GC_USB_DIEPCTL5_NAKSTS_MASK 0x20000
+#define GC_USB_DIEPCTL5_NAKSTS_SIZE 0x1
+#define GC_USB_DIEPCTL5_NAKSTS_DEFAULT 0x0
+#define GC_USB_DIEPCTL5_NAKSTS_OFFSET 0x9a0
+#define GC_USB_DIEPCTL5_EPTYPE_LSB 0x12
+#define GC_USB_DIEPCTL5_EPTYPE_MASK 0xc0000
+#define GC_USB_DIEPCTL5_EPTYPE_SIZE 0x2
+#define GC_USB_DIEPCTL5_EPTYPE_DEFAULT 0x0
+#define GC_USB_DIEPCTL5_EPTYPE_OFFSET 0x9a0
+#define GC_USB_DIEPCTL5_STALL_LSB 0x15
+#define GC_USB_DIEPCTL5_STALL_MASK 0x200000
+#define GC_USB_DIEPCTL5_STALL_SIZE 0x1
+#define GC_USB_DIEPCTL5_STALL_DEFAULT 0x0
+#define GC_USB_DIEPCTL5_STALL_OFFSET 0x9a0
+#define GC_USB_DIEPCTL5_TXFNUM_LSB 0x16
+#define GC_USB_DIEPCTL5_TXFNUM_MASK 0x3c00000
+#define GC_USB_DIEPCTL5_TXFNUM_SIZE 0x4
+#define GC_USB_DIEPCTL5_TXFNUM_DEFAULT 0x0
+#define GC_USB_DIEPCTL5_TXFNUM_OFFSET 0x9a0
+#define GC_USB_DIEPCTL5_CNAK_LSB 0x1a
+#define GC_USB_DIEPCTL5_CNAK_MASK 0x4000000
+#define GC_USB_DIEPCTL5_CNAK_SIZE 0x1
+#define GC_USB_DIEPCTL5_CNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL5_CNAK_OFFSET 0x9a0
+#define GC_USB_DIEPCTL5_SNAK_LSB 0x1b
+#define GC_USB_DIEPCTL5_SNAK_MASK 0x8000000
+#define GC_USB_DIEPCTL5_SNAK_SIZE 0x1
+#define GC_USB_DIEPCTL5_SNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL5_SNAK_OFFSET 0x9a0
+#define GC_USB_DIEPCTL5_SETD0PID_LSB 0x1c
+#define GC_USB_DIEPCTL5_SETD0PID_MASK 0x10000000
+#define GC_USB_DIEPCTL5_SETD0PID_SIZE 0x1
+#define GC_USB_DIEPCTL5_SETD0PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL5_SETD0PID_OFFSET 0x9a0
+#define GC_USB_DIEPCTL5_SETD1PID_LSB 0x1d
+#define GC_USB_DIEPCTL5_SETD1PID_MASK 0x20000000
+#define GC_USB_DIEPCTL5_SETD1PID_SIZE 0x1
+#define GC_USB_DIEPCTL5_SETD1PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL5_SETD1PID_OFFSET 0x9a0
+#define GC_USB_DIEPCTL5_EPDIS_LSB 0x1e
+#define GC_USB_DIEPCTL5_EPDIS_MASK 0x40000000
+#define GC_USB_DIEPCTL5_EPDIS_SIZE 0x1
+#define GC_USB_DIEPCTL5_EPDIS_DEFAULT 0x0
+#define GC_USB_DIEPCTL5_EPDIS_OFFSET 0x9a0
+#define GC_USB_DIEPCTL5_EPENA_LSB 0x1f
+#define GC_USB_DIEPCTL5_EPENA_MASK 0x80000000
+#define GC_USB_DIEPCTL5_EPENA_SIZE 0x1
+#define GC_USB_DIEPCTL5_EPENA_DEFAULT 0x0
+#define GC_USB_DIEPCTL5_EPENA_OFFSET 0x9a0
+#define GC_USB_DIEPINT5_XFERCOMPL_LSB 0x0
+#define GC_USB_DIEPINT5_XFERCOMPL_MASK 0x1
+#define GC_USB_DIEPINT5_XFERCOMPL_SIZE 0x1
+#define GC_USB_DIEPINT5_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DIEPINT5_XFERCOMPL_OFFSET 0x9a8
+#define GC_USB_DIEPINT5_EPDISBLD_LSB 0x1
+#define GC_USB_DIEPINT5_EPDISBLD_MASK 0x2
+#define GC_USB_DIEPINT5_EPDISBLD_SIZE 0x1
+#define GC_USB_DIEPINT5_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DIEPINT5_EPDISBLD_OFFSET 0x9a8
+#define GC_USB_DIEPINT5_AHBERR_LSB 0x2
+#define GC_USB_DIEPINT5_AHBERR_MASK 0x4
+#define GC_USB_DIEPINT5_AHBERR_SIZE 0x1
+#define GC_USB_DIEPINT5_AHBERR_DEFAULT 0x0
+#define GC_USB_DIEPINT5_AHBERR_OFFSET 0x9a8
+#define GC_USB_DIEPINT5_TIMEOUT_LSB 0x3
+#define GC_USB_DIEPINT5_TIMEOUT_MASK 0x8
+#define GC_USB_DIEPINT5_TIMEOUT_SIZE 0x1
+#define GC_USB_DIEPINT5_TIMEOUT_DEFAULT 0x0
+#define GC_USB_DIEPINT5_TIMEOUT_OFFSET 0x9a8
+#define GC_USB_DIEPINT5_INTKNTXFEMP_LSB 0x4
+#define GC_USB_DIEPINT5_INTKNTXFEMP_MASK 0x10
+#define GC_USB_DIEPINT5_INTKNTXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT5_INTKNTXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT5_INTKNTXFEMP_OFFSET 0x9a8
+#define GC_USB_DIEPINT5_INTKNEPMIS_LSB 0x5
+#define GC_USB_DIEPINT5_INTKNEPMIS_MASK 0x20
+#define GC_USB_DIEPINT5_INTKNEPMIS_SIZE 0x1
+#define GC_USB_DIEPINT5_INTKNEPMIS_DEFAULT 0x0
+#define GC_USB_DIEPINT5_INTKNEPMIS_OFFSET 0x9a8
+#define GC_USB_DIEPINT5_INEPNAKEFF_LSB 0x6
+#define GC_USB_DIEPINT5_INEPNAKEFF_MASK 0x40
+#define GC_USB_DIEPINT5_INEPNAKEFF_SIZE 0x1
+#define GC_USB_DIEPINT5_INEPNAKEFF_DEFAULT 0x0
+#define GC_USB_DIEPINT5_INEPNAKEFF_OFFSET 0x9a8
+#define GC_USB_DIEPINT5_TXFEMP_LSB 0x7
+#define GC_USB_DIEPINT5_TXFEMP_MASK 0x80
+#define GC_USB_DIEPINT5_TXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT5_TXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT5_TXFEMP_OFFSET 0x9a8
+#define GC_USB_DIEPINT5_TXFIFOUNDRN_LSB 0x8
+#define GC_USB_DIEPINT5_TXFIFOUNDRN_MASK 0x100
+#define GC_USB_DIEPINT5_TXFIFOUNDRN_SIZE 0x1
+#define GC_USB_DIEPINT5_TXFIFOUNDRN_DEFAULT 0x0
+#define GC_USB_DIEPINT5_TXFIFOUNDRN_OFFSET 0x9a8
+#define GC_USB_DIEPINT5_BNAINTR_LSB 0x9
+#define GC_USB_DIEPINT5_BNAINTR_MASK 0x200
+#define GC_USB_DIEPINT5_BNAINTR_SIZE 0x1
+#define GC_USB_DIEPINT5_BNAINTR_DEFAULT 0x0
+#define GC_USB_DIEPINT5_BNAINTR_OFFSET 0x9a8
+#define GC_USB_DIEPINT5_PKTDRPSTS_LSB 0xb
+#define GC_USB_DIEPINT5_PKTDRPSTS_MASK 0x800
+#define GC_USB_DIEPINT5_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DIEPINT5_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DIEPINT5_PKTDRPSTS_OFFSET 0x9a8
+#define GC_USB_DIEPINT5_BBLEERR_LSB 0xc
+#define GC_USB_DIEPINT5_BBLEERR_MASK 0x1000
+#define GC_USB_DIEPINT5_BBLEERR_SIZE 0x1
+#define GC_USB_DIEPINT5_BBLEERR_DEFAULT 0x0
+#define GC_USB_DIEPINT5_BBLEERR_OFFSET 0x9a8
+#define GC_USB_DIEPINT5_NAKINTRPT_LSB 0xd
+#define GC_USB_DIEPINT5_NAKINTRPT_MASK 0x2000
+#define GC_USB_DIEPINT5_NAKINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT5_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT5_NAKINTRPT_OFFSET 0x9a8
+#define GC_USB_DIEPINT5_NYETINTRPT_LSB 0xe
+#define GC_USB_DIEPINT5_NYETINTRPT_MASK 0x4000
+#define GC_USB_DIEPINT5_NYETINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT5_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT5_NYETINTRPT_OFFSET 0x9a8
+#define GC_USB_DIEPTSIZ5_XFERSIZE_LSB 0x0
+#define GC_USB_DIEPTSIZ5_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DIEPTSIZ5_XFERSIZE_SIZE 0x13
+#define GC_USB_DIEPTSIZ5_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ5_XFERSIZE_OFFSET 0x9b0
+#define GC_USB_DIEPTSIZ5_PKTCNT_LSB 0x13
+#define GC_USB_DIEPTSIZ5_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DIEPTSIZ5_PKTCNT_SIZE 0xa
+#define GC_USB_DIEPTSIZ5_PKTCNT_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ5_PKTCNT_OFFSET 0x9b0
+#define GC_USB_DIEPTSIZ5_MC_LSB 0x1d
+#define GC_USB_DIEPTSIZ5_MC_MASK 0x60000000
+#define GC_USB_DIEPTSIZ5_MC_SIZE 0x2
+#define GC_USB_DIEPTSIZ5_MC_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ5_MC_OFFSET 0x9b0
+#define GC_USB_DIEPDMA5_DMAADDR_LSB 0x0
+#define GC_USB_DIEPDMA5_DMAADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMA5_DMAADDR_SIZE 0x20
+#define GC_USB_DIEPDMA5_DMAADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMA5_DMAADDR_OFFSET 0x9b4
+#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_LSB 0x0
+#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_MASK 0xffff
+#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_SIZE 0x10
+#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_DEFAULT 0x0
+#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_OFFSET 0x9b8
+#define GC_USB_DIEPDMAB5_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DIEPDMAB5_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMAB5_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DIEPDMAB5_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMAB5_DMABUFFERADDR_OFFSET 0x9bc
+#define GC_USB_DIEPCTL6_MPS_LSB 0x0
+#define GC_USB_DIEPCTL6_MPS_MASK 0x7ff
+#define GC_USB_DIEPCTL6_MPS_SIZE 0xb
+#define GC_USB_DIEPCTL6_MPS_DEFAULT 0x0
+#define GC_USB_DIEPCTL6_MPS_OFFSET 0x9c0
+#define GC_USB_DIEPCTL6_USBACTEP_LSB 0xf
+#define GC_USB_DIEPCTL6_USBACTEP_MASK 0x8000
+#define GC_USB_DIEPCTL6_USBACTEP_SIZE 0x1
+#define GC_USB_DIEPCTL6_USBACTEP_DEFAULT 0x0
+#define GC_USB_DIEPCTL6_USBACTEP_OFFSET 0x9c0
+#define GC_USB_DIEPCTL6_DPID_LSB 0x10
+#define GC_USB_DIEPCTL6_DPID_MASK 0x10000
+#define GC_USB_DIEPCTL6_DPID_SIZE 0x1
+#define GC_USB_DIEPCTL6_DPID_DEFAULT 0x0
+#define GC_USB_DIEPCTL6_DPID_OFFSET 0x9c0
+#define GC_USB_DIEPCTL6_NAKSTS_LSB 0x11
+#define GC_USB_DIEPCTL6_NAKSTS_MASK 0x20000
+#define GC_USB_DIEPCTL6_NAKSTS_SIZE 0x1
+#define GC_USB_DIEPCTL6_NAKSTS_DEFAULT 0x0
+#define GC_USB_DIEPCTL6_NAKSTS_OFFSET 0x9c0
+#define GC_USB_DIEPCTL6_EPTYPE_LSB 0x12
+#define GC_USB_DIEPCTL6_EPTYPE_MASK 0xc0000
+#define GC_USB_DIEPCTL6_EPTYPE_SIZE 0x2
+#define GC_USB_DIEPCTL6_EPTYPE_DEFAULT 0x0
+#define GC_USB_DIEPCTL6_EPTYPE_OFFSET 0x9c0
+#define GC_USB_DIEPCTL6_STALL_LSB 0x15
+#define GC_USB_DIEPCTL6_STALL_MASK 0x200000
+#define GC_USB_DIEPCTL6_STALL_SIZE 0x1
+#define GC_USB_DIEPCTL6_STALL_DEFAULT 0x0
+#define GC_USB_DIEPCTL6_STALL_OFFSET 0x9c0
+#define GC_USB_DIEPCTL6_TXFNUM_LSB 0x16
+#define GC_USB_DIEPCTL6_TXFNUM_MASK 0x3c00000
+#define GC_USB_DIEPCTL6_TXFNUM_SIZE 0x4
+#define GC_USB_DIEPCTL6_TXFNUM_DEFAULT 0x0
+#define GC_USB_DIEPCTL6_TXFNUM_OFFSET 0x9c0
+#define GC_USB_DIEPCTL6_CNAK_LSB 0x1a
+#define GC_USB_DIEPCTL6_CNAK_MASK 0x4000000
+#define GC_USB_DIEPCTL6_CNAK_SIZE 0x1
+#define GC_USB_DIEPCTL6_CNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL6_CNAK_OFFSET 0x9c0
+#define GC_USB_DIEPCTL6_SNAK_LSB 0x1b
+#define GC_USB_DIEPCTL6_SNAK_MASK 0x8000000
+#define GC_USB_DIEPCTL6_SNAK_SIZE 0x1
+#define GC_USB_DIEPCTL6_SNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL6_SNAK_OFFSET 0x9c0
+#define GC_USB_DIEPCTL6_SETD0PID_LSB 0x1c
+#define GC_USB_DIEPCTL6_SETD0PID_MASK 0x10000000
+#define GC_USB_DIEPCTL6_SETD0PID_SIZE 0x1
+#define GC_USB_DIEPCTL6_SETD0PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL6_SETD0PID_OFFSET 0x9c0
+#define GC_USB_DIEPCTL6_SETD1PID_LSB 0x1d
+#define GC_USB_DIEPCTL6_SETD1PID_MASK 0x20000000
+#define GC_USB_DIEPCTL6_SETD1PID_SIZE 0x1
+#define GC_USB_DIEPCTL6_SETD1PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL6_SETD1PID_OFFSET 0x9c0
+#define GC_USB_DIEPCTL6_EPDIS_LSB 0x1e
+#define GC_USB_DIEPCTL6_EPDIS_MASK 0x40000000
+#define GC_USB_DIEPCTL6_EPDIS_SIZE 0x1
+#define GC_USB_DIEPCTL6_EPDIS_DEFAULT 0x0
+#define GC_USB_DIEPCTL6_EPDIS_OFFSET 0x9c0
+#define GC_USB_DIEPCTL6_EPENA_LSB 0x1f
+#define GC_USB_DIEPCTL6_EPENA_MASK 0x80000000
+#define GC_USB_DIEPCTL6_EPENA_SIZE 0x1
+#define GC_USB_DIEPCTL6_EPENA_DEFAULT 0x0
+#define GC_USB_DIEPCTL6_EPENA_OFFSET 0x9c0
+#define GC_USB_DIEPINT6_XFERCOMPL_LSB 0x0
+#define GC_USB_DIEPINT6_XFERCOMPL_MASK 0x1
+#define GC_USB_DIEPINT6_XFERCOMPL_SIZE 0x1
+#define GC_USB_DIEPINT6_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DIEPINT6_XFERCOMPL_OFFSET 0x9c8
+#define GC_USB_DIEPINT6_EPDISBLD_LSB 0x1
+#define GC_USB_DIEPINT6_EPDISBLD_MASK 0x2
+#define GC_USB_DIEPINT6_EPDISBLD_SIZE 0x1
+#define GC_USB_DIEPINT6_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DIEPINT6_EPDISBLD_OFFSET 0x9c8
+#define GC_USB_DIEPINT6_AHBERR_LSB 0x2
+#define GC_USB_DIEPINT6_AHBERR_MASK 0x4
+#define GC_USB_DIEPINT6_AHBERR_SIZE 0x1
+#define GC_USB_DIEPINT6_AHBERR_DEFAULT 0x0
+#define GC_USB_DIEPINT6_AHBERR_OFFSET 0x9c8
+#define GC_USB_DIEPINT6_TIMEOUT_LSB 0x3
+#define GC_USB_DIEPINT6_TIMEOUT_MASK 0x8
+#define GC_USB_DIEPINT6_TIMEOUT_SIZE 0x1
+#define GC_USB_DIEPINT6_TIMEOUT_DEFAULT 0x0
+#define GC_USB_DIEPINT6_TIMEOUT_OFFSET 0x9c8
+#define GC_USB_DIEPINT6_INTKNTXFEMP_LSB 0x4
+#define GC_USB_DIEPINT6_INTKNTXFEMP_MASK 0x10
+#define GC_USB_DIEPINT6_INTKNTXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT6_INTKNTXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT6_INTKNTXFEMP_OFFSET 0x9c8
+#define GC_USB_DIEPINT6_INTKNEPMIS_LSB 0x5
+#define GC_USB_DIEPINT6_INTKNEPMIS_MASK 0x20
+#define GC_USB_DIEPINT6_INTKNEPMIS_SIZE 0x1
+#define GC_USB_DIEPINT6_INTKNEPMIS_DEFAULT 0x0
+#define GC_USB_DIEPINT6_INTKNEPMIS_OFFSET 0x9c8
+#define GC_USB_DIEPINT6_INEPNAKEFF_LSB 0x6
+#define GC_USB_DIEPINT6_INEPNAKEFF_MASK 0x40
+#define GC_USB_DIEPINT6_INEPNAKEFF_SIZE 0x1
+#define GC_USB_DIEPINT6_INEPNAKEFF_DEFAULT 0x0
+#define GC_USB_DIEPINT6_INEPNAKEFF_OFFSET 0x9c8
+#define GC_USB_DIEPINT6_TXFEMP_LSB 0x7
+#define GC_USB_DIEPINT6_TXFEMP_MASK 0x80
+#define GC_USB_DIEPINT6_TXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT6_TXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT6_TXFEMP_OFFSET 0x9c8
+#define GC_USB_DIEPINT6_TXFIFOUNDRN_LSB 0x8
+#define GC_USB_DIEPINT6_TXFIFOUNDRN_MASK 0x100
+#define GC_USB_DIEPINT6_TXFIFOUNDRN_SIZE 0x1
+#define GC_USB_DIEPINT6_TXFIFOUNDRN_DEFAULT 0x0
+#define GC_USB_DIEPINT6_TXFIFOUNDRN_OFFSET 0x9c8
+#define GC_USB_DIEPINT6_BNAINTR_LSB 0x9
+#define GC_USB_DIEPINT6_BNAINTR_MASK 0x200
+#define GC_USB_DIEPINT6_BNAINTR_SIZE 0x1
+#define GC_USB_DIEPINT6_BNAINTR_DEFAULT 0x0
+#define GC_USB_DIEPINT6_BNAINTR_OFFSET 0x9c8
+#define GC_USB_DIEPINT6_PKTDRPSTS_LSB 0xb
+#define GC_USB_DIEPINT6_PKTDRPSTS_MASK 0x800
+#define GC_USB_DIEPINT6_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DIEPINT6_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DIEPINT6_PKTDRPSTS_OFFSET 0x9c8
+#define GC_USB_DIEPINT6_BBLEERR_LSB 0xc
+#define GC_USB_DIEPINT6_BBLEERR_MASK 0x1000
+#define GC_USB_DIEPINT6_BBLEERR_SIZE 0x1
+#define GC_USB_DIEPINT6_BBLEERR_DEFAULT 0x0
+#define GC_USB_DIEPINT6_BBLEERR_OFFSET 0x9c8
+#define GC_USB_DIEPINT6_NAKINTRPT_LSB 0xd
+#define GC_USB_DIEPINT6_NAKINTRPT_MASK 0x2000
+#define GC_USB_DIEPINT6_NAKINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT6_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT6_NAKINTRPT_OFFSET 0x9c8
+#define GC_USB_DIEPINT6_NYETINTRPT_LSB 0xe
+#define GC_USB_DIEPINT6_NYETINTRPT_MASK 0x4000
+#define GC_USB_DIEPINT6_NYETINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT6_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT6_NYETINTRPT_OFFSET 0x9c8
+#define GC_USB_DIEPTSIZ6_XFERSIZE_LSB 0x0
+#define GC_USB_DIEPTSIZ6_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DIEPTSIZ6_XFERSIZE_SIZE 0x13
+#define GC_USB_DIEPTSIZ6_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ6_XFERSIZE_OFFSET 0x9d0
+#define GC_USB_DIEPTSIZ6_PKTCNT_LSB 0x13
+#define GC_USB_DIEPTSIZ6_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DIEPTSIZ6_PKTCNT_SIZE 0xa
+#define GC_USB_DIEPTSIZ6_PKTCNT_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ6_PKTCNT_OFFSET 0x9d0
+#define GC_USB_DIEPTSIZ6_MC_LSB 0x1d
+#define GC_USB_DIEPTSIZ6_MC_MASK 0x60000000
+#define GC_USB_DIEPTSIZ6_MC_SIZE 0x2
+#define GC_USB_DIEPTSIZ6_MC_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ6_MC_OFFSET 0x9d0
+#define GC_USB_DIEPDMA6_DMAADDR_LSB 0x0
+#define GC_USB_DIEPDMA6_DMAADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMA6_DMAADDR_SIZE 0x20
+#define GC_USB_DIEPDMA6_DMAADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMA6_DMAADDR_OFFSET 0x9d4
+#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_LSB 0x0
+#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_MASK 0xffff
+#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_SIZE 0x10
+#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_DEFAULT 0x0
+#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_OFFSET 0x9d8
+#define GC_USB_DIEPDMAB6_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DIEPDMAB6_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMAB6_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DIEPDMAB6_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMAB6_DMABUFFERADDR_OFFSET 0x9dc
+#define GC_USB_DIEPCTL7_MPS_LSB 0x0
+#define GC_USB_DIEPCTL7_MPS_MASK 0x7ff
+#define GC_USB_DIEPCTL7_MPS_SIZE 0xb
+#define GC_USB_DIEPCTL7_MPS_DEFAULT 0x0
+#define GC_USB_DIEPCTL7_MPS_OFFSET 0x9e0
+#define GC_USB_DIEPCTL7_USBACTEP_LSB 0xf
+#define GC_USB_DIEPCTL7_USBACTEP_MASK 0x8000
+#define GC_USB_DIEPCTL7_USBACTEP_SIZE 0x1
+#define GC_USB_DIEPCTL7_USBACTEP_DEFAULT 0x0
+#define GC_USB_DIEPCTL7_USBACTEP_OFFSET 0x9e0
+#define GC_USB_DIEPCTL7_DPID_LSB 0x10
+#define GC_USB_DIEPCTL7_DPID_MASK 0x10000
+#define GC_USB_DIEPCTL7_DPID_SIZE 0x1
+#define GC_USB_DIEPCTL7_DPID_DEFAULT 0x0
+#define GC_USB_DIEPCTL7_DPID_OFFSET 0x9e0
+#define GC_USB_DIEPCTL7_NAKSTS_LSB 0x11
+#define GC_USB_DIEPCTL7_NAKSTS_MASK 0x20000
+#define GC_USB_DIEPCTL7_NAKSTS_SIZE 0x1
+#define GC_USB_DIEPCTL7_NAKSTS_DEFAULT 0x0
+#define GC_USB_DIEPCTL7_NAKSTS_OFFSET 0x9e0
+#define GC_USB_DIEPCTL7_EPTYPE_LSB 0x12
+#define GC_USB_DIEPCTL7_EPTYPE_MASK 0xc0000
+#define GC_USB_DIEPCTL7_EPTYPE_SIZE 0x2
+#define GC_USB_DIEPCTL7_EPTYPE_DEFAULT 0x0
+#define GC_USB_DIEPCTL7_EPTYPE_OFFSET 0x9e0
+#define GC_USB_DIEPCTL7_STALL_LSB 0x15
+#define GC_USB_DIEPCTL7_STALL_MASK 0x200000
+#define GC_USB_DIEPCTL7_STALL_SIZE 0x1
+#define GC_USB_DIEPCTL7_STALL_DEFAULT 0x0
+#define GC_USB_DIEPCTL7_STALL_OFFSET 0x9e0
+#define GC_USB_DIEPCTL7_TXFNUM_LSB 0x16
+#define GC_USB_DIEPCTL7_TXFNUM_MASK 0x3c00000
+#define GC_USB_DIEPCTL7_TXFNUM_SIZE 0x4
+#define GC_USB_DIEPCTL7_TXFNUM_DEFAULT 0x0
+#define GC_USB_DIEPCTL7_TXFNUM_OFFSET 0x9e0
+#define GC_USB_DIEPCTL7_CNAK_LSB 0x1a
+#define GC_USB_DIEPCTL7_CNAK_MASK 0x4000000
+#define GC_USB_DIEPCTL7_CNAK_SIZE 0x1
+#define GC_USB_DIEPCTL7_CNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL7_CNAK_OFFSET 0x9e0
+#define GC_USB_DIEPCTL7_SNAK_LSB 0x1b
+#define GC_USB_DIEPCTL7_SNAK_MASK 0x8000000
+#define GC_USB_DIEPCTL7_SNAK_SIZE 0x1
+#define GC_USB_DIEPCTL7_SNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL7_SNAK_OFFSET 0x9e0
+#define GC_USB_DIEPCTL7_SETD0PID_LSB 0x1c
+#define GC_USB_DIEPCTL7_SETD0PID_MASK 0x10000000
+#define GC_USB_DIEPCTL7_SETD0PID_SIZE 0x1
+#define GC_USB_DIEPCTL7_SETD0PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL7_SETD0PID_OFFSET 0x9e0
+#define GC_USB_DIEPCTL7_SETD1PID_LSB 0x1d
+#define GC_USB_DIEPCTL7_SETD1PID_MASK 0x20000000
+#define GC_USB_DIEPCTL7_SETD1PID_SIZE 0x1
+#define GC_USB_DIEPCTL7_SETD1PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL7_SETD1PID_OFFSET 0x9e0
+#define GC_USB_DIEPCTL7_EPDIS_LSB 0x1e
+#define GC_USB_DIEPCTL7_EPDIS_MASK 0x40000000
+#define GC_USB_DIEPCTL7_EPDIS_SIZE 0x1
+#define GC_USB_DIEPCTL7_EPDIS_DEFAULT 0x0
+#define GC_USB_DIEPCTL7_EPDIS_OFFSET 0x9e0
+#define GC_USB_DIEPCTL7_EPENA_LSB 0x1f
+#define GC_USB_DIEPCTL7_EPENA_MASK 0x80000000
+#define GC_USB_DIEPCTL7_EPENA_SIZE 0x1
+#define GC_USB_DIEPCTL7_EPENA_DEFAULT 0x0
+#define GC_USB_DIEPCTL7_EPENA_OFFSET 0x9e0
+#define GC_USB_DIEPINT7_XFERCOMPL_LSB 0x0
+#define GC_USB_DIEPINT7_XFERCOMPL_MASK 0x1
+#define GC_USB_DIEPINT7_XFERCOMPL_SIZE 0x1
+#define GC_USB_DIEPINT7_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DIEPINT7_XFERCOMPL_OFFSET 0x9e8
+#define GC_USB_DIEPINT7_EPDISBLD_LSB 0x1
+#define GC_USB_DIEPINT7_EPDISBLD_MASK 0x2
+#define GC_USB_DIEPINT7_EPDISBLD_SIZE 0x1
+#define GC_USB_DIEPINT7_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DIEPINT7_EPDISBLD_OFFSET 0x9e8
+#define GC_USB_DIEPINT7_AHBERR_LSB 0x2
+#define GC_USB_DIEPINT7_AHBERR_MASK 0x4
+#define GC_USB_DIEPINT7_AHBERR_SIZE 0x1
+#define GC_USB_DIEPINT7_AHBERR_DEFAULT 0x0
+#define GC_USB_DIEPINT7_AHBERR_OFFSET 0x9e8
+#define GC_USB_DIEPINT7_TIMEOUT_LSB 0x3
+#define GC_USB_DIEPINT7_TIMEOUT_MASK 0x8
+#define GC_USB_DIEPINT7_TIMEOUT_SIZE 0x1
+#define GC_USB_DIEPINT7_TIMEOUT_DEFAULT 0x0
+#define GC_USB_DIEPINT7_TIMEOUT_OFFSET 0x9e8
+#define GC_USB_DIEPINT7_INTKNTXFEMP_LSB 0x4
+#define GC_USB_DIEPINT7_INTKNTXFEMP_MASK 0x10
+#define GC_USB_DIEPINT7_INTKNTXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT7_INTKNTXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT7_INTKNTXFEMP_OFFSET 0x9e8
+#define GC_USB_DIEPINT7_INTKNEPMIS_LSB 0x5
+#define GC_USB_DIEPINT7_INTKNEPMIS_MASK 0x20
+#define GC_USB_DIEPINT7_INTKNEPMIS_SIZE 0x1
+#define GC_USB_DIEPINT7_INTKNEPMIS_DEFAULT 0x0
+#define GC_USB_DIEPINT7_INTKNEPMIS_OFFSET 0x9e8
+#define GC_USB_DIEPINT7_INEPNAKEFF_LSB 0x6
+#define GC_USB_DIEPINT7_INEPNAKEFF_MASK 0x40
+#define GC_USB_DIEPINT7_INEPNAKEFF_SIZE 0x1
+#define GC_USB_DIEPINT7_INEPNAKEFF_DEFAULT 0x0
+#define GC_USB_DIEPINT7_INEPNAKEFF_OFFSET 0x9e8
+#define GC_USB_DIEPINT7_TXFEMP_LSB 0x7
+#define GC_USB_DIEPINT7_TXFEMP_MASK 0x80
+#define GC_USB_DIEPINT7_TXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT7_TXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT7_TXFEMP_OFFSET 0x9e8
+#define GC_USB_DIEPINT7_TXFIFOUNDRN_LSB 0x8
+#define GC_USB_DIEPINT7_TXFIFOUNDRN_MASK 0x100
+#define GC_USB_DIEPINT7_TXFIFOUNDRN_SIZE 0x1
+#define GC_USB_DIEPINT7_TXFIFOUNDRN_DEFAULT 0x0
+#define GC_USB_DIEPINT7_TXFIFOUNDRN_OFFSET 0x9e8
+#define GC_USB_DIEPINT7_BNAINTR_LSB 0x9
+#define GC_USB_DIEPINT7_BNAINTR_MASK 0x200
+#define GC_USB_DIEPINT7_BNAINTR_SIZE 0x1
+#define GC_USB_DIEPINT7_BNAINTR_DEFAULT 0x0
+#define GC_USB_DIEPINT7_BNAINTR_OFFSET 0x9e8
+#define GC_USB_DIEPINT7_PKTDRPSTS_LSB 0xb
+#define GC_USB_DIEPINT7_PKTDRPSTS_MASK 0x800
+#define GC_USB_DIEPINT7_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DIEPINT7_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DIEPINT7_PKTDRPSTS_OFFSET 0x9e8
+#define GC_USB_DIEPINT7_BBLEERR_LSB 0xc
+#define GC_USB_DIEPINT7_BBLEERR_MASK 0x1000
+#define GC_USB_DIEPINT7_BBLEERR_SIZE 0x1
+#define GC_USB_DIEPINT7_BBLEERR_DEFAULT 0x0
+#define GC_USB_DIEPINT7_BBLEERR_OFFSET 0x9e8
+#define GC_USB_DIEPINT7_NAKINTRPT_LSB 0xd
+#define GC_USB_DIEPINT7_NAKINTRPT_MASK 0x2000
+#define GC_USB_DIEPINT7_NAKINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT7_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT7_NAKINTRPT_OFFSET 0x9e8
+#define GC_USB_DIEPINT7_NYETINTRPT_LSB 0xe
+#define GC_USB_DIEPINT7_NYETINTRPT_MASK 0x4000
+#define GC_USB_DIEPINT7_NYETINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT7_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT7_NYETINTRPT_OFFSET 0x9e8
+#define GC_USB_DIEPTSIZ7_XFERSIZE_LSB 0x0
+#define GC_USB_DIEPTSIZ7_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DIEPTSIZ7_XFERSIZE_SIZE 0x13
+#define GC_USB_DIEPTSIZ7_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ7_XFERSIZE_OFFSET 0x9f0
+#define GC_USB_DIEPTSIZ7_PKTCNT_LSB 0x13
+#define GC_USB_DIEPTSIZ7_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DIEPTSIZ7_PKTCNT_SIZE 0xa
+#define GC_USB_DIEPTSIZ7_PKTCNT_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ7_PKTCNT_OFFSET 0x9f0
+#define GC_USB_DIEPTSIZ7_MC_LSB 0x1d
+#define GC_USB_DIEPTSIZ7_MC_MASK 0x60000000
+#define GC_USB_DIEPTSIZ7_MC_SIZE 0x2
+#define GC_USB_DIEPTSIZ7_MC_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ7_MC_OFFSET 0x9f0
+#define GC_USB_DIEPDMA7_DMAADDR_LSB 0x0
+#define GC_USB_DIEPDMA7_DMAADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMA7_DMAADDR_SIZE 0x20
+#define GC_USB_DIEPDMA7_DMAADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMA7_DMAADDR_OFFSET 0x9f4
+#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_LSB 0x0
+#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_MASK 0xffff
+#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_SIZE 0x10
+#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_DEFAULT 0x0
+#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_OFFSET 0x9f8
+#define GC_USB_DIEPDMAB7_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DIEPDMAB7_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMAB7_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DIEPDMAB7_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMAB7_DMABUFFERADDR_OFFSET 0x9fc
+#define GC_USB_DIEPCTL8_MPS_LSB 0x0
+#define GC_USB_DIEPCTL8_MPS_MASK 0x7ff
+#define GC_USB_DIEPCTL8_MPS_SIZE 0xb
+#define GC_USB_DIEPCTL8_MPS_DEFAULT 0x0
+#define GC_USB_DIEPCTL8_MPS_OFFSET 0xa00
+#define GC_USB_DIEPCTL8_USBACTEP_LSB 0xf
+#define GC_USB_DIEPCTL8_USBACTEP_MASK 0x8000
+#define GC_USB_DIEPCTL8_USBACTEP_SIZE 0x1
+#define GC_USB_DIEPCTL8_USBACTEP_DEFAULT 0x0
+#define GC_USB_DIEPCTL8_USBACTEP_OFFSET 0xa00
+#define GC_USB_DIEPCTL8_DPID_LSB 0x10
+#define GC_USB_DIEPCTL8_DPID_MASK 0x10000
+#define GC_USB_DIEPCTL8_DPID_SIZE 0x1
+#define GC_USB_DIEPCTL8_DPID_DEFAULT 0x0
+#define GC_USB_DIEPCTL8_DPID_OFFSET 0xa00
+#define GC_USB_DIEPCTL8_NAKSTS_LSB 0x11
+#define GC_USB_DIEPCTL8_NAKSTS_MASK 0x20000
+#define GC_USB_DIEPCTL8_NAKSTS_SIZE 0x1
+#define GC_USB_DIEPCTL8_NAKSTS_DEFAULT 0x0
+#define GC_USB_DIEPCTL8_NAKSTS_OFFSET 0xa00
+#define GC_USB_DIEPCTL8_EPTYPE_LSB 0x12
+#define GC_USB_DIEPCTL8_EPTYPE_MASK 0xc0000
+#define GC_USB_DIEPCTL8_EPTYPE_SIZE 0x2
+#define GC_USB_DIEPCTL8_EPTYPE_DEFAULT 0x0
+#define GC_USB_DIEPCTL8_EPTYPE_OFFSET 0xa00
+#define GC_USB_DIEPCTL8_STALL_LSB 0x15
+#define GC_USB_DIEPCTL8_STALL_MASK 0x200000
+#define GC_USB_DIEPCTL8_STALL_SIZE 0x1
+#define GC_USB_DIEPCTL8_STALL_DEFAULT 0x0
+#define GC_USB_DIEPCTL8_STALL_OFFSET 0xa00
+#define GC_USB_DIEPCTL8_TXFNUM_LSB 0x16
+#define GC_USB_DIEPCTL8_TXFNUM_MASK 0x3c00000
+#define GC_USB_DIEPCTL8_TXFNUM_SIZE 0x4
+#define GC_USB_DIEPCTL8_TXFNUM_DEFAULT 0x0
+#define GC_USB_DIEPCTL8_TXFNUM_OFFSET 0xa00
+#define GC_USB_DIEPCTL8_CNAK_LSB 0x1a
+#define GC_USB_DIEPCTL8_CNAK_MASK 0x4000000
+#define GC_USB_DIEPCTL8_CNAK_SIZE 0x1
+#define GC_USB_DIEPCTL8_CNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL8_CNAK_OFFSET 0xa00
+#define GC_USB_DIEPCTL8_SNAK_LSB 0x1b
+#define GC_USB_DIEPCTL8_SNAK_MASK 0x8000000
+#define GC_USB_DIEPCTL8_SNAK_SIZE 0x1
+#define GC_USB_DIEPCTL8_SNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL8_SNAK_OFFSET 0xa00
+#define GC_USB_DIEPCTL8_SETD0PID_LSB 0x1c
+#define GC_USB_DIEPCTL8_SETD0PID_MASK 0x10000000
+#define GC_USB_DIEPCTL8_SETD0PID_SIZE 0x1
+#define GC_USB_DIEPCTL8_SETD0PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL8_SETD0PID_OFFSET 0xa00
+#define GC_USB_DIEPCTL8_SETD1PID_LSB 0x1d
+#define GC_USB_DIEPCTL8_SETD1PID_MASK 0x20000000
+#define GC_USB_DIEPCTL8_SETD1PID_SIZE 0x1
+#define GC_USB_DIEPCTL8_SETD1PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL8_SETD1PID_OFFSET 0xa00
+#define GC_USB_DIEPCTL8_EPDIS_LSB 0x1e
+#define GC_USB_DIEPCTL8_EPDIS_MASK 0x40000000
+#define GC_USB_DIEPCTL8_EPDIS_SIZE 0x1
+#define GC_USB_DIEPCTL8_EPDIS_DEFAULT 0x0
+#define GC_USB_DIEPCTL8_EPDIS_OFFSET 0xa00
+#define GC_USB_DIEPCTL8_EPENA_LSB 0x1f
+#define GC_USB_DIEPCTL8_EPENA_MASK 0x80000000
+#define GC_USB_DIEPCTL8_EPENA_SIZE 0x1
+#define GC_USB_DIEPCTL8_EPENA_DEFAULT 0x0
+#define GC_USB_DIEPCTL8_EPENA_OFFSET 0xa00
+#define GC_USB_DIEPINT8_XFERCOMPL_LSB 0x0
+#define GC_USB_DIEPINT8_XFERCOMPL_MASK 0x1
+#define GC_USB_DIEPINT8_XFERCOMPL_SIZE 0x1
+#define GC_USB_DIEPINT8_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DIEPINT8_XFERCOMPL_OFFSET 0xa08
+#define GC_USB_DIEPINT8_EPDISBLD_LSB 0x1
+#define GC_USB_DIEPINT8_EPDISBLD_MASK 0x2
+#define GC_USB_DIEPINT8_EPDISBLD_SIZE 0x1
+#define GC_USB_DIEPINT8_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DIEPINT8_EPDISBLD_OFFSET 0xa08
+#define GC_USB_DIEPINT8_AHBERR_LSB 0x2
+#define GC_USB_DIEPINT8_AHBERR_MASK 0x4
+#define GC_USB_DIEPINT8_AHBERR_SIZE 0x1
+#define GC_USB_DIEPINT8_AHBERR_DEFAULT 0x0
+#define GC_USB_DIEPINT8_AHBERR_OFFSET 0xa08
+#define GC_USB_DIEPINT8_TIMEOUT_LSB 0x3
+#define GC_USB_DIEPINT8_TIMEOUT_MASK 0x8
+#define GC_USB_DIEPINT8_TIMEOUT_SIZE 0x1
+#define GC_USB_DIEPINT8_TIMEOUT_DEFAULT 0x0
+#define GC_USB_DIEPINT8_TIMEOUT_OFFSET 0xa08
+#define GC_USB_DIEPINT8_INTKNTXFEMP_LSB 0x4
+#define GC_USB_DIEPINT8_INTKNTXFEMP_MASK 0x10
+#define GC_USB_DIEPINT8_INTKNTXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT8_INTKNTXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT8_INTKNTXFEMP_OFFSET 0xa08
+#define GC_USB_DIEPINT8_INTKNEPMIS_LSB 0x5
+#define GC_USB_DIEPINT8_INTKNEPMIS_MASK 0x20
+#define GC_USB_DIEPINT8_INTKNEPMIS_SIZE 0x1
+#define GC_USB_DIEPINT8_INTKNEPMIS_DEFAULT 0x0
+#define GC_USB_DIEPINT8_INTKNEPMIS_OFFSET 0xa08
+#define GC_USB_DIEPINT8_INEPNAKEFF_LSB 0x6
+#define GC_USB_DIEPINT8_INEPNAKEFF_MASK 0x40
+#define GC_USB_DIEPINT8_INEPNAKEFF_SIZE 0x1
+#define GC_USB_DIEPINT8_INEPNAKEFF_DEFAULT 0x0
+#define GC_USB_DIEPINT8_INEPNAKEFF_OFFSET 0xa08
+#define GC_USB_DIEPINT8_TXFEMP_LSB 0x7
+#define GC_USB_DIEPINT8_TXFEMP_MASK 0x80
+#define GC_USB_DIEPINT8_TXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT8_TXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT8_TXFEMP_OFFSET 0xa08
+#define GC_USB_DIEPINT8_TXFIFOUNDRN_LSB 0x8
+#define GC_USB_DIEPINT8_TXFIFOUNDRN_MASK 0x100
+#define GC_USB_DIEPINT8_TXFIFOUNDRN_SIZE 0x1
+#define GC_USB_DIEPINT8_TXFIFOUNDRN_DEFAULT 0x0
+#define GC_USB_DIEPINT8_TXFIFOUNDRN_OFFSET 0xa08
+#define GC_USB_DIEPINT8_BNAINTR_LSB 0x9
+#define GC_USB_DIEPINT8_BNAINTR_MASK 0x200
+#define GC_USB_DIEPINT8_BNAINTR_SIZE 0x1
+#define GC_USB_DIEPINT8_BNAINTR_DEFAULT 0x0
+#define GC_USB_DIEPINT8_BNAINTR_OFFSET 0xa08
+#define GC_USB_DIEPINT8_PKTDRPSTS_LSB 0xb
+#define GC_USB_DIEPINT8_PKTDRPSTS_MASK 0x800
+#define GC_USB_DIEPINT8_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DIEPINT8_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DIEPINT8_PKTDRPSTS_OFFSET 0xa08
+#define GC_USB_DIEPINT8_BBLEERR_LSB 0xc
+#define GC_USB_DIEPINT8_BBLEERR_MASK 0x1000
+#define GC_USB_DIEPINT8_BBLEERR_SIZE 0x1
+#define GC_USB_DIEPINT8_BBLEERR_DEFAULT 0x0
+#define GC_USB_DIEPINT8_BBLEERR_OFFSET 0xa08
+#define GC_USB_DIEPINT8_NAKINTRPT_LSB 0xd
+#define GC_USB_DIEPINT8_NAKINTRPT_MASK 0x2000
+#define GC_USB_DIEPINT8_NAKINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT8_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT8_NAKINTRPT_OFFSET 0xa08
+#define GC_USB_DIEPINT8_NYETINTRPT_LSB 0xe
+#define GC_USB_DIEPINT8_NYETINTRPT_MASK 0x4000
+#define GC_USB_DIEPINT8_NYETINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT8_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT8_NYETINTRPT_OFFSET 0xa08
+#define GC_USB_DIEPTSIZ8_XFERSIZE_LSB 0x0
+#define GC_USB_DIEPTSIZ8_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DIEPTSIZ8_XFERSIZE_SIZE 0x13
+#define GC_USB_DIEPTSIZ8_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ8_XFERSIZE_OFFSET 0xa10
+#define GC_USB_DIEPTSIZ8_PKTCNT_LSB 0x13
+#define GC_USB_DIEPTSIZ8_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DIEPTSIZ8_PKTCNT_SIZE 0xa
+#define GC_USB_DIEPTSIZ8_PKTCNT_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ8_PKTCNT_OFFSET 0xa10
+#define GC_USB_DIEPTSIZ8_MC_LSB 0x1d
+#define GC_USB_DIEPTSIZ8_MC_MASK 0x60000000
+#define GC_USB_DIEPTSIZ8_MC_SIZE 0x2
+#define GC_USB_DIEPTSIZ8_MC_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ8_MC_OFFSET 0xa10
+#define GC_USB_DIEPDMA8_DMAADDR_LSB 0x0
+#define GC_USB_DIEPDMA8_DMAADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMA8_DMAADDR_SIZE 0x20
+#define GC_USB_DIEPDMA8_DMAADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMA8_DMAADDR_OFFSET 0xa14
+#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_LSB 0x0
+#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_MASK 0xffff
+#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_SIZE 0x10
+#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_DEFAULT 0x0
+#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_OFFSET 0xa18
+#define GC_USB_DIEPDMAB8_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DIEPDMAB8_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMAB8_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DIEPDMAB8_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMAB8_DMABUFFERADDR_OFFSET 0xa1c
+#define GC_USB_DIEPCTL9_MPS_LSB 0x0
+#define GC_USB_DIEPCTL9_MPS_MASK 0x7ff
+#define GC_USB_DIEPCTL9_MPS_SIZE 0xb
+#define GC_USB_DIEPCTL9_MPS_DEFAULT 0x0
+#define GC_USB_DIEPCTL9_MPS_OFFSET 0xa20
+#define GC_USB_DIEPCTL9_USBACTEP_LSB 0xf
+#define GC_USB_DIEPCTL9_USBACTEP_MASK 0x8000
+#define GC_USB_DIEPCTL9_USBACTEP_SIZE 0x1
+#define GC_USB_DIEPCTL9_USBACTEP_DEFAULT 0x0
+#define GC_USB_DIEPCTL9_USBACTEP_OFFSET 0xa20
+#define GC_USB_DIEPCTL9_DPID_LSB 0x10
+#define GC_USB_DIEPCTL9_DPID_MASK 0x10000
+#define GC_USB_DIEPCTL9_DPID_SIZE 0x1
+#define GC_USB_DIEPCTL9_DPID_DEFAULT 0x0
+#define GC_USB_DIEPCTL9_DPID_OFFSET 0xa20
+#define GC_USB_DIEPCTL9_NAKSTS_LSB 0x11
+#define GC_USB_DIEPCTL9_NAKSTS_MASK 0x20000
+#define GC_USB_DIEPCTL9_NAKSTS_SIZE 0x1
+#define GC_USB_DIEPCTL9_NAKSTS_DEFAULT 0x0
+#define GC_USB_DIEPCTL9_NAKSTS_OFFSET 0xa20
+#define GC_USB_DIEPCTL9_EPTYPE_LSB 0x12
+#define GC_USB_DIEPCTL9_EPTYPE_MASK 0xc0000
+#define GC_USB_DIEPCTL9_EPTYPE_SIZE 0x2
+#define GC_USB_DIEPCTL9_EPTYPE_DEFAULT 0x0
+#define GC_USB_DIEPCTL9_EPTYPE_OFFSET 0xa20
+#define GC_USB_DIEPCTL9_STALL_LSB 0x15
+#define GC_USB_DIEPCTL9_STALL_MASK 0x200000
+#define GC_USB_DIEPCTL9_STALL_SIZE 0x1
+#define GC_USB_DIEPCTL9_STALL_DEFAULT 0x0
+#define GC_USB_DIEPCTL9_STALL_OFFSET 0xa20
+#define GC_USB_DIEPCTL9_TXFNUM_LSB 0x16
+#define GC_USB_DIEPCTL9_TXFNUM_MASK 0x3c00000
+#define GC_USB_DIEPCTL9_TXFNUM_SIZE 0x4
+#define GC_USB_DIEPCTL9_TXFNUM_DEFAULT 0x0
+#define GC_USB_DIEPCTL9_TXFNUM_OFFSET 0xa20
+#define GC_USB_DIEPCTL9_CNAK_LSB 0x1a
+#define GC_USB_DIEPCTL9_CNAK_MASK 0x4000000
+#define GC_USB_DIEPCTL9_CNAK_SIZE 0x1
+#define GC_USB_DIEPCTL9_CNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL9_CNAK_OFFSET 0xa20
+#define GC_USB_DIEPCTL9_SNAK_LSB 0x1b
+#define GC_USB_DIEPCTL9_SNAK_MASK 0x8000000
+#define GC_USB_DIEPCTL9_SNAK_SIZE 0x1
+#define GC_USB_DIEPCTL9_SNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL9_SNAK_OFFSET 0xa20
+#define GC_USB_DIEPCTL9_SETD0PID_LSB 0x1c
+#define GC_USB_DIEPCTL9_SETD0PID_MASK 0x10000000
+#define GC_USB_DIEPCTL9_SETD0PID_SIZE 0x1
+#define GC_USB_DIEPCTL9_SETD0PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL9_SETD0PID_OFFSET 0xa20
+#define GC_USB_DIEPCTL9_SETD1PID_LSB 0x1d
+#define GC_USB_DIEPCTL9_SETD1PID_MASK 0x20000000
+#define GC_USB_DIEPCTL9_SETD1PID_SIZE 0x1
+#define GC_USB_DIEPCTL9_SETD1PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL9_SETD1PID_OFFSET 0xa20
+#define GC_USB_DIEPCTL9_EPDIS_LSB 0x1e
+#define GC_USB_DIEPCTL9_EPDIS_MASK 0x40000000
+#define GC_USB_DIEPCTL9_EPDIS_SIZE 0x1
+#define GC_USB_DIEPCTL9_EPDIS_DEFAULT 0x0
+#define GC_USB_DIEPCTL9_EPDIS_OFFSET 0xa20
+#define GC_USB_DIEPCTL9_EPENA_LSB 0x1f
+#define GC_USB_DIEPCTL9_EPENA_MASK 0x80000000
+#define GC_USB_DIEPCTL9_EPENA_SIZE 0x1
+#define GC_USB_DIEPCTL9_EPENA_DEFAULT 0x0
+#define GC_USB_DIEPCTL9_EPENA_OFFSET 0xa20
+#define GC_USB_DIEPINT9_XFERCOMPL_LSB 0x0
+#define GC_USB_DIEPINT9_XFERCOMPL_MASK 0x1
+#define GC_USB_DIEPINT9_XFERCOMPL_SIZE 0x1
+#define GC_USB_DIEPINT9_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DIEPINT9_XFERCOMPL_OFFSET 0xa28
+#define GC_USB_DIEPINT9_EPDISBLD_LSB 0x1
+#define GC_USB_DIEPINT9_EPDISBLD_MASK 0x2
+#define GC_USB_DIEPINT9_EPDISBLD_SIZE 0x1
+#define GC_USB_DIEPINT9_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DIEPINT9_EPDISBLD_OFFSET 0xa28
+#define GC_USB_DIEPINT9_AHBERR_LSB 0x2
+#define GC_USB_DIEPINT9_AHBERR_MASK 0x4
+#define GC_USB_DIEPINT9_AHBERR_SIZE 0x1
+#define GC_USB_DIEPINT9_AHBERR_DEFAULT 0x0
+#define GC_USB_DIEPINT9_AHBERR_OFFSET 0xa28
+#define GC_USB_DIEPINT9_TIMEOUT_LSB 0x3
+#define GC_USB_DIEPINT9_TIMEOUT_MASK 0x8
+#define GC_USB_DIEPINT9_TIMEOUT_SIZE 0x1
+#define GC_USB_DIEPINT9_TIMEOUT_DEFAULT 0x0
+#define GC_USB_DIEPINT9_TIMEOUT_OFFSET 0xa28
+#define GC_USB_DIEPINT9_INTKNTXFEMP_LSB 0x4
+#define GC_USB_DIEPINT9_INTKNTXFEMP_MASK 0x10
+#define GC_USB_DIEPINT9_INTKNTXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT9_INTKNTXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT9_INTKNTXFEMP_OFFSET 0xa28
+#define GC_USB_DIEPINT9_INTKNEPMIS_LSB 0x5
+#define GC_USB_DIEPINT9_INTKNEPMIS_MASK 0x20
+#define GC_USB_DIEPINT9_INTKNEPMIS_SIZE 0x1
+#define GC_USB_DIEPINT9_INTKNEPMIS_DEFAULT 0x0
+#define GC_USB_DIEPINT9_INTKNEPMIS_OFFSET 0xa28
+#define GC_USB_DIEPINT9_INEPNAKEFF_LSB 0x6
+#define GC_USB_DIEPINT9_INEPNAKEFF_MASK 0x40
+#define GC_USB_DIEPINT9_INEPNAKEFF_SIZE 0x1
+#define GC_USB_DIEPINT9_INEPNAKEFF_DEFAULT 0x0
+#define GC_USB_DIEPINT9_INEPNAKEFF_OFFSET 0xa28
+#define GC_USB_DIEPINT9_TXFEMP_LSB 0x7
+#define GC_USB_DIEPINT9_TXFEMP_MASK 0x80
+#define GC_USB_DIEPINT9_TXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT9_TXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT9_TXFEMP_OFFSET 0xa28
+#define GC_USB_DIEPINT9_TXFIFOUNDRN_LSB 0x8
+#define GC_USB_DIEPINT9_TXFIFOUNDRN_MASK 0x100
+#define GC_USB_DIEPINT9_TXFIFOUNDRN_SIZE 0x1
+#define GC_USB_DIEPINT9_TXFIFOUNDRN_DEFAULT 0x0
+#define GC_USB_DIEPINT9_TXFIFOUNDRN_OFFSET 0xa28
+#define GC_USB_DIEPINT9_BNAINTR_LSB 0x9
+#define GC_USB_DIEPINT9_BNAINTR_MASK 0x200
+#define GC_USB_DIEPINT9_BNAINTR_SIZE 0x1
+#define GC_USB_DIEPINT9_BNAINTR_DEFAULT 0x0
+#define GC_USB_DIEPINT9_BNAINTR_OFFSET 0xa28
+#define GC_USB_DIEPINT9_PKTDRPSTS_LSB 0xb
+#define GC_USB_DIEPINT9_PKTDRPSTS_MASK 0x800
+#define GC_USB_DIEPINT9_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DIEPINT9_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DIEPINT9_PKTDRPSTS_OFFSET 0xa28
+#define GC_USB_DIEPINT9_BBLEERR_LSB 0xc
+#define GC_USB_DIEPINT9_BBLEERR_MASK 0x1000
+#define GC_USB_DIEPINT9_BBLEERR_SIZE 0x1
+#define GC_USB_DIEPINT9_BBLEERR_DEFAULT 0x0
+#define GC_USB_DIEPINT9_BBLEERR_OFFSET 0xa28
+#define GC_USB_DIEPINT9_NAKINTRPT_LSB 0xd
+#define GC_USB_DIEPINT9_NAKINTRPT_MASK 0x2000
+#define GC_USB_DIEPINT9_NAKINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT9_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT9_NAKINTRPT_OFFSET 0xa28
+#define GC_USB_DIEPINT9_NYETINTRPT_LSB 0xe
+#define GC_USB_DIEPINT9_NYETINTRPT_MASK 0x4000
+#define GC_USB_DIEPINT9_NYETINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT9_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT9_NYETINTRPT_OFFSET 0xa28
+#define GC_USB_DIEPTSIZ9_XFERSIZE_LSB 0x0
+#define GC_USB_DIEPTSIZ9_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DIEPTSIZ9_XFERSIZE_SIZE 0x13
+#define GC_USB_DIEPTSIZ9_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ9_XFERSIZE_OFFSET 0xa30
+#define GC_USB_DIEPTSIZ9_PKTCNT_LSB 0x13
+#define GC_USB_DIEPTSIZ9_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DIEPTSIZ9_PKTCNT_SIZE 0xa
+#define GC_USB_DIEPTSIZ9_PKTCNT_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ9_PKTCNT_OFFSET 0xa30
+#define GC_USB_DIEPTSIZ9_MC_LSB 0x1d
+#define GC_USB_DIEPTSIZ9_MC_MASK 0x60000000
+#define GC_USB_DIEPTSIZ9_MC_SIZE 0x2
+#define GC_USB_DIEPTSIZ9_MC_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ9_MC_OFFSET 0xa30
+#define GC_USB_DIEPDMA9_DMAADDR_LSB 0x0
+#define GC_USB_DIEPDMA9_DMAADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMA9_DMAADDR_SIZE 0x20
+#define GC_USB_DIEPDMA9_DMAADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMA9_DMAADDR_OFFSET 0xa34
+#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_LSB 0x0
+#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_MASK 0xffff
+#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_SIZE 0x10
+#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_DEFAULT 0x0
+#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_OFFSET 0xa38
+#define GC_USB_DIEPDMAB9_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DIEPDMAB9_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMAB9_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DIEPDMAB9_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMAB9_DMABUFFERADDR_OFFSET 0xa3c
+#define GC_USB_DIEPCTL10_MPS_LSB 0x0
+#define GC_USB_DIEPCTL10_MPS_MASK 0x7ff
+#define GC_USB_DIEPCTL10_MPS_SIZE 0xb
+#define GC_USB_DIEPCTL10_MPS_DEFAULT 0x0
+#define GC_USB_DIEPCTL10_MPS_OFFSET 0xa40
+#define GC_USB_DIEPCTL10_USBACTEP_LSB 0xf
+#define GC_USB_DIEPCTL10_USBACTEP_MASK 0x8000
+#define GC_USB_DIEPCTL10_USBACTEP_SIZE 0x1
+#define GC_USB_DIEPCTL10_USBACTEP_DEFAULT 0x0
+#define GC_USB_DIEPCTL10_USBACTEP_OFFSET 0xa40
+#define GC_USB_DIEPCTL10_DPID_LSB 0x10
+#define GC_USB_DIEPCTL10_DPID_MASK 0x10000
+#define GC_USB_DIEPCTL10_DPID_SIZE 0x1
+#define GC_USB_DIEPCTL10_DPID_DEFAULT 0x0
+#define GC_USB_DIEPCTL10_DPID_OFFSET 0xa40
+#define GC_USB_DIEPCTL10_NAKSTS_LSB 0x11
+#define GC_USB_DIEPCTL10_NAKSTS_MASK 0x20000
+#define GC_USB_DIEPCTL10_NAKSTS_SIZE 0x1
+#define GC_USB_DIEPCTL10_NAKSTS_DEFAULT 0x0
+#define GC_USB_DIEPCTL10_NAKSTS_OFFSET 0xa40
+#define GC_USB_DIEPCTL10_EPTYPE_LSB 0x12
+#define GC_USB_DIEPCTL10_EPTYPE_MASK 0xc0000
+#define GC_USB_DIEPCTL10_EPTYPE_SIZE 0x2
+#define GC_USB_DIEPCTL10_EPTYPE_DEFAULT 0x0
+#define GC_USB_DIEPCTL10_EPTYPE_OFFSET 0xa40
+#define GC_USB_DIEPCTL10_STALL_LSB 0x15
+#define GC_USB_DIEPCTL10_STALL_MASK 0x200000
+#define GC_USB_DIEPCTL10_STALL_SIZE 0x1
+#define GC_USB_DIEPCTL10_STALL_DEFAULT 0x0
+#define GC_USB_DIEPCTL10_STALL_OFFSET 0xa40
+#define GC_USB_DIEPCTL10_TXFNUM_LSB 0x16
+#define GC_USB_DIEPCTL10_TXFNUM_MASK 0x3c00000
+#define GC_USB_DIEPCTL10_TXFNUM_SIZE 0x4
+#define GC_USB_DIEPCTL10_TXFNUM_DEFAULT 0x0
+#define GC_USB_DIEPCTL10_TXFNUM_OFFSET 0xa40
+#define GC_USB_DIEPCTL10_CNAK_LSB 0x1a
+#define GC_USB_DIEPCTL10_CNAK_MASK 0x4000000
+#define GC_USB_DIEPCTL10_CNAK_SIZE 0x1
+#define GC_USB_DIEPCTL10_CNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL10_CNAK_OFFSET 0xa40
+#define GC_USB_DIEPCTL10_SNAK_LSB 0x1b
+#define GC_USB_DIEPCTL10_SNAK_MASK 0x8000000
+#define GC_USB_DIEPCTL10_SNAK_SIZE 0x1
+#define GC_USB_DIEPCTL10_SNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL10_SNAK_OFFSET 0xa40
+#define GC_USB_DIEPCTL10_SETD0PID_LSB 0x1c
+#define GC_USB_DIEPCTL10_SETD0PID_MASK 0x10000000
+#define GC_USB_DIEPCTL10_SETD0PID_SIZE 0x1
+#define GC_USB_DIEPCTL10_SETD0PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL10_SETD0PID_OFFSET 0xa40
+#define GC_USB_DIEPCTL10_SETD1PID_LSB 0x1d
+#define GC_USB_DIEPCTL10_SETD1PID_MASK 0x20000000
+#define GC_USB_DIEPCTL10_SETD1PID_SIZE 0x1
+#define GC_USB_DIEPCTL10_SETD1PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL10_SETD1PID_OFFSET 0xa40
+#define GC_USB_DIEPCTL10_EPDIS_LSB 0x1e
+#define GC_USB_DIEPCTL10_EPDIS_MASK 0x40000000
+#define GC_USB_DIEPCTL10_EPDIS_SIZE 0x1
+#define GC_USB_DIEPCTL10_EPDIS_DEFAULT 0x0
+#define GC_USB_DIEPCTL10_EPDIS_OFFSET 0xa40
+#define GC_USB_DIEPCTL10_EPENA_LSB 0x1f
+#define GC_USB_DIEPCTL10_EPENA_MASK 0x80000000
+#define GC_USB_DIEPCTL10_EPENA_SIZE 0x1
+#define GC_USB_DIEPCTL10_EPENA_DEFAULT 0x0
+#define GC_USB_DIEPCTL10_EPENA_OFFSET 0xa40
+#define GC_USB_DIEPINT10_XFERCOMPL_LSB 0x0
+#define GC_USB_DIEPINT10_XFERCOMPL_MASK 0x1
+#define GC_USB_DIEPINT10_XFERCOMPL_SIZE 0x1
+#define GC_USB_DIEPINT10_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DIEPINT10_XFERCOMPL_OFFSET 0xa48
+#define GC_USB_DIEPINT10_EPDISBLD_LSB 0x1
+#define GC_USB_DIEPINT10_EPDISBLD_MASK 0x2
+#define GC_USB_DIEPINT10_EPDISBLD_SIZE 0x1
+#define GC_USB_DIEPINT10_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DIEPINT10_EPDISBLD_OFFSET 0xa48
+#define GC_USB_DIEPINT10_AHBERR_LSB 0x2
+#define GC_USB_DIEPINT10_AHBERR_MASK 0x4
+#define GC_USB_DIEPINT10_AHBERR_SIZE 0x1
+#define GC_USB_DIEPINT10_AHBERR_DEFAULT 0x0
+#define GC_USB_DIEPINT10_AHBERR_OFFSET 0xa48
+#define GC_USB_DIEPINT10_TIMEOUT_LSB 0x3
+#define GC_USB_DIEPINT10_TIMEOUT_MASK 0x8
+#define GC_USB_DIEPINT10_TIMEOUT_SIZE 0x1
+#define GC_USB_DIEPINT10_TIMEOUT_DEFAULT 0x0
+#define GC_USB_DIEPINT10_TIMEOUT_OFFSET 0xa48
+#define GC_USB_DIEPINT10_INTKNTXFEMP_LSB 0x4
+#define GC_USB_DIEPINT10_INTKNTXFEMP_MASK 0x10
+#define GC_USB_DIEPINT10_INTKNTXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT10_INTKNTXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT10_INTKNTXFEMP_OFFSET 0xa48
+#define GC_USB_DIEPINT10_INTKNEPMIS_LSB 0x5
+#define GC_USB_DIEPINT10_INTKNEPMIS_MASK 0x20
+#define GC_USB_DIEPINT10_INTKNEPMIS_SIZE 0x1
+#define GC_USB_DIEPINT10_INTKNEPMIS_DEFAULT 0x0
+#define GC_USB_DIEPINT10_INTKNEPMIS_OFFSET 0xa48
+#define GC_USB_DIEPINT10_INEPNAKEFF_LSB 0x6
+#define GC_USB_DIEPINT10_INEPNAKEFF_MASK 0x40
+#define GC_USB_DIEPINT10_INEPNAKEFF_SIZE 0x1
+#define GC_USB_DIEPINT10_INEPNAKEFF_DEFAULT 0x0
+#define GC_USB_DIEPINT10_INEPNAKEFF_OFFSET 0xa48
+#define GC_USB_DIEPINT10_TXFEMP_LSB 0x7
+#define GC_USB_DIEPINT10_TXFEMP_MASK 0x80
+#define GC_USB_DIEPINT10_TXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT10_TXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT10_TXFEMP_OFFSET 0xa48
+#define GC_USB_DIEPINT10_TXFIFOUNDRN_LSB 0x8
+#define GC_USB_DIEPINT10_TXFIFOUNDRN_MASK 0x100
+#define GC_USB_DIEPINT10_TXFIFOUNDRN_SIZE 0x1
+#define GC_USB_DIEPINT10_TXFIFOUNDRN_DEFAULT 0x0
+#define GC_USB_DIEPINT10_TXFIFOUNDRN_OFFSET 0xa48
+#define GC_USB_DIEPINT10_BNAINTR_LSB 0x9
+#define GC_USB_DIEPINT10_BNAINTR_MASK 0x200
+#define GC_USB_DIEPINT10_BNAINTR_SIZE 0x1
+#define GC_USB_DIEPINT10_BNAINTR_DEFAULT 0x0
+#define GC_USB_DIEPINT10_BNAINTR_OFFSET 0xa48
+#define GC_USB_DIEPINT10_PKTDRPSTS_LSB 0xb
+#define GC_USB_DIEPINT10_PKTDRPSTS_MASK 0x800
+#define GC_USB_DIEPINT10_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DIEPINT10_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DIEPINT10_PKTDRPSTS_OFFSET 0xa48
+#define GC_USB_DIEPINT10_BBLEERR_LSB 0xc
+#define GC_USB_DIEPINT10_BBLEERR_MASK 0x1000
+#define GC_USB_DIEPINT10_BBLEERR_SIZE 0x1
+#define GC_USB_DIEPINT10_BBLEERR_DEFAULT 0x0
+#define GC_USB_DIEPINT10_BBLEERR_OFFSET 0xa48
+#define GC_USB_DIEPINT10_NAKINTRPT_LSB 0xd
+#define GC_USB_DIEPINT10_NAKINTRPT_MASK 0x2000
+#define GC_USB_DIEPINT10_NAKINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT10_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT10_NAKINTRPT_OFFSET 0xa48
+#define GC_USB_DIEPINT10_NYETINTRPT_LSB 0xe
+#define GC_USB_DIEPINT10_NYETINTRPT_MASK 0x4000
+#define GC_USB_DIEPINT10_NYETINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT10_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT10_NYETINTRPT_OFFSET 0xa48
+#define GC_USB_DIEPTSIZ10_XFERSIZE_LSB 0x0
+#define GC_USB_DIEPTSIZ10_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DIEPTSIZ10_XFERSIZE_SIZE 0x13
+#define GC_USB_DIEPTSIZ10_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ10_XFERSIZE_OFFSET 0xa50
+#define GC_USB_DIEPTSIZ10_PKTCNT_LSB 0x13
+#define GC_USB_DIEPTSIZ10_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DIEPTSIZ10_PKTCNT_SIZE 0xa
+#define GC_USB_DIEPTSIZ10_PKTCNT_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ10_PKTCNT_OFFSET 0xa50
+#define GC_USB_DIEPTSIZ10_MC_LSB 0x1d
+#define GC_USB_DIEPTSIZ10_MC_MASK 0x60000000
+#define GC_USB_DIEPTSIZ10_MC_SIZE 0x2
+#define GC_USB_DIEPTSIZ10_MC_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ10_MC_OFFSET 0xa50
+#define GC_USB_DIEPDMA10_DMAADDR_LSB 0x0
+#define GC_USB_DIEPDMA10_DMAADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMA10_DMAADDR_SIZE 0x20
+#define GC_USB_DIEPDMA10_DMAADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMA10_DMAADDR_OFFSET 0xa54
+#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_LSB 0x0
+#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_MASK 0xffff
+#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_SIZE 0x10
 #define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_DEFAULT 0x0
-#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_OFFSET  0xa58
-#define GC_USB_DIEPDMAB10_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DIEPDMAB10_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DIEPDMAB10_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DIEPDMAB10_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DIEPDMAB10_DMABUFFERADDR_OFFSET   0xa5c
-#define GC_USB_DIEPCTL11_MPS_LSB                 0x0
-#define GC_USB_DIEPCTL11_MPS_MASK                0x7ff
-#define GC_USB_DIEPCTL11_MPS_SIZE                0xb
-#define GC_USB_DIEPCTL11_MPS_DEFAULT             0x0
-#define GC_USB_DIEPCTL11_MPS_OFFSET              0xa60
-#define GC_USB_DIEPCTL11_USBACTEP_LSB            0xf
-#define GC_USB_DIEPCTL11_USBACTEP_MASK           0x8000
-#define GC_USB_DIEPCTL11_USBACTEP_SIZE           0x1
-#define GC_USB_DIEPCTL11_USBACTEP_DEFAULT        0x0
-#define GC_USB_DIEPCTL11_USBACTEP_OFFSET         0xa60
-#define GC_USB_DIEPCTL11_DPID_LSB                0x10
-#define GC_USB_DIEPCTL11_DPID_MASK               0x10000
-#define GC_USB_DIEPCTL11_DPID_SIZE               0x1
-#define GC_USB_DIEPCTL11_DPID_DEFAULT            0x0
-#define GC_USB_DIEPCTL11_DPID_OFFSET             0xa60
-#define GC_USB_DIEPCTL11_NAKSTS_LSB              0x11
-#define GC_USB_DIEPCTL11_NAKSTS_MASK             0x20000
-#define GC_USB_DIEPCTL11_NAKSTS_SIZE             0x1
-#define GC_USB_DIEPCTL11_NAKSTS_DEFAULT          0x0
-#define GC_USB_DIEPCTL11_NAKSTS_OFFSET           0xa60
-#define GC_USB_DIEPCTL11_EPTYPE_LSB              0x12
-#define GC_USB_DIEPCTL11_EPTYPE_MASK             0xc0000
-#define GC_USB_DIEPCTL11_EPTYPE_SIZE             0x2
-#define GC_USB_DIEPCTL11_EPTYPE_DEFAULT          0x0
-#define GC_USB_DIEPCTL11_EPTYPE_OFFSET           0xa60
-#define GC_USB_DIEPCTL11_STALL_LSB               0x15
-#define GC_USB_DIEPCTL11_STALL_MASK              0x200000
-#define GC_USB_DIEPCTL11_STALL_SIZE              0x1
-#define GC_USB_DIEPCTL11_STALL_DEFAULT           0x0
-#define GC_USB_DIEPCTL11_STALL_OFFSET            0xa60
-#define GC_USB_DIEPCTL11_TXFNUM_LSB              0x16
-#define GC_USB_DIEPCTL11_TXFNUM_MASK             0x3c00000
-#define GC_USB_DIEPCTL11_TXFNUM_SIZE             0x4
-#define GC_USB_DIEPCTL11_TXFNUM_DEFAULT          0x0
-#define GC_USB_DIEPCTL11_TXFNUM_OFFSET           0xa60
-#define GC_USB_DIEPCTL11_CNAK_LSB                0x1a
-#define GC_USB_DIEPCTL11_CNAK_MASK               0x4000000
-#define GC_USB_DIEPCTL11_CNAK_SIZE               0x1
-#define GC_USB_DIEPCTL11_CNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL11_CNAK_OFFSET             0xa60
-#define GC_USB_DIEPCTL11_SNAK_LSB                0x1b
-#define GC_USB_DIEPCTL11_SNAK_MASK               0x8000000
-#define GC_USB_DIEPCTL11_SNAK_SIZE               0x1
-#define GC_USB_DIEPCTL11_SNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL11_SNAK_OFFSET             0xa60
-#define GC_USB_DIEPCTL11_SETD0PID_LSB            0x1c
-#define GC_USB_DIEPCTL11_SETD0PID_MASK           0x10000000
-#define GC_USB_DIEPCTL11_SETD0PID_SIZE           0x1
-#define GC_USB_DIEPCTL11_SETD0PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL11_SETD0PID_OFFSET         0xa60
-#define GC_USB_DIEPCTL11_SETD1PID_LSB            0x1d
-#define GC_USB_DIEPCTL11_SETD1PID_MASK           0x20000000
-#define GC_USB_DIEPCTL11_SETD1PID_SIZE           0x1
-#define GC_USB_DIEPCTL11_SETD1PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL11_SETD1PID_OFFSET         0xa60
-#define GC_USB_DIEPCTL11_EPDIS_LSB               0x1e
-#define GC_USB_DIEPCTL11_EPDIS_MASK              0x40000000
-#define GC_USB_DIEPCTL11_EPDIS_SIZE              0x1
-#define GC_USB_DIEPCTL11_EPDIS_DEFAULT           0x0
-#define GC_USB_DIEPCTL11_EPDIS_OFFSET            0xa60
-#define GC_USB_DIEPCTL11_EPENA_LSB               0x1f
-#define GC_USB_DIEPCTL11_EPENA_MASK              0x80000000
-#define GC_USB_DIEPCTL11_EPENA_SIZE              0x1
-#define GC_USB_DIEPCTL11_EPENA_DEFAULT           0x0
-#define GC_USB_DIEPCTL11_EPENA_OFFSET            0xa60
-#define GC_USB_DIEPINT11_XFERCOMPL_LSB           0x0
-#define GC_USB_DIEPINT11_XFERCOMPL_MASK          0x1
-#define GC_USB_DIEPINT11_XFERCOMPL_SIZE          0x1
-#define GC_USB_DIEPINT11_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DIEPINT11_XFERCOMPL_OFFSET        0xa68
-#define GC_USB_DIEPINT11_EPDISBLD_LSB            0x1
-#define GC_USB_DIEPINT11_EPDISBLD_MASK           0x2
-#define GC_USB_DIEPINT11_EPDISBLD_SIZE           0x1
-#define GC_USB_DIEPINT11_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DIEPINT11_EPDISBLD_OFFSET         0xa68
-#define GC_USB_DIEPINT11_AHBERR_LSB              0x2
-#define GC_USB_DIEPINT11_AHBERR_MASK             0x4
-#define GC_USB_DIEPINT11_AHBERR_SIZE             0x1
-#define GC_USB_DIEPINT11_AHBERR_DEFAULT          0x0
-#define GC_USB_DIEPINT11_AHBERR_OFFSET           0xa68
-#define GC_USB_DIEPINT11_TIMEOUT_LSB             0x3
-#define GC_USB_DIEPINT11_TIMEOUT_MASK            0x8
-#define GC_USB_DIEPINT11_TIMEOUT_SIZE            0x1
-#define GC_USB_DIEPINT11_TIMEOUT_DEFAULT         0x0
-#define GC_USB_DIEPINT11_TIMEOUT_OFFSET          0xa68
-#define GC_USB_DIEPINT11_INTKNTXFEMP_LSB         0x4
-#define GC_USB_DIEPINT11_INTKNTXFEMP_MASK        0x10
-#define GC_USB_DIEPINT11_INTKNTXFEMP_SIZE        0x1
-#define GC_USB_DIEPINT11_INTKNTXFEMP_DEFAULT     0x0
-#define GC_USB_DIEPINT11_INTKNTXFEMP_OFFSET      0xa68
-#define GC_USB_DIEPINT11_INTKNEPMIS_LSB          0x5
-#define GC_USB_DIEPINT11_INTKNEPMIS_MASK         0x20
-#define GC_USB_DIEPINT11_INTKNEPMIS_SIZE         0x1
-#define GC_USB_DIEPINT11_INTKNEPMIS_DEFAULT      0x0
-#define GC_USB_DIEPINT11_INTKNEPMIS_OFFSET       0xa68
-#define GC_USB_DIEPINT11_INEPNAKEFF_LSB          0x6
-#define GC_USB_DIEPINT11_INEPNAKEFF_MASK         0x40
-#define GC_USB_DIEPINT11_INEPNAKEFF_SIZE         0x1
-#define GC_USB_DIEPINT11_INEPNAKEFF_DEFAULT      0x0
-#define GC_USB_DIEPINT11_INEPNAKEFF_OFFSET       0xa68
-#define GC_USB_DIEPINT11_TXFEMP_LSB              0x7
-#define GC_USB_DIEPINT11_TXFEMP_MASK             0x80
-#define GC_USB_DIEPINT11_TXFEMP_SIZE             0x1
-#define GC_USB_DIEPINT11_TXFEMP_DEFAULT          0x0
-#define GC_USB_DIEPINT11_TXFEMP_OFFSET           0xa68
-#define GC_USB_DIEPINT11_TXFIFOUNDRN_LSB         0x8
-#define GC_USB_DIEPINT11_TXFIFOUNDRN_MASK        0x100
-#define GC_USB_DIEPINT11_TXFIFOUNDRN_SIZE        0x1
-#define GC_USB_DIEPINT11_TXFIFOUNDRN_DEFAULT     0x0
-#define GC_USB_DIEPINT11_TXFIFOUNDRN_OFFSET      0xa68
-#define GC_USB_DIEPINT11_BNAINTR_LSB             0x9
-#define GC_USB_DIEPINT11_BNAINTR_MASK            0x200
-#define GC_USB_DIEPINT11_BNAINTR_SIZE            0x1
-#define GC_USB_DIEPINT11_BNAINTR_DEFAULT         0x0
-#define GC_USB_DIEPINT11_BNAINTR_OFFSET          0xa68
-#define GC_USB_DIEPINT11_PKTDRPSTS_LSB           0xb
-#define GC_USB_DIEPINT11_PKTDRPSTS_MASK          0x800
-#define GC_USB_DIEPINT11_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DIEPINT11_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DIEPINT11_PKTDRPSTS_OFFSET        0xa68
-#define GC_USB_DIEPINT11_BBLEERR_LSB             0xc
-#define GC_USB_DIEPINT11_BBLEERR_MASK            0x1000
-#define GC_USB_DIEPINT11_BBLEERR_SIZE            0x1
-#define GC_USB_DIEPINT11_BBLEERR_DEFAULT         0x0
-#define GC_USB_DIEPINT11_BBLEERR_OFFSET          0xa68
-#define GC_USB_DIEPINT11_NAKINTRPT_LSB           0xd
-#define GC_USB_DIEPINT11_NAKINTRPT_MASK          0x2000
-#define GC_USB_DIEPINT11_NAKINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT11_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT11_NAKINTRPT_OFFSET        0xa68
-#define GC_USB_DIEPINT11_NYETINTRPT_LSB          0xe
-#define GC_USB_DIEPINT11_NYETINTRPT_MASK         0x4000
-#define GC_USB_DIEPINT11_NYETINTRPT_SIZE         0x1
-#define GC_USB_DIEPINT11_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DIEPINT11_NYETINTRPT_OFFSET       0xa68
-#define GC_USB_DIEPTSIZ11_XFERSIZE_LSB           0x0
-#define GC_USB_DIEPTSIZ11_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DIEPTSIZ11_XFERSIZE_SIZE          0x13
-#define GC_USB_DIEPTSIZ11_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DIEPTSIZ11_XFERSIZE_OFFSET        0xa70
-#define GC_USB_DIEPTSIZ11_PKTCNT_LSB             0x13
-#define GC_USB_DIEPTSIZ11_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DIEPTSIZ11_PKTCNT_SIZE            0xa
-#define GC_USB_DIEPTSIZ11_PKTCNT_DEFAULT         0x0
-#define GC_USB_DIEPTSIZ11_PKTCNT_OFFSET          0xa70
-#define GC_USB_DIEPTSIZ11_MC_LSB                 0x1d
-#define GC_USB_DIEPTSIZ11_MC_MASK                0x60000000
-#define GC_USB_DIEPTSIZ11_MC_SIZE                0x2
-#define GC_USB_DIEPTSIZ11_MC_DEFAULT             0x0
-#define GC_USB_DIEPTSIZ11_MC_OFFSET              0xa70
-#define GC_USB_DIEPDMA11_DMAADDR_LSB             0x0
-#define GC_USB_DIEPDMA11_DMAADDR_MASK            0xffffffff
-#define GC_USB_DIEPDMA11_DMAADDR_SIZE            0x20
-#define GC_USB_DIEPDMA11_DMAADDR_DEFAULT         0x0
-#define GC_USB_DIEPDMA11_DMAADDR_OFFSET          0xa74
-#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_LSB     0x0
-#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_MASK    0xffff
-#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_SIZE    0x10
+#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_OFFSET 0xa58
+#define GC_USB_DIEPDMAB10_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DIEPDMAB10_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMAB10_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DIEPDMAB10_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMAB10_DMABUFFERADDR_OFFSET 0xa5c
+#define GC_USB_DIEPCTL11_MPS_LSB 0x0
+#define GC_USB_DIEPCTL11_MPS_MASK 0x7ff
+#define GC_USB_DIEPCTL11_MPS_SIZE 0xb
+#define GC_USB_DIEPCTL11_MPS_DEFAULT 0x0
+#define GC_USB_DIEPCTL11_MPS_OFFSET 0xa60
+#define GC_USB_DIEPCTL11_USBACTEP_LSB 0xf
+#define GC_USB_DIEPCTL11_USBACTEP_MASK 0x8000
+#define GC_USB_DIEPCTL11_USBACTEP_SIZE 0x1
+#define GC_USB_DIEPCTL11_USBACTEP_DEFAULT 0x0
+#define GC_USB_DIEPCTL11_USBACTEP_OFFSET 0xa60
+#define GC_USB_DIEPCTL11_DPID_LSB 0x10
+#define GC_USB_DIEPCTL11_DPID_MASK 0x10000
+#define GC_USB_DIEPCTL11_DPID_SIZE 0x1
+#define GC_USB_DIEPCTL11_DPID_DEFAULT 0x0
+#define GC_USB_DIEPCTL11_DPID_OFFSET 0xa60
+#define GC_USB_DIEPCTL11_NAKSTS_LSB 0x11
+#define GC_USB_DIEPCTL11_NAKSTS_MASK 0x20000
+#define GC_USB_DIEPCTL11_NAKSTS_SIZE 0x1
+#define GC_USB_DIEPCTL11_NAKSTS_DEFAULT 0x0
+#define GC_USB_DIEPCTL11_NAKSTS_OFFSET 0xa60
+#define GC_USB_DIEPCTL11_EPTYPE_LSB 0x12
+#define GC_USB_DIEPCTL11_EPTYPE_MASK 0xc0000
+#define GC_USB_DIEPCTL11_EPTYPE_SIZE 0x2
+#define GC_USB_DIEPCTL11_EPTYPE_DEFAULT 0x0
+#define GC_USB_DIEPCTL11_EPTYPE_OFFSET 0xa60
+#define GC_USB_DIEPCTL11_STALL_LSB 0x15
+#define GC_USB_DIEPCTL11_STALL_MASK 0x200000
+#define GC_USB_DIEPCTL11_STALL_SIZE 0x1
+#define GC_USB_DIEPCTL11_STALL_DEFAULT 0x0
+#define GC_USB_DIEPCTL11_STALL_OFFSET 0xa60
+#define GC_USB_DIEPCTL11_TXFNUM_LSB 0x16
+#define GC_USB_DIEPCTL11_TXFNUM_MASK 0x3c00000
+#define GC_USB_DIEPCTL11_TXFNUM_SIZE 0x4
+#define GC_USB_DIEPCTL11_TXFNUM_DEFAULT 0x0
+#define GC_USB_DIEPCTL11_TXFNUM_OFFSET 0xa60
+#define GC_USB_DIEPCTL11_CNAK_LSB 0x1a
+#define GC_USB_DIEPCTL11_CNAK_MASK 0x4000000
+#define GC_USB_DIEPCTL11_CNAK_SIZE 0x1
+#define GC_USB_DIEPCTL11_CNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL11_CNAK_OFFSET 0xa60
+#define GC_USB_DIEPCTL11_SNAK_LSB 0x1b
+#define GC_USB_DIEPCTL11_SNAK_MASK 0x8000000
+#define GC_USB_DIEPCTL11_SNAK_SIZE 0x1
+#define GC_USB_DIEPCTL11_SNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL11_SNAK_OFFSET 0xa60
+#define GC_USB_DIEPCTL11_SETD0PID_LSB 0x1c
+#define GC_USB_DIEPCTL11_SETD0PID_MASK 0x10000000
+#define GC_USB_DIEPCTL11_SETD0PID_SIZE 0x1
+#define GC_USB_DIEPCTL11_SETD0PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL11_SETD0PID_OFFSET 0xa60
+#define GC_USB_DIEPCTL11_SETD1PID_LSB 0x1d
+#define GC_USB_DIEPCTL11_SETD1PID_MASK 0x20000000
+#define GC_USB_DIEPCTL11_SETD1PID_SIZE 0x1
+#define GC_USB_DIEPCTL11_SETD1PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL11_SETD1PID_OFFSET 0xa60
+#define GC_USB_DIEPCTL11_EPDIS_LSB 0x1e
+#define GC_USB_DIEPCTL11_EPDIS_MASK 0x40000000
+#define GC_USB_DIEPCTL11_EPDIS_SIZE 0x1
+#define GC_USB_DIEPCTL11_EPDIS_DEFAULT 0x0
+#define GC_USB_DIEPCTL11_EPDIS_OFFSET 0xa60
+#define GC_USB_DIEPCTL11_EPENA_LSB 0x1f
+#define GC_USB_DIEPCTL11_EPENA_MASK 0x80000000
+#define GC_USB_DIEPCTL11_EPENA_SIZE 0x1
+#define GC_USB_DIEPCTL11_EPENA_DEFAULT 0x0
+#define GC_USB_DIEPCTL11_EPENA_OFFSET 0xa60
+#define GC_USB_DIEPINT11_XFERCOMPL_LSB 0x0
+#define GC_USB_DIEPINT11_XFERCOMPL_MASK 0x1
+#define GC_USB_DIEPINT11_XFERCOMPL_SIZE 0x1
+#define GC_USB_DIEPINT11_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DIEPINT11_XFERCOMPL_OFFSET 0xa68
+#define GC_USB_DIEPINT11_EPDISBLD_LSB 0x1
+#define GC_USB_DIEPINT11_EPDISBLD_MASK 0x2
+#define GC_USB_DIEPINT11_EPDISBLD_SIZE 0x1
+#define GC_USB_DIEPINT11_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DIEPINT11_EPDISBLD_OFFSET 0xa68
+#define GC_USB_DIEPINT11_AHBERR_LSB 0x2
+#define GC_USB_DIEPINT11_AHBERR_MASK 0x4
+#define GC_USB_DIEPINT11_AHBERR_SIZE 0x1
+#define GC_USB_DIEPINT11_AHBERR_DEFAULT 0x0
+#define GC_USB_DIEPINT11_AHBERR_OFFSET 0xa68
+#define GC_USB_DIEPINT11_TIMEOUT_LSB 0x3
+#define GC_USB_DIEPINT11_TIMEOUT_MASK 0x8
+#define GC_USB_DIEPINT11_TIMEOUT_SIZE 0x1
+#define GC_USB_DIEPINT11_TIMEOUT_DEFAULT 0x0
+#define GC_USB_DIEPINT11_TIMEOUT_OFFSET 0xa68
+#define GC_USB_DIEPINT11_INTKNTXFEMP_LSB 0x4
+#define GC_USB_DIEPINT11_INTKNTXFEMP_MASK 0x10
+#define GC_USB_DIEPINT11_INTKNTXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT11_INTKNTXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT11_INTKNTXFEMP_OFFSET 0xa68
+#define GC_USB_DIEPINT11_INTKNEPMIS_LSB 0x5
+#define GC_USB_DIEPINT11_INTKNEPMIS_MASK 0x20
+#define GC_USB_DIEPINT11_INTKNEPMIS_SIZE 0x1
+#define GC_USB_DIEPINT11_INTKNEPMIS_DEFAULT 0x0
+#define GC_USB_DIEPINT11_INTKNEPMIS_OFFSET 0xa68
+#define GC_USB_DIEPINT11_INEPNAKEFF_LSB 0x6
+#define GC_USB_DIEPINT11_INEPNAKEFF_MASK 0x40
+#define GC_USB_DIEPINT11_INEPNAKEFF_SIZE 0x1
+#define GC_USB_DIEPINT11_INEPNAKEFF_DEFAULT 0x0
+#define GC_USB_DIEPINT11_INEPNAKEFF_OFFSET 0xa68
+#define GC_USB_DIEPINT11_TXFEMP_LSB 0x7
+#define GC_USB_DIEPINT11_TXFEMP_MASK 0x80
+#define GC_USB_DIEPINT11_TXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT11_TXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT11_TXFEMP_OFFSET 0xa68
+#define GC_USB_DIEPINT11_TXFIFOUNDRN_LSB 0x8
+#define GC_USB_DIEPINT11_TXFIFOUNDRN_MASK 0x100
+#define GC_USB_DIEPINT11_TXFIFOUNDRN_SIZE 0x1
+#define GC_USB_DIEPINT11_TXFIFOUNDRN_DEFAULT 0x0
+#define GC_USB_DIEPINT11_TXFIFOUNDRN_OFFSET 0xa68
+#define GC_USB_DIEPINT11_BNAINTR_LSB 0x9
+#define GC_USB_DIEPINT11_BNAINTR_MASK 0x200
+#define GC_USB_DIEPINT11_BNAINTR_SIZE 0x1
+#define GC_USB_DIEPINT11_BNAINTR_DEFAULT 0x0
+#define GC_USB_DIEPINT11_BNAINTR_OFFSET 0xa68
+#define GC_USB_DIEPINT11_PKTDRPSTS_LSB 0xb
+#define GC_USB_DIEPINT11_PKTDRPSTS_MASK 0x800
+#define GC_USB_DIEPINT11_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DIEPINT11_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DIEPINT11_PKTDRPSTS_OFFSET 0xa68
+#define GC_USB_DIEPINT11_BBLEERR_LSB 0xc
+#define GC_USB_DIEPINT11_BBLEERR_MASK 0x1000
+#define GC_USB_DIEPINT11_BBLEERR_SIZE 0x1
+#define GC_USB_DIEPINT11_BBLEERR_DEFAULT 0x0
+#define GC_USB_DIEPINT11_BBLEERR_OFFSET 0xa68
+#define GC_USB_DIEPINT11_NAKINTRPT_LSB 0xd
+#define GC_USB_DIEPINT11_NAKINTRPT_MASK 0x2000
+#define GC_USB_DIEPINT11_NAKINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT11_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT11_NAKINTRPT_OFFSET 0xa68
+#define GC_USB_DIEPINT11_NYETINTRPT_LSB 0xe
+#define GC_USB_DIEPINT11_NYETINTRPT_MASK 0x4000
+#define GC_USB_DIEPINT11_NYETINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT11_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT11_NYETINTRPT_OFFSET 0xa68
+#define GC_USB_DIEPTSIZ11_XFERSIZE_LSB 0x0
+#define GC_USB_DIEPTSIZ11_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DIEPTSIZ11_XFERSIZE_SIZE 0x13
+#define GC_USB_DIEPTSIZ11_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ11_XFERSIZE_OFFSET 0xa70
+#define GC_USB_DIEPTSIZ11_PKTCNT_LSB 0x13
+#define GC_USB_DIEPTSIZ11_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DIEPTSIZ11_PKTCNT_SIZE 0xa
+#define GC_USB_DIEPTSIZ11_PKTCNT_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ11_PKTCNT_OFFSET 0xa70
+#define GC_USB_DIEPTSIZ11_MC_LSB 0x1d
+#define GC_USB_DIEPTSIZ11_MC_MASK 0x60000000
+#define GC_USB_DIEPTSIZ11_MC_SIZE 0x2
+#define GC_USB_DIEPTSIZ11_MC_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ11_MC_OFFSET 0xa70
+#define GC_USB_DIEPDMA11_DMAADDR_LSB 0x0
+#define GC_USB_DIEPDMA11_DMAADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMA11_DMAADDR_SIZE 0x20
+#define GC_USB_DIEPDMA11_DMAADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMA11_DMAADDR_OFFSET 0xa74
+#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_LSB 0x0
+#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_MASK 0xffff
+#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_SIZE 0x10
 #define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_DEFAULT 0x0
-#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_OFFSET  0xa78
-#define GC_USB_DIEPDMAB11_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DIEPDMAB11_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DIEPDMAB11_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DIEPDMAB11_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DIEPDMAB11_DMABUFFERADDR_OFFSET   0xa7c
-#define GC_USB_DIEPCTL12_MPS_LSB                 0x0
-#define GC_USB_DIEPCTL12_MPS_MASK                0x7ff
-#define GC_USB_DIEPCTL12_MPS_SIZE                0xb
-#define GC_USB_DIEPCTL12_MPS_DEFAULT             0x0
-#define GC_USB_DIEPCTL12_MPS_OFFSET              0xa80
-#define GC_USB_DIEPCTL12_USBACTEP_LSB            0xf
-#define GC_USB_DIEPCTL12_USBACTEP_MASK           0x8000
-#define GC_USB_DIEPCTL12_USBACTEP_SIZE           0x1
-#define GC_USB_DIEPCTL12_USBACTEP_DEFAULT        0x0
-#define GC_USB_DIEPCTL12_USBACTEP_OFFSET         0xa80
-#define GC_USB_DIEPCTL12_DPID_LSB                0x10
-#define GC_USB_DIEPCTL12_DPID_MASK               0x10000
-#define GC_USB_DIEPCTL12_DPID_SIZE               0x1
-#define GC_USB_DIEPCTL12_DPID_DEFAULT            0x0
-#define GC_USB_DIEPCTL12_DPID_OFFSET             0xa80
-#define GC_USB_DIEPCTL12_NAKSTS_LSB              0x11
-#define GC_USB_DIEPCTL12_NAKSTS_MASK             0x20000
-#define GC_USB_DIEPCTL12_NAKSTS_SIZE             0x1
-#define GC_USB_DIEPCTL12_NAKSTS_DEFAULT          0x0
-#define GC_USB_DIEPCTL12_NAKSTS_OFFSET           0xa80
-#define GC_USB_DIEPCTL12_EPTYPE_LSB              0x12
-#define GC_USB_DIEPCTL12_EPTYPE_MASK             0xc0000
-#define GC_USB_DIEPCTL12_EPTYPE_SIZE             0x2
-#define GC_USB_DIEPCTL12_EPTYPE_DEFAULT          0x0
-#define GC_USB_DIEPCTL12_EPTYPE_OFFSET           0xa80
-#define GC_USB_DIEPCTL12_STALL_LSB               0x15
-#define GC_USB_DIEPCTL12_STALL_MASK              0x200000
-#define GC_USB_DIEPCTL12_STALL_SIZE              0x1
-#define GC_USB_DIEPCTL12_STALL_DEFAULT           0x0
-#define GC_USB_DIEPCTL12_STALL_OFFSET            0xa80
-#define GC_USB_DIEPCTL12_TXFNUM_LSB              0x16
-#define GC_USB_DIEPCTL12_TXFNUM_MASK             0x3c00000
-#define GC_USB_DIEPCTL12_TXFNUM_SIZE             0x4
-#define GC_USB_DIEPCTL12_TXFNUM_DEFAULT          0x0
-#define GC_USB_DIEPCTL12_TXFNUM_OFFSET           0xa80
-#define GC_USB_DIEPCTL12_CNAK_LSB                0x1a
-#define GC_USB_DIEPCTL12_CNAK_MASK               0x4000000
-#define GC_USB_DIEPCTL12_CNAK_SIZE               0x1
-#define GC_USB_DIEPCTL12_CNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL12_CNAK_OFFSET             0xa80
-#define GC_USB_DIEPCTL12_SNAK_LSB                0x1b
-#define GC_USB_DIEPCTL12_SNAK_MASK               0x8000000
-#define GC_USB_DIEPCTL12_SNAK_SIZE               0x1
-#define GC_USB_DIEPCTL12_SNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL12_SNAK_OFFSET             0xa80
-#define GC_USB_DIEPCTL12_SETD0PID_LSB            0x1c
-#define GC_USB_DIEPCTL12_SETD0PID_MASK           0x10000000
-#define GC_USB_DIEPCTL12_SETD0PID_SIZE           0x1
-#define GC_USB_DIEPCTL12_SETD0PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL12_SETD0PID_OFFSET         0xa80
-#define GC_USB_DIEPCTL12_SETD1PID_LSB            0x1d
-#define GC_USB_DIEPCTL12_SETD1PID_MASK           0x20000000
-#define GC_USB_DIEPCTL12_SETD1PID_SIZE           0x1
-#define GC_USB_DIEPCTL12_SETD1PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL12_SETD1PID_OFFSET         0xa80
-#define GC_USB_DIEPCTL12_EPDIS_LSB               0x1e
-#define GC_USB_DIEPCTL12_EPDIS_MASK              0x40000000
-#define GC_USB_DIEPCTL12_EPDIS_SIZE              0x1
-#define GC_USB_DIEPCTL12_EPDIS_DEFAULT           0x0
-#define GC_USB_DIEPCTL12_EPDIS_OFFSET            0xa80
-#define GC_USB_DIEPCTL12_EPENA_LSB               0x1f
-#define GC_USB_DIEPCTL12_EPENA_MASK              0x80000000
-#define GC_USB_DIEPCTL12_EPENA_SIZE              0x1
-#define GC_USB_DIEPCTL12_EPENA_DEFAULT           0x0
-#define GC_USB_DIEPCTL12_EPENA_OFFSET            0xa80
-#define GC_USB_DIEPINT12_XFERCOMPL_LSB           0x0
-#define GC_USB_DIEPINT12_XFERCOMPL_MASK          0x1
-#define GC_USB_DIEPINT12_XFERCOMPL_SIZE          0x1
-#define GC_USB_DIEPINT12_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DIEPINT12_XFERCOMPL_OFFSET        0xa88
-#define GC_USB_DIEPINT12_EPDISBLD_LSB            0x1
-#define GC_USB_DIEPINT12_EPDISBLD_MASK           0x2
-#define GC_USB_DIEPINT12_EPDISBLD_SIZE           0x1
-#define GC_USB_DIEPINT12_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DIEPINT12_EPDISBLD_OFFSET         0xa88
-#define GC_USB_DIEPINT12_AHBERR_LSB              0x2
-#define GC_USB_DIEPINT12_AHBERR_MASK             0x4
-#define GC_USB_DIEPINT12_AHBERR_SIZE             0x1
-#define GC_USB_DIEPINT12_AHBERR_DEFAULT          0x0
-#define GC_USB_DIEPINT12_AHBERR_OFFSET           0xa88
-#define GC_USB_DIEPINT12_TIMEOUT_LSB             0x3
-#define GC_USB_DIEPINT12_TIMEOUT_MASK            0x8
-#define GC_USB_DIEPINT12_TIMEOUT_SIZE            0x1
-#define GC_USB_DIEPINT12_TIMEOUT_DEFAULT         0x0
-#define GC_USB_DIEPINT12_TIMEOUT_OFFSET          0xa88
-#define GC_USB_DIEPINT12_INTKNTXFEMP_LSB         0x4
-#define GC_USB_DIEPINT12_INTKNTXFEMP_MASK        0x10
-#define GC_USB_DIEPINT12_INTKNTXFEMP_SIZE        0x1
-#define GC_USB_DIEPINT12_INTKNTXFEMP_DEFAULT     0x0
-#define GC_USB_DIEPINT12_INTKNTXFEMP_OFFSET      0xa88
-#define GC_USB_DIEPINT12_INTKNEPMIS_LSB          0x5
-#define GC_USB_DIEPINT12_INTKNEPMIS_MASK         0x20
-#define GC_USB_DIEPINT12_INTKNEPMIS_SIZE         0x1
-#define GC_USB_DIEPINT12_INTKNEPMIS_DEFAULT      0x0
-#define GC_USB_DIEPINT12_INTKNEPMIS_OFFSET       0xa88
-#define GC_USB_DIEPINT12_INEPNAKEFF_LSB          0x6
-#define GC_USB_DIEPINT12_INEPNAKEFF_MASK         0x40
-#define GC_USB_DIEPINT12_INEPNAKEFF_SIZE         0x1
-#define GC_USB_DIEPINT12_INEPNAKEFF_DEFAULT      0x0
-#define GC_USB_DIEPINT12_INEPNAKEFF_OFFSET       0xa88
-#define GC_USB_DIEPINT12_TXFEMP_LSB              0x7
-#define GC_USB_DIEPINT12_TXFEMP_MASK             0x80
-#define GC_USB_DIEPINT12_TXFEMP_SIZE             0x1
-#define GC_USB_DIEPINT12_TXFEMP_DEFAULT          0x0
-#define GC_USB_DIEPINT12_TXFEMP_OFFSET           0xa88
-#define GC_USB_DIEPINT12_TXFIFOUNDRN_LSB         0x8
-#define GC_USB_DIEPINT12_TXFIFOUNDRN_MASK        0x100
-#define GC_USB_DIEPINT12_TXFIFOUNDRN_SIZE        0x1
-#define GC_USB_DIEPINT12_TXFIFOUNDRN_DEFAULT     0x0
-#define GC_USB_DIEPINT12_TXFIFOUNDRN_OFFSET      0xa88
-#define GC_USB_DIEPINT12_BNAINTR_LSB             0x9
-#define GC_USB_DIEPINT12_BNAINTR_MASK            0x200
-#define GC_USB_DIEPINT12_BNAINTR_SIZE            0x1
-#define GC_USB_DIEPINT12_BNAINTR_DEFAULT         0x0
-#define GC_USB_DIEPINT12_BNAINTR_OFFSET          0xa88
-#define GC_USB_DIEPINT12_PKTDRPSTS_LSB           0xb
-#define GC_USB_DIEPINT12_PKTDRPSTS_MASK          0x800
-#define GC_USB_DIEPINT12_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DIEPINT12_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DIEPINT12_PKTDRPSTS_OFFSET        0xa88
-#define GC_USB_DIEPINT12_BBLEERR_LSB             0xc
-#define GC_USB_DIEPINT12_BBLEERR_MASK            0x1000
-#define GC_USB_DIEPINT12_BBLEERR_SIZE            0x1
-#define GC_USB_DIEPINT12_BBLEERR_DEFAULT         0x0
-#define GC_USB_DIEPINT12_BBLEERR_OFFSET          0xa88
-#define GC_USB_DIEPINT12_NAKINTRPT_LSB           0xd
-#define GC_USB_DIEPINT12_NAKINTRPT_MASK          0x2000
-#define GC_USB_DIEPINT12_NAKINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT12_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT12_NAKINTRPT_OFFSET        0xa88
-#define GC_USB_DIEPINT12_NYETINTRPT_LSB          0xe
-#define GC_USB_DIEPINT12_NYETINTRPT_MASK         0x4000
-#define GC_USB_DIEPINT12_NYETINTRPT_SIZE         0x1
-#define GC_USB_DIEPINT12_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DIEPINT12_NYETINTRPT_OFFSET       0xa88
-#define GC_USB_DIEPTSIZ12_XFERSIZE_LSB           0x0
-#define GC_USB_DIEPTSIZ12_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DIEPTSIZ12_XFERSIZE_SIZE          0x13
-#define GC_USB_DIEPTSIZ12_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DIEPTSIZ12_XFERSIZE_OFFSET        0xa90
-#define GC_USB_DIEPTSIZ12_PKTCNT_LSB             0x13
-#define GC_USB_DIEPTSIZ12_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DIEPTSIZ12_PKTCNT_SIZE            0xa
-#define GC_USB_DIEPTSIZ12_PKTCNT_DEFAULT         0x0
-#define GC_USB_DIEPTSIZ12_PKTCNT_OFFSET          0xa90
-#define GC_USB_DIEPTSIZ12_MC_LSB                 0x1d
-#define GC_USB_DIEPTSIZ12_MC_MASK                0x60000000
-#define GC_USB_DIEPTSIZ12_MC_SIZE                0x2
-#define GC_USB_DIEPTSIZ12_MC_DEFAULT             0x0
-#define GC_USB_DIEPTSIZ12_MC_OFFSET              0xa90
-#define GC_USB_DIEPDMA12_DMAADDR_LSB             0x0
-#define GC_USB_DIEPDMA12_DMAADDR_MASK            0xffffffff
-#define GC_USB_DIEPDMA12_DMAADDR_SIZE            0x20
-#define GC_USB_DIEPDMA12_DMAADDR_DEFAULT         0x0
-#define GC_USB_DIEPDMA12_DMAADDR_OFFSET          0xa94
-#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_LSB     0x0
-#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_MASK    0xffff
-#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_SIZE    0x10
+#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_OFFSET 0xa78
+#define GC_USB_DIEPDMAB11_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DIEPDMAB11_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMAB11_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DIEPDMAB11_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMAB11_DMABUFFERADDR_OFFSET 0xa7c
+#define GC_USB_DIEPCTL12_MPS_LSB 0x0
+#define GC_USB_DIEPCTL12_MPS_MASK 0x7ff
+#define GC_USB_DIEPCTL12_MPS_SIZE 0xb
+#define GC_USB_DIEPCTL12_MPS_DEFAULT 0x0
+#define GC_USB_DIEPCTL12_MPS_OFFSET 0xa80
+#define GC_USB_DIEPCTL12_USBACTEP_LSB 0xf
+#define GC_USB_DIEPCTL12_USBACTEP_MASK 0x8000
+#define GC_USB_DIEPCTL12_USBACTEP_SIZE 0x1
+#define GC_USB_DIEPCTL12_USBACTEP_DEFAULT 0x0
+#define GC_USB_DIEPCTL12_USBACTEP_OFFSET 0xa80
+#define GC_USB_DIEPCTL12_DPID_LSB 0x10
+#define GC_USB_DIEPCTL12_DPID_MASK 0x10000
+#define GC_USB_DIEPCTL12_DPID_SIZE 0x1
+#define GC_USB_DIEPCTL12_DPID_DEFAULT 0x0
+#define GC_USB_DIEPCTL12_DPID_OFFSET 0xa80
+#define GC_USB_DIEPCTL12_NAKSTS_LSB 0x11
+#define GC_USB_DIEPCTL12_NAKSTS_MASK 0x20000
+#define GC_USB_DIEPCTL12_NAKSTS_SIZE 0x1
+#define GC_USB_DIEPCTL12_NAKSTS_DEFAULT 0x0
+#define GC_USB_DIEPCTL12_NAKSTS_OFFSET 0xa80
+#define GC_USB_DIEPCTL12_EPTYPE_LSB 0x12
+#define GC_USB_DIEPCTL12_EPTYPE_MASK 0xc0000
+#define GC_USB_DIEPCTL12_EPTYPE_SIZE 0x2
+#define GC_USB_DIEPCTL12_EPTYPE_DEFAULT 0x0
+#define GC_USB_DIEPCTL12_EPTYPE_OFFSET 0xa80
+#define GC_USB_DIEPCTL12_STALL_LSB 0x15
+#define GC_USB_DIEPCTL12_STALL_MASK 0x200000
+#define GC_USB_DIEPCTL12_STALL_SIZE 0x1
+#define GC_USB_DIEPCTL12_STALL_DEFAULT 0x0
+#define GC_USB_DIEPCTL12_STALL_OFFSET 0xa80
+#define GC_USB_DIEPCTL12_TXFNUM_LSB 0x16
+#define GC_USB_DIEPCTL12_TXFNUM_MASK 0x3c00000
+#define GC_USB_DIEPCTL12_TXFNUM_SIZE 0x4
+#define GC_USB_DIEPCTL12_TXFNUM_DEFAULT 0x0
+#define GC_USB_DIEPCTL12_TXFNUM_OFFSET 0xa80
+#define GC_USB_DIEPCTL12_CNAK_LSB 0x1a
+#define GC_USB_DIEPCTL12_CNAK_MASK 0x4000000
+#define GC_USB_DIEPCTL12_CNAK_SIZE 0x1
+#define GC_USB_DIEPCTL12_CNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL12_CNAK_OFFSET 0xa80
+#define GC_USB_DIEPCTL12_SNAK_LSB 0x1b
+#define GC_USB_DIEPCTL12_SNAK_MASK 0x8000000
+#define GC_USB_DIEPCTL12_SNAK_SIZE 0x1
+#define GC_USB_DIEPCTL12_SNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL12_SNAK_OFFSET 0xa80
+#define GC_USB_DIEPCTL12_SETD0PID_LSB 0x1c
+#define GC_USB_DIEPCTL12_SETD0PID_MASK 0x10000000
+#define GC_USB_DIEPCTL12_SETD0PID_SIZE 0x1
+#define GC_USB_DIEPCTL12_SETD0PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL12_SETD0PID_OFFSET 0xa80
+#define GC_USB_DIEPCTL12_SETD1PID_LSB 0x1d
+#define GC_USB_DIEPCTL12_SETD1PID_MASK 0x20000000
+#define GC_USB_DIEPCTL12_SETD1PID_SIZE 0x1
+#define GC_USB_DIEPCTL12_SETD1PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL12_SETD1PID_OFFSET 0xa80
+#define GC_USB_DIEPCTL12_EPDIS_LSB 0x1e
+#define GC_USB_DIEPCTL12_EPDIS_MASK 0x40000000
+#define GC_USB_DIEPCTL12_EPDIS_SIZE 0x1
+#define GC_USB_DIEPCTL12_EPDIS_DEFAULT 0x0
+#define GC_USB_DIEPCTL12_EPDIS_OFFSET 0xa80
+#define GC_USB_DIEPCTL12_EPENA_LSB 0x1f
+#define GC_USB_DIEPCTL12_EPENA_MASK 0x80000000
+#define GC_USB_DIEPCTL12_EPENA_SIZE 0x1
+#define GC_USB_DIEPCTL12_EPENA_DEFAULT 0x0
+#define GC_USB_DIEPCTL12_EPENA_OFFSET 0xa80
+#define GC_USB_DIEPINT12_XFERCOMPL_LSB 0x0
+#define GC_USB_DIEPINT12_XFERCOMPL_MASK 0x1
+#define GC_USB_DIEPINT12_XFERCOMPL_SIZE 0x1
+#define GC_USB_DIEPINT12_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DIEPINT12_XFERCOMPL_OFFSET 0xa88
+#define GC_USB_DIEPINT12_EPDISBLD_LSB 0x1
+#define GC_USB_DIEPINT12_EPDISBLD_MASK 0x2
+#define GC_USB_DIEPINT12_EPDISBLD_SIZE 0x1
+#define GC_USB_DIEPINT12_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DIEPINT12_EPDISBLD_OFFSET 0xa88
+#define GC_USB_DIEPINT12_AHBERR_LSB 0x2
+#define GC_USB_DIEPINT12_AHBERR_MASK 0x4
+#define GC_USB_DIEPINT12_AHBERR_SIZE 0x1
+#define GC_USB_DIEPINT12_AHBERR_DEFAULT 0x0
+#define GC_USB_DIEPINT12_AHBERR_OFFSET 0xa88
+#define GC_USB_DIEPINT12_TIMEOUT_LSB 0x3
+#define GC_USB_DIEPINT12_TIMEOUT_MASK 0x8
+#define GC_USB_DIEPINT12_TIMEOUT_SIZE 0x1
+#define GC_USB_DIEPINT12_TIMEOUT_DEFAULT 0x0
+#define GC_USB_DIEPINT12_TIMEOUT_OFFSET 0xa88
+#define GC_USB_DIEPINT12_INTKNTXFEMP_LSB 0x4
+#define GC_USB_DIEPINT12_INTKNTXFEMP_MASK 0x10
+#define GC_USB_DIEPINT12_INTKNTXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT12_INTKNTXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT12_INTKNTXFEMP_OFFSET 0xa88
+#define GC_USB_DIEPINT12_INTKNEPMIS_LSB 0x5
+#define GC_USB_DIEPINT12_INTKNEPMIS_MASK 0x20
+#define GC_USB_DIEPINT12_INTKNEPMIS_SIZE 0x1
+#define GC_USB_DIEPINT12_INTKNEPMIS_DEFAULT 0x0
+#define GC_USB_DIEPINT12_INTKNEPMIS_OFFSET 0xa88
+#define GC_USB_DIEPINT12_INEPNAKEFF_LSB 0x6
+#define GC_USB_DIEPINT12_INEPNAKEFF_MASK 0x40
+#define GC_USB_DIEPINT12_INEPNAKEFF_SIZE 0x1
+#define GC_USB_DIEPINT12_INEPNAKEFF_DEFAULT 0x0
+#define GC_USB_DIEPINT12_INEPNAKEFF_OFFSET 0xa88
+#define GC_USB_DIEPINT12_TXFEMP_LSB 0x7
+#define GC_USB_DIEPINT12_TXFEMP_MASK 0x80
+#define GC_USB_DIEPINT12_TXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT12_TXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT12_TXFEMP_OFFSET 0xa88
+#define GC_USB_DIEPINT12_TXFIFOUNDRN_LSB 0x8
+#define GC_USB_DIEPINT12_TXFIFOUNDRN_MASK 0x100
+#define GC_USB_DIEPINT12_TXFIFOUNDRN_SIZE 0x1
+#define GC_USB_DIEPINT12_TXFIFOUNDRN_DEFAULT 0x0
+#define GC_USB_DIEPINT12_TXFIFOUNDRN_OFFSET 0xa88
+#define GC_USB_DIEPINT12_BNAINTR_LSB 0x9
+#define GC_USB_DIEPINT12_BNAINTR_MASK 0x200
+#define GC_USB_DIEPINT12_BNAINTR_SIZE 0x1
+#define GC_USB_DIEPINT12_BNAINTR_DEFAULT 0x0
+#define GC_USB_DIEPINT12_BNAINTR_OFFSET 0xa88
+#define GC_USB_DIEPINT12_PKTDRPSTS_LSB 0xb
+#define GC_USB_DIEPINT12_PKTDRPSTS_MASK 0x800
+#define GC_USB_DIEPINT12_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DIEPINT12_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DIEPINT12_PKTDRPSTS_OFFSET 0xa88
+#define GC_USB_DIEPINT12_BBLEERR_LSB 0xc
+#define GC_USB_DIEPINT12_BBLEERR_MASK 0x1000
+#define GC_USB_DIEPINT12_BBLEERR_SIZE 0x1
+#define GC_USB_DIEPINT12_BBLEERR_DEFAULT 0x0
+#define GC_USB_DIEPINT12_BBLEERR_OFFSET 0xa88
+#define GC_USB_DIEPINT12_NAKINTRPT_LSB 0xd
+#define GC_USB_DIEPINT12_NAKINTRPT_MASK 0x2000
+#define GC_USB_DIEPINT12_NAKINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT12_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT12_NAKINTRPT_OFFSET 0xa88
+#define GC_USB_DIEPINT12_NYETINTRPT_LSB 0xe
+#define GC_USB_DIEPINT12_NYETINTRPT_MASK 0x4000
+#define GC_USB_DIEPINT12_NYETINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT12_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT12_NYETINTRPT_OFFSET 0xa88
+#define GC_USB_DIEPTSIZ12_XFERSIZE_LSB 0x0
+#define GC_USB_DIEPTSIZ12_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DIEPTSIZ12_XFERSIZE_SIZE 0x13
+#define GC_USB_DIEPTSIZ12_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ12_XFERSIZE_OFFSET 0xa90
+#define GC_USB_DIEPTSIZ12_PKTCNT_LSB 0x13
+#define GC_USB_DIEPTSIZ12_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DIEPTSIZ12_PKTCNT_SIZE 0xa
+#define GC_USB_DIEPTSIZ12_PKTCNT_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ12_PKTCNT_OFFSET 0xa90
+#define GC_USB_DIEPTSIZ12_MC_LSB 0x1d
+#define GC_USB_DIEPTSIZ12_MC_MASK 0x60000000
+#define GC_USB_DIEPTSIZ12_MC_SIZE 0x2
+#define GC_USB_DIEPTSIZ12_MC_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ12_MC_OFFSET 0xa90
+#define GC_USB_DIEPDMA12_DMAADDR_LSB 0x0
+#define GC_USB_DIEPDMA12_DMAADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMA12_DMAADDR_SIZE 0x20
+#define GC_USB_DIEPDMA12_DMAADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMA12_DMAADDR_OFFSET 0xa94
+#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_LSB 0x0
+#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_MASK 0xffff
+#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_SIZE 0x10
 #define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_DEFAULT 0x0
-#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_OFFSET  0xa98
-#define GC_USB_DIEPDMAB12_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DIEPDMAB12_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DIEPDMAB12_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DIEPDMAB12_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DIEPDMAB12_DMABUFFERADDR_OFFSET   0xa9c
-#define GC_USB_DIEPCTL13_MPS_LSB                 0x0
-#define GC_USB_DIEPCTL13_MPS_MASK                0x7ff
-#define GC_USB_DIEPCTL13_MPS_SIZE                0xb
-#define GC_USB_DIEPCTL13_MPS_DEFAULT             0x0
-#define GC_USB_DIEPCTL13_MPS_OFFSET              0xaa0
-#define GC_USB_DIEPCTL13_USBACTEP_LSB            0xf
-#define GC_USB_DIEPCTL13_USBACTEP_MASK           0x8000
-#define GC_USB_DIEPCTL13_USBACTEP_SIZE           0x1
-#define GC_USB_DIEPCTL13_USBACTEP_DEFAULT        0x0
-#define GC_USB_DIEPCTL13_USBACTEP_OFFSET         0xaa0
-#define GC_USB_DIEPCTL13_DPID_LSB                0x10
-#define GC_USB_DIEPCTL13_DPID_MASK               0x10000
-#define GC_USB_DIEPCTL13_DPID_SIZE               0x1
-#define GC_USB_DIEPCTL13_DPID_DEFAULT            0x0
-#define GC_USB_DIEPCTL13_DPID_OFFSET             0xaa0
-#define GC_USB_DIEPCTL13_NAKSTS_LSB              0x11
-#define GC_USB_DIEPCTL13_NAKSTS_MASK             0x20000
-#define GC_USB_DIEPCTL13_NAKSTS_SIZE             0x1
-#define GC_USB_DIEPCTL13_NAKSTS_DEFAULT          0x0
-#define GC_USB_DIEPCTL13_NAKSTS_OFFSET           0xaa0
-#define GC_USB_DIEPCTL13_EPTYPE_LSB              0x12
-#define GC_USB_DIEPCTL13_EPTYPE_MASK             0xc0000
-#define GC_USB_DIEPCTL13_EPTYPE_SIZE             0x2
-#define GC_USB_DIEPCTL13_EPTYPE_DEFAULT          0x0
-#define GC_USB_DIEPCTL13_EPTYPE_OFFSET           0xaa0
-#define GC_USB_DIEPCTL13_STALL_LSB               0x15
-#define GC_USB_DIEPCTL13_STALL_MASK              0x200000
-#define GC_USB_DIEPCTL13_STALL_SIZE              0x1
-#define GC_USB_DIEPCTL13_STALL_DEFAULT           0x0
-#define GC_USB_DIEPCTL13_STALL_OFFSET            0xaa0
-#define GC_USB_DIEPCTL13_TXFNUM_LSB              0x16
-#define GC_USB_DIEPCTL13_TXFNUM_MASK             0x3c00000
-#define GC_USB_DIEPCTL13_TXFNUM_SIZE             0x4
-#define GC_USB_DIEPCTL13_TXFNUM_DEFAULT          0x0
-#define GC_USB_DIEPCTL13_TXFNUM_OFFSET           0xaa0
-#define GC_USB_DIEPCTL13_CNAK_LSB                0x1a
-#define GC_USB_DIEPCTL13_CNAK_MASK               0x4000000
-#define GC_USB_DIEPCTL13_CNAK_SIZE               0x1
-#define GC_USB_DIEPCTL13_CNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL13_CNAK_OFFSET             0xaa0
-#define GC_USB_DIEPCTL13_SNAK_LSB                0x1b
-#define GC_USB_DIEPCTL13_SNAK_MASK               0x8000000
-#define GC_USB_DIEPCTL13_SNAK_SIZE               0x1
-#define GC_USB_DIEPCTL13_SNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL13_SNAK_OFFSET             0xaa0
-#define GC_USB_DIEPCTL13_SETD0PID_LSB            0x1c
-#define GC_USB_DIEPCTL13_SETD0PID_MASK           0x10000000
-#define GC_USB_DIEPCTL13_SETD0PID_SIZE           0x1
-#define GC_USB_DIEPCTL13_SETD0PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL13_SETD0PID_OFFSET         0xaa0
-#define GC_USB_DIEPCTL13_SETD1PID_LSB            0x1d
-#define GC_USB_DIEPCTL13_SETD1PID_MASK           0x20000000
-#define GC_USB_DIEPCTL13_SETD1PID_SIZE           0x1
-#define GC_USB_DIEPCTL13_SETD1PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL13_SETD1PID_OFFSET         0xaa0
-#define GC_USB_DIEPCTL13_EPDIS_LSB               0x1e
-#define GC_USB_DIEPCTL13_EPDIS_MASK              0x40000000
-#define GC_USB_DIEPCTL13_EPDIS_SIZE              0x1
-#define GC_USB_DIEPCTL13_EPDIS_DEFAULT           0x0
-#define GC_USB_DIEPCTL13_EPDIS_OFFSET            0xaa0
-#define GC_USB_DIEPCTL13_EPENA_LSB               0x1f
-#define GC_USB_DIEPCTL13_EPENA_MASK              0x80000000
-#define GC_USB_DIEPCTL13_EPENA_SIZE              0x1
-#define GC_USB_DIEPCTL13_EPENA_DEFAULT           0x0
-#define GC_USB_DIEPCTL13_EPENA_OFFSET            0xaa0
-#define GC_USB_DIEPINT13_XFERCOMPL_LSB           0x0
-#define GC_USB_DIEPINT13_XFERCOMPL_MASK          0x1
-#define GC_USB_DIEPINT13_XFERCOMPL_SIZE          0x1
-#define GC_USB_DIEPINT13_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DIEPINT13_XFERCOMPL_OFFSET        0xaa8
-#define GC_USB_DIEPINT13_EPDISBLD_LSB            0x1
-#define GC_USB_DIEPINT13_EPDISBLD_MASK           0x2
-#define GC_USB_DIEPINT13_EPDISBLD_SIZE           0x1
-#define GC_USB_DIEPINT13_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DIEPINT13_EPDISBLD_OFFSET         0xaa8
-#define GC_USB_DIEPINT13_AHBERR_LSB              0x2
-#define GC_USB_DIEPINT13_AHBERR_MASK             0x4
-#define GC_USB_DIEPINT13_AHBERR_SIZE             0x1
-#define GC_USB_DIEPINT13_AHBERR_DEFAULT          0x0
-#define GC_USB_DIEPINT13_AHBERR_OFFSET           0xaa8
-#define GC_USB_DIEPINT13_TIMEOUT_LSB             0x3
-#define GC_USB_DIEPINT13_TIMEOUT_MASK            0x8
-#define GC_USB_DIEPINT13_TIMEOUT_SIZE            0x1
-#define GC_USB_DIEPINT13_TIMEOUT_DEFAULT         0x0
-#define GC_USB_DIEPINT13_TIMEOUT_OFFSET          0xaa8
-#define GC_USB_DIEPINT13_INTKNTXFEMP_LSB         0x4
-#define GC_USB_DIEPINT13_INTKNTXFEMP_MASK        0x10
-#define GC_USB_DIEPINT13_INTKNTXFEMP_SIZE        0x1
-#define GC_USB_DIEPINT13_INTKNTXFEMP_DEFAULT     0x0
-#define GC_USB_DIEPINT13_INTKNTXFEMP_OFFSET      0xaa8
-#define GC_USB_DIEPINT13_INTKNEPMIS_LSB          0x5
-#define GC_USB_DIEPINT13_INTKNEPMIS_MASK         0x20
-#define GC_USB_DIEPINT13_INTKNEPMIS_SIZE         0x1
-#define GC_USB_DIEPINT13_INTKNEPMIS_DEFAULT      0x0
-#define GC_USB_DIEPINT13_INTKNEPMIS_OFFSET       0xaa8
-#define GC_USB_DIEPINT13_INEPNAKEFF_LSB          0x6
-#define GC_USB_DIEPINT13_INEPNAKEFF_MASK         0x40
-#define GC_USB_DIEPINT13_INEPNAKEFF_SIZE         0x1
-#define GC_USB_DIEPINT13_INEPNAKEFF_DEFAULT      0x0
-#define GC_USB_DIEPINT13_INEPNAKEFF_OFFSET       0xaa8
-#define GC_USB_DIEPINT13_TXFEMP_LSB              0x7
-#define GC_USB_DIEPINT13_TXFEMP_MASK             0x80
-#define GC_USB_DIEPINT13_TXFEMP_SIZE             0x1
-#define GC_USB_DIEPINT13_TXFEMP_DEFAULT          0x0
-#define GC_USB_DIEPINT13_TXFEMP_OFFSET           0xaa8
-#define GC_USB_DIEPINT13_TXFIFOUNDRN_LSB         0x8
-#define GC_USB_DIEPINT13_TXFIFOUNDRN_MASK        0x100
-#define GC_USB_DIEPINT13_TXFIFOUNDRN_SIZE        0x1
-#define GC_USB_DIEPINT13_TXFIFOUNDRN_DEFAULT     0x0
-#define GC_USB_DIEPINT13_TXFIFOUNDRN_OFFSET      0xaa8
-#define GC_USB_DIEPINT13_BNAINTR_LSB             0x9
-#define GC_USB_DIEPINT13_BNAINTR_MASK            0x200
-#define GC_USB_DIEPINT13_BNAINTR_SIZE            0x1
-#define GC_USB_DIEPINT13_BNAINTR_DEFAULT         0x0
-#define GC_USB_DIEPINT13_BNAINTR_OFFSET          0xaa8
-#define GC_USB_DIEPINT13_PKTDRPSTS_LSB           0xb
-#define GC_USB_DIEPINT13_PKTDRPSTS_MASK          0x800
-#define GC_USB_DIEPINT13_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DIEPINT13_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DIEPINT13_PKTDRPSTS_OFFSET        0xaa8
-#define GC_USB_DIEPINT13_BBLEERR_LSB             0xc
-#define GC_USB_DIEPINT13_BBLEERR_MASK            0x1000
-#define GC_USB_DIEPINT13_BBLEERR_SIZE            0x1
-#define GC_USB_DIEPINT13_BBLEERR_DEFAULT         0x0
-#define GC_USB_DIEPINT13_BBLEERR_OFFSET          0xaa8
-#define GC_USB_DIEPINT13_NAKINTRPT_LSB           0xd
-#define GC_USB_DIEPINT13_NAKINTRPT_MASK          0x2000
-#define GC_USB_DIEPINT13_NAKINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT13_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT13_NAKINTRPT_OFFSET        0xaa8
-#define GC_USB_DIEPINT13_NYETINTRPT_LSB          0xe
-#define GC_USB_DIEPINT13_NYETINTRPT_MASK         0x4000
-#define GC_USB_DIEPINT13_NYETINTRPT_SIZE         0x1
-#define GC_USB_DIEPINT13_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DIEPINT13_NYETINTRPT_OFFSET       0xaa8
-#define GC_USB_DIEPTSIZ13_XFERSIZE_LSB           0x0
-#define GC_USB_DIEPTSIZ13_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DIEPTSIZ13_XFERSIZE_SIZE          0x13
-#define GC_USB_DIEPTSIZ13_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DIEPTSIZ13_XFERSIZE_OFFSET        0xab0
-#define GC_USB_DIEPTSIZ13_PKTCNT_LSB             0x13
-#define GC_USB_DIEPTSIZ13_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DIEPTSIZ13_PKTCNT_SIZE            0xa
-#define GC_USB_DIEPTSIZ13_PKTCNT_DEFAULT         0x0
-#define GC_USB_DIEPTSIZ13_PKTCNT_OFFSET          0xab0
-#define GC_USB_DIEPTSIZ13_MC_LSB                 0x1d
-#define GC_USB_DIEPTSIZ13_MC_MASK                0x60000000
-#define GC_USB_DIEPTSIZ13_MC_SIZE                0x2
-#define GC_USB_DIEPTSIZ13_MC_DEFAULT             0x0
-#define GC_USB_DIEPTSIZ13_MC_OFFSET              0xab0
-#define GC_USB_DIEPDMA13_DMAADDR_LSB             0x0
-#define GC_USB_DIEPDMA13_DMAADDR_MASK            0xffffffff
-#define GC_USB_DIEPDMA13_DMAADDR_SIZE            0x20
-#define GC_USB_DIEPDMA13_DMAADDR_DEFAULT         0x0
-#define GC_USB_DIEPDMA13_DMAADDR_OFFSET          0xab4
-#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_LSB     0x0
-#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_MASK    0xffff
-#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_SIZE    0x10
+#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_OFFSET 0xa98
+#define GC_USB_DIEPDMAB12_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DIEPDMAB12_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMAB12_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DIEPDMAB12_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMAB12_DMABUFFERADDR_OFFSET 0xa9c
+#define GC_USB_DIEPCTL13_MPS_LSB 0x0
+#define GC_USB_DIEPCTL13_MPS_MASK 0x7ff
+#define GC_USB_DIEPCTL13_MPS_SIZE 0xb
+#define GC_USB_DIEPCTL13_MPS_DEFAULT 0x0
+#define GC_USB_DIEPCTL13_MPS_OFFSET 0xaa0
+#define GC_USB_DIEPCTL13_USBACTEP_LSB 0xf
+#define GC_USB_DIEPCTL13_USBACTEP_MASK 0x8000
+#define GC_USB_DIEPCTL13_USBACTEP_SIZE 0x1
+#define GC_USB_DIEPCTL13_USBACTEP_DEFAULT 0x0
+#define GC_USB_DIEPCTL13_USBACTEP_OFFSET 0xaa0
+#define GC_USB_DIEPCTL13_DPID_LSB 0x10
+#define GC_USB_DIEPCTL13_DPID_MASK 0x10000
+#define GC_USB_DIEPCTL13_DPID_SIZE 0x1
+#define GC_USB_DIEPCTL13_DPID_DEFAULT 0x0
+#define GC_USB_DIEPCTL13_DPID_OFFSET 0xaa0
+#define GC_USB_DIEPCTL13_NAKSTS_LSB 0x11
+#define GC_USB_DIEPCTL13_NAKSTS_MASK 0x20000
+#define GC_USB_DIEPCTL13_NAKSTS_SIZE 0x1
+#define GC_USB_DIEPCTL13_NAKSTS_DEFAULT 0x0
+#define GC_USB_DIEPCTL13_NAKSTS_OFFSET 0xaa0
+#define GC_USB_DIEPCTL13_EPTYPE_LSB 0x12
+#define GC_USB_DIEPCTL13_EPTYPE_MASK 0xc0000
+#define GC_USB_DIEPCTL13_EPTYPE_SIZE 0x2
+#define GC_USB_DIEPCTL13_EPTYPE_DEFAULT 0x0
+#define GC_USB_DIEPCTL13_EPTYPE_OFFSET 0xaa0
+#define GC_USB_DIEPCTL13_STALL_LSB 0x15
+#define GC_USB_DIEPCTL13_STALL_MASK 0x200000
+#define GC_USB_DIEPCTL13_STALL_SIZE 0x1
+#define GC_USB_DIEPCTL13_STALL_DEFAULT 0x0
+#define GC_USB_DIEPCTL13_STALL_OFFSET 0xaa0
+#define GC_USB_DIEPCTL13_TXFNUM_LSB 0x16
+#define GC_USB_DIEPCTL13_TXFNUM_MASK 0x3c00000
+#define GC_USB_DIEPCTL13_TXFNUM_SIZE 0x4
+#define GC_USB_DIEPCTL13_TXFNUM_DEFAULT 0x0
+#define GC_USB_DIEPCTL13_TXFNUM_OFFSET 0xaa0
+#define GC_USB_DIEPCTL13_CNAK_LSB 0x1a
+#define GC_USB_DIEPCTL13_CNAK_MASK 0x4000000
+#define GC_USB_DIEPCTL13_CNAK_SIZE 0x1
+#define GC_USB_DIEPCTL13_CNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL13_CNAK_OFFSET 0xaa0
+#define GC_USB_DIEPCTL13_SNAK_LSB 0x1b
+#define GC_USB_DIEPCTL13_SNAK_MASK 0x8000000
+#define GC_USB_DIEPCTL13_SNAK_SIZE 0x1
+#define GC_USB_DIEPCTL13_SNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL13_SNAK_OFFSET 0xaa0
+#define GC_USB_DIEPCTL13_SETD0PID_LSB 0x1c
+#define GC_USB_DIEPCTL13_SETD0PID_MASK 0x10000000
+#define GC_USB_DIEPCTL13_SETD0PID_SIZE 0x1
+#define GC_USB_DIEPCTL13_SETD0PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL13_SETD0PID_OFFSET 0xaa0
+#define GC_USB_DIEPCTL13_SETD1PID_LSB 0x1d
+#define GC_USB_DIEPCTL13_SETD1PID_MASK 0x20000000
+#define GC_USB_DIEPCTL13_SETD1PID_SIZE 0x1
+#define GC_USB_DIEPCTL13_SETD1PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL13_SETD1PID_OFFSET 0xaa0
+#define GC_USB_DIEPCTL13_EPDIS_LSB 0x1e
+#define GC_USB_DIEPCTL13_EPDIS_MASK 0x40000000
+#define GC_USB_DIEPCTL13_EPDIS_SIZE 0x1
+#define GC_USB_DIEPCTL13_EPDIS_DEFAULT 0x0
+#define GC_USB_DIEPCTL13_EPDIS_OFFSET 0xaa0
+#define GC_USB_DIEPCTL13_EPENA_LSB 0x1f
+#define GC_USB_DIEPCTL13_EPENA_MASK 0x80000000
+#define GC_USB_DIEPCTL13_EPENA_SIZE 0x1
+#define GC_USB_DIEPCTL13_EPENA_DEFAULT 0x0
+#define GC_USB_DIEPCTL13_EPENA_OFFSET 0xaa0
+#define GC_USB_DIEPINT13_XFERCOMPL_LSB 0x0
+#define GC_USB_DIEPINT13_XFERCOMPL_MASK 0x1
+#define GC_USB_DIEPINT13_XFERCOMPL_SIZE 0x1
+#define GC_USB_DIEPINT13_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DIEPINT13_XFERCOMPL_OFFSET 0xaa8
+#define GC_USB_DIEPINT13_EPDISBLD_LSB 0x1
+#define GC_USB_DIEPINT13_EPDISBLD_MASK 0x2
+#define GC_USB_DIEPINT13_EPDISBLD_SIZE 0x1
+#define GC_USB_DIEPINT13_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DIEPINT13_EPDISBLD_OFFSET 0xaa8
+#define GC_USB_DIEPINT13_AHBERR_LSB 0x2
+#define GC_USB_DIEPINT13_AHBERR_MASK 0x4
+#define GC_USB_DIEPINT13_AHBERR_SIZE 0x1
+#define GC_USB_DIEPINT13_AHBERR_DEFAULT 0x0
+#define GC_USB_DIEPINT13_AHBERR_OFFSET 0xaa8
+#define GC_USB_DIEPINT13_TIMEOUT_LSB 0x3
+#define GC_USB_DIEPINT13_TIMEOUT_MASK 0x8
+#define GC_USB_DIEPINT13_TIMEOUT_SIZE 0x1
+#define GC_USB_DIEPINT13_TIMEOUT_DEFAULT 0x0
+#define GC_USB_DIEPINT13_TIMEOUT_OFFSET 0xaa8
+#define GC_USB_DIEPINT13_INTKNTXFEMP_LSB 0x4
+#define GC_USB_DIEPINT13_INTKNTXFEMP_MASK 0x10
+#define GC_USB_DIEPINT13_INTKNTXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT13_INTKNTXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT13_INTKNTXFEMP_OFFSET 0xaa8
+#define GC_USB_DIEPINT13_INTKNEPMIS_LSB 0x5
+#define GC_USB_DIEPINT13_INTKNEPMIS_MASK 0x20
+#define GC_USB_DIEPINT13_INTKNEPMIS_SIZE 0x1
+#define GC_USB_DIEPINT13_INTKNEPMIS_DEFAULT 0x0
+#define GC_USB_DIEPINT13_INTKNEPMIS_OFFSET 0xaa8
+#define GC_USB_DIEPINT13_INEPNAKEFF_LSB 0x6
+#define GC_USB_DIEPINT13_INEPNAKEFF_MASK 0x40
+#define GC_USB_DIEPINT13_INEPNAKEFF_SIZE 0x1
+#define GC_USB_DIEPINT13_INEPNAKEFF_DEFAULT 0x0
+#define GC_USB_DIEPINT13_INEPNAKEFF_OFFSET 0xaa8
+#define GC_USB_DIEPINT13_TXFEMP_LSB 0x7
+#define GC_USB_DIEPINT13_TXFEMP_MASK 0x80
+#define GC_USB_DIEPINT13_TXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT13_TXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT13_TXFEMP_OFFSET 0xaa8
+#define GC_USB_DIEPINT13_TXFIFOUNDRN_LSB 0x8
+#define GC_USB_DIEPINT13_TXFIFOUNDRN_MASK 0x100
+#define GC_USB_DIEPINT13_TXFIFOUNDRN_SIZE 0x1
+#define GC_USB_DIEPINT13_TXFIFOUNDRN_DEFAULT 0x0
+#define GC_USB_DIEPINT13_TXFIFOUNDRN_OFFSET 0xaa8
+#define GC_USB_DIEPINT13_BNAINTR_LSB 0x9
+#define GC_USB_DIEPINT13_BNAINTR_MASK 0x200
+#define GC_USB_DIEPINT13_BNAINTR_SIZE 0x1
+#define GC_USB_DIEPINT13_BNAINTR_DEFAULT 0x0
+#define GC_USB_DIEPINT13_BNAINTR_OFFSET 0xaa8
+#define GC_USB_DIEPINT13_PKTDRPSTS_LSB 0xb
+#define GC_USB_DIEPINT13_PKTDRPSTS_MASK 0x800
+#define GC_USB_DIEPINT13_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DIEPINT13_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DIEPINT13_PKTDRPSTS_OFFSET 0xaa8
+#define GC_USB_DIEPINT13_BBLEERR_LSB 0xc
+#define GC_USB_DIEPINT13_BBLEERR_MASK 0x1000
+#define GC_USB_DIEPINT13_BBLEERR_SIZE 0x1
+#define GC_USB_DIEPINT13_BBLEERR_DEFAULT 0x0
+#define GC_USB_DIEPINT13_BBLEERR_OFFSET 0xaa8
+#define GC_USB_DIEPINT13_NAKINTRPT_LSB 0xd
+#define GC_USB_DIEPINT13_NAKINTRPT_MASK 0x2000
+#define GC_USB_DIEPINT13_NAKINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT13_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT13_NAKINTRPT_OFFSET 0xaa8
+#define GC_USB_DIEPINT13_NYETINTRPT_LSB 0xe
+#define GC_USB_DIEPINT13_NYETINTRPT_MASK 0x4000
+#define GC_USB_DIEPINT13_NYETINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT13_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT13_NYETINTRPT_OFFSET 0xaa8
+#define GC_USB_DIEPTSIZ13_XFERSIZE_LSB 0x0
+#define GC_USB_DIEPTSIZ13_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DIEPTSIZ13_XFERSIZE_SIZE 0x13
+#define GC_USB_DIEPTSIZ13_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ13_XFERSIZE_OFFSET 0xab0
+#define GC_USB_DIEPTSIZ13_PKTCNT_LSB 0x13
+#define GC_USB_DIEPTSIZ13_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DIEPTSIZ13_PKTCNT_SIZE 0xa
+#define GC_USB_DIEPTSIZ13_PKTCNT_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ13_PKTCNT_OFFSET 0xab0
+#define GC_USB_DIEPTSIZ13_MC_LSB 0x1d
+#define GC_USB_DIEPTSIZ13_MC_MASK 0x60000000
+#define GC_USB_DIEPTSIZ13_MC_SIZE 0x2
+#define GC_USB_DIEPTSIZ13_MC_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ13_MC_OFFSET 0xab0
+#define GC_USB_DIEPDMA13_DMAADDR_LSB 0x0
+#define GC_USB_DIEPDMA13_DMAADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMA13_DMAADDR_SIZE 0x20
+#define GC_USB_DIEPDMA13_DMAADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMA13_DMAADDR_OFFSET 0xab4
+#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_LSB 0x0
+#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_MASK 0xffff
+#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_SIZE 0x10
 #define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_DEFAULT 0x0
-#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_OFFSET  0xab8
-#define GC_USB_DIEPDMAB13_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DIEPDMAB13_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DIEPDMAB13_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DIEPDMAB13_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DIEPDMAB13_DMABUFFERADDR_OFFSET   0xabc
-#define GC_USB_DIEPCTL14_MPS_LSB                 0x0
-#define GC_USB_DIEPCTL14_MPS_MASK                0x7ff
-#define GC_USB_DIEPCTL14_MPS_SIZE                0xb
-#define GC_USB_DIEPCTL14_MPS_DEFAULT             0x0
-#define GC_USB_DIEPCTL14_MPS_OFFSET              0xac0
-#define GC_USB_DIEPCTL14_USBACTEP_LSB            0xf
-#define GC_USB_DIEPCTL14_USBACTEP_MASK           0x8000
-#define GC_USB_DIEPCTL14_USBACTEP_SIZE           0x1
-#define GC_USB_DIEPCTL14_USBACTEP_DEFAULT        0x0
-#define GC_USB_DIEPCTL14_USBACTEP_OFFSET         0xac0
-#define GC_USB_DIEPCTL14_DPID_LSB                0x10
-#define GC_USB_DIEPCTL14_DPID_MASK               0x10000
-#define GC_USB_DIEPCTL14_DPID_SIZE               0x1
-#define GC_USB_DIEPCTL14_DPID_DEFAULT            0x0
-#define GC_USB_DIEPCTL14_DPID_OFFSET             0xac0
-#define GC_USB_DIEPCTL14_NAKSTS_LSB              0x11
-#define GC_USB_DIEPCTL14_NAKSTS_MASK             0x20000
-#define GC_USB_DIEPCTL14_NAKSTS_SIZE             0x1
-#define GC_USB_DIEPCTL14_NAKSTS_DEFAULT          0x0
-#define GC_USB_DIEPCTL14_NAKSTS_OFFSET           0xac0
-#define GC_USB_DIEPCTL14_EPTYPE_LSB              0x12
-#define GC_USB_DIEPCTL14_EPTYPE_MASK             0xc0000
-#define GC_USB_DIEPCTL14_EPTYPE_SIZE             0x2
-#define GC_USB_DIEPCTL14_EPTYPE_DEFAULT          0x0
-#define GC_USB_DIEPCTL14_EPTYPE_OFFSET           0xac0
-#define GC_USB_DIEPCTL14_STALL_LSB               0x15
-#define GC_USB_DIEPCTL14_STALL_MASK              0x200000
-#define GC_USB_DIEPCTL14_STALL_SIZE              0x1
-#define GC_USB_DIEPCTL14_STALL_DEFAULT           0x0
-#define GC_USB_DIEPCTL14_STALL_OFFSET            0xac0
-#define GC_USB_DIEPCTL14_TXFNUM_LSB              0x16
-#define GC_USB_DIEPCTL14_TXFNUM_MASK             0x3c00000
-#define GC_USB_DIEPCTL14_TXFNUM_SIZE             0x4
-#define GC_USB_DIEPCTL14_TXFNUM_DEFAULT          0x0
-#define GC_USB_DIEPCTL14_TXFNUM_OFFSET           0xac0
-#define GC_USB_DIEPCTL14_CNAK_LSB                0x1a
-#define GC_USB_DIEPCTL14_CNAK_MASK               0x4000000
-#define GC_USB_DIEPCTL14_CNAK_SIZE               0x1
-#define GC_USB_DIEPCTL14_CNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL14_CNAK_OFFSET             0xac0
-#define GC_USB_DIEPCTL14_SNAK_LSB                0x1b
-#define GC_USB_DIEPCTL14_SNAK_MASK               0x8000000
-#define GC_USB_DIEPCTL14_SNAK_SIZE               0x1
-#define GC_USB_DIEPCTL14_SNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL14_SNAK_OFFSET             0xac0
-#define GC_USB_DIEPCTL14_SETD0PID_LSB            0x1c
-#define GC_USB_DIEPCTL14_SETD0PID_MASK           0x10000000
-#define GC_USB_DIEPCTL14_SETD0PID_SIZE           0x1
-#define GC_USB_DIEPCTL14_SETD0PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL14_SETD0PID_OFFSET         0xac0
-#define GC_USB_DIEPCTL14_SETD1PID_LSB            0x1d
-#define GC_USB_DIEPCTL14_SETD1PID_MASK           0x20000000
-#define GC_USB_DIEPCTL14_SETD1PID_SIZE           0x1
-#define GC_USB_DIEPCTL14_SETD1PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL14_SETD1PID_OFFSET         0xac0
-#define GC_USB_DIEPCTL14_EPDIS_LSB               0x1e
-#define GC_USB_DIEPCTL14_EPDIS_MASK              0x40000000
-#define GC_USB_DIEPCTL14_EPDIS_SIZE              0x1
-#define GC_USB_DIEPCTL14_EPDIS_DEFAULT           0x0
-#define GC_USB_DIEPCTL14_EPDIS_OFFSET            0xac0
-#define GC_USB_DIEPCTL14_EPENA_LSB               0x1f
-#define GC_USB_DIEPCTL14_EPENA_MASK              0x80000000
-#define GC_USB_DIEPCTL14_EPENA_SIZE              0x1
-#define GC_USB_DIEPCTL14_EPENA_DEFAULT           0x0
-#define GC_USB_DIEPCTL14_EPENA_OFFSET            0xac0
-#define GC_USB_DIEPINT14_XFERCOMPL_LSB           0x0
-#define GC_USB_DIEPINT14_XFERCOMPL_MASK          0x1
-#define GC_USB_DIEPINT14_XFERCOMPL_SIZE          0x1
-#define GC_USB_DIEPINT14_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DIEPINT14_XFERCOMPL_OFFSET        0xac8
-#define GC_USB_DIEPINT14_EPDISBLD_LSB            0x1
-#define GC_USB_DIEPINT14_EPDISBLD_MASK           0x2
-#define GC_USB_DIEPINT14_EPDISBLD_SIZE           0x1
-#define GC_USB_DIEPINT14_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DIEPINT14_EPDISBLD_OFFSET         0xac8
-#define GC_USB_DIEPINT14_AHBERR_LSB              0x2
-#define GC_USB_DIEPINT14_AHBERR_MASK             0x4
-#define GC_USB_DIEPINT14_AHBERR_SIZE             0x1
-#define GC_USB_DIEPINT14_AHBERR_DEFAULT          0x0
-#define GC_USB_DIEPINT14_AHBERR_OFFSET           0xac8
-#define GC_USB_DIEPINT14_TIMEOUT_LSB             0x3
-#define GC_USB_DIEPINT14_TIMEOUT_MASK            0x8
-#define GC_USB_DIEPINT14_TIMEOUT_SIZE            0x1
-#define GC_USB_DIEPINT14_TIMEOUT_DEFAULT         0x0
-#define GC_USB_DIEPINT14_TIMEOUT_OFFSET          0xac8
-#define GC_USB_DIEPINT14_INTKNTXFEMP_LSB         0x4
-#define GC_USB_DIEPINT14_INTKNTXFEMP_MASK        0x10
-#define GC_USB_DIEPINT14_INTKNTXFEMP_SIZE        0x1
-#define GC_USB_DIEPINT14_INTKNTXFEMP_DEFAULT     0x0
-#define GC_USB_DIEPINT14_INTKNTXFEMP_OFFSET      0xac8
-#define GC_USB_DIEPINT14_INTKNEPMIS_LSB          0x5
-#define GC_USB_DIEPINT14_INTKNEPMIS_MASK         0x20
-#define GC_USB_DIEPINT14_INTKNEPMIS_SIZE         0x1
-#define GC_USB_DIEPINT14_INTKNEPMIS_DEFAULT      0x0
-#define GC_USB_DIEPINT14_INTKNEPMIS_OFFSET       0xac8
-#define GC_USB_DIEPINT14_INEPNAKEFF_LSB          0x6
-#define GC_USB_DIEPINT14_INEPNAKEFF_MASK         0x40
-#define GC_USB_DIEPINT14_INEPNAKEFF_SIZE         0x1
-#define GC_USB_DIEPINT14_INEPNAKEFF_DEFAULT      0x0
-#define GC_USB_DIEPINT14_INEPNAKEFF_OFFSET       0xac8
-#define GC_USB_DIEPINT14_TXFEMP_LSB              0x7
-#define GC_USB_DIEPINT14_TXFEMP_MASK             0x80
-#define GC_USB_DIEPINT14_TXFEMP_SIZE             0x1
-#define GC_USB_DIEPINT14_TXFEMP_DEFAULT          0x0
-#define GC_USB_DIEPINT14_TXFEMP_OFFSET           0xac8
-#define GC_USB_DIEPINT14_TXFIFOUNDRN_LSB         0x8
-#define GC_USB_DIEPINT14_TXFIFOUNDRN_MASK        0x100
-#define GC_USB_DIEPINT14_TXFIFOUNDRN_SIZE        0x1
-#define GC_USB_DIEPINT14_TXFIFOUNDRN_DEFAULT     0x0
-#define GC_USB_DIEPINT14_TXFIFOUNDRN_OFFSET      0xac8
-#define GC_USB_DIEPINT14_BNAINTR_LSB             0x9
-#define GC_USB_DIEPINT14_BNAINTR_MASK            0x200
-#define GC_USB_DIEPINT14_BNAINTR_SIZE            0x1
-#define GC_USB_DIEPINT14_BNAINTR_DEFAULT         0x0
-#define GC_USB_DIEPINT14_BNAINTR_OFFSET          0xac8
-#define GC_USB_DIEPINT14_PKTDRPSTS_LSB           0xb
-#define GC_USB_DIEPINT14_PKTDRPSTS_MASK          0x800
-#define GC_USB_DIEPINT14_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DIEPINT14_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DIEPINT14_PKTDRPSTS_OFFSET        0xac8
-#define GC_USB_DIEPINT14_BBLEERR_LSB             0xc
-#define GC_USB_DIEPINT14_BBLEERR_MASK            0x1000
-#define GC_USB_DIEPINT14_BBLEERR_SIZE            0x1
-#define GC_USB_DIEPINT14_BBLEERR_DEFAULT         0x0
-#define GC_USB_DIEPINT14_BBLEERR_OFFSET          0xac8
-#define GC_USB_DIEPINT14_NAKINTRPT_LSB           0xd
-#define GC_USB_DIEPINT14_NAKINTRPT_MASK          0x2000
-#define GC_USB_DIEPINT14_NAKINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT14_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT14_NAKINTRPT_OFFSET        0xac8
-#define GC_USB_DIEPINT14_NYETINTRPT_LSB          0xe
-#define GC_USB_DIEPINT14_NYETINTRPT_MASK         0x4000
-#define GC_USB_DIEPINT14_NYETINTRPT_SIZE         0x1
-#define GC_USB_DIEPINT14_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DIEPINT14_NYETINTRPT_OFFSET       0xac8
-#define GC_USB_DIEPTSIZ14_XFERSIZE_LSB           0x0
-#define GC_USB_DIEPTSIZ14_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DIEPTSIZ14_XFERSIZE_SIZE          0x13
-#define GC_USB_DIEPTSIZ14_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DIEPTSIZ14_XFERSIZE_OFFSET        0xad0
-#define GC_USB_DIEPTSIZ14_PKTCNT_LSB             0x13
-#define GC_USB_DIEPTSIZ14_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DIEPTSIZ14_PKTCNT_SIZE            0xa
-#define GC_USB_DIEPTSIZ14_PKTCNT_DEFAULT         0x0
-#define GC_USB_DIEPTSIZ14_PKTCNT_OFFSET          0xad0
-#define GC_USB_DIEPTSIZ14_MC_LSB                 0x1d
-#define GC_USB_DIEPTSIZ14_MC_MASK                0x60000000
-#define GC_USB_DIEPTSIZ14_MC_SIZE                0x2
-#define GC_USB_DIEPTSIZ14_MC_DEFAULT             0x0
-#define GC_USB_DIEPTSIZ14_MC_OFFSET              0xad0
-#define GC_USB_DIEPDMA14_DMAADDR_LSB             0x0
-#define GC_USB_DIEPDMA14_DMAADDR_MASK            0xffffffff
-#define GC_USB_DIEPDMA14_DMAADDR_SIZE            0x20
-#define GC_USB_DIEPDMA14_DMAADDR_DEFAULT         0x0
-#define GC_USB_DIEPDMA14_DMAADDR_OFFSET          0xad4
-#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_LSB     0x0
-#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_MASK    0xffff
-#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_SIZE    0x10
+#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_OFFSET 0xab8
+#define GC_USB_DIEPDMAB13_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DIEPDMAB13_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMAB13_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DIEPDMAB13_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMAB13_DMABUFFERADDR_OFFSET 0xabc
+#define GC_USB_DIEPCTL14_MPS_LSB 0x0
+#define GC_USB_DIEPCTL14_MPS_MASK 0x7ff
+#define GC_USB_DIEPCTL14_MPS_SIZE 0xb
+#define GC_USB_DIEPCTL14_MPS_DEFAULT 0x0
+#define GC_USB_DIEPCTL14_MPS_OFFSET 0xac0
+#define GC_USB_DIEPCTL14_USBACTEP_LSB 0xf
+#define GC_USB_DIEPCTL14_USBACTEP_MASK 0x8000
+#define GC_USB_DIEPCTL14_USBACTEP_SIZE 0x1
+#define GC_USB_DIEPCTL14_USBACTEP_DEFAULT 0x0
+#define GC_USB_DIEPCTL14_USBACTEP_OFFSET 0xac0
+#define GC_USB_DIEPCTL14_DPID_LSB 0x10
+#define GC_USB_DIEPCTL14_DPID_MASK 0x10000
+#define GC_USB_DIEPCTL14_DPID_SIZE 0x1
+#define GC_USB_DIEPCTL14_DPID_DEFAULT 0x0
+#define GC_USB_DIEPCTL14_DPID_OFFSET 0xac0
+#define GC_USB_DIEPCTL14_NAKSTS_LSB 0x11
+#define GC_USB_DIEPCTL14_NAKSTS_MASK 0x20000
+#define GC_USB_DIEPCTL14_NAKSTS_SIZE 0x1
+#define GC_USB_DIEPCTL14_NAKSTS_DEFAULT 0x0
+#define GC_USB_DIEPCTL14_NAKSTS_OFFSET 0xac0
+#define GC_USB_DIEPCTL14_EPTYPE_LSB 0x12
+#define GC_USB_DIEPCTL14_EPTYPE_MASK 0xc0000
+#define GC_USB_DIEPCTL14_EPTYPE_SIZE 0x2
+#define GC_USB_DIEPCTL14_EPTYPE_DEFAULT 0x0
+#define GC_USB_DIEPCTL14_EPTYPE_OFFSET 0xac0
+#define GC_USB_DIEPCTL14_STALL_LSB 0x15
+#define GC_USB_DIEPCTL14_STALL_MASK 0x200000
+#define GC_USB_DIEPCTL14_STALL_SIZE 0x1
+#define GC_USB_DIEPCTL14_STALL_DEFAULT 0x0
+#define GC_USB_DIEPCTL14_STALL_OFFSET 0xac0
+#define GC_USB_DIEPCTL14_TXFNUM_LSB 0x16
+#define GC_USB_DIEPCTL14_TXFNUM_MASK 0x3c00000
+#define GC_USB_DIEPCTL14_TXFNUM_SIZE 0x4
+#define GC_USB_DIEPCTL14_TXFNUM_DEFAULT 0x0
+#define GC_USB_DIEPCTL14_TXFNUM_OFFSET 0xac0
+#define GC_USB_DIEPCTL14_CNAK_LSB 0x1a
+#define GC_USB_DIEPCTL14_CNAK_MASK 0x4000000
+#define GC_USB_DIEPCTL14_CNAK_SIZE 0x1
+#define GC_USB_DIEPCTL14_CNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL14_CNAK_OFFSET 0xac0
+#define GC_USB_DIEPCTL14_SNAK_LSB 0x1b
+#define GC_USB_DIEPCTL14_SNAK_MASK 0x8000000
+#define GC_USB_DIEPCTL14_SNAK_SIZE 0x1
+#define GC_USB_DIEPCTL14_SNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL14_SNAK_OFFSET 0xac0
+#define GC_USB_DIEPCTL14_SETD0PID_LSB 0x1c
+#define GC_USB_DIEPCTL14_SETD0PID_MASK 0x10000000
+#define GC_USB_DIEPCTL14_SETD0PID_SIZE 0x1
+#define GC_USB_DIEPCTL14_SETD0PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL14_SETD0PID_OFFSET 0xac0
+#define GC_USB_DIEPCTL14_SETD1PID_LSB 0x1d
+#define GC_USB_DIEPCTL14_SETD1PID_MASK 0x20000000
+#define GC_USB_DIEPCTL14_SETD1PID_SIZE 0x1
+#define GC_USB_DIEPCTL14_SETD1PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL14_SETD1PID_OFFSET 0xac0
+#define GC_USB_DIEPCTL14_EPDIS_LSB 0x1e
+#define GC_USB_DIEPCTL14_EPDIS_MASK 0x40000000
+#define GC_USB_DIEPCTL14_EPDIS_SIZE 0x1
+#define GC_USB_DIEPCTL14_EPDIS_DEFAULT 0x0
+#define GC_USB_DIEPCTL14_EPDIS_OFFSET 0xac0
+#define GC_USB_DIEPCTL14_EPENA_LSB 0x1f
+#define GC_USB_DIEPCTL14_EPENA_MASK 0x80000000
+#define GC_USB_DIEPCTL14_EPENA_SIZE 0x1
+#define GC_USB_DIEPCTL14_EPENA_DEFAULT 0x0
+#define GC_USB_DIEPCTL14_EPENA_OFFSET 0xac0
+#define GC_USB_DIEPINT14_XFERCOMPL_LSB 0x0
+#define GC_USB_DIEPINT14_XFERCOMPL_MASK 0x1
+#define GC_USB_DIEPINT14_XFERCOMPL_SIZE 0x1
+#define GC_USB_DIEPINT14_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DIEPINT14_XFERCOMPL_OFFSET 0xac8
+#define GC_USB_DIEPINT14_EPDISBLD_LSB 0x1
+#define GC_USB_DIEPINT14_EPDISBLD_MASK 0x2
+#define GC_USB_DIEPINT14_EPDISBLD_SIZE 0x1
+#define GC_USB_DIEPINT14_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DIEPINT14_EPDISBLD_OFFSET 0xac8
+#define GC_USB_DIEPINT14_AHBERR_LSB 0x2
+#define GC_USB_DIEPINT14_AHBERR_MASK 0x4
+#define GC_USB_DIEPINT14_AHBERR_SIZE 0x1
+#define GC_USB_DIEPINT14_AHBERR_DEFAULT 0x0
+#define GC_USB_DIEPINT14_AHBERR_OFFSET 0xac8
+#define GC_USB_DIEPINT14_TIMEOUT_LSB 0x3
+#define GC_USB_DIEPINT14_TIMEOUT_MASK 0x8
+#define GC_USB_DIEPINT14_TIMEOUT_SIZE 0x1
+#define GC_USB_DIEPINT14_TIMEOUT_DEFAULT 0x0
+#define GC_USB_DIEPINT14_TIMEOUT_OFFSET 0xac8
+#define GC_USB_DIEPINT14_INTKNTXFEMP_LSB 0x4
+#define GC_USB_DIEPINT14_INTKNTXFEMP_MASK 0x10
+#define GC_USB_DIEPINT14_INTKNTXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT14_INTKNTXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT14_INTKNTXFEMP_OFFSET 0xac8
+#define GC_USB_DIEPINT14_INTKNEPMIS_LSB 0x5
+#define GC_USB_DIEPINT14_INTKNEPMIS_MASK 0x20
+#define GC_USB_DIEPINT14_INTKNEPMIS_SIZE 0x1
+#define GC_USB_DIEPINT14_INTKNEPMIS_DEFAULT 0x0
+#define GC_USB_DIEPINT14_INTKNEPMIS_OFFSET 0xac8
+#define GC_USB_DIEPINT14_INEPNAKEFF_LSB 0x6
+#define GC_USB_DIEPINT14_INEPNAKEFF_MASK 0x40
+#define GC_USB_DIEPINT14_INEPNAKEFF_SIZE 0x1
+#define GC_USB_DIEPINT14_INEPNAKEFF_DEFAULT 0x0
+#define GC_USB_DIEPINT14_INEPNAKEFF_OFFSET 0xac8
+#define GC_USB_DIEPINT14_TXFEMP_LSB 0x7
+#define GC_USB_DIEPINT14_TXFEMP_MASK 0x80
+#define GC_USB_DIEPINT14_TXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT14_TXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT14_TXFEMP_OFFSET 0xac8
+#define GC_USB_DIEPINT14_TXFIFOUNDRN_LSB 0x8
+#define GC_USB_DIEPINT14_TXFIFOUNDRN_MASK 0x100
+#define GC_USB_DIEPINT14_TXFIFOUNDRN_SIZE 0x1
+#define GC_USB_DIEPINT14_TXFIFOUNDRN_DEFAULT 0x0
+#define GC_USB_DIEPINT14_TXFIFOUNDRN_OFFSET 0xac8
+#define GC_USB_DIEPINT14_BNAINTR_LSB 0x9
+#define GC_USB_DIEPINT14_BNAINTR_MASK 0x200
+#define GC_USB_DIEPINT14_BNAINTR_SIZE 0x1
+#define GC_USB_DIEPINT14_BNAINTR_DEFAULT 0x0
+#define GC_USB_DIEPINT14_BNAINTR_OFFSET 0xac8
+#define GC_USB_DIEPINT14_PKTDRPSTS_LSB 0xb
+#define GC_USB_DIEPINT14_PKTDRPSTS_MASK 0x800
+#define GC_USB_DIEPINT14_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DIEPINT14_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DIEPINT14_PKTDRPSTS_OFFSET 0xac8
+#define GC_USB_DIEPINT14_BBLEERR_LSB 0xc
+#define GC_USB_DIEPINT14_BBLEERR_MASK 0x1000
+#define GC_USB_DIEPINT14_BBLEERR_SIZE 0x1
+#define GC_USB_DIEPINT14_BBLEERR_DEFAULT 0x0
+#define GC_USB_DIEPINT14_BBLEERR_OFFSET 0xac8
+#define GC_USB_DIEPINT14_NAKINTRPT_LSB 0xd
+#define GC_USB_DIEPINT14_NAKINTRPT_MASK 0x2000
+#define GC_USB_DIEPINT14_NAKINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT14_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT14_NAKINTRPT_OFFSET 0xac8
+#define GC_USB_DIEPINT14_NYETINTRPT_LSB 0xe
+#define GC_USB_DIEPINT14_NYETINTRPT_MASK 0x4000
+#define GC_USB_DIEPINT14_NYETINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT14_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT14_NYETINTRPT_OFFSET 0xac8
+#define GC_USB_DIEPTSIZ14_XFERSIZE_LSB 0x0
+#define GC_USB_DIEPTSIZ14_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DIEPTSIZ14_XFERSIZE_SIZE 0x13
+#define GC_USB_DIEPTSIZ14_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ14_XFERSIZE_OFFSET 0xad0
+#define GC_USB_DIEPTSIZ14_PKTCNT_LSB 0x13
+#define GC_USB_DIEPTSIZ14_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DIEPTSIZ14_PKTCNT_SIZE 0xa
+#define GC_USB_DIEPTSIZ14_PKTCNT_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ14_PKTCNT_OFFSET 0xad0
+#define GC_USB_DIEPTSIZ14_MC_LSB 0x1d
+#define GC_USB_DIEPTSIZ14_MC_MASK 0x60000000
+#define GC_USB_DIEPTSIZ14_MC_SIZE 0x2
+#define GC_USB_DIEPTSIZ14_MC_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ14_MC_OFFSET 0xad0
+#define GC_USB_DIEPDMA14_DMAADDR_LSB 0x0
+#define GC_USB_DIEPDMA14_DMAADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMA14_DMAADDR_SIZE 0x20
+#define GC_USB_DIEPDMA14_DMAADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMA14_DMAADDR_OFFSET 0xad4
+#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_LSB 0x0
+#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_MASK 0xffff
+#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_SIZE 0x10
 #define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_DEFAULT 0x0
-#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_OFFSET  0xad8
-#define GC_USB_DIEPDMAB14_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DIEPDMAB14_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DIEPDMAB14_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DIEPDMAB14_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DIEPDMAB14_DMABUFFERADDR_OFFSET   0xadc
-#define GC_USB_DIEPCTL15_MPS_LSB                 0x0
-#define GC_USB_DIEPCTL15_MPS_MASK                0x7ff
-#define GC_USB_DIEPCTL15_MPS_SIZE                0xb
-#define GC_USB_DIEPCTL15_MPS_DEFAULT             0x0
-#define GC_USB_DIEPCTL15_MPS_OFFSET              0xae0
-#define GC_USB_DIEPCTL15_USBACTEP_LSB            0xf
-#define GC_USB_DIEPCTL15_USBACTEP_MASK           0x8000
-#define GC_USB_DIEPCTL15_USBACTEP_SIZE           0x1
-#define GC_USB_DIEPCTL15_USBACTEP_DEFAULT        0x0
-#define GC_USB_DIEPCTL15_USBACTEP_OFFSET         0xae0
-#define GC_USB_DIEPCTL15_DPID_LSB                0x10
-#define GC_USB_DIEPCTL15_DPID_MASK               0x10000
-#define GC_USB_DIEPCTL15_DPID_SIZE               0x1
-#define GC_USB_DIEPCTL15_DPID_DEFAULT            0x0
-#define GC_USB_DIEPCTL15_DPID_OFFSET             0xae0
-#define GC_USB_DIEPCTL15_NAKSTS_LSB              0x11
-#define GC_USB_DIEPCTL15_NAKSTS_MASK             0x20000
-#define GC_USB_DIEPCTL15_NAKSTS_SIZE             0x1
-#define GC_USB_DIEPCTL15_NAKSTS_DEFAULT          0x0
-#define GC_USB_DIEPCTL15_NAKSTS_OFFSET           0xae0
-#define GC_USB_DIEPCTL15_EPTYPE_LSB              0x12
-#define GC_USB_DIEPCTL15_EPTYPE_MASK             0xc0000
-#define GC_USB_DIEPCTL15_EPTYPE_SIZE             0x2
-#define GC_USB_DIEPCTL15_EPTYPE_DEFAULT          0x0
-#define GC_USB_DIEPCTL15_EPTYPE_OFFSET           0xae0
-#define GC_USB_DIEPCTL15_STALL_LSB               0x15
-#define GC_USB_DIEPCTL15_STALL_MASK              0x200000
-#define GC_USB_DIEPCTL15_STALL_SIZE              0x1
-#define GC_USB_DIEPCTL15_STALL_DEFAULT           0x0
-#define GC_USB_DIEPCTL15_STALL_OFFSET            0xae0
-#define GC_USB_DIEPCTL15_TXFNUM_LSB              0x16
-#define GC_USB_DIEPCTL15_TXFNUM_MASK             0x3c00000
-#define GC_USB_DIEPCTL15_TXFNUM_SIZE             0x4
-#define GC_USB_DIEPCTL15_TXFNUM_DEFAULT          0x0
-#define GC_USB_DIEPCTL15_TXFNUM_OFFSET           0xae0
-#define GC_USB_DIEPCTL15_CNAK_LSB                0x1a
-#define GC_USB_DIEPCTL15_CNAK_MASK               0x4000000
-#define GC_USB_DIEPCTL15_CNAK_SIZE               0x1
-#define GC_USB_DIEPCTL15_CNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL15_CNAK_OFFSET             0xae0
-#define GC_USB_DIEPCTL15_SNAK_LSB                0x1b
-#define GC_USB_DIEPCTL15_SNAK_MASK               0x8000000
-#define GC_USB_DIEPCTL15_SNAK_SIZE               0x1
-#define GC_USB_DIEPCTL15_SNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL15_SNAK_OFFSET             0xae0
-#define GC_USB_DIEPCTL15_SETD0PID_LSB            0x1c
-#define GC_USB_DIEPCTL15_SETD0PID_MASK           0x10000000
-#define GC_USB_DIEPCTL15_SETD0PID_SIZE           0x1
-#define GC_USB_DIEPCTL15_SETD0PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL15_SETD0PID_OFFSET         0xae0
-#define GC_USB_DIEPCTL15_SETD1PID_LSB            0x1d
-#define GC_USB_DIEPCTL15_SETD1PID_MASK           0x20000000
-#define GC_USB_DIEPCTL15_SETD1PID_SIZE           0x1
-#define GC_USB_DIEPCTL15_SETD1PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL15_SETD1PID_OFFSET         0xae0
-#define GC_USB_DIEPCTL15_EPDIS_LSB               0x1e
-#define GC_USB_DIEPCTL15_EPDIS_MASK              0x40000000
-#define GC_USB_DIEPCTL15_EPDIS_SIZE              0x1
-#define GC_USB_DIEPCTL15_EPDIS_DEFAULT           0x0
-#define GC_USB_DIEPCTL15_EPDIS_OFFSET            0xae0
-#define GC_USB_DIEPCTL15_EPENA_LSB               0x1f
-#define GC_USB_DIEPCTL15_EPENA_MASK              0x80000000
-#define GC_USB_DIEPCTL15_EPENA_SIZE              0x1
-#define GC_USB_DIEPCTL15_EPENA_DEFAULT           0x0
-#define GC_USB_DIEPCTL15_EPENA_OFFSET            0xae0
-#define GC_USB_DIEPINT15_XFERCOMPL_LSB           0x0
-#define GC_USB_DIEPINT15_XFERCOMPL_MASK          0x1
-#define GC_USB_DIEPINT15_XFERCOMPL_SIZE          0x1
-#define GC_USB_DIEPINT15_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DIEPINT15_XFERCOMPL_OFFSET        0xae8
-#define GC_USB_DIEPINT15_EPDISBLD_LSB            0x1
-#define GC_USB_DIEPINT15_EPDISBLD_MASK           0x2
-#define GC_USB_DIEPINT15_EPDISBLD_SIZE           0x1
-#define GC_USB_DIEPINT15_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DIEPINT15_EPDISBLD_OFFSET         0xae8
-#define GC_USB_DIEPINT15_AHBERR_LSB              0x2
-#define GC_USB_DIEPINT15_AHBERR_MASK             0x4
-#define GC_USB_DIEPINT15_AHBERR_SIZE             0x1
-#define GC_USB_DIEPINT15_AHBERR_DEFAULT          0x0
-#define GC_USB_DIEPINT15_AHBERR_OFFSET           0xae8
-#define GC_USB_DIEPINT15_TIMEOUT_LSB             0x3
-#define GC_USB_DIEPINT15_TIMEOUT_MASK            0x8
-#define GC_USB_DIEPINT15_TIMEOUT_SIZE            0x1
-#define GC_USB_DIEPINT15_TIMEOUT_DEFAULT         0x0
-#define GC_USB_DIEPINT15_TIMEOUT_OFFSET          0xae8
-#define GC_USB_DIEPINT15_INTKNTXFEMP_LSB         0x4
-#define GC_USB_DIEPINT15_INTKNTXFEMP_MASK        0x10
-#define GC_USB_DIEPINT15_INTKNTXFEMP_SIZE        0x1
-#define GC_USB_DIEPINT15_INTKNTXFEMP_DEFAULT     0x0
-#define GC_USB_DIEPINT15_INTKNTXFEMP_OFFSET      0xae8
-#define GC_USB_DIEPINT15_INTKNEPMIS_LSB          0x5
-#define GC_USB_DIEPINT15_INTKNEPMIS_MASK         0x20
-#define GC_USB_DIEPINT15_INTKNEPMIS_SIZE         0x1
-#define GC_USB_DIEPINT15_INTKNEPMIS_DEFAULT      0x0
-#define GC_USB_DIEPINT15_INTKNEPMIS_OFFSET       0xae8
-#define GC_USB_DIEPINT15_INEPNAKEFF_LSB          0x6
-#define GC_USB_DIEPINT15_INEPNAKEFF_MASK         0x40
-#define GC_USB_DIEPINT15_INEPNAKEFF_SIZE         0x1
-#define GC_USB_DIEPINT15_INEPNAKEFF_DEFAULT      0x0
-#define GC_USB_DIEPINT15_INEPNAKEFF_OFFSET       0xae8
-#define GC_USB_DIEPINT15_TXFEMP_LSB              0x7
-#define GC_USB_DIEPINT15_TXFEMP_MASK             0x80
-#define GC_USB_DIEPINT15_TXFEMP_SIZE             0x1
-#define GC_USB_DIEPINT15_TXFEMP_DEFAULT          0x0
-#define GC_USB_DIEPINT15_TXFEMP_OFFSET           0xae8
-#define GC_USB_DIEPINT15_TXFIFOUNDRN_LSB         0x8
-#define GC_USB_DIEPINT15_TXFIFOUNDRN_MASK        0x100
-#define GC_USB_DIEPINT15_TXFIFOUNDRN_SIZE        0x1
-#define GC_USB_DIEPINT15_TXFIFOUNDRN_DEFAULT     0x0
-#define GC_USB_DIEPINT15_TXFIFOUNDRN_OFFSET      0xae8
-#define GC_USB_DIEPINT15_BNAINTR_LSB             0x9
-#define GC_USB_DIEPINT15_BNAINTR_MASK            0x200
-#define GC_USB_DIEPINT15_BNAINTR_SIZE            0x1
-#define GC_USB_DIEPINT15_BNAINTR_DEFAULT         0x0
-#define GC_USB_DIEPINT15_BNAINTR_OFFSET          0xae8
-#define GC_USB_DIEPINT15_PKTDRPSTS_LSB           0xb
-#define GC_USB_DIEPINT15_PKTDRPSTS_MASK          0x800
-#define GC_USB_DIEPINT15_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DIEPINT15_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DIEPINT15_PKTDRPSTS_OFFSET        0xae8
-#define GC_USB_DIEPINT15_BBLEERR_LSB             0xc
-#define GC_USB_DIEPINT15_BBLEERR_MASK            0x1000
-#define GC_USB_DIEPINT15_BBLEERR_SIZE            0x1
-#define GC_USB_DIEPINT15_BBLEERR_DEFAULT         0x0
-#define GC_USB_DIEPINT15_BBLEERR_OFFSET          0xae8
-#define GC_USB_DIEPINT15_NAKINTRPT_LSB           0xd
-#define GC_USB_DIEPINT15_NAKINTRPT_MASK          0x2000
-#define GC_USB_DIEPINT15_NAKINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT15_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT15_NAKINTRPT_OFFSET        0xae8
-#define GC_USB_DIEPINT15_NYETINTRPT_LSB          0xe
-#define GC_USB_DIEPINT15_NYETINTRPT_MASK         0x4000
-#define GC_USB_DIEPINT15_NYETINTRPT_SIZE         0x1
-#define GC_USB_DIEPINT15_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DIEPINT15_NYETINTRPT_OFFSET       0xae8
-#define GC_USB_DIEPTSIZ15_XFERSIZE_LSB           0x0
-#define GC_USB_DIEPTSIZ15_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DIEPTSIZ15_XFERSIZE_SIZE          0x13
-#define GC_USB_DIEPTSIZ15_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DIEPTSIZ15_XFERSIZE_OFFSET        0xaf0
-#define GC_USB_DIEPTSIZ15_PKTCNT_LSB             0x13
-#define GC_USB_DIEPTSIZ15_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DIEPTSIZ15_PKTCNT_SIZE            0xa
-#define GC_USB_DIEPTSIZ15_PKTCNT_DEFAULT         0x0
-#define GC_USB_DIEPTSIZ15_PKTCNT_OFFSET          0xaf0
-#define GC_USB_DIEPTSIZ15_MC_LSB                 0x1d
-#define GC_USB_DIEPTSIZ15_MC_MASK                0x60000000
-#define GC_USB_DIEPTSIZ15_MC_SIZE                0x2
-#define GC_USB_DIEPTSIZ15_MC_DEFAULT             0x0
-#define GC_USB_DIEPTSIZ15_MC_OFFSET              0xaf0
-#define GC_USB_DIEPDMA15_DMAADDR_LSB             0x0
-#define GC_USB_DIEPDMA15_DMAADDR_MASK            0xffffffff
-#define GC_USB_DIEPDMA15_DMAADDR_SIZE            0x20
-#define GC_USB_DIEPDMA15_DMAADDR_DEFAULT         0x0
-#define GC_USB_DIEPDMA15_DMAADDR_OFFSET          0xaf4
-#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_LSB     0x0
-#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_MASK    0xffff
-#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_SIZE    0x10
+#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_OFFSET 0xad8
+#define GC_USB_DIEPDMAB14_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DIEPDMAB14_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMAB14_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DIEPDMAB14_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMAB14_DMABUFFERADDR_OFFSET 0xadc
+#define GC_USB_DIEPCTL15_MPS_LSB 0x0
+#define GC_USB_DIEPCTL15_MPS_MASK 0x7ff
+#define GC_USB_DIEPCTL15_MPS_SIZE 0xb
+#define GC_USB_DIEPCTL15_MPS_DEFAULT 0x0
+#define GC_USB_DIEPCTL15_MPS_OFFSET 0xae0
+#define GC_USB_DIEPCTL15_USBACTEP_LSB 0xf
+#define GC_USB_DIEPCTL15_USBACTEP_MASK 0x8000
+#define GC_USB_DIEPCTL15_USBACTEP_SIZE 0x1
+#define GC_USB_DIEPCTL15_USBACTEP_DEFAULT 0x0
+#define GC_USB_DIEPCTL15_USBACTEP_OFFSET 0xae0
+#define GC_USB_DIEPCTL15_DPID_LSB 0x10
+#define GC_USB_DIEPCTL15_DPID_MASK 0x10000
+#define GC_USB_DIEPCTL15_DPID_SIZE 0x1
+#define GC_USB_DIEPCTL15_DPID_DEFAULT 0x0
+#define GC_USB_DIEPCTL15_DPID_OFFSET 0xae0
+#define GC_USB_DIEPCTL15_NAKSTS_LSB 0x11
+#define GC_USB_DIEPCTL15_NAKSTS_MASK 0x20000
+#define GC_USB_DIEPCTL15_NAKSTS_SIZE 0x1
+#define GC_USB_DIEPCTL15_NAKSTS_DEFAULT 0x0
+#define GC_USB_DIEPCTL15_NAKSTS_OFFSET 0xae0
+#define GC_USB_DIEPCTL15_EPTYPE_LSB 0x12
+#define GC_USB_DIEPCTL15_EPTYPE_MASK 0xc0000
+#define GC_USB_DIEPCTL15_EPTYPE_SIZE 0x2
+#define GC_USB_DIEPCTL15_EPTYPE_DEFAULT 0x0
+#define GC_USB_DIEPCTL15_EPTYPE_OFFSET 0xae0
+#define GC_USB_DIEPCTL15_STALL_LSB 0x15
+#define GC_USB_DIEPCTL15_STALL_MASK 0x200000
+#define GC_USB_DIEPCTL15_STALL_SIZE 0x1
+#define GC_USB_DIEPCTL15_STALL_DEFAULT 0x0
+#define GC_USB_DIEPCTL15_STALL_OFFSET 0xae0
+#define GC_USB_DIEPCTL15_TXFNUM_LSB 0x16
+#define GC_USB_DIEPCTL15_TXFNUM_MASK 0x3c00000
+#define GC_USB_DIEPCTL15_TXFNUM_SIZE 0x4
+#define GC_USB_DIEPCTL15_TXFNUM_DEFAULT 0x0
+#define GC_USB_DIEPCTL15_TXFNUM_OFFSET 0xae0
+#define GC_USB_DIEPCTL15_CNAK_LSB 0x1a
+#define GC_USB_DIEPCTL15_CNAK_MASK 0x4000000
+#define GC_USB_DIEPCTL15_CNAK_SIZE 0x1
+#define GC_USB_DIEPCTL15_CNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL15_CNAK_OFFSET 0xae0
+#define GC_USB_DIEPCTL15_SNAK_LSB 0x1b
+#define GC_USB_DIEPCTL15_SNAK_MASK 0x8000000
+#define GC_USB_DIEPCTL15_SNAK_SIZE 0x1
+#define GC_USB_DIEPCTL15_SNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL15_SNAK_OFFSET 0xae0
+#define GC_USB_DIEPCTL15_SETD0PID_LSB 0x1c
+#define GC_USB_DIEPCTL15_SETD0PID_MASK 0x10000000
+#define GC_USB_DIEPCTL15_SETD0PID_SIZE 0x1
+#define GC_USB_DIEPCTL15_SETD0PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL15_SETD0PID_OFFSET 0xae0
+#define GC_USB_DIEPCTL15_SETD1PID_LSB 0x1d
+#define GC_USB_DIEPCTL15_SETD1PID_MASK 0x20000000
+#define GC_USB_DIEPCTL15_SETD1PID_SIZE 0x1
+#define GC_USB_DIEPCTL15_SETD1PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL15_SETD1PID_OFFSET 0xae0
+#define GC_USB_DIEPCTL15_EPDIS_LSB 0x1e
+#define GC_USB_DIEPCTL15_EPDIS_MASK 0x40000000
+#define GC_USB_DIEPCTL15_EPDIS_SIZE 0x1
+#define GC_USB_DIEPCTL15_EPDIS_DEFAULT 0x0
+#define GC_USB_DIEPCTL15_EPDIS_OFFSET 0xae0
+#define GC_USB_DIEPCTL15_EPENA_LSB 0x1f
+#define GC_USB_DIEPCTL15_EPENA_MASK 0x80000000
+#define GC_USB_DIEPCTL15_EPENA_SIZE 0x1
+#define GC_USB_DIEPCTL15_EPENA_DEFAULT 0x0
+#define GC_USB_DIEPCTL15_EPENA_OFFSET 0xae0
+#define GC_USB_DIEPINT15_XFERCOMPL_LSB 0x0
+#define GC_USB_DIEPINT15_XFERCOMPL_MASK 0x1
+#define GC_USB_DIEPINT15_XFERCOMPL_SIZE 0x1
+#define GC_USB_DIEPINT15_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DIEPINT15_XFERCOMPL_OFFSET 0xae8
+#define GC_USB_DIEPINT15_EPDISBLD_LSB 0x1
+#define GC_USB_DIEPINT15_EPDISBLD_MASK 0x2
+#define GC_USB_DIEPINT15_EPDISBLD_SIZE 0x1
+#define GC_USB_DIEPINT15_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DIEPINT15_EPDISBLD_OFFSET 0xae8
+#define GC_USB_DIEPINT15_AHBERR_LSB 0x2
+#define GC_USB_DIEPINT15_AHBERR_MASK 0x4
+#define GC_USB_DIEPINT15_AHBERR_SIZE 0x1
+#define GC_USB_DIEPINT15_AHBERR_DEFAULT 0x0
+#define GC_USB_DIEPINT15_AHBERR_OFFSET 0xae8
+#define GC_USB_DIEPINT15_TIMEOUT_LSB 0x3
+#define GC_USB_DIEPINT15_TIMEOUT_MASK 0x8
+#define GC_USB_DIEPINT15_TIMEOUT_SIZE 0x1
+#define GC_USB_DIEPINT15_TIMEOUT_DEFAULT 0x0
+#define GC_USB_DIEPINT15_TIMEOUT_OFFSET 0xae8
+#define GC_USB_DIEPINT15_INTKNTXFEMP_LSB 0x4
+#define GC_USB_DIEPINT15_INTKNTXFEMP_MASK 0x10
+#define GC_USB_DIEPINT15_INTKNTXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT15_INTKNTXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT15_INTKNTXFEMP_OFFSET 0xae8
+#define GC_USB_DIEPINT15_INTKNEPMIS_LSB 0x5
+#define GC_USB_DIEPINT15_INTKNEPMIS_MASK 0x20
+#define GC_USB_DIEPINT15_INTKNEPMIS_SIZE 0x1
+#define GC_USB_DIEPINT15_INTKNEPMIS_DEFAULT 0x0
+#define GC_USB_DIEPINT15_INTKNEPMIS_OFFSET 0xae8
+#define GC_USB_DIEPINT15_INEPNAKEFF_LSB 0x6
+#define GC_USB_DIEPINT15_INEPNAKEFF_MASK 0x40
+#define GC_USB_DIEPINT15_INEPNAKEFF_SIZE 0x1
+#define GC_USB_DIEPINT15_INEPNAKEFF_DEFAULT 0x0
+#define GC_USB_DIEPINT15_INEPNAKEFF_OFFSET 0xae8
+#define GC_USB_DIEPINT15_TXFEMP_LSB 0x7
+#define GC_USB_DIEPINT15_TXFEMP_MASK 0x80
+#define GC_USB_DIEPINT15_TXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT15_TXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT15_TXFEMP_OFFSET 0xae8
+#define GC_USB_DIEPINT15_TXFIFOUNDRN_LSB 0x8
+#define GC_USB_DIEPINT15_TXFIFOUNDRN_MASK 0x100
+#define GC_USB_DIEPINT15_TXFIFOUNDRN_SIZE 0x1
+#define GC_USB_DIEPINT15_TXFIFOUNDRN_DEFAULT 0x0
+#define GC_USB_DIEPINT15_TXFIFOUNDRN_OFFSET 0xae8
+#define GC_USB_DIEPINT15_BNAINTR_LSB 0x9
+#define GC_USB_DIEPINT15_BNAINTR_MASK 0x200
+#define GC_USB_DIEPINT15_BNAINTR_SIZE 0x1
+#define GC_USB_DIEPINT15_BNAINTR_DEFAULT 0x0
+#define GC_USB_DIEPINT15_BNAINTR_OFFSET 0xae8
+#define GC_USB_DIEPINT15_PKTDRPSTS_LSB 0xb
+#define GC_USB_DIEPINT15_PKTDRPSTS_MASK 0x800
+#define GC_USB_DIEPINT15_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DIEPINT15_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DIEPINT15_PKTDRPSTS_OFFSET 0xae8
+#define GC_USB_DIEPINT15_BBLEERR_LSB 0xc
+#define GC_USB_DIEPINT15_BBLEERR_MASK 0x1000
+#define GC_USB_DIEPINT15_BBLEERR_SIZE 0x1
+#define GC_USB_DIEPINT15_BBLEERR_DEFAULT 0x0
+#define GC_USB_DIEPINT15_BBLEERR_OFFSET 0xae8
+#define GC_USB_DIEPINT15_NAKINTRPT_LSB 0xd
+#define GC_USB_DIEPINT15_NAKINTRPT_MASK 0x2000
+#define GC_USB_DIEPINT15_NAKINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT15_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT15_NAKINTRPT_OFFSET 0xae8
+#define GC_USB_DIEPINT15_NYETINTRPT_LSB 0xe
+#define GC_USB_DIEPINT15_NYETINTRPT_MASK 0x4000
+#define GC_USB_DIEPINT15_NYETINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT15_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT15_NYETINTRPT_OFFSET 0xae8
+#define GC_USB_DIEPTSIZ15_XFERSIZE_LSB 0x0
+#define GC_USB_DIEPTSIZ15_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DIEPTSIZ15_XFERSIZE_SIZE 0x13
+#define GC_USB_DIEPTSIZ15_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ15_XFERSIZE_OFFSET 0xaf0
+#define GC_USB_DIEPTSIZ15_PKTCNT_LSB 0x13
+#define GC_USB_DIEPTSIZ15_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DIEPTSIZ15_PKTCNT_SIZE 0xa
+#define GC_USB_DIEPTSIZ15_PKTCNT_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ15_PKTCNT_OFFSET 0xaf0
+#define GC_USB_DIEPTSIZ15_MC_LSB 0x1d
+#define GC_USB_DIEPTSIZ15_MC_MASK 0x60000000
+#define GC_USB_DIEPTSIZ15_MC_SIZE 0x2
+#define GC_USB_DIEPTSIZ15_MC_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ15_MC_OFFSET 0xaf0
+#define GC_USB_DIEPDMA15_DMAADDR_LSB 0x0
+#define GC_USB_DIEPDMA15_DMAADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMA15_DMAADDR_SIZE 0x20
+#define GC_USB_DIEPDMA15_DMAADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMA15_DMAADDR_OFFSET 0xaf4
+#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_LSB 0x0
+#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_MASK 0xffff
+#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_SIZE 0x10
 #define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_DEFAULT 0x0
-#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_OFFSET  0xaf8
-#define GC_USB_DIEPDMAB15_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DIEPDMAB15_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DIEPDMAB15_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DIEPDMAB15_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DIEPDMAB15_DMABUFFERADDR_OFFSET   0xafc
-#define GC_USB_DOEPCTL0_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL0_MPS_MASK                 0x3
-#define GC_USB_DOEPCTL0_MPS_SIZE                 0x2
-#define GC_USB_DOEPCTL0_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL0_MPS_OFFSET               0xb00
-#define GC_USB_DOEPCTL0_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL0_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL0_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL0_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL0_USBACTEP_OFFSET          0xb00
-#define GC_USB_DOEPCTL0_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL0_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL0_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL0_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL0_NAKSTS_OFFSET            0xb00
-#define GC_USB_DOEPCTL0_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL0_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL0_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL0_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL0_EPTYPE_OFFSET            0xb00
-#define GC_USB_DOEPCTL0_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL0_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL0_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL0_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL0_SNP_OFFSET               0xb00
-#define GC_USB_DOEPCTL0_STALL_LSB                0x15
-#define GC_USB_DOEPCTL0_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL0_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL0_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL0_STALL_OFFSET             0xb00
-#define GC_USB_DOEPCTL0_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL0_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL0_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL0_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL0_CNAK_OFFSET              0xb00
-#define GC_USB_DOEPCTL0_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL0_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL0_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL0_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL0_SNAK_OFFSET              0xb00
-#define GC_USB_DOEPCTL0_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL0_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL0_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL0_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL0_EPDIS_OFFSET             0xb00
-#define GC_USB_DOEPCTL0_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL0_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL0_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL0_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL0_EPENA_OFFSET             0xb00
-#define GC_USB_DOEPINT0_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT0_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT0_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT0_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT0_XFERCOMPL_OFFSET         0xb08
-#define GC_USB_DOEPINT0_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT0_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT0_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT0_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT0_EPDISBLD_OFFSET          0xb08
-#define GC_USB_DOEPINT0_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT0_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT0_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT0_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT0_AHBERR_OFFSET            0xb08
-#define GC_USB_DOEPINT0_SETUP_LSB                0x3
-#define GC_USB_DOEPINT0_SETUP_MASK               0x8
-#define GC_USB_DOEPINT0_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT0_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT0_SETUP_OFFSET             0xb08
-#define GC_USB_DOEPINT0_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT0_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT0_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT0_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT0_OUTTKNEPDIS_OFFSET       0xb08
-#define GC_USB_DOEPINT0_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT0_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT0_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT0_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT0_STSPHSERCVD_OFFSET       0xb08
-#define GC_USB_DOEPINT0_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT0_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT0_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT0_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT0_BACK2BACKSETUP_OFFSET    0xb08
-#define GC_USB_DOEPINT0_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT0_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT0_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT0_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT0_OUTPKTERR_OFFSET         0xb08
-#define GC_USB_DOEPINT0_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT0_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT0_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT0_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT0_BNAINTR_OFFSET           0xb08
-#define GC_USB_DOEPINT0_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT0_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT0_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT0_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT0_PKTDRPSTS_OFFSET         0xb08
-#define GC_USB_DOEPINT0_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT0_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT0_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT0_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT0_BBLEERR_OFFSET           0xb08
-#define GC_USB_DOEPINT0_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT0_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT0_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT0_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT0_NAKINTRPT_OFFSET         0xb08
-#define GC_USB_DOEPINT0_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT0_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT0_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT0_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT0_NYETINTRPT_OFFSET        0xb08
-#define GC_USB_DOEPINT0_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT0_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT0_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT0_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT0_STUPPKTRCVD_OFFSET       0xb08
-#define GC_USB_DOEPTSIZ0_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ0_XFERSIZE_MASK           0x7f
-#define GC_USB_DOEPTSIZ0_XFERSIZE_SIZE           0x7
-#define GC_USB_DOEPTSIZ0_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ0_XFERSIZE_OFFSET         0xb10
-#define GC_USB_DOEPTSIZ0_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ0_PKTCNT_MASK             0x80000
-#define GC_USB_DOEPTSIZ0_PKTCNT_SIZE             0x1
-#define GC_USB_DOEPTSIZ0_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ0_PKTCNT_OFFSET           0xb10
-#define GC_USB_DOEPTSIZ0_SUPCNT_LSB              0x1d
-#define GC_USB_DOEPTSIZ0_SUPCNT_MASK             0x60000000
-#define GC_USB_DOEPTSIZ0_SUPCNT_SIZE             0x2
-#define GC_USB_DOEPTSIZ0_SUPCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ0_SUPCNT_OFFSET           0xb10
-#define GC_USB_DOEPDMA0_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA0_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA0_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA0_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA0_DMAADDR_OFFSET           0xb14
-#define GC_USB_DOEPDMAB0_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB0_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB0_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB0_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB0_DMABUFFERADDR_OFFSET    0xb1c
-#define GC_USB_DOEPCTL1_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL1_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL1_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL1_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL1_MPS_OFFSET               0xb20
-#define GC_USB_DOEPCTL1_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL1_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL1_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL1_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL1_USBACTEP_OFFSET          0xb20
-#define GC_USB_DOEPCTL1_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL1_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL1_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL1_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL1_DPID_OFFSET              0xb20
-#define GC_USB_DOEPCTL1_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL1_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL1_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL1_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL1_NAKSTS_OFFSET            0xb20
-#define GC_USB_DOEPCTL1_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL1_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL1_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL1_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL1_EPTYPE_OFFSET            0xb20
-#define GC_USB_DOEPCTL1_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL1_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL1_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL1_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL1_SNP_OFFSET               0xb20
-#define GC_USB_DOEPCTL1_STALL_LSB                0x15
-#define GC_USB_DOEPCTL1_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL1_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL1_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL1_STALL_OFFSET             0xb20
-#define GC_USB_DOEPCTL1_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL1_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL1_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL1_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL1_CNAK_OFFSET              0xb20
-#define GC_USB_DOEPCTL1_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL1_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL1_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL1_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL1_SNAK_OFFSET              0xb20
-#define GC_USB_DOEPCTL1_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL1_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL1_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL1_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL1_SETD0PID_OFFSET          0xb20
-#define GC_USB_DOEPCTL1_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL1_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL1_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL1_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL1_SETD1PID_OFFSET          0xb20
-#define GC_USB_DOEPCTL1_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL1_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL1_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL1_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL1_EPDIS_OFFSET             0xb20
-#define GC_USB_DOEPCTL1_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL1_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL1_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL1_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL1_EPENA_OFFSET             0xb20
-#define GC_USB_DOEPINT1_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT1_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT1_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT1_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT1_XFERCOMPL_OFFSET         0xb28
-#define GC_USB_DOEPINT1_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT1_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT1_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT1_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT1_EPDISBLD_OFFSET          0xb28
-#define GC_USB_DOEPINT1_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT1_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT1_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT1_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT1_AHBERR_OFFSET            0xb28
-#define GC_USB_DOEPINT1_SETUP_LSB                0x3
-#define GC_USB_DOEPINT1_SETUP_MASK               0x8
-#define GC_USB_DOEPINT1_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT1_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT1_SETUP_OFFSET             0xb28
-#define GC_USB_DOEPINT1_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT1_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT1_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT1_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT1_OUTTKNEPDIS_OFFSET       0xb28
-#define GC_USB_DOEPINT1_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT1_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT1_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT1_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT1_STSPHSERCVD_OFFSET       0xb28
-#define GC_USB_DOEPINT1_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT1_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT1_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT1_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT1_BACK2BACKSETUP_OFFSET    0xb28
-#define GC_USB_DOEPINT1_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT1_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT1_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT1_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT1_OUTPKTERR_OFFSET         0xb28
-#define GC_USB_DOEPINT1_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT1_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT1_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT1_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT1_BNAINTR_OFFSET           0xb28
-#define GC_USB_DOEPINT1_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT1_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT1_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT1_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT1_PKTDRPSTS_OFFSET         0xb28
-#define GC_USB_DOEPINT1_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT1_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT1_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT1_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT1_BBLEERR_OFFSET           0xb28
-#define GC_USB_DOEPINT1_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT1_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT1_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT1_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT1_NAKINTRPT_OFFSET         0xb28
-#define GC_USB_DOEPINT1_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT1_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT1_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT1_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT1_NYETINTRPT_OFFSET        0xb28
-#define GC_USB_DOEPINT1_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT1_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT1_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT1_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT1_STUPPKTRCVD_OFFSET       0xb28
-#define GC_USB_DOEPTSIZ1_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ1_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ1_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ1_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ1_XFERSIZE_OFFSET         0xb30
-#define GC_USB_DOEPTSIZ1_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ1_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ1_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ1_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ1_PKTCNT_OFFSET           0xb30
-#define GC_USB_DOEPTSIZ1_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ1_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ1_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ1_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ1_RXDPID_OFFSET           0xb30
-#define GC_USB_DOEPDMA1_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA1_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA1_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA1_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA1_DMAADDR_OFFSET           0xb34
-#define GC_USB_DOEPDMAB1_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB1_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB1_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB1_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB1_DMABUFFERADDR_OFFSET    0xb3c
-#define GC_USB_DOEPCTL2_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL2_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL2_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL2_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL2_MPS_OFFSET               0xb40
-#define GC_USB_DOEPCTL2_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL2_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL2_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL2_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL2_USBACTEP_OFFSET          0xb40
-#define GC_USB_DOEPCTL2_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL2_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL2_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL2_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL2_DPID_OFFSET              0xb40
-#define GC_USB_DOEPCTL2_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL2_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL2_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL2_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL2_NAKSTS_OFFSET            0xb40
-#define GC_USB_DOEPCTL2_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL2_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL2_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL2_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL2_EPTYPE_OFFSET            0xb40
-#define GC_USB_DOEPCTL2_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL2_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL2_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL2_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL2_SNP_OFFSET               0xb40
-#define GC_USB_DOEPCTL2_STALL_LSB                0x15
-#define GC_USB_DOEPCTL2_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL2_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL2_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL2_STALL_OFFSET             0xb40
-#define GC_USB_DOEPCTL2_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL2_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL2_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL2_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL2_CNAK_OFFSET              0xb40
-#define GC_USB_DOEPCTL2_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL2_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL2_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL2_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL2_SNAK_OFFSET              0xb40
-#define GC_USB_DOEPCTL2_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL2_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL2_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL2_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL2_SETD0PID_OFFSET          0xb40
-#define GC_USB_DOEPCTL2_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL2_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL2_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL2_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL2_SETD1PID_OFFSET          0xb40
-#define GC_USB_DOEPCTL2_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL2_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL2_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL2_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL2_EPDIS_OFFSET             0xb40
-#define GC_USB_DOEPCTL2_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL2_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL2_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL2_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL2_EPENA_OFFSET             0xb40
-#define GC_USB_DOEPINT2_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT2_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT2_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT2_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT2_XFERCOMPL_OFFSET         0xb48
-#define GC_USB_DOEPINT2_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT2_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT2_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT2_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT2_EPDISBLD_OFFSET          0xb48
-#define GC_USB_DOEPINT2_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT2_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT2_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT2_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT2_AHBERR_OFFSET            0xb48
-#define GC_USB_DOEPINT2_SETUP_LSB                0x3
-#define GC_USB_DOEPINT2_SETUP_MASK               0x8
-#define GC_USB_DOEPINT2_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT2_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT2_SETUP_OFFSET             0xb48
-#define GC_USB_DOEPINT2_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT2_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT2_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT2_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT2_OUTTKNEPDIS_OFFSET       0xb48
-#define GC_USB_DOEPINT2_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT2_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT2_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT2_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT2_STSPHSERCVD_OFFSET       0xb48
-#define GC_USB_DOEPINT2_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT2_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT2_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT2_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT2_BACK2BACKSETUP_OFFSET    0xb48
-#define GC_USB_DOEPINT2_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT2_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT2_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT2_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT2_OUTPKTERR_OFFSET         0xb48
-#define GC_USB_DOEPINT2_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT2_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT2_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT2_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT2_BNAINTR_OFFSET           0xb48
-#define GC_USB_DOEPINT2_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT2_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT2_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT2_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT2_PKTDRPSTS_OFFSET         0xb48
-#define GC_USB_DOEPINT2_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT2_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT2_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT2_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT2_BBLEERR_OFFSET           0xb48
-#define GC_USB_DOEPINT2_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT2_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT2_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT2_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT2_NAKINTRPT_OFFSET         0xb48
-#define GC_USB_DOEPINT2_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT2_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT2_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT2_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT2_NYETINTRPT_OFFSET        0xb48
-#define GC_USB_DOEPINT2_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT2_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT2_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT2_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT2_STUPPKTRCVD_OFFSET       0xb48
-#define GC_USB_DOEPTSIZ2_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ2_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ2_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ2_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ2_XFERSIZE_OFFSET         0xb50
-#define GC_USB_DOEPTSIZ2_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ2_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ2_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ2_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ2_PKTCNT_OFFSET           0xb50
-#define GC_USB_DOEPTSIZ2_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ2_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ2_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ2_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ2_RXDPID_OFFSET           0xb50
-#define GC_USB_DOEPDMA2_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA2_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA2_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA2_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA2_DMAADDR_OFFSET           0xb54
-#define GC_USB_DOEPDMAB2_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB2_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB2_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB2_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB2_DMABUFFERADDR_OFFSET    0xb5c
-#define GC_USB_DOEPCTL3_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL3_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL3_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL3_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL3_MPS_OFFSET               0xb60
-#define GC_USB_DOEPCTL3_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL3_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL3_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL3_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL3_USBACTEP_OFFSET          0xb60
-#define GC_USB_DOEPCTL3_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL3_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL3_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL3_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL3_DPID_OFFSET              0xb60
-#define GC_USB_DOEPCTL3_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL3_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL3_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL3_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL3_NAKSTS_OFFSET            0xb60
-#define GC_USB_DOEPCTL3_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL3_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL3_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL3_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL3_EPTYPE_OFFSET            0xb60
-#define GC_USB_DOEPCTL3_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL3_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL3_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL3_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL3_SNP_OFFSET               0xb60
-#define GC_USB_DOEPCTL3_STALL_LSB                0x15
-#define GC_USB_DOEPCTL3_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL3_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL3_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL3_STALL_OFFSET             0xb60
-#define GC_USB_DOEPCTL3_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL3_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL3_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL3_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL3_CNAK_OFFSET              0xb60
-#define GC_USB_DOEPCTL3_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL3_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL3_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL3_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL3_SNAK_OFFSET              0xb60
-#define GC_USB_DOEPCTL3_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL3_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL3_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL3_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL3_SETD0PID_OFFSET          0xb60
-#define GC_USB_DOEPCTL3_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL3_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL3_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL3_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL3_SETD1PID_OFFSET          0xb60
-#define GC_USB_DOEPCTL3_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL3_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL3_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL3_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL3_EPDIS_OFFSET             0xb60
-#define GC_USB_DOEPCTL3_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL3_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL3_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL3_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL3_EPENA_OFFSET             0xb60
-#define GC_USB_DOEPINT3_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT3_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT3_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT3_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT3_XFERCOMPL_OFFSET         0xb68
-#define GC_USB_DOEPINT3_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT3_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT3_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT3_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT3_EPDISBLD_OFFSET          0xb68
-#define GC_USB_DOEPINT3_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT3_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT3_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT3_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT3_AHBERR_OFFSET            0xb68
-#define GC_USB_DOEPINT3_SETUP_LSB                0x3
-#define GC_USB_DOEPINT3_SETUP_MASK               0x8
-#define GC_USB_DOEPINT3_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT3_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT3_SETUP_OFFSET             0xb68
-#define GC_USB_DOEPINT3_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT3_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT3_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT3_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT3_OUTTKNEPDIS_OFFSET       0xb68
-#define GC_USB_DOEPINT3_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT3_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT3_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT3_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT3_STSPHSERCVD_OFFSET       0xb68
-#define GC_USB_DOEPINT3_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT3_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT3_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT3_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT3_BACK2BACKSETUP_OFFSET    0xb68
-#define GC_USB_DOEPINT3_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT3_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT3_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT3_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT3_OUTPKTERR_OFFSET         0xb68
-#define GC_USB_DOEPINT3_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT3_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT3_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT3_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT3_BNAINTR_OFFSET           0xb68
-#define GC_USB_DOEPINT3_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT3_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT3_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT3_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT3_PKTDRPSTS_OFFSET         0xb68
-#define GC_USB_DOEPINT3_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT3_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT3_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT3_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT3_BBLEERR_OFFSET           0xb68
-#define GC_USB_DOEPINT3_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT3_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT3_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT3_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT3_NAKINTRPT_OFFSET         0xb68
-#define GC_USB_DOEPINT3_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT3_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT3_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT3_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT3_NYETINTRPT_OFFSET        0xb68
-#define GC_USB_DOEPINT3_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT3_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT3_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT3_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT3_STUPPKTRCVD_OFFSET       0xb68
-#define GC_USB_DOEPTSIZ3_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ3_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ3_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ3_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ3_XFERSIZE_OFFSET         0xb70
-#define GC_USB_DOEPTSIZ3_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ3_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ3_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ3_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ3_PKTCNT_OFFSET           0xb70
-#define GC_USB_DOEPTSIZ3_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ3_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ3_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ3_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ3_RXDPID_OFFSET           0xb70
-#define GC_USB_DOEPDMA3_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA3_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA3_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA3_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA3_DMAADDR_OFFSET           0xb74
-#define GC_USB_DOEPDMAB3_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB3_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB3_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB3_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB3_DMABUFFERADDR_OFFSET    0xb7c
-#define GC_USB_DOEPCTL4_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL4_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL4_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL4_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL4_MPS_OFFSET               0xb80
-#define GC_USB_DOEPCTL4_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL4_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL4_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL4_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL4_USBACTEP_OFFSET          0xb80
-#define GC_USB_DOEPCTL4_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL4_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL4_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL4_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL4_DPID_OFFSET              0xb80
-#define GC_USB_DOEPCTL4_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL4_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL4_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL4_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL4_NAKSTS_OFFSET            0xb80
-#define GC_USB_DOEPCTL4_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL4_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL4_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL4_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL4_EPTYPE_OFFSET            0xb80
-#define GC_USB_DOEPCTL4_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL4_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL4_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL4_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL4_SNP_OFFSET               0xb80
-#define GC_USB_DOEPCTL4_STALL_LSB                0x15
-#define GC_USB_DOEPCTL4_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL4_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL4_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL4_STALL_OFFSET             0xb80
-#define GC_USB_DOEPCTL4_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL4_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL4_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL4_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL4_CNAK_OFFSET              0xb80
-#define GC_USB_DOEPCTL4_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL4_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL4_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL4_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL4_SNAK_OFFSET              0xb80
-#define GC_USB_DOEPCTL4_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL4_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL4_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL4_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL4_SETD0PID_OFFSET          0xb80
-#define GC_USB_DOEPCTL4_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL4_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL4_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL4_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL4_SETD1PID_OFFSET          0xb80
-#define GC_USB_DOEPCTL4_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL4_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL4_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL4_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL4_EPDIS_OFFSET             0xb80
-#define GC_USB_DOEPCTL4_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL4_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL4_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL4_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL4_EPENA_OFFSET             0xb80
-#define GC_USB_DOEPINT4_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT4_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT4_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT4_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT4_XFERCOMPL_OFFSET         0xb88
-#define GC_USB_DOEPINT4_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT4_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT4_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT4_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT4_EPDISBLD_OFFSET          0xb88
-#define GC_USB_DOEPINT4_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT4_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT4_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT4_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT4_AHBERR_OFFSET            0xb88
-#define GC_USB_DOEPINT4_SETUP_LSB                0x3
-#define GC_USB_DOEPINT4_SETUP_MASK               0x8
-#define GC_USB_DOEPINT4_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT4_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT4_SETUP_OFFSET             0xb88
-#define GC_USB_DOEPINT4_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT4_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT4_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT4_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT4_OUTTKNEPDIS_OFFSET       0xb88
-#define GC_USB_DOEPINT4_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT4_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT4_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT4_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT4_STSPHSERCVD_OFFSET       0xb88
-#define GC_USB_DOEPINT4_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT4_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT4_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT4_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT4_BACK2BACKSETUP_OFFSET    0xb88
-#define GC_USB_DOEPINT4_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT4_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT4_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT4_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT4_OUTPKTERR_OFFSET         0xb88
-#define GC_USB_DOEPINT4_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT4_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT4_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT4_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT4_BNAINTR_OFFSET           0xb88
-#define GC_USB_DOEPINT4_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT4_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT4_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT4_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT4_PKTDRPSTS_OFFSET         0xb88
-#define GC_USB_DOEPINT4_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT4_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT4_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT4_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT4_BBLEERR_OFFSET           0xb88
-#define GC_USB_DOEPINT4_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT4_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT4_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT4_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT4_NAKINTRPT_OFFSET         0xb88
-#define GC_USB_DOEPINT4_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT4_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT4_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT4_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT4_NYETINTRPT_OFFSET        0xb88
-#define GC_USB_DOEPINT4_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT4_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT4_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT4_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT4_STUPPKTRCVD_OFFSET       0xb88
-#define GC_USB_DOEPTSIZ4_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ4_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ4_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ4_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ4_XFERSIZE_OFFSET         0xb90
-#define GC_USB_DOEPTSIZ4_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ4_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ4_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ4_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ4_PKTCNT_OFFSET           0xb90
-#define GC_USB_DOEPTSIZ4_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ4_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ4_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ4_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ4_RXDPID_OFFSET           0xb90
-#define GC_USB_DOEPDMA4_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA4_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA4_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA4_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA4_DMAADDR_OFFSET           0xb94
-#define GC_USB_DOEPDMAB4_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB4_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB4_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB4_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB4_DMABUFFERADDR_OFFSET    0xb9c
-#define GC_USB_DOEPCTL5_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL5_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL5_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL5_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL5_MPS_OFFSET               0xba0
-#define GC_USB_DOEPCTL5_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL5_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL5_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL5_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL5_USBACTEP_OFFSET          0xba0
-#define GC_USB_DOEPCTL5_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL5_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL5_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL5_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL5_DPID_OFFSET              0xba0
-#define GC_USB_DOEPCTL5_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL5_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL5_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL5_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL5_NAKSTS_OFFSET            0xba0
-#define GC_USB_DOEPCTL5_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL5_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL5_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL5_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL5_EPTYPE_OFFSET            0xba0
-#define GC_USB_DOEPCTL5_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL5_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL5_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL5_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL5_SNP_OFFSET               0xba0
-#define GC_USB_DOEPCTL5_STALL_LSB                0x15
-#define GC_USB_DOEPCTL5_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL5_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL5_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL5_STALL_OFFSET             0xba0
-#define GC_USB_DOEPCTL5_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL5_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL5_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL5_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL5_CNAK_OFFSET              0xba0
-#define GC_USB_DOEPCTL5_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL5_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL5_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL5_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL5_SNAK_OFFSET              0xba0
-#define GC_USB_DOEPCTL5_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL5_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL5_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL5_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL5_SETD0PID_OFFSET          0xba0
-#define GC_USB_DOEPCTL5_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL5_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL5_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL5_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL5_SETD1PID_OFFSET          0xba0
-#define GC_USB_DOEPCTL5_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL5_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL5_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL5_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL5_EPDIS_OFFSET             0xba0
-#define GC_USB_DOEPCTL5_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL5_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL5_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL5_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL5_EPENA_OFFSET             0xba0
-#define GC_USB_DOEPINT5_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT5_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT5_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT5_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT5_XFERCOMPL_OFFSET         0xba8
-#define GC_USB_DOEPINT5_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT5_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT5_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT5_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT5_EPDISBLD_OFFSET          0xba8
-#define GC_USB_DOEPINT5_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT5_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT5_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT5_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT5_AHBERR_OFFSET            0xba8
-#define GC_USB_DOEPINT5_SETUP_LSB                0x3
-#define GC_USB_DOEPINT5_SETUP_MASK               0x8
-#define GC_USB_DOEPINT5_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT5_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT5_SETUP_OFFSET             0xba8
-#define GC_USB_DOEPINT5_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT5_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT5_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT5_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT5_OUTTKNEPDIS_OFFSET       0xba8
-#define GC_USB_DOEPINT5_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT5_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT5_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT5_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT5_STSPHSERCVD_OFFSET       0xba8
-#define GC_USB_DOEPINT5_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT5_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT5_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT5_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT5_BACK2BACKSETUP_OFFSET    0xba8
-#define GC_USB_DOEPINT5_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT5_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT5_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT5_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT5_OUTPKTERR_OFFSET         0xba8
-#define GC_USB_DOEPINT5_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT5_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT5_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT5_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT5_BNAINTR_OFFSET           0xba8
-#define GC_USB_DOEPINT5_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT5_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT5_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT5_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT5_PKTDRPSTS_OFFSET         0xba8
-#define GC_USB_DOEPINT5_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT5_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT5_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT5_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT5_BBLEERR_OFFSET           0xba8
-#define GC_USB_DOEPINT5_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT5_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT5_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT5_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT5_NAKINTRPT_OFFSET         0xba8
-#define GC_USB_DOEPINT5_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT5_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT5_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT5_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT5_NYETINTRPT_OFFSET        0xba8
-#define GC_USB_DOEPINT5_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT5_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT5_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT5_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT5_STUPPKTRCVD_OFFSET       0xba8
-#define GC_USB_DOEPTSIZ5_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ5_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ5_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ5_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ5_XFERSIZE_OFFSET         0xbb0
-#define GC_USB_DOEPTSIZ5_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ5_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ5_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ5_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ5_PKTCNT_OFFSET           0xbb0
-#define GC_USB_DOEPTSIZ5_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ5_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ5_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ5_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ5_RXDPID_OFFSET           0xbb0
-#define GC_USB_DOEPDMA5_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA5_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA5_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA5_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA5_DMAADDR_OFFSET           0xbb4
-#define GC_USB_DOEPDMAB5_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB5_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB5_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB5_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB5_DMABUFFERADDR_OFFSET    0xbbc
-#define GC_USB_DOEPCTL6_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL6_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL6_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL6_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL6_MPS_OFFSET               0xbc0
-#define GC_USB_DOEPCTL6_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL6_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL6_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL6_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL6_USBACTEP_OFFSET          0xbc0
-#define GC_USB_DOEPCTL6_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL6_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL6_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL6_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL6_DPID_OFFSET              0xbc0
-#define GC_USB_DOEPCTL6_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL6_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL6_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL6_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL6_NAKSTS_OFFSET            0xbc0
-#define GC_USB_DOEPCTL6_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL6_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL6_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL6_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL6_EPTYPE_OFFSET            0xbc0
-#define GC_USB_DOEPCTL6_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL6_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL6_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL6_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL6_SNP_OFFSET               0xbc0
-#define GC_USB_DOEPCTL6_STALL_LSB                0x15
-#define GC_USB_DOEPCTL6_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL6_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL6_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL6_STALL_OFFSET             0xbc0
-#define GC_USB_DOEPCTL6_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL6_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL6_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL6_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL6_CNAK_OFFSET              0xbc0
-#define GC_USB_DOEPCTL6_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL6_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL6_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL6_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL6_SNAK_OFFSET              0xbc0
-#define GC_USB_DOEPCTL6_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL6_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL6_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL6_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL6_SETD0PID_OFFSET          0xbc0
-#define GC_USB_DOEPCTL6_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL6_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL6_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL6_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL6_SETD1PID_OFFSET          0xbc0
-#define GC_USB_DOEPCTL6_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL6_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL6_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL6_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL6_EPDIS_OFFSET             0xbc0
-#define GC_USB_DOEPCTL6_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL6_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL6_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL6_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL6_EPENA_OFFSET             0xbc0
-#define GC_USB_DOEPINT6_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT6_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT6_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT6_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT6_XFERCOMPL_OFFSET         0xbc8
-#define GC_USB_DOEPINT6_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT6_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT6_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT6_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT6_EPDISBLD_OFFSET          0xbc8
-#define GC_USB_DOEPINT6_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT6_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT6_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT6_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT6_AHBERR_OFFSET            0xbc8
-#define GC_USB_DOEPINT6_SETUP_LSB                0x3
-#define GC_USB_DOEPINT6_SETUP_MASK               0x8
-#define GC_USB_DOEPINT6_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT6_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT6_SETUP_OFFSET             0xbc8
-#define GC_USB_DOEPINT6_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT6_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT6_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT6_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT6_OUTTKNEPDIS_OFFSET       0xbc8
-#define GC_USB_DOEPINT6_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT6_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT6_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT6_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT6_STSPHSERCVD_OFFSET       0xbc8
-#define GC_USB_DOEPINT6_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT6_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT6_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT6_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT6_BACK2BACKSETUP_OFFSET    0xbc8
-#define GC_USB_DOEPINT6_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT6_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT6_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT6_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT6_OUTPKTERR_OFFSET         0xbc8
-#define GC_USB_DOEPINT6_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT6_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT6_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT6_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT6_BNAINTR_OFFSET           0xbc8
-#define GC_USB_DOEPINT6_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT6_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT6_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT6_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT6_PKTDRPSTS_OFFSET         0xbc8
-#define GC_USB_DOEPINT6_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT6_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT6_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT6_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT6_BBLEERR_OFFSET           0xbc8
-#define GC_USB_DOEPINT6_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT6_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT6_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT6_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT6_NAKINTRPT_OFFSET         0xbc8
-#define GC_USB_DOEPINT6_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT6_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT6_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT6_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT6_NYETINTRPT_OFFSET        0xbc8
-#define GC_USB_DOEPINT6_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT6_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT6_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT6_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT6_STUPPKTRCVD_OFFSET       0xbc8
-#define GC_USB_DOEPTSIZ6_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ6_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ6_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ6_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ6_XFERSIZE_OFFSET         0xbd0
-#define GC_USB_DOEPTSIZ6_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ6_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ6_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ6_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ6_PKTCNT_OFFSET           0xbd0
-#define GC_USB_DOEPTSIZ6_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ6_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ6_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ6_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ6_RXDPID_OFFSET           0xbd0
-#define GC_USB_DOEPDMA6_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA6_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA6_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA6_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA6_DMAADDR_OFFSET           0xbd4
-#define GC_USB_DOEPDMAB6_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB6_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB6_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB6_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB6_DMABUFFERADDR_OFFSET    0xbdc
-#define GC_USB_DOEPCTL7_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL7_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL7_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL7_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL7_MPS_OFFSET               0xbe0
-#define GC_USB_DOEPCTL7_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL7_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL7_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL7_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL7_USBACTEP_OFFSET          0xbe0
-#define GC_USB_DOEPCTL7_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL7_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL7_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL7_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL7_DPID_OFFSET              0xbe0
-#define GC_USB_DOEPCTL7_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL7_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL7_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL7_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL7_NAKSTS_OFFSET            0xbe0
-#define GC_USB_DOEPCTL7_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL7_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL7_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL7_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL7_EPTYPE_OFFSET            0xbe0
-#define GC_USB_DOEPCTL7_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL7_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL7_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL7_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL7_SNP_OFFSET               0xbe0
-#define GC_USB_DOEPCTL7_STALL_LSB                0x15
-#define GC_USB_DOEPCTL7_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL7_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL7_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL7_STALL_OFFSET             0xbe0
-#define GC_USB_DOEPCTL7_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL7_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL7_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL7_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL7_CNAK_OFFSET              0xbe0
-#define GC_USB_DOEPCTL7_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL7_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL7_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL7_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL7_SNAK_OFFSET              0xbe0
-#define GC_USB_DOEPCTL7_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL7_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL7_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL7_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL7_SETD0PID_OFFSET          0xbe0
-#define GC_USB_DOEPCTL7_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL7_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL7_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL7_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL7_SETD1PID_OFFSET          0xbe0
-#define GC_USB_DOEPCTL7_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL7_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL7_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL7_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL7_EPDIS_OFFSET             0xbe0
-#define GC_USB_DOEPCTL7_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL7_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL7_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL7_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL7_EPENA_OFFSET             0xbe0
-#define GC_USB_DOEPINT7_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT7_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT7_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT7_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT7_XFERCOMPL_OFFSET         0xbe8
-#define GC_USB_DOEPINT7_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT7_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT7_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT7_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT7_EPDISBLD_OFFSET          0xbe8
-#define GC_USB_DOEPINT7_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT7_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT7_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT7_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT7_AHBERR_OFFSET            0xbe8
-#define GC_USB_DOEPINT7_SETUP_LSB                0x3
-#define GC_USB_DOEPINT7_SETUP_MASK               0x8
-#define GC_USB_DOEPINT7_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT7_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT7_SETUP_OFFSET             0xbe8
-#define GC_USB_DOEPINT7_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT7_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT7_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT7_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT7_OUTTKNEPDIS_OFFSET       0xbe8
-#define GC_USB_DOEPINT7_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT7_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT7_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT7_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT7_STSPHSERCVD_OFFSET       0xbe8
-#define GC_USB_DOEPINT7_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT7_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT7_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT7_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT7_BACK2BACKSETUP_OFFSET    0xbe8
-#define GC_USB_DOEPINT7_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT7_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT7_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT7_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT7_OUTPKTERR_OFFSET         0xbe8
-#define GC_USB_DOEPINT7_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT7_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT7_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT7_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT7_BNAINTR_OFFSET           0xbe8
-#define GC_USB_DOEPINT7_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT7_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT7_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT7_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT7_PKTDRPSTS_OFFSET         0xbe8
-#define GC_USB_DOEPINT7_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT7_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT7_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT7_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT7_BBLEERR_OFFSET           0xbe8
-#define GC_USB_DOEPINT7_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT7_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT7_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT7_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT7_NAKINTRPT_OFFSET         0xbe8
-#define GC_USB_DOEPINT7_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT7_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT7_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT7_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT7_NYETINTRPT_OFFSET        0xbe8
-#define GC_USB_DOEPINT7_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT7_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT7_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT7_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT7_STUPPKTRCVD_OFFSET       0xbe8
-#define GC_USB_DOEPTSIZ7_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ7_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ7_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ7_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ7_XFERSIZE_OFFSET         0xbf0
-#define GC_USB_DOEPTSIZ7_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ7_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ7_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ7_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ7_PKTCNT_OFFSET           0xbf0
-#define GC_USB_DOEPTSIZ7_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ7_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ7_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ7_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ7_RXDPID_OFFSET           0xbf0
-#define GC_USB_DOEPDMA7_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA7_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA7_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA7_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA7_DMAADDR_OFFSET           0xbf4
-#define GC_USB_DOEPDMAB7_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB7_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB7_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB7_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB7_DMABUFFERADDR_OFFSET    0xbfc
-#define GC_USB_DOEPCTL8_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL8_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL8_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL8_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL8_MPS_OFFSET               0xc00
-#define GC_USB_DOEPCTL8_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL8_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL8_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL8_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL8_USBACTEP_OFFSET          0xc00
-#define GC_USB_DOEPCTL8_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL8_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL8_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL8_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL8_DPID_OFFSET              0xc00
-#define GC_USB_DOEPCTL8_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL8_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL8_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL8_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL8_NAKSTS_OFFSET            0xc00
-#define GC_USB_DOEPCTL8_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL8_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL8_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL8_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL8_EPTYPE_OFFSET            0xc00
-#define GC_USB_DOEPCTL8_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL8_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL8_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL8_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL8_SNP_OFFSET               0xc00
-#define GC_USB_DOEPCTL8_STALL_LSB                0x15
-#define GC_USB_DOEPCTL8_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL8_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL8_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL8_STALL_OFFSET             0xc00
-#define GC_USB_DOEPCTL8_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL8_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL8_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL8_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL8_CNAK_OFFSET              0xc00
-#define GC_USB_DOEPCTL8_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL8_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL8_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL8_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL8_SNAK_OFFSET              0xc00
-#define GC_USB_DOEPCTL8_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL8_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL8_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL8_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL8_SETD0PID_OFFSET          0xc00
-#define GC_USB_DOEPCTL8_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL8_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL8_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL8_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL8_SETD1PID_OFFSET          0xc00
-#define GC_USB_DOEPCTL8_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL8_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL8_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL8_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL8_EPDIS_OFFSET             0xc00
-#define GC_USB_DOEPCTL8_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL8_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL8_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL8_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL8_EPENA_OFFSET             0xc00
-#define GC_USB_DOEPINT8_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT8_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT8_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT8_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT8_XFERCOMPL_OFFSET         0xc08
-#define GC_USB_DOEPINT8_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT8_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT8_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT8_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT8_EPDISBLD_OFFSET          0xc08
-#define GC_USB_DOEPINT8_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT8_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT8_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT8_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT8_AHBERR_OFFSET            0xc08
-#define GC_USB_DOEPINT8_SETUP_LSB                0x3
-#define GC_USB_DOEPINT8_SETUP_MASK               0x8
-#define GC_USB_DOEPINT8_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT8_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT8_SETUP_OFFSET             0xc08
-#define GC_USB_DOEPINT8_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT8_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT8_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT8_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT8_OUTTKNEPDIS_OFFSET       0xc08
-#define GC_USB_DOEPINT8_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT8_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT8_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT8_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT8_STSPHSERCVD_OFFSET       0xc08
-#define GC_USB_DOEPINT8_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT8_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT8_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT8_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT8_BACK2BACKSETUP_OFFSET    0xc08
-#define GC_USB_DOEPINT8_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT8_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT8_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT8_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT8_OUTPKTERR_OFFSET         0xc08
-#define GC_USB_DOEPINT8_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT8_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT8_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT8_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT8_BNAINTR_OFFSET           0xc08
-#define GC_USB_DOEPINT8_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT8_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT8_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT8_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT8_PKTDRPSTS_OFFSET         0xc08
-#define GC_USB_DOEPINT8_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT8_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT8_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT8_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT8_BBLEERR_OFFSET           0xc08
-#define GC_USB_DOEPINT8_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT8_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT8_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT8_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT8_NAKINTRPT_OFFSET         0xc08
-#define GC_USB_DOEPINT8_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT8_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT8_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT8_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT8_NYETINTRPT_OFFSET        0xc08
-#define GC_USB_DOEPINT8_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT8_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT8_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT8_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT8_STUPPKTRCVD_OFFSET       0xc08
-#define GC_USB_DOEPTSIZ8_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ8_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ8_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ8_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ8_XFERSIZE_OFFSET         0xc10
-#define GC_USB_DOEPTSIZ8_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ8_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ8_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ8_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ8_PKTCNT_OFFSET           0xc10
-#define GC_USB_DOEPTSIZ8_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ8_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ8_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ8_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ8_RXDPID_OFFSET           0xc10
-#define GC_USB_DOEPDMA8_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA8_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA8_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA8_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA8_DMAADDR_OFFSET           0xc14
-#define GC_USB_DOEPDMAB8_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB8_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB8_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB8_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB8_DMABUFFERADDR_OFFSET    0xc1c
-#define GC_USB_DOEPCTL9_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL9_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL9_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL9_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL9_MPS_OFFSET               0xc20
-#define GC_USB_DOEPCTL9_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL9_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL9_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL9_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL9_USBACTEP_OFFSET          0xc20
-#define GC_USB_DOEPCTL9_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL9_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL9_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL9_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL9_DPID_OFFSET              0xc20
-#define GC_USB_DOEPCTL9_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL9_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL9_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL9_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL9_NAKSTS_OFFSET            0xc20
-#define GC_USB_DOEPCTL9_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL9_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL9_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL9_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL9_EPTYPE_OFFSET            0xc20
-#define GC_USB_DOEPCTL9_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL9_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL9_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL9_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL9_SNP_OFFSET               0xc20
-#define GC_USB_DOEPCTL9_STALL_LSB                0x15
-#define GC_USB_DOEPCTL9_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL9_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL9_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL9_STALL_OFFSET             0xc20
-#define GC_USB_DOEPCTL9_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL9_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL9_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL9_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL9_CNAK_OFFSET              0xc20
-#define GC_USB_DOEPCTL9_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL9_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL9_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL9_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL9_SNAK_OFFSET              0xc20
-#define GC_USB_DOEPCTL9_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL9_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL9_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL9_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL9_SETD0PID_OFFSET          0xc20
-#define GC_USB_DOEPCTL9_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL9_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL9_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL9_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL9_SETD1PID_OFFSET          0xc20
-#define GC_USB_DOEPCTL9_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL9_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL9_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL9_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL9_EPDIS_OFFSET             0xc20
-#define GC_USB_DOEPCTL9_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL9_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL9_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL9_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL9_EPENA_OFFSET             0xc20
-#define GC_USB_DOEPINT9_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT9_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT9_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT9_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT9_XFERCOMPL_OFFSET         0xc28
-#define GC_USB_DOEPINT9_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT9_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT9_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT9_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT9_EPDISBLD_OFFSET          0xc28
-#define GC_USB_DOEPINT9_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT9_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT9_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT9_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT9_AHBERR_OFFSET            0xc28
-#define GC_USB_DOEPINT9_SETUP_LSB                0x3
-#define GC_USB_DOEPINT9_SETUP_MASK               0x8
-#define GC_USB_DOEPINT9_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT9_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT9_SETUP_OFFSET             0xc28
-#define GC_USB_DOEPINT9_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT9_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT9_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT9_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT9_OUTTKNEPDIS_OFFSET       0xc28
-#define GC_USB_DOEPINT9_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT9_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT9_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT9_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT9_STSPHSERCVD_OFFSET       0xc28
-#define GC_USB_DOEPINT9_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT9_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT9_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT9_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT9_BACK2BACKSETUP_OFFSET    0xc28
-#define GC_USB_DOEPINT9_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT9_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT9_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT9_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT9_OUTPKTERR_OFFSET         0xc28
-#define GC_USB_DOEPINT9_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT9_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT9_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT9_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT9_BNAINTR_OFFSET           0xc28
-#define GC_USB_DOEPINT9_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT9_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT9_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT9_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT9_PKTDRPSTS_OFFSET         0xc28
-#define GC_USB_DOEPINT9_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT9_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT9_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT9_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT9_BBLEERR_OFFSET           0xc28
-#define GC_USB_DOEPINT9_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT9_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT9_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT9_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT9_NAKINTRPT_OFFSET         0xc28
-#define GC_USB_DOEPINT9_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT9_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT9_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT9_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT9_NYETINTRPT_OFFSET        0xc28
-#define GC_USB_DOEPINT9_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT9_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT9_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT9_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT9_STUPPKTRCVD_OFFSET       0xc28
-#define GC_USB_DOEPTSIZ9_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ9_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ9_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ9_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ9_XFERSIZE_OFFSET         0xc30
-#define GC_USB_DOEPTSIZ9_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ9_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ9_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ9_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ9_PKTCNT_OFFSET           0xc30
-#define GC_USB_DOEPTSIZ9_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ9_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ9_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ9_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ9_RXDPID_OFFSET           0xc30
-#define GC_USB_DOEPDMA9_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA9_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA9_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA9_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA9_DMAADDR_OFFSET           0xc34
-#define GC_USB_DOEPDMAB9_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB9_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB9_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB9_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB9_DMABUFFERADDR_OFFSET    0xc3c
-#define GC_USB_DOEPCTL10_MPS_LSB                 0x0
-#define GC_USB_DOEPCTL10_MPS_MASK                0x7ff
-#define GC_USB_DOEPCTL10_MPS_SIZE                0xb
-#define GC_USB_DOEPCTL10_MPS_DEFAULT             0x0
-#define GC_USB_DOEPCTL10_MPS_OFFSET              0xc40
-#define GC_USB_DOEPCTL10_USBACTEP_LSB            0xf
-#define GC_USB_DOEPCTL10_USBACTEP_MASK           0x8000
-#define GC_USB_DOEPCTL10_USBACTEP_SIZE           0x1
-#define GC_USB_DOEPCTL10_USBACTEP_DEFAULT        0x0
-#define GC_USB_DOEPCTL10_USBACTEP_OFFSET         0xc40
-#define GC_USB_DOEPCTL10_DPID_LSB                0x10
-#define GC_USB_DOEPCTL10_DPID_MASK               0x10000
-#define GC_USB_DOEPCTL10_DPID_SIZE               0x1
-#define GC_USB_DOEPCTL10_DPID_DEFAULT            0x0
-#define GC_USB_DOEPCTL10_DPID_OFFSET             0xc40
-#define GC_USB_DOEPCTL10_NAKSTS_LSB              0x11
-#define GC_USB_DOEPCTL10_NAKSTS_MASK             0x20000
-#define GC_USB_DOEPCTL10_NAKSTS_SIZE             0x1
-#define GC_USB_DOEPCTL10_NAKSTS_DEFAULT          0x0
-#define GC_USB_DOEPCTL10_NAKSTS_OFFSET           0xc40
-#define GC_USB_DOEPCTL10_EPTYPE_LSB              0x12
-#define GC_USB_DOEPCTL10_EPTYPE_MASK             0xc0000
-#define GC_USB_DOEPCTL10_EPTYPE_SIZE             0x2
-#define GC_USB_DOEPCTL10_EPTYPE_DEFAULT          0x0
-#define GC_USB_DOEPCTL10_EPTYPE_OFFSET           0xc40
-#define GC_USB_DOEPCTL10_SNP_LSB                 0x14
-#define GC_USB_DOEPCTL10_SNP_MASK                0x100000
-#define GC_USB_DOEPCTL10_SNP_SIZE                0x1
-#define GC_USB_DOEPCTL10_SNP_DEFAULT             0x0
-#define GC_USB_DOEPCTL10_SNP_OFFSET              0xc40
-#define GC_USB_DOEPCTL10_STALL_LSB               0x15
-#define GC_USB_DOEPCTL10_STALL_MASK              0x200000
-#define GC_USB_DOEPCTL10_STALL_SIZE              0x1
-#define GC_USB_DOEPCTL10_STALL_DEFAULT           0x0
-#define GC_USB_DOEPCTL10_STALL_OFFSET            0xc40
-#define GC_USB_DOEPCTL10_CNAK_LSB                0x1a
-#define GC_USB_DOEPCTL10_CNAK_MASK               0x4000000
-#define GC_USB_DOEPCTL10_CNAK_SIZE               0x1
-#define GC_USB_DOEPCTL10_CNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL10_CNAK_OFFSET             0xc40
-#define GC_USB_DOEPCTL10_SNAK_LSB                0x1b
-#define GC_USB_DOEPCTL10_SNAK_MASK               0x8000000
-#define GC_USB_DOEPCTL10_SNAK_SIZE               0x1
-#define GC_USB_DOEPCTL10_SNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL10_SNAK_OFFSET             0xc40
-#define GC_USB_DOEPCTL10_SETD0PID_LSB            0x1c
-#define GC_USB_DOEPCTL10_SETD0PID_MASK           0x10000000
-#define GC_USB_DOEPCTL10_SETD0PID_SIZE           0x1
-#define GC_USB_DOEPCTL10_SETD0PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL10_SETD0PID_OFFSET         0xc40
-#define GC_USB_DOEPCTL10_SETD1PID_LSB            0x1d
-#define GC_USB_DOEPCTL10_SETD1PID_MASK           0x20000000
-#define GC_USB_DOEPCTL10_SETD1PID_SIZE           0x1
-#define GC_USB_DOEPCTL10_SETD1PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL10_SETD1PID_OFFSET         0xc40
-#define GC_USB_DOEPCTL10_EPDIS_LSB               0x1e
-#define GC_USB_DOEPCTL10_EPDIS_MASK              0x40000000
-#define GC_USB_DOEPCTL10_EPDIS_SIZE              0x1
-#define GC_USB_DOEPCTL10_EPDIS_DEFAULT           0x0
-#define GC_USB_DOEPCTL10_EPDIS_OFFSET            0xc40
-#define GC_USB_DOEPCTL10_EPENA_LSB               0x1f
-#define GC_USB_DOEPCTL10_EPENA_MASK              0x80000000
-#define GC_USB_DOEPCTL10_EPENA_SIZE              0x1
-#define GC_USB_DOEPCTL10_EPENA_DEFAULT           0x0
-#define GC_USB_DOEPCTL10_EPENA_OFFSET            0xc40
-#define GC_USB_DOEPINT10_XFERCOMPL_LSB           0x0
-#define GC_USB_DOEPINT10_XFERCOMPL_MASK          0x1
-#define GC_USB_DOEPINT10_XFERCOMPL_SIZE          0x1
-#define GC_USB_DOEPINT10_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DOEPINT10_XFERCOMPL_OFFSET        0xc48
-#define GC_USB_DOEPINT10_EPDISBLD_LSB            0x1
-#define GC_USB_DOEPINT10_EPDISBLD_MASK           0x2
-#define GC_USB_DOEPINT10_EPDISBLD_SIZE           0x1
-#define GC_USB_DOEPINT10_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DOEPINT10_EPDISBLD_OFFSET         0xc48
-#define GC_USB_DOEPINT10_AHBERR_LSB              0x2
-#define GC_USB_DOEPINT10_AHBERR_MASK             0x4
-#define GC_USB_DOEPINT10_AHBERR_SIZE             0x1
-#define GC_USB_DOEPINT10_AHBERR_DEFAULT          0x0
-#define GC_USB_DOEPINT10_AHBERR_OFFSET           0xc48
-#define GC_USB_DOEPINT10_SETUP_LSB               0x3
-#define GC_USB_DOEPINT10_SETUP_MASK              0x8
-#define GC_USB_DOEPINT10_SETUP_SIZE              0x1
-#define GC_USB_DOEPINT10_SETUP_DEFAULT           0x0
-#define GC_USB_DOEPINT10_SETUP_OFFSET            0xc48
-#define GC_USB_DOEPINT10_OUTTKNEPDIS_LSB         0x4
-#define GC_USB_DOEPINT10_OUTTKNEPDIS_MASK        0x10
-#define GC_USB_DOEPINT10_OUTTKNEPDIS_SIZE        0x1
-#define GC_USB_DOEPINT10_OUTTKNEPDIS_DEFAULT     0x0
-#define GC_USB_DOEPINT10_OUTTKNEPDIS_OFFSET      0xc48
-#define GC_USB_DOEPINT10_STSPHSERCVD_LSB         0x5
-#define GC_USB_DOEPINT10_STSPHSERCVD_MASK        0x20
-#define GC_USB_DOEPINT10_STSPHSERCVD_SIZE        0x1
-#define GC_USB_DOEPINT10_STSPHSERCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT10_STSPHSERCVD_OFFSET      0xc48
-#define GC_USB_DOEPINT10_BACK2BACKSETUP_LSB      0x6
-#define GC_USB_DOEPINT10_BACK2BACKSETUP_MASK     0x40
-#define GC_USB_DOEPINT10_BACK2BACKSETUP_SIZE     0x1
-#define GC_USB_DOEPINT10_BACK2BACKSETUP_DEFAULT  0x0
-#define GC_USB_DOEPINT10_BACK2BACKSETUP_OFFSET   0xc48
-#define GC_USB_DOEPINT10_OUTPKTERR_LSB           0x8
-#define GC_USB_DOEPINT10_OUTPKTERR_MASK          0x100
-#define GC_USB_DOEPINT10_OUTPKTERR_SIZE          0x1
-#define GC_USB_DOEPINT10_OUTPKTERR_DEFAULT       0x0
-#define GC_USB_DOEPINT10_OUTPKTERR_OFFSET        0xc48
-#define GC_USB_DOEPINT10_BNAINTR_LSB             0x9
-#define GC_USB_DOEPINT10_BNAINTR_MASK            0x200
-#define GC_USB_DOEPINT10_BNAINTR_SIZE            0x1
-#define GC_USB_DOEPINT10_BNAINTR_DEFAULT         0x0
-#define GC_USB_DOEPINT10_BNAINTR_OFFSET          0xc48
-#define GC_USB_DOEPINT10_PKTDRPSTS_LSB           0xb
-#define GC_USB_DOEPINT10_PKTDRPSTS_MASK          0x800
-#define GC_USB_DOEPINT10_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DOEPINT10_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DOEPINT10_PKTDRPSTS_OFFSET        0xc48
-#define GC_USB_DOEPINT10_BBLEERR_LSB             0xc
-#define GC_USB_DOEPINT10_BBLEERR_MASK            0x1000
-#define GC_USB_DOEPINT10_BBLEERR_SIZE            0x1
-#define GC_USB_DOEPINT10_BBLEERR_DEFAULT         0x0
-#define GC_USB_DOEPINT10_BBLEERR_OFFSET          0xc48
-#define GC_USB_DOEPINT10_NAKINTRPT_LSB           0xd
-#define GC_USB_DOEPINT10_NAKINTRPT_MASK          0x2000
-#define GC_USB_DOEPINT10_NAKINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT10_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT10_NAKINTRPT_OFFSET        0xc48
-#define GC_USB_DOEPINT10_NYETINTRPT_LSB          0xe
-#define GC_USB_DOEPINT10_NYETINTRPT_MASK         0x4000
-#define GC_USB_DOEPINT10_NYETINTRPT_SIZE         0x1
-#define GC_USB_DOEPINT10_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DOEPINT10_NYETINTRPT_OFFSET       0xc48
-#define GC_USB_DOEPINT10_STUPPKTRCVD_LSB         0xf
-#define GC_USB_DOEPINT10_STUPPKTRCVD_MASK        0x8000
-#define GC_USB_DOEPINT10_STUPPKTRCVD_SIZE        0x1
-#define GC_USB_DOEPINT10_STUPPKTRCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT10_STUPPKTRCVD_OFFSET      0xc48
-#define GC_USB_DOEPTSIZ10_XFERSIZE_LSB           0x0
-#define GC_USB_DOEPTSIZ10_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DOEPTSIZ10_XFERSIZE_SIZE          0x13
-#define GC_USB_DOEPTSIZ10_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DOEPTSIZ10_XFERSIZE_OFFSET        0xc50
-#define GC_USB_DOEPTSIZ10_PKTCNT_LSB             0x13
-#define GC_USB_DOEPTSIZ10_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DOEPTSIZ10_PKTCNT_SIZE            0xa
-#define GC_USB_DOEPTSIZ10_PKTCNT_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ10_PKTCNT_OFFSET          0xc50
-#define GC_USB_DOEPTSIZ10_RXDPID_LSB             0x1d
-#define GC_USB_DOEPTSIZ10_RXDPID_MASK            0x60000000
-#define GC_USB_DOEPTSIZ10_RXDPID_SIZE            0x2
-#define GC_USB_DOEPTSIZ10_RXDPID_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ10_RXDPID_OFFSET          0xc50
-#define GC_USB_DOEPDMA10_DMAADDR_LSB             0x0
-#define GC_USB_DOEPDMA10_DMAADDR_MASK            0xffffffff
-#define GC_USB_DOEPDMA10_DMAADDR_SIZE            0x20
-#define GC_USB_DOEPDMA10_DMAADDR_DEFAULT         0x0
-#define GC_USB_DOEPDMA10_DMAADDR_OFFSET          0xc54
-#define GC_USB_DOEPDMAB10_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DOEPDMAB10_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DOEPDMAB10_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DOEPDMAB10_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DOEPDMAB10_DMABUFFERADDR_OFFSET   0xc5c
-#define GC_USB_DOEPCTL11_MPS_LSB                 0x0
-#define GC_USB_DOEPCTL11_MPS_MASK                0x7ff
-#define GC_USB_DOEPCTL11_MPS_SIZE                0xb
-#define GC_USB_DOEPCTL11_MPS_DEFAULT             0x0
-#define GC_USB_DOEPCTL11_MPS_OFFSET              0xc60
-#define GC_USB_DOEPCTL11_USBACTEP_LSB            0xf
-#define GC_USB_DOEPCTL11_USBACTEP_MASK           0x8000
-#define GC_USB_DOEPCTL11_USBACTEP_SIZE           0x1
-#define GC_USB_DOEPCTL11_USBACTEP_DEFAULT        0x0
-#define GC_USB_DOEPCTL11_USBACTEP_OFFSET         0xc60
-#define GC_USB_DOEPCTL11_DPID_LSB                0x10
-#define GC_USB_DOEPCTL11_DPID_MASK               0x10000
-#define GC_USB_DOEPCTL11_DPID_SIZE               0x1
-#define GC_USB_DOEPCTL11_DPID_DEFAULT            0x0
-#define GC_USB_DOEPCTL11_DPID_OFFSET             0xc60
-#define GC_USB_DOEPCTL11_NAKSTS_LSB              0x11
-#define GC_USB_DOEPCTL11_NAKSTS_MASK             0x20000
-#define GC_USB_DOEPCTL11_NAKSTS_SIZE             0x1
-#define GC_USB_DOEPCTL11_NAKSTS_DEFAULT          0x0
-#define GC_USB_DOEPCTL11_NAKSTS_OFFSET           0xc60
-#define GC_USB_DOEPCTL11_EPTYPE_LSB              0x12
-#define GC_USB_DOEPCTL11_EPTYPE_MASK             0xc0000
-#define GC_USB_DOEPCTL11_EPTYPE_SIZE             0x2
-#define GC_USB_DOEPCTL11_EPTYPE_DEFAULT          0x0
-#define GC_USB_DOEPCTL11_EPTYPE_OFFSET           0xc60
-#define GC_USB_DOEPCTL11_SNP_LSB                 0x14
-#define GC_USB_DOEPCTL11_SNP_MASK                0x100000
-#define GC_USB_DOEPCTL11_SNP_SIZE                0x1
-#define GC_USB_DOEPCTL11_SNP_DEFAULT             0x0
-#define GC_USB_DOEPCTL11_SNP_OFFSET              0xc60
-#define GC_USB_DOEPCTL11_STALL_LSB               0x15
-#define GC_USB_DOEPCTL11_STALL_MASK              0x200000
-#define GC_USB_DOEPCTL11_STALL_SIZE              0x1
-#define GC_USB_DOEPCTL11_STALL_DEFAULT           0x0
-#define GC_USB_DOEPCTL11_STALL_OFFSET            0xc60
-#define GC_USB_DOEPCTL11_CNAK_LSB                0x1a
-#define GC_USB_DOEPCTL11_CNAK_MASK               0x4000000
-#define GC_USB_DOEPCTL11_CNAK_SIZE               0x1
-#define GC_USB_DOEPCTL11_CNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL11_CNAK_OFFSET             0xc60
-#define GC_USB_DOEPCTL11_SNAK_LSB                0x1b
-#define GC_USB_DOEPCTL11_SNAK_MASK               0x8000000
-#define GC_USB_DOEPCTL11_SNAK_SIZE               0x1
-#define GC_USB_DOEPCTL11_SNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL11_SNAK_OFFSET             0xc60
-#define GC_USB_DOEPCTL11_SETD0PID_LSB            0x1c
-#define GC_USB_DOEPCTL11_SETD0PID_MASK           0x10000000
-#define GC_USB_DOEPCTL11_SETD0PID_SIZE           0x1
-#define GC_USB_DOEPCTL11_SETD0PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL11_SETD0PID_OFFSET         0xc60
-#define GC_USB_DOEPCTL11_SETD1PID_LSB            0x1d
-#define GC_USB_DOEPCTL11_SETD1PID_MASK           0x20000000
-#define GC_USB_DOEPCTL11_SETD1PID_SIZE           0x1
-#define GC_USB_DOEPCTL11_SETD1PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL11_SETD1PID_OFFSET         0xc60
-#define GC_USB_DOEPCTL11_EPDIS_LSB               0x1e
-#define GC_USB_DOEPCTL11_EPDIS_MASK              0x40000000
-#define GC_USB_DOEPCTL11_EPDIS_SIZE              0x1
-#define GC_USB_DOEPCTL11_EPDIS_DEFAULT           0x0
-#define GC_USB_DOEPCTL11_EPDIS_OFFSET            0xc60
-#define GC_USB_DOEPCTL11_EPENA_LSB               0x1f
-#define GC_USB_DOEPCTL11_EPENA_MASK              0x80000000
-#define GC_USB_DOEPCTL11_EPENA_SIZE              0x1
-#define GC_USB_DOEPCTL11_EPENA_DEFAULT           0x0
-#define GC_USB_DOEPCTL11_EPENA_OFFSET            0xc60
-#define GC_USB_DOEPINT11_XFERCOMPL_LSB           0x0
-#define GC_USB_DOEPINT11_XFERCOMPL_MASK          0x1
-#define GC_USB_DOEPINT11_XFERCOMPL_SIZE          0x1
-#define GC_USB_DOEPINT11_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DOEPINT11_XFERCOMPL_OFFSET        0xc68
-#define GC_USB_DOEPINT11_EPDISBLD_LSB            0x1
-#define GC_USB_DOEPINT11_EPDISBLD_MASK           0x2
-#define GC_USB_DOEPINT11_EPDISBLD_SIZE           0x1
-#define GC_USB_DOEPINT11_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DOEPINT11_EPDISBLD_OFFSET         0xc68
-#define GC_USB_DOEPINT11_AHBERR_LSB              0x2
-#define GC_USB_DOEPINT11_AHBERR_MASK             0x4
-#define GC_USB_DOEPINT11_AHBERR_SIZE             0x1
-#define GC_USB_DOEPINT11_AHBERR_DEFAULT          0x0
-#define GC_USB_DOEPINT11_AHBERR_OFFSET           0xc68
-#define GC_USB_DOEPINT11_SETUP_LSB               0x3
-#define GC_USB_DOEPINT11_SETUP_MASK              0x8
-#define GC_USB_DOEPINT11_SETUP_SIZE              0x1
-#define GC_USB_DOEPINT11_SETUP_DEFAULT           0x0
-#define GC_USB_DOEPINT11_SETUP_OFFSET            0xc68
-#define GC_USB_DOEPINT11_OUTTKNEPDIS_LSB         0x4
-#define GC_USB_DOEPINT11_OUTTKNEPDIS_MASK        0x10
-#define GC_USB_DOEPINT11_OUTTKNEPDIS_SIZE        0x1
-#define GC_USB_DOEPINT11_OUTTKNEPDIS_DEFAULT     0x0
-#define GC_USB_DOEPINT11_OUTTKNEPDIS_OFFSET      0xc68
-#define GC_USB_DOEPINT11_STSPHSERCVD_LSB         0x5
-#define GC_USB_DOEPINT11_STSPHSERCVD_MASK        0x20
-#define GC_USB_DOEPINT11_STSPHSERCVD_SIZE        0x1
-#define GC_USB_DOEPINT11_STSPHSERCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT11_STSPHSERCVD_OFFSET      0xc68
-#define GC_USB_DOEPINT11_BACK2BACKSETUP_LSB      0x6
-#define GC_USB_DOEPINT11_BACK2BACKSETUP_MASK     0x40
-#define GC_USB_DOEPINT11_BACK2BACKSETUP_SIZE     0x1
-#define GC_USB_DOEPINT11_BACK2BACKSETUP_DEFAULT  0x0
-#define GC_USB_DOEPINT11_BACK2BACKSETUP_OFFSET   0xc68
-#define GC_USB_DOEPINT11_OUTPKTERR_LSB           0x8
-#define GC_USB_DOEPINT11_OUTPKTERR_MASK          0x100
-#define GC_USB_DOEPINT11_OUTPKTERR_SIZE          0x1
-#define GC_USB_DOEPINT11_OUTPKTERR_DEFAULT       0x0
-#define GC_USB_DOEPINT11_OUTPKTERR_OFFSET        0xc68
-#define GC_USB_DOEPINT11_BNAINTR_LSB             0x9
-#define GC_USB_DOEPINT11_BNAINTR_MASK            0x200
-#define GC_USB_DOEPINT11_BNAINTR_SIZE            0x1
-#define GC_USB_DOEPINT11_BNAINTR_DEFAULT         0x0
-#define GC_USB_DOEPINT11_BNAINTR_OFFSET          0xc68
-#define GC_USB_DOEPINT11_PKTDRPSTS_LSB           0xb
-#define GC_USB_DOEPINT11_PKTDRPSTS_MASK          0x800
-#define GC_USB_DOEPINT11_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DOEPINT11_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DOEPINT11_PKTDRPSTS_OFFSET        0xc68
-#define GC_USB_DOEPINT11_BBLEERR_LSB             0xc
-#define GC_USB_DOEPINT11_BBLEERR_MASK            0x1000
-#define GC_USB_DOEPINT11_BBLEERR_SIZE            0x1
-#define GC_USB_DOEPINT11_BBLEERR_DEFAULT         0x0
-#define GC_USB_DOEPINT11_BBLEERR_OFFSET          0xc68
-#define GC_USB_DOEPINT11_NAKINTRPT_LSB           0xd
-#define GC_USB_DOEPINT11_NAKINTRPT_MASK          0x2000
-#define GC_USB_DOEPINT11_NAKINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT11_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT11_NAKINTRPT_OFFSET        0xc68
-#define GC_USB_DOEPINT11_NYETINTRPT_LSB          0xe
-#define GC_USB_DOEPINT11_NYETINTRPT_MASK         0x4000
-#define GC_USB_DOEPINT11_NYETINTRPT_SIZE         0x1
-#define GC_USB_DOEPINT11_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DOEPINT11_NYETINTRPT_OFFSET       0xc68
-#define GC_USB_DOEPINT11_STUPPKTRCVD_LSB         0xf
-#define GC_USB_DOEPINT11_STUPPKTRCVD_MASK        0x8000
-#define GC_USB_DOEPINT11_STUPPKTRCVD_SIZE        0x1
-#define GC_USB_DOEPINT11_STUPPKTRCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT11_STUPPKTRCVD_OFFSET      0xc68
-#define GC_USB_DOEPTSIZ11_XFERSIZE_LSB           0x0
-#define GC_USB_DOEPTSIZ11_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DOEPTSIZ11_XFERSIZE_SIZE          0x13
-#define GC_USB_DOEPTSIZ11_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DOEPTSIZ11_XFERSIZE_OFFSET        0xc70
-#define GC_USB_DOEPTSIZ11_PKTCNT_LSB             0x13
-#define GC_USB_DOEPTSIZ11_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DOEPTSIZ11_PKTCNT_SIZE            0xa
-#define GC_USB_DOEPTSIZ11_PKTCNT_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ11_PKTCNT_OFFSET          0xc70
-#define GC_USB_DOEPTSIZ11_RXDPID_LSB             0x1d
-#define GC_USB_DOEPTSIZ11_RXDPID_MASK            0x60000000
-#define GC_USB_DOEPTSIZ11_RXDPID_SIZE            0x2
-#define GC_USB_DOEPTSIZ11_RXDPID_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ11_RXDPID_OFFSET          0xc70
-#define GC_USB_DOEPDMA11_DMAADDR_LSB             0x0
-#define GC_USB_DOEPDMA11_DMAADDR_MASK            0xffffffff
-#define GC_USB_DOEPDMA11_DMAADDR_SIZE            0x20
-#define GC_USB_DOEPDMA11_DMAADDR_DEFAULT         0x0
-#define GC_USB_DOEPDMA11_DMAADDR_OFFSET          0xc74
-#define GC_USB_DOEPDMAB11_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DOEPDMAB11_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DOEPDMAB11_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DOEPDMAB11_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DOEPDMAB11_DMABUFFERADDR_OFFSET   0xc7c
-#define GC_USB_DOEPCTL12_MPS_LSB                 0x0
-#define GC_USB_DOEPCTL12_MPS_MASK                0x7ff
-#define GC_USB_DOEPCTL12_MPS_SIZE                0xb
-#define GC_USB_DOEPCTL12_MPS_DEFAULT             0x0
-#define GC_USB_DOEPCTL12_MPS_OFFSET              0xc80
-#define GC_USB_DOEPCTL12_USBACTEP_LSB            0xf
-#define GC_USB_DOEPCTL12_USBACTEP_MASK           0x8000
-#define GC_USB_DOEPCTL12_USBACTEP_SIZE           0x1
-#define GC_USB_DOEPCTL12_USBACTEP_DEFAULT        0x0
-#define GC_USB_DOEPCTL12_USBACTEP_OFFSET         0xc80
-#define GC_USB_DOEPCTL12_DPID_LSB                0x10
-#define GC_USB_DOEPCTL12_DPID_MASK               0x10000
-#define GC_USB_DOEPCTL12_DPID_SIZE               0x1
-#define GC_USB_DOEPCTL12_DPID_DEFAULT            0x0
-#define GC_USB_DOEPCTL12_DPID_OFFSET             0xc80
-#define GC_USB_DOEPCTL12_NAKSTS_LSB              0x11
-#define GC_USB_DOEPCTL12_NAKSTS_MASK             0x20000
-#define GC_USB_DOEPCTL12_NAKSTS_SIZE             0x1
-#define GC_USB_DOEPCTL12_NAKSTS_DEFAULT          0x0
-#define GC_USB_DOEPCTL12_NAKSTS_OFFSET           0xc80
-#define GC_USB_DOEPCTL12_EPTYPE_LSB              0x12
-#define GC_USB_DOEPCTL12_EPTYPE_MASK             0xc0000
-#define GC_USB_DOEPCTL12_EPTYPE_SIZE             0x2
-#define GC_USB_DOEPCTL12_EPTYPE_DEFAULT          0x0
-#define GC_USB_DOEPCTL12_EPTYPE_OFFSET           0xc80
-#define GC_USB_DOEPCTL12_SNP_LSB                 0x14
-#define GC_USB_DOEPCTL12_SNP_MASK                0x100000
-#define GC_USB_DOEPCTL12_SNP_SIZE                0x1
-#define GC_USB_DOEPCTL12_SNP_DEFAULT             0x0
-#define GC_USB_DOEPCTL12_SNP_OFFSET              0xc80
-#define GC_USB_DOEPCTL12_STALL_LSB               0x15
-#define GC_USB_DOEPCTL12_STALL_MASK              0x200000
-#define GC_USB_DOEPCTL12_STALL_SIZE              0x1
-#define GC_USB_DOEPCTL12_STALL_DEFAULT           0x0
-#define GC_USB_DOEPCTL12_STALL_OFFSET            0xc80
-#define GC_USB_DOEPCTL12_CNAK_LSB                0x1a
-#define GC_USB_DOEPCTL12_CNAK_MASK               0x4000000
-#define GC_USB_DOEPCTL12_CNAK_SIZE               0x1
-#define GC_USB_DOEPCTL12_CNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL12_CNAK_OFFSET             0xc80
-#define GC_USB_DOEPCTL12_SNAK_LSB                0x1b
-#define GC_USB_DOEPCTL12_SNAK_MASK               0x8000000
-#define GC_USB_DOEPCTL12_SNAK_SIZE               0x1
-#define GC_USB_DOEPCTL12_SNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL12_SNAK_OFFSET             0xc80
-#define GC_USB_DOEPCTL12_SETD0PID_LSB            0x1c
-#define GC_USB_DOEPCTL12_SETD0PID_MASK           0x10000000
-#define GC_USB_DOEPCTL12_SETD0PID_SIZE           0x1
-#define GC_USB_DOEPCTL12_SETD0PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL12_SETD0PID_OFFSET         0xc80
-#define GC_USB_DOEPCTL12_SETD1PID_LSB            0x1d
-#define GC_USB_DOEPCTL12_SETD1PID_MASK           0x20000000
-#define GC_USB_DOEPCTL12_SETD1PID_SIZE           0x1
-#define GC_USB_DOEPCTL12_SETD1PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL12_SETD1PID_OFFSET         0xc80
-#define GC_USB_DOEPCTL12_EPDIS_LSB               0x1e
-#define GC_USB_DOEPCTL12_EPDIS_MASK              0x40000000
-#define GC_USB_DOEPCTL12_EPDIS_SIZE              0x1
-#define GC_USB_DOEPCTL12_EPDIS_DEFAULT           0x0
-#define GC_USB_DOEPCTL12_EPDIS_OFFSET            0xc80
-#define GC_USB_DOEPCTL12_EPENA_LSB               0x1f
-#define GC_USB_DOEPCTL12_EPENA_MASK              0x80000000
-#define GC_USB_DOEPCTL12_EPENA_SIZE              0x1
-#define GC_USB_DOEPCTL12_EPENA_DEFAULT           0x0
-#define GC_USB_DOEPCTL12_EPENA_OFFSET            0xc80
-#define GC_USB_DOEPINT12_XFERCOMPL_LSB           0x0
-#define GC_USB_DOEPINT12_XFERCOMPL_MASK          0x1
-#define GC_USB_DOEPINT12_XFERCOMPL_SIZE          0x1
-#define GC_USB_DOEPINT12_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DOEPINT12_XFERCOMPL_OFFSET        0xc88
-#define GC_USB_DOEPINT12_EPDISBLD_LSB            0x1
-#define GC_USB_DOEPINT12_EPDISBLD_MASK           0x2
-#define GC_USB_DOEPINT12_EPDISBLD_SIZE           0x1
-#define GC_USB_DOEPINT12_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DOEPINT12_EPDISBLD_OFFSET         0xc88
-#define GC_USB_DOEPINT12_AHBERR_LSB              0x2
-#define GC_USB_DOEPINT12_AHBERR_MASK             0x4
-#define GC_USB_DOEPINT12_AHBERR_SIZE             0x1
-#define GC_USB_DOEPINT12_AHBERR_DEFAULT          0x0
-#define GC_USB_DOEPINT12_AHBERR_OFFSET           0xc88
-#define GC_USB_DOEPINT12_SETUP_LSB               0x3
-#define GC_USB_DOEPINT12_SETUP_MASK              0x8
-#define GC_USB_DOEPINT12_SETUP_SIZE              0x1
-#define GC_USB_DOEPINT12_SETUP_DEFAULT           0x0
-#define GC_USB_DOEPINT12_SETUP_OFFSET            0xc88
-#define GC_USB_DOEPINT12_OUTTKNEPDIS_LSB         0x4
-#define GC_USB_DOEPINT12_OUTTKNEPDIS_MASK        0x10
-#define GC_USB_DOEPINT12_OUTTKNEPDIS_SIZE        0x1
-#define GC_USB_DOEPINT12_OUTTKNEPDIS_DEFAULT     0x0
-#define GC_USB_DOEPINT12_OUTTKNEPDIS_OFFSET      0xc88
-#define GC_USB_DOEPINT12_STSPHSERCVD_LSB         0x5
-#define GC_USB_DOEPINT12_STSPHSERCVD_MASK        0x20
-#define GC_USB_DOEPINT12_STSPHSERCVD_SIZE        0x1
-#define GC_USB_DOEPINT12_STSPHSERCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT12_STSPHSERCVD_OFFSET      0xc88
-#define GC_USB_DOEPINT12_BACK2BACKSETUP_LSB      0x6
-#define GC_USB_DOEPINT12_BACK2BACKSETUP_MASK     0x40
-#define GC_USB_DOEPINT12_BACK2BACKSETUP_SIZE     0x1
-#define GC_USB_DOEPINT12_BACK2BACKSETUP_DEFAULT  0x0
-#define GC_USB_DOEPINT12_BACK2BACKSETUP_OFFSET   0xc88
-#define GC_USB_DOEPINT12_OUTPKTERR_LSB           0x8
-#define GC_USB_DOEPINT12_OUTPKTERR_MASK          0x100
-#define GC_USB_DOEPINT12_OUTPKTERR_SIZE          0x1
-#define GC_USB_DOEPINT12_OUTPKTERR_DEFAULT       0x0
-#define GC_USB_DOEPINT12_OUTPKTERR_OFFSET        0xc88
-#define GC_USB_DOEPINT12_BNAINTR_LSB             0x9
-#define GC_USB_DOEPINT12_BNAINTR_MASK            0x200
-#define GC_USB_DOEPINT12_BNAINTR_SIZE            0x1
-#define GC_USB_DOEPINT12_BNAINTR_DEFAULT         0x0
-#define GC_USB_DOEPINT12_BNAINTR_OFFSET          0xc88
-#define GC_USB_DOEPINT12_PKTDRPSTS_LSB           0xb
-#define GC_USB_DOEPINT12_PKTDRPSTS_MASK          0x800
-#define GC_USB_DOEPINT12_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DOEPINT12_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DOEPINT12_PKTDRPSTS_OFFSET        0xc88
-#define GC_USB_DOEPINT12_BBLEERR_LSB             0xc
-#define GC_USB_DOEPINT12_BBLEERR_MASK            0x1000
-#define GC_USB_DOEPINT12_BBLEERR_SIZE            0x1
-#define GC_USB_DOEPINT12_BBLEERR_DEFAULT         0x0
-#define GC_USB_DOEPINT12_BBLEERR_OFFSET          0xc88
-#define GC_USB_DOEPINT12_NAKINTRPT_LSB           0xd
-#define GC_USB_DOEPINT12_NAKINTRPT_MASK          0x2000
-#define GC_USB_DOEPINT12_NAKINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT12_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT12_NAKINTRPT_OFFSET        0xc88
-#define GC_USB_DOEPINT12_NYETINTRPT_LSB          0xe
-#define GC_USB_DOEPINT12_NYETINTRPT_MASK         0x4000
-#define GC_USB_DOEPINT12_NYETINTRPT_SIZE         0x1
-#define GC_USB_DOEPINT12_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DOEPINT12_NYETINTRPT_OFFSET       0xc88
-#define GC_USB_DOEPINT12_STUPPKTRCVD_LSB         0xf
-#define GC_USB_DOEPINT12_STUPPKTRCVD_MASK        0x8000
-#define GC_USB_DOEPINT12_STUPPKTRCVD_SIZE        0x1
-#define GC_USB_DOEPINT12_STUPPKTRCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT12_STUPPKTRCVD_OFFSET      0xc88
-#define GC_USB_DOEPTSIZ12_XFERSIZE_LSB           0x0
-#define GC_USB_DOEPTSIZ12_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DOEPTSIZ12_XFERSIZE_SIZE          0x13
-#define GC_USB_DOEPTSIZ12_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DOEPTSIZ12_XFERSIZE_OFFSET        0xc90
-#define GC_USB_DOEPTSIZ12_PKTCNT_LSB             0x13
-#define GC_USB_DOEPTSIZ12_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DOEPTSIZ12_PKTCNT_SIZE            0xa
-#define GC_USB_DOEPTSIZ12_PKTCNT_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ12_PKTCNT_OFFSET          0xc90
-#define GC_USB_DOEPTSIZ12_RXDPID_LSB             0x1d
-#define GC_USB_DOEPTSIZ12_RXDPID_MASK            0x60000000
-#define GC_USB_DOEPTSIZ12_RXDPID_SIZE            0x2
-#define GC_USB_DOEPTSIZ12_RXDPID_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ12_RXDPID_OFFSET          0xc90
-#define GC_USB_DOEPDMA12_DMAADDR_LSB             0x0
-#define GC_USB_DOEPDMA12_DMAADDR_MASK            0xffffffff
-#define GC_USB_DOEPDMA12_DMAADDR_SIZE            0x20
-#define GC_USB_DOEPDMA12_DMAADDR_DEFAULT         0x0
-#define GC_USB_DOEPDMA12_DMAADDR_OFFSET          0xc94
-#define GC_USB_DOEPDMAB12_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DOEPDMAB12_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DOEPDMAB12_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DOEPDMAB12_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DOEPDMAB12_DMABUFFERADDR_OFFSET   0xc9c
-#define GC_USB_DOEPCTL13_MPS_LSB                 0x0
-#define GC_USB_DOEPCTL13_MPS_MASK                0x7ff
-#define GC_USB_DOEPCTL13_MPS_SIZE                0xb
-#define GC_USB_DOEPCTL13_MPS_DEFAULT             0x0
-#define GC_USB_DOEPCTL13_MPS_OFFSET              0xca0
-#define GC_USB_DOEPCTL13_USBACTEP_LSB            0xf
-#define GC_USB_DOEPCTL13_USBACTEP_MASK           0x8000
-#define GC_USB_DOEPCTL13_USBACTEP_SIZE           0x1
-#define GC_USB_DOEPCTL13_USBACTEP_DEFAULT        0x0
-#define GC_USB_DOEPCTL13_USBACTEP_OFFSET         0xca0
-#define GC_USB_DOEPCTL13_DPID_LSB                0x10
-#define GC_USB_DOEPCTL13_DPID_MASK               0x10000
-#define GC_USB_DOEPCTL13_DPID_SIZE               0x1
-#define GC_USB_DOEPCTL13_DPID_DEFAULT            0x0
-#define GC_USB_DOEPCTL13_DPID_OFFSET             0xca0
-#define GC_USB_DOEPCTL13_NAKSTS_LSB              0x11
-#define GC_USB_DOEPCTL13_NAKSTS_MASK             0x20000
-#define GC_USB_DOEPCTL13_NAKSTS_SIZE             0x1
-#define GC_USB_DOEPCTL13_NAKSTS_DEFAULT          0x0
-#define GC_USB_DOEPCTL13_NAKSTS_OFFSET           0xca0
-#define GC_USB_DOEPCTL13_EPTYPE_LSB              0x12
-#define GC_USB_DOEPCTL13_EPTYPE_MASK             0xc0000
-#define GC_USB_DOEPCTL13_EPTYPE_SIZE             0x2
-#define GC_USB_DOEPCTL13_EPTYPE_DEFAULT          0x0
-#define GC_USB_DOEPCTL13_EPTYPE_OFFSET           0xca0
-#define GC_USB_DOEPCTL13_SNP_LSB                 0x14
-#define GC_USB_DOEPCTL13_SNP_MASK                0x100000
-#define GC_USB_DOEPCTL13_SNP_SIZE                0x1
-#define GC_USB_DOEPCTL13_SNP_DEFAULT             0x0
-#define GC_USB_DOEPCTL13_SNP_OFFSET              0xca0
-#define GC_USB_DOEPCTL13_STALL_LSB               0x15
-#define GC_USB_DOEPCTL13_STALL_MASK              0x200000
-#define GC_USB_DOEPCTL13_STALL_SIZE              0x1
-#define GC_USB_DOEPCTL13_STALL_DEFAULT           0x0
-#define GC_USB_DOEPCTL13_STALL_OFFSET            0xca0
-#define GC_USB_DOEPCTL13_CNAK_LSB                0x1a
-#define GC_USB_DOEPCTL13_CNAK_MASK               0x4000000
-#define GC_USB_DOEPCTL13_CNAK_SIZE               0x1
-#define GC_USB_DOEPCTL13_CNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL13_CNAK_OFFSET             0xca0
-#define GC_USB_DOEPCTL13_SNAK_LSB                0x1b
-#define GC_USB_DOEPCTL13_SNAK_MASK               0x8000000
-#define GC_USB_DOEPCTL13_SNAK_SIZE               0x1
-#define GC_USB_DOEPCTL13_SNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL13_SNAK_OFFSET             0xca0
-#define GC_USB_DOEPCTL13_SETD0PID_LSB            0x1c
-#define GC_USB_DOEPCTL13_SETD0PID_MASK           0x10000000
-#define GC_USB_DOEPCTL13_SETD0PID_SIZE           0x1
-#define GC_USB_DOEPCTL13_SETD0PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL13_SETD0PID_OFFSET         0xca0
-#define GC_USB_DOEPCTL13_SETD1PID_LSB            0x1d
-#define GC_USB_DOEPCTL13_SETD1PID_MASK           0x20000000
-#define GC_USB_DOEPCTL13_SETD1PID_SIZE           0x1
-#define GC_USB_DOEPCTL13_SETD1PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL13_SETD1PID_OFFSET         0xca0
-#define GC_USB_DOEPCTL13_EPDIS_LSB               0x1e
-#define GC_USB_DOEPCTL13_EPDIS_MASK              0x40000000
-#define GC_USB_DOEPCTL13_EPDIS_SIZE              0x1
-#define GC_USB_DOEPCTL13_EPDIS_DEFAULT           0x0
-#define GC_USB_DOEPCTL13_EPDIS_OFFSET            0xca0
-#define GC_USB_DOEPCTL13_EPENA_LSB               0x1f
-#define GC_USB_DOEPCTL13_EPENA_MASK              0x80000000
-#define GC_USB_DOEPCTL13_EPENA_SIZE              0x1
-#define GC_USB_DOEPCTL13_EPENA_DEFAULT           0x0
-#define GC_USB_DOEPCTL13_EPENA_OFFSET            0xca0
-#define GC_USB_DOEPINT13_XFERCOMPL_LSB           0x0
-#define GC_USB_DOEPINT13_XFERCOMPL_MASK          0x1
-#define GC_USB_DOEPINT13_XFERCOMPL_SIZE          0x1
-#define GC_USB_DOEPINT13_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DOEPINT13_XFERCOMPL_OFFSET        0xca8
-#define GC_USB_DOEPINT13_EPDISBLD_LSB            0x1
-#define GC_USB_DOEPINT13_EPDISBLD_MASK           0x2
-#define GC_USB_DOEPINT13_EPDISBLD_SIZE           0x1
-#define GC_USB_DOEPINT13_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DOEPINT13_EPDISBLD_OFFSET         0xca8
-#define GC_USB_DOEPINT13_AHBERR_LSB              0x2
-#define GC_USB_DOEPINT13_AHBERR_MASK             0x4
-#define GC_USB_DOEPINT13_AHBERR_SIZE             0x1
-#define GC_USB_DOEPINT13_AHBERR_DEFAULT          0x0
-#define GC_USB_DOEPINT13_AHBERR_OFFSET           0xca8
-#define GC_USB_DOEPINT13_SETUP_LSB               0x3
-#define GC_USB_DOEPINT13_SETUP_MASK              0x8
-#define GC_USB_DOEPINT13_SETUP_SIZE              0x1
-#define GC_USB_DOEPINT13_SETUP_DEFAULT           0x0
-#define GC_USB_DOEPINT13_SETUP_OFFSET            0xca8
-#define GC_USB_DOEPINT13_OUTTKNEPDIS_LSB         0x4
-#define GC_USB_DOEPINT13_OUTTKNEPDIS_MASK        0x10
-#define GC_USB_DOEPINT13_OUTTKNEPDIS_SIZE        0x1
-#define GC_USB_DOEPINT13_OUTTKNEPDIS_DEFAULT     0x0
-#define GC_USB_DOEPINT13_OUTTKNEPDIS_OFFSET      0xca8
-#define GC_USB_DOEPINT13_STSPHSERCVD_LSB         0x5
-#define GC_USB_DOEPINT13_STSPHSERCVD_MASK        0x20
-#define GC_USB_DOEPINT13_STSPHSERCVD_SIZE        0x1
-#define GC_USB_DOEPINT13_STSPHSERCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT13_STSPHSERCVD_OFFSET      0xca8
-#define GC_USB_DOEPINT13_BACK2BACKSETUP_LSB      0x6
-#define GC_USB_DOEPINT13_BACK2BACKSETUP_MASK     0x40
-#define GC_USB_DOEPINT13_BACK2BACKSETUP_SIZE     0x1
-#define GC_USB_DOEPINT13_BACK2BACKSETUP_DEFAULT  0x0
-#define GC_USB_DOEPINT13_BACK2BACKSETUP_OFFSET   0xca8
-#define GC_USB_DOEPINT13_OUTPKTERR_LSB           0x8
-#define GC_USB_DOEPINT13_OUTPKTERR_MASK          0x100
-#define GC_USB_DOEPINT13_OUTPKTERR_SIZE          0x1
-#define GC_USB_DOEPINT13_OUTPKTERR_DEFAULT       0x0
-#define GC_USB_DOEPINT13_OUTPKTERR_OFFSET        0xca8
-#define GC_USB_DOEPINT13_BNAINTR_LSB             0x9
-#define GC_USB_DOEPINT13_BNAINTR_MASK            0x200
-#define GC_USB_DOEPINT13_BNAINTR_SIZE            0x1
-#define GC_USB_DOEPINT13_BNAINTR_DEFAULT         0x0
-#define GC_USB_DOEPINT13_BNAINTR_OFFSET          0xca8
-#define GC_USB_DOEPINT13_PKTDRPSTS_LSB           0xb
-#define GC_USB_DOEPINT13_PKTDRPSTS_MASK          0x800
-#define GC_USB_DOEPINT13_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DOEPINT13_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DOEPINT13_PKTDRPSTS_OFFSET        0xca8
-#define GC_USB_DOEPINT13_BBLEERR_LSB             0xc
-#define GC_USB_DOEPINT13_BBLEERR_MASK            0x1000
-#define GC_USB_DOEPINT13_BBLEERR_SIZE            0x1
-#define GC_USB_DOEPINT13_BBLEERR_DEFAULT         0x0
-#define GC_USB_DOEPINT13_BBLEERR_OFFSET          0xca8
-#define GC_USB_DOEPINT13_NAKINTRPT_LSB           0xd
-#define GC_USB_DOEPINT13_NAKINTRPT_MASK          0x2000
-#define GC_USB_DOEPINT13_NAKINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT13_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT13_NAKINTRPT_OFFSET        0xca8
-#define GC_USB_DOEPINT13_NYETINTRPT_LSB          0xe
-#define GC_USB_DOEPINT13_NYETINTRPT_MASK         0x4000
-#define GC_USB_DOEPINT13_NYETINTRPT_SIZE         0x1
-#define GC_USB_DOEPINT13_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DOEPINT13_NYETINTRPT_OFFSET       0xca8
-#define GC_USB_DOEPINT13_STUPPKTRCVD_LSB         0xf
-#define GC_USB_DOEPINT13_STUPPKTRCVD_MASK        0x8000
-#define GC_USB_DOEPINT13_STUPPKTRCVD_SIZE        0x1
-#define GC_USB_DOEPINT13_STUPPKTRCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT13_STUPPKTRCVD_OFFSET      0xca8
-#define GC_USB_DOEPTSIZ13_XFERSIZE_LSB           0x0
-#define GC_USB_DOEPTSIZ13_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DOEPTSIZ13_XFERSIZE_SIZE          0x13
-#define GC_USB_DOEPTSIZ13_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DOEPTSIZ13_XFERSIZE_OFFSET        0xcb0
-#define GC_USB_DOEPTSIZ13_PKTCNT_LSB             0x13
-#define GC_USB_DOEPTSIZ13_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DOEPTSIZ13_PKTCNT_SIZE            0xa
-#define GC_USB_DOEPTSIZ13_PKTCNT_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ13_PKTCNT_OFFSET          0xcb0
-#define GC_USB_DOEPTSIZ13_RXDPID_LSB             0x1d
-#define GC_USB_DOEPTSIZ13_RXDPID_MASK            0x60000000
-#define GC_USB_DOEPTSIZ13_RXDPID_SIZE            0x2
-#define GC_USB_DOEPTSIZ13_RXDPID_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ13_RXDPID_OFFSET          0xcb0
-#define GC_USB_DOEPDMA13_DMAADDR_LSB             0x0
-#define GC_USB_DOEPDMA13_DMAADDR_MASK            0xffffffff
-#define GC_USB_DOEPDMA13_DMAADDR_SIZE            0x20
-#define GC_USB_DOEPDMA13_DMAADDR_DEFAULT         0x0
-#define GC_USB_DOEPDMA13_DMAADDR_OFFSET          0xcb4
-#define GC_USB_DOEPDMAB13_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DOEPDMAB13_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DOEPDMAB13_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DOEPDMAB13_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DOEPDMAB13_DMABUFFERADDR_OFFSET   0xcbc
-#define GC_USB_DOEPCTL14_MPS_LSB                 0x0
-#define GC_USB_DOEPCTL14_MPS_MASK                0x7ff
-#define GC_USB_DOEPCTL14_MPS_SIZE                0xb
-#define GC_USB_DOEPCTL14_MPS_DEFAULT             0x0
-#define GC_USB_DOEPCTL14_MPS_OFFSET              0xcc0
-#define GC_USB_DOEPCTL14_USBACTEP_LSB            0xf
-#define GC_USB_DOEPCTL14_USBACTEP_MASK           0x8000
-#define GC_USB_DOEPCTL14_USBACTEP_SIZE           0x1
-#define GC_USB_DOEPCTL14_USBACTEP_DEFAULT        0x0
-#define GC_USB_DOEPCTL14_USBACTEP_OFFSET         0xcc0
-#define GC_USB_DOEPCTL14_DPID_LSB                0x10
-#define GC_USB_DOEPCTL14_DPID_MASK               0x10000
-#define GC_USB_DOEPCTL14_DPID_SIZE               0x1
-#define GC_USB_DOEPCTL14_DPID_DEFAULT            0x0
-#define GC_USB_DOEPCTL14_DPID_OFFSET             0xcc0
-#define GC_USB_DOEPCTL14_NAKSTS_LSB              0x11
-#define GC_USB_DOEPCTL14_NAKSTS_MASK             0x20000
-#define GC_USB_DOEPCTL14_NAKSTS_SIZE             0x1
-#define GC_USB_DOEPCTL14_NAKSTS_DEFAULT          0x0
-#define GC_USB_DOEPCTL14_NAKSTS_OFFSET           0xcc0
-#define GC_USB_DOEPCTL14_EPTYPE_LSB              0x12
-#define GC_USB_DOEPCTL14_EPTYPE_MASK             0xc0000
-#define GC_USB_DOEPCTL14_EPTYPE_SIZE             0x2
-#define GC_USB_DOEPCTL14_EPTYPE_DEFAULT          0x0
-#define GC_USB_DOEPCTL14_EPTYPE_OFFSET           0xcc0
-#define GC_USB_DOEPCTL14_SNP_LSB                 0x14
-#define GC_USB_DOEPCTL14_SNP_MASK                0x100000
-#define GC_USB_DOEPCTL14_SNP_SIZE                0x1
-#define GC_USB_DOEPCTL14_SNP_DEFAULT             0x0
-#define GC_USB_DOEPCTL14_SNP_OFFSET              0xcc0
-#define GC_USB_DOEPCTL14_STALL_LSB               0x15
-#define GC_USB_DOEPCTL14_STALL_MASK              0x200000
-#define GC_USB_DOEPCTL14_STALL_SIZE              0x1
-#define GC_USB_DOEPCTL14_STALL_DEFAULT           0x0
-#define GC_USB_DOEPCTL14_STALL_OFFSET            0xcc0
-#define GC_USB_DOEPCTL14_CNAK_LSB                0x1a
-#define GC_USB_DOEPCTL14_CNAK_MASK               0x4000000
-#define GC_USB_DOEPCTL14_CNAK_SIZE               0x1
-#define GC_USB_DOEPCTL14_CNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL14_CNAK_OFFSET             0xcc0
-#define GC_USB_DOEPCTL14_SNAK_LSB                0x1b
-#define GC_USB_DOEPCTL14_SNAK_MASK               0x8000000
-#define GC_USB_DOEPCTL14_SNAK_SIZE               0x1
-#define GC_USB_DOEPCTL14_SNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL14_SNAK_OFFSET             0xcc0
-#define GC_USB_DOEPCTL14_SETD0PID_LSB            0x1c
-#define GC_USB_DOEPCTL14_SETD0PID_MASK           0x10000000
-#define GC_USB_DOEPCTL14_SETD0PID_SIZE           0x1
-#define GC_USB_DOEPCTL14_SETD0PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL14_SETD0PID_OFFSET         0xcc0
-#define GC_USB_DOEPCTL14_SETD1PID_LSB            0x1d
-#define GC_USB_DOEPCTL14_SETD1PID_MASK           0x20000000
-#define GC_USB_DOEPCTL14_SETD1PID_SIZE           0x1
-#define GC_USB_DOEPCTL14_SETD1PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL14_SETD1PID_OFFSET         0xcc0
-#define GC_USB_DOEPCTL14_EPDIS_LSB               0x1e
-#define GC_USB_DOEPCTL14_EPDIS_MASK              0x40000000
-#define GC_USB_DOEPCTL14_EPDIS_SIZE              0x1
-#define GC_USB_DOEPCTL14_EPDIS_DEFAULT           0x0
-#define GC_USB_DOEPCTL14_EPDIS_OFFSET            0xcc0
-#define GC_USB_DOEPCTL14_EPENA_LSB               0x1f
-#define GC_USB_DOEPCTL14_EPENA_MASK              0x80000000
-#define GC_USB_DOEPCTL14_EPENA_SIZE              0x1
-#define GC_USB_DOEPCTL14_EPENA_DEFAULT           0x0
-#define GC_USB_DOEPCTL14_EPENA_OFFSET            0xcc0
-#define GC_USB_DOEPINT14_XFERCOMPL_LSB           0x0
-#define GC_USB_DOEPINT14_XFERCOMPL_MASK          0x1
-#define GC_USB_DOEPINT14_XFERCOMPL_SIZE          0x1
-#define GC_USB_DOEPINT14_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DOEPINT14_XFERCOMPL_OFFSET        0xcc8
-#define GC_USB_DOEPINT14_EPDISBLD_LSB            0x1
-#define GC_USB_DOEPINT14_EPDISBLD_MASK           0x2
-#define GC_USB_DOEPINT14_EPDISBLD_SIZE           0x1
-#define GC_USB_DOEPINT14_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DOEPINT14_EPDISBLD_OFFSET         0xcc8
-#define GC_USB_DOEPINT14_AHBERR_LSB              0x2
-#define GC_USB_DOEPINT14_AHBERR_MASK             0x4
-#define GC_USB_DOEPINT14_AHBERR_SIZE             0x1
-#define GC_USB_DOEPINT14_AHBERR_DEFAULT          0x0
-#define GC_USB_DOEPINT14_AHBERR_OFFSET           0xcc8
-#define GC_USB_DOEPINT14_SETUP_LSB               0x3
-#define GC_USB_DOEPINT14_SETUP_MASK              0x8
-#define GC_USB_DOEPINT14_SETUP_SIZE              0x1
-#define GC_USB_DOEPINT14_SETUP_DEFAULT           0x0
-#define GC_USB_DOEPINT14_SETUP_OFFSET            0xcc8
-#define GC_USB_DOEPINT14_OUTTKNEPDIS_LSB         0x4
-#define GC_USB_DOEPINT14_OUTTKNEPDIS_MASK        0x10
-#define GC_USB_DOEPINT14_OUTTKNEPDIS_SIZE        0x1
-#define GC_USB_DOEPINT14_OUTTKNEPDIS_DEFAULT     0x0
-#define GC_USB_DOEPINT14_OUTTKNEPDIS_OFFSET      0xcc8
-#define GC_USB_DOEPINT14_STSPHSERCVD_LSB         0x5
-#define GC_USB_DOEPINT14_STSPHSERCVD_MASK        0x20
-#define GC_USB_DOEPINT14_STSPHSERCVD_SIZE        0x1
-#define GC_USB_DOEPINT14_STSPHSERCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT14_STSPHSERCVD_OFFSET      0xcc8
-#define GC_USB_DOEPINT14_BACK2BACKSETUP_LSB      0x6
-#define GC_USB_DOEPINT14_BACK2BACKSETUP_MASK     0x40
-#define GC_USB_DOEPINT14_BACK2BACKSETUP_SIZE     0x1
-#define GC_USB_DOEPINT14_BACK2BACKSETUP_DEFAULT  0x0
-#define GC_USB_DOEPINT14_BACK2BACKSETUP_OFFSET   0xcc8
-#define GC_USB_DOEPINT14_OUTPKTERR_LSB           0x8
-#define GC_USB_DOEPINT14_OUTPKTERR_MASK          0x100
-#define GC_USB_DOEPINT14_OUTPKTERR_SIZE          0x1
-#define GC_USB_DOEPINT14_OUTPKTERR_DEFAULT       0x0
-#define GC_USB_DOEPINT14_OUTPKTERR_OFFSET        0xcc8
-#define GC_USB_DOEPINT14_BNAINTR_LSB             0x9
-#define GC_USB_DOEPINT14_BNAINTR_MASK            0x200
-#define GC_USB_DOEPINT14_BNAINTR_SIZE            0x1
-#define GC_USB_DOEPINT14_BNAINTR_DEFAULT         0x0
-#define GC_USB_DOEPINT14_BNAINTR_OFFSET          0xcc8
-#define GC_USB_DOEPINT14_PKTDRPSTS_LSB           0xb
-#define GC_USB_DOEPINT14_PKTDRPSTS_MASK          0x800
-#define GC_USB_DOEPINT14_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DOEPINT14_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DOEPINT14_PKTDRPSTS_OFFSET        0xcc8
-#define GC_USB_DOEPINT14_BBLEERR_LSB             0xc
-#define GC_USB_DOEPINT14_BBLEERR_MASK            0x1000
-#define GC_USB_DOEPINT14_BBLEERR_SIZE            0x1
-#define GC_USB_DOEPINT14_BBLEERR_DEFAULT         0x0
-#define GC_USB_DOEPINT14_BBLEERR_OFFSET          0xcc8
-#define GC_USB_DOEPINT14_NAKINTRPT_LSB           0xd
-#define GC_USB_DOEPINT14_NAKINTRPT_MASK          0x2000
-#define GC_USB_DOEPINT14_NAKINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT14_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT14_NAKINTRPT_OFFSET        0xcc8
-#define GC_USB_DOEPINT14_NYETINTRPT_LSB          0xe
-#define GC_USB_DOEPINT14_NYETINTRPT_MASK         0x4000
-#define GC_USB_DOEPINT14_NYETINTRPT_SIZE         0x1
-#define GC_USB_DOEPINT14_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DOEPINT14_NYETINTRPT_OFFSET       0xcc8
-#define GC_USB_DOEPINT14_STUPPKTRCVD_LSB         0xf
-#define GC_USB_DOEPINT14_STUPPKTRCVD_MASK        0x8000
-#define GC_USB_DOEPINT14_STUPPKTRCVD_SIZE        0x1
-#define GC_USB_DOEPINT14_STUPPKTRCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT14_STUPPKTRCVD_OFFSET      0xcc8
-#define GC_USB_DOEPTSIZ14_XFERSIZE_LSB           0x0
-#define GC_USB_DOEPTSIZ14_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DOEPTSIZ14_XFERSIZE_SIZE          0x13
-#define GC_USB_DOEPTSIZ14_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DOEPTSIZ14_XFERSIZE_OFFSET        0xcd0
-#define GC_USB_DOEPTSIZ14_PKTCNT_LSB             0x13
-#define GC_USB_DOEPTSIZ14_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DOEPTSIZ14_PKTCNT_SIZE            0xa
-#define GC_USB_DOEPTSIZ14_PKTCNT_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ14_PKTCNT_OFFSET          0xcd0
-#define GC_USB_DOEPTSIZ14_RXDPID_LSB             0x1d
-#define GC_USB_DOEPTSIZ14_RXDPID_MASK            0x60000000
-#define GC_USB_DOEPTSIZ14_RXDPID_SIZE            0x2
-#define GC_USB_DOEPTSIZ14_RXDPID_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ14_RXDPID_OFFSET          0xcd0
-#define GC_USB_DOEPDMA14_DMAADDR_LSB             0x0
-#define GC_USB_DOEPDMA14_DMAADDR_MASK            0xffffffff
-#define GC_USB_DOEPDMA14_DMAADDR_SIZE            0x20
-#define GC_USB_DOEPDMA14_DMAADDR_DEFAULT         0x0
-#define GC_USB_DOEPDMA14_DMAADDR_OFFSET          0xcd4
-#define GC_USB_DOEPDMAB14_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DOEPDMAB14_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DOEPDMAB14_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DOEPDMAB14_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DOEPDMAB14_DMABUFFERADDR_OFFSET   0xcdc
-#define GC_USB_DOEPCTL15_MPS_LSB                 0x0
-#define GC_USB_DOEPCTL15_MPS_MASK                0x7ff
-#define GC_USB_DOEPCTL15_MPS_SIZE                0xb
-#define GC_USB_DOEPCTL15_MPS_DEFAULT             0x0
-#define GC_USB_DOEPCTL15_MPS_OFFSET              0xce0
-#define GC_USB_DOEPCTL15_USBACTEP_LSB            0xf
-#define GC_USB_DOEPCTL15_USBACTEP_MASK           0x8000
-#define GC_USB_DOEPCTL15_USBACTEP_SIZE           0x1
-#define GC_USB_DOEPCTL15_USBACTEP_DEFAULT        0x0
-#define GC_USB_DOEPCTL15_USBACTEP_OFFSET         0xce0
-#define GC_USB_DOEPCTL15_DPID_LSB                0x10
-#define GC_USB_DOEPCTL15_DPID_MASK               0x10000
-#define GC_USB_DOEPCTL15_DPID_SIZE               0x1
-#define GC_USB_DOEPCTL15_DPID_DEFAULT            0x0
-#define GC_USB_DOEPCTL15_DPID_OFFSET             0xce0
-#define GC_USB_DOEPCTL15_NAKSTS_LSB              0x11
-#define GC_USB_DOEPCTL15_NAKSTS_MASK             0x20000
-#define GC_USB_DOEPCTL15_NAKSTS_SIZE             0x1
-#define GC_USB_DOEPCTL15_NAKSTS_DEFAULT          0x0
-#define GC_USB_DOEPCTL15_NAKSTS_OFFSET           0xce0
-#define GC_USB_DOEPCTL15_EPTYPE_LSB              0x12
-#define GC_USB_DOEPCTL15_EPTYPE_MASK             0xc0000
-#define GC_USB_DOEPCTL15_EPTYPE_SIZE             0x2
-#define GC_USB_DOEPCTL15_EPTYPE_DEFAULT          0x0
-#define GC_USB_DOEPCTL15_EPTYPE_OFFSET           0xce0
-#define GC_USB_DOEPCTL15_SNP_LSB                 0x14
-#define GC_USB_DOEPCTL15_SNP_MASK                0x100000
-#define GC_USB_DOEPCTL15_SNP_SIZE                0x1
-#define GC_USB_DOEPCTL15_SNP_DEFAULT             0x0
-#define GC_USB_DOEPCTL15_SNP_OFFSET              0xce0
-#define GC_USB_DOEPCTL15_STALL_LSB               0x15
-#define GC_USB_DOEPCTL15_STALL_MASK              0x200000
-#define GC_USB_DOEPCTL15_STALL_SIZE              0x1
-#define GC_USB_DOEPCTL15_STALL_DEFAULT           0x0
-#define GC_USB_DOEPCTL15_STALL_OFFSET            0xce0
-#define GC_USB_DOEPCTL15_CNAK_LSB                0x1a
-#define GC_USB_DOEPCTL15_CNAK_MASK               0x4000000
-#define GC_USB_DOEPCTL15_CNAK_SIZE               0x1
-#define GC_USB_DOEPCTL15_CNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL15_CNAK_OFFSET             0xce0
-#define GC_USB_DOEPCTL15_SNAK_LSB                0x1b
-#define GC_USB_DOEPCTL15_SNAK_MASK               0x8000000
-#define GC_USB_DOEPCTL15_SNAK_SIZE               0x1
-#define GC_USB_DOEPCTL15_SNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL15_SNAK_OFFSET             0xce0
-#define GC_USB_DOEPCTL15_SETD0PID_LSB            0x1c
-#define GC_USB_DOEPCTL15_SETD0PID_MASK           0x10000000
-#define GC_USB_DOEPCTL15_SETD0PID_SIZE           0x1
-#define GC_USB_DOEPCTL15_SETD0PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL15_SETD0PID_OFFSET         0xce0
-#define GC_USB_DOEPCTL15_SETD1PID_LSB            0x1d
-#define GC_USB_DOEPCTL15_SETD1PID_MASK           0x20000000
-#define GC_USB_DOEPCTL15_SETD1PID_SIZE           0x1
-#define GC_USB_DOEPCTL15_SETD1PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL15_SETD1PID_OFFSET         0xce0
-#define GC_USB_DOEPCTL15_EPDIS_LSB               0x1e
-#define GC_USB_DOEPCTL15_EPDIS_MASK              0x40000000
-#define GC_USB_DOEPCTL15_EPDIS_SIZE              0x1
-#define GC_USB_DOEPCTL15_EPDIS_DEFAULT           0x0
-#define GC_USB_DOEPCTL15_EPDIS_OFFSET            0xce0
-#define GC_USB_DOEPCTL15_EPENA_LSB               0x1f
-#define GC_USB_DOEPCTL15_EPENA_MASK              0x80000000
-#define GC_USB_DOEPCTL15_EPENA_SIZE              0x1
-#define GC_USB_DOEPCTL15_EPENA_DEFAULT           0x0
-#define GC_USB_DOEPCTL15_EPENA_OFFSET            0xce0
-#define GC_USB_DOEPINT15_XFERCOMPL_LSB           0x0
-#define GC_USB_DOEPINT15_XFERCOMPL_MASK          0x1
-#define GC_USB_DOEPINT15_XFERCOMPL_SIZE          0x1
-#define GC_USB_DOEPINT15_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DOEPINT15_XFERCOMPL_OFFSET        0xce8
-#define GC_USB_DOEPINT15_EPDISBLD_LSB            0x1
-#define GC_USB_DOEPINT15_EPDISBLD_MASK           0x2
-#define GC_USB_DOEPINT15_EPDISBLD_SIZE           0x1
-#define GC_USB_DOEPINT15_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DOEPINT15_EPDISBLD_OFFSET         0xce8
-#define GC_USB_DOEPINT15_AHBERR_LSB              0x2
-#define GC_USB_DOEPINT15_AHBERR_MASK             0x4
-#define GC_USB_DOEPINT15_AHBERR_SIZE             0x1
-#define GC_USB_DOEPINT15_AHBERR_DEFAULT          0x0
-#define GC_USB_DOEPINT15_AHBERR_OFFSET           0xce8
-#define GC_USB_DOEPINT15_SETUP_LSB               0x3
-#define GC_USB_DOEPINT15_SETUP_MASK              0x8
-#define GC_USB_DOEPINT15_SETUP_SIZE              0x1
-#define GC_USB_DOEPINT15_SETUP_DEFAULT           0x0
-#define GC_USB_DOEPINT15_SETUP_OFFSET            0xce8
-#define GC_USB_DOEPINT15_OUTTKNEPDIS_LSB         0x4
-#define GC_USB_DOEPINT15_OUTTKNEPDIS_MASK        0x10
-#define GC_USB_DOEPINT15_OUTTKNEPDIS_SIZE        0x1
-#define GC_USB_DOEPINT15_OUTTKNEPDIS_DEFAULT     0x0
-#define GC_USB_DOEPINT15_OUTTKNEPDIS_OFFSET      0xce8
-#define GC_USB_DOEPINT15_STSPHSERCVD_LSB         0x5
-#define GC_USB_DOEPINT15_STSPHSERCVD_MASK        0x20
-#define GC_USB_DOEPINT15_STSPHSERCVD_SIZE        0x1
-#define GC_USB_DOEPINT15_STSPHSERCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT15_STSPHSERCVD_OFFSET      0xce8
-#define GC_USB_DOEPINT15_BACK2BACKSETUP_LSB      0x6
-#define GC_USB_DOEPINT15_BACK2BACKSETUP_MASK     0x40
-#define GC_USB_DOEPINT15_BACK2BACKSETUP_SIZE     0x1
-#define GC_USB_DOEPINT15_BACK2BACKSETUP_DEFAULT  0x0
-#define GC_USB_DOEPINT15_BACK2BACKSETUP_OFFSET   0xce8
-#define GC_USB_DOEPINT15_OUTPKTERR_LSB           0x8
-#define GC_USB_DOEPINT15_OUTPKTERR_MASK          0x100
-#define GC_USB_DOEPINT15_OUTPKTERR_SIZE          0x1
-#define GC_USB_DOEPINT15_OUTPKTERR_DEFAULT       0x0
-#define GC_USB_DOEPINT15_OUTPKTERR_OFFSET        0xce8
-#define GC_USB_DOEPINT15_BNAINTR_LSB             0x9
-#define GC_USB_DOEPINT15_BNAINTR_MASK            0x200
-#define GC_USB_DOEPINT15_BNAINTR_SIZE            0x1
-#define GC_USB_DOEPINT15_BNAINTR_DEFAULT         0x0
-#define GC_USB_DOEPINT15_BNAINTR_OFFSET          0xce8
-#define GC_USB_DOEPINT15_PKTDRPSTS_LSB           0xb
-#define GC_USB_DOEPINT15_PKTDRPSTS_MASK          0x800
-#define GC_USB_DOEPINT15_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DOEPINT15_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DOEPINT15_PKTDRPSTS_OFFSET        0xce8
-#define GC_USB_DOEPINT15_BBLEERR_LSB             0xc
-#define GC_USB_DOEPINT15_BBLEERR_MASK            0x1000
-#define GC_USB_DOEPINT15_BBLEERR_SIZE            0x1
-#define GC_USB_DOEPINT15_BBLEERR_DEFAULT         0x0
-#define GC_USB_DOEPINT15_BBLEERR_OFFSET          0xce8
-#define GC_USB_DOEPINT15_NAKINTRPT_LSB           0xd
-#define GC_USB_DOEPINT15_NAKINTRPT_MASK          0x2000
-#define GC_USB_DOEPINT15_NAKINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT15_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT15_NAKINTRPT_OFFSET        0xce8
-#define GC_USB_DOEPINT15_NYETINTRPT_LSB          0xe
-#define GC_USB_DOEPINT15_NYETINTRPT_MASK         0x4000
-#define GC_USB_DOEPINT15_NYETINTRPT_SIZE         0x1
-#define GC_USB_DOEPINT15_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DOEPINT15_NYETINTRPT_OFFSET       0xce8
-#define GC_USB_DOEPINT15_STUPPKTRCVD_LSB         0xf
-#define GC_USB_DOEPINT15_STUPPKTRCVD_MASK        0x8000
-#define GC_USB_DOEPINT15_STUPPKTRCVD_SIZE        0x1
-#define GC_USB_DOEPINT15_STUPPKTRCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT15_STUPPKTRCVD_OFFSET      0xce8
-#define GC_USB_DOEPTSIZ15_XFERSIZE_LSB           0x0
-#define GC_USB_DOEPTSIZ15_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DOEPTSIZ15_XFERSIZE_SIZE          0x13
-#define GC_USB_DOEPTSIZ15_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DOEPTSIZ15_XFERSIZE_OFFSET        0xcf0
-#define GC_USB_DOEPTSIZ15_PKTCNT_LSB             0x13
-#define GC_USB_DOEPTSIZ15_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DOEPTSIZ15_PKTCNT_SIZE            0xa
-#define GC_USB_DOEPTSIZ15_PKTCNT_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ15_PKTCNT_OFFSET          0xcf0
-#define GC_USB_DOEPTSIZ15_RXDPID_LSB             0x1d
-#define GC_USB_DOEPTSIZ15_RXDPID_MASK            0x60000000
-#define GC_USB_DOEPTSIZ15_RXDPID_SIZE            0x2
-#define GC_USB_DOEPTSIZ15_RXDPID_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ15_RXDPID_OFFSET          0xcf0
-#define GC_USB_DOEPDMA15_DMAADDR_LSB             0x0
-#define GC_USB_DOEPDMA15_DMAADDR_MASK            0xffffffff
-#define GC_USB_DOEPDMA15_DMAADDR_SIZE            0x20
-#define GC_USB_DOEPDMA15_DMAADDR_DEFAULT         0x0
-#define GC_USB_DOEPDMA15_DMAADDR_OFFSET          0xcf4
-#define GC_USB_DOEPDMAB15_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DOEPDMAB15_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DOEPDMAB15_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DOEPDMAB15_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DOEPDMAB15_DMABUFFERADDR_OFFSET   0xcfc
-#define GC_USB_PCGCCTL_STOPPCLK_LSB              0x0
-#define GC_USB_PCGCCTL_STOPPCLK_MASK             0x1
-#define GC_USB_PCGCCTL_STOPPCLK_SIZE             0x1
-#define GC_USB_PCGCCTL_STOPPCLK_DEFAULT          0x0
-#define GC_USB_PCGCCTL_STOPPCLK_OFFSET           0xe00
-#define GC_USB_PCGCCTL_GATEHCLK_LSB              0x1
-#define GC_USB_PCGCCTL_GATEHCLK_MASK             0x2
-#define GC_USB_PCGCCTL_GATEHCLK_SIZE             0x1
-#define GC_USB_PCGCCTL_GATEHCLK_DEFAULT          0x0
-#define GC_USB_PCGCCTL_GATEHCLK_OFFSET           0xe00
-#define GC_USB_PCGCCTL_PWRCLMP_LSB               0x2
-#define GC_USB_PCGCCTL_PWRCLMP_MASK              0x4
-#define GC_USB_PCGCCTL_PWRCLMP_SIZE              0x1
-#define GC_USB_PCGCCTL_PWRCLMP_DEFAULT           0x0
-#define GC_USB_PCGCCTL_PWRCLMP_OFFSET            0xe00
-#define GC_USB_PCGCCTL_RSTPDWNMODULE_LSB         0x3
-#define GC_USB_PCGCCTL_RSTPDWNMODULE_MASK        0x8
-#define GC_USB_PCGCCTL_RSTPDWNMODULE_SIZE        0x1
-#define GC_USB_PCGCCTL_RSTPDWNMODULE_DEFAULT     0x0
-#define GC_USB_PCGCCTL_RSTPDWNMODULE_OFFSET      0xe00
-#define GC_USB_PCGCCTL_PHYSLEEP_LSB              0x6
-#define GC_USB_PCGCCTL_PHYSLEEP_MASK             0x40
-#define GC_USB_PCGCCTL_PHYSLEEP_SIZE             0x1
-#define GC_USB_PCGCCTL_PHYSLEEP_DEFAULT          0x0
-#define GC_USB_PCGCCTL_PHYSLEEP_OFFSET           0xe00
-#define GC_USB_PCGCCTL_L1SUSPENDED_LSB           0x7
-#define GC_USB_PCGCCTL_L1SUSPENDED_MASK          0x80
-#define GC_USB_PCGCCTL_L1SUSPENDED_SIZE          0x1
-#define GC_USB_PCGCCTL_L1SUSPENDED_DEFAULT       0x0
-#define GC_USB_PCGCCTL_L1SUSPENDED_OFFSET        0xe00
-#define GC_USB_DFIFO_SIZE                        0x1000
-
+#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_OFFSET 0xaf8
+#define GC_USB_DIEPDMAB15_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DIEPDMAB15_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMAB15_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DIEPDMAB15_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMAB15_DMABUFFERADDR_OFFSET 0xafc
+#define GC_USB_DOEPCTL0_MPS_LSB 0x0
+#define GC_USB_DOEPCTL0_MPS_MASK 0x3
+#define GC_USB_DOEPCTL0_MPS_SIZE 0x2
+#define GC_USB_DOEPCTL0_MPS_DEFAULT 0x0
+#define GC_USB_DOEPCTL0_MPS_OFFSET 0xb00
+#define GC_USB_DOEPCTL0_USBACTEP_LSB 0xf
+#define GC_USB_DOEPCTL0_USBACTEP_MASK 0x8000
+#define GC_USB_DOEPCTL0_USBACTEP_SIZE 0x1
+#define GC_USB_DOEPCTL0_USBACTEP_DEFAULT 0x0
+#define GC_USB_DOEPCTL0_USBACTEP_OFFSET 0xb00
+#define GC_USB_DOEPCTL0_NAKSTS_LSB 0x11
+#define GC_USB_DOEPCTL0_NAKSTS_MASK 0x20000
+#define GC_USB_DOEPCTL0_NAKSTS_SIZE 0x1
+#define GC_USB_DOEPCTL0_NAKSTS_DEFAULT 0x0
+#define GC_USB_DOEPCTL0_NAKSTS_OFFSET 0xb00
+#define GC_USB_DOEPCTL0_EPTYPE_LSB 0x12
+#define GC_USB_DOEPCTL0_EPTYPE_MASK 0xc0000
+#define GC_USB_DOEPCTL0_EPTYPE_SIZE 0x2
+#define GC_USB_DOEPCTL0_EPTYPE_DEFAULT 0x0
+#define GC_USB_DOEPCTL0_EPTYPE_OFFSET 0xb00
+#define GC_USB_DOEPCTL0_SNP_LSB 0x14
+#define GC_USB_DOEPCTL0_SNP_MASK 0x100000
+#define GC_USB_DOEPCTL0_SNP_SIZE 0x1
+#define GC_USB_DOEPCTL0_SNP_DEFAULT 0x0
+#define GC_USB_DOEPCTL0_SNP_OFFSET 0xb00
+#define GC_USB_DOEPCTL0_STALL_LSB 0x15
+#define GC_USB_DOEPCTL0_STALL_MASK 0x200000
+#define GC_USB_DOEPCTL0_STALL_SIZE 0x1
+#define GC_USB_DOEPCTL0_STALL_DEFAULT 0x0
+#define GC_USB_DOEPCTL0_STALL_OFFSET 0xb00
+#define GC_USB_DOEPCTL0_CNAK_LSB 0x1a
+#define GC_USB_DOEPCTL0_CNAK_MASK 0x4000000
+#define GC_USB_DOEPCTL0_CNAK_SIZE 0x1
+#define GC_USB_DOEPCTL0_CNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL0_CNAK_OFFSET 0xb00
+#define GC_USB_DOEPCTL0_SNAK_LSB 0x1b
+#define GC_USB_DOEPCTL0_SNAK_MASK 0x8000000
+#define GC_USB_DOEPCTL0_SNAK_SIZE 0x1
+#define GC_USB_DOEPCTL0_SNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL0_SNAK_OFFSET 0xb00
+#define GC_USB_DOEPCTL0_EPDIS_LSB 0x1e
+#define GC_USB_DOEPCTL0_EPDIS_MASK 0x40000000
+#define GC_USB_DOEPCTL0_EPDIS_SIZE 0x1
+#define GC_USB_DOEPCTL0_EPDIS_DEFAULT 0x0
+#define GC_USB_DOEPCTL0_EPDIS_OFFSET 0xb00
+#define GC_USB_DOEPCTL0_EPENA_LSB 0x1f
+#define GC_USB_DOEPCTL0_EPENA_MASK 0x80000000
+#define GC_USB_DOEPCTL0_EPENA_SIZE 0x1
+#define GC_USB_DOEPCTL0_EPENA_DEFAULT 0x0
+#define GC_USB_DOEPCTL0_EPENA_OFFSET 0xb00
+#define GC_USB_DOEPINT0_XFERCOMPL_LSB 0x0
+#define GC_USB_DOEPINT0_XFERCOMPL_MASK 0x1
+#define GC_USB_DOEPINT0_XFERCOMPL_SIZE 0x1
+#define GC_USB_DOEPINT0_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DOEPINT0_XFERCOMPL_OFFSET 0xb08
+#define GC_USB_DOEPINT0_EPDISBLD_LSB 0x1
+#define GC_USB_DOEPINT0_EPDISBLD_MASK 0x2
+#define GC_USB_DOEPINT0_EPDISBLD_SIZE 0x1
+#define GC_USB_DOEPINT0_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DOEPINT0_EPDISBLD_OFFSET 0xb08
+#define GC_USB_DOEPINT0_AHBERR_LSB 0x2
+#define GC_USB_DOEPINT0_AHBERR_MASK 0x4
+#define GC_USB_DOEPINT0_AHBERR_SIZE 0x1
+#define GC_USB_DOEPINT0_AHBERR_DEFAULT 0x0
+#define GC_USB_DOEPINT0_AHBERR_OFFSET 0xb08
+#define GC_USB_DOEPINT0_SETUP_LSB 0x3
+#define GC_USB_DOEPINT0_SETUP_MASK 0x8
+#define GC_USB_DOEPINT0_SETUP_SIZE 0x1
+#define GC_USB_DOEPINT0_SETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT0_SETUP_OFFSET 0xb08
+#define GC_USB_DOEPINT0_OUTTKNEPDIS_LSB 0x4
+#define GC_USB_DOEPINT0_OUTTKNEPDIS_MASK 0x10
+#define GC_USB_DOEPINT0_OUTTKNEPDIS_SIZE 0x1
+#define GC_USB_DOEPINT0_OUTTKNEPDIS_DEFAULT 0x0
+#define GC_USB_DOEPINT0_OUTTKNEPDIS_OFFSET 0xb08
+#define GC_USB_DOEPINT0_STSPHSERCVD_LSB 0x5
+#define GC_USB_DOEPINT0_STSPHSERCVD_MASK 0x20
+#define GC_USB_DOEPINT0_STSPHSERCVD_SIZE 0x1
+#define GC_USB_DOEPINT0_STSPHSERCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT0_STSPHSERCVD_OFFSET 0xb08
+#define GC_USB_DOEPINT0_BACK2BACKSETUP_LSB 0x6
+#define GC_USB_DOEPINT0_BACK2BACKSETUP_MASK 0x40
+#define GC_USB_DOEPINT0_BACK2BACKSETUP_SIZE 0x1
+#define GC_USB_DOEPINT0_BACK2BACKSETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT0_BACK2BACKSETUP_OFFSET 0xb08
+#define GC_USB_DOEPINT0_OUTPKTERR_LSB 0x8
+#define GC_USB_DOEPINT0_OUTPKTERR_MASK 0x100
+#define GC_USB_DOEPINT0_OUTPKTERR_SIZE 0x1
+#define GC_USB_DOEPINT0_OUTPKTERR_DEFAULT 0x0
+#define GC_USB_DOEPINT0_OUTPKTERR_OFFSET 0xb08
+#define GC_USB_DOEPINT0_BNAINTR_LSB 0x9
+#define GC_USB_DOEPINT0_BNAINTR_MASK 0x200
+#define GC_USB_DOEPINT0_BNAINTR_SIZE 0x1
+#define GC_USB_DOEPINT0_BNAINTR_DEFAULT 0x0
+#define GC_USB_DOEPINT0_BNAINTR_OFFSET 0xb08
+#define GC_USB_DOEPINT0_PKTDRPSTS_LSB 0xb
+#define GC_USB_DOEPINT0_PKTDRPSTS_MASK 0x800
+#define GC_USB_DOEPINT0_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DOEPINT0_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DOEPINT0_PKTDRPSTS_OFFSET 0xb08
+#define GC_USB_DOEPINT0_BBLEERR_LSB 0xc
+#define GC_USB_DOEPINT0_BBLEERR_MASK 0x1000
+#define GC_USB_DOEPINT0_BBLEERR_SIZE 0x1
+#define GC_USB_DOEPINT0_BBLEERR_DEFAULT 0x0
+#define GC_USB_DOEPINT0_BBLEERR_OFFSET 0xb08
+#define GC_USB_DOEPINT0_NAKINTRPT_LSB 0xd
+#define GC_USB_DOEPINT0_NAKINTRPT_MASK 0x2000
+#define GC_USB_DOEPINT0_NAKINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT0_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT0_NAKINTRPT_OFFSET 0xb08
+#define GC_USB_DOEPINT0_NYETINTRPT_LSB 0xe
+#define GC_USB_DOEPINT0_NYETINTRPT_MASK 0x4000
+#define GC_USB_DOEPINT0_NYETINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT0_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT0_NYETINTRPT_OFFSET 0xb08
+#define GC_USB_DOEPINT0_STUPPKTRCVD_LSB 0xf
+#define GC_USB_DOEPINT0_STUPPKTRCVD_MASK 0x8000
+#define GC_USB_DOEPINT0_STUPPKTRCVD_SIZE 0x1
+#define GC_USB_DOEPINT0_STUPPKTRCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT0_STUPPKTRCVD_OFFSET 0xb08
+#define GC_USB_DOEPTSIZ0_XFERSIZE_LSB 0x0
+#define GC_USB_DOEPTSIZ0_XFERSIZE_MASK 0x7f
+#define GC_USB_DOEPTSIZ0_XFERSIZE_SIZE 0x7
+#define GC_USB_DOEPTSIZ0_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ0_XFERSIZE_OFFSET 0xb10
+#define GC_USB_DOEPTSIZ0_PKTCNT_LSB 0x13
+#define GC_USB_DOEPTSIZ0_PKTCNT_MASK 0x80000
+#define GC_USB_DOEPTSIZ0_PKTCNT_SIZE 0x1
+#define GC_USB_DOEPTSIZ0_PKTCNT_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ0_PKTCNT_OFFSET 0xb10
+#define GC_USB_DOEPTSIZ0_SUPCNT_LSB 0x1d
+#define GC_USB_DOEPTSIZ0_SUPCNT_MASK 0x60000000
+#define GC_USB_DOEPTSIZ0_SUPCNT_SIZE 0x2
+#define GC_USB_DOEPTSIZ0_SUPCNT_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ0_SUPCNT_OFFSET 0xb10
+#define GC_USB_DOEPDMA0_DMAADDR_LSB 0x0
+#define GC_USB_DOEPDMA0_DMAADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMA0_DMAADDR_SIZE 0x20
+#define GC_USB_DOEPDMA0_DMAADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMA0_DMAADDR_OFFSET 0xb14
+#define GC_USB_DOEPDMAB0_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DOEPDMAB0_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMAB0_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DOEPDMAB0_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMAB0_DMABUFFERADDR_OFFSET 0xb1c
+#define GC_USB_DOEPCTL1_MPS_LSB 0x0
+#define GC_USB_DOEPCTL1_MPS_MASK 0x7ff
+#define GC_USB_DOEPCTL1_MPS_SIZE 0xb
+#define GC_USB_DOEPCTL1_MPS_DEFAULT 0x0
+#define GC_USB_DOEPCTL1_MPS_OFFSET 0xb20
+#define GC_USB_DOEPCTL1_USBACTEP_LSB 0xf
+#define GC_USB_DOEPCTL1_USBACTEP_MASK 0x8000
+#define GC_USB_DOEPCTL1_USBACTEP_SIZE 0x1
+#define GC_USB_DOEPCTL1_USBACTEP_DEFAULT 0x0
+#define GC_USB_DOEPCTL1_USBACTEP_OFFSET 0xb20
+#define GC_USB_DOEPCTL1_DPID_LSB 0x10
+#define GC_USB_DOEPCTL1_DPID_MASK 0x10000
+#define GC_USB_DOEPCTL1_DPID_SIZE 0x1
+#define GC_USB_DOEPCTL1_DPID_DEFAULT 0x0
+#define GC_USB_DOEPCTL1_DPID_OFFSET 0xb20
+#define GC_USB_DOEPCTL1_NAKSTS_LSB 0x11
+#define GC_USB_DOEPCTL1_NAKSTS_MASK 0x20000
+#define GC_USB_DOEPCTL1_NAKSTS_SIZE 0x1
+#define GC_USB_DOEPCTL1_NAKSTS_DEFAULT 0x0
+#define GC_USB_DOEPCTL1_NAKSTS_OFFSET 0xb20
+#define GC_USB_DOEPCTL1_EPTYPE_LSB 0x12
+#define GC_USB_DOEPCTL1_EPTYPE_MASK 0xc0000
+#define GC_USB_DOEPCTL1_EPTYPE_SIZE 0x2
+#define GC_USB_DOEPCTL1_EPTYPE_DEFAULT 0x0
+#define GC_USB_DOEPCTL1_EPTYPE_OFFSET 0xb20
+#define GC_USB_DOEPCTL1_SNP_LSB 0x14
+#define GC_USB_DOEPCTL1_SNP_MASK 0x100000
+#define GC_USB_DOEPCTL1_SNP_SIZE 0x1
+#define GC_USB_DOEPCTL1_SNP_DEFAULT 0x0
+#define GC_USB_DOEPCTL1_SNP_OFFSET 0xb20
+#define GC_USB_DOEPCTL1_STALL_LSB 0x15
+#define GC_USB_DOEPCTL1_STALL_MASK 0x200000
+#define GC_USB_DOEPCTL1_STALL_SIZE 0x1
+#define GC_USB_DOEPCTL1_STALL_DEFAULT 0x0
+#define GC_USB_DOEPCTL1_STALL_OFFSET 0xb20
+#define GC_USB_DOEPCTL1_CNAK_LSB 0x1a
+#define GC_USB_DOEPCTL1_CNAK_MASK 0x4000000
+#define GC_USB_DOEPCTL1_CNAK_SIZE 0x1
+#define GC_USB_DOEPCTL1_CNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL1_CNAK_OFFSET 0xb20
+#define GC_USB_DOEPCTL1_SNAK_LSB 0x1b
+#define GC_USB_DOEPCTL1_SNAK_MASK 0x8000000
+#define GC_USB_DOEPCTL1_SNAK_SIZE 0x1
+#define GC_USB_DOEPCTL1_SNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL1_SNAK_OFFSET 0xb20
+#define GC_USB_DOEPCTL1_SETD0PID_LSB 0x1c
+#define GC_USB_DOEPCTL1_SETD0PID_MASK 0x10000000
+#define GC_USB_DOEPCTL1_SETD0PID_SIZE 0x1
+#define GC_USB_DOEPCTL1_SETD0PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL1_SETD0PID_OFFSET 0xb20
+#define GC_USB_DOEPCTL1_SETD1PID_LSB 0x1d
+#define GC_USB_DOEPCTL1_SETD1PID_MASK 0x20000000
+#define GC_USB_DOEPCTL1_SETD1PID_SIZE 0x1
+#define GC_USB_DOEPCTL1_SETD1PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL1_SETD1PID_OFFSET 0xb20
+#define GC_USB_DOEPCTL1_EPDIS_LSB 0x1e
+#define GC_USB_DOEPCTL1_EPDIS_MASK 0x40000000
+#define GC_USB_DOEPCTL1_EPDIS_SIZE 0x1
+#define GC_USB_DOEPCTL1_EPDIS_DEFAULT 0x0
+#define GC_USB_DOEPCTL1_EPDIS_OFFSET 0xb20
+#define GC_USB_DOEPCTL1_EPENA_LSB 0x1f
+#define GC_USB_DOEPCTL1_EPENA_MASK 0x80000000
+#define GC_USB_DOEPCTL1_EPENA_SIZE 0x1
+#define GC_USB_DOEPCTL1_EPENA_DEFAULT 0x0
+#define GC_USB_DOEPCTL1_EPENA_OFFSET 0xb20
+#define GC_USB_DOEPINT1_XFERCOMPL_LSB 0x0
+#define GC_USB_DOEPINT1_XFERCOMPL_MASK 0x1
+#define GC_USB_DOEPINT1_XFERCOMPL_SIZE 0x1
+#define GC_USB_DOEPINT1_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DOEPINT1_XFERCOMPL_OFFSET 0xb28
+#define GC_USB_DOEPINT1_EPDISBLD_LSB 0x1
+#define GC_USB_DOEPINT1_EPDISBLD_MASK 0x2
+#define GC_USB_DOEPINT1_EPDISBLD_SIZE 0x1
+#define GC_USB_DOEPINT1_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DOEPINT1_EPDISBLD_OFFSET 0xb28
+#define GC_USB_DOEPINT1_AHBERR_LSB 0x2
+#define GC_USB_DOEPINT1_AHBERR_MASK 0x4
+#define GC_USB_DOEPINT1_AHBERR_SIZE 0x1
+#define GC_USB_DOEPINT1_AHBERR_DEFAULT 0x0
+#define GC_USB_DOEPINT1_AHBERR_OFFSET 0xb28
+#define GC_USB_DOEPINT1_SETUP_LSB 0x3
+#define GC_USB_DOEPINT1_SETUP_MASK 0x8
+#define GC_USB_DOEPINT1_SETUP_SIZE 0x1
+#define GC_USB_DOEPINT1_SETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT1_SETUP_OFFSET 0xb28
+#define GC_USB_DOEPINT1_OUTTKNEPDIS_LSB 0x4
+#define GC_USB_DOEPINT1_OUTTKNEPDIS_MASK 0x10
+#define GC_USB_DOEPINT1_OUTTKNEPDIS_SIZE 0x1
+#define GC_USB_DOEPINT1_OUTTKNEPDIS_DEFAULT 0x0
+#define GC_USB_DOEPINT1_OUTTKNEPDIS_OFFSET 0xb28
+#define GC_USB_DOEPINT1_STSPHSERCVD_LSB 0x5
+#define GC_USB_DOEPINT1_STSPHSERCVD_MASK 0x20
+#define GC_USB_DOEPINT1_STSPHSERCVD_SIZE 0x1
+#define GC_USB_DOEPINT1_STSPHSERCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT1_STSPHSERCVD_OFFSET 0xb28
+#define GC_USB_DOEPINT1_BACK2BACKSETUP_LSB 0x6
+#define GC_USB_DOEPINT1_BACK2BACKSETUP_MASK 0x40
+#define GC_USB_DOEPINT1_BACK2BACKSETUP_SIZE 0x1
+#define GC_USB_DOEPINT1_BACK2BACKSETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT1_BACK2BACKSETUP_OFFSET 0xb28
+#define GC_USB_DOEPINT1_OUTPKTERR_LSB 0x8
+#define GC_USB_DOEPINT1_OUTPKTERR_MASK 0x100
+#define GC_USB_DOEPINT1_OUTPKTERR_SIZE 0x1
+#define GC_USB_DOEPINT1_OUTPKTERR_DEFAULT 0x0
+#define GC_USB_DOEPINT1_OUTPKTERR_OFFSET 0xb28
+#define GC_USB_DOEPINT1_BNAINTR_LSB 0x9
+#define GC_USB_DOEPINT1_BNAINTR_MASK 0x200
+#define GC_USB_DOEPINT1_BNAINTR_SIZE 0x1
+#define GC_USB_DOEPINT1_BNAINTR_DEFAULT 0x0
+#define GC_USB_DOEPINT1_BNAINTR_OFFSET 0xb28
+#define GC_USB_DOEPINT1_PKTDRPSTS_LSB 0xb
+#define GC_USB_DOEPINT1_PKTDRPSTS_MASK 0x800
+#define GC_USB_DOEPINT1_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DOEPINT1_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DOEPINT1_PKTDRPSTS_OFFSET 0xb28
+#define GC_USB_DOEPINT1_BBLEERR_LSB 0xc
+#define GC_USB_DOEPINT1_BBLEERR_MASK 0x1000
+#define GC_USB_DOEPINT1_BBLEERR_SIZE 0x1
+#define GC_USB_DOEPINT1_BBLEERR_DEFAULT 0x0
+#define GC_USB_DOEPINT1_BBLEERR_OFFSET 0xb28
+#define GC_USB_DOEPINT1_NAKINTRPT_LSB 0xd
+#define GC_USB_DOEPINT1_NAKINTRPT_MASK 0x2000
+#define GC_USB_DOEPINT1_NAKINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT1_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT1_NAKINTRPT_OFFSET 0xb28
+#define GC_USB_DOEPINT1_NYETINTRPT_LSB 0xe
+#define GC_USB_DOEPINT1_NYETINTRPT_MASK 0x4000
+#define GC_USB_DOEPINT1_NYETINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT1_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT1_NYETINTRPT_OFFSET 0xb28
+#define GC_USB_DOEPINT1_STUPPKTRCVD_LSB 0xf
+#define GC_USB_DOEPINT1_STUPPKTRCVD_MASK 0x8000
+#define GC_USB_DOEPINT1_STUPPKTRCVD_SIZE 0x1
+#define GC_USB_DOEPINT1_STUPPKTRCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT1_STUPPKTRCVD_OFFSET 0xb28
+#define GC_USB_DOEPTSIZ1_XFERSIZE_LSB 0x0
+#define GC_USB_DOEPTSIZ1_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DOEPTSIZ1_XFERSIZE_SIZE 0x13
+#define GC_USB_DOEPTSIZ1_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ1_XFERSIZE_OFFSET 0xb30
+#define GC_USB_DOEPTSIZ1_PKTCNT_LSB 0x13
+#define GC_USB_DOEPTSIZ1_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DOEPTSIZ1_PKTCNT_SIZE 0xa
+#define GC_USB_DOEPTSIZ1_PKTCNT_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ1_PKTCNT_OFFSET 0xb30
+#define GC_USB_DOEPTSIZ1_RXDPID_LSB 0x1d
+#define GC_USB_DOEPTSIZ1_RXDPID_MASK 0x60000000
+#define GC_USB_DOEPTSIZ1_RXDPID_SIZE 0x2
+#define GC_USB_DOEPTSIZ1_RXDPID_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ1_RXDPID_OFFSET 0xb30
+#define GC_USB_DOEPDMA1_DMAADDR_LSB 0x0
+#define GC_USB_DOEPDMA1_DMAADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMA1_DMAADDR_SIZE 0x20
+#define GC_USB_DOEPDMA1_DMAADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMA1_DMAADDR_OFFSET 0xb34
+#define GC_USB_DOEPDMAB1_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DOEPDMAB1_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMAB1_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DOEPDMAB1_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMAB1_DMABUFFERADDR_OFFSET 0xb3c
+#define GC_USB_DOEPCTL2_MPS_LSB 0x0
+#define GC_USB_DOEPCTL2_MPS_MASK 0x7ff
+#define GC_USB_DOEPCTL2_MPS_SIZE 0xb
+#define GC_USB_DOEPCTL2_MPS_DEFAULT 0x0
+#define GC_USB_DOEPCTL2_MPS_OFFSET 0xb40
+#define GC_USB_DOEPCTL2_USBACTEP_LSB 0xf
+#define GC_USB_DOEPCTL2_USBACTEP_MASK 0x8000
+#define GC_USB_DOEPCTL2_USBACTEP_SIZE 0x1
+#define GC_USB_DOEPCTL2_USBACTEP_DEFAULT 0x0
+#define GC_USB_DOEPCTL2_USBACTEP_OFFSET 0xb40
+#define GC_USB_DOEPCTL2_DPID_LSB 0x10
+#define GC_USB_DOEPCTL2_DPID_MASK 0x10000
+#define GC_USB_DOEPCTL2_DPID_SIZE 0x1
+#define GC_USB_DOEPCTL2_DPID_DEFAULT 0x0
+#define GC_USB_DOEPCTL2_DPID_OFFSET 0xb40
+#define GC_USB_DOEPCTL2_NAKSTS_LSB 0x11
+#define GC_USB_DOEPCTL2_NAKSTS_MASK 0x20000
+#define GC_USB_DOEPCTL2_NAKSTS_SIZE 0x1
+#define GC_USB_DOEPCTL2_NAKSTS_DEFAULT 0x0
+#define GC_USB_DOEPCTL2_NAKSTS_OFFSET 0xb40
+#define GC_USB_DOEPCTL2_EPTYPE_LSB 0x12
+#define GC_USB_DOEPCTL2_EPTYPE_MASK 0xc0000
+#define GC_USB_DOEPCTL2_EPTYPE_SIZE 0x2
+#define GC_USB_DOEPCTL2_EPTYPE_DEFAULT 0x0
+#define GC_USB_DOEPCTL2_EPTYPE_OFFSET 0xb40
+#define GC_USB_DOEPCTL2_SNP_LSB 0x14
+#define GC_USB_DOEPCTL2_SNP_MASK 0x100000
+#define GC_USB_DOEPCTL2_SNP_SIZE 0x1
+#define GC_USB_DOEPCTL2_SNP_DEFAULT 0x0
+#define GC_USB_DOEPCTL2_SNP_OFFSET 0xb40
+#define GC_USB_DOEPCTL2_STALL_LSB 0x15
+#define GC_USB_DOEPCTL2_STALL_MASK 0x200000
+#define GC_USB_DOEPCTL2_STALL_SIZE 0x1
+#define GC_USB_DOEPCTL2_STALL_DEFAULT 0x0
+#define GC_USB_DOEPCTL2_STALL_OFFSET 0xb40
+#define GC_USB_DOEPCTL2_CNAK_LSB 0x1a
+#define GC_USB_DOEPCTL2_CNAK_MASK 0x4000000
+#define GC_USB_DOEPCTL2_CNAK_SIZE 0x1
+#define GC_USB_DOEPCTL2_CNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL2_CNAK_OFFSET 0xb40
+#define GC_USB_DOEPCTL2_SNAK_LSB 0x1b
+#define GC_USB_DOEPCTL2_SNAK_MASK 0x8000000
+#define GC_USB_DOEPCTL2_SNAK_SIZE 0x1
+#define GC_USB_DOEPCTL2_SNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL2_SNAK_OFFSET 0xb40
+#define GC_USB_DOEPCTL2_SETD0PID_LSB 0x1c
+#define GC_USB_DOEPCTL2_SETD0PID_MASK 0x10000000
+#define GC_USB_DOEPCTL2_SETD0PID_SIZE 0x1
+#define GC_USB_DOEPCTL2_SETD0PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL2_SETD0PID_OFFSET 0xb40
+#define GC_USB_DOEPCTL2_SETD1PID_LSB 0x1d
+#define GC_USB_DOEPCTL2_SETD1PID_MASK 0x20000000
+#define GC_USB_DOEPCTL2_SETD1PID_SIZE 0x1
+#define GC_USB_DOEPCTL2_SETD1PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL2_SETD1PID_OFFSET 0xb40
+#define GC_USB_DOEPCTL2_EPDIS_LSB 0x1e
+#define GC_USB_DOEPCTL2_EPDIS_MASK 0x40000000
+#define GC_USB_DOEPCTL2_EPDIS_SIZE 0x1
+#define GC_USB_DOEPCTL2_EPDIS_DEFAULT 0x0
+#define GC_USB_DOEPCTL2_EPDIS_OFFSET 0xb40
+#define GC_USB_DOEPCTL2_EPENA_LSB 0x1f
+#define GC_USB_DOEPCTL2_EPENA_MASK 0x80000000
+#define GC_USB_DOEPCTL2_EPENA_SIZE 0x1
+#define GC_USB_DOEPCTL2_EPENA_DEFAULT 0x0
+#define GC_USB_DOEPCTL2_EPENA_OFFSET 0xb40
+#define GC_USB_DOEPINT2_XFERCOMPL_LSB 0x0
+#define GC_USB_DOEPINT2_XFERCOMPL_MASK 0x1
+#define GC_USB_DOEPINT2_XFERCOMPL_SIZE 0x1
+#define GC_USB_DOEPINT2_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DOEPINT2_XFERCOMPL_OFFSET 0xb48
+#define GC_USB_DOEPINT2_EPDISBLD_LSB 0x1
+#define GC_USB_DOEPINT2_EPDISBLD_MASK 0x2
+#define GC_USB_DOEPINT2_EPDISBLD_SIZE 0x1
+#define GC_USB_DOEPINT2_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DOEPINT2_EPDISBLD_OFFSET 0xb48
+#define GC_USB_DOEPINT2_AHBERR_LSB 0x2
+#define GC_USB_DOEPINT2_AHBERR_MASK 0x4
+#define GC_USB_DOEPINT2_AHBERR_SIZE 0x1
+#define GC_USB_DOEPINT2_AHBERR_DEFAULT 0x0
+#define GC_USB_DOEPINT2_AHBERR_OFFSET 0xb48
+#define GC_USB_DOEPINT2_SETUP_LSB 0x3
+#define GC_USB_DOEPINT2_SETUP_MASK 0x8
+#define GC_USB_DOEPINT2_SETUP_SIZE 0x1
+#define GC_USB_DOEPINT2_SETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT2_SETUP_OFFSET 0xb48
+#define GC_USB_DOEPINT2_OUTTKNEPDIS_LSB 0x4
+#define GC_USB_DOEPINT2_OUTTKNEPDIS_MASK 0x10
+#define GC_USB_DOEPINT2_OUTTKNEPDIS_SIZE 0x1
+#define GC_USB_DOEPINT2_OUTTKNEPDIS_DEFAULT 0x0
+#define GC_USB_DOEPINT2_OUTTKNEPDIS_OFFSET 0xb48
+#define GC_USB_DOEPINT2_STSPHSERCVD_LSB 0x5
+#define GC_USB_DOEPINT2_STSPHSERCVD_MASK 0x20
+#define GC_USB_DOEPINT2_STSPHSERCVD_SIZE 0x1
+#define GC_USB_DOEPINT2_STSPHSERCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT2_STSPHSERCVD_OFFSET 0xb48
+#define GC_USB_DOEPINT2_BACK2BACKSETUP_LSB 0x6
+#define GC_USB_DOEPINT2_BACK2BACKSETUP_MASK 0x40
+#define GC_USB_DOEPINT2_BACK2BACKSETUP_SIZE 0x1
+#define GC_USB_DOEPINT2_BACK2BACKSETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT2_BACK2BACKSETUP_OFFSET 0xb48
+#define GC_USB_DOEPINT2_OUTPKTERR_LSB 0x8
+#define GC_USB_DOEPINT2_OUTPKTERR_MASK 0x100
+#define GC_USB_DOEPINT2_OUTPKTERR_SIZE 0x1
+#define GC_USB_DOEPINT2_OUTPKTERR_DEFAULT 0x0
+#define GC_USB_DOEPINT2_OUTPKTERR_OFFSET 0xb48
+#define GC_USB_DOEPINT2_BNAINTR_LSB 0x9
+#define GC_USB_DOEPINT2_BNAINTR_MASK 0x200
+#define GC_USB_DOEPINT2_BNAINTR_SIZE 0x1
+#define GC_USB_DOEPINT2_BNAINTR_DEFAULT 0x0
+#define GC_USB_DOEPINT2_BNAINTR_OFFSET 0xb48
+#define GC_USB_DOEPINT2_PKTDRPSTS_LSB 0xb
+#define GC_USB_DOEPINT2_PKTDRPSTS_MASK 0x800
+#define GC_USB_DOEPINT2_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DOEPINT2_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DOEPINT2_PKTDRPSTS_OFFSET 0xb48
+#define GC_USB_DOEPINT2_BBLEERR_LSB 0xc
+#define GC_USB_DOEPINT2_BBLEERR_MASK 0x1000
+#define GC_USB_DOEPINT2_BBLEERR_SIZE 0x1
+#define GC_USB_DOEPINT2_BBLEERR_DEFAULT 0x0
+#define GC_USB_DOEPINT2_BBLEERR_OFFSET 0xb48
+#define GC_USB_DOEPINT2_NAKINTRPT_LSB 0xd
+#define GC_USB_DOEPINT2_NAKINTRPT_MASK 0x2000
+#define GC_USB_DOEPINT2_NAKINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT2_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT2_NAKINTRPT_OFFSET 0xb48
+#define GC_USB_DOEPINT2_NYETINTRPT_LSB 0xe
+#define GC_USB_DOEPINT2_NYETINTRPT_MASK 0x4000
+#define GC_USB_DOEPINT2_NYETINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT2_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT2_NYETINTRPT_OFFSET 0xb48
+#define GC_USB_DOEPINT2_STUPPKTRCVD_LSB 0xf
+#define GC_USB_DOEPINT2_STUPPKTRCVD_MASK 0x8000
+#define GC_USB_DOEPINT2_STUPPKTRCVD_SIZE 0x1
+#define GC_USB_DOEPINT2_STUPPKTRCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT2_STUPPKTRCVD_OFFSET 0xb48
+#define GC_USB_DOEPTSIZ2_XFERSIZE_LSB 0x0
+#define GC_USB_DOEPTSIZ2_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DOEPTSIZ2_XFERSIZE_SIZE 0x13
+#define GC_USB_DOEPTSIZ2_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ2_XFERSIZE_OFFSET 0xb50
+#define GC_USB_DOEPTSIZ2_PKTCNT_LSB 0x13
+#define GC_USB_DOEPTSIZ2_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DOEPTSIZ2_PKTCNT_SIZE 0xa
+#define GC_USB_DOEPTSIZ2_PKTCNT_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ2_PKTCNT_OFFSET 0xb50
+#define GC_USB_DOEPTSIZ2_RXDPID_LSB 0x1d
+#define GC_USB_DOEPTSIZ2_RXDPID_MASK 0x60000000
+#define GC_USB_DOEPTSIZ2_RXDPID_SIZE 0x2
+#define GC_USB_DOEPTSIZ2_RXDPID_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ2_RXDPID_OFFSET 0xb50
+#define GC_USB_DOEPDMA2_DMAADDR_LSB 0x0
+#define GC_USB_DOEPDMA2_DMAADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMA2_DMAADDR_SIZE 0x20
+#define GC_USB_DOEPDMA2_DMAADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMA2_DMAADDR_OFFSET 0xb54
+#define GC_USB_DOEPDMAB2_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DOEPDMAB2_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMAB2_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DOEPDMAB2_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMAB2_DMABUFFERADDR_OFFSET 0xb5c
+#define GC_USB_DOEPCTL3_MPS_LSB 0x0
+#define GC_USB_DOEPCTL3_MPS_MASK 0x7ff
+#define GC_USB_DOEPCTL3_MPS_SIZE 0xb
+#define GC_USB_DOEPCTL3_MPS_DEFAULT 0x0
+#define GC_USB_DOEPCTL3_MPS_OFFSET 0xb60
+#define GC_USB_DOEPCTL3_USBACTEP_LSB 0xf
+#define GC_USB_DOEPCTL3_USBACTEP_MASK 0x8000
+#define GC_USB_DOEPCTL3_USBACTEP_SIZE 0x1
+#define GC_USB_DOEPCTL3_USBACTEP_DEFAULT 0x0
+#define GC_USB_DOEPCTL3_USBACTEP_OFFSET 0xb60
+#define GC_USB_DOEPCTL3_DPID_LSB 0x10
+#define GC_USB_DOEPCTL3_DPID_MASK 0x10000
+#define GC_USB_DOEPCTL3_DPID_SIZE 0x1
+#define GC_USB_DOEPCTL3_DPID_DEFAULT 0x0
+#define GC_USB_DOEPCTL3_DPID_OFFSET 0xb60
+#define GC_USB_DOEPCTL3_NAKSTS_LSB 0x11
+#define GC_USB_DOEPCTL3_NAKSTS_MASK 0x20000
+#define GC_USB_DOEPCTL3_NAKSTS_SIZE 0x1
+#define GC_USB_DOEPCTL3_NAKSTS_DEFAULT 0x0
+#define GC_USB_DOEPCTL3_NAKSTS_OFFSET 0xb60
+#define GC_USB_DOEPCTL3_EPTYPE_LSB 0x12
+#define GC_USB_DOEPCTL3_EPTYPE_MASK 0xc0000
+#define GC_USB_DOEPCTL3_EPTYPE_SIZE 0x2
+#define GC_USB_DOEPCTL3_EPTYPE_DEFAULT 0x0
+#define GC_USB_DOEPCTL3_EPTYPE_OFFSET 0xb60
+#define GC_USB_DOEPCTL3_SNP_LSB 0x14
+#define GC_USB_DOEPCTL3_SNP_MASK 0x100000
+#define GC_USB_DOEPCTL3_SNP_SIZE 0x1
+#define GC_USB_DOEPCTL3_SNP_DEFAULT 0x0
+#define GC_USB_DOEPCTL3_SNP_OFFSET 0xb60
+#define GC_USB_DOEPCTL3_STALL_LSB 0x15
+#define GC_USB_DOEPCTL3_STALL_MASK 0x200000
+#define GC_USB_DOEPCTL3_STALL_SIZE 0x1
+#define GC_USB_DOEPCTL3_STALL_DEFAULT 0x0
+#define GC_USB_DOEPCTL3_STALL_OFFSET 0xb60
+#define GC_USB_DOEPCTL3_CNAK_LSB 0x1a
+#define GC_USB_DOEPCTL3_CNAK_MASK 0x4000000
+#define GC_USB_DOEPCTL3_CNAK_SIZE 0x1
+#define GC_USB_DOEPCTL3_CNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL3_CNAK_OFFSET 0xb60
+#define GC_USB_DOEPCTL3_SNAK_LSB 0x1b
+#define GC_USB_DOEPCTL3_SNAK_MASK 0x8000000
+#define GC_USB_DOEPCTL3_SNAK_SIZE 0x1
+#define GC_USB_DOEPCTL3_SNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL3_SNAK_OFFSET 0xb60
+#define GC_USB_DOEPCTL3_SETD0PID_LSB 0x1c
+#define GC_USB_DOEPCTL3_SETD0PID_MASK 0x10000000
+#define GC_USB_DOEPCTL3_SETD0PID_SIZE 0x1
+#define GC_USB_DOEPCTL3_SETD0PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL3_SETD0PID_OFFSET 0xb60
+#define GC_USB_DOEPCTL3_SETD1PID_LSB 0x1d
+#define GC_USB_DOEPCTL3_SETD1PID_MASK 0x20000000
+#define GC_USB_DOEPCTL3_SETD1PID_SIZE 0x1
+#define GC_USB_DOEPCTL3_SETD1PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL3_SETD1PID_OFFSET 0xb60
+#define GC_USB_DOEPCTL3_EPDIS_LSB 0x1e
+#define GC_USB_DOEPCTL3_EPDIS_MASK 0x40000000
+#define GC_USB_DOEPCTL3_EPDIS_SIZE 0x1
+#define GC_USB_DOEPCTL3_EPDIS_DEFAULT 0x0
+#define GC_USB_DOEPCTL3_EPDIS_OFFSET 0xb60
+#define GC_USB_DOEPCTL3_EPENA_LSB 0x1f
+#define GC_USB_DOEPCTL3_EPENA_MASK 0x80000000
+#define GC_USB_DOEPCTL3_EPENA_SIZE 0x1
+#define GC_USB_DOEPCTL3_EPENA_DEFAULT 0x0
+#define GC_USB_DOEPCTL3_EPENA_OFFSET 0xb60
+#define GC_USB_DOEPINT3_XFERCOMPL_LSB 0x0
+#define GC_USB_DOEPINT3_XFERCOMPL_MASK 0x1
+#define GC_USB_DOEPINT3_XFERCOMPL_SIZE 0x1
+#define GC_USB_DOEPINT3_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DOEPINT3_XFERCOMPL_OFFSET 0xb68
+#define GC_USB_DOEPINT3_EPDISBLD_LSB 0x1
+#define GC_USB_DOEPINT3_EPDISBLD_MASK 0x2
+#define GC_USB_DOEPINT3_EPDISBLD_SIZE 0x1
+#define GC_USB_DOEPINT3_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DOEPINT3_EPDISBLD_OFFSET 0xb68
+#define GC_USB_DOEPINT3_AHBERR_LSB 0x2
+#define GC_USB_DOEPINT3_AHBERR_MASK 0x4
+#define GC_USB_DOEPINT3_AHBERR_SIZE 0x1
+#define GC_USB_DOEPINT3_AHBERR_DEFAULT 0x0
+#define GC_USB_DOEPINT3_AHBERR_OFFSET 0xb68
+#define GC_USB_DOEPINT3_SETUP_LSB 0x3
+#define GC_USB_DOEPINT3_SETUP_MASK 0x8
+#define GC_USB_DOEPINT3_SETUP_SIZE 0x1
+#define GC_USB_DOEPINT3_SETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT3_SETUP_OFFSET 0xb68
+#define GC_USB_DOEPINT3_OUTTKNEPDIS_LSB 0x4
+#define GC_USB_DOEPINT3_OUTTKNEPDIS_MASK 0x10
+#define GC_USB_DOEPINT3_OUTTKNEPDIS_SIZE 0x1
+#define GC_USB_DOEPINT3_OUTTKNEPDIS_DEFAULT 0x0
+#define GC_USB_DOEPINT3_OUTTKNEPDIS_OFFSET 0xb68
+#define GC_USB_DOEPINT3_STSPHSERCVD_LSB 0x5
+#define GC_USB_DOEPINT3_STSPHSERCVD_MASK 0x20
+#define GC_USB_DOEPINT3_STSPHSERCVD_SIZE 0x1
+#define GC_USB_DOEPINT3_STSPHSERCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT3_STSPHSERCVD_OFFSET 0xb68
+#define GC_USB_DOEPINT3_BACK2BACKSETUP_LSB 0x6
+#define GC_USB_DOEPINT3_BACK2BACKSETUP_MASK 0x40
+#define GC_USB_DOEPINT3_BACK2BACKSETUP_SIZE 0x1
+#define GC_USB_DOEPINT3_BACK2BACKSETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT3_BACK2BACKSETUP_OFFSET 0xb68
+#define GC_USB_DOEPINT3_OUTPKTERR_LSB 0x8
+#define GC_USB_DOEPINT3_OUTPKTERR_MASK 0x100
+#define GC_USB_DOEPINT3_OUTPKTERR_SIZE 0x1
+#define GC_USB_DOEPINT3_OUTPKTERR_DEFAULT 0x0
+#define GC_USB_DOEPINT3_OUTPKTERR_OFFSET 0xb68
+#define GC_USB_DOEPINT3_BNAINTR_LSB 0x9
+#define GC_USB_DOEPINT3_BNAINTR_MASK 0x200
+#define GC_USB_DOEPINT3_BNAINTR_SIZE 0x1
+#define GC_USB_DOEPINT3_BNAINTR_DEFAULT 0x0
+#define GC_USB_DOEPINT3_BNAINTR_OFFSET 0xb68
+#define GC_USB_DOEPINT3_PKTDRPSTS_LSB 0xb
+#define GC_USB_DOEPINT3_PKTDRPSTS_MASK 0x800
+#define GC_USB_DOEPINT3_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DOEPINT3_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DOEPINT3_PKTDRPSTS_OFFSET 0xb68
+#define GC_USB_DOEPINT3_BBLEERR_LSB 0xc
+#define GC_USB_DOEPINT3_BBLEERR_MASK 0x1000
+#define GC_USB_DOEPINT3_BBLEERR_SIZE 0x1
+#define GC_USB_DOEPINT3_BBLEERR_DEFAULT 0x0
+#define GC_USB_DOEPINT3_BBLEERR_OFFSET 0xb68
+#define GC_USB_DOEPINT3_NAKINTRPT_LSB 0xd
+#define GC_USB_DOEPINT3_NAKINTRPT_MASK 0x2000
+#define GC_USB_DOEPINT3_NAKINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT3_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT3_NAKINTRPT_OFFSET 0xb68
+#define GC_USB_DOEPINT3_NYETINTRPT_LSB 0xe
+#define GC_USB_DOEPINT3_NYETINTRPT_MASK 0x4000
+#define GC_USB_DOEPINT3_NYETINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT3_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT3_NYETINTRPT_OFFSET 0xb68
+#define GC_USB_DOEPINT3_STUPPKTRCVD_LSB 0xf
+#define GC_USB_DOEPINT3_STUPPKTRCVD_MASK 0x8000
+#define GC_USB_DOEPINT3_STUPPKTRCVD_SIZE 0x1
+#define GC_USB_DOEPINT3_STUPPKTRCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT3_STUPPKTRCVD_OFFSET 0xb68
+#define GC_USB_DOEPTSIZ3_XFERSIZE_LSB 0x0
+#define GC_USB_DOEPTSIZ3_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DOEPTSIZ3_XFERSIZE_SIZE 0x13
+#define GC_USB_DOEPTSIZ3_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ3_XFERSIZE_OFFSET 0xb70
+#define GC_USB_DOEPTSIZ3_PKTCNT_LSB 0x13
+#define GC_USB_DOEPTSIZ3_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DOEPTSIZ3_PKTCNT_SIZE 0xa
+#define GC_USB_DOEPTSIZ3_PKTCNT_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ3_PKTCNT_OFFSET 0xb70
+#define GC_USB_DOEPTSIZ3_RXDPID_LSB 0x1d
+#define GC_USB_DOEPTSIZ3_RXDPID_MASK 0x60000000
+#define GC_USB_DOEPTSIZ3_RXDPID_SIZE 0x2
+#define GC_USB_DOEPTSIZ3_RXDPID_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ3_RXDPID_OFFSET 0xb70
+#define GC_USB_DOEPDMA3_DMAADDR_LSB 0x0
+#define GC_USB_DOEPDMA3_DMAADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMA3_DMAADDR_SIZE 0x20
+#define GC_USB_DOEPDMA3_DMAADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMA3_DMAADDR_OFFSET 0xb74
+#define GC_USB_DOEPDMAB3_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DOEPDMAB3_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMAB3_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DOEPDMAB3_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMAB3_DMABUFFERADDR_OFFSET 0xb7c
+#define GC_USB_DOEPCTL4_MPS_LSB 0x0
+#define GC_USB_DOEPCTL4_MPS_MASK 0x7ff
+#define GC_USB_DOEPCTL4_MPS_SIZE 0xb
+#define GC_USB_DOEPCTL4_MPS_DEFAULT 0x0
+#define GC_USB_DOEPCTL4_MPS_OFFSET 0xb80
+#define GC_USB_DOEPCTL4_USBACTEP_LSB 0xf
+#define GC_USB_DOEPCTL4_USBACTEP_MASK 0x8000
+#define GC_USB_DOEPCTL4_USBACTEP_SIZE 0x1
+#define GC_USB_DOEPCTL4_USBACTEP_DEFAULT 0x0
+#define GC_USB_DOEPCTL4_USBACTEP_OFFSET 0xb80
+#define GC_USB_DOEPCTL4_DPID_LSB 0x10
+#define GC_USB_DOEPCTL4_DPID_MASK 0x10000
+#define GC_USB_DOEPCTL4_DPID_SIZE 0x1
+#define GC_USB_DOEPCTL4_DPID_DEFAULT 0x0
+#define GC_USB_DOEPCTL4_DPID_OFFSET 0xb80
+#define GC_USB_DOEPCTL4_NAKSTS_LSB 0x11
+#define GC_USB_DOEPCTL4_NAKSTS_MASK 0x20000
+#define GC_USB_DOEPCTL4_NAKSTS_SIZE 0x1
+#define GC_USB_DOEPCTL4_NAKSTS_DEFAULT 0x0
+#define GC_USB_DOEPCTL4_NAKSTS_OFFSET 0xb80
+#define GC_USB_DOEPCTL4_EPTYPE_LSB 0x12
+#define GC_USB_DOEPCTL4_EPTYPE_MASK 0xc0000
+#define GC_USB_DOEPCTL4_EPTYPE_SIZE 0x2
+#define GC_USB_DOEPCTL4_EPTYPE_DEFAULT 0x0
+#define GC_USB_DOEPCTL4_EPTYPE_OFFSET 0xb80
+#define GC_USB_DOEPCTL4_SNP_LSB 0x14
+#define GC_USB_DOEPCTL4_SNP_MASK 0x100000
+#define GC_USB_DOEPCTL4_SNP_SIZE 0x1
+#define GC_USB_DOEPCTL4_SNP_DEFAULT 0x0
+#define GC_USB_DOEPCTL4_SNP_OFFSET 0xb80
+#define GC_USB_DOEPCTL4_STALL_LSB 0x15
+#define GC_USB_DOEPCTL4_STALL_MASK 0x200000
+#define GC_USB_DOEPCTL4_STALL_SIZE 0x1
+#define GC_USB_DOEPCTL4_STALL_DEFAULT 0x0
+#define GC_USB_DOEPCTL4_STALL_OFFSET 0xb80
+#define GC_USB_DOEPCTL4_CNAK_LSB 0x1a
+#define GC_USB_DOEPCTL4_CNAK_MASK 0x4000000
+#define GC_USB_DOEPCTL4_CNAK_SIZE 0x1
+#define GC_USB_DOEPCTL4_CNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL4_CNAK_OFFSET 0xb80
+#define GC_USB_DOEPCTL4_SNAK_LSB 0x1b
+#define GC_USB_DOEPCTL4_SNAK_MASK 0x8000000
+#define GC_USB_DOEPCTL4_SNAK_SIZE 0x1
+#define GC_USB_DOEPCTL4_SNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL4_SNAK_OFFSET 0xb80
+#define GC_USB_DOEPCTL4_SETD0PID_LSB 0x1c
+#define GC_USB_DOEPCTL4_SETD0PID_MASK 0x10000000
+#define GC_USB_DOEPCTL4_SETD0PID_SIZE 0x1
+#define GC_USB_DOEPCTL4_SETD0PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL4_SETD0PID_OFFSET 0xb80
+#define GC_USB_DOEPCTL4_SETD1PID_LSB 0x1d
+#define GC_USB_DOEPCTL4_SETD1PID_MASK 0x20000000
+#define GC_USB_DOEPCTL4_SETD1PID_SIZE 0x1
+#define GC_USB_DOEPCTL4_SETD1PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL4_SETD1PID_OFFSET 0xb80
+#define GC_USB_DOEPCTL4_EPDIS_LSB 0x1e
+#define GC_USB_DOEPCTL4_EPDIS_MASK 0x40000000
+#define GC_USB_DOEPCTL4_EPDIS_SIZE 0x1
+#define GC_USB_DOEPCTL4_EPDIS_DEFAULT 0x0
+#define GC_USB_DOEPCTL4_EPDIS_OFFSET 0xb80
+#define GC_USB_DOEPCTL4_EPENA_LSB 0x1f
+#define GC_USB_DOEPCTL4_EPENA_MASK 0x80000000
+#define GC_USB_DOEPCTL4_EPENA_SIZE 0x1
+#define GC_USB_DOEPCTL4_EPENA_DEFAULT 0x0
+#define GC_USB_DOEPCTL4_EPENA_OFFSET 0xb80
+#define GC_USB_DOEPINT4_XFERCOMPL_LSB 0x0
+#define GC_USB_DOEPINT4_XFERCOMPL_MASK 0x1
+#define GC_USB_DOEPINT4_XFERCOMPL_SIZE 0x1
+#define GC_USB_DOEPINT4_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DOEPINT4_XFERCOMPL_OFFSET 0xb88
+#define GC_USB_DOEPINT4_EPDISBLD_LSB 0x1
+#define GC_USB_DOEPINT4_EPDISBLD_MASK 0x2
+#define GC_USB_DOEPINT4_EPDISBLD_SIZE 0x1
+#define GC_USB_DOEPINT4_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DOEPINT4_EPDISBLD_OFFSET 0xb88
+#define GC_USB_DOEPINT4_AHBERR_LSB 0x2
+#define GC_USB_DOEPINT4_AHBERR_MASK 0x4
+#define GC_USB_DOEPINT4_AHBERR_SIZE 0x1
+#define GC_USB_DOEPINT4_AHBERR_DEFAULT 0x0
+#define GC_USB_DOEPINT4_AHBERR_OFFSET 0xb88
+#define GC_USB_DOEPINT4_SETUP_LSB 0x3
+#define GC_USB_DOEPINT4_SETUP_MASK 0x8
+#define GC_USB_DOEPINT4_SETUP_SIZE 0x1
+#define GC_USB_DOEPINT4_SETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT4_SETUP_OFFSET 0xb88
+#define GC_USB_DOEPINT4_OUTTKNEPDIS_LSB 0x4
+#define GC_USB_DOEPINT4_OUTTKNEPDIS_MASK 0x10
+#define GC_USB_DOEPINT4_OUTTKNEPDIS_SIZE 0x1
+#define GC_USB_DOEPINT4_OUTTKNEPDIS_DEFAULT 0x0
+#define GC_USB_DOEPINT4_OUTTKNEPDIS_OFFSET 0xb88
+#define GC_USB_DOEPINT4_STSPHSERCVD_LSB 0x5
+#define GC_USB_DOEPINT4_STSPHSERCVD_MASK 0x20
+#define GC_USB_DOEPINT4_STSPHSERCVD_SIZE 0x1
+#define GC_USB_DOEPINT4_STSPHSERCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT4_STSPHSERCVD_OFFSET 0xb88
+#define GC_USB_DOEPINT4_BACK2BACKSETUP_LSB 0x6
+#define GC_USB_DOEPINT4_BACK2BACKSETUP_MASK 0x40
+#define GC_USB_DOEPINT4_BACK2BACKSETUP_SIZE 0x1
+#define GC_USB_DOEPINT4_BACK2BACKSETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT4_BACK2BACKSETUP_OFFSET 0xb88
+#define GC_USB_DOEPINT4_OUTPKTERR_LSB 0x8
+#define GC_USB_DOEPINT4_OUTPKTERR_MASK 0x100
+#define GC_USB_DOEPINT4_OUTPKTERR_SIZE 0x1
+#define GC_USB_DOEPINT4_OUTPKTERR_DEFAULT 0x0
+#define GC_USB_DOEPINT4_OUTPKTERR_OFFSET 0xb88
+#define GC_USB_DOEPINT4_BNAINTR_LSB 0x9
+#define GC_USB_DOEPINT4_BNAINTR_MASK 0x200
+#define GC_USB_DOEPINT4_BNAINTR_SIZE 0x1
+#define GC_USB_DOEPINT4_BNAINTR_DEFAULT 0x0
+#define GC_USB_DOEPINT4_BNAINTR_OFFSET 0xb88
+#define GC_USB_DOEPINT4_PKTDRPSTS_LSB 0xb
+#define GC_USB_DOEPINT4_PKTDRPSTS_MASK 0x800
+#define GC_USB_DOEPINT4_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DOEPINT4_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DOEPINT4_PKTDRPSTS_OFFSET 0xb88
+#define GC_USB_DOEPINT4_BBLEERR_LSB 0xc
+#define GC_USB_DOEPINT4_BBLEERR_MASK 0x1000
+#define GC_USB_DOEPINT4_BBLEERR_SIZE 0x1
+#define GC_USB_DOEPINT4_BBLEERR_DEFAULT 0x0
+#define GC_USB_DOEPINT4_BBLEERR_OFFSET 0xb88
+#define GC_USB_DOEPINT4_NAKINTRPT_LSB 0xd
+#define GC_USB_DOEPINT4_NAKINTRPT_MASK 0x2000
+#define GC_USB_DOEPINT4_NAKINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT4_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT4_NAKINTRPT_OFFSET 0xb88
+#define GC_USB_DOEPINT4_NYETINTRPT_LSB 0xe
+#define GC_USB_DOEPINT4_NYETINTRPT_MASK 0x4000
+#define GC_USB_DOEPINT4_NYETINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT4_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT4_NYETINTRPT_OFFSET 0xb88
+#define GC_USB_DOEPINT4_STUPPKTRCVD_LSB 0xf
+#define GC_USB_DOEPINT4_STUPPKTRCVD_MASK 0x8000
+#define GC_USB_DOEPINT4_STUPPKTRCVD_SIZE 0x1
+#define GC_USB_DOEPINT4_STUPPKTRCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT4_STUPPKTRCVD_OFFSET 0xb88
+#define GC_USB_DOEPTSIZ4_XFERSIZE_LSB 0x0
+#define GC_USB_DOEPTSIZ4_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DOEPTSIZ4_XFERSIZE_SIZE 0x13
+#define GC_USB_DOEPTSIZ4_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ4_XFERSIZE_OFFSET 0xb90
+#define GC_USB_DOEPTSIZ4_PKTCNT_LSB 0x13
+#define GC_USB_DOEPTSIZ4_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DOEPTSIZ4_PKTCNT_SIZE 0xa
+#define GC_USB_DOEPTSIZ4_PKTCNT_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ4_PKTCNT_OFFSET 0xb90
+#define GC_USB_DOEPTSIZ4_RXDPID_LSB 0x1d
+#define GC_USB_DOEPTSIZ4_RXDPID_MASK 0x60000000
+#define GC_USB_DOEPTSIZ4_RXDPID_SIZE 0x2
+#define GC_USB_DOEPTSIZ4_RXDPID_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ4_RXDPID_OFFSET 0xb90
+#define GC_USB_DOEPDMA4_DMAADDR_LSB 0x0
+#define GC_USB_DOEPDMA4_DMAADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMA4_DMAADDR_SIZE 0x20
+#define GC_USB_DOEPDMA4_DMAADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMA4_DMAADDR_OFFSET 0xb94
+#define GC_USB_DOEPDMAB4_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DOEPDMAB4_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMAB4_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DOEPDMAB4_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMAB4_DMABUFFERADDR_OFFSET 0xb9c
+#define GC_USB_DOEPCTL5_MPS_LSB 0x0
+#define GC_USB_DOEPCTL5_MPS_MASK 0x7ff
+#define GC_USB_DOEPCTL5_MPS_SIZE 0xb
+#define GC_USB_DOEPCTL5_MPS_DEFAULT 0x0
+#define GC_USB_DOEPCTL5_MPS_OFFSET 0xba0
+#define GC_USB_DOEPCTL5_USBACTEP_LSB 0xf
+#define GC_USB_DOEPCTL5_USBACTEP_MASK 0x8000
+#define GC_USB_DOEPCTL5_USBACTEP_SIZE 0x1
+#define GC_USB_DOEPCTL5_USBACTEP_DEFAULT 0x0
+#define GC_USB_DOEPCTL5_USBACTEP_OFFSET 0xba0
+#define GC_USB_DOEPCTL5_DPID_LSB 0x10
+#define GC_USB_DOEPCTL5_DPID_MASK 0x10000
+#define GC_USB_DOEPCTL5_DPID_SIZE 0x1
+#define GC_USB_DOEPCTL5_DPID_DEFAULT 0x0
+#define GC_USB_DOEPCTL5_DPID_OFFSET 0xba0
+#define GC_USB_DOEPCTL5_NAKSTS_LSB 0x11
+#define GC_USB_DOEPCTL5_NAKSTS_MASK 0x20000
+#define GC_USB_DOEPCTL5_NAKSTS_SIZE 0x1
+#define GC_USB_DOEPCTL5_NAKSTS_DEFAULT 0x0
+#define GC_USB_DOEPCTL5_NAKSTS_OFFSET 0xba0
+#define GC_USB_DOEPCTL5_EPTYPE_LSB 0x12
+#define GC_USB_DOEPCTL5_EPTYPE_MASK 0xc0000
+#define GC_USB_DOEPCTL5_EPTYPE_SIZE 0x2
+#define GC_USB_DOEPCTL5_EPTYPE_DEFAULT 0x0
+#define GC_USB_DOEPCTL5_EPTYPE_OFFSET 0xba0
+#define GC_USB_DOEPCTL5_SNP_LSB 0x14
+#define GC_USB_DOEPCTL5_SNP_MASK 0x100000
+#define GC_USB_DOEPCTL5_SNP_SIZE 0x1
+#define GC_USB_DOEPCTL5_SNP_DEFAULT 0x0
+#define GC_USB_DOEPCTL5_SNP_OFFSET 0xba0
+#define GC_USB_DOEPCTL5_STALL_LSB 0x15
+#define GC_USB_DOEPCTL5_STALL_MASK 0x200000
+#define GC_USB_DOEPCTL5_STALL_SIZE 0x1
+#define GC_USB_DOEPCTL5_STALL_DEFAULT 0x0
+#define GC_USB_DOEPCTL5_STALL_OFFSET 0xba0
+#define GC_USB_DOEPCTL5_CNAK_LSB 0x1a
+#define GC_USB_DOEPCTL5_CNAK_MASK 0x4000000
+#define GC_USB_DOEPCTL5_CNAK_SIZE 0x1
+#define GC_USB_DOEPCTL5_CNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL5_CNAK_OFFSET 0xba0
+#define GC_USB_DOEPCTL5_SNAK_LSB 0x1b
+#define GC_USB_DOEPCTL5_SNAK_MASK 0x8000000
+#define GC_USB_DOEPCTL5_SNAK_SIZE 0x1
+#define GC_USB_DOEPCTL5_SNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL5_SNAK_OFFSET 0xba0
+#define GC_USB_DOEPCTL5_SETD0PID_LSB 0x1c
+#define GC_USB_DOEPCTL5_SETD0PID_MASK 0x10000000
+#define GC_USB_DOEPCTL5_SETD0PID_SIZE 0x1
+#define GC_USB_DOEPCTL5_SETD0PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL5_SETD0PID_OFFSET 0xba0
+#define GC_USB_DOEPCTL5_SETD1PID_LSB 0x1d
+#define GC_USB_DOEPCTL5_SETD1PID_MASK 0x20000000
+#define GC_USB_DOEPCTL5_SETD1PID_SIZE 0x1
+#define GC_USB_DOEPCTL5_SETD1PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL5_SETD1PID_OFFSET 0xba0
+#define GC_USB_DOEPCTL5_EPDIS_LSB 0x1e
+#define GC_USB_DOEPCTL5_EPDIS_MASK 0x40000000
+#define GC_USB_DOEPCTL5_EPDIS_SIZE 0x1
+#define GC_USB_DOEPCTL5_EPDIS_DEFAULT 0x0
+#define GC_USB_DOEPCTL5_EPDIS_OFFSET 0xba0
+#define GC_USB_DOEPCTL5_EPENA_LSB 0x1f
+#define GC_USB_DOEPCTL5_EPENA_MASK 0x80000000
+#define GC_USB_DOEPCTL5_EPENA_SIZE 0x1
+#define GC_USB_DOEPCTL5_EPENA_DEFAULT 0x0
+#define GC_USB_DOEPCTL5_EPENA_OFFSET 0xba0
+#define GC_USB_DOEPINT5_XFERCOMPL_LSB 0x0
+#define GC_USB_DOEPINT5_XFERCOMPL_MASK 0x1
+#define GC_USB_DOEPINT5_XFERCOMPL_SIZE 0x1
+#define GC_USB_DOEPINT5_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DOEPINT5_XFERCOMPL_OFFSET 0xba8
+#define GC_USB_DOEPINT5_EPDISBLD_LSB 0x1
+#define GC_USB_DOEPINT5_EPDISBLD_MASK 0x2
+#define GC_USB_DOEPINT5_EPDISBLD_SIZE 0x1
+#define GC_USB_DOEPINT5_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DOEPINT5_EPDISBLD_OFFSET 0xba8
+#define GC_USB_DOEPINT5_AHBERR_LSB 0x2
+#define GC_USB_DOEPINT5_AHBERR_MASK 0x4
+#define GC_USB_DOEPINT5_AHBERR_SIZE 0x1
+#define GC_USB_DOEPINT5_AHBERR_DEFAULT 0x0
+#define GC_USB_DOEPINT5_AHBERR_OFFSET 0xba8
+#define GC_USB_DOEPINT5_SETUP_LSB 0x3
+#define GC_USB_DOEPINT5_SETUP_MASK 0x8
+#define GC_USB_DOEPINT5_SETUP_SIZE 0x1
+#define GC_USB_DOEPINT5_SETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT5_SETUP_OFFSET 0xba8
+#define GC_USB_DOEPINT5_OUTTKNEPDIS_LSB 0x4
+#define GC_USB_DOEPINT5_OUTTKNEPDIS_MASK 0x10
+#define GC_USB_DOEPINT5_OUTTKNEPDIS_SIZE 0x1
+#define GC_USB_DOEPINT5_OUTTKNEPDIS_DEFAULT 0x0
+#define GC_USB_DOEPINT5_OUTTKNEPDIS_OFFSET 0xba8
+#define GC_USB_DOEPINT5_STSPHSERCVD_LSB 0x5
+#define GC_USB_DOEPINT5_STSPHSERCVD_MASK 0x20
+#define GC_USB_DOEPINT5_STSPHSERCVD_SIZE 0x1
+#define GC_USB_DOEPINT5_STSPHSERCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT5_STSPHSERCVD_OFFSET 0xba8
+#define GC_USB_DOEPINT5_BACK2BACKSETUP_LSB 0x6
+#define GC_USB_DOEPINT5_BACK2BACKSETUP_MASK 0x40
+#define GC_USB_DOEPINT5_BACK2BACKSETUP_SIZE 0x1
+#define GC_USB_DOEPINT5_BACK2BACKSETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT5_BACK2BACKSETUP_OFFSET 0xba8
+#define GC_USB_DOEPINT5_OUTPKTERR_LSB 0x8
+#define GC_USB_DOEPINT5_OUTPKTERR_MASK 0x100
+#define GC_USB_DOEPINT5_OUTPKTERR_SIZE 0x1
+#define GC_USB_DOEPINT5_OUTPKTERR_DEFAULT 0x0
+#define GC_USB_DOEPINT5_OUTPKTERR_OFFSET 0xba8
+#define GC_USB_DOEPINT5_BNAINTR_LSB 0x9
+#define GC_USB_DOEPINT5_BNAINTR_MASK 0x200
+#define GC_USB_DOEPINT5_BNAINTR_SIZE 0x1
+#define GC_USB_DOEPINT5_BNAINTR_DEFAULT 0x0
+#define GC_USB_DOEPINT5_BNAINTR_OFFSET 0xba8
+#define GC_USB_DOEPINT5_PKTDRPSTS_LSB 0xb
+#define GC_USB_DOEPINT5_PKTDRPSTS_MASK 0x800
+#define GC_USB_DOEPINT5_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DOEPINT5_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DOEPINT5_PKTDRPSTS_OFFSET 0xba8
+#define GC_USB_DOEPINT5_BBLEERR_LSB 0xc
+#define GC_USB_DOEPINT5_BBLEERR_MASK 0x1000
+#define GC_USB_DOEPINT5_BBLEERR_SIZE 0x1
+#define GC_USB_DOEPINT5_BBLEERR_DEFAULT 0x0
+#define GC_USB_DOEPINT5_BBLEERR_OFFSET 0xba8
+#define GC_USB_DOEPINT5_NAKINTRPT_LSB 0xd
+#define GC_USB_DOEPINT5_NAKINTRPT_MASK 0x2000
+#define GC_USB_DOEPINT5_NAKINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT5_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT5_NAKINTRPT_OFFSET 0xba8
+#define GC_USB_DOEPINT5_NYETINTRPT_LSB 0xe
+#define GC_USB_DOEPINT5_NYETINTRPT_MASK 0x4000
+#define GC_USB_DOEPINT5_NYETINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT5_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT5_NYETINTRPT_OFFSET 0xba8
+#define GC_USB_DOEPINT5_STUPPKTRCVD_LSB 0xf
+#define GC_USB_DOEPINT5_STUPPKTRCVD_MASK 0x8000
+#define GC_USB_DOEPINT5_STUPPKTRCVD_SIZE 0x1
+#define GC_USB_DOEPINT5_STUPPKTRCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT5_STUPPKTRCVD_OFFSET 0xba8
+#define GC_USB_DOEPTSIZ5_XFERSIZE_LSB 0x0
+#define GC_USB_DOEPTSIZ5_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DOEPTSIZ5_XFERSIZE_SIZE 0x13
+#define GC_USB_DOEPTSIZ5_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ5_XFERSIZE_OFFSET 0xbb0
+#define GC_USB_DOEPTSIZ5_PKTCNT_LSB 0x13
+#define GC_USB_DOEPTSIZ5_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DOEPTSIZ5_PKTCNT_SIZE 0xa
+#define GC_USB_DOEPTSIZ5_PKTCNT_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ5_PKTCNT_OFFSET 0xbb0
+#define GC_USB_DOEPTSIZ5_RXDPID_LSB 0x1d
+#define GC_USB_DOEPTSIZ5_RXDPID_MASK 0x60000000
+#define GC_USB_DOEPTSIZ5_RXDPID_SIZE 0x2
+#define GC_USB_DOEPTSIZ5_RXDPID_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ5_RXDPID_OFFSET 0xbb0
+#define GC_USB_DOEPDMA5_DMAADDR_LSB 0x0
+#define GC_USB_DOEPDMA5_DMAADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMA5_DMAADDR_SIZE 0x20
+#define GC_USB_DOEPDMA5_DMAADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMA5_DMAADDR_OFFSET 0xbb4
+#define GC_USB_DOEPDMAB5_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DOEPDMAB5_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMAB5_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DOEPDMAB5_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMAB5_DMABUFFERADDR_OFFSET 0xbbc
+#define GC_USB_DOEPCTL6_MPS_LSB 0x0
+#define GC_USB_DOEPCTL6_MPS_MASK 0x7ff
+#define GC_USB_DOEPCTL6_MPS_SIZE 0xb
+#define GC_USB_DOEPCTL6_MPS_DEFAULT 0x0
+#define GC_USB_DOEPCTL6_MPS_OFFSET 0xbc0
+#define GC_USB_DOEPCTL6_USBACTEP_LSB 0xf
+#define GC_USB_DOEPCTL6_USBACTEP_MASK 0x8000
+#define GC_USB_DOEPCTL6_USBACTEP_SIZE 0x1
+#define GC_USB_DOEPCTL6_USBACTEP_DEFAULT 0x0
+#define GC_USB_DOEPCTL6_USBACTEP_OFFSET 0xbc0
+#define GC_USB_DOEPCTL6_DPID_LSB 0x10
+#define GC_USB_DOEPCTL6_DPID_MASK 0x10000
+#define GC_USB_DOEPCTL6_DPID_SIZE 0x1
+#define GC_USB_DOEPCTL6_DPID_DEFAULT 0x0
+#define GC_USB_DOEPCTL6_DPID_OFFSET 0xbc0
+#define GC_USB_DOEPCTL6_NAKSTS_LSB 0x11
+#define GC_USB_DOEPCTL6_NAKSTS_MASK 0x20000
+#define GC_USB_DOEPCTL6_NAKSTS_SIZE 0x1
+#define GC_USB_DOEPCTL6_NAKSTS_DEFAULT 0x0
+#define GC_USB_DOEPCTL6_NAKSTS_OFFSET 0xbc0
+#define GC_USB_DOEPCTL6_EPTYPE_LSB 0x12
+#define GC_USB_DOEPCTL6_EPTYPE_MASK 0xc0000
+#define GC_USB_DOEPCTL6_EPTYPE_SIZE 0x2
+#define GC_USB_DOEPCTL6_EPTYPE_DEFAULT 0x0
+#define GC_USB_DOEPCTL6_EPTYPE_OFFSET 0xbc0
+#define GC_USB_DOEPCTL6_SNP_LSB 0x14
+#define GC_USB_DOEPCTL6_SNP_MASK 0x100000
+#define GC_USB_DOEPCTL6_SNP_SIZE 0x1
+#define GC_USB_DOEPCTL6_SNP_DEFAULT 0x0
+#define GC_USB_DOEPCTL6_SNP_OFFSET 0xbc0
+#define GC_USB_DOEPCTL6_STALL_LSB 0x15
+#define GC_USB_DOEPCTL6_STALL_MASK 0x200000
+#define GC_USB_DOEPCTL6_STALL_SIZE 0x1
+#define GC_USB_DOEPCTL6_STALL_DEFAULT 0x0
+#define GC_USB_DOEPCTL6_STALL_OFFSET 0xbc0
+#define GC_USB_DOEPCTL6_CNAK_LSB 0x1a
+#define GC_USB_DOEPCTL6_CNAK_MASK 0x4000000
+#define GC_USB_DOEPCTL6_CNAK_SIZE 0x1
+#define GC_USB_DOEPCTL6_CNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL6_CNAK_OFFSET 0xbc0
+#define GC_USB_DOEPCTL6_SNAK_LSB 0x1b
+#define GC_USB_DOEPCTL6_SNAK_MASK 0x8000000
+#define GC_USB_DOEPCTL6_SNAK_SIZE 0x1
+#define GC_USB_DOEPCTL6_SNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL6_SNAK_OFFSET 0xbc0
+#define GC_USB_DOEPCTL6_SETD0PID_LSB 0x1c
+#define GC_USB_DOEPCTL6_SETD0PID_MASK 0x10000000
+#define GC_USB_DOEPCTL6_SETD0PID_SIZE 0x1
+#define GC_USB_DOEPCTL6_SETD0PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL6_SETD0PID_OFFSET 0xbc0
+#define GC_USB_DOEPCTL6_SETD1PID_LSB 0x1d
+#define GC_USB_DOEPCTL6_SETD1PID_MASK 0x20000000
+#define GC_USB_DOEPCTL6_SETD1PID_SIZE 0x1
+#define GC_USB_DOEPCTL6_SETD1PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL6_SETD1PID_OFFSET 0xbc0
+#define GC_USB_DOEPCTL6_EPDIS_LSB 0x1e
+#define GC_USB_DOEPCTL6_EPDIS_MASK 0x40000000
+#define GC_USB_DOEPCTL6_EPDIS_SIZE 0x1
+#define GC_USB_DOEPCTL6_EPDIS_DEFAULT 0x0
+#define GC_USB_DOEPCTL6_EPDIS_OFFSET 0xbc0
+#define GC_USB_DOEPCTL6_EPENA_LSB 0x1f
+#define GC_USB_DOEPCTL6_EPENA_MASK 0x80000000
+#define GC_USB_DOEPCTL6_EPENA_SIZE 0x1
+#define GC_USB_DOEPCTL6_EPENA_DEFAULT 0x0
+#define GC_USB_DOEPCTL6_EPENA_OFFSET 0xbc0
+#define GC_USB_DOEPINT6_XFERCOMPL_LSB 0x0
+#define GC_USB_DOEPINT6_XFERCOMPL_MASK 0x1
+#define GC_USB_DOEPINT6_XFERCOMPL_SIZE 0x1
+#define GC_USB_DOEPINT6_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DOEPINT6_XFERCOMPL_OFFSET 0xbc8
+#define GC_USB_DOEPINT6_EPDISBLD_LSB 0x1
+#define GC_USB_DOEPINT6_EPDISBLD_MASK 0x2
+#define GC_USB_DOEPINT6_EPDISBLD_SIZE 0x1
+#define GC_USB_DOEPINT6_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DOEPINT6_EPDISBLD_OFFSET 0xbc8
+#define GC_USB_DOEPINT6_AHBERR_LSB 0x2
+#define GC_USB_DOEPINT6_AHBERR_MASK 0x4
+#define GC_USB_DOEPINT6_AHBERR_SIZE 0x1
+#define GC_USB_DOEPINT6_AHBERR_DEFAULT 0x0
+#define GC_USB_DOEPINT6_AHBERR_OFFSET 0xbc8
+#define GC_USB_DOEPINT6_SETUP_LSB 0x3
+#define GC_USB_DOEPINT6_SETUP_MASK 0x8
+#define GC_USB_DOEPINT6_SETUP_SIZE 0x1
+#define GC_USB_DOEPINT6_SETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT6_SETUP_OFFSET 0xbc8
+#define GC_USB_DOEPINT6_OUTTKNEPDIS_LSB 0x4
+#define GC_USB_DOEPINT6_OUTTKNEPDIS_MASK 0x10
+#define GC_USB_DOEPINT6_OUTTKNEPDIS_SIZE 0x1
+#define GC_USB_DOEPINT6_OUTTKNEPDIS_DEFAULT 0x0
+#define GC_USB_DOEPINT6_OUTTKNEPDIS_OFFSET 0xbc8
+#define GC_USB_DOEPINT6_STSPHSERCVD_LSB 0x5
+#define GC_USB_DOEPINT6_STSPHSERCVD_MASK 0x20
+#define GC_USB_DOEPINT6_STSPHSERCVD_SIZE 0x1
+#define GC_USB_DOEPINT6_STSPHSERCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT6_STSPHSERCVD_OFFSET 0xbc8
+#define GC_USB_DOEPINT6_BACK2BACKSETUP_LSB 0x6
+#define GC_USB_DOEPINT6_BACK2BACKSETUP_MASK 0x40
+#define GC_USB_DOEPINT6_BACK2BACKSETUP_SIZE 0x1
+#define GC_USB_DOEPINT6_BACK2BACKSETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT6_BACK2BACKSETUP_OFFSET 0xbc8
+#define GC_USB_DOEPINT6_OUTPKTERR_LSB 0x8
+#define GC_USB_DOEPINT6_OUTPKTERR_MASK 0x100
+#define GC_USB_DOEPINT6_OUTPKTERR_SIZE 0x1
+#define GC_USB_DOEPINT6_OUTPKTERR_DEFAULT 0x0
+#define GC_USB_DOEPINT6_OUTPKTERR_OFFSET 0xbc8
+#define GC_USB_DOEPINT6_BNAINTR_LSB 0x9
+#define GC_USB_DOEPINT6_BNAINTR_MASK 0x200
+#define GC_USB_DOEPINT6_BNAINTR_SIZE 0x1
+#define GC_USB_DOEPINT6_BNAINTR_DEFAULT 0x0
+#define GC_USB_DOEPINT6_BNAINTR_OFFSET 0xbc8
+#define GC_USB_DOEPINT6_PKTDRPSTS_LSB 0xb
+#define GC_USB_DOEPINT6_PKTDRPSTS_MASK 0x800
+#define GC_USB_DOEPINT6_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DOEPINT6_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DOEPINT6_PKTDRPSTS_OFFSET 0xbc8
+#define GC_USB_DOEPINT6_BBLEERR_LSB 0xc
+#define GC_USB_DOEPINT6_BBLEERR_MASK 0x1000
+#define GC_USB_DOEPINT6_BBLEERR_SIZE 0x1
+#define GC_USB_DOEPINT6_BBLEERR_DEFAULT 0x0
+#define GC_USB_DOEPINT6_BBLEERR_OFFSET 0xbc8
+#define GC_USB_DOEPINT6_NAKINTRPT_LSB 0xd
+#define GC_USB_DOEPINT6_NAKINTRPT_MASK 0x2000
+#define GC_USB_DOEPINT6_NAKINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT6_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT6_NAKINTRPT_OFFSET 0xbc8
+#define GC_USB_DOEPINT6_NYETINTRPT_LSB 0xe
+#define GC_USB_DOEPINT6_NYETINTRPT_MASK 0x4000
+#define GC_USB_DOEPINT6_NYETINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT6_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT6_NYETINTRPT_OFFSET 0xbc8
+#define GC_USB_DOEPINT6_STUPPKTRCVD_LSB 0xf
+#define GC_USB_DOEPINT6_STUPPKTRCVD_MASK 0x8000
+#define GC_USB_DOEPINT6_STUPPKTRCVD_SIZE 0x1
+#define GC_USB_DOEPINT6_STUPPKTRCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT6_STUPPKTRCVD_OFFSET 0xbc8
+#define GC_USB_DOEPTSIZ6_XFERSIZE_LSB 0x0
+#define GC_USB_DOEPTSIZ6_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DOEPTSIZ6_XFERSIZE_SIZE 0x13
+#define GC_USB_DOEPTSIZ6_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ6_XFERSIZE_OFFSET 0xbd0
+#define GC_USB_DOEPTSIZ6_PKTCNT_LSB 0x13
+#define GC_USB_DOEPTSIZ6_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DOEPTSIZ6_PKTCNT_SIZE 0xa
+#define GC_USB_DOEPTSIZ6_PKTCNT_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ6_PKTCNT_OFFSET 0xbd0
+#define GC_USB_DOEPTSIZ6_RXDPID_LSB 0x1d
+#define GC_USB_DOEPTSIZ6_RXDPID_MASK 0x60000000
+#define GC_USB_DOEPTSIZ6_RXDPID_SIZE 0x2
+#define GC_USB_DOEPTSIZ6_RXDPID_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ6_RXDPID_OFFSET 0xbd0
+#define GC_USB_DOEPDMA6_DMAADDR_LSB 0x0
+#define GC_USB_DOEPDMA6_DMAADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMA6_DMAADDR_SIZE 0x20
+#define GC_USB_DOEPDMA6_DMAADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMA6_DMAADDR_OFFSET 0xbd4
+#define GC_USB_DOEPDMAB6_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DOEPDMAB6_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMAB6_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DOEPDMAB6_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMAB6_DMABUFFERADDR_OFFSET 0xbdc
+#define GC_USB_DOEPCTL7_MPS_LSB 0x0
+#define GC_USB_DOEPCTL7_MPS_MASK 0x7ff
+#define GC_USB_DOEPCTL7_MPS_SIZE 0xb
+#define GC_USB_DOEPCTL7_MPS_DEFAULT 0x0
+#define GC_USB_DOEPCTL7_MPS_OFFSET 0xbe0
+#define GC_USB_DOEPCTL7_USBACTEP_LSB 0xf
+#define GC_USB_DOEPCTL7_USBACTEP_MASK 0x8000
+#define GC_USB_DOEPCTL7_USBACTEP_SIZE 0x1
+#define GC_USB_DOEPCTL7_USBACTEP_DEFAULT 0x0
+#define GC_USB_DOEPCTL7_USBACTEP_OFFSET 0xbe0
+#define GC_USB_DOEPCTL7_DPID_LSB 0x10
+#define GC_USB_DOEPCTL7_DPID_MASK 0x10000
+#define GC_USB_DOEPCTL7_DPID_SIZE 0x1
+#define GC_USB_DOEPCTL7_DPID_DEFAULT 0x0
+#define GC_USB_DOEPCTL7_DPID_OFFSET 0xbe0
+#define GC_USB_DOEPCTL7_NAKSTS_LSB 0x11
+#define GC_USB_DOEPCTL7_NAKSTS_MASK 0x20000
+#define GC_USB_DOEPCTL7_NAKSTS_SIZE 0x1
+#define GC_USB_DOEPCTL7_NAKSTS_DEFAULT 0x0
+#define GC_USB_DOEPCTL7_NAKSTS_OFFSET 0xbe0
+#define GC_USB_DOEPCTL7_EPTYPE_LSB 0x12
+#define GC_USB_DOEPCTL7_EPTYPE_MASK 0xc0000
+#define GC_USB_DOEPCTL7_EPTYPE_SIZE 0x2
+#define GC_USB_DOEPCTL7_EPTYPE_DEFAULT 0x0
+#define GC_USB_DOEPCTL7_EPTYPE_OFFSET 0xbe0
+#define GC_USB_DOEPCTL7_SNP_LSB 0x14
+#define GC_USB_DOEPCTL7_SNP_MASK 0x100000
+#define GC_USB_DOEPCTL7_SNP_SIZE 0x1
+#define GC_USB_DOEPCTL7_SNP_DEFAULT 0x0
+#define GC_USB_DOEPCTL7_SNP_OFFSET 0xbe0
+#define GC_USB_DOEPCTL7_STALL_LSB 0x15
+#define GC_USB_DOEPCTL7_STALL_MASK 0x200000
+#define GC_USB_DOEPCTL7_STALL_SIZE 0x1
+#define GC_USB_DOEPCTL7_STALL_DEFAULT 0x0
+#define GC_USB_DOEPCTL7_STALL_OFFSET 0xbe0
+#define GC_USB_DOEPCTL7_CNAK_LSB 0x1a
+#define GC_USB_DOEPCTL7_CNAK_MASK 0x4000000
+#define GC_USB_DOEPCTL7_CNAK_SIZE 0x1
+#define GC_USB_DOEPCTL7_CNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL7_CNAK_OFFSET 0xbe0
+#define GC_USB_DOEPCTL7_SNAK_LSB 0x1b
+#define GC_USB_DOEPCTL7_SNAK_MASK 0x8000000
+#define GC_USB_DOEPCTL7_SNAK_SIZE 0x1
+#define GC_USB_DOEPCTL7_SNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL7_SNAK_OFFSET 0xbe0
+#define GC_USB_DOEPCTL7_SETD0PID_LSB 0x1c
+#define GC_USB_DOEPCTL7_SETD0PID_MASK 0x10000000
+#define GC_USB_DOEPCTL7_SETD0PID_SIZE 0x1
+#define GC_USB_DOEPCTL7_SETD0PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL7_SETD0PID_OFFSET 0xbe0
+#define GC_USB_DOEPCTL7_SETD1PID_LSB 0x1d
+#define GC_USB_DOEPCTL7_SETD1PID_MASK 0x20000000
+#define GC_USB_DOEPCTL7_SETD1PID_SIZE 0x1
+#define GC_USB_DOEPCTL7_SETD1PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL7_SETD1PID_OFFSET 0xbe0
+#define GC_USB_DOEPCTL7_EPDIS_LSB 0x1e
+#define GC_USB_DOEPCTL7_EPDIS_MASK 0x40000000
+#define GC_USB_DOEPCTL7_EPDIS_SIZE 0x1
+#define GC_USB_DOEPCTL7_EPDIS_DEFAULT 0x0
+#define GC_USB_DOEPCTL7_EPDIS_OFFSET 0xbe0
+#define GC_USB_DOEPCTL7_EPENA_LSB 0x1f
+#define GC_USB_DOEPCTL7_EPENA_MASK 0x80000000
+#define GC_USB_DOEPCTL7_EPENA_SIZE 0x1
+#define GC_USB_DOEPCTL7_EPENA_DEFAULT 0x0
+#define GC_USB_DOEPCTL7_EPENA_OFFSET 0xbe0
+#define GC_USB_DOEPINT7_XFERCOMPL_LSB 0x0
+#define GC_USB_DOEPINT7_XFERCOMPL_MASK 0x1
+#define GC_USB_DOEPINT7_XFERCOMPL_SIZE 0x1
+#define GC_USB_DOEPINT7_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DOEPINT7_XFERCOMPL_OFFSET 0xbe8
+#define GC_USB_DOEPINT7_EPDISBLD_LSB 0x1
+#define GC_USB_DOEPINT7_EPDISBLD_MASK 0x2
+#define GC_USB_DOEPINT7_EPDISBLD_SIZE 0x1
+#define GC_USB_DOEPINT7_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DOEPINT7_EPDISBLD_OFFSET 0xbe8
+#define GC_USB_DOEPINT7_AHBERR_LSB 0x2
+#define GC_USB_DOEPINT7_AHBERR_MASK 0x4
+#define GC_USB_DOEPINT7_AHBERR_SIZE 0x1
+#define GC_USB_DOEPINT7_AHBERR_DEFAULT 0x0
+#define GC_USB_DOEPINT7_AHBERR_OFFSET 0xbe8
+#define GC_USB_DOEPINT7_SETUP_LSB 0x3
+#define GC_USB_DOEPINT7_SETUP_MASK 0x8
+#define GC_USB_DOEPINT7_SETUP_SIZE 0x1
+#define GC_USB_DOEPINT7_SETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT7_SETUP_OFFSET 0xbe8
+#define GC_USB_DOEPINT7_OUTTKNEPDIS_LSB 0x4
+#define GC_USB_DOEPINT7_OUTTKNEPDIS_MASK 0x10
+#define GC_USB_DOEPINT7_OUTTKNEPDIS_SIZE 0x1
+#define GC_USB_DOEPINT7_OUTTKNEPDIS_DEFAULT 0x0
+#define GC_USB_DOEPINT7_OUTTKNEPDIS_OFFSET 0xbe8
+#define GC_USB_DOEPINT7_STSPHSERCVD_LSB 0x5
+#define GC_USB_DOEPINT7_STSPHSERCVD_MASK 0x20
+#define GC_USB_DOEPINT7_STSPHSERCVD_SIZE 0x1
+#define GC_USB_DOEPINT7_STSPHSERCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT7_STSPHSERCVD_OFFSET 0xbe8
+#define GC_USB_DOEPINT7_BACK2BACKSETUP_LSB 0x6
+#define GC_USB_DOEPINT7_BACK2BACKSETUP_MASK 0x40
+#define GC_USB_DOEPINT7_BACK2BACKSETUP_SIZE 0x1
+#define GC_USB_DOEPINT7_BACK2BACKSETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT7_BACK2BACKSETUP_OFFSET 0xbe8
+#define GC_USB_DOEPINT7_OUTPKTERR_LSB 0x8
+#define GC_USB_DOEPINT7_OUTPKTERR_MASK 0x100
+#define GC_USB_DOEPINT7_OUTPKTERR_SIZE 0x1
+#define GC_USB_DOEPINT7_OUTPKTERR_DEFAULT 0x0
+#define GC_USB_DOEPINT7_OUTPKTERR_OFFSET 0xbe8
+#define GC_USB_DOEPINT7_BNAINTR_LSB 0x9
+#define GC_USB_DOEPINT7_BNAINTR_MASK 0x200
+#define GC_USB_DOEPINT7_BNAINTR_SIZE 0x1
+#define GC_USB_DOEPINT7_BNAINTR_DEFAULT 0x0
+#define GC_USB_DOEPINT7_BNAINTR_OFFSET 0xbe8
+#define GC_USB_DOEPINT7_PKTDRPSTS_LSB 0xb
+#define GC_USB_DOEPINT7_PKTDRPSTS_MASK 0x800
+#define GC_USB_DOEPINT7_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DOEPINT7_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DOEPINT7_PKTDRPSTS_OFFSET 0xbe8
+#define GC_USB_DOEPINT7_BBLEERR_LSB 0xc
+#define GC_USB_DOEPINT7_BBLEERR_MASK 0x1000
+#define GC_USB_DOEPINT7_BBLEERR_SIZE 0x1
+#define GC_USB_DOEPINT7_BBLEERR_DEFAULT 0x0
+#define GC_USB_DOEPINT7_BBLEERR_OFFSET 0xbe8
+#define GC_USB_DOEPINT7_NAKINTRPT_LSB 0xd
+#define GC_USB_DOEPINT7_NAKINTRPT_MASK 0x2000
+#define GC_USB_DOEPINT7_NAKINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT7_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT7_NAKINTRPT_OFFSET 0xbe8
+#define GC_USB_DOEPINT7_NYETINTRPT_LSB 0xe
+#define GC_USB_DOEPINT7_NYETINTRPT_MASK 0x4000
+#define GC_USB_DOEPINT7_NYETINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT7_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT7_NYETINTRPT_OFFSET 0xbe8
+#define GC_USB_DOEPINT7_STUPPKTRCVD_LSB 0xf
+#define GC_USB_DOEPINT7_STUPPKTRCVD_MASK 0x8000
+#define GC_USB_DOEPINT7_STUPPKTRCVD_SIZE 0x1
+#define GC_USB_DOEPINT7_STUPPKTRCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT7_STUPPKTRCVD_OFFSET 0xbe8
+#define GC_USB_DOEPTSIZ7_XFERSIZE_LSB 0x0
+#define GC_USB_DOEPTSIZ7_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DOEPTSIZ7_XFERSIZE_SIZE 0x13
+#define GC_USB_DOEPTSIZ7_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ7_XFERSIZE_OFFSET 0xbf0
+#define GC_USB_DOEPTSIZ7_PKTCNT_LSB 0x13
+#define GC_USB_DOEPTSIZ7_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DOEPTSIZ7_PKTCNT_SIZE 0xa
+#define GC_USB_DOEPTSIZ7_PKTCNT_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ7_PKTCNT_OFFSET 0xbf0
+#define GC_USB_DOEPTSIZ7_RXDPID_LSB 0x1d
+#define GC_USB_DOEPTSIZ7_RXDPID_MASK 0x60000000
+#define GC_USB_DOEPTSIZ7_RXDPID_SIZE 0x2
+#define GC_USB_DOEPTSIZ7_RXDPID_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ7_RXDPID_OFFSET 0xbf0
+#define GC_USB_DOEPDMA7_DMAADDR_LSB 0x0
+#define GC_USB_DOEPDMA7_DMAADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMA7_DMAADDR_SIZE 0x20
+#define GC_USB_DOEPDMA7_DMAADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMA7_DMAADDR_OFFSET 0xbf4
+#define GC_USB_DOEPDMAB7_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DOEPDMAB7_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMAB7_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DOEPDMAB7_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMAB7_DMABUFFERADDR_OFFSET 0xbfc
+#define GC_USB_DOEPCTL8_MPS_LSB 0x0
+#define GC_USB_DOEPCTL8_MPS_MASK 0x7ff
+#define GC_USB_DOEPCTL8_MPS_SIZE 0xb
+#define GC_USB_DOEPCTL8_MPS_DEFAULT 0x0
+#define GC_USB_DOEPCTL8_MPS_OFFSET 0xc00
+#define GC_USB_DOEPCTL8_USBACTEP_LSB 0xf
+#define GC_USB_DOEPCTL8_USBACTEP_MASK 0x8000
+#define GC_USB_DOEPCTL8_USBACTEP_SIZE 0x1
+#define GC_USB_DOEPCTL8_USBACTEP_DEFAULT 0x0
+#define GC_USB_DOEPCTL8_USBACTEP_OFFSET 0xc00
+#define GC_USB_DOEPCTL8_DPID_LSB 0x10
+#define GC_USB_DOEPCTL8_DPID_MASK 0x10000
+#define GC_USB_DOEPCTL8_DPID_SIZE 0x1
+#define GC_USB_DOEPCTL8_DPID_DEFAULT 0x0
+#define GC_USB_DOEPCTL8_DPID_OFFSET 0xc00
+#define GC_USB_DOEPCTL8_NAKSTS_LSB 0x11
+#define GC_USB_DOEPCTL8_NAKSTS_MASK 0x20000
+#define GC_USB_DOEPCTL8_NAKSTS_SIZE 0x1
+#define GC_USB_DOEPCTL8_NAKSTS_DEFAULT 0x0
+#define GC_USB_DOEPCTL8_NAKSTS_OFFSET 0xc00
+#define GC_USB_DOEPCTL8_EPTYPE_LSB 0x12
+#define GC_USB_DOEPCTL8_EPTYPE_MASK 0xc0000
+#define GC_USB_DOEPCTL8_EPTYPE_SIZE 0x2
+#define GC_USB_DOEPCTL8_EPTYPE_DEFAULT 0x0
+#define GC_USB_DOEPCTL8_EPTYPE_OFFSET 0xc00
+#define GC_USB_DOEPCTL8_SNP_LSB 0x14
+#define GC_USB_DOEPCTL8_SNP_MASK 0x100000
+#define GC_USB_DOEPCTL8_SNP_SIZE 0x1
+#define GC_USB_DOEPCTL8_SNP_DEFAULT 0x0
+#define GC_USB_DOEPCTL8_SNP_OFFSET 0xc00
+#define GC_USB_DOEPCTL8_STALL_LSB 0x15
+#define GC_USB_DOEPCTL8_STALL_MASK 0x200000
+#define GC_USB_DOEPCTL8_STALL_SIZE 0x1
+#define GC_USB_DOEPCTL8_STALL_DEFAULT 0x0
+#define GC_USB_DOEPCTL8_STALL_OFFSET 0xc00
+#define GC_USB_DOEPCTL8_CNAK_LSB 0x1a
+#define GC_USB_DOEPCTL8_CNAK_MASK 0x4000000
+#define GC_USB_DOEPCTL8_CNAK_SIZE 0x1
+#define GC_USB_DOEPCTL8_CNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL8_CNAK_OFFSET 0xc00
+#define GC_USB_DOEPCTL8_SNAK_LSB 0x1b
+#define GC_USB_DOEPCTL8_SNAK_MASK 0x8000000
+#define GC_USB_DOEPCTL8_SNAK_SIZE 0x1
+#define GC_USB_DOEPCTL8_SNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL8_SNAK_OFFSET 0xc00
+#define GC_USB_DOEPCTL8_SETD0PID_LSB 0x1c
+#define GC_USB_DOEPCTL8_SETD0PID_MASK 0x10000000
+#define GC_USB_DOEPCTL8_SETD0PID_SIZE 0x1
+#define GC_USB_DOEPCTL8_SETD0PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL8_SETD0PID_OFFSET 0xc00
+#define GC_USB_DOEPCTL8_SETD1PID_LSB 0x1d
+#define GC_USB_DOEPCTL8_SETD1PID_MASK 0x20000000
+#define GC_USB_DOEPCTL8_SETD1PID_SIZE 0x1
+#define GC_USB_DOEPCTL8_SETD1PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL8_SETD1PID_OFFSET 0xc00
+#define GC_USB_DOEPCTL8_EPDIS_LSB 0x1e
+#define GC_USB_DOEPCTL8_EPDIS_MASK 0x40000000
+#define GC_USB_DOEPCTL8_EPDIS_SIZE 0x1
+#define GC_USB_DOEPCTL8_EPDIS_DEFAULT 0x0
+#define GC_USB_DOEPCTL8_EPDIS_OFFSET 0xc00
+#define GC_USB_DOEPCTL8_EPENA_LSB 0x1f
+#define GC_USB_DOEPCTL8_EPENA_MASK 0x80000000
+#define GC_USB_DOEPCTL8_EPENA_SIZE 0x1
+#define GC_USB_DOEPCTL8_EPENA_DEFAULT 0x0
+#define GC_USB_DOEPCTL8_EPENA_OFFSET 0xc00
+#define GC_USB_DOEPINT8_XFERCOMPL_LSB 0x0
+#define GC_USB_DOEPINT8_XFERCOMPL_MASK 0x1
+#define GC_USB_DOEPINT8_XFERCOMPL_SIZE 0x1
+#define GC_USB_DOEPINT8_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DOEPINT8_XFERCOMPL_OFFSET 0xc08
+#define GC_USB_DOEPINT8_EPDISBLD_LSB 0x1
+#define GC_USB_DOEPINT8_EPDISBLD_MASK 0x2
+#define GC_USB_DOEPINT8_EPDISBLD_SIZE 0x1
+#define GC_USB_DOEPINT8_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DOEPINT8_EPDISBLD_OFFSET 0xc08
+#define GC_USB_DOEPINT8_AHBERR_LSB 0x2
+#define GC_USB_DOEPINT8_AHBERR_MASK 0x4
+#define GC_USB_DOEPINT8_AHBERR_SIZE 0x1
+#define GC_USB_DOEPINT8_AHBERR_DEFAULT 0x0
+#define GC_USB_DOEPINT8_AHBERR_OFFSET 0xc08
+#define GC_USB_DOEPINT8_SETUP_LSB 0x3
+#define GC_USB_DOEPINT8_SETUP_MASK 0x8
+#define GC_USB_DOEPINT8_SETUP_SIZE 0x1
+#define GC_USB_DOEPINT8_SETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT8_SETUP_OFFSET 0xc08
+#define GC_USB_DOEPINT8_OUTTKNEPDIS_LSB 0x4
+#define GC_USB_DOEPINT8_OUTTKNEPDIS_MASK 0x10
+#define GC_USB_DOEPINT8_OUTTKNEPDIS_SIZE 0x1
+#define GC_USB_DOEPINT8_OUTTKNEPDIS_DEFAULT 0x0
+#define GC_USB_DOEPINT8_OUTTKNEPDIS_OFFSET 0xc08
+#define GC_USB_DOEPINT8_STSPHSERCVD_LSB 0x5
+#define GC_USB_DOEPINT8_STSPHSERCVD_MASK 0x20
+#define GC_USB_DOEPINT8_STSPHSERCVD_SIZE 0x1
+#define GC_USB_DOEPINT8_STSPHSERCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT8_STSPHSERCVD_OFFSET 0xc08
+#define GC_USB_DOEPINT8_BACK2BACKSETUP_LSB 0x6
+#define GC_USB_DOEPINT8_BACK2BACKSETUP_MASK 0x40
+#define GC_USB_DOEPINT8_BACK2BACKSETUP_SIZE 0x1
+#define GC_USB_DOEPINT8_BACK2BACKSETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT8_BACK2BACKSETUP_OFFSET 0xc08
+#define GC_USB_DOEPINT8_OUTPKTERR_LSB 0x8
+#define GC_USB_DOEPINT8_OUTPKTERR_MASK 0x100
+#define GC_USB_DOEPINT8_OUTPKTERR_SIZE 0x1
+#define GC_USB_DOEPINT8_OUTPKTERR_DEFAULT 0x0
+#define GC_USB_DOEPINT8_OUTPKTERR_OFFSET 0xc08
+#define GC_USB_DOEPINT8_BNAINTR_LSB 0x9
+#define GC_USB_DOEPINT8_BNAINTR_MASK 0x200
+#define GC_USB_DOEPINT8_BNAINTR_SIZE 0x1
+#define GC_USB_DOEPINT8_BNAINTR_DEFAULT 0x0
+#define GC_USB_DOEPINT8_BNAINTR_OFFSET 0xc08
+#define GC_USB_DOEPINT8_PKTDRPSTS_LSB 0xb
+#define GC_USB_DOEPINT8_PKTDRPSTS_MASK 0x800
+#define GC_USB_DOEPINT8_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DOEPINT8_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DOEPINT8_PKTDRPSTS_OFFSET 0xc08
+#define GC_USB_DOEPINT8_BBLEERR_LSB 0xc
+#define GC_USB_DOEPINT8_BBLEERR_MASK 0x1000
+#define GC_USB_DOEPINT8_BBLEERR_SIZE 0x1
+#define GC_USB_DOEPINT8_BBLEERR_DEFAULT 0x0
+#define GC_USB_DOEPINT8_BBLEERR_OFFSET 0xc08
+#define GC_USB_DOEPINT8_NAKINTRPT_LSB 0xd
+#define GC_USB_DOEPINT8_NAKINTRPT_MASK 0x2000
+#define GC_USB_DOEPINT8_NAKINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT8_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT8_NAKINTRPT_OFFSET 0xc08
+#define GC_USB_DOEPINT8_NYETINTRPT_LSB 0xe
+#define GC_USB_DOEPINT8_NYETINTRPT_MASK 0x4000
+#define GC_USB_DOEPINT8_NYETINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT8_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT8_NYETINTRPT_OFFSET 0xc08
+#define GC_USB_DOEPINT8_STUPPKTRCVD_LSB 0xf
+#define GC_USB_DOEPINT8_STUPPKTRCVD_MASK 0x8000
+#define GC_USB_DOEPINT8_STUPPKTRCVD_SIZE 0x1
+#define GC_USB_DOEPINT8_STUPPKTRCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT8_STUPPKTRCVD_OFFSET 0xc08
+#define GC_USB_DOEPTSIZ8_XFERSIZE_LSB 0x0
+#define GC_USB_DOEPTSIZ8_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DOEPTSIZ8_XFERSIZE_SIZE 0x13
+#define GC_USB_DOEPTSIZ8_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ8_XFERSIZE_OFFSET 0xc10
+#define GC_USB_DOEPTSIZ8_PKTCNT_LSB 0x13
+#define GC_USB_DOEPTSIZ8_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DOEPTSIZ8_PKTCNT_SIZE 0xa
+#define GC_USB_DOEPTSIZ8_PKTCNT_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ8_PKTCNT_OFFSET 0xc10
+#define GC_USB_DOEPTSIZ8_RXDPID_LSB 0x1d
+#define GC_USB_DOEPTSIZ8_RXDPID_MASK 0x60000000
+#define GC_USB_DOEPTSIZ8_RXDPID_SIZE 0x2
+#define GC_USB_DOEPTSIZ8_RXDPID_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ8_RXDPID_OFFSET 0xc10
+#define GC_USB_DOEPDMA8_DMAADDR_LSB 0x0
+#define GC_USB_DOEPDMA8_DMAADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMA8_DMAADDR_SIZE 0x20
+#define GC_USB_DOEPDMA8_DMAADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMA8_DMAADDR_OFFSET 0xc14
+#define GC_USB_DOEPDMAB8_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DOEPDMAB8_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMAB8_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DOEPDMAB8_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMAB8_DMABUFFERADDR_OFFSET 0xc1c
+#define GC_USB_DOEPCTL9_MPS_LSB 0x0
+#define GC_USB_DOEPCTL9_MPS_MASK 0x7ff
+#define GC_USB_DOEPCTL9_MPS_SIZE 0xb
+#define GC_USB_DOEPCTL9_MPS_DEFAULT 0x0
+#define GC_USB_DOEPCTL9_MPS_OFFSET 0xc20
+#define GC_USB_DOEPCTL9_USBACTEP_LSB 0xf
+#define GC_USB_DOEPCTL9_USBACTEP_MASK 0x8000
+#define GC_USB_DOEPCTL9_USBACTEP_SIZE 0x1
+#define GC_USB_DOEPCTL9_USBACTEP_DEFAULT 0x0
+#define GC_USB_DOEPCTL9_USBACTEP_OFFSET 0xc20
+#define GC_USB_DOEPCTL9_DPID_LSB 0x10
+#define GC_USB_DOEPCTL9_DPID_MASK 0x10000
+#define GC_USB_DOEPCTL9_DPID_SIZE 0x1
+#define GC_USB_DOEPCTL9_DPID_DEFAULT 0x0
+#define GC_USB_DOEPCTL9_DPID_OFFSET 0xc20
+#define GC_USB_DOEPCTL9_NAKSTS_LSB 0x11
+#define GC_USB_DOEPCTL9_NAKSTS_MASK 0x20000
+#define GC_USB_DOEPCTL9_NAKSTS_SIZE 0x1
+#define GC_USB_DOEPCTL9_NAKSTS_DEFAULT 0x0
+#define GC_USB_DOEPCTL9_NAKSTS_OFFSET 0xc20
+#define GC_USB_DOEPCTL9_EPTYPE_LSB 0x12
+#define GC_USB_DOEPCTL9_EPTYPE_MASK 0xc0000
+#define GC_USB_DOEPCTL9_EPTYPE_SIZE 0x2
+#define GC_USB_DOEPCTL9_EPTYPE_DEFAULT 0x0
+#define GC_USB_DOEPCTL9_EPTYPE_OFFSET 0xc20
+#define GC_USB_DOEPCTL9_SNP_LSB 0x14
+#define GC_USB_DOEPCTL9_SNP_MASK 0x100000
+#define GC_USB_DOEPCTL9_SNP_SIZE 0x1
+#define GC_USB_DOEPCTL9_SNP_DEFAULT 0x0
+#define GC_USB_DOEPCTL9_SNP_OFFSET 0xc20
+#define GC_USB_DOEPCTL9_STALL_LSB 0x15
+#define GC_USB_DOEPCTL9_STALL_MASK 0x200000
+#define GC_USB_DOEPCTL9_STALL_SIZE 0x1
+#define GC_USB_DOEPCTL9_STALL_DEFAULT 0x0
+#define GC_USB_DOEPCTL9_STALL_OFFSET 0xc20
+#define GC_USB_DOEPCTL9_CNAK_LSB 0x1a
+#define GC_USB_DOEPCTL9_CNAK_MASK 0x4000000
+#define GC_USB_DOEPCTL9_CNAK_SIZE 0x1
+#define GC_USB_DOEPCTL9_CNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL9_CNAK_OFFSET 0xc20
+#define GC_USB_DOEPCTL9_SNAK_LSB 0x1b
+#define GC_USB_DOEPCTL9_SNAK_MASK 0x8000000
+#define GC_USB_DOEPCTL9_SNAK_SIZE 0x1
+#define GC_USB_DOEPCTL9_SNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL9_SNAK_OFFSET 0xc20
+#define GC_USB_DOEPCTL9_SETD0PID_LSB 0x1c
+#define GC_USB_DOEPCTL9_SETD0PID_MASK 0x10000000
+#define GC_USB_DOEPCTL9_SETD0PID_SIZE 0x1
+#define GC_USB_DOEPCTL9_SETD0PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL9_SETD0PID_OFFSET 0xc20
+#define GC_USB_DOEPCTL9_SETD1PID_LSB 0x1d
+#define GC_USB_DOEPCTL9_SETD1PID_MASK 0x20000000
+#define GC_USB_DOEPCTL9_SETD1PID_SIZE 0x1
+#define GC_USB_DOEPCTL9_SETD1PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL9_SETD1PID_OFFSET 0xc20
+#define GC_USB_DOEPCTL9_EPDIS_LSB 0x1e
+#define GC_USB_DOEPCTL9_EPDIS_MASK 0x40000000
+#define GC_USB_DOEPCTL9_EPDIS_SIZE 0x1
+#define GC_USB_DOEPCTL9_EPDIS_DEFAULT 0x0
+#define GC_USB_DOEPCTL9_EPDIS_OFFSET 0xc20
+#define GC_USB_DOEPCTL9_EPENA_LSB 0x1f
+#define GC_USB_DOEPCTL9_EPENA_MASK 0x80000000
+#define GC_USB_DOEPCTL9_EPENA_SIZE 0x1
+#define GC_USB_DOEPCTL9_EPENA_DEFAULT 0x0
+#define GC_USB_DOEPCTL9_EPENA_OFFSET 0xc20
+#define GC_USB_DOEPINT9_XFERCOMPL_LSB 0x0
+#define GC_USB_DOEPINT9_XFERCOMPL_MASK 0x1
+#define GC_USB_DOEPINT9_XFERCOMPL_SIZE 0x1
+#define GC_USB_DOEPINT9_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DOEPINT9_XFERCOMPL_OFFSET 0xc28
+#define GC_USB_DOEPINT9_EPDISBLD_LSB 0x1
+#define GC_USB_DOEPINT9_EPDISBLD_MASK 0x2
+#define GC_USB_DOEPINT9_EPDISBLD_SIZE 0x1
+#define GC_USB_DOEPINT9_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DOEPINT9_EPDISBLD_OFFSET 0xc28
+#define GC_USB_DOEPINT9_AHBERR_LSB 0x2
+#define GC_USB_DOEPINT9_AHBERR_MASK 0x4
+#define GC_USB_DOEPINT9_AHBERR_SIZE 0x1
+#define GC_USB_DOEPINT9_AHBERR_DEFAULT 0x0
+#define GC_USB_DOEPINT9_AHBERR_OFFSET 0xc28
+#define GC_USB_DOEPINT9_SETUP_LSB 0x3
+#define GC_USB_DOEPINT9_SETUP_MASK 0x8
+#define GC_USB_DOEPINT9_SETUP_SIZE 0x1
+#define GC_USB_DOEPINT9_SETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT9_SETUP_OFFSET 0xc28
+#define GC_USB_DOEPINT9_OUTTKNEPDIS_LSB 0x4
+#define GC_USB_DOEPINT9_OUTTKNEPDIS_MASK 0x10
+#define GC_USB_DOEPINT9_OUTTKNEPDIS_SIZE 0x1
+#define GC_USB_DOEPINT9_OUTTKNEPDIS_DEFAULT 0x0
+#define GC_USB_DOEPINT9_OUTTKNEPDIS_OFFSET 0xc28
+#define GC_USB_DOEPINT9_STSPHSERCVD_LSB 0x5
+#define GC_USB_DOEPINT9_STSPHSERCVD_MASK 0x20
+#define GC_USB_DOEPINT9_STSPHSERCVD_SIZE 0x1
+#define GC_USB_DOEPINT9_STSPHSERCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT9_STSPHSERCVD_OFFSET 0xc28
+#define GC_USB_DOEPINT9_BACK2BACKSETUP_LSB 0x6
+#define GC_USB_DOEPINT9_BACK2BACKSETUP_MASK 0x40
+#define GC_USB_DOEPINT9_BACK2BACKSETUP_SIZE 0x1
+#define GC_USB_DOEPINT9_BACK2BACKSETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT9_BACK2BACKSETUP_OFFSET 0xc28
+#define GC_USB_DOEPINT9_OUTPKTERR_LSB 0x8
+#define GC_USB_DOEPINT9_OUTPKTERR_MASK 0x100
+#define GC_USB_DOEPINT9_OUTPKTERR_SIZE 0x1
+#define GC_USB_DOEPINT9_OUTPKTERR_DEFAULT 0x0
+#define GC_USB_DOEPINT9_OUTPKTERR_OFFSET 0xc28
+#define GC_USB_DOEPINT9_BNAINTR_LSB 0x9
+#define GC_USB_DOEPINT9_BNAINTR_MASK 0x200
+#define GC_USB_DOEPINT9_BNAINTR_SIZE 0x1
+#define GC_USB_DOEPINT9_BNAINTR_DEFAULT 0x0
+#define GC_USB_DOEPINT9_BNAINTR_OFFSET 0xc28
+#define GC_USB_DOEPINT9_PKTDRPSTS_LSB 0xb
+#define GC_USB_DOEPINT9_PKTDRPSTS_MASK 0x800
+#define GC_USB_DOEPINT9_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DOEPINT9_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DOEPINT9_PKTDRPSTS_OFFSET 0xc28
+#define GC_USB_DOEPINT9_BBLEERR_LSB 0xc
+#define GC_USB_DOEPINT9_BBLEERR_MASK 0x1000
+#define GC_USB_DOEPINT9_BBLEERR_SIZE 0x1
+#define GC_USB_DOEPINT9_BBLEERR_DEFAULT 0x0
+#define GC_USB_DOEPINT9_BBLEERR_OFFSET 0xc28
+#define GC_USB_DOEPINT9_NAKINTRPT_LSB 0xd
+#define GC_USB_DOEPINT9_NAKINTRPT_MASK 0x2000
+#define GC_USB_DOEPINT9_NAKINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT9_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT9_NAKINTRPT_OFFSET 0xc28
+#define GC_USB_DOEPINT9_NYETINTRPT_LSB 0xe
+#define GC_USB_DOEPINT9_NYETINTRPT_MASK 0x4000
+#define GC_USB_DOEPINT9_NYETINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT9_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT9_NYETINTRPT_OFFSET 0xc28
+#define GC_USB_DOEPINT9_STUPPKTRCVD_LSB 0xf
+#define GC_USB_DOEPINT9_STUPPKTRCVD_MASK 0x8000
+#define GC_USB_DOEPINT9_STUPPKTRCVD_SIZE 0x1
+#define GC_USB_DOEPINT9_STUPPKTRCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT9_STUPPKTRCVD_OFFSET 0xc28
+#define GC_USB_DOEPTSIZ9_XFERSIZE_LSB 0x0
+#define GC_USB_DOEPTSIZ9_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DOEPTSIZ9_XFERSIZE_SIZE 0x13
+#define GC_USB_DOEPTSIZ9_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ9_XFERSIZE_OFFSET 0xc30
+#define GC_USB_DOEPTSIZ9_PKTCNT_LSB 0x13
+#define GC_USB_DOEPTSIZ9_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DOEPTSIZ9_PKTCNT_SIZE 0xa
+#define GC_USB_DOEPTSIZ9_PKTCNT_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ9_PKTCNT_OFFSET 0xc30
+#define GC_USB_DOEPTSIZ9_RXDPID_LSB 0x1d
+#define GC_USB_DOEPTSIZ9_RXDPID_MASK 0x60000000
+#define GC_USB_DOEPTSIZ9_RXDPID_SIZE 0x2
+#define GC_USB_DOEPTSIZ9_RXDPID_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ9_RXDPID_OFFSET 0xc30
+#define GC_USB_DOEPDMA9_DMAADDR_LSB 0x0
+#define GC_USB_DOEPDMA9_DMAADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMA9_DMAADDR_SIZE 0x20
+#define GC_USB_DOEPDMA9_DMAADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMA9_DMAADDR_OFFSET 0xc34
+#define GC_USB_DOEPDMAB9_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DOEPDMAB9_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMAB9_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DOEPDMAB9_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMAB9_DMABUFFERADDR_OFFSET 0xc3c
+#define GC_USB_DOEPCTL10_MPS_LSB 0x0
+#define GC_USB_DOEPCTL10_MPS_MASK 0x7ff
+#define GC_USB_DOEPCTL10_MPS_SIZE 0xb
+#define GC_USB_DOEPCTL10_MPS_DEFAULT 0x0
+#define GC_USB_DOEPCTL10_MPS_OFFSET 0xc40
+#define GC_USB_DOEPCTL10_USBACTEP_LSB 0xf
+#define GC_USB_DOEPCTL10_USBACTEP_MASK 0x8000
+#define GC_USB_DOEPCTL10_USBACTEP_SIZE 0x1
+#define GC_USB_DOEPCTL10_USBACTEP_DEFAULT 0x0
+#define GC_USB_DOEPCTL10_USBACTEP_OFFSET 0xc40
+#define GC_USB_DOEPCTL10_DPID_LSB 0x10
+#define GC_USB_DOEPCTL10_DPID_MASK 0x10000
+#define GC_USB_DOEPCTL10_DPID_SIZE 0x1
+#define GC_USB_DOEPCTL10_DPID_DEFAULT 0x0
+#define GC_USB_DOEPCTL10_DPID_OFFSET 0xc40
+#define GC_USB_DOEPCTL10_NAKSTS_LSB 0x11
+#define GC_USB_DOEPCTL10_NAKSTS_MASK 0x20000
+#define GC_USB_DOEPCTL10_NAKSTS_SIZE 0x1
+#define GC_USB_DOEPCTL10_NAKSTS_DEFAULT 0x0
+#define GC_USB_DOEPCTL10_NAKSTS_OFFSET 0xc40
+#define GC_USB_DOEPCTL10_EPTYPE_LSB 0x12
+#define GC_USB_DOEPCTL10_EPTYPE_MASK 0xc0000
+#define GC_USB_DOEPCTL10_EPTYPE_SIZE 0x2
+#define GC_USB_DOEPCTL10_EPTYPE_DEFAULT 0x0
+#define GC_USB_DOEPCTL10_EPTYPE_OFFSET 0xc40
+#define GC_USB_DOEPCTL10_SNP_LSB 0x14
+#define GC_USB_DOEPCTL10_SNP_MASK 0x100000
+#define GC_USB_DOEPCTL10_SNP_SIZE 0x1
+#define GC_USB_DOEPCTL10_SNP_DEFAULT 0x0
+#define GC_USB_DOEPCTL10_SNP_OFFSET 0xc40
+#define GC_USB_DOEPCTL10_STALL_LSB 0x15
+#define GC_USB_DOEPCTL10_STALL_MASK 0x200000
+#define GC_USB_DOEPCTL10_STALL_SIZE 0x1
+#define GC_USB_DOEPCTL10_STALL_DEFAULT 0x0
+#define GC_USB_DOEPCTL10_STALL_OFFSET 0xc40
+#define GC_USB_DOEPCTL10_CNAK_LSB 0x1a
+#define GC_USB_DOEPCTL10_CNAK_MASK 0x4000000
+#define GC_USB_DOEPCTL10_CNAK_SIZE 0x1
+#define GC_USB_DOEPCTL10_CNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL10_CNAK_OFFSET 0xc40
+#define GC_USB_DOEPCTL10_SNAK_LSB 0x1b
+#define GC_USB_DOEPCTL10_SNAK_MASK 0x8000000
+#define GC_USB_DOEPCTL10_SNAK_SIZE 0x1
+#define GC_USB_DOEPCTL10_SNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL10_SNAK_OFFSET 0xc40
+#define GC_USB_DOEPCTL10_SETD0PID_LSB 0x1c
+#define GC_USB_DOEPCTL10_SETD0PID_MASK 0x10000000
+#define GC_USB_DOEPCTL10_SETD0PID_SIZE 0x1
+#define GC_USB_DOEPCTL10_SETD0PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL10_SETD0PID_OFFSET 0xc40
+#define GC_USB_DOEPCTL10_SETD1PID_LSB 0x1d
+#define GC_USB_DOEPCTL10_SETD1PID_MASK 0x20000000
+#define GC_USB_DOEPCTL10_SETD1PID_SIZE 0x1
+#define GC_USB_DOEPCTL10_SETD1PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL10_SETD1PID_OFFSET 0xc40
+#define GC_USB_DOEPCTL10_EPDIS_LSB 0x1e
+#define GC_USB_DOEPCTL10_EPDIS_MASK 0x40000000
+#define GC_USB_DOEPCTL10_EPDIS_SIZE 0x1
+#define GC_USB_DOEPCTL10_EPDIS_DEFAULT 0x0
+#define GC_USB_DOEPCTL10_EPDIS_OFFSET 0xc40
+#define GC_USB_DOEPCTL10_EPENA_LSB 0x1f
+#define GC_USB_DOEPCTL10_EPENA_MASK 0x80000000
+#define GC_USB_DOEPCTL10_EPENA_SIZE 0x1
+#define GC_USB_DOEPCTL10_EPENA_DEFAULT 0x0
+#define GC_USB_DOEPCTL10_EPENA_OFFSET 0xc40
+#define GC_USB_DOEPINT10_XFERCOMPL_LSB 0x0
+#define GC_USB_DOEPINT10_XFERCOMPL_MASK 0x1
+#define GC_USB_DOEPINT10_XFERCOMPL_SIZE 0x1
+#define GC_USB_DOEPINT10_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DOEPINT10_XFERCOMPL_OFFSET 0xc48
+#define GC_USB_DOEPINT10_EPDISBLD_LSB 0x1
+#define GC_USB_DOEPINT10_EPDISBLD_MASK 0x2
+#define GC_USB_DOEPINT10_EPDISBLD_SIZE 0x1
+#define GC_USB_DOEPINT10_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DOEPINT10_EPDISBLD_OFFSET 0xc48
+#define GC_USB_DOEPINT10_AHBERR_LSB 0x2
+#define GC_USB_DOEPINT10_AHBERR_MASK 0x4
+#define GC_USB_DOEPINT10_AHBERR_SIZE 0x1
+#define GC_USB_DOEPINT10_AHBERR_DEFAULT 0x0
+#define GC_USB_DOEPINT10_AHBERR_OFFSET 0xc48
+#define GC_USB_DOEPINT10_SETUP_LSB 0x3
+#define GC_USB_DOEPINT10_SETUP_MASK 0x8
+#define GC_USB_DOEPINT10_SETUP_SIZE 0x1
+#define GC_USB_DOEPINT10_SETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT10_SETUP_OFFSET 0xc48
+#define GC_USB_DOEPINT10_OUTTKNEPDIS_LSB 0x4
+#define GC_USB_DOEPINT10_OUTTKNEPDIS_MASK 0x10
+#define GC_USB_DOEPINT10_OUTTKNEPDIS_SIZE 0x1
+#define GC_USB_DOEPINT10_OUTTKNEPDIS_DEFAULT 0x0
+#define GC_USB_DOEPINT10_OUTTKNEPDIS_OFFSET 0xc48
+#define GC_USB_DOEPINT10_STSPHSERCVD_LSB 0x5
+#define GC_USB_DOEPINT10_STSPHSERCVD_MASK 0x20
+#define GC_USB_DOEPINT10_STSPHSERCVD_SIZE 0x1
+#define GC_USB_DOEPINT10_STSPHSERCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT10_STSPHSERCVD_OFFSET 0xc48
+#define GC_USB_DOEPINT10_BACK2BACKSETUP_LSB 0x6
+#define GC_USB_DOEPINT10_BACK2BACKSETUP_MASK 0x40
+#define GC_USB_DOEPINT10_BACK2BACKSETUP_SIZE 0x1
+#define GC_USB_DOEPINT10_BACK2BACKSETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT10_BACK2BACKSETUP_OFFSET 0xc48
+#define GC_USB_DOEPINT10_OUTPKTERR_LSB 0x8
+#define GC_USB_DOEPINT10_OUTPKTERR_MASK 0x100
+#define GC_USB_DOEPINT10_OUTPKTERR_SIZE 0x1
+#define GC_USB_DOEPINT10_OUTPKTERR_DEFAULT 0x0
+#define GC_USB_DOEPINT10_OUTPKTERR_OFFSET 0xc48
+#define GC_USB_DOEPINT10_BNAINTR_LSB 0x9
+#define GC_USB_DOEPINT10_BNAINTR_MASK 0x200
+#define GC_USB_DOEPINT10_BNAINTR_SIZE 0x1
+#define GC_USB_DOEPINT10_BNAINTR_DEFAULT 0x0
+#define GC_USB_DOEPINT10_BNAINTR_OFFSET 0xc48
+#define GC_USB_DOEPINT10_PKTDRPSTS_LSB 0xb
+#define GC_USB_DOEPINT10_PKTDRPSTS_MASK 0x800
+#define GC_USB_DOEPINT10_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DOEPINT10_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DOEPINT10_PKTDRPSTS_OFFSET 0xc48
+#define GC_USB_DOEPINT10_BBLEERR_LSB 0xc
+#define GC_USB_DOEPINT10_BBLEERR_MASK 0x1000
+#define GC_USB_DOEPINT10_BBLEERR_SIZE 0x1
+#define GC_USB_DOEPINT10_BBLEERR_DEFAULT 0x0
+#define GC_USB_DOEPINT10_BBLEERR_OFFSET 0xc48
+#define GC_USB_DOEPINT10_NAKINTRPT_LSB 0xd
+#define GC_USB_DOEPINT10_NAKINTRPT_MASK 0x2000
+#define GC_USB_DOEPINT10_NAKINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT10_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT10_NAKINTRPT_OFFSET 0xc48
+#define GC_USB_DOEPINT10_NYETINTRPT_LSB 0xe
+#define GC_USB_DOEPINT10_NYETINTRPT_MASK 0x4000
+#define GC_USB_DOEPINT10_NYETINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT10_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT10_NYETINTRPT_OFFSET 0xc48
+#define GC_USB_DOEPINT10_STUPPKTRCVD_LSB 0xf
+#define GC_USB_DOEPINT10_STUPPKTRCVD_MASK 0x8000
+#define GC_USB_DOEPINT10_STUPPKTRCVD_SIZE 0x1
+#define GC_USB_DOEPINT10_STUPPKTRCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT10_STUPPKTRCVD_OFFSET 0xc48
+#define GC_USB_DOEPTSIZ10_XFERSIZE_LSB 0x0
+#define GC_USB_DOEPTSIZ10_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DOEPTSIZ10_XFERSIZE_SIZE 0x13
+#define GC_USB_DOEPTSIZ10_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ10_XFERSIZE_OFFSET 0xc50
+#define GC_USB_DOEPTSIZ10_PKTCNT_LSB 0x13
+#define GC_USB_DOEPTSIZ10_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DOEPTSIZ10_PKTCNT_SIZE 0xa
+#define GC_USB_DOEPTSIZ10_PKTCNT_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ10_PKTCNT_OFFSET 0xc50
+#define GC_USB_DOEPTSIZ10_RXDPID_LSB 0x1d
+#define GC_USB_DOEPTSIZ10_RXDPID_MASK 0x60000000
+#define GC_USB_DOEPTSIZ10_RXDPID_SIZE 0x2
+#define GC_USB_DOEPTSIZ10_RXDPID_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ10_RXDPID_OFFSET 0xc50
+#define GC_USB_DOEPDMA10_DMAADDR_LSB 0x0
+#define GC_USB_DOEPDMA10_DMAADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMA10_DMAADDR_SIZE 0x20
+#define GC_USB_DOEPDMA10_DMAADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMA10_DMAADDR_OFFSET 0xc54
+#define GC_USB_DOEPDMAB10_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DOEPDMAB10_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMAB10_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DOEPDMAB10_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMAB10_DMABUFFERADDR_OFFSET 0xc5c
+#define GC_USB_DOEPCTL11_MPS_LSB 0x0
+#define GC_USB_DOEPCTL11_MPS_MASK 0x7ff
+#define GC_USB_DOEPCTL11_MPS_SIZE 0xb
+#define GC_USB_DOEPCTL11_MPS_DEFAULT 0x0
+#define GC_USB_DOEPCTL11_MPS_OFFSET 0xc60
+#define GC_USB_DOEPCTL11_USBACTEP_LSB 0xf
+#define GC_USB_DOEPCTL11_USBACTEP_MASK 0x8000
+#define GC_USB_DOEPCTL11_USBACTEP_SIZE 0x1
+#define GC_USB_DOEPCTL11_USBACTEP_DEFAULT 0x0
+#define GC_USB_DOEPCTL11_USBACTEP_OFFSET 0xc60
+#define GC_USB_DOEPCTL11_DPID_LSB 0x10
+#define GC_USB_DOEPCTL11_DPID_MASK 0x10000
+#define GC_USB_DOEPCTL11_DPID_SIZE 0x1
+#define GC_USB_DOEPCTL11_DPID_DEFAULT 0x0
+#define GC_USB_DOEPCTL11_DPID_OFFSET 0xc60
+#define GC_USB_DOEPCTL11_NAKSTS_LSB 0x11
+#define GC_USB_DOEPCTL11_NAKSTS_MASK 0x20000
+#define GC_USB_DOEPCTL11_NAKSTS_SIZE 0x1
+#define GC_USB_DOEPCTL11_NAKSTS_DEFAULT 0x0
+#define GC_USB_DOEPCTL11_NAKSTS_OFFSET 0xc60
+#define GC_USB_DOEPCTL11_EPTYPE_LSB 0x12
+#define GC_USB_DOEPCTL11_EPTYPE_MASK 0xc0000
+#define GC_USB_DOEPCTL11_EPTYPE_SIZE 0x2
+#define GC_USB_DOEPCTL11_EPTYPE_DEFAULT 0x0
+#define GC_USB_DOEPCTL11_EPTYPE_OFFSET 0xc60
+#define GC_USB_DOEPCTL11_SNP_LSB 0x14
+#define GC_USB_DOEPCTL11_SNP_MASK 0x100000
+#define GC_USB_DOEPCTL11_SNP_SIZE 0x1
+#define GC_USB_DOEPCTL11_SNP_DEFAULT 0x0
+#define GC_USB_DOEPCTL11_SNP_OFFSET 0xc60
+#define GC_USB_DOEPCTL11_STALL_LSB 0x15
+#define GC_USB_DOEPCTL11_STALL_MASK 0x200000
+#define GC_USB_DOEPCTL11_STALL_SIZE 0x1
+#define GC_USB_DOEPCTL11_STALL_DEFAULT 0x0
+#define GC_USB_DOEPCTL11_STALL_OFFSET 0xc60
+#define GC_USB_DOEPCTL11_CNAK_LSB 0x1a
+#define GC_USB_DOEPCTL11_CNAK_MASK 0x4000000
+#define GC_USB_DOEPCTL11_CNAK_SIZE 0x1
+#define GC_USB_DOEPCTL11_CNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL11_CNAK_OFFSET 0xc60
+#define GC_USB_DOEPCTL11_SNAK_LSB 0x1b
+#define GC_USB_DOEPCTL11_SNAK_MASK 0x8000000
+#define GC_USB_DOEPCTL11_SNAK_SIZE 0x1
+#define GC_USB_DOEPCTL11_SNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL11_SNAK_OFFSET 0xc60
+#define GC_USB_DOEPCTL11_SETD0PID_LSB 0x1c
+#define GC_USB_DOEPCTL11_SETD0PID_MASK 0x10000000
+#define GC_USB_DOEPCTL11_SETD0PID_SIZE 0x1
+#define GC_USB_DOEPCTL11_SETD0PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL11_SETD0PID_OFFSET 0xc60
+#define GC_USB_DOEPCTL11_SETD1PID_LSB 0x1d
+#define GC_USB_DOEPCTL11_SETD1PID_MASK 0x20000000
+#define GC_USB_DOEPCTL11_SETD1PID_SIZE 0x1
+#define GC_USB_DOEPCTL11_SETD1PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL11_SETD1PID_OFFSET 0xc60
+#define GC_USB_DOEPCTL11_EPDIS_LSB 0x1e
+#define GC_USB_DOEPCTL11_EPDIS_MASK 0x40000000
+#define GC_USB_DOEPCTL11_EPDIS_SIZE 0x1
+#define GC_USB_DOEPCTL11_EPDIS_DEFAULT 0x0
+#define GC_USB_DOEPCTL11_EPDIS_OFFSET 0xc60
+#define GC_USB_DOEPCTL11_EPENA_LSB 0x1f
+#define GC_USB_DOEPCTL11_EPENA_MASK 0x80000000
+#define GC_USB_DOEPCTL11_EPENA_SIZE 0x1
+#define GC_USB_DOEPCTL11_EPENA_DEFAULT 0x0
+#define GC_USB_DOEPCTL11_EPENA_OFFSET 0xc60
+#define GC_USB_DOEPINT11_XFERCOMPL_LSB 0x0
+#define GC_USB_DOEPINT11_XFERCOMPL_MASK 0x1
+#define GC_USB_DOEPINT11_XFERCOMPL_SIZE 0x1
+#define GC_USB_DOEPINT11_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DOEPINT11_XFERCOMPL_OFFSET 0xc68
+#define GC_USB_DOEPINT11_EPDISBLD_LSB 0x1
+#define GC_USB_DOEPINT11_EPDISBLD_MASK 0x2
+#define GC_USB_DOEPINT11_EPDISBLD_SIZE 0x1
+#define GC_USB_DOEPINT11_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DOEPINT11_EPDISBLD_OFFSET 0xc68
+#define GC_USB_DOEPINT11_AHBERR_LSB 0x2
+#define GC_USB_DOEPINT11_AHBERR_MASK 0x4
+#define GC_USB_DOEPINT11_AHBERR_SIZE 0x1
+#define GC_USB_DOEPINT11_AHBERR_DEFAULT 0x0
+#define GC_USB_DOEPINT11_AHBERR_OFFSET 0xc68
+#define GC_USB_DOEPINT11_SETUP_LSB 0x3
+#define GC_USB_DOEPINT11_SETUP_MASK 0x8
+#define GC_USB_DOEPINT11_SETUP_SIZE 0x1
+#define GC_USB_DOEPINT11_SETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT11_SETUP_OFFSET 0xc68
+#define GC_USB_DOEPINT11_OUTTKNEPDIS_LSB 0x4
+#define GC_USB_DOEPINT11_OUTTKNEPDIS_MASK 0x10
+#define GC_USB_DOEPINT11_OUTTKNEPDIS_SIZE 0x1
+#define GC_USB_DOEPINT11_OUTTKNEPDIS_DEFAULT 0x0
+#define GC_USB_DOEPINT11_OUTTKNEPDIS_OFFSET 0xc68
+#define GC_USB_DOEPINT11_STSPHSERCVD_LSB 0x5
+#define GC_USB_DOEPINT11_STSPHSERCVD_MASK 0x20
+#define GC_USB_DOEPINT11_STSPHSERCVD_SIZE 0x1
+#define GC_USB_DOEPINT11_STSPHSERCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT11_STSPHSERCVD_OFFSET 0xc68
+#define GC_USB_DOEPINT11_BACK2BACKSETUP_LSB 0x6
+#define GC_USB_DOEPINT11_BACK2BACKSETUP_MASK 0x40
+#define GC_USB_DOEPINT11_BACK2BACKSETUP_SIZE 0x1
+#define GC_USB_DOEPINT11_BACK2BACKSETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT11_BACK2BACKSETUP_OFFSET 0xc68
+#define GC_USB_DOEPINT11_OUTPKTERR_LSB 0x8
+#define GC_USB_DOEPINT11_OUTPKTERR_MASK 0x100
+#define GC_USB_DOEPINT11_OUTPKTERR_SIZE 0x1
+#define GC_USB_DOEPINT11_OUTPKTERR_DEFAULT 0x0
+#define GC_USB_DOEPINT11_OUTPKTERR_OFFSET 0xc68
+#define GC_USB_DOEPINT11_BNAINTR_LSB 0x9
+#define GC_USB_DOEPINT11_BNAINTR_MASK 0x200
+#define GC_USB_DOEPINT11_BNAINTR_SIZE 0x1
+#define GC_USB_DOEPINT11_BNAINTR_DEFAULT 0x0
+#define GC_USB_DOEPINT11_BNAINTR_OFFSET 0xc68
+#define GC_USB_DOEPINT11_PKTDRPSTS_LSB 0xb
+#define GC_USB_DOEPINT11_PKTDRPSTS_MASK 0x800
+#define GC_USB_DOEPINT11_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DOEPINT11_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DOEPINT11_PKTDRPSTS_OFFSET 0xc68
+#define GC_USB_DOEPINT11_BBLEERR_LSB 0xc
+#define GC_USB_DOEPINT11_BBLEERR_MASK 0x1000
+#define GC_USB_DOEPINT11_BBLEERR_SIZE 0x1
+#define GC_USB_DOEPINT11_BBLEERR_DEFAULT 0x0
+#define GC_USB_DOEPINT11_BBLEERR_OFFSET 0xc68
+#define GC_USB_DOEPINT11_NAKINTRPT_LSB 0xd
+#define GC_USB_DOEPINT11_NAKINTRPT_MASK 0x2000
+#define GC_USB_DOEPINT11_NAKINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT11_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT11_NAKINTRPT_OFFSET 0xc68
+#define GC_USB_DOEPINT11_NYETINTRPT_LSB 0xe
+#define GC_USB_DOEPINT11_NYETINTRPT_MASK 0x4000
+#define GC_USB_DOEPINT11_NYETINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT11_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT11_NYETINTRPT_OFFSET 0xc68
+#define GC_USB_DOEPINT11_STUPPKTRCVD_LSB 0xf
+#define GC_USB_DOEPINT11_STUPPKTRCVD_MASK 0x8000
+#define GC_USB_DOEPINT11_STUPPKTRCVD_SIZE 0x1
+#define GC_USB_DOEPINT11_STUPPKTRCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT11_STUPPKTRCVD_OFFSET 0xc68
+#define GC_USB_DOEPTSIZ11_XFERSIZE_LSB 0x0
+#define GC_USB_DOEPTSIZ11_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DOEPTSIZ11_XFERSIZE_SIZE 0x13
+#define GC_USB_DOEPTSIZ11_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ11_XFERSIZE_OFFSET 0xc70
+#define GC_USB_DOEPTSIZ11_PKTCNT_LSB 0x13
+#define GC_USB_DOEPTSIZ11_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DOEPTSIZ11_PKTCNT_SIZE 0xa
+#define GC_USB_DOEPTSIZ11_PKTCNT_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ11_PKTCNT_OFFSET 0xc70
+#define GC_USB_DOEPTSIZ11_RXDPID_LSB 0x1d
+#define GC_USB_DOEPTSIZ11_RXDPID_MASK 0x60000000
+#define GC_USB_DOEPTSIZ11_RXDPID_SIZE 0x2
+#define GC_USB_DOEPTSIZ11_RXDPID_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ11_RXDPID_OFFSET 0xc70
+#define GC_USB_DOEPDMA11_DMAADDR_LSB 0x0
+#define GC_USB_DOEPDMA11_DMAADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMA11_DMAADDR_SIZE 0x20
+#define GC_USB_DOEPDMA11_DMAADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMA11_DMAADDR_OFFSET 0xc74
+#define GC_USB_DOEPDMAB11_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DOEPDMAB11_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMAB11_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DOEPDMAB11_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMAB11_DMABUFFERADDR_OFFSET 0xc7c
+#define GC_USB_DOEPCTL12_MPS_LSB 0x0
+#define GC_USB_DOEPCTL12_MPS_MASK 0x7ff
+#define GC_USB_DOEPCTL12_MPS_SIZE 0xb
+#define GC_USB_DOEPCTL12_MPS_DEFAULT 0x0
+#define GC_USB_DOEPCTL12_MPS_OFFSET 0xc80
+#define GC_USB_DOEPCTL12_USBACTEP_LSB 0xf
+#define GC_USB_DOEPCTL12_USBACTEP_MASK 0x8000
+#define GC_USB_DOEPCTL12_USBACTEP_SIZE 0x1
+#define GC_USB_DOEPCTL12_USBACTEP_DEFAULT 0x0
+#define GC_USB_DOEPCTL12_USBACTEP_OFFSET 0xc80
+#define GC_USB_DOEPCTL12_DPID_LSB 0x10
+#define GC_USB_DOEPCTL12_DPID_MASK 0x10000
+#define GC_USB_DOEPCTL12_DPID_SIZE 0x1
+#define GC_USB_DOEPCTL12_DPID_DEFAULT 0x0
+#define GC_USB_DOEPCTL12_DPID_OFFSET 0xc80
+#define GC_USB_DOEPCTL12_NAKSTS_LSB 0x11
+#define GC_USB_DOEPCTL12_NAKSTS_MASK 0x20000
+#define GC_USB_DOEPCTL12_NAKSTS_SIZE 0x1
+#define GC_USB_DOEPCTL12_NAKSTS_DEFAULT 0x0
+#define GC_USB_DOEPCTL12_NAKSTS_OFFSET 0xc80
+#define GC_USB_DOEPCTL12_EPTYPE_LSB 0x12
+#define GC_USB_DOEPCTL12_EPTYPE_MASK 0xc0000
+#define GC_USB_DOEPCTL12_EPTYPE_SIZE 0x2
+#define GC_USB_DOEPCTL12_EPTYPE_DEFAULT 0x0
+#define GC_USB_DOEPCTL12_EPTYPE_OFFSET 0xc80
+#define GC_USB_DOEPCTL12_SNP_LSB 0x14
+#define GC_USB_DOEPCTL12_SNP_MASK 0x100000
+#define GC_USB_DOEPCTL12_SNP_SIZE 0x1
+#define GC_USB_DOEPCTL12_SNP_DEFAULT 0x0
+#define GC_USB_DOEPCTL12_SNP_OFFSET 0xc80
+#define GC_USB_DOEPCTL12_STALL_LSB 0x15
+#define GC_USB_DOEPCTL12_STALL_MASK 0x200000
+#define GC_USB_DOEPCTL12_STALL_SIZE 0x1
+#define GC_USB_DOEPCTL12_STALL_DEFAULT 0x0
+#define GC_USB_DOEPCTL12_STALL_OFFSET 0xc80
+#define GC_USB_DOEPCTL12_CNAK_LSB 0x1a
+#define GC_USB_DOEPCTL12_CNAK_MASK 0x4000000
+#define GC_USB_DOEPCTL12_CNAK_SIZE 0x1
+#define GC_USB_DOEPCTL12_CNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL12_CNAK_OFFSET 0xc80
+#define GC_USB_DOEPCTL12_SNAK_LSB 0x1b
+#define GC_USB_DOEPCTL12_SNAK_MASK 0x8000000
+#define GC_USB_DOEPCTL12_SNAK_SIZE 0x1
+#define GC_USB_DOEPCTL12_SNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL12_SNAK_OFFSET 0xc80
+#define GC_USB_DOEPCTL12_SETD0PID_LSB 0x1c
+#define GC_USB_DOEPCTL12_SETD0PID_MASK 0x10000000
+#define GC_USB_DOEPCTL12_SETD0PID_SIZE 0x1
+#define GC_USB_DOEPCTL12_SETD0PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL12_SETD0PID_OFFSET 0xc80
+#define GC_USB_DOEPCTL12_SETD1PID_LSB 0x1d
+#define GC_USB_DOEPCTL12_SETD1PID_MASK 0x20000000
+#define GC_USB_DOEPCTL12_SETD1PID_SIZE 0x1
+#define GC_USB_DOEPCTL12_SETD1PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL12_SETD1PID_OFFSET 0xc80
+#define GC_USB_DOEPCTL12_EPDIS_LSB 0x1e
+#define GC_USB_DOEPCTL12_EPDIS_MASK 0x40000000
+#define GC_USB_DOEPCTL12_EPDIS_SIZE 0x1
+#define GC_USB_DOEPCTL12_EPDIS_DEFAULT 0x0
+#define GC_USB_DOEPCTL12_EPDIS_OFFSET 0xc80
+#define GC_USB_DOEPCTL12_EPENA_LSB 0x1f
+#define GC_USB_DOEPCTL12_EPENA_MASK 0x80000000
+#define GC_USB_DOEPCTL12_EPENA_SIZE 0x1
+#define GC_USB_DOEPCTL12_EPENA_DEFAULT 0x0
+#define GC_USB_DOEPCTL12_EPENA_OFFSET 0xc80
+#define GC_USB_DOEPINT12_XFERCOMPL_LSB 0x0
+#define GC_USB_DOEPINT12_XFERCOMPL_MASK 0x1
+#define GC_USB_DOEPINT12_XFERCOMPL_SIZE 0x1
+#define GC_USB_DOEPINT12_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DOEPINT12_XFERCOMPL_OFFSET 0xc88
+#define GC_USB_DOEPINT12_EPDISBLD_LSB 0x1
+#define GC_USB_DOEPINT12_EPDISBLD_MASK 0x2
+#define GC_USB_DOEPINT12_EPDISBLD_SIZE 0x1
+#define GC_USB_DOEPINT12_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DOEPINT12_EPDISBLD_OFFSET 0xc88
+#define GC_USB_DOEPINT12_AHBERR_LSB 0x2
+#define GC_USB_DOEPINT12_AHBERR_MASK 0x4
+#define GC_USB_DOEPINT12_AHBERR_SIZE 0x1
+#define GC_USB_DOEPINT12_AHBERR_DEFAULT 0x0
+#define GC_USB_DOEPINT12_AHBERR_OFFSET 0xc88
+#define GC_USB_DOEPINT12_SETUP_LSB 0x3
+#define GC_USB_DOEPINT12_SETUP_MASK 0x8
+#define GC_USB_DOEPINT12_SETUP_SIZE 0x1
+#define GC_USB_DOEPINT12_SETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT12_SETUP_OFFSET 0xc88
+#define GC_USB_DOEPINT12_OUTTKNEPDIS_LSB 0x4
+#define GC_USB_DOEPINT12_OUTTKNEPDIS_MASK 0x10
+#define GC_USB_DOEPINT12_OUTTKNEPDIS_SIZE 0x1
+#define GC_USB_DOEPINT12_OUTTKNEPDIS_DEFAULT 0x0
+#define GC_USB_DOEPINT12_OUTTKNEPDIS_OFFSET 0xc88
+#define GC_USB_DOEPINT12_STSPHSERCVD_LSB 0x5
+#define GC_USB_DOEPINT12_STSPHSERCVD_MASK 0x20
+#define GC_USB_DOEPINT12_STSPHSERCVD_SIZE 0x1
+#define GC_USB_DOEPINT12_STSPHSERCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT12_STSPHSERCVD_OFFSET 0xc88
+#define GC_USB_DOEPINT12_BACK2BACKSETUP_LSB 0x6
+#define GC_USB_DOEPINT12_BACK2BACKSETUP_MASK 0x40
+#define GC_USB_DOEPINT12_BACK2BACKSETUP_SIZE 0x1
+#define GC_USB_DOEPINT12_BACK2BACKSETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT12_BACK2BACKSETUP_OFFSET 0xc88
+#define GC_USB_DOEPINT12_OUTPKTERR_LSB 0x8
+#define GC_USB_DOEPINT12_OUTPKTERR_MASK 0x100
+#define GC_USB_DOEPINT12_OUTPKTERR_SIZE 0x1
+#define GC_USB_DOEPINT12_OUTPKTERR_DEFAULT 0x0
+#define GC_USB_DOEPINT12_OUTPKTERR_OFFSET 0xc88
+#define GC_USB_DOEPINT12_BNAINTR_LSB 0x9
+#define GC_USB_DOEPINT12_BNAINTR_MASK 0x200
+#define GC_USB_DOEPINT12_BNAINTR_SIZE 0x1
+#define GC_USB_DOEPINT12_BNAINTR_DEFAULT 0x0
+#define GC_USB_DOEPINT12_BNAINTR_OFFSET 0xc88
+#define GC_USB_DOEPINT12_PKTDRPSTS_LSB 0xb
+#define GC_USB_DOEPINT12_PKTDRPSTS_MASK 0x800
+#define GC_USB_DOEPINT12_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DOEPINT12_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DOEPINT12_PKTDRPSTS_OFFSET 0xc88
+#define GC_USB_DOEPINT12_BBLEERR_LSB 0xc
+#define GC_USB_DOEPINT12_BBLEERR_MASK 0x1000
+#define GC_USB_DOEPINT12_BBLEERR_SIZE 0x1
+#define GC_USB_DOEPINT12_BBLEERR_DEFAULT 0x0
+#define GC_USB_DOEPINT12_BBLEERR_OFFSET 0xc88
+#define GC_USB_DOEPINT12_NAKINTRPT_LSB 0xd
+#define GC_USB_DOEPINT12_NAKINTRPT_MASK 0x2000
+#define GC_USB_DOEPINT12_NAKINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT12_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT12_NAKINTRPT_OFFSET 0xc88
+#define GC_USB_DOEPINT12_NYETINTRPT_LSB 0xe
+#define GC_USB_DOEPINT12_NYETINTRPT_MASK 0x4000
+#define GC_USB_DOEPINT12_NYETINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT12_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT12_NYETINTRPT_OFFSET 0xc88
+#define GC_USB_DOEPINT12_STUPPKTRCVD_LSB 0xf
+#define GC_USB_DOEPINT12_STUPPKTRCVD_MASK 0x8000
+#define GC_USB_DOEPINT12_STUPPKTRCVD_SIZE 0x1
+#define GC_USB_DOEPINT12_STUPPKTRCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT12_STUPPKTRCVD_OFFSET 0xc88
+#define GC_USB_DOEPTSIZ12_XFERSIZE_LSB 0x0
+#define GC_USB_DOEPTSIZ12_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DOEPTSIZ12_XFERSIZE_SIZE 0x13
+#define GC_USB_DOEPTSIZ12_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ12_XFERSIZE_OFFSET 0xc90
+#define GC_USB_DOEPTSIZ12_PKTCNT_LSB 0x13
+#define GC_USB_DOEPTSIZ12_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DOEPTSIZ12_PKTCNT_SIZE 0xa
+#define GC_USB_DOEPTSIZ12_PKTCNT_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ12_PKTCNT_OFFSET 0xc90
+#define GC_USB_DOEPTSIZ12_RXDPID_LSB 0x1d
+#define GC_USB_DOEPTSIZ12_RXDPID_MASK 0x60000000
+#define GC_USB_DOEPTSIZ12_RXDPID_SIZE 0x2
+#define GC_USB_DOEPTSIZ12_RXDPID_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ12_RXDPID_OFFSET 0xc90
+#define GC_USB_DOEPDMA12_DMAADDR_LSB 0x0
+#define GC_USB_DOEPDMA12_DMAADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMA12_DMAADDR_SIZE 0x20
+#define GC_USB_DOEPDMA12_DMAADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMA12_DMAADDR_OFFSET 0xc94
+#define GC_USB_DOEPDMAB12_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DOEPDMAB12_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMAB12_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DOEPDMAB12_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMAB12_DMABUFFERADDR_OFFSET 0xc9c
+#define GC_USB_DOEPCTL13_MPS_LSB 0x0
+#define GC_USB_DOEPCTL13_MPS_MASK 0x7ff
+#define GC_USB_DOEPCTL13_MPS_SIZE 0xb
+#define GC_USB_DOEPCTL13_MPS_DEFAULT 0x0
+#define GC_USB_DOEPCTL13_MPS_OFFSET 0xca0
+#define GC_USB_DOEPCTL13_USBACTEP_LSB 0xf
+#define GC_USB_DOEPCTL13_USBACTEP_MASK 0x8000
+#define GC_USB_DOEPCTL13_USBACTEP_SIZE 0x1
+#define GC_USB_DOEPCTL13_USBACTEP_DEFAULT 0x0
+#define GC_USB_DOEPCTL13_USBACTEP_OFFSET 0xca0
+#define GC_USB_DOEPCTL13_DPID_LSB 0x10
+#define GC_USB_DOEPCTL13_DPID_MASK 0x10000
+#define GC_USB_DOEPCTL13_DPID_SIZE 0x1
+#define GC_USB_DOEPCTL13_DPID_DEFAULT 0x0
+#define GC_USB_DOEPCTL13_DPID_OFFSET 0xca0
+#define GC_USB_DOEPCTL13_NAKSTS_LSB 0x11
+#define GC_USB_DOEPCTL13_NAKSTS_MASK 0x20000
+#define GC_USB_DOEPCTL13_NAKSTS_SIZE 0x1
+#define GC_USB_DOEPCTL13_NAKSTS_DEFAULT 0x0
+#define GC_USB_DOEPCTL13_NAKSTS_OFFSET 0xca0
+#define GC_USB_DOEPCTL13_EPTYPE_LSB 0x12
+#define GC_USB_DOEPCTL13_EPTYPE_MASK 0xc0000
+#define GC_USB_DOEPCTL13_EPTYPE_SIZE 0x2
+#define GC_USB_DOEPCTL13_EPTYPE_DEFAULT 0x0
+#define GC_USB_DOEPCTL13_EPTYPE_OFFSET 0xca0
+#define GC_USB_DOEPCTL13_SNP_LSB 0x14
+#define GC_USB_DOEPCTL13_SNP_MASK 0x100000
+#define GC_USB_DOEPCTL13_SNP_SIZE 0x1
+#define GC_USB_DOEPCTL13_SNP_DEFAULT 0x0
+#define GC_USB_DOEPCTL13_SNP_OFFSET 0xca0
+#define GC_USB_DOEPCTL13_STALL_LSB 0x15
+#define GC_USB_DOEPCTL13_STALL_MASK 0x200000
+#define GC_USB_DOEPCTL13_STALL_SIZE 0x1
+#define GC_USB_DOEPCTL13_STALL_DEFAULT 0x0
+#define GC_USB_DOEPCTL13_STALL_OFFSET 0xca0
+#define GC_USB_DOEPCTL13_CNAK_LSB 0x1a
+#define GC_USB_DOEPCTL13_CNAK_MASK 0x4000000
+#define GC_USB_DOEPCTL13_CNAK_SIZE 0x1
+#define GC_USB_DOEPCTL13_CNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL13_CNAK_OFFSET 0xca0
+#define GC_USB_DOEPCTL13_SNAK_LSB 0x1b
+#define GC_USB_DOEPCTL13_SNAK_MASK 0x8000000
+#define GC_USB_DOEPCTL13_SNAK_SIZE 0x1
+#define GC_USB_DOEPCTL13_SNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL13_SNAK_OFFSET 0xca0
+#define GC_USB_DOEPCTL13_SETD0PID_LSB 0x1c
+#define GC_USB_DOEPCTL13_SETD0PID_MASK 0x10000000
+#define GC_USB_DOEPCTL13_SETD0PID_SIZE 0x1
+#define GC_USB_DOEPCTL13_SETD0PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL13_SETD0PID_OFFSET 0xca0
+#define GC_USB_DOEPCTL13_SETD1PID_LSB 0x1d
+#define GC_USB_DOEPCTL13_SETD1PID_MASK 0x20000000
+#define GC_USB_DOEPCTL13_SETD1PID_SIZE 0x1
+#define GC_USB_DOEPCTL13_SETD1PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL13_SETD1PID_OFFSET 0xca0
+#define GC_USB_DOEPCTL13_EPDIS_LSB 0x1e
+#define GC_USB_DOEPCTL13_EPDIS_MASK 0x40000000
+#define GC_USB_DOEPCTL13_EPDIS_SIZE 0x1
+#define GC_USB_DOEPCTL13_EPDIS_DEFAULT 0x0
+#define GC_USB_DOEPCTL13_EPDIS_OFFSET 0xca0
+#define GC_USB_DOEPCTL13_EPENA_LSB 0x1f
+#define GC_USB_DOEPCTL13_EPENA_MASK 0x80000000
+#define GC_USB_DOEPCTL13_EPENA_SIZE 0x1
+#define GC_USB_DOEPCTL13_EPENA_DEFAULT 0x0
+#define GC_USB_DOEPCTL13_EPENA_OFFSET 0xca0
+#define GC_USB_DOEPINT13_XFERCOMPL_LSB 0x0
+#define GC_USB_DOEPINT13_XFERCOMPL_MASK 0x1
+#define GC_USB_DOEPINT13_XFERCOMPL_SIZE 0x1
+#define GC_USB_DOEPINT13_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DOEPINT13_XFERCOMPL_OFFSET 0xca8
+#define GC_USB_DOEPINT13_EPDISBLD_LSB 0x1
+#define GC_USB_DOEPINT13_EPDISBLD_MASK 0x2
+#define GC_USB_DOEPINT13_EPDISBLD_SIZE 0x1
+#define GC_USB_DOEPINT13_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DOEPINT13_EPDISBLD_OFFSET 0xca8
+#define GC_USB_DOEPINT13_AHBERR_LSB 0x2
+#define GC_USB_DOEPINT13_AHBERR_MASK 0x4
+#define GC_USB_DOEPINT13_AHBERR_SIZE 0x1
+#define GC_USB_DOEPINT13_AHBERR_DEFAULT 0x0
+#define GC_USB_DOEPINT13_AHBERR_OFFSET 0xca8
+#define GC_USB_DOEPINT13_SETUP_LSB 0x3
+#define GC_USB_DOEPINT13_SETUP_MASK 0x8
+#define GC_USB_DOEPINT13_SETUP_SIZE 0x1
+#define GC_USB_DOEPINT13_SETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT13_SETUP_OFFSET 0xca8
+#define GC_USB_DOEPINT13_OUTTKNEPDIS_LSB 0x4
+#define GC_USB_DOEPINT13_OUTTKNEPDIS_MASK 0x10
+#define GC_USB_DOEPINT13_OUTTKNEPDIS_SIZE 0x1
+#define GC_USB_DOEPINT13_OUTTKNEPDIS_DEFAULT 0x0
+#define GC_USB_DOEPINT13_OUTTKNEPDIS_OFFSET 0xca8
+#define GC_USB_DOEPINT13_STSPHSERCVD_LSB 0x5
+#define GC_USB_DOEPINT13_STSPHSERCVD_MASK 0x20
+#define GC_USB_DOEPINT13_STSPHSERCVD_SIZE 0x1
+#define GC_USB_DOEPINT13_STSPHSERCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT13_STSPHSERCVD_OFFSET 0xca8
+#define GC_USB_DOEPINT13_BACK2BACKSETUP_LSB 0x6
+#define GC_USB_DOEPINT13_BACK2BACKSETUP_MASK 0x40
+#define GC_USB_DOEPINT13_BACK2BACKSETUP_SIZE 0x1
+#define GC_USB_DOEPINT13_BACK2BACKSETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT13_BACK2BACKSETUP_OFFSET 0xca8
+#define GC_USB_DOEPINT13_OUTPKTERR_LSB 0x8
+#define GC_USB_DOEPINT13_OUTPKTERR_MASK 0x100
+#define GC_USB_DOEPINT13_OUTPKTERR_SIZE 0x1
+#define GC_USB_DOEPINT13_OUTPKTERR_DEFAULT 0x0
+#define GC_USB_DOEPINT13_OUTPKTERR_OFFSET 0xca8
+#define GC_USB_DOEPINT13_BNAINTR_LSB 0x9
+#define GC_USB_DOEPINT13_BNAINTR_MASK 0x200
+#define GC_USB_DOEPINT13_BNAINTR_SIZE 0x1
+#define GC_USB_DOEPINT13_BNAINTR_DEFAULT 0x0
+#define GC_USB_DOEPINT13_BNAINTR_OFFSET 0xca8
+#define GC_USB_DOEPINT13_PKTDRPSTS_LSB 0xb
+#define GC_USB_DOEPINT13_PKTDRPSTS_MASK 0x800
+#define GC_USB_DOEPINT13_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DOEPINT13_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DOEPINT13_PKTDRPSTS_OFFSET 0xca8
+#define GC_USB_DOEPINT13_BBLEERR_LSB 0xc
+#define GC_USB_DOEPINT13_BBLEERR_MASK 0x1000
+#define GC_USB_DOEPINT13_BBLEERR_SIZE 0x1
+#define GC_USB_DOEPINT13_BBLEERR_DEFAULT 0x0
+#define GC_USB_DOEPINT13_BBLEERR_OFFSET 0xca8
+#define GC_USB_DOEPINT13_NAKINTRPT_LSB 0xd
+#define GC_USB_DOEPINT13_NAKINTRPT_MASK 0x2000
+#define GC_USB_DOEPINT13_NAKINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT13_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT13_NAKINTRPT_OFFSET 0xca8
+#define GC_USB_DOEPINT13_NYETINTRPT_LSB 0xe
+#define GC_USB_DOEPINT13_NYETINTRPT_MASK 0x4000
+#define GC_USB_DOEPINT13_NYETINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT13_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT13_NYETINTRPT_OFFSET 0xca8
+#define GC_USB_DOEPINT13_STUPPKTRCVD_LSB 0xf
+#define GC_USB_DOEPINT13_STUPPKTRCVD_MASK 0x8000
+#define GC_USB_DOEPINT13_STUPPKTRCVD_SIZE 0x1
+#define GC_USB_DOEPINT13_STUPPKTRCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT13_STUPPKTRCVD_OFFSET 0xca8
+#define GC_USB_DOEPTSIZ13_XFERSIZE_LSB 0x0
+#define GC_USB_DOEPTSIZ13_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DOEPTSIZ13_XFERSIZE_SIZE 0x13
+#define GC_USB_DOEPTSIZ13_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ13_XFERSIZE_OFFSET 0xcb0
+#define GC_USB_DOEPTSIZ13_PKTCNT_LSB 0x13
+#define GC_USB_DOEPTSIZ13_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DOEPTSIZ13_PKTCNT_SIZE 0xa
+#define GC_USB_DOEPTSIZ13_PKTCNT_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ13_PKTCNT_OFFSET 0xcb0
+#define GC_USB_DOEPTSIZ13_RXDPID_LSB 0x1d
+#define GC_USB_DOEPTSIZ13_RXDPID_MASK 0x60000000
+#define GC_USB_DOEPTSIZ13_RXDPID_SIZE 0x2
+#define GC_USB_DOEPTSIZ13_RXDPID_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ13_RXDPID_OFFSET 0xcb0
+#define GC_USB_DOEPDMA13_DMAADDR_LSB 0x0
+#define GC_USB_DOEPDMA13_DMAADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMA13_DMAADDR_SIZE 0x20
+#define GC_USB_DOEPDMA13_DMAADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMA13_DMAADDR_OFFSET 0xcb4
+#define GC_USB_DOEPDMAB13_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DOEPDMAB13_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMAB13_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DOEPDMAB13_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMAB13_DMABUFFERADDR_OFFSET 0xcbc
+#define GC_USB_DOEPCTL14_MPS_LSB 0x0
+#define GC_USB_DOEPCTL14_MPS_MASK 0x7ff
+#define GC_USB_DOEPCTL14_MPS_SIZE 0xb
+#define GC_USB_DOEPCTL14_MPS_DEFAULT 0x0
+#define GC_USB_DOEPCTL14_MPS_OFFSET 0xcc0
+#define GC_USB_DOEPCTL14_USBACTEP_LSB 0xf
+#define GC_USB_DOEPCTL14_USBACTEP_MASK 0x8000
+#define GC_USB_DOEPCTL14_USBACTEP_SIZE 0x1
+#define GC_USB_DOEPCTL14_USBACTEP_DEFAULT 0x0
+#define GC_USB_DOEPCTL14_USBACTEP_OFFSET 0xcc0
+#define GC_USB_DOEPCTL14_DPID_LSB 0x10
+#define GC_USB_DOEPCTL14_DPID_MASK 0x10000
+#define GC_USB_DOEPCTL14_DPID_SIZE 0x1
+#define GC_USB_DOEPCTL14_DPID_DEFAULT 0x0
+#define GC_USB_DOEPCTL14_DPID_OFFSET 0xcc0
+#define GC_USB_DOEPCTL14_NAKSTS_LSB 0x11
+#define GC_USB_DOEPCTL14_NAKSTS_MASK 0x20000
+#define GC_USB_DOEPCTL14_NAKSTS_SIZE 0x1
+#define GC_USB_DOEPCTL14_NAKSTS_DEFAULT 0x0
+#define GC_USB_DOEPCTL14_NAKSTS_OFFSET 0xcc0
+#define GC_USB_DOEPCTL14_EPTYPE_LSB 0x12
+#define GC_USB_DOEPCTL14_EPTYPE_MASK 0xc0000
+#define GC_USB_DOEPCTL14_EPTYPE_SIZE 0x2
+#define GC_USB_DOEPCTL14_EPTYPE_DEFAULT 0x0
+#define GC_USB_DOEPCTL14_EPTYPE_OFFSET 0xcc0
+#define GC_USB_DOEPCTL14_SNP_LSB 0x14
+#define GC_USB_DOEPCTL14_SNP_MASK 0x100000
+#define GC_USB_DOEPCTL14_SNP_SIZE 0x1
+#define GC_USB_DOEPCTL14_SNP_DEFAULT 0x0
+#define GC_USB_DOEPCTL14_SNP_OFFSET 0xcc0
+#define GC_USB_DOEPCTL14_STALL_LSB 0x15
+#define GC_USB_DOEPCTL14_STALL_MASK 0x200000
+#define GC_USB_DOEPCTL14_STALL_SIZE 0x1
+#define GC_USB_DOEPCTL14_STALL_DEFAULT 0x0
+#define GC_USB_DOEPCTL14_STALL_OFFSET 0xcc0
+#define GC_USB_DOEPCTL14_CNAK_LSB 0x1a
+#define GC_USB_DOEPCTL14_CNAK_MASK 0x4000000
+#define GC_USB_DOEPCTL14_CNAK_SIZE 0x1
+#define GC_USB_DOEPCTL14_CNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL14_CNAK_OFFSET 0xcc0
+#define GC_USB_DOEPCTL14_SNAK_LSB 0x1b
+#define GC_USB_DOEPCTL14_SNAK_MASK 0x8000000
+#define GC_USB_DOEPCTL14_SNAK_SIZE 0x1
+#define GC_USB_DOEPCTL14_SNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL14_SNAK_OFFSET 0xcc0
+#define GC_USB_DOEPCTL14_SETD0PID_LSB 0x1c
+#define GC_USB_DOEPCTL14_SETD0PID_MASK 0x10000000
+#define GC_USB_DOEPCTL14_SETD0PID_SIZE 0x1
+#define GC_USB_DOEPCTL14_SETD0PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL14_SETD0PID_OFFSET 0xcc0
+#define GC_USB_DOEPCTL14_SETD1PID_LSB 0x1d
+#define GC_USB_DOEPCTL14_SETD1PID_MASK 0x20000000
+#define GC_USB_DOEPCTL14_SETD1PID_SIZE 0x1
+#define GC_USB_DOEPCTL14_SETD1PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL14_SETD1PID_OFFSET 0xcc0
+#define GC_USB_DOEPCTL14_EPDIS_LSB 0x1e
+#define GC_USB_DOEPCTL14_EPDIS_MASK 0x40000000
+#define GC_USB_DOEPCTL14_EPDIS_SIZE 0x1
+#define GC_USB_DOEPCTL14_EPDIS_DEFAULT 0x0
+#define GC_USB_DOEPCTL14_EPDIS_OFFSET 0xcc0
+#define GC_USB_DOEPCTL14_EPENA_LSB 0x1f
+#define GC_USB_DOEPCTL14_EPENA_MASK 0x80000000
+#define GC_USB_DOEPCTL14_EPENA_SIZE 0x1
+#define GC_USB_DOEPCTL14_EPENA_DEFAULT 0x0
+#define GC_USB_DOEPCTL14_EPENA_OFFSET 0xcc0
+#define GC_USB_DOEPINT14_XFERCOMPL_LSB 0x0
+#define GC_USB_DOEPINT14_XFERCOMPL_MASK 0x1
+#define GC_USB_DOEPINT14_XFERCOMPL_SIZE 0x1
+#define GC_USB_DOEPINT14_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DOEPINT14_XFERCOMPL_OFFSET 0xcc8
+#define GC_USB_DOEPINT14_EPDISBLD_LSB 0x1
+#define GC_USB_DOEPINT14_EPDISBLD_MASK 0x2
+#define GC_USB_DOEPINT14_EPDISBLD_SIZE 0x1
+#define GC_USB_DOEPINT14_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DOEPINT14_EPDISBLD_OFFSET 0xcc8
+#define GC_USB_DOEPINT14_AHBERR_LSB 0x2
+#define GC_USB_DOEPINT14_AHBERR_MASK 0x4
+#define GC_USB_DOEPINT14_AHBERR_SIZE 0x1
+#define GC_USB_DOEPINT14_AHBERR_DEFAULT 0x0
+#define GC_USB_DOEPINT14_AHBERR_OFFSET 0xcc8
+#define GC_USB_DOEPINT14_SETUP_LSB 0x3
+#define GC_USB_DOEPINT14_SETUP_MASK 0x8
+#define GC_USB_DOEPINT14_SETUP_SIZE 0x1
+#define GC_USB_DOEPINT14_SETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT14_SETUP_OFFSET 0xcc8
+#define GC_USB_DOEPINT14_OUTTKNEPDIS_LSB 0x4
+#define GC_USB_DOEPINT14_OUTTKNEPDIS_MASK 0x10
+#define GC_USB_DOEPINT14_OUTTKNEPDIS_SIZE 0x1
+#define GC_USB_DOEPINT14_OUTTKNEPDIS_DEFAULT 0x0
+#define GC_USB_DOEPINT14_OUTTKNEPDIS_OFFSET 0xcc8
+#define GC_USB_DOEPINT14_STSPHSERCVD_LSB 0x5
+#define GC_USB_DOEPINT14_STSPHSERCVD_MASK 0x20
+#define GC_USB_DOEPINT14_STSPHSERCVD_SIZE 0x1
+#define GC_USB_DOEPINT14_STSPHSERCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT14_STSPHSERCVD_OFFSET 0xcc8
+#define GC_USB_DOEPINT14_BACK2BACKSETUP_LSB 0x6
+#define GC_USB_DOEPINT14_BACK2BACKSETUP_MASK 0x40
+#define GC_USB_DOEPINT14_BACK2BACKSETUP_SIZE 0x1
+#define GC_USB_DOEPINT14_BACK2BACKSETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT14_BACK2BACKSETUP_OFFSET 0xcc8
+#define GC_USB_DOEPINT14_OUTPKTERR_LSB 0x8
+#define GC_USB_DOEPINT14_OUTPKTERR_MASK 0x100
+#define GC_USB_DOEPINT14_OUTPKTERR_SIZE 0x1
+#define GC_USB_DOEPINT14_OUTPKTERR_DEFAULT 0x0
+#define GC_USB_DOEPINT14_OUTPKTERR_OFFSET 0xcc8
+#define GC_USB_DOEPINT14_BNAINTR_LSB 0x9
+#define GC_USB_DOEPINT14_BNAINTR_MASK 0x200
+#define GC_USB_DOEPINT14_BNAINTR_SIZE 0x1
+#define GC_USB_DOEPINT14_BNAINTR_DEFAULT 0x0
+#define GC_USB_DOEPINT14_BNAINTR_OFFSET 0xcc8
+#define GC_USB_DOEPINT14_PKTDRPSTS_LSB 0xb
+#define GC_USB_DOEPINT14_PKTDRPSTS_MASK 0x800
+#define GC_USB_DOEPINT14_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DOEPINT14_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DOEPINT14_PKTDRPSTS_OFFSET 0xcc8
+#define GC_USB_DOEPINT14_BBLEERR_LSB 0xc
+#define GC_USB_DOEPINT14_BBLEERR_MASK 0x1000
+#define GC_USB_DOEPINT14_BBLEERR_SIZE 0x1
+#define GC_USB_DOEPINT14_BBLEERR_DEFAULT 0x0
+#define GC_USB_DOEPINT14_BBLEERR_OFFSET 0xcc8
+#define GC_USB_DOEPINT14_NAKINTRPT_LSB 0xd
+#define GC_USB_DOEPINT14_NAKINTRPT_MASK 0x2000
+#define GC_USB_DOEPINT14_NAKINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT14_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT14_NAKINTRPT_OFFSET 0xcc8
+#define GC_USB_DOEPINT14_NYETINTRPT_LSB 0xe
+#define GC_USB_DOEPINT14_NYETINTRPT_MASK 0x4000
+#define GC_USB_DOEPINT14_NYETINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT14_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT14_NYETINTRPT_OFFSET 0xcc8
+#define GC_USB_DOEPINT14_STUPPKTRCVD_LSB 0xf
+#define GC_USB_DOEPINT14_STUPPKTRCVD_MASK 0x8000
+#define GC_USB_DOEPINT14_STUPPKTRCVD_SIZE 0x1
+#define GC_USB_DOEPINT14_STUPPKTRCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT14_STUPPKTRCVD_OFFSET 0xcc8
+#define GC_USB_DOEPTSIZ14_XFERSIZE_LSB 0x0
+#define GC_USB_DOEPTSIZ14_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DOEPTSIZ14_XFERSIZE_SIZE 0x13
+#define GC_USB_DOEPTSIZ14_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ14_XFERSIZE_OFFSET 0xcd0
+#define GC_USB_DOEPTSIZ14_PKTCNT_LSB 0x13
+#define GC_USB_DOEPTSIZ14_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DOEPTSIZ14_PKTCNT_SIZE 0xa
+#define GC_USB_DOEPTSIZ14_PKTCNT_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ14_PKTCNT_OFFSET 0xcd0
+#define GC_USB_DOEPTSIZ14_RXDPID_LSB 0x1d
+#define GC_USB_DOEPTSIZ14_RXDPID_MASK 0x60000000
+#define GC_USB_DOEPTSIZ14_RXDPID_SIZE 0x2
+#define GC_USB_DOEPTSIZ14_RXDPID_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ14_RXDPID_OFFSET 0xcd0
+#define GC_USB_DOEPDMA14_DMAADDR_LSB 0x0
+#define GC_USB_DOEPDMA14_DMAADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMA14_DMAADDR_SIZE 0x20
+#define GC_USB_DOEPDMA14_DMAADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMA14_DMAADDR_OFFSET 0xcd4
+#define GC_USB_DOEPDMAB14_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DOEPDMAB14_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMAB14_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DOEPDMAB14_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMAB14_DMABUFFERADDR_OFFSET 0xcdc
+#define GC_USB_DOEPCTL15_MPS_LSB 0x0
+#define GC_USB_DOEPCTL15_MPS_MASK 0x7ff
+#define GC_USB_DOEPCTL15_MPS_SIZE 0xb
+#define GC_USB_DOEPCTL15_MPS_DEFAULT 0x0
+#define GC_USB_DOEPCTL15_MPS_OFFSET 0xce0
+#define GC_USB_DOEPCTL15_USBACTEP_LSB 0xf
+#define GC_USB_DOEPCTL15_USBACTEP_MASK 0x8000
+#define GC_USB_DOEPCTL15_USBACTEP_SIZE 0x1
+#define GC_USB_DOEPCTL15_USBACTEP_DEFAULT 0x0
+#define GC_USB_DOEPCTL15_USBACTEP_OFFSET 0xce0
+#define GC_USB_DOEPCTL15_DPID_LSB 0x10
+#define GC_USB_DOEPCTL15_DPID_MASK 0x10000
+#define GC_USB_DOEPCTL15_DPID_SIZE 0x1
+#define GC_USB_DOEPCTL15_DPID_DEFAULT 0x0
+#define GC_USB_DOEPCTL15_DPID_OFFSET 0xce0
+#define GC_USB_DOEPCTL15_NAKSTS_LSB 0x11
+#define GC_USB_DOEPCTL15_NAKSTS_MASK 0x20000
+#define GC_USB_DOEPCTL15_NAKSTS_SIZE 0x1
+#define GC_USB_DOEPCTL15_NAKSTS_DEFAULT 0x0
+#define GC_USB_DOEPCTL15_NAKSTS_OFFSET 0xce0
+#define GC_USB_DOEPCTL15_EPTYPE_LSB 0x12
+#define GC_USB_DOEPCTL15_EPTYPE_MASK 0xc0000
+#define GC_USB_DOEPCTL15_EPTYPE_SIZE 0x2
+#define GC_USB_DOEPCTL15_EPTYPE_DEFAULT 0x0
+#define GC_USB_DOEPCTL15_EPTYPE_OFFSET 0xce0
+#define GC_USB_DOEPCTL15_SNP_LSB 0x14
+#define GC_USB_DOEPCTL15_SNP_MASK 0x100000
+#define GC_USB_DOEPCTL15_SNP_SIZE 0x1
+#define GC_USB_DOEPCTL15_SNP_DEFAULT 0x0
+#define GC_USB_DOEPCTL15_SNP_OFFSET 0xce0
+#define GC_USB_DOEPCTL15_STALL_LSB 0x15
+#define GC_USB_DOEPCTL15_STALL_MASK 0x200000
+#define GC_USB_DOEPCTL15_STALL_SIZE 0x1
+#define GC_USB_DOEPCTL15_STALL_DEFAULT 0x0
+#define GC_USB_DOEPCTL15_STALL_OFFSET 0xce0
+#define GC_USB_DOEPCTL15_CNAK_LSB 0x1a
+#define GC_USB_DOEPCTL15_CNAK_MASK 0x4000000
+#define GC_USB_DOEPCTL15_CNAK_SIZE 0x1
+#define GC_USB_DOEPCTL15_CNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL15_CNAK_OFFSET 0xce0
+#define GC_USB_DOEPCTL15_SNAK_LSB 0x1b
+#define GC_USB_DOEPCTL15_SNAK_MASK 0x8000000
+#define GC_USB_DOEPCTL15_SNAK_SIZE 0x1
+#define GC_USB_DOEPCTL15_SNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL15_SNAK_OFFSET 0xce0
+#define GC_USB_DOEPCTL15_SETD0PID_LSB 0x1c
+#define GC_USB_DOEPCTL15_SETD0PID_MASK 0x10000000
+#define GC_USB_DOEPCTL15_SETD0PID_SIZE 0x1
+#define GC_USB_DOEPCTL15_SETD0PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL15_SETD0PID_OFFSET 0xce0
+#define GC_USB_DOEPCTL15_SETD1PID_LSB 0x1d
+#define GC_USB_DOEPCTL15_SETD1PID_MASK 0x20000000
+#define GC_USB_DOEPCTL15_SETD1PID_SIZE 0x1
+#define GC_USB_DOEPCTL15_SETD1PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL15_SETD1PID_OFFSET 0xce0
+#define GC_USB_DOEPCTL15_EPDIS_LSB 0x1e
+#define GC_USB_DOEPCTL15_EPDIS_MASK 0x40000000
+#define GC_USB_DOEPCTL15_EPDIS_SIZE 0x1
+#define GC_USB_DOEPCTL15_EPDIS_DEFAULT 0x0
+#define GC_USB_DOEPCTL15_EPDIS_OFFSET 0xce0
+#define GC_USB_DOEPCTL15_EPENA_LSB 0x1f
+#define GC_USB_DOEPCTL15_EPENA_MASK 0x80000000
+#define GC_USB_DOEPCTL15_EPENA_SIZE 0x1
+#define GC_USB_DOEPCTL15_EPENA_DEFAULT 0x0
+#define GC_USB_DOEPCTL15_EPENA_OFFSET 0xce0
+#define GC_USB_DOEPINT15_XFERCOMPL_LSB 0x0
+#define GC_USB_DOEPINT15_XFERCOMPL_MASK 0x1
+#define GC_USB_DOEPINT15_XFERCOMPL_SIZE 0x1
+#define GC_USB_DOEPINT15_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DOEPINT15_XFERCOMPL_OFFSET 0xce8
+#define GC_USB_DOEPINT15_EPDISBLD_LSB 0x1
+#define GC_USB_DOEPINT15_EPDISBLD_MASK 0x2
+#define GC_USB_DOEPINT15_EPDISBLD_SIZE 0x1
+#define GC_USB_DOEPINT15_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DOEPINT15_EPDISBLD_OFFSET 0xce8
+#define GC_USB_DOEPINT15_AHBERR_LSB 0x2
+#define GC_USB_DOEPINT15_AHBERR_MASK 0x4
+#define GC_USB_DOEPINT15_AHBERR_SIZE 0x1
+#define GC_USB_DOEPINT15_AHBERR_DEFAULT 0x0
+#define GC_USB_DOEPINT15_AHBERR_OFFSET 0xce8
+#define GC_USB_DOEPINT15_SETUP_LSB 0x3
+#define GC_USB_DOEPINT15_SETUP_MASK 0x8
+#define GC_USB_DOEPINT15_SETUP_SIZE 0x1
+#define GC_USB_DOEPINT15_SETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT15_SETUP_OFFSET 0xce8
+#define GC_USB_DOEPINT15_OUTTKNEPDIS_LSB 0x4
+#define GC_USB_DOEPINT15_OUTTKNEPDIS_MASK 0x10
+#define GC_USB_DOEPINT15_OUTTKNEPDIS_SIZE 0x1
+#define GC_USB_DOEPINT15_OUTTKNEPDIS_DEFAULT 0x0
+#define GC_USB_DOEPINT15_OUTTKNEPDIS_OFFSET 0xce8
+#define GC_USB_DOEPINT15_STSPHSERCVD_LSB 0x5
+#define GC_USB_DOEPINT15_STSPHSERCVD_MASK 0x20
+#define GC_USB_DOEPINT15_STSPHSERCVD_SIZE 0x1
+#define GC_USB_DOEPINT15_STSPHSERCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT15_STSPHSERCVD_OFFSET 0xce8
+#define GC_USB_DOEPINT15_BACK2BACKSETUP_LSB 0x6
+#define GC_USB_DOEPINT15_BACK2BACKSETUP_MASK 0x40
+#define GC_USB_DOEPINT15_BACK2BACKSETUP_SIZE 0x1
+#define GC_USB_DOEPINT15_BACK2BACKSETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT15_BACK2BACKSETUP_OFFSET 0xce8
+#define GC_USB_DOEPINT15_OUTPKTERR_LSB 0x8
+#define GC_USB_DOEPINT15_OUTPKTERR_MASK 0x100
+#define GC_USB_DOEPINT15_OUTPKTERR_SIZE 0x1
+#define GC_USB_DOEPINT15_OUTPKTERR_DEFAULT 0x0
+#define GC_USB_DOEPINT15_OUTPKTERR_OFFSET 0xce8
+#define GC_USB_DOEPINT15_BNAINTR_LSB 0x9
+#define GC_USB_DOEPINT15_BNAINTR_MASK 0x200
+#define GC_USB_DOEPINT15_BNAINTR_SIZE 0x1
+#define GC_USB_DOEPINT15_BNAINTR_DEFAULT 0x0
+#define GC_USB_DOEPINT15_BNAINTR_OFFSET 0xce8
+#define GC_USB_DOEPINT15_PKTDRPSTS_LSB 0xb
+#define GC_USB_DOEPINT15_PKTDRPSTS_MASK 0x800
+#define GC_USB_DOEPINT15_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DOEPINT15_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DOEPINT15_PKTDRPSTS_OFFSET 0xce8
+#define GC_USB_DOEPINT15_BBLEERR_LSB 0xc
+#define GC_USB_DOEPINT15_BBLEERR_MASK 0x1000
+#define GC_USB_DOEPINT15_BBLEERR_SIZE 0x1
+#define GC_USB_DOEPINT15_BBLEERR_DEFAULT 0x0
+#define GC_USB_DOEPINT15_BBLEERR_OFFSET 0xce8
+#define GC_USB_DOEPINT15_NAKINTRPT_LSB 0xd
+#define GC_USB_DOEPINT15_NAKINTRPT_MASK 0x2000
+#define GC_USB_DOEPINT15_NAKINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT15_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT15_NAKINTRPT_OFFSET 0xce8
+#define GC_USB_DOEPINT15_NYETINTRPT_LSB 0xe
+#define GC_USB_DOEPINT15_NYETINTRPT_MASK 0x4000
+#define GC_USB_DOEPINT15_NYETINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT15_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT15_NYETINTRPT_OFFSET 0xce8
+#define GC_USB_DOEPINT15_STUPPKTRCVD_LSB 0xf
+#define GC_USB_DOEPINT15_STUPPKTRCVD_MASK 0x8000
+#define GC_USB_DOEPINT15_STUPPKTRCVD_SIZE 0x1
+#define GC_USB_DOEPINT15_STUPPKTRCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT15_STUPPKTRCVD_OFFSET 0xce8
+#define GC_USB_DOEPTSIZ15_XFERSIZE_LSB 0x0
+#define GC_USB_DOEPTSIZ15_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DOEPTSIZ15_XFERSIZE_SIZE 0x13
+#define GC_USB_DOEPTSIZ15_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ15_XFERSIZE_OFFSET 0xcf0
+#define GC_USB_DOEPTSIZ15_PKTCNT_LSB 0x13
+#define GC_USB_DOEPTSIZ15_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DOEPTSIZ15_PKTCNT_SIZE 0xa
+#define GC_USB_DOEPTSIZ15_PKTCNT_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ15_PKTCNT_OFFSET 0xcf0
+#define GC_USB_DOEPTSIZ15_RXDPID_LSB 0x1d
+#define GC_USB_DOEPTSIZ15_RXDPID_MASK 0x60000000
+#define GC_USB_DOEPTSIZ15_RXDPID_SIZE 0x2
+#define GC_USB_DOEPTSIZ15_RXDPID_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ15_RXDPID_OFFSET 0xcf0
+#define GC_USB_DOEPDMA15_DMAADDR_LSB 0x0
+#define GC_USB_DOEPDMA15_DMAADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMA15_DMAADDR_SIZE 0x20
+#define GC_USB_DOEPDMA15_DMAADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMA15_DMAADDR_OFFSET 0xcf4
+#define GC_USB_DOEPDMAB15_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DOEPDMAB15_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMAB15_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DOEPDMAB15_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMAB15_DMABUFFERADDR_OFFSET 0xcfc
+#define GC_USB_PCGCCTL_STOPPCLK_LSB 0x0
+#define GC_USB_PCGCCTL_STOPPCLK_MASK 0x1
+#define GC_USB_PCGCCTL_STOPPCLK_SIZE 0x1
+#define GC_USB_PCGCCTL_STOPPCLK_DEFAULT 0x0
+#define GC_USB_PCGCCTL_STOPPCLK_OFFSET 0xe00
+#define GC_USB_PCGCCTL_GATEHCLK_LSB 0x1
+#define GC_USB_PCGCCTL_GATEHCLK_MASK 0x2
+#define GC_USB_PCGCCTL_GATEHCLK_SIZE 0x1
+#define GC_USB_PCGCCTL_GATEHCLK_DEFAULT 0x0
+#define GC_USB_PCGCCTL_GATEHCLK_OFFSET 0xe00
+#define GC_USB_PCGCCTL_PWRCLMP_LSB 0x2
+#define GC_USB_PCGCCTL_PWRCLMP_MASK 0x4
+#define GC_USB_PCGCCTL_PWRCLMP_SIZE 0x1
+#define GC_USB_PCGCCTL_PWRCLMP_DEFAULT 0x0
+#define GC_USB_PCGCCTL_PWRCLMP_OFFSET 0xe00
+#define GC_USB_PCGCCTL_RSTPDWNMODULE_LSB 0x3
+#define GC_USB_PCGCCTL_RSTPDWNMODULE_MASK 0x8
+#define GC_USB_PCGCCTL_RSTPDWNMODULE_SIZE 0x1
+#define GC_USB_PCGCCTL_RSTPDWNMODULE_DEFAULT 0x0
+#define GC_USB_PCGCCTL_RSTPDWNMODULE_OFFSET 0xe00
+#define GC_USB_PCGCCTL_PHYSLEEP_LSB 0x6
+#define GC_USB_PCGCCTL_PHYSLEEP_MASK 0x40
+#define GC_USB_PCGCCTL_PHYSLEEP_SIZE 0x1
+#define GC_USB_PCGCCTL_PHYSLEEP_DEFAULT 0x0
+#define GC_USB_PCGCCTL_PHYSLEEP_OFFSET 0xe00
+#define GC_USB_PCGCCTL_L1SUSPENDED_LSB 0x7
+#define GC_USB_PCGCCTL_L1SUSPENDED_MASK 0x80
+#define GC_USB_PCGCCTL_L1SUSPENDED_SIZE 0x1
+#define GC_USB_PCGCCTL_L1SUSPENDED_DEFAULT 0x0
+#define GC_USB_PCGCCTL_L1SUSPENDED_OFFSET 0xe00
+#define GC_USB_DFIFO_SIZE 0x1000
 
 #endif /* __CHIP_STM32_USB_DWC_REGISTERS_H */
diff --git a/chip/stm32/usb_dwc_stream.c b/chip/stm32/usb_dwc_stream.c
index 2f20d88dda..78e0a4b484 100644
--- a/chip/stm32/usb_dwc_stream.c
+++ b/chip/stm32/usb_dwc_stream.c
@@ -1,15 +1,14 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "console.h"
 #include "registers.h"
 #include "timer.h"
 #include "usb_dwc_stream.h"
 #include "util.h"
-
-#include "console.h"
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args)
 
 /*
  * This function tries to shove new bytes from the USB host into the queue for
@@ -24,9 +23,8 @@ int rx_stream_handler(struct usb_stream_config const *config)
 
 	/* If we have some, try to shove them into the queue */
 	if (rx_count) {
-		size_t added = QUEUE_ADD_UNITS(
-			config->producer.queue, config->rx_ram,
-			rx_count);
+		size_t added = QUEUE_ADD_UNITS(config->producer.queue,
+					       config->rx_ram, rx_count);
 		if (added != rx_count) {
 			CPRINTF("rx_stream_handler: failed ep%d "
 				"queue %d bytes, accepted %d\n",
@@ -60,7 +58,7 @@ int tx_stream_handler(struct usb_stream_config const *config)
 
 /* Reset stream */
 void usb_stream_event(struct usb_stream_config const *config,
-		enum usb_ep_event evt)
+		      enum usb_ep_event evt)
 {
 	if (evt != USB_EVENT_RESET)
 		return;
diff --git a/chip/stm32/usb_dwc_stream.h b/chip/stm32/usb_dwc_stream.h
index e46e7a929c..bd512f5e9a 100644
--- a/chip/stm32/usb_dwc_stream.h
+++ b/chip/stm32/usb_dwc_stream.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,9 +10,9 @@
 #include "compile_time_macros.h"
 #include "consumer.h"
 #include "hooks.h"
-#include "registers.h"
 #include "producer.h"
 #include "queue.h"
+#include "registers.h"
 #include "usb_descriptor.h"
 #include "usb_hw.h"
 
@@ -54,7 +54,6 @@ struct usb_stream_config {
 extern struct consumer_ops const usb_stream_consumer_ops;
 extern struct producer_ops const usb_stream_producer_ops;
 
-
 /*
  * Convenience macro for defining USB streams and their associated state and
  * buffers.
@@ -92,26 +91,19 @@ extern struct producer_ops const usb_stream_producer_ops;
  * BUILD_ASSERT(RX_QUEUE.unit_bytes == 1);
  * BUILD_ASSERT(TX_QUEUE.unit_bytes == 1);
  */
-#define USB_STREAM_CONFIG_FULL(NAME,					\
-			       INTERFACE,				\
-			       INTERFACE_CLASS,				\
-			       INTERFACE_SUBCLASS,			\
-			       INTERFACE_PROTOCOL,			\
-			       INTERFACE_NAME,				\
-			       ENDPOINT,				\
-			       RX_SIZE,					\
-			       TX_SIZE,					\
-			       RX_QUEUE,				\
-			       TX_QUEUE)				\
-									\
-	static uint8_t CONCAT2(NAME, _buf_rx_)[RX_SIZE];		\
-	static uint8_t CONCAT2(NAME, _buf_tx_)[TX_SIZE];		\
-	static int CONCAT2(NAME, _is_reset_);				\
-	static int CONCAT2(NAME, _overflow_);				\
-	static void CONCAT2(NAME, _deferred_tx_)(void);			\
-	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_tx_));			\
-	static void CONCAT2(NAME, _deferred_rx_)(void);			\
-	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_rx_));			\
+#define USB_STREAM_CONFIG_FULL(NAME, INTERFACE, INTERFACE_CLASS,               \
+			       INTERFACE_SUBCLASS, INTERFACE_PROTOCOL,         \
+			       INTERFACE_NAME, ENDPOINT, RX_SIZE, TX_SIZE,     \
+			       RX_QUEUE, TX_QUEUE)                             \
+                                                                               \
+	static uint8_t CONCAT2(NAME, _buf_rx_)[RX_SIZE];                       \
+	static uint8_t CONCAT2(NAME, _buf_tx_)[TX_SIZE];                       \
+	static int CONCAT2(NAME, _is_reset_);                                  \
+	static int CONCAT2(NAME, _overflow_);                                  \
+	static void CONCAT2(NAME, _deferred_tx_)(void);                        \
+	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_tx_));                        \
+	static void CONCAT2(NAME, _deferred_rx_)(void);                        \
+	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_rx_));                        \
 	struct usb_stream_config const NAME = {				\
 		.endpoint     = ENDPOINT,				\
 		.is_reset     = &CONCAT2(NAME, _is_reset_),		\
@@ -130,94 +122,80 @@ extern struct producer_ops const usb_stream_producer_ops;
 			.queue = &RX_QUEUE,				\
 			.ops   = &usb_stream_producer_ops,		\
 		},							\
-	};								\
-	const struct usb_interface_descriptor				\
-	USB_IFACE_DESC(INTERFACE) = {					\
-		.bLength            = USB_DT_INTERFACE_SIZE,		\
-		.bDescriptorType    = USB_DT_INTERFACE,			\
-		.bInterfaceNumber   = INTERFACE,			\
-		.bAlternateSetting  = 0,				\
-		.bNumEndpoints      = 2,				\
-		.bInterfaceClass    = INTERFACE_CLASS,			\
-		.bInterfaceSubClass = INTERFACE_SUBCLASS,		\
-		.bInterfaceProtocol = INTERFACE_PROTOCOL,		\
-		.iInterface         = INTERFACE_NAME,			\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 0) = {					\
-		.bLength          = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = 0x80 | ENDPOINT,			\
-		.bmAttributes     = 0x02 /* Bulk IN */,			\
-		.wMaxPacketSize   = TX_SIZE,				\
-		.bInterval        = 10,					\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 1) = {					\
-		.bLength          = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = ENDPOINT,				\
-		.bmAttributes     = 0x02 /* Bulk OUT */,		\
-		.wMaxPacketSize   = RX_SIZE,				\
-		.bInterval        = 0,					\
-	};								\
-	static void CONCAT2(NAME, _deferred_tx_)(void)			\
-	{ tx_stream_handler(&NAME); }					\
-	static void CONCAT2(NAME, _deferred_rx_)(void)			\
-	{ rx_stream_handler(&NAME); }					\
-	static void CONCAT2(NAME, _ep_tx)(void)				\
-	{								\
-		usb_epN_tx(ENDPOINT);					\
-	}								\
-	static void CONCAT2(NAME, _ep_rx)(void)				\
-	{								\
-		usb_epN_rx(ENDPOINT);					\
-	}								\
-	static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt)	\
-	{								\
-		usb_stream_event(&NAME, evt);				\
-	}								\
-	struct dwc_usb_ep CONCAT2(NAME, _ep_ctl) = {			\
-		.max_packet = USB_MAX_PACKET_SIZE,			\
-		.tx_fifo = ENDPOINT,					\
-		.out_pending = 0,					\
-		.out_expected = 0,					\
-		.out_data = 0,						\
-		.out_databuffer = CONCAT2(NAME, _buf_rx_),		\
-		.out_databuffer_max = RX_SIZE,				\
-		.rx_deferred = &CONCAT2(NAME, _deferred_rx__data),	\
-		.in_packets = 0,					\
-		.in_pending = 0,					\
-		.in_data = 0,						\
-		.in_databuffer = CONCAT2(NAME, _buf_tx_),		\
-		.in_databuffer_max = TX_SIZE,				\
-		.tx_deferred = &CONCAT2(NAME, _deferred_tx__data),	\
-	};								\
-	USB_DECLARE_EP(ENDPOINT,					\
-		       CONCAT2(NAME, _ep_tx),				\
-		       CONCAT2(NAME, _ep_rx),				\
+	};                           \
+	const struct usb_interface_descriptor USB_IFACE_DESC(INTERFACE) = {    \
+		.bLength = USB_DT_INTERFACE_SIZE,                              \
+		.bDescriptorType = USB_DT_INTERFACE,                           \
+		.bInterfaceNumber = INTERFACE,                                 \
+		.bAlternateSetting = 0,                                        \
+		.bNumEndpoints = 2,                                            \
+		.bInterfaceClass = INTERFACE_CLASS,                            \
+		.bInterfaceSubClass = INTERFACE_SUBCLASS,                      \
+		.bInterfaceProtocol = INTERFACE_PROTOCOL,                      \
+		.iInterface = INTERFACE_NAME,                                  \
+	};                                                                     \
+	const struct usb_endpoint_descriptor USB_EP_DESC(INTERFACE, 0) = {     \
+		.bLength = USB_DT_ENDPOINT_SIZE,                               \
+		.bDescriptorType = USB_DT_ENDPOINT,                            \
+		.bEndpointAddress = 0x80 | ENDPOINT,                           \
+		.bmAttributes = 0x02 /* Bulk IN */,                            \
+		.wMaxPacketSize = TX_SIZE,                                     \
+		.bInterval = 10,                                               \
+	};                                                                     \
+	const struct usb_endpoint_descriptor USB_EP_DESC(INTERFACE, 1) = {     \
+		.bLength = USB_DT_ENDPOINT_SIZE,                               \
+		.bDescriptorType = USB_DT_ENDPOINT,                            \
+		.bEndpointAddress = ENDPOINT,                                  \
+		.bmAttributes = 0x02 /* Bulk OUT */,                           \
+		.wMaxPacketSize = RX_SIZE,                                     \
+		.bInterval = 0,                                                \
+	};                                                                     \
+	static void CONCAT2(NAME, _deferred_tx_)(void)                         \
+	{                                                                      \
+		tx_stream_handler(&NAME);                                      \
+	}                                                                      \
+	static void CONCAT2(NAME, _deferred_rx_)(void)                         \
+	{                                                                      \
+		rx_stream_handler(&NAME);                                      \
+	}                                                                      \
+	static void CONCAT2(NAME, _ep_tx)(void)                                \
+	{                                                                      \
+		usb_epN_tx(ENDPOINT);                                          \
+	}                                                                      \
+	static void CONCAT2(NAME, _ep_rx)(void)                                \
+	{                                                                      \
+		usb_epN_rx(ENDPOINT);                                          \
+	}                                                                      \
+	static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt)            \
+	{                                                                      \
+		usb_stream_event(&NAME, evt);                                  \
+	}                                                                      \
+	struct dwc_usb_ep CONCAT2(NAME, _ep_ctl) = {                           \
+		.max_packet = USB_MAX_PACKET_SIZE,                             \
+		.tx_fifo = ENDPOINT,                                           \
+		.out_pending = 0,                                              \
+		.out_expected = 0,                                             \
+		.out_data = 0,                                                 \
+		.out_databuffer = CONCAT2(NAME, _buf_rx_),                     \
+		.out_databuffer_max = RX_SIZE,                                 \
+		.rx_deferred = &CONCAT2(NAME, _deferred_rx__data),             \
+		.in_packets = 0,                                               \
+		.in_pending = 0,                                               \
+		.in_data = 0,                                                  \
+		.in_databuffer = CONCAT2(NAME, _buf_tx_),                      \
+		.in_databuffer_max = TX_SIZE,                                  \
+		.tx_deferred = &CONCAT2(NAME, _deferred_tx__data),             \
+	};                                                                     \
+	USB_DECLARE_EP(ENDPOINT, CONCAT2(NAME, _ep_tx), CONCAT2(NAME, _ep_rx), \
 		       CONCAT2(NAME, _ep_event));
 
 /* This is a short version for declaring Google serial endpoints */
-#define USB_STREAM_CONFIG(NAME,						\
-			  INTERFACE,					\
-			  INTERFACE_NAME,				\
-			  ENDPOINT,					\
-			  RX_SIZE,					\
-			  TX_SIZE,					\
-			  RX_QUEUE,					\
-			  TX_QUEUE)					\
-	USB_STREAM_CONFIG_FULL(NAME,					\
-			       INTERFACE,				\
-			       USB_CLASS_VENDOR_SPEC,			\
-			       USB_SUBCLASS_GOOGLE_SERIAL,		\
-			       USB_PROTOCOL_GOOGLE_SERIAL,		\
-			       INTERFACE_NAME,				\
-			       ENDPOINT,				\
-			       RX_SIZE,					\
-			       TX_SIZE,					\
-			       RX_QUEUE,				\
-			       TX_QUEUE)
+#define USB_STREAM_CONFIG(NAME, INTERFACE, INTERFACE_NAME, ENDPOINT, RX_SIZE, \
+			  TX_SIZE, RX_QUEUE, TX_QUEUE)                        \
+	USB_STREAM_CONFIG_FULL(NAME, INTERFACE, USB_CLASS_VENDOR_SPEC,        \
+			       USB_SUBCLASS_GOOGLE_SERIAL,                    \
+			       USB_PROTOCOL_GOOGLE_SERIAL, INTERFACE_NAME,    \
+			       ENDPOINT, RX_SIZE, TX_SIZE, RX_QUEUE, TX_QUEUE)
 
 /*
  * Handle USB and Queue request in a deferred callback.
@@ -232,6 +210,6 @@ int tx_stream_handler(struct usb_stream_config const *config);
 void usb_stream_tx(struct usb_stream_config const *config);
 void usb_stream_rx(struct usb_stream_config const *config);
 void usb_stream_event(struct usb_stream_config const *config,
-		enum usb_ep_event evt);
+		      enum usb_ep_event evt);
 
 #endif /* __CROS_EC_USB_STREAM_H */
diff --git a/chip/stm32/usb_dwc_update.h b/chip/stm32/usb_dwc_update.h
index 6d79f3aca9..1d5027a01f 100644
--- a/chip/stm32/usb_dwc_update.h
+++ b/chip/stm32/usb_dwc_update.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/stm32/usb_endpoints.c b/chip/stm32/usb_endpoints.c
index 85952a1387..57ebc86eb2 100644
--- a/chip/stm32/usb_endpoints.c
+++ b/chip/stm32/usb_endpoints.c
@@ -1,18 +1,20 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * USB endpoints/interfaces callbacks declaration
  */
 
-#include <stdint.h>
-#include <stddef.h>
-#include "config.h"
 #include "common.h"
+#include "compiler.h"
+#include "config.h"
 #include "usb_hw.h"
 
+#include <stddef.h>
+#include <stdint.h>
+
 typedef void (*xfer_func)(void);
-typedef void (*evt_func) (enum usb_ep_event evt);
+typedef void (*evt_func)(enum usb_ep_event evt);
 
 #if defined(CHIP_FAMILY_STM32F4)
 #define iface_arguments struct usb_setup_packet *req
@@ -44,18 +46,18 @@ int iface_undefined(iface_arguments)
 
 #define table(type, name, x) x
 
-#define endpoint_tx(number) \
+#define endpoint_tx(number)                                            \
 	extern void __attribute__((used, weak, alias("ep_undefined"))) \
-		ep_ ## number ## _tx(void);
-#define endpoint_rx(number) \
+	ep_##number##_tx(void);
+#define endpoint_rx(number)                                            \
 	extern void __attribute__((used, weak, alias("ep_undefined"))) \
-		ep_ ## number ## _rx(void);
-#define endpoint_evt(number) \
+	ep_##number##_rx(void);
+#define endpoint_evt(number)                                               \
 	extern void __attribute__((used, weak, alias("ep_evt_undefined"))) \
-		ep_ ## number ## _evt(enum usb_ep_event evt);
-#define interface(number) \
+	ep_##number##_evt(enum usb_ep_event evt);
+#define interface(number)                                                \
 	extern int __attribute__((used, weak, alias("iface_undefined"))) \
-		iface_ ## number ## _request(iface_arguments);
+	iface_##number##_request(iface_arguments);
 
 #define null
 
@@ -69,21 +71,30 @@ int iface_undefined(iface_arguments)
 #undef interface
 #undef null
 
+/* Disable warning that "initializer overrides prior initialization of this
+ * subobject", since we are explicitly doing this to handle the unused
+ * endpoints.
+ */
+DISABLE_CLANG_WARNING("-Winitializer-overrides")
+
 /* align function pointers on a 32-bit boundary */
-#define table(type, name, x) type name[] __attribute__((aligned(4), section(".rodata.usb_ep." #name ",\"a\" @"))) = { x };
-#define null (void*)0
+#define table(type, name, x)                                                   \
+	type name[] __attribute__((aligned(4), section(".rodata.usb_ep." #name \
+						       ",\"a\" @"))) = { x };
+#define null (void *)0
 
 #define ep_(num, suf) CONCAT3(ep_, num, suf)
 #define ep(num, suf) ep_(num, suf)
 
 #define endpoint_tx(number) \
-	[number < USB_EP_COUNT ? number : USB_EP_COUNT - 1] = ep_ ## number ## _tx,
+	[number < USB_EP_COUNT ? number : USB_EP_COUNT - 1] = ep_##number##_tx,
 #define endpoint_rx(number) \
-	[number < USB_EP_COUNT ? number : USB_EP_COUNT - 1] = ep_ ## number ## _rx,
+	[number < USB_EP_COUNT ? number : USB_EP_COUNT - 1] = ep_##number##_rx,
 #define endpoint_evt(number) \
-	[number < USB_EP_COUNT ? number : USB_EP_COUNT - 1] = ep_ ## number ## _evt,
-#define interface(number) \
-	[number < USB_IFACE_COUNT ? number : USB_IFACE_COUNT - 1] = iface_ ## number ## _request,
+	[number < USB_EP_COUNT ? number : USB_EP_COUNT - 1] = ep_##number##_evt,
+#define interface(number)                                           \
+	[number < USB_IFACE_COUNT ? number : USB_IFACE_COUNT - 1] = \
+		iface_##number##_request,
 #endif /* PASS 2 */
 
 /*
@@ -93,73 +104,40 @@ int iface_undefined(iface_arguments)
  * It all sorts out nicely
  */
 table(xfer_func, usb_ep_tx,
-	endpoint_tx(15)
-	endpoint_tx(14)
-	endpoint_tx(13)
-	endpoint_tx(12)
-	endpoint_tx(11)
-	endpoint_tx(10)
-	endpoint_tx(9)
-	endpoint_tx(8)
-	endpoint_tx(7)
-	endpoint_tx(6)
-	endpoint_tx(5)
-	endpoint_tx(4)
-	endpoint_tx(3)
-	endpoint_tx(2)
-	endpoint_tx(1)
-	endpoint_tx(0)
-)
-
-table(xfer_func, usb_ep_rx,
-	endpoint_rx(15)
-	endpoint_rx(14)
-	endpoint_rx(13)
-	endpoint_rx(12)
-	endpoint_rx(11)
-	endpoint_rx(10)
-	endpoint_rx(9)
-	endpoint_rx(8)
-	endpoint_rx(7)
-	endpoint_rx(6)
-	endpoint_rx(5)
-	endpoint_rx(4)
-	endpoint_rx(3)
-	endpoint_rx(2)
-	endpoint_rx(1)
-	endpoint_rx(0)
-)
-
-table(evt_func, usb_ep_event,
-	endpoint_evt(15)
-	endpoint_evt(14)
-	endpoint_evt(13)
-	endpoint_evt(12)
-	endpoint_evt(11)
-	endpoint_evt(10)
-	endpoint_evt(9)
-	endpoint_evt(8)
-	endpoint_evt(7)
-	endpoint_evt(6)
-	endpoint_evt(5)
-	endpoint_evt(4)
-	endpoint_evt(3)
-	endpoint_evt(2)
-	endpoint_evt(1)
-	endpoint_evt(0)
-)
+      endpoint_tx(15) endpoint_tx(14) endpoint_tx(13) endpoint_tx(12)
+	      endpoint_tx(11) endpoint_tx(10) endpoint_tx(9) endpoint_tx(8)
+		      endpoint_tx(7) endpoint_tx(6) endpoint_tx(5)
+			      endpoint_tx(4) endpoint_tx(3) endpoint_tx(2)
+				      endpoint_tx(1) endpoint_tx(0))
+
+	table(xfer_func, usb_ep_rx,
+	      endpoint_rx(15) endpoint_rx(14) endpoint_rx(13) endpoint_rx(12)
+		      endpoint_rx(11) endpoint_rx(10) endpoint_rx(9)
+			      endpoint_rx(8) endpoint_rx(7) endpoint_rx(6)
+				      endpoint_rx(5) endpoint_rx(4)
+					      endpoint_rx(3) endpoint_rx(2)
+						      endpoint_rx(1)
+							      endpoint_rx(0))
+
+		table(evt_func, usb_ep_event,
+		      endpoint_evt(15) endpoint_evt(14) endpoint_evt(
+			      13) endpoint_evt(12) endpoint_evt(11)
+			      endpoint_evt(10) endpoint_evt(9) endpoint_evt(
+				      8) endpoint_evt(7) endpoint_evt(6)
+				      endpoint_evt(5) endpoint_evt(4)
+					      endpoint_evt(3) endpoint_evt(2)
+						      endpoint_evt(1)
+							      endpoint_evt(0))
 
 #if USB_IFACE_COUNT > 0
-table(iface_func, usb_iface_request,
-	interface(7)
-	interface(6)
-	interface(5)
-	interface(4)
-	interface(3)
-	interface(2)
-	interface(1)
-	interface(0)
-)
+			table(iface_func, usb_iface_request,
+			      interface(7) interface(6) interface(5)
+				      interface(4) interface(3) interface(2)
+					      interface(1) interface(0))
+#endif
+
+#if PASS == 2
+				ENABLE_CLANG_WARNING("-Winitializer-overrides")
 #endif
 
 #if PASS == 1
diff --git a/chip/stm32/usb_gpio.c b/chip/stm32/usb_gpio.c
index 64d46875b5..a0655fd045 100644
--- a/chip/stm32/usb_gpio.c
+++ b/chip/stm32/usb_gpio.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,8 @@
 
 void usb_gpio_tx(struct usb_gpio_config const *config)
 {
-	size_t   i;
-	uint32_t mask  = 1;
+	size_t i;
+	uint32_t mask = 1;
 	uint32_t value = 0;
 
 	for (i = 0; i < config->num_gpios; ++i, mask <<= 1)
@@ -31,12 +31,12 @@ void usb_gpio_tx(struct usb_gpio_config const *config)
 
 void usb_gpio_rx(struct usb_gpio_config const *config)
 {
-	size_t   i;
-	uint32_t mask        = 1;
-	uint32_t set_mask    = ((uint32_t)(config->rx_ram[0]) |
-			        (uint32_t)(config->rx_ram[1]) << 16);
-	uint32_t clear_mask  = ((uint32_t)(config->rx_ram[2]) |
-			        (uint32_t)(config->rx_ram[3]) << 16);
+	size_t i;
+	uint32_t mask = 1;
+	uint32_t set_mask = ((uint32_t)(config->rx_ram[0]) |
+			     (uint32_t)(config->rx_ram[1]) << 16);
+	uint32_t clear_mask = ((uint32_t)(config->rx_ram[2]) |
+			       (uint32_t)(config->rx_ram[3]) << 16);
 	uint32_t ignore_mask = set_mask & clear_mask;
 
 	config->state->set_mask = set_mask;
@@ -69,10 +69,10 @@ void usb_gpio_event(struct usb_gpio_config const *config, enum usb_ep_event evt)
 
 	i = config->endpoint;
 
-	btable_ep[i].tx_addr  = usb_sram_addr(config->tx_ram);
+	btable_ep[i].tx_addr = usb_sram_addr(config->tx_ram);
 	btable_ep[i].tx_count = USB_GPIO_TX_PACKET_SIZE;
 
-	btable_ep[i].rx_addr  = usb_sram_addr(config->rx_ram);
+	btable_ep[i].rx_addr = usb_sram_addr(config->rx_ram);
 	btable_ep[i].rx_count = ((USB_GPIO_RX_PACKET_SIZE / 2) << 10);
 
 	/*
@@ -82,8 +82,8 @@ void usb_gpio_event(struct usb_gpio_config const *config, enum usb_ep_event evt)
 	config->tx_ram[0] = 0;
 	config->tx_ram[1] = 0;
 
-	STM32_USB_EP(i) = ((i <<  0) | /* Endpoint Addr*/
-			   (3 <<  4) | /* TX Valid */
-			   (0 <<  9) | /* Bulk EP */
+	STM32_USB_EP(i) = ((i << 0) | /* Endpoint Addr*/
+			   (3 << 4) | /* TX Valid */
+			   (0 << 9) | /* Bulk EP */
 			   (3 << 12)); /* RX Valid */
 }
diff --git a/chip/stm32/usb_gpio.h b/chip/stm32/usb_gpio.h
index b27c7f9485..a54801048b 100644
--- a/chip/stm32/usb_gpio.h
+++ b/chip/stm32/usb_gpio.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -55,69 +55,62 @@ struct usb_gpio_config {
  * ENDPOINT is the index of the USB bulk endpoint used for receiving and
  * transmitting bytes.
  */
-#define USB_GPIO_CONFIG(NAME,						\
-			GPIO_LIST,					\
-			INTERFACE,					\
-			ENDPOINT)					\
-	BUILD_ASSERT(ARRAY_SIZE(GPIO_LIST) <= 32);			\
-	static usb_uint CONCAT2(NAME, _ep_rx_buffer)[USB_GPIO_RX_PACKET_SIZE / 2] __usb_ram;	\
-	static usb_uint CONCAT2(NAME, _ep_tx_buffer)[USB_GPIO_TX_PACKET_SIZE / 2] __usb_ram;	\
-	struct usb_gpio_config const NAME = {				\
-		.state     = &((struct usb_gpio_state){}),		\
-		.endpoint  = ENDPOINT,					\
-		.rx_ram    = CONCAT2(NAME, _ep_rx_buffer),		\
-		.tx_ram    = CONCAT2(NAME, _ep_tx_buffer),		\
-		.gpios     = GPIO_LIST,					\
-		.num_gpios = ARRAY_SIZE(GPIO_LIST),			\
-	};								\
-	const struct usb_interface_descriptor				\
-	USB_IFACE_DESC(INTERFACE) = {					\
-		.bLength            = USB_DT_INTERFACE_SIZE,		\
-		.bDescriptorType    = USB_DT_INTERFACE,			\
-		.bInterfaceNumber   = INTERFACE,			\
-		.bAlternateSetting  = 0,				\
-		.bNumEndpoints      = 2,				\
-		.bInterfaceClass    = USB_CLASS_VENDOR_SPEC,		\
-		.bInterfaceSubClass = 0,				\
-		.bInterfaceProtocol = 0,				\
-		.iInterface         = 0,				\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 0) = {					\
-		.bLength          = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = 0x80 | ENDPOINT,			\
-		.bmAttributes     = 0x02 /* Bulk IN */,			\
-		.wMaxPacketSize   = USB_GPIO_TX_PACKET_SIZE,		\
-		.bInterval        = 10,					\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 1) = {					\
-		.bLength          = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = ENDPOINT,				\
-		.bmAttributes     = 0x02 /* Bulk OUT */,		\
-		.wMaxPacketSize   = USB_GPIO_RX_PACKET_SIZE,		\
-		.bInterval        = 0,					\
-	};								\
-	static void CONCAT2(NAME, _ep_tx)(void)				\
-	{								\
-		usb_gpio_tx(&NAME);					\
-	}								\
-	static void CONCAT2(NAME, _ep_rx)(void)				\
-	{								\
-		usb_gpio_rx(&NAME);					\
-	}								\
-	static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt)	\
-	{								\
-		usb_gpio_event(&NAME, evt);				\
-	}								\
-	USB_DECLARE_EP(ENDPOINT,					\
-		       CONCAT2(NAME, _ep_tx),				\
-		       CONCAT2(NAME, _ep_rx),				\
+#define USB_GPIO_CONFIG(NAME, GPIO_LIST, INTERFACE, ENDPOINT)                  \
+	BUILD_ASSERT(ARRAY_SIZE(GPIO_LIST) <= 32);                             \
+	static usb_uint CONCAT2(                                               \
+		NAME, _ep_rx_buffer)[USB_GPIO_RX_PACKET_SIZE / 2] __usb_ram;   \
+	static usb_uint CONCAT2(                                               \
+		NAME, _ep_tx_buffer)[USB_GPIO_TX_PACKET_SIZE / 2] __usb_ram;   \
+	struct usb_gpio_config const NAME = {                                  \
+		.state = &((struct usb_gpio_state){}),                         \
+		.endpoint = ENDPOINT,                                          \
+		.rx_ram = CONCAT2(NAME, _ep_rx_buffer),                        \
+		.tx_ram = CONCAT2(NAME, _ep_tx_buffer),                        \
+		.gpios = GPIO_LIST,                                            \
+		.num_gpios = ARRAY_SIZE(GPIO_LIST),                            \
+	};                                                                     \
+	const struct usb_interface_descriptor USB_IFACE_DESC(INTERFACE) = {    \
+		.bLength = USB_DT_INTERFACE_SIZE,                              \
+		.bDescriptorType = USB_DT_INTERFACE,                           \
+		.bInterfaceNumber = INTERFACE,                                 \
+		.bAlternateSetting = 0,                                        \
+		.bNumEndpoints = 2,                                            \
+		.bInterfaceClass = USB_CLASS_VENDOR_SPEC,                      \
+		.bInterfaceSubClass = 0,                                       \
+		.bInterfaceProtocol = 0,                                       \
+		.iInterface = 0,                                               \
+	};                                                                     \
+	const struct usb_endpoint_descriptor USB_EP_DESC(INTERFACE, 0) = {     \
+		.bLength = USB_DT_ENDPOINT_SIZE,                               \
+		.bDescriptorType = USB_DT_ENDPOINT,                            \
+		.bEndpointAddress = 0x80 | ENDPOINT,                           \
+		.bmAttributes = 0x02 /* Bulk IN */,                            \
+		.wMaxPacketSize = USB_GPIO_TX_PACKET_SIZE,                     \
+		.bInterval = 10,                                               \
+	};                                                                     \
+	const struct usb_endpoint_descriptor USB_EP_DESC(INTERFACE, 1) = {     \
+		.bLength = USB_DT_ENDPOINT_SIZE,                               \
+		.bDescriptorType = USB_DT_ENDPOINT,                            \
+		.bEndpointAddress = ENDPOINT,                                  \
+		.bmAttributes = 0x02 /* Bulk OUT */,                           \
+		.wMaxPacketSize = USB_GPIO_RX_PACKET_SIZE,                     \
+		.bInterval = 0,                                                \
+	};                                                                     \
+	static void CONCAT2(NAME, _ep_tx)(void)                                \
+	{                                                                      \
+		usb_gpio_tx(&NAME);                                            \
+	}                                                                      \
+	static void CONCAT2(NAME, _ep_rx)(void)                                \
+	{                                                                      \
+		usb_gpio_rx(&NAME);                                            \
+	}                                                                      \
+	static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt)            \
+	{                                                                      \
+		usb_gpio_event(&NAME, evt);                                    \
+	}                                                                      \
+	USB_DECLARE_EP(ENDPOINT, CONCAT2(NAME, _ep_tx), CONCAT2(NAME, _ep_rx), \
 		       CONCAT2(NAME, _ep_event))
 
-
 /*
  * These functions are used by the trampoline functions defined above to
  * connect USB endpoint events with the generic USB GPIO driver.
diff --git a/chip/stm32/usb_hid.c b/chip/stm32/usb_hid.c
index b8336fa0a0..321248c702 100644
--- a/chip/stm32/usb_hid.c
+++ b/chip/stm32/usb_hid.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,14 +13,14 @@
 #include "registers.h"
 #include "task.h"
 #include "timer.h"
-#include "util.h"
 #include "usb_descriptor.h"
-#include "usb_hw.h"
 #include "usb_hid.h"
 #include "usb_hid_hw.h"
+#include "usb_hw.h"
+#include "util.h"
 
 /* Console output macro */
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args)
 
 void hid_tx(int ep)
 {
@@ -41,17 +41,15 @@ void hid_reset(int ep, usb_uint *hid_ep_tx_buf, int tx_len,
 	for (i = 0; i < DIV_ROUND_UP(tx_len, 2); i++)
 		hid_ep_tx_buf[i] = 0;
 
-	ep_reg = (ep << 0) /* Endpoint Address */ |
-		EP_TX_VALID |
-		(3 << 9) /* interrupt EP */ |
-		EP_RX_DISAB;
+	ep_reg = (ep << 0) /* Endpoint Address */ | EP_TX_VALID |
+		 (3 << 9) /* interrupt EP */ | EP_RX_DISAB;
 
 	/* Enable RX for output reports */
 	if (hid_ep_rx_buf && rx_len > 0) {
 		btable_ep[ep].rx_addr = usb_sram_addr(hid_ep_rx_buf);
 		btable_ep[ep].rx_count = ((rx_len + 1) / 2) << 10;
 
-		ep_reg |= EP_RX_VALID;  /* RX Valid */
+		ep_reg |= EP_RX_VALID; /* RX Valid */
 	}
 
 	STM32_USB_EP(ep) = ep_reg;
@@ -73,14 +71,13 @@ static const uint8_t *report_ptr;
  *
  * @return 0 if entire report is sent, 1 if there are remaining data.
  */
-static int send_report(usb_uint *ep0_buf_tx,
-		       const uint8_t *report,
+static int send_report(usb_uint *ep0_buf_tx, const uint8_t *report,
 		       int report_size)
 {
 	int packet_size = MIN(report_size, USB_MAX_PACKET_SIZE);
 
-	memcpy_to_usbram((void *) usb_sram_addr(ep0_buf_tx),
-			 report, packet_size);
+	memcpy_to_usbram((void *)usb_sram_addr(ep0_buf_tx), report,
+			 packet_size);
 	btable_ep[0].tx_count = packet_size;
 	/* report_left != 0 if report doesn't fit in 1 packet. */
 	report_left = report_size - packet_size;
@@ -108,8 +105,8 @@ int hid_iface_request(usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx,
 		if (report_left == 0)
 			return -1;
 		report_size = MIN(USB_MAX_PACKET_SIZE, report_left);
-		memcpy_to_usbram((void *) usb_sram_addr(ep0_buf_tx),
-				 report_ptr, report_size);
+		memcpy_to_usbram((void *)usb_sram_addr(ep0_buf_tx), report_ptr,
+				 report_size);
 		btable_ep[0].tx_count = report_size;
 		report_left -= report_size;
 		report_ptr += report_size;
@@ -117,7 +114,7 @@ int hid_iface_request(usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx,
 				report_left ? 0 : EP_STATUS_OUT);
 		return report_left ? 1 : 0;
 	} else if (ep0_buf_rx[0] == (USB_DIR_IN | USB_RECIP_INTERFACE |
-					(USB_REQ_GET_DESCRIPTOR << 8))) {
+				     (USB_REQ_GET_DESCRIPTOR << 8))) {
 		if (ep0_buf_rx[1] == (USB_HID_DT_REPORT << 8)) {
 			/* Setup : HID specific : Get Report descriptor */
 			return send_report(ep0_buf_tx, report_desc,
@@ -130,10 +127,9 @@ int hid_iface_request(usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx,
 					EP_STATUS_OUT);
 			return 0;
 		}
-	} else if (ep0_buf_rx[0] == (USB_DIR_IN |
-				     USB_RECIP_INTERFACE |
-				     USB_TYPE_CLASS |
-				     (USB_HID_REQ_GET_REPORT << 8))) {
+	} else if (ep0_buf_rx[0] ==
+		   (USB_DIR_IN | USB_RECIP_INTERFACE | USB_TYPE_CLASS |
+		    (USB_HID_REQ_GET_REPORT << 8))) {
 		const uint8_t report_type = (ep0_buf_rx[1] >> 8) & 0xFF;
 		const uint8_t report_id = ep0_buf_rx[1] & 0xFF;
 		int retval;
@@ -142,9 +138,7 @@ int hid_iface_request(usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx,
 		if (!config->get_report) /* not supported */
 			return -1;
 
-		retval = config->get_report(report_id,
-					    report_type,
-					    &report_ptr,
+		retval = config->get_report(report_id, report_type, &report_ptr,
 					    &report_left);
 		if (retval)
 			return retval;
diff --git a/chip/stm32/usb_hid_hw.h b/chip/stm32/usb_hid_hw.h
index a36a66567e..5e28a801c1 100644
--- a/chip/stm32/usb_hid_hw.h
+++ b/chip/stm32/usb_hid_hw.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,6 +8,8 @@
 #ifndef __CROS_EC_USB_HID_HW_H
 #define __CROS_EC_USB_HID_HW_H
 
+#include "chip/stm32/usb_hw.h"
+
 #include <common.h>
 
 struct usb_hid_config_t {
@@ -25,10 +27,8 @@ struct usb_hid_config_t {
 	 * @param buffer_size: handler should set it to the size of returned
 	 *     buffer.
 	 */
-	int (*get_report)(uint8_t report_id,
-			  uint8_t report_type,
-			  const uint8_t **buffer_ptr,
-			  int *buffer_size);
+	int (*get_report)(uint8_t report_id, uint8_t report_type,
+			  const uint8_t **buffer_ptr, int *buffer_size);
 };
 
 /* internal callbacks for HID class drivers */
diff --git a/chip/stm32/usb_hid_keyboard.c b/chip/stm32/usb_hid_keyboard.c
index c206f9a9c5..7b40f31309 100644
--- a/chip/stm32/usb_hid_keyboard.c
+++ b/chip/stm32/usb_hid_keyboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,15 +20,15 @@
 #include "tablet_mode.h"
 #include "task.h"
 #include "timer.h"
-#include "util.h"
 #include "usb_api.h"
 #include "usb_descriptor.h"
-#include "usb_hw.h"
 #include "usb_hid.h"
 #include "usb_hid_hw.h"
+#include "usb_hw.h"
+#include "util.h"
 
 /* Console output macro */
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args)
 
 static const int keyboard_debug;
 
@@ -51,7 +51,7 @@ enum hid_protocol {
 static enum hid_protocol protocol = HID_REPORT_PROTOCOL;
 
 #if defined(CONFIG_KEYBOARD_ASSISTANT_KEY) || \
-    defined(CONFIG_KEYBOARD_TABLET_MODE_SWITCH)
+	defined(CONFIG_KEYBOARD_TABLET_MODE_SWITCH)
 #define HID_KEYBOARD_EXTRA_FIELD
 #endif
 
@@ -69,6 +69,9 @@ struct usb_hid_keyboard_report {
 	/* Assistant/tablet mode switch bitmask */
 	uint8_t extra;
 #endif
+#ifdef CONFIG_USB_HID_KEYBOARD_VIVALDI
+	uint32_t top_row; /* bitmap of top row action keys */
+#endif
 } __packed;
 
 struct usb_hid_keyboard_output_report {
@@ -105,6 +108,12 @@ struct usb_hid_keyboard_output_report {
 #define HID_KEYBOARD_MODIFIER_LOW 0xe0
 #define HID_KEYBOARD_MODIFIER_HIGH 0xe7
 
+/* Supported function key range */
+#define HID_F1 0x3a
+#define HID_F12 0x45
+#define HID_F13 0x68
+#define HID_F15 0x6a
+
 /* Special keys/switches */
 #define HID_KEYBOARD_EXTRA_LOW 0xf0
 #define HID_KEYBOARD_ASSISTANT_KEY 0xf0
@@ -117,19 +126,20 @@ struct usb_hid_keyboard_output_report {
  * Assistant key is mapped as 0xf0, but this key code is never actually send.
  */
 const uint8_t keycodes[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = {
-	{0x00, 0x00, 0xe0, 0xe3, 0xe4, HID_KEYBOARD_ASSISTANT_KEY, 0x00, 0x00},
-	{0xe3, 0x29, 0x2b, 0x35, 0x04, 0x1d, 0x1e, 0x14},
-	{0x3a, 0x3d, 0x3c, 0x3b, 0x07, 0x06, 0x20, 0x08},
-	{0x05, 0x0a, 0x17, 0x22, 0x09, 0x19, 0x21, 0x15},
-	{0x43, 0x40, 0x3f, 0x3e, 0x16, 0x1b, 0x1f, 0x1a},
-	{0x87, 0x00, 0x30, 0x00, 0x0e, 0x36, 0x25, 0x0c},
-	{0x11, 0x0b, 0x1c, 0x23, 0x0d, 0x10, 0x24, 0x18},
-	{0x00, 0x00, 0x64, 0x00, 0x00, 0xe1, 0x00, 0xe5},
-	{0x2e, 0x34, 0x2F, 0x2d, 0x33, 0x38, 0x27, 0x13},
-	{0x00, 0x42, 0x41, 0x68, 0x0f, 0x37, 0x26, 0x12},
-	{0xe6, 0x00, 0x89, 0x00, 0x31, 0x00, 0xe2, 0x00},
-	{0x00, 0x2a, 0x00, 0x31, 0x28, 0x2c, 0x51, 0x52},
-	{0x00, 0x8a, 0x00, 0x8b, 0x00, 0x00, 0x4f, 0x50},
+	{ 0x00, 0x00, 0xe0, 0xe3, 0xe4, HID_KEYBOARD_ASSISTANT_KEY, 0x00,
+	  0x00 },
+	{ 0xe3, 0x29, 0x2b, 0x35, 0x04, 0x1d, 0x1e, 0x14 },
+	{ 0x3a, 0x3d, 0x3c, 0x3b, 0x07, 0x06, 0x20, 0x08 },
+	{ 0x05, 0x0a, 0x17, 0x22, 0x09, 0x19, 0x21, 0x15 },
+	{ 0x43, 0x40, 0x3f, 0x3e, 0x16, 0x1b, 0x1f, 0x1a },
+	{ 0x87, 0x00, 0x30, 0x00, 0x0e, 0x36, 0x25, 0x0c },
+	{ 0x11, 0x0b, 0x1c, 0x23, 0x0d, 0x10, 0x24, 0x18 },
+	{ 0x00, 0x00, 0x64, 0x00, 0x00, 0xe1, 0x00, 0xe5 },
+	{ 0x2e, 0x34, 0x2F, 0x2d, 0x33, 0x38, 0x27, 0x13 },
+	{ 0x00, 0x42, 0x41, 0x68, 0x0f, 0x37, 0x26, 0x12 },
+	{ 0xe6, 0x00, 0x89, 0x00, 0x31, 0x00, 0xe2, 0x00 },
+	{ 0x00, 0x2a, 0x00, 0x31, 0x28, 0x2c, 0x51, 0x52 },
+	{ 0x00, 0x8a, 0x00, 0x8b, 0x00, 0x00, 0x4f, 0x50 },
 };
 
 /* HID descriptors */
@@ -168,34 +178,84 @@ const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_HID_KEYBOARD, 02) = {
 };
 #endif
 
-#define KEYBOARD_BASE_DESC						\
-	0x05, 0x01, /* Usage Page (Generic Desktop) */			\
-	0x09, 0x06, /* Usage (Keyboard) */				\
-	0xA1, 0x01, /* Collection (Application) */			\
-									\
-	/* Modifiers */							\
-	0x05, 0x07, /* Usage Page (Key Codes) */			\
-	0x19, HID_KEYBOARD_MODIFIER_LOW, /* Usage Minimum */		\
-	0x29, HID_KEYBOARD_MODIFIER_HIGH, /* Usage Maximum */		\
-	0x15, 0x00, /* Logical Minimum (0) */				\
-	0x25, 0x01, /* Logical Maximum (1) */				\
-	0x75, 0x01, /* Report Size (1) */				\
-	0x95, 0x08, /* Report Count (8) */				\
-	0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier byte */ \
-									\
-	0x95, 0x01, /* Report Count (1) */				\
-	0x75, 0x08, /* Report Size (8) */				\
-	0x81, 0x01, /* Input (Constant), ;Reserved byte */		\
-									\
-	/* Normal keys */						\
-	0x95, 0x06, /* Report Count (6) */				\
-	0x75, 0x08, /* Report Size (8) */				\
-	0x15, 0x00, /* Logical Minimum (0) */				\
-	0x25, 0xa4, /* Logical Maximum (164) */				\
-	0x05, 0x07, /* Usage Page (Key Codes) */			\
-	0x19, 0x00, /* Usage Minimum (0) */				\
-	0x29, 0xa4, /* Usage Maximum (164) */				\
-	0x81, 0x00, /* Input (Data, Array), ;Key arrays (6 bytes) */
+#define KEYBOARD_BASE_DESC                                                 \
+	0x05, 0x01, /* Usage Page (Generic Desktop) */                     \
+		0x09, 0x06, /* Usage (Keyboard) */                         \
+		0xA1, 0x01, /* Collection (Application) */                 \
+                                                                           \
+		/* Modifiers */                                            \
+		0x05, 0x07, /* Usage Page (Key Codes) */                   \
+		0x19, HID_KEYBOARD_MODIFIER_LOW, /* Usage Minimum */       \
+		0x29, HID_KEYBOARD_MODIFIER_HIGH, /* Usage Maximum */      \
+		0x15, 0x00, /* Logical Minimum (0) */                      \
+		0x25, 0x01, /* Logical Maximum (1) */                      \
+		0x75, 0x01, /* Report Size (1) */                          \
+		0x95, 0x08, /* Report Count (8) */                         \
+		0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier \
+			       byte */                                     \
+                                                                           \
+		0x95, 0x01, /* Report Count (1) */                         \
+		0x75, 0x08, /* Report Size (8) */                          \
+		0x81, 0x01, /* Input (Constant), ;Reserved byte */         \
+                                                                           \
+		/* Normal keys */                                          \
+		0x95, 0x06, /* Report Count (6) */                         \
+		0x75, 0x08, /* Report Size (8) */                          \
+		0x15, 0x00, /* Logical Minimum (0) */                      \
+		0x25, 0xa4, /* Logical Maximum (164) */                    \
+		0x05, 0x07, /* Usage Page (Key Codes) */                   \
+		0x19, 0x00, /* Usage Minimum (0) */                        \
+		0x29, 0xa4, /* Usage Maximum (164) */                      \
+		0x81, 0x00, /* Input (Data, Array), ;Key arrays (6 bytes) */
+
+#define KEYBOARD_TOP_ROW_DESC                                                 \
+	/* Modifiers */                                                       \
+	0x05, 0x0C, /* Consumer Page */                                       \
+		0x0A, 0x24, 0x02, /* AC Back (0x224) */                       \
+		0x0A, 0x25, 0x02, /* AC Forward (0x225) */                    \
+		0x0A, 0x27, 0x02, /* AC Refresh (0x227) */                    \
+		0x0A, 0x32, 0x02, /* AC View Toggle (0x232) */                \
+		0x0A, 0x9F, 0x02, /* AC Desktop Show All windows (0x29F) */   \
+		0x09, 0x70, /* Display Brightness Decrement (0x70) */         \
+		0x09, 0x6F, /* Display Brightness Increment (0x6F) */         \
+		0x09, 0xE2, /* Mute (0xE2) */                                 \
+		0x09, 0xEA, /* Volume Decrement (0xEA) */                     \
+		0x09, 0xE9, /* Volume Increment (0xE9) */                     \
+		0x0B, 0x46, 0x00, 0x07, 0x00, /* PrintScreen (Page 0x7, Usage \
+						 0x46) */                     \
+		0x0A, 0xD0, 0x02, /* Privacy Screen Toggle (0x2D0) */         \
+		0x09, 0x7A, /* Keyboard Brightness Decrement (0x7A) */        \
+		0x09, 0x79, /* Keyboard Brightness Increment (0x79)*/         \
+		0x09, 0xCD, /* Play / Pause (0xCD) */                         \
+		0x09, 0xB5, /* Scan Next Track (0xB5) */                      \
+		0x09, 0xB6, /* Scan Previous Track (0xB6) */                  \
+		0x09, 0x7C, /* Keyboard Backlight OOC (0x7C) */               \
+		0x0B, 0x2F, 0x00, 0x0B, 0x00, /* Phone Mute (Page 0xB, Usage  \
+						 0x2F) */                     \
+		0x09, 0x32, /* Sleep (0x32) */                                \
+		0x15, 0x00, /* Logical Minimum (0) */                         \
+		0x25, 0x01, /* Logical Maximum (1) */                         \
+		0x75, 0x01, /* Report Size (1) */                             \
+		0x95, 0x14, /* Report Count (20) */                           \
+		0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier    \
+			       byte */                                        \
+                                                                              \
+		/* 12-bit padding */                                          \
+		0x95, 0x0C, /* Report Count (12) */                           \
+		0x75, 0x01, /* Report Size (1) */                             \
+		0x81, 0x01, /* Input (Constant), ;1-bit padding */
+
+#define KEYBOARD_TOP_ROW_FEATURE_DESC                                         \
+	0x06, 0xd1, 0xff, /* Usage Page (Google) */                           \
+		0x09, 0x01, /* Usage (Top Row List) */                        \
+		0xa1, 0x02, /* Collection (Logical) */                        \
+		0x05, 0x0a, /*   Usage Page (Ordinal) */                      \
+		0x19, 0x01, /*   Usage Minimum (1) */                         \
+		0x29, CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS, /* Usage Maximum */ \
+		0x95, CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS, /* Report Count */  \
+		0x75, 0x20, /*   Report Size (32) */                          \
+		0xb1, 0x03, /*   Feature (Cnst,Var,Abs) */                    \
+		0xc0, /* End Collection */
 
 /*
  * Vendor-defined Usage Page 0xffd1:
@@ -204,60 +264,62 @@ const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_HID_KEYBOARD, 02) = {
  */
 #ifdef HID_KEYBOARD_EXTRA_FIELD
 #ifdef CONFIG_KEYBOARD_ASSISTANT_KEY
-#define KEYBOARD_ASSISTANT_KEY_DESC					\
-	0x19, 0x18, /* Usage Minimum */					\
-	0x29, 0x18, /* Usage Maximum */					\
-	0x15, 0x00, /* Logical Minimum (0) */				\
-	0x25, 0x01, /* Logical Maximum (1) */				\
-	0x75, 0x01, /* Report Size (1) */				\
-	0x95, 0x01, /* Report Count (1) */				\
-	0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier byte */
+#define KEYBOARD_ASSISTANT_KEY_DESC                                        \
+	0x19, 0x18, /* Usage Minimum */                                    \
+		0x29, 0x18, /* Usage Maximum */                            \
+		0x15, 0x00, /* Logical Minimum (0) */                      \
+		0x25, 0x01, /* Logical Maximum (1) */                      \
+		0x75, 0x01, /* Report Size (1) */                          \
+		0x95, 0x01, /* Report Count (1) */                         \
+		0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier \
+			       byte */
 #else
 /* No assistant key: just pad 1 bit. */
-#define KEYBOARD_ASSISTANT_KEY_DESC					\
-	0x95, 0x01, /* Report Count (1) */				\
-	0x75, 0x01, /* Report Size (1) */				\
-	0x81, 0x01, /* Input (Constant), ;1-bit padding */
+#define KEYBOARD_ASSISTANT_KEY_DESC               \
+	0x95, 0x01, /* Report Count (1) */        \
+		0x75, 0x01, /* Report Size (1) */ \
+		0x81, 0x01, /* Input (Constant), ;1-bit padding */
 #endif /* !CONFIG_KEYBOARD_ASSISTANT_KEY */
 
 #ifdef CONFIG_KEYBOARD_TABLET_MODE_SWITCH
-#define KEYBOARD_TABLET_MODE_SWITCH_DESC				\
-	0x19, 0x19, /* Usage Minimum */					\
-	0x29, 0x19, /* Usage Maximum */					\
-	0x15, 0x00, /* Logical Minimum (0) */				\
-	0x25, 0x01, /* Logical Maximum (1) */				\
-	0x75, 0x01, /* Report Size (1) */				\
-	0x95, 0x01, /* Report Count (1) */				\
-	0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier byte */
+#define KEYBOARD_TABLET_MODE_SWITCH_DESC                                   \
+	0x19, 0x19, /* Usage Minimum */                                    \
+		0x29, 0x19, /* Usage Maximum */                            \
+		0x15, 0x00, /* Logical Minimum (0) */                      \
+		0x25, 0x01, /* Logical Maximum (1) */                      \
+		0x75, 0x01, /* Report Size (1) */                          \
+		0x95, 0x01, /* Report Count (1) */                         \
+		0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier \
+			       byte */
 #else
 /* No tablet mode swtch: just pad 1 bit. */
-#define KEYBOARD_TABLET_MODE_SWITCH_DESC				\
-	0x95, 0x01, /* Report Count (1) */				\
-	0x75, 0x01, /* Report Size (1) */				\
-	0x81, 0x01, /* Input (Constant), ;1-bit padding */
+#define KEYBOARD_TABLET_MODE_SWITCH_DESC          \
+	0x95, 0x01, /* Report Count (1) */        \
+		0x75, 0x01, /* Report Size (1) */ \
+		0x81, 0x01, /* Input (Constant), ;1-bit padding */
 #endif /* CONFIG_KEYBOARD_TABLET_MODE_SWITCH */
 
-#define KEYBOARD_VENDOR_DESC						\
-	0x06, 0xd1, 0xff, /* Usage Page (Vendor-defined 0xffd1) */	\
-									\
-	KEYBOARD_ASSISTANT_KEY_DESC					\
-	KEYBOARD_TABLET_MODE_SWITCH_DESC				\
-									\
-	0x95, 0x01, /* Report Count (1) */				\
-	0x75, 0x06, /* Report Size (6) */				\
-	0x81, 0x01, /* Input (Constant), ;6-bit padding */
+#define KEYBOARD_VENDOR_DESC                                                 \
+	0x06, 0xd1, 0xff, /* Usage Page (Vendor-defined 0xffd1) */           \
+                                                                             \
+		KEYBOARD_ASSISTANT_KEY_DESC KEYBOARD_TABLET_MODE_SWITCH_DESC \
+                                                                             \
+		0x95,                                                        \
+		0x01, /* Report Count (1) */                                 \
+		0x75, 0x06, /* Report Size (6) */                            \
+		0x81, 0x01, /* Input (Constant), ;6-bit padding */
 #endif /* HID_KEYBOARD_EXTRA_FIELD */
 
-#define KEYBOARD_BACKLIGHT_DESC \
-	0xA1, 0x02, /* Collection (Logical) */				\
-	0x05, 0x14, /*   Usage Page (Alphanumeric Display) */		\
-	0x09, 0x46, /*   Usage (Display Brightness) */			\
-	0x95, 0x01, /*   Report Count (1) */				\
-	0x75, 0x08, /*   Report Size (8) */				\
-	0x15, 0x00, /*   Logical Minimum (0) */				\
-	0x25, 0x64, /*   Logical Maximum (100) */			\
-	0x91, 0x02, /*   Output (Data, Variable, Absolute) */		\
-	0xC0,       /* End Collection */
+#define KEYBOARD_BACKLIGHT_DESC                                       \
+	0xA1, 0x02, /* Collection (Logical) */                        \
+		0x05, 0x14, /*   Usage Page (Alphanumeric Display) */ \
+		0x09, 0x46, /*   Usage (Display Brightness) */        \
+		0x95, 0x01, /*   Report Count (1) */                  \
+		0x75, 0x08, /*   Report Size (8) */                   \
+		0x15, 0x00, /*   Logical Minimum (0) */               \
+		0x25, 0x64, /*   Logical Maximum (100) */             \
+		0x91, 0x02, /*   Output (Data, Variable, Absolute) */ \
+		0xC0, /* End Collection */
 
 /*
  * To allow dynamic detection of keyboard backlights, we define two descriptors.
@@ -270,13 +332,15 @@ static const uint8_t report_desc[] = {
 	KEYBOARD_BASE_DESC
 
 #ifdef KEYBOARD_VENDOR_DESC
-	KEYBOARD_VENDOR_DESC
+		KEYBOARD_VENDOR_DESC
 #endif
 
-	0xC0        /* End Collection */
+#ifdef CONFIG_USB_HID_KEYBOARD_VIVALDI
+			KEYBOARD_TOP_ROW_DESC KEYBOARD_TOP_ROW_FEATURE_DESC
+#endif
+	0xC0 /* End Collection */
 };
 
-
 #ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT
 
 /* HID : Report Descriptor with keyboard backlight */
@@ -285,34 +349,34 @@ static const uint8_t report_desc_with_backlight[] = {
 	KEYBOARD_BASE_DESC
 
 #ifdef KEYBOARD_VENDOR_DESC
-	KEYBOARD_VENDOR_DESC
+		KEYBOARD_VENDOR_DESC
 #endif
 
-	KEYBOARD_BACKLIGHT_DESC
+#ifdef CONFIG_USB_HID_KEYBOARD_VIVALDI
+			KEYBOARD_TOP_ROW_DESC KEYBOARD_TOP_ROW_FEATURE_DESC
+#endif
+				KEYBOARD_BACKLIGHT_DESC
 
-	0xC0        /* End Collection */
+	0xC0 /* End Collection */
 };
 
 #endif
 
 /* HID: HID Descriptor */
-const struct usb_hid_descriptor USB_CUSTOM_DESC_VAR(USB_IFACE_HID_KEYBOARD,
-						hid, hid_desc_kb) = {
+const struct usb_hid_descriptor USB_CUSTOM_DESC_VAR(USB_IFACE_HID_KEYBOARD, hid,
+						    hid_desc_kb) = {
 	.bLength = 9,
 	.bDescriptorType = USB_HID_DT_HID,
 	.bcdHID = 0x0100,
 	.bCountryCode = 0x00, /* Hardware target country */
 	.bNumDescriptors = 1,
-	.desc = {{
-		.bDescriptorType = USB_HID_DT_REPORT,
-		.wDescriptorLength = sizeof(report_desc)
-	}}
+	.desc = { { .bDescriptorType = USB_HID_DT_REPORT,
+		    .wDescriptorLength = sizeof(report_desc) } }
 };
 
 #define EP_TX_BUF_SIZE DIV_ROUND_UP(HID_KEYBOARD_REPORT_SIZE, 2)
 
 static usb_uint hid_ep_tx_buf[EP_TX_BUF_SIZE] __usb_ram;
-static volatile int hid_current_buf;
 
 static volatile int hid_ep_data_ready;
 
@@ -335,16 +399,16 @@ static void write_keyboard_report(void)
 		return;
 	}
 
-	if (deprecated_atomic_read_clear(&hid_ep_data_ready)) {
+	if (atomic_clear((atomic_t *)&hid_ep_data_ready)) {
 		/*
 		 * Endpoint is not busy, and interrupt handler did not just
 		 * send the buffer: enable TX.
 		 */
 
-		memcpy_to_usbram((void *) usb_sram_addr(hid_ep_tx_buf),
-				&report, sizeof(report));
-		STM32_TOGGLE_EP(USB_EP_HID_KEYBOARD, EP_TX_MASK,
-				EP_TX_VALID, 0);
+		memcpy_to_usbram((void *)usb_sram_addr(hid_ep_tx_buf), &report,
+				 sizeof(report));
+		STM32_TOGGLE_EP(USB_EP_HID_KEYBOARD, EP_TX_MASK, EP_TX_VALID,
+				0);
 	}
 
 	/*
@@ -360,7 +424,7 @@ static void write_keyboard_report(void)
 static void hid_keyboard_rx(void)
 {
 	struct usb_hid_keyboard_output_report report;
-	memcpy_from_usbram(&report, (void *) usb_sram_addr(hid_ep_rx_buf),
+	memcpy_from_usbram(&report, (void *)usb_sram_addr(hid_ep_rx_buf),
 			   HID_KEYBOARD_OUTPUT_REPORT_SIZE);
 
 	CPRINTF("Keyboard backlight set to %d%%\n", report.brightness);
@@ -377,10 +441,10 @@ static void hid_keyboard_tx(void)
 {
 	hid_tx(USB_EP_HID_KEYBOARD);
 	if (hid_ep_data_ready) {
-		memcpy_to_usbram((void *) usb_sram_addr(hid_ep_tx_buf),
-				&report, sizeof(report));
-		STM32_TOGGLE_EP(USB_EP_HID_KEYBOARD, EP_TX_MASK,
-				EP_TX_VALID, 0);
+		memcpy_to_usbram((void *)usb_sram_addr(hid_ep_tx_buf), &report,
+				 sizeof(report));
+		STM32_TOGGLE_EP(USB_EP_HID_KEYBOARD, EP_TX_MASK, EP_TX_VALID,
+				0);
 		hid_ep_data_ready = 0;
 	}
 
@@ -393,16 +457,14 @@ static void hid_keyboard_event(enum usb_ep_event evt)
 	if (evt == USB_EVENT_RESET) {
 		protocol = HID_REPORT_PROTOCOL;
 
-		hid_reset(USB_EP_HID_KEYBOARD,
-			  hid_ep_tx_buf,
+		hid_reset(USB_EP_HID_KEYBOARD, hid_ep_tx_buf,
 			  HID_KEYBOARD_REPORT_SIZE,
 #ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT
-			  hid_ep_rx_buf,
-			  HID_KEYBOARD_OUTPUT_REPORT_SIZE
+			  hid_ep_rx_buf, HID_KEYBOARD_OUTPUT_REPORT_SIZE
 #else
 			  NULL, 0
 #endif
-			  );
+		);
 
 		/*
 		 * Reload endpoint on reset, to make sure we report accurate
@@ -425,10 +487,80 @@ USB_DECLARE_EP(USB_EP_HID_KEYBOARD, hid_keyboard_tx,
 #endif
 	       hid_keyboard_event);
 
+struct action_key_config {
+	uint32_t mask; /* bit position of usb_hid_keyboard_report.top_row */
+	uint32_t usage; /*usage ID */
+};
+
+static const struct action_key_config action_key[] = {
+	[TK_BACK] = { .mask = BIT(0), .usage = 0x000C0224 },
+	[TK_FORWARD] = { .mask = BIT(1), .usage = 0x000C0225 },
+	[TK_REFRESH] = { .mask = BIT(2), .usage = 0x000C0227 },
+	[TK_FULLSCREEN] = { .mask = BIT(3), .usage = 0x000C0232 },
+	[TK_OVERVIEW] = { .mask = BIT(4), .usage = 0x000C029F },
+	[TK_BRIGHTNESS_DOWN] = { .mask = BIT(5), .usage = 0x000C0070 },
+	[TK_BRIGHTNESS_UP] = { .mask = BIT(6), .usage = 0x000C006F },
+	[TK_VOL_MUTE] = { .mask = BIT(7), .usage = 0x000C00E2 },
+	[TK_VOL_DOWN] = { .mask = BIT(8), .usage = 0x000C00EA },
+	[TK_VOL_UP] = { .mask = BIT(9), .usage = 0x000C00E9 },
+	[TK_SNAPSHOT] = { .mask = BIT(10), .usage = 0x00070046 },
+	[TK_PRIVACY_SCRN_TOGGLE] = { .mask = BIT(11), .usage = 0x000C02D0 },
+	[TK_KBD_BKLIGHT_DOWN] = { .mask = BIT(12), .usage = 0x000C007A },
+	[TK_KBD_BKLIGHT_UP] = { .mask = BIT(13), .usage = 0x000C0079 },
+	[TK_PLAY_PAUSE] = { .mask = BIT(14), .usage = 0x000C00CD },
+	[TK_NEXT_TRACK] = { .mask = BIT(15), .usage = 0x000C00B5 },
+	[TK_PREV_TRACK] = { .mask = BIT(16), .usage = 0x000C00B6 },
+	[TK_KBD_BKLIGHT_TOGGLE] = { .mask = BIT(17), .usage = 0x000C007C },
+	[TK_MICMUTE] = { .mask = BIT(18), .usage = 0x000B002F },
+};
+
+/* TK_* is 1-indexed, so the next bit is at ARRAY_SIZE(action_key) - 1 */
+static const int SLEEP_KEY_MASK = BIT(ARRAY_SIZE(action_key) - 1);
+
+#ifdef CONFIG_USB_HID_KEYBOARD_VIVALDI
+static uint32_t feature_report[CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS];
+
+static void hid_keyboard_feature_init(void)
+{
+	const struct ec_response_keybd_config *config =
+		board_vivaldi_keybd_config();
+
+	for (int i = 0; i < CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS; i++) {
+		int key = config->action_keys[i];
+
+		if (IN_RANGE(key, 0, ARRAY_SIZE(action_key) - 1))
+			feature_report[i] = action_key[key].usage;
+	}
+}
+DECLARE_HOOK(HOOK_INIT, hid_keyboard_feature_init, HOOK_PRIO_DEFAULT - 1);
+#endif
+
+static int hid_keyboard_get_report(uint8_t report_id, uint8_t report_type,
+				   const uint8_t **buffer_ptr, int *buffer_size)
+{
+	if (report_type == REPORT_TYPE_INPUT) {
+		*buffer_ptr = (uint8_t *)&report;
+		*buffer_size = sizeof(report);
+		return 0;
+	}
+
+#ifdef CONFIG_USB_HID_KEYBOARD_VIVALDI
+	if (report_type == REPORT_TYPE_FEATURE) {
+		*buffer_ptr = (uint8_t *)feature_report;
+		*buffer_size =
+			(sizeof(uint32_t) * CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS);
+		return 0;
+	}
+#endif
+
+	return -1;
+}
+
 static struct usb_hid_config_t hid_config_kb = {
 	.report_desc = report_desc,
 	.report_size = sizeof(report_desc),
 	.hid_desc = &hid_desc_kb,
+	.get_report = &hid_keyboard_get_report,
 };
 
 static int hid_keyboard_iface_request(usb_uint *ep0_buf_rx,
@@ -440,8 +572,9 @@ static int hid_keyboard_iface_request(usb_uint *ep0_buf_rx,
 	if (ret >= 0)
 		return ret;
 
-	if (ep0_buf_rx[0] == (USB_DIR_OUT | USB_TYPE_CLASS |
-		       USB_RECIP_INTERFACE | (USB_HID_REQ_SET_PROTOCOL << 8))) {
+	if (ep0_buf_rx[0] ==
+	    (USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_INTERFACE |
+	     (USB_HID_REQ_SET_PROTOCOL << 8))) {
 		uint16_t value = ep0_buf_rx[1];
 
 		if (value >= HID_PROTOCOL_COUNT)
@@ -452,19 +585,21 @@ static int hid_keyboard_iface_request(usb_uint *ep0_buf_rx,
 		/* Reload endpoint with appropriate tx_count. */
 		btable_ep[USB_EP_HID_KEYBOARD].tx_count =
 			(protocol == HID_BOOT_PROTOCOL) ?
-			HID_KEYBOARD_BOOT_SIZE : HID_KEYBOARD_REPORT_SIZE;
-		STM32_TOGGLE_EP(USB_EP_HID_KEYBOARD, EP_TX_MASK,
-				EP_TX_VALID, 0);
+				HID_KEYBOARD_BOOT_SIZE :
+				HID_KEYBOARD_REPORT_SIZE;
+		STM32_TOGGLE_EP(USB_EP_HID_KEYBOARD, EP_TX_MASK, EP_TX_VALID,
+				0);
 
 		btable_ep[0].tx_count = 0;
 		STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0);
 		return 0;
-	} else if (ep0_buf_rx[0] == (USB_DIR_IN | USB_TYPE_CLASS |
-		       USB_RECIP_INTERFACE | (USB_HID_REQ_GET_PROTOCOL << 8))) {
+	} else if (ep0_buf_rx[0] ==
+		   (USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_INTERFACE |
+		    (USB_HID_REQ_GET_PROTOCOL << 8))) {
 		uint8_t value = protocol;
 
-		memcpy_to_usbram((void *) usb_sram_addr(ep0_buf_tx),
-				 &value, sizeof(value));
+		memcpy_to_usbram((void *)usb_sram_addr(ep0_buf_tx), &value,
+				 sizeof(value));
 		btable_ep[0].tx_count = 1;
 		STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0);
 		return 0;
@@ -483,12 +618,44 @@ void keyboard_clear_buffer(void)
 	memset(&report, 0, sizeof(report));
 #ifdef CONFIG_KEYBOARD_TABLET_MODE_SWITCH
 	if (tablet_get_mode())
-		report.extra |= 0x01 <<	(HID_KEYBOARD_TABLET_MODE_SWITCH -
+		report.extra |= 0x01 << (HID_KEYBOARD_TABLET_MODE_SWITCH -
 					 HID_KEYBOARD_EXTRA_LOW);
 #endif
 	write_keyboard_report();
 }
 
+/*
+ * Convert a function key to the bit mask of corresponding action key.
+ *
+ * Return 0 if no need to map (not a function key or vivaldi not enabled)
+ */
+static uint32_t maybe_convert_function_key(int keycode)
+{
+	const struct ec_response_keybd_config *config =
+		board_vivaldi_keybd_config();
+	/* zero-based function key index (e.g. F1 -> 0) */
+	int index;
+
+	if (!IS_ENABLED(CONFIG_USB_HID_KEYBOARD_VIVALDI) || !config)
+		return 0;
+
+	if (IN_RANGE(keycode, HID_F1, HID_F12))
+		index = keycode - HID_F1;
+	else if (IN_RANGE(keycode, HID_F13, HID_F15))
+		index = keycode - HID_F13 + 12;
+	else
+		return 0; /* not a function key */
+
+	/* convert F13 to Sleep */
+	if (index == 12 && (config->capabilities & KEYBD_CAP_SCRNLOCK_KEY))
+		return SLEEP_KEY_MASK;
+
+	if (index >= config->num_top_row_keys ||
+	    config->action_keys[index] == TK_ABSENT)
+		return 0; /* not mapped */
+	return action_key[config->action_keys[index]].mask;
+}
+
 static void keyboard_process_queue(void)
 {
 	int i;
@@ -502,8 +669,8 @@ static void keyboard_process_queue(void)
 	if (keyboard_debug)
 		CPRINTF("Q%d (s%d ep%d hw%d)\n", queue_count(&key_queue),
 			usb_is_suspended(), hid_ep_data_ready,
-			(STM32_USB_EP(USB_EP_HID_KEYBOARD) & EP_TX_MASK)
-			== EP_TX_VALID);
+			(STM32_USB_EP(USB_EP_HID_KEYBOARD) & EP_TX_MASK) ==
+				EP_TX_VALID);
 	mutex_lock(&key_queue_mutex);
 
 	if (queue_count(&key_queue) == 0) {
@@ -541,6 +708,8 @@ static void keyboard_process_queue(void)
 	 * dropping keys that are too old.
 	 */
 	while (queue_count(&key_queue) > 0) {
+		uint32_t action_key_mask;
+
 		queue_peek_units(&key_queue, &ev, 0, 1);
 		if (keyboard_debug)
 			CPRINTF(" =%02x/%d %d %d\n", ev.keycode, ev.keycode,
@@ -552,8 +721,17 @@ static void keyboard_process_queue(void)
 
 		queue_advance_head(&key_queue, 1);
 
-		if (ev.keycode >= HID_KEYBOARD_EXTRA_LOW &&
-		    ev.keycode <= HID_KEYBOARD_EXTRA_HIGH) {
+		action_key_mask = maybe_convert_function_key(ev.keycode);
+		if (action_key_mask) {
+#ifdef CONFIG_USB_HID_KEYBOARD_VIVALDI
+			if (ev.pressed)
+				report.top_row |= action_key_mask;
+			else
+				report.top_row &= ~action_key_mask;
+			valid = 1;
+#endif
+		} else if (ev.keycode >= HID_KEYBOARD_EXTRA_LOW &&
+			   ev.keycode <= HID_KEYBOARD_EXTRA_HIGH) {
 #ifdef HID_KEYBOARD_EXTRA_FIELD
 			mask = 0x01 << (ev.keycode - HID_KEYBOARD_EXTRA_LOW);
 			if (ev.pressed)
@@ -563,7 +741,7 @@ static void keyboard_process_queue(void)
 			valid = 1;
 #endif
 		} else if (ev.keycode >= HID_KEYBOARD_MODIFIER_LOW &&
-		    ev.keycode <= HID_KEYBOARD_MODIFIER_HIGH) {
+			   ev.keycode <= HID_KEYBOARD_MODIFIER_HIGH) {
 			mask = 0x01 << (ev.keycode - HID_KEYBOARD_MODIFIER_LOW);
 			if (ev.pressed)
 				report.modifiers |= mask;
@@ -630,7 +808,7 @@ static void tablet_mode_change(void)
 }
 DECLARE_HOOK(HOOK_TABLET_MODE_CHANGE, tablet_mode_change, HOOK_PRIO_DEFAULT);
 /* Run after tablet_mode_init. */
-DECLARE_HOOK(HOOK_INIT, tablet_mode_change, HOOK_PRIO_DEFAULT+1);
+DECLARE_HOOK(HOOK_INIT, tablet_mode_change, HOOK_PRIO_DEFAULT + 1);
 #endif
 
 void keyboard_state_changed(int row, int col, int is_pressed)
@@ -646,7 +824,8 @@ void keyboard_state_changed(int row, int col, int is_pressed)
 }
 
 void clear_typematic_key(void)
-{ }
+{
+}
 
 #ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT
 void usb_hid_keyboard_init(void)
@@ -656,8 +835,8 @@ void usb_hid_keyboard_init(void)
 		hid_config_kb.report_size = sizeof(report_desc_with_backlight);
 
 		set_descriptor_patch(USB_DESC_KEYBOARD_BACKLIGHT,
-			&hid_desc_kb.desc[0].wDescriptorLength,
-			sizeof(report_desc_with_backlight));
+				     &hid_desc_kb.desc[0].wDescriptorLength,
+				     sizeof(report_desc_with_backlight));
 	}
 }
 /* This needs to happen before usb_init (HOOK_PRIO_DEFAULT) */
diff --git a/chip/stm32/usb_hid_touchpad.c b/chip/stm32/usb_hid_touchpad.c
index 0ead660432..8eb5ee95dc 100644
--- a/chip/stm32/usb_hid_touchpad.c
+++ b/chip/stm32/usb_hid_touchpad.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,25 +15,25 @@
 #include "registers.h"
 #include "task.h"
 #include "timer.h"
-#include "util.h"
 #include "usb_api.h"
 #include "usb_descriptor.h"
-#include "usb_hw.h"
 #include "usb_hid.h"
 #include "usb_hid_hw.h"
 #include "usb_hid_touchpad.h"
+#include "usb_hw.h"
+#include "util.h"
 
 /* Console output macro */
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USB, format, ##args)
 
 static const int touchpad_debug;
 
-static struct queue const report_queue = QUEUE_NULL(8,
-						struct usb_hid_touchpad_report);
+static struct queue const report_queue =
+	QUEUE_NULL(8, struct usb_hid_touchpad_report);
 static struct mutex report_queue_mutex;
 
-#define HID_TOUCHPAD_REPORT_SIZE  sizeof(struct usb_hid_touchpad_report)
+#define HID_TOUCHPAD_REPORT_SIZE sizeof(struct usb_hid_touchpad_report)
 
 /*
  * Touchpad EP interval: Make sure this value is smaller than the typical
@@ -65,58 +65,63 @@ const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_HID_TOUCHPAD, 81) = {
 	.bInterval = HID_TOUCHPAD_EP_INTERVAL_MS /* polling interval */
 };
 
-#define FINGER_USAGE \
-	0x05, 0x0D,        /*   Usage Page (Digitizer) */ \
-	0x09, 0x22,        /*   Usage (Finger) */ \
-	0xA1, 0x02,        /*   Collection (Logical) */ \
-	0x09, 0x47,        /*     Usage (Confidence) */ \
-	0x09, 0x42,        /*     Usage (Tip Switch) */ \
-	0x09, 0x32,        /*     Usage (In Range) */ \
-	0x15, 0x00,        /*     Logical Minimum (0) */ \
-	0x25, 0x01,        /*     Logical Maximum (1) */ \
-	0x75, 0x01,        /*     Report Size (1) */ \
-	0x95, 0x03,        /*     Report Count (3) */ \
-	0x81, 0x02,        /*     Input (Data,Var,Abs) */ \
-	0x09, 0x51,        /*     Usage (0x51) Contact identifier */ \
-	0x75, 0x04,        /*     Report Size (4) */ \
-	0x95, 0x01,        /*     Report Count (1) */ \
-	0x25, 0x0F,        /*     Logical Maximum (15) */ \
-	0x81, 0x02,        /*     Input (Data,Var,Abs) */ \
-	0x05, 0x0D,        /*     Usage Page (Digitizer) */ \
-			   /*     Logical Maximum of Pressure */ \
-	0x26, (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE & 0xFF), \
-	      (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE >> 8), \
-	0x75, 0x09,        /*     Report Size (9) */ \
-	0x09, 0x30,        /*     Usage (Tip pressure) */ \
-	0x81, 0x02,        /*     Input (Data,Var,Abs) */ \
-	0x26, 0xFF, 0x0F,  /*     Logical Maximum (4095) */ \
-	0x75, 0x0C,        /*     Report Size (12) */ \
-	0x09, 0x48,        /*     Usage (WIDTH) */ \
-	0x81, 0x02,        /*     Input (Data,Var,Abs) */ \
-	0x09, 0x49,        /*     Usage (HEIGHT) */ \
-	0x81, 0x02,        /*     Input (Data,Var,Abs) */ \
-	0x05, 0x01,        /*     Usage Page (Generic Desktop Ctrls) */ \
-	0x75, 0x0C,        /*     Report Size (12) */ \
-	0x55, 0x0E,        /*     Unit Exponent (-2) */ \
-	0x65, 0x11,        /*     Unit (System: SI Linear, Length: cm) */ \
-	0x09, 0x30,        /*     Usage (X) */ \
-	0x35, 0x00,        /*     Physical Minimum (0) */ \
-	0x26, (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X & 0xff), \
-	      (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X >> 8), \
-	                   /*     Logical Maximum */ \
-	0x46, (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X & 0xff), \
-	      (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X >> 8), \
-	                   /*     Physical Maximum (tenth of mm) */ \
-	0x81, 0x02,        /*     Input (Data,Var,Abs) */ \
-	0x26, (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y & 0xff), \
-	      (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y >> 8), \
-	                   /*     Logical Maximum */ \
-	0x46, (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y & 0xff), \
-	      (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y >> 8), \
-	                   /*     Physical Maximum (tenth of mm) */ \
-	0x09, 0x31,        /*     Usage (Y) */ \
-	0x81, 0x02,        /*     Input (Data,Var,Abs) */ \
-	0xC0               /*   End Collection */
+#define FINGER_USAGE                                                           \
+	0x05, 0x0D, /*   Usage Page (Digitizer) */                             \
+		0x09, 0x22, /*   Usage (Finger) */                             \
+		0xA1, 0x02, /*   Collection (Logical) */                       \
+		0x09, 0x47, /*     Usage (Confidence) */                       \
+		0x09, 0x42, /*     Usage (Tip Switch) */                       \
+		0x09, 0x32, /*     Usage (In Range) */                         \
+		0x15, 0x00, /*     Logical Minimum (0) */                      \
+		0x25, 0x01, /*     Logical Maximum (1) */                      \
+		0x75, 0x01, /*     Report Size (1) */                          \
+		0x95, 0x03, /*     Report Count (3) */                         \
+		0x81, 0x02, /*     Input (Data,Var,Abs) */                     \
+		0x09, 0x51, /*     Usage (0x51) Contact identifier */          \
+		0x75, 0x04, /*     Report Size (4) */                          \
+		0x95, 0x01, /*     Report Count (1) */                         \
+		0x25, 0x0F, /*     Logical Maximum (15) */                     \
+		0x81, 0x02, /*     Input (Data,Var,Abs) */                     \
+		0x05, 0x0D, /*     Usage Page (Digitizer) */ /*     Logical    \
+								Maximum of     \
+								Pressure */    \
+		0x26, (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE & 0xFF),   \
+		(CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE >> 8), 0x75,     \
+		0x09, /*     Report Size (9) */                                \
+		0x09, 0x30, /*     Usage (Tip pressure) */                     \
+		0x81, 0x02, /*     Input (Data,Var,Abs) */                     \
+		0x26, 0xFF, 0x0F, /*     Logical Maximum (4095) */             \
+		0x75, 0x0C, /*     Report Size (12) */                         \
+		0x09, 0x48, /*     Usage (WIDTH) */                            \
+		0x81, 0x02, /*     Input (Data,Var,Abs) */                     \
+		0x09, 0x49, /*     Usage (HEIGHT) */                           \
+		0x81, 0x02, /*     Input (Data,Var,Abs) */                     \
+		0x05, 0x01, /*     Usage Page (Generic Desktop Ctrls) */       \
+		0x75, 0x0C, /*     Report Size (12) */                         \
+		0x55, 0x0E, /*     Unit Exponent (-2) */                       \
+		0x65, 0x11, /*     Unit (System: SI Linear, Length: cm) */     \
+		0x09, 0x30, /*     Usage (X) */                                \
+		0x35, 0x00, /*     Physical Minimum (0) */                     \
+		0x26, (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X & 0xff),          \
+		(CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X >> 8), /*     Logical   \
+								 Maximum */    \
+		0x46, (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X & 0xff),         \
+		(CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X >> 8), /*     Physical \
+								  Maximum      \
+								  (tenth of    \
+								  mm) */       \
+		0x81, 0x02, /*     Input (Data,Var,Abs) */                     \
+		0x26, (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y & 0xff),          \
+		(CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y >> 8), /*     Logical   \
+								 Maximum */    \
+		0x46, (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y & 0xff),         \
+		(CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y >> 8), /*     Physical \
+								  Maximum      \
+								  (tenth of    \
+								  mm) */       \
+		0x09, 0x31, /*     Usage (Y) */                                \
+		0x81, 0x02, /*     Input (Data,Var,Abs) */                     \
+		0xC0 /*   End Collection */
 
 /*
  * HID: Report Descriptor
@@ -125,10 +130,10 @@ const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_HID_TOUCHPAD, 81) = {
  */
 static const uint8_t report_desc[] = {
 	/* Touchpad Collection */
-	0x05, 0x0D,                    /* Usage Page (Digitizer) */
-	0x09, 0x05,                    /* Usage (Touch Pad) */
-	0xA1, 0x01,                    /* Collection (Application) */
-	0x85, REPORT_ID_TOUCHPAD,      /*   Report ID (1, Touch) */
+	0x05, 0x0D, /* Usage Page (Digitizer) */
+	0x09, 0x05, /* Usage (Touch Pad) */
+	0xA1, 0x01, /* Collection (Application) */
+	0x85, REPORT_ID_TOUCHPAD, /*   Report ID (1, Touch) */
 	/* Finger 0 */
 	FINGER_USAGE,
 	/* Finger 1 */
@@ -140,52 +145,52 @@ static const uint8_t report_desc[] = {
 	/* Finger 4 */
 	FINGER_USAGE,
 	/* Contact count */
-	0x05, 0x0D,                    /*   Usage Page (Digitizer) */
-	0x09, 0x54,                    /*   Usage (Contact count) */
-	0x25, MAX_FINGERS,             /*   Logical Maximum (MAX_FINGERS) */
-	0x75, 0x07,                    /*   Report Size (7) */
-	0x95, 0x01,                    /*   Report Count (1) */
-	0x81, 0x02,                    /*   Input (Data,Var,Abs) */
+	0x05, 0x0D, /*   Usage Page (Digitizer) */
+	0x09, 0x54, /*   Usage (Contact count) */
+	0x25, MAX_FINGERS, /*   Logical Maximum (MAX_FINGERS) */
+	0x75, 0x07, /*   Report Size (7) */
+	0x95, 0x01, /*   Report Count (1) */
+	0x81, 0x02, /*   Input (Data,Var,Abs) */
 	/* Button */
-	0x05, 0x01,                    /*   Usage Page(Generic Desktop Ctrls) */
-	0x05, 0x09,                    /*   Usage (Button) */
-	0x19, 0x01,                    /*   Usage Minimum (0x01) */
-	0x29, 0x01,                    /*   Usage Maximum (0x01) */
-	0x15, 0x00,                    /*   Logical Minimum (0) */
-	0x25, 0x01,                    /*   Logical Maximum (1) */
-	0x75, 0x01,                    /*   Report Size (1) */
-	0x95, 0x01,                    /*   Report Count (1) */
-	0x81, 0x02,                    /*   Input (Data,Var,Abs) */
+	0x05, 0x01, /*   Usage Page(Generic Desktop Ctrls) */
+	0x05, 0x09, /*   Usage (Button) */
+	0x19, 0x01, /*   Usage Minimum (0x01) */
+	0x29, 0x01, /*   Usage Maximum (0x01) */
+	0x15, 0x00, /*   Logical Minimum (0) */
+	0x25, 0x01, /*   Logical Maximum (1) */
+	0x75, 0x01, /*   Report Size (1) */
+	0x95, 0x01, /*   Report Count (1) */
+	0x81, 0x02, /*   Input (Data,Var,Abs) */
 	/* Timestamp */
-	0x05, 0x0D,                    /*   Usage Page (Digitizer) */
-	0x55, 0x0C,                    /*   Unit Exponent (-4) */
-	0x66, 0x01, 0x10,              /*   Unit (Seconds) */
-	0x47, 0xFF, 0xFF, 0x00, 0x00,  /*   Physical Maximum (65535) */
-	0x27, 0xFF, 0xFF, 0x00, 0x00,  /*   Logical Maximum (65535) */
-	0x75, 0x10,                    /*   Report Size (16) */
-	0x95, 0x01,                    /*   Report Count (1) */
-	0x09, 0x56,                    /*   Usage (0x56, Relative Scan Time) */
-	0x81, 0x02,                    /*   Input (Data,Var,Abs) */
-
-	0x85, REPORT_ID_DEVICE_CAPS,   /*   Report ID (Device Capabilities) */
-	0x09, 0x55,                    /*   Usage (Contact Count Maximum) */
-	0x09, 0x59,                    /*   Usage (Pad Type) */
-	0x25, 0x0F,                    /*   Logical Maximum (15) */
-	0x75, 0x08,                    /*   Report Size (8) */
-	0x95, 0x02,                    /*   Report Count (2) */
-	0xB1, 0x02,                    /*   Feature (Data,Var,Abs) */
+	0x05, 0x0D, /*   Usage Page (Digitizer) */
+	0x55, 0x0C, /*   Unit Exponent (-4) */
+	0x66, 0x01, 0x10, /*   Unit (Seconds) */
+	0x47, 0xFF, 0xFF, 0x00, 0x00, /*   Physical Maximum (65535) */
+	0x27, 0xFF, 0xFF, 0x00, 0x00, /*   Logical Maximum (65535) */
+	0x75, 0x10, /*   Report Size (16) */
+	0x95, 0x01, /*   Report Count (1) */
+	0x09, 0x56, /*   Usage (0x56, Relative Scan Time) */
+	0x81, 0x02, /*   Input (Data,Var,Abs) */
+
+	0x85, REPORT_ID_DEVICE_CAPS, /*   Report ID (Device Capabilities) */
+	0x09, 0x55, /*   Usage (Contact Count Maximum) */
+	0x09, 0x59, /*   Usage (Pad Type) */
+	0x25, 0x0F, /*   Logical Maximum (15) */
+	0x75, 0x08, /*   Report Size (8) */
+	0x95, 0x02, /*   Report Count (2) */
+	0xB1, 0x02, /*   Feature (Data,Var,Abs) */
 
 	/* Page 0xFF, usage 0xC5 is device certificate. */
-	0x06, 0x00, 0xFF,              /*   Usage Page (Vendor Defined) */
-	0x85, REPORT_ID_DEVICE_CERT,   /*   Report ID (Device Certification) */
-	0x09, 0xC5,                    /*   Usage (Vendor Usage 0xC5) */
-	0x15, 0x00,                    /*   Logical Minimum (0) */
-	0x26, 0xFF, 0x00,              /*   Logical Maximum (255) */
-	0x75, 0x08,                    /*   Report Size (8) */
-	0x96, 0x00, 0x01,              /*   Report Count (256) */
-	0xB1, 0x02,                    /*   Feature (Data,Var,Abs) */
-
-	0xC0,                          /* End Collection */
+	0x06, 0x00, 0xFF, /*   Usage Page (Vendor Defined) */
+	0x85, REPORT_ID_DEVICE_CERT, /*   Report ID (Device Certification) */
+	0x09, 0xC5, /*   Usage (Vendor Usage 0xC5) */
+	0x15, 0x00, /*   Logical Minimum (0) */
+	0x26, 0xFF, 0x00, /*   Logical Maximum (255) */
+	0x75, 0x08, /*   Report Size (8) */
+	0x96, 0x00, 0x01, /*   Report Count (256) */
+	0xB1, 0x02, /*   Feature (Data,Var,Abs) */
+
+	0xC0, /* End Collection */
 };
 
 /* A 256-byte default blob for the 'device certification status' feature report.
@@ -195,59 +200,281 @@ static const uint8_t report_desc[] = {
 static const uint8_t device_cert_response[] = {
 	REPORT_ID_DEVICE_CERT,
 
-	0xFC, 0x28, 0xFE, 0x84, 0x40, 0xCB, 0x9A, 0x87,
-	0x0D, 0xBE, 0x57, 0x3C, 0xB6, 0x70, 0x09, 0x88,
-	0x07, 0x97, 0x2D, 0x2B, 0xE3, 0x38, 0x34, 0xB6,
-	0x6C, 0xED, 0xB0, 0xF7, 0xE5, 0x9C, 0xF6, 0xC2,
-	0x2E, 0x84, 0x1B, 0xE8, 0xB4, 0x51, 0x78, 0x43,
-	0x1F, 0x28, 0x4B, 0x7C, 0x2D, 0x53, 0xAF, 0xFC,
-	0x47, 0x70, 0x1B, 0x59, 0x6F, 0x74, 0x43, 0xC4,
-	0xF3, 0x47, 0x18, 0x53, 0x1A, 0xA2, 0xA1, 0x71,
-	0xC7, 0x95, 0x0E, 0x31, 0x55, 0x21, 0xD3, 0xB5,
-	0x1E, 0xE9, 0x0C, 0xBA, 0xEC, 0xB8, 0x89, 0x19,
-	0x3E, 0xB3, 0xAF, 0x75, 0x81, 0x9D, 0x53, 0xB9,
-	0x41, 0x57, 0xF4, 0x6D, 0x39, 0x25, 0x29, 0x7C,
-	0x87, 0xD9, 0xB4, 0x98, 0x45, 0x7D, 0xA7, 0x26,
-	0x9C, 0x65, 0x3B, 0x85, 0x68, 0x89, 0xD7, 0x3B,
-	0xBD, 0xFF, 0x14, 0x67, 0xF2, 0x2B, 0xF0, 0x2A,
-	0x41, 0x54, 0xF0, 0xFD, 0x2C, 0x66, 0x7C, 0xF8,
-	0xC0, 0x8F, 0x33, 0x13, 0x03, 0xF1, 0xD3, 0xC1,
-	0x0B, 0x89, 0xD9, 0x1B, 0x62, 0xCD, 0x51, 0xB7,
-	0x80, 0xB8, 0xAF, 0x3A, 0x10, 0xC1, 0x8A, 0x5B,
-	0xE8, 0x8A, 0x56, 0xF0, 0x8C, 0xAA, 0xFA, 0x35,
-	0xE9, 0x42, 0xC4, 0xD8, 0x55, 0xC3, 0x38, 0xCC,
-	0x2B, 0x53, 0x5C, 0x69, 0x52, 0xD5, 0xC8, 0x73,
-	0x02, 0x38, 0x7C, 0x73, 0xB6, 0x41, 0xE7, 0xFF,
-	0x05, 0xD8, 0x2B, 0x79, 0x9A, 0xE2, 0x34, 0x60,
-	0x8F, 0xA3, 0x32, 0x1F, 0x09, 0x78, 0x62, 0xBC,
-	0x80, 0xE3, 0x0F, 0xBD, 0x65, 0x20, 0x08, 0x13,
-	0xC1, 0xE2, 0xEE, 0x53, 0x2D, 0x86, 0x7E, 0xA7,
-	0x5A, 0xC5, 0xD3, 0x7D, 0x98, 0xBE, 0x31, 0x48,
-	0x1F, 0xFB, 0xDA, 0xAF, 0xA2, 0xA8, 0x6A, 0x89,
-	0xD6, 0xBF, 0xF2, 0xD3, 0x32, 0x2A, 0x9A, 0xE4,
-	0xCF, 0x17, 0xB7, 0xB8, 0xF4, 0xE1, 0x33, 0x08,
-	0x24, 0x8B, 0xC4, 0x43, 0xA5, 0xE5, 0x24, 0xC2,
+	0xFC,
+	0x28,
+	0xFE,
+	0x84,
+	0x40,
+	0xCB,
+	0x9A,
+	0x87,
+	0x0D,
+	0xBE,
+	0x57,
+	0x3C,
+	0xB6,
+	0x70,
+	0x09,
+	0x88,
+	0x07,
+	0x97,
+	0x2D,
+	0x2B,
+	0xE3,
+	0x38,
+	0x34,
+	0xB6,
+	0x6C,
+	0xED,
+	0xB0,
+	0xF7,
+	0xE5,
+	0x9C,
+	0xF6,
+	0xC2,
+	0x2E,
+	0x84,
+	0x1B,
+	0xE8,
+	0xB4,
+	0x51,
+	0x78,
+	0x43,
+	0x1F,
+	0x28,
+	0x4B,
+	0x7C,
+	0x2D,
+	0x53,
+	0xAF,
+	0xFC,
+	0x47,
+	0x70,
+	0x1B,
+	0x59,
+	0x6F,
+	0x74,
+	0x43,
+	0xC4,
+	0xF3,
+	0x47,
+	0x18,
+	0x53,
+	0x1A,
+	0xA2,
+	0xA1,
+	0x71,
+	0xC7,
+	0x95,
+	0x0E,
+	0x31,
+	0x55,
+	0x21,
+	0xD3,
+	0xB5,
+	0x1E,
+	0xE9,
+	0x0C,
+	0xBA,
+	0xEC,
+	0xB8,
+	0x89,
+	0x19,
+	0x3E,
+	0xB3,
+	0xAF,
+	0x75,
+	0x81,
+	0x9D,
+	0x53,
+	0xB9,
+	0x41,
+	0x57,
+	0xF4,
+	0x6D,
+	0x39,
+	0x25,
+	0x29,
+	0x7C,
+	0x87,
+	0xD9,
+	0xB4,
+	0x98,
+	0x45,
+	0x7D,
+	0xA7,
+	0x26,
+	0x9C,
+	0x65,
+	0x3B,
+	0x85,
+	0x68,
+	0x89,
+	0xD7,
+	0x3B,
+	0xBD,
+	0xFF,
+	0x14,
+	0x67,
+	0xF2,
+	0x2B,
+	0xF0,
+	0x2A,
+	0x41,
+	0x54,
+	0xF0,
+	0xFD,
+	0x2C,
+	0x66,
+	0x7C,
+	0xF8,
+	0xC0,
+	0x8F,
+	0x33,
+	0x13,
+	0x03,
+	0xF1,
+	0xD3,
+	0xC1,
+	0x0B,
+	0x89,
+	0xD9,
+	0x1B,
+	0x62,
+	0xCD,
+	0x51,
+	0xB7,
+	0x80,
+	0xB8,
+	0xAF,
+	0x3A,
+	0x10,
+	0xC1,
+	0x8A,
+	0x5B,
+	0xE8,
+	0x8A,
+	0x56,
+	0xF0,
+	0x8C,
+	0xAA,
+	0xFA,
+	0x35,
+	0xE9,
+	0x42,
+	0xC4,
+	0xD8,
+	0x55,
+	0xC3,
+	0x38,
+	0xCC,
+	0x2B,
+	0x53,
+	0x5C,
+	0x69,
+	0x52,
+	0xD5,
+	0xC8,
+	0x73,
+	0x02,
+	0x38,
+	0x7C,
+	0x73,
+	0xB6,
+	0x41,
+	0xE7,
+	0xFF,
+	0x05,
+	0xD8,
+	0x2B,
+	0x79,
+	0x9A,
+	0xE2,
+	0x34,
+	0x60,
+	0x8F,
+	0xA3,
+	0x32,
+	0x1F,
+	0x09,
+	0x78,
+	0x62,
+	0xBC,
+	0x80,
+	0xE3,
+	0x0F,
+	0xBD,
+	0x65,
+	0x20,
+	0x08,
+	0x13,
+	0xC1,
+	0xE2,
+	0xEE,
+	0x53,
+	0x2D,
+	0x86,
+	0x7E,
+	0xA7,
+	0x5A,
+	0xC5,
+	0xD3,
+	0x7D,
+	0x98,
+	0xBE,
+	0x31,
+	0x48,
+	0x1F,
+	0xFB,
+	0xDA,
+	0xAF,
+	0xA2,
+	0xA8,
+	0x6A,
+	0x89,
+	0xD6,
+	0xBF,
+	0xF2,
+	0xD3,
+	0x32,
+	0x2A,
+	0x9A,
+	0xE4,
+	0xCF,
+	0x17,
+	0xB7,
+	0xB8,
+	0xF4,
+	0xE1,
+	0x33,
+	0x08,
+	0x24,
+	0x8B,
+	0xC4,
+	0x43,
+	0xA5,
+	0xE5,
+	0x24,
+	0xC2,
 };
 
 /* Device capabilities feature report. */
 static const uint8_t device_caps_response[] = {
 	REPORT_ID_DEVICE_CAPS,
 
-	MAX_FINGERS,            /* Contact Count Maximum */
-	0x00,                   /* Pad Type: Depressible click-pad */
+	MAX_FINGERS, /* Contact Count Maximum */
+	0x00, /* Pad Type: Depressible click-pad */
 };
 
-const struct usb_hid_descriptor USB_CUSTOM_DESC_VAR(USB_IFACE_HID_TOUCHPAD,
-						hid, hid_desc_tp) = {
+const struct usb_hid_descriptor USB_CUSTOM_DESC_VAR(USB_IFACE_HID_TOUCHPAD, hid,
+						    hid_desc_tp) = {
 	.bLength = 9,
 	.bDescriptorType = USB_HID_DT_HID,
 	.bcdHID = 0x0100,
 	.bCountryCode = 0x00, /* Hardware target country */
 	.bNumDescriptors = 1,
-	.desc = {{
-		.bDescriptorType = USB_HID_DT_REPORT,
-		.wDescriptorLength = sizeof(report_desc)
-	}}
+	.desc = { { .bDescriptorType = USB_HID_DT_REPORT,
+		    .wDescriptorLength = sizeof(report_desc) } }
 };
 
 static usb_uint hid_ep_buf[DIV_ROUND_UP(HID_TOUCHPAD_REPORT_SIZE, 2)] __usb_ram;
@@ -258,8 +485,8 @@ static usb_uint hid_ep_buf[DIV_ROUND_UP(HID_TOUCHPAD_REPORT_SIZE, 2)] __usb_ram;
  */
 static void write_touchpad_report(struct usb_hid_touchpad_report *report)
 {
-	memcpy_to_usbram((void *) usb_sram_addr(hid_ep_buf),
-			 report, sizeof(*report));
+	memcpy_to_usbram((void *)usb_sram_addr(hid_ep_buf), report,
+			 sizeof(*report));
 	/* enable TX */
 	STM32_TOGGLE_EP(USB_EP_HID_TOUCHPAD, EP_TX_MASK, EP_TX_VALID, 0);
 
@@ -289,8 +516,7 @@ static void hid_touchpad_process_queue(void)
 	now = __hw_clock_source_read() / USB_HID_TOUCHPAD_TIMESTAMP_UNIT;
 
 	if (usb_is_suspended() ||
-			(STM32_USB_EP(USB_EP_HID_TOUCHPAD) & EP_TX_MASK)
-				== EP_TX_VALID) {
+	    (STM32_USB_EP(USB_EP_HID_TOUCHPAD) & EP_TX_MASK) == EP_TX_VALID) {
 		usb_wake();
 
 		/* Let's trim old events from the queue, if any. */
@@ -307,8 +533,8 @@ static void hid_touchpad_process_queue(void)
 
 		queue_peek_units(&report_queue, &report, 0, 1);
 
-		delta = (int)((uint16_t)(now - report.timestamp))
-				* USB_HID_TOUCHPAD_TIMESTAMP_UNIT;
+		delta = (int)((uint16_t)(now - report.timestamp)) *
+			USB_HID_TOUCHPAD_TIMESTAMP_UNIT;
 
 		if (touchpad_debug)
 			CPRINTS("evt t=%d d=%d", report.timestamp, delta);
@@ -345,8 +571,8 @@ void set_touchpad_report(struct usb_hid_touchpad_report *report)
 
 	/* USB/EP ready and nothing in queue, just write the report. */
 	if (!usb_is_suspended() &&
-	    (STM32_USB_EP(USB_EP_HID_TOUCHPAD) & EP_TX_MASK) != EP_TX_VALID
-	    && queue_count(&report_queue) == 0) {
+	    (STM32_USB_EP(USB_EP_HID_TOUCHPAD) & EP_TX_MASK) != EP_TX_VALID &&
+	    queue_count(&report_queue) == 0) {
 		write_touchpad_report(report);
 		mutex_unlock(&report_queue_mutex);
 		return;
@@ -385,7 +611,7 @@ static void hid_touchpad_event(enum usb_ep_event evt)
 		hid_reset(USB_EP_HID_TOUCHPAD, hid_ep_buf,
 			  HID_TOUCHPAD_REPORT_SIZE, NULL, 0);
 	else if (evt == USB_EVENT_DEVICE_RESUME &&
-			queue_count(&report_queue) > 0)
+		 queue_count(&report_queue) > 0)
 		hook_call_deferred(&hid_touchpad_process_queue_data, 0);
 }
 
@@ -393,8 +619,7 @@ USB_DECLARE_EP(USB_EP_HID_TOUCHPAD, hid_touchpad_tx, hid_touchpad_tx,
 	       hid_touchpad_event);
 
 static int get_report(uint8_t report_id, uint8_t report_type,
-		      const uint8_t **buffer_ptr,
-		      int *buffer_size)
+		      const uint8_t **buffer_ptr, int *buffer_size)
 {
 	switch (report_id) {
 	case REPORT_ID_DEVICE_CAPS:
diff --git a/chip/stm32/usb_hw.h b/chip/stm32/usb_hw.h
index 0c75322a7d..511cd9c75a 100644
--- a/chip/stm32/usb_hw.h
+++ b/chip/stm32/usb_hw.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,12 +19,11 @@ enum usb_ep_event {
 #include "usb_dwc_hw.h"
 #else
 
-
 /*
  * The STM32 has dedicated USB RAM visible on the APB1 bus (so all reads &
  * writes are 16-bits wide). The endpoint tables and the data buffers live in
  * this RAM.
-*/
+ */
 
 /* Primitive to access the words in USB RAM */
 typedef CONFIG_USB_RAM_ACCESS_TYPE usb_uint;
@@ -87,8 +86,8 @@ enum usb_desc_patch_type {
  * The patches need to be setup before _before_ usb_init is executed (or, at
  * least, before the first call to memcpy_to_usbram_ep0_patch).
  */
-void set_descriptor_patch(enum usb_desc_patch_type type,
-			  const void *address, uint16_t data);
+void set_descriptor_patch(enum usb_desc_patch_type type, const void *address,
+			  uint16_t data);
 
 /* Copy to USB ram, applying patches to src as required. */
 void *memcpy_to_usbram_ep0_patch(const void *src, size_t n);
@@ -106,37 +105,42 @@ void *memcpy_to_usbram_ep0_patch(const void *src, size_t n);
 #define _EP_RX_HANDLER_TYPECHECK(num) _EP_HANDLER2(num, _rx_typecheck)
 #define _EP_EVENT_HANDLER_TYPECHECK(num) _EP_HANDLER2(num, _evt_typecheck)
 
-#define USB_DECLARE_EP(num, tx_handler, rx_handler, evt_handler)  \
-	void _EP_TX_HANDLER(num)(void)				  \
-		__attribute__ ((alias(STRINGIFY(tx_handler))));	  \
-	void _EP_RX_HANDLER(num)(void)                            \
-		__attribute__ ((alias(STRINGIFY(rx_handler))));	  \
-	void _EP_EVENT_HANDLER(num)(enum usb_ep_event evt)        \
-		__attribute__ ((alias(STRINGIFY(evt_handler))));  \
-	static __unused void					  \
-	(*_EP_TX_HANDLER_TYPECHECK(num))(void) = tx_handler;	  \
-	static __unused void					  \
-	(*_EP_RX_HANDLER_TYPECHECK(num))(void) = rx_handler;	  \
-	static __unused void					  \
-	(*_EP_EVENT_HANDLER_TYPECHECK(num))(enum usb_ep_event evt)\
-			= evt_handler
+#define USB_DECLARE_EP(num, tx_handler, rx_handler, evt_handler)      \
+	void _EP_TX_HANDLER(num)(void)                                \
+		__attribute__((alias(STRINGIFY(tx_handler))));        \
+	void _EP_RX_HANDLER(num)(void)                                \
+		__attribute__((alias(STRINGIFY(rx_handler))));        \
+	void _EP_EVENT_HANDLER(num)(enum usb_ep_event evt)            \
+		__attribute__((alias(STRINGIFY(evt_handler))));       \
+	static __unused void (*_EP_TX_HANDLER_TYPECHECK(num))(void) = \
+		tx_handler;                                           \
+	static __unused void (*_EP_RX_HANDLER_TYPECHECK(num))(void) = \
+		rx_handler;                                           \
+	static __unused void (*_EP_EVENT_HANDLER_TYPECHECK(num))(     \
+		enum usb_ep_event evt) = evt_handler
 
 /* arrays with all endpoint callbacks */
-extern void (*usb_ep_tx[]) (void);
-extern void (*usb_ep_rx[]) (void);
-extern void (*usb_ep_event[]) (enum usb_ep_event evt);
+extern void (*usb_ep_tx[])(void);
+extern void (*usb_ep_rx[])(void);
+extern void (*usb_ep_event[])(enum usb_ep_event evt);
 /* array with interface-specific control request callbacks */
-extern int (*usb_iface_request[]) (usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx);
+extern int (*usb_iface_request[])(usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx);
 
 /*
  * Interface handler returns -1 on error, 0 if it wrote the last chunk of data,
  * or 1 if more data needs to be transferred on the next control request.
  */
 #define _IFACE_HANDLER(num) CONCAT3(iface_, num, _request)
-#define USB_DECLARE_IFACE(num, handler)					\
-	int _IFACE_HANDLER(num)(usb_uint *ep0_buf_rx,			\
-			       usb_uint *epo_buf_tx)			\
-	__attribute__ ((alias(STRINGIFY(handler))));
+#define USB_DECLARE_IFACE(num, handler)                                       \
+	int _IFACE_HANDLER(num)(usb_uint * ep0_buf_rx, usb_uint * epo_buf_tx) \
+		__attribute__((alias(STRINGIFY(handler))));
 
 #endif
-#endif	/* __CROS_EC_USB_HW_H */
+
+/*
+ * In and out buffer sizes for host command over USB.
+ */
+#define USBHC_MAX_REQUEST_SIZE 0x200
+#define USBHC_MAX_RESPONSE_SIZE 0x100
+
+#endif /* __CROS_EC_USB_HW_H */
diff --git a/chip/stm32/usb_isochronous.c b/chip/stm32/usb_isochronous.c
index 792507aa75..d2225991c0 100644
--- a/chip/stm32/usb_isochronous.c
+++ b/chip/stm32/usb_isochronous.c
@@ -1,22 +1,21 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include "stddef.h"
 #include "common.h"
 #include "config.h"
 #include "link_defs.h"
 #include "registers.h"
-#include "util.h"
+#include "stddef.h"
 #include "usb_api.h"
 #include "usb_hw.h"
 #include "usb_isochronous.h"
-
+#include "util.h"
 
 /* Console output macro */
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USB, format, ##args)
 
 /*
  * Currently, we only support TX direction for USB isochronous transfer.
@@ -65,8 +64,7 @@ static usb_uint *get_app_addr(struct usb_isochronous_config const *config,
  * Sets number of bytes written to application buffer.
  */
 static void set_app_count(struct usb_isochronous_config const *config,
-			  int dtog_value,
-			  usb_uint count)
+			  int dtog_value, usb_uint count)
 {
 	if (dtog_value)
 		btable_ep[config->endpoint].tx_count = count;
@@ -74,13 +72,9 @@ static void set_app_count(struct usb_isochronous_config const *config,
 		btable_ep[config->endpoint].rx_count = count;
 }
 
-int usb_isochronous_write_buffer(
-		struct usb_isochronous_config const *config,
-		const uint8_t *src,
-		size_t n,
-		size_t dst_offset,
-		int *buffer_id,
-		int commit)
+int usb_isochronous_write_buffer(struct usb_isochronous_config const *config,
+				 const uint8_t *src, size_t n,
+				 size_t dst_offset, int *buffer_id, int commit)
 {
 	int dtog_value = get_tx_dtog(config);
 	usb_uint *buffer = get_app_addr(config, dtog_value);
@@ -142,15 +136,13 @@ void usb_isochronous_tx(struct usb_isochronous_config const *config)
 }
 
 int usb_isochronous_iface_handler(struct usb_isochronous_config const *config,
-				  usb_uint *ep0_buf_rx,
-				  usb_uint *ep0_buf_tx)
+				  usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx)
 {
 	int ret = -1;
 
-	if (ep0_buf_rx[0] == (USB_DIR_OUT |
-			      USB_TYPE_STANDARD |
-			      USB_RECIP_INTERFACE |
-			      USB_REQ_SET_INTERFACE << 8)) {
+	if (ep0_buf_rx[0] ==
+	    (USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE |
+	     USB_REQ_SET_INTERFACE << 8)) {
 		ret = config->set_interface(ep0_buf_rx[1], ep0_buf_rx[2]);
 
 		if (ret == 0) {
diff --git a/chip/stm32/usb_isochronous.h b/chip/stm32/usb_isochronous.h
index efa4d94ab4..a96b6db876 100644
--- a/chip/stm32/usb_isochronous.h
+++ b/chip/stm32/usb_isochronous.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -75,13 +75,9 @@ struct usb_isochronous_config;
  *
  * @return  -EC_ERROR_CODE on failure, or number of bytes written on success.
  */
-int usb_isochronous_write_buffer(
-		struct usb_isochronous_config const *config,
-		const uint8_t *src,
-		size_t n,
-		size_t dst_offset,
-		int *buffer_id,
-		int commit);
+int usb_isochronous_write_buffer(struct usb_isochronous_config const *config,
+				 const uint8_t *src, size_t n,
+				 size_t dst_offset, int *buffer_id, int commit);
 
 struct usb_isochronous_config {
 	int endpoint;
@@ -110,21 +106,15 @@ struct usb_isochronous_config {
 };
 
 /* Define an USB isochronous interface */
-#define USB_ISOCHRONOUS_CONFIG_FULL(NAME,				\
-				    INTERFACE,				\
-				    INTERFACE_CLASS,			\
-				    INTERFACE_SUBCLASS,			\
-				    INTERFACE_PROTOCOL,			\
-				    INTERFACE_NAME,			\
-				    ENDPOINT,				\
-				    TX_SIZE,				\
-				    TX_CALLBACK,			\
-				    SET_INTERFACE,			\
-				    NUM_EXTRA_ENDPOINTS)		\
-	BUILD_ASSERT(TX_SIZE > 0);					\
-	BUILD_ASSERT((TX_SIZE <   64 && (TX_SIZE & 0x01) == 0) ||	\
-		     (TX_SIZE < 1024 && (TX_SIZE & 0x1f) == 0));	\
-	/* Declare buffer */						\
+#define USB_ISOCHRONOUS_CONFIG_FULL(NAME, INTERFACE, INTERFACE_CLASS,          \
+				    INTERFACE_SUBCLASS, INTERFACE_PROTOCOL,    \
+				    INTERFACE_NAME, ENDPOINT, TX_SIZE,         \
+				    TX_CALLBACK, SET_INTERFACE,                \
+				    NUM_EXTRA_ENDPOINTS)                       \
+	BUILD_ASSERT(TX_SIZE > 0);                                             \
+	BUILD_ASSERT((TX_SIZE < 64 && (TX_SIZE & 0x01) == 0) ||                \
+		     (TX_SIZE < 1024 && (TX_SIZE & 0x1f) == 0));               \
+	/* Declare buffer */                                                   \
 	static usb_uint CONCAT2(NAME, _ep_tx_buffer_0)[TX_SIZE / 2] __usb_ram; \
 	static usb_uint CONCAT2(NAME, _ep_tx_buffer_1)[TX_SIZE / 2] __usb_ram; \
 	struct usb_isochronous_config const NAME = {			\
@@ -136,62 +126,57 @@ struct usb_isochronous_config {
 			CONCAT2(NAME, _ep_tx_buffer_0),			\
 			CONCAT2(NAME, _ep_tx_buffer_1),			\
 		},							\
-	};								\
-	const struct usb_interface_descriptor				\
-	USB_IFACE_DESC(INTERFACE) = {					\
-		.bLength            = USB_DT_INTERFACE_SIZE,		\
-		.bDescriptorType    = USB_DT_INTERFACE,			\
-		.bInterfaceNumber   = INTERFACE,			\
-		.bAlternateSetting  = 0,				\
-		.bNumEndpoints      = 0,				\
-		.bInterfaceClass    = INTERFACE_CLASS,			\
-		.bInterfaceSubClass = INTERFACE_SUBCLASS,		\
-		.bInterfaceProtocol = INTERFACE_PROTOCOL,		\
-		.iInterface         = INTERFACE_NAME,			\
-	};								\
-	const struct usb_interface_descriptor				\
-	USB_CONF_DESC(CONCAT3(iface, INTERFACE, _1iface)) = {		\
-		.bLength            = USB_DT_INTERFACE_SIZE,		\
-		.bDescriptorType    = USB_DT_INTERFACE,			\
-		.bInterfaceNumber   = INTERFACE,			\
-		.bAlternateSetting  = 1,				\
-		.bNumEndpoints      = 1 + NUM_EXTRA_ENDPOINTS,		\
-		.bInterfaceClass    = INTERFACE_CLASS,			\
-		.bInterfaceSubClass = INTERFACE_SUBCLASS,		\
-		.bInterfaceProtocol = INTERFACE_PROTOCOL,		\
-		.iInterface         = INTERFACE_NAME,			\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 0) = {					\
-		.bLength          = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = 0x80 | ENDPOINT,			\
-		.bmAttributes     = 0x01 /* Isochronous IN */,		\
-		.wMaxPacketSize   = TX_SIZE,				\
-		.bInterval        = 1,					\
-	};								\
-	static void CONCAT2(NAME, _ep_tx)(void)				\
-	{								\
-		usb_isochronous_tx(&NAME);				\
-	}								\
-	static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt)	\
-	{								\
-		usb_isochronous_event(&NAME, evt);			\
-	}								\
-	static int CONCAT2(NAME, _handler)(usb_uint *rx, usb_uint *tx)	\
-	{								\
-		return usb_isochronous_iface_handler(&NAME, rx, tx);	\
-	}								\
-	USB_DECLARE_IFACE(INTERFACE, CONCAT2(NAME, _handler));		\
-	USB_DECLARE_EP(ENDPOINT,					\
-		       CONCAT2(NAME, _ep_tx),				\
-		       CONCAT2(NAME, _ep_tx),				\
-		       CONCAT2(NAME, _ep_event));			\
+	};                       \
+	const struct usb_interface_descriptor USB_IFACE_DESC(INTERFACE) = {    \
+		.bLength = USB_DT_INTERFACE_SIZE,                              \
+		.bDescriptorType = USB_DT_INTERFACE,                           \
+		.bInterfaceNumber = INTERFACE,                                 \
+		.bAlternateSetting = 0,                                        \
+		.bNumEndpoints = 0,                                            \
+		.bInterfaceClass = INTERFACE_CLASS,                            \
+		.bInterfaceSubClass = INTERFACE_SUBCLASS,                      \
+		.bInterfaceProtocol = INTERFACE_PROTOCOL,                      \
+		.iInterface = INTERFACE_NAME,                                  \
+	};                                                                     \
+	const struct usb_interface_descriptor USB_CONF_DESC(                   \
+		CONCAT3(iface, INTERFACE, _1iface)) = {                        \
+		.bLength = USB_DT_INTERFACE_SIZE,                              \
+		.bDescriptorType = USB_DT_INTERFACE,                           \
+		.bInterfaceNumber = INTERFACE,                                 \
+		.bAlternateSetting = 1,                                        \
+		.bNumEndpoints = 1 + NUM_EXTRA_ENDPOINTS,                      \
+		.bInterfaceClass = INTERFACE_CLASS,                            \
+		.bInterfaceSubClass = INTERFACE_SUBCLASS,                      \
+		.bInterfaceProtocol = INTERFACE_PROTOCOL,                      \
+		.iInterface = INTERFACE_NAME,                                  \
+	};                                                                     \
+	const struct usb_endpoint_descriptor USB_EP_DESC(INTERFACE, 0) = {     \
+		.bLength = USB_DT_ENDPOINT_SIZE,                               \
+		.bDescriptorType = USB_DT_ENDPOINT,                            \
+		.bEndpointAddress = 0x80 | ENDPOINT,                           \
+		.bmAttributes = 0x01 /* Isochronous IN */,                     \
+		.wMaxPacketSize = TX_SIZE,                                     \
+		.bInterval = 1,                                                \
+	};                                                                     \
+	static void CONCAT2(NAME, _ep_tx)(void)                                \
+	{                                                                      \
+		usb_isochronous_tx(&NAME);                                     \
+	}                                                                      \
+	static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt)            \
+	{                                                                      \
+		usb_isochronous_event(&NAME, evt);                             \
+	}                                                                      \
+	static int CONCAT2(NAME, _handler)(usb_uint * rx, usb_uint * tx)       \
+	{                                                                      \
+		return usb_isochronous_iface_handler(&NAME, rx, tx);           \
+	}                                                                      \
+	USB_DECLARE_IFACE(INTERFACE, CONCAT2(NAME, _handler));                 \
+	USB_DECLARE_EP(ENDPOINT, CONCAT2(NAME, _ep_tx), CONCAT2(NAME, _ep_tx), \
+		       CONCAT2(NAME, _ep_event));
 
 void usb_isochronous_tx(struct usb_isochronous_config const *config);
 void usb_isochronous_event(struct usb_isochronous_config const *config,
 			   enum usb_ep_event event);
 int usb_isochronous_iface_handler(struct usb_isochronous_config const *config,
-				  usb_uint *ep0_buf_rx,
-				  usb_uint *ep0_buf_tx);
+				  usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx);
 #endif /* __CROS_EC_USB_ISOCHRONOUS_H */
diff --git a/chip/stm32/usb_pd_phy.c b/chip/stm32/usb_pd_phy.c
index b53c5cfeeb..2d090293f9 100644
--- a/chip/stm32/usb_pd_phy.c
+++ b/chip/stm32/usb_pd_phy.c
@@ -1,28 +1,29 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "adc.h"
+#include "builtin/assert.h"
 #include "clock.h"
 #include "common.h"
 #include "console.h"
 #include "crc.h"
 #include "dma.h"
 #include "gpio.h"
-#include "hwtimer.h"
 #include "hooks.h"
+#include "hwtimer.h"
 #include "registers.h"
 #include "system.h"
 #include "task.h"
 #include "timer.h"
-#include "util.h"
 #include "usb_pd.h"
 #include "usb_pd_config.h"
+#include "util.h"
 
 #ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 #else
 #define CPRINTF(format, args...)
 #define CPRINTS(format, args...)
@@ -38,7 +39,7 @@
  */
 #define PD_BIT_LEN 429
 
-#define PD_MAX_RAW_SIZE (PD_BIT_LEN*2)
+#define PD_MAX_RAW_SIZE (PD_BIT_LEN * 2)
 
 /* maximum number of consecutive similar bits with Biphase Mark Coding */
 #define MAX_BITS 2
@@ -46,12 +47,12 @@
 /* alternating bit sequence used for packet preamble : 00 10 11 01 00 ..  */
 #define PD_PREAMBLE 0xB4B4B4B4 /* starts with 0, ends with 1 */
 
-#define TX_CLOCK_DIV ((clock_get_freq() / (2*PD_DATARATE)))
+#define TX_CLOCK_DIV ((clock_get_freq() / (2 * PD_DATARATE)))
 
 /* threshold for 1 300-khz period */
 #define PERIOD 4
-#define NB_PERIOD(from, to) ((((to) - (from) + (PERIOD/2)) & 0xFF) / PERIOD)
-#define PERIOD_THRESHOLD ((PERIOD + 2*PERIOD) / 2)
+#define NB_PERIOD(from, to) ((((to) - (from) + (PERIOD / 2)) & 0xFF) / PERIOD)
+#define PERIOD_THRESHOLD ((PERIOD + 2 * PERIOD) / 2)
 
 static struct pd_physical {
 	/* samples for the PD messages */
@@ -73,8 +74,8 @@ static struct pd_physical {
 } pd_phy[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 /* keep track of RX edge timing in order to trigger receive */
-static timestamp_t
-	rx_edge_ts[CONFIG_USB_PD_PORT_MAX_COUNT][PD_RX_TRANSITION_COUNT];
+static timestamp_t rx_edge_ts[CONFIG_USB_PD_PORT_MAX_COUNT]
+			     [PD_RX_TRANSITION_COUNT];
 static int rx_edge_ts_idx[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 /* keep track of transmit polarity for DMA interrupt */
@@ -95,8 +96,8 @@ static int wait_bits(int port, int nb)
 
 	avail = dma_bytes_done(rx, PD_MAX_RAW_SIZE);
 	if (avail < nb) { /* no received yet ... */
-		while ((dma_bytes_done(rx, PD_MAX_RAW_SIZE) < nb)
-			&& !(pd_phy[port].tim_rx->sr & 4))
+		while ((dma_bytes_done(rx, PD_MAX_RAW_SIZE) < nb) &&
+		       !(pd_phy[port].tim_rx->sr & 4))
 			; /* optimized for latency, not CPU usage ... */
 		if (dma_bytes_done(rx, PD_MAX_RAW_SIZE) < nb) {
 			CPRINTS("PD TMOUT RX %d/%d",
@@ -117,8 +118,8 @@ int pd_dequeue_bits(int port, int off, int len, uint32_t *val)
 		w = wait_bits(port, off + 2);
 		if (w < 0)
 			goto stream_err;
-		cnt = samples[off] - samples[off-1];
-		if (!cnt || (cnt > 3*PERIOD))
+		cnt = samples[off] - samples[off - 1];
+		if (!cnt || (cnt > 3 * PERIOD))
 			goto stream_err;
 		off++;
 		if (cnt <= PERIOD_THRESHOLD) {
@@ -127,20 +128,22 @@ int pd_dequeue_bits(int port, int off, int len, uint32_t *val)
 			if (w < 0)
 				goto stream_err;
 			*/
-			cnt = samples[off] - samples[off-1];
-			if (cnt >  PERIOD_THRESHOLD)
+			cnt = samples[off] - samples[off - 1];
+			if (cnt > PERIOD_THRESHOLD)
 				goto stream_err;
 			off++;
 		}
 
 		/* enqueue the bit of the last period */
-		pd_phy[port].d_last = (pd_phy[port].d_last >> 1)
-		       | (cnt <= PERIOD_THRESHOLD ? 0x80000000 : 0);
+		pd_phy[port].d_last =
+			(pd_phy[port].d_last >> 1) |
+			(cnt <= PERIOD_THRESHOLD ? 0x80000000 : 0);
 		pd_phy[port].d_lastlen++;
 	}
 	if (off < PD_MAX_RAW_SIZE) {
-		*val = (pd_phy[port].d_last << (pd_phy[port].d_lastlen - len))
-				>> (32 - len);
+		*val = (pd_phy[port].d_last
+			<< (pd_phy[port].d_lastlen - len)) >>
+		       (32 - len);
 		pd_phy[port].d_lastlen -= len;
 		return off;
 	} else {
@@ -168,7 +171,7 @@ int pd_find_preamble(int port)
 		/* wait if the bit is not received yet ... */
 		if (PD_MAX_RAW_SIZE - rx->cndtr < bit + 1) {
 			while ((PD_MAX_RAW_SIZE - rx->cndtr < bit + 1) &&
-				!(pd_phy[port].tim_rx->sr & 4))
+			       !(pd_phy[port].tim_rx->sr & 4))
 				;
 			if (pd_phy[port].tim_rx->sr & 4) {
 				CPRINTS("PD TMOUT RX %d/%d",
@@ -176,7 +179,7 @@ int pd_find_preamble(int port)
 				return -1;
 			}
 		}
-		cnt = vals[bit] - vals[bit-1];
+		cnt = vals[bit] - vals[bit - 1];
 		all = (all >> 1) | (cnt <= PERIOD_THRESHOLD ? BIT(31) : 0);
 		if (all == 0x36db6db6)
 			return bit - 1; /* should be SYNC-1 */
@@ -198,7 +201,7 @@ int pd_write_preamble(int port)
 	msg[2] = PD_PREAMBLE;
 	msg[3] = PD_PREAMBLE;
 	pd_phy[port].b_toggle = 0x3FF; /* preamble ends with 1 */
-	return 2*64;
+	return 2 * 64;
 }
 
 int pd_write_sym(int port, int bit_off, uint32_t val10)
@@ -214,10 +217,10 @@ int pd_write_sym(int port, int bit_off, uint32_t val10)
 		msg[word_idx] |= val << bit_idx;
 	} else {
 		msg[word_idx] |= val << bit_idx;
-		msg[word_idx+1] = val >> (32 - bit_idx);
+		msg[word_idx + 1] = val >> (32 - bit_idx);
 		/* side effect: clear the new word when starting it */
 	}
-	return bit_off + 5*2;
+	return bit_off + 5 * 2;
 }
 
 int pd_write_last_edge(int port, int bit_off)
@@ -239,7 +242,7 @@ int pd_write_last_edge(int port, int bit_off)
 		}
 	}
 	/* ensure that the trailer is 0 */
-	msg[word_idx+1] = 0;
+	msg[word_idx + 1] = 0;
 
 	return bit_off + 3;
 }
@@ -252,15 +255,15 @@ void pd_dump_packet(int port, const char *msg)
 
 	CPRINTF("ERR %s:\n000:- ", msg);
 	/* Packet debug output */
-	for (bit = 1; bit <  PD_MAX_RAW_SIZE; bit++) {
-		int cnt = NB_PERIOD(vals[bit-1], vals[bit]);
+	for (bit = 1; bit < PD_MAX_RAW_SIZE; bit++) {
+		int cnt = NB_PERIOD(vals[bit - 1], vals[bit]);
 		if ((bit & 31) == 0)
 			CPRINTF("\n%03d:", bit);
 		CPRINTF("%1d ", cnt);
 	}
 	CPRINTF("><\n");
 	cflush();
-	for (bit = 0; bit <  PD_MAX_RAW_SIZE; bit++) {
+	for (bit = 0; bit < PD_MAX_RAW_SIZE; bit++) {
 		if ((bit & 31) == 0)
 			CPRINTF("\n%03d:", bit);
 		CPRINTF("%02x ", vals[bit]);
@@ -280,9 +283,9 @@ void pd_tx_spi_init(int port)
 	spi->cr2 = STM32_SPI_CR2_TXDMAEN | STM32_SPI_CR2_DATASIZE(8);
 
 	/* Enable the slave SPI: LSB first, force NSS, TX only, CPHA */
-	spi->cr1 = STM32_SPI_CR1_SPE | STM32_SPI_CR1_LSBFIRST
-		 | STM32_SPI_CR1_SSM | STM32_SPI_CR1_BIDIMODE
-		 | STM32_SPI_CR1_BIDIOE | STM32_SPI_CR1_CPHA;
+	spi->cr1 = STM32_SPI_CR1_SPE | STM32_SPI_CR1_LSBFIRST |
+		   STM32_SPI_CR1_SSM | STM32_SPI_CR1_BIDIMODE |
+		   STM32_SPI_CR1_BIDIOE | STM32_SPI_CR1_CPHA;
 }
 
 static void tx_dma_done(void *data)
@@ -303,7 +306,7 @@ static void tx_dma_done(void *data)
 	pd_tx_disable(port, polarity);
 
 #if defined(CONFIG_COMMON_RUNTIME) && defined(CONFIG_DMA_DEFAULT_HANDLERS)
-	task_set_event(PD_PORT_TO_TASK_ID(port), TASK_EVENT_DMA_TC, 0);
+	task_set_event(PD_PORT_TO_TASK_ID(port), TASK_EVENT_DMA_TC);
 #endif
 }
 
@@ -330,9 +333,8 @@ int pd_start_tx(int port, int polarity, int bit_len)
 	pd_phy[port].tim_tx->cnt = TX_CLOCK_DIV - 1;
 
 	/* update DMA configuration */
-	dma_prepare_tx(&(pd_phy[port].dma_tx_option),
-			DIV_ROUND_UP(bit_len, 8),
-			pd_phy[port].raw_samples);
+	dma_prepare_tx(&(pd_phy[port].dma_tx_option), DIV_ROUND_UP(bit_len, 8),
+		       pd_phy[port].raw_samples);
 	/* Flush data in write buffer so that DMA can get the latest data */
 	asm volatile("dmb;");
 
@@ -343,8 +345,7 @@ int pd_start_tx(int port, int polarity, int bit_len)
 	if (!(pd_phy[port].dma_tx_option.flags & STM32_DMA_CCR_CIRC)) {
 		/* Only enable interrupt if not in circular mode */
 		dma_enable_tc_interrupt_callback(DMAC_SPI_TX(port),
-						 &tx_dma_done,
-						 (void *)port);
+						 &tx_dma_done, (void *)port);
 	}
 #endif
 	dma_go(tx);
@@ -401,9 +402,10 @@ void pd_rx_start(int port)
 {
 	/* start sampling the edges on the CC line using the RX timer */
 	dma_start_rx(&(pd_phy[port].dma_tim_option), PD_MAX_RAW_SIZE,
-			pd_phy[port].raw_samples);
+		     pd_phy[port].raw_samples);
 	/* enable TIM2 DMA requests */
-	pd_phy[port].tim_rx->egr = 0x0001; /* reset counter / reload PSC */;
+	pd_phy[port].tim_rx->egr = 0x0001; /* reset counter / reload PSC */
+	;
 	pd_phy[port].tim_rx->sr = 0; /* clear overflows */
 	pd_phy[port].tim_rx->cr1 |= 1;
 }
@@ -441,8 +443,8 @@ void pd_rx_disable_monitoring(int port)
 uint64_t get_time_since_last_edge(int port)
 {
 	int prev_idx = (rx_edge_ts_idx[port] == 0) ?
-			PD_RX_TRANSITION_COUNT - 1 :
-			rx_edge_ts_idx[port] - 1;
+			       PD_RX_TRANSITION_COUNT - 1 :
+			       rx_edge_ts_idx[port] - 1;
 	return get_time().val - rx_edge_ts[port][prev_idx].val;
 }
 
@@ -467,11 +469,12 @@ void pd_rx_handler(void)
 		if (pending & EXTI_COMP_MASK(i)) {
 			rx_edge_ts[i][rx_edge_ts_idx[i]].val = get_time().val;
 			next_idx = (rx_edge_ts_idx[i] ==
-					PD_RX_TRANSITION_COUNT - 1) ?
-						0 : rx_edge_ts_idx[i] + 1;
+				    PD_RX_TRANSITION_COUNT - 1) ?
+					   0 :
+					   rx_edge_ts_idx[i] + 1;
 
-#if defined(CONFIG_LOW_POWER_IDLE) &&                        \
-defined(CONFIG_USB_PD_LOW_POWER_IDLE_WHEN_CONNECTED)
+#if defined(CONFIG_LOW_POWER_IDLE) && \
+	defined(CONFIG_USB_PD_LOW_POWER_IDLE_WHEN_CONNECTED)
 			/*
 			 * Do not deep sleep while waiting for more edges. For
 			 * most boards, sleep is already disabled due to being
@@ -487,8 +490,8 @@ defined(CONFIG_USB_PD_LOW_POWER_IDLE_WHEN_CONNECTED)
 			 * time, then trigger RX start.
 			 */
 			if ((rx_edge_ts[i][rx_edge_ts_idx[i]].val -
-			     rx_edge_ts[i][next_idx].val)
-			     < PD_RX_TRANSITION_WINDOW) {
+			     rx_edge_ts[i][next_idx].val) <
+			    PD_RX_TRANSITION_WINDOW) {
 				/* start sampling */
 				pd_rx_start(i);
 				/*
@@ -507,7 +510,11 @@ defined(CONFIG_USB_PD_LOW_POWER_IDLE_WHEN_CONNECTED)
 	}
 }
 #ifdef CONFIG_USB_PD_RX_COMP_IRQ
-DECLARE_IRQ(STM32_IRQ_COMP, pd_rx_handler, 1);
+static void _pd_rx_handler(void)
+{
+	pd_rx_handler();
+}
+DECLARE_IRQ(STM32_IRQ_COMP, _pd_rx_handler, 1);
 #endif
 
 /* --- release hardware --- */
@@ -531,7 +538,7 @@ void pd_hw_init_rx(int port)
 	phy->dma_tim_option.channel = DMAC_TIM_RX(port);
 	phy->dma_tim_option.periph = (void *)(TIM_RX_CCR_REG(port));
 	phy->dma_tim_option.flags = STM32_DMA_CCR_MSIZE_8_BIT |
-				     STM32_DMA_CCR_PSIZE_16_BIT;
+				    STM32_DMA_CCR_PSIZE_16_BIT;
 
 	/* --- set counter for RX timing : 2.4Mhz rate, free-running --- */
 	__hw_timer_enable_clock(TIM_CLOCK_PD_RX(port), 1);
@@ -557,7 +564,8 @@ void pd_hw_init_rx(int port)
 
 	phy->tim_rx->ccer = 0xB << ((TIM_RX_CCR_IDX(port) - 1) * 4);
 	/* configure DMA request on CCRx update */
-	phy->tim_rx->dier |= 1 << (8 + TIM_RX_CCR_IDX(port)); /* CCxDE */;
+	phy->tim_rx->dier |= 1 << (8 + TIM_RX_CCR_IDX(port)); /* CCxDE */
+	;
 	/* set prescaler to /26 (F=1.2Mhz, T=0.8us) */
 	phy->tim_rx->psc = (clock_get_freq() / 2400000) - 1;
 	/* Reload the pre-scaler and reset the counter (clear CCRx) */
@@ -586,18 +594,15 @@ void pd_hw_init_rx(int port)
 	clock_wait_bus_cycles(BUS_APB, 1);
 	/* currently in hi-speed mode : TODO revisit later, INM = PA0(INM6) */
 	STM32_COMP_CSR = STM32_COMP_CMP1MODE_LSPEED |
-			 STM32_COMP_CMP1INSEL_INM6 |
-			 CMP1OUTSEL |
-			 STM32_COMP_CMP1HYST_HI |
-			 STM32_COMP_CMP2MODE_LSPEED |
-			 STM32_COMP_CMP2INSEL_INM6 |
-			 CMP2OUTSEL |
+			 STM32_COMP_CMP1INSEL_INM6 | CMP1OUTSEL |
+			 STM32_COMP_CMP1HYST_HI | STM32_COMP_CMP2MODE_LSPEED |
+			 STM32_COMP_CMP2INSEL_INM6 | CMP2OUTSEL |
 			 STM32_COMP_CMP2HYST_HI;
 #elif defined(CHIP_FAMILY_STM32L)
 	STM32_RCC_APB1ENR |= BIT(31); /* turn on COMP */
 
-	STM32_COMP_CSR = STM32_COMP_OUTSEL_TIM2_IC4 | STM32_COMP_INSEL_DAC_OUT1
-			| STM32_COMP_SPEED_FAST;
+	STM32_COMP_CSR = STM32_COMP_OUTSEL_TIM2_IC4 |
+			 STM32_COMP_INSEL_DAC_OUT1 | STM32_COMP_SPEED_FAST;
 	/* route PB4 to COMP input2 through GR6_1 bit 4 (or PB5->GR6_2 bit 5) */
 	STM32_RI_ASCR2 |= BIT(4);
 #else
@@ -634,9 +639,9 @@ void pd_hw_init(int port, enum pd_power_role role)
 	phy->dma_tx_option.channel = DMAC_SPI_TX(port);
 	phy->dma_tx_option.periph = (void *)&SPI_REGS(port)->dr;
 	phy->dma_tx_option.flags = STM32_DMA_CCR_MSIZE_8_BIT |
-				    STM32_DMA_CCR_PSIZE_8_BIT;
+				   STM32_DMA_CCR_PSIZE_8_BIT;
 	dma_prepare_tx(&(phy->dma_tx_option), PD_MAX_RAW_SIZE,
-			phy->raw_samples);
+		       phy->raw_samples);
 
 	/* configure registers used for timers */
 	phy->tim_tx = (void *)TIM_REG_TX(port);
@@ -676,5 +681,5 @@ void pd_hw_init(int port, enum pd_power_role role)
 
 void pd_set_clock(int port, int freq)
 {
-	pd_phy[port].tim_tx->arr = clock_get_freq() / (2*freq);
+	pd_phy[port].tim_tx->arr = clock_get_freq() / (2 * freq);
 }
diff --git a/chip/stm32/usb_power.c b/chip/stm32/usb_power.c
index 90f0039c2c..589767f15c 100644
--- a/chip/stm32/usb_power.c
+++ b/chip/stm32/usb_power.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,7 +14,7 @@
 #include "usb_power.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
 
 static int usb_power_init_inas(struct usb_power_config const *config);
 static int usb_power_read(struct usb_power_config const *config);
@@ -42,16 +42,15 @@ void usb_power_deferred_tx(struct usb_power_config const *config)
 		state->reports_xmit_active = state->reports_tail;
 
 		/* Wait for the next command */
-		usb_read_ep(config->endpoint,
-			config->ep->out_databuffer_max,
-			config->ep->out_databuffer);
+		usb_read_ep(config->endpoint, config->ep->out_databuffer_max,
+			    config->ep->out_databuffer);
 		return;
 	}
 }
 
 /* Reset stream */
 void usb_power_event(struct usb_power_config const *config,
-		enum usb_ep_event evt)
+		     enum usb_ep_event evt)
 {
 	if (evt != USB_EVENT_RESET)
 		return;
@@ -68,15 +67,15 @@ void usb_power_event(struct usb_power_config const *config,
 	hook_call_deferred(config->ep->tx_deferred, 0);
 }
 
-
 /* Write one or more power records to USB */
 static int usb_power_write_line(struct usb_power_config const *config)
 {
 	struct usb_power_state *state = config->state;
-	struct usb_power_report *r = (struct usb_power_report *)(
-		state->reports_data_area +
-		(USB_POWER_RECORD_SIZE(state->ina_count)
-		* state->reports_tail));
+	struct usb_power_report *r =
+		(struct usb_power_report *)(state->reports_data_area +
+					    (USB_POWER_RECORD_SIZE(
+						     state->ina_count) *
+					     state->reports_tail));
 	/* status + size + timestamps + power list */
 	size_t bytes = USB_POWER_RECORD_SIZE(state->ina_count);
 
@@ -89,12 +88,12 @@ static int usb_power_write_line(struct usb_power_config const *config)
 			recordcount = config->state->reports_head -
 				      config->state->reports_tail;
 		else
-			recordcount = state->max_cached -
-				      config->state->reports_tail;
+			recordcount =
+				state->max_cached - config->state->reports_tail;
 
 		state->reports_xmit_active = state->reports_tail;
-		state->reports_tail = (state->reports_tail + recordcount) %
-			state->max_cached;
+		state->reports_tail =
+			(state->reports_tail + recordcount) % state->max_cached;
 
 		usb_write_ep(config->endpoint, bytes * recordcount, r);
 		return bytes;
@@ -103,7 +102,6 @@ static int usb_power_write_line(struct usb_power_config const *config)
 	return 0;
 }
 
-
 static int usb_power_state_reset(struct usb_power_config const *config)
 {
 	struct usb_power_state *state = config->state;
@@ -117,7 +115,6 @@ static int usb_power_state_reset(struct usb_power_config const *config)
 	return USB_POWER_SUCCESS;
 }
 
-
 static int usb_power_state_stop(struct usb_power_config const *config)
 {
 	struct usb_power_state *state = config->state;
@@ -137,8 +134,6 @@ static int usb_power_state_stop(struct usb_power_config const *config)
 	return USB_POWER_SUCCESS;
 }
 
-
-
 static int usb_power_state_start(struct usb_power_config const *config,
 				 union usb_power_command_data *cmd, int count)
 {
@@ -182,13 +177,12 @@ static int usb_power_state_start(struct usb_power_config const *config,
 	return USB_POWER_SUCCESS;
 }
 
-
 static int usb_power_state_settime(struct usb_power_config const *config,
-				 union usb_power_command_data *cmd, int count)
+				   union usb_power_command_data *cmd, int count)
 {
 	if (count != sizeof(struct usb_power_command_settime)) {
-		CPRINTS("[SETTIME] Error: count %d is not %d",
-			(int)count, sizeof(struct usb_power_command_settime));
+		CPRINTS("[SETTIME] Error: count %d is not %d", (int)count,
+			sizeof(struct usb_power_command_settime));
 		return USB_POWER_ERROR_READ_SIZE;
 	}
 
@@ -201,9 +195,8 @@ static int usb_power_state_settime(struct usb_power_config const *config,
 	return USB_POWER_SUCCESS;
 }
 
-
 static int usb_power_state_addina(struct usb_power_config const *config,
-				 union usb_power_command_data *cmd, int count)
+				  union usb_power_command_data *cmd, int count)
 {
 	struct usb_power_state *state = config->state;
 	struct usb_power_ina_cfg *ina;
@@ -217,8 +210,8 @@ static int usb_power_state_addina(struct usb_power_config const *config,
 	}
 
 	if (count != sizeof(struct usb_power_command_addina)) {
-		CPRINTS("[ADDINA] Error count %d is not %d",
-			(int)count, sizeof(struct usb_power_command_addina));
+		CPRINTS("[ADDINA] Error count %d is not %d", (int)count,
+			sizeof(struct usb_power_command_addina));
 		return USB_POWER_ERROR_READ_SIZE;
 	}
 
@@ -286,8 +279,8 @@ static int usb_power_read(struct usb_power_config const *config)
 	 * If there is a USB packet waiting we process it and generate a
 	 * response.
 	 */
-	uint8_t count		= rx_ep_pending(config->endpoint);
-	uint8_t result		= USB_POWER_SUCCESS;
+	uint8_t count = rx_ep_pending(config->endpoint);
+	uint8_t result = USB_POWER_SUCCESS;
 	union usb_power_command_data *cmd =
 		(union usb_power_command_data *)config->ep->out_databuffer;
 
@@ -314,14 +307,14 @@ static int usb_power_read(struct usb_power_config const *config)
 		result = usb_power_state_start(config, cmd, count);
 		if (result == USB_POWER_SUCCESS) {
 			/* Send back actual integration time. */
-			ep->in_databuffer[1] =
-				(state->integration_us >> 0) & 0xff;
-			ep->in_databuffer[2] =
-				(state->integration_us >> 8) & 0xff;
-			ep->in_databuffer[3] =
-				(state->integration_us >> 16) & 0xff;
-			ep->in_databuffer[4] =
-				(state->integration_us >> 24) & 0xff;
+			ep->in_databuffer[1] = (state->integration_us >> 0) &
+					       0xff;
+			ep->in_databuffer[2] = (state->integration_us >> 8) &
+					       0xff;
+			ep->in_databuffer[3] = (state->integration_us >> 16) &
+					       0xff;
+			ep->in_databuffer[4] = (state->integration_us >> 24) &
+					       0xff;
 			in_msgsize += 4;
 		}
 		break;
@@ -363,8 +356,6 @@ static int usb_power_read(struct usb_power_config const *config)
 	return EC_SUCCESS;
 }
 
-
-
 /******************************************************************************
  * INA231 interface.
  * List the registers and fields here.
@@ -374,20 +365,19 @@ static int usb_power_read(struct usb_power_config const *config)
 #define INA231_REG_CONF 0
 #define INA231_REG_RSHV 1
 #define INA231_REG_BUSV 2
-#define INA231_REG_PWR  3
+#define INA231_REG_PWR 3
 #define INA231_REG_CURR 4
-#define INA231_REG_CAL  5
-#define INA231_REG_EN   6
-
-
-#define INA231_CONF_AVG(val)		(((int)(val & 0x7)) << 9)
-#define INA231_CONF_BUS_TIME(val)	(((int)(val & 0x7)) << 6)
-#define INA231_CONF_SHUNT_TIME(val)	(((int)(val & 0x7)) << 3)
-#define INA231_CONF_MODE(val)		(((int)(val & 0x7)) << 0)
-#define INA231_MODE_OFF			0x0
-#define INA231_MODE_SHUNT		0x5
-#define INA231_MODE_BUS			0x6
-#define INA231_MODE_BOTH		0x7
+#define INA231_REG_CAL 5
+#define INA231_REG_EN 6
+
+#define INA231_CONF_AVG(val) (((int)(val & 0x7)) << 9)
+#define INA231_CONF_BUS_TIME(val) (((int)(val & 0x7)) << 6)
+#define INA231_CONF_SHUNT_TIME(val) (((int)(val & 0x7)) << 3)
+#define INA231_CONF_MODE(val) (((int)(val & 0x7)) << 0)
+#define INA231_MODE_OFF 0x0
+#define INA231_MODE_SHUNT 0x5
+#define INA231_MODE_BUS 0x6
+#define INA231_MODE_BOTH 0x7
 
 int reg_type_mapping(enum usb_power_ina_type ina_type)
 {
@@ -406,53 +396,47 @@ int reg_type_mapping(enum usb_power_ina_type ina_type)
 	}
 }
 
-uint16_t ina2xx_readagain(uint8_t port, uint16_t slave_addr_flags)
+uint16_t ina2xx_readagain(uint8_t port, uint16_t addr_flags)
 {
 	int res;
 	uint16_t val;
 
-	res = i2c_xfer(port, slave_addr_flags,
-		       NULL, 0, (uint8_t *)&val, sizeof(uint16_t));
+	res = i2c_xfer(port, addr_flags, NULL, 0, (uint8_t *)&val,
+		       sizeof(uint16_t));
 
 	if (res) {
-		CPRINTS("INA2XX I2C readagain failed p:%d a:%02x",
-			(int)port, (int)I2C_GET_ADDR(slave_addr_flags));
+		CPRINTS("INA2XX I2C readagain failed p:%d a:%02x", (int)port,
+			(int)I2C_STRIP_FLAGS(addr_flags));
 		return 0x0bad;
 	}
 	return (val >> 8) | ((val & 0xff) << 8);
 }
 
-
-uint16_t ina2xx_read(uint8_t port, uint16_t slave_addr_flags,
-		     uint8_t reg)
+uint16_t ina2xx_read(uint8_t port, uint16_t addr_flags, uint8_t reg)
 {
 	int res;
 	int val;
 
-	res = i2c_read16(port, slave_addr_flags, reg, &val);
+	res = i2c_read16(port, addr_flags, reg, &val);
 	if (res) {
-		CPRINTS("INA2XX I2C read failed p:%d a:%02x, r:%02x",
-			(int)port, (int)I2C_GET_ADDR(slave_addr_flags),
-			(int)reg);
+		CPRINTS("INA2XX I2C read failed p:%d a:%02x, r:%02x", (int)port,
+			(int)I2C_STRIP_FLAGS(addr_flags), (int)reg);
 		return 0x0bad;
 	}
 	return (val >> 8) | ((val & 0xff) << 8);
 }
 
-int ina2xx_write(uint8_t port, uint16_t slave_addr_flags,
-		 uint8_t reg, uint16_t val)
+int ina2xx_write(uint8_t port, uint16_t addr_flags, uint8_t reg, uint16_t val)
 {
 	int res;
 	uint16_t be_val = (val >> 8) | ((val & 0xff) << 8);
 
-	res = i2c_write16(port, slave_addr_flags, reg, be_val);
+	res = i2c_write16(port, addr_flags, reg, be_val);
 	if (res)
 		CPRINTS("INA2XX I2C write failed");
 	return res;
 }
 
-
-
 /******************************************************************************
  * Background tasks
  *
@@ -462,11 +446,10 @@ int ina2xx_write(uint8_t port, uint16_t slave_addr_flags,
  */
 
 /* INA231 integration and averaging time presets, indexed by register value */
-#define NELEMS(x)  (sizeof(x) / sizeof((x)[0]))
-static const int average_settings[] = {
-	1, 4, 16, 64, 128, 256, 512, 1024};
-static const int conversion_time_us[] =	{
-	140, 204, 332, 588, 1100, 2116, 4156, 8244};
+#define NELEMS(x) (sizeof(x) / sizeof((x)[0]))
+static const int average_settings[] = { 1, 4, 16, 64, 128, 256, 512, 1024 };
+static const int conversion_time_us[] = { 140,	204,  332,  588,
+					  1100, 2116, 4156, 8244 };
 
 static int usb_power_init_inas(struct usb_power_config const *config)
 {
@@ -491,8 +474,7 @@ static int usb_power_init_inas(struct usb_power_config const *config)
 	/* Find an averaging setting from the INA presets that fits. */
 	while (avg < (NELEMS(average_settings) - 1)) {
 		if ((conversion_time_us[shunt_time] *
-		     average_settings[avg + 1])
-		    > target_us)
+		     average_settings[avg + 1]) > target_us)
 			break;
 		avg++;
 	}
@@ -507,15 +489,15 @@ static int usb_power_init_inas(struct usb_power_config const *config)
 
 #ifdef USB_POWER_VERBOSE
 		{
-		int conf, cal;
-
-		conf = ina2xx_read(ina->port, ina->addr_flags,
-				   INA231_REG_CONF);
-		cal = ina2xx_read(ina->port, ina->addr_flags,
-				  INA231_REG_CAL);
-		CPRINTS("[CAP] %d (%d,0x%02x): conf:%x, cal:%x",
-			i, ina->port, I2C_GET_ADDR(ina->addr_flags),
-			conf, cal);
+			int conf, cal;
+
+			conf = ina2xx_read(ina->port, ina->addr_flags,
+					   INA231_REG_CONF);
+			cal = ina2xx_read(ina->port, ina->addr_flags,
+					  INA231_REG_CAL);
+			CPRINTS("[CAP] %d (%d,0x%02x): conf:%x, cal:%x", i,
+				ina->port, I2C_STRIP_FLAGS(ina->addr_flags),
+				conf, cal);
 		}
 #endif
 		/*
@@ -536,54 +518,53 @@ static int usb_power_init_inas(struct usb_power_config const *config)
 		if (ina->scale == 0)
 			return -1;
 		value = (5120000 * 100) / (ina->scale * ina->rs);
-		ret = ina2xx_write(ina->port, ina->addr_flags,
-				   INA231_REG_CAL, value);
+		ret = ina2xx_write(ina->port, ina->addr_flags, INA231_REG_CAL,
+				   value);
 		if (ret != EC_SUCCESS) {
 			CPRINTS("[CAP] usb_power_init_inas CAL FAIL: %d", ret);
 			return ret;
 		}
 #ifdef USB_POWER_VERBOSE
 		{
-		int actual;
+			int actual;
 
-		actual = ina2xx_read(ina->port, ina->addr_flags,
-				     INA231_REG_CAL);
-		CPRINTS("[CAP] scale: %d uA/div, %d uW/div, cal:%x act:%x",
-			ina->scale / 100, ina->scale*25/100, value, actual);
+			actual = ina2xx_read(ina->port, ina->addr_flags,
+					     INA231_REG_CAL);
+			CPRINTS("[CAP] scale: %d uA/div, %d uW/div, cal:%x act:%x",
+				ina->scale / 100, ina->scale * 25 / 100, value,
+				actual);
 		}
 #endif
 		/* Conversion time, shunt + bus, set average. */
 		value = INA231_CONF_MODE(INA231_MODE_BOTH) |
 			INA231_CONF_SHUNT_TIME(shunt_time) |
-			INA231_CONF_BUS_TIME(shunt_time) |
-			INA231_CONF_AVG(avg);
-		ret = ina2xx_write(ina->port, ina->addr_flags,
-				   INA231_REG_CONF, value);
+			INA231_CONF_BUS_TIME(shunt_time) | INA231_CONF_AVG(avg);
+		ret = ina2xx_write(ina->port, ina->addr_flags, INA231_REG_CONF,
+				   value);
 		if (ret != EC_SUCCESS) {
 			CPRINTS("[CAP] usb_power_init_inas CONF FAIL: %d", ret);
 			return ret;
 		}
 #ifdef USB_POWER_VERBOSE
 		{
-		int actual;
+			int actual;
 
-		actual = ina2xx_read(ina->port, ina->addr_flags,
-				     INA231_REG_CONF);
-		CPRINTS("[CAP] %d (%d,0x%02x): conf:%x, act:%x",
-			i, ina->port, I2C_GET_ADDR(ina->addr_flags),
-			value, actual);
+			actual = ina2xx_read(ina->port, ina->addr_flags,
+					     INA231_REG_CONF);
+			CPRINTS("[CAP] %d (%d,0x%02x): conf:%x, act:%x", i,
+				ina->port, I2C_STRIP_FLAGS(ina->addr_flags),
+				value, actual);
 		}
 #endif
 #ifdef USB_POWER_VERBOSE
 		{
-		int busv_mv =
-			(ina2xx_read(ina->port, ina->addr_flags,
-				     INA231_REG_BUSV)
-			 * 125) / 100;
-
-		CPRINTS("[CAP] %d (%d,0x%02x): busv:%dmv",
-			i, ina->port, I2C_GET_ADDR(ina->addr_flags),
-			busv_mv);
+			int busv_mv = (ina2xx_read(ina->port, ina->addr_flags,
+						   INA231_REG_BUSV) *
+				       125) /
+				      100;
+
+			CPRINTS("[CAP] %d (%d,0x%02x): busv:%dmv", i, ina->port,
+				I2C_STRIP_FLAGS(ina->addr_flags), busv_mv);
 		}
 #endif
 		/* Initialize read from power register. This register address
@@ -600,7 +581,6 @@ static int usb_power_init_inas(struct usb_power_config const *config)
 	return EC_SUCCESS;
 }
 
-
 /*
  * Read each INA's power integration measurement.
  *
@@ -614,19 +594,20 @@ static int usb_power_get_samples(struct usb_power_config const *config)
 {
 	uint64_t time = get_time().val;
 	struct usb_power_state *state = config->state;
-	struct usb_power_report *r = (struct usb_power_report *)(
-		state->reports_data_area +
-		(USB_POWER_RECORD_SIZE(state->ina_count)
-		* state->reports_head));
+	struct usb_power_report *r =
+		(struct usb_power_report *)(state->reports_data_area +
+					    (USB_POWER_RECORD_SIZE(
+						     state->ina_count) *
+					     state->reports_head));
 	struct usb_power_ina_cfg *inas = state->ina_cfg;
 	int i;
 
 	/* TODO(nsanders): Would we prefer to evict oldest? */
-	if (((state->reports_head + 1) % USB_POWER_MAX_CACHED(state->ina_count))
-	    == state->reports_xmit_active) {
-		CPRINTS("Overflow! h:%d a:%d t:%d (%d)",
-			state->reports_head, state->reports_xmit_active,
-			state->reports_tail,
+	if (((state->reports_head + 1) %
+	     USB_POWER_MAX_CACHED(state->ina_count)) ==
+	    state->reports_xmit_active) {
+		CPRINTS("Overflow! h:%d a:%d t:%d (%d)", state->reports_head,
+			state->reports_xmit_active, state->reports_tail,
 			USB_POWER_MAX_CACHED(state->ina_count));
 		return USB_POWER_ERROR_OVERFLOW;
 	}
@@ -650,47 +631,48 @@ static int usb_power_get_samples(struct usb_power_config const *config)
 		 */
 		if (ina->shared)
 			regval = ina2xx_read(ina->port, ina->addr_flags,
-					reg_type_mapping(ina->type));
+					     reg_type_mapping(ina->type));
 		else
-			regval = ina2xx_readagain(ina->port,
-						  ina->addr_flags);
+			regval = ina2xx_readagain(ina->port, ina->addr_flags);
 		r->power[i] = regval;
 #ifdef USB_POWER_VERBOSE
 		{
-		int current;
-		int power;
-		int voltage;
-		int bvoltage;
-
-		voltage = ina2xx_read(ina->port, ina->addr_flags,
-				      INA231_REG_RSHV);
-		bvoltage = ina2xx_read(ina->port, ina->addr_flags,
-				       INA231_REG_BUSV);
-		current = ina2xx_read(ina->port, ina->addr_flags,
-				      INA231_REG_CURR);
-		power = ina2xx_read(ina->port, ina->addr_flags,
-				    INA231_REG_PWR);
-		{
-		int uV = ((int)voltage * 25) / 10;
-		int mV = ((int)bvoltage * 125) / 100;
-		int uA = (uV * 1000) / ina->rs;
-		int CuA = (((int)current * ina->scale) / 100);
-		int uW = (((int)power * ina->scale*25)/100);
-
-		CPRINTS("[CAP] %d (%d,0x%02x): %dmV / %dmO = %dmA",
-			i, ina->port, I2C_GET_ADDR(ina->addr_flags),
-			uV/1000, ina->rs, uA/1000);
-		CPRINTS("[CAP] %duV %dmV %duA %dCuA "
-			"%duW v:%04x, b:%04x, p:%04x",
-			uV, mV, uA, CuA, uW, voltage, bvoltage, power);
-		}
+			int current;
+			int power;
+			int voltage;
+			int bvoltage;
+
+			voltage = ina2xx_read(ina->port, ina->addr_flags,
+					      INA231_REG_RSHV);
+			bvoltage = ina2xx_read(ina->port, ina->addr_flags,
+					       INA231_REG_BUSV);
+			current = ina2xx_read(ina->port, ina->addr_flags,
+					      INA231_REG_CURR);
+			power = ina2xx_read(ina->port, ina->addr_flags,
+					    INA231_REG_PWR);
+			{
+				int uV = ((int)voltage * 25) / 10;
+				int mV = ((int)bvoltage * 125) / 100;
+				int uA = (uV * 1000) / ina->rs;
+				int CuA = (((int)current * ina->scale) / 100);
+				int uW = (((int)power * ina->scale * 25) / 100);
+
+				CPRINTS("[CAP] %d (%d,0x%02x): %dmV / %dmO = %dmA",
+					i, ina->port,
+					I2C_STRIP_FLAGS(ina->addr_flags),
+					uV / 1000, ina->rs, uA / 1000);
+				CPRINTS("[CAP] %duV %dmV %duA %dCuA "
+					"%duW v:%04x, b:%04x, p:%04x",
+					uV, mV, uA, CuA, uW, voltage, bvoltage,
+					power);
+			}
 		}
 #endif
 	}
 
 	/* Mark this slot as used. */
 	state->reports_head = (state->reports_head + 1) %
-		USB_POWER_MAX_CACHED(state->ina_count);
+			      USB_POWER_MAX_CACHED(state->ina_count);
 
 	return EC_SUCCESS;
 }
@@ -730,4 +712,3 @@ void usb_power_deferred_cap(struct usb_power_config const *config)
 	if (config->state->state == USB_POWER_STATE_CAPTURING)
 		hook_call_deferred(config->deferred_cap, timeout);
 }
-
diff --git a/chip/stm32/usb_power.h b/chip/stm32/usb_power.h
index 68b7f75ca2..1445fcea0f 100644
--- a/chip/stm32/usb_power.h
+++ b/chip/stm32/usb_power.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -38,7 +38,8 @@
  *
  *     addina:	0x0002
  *     +--------+--------------------------+-------------+--------------+-----------+--------+
- *     | 0x0002 | 1B: 4b: extender 4b: bus | 1B:INA type | 1B: INA addr | 1B: extra | 4B: Rs |
+ *     | 0x0002 | 1B: 4b: extender 4b: bus | 1B:INA type | 1B: INA addr | 1B:
+ *extra | 4B: Rs |
  *     +--------+--------------------------+-------------+--------------+-----------+--------+
  *
  *     start:	0x0003
@@ -90,40 +91,40 @@
 
 /* 8b status field. */
 enum usb_power_error {
-	USB_POWER_SUCCESS		= 0x00,
-	USB_POWER_ERROR_I2C		= 0x01,
-	USB_POWER_ERROR_OVERFLOW	= 0x02,
-	USB_POWER_ERROR_NOT_SETUP	= 0x03,
-	USB_POWER_ERROR_NOT_CAPTURING	= 0x04,
-	USB_POWER_ERROR_TIMEOUT		= 0x05,
-	USB_POWER_ERROR_BUSY		= 0x06,
-	USB_POWER_ERROR_READ_SIZE	= 0x07,
-	USB_POWER_ERROR_FULL		= 0x08,
-	USB_POWER_ERROR_INVAL		= 0x09,
-	USB_POWER_ERROR_UNKNOWN		= 0x80,
+	USB_POWER_SUCCESS = 0x00,
+	USB_POWER_ERROR_I2C = 0x01,
+	USB_POWER_ERROR_OVERFLOW = 0x02,
+	USB_POWER_ERROR_NOT_SETUP = 0x03,
+	USB_POWER_ERROR_NOT_CAPTURING = 0x04,
+	USB_POWER_ERROR_TIMEOUT = 0x05,
+	USB_POWER_ERROR_BUSY = 0x06,
+	USB_POWER_ERROR_READ_SIZE = 0x07,
+	USB_POWER_ERROR_FULL = 0x08,
+	USB_POWER_ERROR_INVAL = 0x09,
+	USB_POWER_ERROR_UNKNOWN = 0x80,
 };
 
 /* 16b command field. */
 enum usb_power_command {
-	USB_POWER_CMD_RESET	= 0x0000,
-	USB_POWER_CMD_STOP	= 0x0001,
-	USB_POWER_CMD_ADDINA	= 0x0002,
-	USB_POWER_CMD_START	= 0x0003,
-	USB_POWER_CMD_NEXT	= 0x0004,
-	USB_POWER_CMD_SETTIME	= 0x0005,
+	USB_POWER_CMD_RESET = 0x0000,
+	USB_POWER_CMD_STOP = 0x0001,
+	USB_POWER_CMD_ADDINA = 0x0002,
+	USB_POWER_CMD_START = 0x0003,
+	USB_POWER_CMD_NEXT = 0x0004,
+	USB_POWER_CMD_SETTIME = 0x0005,
 };
 
 /* Addina "INA Type" field. */
 enum usb_power_ina_type {
-	USBP_INA231_POWER	= 0x01,
-	USBP_INA231_BUSV	= 0x02,
-	USBP_INA231_CURRENT	= 0x03,
-	USBP_INA231_SHUNTV	= 0x04,
+	USBP_INA231_POWER = 0x01,
+	USBP_INA231_BUSV = 0x02,
+	USBP_INA231_CURRENT = 0x03,
+	USBP_INA231_SHUNTV = 0x04,
 };
 
 /* Internal state machine values */
 enum usb_power_states {
-	USB_POWER_STATE_OFF	= 0,
+	USB_POWER_STATE_OFF = 0,
 	USB_POWER_STATE_SETUP,
 	USB_POWER_STATE_CAPTURING,
 };
@@ -154,8 +155,7 @@ struct usb_power_ina_cfg {
 	int shared;
 };
 
-
-struct __attribute__ ((__packed__)) usb_power_report {
+struct __attribute__((__packed__)) usb_power_report {
 	uint8_t status;
 	uint8_t size;
 	uint64_t timestamp;
@@ -163,17 +163,19 @@ struct __attribute__ ((__packed__)) usb_power_report {
 };
 
 /* Must be 4 byte aligned */
-#define USB_POWER_RECORD_SIZE(ina_count)				\
-	((((sizeof(struct usb_power_report)				\
-	- (sizeof(uint16_t) * USB_POWER_MAX_READ_COUNT)			\
-	+ (sizeof(uint16_t) * (ina_count))) + 3) / 4) * 4)
-
-#define USB_POWER_DATA_SIZE						\
+#define USB_POWER_RECORD_SIZE(ina_count)                    \
+	((((sizeof(struct usb_power_report) -               \
+	    (sizeof(uint16_t) * USB_POWER_MAX_READ_COUNT) + \
+	    (sizeof(uint16_t) * (ina_count))) +             \
+	   3) /                                             \
+	  4) *                                              \
+	 4)
+
+#define USB_POWER_DATA_SIZE \
 	(sizeof(struct usb_power_report) * (USB_POWER_MIN_CACHED + 1))
-#define USB_POWER_MAX_CACHED(ina_count)					\
+#define USB_POWER_MAX_CACHED(ina_count) \
 	(USB_POWER_DATA_SIZE / USB_POWER_RECORD_SIZE(ina_count))
 
-
 struct usb_power_state {
 	/*
 	 * The power data acquisition must be setup, then started, in order to
@@ -212,7 +214,6 @@ struct usb_power_state {
 	uint8_t tx_buf[USB_MAX_PACKET_SIZE * 4];
 };
 
-
 /*
  * Compile time Per-USB gpio configuration stored in flash.  Instances of this
  * structure are provided by the user of the USB gpio.  This structure binds
@@ -234,12 +235,12 @@ struct usb_power_config {
 	const struct deferred_data *deferred_cap;
 };
 
-struct __attribute__ ((__packed__)) usb_power_command_start {
+struct __attribute__((__packed__)) usb_power_command_start {
 	uint16_t command;
 	uint32_t integration_us;
 };
 
-struct __attribute__ ((__packed__)) usb_power_command_addina {
+struct __attribute__((__packed__)) usb_power_command_addina {
 	uint16_t command;
 	uint8_t port;
 	uint8_t type;
@@ -248,7 +249,7 @@ struct __attribute__ ((__packed__)) usb_power_command_addina {
 	uint32_t rs;
 };
 
-struct __attribute__ ((__packed__)) usb_power_command_settime {
+struct __attribute__((__packed__)) usb_power_command_settime {
 	uint16_t command;
 	uint64_t time;
 };
@@ -260,7 +261,6 @@ union usb_power_command_data {
 	struct usb_power_command_settime settime;
 };
 
-
 /*
  * Convenience macro for defining a USB INA Power driver.
  *
@@ -273,92 +273,96 @@ union usb_power_command_data {
  * ENDPOINT is the index of the USB bulk endpoint used for receiving and
  * transmitting bytes.
  */
-#define USB_POWER_CONFIG(NAME,						\
-		       INTERFACE,					\
-		       ENDPOINT)					\
-	static void CONCAT2(NAME, _deferred_tx_)(void);			\
-	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_tx_));			\
-	static void CONCAT2(NAME, _deferred_rx_)(void);			\
-	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_rx_));			\
-	static void CONCAT2(NAME, _deferred_cap_)(void);		\
-	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_cap_));		\
-	struct usb_power_state CONCAT2(NAME, _state_) = {		\
-		.state = USB_POWER_STATE_OFF,				\
-		.ina_count = 0,						\
-		.integration_us = 0,					\
-		.reports_head = 0,					\
-		.reports_tail = 0,					\
-		.wall_offset = 0,					\
-	};								\
-	static struct dwc_usb_ep CONCAT2(NAME, _ep_ctl) = {		\
-		.max_packet = USB_MAX_PACKET_SIZE,			\
-		.tx_fifo = ENDPOINT,					\
-		.out_pending = 0,					\
-		.out_data = 0,						\
-		.out_databuffer = 0,					\
-		.out_databuffer_max = 0,				\
-		.rx_deferred = &CONCAT2(NAME, _deferred_rx__data),	\
-		.in_packets = 0,					\
-		.in_pending = 0,					\
-		.in_data = 0,						\
-		.in_databuffer = 0,					\
-		.in_databuffer_max = 0,					\
-		.tx_deferred = &CONCAT2(NAME, _deferred_tx__data),	\
-	};								\
-	struct usb_power_config const NAME = {				\
-		.state     = &CONCAT2(NAME, _state_),			\
-		.ep	= &CONCAT2(NAME, _ep_ctl),			\
-		.interface = INTERFACE,					\
-		.endpoint  = ENDPOINT,					\
-		.deferred_cap  = &CONCAT2(NAME, _deferred_cap__data),	\
-	};								\
-	const struct usb_interface_descriptor				\
-	USB_IFACE_DESC(INTERFACE) = {					\
-		.bLength	    = USB_DT_INTERFACE_SIZE,		\
-		.bDescriptorType    = USB_DT_INTERFACE,			\
-		.bInterfaceNumber   = INTERFACE,			\
-		.bAlternateSetting  = 0,				\
-		.bNumEndpoints      = 2,				\
-		.bInterfaceClass    = USB_CLASS_VENDOR_SPEC,		\
-		.bInterfaceSubClass = USB_SUBCLASS_GOOGLE_POWER,	\
-		.bInterfaceProtocol = USB_PROTOCOL_GOOGLE_POWER,	\
-		.iInterface	 = 0,				\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 0) = {					\
-		.bLength	  = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = 0x80 | ENDPOINT,			\
-		.bmAttributes     = 0x02 /* Bulk IN */,			\
-		.wMaxPacketSize   = USB_MAX_PACKET_SIZE,		\
-		.bInterval	= 1,					\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 1) = {					\
-		.bLength	  = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = ENDPOINT,				\
-		.bmAttributes     = 0x02 /* Bulk OUT */,		\
-		.wMaxPacketSize   = USB_MAX_PACKET_SIZE,		\
-		.bInterval	= 0,					\
-	};								\
-	static void CONCAT2(NAME, _ep_tx_)   (void) { usb_epN_tx(ENDPOINT); } \
-	static void CONCAT2(NAME, _ep_rx_)   (void) { usb_epN_rx(ENDPOINT); } \
-	static void CONCAT2(NAME, _ep_event_)(enum usb_ep_event evt)	\
-	{								\
-			usb_power_event(&NAME, evt);			\
-	}								\
-	USB_DECLARE_EP(ENDPOINT,					\
-		       CONCAT2(NAME, _ep_tx_),				\
-		       CONCAT2(NAME, _ep_rx_),				\
-		       CONCAT2(NAME, _ep_event_));			\
-	static void CONCAT2(NAME, _deferred_tx_)(void)			\
-	{ usb_power_deferred_tx(&NAME); }				\
-	static void CONCAT2(NAME, _deferred_rx_)(void)			\
-	{ usb_power_deferred_rx(&NAME); }				\
-	static void CONCAT2(NAME, _deferred_cap_)(void)			\
-	{ usb_power_deferred_cap(&NAME); }
-
+#define USB_POWER_CONFIG(NAME, INTERFACE, ENDPOINT)                         \
+	static void CONCAT2(NAME, _deferred_tx_)(void);                     \
+	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_tx_));                     \
+	static void CONCAT2(NAME, _deferred_rx_)(void);                     \
+	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_rx_));                     \
+	static void CONCAT2(NAME, _deferred_cap_)(void);                    \
+	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_cap_));                    \
+	struct usb_power_state CONCAT2(NAME, _state_) = {                   \
+		.state = USB_POWER_STATE_OFF,                               \
+		.ina_count = 0,                                             \
+		.integration_us = 0,                                        \
+		.reports_head = 0,                                          \
+		.reports_tail = 0,                                          \
+		.wall_offset = 0,                                           \
+	};                                                                  \
+	static struct dwc_usb_ep CONCAT2(NAME, _ep_ctl) = {                 \
+		.max_packet = USB_MAX_PACKET_SIZE,                          \
+		.tx_fifo = ENDPOINT,                                        \
+		.out_pending = 0,                                           \
+		.out_data = 0,                                              \
+		.out_databuffer = 0,                                        \
+		.out_databuffer_max = 0,                                    \
+		.rx_deferred = &CONCAT2(NAME, _deferred_rx__data),          \
+		.in_packets = 0,                                            \
+		.in_pending = 0,                                            \
+		.in_data = 0,                                               \
+		.in_databuffer = 0,                                         \
+		.in_databuffer_max = 0,                                     \
+		.tx_deferred = &CONCAT2(NAME, _deferred_tx__data),          \
+	};                                                                  \
+	struct usb_power_config const NAME = {                              \
+		.state = &CONCAT2(NAME, _state_),                           \
+		.ep = &CONCAT2(NAME, _ep_ctl),                              \
+		.interface = INTERFACE,                                     \
+		.endpoint = ENDPOINT,                                       \
+		.deferred_cap = &CONCAT2(NAME, _deferred_cap__data),        \
+	};                                                                  \
+	const struct usb_interface_descriptor USB_IFACE_DESC(INTERFACE) = { \
+		.bLength = USB_DT_INTERFACE_SIZE,                           \
+		.bDescriptorType = USB_DT_INTERFACE,                        \
+		.bInterfaceNumber = INTERFACE,                              \
+		.bAlternateSetting = 0,                                     \
+		.bNumEndpoints = 2,                                         \
+		.bInterfaceClass = USB_CLASS_VENDOR_SPEC,                   \
+		.bInterfaceSubClass = USB_SUBCLASS_GOOGLE_POWER,            \
+		.bInterfaceProtocol = USB_PROTOCOL_GOOGLE_POWER,            \
+		.iInterface = 0,                                            \
+	};                                                                  \
+	const struct usb_endpoint_descriptor USB_EP_DESC(INTERFACE, 0) = {  \
+		.bLength = USB_DT_ENDPOINT_SIZE,                            \
+		.bDescriptorType = USB_DT_ENDPOINT,                         \
+		.bEndpointAddress = 0x80 | ENDPOINT,                        \
+		.bmAttributes = 0x02 /* Bulk IN */,                         \
+		.wMaxPacketSize = USB_MAX_PACKET_SIZE,                      \
+		.bInterval = 1,                                             \
+	};                                                                  \
+	const struct usb_endpoint_descriptor USB_EP_DESC(INTERFACE, 1) = {  \
+		.bLength = USB_DT_ENDPOINT_SIZE,                            \
+		.bDescriptorType = USB_DT_ENDPOINT,                         \
+		.bEndpointAddress = ENDPOINT,                               \
+		.bmAttributes = 0x02 /* Bulk OUT */,                        \
+		.wMaxPacketSize = USB_MAX_PACKET_SIZE,                      \
+		.bInterval = 0,                                             \
+	};                                                                  \
+	static void CONCAT2(NAME, _ep_tx_)(void)                            \
+	{                                                                   \
+		usb_epN_tx(ENDPOINT);                                       \
+	}                                                                   \
+	static void CONCAT2(NAME, _ep_rx_)(void)                            \
+	{                                                                   \
+		usb_epN_rx(ENDPOINT);                                       \
+	}                                                                   \
+	static void CONCAT2(NAME, _ep_event_)(enum usb_ep_event evt)        \
+	{                                                                   \
+		usb_power_event(&NAME, evt);                                \
+	}                                                                   \
+	USB_DECLARE_EP(ENDPOINT, CONCAT2(NAME, _ep_tx_),                    \
+		       CONCAT2(NAME, _ep_rx_), CONCAT2(NAME, _ep_event_));  \
+	static void CONCAT2(NAME, _deferred_tx_)(void)                      \
+	{                                                                   \
+		usb_power_deferred_tx(&NAME);                               \
+	}                                                                   \
+	static void CONCAT2(NAME, _deferred_rx_)(void)                      \
+	{                                                                   \
+		usb_power_deferred_rx(&NAME);                               \
+	}                                                                   \
+	static void CONCAT2(NAME, _deferred_cap_)(void)                     \
+	{                                                                   \
+		usb_power_deferred_cap(&NAME);                              \
+	}
 
 /*
  * Handle power request in a deferred callback.
@@ -374,10 +378,6 @@ void usb_power_deferred_cap(struct usb_power_config const *config);
 void usb_power_tx(struct usb_power_config const *config);
 void usb_power_rx(struct usb_power_config const *config);
 void usb_power_event(struct usb_power_config const *config,
-		enum usb_ep_event evt);
-
-
-
+		     enum usb_ep_event evt);
 
 #endif /* __CROS_EC_USB_DWC_POWER_H */
-
diff --git a/chip/stm32/usb_spi.c b/chip/stm32/usb_spi.c
index 54caae015e..7e45563e4a 100644
--- a/chip/stm32/usb_spi.c
+++ b/chip/stm32/usb_spi.c
@@ -1,24 +1,160 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "common.h"
+#include "gpio.h"
 #include "link_defs.h"
 #include "registers.h"
 #include "spi.h"
+#include "timer.h"
 #include "usb_descriptor.h"
 #include "usb_hw.h"
 #include "usb_spi.h"
 #include "util.h"
 
+/* How long to wait for a flash page programming. */
+#define FLASH_BUSY_POLL_TIMEOUT_USEC (1000 * MSEC)
+
+const uint8_t JEDEC_READ_STATUS = 0x05;
+const uint8_t JEDEC_STATUS_BUSY = 0x01;
+
 /* Forward declare platform specific functions. */
-static bool usb_spi_received_packet(struct usb_spi_config const *config);
-static bool usb_spi_transmitted_packet(struct usb_spi_config const *config);
-static void usb_spi_read_packet(struct usb_spi_config const *config,
-			struct usb_spi_packet_ctx *packet);
-static void usb_spi_write_packet(struct usb_spi_config const *config,
-			struct usb_spi_packet_ctx *packet);
+static bool usb_spi_received_packet(void);
+static bool usb_spi_transmitted_packet(void);
+static void usb_spi_read_packet(struct usb_spi_packet_ctx *packet);
+static void usb_spi_write_packet(struct usb_spi_packet_ctx *packet);
+
+struct usb_spi_transfer_ctx {
+	/* Address of transfer buffer. */
+	uint8_t *buffer;
+	/* Number of bytes in the transfer. */
+	size_t transfer_size;
+	/* Number of bytes transferred. */
+	size_t transfer_index;
+};
+
+enum usb_spi_mode {
+	/* No tasks are required. */
+	USB_SPI_MODE_IDLE = 0,
+	/* Indicates the device needs to send it's USB SPI configuration.*/
+	USB_SPI_MODE_SEND_CONFIGURATION,
+	/* Indicates the device needs to respond to chip select. */
+	USB_SPI_MODE_SEND_CHIP_SELECT_RESPONSE,
+	/* Indicates we device needs start the SPI transfer. */
+	USB_SPI_MODE_START_SPI,
+	/* Indicates we should start a transfer response. */
+	USB_SPI_MODE_START_RESPONSE,
+	/* Indicates we need to continue a transfer response. */
+	USB_SPI_MODE_CONTINUE_RESPONSE,
+};
+
+struct usb_spi_state {
+	/*
+	 * The SPI bridge must be enabled both locally and by the host to allow
+	 * access to the SPI device.  The enabled_host flag is set and cleared
+	 * by sending USB_SPI_REQ_ENABLE and USB_SPI_REQ_DISABLE to the device
+	 * control endpoint.  The enabled_device flag is set by calling
+	 * usb_spi_enable.
+	 */
+	uint8_t enabled_host;
+	uint8_t enabled_device;
+
+	/*
+	 * The current enabled state.  This is only updated in the deferred
+	 * callback.  Whenever either of the host or device specific enable
+	 * flags is changed the deferred callback is queued, and it will check
+	 * their combined state against this flag.  If the combined state is
+	 * different, then one of usb_spi_board_enable or usb_spi_board_disable
+	 * is called and this flag is updated.  This ensures that the board
+	 * specific state update routines are only called from the deferred
+	 * callback.
+	 */
+	uint8_t enabled;
+
+	/*
+	 * The index of the SPI port currently receiving forwarded transactions,
+	 * default is zero.
+	 */
+	uint8_t current_spi_device_idx;
+
+	/* Mark the current operating mode. */
+	enum usb_spi_mode mode;
+
+	/*
+	 * Stores the status code response for the transfer, delivered in the
+	 * header for the first response packet. Error code is cleared during
+	 * first RX packet and set if a failure occurs.
+	 */
+	uint16_t status_code;
+
+	/* Stores the content from the USB packets */
+	struct usb_spi_packet_ctx receive_packet;
+	struct usb_spi_packet_ctx transmit_packet;
+
+	/*
+	 * Flags describing if and how multi-lane (dual/quad), double transfer
+	 * rate, and other advanced flash protocol features are to be used.
+	 */
+	uint32_t flash_flags;
+
+	/*
+	 * Context structures representing the progress receiving the SPI
+	 * write data and transmitting the SPI read data.
+	 */
+	struct usb_spi_transfer_ctx spi_write_ctx;
+	struct usb_spi_transfer_ctx spi_read_ctx;
+};
+
+/*
+ * Compile time Per-USB gpio configuration stored in flash.  Instances of this
+ * structure are provided by the user of the USB gpio.  This structure binds
+ * together all information required to operate a USB gpio.
+ */
+struct usb_spi_config {
+	/* Interface and endpoint indices. */
+	int interface;
+	int endpoint;
+
+	/* Deferred function to call to handle SPI request. */
+	const struct deferred_data *deferred;
+
+	/* Pointers to USB endpoint buffers. */
+	usb_uint *ep_rx_ram;
+	usb_uint *ep_tx_ram;
+};
+
+/*
+ * Handle SPI request in a deferred callback.
+ */
+void usb_spi_deferred(void);
+
+/*
+ * Storage of configuration and state of USB->SPI bridge.
+ */
+static uint16_t usb_spi_buffer_[(USB_SPI_BUFFER_SIZE + 1) / 2];
+static usb_uint usb_spi_ep_rx_buffer_[USB_MAX_PACKET_SIZE / 2] __usb_ram;
+static usb_uint usb_spi_ep_tx_buffer_[USB_MAX_PACKET_SIZE / 2] __usb_ram;
+
+static struct usb_spi_state usb_spi_state = {
+	.enabled_host = 0,
+	.enabled_device = 0,
+	.enabled = 0,
+	.current_spi_device_idx = 0,
+	.spi_write_ctx.buffer = (uint8_t *)usb_spi_buffer_,
+	.spi_read_ctx.buffer = (uint8_t *)usb_spi_buffer_,
+};
+
+DECLARE_DEFERRED(usb_spi_deferred);
+
+struct usb_spi_config const usb_spi = {
+	.interface = USB_IFACE_SPI,
+	.endpoint = USB_EP_SPI,
+	.deferred = &usb_spi_deferred_data,
+	.ep_rx_ram = usb_spi_ep_rx_buffer_,
+	.ep_tx_ram = usb_spi_ep_tx_buffer_,
+};
 
 /*
  * Map EC error codes to USB_SPI error codes.
@@ -30,10 +166,14 @@ static void usb_spi_write_packet(struct usb_spi_config const *config,
 static int16_t usb_spi_map_error(int error)
 {
 	switch (error) {
-	case EC_SUCCESS:       return USB_SPI_SUCCESS;
-	case EC_ERROR_TIMEOUT: return USB_SPI_TIMEOUT;
-	case EC_ERROR_BUSY:    return USB_SPI_BUSY;
-	default:               return USB_SPI_UNKNOWN_ERROR | (error & 0x7fff);
+	case EC_SUCCESS:
+		return USB_SPI_SUCCESS;
+	case EC_ERROR_TIMEOUT:
+		return USB_SPI_TIMEOUT;
+	case EC_ERROR_BUSY:
+		return USB_SPI_BUSY;
+	default:
+		return USB_SPI_UNKNOWN_ERROR | (error & 0x7fff);
 	}
 }
 
@@ -46,7 +186,7 @@ static int16_t usb_spi_map_error(int error)
  * @returns         USB_SPI_RX_DATA_OVERFLOW if the source packet is too large
  */
 static int usb_spi_read_usb_packet(struct usb_spi_transfer_ctx *dst,
-				const struct usb_spi_packet_ctx *src)
+				   const struct usb_spi_packet_ctx *src)
 {
 	size_t max_read_length = dst->transfer_size - dst->transfer_index;
 	size_t bytes_in_buffer = src->packet_size - src->header_size;
@@ -60,7 +200,7 @@ static int usb_spi_read_usb_packet(struct usb_spi_transfer_ctx *dst,
 		return USB_SPI_RX_DATA_OVERFLOW;
 	}
 	memcpy(dst->buffer + dst->transfer_index, packet_buffer,
-		bytes_in_buffer);
+	       bytes_in_buffer);
 
 	dst->transfer_index += bytes_in_buffer;
 	return USB_SPI_SUCCESS;
@@ -73,7 +213,7 @@ static int usb_spi_read_usb_packet(struct usb_spi_transfer_ctx *dst,
  * @param src       Source transmit context we are reading data from.
  */
 static void usb_spi_fill_usb_packet(struct usb_spi_packet_ctx *dst,
-				struct usb_spi_transfer_ctx *src)
+				    struct usb_spi_transfer_ctx *src)
 {
 	size_t transfer_size = src->transfer_size - src->transfer_index;
 	size_t max_buffer_size = USB_MAX_PACKET_SIZE - dst->header_size;
@@ -95,17 +235,16 @@ static void usb_spi_fill_usb_packet(struct usb_spi_packet_ctx *dst,
  * @param write_count   Number of bytes to write in the SPI transfer
  * @param read_count    Number of bytes to read in the SPI transfer
  */
-static void usb_spi_setup_transfer(struct usb_spi_config const *config,
-				size_t write_count, size_t read_count)
+static void usb_spi_setup_transfer(size_t write_count, size_t read_count)
 {
 	/* Reset any status code. */
-	config->state->status_code = USB_SPI_SUCCESS;
+	usb_spi_state.status_code = USB_SPI_SUCCESS;
 
 	/* Reset the write and read counts. */
-	config->state->spi_write_ctx.transfer_size = write_count;
-	config->state->spi_write_ctx.transfer_index = 0;
-	config->state->spi_read_ctx.transfer_size = read_count;
-	config->state->spi_read_ctx.transfer_index = 0;
+	usb_spi_state.spi_write_ctx.transfer_size = write_count;
+	usb_spi_state.spi_write_ctx.transfer_index = 0;
+	usb_spi_state.spi_read_ctx.transfer_size = read_count;
+	usb_spi_state.spi_read_ctx.transfer_index = 0;
 }
 
 /*
@@ -113,10 +252,10 @@ static void usb_spi_setup_transfer(struct usb_spi_config const *config,
  *
  * @param config        USB SPI config
  */
-static void usb_spi_reset_interface(struct usb_spi_config const *config)
+static void usb_spi_reset_interface(void)
 {
 	/* Setup a 0 byte transfer to clear the contexts. */
-	usb_spi_setup_transfer(config, 0, 0);
+	usb_spi_setup_transfer(0, 0);
 }
 
 /*
@@ -126,10 +265,10 @@ static void usb_spi_reset_interface(struct usb_spi_config const *config)
  *
  * @returns         	True if a response transfer is in progress.
  */
-static bool usb_spi_response_in_progress(struct usb_spi_config const *config)
+static bool usb_spi_response_in_progress(void)
 {
-	if ((config->state->mode == USB_SPI_MODE_START_RESPONSE) ||
-	    (config->state->mode == USB_SPI_MODE_CONTINUE_RESPONSE)) {
+	if ((usb_spi_state.mode == USB_SPI_MODE_START_RESPONSE) ||
+	    (usb_spi_state.mode == USB_SPI_MODE_CONTINUE_RESPONSE)) {
 		return true;
 	}
 	return false;
@@ -143,16 +282,15 @@ static bool usb_spi_response_in_progress(struct usb_spi_config const *config)
  * @param config        USB SPI config
  * @param status_code	status code to set for the response.
  */
-static void setup_transfer_response(struct usb_spi_config const *config,
-				uint16_t status_code)
+static void setup_transfer_response(uint16_t status_code)
 {
-	config->state->status_code = status_code;
-	config->state->spi_read_ctx.transfer_index = 0;
-	config->state->mode = USB_SPI_MODE_START_RESPONSE;
+	usb_spi_state.status_code = status_code;
+	usb_spi_state.spi_read_ctx.transfer_index = 0;
+	usb_spi_state.mode = USB_SPI_MODE_START_RESPONSE;
 
 	/* If an error occurred, transmit an empty start packet. */
 	if (status_code != USB_SPI_SUCCESS)
-		config->state->spi_read_ctx.transfer_size = 0;
+		usb_spi_state.spi_read_ctx.transfer_size = 0;
 }
 
 /*
@@ -161,9 +299,11 @@ static void setup_transfer_response(struct usb_spi_config const *config,
  * @param config        USB SPI config
  * @param packet        Packet buffer we will be transmitting.
  */
-static void create_spi_config_response(struct usb_spi_config const *config,
-				struct usb_spi_packet_ctx *packet)
+static void create_spi_config_response(struct usb_spi_packet_ctx *packet)
 {
+	const struct spi_device_t *current_device =
+		&spi_devices[usb_spi_state.current_spi_device_idx];
+
 	/* Construct the response packet. */
 	packet->rsp_config.packet_id = USB_SPI_PKT_ID_RSP_USB_SPI_CONFIG;
 	packet->rsp_config.max_write_count = USB_SPI_MAX_WRITE_COUNT;
@@ -174,8 +314,32 @@ static void create_spi_config_response(struct usb_spi_config const *config,
 	packet->rsp_config.feature_bitmap |=
 		USB_SPI_FEATURE_FULL_DUPLEX_SUPPORTED;
 #endif
-	packet->packet_size =
-		sizeof(struct usb_spi_response_configuration_v2);
+#ifdef CONFIG_USB_SPI_FLASH_EXTENSIONS
+	packet->rsp_config.feature_bitmap |= USB_SPI_FEATURE_FLASH_EXTENSIONS;
+	if (current_device->usb_flags & USB_SPI_FLASH_DUAL_SUPPORT)
+		packet->rsp_config.feature_bitmap |=
+			USB_SPI_FEATURE_DUAL_MODE_SUPPORTED;
+	if (current_device->usb_flags & USB_SPI_FLASH_QUAD_SUPPORT)
+		packet->rsp_config.feature_bitmap |=
+			USB_SPI_FEATURE_QUAD_MODE_SUPPORTED;
+	if (current_device->usb_flags & USB_SPI_FLASH_OCTO_SUPPORT)
+		packet->rsp_config.feature_bitmap |=
+			USB_SPI_FEATURE_OCTO_MODE_SUPPORTED;
+	if (current_device->usb_flags & USB_SPI_FLASH_DTR_SUPPORT)
+		packet->rsp_config.feature_bitmap |=
+			USB_SPI_FEATURE_DTR_SUPPORTED;
+#else
+	(void)current_device; /* Avoid warning about unused variable. */
+#endif
+	packet->packet_size = sizeof(struct usb_spi_response_configuration_v2);
+}
+
+static void create_spi_chip_select_response(struct usb_spi_packet_ctx *packet)
+{
+	/* Construct the response packet. */
+	packet->rsp_cs.packet_id = USB_SPI_PKT_ID_RSP_CHIP_SELECT;
+	packet->rsp_cs.status_code = 0;
+	packet->packet_size = sizeof(packet->rsp_cs);
 }
 
 /*
@@ -186,239 +350,397 @@ static void create_spi_config_response(struct usb_spi_config const *config,
  * @param config        USB SPI config
  * @param packet        Packet buffer we will be transmitting.
  */
-static void usb_spi_create_spi_transfer_response(
-				struct usb_spi_config const *config,
-				struct usb_spi_packet_ctx *transmit_packet)
+static void
+usb_spi_create_spi_transfer_response(struct usb_spi_packet_ctx *transmit_packet)
 {
-
-	if (!usb_spi_response_in_progress(config))
+	if (!usb_spi_response_in_progress())
 		return;
 
-	if (config->state->spi_read_ctx.transfer_index == 0) {
-
+	if (usb_spi_state.spi_read_ctx.transfer_index == 0) {
 		/* Transmit the first packet with the status code. */
 		transmit_packet->header_size =
 			offsetof(struct usb_spi_response_v2, data);
 		transmit_packet->rsp_start.packet_id =
 			USB_SPI_PKT_ID_RSP_TRANSFER_START;
 		transmit_packet->rsp_start.status_code =
-			config->state->status_code;
+			usb_spi_state.status_code;
 
 		usb_spi_fill_usb_packet(transmit_packet,
-			&config->state->spi_read_ctx);
-	} else if (config->state->spi_read_ctx.transfer_index <
-		config->state->spi_read_ctx.transfer_size) {
-
+					&usb_spi_state.spi_read_ctx);
+	} else if (usb_spi_state.spi_read_ctx.transfer_index <
+		   usb_spi_state.spi_read_ctx.transfer_size) {
 		/* Transmit the continue packets. */
 		transmit_packet->header_size =
 			offsetof(struct usb_spi_continue_v2, data);
 		transmit_packet->rsp_continue.packet_id =
 			USB_SPI_PKT_ID_RSP_TRANSFER_CONTINUE;
 		transmit_packet->rsp_continue.data_index =
-			config->state->spi_read_ctx.transfer_index;
+			usb_spi_state.spi_read_ctx.transfer_index;
 
 		usb_spi_fill_usb_packet(transmit_packet,
-			&config->state->spi_read_ctx);
+					&usb_spi_state.spi_read_ctx);
 	}
-	if (config->state->spi_read_ctx.transfer_index <
-		config->state->spi_read_ctx.transfer_size) {
-		config->state->mode = USB_SPI_MODE_CONTINUE_RESPONSE;
+	if (usb_spi_state.spi_read_ctx.transfer_index <
+	    usb_spi_state.spi_read_ctx.transfer_size) {
+		usb_spi_state.mode = USB_SPI_MODE_CONTINUE_RESPONSE;
 	} else {
-		config->state->mode = USB_SPI_MODE_IDLE;
+		usb_spi_state.mode = USB_SPI_MODE_IDLE;
 	}
 }
 
+#ifdef CONFIG_USB_SPI_FLASH_EXTENSIONS
+/*
+ * Decodes the header fields of a Flash Command Start Packet, and sets up the
+ * transaction depending on if it is read or write.
+ */
+static void setup_flash_transfer(struct usb_spi_packet_ctx *packet)
+{
+	const uint32_t flags = packet->cmd_flash_start.flags;
+	usb_spi_state.flash_flags = flags;
+	const uint8_t opcode_count = (flags & FLASH_FLAG_OPCODE_LEN_MSK) >>
+				     FLASH_FLAG_OPCODE_LEN_POS;
+	const uint8_t addr_count = (flags & FLASH_FLAG_ADDR_LEN_MSK) >>
+				   FLASH_FLAG_ADDR_LEN_POS;
+	const bool write_enable = !!(flags & FLASH_FLAG_WRITE_ENABLE);
+	if ((packet->cmd_flash_start.flags & FLASH_FLAG_READ_WRITE_MSK) ==
+	    FLASH_FLAG_READ_WRITE_WRITE) {
+		size_t write_count = packet->cmd_flash_start.count;
+		if (write_count > USB_SPI_MAX_WRITE_COUNT) {
+			usb_spi_state.status_code = USB_SPI_WRITE_COUNT_INVALID;
+			return;
+		}
+		usb_spi_setup_transfer(write_enable + opcode_count +
+					       addr_count + write_count,
+				       0);
+	} else {
+		size_t read_count = packet->cmd_flash_start.count;
+		if (read_count > USB_SPI_MAX_READ_COUNT) {
+			usb_spi_state.status_code = USB_SPI_WRITE_COUNT_INVALID;
+			return;
+		}
+		usb_spi_setup_transfer(write_enable + opcode_count + addr_count,
+				       read_count);
+	}
+	packet->header_size = offsetof(struct usb_spi_flash_command, data);
+	usb_spi_state.status_code =
+		usb_spi_read_usb_packet(&usb_spi_state.spi_write_ctx, packet);
+}
+#endif
+
 /*
  * Process the rx packet.
  *
  * @param config        USB SPI config
  * @param packet        Received packet to process.
  */
-static void usb_spi_process_rx_packet(struct usb_spi_config const *config,
-				struct usb_spi_packet_ctx *packet)
+static void usb_spi_process_rx_packet(struct usb_spi_packet_ctx *packet)
 {
 	if (packet->packet_size < USB_SPI_MIN_PACKET_SIZE) {
 		/* No valid packet exists smaller than the packet id. */
-		setup_transfer_response(config, USB_SPI_RX_UNEXPECTED_PACKET);
+		setup_transfer_response(USB_SPI_RX_UNEXPECTED_PACKET);
 		return;
 	}
 	/* Reset the mode until we've processed the packet. */
-	config->state->mode = USB_SPI_MODE_IDLE;
+	usb_spi_state.mode = USB_SPI_MODE_IDLE;
 
 	switch (packet->packet_id) {
-	case USB_SPI_PKT_ID_CMD_GET_USB_SPI_CONFIG:
-	{
+	case USB_SPI_PKT_ID_CMD_GET_USB_SPI_CONFIG: {
 		/* The host requires the SPI configuration. */
-		config->state->mode = USB_SPI_MODE_SEND_CONFIGURATION;
+		usb_spi_state.mode = USB_SPI_MODE_SEND_CONFIGURATION;
 		break;
 	}
-	case USB_SPI_PKT_ID_CMD_RESTART_RESPONSE:
-	{
+	case USB_SPI_PKT_ID_CMD_RESTART_RESPONSE: {
 		/*
 		 * The host has requested the device restart the last response.
 		 * This is used to recover from lost USB packets without
 		 * duplicating SPI transfers.
 		 */
-		setup_transfer_response(config, config->state->status_code);
+		setup_transfer_response(usb_spi_state.status_code);
 		break;
 	}
-	case USB_SPI_PKT_ID_CMD_TRANSFER_START:
-	{
+	case USB_SPI_PKT_ID_CMD_TRANSFER_START: {
 		/* The host started a new USB SPI transfer */
 		size_t write_count = packet->cmd_start.write_count;
 		size_t read_count = packet->cmd_start.read_count;
+		usb_spi_state.flash_flags = 0;
 
-		if (!config->state->enabled) {
-			setup_transfer_response(config, USB_SPI_DISABLED);
+		if (!usb_spi_state.enabled) {
+			setup_transfer_response(USB_SPI_DISABLED);
 		} else if (write_count > USB_SPI_MAX_WRITE_COUNT) {
-			setup_transfer_response(config,
-				USB_SPI_WRITE_COUNT_INVALID);
+			setup_transfer_response(USB_SPI_WRITE_COUNT_INVALID);
+#ifdef CONFIG_SPI_HALFDUPLEX
 		} else if (read_count == USB_SPI_FULL_DUPLEX_ENABLED) {
-#ifndef CONFIG_SPI_HALFDUPLEX
 			/* Full duplex mode is not supported on this device. */
-			setup_transfer_response(config,
+			setup_transfer_response(
 				USB_SPI_UNSUPPORTED_FULL_DUPLEX);
 #endif
 		} else if (read_count > USB_SPI_MAX_READ_COUNT &&
-				read_count != USB_SPI_FULL_DUPLEX_ENABLED) {
-			setup_transfer_response(config,
-				USB_SPI_READ_COUNT_INVALID);
+			   read_count != USB_SPI_FULL_DUPLEX_ENABLED) {
+			setup_transfer_response(USB_SPI_READ_COUNT_INVALID);
+		} else {
+			usb_spi_setup_transfer(write_count, read_count);
+			packet->header_size =
+				offsetof(struct usb_spi_command_v2, data);
+			usb_spi_state.status_code = usb_spi_read_usb_packet(
+				&usb_spi_state.spi_write_ctx, packet);
+		}
+
+		/* Send responses if we encountered an error. */
+		if (usb_spi_state.status_code != USB_SPI_SUCCESS) {
+			setup_transfer_response(usb_spi_state.status_code);
+			break;
+		}
+
+		/* Start the SPI transfer when we've read all data. */
+		if (usb_spi_state.spi_write_ctx.transfer_index ==
+		    usb_spi_state.spi_write_ctx.transfer_size) {
+			usb_spi_state.mode = USB_SPI_MODE_START_SPI;
+		}
+
+		break;
+	}
+#ifdef CONFIG_USB_SPI_FLASH_EXTENSIONS
+	case USB_SPI_PKT_ID_CMD_FLASH_TRANSFER_START: {
+		/* The host started a new USB serial flash SPI transfer */
+		if (!usb_spi_state.enabled) {
+			setup_transfer_response(USB_SPI_DISABLED);
 		} else {
-		        usb_spi_setup_transfer(config, write_count, read_count);
-		        packet->header_size =
-		        	offsetof(struct usb_spi_command_v2, data);
-		        config->state->status_code = usb_spi_read_usb_packet(
-		        	&config->state->spi_write_ctx, packet);
+			setup_flash_transfer(packet);
 		}
 
 		/* Send responses if we encountered an error. */
-		if (config->state->status_code != USB_SPI_SUCCESS) {
-			setup_transfer_response(config,
-				config->state->status_code);
+		if (usb_spi_state.status_code != USB_SPI_SUCCESS) {
+			setup_transfer_response(usb_spi_state.status_code);
 			break;
 		}
 
 		/* Start the SPI transfer when we've read all data. */
-		if (config->state->spi_write_ctx.transfer_index ==
-				config->state->spi_write_ctx.transfer_size) {
-			config->state->mode = USB_SPI_MODE_START_SPI;
+		if (usb_spi_state.spi_write_ctx.transfer_index ==
+		    usb_spi_state.spi_write_ctx.transfer_size) {
+			usb_spi_state.mode = USB_SPI_MODE_START_SPI;
 		}
 
 		break;
 	}
-	case USB_SPI_PKT_ID_CMD_TRANSFER_CONTINUE:
-	{
+#endif
+	case USB_SPI_PKT_ID_CMD_TRANSFER_CONTINUE: {
 		/*
 		 * The host has sent a continue packet for the SPI transfer
 		 * which contains additional data payload.
 		 */
 		packet->header_size =
 			offsetof(struct usb_spi_continue_v2, data);
-		if (config->state->status_code == USB_SPI_SUCCESS) {
-			config->state->status_code = usb_spi_read_usb_packet(
-					&config->state->spi_write_ctx, packet);
+		if (usb_spi_state.status_code == USB_SPI_SUCCESS) {
+			usb_spi_state.status_code = usb_spi_read_usb_packet(
+				&usb_spi_state.spi_write_ctx, packet);
 		}
 
 		/* Send responses if we encountered an error. */
-		if (config->state->status_code != USB_SPI_SUCCESS) {
-			setup_transfer_response(config,
-				config->state->status_code);
+		if (usb_spi_state.status_code != USB_SPI_SUCCESS) {
+			setup_transfer_response(usb_spi_state.status_code);
 			break;
 		}
 
 		/* Start the SPI transfer when we've read all data. */
-		if (config->state->spi_write_ctx.transfer_index ==
-				config->state->spi_write_ctx.transfer_size) {
-			config->state->mode = USB_SPI_MODE_START_SPI;
+		if (usb_spi_state.spi_write_ctx.transfer_index ==
+		    usb_spi_state.spi_write_ctx.transfer_size) {
+			usb_spi_state.mode = USB_SPI_MODE_START_SPI;
 		}
 
 		break;
 	}
-	default:
-	{
+	case USB_SPI_PKT_ID_CMD_CHIP_SELECT: {
+		/*
+		 * The host is requesting the chip select line be
+		 * asserted or deasserted.
+		 */
+		uint16_t flags = packet->cmd_cs.flags;
+		const struct spi_device_t *current_device =
+			&spi_devices[usb_spi_state.current_spi_device_idx];
+
+		if (flags & USB_SPI_CHIP_SELECT) {
+			/* Set chip select low (asserted). */
+			gpio_set_level(current_device->gpio_cs, 0);
+		} else {
+			/* Set chip select high (adesserted). */
+			gpio_set_level(current_device->gpio_cs, 1);
+		}
+		usb_spi_state.mode = USB_SPI_MODE_SEND_CHIP_SELECT_RESPONSE;
+		break;
+	}
+	default: {
 		/* An unknown USB packet was delivered. */
-		setup_transfer_response(config, USB_SPI_RX_UNEXPECTED_PACKET);
+		setup_transfer_response(USB_SPI_RX_UNEXPECTED_PACKET);
 		break;
 	}
 	}
 }
 
+/*
+ * Perform a SPI write-then-read transaction, optionally preceded by a single
+ * byte "write enable" (separated by deasserting chip select), and optionally
+ * followed by polling the "busy bit" until clear.
+ */
+static uint16_t do_spi_transfer(void)
+{
+	const struct spi_device_t *current_device =
+		&spi_devices[usb_spi_state.current_spi_device_idx];
+	bool custom_board_driver = current_device->usb_flags &
+				   USB_SPI_CUSTOM_SPI_DEVICE;
+	/*
+	 * If CONFIG_USB_SPI_FLASH_EXTENSIONS is not enabled, then the below
+	 * value being zero will allow the compiler to optimize away several
+	 * large if-blocks in this function.
+	 */
+	const uint32_t flash_flags =
+		IS_ENABLED(CONFIG_USB_SPI_FLASH_EXTENSIONS) ?
+			usb_spi_state.flash_flags :
+			0;
+	uint16_t status_code = EC_SUCCESS;
+	int read_count = usb_spi_state.spi_read_ctx.transfer_size;
+	const char *write_data_ptr = usb_spi_state.spi_write_ctx.buffer;
+	int write_count = usb_spi_state.spi_write_ctx.transfer_size;
+#ifndef CONFIG_SPI_HALFDUPLEX
+	/*
+	 * Handle the full duplex mode on supported platforms.
+	 * The read count is equal to the write count.
+	 */
+	if (read_count == USB_SPI_FULL_DUPLEX_ENABLED) {
+		usb_spi_state.spi_read_ctx.transfer_size =
+			usb_spi_state.spi_write_ctx.transfer_size;
+		read_count = SPI_READBACK_ALL;
+	}
+#endif
+
+	if (!custom_board_driver &&
+	    (flash_flags & FLASH_FLAGS_REQUIRING_SUPPORT)) {
+		/*
+		 * The standard spi_transaction() does not support
+		 * any multi-lane modes.
+		 */
+		return USB_SPI_UNSUPPORTED_FLASH_MODE;
+	}
+
+	if (status_code == EC_SUCCESS &&
+	    flash_flags & FLASH_FLAG_WRITE_ENABLE) {
+		/* Precede main transaction with one-byte "write enable". */
+		if (custom_board_driver) {
+			status_code = usb_spi_board_transaction(
+				current_device, 0, write_data_ptr, 1, NULL, 0);
+		} else {
+			status_code = spi_transaction(
+				current_device, write_data_ptr, 1, NULL, 0);
+		}
+		write_data_ptr += 1;
+		write_count -= 1;
+	}
+
+	if (status_code == EC_SUCCESS) {
+		if (custom_board_driver) {
+			status_code = usb_spi_board_transaction(
+				current_device, flash_flags, write_data_ptr,
+				write_count, usb_spi_state.spi_read_ctx.buffer,
+				read_count);
+		} else {
+			status_code = spi_transaction(
+				current_device, write_data_ptr, write_count,
+				usb_spi_state.spi_read_ctx.buffer, read_count);
+		}
+	}
+
+	if (flash_flags & FLASH_FLAG_POLL) {
+		/* After main transaction, poll until no longer "busy". */
+		static timestamp_t deadline;
+		deadline.val = get_time().val + FLASH_BUSY_POLL_TIMEOUT_USEC;
+
+		while (status_code == EC_SUCCESS) {
+			timestamp_t now;
+			uint8_t status_byte;
+			if (custom_board_driver) {
+				status_code = usb_spi_board_transaction(
+					current_device, 0, &JEDEC_READ_STATUS,
+					1, &status_byte, 1);
+			} else {
+				status_code = spi_transaction(
+					current_device, &JEDEC_READ_STATUS, 1,
+					&status_byte, 1);
+			}
+			if ((status_byte & JEDEC_STATUS_BUSY) == 0)
+				break;
+			now = get_time();
+			if (timestamp_expired(deadline, &now)) {
+				status_code = EC_ERROR_TIMEOUT;
+				break;
+			}
+		}
+	}
+	return usb_spi_map_error(status_code);
+}
+
 /* Deferred function to handle state changes, process USB SPI packets,
  * and construct responses.
  *
  * @param config        USB SPI config
  */
-void usb_spi_deferred(struct usb_spi_config const *config)
+void usb_spi_deferred(void)
 {
 	int enabled;
 	struct usb_spi_packet_ctx *receive_packet =
-		&config->state->receive_packet;
+		&usb_spi_state.receive_packet;
 	struct usb_spi_packet_ctx *transmit_packet =
-		&config->state->transmit_packet;
+		&usb_spi_state.transmit_packet;
 	transmit_packet->packet_size = 0;
 
-	if (config->flags & USB_SPI_CONFIG_FLAGS_IGNORE_HOST_SIDE_ENABLE)
-		enabled = config->state->enabled_device;
+	if (IS_ENABLED(CONFIG_USB_SPI_IGNORE_HOST_SIDE_ENABLE))
+		enabled = usb_spi_state.enabled_device;
 	else
-		enabled = config->state->enabled_device &&
-			  config->state->enabled_host;
+		enabled = usb_spi_state.enabled_device &&
+			  usb_spi_state.enabled_host;
 
 	/*
 	 * If our overall enabled state has changed we call the board specific
 	 * enable or disable routines and save our new state.
 	 */
-	if (enabled != config->state->enabled) {
-		if (enabled) usb_spi_board_enable(config);
-		else         usb_spi_board_disable(config);
+	if (enabled != usb_spi_state.enabled) {
+		if (enabled)
+			usb_spi_board_enable();
+		else
+			usb_spi_board_disable();
 
-		config->state->enabled = enabled;
+		usb_spi_state.enabled = enabled;
 	}
 
 	/* Read any packets from the endpoint. */
 
-	usb_spi_read_packet(config, receive_packet);
+	usb_spi_read_packet(receive_packet);
 	if (receive_packet->packet_size) {
-		usb_spi_process_rx_packet(config, receive_packet);
+		usb_spi_process_rx_packet(receive_packet);
 	}
 
 	/* Need to send the USB SPI configuration */
-	if (config->state->mode == USB_SPI_MODE_SEND_CONFIGURATION) {
-		create_spi_config_response(config, transmit_packet);
-		usb_spi_write_packet(config, transmit_packet);
-		config->state->mode = USB_SPI_MODE_IDLE;
+	if (usb_spi_state.mode == USB_SPI_MODE_SEND_CONFIGURATION) {
+		create_spi_config_response(transmit_packet);
+		usb_spi_write_packet(transmit_packet);
+		usb_spi_state.mode = USB_SPI_MODE_IDLE;
+		return;
+	}
+	/* Need to send response to USB SPI chip select. */
+	if (usb_spi_state.mode == USB_SPI_MODE_SEND_CHIP_SELECT_RESPONSE) {
+		create_spi_chip_select_response(transmit_packet);
+		usb_spi_write_packet(transmit_packet);
+		usb_spi_state.mode = USB_SPI_MODE_IDLE;
 		return;
 	}
 
 	/* Start a new SPI transfer. */
-	if (config->state->mode == USB_SPI_MODE_START_SPI) {
-		uint16_t status_code;
-		int read_count = config->state->spi_read_ctx.transfer_size;
-#ifndef CONFIG_SPI_HALFDUPLEX
-		/*
-		 * Handle the full duplex mode on supported platforms.
-		 * The read count is equal to the write count.
-		 */
-		if (read_count == USB_SPI_FULL_DUPLEX_ENABLED) {
-			config->state->spi_read_ctx.transfer_size =
-				config->state->spi_write_ctx.transfer_size;
-			read_count = SPI_READBACK_ALL;
-		}
-#endif
-		status_code = spi_transaction(SPI_FLASH_DEVICE,
-			config->state->spi_write_ctx.buffer,
-			config->state->spi_write_ctx.transfer_size,
-			config->state->spi_read_ctx.buffer,
-			read_count);
-
-		/* Cast the EC status code to USB SPI and start the response. */
-		status_code = usb_spi_map_error(status_code);
-		setup_transfer_response(config, status_code);
+	if (usb_spi_state.mode == USB_SPI_MODE_START_SPI) {
+		uint16_t status_code = do_spi_transfer();
+		setup_transfer_response(status_code);
 	}
 
-	if (usb_spi_response_in_progress(config) &&
-			usb_spi_transmitted_packet(config)) {
-		usb_spi_create_spi_transfer_response(config, transmit_packet);
-		usb_spi_write_packet(config, transmit_packet);
+	if (usb_spi_response_in_progress() && usb_spi_transmitted_packet()) {
+		usb_spi_create_spi_transfer_response(transmit_packet);
+		usb_spi_write_packet(transmit_packet);
 	}
 }
 
@@ -428,11 +750,11 @@ void usb_spi_deferred(struct usb_spi_config const *config)
  * @param config        USB SPI config
  * @param enabled       usb_spi_request indicating which SPI mode is enabled.
  */
-void usb_spi_enable(struct usb_spi_config const *config, int enabled)
+void usb_spi_enable(int enabled)
 {
-	config->state->enabled_device = enabled;
+	usb_spi_state.enabled_device = enabled;
 
-	hook_call_deferred(config->deferred, 0);
+	hook_call_deferred(usb_spi.deferred, 0);
 }
 
 /*
@@ -442,24 +764,24 @@ void usb_spi_enable(struct usb_spi_config const *config, int enabled)
  * @param config        USB SPI config
  * @param packet        Destination packet used to store the endpoint data.
  */
-static void usb_spi_read_packet(struct usb_spi_config const *config,
-				struct usb_spi_packet_ctx *packet)
+static void usb_spi_read_packet(struct usb_spi_packet_ctx *packet)
 {
 	size_t packet_size;
 
-	if (!usb_spi_received_packet(config)) {
+	if (!usb_spi_received_packet()) {
 		/* No data is present on the endpoint. */
 		packet->packet_size = 0;
 		return;
 	}
 
 	/* Copy bytes from endpoint memory. */
-	packet_size = btable_ep[config->endpoint].rx_count & RX_COUNT_MASK;
+	packet_size = btable_ep[usb_spi.endpoint].rx_count & RX_COUNT_MASK;
 	memcpy_from_usbram(packet->bytes,
-		(void *)usb_sram_addr(config->ep_rx_ram), packet_size);
+			   (void *)usb_sram_addr(usb_spi.ep_rx_ram),
+			   packet_size);
 	packet->packet_size = packet_size;
 	/* Set endpoint as valid for accepting new packet. */
-	STM32_TOGGLE_EP(config->endpoint, EP_RX_MASK, EP_RX_VALID, 0);
+	STM32_TOGGLE_EP(usb_spi.endpoint, EP_RX_MASK, EP_RX_VALID, 0);
 }
 
 /*
@@ -469,22 +791,21 @@ static void usb_spi_read_packet(struct usb_spi_config const *config,
  * @param config        USB SPI config
  * @param packet        Source packet we will write to the endpoint data.
  */
-static void usb_spi_write_packet(struct usb_spi_config const *config,
-				struct usb_spi_packet_ctx *packet)
+static void usb_spi_write_packet(struct usb_spi_packet_ctx *packet)
 {
 	if (packet->packet_size == 0)
 		return;
 
 	/* Copy bytes to endpoint memory. */
-	memcpy_to_usbram((void *)usb_sram_addr(config->ep_tx_ram),
-		packet->bytes, packet->packet_size);
-	btable_ep[config->endpoint].tx_count = packet->packet_size;
+	memcpy_to_usbram((void *)usb_sram_addr(usb_spi.ep_tx_ram),
+			 packet->bytes, packet->packet_size);
+	btable_ep[usb_spi.endpoint].tx_count = packet->packet_size;
 
 	/* Mark the packet as having no data. */
 	packet->packet_size = 0;
 
 	/* Set endpoint as valid for transmitting new packet. */
-	STM32_TOGGLE_EP(config->endpoint, EP_TX_MASK, EP_TX_VALID, 0);
+	STM32_TOGGLE_EP(usb_spi.endpoint, EP_TX_MASK, EP_TX_VALID, 0);
 }
 
 /*
@@ -494,9 +815,9 @@ static void usb_spi_write_packet(struct usb_spi_config const *config,
  *
  * @returns             Returns true when the RX endpoint has a packet.
  */
-static bool usb_spi_received_packet(struct usb_spi_config const *config)
+static bool usb_spi_received_packet(void)
 {
-	return (STM32_USB_EP(config->endpoint) & EP_RX_MASK) != EP_RX_VALID;
+	return (STM32_USB_EP(usb_spi.endpoint) & EP_RX_MASK) != EP_RX_VALID;
 }
 
 /* STM32 Platform: Returns the TX endpoint status
@@ -506,16 +827,16 @@ static bool usb_spi_received_packet(struct usb_spi_config const *config)
  * @returns             Returns true when the TX endpoint transmitted
  *                      the packet written.
  */
-static bool usb_spi_transmitted_packet(struct usb_spi_config const *config)
+static bool usb_spi_transmitted_packet(void)
 {
-	return (STM32_USB_EP(config->endpoint) & EP_TX_MASK) != EP_TX_VALID;
+	return (STM32_USB_EP(usb_spi.endpoint) & EP_TX_MASK) != EP_TX_VALID;
 }
 
 /* STM32 Platform: Handle interrupt for USB data received.
  *
  * @param config        USB SPI config
  */
-void usb_spi_rx(struct usb_spi_config const *config)
+void usb_spi_rx(void)
 {
 	/*
 	 * We need to set both the TX and RX endpoints to NAK to prevent
@@ -528,9 +849,9 @@ void usb_spi_rx(struct usb_spi_config const *config)
 	 * This has a side effect of disabling the endpoint interrupts until
 	 * they are set to valid or a USB reset events occurs.
 	 */
-	STM32_TOGGLE_EP(config->endpoint, EP_TX_RX_MASK, EP_TX_RX_NAK, 0);
+	STM32_TOGGLE_EP(usb_spi.endpoint, EP_TX_RX_MASK, EP_TX_RX_NAK, 0);
 
-	hook_call_deferred(config->deferred, 0);
+	hook_call_deferred(usb_spi.deferred, 0);
 }
 
 /*
@@ -538,11 +859,11 @@ void usb_spi_rx(struct usb_spi_config const *config)
  *
  * @param config        USB SPI config
  */
-void usb_spi_tx(struct usb_spi_config const *config)
+void usb_spi_tx(void)
 {
-	STM32_TOGGLE_EP(config->endpoint, EP_TX_MASK, EP_TX_NAK, 0);
+	STM32_TOGGLE_EP(usb_spi.endpoint, EP_TX_MASK, EP_TX_NAK, 0);
 
-	hook_call_deferred(config->deferred, 0);
+	hook_call_deferred(usb_spi.deferred, 0);
 }
 
 /*
@@ -551,28 +872,28 @@ void usb_spi_tx(struct usb_spi_config const *config)
  * @param config        USB SPI config
  * @param evt           USB event
  */
-void usb_spi_event(struct usb_spi_config const *config, enum usb_ep_event evt)
+void usb_spi_event(enum usb_ep_event evt)
 {
 	int endpoint;
 
 	if (evt != USB_EVENT_RESET)
 		return;
 
-	endpoint = config->endpoint;
+	endpoint = usb_spi.endpoint;
 
-	usb_spi_reset_interface(config);
+	usb_spi_reset_interface();
 
-	btable_ep[endpoint].tx_addr  = usb_sram_addr(config->ep_tx_ram);
+	btable_ep[endpoint].tx_addr = usb_sram_addr(usb_spi.ep_tx_ram);
 	btable_ep[endpoint].tx_count = 0;
 
-	btable_ep[endpoint].rx_addr  = usb_sram_addr(config->ep_rx_ram);
-	btable_ep[endpoint].rx_count =
-		0x8000 | ((USB_MAX_PACKET_SIZE / 32 - 1) << 10);
+	btable_ep[endpoint].rx_addr = usb_sram_addr(usb_spi.ep_rx_ram);
+	btable_ep[endpoint].rx_count = 0x8000 |
+				       ((USB_MAX_PACKET_SIZE / 32 - 1) << 10);
 
-	STM32_USB_EP(endpoint) = ((endpoint <<  0) | /* Endpoint Addr*/
-				  (2        <<  4) | /* TX NAK */
-				  (0        <<  9) | /* Bulk EP */
-				  (3        << 12)); /* RX Valid */
+	STM32_USB_EP(endpoint) = ((endpoint << 0) | /* Endpoint Addr*/
+				  (2 << 4) | /* TX NAK */
+				  (0 << 9) | /* Bulk EP */
+				  (3 << 12)); /* RX Valid */
 }
 
 /*
@@ -582,46 +903,88 @@ void usb_spi_event(struct usb_spi_config const *config, enum usb_ep_event evt)
  * @param rx_buf        Contains setup packet
  * @param tx_buf        unused
  */
-int usb_spi_interface(struct usb_spi_config const *config,
-		      usb_uint *rx_buf,
-		      usb_uint *tx_buf)
+int usb_spi_interface(usb_uint *rx_buf, usb_uint *tx_buf)
 {
 	struct usb_setup_packet setup;
 
 	usb_read_setup_packet(rx_buf, &setup);
 
-	if (setup.bmRequestType != (USB_DIR_OUT |
-				    USB_TYPE_VENDOR |
-				    USB_RECIP_INTERFACE))
+	if (setup.bmRequestType !=
+	    (USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_INTERFACE))
 		return 1;
 
-	if (setup.wValue  != 0 ||
-	    setup.wIndex  != config->interface ||
-	    setup.wLength != 0)
+	if (setup.wValue >= spi_devices_used ||
+	    !(spi_devices[setup.wValue].usb_flags & USB_SPI_ENABLED) ||
+	    setup.wIndex != usb_spi.interface || setup.wLength != 0)
 		return 1;
 
+	/* Record which SPI device the host wished to manipulate. */
+	usb_spi_state.current_spi_device_idx = setup.wValue;
+
 	switch (setup.bRequest) {
 	case USB_SPI_REQ_ENABLE:
-		config->state->enabled_host = 1;
+		usb_spi_state.enabled_host = 1;
 		break;
 
 	case USB_SPI_REQ_DISABLE:
-		config->state->enabled_host = 0;
+		usb_spi_state.enabled_host = 0;
 		break;
 
-	default: return 1;
+	default:
+		return 1;
 	}
 
 	/*
 	 * Our state has changed, call the deferred function to handle the
 	 * state change.
 	 */
-	if (!(config->flags & USB_SPI_CONFIG_FLAGS_IGNORE_HOST_SIDE_ENABLE))
-		hook_call_deferred(config->deferred, 0);
+	if (!IS_ENABLED(CONFIG_USB_SPI_IGNORE_HOST_SIDE_ENABLE))
+		hook_call_deferred(usb_spi.deferred, 0);
 
-	usb_spi_reset_interface(config);
+	usb_spi_reset_interface();
 
 	btable_ep[0].tx_count = 0;
 	STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, EP_STATUS_OUT);
 	return 0;
 }
+
+__overridable int
+usb_spi_board_transaction(const struct spi_device_t *spi_device,
+			  uint32_t flash_flags, const uint8_t *txdata,
+			  int txlen, uint8_t *rxdata, int rxlen)
+{
+	return EC_ERROR_UNIMPLEMENTED;
+}
+
+/*
+ * Register this file with the low-level USB driver.
+ */
+const struct usb_interface_descriptor USB_IFACE_DESC(USB_IFACE_SPI) = {
+	.bLength = USB_DT_INTERFACE_SIZE,
+	.bDescriptorType = USB_DT_INTERFACE,
+	.bInterfaceNumber = USB_IFACE_SPI,
+	.bAlternateSetting = 0,
+	.bNumEndpoints = 2,
+	.bInterfaceClass = USB_CLASS_VENDOR_SPEC,
+	.bInterfaceSubClass = USB_SUBCLASS_GOOGLE_SPI,
+	.bInterfaceProtocol = USB_PROTOCOL_GOOGLE_SPI,
+	.iInterface = USB_STR_SPI_NAME,
+};
+const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_SPI, 0) = {
+	.bLength = USB_DT_ENDPOINT_SIZE,
+	.bDescriptorType = USB_DT_ENDPOINT,
+	.bEndpointAddress = 0x80 | USB_EP_SPI,
+	.bmAttributes = 0x02 /* Bulk IN */,
+	.wMaxPacketSize = USB_MAX_PACKET_SIZE,
+	.bInterval = 10,
+};
+const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_SPI, 1) = {
+	.bLength = USB_DT_ENDPOINT_SIZE,
+	.bDescriptorType = USB_DT_ENDPOINT,
+	.bEndpointAddress = USB_EP_SPI,
+	.bmAttributes = 0x02 /* Bulk OUT */,
+	.wMaxPacketSize = USB_MAX_PACKET_SIZE,
+	.bInterval = 0,
+};
+USB_DECLARE_EP(USB_EP_SPI, usb_spi_tx, usb_spi_rx, usb_spi_event);
+USB_DECLARE_IFACE(USB_IFACE_SPI, usb_spi_interface);
diff --git a/chip/stm32/usb_spi.h b/chip/stm32/usb_spi.h
index 591975234d..7ca5a57a7a 100644
--- a/chip/stm32/usb_spi.h
+++ b/chip/stm32/usb_spi.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -146,6 +146,7 @@
  *         0x0008: An unexpected packet arrived that the device could not
  *             process.
  *         0x0009: The device does not support full duplex mode.
+ *         0x000A: Requested serial flash mode not supported
  *         0x8000: Unknown error mask
  *             The bottom 15 bits will contain the bottom 15 bits from the EC
  *             error code.
@@ -218,7 +219,12 @@
  *
  *     feature bitmap:    Bitmap of supported features.
  *                        BIT(0): Full duplex SPI mode is supported
- *                        BIT(1:15): Reserved for future use
+ *                        BIT(1): Serial flash extensions are supported
+ *                        BIT(2): Dual mode flash supported
+ *                        BIT(3): Quad mode flash supported
+ *                        BIT(4): Octo mode flash supported
+ *                        BIT(5): Double transfer rate supported
+ *                        BIT(6:15): Reserved for future use
  *
  * Command Restart Response Packet (Host to Device):
  *
@@ -232,6 +238,88 @@
  *
  *     packet id:         2 byte enum USB_SPI_PKT_ID_CMD_RESTART_RESPONSE
  *
+ * Command chip select Packet (Host to Device):
+ *
+ *     +----------------+-------------+
+ *     | packet id : 2B | action : 2B |
+ *     +----------------+-------------+
+ *
+ *     packet id:         2 byte enum USB_SPI_PKT_ID_CMD_CHIP_SELECT
+ *
+ *     action:            2 byte, current options:
+ *                            0: Deassert chip select
+ *                            1: Assert chip select
+ *
+ * Response chip select Packet (Device to Host):
+ *
+ *     +----------------+------------------+
+ *     | packet id : 2B | status code : 2B |
+ *     +----------------+------------------+
+ *
+ *     packet id:     2 byte enum USB_SPI_PKT_ID_RSP_CHIP_SELECT
+ *
+ *     status code: 2 byte status code
+ *         0x0000: Success
+ *         others: Error
+ *
+ * Flash Command Start Packet (Host to Device):
+ *
+ *      Start of the USB serial flash SPI command, contains the number of
+ *      bytes to write or read on SPI and up to the first 58 bytes of write
+ *      payload.  Longer writes will use the continue packets with packet id
+ *      USB_SPI_PKT_ID_CMD_TRANSFER_CONTINUE to transmit the remaining data.
+ *
+ *      The reading or writing of the "main" data will be preceded by an
+ *      short sequence of opcode, optional address, optional "alternate data",
+ *      and optional 'dummy cycles" on the SPI bus.  Flags indicate how many
+ *      bytes of each stage to send, and whether to use advanced features such
+ *      as dual or quad signal lanes for each stage of the transfer".
+ *
+ *      The indicated number of opcode, address and alternate bytes will be
+ *      the first in the "write payload".  The "count" field will contain the
+ *      number of data bytes to be written/read after the opcode, address and
+ *      alternate bytes.
+ *
+ *      This request is only supported if bit 1 of the "feature bitmap"
+ *      indicates that serial flash extensions are supported.  Implementations
+ *      will further advertise whether they support dual, quad or octo modes, if
+ *      none of these are supported, then support for "dummy cycles" is not
+ *      guaranteed either, and callers should use one or two bytes of "extra
+ *      address data" for dummy cycles, address length can be up to 7 bytes for
+ *      this reason.
+ *
+ *     +----------------+------------+------------+---------------+
+ *     | packet id : 2B | count : 2B | flags : 4B | w.p. : <= 56B |
+ *     +----------------+------------+------------+---------------+
+ *
+ *     packet id:     2 byte enum defined by packet_id_type
+ *                    Valid values packet id =
+ *                    USB_SPI_PKT_ID_CMD_FLASH_TRANSFER_START
+ *
+ *     count:         2 byte, zero based count of bytes to read or write
+ *
+ *     flags:         4 byte, flags
+ *          bits 0:1  opcode length in bytes (0-3)
+ *          bits 2:4  address length in bytes (0-7)
+ *          bits 5:6  mode (0: 1-1-1, 1: 1-1-N, 2: 1-N-N, 3: N-N-N)
+ *          bits 7:8  width (0: N=1, 1: N=2, 2: N=4, 3: N=8)
+ *             bit 9  double transfer rate (in phases marked as N)
+ *        bits 10:14  number of dummy cycles (0-31)
+ *        bits 15:27  reserved, must be zero
+ *            bit 28  write to be preceded by "write enable"
+ *            bit 29  write to be followed by polling of JEDEC "busy bit"
+ *            bit 30  reserved, must be zero
+ *            bit 31  read (0) / write (1)
+ *
+ *     write payload: Up to 56 bytes of data to write to SPI, the total length
+ *                    of all TX packets must match: write enable length (zero or
+ *                    one, depending on bit 27) + opcode length + address length
+ *                    + count, (the last one only if bit 31 indicates a write
+ *                    operation). Due to data alignment constraints, this must
+ *                    be an even number of bytes unless this is the final
+ *                    packet.
+ *
+ *
  * USB Error Codes:
  *
  * send_command return codes have the following format:
@@ -244,47 +332,95 @@
  *                      http://libusb.sourceforge.net/api-1.0/group__misc.html
  */
 
-#define USB_SPI_FULL_DUPLEX_ENABLED         (UINT16_MAX)
+#define USB_SPI_FULL_DUPLEX_ENABLED (UINT16_MAX)
 
-#define USB_SPI_PAYLOAD_SIZE_V2_START       (58)
+#define USB_SPI_PAYLOAD_SIZE_V2_START (58)
 
-#define USB_SPI_PAYLOAD_SIZE_V2_RESPONSE    (60)
+#define USB_SPI_PAYLOAD_SIZE_V2_RESPONSE (60)
 
-#define USB_SPI_PAYLOAD_SIZE_V2_CONTINUE    (60)
+#define USB_SPI_PAYLOAD_SIZE_V2_CONTINUE (60)
 
-#define USB_SPI_PAYLOAD_SIZE_V2_ERROR       (60)
+#define USB_SPI_PAYLOAD_SIZE_V2_ERROR (60)
 
-#define USB_SPI_MIN_PACKET_SIZE             (2)
+#define USB_SPI_PAYLOAD_SIZE_FLASH_START (56)
+
+#define USB_SPI_MIN_PACKET_SIZE (2)
+
+/*
+ * Values used in spi_device_t.usb_flags
+ */
+
+/* Is the USB host allowed to operate on SPI device. */
+#define USB_SPI_ENABLED BIT(0)
+/* Use board specific SPI driver when forwarding to this device. */
+#define USB_SPI_CUSTOM_SPI_DEVICE BIT(1)
+/* This SPI device supports dual lane mode. */
+#define USB_SPI_FLASH_DUAL_SUPPORT BIT(2)
+/* This SPI device supports four lane mode. */
+#define USB_SPI_FLASH_QUAD_SUPPORT BIT(3)
+/* This SPI device supports eight lane mode. */
+#define USB_SPI_FLASH_OCTO_SUPPORT BIT(4)
+/* This SPI device supports double transfer rate (data on both clock edges). */
+#define USB_SPI_FLASH_DTR_SUPPORT BIT(5)
 
 enum packet_id_type {
 	/* Request USB SPI configuration data from device. */
 	USB_SPI_PKT_ID_CMD_GET_USB_SPI_CONFIG = 0,
 	/* USB SPI configuration data from device. */
-	USB_SPI_PKT_ID_RSP_USB_SPI_CONFIG     = 1,
+	USB_SPI_PKT_ID_RSP_USB_SPI_CONFIG = 1,
 	/*
 	 * Start a USB SPI transfer specifying number of bytes to write,
 	 * read and deliver first packet of data to write.
 	 */
-	USB_SPI_PKT_ID_CMD_TRANSFER_START     = 2,
+	USB_SPI_PKT_ID_CMD_TRANSFER_START = 2,
 	/* Additional packets containing write payload. */
-	USB_SPI_PKT_ID_CMD_TRANSFER_CONTINUE  = 3,
+	USB_SPI_PKT_ID_CMD_TRANSFER_CONTINUE = 3,
 	/*
 	 * Request the device restart the response enabling us to recover
 	 * from packet loss without another SPI transfer.
 	 */
-	USB_SPI_PKT_ID_CMD_RESTART_RESPONSE   = 4,
+	USB_SPI_PKT_ID_CMD_RESTART_RESPONSE = 4,
 	/*
 	 * First packet of USB SPI response with the status code
 	 * and read payload if it was successful.
 	 */
-	USB_SPI_PKT_ID_RSP_TRANSFER_START     = 5,
+	USB_SPI_PKT_ID_RSP_TRANSFER_START = 5,
 	/* Additional packets containing read payload. */
-	USB_SPI_PKT_ID_RSP_TRANSFER_CONTINUE  = 6,
+	USB_SPI_PKT_ID_RSP_TRANSFER_CONTINUE = 6,
+	/*
+	 * Request assertion or deassertion of chip select
+	 */
+	USB_SPI_PKT_ID_CMD_CHIP_SELECT = 7,
+	/* Response to above request. */
+	USB_SPI_PKT_ID_RSP_CHIP_SELECT = 8,
+	/*
+	 * Start a USB serial flash SPI transfer.
+	 */
+	USB_SPI_PKT_ID_CMD_FLASH_TRANSFER_START = 9,
 };
 
 enum feature_bitmap {
 	/* Indicates the platform supports full duplex mode. */
-	USB_SPI_FEATURE_FULL_DUPLEX_SUPPORTED = BIT(0)
+	USB_SPI_FEATURE_FULL_DUPLEX_SUPPORTED = BIT(0),
+	/* Indicates support for USB_SPI_PKT_ID_CMD_FLASH_TRANSFER_START. */
+	USB_SPI_FEATURE_FLASH_EXTENSIONS = BIT(1),
+	/*
+	 * Indicates that chip and any MUXes support bidirectional data on the
+	 * two SPI data lines.
+	 */
+	USB_SPI_FEATURE_DUAL_MODE_SUPPORTED = BIT(2),
+	/*
+	 * Indicates that chip and any MUXes support bidirectional data on the
+	 * "hold" and "write protect" lines.
+	 */
+	USB_SPI_FEATURE_QUAD_MODE_SUPPORTED = BIT(3),
+	/* Indicates support for eight-line bidirectional data. */
+	USB_SPI_FEATURE_OCTO_MODE_SUPPORTED = BIT(4),
+	/*
+	 * Indicates support for double transfer rate, i.e. data bit shift on
+	 * both rising and falling clock edges.
+	 */
+	USB_SPI_FEATURE_DTR_SUPPORTED = BIT(5),
 };
 
 struct usb_spi_response_configuration_v2 {
@@ -314,15 +450,57 @@ struct usb_spi_continue_v2 {
 	uint8_t data[USB_SPI_PAYLOAD_SIZE_V2_CONTINUE];
 } __packed;
 
+enum chip_select_flags {
+	/* Indicates chip select should be asserted. */
+	USB_SPI_CHIP_SELECT = BIT(0)
+};
+
+struct usb_spi_chip_select_command {
+	uint16_t packet_id;
+	uint16_t flags;
+} __packed;
+
+struct usb_spi_chip_select_response {
+	uint16_t packet_id;
+	uint16_t status_code;
+} __packed;
+
+struct usb_spi_flash_command {
+	uint16_t packet_id;
+	uint16_t count;
+	uint32_t flags;
+	uint8_t data[USB_SPI_PAYLOAD_SIZE_FLASH_START];
+} __packed;
+
+/*
+ * Mask of the flags that are handled by logic in sub_spi.c, and not passed to
+ * SPI drivers through usb_spi_board_transaction().
+ */
+#define FLASH_FLAGS_NONBOARD 0xF0000000UL
+
+#define FLASH_FLAG_WRITE_ENABLE_POS 28U
+#define FLASH_FLAG_WRITE_ENABLE (0x1UL << FLASH_FLAG_WRITE_ENABLE_POS)
+
+#define FLASH_FLAG_POLL_POS 29U
+#define FLASH_FLAG_POLL (0x1UL << FLASH_FLAG_POLL_POS)
+
+#define FLASH_FLAG_READ_WRITE_POS 31U
+#define FLASH_FLAG_READ_WRITE_MSK (0x1UL << FLASH_FLAG_READ_WRITE_POS)
+#define FLASH_FLAG_READ_WRITE_READ 0
+#define FLASH_FLAG_READ_WRITE_WRITE (0x1UL << FLASH_FLAG_READ_WRITE_POS)
+
 struct usb_spi_packet_ctx {
 	union {
 		uint8_t bytes[USB_MAX_PACKET_SIZE];
 		uint16_t packet_id;
 		struct usb_spi_command_v2 cmd_start;
+		struct usb_spi_flash_command cmd_flash_start;
 		struct usb_spi_continue_v2 cmd_continue;
 		struct usb_spi_response_configuration_v2 rsp_config;
 		struct usb_spi_response_v2 rsp_start;
 		struct usb_spi_continue_v2 rsp_continue;
+		struct usb_spi_chip_select_command cmd_cs;
+		struct usb_spi_chip_select_response rsp_cs;
 	} __packed;
 	/*
 	 * By storing the number of bytes in the header and knowing that the
@@ -336,25 +514,27 @@ struct usb_spi_packet_ctx {
 };
 
 enum usb_spi_error {
-	USB_SPI_SUCCESS                 = 0x0000,
-	USB_SPI_TIMEOUT                 = 0x0001,
-	USB_SPI_BUSY                    = 0x0002,
-	USB_SPI_WRITE_COUNT_INVALID     = 0x0003,
-	USB_SPI_READ_COUNT_INVALID      = 0x0004,
-	USB_SPI_DISABLED                = 0x0005,
+	USB_SPI_SUCCESS = 0x0000,
+	USB_SPI_TIMEOUT = 0x0001,
+	USB_SPI_BUSY = 0x0002,
+	USB_SPI_WRITE_COUNT_INVALID = 0x0003,
+	USB_SPI_READ_COUNT_INVALID = 0x0004,
+	USB_SPI_DISABLED = 0x0005,
 	/* The RX continue packet's data index is invalid. */
-	USB_SPI_RX_BAD_DATA_INDEX       = 0x0006,
+	USB_SPI_RX_BAD_DATA_INDEX = 0x0006,
 	/* The RX endpoint has received more data than write count. */
-	USB_SPI_RX_DATA_OVERFLOW        = 0x0007,
+	USB_SPI_RX_DATA_OVERFLOW = 0x0007,
 	/* An unexpected packet arrived on the device. */
-	USB_SPI_RX_UNEXPECTED_PACKET    = 0x0008,
+	USB_SPI_RX_UNEXPECTED_PACKET = 0x0008,
 	/* The device does not support full duplex mode. */
 	USB_SPI_UNSUPPORTED_FULL_DUPLEX = 0x0009,
-	USB_SPI_UNKNOWN_ERROR           = 0x8000,
+	/* The device does not support dual/quad wire mode. */
+	USB_SPI_UNSUPPORTED_FLASH_MODE = 0x000A,
+	USB_SPI_UNKNOWN_ERROR = 0x8000,
 };
 
 enum usb_spi_request {
-	USB_SPI_REQ_ENABLE  = 0x0000,
+	USB_SPI_REQ_ENABLE = 0x0000,
 	USB_SPI_REQ_DISABLE = 0x0001,
 };
 
@@ -366,229 +546,92 @@ enum usb_spi_request {
  * If a platform has a small maximum SPI transfer size, it can be optimized
  * by setting these limits to the maximum transfer size.
  */
-#define USB_SPI_BUFFER_SIZE	(USB_SPI_PAYLOAD_SIZE_V2_START + \
-				(4 * USB_SPI_PAYLOAD_SIZE_V2_CONTINUE))
-#define USB_SPI_MAX_WRITE_COUNT	USB_SPI_BUFFER_SIZE
-#define USB_SPI_MAX_READ_COUNT	USB_SPI_BUFFER_SIZE
-
-struct usb_spi_transfer_ctx {
-	/* Address of transfer buffer. */
-	uint8_t *buffer;
-	/* Number of bytes in the transfer. */
-	size_t transfer_size;
-	/* Number of bytes transferred. */
-	size_t transfer_index;
-};
-
-enum usb_spi_mode {
-	/* No tasks are required. */
-	USB_SPI_MODE_IDLE = 0,
-	/* Indicates the device needs to send it's USB SPI configuration.*/
-	USB_SPI_MODE_SEND_CONFIGURATION,
-	/* Indicates we device needs start the SPI transfer. */
-	USB_SPI_MODE_START_SPI,
-	/* Indicates we should start a transfer response. */
-	USB_SPI_MODE_START_RESPONSE,
-	/* Indicates we need to continue a transfer response. */
-	USB_SPI_MODE_CONTINUE_RESPONSE,
-};
-
-struct usb_spi_state {
-	/*
-	 * The SPI bridge must be enabled both locally and by the host to allow
-	 * access to the SPI device.  The enabled_host flag is set and cleared
-	 * by sending USB_SPI_REQ_ENABLE and USB_SPI_REQ_DISABLE to the device
-	 * control endpoint.  The enabled_device flag is set by calling
-	 * usb_spi_enable.
-	 */
-	int enabled_host;
-	int enabled_device;
-
-	/*
-	 * The current enabled state.  This is only updated in the deferred
-	 * callback.  Whenever either of the host or device specific enable
-	 * flags is changed the deferred callback is queued, and it will check
-	 * their combined state against this flag.  If the combined state is
-	 * different, then one of usb_spi_board_enable or usb_spi_board_disable
-	 * is called and this flag is updated.  This ensures that the board
-	 * specific state update routines are only called from the deferred
-	 * callback.
-	 */
-	int enabled;
-
-	/* Mark the current operating mode. */
-	enum usb_spi_mode mode;
-
-	/*
-	 * Stores the status code response for the transfer, delivered in the
-	 * header for the first response packet. Error code is cleared during
-	 * first RX packet and set if a failure occurs.
-	 */
-	uint16_t status_code;
-
-	/* Stores the content from the USB packets */
-	struct usb_spi_packet_ctx receive_packet;
-	struct usb_spi_packet_ctx transmit_packet;
-
-	/*
-	 * Context structures representing the progress receiving the SPI
-	 * write data and transmitting the SPI read data.
-	 */
-	struct usb_spi_transfer_ctx spi_write_ctx;
-	struct usb_spi_transfer_ctx spi_read_ctx;
-};
-
-/*
- * Compile time Per-USB gpio configuration stored in flash.  Instances of this
- * structure are provided by the user of the USB gpio.  This structure binds
- * together all information required to operate a USB gpio.
- */
-struct usb_spi_config {
-	/* In RAM state of the USB SPI bridge. */
-	struct usb_spi_state *state;
-
-	/* Interface and endpoint indices. */
-	int interface;
-	int endpoint;
-
-	/* Deferred function to call to handle SPI request. */
-	const struct deferred_data *deferred;
-
-	/* Pointers to USB endpoint buffers. */
-	usb_uint *ep_rx_ram;
-	usb_uint *ep_tx_ram;
-
-	/* Flags. See USB_SPI_CONFIG_FLAGS_* for definitions */
-	uint32_t flags;
-};
+#ifdef CONFIG_USB_SPI_BUFFER_SIZE
+#define USB_SPI_BUFFER_SIZE CONFIG_USB_SPI_BUFFER_SIZE
+#else
+#define USB_SPI_BUFFER_SIZE \
+	(USB_SPI_PAYLOAD_SIZE_V2_START + (4 * USB_SPI_PAYLOAD_SIZE_V2_CONTINUE))
+#endif
+#define USB_SPI_MAX_WRITE_COUNT USB_SPI_BUFFER_SIZE
+#define USB_SPI_MAX_READ_COUNT USB_SPI_BUFFER_SIZE
+
+/* Protocol uses two-byte length fields.  Larger buffer makes no sense. */
+BUILD_ASSERT(USB_SPI_BUFFER_SIZE <= 65536);
 
 /*
- * Use when you want the SPI subsystem to be enabled even when the USB SPI
- * endpoint is not enabled by the host. This means that when this firmware
- * enables SPI, then the HW SPI module is enabled (i.e. SPE bit is set) until
- * this firmware disables the SPI module; it ignores the host's enables state.
- */
-#define USB_SPI_CONFIG_FLAGS_IGNORE_HOST_SIDE_ENABLE BIT(0)
-
-/*
- * Convenience macro for defining a USB SPI bridge driver.
- *
- * NAME is used to construct the names of the trampoline functions and the
- * usb_spi_config struct, the latter is just called NAME.
- *
- * INTERFACE is the index of the USB interface to associate with this
- * SPI driver.
- *
- * ENDPOINT is the index of the USB bulk endpoint used for receiving and
- * transmitting bytes.
+ * Set the enable state for the USB-SPI bridge.
  *
- * FLAGS encodes different run-time control parameters. See
- * USB_SPI_CONFIG_FLAGS_* for definitions.
+ * The bridge must be enabled from both the host and device side
+ * before the SPI bus is usable.  This allows the bridge to be
+ * available for host tools to use without forcing the device to
+ * disconnect or disable whatever else might be using the SPI bus.
  */
-#define USB_SPI_CONFIG(NAME,						\
-		       INTERFACE,					\
-		       ENDPOINT,					\
-		       FLAGS)						\
-	static uint16_t CONCAT2(NAME, _buffer_)[(USB_SPI_BUFFER_SIZE + 1) / 2];\
-	static usb_uint CONCAT2(NAME, _ep_rx_buffer_)[USB_MAX_PACKET_SIZE / 2] __usb_ram; \
-	static usb_uint CONCAT2(NAME, _ep_tx_buffer_)[USB_MAX_PACKET_SIZE / 2] __usb_ram; \
-	static void CONCAT2(NAME, _deferred_)(void);			\
-	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_));			\
-	struct usb_spi_state CONCAT2(NAME, _state_) = {			\
-		.enabled_host   = 0,					\
-		.enabled_device = 0,					\
-		.enabled        = 0,					\
-		.spi_write_ctx.buffer = (uint8_t *)CONCAT2(NAME, _buffer_), \
-		.spi_read_ctx.buffer = (uint8_t *)CONCAT2(NAME, _buffer_), \
-	};								\
-	struct usb_spi_config const NAME = {				\
-		.state     = &CONCAT2(NAME, _state_),			\
-		.interface = INTERFACE,					\
-		.endpoint  = ENDPOINT,					\
-		.deferred  = &CONCAT2(NAME, _deferred__data),		\
-		.ep_rx_ram = CONCAT2(NAME, _ep_rx_buffer_),		\
-		.ep_tx_ram = CONCAT2(NAME, _ep_tx_buffer_),		\
-		.flags     = FLAGS,		\
-	};								\
-	const struct usb_interface_descriptor				\
-	USB_IFACE_DESC(INTERFACE) = {					\
-		.bLength            = USB_DT_INTERFACE_SIZE,		\
-		.bDescriptorType    = USB_DT_INTERFACE,			\
-		.bInterfaceNumber   = INTERFACE,			\
-		.bAlternateSetting  = 0,				\
-		.bNumEndpoints      = 2,				\
-		.bInterfaceClass    = USB_CLASS_VENDOR_SPEC,		\
-		.bInterfaceSubClass = USB_SUBCLASS_GOOGLE_SPI,		\
-		.bInterfaceProtocol = USB_PROTOCOL_GOOGLE_SPI,		\
-		.iInterface         = 0,				\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 0) = {					\
-		.bLength          = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = 0x80 | ENDPOINT,			\
-		.bmAttributes     = 0x02 /* Bulk IN */,			\
-		.wMaxPacketSize   = USB_MAX_PACKET_SIZE,		\
-		.bInterval        = 10,					\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 1) = {					\
-		.bLength          = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = ENDPOINT,				\
-		.bmAttributes     = 0x02 /* Bulk OUT */,		\
-		.wMaxPacketSize   = USB_MAX_PACKET_SIZE,		\
-		.bInterval        = 0,					\
-	};								\
-	static void CONCAT2(NAME, _ep_tx_)   (void) { usb_spi_tx   (&NAME); } \
-	static void CONCAT2(NAME, _ep_rx_)   (void) { usb_spi_rx   (&NAME); } \
-	static void CONCAT2(NAME, _ep_event_)(enum usb_ep_event evt)	\
-	{								\
-		usb_spi_event(&NAME, evt);				\
-	}								\
-	USB_DECLARE_EP(ENDPOINT,					\
-		       CONCAT2(NAME, _ep_tx_),				\
-		       CONCAT2(NAME, _ep_rx_),				\
-		       CONCAT2(NAME, _ep_event_));			\
-	static int CONCAT2(NAME, _interface_)(usb_uint *rx_buf,		\
-					      usb_uint *tx_buf)		\
-	{ return usb_spi_interface(&NAME, rx_buf, tx_buf); }		\
-	USB_DECLARE_IFACE(INTERFACE,					\
-			  CONCAT2(NAME, _interface_));			\
-	static void CONCAT2(NAME, _deferred_)(void)			\
-	{ usb_spi_deferred(&NAME); }
+void usb_spi_enable(int enabled);
 
 /*
- * Handle SPI request in a deferred callback.
+ * These functions should be implemented by the board to provide any board
+ * specific operations required to enable or disable access to the SPI device.
  */
-void usb_spi_deferred(struct usb_spi_config const *config);
+void usb_spi_board_enable(void);
+void usb_spi_board_disable(void);
 
 /*
- * Set the enable state for the USB-SPI bridge.
- *
- * The bridge must be enabled from both the host and device side
- * before the SPI bus is usable.  This allows the bridge to be
- * available for host tools to use without forcing the device to
- * disconnect or disable whatever else might be using the SPI bus.
+ * In order to facilitate special SPI busses not covered by standard EC
+ * drivers, setting the USB_SPI_CUSTOM_SPI_DEVICE_MASK bit of spi_device->port
+ * will cause the USB to SPI forwarding logic to invoke this method rather
+ * than the standard spi_transaction_async().
  */
-void usb_spi_enable(struct usb_spi_config const *config, int enabled);
+int usb_spi_board_transaction(const struct spi_device_t *spi_device,
+			      uint32_t flash_flags, const uint8_t *txdata,
+			      int txlen, uint8_t *rxdata, int rxlen);
 
 /*
- * These functions are used by the trampoline functions defined above to
- * connect USB endpoint events with the generic USB GPIO driver.
+ * Flags to use in usb_spi_board_transaction_async() for advanced serial flash
+ * communication, when supported.
  */
-void usb_spi_tx(struct usb_spi_config const *config);
-void usb_spi_rx(struct usb_spi_config const *config);
-void usb_spi_event(struct usb_spi_config const *config, enum usb_ep_event evt);
-int  usb_spi_interface(struct usb_spi_config const *config,
-		       usb_uint *rx_buf,
-		       usb_uint *tx_buf);
+
+/* Number of bytes of opcode (0-3). */
+#define FLASH_FLAG_OPCODE_LEN_POS 0
+#define FLASH_FLAG_OPCODE_LEN_MSK (0x3U << FLASH_FLAG_OPCODE_LEN_POS)
+
+/* Number of bytes of address plus additional data bytes (0-7). */
+#define FLASH_FLAG_ADDR_LEN_POS 2
+#define FLASH_FLAG_ADDR_LEN_MSK (0x7U << FLASH_FLAG_ADDR_LEN_POS)
+
+/* At what stage to switch to multi-lane mode (if any). */
+#define FLASH_FLAG_MODE_POS 5
+#define FLASH_FLAG_MODE_MSK (0x3U << FLASH_FLAG_MODE_POS)
+#define FLASH_FLAG_MODE_111 (0x0U << FLASH_FLAG_MODE_POS)
+#define FLASH_FLAG_MODE_11N (0x1U << FLASH_FLAG_MODE_POS)
+#define FLASH_FLAG_MODE_1NN (0x2U << FLASH_FLAG_MODE_POS)
+#define FLASH_FLAG_MODE_NNN (0x3U << FLASH_FLAG_MODE_POS)
+
+/* Data width during the later stages (value of N, above). */
+#define FLASH_FLAG_WIDTH_POS 7
+#define FLASH_FLAG_WIDTH_MSK (0x3U << FLASH_FLAG_WIDTH_POS)
+#define FLASH_FLAG_WIDTH_1WIRE (0x0U << FLASH_FLAG_WIDTH_POS)
+#define FLASH_FLAG_WIDTH_2WIRE (0x1U << FLASH_FLAG_WIDTH_POS)
+#define FLASH_FLAG_WIDTH_4WIRE (0x2U << FLASH_FLAG_WIDTH_POS)
+#define FLASH_FLAG_WIDTH_8WIRE (0x3U << FLASH_FLAG_WIDTH_POS)
+
+/* Transmit opcode bits at both clock edges in later stages. */
+#define FLASH_FLAG_DTR_POS 9
+#define FLASH_FLAG_DTR (0x1U << FLASH_FLAG_DTR_POS)
+
+/* Number of dummy clock cycles (0-31). */
+#define FLASH_FLAG_DUMMY_CYCLES_POS 10
+#define FLASH_FLAG_DUMMY_CYCLES_MSK (0x1FU << FLASH_FLAG_DUMMY_CYCLES_POS)
 
 /*
- * These functions should be implemented by the board to provide any board
- * specific operations required to enable or disable access to the SPI device.
+ * Mask of the flags that cannot be ignored.  This is basically any flags
+ * which call for wires to switch direction, or data being clocked on both
+ * rising and falling edges.  As long as none of these are present, then the
+ * remaining flags specifying the length of opcode/address can be ignored, as
+ * the entire data buffer can be transmitted as a sequence of bytes, without
+ * the controller knowing which parts are to be interpreted as
+ * opcode/address/data.
  */
-void usb_spi_board_enable(struct usb_spi_config const *config);
-void usb_spi_board_disable(struct usb_spi_config const *config);
+#define FLASH_FLAGS_REQUIRING_SUPPORT \
+	(FLASH_FLAG_MODE_MSK | FLASH_FLAG_DTR | FLASH_FLAG_DUMMY_CYCLES_MSK)
 
 #endif /* __CROS_EC_USB_SPI_H */
diff --git a/chip/stm32/watchdog.c b/chip/stm32/watchdog.c
index 067ea32aa6..1a54d6f52d 100644
--- a/chip/stm32/watchdog.c
+++ b/chip/stm32/watchdog.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,12 +21,22 @@
  * value large enough that we reload before the worst-case watchdog delay
  * (fastest LSI clock).
  */
+#ifdef CHIP_FAMILY_STM32L4
+#define LSI_CLOCK 34000
+#else
 #define LSI_CLOCK 56000
+#endif
+
+/* The timeout value is multiplied by 1000 to be converted into ms */
+#define HAL_IWDG_DEFAULT_TIMEOUT ((6UL * 256UL * 1000UL) / LSI_CLOCK)
 
 /*
  * Use largest prescaler divider = /256.  This gives a worst-case watchdog
  * clock of 56000/256 = 218 Hz, and a maximum timeout period of (4095/218 Hz) =
  * 18.7 sec.
+ *
+ * For STM32L4, Max LSI is 34000. Watchdog clock is 34000 / 256 = 132Hz,
+ * Max timeout = 4095 / 132 = 31 sec.
  */
 #define IWDG_PRESCALER 6
 #define IWDG_PRESCALER_DIV (4 << IWDG_PRESCALER)
@@ -44,6 +54,12 @@ DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT);
 
 int watchdog_init(void)
 {
+#ifdef CHIP_FAMILY_STM32L4
+	timestamp_t tickstart, ticknow;
+
+	/* Enable watchdog registers */
+	STM32_IWDG_KR = STM32_IWDG_KR_START;
+#endif
 	/* Unlock watchdog registers */
 	STM32_IWDG_KR = STM32_IWDG_KR_UNLOCK;
 
@@ -51,12 +67,50 @@ int watchdog_init(void)
 	STM32_IWDG_PR = IWDG_PRESCALER & 7;
 
 	/* Set the reload value of the watchdog counter */
-	STM32_IWDG_RLR = MIN(STM32_IWDG_RLR_MAX, CONFIG_WATCHDOG_PERIOD_MS *
-			     (LSI_CLOCK / IWDG_PRESCALER_DIV) / 1000);
+	STM32_IWDG_RLR = MIN(STM32_IWDG_RLR_MAX,
+			     CONFIG_WATCHDOG_PERIOD_MS *
+				     (LSI_CLOCK / IWDG_PRESCALER_DIV) / 1000);
+#ifdef CHIP_FAMILY_STM32L4
+	tickstart = get_time();
+	/* Wait for SR */
+	while (STM32_IWDG_SR != 0x00u) {
+		ticknow = get_time();
+		if ((ticknow.val - tickstart.val) >
+		    HAL_IWDG_DEFAULT_TIMEOUT * 1000) {
+			return EC_ERROR_TIMEOUT;
+		}
+	}
 
+	/* Reload the watchdog */
+	STM32_IWDG_KR = STM32_IWDG_KR_RELOAD;
+#else
 	/* Start the watchdog (and re-lock registers) */
 	STM32_IWDG_KR = STM32_IWDG_KR_START;
 
+	/*
+	 * We should really wait for IWDG_PR and IWDG_RLR value to be updated
+	 * but updating those registers can take about 48ms (found
+	 * empirically, it's 6 LSI cycles at 32kHz). Such a big delay is not
+	 * desired during system init.
+	 *
+	 * However documentation allows us to continue code execution, but
+	 * we should wait for RVU bit to be clear before updating IWDG_RLR
+	 * once again (hard reboot for STM32H7 and STM32F4).
+	 *
+	 * RM0433 Rev 7
+	 * Section 45.4.4 Page 1920
+	 * https://www.st.com/resource/en/reference_manual/dm00314099.pdf
+	 * If several reload, prescaler, or window values are used by the
+	 * application, it is mandatory to wait until RVU bit is reset before
+	 * changing the reload value, to wait until PVU bit is reset before
+	 * changing the prescaler value, and to wait until WVU bit is reset
+	 * before changing the window value. However, after updating the
+	 * prescaler and/or the reload/window value it is not necessary to wait
+	 * until RVU or PVU or WVU is reset before continuing code execution
+	 * except in case of low-power mode entry.
+	 */
+
+#endif
 #ifdef CONFIG_WATCHDOG_HELP
 	/* Use a harder timer to warn about an impending watchdog reset */
 	hwtimer_setup_watchdog();
diff --git a/cmake/toolchain-armv7m.cmake b/cmake/toolchain-armv7m.cmake
new file mode 100644
index 0000000000..d05e6c3a1c
--- /dev/null
+++ b/cmake/toolchain-armv7m.cmake
@@ -0,0 +1,21 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+set(CMAKE_SYSTEM_NAME Generic)
+set(CMAKE_SYSTEM_PROCESSOR arm)
+
+set(CROSS_COMPILE armv7m-cros-eabi-)
+set(CMAKE_SYSROOT /usr/armv7m-cros-eabi/)
+
+set(CC_NAME clang)
+set(CXX_NAME clang++)
+
+set(CMAKE_TRY_COMPILE_PLATFORM_VARIABLES CROSS_COMPILE CC_NAME CXX_NAME)
+include("${CMAKE_CURRENT_LIST_DIR}/toolchain-common.cmake")
+
+add_compile_options(-mcpu=cortex-m4)
+add_compile_options(-mfloat-abi=hard)
+
+add_link_options(-lclang_rt.builtins-armv7m)
+add_link_options(-lnosys)
diff --git a/cmake/toolchain-common.cmake b/cmake/toolchain-common.cmake
new file mode 100644
index 0000000000..765487267f
--- /dev/null
+++ b/cmake/toolchain-common.cmake
@@ -0,0 +1,53 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Input variables:
+#   CROSS_COMPILE: the prefix of the cross compiler.
+#   CC_NAME: the name of the C compiler.
+#   CXX_NAME: the name of the C++ compiler.
+
+set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY)
+
+set(CMAKE_C_COMPILER   "${CROSS_COMPILE}${CC_NAME}")
+set(CMAKE_CXX_COMPILER "${CROSS_COMPILE}${CXX_NAME}")
+set(CMAKE_OBJCOPY      "${CROSS_COMPILE}objcopy")
+set(CMAKE_OBJDUMP      "${CROSS_COMPILE}objdump")
+set(CMAKE_READELF      "${CROSS_COMPILE}readelf")
+
+if ("${CC_NAME}" STREQUAL "gcc")
+set(CMAKE_LINKER       "${CROSS_COMPILE}ld")
+else()
+set(CMAKE_LINKER       "${CROSS_COMPILE}ld.lld")
+endif()
+
+# This is only for host unittests build.
+if ("${CC_NAME}" STREQUAL gcc AND "${CMAKE_SYSROOT}" STREQUAL "")
+set(CMAKE_AR           "${CROSS_COMPILE}gcc-ar")
+set(CMAKE_NM           "${CROSS_COMPILE}gcc-nm")
+set(CMAKE_RANLIB       "${CROSS_COMPILE}gcc-ranlib")
+else()
+set(CMAKE_AR           "${CROSS_COMPILE}ar")
+set(CMAKE_NM           "${CROSS_COMPILE}nm")
+set(CMAKE_RANLIB       "${CROSS_COMPILE}ranlib")
+endif()
+
+if ("${CC_NAME}" STREQUAL gcc)
+add_compile_options(-Os)
+else()
+add_compile_options(-Oz)
+endif()
+
+# Enable Link Time Optimization.
+add_compile_options(-flto)
+add_link_options(-flto)
+
+# See https://www.chromium.org/chromium-os/build/c-exception-support
+set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -fno-exceptions -fno-unwind-tables -fno-asynchronous-unwind-tables")
+
+set(CMAKE_POSITION_INDEPENDENT_CODE OFF)
+
+set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER)
+set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY)
+set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY)
+set(CMAKE_FIND_ROOT_PATH_MODE_PACKAGE ONLY)
diff --git a/common/CMakeLists.txt b/common/CMakeLists.txt
new file mode 100644
index 0000000000..2b9baa0e69
--- /dev/null
+++ b/common/CMakeLists.txt
@@ -0,0 +1,5 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+add_subdirectory(spi)
diff --git a/common/Kconfig b/common/Kconfig
new file mode 100644
index 0000000000..545b51ab20
--- /dev/null
+++ b/common/Kconfig
@@ -0,0 +1,5 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+rsource "spi/Kconfig"
diff --git a/common/accel_cal.c b/common/accel_cal.c
index 533a14fbc4..878f3b06fa 100644
--- a/common/accel_cal.c
+++ b/common/accel_cal.c
@@ -1,11 +1,11 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "accel_cal.h"
 #include "common.h"
 #include "console.h"
-#include "accel_cal.h"
 
 #define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ##args)
 
@@ -23,17 +23,17 @@ void accel_cal_reset(struct accel_cal *cal)
 
 static inline int compute_temp_gate(const struct accel_cal *cal, fp_t temp)
 {
-	int gate = (int) fp_div(fp_mul(temp - CONFIG_ACCEL_CAL_MIN_TEMP,
-				       INT_TO_FP(cal->num_temp_windows)),
-				TEMP_RANGE);
+	int gate = (int)fp_div(fp_mul(temp - CONFIG_ACCEL_CAL_MIN_TEMP,
+				      INT_TO_FP(cal->num_temp_windows)),
+			       TEMP_RANGE);
 
-	return gate < cal->num_temp_windows
-		? gate : (cal->num_temp_windows - 1);
+	return gate < cal->num_temp_windows ? gate :
+					      (cal->num_temp_windows - 1);
 }
 
-test_mockable bool accel_cal_accumulate(
-	struct accel_cal *cal, uint32_t timestamp, fp_t x, fp_t y, fp_t z,
-	fp_t temp)
+test_mockable bool accel_cal_accumulate(struct accel_cal *cal,
+					uint32_t timestamp, fp_t x, fp_t y,
+					fp_t z, fp_t temp)
 {
 	struct accel_cal_algo *algo;
 
diff --git a/common/acpi.c b/common/acpi.c
index 92117f09b1..5dd71d244e 100644
--- a/common/acpi.c
+++ b/common/acpi.c
@@ -1,42 +1,46 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "acpi.h"
 #include "battery.h"
+#include "body_detection.h"
 #include "common.h"
 #include "console.h"
 #include "dptf.h"
+#include "ec_commands.h"
+#include "fan.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "host_command.h"
 #include "keyboard_backlight.h"
 #include "lpc.h"
-#include "ec_commands.h"
-#include "tablet_mode.h"
+#include "printf.h"
 #include "pwm.h"
+#include "tablet_mode.h"
 #include "timer.h"
 #include "usb_charge.h"
+#include "usb_common.h"
 #include "util.h"
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTF(format, args...) cprintf(CC_LPC, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_LPC, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args)
 
 /* Last received ACPI command */
-static uint8_t __bss_slow acpi_cmd;
+static uint8_t acpi_cmd;
 /* First byte of data after ACPI command */
-static uint8_t __bss_slow acpi_addr;
+static uint8_t acpi_addr;
 /* Number of data writes after command */
-static int __bss_slow acpi_data_count;
+static int acpi_data_count;
 /* Test byte in ACPI memory space */
-static uint8_t __bss_slow acpi_mem_test;
+static uint8_t acpi_mem_test;
 
 #ifdef CONFIG_DPTF
-static int __bss_slow dptf_temp_sensor_id;	/* last sensor ID written */
-static int __bss_slow dptf_temp_threshold;	/* last threshold written */
+static int dptf_temp_sensor_id; /* last sensor ID written */
+static int dptf_temp_threshold; /* last threshold written */
 
 /*
  * Current DPTF profile number.
@@ -60,9 +64,9 @@ static int current_dptf_profile = DPTF_PROFILE_DEFAULT;
 #define ACPI_READ_CACHE_FLUSHED (EC_ACPI_MEM_MAPPED_BEGIN - 1)
 
 /* Calculate size of valid cache based upon end of memmap data. */
-#define ACPI_VALID_CACHE_SIZE(addr) (MIN( \
-	EC_ACPI_MEM_MAPPED_SIZE + EC_ACPI_MEM_MAPPED_BEGIN - (addr), \
-	ACPI_READ_CACHE_SIZE))
+#define ACPI_VALID_CACHE_SIZE(addr)                                       \
+	(MIN(EC_ACPI_MEM_MAPPED_SIZE + EC_ACPI_MEM_MAPPED_BEGIN - (addr), \
+	     ACPI_READ_CACHE_SIZE))
 
 /*
  * In burst mode, read the requested memmap data and the data immediately
@@ -131,23 +135,22 @@ static int acpi_read(uint8_t addr)
 	uint8_t *memmap_addr = (uint8_t *)(lpc_get_memmap_range() + addr -
 					   EC_ACPI_MEM_MAPPED_BEGIN);
 
+	DISABLE_CLANG_WARNING("-Wtautological-constant-out-of-range-compare");
 	/* Check for out-of-range read. */
 	if (addr < EC_ACPI_MEM_MAPPED_BEGIN ||
 	    addr >= EC_ACPI_MEM_MAPPED_BEGIN + EC_ACPI_MEM_MAPPED_SIZE) {
-		CPRINTS("ACPI read 0x%02x (ignored)",
-			acpi_addr);
+		CPRINTS("ACPI read 0x%02x (ignored)", acpi_addr);
 		return 0xff;
 	}
+	ENABLE_CLANG_WARNING("-Wtautological-constant-out-of-range-compare");
 
 	/* Read from cache if enabled (burst mode). */
 	if (acpi_read_cache.enabled) {
 		/* Fetch to cache on miss. */
 		if (acpi_read_cache.start_addr == ACPI_READ_CACHE_FLUSHED ||
 		    acpi_read_cache.start_addr > addr ||
-		    addr - acpi_read_cache.start_addr >=
-		    ACPI_READ_CACHE_SIZE) {
-			memcpy(acpi_read_cache.data,
-			       memmap_addr,
+		    addr - acpi_read_cache.start_addr >= ACPI_READ_CACHE_SIZE) {
+			memcpy(acpi_read_cache.data, memmap_addr,
 			       ACPI_VALID_CACHE_SIZE(addr));
 			acpi_read_cache.start_addr = addr;
 		}
@@ -167,7 +170,7 @@ int acpi_ap_to_ec(int is_cmd, uint8_t value, uint8_t *resultptr)
 {
 	int data = 0;
 	int retval = 0;
-	int result = 0xff;			/* value for bogus read */
+	int result = 0xff; /* value for bogus read */
 
 	/* Read command/data; this clears the FRMH status bit. */
 	if (is_cmd) {
@@ -231,7 +234,12 @@ int acpi_ap_to_ec(int is_cmd, uint8_t value, uint8_t *resultptr)
 #ifdef CONFIG_DPTF
 			result |= (acpi_dptf_get_profile_num() &
 				   EC_ACPI_MEM_DDPN_MASK)
-				<< EC_ACPI_MEM_DDPN_SHIFT;
+				  << EC_ACPI_MEM_DDPN_SHIFT;
+#endif
+
+#ifdef CONFIG_BODY_DETECTION_NOTIFY_MODE_CHANGE
+			if (body_detect_get_state() == BODY_DETECTION_ON_BODY)
+				result |= BIT(EC_ACPI_MEM_STTB_SHIFT);
 #endif
 			break;
 
@@ -250,7 +258,7 @@ int acpi_ap_to_ec(int is_cmd, uint8_t value, uint8_t *resultptr)
 
 			result = val >> (8 * off);
 			break;
-			}
+		}
 		case EC_ACPI_MEM_DEVICE_FEATURES4:
 		case EC_ACPI_MEM_DEVICE_FEATURES5:
 		case EC_ACPI_MEM_DEVICE_FEATURES6:
@@ -260,7 +268,7 @@ int acpi_ap_to_ec(int is_cmd, uint8_t value, uint8_t *resultptr)
 
 			result = val >> (8 * off);
 			break;
-			}
+		}
 
 #ifdef CONFIG_USB_PORT_POWER_DUMB
 		case EC_ACPI_MEM_USB_PORT_POWER: {
@@ -274,13 +282,18 @@ int acpi_ap_to_ec(int is_cmd, uint8_t value, uint8_t *resultptr)
 			 */
 			result = 0;
 			for (i = 0; i < port_count; ++i) {
-				if (gpio_get_level(usb_port_enable[i]) != 0)
+				if ((usb_port_enable[i] >= 0) &&
+				    (gpio_get_level(usb_port_enable[i]) != 0))
 					result |= 1 << i;
 			}
 			break;
-			}
+		}
+#endif
+#ifdef CONFIG_USBC_RETIMER_FW_UPDATE
+		case EC_ACPI_MEM_USB_RETIMER_FW_UPDATE:
+			result = usb_retimer_fw_update_get_result();
+			break;
 #endif
-
 		default:
 			result = acpi_read(acpi_addr);
 			break;
@@ -303,17 +316,19 @@ int acpi_ap_to_ec(int is_cmd, uint8_t value, uint8_t *resultptr)
 			break;
 #endif
 #ifdef CONFIG_KEYBOARD_BACKLIGHT
-		case EC_ACPI_MEM_KEYBOARD_BACKLIGHT:
+		case EC_ACPI_MEM_KEYBOARD_BACKLIGHT: {
+			char ts_str[PRINTF_TIMESTAMP_BUF_SIZE];
 			/*
 			 * Debug output with CR not newline, because the host
 			 * does a lot of keyboard backlights and it scrolls the
 			 * debug console.
 			 */
-			CPRINTF("\r[%pT ACPI kblight %d]",
-				PRINTF_TIMESTAMP_NOW, data);
+			snprintf_timestamp_now(ts_str, sizeof(ts_str));
+			CPRINTF("\r[%s ACPI kblight %d]", ts_str, data);
 			kblight_set(data);
 			kblight_enable(data > 0);
 			break;
+		}
 #endif
 #ifdef CONFIG_FANS
 		case EC_ACPI_MEM_FAN_DUTY:
@@ -327,13 +342,12 @@ int acpi_ap_to_ec(int is_cmd, uint8_t value, uint8_t *resultptr)
 		case EC_ACPI_MEM_TEMP_THRESHOLD:
 			dptf_temp_threshold = data + EC_TEMP_SENSOR_OFFSET;
 			break;
-		case EC_ACPI_MEM_TEMP_COMMIT:
-		{
+		case EC_ACPI_MEM_TEMP_COMMIT: {
 			int idx = data & EC_ACPI_MEM_TEMP_COMMIT_SELECT_MASK;
 			int enable = data & EC_ACPI_MEM_TEMP_COMMIT_ENABLE_MASK;
 			dptf_set_temp_threshold(dptf_temp_sensor_id,
-						dptf_temp_threshold,
-						idx, enable);
+						dptf_temp_threshold, idx,
+						enable);
 			break;
 		}
 #endif
@@ -365,8 +379,9 @@ int acpi_ap_to_ec(int is_cmd, uint8_t value, uint8_t *resultptr)
 				if (mode_field & 1)
 					mode = USB_CHARGE_MODE_ENABLED;
 
-				if (usb_charge_set_mode(i, mode,
-				    USB_ALLOW_SUSPEND_CHARGE)) {
+				if (usb_charge_set_mode(
+					    i, mode,
+					    USB_ALLOW_SUSPEND_CHARGE)) {
 					CPRINTS("ERROR: could not set charge "
 						"mode of USB port p%d to %d",
 						i, mode);
@@ -374,9 +389,15 @@ int acpi_ap_to_ec(int is_cmd, uint8_t value, uint8_t *resultptr)
 				mode_field >>= 1;
 			}
 			break;
-			}
+		}
+#endif
+#ifdef CONFIG_USBC_RETIMER_FW_UPDATE
+		case EC_ACPI_MEM_USB_RETIMER_FW_UPDATE:
+			usb_retimer_fw_update_process_op(
+				EC_ACPI_MEM_USB_RETIMER_PORT(data),
+				EC_ACPI_MEM_USB_RETIMER_OP(data));
+			break;
 #endif
-
 		default:
 			CPRINTS("ACPI write 0x%02x = 0x%02x (ignored)",
 				acpi_addr, data);
@@ -406,7 +427,8 @@ int acpi_ap_to_ec(int is_cmd, uint8_t value, uint8_t *resultptr)
 		 * Disable from deferred function in case burst mode is enabled
 		 * for an extremely long time  (ex. kernel bug / crash).
 		 */
-		hook_call_deferred(&acpi_disable_burst_deferred_data, 1*SECOND);
+		hook_call_deferred(&acpi_disable_burst_deferred_data,
+				   1 * SECOND);
 
 		/* ACPI 5.0-12.3.3: Burst ACK */
 		*resultptr = 0x90;
diff --git a/common/adc.c b/common/adc.c
index 5407de6cfe..4c2519c046 100644
--- a/common/adc.c
+++ b/common/adc.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,6 @@
 /* ADC module for Chrome EC */
 
 #include "adc.h"
-#include "adc_chip.h"
 #include "common.h"
 #include "console.h"
 #include "ec_commands.h"
@@ -15,21 +14,6 @@
 
 /* 'adc' console command is not supported in continuous mode */
 #ifndef CONFIG_ADC_PROFILE_FAST_CONTINUOUS
-static enum adc_channel find_adc_channel_by_name(const char *name)
-{
-	const struct adc_t *ch = adc_channels;
-	int i;
-
-	if (!name || !*name)
-		return ADC_CH_COUNT;
-
-	for (i = 0; i < ADC_CH_COUNT; i++, ch++) {
-		if (!strcasecmp(name, ch->name))
-			return i;
-	}
-
-	return ADC_CH_COUNT;
-}
 
 static int print_one_adc(int channel)
 {
@@ -38,18 +22,20 @@ static int print_one_adc(int channel)
 	v = adc_read_channel(channel);
 	if (v == ADC_READ_ERROR)
 		return EC_ERROR_UNKNOWN;
-	ccprintf("  %s = %d\n", adc_channels[channel].name, v);
+	ccprintf("[%d] %s = %d mV\n", channel, adc_channels[channel].name, v);
 	return EC_SUCCESS;
 }
 
-static int command_adc(int argc, char **argv)
+static int command_adc(int argc, const char **argv)
 {
 	int i, ret;
 
 	/* If a channel is specified, read only that one */
 	if (argc == 2) {
-		i = find_adc_channel_by_name(argv[1]);
-		if (i == ADC_CH_COUNT)
+		char *end;
+
+		i = strtoi(argv[1], &end, 0);
+		if (*end || i < 0 || i >= ADC_CH_COUNT)
 			return EC_ERROR_PARAM1;
 		return print_one_adc(i);
 	} else {
@@ -62,9 +48,7 @@ static int command_adc(int argc, char **argv)
 		return EC_SUCCESS;
 	}
 }
-DECLARE_CONSOLE_COMMAND(adc, command_adc,
-			"[name]",
-			"Print ADC channel(s)");
+DECLARE_CONSOLE_COMMAND(adc, command_adc, "[id]", NULL);
 
 static enum ec_status hc_adc_read(struct host_cmd_handler_args *args)
 {
diff --git a/common/aes-gcm.c b/common/aes-gcm.c
deleted file mode 120000
index 3176d85ff8..0000000000
--- a/common/aes-gcm.c
+++ /dev/null
@@ -1 +0,0 @@
-../third_party/boringssl/common/aes-gcm.c
\ No newline at end of file
diff --git a/common/aes.c b/common/aes.c
deleted file mode 120000
index ed10836943..0000000000
--- a/common/aes.c
+++ /dev/null
@@ -1 +0,0 @@
-../third_party/boringssl/common/aes.c
\ No newline at end of file
diff --git a/common/als.c b/common/als.c
index 2e9c7ba96c..ea86250fef 100644
--- a/common/als.c
+++ b/common/als.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,10 +18,13 @@
 #include "timer.h"
 #include "util.h"
 
-#define CPUTS(outstr) cputs(CC_ALS, outstr)
-#define CPRINTS(format, args...) cprints(CC_ALS, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_ALS, format, ## args)
+#ifdef CONFIG_ZEPHYR
+#include "cros_als.h"
+#endif
 
+#define CPUTS(outstr) cputs(CC_ALS, outstr)
+#define CPRINTS(format, args...) cprints(CC_ALS, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_ALS, format, ##args)
 
 #define ALS_POLL_PERIOD SECOND
 
@@ -90,8 +93,7 @@ static void als_task_init(void)
 	 * Enable ALS task in S0 only and may need to re-enable
 	 * when sysjumped.
 	 */
-	if (system_jumped_late() &&
-		chipset_in_state(CHIPSET_STATE_ON))
+	if (system_jumped_late() && chipset_in_state(CHIPSET_STATE_ON))
 		als_task_enable();
 }
 
@@ -103,7 +105,7 @@ DECLARE_HOOK(HOOK_INIT, als_task_init, HOOK_PRIO_ALS_INIT);
 /* Console commands */
 
 #ifdef CONFIG_CMD_ALS
-static int command_als(int argc, char **argv)
+static int command_als(int argc, const char **argv)
 {
 	int i, rv, val;
 
@@ -121,7 +123,5 @@ static int command_als(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(als, command_als,
-			NULL,
-			"Print ALS values");
+DECLARE_CONSOLE_COMMAND(als, command_als, NULL, "Print ALS values");
 #endif
diff --git a/common/ap_hang_detect.c b/common/ap_hang_detect.c
index 0c9e7a186d..6e3d7177a7 100644
--- a/common/ap_hang_detect.c
+++ b/common/ap_hang_detect.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,12 +18,12 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 static struct ec_params_hang_detect hdparams;
 
-static int active;  /* Is hang detect timer active / counting? */
-static int timeout_will_reboot;  /* Will the deferred call reboot the AP? */
+static int active; /* Is hang detect timer active / counting? */
+static int timeout_will_reboot; /* Will the deferred call reboot the AP? */
 
 /**
  * Handle the hang detect timer expiring.
@@ -56,7 +56,8 @@ static void hang_detect_deferred(void)
 		timeout_will_reboot = 1;
 		hook_call_deferred(&hang_detect_deferred_data,
 				   (hdparams.warm_reboot_timeout_msec -
-				    hdparams.host_event_timeout_msec) * MSEC);
+				    hdparams.host_event_timeout_msec) *
+					   MSEC);
 	} else {
 		/* Not rebooting, so go back to idle */
 		active = 0;
@@ -196,19 +197,18 @@ hang_detect_host_command(struct host_cmd_handler_args *args)
 	 */
 	if (hdparams.warm_reboot_timeout_msec &&
 	    hdparams.warm_reboot_timeout_msec <=
-	    hdparams.host_event_timeout_msec)
+		    hdparams.host_event_timeout_msec)
 		hdparams.host_event_timeout_msec = 0;
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_HANG_DETECT,
-		     hang_detect_host_command,
+DECLARE_HOST_COMMAND(EC_CMD_HANG_DETECT, hang_detect_host_command,
 		     EC_VER_MASK(0));
 
 /*****************************************************************************/
 /* Console command */
 
-static int command_hang_detect(int argc, char **argv)
+static int command_hang_detect(int argc, const char **argv)
 {
 	ccprintf("flags:  0x%x\n", hdparams.flags);
 
@@ -233,6 +233,5 @@ static int command_hang_detect(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(hangdet, command_hang_detect,
-			NULL,
+DECLARE_CONSOLE_COMMAND(hangdet, command_hang_detect, NULL,
 			"Print hang detect state");
diff --git a/common/asm_define.h b/common/asm_define.h
new file mode 100644
index 0000000000..b47bae067f
--- /dev/null
+++ b/common/asm_define.h
@@ -0,0 +1,25 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_COMMON_ASM_DEFINE_H
+#define __CROS_EC_COMMON_ASM_DEFINE_H
+
+#include "stddef.h"
+
+/*
+ * Use an immediate integer constraint
+ * (https://gcc.gnu.org/onlinedocs/gcc/Simple-Constraints.html) to write the
+ * value. This file is compiled with the "-S" flag, which stops the compiler
+ * after generating assembly. The resulting assembly is then grepped for the
+ * "__ASM_DEFINE__" strings, which is used to create a header file with the
+ * value.
+ */
+#define ASM_DEFINE(NAME, VAL) \
+	__asm__ volatile(".ascii \" __ASM_DEFINE__ " NAME " %0\"" : : "i"(VAL))
+
+#define ASM_DEFINE_OFFSET(NAME, TYPE, MEMBER) \
+	ASM_DEFINE(NAME, offsetof(TYPE, MEMBER))
+
+#endif /* __CROS_EC_COMMON_ASM_DEFINE_H */
diff --git a/common/audio_codec.c b/common/audio_codec.c
index 3f7203ad15..aba1453ce3 100644
--- a/common/audio_codec.c
+++ b/common/audio_codec.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,15 +9,14 @@
 #include "host_command.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ##args)
 
-static const uint32_t capabilities =
-	0
+static const uint32_t capabilities = 0
 #ifdef CONFIG_AUDIO_CODEC_CAP_WOV_AUDIO_SHM
-	| BIT(EC_CODEC_CAP_WOV_AUDIO_SHM)
+				     | BIT(EC_CODEC_CAP_WOV_AUDIO_SHM)
 #endif
 #ifdef CONFIG_AUDIO_CODEC_CAP_WOV_LANG_SHM
-	| BIT(EC_CODEC_CAP_WOV_LANG_SHM)
+				     | BIT(EC_CODEC_CAP_WOV_LANG_SHM)
 #endif
 	;
 
@@ -122,8 +121,8 @@ int audio_codec_capable(uint8_t cap)
 	return capabilities & BIT(cap);
 }
 
-int audio_codec_register_shm(uint8_t shm_id, uint8_t cap,
-		uintptr_t *addr, uint32_t len, uint8_t type)
+int audio_codec_register_shm(uint8_t shm_id, uint8_t cap, uintptr_t *addr,
+			     uint32_t len, uint8_t type)
 {
 	if (shm_id >= EC_CODEC_SHM_ID_LAST)
 		return EC_ERROR_INVAL;
@@ -140,8 +139,8 @@ int audio_codec_register_shm(uint8_t shm_id, uint8_t cap,
 	return EC_SUCCESS;
 }
 
-__attribute__((weak))
-int audio_codec_memmap_ap_to_ec(uintptr_t ap_addr, uintptr_t *ec_addr)
+__attribute__((weak)) int audio_codec_memmap_ap_to_ec(uintptr_t ap_addr,
+						      uintptr_t *ec_addr)
 {
 	return EC_ERROR_UNIMPLEMENTED;
 }
diff --git a/common/audio_codec_dmic.c b/common/audio_codec_dmic.c
index c4f0b07a46..d85245791d 100644
--- a/common/audio_codec_dmic.c
+++ b/common/audio_codec_dmic.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,7 +8,7 @@
 #include "console.h"
 #include "host_command.h"
 
-#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ##args)
 
 static enum ec_status dmic_get_max_gain(struct host_cmd_handler_args *args)
 {
@@ -25,9 +25,9 @@ static enum ec_status dmic_set_gain_idx(struct host_cmd_handler_args *args)
 {
 	const struct ec_param_ec_codec_dmic *p = args->params;
 
-	if (audio_codec_dmic_set_gain_idx(
-			p->set_gain_idx_param.channel,
-			p->set_gain_idx_param.gain) != EC_SUCCESS)
+	if (audio_codec_dmic_set_gain_idx(p->set_gain_idx_param.channel,
+					  p->set_gain_idx_param.gain) !=
+	    EC_SUCCESS)
 		return EC_RES_ERROR;
 
 	return EC_RES_SUCCESS;
@@ -38,8 +38,8 @@ static enum ec_status dmic_get_gain_idx(struct host_cmd_handler_args *args)
 	const struct ec_param_ec_codec_dmic *p = args->params;
 	struct ec_response_ec_codec_dmic_get_gain_idx *r = args->response;
 
-	if (audio_codec_dmic_get_gain_idx(
-			p->get_gain_idx_param.channel, &r->gain) != EC_SUCCESS)
+	if (audio_codec_dmic_get_gain_idx(p->get_gain_idx_param.channel,
+					  &r->gain) != EC_SUCCESS)
 		return EC_RES_ERROR;
 
 	args->response_size = sizeof(*r);
diff --git a/common/audio_codec_i2s_rx.c b/common/audio_codec_i2s_rx.c
index aeae19bdca..ac6aa8ecce 100644
--- a/common/audio_codec_i2s_rx.c
+++ b/common/audio_codec_i2s_rx.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,7 +8,7 @@
 #include "console.h"
 #include "host_command.h"
 
-#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ##args)
 
 static uint8_t i2s_rx_enabled;
 
@@ -128,5 +128,5 @@ static enum ec_status i2s_rx_host_command(struct host_cmd_handler_args *args)
 
 	return EC_RES_INVALID_PARAM;
 }
-DECLARE_HOST_COMMAND(EC_CMD_EC_CODEC_I2S_RX,
-	i2s_rx_host_command, EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_EC_CODEC_I2S_RX, i2s_rx_host_command,
+		     EC_VER_MASK(0));
diff --git a/common/audio_codec_wov.c b/common/audio_codec_wov.c
index f84e45f342..7c7b43acae 100644
--- a/common/audio_codec_wov.c
+++ b/common/audio_codec_wov.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,7 +13,7 @@
 #include "task.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ##args)
 
 /*
  * To shorten the variable names, or the following code is likely to greater
@@ -99,7 +99,7 @@ static enum ec_status wov_set_lang_shm(struct host_cmd_handler_args *args)
 {
 	const struct ec_param_ec_codec_wov *p = args->params;
 	const struct ec_param_ec_codec_wov_set_lang_shm *pp =
-			&p->set_lang_shm_param;
+		&p->set_lang_shm_param;
 
 	if (pp->total_len > LANG_BUF_LEN)
 		return EC_RES_INVALID_PARAM;
@@ -135,11 +135,11 @@ static enum ec_status wov_set_lang(struct host_cmd_handler_args *args)
 		return EC_RES_BUSY;
 
 	if (!pp->offset)
-		memset((uint8_t *)audio_codec_wov_lang_buf_addr,
-		       0, LANG_BUF_LEN);
+		memset((uint8_t *)audio_codec_wov_lang_buf_addr, 0,
+		       LANG_BUF_LEN);
 
-	memcpy((uint8_t *)audio_codec_wov_lang_buf_addr + pp->offset,
-		pp->buf, pp->len);
+	memcpy((uint8_t *)audio_codec_wov_lang_buf_addr + pp->offset, pp->buf,
+	       pp->len);
 
 	if (pp->offset + pp->len == pp->total_len) {
 		if (check_lang_buf((uint8_t *)audio_codec_wov_lang_buf_addr,
@@ -176,7 +176,7 @@ static enum ec_status wov_enable(struct host_cmd_handler_args *args)
 
 	if (!speech_lib_loaded) {
 		if (!GoogleHotwordDspInit(
-				(void *)audio_codec_wov_lang_buf_addr))
+			    (void *)audio_codec_wov_lang_buf_addr))
 			return EC_RES_ERROR;
 		speech_lib_loaded = 1;
 	} else {
@@ -359,7 +359,6 @@ void audio_codec_wov_task(void *arg)
 			continue;
 		}
 
-
 		/* Clear the buffer if full. */
 		if (is_buf_full()) {
 			audio_buf_wp = audio_buf_rp;
@@ -415,7 +414,7 @@ void audio_codec_wov_task(void *arg)
 		 * case, sample is S16_LE.  Thus, n / 2.
 		 */
 		if (!hotword_detected &&
-				GoogleHotwordDspProcess(p, n / 2, &r)) {
+		    GoogleHotwordDspProcess(p, n / 2, &r)) {
 			CPRINTS("hotword detected");
 
 			mutex_lock(&lock);
diff --git a/common/backlight_lid.c b/common/backlight_lid.c
index 3b857df592..f8fd8d637f 100644
--- a/common/backlight_lid.c
+++ b/common/backlight_lid.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,7 +11,6 @@
 #include "host_command.h"
 #include "lid_switch.h"
 
-
 /**
  * Activate/Deactivate the backlight GPIO pin considering active high or low.
  */
@@ -32,7 +31,7 @@ static void update_backlight(void)
 #ifdef CONFIG_BACKLIGHT_REQ_GPIO
 	/* Enable the backlight if lid is open AND requested by AP */
 	enable_backlight(lid_is_open() &&
-		gpio_get_level(CONFIG_BACKLIGHT_REQ_GPIO));
+			 gpio_get_level(CONFIG_BACKLIGHT_REQ_GPIO));
 #else
 	/*
 	 * Enable backlight if lid is open; this is AND'd with the request from
@@ -79,7 +78,4 @@ switch_command_enable_backlight(struct host_cmd_handler_args *args)
 	return EC_RES_SUCCESS;
 }
 DECLARE_HOST_COMMAND(EC_CMD_SWITCH_ENABLE_BKLIGHT,
-		     switch_command_enable_backlight,
-		     EC_VER_MASK(0));
-
-
+		     switch_command_enable_backlight, EC_VER_MASK(0));
diff --git a/common/base32.c b/common/base32.c
index 8a33d7685c..e5c30c4d6f 100644
--- a/common/base32.c
+++ b/common/base32.c
@@ -1,23 +1,21 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Base-32 encoding/decoding */
 
-#include "common.h"
 #include "base32.h"
+#include "common.h"
 #include "util.h"
 
-static const unsigned char crc5_table1[] = {
-	0x00, 0x0E, 0x1C, 0x12, 0x11, 0x1F, 0x0D, 0x03,
-	0x0B, 0x05, 0x17, 0x19, 0x1A, 0x14, 0x06, 0x08
-};
+static const unsigned char crc5_table1[] = { 0x00, 0x0E, 0x1C, 0x12, 0x11, 0x1F,
+					     0x0D, 0x03, 0x0B, 0x05, 0x17, 0x19,
+					     0x1A, 0x14, 0x06, 0x08 };
 
-static const unsigned char crc5_table0[] = {
-	0x00, 0x16, 0x05, 0x13, 0x0A, 0x1C, 0x0F, 0x19,
-	0x14, 0x02, 0x11, 0x07, 0x1E, 0x08, 0x1B, 0x0D
-};
+static const unsigned char crc5_table0[] = { 0x00, 0x16, 0x05, 0x13, 0x0A, 0x1C,
+					     0x0F, 0x19, 0x14, 0x02, 0x11, 0x07,
+					     0x1E, 0x08, 0x1B, 0x0D };
 
 uint8_t crc5_sym(uint8_t sym, uint8_t previous_crc)
 {
@@ -46,9 +44,8 @@ static int decode_sym(int sym)
 	return -1;
 }
 
-int base32_encode(char *dest, int destlen_chars,
-		  const void *srcbits, int srclen_bits,
-		  int add_crc_every)
+int base32_encode(char *dest, int destlen_chars, const void *srcbits,
+		  int srclen_bits, int add_crc_every)
 {
 	const uint8_t *src = srcbits;
 	int destlen_needed;
@@ -59,14 +56,14 @@ int base32_encode(char *dest, int destlen_chars,
 	*dest = 0;
 
 	/* Make sure destination is big enough */
-	destlen_needed = (srclen_bits + 4) / 5;  /* Symbols before adding CRC */
+	destlen_needed = (srclen_bits + 4) / 5; /* Symbols before adding CRC */
 	if (add_crc_every) {
 		/* Must be an exact number of groups to add CRC */
 		if (destlen_needed % add_crc_every)
 			return EC_ERROR_INVAL;
 		destlen_needed += destlen_needed / add_crc_every;
 	}
-	destlen_needed++;  /* For terminating null */
+	destlen_needed++; /* For terminating null */
 	if (destlen_chars < destlen_needed)
 		return EC_ERROR_INVAL;
 
@@ -119,12 +116,12 @@ int base32_decode(uint8_t *dest, int destlen_bits, const char *src,
 	for (; *src; src++) {
 		int sym, sbits, dbits, b;
 
-		if (isspace(*src) || *src == '-')
+		if (isspace((unsigned char)*src) || *src == '-')
 			continue;
 
 		sym = decode_sym(*src);
 		if (sym < 0)
-			return -1;  /* Bad input symbol */
+			return -1; /* Bad input symbol */
 
 		/* Check CRC if needed */
 		if (crc_after_every) {
@@ -155,7 +152,7 @@ int base32_decode(uint8_t *dest, int destlen_bits, const char *src,
 		dbits = 8 - (out_bits & 7);
 		b = MIN(dbits, sbits);
 		if (dbits == 8)
-			dest[out_bits / 8] = 0;  /* Starting a new byte */
+			dest[out_bits / 8] = 0; /* Starting a new byte */
 		dest[out_bits / 8] |= (sym << (dbits - b)) >> (sbits - b);
 		out_bits += b;
 		sbits -= b;
diff --git a/common/base_state.c b/common/base_state.c
index 053b6d4b23..7bbd14eb00 100644
--- a/common/base_state.c
+++ b/common/base_state.c
@@ -1,14 +1,14 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "base_state.h"
 #include "console.h"
-#include "host_command.h"
 #include "hooks.h"
+#include "host_command.h"
 
-#define CPRINTS(format, args...) cprints(CC_MOTION_LID, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_MOTION_LID, format, ##args)
 
 #ifdef CONFIG_BASE_ATTACHED_SWITCH
 /* 1: base attached, 0: otherwise */
@@ -33,22 +33,35 @@ void base_set_state(int state)
 }
 #endif
 
-static int command_setbasestate(int argc, char **argv)
+static int command_setbasestate(int argc, const char **argv)
 {
 	if (argc != 2)
 		return EC_ERROR_PARAM_COUNT;
 	if (argv[1][0] == 'a')
-		base_force_state(1);
+		base_force_state(EC_SET_BASE_STATE_ATTACH);
 	else if (argv[1][0] == 'd')
-		base_force_state(0);
+		base_force_state(EC_SET_BASE_STATE_DETACH);
 	else if (argv[1][0] == 'r')
-		base_force_state(2);
+		base_force_state(EC_SET_BASE_STATE_RESET);
 	else
 		return EC_ERROR_PARAM1;
 
 	return EC_SUCCESS;
-
 }
-DECLARE_CONSOLE_COMMAND(basestate, command_setbasestate,
-	"[attach | detach | reset]",
+DECLARE_CONSOLE_COMMAND(
+	basestate, command_setbasestate, "[attach | detach | reset]",
 	"Manually force base state to attached, detached or reset.");
+
+static enum ec_status hostcmd_setbasestate(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_set_base_state *params = args->params;
+
+	if (params->cmd > EC_SET_BASE_STATE_RESET)
+		return EC_RES_INVALID_PARAM;
+
+	base_force_state(params->cmd);
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_SET_BASE_STATE, hostcmd_setbasestate,
+		     EC_VER_MASK(0));
diff --git a/common/battery.c b/common/battery.c
index 9e03bb83a2..cd25a52b01 100644
--- a/common/battery.c
+++ b/common/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -6,36 +6,30 @@
  */
 
 #include "battery.h"
+#include "battery_fuel_gauge.h"
+#include "charge_manager.h"
 #include "charge_state.h"
 #include "common.h"
 #include "console.h"
-#include "ec_ec_comm_master.h"
+#include "ec_ec_comm_client.h"
 #include "extpower.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "host_command.h"
+#include "math_util.h"
 #include "timer.h"
+#include "usb_pd.h"
 #include "util.h"
 #include "watchdog.h"
 
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 #define CUTOFFPRINTS(info) CPRINTS("%s %s", "Battery cut off", info)
 
 /* See config.h for details */
-const static int batt_full_factor = CONFIG_BATT_FULL_FACTOR;
 const static int batt_host_full_factor = CONFIG_BATT_HOST_FULL_FACTOR;
 const static int batt_host_shutdown_pct = CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE;
 
-#ifdef CONFIG_BATTERY_V2
-/*
- * Store battery information in these 2 structures. Main (lid) battery is always
- * at index 0, and secondary (base) battery at index 1.
- */
-struct ec_response_battery_static_info battery_static[CONFIG_BATTERY_COUNT];
-struct ec_response_battery_dynamic_info battery_dynamic[CONFIG_BATTERY_COUNT];
-#endif
-
 #ifdef CONFIG_BATTERY_CUT_OFF
 
 #ifndef CONFIG_BATTERY_CUTOFF_DELAY_US
@@ -72,7 +66,7 @@ static const char *get_error_text(int rv)
 
 static void print_item_name(const char *name)
 {
-	ccprintf("  %-11s", name);
+	ccprintf("  %-14s", name);
 }
 
 static int check_print_error(int rv)
@@ -84,9 +78,14 @@ static int check_print_error(int rv)
 
 static void print_battery_status(void)
 {
-	static const char * const st[] = {"EMPTY", "FULL", "DCHG", "INIT",};
-	static const char * const al[] = {"RT", "RC", "--", "TD",
-					  "OT", "--", "TC", "OC"};
+	static const char *const st[] = {
+		"EMPTY",
+		"FULL",
+		"DCHG",
+		"INIT",
+	};
+	static const char *const al[] = { "RT", "RC", "--", "TD",
+					  "OT", "--", "TC", "OC" };
 
 	int value, i;
 
@@ -99,12 +98,12 @@ static void print_battery_status(void)
 
 		/* bits 4-7 are status */
 		for (i = 0; i < 4; i++)
-			if (value & (1 << (i+4)))
+			if (value & (1 << (i + 4)))
 				ccprintf(" %s", st[i]);
 
 		/* bits 15-8 are alarms */
 		for (i = 0; i < 8; i++)
-			if (value & (1 << (i+8)))
+			if (value & (1 << (i + 8)))
 				ccprintf(" %s", al[i]);
 
 		ccprintf("\n");
@@ -145,10 +144,8 @@ static void print_battery_params(void)
 	ccprintf("%08x\n", batt->flags);
 
 	print_item_name("Temp:");
-	ccprintf("0x%04x = %.1d K (%.1d C)\n",
-		 batt->temperature,
-		 batt->temperature,
-		 batt->temperature - 2731);
+	ccprintf("0x%04x = %.1d K (%.1d C)\n", batt->temperature,
+		 batt->temperature, batt->temperature - 2731);
 
 	print_item_name("V:");
 	ccprintf("0x%04x = %d mV\n", batt->voltage, batt->voltage);
@@ -174,7 +171,15 @@ static void print_battery_params(void)
 		 batt->flags & BATT_FLAG_WANT_CHARGE ? "" : "Not ");
 
 	print_item_name("Charge:");
-		ccprintf("%d %%\n", batt->state_of_charge);
+	ccprintf("%d %%\n", batt->state_of_charge);
+
+	if (IS_ENABLED(CONFIG_CHARGER)) {
+		int value;
+
+		print_item_name("  Display:");
+		value = charge_get_display_charge();
+		ccprintf("%d.%d %%\n", value / 10, value % 10);
+	}
 }
 
 static void print_battery_info(void)
@@ -204,26 +209,23 @@ static void print_battery_info(void)
 
 	print_item_name("Cap-full:");
 	if (check_print_error(battery_full_charge_capacity(&value)))
-		ccprintf("%d mAh (%d mAh with %d %% compensation)\n",
-			 value, value*batt_full_factor/100, batt_full_factor);
-
-#ifdef CONFIG_CHARGER
-	print_item_name("Display:");
-	value = charge_get_display_charge();
-	ccprintf("%d.%d %%\n", value / 10, value % 10);
-#endif
+		ccprintf("%d mAh\n", value);
 
 	print_item_name("  Design:");
 	if (check_print_error(battery_design_capacity(&value)))
 		ccprintf("%d mAh\n", value);
 
+	print_item_name("Charge Cycle:");
+	if (check_print_error(battery_cycle_count(&value)))
+		ccprintf("%d\n", value);
+
 	print_item_name("Time-full:");
 	if (check_print_error(battery_time_to_full(&value))) {
 		if (value == 65535) {
-			hour   = 0;
+			hour = 0;
 			minute = 0;
 		} else {
-			hour   = value / 60;
+			hour = value / 60;
 			minute = value % 60;
 		}
 		ccprintf("%dh:%d\n", hour, minute);
@@ -232,14 +234,29 @@ static void print_battery_info(void)
 	print_item_name("  Empty:");
 	if (check_print_error(battery_time_to_empty(&value))) {
 		if (value == 65535) {
-			hour   = 0;
+			hour = 0;
 			minute = 0;
 		} else {
-			hour   = value / 60;
+			hour = value / 60;
 			minute = value % 60;
 		}
 		ccprintf("%dh:%d\n", hour, minute);
 	}
+
+	print_item_name("Full Factor:");
+	ccprintf("0.%d\n", batt_host_full_factor);
+
+	print_item_name("Shutdown SoC:");
+	ccprintf("%d %%\n", batt_host_shutdown_pct);
+
+#ifdef CONFIG_BATTERY_FUEL_GAUGE
+	value = battery_is_charge_fet_disabled();
+	/* reverse the flag if no error */
+	if (value != -1)
+		value = !value;
+	print_item_name("C-FET:");
+	ccprintf("%d\n", value);
+#endif
 }
 
 void print_battery_debug(void)
@@ -250,7 +267,7 @@ void print_battery_debug(void)
 	print_battery_info();
 }
 
-static int command_battery(int argc, char **argv)
+static int command_battery(int argc, const char **argv)
 {
 	int repeat = 1;
 	int loop;
@@ -289,20 +306,33 @@ static int command_battery(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(battery, command_battery,
-			"<repeat_count> <sleep_ms>",
+DECLARE_CONSOLE_COMMAND(battery, command_battery, "<repeat_count> <sleep_ms>",
 			"Print battery info");
 
 #ifdef CONFIG_BATTERY_CUT_OFF
+
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+void set_battery_in_cut_off(void)
+{
+	battery_cutoff_state = BATTERY_CUTOFF_STATE_CUT_OFF;
+}
+#endif
+
 int battery_is_cut_off(void)
 {
 	return (battery_cutoff_state == BATTERY_CUTOFF_STATE_CUT_OFF);
 }
 
+int battery_cutoff_in_progress(void)
+{
+	return (battery_cutoff_state == BATTERY_CUTOFF_STATE_IN_PROGRESS);
+}
+
 static void pending_cutoff_deferred(void)
 {
 	int rv;
 
+	battery_cutoff_state = BATTERY_CUTOFF_STATE_IN_PROGRESS;
 	rv = board_cut_off_battery();
 
 	if (rv == EC_RES_SUCCESS) {
@@ -338,6 +368,7 @@ static enum ec_status battery_command_cutoff(struct host_cmd_handler_args *args)
 		}
 	}
 
+	battery_cutoff_state = BATTERY_CUTOFF_STATE_IN_PROGRESS;
 	rv = board_cut_off_battery();
 	if (rv == EC_RES_SUCCESS) {
 		CUTOFFPRINTS("is successful.");
@@ -349,7 +380,7 @@ static enum ec_status battery_command_cutoff(struct host_cmd_handler_args *args)
 	return rv;
 }
 DECLARE_HOST_COMMAND(EC_CMD_BATTERY_CUT_OFF, battery_command_cutoff,
-		EC_VER_MASK(0) | EC_VER_MASK(1));
+		     EC_VER_MASK(0) | EC_VER_MASK(1));
 
 static void check_pending_cutoff(void)
 {
@@ -362,7 +393,7 @@ static void check_pending_cutoff(void)
 }
 DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, check_pending_cutoff, HOOK_PRIO_LAST);
 
-static int command_cutoff(int argc, char **argv)
+static int command_cutoff(int argc, const char **argv)
 {
 	int rv;
 
@@ -375,6 +406,7 @@ static int command_cutoff(int argc, char **argv)
 		}
 	}
 
+	battery_cutoff_state = BATTERY_CUTOFF_STATE_IN_PROGRESS;
 	rv = board_cut_off_battery();
 	if (rv == EC_RES_SUCCESS) {
 		ccprints("Battery cut off");
@@ -384,18 +416,49 @@ static int command_cutoff(int argc, char **argv)
 
 	return EC_ERROR_UNKNOWN;
 }
-DECLARE_CONSOLE_COMMAND(cutoff, command_cutoff,
-		"[at-shutdown]",
-		"Cut off the battery output");
+DECLARE_CONSOLE_COMMAND(cutoff, command_cutoff, "[at-shutdown]",
+			"Cut off the battery output");
 #else
 int battery_is_cut_off(void)
 {
-	return 0;  /* Always return NOT cut off */
+	return 0; /* Always return NOT cut off */
 }
-#endif  /* CONFIG_BATTERY_CUT_OFF */
+#endif /* CONFIG_BATTERY_CUT_OFF */
 
 #ifdef CONFIG_BATTERY_VENDOR_PARAM
-static int console_command_battery_vendor_param(int argc, char **argv)
+__overridable int battery_get_vendor_param(uint32_t param, uint32_t *value)
+{
+	const struct battery_info *bi = battery_get_info();
+	struct battery_static_info *bs = &battery_static[BATT_IDX_MAIN];
+	uint8_t *data = bs->vendor_param;
+	int rv;
+
+	if (param < bi->vendor_param_start)
+		return EC_ERROR_ACCESS_DENIED;
+
+	/* Skip read if cache is valid. */
+	if (!data[0]) {
+		rv = sb_read_string(bi->vendor_param_start, data,
+				    sizeof(bs->vendor_param));
+		if (rv) {
+			data[0] = 0;
+			return rv;
+		}
+	}
+
+	if (param > bi->vendor_param_start + strlen(data))
+		return EC_ERROR_INVAL;
+
+	*value = data[param - bi->vendor_param_start];
+	return EC_SUCCESS;
+}
+
+__overridable int battery_set_vendor_param(uint32_t param, uint32_t value)
+{
+	return EC_ERROR_UNIMPLEMENTED;
+}
+
+static int console_command_battery_vendor_param(int argc, const char **argv)
 {
 	uint32_t param;
 	uint32_t value;
@@ -456,177 +519,201 @@ host_command_battery_vendor_param(struct host_cmd_handler_args *args)
 	return rv;
 }
 DECLARE_HOST_COMMAND(EC_CMD_BATTERY_VENDOR_PARAM,
-		     host_command_battery_vendor_param,
-		     EC_VER_MASK(0));
+		     host_command_battery_vendor_param, EC_VER_MASK(0));
 #endif /* CONFIG_BATTERY_VENDOR_PARAM */
 
-#ifdef CONFIG_BATTERY_V2
-#ifdef CONFIG_HOSTCMD_BATTERY_V2
-static void battery_update(enum battery_index i);
-static enum ec_status
-host_command_battery_get_static(struct host_cmd_handler_args *args)
+void battery_compensate_params(struct batt_params *batt)
 {
-	const struct ec_params_battery_static_info *p = args->params;
-	struct ec_response_battery_static_info *r = args->response;
+	int numer, denom;
+	int *remain = &(batt->remaining_capacity);
+	int full = batt->full_capacity;
 
-	if (p->index < 0 || p->index >= CONFIG_BATTERY_COUNT)
-		return EC_RES_INVALID_PARAM;
-	battery_update(p->index);
-	args->response_size = sizeof(*r);
-	memcpy(r, &battery_static[p->index], sizeof(*r));
+	if ((batt->flags & BATT_FLAG_BAD_FULL_CAPACITY) ||
+	    (batt->flags & BATT_FLAG_BAD_REMAINING_CAPACITY))
+		return;
 
-	return EC_RES_SUCCESS;
+	if (*remain <= 0 || full <= 0)
+		return;
+
+	/* Some batteries don't update full capacity as often. */
+	if (*remain > full)
+		*remain = full;
+
+	/*
+	 * EC calculates the display SoC like how Powerd used to do. Powerd
+	 * reads the display SoC from the EC. This design allows the system to
+	 * behave consistently on a single SoC value across all power states.
+	 *
+	 * Display SoC is computed as follows:
+	 *
+	 *   actual_soc = 100 * remain / full
+	 *
+	 *		   actual_soc - shutdown_pct
+	 *   display_soc = --------------------------- x 1000
+	 *		   full_factor - shutdown_pct
+	 *
+	 *		   (100 * remain / full) - shutdown_pct
+	 *		 = ------------------------------------ x 1000
+	 *		        full_factor - shutdown_pct
+	 *
+	 *		   100 x remain - full x shutdown_pct
+	 *		 = ----------------------------------- x 1000
+	 *		   full x (full_factor - shutdown_pct)
+	 */
+	numer = 1000 * ((100 * *remain) - (full * batt_host_shutdown_pct));
+	denom = full * (batt_host_full_factor - batt_host_shutdown_pct);
+	/* Rounding (instead of truncating) */
+	batt->display_charge = (numer + denom / 2) / denom;
+	if (batt->display_charge < 0)
+		batt->display_charge = 0;
+	if (batt->display_charge > 1000)
+		batt->display_charge = 1000;
 }
-DECLARE_HOST_COMMAND(EC_CMD_BATTERY_GET_STATIC,
-		     host_command_battery_get_static,
-		     EC_VER_MASK(0));
 
-static enum ec_status
-host_command_battery_get_dynamic(struct host_cmd_handler_args *args)
+#ifdef CONFIG_CHARGER
+static enum ec_status battery_display_soc(struct host_cmd_handler_args *args)
 {
-	const struct ec_params_battery_dynamic_info *p = args->params;
-	struct ec_response_battery_dynamic_info *r = args->response;
-
-	if (p->index < 0 || p->index >= CONFIG_BATTERY_COUNT)
-		return EC_RES_INVALID_PARAM;
+	struct ec_response_display_soc *r = args->response;
 
+	r->display_soc = charge_get_display_charge();
+	r->full_factor = batt_host_full_factor * 10;
+	r->shutdown_soc = batt_host_shutdown_pct * 10;
 	args->response_size = sizeof(*r);
-	memcpy(r, &battery_dynamic[p->index], sizeof(*r));
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_BATTERY_GET_DYNAMIC,
-		     host_command_battery_get_dynamic,
-		     EC_VER_MASK(0));
-#endif /* CONFIG_HOSTCMD_BATTERY_V2 */
+DECLARE_HOST_COMMAND(EC_CMD_DISPLAY_SOC, battery_display_soc, EC_VER_MASK(0));
+#endif
 
-#ifdef HAS_TASK_HOSTCMD
-static void battery_update(enum battery_index i)
+__overridable void board_battery_compensate_params(struct batt_params *batt)
 {
-	char *batt_str;
-	int *memmap_dcap = (int *)host_get_memmap(EC_MEMMAP_BATT_DCAP);
-	int *memmap_dvlt = (int *)host_get_memmap(EC_MEMMAP_BATT_DVLT);
-	int *memmap_ccnt = (int *)host_get_memmap(EC_MEMMAP_BATT_CCNT);
-	int *memmap_volt = (int *)host_get_memmap(EC_MEMMAP_BATT_VOLT);
-	int *memmap_rate = (int *)host_get_memmap(EC_MEMMAP_BATT_RATE);
-	int *memmap_cap = (int *)host_get_memmap(EC_MEMMAP_BATT_CAP);
-	int *memmap_lfcc = (int *)host_get_memmap(EC_MEMMAP_BATT_LFCC);
-	uint8_t *memmap_flags = host_get_memmap(EC_MEMMAP_BATT_FLAG);
-
-	/* Smart battery serial number is 16 bits */
-	batt_str = (char *)host_get_memmap(EC_MEMMAP_BATT_SERIAL);
-	memcpy(batt_str, battery_static[i].serial, EC_MEMMAP_TEXT_MAX);
-
-	/* Design Capacity of Full */
-	*memmap_dcap = battery_static[i].design_capacity;
-
-	/* Design Voltage */
-	*memmap_dvlt = battery_static[i].design_voltage;
-
-	/* Cycle Count */
-	*memmap_ccnt = battery_static[i].cycle_count;
-
-	/* Battery Manufacturer string */
-	batt_str = (char *)host_get_memmap(EC_MEMMAP_BATT_MFGR);
-	memcpy(batt_str, battery_static[i].manufacturer, EC_MEMMAP_TEXT_MAX);
+}
 
-	/* Battery Model string */
-	batt_str = (char *)host_get_memmap(EC_MEMMAP_BATT_MODEL);
-	memcpy(batt_str, battery_static[i].model, EC_MEMMAP_TEXT_MAX);
+__attribute__((weak)) int get_battery_manufacturer_name(char *dest, int size)
+{
+	strzcpy(dest, "<unkn>", size);
+	return EC_SUCCESS;
+}
 
-	/* Battery Type string */
-	batt_str = (char *)host_get_memmap(EC_MEMMAP_BATT_TYPE);
-	memcpy(batt_str, battery_static[i].type, EC_MEMMAP_TEXT_MAX);
+__overridable int battery_get_avg_voltage(void)
+{
+	return -EC_ERROR_UNIMPLEMENTED;
+}
 
-	*memmap_volt = battery_dynamic[i].actual_voltage;
-	*memmap_rate = battery_dynamic[i].actual_current;
-	*memmap_cap = battery_dynamic[i].remaining_capacity;
-	*memmap_lfcc = battery_dynamic[i].full_capacity;
-	*memmap_flags = battery_dynamic[i].flags;
+__overridable int battery_get_avg_current(void)
+{
+	return -EC_ERROR_UNIMPLEMENTED;
 }
 
-void battery_memmap_refresh(enum battery_index index)
+int battery_manufacturer_name(char *dest, int size)
 {
-	if (*host_get_memmap(EC_MEMMAP_BATT_INDEX) == index)
-		battery_update(index);
+	return get_battery_manufacturer_name(dest, size);
 }
 
-void battery_memmap_set_index(enum battery_index index)
+__overridable enum battery_disconnect_state battery_get_disconnect_state(void)
 {
-	if (*host_get_memmap(EC_MEMMAP_BATT_INDEX) == index)
-		return;
+	return BATTERY_NOT_DISCONNECTED;
+}
 
-	*host_get_memmap(EC_MEMMAP_BATT_INDEX) = BATT_IDX_INVALID;
-	if (index < 0 || index >= CONFIG_BATTERY_COUNT)
-		return;
+#ifdef CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV
 
-	battery_update(index);
-	*host_get_memmap(EC_MEMMAP_BATT_INDEX) = index;
-}
+#if CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV < 5000 || \
+	CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV >= PD_MAX_VOLTAGE_MV
+#error "Voltage limit must be between 5000 and PD_MAX_VOLTAGE_MV"
+#endif
+
+#if !((defined(CONFIG_USB_PD_TCPMV1) && defined(CONFIG_USB_PD_DUAL_ROLE)) || \
+      (defined(CONFIG_USB_PD_TCPMV2) && defined(CONFIG_USB_PE_SM)))
+#error "Voltage reducing requires TCPM with Policy Engine"
+#endif
 
-static void battery_init(void)
+/*
+ * Returns true if input voltage should be reduced (chipset is in S5/G3) and
+ * battery is full, otherwise returns false
+ */
+static bool board_wants_reduced_input_voltage(void)
 {
-	*host_get_memmap(EC_MEMMAP_BATT_INDEX) = BATT_IDX_INVALID;
-	*host_get_memmap(EC_MEMMAP_BATT_COUNT) = CONFIG_BATTERY_COUNT;
-	*host_get_memmap(EC_MEMMAP_BATTERY_VERSION) = 2;
+	struct batt_params batt;
+
+	/* Chipset not in S5/G3, so we don't want to reduce voltage */
+	if (!chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF))
+		return false;
+
+	battery_get_params(&batt);
 
-	battery_memmap_set_index(BATT_IDX_MAIN);
+	/* Battery needs charge, so we don't want to reduce voltage */
+	if (batt.flags & BATT_FLAG_WANT_CHARGE)
+		return false;
+
+	return true;
 }
-DECLARE_HOOK(HOOK_INIT, battery_init, HOOK_PRIO_DEFAULT);
-#endif /* HAS_TASK_HOSTCMD */
-#endif /* CONFIG_BATTERY_V2 */
 
-void battery_compensate_params(struct batt_params *batt)
+static void reduce_input_voltage_when_full(void)
 {
-	int numer, denom;
-	int *remain = &(batt->remaining_capacity);
-	int *full = &(batt->full_capacity);
+	static int saved_input_voltage = -1;
+	int max_pd_voltage_mv = pd_get_max_voltage();
+	int port;
 
-	if ((batt->flags & BATT_FLAG_BAD_FULL_CAPACITY) ||
-			(batt->flags & BATT_FLAG_BAD_REMAINING_CAPACITY))
-		return;
-
-	if (*remain <= 0 || *full <= 0)
+	port = charge_manager_get_active_charge_port();
+	if (port < 0 || port >= board_get_usb_pd_port_count())
 		return;
 
-	/* full_factor is effectively disabled in powerd. */
-	*full = *full * batt_full_factor / 100;
-	if (*remain > *full)
-		*remain = *full;
+	if (board_wants_reduced_input_voltage()) {
+		/*
+		 * Board wants voltage to be reduced. Apply limit if current
+		 * voltage is different. Save current voltage, it will be
+		 * restored when board wants to stop reducing input voltage.
+		 */
+		if (max_pd_voltage_mv !=
+		    CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV) {
+			saved_input_voltage = max_pd_voltage_mv;
+			max_pd_voltage_mv =
+				CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV;
+		}
+	} else if (saved_input_voltage != -1) {
+		/*
+		 * Board doesn't want to reduce input voltage. If current
+		 * voltage is reduced we will restore previously saved voltage.
+		 * If current voltage is different we will respect newer value.
+		 */
+		if (max_pd_voltage_mv ==
+		    CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV)
+			max_pd_voltage_mv = saved_input_voltage;
 
-	/*
-	 * Powerd uses the following equation to calculate display percentage:
-	 *   charge = 100 * remain / full
-	 *   display = 100 * (charge - shutdown_pct) /
-	 *		     (full_factor - shutdown_pct)
-	 *	     = 100 * ((100 * remain / full) - shutdown_pct) /
-	 *		     (full_factor - shutdown_pct)
-	 *	     = 100 * ((100 * remain) - (full * shutdown_pct)) /
-	 *		     (full * (full_factor - shutdown_pct))
-	 *
-	 * The unit of the following batt->display_charge is 0.1%.
-	 */
-	numer = 1000 * ((100 * *remain) - (*full * batt_host_shutdown_pct));
-	denom = *full * (batt_host_full_factor - batt_host_shutdown_pct);
-	/* Rounding (instead of truncating) */
-	batt->display_charge = (numer + denom / 2) / denom;
-	if (batt->display_charge < 0)
-		batt->display_charge = 0;
-	if (batt->display_charge > 1000)
-		batt->display_charge = 1000;
-}
+		saved_input_voltage = -1;
+	}
 
-__overridable void board_battery_compensate_params(struct batt_params *batt)
-{
+	if (pd_get_max_voltage() != max_pd_voltage_mv)
+		pd_set_external_voltage_limit(port, max_pd_voltage_mv);
 }
+DECLARE_HOOK(HOOK_AC_CHANGE, reduce_input_voltage_when_full, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, reduce_input_voltage_when_full,
+	     HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, reduce_input_voltage_when_full,
+	     HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, reduce_input_voltage_when_full,
+	     HOOK_PRIO_DEFAULT);
+#endif
 
-__attribute__((weak)) int get_battery_manufacturer_name(char *dest, int size)
+void battery_validate_params(struct batt_params *batt)
 {
-	strzcpy(dest, "<unkn>", size);
-	return EC_SUCCESS;
-}
+	/*
+	 * TODO(crosbug.com/p/27527). Sometimes the battery thinks its
+	 * temperature is 6280C, which seems a bit high. Let's ignore
+	 * anything above the boiling point of tungsten until this bug
+	 * is fixed. If the battery is really that warm, we probably
+	 * have more urgent problems.
+	 */
+	if (batt->temperature > CELSIUS_TO_DECI_KELVIN(5660)) {
+		CPRINTS("ignoring ridiculous batt.temp of %dC",
+			DECI_KELVIN_TO_CELSIUS(batt->temperature));
+		batt->flags |= BATT_FLAG_BAD_TEMPERATURE;
+	}
 
-int battery_manufacturer_name(char *dest, int size)
-{
-	return get_battery_manufacturer_name(dest, size);
+	/* If the battery thinks it's above 100%, don't believe it */
+	if (batt->state_of_charge > 100) {
+		CPRINTS("ignoring ridiculous batt.soc of %d%%",
+			batt->state_of_charge);
+		batt->flags |= BATT_FLAG_BAD_STATE_OF_CHARGE;
+	}
 }
diff --git a/common/battery_config.c b/common/battery_config.c
new file mode 100644
index 0000000000..3ff05b2e82
--- /dev/null
+++ b/common/battery_config.c
@@ -0,0 +1,302 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Module for reading battery config
+ *
+ * Default battery config (i.e. default_battery_conf) will be updated as a value
+ * is read from a source storage (e.g. CBI). If a read fails, the failed field
+ * will be ignored and search will continue. This allows a source storage to
+ * store only the differences between the default and the target battery config,
+ * which saves us the boot time and the storage space.
+ *
+ * If data in a storage is corrupted, this may result in mix of two pieces of
+ * battery config. Partially updating the config (or using as much as
+ * discovered) is most likely better (and safer) than entirely falling back to
+ * the default battery config especially when only one field is missing or
+ * corrupted.
+ */
+
+#include "battery_fuel_gauge.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "hooks.h"
+#include "util.h"
+
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, "BCFG " format, ##args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, "BCFG " format, ##args)
+
+static char manuf_name[32];
+static char device_name[32];
+
+test_export_static int batt_conf_read(enum cbi_data_tag tag, uint8_t *data,
+				      uint8_t size)
+{
+	int rv;
+
+	rv = cbi_get_board_info(tag, data, &size);
+	if (rv == EC_ERROR_UNKNOWN)
+		/* Tag not found. This is ok. Fall back to default. */
+		return EC_ERROR_UNKNOWN;
+
+	if (rv == EC_ERROR_INVAL) {
+		/* Data in CBI is larger than expected. */
+		CPRINTS("batt data tag=%d is larger (%d)", tag, size);
+		return EC_ERROR_INVAL;
+	}
+
+	/* It's ok size of the cbi data is smaller than expected, */
+	return EC_SUCCESS;
+}
+
+test_export_static int batt_conf_read_ship_mode(struct board_batt_params *info)
+{
+	struct ship_mode_info *ship = &info->fuel_gauge.ship_mode;
+	uint8_t d8;
+
+	batt_conf_read(CBI_TAG_BATT_SHIP_MODE_REG_ADDR, &ship->reg_addr,
+		       sizeof(ship->reg_addr));
+
+	batt_conf_read(CBI_TAG_BATT_SHIP_MODE_REG_DATA,
+		       (uint8_t *)&ship->reg_data, sizeof(ship->reg_data));
+
+	if (batt_conf_read(CBI_TAG_BATT_SHIP_MODE_FLAGS, &d8, sizeof(d8)) ==
+	    EC_SUCCESS)
+		ship->wb_support = d8 & BIT(0) ? 1 : 0;
+
+	return EC_SUCCESS;
+}
+
+test_export_static int batt_conf_read_sleep_mode(struct board_batt_params *info)
+{
+	struct sleep_mode_info *sleep = &info->fuel_gauge.sleep_mode;
+	uint8_t d8;
+
+	batt_conf_read(CBI_TAG_BATT_SLEEP_MODE_REG_ADDR, &sleep->reg_addr,
+		       sizeof(sleep->reg_addr));
+
+	batt_conf_read(CBI_TAG_BATT_SLEEP_MODE_REG_DATA,
+		       (uint8_t *)&sleep->reg_data, sizeof(sleep->reg_data));
+
+	if (batt_conf_read(CBI_TAG_BATT_SLEEP_MODE_FLAGS, &d8, sizeof(d8)) ==
+	    EC_SUCCESS)
+		sleep->sleep_supported = d8 & BIT(0) ? 1 : 0;
+
+	return EC_SUCCESS;
+}
+
+test_export_static int batt_conf_read_fet_info(struct board_batt_params *info)
+{
+	struct fet_info *fet = &info->fuel_gauge.fet;
+	uint8_t d8;
+
+	batt_conf_read(CBI_TAG_BATT_FET_REG_ADDR, &fet->reg_addr,
+		       sizeof(fet->reg_addr));
+	batt_conf_read(CBI_TAG_BATT_FET_REG_MASK, (uint8_t *)&fet->reg_mask,
+		       sizeof(fet->reg_mask));
+	batt_conf_read(CBI_TAG_BATT_FET_DISCONNECT_VAL,
+		       (uint8_t *)&fet->disconnect_val,
+		       sizeof(fet->disconnect_val));
+	batt_conf_read(CBI_TAG_BATT_FET_CFET_MASK, (uint8_t *)&fet->cfet_mask,
+		       sizeof(fet->cfet_mask));
+	batt_conf_read(CBI_TAG_BATT_FET_CFET_OFF_VAL,
+		       (uint8_t *)&fet->cfet_off_val,
+		       sizeof(fet->cfet_off_val));
+	if (batt_conf_read(CBI_TAG_BATT_FET_FLAGS, &d8, sizeof(d8)) ==
+	    EC_SUCCESS)
+		fet->mfgacc_support = d8 & BIT(0) ? 1 : 0;
+
+	return EC_SUCCESS;
+}
+
+test_export_static int
+batt_conf_read_fuel_gauge_info(struct board_batt_params *info)
+{
+	struct fuel_gauge_info *fg = &info->fuel_gauge;
+	uint8_t d8;
+
+	if (batt_conf_read(CBI_TAG_FUEL_GAUGE_MANUF_NAME, (uint8_t *)manuf_name,
+			   sizeof(manuf_name)) == EC_SUCCESS)
+		fg->manuf_name = manuf_name;
+
+	if (batt_conf_read(CBI_TAG_FUEL_GAUGE_DEVICE_NAME,
+			   (uint8_t *)device_name,
+			   sizeof(device_name)) == EC_SUCCESS)
+		fg->device_name = device_name;
+
+	if (batt_conf_read(CBI_TAG_FUEL_GAUGE_FLAGS, &d8, sizeof(d8)) ==
+	    EC_SUCCESS)
+		fg->override_nil = d8 & BIT(0) ? 1 : 0;
+
+	batt_conf_read_ship_mode(info);
+	batt_conf_read_sleep_mode(info);
+	batt_conf_read_fet_info(info);
+
+	return EC_SUCCESS;
+}
+
+test_export_static int
+batt_conf_read_battery_info(struct board_batt_params *info)
+{
+	const struct battery_info *batt = &info->batt_info;
+
+	batt_conf_read(CBI_TAG_BATT_VOLTAGE_MAX, (uint8_t *)&batt->voltage_max,
+		       sizeof(batt->voltage_max));
+	batt_conf_read(CBI_TAG_BATT_VOLTAGE_NORMAL,
+		       (uint8_t *)&batt->voltage_normal,
+		       sizeof(batt->voltage_normal));
+	batt_conf_read(CBI_TAG_BATT_VOLTAGE_MIN, (uint8_t *)&batt->voltage_min,
+		       sizeof(batt->voltage_min));
+	batt_conf_read(CBI_TAG_BATT_PRECHARGE_VOLTAGE,
+		       (uint8_t *)&batt->precharge_voltage,
+		       sizeof(batt->precharge_voltage));
+	batt_conf_read(CBI_TAG_BATT_PRECHARGE_CURRENT,
+		       (uint8_t *)&batt->precharge_current,
+		       sizeof(batt->precharge_current));
+	batt_conf_read(CBI_TAG_BATT_START_CHARGING_MIN_C,
+		       (uint8_t *)&batt->start_charging_min_c,
+		       sizeof(batt->start_charging_min_c));
+	batt_conf_read(CBI_TAG_BATT_START_CHARGING_MAX_C,
+		       (uint8_t *)&batt->start_charging_max_c,
+		       sizeof(batt->start_charging_max_c));
+	batt_conf_read(CBI_TAG_BATT_CHARGING_MIN_C,
+		       (uint8_t *)&batt->charging_min_c,
+		       sizeof(batt->charging_min_c));
+	batt_conf_read(CBI_TAG_BATT_CHARGING_MAX_C,
+		       (uint8_t *)&batt->charging_max_c,
+		       sizeof(batt->charging_max_c));
+	batt_conf_read(CBI_TAG_BATT_DISCHARGING_MIN_C,
+		       (uint8_t *)&batt->discharging_min_c,
+		       sizeof(batt->discharging_min_c));
+	batt_conf_read(CBI_TAG_BATT_DISCHARGING_MAX_C,
+		       (uint8_t *)&batt->discharging_max_c,
+		       sizeof(batt->discharging_max_c));
+
+	return EC_SUCCESS;
+}
+
+__overridable bool board_batt_conf_enabled(void)
+{
+	return true;
+}
+
+test_export_static void batt_conf_main(void)
+{
+	CPRINTS("%s", __func__);
+	if (board_batt_conf_enabled()) {
+		CPRINTS("Reading CBI");
+		batt_conf_read_fuel_gauge_info(&default_battery_conf);
+		batt_conf_read_battery_info(&default_battery_conf);
+	} else {
+		/* Battery config isn't in CBI. */
+		CPRINTS("Detect battery");
+		init_battery_type();
+	}
+	CPRINTS("%s done", __func__);
+}
+DECLARE_HOOK(HOOK_INIT, batt_conf_main, HOOK_PRIO_POST_I2C);
+
+#ifdef CONFIG_CMD_BATTERY_CONFIG
+static struct board_batt_params scratch_battery_conf;
+
+static void batt_conf_dump(const struct board_batt_params *info)
+{
+	const struct fuel_gauge_info *fg = &info->fuel_gauge;
+	const struct ship_mode_info *ship = &info->fuel_gauge.ship_mode;
+	const struct sleep_mode_info *sleep = &info->fuel_gauge.sleep_mode;
+	const struct fet_info *fet = &info->fuel_gauge.fet;
+	const struct battery_info *batt = &info->batt_info;
+
+	ccprintf("   .fuel_gauge = {\n");
+
+	ccprintf("%02x:\t.manuf_name = \"%s\",\n",
+		 CBI_TAG_FUEL_GAUGE_MANUF_NAME, fg->manuf_name);
+	ccprintf("%02x:\t.device_name= \"%s\",\n",
+		 CBI_TAG_FUEL_GAUGE_DEVICE_NAME, fg->device_name);
+	ccprintf("%02x:\t.override_nil = %d,\n", CBI_TAG_FUEL_GAUGE_FLAGS,
+		 fg->override_nil & BIT(0));
+
+	ccprintf("   \t.ship_mode = {\n");
+	ccprintf("%02x:\t\t.reg_addr = 0x%02x,\n",
+		 CBI_TAG_BATT_SHIP_MODE_REG_ADDR, ship->reg_addr);
+	ccprintf("%02x:\t\t.reg_data = { 0x%04x, 0x%04x },\n",
+		 CBI_TAG_BATT_SHIP_MODE_REG_DATA, ship->reg_data[0],
+		 ship->reg_data[1]);
+	ccprintf("%02x:\t\t.wb_support = %d,\n", CBI_TAG_BATT_SHIP_MODE_FLAGS,
+		 ship->wb_support & BIT(0));
+	ccprintf("   \t},\n");
+
+	ccprintf("   \t.sleep_mode = {\n");
+	ccprintf("%02x:\t\t.reg_addr = 0x%02x,\n",
+		 CBI_TAG_BATT_SLEEP_MODE_REG_ADDR, sleep->reg_addr);
+	ccprintf("%02x:\t\t.reg_data = 0x%04x,\n",
+		 CBI_TAG_BATT_SLEEP_MODE_REG_DATA, sleep->reg_data);
+	ccprintf("%02x:\t\t.sleep_supported = %d,\n",
+		 CBI_TAG_BATT_SLEEP_MODE_FLAGS,
+		 sleep->sleep_supported & BIT(0));
+	ccprintf("   \t},\n");
+
+	ccprintf("   \t.fet = {\n");
+	ccprintf("%02x:\t\t.reg_addr = 0x%02x,\n", CBI_TAG_BATT_FET_REG_ADDR,
+		 fet->reg_addr);
+	ccprintf("%02x:\t\t.reg_mask = 0x%04x,\n", CBI_TAG_BATT_FET_REG_MASK,
+		 fet->reg_mask);
+	ccprintf("%02x:\t\t.disconnect_val = 0x%x,\n",
+		 CBI_TAG_BATT_FET_DISCONNECT_VAL, fet->disconnect_val);
+	ccprintf("%02x:\t\t.cfet_mask = 0x%04x,\n", CBI_TAG_BATT_FET_CFET_MASK,
+		 fet->cfet_mask);
+	ccprintf("%02x:\t\t.cfet_off_val = 0x%04x,\n",
+		 CBI_TAG_BATT_FET_CFET_OFF_VAL, fet->cfet_off_val);
+	ccprintf("%02x:\t\t.mfgacc_support = %d,\n", CBI_TAG_BATT_FET_FLAGS,
+		 fet->mfgacc_support & BIT(0));
+	ccprintf("   \t},\n");
+
+	ccprintf("   },\n"); /* end of fuel_gauge */
+
+	ccprintf("   .batt_info = {\n");
+	ccprintf("%02x:\t.voltage_max = %d,\n", CBI_TAG_BATT_VOLTAGE_MAX,
+		 batt->voltage_max);
+	ccprintf("%02x:\t.voltage_normal = %d,\n", CBI_TAG_BATT_VOLTAGE_NORMAL,
+		 batt->voltage_normal);
+	ccprintf("%02x:\t.voltage_min = %d,\n", CBI_TAG_BATT_VOLTAGE_MIN,
+		 batt->voltage_min);
+	ccprintf("%02x:\t.precharge_voltage= %d,\n",
+		 CBI_TAG_BATT_PRECHARGE_VOLTAGE, batt->precharge_voltage);
+	ccprintf("%02x:\t.precharge_current = %d,\n",
+		 CBI_TAG_BATT_PRECHARGE_CURRENT, batt->precharge_current);
+	ccprintf("%02x:\t.start_charging_min_c = %d,\n",
+		 CBI_TAG_BATT_START_CHARGING_MIN_C, batt->start_charging_min_c);
+	ccprintf("%02x:\t.start_charging_max_c = %d,\n",
+		 CBI_TAG_BATT_START_CHARGING_MAX_C, batt->start_charging_max_c);
+	ccprintf("%02x:\t.charging_min_c = %d,\n", CBI_TAG_BATT_CHARGING_MIN_C,
+		 batt->charging_min_c);
+	ccprintf("%02x:\t.charging_max_c = %d,\n", CBI_TAG_BATT_CHARGING_MAX_C,
+		 batt->charging_max_c);
+	ccprintf("%02x:\t.discharging_min_c = %d,\n",
+		 CBI_TAG_BATT_DISCHARGING_MIN_C, batt->discharging_min_c);
+	ccprintf("%02x:\t.discharging_max_c = %d,\n",
+		 CBI_TAG_BATT_DISCHARGING_MAX_C, batt->discharging_max_c);
+	ccprintf("   },\n"); /* end of batt_info */
+}
+
+static int cc_batt_conf(int argc, const char *argv[])
+{
+	if (argc == 1) {
+		batt_conf_dump(&scratch_battery_conf);
+	} else if (argc == 2 && strcasecmp(argv[1], "read") == 0) {
+		batt_conf_read_fuel_gauge_info(&scratch_battery_conf);
+		batt_conf_read_battery_info(&scratch_battery_conf);
+	} else if (argc == 2 && strcasecmp(argv[1], "reset") == 0) {
+		memcpy(&scratch_battery_conf, &default_battery_conf,
+		       sizeof(scratch_battery_conf));
+	} else {
+		return EC_ERROR_PARAM_COUNT;
+	}
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(bcfg, cc_batt_conf, "[read | reset]",
+			"\n"
+			"Dump scratch battery config\n"
+			"[reset] Load default config to scratch buffer\n"
+			"[read] Load config from CBI to scratch buffer\n");
+#endif /* CONFIG_CMD_BATTERY_CONFIG */
diff --git a/common/battery_fuel_gauge.c b/common/battery_fuel_gauge.c
index 444144dfeb..d19158c62f 100644
--- a/common/battery_fuel_gauge.c
+++ b/common/battery_fuel_gauge.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -7,21 +7,106 @@
 
 #include "battery_fuel_gauge.h"
 #include "battery_smart.h"
+#include "builtin/assert.h"
 #include "console.h"
 #include "hooks.h"
 #include "i2c.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
+#ifdef CONFIG_BATTERY_CONFIG_IN_CBI
+static const struct board_batt_params *battery_conf = &default_battery_conf;
+#endif
+
+/*
+ * Authenticate the battery connected.
+ *
+ * Compare the manufacturer name read from the fuel gauge to the
+ * manufacturer names defined in the board_battery_info table. If
+ * a device name has been specified in the board_battery_info table,
+ * then both the manufacturer and device name must match.
+ */
+test_export_static bool authenticate_battery_type(int index,
+						  const char *manuf_name)
+{
+	char device_name[32];
+
+	const struct fuel_gauge_info *const fuel_gauge =
+		&board_battery_info[index].fuel_gauge;
+	int len = 0;
+
+	/* check for valid index */
+	if (index >= BATTERY_TYPE_COUNT)
+		return false;
+
+	/* manufacturer name mismatch */
+	if (strcasecmp(manuf_name, fuel_gauge->manuf_name))
+		return false;
+
+	/* device name is specified in table */
+	if (fuel_gauge->device_name != NULL) {
+		/* Get the device name */
+		if (battery_device_name(device_name, sizeof(device_name)))
+			return false;
+
+		len = strlen(fuel_gauge->device_name);
+
+		/* device name mismatch */
+		if (strncasecmp(device_name, fuel_gauge->device_name, len))
+			return false;
+	}
+
+	CPRINTS("found batt:%s", fuel_gauge->manuf_name);
+	return true;
+}
+
+#ifdef CONFIG_BATTERY_TYPE_NO_AUTO_DETECT
+
+/* Variable to decide the battery type */
+static int fixed_battery_type = BATTERY_TYPE_UNINITIALIZED;
+
+/*
+ * Function to get the fixed battery type.
+ */
+static int battery_get_fixed_battery_type(void)
+{
+	if (fixed_battery_type == BATTERY_TYPE_UNINITIALIZED) {
+		CPRINTS("Warning: Battery type is not Initialized! "
+			"Setting to default battery type.\n");
+		fixed_battery_type = DEFAULT_BATTERY_TYPE;
+	}
+
+	return fixed_battery_type;
+}
+
+/*
+ * Function to set the battery type, when auto-detection cannot be used.
+ */
+void battery_set_fixed_battery_type(int type)
+{
+	if (type < BATTERY_TYPE_COUNT)
+		fixed_battery_type = type;
+}
+#endif /* CONFIG_BATTERY_TYPE_NO_AUTO_DETECT */
+
+/**
+ * Allows us to override the battery in order to select the battery which has
+ * the right configuration for the test.
+ */
+test_export_static int battery_fuel_gauge_type_override = -1;
 
 /* Get type of the battery connected on the board */
 static int get_battery_type(void)
 {
-	char manuf_name[32], device_name[32];
+	char manuf_name[32];
 	int i;
 	static enum battery_type battery_type = BATTERY_TYPE_COUNT;
 
+	if (IS_ENABLED(TEST_BUILD) && battery_fuel_gauge_type_override >= 0) {
+		return battery_fuel_gauge_type_override;
+	}
+
 	/*
 	 * If battery_type is not the default value, then can return here
 	 * as there is no need to query the fuel gauge.
@@ -33,64 +118,75 @@ static int get_battery_type(void)
 	if (battery_manufacturer_name(manuf_name, sizeof(manuf_name)))
 		return battery_type;
 
-	/*
-	 * Compare the manufacturer name read from the fuel gauge to the
-	 * manufacturer names defined in the board_battery_info table. If
-	 * a device name has been specified in the board_battery_info table,
-	 * then both the manufacturer and device name must match.
-	 */
+#if defined(CONFIG_BATTERY_TYPE_NO_AUTO_DETECT)
+	i = battery_get_fixed_battery_type();
+	if (authenticate_battery_type(i, manuf_name))
+		battery_type = i;
+#else
 	for (i = 0; i < BATTERY_TYPE_COUNT; i++) {
-		const struct fuel_gauge_info * const fuel_gauge =
-			&board_battery_info[i].fuel_gauge;
-
-		if (strcasecmp(manuf_name, fuel_gauge->manuf_name))
-			continue;
+		if (authenticate_battery_type(i, manuf_name)) {
+			battery_type = i;
+			break;
+		}
+	}
+#endif
 
-		if (fuel_gauge->device_name != NULL) {
+	return battery_type;
+}
 
-			if (battery_device_name(device_name,
-						sizeof(device_name)))
-				continue;
+__overridable int board_get_default_battery_type(void)
+{
+	return DEFAULT_BATTERY_TYPE;
+}
 
-			if (strcasecmp(device_name, fuel_gauge->device_name))
-				continue;
-		}
+#ifdef CONFIG_BATTERY_CONFIG_IN_CBI
+void init_battery_type(void)
+{
+	int type = get_battery_type();
 
-		CPRINTS("found batt:%s", fuel_gauge->manuf_name);
-		battery_type = i;
-		break;
+	if (type == BATTERY_TYPE_COUNT) {
+		CPRINTS("battery not found");
+		type = board_get_default_battery_type();
 	}
 
-	return battery_type;
+	battery_conf = &board_battery_info[type];
 }
 
-/*
- * Initialize the battery type for the board.
- *
- * The first call to battery_get_info() is when the charger task starts, so
- * initialize the battery type as soon as I2C is initialized.
- */
-static void init_battery_type(void)
+const struct board_batt_params *get_batt_params(void)
+{
+	return battery_conf;
+}
+
+#else /* !CONFIG_BATTERY_CONFIG_IN_CBI */
+
+void init_battery_type(void)
 {
 	if (get_battery_type() == BATTERY_TYPE_COUNT)
 		CPRINTS("battery not found");
 }
-DECLARE_HOOK(HOOK_INIT, init_battery_type, HOOK_PRIO_INIT_I2C + 1);
 
-static inline const struct board_batt_params *get_batt_params(void)
+const struct board_batt_params *get_batt_params(void)
 {
 	int type = get_battery_type();
 
 	return &board_battery_info[type == BATTERY_TYPE_COUNT ?
-		DEFAULT_BATTERY_TYPE : type];
+					   board_get_default_battery_type() :
+					   type];
 }
+#endif /* CONFIG_BATTERY_CONFIG_IN_CBI */
 
 const struct battery_info *battery_get_info(void)
 {
 	return &get_batt_params()->batt_info;
 }
 
-int cut_off_battery_block_write(const struct ship_mode_info *ship_mode)
+/**
+ * Battery cut off command via SMBus write block.
+ *
+ * @param ship_mode		Battery ship mode information
+ * @return non-zero if error
+ */
+static int cut_off_battery_block_write(const struct ship_mode_info *ship_mode)
 {
 	int rv;
 
@@ -117,7 +213,13 @@ int cut_off_battery_block_write(const struct ship_mode_info *ship_mode)
 	return sb_write_block(ship_mode->reg_addr, cutdata, sizeof(cutdata));
 }
 
-int cut_off_battery_sb_write(const struct ship_mode_info *ship_mode)
+/**
+ * Battery cut off command via SMBus write word.
+ *
+ * @param ship_mode		Battery ship mode information
+ * @return non-zero if error
+ */
+static int cut_off_battery_sb_write(const struct ship_mode_info *ship_mode)
 {
 	int rv;
 
@@ -129,59 +231,74 @@ int cut_off_battery_sb_write(const struct ship_mode_info *ship_mode)
 	return sb_write(ship_mode->reg_addr, ship_mode->reg_data[1]);
 }
 
-int board_cut_off_battery(void)
+__overridable int board_cut_off_battery(void)
 {
+	const struct board_batt_params *params = get_batt_params();
 	int rv;
-	int type = get_battery_type();
 
-	/* If battery type is unknown can't send ship mode command */
-	if (type == BATTERY_TYPE_COUNT)
+	/* If battery is unknown can't send ship mode command */
+	if (!params)
 		return EC_RES_ERROR;
 
-	if (board_battery_info[type].fuel_gauge.ship_mode.wb_support)
-		rv = cut_off_battery_block_write(
-			  &board_battery_info[type].fuel_gauge.ship_mode);
+	if (params->fuel_gauge.ship_mode.wb_support)
+		rv = cut_off_battery_block_write(&params->fuel_gauge.ship_mode);
 	else
-		rv = cut_off_battery_sb_write(
-			  &board_battery_info[type].fuel_gauge.ship_mode);
+		rv = cut_off_battery_sb_write(&params->fuel_gauge.ship_mode);
 
 	return rv ? EC_RES_ERROR : EC_RES_SUCCESS;
 }
 
+enum ec_error_list battery_sleep_fuel_gauge(void)
+{
+	const struct board_batt_params *params = get_batt_params();
+	const struct sleep_mode_info *sleep_command;
+
+	/* Sleep entry command must be supplied as it will vary by gauge */
+	if (!params)
+		return EC_ERROR_UNKNOWN;
+
+	sleep_command = &params->fuel_gauge.sleep_mode;
+
+	if (!sleep_command->sleep_supported)
+		return EC_ERROR_UNIMPLEMENTED;
+
+	return sb_write(sleep_command->reg_addr, sleep_command->reg_data);
+}
+
 static enum ec_error_list battery_get_fet_status_regval(int *regval)
 {
+	const struct board_batt_params *params = get_batt_params();
 	int rv;
 	uint8_t data[6];
-	int type = get_battery_type();
 
-	/* If battery type is not known, can't check CHG/DCHG FETs */
-	if (type == BATTERY_TYPE_COUNT) {
-		/* Still don't know, so return here */
-		return EC_ERROR_BUSY;
-	}
+	ASSERT(params);
 
 	/* Read the status of charge/discharge FETs */
-	if (board_battery_info[type].fuel_gauge.fet.mfgacc_support == 1) {
-		rv = sb_read_mfgacc(PARAM_OPERATION_STATUS,
-				    SB_ALT_MANUFACTURER_ACCESS, data,
-				    sizeof(data));
+	if (params->fuel_gauge.fet.mfgacc_support == 1) {
+		if (params->fuel_gauge.fet.mfgacc_smb_block == 1)
+			rv = sb_read_mfgacc_block(PARAM_OPERATION_STATUS,
+						  SB_ALT_MANUFACTURER_ACCESS,
+						  data, sizeof(data));
+		else
+			rv = sb_read_mfgacc(PARAM_OPERATION_STATUS,
+					    SB_ALT_MANUFACTURER_ACCESS, data,
+					    sizeof(data));
 		/* Get the lowest 16bits of the OperationStatus() data */
 		*regval = data[2] | data[3] << 8;
 	} else
-		rv = sb_read(board_battery_info[type].fuel_gauge.fet.reg_addr,
-			     regval);
+		rv = sb_read(params->fuel_gauge.fet.reg_addr, regval);
 
 	return rv;
 }
 
-int battery_is_charge_fet_disabled(void)
+test_mockable int battery_is_charge_fet_disabled(void)
 {
+	const struct board_batt_params *params = get_batt_params();
 	int rv;
 	int reg;
-	int type = get_battery_type();
 
 	/* If battery type is not known, can't check CHG/DCHG FETs */
-	if (type == BATTERY_TYPE_COUNT) {
+	if (!params) {
 		/* Still don't know, so return here */
 		return -1;
 	}
@@ -189,15 +306,15 @@ int battery_is_charge_fet_disabled(void)
 	/*
 	 * If the CFET mask hasn't been defined, assume that it's not disabled.
 	 */
-	if (!board_battery_info[type].fuel_gauge.fet.cfet_mask)
+	if (!params->fuel_gauge.fet.cfet_mask)
 		return 0;
 
 	rv = battery_get_fet_status_regval(&reg);
 	if (rv)
 		return -1;
 
-	return (reg & board_battery_info[type].fuel_gauge.fet.cfet_mask) ==
-	       board_battery_info[type].fuel_gauge.fet.cfet_off_val;
+	return (reg & params->fuel_gauge.fet.cfet_mask) ==
+	       params->fuel_gauge.fet.cfet_off_val;
 }
 
 /*
@@ -214,24 +331,23 @@ int battery_is_charge_fet_disabled(void)
  */
 enum battery_disconnect_state battery_get_disconnect_state(void)
 {
+	const struct board_batt_params *params = get_batt_params();
 	int reg;
-	int type = get_battery_type();
 
 	/* If battery type is not known, can't check CHG/DCHG FETs */
-	if (type == BATTERY_TYPE_COUNT) {
+	if (!params) {
 		/* Still don't know, so return here */
-		return EC_ERROR_BUSY;
+		return BATTERY_DISCONNECT_ERROR;
 	}
 
 	if (battery_get_fet_status_regval(&reg))
 		return BATTERY_DISCONNECT_ERROR;
 
-	if ((reg & board_battery_info[type].fuel_gauge.fet.reg_mask) ==
-	    board_battery_info[type].fuel_gauge.fet.disconnect_val) {
+	if ((reg & params->fuel_gauge.fet.reg_mask) ==
+	    params->fuel_gauge.fet.disconnect_val) {
 		CPRINTS("Batt disconnected: reg 0x%04x mask 0x%04x disc 0x%04x",
-			reg,
-			board_battery_info[type].fuel_gauge.fet.reg_mask,
-			board_battery_info[type].fuel_gauge.fet.disconnect_val);
+			reg, params->fuel_gauge.fet.reg_mask,
+			params->fuel_gauge.fet.disconnect_val);
 		return BATTERY_DISCONNECTED;
 	}
 
@@ -241,14 +357,13 @@ enum battery_disconnect_state battery_get_disconnect_state(void)
 #ifdef CONFIG_BATTERY_MEASURE_IMBALANCE
 int battery_imbalance_mv(void)
 {
-	int type = get_battery_type();
+	const struct board_batt_params *params = get_batt_params();
 
 	/*
 	 * If battery type is unknown, we cannot safely access non-standard
 	 * registers.
 	 */
-	return (type == BATTERY_TYPE_COUNT) ? 0 :
-		board_battery_info[type].fuel_gauge.imbalance_mv();
+	return (!params) ? 0 : params->fuel_gauge.imbalance_mv();
 }
 
 int battery_default_imbalance_mv(void)
diff --git a/common/battery_v1.c b/common/battery_v1.c
new file mode 100644
index 0000000000..2c81d6b446
--- /dev/null
+++ b/common/battery_v1.c
@@ -0,0 +1,175 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery V1 APIs.
+ */
+
+#include "battery.h"
+#include "charge_state.h"
+#include "common.h"
+#include "console.h"
+#include "extpower.h"
+#include "host_command.h"
+#include "math_util.h"
+#include "printf.h"
+#include "util.h"
+
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+
+/* Returns zero if every item was updated. */
+int update_static_battery_info(void)
+{
+	char *batt_str;
+	int batt_serial;
+	uint8_t batt_flags = 0;
+	/*
+	 * The return values have type enum ec_error_list, but EC_SUCCESS is
+	 * zero. We'll just look for any failures so we can try them all again.
+	 */
+	int rv;
+
+	/* Smart battery serial number is 16 bits */
+	batt_str = (char *)host_get_memmap(EC_MEMMAP_BATT_SERIAL);
+	memset(batt_str, 0, EC_MEMMAP_TEXT_MAX);
+	rv = battery_serial_number(&batt_serial);
+	if (!rv) {
+		if (snprintf(batt_str, EC_MEMMAP_TEXT_MAX, "%04X",
+			     batt_serial) <= 0)
+			rv |= EC_ERROR_UNKNOWN;
+	}
+
+	/* Design Capacity of Full */
+	rv |= battery_design_capacity(
+		(int *)host_get_memmap(EC_MEMMAP_BATT_DCAP));
+
+	/* Design Voltage */
+	rv |= battery_design_voltage(
+		(int *)host_get_memmap(EC_MEMMAP_BATT_DVLT));
+
+	/* Last Full Charge Capacity (this is only mostly static) */
+	rv |= battery_full_charge_capacity(
+		(int *)host_get_memmap(EC_MEMMAP_BATT_LFCC));
+
+	/* Cycle Count */
+	rv |= battery_cycle_count((int *)host_get_memmap(EC_MEMMAP_BATT_CCNT));
+
+	/* Battery Manufacturer string */
+	batt_str = (char *)host_get_memmap(EC_MEMMAP_BATT_MFGR);
+	memset(batt_str, 0, EC_MEMMAP_TEXT_MAX);
+	rv |= battery_manufacturer_name(batt_str, EC_MEMMAP_TEXT_MAX);
+
+	/* Battery Model string */
+	batt_str = (char *)host_get_memmap(EC_MEMMAP_BATT_MODEL);
+	memset(batt_str, 0, EC_MEMMAP_TEXT_MAX);
+	rv |= battery_device_name(batt_str, EC_MEMMAP_TEXT_MAX);
+
+	/* Battery Type string */
+	batt_str = (char *)host_get_memmap(EC_MEMMAP_BATT_TYPE);
+	rv |= battery_device_chemistry(batt_str, EC_MEMMAP_TEXT_MAX);
+
+	/* Zero the dynamic entries. They'll come next. */
+	*(int *)host_get_memmap(EC_MEMMAP_BATT_VOLT) = 0;
+	*(int *)host_get_memmap(EC_MEMMAP_BATT_RATE) = 0;
+	*(int *)host_get_memmap(EC_MEMMAP_BATT_CAP) = 0;
+	*(int *)host_get_memmap(EC_MEMMAP_BATT_LFCC) = 0;
+	if (extpower_is_present())
+		batt_flags |= EC_BATT_FLAG_AC_PRESENT;
+	*host_get_memmap(EC_MEMMAP_BATT_FLAG) = batt_flags;
+
+	if (rv)
+		charge_problem(PR_STATIC_UPDATE, rv);
+	else
+		/* No errors seen. Battery data is now present */
+		*host_get_memmap(EC_MEMMAP_BATTERY_VERSION) = 1;
+
+	return rv;
+}
+
+void update_dynamic_battery_info(void)
+{
+	/* The memmap address is constant. We should fix these calls somehow. */
+	int *memmap_volt = (int *)host_get_memmap(EC_MEMMAP_BATT_VOLT);
+	int *memmap_rate = (int *)host_get_memmap(EC_MEMMAP_BATT_RATE);
+	int *memmap_cap = (int *)host_get_memmap(EC_MEMMAP_BATT_CAP);
+	int *memmap_lfcc = (int *)host_get_memmap(EC_MEMMAP_BATT_LFCC);
+	uint8_t *memmap_flags = host_get_memmap(EC_MEMMAP_BATT_FLAG);
+	uint8_t tmp;
+	int send_batt_status_event = 0;
+	int send_batt_info_event = 0;
+	static int batt_present;
+	struct charge_state_data *curr;
+
+	curr = charge_get_status();
+	tmp = 0;
+	if (curr->ac)
+		tmp |= EC_BATT_FLAG_AC_PRESENT;
+
+	if (curr->batt.is_present == BP_YES) {
+		tmp |= EC_BATT_FLAG_BATT_PRESENT;
+		batt_present = 1;
+		/* Tell the AP to read battery info if it is newly present. */
+		if (!(*memmap_flags & EC_BATT_FLAG_BATT_PRESENT))
+			send_batt_info_event++;
+	} else {
+		/*
+		 * Require two consecutive updates with BP_NOT_SURE
+		 * before reporting it gone to the host.
+		 */
+		if (batt_present)
+			tmp |= EC_BATT_FLAG_BATT_PRESENT;
+		else if (*memmap_flags & EC_BATT_FLAG_BATT_PRESENT)
+			send_batt_info_event++;
+		batt_present = 0;
+	}
+
+	if (curr->batt.flags & BATT_FLAG_BAD_ANY)
+		tmp |= EC_BATT_FLAG_INVALID_DATA;
+
+	if (!(curr->batt.flags & BATT_FLAG_BAD_VOLTAGE))
+		*memmap_volt = curr->batt.voltage;
+
+	if (!(curr->batt.flags & BATT_FLAG_BAD_CURRENT))
+		*memmap_rate = ABS(curr->batt.current);
+
+	if (!(curr->batt.flags & BATT_FLAG_BAD_REMAINING_CAPACITY)) {
+		/*
+		 * If we're running off the battery, it must have some charge.
+		 * Don't report zero charge, as that has special meaning
+		 * to Chrome OS powerd.
+		 */
+		if (curr->batt.remaining_capacity == 0 &&
+		    !curr->batt_is_charging)
+			*memmap_cap = 1;
+		else
+			*memmap_cap = curr->batt.remaining_capacity;
+	}
+
+	if (!(curr->batt.flags & BATT_FLAG_BAD_FULL_CAPACITY) &&
+	    (curr->batt.full_capacity <= (*memmap_lfcc - LFCC_EVENT_THRESH) ||
+	     curr->batt.full_capacity >= (*memmap_lfcc + LFCC_EVENT_THRESH))) {
+		*memmap_lfcc = curr->batt.full_capacity;
+		/* Poke the AP if the full_capacity changes. */
+		send_batt_info_event++;
+	}
+
+	if (curr->batt.is_present == BP_YES &&
+	    battery_is_below_threshold(BATT_THRESHOLD_TYPE_SHUTDOWN, false))
+		tmp |= EC_BATT_FLAG_LEVEL_CRITICAL;
+
+	tmp |= curr->batt_is_charging ? EC_BATT_FLAG_CHARGING :
+					EC_BATT_FLAG_DISCHARGING;
+
+	/* Tell the AP to re-read battery status if charge state changes */
+	if (*memmap_flags != tmp)
+		send_batt_status_event++;
+
+	/* Update flags before sending host events. */
+	*memmap_flags = tmp;
+
+	if (send_batt_info_event)
+		host_set_single_event(EC_HOST_EVENT_BATTERY);
+	if (send_batt_status_event)
+		host_set_single_event(EC_HOST_EVENT_BATTERY_STATUS);
+}
diff --git a/common/battery_v2.c b/common/battery_v2.c
new file mode 100644
index 0000000000..e0c1ed2b54
--- /dev/null
+++ b/common/battery_v2.c
@@ -0,0 +1,519 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery V2 APIs.
+ */
+
+#include "battery.h"
+#include "charge_state.h"
+#include "common.h"
+#include "console.h"
+#include "extpower.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "math_util.h"
+#include "printf.h"
+#include "util.h"
+
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+
+/*
+ * Store battery information in these 2 structures. Main (lid) battery is always
+ * at index 0, and secondary (base) battery at index 1.
+ */
+struct battery_static_info battery_static[CONFIG_BATTERY_COUNT];
+struct ec_response_battery_dynamic_info battery_dynamic[CONFIG_BATTERY_COUNT];
+
+#ifdef HAS_TASK_HOSTCMD
+static void battery_update(enum battery_index i)
+{
+	char *batt_str;
+	int *memmap_dcap = (int *)host_get_memmap(EC_MEMMAP_BATT_DCAP);
+	int *memmap_dvlt = (int *)host_get_memmap(EC_MEMMAP_BATT_DVLT);
+	int *memmap_ccnt = (int *)host_get_memmap(EC_MEMMAP_BATT_CCNT);
+	int *memmap_volt = (int *)host_get_memmap(EC_MEMMAP_BATT_VOLT);
+	int *memmap_rate = (int *)host_get_memmap(EC_MEMMAP_BATT_RATE);
+	int *memmap_cap = (int *)host_get_memmap(EC_MEMMAP_BATT_CAP);
+	int *memmap_lfcc = (int *)host_get_memmap(EC_MEMMAP_BATT_LFCC);
+	uint8_t *memmap_flags = host_get_memmap(EC_MEMMAP_BATT_FLAG);
+
+	/* Smart battery serial number is 16 bits */
+	batt_str = (char *)host_get_memmap(EC_MEMMAP_BATT_SERIAL);
+	memcpy(batt_str, battery_static[i].serial_ext, EC_MEMMAP_TEXT_MAX);
+	batt_str[EC_MEMMAP_TEXT_MAX - 1] = 0;
+
+	/* Design Capacity of Full */
+	*memmap_dcap = battery_static[i].design_capacity;
+
+	/* Design Voltage */
+	*memmap_dvlt = battery_static[i].design_voltage;
+
+	/* Cycle Count */
+	*memmap_ccnt = battery_static[i].cycle_count;
+
+	/* Battery Manufacturer string */
+	batt_str = (char *)host_get_memmap(EC_MEMMAP_BATT_MFGR);
+	memcpy(batt_str, battery_static[i].manufacturer_ext,
+	       EC_MEMMAP_TEXT_MAX);
+	batt_str[EC_MEMMAP_TEXT_MAX - 1] = 0;
+
+	/* Battery Model string */
+	batt_str = (char *)host_get_memmap(EC_MEMMAP_BATT_MODEL);
+	memcpy(batt_str, battery_static[i].model_ext, EC_MEMMAP_TEXT_MAX);
+	batt_str[EC_MEMMAP_TEXT_MAX - 1] = 0;
+
+	/* Battery Type string */
+	batt_str = (char *)host_get_memmap(EC_MEMMAP_BATT_TYPE);
+	memcpy(batt_str, battery_static[i].type_ext, EC_MEMMAP_TEXT_MAX);
+	batt_str[EC_MEMMAP_TEXT_MAX - 1] = 0;
+
+	*memmap_volt = battery_dynamic[i].actual_voltage;
+	/*
+	 * Rate must be absolute, flags will indicate whether
+	 * the battery is charging or discharging.
+	 */
+	*memmap_rate = ABS(battery_dynamic[i].actual_current);
+	*memmap_cap = battery_dynamic[i].remaining_capacity;
+	*memmap_lfcc = battery_dynamic[i].full_capacity;
+	*memmap_flags = battery_dynamic[i].flags;
+}
+
+#ifdef CONFIG_HOSTCMD_BATTERY_V2
+static enum ec_status
+host_command_battery_get_static(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_battery_static_info *p = args->params;
+	const struct battery_static_info *bs;
+
+	if (p->index >= CONFIG_BATTERY_COUNT)
+		return EC_RES_INVALID_PARAM;
+	bs = &battery_static[p->index];
+
+	battery_update(p->index);
+	if (args->version == 0) {
+		struct ec_response_battery_static_info *r = args->response;
+
+		r->design_capacity = bs->design_capacity;
+		r->design_voltage = bs->design_voltage;
+		r->cycle_count = bs->cycle_count;
+
+		strzcpy(r->manufacturer, bs->manufacturer_ext,
+			sizeof(r->manufacturer));
+		strzcpy(r->model, bs->model_ext, sizeof(r->model));
+		strzcpy(r->serial, bs->serial_ext, sizeof(r->serial));
+		strzcpy(r->type, bs->type_ext, sizeof(r->type));
+
+		args->response_size = sizeof(*r);
+	} else if (args->version == 1) {
+		struct ec_response_battery_static_info_v1 *r = args->response;
+
+		r->design_capacity = bs->design_capacity;
+		r->design_voltage = bs->design_voltage;
+		r->cycle_count = bs->cycle_count;
+
+		strzcpy(r->manufacturer_ext, bs->manufacturer_ext,
+			sizeof(r->manufacturer_ext));
+		strzcpy(r->model_ext, bs->model_ext, sizeof(r->model_ext));
+		strzcpy(r->serial_ext, bs->serial_ext, sizeof(r->serial_ext));
+		strzcpy(r->type_ext, bs->type_ext, sizeof(r->type_ext));
+
+		args->response_size = sizeof(*r);
+	} else if (args->version == 2) {
+		struct ec_response_battery_static_info_v2 *r = args->response;
+
+		r->design_capacity = bs->design_capacity;
+		r->design_voltage = bs->design_voltage;
+		r->cycle_count = bs->cycle_count;
+
+		strzcpy(r->manufacturer, bs->manufacturer_ext,
+			sizeof(r->manufacturer));
+		strzcpy(r->device_name, bs->model_ext, sizeof(r->device_name));
+		strzcpy(r->serial, bs->serial_ext, sizeof(r->serial));
+		strzcpy(r->chemistry, bs->type_ext, sizeof(r->chemistry));
+
+		args->response_size = sizeof(*r);
+	} else {
+		return EC_RES_INVALID_VERSION;
+	}
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_BATTERY_GET_STATIC, host_command_battery_get_static,
+		     EC_VER_MASK(0) | EC_VER_MASK(1) | EC_VER_MASK(2));
+
+static enum ec_status
+host_command_battery_get_dynamic(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_battery_dynamic_info *p = args->params;
+	struct ec_response_battery_dynamic_info *r = args->response;
+
+	if (p->index >= CONFIG_BATTERY_COUNT)
+		return EC_RES_INVALID_PARAM;
+
+	args->response_size = sizeof(*r);
+	memcpy(r, &battery_dynamic[p->index], sizeof(*r));
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_BATTERY_GET_DYNAMIC,
+		     host_command_battery_get_dynamic, EC_VER_MASK(0));
+#endif /* CONFIG_HOSTCMD_BATTERY_V2 */
+
+void battery_memmap_refresh(enum battery_index index)
+{
+	if (*host_get_memmap(EC_MEMMAP_BATT_INDEX) == index)
+		battery_update(index);
+}
+
+void battery_memmap_set_index(enum battery_index index)
+{
+	if (*host_get_memmap(EC_MEMMAP_BATT_INDEX) == index)
+		return;
+
+	*host_get_memmap(EC_MEMMAP_BATT_INDEX) = BATT_IDX_INVALID;
+	if (index < 0 || index >= CONFIG_BATTERY_COUNT)
+		return;
+
+	battery_update(index);
+	*host_get_memmap(EC_MEMMAP_BATT_INDEX) = index;
+}
+
+static void battery_init(void)
+{
+	*host_get_memmap(EC_MEMMAP_BATT_INDEX) = BATT_IDX_INVALID;
+	*host_get_memmap(EC_MEMMAP_BATT_COUNT) = CONFIG_BATTERY_COUNT;
+	*host_get_memmap(EC_MEMMAP_BATTERY_VERSION) = 2;
+
+	battery_memmap_set_index(BATT_IDX_MAIN);
+}
+DECLARE_HOOK(HOOK_INIT, battery_init, HOOK_PRIO_DEFAULT);
+#endif /* HAS_TASK_HOSTCMD */
+
+static int is_battery_string_reliable(const char *buf)
+{
+	/*
+	 * From is_string_printable rule, 0xFF is not printable.
+	 * So, EC should think battery string is unreliable if string
+	 * include 0xFF.
+	 */
+	while (*buf) {
+		if ((*buf) == '\xff')
+			return 0;
+		buf++;
+	}
+
+	return 1;
+}
+
+int update_static_battery_info(void)
+{
+	int batt_serial;
+	int val;
+	/*
+	 * The return values have type enum ec_error_list, but EC_SUCCESS is
+	 * zero. We'll just look for any failures so we can try them all again.
+	 */
+	int rv, ret;
+
+	struct battery_static_info *const bs = &battery_static[BATT_IDX_MAIN];
+
+	/* Clear all static information. */
+	memset(bs, 0, sizeof(*bs));
+
+	/* Smart battery serial number is 16 bits */
+	rv = battery_serial_number(&batt_serial);
+	if (!rv)
+		if (snprintf(bs->serial_ext, sizeof(bs->serial_ext), "%04X",
+			     batt_serial) <= 0)
+			rv |= EC_ERROR_UNKNOWN;
+
+	/* Design Capacity of Full */
+	ret = battery_design_capacity(&val);
+	if (!ret)
+		bs->design_capacity = val;
+	rv |= ret;
+
+	/* Design Voltage */
+	ret = battery_design_voltage(&val);
+	if (!ret)
+		bs->design_voltage = val;
+	rv |= ret;
+
+	/* Cycle Count */
+	ret = battery_cycle_count(&val);
+	if (!ret)
+		bs->cycle_count = val;
+	rv |= ret;
+
+	/* Battery Manufacturer string */
+	rv |= battery_manufacturer_name(bs->manufacturer_ext,
+					sizeof(bs->manufacturer_ext));
+
+	/* Battery Model string */
+	rv |= battery_device_name(bs->model_ext, sizeof(bs->model_ext));
+
+	/* Battery Type string */
+	rv |= battery_device_chemistry(bs->type_ext, sizeof(bs->type_ext));
+
+	/*
+	 * b/181639264: Battery gauge follow SMBus SPEC and SMBus define
+	 * cumulative clock low extend time for both controller (master) and
+	 * peripheral (slave). However, I2C doesn't.
+	 * Regarding this issue, we observe EC sometimes pull I2C CLK low
+	 * a while after EC start running. Actually, we are not sure the
+	 * reason until now.
+	 * If EC pull I2C CLK low too long, and it may cause battery fw timeout
+	 * because battery count cumulative clock extend time over 25ms.
+	 * When it happened, battery will release both its CLK and DATA and
+	 * reset itself. So, EC may get 0xFF when EC keep reading data from
+	 * battery. Battery static information will be unreliable and need to
+	 * be updated.
+	 * This change is improvement that EC should retry if battery string is
+	 * unreliable.
+	 */
+	if (!is_battery_string_reliable(bs->serial_ext) ||
+	    !is_battery_string_reliable(bs->manufacturer_ext) ||
+	    !is_battery_string_reliable(bs->model_ext) ||
+	    !is_battery_string_reliable(bs->type_ext))
+		rv |= EC_ERROR_UNKNOWN;
+
+	/* Zero the dynamic entries. They'll come next. */
+	memset(&battery_dynamic[BATT_IDX_MAIN], 0,
+	       sizeof(battery_dynamic[BATT_IDX_MAIN]));
+
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+	if (extpower_is_present())
+		battery_dynamic[BATT_IDX_MAIN].flags |= EC_BATT_FLAG_AC_PRESENT;
+	else
+		battery_dynamic[BATT_IDX_MAIN].flags &= ~EC_BATT_FLAG_AC_PRESENT;
+#endif
+
+	if (rv)
+		charge_problem(PR_STATIC_UPDATE, rv);
+
+#ifdef HAS_TASK_HOSTCMD
+	battery_memmap_refresh(BATT_IDX_MAIN);
+#endif
+
+	return rv;
+}
+
+void update_dynamic_battery_info(void)
+{
+	static int batt_present;
+	uint8_t tmp;
+	int send_batt_status_event = 0;
+	int send_batt_info_event = 0;
+	struct charge_state_data *curr;
+	struct ec_response_battery_dynamic_info *const bd =
+		&battery_dynamic[BATT_IDX_MAIN];
+
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+	struct battery_static_info *const bs = &battery_static[BATT_IDX_MAIN];
+	static int batt_os_percentage;
+	int rsoc_percentage;
+	int design_percentage;
+	static int brc_retry;
+	static int bfc_retry;
+#endif
+
+	curr = charge_get_status();
+	tmp = 0;
+	if (curr->ac)
+		tmp |= EC_BATT_FLAG_AC_PRESENT;
+
+	if (curr->batt.is_present == BP_YES) {
+		tmp |= EC_BATT_FLAG_BATT_PRESENT;
+		batt_present = 1;
+		/* Tell the AP to read battery info if it is newly present. */
+		if (!(bd->flags & EC_BATT_FLAG_BATT_PRESENT))
+			send_batt_info_event++;
+	} else {
+		/*
+		 * Require two consecutive updates with BP_NOT_SURE
+		 * before reporting it gone to the host.
+		 */
+		if (batt_present)
+			tmp |= EC_BATT_FLAG_BATT_PRESENT;
+		else if (bd->flags & EC_BATT_FLAG_BATT_PRESENT)
+			send_batt_info_event++;
+		batt_present = 0;
+	}
+
+	if (curr->batt.flags & BATT_FLAG_BAD_ANY)
+		tmp |= EC_BATT_FLAG_INVALID_DATA;
+
+	if (!(curr->batt.flags & BATT_FLAG_BAD_VOLTAGE))
+		bd->actual_voltage = curr->batt.voltage;
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+	/* let the OS battery remaining time both empty and full time more smooth */
+	if (!(curr->batt.flags & BATT_FLAG_BAD_CURRENT))
+		bd->actual_current = battery_get_avg_current();
+#else
+	if (!(curr->batt.flags & BATT_FLAG_BAD_CURRENT))
+		bd->actual_current = curr->batt.current;
+#endif
+	if (!(curr->batt.flags & BATT_FLAG_BAD_DESIRED_VOLTAGE))
+		bd->desired_voltage = curr->batt.desired_voltage;
+
+	if (!(curr->batt.flags & BATT_FLAG_BAD_DESIRED_CURRENT))
+		bd->desired_current = curr->batt.desired_current;
+
+	if (!(curr->batt.flags & BATT_FLAG_BAD_REMAINING_CAPACITY)
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+		&& !(curr->batt.flags & BATT_FLAG_BAD_FULL_CAPACITY)
+#endif
+	) {
+		/*
+		 * If we're running off the battery, it must have some charge.
+		 * Don't report zero charge, as that has special meaning
+		 * to Chrome OS powerd.
+		 */
+		if (curr->batt.remaining_capacity == 0 &&
+		    !curr->batt_is_charging)
+			bd->remaining_capacity = 1;
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+		/* Avoid to show the percentage when battery fully charge */
+		else if (curr->ac && (curr->batt.status & STATUS_FULLY_CHARGED))
+			bd->remaining_capacity = curr->batt.full_capacity;
+		else {
+
+			/*
+			 * TASK:866aqnw5t
+			 * add workaround to avoid the battery abnormal response
+			 * if new RC - old RC over than dc 2% EC will not update
+			 * it, but if battery send 3 times maybe is battery
+			 * correct data.
+			 *
+			 * example: NRC(90%) 900 - ORC(96%) 960 need lower DC(1000*2/100) 20
+			 * percentage jump too much would not update.
+			 */
+			if (bd->remaining_capacity == 0)
+				bd->remaining_capacity = curr->batt.remaining_capacity;
+			else {
+				rsoc_percentage =
+					curr->batt.remaining_capacity - bd->remaining_capacity;
+				design_percentage = (bs->design_capacity * 2) / 100;
+				if (ABS(rsoc_percentage) < design_percentage) {
+					bd->remaining_capacity = curr->batt.remaining_capacity;
+				} else {
+					brc_retry++;
+					if (brc_retry > 2) {
+						bd->remaining_capacity =
+							curr->batt.remaining_capacity;
+						brc_retry = 0;
+					}
+				}
+			}
+		}
+#else
+		else
+			bd->remaining_capacity = curr->batt.remaining_capacity;
+#endif
+	}
+
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+
+	/*
+	 * TASK:866aqnw5t
+	 * add workaround to avoid the battery abnormal response
+	 * if new FC - old FC over than dc 2% EC will not update
+	 * it, but if battery send 3 times maybe is battery
+	 * correct data.
+	 *
+	 * example: NFC(100%) 900 - OFC(100%) 960 need lower DC(1000*2/100) 20
+	 * FCC jump too much would not update.
+	 */
+	if (!(curr->batt.flags & BATT_FLAG_BAD_FULL_CAPACITY) &&
+		((curr->batt.full_capacity - bd->full_capacity)
+				<  ((bs->design_capacity * 2) / 100))) {
+		if (curr->batt.full_capacity <=
+		     (bd->full_capacity - LFCC_EVENT_THRESH) ||
+			curr->batt.full_capacity >=
+		     (bd->full_capacity + LFCC_EVENT_THRESH)) {
+			bd->full_capacity = curr->batt.full_capacity;
+			/* Poke the AP if the full_capacity changes. */
+			send_batt_info_event++;
+		}
+	} else if (!(curr->batt.flags & BATT_FLAG_BAD_FULL_CAPACITY) &&
+				((curr->batt.full_capacity - bd->full_capacity)
+					>  ((bs->design_capacity * 2) / 100))) {
+		bfc_retry++;
+		if (bfc_retry > 2) {
+			bd->full_capacity = curr->batt.full_capacity;
+			send_batt_info_event++;
+			bfc_retry = 0;
+		}
+	}
+#else
+	if (!(curr->batt.flags & BATT_FLAG_BAD_FULL_CAPACITY) &&
+	    (curr->batt.full_capacity <=
+		     (bd->full_capacity - LFCC_EVENT_THRESH) ||
+	     curr->batt.full_capacity >=
+		     (bd->full_capacity + LFCC_EVENT_THRESH))) {
+		bd->full_capacity = curr->batt.full_capacity;
+		/* Poke the AP if the full_capacity changes. */
+		send_batt_info_event++;
+	}
+#endif
+
+	if (curr->batt.is_present == BP_YES &&
+	    battery_is_below_threshold(BATT_THRESHOLD_TYPE_SHUTDOWN, false))
+		tmp |= EC_BATT_FLAG_LEVEL_CRITICAL;
+
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+	batt_os_percentage = (bd->remaining_capacity * 1000) / (curr->batt.full_capacity + 1);
+	/*
+	 * sync with OS battery percentage to avoid battery show charging icon at 100%
+	 * os battery display formula: rounding (remainig / full capacity)*100
+	 */
+	if (curr->ac && batt_os_percentage > 994) {
+		tmp |= EC_BATT_FLAG_DISCHARGING;
+	} else {
+		tmp |= curr->batt_is_charging ? EC_BATT_FLAG_CHARGING :
+						EC_BATT_FLAG_DISCHARGING;
+	}
+
+	/*
+	 * in ACPI spec _BST(battery status) have a feature
+	 * 3.9.6 Battery Charge Limiting follows the spec
+	 * to return limiting status to OS and if Limiting is engaged
+	 * and the battery has reached the steady state need to
+	 * clear CHARGING and DISCHARGING flag.
+	 */
+	if (battery_sustainer_enabled()) {
+		tmp |= EC_BATT_FLAG_LIMIT_ACTIVE;
+		if (get_chg_ctrl_mode() == CHARGE_CONTROL_IDLE) {
+			tmp &= ~EC_BATT_FLAG_CHARGING;
+			tmp &= ~EC_BATT_FLAG_DISCHARGING;
+		}
+	} else
+		tmp &= ~EC_BATT_FLAG_LIMIT_ACTIVE;
+
+#else
+	tmp |= curr->batt_is_charging ? EC_BATT_FLAG_CHARGING :
+					EC_BATT_FLAG_DISCHARGING;
+#endif
+
+	if (battery_is_cut_off())
+		tmp |= EC_BATT_FLAG_CUT_OFF;
+
+	/* Tell the AP to re-read battery status if charge state changes */
+	if (bd->flags != tmp)
+		send_batt_status_event++;
+
+	bd->flags = tmp;
+
+#ifdef HAS_TASK_HOSTCMD
+	battery_memmap_refresh(BATT_IDX_MAIN);
+#endif
+
+#ifdef CONFIG_HOSTCMD_EVENTS
+	if (send_batt_info_event)
+		host_set_single_event(EC_HOST_EVENT_BATTERY);
+	if (send_batt_status_event)
+		host_set_single_event(EC_HOST_EVENT_BATTERY_STATUS);
+#endif
+}
diff --git a/common/blink.c b/common/blink.c
index ed16146f5a..dcd6f0bdaa 100644
--- a/common/blink.c
+++ b/common/blink.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,12 +10,12 @@
 #include "hooks.h"
 
 #ifndef CONFIG_BLINK_LEDS
-	#error The macro CONFIG_BLINK_LEDS must be specified to use BLINK.
+#error The macro CONFIG_BLINK_LEDS must be specified to use BLINK.
 #endif
 
 static const enum gpio_signal leds[] = { CONFIG_BLINK_LEDS };
 
-BUILD_ASSERT(ARRAY_SIZE(leds) <= sizeof(int)*8, "Too many LEDs to drive.");
+BUILD_ASSERT(ARRAY_SIZE(leds) <= sizeof(int) * 8, "Too many LEDs to drive.");
 BUILD_ASSERT(ARRAY_SIZE(leds) > 0, "Must have at least one LED to blink.");
 
 static void blink(void)
diff --git a/common/bluetooth_le.c b/common/bluetooth_le.c
index 2e68893223..d102740293 100644
--- a/common/bluetooth_le.c
+++ b/common/bluetooth_le.c
@@ -1,13 +1,14 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "bluetooth_le.h"
-#include "util.h"
+#include "builtin/assert.h"
 #include "console.h"
+#include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_BLUETOOTH_LE, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_BLUETOOTH_LE, format, ##args)
 
 /*
  * Convert from BLE Channel to frequency
@@ -15,11 +16,11 @@
  * Bluetooth 4.1 Vol 6 pg 36 4.1 Table 1.1
  */
 
-#define CHAN_0_MHZ      2404
-#define CHAN_11_MHZ     2428
-#define CHAN_37_MHZ     2402
-#define CHAN_38_MHZ     2426
-#define CHAN_39_MHZ     2480
+#define CHAN_0_MHZ 2404
+#define CHAN_11_MHZ 2428
+#define CHAN_37_MHZ 2402
+#define CHAN_38_MHZ 2426
+#define CHAN_39_MHZ 2480
 
 int chan2freq(int channel)
 {
@@ -72,11 +73,11 @@ uint8_t get_next_data_channel(struct remapping_table *rt)
 
 	/* Check if the channel is mapped */
 	if (rt->map[rt->last_unmapped_channel / 8] &
-			(1 << (rt->last_unmapped_channel % 8)))
+	    (1 << (rt->last_unmapped_channel % 8)))
 		return rt->last_unmapped_channel;
 	else
-		return rt->remapping_index
-			[rt->last_unmapped_channel % rt->num_used_channels];
+		return rt->remapping_index[rt->last_unmapped_channel %
+					   rt->num_used_channels];
 }
 
 /* BLE 4.1 Vol 3 Part C 11 */
@@ -85,27 +86,27 @@ uint8_t get_next_data_channel(struct remapping_table *rt)
 uint8_t *pack_adv(uint8_t *dest, int length, int type, const uint8_t *data)
 {
 	/* Add the structure length */
-	dest[0] = (uint8_t)length+1;
+	dest[0] = (uint8_t)length + 1;
 	/* Add the structure type */
 	dest[1] = (uint8_t)type;
 	/* Add the data */
 	memcpy(&dest[2], data, length);
 
 	/* Return a pointer to the next structure */
-	return &dest[2+length];
+	return &dest[2 + length];
 }
 
 uint8_t *pack_adv_int(uint8_t *dest, int length, int type, int data)
 {
 	/* Add the structure length */
-	dest[0] = (uint8_t)length+1;
+	dest[0] = (uint8_t)length + 1;
 	/* Add the structure type */
 	dest[1] = (uint8_t)type;
 	/* Add the data */
 	memcpy(&dest[2], &data, length);
 
 	/* Return a pointer to the next structure */
-	return &dest[2+length];
+	return &dest[2 + length];
 }
 
 uint8_t *pack_adv_addr(uint8_t *dest, uint64_t addr)
@@ -139,7 +140,7 @@ static void mem_dump(uint8_t *mem, int len)
 	for (i = 0; i < len; i++) {
 		value = mem[i];
 		if (i % 8 == 0)
-			CPRINTF("\n%pP: %02x", &mem[i], value);
+			CPRINTF("\n%p: %02x", &mem[i], value);
 		else
 			CPRINTF(" %02x", value);
 	}
@@ -160,19 +161,19 @@ void dump_ble_packet(struct ble_pdu *ble_p)
 	int curr_offs;
 
 	if (ble_p->header_type_adv) {
-		CPRINTF("BLE packet @ %pP: type %d, len %d, %s %s\n",
-			ble_p, ble_p->header.adv.type, ble_p->header.adv.length,
+		CPRINTF("BLE packet @ %p: type %d, len %d, %s %s\n", ble_p,
+			ble_p->header.adv.type, ble_p->header.adv.length,
 			(ble_p->header.adv.txaddr ? " TXADDR" : ""),
 			(ble_p->header.adv.rxaddr ? " RXADDR" : ""));
 
 		curr_offs = 0;
 
 		if (ble_p->header.adv.type ==
-			BLE_ADV_HEADER_PDU_TYPE_SCAN_REQ) {
+		    BLE_ADV_HEADER_PDU_TYPE_SCAN_REQ) {
 			dump_ble_addr(ble_p->payload, "ScanA");
 			curr_offs += BLUETOOTH_ADDR_OCTETS;
 		} else if (ble_p->header.adv.type ==
-			BLE_ADV_HEADER_PDU_TYPE_CONNECT_REQ) {
+			   BLE_ADV_HEADER_PDU_TYPE_CONNECT_REQ) {
 			dump_ble_addr(ble_p->payload, "InitA");
 			curr_offs += BLUETOOTH_ADDR_OCTETS;
 		}
@@ -187,7 +188,7 @@ void dump_ble_packet(struct ble_pdu *ble_p)
 			mem_dump(ble_p->payload + curr_offs,
 				 ble_p->header.adv.length - curr_offs);
 	} else { /* Data PDUs */
-		CPRINTF("BLE data packet @%pP: LLID %d,"
+		CPRINTF("BLE data packet @%p: LLID %d,"
 			" nesn %d, sn %d, md %d, length %d\n",
 			ble_p, ble_p->header.data.llid, ble_p->header.data.nesn,
 			ble_p->header.data.sn, ble_p->header.data.md,
@@ -195,4 +196,3 @@ void dump_ble_packet(struct ble_pdu *ble_p)
 		mem_dump(ble_p->payload, ble_p->header.data.length);
 	}
 }
-
diff --git a/common/body_detection.c b/common/body_detection.c
index f7ea95c8c4..bac4f870b3 100644
--- a/common/body_detection.c
+++ b/common/body_detection.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,22 +6,30 @@
 #include "accelgyro.h"
 #include "body_detection.h"
 #include "console.h"
+#include "hooks.h"
 #include "hwtimer.h"
 #include "lid_switch.h"
 #include "math_util.h"
+#include "mkbp_input_devices.h"
 #include "motion_sense_fifo.h"
 #include "timer.h"
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
 
-static struct motion_sensor_t *body_sensor =
+const static struct body_detect_params default_body_detect_params = {
+	.var_noise_factor = CONFIG_BODY_DETECTION_VAR_NOISE_FACTOR,
+	.var_threshold = CONFIG_BODY_DETECTION_VAR_THRESHOLD,
+	.confidence_delta = CONFIG_BODY_DETECTION_CONFIDENCE_DELTA,
+};
+
+test_export_static struct motion_sensor_t *body_sensor =
 	&motion_sensors[CONFIG_BODY_DETECTION_SENSOR];
 
 static int window_size = CONFIG_BODY_DETECTION_MAX_WINDOW_SIZE;
-static uint64_t var_threshold_scaled, confidence_delta_scaled;
+test_export_static uint64_t var_threshold_scaled, confidence_delta_scaled;
 static int stationary_timeframe;
 
 static int history_idx;
@@ -29,14 +37,20 @@ static enum body_detect_states motion_state = BODY_DETECTION_OFF_BODY;
 
 static bool history_initialized;
 static bool body_detect_enable;
+STATIC_IF(CONFIG_ACCEL_SPOOF_MODE) bool spoof_enable;
 
-static struct body_detect_motion_data
-{
+static struct body_detect_motion_data {
 	int history[CONFIG_BODY_DETECTION_MAX_WINDOW_SIZE]; /* acceleration */
-	int sum;              /* sum(history) */
+	int sum; /* sum(history) */
 	uint64_t n2_variance; /* n^2 * var(history) */
 } data[2]; /* motion data for X-axis and Y-axis */
 
+static void print_body_detect_mode(void)
+{
+	CPRINTS("body detect mode %sabled",
+		body_detect_get_state() ? "en" : "dis");
+}
+
 /*
  * This function will update new variance and new sum according to incoming
  * value, previous value, previous sum and previous variance.
@@ -48,18 +62,18 @@ static struct body_detect_motion_data
  * x_0: oldest value in the window, will be replaced by x_n
  * x_n: new coming value
  *
- * n^2 * var(x') = n^2 * var(x) + (sum(x') - sum(x))^2 +
- *                 (n * x_n - sum(x'))^2 / n - (n * x_0 - sum(x'))^2 / n
+ * n^2 * var(x') = n^2 * var(x) + (x_n - x_0) *
+ *                 (n * (x_n + x_0) - sum(x') - sum(x))
  */
 static void update_motion_data(struct body_detect_motion_data *x, int x_n)
 {
 	const int n = window_size;
 	const int x_0 = x->history[history_idx];
-	const int new_sum = x->sum + (x_n - x->history[history_idx]);
+	const int sum_diff = x_n - x_0;
+	const int new_sum = x->sum + sum_diff;
 
-	x->n2_variance = x->n2_variance + POW2((int64_t)new_sum - x->sum) +
-			 (POW2((int64_t)x_n * n - new_sum) -
-			  POW2((int64_t)x_0 * n - new_sum)) / n;
+	x->n2_variance +=
+		sum_diff * ((int64_t)n * (x_n + x_0) - new_sum - x->sum);
 	x->sum = new_sum;
 	x->history[history_idx] = x_n;
 }
@@ -75,8 +89,8 @@ static void update_motion_variance(void)
 /* return Var(X) + Var(Y) */
 static uint64_t get_motion_variance(void)
 {
-	return (data[X].n2_variance + data[Y].n2_variance)
-		/ window_size / window_size;
+	return (data[X].n2_variance + data[Y].n2_variance) / window_size /
+	       window_size;
 }
 
 static int calculate_motion_confidence(uint64_t var)
@@ -86,32 +100,41 @@ static int calculate_motion_confidence(uint64_t var)
 	if (var > var_threshold_scaled + confidence_delta_scaled)
 		return 100;
 	return 100 * (var - var_threshold_scaled + confidence_delta_scaled) /
-		(2 * confidence_delta_scaled);
+	       (2 * confidence_delta_scaled);
 }
 
 /* Change the motion state and commit the change to AP. */
-void body_detect_change_state(enum body_detect_states state)
-{
-#ifdef CONFIG_GESTURE_HOST_DETECTION
-	struct ec_response_motion_sensor_data vector = {
-		.flags = MOTIONSENSE_SENSOR_FLAG_WAKEUP,
-		.activity = MOTIONSENSE_ACTIVITY_BODY_DETECTION,
-		.state = state,
-		.sensor_num = MOTION_SENSE_ACTIVITY_SENSOR_ID,
-	};
-	motion_sense_fifo_stage_data(&vector, NULL, 0,
-			__hw_clock_source_read());
-	motion_sense_fifo_commit_data();
-#endif
+void body_detect_change_state(enum body_detect_states state, bool spoof)
+{
+	if (IS_ENABLED(CONFIG_ACCEL_SPOOF_MODE) && spoof_enable && !spoof)
+		return;
+	if (IS_ENABLED(CONFIG_GESTURE_HOST_DETECTION)) {
+		struct ec_response_motion_sensor_data vector = {
+			.flags = MOTIONSENSE_SENSOR_FLAG_BYPASS_FIFO,
+			.activity_data = {
+				.activity = MOTIONSENSE_ACTIVITY_BODY_DETECTION,
+				.state = state,
+			},
+			.sensor_num = MOTION_SENSE_ACTIVITY_SENSOR_ID,
+		};
+		motion_sense_fifo_stage_data(&vector, NULL, 0,
+					     __hw_clock_source_read());
+		motion_sense_fifo_commit_data();
+	}
 	/* change the motion state */
 	motion_state = state;
 	if (state == BODY_DETECTION_ON_BODY) {
 		/* reset time counting of stationary */
 		stationary_timeframe = 0;
 	}
+
 	/* state changing log */
-	CPRINTS("body_detect changed state to: %s body",
-		motion_state ? "on" : "off");
+	print_body_detect_mode();
+
+	if (IS_ENABLED(CONFIG_BODY_DETECTION_NOTIFY_MODE_CHANGE))
+		host_set_single_event(EC_HOST_EVENT_BODY_DETECT_CHANGE);
+
+	hook_notify(HOOK_BODY_DETECT_CHANGE);
 }
 
 enum body_detect_states body_detect_get_state(void)
@@ -131,12 +154,13 @@ static void determine_window_size(int odr)
 	}
 }
 
-/* Determine variance threshold scale by range and resolution. */
-static void determine_threshold_scale(int range, int resolution, int rms_noise)
+/* Determine variance threshold scale by range. */
+static void determine_threshold_scale(int range, int rms_noise,
+				      int var_noise_factor, int var_threshold,
+				      int confidence_delta)
 {
 	/*
 	 * range:              g
-	 * resolution:         bits
 	 * data_1g:            LSB/g
 	 * data_1g / 9800:     LSB/(mm/s^2)
 	 * (data_1g / 9800)^2: (LSB^2)/(mm^2/s^4), which number of
@@ -144,9 +168,10 @@ static void determine_threshold_scale(int range, int resolution, int rms_noise)
 	 * rms_noise:          ug
 	 * var_noise:          mm^2/s^4
 	 */
-	const int data_1g = BIT(resolution - 1) / range;
+	const int data_1g = MOTION_SCALING_FACTOR / range;
 	const int multiplier = POW2(data_1g);
 	const int divisor = POW2(9800);
+
 	/*
 	 * We are measuring the var(X) + var(Y), so theoretically, the
 	 * var(noise) should be 2 * rms_noise^2. However, in most case, on a
@@ -154,34 +179,58 @@ static void determine_threshold_scale(int range, int resolution, int rms_noise)
 	 * rms_noise^2. We can multiply the rms_noise^2 with the
 	 * CONFIG_BODY_DETECTION_VAR_NOISE_FACTOR / 100.
 	 */
-	const int var_noise = POW2((uint64_t)rms_noise) *
-			      CONFIG_BODY_DETECTION_VAR_NOISE_FACTOR * POW2(98)
-			      / 100 / POW2(10000);
+	const int var_noise = POW2((uint64_t)rms_noise) * var_noise_factor *
+			      POW2(98) / 100 / POW2(10000);
 
-	var_threshold_scaled = (uint64_t)
-		(CONFIG_BODY_DETECTION_VAR_THRESHOLD + var_noise) *
-		multiplier / divisor;
-	confidence_delta_scaled = (uint64_t)
-		CONFIG_BODY_DETECTION_CONFIDENCE_DELTA *
-		multiplier / divisor;
+	var_threshold_scaled =
+		(uint64_t)(var_threshold + var_noise) * multiplier / divisor;
+	confidence_delta_scaled =
+		(uint64_t)confidence_delta * multiplier / divisor;
 }
 
 void body_detect_reset(void)
 {
 	int odr = body_sensor->drv->get_data_rate(body_sensor);
-	int range = body_sensor->drv->get_range(body_sensor);
-	int resolution = body_sensor->drv->get_resolution(body_sensor);
 	int rms_noise = body_sensor->drv->get_rms_noise(body_sensor);
+	int var_threshold, confidence_delta, var_noise_factor;
 
-	body_detect_change_state(BODY_DETECTION_ON_BODY);
+	if (motion_state == BODY_DETECTION_ON_BODY)
+		stationary_timeframe = 0;
+	else
+		body_detect_change_state(BODY_DETECTION_ON_BODY, false);
 	/*
 	 * The sensor is suspended since its ODR is 0,
 	 * there is no need to reset until sensor is up again
 	 */
 	if (odr == 0)
 		return;
+
+	/* If body detection params haven't been set, use the default ones. */
+	if (!body_sensor->bd_params)
+		body_sensor->bd_params = &default_body_detect_params;
+	/*
+	 * In case only some of the parameters have been specified use
+	 * the default values for the rest of them.
+	 */
+	if (body_sensor->bd_params->var_noise_factor != 0)
+		var_noise_factor = body_sensor->bd_params->var_noise_factor;
+	else
+		var_noise_factor = default_body_detect_params.var_noise_factor;
+
+	if (body_sensor->bd_params->var_threshold != 0)
+		var_threshold = body_sensor->bd_params->var_threshold;
+	else
+		var_threshold = default_body_detect_params.var_threshold;
+
+	if (body_sensor->bd_params->confidence_delta != 0)
+		confidence_delta = body_sensor->bd_params->confidence_delta;
+	else
+		confidence_delta = default_body_detect_params.confidence_delta;
+
 	determine_window_size(odr);
-	determine_threshold_scale(range, resolution, rms_noise);
+	determine_threshold_scale(body_sensor->current_range, rms_noise,
+				  var_noise_factor, var_threshold,
+				  confidence_delta);
 	/* initialize motion data and state */
 	memset(data, 0, sizeof(data));
 	history_idx = 0;
@@ -208,7 +257,7 @@ void body_detect(void)
 	switch (motion_state) {
 	case BODY_DETECTION_OFF_BODY:
 		if (motion_confidence > CONFIG_BODY_DETECTION_ON_BODY_CON)
-			body_detect_change_state(BODY_DETECTION_ON_BODY);
+			body_detect_change_state(BODY_DETECTION_ON_BODY, false);
 		break;
 	case BODY_DETECTION_ON_BODY:
 		stationary_timeframe += 1;
@@ -218,7 +267,8 @@ void body_detect(void)
 		/* if no motion for enough time, change state to off_body */
 		if (stationary_timeframe >=
 		    CONFIG_BODY_DETECTION_STATIONARY_DURATION * window_size)
-			body_detect_change_state(BODY_DETECTION_OFF_BODY);
+			body_detect_change_state(BODY_DETECTION_OFF_BODY,
+						 false);
 		break;
 	}
 }
@@ -226,10 +276,60 @@ void body_detect(void)
 void body_detect_set_enable(int enable)
 {
 	body_detect_enable = enable;
-	body_detect_change_state(BODY_DETECTION_ON_BODY);
+	body_detect_change_state(BODY_DETECTION_ON_BODY, false);
 }
 
 int body_detect_get_enable(void)
 {
 	return body_detect_enable;
 }
+
+#ifdef CONFIG_ACCEL_SPOOF_MODE
+void body_detect_set_spoof(int enable)
+{
+	spoof_enable = enable;
+	/* After disabling spoof mode, commit current state. */
+	if (!enable)
+		body_detect_change_state(motion_state, false);
+}
+
+bool body_detect_get_spoof(void)
+{
+	return spoof_enable;
+}
+
+static int command_setbodydetectionmode(int argc, const char **argv)
+{
+	if (argc == 1) {
+		print_body_detect_mode();
+		return EC_SUCCESS;
+	}
+
+	if (argc != 2)
+		return EC_ERROR_PARAM_COUNT;
+
+	/* |+1| to also make sure the strings the same length. */
+	if (strncmp(argv[1], "on", strlen("on") + 1) == 0) {
+		body_detect_change_state(BODY_DETECTION_ON_BODY, true);
+		spoof_enable = true;
+	} else if (strncmp(argv[1], "off", strlen("off") + 1) == 0) {
+		body_detect_change_state(BODY_DETECTION_OFF_BODY, true);
+		spoof_enable = true;
+	} else if (strncmp(argv[1], "reset", strlen("reset") + 1) == 0) {
+		body_detect_reset();
+		/*
+		 * Don't call body_detect_set_spoof(), since
+		 * body_detect_change_state() was already called by
+		 * body_detect_reset().
+		 */
+		spoof_enable = false;
+	} else {
+		return EC_ERROR_PARAM1;
+	}
+
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(
+	bodydetectmode, command_setbodydetectionmode, "[on | off | reset]",
+	"Manually force body detect mode to on (body), off (body) or reset.");
+#endif /* CONFIG_ACCEL_SPOOF_MODE */
diff --git a/common/btle_hci_controller.c b/common/btle_hci_controller.c
index cc5b872b19..605b67945b 100644
--- a/common/btle_hci_controller.c
+++ b/common/btle_hci_controller.c
@@ -1,18 +1,18 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include "btle_hci_int.h"
-#include "btle_hci2.h"
 #include "bluetooth_le_ll.h"
+#include "btle_hci2.h"
+#include "btle_hci_int.h"
 #include "console.h"
 
 #ifdef CONFIG_BLUETOOTH_HCI_DEBUG
 
 #define CPUTS(outstr) cputs(CC_BLUETOOTH_HCI, outstr)
-#define CPRINTS(format, args...) cprints(CC_BLUETOOTH_HCI, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_BLUETOOTH_HCI, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_BLUETOOTH_HCI, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_BLUETOOTH_HCI, format, ##args)
 
 #else /* CONFIG_BLUETOOTH_HCI_DEBUG */
 
@@ -27,7 +27,7 @@ static uint64_t hci_le_event_mask;
 
 #define MAX_MESSAGE 24
 
-#define STATUS  (return_params[0])
+#define STATUS (return_params[0])
 #define RPARAMS (&(return_params[1]))
 
 void hci_cmd(uint8_t *hciCmdbuf)
@@ -56,215 +56,184 @@ void hci_cmd(uint8_t *hciCmdbuf)
 	}
 
 	switch (hdr->opcode) {
-	case CMD_MAKE_OPCODE(HCI_OGF_Controller_and_Baseband,
-				HCI_CMD_Reset):
+	case CMD_MAKE_OPCODE(HCI_OGF_Controller_and_Baseband, HCI_CMD_Reset):
 		STATUS = ll_reset();
-	break;
+		break;
 	case CMD_MAKE_OPCODE(HCI_OGF_Controller_and_Baseband,
-				HCI_CMD_Set_Event_Mask):
+			     HCI_CMD_Set_Event_Mask):
 		if (hdr->paramLen != sizeof(hci_event_mask))
 			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
 		else
 			STATUS = HCI_SUCCESS;
 		memcpy(&hci_event_mask, params, sizeof(hci_event_mask));
-	break;
+		break;
 	case CMD_MAKE_OPCODE(HCI_OGF_Controller_and_Baseband,
-				HCI_CMD_Read_Transmit_Power_Level):
+			     HCI_CMD_Read_Transmit_Power_Level):
 	case CMD_MAKE_OPCODE(HCI_OGF_Informational,
-				HCI_CMD_Read_Local_Supported_Features):
+			     HCI_CMD_Read_Local_Supported_Features):
 	case CMD_MAKE_OPCODE(HCI_OGF_Informational,
-				HCI_CMD_Read_Local_Supported_Commands):
+			     HCI_CMD_Read_Local_Supported_Commands):
 	case CMD_MAKE_OPCODE(HCI_OGF_Informational,
-				HCI_CMD_Read_Local_Version_Information):
-	case CMD_MAKE_OPCODE(HCI_OGF_Informational,
-				HCI_CMD_Read_BD_ADDR):
+			     HCI_CMD_Read_Local_Version_Information):
+	case CMD_MAKE_OPCODE(HCI_OGF_Informational, HCI_CMD_Read_BD_ADDR):
 	case CMD_MAKE_OPCODE(HCI_OGF_Link_Control,
-				HCI_CMD_Read_Remote_Version_Information):
-	case CMD_MAKE_OPCODE(HCI_OGF_Status,
-				HCI_CMD_Read_RSSI):
+			     HCI_CMD_Read_Remote_Version_Information):
+	case CMD_MAKE_OPCODE(HCI_OGF_Status, HCI_CMD_Read_RSSI):
 		event = 0;
-	break;
+		break;
 
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Set_Event_Mask):
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Set_Event_Mask):
 		if (hdr->paramLen != sizeof(hci_le_event_mask))
 			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
 		else
 			STATUS = HCI_SUCCESS;
 		memcpy(&hci_le_event_mask, params, sizeof(hci_le_event_mask));
-	break;
+		break;
 
 	/* LE Information */
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Read_Buffer_Size):
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Read_Buffer_Size):
 		if (hdr->paramLen != 0)
 			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
 		else
 			STATUS = ll_read_buffer_size(RPARAMS);
 		rparam_count = sizeof(struct hciCmplLeReadBufferSize);
-	break;
+		break;
 	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Read_Local_Supported_Features):
+			     HCI_CMD_LE_Read_Local_Supported_Features):
 		if (hdr->paramLen != 0)
 			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
 		else
 			STATUS = ll_read_local_supported_features(RPARAMS);
 		rparam_count =
 			sizeof(struct hciCmplLeReadLocalSupportedFeatures);
-	break;
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Read_Supported_States):
+		break;
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Read_Supported_States):
 		if (hdr->paramLen != 0)
 			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
 		else
 			STATUS = ll_read_supported_states(RPARAMS);
 		rparam_count = sizeof(struct hciCmplLeReadSupportedStates);
-	break;
+		break;
 	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Set_Host_Channel_Classification):
+			     HCI_CMD_LE_Set_Host_Channel_Classification):
 		if (hdr->paramLen !=
 		    sizeof(struct hciLeSetHostChannelClassification))
 			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
 		else
 			STATUS = ll_set_host_channel_classification(params);
-	break;
+		break;
 
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Set_Random_Address):
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Set_Random_Address):
 		if (hdr->paramLen != sizeof(struct hciLeSetRandomAddress))
 			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
 		else
 			STATUS = ll_set_random_address(params);
-	break;
+		break;
 
 	/* Advertising */
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Set_Advertise_Enable):
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Set_Advertise_Enable):
 		STATUS = ll_set_advertising_enable(params);
-	break;
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Set_Advertising_Data):
+		break;
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Set_Advertising_Data):
 		STATUS = ll_set_adv_data(params);
-	break;
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Set_Adv_Params):
+		break;
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Set_Adv_Params):
 		if (hdr->paramLen != sizeof(struct hciLeSetAdvParams))
 			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
 		else
 			STATUS = ll_set_advertising_params(params);
-	break;
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Read_Adv_Channel_TX_Power):
+		break;
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Read_Adv_Channel_TX_Power):
 		STATUS = ll_read_tx_power();
 		rparam_count = sizeof(struct hciCmplLeReadAdvChannelTxPower);
-	break;
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Set_Scan_Response_Data):
+		break;
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Set_Scan_Response_Data):
 		STATUS = ll_set_scan_response_data(params);
-	break;
+		break;
 
 	/* Connections */
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Read_Remote_Used_Features):
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Read_Remote_Used_Features):
 		if (hdr->paramLen != sizeof(struct hciLeReadRemoteUsedFeatures))
 			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
 		else
 			STATUS = ll_read_remote_used_features(params);
 		event = HCI_EVT_Command_Status;
-	break;
-	case CMD_MAKE_OPCODE(HCI_OGF_Link_Control,
-				HCI_CMD_Disconnect):
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Connection_Update):
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Create_Connection):
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Create_Connection_Cancel):
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Read_Channel_Map):
+		break;
+	case CMD_MAKE_OPCODE(HCI_OGF_Link_Control, HCI_CMD_Disconnect):
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Connection_Update):
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Create_Connection):
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Create_Connection_Cancel):
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Read_Channel_Map):
 		event = 0;
-	break;
+		break;
 
 	/* Encryption */
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Encrypt):
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_LTK_Request_Reply):
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_LTK_Request_Negative_Reply):
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Rand):
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Start_Encryption):
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Encrypt):
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_LTK_Request_Reply):
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_LTK_Request_Negative_Reply):
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Rand):
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Start_Encryption):
 		event = 0;
-	break;
+		break;
 
 	/* Scanning */
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Set_Scan_Enable):
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Set_Scan_Enable):
 		if (hdr->paramLen != sizeof(struct hciLeSetScanEnable))
 			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
 		else
 			STATUS = ll_set_scan_enable(params);
-	break;
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Set_Scan_Parameters):
+		break;
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Set_Scan_Parameters):
 		if (hdr->paramLen != sizeof(struct hciLeSetScanParams))
 			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
 		else
 			STATUS = ll_set_scan_params(params);
-	break;
+		break;
 
 	/* Allow List */
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Clear_Allow_List):
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Clear_Allow_List):
 		if (hdr->paramLen != 0)
 			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
 		else
 			STATUS = ll_clear_allow_list();
-	break;
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Read_Allow_List_Size):
+		break;
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Read_Allow_List_Size):
 		if (hdr->paramLen != 0)
 			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
 		else
 			STATUS = ll_read_allow_list_size(RPARAMS);
 		rparam_count = sizeof(struct hciCmplLeReadAllowListSize);
-	break;
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Add_Device_To_Allow_List):
+		break;
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Add_Device_To_Allow_List):
 		if (hdr->paramLen != sizeof(struct hciLeAddDeviceToAllowList))
 			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
 		else
 			STATUS = ll_add_device_to_allow_list(params);
-	break;
+		break;
 	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Remove_Device_From_Allow_List):
+			     HCI_CMD_LE_Remove_Device_From_Allow_List):
 		if (hdr->paramLen !=
-				sizeof(struct hciLeRemoveDeviceFromAllowList))
+		    sizeof(struct hciLeRemoveDeviceFromAllowList))
 			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
 		else
 			STATUS = ll_remove_device_from_allow_list(params);
-	break;
+		break;
 
 	/* RFPHY Testing Support */
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Receiver_Test):
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Receiver_Test):
 		STATUS = ll_receiver_test(params);
-	break;
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Transmitter_Test):
+		break;
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Transmitter_Test):
 		STATUS = ll_transmitter_test(params);
-	break;
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Test_End):
+		break;
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Test_End):
 		STATUS = ll_test_end(RPARAMS);
 		rparam_count = sizeof(struct hciCmplLeTestEnd);
-	break;
+		break;
 
 	default:
 		STATUS = HCI_ERR_Unknown_HCI_Command;
-	break;
+		break;
 	}
 
 	hci_event(event, rparam_count, return_params);
@@ -275,12 +244,11 @@ void hci_acl_to_host(uint8_t *data, uint16_t hdr, uint16_t len)
 	int i;
 
 	/* Enqueue hdr, len, len bytes of data */
-	CPRINTF("Sending %d bytes of data from handle %d with PB=%x.\n",
-		len, hdr & ACL_HDR_MASK_CONN_ID,
-		hdr & ACL_HDR_MASK_PB);
-		for (i = 0; i < len; i++)
-			CPRINTF("0x%x, ", data[i]);
-		CPRINTF("\n");
+	CPRINTF("Sending %d bytes of data from handle %d with PB=%x.\n", len,
+		hdr & ACL_HDR_MASK_CONN_ID, hdr & ACL_HDR_MASK_PB);
+	for (i = 0; i < len; i++)
+		CPRINTF("0x%x, ", data[i]);
+	CPRINTF("\n");
 }
 
 void hci_acl_from_host(uint8_t *hciAclbuf)
@@ -290,12 +258,11 @@ void hci_acl_from_host(uint8_t *hciAclbuf)
 	int i;
 
 	/* Send the data to the link layer */
-	CPRINTF("Sending %d bytes of data to handle %d with PB=%x.\n",
-		hdr->len, hdr->hdr & ACL_HDR_MASK_CONN_ID,
-		hdr->hdr & ACL_HDR_MASK_PB);
-		for (i = 0; i < hdr->len; i++)
-			CPRINTF("0x%x, ", data[i]);
-		CPRINTF("\n");
+	CPRINTF("Sending %d bytes of data to handle %d with PB=%x.\n", hdr->len,
+		hdr->hdr & ACL_HDR_MASK_CONN_ID, hdr->hdr & ACL_HDR_MASK_PB);
+	for (i = 0; i < hdr->len; i++)
+		CPRINTF("0x%x, ", data[i]);
+	CPRINTF("\n");
 }
 
 /*
@@ -335,52 +302,50 @@ void hci_event(uint8_t event_code, uint8_t len, uint8_t *params)
  * hcitool lcmd 0x2008 18 0x42410906 0x03454443 0x203c119 0x3030501 0x1812
  * hcitool cmd 8 8 6 9 41 42 43 44 45 3 19 c1 3 2 1 5 3 3 12 18
  */
-uint8_t adv0[19] = {0x07, 0x09, 'A', 'B', 'C', 'D', 'E', 'F', /* Name */
-		    0x03, 0x19, 0xc1, 0x03,                   /* Keyboard */
-		    0x02, 0x01, 0x05,                         /* Flags */
-		    0x03, 0x03, 0x12, 0x18};                  /* UUID */
+uint8_t adv0[19] = { 0x07, 0x09, 'A',  'B',  'C', 'D', 'E', 'F', /* Name */
+		     0x03, 0x19, 0xc1, 0x03, /* Keyboard */
+		     0x02, 0x01, 0x05, /* Flags */
+		     0x03, 0x03, 0x12, 0x18 }; /* UUID */
 
-uint8_t adv1[18] = {0x06, 0x09, 'A', 'B', 'C', 'D', 'E',      /* Name */
-		    0x02, 0x01, 0x05,                         /* Flags */
-		    0x03, 0x19, 0xc1, 0x03,                   /* Keyboard */
-		    0x03, 0x03, 0x12, 0x18};                  /* UUID */
+uint8_t adv1[18] = { 0x06, 0x09, 'A',  'B',  'C', 'D', 'E', /* Name */
+		     0x02, 0x01, 0x05, /* Flags */
+		     0x03, 0x19, 0xc1, 0x03, /* Keyboard */
+		     0x03, 0x03, 0x12, 0x18 }; /* UUID */
 
-uint8_t *adverts[] = {adv0, adv1};
-uint8_t adv_lengths[] = {sizeof(adv0), sizeof(adv1)};
+uint8_t *adverts[] = { adv0, adv1 };
+uint8_t adv_lengths[] = { sizeof(adv0), sizeof(adv1) };
 
-uint8_t scan0[4] = {0x03, 0x08, 'A', 'B'}; /* Short Name */
+uint8_t scan0[4] = { 0x03, 0x08, 'A', 'B' }; /* Short Name */
 
-uint8_t scan1[] = {};                         /* Empty */
+uint8_t scan1[] = {}; /* Empty */
 
-uint8_t *scans[] = {scan0, scan1};
-uint8_t scan_lengths[] = {sizeof(scan0), sizeof(scan1)};
+uint8_t *scans[] = { scan0, scan1 };
+uint8_t scan_lengths[] = { sizeof(scan0), sizeof(scan1) };
 
 /*
  * LE_Set_Adv_Params
  * hcitool lcmd 0x2006 15 0x010000f0 0xb0010100 0xb4b3b2b1 0x0007c5
  * hcitool cmd 8 6 f0 0 0 1 0 1 1 b0 b1 b2 b3 b4 c5 7 0
  */
-uint8_t adv_param0[15] = {
-		0xf0, 0x00,                               /* IntervalMin */
-		0x00, 0x01,                               /* IntervalMax */
-		0x00,                                     /* Adv Type */
-		0x01,                                     /* Use Random Addr */
-		0x01,                                     /* Direct Random */
-		0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xc5,       /* Direct Addr */
-		0x07,                                     /* Channel Map */
-		0x00};                                    /* Filter Policy */
-
-uint8_t adv_param1[15] = {
-		0xf0, 0x00,                               /* IntervalMin */
-		0x00, 0x01,                               /* IntervalMax */
-		0x02,                                     /* Adv Type */
-		0x01,                                     /* Use Random Addr */
-		0x01,                                     /* Direct Random */
-		0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xc5,       /* Direct Addr */
-		0x07,                                     /* Channel Map */
-		0x00};                                    /* Filter Policy */
-
-uint8_t *adv_params[] = {adv_param0, adv_param1};
+uint8_t adv_param0[15] = { 0xf0, 0x00, /* IntervalMin */
+			   0x00, 0x01, /* IntervalMax */
+			   0x00, /* Adv Type */
+			   0x01, /* Use Random Addr */
+			   0x01, /* Direct Random */
+			   0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xc5, /* Direct Addr */
+			   0x07, /* Channel Map */
+			   0x00 }; /* Filter Policy */
+
+uint8_t adv_param1[15] = { 0xf0, 0x00, /* IntervalMin */
+			   0x00, 0x01, /* IntervalMax */
+			   0x02, /* Adv Type */
+			   0x01, /* Use Random Addr */
+			   0x01, /* Direct Random */
+			   0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xc5, /* Direct Addr */
+			   0x07, /* Channel Map */
+			   0x00 }; /* Filter Policy */
+
+uint8_t *adv_params[] = { adv_param0, adv_param1 };
 
 /*
  * LE Information
@@ -466,7 +431,7 @@ static uint8_t hci_buf[200];
 #define MAX_BLE_HCI_PARAMS 8
 static uint32_t param[MAX_BLE_HCI_PARAMS];
 
-static int command_ble_hci_cmd(int argc, char **argv)
+static int command_ble_hci_cmd(int argc, const char **argv)
 {
 	static struct hciCmdHdr header;
 	int length, opcode, i;
@@ -489,7 +454,7 @@ static int command_ble_hci_cmd(int argc, char **argv)
 	}
 
 	for (i = 3; i < argc; i++) {
-		param[i-3] = strtoi(argv[i], &e, 0);
+		param[i - 3] = strtoi(argv[i], &e, 0);
 		if (*e)
 			return EC_ERROR_PARAM3 + i;
 	}
@@ -498,12 +463,11 @@ static int command_ble_hci_cmd(int argc, char **argv)
 	header.paramLen = length;
 
 	memcpy(hci_buf, &header, sizeof(struct hciCmdHdr));
-	memcpy(hci_buf + sizeof(struct hciCmdHdr),
-			param, length);
+	memcpy(hci_buf + sizeof(struct hciCmdHdr), param, length);
 
 	hci_cmd(hci_buf);
 
-	CPRINTS("hci cmd @%pP", hci_buf);
+	CPRINTS("hci cmd @%p", hci_buf);
 
 	return EC_SUCCESS;
 }
@@ -511,7 +475,7 @@ DECLARE_CONSOLE_COMMAND(ble_hci_cmd, command_ble_hci_cmd,
 			"opcode len uint32 uint32 uint32... (little endian)",
 			"Send an hci command of length len");
 
-static int command_hcitool(int argc, char **argv)
+static int command_hcitool(int argc, const char **argv)
 {
 	static struct hciCmdHdr header;
 	int i, ogf, ocf;
@@ -521,7 +485,7 @@ static int command_hcitool(int argc, char **argv)
 		return EC_ERROR_PARAM_COUNT;
 
 	if (argv[1][0] == 'l') /* strcmp lcmd */
-		return command_ble_hci_cmd(argc-1, &argv[1]);
+		return command_ble_hci_cmd(argc - 1, &argv[1]);
 
 	ogf = strtoi(argv[2], &e, 16);
 	if (*e)
@@ -532,7 +496,7 @@ static int command_hcitool(int argc, char **argv)
 		return EC_ERROR_PARAM3;
 
 	header.opcode = CMD_MAKE_OPCODE(ogf, ocf);
-	header.paramLen = argc-4;
+	header.paramLen = argc - 4;
 	memcpy(hci_buf, &header, sizeof(struct hciCmdHdr));
 
 	for (i = 4; i < argc; i++) {
@@ -543,15 +507,16 @@ static int command_hcitool(int argc, char **argv)
 
 	hci_cmd(hci_buf);
 
-	CPRINTS("hci cmd @%pP", hci_buf);
+	CPRINTS("hci cmd @%p", hci_buf);
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(hcitool, command_hcitool,
-			"cmd ogf ocf b0 b1 b2 b3... or lcmd opcode len uint32.. (little endian)",
-			"Send an hci command of length len");
+DECLARE_CONSOLE_COMMAND(
+	hcitool, command_hcitool,
+	"cmd ogf ocf b0 b1 b2 b3... or lcmd opcode len uint32.. (little endian)",
+	"Send an hci command of length len");
 
-static int command_ble_hci_acl(int argc, char **argv)
+static int command_ble_hci_acl(int argc, const char **argv)
 {
 	static struct hciAclHdr header;
 	int length, hdr, i;
@@ -574,7 +539,7 @@ static int command_ble_hci_acl(int argc, char **argv)
 	}
 
 	for (i = 3; i < argc; i++) {
-		param[i-3] = strtoi(argv[i], &e, 0);
+		param[i - 3] = strtoi(argv[i], &e, 0);
 		if (*e)
 			return EC_ERROR_PARAM3 + i;
 	}
@@ -583,12 +548,11 @@ static int command_ble_hci_acl(int argc, char **argv)
 	header.len = length;
 
 	memcpy(hci_buf, &header, sizeof(struct hciCmdHdr));
-	memcpy(hci_buf + sizeof(struct hciCmdHdr),
-			param, length);
+	memcpy(hci_buf + sizeof(struct hciCmdHdr), param, length);
 
 	hci_cmd(hci_buf);
 
-	CPRINTS("hci acl @%pP", hci_buf);
+	CPRINTS("hci acl @%p", hci_buf);
 
 	return EC_SUCCESS;
 }
@@ -596,7 +560,7 @@ DECLARE_CONSOLE_COMMAND(ble_hci_acl, command_ble_hci_acl,
 			"hdr len uint32 uint32 uint32... (little endian)",
 			"Send hci acl data of length len");
 
-static int command_ble_hci_adv(int argc, char **argv)
+static int command_ble_hci_adv(int argc, const char **argv)
 {
 	static struct hciCmdHdr header;
 	int adv, p = 0, scan_rsp = 0;
@@ -625,33 +589,33 @@ static int command_ble_hci_adv(int argc, char **argv)
 	header.paramLen = sizeof(struct hciLeSetAdvParams);
 
 	memcpy(hci_buf, &header, sizeof(struct hciCmdHdr));
-	memcpy(hci_buf + sizeof(struct hciCmdHdr),
-			adv_params[p], header.paramLen);
+	memcpy(hci_buf + sizeof(struct hciCmdHdr), adv_params[p],
+	       header.paramLen);
 
 	hci_cmd(hci_buf);
 
-	header.opcode = CMD_MAKE_OPCODE(HCI_OGF_LE,
-					HCI_CMD_LE_Set_Advertising_Data);
+	header.opcode =
+		CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Set_Advertising_Data);
 	header.paramLen = adv_lengths[adv];
 
 	memcpy(hci_buf, &header, sizeof(struct hciCmdHdr));
-	memcpy(hci_buf + sizeof(struct hciCmdHdr),
-			adverts[adv], header.paramLen);
+	memcpy(hci_buf + sizeof(struct hciCmdHdr), adverts[adv],
+	       header.paramLen);
 
 	hci_cmd(hci_buf);
 
-	header.opcode = CMD_MAKE_OPCODE(HCI_OGF_LE,
-					HCI_CMD_LE_Set_Scan_Response_Data);
+	header.opcode =
+		CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Set_Scan_Response_Data);
 	header.paramLen = scan_lengths[scan_rsp];
 
 	memcpy(hci_buf, &header, sizeof(struct hciCmdHdr));
-	memcpy(hci_buf + sizeof(struct hciCmdHdr),
-			scans[scan_rsp], header.paramLen);
+	memcpy(hci_buf + sizeof(struct hciCmdHdr), scans[scan_rsp],
+	       header.paramLen);
 
 	hci_cmd(hci_buf);
 
-	header.opcode = CMD_MAKE_OPCODE(HCI_OGF_LE,
-					HCI_CMD_LE_Set_Advertise_Enable);
+	header.opcode =
+		CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Set_Advertise_Enable);
 	header.paramLen = sizeof(struct hciLeSetAdvEnable);
 
 	memcpy(hci_buf, &header, sizeof(struct hciCmdHdr));
diff --git a/common/btle_ll.c b/common/btle_ll.c
index b2a15ce36e..eea9534fe3 100644
--- a/common/btle_ll.c
+++ b/common/btle_ll.c
@@ -1,23 +1,23 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include "bluetooth_le_ll.h"
 #include "bluetooth_le.h"
+#include "bluetooth_le_ll.h"
 #include "btle_hci_int.h"
-#include "util.h"
 #include "console.h"
 #include "radio.h"
 #include "radio_test.h"
 #include "task.h"
 #include "timer.h"
+#include "util.h"
 
 #ifdef CONFIG_BLUETOOTH_LL_DEBUG
 
 #define CPUTS(outstr) cputs(CC_BLUETOOTH_LL, outstr)
-#define CPRINTS(format, args...) cprints(CC_BLUETOOTH_LL, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_BLUETOOTH_LL, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_BLUETOOTH_LL, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_BLUETOOTH_LL, format, ##args)
 
 #else /* CONFIG_BLUETOOTH_LL_DEBUG */
 
@@ -57,7 +57,7 @@ uint8_t is_first_data_packet;
 
 static uint64_t ll_random_address = 0xC5BADBADBAD1; /* Uninitialized */
 static uint64_t ll_public_address = 0xC5BADBADBADF; /* Uninitialized */
-static uint8_t ll_channel_map[5] = {0xff, 0xff, 0xff, 0xff, 0x1f};
+static uint8_t ll_channel_map[5] = { 0xff, 0xff, 0xff, 0xff, 0x1f };
 
 static uint8_t ll_filter_duplicates;
 
@@ -161,8 +161,8 @@ static uint8_t ll_state_change_request(enum ll_state_t next_state)
 {
 	/* Initialize the radio if it hasn't been initialized */
 	if (ll_state == UNINITIALIZED) {
-		if (ble_radio_init(BLE_ADV_ACCESS_ADDRESS, BLE_ADV_CRCINIT)
-				!= EC_SUCCESS)
+		if (ble_radio_init(BLE_ADV_ACCESS_ADDRESS, BLE_ADV_CRCINIT) !=
+		    EC_SUCCESS)
 			return HCI_ERR_Hardware_Failure;
 		ll_state = STANDBY;
 	}
@@ -236,50 +236,50 @@ uint8_t initialize_connection(void)
 	num_consecutive_failures = 0;
 
 	/* Copy data into the appropriate portions of memory */
-	memcpy((uint8_t *)&(conn_params.init_a),
-			payload_start, CONNECT_REQ_INITA_LEN);
+	memcpy((uint8_t *)&(conn_params.init_a), payload_start,
+	       CONNECT_REQ_INITA_LEN);
 	cur_offset += CONNECT_REQ_INITA_LEN;
 
-	memcpy((uint8_t *)&(conn_params.adv_a),
-			payload_start+cur_offset, CONNECT_REQ_ADVA_LEN);
+	memcpy((uint8_t *)&(conn_params.adv_a), payload_start + cur_offset,
+	       CONNECT_REQ_ADVA_LEN);
 	cur_offset += CONNECT_REQ_ADVA_LEN;
 
-	memcpy(&(conn_params.access_addr),
-			payload_start+cur_offset, CONNECT_REQ_ACCESS_ADDR_LEN);
+	memcpy(&(conn_params.access_addr), payload_start + cur_offset,
+	       CONNECT_REQ_ACCESS_ADDR_LEN);
 	cur_offset += CONNECT_REQ_ACCESS_ADDR_LEN;
 
 	conn_params.crc_init_val = 0;
-	memcpy(&(conn_params.crc_init_val),
-			payload_start+cur_offset, CONNECT_REQ_CRC_INIT_VAL_LEN);
+	memcpy(&(conn_params.crc_init_val), payload_start + cur_offset,
+	       CONNECT_REQ_CRC_INIT_VAL_LEN);
 	cur_offset += CONNECT_REQ_CRC_INIT_VAL_LEN;
 
-	memcpy(&(conn_params.win_size),
-			payload_start+cur_offset, CONNECT_REQ_WIN_SIZE_LEN);
+	memcpy(&(conn_params.win_size), payload_start + cur_offset,
+	       CONNECT_REQ_WIN_SIZE_LEN);
 	cur_offset += CONNECT_REQ_WIN_SIZE_LEN;
 
-	memcpy(&(conn_params.win_offset),
-			payload_start+cur_offset, CONNECT_REQ_WIN_OFFSET_LEN);
+	memcpy(&(conn_params.win_offset), payload_start + cur_offset,
+	       CONNECT_REQ_WIN_OFFSET_LEN);
 	cur_offset += CONNECT_REQ_WIN_OFFSET_LEN;
 
-	memcpy(&(conn_params.interval),
-			payload_start+cur_offset, CONNECT_REQ_INTERVAL_LEN);
+	memcpy(&(conn_params.interval), payload_start + cur_offset,
+	       CONNECT_REQ_INTERVAL_LEN);
 	cur_offset += CONNECT_REQ_INTERVAL_LEN;
 
-	memcpy(&(conn_params.latency),
-			payload_start+cur_offset, CONNECT_REQ_LATENCY_LEN);
+	memcpy(&(conn_params.latency), payload_start + cur_offset,
+	       CONNECT_REQ_LATENCY_LEN);
 	cur_offset += CONNECT_REQ_LATENCY_LEN;
 
-	memcpy(&(conn_params.timeout),
-			payload_start+cur_offset, CONNECT_REQ_TIMEOUT_LEN);
+	memcpy(&(conn_params.timeout), payload_start + cur_offset,
+	       CONNECT_REQ_TIMEOUT_LEN);
 	cur_offset += CONNECT_REQ_TIMEOUT_LEN;
 
 	conn_params.channel_map = 0;
-	memcpy(&(conn_params.channel_map),
-			payload_start+cur_offset, CONNECT_REQ_CHANNEL_MAP_LEN);
+	memcpy(&(conn_params.channel_map), payload_start + cur_offset,
+	       CONNECT_REQ_CHANNEL_MAP_LEN);
 	cur_offset += CONNECT_REQ_CHANNEL_MAP_LEN;
 
-	memcpy(&final_octet, payload_start+cur_offset,
-			CONNECT_REQ_HOP_INCREMENT_AND_SCA_LEN);
+	memcpy(&final_octet, payload_start + cur_offset,
+	       CONNECT_REQ_HOP_INCREMENT_AND_SCA_LEN);
 
 	/* last  5 bits of final_octet: */
 	conn_params.hop_increment = final_octet & 0x1f;
@@ -288,16 +288,16 @@ uint8_t initialize_connection(void)
 
 	/* Set up channel mapping table */
 	for (i = 0; i < 5; ++i)
-		remap_arr[i] = *(((uint8_t *)&(conn_params.channel_map))+i);
+		remap_arr[i] = *(((uint8_t *)&(conn_params.channel_map)) + i);
 	fill_remapping_table(&remap_table, remap_arr,
-		conn_params.hop_increment);
+			     conn_params.hop_increment);
 
 	/* Calculate transmission window parameters */
 	conn_params.transmitWindowSize = conn_params.win_size * 1250;
 	conn_params.transmitWindowOffset = conn_params.win_offset * 1250;
 	conn_params.connInterval = conn_params.interval * 1250;
 	/* The following two lines convert ms -> microseconds */
-	conn_params.connSlaveLatency = 1000 * conn_params.latency;
+	conn_params.connLatency = 1000 * conn_params.latency;
 	conn_params.connSupervisionTimeout = 10000 * conn_params.timeout;
 	/* All these times are in microseconds! */
 
@@ -332,7 +332,7 @@ uint8_t ll_read_allow_list_size(uint8_t *return_params)
 uint8_t ll_add_device_to_allow_list(uint8_t *params)
 {
 	if (ble_radio_add_device_to_allow_list(&params[1], params[0]) ==
-			EC_SUCCESS)
+	    EC_SUCCESS)
 		return HCI_SUCCESS;
 	else
 		return HCI_ERR_Host_Rejected_Due_To_Limited_Resources;
@@ -341,7 +341,7 @@ uint8_t ll_add_device_to_allow_list(uint8_t *params)
 uint8_t ll_remove_device_from_allow_list(uint8_t *params)
 {
 	if (ble_radio_remove_device_from_allow_list(&params[1], params[0]) ==
-			EC_SUCCESS)
+	    EC_SUCCESS)
 		return HCI_SUCCESS;
 	else
 		return HCI_ERR_Hardware_Failure;
@@ -449,27 +449,28 @@ uint8_t ll_set_advertising_params(uint8_t *params)
 	case BLE_ADV_HEADER_PDU_TYPE_ADV_NONCONN_IND:
 	case BLE_ADV_HEADER_PDU_TYPE_ADV_SCAN_IND:
 		if (ll_adv_params.advIntervalMin <
-		    (100000 / LL_ADV_INTERVAL_UNIT_US))    /* 100ms */
+		    (100000 / LL_ADV_INTERVAL_UNIT_US)) /* 100ms */
 			return HCI_ERR_Invalid_HCI_Command_Parameters;
 	/* Fall through */
 	case BLE_ADV_HEADER_PDU_TYPE_ADV_IND:
 		if (ll_adv_params.advIntervalMin > ll_adv_params.advIntervalMax)
 			return HCI_ERR_Invalid_HCI_Command_Parameters;
 		if (ll_adv_params.advIntervalMin <
-		    (20000 / LL_ADV_INTERVAL_UNIT_US) ||   /* 20ms */
+			    (20000 / LL_ADV_INTERVAL_UNIT_US) || /* 20ms */
 		    ll_adv_params.advIntervalMax >
-		    (10240000 / LL_ADV_INTERVAL_UNIT_US))  /* 10.24s */
+			    (10240000 / LL_ADV_INTERVAL_UNIT_US)) /* 10.24s */
 			return HCI_ERR_Invalid_HCI_Command_Parameters;
 		ll_adv_interval_us = (((ll_adv_params.advIntervalMin +
-					ll_adv_params.advIntervalMax) / 2) *
-					LL_ADV_INTERVAL_UNIT_US);
+					ll_adv_params.advIntervalMax) /
+				       2) *
+				      LL_ADV_INTERVAL_UNIT_US);
 		/* Don't time out */
 		ll_adv_timeout_us = -1;
-	break;
+		break;
 	case BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND:
 		ll_adv_interval_us = LL_ADV_DIRECT_INTERVAL_US;
 		ll_adv_timeout_us = LL_ADV_DIRECT_TIMEOUT_US;
-	break;
+		break;
 	default:
 		return HCI_ERR_Invalid_HCI_Command_Parameters;
 	}
@@ -563,25 +564,25 @@ int ble_ll_adv(int chan)
 	case BLE_ADV_HEADER_PDU_TYPE_SCAN_REQ:
 		/* Scan requests are only allowed for ADV_IND and SCAN_IND */
 		if ((ll_adv_pdu.header.adv.type !=
-		     BLE_ADV_HEADER_PDU_TYPE_ADV_IND &&
+			     BLE_ADV_HEADER_PDU_TYPE_ADV_IND &&
 		     ll_adv_pdu.header.adv.type !=
-		     BLE_ADV_HEADER_PDU_TYPE_ADV_SCAN_IND) ||
-			/* The advertising address needs to match */
+			     BLE_ADV_HEADER_PDU_TYPE_ADV_SCAN_IND) ||
+		    /* The advertising address needs to match */
 		    (memcmp(&ll_rcv_packet.payload[BLUETOOTH_ADDR_OCTETS],
 			    &ll_adv_pdu.payload[0], BLUETOOTH_ADDR_OCTETS))) {
 			/* Don't send the scan response */
 			radio_disable();
 			return rv;
 		}
-	break;
+		break;
 	case BLE_ADV_HEADER_PDU_TYPE_CONNECT_REQ:
 		/* Don't send a scan response */
 		radio_disable();
 		/* Connecting is only allowed for ADV_IND and ADV_DIRECT_IND */
 		if (ll_adv_pdu.header.adv.type !=
-			BLE_ADV_HEADER_PDU_TYPE_ADV_IND &&
+			    BLE_ADV_HEADER_PDU_TYPE_ADV_IND &&
 		    ll_adv_pdu.header.adv.type !=
-			BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND)
+			    BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND)
 			return rv;
 		/* The advertising address needs to match */
 		if (memcmp(&ll_rcv_packet.payload[BLUETOOTH_ADDR_OCTETS],
@@ -589,9 +590,9 @@ int ble_ll_adv(int chan)
 			return rv;
 		/* The InitAddr address needs to match for ADV_DIRECT_IND */
 		if (ll_adv_pdu.header.adv.type ==
-			BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND &&
-			memcmp(&ll_adv_pdu.payload[BLUETOOTH_ADDR_OCTETS],
-			&ll_rcv_packet.payload[0], BLUETOOTH_ADDR_OCTETS))
+			    BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND &&
+		    memcmp(&ll_adv_pdu.payload[BLUETOOTH_ADDR_OCTETS],
+			   &ll_rcv_packet.payload[0], BLUETOOTH_ADDR_OCTETS))
 			return rv;
 
 		/* Mark time that connect was received */
@@ -604,11 +605,11 @@ int ble_ll_adv(int chan)
 		ll_state = CONNECTION;
 
 		return rv;
-	break;
+		break;
 	default: /* Unhandled response packet */
 		radio_disable();
 		return rv;
-	break;
+		break;
 	}
 
 	CPRINTF("ADV %u Response %u %u\n", tx_end, rsp_end, tx_rsp_end);
@@ -632,7 +633,6 @@ int ble_ll_adv_event(void)
 	return rv;
 }
 
-
 void print_connection_state(void)
 {
 	CPRINTF("vvvvvvvvvvvvvvvvvvvCONNECTION STATEvvvvvvvvvvvvvvvvvvv\n");
@@ -663,29 +663,29 @@ int connected_communicate(void)
 
 	if (num_consecutive_failures > 0) {
 		ble_radio_init(conn_params.access_addr,
-			conn_params.crc_init_val);
+			       conn_params.crc_init_val);
 		NRF51_RADIO_FREQUENCY =
 			NRF51_RADIO_FREQUENCY_VAL(chan2freq(comm_channel));
 		NRF51_RADIO_DATAWHITEIV = comm_channel;
-		listen_time = last_receive_time + conn_params.connInterval
-			- get_time().val + conn_params.transmitWindowSize;
+		listen_time = last_receive_time + conn_params.connInterval -
+			      get_time().val + conn_params.transmitWindowSize;
 
 		/*
 		 * This listens for 1.25 times the expected amount
 		 * of time. This is a margin of error. This line is
 		 * only called when a connection has failed (a missed
-		 * packet). The slave and the master could have
+		 * packet). The peripheral and the controller could have
 		 * missed this packet due to a disagreement on when
 		 * the packet should have arrived. We listen for
 		 * slightly longer than expected in the case that
 		 * there was a timing disagreement.
 		 */
-		rv = ble_rx(&ll_rcv_packet,
-			listen_time + (listen_time >> 2), 0);
+		rv = ble_rx(&ll_rcv_packet, listen_time + (listen_time >> 2),
+			    0);
 	} else {
 		if (!is_first_data_packet) {
-			sleep_time = receive_time +
-				conn_params.connInterval - get_time().val;
+			sleep_time = receive_time + conn_params.connInterval -
+				     get_time().val;
 			/*
 			 * The time slept is 31/32 (96.875%) of the calculated
 			 * required sleep time because the code to receive
@@ -695,8 +695,8 @@ int connected_communicate(void)
 		} else {
 			last_receive_time = time_of_connect_req;
 			sleep_time = TRANSMIT_WINDOW_OFFSET_CONSTANT +
-					conn_params.transmitWindowOffset +
-					time_of_connect_req - get_time().val;
+				     conn_params.transmitWindowOffset +
+				     time_of_connect_req - get_time().val;
 			if (sleep_time >= 0) {
 				/*
 				 * Radio is on for longer than needed for first
@@ -709,7 +709,7 @@ int connected_communicate(void)
 		}
 
 		ble_radio_init(conn_params.access_addr,
-			conn_params.crc_init_val);
+			       conn_params.crc_init_val);
 		NRF51_RADIO_FREQUENCY =
 			NRF51_RADIO_FREQUENCY_VAL(chan2freq(comm_channel));
 		NRF51_RADIO_DATAWHITEIV = comm_channel;
@@ -722,14 +722,13 @@ int connected_communicate(void)
 		 * how early the window opens in microseconds.
 		 */
 		if (!is_first_data_packet)
-			offset = last_receive_time + conn_params.connInterval
-				- get_time().val;
+			offset = last_receive_time + conn_params.connInterval -
+				 get_time().val;
 		else
 			offset = 0;
 
 		rv = ble_rx(&ll_rcv_packet,
-			    offset + conn_params.transmitWindowSize,
-			    0);
+			    offset + conn_params.transmitWindowSize, 0);
 	}
 
 	/*
@@ -766,9 +765,9 @@ void bluetooth_ll_task(void)
 		case ADVERTISING:
 
 			if (deadline.val == 0) {
-				CPRINTS("ADV @%pP", &ll_adv_pdu);
+				CPRINTS("ADV @%p", &ll_adv_pdu);
 				deadline.val = get_time().val +
-					(uint32_t)ll_adv_timeout_us;
+					       (uint32_t)ll_adv_timeout_us;
 				ll_adv_events = 0;
 			}
 
@@ -786,7 +785,7 @@ void bluetooth_ll_task(void)
 				ll_state = STANDBY;
 				break;
 			}
-		break;
+			break;
 		case STANDBY:
 			deadline.val = 0;
 			CPRINTS("Standby %d events", ll_adv_events);
@@ -795,20 +794,20 @@ void bluetooth_ll_task(void)
 			task_wait_event(-1);
 			connection_initialized = 0;
 			errors_recovered = 0;
-		break;
+			break;
 		case TEST_RX:
 			if (ble_test_rx() == HCI_SUCCESS)
 				ll_test_packets++;
 			/* Packets come every 625us, sleep to save power */
 			usleep(300);
-		break;
+			break;
 		case TEST_TX:
 			start = get_time().le.lo;
 			ble_test_tx();
 			ll_test_packets++;
 			end = get_time().le.lo;
-			usleep(625 - 82 - (end-start)); /* 625us */
-		break;
+			usleep(625 - 82 - (end - start)); /* 625us */
+			break;
 		case UNINITIALIZED:
 			ble_radio_init(BLE_ADV_ACCESS_ADDRESS, BLE_ADV_CRCINIT);
 			ll_adv_events = 0;
@@ -816,7 +815,7 @@ void bluetooth_ll_task(void)
 			connection_initialized = 0;
 			packet_tb_sent = &tx_packet_1;
 			set_empty_data_packet(&tx_packet_1);
-		break;
+			break;
 		case CONNECTION:
 			if (!connection_initialized) {
 				if (initialize_connection() != HCI_SUCCESS) {
@@ -835,8 +834,7 @@ void bluetooth_ll_task(void)
 			} else {
 				num_consecutive_failures++;
 				if ((get_time().val - last_rx_time) >
-					conn_params.connSupervisionTimeout) {
-
+				    conn_params.connSupervisionTimeout) {
 					ll_state = STANDBY;
 					CPRINTF("EXITING CONNECTION STATE "
 						"DUE TO TIMEOUT.\n");
@@ -847,10 +845,11 @@ void bluetooth_ll_task(void)
 			if (ll_state == STANDBY) {
 				CPRINTF("Exiting connection state/Entering "
 					"Standby state after %d connections "
-					"events\n", ll_conn_events);
+					"events\n",
+					ll_conn_events);
 				print_connection_state();
 			}
-		break;
+			break;
 		default:
 			CPRINTS("Unhandled State ll_state = %d", ll_state);
 			ll_state = UNINITIALIZED;
@@ -858,4 +857,3 @@ void bluetooth_ll_task(void)
 		}
 	}
 }
-
diff --git a/common/build.mk b/common/build.mk
index ebaa3cc582..1a61295085 100644
--- a/common/build.mk
+++ b/common/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
+# Copyright 2014 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -10,25 +10,29 @@
 _common_dir:=$(dir $(lastword $(MAKEFILE_LIST)))
 
 common-y=util.o
-common-y+=version.o printf.o queue.o queue_policies.o
+common-y+=version.o printf.o queue.o queue_policies.o irq_locking.o
+common-y+=gettimeofday.o
 
 common-$(CONFIG_ACCELGYRO_BMI160)+=math_util.o
+common-$(CONFIG_ACCELGYRO_BMI220)+=math_util.o
 common-$(CONFIG_ACCELGYRO_BMI260)+=math_util.o
+common-$(CONFIG_ACCELGYRO_BMI3XX)+=math_util.o
 common-$(CONFIG_ACCELGYRO_ICM426XX)+=math_util.o
+common-$(CONFIG_ACCELGYRO_ICM42607)+=math_util.o
 common-$(CONFIG_ACCELGYRO_LSM6DS0)+=math_util.o
 common-$(CONFIG_ACCELGYRO_LSM6DSM)+=math_util.o
 common-$(CONFIG_ACCELGYRO_LSM6DSO)+=math_util.o
 common-$(CONFIG_ACCEL_FIFO)+=motion_sense_fifo.o
 common-$(CONFIG_ACCEL_BMA255)+=math_util.o
+common-$(CONFIG_ACCEL_BMA4XX)+=math_util.o
 common-$(CONFIG_ACCEL_LIS2DW12)+=math_util.o
 common-$(CONFIG_ACCEL_LIS2DH)+=math_util.o
 common-$(CONFIG_ACCEL_LIS2DS)+=math_util.o
 common-$(CONFIG_ACCEL_KXCJ9)+=math_util.o
 common-$(CONFIG_ACCEL_KX022)+=math_util.o
-ifneq ($(CORE),cortex-m)
-common-$(CONFIG_AES)+=aes.o
-endif
-common-$(CONFIG_AES_GCM)+=aes-gcm.o
+common-$(CONFIG_BODY_DETECTION)+=math_util.o
+common-$(CONFIG_TEMP_SENSOR_TMP112)+=math_util.o
+common-$(CONFIG_TEMP_SENSOR_PCT2075)+=math_util.o
 common-$(CONFIG_CMD_ADC)+=adc.o
 common-$(HAS_TASK_ALS)+=als.o
 common-$(CONFIG_AP_HANG_DETECT)+=ap_hang_detect.o
@@ -40,25 +44,41 @@ common-$(CONFIG_BACKLIGHT_LID)+=backlight_lid.o
 common-$(CONFIG_BASE32)+=base32.o
 common-$(CONFIG_BLINK)+=blink.o
 common-$(CONFIG_DETACHABLE_BASE)+=base_state.o
-common-$(CONFIG_BATTERY)+=battery.o
+common-$(CONFIG_BATTERY)+=battery.o math_util.o
+common-$(CONFIG_BATTERY_CONFIG_IN_CBI)+=battery_config.o
+common-$(CONFIG_BATTERY_V1)+=battery_v1.o
+common-$(CONFIG_BATTERY_V2)+=battery_v2.o
 common-$(CONFIG_BATTERY_FUEL_GAUGE)+=battery_fuel_gauge.o
 common-$(CONFIG_BLUETOOTH_LE)+=bluetooth_le.o
 common-$(CONFIG_BLUETOOTH_LE_STACK)+=btle_hci_controller.o btle_ll.o
 common-$(CONFIG_BODY_DETECTION)+=body_detection.o
 common-$(CONFIG_CAPSENSE)+=capsense.o
 common-$(CONFIG_CEC)+=cec.o
-common-$(CONFIG_CROS_BOARD_INFO)+=cbi.o
+common-$(CONFIG_CBI_EEPROM)+=cbi.o cbi_eeprom.o
+common-$(CONFIG_USB_PD_FLAGS)+=usb_pd_flags.o
+common-$(CONFIG_CBI_GPIO)+=cbi.o cbi_gpio.o
+ifeq ($(HAS_MOCK_CHARGE_MANAGER),)
 common-$(CONFIG_CHARGE_MANAGER)+=charge_manager.o
+endif
 common-$(CONFIG_CHARGE_RAMP_HW)+=charge_ramp.o
 common-$(CONFIG_CHARGE_RAMP_SW)+=charge_ramp.o charge_ramp_sw.o
+common-$(CONFIG_CHARGESPLASH)+=chargesplash.o
+common-$(CONFIG_CHIP_INIT_ROM_REGION)+=init_rom.o
 common-$(CONFIG_CMD_CHARGEN) += chargen.o
-common-$(CONFIG_CHARGER)+=charger.o charge_state_v2.o
+common-$(CONFIG_CHARGER)+=charger.o
+ifneq ($(CONFIG_CHARGER),)
+common-$(CONFIG_BATTERY)+=charge_state.o
+endif
+ifneq ($(CONFIG_EC_EC_COMM_BATTERY_CLIENT),)
+common-$(CONFIG_BATTERY)+=charger_base.o
+endif
 common-$(CONFIG_CHARGER_PROFILE_OVERRIDE_COMMON)+=charger_profile_override.o
 common-$(CONFIG_CMD_I2CWEDGE)+=i2c_wedge.o
 common-$(CONFIG_COMMON_GPIO)+=gpio.o gpio_commands.o
-common-$(CONFIG_IO_EXPANDER)+=ioexpander.o
+common-$(CONFIG_IO_EXPANDER)+=ioexpander.o ioexpander_commands.o
 common-$(CONFIG_COMMON_PANIC_OUTPUT)+=panic_output.o
-common-$(CONFIG_COMMON_RUNTIME)+=hooks.o main.o system.o peripheral.o init_rom.o
+common-$(CONFIG_COMMON_RUNTIME)+=hooks.o main.o system.o peripheral.o \
+	system_boot_time.o
 common-$(CONFIG_COMMON_TIMER)+=timer.o
 common-$(CONFIG_CRC8)+= crc8.o
 common-$(CONFIG_CURVE25519)+=curve25519.o
@@ -69,32 +89,36 @@ common-$(CONFIG_DEDICATED_RECOVERY_BUTTON)+=button.o
 common-$(CONFIG_DEVICE_EVENT)+=device_event.o
 common-$(CONFIG_DEVICE_STATE)+=device_state.o
 common-$(CONFIG_DPTF)+=dptf.o
-common-$(CONFIG_EC_EC_COMM_MASTER)+=ec_ec_comm_master.o
-common-$(CONFIG_EC_EC_COMM_SLAVE)+=ec_ec_comm_slave.o
-common-$(CONFIG_HOSTCMD_ESPI)+=espi.o
+common-$(CONFIG_EC_EC_COMM_CLIENT)+=ec_ec_comm_client.o
+common-$(CONFIG_EC_EC_COMM_SERVER)+=ec_ec_comm_server.o
+common-$(CONFIG_HOST_INTERFACE_ESPI)+=espi.o
 common-$(CONFIG_EXTPOWER_GPIO)+=extpower_gpio.o
 common-$(CONFIG_EXTPOWER)+=extpower_common.o
 common-$(CONFIG_FANS)+=fan.o pwm.o
-common-$(CONFIG_FLASH)+=flash.o
+common-$(CONFIG_FLASH_CROS)+=flash.o
 common-$(CONFIG_FMAP)+=fmap.o
 common-$(CONFIG_GESTURE_SW_DETECTION)+=gesture.o
 common-$(CONFIG_HOSTCMD_EVENTS)+=host_event_commands.o
 common-$(CONFIG_HOSTCMD_GET_UPTIME_INFO)+=uptime.o
-common-$(CONFIG_HOSTCMD_PD)+=host_command_master.o
+common-$(CONFIG_HOSTCMD_PD)+=host_command_controller.o
 common-$(CONFIG_HOSTCMD_REGULATOR)+=regulator.o
 common-$(CONFIG_HOSTCMD_RTC)+=rtc.o
 common-$(CONFIG_I2C_DEBUG)+=i2c_trace.o
 common-$(CONFIG_I2C_HID_TOUCHPAD)+=i2c_hid_touchpad.o
-common-$(CONFIG_I2C_MASTER)+=i2c_master.o
-common-$(CONFIG_I2C_SLAVE)+=i2c_slave.o
+common-$(CONFIG_I2C_CONTROLLER)+=i2c_controller.o
+common-$(CONFIG_I2C_CONTROLLER)+=i2c_controller_cros_ec.o
+common-$(CONFIG_I2C_PERIPHERAL)+=i2c_peripheral.o
 common-$(CONFIG_I2C_BITBANG)+=i2c_bitbang.o
 common-$(CONFIG_I2C_VIRTUAL_BATTERY)+=virtual_battery.o
 common-$(CONFIG_INDUCTIVE_CHARGING)+=inductive_charging.o
 common-$(CONFIG_KEYBOARD_PROTOCOL_8042)+=keyboard_8042.o \
 	keyboard_8042_sharedlib.o
-common-$(CONFIG_KEYBOARD_PROTOCOL_MKBP)+=keyboard_mkbp.o
+common-$(CONFIG_KEYBOARD_PROTOCOL_MKBP)+=keyboard_mkbp.o mkbp_fifo.o \
+	mkbp_info.o
 common-$(CONFIG_KEYBOARD_TEST)+=keyboard_test.o
 common-$(CONFIG_KEYBOARD_VIVALDI)+=keyboard_vivaldi.o
+common-$(CONFIG_MKBP_INPUT_DEVICES)+=mkbp_input_devices.o mkbp_fifo.o \
+	mkbp_info.o
 common-$(CONFIG_LED_COMMON)+=led_common.o
 common-$(CONFIG_LED_POLICY_STD)+=led_policy_std.o
 common-$(CONFIG_LED_PWM)+=led_pwm.o
@@ -108,15 +132,19 @@ common-$(CONFIG_MAG_CALIBRATE)+= mag_cal.o math_util.o vec3.o mat33.o mat44.o \
 common-$(CONFIG_MKBP_EVENT)+=mkbp_event.o
 common-$(CONFIG_OCPC)+=ocpc.o
 common-$(CONFIG_ONEWIRE)+=onewire.o
+common-$(CONFIG_ORIENTATION_SENSOR)+=motion_orientation.o
 common-$(CONFIG_PECI_COMMON)+=peci.o
+common-$(CONFIG_PERIPHERAL_CHARGER)+=peripheral_charger.o
 common-$(CONFIG_POWER_BUTTON)+=power_button.o
 common-$(CONFIG_POWER_BUTTON_X86)+=power_button_x86.o
 common-$(CONFIG_PSTORE)+=pstore_commands.o
 common-$(CONFIG_PWM)+=pwm.o
 common-$(CONFIG_PWM_KBLIGHT)+=pwm_kblight.o
 common-$(CONFIG_KEYBOARD_BACKLIGHT)+=keyboard_backlight.o
-common-$(CONFIG_RSA)+=rsa.o
+common-$(CONFIG_RGB_KEYBOARD)+=rgb_keyboard.o
+common-$(CONFIG_RNG)+=trng.o
 common-$(CONFIG_ROLLBACK)+=rollback.o
+common-$(CONFIG_RSA)+=rsa.o
 common-$(CONFIG_RWSIG)+=rwsig.o vboot/common.o
 common-$(CONFIG_RWSIG_TYPE_RWSIG)+=vboot/vb21_lib.o
 common-$(CONFIG_MATH_UTIL)+=math_util.o
@@ -124,12 +152,17 @@ common-$(CONFIG_ONLINE_CALIB)+=stillness_detector.o kasa.o math_util.o \
 	mat44.o vec3.o newton_fit.o accel_cal.o online_calibration.o \
 	mkbp_event.o mag_cal.o math_util.o mat33.o gyro_cal.o gyro_still_det.o
 common-$(CONFIG_SHA1)+= sha1.o
-common-$(CONFIG_SHA256)+=sha256.o
+ifeq ($(CONFIG_SHA256),y)
+# use the standard software SHA256 lib if the chip cannot support SHA256
+# hardware accelerator.
+ifeq ($(CONFIG_SHA256_HW_ACCELERATE),)
+common-y+=sha256.o
+endif
+endif
 common-$(CONFIG_SOFTWARE_CLZ)+=clz.o
 common-$(CONFIG_SOFTWARE_CTZ)+=ctz.o
 common-$(CONFIG_CMD_SPI_XFER)+=spi_commands.o
-common-$(CONFIG_SPI_FLASH)+=spi_flash.o spi_flash_reg.o
-common-$(CONFIG_SPI_FLASH_REGS)+=spi_flash_reg.o
+common-$(CONFIG_SPI_FLASH)+=spi_flash.o
 common-$(CONFIG_SPI_NOR)+=spi_nor.o
 common-$(CONFIG_SWITCH)+=switch.o
 common-$(CONFIG_SW_CRC)+=crc.o
@@ -140,48 +173,76 @@ common-$(CONFIG_THROTTLE_AP_ON_BAT_DISCHG_CURRENT)+=throttle_ap.o
 common-$(CONFIG_THROTTLE_AP_ON_BAT_VOLTAGE)+=throttle_ap.o
 common-$(CONFIG_USB_CHARGER)+=usb_charger.o
 common-$(CONFIG_USB_CONSOLE_STREAM)+=usb_console_stream.o
+common-$(CONFIG_HOST_INTERFACE_USB)+=usb_host_command.o
 common-$(CONFIG_USB_I2C)+=usb_i2c.o
 common-$(CONFIG_USB_PORT_POWER_DUMB)+=usb_port_power_dumb.o
 common-$(CONFIG_USB_PORT_POWER_SMART)+=usb_port_power_smart.o
 common-$(CONFIG_HAS_TASK_PD_INT)+=usbc_intr_task.o
 ifneq ($(CONFIG_USB_POWER_DELIVERY),)
-common-$(CONFIG_USB_POWER_DELIVERY)+=usb_common.o
+common-$(CONFIG_USB_POWER_DELIVERY)+=usb_common.o usb_pd_pdo.o typec_control.o
 ifneq ($(CONFIG_USB_PD_TCPMV1),)
-common-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_protocol.o usb_pd_policy.o
+common-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_protocol.o usb_pd_policy.o \
+	usb_pd_pdo.o
 endif
 common-$(CONFIG_USB_PD_DUAL_ROLE)+=usb_pd_dual_role.o
 common-$(CONFIG_USB_PD_HOST_CMD)+=usb_pd_host_cmd.o
 common-$(CONFIG_USB_PD_CONSOLE_CMD)+=usb_pd_console_cmd.o
 endif
-common-$(CONFIG_USB_PD_ALT_MODE_DFP)+=usb_pd_alt_mode_dfp.o
+common-$(CONFIG_USB_PD_DISCOVERY)+=usb_pd_discovery.o
+common-$(CONFIG_USB_PD_ALT_MODE_UFP)+=usb_pd_alt_mode_ufp.o
+common-$(CONFIG_USB_PD_DPS)+=dps.o
 common-$(CONFIG_USB_PD_LOGGING)+=event_log.o pd_log.o
 common-$(CONFIG_USB_PD_TCPC)+=usb_pd_tcpc.o
 common-$(CONFIG_USB_UPDATE)+=usb_update.o update_fw.o
+common-$(CONFIG_USBC_OCP)+=usbc_ocp.o
 common-$(CONFIG_USBC_PPC)+=usbc_ppc.o
 common-$(CONFIG_VBOOT_EFS)+=vboot/vboot.o
 common-$(CONFIG_VBOOT_EFS2)+=vboot/efs2.o
-common-$(CONFIG_VBOOT_HASH)+=sha256.o vboot_hash.o
+ifeq ($(CONFIG_VBOOT_HASH),y)
+common-y+=vboot_hash.o
+# use the standard software SHA256 lib if the chip cannot support SHA256
+# hardware accelerator.
+ifeq ($(CONFIG_SHA256_HW_ACCELERATE),)
+common-y+=sha256.o
+endif
+endif
 common-$(CONFIG_VOLUME_BUTTONS)+=button.o
 common-$(CONFIG_VSTORE)+=vstore.o
 common-$(CONFIG_WEBUSB_URL)+=webusb_desc.o
 common-$(CONFIG_WIRELESS)+=wireless.o
 common-$(HAS_TASK_CHIPSET)+=chipset.o
-common-$(HAS_TASK_CONSOLE)+=console.o console_output.o uart_buffering.o
+common-$(HAS_TASK_CONSOLE)+=console.o console_output.o
+common-$(HAS_TASK_CONSOLE)+=uart_buffering.o uart_hostcmd.o uart_printf.o
 common-$(CONFIG_CMD_MEM)+=memory_commands.o
 common-$(HAS_TASK_HOSTCMD)+=host_command.o ec_features.o
 common-$(HAS_TASK_PDCMD)+=host_command_pd.o
 common-$(HAS_TASK_KEYSCAN)+=keyboard_scan.o
 common-$(HAS_TASK_LIGHTBAR)+=lb_common.o lightbar.o
 common-$(HAS_TASK_MOTIONSENSE)+=motion_sense.o
+common-$(CONFIG_SYSTEM_SAFE_MODE)+=system_safe_mode.o
 
 ifneq ($(HAVE_PRIVATE_AUDIO_CODEC_WOV_LIBS),y)
 common-$(CONFIG_AUDIO_CODEC_WOV)+=hotword_dsp_api.o
 endif
 
-ifneq ($(CONFIG_COMMON_RUNTIME),)
+ifeq ($(USE_BUILTIN_STDLIB), 0)
+common-y+=shared_mem_libc.o
+else ifneq ($(CONFIG_COMMON_RUNTIME),)
+ifeq ($(CONFIG_DFU_BOOTMANAGER_MAIN),ro)
+# Ordinary RO is replaced with DFU bootloader stub, CONFIG_MALLOC should only affect RW.
+ifeq ($(CONFIG_MALLOC),y)
+common-rw+=shmalloc.o
+else ifeq ($(CONFIG_MALLOC),rw)
+common-rw+=shmalloc.o
+else
+common-rw+=shared_mem.o
+endif
+else
+# CONFIG_MALLOC affects both RO and RW as usual (with shared_mem in case it is disabled.)
 common-$(CONFIG_MALLOC)+=shmalloc.o
 common-$(call not_cfg,$(CONFIG_MALLOC))+=shared_mem.o
 endif
+endif
 
 ifeq ($(CTS_MODULE),)
 common-$(TEST_BUILD)+=test_util.o
@@ -194,11 +255,6 @@ $(out)/RW/common/rsa.o: CFLAGS+=-O3
 $(out)/RO/common/rsa.o: CFLAGS+=-O3
 endif
 
-# AES-GCM code needs C99, else we'd have to move many variables declarations
-# around.
-$(out)/RW/common/aes-gcm.o: CFLAGS+=-std=c99 -Wno-declaration-after-statement
-$(out)/RO/common/aes-gcm.o: CFLAGS+=-std=c99 -Wno-declaration-after-statement
-
 ifneq ($(CONFIG_BOOTBLOCK),)
 
 ifdef BOOTBLOCK
@@ -220,10 +276,6 @@ $(out)/.fake-bootblock:
 
 endif # BOOTBLOCK
 
-build-util-bin += gen_emmc_transfer_data
-
-# Bootblock is only packed in RO image.
-$(out)/util/gen_emmc_transfer_data: BUILD_LDFLAGS += -DSECTION_IS_RO=$(EMPTY)
 $(out)/bootblock_data.h: $(out)/util/gen_emmc_transfer_data $(out)/.bootblock
 	$(call quiet,emmc_bootblock,BTBLK  )
 
@@ -280,37 +332,9 @@ $(out)/rma_key_from_blob.h: board/$(BOARD)/$(BLOB_FILE) util/bin2h.sh
 
 endif
 
-# Build and link against libcryptoc.
-ifeq ($(CONFIG_LIBCRYPTOC),y)
-CRYPTOCLIB := $(realpath ../../third_party/cryptoc)
-ifneq ($(BOARD),host)
-CPPFLAGS += -I$(abspath ./builtin)
-endif
-CPPFLAGS += -I$(CRYPTOCLIB)/include
-CRYPTOC_LDFLAGS := -L$(out)/cryptoc -lcryptoc
-
-# Force the external build each time, so it can look for changed sources.
-.PHONY: $(out)/cryptoc/libcryptoc.a
-$(out)/cryptoc/libcryptoc.a:
-	+$(call quiet,libcryptoc,MAKE   )
-
-# Link RO and RW against cryptoc.
-$(out)/RO/ec.RO.elf $(out)/RO/ec.RO_B.elf: LDFLAGS_EXTRA += $(CRYPTOC_LDFLAGS)
-$(out)/RO/ec.RO.elf $(out)/RO/ec.RO_B.elf: $(out)/cryptoc/libcryptoc.a
-$(out)/RW/ec.RW.elf $(out)/RW/ec.RW_B.elf: LDFLAGS_EXTRA += $(CRYPTOC_LDFLAGS)
-$(out)/RW/ec.RW.elf $(out)/RW/ec.RW_B.elf: $(out)/cryptoc/libcryptoc.a
-# Host test executables (including fuzz tests).
-$(out)/$(PROJECT).exe: LDFLAGS_EXTRA += $(CRYPTOC_LDFLAGS)
-$(out)/$(PROJECT).exe: $(out)/cryptoc/libcryptoc.a
-# On-device tests.
-test-targets=$(foreach test,$(test-list-y),\
-	$(out)/RW/$(test).RW.elf $(out)/RO/$(test).RO.elf)
-$(test-targets): LDFLAGS_EXTRA += $(CRYPTOC_LDFLAGS)
-$(test-targets): $(out)/cryptoc/libcryptoc.a
-endif
-
 include $(_common_dir)fpsensor/build.mk
 include $(_common_dir)usbc/build.mk
+include $(_common_dir)spi/build.mk
 
 include $(_common_dir)mock/build.mk
 common-y+=$(foreach m,$(mock-y),mock/$(m))
diff --git a/common/button.c b/common/button.c
index 6f346ec7cb..27cd8ae058 100644
--- a/common/button.c
+++ b/common/button.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,10 +12,11 @@
 #include "compile_time_macros.h"
 #include "console.h"
 #include "gpio.h"
-#include "host_command.h"
 #include "hooks.h"
+#include "host_command.h"
 #include "keyboard_protocol.h"
 #include "led_common.h"
+#include "mkbp_input_devices.h"
 #include "power_button.h"
 #include "system.h"
 #include "timer.h"
@@ -23,16 +24,16 @@
 #include "watchdog.h"
 
 /* Console output macro */
-#define CPRINTS(format, args...) cprints(CC_SWITCH, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SWITCH, format, ##args)
 
 struct button_state_t {
 	uint64_t debounce_time;
 	int debounced_pressed;
 };
 
-static struct button_state_t __bss_slow state[BUTTON_COUNT];
+static struct button_state_t state[BUTTON_COUNT];
 
-static uint64_t __bss_slow next_deferred_time;
+static uint64_t next_deferred_time;
 
 #if defined(CONFIG_CMD_BUTTON) || defined(CONFIG_HOSTCMD_BUTTON)
 #define CONFIG_SIMULATED_BUTTON
@@ -42,7 +43,7 @@ static uint64_t __bss_slow next_deferred_time;
 /* Bitmask to keep track of simulated state of each button.
  * Bit numbers are aligned to enum button.
  */
-static int sim_button_state;
+static atomic_t sim_button_state;
 
 /*
  * Flip state of associated button type in sim_button_state bitmask.
@@ -61,7 +62,7 @@ static int sim_button_state;
  */
 static int simulated_button_pressed(const struct button_config *button)
 {
-	return !!(sim_button_state & BIT(button->type));
+	return !!((uint32_t)sim_button_state & BIT(button->type));
 }
 #endif
 
@@ -74,12 +75,12 @@ static int raw_button_pressed(const struct button_config *button)
 	int simulated_value = 0;
 	if (!(button->flags & BUTTON_FLAG_DISABLED)) {
 		if (IS_ENABLED(CONFIG_ADC_BUTTONS) &&
-			button_is_adc_detected(button->gpio)) {
-			physical_value =
-				adc_to_physical_value(button->gpio);
+		    button_is_adc_detected(button->gpio)) {
+			physical_value = adc_to_physical_value(button->gpio);
 		} else {
-			physical_value = (!!gpio_get_level(button->gpio) ==
-				!!(button->flags & BUTTON_FLAG_ACTIVE_HIGH));
+			physical_value =
+				(!!gpio_get_level(button->gpio) ==
+				 !!(button->flags & BUTTON_FLAG_ACTIVE_HIGH));
 		}
 #ifdef CONFIG_SIMULATED_BUTTON
 		simulated_value = simulated_button_pressed(button);
@@ -192,7 +193,7 @@ static int is_recovery_boot(void)
 	if (system_jumped_to_this_image())
 		return 0;
 	if (!(system_get_reset_flags() &
-	    (EC_RESET_FLAG_RESET_PIN | EC_RESET_FLAG_POWER_ON)))
+	      (EC_RESET_FLAG_RESET_PIN | EC_RESET_FLAG_POWER_ON)))
 		return 0;
 	if (!is_recovery_button_pressed())
 		return 0;
@@ -201,7 +202,7 @@ static int is_recovery_boot(void)
 #endif /* CONFIG_BUTTON_TRIGGERED_RECOVERY */
 
 static void button_reset(enum button button_type,
-	const struct button_config *button)
+			 const struct button_config *button)
 {
 	state[button_type].debounced_pressed = raw_button_pressed(button);
 	state[button_type].debounce_time = 0;
@@ -259,7 +260,6 @@ int button_disable_gpio(enum button button_type)
 }
 #endif
 
-
 /*
  * Handle debounced button changing state.
  */
@@ -307,13 +307,15 @@ static void button_change_deferred(void)
 					hook_call_deferred(
 						&debug_mode_handle_data, 0);
 #endif
-				CPRINTS("Button '%s' was %s",
-					buttons[i].name, new_pressed ?
-					"pressed" : "released");
-#if defined(HAS_TASK_KEYPROTO) || defined(CONFIG_KEYBOARD_PROTOCOL_MKBP)
-				keyboard_update_button(buttons[i].type,
-					new_pressed);
-#endif
+				CPRINTS("Button '%s' was %s", buttons[i].name,
+					new_pressed ? "pressed" : "released");
+				if (IS_ENABLED(CONFIG_MKBP_INPUT_DEVICES)) {
+					mkbp_button_update(buttons[i].type,
+							   new_pressed);
+				} else if (IS_ENABLED(HAS_TASK_KEYPROTO)) {
+					keyboard_update_button(buttons[i].type,
+							       new_pressed);
+				}
 			}
 
 			/* Clear the debounce time to stop checking it */
@@ -323,10 +325,11 @@ static void button_change_deferred(void)
 			 * Make sure the next deferred call happens on or before
 			 * each button needs it.
 			 */
-			soonest_debounce_time = (soonest_debounce_time == 0) ?
-				state[i].debounce_time :
-				MIN(soonest_debounce_time,
-				    state[i].debounce_time);
+			soonest_debounce_time =
+				(soonest_debounce_time == 0) ?
+					state[i].debounce_time :
+					MIN(soonest_debounce_time,
+					    state[i].debounce_time);
 		}
 	}
 
@@ -385,11 +388,11 @@ static void simulate_button_release_deferred(void)
 	/* Release the button */
 	for (button_idx = 0; button_idx < BUTTON_COUNT; button_idx++) {
 		/* Check state for button pressed */
-		if (sim_button_state & BIT(buttons[button_idx].type)) {
+		if ((uint32_t)sim_button_state &
+		    BIT(buttons[button_idx].type)) {
 			/* Set state of the button as released */
-			deprecated_atomic_clear_bits(
-				&sim_button_state,
-				BIT(buttons[button_idx].type));
+			atomic_clear_bits(&sim_button_state,
+					  BIT(buttons[button_idx].type));
 
 			button_interrupt_simulate(button_idx);
 		}
@@ -405,8 +408,8 @@ static void simulate_button(uint32_t button_mask, int press_ms)
 	for (button_idx = 0; button_idx < BUTTON_COUNT; button_idx++) {
 		if (button_mask & BIT(button_idx)) {
 			/* Set state of the button as pressed */
-			deprecated_atomic_or(&sim_button_state,
-					     BIT(buttons[button_idx].type));
+			atomic_or(&sim_button_state,
+				  BIT(buttons[button_idx].type));
 
 			button_interrupt_simulate(button_idx);
 		}
@@ -414,12 +417,12 @@ static void simulate_button(uint32_t button_mask, int press_ms)
 
 	/* Defer the button release for specified duration */
 	hook_call_deferred(&simulate_button_release_deferred_data,
-				press_ms * MSEC);
+			   press_ms * MSEC);
 }
 #endif /* #ifdef CONFIG_SIMULATED_BUTTON */
 
 #ifdef CONFIG_CMD_BUTTON
-static int console_command_button(int argc, char **argv)
+static int console_command_button(int argc, const char **argv)
 {
 	int press_ms = 50;
 	char *e;
@@ -461,8 +464,7 @@ static int console_command_button(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(button, console_command_button,
-			"vup|vdown|rec msec",
+DECLARE_CONSOLE_COMMAND(button, console_command_button, "vup|vdown|rec msec",
 			"Simulate button press");
 #endif /* CONFIG_CMD_BUTTON */
 
@@ -490,7 +492,6 @@ DECLARE_HOST_COMMAND(EC_CMD_BUTTON, host_command_button, EC_VER_MASK(0));
 
 #endif /* CONFIG_HOSTCMD_BUTTON */
 
-
 #ifdef CONFIG_EMULATED_SYSRQ
 
 #ifdef CONFIG_DEDICATED_RECOVERY_BUTTON
@@ -531,21 +532,10 @@ static void debug_mode_handle(void)
 
 #else /* CONFIG_DEDICATED_RECOVERY_BUTTON */
 
-enum debug_state {
-	STATE_DEBUG_NONE,
-	STATE_DEBUG_CHECK,
-	STATE_STAGING,
-	STATE_DEBUG_MODE_ACTIVE,
-	STATE_SYSRQ_PATH,
-	STATE_WARM_RESET_PATH,
-	STATE_SYSRQ_EXEC,
-	STATE_WARM_RESET_EXEC,
-};
-
-#define DEBUG_BTN_POWER         BIT(0)
-#define DEBUG_BTN_VOL_UP        BIT(1)
-#define DEBUG_BTN_VOL_DN        BIT(2)
-#define DEBUG_TIMEOUT           (10 * SECOND)
+#define DEBUG_BTN_POWER BIT(0)
+#define DEBUG_BTN_VOL_UP BIT(1)
+#define DEBUG_BTN_VOL_DN BIT(2)
+#define DEBUG_TIMEOUT (10 * SECOND)
 
 static enum debug_state curr_debug_state = STATE_DEBUG_NONE;
 static enum debug_state next_debug_state = STATE_DEBUG_NONE;
@@ -668,6 +658,16 @@ static void debug_mode_transition(enum debug_state next_state)
 #endif
 }
 
+__test_only void reset_button_debug_state(void)
+{
+	debug_mode_transition(STATE_DEBUG_NONE);
+}
+
+__test_only enum debug_state get_button_debug_state(void)
+{
+	return curr_debug_state;
+}
+
 static void debug_mode_handle(void)
 {
 	int mask;
@@ -717,8 +717,9 @@ static void debug_mode_handle(void)
 			 * Schedule a deferred call in case timeout hasn't
 			 * occurred yet.
 			 */
-			hook_call_deferred(&debug_mode_handle_data,
-					(debug_state_deadline.val - now.val));
+			hook_call_deferred(
+				&debug_mode_handle_data,
+				(debug_state_deadline.val - now.val));
 		}
 
 		break;
@@ -848,20 +849,26 @@ struct button_config buttons[BUTTON_COUNT] = {
 
 #endif
 #if defined(CONFIG_DEDICATED_RECOVERY_BUTTON)
+#ifndef CONFIG_DEDICATED_RECOVERY_BUTTON_FLAGS
+#define CONFIG_DEDICATED_RECOVERY_BUTTON_FLAGS 0
+#endif
 	[BUTTON_RECOVERY] = {
 		.name = "Recovery",
 		.type = KEYBOARD_BUTTON_RECOVERY,
 		.gpio = GPIO_RECOVERY_L,
 		.debounce_us = BUTTON_DEBOUNCE_US,
-		.flags = 0,
+		.flags = CONFIG_DEDICATED_RECOVERY_BUTTON_FLAGS,
 	},
 #ifdef CONFIG_DEDICATED_RECOVERY_BUTTON_2
+#ifndef CONFIG_DEDICATED_RECOVERY_BUTTON_2_FLAGS
+#define CONFIG_DEDICATED_RECOVERY_BUTTON_2_FLAGS 0
+#endif
 	[BUTTON_RECOVERY_2] = {
 		.name = "Recovery2",
 		.type = KEYBOARD_BUTTON_RECOVERY,
 		.gpio = GPIO_RECOVERY_L_2,
 		.debounce_us = BUTTON_DEBOUNCE_US,
-		.flags = 0,
+		.flags = CONFIG_DEDICATED_RECOVERY_BUTTON_2_FLAGS,
 	}
 #endif /* defined(CONFIG_DEDICATED_RECOVERY_BUTTON_2) */
 #endif /* defined(CONFIG_DEDICATED_RECOVERY_BUTTON) */
diff --git a/common/capsense.c b/common/capsense.c
index b2413ac61f..2c2bbd6db5 100644
--- a/common/capsense.c
+++ b/common/capsense.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,11 +9,12 @@
 #include "hooks.h"
 #include "i2c.h"
 #include "keyboard_protocol.h"
+#include "printf.h"
 #include "timer.h"
 
 /* Console output macro */
-#define CPRINTF(format, args...) cprintf(CC_KEYBOARD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_KEYBOARD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ##args)
 
 #define CAPSENSE_I2C_ADDR 0x08
 #define CAPSENSE_MASK_BITS 8
@@ -24,8 +25,7 @@ static int capsense_read_bitmask(void)
 	int rv;
 	uint8_t val = 0;
 
-	rv = i2c_xfer(I2C_PORT_CAPSENSE, CAPSENSE_I2C_ADDR,
-		      0, 0, &val, 1);
+	rv = i2c_xfer(I2C_PORT_CAPSENSE, CAPSENSE_I2C_ADDR, 0, 0, &val, 1);
 
 	if (rv)
 		CPRINTS("%s failed: error %d", __func__, rv);
@@ -49,11 +49,12 @@ static void capsense_change_deferred(void)
 	static uint8_t cur_val;
 	uint8_t new_val;
 	int i, n, c;
+	char ts_str[PRINTF_TIMESTAMP_BUF_SIZE];
 
 	new_val = capsense_read_bitmask();
 	if (new_val != cur_val) {
-		CPRINTF("[%pT capsense 0x%02x: ",
-			PRINTF_TIMESTAMP_NOW, new_val);
+		snprintf_timestamp_now(ts_str, sizeof(ts_str));
+		CPRINTF("[%s capsense 0x%02x: ", ts_str, new_val);
 		for (i = 0; i < CAPSENSE_MASK_BITS; i++) {
 			/* See what changed */
 			n = (new_val >> i) & 0x01;
diff --git a/common/cbi.c b/common/cbi.c
index c6fa213807..3cbf630492 100644
--- a/common/cbi.c
+++ b/common/cbi.c
@@ -1,10 +1,11 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Cros Board Info
  */
 
+#include "chipset.h"
 #include "common.h"
 #include "console.h"
 #include "crc8.h"
@@ -26,12 +27,12 @@
  */
 uint8_t cbi_crc8(const struct cbi_header *h)
 {
-	return crc8((uint8_t *)&h->crc + 1,
-		    h->total_size - sizeof(h->magic) - sizeof(h->crc));
+	return cros_crc8((uint8_t *)&h->crc + 1,
+			 h->total_size - sizeof(h->magic) - sizeof(h->crc));
 }
 
-uint8_t *cbi_set_data(uint8_t *p, enum cbi_data_tag tag,
-		      const void *buf, int size)
+uint8_t *cbi_set_data(uint8_t *p, enum cbi_data_tag tag, const void *buf,
+		      int size)
 {
 	struct cbi_data *d = (struct cbi_data *)p;
 
@@ -76,57 +77,41 @@ struct cbi_data *cbi_find_tag(const void *buf, enum cbi_data_tag tag)
  */
 #ifndef HOST_TOOLS_BUILD
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, "CBI " format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, "CBI " format, ##args)
 
-/*
- * We allow EEPROMs with page size of 8 or 16. Use 8 to be the most compatible.
- * This causes a little more overhead for writes, but we are not writing to the
- * EEPROM outside of the factory process.
- */
-#define EEPROM_PAGE_WRITE_SIZE	8
-
-#define EEPROM_PAGE_WRITE_MS	5
-#define EC_ERROR_CBI_CACHE_INVALID	EC_ERROR_INTERNAL_FIRST
-
-static int cached_read_result = EC_ERROR_CBI_CACHE_INVALID;
-static uint8_t cbi[CBI_EEPROM_SIZE];
-static struct cbi_header * const head = (struct cbi_header *)cbi;
+static int cache_status = CBI_CACHE_STATUS_INVALID;
+static uint8_t cbi[CBI_IMAGE_SIZE];
+static struct cbi_header *const head = (struct cbi_header *)cbi;
 
 int cbi_create(void)
 {
-	struct cbi_header * const h = (struct cbi_header *)cbi;
-
 	memset(cbi, 0, sizeof(cbi));
-	memcpy(h->magic, cbi_magic, sizeof(cbi_magic));
-	h->total_size = sizeof(*h);
-	h->major_version = CBI_VERSION_MAJOR;
-	h->minor_version = CBI_VERSION_MINOR;
-	h->crc = cbi_crc8(h);
-	cached_read_result = EC_SUCCESS;
+	memcpy(head->magic, cbi_magic, sizeof(cbi_magic));
+	head->total_size = sizeof(*head);
+	head->major_version = CBI_VERSION_MAJOR;
+	head->minor_version = CBI_VERSION_MINOR;
+	head->crc = cbi_crc8(head);
+	cache_status = CBI_CACHE_STATUS_SYNCED;
 
 	return EC_SUCCESS;
 }
 
 void cbi_invalidate_cache(void)
 {
-	cached_read_result = EC_ERROR_CBI_CACHE_INVALID;
+	cache_status = CBI_CACHE_STATUS_INVALID;
 }
 
-static int read_eeprom(uint8_t offset, uint8_t *in, int in_size)
+int cbi_get_cache_status(void)
 {
-	return i2c_read_block(I2C_PORT_EEPROM, I2C_ADDR_EEPROM_FLAGS,
-			      offset, in, in_size);
+	return cache_status;
 }
 
-/*
- * Get board information from EEPROM
- */
-static int do_read_board_info(void)
+static int do_cbi_read(void)
 {
 	CPRINTS("Reading board info");
 
 	/* Read header */
-	if (read_eeprom(0, cbi, sizeof(*head))) {
+	if (cbi_config.drv->load(0, cbi, sizeof(*head))) {
 		CPRINTS("Failed to read header");
 		return EC_ERROR_INVAL;
 	}
@@ -143,23 +128,26 @@ static int do_read_board_info(void)
 		return EC_ERROR_INVAL;
 	}
 
-	/* Check the data size. It's expected to support up to 64k but our
-	 * buffer has practical limitation. */
+	/*
+	 * Check the data size. It's expected to support up to 64k but our
+	 * buffer has practical limitation.
+	 */
 	if (head->total_size < sizeof(*head) ||
-			sizeof(cbi) < head->total_size) {
+	    head->total_size > CBI_IMAGE_SIZE) {
 		CPRINTS("Bad size: %d", head->total_size);
 		return EC_ERROR_OVERFLOW;
 	}
 
 	/* Read the data */
-	if (read_eeprom(sizeof(*head), head->data,
-			head->total_size - sizeof(*head))) {
+	if (cbi_config.drv->load(sizeof(*head), head->data,
+				 head->total_size - sizeof(*head))) {
 		CPRINTS("Failed to read body");
 		return EC_ERROR_INVAL;
 	}
 
 	/* Check CRC. This supports new fields unknown to this parser. */
-	if (cbi_crc8(head) != head->crc) {
+	if (cbi_config.storage_type != CBI_STORAGE_TYPE_GPIO &&
+	    cbi_crc8(head) != head->crc) {
 		CPRINTS("Bad CRC");
 		return EC_ERROR_INVAL;
 	}
@@ -167,21 +155,28 @@ static int do_read_board_info(void)
 	return EC_SUCCESS;
 }
 
-static int read_board_info(void)
+static int cbi_read(void)
 {
-	if (cached_read_result == EC_ERROR_CBI_CACHE_INVALID) {
-		cached_read_result = do_read_board_info();
-		if (cached_read_result)
-			/* On error (I2C or bad contents), retry a read */
-			cached_read_result = do_read_board_info();
+	int i;
+	int rv;
+
+	if (cbi_get_cache_status() == CBI_CACHE_STATUS_SYNCED)
+		return EC_SUCCESS;
+
+	for (i = 0; i < 2; i++) {
+		rv = do_cbi_read();
+		if (rv == EC_SUCCESS) {
+			cache_status = CBI_CACHE_STATUS_SYNCED;
+			return EC_SUCCESS;
+		}
+		/* On error (I2C or bad contents), retry a read */
 	}
-	/* Else, we already tried and know the result. Return the cached
-	 * error code immediately to avoid wasteful reads. */
-	return cached_read_result;
+
+	return rv;
 }
 
-__attribute__((weak))
-int cbi_board_override(enum cbi_data_tag tag, uint8_t *buf, uint8_t *size)
+__attribute__((weak)) int cbi_board_override(enum cbi_data_tag tag,
+					     uint8_t *buf, uint8_t *size)
 {
 	return EC_SUCCESS;
 }
@@ -190,7 +185,7 @@ int cbi_get_board_info(enum cbi_data_tag tag, uint8_t *buf, uint8_t *size)
 {
 	const struct cbi_data *d;
 
-	if (read_board_info())
+	if (cbi_read())
 		return EC_ERROR_UNKNOWN;
 
 	d = cbi_find_tag(cbi, tag);
@@ -221,7 +216,8 @@ static void cbi_remove_tag(void *const cbi, struct cbi_data *const d)
 	h->total_size -= size;
 }
 
-int cbi_set_board_info(enum cbi_data_tag tag, const uint8_t *buf, uint8_t size)
+test_mockable int cbi_set_board_info(enum cbi_data_tag tag, const uint8_t *buf,
+				     uint8_t size)
 {
 	struct cbi_data *d;
 
@@ -249,49 +245,17 @@ int cbi_set_board_info(enum cbi_data_tag tag, const uint8_t *buf, uint8_t size)
 	return EC_SUCCESS;
 }
 
-static int eeprom_is_write_protected(void)
-{
-#ifdef CONFIG_WP_ACTIVE_HIGH
-	return gpio_get_level(GPIO_WP);
-#else
-	return !gpio_get_level(GPIO_WP_L);
-#endif /* CONFIG_WP_ACTIVE_HIGH */
-}
-
-static int write_board_info(void)
+int cbi_write(void)
 {
-	const uint8_t *p = cbi;
-	int rest = head->total_size;
-
-	if (eeprom_is_write_protected()) {
-		CPRINTS("Failed to write for WP");
+	if (cbi_config.drv->is_protected()) {
+		CPRINTS("Failed to write due to WP");
 		return EC_ERROR_ACCESS_DENIED;
 	}
 
-	while (rest > 0) {
-		int size = MIN(EEPROM_PAGE_WRITE_SIZE, rest);
-		int rv;
-		rv = i2c_write_block(I2C_PORT_EEPROM, I2C_ADDR_EEPROM_FLAGS,
-				     p - cbi, p, size);
-		if (rv) {
-			CPRINTS("Failed to write for %d", rv);
-			return rv;
-		}
-		/* Wait for internal write cycle completion */
-		msleep(EEPROM_PAGE_WRITE_MS);
-		p += size;
-		rest -= size;
-	}
-
-	return EC_SUCCESS;
+	return cbi_config.drv->store(cbi);
 }
 
-int cbi_write(void)
-{
-	return write_board_info();
-}
-
-int cbi_get_board_version(uint32_t *ver)
+test_mockable int cbi_get_board_version(uint32_t *ver)
 {
 	uint8_t size = sizeof(*ver);
 
@@ -331,8 +295,7 @@ int cbi_get_ssfc(uint32_t *ssfc)
 {
 	uint8_t size = sizeof(*ssfc);
 
-	return cbi_get_board_info(CBI_TAG_SSFC, (uint8_t *)ssfc,
-				  &size);
+	return cbi_get_board_info(CBI_TAG_SSFC, (uint8_t *)ssfc, &size);
 }
 
 int cbi_get_pcb_supplier(uint32_t *pcb_supplier)
@@ -340,7 +303,21 @@ int cbi_get_pcb_supplier(uint32_t *pcb_supplier)
 	uint8_t size = sizeof(*pcb_supplier);
 
 	return cbi_get_board_info(CBI_TAG_PCB_SUPPLIER, (uint8_t *)pcb_supplier,
-			&size);
+				  &size);
+}
+
+int cbi_get_rework_id(uint64_t *id)
+{
+	uint8_t size = sizeof(*id);
+	return cbi_get_board_info(CBI_TAG_REWORK_ID, (uint8_t *)id, &size);
+}
+
+int cbi_get_factory_calibration_data(uint32_t *calibration_data)
+{
+	uint8_t size = sizeof(*calibration_data);
+
+	return cbi_get_board_info(CBI_TAG_FACTORY_CALIBRATION_DATA,
+				  (uint8_t *)calibration_data, &size);
 }
 
 static enum ec_status hc_cbi_get(struct host_cmd_handler_args *args)
@@ -349,7 +326,7 @@ static enum ec_status hc_cbi_get(struct host_cmd_handler_args *args)
 	uint8_t size = MIN(args->response_max, UINT8_MAX);
 
 	if (p->flag & CBI_GET_RELOAD)
-		cached_read_result = EC_ERROR_CBI_CACHE_INVALID;
+		cbi_invalidate_cache();
 
 	if (cbi_get_board_info(p->tag, args->response, &size))
 		return EC_RES_INVALID_PARAM;
@@ -357,26 +334,25 @@ static enum ec_status hc_cbi_get(struct host_cmd_handler_args *args)
 	args->response_size = size;
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_GET_CROS_BOARD_INFO,
-		     hc_cbi_get,
-		     EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_GET_CROS_BOARD_INFO, hc_cbi_get, EC_VER_MASK(0));
 
-static enum ec_status hc_cbi_set(struct host_cmd_handler_args *args)
+static enum ec_status
+common_cbi_set(const struct __ec_align4 ec_params_set_cbi *p)
 {
-	const struct __ec_align4 ec_params_set_cbi *p = args->params;
-
 	/*
 	 * If we ultimately cannot write to the flash, then fail early unless
 	 * we are explicitly trying to write to the in-memory CBI only
 	 */
-	if (eeprom_is_write_protected() && !(p->flag & CBI_SET_NO_SYNC)) {
-		CPRINTS("Failed to write for WP");
+	if (cbi_config.drv->is_protected() && !(p->flag & CBI_SET_NO_SYNC)) {
+		CPRINTS("Failed to write due to WP");
 		return EC_RES_ACCESS_DENIED;
 	}
 
 #ifndef CONFIG_SYSTEM_UNLOCKED
-	/* These fields are not allowed to be reprogrammed regardless the
-	 * hardware WP state. They're considered as a part of the hardware. */
+	/*
+	 * These fields are not allowed to be reprogrammed regardless the
+	 * hardware WP state. They're considered as a part of the hardware.
+	 */
 	if (p->tag == CBI_TAG_BOARD_VERSION || p->tag == CBI_TAG_OEM_ID)
 		return EC_RES_ACCESS_DENIED;
 #endif
@@ -385,72 +361,79 @@ static enum ec_status hc_cbi_set(struct host_cmd_handler_args *args)
 		memset(cbi, 0, sizeof(cbi));
 		memcpy(head->magic, cbi_magic, sizeof(cbi_magic));
 		head->total_size = sizeof(*head);
-		cached_read_result = EC_SUCCESS;
 	} else {
-		if (read_board_info())
+		if (cbi_read())
 			return EC_RES_ERROR;
 	}
 
-	/* Given data size exceeds the packet size. */
-	if (args->params_size < sizeof(*p) + p->size)
-		return EC_RES_INVALID_PARAM;
-
 	if (cbi_set_board_info(p->tag, p->data, p->size))
 		return EC_RES_INVALID_PARAM;
 
-	/* Whether we're modifying existing data or creating new one,
-	 * we take over the format. */
+	/*
+	 * Whether we're modifying existing data or creating new one,
+	 * we take over the format.
+	 */
 	head->major_version = CBI_VERSION_MAJOR;
 	head->minor_version = CBI_VERSION_MINOR;
 	head->crc = cbi_crc8(head);
+	cache_status = CBI_CACHE_STATUS_SYNCED;
 
 	/* Skip write if client asks so. */
 	if (p->flag & CBI_SET_NO_SYNC)
 		return EC_RES_SUCCESS;
 
 	/* We already checked write protect failure case. */
-	if (write_board_info())
+	if (cbi_write())
 		return EC_RES_ERROR;
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_SET_CROS_BOARD_INFO,
-		     hc_cbi_set,
-		     EC_VER_MASK(0));
 
-#ifdef CONFIG_CMD_CBI
-static void dump_flash(void)
+static enum ec_status hc_cbi_set(struct host_cmd_handler_args *args)
 {
-	uint8_t buf[16];
-	int i;
-	for (i = 0; i < CBI_EEPROM_SIZE; i += sizeof(buf)) {
-		if (read_eeprom(i, buf, sizeof(buf))) {
-			ccprintf("\nFailed to read EEPROM\n");
-			return;
-		}
-		hexdump(buf, sizeof(buf));
-	}
+	const struct __ec_align4 ec_params_set_cbi *p = args->params;
+
+	/* Given data size exceeds the packet size. */
+	if (args->params_size < sizeof(*p) + p->size)
+		return EC_RES_INVALID_PARAM;
+
+	return common_cbi_set(p);
 }
+DECLARE_HOST_COMMAND(EC_CMD_SET_CROS_BOARD_INFO, hc_cbi_set, EC_VER_MASK(0));
 
-static void print_tag(const char * const tag, int rv, const uint32_t *val)
+#ifdef CONFIG_CMD_CBI
+static void print_tag(const char *const tag, int rv, const uint32_t *val)
 {
-	ccprintf(tag);
+	ccprintf("%s", tag);
 	if (rv == EC_SUCCESS && val)
 		ccprintf(": %u (0x%x)\n", *val, *val);
 	else
 		ccprintf(": (Error %d)\n", rv);
 }
 
+static void print_uint64_tag(const char *const tag, int rv,
+			     const uint64_t *lval)
+{
+	ccprintf("%s", tag);
+	if (rv == EC_SUCCESS && lval)
+		ccprintf(": %llu (0x%llx)\n", *(unsigned long long *)lval,
+			 *(unsigned long long *)lval);
+	else
+		ccprintf(": (Error %d)\n", rv);
+}
+
 static void dump_cbi(void)
 {
 	uint32_t val;
+	uint64_t lval;
 
 	/* Ensure we read the latest data from flash. */
-	cached_read_result = EC_ERROR_CBI_CACHE_INVALID;
-	read_board_info();
+	cbi_invalidate_cache();
+	cbi_read();
 
-	if (cached_read_result != EC_SUCCESS) {
-		ccprintf("Cannot Read CBI (Error %d)\n", cached_read_result);
+	if (cbi_get_cache_status() != CBI_CACHE_STATUS_SYNCED) {
+		ccprintf("Cannot Read CBI (Error %d)\n",
+			 cbi_get_cache_status());
 		return;
 	}
 
@@ -464,15 +447,161 @@ static void dump_cbi(void)
 	print_tag("FW_CONFIG", cbi_get_fw_config(&val), &val);
 	print_tag("PCB_SUPPLIER", cbi_get_pcb_supplier(&val), &val);
 	print_tag("SSFC", cbi_get_ssfc(&val), &val);
+	print_uint64_tag("REWORK_ID", cbi_get_rework_id(&lval), &lval);
+}
+
+/*
+ * Space for the set command (does not include data space) plus maximum
+ * possible console input
+ */
+static uint8_t
+	buf[sizeof(struct ec_params_set_cbi) + CONFIG_CONSOLE_INPUT_LINE_SIZE];
+
+static int cc_cbi(int argc, const char **argv)
+{
+	struct __ec_align4 ec_params_set_cbi *setter =
+		(struct __ec_align4 ec_params_set_cbi *)buf;
+	int last_arg;
+	char *e;
+
+	if (argc == 1) {
+		dump_cbi();
+		if (cbi_get_cache_status() == CBI_CACHE_STATUS_SYNCED)
+			hexdump(cbi, CBI_IMAGE_SIZE);
+		return EC_SUCCESS;
+	}
+
+	if (strcasecmp(argv[1], "set") == 0) {
+		if (argc < 5) {
+			ccprintf("Set requires: <tag> <value> <size>\n");
+			return EC_ERROR_PARAM_COUNT;
+		}
+
+		setter->tag = strtoi(argv[2], &e, 0);
+		if (*e)
+			return EC_ERROR_PARAM2;
+
+		if (setter->tag == CBI_TAG_DRAM_PART_NUM ||
+		    setter->tag == CBI_TAG_OEM_NAME ||
+		    setter->tag == CBI_TAG_FUEL_GAUGE_MANUF_NAME ||
+		    setter->tag == CBI_TAG_FUEL_GAUGE_DEVICE_NAME) {
+			setter->size = strlen(argv[3]) + 1;
+			memcpy(setter->data, argv[3], setter->size);
+		} else {
+			uint64_t val = strtoull(argv[3], &e, 0);
+
+			if (*e)
+				return EC_ERROR_PARAM3;
+
+			setter->size = strtoi(argv[4], &e, 0);
+			if (*e)
+				return EC_ERROR_PARAM4;
+
+			if (setter->size < 1) {
+				ccprintf("Set size too small\n");
+				return EC_ERROR_PARAM4;
+			} else if ((setter->size > 8) ||
+				   (setter->size > 4 &&
+				    setter->tag != CBI_TAG_REWORK_ID)) {
+				ccprintf("Set size too large\n");
+				return EC_ERROR_PARAM4;
+			}
+
+			memcpy(setter->data, &val, setter->size);
+		}
+
+		last_arg = 5;
+	} else if (strcasecmp(argv[1], "remove") == 0) {
+		if (argc < 3) {
+			ccprintf("Remove requires: <tag>\n");
+			return EC_ERROR_PARAM_COUNT;
+		}
+
+		setter->tag = strtoi(argv[2], &e, 0);
+		if (*e)
+			return EC_ERROR_PARAM2;
+
+		setter->size = 0;
+		last_arg = 3;
+	} else {
+		return EC_ERROR_PARAM1;
+	}
+
+	setter->flag = 0;
+
+	if (argc > last_arg) {
+		int i;
+
+		for (i = last_arg; i < argc; i++) {
+			if (strcasecmp(argv[i], "init") == 0) {
+				setter->flag |= CBI_SET_INIT;
+			} else if (strcasecmp(argv[i], "skip_write") == 0) {
+				setter->flag |= CBI_SET_NO_SYNC;
+			} else {
+				ccprintf("Invalid additional option\n");
+				return EC_ERROR_PARAM1 + i - 1;
+			}
+		}
+	}
+
+	if (common_cbi_set(setter) == EC_RES_SUCCESS)
+		return EC_SUCCESS;
+
+	return EC_ERROR_UNKNOWN;
 }
+DECLARE_CONSOLE_COMMAND(cbi, cc_cbi,
+			"[set <tag> <value> <size> | "
+			"remove <tag>] [init | skip_write]",
+			"Print or change Cros Board Info from flash");
+#endif /* CONFIG_CMD_CBI */
 
-static int cc_cbi(int argc, char **argv)
+#ifndef CONFIG_AP_POWER_CONTROL
+int cbi_set_fw_config(uint32_t fw_config)
 {
+	/* Check write protect status */
+	if (cbi_config.drv->is_protected())
+		return EC_ERROR_ACCESS_DENIED;
+
+	/* Ensure that CBI has been configured */
+	if (cbi_read())
+		cbi_create();
+
+	/* Update the FW_CONFIG field */
+	cbi_set_board_info(CBI_TAG_FW_CONFIG, (uint8_t *)&fw_config,
+			   sizeof(int));
+
+	/* Update CRC calculation and write to the storage */
+	head->crc = cbi_crc8(head);
+	if (cbi_write())
+		return EC_ERROR_UNKNOWN;
+
 	dump_cbi();
-	dump_flash();
+
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(cbi, cc_cbi, NULL, "Print Cros Board Info from flash");
-#endif /* CONFIG_CMD_CBI */
+
+int cbi_set_ssfc(uint32_t ssfc)
+{
+	/* Check write protect status */
+	if (cbi_config.drv->is_protected())
+		return EC_ERROR_ACCESS_DENIED;
+
+	/* Ensure that CBI has been configured */
+	if (cbi_read())
+		cbi_create();
+
+	/* Update the SSFC field */
+	cbi_set_board_info(CBI_TAG_SSFC, (uint8_t *)&ssfc, sizeof(int));
+
+	/* Update CRC calculation and write to the storage */
+	head->crc = cbi_crc8(head);
+	if (cbi_write())
+		return EC_ERROR_UNKNOWN;
+
+	dump_cbi();
+
+	return EC_SUCCESS;
+}
+#endif
 
 #endif /* !HOST_TOOLS_BUILD */
diff --git a/common/cbi_eeprom.c b/common/cbi_eeprom.c
new file mode 100644
index 0000000000..da7d85f21b
--- /dev/null
+++ b/common/cbi_eeprom.c
@@ -0,0 +1,82 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Support Cros Board Info EEPROM */
+
+#include "console.h"
+#include "cros_board_info.h"
+#include "gpio.h"
+#include "i2c.h"
+#include "system.h"
+#include "timer.h"
+#include "util.h"
+#include "write_protect.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, "CBI " format, ##args)
+
+/*
+ * We allow EEPROMs with page size of 8 or 16. Use 8 to be the most compatible.
+ * This causes a little more overhead for writes, but we are not writing to the
+ * EEPROM outside of the factory process.
+ */
+#define EEPROM_PAGE_WRITE_SIZE 8
+#define EEPROM_PAGE_WRITE_MS 5
+
+static int eeprom_read(uint8_t offset, uint8_t *data, int len)
+{
+	return i2c_read_block(I2C_PORT_EEPROM, I2C_ADDR_EEPROM_FLAGS, offset,
+			      data, len);
+}
+
+static int eeprom_is_write_protected(void)
+{
+	if (IS_ENABLED(CONFIG_BYPASS_CBI_EEPROM_WP_CHECK))
+		return 0;
+
+	return write_protect_is_asserted();
+}
+
+static int eeprom_write(uint8_t *cbi)
+{
+	uint8_t *p = cbi;
+	int rest = ((struct cbi_header *)p)->total_size;
+
+	while (rest > 0) {
+		int size = MIN(EEPROM_PAGE_WRITE_SIZE, rest);
+		int rv;
+
+		rv = i2c_write_block(I2C_PORT_EEPROM, I2C_ADDR_EEPROM_FLAGS,
+				     p - cbi, p, size);
+		if (rv) {
+			CPRINTS("Failed to write for %d", rv);
+			return rv;
+		}
+		/* Wait for internal write cycle completion */
+		msleep(EEPROM_PAGE_WRITE_MS);
+		p += size;
+		rest -= size;
+	}
+
+	return EC_SUCCESS;
+}
+
+#ifdef CONFIG_EEPROM_CBI_WP
+void cbi_latch_eeprom_wp(void)
+{
+	CPRINTS("WP latched");
+	gpio_set_level(GPIO_EC_CBI_WP, 1);
+}
+#endif /* CONFIG_EEPROM_CBI_WP */
+
+const struct cbi_storage_driver eeprom_drv = {
+	.store = eeprom_write,
+	.load = eeprom_read,
+	.is_protected = eeprom_is_write_protected,
+};
+
+const struct cbi_storage_config_t cbi_config = {
+	.storage_type = CBI_STORAGE_TYPE_EEPROM,
+	.drv = &eeprom_drv,
+};
diff --git a/common/cbi_gpio.c b/common/cbi_gpio.c
new file mode 100644
index 0000000000..09e1dd3a18
--- /dev/null
+++ b/common/cbi_gpio.c
@@ -0,0 +1,72 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Support Cros Board Info GPIO */
+
+#include "console.h"
+#include "cros_board_info.h"
+#include "gpio.h"
+#include "system.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, "CBI " format, ##args)
+
+static int cbi_gpio_read(uint8_t offset, uint8_t *data, int len)
+{
+	int board_id;
+	int sku_id;
+	int rv;
+	int err = 0;
+
+	if (cbi_get_cache_status() == CBI_CACHE_STATUS_SYNCED)
+		return EC_SUCCESS;
+
+	cbi_create();
+
+	board_id = system_get_board_version();
+	if (board_id < 0) {
+		CPRINTS("Failed (%d) to get a valid board id", -board_id);
+		err++;
+	} else {
+		rv = cbi_set_board_info(CBI_TAG_BOARD_VERSION,
+					(uint8_t *)&board_id, sizeof(int));
+		if (rv) {
+			CPRINTS("Failed (%d) to set BOARD_VERSION tag", rv);
+			err++;
+		}
+	}
+
+	sku_id = system_get_sku_id();
+	rv = cbi_set_board_info(CBI_TAG_SKU_ID, (uint8_t *)&sku_id,
+				sizeof(int));
+	if (rv) {
+		CPRINTS("Failed (%d) to set SKU_ID tag", rv);
+		err++;
+	}
+
+	if (err > 0)
+		return EC_ERROR_UNKNOWN;
+
+	return EC_SUCCESS;
+}
+
+static int cbi_gpio_is_write_protected(void)
+{
+	/*
+	 * When CBI comes from strapping pins, any attempts for updating CBI
+	 * storage should be rejected.
+	 */
+	return 1;
+}
+
+const struct cbi_storage_driver gpio_drv = {
+	.load = cbi_gpio_read,
+	.is_protected = cbi_gpio_is_write_protected,
+};
+
+const struct cbi_storage_config_t cbi_config = {
+	.storage_type = CBI_STORAGE_TYPE_GPIO,
+	.drv = &gpio_drv,
+};
diff --git a/common/cec.c b/common/cec.c
index 1bc3273c1d..111aa60660 100644
--- a/common/cec.c
+++ b/common/cec.c
@@ -1,14 +1,31 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "atomic.h"
 #include "cec.h"
+#include "chipset.h"
 #include "console.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "mkbp_event.h"
+#include "power_button.h"
+#include "printf.h"
 #include "task.h"
+#include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_CEC, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CEC, format, ## args)
+#ifdef CONFIG_CEC_DEBUG
+#define CPRINTF(format, args...) cprintf(CC_CEC, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CEC, format, ##args)
+#else
+#define CPRINTF(...)
+#define CPRINTS(...)
+#endif
+
+/* Only one port is supported for now */
+#define CEC_PORT 0
+BUILD_ASSERT(CEC_PORT_COUNT == 1);
 
 /*
  * Mutex for the read-offset of the rx queue. Needed since the
@@ -16,6 +33,12 @@
  */
 static struct mutex rx_queue_readoffset_mutex;
 
+/* Queue of completed incoming CEC messages */
+static struct cec_rx_queue cec_rx_queue;
+
+/* Events to send to AP */
+static atomic_t cec_events;
+
 int cec_transfer_get_bit(const struct cec_msg_transfer *transfer)
 {
 	if (transfer->byte >= MAX_CEC_MSG_LEN)
@@ -61,6 +84,62 @@ void cec_rx_queue_flush(struct cec_rx_queue *queue)
 	queue->write_offset = 0;
 }
 
+struct cec_offline_policy cec_default_policy[] = {
+	{
+		.command = CEC_MSG_IMAGE_VIEW_ON,
+		.action = CEC_ACTION_POWER_BUTTON,
+	},
+	{
+		.command = CEC_MSG_TEXT_VIEW_ON,
+		.action = CEC_ACTION_POWER_BUTTON,
+	},
+	/* Terminator */
+	{ 0 },
+};
+
+static enum cec_action cec_find_action(const struct cec_offline_policy *policy,
+				       uint8_t command)
+{
+	if (policy == NULL)
+		return CEC_ACTION_NONE;
+
+	while (policy->command != 0 && policy->action != 0) {
+		if (policy->command == command)
+			return policy->action;
+		policy++;
+	}
+
+	return CEC_ACTION_NONE;
+}
+
+int cec_process_offline_message(struct cec_rx_queue *queue, const uint8_t *msg,
+				uint8_t msg_len)
+{
+	uint8_t command;
+	char str_buf[hex_str_buf_size(msg_len)];
+	int port = CEC_PORT;
+
+	if (!chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		/* Forward to the AP */
+		return EC_ERROR_NOT_HANDLED;
+
+	if (msg_len < 1)
+		return EC_ERROR_INVAL;
+
+	snprintf_hex_buffer(str_buf, sizeof(str_buf), HEX_BUF(msg, msg_len));
+	CPRINTS("MSG: %s", str_buf);
+
+	command = msg[1];
+
+	if (cec_find_action(cec_config[port].offline_policy, command) ==
+	    CEC_ACTION_POWER_BUTTON)
+		/* Equal to PWRBTN_INITIAL_US (for x86). */
+		power_button_simulate_press(200);
+
+	/* Consumed */
+	return EC_SUCCESS;
+}
+
 int cec_rx_queue_push(struct cec_rx_queue *queue, const uint8_t *msg,
 		      uint8_t msg_len)
 {
@@ -75,7 +154,7 @@ int cec_rx_queue_push(struct cec_rx_queue *queue, const uint8_t *msg,
 	queue->buf[offset] = 0;
 	offset = (offset + 1) % CEC_RX_BUFFER_SIZE;
 
-	for (i = 0 ; i < msg_len; i++) {
+	for (i = 0; i < msg_len; i++) {
 		if (offset == queue->read_offset) {
 			/* Buffer full */
 			return EC_ERROR_OVERFLOW;
@@ -101,8 +180,7 @@ int cec_rx_queue_push(struct cec_rx_queue *queue, const uint8_t *msg,
 	return EC_SUCCESS;
 }
 
-int cec_rx_queue_pop(struct cec_rx_queue *queue, uint8_t *msg,
-		     uint8_t *msg_len)
+int cec_rx_queue_pop(struct cec_rx_queue *queue, uint8_t *msg, uint8_t *msg_len)
 {
 	int i;
 
@@ -119,19 +197,197 @@ int cec_rx_queue_pop(struct cec_rx_queue *queue, uint8_t *msg,
 	if (*msg_len == 0 || *msg_len > MAX_CEC_MSG_LEN) {
 		mutex_unlock(&rx_queue_readoffset_mutex);
 		*msg_len = 0;
-		CPRINTF("Invalid CEC msg size: %u\n", *msg_len);
+		cprintf(CC_CEC, "Invalid CEC msg size: %u\n", *msg_len);
 		return -1;
 	}
 
 	queue->read_offset = (queue->read_offset + 1) % CEC_RX_BUFFER_SIZE;
 	for (i = 0; i < *msg_len; i++) {
 		msg[i] = queue->buf[queue->read_offset];
-		queue->read_offset = (queue->read_offset + 1) %
-							CEC_RX_BUFFER_SIZE;
-
+		queue->read_offset =
+			(queue->read_offset + 1) % CEC_RX_BUFFER_SIZE;
 	}
 
 	mutex_unlock(&rx_queue_readoffset_mutex);
 
 	return 0;
 }
+
+static void send_mkbp_event(uint32_t event)
+{
+	atomic_or(&cec_events, event);
+	mkbp_send_event(EC_MKBP_EVENT_CEC_EVENT);
+}
+
+static enum ec_status hc_cec_write(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_cec_write *params = args->params;
+	int port = CEC_PORT;
+
+	if (args->params_size == 0 || args->params_size > MAX_CEC_MSG_LEN)
+		return EC_RES_INVALID_PARAM;
+
+	if (cec_config[port].drv->send(port, params->msg, args->params_size) !=
+	    EC_SUCCESS)
+		return EC_RES_BUSY;
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_CEC_WRITE_MSG, hc_cec_write, EC_VER_MASK(0));
+
+static enum ec_status cec_set_enable(int port, uint8_t enable)
+{
+	if (enable != 0 && enable != 1)
+		return EC_RES_INVALID_PARAM;
+
+	if (cec_config[port].drv->set_enable(port, enable) != EC_SUCCESS)
+		return EC_RES_ERROR;
+
+	if (enable == 0) {
+		/* If disabled, clear the rx queue and events. */
+		memset(&cec_rx_queue, 0, sizeof(struct cec_rx_queue));
+		cec_events = 0;
+	}
+
+	return EC_RES_SUCCESS;
+}
+
+static enum ec_status cec_set_logical_addr(int port, uint8_t logical_addr)
+{
+	if (logical_addr >= CEC_BROADCAST_ADDR &&
+	    logical_addr != CEC_UNREGISTERED_ADDR)
+		return EC_RES_INVALID_PARAM;
+
+	if (cec_config[port].drv->set_logical_addr(port, logical_addr) !=
+	    EC_SUCCESS)
+		return EC_RES_ERROR;
+
+	return EC_RES_SUCCESS;
+}
+
+static enum ec_status hc_cec_set(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_cec_set *params = args->params;
+	int port = CEC_PORT;
+
+	switch (params->cmd) {
+	case CEC_CMD_ENABLE:
+		return cec_set_enable(port, params->val);
+	case CEC_CMD_LOGICAL_ADDRESS:
+		return cec_set_logical_addr(port, params->val);
+	}
+
+	return EC_RES_INVALID_PARAM;
+}
+DECLARE_HOST_COMMAND(EC_CMD_CEC_SET, hc_cec_set, EC_VER_MASK(0));
+
+static enum ec_status hc_cec_get(struct host_cmd_handler_args *args)
+{
+	struct ec_response_cec_get *response = args->response;
+	const struct ec_params_cec_get *params = args->params;
+	int port = CEC_PORT;
+
+	switch (params->cmd) {
+	case CEC_CMD_ENABLE:
+		if (cec_config[port].drv->get_enable(port, &response->val) !=
+		    EC_SUCCESS)
+			return EC_RES_ERROR;
+		break;
+	case CEC_CMD_LOGICAL_ADDRESS:
+		if (cec_config[port].drv->get_logical_addr(
+			    port, &response->val) != EC_SUCCESS)
+			return EC_RES_ERROR;
+		break;
+	default:
+		return EC_RES_INVALID_PARAM;
+	}
+
+	args->response_size = sizeof(*response);
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_CEC_GET, hc_cec_get, EC_VER_MASK(0));
+
+static int cec_get_next_event(uint8_t *out)
+{
+	uint32_t event_out = atomic_clear(&cec_events);
+
+	memcpy(out, &event_out, sizeof(event_out));
+
+	return sizeof(event_out);
+}
+DECLARE_EVENT_SOURCE(EC_MKBP_EVENT_CEC_EVENT, cec_get_next_event);
+
+static int cec_get_next_msg(uint8_t *out)
+{
+	int rv;
+	uint8_t msg_len, msg[MAX_CEC_MSG_LEN];
+
+	rv = cec_rx_queue_pop(&cec_rx_queue, msg, &msg_len);
+	if (rv != 0)
+		return EC_RES_UNAVAILABLE;
+
+	memcpy(out, msg, msg_len);
+
+	return msg_len;
+}
+DECLARE_EVENT_SOURCE(EC_MKBP_EVENT_CEC_MESSAGE, cec_get_next_msg);
+
+static void cec_init(void)
+{
+	int port = CEC_PORT;
+
+	cec_config[port].drv->init(port);
+
+	CPRINTS("CEC initialized");
+}
+DECLARE_HOOK(HOOK_INIT, cec_init, HOOK_PRIO_LAST);
+
+static void handle_received_message(void)
+{
+	int rv;
+	uint8_t *msg;
+	uint8_t msg_len;
+	int port = CEC_PORT;
+
+	if (cec_config[port].drv->get_received_message(port, &msg, &msg_len) !=
+	    EC_SUCCESS) {
+		cprints(CC_CEC, "CEC: failed to get received message");
+		return;
+	}
+
+	if (cec_process_offline_message(&cec_rx_queue, msg, msg_len) ==
+	    EC_SUCCESS) {
+		CPRINTS("Message consumed offline");
+		/* Continue to queue message and notify AP. */
+	}
+	rv = cec_rx_queue_push(&cec_rx_queue, msg, msg_len);
+	if (rv == EC_ERROR_OVERFLOW) {
+		/* Queue full, prefer the most recent msg */
+		cec_rx_queue_flush(&cec_rx_queue);
+		rv = cec_rx_queue_push(&cec_rx_queue, msg, msg_len);
+	}
+	if (rv == EC_SUCCESS)
+		mkbp_send_event(EC_MKBP_EVENT_CEC_MESSAGE);
+}
+
+void cec_task(void *unused)
+{
+	uint32_t events;
+
+	CPRINTF("CEC task starting\n");
+
+	while (1) {
+		events = task_wait_event(-1);
+		if (events & CEC_TASK_EVENT_RECEIVED_DATA) {
+			handle_received_message();
+		}
+		if (events & CEC_TASK_EVENT_OKAY) {
+			send_mkbp_event(EC_MKBP_CEC_SEND_OK);
+			CPRINTS("SEND OKAY");
+		} else if (events & CEC_TASK_EVENT_FAILED) {
+			send_mkbp_event(EC_MKBP_CEC_SEND_FAILED);
+			CPRINTS("SEND FAILED");
+		}
+	}
+}
diff --git a/common/charge_manager.c b/common/charge_manager.c
index bc82859e5d..c5d5543012 100644
--- a/common/charge_manager.c
+++ b/common/charge_manager.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,28 +6,38 @@
 #include "adc.h"
 #include "atomic.h"
 #include "battery.h"
+#include "builtin/assert.h"
 #include "charge_manager.h"
 #include "charge_ramp.h"
-#include "charge_state_v2.h"
+#include "charge_state.h"
 #include "charger.h"
 #include "console.h"
+#include "dps.h"
+#include "extpower.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "host_command.h"
 #include "system.h"
-#include "tcpm.h"
+#include "tcpm/tcpm.h"
 #include "timer.h"
+#include "typec_control.h"
+#include "usb_common.h"
 #include "usb_pd.h"
+#include "usb_pd_dpm_sm.h"
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#ifdef HAS_MOCK_CHARGE_MANAGER
+#error Mock defined HAS_MOCK_CHARGE_MANAGER
+#endif
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
 
 #define POWER(charge_port) ((charge_port.current) * (charge_port.voltage))
 
 /* Timeout for delayed override power swap, allow for 500ms extra */
-#define POWER_SWAP_TIMEOUT (PD_T_SRC_RECOVER_MAX + PD_T_SRC_TURN_ON + \
-			    PD_T_SAFE_0V + 500 * MSEC)
+#define POWER_SWAP_TIMEOUT \
+	(PD_T_SRC_RECOVER_MAX + PD_T_SRC_TURN_ON + PD_T_SAFE_0V + 500 * MSEC)
 
 /*
  * Default charge supplier priority
@@ -61,15 +71,13 @@ __overridable const int supplier_priority[] = {
 	[CHARGE_SUPPLIER_OTHER] = 4,
 	[CHARGE_SUPPLIER_VBUS] = 4,
 #endif
-#ifdef CONFIG_WIRELESS_CHARGER_P9221_R7
-	[CHARGE_SUPPLIER_WPC_BPP] = 5,
-	[CHARGE_SUPPLIER_WPC_EPP] = 5,
-	[CHARGE_SUPPLIER_WPC_GPP] = 5,
-#endif
 
 };
 BUILD_ASSERT(ARRAY_SIZE(supplier_priority) == CHARGE_SUPPLIER_COUNT);
 
+const char *charge_supplier_name[] = { CHARGE_SUPPLIER_NAME };
+BUILD_ASSERT(ARRAY_SIZE(charge_supplier_name) == CHARGE_SUPPLIER_COUNT);
+
 /* Keep track of available charge for each charge port. */
 static struct charge_port_info available_charge[CHARGE_SUPPLIER_COUNT]
 					       [CHARGE_PORT_COUNT];
@@ -99,12 +107,14 @@ static int charge_current = CHARGE_CURRENT_UNINITIALIZED;
 static int charge_current_uncapped = CHARGE_CURRENT_UNINITIALIZED;
 static int charge_voltage;
 static int charge_supplier = CHARGE_SUPPLIER_NONE;
+static int charge_pd_current_uncapped = CHARGE_CURRENT_UNINITIALIZED;
 static int override_port = OVERRIDE_OFF;
 
 static int delayed_override_port = OVERRIDE_OFF;
 static timestamp_t delayed_override_deadline;
 
-static uint8_t source_port_rp[CONFIG_USB_PD_PORT_MAX_COUNT];
+/* Source-out Rp values for TCPMv1 */
+__maybe_unused static uint8_t source_port_rp[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 #ifdef CONFIG_USB_PD_MAX_TOTAL_SOURCE_CURRENT
 /* 3A on one port and 1.5A on the rest */
@@ -139,7 +149,7 @@ enum charge_manager_change_type {
 	CHANGE_DUALROLE,
 };
 
-static int is_pd_port(int port)
+int is_pd_port(int port)
 {
 	return port >= 0 && port < board_get_usb_pd_port_count();
 }
@@ -171,7 +181,6 @@ static int is_valid_port(int port)
 	return 1;
 }
 
-#ifndef TEST_BUILD
 static int is_connected(int port)
 {
 	if (!is_pd_port(port))
@@ -179,7 +188,6 @@ static int is_connected(int port)
 
 	return pd_is_connected(port);
 }
-#endif /* !TEST_BUILD */
 
 #ifndef CONFIG_CHARGE_MANAGER_DRP_CHARGING
 /**
@@ -195,9 +203,8 @@ static int is_connected(int port)
  */
 static int charge_manager_spoof_dualrole_capability(void)
 {
-	return (system_get_image_copy() == EC_IMAGE_RO &&
-		system_is_locked()) || !left_safe_mode;
-
+	return (system_get_image_copy() == EC_IMAGE_RO && system_is_locked()) ||
+	       !left_safe_mode;
 }
 #endif /* !CONFIG_CHARGE_MANAGER_DRP_CHARGING */
 
@@ -222,11 +229,11 @@ static void charge_manager_init(void)
 			charge_ceil[i][j] = CHARGE_CEIL_NONE;
 		if (!is_pd_port(i))
 			dualrole_capability[i] = CAP_DEDICATED;
-		if (is_pd_port(i))
+		if (is_pd_port(i) && !IS_ENABLED(CONFIG_USB_PD_TCPMV2))
 			source_port_rp[i] = CONFIG_USB_PD_PULLUP;
 	}
 }
-DECLARE_HOOK(HOOK_INIT, charge_manager_init, HOOK_PRIO_CHARGE_MANAGER_INIT);
+DECLARE_HOOK(HOOK_INIT, charge_manager_init, HOOK_PRIO_INIT_CHARGE_MANAGER);
 
 /**
  * Check if the charge manager is seeded.
@@ -248,9 +255,9 @@ static int charge_manager_is_seeded(void)
 			if (!is_valid_port(j))
 				continue;
 			if (available_charge[i][j].current ==
-			    CHARGE_CURRENT_UNINITIALIZED ||
+				    CHARGE_CURRENT_UNINITIALIZED ||
 			    available_charge[i][j].voltage ==
-			    CHARGE_VOLTAGE_UNINITIALIZED)
+				    CHARGE_VOLTAGE_UNINITIALIZED)
 				return 0;
 		}
 	}
@@ -258,14 +265,18 @@ static int charge_manager_is_seeded(void)
 	return 1;
 }
 
-#ifndef TEST_BUILD
+int charge_manager_get_pd_current_uncapped(void)
+{
+	return charge_pd_current_uncapped;
+}
+
 /**
  * Get the maximum charge current for a port.
  *
  * @param port	Charge port.
  * @return	Charge current (mA).
  */
-static int charge_manager_get_source_current(int port)
+__maybe_unused static int charge_manager_get_source_current(int port)
 {
 	if (!is_pd_port(port))
 		return 0;
@@ -310,37 +321,128 @@ static enum charge_supplier find_supplier(int port, enum charge_supplier sup,
 	return sup;
 }
 
-/**
- * Fills passed power_info structure with current info about the passed port.
- *
- * @param port	Charge port.
- * @param r	USB PD power info to be updated.
- */
-static void charge_manager_fill_power_info(int port,
-	struct ec_response_usb_pd_power_info *r)
+static enum charge_supplier get_current_supplier(int port)
 {
-	int sup = CHARGE_SUPPLIER_NONE;
+	enum charge_supplier supplier = CHARGE_SUPPLIER_NONE;
 
 	/* Determine supplier information to show. */
 	if (port == charge_port) {
-		sup = charge_supplier;
+		supplier = charge_supplier;
 	} else {
 		/* Consider available current */
-		sup = find_supplier(port, sup, 0);
-		if (sup == CHARGE_SUPPLIER_NONE)
+		supplier = find_supplier(port, supplier, 0);
+		if (supplier == CHARGE_SUPPLIER_NONE)
 			/* Ignore available current */
-			sup = find_supplier(port, sup, -1);
+			supplier = find_supplier(port, supplier, -1);
 	}
 
-	/* Fill in power role */
+	return supplier;
+}
+static enum usb_power_roles
+get_current_power_role(int port, enum charge_supplier supplier)
+{
+	enum usb_power_roles role;
 	if (charge_port == port)
-		r->role = USB_PD_PORT_POWER_SINK;
+		role = USB_PD_PORT_POWER_SINK;
 	else if (is_connected(port) && !is_sink(port))
-		r->role = USB_PD_PORT_POWER_SOURCE;
-	else if (sup != CHARGE_SUPPLIER_NONE)
-		r->role = USB_PD_PORT_POWER_SINK_NOT_CHARGING;
+		role = USB_PD_PORT_POWER_SOURCE;
+	else if (supplier != CHARGE_SUPPLIER_NONE)
+		role = USB_PD_PORT_POWER_SINK_NOT_CHARGING;
 	else
-		r->role = USB_PD_PORT_POWER_DISCONNECTED;
+		role = USB_PD_PORT_POWER_DISCONNECTED;
+	return role;
+}
+
+__overridable int board_get_vbus_voltage(int port)
+{
+	return 0;
+}
+
+static int get_vbus_voltage(int port, enum usb_power_roles current_role)
+{
+	int voltage_mv;
+
+	/*
+	 * If we are sourcing power or sinking but not charging, then VBUS must
+	 * be 5V. If we are charging, then read VBUS ADC.
+	 */
+	if (current_role == USB_PD_PORT_POWER_SINK_NOT_CHARGING) {
+		voltage_mv = 5000;
+	} else {
+#if defined(CONFIG_USB_PD_VBUS_MEASURE_CHARGER)
+		/*
+		 * Try to get VBUS from the charger. If that fails, default to 0
+		 * mV.
+		 */
+		if (charger_get_vbus_voltage(port, &voltage_mv))
+			voltage_mv = 0;
+#elif defined(CONFIG_USB_PD_VBUS_MEASURE_TCPC)
+		voltage_mv = tcpc_get_vbus_voltage(port);
+#elif defined(CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT)
+		voltage_mv = adc_read_channel(board_get_vbus_adc(port));
+#elif defined(CONFIG_USB_PD_VBUS_MEASURE_NOT_PRESENT)
+		/* No VBUS ADC channel - voltage is unknown */
+		voltage_mv = 0;
+#elif defined(CONFIG_USB_PD_VBUS_MEASURE_BY_BOARD)
+		voltage_mv = board_get_vbus_voltage(port);
+#else
+		/* There is a single ADC that measures joint Vbus */
+		voltage_mv = adc_read_channel(ADC_VBUS);
+#endif
+	}
+	return voltage_mv;
+}
+
+int charge_manager_get_vbus_voltage(int port)
+{
+	return get_vbus_voltage(
+		port, get_current_power_role(port, get_current_supplier(port)));
+}
+
+#ifdef CONFIG_CMD_VBUS
+static int command_vbus(int argc, const char **argv)
+{
+	/* port = -1 to print all the ports */
+	int port = -1;
+	int vbus, vsys;
+
+	if (argc == 2)
+		port = atoi(argv[1]);
+
+	ccprintf("       VBUS     VSYS\n");
+	for (int i = 0; i < CHARGE_PORT_COUNT; i++) {
+		if (port < 0 || i == port) {
+			vbus = charge_manager_get_vbus_voltage(i);
+			if (charger_get_vsys_voltage(i, &vsys))
+				vsys = -1;
+			ccprintf("  P%d %6dmV ", i, vbus);
+			if (vsys >= 0)
+				ccprintf("%6dmV\n", vsys);
+			else
+				ccprintf("(unknown)\n");
+		}
+	}
+
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(vbus, command_vbus, "[port]",
+			"Print VBUS & VSYS of the given port");
+#endif
+
+/**
+ * Fills passed power_info structure with current info about the passed port.
+ *
+ * @param port	Charge port.
+ * @param r	USB PD power info to be updated.
+ */
+static void
+charge_manager_fill_power_info(int port,
+			       struct ec_response_usb_pd_power_info *r)
+{
+	enum charge_supplier sup = get_current_supplier(port);
+
+	/* Fill in power role */
+	r->role = get_current_power_role(port, sup);
 
 	/* Is port partner dual-role capable */
 	r->dualrole = (dualrole_capability[port] == CAP_DUALROLE);
@@ -352,15 +454,21 @@ static void charge_manager_fill_power_info(int port,
 			r->meas.voltage_max = 0;
 			r->meas.voltage_now =
 				r->role == USB_PD_PORT_POWER_SOURCE ? 5000 : 0;
-			r->meas.current_max =
-				charge_manager_get_source_current(port);
+			/* TCPMv2 tracks source-out current in the DPM */
+			if (IS_ENABLED(CONFIG_USB_PD_TCPMV2))
+				r->meas.current_max =
+					dpm_get_source_current(port);
+			else
+				r->meas.current_max =
+					charge_manager_get_source_current(port);
 			r->max_power = 0;
 		} else {
 			r->type = USB_CHG_TYPE_NONE;
 			board_fill_source_power_info(port, r);
 		}
 	} else {
-		int use_ramp_current;
+		uint32_t max_mv, max_ma, pdo, unused;
+
 		switch (sup) {
 		case CHARGE_SUPPLIER_PD:
 			r->type = USB_CHG_TYPE_PD;
@@ -386,30 +494,32 @@ static void charge_manager_fill_power_info(int port,
 			r->type = USB_CHG_TYPE_VBUS;
 			break;
 #endif
-#ifdef CONFIG_WIRELESS_CHARGER_P9221_R7
-		/*
-		 * Todo:need kernel add wpc device node in power_supply
-		 * before that use USB_CHG_TYPE_PROPRIETARY to present WPC.
-		 */
-		case CHARGE_SUPPLIER_WPC_BPP:
-		case CHARGE_SUPPLIER_WPC_EPP:
-		case CHARGE_SUPPLIER_WPC_GPP:
-			r->type = USB_CHG_TYPE_PROPRIETARY;
-			break;
-#endif
 #if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
 		case CHARGE_SUPPLIER_DEDICATED:
 			r->type = USB_CHG_TYPE_DEDICATED;
 			break;
 #endif
 		default:
-#ifdef CONFIG_WIRELESS_CHARGER_P9221_R7
-			r->type = USB_CHG_TYPE_VBUS;
-#else
 			r->type = USB_CHG_TYPE_OTHER;
-#endif
 		}
-		r->meas.voltage_max = available_charge[sup][port].voltage;
+
+		if (IS_ENABLED(CONFIG_USB_PD_DPS) && dps_is_enabled() &&
+		    sup == CHARGE_SUPPLIER_PD) {
+			/*
+			 * Returns the maximum power the system can request when
+			 * DPS enabled. This is to prevent the system think it's
+			 * using a low power charger.
+			 */
+			pd_find_pdo_index(pd_get_src_cap_cnt(port),
+					  pd_get_src_caps(port),
+					  pd_get_max_voltage(), &pdo);
+			pd_extract_pdo_power(pdo, &max_ma, &max_mv, &unused);
+		} else {
+			max_mv = available_charge[sup][port].voltage;
+			max_ma = available_charge[sup][port].current;
+		}
+
+		r->meas.voltage_max = max_mv;
 
 		/*
 		 * Report unknown charger CHARGE_DETECT_DELAY after supplier
@@ -423,19 +533,13 @@ static void charge_manager_fill_power_info(int port,
 		 * lose power again).
 		 */
 #ifdef CONFIG_BATTERY
-		if (get_time().val < registration_time[port].val +
-				     CHARGE_DETECT_DELAY)
+		if (get_time().val <
+		    registration_time[port].val + CHARGE_DETECT_DELAY)
 			r->type = USB_CHG_TYPE_UNKNOWN;
 #endif
 
 #if defined(HAS_TASK_CHG_RAMP) || defined(CONFIG_CHARGE_RAMP_HW)
-		/* Read ramped current if active charging port */
-		use_ramp_current =
-			(charge_port == port) && chg_ramp_allowed(port, sup);
-#else
-		use_ramp_current = 0;
-#endif
-		if (use_ramp_current) {
+		if ((charge_port == port) && chg_ramp_allowed(port, sup)) {
 			/* Current limit is output of ramp module */
 			r->meas.current_lim = chg_ramp_get_current_limit();
 
@@ -448,48 +552,21 @@ static void charge_manager_fill_power_info(int port,
 			 * If ramp is not allowed, max current is just the
 			 * available charge current.
 			 */
-			r->meas.current_max = chg_ramp_is_stable() ?
-				r->meas.current_lim : chg_ramp_max(port, sup,
-					available_charge[sup][port].current);
-
-			r->max_power =
-				r->meas.current_max * r->meas.voltage_max;
+			r->meas.current_max =
+				chg_ramp_is_stable() ?
+					r->meas.current_lim :
+					chg_ramp_max(port, sup, max_ma);
 		} else {
-			r->meas.current_max = r->meas.current_lim =
-				available_charge[sup][port].current;
-			r->max_power = POWER(available_charge[sup][port]);
+			r->meas.current_max = r->meas.current_lim = max_ma;
 		}
-
-		/*
-		 * If we are sourcing power, or sinking but not charging, then
-		 * VBUS must be 5V. If we are charging, then read VBUS ADC.
-		 */
-		if (r->role == USB_PD_PORT_POWER_SINK_NOT_CHARGING)
-			r->meas.voltage_now = 5000;
-		else {
-#if defined(CONFIG_USB_PD_VBUS_MEASURE_CHARGER)
-			int voltage;
-
-			if (charger_get_vbus_voltage(port, &voltage))
-				r->meas.voltage_now = 0;
-			else
-				r->meas.voltage_now = voltage;
-#elif defined(CONFIG_USB_PD_VBUS_MEASURE_TCPC)
-			r->meas.voltage_now = tcpc_get_vbus_voltage(port);
-#elif defined(CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT)
-			r->meas.voltage_now =
-				adc_read_channel(board_get_vbus_adc(port));
-#elif defined(CONFIG_USB_PD_VBUS_MEASURE_NOT_PRESENT)
-			/* No VBUS ADC channel - voltage is unknown */
-			r->meas.voltage_now = 0;
 #else
-			/* There is a single ADC that measures joint Vbus */
-			r->meas.voltage_now = adc_read_channel(ADC_VBUS);
+		r->meas.current_max = r->meas.current_lim = max_ma;
 #endif
-		}
+		r->max_power = r->meas.current_max * r->meas.voltage_max;
+
+		r->meas.voltage_now = get_vbus_voltage(port, r->role);
 	}
 }
-#endif /* TEST_BUILD */
 
 #ifdef CONFIG_USB_PD_LOGGING
 /**
@@ -515,8 +592,8 @@ void charge_manager_save_log(int port)
 		 (pinfo.dualrole ? CHARGE_FLAGS_DUAL_ROLE : 0);
 
 	pd_log_event(PD_EVENT_MCU_CHARGE,
-		     PD_LOG_PORT_SIZE(port, sizeof(pinfo.meas)),
-		     flags, &pinfo.meas);
+		     PD_LOG_PORT_SIZE(port, sizeof(pinfo.meas)), flags,
+		     &pinfo.meas);
 }
 #endif /* CONFIG_USB_PD_LOGGING */
 
@@ -579,9 +656,10 @@ static void charge_manager_get_best_charge_port(int *new_port,
 	if (override_port != OVERRIDE_DONT_CHARGE) {
 		/*
 		 * Charge supplier selection logic:
-		 * 1. Prefer higher priority supply.
-		 * 2. Prefer higher power over lower in case priority is tied.
-		 * 3. Prefer current charge port over new port in case (1)
+		 * 1. Prefer DPS charge port.
+		 * 2. Prefer higher priority supply.
+		 * 3. Prefer higher power over lower in case priority is tied.
+		 * 4. Prefer current charge port over new port in case (1)
 		 *    and (2) are tied.
 		 * available_charge can be changed at any time by other tasks,
 		 * so make no assumptions about its consistency.
@@ -605,8 +683,7 @@ static void charge_manager_get_best_charge_port(int *new_port,
 				 * charge on another override port.
 				 */
 				if (override_port != OVERRIDE_OFF &&
-				    override_port == port &&
-				    override_port != j)
+				    override_port == port && override_port != j)
 					continue;
 
 #ifndef CONFIG_CHARGE_MANAGER_DRP_CHARGING
@@ -623,31 +700,44 @@ static void charge_manager_get_best_charge_port(int *new_port,
 				candidate_port_power =
 					POWER(available_charge[i][j]);
 
-				/* Select if no supplier chosen yet. */
-				if (supplier == CHARGE_SUPPLIER_NONE ||
-				/* ..or if supplier priority is higher. */
-				    supplier_priority[i] <
-				    supplier_priority[supplier] ||
-				/* ..or if this is our override port. */
-				   (j == override_port &&
-				    port != override_port) ||
-				/* ..or if priority is tied and.. */
-				   (supplier_priority[i] ==
-				    supplier_priority[supplier] &&
-				/* candidate port can supply more power or.. */
-				   (candidate_port_power > best_port_power ||
-				/*
-				 * candidate port is the active port and can
-				 * supply the same amount of power.
-				 */
-				   (candidate_port_power == best_port_power &&
-				    charge_port == j)))) {
+				/* Select DPS port if provided. */
+				if (IS_ENABLED(CONFIG_USB_PD_DPS) &&
+				    override_port == OVERRIDE_OFF &&
+				    i == CHARGE_SUPPLIER_PD &&
+				    j == dps_get_charge_port()) {
+					supplier = i;
+					port = j;
+					break;
+					/* Select if no supplier chosen yet. */
+				} else if (supplier == CHARGE_SUPPLIER_NONE ||
+					   /* ..or if supplier priority is
+					      higher. */
+					   supplier_priority[i] <
+						   supplier_priority[supplier] ||
+					   /* ..or if this is our override port.
+					    */
+					   (j == override_port &&
+					    port != override_port) ||
+					   /* ..or if priority is tied and.. */
+					   (supplier_priority[i] ==
+						    supplier_priority[supplier] &&
+					    /* candidate port can supply more
+					       power or.. */
+					    (candidate_port_power >
+						     best_port_power ||
+					     /*
+					      * candidate port is the active
+					      * port and can supply the same
+					      * amount of power.
+					      */
+					     (candidate_port_power ==
+						      best_port_power &&
+					      charge_port == j)))) {
 					supplier = i;
 					port = j;
 					best_port_power = candidate_port_power;
 				}
 			}
-
 	}
 
 #ifdef CONFIG_BATTERY
@@ -655,8 +745,7 @@ static void charge_manager_get_best_charge_port(int *new_port,
 	 * if no battery present then retain same charge port
 	 * and charge supplier to avoid the port switching
 	 */
-	if (charge_port != CHARGE_SUPPLIER_NONE &&
-	    charge_port != port &&
+	if (charge_port != CHARGE_SUPPLIER_NONE && charge_port != port &&
 	    (battery_is_present() == BP_NO ||
 	     (battery_is_present() == BP_YES &&
 	      battery_is_cut_off() != BATTERY_CUTOFF_STATE_NORMAL))) {
@@ -699,11 +788,24 @@ static void charge_manager_refresh(void)
 		 * the port, for example, if the port has become a charge
 		 * source.
 		 */
-		if ((active_charge_port_initialized &&
-		     new_port == charge_port &&
-		     new_supplier == charge_supplier) ||
-		     board_set_active_charge_port(new_port) == EC_SUCCESS)
+		if (active_charge_port_initialized && new_port == charge_port &&
+		    new_supplier == charge_supplier)
+			break;
+
+		/*
+		 * For OCPC systems, reset the OCPC state to prevent current
+		 * spikes.
+		 */
+		if (IS_ENABLED(CONFIG_OCPC)) {
+			charge_set_active_chg_chip(new_port);
+			trigger_ocpc_reset();
+		}
+
+		if (board_set_active_charge_port(new_port) == EC_SUCCESS) {
+			if (IS_ENABLED(CONFIG_EXTPOWER))
+				board_check_extpower();
 			break;
+		}
 
 		/* 'Dont charge' request must be accepted. */
 		ASSERT(new_port != CHARGE_PORT_NONE);
@@ -720,10 +822,6 @@ static void charge_manager_refresh(void)
 
 	active_charge_port_initialized = 1;
 
-	/* Set the active charger chip based upon the selected charge port. */
-	if (IS_ENABLED(CONFIG_OCPC))
-		charge_set_active_chg_chip(new_port);
-
 	/*
 	 * Clear override if it wasn't selected as the 'best' port -- it means
 	 * that no charge is available on the port, or the port was rejected.
@@ -732,8 +830,12 @@ static void charge_manager_refresh(void)
 		override_port = OVERRIDE_OFF;
 
 	if (new_supplier == CHARGE_SUPPLIER_NONE) {
+#ifdef CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT
+		new_charge_current = CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT;
+#else
 		new_charge_current = 0;
-		new_charge_current_uncapped = 0;
+#endif
+		new_charge_current_uncapped = new_charge_current;
 		new_charge_voltage = 0;
 	} else {
 		new_charge_current_uncapped =
@@ -751,8 +853,8 @@ static void charge_manager_refresh(void)
 		/* Enforce port charge ceiling. */
 		ceil = charge_manager_get_ceil(new_port);
 		if (left_safe_mode && ceil != CHARGE_CEIL_NONE)
-			new_charge_current = MIN(ceil,
-						 new_charge_current_uncapped);
+			new_charge_current =
+				MIN(ceil, new_charge_current_uncapped);
 		else
 			new_charge_current = new_charge_current_uncapped;
 
@@ -760,29 +862,45 @@ static void charge_manager_refresh(void)
 			available_charge[new_supplier][new_port].voltage;
 	}
 
+	/*
+	 * Record the PD current limit to prevent from over-sinking
+	 * the charger.
+	 */
+	if (new_supplier == CHARGE_SUPPLIER_PD)
+		charge_pd_current_uncapped = new_charge_current_uncapped;
+	else
+		charge_pd_current_uncapped = CHARGE_CURRENT_UNINITIALIZED;
+
 	/* Change the charge limit + charge port/supplier if modified. */
 	if (new_port != charge_port || new_charge_current != charge_current ||
 	    new_supplier != charge_supplier) {
 #ifdef HAS_TASK_CHG_RAMP
-		chg_ramp_charge_supplier_change(
-				new_port, new_supplier, new_charge_current,
-				registration_time[new_port],
-				new_charge_voltage);
+		chg_ramp_charge_supplier_change(new_port, new_supplier,
+						new_charge_current,
+						registration_time[new_port],
+						new_charge_voltage);
 #else
 #ifdef CONFIG_CHARGE_RAMP_HW
 		/* Enable or disable charge ramp */
 		charger_set_hw_ramp(chg_ramp_allowed(new_port, new_supplier));
 #endif
 		board_set_charge_limit(new_port, new_supplier,
-					new_charge_current,
-					new_charge_current_uncapped,
-					new_charge_voltage);
+				       new_charge_current,
+				       new_charge_current_uncapped,
+				       new_charge_voltage);
 #endif /* HAS_TASK_CHG_RAMP */
 
 		power_changed = 1;
 
 		CPRINTS("CL: p%d s%d i%d v%d", new_port, new_supplier,
 			new_charge_current, new_charge_voltage);
+
+		/*
+		 * (b:192638664) We try to check AC OK again to avoid
+		 * unsuccessful detection in the initial detection.
+		 */
+		if (IS_ENABLED(CONFIG_EXTPOWER))
+			board_check_extpower();
 	}
 
 	/*
@@ -834,14 +952,64 @@ static void charge_manager_refresh(void)
 #endif
 
 	/* New power requests must be set only after updating the globals. */
-	if (is_pd_port(updated_new_port))
-		pd_set_new_power_request(updated_new_port);
+	if (is_pd_port(updated_new_port)) {
+		/* Check if we can get requested voltage/current */
+		if ((IS_ENABLED(CONFIG_USB_PD_TCPMV1) &&
+		     IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE)) ||
+		    (IS_ENABLED(CONFIG_USB_PD_TCPMV2) &&
+		     IS_ENABLED(CONFIG_USB_PE_SM))) {
+			uint32_t pdo;
+			uint32_t max_voltage;
+			uint32_t max_current;
+			uint32_t unused;
+			bool new_req = false;
+			/*
+			 * Check if new voltage/current is different
+			 * than requested. If yes, send new power request
+			 */
+			if (pd_get_requested_voltage(updated_new_port) !=
+				    charge_voltage ||
+			    pd_get_requested_current(updated_new_port) !=
+				    charge_current_uncapped)
+				new_req = true;
+
+			if (IS_ENABLED(CONFIG_USB_PD_DPS) && dps_is_enabled()) {
+				/* Fall-through. DPS control sink voltage */
+			} else {
+				/*
+				 * Check if we can get more power from this
+				 * port. If yes, send new power request
+				 */
+				pd_find_pdo_index(
+					pd_get_src_cap_cnt(updated_new_port),
+					pd_get_src_caps(updated_new_port),
+					pd_get_max_voltage(), &pdo);
+				pd_extract_pdo_power(pdo, &max_current,
+						     &max_voltage, &unused);
+
+				if (charge_voltage != max_voltage ||
+				    charge_current_uncapped != max_current)
+					new_req = true;
+			}
+
+			if (new_req)
+				pd_set_new_power_request(updated_new_port);
+		} else {
+			/*
+			 * Functions for getting requested voltage/current
+			 * are not available. Send new power request.
+			 */
+			pd_set_new_power_request(updated_new_port);
+		}
+	}
 	if (is_pd_port(updated_old_port))
 		pd_set_new_power_request(updated_old_port);
 
-	if (power_changed)
+	if (power_changed) {
+		hook_notify(HOOK_POWER_SUPPLY_CHANGE);
 		/* notify host of power info change */
 		pd_send_host_event(PD_EVENT_POWER_CHANGE);
+	}
 }
 DECLARE_DEFERRED(charge_manager_refresh);
 
@@ -874,8 +1042,7 @@ DECLARE_DEFERRED(charger_detect_debounced);
  * @param charge		Charge port current / voltage.
  */
 static void charge_manager_make_change(enum charge_manager_change_type change,
-				       int supplier,
-				       int port,
+				       int supplier, int port,
 				       const struct charge_port_info *charge)
 {
 	int i;
@@ -891,9 +1058,8 @@ static void charge_manager_make_change(enum charge_manager_change_type change,
 	case CHANGE_CHARGE:
 		/* Ignore changes where charge is identical */
 		if (available_charge[supplier][port].current ==
-		    charge->current &&
-		    available_charge[supplier][port].voltage ==
-		    charge->voltage)
+			    charge->current &&
+		    available_charge[supplier][port].voltage == charge->voltage)
 			return;
 		if (charge->current > 0 &&
 		    available_charge[supplier][port].current == 0)
@@ -927,12 +1093,13 @@ static void charge_manager_make_change(enum charge_manager_change_type change,
 	}
 
 	/* Remove override when a charger is plugged */
-	if (clear_override && override_port != port
+	if (clear_override &&
+	    override_port != port
 #ifndef CONFIG_CHARGE_MANAGER_DRP_CHARGING
 	    /* only remove override when it's a dedicated charger */
 	    && dualrole_capability[port] == CAP_DEDICATED
 #endif
-	    ) {
+	) {
 		override_port = OVERRIDE_OFF;
 		if (delayed_override_port != OVERRIDE_OFF) {
 			delayed_override_port = OVERRIDE_OFF;
@@ -960,7 +1127,7 @@ static void charge_manager_make_change(enum charge_manager_change_type change,
 		/*
 		 * If we have a charge on our delayed override port within
 		 * the deadline, make it our override port.
-		*/
+		 */
 		if (port == delayed_override_port && charge->current > 0 &&
 		    is_sink(delayed_override_port) &&
 		    get_time().val < delayed_override_deadline.val) {
@@ -1045,11 +1212,10 @@ void typec_set_input_current_limit(int port, typec_current_t max_ma,
 						     NULL);
 }
 
-void charge_manager_update_charge(int supplier,
-				  int port,
+void charge_manager_update_charge(int supplier, int port,
 				  const struct charge_port_info *charge)
 {
-	struct charge_port_info zero = {0};
+	struct charge_port_info zero = { 0 };
 	if (!charge)
 		charge = &zero;
 	charge_manager_make_change(CHANGE_CHARGE, supplier, port, charge);
@@ -1068,11 +1234,31 @@ void charge_manager_update_dualrole(int port, enum dualrole_capabilities cap)
 }
 
 #ifdef CONFIG_CHARGE_MANAGER_SAFE_MODE
+__overridable int board_get_leave_safe_mode_delay_ms(void)
+{
+	return 500;
+}
+
 void charge_manager_leave_safe_mode(void)
 {
 	if (left_safe_mode)
 		return;
 
+	/*
+	 * Sometimes the fuel gauge will report that it has
+	 * sufficient state of charge and remaining capacity,
+	 * but in actuality it doesn't.  When the EC sees that
+	 * information, it trusts it and leaves charge manager
+	 * safe mode.  Doing so will allow CHARGE_PORT_NONE to
+	 * be selected, thereby cutting off the input FETs.
+	 * When the battery cannot provide the charge it claims,
+	 * the system loses power, shuts down, and the battery
+	 * is not charged even though the charger is plugged in.
+	 * By waiting 500ms, we can avoid the selection of
+	 * CHARGE_PORT_NONE around init time and not cut off the
+	 * input FETs.
+	 */
+	msleep(board_get_leave_safe_mode_delay_ms());
 	CPRINTS("%s()", __func__);
 	cflush();
 	left_safe_mode = 1;
@@ -1099,15 +1285,29 @@ void charge_manager_force_ceil(int port, int ceil)
 	 * Force our input current to ceil if we're exceeding it, without
 	 * waiting for our deferred task to run.
 	 */
-	if (left_safe_mode && port == charge_port && ceil < charge_current)
+	if (left_safe_mode && port == charge_port && ceil < charge_current) {
 		board_set_charge_limit(port, CHARGE_SUPPLIER_PD, ceil,
 				       charge_current_uncapped, charge_voltage);
-
-	/*
-	 * Now inform charge_manager so it stays in sync with the state of
-	 * the world.
-	 */
-	charge_manager_set_ceil(port, CEIL_REQUESTOR_PD, ceil);
+		/* Enforcing charge_ceil here prevents race conditions between
+		 * the hook task and the PD task, which could occur if
+		 * charge_ceil is changed while a deferred
+		 * charge_manager_refresh is in process.
+		 * charge_manager_force_ceil's premise as an API is to lower
+		 * the ceil for the current charge port. It doesn't need to find
+		 * a better port, supplier, or PDO. That means most of
+		 * charge_manager_refresh doesn't need to be called.
+		 */
+		charge_current = ceil;
+		charge_ceil[port][CEIL_REQUESTOR_PD] = ceil;
+		CPRINTS("CL: p%d s%d i%d v%d (forced)", port,
+			CHARGE_SUPPLIER_PD, charge_current, charge_voltage);
+	} else {
+		/*
+		 * Inform charge_manager so it stays in sync with the state
+		 * of the world.
+		 */
+		charge_manager_set_ceil(port, CEIL_REQUESTOR_PD, ceil);
+	}
 }
 
 int charge_manager_set_override(int port)
@@ -1131,8 +1331,8 @@ int charge_manager_set_override(int port)
 		if (override_port != port) {
 			override_port = port;
 			if (charge_manager_is_seeded())
-				hook_call_deferred(
-					&charge_manager_refresh_data, 0);
+				hook_call_deferred(&charge_manager_refresh_data,
+						   0);
 		}
 	}
 	/*
@@ -1140,13 +1340,13 @@ int charge_manager_set_override(int port)
 	 * power swap and set the delayed override for swap completion.
 	 */
 	else if (!is_sink(port) && dualrole_capability[port] == CAP_DUALROLE) {
-		delayed_override_deadline.val = get_time().val +
-						POWER_SWAP_TIMEOUT;
+		delayed_override_deadline.val =
+			get_time().val + POWER_SWAP_TIMEOUT;
 		delayed_override_port = port;
 		hook_call_deferred(&charge_override_timeout_data,
 				   POWER_SWAP_TIMEOUT);
 		pd_request_power_swap(port);
-	/* Can't charge from requested port -- return error. */
+		/* Can't charge from requested port -- return error. */
 	} else
 		retval = EC_ERROR_INVAL;
 
@@ -1198,11 +1398,13 @@ int charge_manager_get_power_limit_uw(void)
 		return current_ma * voltage_mv;
 }
 
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
+#if defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) && \
+	!defined(CONFIG_USB_PD_TCPMV2)
+/* Note: this functionality is a part of the TCPMv2 Device Poicy Manager */
 
 /* Bitmap of ports used as power source */
 static volatile uint32_t source_port_bitmap;
-BUILD_ASSERT(sizeof(source_port_bitmap)*8 >= CONFIG_USB_PD_PORT_MAX_COUNT);
+BUILD_ASSERT(sizeof(source_port_bitmap) * 8 >= CONFIG_USB_PD_PORT_MAX_COUNT);
 
 static inline int has_other_active_source(int port)
 {
@@ -1233,7 +1435,7 @@ static int can_supply_max_current(int port)
 		if (p == port)
 			continue;
 		if (source_port_rp[p] ==
-				CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT)
+		    CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT)
 			return 0;
 	}
 	return 1;
@@ -1248,9 +1450,9 @@ void charge_manager_source_port(int port, int enable)
 	int p, rp;
 
 	if (enable)
-		deprecated_atomic_or(&source_port_bitmap, 1 << port);
+		atomic_or((atomic_t *)&source_port_bitmap, 1 << port);
 	else
-		deprecated_atomic_clear_bits(&source_port_bitmap, 1 << port);
+		atomic_clear_bits((atomic_t *)&source_port_bitmap, 1 << port);
 
 	/* No change, exit early. */
 	if (prev_bitmap == source_port_bitmap)
@@ -1259,8 +1461,8 @@ void charge_manager_source_port(int port, int enable)
 	/* Set port limit according to policy */
 	for (p = 0; p < board_get_usb_pd_port_count(); p++) {
 		rp = can_supply_max_current(p) ?
-				CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT :
-				CONFIG_USB_PD_PULLUP;
+			     CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT :
+			     CONFIG_USB_PD_PULLUP;
 		source_port_rp[p] = rp;
 
 #ifdef CONFIG_USB_PD_LOGGING
@@ -1287,9 +1489,8 @@ int charge_manager_get_source_pdo(const uint32_t **src_pdo, const int port)
 	*src_pdo = pd_src_pdo;
 	return pd_src_pdo_cnt;
 }
-#endif /* CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT */
+#endif /* CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT && !CONFIG_USB_PD_TCPMV2 */
 
-#ifndef TEST_BUILD
 static enum ec_status hc_pd_power_info(struct host_cmd_handler_args *args)
 {
 	const struct ec_params_usb_pd_power_info *p = args->params;
@@ -1313,10 +1514,8 @@ static enum ec_status hc_pd_power_info(struct host_cmd_handler_args *args)
 	args->response_size = sizeof(*r);
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_USB_PD_POWER_INFO,
-		     hc_pd_power_info,
+DECLARE_HOST_COMMAND(EC_CMD_USB_PD_POWER_INFO, hc_pd_power_info,
 		     EC_VER_MASK(0));
-#endif /* TEST_BUILD */
 
 static enum ec_status hc_charge_port_count(struct host_cmd_handler_args *args)
 {
@@ -1327,30 +1526,27 @@ static enum ec_status hc_charge_port_count(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_CHARGE_PORT_COUNT,
-		     hc_charge_port_count,
+DECLARE_HOST_COMMAND(EC_CMD_CHARGE_PORT_COUNT, hc_charge_port_count,
 		     EC_VER_MASK(0));
 
 static enum ec_status
 hc_charge_port_override(struct host_cmd_handler_args *args)
 {
 	const struct ec_params_charge_port_override *p = args->params;
-	const int16_t override_port = p->override_port;
+	const int16_t op = p->override_port;
 
-	if (override_port < OVERRIDE_DONT_CHARGE ||
-	    override_port >= CHARGE_PORT_COUNT)
+	if (op < OVERRIDE_DONT_CHARGE || op >= CHARGE_PORT_COUNT)
 		return EC_RES_INVALID_PARAM;
 
-	return charge_manager_set_override(override_port) == EC_SUCCESS ?
-		EC_RES_SUCCESS : EC_RES_ERROR;
+	return charge_manager_set_override(op) == EC_SUCCESS ? EC_RES_SUCCESS :
+							       EC_RES_ERROR;
 }
-DECLARE_HOST_COMMAND(EC_CMD_PD_CHARGE_PORT_OVERRIDE,
-		     hc_charge_port_override,
+DECLARE_HOST_COMMAND(EC_CMD_PD_CHARGE_PORT_OVERRIDE, hc_charge_port_override,
 		     EC_VER_MASK(0));
 
 #if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
-static enum ec_status hc_override_dedicated_charger_limit(
-		struct host_cmd_handler_args *args)
+static enum ec_status
+hc_override_dedicated_charger_limit(struct host_cmd_handler_args *args)
 {
 	const struct ec_params_dedicated_charger_limit *p = args->params;
 	struct charge_port_info ci = {
@@ -1371,11 +1567,10 @@ static enum ec_status hc_override_dedicated_charger_limit(
 	return EC_RES_SUCCESS;
 }
 DECLARE_HOST_COMMAND(EC_CMD_OVERRIDE_DEDICATED_CHARGER_LIMIT,
-		     hc_override_dedicated_charger_limit,
-		     EC_VER_MASK(0));
+		     hc_override_dedicated_charger_limit, EC_VER_MASK(0));
 #endif
 
-static int command_charge_port_override(int argc, char **argv)
+static int command_charge_port_override(int argc, const char **argv)
 {
 	int port = OVERRIDE_OFF;
 	int ret = EC_SUCCESS;
@@ -1389,12 +1584,12 @@ static int command_charge_port_override(int argc, char **argv)
 		ret = charge_manager_set_override(port);
 	}
 
-	ccprintf("Override: %d\n", (argc >= 2 && ret == EC_SUCCESS) ?
-					port : override_port);
+	ccprintf("Override: %d\n",
+		 (argc >= 2 && ret == EC_SUCCESS) ? port : override_port);
 	return ret;
 }
-DECLARE_CONSOLE_COMMAND(chgoverride, command_charge_port_override,
-	"[port | -1 | -2]",
+DECLARE_CONSOLE_COMMAND(
+	chgoverride, command_charge_port_override, "[port | -1 | -2]",
 	"Force charging from a given port (-1 = off, -2 = disable charging)");
 
 #ifdef CONFIG_CHARGE_MANAGER_EXTERNAL_POWER_LIMIT
@@ -1431,16 +1626,14 @@ hc_external_power_limit(struct host_cmd_handler_args *args)
 {
 	const struct ec_params_external_power_limit_v1 *p = args->params;
 
-	charge_manager_set_external_power_limit(p->current_lim,
-						p->voltage_lim);
+	charge_manager_set_external_power_limit(p->current_lim, p->voltage_lim);
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_EXTERNAL_POWER_LIMIT,
-		     hc_external_power_limit,
+DECLARE_HOST_COMMAND(EC_CMD_EXTERNAL_POWER_LIMIT, hc_external_power_limit,
 		     EC_VER_MASK(1));
 
-static int command_external_power_limit(int argc, char **argv)
+static int command_external_power_limit(int argc, const char **argv)
 {
 	int max_current;
 	int max_voltage;
@@ -1466,41 +1659,63 @@ static int command_external_power_limit(int argc, char **argv)
 	return EC_SUCCESS;
 }
 DECLARE_CONSOLE_COMMAND(chglim, command_external_power_limit,
-	"[max_current (mA)] [max_voltage (mV)]",
-	"Set max charger current / voltage");
+			"[max_current (mA)] [max_voltage (mV)]",
+			"Set max charger current / voltage");
 #endif /* CONFIG_CHARGE_MANAGER_EXTERNAL_POWER_LIMIT */
 
 #ifdef CONFIG_CMD_CHARGE_SUPPLIER_INFO
-static int charge_supplier_info(int argc, char **argv)
+static int charge_supplier_info(int argc, const char **argv)
 {
-	ccprintf("port=%d, type=%d, cur=%dmA, vtg=%dmV, lsm=%d\n",
-			charge_manager_get_active_charge_port(),
-			charge_supplier,
-			charge_current,
-			charge_voltage,
-			left_safe_mode);
-
+	int p, s;
+	int port_printed;
+
+	ccprintf("\n");
+	ccprintf("Port --Supplier-- Prio -Available Power-\n");
+	for (p = 0; p < CHARGE_PORT_COUNT; p++) {
+		port_printed = 0;
+		for (s = 0; s < CHARGE_SUPPLIER_COUNT; s++) {
+			if (available_charge[s][p].current == 0 &&
+			    available_charge[s][p].voltage == 0)
+				continue;
+			if (charge_manager_get_active_charge_port() == p &&
+			    charge_manager_get_supplier() == s)
+				ccprintf("*");
+			else
+				ccprintf(" ");
+			if (!port_printed) {
+				ccprintf("P%d  ", p);
+				port_printed = 1;
+			} else {
+				ccprintf("    ");
+			}
+			ccprintf("%-10s  %4d  %5dmA %5dmV\n",
+				 charge_supplier_name[s], supplier_priority[s],
+				 available_charge[s][p].current,
+				 available_charge[s][p].voltage);
+		}
+	}
+	ccprintf("\n");
+	ccprintf("  %s safe mode\n", left_safe_mode ? "Left" : "In");
+	ccprintf("  Override port = P%d\n", charge_manager_get_override());
+	ccprintf("\n");
 	return 0;
 }
-DECLARE_CONSOLE_COMMAND(chgsup, charge_supplier_info,
-			NULL, "print chg supplier info");
+DECLARE_CONSOLE_COMMAND(chgsup, charge_supplier_info, NULL,
+			"print chg supplier info");
 #endif
 
-__overridable
-int board_charge_port_is_sink(int port)
+__overridable int board_charge_port_is_sink(int port)
 {
 	return 1;
 }
 
-__overridable
-int board_charge_port_is_connected(int port)
+__overridable int board_charge_port_is_connected(int port)
 {
 	return 1;
 }
 
-__overridable
-void board_fill_source_power_info(int port,
-				  struct ec_response_usb_pd_power_info *r)
+__overridable void
+board_fill_source_power_info(int port, struct ec_response_usb_pd_power_info *r)
 {
 	r->meas.voltage_now = 0;
 	r->meas.voltage_max = 0;
@@ -1508,3 +1723,11 @@ void board_fill_source_power_info(int port,
 	r->meas.current_lim = 0;
 	r->max_power = 0;
 }
+
+__overridable void board_set_charge_limit(int port, int supplier, int charge_ma,
+					  int max_ma, int charge_mv)
+{
+#if defined(CONFIG_CHARGER) && defined(CONFIG_BATTERY)
+	charge_set_input_current_limit(charge_ma, charge_mv);
+#endif
+}
diff --git a/common/charge_ramp.c b/common/charge_ramp.c
index a408771f40..fcea02d1c7 100644
--- a/common/charge_ramp.c
+++ b/common/charge_ramp.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,21 +18,37 @@ test_mockable int chg_ramp_allowed(int port, int supplier)
 		return 0;
 
 	switch (supplier) {
-	/* Use ramping for USB-C DTS suppliers (debug accessory eg suzy-q). */
+	/*
+	 * Use ramping for USB-C DTS suppliers (debug accessory eg suzy-q).
+	 * The suzy-q simply passes through the VBUS. The power supplier behind
+	 * may be a SDP/CDP which requires ramping.
+	 */
 	case CHARGE_SUPPLIER_TYPEC_DTS:
 		return 1;
 	/*
-	 * Use HW ramping for USB-C chargers. Don't use SW ramping since the
-	 * slow ramp causes issues with auto power on (b/169634979).
+	 * Don't regulate the input voltage for USB-C chargers. It is
+	 * unnecessary as the USB-C compliant adapters should never trigger it
+	 * active.
+	 *
+	 * The USB-C spec defines their load curves should not be below
+	 * 4.75V @0A and 4V @3A. We can't define the voltage regulation value
+	 * higher than 4V since it limits the current reaching its max 3A. If
+	 * we define the voltage regulation value lower than 4V, their load
+	 * curves will never be below the voltage regulation line.
+	 *
+	 * Check go/charge_ramp_typec for detail.
 	 */
 	case CHARGE_SUPPLIER_PD:
 	case CHARGE_SUPPLIER_TYPEC:
-		return IS_ENABLED(CONFIG_CHARGE_RAMP_HW);
-	/* default: fall through */
+		return 0;
+		/* default: fall through */
 	}
 
+#ifdef CONFIG_USB_CHARGER
 	/* Otherwise ask the BC1.2 detect module */
 	return usb_charger_ramp_allowed(port, supplier);
+#endif
+	return 0;
 }
 
 test_mockable int chg_ramp_max(int port, int supplier, int sup_curr)
@@ -40,15 +56,20 @@ test_mockable int chg_ramp_max(int port, int supplier, int sup_curr)
 	switch (supplier) {
 	case CHARGE_SUPPLIER_PD:
 	case CHARGE_SUPPLIER_TYPEC:
+		return 0;
+
 	case CHARGE_SUPPLIER_TYPEC_DTS:
 		/*
 		 * We should not ramp DTS beyond what they advertise, otherwise
 		 * we may brownout the systems they are connected to.
 		 */
 		return sup_curr;
-	/* default: fall through */
+		/* default: fall through */
 	}
 
+#ifdef CONFIG_USB_CHARGER
 	/* Otherwise ask the BC1.2 detect module */
 	return usb_charger_ramp_max(port, supplier, sup_curr);
+#endif
+	return 0;
 }
diff --git a/common/charge_ramp_sw.c b/common/charge_ramp_sw.c
index bfd6db057b..4e5bdc8149 100644
--- a/common/charge_ramp_sw.c
+++ b/common/charge_ramp_sw.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,30 +16,30 @@
 #include "usb_pd.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
 
 /* Number of times to ramp current searching for limit before stable charging */
-#define RAMP_COUNT          3
+#define RAMP_COUNT 3
 
 /* Maximum allowable time charger can be unplugged to be considered an OCP */
 #define OC_RECOVER_MAX_TIME (SECOND)
 
 /* Delay for running state machine when board is not consuming full current */
-#define CURRENT_DRAW_DELAY  (5*SECOND)
+#define CURRENT_DRAW_DELAY (5 * SECOND)
 
 /* Current ramp increment */
-#define RAMP_CURR_INCR_MA   64
-#define RAMP_CURR_DELAY     (500*MSEC)
-#define RAMP_CURR_START_MA  500
+#define RAMP_CURR_INCR_MA 64
+#define RAMP_CURR_DELAY (500 * MSEC)
+#define RAMP_CURR_START_MA 500
 
 /* How much to backoff the input current limit when limit has been found */
-#define RAMP_ICL_BACKOFF    (2*RAMP_CURR_INCR_MA)
+#define RAMP_ICL_BACKOFF (2 * RAMP_CURR_INCR_MA)
 
 /* Interval at which VBUS voltage is monitored in stable state */
 #define STABLE_VBUS_MONITOR_INTERVAL (SECOND)
 
 /* Time to delay for stablizing the charging current */
-#define STABLIZE_DELAY (5*SECOND)
+#define STABLIZE_DELAY (5 * SECOND)
 
 enum chg_ramp_state {
 	CHG_RAMP_DISCONNECTED,
@@ -78,14 +78,13 @@ static int max_icl;
 static int min_icl;
 
 void chg_ramp_charge_supplier_change(int port, int supplier, int current,
-				timestamp_t registration_time, int voltage)
+				     timestamp_t registration_time, int voltage)
 {
 	/*
 	 * If the last active port was a valid port and the port
 	 * has changed, then this may have been an over-current.
 	 */
-	if (active_port != CHARGE_PORT_NONE &&
-	    port != active_port) {
+	if (active_port != CHARGE_PORT_NONE && port != active_port) {
 		if (oc_info_idx[active_port] == RAMP_COUNT - 1)
 			oc_info_idx[active_port] = 0;
 		else
@@ -111,7 +110,8 @@ void chg_ramp_charge_supplier_change(int port, int supplier, int current,
 	reg_time = registration_time;
 	if (ramp_st != CHG_RAMP_STABILIZE) {
 		ramp_st = (active_port == CHARGE_PORT_NONE) ?
-			  CHG_RAMP_DISCONNECTED : CHG_RAMP_CHARGE_DETECT_DELAY;
+				  CHG_RAMP_DISCONNECTED :
+				  CHG_RAMP_CHARGE_DETECT_DELAY;
 		CPRINTS("Ramp reset: st%d", ramp_st);
 		task_wake(TASK_ID_CHG_RAMP);
 	}
@@ -153,7 +153,7 @@ void chg_ramp_task(void *u)
 	int last_active_port = CHARGE_PORT_NONE;
 
 	enum chg_ramp_state ramp_st_prev = CHG_RAMP_DISCONNECTED,
-				   ramp_st_new = CHG_RAMP_DISCONNECTED;
+			    ramp_st_new = CHG_RAMP_DISCONNECTED;
 	int active_icl_new;
 
 	/* Clear last OCP supplier to guarantee we ramp on first connect */
@@ -190,15 +190,15 @@ void chg_ramp_task(void *u)
 				last_active_port = active_port;
 				if (reg_time.val <
 				    ACTIVE_OC_INFO.ts.val +
-				    OC_RECOVER_MAX_TIME) {
+					    OC_RECOVER_MAX_TIME) {
 					ACTIVE_OC_INFO.oc_detected = 1;
 				} else {
 					for (i = 0; i < RAMP_COUNT; ++i)
-						oc_info[active_port][i].
-							oc_detected = 0;
+						oc_info[active_port][i]
+							.oc_detected = 0;
 				}
-				detect_end_time_us = get_time().val +
-						     CHARGE_DETECT_DELAY;
+				detect_end_time_us =
+					get_time().val + CHARGE_DETECT_DELAY;
 				task_wait_time = CHARGE_DETECT_DELAY;
 				break;
 			}
@@ -214,6 +214,7 @@ void chg_ramp_task(void *u)
 			ramp_st_new = CHG_RAMP_OVERCURRENT_DETECT;
 			/* notify host of power info change */
 			pd_send_host_event(PD_EVENT_POWER_CHANGE);
+			__fallthrough;
 		case CHG_RAMP_OVERCURRENT_DETECT:
 			/* Check if we should ramp or go straight to stable */
 			task_wait_time = SECOND;
@@ -246,8 +247,8 @@ void chg_ramp_task(void *u)
 
 			if (i == RAMP_COUNT) {
 				/* Found OC threshold! */
-				active_icl_new = ACTIVE_OC_INFO.icl -
-						 RAMP_ICL_BACKOFF;
+				active_icl_new =
+					ACTIVE_OC_INFO.icl - RAMP_ICL_BACKOFF;
 				ramp_st_new = CHG_RAMP_STABLE;
 			} else {
 				/*
@@ -272,8 +273,8 @@ void chg_ramp_task(void *u)
 			if (board_is_vbus_too_low(active_port,
 						  CHG_RAMP_VBUS_RAMPING)) {
 				CPRINTS("VBUS low");
-				active_icl_new = MAX(min_icl, active_icl -
-							      RAMP_ICL_BACKOFF);
+				active_icl_new = MAX(
+					min_icl, active_icl - RAMP_ICL_BACKOFF);
 				ramp_st_new = CHG_RAMP_STABILIZE;
 				task_wait_time = STABLIZE_DELAY;
 				stablize_port = active_port;
@@ -300,8 +301,8 @@ void chg_ramp_task(void *u)
 			}
 
 			ramp_st_new = active_port == CHARGE_PORT_NONE ?
-				      CHG_RAMP_DISCONNECTED :
-				      CHG_RAMP_CHARGE_DETECT_DELAY;
+					      CHG_RAMP_DISCONNECTED :
+					      CHG_RAMP_CHARGE_DETECT_DELAY;
 			break;
 		case CHG_RAMP_STABLE:
 			/* Maintain input current limit */
@@ -320,7 +321,7 @@ void chg_ramp_task(void *u)
 						  CHG_RAMP_VBUS_STABLE)) {
 				CPRINTS("VBUS low; Re-ramp");
 				max_icl = MAX(min_icl,
-						max_icl - RAMP_ICL_BACKOFF);
+					      max_icl - RAMP_ICL_BACKOFF);
 				active_icl_new = min_icl;
 				ramp_st_new = CHG_RAMP_RAMP;
 			}
@@ -334,9 +335,9 @@ void chg_ramp_task(void *u)
 
 		/* Skip setting limit if status is stable twice in a row */
 		if (ramp_st_prev != CHG_RAMP_STABLE ||
-				ramp_st != CHG_RAMP_STABLE) {
-			CPRINTS("Ramp p%d st%d %dmA %dmA",
-				active_port, ramp_st, min_icl, active_icl);
+		    ramp_st != CHG_RAMP_STABLE) {
+			CPRINTS("Ramp p%d st%d %dmA %dmA", active_port, ramp_st,
+				min_icl, active_icl);
 			/* Set the input current limit */
 			lim = chg_ramp_get_current_limit();
 			board_set_charge_limit(active_port, active_sup, lim,
@@ -356,13 +357,13 @@ void chg_ramp_task(void *u)
 }
 
 #ifdef CONFIG_CMD_CHGRAMP
-static int command_chgramp(int argc, char **argv)
+static int command_chgramp(int argc, const char **argv)
 {
 	int i;
 	int port;
 
-	ccprintf("Chg Ramp:\nState: %d\nMin ICL: %d\nActive ICL: %d\n",
-		 ramp_st, min_icl, active_icl);
+	ccprintf("Chg Ramp:\nState: %d\nMin ICL: %d\nActive ICL: %d\n", ramp_st,
+		 min_icl, active_icl);
 
 	for (port = 0; port < board_get_usb_pd_port_count(); port++) {
 		ccprintf("Port %d:\n", port);
@@ -377,7 +378,6 @@ static int command_chgramp(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(chgramp, command_chgramp,
-	"",
-	"Dump charge ramp state info");
+DECLARE_CONSOLE_COMMAND(chgramp, command_chgramp, "",
+			"Dump charge ramp state info");
 #endif
diff --git a/common/charge_state.c b/common/charge_state.c
new file mode 100644
index 0000000000..6dd7f3404d
--- /dev/null
+++ b/common/charge_state.c
@@ -0,0 +1,2474 @@
+/* Copyright 2014 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery charging task and state machine.
+ */
+
+#include "battery.h"
+#include "battery_smart.h"
+#include "builtin/assert.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "charger_base.h"
+#include "charger_profile_override.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "i2c.h"
+#include "math_util.h"
+#include "power.h"
+#include "printf.h"
+#include "system.h"
+#include "task.h"
+#include "throttle_ap.h"
+#include "timer.h"
+#include "usb_common.h"
+#include "usb_pd.h"
+#include "util.h"
+
+/* Console output macros */
+#define CPUTS(outstr) cputs(CC_CHARGER, outstr)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+
+/* Extra debugging prints when allocating power between lid and base. */
+#undef CHARGE_ALLOCATE_EXTRA_DEBUG
+
+#define CRITICAL_BATTERY_SHUTDOWN_TIMEOUT_US \
+	(CONFIG_BATTERY_CRITICAL_SHUTDOWN_TIMEOUT * SECOND)
+#define PRECHARGE_TIMEOUT_US (PRECHARGE_TIMEOUT * SECOND)
+
+#if defined(CONFIG_THROTTLE_AP_ON_BAT_DISCHG_CURRENT) || \
+	defined(CONFIG_THROTTLE_AP_ON_BAT_VOLTAGE)
+#ifndef CONFIG_HOSTCMD_EVENTS
+#error "Must define CONFIG_HOSTCMD_EVENTS"
+#endif /* CONFIG_HOSTCMD_EVENTS */
+#endif
+
+#define BAT_MAX_DISCHG_CURRENT 5000 /* mA */
+#define BAT_LOW_VOLTAGE_THRESH 3200 /* mV */
+
+#define BAT_OCP_TIMEOUT_US (60 * SECOND)
+#define BAT_OCP_HYSTERESIS_PCT 10
+#define BAT_OCP_HYSTERESIS \
+	(BAT_MAX_DISCHG_CURRENT * BAT_OCP_HYSTERESIS_PCT / 100) /* mA */
+
+#define BAT_UVP_TIMEOUT_US (60 * SECOND)
+#define BAT_UVP_HYSTERESIS_PCT 3
+#define BAT_UVP_HYSTERESIS \
+	(BAT_LOW_VOLTAGE_THRESH * BAT_UVP_HYSTERESIS_PCT / 100) /* mV */
+
+static timestamp_t uvp_throttle_start_time;
+
+static uint8_t battery_level_shutdown;
+
+/*
+ * State for charger_task(). Here so we can reset it on a HOOK_INIT, and
+ * because stack space is more limited than .bss
+ */
+static const struct battery_info *batt_info;
+static struct charge_state_data curr;
+static enum charge_state prev_state;
+static int prev_ac, prev_charge, prev_disp_charge;
+static enum battery_present prev_bp;
+static unsigned int user_current_limit = -1U;
+test_export_static timestamp_t shutdown_target_time;
+static timestamp_t precharge_start_time;
+static struct sustain_soc sustain_soc;
+static struct current_limit {
+	uint32_t value; /* Charge limit to apply, in mA */
+	int soc; /* Minimum battery SoC at which the limit will be applied. */
+} current_limit = { -1U, 0 };
+
+/* State which is reported out from the charger or updated externally */
+struct state {
+	/*
+	 * battery is full, i.e. not accepting current.
+	 * Accessed externally via charge_get_percent()
+	 */
+	bool is_full;
+	/* exported by get_chg_ctrl_mode() */
+	enum ec_charge_control_mode chg_ctl_mode;
+	/**
+	 * Manual voltage override (-1 = no override)
+	 * Accessed externally via chgstate_set_manual_voltage() and
+	 * charge_get_charge_state_debug()
+	 */
+	int manual_voltage;
+	/*
+	 * Manual current override (-1 = no override)
+	 * Accessed externally via chgstate_set_manual_current() and
+	 * charge_get_charge_state_debug()
+	 */
+	int manual_current;
+	/*
+	 * Accessed externally via charging_progress_displayed() and
+	 * show_charging_progress() (the latter for testing only)
+	 */
+	bool is_charging_progress_displayed;
+} local_state;
+
+/*
+ * The timestamp when the battery charging current becomes stable.
+ * When a new charging status happens, charger needs several seconds to
+ * stabilize the battery charging current.
+ * stable_current should be evaluated when stable_ts expired.
+ * stable_ts should be reset if the charger input voltage/current changes,
+ * or a new battery charging voltage/request happened.
+ * By evaluating stable_current, we can evaluate the battery's desired charging
+ * power desired_mw. This allow us to have a better charging efficiency by
+ * negotiating the most fit PDO, i.e. the PDO provides the power just enough for
+ * the system and battery, or the PDO with preferred voltage.
+ */
+STATIC_IF(CONFIG_USB_PD_PREFER_MV) timestamp_t stable_ts;
+/* battery charging current evaluated after stable_ts expired */
+STATIC_IF(CONFIG_USB_PD_PREFER_MV) int stable_current;
+/* battery desired power in mW. This is used to negotiate the suitable PDO */
+STATIC_IF(CONFIG_USB_PD_PREFER_MV) int desired_mw;
+STATIC_IF_NOT(CONFIG_USB_PD_PREFER_MV) struct pd_pref_config_t pd_pref_config;
+
+/* Is battery connected but unresponsive after precharge? */
+static int battery_seems_dead;
+
+static int battery_seems_disconnected;
+
+/*
+ * Was battery removed?  Set when we see BP_NO, cleared after the battery is
+ * reattached and becomes responsive.  Used to indicate an error state after
+ * removal and trigger re-reading the battery static info when battery is
+ * reattached and responsive.
+ */
+static int battery_was_removed;
+
+static int problems_exist;
+
+static const char *const prob_text[] = {
+	"static update",     "set voltage",	 "set current", "set mode",
+	"set input current", "post init",	 "chg params",	"batt params",
+	"custom profile",    "cfg secondary chg"
+};
+BUILD_ASSERT(ARRAY_SIZE(prob_text) == NUM_PROBLEM_TYPES);
+
+#ifdef CONFIG_CHARGE_DEBUG
+static bool is_debugging;
+#endif
+
+void set_debugging(bool val)
+{
+#ifdef CONFIG_CHARGE_DEBUG
+	is_debugging = val;
+#endif
+}
+
+static bool debugging(void)
+{
+#ifdef CONFIG_CHARGE_DEBUG
+	return is_debugging;
+#else
+	return false;
+#endif
+}
+
+/*
+ * TODO(crosbug.com/p/27639): When do we decide a problem is real and not
+ * just intermittent? And what do we do about it?
+ */
+void charge_problem(enum problem_type p, int v)
+{
+	static int last_prob_val[NUM_PROBLEM_TYPES];
+	static timestamp_t last_prob_time[NUM_PROBLEM_TYPES];
+	timestamp_t t_now, t_diff;
+
+	if (last_prob_val[p] != v) {
+		t_now = get_time();
+		t_diff.val = t_now.val - last_prob_time[p].val;
+		CPRINTS("charge problem: %s, 0x%x -> 0x%x after %.6" PRId64 "s",
+			prob_text[p], last_prob_val[p], v, t_diff.val);
+		last_prob_val[p] = v;
+		last_prob_time[p] = t_now;
+	}
+	problems_exist = 1;
+}
+
+enum ec_charge_control_mode get_chg_ctrl_mode(void)
+{
+	return local_state.chg_ctl_mode;
+}
+
+void reset_prev_disp_charge(void)
+{
+	prev_disp_charge = -1;
+}
+
+int battery_sustainer_set(int8_t lower, int8_t upper)
+{
+	if (lower == -1 || upper == -1) {
+		CPRINTS("Sustainer disabled");
+		sustain_soc.lower = -1;
+		sustain_soc.upper = -1;
+		sustain_soc.flags = 0;
+		return EC_SUCCESS;
+	}
+
+	if (lower <= upper && 0 <= lower && upper <= 100) {
+		/* Currently sustainer requires discharge_on_ac. */
+		if (!IS_ENABLED(CONFIG_CHARGER_DISCHARGE_ON_AC))
+			return EC_RES_UNAVAILABLE;
+		sustain_soc.lower = lower;
+		sustain_soc.upper = upper;
+		CPRINTS("Sustainer set: %d%% ~ %d%%", lower, upper);
+		return EC_SUCCESS;
+	}
+
+	CPRINTS("Invalid param: %s(%d, %d)", __func__, lower, upper);
+	return EC_ERROR_INVAL;
+}
+
+static void battery_sustainer_disable(void)
+{
+	battery_sustainer_set(-1, -1);
+}
+
+bool battery_sustainer_enabled(void)
+{
+	return sustain_soc.lower != -1 && sustain_soc.upper != -1;
+}
+
+static const char *const state_list[] = { "idle", "discharge", "charge",
+					  "precharge" };
+BUILD_ASSERT(ARRAY_SIZE(state_list) == NUM_STATES_V2);
+static const char *const batt_pres[] = {
+	"NO",
+	"YES",
+	"NOT_SURE",
+};
+
+const char *mode_text[] = EC_CHARGE_MODE_TEXT;
+BUILD_ASSERT(ARRAY_SIZE(mode_text) == CHARGE_CONTROL_COUNT);
+
+static void dump_charge_state(void)
+{
+#define DUMP(FLD, FMT) ccprintf(#FLD " = " FMT "\n", curr.FLD)
+#define DUMP_CHG(FLD, FMT) ccprintf("\t" #FLD " = " FMT "\n", curr.chg.FLD)
+#define DUMP_BATT(FLD, FMT) ccprintf("\t" #FLD " = " FMT "\n", curr.batt.FLD)
+#define DUMP_OCPC(FLD, FMT) ccprintf("\t" #FLD " = " FMT "\n", curr.ocpc.FLD)
+
+	enum ec_charge_control_mode cmode = get_chg_ctrl_mode();
+
+	ccprintf("state = %s\n", state_list[curr.state]);
+	DUMP(ac, "%d");
+	DUMP(batt_is_charging, "%d");
+	ccprintf("chg.*:\n");
+	DUMP_CHG(voltage, "%dmV");
+	DUMP_CHG(current, "%dmA");
+	DUMP_CHG(input_current, "%dmA");
+	DUMP_CHG(status, "0x%x");
+	DUMP_CHG(option, "0x%x");
+	DUMP_CHG(flags, "0x%x");
+	cflush();
+	ccprintf("batt.*:\n");
+	ccprintf("\ttemperature = %dC\n",
+		 DECI_KELVIN_TO_CELSIUS(curr.batt.temperature));
+	DUMP_BATT(state_of_charge, "%d%%");
+	DUMP_BATT(voltage, "%dmV");
+	DUMP_BATT(current, "%dmA");
+	DUMP_BATT(desired_voltage, "%dmV");
+	DUMP_BATT(desired_current, "%dmA");
+	DUMP_BATT(flags, "0x%x");
+	DUMP_BATT(remaining_capacity, "%dmAh");
+	DUMP_BATT(full_capacity, "%dmAh");
+	ccprintf("\tis_present = %s\n", batt_pres[curr.batt.is_present]);
+	cflush();
+#ifdef CONFIG_OCPC
+	ccprintf("ocpc.*:\n");
+	DUMP_OCPC(active_chg_chip, "%d");
+	DUMP_OCPC(combined_rsys_rbatt_mo, "%dmOhm");
+	if ((curr.ocpc.active_chg_chip != -1) &&
+	    !(curr.ocpc.chg_flags[curr.ocpc.active_chg_chip] &
+	      OCPC_NO_ISYS_MEAS_CAP)) {
+		DUMP_OCPC(rbatt_mo, "%dmOhm");
+		DUMP_OCPC(rsys_mo, "%dmOhm");
+		DUMP_OCPC(isys_ma, "%dmA");
+	}
+	DUMP_OCPC(vsys_aux_mv, "%dmV");
+	DUMP_OCPC(vsys_mv, "%dmV");
+	DUMP_OCPC(primary_vbus_mv, "%dmV");
+	DUMP_OCPC(primary_ibus_ma, "%dmA");
+	DUMP_OCPC(secondary_vbus_mv, "%dmV");
+	DUMP_OCPC(secondary_ibus_ma, "%dmA");
+	DUMP_OCPC(last_error, "%d");
+	DUMP_OCPC(integral, "%d");
+	DUMP_OCPC(last_vsys, "%dmV");
+	cflush();
+#endif /* CONFIG_OCPC */
+	DUMP(requested_voltage, "%dmV");
+	DUMP(requested_current, "%dmA");
+#ifdef CONFIG_CHARGER_OTG
+	DUMP(output_current, "%dmA");
+#endif
+	if (IS_ENABLED(CONFIG_EC_EC_COMM_BATTERY_CLIENT)) {
+		ccprintf("input_voltage = %dmV\n",
+			 charger_base_get_input_voltage(&curr));
+	}
+	ccprintf("chg_ctl_mode = %s (%d)\n",
+		 cmode < CHARGE_CONTROL_COUNT ? mode_text[cmode] : "UNDEF",
+		 cmode);
+	ccprintf("manual_voltage = %d\n", local_state.manual_voltage);
+	ccprintf("manual_current = %d\n", local_state.manual_current);
+	ccprintf("user_current_limit = %dmA\n", user_current_limit);
+	ccprintf("battery_seems_dead = %d\n", battery_seems_dead);
+	ccprintf("battery_seems_disconnected = %d\n",
+		 battery_seems_disconnected);
+	ccprintf("battery_was_removed = %d\n", battery_was_removed);
+	ccprintf("debug output = %s\n", debugging() ? "on" : "off");
+	ccprintf("Battery sustainer = %s (%d%% ~ %d%%)\n",
+		 battery_sustainer_enabled() ? "on" : "off", sustain_soc.lower,
+		 sustain_soc.upper);
+#undef DUMP
+}
+
+bool charging_progress_displayed(void)
+{
+	bool rv = local_state.is_charging_progress_displayed;
+
+	local_state.is_charging_progress_displayed = false;
+	return rv;
+}
+
+/* Output to the console so progress is visible */
+static void show_charging_progress(bool is_full)
+{
+	int rv = 0, minutes, to_full, chgnum = 0;
+	int dsoc;
+
+	if (IS_ENABLED(TEST_BUILD))
+		local_state.is_charging_progress_displayed = true;
+#ifdef CONFIG_BATTERY_SMART
+	/*
+	 * Predicted remaining battery capacity based on AverageCurrent().
+	 * 65535 = Battery is not being discharged.
+	 */
+	if (!battery_time_to_empty(&minutes) && minutes != 65535)
+		to_full = 0;
+	/*
+	 * Predicted time-to-full charge based on AverageCurrent().
+	 * 65535 = Battery is not being discharged.
+	 */
+	else if (!battery_time_to_full(&minutes) && minutes != 65535)
+		to_full = 1;
+	/*
+	 * If both time to empty and time to full have invalid data, consider
+	 * measured current from the coulomb counter and ac present status to
+	 * decide whether battery is about to full or empty.
+	 */
+	else {
+		to_full = curr.batt_is_charging;
+		rv = EC_ERROR_UNKNOWN;
+	}
+#else
+	if (!curr.batt_is_charging) {
+		rv = battery_time_to_empty(&minutes);
+		to_full = 0;
+	} else {
+		rv = battery_time_to_full(&minutes);
+		to_full = 1;
+	}
+#endif
+
+	dsoc = charge_get_display_charge();
+	if (rv)
+		CPRINTS("Battery %d%% (Display %d.%d %%) / ??h:?? %s%s",
+			curr.batt.state_of_charge, dsoc / 10, dsoc % 10,
+			to_full ? "to full" : "to empty",
+			is_full ? ", not accepting current" : "");
+	else
+		CPRINTS("Battery %d%% (Display %d.%d %%) / %dh:%d %s%s",
+			curr.batt.state_of_charge, dsoc / 10, dsoc % 10,
+			minutes / 60, minutes % 60,
+			to_full ? "to full" : "to empty",
+			is_full ? ", not accepting current" : "");
+
+	if (IS_ENABLED(CONFIG_EC_EC_COMM_BATTERY_CLIENT))
+		charger_base_show_charge();
+
+	if (debugging()) {
+		ccprintf("battery:\n");
+		print_battery_debug();
+		ccprintf("charger:\n");
+		if (IS_ENABLED(CONFIG_OCPC))
+			chgnum = charge_get_active_chg_chip();
+		print_charger_debug(chgnum);
+		ccprintf("chg:\n");
+		dump_charge_state();
+	}
+}
+
+/* Calculate if battery is full based on whether it is accepting charge */
+test_mockable int calc_is_full(void)
+{
+	static int ret;
+
+	/* If bad state of charge reading, return last value */
+	if (curr.batt.flags & BATT_FLAG_BAD_STATE_OF_CHARGE ||
+	    curr.batt.state_of_charge > 100)
+		return ret;
+	/*
+	 * Battery is full when SoC is above 90% and battery desired current
+	 * is 0. This is necessary because some batteries stop charging when
+	 * the SoC still reports <100%, so we need to check desired current
+	 * to know if it is actually full.
+	 */
+	ret = (curr.batt.state_of_charge >= 90 &&
+	       curr.batt.desired_current == 0);
+	return ret;
+}
+
+__overridable int board_should_charger_bypass(void)
+{
+	return false;
+}
+
+#ifdef CONFIG_CHARGER_BYPASS_REVERSE_TURBO
+int board_want_charger_change_mode(void)
+{
+	static int pre_batt = BP_YES;
+	int curr_batt = battery_is_present();
+
+	if (pre_batt != curr_batt) {
+		pre_batt = curr_batt;
+		return true;
+	} else
+		return false;
+}
+#endif
+
+int charge_request(bool use_curr, bool is_full)
+{
+	int r1 = EC_SUCCESS, r2 = EC_SUCCESS, r3 = EC_SUCCESS, r4 = EC_SUCCESS;
+	static int prev_volt, prev_curr;
+	bool should_bypass;
+	int voltage = 0, current = 0;
+
+	if (use_curr) {
+		voltage = curr.requested_voltage;
+		current = curr.requested_current;
+	}
+	if (!voltage || !current) {
+#ifdef CONFIG_CHARGER_NARROW_VDC
+		current = 0;
+		/*
+		 * With NVDC charger, keep VSYS voltage higher than battery,
+		 * otherwise the BGATE FET body diode would conduct and
+		 * discharge the battery.
+		 */
+		voltage = charger_closest_voltage(
+			curr.batt.voltage + charger_get_info()->voltage_step);
+		/* If the battery is full, request the max voltage. */
+		if (is_full)
+			voltage = battery_get_info()->voltage_max;
+		/* And handle dead battery case */
+		voltage = MAX(voltage, battery_get_info()->voltage_normal);
+#else
+		voltage = current = 0;
+#endif
+	}
+
+	if (curr.ac) {
+		if (prev_volt != voltage || prev_curr != current)
+			CPRINTS("%s(%dmV, %dmA)", __func__, voltage, current);
+	}
+
+	/*
+	 * Enable bypass mode if applicable. Transition from Bypass to Bypass +
+	 * CHRG or backward is done after this call (by set_current & set_mode)
+	 * thus not done here. Similarly, when bypass is disabled, transitioning
+	 * from nvdc + chrg will be done separately.
+	 */
+	should_bypass = board_should_charger_bypass();
+	if ((should_bypass && !(curr.chg.status & CHARGER_BYPASS_MODE)) ||
+	    (!should_bypass && (curr.chg.status & CHARGER_BYPASS_MODE))
+#ifdef CONFIG_CHARGER_BYPASS_REVERSE_TURBO
+	    || board_want_charger_change_mode()
+#endif
+	    )
+		charger_enable_bypass_mode(0, should_bypass);
+
+	/*
+	 * Set current before voltage so that if we are just starting
+	 * to charge, we allow some time (i2c delay) for charging circuit to
+	 * start at a voltage just above battery voltage before jumping
+	 * up. This helps avoid large current spikes when connecting
+	 * battery.
+	 */
+	if (current >= 0) {
+#ifdef CONFIG_OCPC
+		/*
+		 * For OCPC systems, don't unconditionally modify the primary
+		 * charger IC's charge current.  It may be handled by the
+		 * charger drivers directly.
+		 */
+		if (curr.ocpc.active_chg_chip == CHARGER_PRIMARY)
+#endif
+			r2 = charger_set_current(0, current);
+	}
+	if (r2 != EC_SUCCESS)
+		charge_problem(PR_SET_CURRENT, r2);
+
+	if (voltage >= 0)
+		r1 = charger_set_voltage(0, voltage);
+	if (r1 != EC_SUCCESS)
+		charge_problem(PR_SET_VOLTAGE, r1);
+
+#ifdef CONFIG_OCPC
+	/*
+	 * For OCPC systems, if the secondary charger is active, we need to
+	 * configure that charge IC as well.  Note that if OCPC ever supports
+	 * more than 2 charger ICs, we'll need to refactor things a bit.  The
+	 * following check should be comparing against CHARGER_PRIMARY and
+	 * config_secondary_charger should probably be config_auxiliary_charger
+	 * and take the active chgnum as a parameter.
+	 */
+	if (curr.ocpc.active_chg_chip == CHARGER_SECONDARY) {
+		if ((current >= 0) || (voltage >= 0))
+			r3 = ocpc_config_secondary_charger(
+				&curr.desired_input_current, &curr.ocpc,
+				voltage, current);
+		if (r3 != EC_SUCCESS)
+			charge_problem(PR_CFG_SEC_CHG, r3);
+	}
+#endif /* CONFIG_OCPC */
+
+	/*
+	 * Set the charge inhibit bit when possible as it appears to save
+	 * power in some cases (e.g. Nyan with BQ24735).
+	 */
+	if (voltage > 0 || current > 0)
+		r4 = charger_set_mode(0);
+	else
+		r4 = charger_set_mode(CHARGE_FLAG_INHIBIT_CHARGE);
+	if (r4 != EC_SUCCESS)
+		charge_problem(PR_SET_MODE, r4);
+
+	/*
+	 * Only update if the request worked, so we'll keep trying on failures.
+	 */
+	if (r1 || r2)
+		return r1 ? r1 : r2;
+	if (IS_ENABLED(CONFIG_OCPC) && r3)
+		return r3;
+
+	if (IS_ENABLED(CONFIG_USB_PD_PREFER_MV) &&
+	    (prev_volt != voltage || prev_curr != current))
+		charge_reset_stable_current();
+
+	prev_volt = voltage;
+	prev_curr = current;
+
+	return EC_SUCCESS;
+}
+
+void chgstate_set_manual_current(int curr_ma)
+{
+	if (curr_ma < 0)
+		local_state.manual_current = -1;
+	else
+		local_state.manual_current = charger_closest_current(curr_ma);
+}
+
+void chgstate_set_manual_voltage(int volt_mv)
+{
+	local_state.manual_voltage = charger_closest_voltage(volt_mv);
+}
+
+/* Force charging off before the battery is full. */
+int set_chg_ctrl_mode(enum ec_charge_control_mode mode)
+{
+	bool discharge_on_ac = false;
+	int current, voltage;
+	int rv;
+
+	current = local_state.manual_current;
+	voltage = local_state.manual_voltage;
+
+	if (mode >= CHARGE_CONTROL_COUNT)
+		return EC_ERROR_INVAL;
+
+	if (mode == CHARGE_CONTROL_NORMAL) {
+		current = -1;
+		voltage = -1;
+	} else {
+		/* Changing mode is only meaningful if AC is present. */
+		if (!curr.ac)
+			return EC_ERROR_NOT_POWERED;
+
+		if (mode == CHARGE_CONTROL_DISCHARGE) {
+			if (!IS_ENABLED(CONFIG_CHARGER_DISCHARGE_ON_AC))
+				return EC_ERROR_UNIMPLEMENTED;
+			discharge_on_ac = true;
+		} else if (mode == CHARGE_CONTROL_IDLE) {
+			current = 0;
+			voltage = 0;
+		}
+	}
+
+	if (IS_ENABLED(CONFIG_CHARGER_DISCHARGE_ON_AC)) {
+		rv = charger_discharge_on_ac(discharge_on_ac);
+		if (rv != EC_SUCCESS)
+			return rv;
+	}
+
+	/* Commit all atomically */
+	local_state.chg_ctl_mode = mode;
+	local_state.manual_current = current;
+	local_state.manual_voltage = voltage;
+
+	return EC_SUCCESS;
+}
+
+static inline int battery_too_hot(int batt_temp_c)
+{
+	return (!(curr.batt.flags & BATT_FLAG_BAD_TEMPERATURE) &&
+		(batt_temp_c > batt_info->discharging_max_c));
+}
+
+static inline int battery_too_cold_for_discharge(int batt_temp_c)
+{
+	return (!(curr.batt.flags & BATT_FLAG_BAD_TEMPERATURE) &&
+		(batt_temp_c < batt_info->discharging_min_c));
+}
+
+__attribute__((weak)) uint8_t board_set_battery_level_shutdown(void)
+{
+	return BATTERY_LEVEL_SHUTDOWN;
+}
+
+/* True if we know the charge is too low, or we know the voltage is too low. */
+static inline int battery_too_low(void)
+{
+	return ((!(curr.batt.flags & BATT_FLAG_BAD_STATE_OF_CHARGE) &&
+		 curr.batt.state_of_charge < battery_level_shutdown) ||
+		(!(curr.batt.flags & BATT_FLAG_BAD_VOLTAGE) &&
+		 curr.batt.voltage <= batt_info->voltage_min));
+}
+
+__attribute__((weak)) enum critical_shutdown
+board_critical_shutdown_check(struct charge_state_data *curr)
+{
+#ifdef CONFIG_BATTERY_CRITICAL_SHUTDOWN_CUT_OFF
+	return CRITICAL_SHUTDOWN_CUTOFF;
+#elif defined(CONFIG_HIBERNATE)
+	return CRITICAL_SHUTDOWN_HIBERNATE;
+#else
+	return CRITICAL_SHUTDOWN_IGNORE;
+#endif
+}
+
+static int is_battery_critical(void)
+{
+	int batt_temp_c = DECI_KELVIN_TO_CELSIUS(curr.batt.temperature);
+
+	/*
+	 * TODO(crosbug.com/p/27642): The thermal loop should watch the battery
+	 * temp, so it can turn fans on.
+	 */
+	if (battery_too_hot(batt_temp_c)) {
+		CPRINTS("Batt too hot: %dC", batt_temp_c);
+		return 1;
+	}
+
+	/* Note: the battery may run on AC without discharging when too cold */
+	if (!curr.ac && battery_too_cold_for_discharge(batt_temp_c)) {
+		CPRINTS("Batt too cold: %dC", batt_temp_c);
+		return 1;
+	}
+
+	if (battery_too_low() && !curr.batt_is_charging) {
+		CPRINTS("Low battery: %d%%, %dmV", curr.batt.state_of_charge,
+			curr.batt.voltage);
+		return 1;
+	}
+
+	return 0;
+}
+
+/*
+ * If the battery is at extremely low charge (and discharging) or extremely
+ * high temperature, the EC will notify the AP and start a timer. If the
+ * critical condition is not corrected before the timeout expires, the EC
+ * will shut down the AP (if the AP is not already off) and then optionally
+ * hibernate or cut off battery.
+ */
+static int shutdown_on_critical_battery(void)
+{
+	if (!is_battery_critical()) {
+		/* Reset shutdown warning time */
+		shutdown_target_time.val = 0;
+		return 0;
+	}
+
+	if (!shutdown_target_time.val) {
+		/* Start count down timer */
+		CPRINTS("Start shutdown due to critical battery");
+		shutdown_target_time.val =
+			get_time().val + CRITICAL_BATTERY_SHUTDOWN_TIMEOUT_US;
+		if (IS_ENABLED(CONFIG_HOSTCMD_EVENTS) &&
+		    !chipset_in_state(CHIPSET_STATE_ANY_OFF))
+			host_set_single_event(EC_HOST_EVENT_BATTERY_SHUTDOWN);
+		return 1;
+	}
+
+	if (!timestamp_expired(shutdown_target_time, 0))
+		return 1;
+
+	/* Timer has expired */
+	if (chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF)) {
+		switch (board_critical_shutdown_check(&curr)) {
+		case CRITICAL_SHUTDOWN_HIBERNATE:
+			if (IS_ENABLED(CONFIG_HIBERNATE)) {
+				/*
+				 * If the chipset is on its way down but not
+				 * quite there yet, give it a little time to
+				 * get there.
+				 */
+				if (!chipset_in_state(CHIPSET_STATE_ANY_OFF))
+					sleep(1);
+				CPRINTS("Hibernate due to critical battery");
+				cflush();
+				system_hibernate(0, 0);
+			}
+			break;
+		case CRITICAL_SHUTDOWN_CUTOFF:
+			/*
+			 * Give the chipset just a sec to get to off if
+			 * it's trying.
+			 */
+			if (!chipset_in_state(CHIPSET_STATE_ANY_OFF))
+				sleep(1);
+			CPRINTS("Cutoff due to critical battery");
+			cflush();
+			board_cut_off_battery();
+			break;
+		case CRITICAL_SHUTDOWN_IGNORE:
+		default:
+			break;
+		}
+	} else {
+		/* Timeout waiting for AP to shut down, so kill it */
+		CPRINTS("charge force shutdown due to critical battery");
+		chipset_force_shutdown(CHIPSET_SHUTDOWN_BATTERY_CRIT);
+	}
+
+	return 1;
+}
+
+int battery_is_below_threshold(enum batt_threshold_type type, bool transitioned)
+{
+	int threshold;
+
+	/* We can't tell what the current charge is. Assume it's okay. */
+	if (curr.batt.flags & BATT_FLAG_BAD_STATE_OF_CHARGE)
+		return 0;
+
+	switch (type) {
+	case BATT_THRESHOLD_TYPE_LOW:
+		threshold = BATTERY_LEVEL_LOW;
+		break;
+	case BATT_THRESHOLD_TYPE_SHUTDOWN:
+		threshold = CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE;
+		break;
+	default:
+		return 0;
+	}
+
+	return curr.batt.state_of_charge <= threshold &&
+	       (!transitioned || prev_charge > threshold);
+}
+
+/*
+ * Send host events as the battery charge drops below certain thresholds.
+ * We handle forced shutdown and other actions elsewhere; this is just for the
+ * host events. We send these even if the AP is off, since the AP will read and
+ * discard any events it doesn't care about the next time it wakes up.
+ */
+static void notify_host_of_low_battery_charge(void)
+{
+	if (IS_ENABLED(CONFIG_HOSTCMD_EVENTS)) {
+		if (battery_is_below_threshold(BATT_THRESHOLD_TYPE_LOW, true))
+			host_set_single_event(EC_HOST_EVENT_BATTERY_LOW);
+
+		if (battery_is_below_threshold(BATT_THRESHOLD_TYPE_SHUTDOWN,
+					       true))
+			host_set_single_event(EC_HOST_EVENT_BATTERY_CRITICAL);
+	}
+}
+
+static void set_charge_state(enum charge_state state)
+{
+	prev_state = curr.state;
+	curr.state = state;
+}
+
+static void notify_host_of_low_battery_voltage(void)
+{
+	if (!IS_ENABLED(CONFIG_THROTTLE_AP_ON_BAT_VOLTAGE))
+		return;
+
+	if ((curr.batt.flags & BATT_FLAG_BAD_VOLTAGE) ||
+	    chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return;
+
+	if (!uvp_throttle_start_time.val &&
+	    (curr.batt.voltage < BAT_LOW_VOLTAGE_THRESH)) {
+		throttle_ap(THROTTLE_ON, THROTTLE_SOFT,
+			    THROTTLE_SRC_BAT_VOLTAGE);
+		uvp_throttle_start_time = get_time();
+	} else if (uvp_throttle_start_time.val &&
+		   (curr.batt.voltage <
+		    BAT_LOW_VOLTAGE_THRESH + BAT_UVP_HYSTERESIS)) {
+		/*
+		 * Reset the timer when we are not sure if VBAT can stay
+		 * above BAT_LOW_VOLTAGE_THRESH after we stop throttling.
+		 */
+		uvp_throttle_start_time = get_time();
+	} else if (uvp_throttle_start_time.val &&
+		   (get_time().val >
+		    uvp_throttle_start_time.val + BAT_UVP_TIMEOUT_US)) {
+		throttle_ap(THROTTLE_OFF, THROTTLE_SOFT,
+			    THROTTLE_SRC_BAT_VOLTAGE);
+		uvp_throttle_start_time.val = 0;
+	}
+}
+
+static void notify_host_of_over_current(struct batt_params *batt)
+{
+	static timestamp_t ocp_throttle_start_time;
+
+	if (!IS_ENABLED(CONFIG_THROTTLE_AP_ON_BAT_DISCHG_CURRENT) ||
+	    (batt->flags & BATT_FLAG_BAD_CURRENT))
+		return;
+
+	if ((!ocp_throttle_start_time.val &&
+	     (batt->current < -BAT_MAX_DISCHG_CURRENT)) ||
+	    (ocp_throttle_start_time.val &&
+	     (batt->current < -BAT_MAX_DISCHG_CURRENT + BAT_OCP_HYSTERESIS))) {
+		ocp_throttle_start_time = get_time();
+		throttle_ap(THROTTLE_ON, THROTTLE_SOFT,
+			    THROTTLE_SRC_BAT_DISCHG_CURRENT);
+	} else if (ocp_throttle_start_time.val &&
+		   (get_time().val >
+		    ocp_throttle_start_time.val + BAT_OCP_TIMEOUT_US)) {
+		/*
+		 * Clear the timer and notify AP to stop throttling if
+		 * we haven't seen over current for BAT_OCP_TIMEOUT_US.
+		 */
+		ocp_throttle_start_time.val = 0;
+		throttle_ap(THROTTLE_OFF, THROTTLE_SOFT,
+			    THROTTLE_SRC_BAT_DISCHG_CURRENT);
+	}
+}
+
+const struct batt_params *charger_current_battery_params(void)
+{
+	return &curr.batt;
+}
+
+struct charge_state_data *charge_get_status(void)
+{
+	return &curr;
+}
+
+/* Determine if the battery is outside of allowable temperature range */
+int battery_outside_charging_temperature(void)
+{
+	const struct battery_info *batt_info = battery_get_info();
+	int batt_temp_c = DECI_KELVIN_TO_CELSIUS(curr.batt.temperature);
+	int max_c, min_c;
+
+	if (curr.batt.flags & BATT_FLAG_BAD_TEMPERATURE)
+		return 0;
+
+	if ((curr.batt.desired_voltage == 0) &&
+	    (curr.batt.desired_current == 0)) {
+		max_c = batt_info->start_charging_max_c;
+		min_c = batt_info->start_charging_min_c;
+	} else {
+		max_c = batt_info->charging_max_c;
+		min_c = batt_info->charging_min_c;
+	}
+
+	if ((batt_temp_c >= max_c) || (batt_temp_c <= min_c)) {
+		return 1;
+	}
+	return 0;
+}
+
+static enum ec_charge_control_mode
+sustain_switch_mode(enum ec_charge_control_mode mode)
+{
+	enum ec_charge_control_mode new_mode = mode;
+	int soc = charge_get_display_charge() / 10;
+
+	/*
+	 * The sustain range is defined by 'lower' and 'upper' where the equal
+	 * values are inclusive:
+	 *
+	 * |------------NORMAL------------+--IDLE--+---DISCHARGE---|
+	 * 0%                             ^        ^              100%
+	 *                              lower    upper
+	 *
+	 * The switch statement below allows the sustainer to start with any soc
+	 * (0% ~ 100%) and any previous lower & upper limits. It sets mode to
+	 * NORMAL to charge till the soc hits the upper limit or sets mode to
+	 * DISCHARGE to discharge till the soc hits the upper limit.
+	 *
+	 * Once the soc enters in the sustain range, it'll switch to IDLE. In
+	 * IDLE mode, the system power is supplied from the AC. Thus, the soc
+	 * normally should stay in the sustain range unless there is high load
+	 * on the system or the charger is too weak.
+	 *
+	 * Some boards have a sing capacitor problem with mode == IDLE. For such
+	 * boards, a host can specify EC_CHARGE_CONTROL_FLAG_NO_IDLE, which
+	 * makes the sustainer use DISCHARGE instead of IDLE. This is done by
+	 * setting lower != upper in V2, which doesn't support the flag.
+	 */
+	switch (mode) {
+	case CHARGE_CONTROL_NORMAL:
+		/* Currently charging */
+		if (sustain_soc.upper < soc) {
+			/*
+			 * We come here only if the soc is already above the
+			 * upper limit at the time the sustainer started.
+			 */
+			new_mode = CHARGE_CONTROL_DISCHARGE;
+		} else if (sustain_soc.upper == soc) {
+			/*
+			 * We've been charging and finally reached the upper.
+			 * Let's switch to IDLE to stay.
+			 */
+			if (sustain_soc.flags & EC_CHARGE_CONTROL_FLAG_NO_IDLE)
+				new_mode = CHARGE_CONTROL_DISCHARGE;
+			else
+				new_mode = CHARGE_CONTROL_IDLE;
+		}
+		break;
+	case CHARGE_CONTROL_IDLE:
+		/* Discharging naturally */
+		if (soc < sustain_soc.lower)
+			/*
+			 * Presumably, we stayed in the sustain range for a
+			 * while but finally fell off the range. Let's charge to
+			 * the upper.
+			 */
+			new_mode = CHARGE_CONTROL_NORMAL;
+		else if (sustain_soc.upper < soc)
+			/*
+			 * This can happen only if sustainer is restarted with
+			 * decreased upper limit. Let's discharge to the upper.
+			 */
+			new_mode = CHARGE_CONTROL_DISCHARGE;
+		break;
+	case CHARGE_CONTROL_DISCHARGE:
+		/* Discharging actively. */
+		if (soc <= sustain_soc.upper &&
+		    !(sustain_soc.flags & EC_CHARGE_CONTROL_FLAG_NO_IDLE))
+			/*
+			 * Normal case. We've been discharging and finally
+			 * reached the upper. Let's switch to IDLE to stay.
+			 */
+			new_mode = CHARGE_CONTROL_IDLE;
+		else if (soc < sustain_soc.lower)
+			/*
+			 * This can happen only if sustainer is restarted with
+			 * increase lower limit. Let's charge to the upper (then
+			 * switch to IDLE).
+			 */
+			new_mode = CHARGE_CONTROL_NORMAL;
+		break;
+	default:
+		break;
+	}
+
+	return new_mode;
+}
+
+static void sustain_battery_soc(void)
+{
+	enum ec_charge_control_mode mode = get_chg_ctrl_mode();
+	enum ec_charge_control_mode new_mode;
+	int rv;
+
+	/* If either AC or battery is not present, nothing to do. */
+	if (!curr.ac || curr.batt.is_present != BP_YES ||
+	    !battery_sustainer_enabled())
+		return;
+
+	new_mode = sustain_switch_mode(mode);
+
+	if (new_mode == mode)
+		return;
+
+	rv = set_chg_ctrl_mode(new_mode);
+	CPRINTS("%s: %s control mode to %s", __func__,
+		rv == EC_SUCCESS ? "Switched" : "Failed to switch",
+		mode_text[new_mode]);
+}
+
+static void current_limit_battery_soc(void)
+{
+	if (user_current_limit != current_limit.value &&
+	    charge_get_display_charge() / 10 >= current_limit.soc) {
+		user_current_limit = current_limit.value;
+		CPRINTS("Current limit %dmA applied", user_current_limit);
+	}
+}
+
+/*****************************************************************************/
+/* Hooks */
+void charger_init(void)
+{
+	/* Initialize current state */
+	memset(&curr, 0, sizeof(curr));
+	curr.batt.is_present = BP_NOT_SURE;
+	/* Manual voltage/current set to off */
+	local_state.manual_voltage = -1;
+	local_state.manual_current = -1;
+	/*
+	 * Other tasks read the params like state_of_charge at the beginning of
+	 * their tasks. Make them ready first.
+	 */
+	battery_get_params(&curr.batt);
+
+	battery_sustainer_disable();
+}
+DECLARE_HOOK(HOOK_INIT, charger_init, HOOK_PRIO_DEFAULT);
+
+void charge_wakeup(void)
+{
+	task_wake(TASK_ID_CHARGER);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, charge_wakeup, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_AC_CHANGE, charge_wakeup, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_POWER_SUPPLY_CHANGE, charge_wakeup, HOOK_PRIO_DEFAULT);
+
+#ifdef CONFIG_THROTTLE_AP_ON_BAT_VOLTAGE
+static void bat_low_voltage_throttle_reset(void)
+{
+	uvp_throttle_start_time.val = 0;
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, bat_low_voltage_throttle_reset,
+	     HOOK_PRIO_DEFAULT);
+#endif
+
+static int get_desired_input_current(enum battery_present batt_present,
+				     const struct charger_info *const info)
+{
+	if (batt_present == BP_YES || system_is_locked() || base_connected()) {
+#ifdef CONFIG_CHARGE_MANAGER
+		int ilim = charge_manager_get_charger_current();
+		return ilim == CHARGE_CURRENT_UNINITIALIZED ?
+			       CHARGE_CURRENT_UNINITIALIZED :
+			       MAX(CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT, ilim);
+#else
+		return CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT;
+#endif
+	} else {
+#ifdef CONFIG_USB_POWER_DELIVERY
+		return MIN(PD_MAX_CURRENT_MA, info->input_current_max);
+#else
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+		int ilim = charge_manager_get_charger_current();
+		return ilim == CHARGE_CURRENT_UNINITIALIZED ?
+			       CHARGE_CURRENT_UNINITIALIZED :
+			       MAX(CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT, ilim);
+#else
+		return info->input_current_max;
+#endif
+#endif
+	}
+}
+
+static void wakeup_battery(int *need_static)
+{
+	if (battery_seems_dead || battery_is_cut_off()) {
+		/* It's dead, do nothing */
+		set_charge_state(ST_IDLE);
+		curr.requested_voltage = 0;
+		curr.requested_current = 0;
+	} else if (curr.state == ST_PRECHARGE &&
+		   (get_time().val >
+		    precharge_start_time.val + PRECHARGE_TIMEOUT_US)) {
+		/* We've tried long enough, give up */
+		CPRINTS("battery seems to be dead");
+		battery_seems_dead = 1;
+		set_charge_state(ST_IDLE);
+		curr.requested_voltage = 0;
+		curr.requested_current = 0;
+	} else {
+		/* See if we can wake it up */
+		if (curr.state != ST_PRECHARGE) {
+			CPRINTS("try to wake battery");
+			precharge_start_time = get_time();
+			*need_static = 1;
+		}
+		set_charge_state(ST_PRECHARGE);
+		curr.requested_voltage = batt_info->voltage_max;
+		curr.requested_current = batt_info->precharge_current;
+	}
+}
+
+__test_only enum charge_state charge_get_state(void)
+{
+	return curr.state;
+}
+
+static void deep_charge_battery(int *need_static)
+{
+	if ((curr.state == ST_IDLE) &&
+	    (curr.batt.flags & BATT_FLAG_DEEP_CHARGE)) {
+		/* Deep charge time out , do nothing */
+		curr.requested_voltage = 0;
+		curr.requested_current = 0;
+	} else if (curr.state == ST_PRECHARGE &&
+		   (get_time().val >
+		    precharge_start_time.val +
+			    CONFIG_BATTERY_LOW_VOLTAGE_TIMEOUT)) {
+		/* We've tried long enough, give up */
+		CPRINTS("Precharge for low voltage timed out");
+		set_charge_state(ST_IDLE);
+		curr.requested_voltage = 0;
+		curr.requested_current = 0;
+	} else {
+		/* See if we can wake it up */
+		if (curr.state != ST_PRECHARGE) {
+			CPRINTS("Start precharge for low voltage");
+			precharge_start_time = get_time();
+			*need_static = 1;
+		}
+		set_charge_state(ST_PRECHARGE);
+		curr.requested_voltage = batt_info->voltage_max;
+		curr.requested_current = batt_info->precharge_current;
+		curr.batt.flags |= BATT_FLAG_DEEP_CHARGE;
+	}
+}
+
+static void revive_battery(int *need_static)
+{
+	if (IS_ENABLED(CONFIG_BATTERY_REQUESTS_NIL_WHEN_DEAD) &&
+	    curr.requested_voltage == 0 && curr.requested_current == 0 &&
+	    curr.batt.state_of_charge == 0) {
+		/*
+		 * Battery is dead, give precharge current
+		 * TODO (crosbug.com/p/29467): remove this workaround
+		 * for dead battery that requests no voltage/current
+		 */
+		curr.requested_voltage = batt_info->voltage_max;
+		curr.requested_current = batt_info->precharge_current;
+	} else if (IS_ENABLED(CONFIG_BATTERY_REVIVE_DISCONNECT) &&
+		   curr.requested_voltage == 0 && curr.requested_current == 0 &&
+		   battery_seems_disconnected) {
+		/*
+		 * Battery is in disconnect state. Apply a
+		 * current to kick it out of this state.
+		 */
+		CPRINTS("found battery in disconnect state");
+		curr.requested_voltage = batt_info->voltage_max;
+		curr.requested_current = batt_info->precharge_current;
+	} else if (curr.state == ST_PRECHARGE || battery_seems_dead ||
+		   battery_was_removed) {
+		CPRINTS("battery woke up");
+		/* Update the battery-specific values */
+		batt_info = battery_get_info();
+		*need_static = 1;
+	}
+
+	battery_seems_dead = battery_was_removed = 0;
+}
+
+/* Set up the initial state of the charger task */
+static void charger_setup(const struct charger_info *info)
+{
+	/* Get the battery-specific values */
+	batt_info = battery_get_info();
+
+	prev_ac = prev_charge = prev_disp_charge = -1;
+	local_state.chg_ctl_mode = CHARGE_CONTROL_NORMAL;
+	shutdown_target_time.val = 0UL;
+	battery_seems_dead = 0;
+	if (IS_ENABLED(CONFIG_EC_EC_COMM_BATTERY_CLIENT)) {
+		charger_base_setup();
+		charger_base_set_input_voltage(&curr,
+					       CHARGE_VOLTAGE_UNINITIALIZED);
+	}
+#ifdef CONFIG_OCPC
+	ocpc_init(&curr.ocpc);
+	charge_set_active_chg_chip(CHARGE_PORT_NONE);
+#endif /* CONFIG_OCPC */
+
+	/*
+	 * If system is not locked and we don't have a battery to live on,
+	 * then use max input current limit so that we can pull as much power
+	 * as needed.
+	 */
+	prev_bp = BP_NOT_INIT;
+	curr.desired_input_current =
+		get_desired_input_current(curr.batt.is_present, info);
+
+	if (IS_ENABLED(CONFIG_USB_PD_PREFER_MV)) {
+		/* init battery desired power */
+		desired_mw =
+			curr.batt.desired_current * curr.batt.desired_voltage;
+		/*
+		 * Battery charging current needs time to be stable when a
+		 * new charge happens. Start the timer so we can evaluate the
+		 * stable current when timeout.
+		 */
+		charge_reset_stable_current();
+	}
+
+	battery_level_shutdown = board_set_battery_level_shutdown();
+}
+
+/* check for and handle any state-of-charge change with the battery */
+void check_battery_change_soc(bool is_full, bool prev_full)
+{
+	if ((!(curr.batt.flags & BATT_FLAG_BAD_STATE_OF_CHARGE) &&
+	     curr.batt.state_of_charge != prev_charge) ||
+	    (IS_ENABLED(CONFIG_EC_EC_COMM_BATTERY_CLIENT) &&
+	     charger_base_charge_changed()) ||
+	    is_full != prev_full || (curr.state != prev_state) ||
+	    (charge_get_display_charge() != prev_disp_charge)) {
+		show_charging_progress(is_full);
+		prev_charge = curr.batt.state_of_charge;
+		prev_disp_charge = charge_get_display_charge();
+		if (IS_ENABLED(CONFIG_EC_EC_COMM_BATTERY_CLIENT))
+			charger_base_charge_update();
+		hook_notify(HOOK_BATTERY_SOC_CHANGE);
+	}
+}
+
+/* We've noticed a change in AC presence, let the board know */
+static void process_ac_change(const int chgnum)
+{
+	board_check_extpower();
+	if (curr.ac) {
+		/*
+		 * Some chargers are unpowered when the AC is off, so we'll
+		 * reinitialize it when AC comes back and set the input current
+		 * limit. Try again if it fails.
+		 */
+		int rv = charger_post_init();
+
+		if (rv != EC_SUCCESS) {
+			charge_problem(PR_POST_INIT, rv);
+		} else if (curr.desired_input_current !=
+			   CHARGE_CURRENT_UNINITIALIZED) {
+			rv = charger_set_input_current_limit(
+				chgnum, curr.desired_input_current);
+			if (rv != EC_SUCCESS)
+				charge_problem(PR_SET_INPUT_CURR, rv);
+		}
+
+		if (rv == EC_SUCCESS)
+			prev_ac = curr.ac;
+	} else {
+		/* Some things are only meaningful on AC */
+		set_chg_ctrl_mode(CHARGE_CONTROL_NORMAL);
+		battery_seems_dead = 0;
+		prev_ac = curr.ac;
+
+		/*
+		 * b/187967523, we should clear charge current, otherwise it
+		 * will affect typeC output. This should be ok for all chargers.
+		 */
+		charger_set_current(chgnum, 0);
+	}
+}
+
+/* Handle a change in the battery-present state */
+static void process_battery_present_change(const struct charger_info *info,
+					   int chgnum)
+{
+	prev_bp = curr.batt.is_present;
+
+	/* Update battery info due to change of battery */
+	batt_info = battery_get_info();
+
+	curr.desired_input_current = get_desired_input_current(prev_bp, info);
+	if (curr.desired_input_current != CHARGE_CURRENT_UNINITIALIZED)
+		charger_set_input_current_limit(chgnum,
+						curr.desired_input_current);
+	hook_notify(HOOK_BATTERY_SOC_CHANGE);
+}
+
+/* Decide on the charge state we are in */
+static void decide_charge_state(int *need_staticp, int *battery_criticalp)
+{
+	/* battery current stable now, so save the current. */
+	if (IS_ENABLED(CONFIG_USB_PD_PREFER_MV) &&
+	    get_time().val > stable_ts.val && curr.batt.current >= 0)
+		stable_current = curr.batt.current;
+
+	/*
+	 * Now decide what we want to do about it. We'll normally just pass
+	 * along whatever the battery wants to the charger. Note that if
+	 * battery_get_params() can't get valid values from the battery it uses
+	 * (0, 0), which is probably safer than blindly applying power to a
+	 * battery we can't talk to.
+	 */
+	if (curr.batt.flags &
+	    (BATT_FLAG_BAD_DESIRED_VOLTAGE | BATT_FLAG_BAD_DESIRED_CURRENT)) {
+		curr.requested_voltage = 0;
+		curr.requested_current = 0;
+	} else {
+		curr.requested_voltage = curr.batt.desired_voltage;
+		curr.requested_current = curr.batt.desired_current;
+	}
+
+	/* If we *know* there's no battery, wait for one to appear. */
+	if (curr.batt.is_present == BP_NO) {
+		if (!curr.ac)
+			CPRINTS("running with no battery and no AC");
+		set_charge_state(ST_IDLE);
+		curr.batt_is_charging = 0;
+		battery_was_removed = 1;
+		return;
+	}
+
+	/*
+	 * Always check the disconnect state if the battery is present. This is
+	 * because the battery disconnect state is one of the items used to
+	 * decide whether or not to leave safe mode.
+	 *
+	 * Note: For our purposes, an unresponsive battery is considered to be
+	 * disconnected
+	 */
+	battery_seems_disconnected = battery_get_disconnect_state() !=
+				     BATTERY_NOT_DISCONNECTED;
+
+	/*
+	 * If we had trouble talking to the battery or the charger, we should
+	 * probably do nothing for a bit, and if it doesn't get better then flag
+	 * it as an error.
+	 */
+	if (curr.chg.flags & CHG_FLAG_BAD_ANY)
+		charge_problem(PR_CHG_FLAGS, curr.chg.flags);
+	if (curr.batt.flags & BATT_FLAG_BAD_ANY)
+		charge_problem(PR_BATT_FLAGS, curr.batt.flags);
+
+	/*
+	 * If AC is present, check if input current is sufficient to actually
+	 * charge battery.
+	 */
+	curr.batt_is_charging = curr.ac && (curr.batt.current >= 0);
+
+	/* Don't let the battery hurt itself. */
+	*battery_criticalp = shutdown_on_critical_battery();
+
+	if (!curr.ac) {
+		set_charge_state(ST_DISCHARGE);
+		return;
+	}
+
+	/* Okay, we're on AC and we should have a battery. */
+
+	/* Used for factory tests. */
+	if (get_chg_ctrl_mode() != CHARGE_CONTROL_NORMAL) {
+		set_charge_state(ST_IDLE);
+		return;
+	}
+
+	/* If the battery is not responsive, try to wake it up. */
+	if (!(curr.batt.flags & BATT_FLAG_RESPONSIVE)) {
+		wakeup_battery(need_staticp);
+		return;
+	}
+
+	/*
+	 * When the battery voltage is lower than voltage_min,precharge first to
+	 * protect the battery
+	 */
+	if (IS_ENABLED(CONFIG_BATTERY_LOW_VOLTAGE_PROTECTION)) {
+		if (!(curr.batt.flags & BATT_FLAG_BAD_VOLTAGE) &&
+		    curr.batt.voltage <= batt_info->voltage_min) {
+			deep_charge_battery(need_staticp);
+			return;
+		}
+
+		/*
+		 * Finished deep charge before timeout. Clear the flag so that
+		 * we can do deep charge again (when it's deeply discharged
+		 * again).
+		 */
+		if ((curr.batt.flags & BATT_FLAG_DEEP_CHARGE))
+			curr.batt.flags &= ~BATT_FLAG_DEEP_CHARGE;
+	}
+	/* The battery is responding. Yay. Try to use it. */
+
+	revive_battery(need_staticp);
+
+	set_charge_state(ST_CHARGE);
+}
+
+/* Determine voltage/current to request and make it so */
+static void adjust_requested_vi(const struct charger_info *const info,
+				bool is_full)
+{
+	/* Turn charger off if it's not needed */
+	if (!IS_ENABLED(CONFIG_CHARGER_MAINTAIN_VBAT) &&
+	    (curr.state == ST_IDLE || curr.state == ST_DISCHARGE)) {
+		curr.requested_voltage = 0;
+		curr.requested_current = 0;
+	}
+
+	/* Apply external limits */
+	if (curr.requested_current > user_current_limit)
+		curr.requested_current = user_current_limit;
+
+	/* Round to valid values */
+	curr.requested_voltage =
+		charger_closest_voltage(curr.requested_voltage);
+	curr.requested_current =
+		charger_closest_current(curr.requested_current);
+
+	/* Charger only accepts request when AC is on. */
+	if (curr.ac) {
+		/*
+		 * Some batteries would wake up after cut-off if we keep
+		 * charging it. Thus, we only charge when AC is on and battery
+		 * is not cut off yet.
+		 */
+		if (battery_is_cut_off()) {
+			curr.requested_voltage = 0;
+			curr.requested_current = 0;
+		}
+		/*
+		 * As a safety feature, some chargers will stop charging if we
+		 * don't communicate with it frequently enough. In manual mode,
+		 * we'll just tell it what it knows.
+		 */
+		else {
+			if (local_state.manual_voltage != -1)
+				curr.requested_voltage =
+					local_state.manual_voltage;
+			if (local_state.manual_current != -1)
+				curr.requested_current =
+					local_state.manual_current;
+		}
+	} else if (!IS_ENABLED(CONFIG_CHARGER_MAINTAIN_VBAT)) {
+		curr.requested_voltage = charger_closest_voltage(
+			curr.batt.voltage + info->voltage_step);
+		curr.requested_current = -1;
+		/*
+		 * On EC-EC server, do not charge if curr.ac is 0: there might
+		 * still be some external power available but we do not want to
+		 * use it for charging.
+		 */
+		if (IS_ENABLED(CONFIG_EC_EC_COMM_BATTERY_SERVER))
+			curr.requested_current = 0;
+	}
+
+	if (IS_ENABLED(CONFIG_EC_EC_COMM_BATTERY_CLIENT)) {
+		base_charge_allocate_input_current_limit(&curr, is_full,
+							 debugging());
+	} else {
+		charge_request(true, is_full);
+	}
+}
+
+/* Handle selection of the preferred voltage */
+static void process_preferred_voltage(void)
+{
+	int is_pd_supply;
+	int port;
+	int bat_spec_desired_mw;
+	int prev_plt_and_desired_mw;
+
+	/* sjg@: Attempt to get code coverage on this function b/281109948 */
+	if (!IS_ENABLED(CONFIG_USB_PD_PREFER_MV))
+		return;
+
+	is_pd_supply = charge_manager_get_supplier() == CHARGE_SUPPLIER_PD;
+	port = charge_manager_get_active_charge_port();
+	bat_spec_desired_mw =
+		curr.batt.desired_current * curr.batt.desired_voltage / 1000;
+
+	/* save previous plt_and_desired_mw, since it will be updated below */
+	prev_plt_and_desired_mw = charge_get_plt_plus_bat_desired_mw();
+
+	/*
+	 * Update desired power by the following rules:
+	 * 1. If the battery is not charging with PD, we reset the desired_mw to
+	 * the battery spec. The actual desired_mw will be evaluated when it
+	 * starts charging with PD again.
+	 * 2. If the battery SoC under battery's constant voltage percent (this
+	 * is a rough value that can be applied to most batteries), the battery
+	 * can fully sink the power, the desired power should be the same as the
+	 * battery spec, and we don't need to use evaluated value
+	 * stable_current.
+	 * 3. If the battery SoC is above battery's constant voltage percent,
+	 * the real battery desired charging power will decrease slowly and so
+	 * does the charging current. We can evaluate the battery desired power
+	 * by the product of stable_current and battery voltage.
+	 */
+	if (!is_pd_supply)
+		desired_mw = bat_spec_desired_mw;
+	else if (curr.batt.state_of_charge < pd_pref_config.cv)
+		desired_mw = bat_spec_desired_mw;
+	else if (stable_current != CHARGE_CURRENT_UNINITIALIZED)
+		desired_mw = curr.batt.voltage * stable_current / 1000;
+
+	/* if the plt_and_desired_mw changes, re-evaluate PDO */
+	if (is_pd_supply &&
+	    prev_plt_and_desired_mw != charge_get_plt_plus_bat_desired_mw())
+		pd_set_new_power_request(port);
+}
+
+/* Calculate the sleep duration, before we run around the task loop again */
+int calculate_sleep_dur(int battery_critical, int sleep_usec)
+{
+	/* How long to sleep? */
+	if (problems_exist) {
+		/* If there are errors, don't wait very long. */
+		sleep_usec = CHARGE_POLL_PERIOD_SHORT;
+	} else if (sleep_usec <= 0) {
+		/* default values depend on the state */
+		if (!curr.ac &&
+		    (curr.state == ST_IDLE || curr.state == ST_DISCHARGE)) {
+#ifdef CONFIG_CHARGER_OTG
+			int output_current = curr.output_current;
+#else
+			int output_current = 0;
+#endif
+			/*
+			 * If AP is off and we do not provide power, we can
+			 * sleep a long time.
+			 */
+			if (chipset_in_state(CHIPSET_STATE_ANY_OFF |
+					     CHIPSET_STATE_ANY_SUSPEND) &&
+			    output_current == 0)
+				sleep_usec = CHARGE_POLL_PERIOD_VERY_LONG;
+			else
+#ifndef CONFIG_CUSTOMIZED_DESIGN
+				/* Discharging, not too urgent */
+				sleep_usec = CHARGE_POLL_PERIOD_LONG;
+#else
+				sleep_usec = CHARGE_POLL_PERIOD_CHARGE;
+#endif
+		} else {
+			/* AC present, so pay closer attention */
+			sleep_usec = CHARGE_POLL_PERIOD_CHARGE;
+		}
+	}
+
+	/* Adjust for time spent in the charge loop */
+	sleep_usec -= (int)(get_time().val - curr.ts.val);
+	if (sleep_usec < CHARGE_MIN_SLEEP_USEC)
+		sleep_usec = CHARGE_MIN_SLEEP_USEC;
+	else if (sleep_usec > CHARGE_MAX_SLEEP_USEC)
+		sleep_usec = CHARGE_MAX_SLEEP_USEC;
+
+	/*
+	 * If battery is critical, ensure that the sleep time is not very long
+	 * since we might want to hibernate or cut-off battery sooner.
+	 */
+	if (battery_critical &&
+	    (sleep_usec > CRITICAL_BATTERY_SHUTDOWN_TIMEOUT_US))
+		sleep_usec = CRITICAL_BATTERY_SHUTDOWN_TIMEOUT_US;
+
+	return sleep_usec;
+}
+
+/* check external power and set curr.ac */
+static void check_extpower(int chgnum)
+{
+	curr.ac = extpower_is_present();
+	if (IS_ENABLED(CONFIG_EC_EC_COMM_BATTERY_CLIENT)) {
+		if (base_check_extpower(curr.ac, prev_ac))
+			curr.ac = 0;
+	}
+}
+
+/* processing for new charge state, returning updated sleep_usec */
+static int process_charge_state(int *need_staticp, int sleep_usec)
+{
+	if (IS_ENABLED(CONFIG_CHARGER_PROFILE_OVERRIDE) &&
+	    get_chg_ctrl_mode() == CHARGE_CONTROL_NORMAL) {
+		sleep_usec = charger_profile_override(&curr);
+		if (sleep_usec < 0)
+			charge_problem(PR_CUSTOM, sleep_usec);
+	}
+
+	if (IS_ENABLED(CONFIG_BATTERY_CHECK_CHARGE_TEMP_LIMITS) &&
+	    battery_outside_charging_temperature()) {
+		curr.requested_current = 0;
+		curr.requested_voltage = 0;
+		curr.batt.flags &= ~BATT_FLAG_WANT_CHARGE;
+		if (curr.state != ST_DISCHARGE)
+			curr.state = ST_IDLE;
+	}
+
+	if (IS_ENABLED(CONFIG_CHARGE_MANAGER) &&
+	    curr.batt.state_of_charge >=
+		    CONFIG_CHARGE_MANAGER_BAT_PCT_SAFE_MODE_EXIT &&
+	    !battery_seems_disconnected)
+		charge_manager_leave_safe_mode();
+
+	/* Keep the AP informed */
+	if (*need_staticp)
+		*need_staticp = update_static_battery_info();
+
+	/* Wait on the dynamic info until the static info is good. */
+	if (!*need_staticp)
+		update_dynamic_battery_info();
+	notify_host_of_low_battery_charge();
+	notify_host_of_low_battery_voltage();
+
+	return sleep_usec;
+}
+
+/* Main loop */
+void charger_task(void *u)
+{
+	int sleep_usec;
+	int battery_critical;
+	int need_static = 1;
+	const struct charger_info *const info = charger_get_info();
+	int chgnum = 0;
+	bool is_full = false; /* battery not accepting current */
+	bool prev_full = false;
+
+	/* Set up the task - note that charger_init() has already run. */
+	charger_setup(info);
+
+	while (1) {
+		/* Let's see what's going on... */
+		curr.ts = get_time();
+		sleep_usec = 0;
+		problems_exist = 0;
+		battery_critical = 0;
+
+		check_extpower(chgnum);
+		if (curr.ac != prev_ac)
+			process_ac_change(chgnum);
+
+		if (IS_ENABLED(CONFIG_EC_EC_COMM_BATTERY_CLIENT))
+			base_update_battery_info();
+
+		charger_get_params(&curr.chg);
+		battery_get_params(&curr.batt);
+
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+		battery_customize(&curr);
+#endif
+
+#ifdef CONFIG_OCPC
+		if (curr.ac)
+			ocpc_get_adcs(&curr.ocpc);
+#endif /* CONFIG_OCPC */
+
+		if (prev_bp != curr.batt.is_present) {
+			process_battery_present_change(info, chgnum);
+			need_static = 1;
+		}
+
+		battery_validate_params(&curr.batt);
+
+		notify_host_of_over_current(&curr.batt);
+
+		decide_charge_state(&need_static, &battery_critical);
+		sleep_usec = process_charge_state(&need_static, sleep_usec);
+
+		/* And the EC console */
+		is_full = calc_is_full();
+
+		/* Run battery sustainer (no-op if not applicable). */
+		sustain_battery_soc();
+
+		/* Run battery soc check for setting the current limit. */
+		current_limit_battery_soc();
+
+		check_battery_change_soc(is_full, prev_full);
+
+		prev_full = is_full;
+
+		adjust_requested_vi(info, is_full);
+
+		process_preferred_voltage();
+
+		/* Report our state */
+		local_state.is_full = is_full;
+
+		sleep_usec = calculate_sleep_dur(battery_critical, sleep_usec);
+		task_wait_event(sleep_usec);
+	}
+}
+
+/*****************************************************************************/
+/* Exported functions */
+
+int charge_want_shutdown(void)
+{
+	return (curr.state == ST_DISCHARGE) &&
+	       !(curr.batt.flags & BATT_FLAG_BAD_STATE_OF_CHARGE) &&
+	       (curr.batt.state_of_charge < battery_level_shutdown);
+}
+
+#ifdef CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON
+test_export_static int charge_prevent_power_on_automatic_power_on = 1;
+#endif
+
+bool charge_prevent_power_on(bool power_button_pressed)
+{
+	int prevent_power_on = 0;
+	struct batt_params params;
+	struct batt_params *current_batt_params = &curr.batt;
+
+	/* If battery params seem uninitialized then retrieve them */
+	if (current_batt_params->is_present == BP_NOT_SURE) {
+		battery_get_params(&params);
+		current_batt_params = &params;
+	}
+
+#ifdef CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON
+
+	/*
+	 * Remember that a power button was pressed, and assume subsequent
+	 * power-ups are user-requested and non-automatic.
+	 */
+	if (power_button_pressed)
+		charge_prevent_power_on_automatic_power_on = 0;
+	/*
+	 * Require a minimum battery level to power on and ensure that the
+	 * battery can provide power to the system.
+	 */
+	if (current_batt_params->is_present != BP_YES ||
+#ifdef CONFIG_BATTERY_MEASURE_IMBALANCE
+	    (current_batt_params->flags & BATT_FLAG_IMBALANCED_CELL &&
+	     current_batt_params->state_of_charge <
+		     CONFIG_CHARGER_MIN_BAT_PCT_IMBALANCED_POWER_ON) ||
+#endif
+#ifdef CONFIG_BATTERY_REVIVE_DISCONNECT
+	    battery_get_disconnect_state() != BATTERY_NOT_DISCONNECTED ||
+#endif
+	    current_batt_params->state_of_charge <
+		    CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON)
+		prevent_power_on = 1;
+
+#if defined(CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON) && \
+	defined(CONFIG_CHARGE_MANAGER)
+	/* However, we can power on if a sufficient charger is present. */
+	if (prevent_power_on) {
+		if (charge_manager_get_power_limit_uw() >=
+		    CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON * 1000)
+			prevent_power_on = 0;
+#if defined(CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT) && \
+	defined(CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC)
+		else if (charge_manager_get_power_limit_uw() >=
+				 CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT *
+					 1000
+#ifdef CONFIG_BATTERY_REVIVE_DISCONNECT
+			 && battery_get_disconnect_state() ==
+				    BATTERY_NOT_DISCONNECTED
+#endif
+			 && (current_batt_params->state_of_charge >=
+			     CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC))
+			prevent_power_on = 0;
+#endif
+	}
+#endif /* CONFIG_CHARGE_MANAGER && CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON */
+
+	/*
+	 * Factory override: Always allow power on if WP is disabled,
+	 * except when auto-power-on at EC startup and the battery
+	 * is physically present.
+	 */
+	prevent_power_on &= (system_is_locked() ||
+			     (charge_prevent_power_on_automatic_power_on
+#ifdef CONFIG_BATTERY_HW_PRESENT_CUSTOM
+
+			      && battery_hw_present() == BP_YES
+#endif
+			      ));
+#endif /* CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON */
+
+#ifdef CONFIG_CHARGE_MANAGER
+	/* Always prevent power on until charge current is initialized */
+	if (extpower_is_present() && (charge_manager_get_charger_current() ==
+				      CHARGE_CURRENT_UNINITIALIZED))
+		prevent_power_on = 1;
+#ifdef CONFIG_BATTERY_HW_PRESENT_CUSTOM
+	/*
+	 * If battery is NOT physically present then prevent power on until
+	 * a sufficient charger is present.
+	 */
+	if (extpower_is_present() && battery_hw_present() == BP_NO
+#ifdef CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
+	    && charge_manager_get_power_limit_uw() <
+		       CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON * 1000
+#endif /* CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON */
+	)
+		prevent_power_on = 1;
+#endif /* CONFIG_BATTERY_HW_PRESENT_CUSTOM */
+#endif /* CONFIG_CHARGE_MANAGER */
+
+		/*
+		 * Prevent power on if there is no battery nor ac power. This
+		 * happens when the servo is powering the EC to flash it. Only
+		 * include this logic for boards in initial bring up phase since
+		 * this won't happen for released boards.
+		 */
+#ifdef CONFIG_SYSTEM_UNLOCKED
+	if (!current_batt_params->is_present && !curr.ac)
+		prevent_power_on = 1;
+#endif /* CONFIG_SYSTEM_UNLOCKED */
+
+	return prevent_power_on != 0;
+}
+
+static int battery_near_full(void)
+{
+	if (charge_get_display_charge() < 1000)
+		return 0;
+
+	if (IS_ENABLED(CONFIG_EC_EC_COMM_BATTERY_CLIENT) &&
+	    !charger_base_charge_near_full())
+		return 0;
+
+	return 1;
+}
+
+enum led_pwr_state led_pwr_get_state(void)
+{
+	uint32_t chflags;
+
+	switch (curr.state) {
+	case ST_IDLE:
+		chflags = charge_get_flags();
+
+		if (battery_seems_dead || curr.batt.is_present == BP_NO)
+			return LED_PWRS_ERROR;
+
+		if (chflags & CHARGE_FLAG_FORCE_IDLE)
+			return LED_PWRS_FORCED_IDLE;
+		else
+			return LED_PWRS_IDLE;
+	case ST_DISCHARGE:
+#ifdef CONFIG_PWR_STATE_DISCHARGE_FULL
+		if (battery_near_full())
+			return LED_PWRS_DISCHARGE_FULL;
+		else
+#endif
+			return LED_PWRS_DISCHARGE;
+	case ST_CHARGE:
+		/* The only difference here is what the LEDs display. */
+		if (IS_ENABLED(CONFIG_CHARGE_MANAGER) &&
+		    charge_manager_get_active_charge_port() == CHARGE_PORT_NONE)
+			return LED_PWRS_DISCHARGE;
+		else if (battery_near_full())
+			return LED_PWRS_CHARGE_NEAR_FULL;
+		else
+			return LED_PWRS_CHARGE;
+	case ST_PRECHARGE:
+		chflags = charge_get_flags();
+
+		/* we're in battery discovery mode */
+		if (chflags & CHARGE_FLAG_FORCE_IDLE)
+			return LED_PWRS_FORCED_IDLE;
+		else
+			return LED_PWRS_IDLE;
+	default:
+		/* Anything else can be considered an error for LED purposes */
+		return LED_PWRS_ERROR;
+	}
+}
+
+uint32_t charge_get_flags(void)
+{
+	uint32_t flags = 0;
+
+	if (get_chg_ctrl_mode() != CHARGE_CONTROL_NORMAL)
+		flags |= CHARGE_FLAG_FORCE_IDLE;
+	if (curr.ac)
+		flags |= CHARGE_FLAG_EXTERNAL_POWER;
+	if (curr.batt.flags & BATT_FLAG_RESPONSIVE)
+		flags |= CHARGE_FLAG_BATT_RESPONSIVE;
+
+	return flags;
+}
+
+int charge_get_percent(void)
+{
+	/*
+	 * Since there's no way to indicate an error to the caller, we'll just
+	 * return the last known value. Even if we've never been able to talk
+	 * to the battery, that'll be zero, which is probably as good as
+	 * anything.
+	 */
+	return local_state.is_full ? 100 : curr.batt.state_of_charge;
+}
+
+test_mockable int charge_get_display_charge(void)
+{
+	return curr.batt.display_charge;
+}
+
+int charge_get_battery_temp(int idx, int *temp_ptr)
+{
+	if (curr.batt.flags & BATT_FLAG_BAD_TEMPERATURE)
+		return EC_ERROR_UNKNOWN;
+
+	/* Battery temp is 10ths of degrees K, temp wants degrees K */
+	*temp_ptr = curr.batt.temperature / 10;
+	return EC_SUCCESS;
+}
+
+__overridable int charge_is_consuming_full_input_current(void)
+{
+	int chg_pct = charge_get_percent();
+
+	return chg_pct > 2 && chg_pct < 95;
+}
+
+#ifdef CONFIG_CHARGER_OTG
+int charge_set_output_current_limit(int chgnum, int ma, int mv)
+{
+	int ret;
+	int enable = ma > 0;
+
+	if (enable) {
+		ret = charger_set_otg_current_voltage(chgnum, ma, mv);
+		if (ret != EC_SUCCESS)
+			return ret;
+	}
+
+	ret = charger_enable_otg_power(chgnum, enable);
+	if (ret != EC_SUCCESS)
+		return ret;
+
+	/* If we start/stop providing power, wake the charger task. */
+	if ((curr.output_current == 0 && enable) ||
+	    (curr.output_current > 0 && !enable))
+		task_wake(TASK_ID_CHARGER);
+
+	curr.output_current = ma;
+
+	return EC_SUCCESS;
+}
+#endif
+
+int charge_set_input_current_limit(int ma, int mv)
+{
+	__maybe_unused int chgnum = 0;
+
+#ifdef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+	if (CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT != 0) {
+		ma = (ma * (100 - CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT)) /
+		     100;
+	}
+#endif
+#ifdef CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT
+	if (CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT > 0) {
+		ma = MAX(ma, CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT);
+	}
+#endif
+
+	if (IS_ENABLED(CONFIG_OCPC))
+		chgnum = charge_get_active_chg_chip();
+	if (IS_ENABLED(CONFIG_EC_EC_COMM_BATTERY_CLIENT))
+		charger_base_set_input_voltage(&curr, mv);
+	/*
+	 * If battery is not present, we are not locked, and base is not
+	 * connected then allow system to pull as much input current as needed.
+	 * Yes, we might overcurrent the charger but this is no worse than
+	 * browning out due to insufficient input current.
+	 */
+	if (curr.batt.is_present != BP_YES && !system_is_locked() &&
+	    !base_connected()) {
+		int prev_input = 0;
+
+		charger_get_input_current_limit(chgnum, &prev_input);
+
+#ifdef CONFIG_USB_POWER_DELIVERY
+#if ((PD_MAX_POWER_MW * 1000) / PD_MAX_VOLTAGE_MV != PD_MAX_CURRENT_MA)
+		/*
+		 * If battery is not present, input current is set to
+		 * PD_MAX_CURRENT_MA. If the input power set is greater than
+		 * the maximum allowed system power, system might get damaged.
+		 * Hence, limit the input current to meet maximum allowed
+		 * input system power.
+		 */
+
+		if (mv > 0 &&
+		    mv * curr.desired_input_current > PD_MAX_POWER_MW * 1000)
+			ma = (PD_MAX_POWER_MW * 1000) / mv;
+		/*
+		 * If the active charger has already been initialized to at
+		 * least this current level, nothing left to do.
+		 */
+		else if (prev_input >= ma)
+			return EC_SUCCESS;
+#else
+		if (prev_input >= ma)
+			return EC_SUCCESS;
+#endif
+			/*
+			 * If the current needs lowered due to PD max power
+			 * considerations, or needs raised for the selected
+			 * active charger chip, fall through to set.
+			 */
+#endif /* CONFIG_USB_POWER_DELIVERY */
+	}
+
+#ifdef CONFIG_CHARGER_MAX_INPUT_CURRENT
+	/* Limit input current limit to max limit for this board */
+	ma = MIN(ma, CONFIG_CHARGER_MAX_INPUT_CURRENT);
+#endif
+
+#if !defined(CONFIG_CHARGER_BYPASS_MODE) || !defined(CONFIG_CUSTOMIZED_DESIGN)
+	if (IS_ENABLED(CONFIG_CHARGE_MANAGER)) {
+		int pd_current_uncapped =
+			charge_manager_get_pd_current_uncapped();
+
+		/*
+		 * clamp the input current to not exceeded the PD's limitation.
+		 */
+		if (pd_current_uncapped != CHARGE_CURRENT_UNINITIALIZED &&
+		    ma > pd_current_uncapped)
+			ma = pd_current_uncapped;
+	}
+#endif
+
+	curr.desired_input_current = ma;
+	if (IS_ENABLED(CONFIG_EC_EC_COMM_BATTERY_CLIENT)) {
+		/*
+		 * Wake up charger task to allocate current between lid and
+		 * base.
+		 */
+		charge_wakeup();
+		return EC_SUCCESS;
+	} else {
+		return charger_set_input_current_limit(chgnum, ma);
+	}
+}
+
+#ifdef CONFIG_OCPC
+void charge_set_active_chg_chip(int idx)
+{
+	ASSERT(idx < (int)board_get_charger_chip_count());
+
+	if (idx == curr.ocpc.active_chg_chip)
+		return;
+
+	CPRINTS("Act Chg: %d", idx);
+	curr.ocpc.active_chg_chip = idx;
+}
+#endif /* CONFIG_OCPC */
+
+int charge_get_active_chg_chip(void)
+{
+#ifdef CONFIG_OCPC
+	return curr.ocpc.active_chg_chip;
+#else
+	return 0;
+#endif
+}
+
+#ifdef CONFIG_USB_PD_PREFER_MV
+bool charge_is_current_stable(void)
+{
+	return get_time().val >= stable_ts.val;
+}
+
+int charge_get_plt_plus_bat_desired_mw(void)
+{
+	/*
+	 * Ideally, the system consuming power could be evaluated by
+	 * "IBus * VBus - battery charging power". But in practice,
+	 * most charger drivers don't implement IBUS ADC reading,
+	 * so we use system PLT instead as an alterntaive approach.
+	 */
+	return pd_pref_config.plt_mw + desired_mw;
+}
+
+int charge_get_stable_current(void)
+{
+	return stable_current;
+}
+
+void charge_set_stable_current(int ma)
+{
+	stable_current = ma;
+}
+
+void charge_reset_stable_current_us(uint64_t us)
+{
+	timestamp_t now = get_time();
+
+	if (stable_ts.val < now.val + us)
+		stable_ts.val = now.val + us;
+
+	stable_current = CHARGE_CURRENT_UNINITIALIZED;
+}
+
+void charge_reset_stable_current(void)
+{
+	/* it takes 8 to 10 seconds to stabilize battery current in practice */
+	charge_reset_stable_current_us(10 * SECOND);
+}
+#endif
+
+#ifdef CONFIG_OCPC
+void trigger_ocpc_reset(void)
+{
+	ocpc_reset(&curr.ocpc);
+}
+#endif
+
+/*****************************************************************************/
+/* Host commands */
+
+static enum ec_status
+charge_command_charge_control(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_charge_control *p = args->params;
+	struct ec_response_charge_control *r = args->response;
+	int rv;
+
+	if (p->cmd == EC_CHARGE_CONTROL_CMD_SET) {
+		if (p->mode == CHARGE_CONTROL_NORMAL) {
+			rv = battery_sustainer_set(p->sustain_soc.lower,
+						   p->sustain_soc.upper);
+			if (rv == EC_RES_UNAVAILABLE)
+				return EC_RES_UNAVAILABLE;
+			if (rv)
+				return EC_RES_INVALID_PARAM;
+			if (args->version == 2) {
+				/*
+				 * V2 uses lower == upper to indicate NO_IDLE.
+				 * TODO: Remove this if-branch once all OS-side
+				 * components are updated to v3.
+				 */
+				if (sustain_soc.lower < sustain_soc.upper)
+					sustain_soc.flags =
+						EC_CHARGE_CONTROL_FLAG_NO_IDLE;
+			} else {
+				sustain_soc.flags = p->flags;
+			}
+		} else {
+			battery_sustainer_disable();
+		}
+	} else if (p->cmd == EC_CHARGE_CONTROL_CMD_GET) {
+		r->mode = get_chg_ctrl_mode();
+		r->sustain_soc.lower = sustain_soc.lower;
+		r->sustain_soc.upper = sustain_soc.upper;
+		if (args->version > 2)
+			r->flags = sustain_soc.flags;
+		args->response_size = sizeof(*r);
+		return EC_RES_SUCCESS;
+	} else {
+		return EC_RES_INVALID_PARAM;
+	}
+
+	rv = set_chg_ctrl_mode(p->mode);
+	if (rv != EC_SUCCESS)
+		return EC_RES_ERROR;
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_CHARGE_CONTROL, charge_command_charge_control,
+		     EC_VER_MASK(2) | EC_VER_MASK(3));
+
+static enum ec_status
+charge_command_current_limit(struct host_cmd_handler_args *args)
+{
+	if (args->version == 0) {
+		const struct ec_params_current_limit *p = args->params;
+		user_current_limit = p->limit;
+		current_limit.value = p->limit;
+	} else {
+		const struct ec_params_current_limit_v1 *p = args->params;
+
+		/* Check if battery state of charge param is within range */
+		if (p->battery_soc > 100) {
+			CPRINTS("Invalid battery_soc: %d", p->battery_soc);
+			return EC_RES_INVALID_PARAM;
+		}
+
+		current_limit.value = p->limit;
+		current_limit.soc = p->battery_soc;
+	}
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_CHARGE_CURRENT_LIMIT, charge_command_current_limit,
+		     EC_VER_MASK(0) | EC_VER_MASK(1));
+
+/*
+ * Expose charge/battery related state
+ *
+ * @param param command to get corresponding data
+ * @param value the corresponding data
+ * @return EC_SUCCESS or error
+ */
+static int charge_get_charge_state_debug(int param, uint32_t *value)
+{
+	switch (param) {
+	case CS_PARAM_DEBUG_CTL_MODE:
+		*value = get_chg_ctrl_mode();
+		break;
+	case CS_PARAM_DEBUG_MANUAL_CURRENT:
+		*value = local_state.manual_current;
+		break;
+	case CS_PARAM_DEBUG_MANUAL_VOLTAGE:
+		*value = local_state.manual_voltage;
+		break;
+	case CS_PARAM_DEBUG_SEEMS_DEAD:
+		*value = battery_seems_dead;
+		break;
+	case CS_PARAM_DEBUG_SEEMS_DISCONNECTED:
+		*value = battery_seems_disconnected;
+		break;
+	case CS_PARAM_DEBUG_BATT_REMOVED:
+		*value = battery_was_removed;
+		break;
+	default:
+		*value = 0;
+		return EC_ERROR_INVAL;
+	}
+
+	return EC_SUCCESS;
+}
+
+static enum ec_status
+charge_command_charge_state(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_charge_state *in = args->params;
+	struct ec_response_charge_state *out = args->response;
+	uint32_t val;
+	int rv = EC_RES_SUCCESS;
+	int chgnum = 0;
+
+	if (args->version > 0)
+		chgnum = in->chgnum;
+
+	switch (in->cmd) {
+	case CHARGE_STATE_CMD_GET_STATE:
+		out->get_state.ac = curr.ac;
+		out->get_state.chg_voltage = curr.chg.voltage;
+		out->get_state.chg_current = curr.chg.current;
+		out->get_state.chg_input_current = curr.chg.input_current;
+		out->get_state.batt_state_of_charge = curr.batt.state_of_charge;
+		args->response_size = sizeof(out->get_state);
+		break;
+
+	case CHARGE_STATE_CMD_GET_PARAM:
+		val = 0;
+		if (IS_ENABLED(CONFIG_CHARGER_PROFILE_OVERRIDE) &&
+		    in->get_param.param >= CS_PARAM_CUSTOM_PROFILE_MIN &&
+		    in->get_param.param <= CS_PARAM_CUSTOM_PROFILE_MAX) {
+			/* custom profile params */
+			rv = charger_profile_override_get_param(
+				in->get_param.param, &val);
+		} else if (IS_ENABLED(CONFIG_CHARGE_STATE_DEBUG) &&
+			   in->get_param.param >= CS_PARAM_DEBUG_MIN &&
+			   in->get_param.param <= CS_PARAM_DEBUG_MAX) {
+			/* debug params */
+			rv = charge_get_charge_state_debug(in->get_param.param,
+							   &val);
+		} else {
+			/* standard params */
+			switch (in->get_param.param) {
+			case CS_PARAM_CHG_VOLTAGE:
+				val = curr.chg.voltage;
+				break;
+			case CS_PARAM_CHG_CURRENT:
+				val = curr.chg.current;
+				break;
+			case CS_PARAM_CHG_INPUT_CURRENT:
+				val = curr.chg.input_current;
+				break;
+			case CS_PARAM_CHG_STATUS:
+				val = curr.chg.status;
+				break;
+			case CS_PARAM_CHG_OPTION:
+				val = curr.chg.option;
+				break;
+			case CS_PARAM_LIMIT_POWER:
+#ifdef CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW
+				/*
+				 * LIMIT_POWER status is based on battery level
+				 * and external charger power.
+				 */
+				if ((curr.batt.is_present != BP_YES ||
+				     curr.batt.state_of_charge <
+					     CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT) &&
+				    charge_manager_get_power_limit_uw() <
+					    CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW *
+						    1000 &&
+				    system_is_locked())
+					val = 1;
+				else
+#endif
+					val = 0;
+				break;
+			default:
+				rv = EC_RES_INVALID_PARAM;
+			}
+		}
+
+		/* got something */
+		out->get_param.value = val;
+		args->response_size = sizeof(out->get_param);
+		break;
+
+	case CHARGE_STATE_CMD_SET_PARAM:
+		if (system_is_locked())
+			return EC_RES_ACCESS_DENIED;
+
+		val = in->set_param.value;
+		if (IS_ENABLED(CONFIG_CHARGER_PROFILE_OVERRIDE) &&
+		    in->set_param.param >= CS_PARAM_CUSTOM_PROFILE_MIN &&
+		    in->set_param.param <= CS_PARAM_CUSTOM_PROFILE_MAX) {
+			/* custom profile params */
+			rv = charger_profile_override_set_param(
+				in->set_param.param, val);
+		} else {
+			switch (in->set_param.param) {
+			case CS_PARAM_CHG_VOLTAGE:
+				chgstate_set_manual_voltage(val);
+				break;
+			case CS_PARAM_CHG_CURRENT:
+				chgstate_set_manual_current(val);
+				break;
+			case CS_PARAM_CHG_INPUT_CURRENT:
+				if (charger_set_input_current_limit(chgnum,
+								    val))
+					rv = EC_RES_ERROR;
+				break;
+			case CS_PARAM_CHG_STATUS:
+			case CS_PARAM_LIMIT_POWER:
+				/* Can't set this */
+				rv = EC_RES_ACCESS_DENIED;
+				break;
+			case CS_PARAM_CHG_OPTION:
+				if (charger_set_option(val))
+					rv = EC_RES_ERROR;
+				break;
+			default:
+				rv = EC_RES_INVALID_PARAM;
+			}
+		}
+		break;
+
+	default:
+		CPRINTS("EC_CMD_CHARGE_STATE: bad cmd 0x%x", in->cmd);
+		rv = EC_RES_INVALID_PARAM;
+	}
+
+	return rv;
+}
+
+DECLARE_HOST_COMMAND(EC_CMD_CHARGE_STATE, charge_command_charge_state,
+		     EC_VER_MASK(0) | EC_VER_MASK(1));
+
+/*****************************************************************************/
+/* Console commands */
+
+#ifdef CONFIG_CMD_PWR_AVG
+
+static int command_pwr_avg(int argc, const char **argv)
+{
+	int avg_mv;
+	int avg_ma;
+	int avg_mw;
+
+	if (argc != 1)
+		return EC_ERROR_PARAM_COUNT;
+
+	avg_mv = battery_get_avg_voltage();
+	if (avg_mv < 0)
+		return EC_ERROR_UNKNOWN;
+	avg_ma = battery_get_avg_current();
+	avg_mw = avg_mv * avg_ma / 1000;
+
+	ccprintf("mv = %d\nma = %d\nmw = %d\n", avg_mv, avg_ma, avg_mw);
+	return EC_SUCCESS;
+}
+
+DECLARE_CONSOLE_COMMAND(pwr_avg, command_pwr_avg, NULL,
+			"Get 1 min power average");
+
+#endif /* CONFIG_CMD_PWR_AVG */
+
+static int command_chgstate(int argc, const char **argv)
+{
+	int rv;
+	int val;
+	char *e;
+
+	if (argc > 1) {
+		if (!strcasecmp(argv[1], "idle")) {
+			if (argc <= 2)
+				return EC_ERROR_PARAM_COUNT;
+			if (!parse_bool(argv[2], &val))
+				return EC_ERROR_PARAM2;
+			rv = set_chg_ctrl_mode(val ? CHARGE_CONTROL_IDLE :
+						     CHARGE_CONTROL_NORMAL);
+			if (rv)
+				return rv;
+		} else if (!strcasecmp(argv[1], "discharge")) {
+			if (argc <= 2)
+				return EC_ERROR_PARAM_COUNT;
+			if (!parse_bool(argv[2], &val))
+				return EC_ERROR_PARAM2;
+			rv = set_chg_ctrl_mode(val ? CHARGE_CONTROL_DISCHARGE :
+						     CHARGE_CONTROL_NORMAL);
+			if (rv)
+				return rv;
+		} else if (IS_ENABLED(CONFIG_CHARGE_DEBUG) &&
+			   !strcasecmp(argv[1], "debug")) {
+			int val;
+
+			if (argc <= 2)
+				return EC_ERROR_PARAM_COUNT;
+			if (!parse_bool(argv[2], &val))
+				return EC_ERROR_PARAM2;
+			set_debugging(val);
+		} else if (!strcasecmp(argv[1], "sustain")) {
+			int lower, upper;
+
+			if (argc <= 3)
+				return EC_ERROR_PARAM_COUNT;
+			lower = strtoi(argv[2], &e, 0);
+			if (*e)
+				return EC_ERROR_PARAM2;
+			upper = strtoi(argv[3], &e, 0);
+			if (*e)
+				return EC_ERROR_PARAM3;
+			rv = battery_sustainer_set(lower, upper);
+			if (rv)
+				return EC_ERROR_INVAL;
+		} else {
+			return EC_ERROR_PARAM1;
+		}
+	}
+
+	dump_charge_state();
+	return EC_SUCCESS;
+}
+#ifdef CONFIG_CHARGE_DEBUG
+#define CHGSTATE_DEBUG_HELP "|debug on|off"
+#else
+#define CHGSTATE_DEBUG_HELP ""
+#endif
+DECLARE_CONSOLE_COMMAND(chgstate, command_chgstate,
+			"[idle|discharge" CHGSTATE_DEBUG_HELP "]"
+			"\n[sustain <lower> <upper>]",
+			"Get/set charge state machine status");
diff --git a/common/charge_state_v2.c b/common/charge_state_v2.c
deleted file mode 100644
index 2bdac84634..0000000000
--- a/common/charge_state_v2.c
+++ /dev/null
@@ -1,2910 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery charging task and state machine.
- */
-
-#include "battery.h"
-#include "battery_smart.h"
-#include "charge_manager.h"
-#include "charger_profile_override.h"
-#include "charge_state.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "ec_ec_comm_master.h"
-#include "ec_ec_comm_slave.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "math_util.h"
-#include "printf.h"
-#include "system.h"
-#include "task.h"
-#include "throttle_ap.h"
-#include "timer.h"
-#include "usb_common.h"
-#include "usb_pd.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CHARGER, outstr)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-
-/* Extra debugging prints when allocating power between lid and base. */
-#undef CHARGE_ALLOCATE_EXTRA_DEBUG
-
-#define CRITICAL_BATTERY_SHUTDOWN_TIMEOUT_US \
-	(CONFIG_BATTERY_CRITICAL_SHUTDOWN_TIMEOUT * SECOND)
-#define PRECHARGE_TIMEOUT_US (PRECHARGE_TIMEOUT * SECOND)
-#define LFCC_EVENT_THRESH 5 /* Full-capacity change reqd for host event */
-
-#ifdef CONFIG_THROTTLE_AP_ON_BAT_DISCHG_CURRENT
-#ifndef CONFIG_HOSTCMD_EVENTS
-#error "CONFIG_THROTTLE_AP_ON_BAT_DISCHG_CURRENT needs CONFIG_HOSTCMD_EVENTS"
-#endif /* CONFIG_HOSTCMD_EVENTS */
-#define BAT_OCP_TIMEOUT_US (60 * SECOND)
-/* BAT_OCP_HYSTERESIS_PCT can be optionally overridden in board.h. */
-#ifndef BAT_OCP_HYSTERESIS_PCT
-#define BAT_OCP_HYSTERESIS_PCT 10
-#endif /* BAT_OCP_HYSTERESIS_PCT */
-#define BAT_OCP_HYSTERESIS \
-	(BAT_MAX_DISCHG_CURRENT * BAT_OCP_HYSTERESIS_PCT / 100) /* mA */
-#endif /* CONFIG_THROTTLE_AP_ON_BAT_DISCHG_CURRENT */
-
-#ifdef CONFIG_THROTTLE_AP_ON_BAT_VOLTAGE
-#ifndef CONFIG_HOSTCMD_EVENTS
-#error "CONFIG_THROTTLE_AP_ON_BAT_VOLTAGE needs CONFIG_HOSTCMD_EVENTS"
-#endif /* CONFIG_HOSTCMD_EVENTS */
-#define BAT_UVP_TIMEOUT_US (60 * SECOND)
-/* BAT_UVP_HYSTERESIS_PCT can be optionally overridden in board.h. */
-#ifndef BAT_UVP_HYSTERESIS_PCT
-#define BAT_UVP_HYSTERESIS_PCT 3
-#endif /* BAT_UVP_HYSTERESIS_PCT */
-#define BAT_UVP_HYSTERESIS \
-	(BAT_LOW_VOLTAGE_THRESH * BAT_UVP_HYSTERESIS_PCT / 100) /* mV */
-static timestamp_t uvp_throttle_start_time;
-#endif /* CONFIG_THROTTLE_AP_ON_BAT_OLTAGE */
-
-static int charge_request(int voltage, int current);
-
-static uint8_t battery_level_shutdown;
-
-/*
- * State for charger_task(). Here so we can reset it on a HOOK_INIT, and
- * because stack space is more limited than .bss
- */
-static const struct battery_info *batt_info;
-static struct charge_state_data curr;
-static enum charge_state_v2 prev_state;
-static int prev_ac, prev_charge, prev_full, prev_disp_charge;
-static enum battery_present prev_bp;
-static int is_full; /* battery not accepting current */
-static enum ec_charge_control_mode chg_ctl_mode;
-static int manual_voltage;  /* Manual voltage override (-1 = no override) */
-static int manual_current;  /* Manual current override (-1 = no override) */
-static unsigned int user_current_limit = -1U;
-test_export_static timestamp_t shutdown_target_time;
-static timestamp_t precharge_start_time;
-
-/*
- * The timestamp when the battery charging current becomes stable.
- * When a new charging status happens, charger needs several seconds to
- * stabilize the battery charging current.
- * stable_current should be evaluated when stable_ts expired.
- * stable_ts should be reset if the charger input voltage/current changes,
- * or a new battery charging voltage/request happened.
- * By evaluating stable_current, we can evaluate the battery's desired charging
- * power desired_mw. This allow us to have a better charging efficiency by
- * negotiating the most fit PDO, i.e. the PDO provides the power just enough for
- * the system and battery, or the PDO with preferred voltage.
- */
-STATIC_IF(CONFIG_USB_PD_PREFER_MV) timestamp_t stable_ts;
-/* battery charging current evaluated after stable_ts expired */
-STATIC_IF(CONFIG_USB_PD_PREFER_MV) int stable_current;
-/* battery desired power in mW. This is used to negotiate the suitable PDO */
-STATIC_IF(CONFIG_USB_PD_PREFER_MV) int desired_mw;
-STATIC_IF_NOT(CONFIG_USB_PD_PREFER_MV) struct pd_pref_config_t pd_pref_config;
-
-#ifdef CONFIG_EC_EC_COMM_BATTERY_MASTER
-static int base_connected;
-/* Base has responded to one of our commands already. */
-static int base_responsive;
-static int charge_base;
-static int prev_charge_base;
-static int prev_current_base;
-static int prev_allow_charge_base;
-static int prev_current_lid;
-
-/*
- * In debugging mode, with AC, input current to allocate to base. Negative
- * value disables manual mode.
- */
-static int manual_ac_current_base = -1;
-/*
- * In debugging mode, when discharging, current to transfer from lid to base
- * (negative to transfer from base to lid). Only valid when enabled is true.
- */
-static int manual_noac_enabled;
-static int manual_noac_current_base;
-#else
-static const int base_connected;
-#endif
-
-/* Is battery connected but unresponsive after precharge? */
-static int battery_seems_to_be_dead;
-
-static int battery_seems_to_be_disconnected;
-
-/*
- * Was battery removed?  Set when we see BP_NO, cleared after the battery is
- * reattached and becomes responsive.  Used to indicate an error state after
- * removal and trigger re-reading the battery static info when battery is
- * reattached and responsive.
- */
-static int battery_was_removed;
-
-static int problems_exist;
-static int debugging;
-
-
-/* Track problems in communicating with the battery or charger */
-enum problem_type {
-	PR_STATIC_UPDATE,
-	PR_SET_VOLTAGE,
-	PR_SET_CURRENT,
-	PR_SET_MODE,
-	PR_SET_INPUT_CURR,
-	PR_POST_INIT,
-	PR_CHG_FLAGS,
-	PR_BATT_FLAGS,
-	PR_CUSTOM,
-	PR_CFG_SEC_CHG,
-
-	NUM_PROBLEM_TYPES
-};
-static const char * const prob_text[] = {
-	"static update",
-	"set voltage",
-	"set current",
-	"set mode",
-	"set input current",
-	"post init",
-	"chg params",
-	"batt params",
-	"custom profile",
-	"cfg secondary chg"
-};
-BUILD_ASSERT(ARRAY_SIZE(prob_text) == NUM_PROBLEM_TYPES);
-
-/*
- * TODO(crosbug.com/p/27639): When do we decide a problem is real and not
- * just intermittent? And what do we do about it?
- */
-static void problem(enum problem_type p, int v)
-{
-	static int __bss_slow last_prob_val[NUM_PROBLEM_TYPES];
-	static timestamp_t __bss_slow last_prob_time[NUM_PROBLEM_TYPES];
-	timestamp_t t_now, t_diff;
-
-	if (last_prob_val[p] != v) {
-		t_now = get_time();
-		t_diff.val = t_now.val - last_prob_time[p].val;
-		CPRINTS("charge problem: %s, 0x%x -> 0x%x after %.6" PRId64 "s",
-			 prob_text[p], last_prob_val[p], v, t_diff.val);
-		last_prob_val[p] = v;
-		last_prob_time[p] = t_now;
-	}
-	problems_exist = 1;
-}
-
-#ifdef CONFIG_EC_EC_COMM_BATTERY_MASTER
-/*
- * Parameters for dual-battery policy.
- * TODO(b:71881017): This should be made configurable by AP in the future.
- */
-struct dual_battery_policy {
-	/*** Policies when AC is not connected. ***/
-	/* Voltage to use when using OTG mode between lid and base (mV) */
-	uint16_t otg_voltage;
-	/* Maximum current to apply from base to lid (mA) */
-	uint16_t max_base_to_lid_current;
-	/*
-	 * Margin to apply between provided OTG output current and input current
-	 * limit, to make sure that input charger does not overcurrent output
-	 * charger. input_current = (1-margin) * output_current. (/128)
-	 */
-	uint8_t margin_otg_current;
-
-	/* Only do base to lid OTG when base battery above this value (%) */
-	uint8_t min_charge_base_otg;
-
-	/*
-	 * When base/lid battery percentage is below this value, do
-	 * battery-to-battery charging. (%)
-	 */
-	uint8_t max_charge_base_batt_to_batt;
-	uint8_t max_charge_lid_batt_to_batt;
-
-	/*** Policies when AC is connected. ***/
-	/* Minimum power to allocate to base (mW), includes some margin to allow
-	 * base to charge when critically low.
-	 */
-	uint16_t min_base_system_power;
-
-	/* Smoothing factor for lid power (/128) */
-	uint8_t lid_system_power_smooth;
-	/*
-	 * Smoothing factor for base/lid battery power, when the battery power
-	 * is decreasing only: we try to estimate the maximum power that the
-	 * battery is willing to take and always reset it when it draws more
-	 * than the estimate. (/128)
-	 */
-	uint8_t battery_power_smooth;
-
-	/*
-	 * Margin to add to requested base/lid battery power, to figure out how
-	 * much current to allocate. allocation = (1+margin) * request. (/128)
-	 */
-	uint8_t margin_base_battery_power;
-	uint8_t margin_lid_battery_power;
-
-	/* Maximum current to apply from lid to base (mA) */
-	uint16_t max_lid_to_base_current;
-};
-
-static const struct dual_battery_policy db_policy = {
-	.otg_voltage = 12000, /* mV */
-	.max_base_to_lid_current = 1800, /* mA, about 2000mA with margin. */
-	.margin_otg_current = 13, /* /128 = 10.1% */
-	.min_charge_base_otg = 5, /* % */
-	.max_charge_base_batt_to_batt = 4, /* % */
-	.max_charge_lid_batt_to_batt = 10, /* % */
-	.min_base_system_power = 1300, /* mW */
-	.lid_system_power_smooth = 32, /* 32/128 = 0.25 */
-	.battery_power_smooth = 1, /* 1/128 = 0.008 */
-	.margin_base_battery_power = 32, /* 32/128 = 0.25 */
-	.margin_lid_battery_power = 32, /* 32/128 = 0.25 */
-	.max_lid_to_base_current = 2000, /* mA */
-};
-
-/* Add at most "value" to power_var, subtracting from total_power budget. */
-#define CHG_ALLOCATE(power_var, total_power, value) do {	\
-	int val_capped = MIN(value, total_power);		\
-	(power_var) += val_capped;				\
-	(total_power) -= val_capped;				\
-} while (0)
-
-/* Update base battery information */
-static void update_base_battery_info(void)
-{
-	struct ec_response_battery_dynamic_info *const bd =
-		&battery_dynamic[BATT_IDX_BASE];
-
-	base_connected = board_is_base_connected();
-
-	if (!base_connected) {
-		const int invalid_flags = EC_BATT_FLAG_INVALID_DATA;
-		/* Invalidate static/dynamic information */
-		if (bd->flags != invalid_flags) {
-			bd->flags = invalid_flags;
-
-			host_set_single_event(EC_HOST_EVENT_BATTERY);
-			host_set_single_event(EC_HOST_EVENT_BATTERY_STATUS);
-		}
-		charge_base = -1;
-		base_responsive = 0;
-		prev_current_base = 0;
-		prev_allow_charge_base = 0;
-	} else if (base_responsive) {
-		int old_flags = bd->flags;
-		int flags_changed;
-		int old_full_capacity = bd->full_capacity;
-
-		ec_ec_master_base_get_dynamic_info();
-		flags_changed = (old_flags != bd->flags);
-		/* Fetch static information when flags change. */
-		if (flags_changed)
-			ec_ec_master_base_get_static_info();
-
-		battery_memmap_refresh(BATT_IDX_BASE);
-
-		/* Newly connected battery, or change in capacity. */
-		if (old_flags & EC_BATT_FLAG_INVALID_DATA ||
-				((old_flags & EC_BATT_FLAG_BATT_PRESENT) !=
-				 (bd->flags & EC_BATT_FLAG_BATT_PRESENT)) ||
-				old_full_capacity != bd->full_capacity)
-			host_set_single_event(EC_HOST_EVENT_BATTERY);
-
-		if (flags_changed)
-			host_set_single_event(EC_HOST_EVENT_BATTERY_STATUS);
-
-		/* Update charge_base */
-		if (bd->flags & (BATT_FLAG_BAD_FULL_CAPACITY |
-				 BATT_FLAG_BAD_REMAINING_CAPACITY))
-			charge_base = -1;
-		else if (bd->full_capacity > 0)
-			charge_base = 100 * bd->remaining_capacity
-						/ bd->full_capacity;
-		else
-			charge_base = 0;
-	}
-}
-
-/**
- * Setup current settings for base, and record previous values, if the base
- * is responsive.
- *
- * @param current_base Current to be drawn by base (negative to provide power)
- * @param allow_charge_base Whether base battery should be charged (only makes
- *                          sense with positive current)
- */
-static int set_base_current(int current_base, int allow_charge_base)
-{
-	/* "OTG" voltage from base to lid. */
-	const int otg_voltage = db_policy.otg_voltage;
-	int ret;
-
-	ret = ec_ec_master_base_charge_control(current_base,
-					otg_voltage, allow_charge_base);
-	if (ret) {
-		/* Ignore errors until the base is responsive. */
-		if (base_responsive)
-			return ret;
-	} else {
-		base_responsive = 1;
-		prev_current_base = current_base;
-		prev_allow_charge_base = allow_charge_base;
-	}
-
-	return EC_RES_SUCCESS;
-}
-
-/**
- * Setup current settings for lid and base, in a safe way.
- *
- * @param current_base Current to be drawn by base (negative to provide power)
- * @param allow_charge_base Whether base battery should be charged (only makes
- *                          sense with positive current)
- * @param current_lid Current to be drawn by lid (negative to provide power)
- * @param allow_charge_lid Whether lid battery should be charged
- */
-static void set_base_lid_current(int current_base, int allow_charge_base,
-				 int current_lid, int allow_charge_lid)
-{
-	/* "OTG" voltage from lid to base. */
-	const int otg_voltage = db_policy.otg_voltage;
-
-	int lid_first;
-	int ret;
-	int chgnum = 0;
-
-	/* TODO(b:71881017): This is still quite verbose during charging. */
-	if (prev_current_base != current_base ||
-	    prev_allow_charge_base != allow_charge_base ||
-	    prev_current_lid != current_lid) {
-		CPRINTS("Base/Lid: %d%s/%d%s mA",
-			current_base, allow_charge_base ? "+" : "",
-			current_lid, allow_charge_lid ? "+" : "");
-	}
-
-	/*
-	 * To decide whether to first control the lid or the base, we first
-	 * control the side that _reduces_ current that would be drawn, then
-	 * setup one that would start providing power, then increase current.
-	 */
-	if (current_lid >= 0 && current_lid < prev_current_lid)
-		lid_first = 1; /* Lid decreases current */
-	else if (current_base >= 0 && current_base < prev_current_base)
-		lid_first = 0; /* Base decreases current */
-	else if (current_lid < 0)
-		lid_first = 1; /* Lid provide power */
-	else
-		lid_first = 0; /* All other cases: control the base first */
-
-	if (!lid_first && base_connected) {
-		ret = set_base_current(current_base, allow_charge_base);
-		if (ret)
-			return;
-	}
-
-	if (current_lid >= 0) {
-		ret = charge_set_output_current_limit(CHARGER_SOLO, 0, 0);
-		if (ret)
-			return;
-		ret = charger_set_input_current(chgnum, current_lid);
-		if (ret)
-			return;
-		if (allow_charge_lid)
-			ret = charge_request(curr.requested_voltage,
-				curr.requested_current);
-		else
-			ret = charge_request(0, 0);
-	} else {
-		ret = charge_set_output_current_limit(CHARGER_SOLO,
-						-current_lid, otg_voltage);
-	}
-
-	if (ret)
-		return;
-
-	prev_current_lid = current_lid;
-
-	if (lid_first && base_connected) {
-		ret = set_base_current(current_base, allow_charge_base);
-		if (ret)
-			return;
-	}
-
-	/*
-	 * Make sure cross-power is enabled (it might not be enabled right after
-	 * plugging the base, or when an adapter just got connected).
-	 */
-	if (base_connected && current_base != 0)
-		board_enable_base_power(1);
-}
-
-/**
- * Smooth power value, covering some edge cases.
- * Compute s*curr+(1-s)*prev, where s is in 1/128 unit.
- */
-static int smooth_value(int prev, int curr, int s)
-{
-	if (curr < 0)
-		curr = 0;
-	if (prev < 0)
-		return curr;
-
-	return prev + s * (curr - prev) / 128;
-}
-
-/**
- * Add margin m to value. Compute (1+m)*value, where m is in 1/128 unit.
- */
-static int add_margin(int value, int m)
-{
-	return value + m * value / 128;
-}
-
-static void charge_allocate_input_current_limit(void)
-{
-	/*
-	 * All the power numbers are in mW.
-	 *
-	 * Since we work with current and voltage in mA and mV, multiplying them
-	 * gives numbers in uW, which are dangerously close to overflowing when
-	 * doing intermediate computations (60W * 100 overflows a 32-bit int,
-	 * for example). We therefore divide the product by 1000 and re-multiply
-	 * the power numbers by 1000 when converting them back to current.
-	 */
-	int total_power = 0;
-
-	static int prev_base_battery_power = -1;
-	int base_battery_power = 0;
-	int base_battery_power_max = 0;
-
-	static int prev_lid_system_power = -1;
-	int lid_system_power;
-
-	static int prev_lid_battery_power = -1;
-	int lid_battery_power = 0;
-	int lid_battery_power_max = 0;
-
-	int power_base = 0;
-	int power_lid = 0;
-
-	int current_base = 0;
-	int current_lid = 0;
-
-	int charge_lid = charge_get_percent();
-
-	const struct ec_response_battery_dynamic_info *const base_bd =
-		&battery_dynamic[BATT_IDX_BASE];
-
-
-	if (!base_connected) {
-		set_base_lid_current(0, 0, curr.desired_input_current, 1);
-		prev_base_battery_power = -1;
-		return;
-	}
-
-	/* Charging */
-	if (curr.desired_input_current > 0 && curr.input_voltage > 0)
-		total_power =
-			curr.desired_input_current * curr.input_voltage / 1000;
-
-	/*
-	 * TODO(b:71723024): We should be able to replace this test by curr.ac,
-	 * but the value is currently wrong, especially during transitions.
-	 */
-	if (total_power <= 0) {
-		int base_critical = charge_base >= 0 &&
-			charge_base < db_policy.max_charge_base_batt_to_batt;
-
-		/* Discharging */
-		prev_base_battery_power = -1;
-		prev_lid_system_power = -1;
-		prev_lid_battery_power = -1;
-
-		/* Manual control */
-		if (manual_noac_enabled) {
-			int lid_current, base_current;
-
-			if (manual_noac_current_base > 0) {
-				base_current = -manual_noac_current_base;
-				lid_current =
-					add_margin(manual_noac_current_base,
-						db_policy.margin_otg_current);
-			} else {
-				lid_current = manual_noac_current_base;
-				base_current =
-					add_margin(-manual_noac_current_base,
-						db_policy.margin_otg_current);
-			}
-
-			set_base_lid_current(base_current, 0, lid_current, 0);
-			return;
-		}
-
-		/*
-		 * System is off, cut power to the base. We'll reset the base
-		 * when system restarts, or when AC is plugged.
-		 */
-		if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
-			set_base_lid_current(0, 0, 0, 0);
-			if (base_responsive) {
-				/* Base still responsive, put it to sleep. */
-				CPRINTF("Hibernating base\n");
-				ec_ec_master_hibernate();
-				base_responsive = 0;
-				board_enable_base_power(0);
-			}
-			return;
-		}
-
-		/*
-		 * System is suspended, let the lid and base run on their
-		 * own power. However, if the base battery is critically low, we
-		 * still want to provide power to the base, to make sure it
-		 * stays alive to be able to wake the system on keyboard or
-		 * touchpad events.
-		 */
-		if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
-					!base_critical) {
-			set_base_lid_current(0, 0, 0, 0);
-			return;
-		}
-
-		if (charge_base > db_policy.min_charge_base_otg) {
-			int lid_current = db_policy.max_base_to_lid_current;
-			int base_current = add_margin(lid_current,
-						db_policy.margin_otg_current);
-			/* Draw current from base to lid */
-			set_base_lid_current(-base_current, 0, lid_current,
-			    charge_lid < db_policy.max_charge_lid_batt_to_batt);
-		} else {
-			/*
-			 * Base battery is too low, apply power to it, and allow
-			 * it to charge if it is critically low.
-			 *
-			 * TODO(b:71881017): When suspended, this will make the
-			 * battery charge oscillate between 3 and 4 percent,
-			 * which might not be great for battery life. We need
-			 * some hysteresis.
-			 */
-			/*
-			 * TODO(b:71881017): Precompute (ideally, at build time)
-			 * the base_current, so we do not need to do a division
-			 * here.
-			 */
-			int base_current =
-				(db_policy.min_base_system_power * 1000) /
-				db_policy.otg_voltage;
-			int lid_current = add_margin(base_current,
-						db_policy.margin_otg_current);
-
-			set_base_lid_current(base_current, base_critical,
-					     -lid_current, 0);
-		}
-
-		return;
-	}
-
-	/* Manual control */
-	if (manual_ac_current_base >= 0) {
-		int current_base = manual_ac_current_base;
-		int current_lid =
-			curr.desired_input_current - manual_ac_current_base;
-
-		if (current_lid < 0) {
-			current_base = curr.desired_input_current;
-			current_lid = 0;
-		}
-
-		set_base_lid_current(current_base, 1, current_lid, 1);
-		return;
-	}
-
-	/* Estimate system power. */
-	lid_system_power = charger_get_system_power() / 1000;
-
-	/* Smooth system power, as it is very spiky */
-	lid_system_power = smooth_value(prev_lid_system_power,
-			lid_system_power, db_policy.lid_system_power_smooth);
-	prev_lid_system_power = lid_system_power;
-
-	/*
-	 * TODO(b:71881017): Smoothing the battery power isn't necessarily a
-	 * good idea: if the system takes up too much power, we may reduce the
-	 * estimate power too quickly, leading to oscillations when the system
-	 * power goes down. Instead, we should probably estimate the current
-	 * based on remaining capacity.
-	 */
-	/* Estimate lid battery power. */
-	if (!(curr.batt.flags &
-			(BATT_FLAG_BAD_VOLTAGE | BATT_FLAG_BAD_CURRENT)))
-		lid_battery_power = curr.batt.current *
-				    curr.batt.voltage / 1000;
-	if (lid_battery_power < prev_lid_battery_power)
-		lid_battery_power = smooth_value(prev_lid_battery_power,
-			     lid_battery_power, db_policy.battery_power_smooth);
-	if (!(curr.batt.flags &
-			(BATT_FLAG_BAD_DESIRED_VOLTAGE |
-				BATT_FLAG_BAD_DESIRED_CURRENT)))
-		lid_battery_power_max = curr.batt.desired_current *
-					curr.batt.desired_voltage / 1000;
-
-	lid_battery_power = MIN(lid_battery_power, lid_battery_power_max);
-
-	/* Estimate base battery power. */
-	if (!(base_bd->flags & EC_BATT_FLAG_INVALID_DATA)) {
-		base_battery_power = base_bd->actual_current *
-				     base_bd->actual_voltage / 1000;
-		base_battery_power_max = base_bd->desired_current *
-					 base_bd->desired_voltage / 1000;
-	}
-	if (base_battery_power < prev_base_battery_power)
-		base_battery_power = smooth_value(prev_base_battery_power,
-			    base_battery_power, db_policy.battery_power_smooth);
-	base_battery_power = MIN(base_battery_power, base_battery_power_max);
-
-	if (debugging) {
-		CPRINTF("%s:\n", __func__);
-		CPRINTF("total power: %d\n", total_power);
-		CPRINTF("base battery power: %d (%d)\n",
-			base_battery_power, base_battery_power_max);
-		CPRINTF("lid system power: %d\n", lid_system_power);
-		CPRINTF("lid battery power: %d\n", lid_battery_power);
-		CPRINTF("percent base/lid: %d%% %d%%\n",
-			charge_base, charge_lid);
-	}
-
-	prev_lid_battery_power = lid_battery_power;
-	prev_base_battery_power = base_battery_power;
-
-	if (total_power > 0) { /* Charging */
-		/* Allocate system power */
-		CHG_ALLOCATE(power_base, total_power,
-			db_policy.min_base_system_power);
-		CHG_ALLOCATE(power_lid, total_power, lid_system_power);
-
-		/* Allocate lid, then base battery power */
-		lid_battery_power = add_margin(lid_battery_power,
-					db_policy.margin_lid_battery_power);
-		CHG_ALLOCATE(power_lid, total_power, lid_battery_power);
-
-		base_battery_power = add_margin(base_battery_power,
-					db_policy.margin_base_battery_power);
-		CHG_ALLOCATE(power_base, total_power, base_battery_power);
-
-		/* Give everything else to the lid. */
-		CHG_ALLOCATE(power_lid, total_power, total_power);
-		if (debugging)
-			CPRINTF("power: base %d mW / lid %d mW\n",
-				power_base, power_lid);
-
-		current_base = 1000 * power_base / curr.input_voltage;
-		current_lid = 1000 * power_lid / curr.input_voltage;
-
-		if (current_base > db_policy.max_lid_to_base_current) {
-			current_lid += (current_base
-					- db_policy.max_lid_to_base_current);
-			current_base = db_policy.max_lid_to_base_current;
-		}
-
-		if (debugging)
-			CPRINTF("current: base %d mA / lid %d mA\n",
-				current_base, current_lid);
-
-		set_base_lid_current(current_base, 1, current_lid, 1);
-	} else { /* Discharging */
-	}
-
-	if (debugging)
-		CPRINTF("====\n");
-}
-#endif /* CONFIG_EC_EC_COMM_BATTERY_MASTER */
-
-#ifndef CONFIG_BATTERY_V2
-/* Returns zero if every item was updated. */
-static int update_static_battery_info(void)
-{
-	char *batt_str;
-	int batt_serial;
-	uint8_t batt_flags = 0;
-	/*
-	 * The return values have type enum ec_error_list, but EC_SUCCESS is
-	 * zero. We'll just look for any failures so we can try them all again.
-	 */
-	int rv;
-
-	/* Smart battery serial number is 16 bits */
-	batt_str = (char *)host_get_memmap(EC_MEMMAP_BATT_SERIAL);
-	memset(batt_str, 0, EC_MEMMAP_TEXT_MAX);
-	rv = battery_serial_number(&batt_serial);
-	if (!rv)
-		snprintf(batt_str, EC_MEMMAP_TEXT_MAX, "%04X", batt_serial);
-
-	/* Design Capacity of Full */
-	rv |= battery_design_capacity(
-		(int *)host_get_memmap(EC_MEMMAP_BATT_DCAP));
-
-	/* Design Voltage */
-	rv |= battery_design_voltage(
-		(int *)host_get_memmap(EC_MEMMAP_BATT_DVLT));
-
-	/* Last Full Charge Capacity (this is only mostly static) */
-	rv |= battery_full_charge_capacity(
-		(int *)host_get_memmap(EC_MEMMAP_BATT_LFCC));
-
-	/* Cycle Count */
-	rv |= battery_cycle_count((int *)host_get_memmap(EC_MEMMAP_BATT_CCNT));
-
-	/* Battery Manufacturer string */
-	batt_str = (char *)host_get_memmap(EC_MEMMAP_BATT_MFGR);
-	memset(batt_str, 0, EC_MEMMAP_TEXT_MAX);
-	rv |= battery_manufacturer_name(batt_str, EC_MEMMAP_TEXT_MAX);
-
-	/* Battery Model string */
-	batt_str = (char *)host_get_memmap(EC_MEMMAP_BATT_MODEL);
-	memset(batt_str, 0, EC_MEMMAP_TEXT_MAX);
-	rv |= battery_device_name(batt_str, EC_MEMMAP_TEXT_MAX);
-
-	/* Battery Type string */
-	batt_str = (char *)host_get_memmap(EC_MEMMAP_BATT_TYPE);
-	rv |= battery_device_chemistry(batt_str, EC_MEMMAP_TEXT_MAX);
-
-	/* Zero the dynamic entries. They'll come next. */
-	*(int *)host_get_memmap(EC_MEMMAP_BATT_VOLT) = 0;
-	*(int *)host_get_memmap(EC_MEMMAP_BATT_RATE) = 0;
-	*(int *)host_get_memmap(EC_MEMMAP_BATT_CAP) = 0;
-	*(int *)host_get_memmap(EC_MEMMAP_BATT_LFCC) = 0;
-	if (extpower_is_present())
-		batt_flags |= EC_BATT_FLAG_AC_PRESENT;
-	*host_get_memmap(EC_MEMMAP_BATT_FLAG) = batt_flags;
-
-	if (rv)
-		problem(PR_STATIC_UPDATE, rv);
-	else
-		/* No errors seen. Battery data is now present */
-		*host_get_memmap(EC_MEMMAP_BATTERY_VERSION) = 1;
-
-	return rv;
-}
-
-static void update_dynamic_battery_info(void)
-{
-	/* The memmap address is constant. We should fix these calls somehow. */
-	int *memmap_volt = (int *)host_get_memmap(EC_MEMMAP_BATT_VOLT);
-	int *memmap_rate = (int *)host_get_memmap(EC_MEMMAP_BATT_RATE);
-	int *memmap_cap = (int *)host_get_memmap(EC_MEMMAP_BATT_CAP);
-	int *memmap_lfcc = (int *)host_get_memmap(EC_MEMMAP_BATT_LFCC);
-	uint8_t *memmap_flags = host_get_memmap(EC_MEMMAP_BATT_FLAG);
-	uint8_t tmp;
-	int send_batt_status_event = 0;
-	int send_batt_info_event = 0;
-	static int __bss_slow batt_present;
-
-	tmp = 0;
-	if (curr.ac)
-		tmp |= EC_BATT_FLAG_AC_PRESENT;
-
-	if (curr.batt.is_present == BP_YES) {
-		tmp |= EC_BATT_FLAG_BATT_PRESENT;
-		batt_present = 1;
-		/* Tell the AP to read battery info if it is newly present. */
-		if (!(*memmap_flags & EC_BATT_FLAG_BATT_PRESENT))
-			send_batt_info_event++;
-	} else {
-		/*
-		 * Require two consecutive updates with BP_NOT_SURE
-		 * before reporting it gone to the host.
-		 */
-		if (batt_present)
-			tmp |= EC_BATT_FLAG_BATT_PRESENT;
-		else if (*memmap_flags & EC_BATT_FLAG_BATT_PRESENT)
-			send_batt_info_event++;
-		batt_present = 0;
-	}
-
-	if (curr.batt.flags & EC_BATT_FLAG_INVALID_DATA)
-		tmp |= EC_BATT_FLAG_INVALID_DATA;
-
-	if (!(curr.batt.flags & BATT_FLAG_BAD_VOLTAGE))
-		*memmap_volt = curr.batt.voltage;
-
-	if (!(curr.batt.flags & BATT_FLAG_BAD_CURRENT))
-		*memmap_rate = ABS(curr.batt.current);
-
-	if (!(curr.batt.flags & BATT_FLAG_BAD_REMAINING_CAPACITY)) {
-		/*
-		 * If we're running off the battery, it must have some charge.
-		 * Don't report zero charge, as that has special meaning
-		 * to Chrome OS powerd.
-		 */
-		if (curr.batt.remaining_capacity == 0 && !curr.batt_is_charging)
-			*memmap_cap = 1;
-		else
-			*memmap_cap = curr.batt.remaining_capacity;
-	}
-
-	if (!(curr.batt.flags & BATT_FLAG_BAD_FULL_CAPACITY) &&
-	    (curr.batt.full_capacity <= (*memmap_lfcc - LFCC_EVENT_THRESH) ||
-	     curr.batt.full_capacity >= (*memmap_lfcc + LFCC_EVENT_THRESH))) {
-		*memmap_lfcc = curr.batt.full_capacity;
-		/* Poke the AP if the full_capacity changes. */
-		send_batt_info_event++;
-	}
-
-	if (curr.batt.is_present == BP_YES &&
-	    !(curr.batt.flags & BATT_FLAG_BAD_STATE_OF_CHARGE) &&
-	    curr.batt.state_of_charge <= BATTERY_LEVEL_CRITICAL)
-		tmp |= EC_BATT_FLAG_LEVEL_CRITICAL;
-
-	tmp |= curr.batt_is_charging ? EC_BATT_FLAG_CHARGING :
-				       EC_BATT_FLAG_DISCHARGING;
-
-	/* Tell the AP to re-read battery status if charge state changes */
-	if (*memmap_flags != tmp)
-		send_batt_status_event++;
-
-	/* Update flags before sending host events. */
-	*memmap_flags = tmp;
-
-	if (send_batt_info_event)
-		host_set_single_event(EC_HOST_EVENT_BATTERY);
-	if (send_batt_status_event)
-		host_set_single_event(EC_HOST_EVENT_BATTERY_STATUS);
-}
-#else /* CONFIG_BATTERY_V2 */
-static int update_static_battery_info(void)
-{
-	int batt_serial;
-	int val;
-	/*
-	 * The return values have type enum ec_error_list, but EC_SUCCESS is
-	 * zero. We'll just look for any failures so we can try them all again.
-	 */
-	int rv, ret;
-
-	struct ec_response_battery_static_info *const bs =
-		&battery_static[BATT_IDX_MAIN];
-
-	/* Clear all static information. */
-	memset(bs, 0, sizeof(*bs));
-
-	/* Smart battery serial number is 16 bits */
-	rv = battery_serial_number(&batt_serial);
-	if (!rv)
-		snprintf(bs->serial, sizeof(bs->serial), "%04X", batt_serial);
-
-	/* Design Capacity of Full */
-	ret = battery_design_capacity(&val);
-	if (!ret)
-		bs->design_capacity = val;
-	rv |= ret;
-
-	/* Design Voltage */
-	ret = battery_design_voltage(&val);
-	if (!ret)
-		bs->design_voltage = val;
-	rv |= ret;
-
-	/* Cycle Count */
-	ret = battery_cycle_count(&val);
-	if (!ret)
-		bs->cycle_count = val;
-	rv |= ret;
-
-	/* Battery Manufacturer string */
-	rv |= battery_manufacturer_name(bs->manufacturer,
-					sizeof(bs->manufacturer));
-
-	/* Battery Model string */
-	rv |= battery_device_name(bs->model, sizeof(bs->model));
-
-	/* Battery Type string */
-	rv |= battery_device_chemistry(bs->type, sizeof(bs->type));
-
-	/* Zero the dynamic entries. They'll come next. */
-	memset(&battery_dynamic[BATT_IDX_MAIN], 0,
-	       sizeof(battery_dynamic[BATT_IDX_MAIN]));
-
-	if (rv)
-		problem(PR_STATIC_UPDATE, rv);
-
-#ifdef HAS_TASK_HOSTCMD
-	battery_memmap_refresh(BATT_IDX_MAIN);
-#endif
-
-	return rv;
-}
-
-static void update_dynamic_battery_info(void)
-{
-	static int __bss_slow batt_present;
-	uint8_t tmp;
-	int send_batt_status_event = 0;
-	int send_batt_info_event = 0;
-
-	struct ec_response_battery_dynamic_info *const bd =
-		&battery_dynamic[BATT_IDX_MAIN];
-
-	tmp = 0;
-	if (curr.ac)
-		tmp |= EC_BATT_FLAG_AC_PRESENT;
-
-	if (curr.batt.is_present == BP_YES) {
-		tmp |= EC_BATT_FLAG_BATT_PRESENT;
-		batt_present = 1;
-		/* Tell the AP to read battery info if it is newly present. */
-		if (!(bd->flags & EC_BATT_FLAG_BATT_PRESENT))
-			send_batt_info_event++;
-	} else {
-		/*
-		 * Require two consecutive updates with BP_NOT_SURE
-		 * before reporting it gone to the host.
-		 */
-		if (batt_present)
-			tmp |= EC_BATT_FLAG_BATT_PRESENT;
-		else if (bd->flags & EC_BATT_FLAG_BATT_PRESENT)
-			send_batt_info_event++;
-		batt_present = 0;
-	}
-
-	if (curr.batt.flags & EC_BATT_FLAG_INVALID_DATA)
-		tmp |= EC_BATT_FLAG_INVALID_DATA;
-
-	if (!(curr.batt.flags & BATT_FLAG_BAD_VOLTAGE))
-		bd->actual_voltage = curr.batt.voltage;
-
-	if (!(curr.batt.flags & BATT_FLAG_BAD_CURRENT))
-		bd->actual_current = curr.batt.current;
-
-	if (!(curr.batt.flags & BATT_FLAG_BAD_DESIRED_VOLTAGE))
-		bd->desired_voltage = curr.batt.desired_voltage;
-
-	if (!(curr.batt.flags & BATT_FLAG_BAD_DESIRED_CURRENT))
-		bd->desired_current = curr.batt.desired_current;
-
-	if (!(curr.batt.flags & BATT_FLAG_BAD_REMAINING_CAPACITY)) {
-		/*
-		 * If we're running off the battery, it must have some charge.
-		 * Don't report zero charge, as that has special meaning
-		 * to Chrome OS powerd.
-		 */
-		if (curr.batt.remaining_capacity == 0 && !curr.batt_is_charging)
-			bd->remaining_capacity = 1;
-		else
-			bd->remaining_capacity = curr.batt.remaining_capacity;
-	}
-
-	if (!(curr.batt.flags & BATT_FLAG_BAD_FULL_CAPACITY) &&
-		(curr.batt.full_capacity <=
-			(bd->full_capacity - LFCC_EVENT_THRESH) ||
-		 curr.batt.full_capacity >=
-			(bd->full_capacity + LFCC_EVENT_THRESH))) {
-		bd->full_capacity = curr.batt.full_capacity;
-		/* Poke the AP if the full_capacity changes. */
-		send_batt_info_event++;
-	}
-
-	if (curr.batt.is_present == BP_YES &&
-	    !(curr.batt.flags & BATT_FLAG_BAD_STATE_OF_CHARGE) &&
-	    curr.batt.state_of_charge <= BATTERY_LEVEL_CRITICAL)
-		tmp |= EC_BATT_FLAG_LEVEL_CRITICAL;
-
-	tmp |= curr.batt_is_charging ? EC_BATT_FLAG_CHARGING :
-				       EC_BATT_FLAG_DISCHARGING;
-
-	/* Tell the AP to re-read battery status if charge state changes */
-	if (bd->flags != tmp)
-		send_batt_status_event++;
-
-	bd->flags = tmp;
-
-#ifdef HAS_TASK_HOSTCMD
-	battery_memmap_refresh(BATT_IDX_MAIN);
-#endif
-
-#ifdef CONFIG_HOSTCMD_EVENTS
-	if (send_batt_info_event)
-		host_set_single_event(EC_HOST_EVENT_BATTERY);
-	if (send_batt_status_event)
-		host_set_single_event(EC_HOST_EVENT_BATTERY_STATUS);
-#endif
-}
-#endif /* CONFIG_BATTERY_V2 */
-
-static const char * const state_list[] = {
-	"idle", "discharge", "charge", "precharge"
-};
-BUILD_ASSERT(ARRAY_SIZE(state_list) == NUM_STATES_V2);
-static const char * const batt_pres[] = {
-	"NO", "YES", "NOT_SURE",
-};
-
-static void dump_charge_state(void)
-{
-#define DUMP(FLD, FMT) ccprintf(#FLD " = " FMT "\n", curr.FLD)
-#define DUMP_CHG(FLD, FMT) ccprintf("\t" #FLD " = " FMT "\n", curr.chg. FLD)
-#define DUMP_BATT(FLD, FMT) ccprintf("\t" #FLD " = " FMT "\n", curr.batt. FLD)
-#define DUMP_OCPC(FLD, FMT) ccprintf("\t" #FLD " = " FMT "\n", curr.ocpc. FLD)
-	ccprintf("state = %s\n", state_list[curr.state]);
-	DUMP(ac, "%d");
-	DUMP(batt_is_charging, "%d");
-	ccprintf("chg.*:\n");
-	DUMP_CHG(voltage, "%dmV");
-	DUMP_CHG(current, "%dmA");
-	DUMP_CHG(input_current, "%dmA");
-	DUMP_CHG(status, "0x%x");
-	DUMP_CHG(option, "0x%x");
-	DUMP_CHG(flags, "0x%x");
-	cflush();
-	ccprintf("batt.*:\n");
-	ccprintf("\ttemperature = %dC\n",
-		 DECI_KELVIN_TO_CELSIUS(curr.batt.temperature));
-	DUMP_BATT(state_of_charge, "%d%%");
-	DUMP_BATT(voltage, "%dmV");
-	DUMP_BATT(current, "%dmA");
-	DUMP_BATT(desired_voltage, "%dmV");
-	DUMP_BATT(desired_current, "%dmA");
-	DUMP_BATT(flags, "0x%x");
-	DUMP_BATT(remaining_capacity, "%dmAh");
-	DUMP_BATT(full_capacity, "%dmAh");
-	ccprintf("\tis_present = %s\n", batt_pres[curr.batt.is_present]);
-	cflush();
-#ifdef CONFIG_OCPC
-	ccprintf("ocpc.*:\n");
-	DUMP_OCPC(active_chg_chip, "%d");
-	DUMP_OCPC(combined_rsys_rbatt_mo, "%dmOhm");
-	if ((curr.ocpc.active_chg_chip != -1) &&
-	    !(curr.ocpc.chg_flags[curr.ocpc.active_chg_chip] &
-	      OCPC_NO_ISYS_MEAS_CAP)) {
-		DUMP_OCPC(rbatt_mo, "%dmOhm");
-		DUMP_OCPC(rsys_mo, "%dmOhm");
-		DUMP_OCPC(isys_ma, "%dmA");
-	}
-	DUMP_OCPC(vsys_aux_mv, "%dmV");
-	DUMP_OCPC(vsys_mv, "%dmV");
-	DUMP_OCPC(primary_vbus_mv, "%dmV");
-	DUMP_OCPC(primary_ibus_ma, "%dmA");
-	DUMP_OCPC(secondary_vbus_mv, "%dmV");
-	DUMP_OCPC(secondary_ibus_ma, "%dmA");
-	DUMP_OCPC(last_error, "%d");
-	DUMP_OCPC(integral, "%d");
-	DUMP_OCPC(last_vsys, "%dmV");
-	cflush();
-#endif /* CONFIG_OCPC */
-	DUMP(requested_voltage, "%dmV");
-	DUMP(requested_current, "%dmA");
-#ifdef CONFIG_CHARGER_OTG
-	DUMP(output_current, "%dmA");
-#endif
-#ifdef CONFIG_EC_EC_COMM_BATTERY_MASTER
-	DUMP(input_voltage, "%dmV");
-#endif
-	ccprintf("chg_ctl_mode = %d\n", chg_ctl_mode);
-	ccprintf("manual_voltage = %d\n", manual_voltage);
-	ccprintf("manual_current = %d\n", manual_current);
-	ccprintf("user_current_limit = %dmA\n", user_current_limit);
-	ccprintf("battery_seems_to_be_dead = %d\n", battery_seems_to_be_dead);
-	ccprintf("battery_seems_to_be_disconnected = %d\n",
-		 battery_seems_to_be_disconnected);
-	ccprintf("battery_was_removed = %d\n", battery_was_removed);
-	ccprintf("debug output = %s\n", debugging ? "on" : "off");
-#undef DUMP
-}
-
-static void show_charging_progress(void)
-{
-	int rv = 0, minutes, to_full, chgnum = 0;
-
-#ifdef CONFIG_BATTERY_SMART
-	/*
-	 * Predicted remaining battery capacity based on AverageCurrent().
-	 * 65535 = Battery is not being discharged.
-	 */
-	if (!battery_time_to_empty(&minutes) && minutes != 65535)
-		to_full = 0;
-	/*
-	 * Predicted time-to-full charge based on AverageCurrent().
-	 * 65535 = Battery is not being discharged.
-	 */
-	else if (!battery_time_to_full(&minutes) && minutes != 65535)
-		to_full = 1;
-	/*
-	 * If both time to empty and time to full have invalid data, consider
-	 * measured current from the coulomb counter and ac present status to
-	 * decide whether battery is about to full or empty.
-	 */
-	else {
-		to_full = curr.batt_is_charging;
-		rv = EC_ERROR_UNKNOWN;
-	}
-#else
-	if (!curr.batt_is_charging) {
-		rv = battery_time_to_empty(&minutes);
-		to_full = 0;
-	} else {
-		rv = battery_time_to_full(&minutes);
-		to_full = 1;
-	}
-#endif
-
-	if (rv)
-		CPRINTS("Battery %d%% (Display %d.%d %%) / ??h:?? %s%s",
-			curr.batt.state_of_charge,
-			curr.batt.display_charge / 10,
-			curr.batt.display_charge % 10,
-			to_full ? "to full" : "to empty",
-			is_full ? ", not accepting current" : "");
-	else
-		CPRINTS("Battery %d%% (Display %d.%d %%) / %dh:%d %s%s",
-			curr.batt.state_of_charge,
-			curr.batt.display_charge / 10,
-			curr.batt.display_charge % 10,
-			minutes / 60, minutes % 60,
-			to_full ? "to full" : "to empty",
-			is_full ? ", not accepting current" : "");
-
-#ifdef CONFIG_EC_EC_COMM_BATTERY_MASTER
-	CPRINTS("Base battery %d%%", charge_base);
-#endif
-
-	if (debugging) {
-		ccprintf("battery:\n");
-		print_battery_debug();
-		ccprintf("charger:\n");
-		if (IS_ENABLED(CONFIG_OCPC))
-			chgnum = charge_get_active_chg_chip();
-		print_charger_debug(chgnum);
-		ccprintf("chg:\n");
-		dump_charge_state();
-	}
-}
-
-/* Calculate if battery is full based on whether it is accepting charge */
-static int calc_is_full(void)
-{
-	static int __bss_slow ret;
-
-	/* If bad state of charge reading, return last value */
-	if (curr.batt.flags & BATT_FLAG_BAD_STATE_OF_CHARGE ||
-	    curr.batt.state_of_charge > 100)
-		return ret;
-	/*
-	 * Battery is full when SoC is above 90% and battery desired current
-	 * is 0. This is necessary because some batteries stop charging when
-	 * the SoC still reports <100%, so we need to check desired current
-	 * to know if it is actually full.
-	 */
-	ret = (curr.batt.state_of_charge >= 90 &&
-	       curr.batt.desired_current == 0);
-	return ret;
-}
-
-/*
- * Ask the charger for some voltage and current. If either value is 0,
- * charging is disabled; otherwise it's enabled. Negative values are ignored.
- */
-static int charge_request(int voltage, int current)
-{
-	int r1 = EC_SUCCESS, r2 = EC_SUCCESS, r3 = EC_SUCCESS, r4 = EC_SUCCESS;
-	static int __bss_slow prev_volt, prev_curr;
-
-	if (!voltage || !current) {
-#ifdef CONFIG_CHARGER_NARROW_VDC
-		current = 0;
-		/*
-		 * With NVDC charger, keep VSYS voltage higher than battery,
-		 * otherwise the BGATE FET body diode would conduct and
-		 * discharge the battery.
-		 */
-		voltage = charger_closest_voltage(
-			curr.batt.voltage + charger_get_info()->voltage_step);
-		/* If the battery is full, request the max voltage. */
-		if (is_full)
-			voltage = battery_get_info()->voltage_max;
-		/* And handle dead battery case */
-		voltage = MAX(voltage, battery_get_info()->voltage_normal);
-#else
-		voltage = current = 0;
-#endif
-	}
-
-	if (curr.ac) {
-		if (prev_volt != voltage || prev_curr != current)
-			CPRINTS("%s(%dmV, %dmA)", __func__, voltage, current);
-	}
-
-	/*
-	 * Set current before voltage so that if we are just starting
-	 * to charge, we allow some time (i2c delay) for charging circuit to
-	 * start at a voltage just above battery voltage before jumping
-	 * up. This helps avoid large current spikes when connecting
-	 * battery.
-	 */
-	if (current >= 0)
-		r2 = charger_set_current(0, current);
-	if (r2 != EC_SUCCESS)
-		problem(PR_SET_CURRENT, r2);
-
-	if (voltage >= 0)
-		r1 = charger_set_voltage(0, voltage);
-	if (r1 != EC_SUCCESS)
-		problem(PR_SET_VOLTAGE, r1);
-
-#ifdef CONFIG_OCPC
-	/*
-	 * For OCPC systems, if the secondary charger is active, we need to
-	 * configure that charge IC as well.  Note that if OCPC ever supports
-	 * more than 2 charger ICs, we'll need to refactor things a bit.  The
-	 * following check should be comparing against CHARGER_PRIMARY and
-	 * config_secondary_charger should probably be config_auxiliary_charger
-	 * and take the active chgnum as a parameter.
-	 */
-	if (curr.ocpc.active_chg_chip == CHARGER_SECONDARY) {
-		if ((current >= 0) || (voltage >= 0))
-			r3 = ocpc_config_secondary_charger(&curr.desired_input_current,
-							   &curr.ocpc,
-							   voltage, current);
-		if (r3 != EC_SUCCESS)
-			problem(PR_CFG_SEC_CHG, r3);
-	}
-#endif /* CONFIG_OCPC */
-
-	/*
-	 * Set the charge inhibit bit when possible as it appears to save
-	 * power in some cases (e.g. Nyan with BQ24735).
-	 */
-	if (voltage > 0 || current > 0)
-		r4 = charger_set_mode(0);
-	else
-		r4 = charger_set_mode(CHARGE_FLAG_INHIBIT_CHARGE);
-	if (r4 != EC_SUCCESS)
-		problem(PR_SET_MODE, r4);
-
-	/*
-	 * Only update if the request worked, so we'll keep trying on failures.
-	 */
-	if (r1 || r2)
-		return r1 ? r1 : r2;
-	if (IS_ENABLED(CONFIG_OCPC) && r3)
-		return r3;
-
-	if (IS_ENABLED(CONFIG_USB_PD_PREFER_MV) &&
-	    (prev_volt != voltage || prev_curr != current))
-		charge_reset_stable_current();
-
-	prev_volt = voltage;
-	prev_curr = current;
-
-	return EC_SUCCESS;
-}
-
-void chgstate_set_manual_current(int curr_ma)
-{
-	if (curr_ma < 0)
-		manual_current = -1;
-	else
-		manual_current = charger_closest_current(curr_ma);
-}
-
-void chgstate_set_manual_voltage(int volt_mv)
-{
-	manual_voltage = charger_closest_voltage(volt_mv);
-}
-
-/* Force charging off before the battery is full. */
-static int set_chg_ctrl_mode(enum ec_charge_control_mode mode)
-{
-	if (mode == CHARGE_CONTROL_NORMAL) {
-		chg_ctl_mode = mode;
-		manual_current = -1;
-		manual_voltage = -1;
-	} else {
-		/*
-		 * Changing mode is only meaningful if external power is
-		 * present. If it's not present we can't charge anyway.
-		 */
-		if (!curr.ac)
-			return EC_ERROR_NOT_POWERED;
-
-		chg_ctl_mode = mode;
-		manual_current = 0;
-		manual_voltage = 0;
-	}
-
-	return EC_SUCCESS;
-}
-
-static inline int battery_too_hot(int batt_temp_c)
-{
-	return (!(curr.batt.flags & BATT_FLAG_BAD_TEMPERATURE) &&
-		(batt_temp_c > batt_info->discharging_max_c));
-}
-
-static inline int battery_too_cold_for_discharge(int batt_temp_c)
-{
-	return (!(curr.batt.flags & BATT_FLAG_BAD_TEMPERATURE) &&
-		(batt_temp_c < batt_info->discharging_min_c));
-}
-
-__attribute__((weak)) uint8_t board_set_battery_level_shutdown(void)
-{
-	return BATTERY_LEVEL_SHUTDOWN;
-}
-
-/* True if we know the charge is too low, or we know the voltage is too low. */
-static inline int battery_too_low(void)
-{
-	return ((!(curr.batt.flags & BATT_FLAG_BAD_STATE_OF_CHARGE) &&
-		 curr.batt.state_of_charge < battery_level_shutdown) ||
-		(!(curr.batt.flags & BATT_FLAG_BAD_VOLTAGE) &&
-		 curr.batt.voltage <= batt_info->voltage_min));
-}
-
-__attribute__((weak))
-enum critical_shutdown board_critical_shutdown_check(
-		struct charge_state_data *curr)
-{
-#ifdef CONFIG_BATTERY_CRITICAL_SHUTDOWN_CUT_OFF
-	return CRITICAL_SHUTDOWN_CUTOFF;
-#elif defined(CONFIG_HIBERNATE)
-	return CRITICAL_SHUTDOWN_HIBERNATE;
-#else
-	return CRITICAL_SHUTDOWN_IGNORE;
-#endif
-}
-
-static int is_battery_critical(void)
-{
-	int batt_temp_c = DECI_KELVIN_TO_CELSIUS(curr.batt.temperature);
-
-	/*
-	 * TODO(crosbug.com/p/27642): The thermal loop should watch the battery
-	 * temp, so it can turn fans on.
-	 */
-	if (battery_too_hot(batt_temp_c)) {
-		CPRINTS("Batt too hot: %dC", batt_temp_c);
-		return 1;
-	}
-
-	/* Note: the battery may run on AC without discharging when too cold */
-	if (!curr.ac && battery_too_cold_for_discharge(batt_temp_c)) {
-		CPRINTS("Batt too cold: %dC", batt_temp_c);
-		return 1;
-	}
-
-	if (battery_too_low() && !curr.batt_is_charging) {
-		CPRINTS("Low battery: %d%%, %dmV",
-			curr.batt.state_of_charge, curr.batt.voltage);
-		return 1;
-	}
-
-	return 0;
-}
-
- /*
-  * If the battery is at extremely low charge (and discharging) or extremely
-  * high temperature, the EC will notify the AP and start a timer. If the
-  * critical condition is not corrected before the timeout expires, the EC
-  * will shut down the AP (if the AP is not already off) and then optionally
-  * hibernate or cut off battery.
-  */
-static int shutdown_on_critical_battery(void)
-{
-	if (!is_battery_critical()) {
-		/* Reset shutdown warning time */
-		shutdown_target_time.val = 0;
-		return 0;
-	}
-
-	if (!shutdown_target_time.val) {
-		/* Start count down timer */
-		CPRINTS("Start shutdown due to critical battery");
-		shutdown_target_time.val = get_time().val
-				+ CRITICAL_BATTERY_SHUTDOWN_TIMEOUT_US;
-#ifdef CONFIG_HOSTCMD_EVENTS
-		if (!chipset_in_state(CHIPSET_STATE_ANY_OFF))
-			host_set_single_event(EC_HOST_EVENT_BATTERY_SHUTDOWN);
-#endif
-		return 1;
-	}
-
-	if (!timestamp_expired(shutdown_target_time, 0))
-		return 1;
-
-	/* Timer has expired */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
-		switch (board_critical_shutdown_check(&curr)) {
-		case CRITICAL_SHUTDOWN_HIBERNATE:
-			CPRINTS("Hibernate due to critical battery");
-			system_hibernate(0, 0);
-			break;
-		case CRITICAL_SHUTDOWN_CUTOFF:
-			CPRINTS("Cutoff due to critical battery");
-			/* Ensure logs are flushed. */
-			cflush();
-			board_cut_off_battery();
-			break;
-		case CRITICAL_SHUTDOWN_IGNORE:
-		default:
-			break;
-		}
-	} else {
-		/* Timeout waiting for AP to shut down, so kill it */
-		CPRINTS(
-		  "charge force shutdown due to critical battery");
-		chipset_force_shutdown(CHIPSET_SHUTDOWN_BATTERY_CRIT);
-	}
-
-	return 1;
-}
-
-/*
- * Send host events as the battery charge drops below certain thresholds.
- * We handle forced shutdown and other actions elsewhere; this is just for the
- * host events. We send these even if the AP is off, since the AP will read and
- * discard any events it doesn't care about the next time it wakes up.
- */
-static void notify_host_of_low_battery_charge(void)
-{
-	/* We can't tell what the current charge is. Assume it's okay. */
-	if (curr.batt.flags & BATT_FLAG_BAD_STATE_OF_CHARGE)
-		return;
-
-#ifdef CONFIG_HOSTCMD_EVENTS
-	if (curr.batt.state_of_charge <= BATTERY_LEVEL_LOW &&
-	    prev_charge > BATTERY_LEVEL_LOW)
-		host_set_single_event(EC_HOST_EVENT_BATTERY_LOW);
-
-	if (curr.batt.state_of_charge <= BATTERY_LEVEL_CRITICAL &&
-	    prev_charge > BATTERY_LEVEL_CRITICAL)
-		host_set_single_event(EC_HOST_EVENT_BATTERY_CRITICAL);
-#endif
-}
-
-static void set_charge_state(enum charge_state_v2 state)
-{
-	prev_state = curr.state;
-	curr.state = state;
-}
-
-static void notify_host_of_low_battery_voltage(void)
-{
-#ifdef CONFIG_THROTTLE_AP_ON_BAT_VOLTAGE
-	if ((curr.batt.flags & BATT_FLAG_BAD_VOLTAGE) ||
-	    chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return;
-
-	if (!uvp_throttle_start_time.val &&
-	    (curr.batt.voltage < BAT_LOW_VOLTAGE_THRESH)) {
-		throttle_ap(THROTTLE_ON, THROTTLE_SOFT,
-			    THROTTLE_SRC_BAT_VOLTAGE);
-		uvp_throttle_start_time = get_time();
-	} else if (uvp_throttle_start_time.val &&
-		   (curr.batt.voltage < BAT_LOW_VOLTAGE_THRESH +
-		    BAT_UVP_HYSTERESIS)) {
-		/*
-		 * Reset the timer when we are not sure if VBAT can stay
-		 * above BAT_LOW_VOLTAGE_THRESH after we stop throttling.
-		 */
-		uvp_throttle_start_time = get_time();
-	} else if (uvp_throttle_start_time.val &&
-		   (get_time().val > uvp_throttle_start_time.val +
-		     BAT_UVP_TIMEOUT_US)) {
-		throttle_ap(THROTTLE_OFF, THROTTLE_SOFT,
-			    THROTTLE_SRC_BAT_VOLTAGE);
-		uvp_throttle_start_time.val = 0;
-	}
-#endif
-}
-
-static void notify_host_of_over_current(struct batt_params *batt)
-{
-#ifdef CONFIG_THROTTLE_AP_ON_BAT_DISCHG_CURRENT
-	static timestamp_t ocp_throttle_start_time;
-
-	if (batt->flags & BATT_FLAG_BAD_CURRENT)
-		return;
-
-	if ((!ocp_throttle_start_time.val &&
-	     (batt->current < -BAT_MAX_DISCHG_CURRENT)) ||
-	    (ocp_throttle_start_time.val &&
-	     (batt->current < -BAT_MAX_DISCHG_CURRENT + BAT_OCP_HYSTERESIS))) {
-		ocp_throttle_start_time = get_time();
-		throttle_ap(THROTTLE_ON, THROTTLE_SOFT,
-			    THROTTLE_SRC_BAT_DISCHG_CURRENT);
-	} else if (ocp_throttle_start_time.val &&
-		   (get_time().val > ocp_throttle_start_time.val +
-		    BAT_OCP_TIMEOUT_US)) {
-		/*
-		 * Clear the timer and notify AP to stop throttling if
-		 * we haven't seen over current for BAT_OCP_TIMEOUT_US.
-		 */
-		ocp_throttle_start_time.val = 0;
-		throttle_ap(THROTTLE_OFF, THROTTLE_SOFT,
-			    THROTTLE_SRC_BAT_DISCHG_CURRENT);
-	}
-#endif
-}
-
-const struct batt_params *charger_current_battery_params(void)
-{
-	return &curr.batt;
-}
-
-#ifdef CONFIG_BATTERY_CHECK_CHARGE_TEMP_LIMITS
-/* Determine if the battery is outside of allowable temperature range */
-static int battery_outside_charging_temperature(void)
-{
-	const struct battery_info *batt_info = battery_get_info();
-	/* battery temp in 0.1 deg C */
-	int batt_temp_c = DECI_KELVIN_TO_CELSIUS(curr.batt.temperature);
-	int max_c, min_c;
-
-	if (curr.batt.flags & BATT_FLAG_BAD_TEMPERATURE)
-		return 0;
-
-	if((curr.batt.desired_voltage == 0) &&
-		(curr.batt.desired_current == 0)){
-		max_c = batt_info->start_charging_max_c;
-		min_c = batt_info->start_charging_min_c;
-	} else {
-		max_c = batt_info->charging_max_c;
-		min_c = batt_info->charging_min_c;
-	}
-
-
-	if ((batt_temp_c >= max_c) ||
-		 (batt_temp_c <= min_c)) {
-		return 1;
-	}
-	return 0;
-}
-#endif
-
-/*****************************************************************************/
-/* Hooks */
-void charger_init(void)
-{
-	/* Initialize current state */
-	memset(&curr, 0, sizeof(curr));
-	curr.batt.is_present = BP_NOT_SURE;
-	/* Manual voltage/current set to off */
-	manual_voltage = -1;
-	manual_current = -1;
-	/*
-	 * Other tasks read the params like state_of_charge at the beginning of
-	 * their tasks. Make them ready first.
-	 */
-	battery_get_params(&curr.batt);
-}
-DECLARE_HOOK(HOOK_INIT, charger_init, HOOK_PRIO_DEFAULT);
-
-/* Wake up the task when something important happens */
-static void charge_wakeup(void)
-{
-	task_wake(TASK_ID_CHARGER);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, charge_wakeup, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_AC_CHANGE, charge_wakeup, HOOK_PRIO_DEFAULT);
-
-#ifdef CONFIG_EC_EC_COMM_BATTERY_MASTER
-/* Reset the base on S5->S0 transition. */
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_base_reset, HOOK_PRIO_DEFAULT);
-#endif
-
-#ifdef CONFIG_THROTTLE_AP_ON_BAT_VOLTAGE
-static void bat_low_voltage_throttle_reset(void)
-{
-	uvp_throttle_start_time.val = 0;
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN,
-	     bat_low_voltage_throttle_reset,
-	     HOOK_PRIO_DEFAULT);
-#endif
-
-static int get_desired_input_current(enum battery_present batt_present,
-				     const struct charger_info * const info)
-{
-	if (batt_present == BP_YES || system_is_locked() || base_connected) {
-#ifdef CONFIG_CHARGE_MANAGER
-		int ilim = charge_manager_get_charger_current();
-		return ilim == CHARGE_CURRENT_UNINITIALIZED ?
-			CHARGE_CURRENT_UNINITIALIZED :
-			MAX(CONFIG_CHARGER_INPUT_CURRENT, ilim);
-#else
-		return CONFIG_CHARGER_INPUT_CURRENT;
-#endif
-	} else {
-#ifdef CONFIG_USB_POWER_DELIVERY
-		return MIN(PD_MAX_CURRENT_MA, info->input_current_max);
-#else
-		return info->input_current_max;
-#endif
-	}
-}
-
-/* Main loop */
-void charger_task(void *u)
-{
-	int sleep_usec;
-	int battery_critical;
-	int need_static = 1;
-	const struct charger_info * const info = charger_get_info();
-	int prev_plt_and_desired_mw;
-	int chgnum = 0;
-
-	/* Get the battery-specific values */
-	batt_info = battery_get_info();
-
-	prev_ac = prev_charge = prev_disp_charge = -1;
-	chg_ctl_mode = CHARGE_CONTROL_NORMAL;
-	shutdown_target_time.val = 0UL;
-	battery_seems_to_be_dead = 0;
-#ifdef CONFIG_EC_EC_COMM_BATTERY_MASTER
-	base_responsive = 0;
-	curr.input_voltage = CHARGE_VOLTAGE_UNINITIALIZED;
-	battery_dynamic[BATT_IDX_BASE].flags = EC_BATT_FLAG_INVALID_DATA;
-	charge_base = -1;
-#endif
-#ifdef CONFIG_OCPC
-	ocpc_init(&curr.ocpc);
-	charge_set_active_chg_chip(CHARGE_PORT_NONE);
-#endif /* CONFIG_OCPC */
-
-	/*
-	 * If system is not locked and we don't have a battery to live on,
-	 * then use max input current limit so that we can pull as much power
-	 * as needed.
-	 */
-	prev_bp = BP_NOT_INIT;
-	curr.desired_input_current = get_desired_input_current(
-			curr.batt.is_present, info);
-
-	if (IS_ENABLED(CONFIG_USB_PD_PREFER_MV)) {
-		/* init battery desired power */
-		desired_mw =
-			curr.batt.desired_current * curr.batt.desired_voltage;
-		/*
-		 * Battery charging current needs time to be stable when a
-		 * new charge happens. Start the timer so we can evaluate the
-		 * stable current when timeout.
-		 */
-		charge_reset_stable_current();
-	}
-
-	battery_level_shutdown = board_set_battery_level_shutdown();
-
-	while (1) {
-
-		/* Let's see what's going on... */
-		curr.ts = get_time();
-		sleep_usec = 0;
-		problems_exist = 0;
-		battery_critical = 0;
-		curr.ac = extpower_is_present();
-#ifdef CONFIG_EC_EC_COMM_BATTERY_MASTER
-		/*
-		 * When base is powering the system, make sure curr.ac stays 0.
-		 * TODO(b:71723024): Fix extpower_is_present() in hardware
-		 * instead.
-		 */
-		if (base_responsive && prev_current_base < 0)
-			curr.ac = 0;
-
-		/* System is off: if AC gets connected, reset the base. */
-		if (chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
-				!prev_ac && curr.ac)
-			board_base_reset();
-#endif
-		if (curr.ac != prev_ac) {
-			if (curr.ac) {
-				/*
-				 * Some chargers are unpowered when the AC is
-				 * off, so we'll reinitialize it when AC
-				 * comes back and set the input current limit.
-				 * Try again if it fails.
-				 */
-				int rv = charger_post_init();
-				if (rv != EC_SUCCESS) {
-					problem(PR_POST_INIT, rv);
-				} else {
-					if (curr.desired_input_current !=
-					    CHARGE_CURRENT_UNINITIALIZED)
-						rv = charger_set_input_current(
-						    chgnum,
-						    curr.desired_input_current);
-					if (rv != EC_SUCCESS)
-						problem(PR_SET_INPUT_CURR, rv);
-					else
-						prev_ac = curr.ac;
-				}
-			} else {
-				/* Some things are only meaningful on AC */
-				chg_ctl_mode = CHARGE_CONTROL_NORMAL;
-				battery_seems_to_be_dead = 0;
-				prev_ac = curr.ac;
-			}
-		}
-
-#ifdef CONFIG_EC_EC_COMM_BATTERY_MASTER
-		update_base_battery_info();
-#endif
-
-		charger_get_params(&curr.chg);
-		battery_get_params(&curr.batt);
-#ifdef CONFIG_OCPC
-		if (curr.ac)
-			ocpc_get_adcs(&curr.ocpc);
-#endif /* CONFIG_OCPC */
-
-		if (prev_bp != curr.batt.is_present) {
-			prev_bp = curr.batt.is_present;
-
-			/* Update battery info due to change of battery */
-			batt_info = battery_get_info();
-			need_static = 1;
-
-			curr.desired_input_current =
-				get_desired_input_current(prev_bp, info);
-			if (curr.desired_input_current !=
-			    CHARGE_CURRENT_UNINITIALIZED)
-				charger_set_input_current(chgnum,
-					curr.desired_input_current);
-			hook_notify(HOOK_BATTERY_SOC_CHANGE);
-		}
-
-		/*
-		 * TODO(crosbug.com/p/27527). Sometimes the battery thinks its
-		 * temperature is 6280C, which seems a bit high. Let's ignore
-		 * anything above the boiling point of tungsten until this bug
-		 * is fixed. If the battery is really that warm, we probably
-		 * have more urgent problems.
-		 */
-		if (curr.batt.temperature > CELSIUS_TO_DECI_KELVIN(5660)) {
-			CPRINTS("ignoring ridiculous batt.temp of %dC",
-				 DECI_KELVIN_TO_CELSIUS(curr.batt.temperature));
-			curr.batt.flags |= BATT_FLAG_BAD_TEMPERATURE;
-		}
-
-		/* If the battery thinks it's above 100%, don't believe it */
-		if (curr.batt.state_of_charge > 100) {
-			CPRINTS("ignoring ridiculous batt.soc of %d%%",
-				curr.batt.state_of_charge);
-			curr.batt.flags |= BATT_FLAG_BAD_STATE_OF_CHARGE;
-		}
-
-		notify_host_of_over_current(&curr.batt);
-
-		/* battery current stable now, saves the current. */
-		if (IS_ENABLED(CONFIG_USB_PD_PREFER_MV) &&
-		    get_time().val > stable_ts.val && curr.batt.current >= 0)
-			stable_current = curr.batt.current;
-
-		/*
-		 * Now decide what we want to do about it. We'll normally just
-		 * pass along whatever the battery wants to the charger. Note
-		 * that if battery_get_params() can't get valid values from the
-		 * battery it uses (0, 0), which is probably safer than blindly
-		 * applying power to a battery we can't talk to.
-		 */
-		if (curr.batt.flags & (BATT_FLAG_BAD_DESIRED_VOLTAGE |
-					BATT_FLAG_BAD_DESIRED_CURRENT)) {
-			curr.requested_voltage = 0;
-			curr.requested_current = 0;
-		} else {
-			curr.requested_voltage = curr.batt.desired_voltage;
-			curr.requested_current = curr.batt.desired_current;
-		}
-
-		/* If we *know* there's no battery, wait for one to appear. */
-		if (curr.batt.is_present == BP_NO) {
-			if (!curr.ac)
-				CPRINTS("running with no battery and no AC");
-			set_charge_state(ST_IDLE);
-			curr.batt_is_charging = 0;
-			battery_was_removed = 1;
-			goto wait_for_it;
-		}
-
-		/*
-		 * If we had trouble talking to the battery or the charger, we
-		 * should probably do nothing for a bit, and if it doesn't get
-		 * better then flag it as an error.
-		 */
-		if (curr.chg.flags & CHG_FLAG_BAD_ANY)
-			problem(PR_CHG_FLAGS, curr.chg.flags);
-		if (curr.batt.flags & BATT_FLAG_BAD_ANY)
-			problem(PR_BATT_FLAGS, curr.batt.flags);
-
-		/*
-		 * If AC is present, check if input current is sufficient to
-		 * actually charge battery.
-		 */
-		curr.batt_is_charging = curr.ac && (curr.batt.current >= 0);
-
-		/* Don't let the battery hurt itself. */
-		battery_critical = shutdown_on_critical_battery();
-
-		if (!curr.ac) {
-			set_charge_state(ST_DISCHARGE);
-			goto wait_for_it;
-		}
-
-		/* Okay, we're on AC and we should have a battery. */
-
-		/* Used for factory tests. */
-		if (chg_ctl_mode != CHARGE_CONTROL_NORMAL) {
-			set_charge_state(ST_IDLE);
-			goto wait_for_it;
-		}
-
-		/* If the battery is not responsive, try to wake it up. */
-		if (!(curr.batt.flags & BATT_FLAG_RESPONSIVE)) {
-			if (battery_seems_to_be_dead || battery_is_cut_off()) {
-				/* It's dead, do nothing */
-				set_charge_state(ST_IDLE);
-				curr.requested_voltage = 0;
-				curr.requested_current = 0;
-			} else if (curr.state == ST_PRECHARGE &&
-				   (get_time().val > precharge_start_time.val +
-				    PRECHARGE_TIMEOUT_US)) {
-				/* We've tried long enough, give up */
-				CPRINTS("battery seems to be dead");
-				battery_seems_to_be_dead = 1;
-				set_charge_state(ST_IDLE);
-				curr.requested_voltage = 0;
-				curr.requested_current = 0;
-			} else {
-				/* See if we can wake it up */
-				if (curr.state != ST_PRECHARGE) {
-					CPRINTS("try to wake battery");
-					precharge_start_time = get_time();
-					need_static = 1;
-				}
-				set_charge_state(ST_PRECHARGE);
-				curr.requested_voltage =
-					batt_info->voltage_max;
-				curr.requested_current =
-					batt_info->precharge_current;
-			}
-			goto wait_for_it;
-		} else {
-			/* The battery is responding. Yay. Try to use it. */
-#ifdef CONFIG_BATTERY_REQUESTS_NIL_WHEN_DEAD
-			/*
-			 * TODO (crosbug.com/p/29467): remove this workaround
-			 * for dead battery that requests no voltage/current
-			 */
-			if (curr.requested_voltage == 0 &&
-			    curr.requested_current == 0 &&
-#ifdef CONFIG_BATTERY_DEAD_UNTIL_VALUE
-			    curr.batt.state_of_charge < CONFIG_BATTERY_DEAD_UNTIL_VALUE) {
-#else
-			    curr.batt.state_of_charge == 0) {
-#endif
-				/* Battery is dead, give precharge current */
-				curr.requested_voltage =
-					batt_info->voltage_max;
-				curr.requested_current =
-					batt_info->precharge_current;
-			} else
-#endif
-#ifdef CONFIG_BATTERY_REVIVE_DISCONNECT
-			/*
-			 * Always check the disconnect state.  This is because
-			 * the battery disconnect state is one of the items used
-			 * to decide whether or not to leave safe mode.
-			 */
-			battery_seems_to_be_disconnected =
-				battery_get_disconnect_state() ==
-				BATTERY_DISCONNECTED;
-
-			if (curr.requested_voltage == 0 &&
-			    curr.requested_current == 0 &&
-			    battery_seems_to_be_disconnected) {
-				/*
-				 * Battery is in disconnect state. Apply a
-				 * current to kick it out of this state.
-				 */
-				CPRINTS("found battery in disconnect state");
-				curr.requested_voltage =
-					batt_info->voltage_max;
-				curr.requested_current =
-					batt_info->precharge_current;
-			} else
-#endif
-			if (curr.state == ST_PRECHARGE ||
-			    battery_seems_to_be_dead ||
-			    battery_was_removed) {
-				CPRINTS("battery woke up");
-
-				/* Update the battery-specific values */
-				batt_info = battery_get_info();
-				need_static = 1;
-			    }
-
-			battery_seems_to_be_dead = battery_was_removed = 0;
-			set_charge_state(ST_CHARGE);
-		}
-
-wait_for_it:
-#ifdef CONFIG_CHARGER_PROFILE_OVERRIDE
-		if (chg_ctl_mode == CHARGE_CONTROL_NORMAL) {
-			sleep_usec = charger_profile_override(&curr);
-			if (sleep_usec < 0)
-				problem(PR_CUSTOM, sleep_usec);
-		}
-#endif
-
-#ifdef CONFIG_BATTERY_CHECK_CHARGE_TEMP_LIMITS
-		if (battery_outside_charging_temperature()) {
-			curr.requested_current = 0;
-			curr.requested_voltage = 0;
-			curr.batt.flags &= ~BATT_FLAG_WANT_CHARGE;
-			if (curr.state != ST_DISCHARGE)
-				curr.state = ST_IDLE;
-		}
-#endif
-
-#ifdef CONFIG_CHARGE_MANAGER
-		if (curr.batt.state_of_charge >=
-		    CONFIG_CHARGE_MANAGER_BAT_PCT_SAFE_MODE_EXIT &&
-		    !battery_seems_to_be_disconnected) {
-			/*
-			 * Sometimes the fuel gauge will report that it has
-			 * sufficient state of charge and remaining capacity,
-			 * but in actuality it doesn't.  When the EC sees that
-			 * information, it trusts it and leaves charge manager
-			 * safe mode.  Doing so will allow CHARGE_PORT_NONE to
-			 * be selected, thereby cutting off the input FETs.
-			 * When the battery cannot provide the charge it claims,
-			 * the system loses power, shuts down, and the battery
-			 * is not charged even though the charger is plugged in.
-			 * By waiting 500ms, we can avoid the selection of
-			 * CHARGE_PORT_NONE around init time and not cut off the
-			 * input FETs.
-			 */
-			msleep(500);
-			charge_manager_leave_safe_mode();
-		}
-#endif
-
-		/* Keep the AP informed */
-		if (need_static)
-			need_static = update_static_battery_info();
-		/* Wait on the dynamic info until the static info is good. */
-		if (!need_static)
-			update_dynamic_battery_info();
-		notify_host_of_low_battery_charge();
-		notify_host_of_low_battery_voltage();
-
-		/* And the EC console */
-		is_full = calc_is_full();
-		if ((!(curr.batt.flags & BATT_FLAG_BAD_STATE_OF_CHARGE) &&
-		    curr.batt.state_of_charge != prev_charge) ||
-#ifdef CONFIG_EC_EC_COMM_BATTERY_MASTER
-		    (charge_base != prev_charge_base) ||
-#endif
-		    (is_full != prev_full) ||
-		    (curr.state != prev_state) ||
-		    (curr.batt.display_charge != prev_disp_charge)) {
-			show_charging_progress();
-			prev_charge = curr.batt.state_of_charge;
-			prev_disp_charge = curr.batt.display_charge;
-#ifdef CONFIG_EC_EC_COMM_BATTERY_MASTER
-			prev_charge_base = charge_base;
-#endif
-			hook_notify(HOOK_BATTERY_SOC_CHANGE);
-		}
-		prev_full = is_full;
-
-#ifndef CONFIG_CHARGER_MAINTAIN_VBAT
-		/* Turn charger off if it's not needed */
-		if (curr.state == ST_IDLE || curr.state == ST_DISCHARGE) {
-			curr.requested_voltage = 0;
-			curr.requested_current = 0;
-		}
-#endif
-
-		/* Apply external limits */
-		if (curr.requested_current > user_current_limit)
-			curr.requested_current = user_current_limit;
-
-		/* Round to valid values */
-		curr.requested_voltage =
-			charger_closest_voltage(curr.requested_voltage);
-		curr.requested_current =
-			charger_closest_current(curr.requested_current);
-
-		/* Charger only accpets request when AC is on. */
-		if (curr.ac) {
-			/*
-			 * Some batteries would wake up after cut-off if we keep
-			 * charging it. Thus, we only charge when AC is on and
-			 * battery is not cut off yet.
-			 */
-			if (battery_is_cut_off()) {
-				curr.requested_voltage = 0;
-				curr.requested_current = 0;
-			}
-			/*
-			 * As a safety feature, some chargers will stop
-			 * charging if we don't communicate with it frequently
-			 * enough. In manual mode, we'll just tell it what it
-			 * knows.
-			 */
-			else {
-				if (manual_voltage != -1)
-					curr.requested_voltage = manual_voltage;
-				if (manual_current != -1)
-					curr.requested_current = manual_current;
-			}
-		} else {
-#ifndef CONFIG_CHARGER_MAINTAIN_VBAT
-			curr.requested_voltage = charger_closest_voltage(
-				curr.batt.voltage + info->voltage_step);
-			curr.requested_current = -1;
-#endif
-#ifdef CONFIG_EC_EC_COMM_BATTERY_SLAVE
-			/*
-			 * On EC-EC slave, do not charge if curr.ac is 0: there
-			 * might still be some external power available but we
-			 * do not want to use it for charging.
-			 */
-			curr.requested_current = 0;
-#endif
-		}
-
-#ifdef CONFIG_EC_EC_COMM_BATTERY_MASTER
-		charge_allocate_input_current_limit();
-#else
-		charge_request(curr.requested_voltage, curr.requested_current);
-#endif
-
-		/* How long to sleep? */
-		if (problems_exist)
-			/* If there are errors, don't wait very long. */
-			sleep_usec = CHARGE_POLL_PERIOD_SHORT;
-		else if (sleep_usec <= 0) {
-			/* default values depend on the state */
-			if (!curr.ac &&
-			    (curr.state == ST_IDLE ||
-			    curr.state == ST_DISCHARGE)) {
-#ifdef CONFIG_CHARGER_OTG
-				int output_current = curr.output_current;
-#else
-				int output_current = 0;
-#endif
-				/*
-				 * If AP is off and we do not provide power, we
-				 * can sleep a long time.
-				 */
-				if (chipset_in_state(CHIPSET_STATE_ANY_OFF |
-						     CHIPSET_STATE_ANY_SUSPEND)
-						&& output_current == 0)
-					sleep_usec =
-						CHARGE_POLL_PERIOD_VERY_LONG;
-				else
-					/* Discharging, not too urgent */
-					sleep_usec = CHARGE_POLL_PERIOD_LONG;
-			} else {
-				/* AC present, so pay closer attention */
-				sleep_usec = CHARGE_POLL_PERIOD_CHARGE;
-			}
-		}
-
-		if (IS_ENABLED(CONFIG_USB_PD_PREFER_MV)) {
-			int is_pd_supply = charge_manager_get_supplier() ==
-					   CHARGE_SUPPLIER_PD;
-			int port = charge_manager_get_active_charge_port();
-			int bat_spec_desired_mw = curr.batt.desired_current *
-						  curr.batt.desired_voltage /
-						  1000;
-
-			/*
-			 * save the previous plt_and_desired_mw, since it
-			 * will be updated below
-			 */
-			prev_plt_and_desired_mw =
-				charge_get_plt_plus_bat_desired_mw();
-
-			/*
-			 * Update desired power by the following rules:
-			 * 1. If the battery is not charging with PD, we reset
-			 * the desired_mw to the battery spec. The actual
-			 * desired_mw will be evaluated when it starts charging
-			 * with PD again.
-			 * 2. If the battery SoC under battery's constant
-			 * voltage percent (this is a rough value that can be
-			 * applied to most batteries), the battery can fully
-			 * sink the power, the desired power should be the
-			 * same as the battery spec, and we don't need to use
-			 * evaluated value stable_current.
-			 * 3. If the battery SoC is above battery's constant
-			 * voltage percent, the real battery desired charging
-			 * power will decrease slowly and so does the charging
-			 * current. We can evaluate the battery desired power
-			 * by the product of stable_current and battery voltage.
-			 */
-			if (!is_pd_supply)
-				desired_mw = bat_spec_desired_mw;
-			else if (curr.batt.state_of_charge < pd_pref_config.cv)
-				desired_mw = bat_spec_desired_mw;
-			else if (stable_current != CHARGE_CURRENT_UNINITIALIZED)
-				desired_mw = curr.batt.voltage *
-					     stable_current / 1000;
-
-			/* if the plt_and_desired_mw changes, re-evaluate PDO */
-			if (is_pd_supply &&
-			    prev_plt_and_desired_mw !=
-				    charge_get_plt_plus_bat_desired_mw())
-				pd_set_new_power_request(port);
-		}
-
-		/* Adjust for time spent in this loop */
-		sleep_usec -= (int)(get_time().val - curr.ts.val);
-		if (sleep_usec < CHARGE_MIN_SLEEP_USEC)
-			sleep_usec = CHARGE_MIN_SLEEP_USEC;
-		else if (sleep_usec > CHARGE_MAX_SLEEP_USEC)
-			sleep_usec = CHARGE_MAX_SLEEP_USEC;
-
-		/*
-		 * If battery is critical, ensure that the sleep time is not
-		 * very long since we might want to hibernate or cut-off
-		 * battery sooner.
-		 */
-		if (battery_critical &&
-		    (sleep_usec > CRITICAL_BATTERY_SHUTDOWN_TIMEOUT_US))
-			sleep_usec = CRITICAL_BATTERY_SHUTDOWN_TIMEOUT_US;
-
-		task_wait_event(sleep_usec);
-	}
-}
-
-
-/*****************************************************************************/
-/* Exported functions */
-
-int charge_want_shutdown(void)
-{
-	return (curr.state == ST_DISCHARGE) &&
-		!(curr.batt.flags & BATT_FLAG_BAD_STATE_OF_CHARGE) &&
-		(curr.batt.state_of_charge < battery_level_shutdown);
-}
-
-int charge_prevent_power_on(int power_button_pressed)
-{
-	int prevent_power_on = 0;
-	struct batt_params params;
-	struct batt_params *current_batt_params = &curr.batt;
-#ifdef CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON
-	static int automatic_power_on = 1;
-#endif
-
-	/* If battery params seem uninitialized then retrieve them */
-	if (current_batt_params->is_present == BP_NOT_SURE) {
-		battery_get_params(&params);
-		current_batt_params = &params;
-	}
-
-#ifdef CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON
-
-	/*
-	 * Remember that a power button was pressed, and assume subsequent
-	 * power-ups are user-requested and non-automatic.
-	 */
-	if (power_button_pressed)
-		automatic_power_on = 0;
-	/*
-	 * Require a minimum battery level to power on and ensure that the
-	 * battery can provide power to the system.
-	 */
-	if (current_batt_params->is_present != BP_YES ||
-#ifdef CONFIG_BATTERY_MEASURE_IMBALANCE
-	    (current_batt_params->flags & BATT_FLAG_IMBALANCED_CELL &&
-		current_batt_params->state_of_charge <
-		CONFIG_CHARGER_MIN_BAT_PCT_IMBALANCED_POWER_ON) ||
-#endif
-#ifdef CONFIG_BATTERY_REVIVE_DISCONNECT
-	    battery_get_disconnect_state() != BATTERY_NOT_DISCONNECTED ||
-#endif
-	    current_batt_params->state_of_charge <
-		CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON)
-		prevent_power_on = 1;
-
-#if defined(CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON) && \
-	defined(CONFIG_CHARGE_MANAGER)
-	/* However, we can power on if a sufficient charger is present. */
-	if (prevent_power_on) {
-		if (charge_manager_get_power_limit_uw() >=
-		    CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON * 1000)
-			prevent_power_on = 0;
-#if defined(CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT) && \
-	defined(CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC)
-		else if (charge_manager_get_power_limit_uw() >=
-		    CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT * 1000
-#ifdef CONFIG_BATTERY_REVIVE_DISCONNECT
-		    && battery_get_disconnect_state() ==
-							BATTERY_NOT_DISCONNECTED
-#endif
-		    && (current_batt_params->state_of_charge >=
-			CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC))
-			prevent_power_on = 0;
-#endif
-	}
-#endif /* CONFIG_CHARGE_MANAGER && CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON */
-
-	/*
-	 * Factory override: Always allow power on if WP is disabled,
-	 * except when auto-power-on at EC startup and the battery
-	 * is physically present.
-	 */
-	prevent_power_on &= (system_is_locked() || (automatic_power_on
-#ifdef CONFIG_BATTERY_HW_PRESENT_CUSTOM
-				    && battery_hw_present() == BP_YES
-#endif
-				     ));
-#endif /* CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON */
-
-#ifdef CONFIG_CHARGE_MANAGER
-	/* Always prevent power on until charge current is initialized */
-	if (extpower_is_present() &&
-	    (charge_manager_get_charger_current() ==
-	     CHARGE_CURRENT_UNINITIALIZED))
-		prevent_power_on = 1;
-#ifdef CONFIG_BATTERY_HW_PRESENT_CUSTOM
-	/*
-	 * If battery is NOT physically present then prevent power on until
-	 * a sufficient charger is present.
-	 */
-	if (extpower_is_present() && battery_hw_present() == BP_NO
-#ifdef CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
-	    && charge_manager_get_power_limit_uw() <
-		CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON * 1000
-#endif /* CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON */
-	    )
-		prevent_power_on = 1;
-#endif /* CONFIG_BATTERY_HW_PRESENT_CUSTOM */
-#endif /* CONFIG_CHARGE_MANAGER */
-
-	/*
-	 * Prevent power on if there is no battery nor ac power. This
-	 * happens when the servo is powering the EC to flash it. Only include
-	 * this logic for boards in initial bring up phase since this won't
-	 * happen for released boards.
-	 */
-#ifdef CONFIG_SYSTEM_UNLOCKED
-	if (!current_batt_params->is_present && !curr.ac)
-		prevent_power_on = 1;
-#endif /* CONFIG_SYSTEM_UNLOCKED */
-
-	return prevent_power_on;
-}
-
-static int battery_near_full(void)
-{
-	if (charge_get_percent() < BATTERY_LEVEL_NEAR_FULL)
-		return 0;
-
-#ifdef CONFIG_EC_EC_COMM_BATTERY_MASTER
-	if (charge_base > -1 && charge_base < BATTERY_LEVEL_NEAR_FULL)
-		return 0;
-#endif
-
-	return 1;
-}
-
-enum charge_state charge_get_state(void)
-{
-	switch (curr.state) {
-	case ST_IDLE:
-		if (battery_seems_to_be_dead || curr.batt.is_present == BP_NO)
-			return PWR_STATE_ERROR;
-		return PWR_STATE_IDLE;
-	case ST_DISCHARGE:
-#ifdef CONFIG_PWR_STATE_DISCHARGE_FULL
-		if (battery_near_full())
-			return PWR_STATE_DISCHARGE_FULL;
-		else
-#endif
-			return PWR_STATE_DISCHARGE;
-	case ST_CHARGE:
-		/* The only difference here is what the LEDs display. */
-		if (battery_near_full())
-			return PWR_STATE_CHARGE_NEAR_FULL;
-		else
-			return PWR_STATE_CHARGE;
-	case ST_PRECHARGE:
-		/* we're in battery discovery mode */
-		return PWR_STATE_IDLE;
-	default:
-		/* Anything else can be considered an error for LED purposes */
-		return PWR_STATE_ERROR;
-	}
-}
-
-uint32_t charge_get_flags(void)
-{
-	uint32_t flags = 0;
-
-	if (chg_ctl_mode != CHARGE_CONTROL_NORMAL)
-		flags |= CHARGE_FLAG_FORCE_IDLE;
-	if (curr.ac)
-		flags |= CHARGE_FLAG_EXTERNAL_POWER;
-	if (curr.batt.flags & BATT_FLAG_RESPONSIVE)
-		flags |= CHARGE_FLAG_BATT_RESPONSIVE;
-
-	return flags;
-}
-
-int charge_get_percent(void)
-{
-	/*
-	 * Since there's no way to indicate an error to the caller, we'll just
-	 * return the last known value. Even if we've never been able to talk
-	 * to the battery, that'll be zero, which is probably as good as
-	 * anything.
-	 */
-	return is_full ? 100 : curr.batt.state_of_charge;
-}
-
-int charge_get_display_charge(void)
-{
-	return curr.batt.display_charge;
-}
-
-int charge_get_battery_temp(int idx, int *temp_ptr)
-{
-	if (curr.batt.flags & BATT_FLAG_BAD_TEMPERATURE)
-		return EC_ERROR_UNKNOWN;
-
-	/* Battery temp is 10ths of degrees K, temp wants degrees K */
-	*temp_ptr = curr.batt.temperature / 10;
-	return EC_SUCCESS;
-}
-
-__overridable int charge_is_consuming_full_input_current(void)
-{
-	int chg_pct = charge_get_percent();
-
-	return chg_pct > 2 && chg_pct < 95;
-}
-
-#ifdef CONFIG_CHARGER_OTG
-int charge_set_output_current_limit(int chgnum, int ma, int mv)
-{
-	int ret;
-	int enable = ma > 0;
-
-	if (enable) {
-		ret = charger_set_otg_current_voltage(chgnum, ma, mv);
-		if (ret != EC_SUCCESS)
-			return ret;
-	}
-
-	ret = charger_enable_otg_power(chgnum, enable);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	/* If we start/stop providing power, wake the charger task. */
-	if ((curr.output_current == 0 && enable) ||
-	    (curr.output_current > 0 && !enable))
-		task_wake(TASK_ID_CHARGER);
-
-	curr.output_current = ma;
-
-	return EC_SUCCESS;
-}
-#endif
-
-int charge_set_input_current_limit(int ma, int mv)
-{
-	__maybe_unused int chgnum = 0;
-
-	if (IS_ENABLED(CONFIG_OCPC))
-		chgnum = charge_get_active_chg_chip();
-#ifdef CONFIG_EC_EC_COMM_BATTERY_MASTER
-	curr.input_voltage = mv;
-#endif
-	/*
-	 * If battery is not present, we are not locked, and base is not
-	 * connected then allow system to pull as much input current as needed.
-	 * Yes, we might overcurrent the charger but this is no worse than
-	 * browning out due to insufficient input current.
-	 */
-	if (curr.batt.is_present != BP_YES && !system_is_locked() &&
-		!base_connected) {
-
-		int prev_input = 0;
-
-		charger_get_input_current(chgnum, &prev_input);
-
-#ifdef CONFIG_USB_POWER_DELIVERY
-#if ((PD_MAX_POWER_MW * 1000) / PD_MAX_VOLTAGE_MV != PD_MAX_CURRENT_MA)
-		/*
-		 * If battery is not present, input current is set to
-		 * PD_MAX_CURRENT_MA. If the input power set is greater than
-		 * the maximum allowed system power, system might get damaged.
-		 * Hence, limit the input current to meet maximum allowed
-		 * input system power.
-		 */
-
-		if (mv > 0 && mv * curr.desired_input_current >
-			PD_MAX_POWER_MW * 1000)
-			ma = (PD_MAX_POWER_MW * 1000) / mv;
-		/*
-		 * If the active charger has already been initialized to at
-		 * least this current level, nothing left to do.
-		 */
-		else if (prev_input >= ma)
-			return EC_SUCCESS;
-#else
-		if (prev_input >= ma)
-			return EC_SUCCESS;
-#endif
-		/*
-		 * If the current needs lowered due to PD max power
-		 * considerations, or needs raised for the selected active
-		 * charger chip, fall through to set.
-		 */
-#endif /* CONFIG_USB_POWER_DELIVERY */
-	}
-
-#ifdef CONFIG_CHARGER_MAX_INPUT_CURRENT
-	/* Limit input current limit to max limit for this board */
-	ma = MIN(ma, CONFIG_CHARGER_MAX_INPUT_CURRENT);
-#endif
-	curr.desired_input_current = ma;
-#ifdef CONFIG_EC_EC_COMM_BATTERY_MASTER
-	/* Wake up charger task to allocate current between lid and base. */
-	charge_wakeup();
-	return EC_SUCCESS;
-#else
-	return charger_set_input_current(chgnum, ma);
-#endif
-}
-
-#ifdef CONFIG_OCPC
-void charge_set_active_chg_chip(int idx)
-{
-	ASSERT(idx < (int)board_get_charger_chip_count());
-
-	if (idx == curr.ocpc.active_chg_chip)
-		return;
-
-	CPRINTS("Act Chg: %d", idx);
-	curr.ocpc.active_chg_chip = idx;
-	if (idx == CHARGE_PORT_NONE) {
-		curr.ocpc.last_error = 0;
-		curr.ocpc.integral = 0;
-		curr.ocpc.last_vsys = OCPC_UNINIT;
-	}
-}
-#endif /* CONFIG_OCPC */
-
-int charge_get_active_chg_chip(void)
-{
-#ifdef CONFIG_OCPC
-	return curr.ocpc.active_chg_chip;
-#else
-	return 0;
-#endif
-}
-
-#ifdef CONFIG_USB_PD_PREFER_MV
-bool charge_is_current_stable(void)
-{
-	return get_time().val >= stable_ts.val;
-}
-
-int charge_get_plt_plus_bat_desired_mw(void)
-{
-	/*
-	 * Ideally, the system consuming power could be evaluated by
-	 * "IBus * VBus - battery charging power". But in practice,
-	 * most charger drivers don't implement IBUS ADC reading,
-	 * so we use system PLT instead as an alterntaive approach.
-	 */
-	return pd_pref_config.plt_mw + desired_mw;
-}
-
-int charge_get_stable_current(void)
-{
-	return stable_current;
-}
-
-void charge_set_stable_current(int ma)
-{
-	stable_current = ma;
-}
-
-void charge_reset_stable_current_us(uint64_t us)
-{
-	timestamp_t now = get_time();
-
-	if (stable_ts.val < now.val + us)
-		stable_ts.val = now.val + us;
-
-	stable_current = CHARGE_CURRENT_UNINITIALIZED;
-}
-
-void charge_reset_stable_current(void)
-{
-	/* it takes 8 to 10 seconds to stabilize battery current in practice */
-	charge_reset_stable_current_us(10 * SECOND);
-}
-#endif
-
-/*****************************************************************************/
-/* Host commands */
-
-static enum ec_status
-charge_command_charge_control(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_charge_control *p = args->params;
-	int rv;
-
-	rv = set_chg_ctrl_mode(p->mode);
-	if (rv != EC_SUCCESS)
-		return EC_RES_ERROR;
-
-#ifdef CONFIG_CHARGER_DISCHARGE_ON_AC
-#ifdef CONFIG_CHARGER_DISCHARGE_ON_AC_CUSTOM
-	rv = board_discharge_on_ac(p->mode == CHARGE_CONTROL_DISCHARGE);
-#else
-	rv = charger_discharge_on_ac(p->mode == CHARGE_CONTROL_DISCHARGE);
-#endif
-	if (rv != EC_SUCCESS)
-		return EC_RES_ERROR;
-#endif
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_CHARGE_CONTROL, charge_command_charge_control,
-		     EC_VER_MASK(1));
-
-static void reset_current_limit(void)
-{
-	user_current_limit = -1U;
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, reset_current_limit, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, reset_current_limit, HOOK_PRIO_DEFAULT);
-
-static enum ec_status
-charge_command_current_limit(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_current_limit *p = args->params;
-
-	user_current_limit = p->limit;
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_CHARGE_CURRENT_LIMIT, charge_command_current_limit,
-		     EC_VER_MASK(0));
-
-static enum ec_status
-charge_command_charge_state(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_charge_state *in = args->params;
-	struct ec_response_charge_state *out = args->response;
-	uint32_t val;
-	int rv = EC_RES_SUCCESS;
-	int chgnum = 0;
-
-	if (args->version > 0)
-		chgnum = in->chgnum;
-
-	switch (in->cmd) {
-
-	case CHARGE_STATE_CMD_GET_STATE:
-		out->get_state.ac = curr.ac;
-		out->get_state.chg_voltage = curr.chg.voltage;
-		out->get_state.chg_current = curr.chg.current;
-		out->get_state.chg_input_current = curr.chg.input_current;
-		out->get_state.batt_state_of_charge = curr.batt.state_of_charge;
-		args->response_size = sizeof(out->get_state);
-		break;
-
-	case CHARGE_STATE_CMD_GET_PARAM:
-		val = 0;
-#ifdef CONFIG_CHARGER_PROFILE_OVERRIDE
-		/* custom profile params */
-		if (in->get_param.param >= CS_PARAM_CUSTOM_PROFILE_MIN &&
-		    in->get_param.param <= CS_PARAM_CUSTOM_PROFILE_MAX) {
-			rv  = charger_profile_override_get_param(
-				in->get_param.param, &val);
-		} else
-#endif
-#ifdef CONFIG_CHARGE_STATE_DEBUG
-		/* debug params */
-		if (in->get_param.param >= CS_PARAM_DEBUG_MIN &&
-		    in->get_param.param <= CS_PARAM_DEBUG_MAX) {
-			rv = charge_get_charge_state_debug(
-				in->get_param.param, &val);
-		} else
-#endif
-			/* standard params */
-			switch (in->get_param.param) {
-			case CS_PARAM_CHG_VOLTAGE:
-				val = curr.chg.voltage;
-				break;
-			case CS_PARAM_CHG_CURRENT:
-				val = curr.chg.current;
-				break;
-			case CS_PARAM_CHG_INPUT_CURRENT:
-				val = curr.chg.input_current;
-				break;
-			case CS_PARAM_CHG_STATUS:
-				val = curr.chg.status;
-				break;
-			case CS_PARAM_CHG_OPTION:
-				val = curr.chg.option;
-				break;
-			case CS_PARAM_LIMIT_POWER:
-#ifdef CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW
-				/*
-				 * LIMIT_POWER status is based on battery level
-				 * and external charger power.
-				 */
-				if ((curr.batt.is_present != BP_YES ||
-				     curr.batt.state_of_charge <
-				     CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT)
-				     && charge_manager_get_power_limit_uw() <
-				     CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW
-				     * 1000 && system_is_locked())
-					val = 1;
-				else
-#endif
-					val = 0;
-				break;
-			default:
-				rv = EC_RES_INVALID_PARAM;
-			}
-
-		/* got something */
-		out->get_param.value = val;
-		args->response_size = sizeof(out->get_param);
-		break;
-
-	case CHARGE_STATE_CMD_SET_PARAM:
-		if (system_is_locked())
-			return EC_RES_ACCESS_DENIED;
-
-		val = in->set_param.value;
-#ifdef CONFIG_CHARGER_PROFILE_OVERRIDE
-		/* custom profile params */
-		if (in->set_param.param >= CS_PARAM_CUSTOM_PROFILE_MIN &&
-		    in->set_param.param <= CS_PARAM_CUSTOM_PROFILE_MAX) {
-			rv  = charger_profile_override_set_param(
-				in->set_param.param, val);
-		} else
-#endif
-			switch (in->set_param.param) {
-			case CS_PARAM_CHG_VOLTAGE:
-				chgstate_set_manual_voltage(val);
-				break;
-			case CS_PARAM_CHG_CURRENT:
-				chgstate_set_manual_current(val);
-				break;
-			case CS_PARAM_CHG_INPUT_CURRENT:
-				if (charger_set_input_current(chgnum, val))
-					rv = EC_RES_ERROR;
-				break;
-			case CS_PARAM_CHG_STATUS:
-			case CS_PARAM_LIMIT_POWER:
-				/* Can't set this */
-				rv = EC_RES_ACCESS_DENIED;
-				break;
-			case CS_PARAM_CHG_OPTION:
-				if (charger_set_option(val))
-					rv = EC_RES_ERROR;
-				break;
-			default:
-				rv = EC_RES_INVALID_PARAM;
-
-			}
-		break;
-
-	default:
-		CPRINTS("EC_CMD_CHARGE_STATE: bad cmd 0x%x", in->cmd);
-		rv = EC_RES_INVALID_PARAM;
-	}
-
-	return rv;
-}
-
-DECLARE_HOST_COMMAND(EC_CMD_CHARGE_STATE, charge_command_charge_state,
-		     EC_VER_MASK(0) | EC_VER_MASK(1));
-
-/*****************************************************************************/
-/* Console commands */
-
-#ifdef CONFIG_CMD_PWR_AVG
-
-static int command_pwr_avg(int argc, char **argv)
-{
-	int avg_mv;
-	int avg_ma;
-	int avg_mw;
-
-	if (argc != 1)
-		return EC_ERROR_PARAM_COUNT;
-
-	avg_mv = battery_get_avg_voltage();
-	if (avg_mv < 0)
-		return EC_ERROR_UNKNOWN;
-	avg_ma = battery_get_avg_current();
-	avg_mw = avg_mv * avg_ma / 1000;
-
-	ccprintf("mv = %d\nma = %d\nmw = %d\n",
-		avg_mv, avg_ma, avg_mw);
-	return EC_SUCCESS;
-}
-
-DECLARE_CONSOLE_COMMAND(pwr_avg, command_pwr_avg,
-			NULL,
-			"Get 1 min power average");
-
-#endif /* CONFIG_CMD_PWR_AVG */
-
-static int command_chgstate(int argc, char **argv)
-{
-	int rv;
-	int val;
-
-	if (argc > 1) {
-		if (!strcasecmp(argv[1], "idle")) {
-			if (argc <= 2)
-				return EC_ERROR_PARAM_COUNT;
-			if (!parse_bool(argv[2], &val))
-				return EC_ERROR_PARAM2;
-			rv = set_chg_ctrl_mode(val ? CHARGE_CONTROL_IDLE :
-						CHARGE_CONTROL_NORMAL);
-			if (rv)
-				return rv;
-#ifdef CONFIG_CHARGER_DISCHARGE_ON_AC
-		} else if (!strcasecmp(argv[1], "discharge")) {
-			if (argc <= 2)
-				return EC_ERROR_PARAM_COUNT;
-			if (!parse_bool(argv[2], &val))
-				return EC_ERROR_PARAM2;
-			rv = set_chg_ctrl_mode(val ? CHARGE_CONTROL_DISCHARGE :
-						CHARGE_CONTROL_NORMAL);
-			if (rv)
-				return rv;
-#ifdef CONFIG_CHARGER_DISCHARGE_ON_AC_CUSTOM
-			rv = board_discharge_on_ac(val);
-#else
-			rv = charger_discharge_on_ac(val);
-#endif /* CONFIG_CHARGER_DISCHARGE_ON_AC_CUSTOM */
-			if (rv)
-				return rv;
-#endif /* CONFIG_CHARGER_DISCHARGE_ON_AC */
-		} else if (!strcasecmp(argv[1], "debug")) {
-			if (argc <= 2)
-				return EC_ERROR_PARAM_COUNT;
-			if (!parse_bool(argv[2], &debugging))
-				return EC_ERROR_PARAM2;
-		} else {
-			return EC_ERROR_PARAM1;
-		}
-	}
-
-	dump_charge_state();
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(chgstate, command_chgstate,
-			"[idle|discharge|debug on|off]",
-			"Get/set charge state machine status");
-
-#ifdef CONFIG_EC_EC_COMM_BATTERY_MASTER
-static int command_chgdualdebug(int argc, char **argv)
-{
-	int val;
-	char *e;
-
-	if (argc > 1) {
-		if (argv[1][0] == 'c') {
-			if (argc <= 2)
-				return EC_ERROR_PARAM_COUNT;
-
-			if (!strcasecmp(argv[2], "auto")) {
-				val = -1;
-			} else {
-				val = strtoi(argv[2], &e, 0);
-				if (*e || val < 0)
-					return EC_ERROR_PARAM2;
-			}
-
-			manual_ac_current_base = val;
-			charge_wakeup();
-		} else if (argv[1][0] == 'd') {
-			if (argc <= 2)
-				return EC_ERROR_PARAM_COUNT;
-
-			if (!strcasecmp(argv[2], "auto")) {
-				manual_noac_enabled = 0;
-			} else {
-				val = strtoi(argv[2], &e, 0);
-				if (*e)
-					return EC_ERROR_PARAM2;
-				manual_noac_current_base = val;
-				manual_noac_enabled = 1;
-			}
-			charge_wakeup();
-		} else {
-			return EC_ERROR_PARAM1;
-		}
-	} else {
-		ccprintf("Base/Lid: %d%s/%d mA\n",
-			 prev_current_base, prev_allow_charge_base ? "+" : "",
-			 prev_current_lid);
-	}
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(chgdualdebug, command_chgdualdebug,
-			"[charge (auto|<current>)|discharge (auto|<current>)]",
-			"Manually control dual-battery charging algorithm.");
-#endif
-
-#ifdef CONFIG_CHARGE_STATE_DEBUG
-int charge_get_charge_state_debug(int param, uint32_t *value)
-{
-	switch (param) {
-	case CS_PARAM_DEBUG_CTL_MODE:
-		*value = chg_ctl_mode;
-		break;
-	case CS_PARAM_DEBUG_MANUAL_CURRENT:
-		*value = manual_current;
-		break;
-	case CS_PARAM_DEBUG_MANUAL_VOLTAGE:
-		*value = manual_voltage;
-		break;
-	case CS_PARAM_DEBUG_SEEMS_DEAD:
-		*value = battery_seems_to_be_dead;
-		break;
-	case CS_PARAM_DEBUG_SEEMS_DISCONNECTED:
-		*value = battery_seems_to_be_disconnected;
-		break;
-	case CS_PARAM_DEBUG_BATT_REMOVED:
-		*value = battery_was_removed;
-		break;
-	default:
-		*value = 0;
-		return EC_ERROR_INVAL;
-	}
-
-	return EC_SUCCESS;
-}
-#endif
diff --git a/common/chargen.c b/common/chargen.c
index 24e30bb878..626e13e71f 100644
--- a/common/chargen.c
+++ b/common/chargen.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,6 +6,8 @@
 #include "common.h"
 #include "config.h"
 #include "console.h"
+#include "hooks.h"
+#include "task.h"
 #include "timer.h"
 #include "uart.h"
 #include "usb_console.h"
@@ -13,62 +15,75 @@
 #include "watchdog.h"
 
 #ifndef SECTION_IS_RO
+
+/**
+ * Some unit tests do not have a watchdog enabled and the watchdog
+ * functions are stubbed. Define a default watchdog period in this case.
+ */
+#ifdef CONFIG_WATCHDOG_PERIOD_MS
+#define CHARGEN_WATCHDOG_PERIOD_MS CONFIG_WATCHDOG_PERIOD_MS
+#else
+#define CHARGEN_WATCHDOG_PERIOD_MS 1600
+#endif
+
 /*
  * Microseconds time to drain entire UART_TX console buffer at 115200 b/s, 10
  * bits per character.
  */
-#define BUFFER_DRAIN_TIME_US (1000000UL * 10 * CONFIG_UART_TX_BUF_SIZE         \
-				/ CONFIG_UART_BAUD_RATE)
+#define BUFFER_DRAIN_TIME_US \
+	(1000000UL * 10 * CONFIG_UART_TX_BUF_SIZE / CONFIG_UART_BAUD_RATE)
+
+struct deferred_chargen_ctx {
+	int wrap_value;
+	uint32_t seq_number;
+	int (*putc)(int c);
+	int (*tx_is_blocked)(void);
+};
+static struct deferred_chargen_ctx chargen_ctx;
+
+static void acquire_console(void)
+{
+#if !defined(CONFIG_USB_CONSOLE) && !defined(CONFIG_USB_CONSOLE_STREAM)
+	uart_shell_rx_bypass(true);
+#endif
+#if !defined(CONFIG_ZEPHYR) && !defined(BOARD_HOST)
+	/* The legacy fw console does not have an rx bypass feature (it is
+	 * stubbed out).  Disable the console task so that it does not
+	 * steal character reads from chargen.
+	 */
+	if (task_start_called())
+		task_disable_task(TASK_ID_CONSOLE);
+#endif /* !CONFIG_ZEPHYR  && !BOARD_HOST */
+}
 
-/*
- * Generate a stream of characters on the UART (and USB) console.
- *
- * The stream is an ever incrementing pattern of characters from the following
- * set: 0..9A..Za..z.
- *
- * The two optional integer command line arguments work as follows:
- *
- * argv[1] - reset the pattern after this many characters have been printed.
- *           Setting this value to the width of the terminal window results
- *           in a very regular stream showing on the terminal, where it is
- *           easy to observe disruptions.
- * argv[2] - limit number of printed characters to this amount. If not
- *           specified - keep printing indefinitely.
- *
- * Hitting 'x' on the keyboard stops the generator.
- */
-static int command_chargen(int argc, char **argv)
+static void release_console(void)
 {
-	int wrap_value = 0;
-	int wrap_counter = 0;
-	uint8_t c;
-	uint32_t seq_counter = 0;
-	uint32_t seq_number = 0;
+#if !defined(CONFIG_USB_CONSOLE) && !defined(CONFIG_USB_CONSOLE_STREAM)
+	uart_shell_rx_bypass(false);
+#endif
+#if !defined(CONFIG_ZEPHYR) && !defined(BOARD_HOST)
+	if (task_start_called())
+		task_enable_task(TASK_ID_CONSOLE);
+#endif /* !CONFIG_ZEPHYR  && !BOARD_HOST */
+}
+
+static void run_chargen(void)
+{
+	int wrap_value = chargen_ctx.wrap_value;
+	uint32_t seq_number = chargen_ctx.seq_number;
+	int (*putc_)(int c) = chargen_ctx.putc;
+	int (*tx_is_blocked_)(void) = chargen_ctx.tx_is_blocked;
+
 	timestamp_t prev_watchdog_time;
+	uint8_t c = '0';
+	uint32_t seq_counter = 0;
+	int wrap_counter = 0;
 
-	int (*putc_)(int c) = uart_putc;
-	int (*tx_is_blocked_)(void) = uart_buffer_full;
+	acquire_console();
 
 	while (uart_getc() != -1 || usb_getc() != -1)
 		; /* Drain received characters, if any. */
 
-	if (argc > 1)
-		wrap_value = atoi(argv[1]);
-
-	if (argc > 2)
-		seq_number = atoi(argv[2]);
-
-#if defined(CONFIG_USB_CONSOLE) || defined(CONFIG_USB_CONSOLE_STREAM)
-	if (argc > 3) {
-		if (memcmp(argv[3], "usb", 3))
-			return EC_ERROR_PARAM3;
-
-		putc_ = usb_putc;
-		tx_is_blocked_ = usb_console_tx_blocked;
-	}
-#endif
-
-	c = '0';
 	prev_watchdog_time = get_time();
 	while (uart_getc() != 'x' && usb_getc() != 'x') {
 		timestamp_t current_time;
@@ -78,18 +93,21 @@ static int command_chargen(int argc, char **argv)
 			 * Let's let other tasks run for a bit while buffer is
 			 * being drained a little.
 			 */
-			usleep(BUFFER_DRAIN_TIME_US/10);
+			usleep(BUFFER_DRAIN_TIME_US / 10);
 
 			current_time = get_time();
 
 			if ((current_time.val - prev_watchdog_time.val) <
-			    (CONFIG_WATCHDOG_PERIOD_MS * 1000 / 2))
+			    (CHARGEN_WATCHDOG_PERIOD_MS * 1000 / 2))
 				continue;
 
 			watchdog_reload();
 			prev_watchdog_time.val = current_time.val;
 		}
 
+		if (IS_ENABLED(CONFIG_ZEPHYR) && c == '0')
+			watchdog_reload();
+
 		putc_(c++);
 
 		if (seq_number && (++seq_counter == seq_number))
@@ -105,12 +123,63 @@ static int command_chargen(int argc, char **argv)
 			c = '0';
 		else if (c == ('Z' + 1))
 			c = 'a';
-		else if (c  == ('9' + 1))
+		else if (c == ('9' + 1))
 			c = 'A';
 	}
 
 	putc_('\n');
-	return EC_SUCCESS;
+
+	release_console();
+}
+DECLARE_DEFERRED(run_chargen);
+
+/*
+ * Generate a stream of characters on the UART (and USB) console.
+ *
+ * The stream is an ever incrementing pattern of characters from the following
+ * set: 0..9A..Za..z.
+ *
+ * The two optional integer command line arguments work as follows:
+ *
+ * argv[1] - reset the pattern after this many characters have been printed.
+ *           Setting this value to the width of the terminal window results
+ *           in a very regular stream showing on the terminal, where it is
+ *           easy to observe disruptions.
+ * argv[2] - limit number of printed characters to this amount. If not
+ *           specified - keep printing indefinitely.
+ *
+ * Hitting 'x' on the keyboard stops the generator.
+ */
+static int command_chargen(int argc, const char **argv)
+{
+	int wrap_value = 0;
+	uint32_t seq_number = 0;
+
+	int (*putc_)(int c) = uart_putc;
+	int (*tx_is_blocked_)(void) = uart_buffer_full;
+
+	if (argc > 1)
+		wrap_value = atoi(argv[1]);
+
+	if (argc > 2)
+		seq_number = atoi(argv[2]);
+
+#if defined(CONFIG_USB_CONSOLE) || defined(CONFIG_USB_CONSOLE_STREAM)
+	if (argc > 3) {
+		if (memcmp(argv[3], "usb", 3))
+			return EC_ERROR_PARAM3;
+
+		putc_ = usb_putc;
+		tx_is_blocked_ = usb_console_tx_blocked;
+	}
+#endif
+
+	chargen_ctx.wrap_value = wrap_value;
+	chargen_ctx.seq_number = seq_number;
+	chargen_ctx.putc = putc_;
+	chargen_ctx.tx_is_blocked = tx_is_blocked_;
+
+	return hook_call_deferred(&run_chargen_data, 0);
 }
 DECLARE_SAFE_CONSOLE_COMMAND(chargen, command_chargen,
 #if defined(CONFIG_USB_CONSOLE) || defined(CONFIG_USB_CONSOLE_STREAM)
@@ -120,6 +189,5 @@ DECLARE_SAFE_CONSOLE_COMMAND(chargen, command_chargen,
 #endif
 			     "Generate a constant stream of characters on the "
 			     "UART console,\nrepeating every 'seq_length' "
-			     "characters, up to 'num_chars' total."
-	);
-#endif  /* !SECTION_IS_RO */
+			     "characters, up to 'num_chars' total.");
+#endif /* !SECTION_IS_RO */
diff --git a/common/charger.c b/common/charger.c
index 4037af9854..95eeb06467 100644
--- a/common/charger.c
+++ b/common/charger.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -6,19 +6,20 @@
  */
 
 #include "battery_smart.h"
-#include "charge_state_v2.h"
+#include "builtin/assert.h"
+#include "charge_state.h"
 #include "charger.h"
 #include "common.h"
 #include "console.h"
 #include "dptf.h"
+#include "hooks.h"
 #include "host_command.h"
 #include "printf.h"
 #include "util.h"
-#include "hooks.h"
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CHARGER, outstr)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 /* DPTF current limit, -1 = none */
 static int dptf_limit_ma = -1;
@@ -71,7 +72,7 @@ int charger_closest_voltage(int voltage)
 
 int charger_closest_current(int current)
 {
-	const struct charger_info * const info = charger_get_info();
+	const struct charger_info *const info = charger_get_info();
 
 	/* Apply DPTF limit if necessary */
 	if (dptf_limit_ma >= 0 && current > dptf_limit_ma)
@@ -96,8 +97,12 @@ void charger_get_params(struct charger_params *chg)
 {
 	int chgnum = 0;
 
-	if (IS_ENABLED(CONFIG_OCPC))
+	if (IS_ENABLED(CONFIG_OCPC)) {
 		chgnum = charge_get_active_chg_chip();
+		/* set to CHARGE_PORT_NONE when no charger connected */
+		if (chgnum < 0)
+			chgnum = 0;
+	}
 
 	memset(chg, 0, sizeof(*chg));
 
@@ -111,7 +116,7 @@ void charger_get_params(struct charger_params *chg)
 	if (charger_get_voltage(chgnum, &chg->voltage))
 		chg->flags |= CHG_FLAG_BAD_VOLTAGE;
 
-	if (charger_get_input_current(chgnum, &chg->input_current))
+	if (charger_get_input_current_limit(chgnum, &chg->input_current))
 		chg->flags |= CHG_FLAG_BAD_INPUT_CURRENT;
 
 	if (charger_get_status(&chg->status))
@@ -146,7 +151,7 @@ void print_charger_debug(int chgnum)
 	/* option */
 	print_item_name("Option:");
 	if (check_print_error(charger_get_option(&d)))
-		ccprintf("%pb (0x%04x)\n", BINARY_VALUE(d, 16), d);
+		ccprintf("(0x%04x)\n", d);
 
 	/* manufacturer id */
 	print_item_name("Man id:");
@@ -158,33 +163,46 @@ void print_charger_debug(int chgnum)
 	if (check_print_error(charger_device_id(&d)))
 		ccprintf("0x%04x\n", d);
 
+	/* dptf current limit */
+	print_item_name("I_dptf:");
+	if (dptf_limit_ma >= 0)
+		ccprintf("%5d\n", dptf_limit_ma);
+	else
+		ccputs("disabled\n");
+
+	/* Limits */
+	ccprintf("Limits\t\t\t ( min    max  step)\n");
+
 	/* charge voltage limit */
-	print_item_name("V_batt:");
+	print_item_name("chg_voltage:");
 	if (check_print_error(charger_get_voltage(chgnum, &d)))
-		ccprintf("%5d (%4d - %5d, %3d)\n", d, info->voltage_min,
+		ccprintf("\t%5d mV (%4d - %5d, %3d)\n", d, info->voltage_min,
 			 info->voltage_max, info->voltage_step);
 
 	/* charge current limit */
-	print_item_name("I_batt:");
+	print_item_name("chg_current:");
 	if (check_print_error(charger_get_current(chgnum, &d)))
-		ccprintf("%5d (%4d - %5d, %3d)\n", d, info->current_min,
+		ccprintf("\t%5d mA (%4d - %5d, %3d)\n", d, info->current_min,
 			 info->current_max, info->current_step);
 
 	/* input current limit */
-	print_item_name("I_in:");
-	if (check_print_error(charger_get_input_current(chgnum, &d)))
-		ccprintf("%5d (%4d - %5d, %3d)\n", d, info->input_current_min,
-			 info->input_current_max, info->input_current_step);
+	print_item_name("input_current:");
+	if (check_print_error(charger_get_input_current_limit(chgnum, &d)))
+		ccprintf("\t%5d mA (%4d - %5d, %3d)\n", d,
+			 info->input_current_min, info->input_current_max,
+			 info->input_current_step);
+}
 
-	/* dptf current limit */
-	print_item_name("I_dptf:");
-	if (dptf_limit_ma >= 0)
-		ccprintf("%5d\n", dptf_limit_ma);
-	else
-		ccputs("disabled\n");
+void print_charger_prochot(int chgnum)
+{
+	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count()))
+		return;
+
+	if (chg_chips[chgnum].drv->dump_prochot)
+		chg_chips[chgnum].drv->dump_prochot(chgnum);
 }
 
-static int command_charger(int argc, char **argv)
+static int command_charger(int argc, const char **argv)
 {
 	int d;
 	char *e;
@@ -196,51 +214,74 @@ static int command_charger(int argc, char **argv)
 		return EC_SUCCESS;
 	}
 
-	idx_provided = isdigit(argv[1][0]);
-	if (idx_provided)
+	idx_provided = isdigit((unsigned char)argv[1][0]);
+	if (idx_provided) {
 		chgnum = atoi(argv[1]);
-	else
+		if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count()))
+			return EC_ERROR_PARAM1;
+	} else {
 		chgnum = 0;
+	}
 
 	if ((argc == 2) && idx_provided) {
 		print_charger_debug(chgnum);
 		return EC_SUCCESS;
 	}
 
-	if (strcasecmp(argv[1+idx_provided], "input") == 0) {
-		d = strtoi(argv[2+idx_provided], &e, 0);
+	if (strcasecmp(argv[1 + idx_provided], "input") == 0) {
+		d = strtoi(argv[2 + idx_provided], &e, 0);
 		if (*e)
-			return EC_ERROR_PARAM2+idx_provided;
-		return charger_set_input_current(chgnum, d);
-	} else if (strcasecmp(argv[1+idx_provided], "current") == 0) {
-		d = strtoi(argv[2+idx_provided], &e, 0);
+			return EC_ERROR_PARAM2 + idx_provided;
+		return charger_set_input_current_limit(chgnum, d);
+	} else if (IS_ENABLED(CONFIG_BATTERY) &&
+		   strcasecmp(argv[1 + idx_provided], "current") == 0) {
+		d = strtoi(argv[2 + idx_provided], &e, 0);
 		if (*e)
-			return EC_ERROR_PARAM2+idx_provided;
+			return EC_ERROR_PARAM2 + idx_provided;
 		chgstate_set_manual_current(d);
 		return charger_set_current(chgnum, d);
-	} else if (strcasecmp(argv[1+idx_provided], "voltage") == 0) {
-		d = strtoi(argv[2+idx_provided], &e, 0);
+	} else if (IS_ENABLED(CONFIG_BATTERY) &&
+		   strcasecmp(argv[1 + idx_provided], "voltage") == 0) {
+		d = strtoi(argv[2 + idx_provided], &e, 0);
 		if (*e)
-			return EC_ERROR_PARAM2+idx_provided;
+			return EC_ERROR_PARAM2 + idx_provided;
 		chgstate_set_manual_voltage(d);
 		return charger_set_voltage(chgnum, d);
-	} else if (strcasecmp(argv[1+idx_provided], "dptf") == 0) {
-		d = strtoi(argv[2+idx_provided], &e, 0);
+	} else if (strcasecmp(argv[1 + idx_provided], "dptf") == 0) {
+		d = strtoi(argv[2 + idx_provided], &e, 0);
 		if (*e)
-			return EC_ERROR_PARAM2+idx_provided;
+			return EC_ERROR_PARAM2 + idx_provided;
 		dptf_limit_ma = d;
 		return EC_SUCCESS;
+	} else if (strcasecmp(argv[1 + idx_provided], "dump") == 0) {
+		if (!IS_ENABLED(CONFIG_CMD_CHARGER_DUMP) ||
+		    !chg_chips[chgnum].drv->dump_registers) {
+			ccprintf("dump not supported\n");
+			return EC_ERROR_PARAM1 + idx_provided;
+		}
+		ccprintf("Dump %s registers\n",
+			 chg_chips[chgnum].drv->get_info(chgnum)->name);
+		chg_chips[chgnum].drv->dump_registers(chgnum);
+		return EC_SUCCESS;
 	} else {
-		return EC_ERROR_PARAM1+idx_provided;
+		return EC_ERROR_PARAM1 + idx_provided;
 	}
 }
 
 DECLARE_CONSOLE_COMMAND(charger, command_charger,
-			"[chgnum] [input | current | voltage | dptf] [newval]",
-			"Get or set charger param(s)");
+			"[chgnum] [input | current | voltage | dptf] [newval]"
+#ifdef CONFIG_CMD_CHARGER_DUMP
+			"\n\t[chgnum] dump"
+#endif
+			,
+			"Get or set charger param(s)"
+#ifdef CONFIG_CMD_CHARGER_DUMP
+			". Dump registers."
+#endif
+);
 
 /* Driver wrapper functions */
-
+#ifndef CONFIG_CHARGER_INIT_CUSTOM
 static void charger_chips_init(void)
 {
 	int chip;
@@ -250,109 +291,101 @@ static void charger_chips_init(void)
 			chg_chips[chip].drv->init(chip);
 	}
 }
-DECLARE_HOOK(HOOK_INIT, charger_chips_init, HOOK_PRIO_INIT_I2C + 1);
+DECLARE_HOOK(HOOK_INIT, charger_chips_init, HOOK_PRIO_POST_I2C);
+#endif
 
 enum ec_error_list charger_post_init(void)
 {
 	int chgnum = 0;
-	int rv = EC_ERROR_UNIMPLEMENTED;
 
-	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
+	if (chgnum >= board_get_charger_chip_count()) {
 		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
 		return EC_ERROR_INVAL;
 	}
 
-	if (chg_chips[chgnum].drv->post_init)
-		rv = chg_chips[chgnum].drv->post_init(chgnum);
+	if (!chg_chips[chgnum].drv->post_init)
+		return EC_ERROR_UNIMPLEMENTED;
 
-	return rv;
+	return chg_chips[chgnum].drv->post_init(chgnum);
 }
 
 const struct charger_info *charger_get_info(void)
 {
 	int chgnum = 0;
-	const struct charger_info *ret = NULL;
 
-	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
+	if (chgnum >= board_get_charger_chip_count()) {
 		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
 		return NULL;
 	}
 
-	if (chg_chips[chgnum].drv->get_info)
-		ret = chg_chips[chgnum].drv->get_info(chgnum);
+	if (!chg_chips[chgnum].drv->get_info)
+		return NULL;
 
-	return ret;
+	return chg_chips[chgnum].drv->get_info(chgnum);
 }
 
 enum ec_error_list charger_get_status(int *status)
 {
 	int chgnum = 0;
-	int rv = EC_ERROR_UNIMPLEMENTED;
 
-	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
+	if (chgnum >= board_get_charger_chip_count()) {
 		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
 		return EC_ERROR_INVAL;
 	}
 
-	if (chg_chips[chgnum].drv->get_status)
-		rv = chg_chips[chgnum].drv->get_status(chgnum, status);
+	if (!chg_chips[chgnum].drv->get_status)
+		return EC_ERROR_UNIMPLEMENTED;
 
-	return rv;
+	return chg_chips[chgnum].drv->get_status(chgnum, status);
 }
 
 enum ec_error_list charger_set_mode(int mode)
 {
 	int chgnum = 0;
-	int rv = EC_ERROR_UNIMPLEMENTED;
 
-	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
+	if (chgnum >= board_get_charger_chip_count()) {
 		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
 		return EC_ERROR_INVAL;
 	}
 
-	if (chg_chips[chgnum].drv->set_mode)
-		rv = chg_chips[chgnum].drv->set_mode(chgnum, mode);
+	if (!chg_chips[chgnum].drv->set_mode)
+		return EC_ERROR_UNIMPLEMENTED;
 
-	return rv;
+	return chg_chips[chgnum].drv->set_mode(chgnum, mode);
 }
 
 enum ec_error_list charger_enable_otg_power(int chgnum, int enabled)
 {
-	int rv = EC_ERROR_UNIMPLEMENTED;
-
 	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
 		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
 		return EC_ERROR_INVAL;
 	}
 
-	if (chg_chips[chgnum].drv->enable_otg_power)
-		rv = chg_chips[chgnum].drv->enable_otg_power(chgnum, enabled);
+	if (!chg_chips[chgnum].drv->enable_otg_power)
+		return EC_ERROR_UNIMPLEMENTED;
 
-	return rv;
+	return chg_chips[chgnum].drv->enable_otg_power(chgnum, enabled);
 }
 
 enum ec_error_list charger_set_otg_current_voltage(int chgnum,
 						   int output_current,
 						   int output_voltage)
 {
-	int rv = EC_ERROR_UNIMPLEMENTED;
-
 	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
 		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
 		return EC_ERROR_INVAL;
 	}
 
-	if (chg_chips[chgnum].drv->set_otg_current_voltage)
-		rv = chg_chips[chgnum].drv->set_otg_current_voltage(chgnum,
-						output_current, output_voltage);
+	if (!chg_chips[chgnum].drv->set_otg_current_voltage)
+		return EC_ERROR_UNIMPLEMENTED;
 
-	return rv;
+	return chg_chips[chgnum].drv->set_otg_current_voltage(
+		chgnum, output_current, output_voltage);
 }
 
 int charger_is_sourcing_otg_power(int port)
 {
 	int chgnum = 0;
-	int rv = 0;
 
 	if (IS_ENABLED(CONFIG_OCPC))
 		chgnum = port;
@@ -362,16 +395,31 @@ int charger_is_sourcing_otg_power(int port)
 		return 0;
 	}
 
-	if (chg_chips[chgnum].drv->is_sourcing_otg_power)
-		rv = chg_chips[chgnum].drv->is_sourcing_otg_power(chgnum, port);
+	if (!chg_chips[chgnum].drv->is_sourcing_otg_power)
+		return 0;
 
-	return rv;
+	return chg_chips[chgnum].drv->is_sourcing_otg_power(chgnum, port);
 }
 
-enum ec_error_list charger_get_current(int chgnum, int *current)
+enum ec_error_list charger_get_actual_current(int chgnum, int *current)
 {
-	int rv = EC_ERROR_UNIMPLEMENTED;
+	/* Note: chgnum may be -1 if no active port is selected */
+	if (chgnum < 0)
+		return EC_ERROR_INVAL;
+
+	if (chgnum >= board_get_charger_chip_count()) {
+		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
+		return EC_ERROR_INVAL;
+	}
+
+	if (!chg_chips[chgnum].drv->get_actual_current)
+		return EC_ERROR_UNIMPLEMENTED;
+
+	return chg_chips[chgnum].drv->get_actual_current(chgnum, current);
+}
 
+enum ec_error_list charger_get_current(int chgnum, int *current)
+{
 	/* Note: chgnum may be -1 if no active port is selected */
 	if (chgnum < 0)
 		return EC_ERROR_INVAL;
@@ -381,31 +429,43 @@ enum ec_error_list charger_get_current(int chgnum, int *current)
 		return EC_ERROR_INVAL;
 	}
 
-	if (chg_chips[chgnum].drv->get_current)
-		rv = chg_chips[chgnum].drv->get_current(chgnum, current);
+	if (!chg_chips[chgnum].drv->get_current)
+		return EC_ERROR_UNIMPLEMENTED;
 
-	return rv;
+	return chg_chips[chgnum].drv->get_current(chgnum, current);
 }
 
 enum ec_error_list charger_set_current(int chgnum, int current)
 {
-	int rv = EC_ERROR_UNIMPLEMENTED;
-
 	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
 		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
 		return EC_ERROR_INVAL;
 	}
 
-	if (chg_chips[chgnum].drv->set_current)
-		rv = chg_chips[chgnum].drv->set_current(chgnum, current);
+	if (!chg_chips[chgnum].drv->set_current)
+		return EC_ERROR_UNIMPLEMENTED;
 
-	return rv;
+	return chg_chips[chgnum].drv->set_current(chgnum, current);
 }
 
-enum ec_error_list charger_get_voltage(int chgnum, int *voltage)
+enum ec_error_list charger_get_actual_voltage(int chgnum, int *voltage)
 {
-	int rv = EC_ERROR_UNIMPLEMENTED;
+	if (chgnum < 0)
+		return EC_ERROR_INVAL;
+
+	if (chgnum >= board_get_charger_chip_count()) {
+		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
+		return EC_ERROR_INVAL;
+	}
+
+	if (!chg_chips[chgnum].drv->get_actual_voltage)
+		return EC_ERROR_UNIMPLEMENTED;
 
+	return chg_chips[chgnum].drv->get_actual_voltage(chgnum, voltage);
+}
+
+enum ec_error_list charger_get_voltage(int chgnum, int *voltage)
+{
 	if (chgnum < 0)
 		return EC_ERROR_INVAL;
 
@@ -414,25 +474,23 @@ enum ec_error_list charger_get_voltage(int chgnum, int *voltage)
 		return EC_ERROR_INVAL;
 	}
 
-	if (chg_chips[chgnum].drv->get_voltage)
-		rv = chg_chips[chgnum].drv->get_voltage(chgnum, voltage);
+	if (!chg_chips[chgnum].drv->get_voltage)
+		return EC_ERROR_UNIMPLEMENTED;
 
-	return rv;
+	return chg_chips[chgnum].drv->get_voltage(chgnum, voltage);
 }
 
 enum ec_error_list charger_set_voltage(int chgnum, int voltage)
 {
-	int rv = EC_ERROR_UNIMPLEMENTED;
-
 	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
 		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
 		return EC_ERROR_INVAL;
 	}
 
-	if (chg_chips[chgnum].drv->set_voltage)
-		rv = chg_chips[chgnum].drv->set_voltage(chgnum, voltage);
+	if (!chg_chips[chgnum].drv->set_voltage)
+		return EC_ERROR_UNIMPLEMENTED;
 
-	return rv;
+	return chg_chips[chgnum].drv->set_voltage(chgnum, voltage);
 }
 
 enum ec_error_list charger_discharge_on_ac(int enable)
@@ -440,6 +498,9 @@ enum ec_error_list charger_discharge_on_ac(int enable)
 	int chgnum;
 	int rv = EC_ERROR_UNIMPLEMENTED;
 
+	if (IS_ENABLED(CONFIG_CHARGER_DISCHARGE_ON_AC_CUSTOM))
+		return board_discharge_on_ac(enable);
+
 	/*
 	 * When discharge on AC is selected, cycle through all chargers to
 	 * enable or disable this feature.
@@ -453,10 +514,18 @@ enum ec_error_list charger_discharge_on_ac(int enable)
 	return rv;
 }
 
-enum ec_error_list charger_get_vbus_voltage(int port, int *voltage)
+enum ec_error_list charger_enable_bypass_mode(int chgnum, bool enable)
+{
+	ASSERT(chgnum >= 0 && chgnum < board_get_charger_chip_count());
+
+	if (!chg_chips[chgnum].drv->enable_bypass_mode)
+		return EC_ERROR_UNIMPLEMENTED;
+	return chg_chips[chgnum].drv->enable_bypass_mode(chgnum, enable);
+}
+
+static int charger_get_valid_chgnum(int port)
 {
 	int chgnum = 0;
-	int rv = 0;
 
 	/* Note: Assumes USBPD port == chgnum on multi-charger systems */
 	if (!IS_ENABLED(CONFIG_CHARGER_SINGLE_CHIP))
@@ -464,36 +533,78 @@ enum ec_error_list charger_get_vbus_voltage(int port, int *voltage)
 
 	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
 		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
-		return 0;
+		return -1;
 	}
 
-	if (chg_chips[chgnum].drv->get_vbus_voltage)
-		rv = chg_chips[chgnum].drv->get_vbus_voltage(chgnum, port,
-							     voltage);
+	return chgnum;
+}
 
-	return rv;
+enum ec_error_list charger_get_vbus_voltage(int port, int *voltage)
+{
+	int chgnum = charger_get_valid_chgnum(port);
+
+	if (chgnum < 0)
+		return EC_ERROR_INVAL;
+
+	if (!chg_chips[chgnum].drv->get_vbus_voltage)
+		return EC_ERROR_UNIMPLEMENTED;
+
+	return chg_chips[chgnum].drv->get_vbus_voltage(chgnum, port, voltage);
 }
 
-enum ec_error_list charger_set_input_current(int chgnum, int input_current)
+enum ec_error_list charger_get_vsys_voltage(int port, int *voltage)
 {
-	int rv = EC_ERROR_UNIMPLEMENTED;
+	int chgnum = charger_get_valid_chgnum(port);
 
-	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
+	if (chgnum < 0)
+		return EC_ERROR_INVAL;
+
+	if (!chg_chips[chgnum].drv->get_vsys_voltage)
+		return EC_ERROR_UNIMPLEMENTED;
+
+	return chg_chips[chgnum].drv->get_vsys_voltage(chgnum, port, voltage);
+}
+
+enum ec_error_list charger_set_input_current_limit(int chgnum,
+						   int input_current)
+{
+	/* Note: may be called with CHARGE_PORT_NONE regularly */
+	if (chgnum < 0)
+		return EC_ERROR_INVAL;
+
+	if (chgnum >= board_get_charger_chip_count()) {
 		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
 		return EC_ERROR_INVAL;
 	}
 
-	if (chg_chips[chgnum].drv->set_input_current)
-		rv = chg_chips[chgnum].drv->set_input_current(chgnum,
+	if (!chg_chips[chgnum].drv->set_input_current_limit)
+		return EC_ERROR_UNIMPLEMENTED;
+
+	return chg_chips[chgnum].drv->set_input_current_limit(chgnum,
 							      input_current);
+}
 
-	return rv;
+enum ec_error_list charger_get_input_current_limit(int chgnum,
+						   int *input_current)
+{
+	/* Note: may be called with CHARGE_PORT_NONE regularly */
+	if (chgnum < 0)
+		return EC_ERROR_INVAL;
+
+	if (chgnum >= board_get_charger_chip_count()) {
+		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
+		return EC_ERROR_INVAL;
+	}
+
+	if (!chg_chips[chgnum].drv->get_input_current_limit)
+		return EC_ERROR_UNIMPLEMENTED;
+
+	return chg_chips[chgnum].drv->get_input_current_limit(chgnum,
+							      input_current);
 }
 
 enum ec_error_list charger_get_input_current(int chgnum, int *input_current)
 {
-	int rv = EC_ERROR_UNIMPLEMENTED;
-
 	if (chgnum < 0)
 		return EC_ERROR_INVAL;
 
@@ -502,89 +613,110 @@ enum ec_error_list charger_get_input_current(int chgnum, int *input_current)
 		return EC_ERROR_INVAL;
 	}
 
-	if (chg_chips[chgnum].drv->get_input_current)
-		rv = chg_chips[chgnum].drv->get_input_current(chgnum,
-							      input_current);
+	if (!chg_chips[chgnum].drv->get_input_current)
+		return EC_ERROR_UNIMPLEMENTED;
 
-	return rv;
+	return chg_chips[chgnum].drv->get_input_current(chgnum, input_current);
 }
 
 enum ec_error_list charger_manufacturer_id(int *id)
 {
 	int chgnum = 0;
-	int rv = EC_ERROR_UNIMPLEMENTED;
 
-	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
+	if (chgnum >= board_get_charger_chip_count()) {
 		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
 		return EC_ERROR_INVAL;
 	}
 
-	if (chg_chips[chgnum].drv->manufacturer_id)
-		rv = chg_chips[chgnum].drv->manufacturer_id(chgnum, id);
+	if (!chg_chips[chgnum].drv->manufacturer_id)
+		return EC_ERROR_UNIMPLEMENTED;
 
-	return rv;
+	return chg_chips[chgnum].drv->manufacturer_id(chgnum, id);
 }
 
 enum ec_error_list charger_device_id(int *id)
 {
 	int chgnum = 0;
-	int rv = EC_ERROR_UNIMPLEMENTED;
 
-	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
+	if (chgnum >= board_get_charger_chip_count()) {
 		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
 		return EC_ERROR_INVAL;
 	}
 
-	if (chg_chips[chgnum].drv->device_id)
-		rv = chg_chips[chgnum].drv->device_id(chgnum, id);
+	if (!chg_chips[chgnum].drv->device_id)
+		return EC_ERROR_UNIMPLEMENTED;
 
-	return rv;
+	return chg_chips[chgnum].drv->device_id(chgnum, id);
 }
 
-enum ec_error_list charger_get_option(int *option)
+enum ec_error_list charger_set_frequency(int freq_khz)
 {
 	int chgnum = 0;
-	int rv = EC_ERROR_UNIMPLEMENTED;
 
-	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
+	if (chgnum >= board_get_charger_chip_count()) {
 		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
 		return EC_ERROR_INVAL;
 	}
 
-	if (chg_chips[chgnum].drv->get_option)
-		rv = chg_chips[chgnum].drv->get_option(chgnum, option);
+	if (!chg_chips[chgnum].drv->set_frequency)
+		return EC_ERROR_UNIMPLEMENTED;
 
-	return rv;
+	return chg_chips[chgnum].drv->set_frequency(chgnum, freq_khz);
 }
 
-enum ec_error_list charger_set_option(int option)
+enum ec_error_list charger_get_option(int *option)
 {
 	int chgnum = 0;
-	int rv = EC_ERROR_UNIMPLEMENTED;
 
-	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
+	if (chgnum >= board_get_charger_chip_count()) {
 		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
 		return EC_ERROR_INVAL;
 	}
 
-	if (chg_chips[chgnum].drv->set_option)
-		rv = chg_chips[chgnum].drv->set_option(chgnum, option);
+	if (!chg_chips[chgnum].drv->get_option)
+		return EC_ERROR_UNIMPLEMENTED;
 
-	return rv;
+	return chg_chips[chgnum].drv->get_option(chgnum, option);
 }
 
-enum ec_error_list charger_set_hw_ramp(int enable)
+enum ec_error_list charger_set_option(int option)
 {
 	int chgnum = 0;
-	int rv = EC_ERROR_UNIMPLEMENTED;
 
-	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
+	if (chgnum >= board_get_charger_chip_count()) {
 		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
 		return EC_ERROR_INVAL;
 	}
 
-	if (chg_chips[chgnum].drv->set_hw_ramp)
-		rv = chg_chips[chgnum].drv->set_hw_ramp(chgnum, enable);
+	if (!chg_chips[chgnum].drv->set_option)
+		return EC_ERROR_UNIMPLEMENTED;
+
+	return chg_chips[chgnum].drv->set_option(chgnum, option);
+}
+
+enum ec_error_list charger_set_hw_ramp(int enable)
+{
+	int chgnum;
+	int rv = EC_ERROR_UNIMPLEMENTED;
+
+	for (chgnum = 0; chgnum < board_get_charger_chip_count(); chgnum++) {
+		/* Check if the chg chip supports set_hw_ramp. */
+		if (chg_chips[chgnum].drv->set_hw_ramp) {
+			if (enable) {
+				/* Check if this is the active chg chip. */
+				if (chgnum == charge_get_active_chg_chip())
+					rv = chg_chips[chgnum].drv->set_hw_ramp(
+						chgnum, 1);
+				/* This is not the active chg chip, disable
+				 * hw_ramp. */
+				else
+					rv = chg_chips[chgnum].drv->set_hw_ramp(
+						chgnum, 0);
+			} else
+				rv = chg_chips[chgnum].drv->set_hw_ramp(chgnum,
+									0);
+		}
+	}
 
 	return rv;
 }
@@ -593,71 +725,110 @@ enum ec_error_list charger_set_hw_ramp(int enable)
 int chg_ramp_is_stable(void)
 {
 	int chgnum = 0;
-	int rv = 0;
 
-	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
+	if (chgnum >= board_get_charger_chip_count()) {
 		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
 		return 0;
 	}
 
-	if (chg_chips[chgnum].drv->ramp_is_stable)
-		rv = chg_chips[chgnum].drv->ramp_is_stable(chgnum);
+	if (!chg_chips[chgnum].drv->ramp_is_stable)
+		return 0;
 
-	return rv;
+	return chg_chips[chgnum].drv->ramp_is_stable(chgnum);
 }
 
 int chg_ramp_is_detected(void)
 {
 	int chgnum = 0;
-	int rv = 0;
 
-	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
+	if (chgnum >= board_get_charger_chip_count()) {
 		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
 		return 0;
 	}
 
-	if (chg_chips[chgnum].drv->ramp_is_detected)
-		rv = chg_chips[chgnum].drv->ramp_is_detected(chgnum);
+	if (!chg_chips[chgnum].drv->ramp_is_detected)
+		return 0;
 
-	return rv;
+	return chg_chips[chgnum].drv->ramp_is_detected(chgnum);
 }
 
 int chg_ramp_get_current_limit(void)
 {
 	int chgnum = 0;
-	int rv = 0;
 
-	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
+	if (chgnum >= board_get_charger_chip_count()) {
 		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
 		return 0;
 	}
 
-	if (chg_chips[chgnum].drv->ramp_get_current_limit)
-		rv = chg_chips[chgnum].drv->ramp_get_current_limit(chgnum);
+	if (!chg_chips[chgnum].drv->ramp_get_current_limit)
+		return 0;
 
-	return rv;
+	return chg_chips[chgnum].drv->ramp_get_current_limit(chgnum);
 }
 #endif
 
-enum ec_error_list charger_set_vsys_compensation(int chgnum,
-						 struct ocpc_data *ocpc,
-						 int current_ma,
-						 int voltage_mv)
+test_mockable enum ec_error_list
+charger_set_vsys_compensation(int chgnum, struct ocpc_data *ocpc,
+			      int current_ma, int voltage_mv)
 {
 	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
 		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
 		return EC_ERROR_INVAL;
 	}
 
-	if (chg_chips[chgnum].drv->set_vsys_compensation)
-		return chg_chips[chgnum].drv->set_vsys_compensation(chgnum,
-								    ocpc,
-								    current_ma,
-								    voltage_mv);
-
 	/*
 	 * This shouldn't happen as this should only be called on chargers
 	 * that support this.
 	 */
+	if (!chg_chips[chgnum].drv->set_vsys_compensation)
+		return EC_ERROR_UNIMPLEMENTED;
+
+	return chg_chips[chgnum].drv->set_vsys_compensation(
+		chgnum, ocpc, current_ma, voltage_mv);
+}
+
+enum ec_error_list charger_is_icl_reached(int chgnum, bool *reached)
+{
+	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
+		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
+		return EC_ERROR_INVAL;
+	}
+
+	if (chg_chips[chgnum].drv->is_icl_reached)
+		return chg_chips[chgnum].drv->is_icl_reached(chgnum, reached);
+
+	return EC_ERROR_UNIMPLEMENTED;
+}
+
+enum ec_error_list charger_enable_linear_charge(int chgnum, bool enable)
+{
+	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
+		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
+		return EC_ERROR_INVAL;
+	}
+
+	if (chg_chips[chgnum].drv->enable_linear_charge)
+		return chg_chips[chgnum].drv->enable_linear_charge(chgnum,
+								   enable);
+
+	return EC_ERROR_UNIMPLEMENTED;
+}
+
+#ifdef CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON
+inline int charger_get_min_bat_pct_for_power_on(void)
+{
+	return CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON;
+}
+#endif
+
+enum ec_error_list charger_get_battery_cells(int chgnum, int *cells)
+{
+	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count()))
+		return EC_ERROR_INVAL;
+
+	if (chg_chips[chgnum].drv->get_battery_cells)
+		return chg_chips[chgnum].drv->get_battery_cells(chgnum, cells);
+
 	return EC_ERROR_UNIMPLEMENTED;
 }
diff --git a/common/charger_base.c b/common/charger_base.c
new file mode 100644
index 0000000000..c2f49dcf21
--- /dev/null
+++ b/common/charger_base.c
@@ -0,0 +1,687 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery charging task and state machine.
+ */
+
+#include "charge_state.h"
+#include "charger.h"
+#include "charger_base.h"
+#include "common.h"
+#include "console.h"
+#include "ec_ec_comm_client.h"
+#include "hooks.h"
+#include "string.h"
+#include "util.h"
+
+/* Console output macros */
+#define CPUTS(outstr) cputs(CC_CHARGER, outstr)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+
+/* Base has responded to one of our commands already. */
+static int base_responsive;
+static int charge_base;
+static int prev_charge_base;
+static int prev_current_base;
+static int prev_allow_charge_base;
+static int prev_current_lid;
+
+/*
+ * In debugging mode, with AC, input current to allocate to base. Negative
+ * value disables manual mode.
+ */
+static int manual_ac_current_base = -1;
+/*
+ * In debugging mode, when discharging, current to transfer from lid to base
+ * (negative to transfer from base to lid). Only valid when enabled is true.
+ */
+static int manual_noac_enabled;
+static int manual_noac_current_base;
+
+/*
+ * Parameters for dual-battery policy.
+ * TODO(b:71881017): This should be made configurable by AP in the future.
+ */
+struct dual_battery_policy {
+	/*** Policies when AC is not connected. ***/
+	/* Voltage to use when using OTG mode between lid and base (mV) */
+	uint16_t otg_voltage;
+	/* Maximum current to apply from base to lid (mA) */
+	uint16_t max_base_to_lid_current;
+	/*
+	 * Margin to apply between provided OTG output current and input current
+	 * limit, to make sure that input charger does not overcurrent output
+	 * charger. input_current = (1-margin) * output_current. (/128)
+	 */
+	uint8_t margin_otg_current;
+
+	/* Only do base to lid OTG when base battery above this value (%) */
+	uint8_t min_charge_base_otg;
+
+	/*
+	 * When base/lid battery percentage is below this value, do
+	 * battery-to-battery charging. (%)
+	 */
+	uint8_t max_charge_base_batt_to_batt;
+	uint8_t max_charge_lid_batt_to_batt;
+
+	/*** Policies when AC is connected. ***/
+	/* Minimum power to allocate to base (mW), includes some margin to allow
+	 * base to charge when critically low.
+	 */
+	uint16_t min_base_system_power;
+
+	/* Smoothing factor for lid power (/128) */
+	uint8_t lid_system_power_smooth;
+	/*
+	 * Smoothing factor for base/lid battery power, when the battery power
+	 * is decreasing only: we try to estimate the maximum power that the
+	 * battery is willing to take and always reset it when it draws more
+	 * than the estimate. (/128)
+	 */
+	uint8_t battery_power_smooth;
+
+	/*
+	 * Margin to add to requested base/lid battery power, to figure out how
+	 * much current to allocate. allocation = (1+margin) * request. (/128)
+	 */
+	uint8_t margin_base_battery_power;
+	uint8_t margin_lid_battery_power;
+
+	/* Maximum current to apply from lid to base (mA) */
+	uint16_t max_lid_to_base_current;
+};
+
+static const struct dual_battery_policy db_policy = {
+	.otg_voltage = 12000, /* mV */
+	.max_base_to_lid_current = 1800, /* mA, about 2000mA with margin. */
+	.margin_otg_current = 13, /* /128 = 10.1% */
+	.min_charge_base_otg = 5, /* % */
+	.max_charge_base_batt_to_batt = 4, /* % */
+	.max_charge_lid_batt_to_batt = 10, /* % */
+	.min_base_system_power = 1300, /* mW */
+	.lid_system_power_smooth = 32, /* 32/128 = 0.25 */
+	.battery_power_smooth = 1, /* 1/128 = 0.008 */
+	.margin_base_battery_power = 32, /* 32/128 = 0.25 */
+	.margin_lid_battery_power = 32, /* 32/128 = 0.25 */
+	.max_lid_to_base_current = 2000, /* mA */
+};
+
+/* Add at most "value" to power_var, subtracting from total_power budget. */
+#define CHG_ALLOCATE(power_var, total_power, value)       \
+	do {                                              \
+		int val_capped = MIN(value, total_power); \
+		(power_var) += val_capped;                \
+		(total_power) -= val_capped;              \
+	} while (0)
+
+/* Check if a base is connected */
+bool base_connected(void)
+{
+	return board_is_base_connected();
+}
+
+/**
+ * Setup current settings for base, and record previous values, if the base
+ * is responsive.
+ *
+ * @param current_base Current to be drawn by base (negative to provide power)
+ * @param allow_charge_base Whether base battery should be charged (only makes
+ *                          sense with positive current)
+ */
+static int set_base_current(int current_base, int allow_charge_base)
+{
+	/* "OTG" voltage from base to lid. */
+	const int otg_voltage = db_policy.otg_voltage;
+	int ret;
+
+	ret = ec_ec_client_base_charge_control(current_base, otg_voltage,
+					       allow_charge_base);
+	if (ret) {
+		/* Ignore errors until the base is responsive. */
+		if (base_responsive)
+			return ret;
+	} else {
+		base_responsive = 1;
+		prev_current_base = current_base;
+		prev_allow_charge_base = allow_charge_base;
+	}
+
+	return EC_RES_SUCCESS;
+}
+
+/**
+ * Setup current settings for lid and base, in a safe way.
+ *
+ * @param current_base Current to be drawn by base (negative to provide power)
+ * @param allow_charge_base Whether base battery should be charged (only makes
+ *                          sense with positive current)
+ * @param current_lid Current to be drawn by lid (negative to provide power)
+ * @param allow_charge_lid Whether lid battery should be charged
+ * @param is_full Whether the lid battery is full
+ */
+static void set_base_lid_current(int current_base, int allow_charge_base,
+				 int current_lid, int allow_charge_lid,
+				 bool is_full)
+{
+	/* "OTG" voltage from lid to base. */
+	const int otg_voltage = db_policy.otg_voltage;
+
+	int lid_first;
+	int ret;
+	int chgnum = 0;
+
+	/* TODO(b:71881017): This is still quite verbose during charging. */
+	if (prev_current_base != current_base ||
+	    prev_allow_charge_base != allow_charge_base ||
+	    prev_current_lid != current_lid) {
+		CPRINTS("Base/Lid: %d%s/%d%s mA", current_base,
+			allow_charge_base ? "+" : "", current_lid,
+			allow_charge_lid ? "+" : "");
+	}
+
+	/*
+	 * To decide whether to first control the lid or the base, we first
+	 * control the side that _reduces_ current that would be drawn, then
+	 * setup one that would start providing power, then increase current.
+	 */
+	if (current_lid >= 0 && current_lid < prev_current_lid)
+		lid_first = 1; /* Lid decreases current */
+	else if (current_base >= 0 && current_base < prev_current_base)
+		lid_first = 0; /* Base decreases current */
+	else if (current_lid < 0)
+		lid_first = 1; /* Lid provide power */
+	else
+		lid_first = 0; /* All other cases: control the base first */
+
+	if (!lid_first && base_connected()) {
+		ret = set_base_current(current_base, allow_charge_base);
+		if (ret)
+			return;
+	}
+
+	if (current_lid >= 0) {
+		ret = charge_set_output_current_limit(CHARGER_SOLO, 0, 0);
+		if (ret)
+			return;
+		ret = charger_set_input_current_limit(chgnum, current_lid);
+		if (ret)
+			return;
+		ret = charge_request(allow_charge_lid, is_full);
+	} else {
+		ret = charge_set_output_current_limit(
+			CHARGER_SOLO, -current_lid, otg_voltage);
+	}
+
+	if (ret)
+		return;
+
+	prev_current_lid = current_lid;
+
+	if (lid_first && base_connected()) {
+		ret = set_base_current(current_base, allow_charge_base);
+		if (ret)
+			return;
+	}
+
+	/*
+	 * Make sure cross-power is enabled (it might not be enabled right after
+	 * plugging the base, or when an adapter just got connected).
+	 */
+	if (base_connected() && current_base != 0)
+		board_enable_base_power(1);
+}
+
+/**
+ * Smooth power value, covering some edge cases.
+ * Compute s*curr+(1-s)*prev, where s is in 1/128 unit.
+ */
+static int smooth_value(int prev, int curr, int s)
+{
+	if (curr < 0)
+		curr = 0;
+	if (prev < 0)
+		return curr;
+
+	return prev + s * (curr - prev) / 128;
+}
+
+/**
+ * Add margin m to value. Compute (1+m)*value, where m is in 1/128 unit.
+ */
+static int add_margin(int value, int m)
+{
+	return value + m * value / 128;
+}
+
+void base_charge_allocate_input_current_limit(
+	const struct charge_state_data *curr, bool is_full, bool debugging)
+{
+	/*
+	 * All the power numbers are in mW.
+	 *
+	 * Since we work with current and voltage in mA and mV, multiplying them
+	 * gives numbers in uW, which are dangerously close to overflowing when
+	 * doing intermediate computations (60W * 100 overflows a 32-bit int,
+	 * for example). We therefore divide the product by 1000 and re-multiply
+	 * the power numbers by 1000 when converting them back to current.
+	 */
+	int total_power = 0;
+
+	static int prev_base_battery_power = -1;
+	int base_battery_power = 0;
+	int base_battery_power_max = 0;
+
+	static int prev_lid_system_power = -1;
+	int lid_system_power;
+
+	static int prev_lid_battery_power = -1;
+	int lid_battery_power = 0;
+	int lid_battery_power_max = 0;
+
+	int power_base = 0;
+	int power_lid = 0;
+
+	int current_base = 0;
+	int current_lid = 0;
+
+	int charge_lid = charge_get_percent();
+
+	const struct ec_response_battery_dynamic_info *const base_bd =
+		&battery_dynamic[BATT_IDX_BASE];
+	const struct batt_params *batt = &curr->batt;
+
+	if (!base_connected()) {
+		set_base_lid_current(0, 0, curr->desired_input_current, 1,
+				     is_full);
+		prev_base_battery_power = -1;
+		return;
+	}
+
+	/* Charging */
+	if (curr->desired_input_current > 0 && curr->input_voltage > 0)
+		total_power = curr->desired_input_current *
+			      curr->input_voltage / 1000;
+
+	/*
+	 * TODO(b:71723024): We should be able to replace this test by curr.ac,
+	 * but the value is currently wrong, especially during transitions.
+	 */
+	if (total_power <= 0) {
+		int base_critical =
+			charge_base >= 0 &&
+			charge_base < db_policy.max_charge_base_batt_to_batt;
+
+		/* Discharging */
+		prev_base_battery_power = -1;
+		prev_lid_system_power = -1;
+		prev_lid_battery_power = -1;
+
+		/* Manual control */
+		if (manual_noac_enabled) {
+			int lid_current, base_current;
+
+			if (manual_noac_current_base > 0) {
+				base_current = -manual_noac_current_base;
+				lid_current = add_margin(
+					manual_noac_current_base,
+					db_policy.margin_otg_current);
+			} else {
+				lid_current = manual_noac_current_base;
+				base_current = add_margin(
+					-manual_noac_current_base,
+					db_policy.margin_otg_current);
+			}
+
+			set_base_lid_current(base_current, 0, lid_current, 0,
+					     is_full);
+			return;
+		}
+
+		/*
+		 * System is off, cut power to the base. We'll reset the base
+		 * when system restarts, or when AC is plugged.
+		 */
+		if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
+			set_base_lid_current(0, 0, 0, 0, is_full);
+			if (base_responsive) {
+				/* Base still responsive, put it to sleep. */
+				CPRINTF("Hibernating base\n");
+				ec_ec_client_hibernate();
+				base_responsive = 0;
+				board_enable_base_power(0);
+			}
+			return;
+		}
+
+		/*
+		 * System is suspended, let the lid and base run on their
+		 * own power. However, if the base battery is critically low, we
+		 * still want to provide power to the base, to make sure it
+		 * stays alive to be able to wake the system on keyboard or
+		 * touchpad events.
+		 */
+		if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
+		    !base_critical) {
+			set_base_lid_current(0, 0, 0, 0, is_full);
+			return;
+		}
+
+		if (charge_base > db_policy.min_charge_base_otg) {
+			int lid_current = db_policy.max_base_to_lid_current;
+			int base_current = add_margin(
+				lid_current, db_policy.margin_otg_current);
+			/* Draw current from base to lid */
+			set_base_lid_current(
+				-base_current, 0, lid_current,
+				charge_lid <
+					db_policy.max_charge_lid_batt_to_batt,
+				is_full);
+		} else {
+			/*
+			 * Base battery is too low, apply power to it, and allow
+			 * it to charge if it is critically low.
+			 *
+			 * TODO(b:71881017): When suspended, this will make the
+			 * battery charge oscillate between 3 and 4 percent,
+			 * which might not be great for battery life. We need
+			 * some hysteresis.
+			 */
+			/*
+			 * TODO(b:71881017): Precompute (ideally, at build time)
+			 * the base_current, so we do not need to do a division
+			 * here.
+			 */
+			int base_current =
+				(db_policy.min_base_system_power * 1000) /
+				db_policy.otg_voltage;
+			int lid_current = add_margin(
+				base_current, db_policy.margin_otg_current);
+
+			set_base_lid_current(base_current, base_critical,
+					     -lid_current, 0, is_full);
+		}
+
+		return;
+	}
+
+	/* Manual control */
+	if (manual_ac_current_base >= 0) {
+		int current_base = manual_ac_current_base;
+		int current_lid =
+			curr->desired_input_current - manual_ac_current_base;
+
+		if (current_lid < 0) {
+			current_base = curr->desired_input_current;
+			current_lid = 0;
+		}
+
+		set_base_lid_current(current_base, 1, current_lid, 1, is_full);
+		return;
+	}
+
+	/* Estimate system power. */
+	lid_system_power = charger_get_system_power() / 1000;
+
+	/* Smooth system power, as it is very spiky */
+	lid_system_power = smooth_value(prev_lid_system_power, lid_system_power,
+					db_policy.lid_system_power_smooth);
+	prev_lid_system_power = lid_system_power;
+
+	/*
+	 * TODO(b:71881017): Smoothing the battery power isn't necessarily a
+	 * good idea: if the system takes up too much power, we may reduce the
+	 * estimate power too quickly, leading to oscillations when the system
+	 * power goes down. Instead, we should probably estimate the current
+	 * based on remaining capacity.
+	 */
+	/* Estimate lid battery power. */
+	if (!(batt->flags & (BATT_FLAG_BAD_VOLTAGE | BATT_FLAG_BAD_CURRENT)))
+		lid_battery_power = batt->current * batt->voltage / 1000;
+	if (lid_battery_power < prev_lid_battery_power)
+		lid_battery_power =
+			smooth_value(prev_lid_battery_power, lid_battery_power,
+				     db_policy.battery_power_smooth);
+	if (!(batt->flags &
+	      (BATT_FLAG_BAD_DESIRED_VOLTAGE | BATT_FLAG_BAD_DESIRED_CURRENT)))
+		lid_battery_power_max =
+			batt->desired_current * batt->desired_voltage / 1000;
+
+	lid_battery_power = MIN(lid_battery_power, lid_battery_power_max);
+
+	/* Estimate base battery power. */
+	if (!(base_bd->flags & EC_BATT_FLAG_INVALID_DATA)) {
+		base_battery_power = base_bd->actual_current *
+				     base_bd->actual_voltage / 1000;
+		base_battery_power_max = base_bd->desired_current *
+					 base_bd->desired_voltage / 1000;
+	}
+	if (base_battery_power < prev_base_battery_power)
+		base_battery_power = smooth_value(
+			prev_base_battery_power, base_battery_power,
+			db_policy.battery_power_smooth);
+	base_battery_power = MIN(base_battery_power, base_battery_power_max);
+
+	if (debugging) {
+		CPRINTF("%s:\n", __func__);
+		CPRINTF("total power: %d\n", total_power);
+		CPRINTF("base battery power: %d (%d)\n", base_battery_power,
+			base_battery_power_max);
+		CPRINTF("lid system power: %d\n", lid_system_power);
+		CPRINTF("lid battery power: %d\n", lid_battery_power);
+		CPRINTF("percent base/lid: %d%% %d%%\n", charge_base,
+			charge_lid);
+	}
+
+	prev_lid_battery_power = lid_battery_power;
+	prev_base_battery_power = base_battery_power;
+
+	if (total_power > 0) { /* Charging */
+		/* Allocate system power */
+		CHG_ALLOCATE(power_base, total_power,
+			     db_policy.min_base_system_power);
+		CHG_ALLOCATE(power_lid, total_power, lid_system_power);
+
+		/* Allocate lid, then base battery power */
+		lid_battery_power = add_margin(
+			lid_battery_power, db_policy.margin_lid_battery_power);
+		CHG_ALLOCATE(power_lid, total_power, lid_battery_power);
+
+		base_battery_power =
+			add_margin(base_battery_power,
+				   db_policy.margin_base_battery_power);
+		CHG_ALLOCATE(power_base, total_power, base_battery_power);
+
+		/* Give everything else to the lid. */
+		CHG_ALLOCATE(power_lid, total_power, total_power);
+		if (debugging)
+			CPRINTF("power: base %d mW / lid %d mW\n", power_base,
+				power_lid);
+
+		current_base = 1000 * power_base / curr->input_voltage;
+		current_lid = 1000 * power_lid / curr->input_voltage;
+
+		if (current_base > db_policy.max_lid_to_base_current) {
+			current_lid += (current_base -
+					db_policy.max_lid_to_base_current);
+			current_base = db_policy.max_lid_to_base_current;
+		}
+
+		if (debugging)
+			CPRINTF("current: base %d mA / lid %d mA\n",
+				current_base, current_lid);
+
+		set_base_lid_current(current_base, 1, current_lid, 1, is_full);
+	} else { /* Discharging */
+	}
+
+	if (debugging)
+		CPRINTF("====\n");
+}
+
+void base_update_battery_info(void)
+{
+	struct ec_response_battery_dynamic_info *const bd =
+		&battery_dynamic[BATT_IDX_BASE];
+
+	if (!base_connected()) {
+		const int invalid_flags = EC_BATT_FLAG_INVALID_DATA;
+		/* Invalidate static/dynamic information */
+		if (bd->flags != invalid_flags) {
+			bd->flags = invalid_flags;
+
+			host_set_single_event(EC_HOST_EVENT_BATTERY);
+			host_set_single_event(EC_HOST_EVENT_BATTERY_STATUS);
+		}
+		charge_base = -1;
+		base_responsive = 0;
+		prev_current_base = 0;
+		prev_allow_charge_base = 0;
+	} else if (base_responsive) {
+		int old_flags = bd->flags;
+		int flags_changed;
+		int old_full_capacity = bd->full_capacity;
+
+		ec_ec_client_base_get_dynamic_info();
+		flags_changed = (old_flags != bd->flags);
+		/* Fetch static information when flags change. */
+		if (flags_changed)
+			ec_ec_client_base_get_static_info();
+
+		battery_memmap_refresh(BATT_IDX_BASE);
+
+		/* Newly connected battery, or change in capacity. */
+		if (old_flags & EC_BATT_FLAG_INVALID_DATA ||
+		    ((old_flags & EC_BATT_FLAG_BATT_PRESENT) !=
+		     (bd->flags & EC_BATT_FLAG_BATT_PRESENT)) ||
+		    old_full_capacity != bd->full_capacity)
+			host_set_single_event(EC_HOST_EVENT_BATTERY);
+
+		if (flags_changed)
+			host_set_single_event(EC_HOST_EVENT_BATTERY_STATUS);
+
+		/* Update charge_base */
+		if (bd->flags & (BATT_FLAG_BAD_FULL_CAPACITY |
+				 BATT_FLAG_BAD_REMAINING_CAPACITY))
+			charge_base = -1;
+		else if (bd->full_capacity > 0)
+			charge_base = 100 * bd->remaining_capacity /
+				      bd->full_capacity;
+		else
+			charge_base = 0;
+	}
+}
+
+bool base_check_extpower(int ac, int prev_ac)
+{
+	bool zero_ac = false;
+
+	/*
+	 * When base is powering the system, make sure ac stays 0.
+	 * TODO(b:71723024): Fix extpower_is_present() in hardware instead.
+	 */
+	if (base_responsive && prev_current_base < 0) {
+		ac = 0;
+		zero_ac = true;
+	}
+
+	/* System is off: if AC gets connected, reset the base. */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF) && !prev_ac && ac)
+		board_base_reset();
+
+	return zero_ac;
+}
+
+static int command_chgdualdebug(int argc, const char **argv)
+{
+	int val;
+	char *e;
+
+	if (argc > 1) {
+		if (argv[1][0] == 'c') {
+			if (argc <= 2)
+				return EC_ERROR_PARAM_COUNT;
+
+			if (!strcasecmp(argv[2], "auto")) {
+				val = -1;
+			} else {
+				val = strtoi(argv[2], &e, 0);
+				if (*e || val < 0)
+					return EC_ERROR_PARAM2;
+			}
+
+			manual_ac_current_base = val;
+			charge_wakeup();
+		} else if (argv[1][0] == 'd') {
+			if (argc <= 2)
+				return EC_ERROR_PARAM_COUNT;
+
+			if (!strcasecmp(argv[2], "auto")) {
+				manual_noac_enabled = 0;
+			} else {
+				val = strtoi(argv[2], &e, 0);
+				if (*e)
+					return EC_ERROR_PARAM2;
+				manual_noac_current_base = val;
+				manual_noac_enabled = 1;
+			}
+			charge_wakeup();
+		} else {
+			return EC_ERROR_PARAM1;
+		}
+	} else {
+		ccprintf("Base/Lid: %d%s/%d mA\n", prev_current_base,
+			 prev_allow_charge_base ? "+" : "", prev_current_lid);
+	}
+
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(chgdualdebug, command_chgdualdebug,
+			"[charge (auto|<current>)|discharge (auto|<current>)]",
+			"Manually control dual-battery charging algorithm.");
+
+void charger_base_setup(void)
+{
+	base_responsive = 0;
+	charge_base = -1;
+	battery_dynamic[BATT_IDX_BASE].flags = EC_BATT_FLAG_INVALID_DATA;
+}
+
+bool charger_base_charge_changed(void)
+{
+	return charge_base != prev_charge_base;
+}
+
+void charger_base_charge_update(void)
+{
+	prev_charge_base = charge_base;
+}
+
+void charger_base_show_charge(void)
+{
+	CPRINTS("Base battery %d%%", charge_base);
+}
+
+bool charger_base_charge_near_full(void)
+{
+	if (charge_base > -1 && charge_base < CONFIG_BATT_HOST_FULL_FACTOR)
+		return false;
+
+	return true;
+}
+
+int charger_base_get_input_voltage(const struct charge_state_data *curr)
+{
+	return curr->input_voltage;
+}
+
+void charger_base_set_input_voltage(struct charge_state_data *curr,
+				    int input_voltage)
+{
+	curr->input_voltage = input_voltage;
+}
+
+/* Reset the base on S5->S0 transition. */
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_base_reset, HOOK_PRIO_DEFAULT);
diff --git a/common/charger_profile_override.c b/common/charger_profile_override.c
index 2b691b9a5a..00aaa2b5bd 100644
--- a/common/charger_profile_override.c
+++ b/common/charger_profile_override.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -20,17 +20,17 @@ static int test_vtg_mV = -1;
 
 static int fast_charging_allowed = 1;
 
-int charger_profile_override_common(struct charge_state_data *curr,
-			const struct fast_charge_params *fast_chg_params,
-			const struct fast_charge_profile **prev_chg_prof_info,
-			int batt_vtg_max)
+int charger_profile_override_common(
+	struct charge_state_data *curr,
+	const struct fast_charge_params *fast_chg_params,
+	const struct fast_charge_profile **prev_chg_prof_info, int batt_vtg_max)
 {
 	int i, voltage_range;
 	/* temp in 0.1 deg C */
 	int temp_c = curr->batt.temperature - 2731;
 	int temp_ranges = fast_chg_params->total_temp_ranges;
 	const struct fast_charge_profile *chg_profile_info =
-				fast_chg_params->chg_profile_info;
+		fast_chg_params->chg_profile_info;
 
 #ifdef CONFIG_CMD_CHARGER_PROFILE_OVERRIDE_TEST
 	if (fast_charge_test_on && test_vtg_mV != -1) {
@@ -78,9 +78,9 @@ int charger_profile_override_common(struct charge_state_data *curr,
 
 	if (!(curr->batt.flags & BATT_FLAG_BAD_VOLTAGE)) {
 		for (i = 0; i < CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES - 1;
-			i++) {
+		     i++) {
 			if (curr->batt.voltage <
-					fast_chg_params->voltage_mV[i]) {
+			    fast_chg_params->voltage_mV[i]) {
 				voltage_range = i;
 				break;
 			}
@@ -98,13 +98,13 @@ int charger_profile_override_common(struct charge_state_data *curr,
 	 * Okay, impose our custom will:
 	 */
 	curr->requested_current =
-			(*prev_chg_prof_info)->current_mA[voltage_range];
+		(*prev_chg_prof_info)->current_mA[voltage_range];
 	curr->requested_voltage = curr->requested_current ? batt_vtg_max : 0;
 
 #ifdef CONFIG_CMD_CHARGER_PROFILE_OVERRIDE_TEST
 	if (fast_charge_test_on)
 		ccprintf("Fast charge profile i=%dmA, v=%dmV\n",
-			curr->requested_current, curr->requested_voltage);
+			 curr->requested_current, curr->requested_voltage);
 #endif
 
 	return 0;
@@ -134,7 +134,7 @@ enum ec_status charger_profile_override_set_param(uint32_t param,
 }
 
 #ifdef CONFIG_CMD_CHARGER_PROFILE_OVERRIDE
-static int command_fastcharge(int argc, char **argv)
+static int command_fastcharge(int argc, const char **argv)
 {
 	if (argc > 1 && !parse_bool(argv[1], &fast_charging_allowed))
 		return EC_ERROR_PARAM1;
@@ -143,8 +143,7 @@ static int command_fastcharge(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(fastcharge, command_fastcharge,
-			"[on|off]",
+DECLARE_CONSOLE_COMMAND(fastcharge, command_fastcharge, "[on|off]",
 			"Get or set fast charging profile");
 #endif
 
@@ -153,7 +152,7 @@ DECLARE_CONSOLE_COMMAND(fastcharge, command_fastcharge,
  * fast charging profile is selected.
  */
 #ifdef CONFIG_CMD_CHARGER_PROFILE_OVERRIDE_TEST
-static int command_fastcharge_test(int argc, char **argv)
+static int command_fastcharge_test(int argc, const char **argv)
 {
 	char *e;
 	int test_on;
diff --git a/common/chargesplash.c b/common/chargesplash.c
new file mode 100644
index 0000000000..1c5187af76
--- /dev/null
+++ b/common/chargesplash.c
@@ -0,0 +1,261 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "extpower.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "lid_switch.h"
+#include "power_button.h"
+#include "timer.h"
+#include "util.h"
+
+#include <stdbool.h>
+#include <string.h>
+
+#define CPRINTS(format, args...) \
+	cprints(CC_USBCHARGE, "chargesplash: " format, ##args)
+
+/*
+ * Was this power on initiated to show a charge splash?
+ *
+ * - Set when powering on for an AC connect.
+ * - Unset when power button is pushed, or the chargesplash request is
+ *   cancelled due to AC disconnection.
+ */
+static bool power_on_for_chargesplash;
+
+/* True once the display has come up */
+static bool display_initialized;
+
+/*
+ * True if the chargesplash is locked out, and we must wait until no
+ * requests happen during the chargesplash period until the lockout can
+ * be cleared.
+ *
+ * A charger can be locked out if it's too flaky, causing the charging status
+ * to bounce between enabled/disabled too many times within a specified
+ * time period.
+ */
+static bool locked_out;
+
+/*
+ * A circular buffer of the most recent chargesplash request
+ * timestamps (stored as an integer value of seconds).
+ */
+static int request_log[CONFIG_CHARGESPLASH_MAX_REQUESTS_PER_PERIOD];
+BUILD_ASSERT(CONFIG_CHARGESPLASH_MAX_REQUESTS_PER_PERIOD >= 1,
+	     "There must be at least one request allowed per period");
+
+/*
+ * Return true if the timestamp is outside of the tracking period,
+ * false otherwise.
+ */
+static bool timestamp_is_expired(int timestamp, int now)
+{
+	if (!timestamp) {
+		/* The log entry hasn't been filled yet */
+		return true;
+	}
+
+	return (now - timestamp) >= CONFIG_CHARGESPLASH_PERIOD;
+}
+
+/*
+ * Returns true only if all timestamps have been expired, or we aren't
+ * locked out anyway.
+ */
+static bool lockout_can_be_cleared(int now)
+{
+	if (!locked_out)
+		return true;
+
+	for (int i = 0; i < ARRAY_SIZE(request_log); i++) {
+		if (!timestamp_is_expired(request_log[i], now)) {
+			return false;
+		}
+	}
+
+	return true;
+}
+
+/*
+ * Write the current time into the request log.  If the request should
+ * be permitted to cause a boot, return true.  Otherwise, if the
+ * chargesplash should be inhibited, return false.
+ */
+static bool log_request(void)
+{
+	static int log_ptr;
+	int now = get_time().val / SECOND;
+	bool inhibit_boot = false;
+
+	if (lockout_can_be_cleared(now)) {
+		locked_out = false;
+	} else {
+		inhibit_boot = true;
+	}
+
+	if (!timestamp_is_expired(request_log[log_ptr], now)) {
+		locked_out = true;
+		inhibit_boot = true;
+	}
+
+	request_log[log_ptr] = now;
+	log_ptr = (log_ptr + 1) % ARRAY_SIZE(request_log);
+	return !inhibit_boot;
+}
+
+/* Manually reset state (via host or UART cmd) */
+static void reset_state(void)
+{
+	power_on_for_chargesplash = false;
+	display_initialized = false;
+	locked_out = false;
+	memset(request_log, 0, sizeof(request_log));
+}
+
+static void request_chargesplash(void)
+{
+	if (!log_request()) {
+		CPRINTS("Locked out, request inhibited");
+		return;
+	}
+
+	CPRINTS("Power on for charge display");
+	power_on_for_chargesplash = true;
+	display_initialized = false;
+	chipset_power_on();
+}
+
+static void display_ready(void)
+{
+	/*
+	 * TODO(b/228370390): Consider asserting PROCHOT (on
+	 * some platforms) to slow down background boot.
+	 */
+
+	CPRINTS("Display initialized");
+	display_initialized = true;
+}
+
+static void handle_ac_change(void)
+{
+	if (extpower_is_present() && !power_on_for_chargesplash) {
+		if (!lid_is_open()) {
+			CPRINTS("Ignore AC connect as lid is closed");
+			return;
+		}
+
+		if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
+			request_chargesplash();
+		}
+	}
+}
+DECLARE_HOOK(HOOK_AC_CHANGE, handle_ac_change, HOOK_PRIO_LAST - 1);
+
+static void handle_power_button_change(void)
+{
+	if (power_button_is_pressed()) {
+		reset_state();
+	}
+}
+DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, handle_power_button_change,
+	     HOOK_PRIO_FIRST);
+
+static void handle_chipset_shutdown(void)
+{
+	power_on_for_chargesplash = false;
+	display_initialized = false;
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, handle_chipset_shutdown, HOOK_PRIO_DEFAULT);
+
+static int command_chargesplash(int argc, const char **argv)
+{
+	if (argc != 2) {
+		return EC_ERROR_PARAM_COUNT;
+	}
+
+	if (!strcasecmp(argv[1], "state")) {
+		ccprintf("requested = %d\n", power_on_for_chargesplash);
+		ccprintf("display_initialized = %d\n", display_initialized);
+		ccprintf("locked_out = %d\n", locked_out);
+
+		ccprintf("\nRequest log (raw data):\n");
+		for (int i = 0; i < ARRAY_SIZE(request_log); i++) {
+			ccprintf("  %d\n", request_log[i]);
+		}
+		return EC_SUCCESS;
+	}
+
+	if (!strcasecmp(argv[1], "request")) {
+		request_chargesplash();
+		return EC_SUCCESS;
+	}
+
+	if (!strcasecmp(argv[1], "reset")) {
+		reset_state();
+		return EC_SUCCESS;
+	}
+
+	if (!strcasecmp(argv[1], "lockout")) {
+		locked_out = true;
+		return EC_SUCCESS;
+	}
+
+	return EC_ERROR_PARAM1;
+}
+DECLARE_CONSOLE_COMMAND(chargesplash, command_chargesplash,
+			"[state|request|reset|lockout]",
+			"Charge splash controls");
+
+static enum ec_status chargesplash_host_cmd(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_chargesplash *params = args->params;
+	struct ec_response_chargesplash *response = args->response;
+
+	if (args->params_size < sizeof(*params)) {
+		return EC_RES_INVALID_PARAM;
+	}
+
+	if (args->response_max < sizeof(*response)) {
+		return EC_RES_INVALID_RESPONSE;
+	}
+
+	switch (params->cmd) {
+	case EC_CHARGESPLASH_GET_STATE:
+		/* No action to do */
+		break;
+	case EC_CHARGESPLASH_DISPLAY_READY:
+		if (power_on_for_chargesplash) {
+			display_ready();
+		}
+		break;
+	case EC_CHARGESPLASH_REQUEST:
+		request_chargesplash();
+		break;
+	case EC_CHARGESPLASH_RESET:
+		reset_state();
+		break;
+	case EC_CHARGESPLASH_LOCKOUT:
+		locked_out = true;
+		break;
+	default:
+		return EC_RES_INVALID_PARAM;
+	}
+
+	/* All commands return the (possibly updated) state */
+	response->requested = power_on_for_chargesplash;
+	response->display_initialized = display_initialized;
+	response->locked_out = locked_out;
+
+	args->response_size = sizeof(*response);
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_CHARGESPLASH, chargesplash_host_cmd,
+		     EC_VER_MASK(0));
diff --git a/common/chipset.c b/common/chipset.c
index 209334add5..5a699bfe25 100644
--- a/common/chipset.c
+++ b/common/chipset.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,30 +18,27 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 /*****************************************************************************/
 /* Console commands */
 
 #ifdef CONFIG_CMD_POWER_AP
-static int command_apreset(int argc, char **argv)
+static int command_apreset(int argc, const char **argv)
 {
 	/* Force the chipset to reset */
 	ccprintf("Issuing AP reset...\n");
 	chipset_reset(CHIPSET_RESET_CONSOLE_CMD);
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(apreset, command_apreset,
-			NULL,
-			"Issue AP reset");
+DECLARE_CONSOLE_COMMAND(apreset, command_apreset, NULL, "Issue AP reset");
 
-static int command_apshutdown(int argc, char **argv)
+static int command_apshutdown(int argc, const char **argv)
 {
 	chipset_force_shutdown(CHIPSET_SHUTDOWN_CONSOLE_CMD);
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(apshutdown, command_apshutdown,
-			NULL,
+DECLARE_CONSOLE_COMMAND(apshutdown, command_apshutdown, NULL,
 			"Force AP shutdown");
 
 #endif
@@ -53,19 +50,16 @@ static enum ec_status host_command_apreset(struct host_cmd_handler_args *args)
 	chipset_reset(CHIPSET_RESET_HOST_CMD);
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_AP_RESET,
-		     host_command_apreset,
-		     EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_AP_RESET, host_command_apreset, EC_VER_MASK(0));
 
 #endif
 
 #ifdef CONFIG_CMD_AP_RESET_LOG
-static struct mutex reset_log_mutex;
+K_MUTEX_DEFINE(reset_log_mutex);
 static int next_reset_log __preserved_logs(next_reset_log);
 static uint32_t ap_resets_since_ec_boot;
 /* keep reset_logs size a power of 2 */
-static struct ap_reset_log_entry
-		reset_logs[4] __preserved_logs(reset_logs);
+static struct ap_reset_log_entry reset_logs[4] __preserved_logs(reset_logs);
 static int reset_log_checksum __preserved_logs(reset_log_checksum);
 
 /* Calculate reset log checksum */
@@ -113,11 +107,10 @@ get_ap_reset_stats(struct ap_reset_log_entry *reset_log_entries,
 
 	mutex_lock(&reset_log_mutex);
 	*resets_since_ec_boot = ap_resets_since_ec_boot;
-	for (i = 0;
-	     i != ARRAY_SIZE(reset_logs) && i != num_reset_log_entries;
+	for (i = 0; i != ARRAY_SIZE(reset_logs) && i != num_reset_log_entries;
 	     ++i) {
 		log_address = (next_reset_log + i) &
-			(ARRAY_SIZE(reset_logs) - 1);
+			      (ARRAY_SIZE(reset_logs) - 1);
 		reset_log_entries[i] = reset_logs[log_address];
 	}
 	mutex_unlock(&reset_log_mutex);
@@ -125,5 +118,37 @@ get_ap_reset_stats(struct ap_reset_log_entry *reset_log_entries,
 	return EC_SUCCESS;
 }
 
-#endif  /* !CONFIG_AP_RESET_LOG */
+enum chipset_shutdown_reason chipset_get_shutdown_reason(void)
+{
+	enum chipset_shutdown_reason reason = CHIPSET_RESET_UNKNOWN;
+
+	mutex_lock(&reset_log_mutex);
+	if (ap_resets_since_ec_boot != 0) {
+		int i = (next_reset_log == 0) ? ARRAY_SIZE(reset_logs) - 1 :
+						next_reset_log - 1;
+		reason = reset_logs[i].reset_cause;
+	}
+	mutex_unlock(&reset_log_mutex);
 
+	return reason;
+}
+
+#endif /* !CONFIG_AP_RESET_LOG */
+
+#ifdef TEST_BUILD
+uint32_t test_chipset_get_ap_resets_since_ec_boot(void)
+{
+	uint32_t count;
+
+	mutex_lock(&reset_log_mutex);
+	count = ap_resets_since_ec_boot;
+	mutex_unlock(&reset_log_mutex);
+
+	return count;
+}
+
+void test_chipset_corrupt_reset_log_checksum(void)
+{
+	reset_log_checksum = ~reset_log_checksum;
+}
+#endif /* TEST_BUILD */
diff --git a/common/clz.c b/common/clz.c
index b0b58e76a0..178c44d345 100644
--- a/common/clz.c
+++ b/common/clz.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/common/console.c b/common/console.c
index 8f42dffbf5..b045af1ddf 100644
--- a/common/console.c
+++ b/common/console.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,16 +19,18 @@
 
 #define MAX_ARGS_PER_COMMAND 10
 
-#define PROMPT "> "
-
 #ifdef CONFIG_EXPERIMENTAL_CONSOLE
 #define EC_SYN 0xEC
 #define EC_ACK 0xC0
-#endif /* defined(CONFIG_EXPERIMENTAL_CONSOLE) */
+#else /* defined(CONFIG_EXPERIMENTAL_CONSOLE) */
+
+#define PROMPT "> "
 
 /* ASCII control character; for example, CTRL('C') = ^C */
 #define CTRL(c) ((c) - '@')
 
+#endif /* defined(CONFIG_EXPERIMENTAL_CONSOLE) */
+
 #ifdef CONFIG_CONSOLE_HISTORY
 /* History buffers */
 static char history[CONFIG_CONSOLE_HISTORY][CONFIG_CONSOLE_INPUT_LINE_SIZE];
@@ -50,13 +52,14 @@ static int last_rx_was_cr;
 #ifndef CONFIG_EXPERIMENTAL_CONSOLE
 /* State of input escape code */
 static enum {
-	ESC_OUTSIDE,   /* Not in escape code */
-	ESC_START,     /* Got ESC */
-	ESC_BAD,       /* Bad escape sequence */
-	ESC_BRACKET,   /* Got ESC [ */
+	ESC_OUTSIDE, /* Not in escape code */
+	ESC_START, /* Got ESC */
+	ESC_BAD, /* Bad escape sequence */
+	ESC_BRACKET, /* Got ESC [ */
 	ESC_BRACKET_1, /* Got ESC [ 1 */
 	ESC_BRACKET_3, /* Got ESC [ 3 */
-	ESC_O,         /* Got ESC O */
+	ESC_BRACKET_4, /* Got ESC [ 4 */
+	ESC_O, /* Got ESC O */
 } esc_state;
 #endif /* !defined(CONFIG_EXPERIMENTAL_CONSOLE) */
 
@@ -82,7 +85,7 @@ enum extended_key_code {
  * @return EC_SUCCESS.  If more than MAX_ARGS_PER_COMMAND words are found,
  *	discards the excess and returns EC_ERROR_OVERFLOW.
  */
-static int split_words(char *input, int *argc, char **argv)
+static int split_words(char *input, int *argc, const char **argv)
 {
 	char *c;
 	int in_word = 0;
@@ -93,7 +96,7 @@ static int split_words(char *input, int *argc, char **argv)
 	for (c = input; in_line; c++) {
 		if (!*c)
 			in_line = 0;
-		if (isspace(*c) || !*c) {
+		if (isspace((unsigned char)*c) || !*c) {
 			if (in_word) {
 				/* Ending a word */
 				*c = '\0';
@@ -126,7 +129,7 @@ static int split_words(char *input, int *argc, char **argv)
  *
  * @return A pointer to the command structure, or NULL if no match found.
  */
-static const struct console_command *find_command(char *name)
+static const struct console_command *find_command(const char *name)
 {
 	const struct console_command *cmd, *match = NULL;
 	int match_length = strlen(name);
@@ -148,18 +151,10 @@ static const struct console_command *find_command(char *name)
 	return match;
 }
 
-
 static const char *const errmsgs[] = {
-	"OK",
-	"Unknown error",
-	"Unimplemented",
-	"Overflow",
-	"Timeout",
-	"Invalid argument",
-	"Busy",
-	"Access Denied",
-	"Not Powered",
-	"Not Calibrated",
+	"OK",	       "Unknown error",	   "Unimplemented", "Overflow",
+	"Timeout",     "Invalid argument", "Busy",	    "Access Denied",
+	"Not Powered", "Not Calibrated",
 };
 
 /**
@@ -172,7 +167,7 @@ static const char *const errmsgs[] = {
 static int handle_command(char *input)
 {
 	const struct console_command *cmd;
-	char *argv[MAX_ARGS_PER_COMMAND];
+	const char *argv[MAX_ARGS_PER_COMMAND];
 	int argc = 0;
 	int rv;
 #ifdef CONFIG_EXPERIMENTAL_CONSOLE
@@ -202,10 +197,10 @@ static int handle_command(char *input)
 	i = input[1] == '&' ? 2 : 1;
 
 	/* Next, there should be 4 hex digits: XXYY + '&' */
-	if (i+5 > input_len)
+	if (i + 5 > input_len)
 		goto command_has_error;
 	/* Replace the '&' with null so we can call strtoi(). */
-	input[i+4] = 0;
+	input[i + 4] = 0;
 	j = strtoi(input + i, &e, 16);
 	if (*e)
 		goto command_has_error;
@@ -215,10 +210,10 @@ static int handle_command(char *input)
 	i += 5;
 
 	/* Lastly, verify the CRC8 of the command. */
-	if (i+command_len > input_len)
+	if (i + command_len > input_len)
 		goto command_has_error;
-	if (packed_crc8 != crc8(&input[i], command_len)) {
-command_has_error:
+	if (packed_crc8 != cros_crc8(&input[i], command_len)) {
+	command_has_error:
 		/* Send back the error string. */
 		ccprintf("&&EE\n");
 		return EC_ERROR_UNKNOWN;
@@ -245,7 +240,7 @@ static int handle_command(char *input)
 		rv = EC_ERROR_ACCESS_DENIED;
 	else
 #endif
-	rv = cmd->handler(argc, argv);
+		rv = cmd->handler(argc, argv);
 	if (rv == EC_SUCCESS)
 		return rv;
 
@@ -273,8 +268,8 @@ static void console_init(void)
 	ccprintf("Enhanced Console is enabled (v1.0.0); type HELP for help.\n");
 #else
 	ccprintf("Console is enabled; type HELP for help.\n");
-#endif /* defined(CONFIG_EXPERIMENTAL_CONSOLE) */
 	ccputs(PROMPT);
+#endif /* defined(CONFIG_EXPERIMENTAL_CONSOLE) */
 }
 
 static int console_putc(int c)
@@ -369,7 +364,7 @@ static void save_history(void)
 static void handle_backspace(void)
 {
 	if (!input_pos)
-		return;  /* Already at beginning of line */
+		return; /* Already at beginning of line */
 
 	/* Move cursor back */
 	console_putc('\b');
@@ -377,8 +372,7 @@ static void handle_backspace(void)
 	/* Print and move anything following the cursor position */
 	if (input_pos != input_len) {
 		ccputs(input_buf + input_pos);
-		memmove(input_buf + input_pos - 1,
-			input_buf + input_pos,
+		memmove(input_buf + input_pos - 1, input_buf + input_pos,
 			input_len - input_pos + 1);
 	} else {
 		input_buf[input_len - 1] = '\0';
@@ -418,6 +412,9 @@ static int handle_esc(int c)
 		} else if (c == '3') {
 			esc_state = ESC_BRACKET_3;
 			return -1;
+		} else if (c == '4') {
+			esc_state = ESC_BRACKET_4;
+			return -1;
 		}
 
 		if (c == 'A')
@@ -445,12 +442,17 @@ static int handle_esc(int c)
 			return KEY_DEL;
 		break;
 
+	case ESC_BRACKET_4:
+		if (c == '~')
+			return KEY_END;
+		break;
+
 	default:
 		break;
 	}
 
 	/* Check if the escape code is done */
-	if (isalpha(c) || c == '~')
+	if (isalpha((unsigned char)c) || c == '~')
 		esc_state = ESC_OUTSIDE;
 	else
 		esc_state = ESC_BAD;
@@ -500,15 +502,28 @@ static void console_handle_char(int c)
 #ifndef CONFIG_EXPERIMENTAL_CONSOLE
 	case KEY_DEL:
 		if (input_pos == input_len)
-			break;  /* Already at end */
+			break; /* Already at end */
 
 		move_cursor_right();
 
 		/* Drop through to backspace handling */
+		__fallthrough;
 	case '\b':
 	case 0x7f:
 		handle_backspace();
 		break;
+
+	case CTRL('C'):
+		/* Terminate this line */
+		ccputs("^C\n");
+
+		/* Start new line, discarding any existing partial input. */
+		input_pos = input_len = 0;
+		input_buf[0] = '\0';
+
+		/* Reprint prompt */
+		ccputs(PROMPT);
+		break;
 #endif /* !defined(CONFIG_EXPERIMENTAL_CONSOLE) */
 
 	case '\n':
@@ -521,8 +536,8 @@ static void console_handle_char(int c)
 		/* Save command in history buffer */
 		if (input_len) {
 			save_history();
-			history_next = (history_next + 1) %
-				CONFIG_CONSOLE_HISTORY;
+			history_next =
+				(history_next + 1) % CONFIG_CONSOLE_HISTORY;
 			history_pos = history_next;
 		}
 #endif
@@ -610,7 +625,7 @@ static void console_handle_char(int c)
 
 	default:
 		/* Ignore non-printing characters */
-		if (!isprint(c))
+		if (!isprint((unsigned char)c))
 			break;
 
 #ifndef CONFIG_EXPERIMENTAL_CONSOLE
@@ -669,7 +684,7 @@ void console_task(void *u)
 			console_handle_char(c);
 		}
 
-		task_wait_event(-1);  /* Wait for more input */
+		task_wait_event(-1); /* Wait for more input */
 	}
 }
 
@@ -677,10 +692,10 @@ void console_task(void *u)
 /* Console commands */
 
 /* Command handler - prints help. */
-static int command_help(int argc, char **argv)
+static int command_help(int argc, const char **argv)
 {
 	const int ncmds = __cmds_end - __cmds;
-	const int cols = 5;			/* printing in five columns */
+	const int cols = 5; /* printing in five columns */
 	const int rows = (ncmds + cols - 1) / cols;
 	int i, j;
 
@@ -692,16 +707,15 @@ static int command_help(int argc, char **argv)
 #ifdef CONFIG_CONSOLE_COMMAND_FLAGS
 			ccputs("Command     Flags   Description\n");
 			for (i = 0; i < ncmds; i++) {
-				ccprintf(" %-14s %x %s\n",
-					 __cmds[i].name, __cmds[i].flags,
-					 __cmds[i].help);
+				ccprintf(" %-14s %x %s\n", __cmds[i].name,
+					 __cmds[i].flags, __cmds[i].help);
 				cflush();
 			}
 #else
 			ccputs("Known commands:\n");
 			for (i = 0; i < ncmds; i++) {
-				ccprintf("  %-15s%s\n",
-					 __cmds[i].name, __cmds[i].help);
+				ccprintf("  %-15s%s\n", __cmds[i].name,
+					 __cmds[i].help);
 				cflush();
 			}
 #endif
@@ -748,12 +762,11 @@ static int command_help(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_SAFE_CONSOLE_COMMAND(help, command_help,
-			     "[ list | <name> ]",
+DECLARE_SAFE_CONSOLE_COMMAND(help, command_help, "[ list | <name> ]",
 			     "Print command help");
 
 #ifdef CONFIG_CONSOLE_HISTORY
-static int command_history(int argc, char **argv)
+static int command_history(int argc, const char **argv)
 {
 	int i;
 
@@ -765,7 +778,6 @@ static int command_history(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_SAFE_CONSOLE_COMMAND(history, command_history,
-			     NULL,
+DECLARE_SAFE_CONSOLE_COMMAND(history, command_history, NULL,
 			     "Print console history");
 #endif
diff --git a/common/console_output.c b/common/console_output.c
index 23c208c61b..72e5c4daf1 100644
--- a/common/console_output.c
+++ b/common/console_output.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,6 +6,7 @@
 /* Console output module for Chrome EC */
 
 #include "console.h"
+#include "printf.h"
 #include "uart.h"
 #include "usb_console.h"
 #include "util.h"
@@ -27,16 +28,52 @@ static uint32_t channel_mask_saved = CC_DEFAULT;
  * might also become more important if we have >32 channels - for example, if
  * we decide to replace enum console_channel with enum module_id.
  */
-static const char * const channel_names[] = {
-	#define CONSOLE_CHANNEL(enumeration, string) string,
-	#include "console_channel.inc"
-	#undef CONSOLE_CHANNEL
+static const char *const channel_names[] = {
+#define CONSOLE_CHANNEL(enumeration, string) string,
+#include "console_channel.inc"
+#undef CONSOLE_CHANNEL
 };
 BUILD_ASSERT(ARRAY_SIZE(channel_names) == CC_CHANNEL_COUNT);
 /* ensure that we are not silently masking additional channels */
-BUILD_ASSERT(CC_CHANNEL_COUNT <= 8*sizeof(uint32_t));
+BUILD_ASSERT(CC_CHANNEL_COUNT <= 8 * sizeof(uint32_t));
+
+static int console_channel_name_to_index(const char *name)
+{
+	int i;
+
+	for (i = 0; i < CC_CHANNEL_COUNT; i++) {
+		if (!strncasecmp(name, channel_names[i], strlen(name)))
+			return i;
+	}
+
+	/* Not found */
+	return -1;
+}
+
+void console_channel_enable(const char *name)
+{
+	int index = console_channel_name_to_index(name);
+
+	if (index >= 0 && index != CC_COMMAND)
+		channel_mask |= CC_MASK(index);
+}
+void console_channel_disable(const char *name)
+{
+	int index = console_channel_name_to_index(name);
+
+	if (index >= 0 && index != CC_COMMAND)
+		channel_mask &= ~CC_MASK(index);
+}
+
+bool console_channel_is_disabled(enum console_channel channel)
+{
+	if (!(CC_MASK(channel) & channel_mask))
+		return true;
+	return false;
+}
 #endif /* CONFIG_CONSOLE_CHANNEL */
 
+#ifndef CONFIG_ZEPHYR
 /*****************************************************************************/
 /* Channel-based console output */
 
@@ -44,11 +81,9 @@ int cputs(enum console_channel channel, const char *outstr)
 {
 	int rv1, rv2;
 
-#ifdef CONFIG_CONSOLE_CHANNEL
 	/* Filter out inactive channels */
-	if (!(CC_MASK(channel) & channel_mask))
+	if (console_channel_is_disabled(channel))
 		return EC_SUCCESS;
-#endif
 
 	rv1 = usb_puts(outstr);
 	rv2 = uart_puts(outstr);
@@ -61,11 +96,9 @@ int cprintf(enum console_channel channel, const char *format, ...)
 	int rv1, rv2;
 	va_list args;
 
-#ifdef CONFIG_CONSOLE_CHANNEL
 	/* Filter out inactive channels */
-	if (!(CC_MASK(channel) & channel_mask))
+	if (console_channel_is_disabled(channel))
 		return EC_SUCCESS;
-#endif
 
 	usb_va_start(args, format);
 	rv1 = usb_vprintf(format, args);
@@ -82,14 +115,14 @@ int cprints(enum console_channel channel, const char *format, ...)
 {
 	int r, rv;
 	va_list args;
+	char ts_str[PRINTF_TIMESTAMP_BUF_SIZE];
 
-#ifdef CONFIG_CONSOLE_CHANNEL
 	/* Filter out inactive channels */
-	if (!(CC_MASK(channel) & channel_mask))
+	if (console_channel_is_disabled(channel))
 		return EC_SUCCESS;
-#endif
 
-	rv = cprintf(channel, "[%pT ", PRINTF_TIMESTAMP_NOW);
+	snprintf_timestamp_now(ts_str, sizeof(ts_str));
+	rv = cprintf(channel, "[%s ", ts_str);
 
 	va_start(args, format);
 	r = uart_vprintf(format, args);
@@ -106,6 +139,7 @@ int cprints(enum console_channel channel, const char *format, ...)
 	r = cputs(channel, "]\n");
 	return r ? r : rv;
 }
+#endif /* CONFIG_ZEPHYR */
 
 void cflush(void)
 {
@@ -117,7 +151,7 @@ void cflush(void)
 
 #ifdef CONFIG_CONSOLE_CHANNEL
 /* Set active channels */
-static int command_ch(int argc, char **argv)
+static int command_ch(int argc, const char **argv)
 {
 	int i;
 	char *e;
@@ -133,12 +167,24 @@ static int command_ch(int argc, char **argv)
 
 		} else {
 			/* Set the mask */
-			int m = strtoi(argv[1], &e, 0);
-			if (*e)
-				return EC_ERROR_PARAM1;
-
-			/* No disabling the command output channel */
-			channel_mask = m | CC_MASK(CC_COMMAND);
+			int index = console_channel_name_to_index(argv[1]);
+
+			if (index >= 0) {
+				if (console_channel_is_disabled(index)) {
+					console_channel_enable(argv[1]);
+					ccprintf("chan %s enabled\n", argv[1]);
+				} else {
+					console_channel_disable(argv[1]);
+					ccprintf("chan %s disabled\n", argv[1]);
+				}
+			} else {
+				int m = strtoi(argv[1], &e, 0);
+				if (*e) {
+					return EC_ERROR_PARAM1;
+				}
+				/* No disabling the command output channel */
+				channel_mask = m | CC_MASK(CC_COMMAND);
+			}
 
 			return EC_SUCCESS;
 		}
@@ -147,8 +193,7 @@ static int command_ch(int argc, char **argv)
 	/* Print the list of channels */
 	ccputs(" # Mask     E Channel\n");
 	for (i = 0; i < CC_CHANNEL_COUNT; i++) {
-		ccprintf("%2d %08x %c %s\n",
-			 i, CC_MASK(i),
+		ccprintf("%2d %08x %c %s\n", i, CC_MASK(i),
 			 (channel_mask & CC_MASK(i)) ? '*' : ' ',
 			 channel_names[i]);
 		cflush();
@@ -156,6 +201,6 @@ static int command_ch(int argc, char **argv)
 	return EC_SUCCESS;
 };
 DECLARE_SAFE_CONSOLE_COMMAND(chan, command_ch,
-			     "[ save | restore | <mask> ]",
+			     "[ save | restore | <mask> | <name> ]",
 			     "Save, restore, get or set console channel mask");
 #endif /* CONFIG_CONSOLE_CHANNEL */
diff --git a/common/crc.c b/common/crc.c
index 2db1ffc361..11c4936d51 100644
--- a/common/crc.c
+++ b/common/crc.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -56,11 +56,11 @@ static const uint32_t crc32_tab[] = {
 	0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d
 };
 
-static uint32_t crc32_hash(uint32_t crc, const void *buf, int size)
+static uint32_t _crc32_hash(uint32_t crc, const void *buf, int size)
 {
 	const uint8_t *p;
 
-	p = buf;
+	p = (const uint8_t *)buf;
 
 	while (size--) {
 		crc ^= *p++;
@@ -75,19 +75,24 @@ void crc32_ctx_init(uint32_t *crc)
 	*crc = CRC32_INITIAL;
 }
 
+void crc32_ctx_hash(uint32_t *crc, const void *buf, int size)
+{
+	*crc = _crc32_hash(*crc, buf, size);
+}
+
 void crc32_ctx_hash32(uint32_t *crc, uint32_t val)
 {
-	*crc = crc32_hash(*crc, &val, sizeof(val));
+	*crc = _crc32_hash(*crc, &val, sizeof(val));
 }
 
 void crc32_ctx_hash16(uint32_t *crc, uint16_t val)
 {
-	*crc = crc32_hash(*crc, &val, sizeof(val));
+	*crc = _crc32_hash(*crc, &val, sizeof(val));
 }
 
 void crc32_ctx_hash8(uint32_t *crc, uint8_t val)
 {
-	*crc = crc32_hash(*crc, &val, sizeof(val));
+	*crc = _crc32_hash(*crc, &val, sizeof(val));
 }
 
 uint32_t crc32_ctx_result(uint32_t *crc)
@@ -103,6 +108,11 @@ void crc32_init(void)
 	crc32_ctx_init(&crc_);
 }
 
+void crc32_hash(const void *buf, int size)
+{
+	crc32_ctx_hash(&crc_, buf, size);
+}
+
 void crc32_hash32(uint32_t val)
 {
 	crc32_ctx_hash32(&crc_, val);
@@ -117,3 +127,23 @@ uint32_t crc32_result(void)
 {
 	return crc32_ctx_result(&crc_);
 }
+
+uint16_t cros_crc16(const uint8_t *data, int len, uint16_t previous_crc)
+{
+	int i, j;
+	uint16_t crc_poly = 0x1021;
+	uint16_t crc16;
+
+	crc16 = previous_crc;
+	for (i = 0; i < len; i++) {
+		crc16 ^= (uint16_t)(data[i] << 8);
+		for (j = 0; j < 8; j++) {
+			if (crc16 & 0x8000)
+				crc16 = (crc16 << 1) ^ crc_poly;
+			else
+				crc16 = crc16 << 1;
+		}
+	}
+
+	return crc16;
+}
diff --git a/common/crc.cc b/common/crc.cc
new file mode 120000
index 0000000000..08c9c8c528
--- /dev/null
+++ b/common/crc.cc
@@ -0,0 +1 @@
+crc.c
\ No newline at end of file
diff --git a/common/crc8.c b/common/crc8.c
index 83ba31c5a4..5d8df8db52 100644
--- a/common/crc8.c
+++ b/common/crc8.c
@@ -1,18 +1,18 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 #include "common.h"
 #include "crc8.h"
 
-inline uint8_t crc8(const uint8_t *data, int len)
+inline uint8_t cros_crc8(const uint8_t *data, int len)
 {
-	return crc8_arg(data, len, 0);
+	return cros_crc8_arg(data, len, 0);
 }
 
-uint8_t crc8_arg(const uint8_t *data, int len, uint8_t previous_crc)
+uint8_t cros_crc8_arg(const uint8_t *data, int len, uint8_t previous_crc)
 {
-	unsigned crc = previous_crc << 8;
+	unsigned int crc = previous_crc << 8;
 	int i, j;
 
 	for (j = len; j; j--, data++) {
diff --git a/common/ctz.c b/common/ctz.c
index bb6f69624e..ad144225f0 100644
--- a/common/ctz.c
+++ b/common/ctz.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -20,8 +20,8 @@
 int __keep __ctzsi2(int x)
 {
 	static const uint8_t MulDeBruijnBitPos[32] = {
-		0, 1, 28, 2, 29, 14, 24, 3, 30, 22, 20, 15, 25, 17, 4, 8,
-		31, 27, 13, 23, 21, 19, 16, 7, 26, 12, 18, 6, 11, 5, 10, 9
+		0,  1,	28, 2,	29, 14, 24, 3, 30, 22, 20, 15, 25, 17, 4,  8,
+		31, 27, 13, 23, 21, 19, 16, 7, 26, 12, 18, 6,  11, 5,  10, 9
 	};
 	return MulDeBruijnBitPos[((uint32_t)((x & -x) * 0x077CB531U)) >> 27];
 }
diff --git a/common/device_event.c b/common/device_event.c
index 3b1fae79d0..b9e1bafc69 100644
--- a/common/device_event.c
+++ b/common/device_event.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,10 +15,10 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_EVENTS, outstr)
-#define CPRINTS(format, args...) cprints(CC_EVENTS, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_EVENTS, format, ##args)
 
-static uint32_t device_current_events;
-static uint32_t device_enabled_events;
+static atomic_t device_current_events;
+static atomic_t device_enabled_events;
 
 uint32_t device_get_current_events(void)
 {
@@ -27,7 +27,7 @@ uint32_t device_get_current_events(void)
 
 static uint32_t device_get_and_clear_events(void)
 {
-	return deprecated_atomic_read_clear(&device_current_events);
+	return atomic_clear(&device_current_events);
 }
 
 static uint32_t device_get_enabled_events(void)
@@ -40,10 +40,22 @@ void device_set_events(uint32_t mask)
 	/* Ignore events that are not enabled */
 	mask &= device_enabled_events;
 
-	if ((device_current_events & mask) != mask)
+	if (((uint32_t)device_current_events & mask) != mask) {
 		CPRINTS("device event set 0x%08x", mask);
+	} else {
+		/*
+		 * We are here because there is no flag change (1->1, 0->0).
+		 * For 0->0, we shouldn't notify the host because the flag is
+		 * disabled. For 1->1, it's most likely redundant but we still
+		 * need to notify the host in case the host didn't have a
+		 * chance to read the flags. Otherwise, the flag would never be
+		 * consumed because the host would never be notified.
+		 */
+		if (!mask)
+			return;
+	}
 
-	deprecated_atomic_or(&device_current_events, mask);
+	atomic_or(&device_current_events, mask);
 
 	/* Signal host that a device event is pending */
 	host_set_single_event(EC_HOST_EVENT_DEVICE);
@@ -52,10 +64,10 @@ void device_set_events(uint32_t mask)
 void device_clear_events(uint32_t mask)
 {
 	/* Only print if something's about to change */
-	if (device_current_events & mask)
+	if ((uint32_t)device_current_events & mask)
 		CPRINTS("device event clear 0x%08x", mask);
 
-	deprecated_atomic_clear_bits(&device_current_events, mask);
+	atomic_clear_bits(&device_current_events, mask);
 }
 
 static void device_set_enabled_events(uint32_t mask)
@@ -66,11 +78,16 @@ static void device_set_enabled_events(uint32_t mask)
 	device_enabled_events = mask;
 }
 
+void device_enable_event(enum ec_device_event event)
+{
+	atomic_or(&device_enabled_events, EC_DEVICE_EVENT_MASK(event));
+}
+
 /*****************************************************************************/
 /* Console commands */
 
 #ifdef CONFIG_CMD_DEVICE_EVENT
-static int command_device_event(int argc, char **argv)
+static int command_device_event(int argc, const char **argv)
 {
 	/* Handle sub-commands */
 	if (argc == 3) {
diff --git a/common/device_state.c b/common/device_state.c
index 0ba94d6115..1739a9beb2 100644
--- a/common/device_state.c
+++ b/common/device_state.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,7 +7,7 @@
 #include "device_state.h"
 #include "hooks.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 /**
  * Return text description for a state
@@ -17,8 +17,9 @@
  */
 static const char *state_desc(enum device_state state)
 {
-	return state == DEVICE_STATE_ON ? "on" :
-			state == DEVICE_STATE_OFF ? "off" : "unknown";
+	return state == DEVICE_STATE_ON	 ? "on" :
+	       state == DEVICE_STATE_OFF ? "off" :
+					   "unknown";
 }
 
 enum device_state device_get_state(enum device_type device)
@@ -65,7 +66,7 @@ static void check_device_state(void)
 }
 DECLARE_HOOK(HOOK_SECOND, check_device_state, HOOK_PRIO_DEFAULT);
 
-static int command_devices(int argc, char **argv)
+static int command_devices(int argc, const char **argv)
 {
 	const struct device_config *dc = device_states;
 	int i;
@@ -78,6 +79,5 @@ static int command_devices(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_SAFE_CONSOLE_COMMAND(devices, command_devices,
-			     "",
+DECLARE_SAFE_CONSOLE_COMMAND(devices, command_devices, "",
 			     "Get the device states");
diff --git a/common/dps.c b/common/dps.c
new file mode 100644
index 0000000000..2a05077fbf
--- /dev/null
+++ b/common/dps.c
@@ -0,0 +1,729 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Dynamic PDO Selection.
+ */
+
+#include "atomic.h"
+#include "battery.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "common.h"
+#include "console.h"
+#include "dps.h"
+#include "ec_commands.h"
+#include "hooks.h"
+#include "math_util.h"
+#include "task.h"
+#include "timer.h"
+#include "usb_common.h"
+#include "usb_pd.h"
+#include "util.h"
+
+#include <stdint.h>
+
+#define K_MORE_PWR 96
+#define K_LESS_PWR 93
+#define K_SAMPLE 1
+#define K_WINDOW 3
+#define T_REQUEST_STABLE_TIME (10 * SECOND)
+#define T_NEXT_CHECK_TIME (5 * SECOND)
+
+#define DPS_FLAG_STOP_EVENTS \
+	(DPS_FLAG_DISABLED | DPS_FLAG_NO_SRCCAP | DPS_FLAG_NO_BATTERY)
+#define DPS_FLAG_ALL GENMASK(31, 0)
+
+#define MAX_MOVING_AVG_WINDOW 5
+
+BUILD_ASSERT(K_MORE_PWR > K_LESS_PWR && 100 >= K_MORE_PWR && 100 >= K_LESS_PWR);
+
+/* lock for updating timeout value */
+K_MUTEX_DEFINE(dps_lock);
+static timestamp_t timeout;
+static bool is_enabled = true;
+static int debug_level;
+static bool fake_enabled;
+static int fake_mv, fake_ma;
+static int dynamic_mv;
+static int dps_port = CHARGE_PORT_NONE;
+static atomic_t flag;
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, "DPS " format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, "DPS " format, ##args)
+
+__overridable struct dps_config_t dps_config = {
+	.k_less_pwr = K_LESS_PWR,
+	.k_more_pwr = K_MORE_PWR,
+	.k_sample = K_SAMPLE,
+	.k_window = K_WINDOW,
+	.t_stable = T_REQUEST_STABLE_TIME,
+	.t_check = T_NEXT_CHECK_TIME,
+	.is_more_efficient = NULL,
+};
+
+__test_only struct dps_config_t *dps_get_config(void)
+{
+	return &dps_config;
+}
+
+int dps_get_dynamic_voltage(void)
+{
+	return dynamic_mv;
+}
+
+int dps_get_charge_port(void)
+{
+	return dps_port;
+}
+
+bool dps_is_enabled(void)
+{
+	return is_enabled;
+}
+
+test_export_static void dps_enable(bool en)
+{
+	bool prev_en = is_enabled;
+
+	is_enabled = en;
+
+	if (is_enabled && !prev_en) {
+		task_wake(TASK_ID_DPS);
+	}
+
+	if (!is_enabled) {
+		/* issue a new PD request for a default voltage */
+		if (dps_port != CHARGE_PORT_NONE)
+			pd_dpm_request(dps_port, DPM_REQUEST_NEW_POWER_LEVEL);
+	}
+}
+
+static void update_timeout(int us)
+{
+	timestamp_t new_timeout;
+
+	new_timeout.val = get_time().val + us;
+
+	mutex_lock(&dps_lock);
+	if (new_timeout.val > timeout.val)
+		timeout = new_timeout;
+	mutex_unlock(&dps_lock);
+}
+
+/*
+ * DPS reset.
+ */
+static void dps_reset(void)
+{
+	dynamic_mv = PD_MAX_VOLTAGE_MV;
+	dps_port = CHARGE_PORT_NONE;
+}
+
+/*
+ * DPS initialization.
+ */
+test_export_static int dps_init(void)
+{
+	int rc = EC_SUCCESS;
+
+	dps_reset();
+
+	if (dps_config.k_window > MAX_MOVING_AVG_WINDOW) {
+		CPRINTS("ERR:WIN");
+		rc = EC_ERROR_INVALID_CONFIG;
+	}
+
+	if (dps_config.k_less_pwr > 100 || dps_config.k_more_pwr > 100 ||
+	    dps_config.k_more_pwr <= dps_config.k_less_pwr) {
+		CPRINTS("ERR:COEF");
+		rc = EC_ERROR_INVALID_CONFIG;
+	}
+
+	return rc;
+}
+
+static bool is_near_limit(int val, int limit)
+{
+	return val >= (limit * dps_config.k_more_pwr / 100);
+}
+
+bool is_more_efficient(int curr_mv, int prev_mv, int batt_mv, int batt_mw,
+		       int input_mw)
+{
+	if (dps_config.is_more_efficient)
+		return dps_config.is_more_efficient(curr_mv, prev_mv, batt_mv,
+						    batt_mw, input_mw);
+
+	return ABS(curr_mv - batt_mv) < ABS(prev_mv - batt_mv);
+}
+
+/*
+ * Get the input power of the active port.
+ *
+ * input_power = vbus * input_current
+ *
+ * @param vbus: VBUS in mV
+ * @param input_curr: input current in mA
+ *
+ * @return input_power of the result of vbus * input_curr in mW
+ */
+test_mockable_static int get_desired_input_power(int *vbus, int *input_current)
+{
+	int active_port;
+	int charger_id;
+	enum ec_error_list rv;
+
+	active_port = charge_manager_get_active_charge_port();
+
+	if (active_port == CHARGE_PORT_NONE)
+		return 0;
+
+	charger_id = charge_get_active_chg_chip();
+
+	if (fake_enabled) {
+		*vbus = fake_mv;
+		*input_current = fake_ma;
+		return fake_mv * fake_ma / 1000;
+	}
+
+	rv = charger_get_input_current(charger_id, input_current);
+	if (rv)
+		return 0;
+
+	*vbus = charge_manager_get_vbus_voltage(active_port);
+
+	return (*vbus) * (*input_current) / 1000;
+}
+
+test_mockable_static int get_battery_target_voltage(int *target_mv)
+{
+	int charger_id = charge_get_active_chg_chip();
+	int error = charger_get_voltage(charger_id, target_mv);
+
+	if (!error) {
+		return EC_SUCCESS;
+	}
+	if (error != EC_ERROR_UNIMPLEMENTED) {
+		CPRINTS("Failed to get voltage for charge port %d: %d",
+			charger_id, error);
+		return error;
+	}
+	/*
+	 * Fall back to battery design voltage if charger output voltage
+	 * is not available.
+	 */
+	return battery_design_voltage(target_mv);
+}
+
+/*
+ * Get the most efficient PDO voltage for the battery of the charging port
+ *
+ * | W\Batt | 1S(3.7V) | 2S(7.4V) | 3S(11.1V) | 4S(14.8V) |
+ * --------------------------------------------------------
+ * | 0-15W  | 5V       | 9V       | 12V       | 15V       |
+ * | 15-27W | 9V       | 9V       | 12V       | 15V       |
+ * | 27-36W | 12V      | 12V      | 12V       | 15V       |
+ * | 36-45W | 15V      | 15V      | 15V       | 15V       |
+ * | 45-60W | 20V      | 20V      | 20V       | 20V       |
+ *
+ *
+ * @return 0 if error occurs, else battery efficient voltage in mV
+ */
+test_mockable_static int get_efficient_voltage(void)
+{
+	int eff_mv = 0;
+	int batt_mv;
+	int batt_pwr;
+	int input_pwr, vbus, input_curr;
+	const struct batt_params *batt = charger_current_battery_params();
+
+	input_pwr = get_desired_input_power(&vbus, &input_curr);
+
+	if (!input_pwr)
+		return 0;
+
+	if (get_battery_target_voltage(&batt_mv))
+		return 0;
+
+	batt_pwr = batt->current * batt->voltage / 1000;
+
+	for (int i = 0; i < board_get_usb_pd_port_count(); ++i) {
+		const int cnt = pd_get_src_cap_cnt(i);
+		const uint32_t *src_caps = pd_get_src_caps(i);
+
+		for (int j = 0; j < cnt; ++j) {
+			int ma, mv, unused;
+
+			pd_extract_pdo_power(src_caps[j], &ma, &mv, &unused);
+			/*
+			 * If the eff_mv is not picked, or we have more
+			 * efficient voltage (less voltage diff)
+			 */
+			if (eff_mv == 0 ||
+			    is_more_efficient(mv, eff_mv, batt_mv, batt_pwr,
+					      input_pwr))
+				eff_mv = mv;
+		}
+	}
+
+	return eff_mv;
+}
+
+struct pdo_candidate {
+	int port;
+	int mv;
+	int mw;
+};
+
+#define UPDATE_CANDIDATE(new_port, new_mv, new_mw) \
+	do {                                       \
+		cand->port = new_port;             \
+		cand->mv = new_mv;                 \
+		cand->mw = new_mw;                 \
+	} while (0)
+
+#define CLEAR_AND_RETURN()            \
+	do {                          \
+		moving_avg_count = 0; \
+		return false;         \
+	} while (0)
+
+test_mockable_static int get_batt_charge_power(void)
+{
+	const struct batt_params *batt = charger_current_battery_params();
+
+	return batt->current * batt->voltage / 1000;
+}
+
+/*
+ * Evaluate the system power if a new PD power request is needed.
+ *
+ * @param struct pdo_candidate: The candidate PDO. (Return value)
+ * @return true if a new power request, or false otherwise.
+ */
+test_mockable_static bool has_new_power_request(struct pdo_candidate *cand)
+{
+	int vbus, input_curr, input_pwr;
+	int input_pwr_avg = 0, input_curr_avg = 0;
+	int batt_pwr, batt_mv;
+	int max_mv = pd_get_max_voltage();
+	int req_pwr, req_ma, req_mv;
+	int input_curr_limit;
+	int active_port = charge_manager_get_active_charge_port();
+	int charger_id;
+	static int input_pwrs[MAX_MOVING_AVG_WINDOW];
+	static int input_currs[MAX_MOVING_AVG_WINDOW];
+	static int prev_active_port = CHARGE_PORT_NONE;
+	static int prev_req_mv;
+	static int moving_avg_count;
+
+	/* set a default value in case it early returns. */
+	UPDATE_CANDIDATE(CHARGE_PORT_NONE, INT32_MAX, 0);
+
+	if (active_port == CHARGE_PORT_NONE)
+		CLEAR_AND_RETURN();
+
+	req_mv = pd_get_requested_voltage(active_port);
+	req_ma = pd_get_requested_current(active_port);
+
+	if (!req_mv)
+		CLEAR_AND_RETURN();
+
+	if (get_battery_target_voltage(&batt_mv))
+		CLEAR_AND_RETURN();
+
+	/* if last sample is not the same as the current one, reset counting. */
+	if (prev_req_mv != req_mv || prev_active_port != active_port)
+		moving_avg_count = 0;
+	prev_active_port = active_port;
+	prev_req_mv = req_mv;
+
+	req_pwr = req_mv * req_ma / 1000;
+	batt_pwr = get_batt_charge_power();
+	input_pwr = get_desired_input_power(&vbus, &input_curr);
+
+	if (!input_pwr)
+		CLEAR_AND_RETURN();
+
+	/* record moving average */
+	input_pwrs[moving_avg_count % dps_config.k_window] = input_pwr;
+	input_currs[moving_avg_count % dps_config.k_window] = input_curr;
+	if (++moving_avg_count < dps_config.k_window)
+		return false;
+
+	for (int i = 0; i < dps_config.k_window; i++) {
+		input_curr_avg += input_currs[i];
+		input_pwr_avg += input_pwrs[i];
+	}
+	input_curr_avg /= dps_config.k_window;
+	input_pwr_avg /= dps_config.k_window;
+
+	charger_id = charge_get_active_chg_chip();
+
+	if (!charger_get_input_current_limit(charger_id, &input_curr_limit))
+		/* set as last requested mA if we're unable to get the limit. */
+		input_curr_limit = req_ma;
+
+	/*
+	 * input power might be insufficient, force it to negotiate a more
+	 * powerful PDO.
+	 */
+	if (is_near_limit(input_pwr_avg, req_pwr) ||
+	    is_near_limit(input_curr_avg, MIN(req_ma, input_curr_limit))) {
+		atomic_or(&flag, DPS_FLAG_NEED_MORE_PWR);
+		if (!fake_enabled)
+			input_pwr_avg = req_pwr + 1;
+	} else {
+		atomic_clear_bits(&flag, DPS_FLAG_NEED_MORE_PWR);
+	}
+
+	if (debug_level)
+		CPRINTS("C%d 0x%x last (%dmW %dmV) input (%dmW %dmV %dmA) "
+			"avg (%dmW, %dmA)",
+			active_port, (int)flag, req_pwr, req_mv, input_pwr,
+			vbus, input_curr, input_pwr_avg, input_curr_avg);
+
+	for (int i = 0; i < board_get_usb_pd_port_count(); ++i) {
+		const uint32_t *const src_caps = pd_get_src_caps(i);
+
+		/* If the port is not SNK, skip evaluating this port. */
+		if (pd_get_power_role(i) != PD_ROLE_SINK)
+			continue;
+
+		for (int j = 0; j < pd_get_src_cap_cnt(i); ++j) {
+			int ma, mv, unused;
+			int mw;
+			bool efficient;
+
+			/* TODO(b:169532537): support augmented PDO. */
+			if ((src_caps[j] & PDO_TYPE_MASK) != PDO_TYPE_FIXED)
+				continue;
+
+			pd_extract_pdo_power(src_caps[j], &ma, &mv, &unused);
+
+			if (mv > max_mv)
+				continue;
+
+			mw = MIN(ma, PD_MAX_CURRENT_MA) * mv / 1000;
+			efficient = is_more_efficient(mv, cand->mv, batt_mv,
+						      batt_pwr, input_pwr_avg);
+
+			if (flag & DPS_FLAG_NEED_MORE_PWR) {
+				/* the insufficient case.*/
+				if (input_pwr_avg > cand->mw &&
+				    (mw > cand->mw ||
+				     (mw == cand->mw && efficient))) {
+					UPDATE_CANDIDATE(i, mv, mw);
+				} else if (input_pwr_avg <= mw && efficient) {
+					UPDATE_CANDIDATE(i, mv, mw);
+				}
+			} else {
+				int adjust_pwr =
+					mw * dps_config.k_less_pwr / 100;
+				int adjust_cand_mw =
+					cand->mw * dps_config.k_less_pwr / 100;
+
+				/* Pick if we don't have a candidate yet. */
+				if (!cand->mw) {
+					UPDATE_CANDIDATE(i, mv, mw);
+					/*
+					 * if the candidate is insufficient, and
+					 * we get one provides more.
+					 */
+				} else if ((adjust_cand_mw < input_pwr_avg &&
+					    cand->mw < mw) ||
+					   /*
+					    * if the candidate is sufficient,
+					    * and we pick a more efficient one.
+					    */
+					   (adjust_cand_mw >= input_pwr_avg &&
+					    adjust_pwr >= input_pwr_avg &&
+					    efficient)) {
+					UPDATE_CANDIDATE(i, mv, mw);
+				}
+			}
+
+			/*
+			 * if the candidate is the same as the current one, pick
+			 * the one at active charge port.
+			 */
+			if (mw == cand->mw && mv == cand->mv &&
+			    i == active_port)
+				UPDATE_CANDIDATE(i, mv, mw);
+		}
+	}
+
+	if (!cand->mv)
+		CPRINTS("ERR:CNDMV");
+
+	return (cand->mv != req_mv);
+}
+
+__maybe_unused static bool has_srccap(void)
+{
+	for (int i = 0; i < board_get_usb_pd_port_count(); ++i) {
+		if (pd_is_connected(i) &&
+		    pd_get_power_role(i) == PD_ROLE_SINK &&
+		    pd_get_src_cap_cnt(i) > 0)
+			return true;
+	}
+	return false;
+}
+
+void dps_update_stabilized_time(int port)
+{
+	update_timeout(dps_config.t_stable);
+}
+
+void dps_task(void *u)
+{
+	struct pdo_candidate last_cand = { CHARGE_PORT_NONE, 0, 0 };
+	int sample_count = 0;
+	int rv;
+
+	rv = dps_init();
+	if (rv) {
+		CPRINTS("ERR:INIT%d", rv);
+		return;
+	}
+
+	update_timeout(dps_config.t_check);
+
+	while (1) {
+		struct pdo_candidate curr_cand = { CHARGE_PORT_NONE, 0, 0 };
+		timestamp_t now;
+
+		now = get_time();
+		if (flag & DPS_FLAG_STOP_EVENTS) {
+			dps_reset();
+			task_wait_event(-1);
+			/* clear flags after wake up. */
+			atomic_clear(&flag);
+			update_timeout(dps_config.t_check);
+			continue;
+		} else if (now.val < timeout.val) {
+			atomic_or(&flag, DPS_FLAG_WAITING);
+			task_wait_event(timeout.val - now.val);
+			atomic_clear_bits(&flag, DPS_FLAG_WAITING);
+			continue;
+		}
+
+		if (!is_enabled) {
+			atomic_or(&flag, DPS_FLAG_DISABLED);
+			continue;
+		}
+
+		if (!has_srccap()) {
+			atomic_or(&flag, DPS_FLAG_NO_SRCCAP);
+			continue;
+		}
+
+		if (battery_is_present() != BP_YES) {
+			atomic_or(&flag, DPS_FLAG_NO_BATTERY);
+			continue;
+		}
+
+		if (!has_new_power_request(&curr_cand)) {
+			sample_count = 0;
+			atomic_clear_bits(&flag, DPS_FLAG_SAMPLED);
+		} else {
+			if (last_cand.port == curr_cand.port &&
+			    last_cand.mv == curr_cand.mv &&
+			    last_cand.mw == curr_cand.mw)
+				sample_count++;
+			else
+				sample_count = 1;
+			atomic_or(&flag, DPS_FLAG_SAMPLED);
+		}
+
+		if (sample_count == dps_config.k_sample) {
+			dynamic_mv = curr_cand.mv;
+			dps_port = curr_cand.port;
+			pd_dpm_request(dps_port, DPM_REQUEST_NEW_POWER_LEVEL);
+			sample_count = 0;
+			atomic_clear_bits(&flag, (DPS_FLAG_SAMPLED |
+						  DPS_FLAG_NEED_MORE_PWR));
+		}
+
+		last_cand.port = curr_cand.port;
+		last_cand.mv = curr_cand.mv;
+		last_cand.mw = curr_cand.mw;
+		update_timeout(dps_config.t_check);
+	}
+}
+
+void check_battery_present(void)
+{
+	const struct batt_params *batt = charger_current_battery_params();
+
+	if (batt->is_present == BP_YES && (flag & DPS_FLAG_NO_BATTERY)) {
+		atomic_clear_bits(&flag, DPS_FLAG_NO_BATTERY);
+		task_wake(TASK_ID_DPS);
+	}
+}
+DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, check_battery_present, HOOK_PRIO_DEFAULT);
+
+static int command_dps(int argc, const char **argv)
+{
+	int port = charge_manager_get_active_charge_port();
+	int input_pwr, vbus, input_curr;
+	int holder;
+
+	if (argc == 1) {
+		uint32_t last_ma = 0, last_mv = 0;
+		int batt_mv;
+
+		ccprintf("flag=0x%x k_more=%d k_less=%d k_sample=%d k_win=%d\n",
+			 (int)flag, dps_config.k_more_pwr,
+			 dps_config.k_less_pwr, dps_config.k_sample,
+			 dps_config.k_window);
+		ccprintf("t_stable=%d t_check=%d\n",
+			 dps_config.t_stable / SECOND,
+			 dps_config.t_check / SECOND);
+		if (!is_enabled) {
+			ccprintf("DPS Disabled\n");
+			return EC_SUCCESS;
+		}
+
+		if (port == CHARGE_PORT_NONE) {
+			ccprintf("No charger attached\n");
+			return EC_SUCCESS;
+		}
+
+		get_battery_target_voltage(&batt_mv);
+		input_pwr = get_desired_input_power(&vbus, &input_curr);
+		if (!(flag & DPS_FLAG_NO_SRCCAP)) {
+			last_mv = pd_get_requested_voltage(port);
+			last_ma = pd_get_requested_current(port);
+		}
+		ccprintf("C%d DPS Enabled\n"
+			 "Requested: %dmV/%dmA\n"
+			 "Measured:  %dmV/%dmA/%dmW\n"
+			 "Efficient: %dmV\n"
+			 "Batt:      %dmv\n"
+			 "PDMaxMV:   %dmV\n",
+			 port, last_mv, last_ma, vbus, input_curr, input_pwr,
+			 get_efficient_voltage(), batt_mv,
+			 pd_get_max_voltage());
+		return EC_SUCCESS;
+	}
+
+	if (!strcasecmp(argv[1], "en")) {
+		dps_enable(true);
+		return EC_SUCCESS;
+	} else if (!strcasecmp(argv[1], "dis")) {
+		dps_enable(false);
+		return EC_SUCCESS;
+	} else if (!strcasecmp(argv[1], "fakepwr")) {
+		if (argc == 2) {
+			ccprintf("%sabled %dmV/%dmA\n",
+				 fake_enabled ? "en" : "dis", fake_mv, fake_ma);
+			return EC_SUCCESS;
+		}
+
+		if (!strcasecmp(argv[2], "dis")) {
+			fake_enabled = false;
+			return EC_SUCCESS;
+		}
+
+		if (argc < 4)
+			return EC_ERROR_PARAM_COUNT;
+
+		holder = atoi(argv[2]);
+		if (holder <= 0)
+			return EC_ERROR_PARAM2;
+		fake_mv = holder;
+
+		holder = atoi(argv[3]);
+		if (holder <= 0)
+			return EC_ERROR_PARAM3;
+		fake_ma = holder;
+
+		fake_enabled = true;
+		return EC_SUCCESS;
+	}
+
+	if (argc != 3)
+		return EC_ERROR_PARAM2;
+
+	if (!strcasecmp(argv[1], "debug")) {
+		debug_level = atoi(argv[2]);
+	} else if (!strcasecmp(argv[1], "setkmore")) {
+		holder = atoi(argv[2]);
+		if (holder > 100 || holder <= 0 ||
+		    holder < dps_config.k_less_pwr)
+			return EC_ERROR_PARAM2;
+		dps_config.k_more_pwr = holder;
+	} else if (!strcasecmp(argv[1], "setkless")) {
+		holder = atoi(argv[2]);
+		if (holder > 100 || holder <= 0 ||
+		    holder > dps_config.k_more_pwr)
+			return EC_ERROR_PARAM2;
+		dps_config.k_less_pwr = holder;
+	} else if (!strcasecmp(argv[1], "setksample")) {
+		holder = atoi(argv[2]);
+		if (holder <= 0)
+			return EC_ERROR_PARAM2;
+		dps_config.k_sample = holder;
+	} else if (!strcasecmp(argv[1], "setkwin")) {
+		holder = atoi(argv[2]);
+		if (holder <= 0 || holder > MAX_MOVING_AVG_WINDOW)
+			return EC_ERROR_PARAM2;
+		dps_config.k_window = holder;
+	} else if (!strcasecmp(argv[1], "settcheck")) {
+		holder = atoi(argv[2]);
+		if (holder <= 0)
+			return EC_ERROR_PARAM2;
+		dps_config.t_check = holder * SECOND;
+	} else if (!strcasecmp(argv[1], "settstable")) {
+		holder = atoi(argv[2]);
+		if (holder <= 0)
+			return EC_ERROR_PARAM2;
+		dps_config.t_stable = holder * SECOND;
+	} else {
+		return EC_ERROR_PARAM1;
+	}
+
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(dps, command_dps,
+			"en|dis|debug <int>\n"
+			"\t\t set(kmore|kless|ksample|kwindow) <int>\n"
+			"\t\t set(tstable|tcheck) <int>\n"
+			"\t\t fakepwr [dis|<mV> <mA>]",
+			"Print/set Dynamic PDO Selection state.");
+
+static enum ec_status hc_usb_pd_dps_control(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_usb_pd_dps_control *p = args->params;
+
+	dps_enable(p->enable);
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_USB_PD_DPS_CONTROL, hc_usb_pd_dps_control,
+		     EC_VER_MASK(0));
+
+#ifdef TEST_BUILD
+__test_only bool dps_is_fake_enabled(void)
+{
+	return fake_enabled;
+}
+__test_only int dps_get_fake_mv(void)
+{
+	return fake_mv;
+}
+__test_only int dps_get_fake_ma(void)
+{
+	return fake_ma;
+}
+__test_only int *dps_get_debug_level(void)
+{
+	return &debug_level;
+}
+__test_only int dps_get_flag(void)
+{
+	return flag;
+}
+#endif /* TEST_BUILD */
diff --git a/common/dptf.c b/common/dptf.c
index f4fc6d0ff6..5c976e8ea9 100644
--- a/common/dptf.c
+++ b/common/dptf.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,17 +13,23 @@
 #include "temp_sensor.h"
 #include "util.h"
 
+#ifdef CONFIG_ZEPHYR
+#include "temp_sensor/temp_sensor.h"
+#endif
+
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_DPTF, outstr)
-#define CPRINTS(format, args...) cprints(CC_DPTF, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_DPTF, format, ##args)
 
 /*****************************************************************************/
 /* DPTF temperature thresholds */
 
 static struct {
-	int temp;     /* degrees K, negative for disabled */
-	cond_t over;      /* watch for crossings */
+	int temp; /* degrees K, negative for disabled */
+	cond_t over; /* watch for crossings */
 } dptf_threshold[TEMP_SENSOR_COUNT][DPTF_THRESHOLDS_PER_SENSOR];
+_STATIC_ASSERT(TEMP_SENSOR_COUNT > 0,
+	       "CONFIG_PLATFORM_EC_DPTF enabled, but no temp sensors");
 
 static void dptf_init(void)
 {
@@ -34,20 +40,19 @@ static void dptf_init(void)
 			dptf_threshold[id][t].temp = -1;
 			cond_init(&dptf_threshold[id][t].over, 0);
 		}
-
 }
 DECLARE_HOOK(HOOK_INIT, dptf_init, HOOK_PRIO_DEFAULT);
 
 /* Keep track of which triggered sensor thresholds the AP has seen */
-static uint32_t dptf_seen;
+static atomic_t dptf_seen;
 
 int dptf_query_next_sensor_event(void)
 {
 	int id;
 
 	for (id = 0; id < TEMP_SENSOR_COUNT; id++)
-		if (dptf_seen & BIT(id)) {  /* atomic? */
-			deprecated_atomic_clear_bits(&dptf_seen, BIT(id));
+		if ((uint32_t)dptf_seen & BIT(id)) {
+			atomic_clear_bits(&dptf_seen, BIT(id));
 			return id;
 		}
 
@@ -66,9 +71,8 @@ static int dptf_check_temp_threshold(int sensor_id, int temp)
 	}
 
 	for (i = 0; i < DPTF_THRESHOLDS_PER_SENSOR; i++) {
-
 		max = dptf_threshold[sensor_id][i].temp;
-		if (max < 0)      /* disabled? */
+		if (max < 0) /* disabled? */
 			continue;
 
 		if (temp >= max)
@@ -77,15 +81,13 @@ static int dptf_check_temp_threshold(int sensor_id, int temp)
 			cond_set_false(&dptf_threshold[sensor_id][i].over);
 
 		if (cond_went_true(&dptf_threshold[sensor_id][i].over)) {
-			CPRINTS("DPTF over threshold [%d][%d",
-				sensor_id, i);
-			deprecated_atomic_or(&dptf_seen, BIT(sensor_id));
+			CPRINTS("DPTF over threshold [%d][%d", sensor_id, i);
+			atomic_or(&dptf_seen, BIT(sensor_id));
 			tripped = 1;
 		}
 		if (cond_went_false(&dptf_threshold[sensor_id][i].over)) {
-			CPRINTS("DPTF under threshold [%d][%d",
-				sensor_id, i);
-			deprecated_atomic_or(&dptf_seen, BIT(sensor_id));
+			CPRINTS("DPTF under threshold [%d][%d", sensor_id, i);
+			atomic_or(&dptf_seen, BIT(sensor_id));
 			tripped = 1;
 		}
 	}
@@ -95,8 +97,8 @@ static int dptf_check_temp_threshold(int sensor_id, int temp)
 
 void dptf_set_temp_threshold(int sensor_id, int temp, int idx, int enable)
 {
-	CPRINTS("DPTF sensor %d, threshold %d C, index %d, %sabled",
-		sensor_id, K_TO_C(temp), idx, enable ? "en" : "dis");
+	CPRINTS("DPTF sensor %d, threshold %d C, index %d, %sabled", sensor_id,
+		K_TO_C(temp), idx, enable ? "en" : "dis");
 
 	if ((sensor_id >= TEMP_SENSOR_COUNT) ||
 	    (idx >= DPTF_THRESHOLDS_PER_SENSOR)) {
@@ -109,7 +111,7 @@ void dptf_set_temp_threshold(int sensor_id, int temp, int idx, int enable)
 		if (dptf_threshold[sensor_id][idx].temp == -1)
 			cond_init(&dptf_threshold[sensor_id][idx].over, 0);
 		dptf_threshold[sensor_id][idx].temp = temp;
-		deprecated_atomic_clear_bits(&dptf_seen, BIT(sensor_id));
+		atomic_clear_bits(&dptf_seen, BIT(sensor_id));
 	} else {
 		dptf_threshold[sensor_id][idx].temp = -1;
 	}
@@ -118,8 +120,20 @@ void dptf_set_temp_threshold(int sensor_id, int temp, int idx, int enable)
 /*****************************************************************************/
 /* EC-specific thermal controls */
 
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+__overridable int board_temp_smi_evet(void)
+{
+	/* Do nothing by default. Boards can modify the temps condition */
+	return true;
+}
+#endif
+
 test_mockable_static void smi_sensor_failure_warning(void)
 {
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+	if (!board_temp_smi_evet())
+		return;
+#endif
 	CPRINTS("can't read any temp sensors!");
 	host_set_single_event(EC_HOST_EVENT_THERMAL);
 }
@@ -172,7 +186,7 @@ DECLARE_HOOK(HOOK_SECOND, thermal_control_dptf, HOOK_PRIO_TEMP_SENSOR_DONE);
 /*****************************************************************************/
 /* Console commands */
 
-static int command_dptftemp(int argc, char **argv)
+static int command_dptftemp(int argc, const char **argv)
 {
 	int id, t;
 	int temp, trig;
@@ -192,9 +206,8 @@ static int command_dptftemp(int argc, char **argv)
 		ccprintf("    %s\n", temp_sensors[id].name);
 	}
 
-	ccprintf("AP seen mask: 0x%08x\n", dptf_seen);
+	ccprintf("AP seen mask: 0x%08x\n", (int)dptf_seen);
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(dptftemp, command_dptftemp,
-			NULL,
+DECLARE_CONSOLE_COMMAND(dptftemp, command_dptftemp, NULL,
 			"Print DPTF thermal parameters (degrees Kelvin)");
diff --git a/common/ec.libsharedobjs.ld b/common/ec.libsharedobjs.ld
index adf5081640..57b67daecc 100644
--- a/common/ec.libsharedobjs.ld
+++ b/common/ec.libsharedobjs.ld
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/common/ec_ec_comm_client.c b/common/ec_ec_comm_client.c
new file mode 100644
index 0000000000..193d121343
--- /dev/null
+++ b/common/ec_ec_comm_client.c
@@ -0,0 +1,377 @@
+/* Copyright 2017 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * EC-EC communication, functions and definitions for client.
+ */
+
+#include "battery.h"
+#include "common.h"
+#include "console.h"
+#include "crc8.h"
+#include "ec_commands.h"
+#include "ec_ec_comm_client.h"
+#include "timer.h"
+#include "uart.h"
+#include "util.h"
+
+/* Console output macros */
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+
+/*
+ * TODO(b:65697962): The packed structures below do not play well if we force EC
+ * host commands structures to be aligned on 32-bit boundary. There are ways to
+ * fix that, possibly requiring copying data around, or modifying
+ * uart_alt_pad_write_read API to write the actual server response to a separate
+ * buffer.
+ */
+#ifdef CONFIG_HOSTCMD_ALIGNED
+#error "Cannot define CONFIG_HOSTCMD_ALIGNED with EC-EC communication client."
+#endif
+
+#define EC_EC_HOSTCMD_VERSION 4
+
+/* Print extra debugging information */
+#undef EXTRA_DEBUG
+
+/*
+ * During early debugging, we would like to check that the error rate does
+ * grow out of control.
+ */
+#define DEBUG_EC_COMM_STATS
+#ifdef DEBUG_EC_COMM_STATS
+struct {
+	int total;
+	int errtimeout;
+	int errbusy;
+	int errunknown;
+	int errdatacrc;
+	int errcrc;
+	int errinval;
+} comm_stats;
+
+#define INCR_COMM_STATS(var) (comm_stats.var++)
+#else
+#define INCR_COMM_STATS(var)
+#endif
+
+/**
+ * Write a command on the EC-EC communication UART channel.
+ *
+ * @param command	One of EC_CMD_*.
+ * @param data		Packed structure with this layout:
+ * struct {
+ *	struct {
+ *		struct ec_host_request4 head;
+ *		struct ec_params_* param;
+ *		uint8_t crc8;
+ *	} req;
+ *	struct {
+ *		struct ec_host_response4 head;
+ *		struct ec_response_* info;
+ *		uint8_t crc8;
+ *	} resp;
+ * } __packed data;
+ *
+ * Where req is the request to be transmitted (head and crc8 are computed by
+ * this function), and resp is the response to be received (head integrity and
+ * crc8 are verified by this function).
+ *
+ * This format is required as the EC-EC UART is half-duplex, and all the
+ * transmitted data is received back, i.e. the client writes req, then reads
+ * req, followed by resp.
+ *
+ * When a command does not take parameters, param/crc8 must be omitted in
+ * tx structure. The same applies to rx structure if the response does not
+ * include a payload: info/crc8 must be omitted.
+ *
+ * @param req_len	size of req.param (0 if no parameter is passed).
+ * @param resp_len	size of resp.info (0 if no information is returned).
+ * @param timeout_us	timeout in microseconds for the transaction to complete.
+ *
+ * @return
+ *  - EC_SUCCESS on success.
+ *  - EC_ERROR_TIMEOUT when remote end times out replying.
+ *  - EC_ERROR_BUSY when UART is busy and cannot transmit currently.
+ *  - EC_ERROR_CRC when the header or data CRC is invalid.
+ *  - EC_ERROR_INVAL when the received header is invalid.
+ *  - EC_ERROR_UNKNOWN on other error.
+ */
+static int write_command(uint16_t command, uint8_t *data, int req_len,
+			 int resp_len, int timeout_us)
+{
+	/* Sequence number. */
+	static uint8_t cur_seq;
+	int ret;
+	int hascrc, response_seq;
+
+	struct ec_host_request4 *request_header = (void *)data;
+	/* Request (TX) length is header + (data + crc8), response follows. */
+	int tx_length =
+		sizeof(*request_header) + ((req_len > 0) ? (req_len + 1) : 0);
+
+	struct ec_host_response4 *response_header = (void *)&data[tx_length];
+	/* RX length is TX length + response from server. */
+	int rx_length = tx_length + sizeof(*request_header) +
+			((resp_len > 0) ? (resp_len + 1) : 0);
+
+	/*
+	 * Make sure there is a gap between each command, so that the server
+	 * can recover its state machine after each command.
+	 *
+	 * TODO(b:65697962): We can be much smarter than this, and record the
+	 * last transaction time instead of just sleeping blindly.
+	 */
+	usleep(10 * MSEC);
+
+#ifdef DEBUG_EC_COMM_STATS
+	if ((comm_stats.total % 128) == 0) {
+		CPRINTF("UART %d (T%dB%d,U%dC%dD%dI%d)\n", comm_stats.total,
+			comm_stats.errtimeout, comm_stats.errbusy,
+			comm_stats.errunknown, comm_stats.errcrc,
+			comm_stats.errdatacrc, comm_stats.errinval);
+	}
+#endif
+
+	cur_seq = (cur_seq + 1) &
+		  (EC_PACKET4_0_SEQ_NUM_MASK >> EC_PACKET4_0_SEQ_NUM_SHIFT);
+
+	memset(request_header, 0, sizeof(*request_header));
+	/* fields0: leave seq_dup and is_response as 0. */
+	request_header->fields0 =
+		EC_EC_HOSTCMD_VERSION | /* version */
+		(cur_seq << EC_PACKET4_0_SEQ_NUM_SHIFT); /* seq_num
+							  */
+	/* fields1: leave command_version as 0. */
+	if (req_len > 0)
+		request_header->fields1 |= EC_PACKET4_1_DATA_CRC_PRESENT_MASK;
+	request_header->command = command;
+	request_header->data_len = req_len;
+	request_header->header_crc = cros_crc8((uint8_t *)request_header,
+					       sizeof(*request_header) - 1);
+	if (req_len > 0)
+		data[sizeof(*request_header) + req_len] =
+			cros_crc8(&data[sizeof(*request_header)], req_len);
+
+	ret = uart_alt_pad_write_read((void *)data, tx_length, (void *)data,
+				      rx_length, timeout_us);
+
+	INCR_COMM_STATS(total);
+
+#ifdef EXTRA_DEBUG
+	CPRINTF("EC-EC ret=%d/%d\n", ret, rx_length);
+#endif
+
+	if (ret != rx_length) {
+		if (ret == -EC_ERROR_TIMEOUT) {
+			INCR_COMM_STATS(errtimeout);
+			return EC_ERROR_TIMEOUT;
+		}
+
+		if (ret == -EC_ERROR_BUSY) {
+			INCR_COMM_STATS(errbusy);
+			return EC_ERROR_BUSY;
+		}
+
+		INCR_COMM_STATS(errunknown);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	if (response_header->header_crc !=
+	    cros_crc8((uint8_t *)response_header,
+		      sizeof(*response_header) - 1)) {
+		INCR_COMM_STATS(errcrc);
+		return EC_ERROR_CRC;
+	}
+
+	hascrc = response_header->fields1 & EC_PACKET4_1_DATA_CRC_PRESENT_MASK;
+	response_seq = (response_header->fields0 & EC_PACKET4_0_SEQ_NUM_MASK) >>
+		       EC_PACKET4_0_SEQ_NUM_SHIFT;
+
+	/*
+	 * Validate received header.
+	 * Note that we _require_ data crc to be present if there is data to be
+	 * read back, else we would not know how many bytes to read exactly.
+	 */
+	if ((response_header->fields0 & EC_PACKET4_0_STRUCT_VERSION_MASK) !=
+		    EC_EC_HOSTCMD_VERSION ||
+	    !(response_header->fields0 & EC_PACKET4_0_IS_RESPONSE_MASK) ||
+	    response_seq != cur_seq ||
+	    (response_header->data_len > 0 && !hascrc) ||
+	    response_header->data_len != resp_len) {
+		INCR_COMM_STATS(errinval);
+		return EC_ERROR_INVAL;
+	}
+
+	/* Check data CRC. */
+	if (hascrc &&
+	    data[rx_length - 1] !=
+		    cros_crc8(&data[tx_length + sizeof(*request_header)],
+			      resp_len)) {
+		INCR_COMM_STATS(errdatacrc);
+		return EC_ERROR_CRC;
+	}
+
+	return EC_SUCCESS;
+}
+
+/**
+ * handle error from write_command
+ *
+ * @param ret is return value from write_command
+ * @param request_result is data.resp.head.result (response result value)
+ *
+ * @return EC_RES_ERROR if ret is not EC_SUCCESS, else request_result.
+ */
+static int handle_error(const char *func, int ret, int request_result)
+{
+	if (ret != EC_SUCCESS) {
+		/* Do not print busy errors as they just spam the console. */
+		if (ret != EC_ERROR_BUSY)
+			CPRINTF("%s: tx error %d\n", func, ret);
+		return EC_RES_ERROR;
+	}
+
+	if (request_result != EC_RES_SUCCESS)
+		CPRINTF("%s: cmd error %d\n", func, ret);
+
+	return request_result;
+}
+
+#ifdef CONFIG_EC_EC_COMM_BATTERY
+int ec_ec_client_base_get_dynamic_info(void)
+{
+	int ret;
+	struct {
+		struct {
+			struct ec_host_request4 head;
+			struct ec_params_battery_dynamic_info param;
+			uint8_t crc8;
+		} req;
+		struct {
+			struct ec_host_response4 head;
+			struct ec_response_battery_dynamic_info info;
+			uint8_t crc8;
+		} resp;
+	} __packed data;
+
+	data.req.param.index = 0;
+
+	ret = write_command(EC_CMD_BATTERY_GET_DYNAMIC, (void *)&data,
+			    sizeof(data.req.param), sizeof(data.resp.info),
+			    15 * MSEC);
+	ret = handle_error(__func__, ret, data.resp.head.result);
+	if (ret != EC_RES_SUCCESS)
+		return ret;
+
+#ifdef EXTRA_DEBUG
+	CPRINTF("V:          %d mV\n", data.resp.info.actual_voltage);
+	CPRINTF("I:          %d mA\n", data.resp.info.actual_current);
+	CPRINTF("Remaining:  %d mAh\n", data.resp.info.remaining_capacity);
+	CPRINTF("Cap-full:   %d mAh\n", data.resp.info.full_capacity);
+	CPRINTF("Flags:      %04x\n", data.resp.info.flags);
+	CPRINTF("V-desired:  %d mV\n", data.resp.info.desired_voltage);
+	CPRINTF("I-desired:  %d mA\n", data.resp.info.desired_current);
+#endif
+
+	memcpy(&battery_dynamic[BATT_IDX_BASE], &data.resp.info,
+	       sizeof(battery_dynamic[BATT_IDX_BASE]));
+	return EC_RES_SUCCESS;
+}
+
+int ec_ec_client_base_get_static_info(void)
+{
+	int ret;
+	struct {
+		struct {
+			struct ec_host_request4 head;
+			struct ec_params_battery_static_info param;
+			uint8_t crc8;
+		} req;
+		struct {
+			struct ec_host_response4 head;
+			struct ec_response_battery_static_info info;
+			uint8_t crc8;
+		} resp;
+	} __packed data;
+	const struct ec_response_battery_static_info *info = &data.resp.info;
+	struct battery_static_info *bs = &battery_static[BATT_IDX_BASE];
+
+	data.req.param.index = 0;
+
+	ret = write_command(EC_CMD_BATTERY_GET_STATIC, (void *)&data,
+			    sizeof(data.req.param), sizeof(data.resp.info),
+			    15 * MSEC);
+	ret = handle_error(__func__, ret, data.resp.head.result);
+	if (ret != EC_RES_SUCCESS)
+		return ret;
+
+#ifdef EXTRA_DEBUG
+	CPRINTF("Cap-design: %d mAh\n", data.resp.info.design_capacity);
+	CPRINTF("V-design:   %d mV\n", data.resp.info.design_voltage);
+	CPRINTF("Manuf:      %s\n", data.resp.info.manufacturer);
+	CPRINTF("Model:      %s\n", data.resp.info.model);
+	CPRINTF("Serial:     %s\n", data.resp.info.serial);
+	CPRINTF("Type:       %s\n", data.resp.info.type);
+	CPRINTF("C-count:    %d\n", data.resp.info.cycle_count);
+#endif
+
+	bs->design_capacity = info->design_capacity;
+	bs->design_voltage = info->design_voltage;
+	bs->cycle_count = info->cycle_count;
+	strncpy(bs->manufacturer_ext, info->manufacturer,
+		sizeof(bs->manufacturer_ext));
+	strncpy(bs->model_ext, info->model, sizeof(bs->model_ext));
+	strncpy(bs->serial_ext, info->serial, sizeof(bs->serial_ext));
+	strncpy(bs->type_ext, info->type, sizeof(bs->type_ext));
+
+	return EC_RES_SUCCESS;
+}
+
+int ec_ec_client_base_charge_control(int max_current, int otg_voltage,
+				     int allow_charging)
+{
+	int ret;
+	struct {
+		struct {
+			struct ec_host_request4 head;
+			struct ec_params_charger_control ctrl;
+			uint8_t crc8;
+		} req;
+		struct {
+			struct ec_host_response4 head;
+		} resp;
+	} __packed data;
+
+	data.req.ctrl.allow_charging = allow_charging;
+	data.req.ctrl.max_current = max_current;
+	data.req.ctrl.otg_voltage = otg_voltage;
+
+	ret = write_command(EC_CMD_CHARGER_CONTROL, (void *)&data,
+			    sizeof(data.req.ctrl), 0, 30 * MSEC);
+
+	return handle_error(__func__, ret, data.resp.head.result);
+}
+
+int ec_ec_client_hibernate(void)
+{
+	int ret;
+	struct {
+		struct {
+			struct ec_host_request4 head;
+			struct ec_params_reboot_ec param;
+		} req;
+		struct {
+			struct ec_host_response4 head;
+		} resp;
+	} __packed data;
+
+	data.req.param.cmd = EC_REBOOT_HIBERNATE;
+	data.req.param.flags = 0;
+
+	ret = write_command(EC_CMD_REBOOT_EC, (void *)&data,
+			    sizeof(data.req.param), 0, 30 * MSEC);
+
+	return handle_error(__func__, ret, data.resp.head.result);
+}
+#endif /* CONFIG_EC_EC_COMM_BATTERY */
diff --git a/common/ec_ec_comm_master.c b/common/ec_ec_comm_master.c
deleted file mode 100644
index 966e4c0f53..0000000000
--- a/common/ec_ec_comm_master.c
+++ /dev/null
@@ -1,370 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * EC-EC communication, functions and definitions for master.
- */
-
-#include "battery.h"
-#include "common.h"
-#include "console.h"
-#include "crc8.h"
-#include "ec_commands.h"
-#include "ec_ec_comm_master.h"
-#include "timer.h"
-#include "uart.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-
-/*
- * TODO(b:65697962): The packed structures below do not play well if we force EC
- * host commands structures to be aligned on 32-bit boundary. There are ways to
- * fix that, possibly requiring copying data around, or modifying
- * uart_alt_pad_write_read API to write the actual slave response to a separate
- * buffer.
- */
-#ifdef CONFIG_HOSTCMD_ALIGNED
-#error "Cannot define CONFIG_HOSTCMD_ALIGNED with EC-EC communication master."
-#endif
-
-#define EC_EC_HOSTCMD_VERSION 4
-
-/* Print extra debugging information */
-#undef EXTRA_DEBUG
-
-/*
- * During early debugging, we would like to check that the error rate does
- * grow out of control.
- */
-#define DEBUG_EC_COMM_STATS
-#ifdef DEBUG_EC_COMM_STATS
-struct {
-	int total;
-	int errtimeout;
-	int errbusy;
-	int errunknown;
-	int errdatacrc;
-	int errcrc;
-	int errinval;
-} comm_stats;
-
-#define INCR_COMM_STATS(var) (comm_stats.var++)
-#else
-#define INCR_COMM_STATS(var)
-#endif
-
-/**
- * Write a command on the EC-EC communication UART channel.
- *
- * @param command	One of EC_CMD_*.
- * @param data		Packed structure with this layout:
- * struct {
- *	struct {
- *		struct ec_host_request4 head;
- *		struct ec_params_* param;
- *		uint8_t crc8;
- *	} req;
- *	struct {
- *		struct ec_host_response4 head;
- *		struct ec_response_* info;
- *		uint8_t crc8;
- *	} resp;
- * } __packed data;
- *
- * Where req is the request to be transmitted (head and crc8 are computed by
- * this function), and resp is the response to be received (head integrity and
- * crc8 are verified by this function).
- *
- * This format is required as the EC-EC UART is half-duplex, and all the
- * transmitted data is received back, i.e. the master writes req, then reads
- * req, followed by resp.
- *
- * When a command does not take parameters, param/crc8 must be omitted in
- * tx structure. The same applies to rx structure if the response does not
- * include a payload: info/crc8 must be omitted.
- *
- * @param req_len	size of req.param (0 if no parameter is passed).
- * @param resp_len	size of resp.info (0 if no information is returned).
- * @param timeout_us	timeout in microseconds for the transaction to complete.
- *
- * @return
- *  - EC_SUCCESS on success.
- *  - EC_ERROR_TIMEOUT when remote end times out replying.
- *  - EC_ERROR_BUSY when UART is busy and cannot transmit currently.
- *  - EC_ERROR_CRC when the header or data CRC is invalid.
- *  - EC_ERROR_INVAL when the received header is invalid.
- *  - EC_ERROR_UNKNOWN on other error.
- */
-static int write_command(uint16_t command,
-			 uint8_t *data, int req_len, int resp_len,
-			 int timeout_us)
-{
-	/* Sequence number. */
-	static uint8_t cur_seq;
-	int ret;
-	int hascrc, response_seq;
-
-	struct ec_host_request4 *request_header = (void *)data;
-	/* Request (TX) length is header + (data + crc8), response follows. */
-	int tx_length =
-		sizeof(*request_header) + ((req_len > 0) ? (req_len + 1) : 0);
-
-	struct ec_host_response4 *response_header =
-		(void *)&data[tx_length];
-	/* RX length is TX length + response from slave. */
-	int rx_length = tx_length +
-		sizeof(*request_header) + ((resp_len > 0) ? (resp_len + 1) : 0);
-
-	/*
-	 * Make sure there is a gap between each command, so that the slave
-	 * can recover its state machine after each command.
-	 *
-	 * TODO(b:65697962): We can be much smarter than this, and record the
-	 * last transaction time instead of just sleeping blindly.
-	 */
-	usleep(10*MSEC);
-
-#ifdef DEBUG_EC_COMM_STATS
-	if ((comm_stats.total % 128) == 0) {
-		CPRINTF("UART %d (T%dB%d,U%dC%dD%dI%d)\n", comm_stats.total,
-			comm_stats.errtimeout, comm_stats.errbusy,
-			comm_stats.errunknown, comm_stats.errcrc,
-			comm_stats.errdatacrc, comm_stats.errinval);
-	}
-#endif
-
-	cur_seq = (cur_seq + 1) &
-		(EC_PACKET4_0_SEQ_NUM_MASK >> EC_PACKET4_0_SEQ_NUM_SHIFT);
-
-	memset(request_header, 0, sizeof(*request_header));
-	/* fields0: leave seq_dup and is_response as 0. */
-	request_header->fields0 =
-		EC_EC_HOSTCMD_VERSION | /* version */
-		(cur_seq << EC_PACKET4_0_SEQ_NUM_SHIFT); /* seq_num */
-	/* fields1: leave command_version as 0. */
-	if (req_len > 0)
-		request_header->fields1 |= EC_PACKET4_1_DATA_CRC_PRESENT_MASK;
-	request_header->command = command;
-	request_header->data_len = req_len;
-	request_header->header_crc =
-		crc8((uint8_t *)request_header, sizeof(*request_header)-1);
-	if (req_len > 0)
-		data[sizeof(*request_header) + req_len] =
-			crc8(&data[sizeof(*request_header)], req_len);
-
-	ret = uart_alt_pad_write_read((void *)data, tx_length,
-				      (void *)data, rx_length, timeout_us);
-
-	INCR_COMM_STATS(total);
-
-#ifdef EXTRA_DEBUG
-	CPRINTF("EC-EC ret=%d/%d\n", ret, rx_length);
-#endif
-
-	if (ret != rx_length) {
-		if (ret == -EC_ERROR_TIMEOUT) {
-			INCR_COMM_STATS(errtimeout);
-			return EC_ERROR_TIMEOUT;
-		}
-
-		if (ret == -EC_ERROR_BUSY) {
-			INCR_COMM_STATS(errbusy);
-			return EC_ERROR_BUSY;
-		}
-
-		INCR_COMM_STATS(errunknown);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	if (response_header->header_crc !=
-			crc8((uint8_t *)response_header,
-				sizeof(*response_header)-1)) {
-		INCR_COMM_STATS(errcrc);
-		return EC_ERROR_CRC;
-	}
-
-	hascrc = response_header->fields1 & EC_PACKET4_1_DATA_CRC_PRESENT_MASK;
-	response_seq = (response_header->fields0 & EC_PACKET4_0_SEQ_NUM_MASK) >>
-		EC_PACKET4_0_SEQ_NUM_SHIFT;
-
-	/*
-	 * Validate received header.
-	 * Note that we _require_ data crc to be present if there is data to be
-	 * read back, else we would not know how many bytes to read exactly.
-	 */
-	if ((response_header->fields0 & EC_PACKET4_0_STRUCT_VERSION_MASK)
-				!= EC_EC_HOSTCMD_VERSION ||
-			!(response_header->fields0 &
-				EC_PACKET4_0_IS_RESPONSE_MASK) ||
-			response_seq != cur_seq ||
-			(response_header->data_len > 0 && !hascrc) ||
-			response_header->data_len != resp_len) {
-		INCR_COMM_STATS(errinval);
-		return EC_ERROR_INVAL;
-	}
-
-	/* Check data CRC. */
-	if (hascrc && data[rx_length - 1] !=
-		    crc8(&data[tx_length + sizeof(*request_header)],
-				 resp_len)) {
-		INCR_COMM_STATS(errdatacrc);
-		return EC_ERROR_CRC;
-	}
-
-	return EC_SUCCESS;
-}
-
-/**
- * handle error from write_command
- *
- * @param ret is return value from write_command
- * @param request_result is data.resp.head.result (response result value)
- *
- * @return EC_RES_ERROR if ret is not EC_SUCCESS, else request_result.
- */
-static int handle_error(const char *func, int ret, int request_result)
-{
-	if (ret != EC_SUCCESS) {
-		/* Do not print busy errors as they just spam the console. */
-		if (ret != EC_ERROR_BUSY)
-			CPRINTF("%s: tx error %d\n", func, ret);
-		return EC_RES_ERROR;
-	}
-
-	if (request_result != EC_RES_SUCCESS)
-		CPRINTF("%s: cmd error %d\n", func, ret);
-
-	return request_result;
-}
-
-#ifdef CONFIG_EC_EC_COMM_BATTERY
-int ec_ec_master_base_get_dynamic_info(void)
-{
-	int ret;
-	struct {
-		struct {
-			struct ec_host_request4 head;
-			struct ec_params_battery_dynamic_info param;
-			uint8_t crc8;
-		} req;
-		struct {
-			struct ec_host_response4 head;
-			struct ec_response_battery_dynamic_info info;
-			uint8_t crc8;
-		} resp;
-	} __packed data;
-
-	data.req.param.index = 0;
-
-	ret = write_command(EC_CMD_BATTERY_GET_DYNAMIC,
-			(void *)&data, sizeof(data.req.param),
-			sizeof(data.resp.info), 15 * MSEC);
-	ret = handle_error(__func__, ret, data.resp.head.result);
-	if (ret != EC_RES_SUCCESS)
-		return ret;
-
-#ifdef EXTRA_DEBUG
-	CPRINTF("V:          %d mV\n", data.resp.info.actual_voltage);
-	CPRINTF("I:          %d mA\n", data.resp.info.actual_current);
-	CPRINTF("Remaining:  %d mAh\n", data.resp.info.remaining_capacity);
-	CPRINTF("Cap-full:   %d mAh\n", data.resp.info.full_capacity);
-	CPRINTF("Flags:      %04x\n", data.resp.info.flags);
-	CPRINTF("V-desired:  %d mV\n", data.resp.info.desired_voltage);
-	CPRINTF("I-desired:  %d mA\n", data.resp.info.desired_current);
-#endif
-
-	memcpy(&battery_dynamic[BATT_IDX_BASE], &data.resp.info,
-				sizeof(battery_dynamic[BATT_IDX_BASE]));
-	return EC_RES_SUCCESS;
-}
-
-int ec_ec_master_base_get_static_info(void)
-{
-	int ret;
-	struct {
-		struct {
-			struct ec_host_request4 head;
-			struct ec_params_battery_static_info param;
-			uint8_t crc8;
-		} req;
-		struct {
-			struct ec_host_response4 head;
-			struct ec_response_battery_static_info info;
-			uint8_t crc8;
-		} resp;
-	} __packed data;
-
-	data.req.param.index = 0;
-
-	ret = write_command(EC_CMD_BATTERY_GET_STATIC,
-			(void *)&data, sizeof(data.req.param),
-			sizeof(data.resp.info), 15 * MSEC);
-	ret = handle_error(__func__, ret, data.resp.head.result);
-	if (ret != EC_RES_SUCCESS)
-		return ret;
-
-#ifdef EXTRA_DEBUG
-	CPRINTF("Cap-design: %d mAh\n", data.resp.info.design_capacity);
-	CPRINTF("V-design:   %d mV\n", data.resp.info.design_voltage);
-	CPRINTF("Manuf:      %s\n", data.resp.info.manufacturer);
-	CPRINTF("Model:      %s\n", data.resp.info.model);
-	CPRINTF("Serial:     %s\n", data.resp.info.serial);
-	CPRINTF("Type:       %s\n", data.resp.info.type);
-	CPRINTF("C-count:    %d\n", data.resp.info.cycle_count);
-#endif
-
-	memcpy(&battery_static[BATT_IDX_BASE], &data.resp.info,
-				sizeof(battery_static[BATT_IDX_BASE]));
-	return EC_RES_SUCCESS;
-}
-
-int ec_ec_master_base_charge_control(int max_current,
-				     int otg_voltage,
-				     int allow_charging)
-{
-	int ret;
-	struct {
-		struct {
-			struct ec_host_request4 head;
-			struct ec_params_charger_control ctrl;
-			uint8_t crc8;
-		} req;
-		struct {
-			struct ec_host_response4 head;
-		} resp;
-	} __packed data;
-
-	data.req.ctrl.allow_charging = allow_charging;
-	data.req.ctrl.max_current = max_current;
-	data.req.ctrl.otg_voltage = otg_voltage;
-
-	ret = write_command(EC_CMD_CHARGER_CONTROL,
-		(void *)&data, sizeof(data.req.ctrl), 0, 30 * MSEC);
-
-	return handle_error(__func__, ret, data.resp.head.result);
-}
-
-int ec_ec_master_hibernate(void)
-{
-	int ret;
-	struct {
-		struct {
-			struct ec_host_request4 head;
-			struct ec_params_reboot_ec param;
-		} req;
-		struct {
-			struct ec_host_response4 head;
-		} resp;
-	} __packed data;
-
-	data.req.param.cmd = EC_REBOOT_HIBERNATE;
-	data.req.param.flags = 0;
-
-	ret = write_command(EC_CMD_REBOOT_EC,
-		(void *)&data, sizeof(data.req.param), 0, 30 * MSEC);
-
-	return handle_error(__func__, ret, data.resp.head.result);
-}
-#endif /* CONFIG_EC_EC_COMM_BATTERY */
diff --git a/common/ec_ec_comm_server.c b/common/ec_ec_comm_server.c
new file mode 100644
index 0000000000..3c83253138
--- /dev/null
+++ b/common/ec_ec_comm_server.c
@@ -0,0 +1,323 @@
+/* Copyright 2017 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * EC-EC communication, task and functions for server.
+ */
+
+#include "battery.h"
+#include "charge_state.h"
+#include "common.h"
+#include "console.h"
+#include "crc8.h"
+#include "ec_commands.h"
+#include "ec_ec_comm_server.h"
+#include "extpower.h"
+#include "hooks.h"
+#include "hwtimer.h"
+#include "queue.h"
+#include "queue_policies.h"
+#include "system.h"
+#include "task.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/* Print extra debugging information */
+#undef EXTRA_DEBUG
+
+/* Set if the client allows the server to charge the battery. */
+static int charging_allowed;
+
+/*
+ * Our command parameter buffer must be big enough to fit any command
+ * parameter, and crc byte.
+ */
+#define LARGEST_PARAMS_SIZE 8
+
+BUILD_ASSERT(LARGEST_PARAMS_SIZE >=
+	     sizeof(struct ec_params_battery_static_info));
+BUILD_ASSERT(LARGEST_PARAMS_SIZE >=
+	     sizeof(struct ec_params_battery_dynamic_info));
+BUILD_ASSERT(LARGEST_PARAMS_SIZE >= sizeof(struct ec_params_charger_control));
+
+#define COMMAND_BUFFER_PARAMS_SIZE (LARGEST_PARAMS_SIZE + 1)
+
+/*
+ * Maximum time needed to read a full command, commands are at most 17 bytes, so
+ * should not take more than 2ms to be sent at 115200 bps.
+ */
+#define COMMAND_TIMEOUT_US (5 * MSEC)
+
+void ec_ec_comm_server_written(struct consumer const *consumer, size_t count)
+{
+	task_wake(TASK_ID_ECCOMM);
+}
+
+/*
+ * Discard all data from the input queue.
+ *
+ * Note that we always sleep for 1ms after clearing the queue, to make sure
+ * that we give enough time for the next byte to arrive.
+ */
+static void discard_queue(void)
+{
+	do {
+		queue_advance_head(&ec_ec_comm_server_input,
+				   queue_count(&ec_ec_comm_server_input));
+		usleep(1 * MSEC);
+	} while (queue_count(&ec_ec_comm_server_input) > 0);
+}
+
+/* Write response to client. */
+static void write_response(uint16_t res, int seq, const void *data, int len)
+{
+	struct ec_host_response4 header;
+	uint8_t crc;
+
+	header.fields0 = 4 | /* version */
+			 EC_PACKET4_0_IS_RESPONSE_MASK | /* is_response */
+			 (seq << EC_PACKET4_0_SEQ_NUM_SHIFT); /* seq_num */
+	/* Set data_crc_present if there is data */
+	header.fields1 = (len > 0) ? EC_PACKET4_1_DATA_CRC_PRESENT_MASK : 0;
+	header.result = res;
+	header.data_len = len;
+	header.reserved = 0;
+	header.header_crc = cros_crc8((uint8_t *)&header, sizeof(header) - 1);
+	QUEUE_ADD_UNITS(&ec_ec_comm_server_output, (uint8_t *)&header,
+			sizeof(header));
+
+	if (len > 0) {
+		QUEUE_ADD_UNITS(&ec_ec_comm_server_output, data, len);
+		crc = cros_crc8(data, len);
+		QUEUE_ADD_UNITS(&ec_ec_comm_server_output, &crc, sizeof(crc));
+	}
+}
+
+/*
+ * Read len bytes into buffer. Waiting up to COMMAND_TIMEOUT_US after start.
+ *
+ * Returns EC_SUCCESS or EC_ERROR_TIMEOUT.
+ */
+static int read_data(void *buffer, size_t len, uint32_t start)
+{
+	uint32_t delta;
+
+	while (queue_count(&ec_ec_comm_server_input) < len) {
+		delta = __hw_clock_source_read() - start;
+		if (delta >= COMMAND_TIMEOUT_US)
+			return EC_ERROR_TIMEOUT;
+
+		/* Every incoming byte wakes the task. */
+		task_wait_event(COMMAND_TIMEOUT_US - delta);
+	}
+
+	/* Fetch header */
+	QUEUE_REMOVE_UNITS(&ec_ec_comm_server_input, buffer, len);
+
+	return EC_SUCCESS;
+}
+
+static void handle_cmd_reboot_ec(const struct ec_params_reboot_ec *params,
+				 int data_len, int seq)
+{
+	int ret = EC_RES_SUCCESS;
+
+	if (data_len != sizeof(*params)) {
+		ret = EC_RES_INVALID_COMMAND;
+		goto out;
+	}
+
+	/* Only handle hibernate */
+	if (params->cmd != EC_REBOOT_HIBERNATE) {
+		ret = EC_RES_INVALID_PARAM;
+		goto out;
+	}
+
+	CPRINTS("Hibernating...");
+
+	system_hibernate(0, 0);
+	/* We should not be able to write back the response. */
+
+out:
+	write_response(ret, seq, NULL, 0);
+}
+
+#ifdef CONFIG_EC_EC_COMM_BATTERY
+static void
+handle_cmd_charger_control(const struct ec_params_charger_control *params,
+			   int data_len, int seq)
+{
+	int ret = EC_RES_SUCCESS;
+	int prev_charging_allowed = charging_allowed;
+
+	if (data_len != sizeof(*params)) {
+		ret = EC_RES_INVALID_COMMAND;
+		goto out;
+	}
+
+	if (params->max_current >= 0) {
+		charge_set_output_current_limit(CHARGER_SOLO, 0, 0);
+		charge_set_input_current_limit(
+			MIN(MAX_CURRENT_MA, params->max_current), 0);
+		charging_allowed = params->allow_charging;
+	} else {
+		if (-params->max_current > MAX_OTG_CURRENT_MA ||
+		    params->otg_voltage > MAX_OTG_VOLTAGE_MV) {
+			ret = EC_RES_INVALID_PARAM;
+			goto out;
+		}
+
+		/* Reset input current to default. */
+		charge_set_input_current_limit(
+			CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT, 0);
+		/* Setup and enable "OTG". */
+		charge_set_output_current_limit(CHARGER_SOLO,
+						-params->max_current,
+						params->otg_voltage);
+		charging_allowed = 0;
+	}
+
+	if (prev_charging_allowed != charging_allowed)
+		hook_notify(HOOK_AC_CHANGE);
+
+out:
+	write_response(ret, seq, NULL, 0);
+}
+
+/*
+ * On dual-battery server, we use the charging allowed signal from client to
+ * indicate whether external power is present.
+ *
+ * In most cases, this actually matches the external power status of the client
+ * (server battery charging when AC is connected, or discharging when server
+ * battery still has enough capacity), with one exception: when we do client to
+ * server battery charging (in this case the "external" power is the client).
+ */
+int extpower_is_present(void)
+{
+	return charging_allowed;
+}
+#endif
+
+void ec_ec_comm_server_task(void *u)
+{
+	struct ec_host_request4 header;
+	/*
+	 * If CONFIG_HOSTCMD_ALIGNED is set, it is important that params is
+	 * aligned on a 32-bit boundary.
+	 */
+	uint8_t __aligned(4) params[COMMAND_BUFFER_PARAMS_SIZE];
+	unsigned int len, seq = 0, hascrc, cmdver;
+	uint32_t start;
+
+	while (1) {
+		task_wait_event(-1);
+
+		if (queue_count(&ec_ec_comm_server_input) == 0)
+			continue;
+
+		/* We got some data, start timeout counter. */
+		start = __hw_clock_source_read();
+
+		/* Wait for whole header to be available and read it. */
+		if (read_data(&header, sizeof(header), start)) {
+			CPRINTS("%s timeout (header)", __func__);
+			goto discard;
+		}
+
+#ifdef EXTRA_DEBUG
+		CPRINTS("%s f0=%02x f1=%02x cmd=%02x, length=%d", __func__,
+			header.fields0, header.fields1, header.command,
+			header.data_len);
+#endif
+
+		/* Ignore response (we wrote that ourselves) */
+		if (header.fields0 & EC_PACKET4_0_IS_RESPONSE_MASK)
+			goto discard;
+
+		/* Validate version and crc. */
+		if ((header.fields0 & EC_PACKET4_0_STRUCT_VERSION_MASK) != 4 ||
+		    header.header_crc !=
+			    cros_crc8((uint8_t *)&header, sizeof(header) - 1)) {
+			CPRINTS("%s header/crc error", __func__);
+			goto discard;
+		}
+
+		len = header.data_len;
+		hascrc = header.fields1 & EC_PACKET4_1_DATA_CRC_PRESENT_MASK;
+		if (hascrc)
+			len += 1;
+
+		/*
+		 * Ignore commands that are too long to fit in our buffer.
+		 */
+		if (len > sizeof(params)) {
+			CPRINTS("%s len error (%d)", __func__, len);
+			/* Discard the data first, then write error back. */
+			discard_queue();
+			write_response(EC_RES_OVERFLOW, seq, NULL, 0);
+			goto discard;
+		}
+
+		seq = (header.fields0 & EC_PACKET4_0_SEQ_NUM_MASK) >>
+		      EC_PACKET4_0_SEQ_NUM_SHIFT;
+
+		cmdver = header.fields1 & EC_PACKET4_1_COMMAND_VERSION_MASK;
+
+		/* Wait for the rest of the data to be available and read it. */
+		if (read_data(params, len, start)) {
+			CPRINTS("%s timeout (data)", __func__);
+			goto discard;
+		}
+
+		/* Check data CRC */
+		if (hascrc && params[len - 1] != cros_crc8(params, len - 1)) {
+			CPRINTS("%s data crc error", __func__);
+			write_response(EC_RES_INVALID_CHECKSUM, seq, NULL, 0);
+			goto discard;
+		}
+
+		/* For now, all commands have version 0. */
+		if (cmdver != 0) {
+			CPRINTS("%s bad command version", __func__);
+			write_response(EC_RES_INVALID_VERSION, seq, NULL, 0);
+			continue;
+		}
+
+		switch (header.command) {
+#ifdef CONFIG_EC_EC_COMM_BATTERY
+		case EC_CMD_BATTERY_GET_STATIC:
+			/* Note that we ignore the battery index parameter. */
+			write_response(EC_RES_SUCCESS, seq,
+				       &battery_static[BATT_IDX_MAIN],
+				       sizeof(battery_static[BATT_IDX_MAIN]));
+			break;
+		case EC_CMD_BATTERY_GET_DYNAMIC:
+			/* Note that we ignore the battery index parameter. */
+			write_response(EC_RES_SUCCESS, seq,
+				       &battery_dynamic[BATT_IDX_MAIN],
+				       sizeof(battery_dynamic[BATT_IDX_MAIN]));
+			break;
+		case EC_CMD_CHARGER_CONTROL:
+			handle_cmd_charger_control((void *)params,
+						   header.data_len, seq);
+			break;
+#endif
+		case EC_CMD_REBOOT_EC:
+			handle_cmd_reboot_ec((void *)params, header.data_len,
+					     seq);
+			break;
+		default:
+			write_response(EC_RES_INVALID_COMMAND, seq, NULL, 0);
+		}
+
+		continue;
+	discard:
+		/*
+		 * Some error occurred: discard all data in the queue.
+		 */
+		discard_queue();
+	}
+}
diff --git a/common/ec_ec_comm_slave.c b/common/ec_ec_comm_slave.c
deleted file mode 100644
index ae845d58bc..0000000000
--- a/common/ec_ec_comm_slave.c
+++ /dev/null
@@ -1,328 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * EC-EC communication, task and functions for slave.
- */
-
-#include "common.h"
-#include "battery.h"
-#include "charge_state_v2.h"
-#include "console.h"
-#include "crc8.h"
-#include "ec_commands.h"
-#include "ec_ec_comm_slave.h"
-#include "extpower.h"
-#include "hwtimer.h"
-#include "hooks.h"
-#include "queue.h"
-#include "queue_policies.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-/* Print extra debugging information */
-#undef EXTRA_DEBUG
-
-/* Set if the master allows the slave to charge the battery. */
-static int charging_allowed;
-
-/*
- * Our command parameter buffer must be big enough to fit any command
- * parameter, and crc byte.
- */
-#define LARGEST_PARAMS_SIZE 8
-
-BUILD_ASSERT(LARGEST_PARAMS_SIZE >=
-	sizeof(struct ec_params_battery_static_info));
-BUILD_ASSERT(LARGEST_PARAMS_SIZE >=
-	sizeof(struct ec_params_battery_dynamic_info));
-BUILD_ASSERT(LARGEST_PARAMS_SIZE >=
-	sizeof(struct ec_params_charger_control));
-
-#define COMMAND_BUFFER_PARAMS_SIZE (LARGEST_PARAMS_SIZE + 1)
-
-/*
- * Maximum time needed to read a full command, commands are at most 17 bytes, so
- * should not take more than 2ms to be sent at 115200 bps.
- */
-#define COMMAND_TIMEOUT_US (5 * MSEC)
-
-
-void ec_ec_comm_slave_written(struct consumer const *consumer, size_t count)
-{
-	task_wake(TASK_ID_ECCOMM);
-}
-
-/*
- * Discard all data from the input queue.
- *
- * Note that we always sleep for 1ms after clearing the queue, to make sure
- * that we give enough time for the next byte to arrive.
- */
-static void discard_queue(void)
-{
-	do {
-		queue_advance_head(&ec_ec_comm_slave_input,
-				queue_count(&ec_ec_comm_slave_input));
-		usleep(1 * MSEC);
-	} while (queue_count(&ec_ec_comm_slave_input) > 0);
-}
-
-/* Write response to master. */
-static void write_response(uint16_t res, int seq, const void *data, int len)
-{
-	struct ec_host_response4 header;
-	uint8_t crc;
-
-	header.fields0 =
-		4 | /* version */
-		EC_PACKET4_0_IS_RESPONSE_MASK | /* is_response */
-		(seq << EC_PACKET4_0_SEQ_NUM_SHIFT); /* seq_num */
-	/* Set data_crc_present if there is data */
-	header.fields1 = (len > 0) ? EC_PACKET4_1_DATA_CRC_PRESENT_MASK : 0;
-	header.result = res;
-	header.data_len = len;
-	header.reserved = 0;
-	header.header_crc =
-		crc8((uint8_t *)&header, sizeof(header)-1);
-	QUEUE_ADD_UNITS(&ec_ec_comm_slave_output,
-			(uint8_t *)&header, sizeof(header));
-
-	if (len > 0) {
-		QUEUE_ADD_UNITS(&ec_ec_comm_slave_output, data, len);
-		crc = crc8(data, len);
-		QUEUE_ADD_UNITS(&ec_ec_comm_slave_output, &crc, sizeof(crc));
-	}
-}
-
-/*
- * Read len bytes into buffer. Waiting up to COMMAND_TIMEOUT_US after start.
- *
- * Returns EC_SUCCESS or EC_ERROR_TIMEOUT.
- */
-static int read_data(void *buffer, size_t len, uint32_t start)
-{
-	uint32_t delta;
-
-	while (queue_count(&ec_ec_comm_slave_input) < len) {
-		delta = __hw_clock_source_read() - start;
-		if (delta >= COMMAND_TIMEOUT_US)
-			return EC_ERROR_TIMEOUT;
-
-		/* Every incoming byte wakes the task. */
-		task_wait_event(COMMAND_TIMEOUT_US - delta);
-	}
-
-	/* Fetch header */
-	QUEUE_REMOVE_UNITS(&ec_ec_comm_slave_input, buffer, len);
-
-	return EC_SUCCESS;
-}
-
-static void handle_cmd_reboot_ec(
-	const struct ec_params_reboot_ec *params,
-	int data_len, int seq)
-{
-	int ret = EC_RES_SUCCESS;
-
-	if (data_len != sizeof(*params)) {
-		ret = EC_RES_INVALID_COMMAND;
-		goto out;
-	}
-
-	/* Only handle hibernate */
-	if (params->cmd != EC_REBOOT_HIBERNATE) {
-		ret = EC_RES_INVALID_PARAM;
-		goto out;
-	}
-
-	CPRINTS("Hibernating...");
-
-	system_hibernate(0, 0);
-	/* We should not be able to write back the response. */
-
-out:
-	write_response(ret, seq, NULL, 0);
-}
-
-#ifdef CONFIG_EC_EC_COMM_BATTERY
-static void handle_cmd_charger_control(
-	const struct ec_params_charger_control *params,
-	int data_len, int seq)
-{
-	int ret = EC_RES_SUCCESS;
-	int prev_charging_allowed = charging_allowed;
-
-	if (data_len != sizeof(*params)) {
-		ret = EC_RES_INVALID_COMMAND;
-		goto out;
-	}
-
-	if (params->max_current >= 0) {
-		charge_set_output_current_limit(CHARGER_SOLO, 0, 0);
-		charge_set_input_current_limit(
-			MIN(MAX_CURRENT_MA, params->max_current), 0);
-		charging_allowed = params->allow_charging;
-	} else {
-		if (-params->max_current > MAX_OTG_CURRENT_MA ||
-				params->otg_voltage > MAX_OTG_VOLTAGE_MV) {
-			ret = EC_RES_INVALID_PARAM;
-			goto out;
-		}
-
-		/* Reset input current to minimum. */
-		charge_set_input_current_limit(CONFIG_CHARGER_INPUT_CURRENT, 0);
-		/* Setup and enable "OTG". */
-		charge_set_output_current_limit(CHARGER_SOLO,
-						-params->max_current,
-						params->otg_voltage);
-		charging_allowed = 0;
-	}
-
-	if (prev_charging_allowed != charging_allowed)
-		hook_notify(HOOK_AC_CHANGE);
-
-out:
-	write_response(ret, seq, NULL, 0);
-}
-
-/*
- * On dual-battery slave, we use the charging allowed signal from master to
- * indicate whether external power is present.
- *
- * In most cases, this actually matches the external power status of the master
- * (slave battery charging when AC is connected, or discharging when slave
- * battery still has enough capacity), with one exception: when we do master to
- * slave battery charging (in this case the "external" power is the master).
- */
-int extpower_is_present(void)
-{
-	return charging_allowed;
-}
-#endif
-
-void ec_ec_comm_slave_task(void *u)
-{
-	struct ec_host_request4 header;
-	/*
-	 * If CONFIG_HOSTCMD_ALIGNED is set, it is important that params is
-	 * aligned on a 32-bit boundary.
-	 */
-	uint8_t __aligned(4) params[COMMAND_BUFFER_PARAMS_SIZE];
-	unsigned int len, seq = 0, hascrc, cmdver;
-	uint32_t start;
-
-	while (1) {
-		task_wait_event(-1);
-
-		if (queue_count(&ec_ec_comm_slave_input) == 0)
-			continue;
-
-		/* We got some data, start timeout counter. */
-		start = __hw_clock_source_read();
-
-		/* Wait for whole header to be available and read it. */
-		if (read_data(&header, sizeof(header), start)) {
-			CPRINTS("%s timeout (header)", __func__);
-			goto discard;
-		}
-
-#ifdef EXTRA_DEBUG
-		CPRINTS("%s f0=%02x f1=%02x cmd=%02x, length=%d", __func__,
-			header.fields0, header.fields1,
-			header.command, header.data_len);
-#endif
-
-		/* Ignore response (we wrote that ourselves) */
-		if (header.fields0 & EC_PACKET4_0_IS_RESPONSE_MASK)
-			goto discard;
-
-		/* Validate version and crc. */
-		if ((header.fields0 & EC_PACKET4_0_STRUCT_VERSION_MASK) != 4 ||
-			   header.header_crc !=
-				crc8((uint8_t *)&header, sizeof(header)-1)) {
-			CPRINTS("%s header/crc error", __func__);
-			goto discard;
-		}
-
-		len = header.data_len;
-		hascrc = header.fields1 & EC_PACKET4_1_DATA_CRC_PRESENT_MASK;
-		if (hascrc)
-			len += 1;
-
-		/*
-		 * Ignore commands that are too long to fit in our buffer.
-		 */
-		if (len > sizeof(params)) {
-			CPRINTS("%s len error (%d)", __func__, len);
-			/* Discard the data first, then write error back. */
-			discard_queue();
-			write_response(EC_RES_OVERFLOW, seq, NULL, 0);
-			goto discard;
-		}
-
-		seq = (header.fields0 & EC_PACKET4_0_SEQ_NUM_MASK) >>
-			EC_PACKET4_0_SEQ_NUM_SHIFT;
-
-		cmdver = header.fields1 & EC_PACKET4_1_COMMAND_VERSION_MASK;
-
-		/* Wait for the rest of the data to be available and read it. */
-		if (read_data(params, len, start)) {
-			CPRINTS("%s timeout (data)", __func__);
-			goto discard;
-		}
-
-		/* Check data CRC */
-		if (hascrc && params[len-1] != crc8(params, len-1)) {
-			CPRINTS("%s data crc error", __func__);
-			write_response(EC_RES_INVALID_CHECKSUM, seq, NULL, 0);
-			goto discard;
-		}
-
-		/* For now, all commands have version 0. */
-		if (cmdver != 0) {
-			CPRINTS("%s bad command version", __func__);
-			write_response(EC_RES_INVALID_VERSION, seq, NULL, 0);
-			continue;
-		}
-
-		switch (header.command) {
-#ifdef CONFIG_EC_EC_COMM_BATTERY
-		case EC_CMD_BATTERY_GET_STATIC:
-			/* Note that we ignore the battery index parameter. */
-			write_response(EC_RES_SUCCESS, seq,
-				&battery_static[BATT_IDX_MAIN],
-				sizeof(battery_static[BATT_IDX_MAIN]));
-			break;
-		case EC_CMD_BATTERY_GET_DYNAMIC:
-			/* Note that we ignore the battery index parameter. */
-			write_response(EC_RES_SUCCESS, seq,
-				&battery_dynamic[BATT_IDX_MAIN],
-				sizeof(battery_dynamic[BATT_IDX_MAIN]));
-			break;
-		case EC_CMD_CHARGER_CONTROL:
-			handle_cmd_charger_control((void *)params,
-						header.data_len, seq);
-			break;
-#endif
-		case EC_CMD_REBOOT_EC:
-			handle_cmd_reboot_ec((void *)params,
-						header.data_len, seq);
-			break;
-		default:
-			write_response(EC_RES_INVALID_COMMAND, seq,
-				NULL, 0);
-		}
-
-		continue;
-discard:
-		/*
-		 * Some error occurred: discard all data in the queue.
-		 */
-		discard_queue();
-	}
-}
diff --git a/common/ec_features.c b/common/ec_features.c
index 5abe121591..9fb257d204 100644
--- a/common/ec_features.c
+++ b/common/ec_features.c
@@ -1,122 +1,125 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Present Chrome EC device features to the outside world */
 
+#include "board_config.h"
 #include "common.h"
 #include "config.h"
 #include "console.h"
 #include "ec_commands.h"
-#include "board_config.h"
+#include "motion_sense.h"
 
+/* LCOV_EXCL_START */
 uint32_t get_feature_flags0(void)
 {
 	uint32_t result = 0
 #ifdef CONFIG_FW_LIMITED_IMAGE
-		| EC_FEATURE_MASK_0(EC_FEATURE_LIMITED)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_LIMITED)
 #endif
-#ifdef CONFIG_FLASH
-		| EC_FEATURE_MASK_0(EC_FEATURE_FLASH)
+#ifdef CONFIG_FLASH_CROS
+			  | EC_FEATURE_MASK_0(EC_FEATURE_FLASH)
 #endif
 #ifdef CONFIG_FANS
-		| EC_FEATURE_MASK_0(EC_FEATURE_PWM_FAN)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_PWM_FAN)
 #endif
 #ifdef CONFIG_KEYBOARD_BACKLIGHT
-		| EC_FEATURE_MASK_0(EC_FEATURE_PWM_KEYB)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_PWM_KEYB)
 #endif
 #ifdef HAS_TASK_LIGHTBAR
-		| EC_FEATURE_MASK_0(EC_FEATURE_LIGHTBAR)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_LIGHTBAR)
 #endif
 #ifdef CONFIG_LED_COMMON
-		| EC_FEATURE_MASK_0(EC_FEATURE_LED)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_LED)
 #endif
 #ifdef HAS_TASK_MOTIONSENSE
-		| EC_FEATURE_MASK_0(EC_FEATURE_MOTION_SENSE)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_MOTION_SENSE)
 #endif
 #ifdef HAS_TASK_KEYSCAN
-		| EC_FEATURE_MASK_0(EC_FEATURE_KEYB)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_KEYB)
 #endif
 #ifdef CONFIG_PSTORE
-		| EC_FEATURE_MASK_0(EC_FEATURE_PSTORE)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_PSTORE)
 #endif
 #ifdef CONFIG_HOSTCMD_X86
-		| EC_FEATURE_MASK_0(EC_FEATURE_PORT80)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_PORT80)
 #endif
 #ifdef CONFIG_TEMP_SENSOR
-		| EC_FEATURE_MASK_0(EC_FEATURE_THERMAL)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_THERMAL)
 #endif
 #if (defined CONFIG_BACKLIGHT_LID) || (defined CONFIG_BACKLIGHT_REQ_GPIO)
-		| EC_FEATURE_MASK_0(EC_FEATURE_BKLIGHT_SWITCH)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_BKLIGHT_SWITCH)
 #endif
 #ifdef CONFIG_WIRELESS
-		| EC_FEATURE_MASK_0(EC_FEATURE_WIFI_SWITCH)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_WIFI_SWITCH)
 #endif
 #ifdef CONFIG_HOSTCMD_EVENTS
-		| EC_FEATURE_MASK_0(EC_FEATURE_HOST_EVENTS)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_HOST_EVENTS)
 #endif
 #ifdef CONFIG_COMMON_GPIO
-		| EC_FEATURE_MASK_0(EC_FEATURE_GPIO)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_GPIO)
 #endif
-#ifdef CONFIG_I2C_MASTER
-		| EC_FEATURE_MASK_0(EC_FEATURE_I2C)
+#ifdef CONFIG_I2C_CONTROLLER
+			  | EC_FEATURE_MASK_0(EC_FEATURE_I2C)
 #endif
 #ifdef CONFIG_CHARGER
-		| EC_FEATURE_MASK_0(EC_FEATURE_CHARGER)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_CHARGER)
 #endif
 #if (defined CONFIG_BATTERY)
-		| EC_FEATURE_MASK_0(EC_FEATURE_BATTERY)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_BATTERY)
 #endif
 #ifdef CONFIG_BATTERY_SMART
-		| EC_FEATURE_MASK_0(EC_FEATURE_SMART_BATTERY)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_SMART_BATTERY)
 #endif
 #ifdef CONFIG_AP_HANG_DETECT
-		| EC_FEATURE_MASK_0(EC_FEATURE_HANG_DETECT)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_HANG_DETECT)
 #endif
 #if 0
 		| EC_FEATURE_MASK_0(EC_FEATURE_PMU) /* Obsolete */
 #endif
 #ifdef CONFIG_HOSTCMD_PD
-		| EC_FEATURE_MASK_0(EC_FEATURE_SUB_MCU)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_SUB_MCU)
 #endif
-#ifdef CONFIG_CHARGE_MANAGER
-		| EC_FEATURE_MASK_0(EC_FEATURE_USB_PD)
+#if defined(CONFIG_CHARGE_MANAGER) && defined(CONFIG_USB_POWER_DELIVERY)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_USB_PD)
 #endif
 #ifdef CONFIG_ACCEL_FIFO
-		| EC_FEATURE_MASK_0(EC_FEATURE_MOTION_SENSE_FIFO)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_MOTION_SENSE_FIFO)
 #endif
 #ifdef CONFIG_VSTORE
-		| EC_FEATURE_MASK_0(EC_FEATURE_VSTORE)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_VSTORE)
 #endif
 #ifdef CONFIG_USB_MUX_VIRTUAL
-		| EC_FEATURE_MASK_0(EC_FEATURE_USBC_SS_MUX_VIRTUAL)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_USBC_SS_MUX_VIRTUAL)
 #endif
 #ifdef CONFIG_HOSTCMD_RTC
-		| EC_FEATURE_MASK_0(EC_FEATURE_RTC)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_RTC)
 #endif
 #ifdef CONFIG_SPI_FP_PORT
-		| EC_FEATURE_MASK_0(EC_FEATURE_FINGERPRINT)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_FINGERPRINT)
 #endif
 #ifdef HAS_TASK_CENTROIDING
-		| EC_FEATURE_MASK_0(EC_FEATURE_TOUCHPAD)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_TOUCHPAD)
 #endif
 #if defined(HAS_TASK_RWSIG) || defined(HAS_TASK_RWSIG_RO)
-		| EC_FEATURE_MASK_0(EC_FEATURE_RWSIG)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_RWSIG)
 #endif
 #ifdef CONFIG_DEVICE_EVENT
-		| EC_FEATURE_MASK_0(EC_FEATURE_DEVICE_EVENT)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_DEVICE_EVENT)
 #endif
 		;
 	return board_override_feature_flags0(result);
 }
+/* LCOV_EXCL_STOP */
 
+/* LCOV_EXCL_START */
 uint32_t get_feature_flags1(void)
 {
-	uint32_t result = EC_FEATURE_MASK_1(EC_FEATURE_UNIFIED_WAKE_MASKS)
-#ifdef CONFIG_HOST_EVENT64
-		| EC_FEATURE_MASK_1(EC_FEATURE_HOST_EVENT64)
-#endif
+	uint32_t result =
+		EC_FEATURE_MASK_1(EC_FEATURE_UNIFIED_WAKE_MASKS) |
+		EC_FEATURE_MASK_1(EC_FEATURE_HOST_EVENT64)
 #ifdef CONFIG_EXTERNAL_STORAGE
 		| EC_FEATURE_MASK_1(EC_FEATURE_EXEC_IN_RAM)
 #endif
@@ -127,7 +130,10 @@ uint32_t get_feature_flags1(void)
 		| EC_FEATURE_MASK_1(EC_FEATURE_MOTION_SENSE_TIGHT_TIMESTAMPS)
 #endif
 #if defined(CONFIG_LID_ANGLE) && defined(CONFIG_TABLET_MODE)
-		| EC_FEATURE_MASK_1(EC_FEATURE_REFINED_TABLET_MODE_HYSTERESIS)
+		| (sensor_board_is_lid_angle_available() ?
+			   EC_FEATURE_MASK_1(
+				   EC_FEATURE_REFINED_TABLET_MODE_HYSTERESIS) :
+			   0)
 #endif
 #ifdef CONFIG_VBOOT_EFS2
 		| EC_FEATURE_MASK_1(EC_FEATURE_EFS2)
@@ -137,10 +143,35 @@ uint32_t get_feature_flags1(void)
 #endif
 #ifdef CHIP_ISH
 		| EC_FEATURE_MASK_1(EC_FEATURE_ISH)
+#endif
+#ifdef CONFIG_USB_PD_TCPMV2
+		| EC_FEATURE_MASK_1(EC_FEATURE_TYPEC_CMD)
+#endif
+#ifdef CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
+		| EC_FEATURE_MASK_1(EC_FEATURE_TYPEC_REQUIRE_AP_MODE_ENTRY)
+#endif
+#ifdef CONFIG_USB_MUX_AP_ACK_REQUEST
+		| EC_FEATURE_MASK_1(EC_FEATURE_TYPEC_MUX_REQUIRE_AP_ACK)
+#endif
+#ifdef CONFIG_POWER_S4_RESIDENCY
+		| EC_FEATURE_MASK_1(EC_FEATURE_S4_RESIDENCY)
+#endif
+#ifdef CONFIG_USB_MUX_AP_CONTROL
+		| EC_FEATURE_MASK_1(EC_FEATURE_TYPEC_AP_MUX_SET)
+#endif
+#ifdef CONFIG_USB_PD_VDM_AP_CONTROL
+		| EC_FEATURE_MASK_1(EC_FEATURE_TYPEC_AP_VDM_SEND)
+#endif
+#ifdef CONFIG_SYSTEM_SAFE_MODE
+		| EC_FEATURE_MASK_1(EC_FEATURE_SYSTEM_SAFE_MODE)
+#endif
+#ifdef CONFIG_DEBUG_ASSERT_REBOOTS
+		| EC_FEATURE_MASK_1(EC_FEATURE_ASSERT_REBOOTS)
 #endif
 		;
 	return board_override_feature_flags1(result);
 }
+/* LCOV_EXCL_STOP */
 
 __overridable uint32_t board_override_feature_flags0(uint32_t flags0)
 {
@@ -152,7 +183,7 @@ __overridable uint32_t board_override_feature_flags1(uint32_t flags1)
 	return flags1;
 }
 
-static int cc_feat(int argc, char **argv)
+static int cc_feat(int argc, const char **argv)
 {
 	ccprintf(" 0-31: 0x%08x\n", get_feature_flags0());
 	ccprintf("32-63: 0x%08x\n", get_feature_flags1());
diff --git a/common/espi.c b/common/espi.c
index 0904f102d7..f57e13cf76 100644
--- a/common/espi.c
+++ b/common/espi.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,13 +6,12 @@
 /* eSPI common functionality for Chrome EC */
 
 #include "common.h"
+#include "espi.h"
 #include "gpio.h"
 #include "registers.h"
-#include "espi.h"
 #include "timer.h"
 #include "util.h"
 
-
 const char *espi_vw_names[] = {
 	"VW_SLP_S3_L",
 	"VW_SLP_S4_L",
@@ -26,7 +25,7 @@ const char *espi_vw_names[] = {
 	"VW_ERROR_FATAL",
 	"VW_ERROR_NON_FATAL",
 	/* Merge bit 3/0 into one signal. Need to set them simultaneously */
-	"VW_SLAVE_BTLD_STATUS_DONE",
+	"VW_PERIPHERAL_BTLD_STATUS_DONE",
 	"VW_SCI_L",
 	"VW_SMI_L",
 	"VW_RCIN_L",
@@ -41,7 +40,6 @@ const char *espi_vw_names[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(espi_vw_names) == VW_SIGNAL_COUNT);
 
-
 const char *espi_vw_get_wire_name(enum espi_vw_signal signal)
 {
 	if (espi_signal_is_vw(signal))
@@ -50,7 +48,6 @@ const char *espi_vw_get_wire_name(enum espi_vw_signal signal)
 	return NULL;
 }
 
-
 int espi_signal_is_vw(int signal)
 {
 	return ((signal >= VW_SIGNAL_START) && (signal < VW_SIGNAL_END));
diff --git a/common/event_log.c b/common/event_log.c
index 994967664c..f748b3d9a7 100644
--- a/common/event_log.c
+++ b/common/event_log.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,9 +13,9 @@
 
 /* Event log FIFO */
 #define UNIT_SIZE sizeof(struct event_log_entry)
-#define UNIT_COUNT (CONFIG_EVENT_LOG_SIZE/UNIT_SIZE)
-#define UNIT_COUNT_MASK		(UNIT_COUNT - 1)
-static struct event_log_entry __bss_slow log_events[UNIT_COUNT];
+#define UNIT_COUNT (CONFIG_EVENT_LOG_SIZE / UNIT_SIZE)
+#define UNIT_COUNT_MASK (UNIT_COUNT - 1)
+static struct event_log_entry log_events[UNIT_COUNT];
 BUILD_ASSERT(POWER_OF_TWO(UNIT_COUNT));
 
 /*
@@ -42,31 +42,32 @@ static size_t log_tail;
 static size_t log_tail_next;
 
 /* Size of one FIFO entry */
-#define ENTRY_SIZE(payload_sz) (1+DIV_ROUND_UP((payload_sz), UNIT_SIZE))
+#define ENTRY_SIZE(payload_sz) (1 + DIV_ROUND_UP((payload_sz), UNIT_SIZE))
 
-void log_add_event(uint8_t type, uint8_t size, uint16_t data,
-			  void *payload, uint32_t timestamp)
+void log_add_event(uint8_t type, uint8_t size, uint16_t data, void *payload,
+		   uint32_t timestamp)
 {
 	struct event_log_entry *r;
 	size_t payload_size = EVENT_LOG_SIZE(size);
 	size_t total_size = ENTRY_SIZE(payload_size);
 	size_t current_tail, first;
+	uint32_t lock_key;
 
 	/* --- critical section : reserve queue space --- */
-	interrupt_disable();
+	lock_key = irq_lock();
 	current_tail = log_tail_next;
 	log_tail_next = current_tail + total_size;
-	interrupt_enable();
+	irq_unlock(lock_key);
 	/* --- end of critical section --- */
 
 	/* Out of space : discard the oldest entry */
 	while ((UNIT_COUNT - (current_tail - log_head)) < total_size) {
 		struct event_log_entry *oldest;
 		/* --- critical section : atomically free-up space --- */
-		interrupt_disable();
+		lock_key = irq_lock();
 		oldest = log_events + (log_head & UNIT_COUNT_MASK);
 		log_head += ENTRY_SIZE(EVENT_LOG_SIZE(oldest->size));
-		interrupt_enable();
+		irq_unlock(lock_key);
 		/* --- end of critical section --- */
 	}
 
@@ -77,13 +78,13 @@ void log_add_event(uint8_t type, uint8_t size, uint16_t data,
 	r->size = size;
 	r->data = data;
 	/* copy the payload into the FIFO */
-	first = MIN(total_size - 1, (UNIT_COUNT -
-		    (current_tail & UNIT_COUNT_MASK)) - 1);
+	first = MIN(total_size - 1,
+		    (UNIT_COUNT - (current_tail & UNIT_COUNT_MASK)) - 1);
 	if (first)
 		memcpy(r->payload, payload, first * UNIT_SIZE);
 	if (first < total_size - 1)
 		memcpy(log_events, ((uint8_t *)payload) + first * UNIT_SIZE,
-			(total_size - first) * UNIT_SIZE);
+		       (total_size - first) * UNIT_SIZE);
 	/* mark the entry available in the queue if nobody is behind us */
 	if (current_tail == log_tail)
 		log_tail = log_tail_next;
@@ -95,6 +96,7 @@ int log_dequeue_event(struct event_log_entry *r)
 	unsigned int total_size, first;
 	struct event_log_entry *entry;
 	size_t current_head;
+	uint32_t lock_key;
 
 retry:
 	current_head = log_head;
@@ -110,16 +112,16 @@ int log_dequeue_event(struct event_log_entry *r)
 	first = MIN(total_size, UNIT_COUNT - (current_head & UNIT_COUNT_MASK));
 	memcpy(r, entry, first * UNIT_SIZE);
 	if (first < total_size)
-		memcpy(r + first, log_events, (total_size-first) * UNIT_SIZE);
+		memcpy(r + first, log_events, (total_size - first) * UNIT_SIZE);
 
 	/* --- critical section : remove the entry from the queue --- */
-	interrupt_disable();
+	lock_key = irq_lock();
 	if (log_head != current_head) { /* our entry was thrown away */
-		interrupt_enable();
+		irq_unlock(lock_key);
 		goto retry;
 	}
 	log_head += total_size;
-	interrupt_enable();
+	irq_unlock(lock_key);
 	/* --- end of critical section --- */
 
 	/* fixup the timestamp : number of milliseconds in the past */
@@ -132,10 +134,10 @@ int log_dequeue_event(struct event_log_entry *r)
 /*
  * Display TPM event logs.
  */
-static int command_dlog(int argc, char **argv)
+static int command_dlog(int argc, const char **argv)
 {
 	size_t log_cur;
-	const uint8_t * const log_events_end =
+	const uint8_t *const log_events_end =
 		(uint8_t *)&log_events[UNIT_COUNT];
 
 	if (argc > 1) {
@@ -162,7 +164,7 @@ static int command_dlog(int argc, char **argv)
 		log_cur += ENTRY_SIZE(payload_bytes);
 
 		ccprintf("%10d   %4d  0x%04X   %4d   ", r->timestamp, r->type,
-			r->data, payload_bytes);
+			 r->data, payload_bytes);
 
 		/* display payload if exists */
 		payload = r->payload;
@@ -177,8 +179,6 @@ static int command_dlog(int argc, char **argv)
 	}
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(dlog,
-			command_dlog,
-			"[clear]",
+DECLARE_CONSOLE_COMMAND(dlog, command_dlog, "[clear]",
 			"Display/clear TPM event logs");
 #endif
diff --git a/common/extpower_common.c b/common/extpower_common.c
index 453bab3a2c..9f0947a529 100644
--- a/common/extpower_common.c
+++ b/common/extpower_common.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,6 +7,10 @@
 #include "hooks.h"
 #include "host_command.h"
 
+__overridable void board_check_extpower(void)
+{
+}
+
 void extpower_handle_update(int is_present)
 {
 	uint8_t *memmap_batt_flags;
diff --git a/common/extpower_gpio.c b/common/extpower_gpio.c
index 4cdcb834f8..bfb9349e0e 100644
--- a/common/extpower_gpio.c
+++ b/common/extpower_gpio.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,7 +14,7 @@
 
 static int debounced_extpower_presence;
 
-int extpower_is_present(void)
+test_mockable int extpower_is_present(void)
 {
 	return debounced_extpower_presence;
 }
@@ -31,7 +31,6 @@ static void extpower_deferred(void)
 
 	debounced_extpower_presence = extpower_presence;
 	extpower_handle_update(extpower_presence);
-
 }
 DECLARE_DEFERRED(extpower_deferred);
 
@@ -39,7 +38,7 @@ void extpower_interrupt(enum gpio_signal signal)
 {
 	/* Trigger deferred notification of external power change */
 	hook_call_deferred(&extpower_deferred_data,
-			CONFIG_EXTPOWER_DEBOUNCE_MS * MSEC);
+			   CONFIG_EXTPOWER_DEBOUNCE_MS * MSEC);
 }
 
 static void extpower_init(void)
diff --git a/common/fan.c b/common/fan.c
index 398a149268..945c16952a 100644
--- a/common/fan.c
+++ b/common/fan.c
@@ -1,11 +1,11 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Basic Chrome OS fan control */
 
-#include "assert.h"
+#include "builtin/assert.h"
 #include "chipset.h"
 #include "common.h"
 #include "console.h"
@@ -56,22 +56,80 @@ void fan_set_count(int count)
  * Convert the percentage to a target RPM. We can't simply scale all
  * the way down to zero because most fans won't turn that slowly, so
  * we'll map [1,100] => [FAN_MIN,FAN_MAX], and [0] => "off".
-*/
-int fan_percent_to_rpm(int fan, int pct)
+ */
+int fan_percent_to_rpm(int fan_index, int temp_ratio)
 {
 	int rpm, max, min;
 
-	if (!pct) {
+	if (temp_ratio <= 0) {
 		rpm = 0;
 	} else {
-		min = fans[fan].rpm->rpm_min;
-		max = fans[fan].rpm->rpm_max;
-		rpm = ((pct - 1) * max + (100 - pct) * min) / 99;
+		min = fans[fan_index].rpm->rpm_min;
+		max = fans[fan_index].rpm->rpm_max;
+		rpm = ((temp_ratio - 1) * max + (100 - temp_ratio) * min) / 99;
+	}
+
+	return rpm;
+}
+#endif /* CONFIG_FAN_RPM_CUSTOM */
+
+int temp_ratio_to_rpm_hysteresis(const struct fan_step_1_1 *fan_table,
+				 int num_fan_levels, int fan_index,
+				 int temp_ratio, void (*on_change)(void))
+{
+	static int previous_temp_ratio;
+	const int previous_rpm = fan_get_rpm_target(FAN_CH(fan_index));
+	int rpm;
+
+	if (temp_ratio <= fan_table[0].decreasing_temp_ratio_threshold) {
+		rpm = 0;
+	} else if (previous_rpm == 0 &&
+		   temp_ratio < fan_table[0].increasing_temp_ratio_threshold) {
+		rpm = 0;
+	} else {
+		/*
+		 * Comparing temp_ratio and previous_temp_ratio, trichotomy:
+		 *  1. decreasing path. (check the decreasing threshold)
+		 *  2. increasing path. (check the increasing threshold)
+		 *  3. invariant path. (return the current RPM)
+		 */
+		if (temp_ratio < previous_temp_ratio) {
+			int i = num_fan_levels - 1;
+
+			while (i > 0 &&
+			       fan_table[i].decreasing_temp_ratio_threshold >=
+				       temp_ratio) {
+				i--;
+			}
+			rpm = fan_table[i].rpm;
+		} else if (temp_ratio > previous_temp_ratio) {
+			int i = 0;
+
+			while (i < num_fan_levels &&
+			       fan_table[i].increasing_temp_ratio_threshold <=
+				       temp_ratio) {
+				i++;
+			}
+			if (i > 0) {
+				i--;
+			}
+			rpm = fan_table[i].rpm;
+		} else {
+			rpm = previous_rpm;
+		}
+	}
+
+	previous_temp_ratio = temp_ratio;
+
+	if (rpm != previous_rpm) {
+		cprints(CC_THERMAL, "Setting fan %d RPM to %d", fan_index, rpm);
+		if (on_change) {
+			on_change();
+		}
 	}
 
 	return rpm;
 }
-#endif	/* CONFIG_FAN_RPM_CUSTOM */
 
 /* The thermal task will only call this function with pct in [0,100]. */
 test_mockable void fan_set_percent_needed(int fan, int pct)
@@ -94,8 +152,7 @@ test_mockable void fan_set_percent_needed(int fan, int pct)
 	/* If we want to turn and the fans are currently significantly below
 	 * the minimum turning speed, we should turn at least as fast as the
 	 * necessary start speed instead. */
-	if (new_rpm &&
-	    actual_rpm < fans[fan].rpm->rpm_min * 9 / 10 &&
+	if (new_rpm && actual_rpm < fans[fan].rpm->rpm_min * 9 / 10 &&
 	    new_rpm < fans[fan].rpm->rpm_start)
 		new_rpm = fans[fan].rpm->rpm_start;
 
@@ -137,7 +194,7 @@ static void set_duty_cycle(int fan, int percent)
 /*****************************************************************************/
 /* Console commands */
 
-static int cc_fanauto(int argc, char **argv)
+static int cc_fanauto(int argc, const char **argv)
 {
 	char *e;
 	int fan = 0;
@@ -157,8 +214,7 @@ static int cc_fanauto(int argc, char **argv)
 	set_thermal_control_enabled(fan, 1);
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(fanauto, cc_fanauto,
-			"{fan}",
+DECLARE_CONSOLE_COMMAND(fanauto, cc_fanauto, "{fan}",
 			"Enable thermal fan control");
 
 /* Return 0 for off, 1 for on, -1 for unknown */
@@ -176,28 +232,27 @@ static int is_powered(int fan)
 	return is_pgood;
 }
 
-static int cc_faninfo(int argc, char **argv)
+static int cc_faninfo(int argc, const char **argv)
 {
-	static const char * const human_status[] = {
-		"not spinning", "changing", "locked", "frustrated"
-	};
+	static const char *const human_status[] = { "not spinning", "changing",
+						    "locked", "frustrated" };
 	int tmp, is_pgood;
 	int fan;
 	char leader[20] = "";
 	for (fan = 0; fan < fan_count; fan++) {
 		if (fan_count > 1)
-			snprintf(leader, sizeof(leader), "Fan %d ", fan);
+			if (snprintf(leader, sizeof(leader), "Fan %d ", fan) <
+			    0)
+				leader[0] = '\0';
 		if (fan)
 			ccprintf("\n");
 		ccprintf("%sActual: %4d rpm\n", leader,
 			 fan_get_rpm_actual(FAN_CH(fan)));
 		ccprintf("%sTarget: %4d rpm\n", leader,
 			 fan_get_rpm_target(FAN_CH(fan)));
-		ccprintf("%sDuty:   %d%%\n", leader,
-			 fan_get_duty(FAN_CH(fan)));
+		ccprintf("%sDuty:   %d%%\n", leader, fan_get_duty(FAN_CH(fan)));
 		tmp = fan_get_status(FAN_CH(fan));
-		ccprintf("%sStatus: %d (%s)\n", leader,
-			 tmp, human_status[tmp]);
+		ccprintf("%sStatus: %d (%s)\n", leader, tmp, human_status[tmp]);
 		ccprintf("%sMode:   %s\n", leader,
 			 fan_get_rpm_mode(FAN_CH(fan)) ? "rpm" : "duty");
 		ccprintf("%sAuto:   %s\n", leader,
@@ -212,12 +267,11 @@ static int cc_faninfo(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(faninfo, cc_faninfo,
-			NULL,
-			"Print fan info");
+DECLARE_CONSOLE_COMMAND(faninfo, cc_faninfo, NULL, "Print fan info");
 
-static int cc_fanset(int argc, char **argv)
+static int cc_fanset(int argc, const char **argv)
 {
+	const char *rpm_str;
 	int rpm;
 	char *e;
 	int fan = 0;
@@ -228,22 +282,25 @@ static int cc_fanset(int argc, char **argv)
 	}
 
 	if (fan_count > 1) {
-		if (argc < 2) {
+		if (argc < 3) {
 			ccprintf("fan number is required as the first arg\n");
 			return EC_ERROR_PARAM_COUNT;
 		}
+	}
+
+	if (argc == 3) {
 		fan = strtoi(argv[1], &e, 0);
 		if (*e || fan >= fan_count)
 			return EC_ERROR_PARAM1;
-		argc--;
-		argv++;
-	}
-
-	if (argc < 2)
+		rpm_str = argv[2];
+	} else if (argc == 2) {
+		rpm_str = argv[1];
+	} else {
 		return EC_ERROR_PARAM_COUNT;
+	}
 
-	rpm = strtoi(argv[2], &e, 0);
-	if (*e == '%') {		/* Wait, that's a percentage */
+	rpm = strtoi(rpm_str, &e, 0);
+	if (*e == '%') { /* Wait, that's a percentage */
 		ccprintf("Fan rpm given as %d%%\n", rpm);
 		if (rpm < 0)
 			rpm = 0;
@@ -269,12 +326,12 @@ static int cc_fanset(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(fanset, cc_fanset,
-			"{fan} (rpm | pct%)",
+DECLARE_CONSOLE_COMMAND(fanset, cc_fanset, "[fan] (rpm | pct%)",
 			"Set fan speed");
 
-static int cc_fanduty(int argc, char **argv)
+static int cc_fanduty(int argc, const char **argv)
 {
+	const char *percent_str;
 	int percent = 0;
 	char *e;
 	int fan = 0;
@@ -285,21 +342,24 @@ static int cc_fanduty(int argc, char **argv)
 	}
 
 	if (fan_count > 1) {
-		if (argc < 2) {
+		if (argc < 3) {
 			ccprintf("fan number is required as the first arg\n");
 			return EC_ERROR_PARAM_COUNT;
 		}
+	}
+
+	if (argc == 3) {
 		fan = strtoi(argv[1], &e, 0);
 		if (*e || fan >= fan_count)
 			return EC_ERROR_PARAM1;
-		argc--;
-		argv++;
-	}
-
-	if (argc < 2)
+		percent_str = argv[2];
+	} else if (argc == 2) {
+		percent_str = argv[1];
+	} else {
 		return EC_ERROR_PARAM_COUNT;
+	}
 
-	percent = strtoi(argv[1], &e, 0);
+	percent = strtoi(percent_str, &e, 0);
 	if (*e)
 		return EC_ERROR_PARAM1;
 
@@ -308,8 +368,7 @@ static int cc_fanduty(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(fanduty, cc_fanduty,
-			"{fan} percent",
+DECLARE_CONSOLE_COMMAND(fanduty, cc_fanduty, "[fan] percent",
 			"Set fan duty cycle");
 
 /*****************************************************************************/
@@ -318,7 +377,7 @@ DECLARE_CONSOLE_COMMAND(fanduty, cc_fanduty,
 /* 0-100% if in duty mode. -1 if not */
 int dptf_get_fan_duty_target(void)
 {
-	int fan = 0;				/* TODO(crosbug.com/p/23803) */
+	int fan = 0; /* TODO(crosbug.com/p/23803) */
 
 	if (fan_count == 0)
 		return -1;
@@ -362,8 +421,7 @@ hc_pwm_get_fan_target_rpm(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_FAN_TARGET_RPM,
-		     hc_pwm_get_fan_target_rpm,
+DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_FAN_TARGET_RPM, hc_pwm_get_fan_target_rpm,
 		     EC_VER_MASK(0));
 
 static enum ec_status
@@ -391,7 +449,7 @@ hc_pwm_set_fan_target_rpm(struct host_cmd_handler_args *args)
 		return EC_RES_ERROR;
 
 	/* enable the fan if rpm is non-zero */
-	set_enabled(fan, (p_v1->rpm > 0) ? 1 :0);
+	set_enabled(fan, (p_v1->rpm > 0) ? 1 : 0);
 
 	set_thermal_control_enabled(fan, 0);
 	fan_set_rpm_mode(FAN_CH(fan), 1);
@@ -399,8 +457,7 @@ hc_pwm_set_fan_target_rpm(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_FAN_TARGET_RPM,
-		     hc_pwm_set_fan_target_rpm,
+DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_FAN_TARGET_RPM, hc_pwm_set_fan_target_rpm,
 		     EC_VER_MASK(0) | EC_VER_MASK(1));
 
 static enum ec_status hc_pwm_set_fan_duty(struct host_cmd_handler_args *args)
@@ -424,8 +481,7 @@ static enum ec_status hc_pwm_set_fan_duty(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_FAN_DUTY,
-		     hc_pwm_set_fan_duty,
+DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_FAN_DUTY, hc_pwm_set_fan_duty,
 		     EC_VER_MASK(0) | EC_VER_MASK(1));
 
 static enum ec_status
@@ -449,10 +505,8 @@ hc_thermal_auto_fan_ctrl(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_THERMAL_AUTO_FAN_CTRL,
-		     hc_thermal_auto_fan_ctrl,
-		     EC_VER_MASK(0)|EC_VER_MASK(1));
-
+DECLARE_HOST_COMMAND(EC_CMD_THERMAL_AUTO_FAN_CTRL, hc_thermal_auto_fan_ctrl,
+		     EC_VER_MASK(0) | EC_VER_MASK(1));
 
 /*****************************************************************************/
 /* Hooks */
@@ -463,18 +517,18 @@ DECLARE_HOST_COMMAND(EC_CMD_THERMAL_AUTO_FAN_CTRL,
  */
 BUILD_ASSERT(CONFIG_FANS <= EC_FAN_SPEED_ENTRIES);
 
-#define PWMFAN_SYSJUMP_TAG 0x5046  /* "PF" */
+#define PWMFAN_SYSJUMP_TAG 0x5046 /* "PF" */
 #define PWM_HOOK_VERSION 1
 /* Saved PWM state across sysjumps */
 struct pwm_fan_state {
 	/* TODO(crosbug.com/p/23530): Still treating all fans as one. */
 	uint16_t rpm;
-	uint8_t flag;	/* FAN_STATE_FLAG_* */
+	uint8_t flag; /* FAN_STATE_FLAG_* */
 };
 
 /* For struct pwm_fan_state.flag */
-#define FAN_STATE_FLAG_ENABLED	BIT(0)
-#define FAN_STATE_FLAG_THERMAL	BIT(1)
+#define FAN_STATE_FLAG_ENABLED BIT(0)
+#define FAN_STATE_FLAG_THERMAL BIT(1)
 
 static void pwm_fan_init(void)
 {
@@ -492,8 +546,8 @@ static void pwm_fan_init(void)
 		fan_channel_setup(FAN_CH(fan), fans[fan].conf->flags);
 
 	/* Restore previous state. */
-	prev = (const struct pwm_fan_state *)
-		system_get_jump_tag(PWMFAN_SYSJUMP_TAG, &version, &size);
+	prev = (const struct pwm_fan_state *)system_get_jump_tag(
+		PWMFAN_SYSJUMP_TAG, &version, &size);
 	if (prev && version == PWM_HOOK_VERSION && size == sizeof(*prev)) {
 		memcpy(&state, prev, sizeof(state));
 	} else {
@@ -505,7 +559,7 @@ static void pwm_fan_init(void)
 				state.flag & FAN_STATE_FLAG_ENABLED);
 		fan_set_rpm_target(FAN_CH(fan), state.rpm);
 		set_thermal_control_enabled(
-				fan, state.flag & FAN_STATE_FLAG_THERMAL);
+			fan, state.flag & FAN_STATE_FLAG_THERMAL);
 	}
 
 	/* Initialize memory-mapped data */
@@ -545,7 +599,7 @@ DECLARE_HOOK(HOOK_SECOND, pwm_fan_second, HOOK_PRIO_DEFAULT);
 
 static void pwm_fan_preserve_state(void)
 {
-	struct pwm_fan_state state = {0};
+	struct pwm_fan_state state = { 0 };
 	int fan = 0;
 
 	if (fan_count == 0)
@@ -558,8 +612,8 @@ static void pwm_fan_preserve_state(void)
 		state.flag |= FAN_STATE_FLAG_THERMAL;
 	state.rpm = fan_get_rpm_target(FAN_CH(fan));
 
-	system_add_jump_tag(PWMFAN_SYSJUMP_TAG, PWM_HOOK_VERSION,
-			    sizeof(state), &state);
+	system_add_jump_tag(PWMFAN_SYSJUMP_TAG, PWM_HOOK_VERSION, sizeof(state),
+			    &state);
 }
 DECLARE_HOOK(HOOK_SYSJUMP, pwm_fan_preserve_state, HOOK_PRIO_DEFAULT);
 
@@ -570,9 +624,11 @@ static void pwm_fan_control(int enable)
 	/* TODO(crosbug.com/p/23530): Still treating all fans as one. */
 	for (fan = 0; fan < fan_count; fan++) {
 		set_thermal_control_enabled(fan, enable);
-		fan_set_rpm_target(FAN_CH(fan), enable ?
-			fan_percent_to_rpm(FAN_CH(fan), CONFIG_FAN_INIT_SPEED) :
-			0);
+		fan_set_rpm_target(
+			FAN_CH(fan),
+			enable ? fan_percent_to_rpm(FAN_CH(fan),
+						    CONFIG_FAN_INIT_SPEED) :
+				 0);
 		set_enabled(fan, enable);
 	}
 }
diff --git a/common/firmware_image.S b/common/firmware_image.S
index b7d0c0d19a..cc9034b89d 100644
--- a/common/firmware_image.S
+++ b/common/firmware_image.S
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -21,6 +21,9 @@
 #define FW_IMAGE_SIGN(sect,suffix) \
 	STRINGIFY(FW_FILE(FINAL_OUTDIR,PROJECT,sect,suffix,.sig))
 
+.global _start
+_start:
+
 /* Read Only firmware */
 #ifdef CONFIG_FW_INCLUDE_RO
 .section .image.RO, "ax"
@@ -58,6 +61,11 @@
 .incbin FW_IMAGE_SIGN(RW,)
 #endif
 
+#ifdef CONFIG_IPI
+.section .ipi_buffer, "aw"
+.space (CONFIG_IPC_SHARED_OBJ_BUF_SIZE + 8) * 2, 0
+#endif
+
 #ifdef CONFIG_DRAM_BASE
 /* Read Write firmware in DRAM */
 .section .image.RW.dram, "ax"
diff --git a/common/firmware_image.lds.S b/common/firmware_image.lds.S
index 7522cf792a..e62818eebb 100644
--- a/common/firmware_image.lds.S
+++ b/common/firmware_image.lds.S
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,6 +22,17 @@
 		       CONFIG_RW_B_STORAGE_OFF)
 
 #elif (CONFIG_RO_MEM_OFF == CONFIG_RW_MEM_OFF)
+
+#ifdef CONFIG_PROGRAM_MEMORY_BASE_LOAD
+
+#define IMAGE_RO_AT (CONFIG_PROGRAM_MEMORY_BASE_LOAD + CONFIG_RO_MEM_OFF)
+#define IMAGE_RW_AT (CONFIG_PROGRAM_MEMORY_BASE_LOAD + \
+		     CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
+#define IMAGE_RW_B_AT (CONFIG_PROGRAM_MEMORY_BASE_LOAD + \
+		       CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE + CONFIG_RW_SIZE)
+
+#else
+
 #define IMAGE_RO_AT (CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RO_MEM_OFF)
 /* This is applicable to ECs in which RO and RW execution is
 mapped to the same location but we still have to generate an ec.bin with RO
@@ -31,26 +42,49 @@ and RW images at different Flash offset */
 #define IMAGE_RW_B_AT (CONFIG_PROGRAM_MEMORY_BASE + \
 		       CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE + CONFIG_RW_SIZE)
 
+#endif /* CONFIG_PROGRAM_MEMORY_BASE_LOAD */
+
 #else
 #define IMAGE_RO_AT (CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RO_MEM_OFF)
 #define IMAGE_RW_AT (CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RW_MEM_OFF)
 #define IMAGE_RW_B_AT (CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RW_B_MEM_OFF)
 #endif
 
+#ifdef CONFIG_PROGRAM_MEMORY_BASE_LOAD
+#define IMAGE_PADDING_AT (CONFIG_PROGRAM_MEMORY_BASE_LOAD + \
+			  CONFIG_FLASH_SIZE_BYTES - 1)
+#else
+#define IMAGE_PADDING_AT (CONFIG_PROGRAM_MEMORY_BASE + \
+        CONFIG_FLASH_SIZE_BYTES - 1)
+#endif
+
 OUTPUT_FORMAT(BFD_FORMAT, BFD_FORMAT, BFD_FORMAT)
 OUTPUT_ARCH(BFD_ARCH)
 
 MEMORY
 {
 	FLASH (rx) : ORIGIN = CONFIG_PROGRAM_MEMORY_BASE,
-		     LENGTH = CONFIG_FLASH_SIZE
+		     LENGTH = CONFIG_FLASH_SIZE_BYTES
+#ifdef CONFIG_IPI
+	IPI_BUFFER (rw) : ORIGIN = CONFIG_PROGRAM_MEMORY_BASE + CONFIG_IPC_SHARED_OBJ_ADDR,
+			  LENGTH = (CONFIG_IPC_SHARED_OBJ_BUF_SIZE + 8) * 2
+#endif
 #ifdef CONFIG_DRAM_BASE
-	DRAM (rx) : ORIGIN = CONFIG_DRAM_BASE_LOAD, LENGTH = CONFIG_DRAM_SIZE
+	DRAM (rx) : ORIGIN = CONFIG_DRAM_BASE, LENGTH = CONFIG_DRAM_SIZE
 #endif
 }
 
 SECTIONS
 {
+	/*
+	 * Create empty text section. Without an explicit text section
+	 * clang/lld will create one and put it at an address it selects. Even
+	 * though the section it creates is empty, if the LMA is beyond the end
+	 * of the flash, ec.bin will be too large since the empty space is
+	 * filled with 0xFF.
+	 */
+	.text (NOLOAD) : {}
+
 	.image.RO : AT(IMAGE_RO_AT) {
 		*(.image.RO)
 	} > FLASH =0xff
@@ -92,9 +126,21 @@ SECTIONS
 	} > FLASH =0xff
 #endif
 #endif
-	.padding : AT(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_FLASH_SIZE - 1) {
+#ifdef CONFIG_IMAGE_PADDING
+	.padding : AT(IMAGE_PADDING_AT) {
 		BYTE(0xff);
 	} > FLASH =0xff
+#endif
+
+#ifdef CONFIG_IPI
+	/* The section holds address of IPI buffer but no symbols. */
+	.ipi_buffer(NOLOAD) :
+#ifdef CONFIG_PROGRAM_MEMORY_BASE_LOAD
+		AT(CONFIG_PROGRAM_MEMORY_BASE_LOAD + CONFIG_IPC_SHARED_OBJ_ADDR)
+#endif
+	{
+	} > IPI_BUFFER
+#endif
 
 #ifdef CONFIG_DRAM_BASE
 	.image.RW.dram : AT(CONFIG_DRAM_BASE_LOAD) {
diff --git a/common/flash.c b/common/flash.c
index 235121f51e..5c570d3eef 100644
--- a/common/flash.c
+++ b/common/flash.c
@@ -1,12 +1,17 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Flash memory module for Chrome EC - common functions */
 
+#include "builtin/assert.h"
+#ifdef CONFIG_ZEPHYR
+#include "cbi_flash.h"
+#endif /* CONFIG_ZEPHYR */
 #include "common.h"
 #include "console.h"
+#include "cros_board_info.h"
 #include "flash.h"
 #include "gpio.h"
 #include "hooks.h"
@@ -17,6 +22,7 @@
 #include "system.h"
 #include "util.h"
 #include "vboot_hash.h"
+#include "write_protect.h"
 
 /*
  * Contents of erased flash, as a 32-bit value.  Most platforms erase flash
@@ -40,35 +46,37 @@
 /* Persistent protection state - emulates a SPI status register for flashrom */
 /* NOTE: It's not expected that RO and RW will support
  * differing PSTATE versions. */
-#define PERSIST_STATE_VERSION 3  /* Expected persist_state.version */
+#define PERSIST_STATE_VERSION 3 /* Expected persist_state.version */
 
 /* Flags for persist_state.flags */
 /* Protect persist state and RO firmware at boot */
 #define PERSIST_FLAG_PROTECT_RO 0x02
-#define PSTATE_VALID_FLAGS      BIT(0)
-#define PSTATE_VALID_SERIALNO   BIT(1)
-#define PSTATE_VALID_MAC_ADDR   BIT(2)
+#define PSTATE_VALID_FLAGS BIT(0)
+#define PSTATE_VALID_SERIALNO BIT(1)
+#define PSTATE_VALID_MAC_ADDR BIT(2)
 
+/*
+ * Error correction code operates on blocks equal to CONFIG_FLASH_WRITE_SIZE
+ * bytes so the persist_state must be a multiple of that length. To ensure this
+ * occurs, the aligned attribute has been set. Alignment has a side effect
+ * in that pointer arithmetic can't break alignment so it adds padding to the
+ * size of the structure to ensure that it is also a multiple of the alignment.
+ */
 struct persist_state {
-	uint8_t version;            /* Version of this struct */
-	uint8_t flags;              /* Lock flags (PERSIST_FLAG_*) */
-	uint8_t valid_fields;       /* Flags for valid data. */
-	uint8_t reserved;           /* Reserved; set 0 */
+	uint8_t version; /* Version of this struct */
+	uint8_t flags; /* Lock flags (PERSIST_FLAG_*) */
+	uint8_t valid_fields; /* Flags for valid data. */
+	uint8_t reserved; /* Reserved; set 0 */
 #ifdef CONFIG_SERIALNO_LEN
 	uint8_t serialno[CONFIG_SERIALNO_LEN]; /* Serial number. */
 #endif /* CONFIG_SERIALNO_LEN */
 #ifdef CONFIG_MAC_ADDR_LEN
 	uint8_t mac_addr[CONFIG_MAC_ADDR_LEN];
 #endif /* CONFIG_MAC_ADDR_LEN */
-#if !defined(CONFIG_SERIALNO_LEN) && !defined(CONFIG_MAC_ADDR_LEN)
-	uint8_t padding[4 % CONFIG_FLASH_WRITE_SIZE];
-#endif
-};
+} __aligned(CONFIG_FLASH_WRITE_SIZE);
 
 /* written with flash_physical_write, need to respect alignment constraints */
-#ifndef CHIP_FAMILY_STM32L /* STM32L1xx is somewhat lying to us */
 BUILD_ASSERT(sizeof(struct persist_state) % CONFIG_FLASH_WRITE_SIZE == 0);
-#endif
 
 BUILD_ASSERT(sizeof(struct persist_state) <= CONFIG_FW_PSTATE_SIZE);
 
@@ -87,11 +95,11 @@ BUILD_ASSERT(sizeof(struct persist_state) <= CONFIG_FW_PSTATE_SIZE);
  * lock the flash at boot.
  */
 #if (CONFIG_FLASH_ERASED_VALUE32 == -1U)
-#define PSTATE_MAGIC_UNLOCKED 0x4f4e5057  /* "WPNO" */
-#define PSTATE_MAGIC_LOCKED   0x00000000  /* ""     */
+#define PSTATE_MAGIC_UNLOCKED 0x4f4e5057 /* "WPNO" */
+#define PSTATE_MAGIC_LOCKED 0x00000000 /* ""     */
 #elif (CONFIG_FLASH_ERASED_VALUE32 == 0)
-#define PSTATE_MAGIC_UNLOCKED 0x4f4e5057  /* "WPNO" */
-#define PSTATE_MAGIC_LOCKED   0x5f5f5057  /* "WP__" */
+#define PSTATE_MAGIC_UNLOCKED 0x4f4e5057 /* "WPNO" */
+#define PSTATE_MAGIC_LOCKED 0x5f5f5057 /* "WP__" */
 #else
 /* What kind of wacky flash doesn't erase all bits to 1 or 0? */
 #error "PSTATE needs magic values for this flash architecture."
@@ -120,6 +128,9 @@ const uint32_t pstate_data __attribute__((section(".rodata.pstate"))) =
 #endif /* !CONFIG_FLASH_PSTATE_BANK */
 #endif /* CONFIG_FLASH_PSTATE */
 
+/* Shim layer provides implementation of these functions based on Zephyr API */
+#if !defined(CONFIG_ZEPHYR) || \
+	!defined(CONFIG_PLATFORM_EC_USE_ZEPHYR_FLASH_PAGE_LAYOUT)
 #ifdef CONFIG_FLASH_MULTIPLE_REGION
 const struct ec_flash_bank *flash_bank_info(int bank)
 {
@@ -133,7 +144,7 @@ const struct ec_flash_bank *flash_bank_info(int bank)
 	return NULL;
 }
 
-int flash_bank_size(int bank)
+int crec_flash_bank_size(int bank)
 {
 	int rv;
 	const struct ec_flash_bank *info = flash_bank_info(bank);
@@ -146,7 +157,7 @@ int flash_bank_size(int bank)
 	return rv;
 }
 
-int flash_bank_erase_size(int bank)
+int crec_flash_bank_erase_size(int bank)
 {
 	int rv;
 	const struct ec_flash_bank *info = flash_bank_info(bank);
@@ -159,7 +170,7 @@ int flash_bank_erase_size(int bank)
 	return rv;
 }
 
-int flash_bank_index(int offset)
+int crec_flash_bank_index(int offset)
 {
 	int bank_offset = 0, i;
 
@@ -167,8 +178,8 @@ int flash_bank_index(int offset)
 		return bank_offset;
 
 	for (i = 0; i < ARRAY_SIZE(flash_bank_array); i++) {
-		int all_sector_size = flash_bank_array[i].count <<
-			flash_bank_array[i].size_exp;
+		int all_sector_size = flash_bank_array[i].count
+				      << flash_bank_array[i].size_exp;
 		if (offset >= all_sector_size) {
 			offset -= all_sector_size;
 			bank_offset += flash_bank_array[i].count;
@@ -183,17 +194,17 @@ int flash_bank_index(int offset)
 	return bank_offset;
 }
 
-int flash_bank_count(int offset, int size)
+int crec_flash_bank_count(int offset, int size)
 {
-	int begin = flash_bank_index(offset);
-	int end = flash_bank_index(offset + size);
+	int begin = crec_flash_bank_index(offset);
+	int end = crec_flash_bank_index(offset + size);
 
 	if (begin == -1 || end == -1)
 		return -1;
 	return end - begin;
 }
 
-int flash_bank_start_offset(int bank)
+int crec_flash_bank_start_offset(int bank)
 {
 	int i;
 	int offset;
@@ -204,7 +215,7 @@ int flash_bank_start_offset(int bank)
 
 	offset = 0;
 	for (i = 0; i < bank; i++) {
-		bank_size = flash_bank_size(i);
+		bank_size = crec_flash_bank_size(i);
 		if (bank_size < 0)
 			return -1;
 		offset += bank_size;
@@ -213,21 +224,73 @@ int flash_bank_start_offset(int bank)
 	return offset;
 }
 
-#endif  /* CONFIG_FLASH_MULTIPLE_REGION */
+int crec_flash_response_fill_banks(struct ec_response_flash_info_2 *r,
+				   int num_banks)
+{
+	const struct ec_flash_bank *banks = flash_bank_array;
+	int banks_to_copy = MIN(ARRAY_SIZE(flash_bank_array), num_banks);
+
+	r->num_banks_desc = banks_to_copy;
+	r->num_banks_total = ARRAY_SIZE(flash_bank_array);
+	if (banks_to_copy > 0)
+		memcpy(r->banks, banks,
+		       banks_to_copy * sizeof(struct ec_flash_bank));
+
+	return EC_RES_SUCCESS;
+}
+#else /* CONFIG_FLASH_MULTIPLE_REGION */
+#if CONFIG_FLASH_BANK_SIZE < CONFIG_FLASH_ERASE_SIZE
+#error "Flash: Bank size expected bigger or equal to erase size."
+#endif
+int crec_flash_response_fill_banks(struct ec_response_flash_info_2 *r,
+				   int num_banks)
+{
+	if (num_banks >= 1) {
+		r->banks[0].count = crec_flash_total_banks();
+		r->banks[0].size_exp = __fls(CONFIG_FLASH_BANK_SIZE);
+		r->banks[0].write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE);
+		r->banks[0].erase_size_exp = __fls(CONFIG_FLASH_ERASE_SIZE);
+		r->banks[0].protect_size_exp = __fls(CONFIG_FLASH_BANK_SIZE);
+
+		r->num_banks_desc = 1;
+	} else {
+		/* num_banks == 0, don't fill the banks array */
+		r->num_banks_desc = 0;
+	}
+
+	r->num_banks_total = 1;
+
+	return EC_RES_SUCCESS;
+}
+#endif /* CONFIG_FLASH_MULTIPLE_REGION */
+
+int crec_flash_total_banks(void)
+{
+	return PHYSICAL_BANKS;
+}
+#endif /* !defined(CONFIG_ZEPHYR) ||                                \
+	* !defined(CONFIG_PLATFORM_EC_USE_ZEPHYR_FLASH_PAGE_LAYOUT) \
+	*/
 
 static int flash_range_ok(int offset, int size_req, int align)
 {
-	if (offset < 0 || size_req < 0 ||
-	    offset > CONFIG_FLASH_SIZE ||
-	    size_req > CONFIG_FLASH_SIZE ||
-	    offset + size_req > CONFIG_FLASH_SIZE ||
+	if (offset < 0 || size_req < 0 || offset > CONFIG_FLASH_SIZE_BYTES ||
+	    size_req > CONFIG_FLASH_SIZE_BYTES ||
+	    offset + size_req > CONFIG_FLASH_SIZE_BYTES ||
 	    (offset | size_req) & (align - 1))
-		return 0;  /* Invalid range */
+		return 0; /* Invalid range */
 
 	return 1;
 }
 
 #ifdef CONFIG_MAPPED_STORAGE
+
+/**
+ * A test public variable allowing us to override the base address of
+ * flash_physical_dataptr().
+ */
+test_export_static const char *flash_physical_dataptr_override;
+
 /**
  * Get the physical memory address of a flash offset
  *
@@ -241,17 +304,20 @@ static int flash_range_ok(int offset, int size_req, int align)
  */
 static const char *flash_physical_dataptr(int offset)
 {
+	if (IS_ENABLED(TEST_BUILD) && flash_physical_dataptr_override != NULL) {
+		return flash_physical_dataptr_override + offset;
+	}
 	return (char *)((uintptr_t)CONFIG_MAPPED_STORAGE_BASE + offset);
 }
 
-int flash_dataptr(int offset, int size_req, int align, const char **ptrp)
+int crec_flash_dataptr(int offset, int size_req, int align, const char **ptrp)
 {
 	if (!flash_range_ok(offset, size_req, align))
-		return -1;  /* Invalid range */
+		return -1; /* Invalid range */
 	if (ptrp)
 		*ptrp = flash_physical_dataptr(offset);
 
-	return CONFIG_FLASH_SIZE - offset;
+	return CONFIG_FLASH_SIZE_BYTES - offset;
 }
 #endif
 
@@ -264,8 +330,8 @@ int flash_dataptr(int offset, int size_req, int align, const char **ptrp)
 static uint32_t flash_read_pstate(void)
 {
 	const struct persist_state *pstate =
-		(const struct persist_state *)
-		flash_physical_dataptr(CONFIG_FW_PSTATE_OFF);
+		(const struct persist_state *)flash_physical_dataptr(
+			CONFIG_FW_PSTATE_OFF);
 
 	if ((pstate->version == PERSIST_STATE_VERSION) &&
 	    (pstate->valid_fields & PSTATE_VALID_FLAGS) &&
@@ -293,8 +359,8 @@ static int flash_write_pstate_data(struct persist_state *newpstate)
 	int rv;
 
 	/* Erase pstate */
-	rv = flash_physical_erase(CONFIG_FW_PSTATE_OFF,
-				  CONFIG_FW_PSTATE_SIZE);
+	rv = crec_flash_physical_erase(CONFIG_FW_PSTATE_OFF,
+				       CONFIG_FW_PSTATE_SIZE);
 	if (rv)
 		return rv;
 
@@ -305,12 +371,11 @@ static int flash_write_pstate_data(struct persist_state *newpstate)
 	 */
 
 	/* Write the updated pstate */
-	return flash_physical_write(CONFIG_FW_PSTATE_OFF, sizeof(*newpstate),
-				    (const char *)newpstate);
+	return crec_flash_physical_write(CONFIG_FW_PSTATE_OFF,
+					 sizeof(*newpstate),
+					 (const char *)newpstate);
 }
 
-
-
 /**
  * Validate and Init persistent state datastructure.
  *
@@ -337,8 +402,8 @@ static int flash_write_pstate(uint32_t flags)
 {
 	struct persist_state newpstate;
 	const struct persist_state *pstate =
-		(const struct persist_state *)
-		flash_physical_dataptr(CONFIG_FW_PSTATE_OFF);
+		(const struct persist_state *)flash_physical_dataptr(
+			CONFIG_FW_PSTATE_OFF);
 
 	/* Only check the flags we write to pstate */
 	flags &= EC_FLASH_PROTECT_RO_AT_BOOT;
@@ -364,11 +429,11 @@ static int flash_write_pstate(uint32_t flags)
 /**
  * Read and return persistent serial number.
  */
-const char *flash_read_pstate_serial(void)
+const char *crec_flash_read_pstate_serial(void)
 {
 	const struct persist_state *pstate =
-		(const struct persist_state *)
-		flash_physical_dataptr(CONFIG_FW_PSTATE_OFF);
+		(const struct persist_state *)flash_physical_dataptr(
+			CONFIG_FW_PSTATE_OFF);
 
 	if ((pstate->version == PERSIST_STATE_VERSION) &&
 	    (pstate->valid_fields & PSTATE_VALID_SERIALNO)) {
@@ -384,13 +449,13 @@ const char *flash_read_pstate_serial(void)
  * @param serialno		New ascii serial number to set in pstate.
  * @return EC_SUCCESS, or nonzero if error.
  */
-int flash_write_pstate_serial(const char *serialno)
+int crec_flash_write_pstate_serial(const char *serialno)
 {
 	int length;
 	struct persist_state newpstate;
 	const struct persist_state *pstate =
-		(const struct persist_state *)
-		flash_physical_dataptr(CONFIG_FW_PSTATE_OFF);
+		(const struct persist_state *)flash_physical_dataptr(
+			CONFIG_FW_PSTATE_OFF);
 
 	/* Check that this is OK */
 	if (!serialno)
@@ -424,11 +489,11 @@ int flash_write_pstate_serial(const char *serialno)
 /**
  * Read and return persistent MAC address.
  */
-const char *flash_read_pstate_mac_addr(void)
+const char *crec_flash_read_pstate_mac_addr(void)
 {
 	const struct persist_state *pstate =
-		(const struct persist_state *)
-		flash_physical_dataptr(CONFIG_FW_PSTATE_OFF);
+		(const struct persist_state *)flash_physical_dataptr(
+			CONFIG_FW_PSTATE_OFF);
 
 	if ((pstate->version == PERSIST_STATE_VERSION) &&
 	    (pstate->valid_fields & PSTATE_VALID_MAC_ADDR)) {
@@ -444,13 +509,13 @@ const char *flash_read_pstate_mac_addr(void)
  * @param mac_addr		New ascii MAC address to set in pstate.
  * @return EC_SUCCESS, or nonzero if error.
  */
-int flash_write_pstate_mac_addr(const char *mac_addr)
+int crec_flash_write_pstate_mac_addr(const char *mac_addr)
 {
 	int length;
 	struct persist_state newpstate;
 	const struct persist_state *pstate =
-		(const struct persist_state *)
-		flash_physical_dataptr(CONFIG_FW_PSTATE_OFF);
+		(const struct persist_state *)flash_physical_dataptr(
+			CONFIG_FW_PSTATE_OFF);
 
 	/* Check that this is OK, data is valid and fits in the region. */
 	if (!mac_addr) {
@@ -554,33 +619,32 @@ static int flash_write_pstate(uint32_t flags)
 	 * Write a new pstate.  We can overwrite the existing value, because
 	 * we're only moving bits from the erased state to the unerased state.
 	 */
-	return flash_physical_write(get_pstate_addr() -
-				    CONFIG_PROGRAM_MEMORY_BASE,
-				    sizeof(new_pstate),
-				    (const char *)&new_pstate);
+	return crec_flash_physical_write(
+		get_pstate_addr() - CONFIG_PROGRAM_MEMORY_BASE,
+		sizeof(new_pstate), (const char *)&new_pstate);
 }
 
 #endif /* !CONFIG_FLASH_PSTATE_BANK */
 #endif /* CONFIG_FLASH_PSTATE */
 
-int flash_is_erased(uint32_t offset, int size)
+int crec_flash_is_erased(uint32_t offset, int size)
 {
 	const uint32_t *ptr;
 
 #ifdef CONFIG_MAPPED_STORAGE
 	/* Use pointer directly to flash */
-	if (flash_dataptr(offset, size, sizeof(uint32_t),
-			  (const char **)&ptr) < 0)
+	if (crec_flash_dataptr(offset, size, sizeof(uint32_t),
+			       (const char **)&ptr) < 0)
 		return 0;
 
-	flash_lock_mapped_storage(1);
+	crec_flash_lock_mapped_storage(1);
 	for (size /= sizeof(uint32_t); size > 0; size--, ptr++)
 		if (*ptr != CONFIG_FLASH_ERASED_VALUE32) {
-			flash_lock_mapped_storage(0);
+			crec_flash_lock_mapped_storage(0);
 			return 0;
-	}
+		}
 
-	flash_lock_mapped_storage(0);
+	crec_flash_lock_mapped_storage(0);
 #else
 	/* Read flash a chunk at a time */
 	uint32_t buf[8];
@@ -589,7 +653,7 @@ int flash_is_erased(uint32_t offset, int size)
 	while (size) {
 		bsize = MIN(size, sizeof(buf));
 
-		if (flash_read(offset, bsize, (char *)buf))
+		if (crec_flash_read(offset, bsize, (char *)buf))
 			return 0;
 
 		size -= bsize;
@@ -599,28 +663,74 @@ int flash_is_erased(uint32_t offset, int size)
 		for (bsize /= sizeof(uint32_t); bsize > 0; bsize--, ptr++)
 			if (*ptr != CONFIG_FLASH_ERASED_VALUE32)
 				return 0;
-
 	}
 #endif
 
 	return 1;
 }
 
-int flash_read(int offset, int size, char *data)
+#if defined(CONFIG_ZEPHYR) && defined(CONFIG_PLATFORM_EC_CBI_FLASH)
+/**
+ * Check if the passed section overlaps with CBI section on EC flash.
+ *
+ * @param offset	Flash offset.
+ * @param size		Length of section in bytes.
+ * @return true if there is overlap, or false if there is no overlap.
+ */
+static bool check_cbi_section_overlap(int offset, int size)
+{
+	int cbi_start = CBI_FLASH_OFFSET;
+	int cbi_end = CBI_FLASH_OFFSET + CBI_IMAGE_SIZE;
+	int sec_start = offset;
+	int sec_end = offset + size;
+
+	return !((sec_end <= cbi_start) || (sec_start >= cbi_end));
+}
+
+/**
+ * Hide the information related to CBI(EC flash) if data contains any.
+ *
+ * @param offset	Flash offset.
+ * @param size		Length of section in bytes.
+ * @param data		Flash data.  Must be 32-bit aligned.
+ */
+static void protect_cbi_overlapped_section(int offset, int size, char *data)
+{
+	if (check_cbi_section_overlap(offset, size)) {
+		int cbi_end = CBI_FLASH_OFFSET + CBI_IMAGE_SIZE;
+		int sec_end = offset + size;
+		int cbi_fill_start = MAX(CBI_FLASH_OFFSET, offset);
+		int cbi_fill_size = MIN(cbi_end, sec_end) - cbi_fill_start;
+
+		memset(data + (cbi_fill_start - offset), 0xff, cbi_fill_size);
+	}
+}
+#endif
+
+test_mockable int crec_flash_unprotected_read(int offset, int size, char *data)
 {
 #ifdef CONFIG_MAPPED_STORAGE
 	const char *src;
 
-	if (flash_dataptr(offset, size, 1, &src) < 0)
+	if (crec_flash_dataptr(offset, size, 1, &src) < 0)
 		return EC_ERROR_INVAL;
 
-	flash_lock_mapped_storage(1);
+	crec_flash_lock_mapped_storage(1);
 	memcpy(data, src, size);
-	flash_lock_mapped_storage(0);
+	crec_flash_lock_mapped_storage(0);
 	return EC_SUCCESS;
 #else
-	return flash_physical_read(offset, size, data);
+	return crec_flash_physical_read(offset, size, data);
+#endif
+}
+
+int crec_flash_read(int offset, int size, char *data)
+{
+	RETURN_ERROR(crec_flash_unprotected_read(offset, size, data));
+#if defined(CONFIG_ZEPHYR) && defined(CONFIG_PLATFORM_EC_CBI_FLASH)
+	protect_cbi_overlapped_section(offset, size, data);
 #endif
+	return EC_SUCCESS;
 }
 
 static void flash_abort_or_invalidate_hash(int offset, int size)
@@ -652,38 +762,71 @@ static void flash_abort_or_invalidate_hash(int offset, int size)
 	 * jump to RW after the timeout.
 	 */
 	if ((offset >= CONFIG_RW_MEM_OFF &&
-		    offset < (CONFIG_RW_MEM_OFF + CONFIG_RW_SIZE)) ||
+	     offset < (CONFIG_RW_MEM_OFF + CONFIG_RW_SIZE)) ||
 	    ((offset + size) > CONFIG_RW_MEM_OFF &&
-		    (offset + size) <= (CONFIG_RW_MEM_OFF + CONFIG_RW_SIZE)) ||
+	     (offset + size) <= (CONFIG_RW_MEM_OFF + CONFIG_RW_SIZE)) ||
 	    (offset < CONFIG_RW_MEM_OFF &&
-		    (offset + size) > (CONFIG_RW_MEM_OFF + CONFIG_RW_SIZE)))
+	     (offset + size) > (CONFIG_RW_MEM_OFF + CONFIG_RW_SIZE)))
 		rwsig_abort();
 #endif
 }
 
-int flash_write(int offset, int size, const char *data)
+int crec_flash_write(int offset, int size, const char *data)
 {
 	if (!flash_range_ok(offset, size, CONFIG_FLASH_WRITE_SIZE))
-		return EC_ERROR_INVAL;  /* Invalid range */
+		return EC_ERROR_INVAL; /* Invalid range */
 
 	flash_abort_or_invalidate_hash(offset, size);
 
-	return flash_physical_write(offset, size, data);
+#if defined(CONFIG_ZEPHYR) && defined(CONFIG_PLATFORM_EC_CBI_FLASH)
+	if (check_cbi_section_overlap(offset, size)) {
+		int cbi_end = CBI_FLASH_OFFSET + CBI_IMAGE_SIZE;
+		int sec_end = offset + size;
+
+		if (offset < CBI_FLASH_OFFSET) {
+			RETURN_ERROR(crec_flash_physical_write(
+				offset, CBI_FLASH_OFFSET - offset, data));
+		}
+		if (sec_end > cbi_end) {
+			RETURN_ERROR(crec_flash_physical_write(
+				cbi_end, sec_end - cbi_end,
+				data + cbi_end - offset));
+		}
+		return EC_SUCCESS;
+	}
+#endif
+	return crec_flash_physical_write(offset, size, data);
 }
 
-int flash_erase(int offset, int size)
+int crec_flash_erase(int offset, int size)
 {
 #ifndef CONFIG_FLASH_MULTIPLE_REGION
 	if (!flash_range_ok(offset, size, CONFIG_FLASH_ERASE_SIZE))
-		return EC_ERROR_INVAL;  /* Invalid range */
+		return EC_ERROR_INVAL; /* Invalid range */
 #endif
 
 	flash_abort_or_invalidate_hash(offset, size);
 
-	return flash_physical_erase(offset, size);
+#if defined(CONFIG_ZEPHYR) && defined(CONFIG_PLATFORM_EC_CBI_FLASH)
+	if (check_cbi_section_overlap(offset, size)) {
+		int cbi_end = CBI_FLASH_OFFSET + CBI_IMAGE_SIZE;
+		int sec_end = offset + size;
+
+		if (offset < CBI_FLASH_OFFSET) {
+			RETURN_ERROR(crec_flash_physical_erase(
+				offset, CBI_FLASH_OFFSET - offset));
+		}
+		if (sec_end > cbi_end) {
+			RETURN_ERROR(crec_flash_physical_erase(
+				cbi_end, sec_end - cbi_end));
+		}
+		return EC_SUCCESS;
+	}
+#endif
+	return crec_flash_physical_erase(offset, size);
 }
 
-int flash_protect_at_boot(uint32_t new_flags)
+int crec_flash_protect_at_boot(uint32_t new_flags)
 {
 #ifdef CONFIG_FLASH_PSTATE
 	uint32_t new_pstate_flags = new_flags & EC_FLASH_PROTECT_RO_AT_BOOT;
@@ -695,7 +838,7 @@ int flash_protect_at_boot(uint32_t new_flags)
 
 #ifdef CONFIG_FLASH_PSTATE_BANK
 		/* Fail if write protect block is already locked */
-		if (flash_physical_get_protect(PSTATE_BANK))
+		if (crec_flash_physical_get_protect(PSTATE_BANK))
 			return EC_ERROR_ACCESS_DENIED;
 #endif
 
@@ -717,21 +860,21 @@ int flash_protect_at_boot(uint32_t new_flags)
 	 * This assumes PSTATE immediately follows RO, which it does on
 	 * all STM32 platforms (which are the only ones with this config).
 	 */
-	flash_physical_protect_at_boot(new_flags);
+	crec_flash_physical_protect_at_boot(new_flags);
 #endif
 
 	return EC_SUCCESS;
 #else
-	return flash_physical_protect_at_boot(new_flags);
+	return crec_flash_physical_protect_at_boot(new_flags);
 #endif
 }
 
-uint32_t flash_get_protect(void)
+uint32_t crec_flash_get_protect(void)
 {
 	uint32_t flags = 0;
 	int i;
 	/* Region protection status */
-	int not_protected[FLASH_REGION_COUNT] = {0};
+	int not_protected[FLASH_REGION_COUNT] = { 0 };
 #ifdef CONFIG_ROLLBACK
 	/* Flags that must be set to set ALL_NOW flag. */
 	const uint32_t all_flags = EC_FLASH_PROTECT_RO_NOW |
@@ -743,15 +886,8 @@ uint32_t flash_get_protect(void)
 #endif
 
 	/* Read write protect GPIO */
-#ifdef CONFIG_WP_ALWAYS
-	flags |= EC_FLASH_PROTECT_GPIO_ASSERTED;
-#elif defined(CONFIG_WP_ACTIVE_HIGH)
-	if (gpio_get_level(GPIO_WP))
+	if (write_protect_is_asserted())
 		flags |= EC_FLASH_PROTECT_GPIO_ASSERTED;
-#else
-	if (!gpio_get_level(GPIO_WP_L))
-		flags |= EC_FLASH_PROTECT_GPIO_ASSERTED;
-#endif
 
 #ifdef CONFIG_FLASH_PSTATE
 	/* Read persistent state of RO-at-boot flag */
@@ -759,13 +895,13 @@ uint32_t flash_get_protect(void)
 #endif
 
 	/* Scan flash protection */
-	for (i = 0; i < PHYSICAL_BANKS; i++) {
+	for (i = 0; i < crec_flash_total_banks(); i++) {
 		int is_ro = (i >= WP_BANK_OFFSET &&
-			i < WP_BANK_OFFSET + WP_BANK_COUNT);
+			     i < WP_BANK_OFFSET + WP_BANK_COUNT);
 		enum flash_region region = is_ro ? FLASH_REGION_RO :
-			FLASH_REGION_RW;
+						   FLASH_REGION_RW;
 		int bank_flag = is_ro ? EC_FLASH_PROTECT_RO_NOW :
-			EC_FLASH_PROTECT_RW_NOW;
+					EC_FLASH_PROTECT_RW_NOW;
 
 #ifdef CONFIG_ROLLBACK
 		if (i >= ROLLBACK_BANK_OFFSET &&
@@ -775,7 +911,7 @@ uint32_t flash_get_protect(void)
 		}
 #endif
 
-		if (flash_physical_get_protect(i)) {
+		if (crec_flash_physical_get_protect(i)) {
 			/* At least one bank in the region is protected */
 			flags |= bank_flag;
 			if (not_protected[region])
@@ -808,7 +944,7 @@ uint32_t flash_get_protect(void)
 #endif
 
 	/* Add in flags from physical layer */
-	return flags | flash_physical_get_protect_flags();
+	return flags | crec_flash_physical_get_protect_flags();
 }
 
 /*
@@ -822,14 +958,15 @@ uint32_t flash_get_protect(void)
  * 4. Commit RO_NOW.
  * 5. Commit ALL_NOW.
  */
-int flash_set_protect(uint32_t mask, uint32_t flags)
+int crec_flash_set_protect(uint32_t mask, uint32_t flags)
 {
 	int retval = EC_SUCCESS;
 	int rv;
-	int old_flags_at_boot = flash_get_protect() &
+	int old_flags_at_boot =
+		crec_flash_get_protect() &
 		(EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RW_AT_BOOT |
-			EC_FLASH_PROTECT_ROLLBACK_AT_BOOT |
-			EC_FLASH_PROTECT_ALL_AT_BOOT);
+		 EC_FLASH_PROTECT_ROLLBACK_AT_BOOT |
+		 EC_FLASH_PROTECT_ALL_AT_BOOT);
 	int new_flags_at_boot = old_flags_at_boot;
 
 	/* Sanitize input flags */
@@ -899,7 +1036,7 @@ int flash_set_protect(uint32_t mask, uint32_t flags)
 
 	/* 1.f - Commit *_AT_BOOT "clears" (and RO "set" 1.b). */
 	if (new_flags_at_boot != old_flags_at_boot) {
-		rv = flash_protect_at_boot(new_flags_at_boot);
+		rv = crec_flash_protect_at_boot(new_flags_at_boot);
 		if (rv)
 			retval = rv;
 		old_flags_at_boot = new_flags_at_boot;
@@ -910,8 +1047,8 @@ int flash_set_protect(uint32_t mask, uint32_t flags)
 	 * All subsequent flags only work if write protect is enabled (that is,
 	 * hardware WP flag) *and* RO is protected at boot (software WP flag).
 	 */
-	if ((~flash_get_protect()) & (EC_FLASH_PROTECT_GPIO_ASSERTED |
-				      EC_FLASH_PROTECT_RO_AT_BOOT))
+	if ((~crec_flash_get_protect()) &
+	    (EC_FLASH_PROTECT_GPIO_ASSERTED | EC_FLASH_PROTECT_RO_AT_BOOT))
 		return retval;
 
 	/*
@@ -934,21 +1071,29 @@ int flash_set_protect(uint32_t mask, uint32_t flags)
 
 	/* 3.d - Commit *_AT_BOOT "sets". */
 	if (new_flags_at_boot != old_flags_at_boot) {
-		rv = flash_protect_at_boot(new_flags_at_boot);
+		rv = crec_flash_protect_at_boot(new_flags_at_boot);
 		if (rv)
 			retval = rv;
 	}
 
 	/* 4 - Commit RO_NOW. */
 	if (flags & EC_FLASH_PROTECT_RO_NOW) {
-		rv = flash_physical_protect_now(0);
+		rv = crec_flash_physical_protect_now(0);
 		if (rv)
 			retval = rv;
+
+		/*
+		 * Latch the CBI EEPROM WP immediately if HW WP is asserted and
+		 * we're now protecting the RO region with SW WP.
+		 */
+		if (IS_ENABLED(CONFIG_EEPROM_CBI_WP) &&
+		    (EC_FLASH_PROTECT_GPIO_ASSERTED & crec_flash_get_protect()))
+			cbi_latch_eeprom_wp();
 	}
 
 	/* 5 - Commit ALL_NOW. */
 	if (flags & EC_FLASH_PROTECT_ALL_NOW) {
-		rv = flash_physical_protect_now(1);
+		rv = crec_flash_physical_protect_now(1);
 		if (rv)
 			retval = rv;
 	}
@@ -962,8 +1107,7 @@ static struct ec_params_flash_erase_v1 erase_info;
 
 static void flash_erase_deferred(void)
 {
-	erase_rc = EC_RES_BUSY;
-	if (flash_erase(erase_info.params.offset, erase_info.params.size))
+	if (crec_flash_erase(erase_info.params.offset, erase_info.params.size))
 		erase_rc = EC_RES_ERROR;
 	else
 		erase_rc = EC_RES_SUCCESS;
@@ -971,22 +1115,16 @@ static void flash_erase_deferred(void)
 DECLARE_DEFERRED(flash_erase_deferred);
 #endif
 
-/*****************************************************************************/
-/* Console commands */
-
-#ifdef CONFIG_CMD_FLASHINFO
-static int command_flash_info(int argc, char **argv)
+#if !defined(CONFIG_ZEPHYR) || \
+	!defined(CONFIG_PLATFORM_EC_USE_ZEPHYR_FLASH_PAGE_LAYOUT)
+void crec_flash_print_region_info(void)
 {
-	int i, flags;
-
-	ccprintf("Usable:  %4d KB\n", CONFIG_FLASH_SIZE / 1024);
-	ccprintf("Write:   %4d B (ideal %d B)\n", CONFIG_FLASH_WRITE_SIZE,
-		 CONFIG_FLASH_WRITE_IDEAL_SIZE);
 #ifdef CONFIG_FLASH_MULTIPLE_REGION
+	int i;
+
 	ccprintf("Regions:\n");
 	for (i = 0; i < ARRAY_SIZE(flash_bank_array); i++) {
-		ccprintf(" %d region%s:\n",
-			 flash_bank_array[i].count,
+		ccprintf(" %d region%s:\n", flash_bank_array[i].count,
 			 (flash_bank_array[i].count == 1 ? "" : "s"));
 		ccprintf("  Erase:   %4d B (to %d-bits)\n",
 			 1 << flash_bank_array[i].erase_size_exp,
@@ -999,60 +1137,77 @@ static int command_flash_info(int argc, char **argv)
 		 CONFIG_FLASH_ERASED_VALUE32 ? 1 : 0);
 	ccprintf("Protect: %4d B\n", CONFIG_FLASH_BANK_SIZE);
 #endif
-	flags = flash_get_protect();
-	ccprintf("Flags:  ");
-	if (flags & EC_FLASH_PROTECT_GPIO_ASSERTED)
-		ccputs(" wp_gpio_asserted");
-	if (flags & EC_FLASH_PROTECT_RO_AT_BOOT)
-		ccputs(" ro_at_boot");
-	if (flags & EC_FLASH_PROTECT_ALL_AT_BOOT)
-		ccputs(" all_at_boot");
-	if (flags & EC_FLASH_PROTECT_RO_NOW)
-		ccputs(" ro_now");
-	if (flags & EC_FLASH_PROTECT_ALL_NOW)
-		ccputs(" all_now");
+}
+#endif
+
+/*****************************************************************************/
+/* Console commands */
+
+#ifdef CONFIG_CMD_FLASHINFO
+#define BIT_TO_ON_OFF(value, mask) \
+	((((value) & (mask)) == (mask)) ? "ON" : "OFF")
+static int command_flash_info(int argc, const char **argv)
+{
+	int i, flags;
+
+	ccprintf("Usable:  %4d KB\n", CONFIG_FLASH_SIZE_BYTES / 1024);
+	ccprintf("Write:   %4d B (ideal %d B)\n", CONFIG_FLASH_WRITE_SIZE,
+		 CONFIG_FLASH_WRITE_IDEAL_SIZE);
+	crec_flash_print_region_info();
+	flags = crec_flash_get_protect();
+	ccprintf("Flags:\n");
+	ccprintf("  wp_gpio_asserted: %s\n",
+		 BIT_TO_ON_OFF(flags, EC_FLASH_PROTECT_GPIO_ASSERTED));
+	ccprintf("  ro_at_boot: %s\n",
+		 BIT_TO_ON_OFF(flags, EC_FLASH_PROTECT_RO_AT_BOOT));
+	ccprintf("  all_at_boot: %s\n",
+		 BIT_TO_ON_OFF(flags, EC_FLASH_PROTECT_ALL_AT_BOOT));
+	ccprintf("  ro_now: %s\n",
+		 BIT_TO_ON_OFF(flags, EC_FLASH_PROTECT_RO_NOW));
+	ccprintf("  all_now: %s\n",
+		 BIT_TO_ON_OFF(flags, EC_FLASH_PROTECT_ALL_NOW));
 #ifdef CONFIG_FLASH_PROTECT_RW
-	if (flags & EC_FLASH_PROTECT_RW_AT_BOOT)
-		ccputs(" rw_at_boot");
-	if (flags & EC_FLASH_PROTECT_RW_NOW)
-		ccputs(" rw_now");
+	ccprintf("  rw_at_boot: %s\n",
+		 BIT_TO_ON_OFF(flags, EC_FLASH_PROTECT_RW_AT_BOOT));
+	ccprintf("  rw_now: %s\n",
+		 BIT_TO_ON_OFF(flags, EC_FLASH_PROTECT_RW_NOW));
 #endif
-	if (flags & EC_FLASH_PROTECT_ERROR_STUCK)
-		ccputs(" STUCK");
-	if (flags & EC_FLASH_PROTECT_ERROR_INCONSISTENT)
-		ccputs(" INCONSISTENT");
+	ccprintf("  STUCK: %s\n",
+		 BIT_TO_ON_OFF(flags, EC_FLASH_PROTECT_ERROR_STUCK));
+	ccprintf("  INCONSISTENT: %s\n",
+		 BIT_TO_ON_OFF(flags, EC_FLASH_PROTECT_ERROR_INCONSISTENT));
+	ccprintf("  UNKNOWN_ERROR: %s\n",
+		 BIT_TO_ON_OFF(flags, EC_FLASH_PROTECT_ERROR_UNKNOWN));
 #ifdef CONFIG_ROLLBACK
-	if (flags & EC_FLASH_PROTECT_ROLLBACK_AT_BOOT)
-		ccputs(" rollback_at_boot");
-	if (flags & EC_FLASH_PROTECT_ROLLBACK_NOW)
-		ccputs(" rollback_now");
+	ccprintf("  rollback_at_boot: %s\n",
+		 BIT_TO_ON_OFF(flags, EC_FLASH_PROTECT_ROLLBACK_AT_BOOT));
+	ccprintf("  rollback_now: %s\n",
+		 BIT_TO_ON_OFF(flags, EC_FLASH_PROTECT_ROLLBACK_NOW));
 #endif
-	ccputs("\n");
 
 	ccputs("Protected now:");
-	for (i = 0; i < PHYSICAL_BANKS; i++) {
+	for (i = 0; i < crec_flash_total_banks(); i++) {
 		if (!(i & 31))
 			ccputs("\n    ");
 		else if (!(i & 7))
 			ccputs(" ");
-		ccputs(flash_physical_get_protect(i) ? "Y" : ".");
+		ccputs(crec_flash_physical_get_protect(i) ? "Y" : ".");
 	}
 	ccputs("\n");
 	return EC_SUCCESS;
 }
-DECLARE_SAFE_CONSOLE_COMMAND(flashinfo, command_flash_info,
-			     NULL,
+DECLARE_SAFE_CONSOLE_COMMAND(flashinfo, command_flash_info, NULL,
 			     "Print flash info");
 #endif /* CONFIG_CMD_FLASHINFO */
 
 #ifdef CONFIG_CMD_FLASH
-static int command_flash_erase(int argc, char **argv)
+static int command_flash_erase(int argc, const char **argv)
 {
 	int offset = -1;
 	int size = -1;
 	int rv;
 
-	if (flash_get_protect() & EC_FLASH_PROTECT_ALL_NOW)
+	if (crec_flash_get_protect() & EC_FLASH_PROTECT_ALL_NOW)
 		return EC_ERROR_ACCESS_DENIED;
 
 	rv = parse_offset_size(argc, argv, 1, &offset, &size);
@@ -1060,13 +1215,12 @@ static int command_flash_erase(int argc, char **argv)
 		return rv;
 
 	ccprintf("Erasing %d bytes at 0x%x...\n", size, offset);
-	return flash_erase(offset, size);
+	return crec_flash_erase(offset, size);
 }
-DECLARE_CONSOLE_COMMAND(flasherase, command_flash_erase,
-			"offset size",
+DECLARE_CONSOLE_COMMAND(flasherase, command_flash_erase, "offset size",
 			"Erase flash");
 
-static int command_flash_write(int argc, char **argv)
+static int command_flash_write(int argc, const char **argv)
 {
 	int offset = -1;
 	int size = -1;
@@ -1074,7 +1228,7 @@ static int command_flash_write(int argc, char **argv)
 	char *data;
 	int i;
 
-	if (flash_get_protect() & EC_FLASH_PROTECT_ALL_NOW)
+	if (crec_flash_get_protect() & EC_FLASH_PROTECT_ALL_NOW)
 		return EC_ERROR_ACCESS_DENIED;
 
 	rv = parse_offset_size(argc, argv, 1, &offset, &size);
@@ -1096,23 +1250,22 @@ static int command_flash_write(int argc, char **argv)
 		data[i] = i;
 
 	ccprintf("Writing %d bytes to 0x%x...\n", size, offset);
-	rv = flash_write(offset, size, data);
+	rv = crec_flash_write(offset, size, data);
 
 	/* Free the buffer */
 	shared_mem_release(data);
 
 	return rv;
 }
-DECLARE_CONSOLE_COMMAND(flashwrite, command_flash_write,
-			"offset size",
+DECLARE_CONSOLE_COMMAND(flashwrite, command_flash_write, "offset size",
 			"Write pattern to flash");
 
-static int command_flash_read(int argc, char **argv)
+static int command_flash_read(int argc, const char **argv)
 {
 	int offset = -1;
 	int size = 256;
 	int rv;
-	char *data;
+	uint8_t *data;
 	int i;
 
 	rv = parse_offset_size(argc, argv, 1, &offset, &size);
@@ -1123,14 +1276,14 @@ static int command_flash_read(int argc, char **argv)
 		size = shared_mem_size();
 
 	/* Acquire the shared memory buffer */
-	rv = shared_mem_acquire(size, &data);
+	rv = shared_mem_acquire(size, (char **)&data);
 	if (rv) {
 		ccputs("Can't get shared mem\n");
 		return rv;
 	}
 
 	/* Read the data */
-	if (flash_read(offset, size, data)) {
+	if (crec_flash_read(offset, size, data)) {
 		shared_mem_release(data);
 		return EC_ERROR_INVAL;
 	}
@@ -1151,12 +1304,12 @@ static int command_flash_read(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(flashread, command_flash_read,
-			"offset [size]",
+DECLARE_CONSOLE_COMMAND(flashread, command_flash_read, "offset [size]",
 			"Read flash");
 #endif
 
-static int command_flash_wp(int argc, char **argv)
+#ifdef CONFIG_CMD_FLASH_WP
+static int command_flash_wp(int argc, const char **argv)
 {
 	int val;
 
@@ -1164,34 +1317,36 @@ static int command_flash_wp(int argc, char **argv)
 		return EC_ERROR_PARAM_COUNT;
 
 	if (!strcasecmp(argv[1], "now"))
-		return flash_set_protect(EC_FLASH_PROTECT_ALL_NOW, -1);
+		return crec_flash_set_protect(EC_FLASH_PROTECT_ALL_NOW, -1);
 
 	if (!strcasecmp(argv[1], "all"))
-		return flash_set_protect(EC_FLASH_PROTECT_ALL_AT_BOOT, -1);
+		return crec_flash_set_protect(EC_FLASH_PROTECT_ALL_AT_BOOT, -1);
 
 	if (!strcasecmp(argv[1], "noall"))
-		return flash_set_protect(EC_FLASH_PROTECT_ALL_AT_BOOT, 0);
+		return crec_flash_set_protect(EC_FLASH_PROTECT_ALL_AT_BOOT, 0);
 
 #ifdef CONFIG_FLASH_PROTECT_RW
 	if (!strcasecmp(argv[1], "rw"))
-		return flash_set_protect(EC_FLASH_PROTECT_RW_AT_BOOT, -1);
+		return crec_flash_set_protect(EC_FLASH_PROTECT_RW_AT_BOOT, -1);
 
 	if (!strcasecmp(argv[1], "norw"))
-		return flash_set_protect(EC_FLASH_PROTECT_RW_AT_BOOT, 0);
+		return crec_flash_set_protect(EC_FLASH_PROTECT_RW_AT_BOOT, 0);
 #endif
 
 #ifdef CONFIG_ROLLBACK
 	if (!strcasecmp(argv[1], "rb"))
-		return flash_set_protect(EC_FLASH_PROTECT_ROLLBACK_AT_BOOT, -1);
+		return crec_flash_set_protect(EC_FLASH_PROTECT_ROLLBACK_AT_BOOT,
+					      -1);
 
 	if (!strcasecmp(argv[1], "norb"))
-		return flash_set_protect(EC_FLASH_PROTECT_ROLLBACK_AT_BOOT, 0);
+		return crec_flash_set_protect(EC_FLASH_PROTECT_ROLLBACK_AT_BOOT,
+					      0);
 #endif
 
 	/* Do this last, since anything starting with 'n' means "no" */
 	if (parse_bool(argv[1], &val))
-		return flash_set_protect(EC_FLASH_PROTECT_RO_AT_BOOT,
-					 val ? -1 : 0);
+		return crec_flash_set_protect(EC_FLASH_PROTECT_RO_AT_BOOT,
+					      val ? -1 : 0);
 
 	return EC_ERROR_PARAM1;
 }
@@ -1203,7 +1358,9 @@ DECLARE_CONSOLE_COMMAND(flashwp, command_flash_wp,
 #ifdef CONFIG_ROLLBACK
 			" | rb | norb"
 #endif
-			, "Modify flash write protect");
+			,
+			"Modify flash write protect");
+#endif /* CONFIG_CMD_FLASH_WP */
 
 /*****************************************************************************/
 /* Host commands */
@@ -1218,40 +1375,24 @@ DECLARE_CONSOLE_COMMAND(flashwp, command_flash_wp,
  * region belonging to the EC. TODO(crbug.com/529365): Handle fmap_base
  * correctly in flashrom, dump_fmap, etc. and remove EC_FLASH_REGION_START.
  */
-#define EC_FLASH_REGION_START MIN(CONFIG_EC_PROTECTED_STORAGE_OFF, \
-				  CONFIG_EC_WRITABLE_STORAGE_OFF)
+#define EC_FLASH_REGION_START \
+	MIN(CONFIG_EC_PROTECTED_STORAGE_OFF, CONFIG_EC_WRITABLE_STORAGE_OFF)
 
 static enum ec_status flash_command_get_info(struct host_cmd_handler_args *args)
 {
 	const struct ec_params_flash_info_2 *p_2 = args->params;
 	struct ec_response_flash_info_2 *r_2 = args->response;
-#ifdef CONFIG_FLASH_MULTIPLE_REGION
-	int banks_size = ARRAY_SIZE(flash_bank_array);
-	const struct ec_flash_bank *banks = flash_bank_array;
-#else
+#ifndef CONFIG_FLASH_MULTIPLE_REGION
 	struct ec_response_flash_info_1 *r_1 = args->response;
-#if CONFIG_FLASH_BANK_SIZE < CONFIG_FLASH_ERASE_SIZE
-#error "Flash: Bank size expected bigger or equal to erase size."
-#endif
-	struct ec_flash_bank single_bank = {
-		.count = CONFIG_FLASH_SIZE / CONFIG_FLASH_BANK_SIZE,
-		.size_exp = __fls(CONFIG_FLASH_BANK_SIZE),
-		.write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE),
-		.erase_size_exp = __fls(CONFIG_FLASH_ERASE_SIZE),
-		.protect_size_exp = __fls(CONFIG_FLASH_BANK_SIZE),
-	};
-	int banks_size = 1;
-	const struct ec_flash_bank *banks = &single_bank;
 #endif
-	int banks_len;
-	int ideal_size;
+	int res;
 
 	/*
 	 * Compute the ideal amount of data for the host to send us,
 	 * based on the maximum response size and the ideal write size.
 	 */
-	ideal_size = (args->response_max -
-		 sizeof(struct ec_params_flash_write)) &
+	int ideal_size =
+		(args->response_max - sizeof(struct ec_params_flash_write)) &
 		~(CONFIG_FLASH_WRITE_IDEAL_SIZE - 1);
 	/*
 	 * If we can't get at least one ideal block, then just want
@@ -1259,13 +1400,13 @@ static enum ec_status flash_command_get_info(struct host_cmd_handler_args *args)
 	 */
 	if (!ideal_size)
 		ideal_size = (args->response_max -
-				sizeof(struct ec_params_flash_write)) &
-				~(CONFIG_FLASH_WRITE_SIZE - 1);
-
+			      sizeof(struct ec_params_flash_write)) &
+			     ~(CONFIG_FLASH_WRITE_SIZE - 1);
 
 	if (args->version >= 2) {
 		args->response_size = sizeof(struct ec_response_flash_info_2);
-		r_2->flash_size = CONFIG_FLASH_SIZE - EC_FLASH_REGION_START;
+		r_2->flash_size =
+			CONFIG_FLASH_SIZE_BYTES - EC_FLASH_REGION_START;
 #if (CONFIG_FLASH_ERASED_VALUE32 == 0)
 		r_2->flags = EC_FLASH_INFO_ERASE_TO_0;
 #else
@@ -1275,17 +1416,22 @@ static enum ec_status flash_command_get_info(struct host_cmd_handler_args *args)
 		r_2->flags |= EC_FLASH_INFO_SELECT_REQUIRED;
 #endif
 		r_2->write_ideal_size = ideal_size;
-		r_2->num_banks_total = banks_size;
-		r_2->num_banks_desc = MIN(banks_size, p_2->num_banks_desc);
-		banks_len = r_2->num_banks_desc * sizeof(struct ec_flash_bank);
-		memcpy(r_2->banks, banks, banks_len);
-		args->response_size += banks_len;
+		/*
+		 * Fill r_2->num_banks_desc, r_2->num_banks_total and
+		 * r_2->banks.
+		 */
+		res = crec_flash_response_fill_banks(r_2, p_2->num_banks_desc);
+		if (res != EC_RES_SUCCESS)
+			return res;
+
+		args->response_size +=
+			r_2->num_banks_desc * sizeof(struct ec_flash_bank);
 		return EC_RES_SUCCESS;
 	}
 #ifdef CONFIG_FLASH_MULTIPLE_REGION
 	return EC_RES_INVALID_PARAM;
 #else
-	r_1->flash_size = CONFIG_FLASH_SIZE - EC_FLASH_REGION_START;
+	r_1->flash_size = CONFIG_FLASH_SIZE_BYTES - EC_FLASH_REGION_START;
 	r_1->flags = 0;
 	r_1->write_block_size = CONFIG_FLASH_WRITE_SIZE;
 	r_1->erase_block_size = CONFIG_FLASH_ERASE_SIZE;
@@ -1305,16 +1451,14 @@ static enum ec_status flash_command_get_info(struct host_cmd_handler_args *args)
 #endif
 	}
 	return EC_RES_SUCCESS;
-#endif  /* CONFIG_FLASH_MULTIPLE_REGION */
+#endif /* CONFIG_FLASH_MULTIPLE_REGION */
 }
 #ifdef CONFIG_FLASH_MULTIPLE_REGION
 #define FLASH_INFO_VER EC_VER_MASK(2)
 #else
 #define FLASH_INFO_VER (EC_VER_MASK(0) | EC_VER_MASK(1) | EC_VER_MASK(2))
 #endif
-DECLARE_HOST_COMMAND(EC_CMD_FLASH_INFO,
-		     flash_command_get_info, FLASH_INFO_VER);
-
+DECLARE_HOST_COMMAND(EC_CMD_FLASH_INFO, flash_command_get_info, FLASH_INFO_VER);
 
 static enum ec_status flash_command_read(struct host_cmd_handler_args *args)
 {
@@ -1324,16 +1468,14 @@ static enum ec_status flash_command_read(struct host_cmd_handler_args *args)
 	if (p->size > args->response_max)
 		return EC_RES_OVERFLOW;
 
-	if (flash_read(offset, p->size, args->response))
+	if (crec_flash_read(offset, p->size, args->response))
 		return EC_RES_ERROR;
 
 	args->response_size = p->size;
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_FLASH_READ,
-		     flash_command_read,
-		     EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_FLASH_READ, flash_command_read, EC_VER_MASK(0));
 
 /**
  * Flash write command
@@ -1346,7 +1488,7 @@ static enum ec_status flash_command_write(struct host_cmd_handler_args *args)
 	const struct ec_params_flash_write *p = args->params;
 	uint32_t offset = p->offset + EC_FLASH_REGION_START;
 
-	if (flash_get_protect() & EC_FLASH_PROTECT_ALL_NOW)
+	if (crec_flash_get_protect() & EC_FLASH_PROTECT_ALL_NOW)
 		return EC_RES_ACCESS_DENIED;
 
 	if (p->size + sizeof(*p) > args->params_size)
@@ -1357,23 +1499,22 @@ static enum ec_status flash_command_write(struct host_cmd_handler_args *args)
 		return EC_RES_ACCESS_DENIED;
 #endif
 
-	if (flash_write(offset, p->size, (const uint8_t *)(p + 1)))
+	if (crec_flash_write(offset, p->size, (const uint8_t *)(p + 1)))
 		return EC_RES_ERROR;
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_FLASH_WRITE,
-		     flash_command_write,
+DECLARE_HOST_COMMAND(EC_CMD_FLASH_WRITE, flash_command_write,
 		     EC_VER_MASK(0) | EC_VER_MASK(EC_VER_FLASH_WRITE));
 
 #ifndef CONFIG_FLASH_MULTIPLE_REGION
 /*
  * Make sure our image sizes are a multiple of flash block erase size so that
  * the host can erase the entire image.
+ * Note that host (flashrom/depthcharge) does not erase/program the
+ * EC_FLASH_REGION_RO region, it only queries this region.
  */
-BUILD_ASSERT(CONFIG_RO_SIZE % CONFIG_FLASH_ERASE_SIZE == 0);
-BUILD_ASSERT(CONFIG_RW_SIZE % CONFIG_FLASH_ERASE_SIZE == 0);
-BUILD_ASSERT(EC_FLASH_REGION_RO_SIZE % CONFIG_FLASH_ERASE_SIZE == 0);
+BUILD_ASSERT(CONFIG_WP_STORAGE_SIZE % CONFIG_FLASH_ERASE_SIZE == 0);
 BUILD_ASSERT(CONFIG_EC_WRITABLE_STORAGE_SIZE % CONFIG_FLASH_ERASE_SIZE == 0);
 
 #endif
@@ -1393,7 +1534,7 @@ static enum ec_status flash_command_erase(struct host_cmd_handler_args *args)
 #endif
 	offset = p->offset + EC_FLASH_REGION_START;
 
-	if (flash_get_protect() & EC_FLASH_PROTECT_ALL_NOW)
+	if (crec_flash_get_protect() & EC_FLASH_PROTECT_ALL_NOW)
 		return EC_RES_ACCESS_DENIED;
 
 #ifdef CONFIG_INTERNAL_STORAGE
@@ -1407,7 +1548,7 @@ static enum ec_status flash_command_erase(struct host_cmd_handler_args *args)
 		args->result = EC_RES_IN_PROGRESS;
 		host_send_response(args);
 #endif
-		if (flash_erase(offset, p->size))
+		if (crec_flash_erase(offset, p->size))
 			return EC_RES_ERROR;
 
 		break;
@@ -1418,6 +1559,7 @@ static enum ec_status flash_command_erase(struct host_cmd_handler_args *args)
 			memcpy(&erase_info, p_1, sizeof(*p_1));
 			hook_call_deferred(&flash_erase_deferred_data,
 					   100 * MSEC);
+			erase_rc = EC_RES_BUSY;
 		} else {
 			/*
 			 * Not our job to return the result of
@@ -1439,16 +1581,115 @@ static enum ec_status flash_command_erase(struct host_cmd_handler_args *args)
 	return rc;
 }
 
-
 DECLARE_HOST_COMMAND(EC_CMD_FLASH_ERASE, flash_command_erase,
-		EC_VER_MASK(0)
+		     EC_VER_MASK(0)
 #ifdef CONFIG_FLASH_DEFERRED_ERASE
-		| EC_VER_MASK(1)
+			     | EC_VER_MASK(1)
+#endif
+);
+
+#ifdef CONFIG_FLASH_PROTECT_DEFERRED
+struct flash_protect_async {
+	uint32_t mask;
+	uint32_t flags;
+
+	volatile enum ec_status rc;
+} __ec_align4;
+
+static struct flash_protect_async flash_protect_async_data = {
+	.rc = EC_RES_SUCCESS
+};
+
+static void crec_flash_set_protect_deferred(void)
+{
+	if (crec_flash_set_protect(flash_protect_async_data.mask,
+				   flash_protect_async_data.flags))
+		flash_protect_async_data.rc = EC_RES_ERROR;
+	else
+		flash_protect_async_data.rc = EC_RES_SUCCESS;
+}
+DECLARE_DEFERRED(crec_flash_set_protect_deferred);
+
+static enum ec_status
+flash_command_protect_v2(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_flash_protect_v2 *p = args->params;
+	struct ec_response_flash_protect *r = args->response;
+	int rc = EC_RES_SUCCESS;
+
+	flash_protect_async_data.mask = p->mask;
+	flash_protect_async_data.flags = p->flags;
+
+	/*
+	 * Handle requesting new flags.  Note that we ignore the return code
+	 * from flash_set_protect(), since errors will be visible to the caller
+	 * via the flags in the response.  (If we returned error, the caller
+	 * wouldn't get the response.)
+	 */
+
+	switch (p->action) {
+	case FLASH_PROTECT_ASYNC:
+		if (p->mask) {
+			rc = flash_protect_async_data.rc;
+			if (rc != EC_RES_SUCCESS) {
+				rc = EC_RES_BUSY;
+				break;
+			}
+			hook_call_deferred(
+				&crec_flash_set_protect_deferred_data,
+				100 * MSEC);
+			/* Not our job to return the result of
+			 * the previous command.
+			 */
+			flash_protect_async_data.rc = EC_RES_BUSY;
+		}
+		return EC_RES_SUCCESS;
+
+	case FLASH_PROTECT_GET_RESULT:
+		/*
+		 * Retrieve the current flags.  The caller can use this
+		 * to determine which of the requested flags could be
+		 * set.  This is cleaner than simply returning error,
+		 * because it provides information to the caller about
+		 * the actual result.
+		 */
+		rc = flash_protect_async_data.rc;
+		if (rc == EC_RES_BUSY || rc == EC_RES_ERROR)
+			break;
+
+		r->flags = crec_flash_get_protect();
+
+		/* Indicate which flags are valid on this platform */
+		r->valid_flags = EC_FLASH_PROTECT_GPIO_ASSERTED |
+				 EC_FLASH_PROTECT_ERROR_STUCK |
+				 EC_FLASH_PROTECT_ERROR_INCONSISTENT |
+				 EC_FLASH_PROTECT_ERROR_UNKNOWN |
+				 crec_flash_physical_get_valid_flags();
+		r->writable_flags =
+			crec_flash_physical_get_writable_flags(r->flags);
+
+		args->response_size = sizeof(*r);
+
+		/* Ready for another command */
+		flash_protect_async_data.rc = EC_RES_SUCCESS;
+		break;
+
+	default:
+		rc = EC_RES_INVALID_PARAM;
+	}
+
+	return rc;
+}
 #endif
-		);
 
 static enum ec_status flash_command_protect(struct host_cmd_handler_args *args)
 {
+#if defined(CONFIG_FLASH_PROTECT_DEFERRED)
+	if (args->version == 2) {
+		return flash_command_protect_v2(args);
+	}
+#endif
+
 	const struct ec_params_flash_protect *p = args->params;
 	struct ec_response_flash_protect *r = args->response;
 
@@ -1459,7 +1700,7 @@ static enum ec_status flash_command_protect(struct host_cmd_handler_args *args)
 	 * wouldn't get the response.)
 	 */
 	if (p->mask)
-		flash_set_protect(p->mask, p->flags);
+		crec_flash_set_protect(p->mask, p->flags);
 
 	/*
 	 * Retrieve the current flags.  The caller can use this to determine
@@ -1467,29 +1708,27 @@ static enum ec_status flash_command_protect(struct host_cmd_handler_args *args)
 	 * simply returning error, because it provides information to the
 	 * caller about the actual result.
 	 */
-	r->flags = flash_get_protect();
+	r->flags = crec_flash_get_protect();
 
 	/* Indicate which flags are valid on this platform */
-	r->valid_flags =
-		EC_FLASH_PROTECT_GPIO_ASSERTED |
-		EC_FLASH_PROTECT_ERROR_STUCK |
-		EC_FLASH_PROTECT_ERROR_INCONSISTENT |
-		flash_physical_get_valid_flags();
-	r->writable_flags = flash_physical_get_writable_flags(r->flags);
+	r->valid_flags = EC_FLASH_PROTECT_GPIO_ASSERTED |
+			 EC_FLASH_PROTECT_ERROR_STUCK |
+			 EC_FLASH_PROTECT_ERROR_INCONSISTENT |
+			 EC_FLASH_PROTECT_ERROR_UNKNOWN |
+			 crec_flash_physical_get_valid_flags();
+	r->writable_flags = crec_flash_physical_get_writable_flags(r->flags);
 
 	args->response_size = sizeof(*r);
 
 	return EC_RES_SUCCESS;
 }
 
-/*
- * TODO(crbug.com/239197) : Adding both versions to the version mask is a
- * temporary workaround for a problem in the cros_ec driver. Drop
- * EC_VER_MASK(0) once cros_ec driver can send the correct version.
- */
-DECLARE_HOST_COMMAND(EC_CMD_FLASH_PROTECT,
-		     flash_command_protect,
-		     EC_VER_MASK(0) | EC_VER_MASK(1));
+DECLARE_HOST_COMMAND(EC_CMD_FLASH_PROTECT, flash_command_protect,
+		     EC_VER_MASK(1)
+#ifdef CONFIG_FLASH_PROTECT_DEFERRED
+			     | EC_VER_MASK(2)
+#endif
+);
 
 static enum ec_status
 flash_command_region_info(struct host_cmd_handler_args *args)
@@ -1500,23 +1739,21 @@ flash_command_region_info(struct host_cmd_handler_args *args)
 	switch (p->region) {
 	case EC_FLASH_REGION_RO:
 		r->offset = CONFIG_EC_PROTECTED_STORAGE_OFF +
-			    CONFIG_RO_STORAGE_OFF -
-			    EC_FLASH_REGION_START;
+			    CONFIG_RO_STORAGE_OFF - EC_FLASH_REGION_START;
 		r->size = EC_FLASH_REGION_RO_SIZE;
 		break;
 	case EC_FLASH_REGION_ACTIVE:
 		r->offset = flash_get_rw_offset(system_get_active_copy()) -
-				EC_FLASH_REGION_START;
+			    EC_FLASH_REGION_START;
 		r->size = CONFIG_EC_WRITABLE_STORAGE_SIZE;
 		break;
 	case EC_FLASH_REGION_WP_RO:
-		r->offset = CONFIG_WP_STORAGE_OFF -
-			    EC_FLASH_REGION_START;
+		r->offset = CONFIG_WP_STORAGE_OFF - EC_FLASH_REGION_START;
 		r->size = CONFIG_WP_STORAGE_SIZE;
 		break;
 	case EC_FLASH_REGION_UPDATE:
 		r->offset = flash_get_rw_offset(system_get_update_copy()) -
-				EC_FLASH_REGION_START;
+			    EC_FLASH_REGION_START;
 		r->size = CONFIG_EC_WRITABLE_STORAGE_SIZE;
 		break;
 	default:
@@ -1526,21 +1763,17 @@ flash_command_region_info(struct host_cmd_handler_args *args)
 	args->response_size = sizeof(*r);
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_FLASH_REGION_INFO,
-		     flash_command_region_info,
+DECLARE_HOST_COMMAND(EC_CMD_FLASH_REGION_INFO, flash_command_region_info,
 		     EC_VER_MASK(EC_VER_FLASH_REGION_INFO));
 
-
 #ifdef CONFIG_FLASH_SELECT_REQUIRED
 
 static enum ec_status flash_command_select(struct host_cmd_handler_args *args)
 {
 	const struct ec_params_flash_select *p = args->params;
 
-	return board_flash_select(p->select);
+	return crec_board_flash_select(p->select);
 }
-DECLARE_HOST_COMMAND(EC_CMD_FLASH_SELECT,
-		     flash_command_select,
-		     EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_FLASH_SELECT, flash_command_select, EC_VER_MASK(0));
 
 #endif /* CONFIG_FLASH_SELECT_REQUIRED */
diff --git a/common/fmap.c b/common/fmap.c
index 001f83a184..0fa77c47cd 100644
--- a/common/fmap.c
+++ b/common/fmap.c
@@ -1,19 +1,20 @@
 /*
- * Copyright 2012 The Chromium OS Authors. All rights reserved.
+ * Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <stddef.h>
-
 #include "common.h"
+#include "cros_version.h"
 #include "rwsig.h"
 #include "util.h"
-#include "version.h"
+
+#include <stddef.h>
 
 /*
  * FMAP structs.
- * See https://chromium.googlesource.com/chromiumos/third_party/flashmap/+/master/lib/fmap.h
+ * See
+ * https://chromium.googlesource.com/chromiumos/third_party/flashmap/+/HEAD/lib/fmap.h
  */
 #define FMAP_NAMELEN 32
 #define FMAP_SIGNATURE "__FMAP__"
@@ -25,8 +26,8 @@
  * For address containing CONFIG_PROGRAM_MEMORY_BASE (symbols in *.RO.lds.S and
  * variable), this computes the offset to the start of the image on flash.
  */
-#define RELATIVE_RO(addr) ((addr) - CONFIG_PROGRAM_MEMORY_BASE - \
-			   CONFIG_RO_MEM_OFF)
+#define RELATIVE_RO(addr) \
+	((addr)-CONFIG_PROGRAM_MEMORY_BASE - CONFIG_RO_MEM_OFF)
 
 /*
  * All internal EC code assumes that offsets are provided relative to
@@ -45,23 +46,23 @@
 #endif
 
 struct fmap_header {
-	char        fmap_signature[FMAP_SIGNATURE_SIZE];
-	uint8_t     fmap_ver_major;
-	uint8_t     fmap_ver_minor;
-	uint64_t    fmap_base;
-	uint32_t    fmap_size;
-	char        fmap_name[FMAP_NAMELEN];
-	uint16_t    fmap_nareas;
+	char fmap_signature[FMAP_SIGNATURE_SIZE];
+	uint8_t fmap_ver_major;
+	uint8_t fmap_ver_minor;
+	uint64_t fmap_base;
+	uint32_t fmap_size;
+	char fmap_name[FMAP_NAMELEN];
+	uint16_t fmap_nareas;
 } __packed;
 
-#define FMAP_AREA_STATIC      BIT(0)	/* can be checksummed */
-#define FMAP_AREA_COMPRESSED  BIT(1)  /* may be compressed */
-#define FMAP_AREA_RO          BIT(2)  /* writes may fail */
+#define FMAP_AREA_STATIC BIT(0) /* can be checksummed */
+#define FMAP_AREA_COMPRESSED BIT(1) /* may be compressed */
+#define FMAP_AREA_RO BIT(2) /* writes may fail */
 
 struct fmap_area_header {
 	uint32_t area_offset;
 	uint32_t area_size;
-	char     area_name[FMAP_NAMELEN];
+	char area_name[FMAP_NAMELEN];
 	uint16_t area_flags;
 } __packed;
 
@@ -77,19 +78,18 @@ struct fmap_area_header {
 #define NUM_EC_FMAP_AREAS_ROLLBACK 0
 #endif
 #ifdef CONFIG_RW_B
-#  ifdef CONFIG_RWSIG_TYPE_RWSIG
-#    define NUM_EC_FMAP_AREAS_RW_B     2
-#  else
-#    define NUM_EC_FMAP_AREAS_RW_B     1
-#  endif
+#ifdef CONFIG_RWSIG_TYPE_RWSIG
+#define NUM_EC_FMAP_AREAS_RW_B 2
+#else
+#define NUM_EC_FMAP_AREAS_RW_B 1
+#endif
 #else
-#define NUM_EC_FMAP_AREAS_RW_B     0
+#define NUM_EC_FMAP_AREAS_RW_B 0
 #endif
 
-#define NUM_EC_FMAP_AREAS (7 + \
-			NUM_EC_FMAP_AREAS_RWSIG + \
-			NUM_EC_FMAP_AREAS_ROLLBACK + \
-			NUM_EC_FMAP_AREAS_RW_B)
+#define NUM_EC_FMAP_AREAS                                           \
+	(7 + NUM_EC_FMAP_AREAS_RWSIG + NUM_EC_FMAP_AREAS_ROLLBACK + \
+	 NUM_EC_FMAP_AREAS_RW_B)
 
 const struct _ec_fmap {
 	struct fmap_header header;
@@ -97,18 +97,18 @@ const struct _ec_fmap {
 } ec_fmap __keep __attribute__((section(".google"))) = {
 	/* Header */
 	{
-		.fmap_signature = {'_', '_', 'F', 'M', 'A', 'P', '_', '_'},
+		.fmap_signature = { '_', '_', 'F', 'M', 'A', 'P', '_', '_' },
 		.fmap_ver_major = FMAP_VER_MAJOR,
 		.fmap_ver_minor = FMAP_VER_MINOR,
 		.fmap_base = CONFIG_PROGRAM_MEMORY_BASE,
-		.fmap_size = CONFIG_FLASH_SIZE,
+		.fmap_size = CONFIG_FLASH_SIZE_BYTES,
 		/* Used to distinguish the EC FMAP from other FMAPs */
 		.fmap_name = "EC_FMAP",
 		.fmap_nareas = NUM_EC_FMAP_AREAS,
 	},
 
 	{
-	/* RO Firmware */
+		/* RO Firmware */
 		{
 			/*
 			 * Range of RO firmware to be updated. EC_RO
@@ -120,7 +120,7 @@ const struct _ec_fmap {
 			 */
 			.area_name = "EC_RO",
 			.area_offset = CONFIG_EC_PROTECTED_STORAGE_OFF -
-				FMAP_REGION_START,
+				       FMAP_REGION_START,
 			.area_size = CONFIG_RO_SIZE + CONFIG_RO_STORAGE_OFF,
 			.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
 		},
@@ -128,7 +128,8 @@ const struct _ec_fmap {
 			/* (Optional) RO firmware code. */
 			.area_name = "FR_MAIN",
 			.area_offset = CONFIG_EC_PROTECTED_STORAGE_OFF -
-				FMAP_REGION_START + CONFIG_RO_STORAGE_OFF,
+				       FMAP_REGION_START +
+				       CONFIG_RO_STORAGE_OFF,
 			.area_size = CONFIG_RO_SIZE,
 			.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
 		},
@@ -138,10 +139,11 @@ const struct _ec_fmap {
 			 * ASCII, and padded with \0.
 			 */
 			.area_name = "RO_FRID",
-			.area_offset = CONFIG_EC_PROTECTED_STORAGE_OFF -
+			.area_offset =
+				CONFIG_EC_PROTECTED_STORAGE_OFF -
 				FMAP_REGION_START + CONFIG_RO_STORAGE_OFF +
 				RELATIVE_RO((uint32_t)__image_data_offset) +
-				offsetof(struct image_data,  version),
+				offsetof(struct image_data, version),
 			.area_size = sizeof(current_image_data.version),
 			.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
 		},
@@ -150,8 +152,9 @@ const struct _ec_fmap {
 		{
 			.area_name = "FMAP",
 			.area_offset = CONFIG_EC_PROTECTED_STORAGE_OFF -
-				FMAP_REGION_START + CONFIG_RO_STORAGE_OFF +
-				RELATIVE_RO((uint32_t)&ec_fmap),
+				       FMAP_REGION_START +
+				       CONFIG_RO_STORAGE_OFF +
+				       RELATIVE_RO((uint32_t)&ec_fmap),
 			.area_size = sizeof(ec_fmap),
 			.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
 		},
@@ -162,8 +165,7 @@ const struct _ec_fmap {
 			 * EC_RO and aligned to hardware specification.
 			 */
 			.area_name = "WP_RO",
-			.area_offset = CONFIG_WP_STORAGE_OFF -
-				       FMAP_REGION_START,
+			.area_offset = CONFIG_WP_STORAGE_OFF - FMAP_REGION_START,
 			.area_size = CONFIG_WP_STORAGE_SIZE,
 			.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
 		},
@@ -172,8 +174,9 @@ const struct _ec_fmap {
 			/* RO public key address, for RW verification */
 			.area_name = "KEY_RO",
 			.area_offset = CONFIG_EC_PROTECTED_STORAGE_OFF -
-				FMAP_REGION_START + CONFIG_RO_PUBKEY_ADDR -
-				CONFIG_PROGRAM_MEMORY_BASE,
+				       FMAP_REGION_START +
+				       CONFIG_RO_PUBKEY_ADDR -
+				       CONFIG_PROGRAM_MEMORY_BASE,
 			.area_size = CONFIG_RO_PUBKEY_SIZE,
 			.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
 		},
@@ -181,10 +184,11 @@ const struct _ec_fmap {
 
 		/* RW Firmware */
 		{
-			 /* The range of RW firmware to be auto-updated. */
+			/* The range of RW firmware to be auto-updated. */
 			.area_name = "EC_RW",
 			.area_offset = CONFIG_EC_WRITABLE_STORAGE_OFF -
-				FMAP_REGION_START + CONFIG_RW_STORAGE_OFF,
+				       FMAP_REGION_START +
+				       CONFIG_RW_STORAGE_OFF,
 			.area_size = CONFIG_RW_SIZE,
 			.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
 		},
@@ -197,10 +201,11 @@ const struct _ec_fmap {
 			 * accommodate image asymmetry.
 			 */
 			.area_name = "RW_FWID",
-			.area_offset = CONFIG_EC_WRITABLE_STORAGE_OFF -
+			.area_offset =
+				CONFIG_EC_WRITABLE_STORAGE_OFF -
 				FMAP_REGION_START + CONFIG_RW_STORAGE_OFF +
 				RELATIVE_RO((uint32_t)__image_data_offset) +
-				offsetof(struct image_data,  version),
+				offsetof(struct image_data, version),
 			.area_size = sizeof(current_image_data.version),
 			.area_flags = FMAP_AREA_STATIC,
 		},
@@ -213,22 +218,22 @@ const struct _ec_fmap {
 			 * accommodate image asymmetry.
 			 */
 			.area_name = "RW_RBVER",
-			.area_offset = CONFIG_EC_WRITABLE_STORAGE_OFF -
+			.area_offset =
+				CONFIG_EC_WRITABLE_STORAGE_OFF -
 				FMAP_REGION_START + CONFIG_RW_STORAGE_OFF +
 				RELATIVE_RO((uint32_t)__image_data_offset) +
 				offsetof(struct image_data, rollback_version),
-			.area_size = sizeof(
-				current_image_data.rollback_version),
+			.area_size = sizeof(current_image_data.rollback_version),
 			.area_flags = FMAP_AREA_STATIC,
 		},
 #endif
 #ifdef CONFIG_RWSIG_TYPE_RWSIG
 		{
-			 /* RW image signature */
+			/* RW image signature */
 			.area_name = "SIG_RW",
 			.area_offset = CONFIG_EC_PROTECTED_STORAGE_OFF -
-				FMAP_REGION_START + CONFIG_RW_SIG_ADDR -
-				CONFIG_PROGRAM_MEMORY_BASE,
+				       FMAP_REGION_START + CONFIG_RW_SIG_ADDR -
+				       CONFIG_PROGRAM_MEMORY_BASE,
 			.area_size = CONFIG_RW_SIG_SIZE,
 			.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
 		},
@@ -236,21 +241,22 @@ const struct _ec_fmap {
 #ifdef CONFIG_RW_B
 		/* RW Firmware */
 		{
-			 /* The range of RW firmware to be auto-updated. */
+			/* The range of RW firmware to be auto-updated. */
 			.area_name = "EC_RW_B",
 			.area_offset = CONFIG_EC_WRITABLE_STORAGE_OFF -
-				FMAP_REGION_START + CONFIG_RW_STORAGE_OFF +
-				CONFIG_RW_SIZE,
+				       FMAP_REGION_START +
+				       CONFIG_RW_STORAGE_OFF + CONFIG_RW_SIZE,
 			.area_size = CONFIG_RW_SIZE,
 			.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
 		},
 #ifdef CONFIG_RWSIG_TYPE_RWSIG
 		{
-			 /* RW_B image signature */
+			/* RW_B image signature */
 			.area_name = "SIG_RW_B",
 			.area_offset = CONFIG_EC_PROTECTED_STORAGE_OFF -
-				FMAP_REGION_START + CONFIG_RW_B_SIG_ADDR -
-				CONFIG_PROGRAM_MEMORY_BASE,
+				       FMAP_REGION_START +
+				       CONFIG_RW_B_SIG_ADDR -
+				       CONFIG_PROGRAM_MEMORY_BASE,
 			.area_size = CONFIG_RW_SIG_SIZE,
 			.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
 		},
diff --git a/common/fpsensor/OWNERS b/common/fpsensor/OWNERS
index 41820f5b0c..bccfa32fde 100644
--- a/common/fpsensor/OWNERS
+++ b/common/fpsensor/OWNERS
@@ -3,5 +3,4 @@
 # Don't inherit owners from elsewhere in the manifest
 set noparent
 
-tomhughes@chromium.org
-adlr@chromium.org
+include chromiumos/platform2:/biod/OWNERS
diff --git a/common/fpsensor/build.mk b/common/fpsensor/build.mk
index d7e0e72b63..129deb484d 100644
--- a/common/fpsensor/build.mk
+++ b/common/fpsensor/build.mk
@@ -1,13 +1,64 @@
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 # Build for fingerprint sensor
 
+# Only build if CONFIG_FINGERPRINT_MCU or TEST_BUILD is "y".
+ifneq (,$(filter y,$(CONFIG_FINGERPRINT_MCU) $(TEST_BUILD)))
+
 # Note that this variable includes the trailing "/"
 _fpsensor_dir:=$(dir $(lastword $(MAKEFILE_LIST)))
 
-all-obj-$(HAS_TASK_FPSENSOR)+=$(_fpsensor_dir)fpsensor_state.o
-all-obj-$(HAS_TASK_FPSENSOR)+=$(_fpsensor_dir)fpsensor_crypto.o
-all-obj-$(HAS_TASK_FPSENSOR)+=$(_fpsensor_dir)fpsensor.o
-all-obj-$(HAS_TASK_CONSOLE)+=$(_fpsensor_dir)fpsensor_detect_strings.o
+# Additional CFLAGS for only fpsensor objects
+fpsensor_CFLAGS=-Wvla
+
+_fpsensor_state_obj:=$(_fpsensor_dir)fpsensor_state.o
+_fpsensor_crypto_obj:=$(_fpsensor_dir)fpsensor_crypto.o
+_fpsensor_obj:=$(_fpsensor_dir)fpsensor.o
+_fpsensor_detect_strings_obj:=$(_fpsensor_dir)fpsensor_detect_strings.o
+_fpsensor_debug_obj:=$(_fpsensor_dir)fpsensor_debug.o
+_fpsensor_auth_commands_obj:=$(_fpsensor_dir)fpsensor_auth_commands.o
+_fpsensor_auth_crypto_stateful_obj:=$(_fpsensor_dir)fpsensor_auth_crypto_stateful.o
+_fpsensor_auth_crypto_stateless_obj:=$(_fpsensor_dir)fpsensor_auth_crypto_stateless.o
+_fpsensor_state_without_driver_info_obj:=$(_fpsensor_dir)fpsensor_state_without_driver_info.o
+
+$(out)/RW/$(_fpsensor_state_obj): CFLAGS+=$(fpsensor_CFLAGS)
+$(out)/RW/$(_fpsensor_crypto_obj): CFLAGS+=$(fpsensor_CFLAGS)
+$(out)/RW/$(_fpsensor_obj): CFLAGS+=$(fpsensor_CFLAGS)
+$(out)/RW/$(_fpsensor_detect_strings_obj): CFLAGS+=$(fpsensor_CFLAGS)
+$(out)/RW/$(_fpsensor_debug_obj): CFLAGS+=$(fpsensor_CFLAGS)
+$(out)/RW/$(_fpsensor_auth_commands_obj): CFLAGS+=$(fpsensor_CFLAGS)
+$(out)/RW/$(_fpsensor_auth_crypto_stateful_obj): CFLAGS+=$(fpsensor_CFLAGS)
+$(out)/RW/$(_fpsensor_auth_crypto_stateless_obj): CFLAGS+=$(fpsensor_CFLAGS)
+$(out)/RW/$(_fpsensor_state_without_driver_info_obj): CFLAGS+=$(fpsensor_CFLAGS)
+
+all-obj-$(HAS_TASK_FPSENSOR)+=$(_fpsensor_state_obj)
+all-obj-$(HAS_TASK_FPSENSOR)+=$(_fpsensor_obj)
+all-obj-$(HAS_TASK_CONSOLE)+=$(_fpsensor_detect_strings_obj)
+all-obj-$(HAS_TASK_FPSENSOR)+=$(_fpsensor_debug_obj)
+all-obj-$(HAS_TASK_FPSENSOR)+=$(_fpsensor_auth_commands_obj)
+
+# If HAS_TASK_FPSENSOR is not empty.
+ifneq (,$(HAS_TASK_FPSENSOR))
+all-obj-$(HAS_TASK_FPSENSOR)+=$(_fpsensor_auth_crypto_stateless_obj)
+endif # HAS_TASK_FPSENSOR.
+# Or we are building fpsensor related projects.
+ifeq (fpsensor,$(findstring fpsensor,$(PROJECT)))
+all-obj-y+=$(_fpsensor_auth_crypto_stateless_obj)
+endif # fpsensor projects.
+
+# If HAS_TASK_FPSENSOR is not empty.
+ifneq (,$(HAS_TASK_FPSENSOR))
+all-obj-$(HAS_TASK_FPSENSOR)+=$(_fpsensor_crypto_obj)
+all-obj-$(HAS_TASK_FPSENSOR)+=$(_fpsensor_state_without_driver_info_obj)
+all-obj-$(HAS_TASK_FPSENSOR)+=$(_fpsensor_auth_crypto_stateful_obj)
+endif # HAS_TASK_FPSENSOR.
+# Or we are building stateful fpsensor related projects.
+ifeq (fpsensor,$(findstring fpsensor,$(PROJECT))$(findstring stateless,$(PROJECT)))
+all-obj-y+=$(_fpsensor_crypto_obj)
+all-obj-y+=$(_fpsensor_state_without_driver_info_obj)
+all-obj-y+=$(_fpsensor_auth_crypto_stateful_obj)
+endif # stateful fpsensor projects.
+
+endif # CONFIG_FINGERPRINT_MCU or TEST_BUILD
diff --git a/common/fpsensor/fpsensor.c b/common/fpsensor/fpsensor.c
deleted file mode 100644
index 5611fd828d..0000000000
--- a/common/fpsensor/fpsensor.c
+++ /dev/null
@@ -1,853 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "atomic.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "cryptoc/util.h"
-#include "ec_commands.h"
-#include "fpsensor.h"
-#include "fpsensor_crypto.h"
-#include "fpsensor_detect.h"
-#include "fpsensor_private.h"
-#include "fpsensor_state.h"
-#include "gpio.h"
-#include "host_command.h"
-#include "link_defs.h"
-#include "mkbp_event.h"
-#include "overflow.h"
-#include "spi.h"
-#include "system.h"
-#include "task.h"
-#include "trng.h"
-#include "util.h"
-#include "watchdog.h"
-
-#if !defined(CONFIG_RNG)
-#error "fpsensor requires RNG"
-#endif
-
-/* Ready to encrypt a template. */
-static timestamp_t encryption_deadline;
-
-/* raw image offset inside the acquired frame */
-#ifndef FP_SENSOR_IMAGE_OFFSET
-#define FP_SENSOR_IMAGE_OFFSET 0
-#endif
-
-#define FP_MODE_ANY_CAPTURE (FP_MODE_CAPTURE | FP_MODE_ENROLL_IMAGE | \
-			     FP_MODE_MATCH)
-#define FP_MODE_ANY_DETECT_FINGER (FP_MODE_FINGER_DOWN | FP_MODE_FINGER_UP | \
-				   FP_MODE_ANY_CAPTURE)
-#define FP_MODE_ANY_WAIT_IRQ      (FP_MODE_FINGER_DOWN | FP_MODE_ANY_CAPTURE)
-
-/* Delay between 2 s of the sensor to detect finger removal */
-#define FINGER_POLLING_DELAY (100*MSEC)
-
-/* Timing statistics. */
-static uint32_t capture_time_us;
-static uint32_t matching_time_us;
-static uint32_t overall_time_us;
-static timestamp_t overall_t0;
-static uint8_t timestamps_invalid;
-
-BUILD_ASSERT(sizeof(struct ec_fp_template_encryption_metadata) % 4 == 0);
-
-/* Interrupt line from the fingerprint sensor */
-void fps_event(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_FPSENSOR, TASK_EVENT_SENSOR_IRQ, 0);
-}
-
-static void send_mkbp_event(uint32_t event)
-{
-	deprecated_atomic_or(&fp_events, event);
-	mkbp_send_event(EC_MKBP_EVENT_FINGERPRINT);
-}
-
-static inline int is_raw_capture(uint32_t mode)
-{
-	int capture_type = FP_CAPTURE_TYPE(mode);
-
-	return (capture_type == FP_CAPTURE_VENDOR_FORMAT
-	     || capture_type == FP_CAPTURE_QUALITY_TEST);
-}
-
-#ifdef HAVE_FP_PRIVATE_DRIVER
-static inline int is_test_capture(uint32_t mode)
-{
-	int capture_type = FP_CAPTURE_TYPE(mode);
-
-	return (mode & FP_MODE_CAPTURE)
-		&& (capture_type == FP_CAPTURE_PATTERN0
-		    || capture_type == FP_CAPTURE_PATTERN1
-		    || capture_type == FP_CAPTURE_RESET_TEST);
-}
-
-/*
- * contains the bit FP_MODE_ENROLL_SESSION if a finger enrollment is on-going.
- * It is used to detect the ENROLL_SESSION transition when sensor_mode is
- * updated by the host.
- */
-static uint32_t enroll_session;
-
-static uint32_t fp_process_enroll(void)
-{
-	int percent = 0;
-	int res;
-
-	if (template_newly_enrolled != FP_NO_SUCH_TEMPLATE)
-		CPRINTS("Warning: previously enrolled template has not been "
-			"read yet.");
-
-	/* begin/continue enrollment */
-	CPRINTS("[%d]Enrolling ...", templ_valid);
-	res = fp_finger_enroll(fp_buffer, &percent);
-	CPRINTS("[%d]Enroll =>%d (%d%%)", templ_valid, res, percent);
-	if (res < 0)
-		return EC_MKBP_FP_ENROLL
-		     | EC_MKBP_FP_ERRCODE(EC_MKBP_FP_ERR_ENROLL_INTERNAL);
-	templ_dirty |= BIT(templ_valid);
-	if (percent == 100) {
-		res = fp_enrollment_finish(fp_template[templ_valid]);
-		if (res) {
-			res = EC_MKBP_FP_ERR_ENROLL_INTERNAL;
-		} else {
-			template_newly_enrolled = templ_valid;
-			fp_enable_positive_match_secret(templ_valid,
-				&positive_match_secret_state);
-			templ_valid++;
-		}
-		sensor_mode &= ~FP_MODE_ENROLL_SESSION;
-		enroll_session &= ~FP_MODE_ENROLL_SESSION;
-	}
-	return EC_MKBP_FP_ENROLL | EC_MKBP_FP_ERRCODE(res)
-	     | (percent << EC_MKBP_FP_ENROLL_PROGRESS_OFFSET);
-}
-
-static uint32_t fp_process_match(void)
-{
-	timestamp_t t0 = get_time();
-	int res = -1;
-	uint32_t updated = 0;
-	int32_t fgr = FP_NO_SUCH_TEMPLATE;
-
-	/* match finger against current templates */
-	fp_disable_positive_match_secret(&positive_match_secret_state);
-	CPRINTS("Matching/%d ...", templ_valid);
-	if (templ_valid) {
-		res = fp_finger_match(fp_template[0], templ_valid, fp_buffer,
-				      &fgr, &updated);
-		CPRINTS("Match =>%d (finger %d)", res, fgr);
-		if (res < 0 || fgr < 0 || fgr >= FP_MAX_FINGER_COUNT) {
-			res = EC_MKBP_FP_ERR_MATCH_NO_INTERNAL;
-			timestamps_invalid |= FPSTATS_MATCHING_INV;
-		} else {
-			fp_enable_positive_match_secret(fgr,
-				&positive_match_secret_state);
-		}
-		if (res == EC_MKBP_FP_ERR_MATCH_YES_UPDATED)
-			templ_dirty |= updated;
-	} else {
-		CPRINTS("No enrolled templates");
-		res = EC_MKBP_FP_ERR_MATCH_NO_TEMPLATES;
-		timestamps_invalid |= FPSTATS_MATCHING_INV;
-	}
-	matching_time_us = time_since32(t0);
-	return EC_MKBP_FP_MATCH | EC_MKBP_FP_ERRCODE(res)
-	| ((fgr << EC_MKBP_FP_MATCH_IDX_OFFSET) & EC_MKBP_FP_MATCH_IDX_MASK);
-}
-
-static void fp_process_finger(void)
-{
-	timestamp_t t0 = get_time();
-	int res = fp_sensor_acquire_image_with_mode(fp_buffer,
-			FP_CAPTURE_TYPE(sensor_mode));
-	capture_time_us = time_since32(t0);
-	if (!res) {
-		uint32_t evt = EC_MKBP_FP_IMAGE_READY;
-
-		/* Clean up SPI before clocking up to avoid hang on the dsb
-		 * in dma_go. Ignore the return value to let the WDT reboot
-		 * the MCU (and avoid getting trapped in the loop).
-		 * b/112781659 */
-		res = spi_transaction_flush(&spi_devices[0]);
-		if (res)
-			CPRINTS("Failed to flush SPI: 0x%x", res);
-		/* we need CPU power to do the computations */
-		clock_enable_module(MODULE_FAST_CPU, 1);
-
-		if (sensor_mode & FP_MODE_ENROLL_IMAGE)
-			evt = fp_process_enroll();
-		else if (sensor_mode & FP_MODE_MATCH)
-			evt = fp_process_match();
-
-		sensor_mode &= ~FP_MODE_ANY_CAPTURE;
-		overall_time_us = time_since32(overall_t0);
-		send_mkbp_event(evt);
-
-		/* go back to lower power mode */
-		clock_enable_module(MODULE_FAST_CPU, 0);
-	} else {
-		timestamps_invalid |= FPSTATS_CAPTURE_INV;
-	}
-}
-#endif /* HAVE_FP_PRIVATE_DRIVER */
-
-void fp_task(void)
-{
-	int timeout_us = -1;
-
-	CPRINTS("FP_SENSOR_SEL: %s",
-		fp_sensor_type_to_str(get_fp_sensor_type()));
-
-#ifdef HAVE_FP_PRIVATE_DRIVER
-	/* Reset and initialize the sensor IC */
-	fp_sensor_init();
-
-	while (1) {
-		uint32_t evt;
-		enum finger_state st = FINGER_NONE;
-
-		/* Wait for a sensor IRQ or a new mode configuration */
-		evt = task_wait_event(timeout_us);
-
-		if (evt & TASK_EVENT_UPDATE_CONFIG) {
-			uint32_t mode = sensor_mode;
-
-			gpio_disable_interrupt(GPIO_FPS_INT);
-			if ((mode ^ enroll_session) & FP_MODE_ENROLL_SESSION) {
-				if (mode & FP_MODE_ENROLL_SESSION) {
-					if (fp_enrollment_begin())
-						sensor_mode &=
-							~FP_MODE_ENROLL_SESSION;
-				} else {
-					fp_enrollment_finish(NULL);
-				}
-				enroll_session =
-					sensor_mode & FP_MODE_ENROLL_SESSION;
-			}
-			if (is_test_capture(mode)) {
-				fp_sensor_acquire_image_with_mode(fp_buffer,
-					FP_CAPTURE_TYPE(mode));
-				sensor_mode &= ~FP_MODE_CAPTURE;
-				send_mkbp_event(EC_MKBP_FP_IMAGE_READY);
-				continue;
-			} else if (sensor_mode & FP_MODE_ANY_DETECT_FINGER) {
-				/* wait for a finger on the sensor */
-				fp_sensor_configure_detect();
-			}
-			if (sensor_mode & FP_MODE_DEEPSLEEP)
-				/* Shutdown the sensor */
-				fp_sensor_low_power();
-			if (sensor_mode & FP_MODE_FINGER_UP)
-				/* Poll the sensor to detect finger removal */
-				timeout_us = FINGER_POLLING_DELAY;
-			else
-				timeout_us = -1;
-			if (mode & FP_MODE_ANY_WAIT_IRQ) {
-				gpio_enable_interrupt(GPIO_FPS_INT);
-			} else if (mode & FP_MODE_RESET_SENSOR) {
-				fp_reset_and_clear_context();
-				sensor_mode &= ~FP_MODE_RESET_SENSOR;
-			} else if (mode & FP_MODE_SENSOR_MAINTENANCE) {
-				fp_maintenance();
-				sensor_mode &= ~FP_MODE_SENSOR_MAINTENANCE;
-			} else {
-				fp_sensor_low_power();
-			}
-		} else if (evt & (TASK_EVENT_SENSOR_IRQ | TASK_EVENT_TIMER)) {
-			overall_t0 = get_time();
-			timestamps_invalid = 0;
-			gpio_disable_interrupt(GPIO_FPS_INT);
-			if (sensor_mode & FP_MODE_ANY_DETECT_FINGER) {
-				st = fp_sensor_finger_status();
-				if (st == FINGER_PRESENT &&
-				    sensor_mode & FP_MODE_FINGER_DOWN) {
-					CPRINTS("Finger!");
-					sensor_mode &= ~FP_MODE_FINGER_DOWN;
-					send_mkbp_event(EC_MKBP_FP_FINGER_DOWN);
-				}
-				if (st == FINGER_NONE &&
-				    sensor_mode & FP_MODE_FINGER_UP) {
-					sensor_mode &= ~FP_MODE_FINGER_UP;
-					timeout_us = -1;
-					send_mkbp_event(EC_MKBP_FP_FINGER_UP);
-				}
-			}
-
-			if (st == FINGER_PRESENT &&
-			    sensor_mode & FP_MODE_ANY_CAPTURE)
-				fp_process_finger();
-
-			if (sensor_mode & FP_MODE_ANY_WAIT_IRQ) {
-				fp_sensor_configure_detect();
-				gpio_enable_interrupt(GPIO_FPS_INT);
-			} else {
-				fp_sensor_low_power();
-			}
-		}
-	}
-#else /* !HAVE_FP_PRIVATE_DRIVER */
-	while (1) {
-		uint32_t evt = task_wait_event(timeout_us);
-
-		send_mkbp_event(evt);
-	}
-#endif /* !HAVE_FP_PRIVATE_DRIVER */
-}
-
-static enum ec_status fp_command_passthru(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_fp_passthru *params = args->params;
-	void *out = args->response;
-	int rc;
-	int ret = EC_RES_SUCCESS;
-
-	if (system_is_locked())
-		return EC_RES_ACCESS_DENIED;
-
-	if (params->len > args->params_size +
-	    offsetof(struct ec_params_fp_passthru, data) ||
-	    params->len > args->response_max)
-		return EC_RES_INVALID_PARAM;
-
-	rc = spi_transaction_async(&spi_devices[0], params->data,
-				   params->len, out, SPI_READBACK_ALL);
-	if (params->flags & EC_FP_FLAG_NOT_COMPLETE)
-		rc |= spi_transaction_wait(&spi_devices[0]);
-	else
-		rc |= spi_transaction_flush(&spi_devices[0]);
-
-	if (rc == EC_ERROR_TIMEOUT)
-		ret = EC_RES_TIMEOUT;
-	else if (rc)
-		ret = EC_RES_ERROR;
-
-	args->response_size = params->len;
-	return ret;
-}
-DECLARE_HOST_COMMAND(EC_CMD_FP_PASSTHRU, fp_command_passthru, EC_VER_MASK(0));
-
-static enum ec_status fp_command_info(struct host_cmd_handler_args *args)
-{
-	struct ec_response_fp_info *r = args->response;
-
-#ifdef HAVE_FP_PRIVATE_DRIVER
-	if (fp_sensor_get_info(r) < 0)
-#endif
-		return EC_RES_UNAVAILABLE;
-
-	r->template_size = FP_ALGORITHM_ENCRYPTED_TEMPLATE_SIZE;
-	r->template_max = FP_MAX_FINGER_COUNT;
-	r->template_valid = templ_valid;
-	r->template_dirty = templ_dirty;
-	r->template_version = FP_TEMPLATE_FORMAT_VERSION;
-
-	/* V1 is identical to V0 with more information appended */
-	args->response_size = args->version ? sizeof(*r) :
-			sizeof(struct ec_response_fp_info_v0);
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_FP_INFO, fp_command_info,
-		     EC_VER_MASK(0) | EC_VER_MASK(1));
-
-BUILD_ASSERT(FP_CONTEXT_NONCE_BYTES == 12);
-
-int validate_fp_buffer_offset(const uint32_t buffer_size, const uint32_t offset,
-			      const uint32_t size)
-{
-	uint32_t bytes_requested;
-
-	if (check_add_overflow(size, offset, &bytes_requested))
-		return EC_ERROR_OVERFLOW;
-
-	if (bytes_requested > buffer_size)
-		return EC_ERROR_INVAL;
-
-	return EC_SUCCESS;
-}
-
-static enum ec_status fp_command_frame(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_fp_frame *params = args->params;
-	void *out = args->response;
-	uint32_t idx = FP_FRAME_GET_BUFFER_INDEX(params->offset);
-	uint32_t offset = params->offset & FP_FRAME_OFFSET_MASK;
-	uint32_t size = params->size;
-	uint32_t fgr;
-	uint8_t key[SBP_ENC_KEY_LEN];
-	struct ec_fp_template_encryption_metadata *enc_info;
-	int ret;
-
-	if (size > args->response_max)
-		return EC_RES_INVALID_PARAM;
-
-	if (idx == FP_FRAME_INDEX_RAW_IMAGE) {
-		/* The host requested a frame. */
-		if (system_is_locked())
-			return EC_RES_ACCESS_DENIED;
-		if (!is_raw_capture(sensor_mode))
-			offset += FP_SENSOR_IMAGE_OFFSET;
-
-		ret = validate_fp_buffer_offset(sizeof(fp_buffer), offset,
-						size);
-		if (ret != EC_SUCCESS)
-			return EC_RES_INVALID_PARAM;
-
-		memcpy(out, fp_buffer + offset, size);
-		args->response_size = size;
-		return EC_RES_SUCCESS;
-	}
-
-	/* The host requested a template. */
-
-	/* Templates are numbered from 1 in this host request. */
-	fgr = idx - FP_FRAME_INDEX_TEMPLATE;
-
-	if (fgr >= FP_MAX_FINGER_COUNT)
-		return EC_RES_INVALID_PARAM;
-	if (fgr >= templ_valid)
-		return EC_RES_UNAVAILABLE;
-	ret = validate_fp_buffer_offset(sizeof(fp_enc_buffer), offset, size);
-	if (ret != EC_SUCCESS)
-		return EC_RES_INVALID_PARAM;
-
-	if (!offset) {
-		/* Host has requested the first chunk, do the encryption. */
-		timestamp_t now = get_time();
-		/* Encrypted template is after the metadata. */
-		uint8_t *encrypted_template = fp_enc_buffer + sizeof(*enc_info);
-		/* Positive match salt is after the template. */
-		uint8_t *positive_match_salt =
-			encrypted_template + sizeof(fp_template[0]);
-		size_t encrypted_blob_size = sizeof(fp_template[0]) +
-					     sizeof(fp_positive_match_salt[0]);
-
-		/* b/114160734: Not more than 1 encrypted message per second. */
-		if (!timestamp_expired(encryption_deadline, &now))
-			return EC_RES_BUSY;
-		encryption_deadline.val = now.val + (1 * SECOND);
-
-		memset(fp_enc_buffer, 0, sizeof(fp_enc_buffer));
-		/*
-		 * The beginning of the buffer contains nonce, encryption_salt
-		 * and tag.
-		 */
-		enc_info = (void *)fp_enc_buffer;
-		enc_info->struct_version = FP_TEMPLATE_FORMAT_VERSION;
-		init_trng();
-		rand_bytes(enc_info->nonce, FP_CONTEXT_NONCE_BYTES);
-		rand_bytes(enc_info->encryption_salt,
-			   FP_CONTEXT_ENCRYPTION_SALT_BYTES);
-		exit_trng();
-
-		if (fgr == template_newly_enrolled) {
-			/*
-			 * Newly enrolled templates need new positive match
-			 * salt, new positive match secret and new validation
-			 * value.
-			 */
-			template_newly_enrolled = FP_NO_SUCH_TEMPLATE;
-			init_trng();
-			rand_bytes(fp_positive_match_salt[fgr],
-				   FP_POSITIVE_MATCH_SALT_BYTES);
-			exit_trng();
-		}
-
-		ret = derive_encryption_key(key, enc_info->encryption_salt);
-		if (ret != EC_SUCCESS) {
-			CPRINTS("fgr%d: Failed to derive key", fgr);
-			return EC_RES_UNAVAILABLE;
-		}
-
-		/*
-		 * Copy the payload to |fp_enc_buffer| where it will be
-		 * encrypted in-place.
-		 */
-		memcpy(encrypted_template, fp_template[fgr],
-		       sizeof(fp_template[0]));
-		memcpy(positive_match_salt, fp_positive_match_salt[fgr],
-		       sizeof(fp_positive_match_salt[0]));
-
-		/* Encrypt the secret blob in-place. */
-		ret = aes_gcm_encrypt(key, SBP_ENC_KEY_LEN, encrypted_template,
-				      encrypted_template,
-				      encrypted_blob_size,
-				      enc_info->nonce, FP_CONTEXT_NONCE_BYTES,
-				      enc_info->tag, FP_CONTEXT_TAG_BYTES);
-		always_memset(key, 0, sizeof(key));
-		if (ret != EC_SUCCESS) {
-			CPRINTS("fgr%d: Failed to encrypt template", fgr);
-			return EC_RES_UNAVAILABLE;
-		}
-		templ_dirty &= ~BIT(fgr);
-	}
-	memcpy(out, fp_enc_buffer + offset, size);
-	args->response_size = size;
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_FP_FRAME, fp_command_frame, EC_VER_MASK(0));
-
-static enum ec_status fp_command_stats(struct host_cmd_handler_args *args)
-{
-	struct ec_response_fp_stats *r = args->response;
-
-	r->capture_time_us = capture_time_us;
-	r->matching_time_us = matching_time_us;
-	r->overall_time_us = overall_time_us;
-	r->overall_t0.lo = overall_t0.le.lo;
-	r->overall_t0.hi = overall_t0.le.hi;
-	r->timestamps_invalid = timestamps_invalid;
-	/*
-	 * Note that this is set to FP_NO_SUCH_TEMPLATE when positive match
-	 * secret is read/disabled, and we are not using this field in biod.
-	 */
-	r->template_matched = positive_match_secret_state.template_matched;
-
-	args->response_size = sizeof(*r);
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_FP_STATS, fp_command_stats, EC_VER_MASK(0));
-
-static bool template_needs_validation_value(
-	struct ec_fp_template_encryption_metadata *enc_info)
-{
-	return enc_info->struct_version == 3
-		&& FP_TEMPLATE_FORMAT_VERSION == 4;
-}
-
-static int validate_template_format(
-	struct ec_fp_template_encryption_metadata *enc_info)
-{
-	if (template_needs_validation_value(enc_info))
-		/* The host requested migration to v4. */
-		return EC_RES_SUCCESS;
-
-	if (enc_info->struct_version != FP_TEMPLATE_FORMAT_VERSION) {
-		CPRINTS("Invalid template format %d", enc_info->struct_version);
-		return EC_RES_INVALID_PARAM;
-	}
-	return EC_RES_SUCCESS;
-}
-
-static enum ec_status fp_command_template(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_fp_template *params = args->params;
-	uint32_t size = params->size & ~FP_TEMPLATE_COMMIT;
-	int xfer_complete = params->size & FP_TEMPLATE_COMMIT;
-	uint32_t offset = params->offset;
-	uint32_t idx = templ_valid;
-	uint8_t key[SBP_ENC_KEY_LEN];
-	struct ec_fp_template_encryption_metadata *enc_info;
-	int ret;
-
-	/* Can we store one more template ? */
-	if (idx >= FP_MAX_FINGER_COUNT)
-		return EC_RES_OVERFLOW;
-
-	if (args->params_size !=
-	    size + offsetof(struct ec_params_fp_template, data))
-		return EC_RES_INVALID_PARAM;
-	ret = validate_fp_buffer_offset(sizeof(fp_enc_buffer), offset, size);
-	if (ret != EC_SUCCESS)
-		return EC_RES_INVALID_PARAM;
-
-	memcpy(&fp_enc_buffer[offset], params->data, size);
-
-	if (xfer_complete) {
-		/* Encrypted template is after the metadata. */
-		uint8_t *encrypted_template = fp_enc_buffer + sizeof(*enc_info);
-		/* Positive match salt is after the template. */
-		uint8_t *positive_match_salt =
-			encrypted_template + sizeof(fp_template[0]);
-		size_t encrypted_blob_size;
-
-		/*
-		 * The complete encrypted template has been received, start
-		 * decryption.
-		 */
-		fp_clear_finger_context(idx);
-		/*
-		 * The beginning of the buffer contains nonce, encryption_salt
-		 * and tag.
-		 */
-		enc_info = (void *)fp_enc_buffer;
-		ret = validate_template_format(enc_info);
-		if (ret != EC_RES_SUCCESS) {
-			CPRINTS("fgr%d: Template format not supported", idx);
-			return EC_RES_INVALID_PARAM;
-		}
-
-		if (enc_info->struct_version <= 3) {
-			encrypted_blob_size = sizeof(fp_template[0]);
-		} else {
-			encrypted_blob_size =
-				sizeof(fp_template[0]) +
-				sizeof(fp_positive_match_salt[0]);
-		}
-
-		ret = derive_encryption_key(key, enc_info->encryption_salt);
-		if (ret != EC_SUCCESS) {
-			CPRINTS("fgr%d: Failed to derive key", idx);
-			return EC_RES_UNAVAILABLE;
-		}
-
-		/* Decrypt the secret blob in-place. */
-		ret = aes_gcm_decrypt(key, SBP_ENC_KEY_LEN, encrypted_template,
-				      encrypted_template,
-				      encrypted_blob_size,
-				      enc_info->nonce, FP_CONTEXT_NONCE_BYTES,
-				      enc_info->tag, FP_CONTEXT_TAG_BYTES);
-		always_memset(key, 0, sizeof(key));
-		if (ret != EC_SUCCESS) {
-			CPRINTS("fgr%d: Failed to decipher template", idx);
-			/* Don't leave bad data in the template buffer */
-			fp_clear_finger_context(idx);
-			return EC_RES_UNAVAILABLE;
-		}
-		memcpy(fp_template[idx], encrypted_template,
-		       sizeof(fp_template[0]));
-		if (template_needs_validation_value(enc_info)) {
-			CPRINTS("fgr%d: Generating positive match salt.", idx);
-			init_trng();
-			rand_bytes(positive_match_salt,
-				   FP_POSITIVE_MATCH_SALT_BYTES);
-			exit_trng();
-		}
-		if (bytes_are_trivial(positive_match_salt,
-				      sizeof(fp_positive_match_salt[0]))) {
-			CPRINTS("fgr%d: Trivial positive match salt.", idx);
-			always_memset(fp_template[idx], 0,
-				      sizeof(fp_template[0]));
-			return EC_RES_INVALID_PARAM;
-		}
-		memcpy(fp_positive_match_salt[idx], positive_match_salt,
-		       sizeof(fp_positive_match_salt[0]));
-
-		templ_valid++;
-	}
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_FP_TEMPLATE, fp_command_template, EC_VER_MASK(0));
-
-#ifdef CONFIG_CMD_FPSENSOR_DEBUG
-/* --- Debug console commands --- */
-
-/*
- * Send the current Fingerprint buffer to the host
- * it is formatted as an 8-bpp PGM ASCII file.
- *
- * In addition, it prepends a short Z-Modem download signature,
- * which triggers automatically your preferred viewer if you configure it
- * properly in "File transfer protocols" in the Minicom options menu.
- * (as triggered by Ctrl-A O)
- * +--------------------------------------------------------------------------+
- * |     Name             Program             Name U/D FullScr IO-Red. Multi  |
- * | A  zmodem     /usr/bin/sz -vv -b          Y    U    N       Y       Y    |
- *  [...]
- * | L  pgm        /usr/bin/display_pgm        N    D    N       Y       N    |
- * | M  Zmodem download string activates... L                                 |
- *
- * My /usr/bin/display_pgm looks like this:
- * #!/bin/sh
- * TMPF=$(mktemp)
- * ascii-xfr -rdv ${TMPF}
- * display ${TMPF}
- *
- * Alternative (if you're using screen as your terminal):
- *
- * From *outside* the chroot:
- *
- * Install ascii-xfr: sudo apt-get install minicom
- * Install imagemagick: sudo apt-get install imagemagick
- *
- * Add the following to your ${HOME}/.screenrc:
- *
- * zmodem catch
- * zmodem recvcmd '!!! bash -c "ascii-xfr -rdv /tmp/finger.pgm && display /tmp/finger.pgm"'
- *
- * From *outside the chroot*, use screen to connect to UART console:
- *
- * sudo screen -c ${HOME}/.screenrc /dev/pts/NN 115200
- *
- */
-static void upload_pgm_image(uint8_t *frame)
-{
-	int x, y;
-	uint8_t *ptr = frame;
-
-	/* fake Z-modem ZRQINIT signature */
-	CPRINTF("#IGNORE for ZModem\r**\030B00");
-	msleep(2000); /* let the download program start */
-	/* Print 8-bpp PGM ASCII header */
-	CPRINTF("P2\n%d %d\n255\n", FP_SENSOR_RES_X, FP_SENSOR_RES_Y);
-
-	for (y = 0; y < FP_SENSOR_RES_Y; y++) {
-		watchdog_reload();
-		for (x = 0; x < FP_SENSOR_RES_X; x++, ptr++)
-			CPRINTF("%d ", *ptr);
-		CPRINTF("\n");
-		cflush();
-	}
-
-	CPRINTF("\x04"); /* End Of Transmission */
-}
-
-static enum ec_error_list fp_console_action(uint32_t mode)
-{
-	int tries = 200;
-	uint32_t mode_output = 0;
-	int rc = 0;
-
-	if (!(sensor_mode & FP_MODE_RESET_SENSOR))
-		CPRINTS("Waiting for finger ...");
-
-	rc = fp_set_sensor_mode(mode, &mode_output);
-
-	if (rc != EC_RES_SUCCESS) {
-		/*
-		 * EC host command errors do not directly map to console command
-		 * errors.
-		 */
-		return EC_ERROR_UNKNOWN;
-	}
-
-	while (tries--) {
-		if (!(sensor_mode & FP_MODE_ANY_CAPTURE)) {
-			CPRINTS("done (events:%x)", fp_events);
-			return 0;
-		}
-		usleep(100 * MSEC);
-	}
-	return EC_ERROR_TIMEOUT;
-}
-
-int command_fpcapture(int argc, char **argv)
-{
-	int capture_type = FP_CAPTURE_SIMPLE_IMAGE;
-	uint32_t mode;
-	enum ec_error_list rc;
-
-	/*
-	 * TODO(b/142944002): Remove this redundant check for system_is_locked
-	 * once we have unit-tests/integration-tests in place.
-	 */
-	if (system_is_locked())
-		return EC_ERROR_ACCESS_DENIED;
-
-	if (argc >= 2) {
-		char *e;
-
-		capture_type = strtoi(argv[1], &e, 0);
-		if (*e || capture_type < 0)
-			return EC_ERROR_PARAM1;
-	}
-	mode = FP_MODE_CAPTURE | ((capture_type << FP_MODE_CAPTURE_TYPE_SHIFT)
-				  & FP_MODE_CAPTURE_TYPE_MASK);
-
-	rc = fp_console_action(mode);
-	if (rc == EC_SUCCESS)
-		upload_pgm_image(fp_buffer + FP_SENSOR_IMAGE_OFFSET);
-
-	return rc;
-}
-DECLARE_CONSOLE_COMMAND_FLAGS(fpcapture, command_fpcapture, NULL,
-			      "Capture fingerprint in PGM format",
-			      CMD_FLAG_RESTRICTED);
-
-int command_fpenroll(int argc, char **argv)
-{
-	enum ec_error_list rc;
-	int percent = 0;
-	uint32_t event;
-	static const char * const enroll_str[] = {"OK", "Low Quality",
-						  "Immobile", "Low Coverage"};
-
-	/*
-	 * TODO(b/142944002): Remove this redundant check for system_is_locked
-	 * once we have unit-tests/integration-tests in place.
-	 */
-	if (system_is_locked())
-		return EC_ERROR_ACCESS_DENIED;
-
-	do {
-		int tries = 1000;
-
-		rc = fp_console_action(FP_MODE_ENROLL_SESSION |
-				       FP_MODE_ENROLL_IMAGE);
-		if (rc != EC_SUCCESS)
-			break;
-		event = deprecated_atomic_read_clear(&fp_events);
-		percent = EC_MKBP_FP_ENROLL_PROGRESS(event);
-		CPRINTS("Enroll capture: %s (%d%%)",
-			enroll_str[EC_MKBP_FP_ERRCODE(event) & 3], percent);
-		/* wait for finger release between captures */
-		sensor_mode = FP_MODE_ENROLL_SESSION | FP_MODE_FINGER_UP;
-		task_set_event(TASK_ID_FPSENSOR, TASK_EVENT_UPDATE_CONFIG, 0);
-		while (tries-- && sensor_mode & FP_MODE_FINGER_UP)
-			usleep(20 * MSEC);
-	} while (percent < 100);
-	sensor_mode = 0; /* reset FP_MODE_ENROLL_SESSION */
-	task_set_event(TASK_ID_FPSENSOR, TASK_EVENT_UPDATE_CONFIG, 0);
-
-	return rc;
-}
-DECLARE_CONSOLE_COMMAND_FLAGS(fpenroll, command_fpenroll, NULL,
-			      "Enroll a new fingerprint",
-			      CMD_FLAG_RESTRICTED);
-
-
-int command_fpmatch(int argc, char **argv)
-{
-	enum ec_error_list rc = fp_console_action(FP_MODE_MATCH);
-	uint32_t event = deprecated_atomic_read_clear(&fp_events);
-
-	if (rc == EC_SUCCESS && event & EC_MKBP_FP_MATCH) {
-		uint32_t errcode = EC_MKBP_FP_ERRCODE(event);
-
-		CPRINTS("Match: %s (%d)",
-			errcode & EC_MKBP_FP_ERR_MATCH_YES ? "YES" : "NO",
-			errcode);
-	}
-
-	return rc;
-}
-DECLARE_CONSOLE_COMMAND(fpmatch, command_fpmatch, NULL,
-			"Run match algorithm against finger");
-
-int command_fpclear(int argc, char **argv)
-{
-	/*
-	 * We intentionally run this on the fp_task so that we use the
-	 * same code path as host commands.
-	 */
-	enum ec_error_list rc = fp_console_action(FP_MODE_RESET_SENSOR);
-
-	if (rc < 0)
-		CPRINTS("Failed to clear fingerprint context: %d", rc);
-
-	deprecated_atomic_read_clear(&fp_events);
-
-	return rc;
-}
-DECLARE_CONSOLE_COMMAND(fpclear, command_fpclear, NULL,
-			"Clear fingerprint sensor context");
-
-int command_fpmaintenance(int argc, char **argv)
-{
-#ifdef HAVE_FP_PRIVATE_DRIVER
-	return fp_maintenance();
-#else
-	return EC_SUCCESS;
-#endif /* #ifdef HAVE_FP_PRIVATE_DRIVER */
-}
-DECLARE_CONSOLE_COMMAND(fpmaintenance, command_fpmaintenance, NULL,
-			"Run fingerprint sensor maintenance");
-
-#endif /* CONFIG_CMD_FPSENSOR_DEBUG */
diff --git a/common/fpsensor/fpsensor.cc b/common/fpsensor/fpsensor.cc
new file mode 100644
index 0000000000..27758492b6
--- /dev/null
+++ b/common/fpsensor/fpsensor.cc
@@ -0,0 +1,674 @@
+/* Copyright 2017 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "compile_time_macros.h"
+
+/* Boringssl headers need to be included before extern "C" section. */
+#include "openssl/mem.h"
+
+extern "C" {
+#include "atomic.h"
+#include "clock.h"
+#include "common.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "host_command.h"
+#include "link_defs.h"
+#include "mkbp_event.h"
+#include "overflow.h"
+#include "spi.h"
+#include "system.h"
+#include "task.h"
+#include "trng.h"
+#include "util.h"
+#include "watchdog.h"
+}
+
+#include "fpsensor.h"
+#include "fpsensor_crypto.h"
+#include "fpsensor_detect.h"
+#include "fpsensor_state.h"
+#include "fpsensor_utils.h"
+#include "scoped_fast_cpu.h"
+
+#if !defined(CONFIG_RNG)
+#error "fpsensor requires RNG"
+#endif
+
+#if defined(SECTION_IS_RO)
+#error "fpsensor code should not be in RO image."
+#endif
+
+/* Ready to encrypt a template. */
+static timestamp_t encryption_deadline;
+
+/* Delay between 2 s of the sensor to detect finger removal */
+#define FINGER_POLLING_DELAY (100 * MSEC)
+
+/* Timing statistics. */
+static uint32_t capture_time_us;
+static uint32_t matching_time_us;
+static uint32_t overall_time_us;
+static timestamp_t overall_t0;
+static uint8_t timestamps_invalid;
+
+BUILD_ASSERT(sizeof(struct ec_fp_template_encryption_metadata) % 4 == 0);
+
+/* Interrupt line from the fingerprint sensor */
+void fps_event(enum gpio_signal signal)
+{
+	task_set_event(TASK_ID_FPSENSOR, TASK_EVENT_SENSOR_IRQ);
+}
+
+static void send_mkbp_event(uint32_t event)
+{
+	atomic_or(&fp_events, event);
+	mkbp_send_event(EC_MKBP_EVENT_FINGERPRINT);
+}
+
+static inline int is_raw_capture(uint32_t mode)
+{
+	int capture_type = FP_CAPTURE_TYPE(mode);
+
+	return (capture_type == FP_CAPTURE_VENDOR_FORMAT ||
+		capture_type == FP_CAPTURE_QUALITY_TEST);
+}
+
+__maybe_unused bool fp_match_success(int match_result)
+{
+	return match_result == EC_MKBP_FP_ERR_MATCH_YES ||
+	       match_result == EC_MKBP_FP_ERR_MATCH_YES_UPDATED ||
+	       match_result == EC_MKBP_FP_ERR_MATCH_YES_UPDATE_FAILED;
+}
+
+#ifdef HAVE_FP_PRIVATE_DRIVER
+static inline int is_test_capture(uint32_t mode)
+{
+	int capture_type = FP_CAPTURE_TYPE(mode);
+
+	return (mode & FP_MODE_CAPTURE) &&
+	       (capture_type == FP_CAPTURE_PATTERN0 ||
+		capture_type == FP_CAPTURE_PATTERN1 ||
+		capture_type == FP_CAPTURE_RESET_TEST);
+}
+
+/*
+ * contains the bit FP_MODE_ENROLL_SESSION if a finger enrollment is on-going.
+ * It is used to detect the ENROLL_SESSION transition when sensor_mode is
+ * updated by the host.
+ */
+static uint32_t enroll_session;
+
+static uint32_t fp_process_enroll(void)
+{
+	int percent = 0;
+	int res;
+
+	if (template_newly_enrolled != FP_NO_SUCH_TEMPLATE)
+		CPRINTS("Warning: previously enrolled template has not been "
+			"read yet.");
+
+	/* begin/continue enrollment */
+	CPRINTS("[%d]Enrolling ...", templ_valid);
+	res = fp_finger_enroll(fp_buffer, &percent);
+	CPRINTS("[%d]Enroll =>%d (%d%%)", templ_valid, res, percent);
+	if (res < 0)
+		return EC_MKBP_FP_ENROLL |
+		       EC_MKBP_FP_ERRCODE(EC_MKBP_FP_ERR_ENROLL_INTERNAL);
+	templ_dirty |= BIT(templ_valid);
+	if (percent == 100) {
+		res = fp_enrollment_finish(fp_template[templ_valid]);
+		if (res) {
+			res = EC_MKBP_FP_ERR_ENROLL_INTERNAL;
+		} else {
+			template_newly_enrolled = templ_valid;
+			fp_enable_positive_match_secret(
+				templ_valid, &positive_match_secret_state);
+			templ_valid++;
+		}
+		sensor_mode &= ~FP_MODE_ENROLL_SESSION;
+		enroll_session &= ~FP_MODE_ENROLL_SESSION;
+	}
+	return EC_MKBP_FP_ENROLL | EC_MKBP_FP_ERRCODE(res) |
+	       (percent << EC_MKBP_FP_ENROLL_PROGRESS_OFFSET);
+}
+
+static uint32_t fp_process_match(void)
+{
+	timestamp_t t0 = get_time();
+	int res = -1;
+	uint32_t updated = 0;
+	int32_t fgr = FP_NO_SUCH_TEMPLATE;
+
+	/* match finger against current templates */
+	fp_disable_positive_match_secret(&positive_match_secret_state);
+	CPRINTS("Matching/%d ...", templ_valid);
+	if (templ_valid) {
+		res = fp_finger_match(fp_template[0], templ_valid, fp_buffer,
+				      &fgr, &updated);
+		CPRINTS("Match =>%d (finger %d)", res, fgr);
+
+		if (fp_match_success(res)) {
+			/*
+			 * Match succeded! Let's check if template number
+			 * is valid. If it is not valid, overwrite result
+			 * with EC_MKBP_FP_ERR_MATCH_NO_INTERNAL.
+			 */
+			if (fgr >= 0 && fgr < FP_MAX_FINGER_COUNT) {
+				fp_enable_positive_match_secret(
+					fgr, &positive_match_secret_state);
+			} else {
+				res = EC_MKBP_FP_ERR_MATCH_NO_INTERNAL;
+			}
+		} else if (res < 0) {
+			/*
+			 * Negative result means that there is a problem with
+			 * code responsible for matching. Overwrite it with
+			 * MATCH_NO_INTERNAL to let upper layers know what
+			 * happened.
+			 */
+			res = EC_MKBP_FP_ERR_MATCH_NO_INTERNAL;
+		}
+
+		if (res == EC_MKBP_FP_ERR_MATCH_YES_UPDATED)
+			templ_dirty |= updated;
+	} else {
+		CPRINTS("No enrolled templates");
+		res = EC_MKBP_FP_ERR_MATCH_NO_TEMPLATES;
+	}
+
+	if (!fp_match_success(res))
+		timestamps_invalid |= FPSTATS_MATCHING_INV;
+
+	matching_time_us = time_since32(t0);
+	return EC_MKBP_FP_MATCH | EC_MKBP_FP_ERRCODE(res) |
+	       ((fgr << EC_MKBP_FP_MATCH_IDX_OFFSET) &
+		EC_MKBP_FP_MATCH_IDX_MASK);
+}
+
+static void fp_process_finger(void)
+{
+	timestamp_t t0 = get_time();
+	int res;
+
+	CPRINTS("Capturing ...");
+	res = fp_sensor_acquire_image_with_mode(fp_buffer,
+						FP_CAPTURE_TYPE(sensor_mode));
+	capture_time_us = time_since32(t0);
+	if (!res) {
+		uint32_t evt = EC_MKBP_FP_IMAGE_READY;
+
+		/* Clean up SPI before clocking up to avoid hang on the dsb
+		 * in dma_go. Ignore the return value to let the WDT reboot
+		 * the MCU (and avoid getting trapped in the loop).
+		 * b/112781659 */
+		res = spi_transaction_flush(&spi_devices[0]);
+		if (res)
+			CPRINTS("Failed to flush SPI: 0x%x", res);
+
+		/* we need CPU power to do the computations */
+		ScopedFastCpu fast_cpu;
+
+		if (sensor_mode & FP_MODE_ENROLL_IMAGE)
+			evt = fp_process_enroll();
+		else if (sensor_mode & FP_MODE_MATCH)
+			evt = fp_process_match();
+
+		sensor_mode &= ~FP_MODE_ANY_CAPTURE;
+		overall_time_us = time_since32(overall_t0);
+		send_mkbp_event(evt);
+	} else {
+		timestamps_invalid |= FPSTATS_CAPTURE_INV;
+	}
+}
+#endif /* HAVE_FP_PRIVATE_DRIVER */
+
+extern "C" void fp_task(void)
+{
+	int timeout_us = -1;
+
+	CPRINTS("FP_SENSOR_SEL: %s",
+		fp_sensor_type_to_str(fpsensor_detect_get_type()));
+
+#ifdef HAVE_FP_PRIVATE_DRIVER
+	/* Reset and initialize the sensor IC */
+	fp_sensor_init();
+
+	while (1) {
+		uint32_t evt;
+		enum finger_state st = FINGER_NONE;
+
+		/* Wait for a sensor IRQ or a new mode configuration */
+		evt = task_wait_event(timeout_us);
+
+		if (evt & TASK_EVENT_UPDATE_CONFIG) {
+			uint32_t mode = sensor_mode;
+
+			gpio_disable_interrupt(GPIO_FPS_INT);
+			if ((mode ^ enroll_session) & FP_MODE_ENROLL_SESSION) {
+				if (mode & FP_MODE_ENROLL_SESSION) {
+					if (fp_enrollment_begin())
+						sensor_mode &=
+							~FP_MODE_ENROLL_SESSION;
+				} else {
+					fp_enrollment_finish(NULL);
+				}
+				enroll_session = sensor_mode &
+						 FP_MODE_ENROLL_SESSION;
+			}
+			if (is_test_capture(mode)) {
+				fp_sensor_acquire_image_with_mode(
+					fp_buffer, FP_CAPTURE_TYPE(mode));
+				sensor_mode &= ~FP_MODE_CAPTURE;
+				send_mkbp_event(EC_MKBP_FP_IMAGE_READY);
+				continue;
+			} else if (sensor_mode & FP_MODE_ANY_DETECT_FINGER) {
+				/* wait for a finger on the sensor */
+				fp_sensor_configure_detect();
+			}
+			if (sensor_mode & FP_MODE_DEEPSLEEP)
+				/* Shutdown the sensor */
+				fp_sensor_low_power();
+			if (sensor_mode & FP_MODE_FINGER_UP)
+				/* Poll the sensor to detect finger removal */
+				timeout_us = FINGER_POLLING_DELAY;
+			else
+				timeout_us = -1;
+			if (mode & FP_MODE_ANY_WAIT_IRQ) {
+				gpio_enable_interrupt(GPIO_FPS_INT);
+			} else if (mode & FP_MODE_RESET_SENSOR) {
+				fp_reset_and_clear_context();
+				sensor_mode &= ~FP_MODE_RESET_SENSOR;
+			} else if (mode & FP_MODE_SENSOR_MAINTENANCE) {
+				fp_maintenance();
+				sensor_mode &= ~FP_MODE_SENSOR_MAINTENANCE;
+			} else {
+				fp_sensor_low_power();
+			}
+		} else if (evt & (TASK_EVENT_SENSOR_IRQ | TASK_EVENT_TIMER)) {
+			overall_t0 = get_time();
+			timestamps_invalid = 0;
+			gpio_disable_interrupt(GPIO_FPS_INT);
+			if (sensor_mode & FP_MODE_ANY_DETECT_FINGER) {
+				st = fp_sensor_finger_status();
+				if (st == FINGER_PRESENT &&
+				    sensor_mode & FP_MODE_FINGER_DOWN) {
+					CPRINTS("Finger!");
+					sensor_mode &= ~FP_MODE_FINGER_DOWN;
+					send_mkbp_event(EC_MKBP_FP_FINGER_DOWN);
+				}
+				if (st == FINGER_NONE &&
+				    sensor_mode & FP_MODE_FINGER_UP) {
+					sensor_mode &= ~FP_MODE_FINGER_UP;
+					timeout_us = -1;
+					send_mkbp_event(EC_MKBP_FP_FINGER_UP);
+				}
+			}
+
+			if (st == FINGER_PRESENT &&
+			    sensor_mode & FP_MODE_ANY_CAPTURE)
+				fp_process_finger();
+
+			if (sensor_mode & FP_MODE_ANY_WAIT_IRQ) {
+				fp_sensor_configure_detect();
+				gpio_enable_interrupt(GPIO_FPS_INT);
+			} else {
+				fp_sensor_low_power();
+			}
+		}
+	}
+#else /* !HAVE_FP_PRIVATE_DRIVER */
+	while (1) {
+		uint32_t evt = task_wait_event(timeout_us);
+
+		send_mkbp_event(evt);
+	}
+#endif /* !HAVE_FP_PRIVATE_DRIVER */
+}
+
+static enum ec_status fp_command_passthru(struct host_cmd_handler_args *args)
+{
+	const auto *params =
+		static_cast<const ec_params_fp_passthru *>(args->params);
+	auto *out = static_cast<uint8_t *>(args->response);
+	int rc;
+	enum ec_status ret = EC_RES_SUCCESS;
+
+	if (system_is_locked())
+		return EC_RES_ACCESS_DENIED;
+
+	if (params->len >
+		    args->params_size +
+			    offsetof(struct ec_params_fp_passthru, data) ||
+	    params->len > args->response_max)
+		return EC_RES_INVALID_PARAM;
+
+	rc = spi_transaction_async(&spi_devices[0], params->data, params->len,
+				   out, SPI_READBACK_ALL);
+	if (params->flags & EC_FP_FLAG_NOT_COMPLETE)
+		rc |= spi_transaction_wait(&spi_devices[0]);
+	else
+		rc |= spi_transaction_flush(&spi_devices[0]);
+
+	if (rc == EC_ERROR_TIMEOUT)
+		ret = EC_RES_TIMEOUT;
+	else if (rc)
+		ret = EC_RES_ERROR;
+
+	args->response_size = params->len;
+	return ret;
+}
+DECLARE_HOST_COMMAND(EC_CMD_FP_PASSTHRU, fp_command_passthru, EC_VER_MASK(0));
+
+static enum ec_status fp_command_info(struct host_cmd_handler_args *args)
+{
+	auto *r = static_cast<ec_response_fp_info *>(args->response);
+
+#ifdef HAVE_FP_PRIVATE_DRIVER
+	if (fp_sensor_get_info(r) < 0)
+#endif
+		return EC_RES_UNAVAILABLE;
+
+	r->template_size = FP_ALGORITHM_ENCRYPTED_TEMPLATE_SIZE;
+	r->template_max = FP_MAX_FINGER_COUNT;
+	r->template_valid = templ_valid;
+	r->template_dirty = templ_dirty;
+	r->template_version = FP_TEMPLATE_FORMAT_VERSION;
+
+	/* V1 is identical to V0 with more information appended */
+	args->response_size = args->version ?
+				      sizeof(*r) :
+				      sizeof(struct ec_response_fp_info_v0);
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_FP_INFO, fp_command_info,
+		     EC_VER_MASK(0) | EC_VER_MASK(1));
+
+BUILD_ASSERT(FP_CONTEXT_NONCE_BYTES == 12);
+
+enum ec_error_list validate_fp_buffer_offset(const uint32_t buffer_size,
+					     const uint32_t offset,
+					     const uint32_t size)
+{
+	uint32_t bytes_requested;
+
+	if (check_add_overflow(size, offset, &bytes_requested))
+		return EC_ERROR_OVERFLOW;
+
+	if (bytes_requested > buffer_size)
+		return EC_ERROR_INVAL;
+
+	return EC_SUCCESS;
+}
+
+static enum ec_status fp_command_frame(struct host_cmd_handler_args *args)
+{
+	const auto *params =
+		static_cast<const struct ec_params_fp_frame *>(args->params);
+	void *out = args->response;
+	uint16_t idx = FP_FRAME_GET_BUFFER_INDEX(params->offset);
+	uint32_t offset = params->offset & FP_FRAME_OFFSET_MASK;
+	uint32_t size = params->size;
+	uint16_t fgr;
+	uint8_t key[SBP_ENC_KEY_LEN];
+	struct ec_fp_template_encryption_metadata *enc_info;
+	enum ec_error_list ret;
+
+	if (size > args->response_max)
+		return EC_RES_INVALID_PARAM;
+
+	if (idx == FP_FRAME_INDEX_RAW_IMAGE) {
+		/* The host requested a frame. */
+		if (system_is_locked())
+			return EC_RES_ACCESS_DENIED;
+		if (!is_raw_capture(sensor_mode))
+			offset += FP_SENSOR_IMAGE_OFFSET;
+
+		ret = validate_fp_buffer_offset(sizeof(fp_buffer), offset,
+						size);
+		if (ret != EC_SUCCESS)
+			return EC_RES_INVALID_PARAM;
+
+		memcpy(out, fp_buffer + offset, size);
+		args->response_size = size;
+		return EC_RES_SUCCESS;
+	}
+
+	/* The host requested a template. */
+
+	/* Templates are numbered from 1 in this host request. */
+	fgr = idx - FP_FRAME_INDEX_TEMPLATE;
+
+	if (fgr >= FP_MAX_FINGER_COUNT)
+		return EC_RES_INVALID_PARAM;
+	if (fgr >= templ_valid)
+		return EC_RES_UNAVAILABLE;
+	ret = validate_fp_buffer_offset(sizeof(fp_enc_buffer), offset, size);
+	if (ret != EC_SUCCESS)
+		return EC_RES_INVALID_PARAM;
+
+	if (!offset) {
+		ScopedFastCpu fast_cpu;
+
+		/* Host has requested the first chunk, do the encryption. */
+		timestamp_t now = get_time();
+		/* Encrypted template is after the metadata. */
+		uint8_t *encrypted_template = fp_enc_buffer + sizeof(*enc_info);
+		/* Positive match salt is after the template. */
+		uint8_t *positive_match_salt =
+			encrypted_template + sizeof(fp_template[0]);
+		size_t encrypted_blob_size = sizeof(fp_template[0]) +
+					     sizeof(fp_positive_match_salt[0]);
+
+		/* b/114160734: Not more than 1 encrypted message per second. */
+		if (!timestamp_expired(encryption_deadline, &now))
+			return EC_RES_BUSY;
+		encryption_deadline.val = now.val + (1 * SECOND);
+
+		memset(fp_enc_buffer, 0, sizeof(fp_enc_buffer));
+		/*
+		 * The beginning of the buffer contains nonce, encryption_salt
+		 * and tag.
+		 */
+		enc_info = reinterpret_cast<
+			struct ec_fp_template_encryption_metadata *>(
+			fp_enc_buffer);
+		enc_info->struct_version = FP_TEMPLATE_FORMAT_VERSION;
+		trng_init();
+		trng_rand_bytes(enc_info->nonce, FP_CONTEXT_NONCE_BYTES);
+		trng_rand_bytes(enc_info->encryption_salt,
+				FP_CONTEXT_ENCRYPTION_SALT_BYTES);
+		trng_exit();
+
+		if (fgr == template_newly_enrolled) {
+			/*
+			 * Newly enrolled templates need new positive match
+			 * salt, new positive match secret and new validation
+			 * value.
+			 */
+			template_newly_enrolled = FP_NO_SUCH_TEMPLATE;
+			trng_init();
+			trng_rand_bytes(fp_positive_match_salt[fgr],
+					FP_POSITIVE_MATCH_SALT_BYTES);
+			trng_exit();
+		}
+
+		ret = derive_encryption_key(key, enc_info->encryption_salt);
+		if (ret != EC_SUCCESS) {
+			CPRINTS("fgr%d: Failed to derive key", fgr);
+			return EC_RES_UNAVAILABLE;
+		}
+
+		/*
+		 * Copy the payload to |fp_enc_buffer| where it will be
+		 * encrypted in-place.
+		 */
+		memcpy(encrypted_template, fp_template[fgr],
+		       sizeof(fp_template[0]));
+		memcpy(positive_match_salt, fp_positive_match_salt[fgr],
+		       sizeof(fp_positive_match_salt[0]));
+
+		/* Encrypt the secret blob in-place. */
+		ret = aes_gcm_encrypt(key, SBP_ENC_KEY_LEN, encrypted_template,
+				      encrypted_template, encrypted_blob_size,
+				      enc_info->nonce, FP_CONTEXT_NONCE_BYTES,
+				      enc_info->tag, FP_CONTEXT_TAG_BYTES);
+		OPENSSL_cleanse(key, sizeof(key));
+		if (ret != EC_SUCCESS) {
+			CPRINTS("fgr%d: Failed to encrypt template", fgr);
+			return EC_RES_UNAVAILABLE;
+		}
+		templ_dirty &= ~BIT(fgr);
+	}
+	memcpy(out, fp_enc_buffer + offset, size);
+	args->response_size = size;
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_FP_FRAME, fp_command_frame, EC_VER_MASK(0));
+
+static enum ec_status fp_command_stats(struct host_cmd_handler_args *args)
+{
+	auto *r = static_cast<struct ec_response_fp_stats *>(args->response);
+
+	r->capture_time_us = capture_time_us;
+	r->matching_time_us = matching_time_us;
+	r->overall_time_us = overall_time_us;
+	r->overall_t0.lo = overall_t0.le.lo;
+	r->overall_t0.hi = overall_t0.le.hi;
+	r->timestamps_invalid = timestamps_invalid;
+	/*
+	 * Note that this is set to FP_NO_SUCH_TEMPLATE when positive match
+	 * secret is read/disabled, and we are not using this field in biod.
+	 */
+	r->template_matched = positive_match_secret_state.template_matched;
+
+	args->response_size = sizeof(*r);
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_FP_STATS, fp_command_stats, EC_VER_MASK(0));
+
+static bool template_needs_validation_value(
+	struct ec_fp_template_encryption_metadata *enc_info)
+{
+	return enc_info->struct_version == 3 && FP_TEMPLATE_FORMAT_VERSION == 4;
+}
+
+static enum ec_status
+validate_template_format(struct ec_fp_template_encryption_metadata *enc_info)
+{
+	if (template_needs_validation_value(enc_info))
+		/* The host requested migration to v4. */
+		return EC_RES_SUCCESS;
+
+	if (enc_info->struct_version != FP_TEMPLATE_FORMAT_VERSION) {
+		CPRINTS("Invalid template format %d", enc_info->struct_version);
+		return EC_RES_INVALID_PARAM;
+	}
+	return EC_RES_SUCCESS;
+}
+
+static enum ec_status fp_command_template(struct host_cmd_handler_args *args)
+{
+	const auto *params =
+		static_cast<const struct ec_params_fp_template *>(args->params);
+	uint32_t size = params->size & ~FP_TEMPLATE_COMMIT;
+	bool xfer_complete = params->size & FP_TEMPLATE_COMMIT;
+	uint32_t offset = params->offset;
+	uint16_t idx = templ_valid;
+	uint8_t key[SBP_ENC_KEY_LEN];
+	struct ec_fp_template_encryption_metadata *enc_info;
+
+	/* Can we store one more template ? */
+	if (idx >= FP_MAX_FINGER_COUNT)
+		return EC_RES_OVERFLOW;
+
+	if (args->params_size !=
+	    size + offsetof(struct ec_params_fp_template, data))
+		return EC_RES_INVALID_PARAM;
+	enum ec_error_list ret =
+		validate_fp_buffer_offset(sizeof(fp_enc_buffer), offset, size);
+	if (ret != EC_SUCCESS)
+		return EC_RES_INVALID_PARAM;
+
+	memcpy(&fp_enc_buffer[offset], params->data, size);
+
+	if (xfer_complete) {
+		ScopedFastCpu fast_cpu;
+
+		/* Encrypted template is after the metadata. */
+		uint8_t *encrypted_template = fp_enc_buffer + sizeof(*enc_info);
+		/* Positive match salt is after the template. */
+		uint8_t *positive_match_salt =
+			encrypted_template + sizeof(fp_template[0]);
+		size_t encrypted_blob_size;
+
+		/*
+		 * The complete encrypted template has been received, start
+		 * decryption.
+		 */
+		fp_clear_finger_context(idx);
+		/*
+		 * The beginning of the buffer contains nonce, encryption_salt
+		 * and tag.
+		 */
+		enc_info = (struct ec_fp_template_encryption_metadata *)
+			fp_enc_buffer;
+		enum ec_status res = validate_template_format(enc_info);
+		if (res != EC_RES_SUCCESS) {
+			CPRINTS("fgr%d: Template format not supported", idx);
+			return EC_RES_INVALID_PARAM;
+		}
+
+		if (enc_info->struct_version <= 3) {
+			encrypted_blob_size = sizeof(fp_template[0]);
+		} else {
+			encrypted_blob_size = sizeof(fp_template[0]) +
+					      sizeof(fp_positive_match_salt[0]);
+		}
+
+		ret = derive_encryption_key(key, enc_info->encryption_salt);
+		if (ret != EC_SUCCESS) {
+			CPRINTS("fgr%d: Failed to derive key", idx);
+			return EC_RES_UNAVAILABLE;
+		}
+
+		/* Decrypt the secret blob in-place. */
+		ret = aes_gcm_decrypt(key, SBP_ENC_KEY_LEN, encrypted_template,
+				      encrypted_template, encrypted_blob_size,
+				      enc_info->nonce, FP_CONTEXT_NONCE_BYTES,
+				      enc_info->tag, FP_CONTEXT_TAG_BYTES);
+		OPENSSL_cleanse(key, sizeof(key));
+		if (ret != EC_SUCCESS) {
+			CPRINTS("fgr%d: Failed to decipher template", idx);
+			/* Don't leave bad data in the template buffer */
+			fp_clear_finger_context(idx);
+			return EC_RES_UNAVAILABLE;
+		}
+		memcpy(fp_template[idx], encrypted_template,
+		       sizeof(fp_template[0]));
+		if (template_needs_validation_value(enc_info)) {
+			CPRINTS("fgr%d: Generating positive match salt.", idx);
+			trng_init();
+			trng_rand_bytes(positive_match_salt,
+					FP_POSITIVE_MATCH_SALT_BYTES);
+			trng_exit();
+		}
+		if (bytes_are_trivial(positive_match_salt,
+				      sizeof(fp_positive_match_salt[0]))) {
+			CPRINTS("fgr%d: Trivial positive match salt.", idx);
+			OPENSSL_cleanse(fp_template[idx],
+					sizeof(fp_template[0]));
+			return EC_RES_INVALID_PARAM;
+		}
+		memcpy(fp_positive_match_salt[idx], positive_match_salt,
+		       sizeof(fp_positive_match_salt[0]));
+
+		templ_valid++;
+	}
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_FP_TEMPLATE, fp_command_template, EC_VER_MASK(0));
diff --git a/common/fpsensor/fpsensor_auth_commands.cc b/common/fpsensor/fpsensor_auth_commands.cc
new file mode 100644
index 0000000000..4edc0f4083
--- /dev/null
+++ b/common/fpsensor/fpsensor_auth_commands.cc
@@ -0,0 +1,114 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "crypto/elliptic_curve_key.h"
+#include "ec_commands.h"
+#include "fpsensor.h"
+#include "fpsensor_auth_commands.h"
+#include "fpsensor_auth_crypto.h"
+#include "fpsensor_crypto.h"
+#include "fpsensor_state.h"
+#include "fpsensor_utils.h"
+#include "openssl/mem.h"
+#include "scoped_fast_cpu.h"
+
+#include <algorithm>
+#include <array>
+#include <utility>
+
+enum ec_error_list check_context_cleared()
+{
+	for (uint32_t partial : user_id)
+		if (partial != 0)
+			return EC_ERROR_ACCESS_DENIED;
+	if (templ_valid != 0)
+		return EC_ERROR_ACCESS_DENIED;
+	if (templ_dirty != 0)
+		return EC_ERROR_ACCESS_DENIED;
+	if (positive_match_secret_state.template_matched != FP_NO_SUCH_TEMPLATE)
+		return EC_ERROR_ACCESS_DENIED;
+	return EC_SUCCESS;
+}
+
+static enum ec_status
+fp_command_establish_pairing_key_keygen(struct host_cmd_handler_args *args)
+{
+	auto *r = static_cast<ec_response_fp_establish_pairing_key_keygen *>(
+		args->response);
+
+	ScopedFastCpu fast_cpu;
+
+	bssl::UniquePtr<EC_KEY> ecdh_key = generate_elliptic_curve_key();
+	if (ecdh_key == nullptr) {
+		return EC_RES_UNAVAILABLE;
+	}
+
+	std::optional<fp_encrypted_private_key> encrypted_private_key =
+		create_encrypted_private_key(*ecdh_key,
+					     FP_AES_KEY_ENC_METADATA_VERSION);
+	if (!encrypted_private_key.has_value()) {
+		CPRINTS("pairing_keygen: Failed to fill response encrypted private key");
+		return EC_RES_UNAVAILABLE;
+	}
+
+	r->encrypted_private_key = std::move(encrypted_private_key).value();
+
+	std::optional<fp_elliptic_curve_public_key> pubkey =
+		create_pubkey_from_ec_key(*ecdh_key);
+	if (!pubkey.has_value()) {
+		return EC_RES_UNAVAILABLE;
+	}
+
+	r->pubkey = std::move(pubkey).value();
+
+	args->response_size = sizeof(*r);
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_FP_ESTABLISH_PAIRING_KEY_KEYGEN,
+		     fp_command_establish_pairing_key_keygen, EC_VER_MASK(0));
+
+static enum ec_status
+fp_command_establish_pairing_key_wrap(struct host_cmd_handler_args *args)
+{
+	const auto *params =
+		static_cast<const ec_params_fp_establish_pairing_key_wrap *>(
+			args->params);
+	auto *r = static_cast<ec_response_fp_establish_pairing_key_wrap *>(
+		args->response);
+
+	ScopedFastCpu fast_cpu;
+
+	bssl::UniquePtr<EC_KEY> private_key =
+		decrypt_private_key(params->encrypted_private_key);
+	if (private_key == nullptr) {
+		return EC_RES_UNAVAILABLE;
+	}
+
+	bssl::UniquePtr<EC_KEY> public_key =
+		create_ec_key_from_pubkey(params->peers_pubkey);
+	if (public_key == nullptr) {
+		return EC_RES_UNAVAILABLE;
+	}
+
+	enum ec_error_list ret = generate_ecdh_shared_secret(
+		*private_key, *public_key, r->encrypted_pairing_key.data,
+		sizeof(r->encrypted_pairing_key.data));
+	if (ret != EC_SUCCESS) {
+		return EC_RES_UNAVAILABLE;
+	}
+
+	ret = encrypt_data_in_place(FP_AES_KEY_ENC_METADATA_VERSION,
+				    r->encrypted_pairing_key.info,
+				    r->encrypted_pairing_key.data,
+				    sizeof(r->encrypted_pairing_key.data));
+	if (ret != EC_SUCCESS) {
+		return EC_RES_UNAVAILABLE;
+	}
+
+	args->response_size = sizeof(*r);
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_FP_ESTABLISH_PAIRING_KEY_WRAP,
+		     fp_command_establish_pairing_key_wrap, EC_VER_MASK(0));
diff --git a/common/fpsensor/fpsensor_auth_crypto_stateful.cc b/common/fpsensor/fpsensor_auth_crypto_stateful.cc
new file mode 100644
index 0000000000..eea26226e7
--- /dev/null
+++ b/common/fpsensor/fpsensor_auth_crypto_stateful.cc
@@ -0,0 +1,130 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* TODO(b/286119221): refactor FPMCU code so that functions in this file don't
+ * rely on global state. */
+
+#include "compile_time_macros.h"
+
+/* Boringssl headers need to be included before extern "C" section. */
+#include "crypto/cleanse_wrapper.h"
+#include "crypto/elliptic_curve_key.h"
+#include "openssl/bn.h"
+#include "openssl/ec.h"
+#include "openssl/mem.h"
+#include "openssl/obj_mac.h"
+#include "openssl/rand.h"
+
+extern "C" {
+#include "ec_commands.h"
+#include "sha256.h"
+}
+
+#include "fpsensor_auth_crypto.h"
+#include "fpsensor_crypto.h"
+#include "fpsensor_state_without_driver_info.h"
+#include "fpsensor_utils.h"
+
+#include <array>
+
+enum ec_error_list
+encrypt_data_in_place(uint16_t version,
+		      struct fp_auth_command_encryption_metadata &info,
+		      uint8_t *data, size_t data_size)
+{
+	if (version != 1) {
+		return EC_ERROR_INVAL;
+	}
+
+	info.struct_version = version;
+	RAND_bytes(info.nonce, sizeof(info.nonce));
+	RAND_bytes(info.encryption_salt, sizeof(info.encryption_salt));
+
+	CleanseWrapper<std::array<uint8_t, SBP_ENC_KEY_LEN> > enc_key;
+	enum ec_error_list ret =
+		derive_encryption_key(enc_key.data(), info.encryption_salt);
+	if (ret != EC_SUCCESS) {
+		return ret;
+	}
+
+	/* Encrypt the secret blob in-place. */
+	ret = aes_gcm_encrypt(enc_key.data(), enc_key.size(), data, data,
+			      data_size, info.nonce, sizeof(info.nonce),
+			      info.tag, sizeof(info.tag));
+	if (ret != EC_SUCCESS) {
+		return ret;
+	}
+
+	return EC_SUCCESS;
+}
+
+std::optional<fp_encrypted_private_key>
+create_encrypted_private_key(const EC_KEY &key, uint16_t version)
+{
+	fp_encrypted_private_key enc_key;
+
+	if (EC_KEY_priv2oct(&key, enc_key.data, sizeof(enc_key.data)) !=
+	    sizeof(enc_key.data)) {
+		return std::nullopt;
+	}
+
+	if (encrypt_data_in_place(version, enc_key.info, enc_key.data,
+				  sizeof(enc_key.data)) != EC_SUCCESS) {
+		return std::nullopt;
+	}
+
+	return enc_key;
+}
+
+enum ec_error_list
+decrypt_data(const struct fp_auth_command_encryption_metadata &info,
+	     const uint8_t *enc_data, size_t enc_data_size, uint8_t *data,
+	     size_t data_size)
+{
+	if (info.struct_version != 1) {
+		return EC_ERROR_INVAL;
+	}
+
+	CleanseWrapper<std::array<uint8_t, SBP_ENC_KEY_LEN> > enc_key;
+	enum ec_error_list ret =
+		derive_encryption_key(enc_key.data(), info.encryption_salt);
+	if (ret != EC_SUCCESS) {
+		CPRINTS("Failed to derive key");
+		return ret;
+	}
+
+	if (enc_data_size != data_size) {
+		CPRINTS("Data size mismatch");
+		return EC_ERROR_OVERFLOW;
+	}
+
+	ret = aes_gcm_decrypt(enc_key.data(), enc_key.size(), data, enc_data,
+			      data_size, info.nonce, sizeof(info.nonce),
+			      info.tag, sizeof(info.tag));
+	if (ret != EC_SUCCESS) {
+		CPRINTS("Failed to decipher data");
+		return ret;
+	}
+
+	return EC_SUCCESS;
+}
+
+bssl::UniquePtr<EC_KEY> decrypt_private_key(
+	const struct fp_encrypted_private_key &encrypted_private_key)
+{
+	CleanseWrapper<std::array<uint8_t, sizeof(encrypted_private_key.data)> >
+		privkey;
+
+	enum ec_error_list ret = decrypt_data(
+		encrypted_private_key.info, encrypted_private_key.data,
+		sizeof(encrypted_private_key.data), privkey.data(),
+		privkey.size());
+	if (ret != EC_SUCCESS) {
+		CPRINTS("Failed to decrypt private key");
+		return nullptr;
+	}
+
+	return create_ec_key_from_privkey(privkey.data(), privkey.size());
+}
diff --git a/common/fpsensor/fpsensor_auth_crypto_stateless.cc b/common/fpsensor/fpsensor_auth_crypto_stateless.cc
new file mode 100644
index 0000000000..b4e33bd12e
--- /dev/null
+++ b/common/fpsensor/fpsensor_auth_crypto_stateless.cc
@@ -0,0 +1,224 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "compile_time_macros.h"
+
+#include <array>
+
+/* Boringssl headers need to be included before extern "C" section. */
+#include "crypto/cleanse_wrapper.h"
+#include "crypto/elliptic_curve_key.h"
+#include "openssl/aes.h"
+#include "openssl/bn.h"
+#include "openssl/ec.h"
+#include "openssl/ecdh.h"
+#include "openssl/mem.h"
+#include "openssl/obj_mac.h"
+#include "openssl/rand.h"
+
+extern "C" {
+#include "ec_commands.h"
+#include "sha256.h"
+}
+
+#include "fpsensor_auth_crypto.h"
+
+std::optional<fp_elliptic_curve_public_key>
+create_pubkey_from_ec_key(const EC_KEY &key)
+{
+	fp_elliptic_curve_public_key pubkey;
+	static_assert(sizeof(pubkey) == sizeof(pubkey.x) + sizeof(pubkey.y));
+
+	/* POINT_CONVERSION_UNCOMPRESSED indicates that the point is encoded as
+	 * z||x||y, where z is the octet 0x04. */
+	uint8_t *data = nullptr;
+	if (EC_KEY_key2buf(&key, POINT_CONVERSION_UNCOMPRESSED, &data,
+			   nullptr) !=
+	    sizeof(pubkey.x) + sizeof(pubkey.y) + 1) {
+		return std::nullopt;
+	}
+
+	bssl::UniquePtr<uint8_t> pubkey_data(data);
+	uint8_t *pubkey_ptr = reinterpret_cast<uint8_t *>(&pubkey);
+	std::copy(pubkey_data.get() + 1,
+		  pubkey_data.get() + 1 + sizeof(pubkey.x) + sizeof(pubkey.y),
+		  pubkey_ptr);
+
+	return pubkey;
+}
+
+bssl::UniquePtr<EC_KEY>
+create_ec_key_from_pubkey(const fp_elliptic_curve_public_key &pubkey)
+{
+	bssl::UniquePtr<BIGNUM> x_bn(
+		BN_bin2bn(pubkey.x, sizeof(pubkey.x), nullptr));
+	if (x_bn == nullptr) {
+		return nullptr;
+	}
+
+	bssl::UniquePtr<BIGNUM> y_bn(
+		BN_bin2bn(pubkey.y, sizeof(pubkey.y), nullptr));
+	if (y_bn == nullptr) {
+		return nullptr;
+	}
+
+	static_assert(sizeof(pubkey.x) == 32);
+	static_assert(sizeof(pubkey.y) == 32);
+	bssl::UniquePtr<EC_KEY> key(
+		EC_KEY_new_by_curve_name(NID_X9_62_prime256v1));
+	if (key == nullptr) {
+		return nullptr;
+	}
+
+	if (EC_KEY_set_public_key_affine_coordinates(key.get(), x_bn.get(),
+						     y_bn.get()) != 1) {
+		return nullptr;
+	}
+
+	return key;
+}
+
+bssl::UniquePtr<EC_KEY> create_ec_key_from_privkey(const uint8_t *privkey,
+						   size_t privkey_size)
+{
+	bssl::UniquePtr<EC_KEY> key(
+		EC_KEY_new_by_curve_name(NID_X9_62_prime256v1));
+	if (key == nullptr) {
+		return nullptr;
+	}
+
+	if (EC_KEY_oct2priv(key.get(), privkey, privkey_size) != 1) {
+		return nullptr;
+	}
+
+	return key;
+}
+
+enum ec_error_list generate_ecdh_shared_secret(const EC_KEY &private_key,
+					       const EC_KEY &public_key,
+					       uint8_t *shared_secret,
+					       uint8_t shared_secret_size)
+{
+	const EC_POINT *public_point = EC_KEY_get0_public_key(&public_key);
+	if (public_point == nullptr) {
+		return EC_ERROR_INVAL;
+	}
+
+	if (ECDH_compute_key_fips(shared_secret, shared_secret_size,
+				  public_point, &private_key) != 1) {
+		return EC_ERROR_INVAL;
+	}
+
+	return EC_SUCCESS;
+}
+
+enum ec_error_list
+generate_gsc_session_key(const uint8_t *auth_nonce, size_t auth_nonce_size,
+			 const uint8_t *gsc_nonce, size_t gsc_nonce_size,
+			 const uint8_t *pairing_key, size_t pairing_key_size,
+			 uint8_t *gsc_session_key, size_t gsc_session_key_size)
+{
+	if (auth_nonce_size != 32 || gsc_nonce_size != 32 ||
+	    pairing_key_size != 32 ||
+	    gsc_session_key_size != SHA256_DIGEST_SIZE) {
+		return EC_ERROR_INVAL;
+	}
+	CleanseWrapper<struct sha256_ctx> ctx;
+	SHA256_init(&ctx);
+	SHA256_update(&ctx, auth_nonce, auth_nonce_size);
+	SHA256_update(&ctx, gsc_nonce, gsc_nonce_size);
+	SHA256_update(&ctx, pairing_key, pairing_key_size);
+	uint8_t *result = SHA256_final(&ctx);
+
+	std::copy(result, result + SHA256_DIGEST_SIZE, gsc_session_key);
+
+	return EC_SUCCESS;
+}
+
+enum ec_error_list decrypt_data_with_gsc_session_key_in_place(
+	const uint8_t *gsc_session_key, size_t gsc_session_key_size,
+	const uint8_t *iv, size_t iv_size, uint8_t *data, size_t data_size)
+{
+	if (gsc_session_key_size != 32 || iv_size != AES_BLOCK_SIZE) {
+		return EC_ERROR_INVAL;
+	}
+
+	CleanseWrapper<AES_KEY> aes_key;
+	int res = AES_set_encrypt_key(gsc_session_key, 256, &aes_key);
+	if (res) {
+		return EC_ERROR_INVAL;
+	}
+
+	std::array<uint8_t, AES_BLOCK_SIZE> aes_iv;
+	std::copy(iv, iv + iv_size, aes_iv.begin());
+
+	/* The AES CTR uses the same function for encryption & decryption. */
+	unsigned int block_num = 0;
+	std::array<uint8_t, AES_BLOCK_SIZE> ecount_buf;
+	AES_ctr128_encrypt(data, data, data_size, &aes_key, aes_iv.data(),
+			   ecount_buf.data(), &block_num);
+
+	return EC_SUCCESS;
+}
+
+enum ec_error_list encrypt_data_with_ecdh_key_in_place(
+	const struct fp_elliptic_curve_public_key &in_pubkey, uint8_t *data,
+	size_t data_size, uint8_t *iv, size_t iv_size,
+	struct fp_elliptic_curve_public_key &out_pubkey)
+{
+	if (iv_size != AES_BLOCK_SIZE) {
+		return EC_ERROR_INVAL;
+	}
+
+	bssl::UniquePtr<EC_KEY> private_key = generate_elliptic_curve_key();
+	if (private_key == nullptr) {
+		return EC_ERROR_MEMORY_ALLOCATION;
+	}
+
+	std::optional<fp_elliptic_curve_public_key> out_key =
+		create_pubkey_from_ec_key(*private_key);
+	if (!out_key.has_value()) {
+		return EC_ERROR_INVAL;
+	}
+
+	out_pubkey = out_key.value();
+
+	bssl::UniquePtr<EC_KEY> public_key =
+		create_ec_key_from_pubkey(in_pubkey);
+	if (public_key == nullptr) {
+		return EC_ERROR_MEMORY_ALLOCATION;
+	}
+
+	CleanseWrapper<std::array<uint8_t, SHA256_DIGEST_SIZE> > enc_key;
+
+	enum ec_error_list ret = generate_ecdh_shared_secret(
+		*private_key, *public_key, enc_key.data(), enc_key.size());
+	if (ret != EC_SUCCESS) {
+		return ret;
+	}
+
+	CleanseWrapper<AES_KEY> aes_key;
+	int res = AES_set_encrypt_key(enc_key.data(), 256, &aes_key);
+	if (res) {
+		return EC_ERROR_INVAL;
+	}
+
+	RAND_bytes(iv, iv_size);
+
+	/* The IV will be changed after the AES_ctr128_encrypt, we need a copy
+	 * for that. */
+	std::array<uint8_t, AES_BLOCK_SIZE> aes_iv;
+
+	std::copy(iv, iv + iv_size, aes_iv.begin());
+
+	unsigned int block_num = 0;
+	std::array<uint8_t, AES_BLOCK_SIZE> ecount_buf;
+
+	/* The AES CTR uses the same function for encryption & decryption. */
+	AES_ctr128_encrypt(data, data, data_size, &aes_key, aes_iv.data(),
+			   ecount_buf.data(), &block_num);
+
+	return EC_SUCCESS;
+}
diff --git a/common/fpsensor/fpsensor_crypto.c b/common/fpsensor/fpsensor_crypto.c
deleted file mode 100644
index 73d7aca681..0000000000
--- a/common/fpsensor/fpsensor_crypto.c
+++ /dev/null
@@ -1,286 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#include <stdbool.h>
-
-#include "aes.h"
-#include "aes-gcm.h"
-#include "cryptoc/util.h"
-#include "fpsensor_crypto.h"
-#include "fpsensor_private.h"
-#include "fpsensor_state.h"
-#include "rollback.h"
-
-#if !defined(CONFIG_AES) || !defined(CONFIG_AES_GCM) || \
-	!defined(CONFIG_ROLLBACK_SECRET_SIZE)
-#error "fpsensor requires AES, AES_GCM and ROLLBACK_SECRET_SIZE"
-#endif
-
-static int get_ikm(uint8_t *ikm)
-{
-	int ret;
-
-	if (!fp_tpm_seed_is_set()) {
-		CPRINTS("Seed hasn't been set.");
-		return EC_ERROR_ACCESS_DENIED;
-	}
-
-	/*
-	 * The first CONFIG_ROLLBACK_SECRET_SIZE bytes of IKM are read from the
-	 * anti-rollback blocks.
-	 */
-	ret = rollback_get_secret(ikm);
-	if (ret != EC_SUCCESS) {
-		CPRINTS("Failed to read rollback secret: %d", ret);
-		return EC_ERROR_HW_INTERNAL;
-	}
-	/*
-	 * IKM is the concatenation of the rollback secret and the seed from
-	 * the TPM.
-	 */
-	memcpy(ikm + CONFIG_ROLLBACK_SECRET_SIZE, tpm_seed, sizeof(tpm_seed));
-
-	return EC_SUCCESS;
-}
-
-static void hkdf_extract(uint8_t *prk, const uint8_t *salt, size_t salt_size,
-			 const uint8_t *ikm, size_t ikm_size)
-{
-	/*
-	 * Derive a key with the "extract" step of HKDF
-	 * https://tools.ietf.org/html/rfc5869#section-2.2
-	 */
-	hmac_SHA256(prk, salt, salt_size, ikm, ikm_size);
-}
-
-static int hkdf_expand_one_step(uint8_t *out_key, size_t out_key_size,
-				uint8_t *prk, size_t prk_size,
-				uint8_t *info, size_t info_size)
-{
-	uint8_t key_buf[SHA256_DIGEST_SIZE];
-	uint8_t message_buf[SHA256_DIGEST_SIZE + 1];
-
-	if (out_key_size > SHA256_DIGEST_SIZE) {
-		CPRINTS("Deriving key material longer than SHA256_DIGEST_SIZE "
-			"requires more steps of HKDF expand.");
-		return EC_ERROR_INVAL;
-	}
-
-	if (info_size > SHA256_DIGEST_SIZE) {
-		CPRINTS("Info size too big for HKDF.");
-		return EC_ERROR_INVAL;
-	}
-
-	memcpy(message_buf, info, info_size);
-	/* 1 step, set the counter byte to 1. */
-	message_buf[info_size] = 0x01;
-	hmac_SHA256(key_buf, prk, prk_size, message_buf, info_size + 1);
-
-	memcpy(out_key, key_buf, out_key_size);
-	always_memset(key_buf, 0, sizeof(key_buf));
-
-	return EC_SUCCESS;
-}
-
-int hkdf_expand(uint8_t *out_key, size_t L, const uint8_t *prk,
-		size_t prk_size, const uint8_t *info, size_t info_size)
-{
-	/*
-	 * "Expand" step of HKDF.
-	 * https://tools.ietf.org/html/rfc5869#section-2.3
-	 */
-#define HASH_LEN SHA256_DIGEST_SIZE
-	uint8_t count = 1;
-	const uint8_t *T = out_key;
-	size_t T_len = 0;
-	uint8_t T_buffer[HASH_LEN];
-	/* Number of blocks. */
-	const uint32_t N = DIV_ROUND_UP(L, HASH_LEN);
-	uint8_t info_buffer[HASH_LEN + HKDF_MAX_INFO_SIZE + sizeof(count)];
-	bool arguments_valid = false;
-
-	if (out_key == NULL || L == 0)
-		CPRINTS("HKDF expand: output buffer not valid.");
-	else if (prk == NULL)
-		CPRINTS("HKDF expand: prk is NULL.");
-	else if (info == NULL && info_size > 0)
-		CPRINTS("HKDF expand: info is NULL but info size is not zero.");
-	else if (info_size > HKDF_MAX_INFO_SIZE)
-		CPRINTF("HKDF expand: info size larger than %d bytes.\n",
-			HKDF_MAX_INFO_SIZE);
-	else if (N > HKDF_SHA256_MAX_BLOCK_COUNT)
-		CPRINTS("HKDF expand: output key size too large.");
-	else
-		arguments_valid = true;
-
-	if (!arguments_valid)
-		return EC_ERROR_INVAL;
-
-	while (L > 0) {
-		const size_t block_size = L < HASH_LEN ? L : HASH_LEN;
-
-		memcpy(info_buffer, T, T_len);
-		memcpy(info_buffer + T_len, info, info_size);
-		info_buffer[T_len + info_size] = count;
-		hmac_SHA256(T_buffer, prk, prk_size, info_buffer,
-			    T_len + info_size + sizeof(count));
-		memcpy(out_key, T_buffer, block_size);
-
-		T += T_len;
-		T_len = HASH_LEN;
-		count++;
-		out_key += block_size;
-		L -= block_size;
-	}
-	always_memset(T_buffer, 0, sizeof(T_buffer));
-	always_memset(info_buffer, 0, sizeof(info_buffer));
-	return EC_SUCCESS;
-#undef HASH_LEN
-}
-
-int derive_positive_match_secret(uint8_t *output,
-				 const uint8_t *input_positive_match_salt)
-{
-	int ret;
-	uint8_t ikm[CONFIG_ROLLBACK_SECRET_SIZE + sizeof(tpm_seed)];
-	uint8_t prk[SHA256_DIGEST_SIZE];
-	static const char info_prefix[] = "positive_match_secret for user ";
-	uint8_t info[sizeof(info_prefix) - 1 + sizeof(user_id)];
-
-	if (bytes_are_trivial(input_positive_match_salt,
-			      FP_POSITIVE_MATCH_SALT_BYTES)) {
-		CPRINTS("Failed to derive positive match secret: "
-			"salt bytes are trivial.");
-		return EC_ERROR_INVAL;
-	}
-
-	ret = get_ikm(ikm);
-	if (ret != EC_SUCCESS) {
-		CPRINTS("Failed to get IKM: %d", ret);
-		return ret;
-	}
-
-	/* "Extract" step of HKDF. */
-	hkdf_extract(prk, input_positive_match_salt,
-		     FP_POSITIVE_MATCH_SALT_BYTES, ikm, sizeof(ikm));
-	always_memset(ikm, 0, sizeof(ikm));
-
-	memcpy(info, info_prefix, strlen(info_prefix));
-	memcpy(info + strlen(info_prefix), user_id, sizeof(user_id));
-
-	/* "Expand" step of HKDF. */
-	ret = hkdf_expand(output, FP_POSITIVE_MATCH_SECRET_BYTES, prk,
-			  sizeof(prk), info, sizeof(info));
-	always_memset(prk, 0, sizeof(prk));
-
-	/* Check that secret is not full of 0x00 or 0xff. */
-	if (bytes_are_trivial(output, FP_POSITIVE_MATCH_SECRET_BYTES)) {
-		CPRINTS("Failed to derive positive match secret: "
-			"derived secret bytes are trivial.");
-		ret = EC_ERROR_HW_INTERNAL;
-	}
-	return ret;
-}
-
-int derive_encryption_key(uint8_t *out_key, const uint8_t *salt)
-{
-	int ret;
-	uint8_t ikm[CONFIG_ROLLBACK_SECRET_SIZE + sizeof(tpm_seed)];
-	uint8_t prk[SHA256_DIGEST_SIZE];
-
-	BUILD_ASSERT(SBP_ENC_KEY_LEN <= SHA256_DIGEST_SIZE);
-	BUILD_ASSERT(SBP_ENC_KEY_LEN <= CONFIG_ROLLBACK_SECRET_SIZE);
-	BUILD_ASSERT(sizeof(user_id) == SHA256_DIGEST_SIZE);
-
-	ret = get_ikm(ikm);
-	if (ret != EC_SUCCESS) {
-		CPRINTS("Failed to get IKM: %d", ret);
-		return ret;
-	}
-
-	/* "Extract step of HKDF. */
-	hkdf_extract(prk, salt, FP_CONTEXT_ENCRYPTION_SALT_BYTES, ikm,
-		     sizeof(ikm));
-	always_memset(ikm, 0, sizeof(ikm));
-
-	/*
-	 * Only 1 "expand" step of HKDF since the size of the "info" context
-	 * (user_id in our case) is exactly SHA256_DIGEST_SIZE.
-	 * https://tools.ietf.org/html/rfc5869#section-2.3
-	 */
-	ret = hkdf_expand_one_step(out_key, SBP_ENC_KEY_LEN, prk, sizeof(prk),
-				   (uint8_t *)user_id, sizeof(user_id));
-	always_memset(prk, 0, sizeof(prk));
-
-	return ret;
-}
-
-int aes_gcm_encrypt(const uint8_t *key, int key_size,
-		    const uint8_t *plaintext,
-		    uint8_t *ciphertext, int text_size,
-		    const uint8_t *nonce, int nonce_size,
-		    uint8_t *tag, int tag_size)
-{
-	int res;
-	AES_KEY aes_key;
-	GCM128_CONTEXT ctx;
-
-	if (nonce_size != FP_CONTEXT_NONCE_BYTES) {
-		CPRINTS("Invalid nonce size %d bytes", nonce_size);
-		return EC_ERROR_INVAL;
-	}
-
-	res = AES_set_encrypt_key(key, 8 * key_size, &aes_key);
-	if (res) {
-		CPRINTS("Failed to set encryption key: %d", res);
-		return EC_ERROR_UNKNOWN;
-	}
-	CRYPTO_gcm128_init(&ctx, &aes_key, (block128_f)AES_encrypt, 0);
-	CRYPTO_gcm128_setiv(&ctx, &aes_key, nonce, nonce_size);
-	/* CRYPTO functions return 1 on success, 0 on error. */
-	res = CRYPTO_gcm128_encrypt(&ctx, &aes_key, plaintext, ciphertext,
-				    text_size);
-	if (!res) {
-		CPRINTS("Failed to encrypt: %d", res);
-		return EC_ERROR_UNKNOWN;
-	}
-	CRYPTO_gcm128_tag(&ctx, tag, tag_size);
-	return EC_SUCCESS;
-}
-
-int aes_gcm_decrypt(const uint8_t *key, int key_size, uint8_t *plaintext,
-		    const uint8_t *ciphertext, int text_size,
-		    const uint8_t *nonce, int nonce_size,
-		    const uint8_t *tag, int tag_size)
-{
-	int res;
-	AES_KEY aes_key;
-	GCM128_CONTEXT ctx;
-
-	if (nonce_size != FP_CONTEXT_NONCE_BYTES) {
-		CPRINTS("Invalid nonce size %d bytes", nonce_size);
-		return EC_ERROR_INVAL;
-	}
-
-	res = AES_set_encrypt_key(key, 8 * key_size, &aes_key);
-	if (res) {
-		CPRINTS("Failed to set decryption key: %d", res);
-		return EC_ERROR_UNKNOWN;
-	}
-	CRYPTO_gcm128_init(&ctx, &aes_key, (block128_f)AES_encrypt, 0);
-	CRYPTO_gcm128_setiv(&ctx, &aes_key, nonce, nonce_size);
-	/* CRYPTO functions return 1 on success, 0 on error. */
-	res = CRYPTO_gcm128_decrypt(&ctx, &aes_key, ciphertext, plaintext,
-				    text_size);
-	if (!res) {
-		CPRINTS("Failed to decrypt: %d", res);
-		return EC_ERROR_UNKNOWN;
-	}
-	res = CRYPTO_gcm128_finish(&ctx, tag, tag_size);
-	if (!res) {
-		CPRINTS("Found incorrect tag: %d", res);
-		return EC_ERROR_UNKNOWN;
-	}
-	return EC_SUCCESS;
-}
diff --git a/common/fpsensor/fpsensor_crypto.cc b/common/fpsensor/fpsensor_crypto.cc
new file mode 100644
index 0000000000..01ea91f73f
--- /dev/null
+++ b/common/fpsensor/fpsensor_crypto.cc
@@ -0,0 +1,315 @@
+/* Copyright 2019 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "aes_gcm_helpers.h"
+#include "fpsensor_crypto.h"
+#include "fpsensor_state_without_driver_info.h"
+#include "fpsensor_utils.h"
+#include "openssl/aes.h"
+#include "openssl/mem.h"
+
+/* These must be included after the "openssl/aes.h" */
+#include "crypto/fipsmodule/aes/internal.h"
+#include "crypto/fipsmodule/modes/internal.h"
+
+extern "C" {
+#include "rollback.h"
+#include "sha256.h"
+#include "util.h"
+
+test_mockable void compute_hmac_sha256(uint8_t *output, const uint8_t *key,
+				       const int key_len,
+				       const uint8_t *message,
+				       const int message_len);
+}
+
+#include <stdbool.h>
+
+#if !defined(CONFIG_BORINGSSL_CRYPTO) || !defined(CONFIG_ROLLBACK_SECRET_SIZE)
+#error "fpsensor requires CONFIG_BORINGSSL_CRYPTO and ROLLBACK_SECRET_SIZE"
+#endif
+
+test_export_static enum ec_error_list get_ikm(uint8_t *ikm)
+{
+	enum ec_error_list ret;
+
+	if (!fp_tpm_seed_is_set()) {
+		CPRINTS("Seed hasn't been set.");
+		return EC_ERROR_ACCESS_DENIED;
+	}
+
+	/*
+	 * The first CONFIG_ROLLBACK_SECRET_SIZE bytes of IKM are read from the
+	 * anti-rollback blocks.
+	 */
+	ret = rollback_get_secret(ikm);
+	if (ret != EC_SUCCESS) {
+		CPRINTS("Failed to read rollback secret: %d", ret);
+		return EC_ERROR_HW_INTERNAL;
+	}
+	/*
+	 * IKM is the concatenation of the rollback secret and the seed from
+	 * the TPM.
+	 */
+	memcpy(ikm + CONFIG_ROLLBACK_SECRET_SIZE, tpm_seed, sizeof(tpm_seed));
+
+	return EC_SUCCESS;
+}
+
+test_mockable void compute_hmac_sha256(uint8_t *output, const uint8_t *key,
+				       const int key_len,
+				       const uint8_t *message,
+				       const int message_len)
+{
+	hmac_SHA256(output, key, key_len, message, message_len);
+}
+
+static void hkdf_extract(uint8_t *prk, const uint8_t *salt, size_t salt_size,
+			 const uint8_t *ikm, size_t ikm_size)
+{
+	/*
+	 * Derive a key with the "extract" step of HKDF
+	 * https://tools.ietf.org/html/rfc5869#section-2.2
+	 */
+	compute_hmac_sha256(prk, salt, salt_size, ikm, ikm_size);
+}
+
+static enum ec_error_list hkdf_expand_one_step(uint8_t *out_key,
+					       size_t out_key_size,
+					       uint8_t *prk, size_t prk_size,
+					       uint8_t *info, size_t info_size)
+{
+	uint8_t key_buf[SHA256_DIGEST_SIZE];
+	uint8_t message_buf[SHA256_DIGEST_SIZE + 1];
+
+	if (out_key_size > SHA256_DIGEST_SIZE) {
+		CPRINTS("Deriving key material longer than SHA256_DIGEST_SIZE "
+			"requires more steps of HKDF expand.");
+		return EC_ERROR_INVAL;
+	}
+
+	if (info_size > SHA256_DIGEST_SIZE) {
+		CPRINTS("Info size too big for HKDF.");
+		return EC_ERROR_INVAL;
+	}
+
+	memcpy(message_buf, info, info_size);
+	/* 1 step, set the counter byte to 1. */
+	message_buf[info_size] = 0x01;
+	compute_hmac_sha256(key_buf, prk, prk_size, message_buf, info_size + 1);
+
+	memcpy(out_key, key_buf, out_key_size);
+	OPENSSL_cleanse(key_buf, sizeof(key_buf));
+
+	return EC_SUCCESS;
+}
+
+enum ec_error_list hkdf_expand(uint8_t *out_key, size_t L, const uint8_t *prk,
+			       size_t prk_size, const uint8_t *info,
+			       size_t info_size)
+{
+	/*
+	 * "Expand" step of HKDF.
+	 * https://tools.ietf.org/html/rfc5869#section-2.3
+	 */
+#define HASH_LEN SHA256_DIGEST_SIZE
+	uint8_t count = 1;
+	const uint8_t *T = out_key;
+	size_t T_len = 0;
+	uint8_t T_buffer[HASH_LEN];
+	/* Number of blocks. */
+	const uint32_t N = DIV_ROUND_UP(L, HASH_LEN);
+	uint8_t info_buffer[HASH_LEN + HKDF_MAX_INFO_SIZE + sizeof(count)];
+	bool arguments_valid = false;
+
+	if (out_key == NULL || L == 0)
+		CPRINTS("HKDF expand: output buffer not valid.");
+	else if (prk == NULL)
+		CPRINTS("HKDF expand: prk is NULL.");
+	else if (info == NULL && info_size > 0)
+		CPRINTS("HKDF expand: info is NULL but info size is not zero.");
+	else if (info_size > HKDF_MAX_INFO_SIZE)
+		CPRINTF("HKDF expand: info size larger than %d bytes.\n",
+			HKDF_MAX_INFO_SIZE);
+	else if (N > HKDF_SHA256_MAX_BLOCK_COUNT)
+		CPRINTS("HKDF expand: output key size too large.");
+	else
+		arguments_valid = true;
+
+	if (!arguments_valid)
+		return EC_ERROR_INVAL;
+
+	while (L > 0) {
+		const size_t block_size = L < HASH_LEN ? L : HASH_LEN;
+
+		memcpy(info_buffer, T, T_len);
+		memcpy(info_buffer + T_len, info, info_size);
+		info_buffer[T_len + info_size] = count;
+		compute_hmac_sha256(T_buffer, prk, prk_size, info_buffer,
+				    T_len + info_size + sizeof(count));
+		memcpy(out_key, T_buffer, block_size);
+
+		T += T_len;
+		T_len = HASH_LEN;
+		count++;
+		out_key += block_size;
+		L -= block_size;
+	}
+	OPENSSL_cleanse(T_buffer, sizeof(T_buffer));
+	OPENSSL_cleanse(info_buffer, sizeof(info_buffer));
+	return EC_SUCCESS;
+#undef HASH_LEN
+}
+
+enum ec_error_list
+derive_positive_match_secret(uint8_t *output,
+			     const uint8_t *input_positive_match_salt)
+{
+	enum ec_error_list ret;
+	uint8_t ikm[CONFIG_ROLLBACK_SECRET_SIZE + sizeof(tpm_seed)];
+	uint8_t prk[SHA256_DIGEST_SIZE];
+	static const char info_prefix[] = "positive_match_secret for user ";
+	uint8_t info[sizeof(info_prefix) - 1 + sizeof(user_id)];
+
+	if (bytes_are_trivial(input_positive_match_salt,
+			      FP_POSITIVE_MATCH_SALT_BYTES)) {
+		CPRINTS("Failed to derive positive match secret: "
+			"salt bytes are trivial.");
+		return EC_ERROR_INVAL;
+	}
+
+	ret = get_ikm(ikm);
+	if (ret != EC_SUCCESS) {
+		CPRINTS("Failed to get IKM: %d", ret);
+		return ret;
+	}
+
+	/* "Extract" step of HKDF. */
+	hkdf_extract(prk, input_positive_match_salt,
+		     FP_POSITIVE_MATCH_SALT_BYTES, ikm, sizeof(ikm));
+	OPENSSL_cleanse(ikm, sizeof(ikm));
+
+	memcpy(info, info_prefix, strlen(info_prefix));
+	memcpy(info + strlen(info_prefix), user_id, sizeof(user_id));
+
+	/* "Expand" step of HKDF. */
+	ret = hkdf_expand(output, FP_POSITIVE_MATCH_SECRET_BYTES, prk,
+			  sizeof(prk), info, sizeof(info));
+	OPENSSL_cleanse(prk, sizeof(prk));
+
+	/* Check that secret is not full of 0x00 or 0xff. */
+	if (bytes_are_trivial(output, FP_POSITIVE_MATCH_SECRET_BYTES)) {
+		CPRINTS("Failed to derive positive match secret: "
+			"derived secret bytes are trivial.");
+		ret = EC_ERROR_HW_INTERNAL;
+	}
+	return ret;
+}
+
+enum ec_error_list derive_encryption_key(uint8_t *out_key, const uint8_t *salt)
+{
+	enum ec_error_list ret;
+	uint8_t ikm[CONFIG_ROLLBACK_SECRET_SIZE + sizeof(tpm_seed)];
+	uint8_t prk[SHA256_DIGEST_SIZE];
+
+	BUILD_ASSERT(SBP_ENC_KEY_LEN <= SHA256_DIGEST_SIZE);
+	BUILD_ASSERT(SBP_ENC_KEY_LEN <= CONFIG_ROLLBACK_SECRET_SIZE);
+	BUILD_ASSERT(sizeof(user_id) == SHA256_DIGEST_SIZE);
+
+	ret = get_ikm(ikm);
+	if (ret != EC_SUCCESS) {
+		CPRINTS("Failed to get IKM: %d", ret);
+		return ret;
+	}
+
+	/* TODO (b/276344630): Replace with boringssl version. */
+	/* "Extract step of HKDF. */
+	hkdf_extract(prk, salt, FP_CONTEXT_ENCRYPTION_SALT_BYTES, ikm,
+		     sizeof(ikm));
+	OPENSSL_cleanse(ikm, sizeof(ikm));
+
+	/*
+	 * Only 1 "expand" step of HKDF since the size of the "info" context
+	 * (user_id in our case) is exactly SHA256_DIGEST_SIZE.
+	 * https://tools.ietf.org/html/rfc5869#section-2.3
+	 */
+	ret = hkdf_expand_one_step(out_key, SBP_ENC_KEY_LEN, prk, sizeof(prk),
+				   (uint8_t *)user_id, sizeof(user_id));
+	OPENSSL_cleanse(prk, sizeof(prk));
+
+	return ret;
+}
+
+enum ec_error_list aes_gcm_encrypt(const uint8_t *key, int key_size,
+				   const uint8_t *plaintext,
+				   uint8_t *ciphertext, int text_size,
+				   const uint8_t *nonce, int nonce_size,
+				   uint8_t *tag, int tag_size)
+{
+	int res;
+	AES_KEY aes_key;
+	GCM128_CONTEXT ctx;
+
+	if (nonce_size != FP_CONTEXT_NONCE_BYTES) {
+		CPRINTS("Invalid nonce size %d bytes", nonce_size);
+		return EC_ERROR_INVAL;
+	}
+
+	/* TODO(b/279950931): Use public boringssl API. */
+	res = AES_set_encrypt_key(key, 8 * key_size, &aes_key);
+	if (res) {
+		CPRINTS("Failed to set encryption key: %d", res);
+		return EC_ERROR_UNKNOWN;
+	}
+	CRYPTO_gcm128_init(&ctx, &aes_key, (block128_f)AES_encrypt, 0);
+	CRYPTO_gcm128_setiv(&ctx, &aes_key, nonce, nonce_size);
+	/* CRYPTO functions return 1 on success, 0 on error. */
+	res = CRYPTO_gcm128_encrypt(&ctx, &aes_key, plaintext, ciphertext,
+				    text_size);
+	if (!res) {
+		CPRINTS("Failed to encrypt: %d", res);
+		return EC_ERROR_UNKNOWN;
+	}
+	CRYPTO_gcm128_tag(&ctx, tag, tag_size);
+	return EC_SUCCESS;
+}
+
+enum ec_error_list aes_gcm_decrypt(const uint8_t *key, int key_size,
+				   uint8_t *plaintext,
+				   const uint8_t *ciphertext, int text_size,
+				   const uint8_t *nonce, int nonce_size,
+				   const uint8_t *tag, int tag_size)
+{
+	int res;
+	AES_KEY aes_key;
+	GCM128_CONTEXT ctx;
+
+	if (nonce_size != FP_CONTEXT_NONCE_BYTES) {
+		CPRINTS("Invalid nonce size %d bytes", nonce_size);
+		return EC_ERROR_INVAL;
+	}
+
+	/* TODO(b/279950931): Use public boringssl API. */
+	res = AES_set_encrypt_key(key, 8 * key_size, &aes_key);
+	if (res) {
+		CPRINTS("Failed to set decryption key: %d", res);
+		return EC_ERROR_UNKNOWN;
+	}
+	CRYPTO_gcm128_init(&ctx, &aes_key, (block128_f)AES_encrypt, 0);
+	CRYPTO_gcm128_setiv(&ctx, &aes_key, nonce, nonce_size);
+	/* CRYPTO functions return 1 on success, 0 on error. */
+	res = CRYPTO_gcm128_decrypt(&ctx, &aes_key, ciphertext, plaintext,
+				    text_size);
+	if (!res) {
+		CPRINTS("Failed to decrypt: %d", res);
+		return EC_ERROR_UNKNOWN;
+	}
+	res = CRYPTO_gcm128_finish(&ctx, tag, tag_size);
+	if (!res) {
+		CPRINTS("Found incorrect tag: %d", res);
+		return EC_ERROR_UNKNOWN;
+	}
+	return EC_SUCCESS;
+}
diff --git a/common/fpsensor/fpsensor_debug.cc b/common/fpsensor/fpsensor_debug.cc
new file mode 100644
index 0000000000..cdb79b944c
--- /dev/null
+++ b/common/fpsensor/fpsensor_debug.cc
@@ -0,0 +1,303 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "compile_time_macros.h"
+
+extern "C" {
+#include "atomic.h"
+#include "clock.h"
+#include "common.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "host_command.h"
+#include "link_defs.h"
+#include "mkbp_event.h"
+#include "overflow.h"
+#include "spi.h"
+#include "system.h"
+#include "task.h"
+#include "trng.h"
+#include "util.h"
+#include "watchdog.h"
+}
+
+#include "fpsensor.h"
+#include "fpsensor_crypto.h"
+#include "fpsensor_detect.h"
+#include "fpsensor_state.h"
+#include "fpsensor_utils.h"
+
+#ifdef CONFIG_CMD_FPSENSOR_DEBUG
+/* --- Debug console commands --- */
+
+/*
+ * Send the current Fingerprint buffer to the host
+ * it is formatted as an 8-bpp PGM ASCII file.
+ *
+ * In addition, it prepends a short Z-Modem download signature,
+ * which triggers automatically your preferred viewer if you configure it
+ * properly in "File transfer protocols" in the Minicom options menu.
+ * (as triggered by Ctrl-A O)
+ * +--------------------------------------------------------------------------+
+ * |     Name             Program             Name U/D FullScr IO-Red. Multi  |
+ * | A  zmodem     /usr/bin/sz -vv -b          Y    U    N       Y       Y    |
+ *  [...]
+ * | L  pgm        /usr/bin/display_pgm        N    D    N       Y       N    |
+ * | M  Zmodem download string activates... L                                 |
+ *
+ * My /usr/bin/display_pgm looks like this:
+ * #!/bin/sh
+ * TMPF=$(mktemp)
+ * ascii-xfr -rdv ${TMPF}
+ * display ${TMPF}
+ *
+ * Alternative (if you're using screen as your terminal):
+ *
+ * From *outside* the chroot:
+ *
+ * Install ascii-xfr: sudo apt-get install minicom
+ * Install imagemagick: sudo apt-get install imagemagick
+ *
+ * Add the following to your ${HOME}/.screenrc:
+ *
+ * zmodem catch
+ * zmodem recvcmd '!!! bash -c "ascii-xfr -rdv /tmp/finger.pgm && display
+ * /tmp/finger.pgm"'
+ *
+ * From *outside the chroot*, use screen to connect to UART console:
+ *
+ * sudo screen -c ${HOME}/.screenrc /dev/pts/NN 115200
+ *
+ */
+static void upload_pgm_image(uint8_t *frame)
+{
+	int x, y;
+	uint8_t *ptr = frame;
+
+	/* fake Z-modem ZRQINIT signature */
+	CPRINTF("#IGNORE for ZModem\r**\030B00");
+	msleep(2000); /* let the download program start */
+	/* Print 8-bpp PGM ASCII header */
+	CPRINTF("P2\n%d %d\n255\n", FP_SENSOR_RES_X, FP_SENSOR_RES_Y);
+
+	for (y = 0; y < FP_SENSOR_RES_Y; y++) {
+		watchdog_reload();
+		for (x = 0; x < FP_SENSOR_RES_X; x++, ptr++)
+			CPRINTF("%d ", *ptr);
+		CPRINTF("\n");
+		cflush();
+	}
+
+	CPRINTF("\x04"); /* End Of Transmission */
+}
+
+static enum ec_error_list fp_console_action(uint32_t mode)
+{
+	int tries = 200;
+	uint32_t mode_output = 0;
+	int rc = 0;
+
+	if (!(sensor_mode & FP_MODE_RESET_SENSOR))
+		CPRINTS("Waiting for finger ...");
+
+	rc = fp_set_sensor_mode(mode, &mode_output);
+
+	if (rc != EC_RES_SUCCESS) {
+		/*
+		 * EC host command errors do not directly map to console command
+		 * errors.
+		 */
+		return EC_ERROR_UNKNOWN;
+	}
+
+	while (tries--) {
+		if (!(sensor_mode & FP_MODE_ANY_CAPTURE)) {
+			CPRINTS("done (events:%x)", (int)fp_events);
+			return EC_SUCCESS;
+		}
+		usleep(100 * MSEC);
+	}
+	return EC_ERROR_TIMEOUT;
+}
+
+static int command_fpcapture(int argc, const char **argv)
+{
+	int capture_type = FP_CAPTURE_SIMPLE_IMAGE;
+	uint32_t mode;
+	enum ec_error_list rc;
+
+	/*
+	 * TODO(b/142944002): Remove this redundant check for system_is_locked
+	 * once we have unit-tests/integration-tests in place.
+	 */
+	if (system_is_locked())
+		return EC_ERROR_ACCESS_DENIED;
+
+	if (argc >= 2) {
+		char *e;
+
+		capture_type = strtoi(argv[1], &e, 0);
+		if (*e || capture_type < 0)
+			return EC_ERROR_PARAM1;
+	}
+	mode = FP_MODE_CAPTURE | ((capture_type << FP_MODE_CAPTURE_TYPE_SHIFT) &
+				  FP_MODE_CAPTURE_TYPE_MASK);
+
+	rc = fp_console_action(mode);
+	if (rc == EC_SUCCESS)
+		upload_pgm_image(fp_buffer + FP_SENSOR_IMAGE_OFFSET);
+
+	return rc;
+}
+DECLARE_CONSOLE_COMMAND_FLAGS(fpcapture, command_fpcapture, NULL,
+			      "Capture fingerprint in PGM format",
+			      CMD_FLAG_RESTRICTED);
+
+/* Transfer a chunk of the image from the host to the FPMCU
+ *
+ * Command format:
+ *  fpupload <offset> <hex encoded pixel string>
+ *
+ * To limit the size of the commands, only a chunk of the image is sent for
+ * each command invocation.
+ */
+static int command_fpupload(int argc, const char **argv)
+{
+	const char *pixels_str;
+	uint8_t *dest;
+	int offset;
+
+	if (argc != 3)
+		return EC_ERROR_PARAM1;
+	if (system_is_locked())
+		return EC_ERROR_ACCESS_DENIED;
+	offset = atoi(argv[1]);
+	if (offset < 0)
+		return EC_ERROR_PARAM1;
+	dest = fp_buffer + FP_SENSOR_IMAGE_OFFSET + offset;
+
+	pixels_str = argv[2];
+	while (*pixels_str) {
+		if (dest >= fp_buffer + FP_SENSOR_IMAGE_SIZE)
+			return EC_ERROR_PARAM1;
+		char hex_str[] = { pixels_str[0], pixels_str[1], '\0' };
+		*dest = static_cast<uint8_t>(strtol(hex_str, NULL, 16));
+		pixels_str += 2;
+		++dest;
+	}
+
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(fpupload, command_fpupload, NULL,
+			"Copy fp image onto fpmcu fpsensor buffer");
+
+/* Transfer an image from the FPMCU to the host
+ *
+ * Command format:
+ *  fpdownload
+ *
+ * This is useful to verify the data was transferred correctly. Note that it
+ * requires the terminal to be configured as explained in the comment above
+ * upload_pgm_image().
+ */
+static int command_fpdownload(int argc, const char **argv)
+{
+	if (system_is_locked())
+		return EC_ERROR_ACCESS_DENIED;
+
+	upload_pgm_image(fp_buffer + FP_SENSOR_IMAGE_OFFSET);
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(fpdownload, command_fpdownload, NULL,
+			"Copy fp image from fpmcu fpsensor buffer");
+
+static int command_fpenroll(int argc, const char **argv)
+{
+	enum ec_error_list rc;
+	int percent = 0;
+	uint32_t event;
+	static const char *const enroll_str[] = { "OK", "Low Quality",
+						  "Immobile", "Low Coverage" };
+
+	/*
+	 * TODO(b/142944002): Remove this redundant check for system_is_locked
+	 * once we have unit-tests/integration-tests in place.
+	 */
+	if (system_is_locked())
+		return EC_ERROR_ACCESS_DENIED;
+
+	do {
+		int tries = 1000;
+
+		rc = fp_console_action(FP_MODE_ENROLL_SESSION |
+				       FP_MODE_ENROLL_IMAGE);
+		if (rc != EC_SUCCESS)
+			break;
+		event = atomic_clear(&fp_events);
+		percent = EC_MKBP_FP_ENROLL_PROGRESS(event);
+		CPRINTS("Enroll capture: %s (%d%%)",
+			enroll_str[EC_MKBP_FP_ERRCODE(event) & 3], percent);
+		/* wait for finger release between captures */
+		sensor_mode = FP_MODE_ENROLL_SESSION | FP_MODE_FINGER_UP;
+		task_set_event(TASK_ID_FPSENSOR, TASK_EVENT_UPDATE_CONFIG);
+		while (tries-- && sensor_mode & FP_MODE_FINGER_UP)
+			usleep(20 * MSEC);
+	} while (percent < 100);
+	sensor_mode = 0; /* reset FP_MODE_ENROLL_SESSION */
+	task_set_event(TASK_ID_FPSENSOR, TASK_EVENT_UPDATE_CONFIG);
+
+	return rc;
+}
+DECLARE_CONSOLE_COMMAND_FLAGS(fpenroll, command_fpenroll, NULL,
+			      "Enroll a new fingerprint", CMD_FLAG_RESTRICTED);
+
+static int command_fpmatch(int argc, const char **argv)
+{
+	enum ec_error_list rc = fp_console_action(FP_MODE_MATCH);
+	uint32_t event = atomic_clear(&fp_events);
+
+	if (rc == EC_SUCCESS && event & EC_MKBP_FP_MATCH) {
+		uint32_t match_errcode = EC_MKBP_FP_ERRCODE(event);
+
+		CPRINTS("Match: %s (%d)",
+			fp_match_success(match_errcode) ? "YES" : "NO",
+			match_errcode);
+	}
+
+	return rc;
+}
+DECLARE_CONSOLE_COMMAND(fpmatch, command_fpmatch, NULL,
+			"Run match algorithm against finger");
+
+static int command_fpclear(int argc, const char **argv)
+{
+	/*
+	 * We intentionally run this on the fp_task so that we use the
+	 * same code path as host commands.
+	 */
+	enum ec_error_list rc = fp_console_action(FP_MODE_RESET_SENSOR);
+
+	if (rc != EC_SUCCESS)
+		CPRINTS("Failed to clear fingerprint context: %d", rc);
+
+	atomic_clear(&fp_events);
+
+	return rc;
+}
+DECLARE_CONSOLE_COMMAND(fpclear, command_fpclear, NULL,
+			"Clear fingerprint sensor context");
+
+static int command_fpmaintenance(int argc, const char **argv)
+{
+#ifdef HAVE_FP_PRIVATE_DRIVER
+	return fp_maintenance();
+#else
+	return EC_SUCCESS;
+#endif /* #ifdef HAVE_FP_PRIVATE_DRIVER */
+}
+DECLARE_CONSOLE_COMMAND(fpmaintenance, command_fpmaintenance, NULL,
+			"Run fingerprint sensor maintenance");
+
+#endif /* CONFIG_CMD_FPSENSOR_DEBUG */
diff --git a/common/fpsensor/fpsensor_detect_strings.c b/common/fpsensor/fpsensor_detect_strings.c
deleted file mode 100644
index b9bcf9bb3b..0000000000
--- a/common/fpsensor/fpsensor_detect_strings.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#include "fpsensor_detect.h"
-
-const char *fp_transport_type_to_str(enum fp_transport_type type)
-{
-	switch (type) {
-	case FP_TRANSPORT_TYPE_UNKNOWN:
-	default:
-		return "UNKNOWN";
-	case FP_TRANSPORT_TYPE_SPI:
-		return "SPI";
-	case FP_TRANSPORT_TYPE_UART:
-		return "UART";
-	}
-}
-
-const char *fp_sensor_type_to_str(enum fp_sensor_type type)
-{
-	switch (type) {
-	case FP_SENSOR_TYPE_UNKNOWN:
-	default:
-		return "UNKNOWN";
-	case FP_SENSOR_TYPE_FPC:
-		return "FPC";
-	case FP_SENSOR_TYPE_ELAN:
-		return "ELAN";
-	}
-}
-
diff --git a/common/fpsensor/fpsensor_detect_strings.cc b/common/fpsensor/fpsensor_detect_strings.cc
new file mode 100644
index 0000000000..af08219ced
--- /dev/null
+++ b/common/fpsensor/fpsensor_detect_strings.cc
@@ -0,0 +1,44 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "fpsensor_detect.h"
+
+const char *fp_transport_type_to_str(enum fp_transport_type type)
+{
+	switch (type) {
+	case FP_TRANSPORT_TYPE_UNKNOWN:
+	default:
+		return "UNKNOWN";
+	case FP_TRANSPORT_TYPE_SPI:
+		return "SPI";
+	case FP_TRANSPORT_TYPE_UART:
+		return "UART";
+	}
+}
+
+const char *fp_sensor_type_to_str(enum fp_sensor_type type)
+{
+	switch (type) {
+	case FP_SENSOR_TYPE_UNKNOWN:
+	default:
+		return "UNKNOWN";
+	case FP_SENSOR_TYPE_FPC:
+		return "FPC";
+	case FP_SENSOR_TYPE_ELAN:
+		return "ELAN";
+	}
+}
+
+const char *fp_sensor_spi_select_to_str(enum fp_sensor_spi_select type)
+{
+	switch (type) {
+	case FP_SENSOR_SPI_SELECT_UNKNOWN:
+	default:
+		return "UNKNOWN";
+	case FP_SENSOR_SPI_SELECT_DEVELOPMENT:
+		return "DEVELOPMENT";
+	case FP_SENSOR_SPI_SELECT_PRODUCTION:
+		return "PRODUCTION";
+	}
+}
diff --git a/common/fpsensor/fpsensor_private.h b/common/fpsensor/fpsensor_private.h
deleted file mode 100644
index a42049dece..0000000000
--- a/common/fpsensor/fpsensor_private.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Internal header file for common/fpsensor directory */
-
-#ifndef __CROS_EC_FPSENSOR_PRIVATE_H
-#define __CROS_EC_FPSENSOR_PRIVATE_H
-
-#include <stdint.h>
-
-#define CPRINTF(format, args...) cprintf(CC_FP, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_FP, format, ## args)
-
-int validate_fp_buffer_offset(uint32_t buffer_size, uint32_t offset,
-			      uint32_t size);
-
-#endif /* __CROS_EC_FPSENSOR_PRIVATE_H */
diff --git a/common/fpsensor/fpsensor_state.c b/common/fpsensor/fpsensor_state.c
deleted file mode 100644
index 82fa4f23a1..0000000000
--- a/common/fpsensor/fpsensor_state.c
+++ /dev/null
@@ -1,313 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "cryptoc/util.h"
-#include "ec_commands.h"
-#include "fpsensor.h"
-#include "fpsensor_crypto.h"
-#include "fpsensor_private.h"
-#include "fpsensor_state.h"
-#include "host_command.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-
-/* Last acquired frame (aligned as it is used by arbitrary binary libraries) */
-uint8_t fp_buffer[FP_SENSOR_IMAGE_SIZE] FP_FRAME_SECTION __aligned(4);
-/* Fingers templates for the current user */
-uint8_t fp_template[FP_MAX_FINGER_COUNT][FP_ALGORITHM_TEMPLATE_SIZE]
-	FP_TEMPLATE_SECTION;
-/* Encryption/decryption buffer */
-/* TODO: On-the-fly encryption/decryption without a dedicated buffer */
-/*
- * Store the encryption metadata at the beginning of the buffer containing the
- * ciphered data.
- */
-uint8_t fp_enc_buffer[FP_ALGORITHM_ENCRYPTED_TEMPLATE_SIZE]
-	FP_TEMPLATE_SECTION;
-/* Salt used in derivation of positive match secret. */
-uint8_t fp_positive_match_salt
-	[FP_MAX_FINGER_COUNT][FP_POSITIVE_MATCH_SALT_BYTES];
-
-struct positive_match_secret_state positive_match_secret_state = {
-	.template_matched = FP_NO_SUCH_TEMPLATE,
-	.readable = false,
-	.deadline.val = 0,
-};
-
-/* Index of the last enrolled but not retrieved template. */
-int8_t template_newly_enrolled = FP_NO_SUCH_TEMPLATE;
-/* Number of used templates */
-uint32_t templ_valid;
-/* Bitmap of the templates with local modifications */
-uint32_t templ_dirty;
-/* Current user ID */
-uint32_t user_id[FP_CONTEXT_USERID_WORDS];
-/* Part of the IKM used to derive encryption keys received from the TPM. */
-uint8_t tpm_seed[FP_CONTEXT_TPM_BYTES];
-/* Status of the FP encryption engine. */
-static uint32_t fp_encryption_status;
-
-uint32_t fp_events;
-
-uint32_t sensor_mode;
-
-void fp_task_simulate(void)
-{
-	int timeout_us = -1;
-
-	while (1)
-		task_wait_event(timeout_us);
-}
-
-void fp_clear_finger_context(int idx)
-{
-	always_memset(fp_template[idx], 0, sizeof(fp_template[0]));
-	always_memset(fp_positive_match_salt[idx], 0,
-		      sizeof(fp_positive_match_salt[0]));
-}
-
-/**
- * @warning |fp_buffer| contains data used by the matching algorithm that must
- * be released by calling fp_sensor_deinit() first. Call
- * fp_reset_and_clear_context instead of calling this directly.
- */
-static void _fp_clear_context(void)
-{
-	int idx;
-
-	templ_valid = 0;
-	templ_dirty = 0;
-	always_memset(fp_buffer, 0, sizeof(fp_buffer));
-	always_memset(fp_enc_buffer, 0, sizeof(fp_enc_buffer));
-	always_memset(user_id, 0, sizeof(user_id));
-	fp_disable_positive_match_secret(&positive_match_secret_state);
-	for (idx = 0; idx < FP_MAX_FINGER_COUNT; idx++)
-		fp_clear_finger_context(idx);
-}
-
-void fp_reset_and_clear_context(void)
-{
-	if (fp_sensor_deinit() != EC_SUCCESS)
-		CPRINTS("Failed to deinit sensor");
-	_fp_clear_context();
-	if (fp_sensor_init() != EC_SUCCESS)
-		CPRINTS("Failed to init sensor");
-}
-
-int fp_get_next_event(uint8_t *out)
-{
-	uint32_t event_out = deprecated_atomic_read_clear(&fp_events);
-
-	memcpy(out, &event_out, sizeof(event_out));
-
-	return sizeof(event_out);
-}
-DECLARE_EVENT_SOURCE(EC_MKBP_EVENT_FINGERPRINT, fp_get_next_event);
-
-static enum ec_status fp_command_tpm_seed(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_fp_seed *params = args->params;
-
-	if (params->struct_version != FP_TEMPLATE_FORMAT_VERSION) {
-		CPRINTS("Invalid seed format %d", params->struct_version);
-		return EC_RES_INVALID_PARAM;
-	}
-
-	if (fp_encryption_status & FP_ENC_STATUS_SEED_SET) {
-		CPRINTS("Seed has already been set.");
-		return EC_RES_ACCESS_DENIED;
-	}
-	memcpy(tpm_seed, params->seed, sizeof(tpm_seed));
-	fp_encryption_status |= FP_ENC_STATUS_SEED_SET;
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_FP_SEED, fp_command_tpm_seed, EC_VER_MASK(0));
-
-int fp_tpm_seed_is_set(void)
-{
-	return fp_encryption_status & FP_ENC_STATUS_SEED_SET;
-}
-
-static enum ec_status
-fp_command_encryption_status(struct host_cmd_handler_args *args)
-{
-	struct ec_response_fp_encryption_status *r = args->response;
-
-	r->valid_flags = FP_ENC_STATUS_SEED_SET;
-	r->status = fp_encryption_status;
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_FP_ENC_STATUS, fp_command_encryption_status,
-		     EC_VER_MASK(0));
-
-static int validate_fp_mode(const uint32_t mode)
-{
-	uint32_t capture_type = FP_CAPTURE_TYPE(mode);
-	uint32_t algo_mode = mode & ~FP_MODE_CAPTURE_TYPE_MASK;
-	uint32_t cur_mode = sensor_mode;
-
-	if (capture_type >= FP_CAPTURE_TYPE_MAX)
-		return EC_ERROR_INVAL;
-
-	if (algo_mode & ~FP_VALID_MODES)
-		return EC_ERROR_INVAL;
-
-	if ((mode & FP_MODE_ENROLL_SESSION) &&
-	    templ_valid >= FP_MAX_FINGER_COUNT) {
-		CPRINTS("Maximum number of fingers already enrolled: %d",
-			FP_MAX_FINGER_COUNT);
-		return EC_ERROR_INVAL;
-	}
-
-	/* Don't allow sensor reset if any other mode is
-	 * set (including FP_MODE_RESET_SENSOR itself).
-	 */
-	if (mode & FP_MODE_RESET_SENSOR) {
-		if (cur_mode & FP_VALID_MODES)
-			return EC_ERROR_INVAL;
-	}
-
-	return EC_SUCCESS;
-}
-
-int fp_set_sensor_mode(uint32_t mode, uint32_t *mode_output)
-{
-	int ret;
-
-	if (mode_output == NULL)
-		return EC_RES_INVALID_PARAM;
-
-	ret = validate_fp_mode(mode);
-	if (ret != EC_SUCCESS) {
-		CPRINTS("Invalid FP mode 0x%x", mode);
-		return EC_RES_INVALID_PARAM;
-	}
-
-	if (!(mode & FP_MODE_DONT_CHANGE)) {
-		sensor_mode = mode;
-		task_set_event(TASK_ID_FPSENSOR, TASK_EVENT_UPDATE_CONFIG, 0);
-	}
-
-	*mode_output = sensor_mode;
-	return EC_RES_SUCCESS;
-}
-
-static enum ec_status fp_command_mode(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_fp_mode *p = args->params;
-	struct ec_response_fp_mode *r = args->response;
-
-	int ret = fp_set_sensor_mode(p->mode, &r->mode);
-
-	if (ret == EC_RES_SUCCESS)
-		args->response_size = sizeof(*r);
-
-	return ret;
-}
-DECLARE_HOST_COMMAND(EC_CMD_FP_MODE, fp_command_mode, EC_VER_MASK(0));
-
-static enum ec_status fp_command_context(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_fp_context_v1 *p = args->params;
-	uint32_t mode_output;
-
-	switch (p->action) {
-	case FP_CONTEXT_ASYNC:
-		if (sensor_mode & FP_MODE_RESET_SENSOR)
-			return EC_RES_BUSY;
-
-		/**
-		 * Trigger a call to fp_reset_and_clear_context() by
-		 * requesting a reset. Since that function triggers a call to
-		 * fp_sensor_open(), this must be asynchronous because
-		 * fp_sensor_open() can take ~175 ms. See http://b/137288498.
-		 */
-		return fp_set_sensor_mode(FP_MODE_RESET_SENSOR, &mode_output);
-
-	case FP_CONTEXT_GET_RESULT:
-		if (sensor_mode & FP_MODE_RESET_SENSOR)
-			return EC_RES_BUSY;
-
-		memcpy(user_id, p->userid, sizeof(user_id));
-		return EC_RES_SUCCESS;
-	}
-
-	return EC_RES_INVALID_PARAM;
-}
-DECLARE_HOST_COMMAND(EC_CMD_FP_CONTEXT, fp_command_context, EC_VER_MASK(1));
-
-int fp_enable_positive_match_secret(uint32_t fgr,
-				    struct positive_match_secret_state *state)
-{
-	timestamp_t now;
-
-	if (state->readable) {
-		CPRINTS("Error: positive match secret already readable.");
-		fp_disable_positive_match_secret(state);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	now = get_time();
-	state->template_matched = fgr;
-	state->readable = true;
-	state->deadline.val = now.val + (5 * SECOND);
-	return EC_SUCCESS;
-}
-
-void fp_disable_positive_match_secret(
-	struct positive_match_secret_state *state)
-{
-	state->template_matched = FP_NO_SUCH_TEMPLATE;
-	state->readable = false;
-	state->deadline.val = 0;
-}
-
-static enum ec_status fp_command_read_match_secret(
-	struct host_cmd_handler_args *args)
-{
-	const struct ec_params_fp_read_match_secret *params = args->params;
-	struct ec_response_fp_read_match_secret *response = args->response;
-	int8_t fgr = params->fgr;
-	timestamp_t now = get_time();
-	struct positive_match_secret_state state_copy
-		= positive_match_secret_state;
-
-	fp_disable_positive_match_secret(&positive_match_secret_state);
-
-	if (fgr < 0 || fgr >= FP_MAX_FINGER_COUNT) {
-		CPRINTS("Invalid finger number %d", fgr);
-		return EC_RES_INVALID_PARAM;
-	}
-	if (timestamp_expired(state_copy.deadline, &now)) {
-		CPRINTS("Reading positive match secret disallowed: "
-			"deadline has passed.");
-		return EC_RES_TIMEOUT;
-	}
-	if (fgr != state_copy.template_matched || !state_copy.readable) {
-		CPRINTS("Positive match secret for finger %d is not meant to "
-			"be read now.", fgr);
-		return EC_RES_ACCESS_DENIED;
-	}
-
-	if (derive_positive_match_secret(response->positive_match_secret,
-					 fp_positive_match_salt[fgr])
-		!= EC_SUCCESS) {
-		CPRINTS("Failed to derive positive match secret for finger %d",
-			fgr);
-		/* Keep the template and encryption salt. */
-		return EC_RES_ERROR;
-	}
-	CPRINTS("Derived positive match secret for finger %d", fgr);
-	args->response_size = sizeof(*response);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_FP_READ_MATCH_SECRET, fp_command_read_match_secret,
-		     EC_VER_MASK(0));
diff --git a/common/fpsensor/fpsensor_state.cc b/common/fpsensor/fpsensor_state.cc
new file mode 100644
index 0000000000..453d982eab
--- /dev/null
+++ b/common/fpsensor/fpsensor_state.cc
@@ -0,0 +1,312 @@
+/* Copyright 2019 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "compile_time_macros.h"
+
+/* Boringssl headers need to be included before extern "C" section. */
+#include "openssl/mem.h"
+
+extern "C" {
+#include "atomic.h"
+#include "common.h"
+#include "ec_commands.h"
+#include "host_command.h"
+#include "system.h"
+#include "task.h"
+#include "util.h"
+}
+
+#include "fpsensor.h"
+#include "fpsensor_crypto.h"
+#include "fpsensor_state.h"
+#include "fpsensor_utils.h"
+
+/* Last acquired frame (aligned as it is used by arbitrary binary libraries) */
+uint8_t fp_buffer[FP_SENSOR_IMAGE_SIZE] FP_FRAME_SECTION __aligned(4);
+/* Fingers templates for the current user */
+uint8_t fp_template[FP_MAX_FINGER_COUNT]
+		   [FP_ALGORITHM_TEMPLATE_SIZE] FP_TEMPLATE_SECTION;
+/* Encryption/decryption buffer */
+/* TODO: On-the-fly encryption/decryption without a dedicated buffer */
+/*
+ * Store the encryption metadata at the beginning of the buffer containing the
+ * ciphered data.
+ */
+uint8_t fp_enc_buffer[FP_ALGORITHM_ENCRYPTED_TEMPLATE_SIZE] FP_TEMPLATE_SECTION;
+/* Salt used in derivation of positive match secret. */
+uint8_t fp_positive_match_salt[FP_MAX_FINGER_COUNT]
+			      [FP_POSITIVE_MATCH_SALT_BYTES];
+
+void fp_task_simulate(void)
+{
+	int timeout_us = -1;
+
+	while (1)
+		task_wait_event(timeout_us);
+}
+
+void fp_clear_finger_context(uint16_t idx)
+{
+	OPENSSL_cleanse(fp_template[idx], sizeof(fp_template[0]));
+	OPENSSL_cleanse(fp_positive_match_salt[idx],
+			sizeof(fp_positive_match_salt[0]));
+}
+
+/**
+ * @warning |fp_buffer| contains data used by the matching algorithm that must
+ * be released by calling fp_sensor_deinit() first. Call
+ * fp_reset_and_clear_context instead of calling this directly.
+ */
+static void _fp_clear_context(void)
+{
+	templ_valid = 0;
+	templ_dirty = 0;
+	OPENSSL_cleanse(fp_buffer, sizeof(fp_buffer));
+	OPENSSL_cleanse(fp_enc_buffer, sizeof(fp_enc_buffer));
+	OPENSSL_cleanse(user_id, sizeof(user_id));
+	fp_disable_positive_match_secret(&positive_match_secret_state);
+	for (uint16_t idx = 0; idx < FP_MAX_FINGER_COUNT; idx++)
+		fp_clear_finger_context(idx);
+}
+
+void fp_reset_and_clear_context(void)
+{
+	if (fp_sensor_deinit() != EC_SUCCESS)
+		CPRINTS("Failed to deinit sensor");
+	_fp_clear_context();
+	if (fp_sensor_init() != EC_SUCCESS)
+		CPRINTS("Failed to init sensor");
+}
+
+int fp_get_next_event(uint8_t *out)
+{
+	uint32_t event_out = atomic_clear(&fp_events);
+
+	memcpy(out, &event_out, sizeof(event_out));
+
+	return sizeof(event_out);
+}
+DECLARE_EVENT_SOURCE(EC_MKBP_EVENT_FINGERPRINT, fp_get_next_event);
+
+static enum ec_status fp_command_tpm_seed(struct host_cmd_handler_args *args)
+{
+	const auto *params =
+		static_cast<const ec_params_fp_seed *>(args->params);
+
+	if (params->struct_version != FP_TEMPLATE_FORMAT_VERSION) {
+		CPRINTS("Invalid seed format %d", params->struct_version);
+		return EC_RES_INVALID_PARAM;
+	}
+
+	if (fp_encryption_status & FP_ENC_STATUS_SEED_SET) {
+		CPRINTS("Seed has already been set.");
+		return EC_RES_ACCESS_DENIED;
+	}
+	memcpy(tpm_seed, params->seed, sizeof(tpm_seed));
+	fp_encryption_status |= FP_ENC_STATUS_SEED_SET;
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_FP_SEED, fp_command_tpm_seed, EC_VER_MASK(0));
+
+static enum ec_status
+fp_command_encryption_status(struct host_cmd_handler_args *args)
+{
+	auto *r =
+		static_cast<ec_response_fp_encryption_status *>(args->response);
+
+	r->valid_flags = FP_ENC_STATUS_SEED_SET;
+	r->status = fp_encryption_status;
+	args->response_size = sizeof(*r);
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_FP_ENC_STATUS, fp_command_encryption_status,
+		     EC_VER_MASK(0));
+
+static int validate_fp_mode(const uint32_t mode)
+{
+	uint32_t capture_type = FP_CAPTURE_TYPE(mode);
+	uint32_t algo_mode = mode & ~FP_MODE_CAPTURE_TYPE_MASK;
+	uint32_t cur_mode = sensor_mode;
+
+	if (capture_type >= FP_CAPTURE_TYPE_MAX)
+		return EC_ERROR_INVAL;
+
+	if (algo_mode & ~FP_VALID_MODES)
+		return EC_ERROR_INVAL;
+
+	if ((mode & FP_MODE_ENROLL_SESSION) &&
+	    templ_valid >= FP_MAX_FINGER_COUNT) {
+		CPRINTS("Maximum number of fingers already enrolled: %d",
+			FP_MAX_FINGER_COUNT);
+		return EC_ERROR_INVAL;
+	}
+
+	/* Don't allow sensor reset if any other mode is
+	 * set (including FP_MODE_RESET_SENSOR itself).
+	 */
+	if (mode & FP_MODE_RESET_SENSOR) {
+		if (cur_mode & FP_VALID_MODES)
+			return EC_ERROR_INVAL;
+	}
+
+	return EC_SUCCESS;
+}
+
+enum ec_status fp_set_sensor_mode(uint32_t mode, uint32_t *mode_output)
+{
+	int ret;
+
+	if (mode_output == NULL)
+		return EC_RES_INVALID_PARAM;
+
+	ret = validate_fp_mode(mode);
+	if (ret != EC_SUCCESS) {
+		CPRINTS("Invalid FP mode 0x%x", mode);
+		return EC_RES_INVALID_PARAM;
+	}
+
+	if (!(mode & FP_MODE_DONT_CHANGE)) {
+		sensor_mode = mode;
+		task_set_event(TASK_ID_FPSENSOR, TASK_EVENT_UPDATE_CONFIG);
+	}
+
+	*mode_output = sensor_mode;
+	return EC_RES_SUCCESS;
+}
+
+static enum ec_status fp_command_mode(struct host_cmd_handler_args *args)
+{
+	const auto *p = static_cast<const ec_params_fp_mode *>(args->params);
+	auto *r = static_cast<ec_response_fp_mode *>(args->response);
+
+	enum ec_status ret = fp_set_sensor_mode(p->mode, &r->mode);
+
+	if (ret == EC_RES_SUCCESS)
+		args->response_size = sizeof(*r);
+
+	return ret;
+}
+DECLARE_HOST_COMMAND(EC_CMD_FP_MODE, fp_command_mode, EC_VER_MASK(0));
+
+static enum ec_status fp_command_context(struct host_cmd_handler_args *args)
+{
+	const auto *p =
+		static_cast<const ec_params_fp_context_v1 *>(args->params);
+	uint32_t mode_output;
+
+	switch (p->action) {
+	case FP_CONTEXT_ASYNC:
+		if (sensor_mode & FP_MODE_RESET_SENSOR)
+			return EC_RES_BUSY;
+
+		/**
+		 * Trigger a call to fp_reset_and_clear_context() by
+		 * requesting a reset. Since that function triggers a call to
+		 * fp_sensor_open(), this must be asynchronous because
+		 * fp_sensor_open() can take ~175 ms. See http://b/137288498.
+		 */
+		return fp_set_sensor_mode(FP_MODE_RESET_SENSOR, &mode_output);
+
+	case FP_CONTEXT_GET_RESULT:
+		if (sensor_mode & FP_MODE_RESET_SENSOR)
+			return EC_RES_BUSY;
+
+		memcpy(user_id, p->userid, sizeof(user_id));
+		return EC_RES_SUCCESS;
+	}
+
+	return EC_RES_INVALID_PARAM;
+}
+DECLARE_HOST_COMMAND(EC_CMD_FP_CONTEXT, fp_command_context, EC_VER_MASK(1));
+
+int fp_enable_positive_match_secret(uint16_t fgr,
+				    struct positive_match_secret_state *state)
+{
+	timestamp_t now;
+
+	if (state->readable) {
+		CPRINTS("Error: positive match secret already readable.");
+		fp_disable_positive_match_secret(state);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	now = get_time();
+	state->template_matched = fgr;
+	state->readable = true;
+	state->deadline.val = now.val + (5 * SECOND);
+	return EC_SUCCESS;
+}
+
+void fp_disable_positive_match_secret(struct positive_match_secret_state *state)
+{
+	state->template_matched = FP_NO_SUCH_TEMPLATE;
+	state->readable = false;
+	state->deadline.val = 0;
+}
+
+enum ec_status fp_read_match_secret(
+	int8_t fgr,
+	uint8_t positive_match_secret[FP_POSITIVE_MATCH_SECRET_BYTES])
+{
+	timestamp_t now = get_time();
+	struct positive_match_secret_state state_copy =
+		positive_match_secret_state;
+
+	fp_disable_positive_match_secret(&positive_match_secret_state);
+
+	if (fgr < 0 || fgr >= FP_MAX_FINGER_COUNT) {
+		CPRINTS("Invalid finger number %d", fgr);
+		return EC_RES_INVALID_PARAM;
+	}
+	if (timestamp_expired(state_copy.deadline, &now)) {
+		CPRINTS("Reading positive match secret disallowed: "
+			"deadline has passed.");
+		return EC_RES_TIMEOUT;
+	}
+	if (fgr != state_copy.template_matched || !state_copy.readable) {
+		CPRINTS("Positive match secret for finger %d is not meant to "
+			"be read now.",
+			fgr);
+		return EC_RES_ACCESS_DENIED;
+	}
+
+	if (derive_positive_match_secret(positive_match_secret,
+					 fp_positive_match_salt[fgr]) !=
+	    EC_SUCCESS) {
+		CPRINTS("Failed to derive positive match secret for finger %d",
+			fgr);
+		/* Keep the template and encryption salt. */
+		return EC_RES_ERROR;
+	}
+	CPRINTS("Derived positive match secret for finger %d", fgr);
+
+	return EC_RES_SUCCESS;
+}
+
+static enum ec_status
+fp_command_read_match_secret(struct host_cmd_handler_args *args)
+{
+	const auto *params =
+		static_cast<const ec_params_fp_read_match_secret *>(
+			args->params);
+	auto *response =
+		static_cast<ec_response_fp_read_match_secret *>(args->response);
+	int8_t fgr = params->fgr;
+
+	ec_status ret =
+		fp_read_match_secret(fgr, response->positive_match_secret);
+
+	if (ret != EC_RES_SUCCESS) {
+		return ret;
+	}
+
+	args->response_size = sizeof(*response);
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_FP_READ_MATCH_SECRET, fp_command_read_match_secret,
+		     EC_VER_MASK(0));
diff --git a/common/fpsensor/fpsensor_state_without_driver_info.cc b/common/fpsensor/fpsensor_state_without_driver_info.cc
new file mode 100644
index 0000000000..80bee55452
--- /dev/null
+++ b/common/fpsensor/fpsensor_state_without_driver_info.cc
@@ -0,0 +1,40 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "fpsensor_state_without_driver_info.h"
+
+/* TODO(b/286119221): Refactor fingerprint sensor state. */
+
+extern "C" {
+
+struct positive_match_secret_state
+	positive_match_secret_state = { .template_matched = FP_NO_SUCH_TEMPLATE,
+					.readable = false,
+					.deadline = {
+						.val = 0,
+					} };
+
+/* Index of the last enrolled but not retrieved template. */
+uint16_t template_newly_enrolled = FP_NO_SUCH_TEMPLATE;
+/* Number of used templates */
+uint16_t templ_valid;
+/* Bitmap of the templates with local modifications */
+uint32_t templ_dirty;
+/* Current user ID */
+uint32_t user_id[FP_CONTEXT_USERID_WORDS];
+/* Part of the IKM used to derive encryption keys received from the TPM. */
+uint8_t tpm_seed[FP_CONTEXT_TPM_BYTES];
+/* Status of the FP encryption engine & context. */
+uint32_t fp_encryption_status;
+
+atomic_t fp_events;
+
+uint32_t sensor_mode;
+
+int fp_tpm_seed_is_set(void)
+{
+	return fp_encryption_status & FP_ENC_STATUS_SEED_SET;
+}
+}
diff --git a/common/gesture.c b/common/gesture.c
index 86039e33bb..48e6af3571 100644
--- a/common/gesture.c
+++ b/common/gesture.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,8 +8,8 @@
 #include "accelgyro.h"
 #include "common.h"
 #include "console.h"
-#include "hooks.h"
 #include "gesture.h"
+#include "hooks.h"
 #include "lid_switch.h"
 #include "lightbar.h"
 #include "motion_sense.h"
@@ -19,9 +19,8 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_GESTURE, outstr)
-#define CPRINTS(format, args...) cprints(CC_GESTURE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_GESTURE, format, ## args)
-
+#define CPRINTS(format, args...) cprints(CC_GESTURE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_GESTURE, format, ##args)
 
 /*
  * Double tap detection parameters
@@ -34,16 +33,16 @@
  * which to check for relatively calm periods. In between the two impulses
  * there is a minimum and maximum interstice time allowed.
  */
-#define OUTER_WINDOW \
+#define OUTER_WINDOW                         \
 	(CONFIG_GESTURE_TAP_OUTER_WINDOW_T / \
 	 CONFIG_GESTURE_SAMPLING_INTERVAL_MS)
-#define INNER_WINDOW \
+#define INNER_WINDOW                         \
 	(CONFIG_GESTURE_TAP_INNER_WINDOW_T / \
 	 CONFIG_GESTURE_SAMPLING_INTERVAL_MS)
-#define MIN_INTERSTICE \
+#define MIN_INTERSTICE                         \
 	(CONFIG_GESTURE_TAP_MIN_INTERSTICE_T / \
 	 CONFIG_GESTURE_SAMPLING_INTERVAL_MS)
-#define MAX_INTERSTICE \
+#define MAX_INTERSTICE                         \
 	(CONFIG_GESTURE_TAP_MAX_INTERSTICE_T / \
 	 CONFIG_GESTURE_SAMPLING_INTERVAL_MS)
 #define MAX_WINDOW OUTER_WINDOW
@@ -67,10 +66,10 @@ enum tap_states {
 
 /* Tap sensor to use */
 static struct motion_sensor_t *sensor =
-&motion_sensors[CONFIG_GESTURE_SENSOR_DOUBLE_TAP];
+	&motion_sensors[CONFIG_GESTURE_TAP_SENSOR];
 
 /* Tap state information */
-static int history_z[MAX_WINDOW];  /* Changes in Z */
+static int history_z[MAX_WINDOW]; /* Changes in Z */
 static int history_xy[MAX_WINDOW]; /* Changes in X and Y */
 static int state, history_idx;
 static int history_initialized, history_init_index;
@@ -166,7 +165,7 @@ static int gesture_tap_for_battery(void)
 			(OUTER_WINDOW - INNER_WINDOW);
 	delta_z_inner = sum_z_inner * 1000 / INNER_WINDOW;
 	delta_xy_outer = (sum_xy_outer - sum_xy_inner) * 1000 /
-			(OUTER_WINDOW - INNER_WINDOW);
+			 (OUTER_WINDOW - INNER_WINDOW);
 	delta_xy_inner = sum_xy_inner * 1000 / INNER_WINDOW;
 
 	state_cnt++;
@@ -253,13 +252,11 @@ static int gesture_tap_for_battery(void)
 	}
 
 	/* On state transitions, print debug info */
-	if (tap_debug &&
-	    (state != state_p ||
-	     (state_cnt % 10000 == 9999))) {
+	if (tap_debug && (state != state_p || (state_cnt % 10000 == 9999))) {
 		/* make sure we don't divide by 0 */
 		if (delta_z_outer == 0 || delta_xy_inner == 0)
-			CPRINTS("tap st %d->%d, error div by 0",
-				state_p, state);
+			CPRINTS("tap st %d->%d, error div by 0", state_p,
+				state);
 		else
 			CPRINTS("tap st %d->%d, st_cnt %-3d "
 				"Z_in:Z_out %-3d, Z_in:XY_in %-3d "
@@ -267,10 +264,8 @@ static int gesture_tap_for_battery(void)
 				"dZ_out %-8.3d",
 				state_p, state, state_cnt,
 				delta_z_inner / delta_z_outer,
-				delta_z_inner / delta_xy_inner,
-				delta_z_inner,
-				delta_z_inner_max,
-				delta_z_outer);
+				delta_z_inner / delta_xy_inner, delta_z_inner,
+				delta_z_inner_max, delta_z_outer);
 	}
 
 	return ret;
@@ -281,8 +276,7 @@ static void gesture_chipset_resume(void)
 	/* disable tap detection */
 	tap_detection = 0;
 }
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, gesture_chipset_resume,
-	     GESTURE_HOOK_PRIO);
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, gesture_chipset_resume, GESTURE_HOOK_PRIO);
 
 static void gesture_chipset_suspend(void)
 {
@@ -295,8 +289,7 @@ static void gesture_chipset_suspend(void)
 	state = TAP_IDLE;
 	tap_detection = 1;
 }
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, gesture_chipset_suspend,
-	     GESTURE_HOOK_PRIO);
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, gesture_chipset_suspend, GESTURE_HOOK_PRIO);
 
 void gesture_calc(uint32_t *event)
 {
@@ -306,17 +299,17 @@ void gesture_calc(uint32_t *event)
 
 	if (gesture_tap_for_battery())
 		*event |= TASK_EVENT_MOTION_ACTIVITY_INTERRUPT(
-				MOTIONSENSE_ACTIVITY_DOUBLE_TAP);
+			MOTIONSENSE_ACTIVITY_DOUBLE_TAP);
 }
 
 /*****************************************************************************/
 /* Console commands */
-static int command_tap_info(int argc, char **argv)
+static int command_tap_info(int argc, const char **argv)
 {
 	int val;
 
-	ccprintf("tap:   %s\n", (tap_detection && !lid_is_open()) ?
-					"on" : "off");
+	ccprintf("tap:   %s\n",
+		 (tap_detection && !lid_is_open()) ? "on" : "off");
 
 	if (argc > 1) {
 		if (!parse_bool(argv[1], &val))
@@ -329,7 +322,5 @@ static int command_tap_info(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(tapinfo, command_tap_info,
-			"debug on/off",
+DECLARE_CONSOLE_COMMAND(tapinfo, command_tap_info, "debug on/off",
 			"Print tap information");
-
diff --git a/common/gettimeofday.c b/common/gettimeofday.c
new file mode 100644
index 0000000000..fce5c7e04e
--- /dev/null
+++ b/common/gettimeofday.c
@@ -0,0 +1,23 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "gettimeofday.h"
+#include "timer.h"
+
+#include <stddef.h>
+
+enum ec_error_list ec_gettimeofday(struct timeval *restrict tv,
+				   void *restrict tz)
+{
+	uint64_t now;
+
+	if (tv == NULL)
+		return EC_ERROR_INVAL;
+
+	now = get_time().val;
+	tv->tv_sec = now / SECOND;
+	tv->tv_usec = now % SECOND;
+	return EC_SUCCESS;
+}
diff --git a/common/gpio.c b/common/gpio.c
index f89be2700d..b69878eca3 100644
--- a/common/gpio.c
+++ b/common/gpio.c
@@ -1,10 +1,11 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* GPIO common functionality for Chrome EC */
 
+#include "builtin/assert.h"
 #include "common.h"
 #include "gpio.h"
 #include "ioexpander.h"
@@ -34,11 +35,11 @@ struct gpio_alt_func {
  * Construct the gpio_alt_funcs array.  This array is used by gpio_config_module
  * to enable and disable GPIO alternate functions on a module by module basis.
  */
-#define ALTERNATE(pinmask, function, module, flagz)                            \
-	{GPIO_##pinmask, .func = (function), .module_id = (module),            \
-	 .flags = (flagz)},
+#define ALTERNATE(pinmask, function, module, flagz)                  \
+	{ GPIO_##pinmask, .func = (function), .module_id = (module), \
+	  .flags = (flagz) },
 
-static const struct gpio_alt_func gpio_alt_funcs[] = {
+static __const_data const struct gpio_alt_func gpio_alt_funcs[] = {
 #include "gpio.wrap"
 };
 
@@ -74,9 +75,9 @@ static int gpio_config_pins(enum module_id id, uint32_t port, uint32_t pin_mask,
 				gpio_set_flags_by_mask(
 					af->port, (af->mask & pin_mask),
 					enable ? af->flags : GPIO_INPUT);
-			gpio_set_alternate_function(af->port,
-				    (af->mask & pin_mask),
-				    enable ? af->func : GPIO_ALT_FUNC_NONE);
+			gpio_set_alternate_function(
+				af->port, (af->mask & pin_mask),
+				enable ? af->func : GPIO_ALT_FUNC_NONE);
 			rv = EC_SUCCESS;
 			/* We're done here if we were just setting one port. */
 			if (port != GPIO_CONFIG_ALL_PORTS)
@@ -109,14 +110,15 @@ void gpio_set_flags(enum gpio_signal signal, int flags)
 	gpio_set_flags_by_mask(g->port, g->mask, flags);
 }
 
-#ifdef CONFIG_GPIO_GET_EXTENDED
 int gpio_get_flags(enum gpio_signal signal)
 {
 	const struct gpio_info *g = gpio_list + signal;
 
-	return gpio_get_flags_by_mask(g->port, g->mask);
+	if (IS_ENABLED(CONFIG_GPIO_GET_EXTENDED))
+		return gpio_get_flags_by_mask(g->port, g->mask);
+	else
+		return gpio_get_default_flags(signal);
 }
-#endif
 
 int gpio_get_default_flags(enum gpio_signal signal)
 {
@@ -127,8 +129,8 @@ void gpio_reset(enum gpio_signal signal)
 {
 	const struct gpio_info *g = gpio_list + signal;
 
-	gpio_set_flags_by_mask(g->port, g->mask, g->flags);
 	gpio_set_alternate_function(g->port, g->mask, GPIO_ALT_FUNC_NONE);
+	gpio_set_flags_by_mask(g->port, g->mask, g->flags);
 }
 
 const char *gpio_get_name(enum gpio_signal signal)
@@ -222,8 +224,8 @@ int gpio_or_ioex_get_level(int signal, int *value)
 
 int signal_is_gpio(int signal)
 {
-	return ((signal >= GPIO_SIGNAL_START)
-		&& (signal < GPIO_SIGNAL_START + GPIO_COUNT));
+	return ((signal >= GPIO_SIGNAL_START) &&
+		(signal < GPIO_SIGNAL_START + GPIO_COUNT));
 }
 
 __attribute__((weak)) void gpio_set_wakepin(enum gpio_signal signal,
diff --git a/common/gpio_commands.c b/common/gpio_commands.c
index 967d051f6c..4a7be22741 100644
--- a/common/gpio_commands.c
+++ b/common/gpio_commands.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -67,7 +67,7 @@ static enum ec_error_list set(const char *name, int value)
 	if (!gpio_is_implemented(signal))
 		return EC_ERROR_INVAL;
 
-	if (!(gpio_get_default_flags(signal) & GPIO_OUTPUT))
+	if (!(gpio_get_flags(signal) & GPIO_OUTPUT))
 		return EC_ERROR_INVAL;
 
 	gpio_set_level(signal, value);
@@ -78,45 +78,45 @@ static enum ec_error_list set(const char *name, int value)
 /* Console commands */
 
 struct gpio_flag_description {
-    const int bitfield;
-    const char* name;
+	const int bitfield;
+	const char *name;
 };
 
-const struct gpio_flag_description gpio_descriptions[] = {
-	{GPIO_INPUT, "I"},
-	{GPIO_OUTPUT, "O"},
-	{GPIO_LOW, "L"},
-	{GPIO_HIGH, "H"},
-	{GPIO_ANALOG, "A"},
-	{GPIO_OPEN_DRAIN, "ODR"},
-	{GPIO_PULL_UP, "PU"},
-	{GPIO_PULL_DOWN, "PD"},
-	{GPIO_ALTERNATE, "ALT"},
-	{GPIO_SEL_1P8V, "1P8"},
-	{GPIO_LOCKED, "LCK"}
+__maybe_unused static const struct gpio_flag_description gpio_descriptions[] = {
+	{ GPIO_INPUT, "I" },	    { GPIO_OUTPUT, "O" },
+	{ GPIO_LOW, "L" },	    { GPIO_HIGH, "H" },
+	{ GPIO_OPEN_DRAIN, "ODR" }, { GPIO_PULL_UP, "PU" },
+	{ GPIO_PULL_DOWN, "PD" },
+#ifdef GPIO_SEL_1P8V
+	{ GPIO_SEL_1P8V, "1P8" },
+#endif
+#ifndef CONFIG_ZEPHYR
+	{ GPIO_ANALOG, "A" },	    { GPIO_ALTERNATE, "ALT" },
+	{ GPIO_LOCKED, "LCK" }
+#endif
 };
 
 static void print_gpio_info(int gpio)
 {
-	int changed, v, flags, i;
+	int changed, v, i;
 
 	if (!gpio_is_implemented(gpio))
-		return;  /* Skip unsupported signals */
+		return; /* Skip unsupported signals */
 
 	v = gpio_get_level(gpio);
-#ifdef CONFIG_CMD_GPIO_EXTENDED
-	flags = gpio_get_flags(gpio);
-#else
-	flags = 0;
-#endif
 	changed = last_val_changed(gpio, v);
 
-	/* Split the printf call into multiple calls to reduce the stack usage. */
+	/* Split the printf call into multiple calls to reduce the stack usage.
+	 */
 	ccprintf("  %d%c ", v, (changed ? '*' : ' '));
 
-	for (i = 0; i < ARRAY_SIZE(gpio_descriptions); i++) {
-		if (flags & gpio_descriptions[i].bitfield)
-			ccprintf("%s ", gpio_descriptions[i].name);
+	if (IS_ENABLED(CONFIG_CMD_GPIO_EXTENDED)) {
+		int flags = gpio_get_flags(gpio);
+
+		for (i = 0; i < ARRAY_SIZE(gpio_descriptions); i++) {
+			if (flags & gpio_descriptions[i].bitfield)
+				ccprintf("%s ", gpio_descriptions[i].name);
+		}
 	}
 
 	ccprintf("%s\n", gpio_get_name(gpio));
@@ -125,7 +125,7 @@ static void print_gpio_info(int gpio)
 	cflush();
 }
 
-static int command_gpio_get(int argc, char **argv)
+static int command_gpio_get(int argc, const char **argv)
 {
 	int i;
 
@@ -142,24 +142,22 @@ static int command_gpio_get(int argc, char **argv)
 	/* Otherwise print them all */
 	for (i = 0; i < GPIO_COUNT; i++) {
 		if (!gpio_is_implemented(i))
-			continue;  /* Skip unsupported signals */
+			continue; /* Skip unsupported signals */
 
 		print_gpio_info(i);
 	}
 
 	return EC_SUCCESS;
 }
-DECLARE_SAFE_CONSOLE_COMMAND(gpioget, command_gpio_get,
-			     "[name]",
+DECLARE_SAFE_CONSOLE_COMMAND(gpioget, command_gpio_get, "[name]",
 			     "Read GPIO value(s)");
 
-static int command_gpio_set(int argc, char **argv)
+static int command_gpio_set(int argc, const char **argv)
 {
 #ifdef CONFIG_CMD_GPIO_EXTENDED
 	int gpio;
 	int flags = 0;
 	int af = -1;
-	char *e;
 
 	if (argc < 3)
 		return EC_ERROR_PARAM_COUNT;
@@ -174,16 +172,20 @@ static int command_gpio_set(int argc, char **argv)
 		flags = GPIO_OUT_HIGH;
 	else if (strcasecmp(argv[2], "0") == 0)
 		flags = GPIO_OUT_LOW;
+#ifndef CONFIG_ZEPHYR
 	else if (strcasecmp(argv[2], "A") == 0)
 		flags = GPIO_ANALOG;
 	else if (strcasecmp(argv[2], "ALT") == 0) {
+		char *e;
 		if (argc >= 4) {
 			af = strtoi(argv[3], &e, 0);
 			if (*e || af < 0 || af > 5)
 				return EC_ERROR_PARAM2;
 		}
 		flags = GPIO_ALTERNATE;
-	} else
+	}
+#endif
+	else
 		return EC_ERROR_PARAM2;
 
 	/* Update alt function if requested. */
@@ -216,9 +218,7 @@ DECLARE_CONSOLE_COMMAND_FLAGS(gpioset, command_gpio_set,
 #else
 			      "name <0 | 1>",
 #endif
-			      "Set a GPIO",
-			      CMD_FLAG_RESTRICTED
-);
+			      "Set a GPIO", CMD_FLAG_RESTRICTED);
 
 /*****************************************************************************/
 /* Host commands */
@@ -261,7 +261,7 @@ static enum ec_status gpio_command_get(struct host_cmd_handler_args *args)
 
 		i = p_v1->get_info.index;
 		len = strlen(gpio_get_name(i));
-		memcpy(r_v1->get_info.name, gpio_get_name(i), len+1);
+		memcpy(r_v1->get_info.name, gpio_get_name(i), len + 1);
 		r_v1->get_info.val = gpio_get_level(i);
 		r_v1->get_info.flags = gpio_get_default_flags(i);
 		args->response_size = sizeof(r_v1->get_info);
@@ -271,7 +271,6 @@ static enum ec_status gpio_command_get(struct host_cmd_handler_args *args)
 	}
 
 	return EC_RES_SUCCESS;
-
 }
 DECLARE_HOST_COMMAND(EC_CMD_GPIO_GET, gpio_command_get,
 		     EC_VER_MASK(0) | EC_VER_MASK(1));
diff --git a/common/gyro_cal.c b/common/gyro_cal.c
index 572e401b18..e2cb8d55db 100644
--- a/common/gyro_cal.c
+++ b/common/gyro_cal.c
@@ -1,10 +1,11 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "gyro_cal.h"
 #include "string.h"
+
 #include <stdbool.h>
 
 /*
diff --git a/common/gyro_still_det.c b/common/gyro_still_det.c
index 4574e22e5f..303b73b15f 100644
--- a/common/gyro_still_det.c
+++ b/common/gyro_still_det.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/common/hooks.c b/common/hooks.c
index 4c2a4e48c6..88a6b93b93 100644
--- a/common/hooks.c
+++ b/common/hooks.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,7 +14,7 @@
 
 #ifdef CONFIG_HOOK_DEBUG
 #define CPUTS(outstr) cputs(CC_HOOK, outstr)
-#define CPRINTS(format, args...) cprints(CC_HOOK, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_HOOK, format, ##args)
 #else
 #define CPUTS(outstr)
 #define CPRINTS(format, args...)
@@ -32,40 +32,44 @@ struct hook_ptrs {
  * order as enum hook_type.
  */
 static const struct hook_ptrs hook_list[] = {
-	{__hooks_init, __hooks_init_end},
-	{__hooks_pre_freq_change, __hooks_pre_freq_change_end},
-	{__hooks_freq_change, __hooks_freq_change_end},
-	{__hooks_sysjump, __hooks_sysjump_end},
-	{__hooks_chipset_pre_init, __hooks_chipset_pre_init_end},
-	{__hooks_chipset_startup, __hooks_chipset_startup_end},
-	{__hooks_chipset_resume, __hooks_chipset_resume_end},
-	{__hooks_chipset_suspend, __hooks_chipset_suspend_end},
+	{ __hooks_init, __hooks_init_end },
+	{ __hooks_pre_freq_change, __hooks_pre_freq_change_end },
+	{ __hooks_freq_change, __hooks_freq_change_end },
+	{ __hooks_sysjump, __hooks_sysjump_end },
+	{ __hooks_chipset_pre_init, __hooks_chipset_pre_init_end },
+	{ __hooks_chipset_startup, __hooks_chipset_startup_end },
+	{ __hooks_chipset_resume, __hooks_chipset_resume_end },
+	{ __hooks_chipset_suspend, __hooks_chipset_suspend_end },
 #ifdef CONFIG_CHIPSET_RESUME_INIT_HOOK
-	{__hooks_chipset_resume_init, __hooks_chipset_resume_init_end},
-	{__hooks_chipset_suspend_complete,
-	 __hooks_chipset_suspend_complete_end},
+	{ __hooks_chipset_resume_init, __hooks_chipset_resume_init_end },
+	{ __hooks_chipset_suspend_complete,
+	  __hooks_chipset_suspend_complete_end },
 #endif
-	{__hooks_chipset_shutdown, __hooks_chipset_shutdown_end},
-	{__hooks_chipset_shutdown_complete,
-	 __hooks_chipset_shutdown_complete_end},
-	{__hooks_chipset_reset, __hooks_chipset_reset_end},
-	{__hooks_ac_change, __hooks_ac_change_end},
-	{__hooks_lid_change, __hooks_lid_change_end},
-	{__hooks_tablet_mode_change, __hooks_tablet_mode_change_end},
-	{__hooks_base_attached_change, __hooks_base_attached_change_end},
-	{__hooks_pwrbtn_change, __hooks_pwrbtn_change_end},
-	{__hooks_battery_soc_change, __hooks_battery_soc_change_end},
+	{ __hooks_chipset_shutdown, __hooks_chipset_shutdown_end },
+	{ __hooks_chipset_shutdown_complete,
+	  __hooks_chipset_shutdown_complete_end },
+	{ __hooks_chipset_hard_off, __hooks_chipset_hard_off_end },
+	{ __hooks_chipset_reset, __hooks_chipset_reset_end },
+	{ __hooks_ac_change, __hooks_ac_change_end },
+	{ __hooks_lid_change, __hooks_lid_change_end },
+	{ __hooks_tablet_mode_change, __hooks_tablet_mode_change_end },
+#ifdef CONFIG_BODY_DETECTION
+	{ __hooks_body_detect_change, __hooks_body_detect_change_end },
+#endif
+	{ __hooks_base_attached_change, __hooks_base_attached_change_end },
+	{ __hooks_pwrbtn_change, __hooks_pwrbtn_change_end },
+	{ __hooks_battery_soc_change, __hooks_battery_soc_change_end },
 #ifdef CONFIG_USB_SUSPEND
-	{__hooks_usb_change, __hooks_usb_change_end},
+	{ __hooks_usb_change, __hooks_usb_change_end },
 #endif
-	{__hooks_tick, __hooks_tick_end},
-	{__hooks_second, __hooks_second_end},
-	{__hooks_usb_pd_disconnect, __hooks_usb_pd_disconnect_end},
-	{__hooks_usb_pd_connect, __hooks_usb_pd_connect_end},
+	{ __hooks_tick, __hooks_tick_end },
+	{ __hooks_second, __hooks_second_end },
+	{ __hooks_usb_pd_disconnect, __hooks_usb_pd_disconnect_end },
+	{ __hooks_usb_pd_connect, __hooks_usb_pd_connect_end },
+	{ __hooks_power_supply_change, __hooks_power_supply_change_end },
 };
 
 /* Times for deferrable functions */
-static int defer_new_call;
 static int hook_task_started;
 
 #ifdef CONFIG_HOOK_DEBUG
@@ -149,7 +153,7 @@ int hook_call_deferred(const struct deferred_data *data, int us)
 	int i = data - __deferred_funcs;
 
 	if (data < __deferred_funcs || data >= __deferred_funcs_end)
-		return EC_ERROR_INVAL;  /* Routine not registered */
+		return EC_ERROR_INVAL; /* Routine not registered */
 
 	if (us == -1) {
 		/* Cancel */
@@ -157,12 +161,6 @@ int hook_call_deferred(const struct deferred_data *data, int us)
 	} else {
 		/* Set alarm */
 		__deferred_until[i] = get_time().val + us;
-		/*
-		 * Flag that hook_call_deferred() has been called.  If the hook
-		 * task is already active, this will allow it to go through the
-		 * loop one more time before sleeping.
-		 */
-		defer_new_call = 1;
 
 		/* Wake task so it can re-sleep for the proper time */
 		if (hook_task_started)
@@ -191,20 +189,24 @@ void hook_task(void *u)
 		int next = 0;
 		int i;
 
+		interrupt_disable();
 		/* Handle deferred routines */
 		for (i = 0; i < DEFERRED_FUNCS_COUNT; i++) {
 			if (__deferred_until[i] && __deferred_until[i] < t) {
-				CPRINTS("hook call deferred 0x%pP",
-					__deferred_funcs[i].routine);
 				/*
 				 * Call deferred function.  Clear timer first,
 				 * so it can request itself be called later.
 				 */
 				__deferred_until[i] = 0;
+				interrupt_enable();
+				CPRINTS("hook call deferred 0x%p",
+					__deferred_funcs[i].routine);
 				__deferred_funcs[i].routine();
+				interrupt_disable();
 			}
 		}
 
+		interrupt_enable();
 		if (t - last_tick >= HOOK_TICK_INTERVAL) {
 #ifdef CONFIG_HOOK_DEBUG
 			record_hook_delay(t, last_tick, HOOK_TICK_INTERVAL,
@@ -230,9 +232,7 @@ void hook_task(void *u)
 		if (last_tick + HOOK_TICK_INTERVAL > t)
 			next = last_tick + HOOK_TICK_INTERVAL - t;
 
-		/* Wake earlier if needed by a deferred routine */
-		defer_new_call = 0;
-
+		interrupt_disable();
 		for (i = 0; i < DEFERRED_FUNCS_COUNT && next > 0; i++) {
 			if (!__deferred_until[i])
 				continue;
@@ -243,12 +243,13 @@ void hook_task(void *u)
 				next = __deferred_until[i] - t;
 		}
 
+		interrupt_enable();
+
 		/*
-		 * If nothing is immediately pending, and hook_call_deferred()
-		 * hasn't been called since we started calculating next, sleep
-		 * until the next event.
+		 * If nothing is immediately pending, sleep until the next
+		 * event.
 		 */
-		if (next > 0 && !defer_new_call)
+		if (next > 0)
 			task_wait_event(next);
 	}
 }
@@ -267,7 +268,7 @@ static void print_hook_delay(uint32_t interval, uint32_t delay, uint32_t avg)
 	ccprintf("  Average:     %7d us (%d%%)\n\n", avg, percent_avg);
 }
 
-static int command_stats(int argc, char **argv)
+static int command_stats(int argc, const char **argv)
 {
 	int i;
 
@@ -286,7 +287,5 @@ static int command_stats(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(hookstats, command_stats,
-			NULL,
-			"Print stats of hooks");
+DECLARE_CONSOLE_COMMAND(hookstats, command_stats, NULL, "Print stats of hooks");
 #endif
diff --git a/common/host_command.c b/common/host_command.c
index c7fd1baa15..37715b793f 100644
--- a/common/host_command.c
+++ b/common/host_command.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,22 +6,26 @@
 /* Host command module for Chrome EC */
 
 #include "ap_hang_detect.h"
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
 #include "ec_commands.h"
 #include "host_command.h"
 #include "link_defs.h"
 #include "lpc.h"
+#include "power.h"
+#include "printf.h"
 #include "shared_mem.h"
 #include "system.h"
+#include "system_safe_mode.h"
 #include "task.h"
 #include "timer.h"
 #include "util.h"
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_HOSTCMD, outstr)
-#define CPRINTF(format, args...) cprintf(CC_HOSTCMD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_HOSTCMD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_HOSTCMD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_HOSTCMD, format, ##args)
 
 #define TASK_EVENT_CMD_PENDING TASK_EVENT_CUSTOM_BIT(0)
 
@@ -42,18 +46,19 @@ static uint8_t host_memmap[EC_MEMMAP_SIZE] __aligned(4);
 #endif
 
 static enum {
-	HCDEBUG_OFF,     /* No host command debug output */
-	HCDEBUG_NORMAL,  /* Normal output mode; skips repeated commands */
-	HCDEBUG_EVERY,   /* Print every command */
-	HCDEBUG_PARAMS,  /* ... and print params for request/response */
+	HCDEBUG_OFF, /* No host command debug output */
+	HCDEBUG_NORMAL, /* Normal output mode; skips repeated commands */
+	HCDEBUG_EVERY, /* Print every command */
+	HCDEBUG_PARAMS, /* ... and print params for request/response */
 
 	/* Number of host command debug modes */
 	HCDEBUG_MODES
 } hcdebug = CONFIG_HOSTCMD_DEBUG_MODE;
 
 #ifdef CONFIG_CMD_HCDEBUG
-static const char * const hcdebug_mode_names[HCDEBUG_MODES] = {
-	"off", "normal", "every", "params"};
+static const char *const hcdebug_mode_names[HCDEBUG_MODES] = { "off", "normal",
+							       "every",
+							       "params" };
 #endif
 
 #ifdef CONFIG_HOST_COMMAND_STATUS
@@ -179,7 +184,7 @@ void host_command_received(struct host_cmd_handler_args *args)
 		pending_args = args;
 
 		/* Wake up the task to handle the command */
-		task_set_event(TASK_ID_HOSTCMD, TASK_EVENT_CMD_PENDING, 0);
+		task_set_event(TASK_ID_HOSTCMD, TASK_EVENT_CMD_PENDING);
 		return;
 	}
 
@@ -343,8 +348,8 @@ void host_packet_receive(struct host_packet *pkt)
 	args0.version = r->command_version;
 	args0.params_size = r->data_len;
 	args0.response = (struct ec_host_response *)(pkt->response) + 1;
-	args0.response_max = pkt->response_max -
-		sizeof(struct ec_host_response);
+	args0.response_max =
+		pkt->response_max - sizeof(struct ec_host_response);
 	args0.response_size = 0;
 	args0.result = EC_RES_SUCCESS;
 
@@ -370,38 +375,44 @@ void host_packet_receive(struct host_packet *pkt)
  */
 static const struct host_command *find_host_command(int command)
 {
-#ifdef CONFIG_HOSTCMD_SECTION_SORTED
-	const struct host_command *l, *r, *m;
-	uint32_t num;
-
-/* Use binary search to locate host command handler */
-	l = __hcmds;
-	r = __hcmds_end - 1;
-
-	while (1) {
-		if (l > r)
+	if (IS_ENABLED(CONFIG_SYSTEM_SAFE_MODE) && system_is_in_safe_mode()) {
+		if (!command_is_allowed_in_safe_mode(command))
 			return NULL;
-
-		num = r - l;
-		m = l + (num / 2);
-
-		if (m->command < command)
-			l = m + 1;
-		else if (m->command > command)
-			r = m - 1;
-		else
-			return m;
 	}
-#else
-	const struct host_command *cmd;
+	if (IS_ENABLED(CONFIG_ZEPHYR)) {
+		return zephyr_find_host_command(command);
+	} else if (IS_ENABLED(CONFIG_HOSTCMD_SECTION_SORTED)) {
+		const struct host_command *l, *r, *m;
+		uint32_t num;
+
+		/* Use binary search to locate host command handler */
+		l = __hcmds;
+		r = __hcmds_end - 1;
+
+		while (1) {
+			if (l > r)
+				return NULL;
+
+			num = r - l;
+			m = l + (num / 2);
+
+			if (m->command < command)
+				l = m + 1;
+			else if (m->command > command)
+				r = m - 1;
+			else
+				return m;
+		}
+	} else {
+		const struct host_command *cmd;
 
-	for (cmd = __hcmds; cmd < __hcmds_end; cmd++) {
-		if (command == cmd->command)
-			return cmd;
-	}
+		for (cmd = __hcmds; cmd < __hcmds_end; cmd++) {
+			if (command == cmd->command)
+				return cmd;
+		}
 
-	return NULL;
-#endif
+		return NULL;
+	}
 }
 
 static void host_command_init(void)
@@ -438,7 +449,7 @@ void host_command_task(void *u)
 		/* Process it */
 		if ((evt & TASK_EVENT_CMD_PENDING) && pending_args) {
 			pending_args->result =
-					host_command_process(pending_args);
+				host_command_process(pending_args);
 			host_send_response(pending_args);
 		}
 
@@ -471,8 +482,7 @@ host_command_proto_version(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_PROTO_VERSION,
-		     host_command_proto_version,
+DECLARE_HOST_COMMAND(EC_CMD_PROTO_VERSION, host_command_proto_version,
 		     EC_VER_MASK(0));
 
 static enum ec_status host_command_hello(struct host_cmd_handler_args *args)
@@ -486,32 +496,7 @@ static enum ec_status host_command_hello(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_HELLO,
-		     host_command_hello,
-		     EC_VER_MASK(0));
-
-static enum ec_status host_command_read_test(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_read_test *p = args->params;
-	struct ec_response_read_test *r = args->response;
-
-	int offset = p->offset;
-	int size = p->size / sizeof(uint32_t);
-	int i;
-
-	if (size > ARRAY_SIZE(r->data) || p->size > args->response_size)
-		return EC_RES_ERROR;
-
-	for (i = 0; i < size; i++)
-		r->data[i] = offset + i;
-
-	args->response_size = size * sizeof(uint32_t);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_READ_TEST,
-		     host_command_read_test,
-		     EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_HELLO, host_command_hello, EC_VER_MASK(0));
 
 #ifndef CONFIG_HOSTCMD_X86
 /*
@@ -541,8 +526,7 @@ host_command_read_memmap(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_READ_MEMMAP,
-		     host_command_read_memmap,
+DECLARE_HOST_COMMAND(EC_CMD_READ_MEMMAP, host_command_read_memmap,
 		     EC_VER_MASK(0));
 #endif
 
@@ -553,9 +537,9 @@ host_command_get_cmd_versions(struct host_cmd_handler_args *args)
 	const struct ec_params_get_cmd_versions_v1 *p_v1 = args->params;
 	struct ec_response_get_cmd_versions *r = args->response;
 
-	const struct host_command *cmd =
-		(args->version == 1) ? find_host_command(p_v1->cmd) :
-				       find_host_command(p->cmd);
+	const struct host_command *cmd = (args->version == 1) ?
+						 find_host_command(p_v1->cmd) :
+						 find_host_command(p->cmd);
 
 	if (!cmd)
 		return EC_RES_INVALID_PARAM;
@@ -566,8 +550,7 @@ host_command_get_cmd_versions(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_GET_CMD_VERSIONS,
-		     host_command_get_cmd_versions,
+DECLARE_HOST_COMMAND(EC_CMD_GET_CMD_VERSIONS, host_command_get_cmd_versions,
 		     EC_VER_MASK(0) | EC_VER_MASK(1));
 
 static int host_command_is_suppressed(uint16_t cmd)
@@ -592,11 +575,13 @@ static void dump_host_command_suppressed(int force)
 {
 #ifdef CONFIG_SUPPRESSED_HOST_COMMANDS
 	int i;
+	char ts_str[PRINTF_TIMESTAMP_BUF_SIZE];
 
 	if (!force && !timestamp_expired(suppressed_cmd_deadline, NULL))
 		return;
 
-	CPRINTF("[%pT HC Suppressed:", PRINTF_TIMESTAMP_NOW);
+	snprintf_timestamp_now(ts_str, sizeof(ts_str));
+	CPRINTF("[%s HC Suppressed:", ts_str);
 	for (i = 0; i < ARRAY_SIZE(hc_suppressed_cmd); i++) {
 		CPRINTF(" 0x%x=%d", hc_suppressed_cmd[i], hc_suppressed_cnt[i]);
 		hc_suppressed_cnt[i] = 0;
@@ -612,10 +597,9 @@ static void dump_host_command_suppressed_(void)
 {
 	dump_host_command_suppressed(1);
 }
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN,
-	     dump_host_command_suppressed_, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_SYSJUMP,
-	     dump_host_command_suppressed_, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, dump_host_command_suppressed_,
+	     HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_SYSJUMP, dump_host_command_suppressed_, HOOK_PRIO_DEFAULT);
 #else
 }
 #endif /* CONFIG_SUPPRESSED_HOST_COMMANDS */
@@ -657,12 +641,15 @@ static void host_command_debug_request(struct host_cmd_handler_args *args)
 		hc_prev_cmd = args->command;
 	}
 
-	if (hcdebug >= HCDEBUG_PARAMS && args->params_size)
-		CPRINTS("HC 0x%02x.%d:%ph", args->command,
-			args->version,
-			HEX_BUF(args->params, args->params_size));
-	else
-		CPRINTS("HC 0x%02x", args->command);
+	if (hcdebug >= HCDEBUG_PARAMS && args->params_size) {
+		char str_buf[hex_str_buf_size(args->params_size)];
+
+		snprintf_hex_buffer(str_buf, sizeof(str_buf),
+				    HEX_BUF(args->params, args->params_size));
+		CPRINTS("HC 0x%04x.%d:%s", args->command, args->version,
+			str_buf);
+	} else
+		CPRINTS("HC 0x%04x", args->command);
 }
 
 uint16_t host_command_process(struct host_cmd_handler_args *args)
@@ -691,9 +678,9 @@ uint16_t host_command_process(struct host_cmd_handler_args *args)
 	if (args->command >= EC_CMD_PASSTHRU_OFFSET(1) &&
 	    args->command <= EC_CMD_PASSTHRU_MAX(1)) {
 		rv = pd_host_command(args->command - EC_CMD_PASSTHRU_OFFSET(1),
-				     args->version,
-				     args->params, args->params_size,
-				     args->response, args->response_max);
+				     args->version, args->params,
+				     args->params_size, args->response,
+				     args->response_max);
 		if (rv >= 0) {
 			/* Success; store actual response size */
 			args->response_size = rv;
@@ -715,11 +702,16 @@ uint16_t host_command_process(struct host_cmd_handler_args *args)
 	}
 
 	if (rv != EC_RES_SUCCESS)
-		CPRINTS("HC 0x%02x err %d", args->command, rv);
+		CPRINTS("HC 0x%04x err %d", args->command, rv);
+
+	if (hcdebug >= HCDEBUG_PARAMS && args->response_size) {
+		char str_buf[hex_str_buf_size(args->response_size)];
 
-	if (hcdebug >= HCDEBUG_PARAMS && args->response_size)
-		CPRINTS("HC resp:%ph",
-			HEX_BUF(args->response, args->response_size));
+		snprintf_hex_buffer(str_buf, sizeof(str_buf),
+				    HEX_BUF(args->response,
+					    args->response_size));
+		CPRINTS("HC resp:%s", str_buf);
+	}
 
 	return rv;
 }
@@ -737,8 +729,7 @@ host_command_get_comms_status(struct host_cmd_handler_args *args)
 	return EC_RES_SUCCESS;
 }
 
-DECLARE_HOST_COMMAND(EC_CMD_GET_COMMS_STATUS,
-		     host_command_get_comms_status,
+DECLARE_HOST_COMMAND(EC_CMD_GET_COMMS_STATUS, host_command_get_comms_status,
 		     EC_VER_MASK(0));
 
 /* Resend the last saved response */
@@ -754,8 +745,7 @@ host_command_resend_response(struct host_cmd_handler_args *args)
 	return EC_RES_SUCCESS;
 }
 
-DECLARE_HOST_COMMAND(EC_CMD_RESEND_RESPONSE,
-		     host_command_resend_response,
+DECLARE_HOST_COMMAND(EC_CMD_RESEND_RESPONSE, host_command_resend_response,
 		     EC_VER_MASK(0));
 #endif /* CONFIG_HOST_COMMAND_STATUS */
 
@@ -773,8 +763,7 @@ host_command_test_protocol(struct host_cmd_handler_args *args)
 
 	return p->ec_result;
 }
-DECLARE_HOST_COMMAND(EC_CMD_TEST_PROTOCOL,
-		     host_command_test_protocol,
+DECLARE_HOST_COMMAND(EC_CMD_TEST_PROTOCOL, host_command_test_protocol,
 		     EC_VER_MASK(0));
 
 /* Returns supported features. */
@@ -789,16 +778,14 @@ host_command_get_features(struct host_cmd_handler_args *args)
 	r->flags[1] = get_feature_flags1();
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_GET_FEATURES,
-		     host_command_get_features,
+DECLARE_HOST_COMMAND(EC_CMD_GET_FEATURES, host_command_get_features,
 		     EC_VER_MASK(0));
 
-
 /*****************************************************************************/
 /* Console commands */
 
 #ifdef CONFIG_CMD_HOSTCMD
-static int parse_byte(char *b, uint8_t *out)
+static int parse_byte(const char *b, uint8_t *out)
 {
 	int i;
 	*out = 0;
@@ -817,7 +804,7 @@ static int parse_byte(char *b, uint8_t *out)
 	return EC_SUCCESS;
 }
 
-static int parse_params(char *s, uint8_t *params)
+static int parse_params(const char *s, uint8_t *params)
 {
 	int len = 0;
 
@@ -831,7 +818,7 @@ static int parse_params(char *s, uint8_t *params)
 	return len;
 }
 
-static int command_host_command(int argc, char **argv)
+static int command_host_command(int argc, const char **argv)
 {
 	struct host_cmd_handler_args args;
 	char *cmd_params;
@@ -886,23 +873,27 @@ static int command_host_command(int argc, char **argv)
 
 	if (res != EC_RES_SUCCESS)
 		ccprintf("Command returned %d\n", res);
-	else if (args.response_size)
-		ccprintf("Response: %ph\n",
-			 HEX_BUF(cmd_params, args.response_size));
-	else
+	else if (args.response_size) {
+		char str_buf[hex_str_buf_size(args.response_size)];
+
+		snprintf_hex_buffer(str_buf, sizeof(str_buf),
+				    HEX_BUF(cmd_params, args.response_size));
+		ccprintf("Response: %s\n", str_buf);
+	} else
 		ccprintf("Command succeeded; no response.\n");
 
 	shared_mem_release(cmd_params);
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(hostcmd, command_host_command,
-			"cmd ver param",
+DECLARE_CONSOLE_COMMAND(hostcmd, command_host_command, "cmd ver param",
 			"Fake host command");
 #endif /* CONFIG_CMD_HOSTCMD */
 
 #ifdef CONFIG_CMD_HCDEBUG
-static int command_hcdebug(int argc, char **argv)
+static int command_hcdebug(int argc, const char **argv)
 {
+	if (argc >= 3)
+		return EC_ERROR_PARAM_COUNT;
 	if (argc > 1) {
 		int i;
 
@@ -926,3 +917,24 @@ DECLARE_CONSOLE_COMMAND(hcdebug, command_hcdebug,
 			"hcdebug [off | normal | every | params]",
 			"Set host command debug output mode");
 #endif /* CONFIG_CMD_HCDEBUG */
+
+#if defined(CONFIG_AP_PWRSEQ_S0IX_COUNTER) || \
+	defined(CONFIG_POWERSEQ_S0IX_COUNTER)
+static enum ec_status
+host_command_get_s0ix_cnt(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_s0ix_cnt *p = args->params;
+	struct ec_response_s0ix_cnt *r = args->response;
+
+	if (p->flags & EC_S0IX_COUNTER_RESET) {
+		atomic_clear(&s0ix_counter);
+	}
+
+	r->s0ix_counter = atomic_get(&s0ix_counter);
+
+	args->response_size = sizeof(*r);
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_GET_S0IX_COUNTER, host_command_get_s0ix_cnt,
+		     EC_VER_MASK(0));
+#endif
diff --git a/common/host_command_controller.c b/common/host_command_controller.c
new file mode 100644
index 0000000000..83d4ce0c86
--- /dev/null
+++ b/common/host_command_controller.c
@@ -0,0 +1,222 @@
+/* Copyright 2014 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Host command controller module for Chrome EC */
+
+#include "common.h"
+#include "console.h"
+#include "host_command.h"
+#include "i2c.h"
+#include "task.h"
+#include "timer.h"
+#include "usb_pd.h"
+#include "util.h"
+
+/* Console output macros */
+#define CPUTS(outstr) cputs(CC_HOSTCMD, outstr)
+#define CPRINTS(format, args...) cprints(CC_HOSTCMD, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_HOSTCMD, format, ##args)
+
+/* Number of attempts for each PD host command */
+#define PD_HOST_COMMAND_ATTEMPTS 3
+
+static struct mutex pd_mutex;
+
+/**
+ * Non-task-safe internal version of pd_host_command().
+ *
+ * Do not call this version directly!  Use pd_host_command().
+ */
+static int pd_host_command_internal(int command, int version,
+				    const void *outdata, int outsize,
+				    void *indata, int insize)
+{
+	int ret, i;
+	int resp_len;
+	struct ec_host_request rq;
+	struct ec_host_response rs;
+	static uint8_t req_buf[EC_LPC_HOST_PACKET_SIZE];
+	static uint8_t resp_buf[EC_LPC_HOST_PACKET_SIZE];
+	uint8_t sum = 0;
+	const uint8_t *c;
+	uint8_t *d;
+
+	/* Fail if output size is too big */
+	if (outsize + sizeof(rq) > EC_LPC_HOST_PACKET_SIZE)
+		return -EC_RES_REQUEST_TRUNCATED;
+
+	/* Fill in request packet */
+	rq.struct_version = EC_HOST_REQUEST_VERSION;
+	rq.checksum = 0;
+	rq.command = command;
+	rq.command_version = version;
+	rq.reserved = 0;
+	rq.data_len = outsize;
+
+	/* Copy data and start checksum */
+	for (i = 0, c = (const uint8_t *)outdata; i < outsize; i++, c++) {
+		req_buf[sizeof(rq) + 1 + i] = *c;
+		sum += *c;
+	}
+
+	/* Finish checksum */
+	for (i = 0, c = (const uint8_t *)&rq; i < sizeof(rq); i++, c++)
+		sum += *c;
+
+	/* Write checksum field so the entire packet sums to 0 */
+	rq.checksum = (uint8_t)(-sum);
+
+	/* Copy header */
+	for (i = 0, c = (const uint8_t *)&rq; i < sizeof(rq); i++, c++)
+		req_buf[1 + i] = *c;
+
+	/* Set command to use protocol v3 */
+	req_buf[0] = EC_COMMAND_PROTOCOL_3;
+
+	/*
+	 * Transmit all data and receive 2 bytes for return value and response
+	 * length.
+	 */
+	i2c_lock(I2C_PORT_PD_MCU, 1);
+	i2c_set_timeout(I2C_PORT_PD_MCU, PD_HOST_COMMAND_TIMEOUT_US);
+	ret = i2c_xfer_unlocked(I2C_PORT_PD_MCU, CONFIG_USB_PD_I2C_ADDR_FLAGS,
+				&req_buf[0], outsize + sizeof(rq) + 1,
+				&resp_buf[0], 2, I2C_XFER_START);
+	i2c_set_timeout(I2C_PORT_PD_MCU, 0);
+	if (ret) {
+		i2c_lock(I2C_PORT_PD_MCU, 0);
+		CPRINTS("i2c transaction 1 failed: %d", ret);
+		return -EC_RES_BUS_ERROR;
+	}
+
+	resp_len = resp_buf[1];
+
+	if (resp_len > (insize + sizeof(rs))) {
+		/* Do a read to generate stop condition */
+		i2c_xfer_unlocked(I2C_PORT_PD_MCU, CONFIG_USB_PD_I2C_ADDR_FLAGS,
+				  0, 0, &resp_buf[2], 1, I2C_XFER_STOP);
+		i2c_lock(I2C_PORT_PD_MCU, 0);
+		CPRINTS("response size is too large %d > %d", resp_len,
+			insize + sizeof(rs));
+		return -EC_RES_RESPONSE_TOO_BIG;
+	}
+
+	/* Receive remaining data */
+	ret = i2c_xfer_unlocked(I2C_PORT_PD_MCU, CONFIG_USB_PD_I2C_ADDR_FLAGS,
+				0, 0, &resp_buf[2], resp_len, I2C_XFER_STOP);
+	i2c_lock(I2C_PORT_PD_MCU, 0);
+	if (ret) {
+		CPRINTS("i2c transaction 2 failed: %d", ret);
+		return -EC_RES_BUS_ERROR;
+	}
+
+	/* Check for host command error code */
+	ret = resp_buf[0];
+	if (ret) {
+		CPRINTS("command 0x%04x returned error %d", command, ret);
+		return -ret;
+	}
+
+	/* Read back response header and start checksum */
+	sum = 0;
+	for (i = 0, d = (uint8_t *)&rs; i < sizeof(rs); i++, d++) {
+		*d = resp_buf[i + 2];
+		sum += *d;
+	}
+
+	if (rs.struct_version != EC_HOST_RESPONSE_VERSION) {
+		CPRINTS("PD response version mismatch");
+		return -EC_RES_INVALID_RESPONSE;
+	}
+
+	if (rs.reserved) {
+		CPRINTS("PD response reserved != 0");
+		return -EC_RES_INVALID_RESPONSE;
+	}
+
+	if (rs.data_len > insize) {
+		CPRINTS("PD returned too much data");
+		return -EC_RES_RESPONSE_TOO_BIG;
+	}
+
+	/* Read back data and update checksum */
+	resp_len -= sizeof(rs);
+	for (i = 0, d = (uint8_t *)indata; i < resp_len; i++, d++) {
+		*d = resp_buf[sizeof(rs) + i + 2];
+		sum += *d;
+	}
+
+	if ((uint8_t)sum) {
+		CPRINTS("command 0x%04x bad checksum returned: %d", command,
+			sum);
+		return -EC_RES_INVALID_CHECKSUM;
+	}
+
+	/* Return output buffer size */
+	return resp_len;
+}
+
+int pd_host_command(int command, int version, const void *outdata, int outsize,
+		    void *indata, int insize)
+{
+	int rv;
+	int tries = 0;
+
+	/* Try multiple times to send host command. */
+	for (tries = 0; tries < PD_HOST_COMMAND_ATTEMPTS; tries++) {
+		/* Acquire mutex */
+		mutex_lock(&pd_mutex);
+		/* Call internal version of host command */
+		rv = pd_host_command_internal(command, version, outdata,
+					      outsize, indata, insize);
+		/* Release mutex */
+		mutex_unlock(&pd_mutex);
+
+		/* If host command error due to i2c bus error, try again. */
+		if (rv != -EC_RES_BUS_ERROR)
+			break;
+		task_wait_event(50 * MSEC);
+	}
+
+	return rv;
+}
+
+static int command_pd_mcu(int argc, const char **argv)
+{
+	char *e;
+	static char outbuf[128];
+	static char inbuf[128];
+	int command, version;
+	int i, ret, tmp;
+
+	if (argc < 3)
+		return EC_ERROR_PARAM_COUNT;
+
+	command = strtoi(argv[1], &e, 0);
+	if (*e)
+		return EC_ERROR_PARAM1;
+
+	version = strtoi(argv[2], &e, 0);
+	if (*e)
+		return EC_ERROR_PARAM2;
+
+	for (i = 3; i < argc; i++) {
+		tmp = strtoi(argv[i], &e, 0);
+		if (*e)
+			return EC_ERROR_PARAM3;
+		outbuf[i - 3] = tmp;
+	}
+
+	ret = pd_host_command(command, version, &outbuf, argc - 3, &inbuf,
+			      sizeof(inbuf));
+
+	ccprintf("Host command 0x%02x, returned %d\n", command, ret);
+	for (i = 0; i < ret; i++)
+		ccprintf("0x%02x\n", inbuf[i]);
+
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(pdcmd, command_pd_mcu, "cmd ver [params]",
+			"Send PD host command");
diff --git a/common/host_command_master.c b/common/host_command_master.c
deleted file mode 100644
index d51c8cdc15..0000000000
--- a/common/host_command_master.c
+++ /dev/null
@@ -1,230 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Host command master module for Chrome EC */
-
-#include "common.h"
-#include "console.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "task.h"
-#include "timer.h"
-#include "usb_pd.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_HOSTCMD, outstr)
-#define CPRINTS(format, args...) cprints(CC_HOSTCMD, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_HOSTCMD, format, ## args)
-
-/* Number of attempts for each PD host command */
-#define PD_HOST_COMMAND_ATTEMPTS 3
-
-static struct mutex pd_mutex;
-
-/**
- * Non-task-safe internal version of pd_host_command().
- *
- * Do not call this version directly!  Use pd_host_command().
- */
-static int pd_host_command_internal(int command, int version,
-				    const void *outdata, int outsize,
-				    void *indata, int insize)
-{
-	int ret, i;
-	int resp_len;
-	struct ec_host_request rq;
-	struct ec_host_response rs;
-	static uint8_t req_buf[EC_LPC_HOST_PACKET_SIZE];
-	static uint8_t resp_buf[EC_LPC_HOST_PACKET_SIZE];
-	uint8_t sum = 0;
-	const uint8_t *c;
-	uint8_t *d;
-
-	/* Fail if output size is too big */
-	if (outsize + sizeof(rq) > EC_LPC_HOST_PACKET_SIZE)
-		return -EC_RES_REQUEST_TRUNCATED;
-
-	/* Fill in request packet */
-	rq.struct_version = EC_HOST_REQUEST_VERSION;
-	rq.checksum = 0;
-	rq.command = command;
-	rq.command_version = version;
-	rq.reserved = 0;
-	rq.data_len = outsize;
-
-	/* Copy data and start checksum */
-	for (i = 0, c = (const uint8_t *)outdata; i < outsize; i++, c++) {
-		req_buf[sizeof(rq) + 1 + i] = *c;
-		sum += *c;
-	}
-
-	/* Finish checksum */
-	for (i = 0, c = (const uint8_t *)&rq; i < sizeof(rq); i++, c++)
-		sum += *c;
-
-	/* Write checksum field so the entire packet sums to 0 */
-	rq.checksum = (uint8_t)(-sum);
-
-	/* Copy header */
-	for (i = 0, c = (const uint8_t *)&rq; i < sizeof(rq); i++, c++)
-		req_buf[1 + i] = *c;
-
-	/* Set command to use protocol v3 */
-	req_buf[0] = EC_COMMAND_PROTOCOL_3;
-
-	/*
-	 * Transmit all data and receive 2 bytes for return value and response
-	 * length.
-	 */
-	i2c_lock(I2C_PORT_PD_MCU, 1);
-	i2c_set_timeout(I2C_PORT_PD_MCU, PD_HOST_COMMAND_TIMEOUT_US);
-	ret = i2c_xfer_unlocked(I2C_PORT_PD_MCU,
-				CONFIG_USB_PD_I2C_SLAVE_ADDR_FLAGS,
-				&req_buf[0], outsize + sizeof(rq) + 1,
-				&resp_buf[0], 2, I2C_XFER_START);
-	i2c_set_timeout(I2C_PORT_PD_MCU, 0);
-	if (ret) {
-		i2c_lock(I2C_PORT_PD_MCU, 0);
-		CPRINTS("i2c transaction 1 failed: %d", ret);
-		return -EC_RES_BUS_ERROR;
-	}
-
-	resp_len = resp_buf[1];
-
-	if (resp_len > (insize + sizeof(rs))) {
-		/* Do a read to generate stop condition */
-		i2c_xfer_unlocked(I2C_PORT_PD_MCU,
-				  CONFIG_USB_PD_I2C_SLAVE_ADDR_FLAGS,
-				  0, 0, &resp_buf[2], 1, I2C_XFER_STOP);
-		i2c_lock(I2C_PORT_PD_MCU, 0);
-		CPRINTS("response size is too large %d > %d",
-			resp_len, insize + sizeof(rs));
-		return -EC_RES_RESPONSE_TOO_BIG;
-	}
-
-	/* Receive remaining data */
-	ret = i2c_xfer_unlocked(I2C_PORT_PD_MCU,
-				CONFIG_USB_PD_I2C_SLAVE_ADDR_FLAGS,
-				0, 0,
-				&resp_buf[2], resp_len, I2C_XFER_STOP);
-	i2c_lock(I2C_PORT_PD_MCU, 0);
-	if (ret) {
-		CPRINTS("i2c transaction 2 failed: %d", ret);
-		return -EC_RES_BUS_ERROR;
-	}
-
-	/* Check for host command error code */
-	ret = resp_buf[0];
-	if (ret) {
-		CPRINTS("command 0x%02x returned error %d", command, ret);
-		return -ret;
-	}
-
-	/* Read back response header and start checksum */
-	sum = 0;
-	for (i = 0, d = (uint8_t *)&rs; i < sizeof(rs); i++, d++) {
-		*d = resp_buf[i + 2];
-		sum += *d;
-	}
-
-	if (rs.struct_version != EC_HOST_RESPONSE_VERSION) {
-		CPRINTS("PD response version mismatch");
-		return -EC_RES_INVALID_RESPONSE;
-	}
-
-	if (rs.reserved) {
-		CPRINTS("PD response reserved != 0");
-		return -EC_RES_INVALID_RESPONSE;
-	}
-
-	if (rs.data_len > insize) {
-		CPRINTS("PD returned too much data");
-		return -EC_RES_RESPONSE_TOO_BIG;
-	}
-
-	/* Read back data and update checksum */
-	resp_len -= sizeof(rs);
-	for (i = 0, d = (uint8_t *)indata; i < resp_len; i++, d++) {
-		*d = resp_buf[sizeof(rs) + i + 2];
-		sum += *d;
-	}
-
-
-	if ((uint8_t)sum) {
-		CPRINTS("command 0x%02x bad checksum returned: %d",
-			command, sum);
-		return -EC_RES_INVALID_CHECKSUM;
-	}
-
-	/* Return output buffer size */
-	return resp_len;
-}
-
-int pd_host_command(int command, int version,
-		    const void *outdata, int outsize,
-		    void *indata, int insize)
-{
-	int rv;
-	int tries = 0;
-
-	/* Try multiple times to send host command. */
-	for (tries = 0; tries < PD_HOST_COMMAND_ATTEMPTS; tries++) {
-		/* Acquire mutex */
-		mutex_lock(&pd_mutex);
-		/* Call internal version of host command */
-		rv = pd_host_command_internal(command, version, outdata,
-					      outsize, indata, insize);
-		/* Release mutex */
-		mutex_unlock(&pd_mutex);
-
-		/* If host command error due to i2c bus error, try again. */
-		if (rv != -EC_RES_BUS_ERROR)
-			break;
-		task_wait_event(50*MSEC);
-	}
-
-	return rv;
-}
-
-static int command_pd_mcu(int argc, char **argv)
-{
-	char *e;
-	static char __bss_slow outbuf[128];
-	static char __bss_slow inbuf[128];
-	int command, version;
-	int i, ret, tmp;
-
-	if (argc < 3)
-		return EC_ERROR_PARAM_COUNT;
-
-	command = strtoi(argv[1], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM1;
-
-	version = strtoi(argv[2], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM2;
-
-	for (i = 3; i < argc; i++) {
-		tmp = strtoi(argv[i], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM3;
-		outbuf[i-3] = tmp;
-	}
-
-	ret = pd_host_command(command, version, &outbuf, argc - 3, &inbuf,
-			sizeof(inbuf));
-
-	ccprintf("Host command 0x%02x, returned %d\n", command, ret);
-	for (i = 0; i < ret; i++)
-		ccprintf("0x%02x\n", inbuf[i]);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(pdcmd, command_pd_mcu,
-			"cmd ver [params]",
-			"Send PD host command");
-
diff --git a/common/host_command_memory_dump.c b/common/host_command_memory_dump.c
new file mode 100644
index 0000000000..f8d06c5762
--- /dev/null
+++ b/common/host_command_memory_dump.c
@@ -0,0 +1,135 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "ec_commands.h"
+#include "host_command.h"
+#include "host_command_memory_dump.h"
+#include "string.h"
+#include "task.h"
+
+#define MAX_DUMP_ENTRIES 64
+
+#ifndef CONFIG_ZEPHYR
+/* TODO(b/271883902): Add memory dump command support for CrOS EC */
+#error "Memory Dump commands are only supported on Zephyr EC."
+#endif
+
+struct memory_dump_entry {
+	uint32_t address;
+	uint32_t size;
+};
+
+static struct memory_dump_entry entries[MAX_DUMP_ENTRIES];
+static uint16_t memory_dump_entry_count;
+K_MUTEX_DEFINE(memory_dump_mutex);
+
+int register_memory_dump(uint32_t address, uint32_t size)
+{
+	mutex_lock(&memory_dump_mutex);
+
+	if (memory_dump_entry_count >= MAX_DUMP_ENTRIES) {
+		mutex_unlock(&memory_dump_mutex);
+		ccprintf("ERROR: Memory dump count exceeds max\n");
+		return EC_ERROR_OVERFLOW;
+	}
+
+	entries[memory_dump_entry_count].address = address;
+	entries[memory_dump_entry_count].size = size;
+
+	memory_dump_entry_count += 1;
+
+	mutex_unlock(&memory_dump_mutex);
+
+	return EC_SUCCESS;
+}
+
+int clear_memory_dump(void)
+{
+	mutex_lock(&memory_dump_mutex);
+	memset(entries, 0, sizeof(entries));
+	memory_dump_entry_count = 0;
+	mutex_unlock(&memory_dump_mutex);
+
+	return EC_SUCCESS;
+}
+
+static enum ec_status
+get_memory_dump_metadata(struct host_cmd_handler_args *args)
+{
+	struct ec_response_memory_dump_get_metadata *r = args->response;
+
+	mutex_lock(&memory_dump_mutex);
+
+	r->memory_dump_entry_count = memory_dump_entry_count;
+	r->memory_dump_total_size = 0;
+	for (int i = 0; i < memory_dump_entry_count; i++) {
+		r->memory_dump_total_size += entries[i].size;
+	}
+
+	mutex_unlock(&memory_dump_mutex);
+
+	args->response_size = sizeof(*r);
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_MEMORY_DUMP_GET_METADATA, get_memory_dump_metadata,
+		     EC_VER_MASK(0));
+
+static enum ec_status
+memory_dump_get_entry_info(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_memory_dump_get_entry_info *p = args->params;
+	struct ec_response_memory_dump_get_entry_info *r = args->response;
+
+	mutex_lock(&memory_dump_mutex);
+
+	if (p->memory_dump_entry_index >= memory_dump_entry_count) {
+		return EC_RES_INVALID_PARAM;
+	}
+
+	r->address = entries[p->memory_dump_entry_index].address;
+	r->size = entries[p->memory_dump_entry_index].size;
+
+	mutex_unlock(&memory_dump_mutex);
+
+	args->response_size = sizeof(*r);
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_MEMORY_DUMP_GET_ENTRY_INFO,
+		     memory_dump_get_entry_info, EC_VER_MASK(0));
+
+static enum ec_status read_memory_dump(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_memory_dump_read_memory *p = args->params;
+	void *r = args->response;
+	struct memory_dump_entry entry;
+
+	mutex_lock(&memory_dump_mutex);
+
+	if (p->memory_dump_entry_index >= memory_dump_entry_count) {
+		return EC_RES_INVALID_PARAM;
+	}
+
+	entry = entries[p->memory_dump_entry_index];
+
+	if (p->address < entry.address ||
+	    p->address + p->size > entry.address + entry.size) {
+		return EC_RES_INVALID_PARAM;
+	}
+
+	/* Must leave room for ec_host_response header */
+	args->response_size = MIN(
+		p->size, args->response_max - sizeof(struct ec_host_response));
+
+	memcpy(r, (void *)p->address, args->response_size);
+
+	mutex_unlock(&memory_dump_mutex);
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_MEMORY_DUMP_READ_MEMORY, read_memory_dump,
+		     EC_VER_MASK(0));
diff --git a/common/host_command_pd.c b/common/host_command_pd.c
index 869cad4493..062113fb0e 100644
--- a/common/host_command_pd.c
+++ b/common/host_command_pd.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,16 +14,16 @@
 #include "panic.h"
 #include "system.h"
 #include "task.h"
-#include "tcpm.h"
+#include "tcpm/tcpm.h"
 #include "timer.h"
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_PD_HOST_CMD, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_PD_HOST_CMD, format, ##args)
 
-#define TASK_EVENT_EXCHANGE_PD_STATUS  TASK_EVENT_CUSTOM_BIT(0)
-#define TASK_EVENT_HIBERNATING         TASK_EVENT_CUSTOM_BIT(1)
+#define TASK_EVENT_EXCHANGE_PD_STATUS TASK_EVENT_CUSTOM_BIT(0)
+#define TASK_EVENT_HIBERNATING TASK_EVENT_CUSTOM_BIT(1)
 
 /* Define local option for if we are a TCPM with an off chip TCPC */
 #if defined(CONFIG_USB_POWER_DELIVERY) && !defined(CONFIG_USB_PD_TCPM_STUB)
@@ -32,7 +32,7 @@
 
 #ifdef CONFIG_HOSTCMD_PD_CHG_CTRL
 /* By default allow 5V charging only for the dead battery case */
-static enum pd_charge_state charge_state = PD_CHARGE_5V;
+static enum pd_charge_state pd_chg_state = PD_CHARGE_5V;
 
 #define CHARGE_PORT_UNINITIALIZED -2
 static int charge_port = CHARGE_PORT_UNINITIALIZED;
@@ -48,20 +48,20 @@ void host_command_pd_send_status(enum pd_charge_state new_chg_state)
 #ifdef CONFIG_HOSTCMD_PD_CHG_CTRL
 	/* Update PD MCU charge state if necessary */
 	if (new_chg_state != PD_CHARGE_NO_CHANGE)
-		charge_state = new_chg_state;
+		pd_chg_state = new_chg_state;
 #endif
 	/* Wake PD HC task to send status */
-	task_set_event(TASK_ID_PDCMD, TASK_EVENT_EXCHANGE_PD_STATUS, 0);
+	task_set_event(TASK_ID_PDCMD, TASK_EVENT_EXCHANGE_PD_STATUS);
 }
 
 void host_command_pd_request_hibernate(void)
 {
-	task_set_event(TASK_ID_PDCMD, TASK_EVENT_HIBERNATING, 0);
+	task_set_event(TASK_ID_PDCMD, TASK_EVENT_HIBERNATING);
 }
 
 #ifdef CONFIG_HOSTCMD_PD
 static int pd_send_host_command(struct ec_params_pd_status *ec_status,
-	struct ec_response_pd_status *pd_status)
+				struct ec_response_pd_status *pd_status)
 {
 	return pd_host_command(EC_CMD_PD_EXCHANGE_STATUS,
 			       EC_VER_PD_EXCHANGE_STATUS, ec_status,
@@ -74,7 +74,7 @@ static void pd_exchange_update_ec_status(struct ec_params_pd_status *ec_status,
 {
 	/* Send PD charge state and battery state of charge */
 #ifdef CONFIG_HOSTCMD_PD_CHG_CTRL
-	ec_status->charge_state = charge_state;
+	ec_status->charge_state = pd_chg_state;
 #endif
 	if (charge_get_flags() & CHARGE_FLAG_BATT_RESPONSIVE)
 		ec_status->batt_soc = charge_get_percent();
@@ -126,10 +126,7 @@ static void pd_check_chg_status(struct ec_response_pd_status *pd_status)
 #endif
 
 	/* Set input current limit */
-	rv = charge_set_input_current_limit(MAX(pd_status->curr_lim_ma,
-					CONFIG_CHARGER_INPUT_CURRENT), 0);
-	if (rv < 0)
-		CPRINTS("Failed to set input curr limit from PD MCU");
+	board_set_charge_limit(pd_status->curr_lim_ma, 0);
 }
 #endif /* CONFIG_HOSTCMD_PD_CHG_CTRL */
 #endif /* CONFIG_HOSTCMD_PD */
@@ -201,7 +198,7 @@ static void pd_exchange_status(uint32_t ec_state)
 
 		if (!first_exchange)
 			/* Delay to prevent task starvation */
-			usleep(5*MSEC);
+			usleep(5 * MSEC);
 		first_exchange = 0;
 	} while (pd_get_alert());
 #endif /* USB_TCPM_WITH_OFF_CHIP_TCPC */
@@ -226,4 +223,3 @@ void pd_command_task(void *u)
 			pd_exchange_status(ec_state);
 	}
 }
-
diff --git a/common/host_event_commands.c b/common/host_event_commands.c
index 9ab7f19d04..a89c89382d 100644
--- a/common/host_event_commands.c
+++ b/common/host_event_commands.c
@@ -1,10 +1,11 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Host event commands for Chrome EC */
 
+#include "chipset.h"
 #include "common.h"
 #include "console.h"
 #include "hooks.h"
@@ -18,13 +19,13 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_EVENTS, outstr)
-#define CPRINTS(format, args...) cprints(CC_EVENTS, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_EVENTS, format, ##args)
 
 /*
  * This is used to avoid 64-bit shifts which might require a new library
  * function.
  */
-#define HOST_EVENT_32BIT_MASK(x)	(1UL << ((x) - 1))
+#define HOST_EVENT_32BIT_MASK(x) (1UL << ((x)-1))
 static void host_event_set_bit(host_event_t *ev, uint8_t bit)
 {
 	uint32_t *ptr = (uint32_t *)ev;
@@ -38,17 +39,19 @@ static void host_event_set_bit(host_event_t *ev, uint8_t bit)
 	if (bit == 0)
 		return;
 
-#ifdef CONFIG_HOST_EVENT64
+	/*
+	 * The overall host event implementation assumes it's running on and
+	 * communicating with little-endian architectures.
+	 */
 	if (bit > 32)
 		*(ptr + 1) = HOST_EVENT_32BIT_MASK(bit - 32);
 	else
-#endif
 		*ptr = HOST_EVENT_32BIT_MASK(bit);
 }
 
 #ifdef CONFIG_HOSTCMD_X86
 
-#define LPC_SYSJUMP_TAG 0x4c50  /* "LP" */
+#define LPC_SYSJUMP_TAG 0x4c50 /* "LP" */
 #define LPC_SYSJUMP_OLD_VERSION 1
 #define LPC_SYSJUMP_VERSION 2
 
@@ -71,14 +74,14 @@ static void host_event_set_bit(host_event_t *ev, uint8_t bit)
  *   - EC_HOST_EVENT_MKBP
  *
  */
-#define LPC_HOST_EVENT_ALWAYS_REPORT_DEFAULT_MASK			\
-	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY) |		\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |		\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |		\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_REBOOT) |		\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC) |			\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_FASTBOOT) |		\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |			\
+#define LPC_HOST_EVENT_ALWAYS_REPORT_DEFAULT_MASK              \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |  \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |  \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_REBOOT) |       \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC) |             \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_FASTBOOT) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |              \
 	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT))
 
 static host_event_t lpc_host_events;
@@ -113,7 +116,7 @@ static host_event_t lpc_get_all_host_event_masks(void)
 	return or_mask;
 }
 
-static void lpc_set_host_event_state(host_event_t events)
+test_export_static void lpc_set_host_event_state(host_event_t events)
 {
 	if (events == lpc_host_events)
 		return;
@@ -135,21 +138,25 @@ host_event_t lpc_get_host_events(void)
 int lpc_get_next_host_event(void)
 {
 	host_event_t ev;
-	int evt_idx =  __builtin_ffs(lpc_host_events);
+	int evt_idx = __builtin_ffs(lpc_host_events);
 
-#ifdef CONFIG_HOST_EVENT64
 	if (evt_idx == 0) {
 		int evt_idx_high = __builtin_ffs(lpc_host_events >> 32);
 
 		if (evt_idx_high)
 			evt_idx = 32 + evt_idx_high;
 	}
-#endif
 
 	if (evt_idx) {
 		host_event_set_bit(&ev, evt_idx);
 		host_clear_events(ev);
 	}
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+	else {
+		/* Workaround, call function to clear SCI event when index = 0") */
+		lpc_update_host_event_status();
+	}
+#endif
 	return evt_idx;
 }
 
@@ -174,7 +181,7 @@ static int lpc_post_sysjump_restore_mask(void)
 	int size, version;
 
 	prev_mask = (const host_event_t *)system_get_jump_tag(LPC_SYSJUMP_TAG,
-			&version, &size);
+							      &version, &size);
 	if (!prev_mask || size != sizeof(lpc_host_event_mask) ||
 	    (version != LPC_SYSJUMP_VERSION &&
 	     version != LPC_SYSJUMP_OLD_VERSION))
@@ -264,28 +271,23 @@ static struct lazy_wake_masks {
 
 static void host_events_atomic_or(host_event_t *e, host_event_t m)
 {
-	uint32_t *ptr = (uint32_t *)e;
+	atomic_t *ptr = (atomic_t *)e;
 
-	deprecated_atomic_or(ptr, (uint32_t)m);
-#ifdef CONFIG_HOST_EVENT64
-	deprecated_atomic_or(ptr + 1, (uint32_t)(m >> 32));
-#endif
+	atomic_or(ptr, (uint32_t)m);
+	atomic_or(ptr + 1, (uint32_t)(m >> 32));
 }
 
 static void host_events_atomic_clear(host_event_t *e, host_event_t m)
 {
-	uint32_t *ptr = (uint32_t *)e;
+	atomic_t *ptr = (atomic_t *)e;
 
-	deprecated_atomic_clear_bits(ptr, (uint32_t)m);
-#ifdef CONFIG_HOST_EVENT64
-	deprecated_atomic_clear_bits(ptr + 1, (uint32_t)(m >> 32));
-#endif
+	atomic_clear_bits(ptr, (uint32_t)m);
+	atomic_clear_bits(ptr + 1, (uint32_t)(m >> 32));
 }
 
 #if !defined(CONFIG_HOSTCMD_X86) && defined(CONFIG_MKBP_EVENT)
 static void host_events_send_mkbp_event(host_event_t e)
 {
-#ifdef CONFIG_HOST_EVENT64
 	/*
 	 * If event bits in the upper 32-bit are set, indicate 64-bit host
 	 * event.
@@ -293,7 +295,6 @@ static void host_events_send_mkbp_event(host_event_t e)
 	if (!(uint32_t)e)
 		mkbp_send_event(EC_MKBP_EVENT_HOST_EVENT64);
 	else
-#endif
 		mkbp_send_event(EC_MKBP_EVENT_HOST_EVENT);
 }
 #endif
@@ -306,11 +307,7 @@ host_event_t host_get_events(void)
 void host_set_events(host_event_t mask)
 {
 	/* ignore host events the rest of board doesn't care about */
-#ifdef CONFIG_HOST_EVENT64
-	mask &= CONFIG_HOST_EVENT64_REPORT_MASK;
-#else
 	mask &= CONFIG_HOST_EVENT_REPORT_MASK;
-#endif
 
 #ifdef CONFIG_HOSTCMD_X86
 	/*
@@ -330,6 +327,10 @@ void host_set_events(host_event_t mask)
 
 	HOST_EVENT_CPRINTS("event set", mask);
 
+	if (!IS_ENABLED(CONFIG_ZTEST) &&
+	    (mask & EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)))
+		system_enter_manual_recovery();
+
 	host_events_atomic_or(&events, mask);
 	host_events_atomic_or(&events_copy_b, mask);
 
@@ -342,8 +343,8 @@ void host_set_events(host_event_t mask)
 #error "Config error: MKBP must not be on top of host event"
 #endif
 	host_events_send_mkbp_event(events);
-#endif  /* CONFIG_MKBP_EVENT */
-#endif  /* !CONFIG_HOSTCMD_X86 */
+#endif /* CONFIG_MKBP_EVENT */
+#endif /* !CONFIG_HOSTCMD_X86 */
 }
 
 void host_set_single_event(enum host_event_code event)
@@ -365,16 +366,17 @@ int host_is_event_set(enum host_event_code event)
 void host_clear_events(host_event_t mask)
 {
 	/* ignore host events the rest of board doesn't care about */
-#ifdef CONFIG_HOST_EVENT64
-	mask &= CONFIG_HOST_EVENT64_REPORT_MASK;
-#else
 	mask &= CONFIG_HOST_EVENT_REPORT_MASK;
-#endif
 
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+	/* return early if nothing changed */
+	if (!(lpc_host_events & mask))
+		return;
+#else
 	/* return early if nothing changed */
 	if (!(events & mask))
 		return;
-
+#endif
 	HOST_EVENT_CPRINTS("event clear", mask);
 
 	host_events_atomic_clear(&events, mask);
@@ -386,7 +388,7 @@ void host_clear_events(host_event_t mask)
 #ifdef CONFIG_MKBP_EVENT
 	host_events_send_mkbp_event(events);
 #endif
-#endif  /* !CONFIG_HOSTCMD_X86 */
+#endif /* !CONFIG_HOSTCMD_X86 */
 }
 
 #ifndef CONFIG_HOSTCMD_X86
@@ -400,7 +402,6 @@ static int host_get_next_event(uint8_t *out)
 }
 DECLARE_EVENT_SOURCE(EC_MKBP_EVENT_HOST_EVENT, host_get_next_event);
 
-#ifdef CONFIG_HOST_EVENT64
 static int host_get_next_event64(uint8_t *out)
 {
 	host_event_t event_out = events;
@@ -412,7 +413,6 @@ static int host_get_next_event64(uint8_t *out)
 }
 DECLARE_EVENT_SOURCE(EC_MKBP_EVENT_HOST_EVENT64, host_get_next_event64);
 #endif
-#endif
 
 /**
  * Clear one or more host event bits from copy B.
@@ -454,12 +454,12 @@ DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, clear_events_copy_b, HOOK_PRIO_DEFAULT);
 
 /*****************************************************************************/
 /* Console commands */
-static int command_host_event(int argc, char **argv)
+static int command_host_event(int argc, const char **argv)
 {
 	/* Handle sub-commands */
 	if (argc == 3) {
 		char *e;
-		host_event_t i = strtoul(argv[2], &e, 0);
+		host_event_t i = strtoull(argv[2], &e, 0);
 		if (*e)
 			return EC_ERROR_PARAM2;
 
@@ -489,19 +489,21 @@ static int command_host_event(int argc, char **argv)
 	HOST_EVENT_CCPRINTF("Events-B:           ", events_copy_b);
 #ifdef CONFIG_HOSTCMD_X86
 	HOST_EVENT_CCPRINTF("SMI mask:           ",
-		 lpc_get_host_event_mask(LPC_HOST_EVENT_SMI));
+			    lpc_get_host_event_mask(LPC_HOST_EVENT_SMI));
 	HOST_EVENT_CCPRINTF("SCI mask:           ",
-		 lpc_get_host_event_mask(LPC_HOST_EVENT_SCI));
+			    lpc_get_host_event_mask(LPC_HOST_EVENT_SCI));
 	HOST_EVENT_CCPRINTF("Wake mask:          ",
-		 lpc_get_host_event_mask(LPC_HOST_EVENT_WAKE));
-	HOST_EVENT_CCPRINTF("Always report mask: ",
-		 lpc_get_host_event_mask(LPC_HOST_EVENT_ALWAYS_REPORT));
+			    lpc_get_host_event_mask(LPC_HOST_EVENT_WAKE));
+	HOST_EVENT_CCPRINTF(
+		"Always report mask: ",
+		lpc_get_host_event_mask(LPC_HOST_EVENT_ALWAYS_REPORT));
 #endif
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(hostevent, command_host_event,
-			"[set | clear | clearb | smi | sci | wake | always_report] [mask]",
-			"Print / set host event state");
+DECLARE_CONSOLE_COMMAND(
+	hostevent, command_host_event,
+	"[set | clear | clearb | smi | sci | wake | always_report] [mask]",
+	"Print / set host event state");
 
 /*****************************************************************************/
 /* Host commands */
@@ -518,8 +520,7 @@ host_event_get_smi_mask(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_GET_SMI_MASK,
-		     host_event_get_smi_mask,
+DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_GET_SMI_MASK, host_event_get_smi_mask,
 		     EC_VER_MASK(0));
 
 static enum ec_status
@@ -532,8 +533,7 @@ host_event_get_sci_mask(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_GET_SCI_MASK,
-		     host_event_get_sci_mask,
+DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_GET_SCI_MASK, host_event_get_sci_mask,
 		     EC_VER_MASK(0));
 
 static enum ec_status
@@ -546,8 +546,7 @@ host_event_get_wake_mask(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_GET_WAKE_MASK,
-		     host_event_get_wake_mask,
+DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_GET_WAKE_MASK, host_event_get_wake_mask,
 		     EC_VER_MASK(0));
 
 static enum ec_status
@@ -558,8 +557,7 @@ host_event_set_smi_mask(struct host_cmd_handler_args *args)
 	lpc_set_host_event_mask(LPC_HOST_EVENT_SMI, p->mask);
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_SET_SMI_MASK,
-		     host_event_set_smi_mask,
+DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_SET_SMI_MASK, host_event_set_smi_mask,
 		     EC_VER_MASK(0));
 
 static enum ec_status
@@ -570,8 +568,7 @@ host_event_set_sci_mask(struct host_cmd_handler_args *args)
 	lpc_set_host_event_mask(LPC_HOST_EVENT_SCI, p->mask);
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_SET_SCI_MASK,
-		     host_event_set_sci_mask,
+DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_SET_SCI_MASK, host_event_set_sci_mask,
 		     EC_VER_MASK(0));
 
 static enum ec_status
@@ -583,8 +580,7 @@ host_event_set_wake_mask(struct host_cmd_handler_args *args)
 	active_wm_set_by_host = !!p->mask;
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_SET_WAKE_MASK,
-		     host_event_set_wake_mask,
+DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_SET_WAKE_MASK, host_event_set_wake_mask,
 		     EC_VER_MASK(0));
 
 uint8_t lpc_is_active_wm_set_by_host(void)
@@ -592,7 +588,7 @@ uint8_t lpc_is_active_wm_set_by_host(void)
 	return active_wm_set_by_host;
 }
 
-#endif  /* CONFIG_HOSTCMD_X86 */
+#endif /* CONFIG_HOSTCMD_X86 */
 
 static enum ec_status host_event_get_b(struct host_cmd_handler_args *args)
 {
@@ -603,9 +599,7 @@ static enum ec_status host_event_get_b(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_GET_B,
-		     host_event_get_b,
-		     EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_GET_B, host_event_get_b, EC_VER_MASK(0));
 
 static enum ec_status host_event_clear(struct host_cmd_handler_args *args)
 {
@@ -614,9 +608,7 @@ static enum ec_status host_event_clear(struct host_cmd_handler_args *args)
 	host_clear_events(p->mask);
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_CLEAR,
-		     host_event_clear,
-		     EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_CLEAR, host_event_clear, EC_VER_MASK(0));
 
 static enum ec_status host_event_clear_b(struct host_cmd_handler_args *args)
 {
@@ -625,8 +617,7 @@ static enum ec_status host_event_clear_b(struct host_cmd_handler_args *args)
 	host_clear_events_b(p->mask);
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_CLEAR_B,
-		     host_event_clear_b,
+DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_CLEAR_B, host_event_clear_b,
 		     EC_VER_MASK(0));
 
 static enum ec_status host_event_action_get(struct host_cmd_handler_args *args)
@@ -653,8 +644,8 @@ static enum ec_status host_event_action_get(struct host_cmd_handler_args *args)
 		r->value = lpc_get_host_event_mask(LPC_HOST_EVENT_SMI);
 		break;
 	case EC_HOST_EVENT_ALWAYS_REPORT_MASK:
-		r->value = lpc_get_host_event_mask
-				(LPC_HOST_EVENT_ALWAYS_REPORT);
+		r->value =
+			lpc_get_host_event_mask(LPC_HOST_EVENT_ALWAYS_REPORT);
 		break;
 	case EC_HOST_EVENT_ACTIVE_WAKE_MASK:
 		r->value = lpc_get_host_event_mask(LPC_HOST_EVENT_WAKE);
@@ -699,7 +690,7 @@ static enum ec_status host_event_action_set(struct host_cmd_handler_args *args)
 		break;
 	case EC_HOST_EVENT_ALWAYS_REPORT_MASK:
 		lpc_set_host_event_mask(LPC_HOST_EVENT_ALWAYS_REPORT,
-						mask_value);
+					mask_value);
 		break;
 	case EC_HOST_EVENT_ACTIVE_WAKE_MASK:
 		active_wm_set_by_host = !!mask_value;
@@ -778,12 +769,11 @@ host_command_host_event(struct host_cmd_handler_args *args)
 	}
 }
 
-DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT,
-		     host_command_host_event,
+DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT, host_command_host_event,
 		     EC_VER_MASK(0));
 
-#define LAZY_WAKE_MASK_SYSJUMP_TAG		0x4C4D /* LM - Lazy Mask*/
-#define LAZY_WAKE_MASK_HOOK_VERSION		1
+#define LAZY_WAKE_MASK_SYSJUMP_TAG 0x4C4D /* LM - Lazy Mask*/
+#define LAZY_WAKE_MASK_HOOK_VERSION 1
 
 #ifdef CONFIG_HOSTCMD_X86
 int get_lazy_wake_mask(enum power_state state, host_event_t *mask)
@@ -813,8 +803,7 @@ int get_lazy_wake_mask(enum power_state state, host_event_t *mask)
 static void preserve_lazy_wm(void)
 {
 	system_add_jump_tag(LAZY_WAKE_MASK_SYSJUMP_TAG,
-			    LAZY_WAKE_MASK_HOOK_VERSION,
-			    sizeof(lazy_wm),
+			    LAZY_WAKE_MASK_HOOK_VERSION, sizeof(lazy_wm),
 			    &lazy_wm);
 }
 DECLARE_HOOK(HOOK_SYSJUMP, preserve_lazy_wm, HOOK_PRIO_DEFAULT);
@@ -824,14 +813,13 @@ static void restore_lazy_wm(void)
 	const struct lazy_wake_masks *wm_state;
 	int version, size;
 
-	wm_state = (const struct lazy_wake_masks *)
-			system_get_jump_tag(LAZY_WAKE_MASK_SYSJUMP_TAG,
-				 &version, &size);
+	wm_state = (const struct lazy_wake_masks *)system_get_jump_tag(
+		LAZY_WAKE_MASK_SYSJUMP_TAG, &version, &size);
 
 	if (wm_state && (version == LAZY_WAKE_MASK_HOOK_VERSION) &&
 	    (size == sizeof(lazy_wm))) {
 		lazy_wm = *wm_state;
 	}
 }
-DECLARE_HOOK(HOOK_INIT, restore_lazy_wm, HOOK_PRIO_INIT_CHIPSET + 1);
+DECLARE_HOOK(HOOK_INIT, restore_lazy_wm, HOOK_PRIO_POST_CHIPSET);
 #endif
diff --git a/common/hotword_dsp_api.c b/common/hotword_dsp_api.c
index dc53cd0055..24291df8c0 100644
--- a/common/hotword_dsp_api.c
+++ b/common/hotword_dsp_api.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/common/i2c_bitbang.c b/common/i2c_bitbang.c
index 238cc182ff..01d4f5f31e 100644
--- a/common/i2c_bitbang.c
+++ b/common/i2c_bitbang.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,7 +10,8 @@
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
+#define CPUTS(str) cputs(CC_I2C, str)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
 
 static int started;
 
@@ -21,8 +22,8 @@ static void i2c_delay(void)
 }
 
 /* Number of attempts to unwedge each pin. */
-#define UNWEDGE_SCL_ATTEMPTS  10
-#define UNWEDGE_SDA_ATTEMPTS  3
+#define UNWEDGE_SCL_ATTEMPTS 10
+#define UNWEDGE_SDA_ATTEMPTS 3
 
 static void i2c_bitbang_unwedge(const struct i2c_port_t *i2c_port)
 {
@@ -31,17 +32,16 @@ static void i2c_bitbang_unwedge(const struct i2c_port_t *i2c_port)
 	gpio_set_level(i2c_port->scl, 1);
 	/*
 	 * If clock is low, wait for a while in case of clock stretched
-	 * by a slave.
+	 * by a peripheral.
 	 */
 	if (!gpio_get_level(i2c_port->scl)) {
 		for (i = 0;; i++) {
 			if (i >= UNWEDGE_SCL_ATTEMPTS) {
 				/*
-				 * If we get here, a slave is holding the clock
-				 * low and there is nothing we can do.
+				 * If we get here, a peripheral is holding the
+				 * clock low and there is nothing we can do.
 				 */
-				CPRINTS("I2C%d unwedge failed, "
-					"SCL is held low", i2c_port->port);
+				CPUTS("I2C unwedge failed, SCL is held low\n");
 				return;
 			}
 			i2c_delay();
@@ -53,7 +53,7 @@ static void i2c_bitbang_unwedge(const struct i2c_port_t *i2c_port)
 	if (gpio_get_level(i2c_port->sda))
 		return;
 
-	CPRINTS("I2C%d unwedge called with SDA held low", i2c_port->port);
+	CPUTS("I2C unwedge called with SDA held low\n");
 
 	/* Keep trying to unwedge the SDA line until we run out of attempts. */
 	for (i = 0; i < UNWEDGE_SDA_ATTEMPTS; i++) {
@@ -62,9 +62,9 @@ static void i2c_bitbang_unwedge(const struct i2c_port_t *i2c_port)
 		i2c_delay();
 
 		/*
-		 * Clock through the problem by clocking out 9 bits. If slave
-		 * releases the SDA line, then we can stop clocking bits and
-		 * send a STOP.
+		 * Clock through the problem by clocking out 9 bits. If
+		 * peripheral releases the SDA line, then we can stop clocking
+		 * bits and send a STOP.
 		 */
 		for (j = 0; j < 9; j++) {
 			if (gpio_get_level(i2c_port->sda))
@@ -84,14 +84,14 @@ static void i2c_bitbang_unwedge(const struct i2c_port_t *i2c_port)
 
 		/* Check if the bus is unwedged. */
 		if (gpio_get_level(i2c_port->sda) &&
-				gpio_get_level(i2c_port->scl))
+		    gpio_get_level(i2c_port->scl))
 			break;
 	}
 
 	if (!gpio_get_level(i2c_port->sda))
-		CPRINTS("I2C%d unwedge failed, SDA still low", i2c_port->port);
+		CPUTS("I2C unwedge failed, SDA still low\n");
 	if (!gpio_get_level(i2c_port->scl))
-		CPRINTS("I2C%d unwedge failed, SCL still low", i2c_port->port);
+		CPUTS("I2C unwedge failed, SCL still low\n");
 }
 
 static void i2c_stop_cond(const struct i2c_port_t *i2c_port)
@@ -110,9 +110,9 @@ static void i2c_stop_cond(const struct i2c_port_t *i2c_port)
 	 * SMBus 3.0, 4.2.5
 	 *
 	 *  the recommendation is that if SMBDAT is still low tTIMEOUT,MAX after
-	 *  SMBCLK has gone high at the end of a transaction the master should
-	 *  hold SMBCLK low for at least tTIMEOUT,MAX in an attempt to reset the
-	 *  SMBus interface of all of the devices on the bus.
+	 *  SMBCLK has gone high at the end of a transaction the controller
+	 *  should hold SMBCLK low for at least tTIMEOUT,MAX in an attempt to
+	 *  reset the SMBus interface of all of the devices on the bus.
 	 */
 	for (i = 0; i < 7000; i++) {
 		if (gpio_get_level(i2c_port->scl))
@@ -145,12 +145,12 @@ static int clock_stretching(const struct i2c_port_t *i2c_port)
 	 * Devices participating in a transfer can abort the transfer in
 	 * progress and release the bus when any single clock low interval
 	 * exceeds the value of tTIMEOUT,MIN(=25ms).
-	 * After the master in a transaction detects this condition, it must
+	 * After the controller in a transaction detects this condition, it must
 	 * generate a stop condition within or after the current data byte in
 	 * the transfer process.
 	 */
 	i2c_stop_cond(i2c_port);
-	CPRINTS("clock low timeout");
+	CPUTS("clock low timeout\n");
 
 	return EC_ERROR_TIMEOUT;
 }
@@ -170,7 +170,7 @@ static int i2c_start_cond(const struct i2c_port_t *i2c_port)
 		i2c_delay();
 
 		if (gpio_get_level(i2c_port->sda) == 0) {
-			CPRINTS("%s: arbitration lost", __func__);
+			CPUTS("start_cond: arbitration lost\n");
 			started = 0;
 			return EC_ERROR_UNKNOWN;
 		}
@@ -204,7 +204,7 @@ static int i2c_write_bit(const struct i2c_port_t *i2c_port, int bit)
 	i2c_delay();
 
 	if (bit && gpio_get_level(i2c_port->sda) == 0) {
-		CPRINTS("%s: arbitration lost", __func__);
+		CPUTS("write_bit: arbitration lost\n");
 		started = 0;
 		return EC_ERROR_UNKNOWN;
 	}
@@ -249,10 +249,11 @@ static int i2c_write_byte(const struct i2c_port_t *i2c_port, uint8_t byte)
 
 	if (nack) {
 		/*
-		 * The slave device detects an invalid command or invalid data.
-		 * In this case the slave device must NACK the received byte.
-		 * The master upon detection of this condition must generate a
-		 * STOP condition and retry the transaction
+		 * The peripheral device detects an invalid command or invalid
+		 * data. In this case the peripheral device must NACK the
+		 * received byte. The controller upon detection of this
+		 * condition must generate a STOP condition and retry the
+		 * transaction
 		 */
 		i2c_stop_cond(i2c_port);
 		/* return EC_ERROR_BUSY to indicate i2c_xfer() to retry */
@@ -262,7 +263,7 @@ static int i2c_write_byte(const struct i2c_port_t *i2c_port, uint8_t byte)
 }
 
 static int i2c_read_byte(const struct i2c_port_t *i2c_port, uint8_t *byte,
-		int nack)
+			 int nack)
 {
 	int i;
 
@@ -280,15 +281,14 @@ static int i2c_read_byte(const struct i2c_port_t *i2c_port, uint8_t *byte,
 }
 
 static int i2c_bitbang_xfer(const struct i2c_port_t *i2c_port,
-		const uint16_t slave_addr_flags,
-		const uint8_t *out, int out_size,
-		uint8_t *in, int in_size, int flags)
+			    const uint16_t addr_flags, const uint8_t *out,
+			    int out_size, uint8_t *in, int in_size, int flags)
 {
-	uint16_t addr_8bit = slave_addr_flags << 1, err = EC_SUCCESS;
+	uint16_t addr_8bit = addr_flags << 1, err = EC_SUCCESS;
 	int i = 0;
 
 	if (i2c_port->kbps != 100)
-		CPRINTS("warning: bitbang driver only supports 100kbps");
+		CPUTS("warning: bitbang driver only supports 100kbps\n");
 
 	if (out_size) {
 		if (flags & I2C_XFER_START) {
@@ -319,7 +319,8 @@ static int i2c_bitbang_xfer(const struct i2c_port_t *i2c_port,
 
 		for (i = 0; i < in_size; i++) {
 			err = i2c_read_byte(i2c_port, &in[i],
-				(flags & I2C_XFER_STOP) && (i == in_size - 1));
+					    (flags & I2C_XFER_STOP) &&
+						    (i == in_size - 1));
 			if (err)
 				goto exit;
 		}
@@ -336,9 +337,23 @@ static int i2c_bitbang_xfer(const struct i2c_port_t *i2c_port,
 	return err;
 }
 
-const struct i2c_drv bitbang_drv = {
-	.xfer = &i2c_bitbang_xfer
-};
+void enable_i2c_raw_mode(bool enable)
+{
+	int i;
+
+	for (i = 0; i < i2c_bitbang_ports_used; i++) {
+		if (i2c_raw_mode(i2c_bitbang_ports[i].port, enable))
+			CPRINTS("I2C p%d: Failed to %s raw mode",
+				i2c_bitbang_ports[i].port,
+				enable ? "enable" : "disable");
+	}
+}
+
+__overridable void board_pre_task_i2c_peripheral_init(void)
+{
+}
+
+const struct i2c_drv bitbang_drv = { .xfer = &i2c_bitbang_xfer };
 
 #ifdef TEST_BUILD
 int bitbang_start_cond(const struct i2c_port_t *i2c_port)
diff --git a/common/i2c_controller.c b/common/i2c_controller.c
new file mode 100644
index 0000000000..568e8832d0
--- /dev/null
+++ b/common/i2c_controller.c
@@ -0,0 +1,1530 @@
+/* Copyright 2013 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* I2C cross-platform code for Chrome EC */
+
+#include "battery.h"
+#include "builtin/assert.h"
+#include "charge_state.h"
+#include "clock.h"
+#include "console.h"
+#include "crc8.h"
+#include "gpio.h"
+#include "host_command.h"
+#include "i2c.h"
+#include "i2c_bitbang.h"
+#include "i2c_private.h"
+#include "printf.h"
+#include "system.h"
+#include "task.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "util.h"
+#include "virtual_battery.h"
+#include "watchdog.h"
+
+#ifdef CONFIG_ZEPHYR
+#include "i2c/i2c.h"
+
+#include <zephyr/drivers/i2c.h>
+#endif /* CONFIG_ZEPHYR */
+
+#define CPUTS(outstr) cputs(CC_I2C, outstr)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args)
+
+/* Only chips with multi-port controllers will define I2C_CONTROLLER_COUNT */
+#ifndef I2C_CONTROLLER_COUNT
+#define I2C_CONTROLLER_COUNT I2C_PORT_COUNT
+#endif
+
+#ifndef CONFIG_I2C_BITBANG
+#define I2C_BITBANG_PORT_COUNT 0
+#endif
+
+static mutex_t port_mutex[I2C_CONTROLLER_COUNT + I2C_BITBANG_PORT_COUNT];
+
+/* A bitmap of the controllers which are currently servicing a request. */
+static volatile uint32_t i2c_port_active_list;
+BUILD_ASSERT(ARRAY_SIZE(port_mutex) < 32);
+static uint8_t port_protected[I2C_PORT_COUNT + I2C_BITBANG_PORT_COUNT];
+
+#ifdef CONFIG_ZEPHYR
+static int init_port_mutex(void)
+{
+	for (int i = 0; i < ARRAY_SIZE(port_mutex); ++i)
+		k_mutex_init(port_mutex + i);
+
+	return 0;
+}
+SYS_INIT(init_port_mutex, POST_KERNEL, 50);
+#endif /* CONFIG_ZEPHYR */
+
+/**
+ * Non-deterministically test the lock status of the port.  If another task
+ * has locked the port and the caller is accessing it illegally, then this test
+ * will incorrectly return true.  However, callers which failed to statically
+ * lock the port will fail quickly.
+ */
+STATIC_IF_NOT(CONFIG_ZTEST)
+int i2c_port_is_locked(int port)
+{
+#ifdef CONFIG_I2C_MULTI_PORT_CONTROLLER
+	/* Test the controller, not the port */
+	port = i2c_port_to_controller(port);
+#endif
+	/* can't lock a non-existing port */
+	if (port < 0)
+		return 0;
+
+	return (i2c_port_active_list >> port) & 1;
+}
+
+const struct i2c_port_t *get_i2c_port(const int port)
+{
+	int i;
+
+	/*
+	 * If the EC's I2C driver implementation is task event based and the
+	 * I2C is accessed before the task is initialized, it causes the system
+	 * panic hence these I2C will fall back to bitbang mode if enabled at
+	 * board level and will again switch back to event based I2C upon task
+	 * initialization.
+	 */
+	if (task_start_called()) {
+		/* Find the matching port in i2c_ports[] table. */
+		for (i = 0; i < i2c_ports_used; i++) {
+			if (i2c_ports[i].port == port)
+				return &i2c_ports[i];
+		}
+	}
+
+	if (IS_ENABLED(CONFIG_I2C_BITBANG)) {
+		/* Find the matching port in i2c_bitbang_ports[] table. */
+		for (i = 0; i < i2c_bitbang_ports_used; i++) {
+			if (i2c_bitbang_ports[i].port == port)
+				return &i2c_bitbang_ports[i];
+		}
+	}
+
+	return NULL;
+}
+
+__maybe_unused static int chip_i2c_xfer_with_notify(const int port,
+						    const uint16_t addr_flags,
+						    const uint8_t *out,
+						    int out_size, uint8_t *in,
+						    int in_size, int flags)
+{
+	int ret;
+	uint16_t no_pec_af = addr_flags;
+	const struct i2c_port_t *i2c_port = get_i2c_port(port);
+
+	if (i2c_port == NULL)
+		return EC_ERROR_INVAL;
+
+	if (IS_ENABLED(CONFIG_I2C_XFER_BOARD_CALLBACK))
+		i2c_start_xfer_notify(port, addr_flags);
+
+	if (IS_ENABLED(CONFIG_SMBUS_PEC))
+		/*
+		 * Since we've done PEC processing here,
+		 * remove the flag so it won't confuse chip driver.
+		 */
+		no_pec_af &= ~I2C_FLAG_PEC;
+
+	if (i2c_port->drv)
+		ret = i2c_port->drv->xfer(i2c_port, no_pec_af, out, out_size,
+					  in, in_size, flags);
+	else
+		ret = chip_i2c_xfer(port, no_pec_af, out, out_size, in, in_size,
+				    flags);
+
+	if (IS_ENABLED(CONFIG_I2C_XFER_BOARD_CALLBACK))
+		i2c_end_xfer_notify(port, addr_flags);
+
+	if (IS_ENABLED(CONFIG_I2C_DEBUG)) {
+		i2c_trace_notify(port, addr_flags, out, out_size, in, in_size,
+				 ret);
+	}
+
+	return ret;
+}
+
+#ifdef CONFIG_I2C_XFER_LARGE_TRANSFER
+/*
+ * Internal function that splits transfer into multiple chip_i2c_xfer() calls
+ * if in_size or out_size exceeds CONFIG_I2C_CHIP_MAX_TRANSFER_SIZE.
+ */
+static int i2c_xfer_no_retry(const int port, const uint16_t addr_flags,
+			     const uint8_t *out, int out_size, uint8_t *in,
+			     int in_size, int flags)
+{
+	int offset;
+
+	for (offset = 0; offset < out_size;) {
+		int chunk_size = MIN(out_size - offset,
+				     CONFIG_I2C_CHIP_MAX_TRANSFER_SIZE);
+		int out_flags = 0;
+
+		if (offset == 0)
+			out_flags |= flags & I2C_XFER_START;
+		if (in_size == 0 && offset + chunk_size == out_size)
+			out_flags |= flags & I2C_XFER_STOP;
+
+		RETURN_ERROR(chip_i2c_xfer_with_notify(port, addr_flags,
+						       out + offset, chunk_size,
+						       NULL, 0, out_flags));
+		offset += chunk_size;
+	}
+	for (offset = 0; offset < in_size;) {
+		int chunk_size = MIN(in_size - offset,
+				     CONFIG_I2C_CHIP_MAX_TRANSFER_SIZE);
+		int in_flags = 0;
+
+		if (offset == 0)
+			in_flags |= flags & I2C_XFER_START;
+		if (offset + chunk_size == in_size)
+			in_flags |= flags & I2C_XFER_STOP;
+
+		RETURN_ERROR(chip_i2c_xfer_with_notify(port, addr_flags, NULL,
+						       0, in + offset,
+						       chunk_size, in_flags));
+		offset += chunk_size;
+	}
+	return EC_SUCCESS;
+}
+#endif /* CONFIG_I2C_XFER_LARGE_TRANSFER */
+
+int i2c_xfer_unlocked(const int port, const uint16_t addr_flags,
+		      const uint8_t *out, int out_size, uint8_t *in,
+		      int in_size, int flags)
+{
+	int i;
+	int ret = EC_SUCCESS;
+	uint16_t no_pec_af = addr_flags & ~I2C_FLAG_PEC;
+
+	if (!i2c_port_is_locked(port)) {
+		CPUTS("Access I2C without lock!");
+		return EC_ERROR_INVAL;
+	}
+
+	for (i = 0; i <= CONFIG_I2C_NACK_RETRY_COUNT; i++) {
+#ifdef CONFIG_ZEPHYR
+		struct i2c_msg msg[2];
+		int num_msgs = 0;
+
+		/* Be careful to respect the flags passed in */
+		if (out_size) {
+			unsigned int wflags = I2C_MSG_WRITE;
+
+			msg[num_msgs].buf = (uint8_t *)out;
+			msg[num_msgs].len = out_size;
+
+			/* If this is the last write, add a stop */
+			if (!in_size && (flags & I2C_XFER_STOP))
+				wflags |= I2C_MSG_STOP;
+			msg[num_msgs].flags = wflags;
+			num_msgs++;
+		}
+		if (in_size) {
+			unsigned int rflags = I2C_MSG_READ;
+
+			msg[num_msgs].buf = (uint8_t *)in;
+			msg[num_msgs].len = in_size;
+			rflags = I2C_MSG_READ;
+
+			/* If a stop is requested, add it */
+			if (flags & I2C_XFER_STOP)
+				rflags |= I2C_MSG_STOP;
+
+			/*
+			 * If this read follows a write (above) then we need a
+			 * restart
+			 */
+			if (num_msgs)
+				rflags |= I2C_MSG_RESTART;
+			msg[num_msgs].flags = rflags;
+			num_msgs++;
+		}
+
+		/* Big endian flag is used in wrappers for this call */
+		if (no_pec_af & ~(I2C_ADDR_MASK | I2C_FLAG_BIG_ENDIAN |
+						I2C_FLAG_ADDR16_LITTLE_ENDIAN))
+			ccprintf("Ignoring flags from i2c addr_flags: %04x",
+				 no_pec_af);
+
+		ret = i2c_transfer(i2c_get_device_for_port(port), msg, num_msgs,
+				   I2C_STRIP_FLAGS(no_pec_af));
+
+		if (IS_ENABLED(CONFIG_I2C_DEBUG)) {
+			i2c_trace_notify(port, addr_flags, out, out_size, in,
+					 in_size, ret);
+		}
+
+		switch (ret) {
+		case 0:
+			return EC_SUCCESS;
+		case -EIO:
+			ret = EC_ERROR_INVAL;
+			continue;
+		default:
+			return EC_ERROR_UNKNOWN;
+		}
+#elif defined(CONFIG_I2C_XFER_LARGE_TRANSFER)
+		ret = i2c_xfer_no_retry(port, no_pec_af, out, out_size, in,
+					in_size, flags);
+#else
+		ret = chip_i2c_xfer_with_notify(port, no_pec_af, out, out_size,
+						in, in_size, flags);
+#endif /* CONFIG_I2C_XFER_LARGE_TRANSFER */
+		if (ret != EC_ERROR_BUSY)
+			break;
+	}
+	return ret;
+}
+
+int i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out,
+	     int out_size, uint8_t *in, int in_size)
+{
+	int rv;
+
+	i2c_lock(port, 1);
+	rv = i2c_xfer_unlocked(port, addr_flags, out, out_size, in, in_size,
+			       I2C_XFER_SINGLE);
+	i2c_lock(port, 0);
+
+	return rv;
+}
+
+void i2c_lock(int port, int lock)
+{
+#ifdef CONFIG_I2C_MULTI_PORT_CONTROLLER
+	/* Lock the controller, not the port */
+	port = i2c_port_to_controller(port);
+#endif
+	if (port < 0 || port >= ARRAY_SIZE(port_mutex))
+		return;
+
+	if (lock) {
+		uint32_t irq_lock_key;
+
+		mutex_lock(port_mutex + port);
+
+		/* Disable interrupt during changing counter for preemption. */
+		irq_lock_key = irq_lock();
+
+		i2c_port_active_list |= BIT(port);
+		/* EC cannot enter sleep if there's any i2c port active. */
+		disable_sleep(SLEEP_MASK_I2C_CONTROLLER);
+
+		irq_unlock(irq_lock_key);
+	} else {
+		uint32_t irq_lock_key = irq_lock();
+
+		i2c_port_active_list &= ~BIT(port);
+		/* Once there is no i2c port active, enable sleep bit of i2c. */
+		if (!i2c_port_active_list)
+			enable_sleep(SLEEP_MASK_I2C_CONTROLLER);
+
+		irq_unlock(irq_lock_key);
+
+		mutex_unlock(port_mutex + port);
+	}
+}
+
+void i2c_prepare_sysjump(void)
+{
+	int i;
+
+	/* Lock all i2c controllers */
+	for (i = 0; i < ARRAY_SIZE(port_mutex); ++i)
+		mutex_lock(port_mutex + i);
+}
+
+/* i2c_readN with optional error checking */
+static int platform_ec_i2c_read(const int port, const uint16_t addr_flags,
+				uint8_t reg, uint8_t *in, int in_size)
+{
+	if (!IS_ENABLED(CONFIG_SMBUS_PEC) && I2C_USE_PEC(addr_flags))
+		return EC_ERROR_UNIMPLEMENTED;
+
+	if (IS_ENABLED(CONFIG_SMBUS_PEC) && I2C_USE_PEC(addr_flags)) {
+		int i, rv;
+		/* addr_8bit = 7 bit addr_flags + 1 bit r/w */
+		uint8_t addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1;
+		uint8_t out[3] = { addr_8bit, reg, addr_8bit | 1 };
+		uint8_t pec_local = 0, pec_remote;
+
+		i2c_lock(port, 1);
+		for (i = 0; i <= CONFIG_I2C_NACK_RETRY_COUNT; i++) {
+			rv = i2c_xfer_unlocked(port, addr_flags, &reg, 1, in,
+					       in_size, I2C_XFER_START);
+			if (rv)
+				continue;
+
+			rv = i2c_xfer_unlocked(port, addr_flags, NULL, 0,
+					       &pec_remote, 1, I2C_XFER_STOP);
+			if (rv)
+				continue;
+
+			pec_local = cros_crc8(out, ARRAY_SIZE(out));
+			pec_local = cros_crc8_arg(in, in_size, pec_local);
+			if (pec_local == pec_remote)
+				break;
+
+			rv = EC_ERROR_CRC;
+		}
+		i2c_lock(port, 0);
+
+		return rv;
+	}
+
+	return i2c_xfer(port, addr_flags, &reg, 1, in, in_size);
+}
+
+/* i2c_writeN with optional error checking */
+static int platform_ec_i2c_write(const int port, const uint16_t addr_flags,
+				 const uint8_t *out, int out_size)
+{
+	if (!IS_ENABLED(CONFIG_SMBUS_PEC) && I2C_USE_PEC(addr_flags))
+		return EC_ERROR_UNIMPLEMENTED;
+
+	if (IS_ENABLED(CONFIG_SMBUS_PEC) && I2C_USE_PEC(addr_flags)) {
+		int i, rv;
+		uint8_t addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1;
+		uint8_t pec;
+
+		pec = cros_crc8(&addr_8bit, 1);
+		pec = cros_crc8_arg(out, out_size, pec);
+
+		i2c_lock(port, 1);
+		for (i = 0; i <= CONFIG_I2C_NACK_RETRY_COUNT; i++) {
+			rv = i2c_xfer_unlocked(port, addr_flags, out, out_size,
+					       NULL, 0, I2C_XFER_START);
+			if (rv)
+				continue;
+
+			rv = i2c_xfer_unlocked(port, addr_flags, &pec, 1, NULL,
+					       0, I2C_XFER_STOP);
+			if (!rv)
+				break;
+		}
+		i2c_lock(port, 0);
+
+		return rv;
+	}
+
+	return i2c_xfer(port, addr_flags, out, out_size, NULL, 0);
+}
+
+int i2c_read32(const int port, const uint16_t addr_flags, int offset, int *data)
+{
+	int rv;
+	uint8_t reg, buf[sizeof(uint32_t)];
+
+	reg = offset & 0xff;
+	/* I2C read 32-bit word: transmit 8-bit offset, and read 32bits */
+	rv = platform_ec_i2c_read(port, addr_flags, reg, buf, sizeof(uint32_t));
+
+	if (rv)
+		return rv;
+
+	if (I2C_IS_BIG_ENDIAN(addr_flags))
+		*data = ((int)buf[0] << 24) | ((int)buf[1] << 16) |
+			((int)buf[2] << 8) | buf[3];
+	else
+		*data = ((int)buf[3] << 24) | ((int)buf[2] << 16) |
+			((int)buf[1] << 8) | buf[0];
+
+	return EC_SUCCESS;
+}
+
+int i2c_write32(const int port, const uint16_t addr_flags, int offset, int data)
+{
+	uint8_t buf[1 + sizeof(uint32_t)];
+
+	buf[0] = offset & 0xff;
+
+	if (I2C_IS_BIG_ENDIAN(addr_flags)) {
+		buf[1] = (data >> 24) & 0xff;
+		buf[2] = (data >> 16) & 0xff;
+		buf[3] = (data >> 8) & 0xff;
+		buf[4] = data & 0xff;
+	} else {
+		buf[1] = data & 0xff;
+		buf[2] = (data >> 8) & 0xff;
+		buf[3] = (data >> 16) & 0xff;
+		buf[4] = (data >> 24) & 0xff;
+	}
+
+	return platform_ec_i2c_write(port, addr_flags, buf,
+				     sizeof(uint32_t) + 1);
+}
+
+int i2c_read16(const int port, const uint16_t addr_flags, int offset, int *data)
+{
+	int rv;
+	uint8_t reg, buf[sizeof(uint16_t)];
+
+	reg = offset & 0xff;
+	/* I2C read 16-bit word: transmit 8-bit offset, and read 16bits */
+	rv = platform_ec_i2c_read(port, addr_flags, reg, buf, sizeof(uint16_t));
+
+	if (rv)
+		return rv;
+
+	if (I2C_IS_BIG_ENDIAN(addr_flags))
+		*data = ((int)buf[0] << 8) | buf[1];
+	else
+		*data = ((int)buf[1] << 8) | buf[0];
+
+	return EC_SUCCESS;
+}
+
+int i2c_write16(const int port, const uint16_t addr_flags, int offset, int data)
+{
+	uint8_t buf[1 + sizeof(uint16_t)];
+
+	buf[0] = offset & 0xff;
+
+	if (I2C_IS_BIG_ENDIAN(addr_flags)) {
+		buf[1] = (data >> 8) & 0xff;
+		buf[2] = data & 0xff;
+	} else {
+		buf[1] = data & 0xff;
+		buf[2] = (data >> 8) & 0xff;
+	}
+
+	return platform_ec_i2c_write(port, addr_flags, buf,
+				     1 + sizeof(uint16_t));
+}
+
+int i2c_read8(const int port, const uint16_t addr_flags, int offset, int *data)
+{
+	int rv;
+	uint8_t reg = offset;
+	uint8_t buf;
+
+	reg = offset;
+
+	rv = platform_ec_i2c_read(port, addr_flags, reg, &buf, sizeof(uint8_t));
+	if (!rv)
+		*data = buf;
+
+	return rv;
+}
+
+int i2c_write8(const int port, const uint16_t addr_flags, int offset, int data)
+{
+	uint8_t buf[2];
+
+	buf[0] = offset;
+	buf[1] = data;
+
+	return platform_ec_i2c_write(port, addr_flags, buf, sizeof(buf));
+}
+
+int i2c_update8(const int port, const uint16_t addr_flags, const int offset,
+		const uint8_t mask, const enum mask_update_action action)
+{
+	int rv;
+	int read_val;
+	int write_val;
+
+	rv = i2c_read8(port, addr_flags, offset, &read_val);
+	if (rv)
+		return rv;
+
+	write_val = (action == MASK_SET) ? (read_val | mask) :
+					   (read_val & ~mask);
+
+	if (IS_ENABLED(CONFIG_I2C_UPDATE_IF_CHANGED) && write_val == read_val)
+		return EC_SUCCESS;
+
+	return i2c_write8(port, addr_flags, offset, write_val);
+}
+
+int i2c_update16(const int port, const uint16_t addr_flags, const int offset,
+		 const uint16_t mask, const enum mask_update_action action)
+{
+	int rv;
+	int read_val;
+	int write_val;
+
+	rv = i2c_read16(port, addr_flags, offset, &read_val);
+	if (rv)
+		return rv;
+
+	write_val = (action == MASK_SET) ? (read_val | mask) :
+					   (read_val & ~mask);
+
+	if (IS_ENABLED(CONFIG_I2C_UPDATE_IF_CHANGED) && write_val == read_val)
+		return EC_SUCCESS;
+
+	return i2c_write16(port, addr_flags, offset, write_val);
+}
+
+int i2c_field_update8(const int port, const uint16_t addr_flags,
+		      const int offset, const uint8_t field_mask,
+		      const uint8_t set_value)
+{
+	int rv;
+	int read_val;
+	int write_val;
+
+	rv = i2c_read8(port, addr_flags, offset, &read_val);
+	if (rv)
+		return rv;
+
+	write_val = (read_val & (~field_mask)) | set_value;
+
+	if (IS_ENABLED(CONFIG_I2C_UPDATE_IF_CHANGED) && write_val == read_val)
+		return EC_SUCCESS;
+
+	return i2c_write8(port, addr_flags, offset, write_val);
+}
+
+int i2c_field_update16(const int port, const uint16_t addr_flags,
+		       const int offset, const uint16_t field_mask,
+		       const uint16_t set_value)
+{
+	int rv;
+	int read_val;
+	int write_val;
+
+	rv = i2c_read16(port, addr_flags, offset, &read_val);
+	if (rv)
+		return rv;
+
+	write_val = (read_val & (~field_mask)) | set_value;
+
+	if (IS_ENABLED(CONFIG_I2C_UPDATE_IF_CHANGED) && write_val == read_val)
+		return EC_SUCCESS;
+
+	return i2c_write16(port, addr_flags, offset, write_val);
+}
+
+int i2c_read_offset16(const int port, const uint16_t addr_flags,
+		      uint16_t offset, int *data, int len)
+{
+	int rv;
+	uint8_t buf[sizeof(uint16_t)], addr[sizeof(uint16_t)];
+
+	if (len < 0 || len > 2)
+		return EC_ERROR_INVAL;
+
+	if (I2C_IS_ADDR16_LITTLE_ENDIAN(addr_flags)) {
+		addr[0] = offset & 0xff;
+		addr[1] = (offset >> 8) & 0xff;
+	} else {
+		addr[0] = (offset >> 8) & 0xff;
+		addr[1] = offset & 0xff;
+	}
+
+	/* I2C read 16-bit word: transmit 16-bit offset, and read buffer */
+	rv = i2c_xfer(port, addr_flags, addr, 2, buf, len);
+
+	if (rv)
+		return rv;
+
+	if (len == 1) {
+		*data = buf[0];
+	} else {
+		if (I2C_IS_BIG_ENDIAN(addr_flags))
+			*data = ((int)buf[0] << 8) | buf[1];
+		else
+			*data = ((int)buf[1] << 8) | buf[0];
+	}
+
+	return EC_SUCCESS;
+}
+
+int i2c_write_offset16(const int port, const uint16_t addr_flags,
+		       uint16_t offset, int data, int len)
+{
+	uint8_t buf[2 + sizeof(uint16_t)];
+
+	if (len < 0 || len > 2)
+		return EC_ERROR_INVAL;
+
+	if (I2C_IS_ADDR16_LITTLE_ENDIAN(addr_flags)) {
+		buf[0] = offset & 0xff;
+		buf[1] = (offset >> 8) & 0xff;
+	} else {
+		buf[0] = (offset >> 8) & 0xff;
+		buf[1] = offset & 0xff;
+	}
+
+	if (len == 1) {
+		buf[2] = data & 0xff;
+	} else {
+		if (I2C_IS_BIG_ENDIAN(addr_flags)) {
+			buf[2] = (data >> 8) & 0xff;
+			buf[3] = data & 0xff;
+		} else {
+			buf[2] = data & 0xff;
+			buf[3] = (data >> 8) & 0xff;
+		}
+	}
+
+	return i2c_xfer(port, addr_flags, buf, 2 + len, NULL, 0);
+}
+
+int i2c_read_offset16_block(const int port, const uint16_t addr_flags,
+			    uint16_t offset, uint8_t *data, int len)
+{
+	uint8_t addr[sizeof(uint16_t)];
+
+	if (I2C_IS_ADDR16_LITTLE_ENDIAN(addr_flags)) {
+		addr[0] = offset & 0xff;
+		addr[1] = (offset >> 8) & 0xff;
+	} else {
+		addr[0] = (offset >> 8) & 0xff;
+		addr[1] = offset & 0xff;
+	}
+
+	return i2c_xfer(port, addr_flags, addr, 2, data, len);
+}
+
+int i2c_write_offset16_block(const int port, const uint16_t addr_flags,
+			     uint16_t offset, const uint8_t *data, int len)
+{
+	int rv;
+	uint8_t addr[sizeof(uint16_t)];
+
+	if (I2C_IS_ADDR16_LITTLE_ENDIAN(addr_flags)) {
+		addr[0] = offset & 0xff;
+		addr[1] = (offset >> 8) & 0xff;
+	} else {
+		addr[0] = (offset >> 8) & 0xff;
+		addr[1] = offset & 0xff;
+	}
+
+	/*
+	 * Split into two transactions to avoid the stack space consumption of
+	 * appending the destination address with the data array.
+	 */
+	i2c_lock(port, 1);
+	rv = i2c_xfer_unlocked(port, addr_flags, addr, 2, NULL, 0,
+			       I2C_XFER_START);
+	if (!rv)
+		rv = i2c_xfer_unlocked(port, addr_flags, data, len, NULL, 0,
+				       I2C_XFER_STOP);
+	i2c_lock(port, 0);
+
+	return rv;
+}
+
+int i2c_read_sized_block(const int port, const uint16_t addr_flags, int offset,
+			 uint8_t *data, int max_len, int *read_len)
+{
+	int i, rv;
+	uint8_t reg, block_length;
+
+	if (max_len == 0)
+		return EC_ERROR_INVAL;
+
+	if (!IS_ENABLED(CONFIG_SMBUS_PEC) && I2C_USE_PEC(addr_flags))
+		return EC_ERROR_UNIMPLEMENTED;
+
+	reg = offset;
+	i2c_lock(port, 1);
+
+	for (i = 0; i <= CONFIG_I2C_NACK_RETRY_COUNT; i++) {
+		int data_length = 0;
+
+		/*
+		 * Send device reg space offset, and read back block length.
+		 * Keep this session open without a stop.
+		 */
+		rv = i2c_xfer_unlocked(port, addr_flags, &reg, 1, &block_length,
+				       1, I2C_XFER_START);
+		if (rv)
+			continue;
+
+		if (block_length > max_len)
+			data_length = max_len;
+		else
+			data_length = block_length;
+
+		if (IS_ENABLED(CONFIG_SMBUS_PEC) && I2C_USE_PEC(addr_flags)) {
+			uint8_t addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1;
+			uint8_t out[3] = { addr_8bit, reg, addr_8bit | 1 };
+			uint8_t pec, pec_remote;
+
+			rv = i2c_xfer_unlocked(port, addr_flags, 0, 0, data,
+					       data_length, 0);
+			if (rv)
+				continue;
+
+			pec = cros_crc8(out, sizeof(out));
+			pec = cros_crc8_arg(&block_length, 1, pec);
+			pec = cros_crc8_arg(data, data_length, pec);
+
+			/* read all remaining bytes */
+			block_length -= data_length;
+			while (block_length) {
+				uint8_t byte;
+
+				rv = i2c_xfer_unlocked(port, addr_flags, NULL,
+						       0, &byte, 1, 0);
+				if (rv)
+					break;
+				pec = cros_crc8_arg(&byte, 1, pec);
+				--block_length;
+			}
+			if (rv)
+				continue;
+
+			rv = i2c_xfer_unlocked(port, addr_flags, NULL, 0,
+					       &pec_remote, 1, I2C_XFER_STOP);
+			if (rv)
+				continue;
+
+			if (pec != pec_remote)
+				rv = EC_ERROR_CRC;
+		} else {
+			rv = i2c_xfer_unlocked(port, addr_flags, 0, 0, data,
+					       data_length, I2C_XFER_STOP);
+			if (rv)
+				continue;
+		}
+
+		/* execution reaches here implies rv=0, so we can exit now */
+		*read_len = data_length;
+		break;
+	}
+
+	i2c_lock(port, 0);
+	return rv;
+}
+
+int i2c_read_string(const int port, const uint16_t addr_flags, int offset,
+		    uint8_t *data, int len)
+{
+	int read_len = 0;
+	int rv = 0;
+
+	if (len == 0)
+		return EC_ERROR_INVAL;
+
+	rv = i2c_read_sized_block(port, addr_flags, offset, data, len - 1,
+				  &read_len);
+	data[read_len] = 0;
+	return rv;
+}
+
+int i2c_read_block(const int port, const uint16_t addr_flags, int offset,
+		   uint8_t *data, int len)
+{
+	int rv;
+	uint8_t reg_address = offset;
+
+	rv = i2c_xfer(port, addr_flags, &reg_address, 1, data, len);
+	return rv;
+}
+
+int i2c_write_block(const int port, const uint16_t addr_flags, int offset,
+		    const uint8_t *data, int len)
+{
+	int i, rv;
+	uint8_t reg_address = offset, pec = 0;
+
+	if (!IS_ENABLED(CONFIG_SMBUS_PEC) && I2C_USE_PEC(addr_flags))
+		return EC_ERROR_UNIMPLEMENTED;
+
+	if (IS_ENABLED(CONFIG_SMBUS_PEC) && I2C_USE_PEC(addr_flags)) {
+		uint8_t addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1;
+
+		pec = cros_crc8(&addr_8bit, sizeof(uint8_t));
+		pec = cros_crc8_arg(&reg_address, sizeof(uint8_t), pec);
+		pec = cros_crc8_arg(data, len, pec);
+	}
+
+	/*
+	 * Split into two transactions to avoid the stack space consumption of
+	 * appending the destination address with the data array.
+	 */
+	i2c_lock(port, 1);
+	for (i = 0; i <= CONFIG_I2C_NACK_RETRY_COUNT; i++) {
+		rv = i2c_xfer_unlocked(port, addr_flags, &reg_address, 1, NULL,
+				       0, I2C_XFER_START);
+		if (rv)
+			continue;
+
+		if (IS_ENABLED(CONFIG_SMBUS_PEC) && I2C_USE_PEC(addr_flags)) {
+			rv = i2c_xfer_unlocked(port, addr_flags, data, len,
+					       NULL, 0, 0);
+			if (rv)
+				continue;
+
+			rv = i2c_xfer_unlocked(port, addr_flags, &pec,
+					       sizeof(uint8_t), NULL, 0,
+					       I2C_XFER_STOP);
+			if (rv)
+				continue;
+		} else {
+			rv = i2c_xfer_unlocked(port, addr_flags, data, len,
+					       NULL, 0, I2C_XFER_STOP);
+			if (rv)
+				continue;
+		}
+
+		/* execution reaches here implies rv=0, so we can exit now */
+		break;
+	}
+	i2c_lock(port, 0);
+
+	return rv;
+}
+
+int i2c_freq_to_khz(enum i2c_freq freq)
+{
+	switch (freq) {
+	case I2C_FREQ_100KHZ:
+		return 100;
+	case I2C_FREQ_400KHZ:
+		return 400;
+	case I2C_FREQ_1000KHZ:
+		return 1000;
+	default:
+		return 0;
+	}
+}
+
+enum i2c_freq i2c_khz_to_freq(int speed_khz)
+{
+	switch (speed_khz) {
+	case 100:
+		return I2C_FREQ_100KHZ;
+	case 400:
+		return I2C_FREQ_400KHZ;
+	case 1000:
+		return I2C_FREQ_1000KHZ;
+	default:
+		return I2C_FREQ_COUNT;
+	}
+}
+
+int i2c_set_freq(int port, enum i2c_freq freq)
+{
+	int ret;
+	const struct i2c_port_t *cfg;
+
+	cfg = get_i2c_port(port);
+	if (cfg == NULL)
+		return EC_ERROR_INVAL;
+
+	if (!(cfg->flags & I2C_PORT_FLAG_DYNAMIC_SPEED))
+		return EC_ERROR_UNIMPLEMENTED;
+
+	i2c_lock(port, 1);
+	ret = chip_i2c_set_freq(port, freq);
+	i2c_lock(port, 0);
+	return ret;
+}
+
+enum i2c_freq i2c_get_freq(int port)
+{
+	return chip_i2c_get_freq(port);
+}
+
+/*****************************************************************************/
+/* Host commands */
+
+#ifdef CONFIG_I2C_DEBUG_PASSTHRU
+#define PTHRUPRINTS(format, args...) CPRINTS("I2C_PTHRU " format, ##args)
+#define PTHRUPRINTF(format, args...) CPRINTF(format, ##args)
+#else
+#define PTHRUPRINTS(format, args...)
+#define PTHRUPRINTF(format, args...)
+#endif
+
+/**
+ * Perform the voluminous checking required for this message
+ *
+ * @param args	Arguments
+ * @return 0 if OK, EC_RES_INVALID_PARAM on error
+ */
+static int check_i2c_params(const struct host_cmd_handler_args *args)
+{
+	const struct ec_params_i2c_passthru *params = args->params;
+	const struct ec_params_i2c_passthru_msg *msg;
+	int read_len = 0, write_len = 0;
+	unsigned int size;
+	int msgnum;
+
+#ifdef CONFIG_I2C_PASSTHRU_RESTRICTED
+	uint8_t cmd_id = 0xff;
+	const uint8_t *out;
+#endif
+
+	if (args->params_size < sizeof(*params)) {
+		PTHRUPRINTS("no params, params_size=%d, need at least %d",
+			    args->params_size, sizeof(*params));
+		return EC_RES_INVALID_PARAM;
+	}
+	size = sizeof(*params) + params->num_msgs * sizeof(*msg);
+	if (args->params_size < size) {
+		PTHRUPRINTS("params_size=%d, need at least %d",
+			    args->params_size, size);
+		return EC_RES_INVALID_PARAM;
+	}
+
+#ifdef CONFIG_I2C_PASSTHRU_RESTRICTED
+	out = (uint8_t *)args->params + size;
+#endif
+
+	/* Loop and process messages */;
+	for (msgnum = 0, msg = params->msg; msgnum < params->num_msgs;
+	     msgnum++, msg++) {
+		unsigned int addr_flags = msg->addr_flags;
+
+		PTHRUPRINTS("port=%d, %s, addr=0x%x(7-bit), len=%d",
+			    params->port,
+			    addr_flags & EC_I2C_FLAG_READ ? "read" : "write",
+			    addr_flags & EC_I2C_ADDR_MASK, msg->len);
+
+		if (addr_flags & EC_I2C_FLAG_READ) {
+			read_len += msg->len;
+		} else {
+#ifdef CONFIG_I2C_PASSTHRU_RESTRICTED
+			cmd_id = out[write_len];
+#endif
+			write_len += msg->len;
+		}
+#ifdef CONFIG_I2C_PASSTHRU_RESTRICTED
+		if (system_is_locked()) {
+			const struct i2c_cmd_desc_t cmd_desc = {
+				.port = params->port,
+				.addr_flags = addr_flags,
+				.cmd = cmd_id,
+			};
+			if (!board_allow_i2c_passthru(&cmd_desc))
+				return EC_RES_ACCESS_DENIED;
+		}
+#endif
+	}
+
+	/* Check there is room for the data */
+	if (args->response_max <
+	    sizeof(struct ec_response_i2c_passthru) + read_len) {
+		PTHRUPRINTS("overflow1");
+		return EC_RES_INVALID_PARAM;
+	}
+
+	/* Must have bytes to write */
+	if (args->params_size < size + write_len) {
+		PTHRUPRINTS("overflow2");
+		return EC_RES_INVALID_PARAM;
+	}
+
+	return EC_RES_SUCCESS;
+}
+
+#ifdef CONFIG_I2C_VIRTUAL_BATTERY
+static inline int is_i2c_port_virtual_battery(int port)
+{
+#ifdef CONFIG_ZEPHYR
+	/* For Zephyr compare the actual device, which will be used in
+	 * i2c_transfer function.
+	 */
+	return (i2c_get_device_for_port(port) ==
+		i2c_get_device_for_port(I2C_PORT_VIRTUAL_BATTERY));
+#else
+	return (port == I2C_PORT_VIRTUAL_BATTERY);
+#endif
+}
+#endif /* CONFIG_I2C_VIRTUAL_BATTERY */
+
+static enum ec_status i2c_command_passthru(struct host_cmd_handler_args *args)
+{
+#ifdef CONFIG_ZEPHYR
+	/* For Zephyr, convert the received remote port number to a port number
+	 * used in EC.
+	 */
+	((struct ec_params_i2c_passthru *)(args->params))->port =
+		i2c_get_port_from_remote_port(
+			((struct ec_params_i2c_passthru *)(args->params))->port);
+#endif
+	const struct ec_params_i2c_passthru *params = args->params;
+	const struct ec_params_i2c_passthru_msg *msg;
+	struct ec_response_i2c_passthru *resp = args->response;
+	const struct i2c_port_t *i2c_port;
+	const uint8_t *out;
+	int in_len;
+	int ret, i;
+	int port_is_locked = 0;
+
+#ifdef CONFIG_BATTERY_CUT_OFF
+	/*
+	 * Some batteries would wake up after cut-off if we talk to it.
+	 */
+	if (battery_is_cut_off())
+		return EC_RES_ACCESS_DENIED;
+#endif
+
+	i2c_port = get_i2c_port(params->port);
+	if (!i2c_port)
+		return EC_RES_INVALID_PARAM;
+
+	ret = check_i2c_params(args);
+	if (ret)
+		return ret;
+
+	if (port_protected[params->port]) {
+		if (!i2c_port->passthru_allowed)
+			return EC_RES_ACCESS_DENIED;
+
+		for (i = 0; i < params->num_msgs; i++) {
+			if (!i2c_port->passthru_allowed(
+				    i2c_port, params->msg[i].addr_flags))
+				return EC_RES_ACCESS_DENIED;
+		}
+	}
+
+	/* Loop and process messages */
+	resp->i2c_status = 0;
+	out = (uint8_t *)args->params + sizeof(*params) +
+	      params->num_msgs * sizeof(*msg);
+	in_len = 0;
+
+	for (resp->num_msgs = 0, msg = params->msg;
+	     resp->num_msgs < params->num_msgs; resp->num_msgs++, msg++) {
+		int xferflags = I2C_XFER_START;
+		int read_len = 0, write_len = 0;
+		int rv = 1;
+
+		/* Have to remove the EC flags from the address flags */
+		uint16_t addr_flags = msg->addr_flags & EC_I2C_ADDR_MASK;
+
+		if (msg->addr_flags & EC_I2C_FLAG_READ)
+			read_len = msg->len;
+		else
+			write_len = msg->len;
+
+		/* Set stop bit for last message */
+		if (resp->num_msgs == params->num_msgs - 1)
+			xferflags |= I2C_XFER_STOP;
+
+#ifdef CONFIG_I2C_VIRTUAL_BATTERY
+		if (is_i2c_port_virtual_battery(params->port) &&
+		    addr_flags == VIRTUAL_BATTERY_ADDR_FLAGS) {
+			if (virtual_battery_handler(resp, in_len, &rv,
+						    xferflags, read_len,
+						    write_len, out))
+				break;
+		}
+#endif
+		/* Transfer next message */
+		PTHRUPRINTS("xfer port=%x addr=0x%x rlen=%d flags=0x%x",
+			    params->port, addr_flags, read_len, xferflags);
+		if (write_len) {
+			PTHRUPRINTF("  out:");
+			for (i = 0; i < write_len; i++)
+				PTHRUPRINTF(" 0x%02x", out[i]);
+			PTHRUPRINTF("\n");
+		}
+		if (rv) {
+			if (!port_is_locked)
+				i2c_lock(params->port, (port_is_locked = 1));
+			rv = i2c_xfer_unlocked(params->port, addr_flags, out,
+					       write_len, &resp->data[in_len],
+					       read_len, xferflags);
+		}
+
+		if (rv) {
+			/* Driver will have sent a stop bit here */
+			if (rv == EC_ERROR_TIMEOUT)
+				resp->i2c_status = EC_I2C_STATUS_TIMEOUT;
+			else
+				resp->i2c_status = EC_I2C_STATUS_NAK;
+			break;
+		}
+
+		in_len += read_len;
+		out += write_len;
+	}
+	args->response_size = sizeof(*resp) + in_len;
+
+	/* Unlock port */
+	if (port_is_locked)
+		i2c_lock(params->port, 0);
+
+	/*
+	 * Return success even if transfer failed so response is sent.  Host
+	 * will check message status to determine the transfer result.
+	 */
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_I2C_PASSTHRU, i2c_command_passthru, EC_VER_MASK(0));
+
+__test_only void i2c_passthru_protect_reset(void)
+{
+	memset(port_protected, 0, sizeof(port_protected));
+}
+
+static void i2c_passthru_protect_port(uint32_t port)
+{
+	if (port < ARRAY_SIZE(port_protected))
+		port_protected[port] = 1;
+	else
+		PTHRUPRINTS("Invalid I2C port %d to be protected\n", port);
+}
+
+static void i2c_passthru_protect_tcpc_ports(void)
+{
+#ifdef CONFIG_USB_PD_PORT_MAX_COUNT
+	int i;
+
+	/*
+	 * If WP is not enabled i.e. system is not locked leave the tunnels open
+	 * so that factory line can do updates without a new RO BIOS.
+	 */
+	if (!system_is_locked()) {
+		CPRINTS("System unlocked, TCPC I2C tunnels may be unprotected");
+		return;
+	}
+
+	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+		/* TCPC tunnel not configured. No need to protect anything */
+		if (!I2C_STRIP_FLAGS(tcpc_config[i].i2c_info.addr_flags))
+			continue;
+		i2c_passthru_protect_port(tcpc_config[i].i2c_info.port);
+	}
+#endif
+}
+
+static enum ec_status
+i2c_command_passthru_protect(struct host_cmd_handler_args *args)
+{
+#ifdef CONFIG_ZEPHYR
+	/* For Zephyr, convert the received remote port number to a port number
+	 * used in EC.
+	 */
+	((struct ec_params_i2c_passthru_protect *)(args->params))
+		->port = i2c_get_port_from_remote_port(
+		((struct ec_params_i2c_passthru_protect *)(args->params))->port);
+#endif
+	const struct ec_params_i2c_passthru_protect *params = args->params;
+	struct ec_response_i2c_passthru_protect *resp = args->response;
+
+	if (args->params_size < sizeof(*params)) {
+		PTHRUPRINTS("protect no params, params_size=%d, ",
+			    args->params_size);
+		return EC_RES_INVALID_PARAM;
+	}
+
+	/*
+	 * When calling the subcmd to protect all tcpcs, the i2c port isn't
+	 * expected to be set in the args. So, putting a check here to avoid
+	 * the get_i2c_port return error.
+	 */
+	if (params->subcmd == EC_CMD_I2C_PASSTHRU_PROTECT_ENABLE_TCPCS) {
+		if (IS_ENABLED(CONFIG_USB_POWER_DELIVERY) &&
+		    !IS_ENABLED(CONFIG_USB_PD_TCPM_STUB))
+			i2c_passthru_protect_tcpc_ports();
+		return EC_RES_SUCCESS;
+	}
+
+	if (!get_i2c_port(params->port)) {
+		PTHRUPRINTS("protect invalid port %d", params->port);
+		return EC_RES_INVALID_PARAM;
+	}
+
+	if (params->subcmd == EC_CMD_I2C_PASSTHRU_PROTECT_STATUS) {
+		if (args->response_max < sizeof(*resp)) {
+			PTHRUPRINTS("protect no response, "
+				    "response_max=%d, need at least %d",
+				    args->response_max, sizeof(*resp));
+			return EC_RES_INVALID_PARAM;
+		}
+
+		resp->status = port_protected[params->port];
+		args->response_size = sizeof(*resp);
+	} else if (params->subcmd == EC_CMD_I2C_PASSTHRU_PROTECT_ENABLE) {
+		i2c_passthru_protect_port(params->port);
+	} else {
+		return EC_RES_INVALID_COMMAND;
+	}
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_I2C_PASSTHRU_PROTECT, i2c_command_passthru_protect,
+		     EC_VER_MASK(0));
+
+#ifdef CONFIG_HOSTCMD_I2C_CONTROL
+
+static enum ec_status i2c_command_control(struct host_cmd_handler_args *args)
+{
+#ifdef CONFIG_ZEPHYR
+	/* For Zephyr, convert the received remote port number to a port number
+	 * used in EC.
+	 */
+	((struct ec_params_i2c_control *)(args->params))->port =
+		i2c_get_port_from_remote_port(
+			((struct ec_params_i2c_control *)(args->params))->port);
+#endif
+	const struct ec_params_i2c_control *params = args->params;
+	struct ec_response_i2c_control *resp = args->response;
+	enum i2c_freq old_i2c_freq;
+	enum i2c_freq new_i2c_freq;
+	const struct i2c_port_t *cfg;
+	uint16_t old_i2c_speed_khz;
+	uint16_t new_i2c_speed_khz;
+	enum ec_error_list rv;
+	int khz;
+
+	cfg = get_i2c_port(params->port);
+	if (!cfg)
+		return EC_RES_INVALID_PARAM;
+
+	switch (params->cmd) {
+	case EC_I2C_CONTROL_GET_SPEED:
+		old_i2c_freq = i2c_get_freq(cfg->port);
+		khz = i2c_freq_to_khz(old_i2c_freq);
+		old_i2c_speed_khz = (khz != 0) ? khz :
+						 EC_I2C_CONTROL_SPEED_UNKNOWN;
+		break;
+
+	case EC_I2C_CONTROL_SET_SPEED:
+		new_i2c_speed_khz = params->cmd_params.speed_khz;
+		new_i2c_freq = i2c_khz_to_freq(new_i2c_speed_khz);
+		if (new_i2c_freq == I2C_FREQ_COUNT)
+			return EC_RES_INVALID_PARAM;
+
+		old_i2c_freq = i2c_get_freq(cfg->port);
+		old_i2c_speed_khz = i2c_freq_to_khz(old_i2c_freq);
+
+		rv = i2c_set_freq(cfg->port, new_i2c_freq);
+		if (rv != EC_SUCCESS)
+			return EC_RES_ERROR;
+
+		CPRINTS("I2C%d speed changed from %d kHz to %d kHz",
+			params->port, old_i2c_speed_khz, new_i2c_speed_khz);
+		break;
+
+	default:
+		return EC_RES_INVALID_COMMAND;
+	}
+
+	resp->cmd_response.speed_khz = old_i2c_speed_khz;
+	args->response_size = sizeof(*resp);
+
+	return EC_RES_SUCCESS;
+}
+
+DECLARE_HOST_COMMAND(EC_CMD_I2C_CONTROL, i2c_command_control, EC_VER_MASK(0));
+
+#endif /* CONFIG_HOSTCMD_I2C_CONTROL */
+
+/*****************************************************************************/
+/* Console commands */
+
+#ifdef CONFIG_CMD_I2C_PROTECT
+static int command_i2cprotect(int argc, const char **argv)
+{
+	if (argc == 1) {
+		int i, port;
+
+		for (i = 0; i < i2c_ports_used; i++) {
+			port = i2c_ports[i].port;
+			ccprintf("Port %d: %s\n", port,
+				 port_protected[port] ? "Protected" :
+							"Unprotected");
+		}
+	} else if (argc == 2) {
+		int port;
+		char *e;
+
+		port = strtoi(argv[1], &e, 0);
+		if (*e)
+			return EC_ERROR_PARAM2;
+
+		if (!get_i2c_port(port)) {
+			ccprintf("i2c passthru protect invalid port %d\n",
+				 port);
+			return EC_RES_INVALID_PARAM;
+		}
+
+		port_protected[port] = 1;
+	} else {
+		return EC_ERROR_PARAM_COUNT;
+	}
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(i2cprotect, command_i2cprotect, "[port]",
+			"Protect I2C bus");
+#endif
+
+#ifdef CONFIG_CMD_I2C_STRESS_TEST
+static void i2c_test_status(struct i2c_test_results *i2c_test, int test_dev)
+{
+	ccprintf("test_dev=%2d, ", test_dev);
+	ccprintf("r=%5d, rs=%5d, rf=%5d, ",
+		 i2c_test->read_success + i2c_test->read_fail,
+		 i2c_test->read_success, i2c_test->read_fail);
+
+	ccprintf("w=%5d, ws=%5d, wf=%5d\n",
+		 i2c_test->write_success + i2c_test->write_fail,
+		 i2c_test->write_success, i2c_test->write_fail);
+
+	i2c_test->read_success = 0;
+	i2c_test->read_fail = 0;
+	i2c_test->write_success = 0, i2c_test->write_fail = 0;
+}
+
+#define I2C_STRESS_TEST_DATA_VERIFY_RETRY_COUNT 3
+static int command_i2ctest(int argc, const char **argv)
+{
+	char *e;
+	int i, j, rv;
+	uint32_t rand;
+	int data, data_verify;
+	int count = 10000;
+	int udelay = 100;
+	int test_dev = i2c_test_dev_used;
+	struct i2c_stress_test_dev *i2c_s_test = NULL;
+	struct i2c_test_reg_info *reg_s_info;
+	struct i2c_test_results *test_s_results;
+
+	if (argc > 1) {
+		count = strtoi(argv[1], &e, 0);
+		if (*e)
+			return EC_ERROR_PARAM2;
+	}
+
+	if (argc > 2) {
+		udelay = strtoi(argv[2], &e, 0);
+		if (*e)
+			return EC_ERROR_PARAM3;
+	}
+
+	if (argc > 3) {
+		test_dev = strtoi(argv[3], &e, 0);
+		if (*e || test_dev < 1 || test_dev > i2c_test_dev_used)
+			return EC_ERROR_PARAM4;
+		test_dev--;
+	}
+
+	for (i = 0; i < count; i++) {
+		int port;
+		uint16_t addr_flags;
+
+		if (!(i % 1000))
+			ccprintf("running test %d\n", i);
+
+		if (argc < 4) {
+			rand = get_time().val;
+			test_dev = rand % i2c_test_dev_used;
+		}
+
+		port = i2c_stress_tests[test_dev].port;
+		addr_flags = i2c_stress_tests[test_dev].addr_flags;
+		i2c_s_test = i2c_stress_tests[test_dev].i2c_test;
+		reg_s_info = &i2c_s_test->reg_info;
+		test_s_results = &i2c_s_test->test_results;
+
+		rand = get_time().val;
+		if (rand & 0x1) {
+			/* read */
+			rv = i2c_s_test->i2c_read ?
+				     i2c_s_test->i2c_read(port, addr_flags,
+							  reg_s_info->read_reg,
+							  &data) :
+				     i2c_s_test->i2c_read_dev(
+					     reg_s_info->read_reg, &data);
+			if (rv || data != reg_s_info->read_val)
+				test_s_results->read_fail++;
+			else
+				test_s_results->read_success++;
+		} else {
+			/*
+			 * Reads are more than writes in the system.
+			 * Read and then write same value to ensure we are
+			 * not changing any settings.
+			 */
+
+			/* Read the write register */
+			rv = i2c_s_test->i2c_read ?
+				     i2c_s_test->i2c_read(port, addr_flags,
+							  reg_s_info->read_reg,
+							  &data) :
+				     i2c_s_test->i2c_read_dev(
+					     reg_s_info->read_reg, &data);
+			if (rv) {
+				/* Skip writing invalid data */
+				test_s_results->read_fail++;
+				continue;
+			} else
+				test_s_results->read_success++;
+
+			j = I2C_STRESS_TEST_DATA_VERIFY_RETRY_COUNT;
+			do {
+				/* Write same value back */
+				rv = i2c_s_test->i2c_write ?
+					     i2c_s_test->i2c_write(
+						     port, addr_flags,
+						     reg_s_info->write_reg,
+						     data) :
+					     i2c_s_test->i2c_write_dev(
+						     reg_s_info->write_reg,
+						     data);
+				i++;
+				if (rv) {
+					/* Skip reading as write failed */
+					test_s_results->write_fail++;
+					break;
+				}
+				test_s_results->write_success++;
+
+				/* Read back to verify the data */
+				rv = i2c_s_test->i2c_read ?
+					     i2c_s_test->i2c_read(
+						     port, addr_flags,
+						     reg_s_info->read_reg,
+						     &data_verify) :
+					     i2c_s_test->i2c_read_dev(
+						     reg_s_info->read_reg,
+						     &data_verify);
+				i++;
+				if (rv) {
+					/* Read failed try next time */
+					test_s_results->read_fail++;
+					break;
+				} else if (!rv && data != data_verify) {
+					/* Either data writes/read is wrong */
+					j--;
+				} else {
+					j = 0;
+					test_s_results->read_success++;
+				}
+			} while (j);
+		}
+
+		usleep(udelay);
+	}
+
+	ccprintf("\n**********final result **********\n");
+
+	cflush();
+	if (argc > 3) {
+		i2c_test_status(&i2c_s_test->test_results, test_dev + 1);
+	} else {
+		for (i = 0; i < i2c_test_dev_used; i++) {
+			i2c_s_test = i2c_stress_tests[i].i2c_test;
+			i2c_test_status(&i2c_s_test->test_results, i + 1);
+			msleep(100);
+		}
+	}
+	cflush();
+
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(i2ctest, command_i2ctest, "i2ctest count|udelay|dev",
+			"I2C stress test");
+#endif /* CONFIG_CMD_I2C_STRESS_TEST */
diff --git a/common/i2c_controller_cros_ec.c b/common/i2c_controller_cros_ec.c
new file mode 100644
index 0000000000..d68f67c60e
--- /dev/null
+++ b/common/i2c_controller_cros_ec.c
@@ -0,0 +1,548 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "builtin/assert.h"
+#include "console.h"
+#include "gpio.h"
+#include "i2c.h"
+#include "i2c_bitbang.h"
+#include "i2c_private.h"
+#include "printf.h"
+#include "system.h"
+#include "util.h"
+#include "watchdog.h"
+
+/* This source file contains I2C controller code that is used only in legacy
+ * (CrOS EC) builds.
+ */
+
+#ifdef CONFIG_ZEPHYR
+#error "Don't use this source in Zephyr builds"
+#endif
+
+/* Delay for bitbanging i2c corresponds roughly to 100kHz. */
+#define I2C_BITBANG_DELAY_US 5
+
+/* Number of attempts to unwedge each pin. */
+#define UNWEDGE_SCL_ATTEMPTS 10
+#define UNWEDGE_SDA_ATTEMPTS 3
+
+#define CPUTS(outstr) cputs(CC_I2C, outstr)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args)
+
+int get_sda_from_i2c_port(int port, enum gpio_signal *sda)
+{
+	const struct i2c_port_t *i2c_port = get_i2c_port(port);
+
+	/* Crash if the port given is not in the i2c_ports[] table. */
+	ASSERT(i2c_port);
+
+	/* Check if the SCL and SDA pins have been defined for this port. */
+	if (i2c_port->scl == 0 && i2c_port->sda == 0)
+		return EC_ERROR_INVAL;
+
+	*sda = i2c_port->sda;
+	return EC_SUCCESS;
+}
+
+int get_scl_from_i2c_port(int port, enum gpio_signal *scl)
+{
+	const struct i2c_port_t *i2c_port = get_i2c_port(port);
+
+	/* Crash if the port given is not in the i2c_ports[] table. */
+	ASSERT(i2c_port);
+
+	/* Check if the SCL and SDA pins have been defined for this port. */
+	if (i2c_port->scl == 0 && i2c_port->sda == 0)
+		return EC_ERROR_INVAL;
+
+	*scl = i2c_port->scl;
+	return EC_SUCCESS;
+}
+
+void i2c_raw_set_scl(int port, int level)
+{
+	enum gpio_signal g;
+
+	if (get_scl_from_i2c_port(port, &g) == EC_SUCCESS)
+		gpio_set_level(g, level);
+}
+
+void i2c_raw_set_sda(int port, int level)
+{
+	enum gpio_signal g;
+
+	if (get_sda_from_i2c_port(port, &g) == EC_SUCCESS)
+		gpio_set_level(g, level);
+}
+
+int i2c_raw_mode(int port, int enable)
+{
+	enum gpio_signal sda, scl;
+	int ret_sda, ret_scl;
+
+	/* Get the SDA and SCL pins for this port. If none, then return. */
+	if (get_sda_from_i2c_port(port, &sda) != EC_SUCCESS)
+		return EC_ERROR_INVAL;
+	if (get_scl_from_i2c_port(port, &scl) != EC_SUCCESS)
+		return EC_ERROR_INVAL;
+
+	if (enable) {
+		int raw_gpio_mode_flags = GPIO_ODR_HIGH;
+
+		/* If the CLK line is 1.8V, then ensure we set 1.8V mode */
+		if ((gpio_list + scl)->flags & GPIO_SEL_1P8V)
+			raw_gpio_mode_flags |= GPIO_SEL_1P8V;
+
+		/*
+		 * To enable raw mode, take out of alternate function mode and
+		 * set the flags to open drain output.
+		 */
+		ret_sda = gpio_config_pin(MODULE_I2C, sda, 0);
+		ret_scl = gpio_config_pin(MODULE_I2C, scl, 0);
+
+		gpio_set_flags(scl, raw_gpio_mode_flags);
+		gpio_set_flags(sda, raw_gpio_mode_flags);
+	} else {
+		/*
+		 * Configure the I2C pins to exit raw mode and return
+		 * to normal mode.
+		 */
+		ret_sda = gpio_config_pin(MODULE_I2C, sda, 1);
+		ret_scl = gpio_config_pin(MODULE_I2C, scl, 1);
+	}
+
+	return ret_sda == EC_SUCCESS ? ret_scl : ret_sda;
+}
+
+/*
+ * Unwedge the i2c bus for the given port.
+ *
+ * Some devices on our i2c busses keep power even if we get a reset.  That
+ * means that they could be part way through a transaction and could be
+ * driving the bus in a way that makes it hard for us to talk on the bus.
+ * ...or they might listen to the next transaction and interpret it in a
+ * weird way.
+ *
+ * Note that devices could be in one of several states:
+ * - If a device got interrupted in a write transaction it will be watching
+ *   for additional data to finish its write.  It will probably be looking to
+ *   ack the data (drive the data line low) after it gets everything.
+ * - If a device got interrupted while responding to a register read, it will
+ *   be watching for clocks and will drive data out when it sees clocks.  At
+ *   the moment it might be trying to send out a 1 (so both clock and data
+ *   may be high) or it might be trying to send out a 0 (so it's driving data
+ *   low).
+ *
+ * We attempt to unwedge the bus by doing:
+ * - If SCL is being held low, then a peripheral is clock extending. The only
+ *   thing we can do is try to wait until the peripheral stops clock extending.
+ * - Otherwise, we will toggle the clock until the peripheral releases the SDA
+ *   line. Once the SDA line is released, try to send a STOP bit. Rinse and
+ *   repeat until either the bus is normal, or we run out of attempts.
+ *
+ * Note this should work for most devices, but depending on the peripheral's
+ * i2c state machine, it may not be possible to unwedge the bus.
+ */
+int i2c_unwedge(int port)
+{
+	int i, j;
+	int ret = EC_SUCCESS;
+
+#ifdef CONFIG_I2C_BUS_MAY_BE_UNPOWERED
+	/*
+	 * Don't try to unwedge the port if we know it's unpowered; it's futile.
+	 */
+	if (!board_is_i2c_port_powered(port)) {
+		CPRINTS("Skipping i2c unwedge, bus not powered.");
+		return EC_ERROR_NOT_POWERED;
+	}
+#endif /* CONFIG_I2C_BUS_MAY_BE_UNPOWERED */
+
+	/* Try to put port in to raw bit bang mode. */
+	if (i2c_raw_mode(port, 1) != EC_SUCCESS)
+		return EC_ERROR_UNKNOWN;
+
+	/*
+	 * If clock is low, wait for a while in case of clock stretched
+	 * by a peripheral.
+	 */
+	if (!i2c_raw_get_scl(port)) {
+		for (i = 0;; i++) {
+			if (i >= UNWEDGE_SCL_ATTEMPTS) {
+				/*
+				 * If we get here, a peripheral is holding the
+				 * clock low and there is nothing we can do.
+				 */
+				CPRINTS("I2C%d unwedge failed, "
+					"SCL is held low",
+					port);
+				ret = EC_ERROR_UNKNOWN;
+				goto unwedge_done;
+			}
+			udelay(I2C_BITBANG_DELAY_US);
+			if (i2c_raw_get_scl(port))
+				break;
+		}
+	}
+
+	if (i2c_raw_get_sda(port))
+		goto unwedge_done;
+
+	CPRINTS("I2C%d unwedge called with SDA held low", port);
+
+	/* Keep trying to unwedge the SDA line until we run out of attempts. */
+	for (i = 0; i < UNWEDGE_SDA_ATTEMPTS; i++) {
+		/* Drive the clock high. */
+		i2c_raw_set_scl(port, 1);
+		udelay(I2C_BITBANG_DELAY_US);
+
+		/*
+		 * Clock through the problem by clocking out 9 bits. If
+		 * peripheral releases the SDA line, then we can stop clocking
+		 * bits and send a STOP.
+		 */
+		for (j = 0; j < 9; j++) {
+			if (i2c_raw_get_sda(port))
+				break;
+
+			i2c_raw_set_scl(port, 0);
+			udelay(I2C_BITBANG_DELAY_US);
+			i2c_raw_set_scl(port, 1);
+			udelay(I2C_BITBANG_DELAY_US);
+		}
+
+		/* Take control of SDA line and issue a STOP command. */
+		i2c_raw_set_sda(port, 0);
+		udelay(I2C_BITBANG_DELAY_US);
+		i2c_raw_set_sda(port, 1);
+		udelay(I2C_BITBANG_DELAY_US);
+
+		/* Check if the bus is unwedged. */
+		if (i2c_raw_get_sda(port) && i2c_raw_get_scl(port))
+			break;
+	}
+
+	if (!i2c_raw_get_sda(port)) {
+		CPRINTS("I2C%d unwedge failed, SDA still low", port);
+		ret = EC_ERROR_UNKNOWN;
+	}
+	if (!i2c_raw_get_scl(port)) {
+		CPRINTS("I2C%d unwedge failed, SCL still low", port);
+		ret = EC_ERROR_UNKNOWN;
+	}
+
+unwedge_done:
+	/* Take port out of raw bit bang mode. */
+	i2c_raw_mode(port, 0);
+
+	return ret;
+}
+
+#ifdef CONFIG_CMD_I2C_SCAN
+static void scan_bus(int port, const char *desc)
+{
+	int level;
+	uint8_t tmp;
+	uint16_t addr_flags;
+
+	ccprintf("Scanning %d %s", port, desc);
+
+	i2c_lock(port, 1);
+
+	/* Don't scan a busy port, since reads will just fail / time out */
+	level = i2c_get_line_levels(port);
+	if (level != I2C_LINE_IDLE) {
+		ccprintf(": port busy (SDA=%d, SCL=%d)",
+			 (level & I2C_LINE_SDA_HIGH) ? 1 : 0,
+			 (level & I2C_LINE_SCL_HIGH) ? 1 : 0);
+		goto scan_bus_exit;
+	}
+	/*
+	 * Only scan in the valid client device address range, otherwise some
+	 * client devices stretch the clock in weird ways that prevent the
+	 * discovery of other devices.
+	 */
+	for (addr_flags = I2C_FIRST_VALID_ADDR;
+	     addr_flags <= I2C_LAST_VALID_ADDR; ++addr_flags) {
+		watchdog_reload(); /* Otherwise a full scan trips watchdog */
+		ccputs(".");
+
+		/* Do a single read */
+		if (!i2c_xfer_unlocked(port, addr_flags, NULL, 0, &tmp, 1,
+				       I2C_XFER_SINGLE))
+			ccprintf("\n  0x%02x", addr_flags);
+	}
+
+scan_bus_exit:
+	i2c_lock(port, 0);
+	ccputs("\n");
+}
+
+static int command_scan(int argc, const char **argv)
+{
+	int port;
+	char *e;
+	const struct i2c_port_t *i2c_port;
+
+	if (argc == 1) {
+		for (port = 0; port < i2c_ports_used; port++)
+			scan_bus(i2c_ports[port].port, i2c_ports[port].name);
+
+		if (IS_ENABLED(CONFIG_I2C_BITBANG))
+			for (port = 0; port < i2c_bitbang_ports_used; port++)
+				scan_bus(i2c_bitbang_ports[port].port,
+					 i2c_bitbang_ports[port].name);
+
+		return EC_SUCCESS;
+	}
+
+	port = strtoi(argv[1], &e, 0);
+	if (*e)
+		return EC_ERROR_PARAM2;
+
+	i2c_port = get_i2c_port(port);
+	if (!i2c_port)
+		return EC_ERROR_PARAM2;
+
+	scan_bus(port, i2c_port->name);
+
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(i2cscan, command_scan, "i2cscan [port]",
+			"Scan I2C ports for devices");
+#endif
+
+#ifdef CONFIG_CMD_I2C_XFER
+static int command_i2cxfer(int argc, const char **argv)
+{
+	int port;
+	uint16_t addr_flags;
+	uint16_t offset = 0;
+	uint8_t offset_size = 0;
+	int v = 0;
+	uint8_t data[32];
+	char *e;
+	int rv = 0;
+
+	if (argc < 5)
+		return EC_ERROR_PARAM_COUNT;
+
+	port = strtoi(argv[2], &e, 0);
+	if (*e)
+		return EC_ERROR_PARAM2;
+
+	addr_flags = strtoi(argv[3], &e, 0);
+	if (*e)
+		return EC_ERROR_PARAM3;
+
+	offset = strtoi(argv[4], &e, 0);
+	if (*e)
+		return EC_ERROR_PARAM4;
+
+	offset_size = (strlen(argv[4]) == 6) ? 2 : 1;
+
+	if (argc >= 6) {
+		v = strtoi(argv[5], &e, 0);
+		if (*e)
+			return EC_ERROR_PARAM5;
+	}
+
+	if (strcasecmp(argv[1], "r") == 0) {
+		/* 8-bit read */
+		if (offset_size == 2)
+			rv = i2c_read_offset16(port, addr_flags, offset, &v, 1);
+		else
+			rv = i2c_read8(port, addr_flags, offset, &v);
+		if (!rv)
+			ccprintf("0x%02x [%d]\n", v, v);
+
+	} else if (strcasecmp(argv[1], "r16") == 0) {
+		/* 16-bit read */
+		if (offset_size == 2)
+			rv = i2c_read_offset16(port, addr_flags, offset, &v, 2);
+		else
+			rv = i2c_read16(port, addr_flags, offset, &v);
+		if (!rv)
+			ccprintf("0x%04x [%d]\n", v, v);
+
+	} else if (strcasecmp(argv[1], "rlen") == 0) {
+		/* Arbitrary length read; param5 = len */
+		if (argc < 6 || v < 0 || v > sizeof(data))
+			return EC_ERROR_PARAM5;
+
+		rv = i2c_xfer(port, addr_flags, (uint8_t *)&offset, 1, data, v);
+
+		if (!rv) {
+			char str_buf[hex_str_buf_size(v)];
+
+			snprintf_hex_buffer(str_buf, sizeof(str_buf),
+					    HEX_BUF(data, v));
+			ccprintf("Data: %s\n", str_buf);
+		}
+
+	} else if (strcasecmp(argv[1], "w") == 0) {
+		/* 8-bit write */
+		if (argc < 6)
+			return EC_ERROR_PARAM5;
+		if (offset_size == 2)
+			rv = i2c_write_offset16(port, addr_flags, offset, v, 1);
+		else
+			rv = i2c_write8(port, addr_flags, offset, v);
+
+	} else if (strcasecmp(argv[1], "w16") == 0) {
+		/* 16-bit write */
+		if (argc < 6)
+			return EC_ERROR_PARAM5;
+		if (offset_size == 2)
+			rv = i2c_write_offset16(port, addr_flags, offset, v, 2);
+		else
+			rv = i2c_write16(port, addr_flags, offset, v);
+#ifdef CONFIG_CMD_I2C_XFER_RAW
+	} else if (strcasecmp(argv[1], "raw") == 0) {
+		/* <port> <addr_flags> <read_count> [write_bytes..] */
+		int i;
+		int write_count = 0, read_count = 0;
+		int xferflags = I2C_XFER_START;
+
+		read_count = offset;
+		if (read_count < 0 || read_count > sizeof(data))
+			return EC_ERROR_PARAM5;
+
+		if (argc >= 6) {
+			/* Parse bytes to write */
+			argc -= 5;
+			argv += 5;
+			write_count = argc;
+			if (write_count > sizeof(data)) {
+				ccprintf("Too many bytes to write\n");
+				return EC_ERROR_PARAM_COUNT;
+			}
+
+			for (i = 0; i < write_count; i++) {
+				data[i] = strtoi(argv[i], &e, 0);
+				if (*e) {
+					ccprintf("Bad write byte %d\n", i);
+					return EC_ERROR_INVAL;
+				}
+			}
+		}
+
+		if (write_count) {
+			if (read_count == 0)
+				xferflags |= I2C_XFER_STOP;
+			ccprintf("Writing %d bytes\n", write_count);
+			i2c_lock(port, 1);
+			rv = i2c_xfer_unlocked(port, addr_flags, data,
+					       write_count, NULL, 0, xferflags);
+			if (rv || read_count == 0) {
+				i2c_lock(port, 0);
+				return rv;
+			}
+		}
+		if (read_count) {
+			ccprintf("Reading %d bytes\n", read_count);
+			if (write_count == 0)
+				i2c_lock(port, 1);
+			rv = i2c_xfer_unlocked(port, addr_flags, NULL, 0, data,
+					       read_count,
+					       I2C_XFER_START | I2C_XFER_STOP);
+			i2c_lock(port, 0);
+			if (!rv) {
+				char str_buf[hex_str_buf_size(read_count)];
+
+				snprintf_hex_buffer(str_buf, sizeof(str_buf),
+						    HEX_BUF(data, read_count));
+				ccprintf("Data: %s\n", str_buf);
+			}
+		}
+#endif /* CONFIG_CMD_I2C_XFER_RAW */
+	} else {
+		return EC_ERROR_PARAM1;
+	}
+
+	return rv;
+}
+DECLARE_CONSOLE_COMMAND(i2cxfer, command_i2cxfer,
+			"r/r16/rlen/w/w16 port addr offset [value | len]"
+#ifdef CONFIG_CMD_I2C_XFER_RAW
+			"\nraw port addr read_count [bytes_to_write..]"
+#endif /* CONFIG_CMD_I2C_XFER_RAW */
+			,
+			"Read write I2C");
+#endif
+
+#ifdef CONFIG_CMD_I2C_SPEED
+
+static const char *const i2c_freq_str[] = {
+	[I2C_FREQ_1000KHZ] = "1000 kHz",
+	[I2C_FREQ_400KHZ] = "400 kHz",
+	[I2C_FREQ_100KHZ] = "100 kHz",
+	[I2C_FREQ_COUNT] = "unknown",
+};
+
+BUILD_ASSERT(ARRAY_SIZE(i2c_freq_str) == I2C_FREQ_COUNT + 1);
+
+static int command_i2c_speed(int argc, const char **argv)
+{
+	int port;
+	char *e;
+	enum i2c_freq freq;
+	enum i2c_freq new_freq = I2C_FREQ_COUNT;
+
+	if (argc < 2 || argc > 3)
+		return EC_ERROR_PARAM_COUNT;
+
+	port = strtoi(argv[1], &e, 0);
+	if (*e)
+		return EC_ERROR_PARAM1;
+
+	if (port < 0 || port >= I2C_PORT_COUNT)
+		return EC_ERROR_INVAL;
+
+	freq = i2c_get_freq(port);
+	if (freq < 0 || freq > I2C_FREQ_COUNT)
+		return EC_ERROR_UNKNOWN;
+
+	if (argc == 3) {
+		int khz;
+		int rv;
+
+		khz = strtoi(argv[2], &e, 0);
+		if (*e)
+			return EC_ERROR_PARAM2;
+
+		switch (khz) {
+		case 100:
+			new_freq = I2C_FREQ_100KHZ;
+			break;
+		case 400:
+			new_freq = I2C_FREQ_400KHZ;
+			break;
+		case 1000:
+			new_freq = I2C_FREQ_1000KHZ;
+			break;
+		default:
+			return EC_ERROR_PARAM2;
+		}
+		rv = i2c_set_freq(port, new_freq);
+		if (rv != EC_SUCCESS)
+			return rv;
+	}
+
+	if (new_freq != I2C_FREQ_COUNT)
+		ccprintf("Port %d speed changed from %s to %s\n", port,
+			 i2c_freq_str[freq], i2c_freq_str[new_freq]);
+	else
+		ccprintf("Port %d speed is %s\n", port, i2c_freq_str[freq]);
+
+	return EC_SUCCESS;
+}
+
+DECLARE_CONSOLE_COMMAND(i2cspeed, command_i2c_speed, "port [speed in kHz]",
+			"Get or set I2C port speed");
+
+#endif /* CONFIG_CMD_I2C_SPEED */
diff --git a/common/i2c_hid_touchpad.c b/common/i2c_hid_touchpad.c
index 29122f83d6..2664dabe3e 100644
--- a/common/i2c_hid_touchpad.c
+++ b/common/i2c_hid_touchpad.c
@@ -1,32 +1,31 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include "i2c_hid_touchpad.h"
-
 #include "console.h"
 #include "hwtimer.h"
+#include "i2c_hid_touchpad.h"
 #include "util.h"
 
 /* 2 bytes for length + 1 byte for report ID */
-#define I2C_HID_HEADER_SIZE			3
+#define I2C_HID_HEADER_SIZE 3
 
 /* Report ID */
-#define REPORT_ID_TOUCH				0x01
-#define REPORT_ID_MOUSE				0x02
-#define REPORT_ID_DEVICE_CAPS			0x0A
-#define REPORT_ID_DEVICE_CERT			0x0B
-#define REPORT_ID_INPUT_MODE			0x0C
-#define REPORT_ID_REPORTING			0x0D
+#define REPORT_ID_TOUCH 0x01
+#define REPORT_ID_MOUSE 0x02
+#define REPORT_ID_DEVICE_CAPS 0x0A
+#define REPORT_ID_DEVICE_CERT 0x0B
+#define REPORT_ID_INPUT_MODE 0x0C
+#define REPORT_ID_REPORTING 0x0D
 
-#define INPUT_MODE_MOUSE			0x00
-#define INPUT_MODE_TOUCH			0x03
+#define INPUT_MODE_MOUSE 0x00
+#define INPUT_MODE_TOUCH 0x03
 
 /* VID/PID/FW version */
-#if !defined(I2C_HID_TOUCHPAD_VENDOR_ID) || \
-    !defined(I2C_HID_TOUCHPAD_PRODUCT_ID) || \
-    !defined(I2C_HID_TOUCHPAD_FW_VERSION)
+#if !defined(I2C_HID_TOUCHPAD_VENDOR_ID) ||      \
+	!defined(I2C_HID_TOUCHPAD_PRODUCT_ID) || \
+	!defined(I2C_HID_TOUCHPAD_FW_VERSION)
 #error "Must define touchpad VID/PID/FW version"
 #endif
 /*
@@ -34,10 +33,9 @@
  *
  * Physical dimensions are in the unit of mms.
  */
-#if !defined(I2C_HID_TOUCHPAD_MAX_X) || \
-    !defined(I2C_HID_TOUCHPAD_MAX_Y) || \
-    !defined(I2C_HID_TOUCHPAD_MAX_PHYSICAL_X) || \
-    !defined(I2C_HID_TOUCHPAD_MAX_PHYSICAL_Y)
+#if !defined(I2C_HID_TOUCHPAD_MAX_X) || !defined(I2C_HID_TOUCHPAD_MAX_Y) || \
+	!defined(I2C_HID_TOUCHPAD_MAX_PHYSICAL_X) ||                        \
+	!defined(I2C_HID_TOUCHPAD_MAX_PHYSICAL_Y)
 #error "Must define finger maximum X/Y and physical dimensions"
 #endif
 /*
@@ -49,9 +47,9 @@
  * different data ranges. It is therefore recommended for the user to check the
  * device's spec and set these values manually.
  */
-#if !defined(I2C_HID_TOUCHPAD_MAX_WIDTH) || \
-    !defined(I2C_HID_TOUCHPAD_MAX_HEIGHT) || \
-    !defined(I2C_HID_TOUCHPAD_MAX_PRESSURE)
+#if !defined(I2C_HID_TOUCHPAD_MAX_WIDTH) ||      \
+	!defined(I2C_HID_TOUCHPAD_MAX_HEIGHT) || \
+	!defined(I2C_HID_TOUCHPAD_MAX_PRESSURE)
 #error "Must define finger maximum width/height/pressure"
 #endif
 /*
@@ -67,42 +65,37 @@
  * This is a bit similar to the mouse CPI and is used by mouse reports only.
  */
 #if !defined(I2C_HID_TOUCHPAD_MOUSE_SCALE_X) || \
-    !defined(I2C_HID_TOUCHPAD_MOUSE_SCALE_Y)
+	!defined(I2C_HID_TOUCHPAD_MOUSE_SCALE_Y)
 #error "Must define mouse horizontal/vertical scaling factors"
 #endif
 
 /* Helper bit-op macros */
-#define N_BITS(n) \
-( \
-		(n) < (1 << 1) ? 1 : \
-		(n) < (1 << 2) ? 2 : \
-		(n) < (1 << 3) ? 3 : \
-		(n) < (1 << 4) ? 4 : \
-		(n) < (1 << 5) ? 5 : \
-		(n) < (1 << 6) ? 6 : \
-		(n) < (1 << 7) ? 7 : \
-		(n) < (1 << 8) ? 8 : \
-		(n) < (1 << 9) ? 9 : \
-		(n) < (1 << 10) ? 10 : \
-		(n) < (1 << 11) ? 11 : \
-		(n) < (1 << 12) ? 12 : \
-		(n) < (1 << 13) ? 13 : \
-		(n) < (1 << 14) ? 14 : \
-		(n) < (1 << 15) ? 15 : \
-		16 \
-)
+#define N_BITS(n)               \
+	((n) < (1 << 1)	 ? 1 :  \
+	 (n) < (1 << 2)	 ? 2 :  \
+	 (n) < (1 << 3)	 ? 3 :  \
+	 (n) < (1 << 4)	 ? 4 :  \
+	 (n) < (1 << 5)	 ? 5 :  \
+	 (n) < (1 << 6)	 ? 6 :  \
+	 (n) < (1 << 7)	 ? 7 :  \
+	 (n) < (1 << 8)	 ? 8 :  \
+	 (n) < (1 << 9)	 ? 9 :  \
+	 (n) < (1 << 10) ? 10 : \
+	 (n) < (1 << 11) ? 11 : \
+	 (n) < (1 << 12) ? 12 : \
+	 (n) < (1 << 13) ? 13 : \
+	 (n) < (1 << 14) ? 14 : \
+	 (n) < (1 << 15) ? 15 : \
+			   16)
 /* We would need to pad some bits at the end of each finger struct to match
  * the allocation unit's boundary so the array indexing may work correctly.
  */
-#define N_VAR_BITS \
-( \
-		N_BITS(I2C_HID_TOUCHPAD_MAX_X) + \
-		N_BITS(I2C_HID_TOUCHPAD_MAX_Y) + \
-		N_BITS(I2C_HID_TOUCHPAD_MAX_WIDTH) + \
-		N_BITS(I2C_HID_TOUCHPAD_MAX_HEIGHT) + \
-		N_BITS(I2C_HID_TOUCHPAD_MAX_PRESSURE) + \
-		N_BITS(I2C_HID_TOUCHPAD_MAX_ORIENTATION) \
-)
+#define N_VAR_BITS                                                         \
+	(N_BITS(I2C_HID_TOUCHPAD_MAX_X) + N_BITS(I2C_HID_TOUCHPAD_MAX_Y) + \
+	 N_BITS(I2C_HID_TOUCHPAD_MAX_WIDTH) +                              \
+	 N_BITS(I2C_HID_TOUCHPAD_MAX_HEIGHT) +                             \
+	 N_BITS(I2C_HID_TOUCHPAD_MAX_PRESSURE) +                           \
+	 N_BITS(I2C_HID_TOUCHPAD_MAX_ORIENTATION))
 #define N_PADDING_BITS ((DIV_ROUND_UP(N_VAR_BITS, 8) * 8) - N_VAR_BITS)
 #define N_BITS_ORIENTATION \
 	(N_BITS(I2C_HID_TOUCHPAD_MAX_ORIENTATION) + N_PADDING_BITS)
@@ -121,45 +114,45 @@ struct finger {
 	 * identify unintended contacts or palms but is up to the OS
 	 * explanation.
 	 */
-	uint8_t confidence:1;
+	uint8_t confidence : 1;
 	/*
 	 * Whether a finger is touching the surface (leaving/left finger gets
 	 * 0).
 	 */
-	uint8_t tip:1;
+	uint8_t tip : 1;
 	/*
 	 * Whether a finger is within the sensor range. For example, hovering
 	 * fingers would have tip=0 and inrange=1.
 	 */
-	uint8_t inrange:1;
+	uint8_t inrange : 1;
 	/*
 	 * Contact id. This is like slot numbers in Linux MT-B.
 	 */
-	uint8_t id:5;
-	uint16_t x:N_BITS(I2C_HID_TOUCHPAD_MAX_X);
-	uint16_t y:N_BITS(I2C_HID_TOUCHPAD_MAX_Y);
-	uint16_t width:N_BITS(I2C_HID_TOUCHPAD_MAX_WIDTH);
-	uint16_t height:N_BITS(I2C_HID_TOUCHPAD_MAX_HEIGHT);
-	uint16_t pressure:N_BITS(I2C_HID_TOUCHPAD_MAX_PRESSURE);
-	uint16_t orientation:N_BITS_ORIENTATION;
+	uint8_t id : 5;
+	uint16_t x : N_BITS(I2C_HID_TOUCHPAD_MAX_X);
+	uint16_t y : N_BITS(I2C_HID_TOUCHPAD_MAX_Y);
+	uint16_t width : N_BITS(I2C_HID_TOUCHPAD_MAX_WIDTH);
+	uint16_t height : N_BITS(I2C_HID_TOUCHPAD_MAX_HEIGHT);
+	uint16_t pressure : N_BITS(I2C_HID_TOUCHPAD_MAX_PRESSURE);
+	uint16_t orientation : N_BITS_ORIENTATION;
 } __packed;
 
 struct touch_report {
-	uint8_t button:1;
-	uint8_t count:7;
+	uint8_t button : 1;
+	uint8_t count : 7;
 	uint16_t timestamp;
 	struct finger finger[I2C_HID_TOUCHPAD_MAX_FINGERS];
 } __packed;
 
 struct mouse_report {
-	uint8_t button1:1;
+	uint8_t button1 : 1;
 	/* Windows expects at least two button usages in a mouse report. Many
 	 * touchpads on the Chromebook are a single clickable surface, so
 	 * button2 isn't used. That said, we may later report a button2 event if
 	 * necessary.
 	 */
-	uint8_t button2:1;
-	uint8_t unused:6;
+	uint8_t button2 : 1;
+	uint8_t unused : 6;
 	int8_t x;
 	int8_t y;
 } __packed;
@@ -173,231 +166,215 @@ struct mouse_report {
  */
 static const uint8_t report_desc[] = {
 	/* Mouse Collection */
-	0x05, 0x01,			/* Usage Page (Generic Desktop) */
-	0x09, 0x02,			/* Usage (Mouse) */
-	0xA1, 0x01,			/* Collection (Application) */
-	0x85, REPORT_ID_MOUSE,		/* Report ID (Mouse) */
-	0x09, 0x01,			/*   Usage (Pointer) */
-	0xA1, 0x00,			/*   Collection (Physical) */
-	0x05, 0x09,			/*     Usage Page (Button) */
-	0x19, 0x01,			/*     Usage Minimum (Button 1) */
-	0x29, 0x02,			/*     Usage Maximum (Button 2) */
-	0x15, 0x00,			/*     Logical Minimum (0) */
-	0x25, 0x01,			/*     Logical Maximum (1) */
-	0x75, 0x01,			/*     Report Size (1) */
-	0x95, 0x02,			/*     Report Count (2) */
-	0x81, 0x02,			/*     Input (Data,Var,Abs) */
-	0x95, 0x06,			/*     Report Count (6) */
-	0x81, 0x03,			/*     Input (Cnst,Var,Abs) */
-	0x05, 0x01,			/*     Usage Page (Generic Desktop) */
-	0x09, 0x30,			/*     Usage (X) */
-	0x09, 0x31,			/*     Usage (Y) */
-	0x15, 0x81,			/*     Logical Minimum (-127) */
-	0x25, 0x7F,			/*     Logical Maximum (127) */
-	0x75, 0x08,			/*     Report Size (8) */
-	0x95, 0x02,			/*     Report Count (2) */
-	0x81, 0x06,			/*     Input (Data,Var,Rel) */
-	0xC0,				/*   End Collection */
-	0xC0,				/* End Collection */
+	0x05, 0x01, /* Usage Page (Generic Desktop) */
+	0x09, 0x02, /* Usage (Mouse) */
+	0xA1, 0x01, /* Collection (Application) */
+	0x85, REPORT_ID_MOUSE, /* Report ID (Mouse) */
+	0x09, 0x01, /*   Usage (Pointer) */
+	0xA1, 0x00, /*   Collection (Physical) */
+	0x05, 0x09, /*     Usage Page (Button) */
+	0x19, 0x01, /*     Usage Minimum (Button 1) */
+	0x29, 0x02, /*     Usage Maximum (Button 2) */
+	0x15, 0x00, /*     Logical Minimum (0) */
+	0x25, 0x01, /*     Logical Maximum (1) */
+	0x75, 0x01, /*     Report Size (1) */
+	0x95, 0x02, /*     Report Count (2) */
+	0x81, 0x02, /*     Input (Data,Var,Abs) */
+	0x95, 0x06, /*     Report Count (6) */
+	0x81, 0x03, /*     Input (Cnst,Var,Abs) */
+	0x05, 0x01, /*     Usage Page (Generic Desktop) */
+	0x09, 0x30, /*     Usage (X) */
+	0x09, 0x31, /*     Usage (Y) */
+	0x15, 0x81, /*     Logical Minimum (-127) */
+	0x25, 0x7F, /*     Logical Maximum (127) */
+	0x75, 0x08, /*     Report Size (8) */
+	0x95, 0x02, /*     Report Count (2) */
+	0x81, 0x06, /*     Input (Data,Var,Rel) */
+	0xC0, /*   End Collection */
+	0xC0, /* End Collection */
 
 	/* Touchpad Collection */
-	0x05, 0x0D,			/* Usage Page (Digitizer) */
-	0x09, 0x05,			/* Usage (Touch Pad) */
-	0xA1, 0x01,			/* Collection (Application) */
-	0x85, REPORT_ID_TOUCH,		/*   Report ID (Touch) */
+	0x05, 0x0D, /* Usage Page (Digitizer) */
+	0x09, 0x05, /* Usage (Touch Pad) */
+	0xA1, 0x01, /* Collection (Application) */
+	0x85, REPORT_ID_TOUCH, /*   Report ID (Touch) */
 
 	/* Button */
-	0x05, 0x09,			/*   Usage Page (Button) */
-	0x19, 0x01,			/*   Usage Minimum (0x01) */
-	0x29, 0x01,			/*   Usage Maximum (0x01) */
-	0x15, 0x00,			/*   Logical Minimum (0) */
-	0x25, 0x01,			/*   Logical Maximum (1) */
-	0x75, 0x01,			/*   Report Size (1) */
-	0x95, 0x01,			/*   Report Count (1) */
-	0x81, 0x02,			/*   Input (Data,Var,Abs) */
+	0x05, 0x09, /*   Usage Page (Button) */
+	0x19, 0x01, /*   Usage Minimum (0x01) */
+	0x29, 0x01, /*   Usage Maximum (0x01) */
+	0x15, 0x00, /*   Logical Minimum (0) */
+	0x25, 0x01, /*   Logical Maximum (1) */
+	0x75, 0x01, /*   Report Size (1) */
+	0x95, 0x01, /*   Report Count (1) */
+	0x81, 0x02, /*   Input (Data,Var,Abs) */
 
 	/* Contact count */
-	0x05, 0x0D,			/*   Usage Page (Digitizer) */
-	0x09, 0x54,			/*   Usage (Contact count) */
-	0x25, I2C_HID_TOUCHPAD_MAX_FINGERS,	/* Logical Max. (MAX_FINGERS) */
-	0x75, 0x07,			/*   Report Size (7) */
-	0x95, 0x01,			/*   Report Count (1) */
-	0x81, 0x02,			/*   Input (Data,Var,Abs) */
+	0x05, 0x0D, /*   Usage Page (Digitizer) */
+	0x09, 0x54, /*   Usage (Contact count) */
+	0x25, I2C_HID_TOUCHPAD_MAX_FINGERS, /* Logical Max. (MAX_FINGERS) */
+	0x75, 0x07, /*   Report Size (7) */
+	0x95, 0x01, /*   Report Count (1) */
+	0x81, 0x02, /*   Input (Data,Var,Abs) */
 
 	/* Scan time */
-	0x55, 0x0C,			/*   Unit Exponent (-4) */
-	0x66, 0x01, 0x10,		/*   Unit (Seconds) */
-	0x47, 0xFF, 0xFF, 0x00, 0x00,	/*   Physical Maximum (65535) */
-	0x27, 0xFF, 0xFF, 0x00, 0x00,	/*   Logical Maximum (65535) */
-	0x75, 0x10,			/*   Report Size (16) */
-	0x95, 0x01,			/*   Report Count (1) */
-	0x05, 0x0D,			/*   Usage Page (Digitizers) */
-	0x09, 0x56,			/*   Usage (Scan Time) */
-	0x81, 0x02,			/*   Input (Data,Var,Abs) */
-
-#define FINGER(FINGER_NUMBER)						       \
-	/* Finger FINGER_NUMBER */					       \
-	0x05, 0x0D,			/*   Usage Page (Digitizer) */         \
-	0x09, 0x22,			/*   Usage (Finger) */                 \
-	0xA1, 0x02,			/*   Collection (Logical) */           \
-	0x09, 0x47,			/*     Usage (Confidence) */           \
-	0x09, 0x42,			/*     Usage (Tip Switch) */           \
-	0x09, 0x32,			/*     Usage (In Range) */             \
-	0x15, 0x00,			/*     Logical Minimum (0) */          \
-	0x25, 0x01,			/*     Logical Maximum (1) */          \
-	0x75, 0x01,			/*     Report Size (1) */              \
-	0x95, 0x03,			/*     Report Count (3) */             \
-	0x81, 0x02,			/*     Input (Data,Var,Abs) */         \
-	0x09, 0x51,			/*     Usage (Contact identifier) */   \
-	0x25, 0x1F,			/*     Logical Maximum (31) */         \
-	0x75, 0x05,			/*     Report Size (5) */              \
-	0x95, 0x01,			/*     Report Count (1) */             \
-	0x81, 0x02,			/*     Input (Data,Var,Abs) */         \
-	0x05, 0x01,			/*     Usage Page (Generic Desktop) */ \
-	0x09, 0x30,			/*     Usage (X) */                    \
-	0x55, 0x0E,			/*     Unit Exponent (-2) */           \
-	0x65, 0x11,			/*     Unit (SI Linear, Length: cm) */ \
-	0x35, 0x00,			/*     Physical Minimum (0) */         \
-	0x46, I2C_HID_TOUCHPAD_MAX_PHYSICAL_X&0xff,			       \
-	      I2C_HID_TOUCHPAD_MAX_PHYSICAL_X>>8,			       \
-					/*     Physical Maximum */	       \
-	0x26, I2C_HID_TOUCHPAD_MAX_X&0xff, I2C_HID_TOUCHPAD_MAX_X>>8,	       \
-					/*     Logical Maximum */	       \
-	0x75, N_BITS(I2C_HID_TOUCHPAD_MAX_X),				       \
-					/*     Report Size */		       \
-	0x81, 0x02,			/*     Input (Data,Var,Abs) */         \
-	0x09, 0x31,			/*     Usage (Y) */                    \
-	0x46, I2C_HID_TOUCHPAD_MAX_PHYSICAL_Y&0xff,			       \
-	      I2C_HID_TOUCHPAD_MAX_PHYSICAL_Y>>8,			       \
-					/*     Physical Maximum */	       \
-	0x26, I2C_HID_TOUCHPAD_MAX_Y&0xff, I2C_HID_TOUCHPAD_MAX_Y>>8,	       \
-					/*     Logical Maximum */	       \
-	0x75, N_BITS(I2C_HID_TOUCHPAD_MAX_Y),				       \
-					/*     Report Size */		       \
-	0x81, 0x02,			/*     Input (Data,Var,Abs) */         \
-	0x05, 0x0D,			/*     Usage Page (Digitizer) */       \
-	0x09, 0x48,			/*     Usage (Width) */                \
-	0x26, I2C_HID_TOUCHPAD_MAX_WIDTH&0xff, I2C_HID_TOUCHPAD_MAX_WIDTH>>8,  \
-					/*     Logical Maximum */	       \
-	0x75, N_BITS(I2C_HID_TOUCHPAD_MAX_WIDTH),			       \
-					/*     Report Size */		       \
-	0x81, 0x02,			/*     Input (Data,Var,Abs) */         \
-	0x09, 0x49,			/*     Usage (Height) */               \
-	0x26, I2C_HID_TOUCHPAD_MAX_HEIGHT&0xff, I2C_HID_TOUCHPAD_MAX_HEIGHT>>8,\
-					/*     Logical Maximum */	       \
-	0x75, N_BITS(I2C_HID_TOUCHPAD_MAX_HEIGHT),			       \
-					/*     Report Size */		       \
-	0x81, 0x02,			/*     Input (Data,Var,Abs) */         \
-	0x09, 0x30,			/*     Usage (Tip pressure) */         \
-	0x26, I2C_HID_TOUCHPAD_MAX_PRESSURE&0xff,			       \
-	      I2C_HID_TOUCHPAD_MAX_PRESSURE>>8,				       \
-					/*     Logical Maximum */	       \
-	0x75, N_BITS(I2C_HID_TOUCHPAD_MAX_PRESSURE),			       \
-					/*     Report Size */		       \
-	0x81, 0x02,			/*     Input (Data,Var,Abs) */         \
-	0x09, 0x3f,			/*     Usage (Azimuth Orientation) */  \
-	0x16, 0x00, 0x00,		/*     Logical Minimum (0) */          \
-	0x26, I2C_HID_TOUCHPAD_MAX_ORIENTATION&0xff,			       \
-	      I2C_HID_TOUCHPAD_MAX_ORIENTATION>>8,			       \
-					/*     Logical Maximum */	       \
-	0x75, N_BITS_ORIENTATION,	/*     Report Size */		       \
-	0x81, 0x02,			/*     Input (Data,Var,Abs) */         \
-	0xC0,				/*   End Collection */
-
-	FINGER(1)
-	FINGER(2)
-	FINGER(3)
-	FINGER(4)
-	FINGER(5)
+	0x55, 0x0C, /*   Unit Exponent (-4) */
+	0x66, 0x01, 0x10, /*   Unit (Seconds) */
+	0x47, 0xFF, 0xFF, 0x00, 0x00, /*   Physical Maximum (65535) */
+	0x27, 0xFF, 0xFF, 0x00, 0x00, /*   Logical Maximum (65535) */
+	0x75, 0x10, /*   Report Size (16) */
+	0x95, 0x01, /*   Report Count (1) */
+	0x05, 0x0D, /*   Usage Page (Digitizers) */
+	0x09, 0x56, /*   Usage (Scan Time) */
+	0x81, 0x02, /*   Input (Data,Var,Abs) */
+
+#define FINGER(FINGER_NUMBER)                                                 \
+	/* Finger FINGER_NUMBER */                                            \
+	0x05, 0x0D, /*   Usage Page (Digitizer) */                            \
+		0x09, 0x22, /*   Usage (Finger) */                            \
+		0xA1, 0x02, /*   Collection (Logical) */                      \
+		0x09, 0x47, /*     Usage (Confidence) */                      \
+		0x09, 0x42, /*     Usage (Tip Switch) */                      \
+		0x09, 0x32, /*     Usage (In Range) */                        \
+		0x15, 0x00, /*     Logical Minimum (0) */                     \
+		0x25, 0x01, /*     Logical Maximum (1) */                     \
+		0x75, 0x01, /*     Report Size (1) */                         \
+		0x95, 0x03, /*     Report Count (3) */                        \
+		0x81, 0x02, /*     Input (Data,Var,Abs) */                    \
+		0x09, 0x51, /*     Usage (Contact identifier) */              \
+		0x25, 0x1F, /*     Logical Maximum (31) */                    \
+		0x75, 0x05, /*     Report Size (5) */                         \
+		0x95, 0x01, /*     Report Count (1) */                        \
+		0x81, 0x02, /*     Input (Data,Var,Abs) */                    \
+		0x05, 0x01, /*     Usage Page (Generic Desktop) */            \
+		0x09, 0x30, /*     Usage (X) */                               \
+		0x55, 0x0E, /*     Unit Exponent (-2) */                      \
+		0x65, 0x11, /*     Unit (SI Linear, Length: cm) */            \
+		0x35, 0x00, /*     Physical Minimum (0) */                    \
+		0x46, I2C_HID_TOUCHPAD_MAX_PHYSICAL_X & 0xff,                 \
+		I2C_HID_TOUCHPAD_MAX_PHYSICAL_X >> 8, /*     Physical Maximum \
+						       */                     \
+		0x26, I2C_HID_TOUCHPAD_MAX_X & 0xff,                          \
+		I2C_HID_TOUCHPAD_MAX_X >> 8, /*     Logical Maximum */        \
+		0x75, N_BITS(I2C_HID_TOUCHPAD_MAX_X), /*     Report Size */   \
+		0x81, 0x02, /*     Input (Data,Var,Abs) */                    \
+		0x09, 0x31, /*     Usage (Y) */                               \
+		0x46, I2C_HID_TOUCHPAD_MAX_PHYSICAL_Y & 0xff,                 \
+		I2C_HID_TOUCHPAD_MAX_PHYSICAL_Y >> 8, /*     Physical Maximum \
+						       */                     \
+		0x26, I2C_HID_TOUCHPAD_MAX_Y & 0xff,                          \
+		I2C_HID_TOUCHPAD_MAX_Y >> 8, /*     Logical Maximum */        \
+		0x75, N_BITS(I2C_HID_TOUCHPAD_MAX_Y), /*     Report Size */   \
+		0x81, 0x02, /*     Input (Data,Var,Abs) */                    \
+		0x05, 0x0D, /*     Usage Page (Digitizer) */                  \
+		0x09, 0x48, /*     Usage (Width) */                           \
+		0x26, I2C_HID_TOUCHPAD_MAX_WIDTH & 0xff,                      \
+		I2C_HID_TOUCHPAD_MAX_WIDTH >> 8, /*     Logical Maximum */    \
+		0x75, N_BITS(I2C_HID_TOUCHPAD_MAX_WIDTH), /*     Report Size  \
+							   */                 \
+		0x81, 0x02, /*     Input (Data,Var,Abs) */                    \
+		0x09, 0x49, /*     Usage (Height) */                          \
+		0x26, I2C_HID_TOUCHPAD_MAX_HEIGHT & 0xff,                     \
+		I2C_HID_TOUCHPAD_MAX_HEIGHT >> 8, /*     Logical Maximum */   \
+		0x75, N_BITS(I2C_HID_TOUCHPAD_MAX_HEIGHT), /*     Report Size \
+							    */                \
+		0x81, 0x02, /*     Input (Data,Var,Abs) */                    \
+		0x09, 0x30, /*     Usage (Tip pressure) */                    \
+		0x26, I2C_HID_TOUCHPAD_MAX_PRESSURE & 0xff,                   \
+		I2C_HID_TOUCHPAD_MAX_PRESSURE >> 8, /*     Logical Maximum */ \
+		0x75, N_BITS(I2C_HID_TOUCHPAD_MAX_PRESSURE), /*     Report    \
+								Size */       \
+		0x81, 0x02, /*     Input (Data,Var,Abs) */                    \
+		0x09, 0x3f, /*     Usage (Azimuth Orientation) */             \
+		0x16, 0x00, 0x00, /*     Logical Minimum (0) */               \
+		0x26, I2C_HID_TOUCHPAD_MAX_ORIENTATION & 0xff,                \
+		I2C_HID_TOUCHPAD_MAX_ORIENTATION >> 8, /*     Logical Maximum \
+							*/                    \
+		0x75, N_BITS_ORIENTATION, /*     Report Size */               \
+		0x81, 0x02, /*     Input (Data,Var,Abs) */                    \
+		0xC0, /*   End Collection */
+
+	FINGER(1) FINGER(2) FINGER(3) FINGER(4) FINGER(5)
 
 #undef FINGER
 
-	0x05, 0x0D,			/*   Usage Page (Digitizer) */
-	0x85, REPORT_ID_DEVICE_CAPS,	/*   Report ID (Device Capabilities) */
-	0x09, 0x55,			/*   Usage (Contact Count Maximum) */
-	0x09, 0x59,			/*   Usage (Pad Type) */
-	0x75, 0x08,			/*   Report Size (8) */
-	0x95, 0x02,			/*   Report Count (2) */
-	0x25, 0x0F,			/*   Logical Maximum (15) */
-	0xB1, 0x02,			/*   Feature (Data,Var,Abs) */
-	0x06, 0x00, 0xFF,		/*   Usage Page (Vendor Defined) */
-	0x85, REPORT_ID_DEVICE_CERT,	/*   Report ID (Device Certification) */
-	0x09, 0xC5,			/*   Usage (Vendor Usage 0xC5) */
-	0x15, 0x00,			/*   Logical Minimum (0) */
-	0x26, 0xFF, 0x00,		/*   Logical Maximum (255) */
-	0x75, 0x08,			/*   Report Size (8) */
-	0x96, 0x00, 0x01,		/*   Report Count (256) */
-	0xB1, 0x02,			/*   Feature (Data,Var,Abs) */
-	0xC0,				/* End Collection */
+		0x05,
+	0x0D, /*   Usage Page (Digitizer) */
+	0x85, REPORT_ID_DEVICE_CAPS, /*   Report ID (Device Capabilities) */
+	0x09, 0x55, /*   Usage (Contact Count Maximum) */
+	0x09, 0x59, /*   Usage (Pad Type) */
+	0x75, 0x08, /*   Report Size (8) */
+	0x95, 0x02, /*   Report Count (2) */
+	0x25, 0x0F, /*   Logical Maximum (15) */
+	0xB1, 0x02, /*   Feature (Data,Var,Abs) */
+	0x06, 0x00, 0xFF, /*   Usage Page (Vendor Defined) */
+	0x85, REPORT_ID_DEVICE_CERT, /*   Report ID (Device Certification) */
+	0x09, 0xC5, /*   Usage (Vendor Usage 0xC5) */
+	0x15, 0x00, /*   Logical Minimum (0) */
+	0x26, 0xFF, 0x00, /*   Logical Maximum (255) */
+	0x75, 0x08, /*   Report Size (8) */
+	0x96, 0x00, 0x01, /*   Report Count (256) */
+	0xB1, 0x02, /*   Feature (Data,Var,Abs) */
+	0xC0, /* End Collection */
 
 	/* Configuration Collection */
-	0x05, 0x0D,			/* Usage Page (Digitizer) */
-	0x09, 0x0E,			/* Usage (Configuration) */
-	0xA1, 0x01,			/* Collection (Application) */
-	0x85, REPORT_ID_INPUT_MODE,	/*   Report ID (Input Mode) */
-	0x09, 0x22,			/*   Usage (Finger) */
-	0xA1, 0x02,			/*   Collection (Logical) */
-	0x09, 0x52,			/*     Usage (Input Mode) */
-	0x15, 0x00,			/*     Logical Minimum (0) */
-	0x25, 0x0F,			/*     Logical Maximum (15) */
-	0x75, 0x08,			/*     Report Size (8) */
-	0x95, 0x01,			/*     Report Count (1) */
-	0xB1, 0x02,			/*     Feature (Data,Var,Abs) */
-	0xC0,				/*   End Collection */
-	0x09, 0x22,			/*   Usage (Finger) */
-	0xA1, 0x00,			/*   Collection (Physical) */
-	0x85, REPORT_ID_REPORTING,	/*     Report ID (Selective Reporting)*/
-	0x09, 0x57,			/*     Usage (Surface Switch) */
-	0x09, 0x58,			/*     Usage (Button Switch) */
-	0x75, 0x04,			/*     Report Size (4) */
-	0x95, 0x02,			/*     Report Count (2) */
-	0x25, 0x01,			/*     Logical Maximum (1) */
-	0xB1, 0x02,			/*     Feature (Data,Var,Abs) */
-	0xC0,				/*   End Collection */
-	0xC0,				/* End Collection */
+	0x05, 0x0D, /* Usage Page (Digitizer) */
+	0x09, 0x0E, /* Usage (Configuration) */
+	0xA1, 0x01, /* Collection (Application) */
+	0x85, REPORT_ID_INPUT_MODE, /*   Report ID (Input Mode) */
+	0x09, 0x22, /*   Usage (Finger) */
+	0xA1, 0x02, /*   Collection (Logical) */
+	0x09, 0x52, /*     Usage (Input Mode) */
+	0x15, 0x00, /*     Logical Minimum (0) */
+	0x25, 0x0F, /*     Logical Maximum (15) */
+	0x75, 0x08, /*     Report Size (8) */
+	0x95, 0x01, /*     Report Count (1) */
+	0xB1, 0x02, /*     Feature (Data,Var,Abs) */
+	0xC0, /*   End Collection */
+	0x09, 0x22, /*   Usage (Finger) */
+	0xA1, 0x00, /*   Collection (Physical) */
+	0x85, REPORT_ID_REPORTING, /*     Report ID (Selective Reporting)*/
+	0x09, 0x57, /*     Usage (Surface Switch) */
+	0x09, 0x58, /*     Usage (Button Switch) */
+	0x75, 0x04, /*     Report Size (4) */
+	0x95, 0x02, /*     Report Count (2) */
+	0x25, 0x01, /*     Logical Maximum (1) */
+	0xB1, 0x02, /*     Feature (Data,Var,Abs) */
+	0xC0, /*   End Collection */
+	0xC0, /* End Collection */
 };
 
 static const uint8_t device_caps[] = {
-	I2C_HID_TOUCHPAD_MAX_FINGERS,	/* Contact Count Maximum */
-	0x00,				/* Pad Type: Depressible click-pad */
+	I2C_HID_TOUCHPAD_MAX_FINGERS, /* Contact Count Maximum */
+	0x00, /* Pad Type: Depressible click-pad */
 };
 
 /* A 256-byte default blob for the 'device certification status' feature report
  * expected by Windows.
  */
 static const uint8_t device_cert[] = {
-	0xFC, 0x28, 0xFE, 0x84, 0x40, 0xCB, 0x9A, 0x87,
-	0x0D, 0xBE, 0x57, 0x3C, 0xB6, 0x70, 0x09, 0x88,
-	0x07, 0x97, 0x2D, 0x2B, 0xE3, 0x38, 0x34, 0xB6,
-	0x6C, 0xED, 0xB0, 0xF7, 0xE5, 0x9C, 0xF6, 0xC2,
-	0x2E, 0x84, 0x1B, 0xE8, 0xB4, 0x51, 0x78, 0x43,
-	0x1F, 0x28, 0x4B, 0x7C, 0x2D, 0x53, 0xAF, 0xFC,
-	0x47, 0x70, 0x1B, 0x59, 0x6F, 0x74, 0x43, 0xC4,
-	0xF3, 0x47, 0x18, 0x53, 0x1A, 0xA2, 0xA1, 0x71,
-	0xC7, 0x95, 0x0E, 0x31, 0x55, 0x21, 0xD3, 0xB5,
-	0x1E, 0xE9, 0x0C, 0xBA, 0xEC, 0xB8, 0x89, 0x19,
-	0x3E, 0xB3, 0xAF, 0x75, 0x81, 0x9D, 0x53, 0xB9,
-	0x41, 0x57, 0xF4, 0x6D, 0x39, 0x25, 0x29, 0x7C,
-	0x87, 0xD9, 0xB4, 0x98, 0x45, 0x7D, 0xA7, 0x26,
-	0x9C, 0x65, 0x3B, 0x85, 0x68, 0x89, 0xD7, 0x3B,
-	0xBD, 0xFF, 0x14, 0x67, 0xF2, 0x2B, 0xF0, 0x2A,
-	0x41, 0x54, 0xF0, 0xFD, 0x2C, 0x66, 0x7C, 0xF8,
-	0xC0, 0x8F, 0x33, 0x13, 0x03, 0xF1, 0xD3, 0xC1,
-	0x0B, 0x89, 0xD9, 0x1B, 0x62, 0xCD, 0x51, 0xB7,
-	0x80, 0xB8, 0xAF, 0x3A, 0x10, 0xC1, 0x8A, 0x5B,
-	0xE8, 0x8A, 0x56, 0xF0, 0x8C, 0xAA, 0xFA, 0x35,
-	0xE9, 0x42, 0xC4, 0xD8, 0x55, 0xC3, 0x38, 0xCC,
-	0x2B, 0x53, 0x5C, 0x69, 0x52, 0xD5, 0xC8, 0x73,
-	0x02, 0x38, 0x7C, 0x73, 0xB6, 0x41, 0xE7, 0xFF,
-	0x05, 0xD8, 0x2B, 0x79, 0x9A, 0xE2, 0x34, 0x60,
-	0x8F, 0xA3, 0x32, 0x1F, 0x09, 0x78, 0x62, 0xBC,
-	0x80, 0xE3, 0x0F, 0xBD, 0x65, 0x20, 0x08, 0x13,
-	0xC1, 0xE2, 0xEE, 0x53, 0x2D, 0x86, 0x7E, 0xA7,
-	0x5A, 0xC5, 0xD3, 0x7D, 0x98, 0xBE, 0x31, 0x48,
-	0x1F, 0xFB, 0xDA, 0xAF, 0xA2, 0xA8, 0x6A, 0x89,
-	0xD6, 0xBF, 0xF2, 0xD3, 0x32, 0x2A, 0x9A, 0xE4,
-	0xCF, 0x17, 0xB7, 0xB8, 0xF4, 0xE1, 0x33, 0x08,
-	0x24, 0x8B, 0xC4, 0x43, 0xA5, 0xE5, 0x24, 0xC2,
+	0xFC, 0x28, 0xFE, 0x84, 0x40, 0xCB, 0x9A, 0x87, 0x0D, 0xBE, 0x57, 0x3C,
+	0xB6, 0x70, 0x09, 0x88, 0x07, 0x97, 0x2D, 0x2B, 0xE3, 0x38, 0x34, 0xB6,
+	0x6C, 0xED, 0xB0, 0xF7, 0xE5, 0x9C, 0xF6, 0xC2, 0x2E, 0x84, 0x1B, 0xE8,
+	0xB4, 0x51, 0x78, 0x43, 0x1F, 0x28, 0x4B, 0x7C, 0x2D, 0x53, 0xAF, 0xFC,
+	0x47, 0x70, 0x1B, 0x59, 0x6F, 0x74, 0x43, 0xC4, 0xF3, 0x47, 0x18, 0x53,
+	0x1A, 0xA2, 0xA1, 0x71, 0xC7, 0x95, 0x0E, 0x31, 0x55, 0x21, 0xD3, 0xB5,
+	0x1E, 0xE9, 0x0C, 0xBA, 0xEC, 0xB8, 0x89, 0x19, 0x3E, 0xB3, 0xAF, 0x75,
+	0x81, 0x9D, 0x53, 0xB9, 0x41, 0x57, 0xF4, 0x6D, 0x39, 0x25, 0x29, 0x7C,
+	0x87, 0xD9, 0xB4, 0x98, 0x45, 0x7D, 0xA7, 0x26, 0x9C, 0x65, 0x3B, 0x85,
+	0x68, 0x89, 0xD7, 0x3B, 0xBD, 0xFF, 0x14, 0x67, 0xF2, 0x2B, 0xF0, 0x2A,
+	0x41, 0x54, 0xF0, 0xFD, 0x2C, 0x66, 0x7C, 0xF8, 0xC0, 0x8F, 0x33, 0x13,
+	0x03, 0xF1, 0xD3, 0xC1, 0x0B, 0x89, 0xD9, 0x1B, 0x62, 0xCD, 0x51, 0xB7,
+	0x80, 0xB8, 0xAF, 0x3A, 0x10, 0xC1, 0x8A, 0x5B, 0xE8, 0x8A, 0x56, 0xF0,
+	0x8C, 0xAA, 0xFA, 0x35, 0xE9, 0x42, 0xC4, 0xD8, 0x55, 0xC3, 0x38, 0xCC,
+	0x2B, 0x53, 0x5C, 0x69, 0x52, 0xD5, 0xC8, 0x73, 0x02, 0x38, 0x7C, 0x73,
+	0xB6, 0x41, 0xE7, 0xFF, 0x05, 0xD8, 0x2B, 0x79, 0x9A, 0xE2, 0x34, 0x60,
+	0x8F, 0xA3, 0x32, 0x1F, 0x09, 0x78, 0x62, 0xBC, 0x80, 0xE3, 0x0F, 0xBD,
+	0x65, 0x20, 0x08, 0x13, 0xC1, 0xE2, 0xEE, 0x53, 0x2D, 0x86, 0x7E, 0xA7,
+	0x5A, 0xC5, 0xD3, 0x7D, 0x98, 0xBE, 0x31, 0x48, 0x1F, 0xFB, 0xDA, 0xAF,
+	0xA2, 0xA8, 0x6A, 0x89, 0xD6, 0xBF, 0xF2, 0xD3, 0x32, 0x2A, 0x9A, 0xE4,
+	0xCF, 0x17, 0xB7, 0xB8, 0xF4, 0xE1, 0x33, 0x08, 0x24, 0x8B, 0xC4, 0x43,
+	0xA5, 0xE5, 0x24, 0xC2,
 };
 
 #define MAX_SIZEOF(a, b) (sizeof(a) > sizeof(b) ? sizeof(a) : sizeof(b))
@@ -431,7 +408,7 @@ static bool pending_probe;
 static bool pending_reset;
 
 /* Reports (double buffered) */
-#define MAX_REPORT_CNT	2
+#define MAX_REPORT_CNT 2
 
 static struct touch_report touch_reports[MAX_REPORT_CNT];
 static struct mouse_report mouse_reports[MAX_REPORT_CNT];
@@ -448,8 +425,8 @@ static uint8_t input_mode;
  * |reporting.button_switch|, respectively.
  */
 struct selective_reporting {
-	uint8_t surface_switch:4;
-	uint8_t button_switch:4;
+	uint8_t surface_switch : 4;
+	uint8_t button_switch : 4;
 } __packed;
 
 static struct selective_reporting reporting;
@@ -568,7 +545,7 @@ int i2c_hid_touchpad_process(unsigned int len, uint8_t *buffer,
 		break;
 	case I2C_HID_COMMAND_REGISTER:
 		*cmd = i2c_hid_touchpad_command_process(len, buffer,
-						       send_response, data);
+							send_response, data);
 		break;
 	default:
 		/* Unknown register has been received. */
@@ -697,9 +674,9 @@ void i2c_hid_compile_report(struct touchpad_event *event)
 			touch->finger[i].pressure = event->finger[i].pressure;
 			if (event->finger[i].is_palm)
 				touch->finger[i].pressure =
-						I2C_HID_TOUCHPAD_MAX_PRESSURE;
+					I2C_HID_TOUCHPAD_MAX_PRESSURE;
 			touch->finger[i].orientation =
-					event->finger[i].orientation;
+				event->finger[i].orientation;
 			contact_num++;
 		} else if (touch_old->finger[i].tip) {
 			/*
diff --git a/common/i2c_master.c b/common/i2c_master.c
deleted file mode 100644
index f078e690f7..0000000000
--- a/common/i2c_master.c
+++ /dev/null
@@ -1,1665 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* I2C cross-platform code for Chrome EC */
-
-#include "battery.h"
-#include "clock.h"
-#include "charge_state.h"
-#include "console.h"
-#include "crc8.h"
-#include "host_command.h"
-#include "gpio.h"
-#include "i2c.h"
-#include "i2c_bitbang.h"
-#include "i2c_private.h"
-#include "system.h"
-#include "task.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-#include "watchdog.h"
-#include "virtual_battery.h"
-
-/* Delay for bitbanging i2c corresponds roughly to 100kHz. */
-#define I2C_BITBANG_DELAY_US	5
-
-/* Number of attempts to unwedge each pin. */
-#define UNWEDGE_SCL_ATTEMPTS  10
-#define UNWEDGE_SDA_ATTEMPTS  3
-
-#define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args)
-
-/* Only chips with multi-port controllers will define I2C_CONTROLLER_COUNT */
-#ifndef I2C_CONTROLLER_COUNT
-#define I2C_CONTROLLER_COUNT I2C_PORT_COUNT
-#endif
-
-#ifndef CONFIG_I2C_BITBANG
-#define I2C_BITBANG_PORT_COUNT 0
-#endif
-
-static struct mutex port_mutex[I2C_CONTROLLER_COUNT + I2C_BITBANG_PORT_COUNT];
-/* A bitmap of the controllers which are currently servicing a request. */
-static uint32_t i2c_port_active_list;
-BUILD_ASSERT(ARRAY_SIZE(port_mutex) < 32);
-static uint8_t port_protected[I2C_PORT_COUNT + I2C_BITBANG_PORT_COUNT];
-
-/**
- * Non-deterministically test the lock status of the port.  If another task
- * has locked the port and the caller is accessing it illegally, then this test
- * will incorrectly return true.  However, callers which failed to statically
- * lock the port will fail quickly.
- */
-static int i2c_port_is_locked(int port)
-{
-#ifdef CONFIG_I2C_MULTI_PORT_CONTROLLER
-	/* Test the controller, not the port */
-	port = i2c_port_to_controller(port);
-#endif
-	/* can't lock a non-existing port */
-	if (port < 0)
-		return 0;
-
-	return (i2c_port_active_list >> port) & 1;
-}
-
-
-const struct i2c_port_t *get_i2c_port(const int port)
-{
-	int i;
-
-	/* Find the matching port in i2c_ports[] table. */
-	for (i = 0; i < i2c_ports_used; i++) {
-		if (i2c_ports[i].port == port)
-			return &i2c_ports[i];
-	}
-
-	if (IS_ENABLED(CONFIG_I2C_BITBANG)) {
-		for (i = 0; i < i2c_bitbang_ports_used; i++) {
-			if (i2c_bitbang_ports[i].port == port)
-				return &i2c_bitbang_ports[i];
-		}
-	}
-
-	return NULL;
-}
-
-static int chip_i2c_xfer_with_notify(const int port,
-				     const uint16_t slave_addr_flags,
-				     const uint8_t *out, int out_size,
-				     uint8_t *in, int in_size, int flags)
-{
-	int ret;
-	uint16_t addr_flags = slave_addr_flags;
-	const struct i2c_port_t *i2c_port = get_i2c_port(port);
-
-	if (IS_ENABLED(CONFIG_I2C_XFER_BOARD_CALLBACK))
-		i2c_start_xfer_notify(port, slave_addr_flags);
-
-	if (IS_ENABLED(CONFIG_SMBUS_PEC))
-		/*
-		 * Since we've done PEC processing here,
-		 * remove the flag so it won't confuse chip driver.
-		 */
-		addr_flags &= ~I2C_FLAG_PEC;
-	if (i2c_port->drv)
-		ret = i2c_port->drv->xfer(i2c_port, addr_flags,
-					  out, out_size, in, in_size, flags);
-	else
-		ret = chip_i2c_xfer(port, addr_flags,
-				    out, out_size, in, in_size, flags);
-
-	if (IS_ENABLED(CONFIG_I2C_XFER_BOARD_CALLBACK))
-		i2c_end_xfer_notify(port, slave_addr_flags);
-
-	if (IS_ENABLED(CONFIG_I2C_DEBUG)) {
-		i2c_trace_notify(port, slave_addr_flags, out, out_size,
-				 in, in_size);
-	}
-
-	return ret;
-}
-
-#ifdef CONFIG_I2C_XFER_LARGE_READ
-/*
- * Internal function that splits reading into multiple chip_i2c_xfer() calls
- * if in_size exceeds CONFIG_I2C_CHIP_MAX_READ_SIZE.
- */
-static int i2c_xfer_no_retry(const int port,
-			     const uint16_t slave_addr_flags,
-			     const uint8_t *out, int out_size,
-			     uint8_t *in, int in_size, int flags)
-{
-	int ret;
-	int out_flags = flags & I2C_XFER_START;
-	int in_chunk_size = MIN(in_size, CONFIG_I2C_CHIP_MAX_READ_SIZE);
-
-	in_size -= in_chunk_size;
-	out_flags |= !in_size ? (flags & I2C_XFER_STOP) : 0;
-	ret = chip_i2c_xfer_with_notify(port, slave_addr_flags,
-					out, out_size, in,
-					in_chunk_size, out_flags);
-	in += in_chunk_size;
-	while (in_size && ret == EC_SUCCESS) {
-		in_chunk_size = MIN(in_size, CONFIG_I2C_CHIP_MAX_READ_SIZE);
-		in_size -= in_chunk_size;
-		ret = chip_i2c_xfer_with_notify(port, slave_addr_flags,
-			NULL, 0, in,
-			in_chunk_size, !in_size ? (flags & I2C_XFER_STOP) : 0);
-		in += in_chunk_size;
-	}
-	return ret;
-}
-#endif /* CONFIG_I2C_XFER_LARGE_READ */
-
-int i2c_xfer_unlocked(const int port,
-		      const uint16_t slave_addr_flags,
-		      const uint8_t *out, int out_size,
-		      uint8_t *in, int in_size, int flags)
-{
-	int i;
-	int ret = EC_SUCCESS;
-
-	uint16_t addr_flags = slave_addr_flags & ~I2C_FLAG_PEC;
-
-	if (!i2c_port_is_locked(port)) {
-		CPUTS("Access I2C without lock!");
-		return EC_ERROR_INVAL;
-	}
-
-	for (i = 0; i <= CONFIG_I2C_NACK_RETRY_COUNT; i++) {
-#ifdef CONFIG_I2C_XFER_LARGE_READ
-		ret = i2c_xfer_no_retry(port, addr_flags,
-					    out, out_size, in,
-					    in_size, flags);
-#else
-		ret = chip_i2c_xfer_with_notify(port, addr_flags,
-						    out, out_size,
-						    in, in_size, flags);
-#endif /* CONFIG_I2C_XFER_LARGE_READ */
-		if (ret != EC_ERROR_BUSY)
-			break;
-	}
-	return ret;
-}
-
-int i2c_xfer(const int port,
-	     const uint16_t slave_addr_flags,
-	     const uint8_t *out, int out_size,
-	     uint8_t *in, int in_size)
-{
-	int rv;
-
-	i2c_lock(port, 1);
-	rv = i2c_xfer_unlocked(port, slave_addr_flags,
-			       out, out_size, in, in_size,
-			       I2C_XFER_SINGLE);
-	i2c_lock(port, 0);
-
-	return rv;
-}
-
-void i2c_lock(int port, int lock)
-{
-#ifdef CONFIG_I2C_MULTI_PORT_CONTROLLER
-	/* Lock the controller, not the port */
-	port = i2c_port_to_controller(port);
-#endif
-	if (port < 0)
-		return;
-
-	if (lock) {
-		mutex_lock(port_mutex + port);
-
-		/* Disable interrupt during changing counter for preemption. */
-		interrupt_disable();
-
-		i2c_port_active_list |= 1 << port;
-		/* Ec cannot enter sleep if there's any i2c port active. */
-		disable_sleep(SLEEP_MASK_I2C_MASTER);
-
-		interrupt_enable();
-	} else {
-		interrupt_disable();
-
-		i2c_port_active_list &= ~BIT(port);
-		/* Once there is no i2c port active, enable sleep bit of i2c. */
-		if (!i2c_port_active_list)
-			enable_sleep(SLEEP_MASK_I2C_MASTER);
-
-		interrupt_enable();
-
-		mutex_unlock(port_mutex + port);
-	}
-}
-
-void i2c_prepare_sysjump(void)
-{
-	int i;
-
-	/* Lock all i2c controllers */
-	for (i = 0; i < ARRAY_SIZE(port_mutex); ++i)
-		mutex_lock(port_mutex + i);
-}
-
-/* i2c_readN with optional error checking */
-static int i2c_read(const int port, const uint16_t slave_addr_flags,
-			uint8_t reg, uint8_t *in, int in_size)
-{
-	if (!IS_ENABLED(CONFIG_SMBUS_PEC) && I2C_USE_PEC(slave_addr_flags))
-		return EC_ERROR_UNIMPLEMENTED;
-
-	if (IS_ENABLED(CONFIG_SMBUS_PEC) && I2C_USE_PEC(slave_addr_flags)) {
-		int i, rv;
-		/* addr_8bit = 7 bit addr_flags + 1 bit r/w */
-		uint8_t addr_8bit = I2C_GET_ADDR(slave_addr_flags) << 1;
-		uint8_t out[3] = {addr_8bit, reg, addr_8bit | 1};
-		uint8_t pec_local = 0, pec_remote;
-
-		i2c_lock(port, 1);
-		for (i = 0; i <= CONFIG_I2C_NACK_RETRY_COUNT; i++) {
-			rv = i2c_xfer_unlocked(port, slave_addr_flags, &reg, 1,
-					       in, in_size, I2C_XFER_START);
-			if (rv)
-				continue;
-
-			rv = i2c_xfer_unlocked(port, slave_addr_flags, NULL, 0,
-					       &pec_remote, 1, I2C_XFER_STOP);
-			if (rv)
-				continue;
-
-			pec_local = crc8(out, ARRAY_SIZE(out));
-			pec_local = crc8_arg(in, in_size, pec_local);
-			if (pec_local == pec_remote)
-				break;
-
-			rv = EC_ERROR_CRC;
-		}
-		i2c_lock(port, 0);
-
-		return rv;
-	}
-
-	return i2c_xfer(port, slave_addr_flags, &reg, 1, in, in_size);
-}
-
-/* i2c_writeN with optional error checking */
-static int i2c_write(const int port, const uint16_t slave_addr_flags,
-			 const uint8_t *out, int out_size)
-{
-	if (!IS_ENABLED(CONFIG_SMBUS_PEC) && I2C_USE_PEC(slave_addr_flags))
-		return EC_ERROR_UNIMPLEMENTED;
-
-	if (IS_ENABLED(CONFIG_SMBUS_PEC) && I2C_USE_PEC(slave_addr_flags)) {
-		int i, rv;
-		uint8_t addr_8bit = I2C_GET_ADDR(slave_addr_flags) << 1;
-		uint8_t pec;
-
-		pec = crc8(&addr_8bit, 1);
-		pec = crc8_arg(out, out_size, pec);
-
-		i2c_lock(port, 1);
-		for (i = 0; i <= CONFIG_I2C_NACK_RETRY_COUNT; i++) {
-			rv = i2c_xfer_unlocked(port, slave_addr_flags,
-					       out, out_size, NULL, 0,
-					       I2C_XFER_START);
-			if (rv)
-				continue;
-
-			rv = i2c_xfer_unlocked(port, slave_addr_flags,
-					       &pec, 1, NULL, 0,
-					       I2C_XFER_STOP);
-			if (!rv)
-				break;
-		}
-		i2c_lock(port, 0);
-
-		return rv;
-	}
-
-	return i2c_xfer(port, slave_addr_flags, out, out_size, NULL, 0);
-}
-
-int i2c_read32(const int port,
-	       const uint16_t slave_addr_flags,
-	       int offset, int *data)
-{
-	int rv;
-	uint8_t reg, buf[sizeof(uint32_t)];
-
-	reg = offset & 0xff;
-	/* I2C read 32-bit word: transmit 8-bit offset, and read 32bits */
-	rv = i2c_read(port, slave_addr_flags, reg, buf, sizeof(uint32_t));
-
-	if (rv)
-		return rv;
-
-	if (I2C_IS_BIG_ENDIAN(slave_addr_flags))
-		*data = ((int)buf[0] << 24) | ((int)buf[1] << 16) |
-			((int)buf[0] << 8) | buf[1];
-	else
-		*data = ((int)buf[3] << 24) | ((int)buf[2] << 16) |
-			((int)buf[1] << 8) | buf[0];
-
-	return EC_SUCCESS;
-}
-
-int i2c_write32(const int port,
-		const uint16_t slave_addr_flags,
-		int offset, int data)
-{
-	uint8_t buf[1 + sizeof(uint32_t)];
-
-	buf[0] = offset & 0xff;
-
-	if (I2C_IS_BIG_ENDIAN(slave_addr_flags)) {
-		buf[1] = (data >> 24) & 0xff;
-		buf[2] = (data >> 16) & 0xff;
-		buf[3] = (data >> 8) & 0xff;
-		buf[4] = data & 0xff;
-	} else {
-		buf[1] = data & 0xff;
-		buf[2] = (data >> 8) & 0xff;
-		buf[3] = (data >> 16) & 0xff;
-		buf[4] = (data >> 24) & 0xff;
-	}
-
-	return i2c_write(port, slave_addr_flags, buf, sizeof(uint32_t) + 1);
-}
-
-int i2c_read16(const int port,
-	       const uint16_t slave_addr_flags,
-	       int offset, int *data)
-{
-	int rv;
-	uint8_t reg, buf[sizeof(uint16_t)];
-
-	reg = offset & 0xff;
-	/* I2C read 16-bit word: transmit 8-bit offset, and read 16bits */
-	rv = i2c_read(port, slave_addr_flags, reg, buf, sizeof(uint16_t));
-
-	if (rv)
-		return rv;
-
-	if (I2C_IS_BIG_ENDIAN(slave_addr_flags))
-		*data = ((int)buf[0] << 8) | buf[1];
-	else
-		*data = ((int)buf[1] << 8) | buf[0];
-
-	return EC_SUCCESS;
-}
-
-int i2c_write16(const int port,
-		const uint16_t slave_addr_flags,
-		int offset, int data)
-{
-	uint8_t buf[1 + sizeof(uint16_t)];
-
-	buf[0] = offset & 0xff;
-
-	if (I2C_IS_BIG_ENDIAN(slave_addr_flags)) {
-		buf[1] = (data >> 8) & 0xff;
-		buf[2] = data & 0xff;
-	} else {
-		buf[1] = data & 0xff;
-		buf[2] = (data >> 8) & 0xff;
-	}
-
-	return i2c_write(port, slave_addr_flags, buf, 1 + sizeof(uint16_t));
-}
-
-int i2c_read8(const int port,
-	      const uint16_t slave_addr_flags,
-	      int offset, int *data)
-{
-	int rv;
-	uint8_t reg = offset;
-	uint8_t buf;
-
-	reg = offset;
-
-	rv = i2c_read(port, slave_addr_flags, reg, &buf, sizeof(uint8_t));
-	if (!rv)
-		*data = buf;
-
-	return rv;
-}
-
-int i2c_write8(const int port,
-	       const uint16_t slave_addr_flags,
-	       int offset, int data)
-{
-	uint8_t buf[2];
-
-	buf[0] = offset;
-	buf[1] = data;
-
-	return i2c_write(port, slave_addr_flags, buf, sizeof(buf));
-}
-
-int i2c_update8(const int port,
-		const uint16_t slave_addr_flags,
-		const int offset,
-		const uint8_t mask,
-		const enum mask_update_action action)
-{
-	int rv;
-	int read_val;
-	int write_val;
-
-	rv = i2c_read8(port, slave_addr_flags, offset, &read_val);
-	if (rv)
-		return rv;
-
-	write_val = (action == MASK_SET) ? (read_val | mask)
-					 : (read_val & ~mask);
-
-	if (IS_ENABLED(CONFIG_I2C_UPDATE_IF_CHANGED) && write_val == read_val)
-		return EC_SUCCESS;
-
-	return i2c_write8(port, slave_addr_flags, offset, write_val);
-}
-
-int i2c_update16(const int port,
-		 const uint16_t slave_addr_flags,
-		 const int offset,
-		 const uint16_t mask,
-		 const enum mask_update_action action)
-{
-	int rv;
-	int read_val;
-	int write_val;
-
-	rv = i2c_read16(port, slave_addr_flags, offset, &read_val);
-	if (rv)
-		return rv;
-
-	write_val = (action == MASK_SET) ? (read_val | mask)
-					 : (read_val & ~mask);
-
-	if (IS_ENABLED(CONFIG_I2C_UPDATE_IF_CHANGED) && write_val == read_val)
-		return EC_SUCCESS;
-
-	return i2c_write16(port, slave_addr_flags, offset, write_val);
-}
-
-int i2c_field_update8(const int port,
-		      const uint16_t slave_addr_flags,
-		      const int offset,
-		      const uint8_t field_mask,
-		      const uint8_t set_value)
-{
-	int rv;
-	int read_val;
-	int write_val;
-
-	rv = i2c_read8(port, slave_addr_flags, offset, &read_val);
-	if (rv)
-		return rv;
-
-	write_val = (read_val & (~field_mask)) | set_value;
-
-	if (IS_ENABLED(CONFIG_I2C_UPDATE_IF_CHANGED) && write_val == read_val)
-		return EC_SUCCESS;
-
-	return i2c_write8(port, slave_addr_flags, offset, write_val);
-}
-
-int i2c_field_update16(const int port,
-		       const uint16_t slave_addr_flags,
-		       const int offset,
-		       const uint16_t field_mask,
-		       const uint16_t set_value)
-{
-	int rv;
-	int read_val;
-	int write_val;
-
-	rv = i2c_read16(port, slave_addr_flags, offset, &read_val);
-	if (rv)
-		return rv;
-
-	write_val = (read_val & (~field_mask)) | set_value;
-
-	if (IS_ENABLED(CONFIG_I2C_UPDATE_IF_CHANGED) && write_val == read_val)
-		return EC_SUCCESS;
-
-	return i2c_write16(port, slave_addr_flags, offset, write_val);
-}
-
-int i2c_read_offset16(const int port,
-		      const uint16_t slave_addr_flags,
-		      uint16_t offset, int *data, int len)
-{
-	int rv;
-	uint8_t buf[sizeof(uint16_t)], addr[sizeof(uint16_t)];
-
-	if (len < 0 || len > 2)
-		return EC_ERROR_INVAL;
-
-	addr[0] = (offset >> 8) & 0xff;
-	addr[1] = offset & 0xff;
-
-	/* I2C read 16-bit word: transmit 16-bit offset, and read buffer */
-	rv = i2c_xfer(port, slave_addr_flags, addr, 2, buf, len);
-
-	if (rv)
-		return rv;
-
-	if (len == 1) {
-		*data = buf[0];
-	} else {
-		if (I2C_IS_BIG_ENDIAN(slave_addr_flags))
-			*data = ((int)buf[0] << 8) | buf[1];
-		else
-			*data = ((int)buf[1] << 8) | buf[0];
-	}
-
-	return EC_SUCCESS;
-}
-
-int i2c_write_offset16(const int port,
-		       const uint16_t slave_addr_flags,
-		       uint16_t offset, int data, int len)
-{
-	uint8_t buf[2 + sizeof(uint16_t)];
-
-	if (len < 0 || len > 2)
-		return EC_ERROR_INVAL;
-
-	buf[0] = (offset >> 8) & 0xff;
-	buf[1] = offset & 0xff;
-
-	if (len == 1) {
-		buf[2] = data & 0xff;
-	} else {
-		if (I2C_IS_BIG_ENDIAN(slave_addr_flags)) {
-			buf[2] = (data >> 8) & 0xff;
-			buf[3] = data & 0xff;
-		} else {
-			buf[2] = data & 0xff;
-			buf[3] = (data >> 8) & 0xff;
-		}
-	}
-
-	return i2c_xfer(port, slave_addr_flags, buf, 2 + len, NULL, 0);
-}
-
-int i2c_read_offset16_block(const int port,
-			    const uint16_t slave_addr_flags,
-			    uint16_t offset, uint8_t *data, int len)
-{
-	uint8_t addr[sizeof(uint16_t)];
-
-	addr[0] = (offset >> 8) & 0xff;
-	addr[1] = offset & 0xff;
-
-	return i2c_xfer(port, slave_addr_flags, addr, 2, data, len);
-}
-
-int i2c_write_offset16_block(const int port,
-			     const uint16_t slave_addr_flags,
-			     uint16_t offset, const uint8_t *data, int len)
-{
-	int rv;
-	uint8_t addr[sizeof(uint16_t)];
-
-	addr[0] = (offset >> 8) & 0xff;
-	addr[1] = offset & 0xff;
-
-	/*
-	 * Split into two transactions to avoid the stack space consumption of
-	 * appending the destination address with the data array.
-	 */
-	i2c_lock(port, 1);
-	rv = i2c_xfer_unlocked(port, slave_addr_flags, addr, 2, NULL, 0,
-			       I2C_XFER_START);
-	if (!rv)
-		rv = i2c_xfer_unlocked(port, slave_addr_flags,
-				       data, len, NULL, 0, I2C_XFER_STOP);
-	i2c_lock(port, 0);
-
-	return rv;
-}
-
-int i2c_read_string(const int port,
-		    const uint16_t slave_addr_flags,
-		    int offset, uint8_t *data, int len)
-{
-	int i, rv;
-	uint8_t reg, block_length;
-
-	if (!IS_ENABLED(CONFIG_SMBUS_PEC) && I2C_USE_PEC(slave_addr_flags))
-		return EC_ERROR_UNIMPLEMENTED;
-
-	reg = offset;
-	i2c_lock(port, 1);
-
-	for (i = 0; i <= CONFIG_I2C_NACK_RETRY_COUNT; i++) {
-		int data_length;
-
-		/*
-		 * Send device reg space offset, and read back block length.
-		 * Keep this session open without a stop.
-		 */
-		rv = i2c_xfer_unlocked(port, slave_addr_flags,
-				       &reg, 1, &block_length, 1,
-				       I2C_XFER_START);
-		if (rv)
-			continue;
-
-		if (len && block_length > (len - 1))
-			data_length = len - 1;
-		else
-			data_length = block_length;
-
-		if (IS_ENABLED(CONFIG_SMBUS_PEC) &&
-				I2C_USE_PEC(slave_addr_flags)) {
-			uint8_t addr_8bit = I2C_GET_ADDR(slave_addr_flags) << 1;
-			uint8_t out[3] = {addr_8bit, reg, addr_8bit | 1};
-			uint8_t pec, pec_remote;
-
-			rv = i2c_xfer_unlocked(port, slave_addr_flags,
-					       0, 0, data, data_length, 0);
-			data[data_length] = 0;
-			if (rv)
-				continue;
-
-			pec = crc8(out, sizeof(out));
-			pec = crc8_arg(&block_length, 1, pec);
-			pec = crc8_arg(data, data_length, pec);
-
-			/* read all remaining bytes */
-			block_length -= data_length;
-			while (block_length) {
-				uint8_t byte;
-
-				rv = i2c_xfer_unlocked(port, slave_addr_flags,
-						       NULL, 0, &byte, 1, 0);
-				if (rv)
-					break;
-				pec = crc8_arg(&byte, 1, pec);
-				--block_length;
-			}
-			if (rv)
-				continue;
-
-			rv = i2c_xfer_unlocked(port, slave_addr_flags, NULL, 0,
-					       &pec_remote, 1, I2C_XFER_STOP);
-			if (rv)
-				continue;
-
-			if (pec != pec_remote)
-				rv = EC_ERROR_CRC;
-		} else {
-			rv = i2c_xfer_unlocked(port, slave_addr_flags,
-					       0, 0, data, data_length,
-					       I2C_XFER_STOP);
-			data[data_length] = 0;
-			if (rv)
-				continue;
-		}
-
-		/* execution reaches here implies rv=0, so we can exit now */
-		break;
-	}
-
-	i2c_lock(port, 0);
-	return rv;
-}
-
-int i2c_read_block(const int port,
-		   const uint16_t slave_addr_flags,
-		   int offset, uint8_t *data, int len)
-{
-	int rv;
-	uint8_t reg_address = offset;
-
-	rv = i2c_xfer(port, slave_addr_flags, &reg_address, 1, data, len);
-	return rv;
-}
-
-int i2c_write_block(const int port,
-		    const uint16_t slave_addr_flags,
-		    int offset, const uint8_t *data, int len)
-{
-	int i, rv;
-	uint8_t reg_address = offset, pec = 0;
-
-	if (!IS_ENABLED(CONFIG_SMBUS_PEC) && I2C_USE_PEC(slave_addr_flags))
-		return EC_ERROR_UNIMPLEMENTED;
-
-	if (IS_ENABLED(CONFIG_SMBUS_PEC) && I2C_USE_PEC(slave_addr_flags)) {
-		uint8_t addr_8bit = I2C_GET_ADDR(slave_addr_flags) << 1;
-
-		pec = crc8(&addr_8bit, sizeof(uint8_t));
-		pec = crc8_arg(data, len, pec);
-	}
-
-	/*
-	 * Split into two transactions to avoid the stack space consumption of
-	 * appending the destination address with the data array.
-	 */
-	i2c_lock(port, 1);
-	for (i = 0; i <= CONFIG_I2C_NACK_RETRY_COUNT; i++) {
-		rv = i2c_xfer_unlocked(port, slave_addr_flags,
-				       &reg_address, 1, NULL, 0,
-				       I2C_XFER_START);
-		if (rv)
-			continue;
-
-		if (I2C_USE_PEC(slave_addr_flags)) {
-			rv = i2c_xfer_unlocked(port, slave_addr_flags,
-					       data, len, NULL, 0, 0);
-			if (rv)
-				continue;
-
-			rv = i2c_xfer_unlocked(port, slave_addr_flags,
-					       &pec, sizeof(uint8_t), NULL, 0,
-					       I2C_XFER_STOP);
-			if (rv)
-				continue;
-		} else {
-			rv = i2c_xfer_unlocked(port, slave_addr_flags,
-					       data, len, NULL, 0,
-					       I2C_XFER_STOP);
-			if (rv)
-				continue;
-		}
-
-		/* execution reaches here implies rv=0, so we can exit now */
-		break;
-	}
-	i2c_lock(port, 0);
-
-	return rv;
-}
-
-int get_sda_from_i2c_port(int port, enum gpio_signal *sda)
-{
-	const struct i2c_port_t *i2c_port = get_i2c_port(port);
-
-	/* Crash if the port given is not in the i2c_ports[] table. */
-	ASSERT(i2c_port);
-
-	/* Check if the SCL and SDA pins have been defined for this port. */
-	if (i2c_port->scl == 0 && i2c_port->sda == 0)
-		return EC_ERROR_INVAL;
-
-	*sda = i2c_port->sda;
-	return EC_SUCCESS;
-}
-
-int get_scl_from_i2c_port(int port, enum gpio_signal *scl)
-{
-	const struct i2c_port_t *i2c_port = get_i2c_port(port);
-
-	/* Crash if the port given is not in the i2c_ports[] table. */
-	ASSERT(i2c_port);
-
-	/* Check if the SCL and SDA pins have been defined for this port. */
-	if (i2c_port->scl == 0 && i2c_port->sda == 0)
-		return EC_ERROR_INVAL;
-
-	*scl = i2c_port->scl;
-	return EC_SUCCESS;
-}
-
-void i2c_raw_set_scl(int port, int level)
-{
-	enum gpio_signal g;
-
-	if (get_scl_from_i2c_port(port, &g) == EC_SUCCESS)
-		gpio_set_level(g, level);
-}
-
-void i2c_raw_set_sda(int port, int level)
-{
-	enum gpio_signal g;
-
-	if (get_sda_from_i2c_port(port, &g) == EC_SUCCESS)
-		gpio_set_level(g, level);
-}
-
-int i2c_raw_mode(int port, int enable)
-{
-	enum gpio_signal sda, scl;
-	int ret_sda, ret_scl;
-
-	/* Get the SDA and SCL pins for this port. If none, then return. */
-	if (get_sda_from_i2c_port(port, &sda) != EC_SUCCESS)
-		return EC_ERROR_INVAL;
-	if (get_scl_from_i2c_port(port, &scl) != EC_SUCCESS)
-		return EC_ERROR_INVAL;
-
-	if (enable) {
-		int raw_gpio_mode_flags = GPIO_ODR_HIGH;
-
-		/* If the CLK line is 1.8V, then ensure we set 1.8V mode */
-		if ((gpio_list + scl)->flags & GPIO_SEL_1P8V)
-			raw_gpio_mode_flags |= GPIO_SEL_1P8V;
-
-		/*
-		 * To enable raw mode, take out of alternate function mode and
-		 * set the flags to open drain output.
-		 */
-		ret_sda = gpio_config_pin(MODULE_I2C, sda, 0);
-		ret_scl = gpio_config_pin(MODULE_I2C, scl, 0);
-
-		gpio_set_flags(scl, raw_gpio_mode_flags);
-		gpio_set_flags(sda, raw_gpio_mode_flags);
-	} else {
-		/*
-		 * Configure the I2C pins to exit raw mode and return
-		 * to normal mode.
-		 */
-		ret_sda = gpio_config_pin(MODULE_I2C, sda, 1);
-		ret_scl = gpio_config_pin(MODULE_I2C, scl, 1);
-	}
-
-	return ret_sda == EC_SUCCESS ? ret_scl : ret_sda;
-}
-
-
-/*
- * Unwedge the i2c bus for the given port.
- *
- * Some devices on our i2c busses keep power even if we get a reset.  That
- * means that they could be part way through a transaction and could be
- * driving the bus in a way that makes it hard for us to talk on the bus.
- * ...or they might listen to the next transaction and interpret it in a
- * weird way.
- *
- * Note that devices could be in one of several states:
- * - If a device got interrupted in a write transaction it will be watching
- *   for additional data to finish its write.  It will probably be looking to
- *   ack the data (drive the data line low) after it gets everything.
- * - If a device got interrupted while responding to a register read, it will
- *   be watching for clocks and will drive data out when it sees clocks.  At
- *   the moment it might be trying to send out a 1 (so both clock and data
- *   may be high) or it might be trying to send out a 0 (so it's driving data
- *   low).
- *
- * We attempt to unwedge the bus by doing:
- * - If SCL is being held low, then a slave is clock extending. The only
- *   thing we can do is try to wait until the slave stops clock extending.
- * - Otherwise, we will toggle the clock until the slave releases the SDA line.
- *   Once the SDA line is released, try to send a STOP bit. Rinse and repeat
- *   until either the bus is normal, or we run out of attempts.
- *
- * Note this should work for most devices, but depending on the slaves i2c
- * state machine, it may not be possible to unwedge the bus.
- */
-int i2c_unwedge(int port)
-{
-	int i, j;
-	int ret = EC_SUCCESS;
-
-#ifdef CONFIG_I2C_BUS_MAY_BE_UNPOWERED
-	/*
-	 * Don't try to unwedge the port if we know it's unpowered; it's futile.
-	 */
-	if (!board_is_i2c_port_powered(port)) {
-		CPRINTS("Skipping i2c unwedge, bus not powered.");
-		return EC_ERROR_NOT_POWERED;
-	}
-#endif /* CONFIG_I2C_BUS_MAY_BE_UNPOWERED */
-
-	/* Try to put port in to raw bit bang mode. */
-	if (i2c_raw_mode(port, 1) != EC_SUCCESS)
-		return EC_ERROR_UNKNOWN;
-
-	/*
-	 * If clock is low, wait for a while in case of clock stretched
-	 * by a slave.
-	 */
-	if (!i2c_raw_get_scl(port)) {
-		for (i = 0;; i++) {
-			if (i >= UNWEDGE_SCL_ATTEMPTS) {
-				/*
-				 * If we get here, a slave is holding the clock
-				 * low and there is nothing we can do.
-				 */
-				CPRINTS("I2C%d unwedge failed, "
-					"SCL is held low", port);
-				ret = EC_ERROR_UNKNOWN;
-				goto unwedge_done;
-			}
-			udelay(I2C_BITBANG_DELAY_US);
-			if (i2c_raw_get_scl(port))
-				break;
-		}
-	}
-
-	if (i2c_raw_get_sda(port))
-		goto unwedge_done;
-
-	CPRINTS("I2C%d unwedge called with SDA held low", port);
-
-	/* Keep trying to unwedge the SDA line until we run out of attempts. */
-	for (i = 0; i < UNWEDGE_SDA_ATTEMPTS; i++) {
-		/* Drive the clock high. */
-		i2c_raw_set_scl(port, 1);
-		udelay(I2C_BITBANG_DELAY_US);
-
-		/*
-		 * Clock through the problem by clocking out 9 bits. If slave
-		 * releases the SDA line, then we can stop clocking bits and
-		 * send a STOP.
-		 */
-		for (j = 0; j < 9; j++) {
-			if (i2c_raw_get_sda(port))
-				break;
-
-			i2c_raw_set_scl(port, 0);
-			udelay(I2C_BITBANG_DELAY_US);
-			i2c_raw_set_scl(port, 1);
-			udelay(I2C_BITBANG_DELAY_US);
-		}
-
-		/* Take control of SDA line and issue a STOP command. */
-		i2c_raw_set_sda(port, 0);
-		udelay(I2C_BITBANG_DELAY_US);
-		i2c_raw_set_sda(port, 1);
-		udelay(I2C_BITBANG_DELAY_US);
-
-		/* Check if the bus is unwedged. */
-		if (i2c_raw_get_sda(port) && i2c_raw_get_scl(port))
-			break;
-	}
-
-	if (!i2c_raw_get_sda(port)) {
-		CPRINTS("I2C%d unwedge failed, SDA still low", port);
-		ret = EC_ERROR_UNKNOWN;
-	}
-	if (!i2c_raw_get_scl(port)) {
-		CPRINTS("I2C%d unwedge failed, SCL still low", port);
-		ret = EC_ERROR_UNKNOWN;
-	}
-
-unwedge_done:
-	/* Take port out of raw bit bang mode. */
-	i2c_raw_mode(port, 0);
-
-	return ret;
-}
-
-int i2c_set_freq(int port, enum i2c_freq freq)
-{
-	int ret;
-
-	if (!(get_i2c_port(port)->flags & I2C_PORT_FLAG_DYNAMIC_SPEED))
-		return EC_ERROR_INVAL;
-
-	i2c_lock(port, 1);
-	ret = chip_i2c_set_freq(port, freq);
-	i2c_lock(port, 0);
-	return ret;
-}
-
-enum i2c_freq i2c_get_freq(int port)
-{
-	return chip_i2c_get_freq(port);
-}
-
-/*****************************************************************************/
-/* Host commands */
-
-#ifdef CONFIG_I2C_DEBUG_PASSTHRU
-#define PTHRUPRINTS(format, args...) CPRINTS("I2C_PTHRU " format, ## args)
-#define PTHRUPRINTF(format, args...) CPRINTF(format, ## args)
-#else
-#define PTHRUPRINTS(format, args...)
-#define PTHRUPRINTF(format, args...)
-#endif
-
-/**
- * Perform the voluminous checking required for this message
- *
- * @param args	Arguments
- * @return 0 if OK, EC_RES_INVALID_PARAM on error
- */
-static int check_i2c_params(const struct host_cmd_handler_args *args)
-{
-	const struct ec_params_i2c_passthru *params = args->params;
-	const struct ec_params_i2c_passthru_msg *msg;
-	int read_len = 0, write_len = 0;
-	unsigned int size;
-	int msgnum;
-
-	if (args->params_size < sizeof(*params)) {
-		PTHRUPRINTS("no params, params_size=%d, need at least %d",
-			    args->params_size, sizeof(*params));
-		return EC_RES_INVALID_PARAM;
-	}
-	size = sizeof(*params) + params->num_msgs * sizeof(*msg);
-	if (args->params_size < size) {
-		PTHRUPRINTS("params_size=%d, need at least %d",
-			    args->params_size, size);
-		return EC_RES_INVALID_PARAM;
-	}
-
-	/* Loop and process messages */;
-	for (msgnum = 0, msg = params->msg; msgnum < params->num_msgs;
-	     msgnum++, msg++) {
-		unsigned int addr_flags = msg->addr_flags;
-
-		PTHRUPRINTS("port=%d, %s, addr=0x%x(7-bit), len=%d",
-			    params->port,
-			    addr_flags & EC_I2C_FLAG_READ ? "read" : "write",
-			    addr_flags & EC_I2C_ADDR_MASK,
-			    msg->len);
-
-		if (addr_flags & EC_I2C_FLAG_READ)
-			read_len += msg->len;
-		else
-			write_len += msg->len;
-	}
-
-	/* Check there is room for the data */
-	if (args->response_max <
-			sizeof(struct ec_response_i2c_passthru) + read_len) {
-		PTHRUPRINTS("overflow1");
-		return EC_RES_INVALID_PARAM;
-	}
-
-	/* Must have bytes to write */
-	if (args->params_size < size + write_len) {
-		PTHRUPRINTS("overflow2");
-		return EC_RES_INVALID_PARAM;
-	}
-
-	return EC_RES_SUCCESS;
-}
-
-static enum ec_status i2c_command_passthru(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_i2c_passthru *params = args->params;
-	const struct ec_params_i2c_passthru_msg *msg;
-	struct ec_response_i2c_passthru *resp = args->response;
-	const struct i2c_port_t *i2c_port;
-	const uint8_t *out;
-	int in_len;
-	int ret, i;
-	int port_is_locked = 0;
-
-#ifdef CONFIG_BATTERY_CUT_OFF
-	/*
-	 * Some batteries would wake up after cut-off if we talk to it.
-	 */
-	if (battery_is_cut_off())
-		return EC_RES_ACCESS_DENIED;
-#endif
-
-	i2c_port = get_i2c_port(params->port);
-	if (!i2c_port)
-		return EC_RES_INVALID_PARAM;
-
-	ret = check_i2c_params(args);
-	if (ret)
-		return ret;
-
-	if (port_protected[params->port] && i2c_port->passthru_allowed) {
-		for (i = 0; i < params->num_msgs; i++) {
-			if (!i2c_port->passthru_allowed(i2c_port,
-					params->msg[i].addr_flags))
-				return EC_RES_ACCESS_DENIED;
-		}
-	}
-
-	/* Loop and process messages */
-	resp->i2c_status = 0;
-	out = args->params + sizeof(*params) + params->num_msgs * sizeof(*msg);
-	in_len = 0;
-
-	for (resp->num_msgs = 0, msg = params->msg;
-	     resp->num_msgs < params->num_msgs;
-	     resp->num_msgs++, msg++) {
-		int xferflags = I2C_XFER_START;
-		int read_len = 0, write_len = 0;
-		int rv = 1;
-
-		/* Have to remove the EC flags from the address flags */
-		uint16_t addr_flags = msg->addr_flags & EC_I2C_ADDR_MASK;
-
-
-		if (msg->addr_flags & EC_I2C_FLAG_READ)
-			read_len = msg->len;
-		else
-			write_len = msg->len;
-
-		/* Set stop bit for last message */
-		if (resp->num_msgs == params->num_msgs - 1)
-			xferflags |= I2C_XFER_STOP;
-
-#if defined(VIRTUAL_BATTERY_ADDR_FLAGS) && defined(I2C_PORT_VIRTUAL_BATTERY)
-		if (params->port == I2C_PORT_VIRTUAL_BATTERY &&
-		    addr_flags == VIRTUAL_BATTERY_ADDR_FLAGS) {
-			if (virtual_battery_handler(resp, in_len, &rv,
-						xferflags, read_len,
-						write_len, out))
-				break;
-		}
-#endif
-		/* Transfer next message */
-		PTHRUPRINTS("xfer port=%x addr=0x%x rlen=%d flags=0x%x",
-			    params->port, addr_flags,
-			    read_len, xferflags);
-		if (write_len) {
-			PTHRUPRINTF("  out:");
-			for (i = 0; i < write_len; i++)
-				PTHRUPRINTF(" 0x%02x", out[i]);
-			PTHRUPRINTF("\n");
-		}
-		if (rv) {
-#ifdef CONFIG_I2C_PASSTHRU_RESTRICTED
-			if (system_is_locked() &&
-			    !board_allow_i2c_passthru(params->port)) {
-				if (port_is_locked)
-					i2c_lock(params->port, 0);
-				return EC_RES_ACCESS_DENIED;
-			}
-#endif
-			if (!port_is_locked)
-				i2c_lock(params->port, (port_is_locked = 1));
-			rv = i2c_xfer_unlocked(params->port,
-					       addr_flags,
-					       out, write_len,
-					       &resp->data[in_len], read_len,
-					       xferflags);
-		}
-
-		if (rv) {
-			/* Driver will have sent a stop bit here */
-			if (rv == EC_ERROR_TIMEOUT)
-				resp->i2c_status = EC_I2C_STATUS_TIMEOUT;
-			else
-				resp->i2c_status = EC_I2C_STATUS_NAK;
-			break;
-		}
-
-		in_len += read_len;
-		out += write_len;
-	}
-	args->response_size = sizeof(*resp) + in_len;
-
-	/* Unlock port */
-	if (port_is_locked)
-		i2c_lock(params->port, 0);
-
-	/*
-	 * Return success even if transfer failed so response is sent.  Host
-	 * will check message status to determine the transfer result.
-	 */
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_I2C_PASSTHRU, i2c_command_passthru, EC_VER_MASK(0));
-
-static void i2c_passthru_protect_port(uint32_t port)
-{
-	if (port < ARRAY_SIZE(port_protected))
-		port_protected[port] = 1;
-	else
-		PTHRUPRINTS("Invalid I2C port %d to be protected\n", port);
-}
-
-static void i2c_passthru_protect_tcpc_ports(void)
-{
-#ifdef CONFIG_USB_PD_PORT_MAX_COUNT
-	int i;
-
-	/*
-	 * If WP is not enabled i.e. system is not locked leave the tunnels open
-	 * so that factory line can do updates without a new RO BIOS.
-	 */
-	if (!system_is_locked()) {
-		CPRINTS("System unlocked, TCPC I2C tunnels may be unprotected");
-		return;
-	}
-
-	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
-		/* TCPC tunnel not configured. No need to protect anything */
-		if (!I2C_GET_ADDR(tcpc_config[i].i2c_info.addr_flags))
-			continue;
-		i2c_passthru_protect_port(tcpc_config[i].i2c_info.port);
-	}
-#endif
-}
-
-static enum ec_status
-i2c_command_passthru_protect(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_i2c_passthru_protect *params = args->params;
-	struct ec_response_i2c_passthru_protect *resp = args->response;
-
-	if (args->params_size < sizeof(*params)) {
-		PTHRUPRINTS("protect no params, params_size=%d, ",
-			    args->params_size);
-		return EC_RES_INVALID_PARAM;
-	}
-
-	/*
-	 * When calling the subcmd to protect all tcpcs, the i2c port isn't
-	 * expected to be set in the args. So, putting a check here to avoid
-	 * the get_i2c_port return error.
-	 */
-	if (params->subcmd == EC_CMD_I2C_PASSTHRU_PROTECT_ENABLE_TCPCS) {
-		if (IS_ENABLED(CONFIG_USB_POWER_DELIVERY) &&
-				!IS_ENABLED(CONFIG_USB_PD_TCPM_STUB))
-			i2c_passthru_protect_tcpc_ports();
-		return EC_RES_SUCCESS;
-	}
-
-	if (!get_i2c_port(params->port)) {
-		PTHRUPRINTS("protect invalid port %d", params->port);
-		return EC_RES_INVALID_PARAM;
-	}
-
-	if (params->subcmd == EC_CMD_I2C_PASSTHRU_PROTECT_STATUS) {
-		if (args->response_max < sizeof(*resp)) {
-			PTHRUPRINTS("protect no response, "
-					"response_max=%d, need at least %d",
-					args->response_max, sizeof(*resp));
-			return EC_RES_INVALID_PARAM;
-		}
-
-		resp->status = port_protected[params->port];
-		args->response_size = sizeof(*resp);
-	} else if (params->subcmd == EC_CMD_I2C_PASSTHRU_PROTECT_ENABLE) {
-		i2c_passthru_protect_port(params->port);
-	} else {
-		return EC_RES_INVALID_COMMAND;
-	}
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_I2C_PASSTHRU_PROTECT, i2c_command_passthru_protect,
-		     EC_VER_MASK(0));
-
-/*****************************************************************************/
-/* Console commands */
-
-#ifdef CONFIG_CMD_I2C_PROTECT
-static int command_i2cprotect(int argc, char **argv)
-{
-	if (argc == 1) {
-		int i, port;
-
-		for (i = 0; i < i2c_ports_used; i++) {
-			port = i2c_ports[i].port;
-			ccprintf("Port %d: %s\n", port,
-			   port_protected[port] ? "Protected" : "Unprotected");
-		}
-	} else if (argc == 2) {
-		int port;
-		char *e;
-
-		port = strtoi(argv[1], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM2;
-
-		if (!get_i2c_port(port)) {
-			ccprintf("i2c passthru protect invalid port %d\n",
-				port);
-			return EC_RES_INVALID_PARAM;
-		}
-
-		port_protected[port] = 1;
-	} else {
-		return EC_ERROR_PARAM_COUNT;
-	}
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(i2cprotect, command_i2cprotect,
-			"[port]",
-			"Protect I2C bus");
-#endif
-
-#ifdef CONFIG_CMD_I2C_SCAN
-static void scan_bus(int port, const char *desc)
-{
-	int level;
-	uint8_t tmp;
-	uint16_t addr_flags;
-
-	ccprintf("Scanning %d %s", port, desc);
-
-	i2c_lock(port, 1);
-
-	/* Don't scan a busy port, since reads will just fail / time out */
-	level = i2c_get_line_levels(port);
-	if (level != I2C_LINE_IDLE) {
-		ccprintf(": port busy (SDA=%d, SCL=%d)",
-			 (level & I2C_LINE_SDA_HIGH) ? 1 : 0,
-			 (level & I2C_LINE_SCL_HIGH) ? 1 : 0);
-		goto scan_bus_exit;
-	}
-	/*
-	 * Only scan in the valid client device address range, otherwise some
-	 * client devices stretch the clock in weird ways that prevent the
-	 * discovery of other devices.
-	 */
-	for (addr_flags = I2C_FIRST_VALID_ADDR;
-	     addr_flags <= I2C_LAST_VALID_ADDR; ++addr_flags) {
-		watchdog_reload();  /* Otherwise a full scan trips watchdog */
-		ccputs(".");
-
-		/* Do a single read */
-		if (!i2c_xfer_unlocked(port, addr_flags,
-				       NULL, 0, &tmp, 1, I2C_XFER_SINGLE))
-			ccprintf("\n  0x%02x", addr_flags);
-	}
-
-scan_bus_exit:
-	i2c_lock(port, 0);
-	ccputs("\n");
-}
-
-static int command_scan(int argc, char **argv)
-{
-	int port;
-	char *e;
-	const struct i2c_port_t *i2c_port;
-
-	if (argc == 1) {
-		for (port = 0; port < i2c_ports_used; port++)
-			scan_bus(i2c_ports[port].port, i2c_ports[port].name);
-
-		if (IS_ENABLED(CONFIG_I2C_BITBANG))
-			for (port = 0; port < i2c_bitbang_ports_used; port++)
-				scan_bus(i2c_bitbang_ports[port].port,
-					 i2c_bitbang_ports[port].name);
-
-		return EC_SUCCESS;
-	}
-
-
-	port = strtoi(argv[1], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM2;
-
-	i2c_port = get_i2c_port(port);
-	if (!i2c_port)
-		return EC_ERROR_PARAM2;
-
-	scan_bus(port, i2c_port->name);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(i2cscan, command_scan,
-			"i2cscan [port]",
-			"Scan I2C ports for devices");
-#endif
-
-#ifdef CONFIG_CMD_I2C_XFER
-static int command_i2cxfer(int argc, char **argv)
-{
-	int port;
-	uint16_t addr_flags;
-	uint16_t offset = 0;
-	uint8_t offset_size = 0;
-	int v = 0;
-	uint8_t data[32];
-	char *e;
-	int rv = 0;
-
-	if (argc < 5)
-		return EC_ERROR_PARAM_COUNT;
-
-	port = strtoi(argv[2], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM2;
-
-	addr_flags = strtoi(argv[3], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM3;
-
-	offset = strtoi(argv[4], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM4;
-
-	offset_size = (strlen(argv[4]) == 6) ? 2 : 1;
-
-	if (argc >= 6) {
-		v = strtoi(argv[5], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM5;
-	}
-
-	if (strcasecmp(argv[1], "r") == 0) {
-		/* 8-bit read */
-		if (offset_size == 2)
-			rv = i2c_read_offset16(port, addr_flags,
-					       offset, &v, 1);
-		else
-			rv = i2c_read8(port, addr_flags,
-				       offset, &v);
-		if (!rv)
-			ccprintf("0x%02x [%d]\n", v, v);
-
-	} else if (strcasecmp(argv[1], "r16") == 0) {
-		/* 16-bit read */
-		if (offset_size == 2)
-			rv = i2c_read_offset16(port, addr_flags,
-					       offset, &v, 2);
-		else
-			rv = i2c_read16(port, addr_flags,
-					offset, &v);
-		if (!rv)
-			ccprintf("0x%04x [%d]\n", v, v);
-
-	} else if (strcasecmp(argv[1], "rlen") == 0) {
-		/* Arbitrary length read; param5 = len */
-		if (argc < 6 || v < 0 || v > sizeof(data))
-			return EC_ERROR_PARAM5;
-
-		rv = i2c_xfer(port, addr_flags,
-			      (uint8_t *)&offset, 1, data, v);
-
-		if (!rv)
-			ccprintf("Data: %ph\n", HEX_BUF(data, v));
-
-	} else if (strcasecmp(argv[1], "w") == 0) {
-		/* 8-bit write */
-		if (argc < 6)
-			return EC_ERROR_PARAM5;
-		if (offset_size == 2)
-			rv = i2c_write_offset16(port, addr_flags,
-						offset, v, 1);
-		else
-			rv = i2c_write8(port, addr_flags,
-					offset, v);
-
-	} else if (strcasecmp(argv[1], "w16") == 0) {
-		/* 16-bit write */
-		if (argc < 6)
-			return EC_ERROR_PARAM5;
-		if (offset_size == 2)
-			rv = i2c_write_offset16(port, addr_flags,
-						offset, v, 2);
-		else
-			rv = i2c_write16(port, addr_flags,
-					 offset, v);
-
-	} else {
-		return EC_ERROR_PARAM1;
-	}
-
-	return rv;
-}
-DECLARE_CONSOLE_COMMAND(i2cxfer, command_i2cxfer,
-			"r/r16/rlen/w/w16 port addr offset [value | len]",
-			"Read write I2C");
-#endif
-
-#ifdef CONFIG_CMD_I2C_STRESS_TEST
-static void i2c_test_status(struct i2c_test_results *i2c_test, int test_dev)
-{
-	ccprintf("test_dev=%2d, ", test_dev);
-	ccprintf("r=%5d, rs=%5d, rf=%5d, ",
-		i2c_test->read_success + i2c_test->read_fail,
-		i2c_test->read_success,
-		i2c_test->read_fail);
-
-	ccprintf("w=%5d, ws=%5d, wf=%5d\n",
-		i2c_test->write_success + i2c_test->write_fail,
-		i2c_test->write_success,
-		i2c_test->write_fail);
-
-	i2c_test->read_success = 0;
-	i2c_test->read_fail = 0;
-	i2c_test->write_success = 0,
-	i2c_test->write_fail = 0;
-}
-
-#define I2C_STRESS_TEST_DATA_VERIFY_RETRY_COUNT 3
-static int command_i2ctest(int argc, char **argv)
-{
-	char *e;
-	int i, j, rv;
-	uint32_t rand;
-	int data, data_verify;
-	int count = 10000;
-	int udelay = 100;
-	int test_dev = i2c_test_dev_used;
-	struct i2c_stress_test_dev *i2c_s_test = NULL;
-	struct i2c_test_reg_info *reg_s_info;
-	struct i2c_test_results *test_s_results;
-
-	if (argc > 1) {
-		count = strtoi(argv[1], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM2;
-	}
-
-	if (argc > 2) {
-		udelay = strtoi(argv[2], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM3;
-	}
-
-	if (argc > 3) {
-		test_dev = strtoi(argv[3], &e, 0);
-		if (*e || test_dev < 1 || test_dev > i2c_test_dev_used)
-			return EC_ERROR_PARAM4;
-		test_dev--;
-	}
-
-	for (i = 0; i < count; i++) {
-		int port;
-		uint16_t addr_flags;
-
-		if (!(i % 1000))
-			ccprintf("running test %d\n", i);
-
-		if (argc < 4) {
-			rand = get_time().val;
-			test_dev = rand % i2c_test_dev_used;
-		}
-
-		port = i2c_stress_tests[test_dev].port;
-		addr_flags = i2c_stress_tests[test_dev].addr_flags;
-		i2c_s_test = i2c_stress_tests[test_dev].i2c_test;
-		reg_s_info = &i2c_s_test->reg_info;
-		test_s_results = &i2c_s_test->test_results;
-
-		rand = get_time().val;
-		if (rand & 0x1) {
-			/* read */
-			rv = i2c_s_test->i2c_read ?
-				i2c_s_test->i2c_read(port, addr_flags,
-					reg_s_info->read_reg, &data) :
-				i2c_s_test->i2c_read_dev(
-					reg_s_info->read_reg, &data);
-			if (rv || data != reg_s_info->read_val)
-				test_s_results->read_fail++;
-			else
-				test_s_results->read_success++;
-		} else {
-			/*
-			 * Reads are more than writes in the system.
-			 * Read and then write same value to ensure we are
-			 * not changing any settings.
-			 */
-
-			/* Read the write register */
-			rv = i2c_s_test->i2c_read ?
-				i2c_s_test->i2c_read(port, addr_flags,
-					reg_s_info->read_reg, &data) :
-				i2c_s_test->i2c_read_dev(
-					reg_s_info->read_reg, &data);
-			if (rv) {
-				/* Skip writing invalid data */
-				test_s_results->read_fail++;
-				continue;
-			} else
-				test_s_results->read_success++;
-
-			j = I2C_STRESS_TEST_DATA_VERIFY_RETRY_COUNT;
-			do {
-				/* Write same value back */
-				rv = i2c_s_test->i2c_write ?
-					i2c_s_test->i2c_write(port,
-					addr_flags,
-					reg_s_info->write_reg, data) :
-					i2c_s_test->i2c_write_dev(
-					reg_s_info->write_reg, data);
-				i++;
-				if (rv) {
-					/* Skip reading as write failed */
-					test_s_results->write_fail++;
-					break;
-				}
-				test_s_results->write_success++;
-
-				/* Read back to verify the data */
-				rv = i2c_s_test->i2c_read ?
-					i2c_s_test->i2c_read(port,
-					addr_flags,
-					reg_s_info->read_reg, &data_verify) :
-					i2c_s_test->i2c_read_dev(
-					reg_s_info->read_reg, &data_verify);
-				i++;
-				if (rv) {
-					/* Read failed try next time */
-					test_s_results->read_fail++;
-					break;
-				} else if (!rv && data != data_verify) {
-					/* Either data writes/read is wrong */
-					j--;
-				} else {
-					j = 0;
-					test_s_results->read_success++;
-				}
-			} while (j);
-		}
-
-		usleep(udelay);
-	}
-
-	ccprintf("\n**********final result **********\n");
-
-	cflush();
-	if (argc > 3) {
-		i2c_test_status(&i2c_s_test->test_results, test_dev + 1);
-	} else {
-		for (i = 0; i < i2c_test_dev_used; i++) {
-			i2c_s_test = i2c_stress_tests[i].i2c_test;
-			i2c_test_status(&i2c_s_test->test_results, i + 1);
-			msleep(100);
-		}
-	}
-	cflush();
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(i2ctest, command_i2ctest,
-			"i2ctest count|udelay|dev",
-			"I2C stress test");
-#endif /* CONFIG_CMD_I2C_STRESS_TEST */
diff --git a/common/i2c_peripheral.c b/common/i2c_peripheral.c
new file mode 100644
index 0000000000..26e46175b4
--- /dev/null
+++ b/common/i2c_peripheral.c
@@ -0,0 +1,33 @@
+/* Copyright 2017 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* I2C peripheral cross-platform code for Chrome EC */
+
+#include "host_command.h"
+#include "i2c.h"
+#include "util.h"
+
+/**
+ * Command handler to get host command protocol information
+ *
+ * @param args:	host command handler arguments
+ * @return	EC_SUCCESS
+ */
+static enum ec_status i2c_get_protocol_info(struct host_cmd_handler_args *args)
+{
+	struct ec_response_get_protocol_info *r = args->response;
+
+	memset(r, 0, sizeof(*r));
+	r->protocol_versions = BIT(3);
+	r->max_request_packet_size = I2C_MAX_HOST_PACKET_SIZE;
+	r->max_response_packet_size = I2C_MAX_HOST_PACKET_SIZE;
+	r->flags = 0;
+
+	args->response_size = sizeof(*r);
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, i2c_get_protocol_info,
+		     EC_VER_MASK(0));
diff --git a/common/i2c_slave.c b/common/i2c_slave.c
deleted file mode 100644
index 7e710b2ef4..0000000000
--- a/common/i2c_slave.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* I2C slave cross-platform code for Chrome EC */
-
-#include "host_command.h"
-#include "i2c.h"
-#include "util.h"
-
-enum ec_status i2c_get_protocol_info(struct host_cmd_handler_args *args)
-{
-	struct ec_response_get_protocol_info *r = args->response;
-
-	memset(r, 0, sizeof(*r));
-	r->protocol_versions = BIT(3);
-	r->max_request_packet_size = I2C_MAX_HOST_PACKET_SIZE;
-	r->max_response_packet_size = I2C_MAX_HOST_PACKET_SIZE;
-	r->flags = 0;
-
-	args->response_size = sizeof(*r);
-
-	return EC_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO,
-		     i2c_get_protocol_info,
-		     EC_VER_MASK(0));
diff --git a/common/i2c_trace.c b/common/i2c_trace.c
index 340de901f9..8532766ea8 100644
--- a/common/i2c_trace.c
+++ b/common/i2c_trace.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,35 +6,34 @@
 #include "common.h"
 #include "console.h"
 #include "i2c.h"
-#include "stddef.h"
 #include "stdbool.h"
+#include "stddef.h"
 #include "util.h"
 
 #define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args)
 
 struct i2c_trace_range {
 	bool enabled;
 	int port;
-	int slave_addr_lo; /* Inclusive */
-	int slave_addr_hi; /* Inclusive */
+	int addr_lo; /* Inclusive */
+	int addr_hi; /* Inclusive */
 };
 
 static struct i2c_trace_range trace_entries[8];
 
-void i2c_trace_notify(int port, uint16_t slave_addr_flags,
-		      const uint8_t *out_data, size_t out_size,
-		      const uint8_t *in_data, size_t in_size)
+void i2c_trace_notify(int port, uint16_t addr_flags, const uint8_t *out_data,
+		      size_t out_size, const uint8_t *in_data, size_t in_size,
+		      int ret)
 {
 	size_t i;
-	uint16_t addr = I2C_GET_ADDR(slave_addr_flags);
+	uint16_t addr = I2C_STRIP_FLAGS(addr_flags);
 
 	for (i = 0; i < ARRAY_SIZE(trace_entries); i++)
-		if (trace_entries[i].enabled
-		    && trace_entries[i].port == port
-		    && trace_entries[i].slave_addr_lo <= addr
-		    && trace_entries[i].slave_addr_hi >= addr)
+		if (trace_entries[i].enabled && trace_entries[i].port == port &&
+		    trace_entries[i].addr_lo <= addr &&
+		    trace_entries[i].addr_hi >= addr)
 			goto trace_enabled;
 	return;
 
@@ -45,7 +44,9 @@ void i2c_trace_notify(int port, uint16_t slave_addr_flags,
 		for (i = 0; i < out_size; i++)
 			CPRINTF("0x%02X ", out_data[i]);
 	}
-	if (in_size) {
+	if (ret != EC_SUCCESS) {
+		CPRINTF(" error: %d", ret);
+	} else if (in_size) {
 		CPRINTF("  rd ");
 		for (i = 0; i < in_size; i++)
 			CPRINTF("0x%02X ", in_data[i]);
@@ -64,15 +65,16 @@ static int command_i2ctrace_list(void)
 	for (i = 0; i < ARRAY_SIZE(trace_entries); i++) {
 		if (trace_entries[i].enabled) {
 			i2c_port = get_i2c_port(trace_entries[i].port);
-			ccprintf("%-2zd %d %-8s 0x%X",
-				 i,
-				 trace_entries[i].port,
-				 i2c_port->name,
-				 trace_entries[i].slave_addr_lo);
-			if (trace_entries[i].slave_addr_hi
-			    != trace_entries[i].slave_addr_lo)
-				ccprintf(" to 0x%X",
-					 trace_entries[i].slave_addr_hi);
+			ccprintf("%-2zd %d %-8s 0x%X", i, trace_entries[i].port,
+#ifndef CONFIG_ZEPHYR
+				 i2c_port ? i2c_port->name : "invalid",
+#else
+				 "",
+#endif /* CONFIG_ZEPHYR */
+				 trace_entries[i].addr_lo);
+			if (trace_entries[i].addr_hi !=
+			    trace_entries[i].addr_lo)
+				ccprintf(" to 0x%X", trace_entries[i].addr_hi);
 			ccprintf("\n");
 		}
 	}
@@ -89,8 +91,7 @@ static int command_i2ctrace_disable(size_t id)
 	return EC_SUCCESS;
 }
 
-static int command_i2ctrace_enable(int port, int slave_addr_lo,
-				   int slave_addr_hi)
+static int command_i2ctrace_enable(int port, int addr_lo, int addr_hi)
 {
 	struct i2c_trace_range *t;
 	struct i2c_trace_range *new_entry = NULL;
@@ -98,48 +99,41 @@ static int command_i2ctrace_enable(int port, int slave_addr_lo,
 	if (!get_i2c_port(port))
 		return EC_ERROR_PARAM2;
 
-	if (slave_addr_lo > slave_addr_hi)
+	if (addr_lo > addr_hi)
 		return EC_ERROR_PARAM3;
 
 	/*
 	 * Scan thru existing entries to see if there is one we can
 	 * extend instead of making a new entry
 	 */
-	for (t = trace_entries;
-	     t < trace_entries + ARRAY_SIZE(trace_entries);
+	for (t = trace_entries; t < trace_entries + ARRAY_SIZE(trace_entries);
 	     t++) {
 		if (t->enabled && t->port == port) {
 			/* Subset of existing range, do nothing */
-			if (t->slave_addr_lo <= slave_addr_lo &&
-			    t->slave_addr_hi >= slave_addr_hi)
+			if (t->addr_lo <= addr_lo && t->addr_hi >= addr_hi)
 				return EC_SUCCESS;
 
 			/* Extends exising range on both directions, replace */
-			if (t->slave_addr_lo >= slave_addr_lo &&
-			    t->slave_addr_hi <= slave_addr_hi) {
+			if (t->addr_lo >= addr_lo && t->addr_hi <= addr_hi) {
 				t->enabled = 0;
-				return command_i2ctrace_enable(
-					port, slave_addr_lo, slave_addr_hi);
+				return command_i2ctrace_enable(port, addr_lo,
+							       addr_hi);
 			}
 
 			/* Extends existing range below */
-			if (t->slave_addr_lo - 1 <= slave_addr_hi &&
-			    t->slave_addr_hi >= slave_addr_hi) {
+			if (t->addr_lo - 1 <= addr_hi &&
+			    t->addr_hi >= addr_hi) {
 				t->enabled = 0;
-				return command_i2ctrace_enable(
-					port,
-					slave_addr_lo,
-					t->slave_addr_hi);
+				return command_i2ctrace_enable(port, addr_lo,
+							       t->addr_hi);
 			}
 
 			/* Extends existing range above */
-			if (t->slave_addr_lo <= slave_addr_lo &&
-			    t->slave_addr_hi + 1 >= slave_addr_lo) {
+			if (t->addr_lo <= addr_lo &&
+			    t->addr_hi + 1 >= addr_lo) {
 				t->enabled = 0;
-				return command_i2ctrace_enable(
-					port,
-					t->slave_addr_lo,
-					slave_addr_hi);
+				return command_i2ctrace_enable(port, t->addr_lo,
+							       addr_hi);
 			}
 		} else if (!t->enabled && !new_entry) {
 			new_entry = t;
@@ -150,8 +144,8 @@ static int command_i2ctrace_enable(int port, int slave_addr_lo,
 	if (new_entry) {
 		new_entry->enabled = 1;
 		new_entry->port = port;
-		new_entry->slave_addr_lo = slave_addr_lo;
-		new_entry->slave_addr_hi = slave_addr_hi;
+		new_entry->addr_lo = addr_lo;
+		new_entry->addr_hi = addr_hi;
 		return EC_SUCCESS;
 	}
 
@@ -159,8 +153,7 @@ static int command_i2ctrace_enable(int port, int slave_addr_lo,
 	return EC_ERROR_MEMORY_ALLOCATION;
 }
 
-
-static int command_i2ctrace(int argc, char **argv)
+static int command_i2ctrace(int argc, const char **argv)
 {
 	int id_or_port;
 	int address_low;
@@ -198,14 +191,13 @@ static int command_i2ctrace(int argc, char **argv)
 			return EC_ERROR_PARAM_COUNT;
 		}
 
-		return command_i2ctrace_enable(
-			id_or_port, address_low, address_high);
+		return command_i2ctrace_enable(id_or_port, address_low,
+					       address_high);
 	}
 
 	return EC_ERROR_PARAM1;
 }
-DECLARE_CONSOLE_COMMAND(i2ctrace,
-			command_i2ctrace,
+DECLARE_CONSOLE_COMMAND(i2ctrace, command_i2ctrace,
 			"[list | disable <id> | enable <port> <address> | "
 			"enable <port> <address-low> <address-high>]",
 			"Trace I2C transactions");
diff --git a/common/i2c_wedge.c b/common/i2c_wedge.c
index ef87234cce..23e3f6ceae 100644
--- a/common/i2c_wedge.c
+++ b/common/i2c_wedge.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,7 +10,7 @@
  * pit:
  *
  * #define CONFIG_CMD_I2CWEDGE
- * #define I2C_PORT_HOST I2C_PORT_MASTER
+ * #define I2C_PORT_HOST I2C_PORT_CONTROLLER
  *
  */
 
@@ -117,7 +117,7 @@ static int i2c_bang_in_bit(void)
 {
 	int bit;
 
-	/* Let the slave drive data */
+	/* Let the peripheral drive data */
 	i2c_raw_set_sda(I2C_PORT_HOST, 1);
 	i2c_bang_delay();
 
@@ -134,10 +134,10 @@ static int i2c_bang_in_bit(void)
 	return bit;
 }
 
-/* Write a byte to I2C bus. Return 0 if ack by the slave. */
+/* Write a byte to I2C bus. Return 0 if ack by the peripheral. */
 static int i2c_bang_out_byte(int send_start, int send_stop, unsigned char byte)
 {
-	unsigned bit;
+	unsigned int bit;
 	int nack;
 	int tmp = byte;
 
@@ -178,19 +178,19 @@ static void i2c_bang_init(void)
 	i2c_raw_mode(I2C_PORT_HOST, 1);
 }
 
-static void i2c_bang_xfer(int slave_addr, int reg)
+static void i2c_bang_xfer(int addr, int reg)
 {
 	int byte;
 
 	i2c_bang_init();
 
-	/* State a write command to 'slave_addr' */
-	i2c_bang_out_byte(1 /*start*/, 0 /*stop*/, slave_addr);
+	/* State a write command to 'addr' */
+	i2c_bang_out_byte(1 /*start*/, 0 /*stop*/, addr);
 	/* Write 'reg' */
 	i2c_bang_out_byte(0 /*start*/, 0 /*stop*/, reg);
 
 	/* Start a read command */
-	i2c_bang_out_byte(1 /*start*/, 0 /*stop*/, slave_addr | 1);
+	i2c_bang_out_byte(1 /*start*/, 0 /*stop*/, addr | 1);
 
 	/* Read two bytes */
 	byte = i2c_bang_in_byte(0, 0); /* ack and no stop */
@@ -199,15 +199,14 @@ static void i2c_bang_xfer(int slave_addr, int reg)
 	ccprintf("  read byte: %d\n", byte);
 }
 
-static void i2c_bang_wedge_write(int slave_addr, int byte, int bit_count,
-	int reboot)
+static void i2c_bang_wedge_write(int addr, int byte, int bit_count, int reboot)
 {
 	int i;
 
 	i2c_bang_init();
 
-	/* State a write command to 'slave_addr' */
-	i2c_bang_out_byte(1 /*start*/, 0 /*stop*/, slave_addr);
+	/* State a write command to 'addr' */
+	i2c_bang_out_byte(1 /*start*/, 0 /*stop*/, addr);
 	/* Send a few bits and stop */
 	for (i = 0; i < bit_count; ++i) {
 		i2c_bang_out_bit((byte & 0x80) != 0);
@@ -219,20 +218,19 @@ static void i2c_bang_wedge_write(int slave_addr, int byte, int bit_count,
 		system_reset(0);
 }
 
-static void i2c_bang_wedge_read(int slave_addr, int reg, int bit_count,
-	int reboot)
+static void i2c_bang_wedge_read(int addr, int reg, int bit_count, int reboot)
 {
 	int i;
 
 	i2c_bang_init();
 
-	/* State a write command to 'slave_addr' */
-	i2c_bang_out_byte(1 /*start*/, 0 /*stop*/, slave_addr);
+	/* State a write command to 'addr' */
+	i2c_bang_out_byte(1 /*start*/, 0 /*stop*/, addr);
 	/* Write 'reg' */
 	i2c_bang_out_byte(0 /*start*/, 0 /*stop*/, reg);
 
 	/* Start a read command */
-	i2c_bang_out_byte(1 /*start*/, 0 /*stop*/, slave_addr | 1);
+	i2c_bang_out_byte(1 /*start*/, 0 /*stop*/, addr | 1);
 
 	/* Read bit_count bits and stop */
 	for (i = 0; i < bit_count; ++i)
@@ -244,36 +242,36 @@ static void i2c_bang_wedge_read(int slave_addr, int reg, int bit_count,
 		system_reset(0);
 }
 
-#define WEDGE_WRITE	1
-#define WEDGE_READ	2
-#define WEDGE_REBOOT	4
+#define WEDGE_WRITE 1
+#define WEDGE_READ 2
+#define WEDGE_REBOOT 4
 
-static int command_i2c_wedge(int argc, char **argv)
+static int command_i2c_wedge(int argc, const char **argv)
 {
-	int slave_addr, reg, wedge_flag = 0, wedge_bit_count = -1;
+	int addr, reg, wedge_flag = 0, wedge_bit_count = -1;
 	char *e;
 	enum gpio_signal tmp;
 
 	/* Verify that the I2C_PORT_HOST has SDA and SCL pins defined. */
 	if (get_sda_from_i2c_port(I2C_PORT_HOST, &tmp) != EC_SUCCESS ||
-		get_scl_from_i2c_port(I2C_PORT_HOST, &tmp) != EC_SUCCESS) {
+	    get_scl_from_i2c_port(I2C_PORT_HOST, &tmp) != EC_SUCCESS) {
 		ccprintf("Cannot wedge bus because no SCL and SDA pins are"
-			"defined for this port. Check i2c_ports[].\n");
+			 "defined for this port. Check i2c_ports[].\n");
 		return EC_SUCCESS;
 	}
 
 	if (argc < 3) {
-		ccputs("Usage: i2cwedge slave_addr out_byte "
-			"[wedge_flag [wedge_bit_count]]\n");
+		ccputs("Usage: i2cwedge addr out_byte "
+		       "[wedge_flag [wedge_bit_count]]\n");
 		ccputs("  wedge_flag - (1: wedge out; 2: wedge in;"
-			" 5: wedge out+reboot; 6: wedge in+reboot)]\n");
+		       " 5: wedge out+reboot; 6: wedge in+reboot)]\n");
 		ccputs("  wedge_bit_count - 0 to 8\n");
 		return EC_ERROR_UNKNOWN;
 	}
 
-	slave_addr = strtoi(argv[1], &e, 0);
+	addr = strtoi(argv[1], &e, 0);
 	if (*e) {
-		ccprintf("Invalid slave_addr %s\n", argv[1]);
+		ccprintf("Invalid addr %s\n", argv[1]);
 		return EC_ERROR_INVAL;
 	}
 	reg = strtoi(argv[2], &e, 0);
@@ -301,15 +299,15 @@ static int command_i2c_wedge(int argc, char **argv)
 	if (wedge_flag & WEDGE_WRITE) {
 		if (wedge_bit_count < 0)
 			wedge_bit_count = 8;
-		i2c_bang_wedge_write(slave_addr, reg, wedge_bit_count,
-			(wedge_flag & WEDGE_REBOOT));
+		i2c_bang_wedge_write(addr, reg, wedge_bit_count,
+				     (wedge_flag & WEDGE_REBOOT));
 	} else if (wedge_flag & WEDGE_READ) {
 		if (wedge_bit_count < 0)
 			wedge_bit_count = 2;
-		i2c_bang_wedge_read(slave_addr, reg, wedge_bit_count,
-			(wedge_flag & WEDGE_REBOOT));
+		i2c_bang_wedge_read(addr, reg, wedge_bit_count,
+				    (wedge_flag & WEDGE_REBOOT));
 	} else {
-		i2c_bang_xfer(slave_addr, reg);
+		i2c_bang_xfer(addr, reg);
 	}
 
 	/* Put it back into normal mode */
@@ -325,17 +323,15 @@ static int command_i2c_wedge(int argc, char **argv)
 	return EC_SUCCESS;
 }
 DECLARE_CONSOLE_COMMAND(i2cwedge, command_i2c_wedge,
-			"i2cwedge slave_addr out_byte "
-				"[wedge_flag [wedge_bit_count]]",
+			"i2cwedge addr out_byte "
+			"[wedge_flag [wedge_bit_count]]",
 			"Wedge host I2C bus");
 
-static int command_i2c_unwedge(int argc, char **argv)
+static int command_i2c_unwedge(int argc, const char **argv)
 {
 	i2c_unwedge(I2C_PORT_HOST);
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(i2cunwedge, command_i2c_unwedge,
-	"",
-	"Unwedge host I2C bus");
-
+DECLARE_CONSOLE_COMMAND(i2cunwedge, command_i2c_unwedge, "",
+			"Unwedge host I2C bus");
diff --git a/common/inductive_charging.c b/common/inductive_charging.c
index 793f535afe..9700e37dcc 100644
--- a/common/inductive_charging.c
+++ b/common/inductive_charging.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/common/init_rom.c b/common/init_rom.c
index fd796f7fe9..ad9e80f423 100644
--- a/common/init_rom.c
+++ b/common/init_rom.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,8 +7,8 @@
 
 #include "builtin/assert.h"
 #include "common.h"
-#include "init_rom.h"
 #include "flash.h"
+#include "init_rom.h"
 #include "stdbool.h"
 #include "stddef.h"
 
@@ -43,11 +43,11 @@ const void *init_rom_map(const void *addr, int size)
 	/*
 	 * Convert flash offset to memory mapped address
 	 */
-	if (flash_dataptr((int)offset, size, 1, &src) < 0)
+	if (crec_flash_dataptr((int)offset, size, 1, &src) < 0)
 		return NULL;
 
 	/* Once the flash offset is validated, lock the flash for the caller */
-	flash_lock_mapped_storage(1);
+	crec_flash_lock_mapped_storage(1);
 
 	return src;
 }
@@ -59,11 +59,10 @@ const void *init_rom_map(const void *addr, int size)
 void init_rom_unmap(const void *addr, int size)
 {
 	if (IS_ENABLED(CONFIG_CHIP_INIT_ROM_REGION))
-		flash_lock_mapped_storage(0);
+		crec_flash_lock_mapped_storage(0);
 }
 
 int init_rom_copy(int offset, int size, char *data)
 {
-	return flash_read(offset, size, data);
+	return crec_flash_read(offset, size, data);
 }
-
diff --git a/common/ioexpander.c b/common/ioexpander.c
index c5c06ee8e1..0a08f37c46 100644
--- a/common/ioexpander.c
+++ b/common/ioexpander.c
@@ -1,38 +1,19 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* IO Expander Controller Common Code */
 
-#include "console.h"
+#include "builtin/assert.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "ioexpander.h"
 #include "system.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_GPIO, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
-
-static uint8_t last_val[(IOEX_COUNT + 7) / 8];
-
-static int last_val_changed(enum ioex_signal signal, int v)
-{
-	const int i = signal - IOEX_SIGNAL_START;
-
-	ASSERT(signal_is_ioex(signal));
-
-	if (v && !(last_val[i / 8] & (BIT(i % 8)))) {
-		last_val[i / 8] |= BIT(i % 8);
-		return 1;
-	} else if (!v && last_val[i / 8] & (BIT(i % 8))) {
-		last_val[i / 8] &= ~(BIT(i % 8));
-		return 1;
-	} else {
-		return 0;
-	}
-}
+#define CPRINTF(format, args...) cprintf(CC_GPIO, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
 
 int signal_is_ioex(int signal)
 {
@@ -47,7 +28,7 @@ static const struct ioex_info *ioex_get_signal_info(enum ioex_signal signal)
 
 	g = ioex_list + signal - IOEX_SIGNAL_START;
 
-	if (ioex_config[g->ioex].flags & IOEX_FLAGS_DISABLED) {
+	if (!(ioex_config[g->ioex].flags & IOEX_FLAGS_INITIALIZED)) {
 		CPRINTS("ioex %s disabled", g->name);
 		return NULL;
 	}
@@ -79,6 +60,7 @@ static int ioex_is_valid_interrupt_signal(enum ioex_signal signal)
 
 	return EC_SUCCESS;
 }
+
 int ioex_enable_interrupt(enum ioex_signal signal)
 {
 	int rv;
@@ -87,7 +69,7 @@ int ioex_enable_interrupt(enum ioex_signal signal)
 
 	rv = ioex_is_valid_interrupt_signal(signal);
 	if (rv != EC_SUCCESS)
-		return  rv;
+		return rv;
 
 	drv = ioex_config[g->ioex].drv;
 	return drv->enable_interrupt(g->ioex, g->port, g->mask, 1);
@@ -101,12 +83,24 @@ int ioex_disable_interrupt(enum ioex_signal signal)
 
 	rv = ioex_is_valid_interrupt_signal(signal);
 	if (rv != EC_SUCCESS)
-		return  rv;
+		return rv;
 
 	drv = ioex_config[g->ioex].drv;
 	return drv->enable_interrupt(g->ioex, g->port, g->mask, 0);
 }
 
+int ioex_get_ioex_flags(enum ioex_signal signal, int *val)
+{
+	const struct ioex_info *g = ioex_get_signal_info(signal);
+
+	if (g == NULL)
+		return EC_ERROR_BUSY;
+
+	*val = ioex_config[g->ioex].flags;
+
+	return EC_SUCCESS;
+}
+
 int ioex_get_flags(enum ioex_signal signal, int *flags)
 {
 	const struct ioex_info *g = ioex_get_signal_info(signal);
@@ -114,8 +108,8 @@ int ioex_get_flags(enum ioex_signal signal, int *flags)
 	if (g == NULL)
 		return EC_ERROR_BUSY;
 
-	return ioex_config[g->ioex].drv->get_flags_by_mask(g->ioex,
-						g->port, g->mask, flags);
+	return ioex_config[g->ioex].drv->get_flags_by_mask(g->ioex, g->port,
+							   g->mask, flags);
 }
 
 int ioex_set_flags(enum ioex_signal signal, int flags)
@@ -125,8 +119,8 @@ int ioex_set_flags(enum ioex_signal signal, int flags)
 	if (g == NULL)
 		return EC_ERROR_BUSY;
 
-	return ioex_config[g->ioex].drv->set_flags_by_mask(g->ioex,
-						g->port, g->mask, flags);
+	return ioex_config[g->ioex].drv->set_flags_by_mask(g->ioex, g->port,
+							   g->mask, flags);
 }
 
 int ioex_get_level(enum ioex_signal signal, int *val)
@@ -136,8 +130,8 @@ int ioex_get_level(enum ioex_signal signal, int *val)
 	if (g == NULL)
 		return EC_ERROR_BUSY;
 
-	return ioex_config[g->ioex].drv->get_level(g->ioex, g->port,
-							g->mask, val);
+	return ioex_config[g->ioex].drv->get_level(g->ioex, g->port, g->mask,
+						   val);
 }
 
 int ioex_set_level(enum ioex_signal signal, int value)
@@ -147,8 +141,72 @@ int ioex_set_level(enum ioex_signal signal, int value)
 	if (g == NULL)
 		return EC_ERROR_BUSY;
 
-	return ioex_config[g->ioex].drv->set_level(g->ioex, g->port,
-							g->mask, value);
+	return ioex_config[g->ioex].drv->set_level(g->ioex, g->port, g->mask,
+						   value);
+}
+
+#ifdef CONFIG_IO_EXPANDER_SUPPORT_GET_PORT
+int ioex_get_port(int ioex, int port, int *val)
+{
+	if (ioex_config[ioex].drv->get_port == NULL)
+		return EC_ERROR_UNIMPLEMENTED;
+
+	return ioex_config[ioex].drv->get_port(ioex, port, val);
+}
+#endif
+
+int ioex_save_gpio_state(int ioex, int *state, int state_len)
+{
+	int rv;
+	const struct ioex_info *g = ioex_list;
+	const struct ioexpander_drv *drv = ioex_config[ioex].drv;
+	int state_offset = 0;
+
+	for (int i = 0; i < IOEX_COUNT; i++, g++) {
+		if (g->ioex != ioex)
+			continue;
+
+		if (state_offset >= state_len) {
+			CPRINTS("%s state buffer is too small", __func__);
+			return EC_ERROR_UNKNOWN;
+		}
+
+		rv = drv->get_flags_by_mask(g->ioex, g->port, g->mask,
+					    &state[state_offset++]);
+		if (rv) {
+			CPRINTS("%s failed to get flags rv=%d", __func__, rv);
+			return rv;
+		}
+	}
+
+	return EC_SUCCESS;
+}
+
+int ioex_restore_gpio_state(int ioex, const int *state, int state_len)
+{
+	int rv;
+	const struct ioex_info *g = ioex_list;
+	const struct ioexpander_drv *drv = ioex_config[ioex].drv;
+	int state_offset = 0;
+
+	for (int i = 0; i < IOEX_COUNT; i++, g++) {
+		if (g->ioex != ioex)
+			continue;
+
+		if (state_offset >= state_len) {
+			CPRINTS("%s state buffer is too small", __func__);
+			return EC_ERROR_UNKNOWN;
+		}
+
+		rv = drv->set_flags_by_mask(g->ioex, g->port, g->mask,
+					    state[state_offset++]);
+		if (rv) {
+			CPRINTS("%s failed to set flags rv=%d", __func__, rv);
+			return rv;
+		}
+	}
+
+	return EC_SUCCESS;
 }
 
 int ioex_init(int ioex)
@@ -158,9 +216,6 @@ int ioex_init(int ioex)
 	int rv;
 	int i;
 
-	if (ioex_config[ioex].flags & IOEX_FLAGS_DISABLED)
-		return EC_ERROR_BUSY;
-
 	if (drv->init != NULL) {
 		rv = drv->init(ioex);
 		if (rv != EC_SUCCESS)
@@ -179,11 +234,14 @@ int ioex_init(int ioex)
 			if (system_jumped_late())
 				flags &= ~(GPIO_LOW | GPIO_HIGH);
 
-			drv->set_flags_by_mask(g->ioex, g->port,
-						g->mask, flags);
+			drv->set_flags_by_mask(g->ioex, g->port, g->mask,
+					       flags);
 		}
 	}
 
+	ioex_config[ioex].flags &= ~IOEX_FLAGS_DEFAULT_INIT_DISABLED;
+	ioex_config[ioex].flags |= IOEX_FLAGS_INITIALIZED;
+
 	return EC_SUCCESS;
 }
 
@@ -191,8 +249,17 @@ static void ioex_init_default(void)
 {
 	int i;
 
-	for (i = 0; i < CONFIG_IO_EXPANDER_PORT_COUNT; i++)
+	for (i = 0; i < CONFIG_IO_EXPANDER_PORT_COUNT; i++) {
+		/*
+		 * If the IO Expander has been initialized or if the default
+		 * initialization is disabled, skip initializing.
+		 */
+		if (ioex_config[i].flags &
+		    (IOEX_FLAGS_INITIALIZED | IOEX_FLAGS_DEFAULT_INIT_DISABLED))
+			continue;
+
 		ioex_init(i);
+	}
 }
 DECLARE_HOOK(HOOK_INIT, ioex_init_default, HOOK_PRIO_INIT_I2C + 1);
 
@@ -202,126 +269,3 @@ const char *ioex_get_name(enum ioex_signal signal)
 
 	return g->name;
 }
-
-static void print_ioex_info(enum ioex_signal signal)
-{
-	int changed, v, val;
-	int flags = 0;
-	const struct ioex_info *g = ioex_list + signal - IOEX_SIGNAL_START;
-
-	if (ioex_config[g->ioex].flags & IOEX_FLAGS_DISABLED) {
-		ccprintf("  DISABLED %s\n", ioex_get_name(signal));
-		return;
-	}
-
-
-	v = ioex_get_level(signal, &val);
-	if (v) {
-		ccprintf("Fail to get %s level\n", ioex_get_name(signal));
-		return;
-	}
-	v = ioex_get_flags(signal, &flags);
-	if (v) {
-		ccprintf("Fail to get %s flags\n", ioex_get_name(signal));
-		return;
-	}
-
-	changed = last_val_changed(signal, val);
-
-	ccprintf("  %d%c %s%s%s%s%s%s\n", val,
-		 (changed ? '*' : ' '),
-		 (flags & GPIO_INPUT ? "I " : ""),
-		 (flags & GPIO_OUTPUT ? "O " : ""),
-		 (flags & GPIO_LOW ? "L " : ""),
-		 (flags & GPIO_HIGH ? "H " : ""),
-		 (flags & GPIO_OPEN_DRAIN ? "ODR " : ""),
-		ioex_get_name(signal));
-
-	/* Flush console to avoid truncating output */
-	cflush();
-}
-
-static int ioex_get_default_flags(enum ioex_signal signal)
-{
-	const struct ioex_info *g = ioex_get_signal_info(signal);
-
-	if (g == NULL)
-		return 0;
-
-	return g->flags;
-}
-
-/* IO expander commands */
-static enum ioex_signal find_ioex_by_name(const char *name)
-{
-	int i;
-
-	if (!name)
-		return -1;
-
-	for (i = IOEX_SIGNAL_START; i < IOEX_SIGNAL_END; i++) {
-		if (!strcasecmp(name, ioex_get_name(i)))
-			return i;
-	}
-
-	return -1;
-}
-
-static enum ec_error_list ioex_set(const char *name, int value)
-{
-	enum ioex_signal signal = find_ioex_by_name(name);
-
-	if (signal == -1)
-		return EC_ERROR_INVAL;
-
-	if (!(ioex_get_default_flags(signal) & GPIO_OUTPUT))
-		return EC_ERROR_INVAL;
-
-	return ioex_set_level(signal, value);
-}
-
-static int command_ioex_set(int argc, char **argv)
-{
-	char *e;
-	int v;
-
-	if (argc < 3)
-		return EC_ERROR_PARAM_COUNT;
-
-	v = strtoi(argv[2], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM2;
-
-	if (ioex_set(argv[1], v) != EC_SUCCESS)
-		return EC_ERROR_PARAM1;
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(ioexset, command_ioex_set,
-			"name <0 | 1>",
-			"Set level of a IO expander IO");
-
-static int command_ioex_get(int argc, char **argv)
-{
-	int i;
-
-	/* If a signal is specified, print only that one */
-	if (argc == 2) {
-		i = find_ioex_by_name(argv[1]);
-		if (i == -1)
-			return EC_ERROR_PARAM1;
-		print_ioex_info(i);
-
-		return EC_SUCCESS;
-	}
-
-	/* Otherwise print them all */
-	for (i = IOEX_SIGNAL_START; i < IOEX_SIGNAL_END; i++)
-		print_ioex_info(i);
-
-	return EC_SUCCESS;
-}
-DECLARE_SAFE_CONSOLE_COMMAND(ioexget, command_ioex_get,
-			     "[name]",
-			     "Read level of IO expander pin(s)");
-
diff --git a/common/ioexpander_commands.c b/common/ioexpander_commands.c
new file mode 100644
index 0000000000..38ab82565a
--- /dev/null
+++ b/common/ioexpander_commands.c
@@ -0,0 +1,144 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "builtin/assert.h"
+#include "console.h"
+#include "gpio.h"
+#include "ioexpander.h"
+#include "util.h"
+
+static uint8_t last_val[(IOEX_COUNT + 7) / 8];
+
+static int last_val_changed(enum ioex_signal signal, int v)
+{
+	const int i = signal - IOEX_SIGNAL_START;
+
+	ASSERT(signal_is_ioex(signal));
+
+	if (v && !(last_val[i / 8] & (BIT(i % 8)))) {
+		last_val[i / 8] |= BIT(i % 8);
+		return 1;
+	} else if (!v && last_val[i / 8] & (BIT(i % 8))) {
+		last_val[i / 8] &= ~(BIT(i % 8));
+		return 1;
+	} else {
+		return 0;
+	}
+}
+
+static enum ioex_signal find_ioex_by_name(const char *name)
+{
+	enum ioex_signal signal;
+
+	if (!name)
+		return IOEX_SIGNAL_END;
+
+	for (signal = IOEX_SIGNAL_START; signal < IOEX_SIGNAL_END; signal++) {
+		if (!strcasecmp(name, ioex_get_name(signal)))
+			return signal;
+	}
+
+	return IOEX_SIGNAL_END;
+}
+
+static void print_ioex_info(enum ioex_signal signal)
+{
+	int changed, v, val;
+	int flags = 0;
+
+	if (ioex_get_ioex_flags(signal, &flags)) {
+		ccprintf("  ERROR getting flags\n");
+		return;
+	}
+
+	if (!(flags & IOEX_FLAGS_INITIALIZED)) {
+		ccprintf("  DISABLED %s\n", ioex_get_name(signal));
+		return;
+	}
+
+	v = ioex_get_level(signal, &val);
+	if (v) {
+		ccprintf("Fail to get %s level\n", ioex_get_name(signal));
+		return;
+	}
+	v = ioex_get_flags(signal, &flags);
+	if (v) {
+		ccprintf("Fail to get %s flags\n", ioex_get_name(signal));
+		return;
+	}
+
+	changed = last_val_changed(signal, val);
+
+	ccprintf("  %d%c %s%s%s%s%s%s\n", val, (changed ? '*' : ' '),
+		 (flags & GPIO_INPUT ? "I " : ""),
+		 (flags & GPIO_OUTPUT ? "O " : ""),
+		 (flags & GPIO_LOW ? "L " : ""),
+		 (flags & GPIO_HIGH ? "H " : ""),
+		 (flags & GPIO_OPEN_DRAIN ? "ODR " : ""),
+		 ioex_get_name(signal));
+
+	/* Flush console to avoid truncating output */
+	cflush();
+}
+
+static enum ec_error_list ioex_set(const char *name, int value)
+{
+	enum ioex_signal signal = find_ioex_by_name(name);
+	int flags;
+
+	if (!signal_is_ioex(signal))
+		return EC_ERROR_INVAL;
+
+	if (ioex_get_flags(signal, &flags))
+		return EC_ERROR_INVAL;
+
+	if (!(flags & GPIO_OUTPUT))
+		return EC_ERROR_INVAL;
+
+	return ioex_set_level(signal, value);
+}
+
+static int command_ioex_set(int argc, const char **argv)
+{
+	char *e;
+	int v;
+
+	if (argc < 3)
+		return EC_ERROR_PARAM_COUNT;
+
+	v = strtoi(argv[2], &e, 0);
+	if (*e)
+		return EC_ERROR_PARAM2;
+
+	if (ioex_set(argv[1], v) != EC_SUCCESS)
+		return EC_ERROR_PARAM1;
+
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(ioexset, command_ioex_set, "name <0 | 1>",
+			"Set level of a IO expander pin");
+
+static int command_ioex_get(int argc, const char **argv)
+{
+	enum ioex_signal signal;
+
+	/* If a signal is specified, print only that one */
+	if (argc == 2) {
+		signal = find_ioex_by_name(argv[1]);
+		if (!signal_is_ioex(signal))
+			return EC_ERROR_PARAM1;
+		print_ioex_info(signal);
+
+		return EC_SUCCESS;
+	}
+
+	/* Otherwise print them all */
+	for (signal = IOEX_SIGNAL_START; signal < IOEX_SIGNAL_END; signal++)
+		print_ioex_info(signal);
+
+	return EC_SUCCESS;
+}
+DECLARE_SAFE_CONSOLE_COMMAND(ioexget, command_ioex_get, "[name]",
+			     "Read level of IO expander pin(s)");
diff --git a/common/irq_locking.c b/common/irq_locking.c
new file mode 100644
index 0000000000..1146145c5e
--- /dev/null
+++ b/common/irq_locking.c
@@ -0,0 +1,32 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * This file is used for platform/ec implementations of irq_lock and irq_unlock
+ * which are defined by Zephyr.
+ */
+
+#include "task.h"
+#include "util.h"
+
+static uint32_t lock_count;
+
+uint32_t irq_lock(void)
+{
+	interrupt_disable();
+	return lock_count++;
+}
+
+void irq_unlock(uint32_t key)
+{
+	lock_count = key;
+
+	/*
+	 * Since we're allowing nesting locks, we only actually want to release
+	 * the lock if the lock count reached 0.
+	 */
+	if (lock_count == 0)
+		interrupt_enable();
+}
diff --git a/common/kasa.c b/common/kasa.c
index 79c75ad55b..0ab716c729 100644
--- a/common/kasa.c
+++ b/common/kasa.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,6 +6,7 @@
 #include "common.h"
 #include "kasa.h"
 #include "mat44.h"
+
 #include <string.h>
 
 void kasa_reset(struct kasa_fit *kasa)
diff --git a/common/keyboard_8042.c b/common/keyboard_8042.c
index 4e3a5b4b98..26b424dd0f 100644
--- a/common/keyboard_8042.c
+++ b/common/keyboard_8042.c
@@ -1,12 +1,14 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * 8042 keyboard protocol
  */
 
-#include "chipset.h"
+#include "atkbd_protocol.h"
+#include "builtin/assert.h"
 #include "button.h"
+#include "chipset.h"
 #include "common.h"
 #include "console.h"
 #include "device_event.h"
@@ -28,28 +30,39 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_KEYBOARD, outstr)
-#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ##args)
 
 #ifdef CONFIG_KEYBOARD_DEBUG
 #define CPUTS5(outstr) cputs(CC_KEYBOARD, outstr)
-#define CPRINTS5(format, args...) cprints(CC_KEYBOARD, format, ## args)
+#define CPRINTS5(format, args...) cprints(CC_KEYBOARD, format, ##args)
 #else
 #define CPUTS5(outstr)
 #define CPRINTS5(format, args...)
 #endif
 
+/*
+ * This command needs malloc to work. Could we use this instead?
+ *
+ * #define CMD_KEYBOARD_LOG IS_ENABLED(CONFIG_MALLOC)
+ */
+#ifdef CONFIG_MALLOC
+#define CMD_KEYBOARD_LOG 1
+#else
+#define CMD_KEYBOARD_LOG 0
+#endif
+
 static enum {
-	STATE_NORMAL = 0,
-	STATE_SCANCODE,
-	STATE_SETLEDS,
-	STATE_EX_SETLEDS_1,		/* Expect 2-byte parameter */
-	STATE_EX_SETLEDS_2,
-	STATE_WRITE_CMD_BYTE,
-	STATE_WRITE_OUTPUT_PORT,
-	STATE_ECHO_MOUSE,
-	STATE_SETREP,
-	STATE_SEND_TO_MOUSE,
-} data_port_state = STATE_NORMAL;
+	STATE_ATKBD_CMD = 0,
+	STATE_ATKBD_SCANCODE,
+	STATE_ATKBD_SETLEDS,
+	STATE_ATKBD_EX_SETLEDS_1, /* Expect 2-byte parameter */
+	STATE_ATKBD_EX_SETLEDS_2,
+	STATE_8042_WRITE_CMD_BYTE,
+	STATE_8042_WRITE_OUTPUT_PORT,
+	STATE_8042_ECHO_MOUSE,
+	STATE_ATKBD_SETREP,
+	STATE_8042_SEND_TO_MOUSE,
+} data_port_state = STATE_ATKBD_CMD;
 
 enum scancode_set_list {
 	SCANCODE_GET_SET = 0,
@@ -64,16 +77,30 @@ enum scancode_set_list {
 /* Number of bytes host can get behind before we start generating extra IRQs */
 #define KB_TO_HOST_RETRIES 3
 
+/*
+ * Timeout for SETLEDS command. Kernel is supposed to send the second byte
+ * within this period. When timeout occurs, the second byte is received as
+ * 'Unsupported AT keyboard command 0x00' (or 0x04). You can evaluate your
+ * timeout is too long or too short by calculating the duration between 'KB
+ * SETLEDS' and 'Unsupported AT...'.
+ */
+#define SETLEDS_TIMEOUT (30 * MSEC)
+
 /*
  * Mutex to control write access to the to-host buffer head.  Don't need to
  * mutex the tail because reads are only done in one place.
  */
-static struct mutex to_host_mutex;
+K_MUTEX_DEFINE(to_host_mutex);
+
+#if defined(CONFIG_PLATFORM_EC_CUSTOMIZED_DESIGN)
+K_MUTEX_DEFINE(from_host_mutex);
+#endif
 
 /* Queue command/data to the host */
 enum {
 	CHAN_KBD = 0,
 	CHAN_AUX,
+	CHAN_CMD,
 };
 struct data_byte {
 	uint8_t chan;
@@ -81,6 +108,7 @@ struct data_byte {
 };
 
 static struct queue const to_host = QUEUE_NULL(16, struct data_byte);
+static struct queue const to_host_cmd = QUEUE_NULL(16, struct data_byte);
 
 /* Queue command/data from the host */
 enum {
@@ -112,9 +140,12 @@ static int i8042_keyboard_irq_enabled;
 static int i8042_aux_irq_enabled;
 
 /* i8042 global settings */
-static int keyboard_enabled;	/* default the keyboard is disabled. */
-static int aux_chan_enabled;	/* default the mouse is disabled. */
-static int keystroke_enabled;	/* output keystrokes */
+#ifdef CONFIG_BOARD_AZALEA
+static bool to_host_queue_paused;
+#endif
+static int keyboard_enabled; /* default the keyboard is disabled. */
+static int aux_chan_enabled; /* default the mouse is disabled. */
+static int keystroke_enabled; /* output keystrokes */
 static uint8_t resend_command[MAX_SCAN_CODE_LEN];
 static uint8_t resend_command_len;
 static uint8_t controller_ram_address;
@@ -142,15 +173,16 @@ static enum scancode_set_list scancode_set = SCANCODE_SET_2;
  *   the inter-char delay = (2 ** B) * (D + 8) / 240 (sec)
  * Default: 500ms delay, 10.9 chars/sec.
  */
-#define DEFAULT_TYPEMATIC_VALUE (BIT(5) | BIT(3) | (3 << 0))
+#define DEFAULT_TYPEMATIC_VALUE (BIT(5) | (3 << 0))
 static uint8_t typematic_value_from_host;
 static int typematic_first_delay;
 static int typematic_inter_delay;
-static int typematic_len;  /* length of typematic_scan_code */
+static int typematic_len; /* length of typematic_scan_code */
 static uint8_t typematic_scan_code[MAX_SCAN_CODE_LEN];
 static timestamp_t typematic_deadline;
+static timestamp_t setleds_deadline;
 
-#define KB_SYSJUMP_TAG 0x4b42  /* "KB" */
+#define KB_SYSJUMP_TAG 0x4b42 /* "KB" */
 #define KB_HOOK_VERSION 2
 /* the previous keyboard state before reboot_ec. */
 struct kb_state {
@@ -163,24 +195,22 @@ struct kb_state {
 /* Keyboard event log */
 
 /* Log the traffic between EC and host -- for debug only */
-#define MAX_KBLOG 512  /* Max events in keyboard log */
+#define MAX_KBLOG 512 /* Max events in keyboard log */
 
 struct kblog_t {
 	/*
 	 * Type:
 	 *
-	 * s = byte enqueued to send to host
 	 * a = aux byte enqueued to send to host
-	 * t = to-host queue tail pointer before type='s' bytes enqueued
-	 *
-	 * d = data byte from host
 	 * c = command byte from host
-	 *
-	 * k = to-host queue head pointer before byte dequeued
-	 * K = byte actually sent to host via LPC
-	 * A = byte actually sent to host via LPC as AUX
-	 *
+	 * d = data byte from host
+	 * r = typematic
+	 * s = byte enqueued to send to host
+	 * t = to-host queue tail pointer before type='s' bytes enqueued
+	 * u = byte enqueued to send to host with priority
 	 * x = to_host queue was cleared
+	 * A = byte actually sent to host via LPC as AUX
+	 * K = byte actually sent to host via LPC
 	 *
 	 * The to-host head and tail pointers are logged pre-wrapping to the
 	 * queue size.  This means that they continually increment as units
@@ -191,8 +221,8 @@ struct kblog_t {
 	uint8_t byte;
 };
 
-static struct kblog_t *kblog_buf;	/* Log buffer; NULL if not logging */
-static int kblog_len;			/* Current log length */
+static struct kblog_t *kblog_buf; /* Log buffer; NULL if not logging */
+static int kblog_len; /* Current log length */
 
 /**
  * Add event to keyboard log.
@@ -215,9 +245,17 @@ void keyboard_host_write(int data, int is_cmd)
 	h.type = is_cmd ? HOST_COMMAND : HOST_DATA;
 	h.byte = data;
 	queue_add_unit(&from_host, &h);
+#if defined(CONFIG_THIRD_PARTY_CUSTOMIZED_DESIGN)
+	lpc_kbc_ibf_clear();
+#endif
 	task_wake(TASK_ID_KEYPROTO);
 }
 
+int keyboard_host_write_avaliable(void)
+{
+	return queue_space(&from_host);
+}
+
 /**
  * Enable keyboard IRQ generation.
  *
@@ -252,11 +290,11 @@ static void aux_enable_irq(int enable)
  * host cannot read the previous byte away in time.
  *
  * @param len		Number of bytes to send to the host
- * @param to_host	Data to send
+ * @param bytes		Data to send
  * @param chan		Channel to send data on
  */
-static void i8042_send_to_host(int len, const uint8_t *bytes,
-			       uint8_t chan)
+static void i8042_send_to_host(int len, const uint8_t *bytes, uint8_t chan,
+			       int is_typematic)
 {
 	int i;
 	struct data_byte data;
@@ -264,15 +302,34 @@ static void i8042_send_to_host(int len, const uint8_t *bytes,
 	/* Enqueue output data if there's space */
 	mutex_lock(&to_host_mutex);
 
-	for (i = 0; i < len; i++)
-		kblog_put(chan == CHAN_AUX ? 'a' : 's', bytes[i]);
+	if (is_typematic && !typematic_len) {
+		for (i = 0; i < len; i++)
+			kblog_put('r', bytes[i]);
+	} else {
+		struct queue const *queue = &to_host;
+
+		if (chan == CHAN_CMD)
+			queue = &to_host_cmd;
 
-	if (queue_space(&to_host) >= len) {
-		kblog_put('t', to_host.state->tail);
 		for (i = 0; i < len; i++) {
-			data.chan = chan;
-			data.byte = bytes[i];
-			queue_add_unit(&to_host, &data);
+			char type;
+
+			if (chan == CHAN_AUX)
+				type = 'a';
+			else if (chan == CHAN_CMD)
+				type = 'u';
+			else
+				type = 's';
+			kblog_put(type, bytes[i]);
+		}
+
+		if (queue_space(queue) >= len) {
+			kblog_put('t', queue->state->tail);
+			for (i = 0; i < len; i++) {
+				data.chan = chan;
+				data.byte = bytes[i];
+				queue_add_unit(queue, &data);
+			}
 		}
 	}
 	mutex_unlock(&to_host_mutex);
@@ -353,8 +410,8 @@ static enum ec_error_list matrix_callback(int8_t row, int8_t col,
 
 #ifdef CONFIG_KEYBOARD_SCANCODE_CALLBACK
 	{
-		enum ec_error_list r = keyboard_scancode_callback(
-				&make_code, pressed);
+		enum ec_error_list r =
+			keyboard_scancode_callback(&make_code, pressed);
 		if (r != EC_SUCCESS)
 			return r;
 	}
@@ -381,14 +438,14 @@ static enum ec_error_list matrix_callback(int8_t row, int8_t col,
 static void set_typematic_delays(uint8_t data)
 {
 	typematic_value_from_host = data;
-	typematic_first_delay = MSEC *
-		(((typematic_value_from_host & 0x60) >> 5) + 1) * 250;
-	typematic_inter_delay = SECOND *
-		(1 << ((typematic_value_from_host & 0x18) >> 3)) *
+	typematic_first_delay =
+		MSEC * (((typematic_value_from_host & 0x60) >> 5) + 1) * 250;
+	typematic_inter_delay =
+		SECOND * (1 << ((typematic_value_from_host & 0x18) >> 3)) *
 		((typematic_value_from_host & 0x7) + 8) / 240;
 }
 
-static void reset_rate_and_delay(void)
+test_export_static void reset_rate_and_delay(void)
 {
 	set_typematic_delays(DEFAULT_TYPEMATIC_VALUE);
 }
@@ -399,6 +456,7 @@ void keyboard_clear_buffer(void)
 	mutex_lock(&to_host_mutex);
 	kblog_put('x', queue_count(&to_host));
 	queue_init(&to_host);
+	queue_init(&to_host_cmd);
 	mutex_unlock(&to_host_mutex);
 	lpc_keyboard_clear_buffer();
 }
@@ -408,7 +466,7 @@ static void keyboard_wakeup(void)
 	host_set_single_event(EC_HOST_EVENT_KEY_PRESSED);
 }
 
-static void set_typematic_key(const uint8_t *scan_code, int32_t len)
+test_export_static void set_typematic_key(const uint8_t *scan_code, int32_t len)
 {
 	typematic_deadline.val = get_time().val + typematic_first_delay;
 	memcpy(typematic_scan_code, scan_code, len);
@@ -427,11 +485,12 @@ void keyboard_state_changed(int row, int col, int is_pressed)
 	enum ec_error_list ret;
 
 #ifdef CONFIG_KEYBOARD_DEBUG
-	char mylabel = get_keycap_label(row, col);
+	uint8_t mylabel = get_keycap_label(row, col);
 
 	if (mylabel & KEYCAP_LONG_LABEL_BIT)
 		CPRINTS("KB (%d,%d)=%d %s", row, col, is_pressed,
-			get_keycap_long_label(mylabel & KEYCAP_LONG_LABEL_INDEX_BITMASK));
+			get_keycap_long_label(mylabel &
+					      KEYCAP_LONG_LABEL_INDEX_BITMASK));
 	else
 		CPRINTS("KB (%d,%d)=%d %c", row, col, is_pressed, mylabel);
 #endif
@@ -441,7 +500,7 @@ void keyboard_state_changed(int row, int col, int is_pressed)
 	if (ret == EC_SUCCESS) {
 		ASSERT(len > 0);
 		if (keystroke_enabled)
-			i8042_send_to_host(len, scan_code, CHAN_KBD);
+			i8042_send_to_host(len, scan_code, CHAN_KBD, 0);
 	}
 
 	if (is_pressed) {
@@ -452,7 +511,17 @@ void keyboard_state_changed(int row, int col, int is_pressed)
 		clear_typematic_key();
 	}
 }
+#ifdef CONFIG_BOARD_AZALEA
+void i8042_pause_to_host_queue(bool pause)
+{
+	CPRINTS5("8042 %s to_host queue", pause ? "pause" : "resume");
+
+	to_host_queue_paused = pause;
 
+	if (!to_host_queue_paused)
+		task_wake(TASK_ID_KEYPROTO);
+}
+#endif
 static void keystroke_enable(int enable)
 {
 	if (!keystroke_enabled && enable)
@@ -505,8 +574,8 @@ static void update_ctl_ram(uint8_t addr, uint8_t data)
 
 	orig = controller_ram[addr];
 	controller_ram[addr] = data;
-	CPRINTS5("KB set CTR_RAM(0x%02x)=0x%02x (old:0x%02x)",
-		 addr, data, orig);
+	CPRINTS5("KB set CTR_RAM(0x%02x)=0x%02x (old:0x%02x)", addr, data,
+		 orig);
 
 	if (addr == 0x00) {
 		/* Keyboard enable/disable */
@@ -544,19 +613,19 @@ static int handle_mouse_data(uint8_t data, uint8_t *output, int *count)
 	int out_len = 0;
 
 	switch (data_port_state) {
-	case STATE_ECHO_MOUSE:
-		CPRINTS5("STATE_ECHO_MOUSE: 0x%02x", data);
+	case STATE_8042_ECHO_MOUSE:
+		CPRINTS5("STATE_8042_ECHO_MOUSE: 0x%02x", data);
 		output[out_len++] = data;
-		data_port_state = STATE_NORMAL;
+		data_port_state = STATE_ATKBD_CMD;
 		break;
 
-	case STATE_SEND_TO_MOUSE:
-		CPRINTS5("STATE_SEND_TO_MOUSE: 0x%02x", data);
+	case STATE_8042_SEND_TO_MOUSE:
+		CPRINTS5("STATE_8042_SEND_TO_MOUSE: 0x%02x", data);
 		send_aux_data_to_device(data);
-		data_port_state = STATE_NORMAL;
+		data_port_state = STATE_ATKBD_CMD;
 		break;
 
-	default:  /* STATE_NORMAL */
+	default: /* STATE_ATKBD_CMD */
 		return 0;
 	}
 
@@ -579,120 +648,125 @@ static int handle_keyboard_data(uint8_t data, uint8_t *output)
 	int i;
 
 	switch (data_port_state) {
-	case STATE_SCANCODE:
-		CPRINTS5("KB eaten by STATE_SCANCODE: 0x%02x", data);
+	case STATE_ATKBD_SCANCODE:
+		CPRINTS5("KB eaten by STATE_ATKBD_SCANCODE: 0x%02x", data);
 		if (data == SCANCODE_GET_SET) {
-			output[out_len++] = I8042_RET_ACK;
+			output[out_len++] = ATKBD_RET_ACK;
 			output[out_len++] = scancode_set;
 		} else {
 			scancode_set = data;
 			CPRINTS("KB scancode set to %d", scancode_set);
-			output[out_len++] = I8042_RET_ACK;
+			output[out_len++] = ATKBD_RET_ACK;
 		}
-		data_port_state = STATE_NORMAL;
+		data_port_state = STATE_ATKBD_CMD;
 		break;
 
-	case STATE_SETLEDS:
-		CPRINTS5("KB eaten by STATE_SETLEDS");
-		output[out_len++] = I8042_RET_ACK;
-		data_port_state = STATE_NORMAL;
+	case STATE_ATKBD_SETLEDS:
+		CPRINTS5("KB eaten by STATE_ATKBD_SETLEDS");
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+		board_caps_led_control(data);
+#endif /* CONFIG_CUSTOMIZED_DESIGN */
+		output[out_len++] = ATKBD_RET_ACK;
+		data_port_state = STATE_ATKBD_CMD;
 		break;
 
-	case STATE_EX_SETLEDS_1:
-		CPRINTS5("KB eaten by STATE_EX_SETLEDS_1");
-		output[out_len++] = I8042_RET_ACK;
-		data_port_state = STATE_EX_SETLEDS_2;
+	case STATE_ATKBD_EX_SETLEDS_1:
+		CPRINTS5("KB eaten by STATE_ATKBD_EX_SETLEDS_1");
+		output[out_len++] = ATKBD_RET_ACK;
+		data_port_state = STATE_ATKBD_EX_SETLEDS_2;
 		break;
 
-	case STATE_EX_SETLEDS_2:
-		CPRINTS5("KB eaten by STATE_EX_SETLEDS_2");
-		output[out_len++] = I8042_RET_ACK;
-		data_port_state = STATE_NORMAL;
+	case STATE_ATKBD_EX_SETLEDS_2:
+		CPRINTS5("KB eaten by STATE_ATKBD_EX_SETLEDS_2");
+		output[out_len++] = ATKBD_RET_ACK;
+		data_port_state = STATE_ATKBD_CMD;
 		break;
 
-	case STATE_WRITE_CMD_BYTE:
-		CPRINTS5("KB eaten by STATE_WRITE_CMD_BYTE: 0x%02x",
-			 data);
+	case STATE_8042_WRITE_CMD_BYTE:
+		CPRINTS5("KB eaten by STATE_8042_WRITE_CMD_BYTE: 0x%02x", data);
 		update_ctl_ram(controller_ram_address, data);
-		data_port_state = STATE_NORMAL;
+		data_port_state = STATE_ATKBD_CMD;
 		break;
 
-	case STATE_WRITE_OUTPUT_PORT:
-		CPRINTS5("KB eaten by STATE_WRITE_OUTPUT_PORT: 0x%02x",
+	case STATE_8042_WRITE_OUTPUT_PORT:
+		CPRINTS5("KB eaten by STATE_8042_WRITE_OUTPUT_PORT: 0x%02x",
 			 data);
 		A20_status = (data & BIT(1)) ? 1 : 0;
-		data_port_state = STATE_NORMAL;
+		data_port_state = STATE_ATKBD_CMD;
 		break;
 
-	case STATE_SETREP:
-		CPRINTS5("KB eaten by STATE_SETREP: 0x%02x", data);
+	case STATE_ATKBD_SETREP:
+		CPRINTS5("KB eaten by STATE_ATKBD_SETREP: 0x%02x", data);
 		set_typematic_delays(data);
 
-		output[out_len++] = I8042_RET_ACK;
-		data_port_state = STATE_NORMAL;
+		output[out_len++] = ATKBD_RET_ACK;
+		data_port_state = STATE_ATKBD_CMD;
 		break;
 
-	default:  /* STATE_NORMAL */
+	default: /* STATE_ATKBD_CMD */
 		switch (data) {
-		case I8042_CMD_GSCANSET:  /* also I8042_CMD_SSCANSET */
-			output[out_len++] = I8042_RET_ACK;
-			data_port_state = STATE_SCANCODE;
+		case ATKBD_CMD_GSCANSET: /* also ATKBD_CMD_SSCANSET */
+			output[out_len++] = ATKBD_RET_ACK;
+			data_port_state = STATE_ATKBD_SCANCODE;
 			break;
 
-		case I8042_CMD_SETLEDS:
+		case ATKBD_CMD_SETLEDS:
 			/* Chrome OS doesn't have keyboard LEDs, so ignore */
-			output[out_len++] = I8042_RET_ACK;
-			data_port_state = STATE_SETLEDS;
+			output[out_len++] = ATKBD_RET_ACK;
+			data_port_state = STATE_ATKBD_SETLEDS;
+			setleds_deadline.val = get_time().val + SETLEDS_TIMEOUT;
+			CPRINTS5("KB SETLEDS");
 			break;
 
-		case I8042_CMD_EX_SETLEDS:
-			output[out_len++] = I8042_RET_ACK;
-			data_port_state = STATE_EX_SETLEDS_1;
+		case ATKBD_CMD_EX_SETLEDS:
+			output[out_len++] = ATKBD_RET_ACK;
+			data_port_state = STATE_ATKBD_EX_SETLEDS_1;
 			break;
 
-		case I8042_CMD_DIAG_ECHO:
-			output[out_len++] = I8042_RET_ACK;
-			output[out_len++] = I8042_CMD_DIAG_ECHO;
+		case ATKBD_CMD_DIAG_ECHO:
+			output[out_len++] = ATKBD_RET_ACK;
+			output[out_len++] = ATKBD_RET_ECHO;
 			break;
 
-		case I8042_CMD_GETID:    /* fall-thru */
-		case I8042_CMD_OK_GETID:
-			output[out_len++] = I8042_RET_ACK;
-			output[out_len++] = 0xab;  /* Regular keyboards */
+		case ATKBD_CMD_GETID: /* fall-thru */
+		case ATKBD_CMD_OK_GETID:
+			output[out_len++] = ATKBD_RET_ACK;
+			output[out_len++] = 0xab; /* Regular keyboards */
 			output[out_len++] = 0x83;
 			break;
 
-		case I8042_CMD_SETREP:
-			output[out_len++] = I8042_RET_ACK;
-			data_port_state = STATE_SETREP;
+		case ATKBD_CMD_SETREP:
+			output[out_len++] = ATKBD_RET_ACK;
+			data_port_state = STATE_ATKBD_SETREP;
 			break;
 
-		case I8042_CMD_ENABLE:
-			output[out_len++] = I8042_RET_ACK;
+		case ATKBD_CMD_ENABLE:
+			output[out_len++] = ATKBD_RET_ACK;
 			keystroke_enable(1);
 			keyboard_clear_buffer();
 			break;
 
-		case I8042_CMD_RESET_DIS:
-			output[out_len++] = I8042_RET_ACK;
+		case ATKBD_CMD_RESET_DIS:
+			output[out_len++] = ATKBD_RET_ACK;
 			keystroke_enable(0);
 			reset_rate_and_delay();
 			keyboard_clear_buffer();
 			break;
 
-		case I8042_CMD_RESET_DEF:
-			output[out_len++] = I8042_RET_ACK;
+		case ATKBD_CMD_RESET_DEF:
+			output[out_len++] = ATKBD_RET_ACK;
 			reset_rate_and_delay();
 			keyboard_clear_buffer();
 			break;
 
-		case I8042_CMD_RESET:
+		case ATKBD_CMD_RESET:
 			reset_rate_and_delay();
 			keyboard_clear_buffer();
-			output[out_len++] = I8042_RET_ACK;
+			output[out_len++] = ATKBD_RET_ACK;
+			output[out_len++] = ATKBD_RET_TEST_SUCCESS;
 			break;
 
-		case I8042_CMD_RESEND:
+		case ATKBD_CMD_RESEND:
 			save_for_resend = 0;
 			for (i = 0; i < resend_command_len; ++i)
 				output[out_len++] = resend_command[i];
@@ -703,12 +777,12 @@ static int handle_keyboard_data(uint8_t data, uint8_t *output)
 			/* U-boot hack.  Just ignore; don't reply. */
 			break;
 
-		case I8042_CMD_SETALL_MB:  /* fall-thru */
-		case I8042_CMD_SETALL_MBR:
-		case I8042_CMD_EX_ENABLE:
+		case ATKBD_CMD_SETALL_MB: /* fall-thru */
+		case ATKBD_CMD_SETALL_MBR:
+		case ATKBD_CMD_EX_ENABLE:
 		default:
-			output[out_len++] = I8042_RET_NAK;
-			CPRINTS("KB Unsupported i8042 data 0x%02x",
+			output[out_len++] = ATKBD_RET_RESEND;
+			CPRINTS("KB Unsupported AT keyboard command 0x%02x",
 				data);
 			break;
 		}
@@ -752,14 +826,14 @@ static int handle_keyboard_command(uint8_t command, uint8_t *output)
 		break;
 
 	case I8042_WRITE_CMD_BYTE:
-		data_port_state = STATE_WRITE_CMD_BYTE;
+		data_port_state = STATE_8042_WRITE_CMD_BYTE;
 		controller_ram_address = command - 0x60;
 		break;
 
 	case I8042_DIS_KB:
 		update_ctl_ram(0, read_ctl_ram(0) | I8042_KBD_DIS);
 		reset_rate_and_delay();
-		typematic_len = 0;  /* stop typematic */
+		typematic_len = 0; /* stop typematic */
 		keyboard_clear_buffer();
 		break;
 
@@ -773,16 +847,16 @@ static int handle_keyboard_command(uint8_t command, uint8_t *output)
 		output[out_len++] =
 			(lpc_keyboard_input_pending() ? BIT(5) : 0) |
 			(lpc_keyboard_has_char() ? BIT(4) : 0) |
-			(A20_status ? BIT(1) : 0) |
-			1;  /* Main processor in normal mode */
+			(A20_status ? BIT(1) : 0) | 1; /* Main processor in
+							  normal mode */
 		break;
 
 	case I8042_WRITE_OUTPUT_PORT:
-		data_port_state = STATE_WRITE_OUTPUT_PORT;
+		data_port_state = STATE_8042_WRITE_OUTPUT_PORT;
 		break;
 
 	case I8042_RESET_SELF_TEST:
-		output[out_len++] = 0x55;  /* Self test success */
+		output[out_len++] = 0x55; /* Self test success */
 		break;
 
 	case I8042_TEST_KB_PORT:
@@ -798,15 +872,15 @@ static int handle_keyboard_command(uint8_t command, uint8_t *output)
 		break;
 
 	case I8042_TEST_MOUSE:
-		output[out_len++] = 0;  /* No error detected */
+		output[out_len++] = 0; /* No error detected */
 		break;
 
 	case I8042_ECHO_MOUSE:
-		data_port_state = STATE_ECHO_MOUSE;
+		data_port_state = STATE_8042_ECHO_MOUSE;
 		break;
 
 	case I8042_SEND_TO_MOUSE:
-		data_port_state = STATE_SEND_TO_MOUSE;
+		data_port_state = STATE_8042_SEND_TO_MOUSE;
 		break;
 
 	case I8042_SYSTEM_RESET:
@@ -819,7 +893,7 @@ static int handle_keyboard_command(uint8_t command, uint8_t *output)
 			output[out_len++] = read_ctl_ram(command - 0x20);
 		} else if (command >= I8042_WRITE_CTL_RAM &&
 			   command <= I8042_WRITE_CTL_RAM_END) {
-			data_port_state = STATE_WRITE_CMD_BYTE;
+			data_port_state = STATE_8042_WRITE_CMD_BYTE;
 			controller_ram_address = command - 0x60;
 		} else if (command == I8042_DISABLE_A20) {
 			A20_status = 0;
@@ -837,7 +911,7 @@ static int handle_keyboard_command(uint8_t command, uint8_t *output)
 			reset_rate_and_delay();
 			keyboard_clear_buffer();
 			output[out_len++] = I8042_RET_NAK;
-			data_port_state = STATE_NORMAL;
+			data_port_state = STATE_ATKBD_CMD;
 		}
 		break;
 	}
@@ -845,30 +919,67 @@ static int handle_keyboard_command(uint8_t command, uint8_t *output)
 	return out_len;
 }
 
+#if defined(CONFIG_PLATFORM_EC_CUSTOMIZED_DESIGN)
 static void i8042_handle_from_host(void)
 {
 	struct host_byte h;
 	int ret_len;
 	uint8_t output[MAX_SCAN_CODE_LEN];
-	uint8_t chan = CHAN_KBD;
+	uint8_t chan;
+
+	k_mutex_lock(&from_host_mutex, K_FOREVER);
+	while (queue_count(&from_host) > 0) {
+		queue_peek_units(&from_host, &h, 0, 1);
+		if (h.type == HOST_COMMAND) {
+			ret_len = handle_keyboard_command(h.byte, output);
+			chan = CHAN_KBD;
+		} else {
+			CPRINTS5("KB recv data: 0x%02x", h.byte);
+			kblog_put('d', h.byte);
+
+			if (IS_ENABLED(CONFIG_8042_AUX) &&
+			    handle_mouse_data(h.byte, output, &ret_len)) {
+				chan = CHAN_AUX;
+			} else {
+				ret_len = handle_keyboard_data(h.byte, output);
+				chan = CHAN_CMD;
+			}
+		}
+		/* clear queue buffer */
+		queue_advance_head(&from_host, 1);
+		i8042_send_to_host(ret_len, output, chan, 0);
+	}
+	k_mutex_unlock(&from_host_mutex);
+}
+#else
+static void i8042_handle_from_host(void)
+{
+	struct host_byte h;
+	int ret_len;
+	uint8_t output[MAX_SCAN_CODE_LEN];
+	uint8_t chan;
 
 	while (queue_remove_unit(&from_host, &h)) {
 		if (h.type == HOST_COMMAND) {
 			ret_len = handle_keyboard_command(h.byte, output);
+			chan = CHAN_KBD;
 		} else {
 			CPRINTS5("KB recv data: 0x%02x", h.byte);
 			kblog_put('d', h.byte);
 
 			if (IS_ENABLED(CONFIG_8042_AUX) &&
-			    handle_mouse_data(h.byte, output, &ret_len))
+			    handle_mouse_data(h.byte, output, &ret_len)) {
 				chan = CHAN_AUX;
-			else
+			} else {
 				ret_len = handle_keyboard_data(h.byte, output);
+				chan = CHAN_CMD;
+			}
 		}
 
-		i8042_send_to_host(ret_len, output, chan);
+		i8042_send_to_host(ret_len, output, chan, 0);
 	}
 }
+#endif
 
 void keyboard_protocol_task(void *u)
 {
@@ -894,23 +1005,32 @@ void keyboard_protocol_task(void *u)
 				if (keystroke_enabled)
 					i8042_send_to_host(typematic_len,
 							   typematic_scan_code,
-							   CHAN_KBD);
-				typematic_deadline.val = t.val +
-					typematic_inter_delay;
+							   CHAN_KBD, 1);
+				typematic_deadline.val =
+					t.val + typematic_inter_delay;
 				wait = typematic_inter_delay;
 			} else {
 				/* Wait for remaining interval */
 				wait = typematic_deadline.val - t.val;
 			}
-
+#ifdef CONFIG_BOARD_AZALEA
+			if (to_host_queue_paused) {
+				CPRINTS5("i8042 to_host queue is paused");
+				break;
+			}
+#endif
 			/* Handle command/data write from host */
 			i8042_handle_from_host();
 
 			/* Check if we have data to send to host */
-			if (queue_is_empty(&to_host))
+			if (queue_is_empty(&to_host) &&
+			    queue_is_empty(&to_host_cmd))
 				break;
 
-			/* Handle data waiting for host */
+			/*
+			 * Check if the output buffer is full. We can't proceed
+			 * until the host read the data.
+			 */
 			if (lpc_keyboard_has_char()) {
 				/* If interrupts disabled, nothing we can do */
 				if (!i8042_keyboard_irq_enabled &&
@@ -928,26 +1048,71 @@ void keyboard_protocol_task(void *u)
 				 * data?  Send it another interrupt in case it
 				 * somehow missed the first one.
 				 */
-				CPRINTS("KB extra IRQ");
+				CPRINTS("KB host not responding");
 				lpc_keyboard_resume_irq();
 				retries = 0;
 				break;
 			}
 
+			/*
+			 * We know DBBOUT is empty but we need act quickly as
+			 * the host might be sending a byte to DBBIN.
+			 *
+			 * So be cautious if you're adding any code below up to
+			 * lpc_keyboard_put_char since that'll increase the race
+			 * condition. For example, you don't want to add CPRINTS
+			 * or kblog_put.
+			 *
+			 * We should claim OBF=1 atomically to prevent the host
+			 * from writing to DBBIN (i.e. set-ibf-if-not-obf). It's
+			 * not possible for NPCX because NPCX's HIKMST-IBF is
+			 * read-only.
+			 */
+
 			/* Get a char from buffer. */
-			kblog_put('k', to_host.state->head);
-			queue_remove_unit(&to_host, &entry);
+			if (queue_count(&to_host_cmd)) {
+				queue_remove_unit(&to_host_cmd, &entry);
+			} else if (data_port_state == STATE_ATKBD_SETLEDS) {
+				/*
+				 * to_host_cmd == empty and to_host != empty.
+				 * We're in SETLEDS thus expecting the 2nd byte.
+				 * Until timer expires, don't process scancode.
+				 */
+				if (!timestamp_expired(setleds_deadline, &t)) {
+					/*
+					 * Let's wait for the 2nd byte but we
+					 * don't want to wait too long because
+					 * we already have scancode to send.
+					 */
+					if (wait == -1 ||
+					    wait > setleds_deadline.val - t.val)
+						wait = setleds_deadline.val -
+						       t.val;
+					break;
+				}
+				/*
+				 * Didn't receive 2nd byte. Go back to CMD. We
+				 * don't need to cancel the timer because going
+				 * back to CMD state implicitly disables timer.
+				 */
+				CPRINTS("KB SETLEDS timeout");
+				data_port_state = STATE_ATKBD_CMD;
+				queue_remove_unit(&to_host, &entry);
+			} else {
+				/* to_host isn't empty && not in SETLEDS */
+				queue_remove_unit(&to_host, &entry);
+			}
 
 			/* Write to host. */
 			if (entry.chan == CHAN_AUX &&
 			    IS_ENABLED(CONFIG_8042_AUX)) {
-				kblog_put('A', entry.byte);
 				lpc_aux_put_char(entry.byte,
 						 i8042_aux_irq_enabled);
+				kblog_put('A', entry.byte);
 			} else {
-				kblog_put('K', entry.byte);
 				lpc_keyboard_put_char(
 					entry.byte, i8042_keyboard_irq_enabled);
+				kblog_put('K', entry.byte);
 			}
 			retries = 0;
 		}
@@ -959,13 +1124,13 @@ static void send_aux_data_to_host_deferred(void)
 	uint8_t data;
 
 	if (IS_ENABLED(CONFIG_DEVICE_EVENT) &&
-		chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
+	    chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
 		device_set_single_event(EC_DEVICE_EVENT_TRACKPAD);
 
 	while (!queue_is_empty(&aux_to_host_queue)) {
 		queue_remove_unit(&aux_to_host_queue, &data);
 		if (aux_chan_enabled && IS_ENABLED(CONFIG_8042_AUX))
-			i8042_send_to_host(1, &data, CHAN_AUX);
+			i8042_send_to_host(1, &data, CHAN_AUX, 0);
 		else
 			CPRINTS("AUX Callback ignored");
 	}
@@ -1021,15 +1186,51 @@ test_mockable void keyboard_update_button(enum keyboard_button_type button,
 	}
 
 	if (keystroke_enabled) {
-		i8042_send_to_host(len, scan_code, CHAN_KBD);
+		CPRINTS5("KB UPDATE BTN");
+
+		i8042_send_to_host(len, scan_code, CHAN_KBD, 0);
 		task_wake(TASK_ID_KEYPROTO);
 	}
 }
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+void simulate_keyboard(uint16_t scancode, int is_pressed)
+{
+	uint8_t scan_code[MAX_SCAN_CODE_LEN];
+	uint32_t len;
+	enum scancode_set_list code_set;
+
+	/*
+	 * Only send the scan code if main chipset is fully awake and
+	 * keystrokes are enabled.
+	 */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF) ||
+		!keystroke_enabled ||
+		chipset_in_state(CHIPSET_STATE_SUSPEND))
+		return;
+
+	code_set = acting_code_set(scancode_set);
+	if (!is_supported_code_set(code_set))
+		return;
+
+	scancode_bytes(scancode, is_pressed, code_set, scan_code,
+		       &len);
+	ASSERT(len > 0);
+
+	if (is_pressed)
+		set_typematic_key(scan_code, len);
+	else
+		clear_typematic_key();
 
+	if (keystroke_enabled) {
+		i8042_send_to_host(len, scan_code, CHAN_KBD, 0);
+		task_wake(TASK_ID_KEYPROTO);
+	}
+}
+#endif /* CONFIG_CUSTOMIZED_DESIGN */
 /*****************************************************************************/
 /* Console commands */
 #ifdef CONFIG_CMD_KEYBOARD
-static int command_typematic(int argc, char **argv)
+static int command_typematic(int argc, const char **argv)
 {
 	int i;
 
@@ -1050,18 +1251,14 @@ static int command_typematic(int argc, char **argv)
 	ccputs("}\n");
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(typematic, command_typematic,
-			"[first] [inter]",
-			"Get/set typematic delays");
-
 
-static int command_codeset(int argc, char **argv)
+static int command_codeset(int argc, const char **argv)
 {
 	if (argc == 2) {
 		int set = strtoi(argv[1], NULL, 0);
 		switch (set) {
-		case SCANCODE_SET_1:  /* fall-thru */
-		case SCANCODE_SET_2:  /* fall-thru */
+		case SCANCODE_SET_1: /* fall-thru */
+		case SCANCODE_SET_2: /* fall-thru */
 			scancode_set = set;
 			break;
 		default:
@@ -1073,12 +1270,8 @@ static int command_codeset(int argc, char **argv)
 	ccprintf("I8042_XLATE: %d\n", controller_ram[0] & I8042_XLATE ? 1 : 0);
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(codeset, command_codeset,
-			"[set]",
-			"Get/set keyboard codeset");
 
-
-static int command_controller_ram(int argc, char **argv)
+static int command_controller_ram(int argc, const char **argv)
 {
 	int index;
 
@@ -1095,11 +1288,8 @@ static int command_controller_ram(int argc, char **argv)
 	ccprintf("%d = 0x%02x\n", index, controller_ram[index]);
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(ctrlram, command_controller_ram,
-			"index [value]",
-			"Get/set keyboard controller RAM");
 
-static int command_keyboard_log(int argc, char **argv)
+static int command_keyboard_log(int argc, const char **argv)
 {
 	int i;
 
@@ -1107,8 +1297,8 @@ static int command_keyboard_log(int argc, char **argv)
 	if (argc == 1) {
 		ccprintf("KBC log (len=%d):\n", kblog_len);
 		for (i = 0; kblog_buf && i < kblog_len; ++i) {
-			ccprintf("%c.%02x ",
-				 kblog_buf[i].type, kblog_buf[i].byte);
+			ccprintf("%c.%02x ", kblog_buf[i].type,
+				 kblog_buf[i].byte);
 			if ((i & 15) == 15) {
 				ccputs("\n");
 				cflush();
@@ -1124,9 +1314,9 @@ static int command_keyboard_log(int argc, char **argv)
 
 	if (i) {
 		if (!kblog_buf) {
-			int rv = SHARED_MEM_ACQUIRE_CHECK(
-				sizeof(*kblog_buf) * MAX_KBLOG,
-				(char **)&kblog_buf);
+			int rv = SHARED_MEM_ACQUIRE_CHECK(sizeof(*kblog_buf) *
+								  MAX_KBLOG,
+							  (char **)&kblog_buf);
 			if (rv != EC_SUCCESS)
 				kblog_buf = NULL;
 			kblog_len = 0;
@@ -1141,12 +1331,8 @@ static int command_keyboard_log(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(kblog, command_keyboard_log,
-			"[on | off]",
-			"Print or toggle keyboard event log");
-
 
-static int command_keyboard(int argc, char **argv)
+static int command_keyboard(int argc, const char **argv)
 {
 	int ena;
 
@@ -1160,12 +1346,8 @@ static int command_keyboard(int argc, char **argv)
 	ccprintf("Enabled: %d\n", keyboard_enabled);
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(kbd, command_keyboard,
-			"[on | off]",
-			"Print or toggle keyboard info");
 
-
-static int command_8042_internal(int argc, char **argv)
+static int command_8042_internal(int argc, const char **argv)
 {
 	int i;
 
@@ -1175,7 +1357,9 @@ static int command_8042_internal(int argc, char **argv)
 	ccprintf("keyboard_enabled=%d\n", keyboard_enabled);
 	ccprintf("keystroke_enabled=%d\n", keystroke_enabled);
 	ccprintf("aux_chan_enabled=%d\n", aux_chan_enabled);
-
+#ifdef CONFIG_BOARD_AZALEA
+	ccprintf("to_host_queue_paused=%d\n", to_host_queue_paused);
+#endif
 	ccprintf("resend_command[]={");
 	for (i = 0; i < resend_command_len; i++)
 		ccprintf("0x%02x, ", resend_command[i]);
@@ -1208,8 +1392,21 @@ static int command_8042_internal(int argc, char **argv)
 	return EC_SUCCESS;
 }
 
+/* Zephyr only provides these as subcommands*/
+#ifndef CONFIG_ZEPHYR
+DECLARE_CONSOLE_COMMAND(typematic, command_typematic, "[first] [inter]",
+			"Get/set typematic delays");
+DECLARE_CONSOLE_COMMAND(codeset, command_codeset, "[set]",
+			"Get/set keyboard codeset");
+DECLARE_CONSOLE_COMMAND(ctrlram, command_controller_ram, "index [value]",
+			"Get/set keyboard controller RAM");
+DECLARE_CONSOLE_COMMAND(kblog, command_keyboard_log, "[on | off]",
+			"Print or toggle keyboard event log");
+DECLARE_CONSOLE_COMMAND(kbd, command_keyboard, "[on | off]",
+			"Print or toggle keyboard info");
+#endif
 
-static int command_8042(int argc, char **argv)
+static int command_8042(int argc, const char **argv)
 {
 	if (argc >= 2) {
 		if (!strcasecmp(argv[1], "internal"))
@@ -1220,25 +1417,27 @@ static int command_8042(int argc, char **argv)
 			return command_codeset(argc - 1, argv + 1);
 		else if (!strcasecmp(argv[1], "ctrlram"))
 			return command_controller_ram(argc - 1, argv + 1);
-		else if (!strcasecmp(argv[1], "kblog"))
+		else if (CMD_KEYBOARD_LOG && !strcasecmp(argv[1], "kblog"))
 			return command_keyboard_log(argc - 1, argv + 1);
 		else if (!strcasecmp(argv[1], "kbd"))
 			return command_keyboard(argc - 1, argv + 1);
 		else
 			return EC_ERROR_PARAM1;
 	} else {
-		char *ctlram_argv[] = {"ctrlram", "0"};
+		const char *ctlram_argv[] = { "ctrlram", "0" };
 
 		ccprintf("\n- Typematic:\n");
 		command_typematic(argc, argv);
 		ccprintf("\n- Codeset:\n");
 		command_codeset(argc, argv);
 		ccprintf("\n- Control RAM:\n");
-		command_controller_ram(
-			sizeof(ctlram_argv) / sizeof(ctlram_argv[0]),
-			ctlram_argv);
-		ccprintf("\n- Keyboard log:\n");
-		command_keyboard_log(argc, argv);
+		command_controller_ram(sizeof(ctlram_argv) /
+					       sizeof(ctlram_argv[0]),
+				       ctlram_argv);
+		if (CMD_KEYBOARD_LOG) {
+			ccprintf("\n- Keyboard log:\n");
+			command_keyboard_log(argc, argv);
+		}
 		ccprintf("\n- Keyboard:\n");
 		command_keyboard(argc, argv);
 		ccprintf("\n- Internal:\n");
@@ -1254,7 +1453,6 @@ DECLARE_CONSOLE_COMMAND(8042, command_8042,
 			"Print 8042 state in one place");
 #endif
 
-
 /*****************************************************************************/
 /* Hooks */
 
@@ -1276,8 +1474,8 @@ static void keyboard_preserve_state(void)
 	state.ctlram = controller_ram[0];
 	state.keystroke_enabled = keystroke_enabled;
 
-	system_add_jump_tag(KB_SYSJUMP_TAG, KB_HOOK_VERSION,
-			    sizeof(state), &state);
+	system_add_jump_tag(KB_SYSJUMP_TAG, KB_HOOK_VERSION, sizeof(state),
+			    &state);
 }
 DECLARE_HOOK(HOOK_SYSJUMP, keyboard_preserve_state, HOOK_PRIO_DEFAULT);
 
@@ -1300,6 +1498,8 @@ static void keyboard_restore_state(void)
 }
 DECLARE_HOOK(HOOK_INIT, keyboard_restore_state, HOOK_PRIO_DEFAULT);
 
+#ifndef CONFIG_PLATFORM_EC_CUSTOMIZED_DESIGN
+#if defined(CONFIG_POWER_BUTTON) && !defined(CONFIG_MKBP_INPUT_DEVICES)
 /**
  * Handle power button changing state.
  */
@@ -1310,3 +1510,35 @@ static void keyboard_power_button(void)
 }
 DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, keyboard_power_button,
 	     HOOK_PRIO_DEFAULT);
+
+#endif /* CONFIG_POWER_BUTTON && !CONFIG_MKBP_INPUT_DEVICES */
+#endif /* CONFIG_PLATFORM_EC_CUSTOMIZED_DESIGN */
+
+#ifdef TEST_BUILD
+void test_keyboard_8042_set_resend_command(const uint8_t *data, int length)
+{
+	length = MIN(length, sizeof(resend_command));
+
+	memcpy(resend_command, data, length);
+	resend_command_len = length;
+}
+
+void test_keyboard_8042_reset(void)
+{
+	/* Initialize controller ram */
+	memset(controller_ram, 0, sizeof(controller_ram));
+	controller_ram[0] = I8042_XLATE | I8042_AUX_DIS | I8042_KBD_DIS;
+
+	/* Typematic state reset */
+	reset_rate_and_delay();
+	clear_typematic_key();
+
+	/* Use default scancode set # 2 */
+	scancode_set = SCANCODE_SET_2;
+
+	/* Keyboard not enabled (matches I8042_KBD_DIS bit being set) */
+	keyboard_enabled = false;
+
+	A20_status = 0;
+}
+#endif /* TEST_BUILD */
diff --git a/common/keyboard_8042_sharedlib.c b/common/keyboard_8042_sharedlib.c
index 1d024d3f47..b8902cdf04 100644
--- a/common/keyboard_8042_sharedlib.c
+++ b/common/keyboard_8042_sharedlib.c
@@ -1,10 +1,11 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Objects which can be shared between RO and RW for 8042 keyboard protocol.
  */
 
+#include "builtin/assert.h"
 #include "button.h"
 #include "keyboard_8042_sharedlib.h"
 #include "keyboard_config.h"
@@ -12,31 +13,39 @@
 #include "libsharedobjs.h"
 #include "util.h"
 
+#include <stddef.h>
+
 #ifndef CONFIG_KEYBOARD_CUSTOMIZATION
 /* The standard Chrome OS keyboard matrix table in scan code set 2. */
 static uint16_t scancode_set2[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = {
-	{0x0000, 0x0000, 0x0014, 0xe01f, 0xe014, 0xe007, 0x0000, 0x0000},
-	{0xe01f, 0x0076, 0x000d, 0x000e, 0x001c, 0x001a, 0x0016, 0x0015},
-	{0x0005, 0x000c, 0x0004, 0x0006, 0x0023, 0x0021, 0x0026, 0x0024},
-	{0x0032, 0x0034, 0x002c, 0x002e, 0x002b, 0x002a, 0x0025, 0x002d},
-	{0x0009, 0x0083, 0x000b, 0x0003, 0x001b, 0x0022, 0x001e, 0x001d},
-	{0x0051, 0x0000, 0x005b, 0x0000, 0x0042, 0x0041, 0x003e, 0x0043},
-	{0x0031, 0x0033, 0x0035, 0x0036, 0x003b, 0x003a, 0x003d, 0x003c},
-	{0x0000, 0x0000, 0x0061, 0x0000, 0x0000, 0x0012, 0x0000, 0x0059},
-	{0x0055, 0x0052, 0x0054, 0x004e, 0x004c, 0x004a, 0x0045, 0x004d},
-	{0x0000, 0x0001, 0x000a, 0x002f, 0x004b, 0x0049, 0x0046, 0x0044},
-	{0xe011, 0x0000, 0x006a, 0x0000, 0x005d, 0x0000, 0x0011, 0x0000},
+	{ 0x0000, 0x0000, 0x0014, 0xe01f, 0xe014, 0xe007, 0x0000, 0x0000 },
+	{ 0xe01f, 0x0076, 0x000d, 0x000e, 0x001c, 0x001a, 0x0016, 0x0015 },
+	{ 0x0005, 0x000c, 0x0004, 0x0006, 0x0023, 0x0021, 0x0026, 0x0024 },
+	{ 0x0032, 0x0034, 0x002c, 0x002e, 0x002b, 0x002a, 0x0025, 0x002d },
+	{ 0x0009, 0x0083, 0x000b, 0x0003, 0x001b, 0x0022, 0x001e, 0x001d },
+	{ 0x0051, 0x0000, 0x005b, 0x0000, 0x0042, 0x0041, 0x003e, 0x0043 },
+	{ 0x0031, 0x0033, 0x0035, 0x0036, 0x003b, 0x003a, 0x003d, 0x003c },
+	{ 0x0000, 0x0000, 0x0061, 0x0000, 0x0000, 0x0012, 0x0000, 0x0059 },
+	{ 0x0055, 0x0052, 0x0054, 0x004e, 0x004c, 0x004a, 0x0045, 0x004d },
+	{ 0x0000, 0x0001, 0x000a, 0x002f, 0x004b, 0x0049, 0x0046, 0x0044 },
+	{ 0xe011, 0x0000, 0x006a, 0x0000, 0x005d, 0x0000, 0x0011, 0x0000 },
 #ifndef CONFIG_KEYBOARD_KEYPAD
-	{0x0000, 0x0066, 0x0000, 0x005d, 0x005a, 0x0029, 0xe072, 0xe075},
-	{0x0000, 0x0064, 0x0000, 0x0067, 0x0000, 0x0000, 0xe074, 0xe06b},
+	{ 0x0000, 0x0066, 0x0000, 0x005d, 0x005a, 0x0029, 0xe072, 0xe075 },
+	{ 0x0000, 0x0064, 0x0000, 0x0067, 0x0000, 0x0000, 0xe074, 0xe06b },
 #else
-	{0x0000, 0x0066, 0xe071, 0x005d, 0x005a, 0x0029, 0xe072, 0xe075},
-	{0xe06c, 0x0064, 0xe07d, 0x0067, 0xe069, 0xe07a, 0xe074, 0xe06b},
-	{0xe04a, 0x007c, 0x007b, 0x0074, 0x0071, 0x0073, 0x006b, 0x0070},
-	{0x006c, 0x0075, 0x007d, 0x0079, 0x007a, 0x0072, 0x0069, 0xe05a},
+	{ 0x0000, 0x0066, 0xe071, 0x005d, 0x005a, 0x0029, 0xe072, 0xe075 },
+	{ 0xe06c, 0x0064, 0xe07d, 0x0067, 0xe069, 0xe07a, 0xe074, 0xe06b },
+	{ 0xe04a, 0x007c, 0x007b, 0x0074, 0x0071, 0x0073, 0x006b, 0x0070 },
+	{ 0x006c, 0x0075, 0x007d, 0x0079, 0x007a, 0x0072, 0x0069, 0xe05a },
 #endif
 };
 
+void register_scancode_set2(uint16_t *scancode_set, size_t size)
+{
+	ASSERT(size == sizeof(scancode_set2));
+	memcpy(scancode_set2, scancode_set, size);
+}
+
 uint16_t get_scancode_set2(uint8_t row, uint8_t col)
 {
 	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS)
@@ -60,37 +69,32 @@ void set_scancode_set2(uint8_t row, uint8_t col, uint16_t val)
  * see scancode_translate_set2_to_1 below).
  */
 SHAREDLIB(const uint8_t scancode_translate_table[128] = {
-	0xff, 0x43, 0x41, 0x3f, 0x3d, 0x3b, 0x3c, 0x58,
-	0x64, 0x44, 0x42, 0x40, 0x3e, 0x0f, 0x29, 0x59,
-	0x65, 0x38, 0x2a, 0x70, 0x1d, 0x10, 0x02, 0x5a,
-	0x66, 0x71, 0x2c, 0x1f, 0x1e, 0x11, 0x03, 0x5b,
-	0x67, 0x2e, 0x2d, 0x20, 0x12, 0x05, 0x04, 0x5c,
-	0x68, 0x39, 0x2f, 0x21, 0x14, 0x13, 0x06, 0x5d,
-	0x69, 0x31, 0x30, 0x23, 0x22, 0x15, 0x07, 0x5e,
-	0x6a, 0x72, 0x32, 0x24, 0x16, 0x08, 0x09, 0x5f,
-	0x6b, 0x33, 0x25, 0x17, 0x18, 0x0b, 0x0a, 0x60,
-	0x6c, 0x34, 0x35, 0x26, 0x27, 0x19, 0x0c, 0x61,
-	0x6d, 0x73, 0x28, 0x74, 0x1a, 0x0d, 0x62, 0x6e,
-	0x3a, 0x36, 0x1c, 0x1b, 0x75, 0x2b, 0x63, 0x76,
-	0x55, 0x56, 0x77, 0x78, 0x79, 0x7a, 0x0e, 0x7b,
-	0x7c, 0x4f, 0x7d, 0x4b, 0x47, 0x7e, 0x7f, 0x6f,
-	0x52, 0x53, 0x50, 0x4c, 0x4d, 0x48, 0x01, 0x45,
-	0x57, 0x4e, 0x51, 0x4a, 0x37, 0x49, 0x46, 0x54,
-});
-
+		  0xff, 0x43, 0x41, 0x3f, 0x3d, 0x3b, 0x3c, 0x58, 0x64, 0x44,
+		  0x42, 0x40, 0x3e, 0x0f, 0x29, 0x59, 0x65, 0x38, 0x2a, 0x70,
+		  0x1d, 0x10, 0x02, 0x5a, 0x66, 0x71, 0x2c, 0x1f, 0x1e, 0x11,
+		  0x03, 0x5b, 0x67, 0x2e, 0x2d, 0x20, 0x12, 0x05, 0x04, 0x5c,
+		  0x68, 0x39, 0x2f, 0x21, 0x14, 0x13, 0x06, 0x5d, 0x69, 0x31,
+		  0x30, 0x23, 0x22, 0x15, 0x07, 0x5e, 0x6a, 0x72, 0x32, 0x24,
+		  0x16, 0x08, 0x09, 0x5f, 0x6b, 0x33, 0x25, 0x17, 0x18, 0x0b,
+		  0x0a, 0x60, 0x6c, 0x34, 0x35, 0x26, 0x27, 0x19, 0x0c, 0x61,
+		  0x6d, 0x73, 0x28, 0x74, 0x1a, 0x0d, 0x62, 0x6e, 0x3a, 0x36,
+		  0x1c, 0x1b, 0x75, 0x2b, 0x63, 0x76, 0x55, 0x56, 0x77, 0x78,
+		  0x79, 0x7a, 0x0e, 0x7b, 0x7c, 0x4f, 0x7d, 0x4b, 0x47, 0x7e,
+		  0x7f, 0x6f, 0x52, 0x53, 0x50, 0x4c, 0x4d, 0x48, 0x01, 0x45,
+		  0x57, 0x4e, 0x51, 0x4a, 0x37, 0x49, 0x46, 0x54,
+	  });
 
 #ifdef CONFIG_KEYBOARD_DEBUG
-SHAREDLIB(const
-static char * const keycap_long_label[KLLI_MAX & KEYCAP_LONG_LABEL_INDEX_BITMASK] = {
-	"UNKNOWN", "F1",    "F2",    "F3",
-	"F4",      "F5",    "F6",    "F7",
-	"F8",      "F9",    "F10",   "F11",
-	"F12",     "F13",   "F14",   "F15",
-	"L-ALT",   "R-ALT", "L-CTR", "R-CTR",
-	"L-SHT",   "R-SHT", "ENTER", "SPACE",
-	"B-SPC",   "TAB",   "SEARC", "LEFT",
-	"RIGHT",   "DOWN",  "UP",    "ESC",
-});
+SHAREDLIB(
+	const static char *const
+		keycap_long_label[KLLI_MAX & KEYCAP_LONG_LABEL_INDEX_BITMASK] = {
+			"UNKNOWN", "F1",    "F2",    "F3",    "F4",    "F5",
+			"F6",	   "F7",    "F8",    "F9",    "F10",   "F11",
+			"F12",	   "F13",   "F14",   "F15",   "L-ALT", "R-ALT",
+			"L-CTR",   "R-CTR", "L-SHT", "R-SHT", "ENTER", "SPACE",
+			"B-SPC",   "TAB",   "SEARC", "LEFT",  "RIGHT", "DOWN",
+			"UP",	   "ESC",
+		});
 
 const char *get_keycap_long_label(uint8_t idx)
 {
@@ -100,50 +104,42 @@ const char *get_keycap_long_label(uint8_t idx)
 }
 
 #ifndef CONFIG_KEYBOARD_CUSTOMIZATION
-static char keycap_label[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = {
-	{KLLI_UNKNO, KLLI_UNKNO, KLLI_L_CTR, KLLI_SEARC,
-			KLLI_R_CTR, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO},
-	{KLLI_F11,   KLLI_ESC,   KLLI_TAB,   '~',
-			'a',        'z',        '1',        'q'},
-	{KLLI_F1,    KLLI_F4,    KLLI_F3,    KLLI_F2,
-			'd',        'c',        '3',        'e'},
-	{'b',        'g',        't',        '5',
-			'f',        'v',        '4',        'r'},
-	{KLLI_F10,   KLLI_F7,    KLLI_F6,    KLLI_F5,
-			's',        'x',        '2',        'w'},
-	{KLLI_UNKNO, KLLI_F12,   ']',        KLLI_F13,
-			'k',        ',',        '8',        'i'},
-	{'n',        'h',        'y',        '6',
-			'j',        'm',        '7',        'u'},
-	{KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
-			KLLI_UNKNO, KLLI_L_SHT, KLLI_UNKNO, KLLI_R_SHT},
-	{'=',        '\'',       '[',        '-',
-			';',        '/',        '0',        'p'},
-	{KLLI_F14,   KLLI_F9,    KLLI_F8,    KLLI_UNKNO,
-			'|',        '.',        '9',        'o'},
-	{KLLI_R_ALT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
-			KLLI_UNKNO, KLLI_UNKNO, KLLI_L_ALT, KLLI_UNKNO},
-	{KLLI_F15,   KLLI_B_SPC, KLLI_UNKNO, '\\',
-			KLLI_ENTER, KLLI_SPACE, KLLI_DOWN,  KLLI_UP},
-	{KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
-			KLLI_UNKNO, KLLI_UNKNO, KLLI_RIGHT, KLLI_LEFT},
+static uint8_t keycap_label[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = {
+	{ KLLI_UNKNO, KLLI_UNKNO, KLLI_L_CTR, KLLI_SEARC, KLLI_R_CTR,
+	  KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO },
+	{ KLLI_F11, KLLI_ESC, KLLI_TAB, '~', 'a', 'z', '1', 'q' },
+	{ KLLI_F1, KLLI_F4, KLLI_F3, KLLI_F2, 'd', 'c', '3', 'e' },
+	{ 'b', 'g', 't', '5', 'f', 'v', '4', 'r' },
+	{ KLLI_F10, KLLI_F7, KLLI_F6, KLLI_F5, 's', 'x', '2', 'w' },
+	{ KLLI_UNKNO, KLLI_F12, ']', KLLI_F13, 'k', ',', '8', 'i' },
+	{ 'n', 'h', 'y', '6', 'j', 'm', '7', 'u' },
+	{ KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_L_SHT, KLLI_UNKNO, KLLI_R_SHT },
+	{ '=', '\'', '[', '-', ';', '/', '0', 'p' },
+	{ KLLI_F14, KLLI_F9, KLLI_F8, KLLI_UNKNO, '|', '.', '9', 'o' },
+	{ KLLI_R_ALT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_L_ALT, KLLI_UNKNO },
+	{ KLLI_F15, KLLI_B_SPC, KLLI_UNKNO, '\\', KLLI_ENTER, KLLI_SPACE,
+	  KLLI_DOWN, KLLI_UP },
+	{ KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_RIGHT, KLLI_LEFT },
 #ifdef CONFIG_KEYBOARD_KEYPAD
 	/* TODO: Populate these */
-	{KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
-			KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO},
-	{KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
-			KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO},
+	{ KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO },
+	{ KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO },
 #endif
 };
 
-char get_keycap_label(uint8_t row, uint8_t col)
+uint8_t get_keycap_label(uint8_t row, uint8_t col)
 {
 	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS)
 		return keycap_label[col][row];
 	return KLLI_UNKNO;
 }
 
-void set_keycap_label(uint8_t row, uint8_t col, char val)
+void set_keycap_label(uint8_t row, uint8_t col, uint8_t val)
 {
 	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS)
 		keycap_label[col][row] = val;
@@ -166,16 +162,19 @@ uint8_t scancode_translate_set2_to_1(uint8_t code)
  * Must be in the same order as defined in keyboard_button_type.
  */
 SHAREDLIB(const struct button_8042_t buttons_8042[] = {
-	{SCANCODE_POWER, 0},
-	{SCANCODE_VOLUME_DOWN, 1},
-	{SCANCODE_VOLUME_UP, 1},
-	{SCANCODE_1, 1},
-	{SCANCODE_2, 1},
-	{SCANCODE_3, 1},
-	{SCANCODE_4, 1},
-	{SCANCODE_5, 1},
-	{SCANCODE_6, 1},
-	{SCANCODE_7, 1},
-	{SCANCODE_8, 1},
-});
+		  { SCANCODE_POWER, 0 },
+		  { SCANCODE_VOLUME_DOWN, 1 },
+		  { SCANCODE_VOLUME_UP, 1 },
+		  { SCANCODE_1, 1 },
+		  { SCANCODE_2, 1 },
+		  { SCANCODE_3, 1 },
+		  { SCANCODE_4, 1 },
+		  { SCANCODE_5, 1 },
+		  { SCANCODE_6, 1 },
+		  { SCANCODE_7, 1 },
+		  { SCANCODE_8, 1 },
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+		  {SCANCODE_FAKE_POWER, 0},
+#endif /* CONFIG_CUSTOMIZED_DESIGN */
+	  });
 BUILD_ASSERT(ARRAY_SIZE(buttons_8042) == KEYBOARD_BUTTON_COUNT);
diff --git a/common/keyboard_backlight.c b/common/keyboard_backlight.c
index 694ac77446..fde20de7ef 100644
--- a/common/keyboard_backlight.c
+++ b/common/keyboard_backlight.c
@@ -1,25 +1,34 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "chipset.h"
 #include "console.h"
 #include "ec_commands.h"
+#include "gpio.h"
 #include "hooks.h"
 #include "host_command.h"
 #include "keyboard_backlight.h"
 #include "lid_switch.h"
+#include "rgb_keyboard.h"
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_KEYBOARD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_KEYBOARD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ##args)
 
 static struct kblight_conf kblight;
 static int current_percent;
+static uint8_t current_enable;
 
-void __attribute__((weak)) board_kblight_init(void)
-{ }
+__overridable void board_kblight_init(void)
+{
+}
+
+__overridable void board_kblight_shutdown(void)
+{
+}
 
 static int kblight_init(void)
 {
@@ -54,11 +63,34 @@ int kblight_get(void)
 	return current_percent;
 }
 
-int kblight_enable(int enable)
+static void kblight_enable_deferred(void)
 {
+#ifdef CONFIG_KBLIGHT_ENABLE_PIN
+	gpio_set_level(GPIO_EN_KEYBOARD_BACKLIGHT, current_enable);
+#endif
 	if (!kblight.drv || !kblight.drv->enable)
-		return -1;
-	return kblight.drv->enable(enable);
+		return;
+	kblight.drv->enable(current_enable);
+}
+DECLARE_DEFERRED(kblight_enable_deferred);
+
+int kblight_enable(int enable)
+{
+	current_enable = enable;
+	/* Need to defer i2c in case it's called from an interrupt handler. */
+	hook_call_deferred(&kblight_enable_deferred_data, 0);
+	return EC_SUCCESS;
+}
+
+int kblight_get_enabled(void)
+{
+#ifdef CONFIG_KBLIGHT_ENABLE_PIN
+	if (!gpio_get_level(GPIO_EN_KEYBOARD_BACKLIGHT))
+		return 0;
+#endif
+	if (kblight.drv && kblight.drv->get_enabled)
+		return kblight.drv->get_enabled();
+	return -1;
 }
 
 int kblight_register(const struct kblight_drv *drv)
@@ -74,15 +106,26 @@ int kblight_register(const struct kblight_drv *drv)
 static void keyboard_backlight_init(void)
 {
 	/* Uses PWM by default. Can be customized by board_kblight_init */
-#ifdef CONFIG_PWM_KBLIGHT
-	kblight_register(&kblight_pwm);
-#endif
+	if (IS_ENABLED(CONFIG_PWM_KBLIGHT))
+		kblight_register(&kblight_pwm);
+	else if (IS_ENABLED(CONFIG_RGB_KEYBOARD))
+		kblight_register(&kblight_rgbkbd);
+
 	board_kblight_init();
 	if (kblight_init())
 		CPRINTS("kblight init failed");
+	/* Don't leave kblight enable state undetermined */
+	kblight_enable(0);
 }
+#ifdef HAS_TASK_CHIPSET
+/* We're running on a system EC. Initialize kblight once per AP start-up. */
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, keyboard_backlight_init, HOOK_PRIO_DEFAULT);
+#else
+/* We're running on a KBMCU thus powered when AP starts. Do init on reset. */
 DECLARE_HOOK(HOOK_INIT, keyboard_backlight_init, HOOK_PRIO_DEFAULT);
+#endif
 
+#ifdef CONFIG_AP_POWER_CONTROL
 static void kblight_suspend(void)
 {
 	kblight_enable(0);
@@ -97,17 +140,20 @@ static void kblight_resume(void)
 	}
 }
 DECLARE_HOOK(HOOK_CHIPSET_RESUME, kblight_resume, HOOK_PRIO_DEFAULT);
+#endif /* CONFIG_AP_POWER_CONTROL */
 
+#ifdef CONFIG_LID_SWITCH
 static void kblight_lid_change(void)
 {
 	kblight_enable(lid_is_open() && current_percent);
 }
 DECLARE_HOOK(HOOK_LID_CHANGE, kblight_lid_change, HOOK_PRIO_DEFAULT);
+#endif
 
 /*
  * Console and host commands
  */
-static int cc_kblight(int argc, char **argv)
+static int cc_kblight(int argc, const char **argv)
 {
 	if (argc >= 2) {
 		char *e;
@@ -119,28 +165,29 @@ static int cc_kblight(int argc, char **argv)
 		if (kblight_enable(i > 0))
 			return EC_ERROR_PARAM1;
 	}
-	ccprintf("Keyboard backlight: %d%%\n", kblight_get());
+	ccprintf("Keyboard backlight: %d%% enabled: %d\n", kblight_get(),
+		 kblight_get_enabled());
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(kblight, cc_kblight,
-			"percent",
+DECLARE_CONSOLE_COMMAND(kblight, cc_kblight, "percent",
 			"Get/set keyboard backlight");
 
-enum ec_status hc_get_keyboard_backlight(struct host_cmd_handler_args *args)
+static enum ec_status
+hc_get_keyboard_backlight(struct host_cmd_handler_args *args)
 {
 	struct ec_response_pwm_get_keyboard_backlight *r = args->response;
 
 	r->percent = kblight_get();
-	r->enabled = 1;			/* Deprecated */
+	r->enabled = kblight_get_enabled();
 	args->response_size = sizeof(*r);
 
 	return EC_RES_SUCCESS;
 }
 DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_KEYBOARD_BACKLIGHT,
-		     hc_get_keyboard_backlight,
-		     EC_VER_MASK(0));
+		     hc_get_keyboard_backlight, EC_VER_MASK(0));
 
-enum ec_status hc_set_keyboard_backlight(struct host_cmd_handler_args *args)
+static enum ec_status
+hc_set_keyboard_backlight(struct host_cmd_handler_args *args)
 {
 	const struct ec_params_pwm_set_keyboard_backlight *p = args->params;
 
@@ -151,5 +198,11 @@ enum ec_status hc_set_keyboard_backlight(struct host_cmd_handler_args *args)
 	return EC_RES_SUCCESS;
 }
 DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT,
-		     hc_set_keyboard_backlight,
-		     EC_VER_MASK(0));
+		     hc_set_keyboard_backlight, EC_VER_MASK(0));
+
+#ifdef TEST_BUILD
+uint8_t kblight_get_current_enable(void)
+{
+	return current_enable;
+}
+#endif /* TEST_BUILD */
diff --git a/common/keyboard_mkbp.c b/common/keyboard_mkbp.c
index 9b41ef593e..fa003c31a2 100644
--- a/common/keyboard_mkbp.c
+++ b/common/keyboard_mkbp.c
@@ -1,19 +1,12 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * MKBP keyboard protocol
  */
 
-#include "atomic.h"
-#include "base_state.h"
-#include "button.h"
 #include "chipset.h"
 #include "common.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
 #include "host_command.h"
 #include "keyboard_config.h"
 #include "keyboard_mkbp.h"
@@ -21,29 +14,14 @@
 #include "keyboard_raw.h"
 #include "keyboard_scan.h"
 #include "keyboard_test.h"
-#include "lid_switch.h"
 #include "mkbp_event.h"
-#include "power_button.h"
-#include "system.h"
-#include "tablet_mode.h"
+#include "mkbp_fifo.h"
 #include "task.h"
-#include "timer.h"
 #include "util.h"
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_KEYBOARD, outstr)
-#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ## args)
-
-/*
- * Common FIFO depth.  This needs to be big enough not to overflow if a
- * series of keys is pressed in rapid succession and the kernel is too busy
- * to read them out right away.
- *
- * RAM usage is (depth * #cols); A 16-entry FIFO will consume 16x13=208 bytes,
- * which is non-trivial but not horrible.
- */
-
-#define FIFO_DEPTH 16
+#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ##args)
 
 /* Changes to col,row here need to also be reflected in kernel.
  * drivers/input/mkbp.c ... see KEY_BATTERY.
@@ -52,35 +30,15 @@
 #define BATTERY_KEY_ROW 7
 #define BATTERY_KEY_ROW_MASK BIT(BATTERY_KEY_ROW)
 
-static uint32_t fifo_start;	/* first entry */
-static uint32_t fifo_end;	/* last entry */
-static uint32_t fifo_entries;	/* number of existing entries */
-static struct ec_response_get_next_event fifo[FIFO_DEPTH];
-/*
- * Mutex for critical sections of mkbp_fifo_add(), which is called
- * from various tasks.
- */
-static struct mutex fifo_add_mutex;
-/*
- * Mutex for critical sections of fifo_remove(), which is called from the
- * hostcmd task and from keyboard_clear_buffer().
- */
-static struct mutex fifo_remove_mutex;
-
-/* Button and switch state. */
-static uint32_t mkbp_button_state;
-static uint32_t mkbp_switch_state;
 #ifndef HAS_TASK_KEYSCAN
-/* Keys simulated-pressed */
-static uint8_t __bss_slow simulated_key[KEYBOARD_COLS_MAX];
-uint8_t keyboard_cols = KEYBOARD_COLS_MAX;
+#error "Task KEYSCAN has to be enabled for MKBP keyboard"
 #endif /* !defined(HAS_TASK_KEYSCAN) */
 
 /* Config for mkbp protocol; does not include fields from scan config */
 struct ec_mkbp_protocol_config {
-	uint32_t valid_mask;	/* valid fields */
-	uint8_t flags;		/* some flags (enum mkbp_config_flags) */
-	uint8_t valid_flags;	/* which flags are valid */
+	uint32_t valid_mask; /* valid fields */
+	uint8_t flags; /* some flags (enum mkbp_config_flags) */
+	uint8_t valid_flags; /* which flags are valid */
 
 	/* maximum depth to allow for fifo (0 = no keyscan output) */
 	uint8_t fifo_max_depth;
@@ -88,540 +46,45 @@ struct ec_mkbp_protocol_config {
 
 static struct ec_mkbp_protocol_config config = {
 	.valid_mask = EC_MKBP_VALID_SCAN_PERIOD | EC_MKBP_VALID_POLL_TIMEOUT |
-		EC_MKBP_VALID_MIN_POST_SCAN_DELAY |
-		EC_MKBP_VALID_OUTPUT_SETTLE | EC_MKBP_VALID_DEBOUNCE_DOWN |
-		EC_MKBP_VALID_DEBOUNCE_UP | EC_MKBP_VALID_FIFO_MAX_DEPTH,
+		      EC_MKBP_VALID_MIN_POST_SCAN_DELAY |
+		      EC_MKBP_VALID_OUTPUT_SETTLE |
+		      EC_MKBP_VALID_DEBOUNCE_DOWN | EC_MKBP_VALID_DEBOUNCE_UP |
+		      EC_MKBP_VALID_FIFO_MAX_DEPTH,
 	.valid_flags = EC_MKBP_FLAGS_ENABLE,
 	.flags = EC_MKBP_FLAGS_ENABLE,
 	.fifo_max_depth = FIFO_DEPTH,
 };
 
-static int get_data_size(enum ec_mkbp_event e)
-{
-	switch (e) {
-	case EC_MKBP_EVENT_KEY_MATRIX:
-		return keyboard_cols;
-
-#ifdef CONFIG_HOST_EVENT64
-	case EC_MKBP_EVENT_HOST_EVENT64:
-		return sizeof(uint64_t);
-#endif
-
-	case EC_MKBP_EVENT_HOST_EVENT:
-	case EC_MKBP_EVENT_BUTTON:
-	case EC_MKBP_EVENT_SWITCH:
-	case EC_MKBP_EVENT_SYSRQ:
-		return sizeof(uint32_t);
-	default:
-		/* For unknown types, say it's 0. */
-		return 0;
-	}
-}
-
-/**
- * Pop MKBP event data from FIFO
- *
- * @return EC_SUCCESS if entry popped, EC_ERROR_UNKNOWN if FIFO is empty
- */
-static int fifo_remove(uint8_t *buffp)
-{
-	int size;
-
-	mutex_lock(&fifo_remove_mutex);
-	if (!fifo_entries) {
-		/* no entry remaining in FIFO : return last known state */
-		int last = (fifo_start + FIFO_DEPTH - 1) % FIFO_DEPTH;
-
-		size = get_data_size(fifo[last].event_type);
-
-		memcpy(buffp, &fifo[last].data, size);
-		mutex_unlock(&fifo_remove_mutex);
-
-		/*
-		 * Bail out without changing any FIFO indices and let the
-		 * caller know something strange happened. The buffer will
-		 * will contain the last known state of the keyboard.
-		 */
-		return EC_ERROR_UNKNOWN;
-	}
-
-	/* Return just the event data. */
-	if (buffp) {
-		size = get_data_size(fifo[fifo_start].event_type);
-		/* skip over event_type. */
-		memcpy(buffp, &fifo[fifo_start].data, size);
-	}
-
-	fifo_start = (fifo_start + 1) % FIFO_DEPTH;
-	deprecated_atomic_sub(&fifo_entries, 1);
-	mutex_unlock(&fifo_remove_mutex);
-
-	return EC_SUCCESS;
-}
-
 /*****************************************************************************/
 /* Interface */
 
 void keyboard_clear_buffer(void)
 {
-	int i, new_fifo_entries = 0;
-
-	CPRINTS("clear keyboard MKBP fifo");
-
-	/*
-	 * Order of these locks is important to prevent deadlock since
-	 * mkbp_fifo_add() may call fifo_remove().
-	 */
-	mutex_lock(&fifo_add_mutex);
-	mutex_lock(&fifo_remove_mutex);
-
-	/* Reset the end position */
-	fifo_end = fifo_start;
-
-	for (i = 0; i < fifo_entries; i++) {
-		int cur = (fifo_start + i) % FIFO_DEPTH;
-
-		/* Drop keyboard events */
-		if (fifo[cur].event_type == EC_MKBP_EVENT_KEY_MATRIX)
-			continue;
-
-		/* And move other events to the front */
-		memmove(&fifo[fifo_end], &fifo[cur], sizeof(fifo[cur]));
-		fifo_end = (fifo_end + 1) % FIFO_DEPTH;
-		++new_fifo_entries;
-	}
-	fifo_entries = new_fifo_entries;
-
-	mutex_unlock(&fifo_remove_mutex);
-	mutex_unlock(&fifo_add_mutex);
-}
-
-void mkbp_clear_fifo(void)
-{
-	int i;
-
-	CPRINTS("clear MKBP fifo");
-
-	/*
-	 * Order of these locks is important to prevent deadlock since
-	 * mkbp_fifo_add() may call fifo_remove().
-	 */
-	mutex_lock(&fifo_add_mutex);
-	mutex_lock(&fifo_remove_mutex);
-
-	fifo_start = 0;
-	fifo_end = 0;
-	/* This assignment is safe since both mutexes are held. */
-	fifo_entries = 0;
-	for (i = 0; i < FIFO_DEPTH; i++)
-		memset(&fifo[i], 0, sizeof(struct ec_response_get_next_event));
-
-	mutex_unlock(&fifo_remove_mutex);
-	mutex_unlock(&fifo_add_mutex);
-}
-
-test_mockable int keyboard_fifo_add(const uint8_t *buffp)
-{
-	return mkbp_fifo_add((uint8_t)EC_MKBP_EVENT_KEY_MATRIX, buffp);
+	mkbp_fifo_clear_keyboard();
 }
 
-test_mockable int mkbp_fifo_add(uint8_t event_type, const uint8_t *buffp)
+test_mockable int mkbp_keyboard_add(const uint8_t *buffp)
 {
-	uint8_t size;
-
 	/*
-	 * If the data is a keyboard matrix and the keyboard protocol is not
-	 * enabled, don't save the state to the FIFO or trigger an interrupt.
+	 * If the keyboard protocol is not enabled, don't save the state to
+	 * the FIFO or trigger an interrupt.
 	 */
-	if (!(config.flags & EC_MKBP_FLAGS_ENABLE) &&
-	    (event_type == EC_MKBP_EVENT_KEY_MATRIX))
+	if (!(config.flags & EC_MKBP_FLAGS_ENABLE))
 		return EC_SUCCESS;
 
-	mutex_lock(&fifo_add_mutex);
-	if (fifo_entries >= config.fifo_max_depth) {
-		mutex_unlock(&fifo_add_mutex);
-		CPRINTS("MKBP common FIFO depth %d reached",
-			config.fifo_max_depth);
-
-		return EC_ERROR_OVERFLOW;
-	}
-
-	size = get_data_size(event_type);
-	fifo[fifo_end].event_type = event_type;
-	memcpy(&fifo[fifo_end].data, buffp, size);
-	fifo_end = (fifo_end + 1) % FIFO_DEPTH;
-	deprecated_atomic_add(&fifo_entries, 1);
-
-	/*
-	 * If our event didn't generate an interrupt then the host is still
-	 * asleep. In this case, we don't want to queue our event, except if
-	 * another event just woke the host (and wake is already in progress).
-	 */
-	if (!mkbp_send_event(event_type) && fifo_entries == 1)
-		fifo_remove(NULL);
-
-	mutex_unlock(&fifo_add_mutex);
-	return EC_SUCCESS;
-}
-
-void mkbp_update_switches(uint32_t sw, int state)
-{
-
-	mkbp_switch_state &= ~BIT(sw);
-	mkbp_switch_state |= (!!state << sw);
-
-	mkbp_fifo_add(EC_MKBP_EVENT_SWITCH,
-		      (const uint8_t *)&mkbp_switch_state);
-}
-
-#ifdef CONFIG_LID_SWITCH
-/**
- * Handle lid changing state.
- */
-static void mkbp_lid_change(void)
-{
-	mkbp_update_switches(EC_MKBP_LID_OPEN, lid_is_open());
-}
-DECLARE_HOOK(HOOK_LID_CHANGE, mkbp_lid_change, HOOK_PRIO_LAST);
-DECLARE_HOOK(HOOK_INIT, mkbp_lid_change, HOOK_PRIO_INIT_LID+1);
-#endif
-
-#ifdef CONFIG_TABLET_MODE_SWITCH
-static void mkbp_tablet_mode_change(void)
-{
-	mkbp_update_switches(EC_MKBP_TABLET_MODE, tablet_get_mode());
-}
-DECLARE_HOOK(HOOK_TABLET_MODE_CHANGE, mkbp_tablet_mode_change, HOOK_PRIO_LAST);
-DECLARE_HOOK(HOOK_INIT, mkbp_tablet_mode_change, HOOK_PRIO_INIT_LID+1);
-#endif
-
-#ifdef CONFIG_BASE_ATTACHED_SWITCH
-static void mkbp_base_attached_change(void)
-{
-	mkbp_update_switches(EC_MKBP_BASE_ATTACHED, base_get_state());
-}
-DECLARE_HOOK(HOOK_BASE_ATTACHED_CHANGE, mkbp_base_attached_change,
-	     HOOK_PRIO_LAST);
-DECLARE_HOOK(HOOK_INIT, mkbp_base_attached_change, HOOK_PRIO_INIT_LID+1);
-#endif
-
-void keyboard_update_button(enum keyboard_button_type button, int is_pressed)
-{
-	switch (button) {
-	case KEYBOARD_BUTTON_POWER:
-		mkbp_button_state &= ~BIT(EC_MKBP_POWER_BUTTON);
-		mkbp_button_state |= (is_pressed << EC_MKBP_POWER_BUTTON);
-		break;
-
-	case KEYBOARD_BUTTON_VOLUME_UP:
-		mkbp_button_state &= ~BIT(EC_MKBP_VOL_UP);
-		mkbp_button_state |= (is_pressed << EC_MKBP_VOL_UP);
-		break;
-
-	case KEYBOARD_BUTTON_VOLUME_DOWN:
-		mkbp_button_state &= ~BIT(EC_MKBP_VOL_DOWN);
-		mkbp_button_state |= (is_pressed << EC_MKBP_VOL_DOWN);
-		break;
-
-	case KEYBOARD_BUTTON_RECOVERY:
-		mkbp_button_state &= ~BIT(EC_MKBP_RECOVERY);
-		mkbp_button_state |= (is_pressed << EC_MKBP_RECOVERY);
-		break;
-
-	default:
-		/* ignored. */
-		return;
-	}
-
-	CPRINTS("buttons: %x", mkbp_button_state);
-
-	/* Add the new state to the FIFO. */
-	mkbp_fifo_add(EC_MKBP_EVENT_BUTTON,
-		      (const uint8_t *)&mkbp_button_state);
-}
-
-#ifdef CONFIG_EMULATED_SYSRQ
-void host_send_sysrq(uint8_t key)
-{
-	uint32_t value = key;
-
-	mkbp_fifo_add(EC_MKBP_EVENT_SYSRQ, (const uint8_t *)&value);
-}
-#endif
-
-#ifdef CONFIG_POWER_BUTTON
-/**
- * Handle power button changing state.
- */
-static void keyboard_power_button(void)
-{
-	keyboard_update_button(KEYBOARD_BUTTON_POWER,
-			       power_button_is_pressed());
-}
-DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, keyboard_power_button,
-	     HOOK_PRIO_DEFAULT);
-#endif /* defined(CONFIG_POWER_BUTTON) */
-
-static int get_next_event(uint8_t *out, enum ec_mkbp_event evt)
-{
-	uint8_t t = fifo[fifo_start].event_type;
-	uint8_t size;
-
-	if (!fifo_entries)
-		return -1;
-
-	/*
-	 * We need to peek at the next event to check that we were called with
-	 * the correct event.
-	 */
-	if (t != (uint8_t)evt) {
-		/*
-		 * We were called with the wrong event.  The next element in the
-		 * FIFO's event type doesn't match with what we were called
-		 * with.  Return an error that we're busy.  The caller will need
-		 * to call us with the correct event first.
-		 */
-		return -EC_ERROR_BUSY;
-	}
-
-	fifo_remove(out);
-
-	/* Keep sending events if FIFO is not empty */
-	if (fifo_entries)
-		mkbp_send_event(fifo[fifo_start].event_type);
-
-	/* Return the correct size of the data. */
-	size = get_data_size(t);
-	if (size)
-		return size;
-	else
-		return -EC_ERROR_UNKNOWN;
+	return mkbp_fifo_add((uint8_t)EC_MKBP_EVENT_KEY_MATRIX, buffp);
 }
 
 static int keyboard_get_next_event(uint8_t *out)
 {
-	return get_next_event(out, EC_MKBP_EVENT_KEY_MATRIX);
+	return mkbp_fifo_get_next_event(out, EC_MKBP_EVENT_KEY_MATRIX);
 }
 DECLARE_EVENT_SOURCE(EC_MKBP_EVENT_KEY_MATRIX, keyboard_get_next_event);
 
-static int button_get_next_event(uint8_t *out)
-{
-	return get_next_event(out, EC_MKBP_EVENT_BUTTON);
-}
-DECLARE_EVENT_SOURCE(EC_MKBP_EVENT_BUTTON, button_get_next_event);
-
-static int switch_get_next_event(uint8_t *out)
-{
-	return get_next_event(out, EC_MKBP_EVENT_SWITCH);
-}
-DECLARE_EVENT_SOURCE(EC_MKBP_EVENT_SWITCH, switch_get_next_event);
-
-#ifdef CONFIG_EMULATED_SYSRQ
-static int sysrq_get_next_event(uint8_t *out)
-{
-	return get_next_event(out, EC_MKBP_EVENT_SYSRQ);
-}
-DECLARE_EVENT_SOURCE(EC_MKBP_EVENT_SYSRQ, sysrq_get_next_event);
-#endif
-
-void keyboard_send_battery_key(void)
-{
-	uint8_t state[KEYBOARD_COLS_MAX];
-
-	/* Copy debounced state and add battery pseudo-key */
-	memcpy(state, keyboard_scan_get_state(), sizeof(state));
-	state[BATTERY_KEY_COL] ^= BATTERY_KEY_ROW_MASK;
-
-	/* Add to FIFO only if AP is on or else it will wake from suspend */
-	if (chipset_in_state(CHIPSET_STATE_ON))
-		keyboard_fifo_add(state);
-}
-
 void clear_typematic_key(void)
-{ }
-
-/*****************************************************************************/
-/* Host commands */
-static uint32_t get_supported_buttons(void)
 {
-	uint32_t val = 0;
-
-#ifdef CONFIG_VOLUME_BUTTONS
-	val |= BIT(EC_MKBP_VOL_UP) | BIT(EC_MKBP_VOL_DOWN);
-#endif /* defined(CONFIG_VOLUME_BUTTONS) */
-
-#ifdef CONFIG_DEDICATED_RECOVERY_BUTTON
-	val |= BIT(EC_MKBP_RECOVERY);
-#endif /* defined(CONFIG_DEDICATED_RECOVERY_BUTTON) */
-
-#ifdef CONFIG_POWER_BUTTON
-	val |= BIT(EC_MKBP_POWER_BUTTON);
-#endif /* defined(CONFIG_POWER_BUTTON) */
-
-	return val;
 }
 
-static uint32_t get_supported_switches(void)
-{
-	uint32_t val = 0;
-
-#ifdef CONFIG_LID_SWITCH
-	val |= BIT(EC_MKBP_LID_OPEN);
-#endif
-#ifdef CONFIG_TABLET_MODE_SWITCH
-	val |= BIT(EC_MKBP_TABLET_MODE);
-#endif
-#ifdef CONFIG_BASE_ATTACHED_SWITCH
-	val |= BIT(EC_MKBP_BASE_ATTACHED);
-#endif
-	return val;
-}
-
-static enum ec_status mkbp_get_info(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_mkbp_info *p = args->params;
-
-	if (args->params_size == 0 || p->info_type == EC_MKBP_INFO_KBD) {
-		struct ec_response_mkbp_info *r = args->response;
-
-		/* Version 0 just returns info about the keyboard. */
-		r->rows = KEYBOARD_ROWS;
-		r->cols = keyboard_cols;
-		/* This used to be "switches" which was previously 0. */
-		r->reserved = 0;
-
-		args->response_size = sizeof(struct ec_response_mkbp_info);
-	} else {
-		union ec_response_get_next_data *r = args->response;
-
-		/* Version 1 (other than EC_MKBP_INFO_KBD) */
-		switch (p->info_type) {
-		case EC_MKBP_INFO_SUPPORTED:
-			switch (p->event_type) {
-			case EC_MKBP_EVENT_BUTTON:
-				r->buttons = get_supported_buttons();
-				args->response_size = sizeof(r->buttons);
-				break;
-
-			case EC_MKBP_EVENT_SWITCH:
-				r->switches = get_supported_switches();
-				args->response_size = sizeof(r->switches);
-				break;
-
-			default:
-				/* Don't care for now for other types. */
-				return EC_RES_INVALID_PARAM;
-			}
-			break;
-
-		case EC_MKBP_INFO_CURRENT:
-			switch (p->event_type) {
-#ifdef HAS_TASK_KEYSCAN
-			case EC_MKBP_EVENT_KEY_MATRIX:
-				memcpy(r->key_matrix, keyboard_scan_get_state(),
-				       sizeof(r->key_matrix));
-				args->response_size = sizeof(r->key_matrix);
-				break;
-#endif
-			case EC_MKBP_EVENT_HOST_EVENT:
-				r->host_event = (uint32_t)host_get_events();
-				args->response_size = sizeof(r->host_event);
-				break;
-
-#ifdef CONFIG_HOST_EVENT64
-			case EC_MKBP_EVENT_HOST_EVENT64:
-				r->host_event64 = host_get_events();
-				args->response_size = sizeof(r->host_event64);
-				break;
-#endif
-
-			case EC_MKBP_EVENT_BUTTON:
-				r->buttons = mkbp_button_state;
-				args->response_size = sizeof(r->buttons);
-				break;
-
-			case EC_MKBP_EVENT_SWITCH:
-				r->switches = mkbp_switch_state;
-				args->response_size = sizeof(r->switches);
-				break;
-
-			default:
-				/* Doesn't make sense for other event types. */
-				return EC_RES_INVALID_PARAM;
-			}
-			break;
-
-		default:
-			/* Unsupported query. */
-			return EC_RES_ERROR;
-		}
-	}
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_MKBP_INFO, mkbp_get_info,
-		     EC_VER_MASK(0) | EC_VER_MASK(1));
-
-#ifndef HAS_TASK_KEYSCAN
-/* For boards without a keyscan task, try and simulate keyboard presses. */
-static void simulate_key(int row, int col, int pressed)
-{
-	if ((simulated_key[col] & BIT(row)) == ((pressed ? 1 : 0) << row))
-		return;  /* No change */
-
-	simulated_key[col] &= ~BIT(row);
-	if (pressed)
-		simulated_key[col] |= BIT(row);
-
-	keyboard_fifo_add(simulated_key);
-}
-
-static int command_mkbp_keyboard_press(int argc, char **argv)
-{
-	if (argc == 1) {
-		int i, j;
-
-		ccputs("Simulated keys:\n");
-		for (i = 0; i < keyboard_cols; ++i) {
-			if (simulated_key[i] == 0)
-				continue;
-			for (j = 0; j < KEYBOARD_ROWS; ++j)
-				if (simulated_key[i] & BIT(j))
-					ccprintf("\t%d %d\n", i, j);
-		}
-
-	} else if (argc == 3 || argc == 4) {
-		int r, c, p;
-		char *e;
-
-		c = strtoi(argv[1], &e, 0);
-		if (*e || c < 0 || c >= keyboard_cols)
-			return EC_ERROR_PARAM1;
-
-		r = strtoi(argv[2], &e, 0);
-		if (*e || r < 0 || r >= KEYBOARD_ROWS)
-			return EC_ERROR_PARAM2;
-
-		if (argc == 3) {
-			/* Simulate a press and release */
-			simulate_key(r, c, 1);
-			simulate_key(r, c, 0);
-		} else {
-			p = strtoi(argv[3], &e, 0);
-			if (*e || p < 0 || p > 1)
-				return EC_ERROR_PARAM3;
-
-			simulate_key(r, c, p);
-		}
-	}
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(kbpress, command_mkbp_keyboard_press,
-			"[col row [0 | 1]]",
-			"Simulate keypress");
-#endif /* !defined(HAS_TASK_KEYSCAN) */
-
-#ifdef HAS_TASK_KEYSCAN
 static void set_keyscan_config(const struct ec_mkbp_config *src,
 			       struct ec_mkbp_protocol_config *dst,
 			       uint32_t valid_mask, uint8_t new_flags)
@@ -658,11 +121,11 @@ static void set_keyscan_config(const struct ec_mkbp_config *src,
 	 * fall out of the task_wait_event() in keyboard_scan_task().
 	 */
 	if ((new_flags & EC_MKBP_FLAGS_ENABLE) &&
-			!(dst->flags & EC_MKBP_FLAGS_ENABLE))
+	    !(dst->flags & EC_MKBP_FLAGS_ENABLE))
 		task_wake(TASK_ID_KEYSCAN);
 }
 
-static void get_keyscan_config(struct ec_mkbp_config *dst)
+test_export_static void get_keyscan_config(struct ec_mkbp_config *dst)
 {
 	const struct keyboard_scan_config *ksc = keyboard_scan_get_config();
 
@@ -690,15 +153,14 @@ static void get_keyscan_config(struct ec_mkbp_config *dst)
  *			over to dst->flags
  */
 static void keyscan_copy_config(const struct ec_mkbp_config *src,
-				 struct ec_mkbp_protocol_config *dst,
-				 uint32_t valid_mask, uint8_t valid_flags)
+				struct ec_mkbp_protocol_config *dst,
+				uint32_t valid_mask, uint8_t valid_flags)
 {
 	uint8_t new_flags;
 
 	if (valid_mask & EC_MKBP_VALID_FIFO_MAX_DEPTH) {
 		/* Validity check for fifo depth */
-		dst->fifo_max_depth = MIN(src->fifo_max_depth,
-					  FIFO_DEPTH);
+		dst->fifo_max_depth = MIN(src->fifo_max_depth, FIFO_DEPTH);
 	}
 
 	new_flags = dst->flags & ~valid_flags;
@@ -717,10 +179,11 @@ host_command_mkbp_set_config(struct host_cmd_handler_args *args)
 			    config.valid_mask & req->config.valid_mask,
 			    config.valid_flags & req->config.valid_flags);
 
+	mkbp_fifo_depth_update(config.fifo_max_depth);
+
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_MKBP_SET_CONFIG,
-		     host_command_mkbp_set_config,
+DECLARE_HOST_COMMAND(EC_CMD_MKBP_SET_CONFIG, host_command_mkbp_set_config,
 		     EC_VER_MASK(0));
 
 static enum ec_status
@@ -743,7 +206,5 @@ host_command_mkbp_get_config(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_MKBP_GET_CONFIG,
-		     host_command_mkbp_get_config,
+DECLARE_HOST_COMMAND(EC_CMD_MKBP_GET_CONFIG, host_command_mkbp_get_config,
 		     EC_VER_MASK(0));
-#endif /* HAS_TASK_KEYSCAN */
diff --git a/common/keyboard_scan.c b/common/keyboard_scan.c
index 0e95eb6c34..1568f5ae10 100644
--- a/common/keyboard_scan.c
+++ b/common/keyboard_scan.c
@@ -1,10 +1,12 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Keyboard scanner module for Chrome EC */
 
+#include "adc.h"
+#include "atomic_bit.h"
 #include "chipset.h"
 #include "clock.h"
 #include "common.h"
@@ -18,6 +20,7 @@
 #include "keyboard_scan.h"
 #include "keyboard_test.h"
 #include "lid_switch.h"
+#include "printf.h"
 #include "switch.h"
 #include "system.h"
 #include "tablet_mode.h"
@@ -26,23 +29,27 @@
 #include "usb_api.h"
 #include "util.h"
 
+#ifdef CONFIG_KEYBOARD_MULTIPLE
+#include "keyboard_customization.h"
+#endif
+
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_KEYSCAN, outstr)
-#define CPRINTF(format, args...) cprintf(CC_KEYSCAN, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_KEYSCAN, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_KEYSCAN, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_KEYSCAN, format, ##args)
 
 #ifdef CONFIG_KEYBOARD_DEBUG
 #define CPUTS5(outstr) cputs(CC_KEYSCAN, outstr)
-#define CPRINTS5(format, args...) cprints(CC_KEYBOARD, format, ## args)
+#define CPRINTS5(format, args...) cprints(CC_KEYBOARD, format, ##args)
 #else
 #define CPUTS5(outstr)
 #define CPRINTS5(format, args...)
 #endif
 
-#define SCAN_TIME_COUNT 32  /* Number of last scan times to track */
+#define SCAN_TIME_COUNT 32 /* Number of last scan times to track */
 
 /* If we're waiting for a scan to happen, we'll give it this long */
-#define SCAN_TASK_TIMEOUT_US	(100 * MSEC)
+#define SCAN_TASK_TIMEOUT_US (100 * MSEC)
 
 #ifndef CONFIG_KEYBOARD_POST_SCAN_CLOCKS
 /*
@@ -53,9 +60,7 @@
 #define CONFIG_KEYBOARD_POST_SCAN_CLOCKS 16000
 #endif
 
-#ifndef CONFIG_KEYBOARD_BOARD_CONFIG
-/* Use default keyboard scan config, because board didn't supply one */
-struct keyboard_scan_config keyscan_config = {
+__overridable struct keyboard_scan_config keyscan_config = {
 #ifdef CONFIG_KEYBOARD_COL2_INVERTED
 	/*
 	 * CONFIG_KEYBOARD_COL2_INVERTED is defined for passing the column 2
@@ -78,54 +83,52 @@ struct keyboard_scan_config keyscan_config = {
 		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
 	},
 };
-#endif
-
-/* Boot key list.  Must be in same order as enum boot_key. */
-struct boot_key_entry {
-	uint8_t mask_index;
-	uint8_t mask_value;
-};
 
 #ifdef CONFIG_KEYBOARD_BOOT_KEYS
+#ifndef CONFIG_KEYBOARD_MULTIPLE
 static const struct boot_key_entry boot_key_list[] = {
-	{KEYBOARD_COL_ESC, KEYBOARD_MASK_ESC},   /* Esc */
-	{KEYBOARD_COL_DOWN, KEYBOARD_MASK_DOWN}, /* Down-arrow */
-	{KEYBOARD_COL_LEFT_SHIFT, KEYBOARD_MASK_LEFT_SHIFT}, /* Left-Shift */
+	{ KEYBOARD_COL_ESC, KEYBOARD_ROW_ESC }, /* Esc */
+	{ KEYBOARD_COL_DOWN, KEYBOARD_ROW_DOWN }, /* Down-arrow */
+	{ KEYBOARD_COL_LEFT_SHIFT, KEYBOARD_ROW_LEFT_SHIFT }, /* Left-Shift */
+};
+#else
+struct boot_key_entry boot_key_list[] = {
+	{ KEYBOARD_COL_ESC, KEYBOARD_ROW_ESC }, /* Esc */
+	{ KEYBOARD_COL_DOWN, KEYBOARD_ROW_DOWN }, /* Down-arrow */
+	{ KEYBOARD_COL_LEFT_SHIFT, KEYBOARD_ROW_LEFT_SHIFT }, /* Left-Shift */
 };
+#endif
 static uint32_t boot_key_value = BOOT_KEY_NONE;
 #endif
 
 uint8_t keyboard_cols = KEYBOARD_COLS_MAX;
 
 /* Debounced key matrix */
-static uint8_t __bss_slow debounced_state[KEYBOARD_COLS_MAX];
+static uint8_t debounced_state[KEYBOARD_COLS_MAX];
 /* Mask of keys being debounced */
-static uint8_t __bss_slow debouncing[KEYBOARD_COLS_MAX];
+static uint8_t debouncing[KEYBOARD_COLS_MAX];
 /* Keys simulated-pressed */
-static uint8_t __bss_slow simulated_key[KEYBOARD_COLS_MAX];
-#ifdef CONFIG_KEYBOARD_LANGUAGE_ID
-static uint8_t __bss_slow keyboard_id[KEYBOARD_IDS];
-#endif
+static uint8_t simulated_key[KEYBOARD_COLS_MAX];
 
 /* Times of last scans */
-static uint32_t __bss_slow scan_time[SCAN_TIME_COUNT];
+static uint32_t scan_time[SCAN_TIME_COUNT];
 /* Current scan_time[] index */
-static int __bss_slow scan_time_index;
+static int scan_time_index;
 
 /* Index into scan_time[] when each key started debouncing */
-static uint8_t __bss_slow scan_edge_index[KEYBOARD_COLS_MAX][KEYBOARD_ROWS];
+static uint8_t scan_edge_index[KEYBOARD_COLS_MAX][KEYBOARD_ROWS];
 
 /* Minimum delay between keyboard scans based on current clock frequency */
-static uint32_t __bss_slow post_scan_clock_us;
+static uint32_t post_scan_clock_us;
 
 /*
  * Print all keyboard scan state changes?  Off by default because it generates
  * a lot of debug output, which makes the saved EC console data less useful.
  */
-static int __bss_slow print_state_changes;
+static int print_state_changes;
 
 /* Must init to 0 for scanning at boot */
-static volatile uint32_t __bss_slow disable_scanning_mask;
+static volatile uint32_t disable_scanning_mask;
 
 /* Constantly incrementing counter of the number of times we polled */
 static volatile int kbd_polls;
@@ -133,7 +136,7 @@ static volatile int kbd_polls;
 /* If true, we'll force a keyboard poll */
 static volatile int force_poll;
 
-static int keyboard_scan_is_enabled(void)
+test_export_static int keyboard_scan_is_enabled(void)
 {
 	/* NOTE: this is just an instantaneous glimpse of the variable. */
 	return !disable_scanning_mask;
@@ -141,17 +144,21 @@ static int keyboard_scan_is_enabled(void)
 
 void keyboard_scan_enable(int enable, enum kb_scan_disable_masks mask)
 {
+	atomic_val_t old;
 	/* Access atomically */
 	if (enable) {
-		deprecated_atomic_clear_bits((uint32_t *)&disable_scanning_mask,
-					     mask);
+		old = atomic_clear_bits((atomic_t *)&disable_scanning_mask,
+					mask);
 	} else {
-		deprecated_atomic_or((uint32_t *)&disable_scanning_mask, mask);
+		old = atomic_or((atomic_t *)&disable_scanning_mask, mask);
 		clear_typematic_key();
 	}
 
-	/* Let the task figure things out */
-	task_wake(TASK_ID_KEYSCAN);
+	/* Using atomic_get() causes build errors on some archs */
+	if (old != disable_scanning_mask) {
+		/* If the mask has changed, let the task figure things out */
+		task_wake(TASK_ID_KEYSCAN);
+	}
 }
 
 /**
@@ -163,8 +170,10 @@ void keyboard_scan_enable(int enable, enum kb_scan_disable_masks mask)
 static void print_state(const uint8_t *state, const char *msg)
 {
 	int c;
+	char ts_str[PRINTF_TIMESTAMP_BUF_SIZE];
 
-	CPRINTF("[%pT KB %s:", PRINTF_TIMESTAMP_NOW, msg);
+	snprintf_timestamp_now(ts_str, sizeof(ts_str));
+	CPRINTF("[%s KB %s:", ts_str, msg);
 	for (c = 0; c < keyboard_cols; c++) {
 		if (state[c])
 			CPRINTF(" %02x", state[c]);
@@ -198,6 +207,51 @@ static void ensure_keyboard_scanned(int old_polls)
 		usleep(keyscan_config.scan_period_us);
 }
 
+#ifdef CONFIG_KEYBOARD_SCAN_ADC
+/**
+ * Read KSI ADC rows
+ *
+ * Read each adc channel and look for voltage crossing threshold level
+ */
+static int keyboard_read_adc_rows(void)
+{
+	uint8_t kb_row = 0;
+
+	/* Read each adc channel to build row byte */
+	for (int i = 0; i < KEYBOARD_ROWS; i++) {
+		if (adc_read_channel(ADC_KSI_00 + i) >
+		    keyscan_config.ksi_threshold_mv)
+			kb_row |= (1 << i);
+	}
+
+	return kb_row;
+}
+
+/**
+ * Read refresh key
+ *
+ * Refresh key is detached from rest of the matrix in ADC based
+ * keyboard, so needs to be read through GPIO
+ *
+ * @param state		Destination for new state (must be KEYBOARD_COLS_MAX
+ *			long).
+ */
+static void keyboard_read_refresh_key(uint8_t *state)
+{
+#ifndef CONFIG_KEYBOARD_MULTIPLE
+	if (!gpio_get_level(GPIO_RFR_KEY_L))
+		state[KEYBOARD_COL_REFRESH] |= BIT(KEYBOARD_ROW_REFRESH);
+	else
+		state[KEYBOARD_COL_REFRESH] &= ~BIT(KEYBOARD_ROW_REFRESH);
+#else
+	if (!gpio_get_level(GPIO_RFR_KEY_L))
+		state[key_typ.col_refresh] |= BIT(key_typ.row_refresh);
+	else
+		state[key_typ.col_refresh] &= ~BIT(key_typ.row_refresh);
+#endif
+}
+#endif
+
 /**
  * Simulate a keypress.
  *
@@ -210,7 +264,7 @@ static void simulate_key(int row, int col, int pressed)
 	int old_polls;
 
 	if ((simulated_key[col] & BIT(row)) == ((pressed ? 1 : 0) << row))
-		return;  /* No change */
+		return; /* No change */
 
 	simulated_key[col] ^= BIT(row);
 
@@ -230,8 +284,8 @@ static void simulate_key(int row, int col, int pressed)
 	 * That means it needs to have run and for enough time.
 	 */
 	ensure_keyboard_scanned(old_polls);
-	usleep(pressed ?
-	       keyscan_config.debounce_down_us : keyscan_config.debounce_up_us);
+	usleep(pressed ? keyscan_config.debounce_down_us :
+			 keyscan_config.debounce_up_us);
 	ensure_keyboard_scanned(kbd_polls);
 }
 
@@ -243,10 +297,11 @@ static void simulate_key(int row, int col, int pressed)
  *
  * @param state		Destination for new state (must be KEYBOARD_COLS_MAX
  *			long).
+ * @param at_boot	True if we are reading the boot key state.
  *
  * @return 1 if at least one key is pressed, else zero.
  */
-static int read_matrix(uint8_t *state)
+static int read_matrix(uint8_t *state, bool at_boot)
 {
 	int c;
 	int pressed = 0;
@@ -270,14 +325,52 @@ static int read_matrix(uint8_t *state)
 		udelay(keyscan_config.output_settle_us);
 
 		/* Read the row state */
+#ifdef CONFIG_KEYBOARD_SCAN_ADC
+		state[c] = keyboard_read_adc_rows();
+#else
 		state[c] = keyboard_raw_read_rows();
+#endif
 
 		/* Use simulated keyscan sequence instead if testing active */
 		if (IS_ENABLED(CONFIG_KEYBOARD_TEST))
 			state[c] = keyscan_seq_get_scan(c, state[c]);
 	}
 
-	/* 2. Detect transitional ghost */
+#ifdef KEYBOARD_MASK_PWRBTN
+	/*
+	 * 2. Boot key workaround.
+	 *
+	 * Check if KSI2 or KSI3 is asserted for all columns due to power
+	 * button hold, and ignore it if so.
+	 */
+	if (at_boot) {
+		for (c = 0; c < keyboard_cols; c++) {
+			if (!(state[c] & KEYBOARD_MASK_PWRBTN))
+				break;
+		}
+
+		if (c == keyboard_cols) {
+			for (c = 0; c < keyboard_cols; c++)
+				state[c] &= ~KEYBOARD_MASK_PWRBTN;
+#ifndef CONFIG_KEYBOARD_MULTIPLE
+			state[KEYBOARD_COL_REFRESH] |= KEYBOARD_MASK_PWRBTN;
+#else
+			state[key_typ.col_refresh] |= KEYBOARD_MASK_PWRBTN;
+#endif
+		}
+	}
+#endif
+
+#ifdef CONFIG_KEYBOARD_SCAN_ADC
+	/* Account for the refresh key */
+	keyboard_read_refresh_key(state);
+
+	/*
+	 * KB with ADC support doesn't have transitional ghost,
+	 * this check isn't required
+	 */
+#else
+	/* 3. Detect transitional ghost */
 	for (c = 0; c < keyboard_cols; c++) {
 		int c2;
 
@@ -300,8 +393,9 @@ static int read_matrix(uint8_t *state)
 			}
 		}
 	}
+#endif
 
-	/* 3. Fix result */
+	/* 4. Fix result */
 	for (c = 0; c < keyboard_cols; c++) {
 		/* Add in simulated keypresses */
 		state[c] |= simulated_key[c];
@@ -315,7 +409,6 @@ static int read_matrix(uint8_t *state)
 
 		/* Mask off keys that don't exist on the actual keyboard */
 		state[c] &= keyscan_config.actual_key_mask[c];
-
 	}
 
 	keyboard_raw_drive_column(KEYBOARD_COLUMN_NONE);
@@ -323,38 +416,6 @@ static int read_matrix(uint8_t *state)
 	return pressed ? 1 : 0;
 }
 
-#ifdef CONFIG_KEYBOARD_LANGUAGE_ID
-/**
- * Read the raw keyboard IDs state.
- *
- * Used in pre-init, so must not make task-switching-dependent calls; udelay()
- * is ok because it's a spin-loop.
- *
- * @param id		Destination for keyboard id (must be KEYBOARD_IDS long).
- *
- */
-static void read_matrix_id(uint8_t *id)
-{
-	int c;
-
-	for (c = 0; c < KEYBOARD_IDS; c++) {
-		/* Select the ID pin, then wait a bit for it to settle.
-		 * Caveat: If a keyboard maker puts ID pins right after scan
-		 * columns, we can't support variable column size with a single
-		 * image. */
-		keyboard_raw_drive_column(KEYBOARD_COLS_MAX + c);
-		udelay(keyscan_config.output_settle_us);
-
-		/* Read the row state */
-		id[c] = keyboard_raw_read_rows();
-
-		CPRINTS("Keyboard ID%u: 0x%02x", c, id[c]);
-	}
-
-	keyboard_raw_drive_column(KEYBOARD_COLUMN_NONE);
-}
-#endif
-
 #ifdef CONFIG_KEYBOARD_RUNTIME_KEYS
 
 static uint8_t key_vol_up_row = KEYBOARD_DEFAULT_ROW_VOL_UP;
@@ -380,47 +441,6 @@ static int check_runtime_keys(const uint8_t *state)
 	int num_press = 0;
 	int c;
 
-#ifdef BOARD_SAMUS
-	int16_t chg_override;
-
-	/*
-	 * TODO(crosbug.com/p/34850): remove these hot-keys for samus, should
-	 * be done at higher level than this.
-	 */
-	/*
-	 * On samus, ctrl + search + 0|1|2 sets the active charge port
-	 * by sending the charge override host command. Should only be sent
-	 * when chipset is in S0. Note that 'search' and '1' keys are on
-	 * the same column.
-	 */
-	if ((state[KEYBOARD_COL_LEFT_CTRL] == KEYBOARD_MASK_LEFT_CTRL ||
-	     state[KEYBOARD_COL_RIGHT_CTRL] == KEYBOARD_MASK_RIGHT_CTRL) &&
-	    ((state[KEYBOARD_COL_SEARCH] & KEYBOARD_MASK_SEARCH) ==
-						KEYBOARD_MASK_SEARCH) &&
-	    chipset_in_state(CHIPSET_STATE_ON)) {
-		if (state[KEYBOARD_COL_KEY_0] == KEYBOARD_MASK_KEY_0) {
-			/* Charge from neither port */
-			chg_override = -2;
-			pd_host_command(EC_CMD_PD_CHARGE_PORT_OVERRIDE, 0,
-					&chg_override, 2, NULL, 0);
-			return 0;
-		} else if (state[KEYBOARD_COL_KEY_1] ==
-			   (KEYBOARD_MASK_KEY_1 | KEYBOARD_MASK_SEARCH)) {
-			/* Charge from port 0 (left side) */
-			chg_override = 0;
-			pd_host_command(EC_CMD_PD_CHARGE_PORT_OVERRIDE, 0,
-					&chg_override, 2, NULL, 0);
-			return 0;
-		} else if (state[KEYBOARD_COL_KEY_2] == KEYBOARD_MASK_KEY_2) {
-			/* Charge from port 1 (right side) */
-			chg_override = 1;
-			pd_host_command(EC_CMD_PD_CHARGE_PORT_OVERRIDE, 0,
-					&chg_override, 2, NULL, 0);
-			return 0;
-		}
-	}
-#endif
-
 	/*
 	 * All runtime key combos are (right or left ) alt + volume up + (some
 	 * key NOT on the same col as alt or volume up )
@@ -428,9 +448,15 @@ static int check_runtime_keys(const uint8_t *state)
 	if (state[key_vol_up_col] != KEYBOARD_ROW_TO_MASK(key_vol_up_row))
 		return 0;
 
+#ifndef CONFIG_KEYBOARD_MULTIPLE
 	if (state[KEYBOARD_COL_RIGHT_ALT] != KEYBOARD_MASK_RIGHT_ALT &&
 	    state[KEYBOARD_COL_LEFT_ALT] != KEYBOARD_MASK_LEFT_ALT)
 		return 0;
+#else
+	if (state[key_typ.col_right_alt] != KEYBOARD_MASK_RIGHT_ALT &&
+	    state[key_typ.col_left_alt] != KEYBOARD_MASK_LEFT_ALT)
+		return 0;
+#endif
 
 	/*
 	 * Count number of columns with keys pressed.  We know two columns are
@@ -445,6 +471,7 @@ static int check_runtime_keys(const uint8_t *state)
 	if (num_press != 3)
 		return 0;
 
+#ifndef CONFIG_KEYBOARD_MULTIPLE
 	/* Check individual keys */
 	if (state[KEYBOARD_COL_KEY_R] == KEYBOARD_MASK_KEY_R) {
 		/* R = reboot */
@@ -455,9 +482,24 @@ static int check_runtime_keys(const uint8_t *state)
 	} else if (state[KEYBOARD_COL_KEY_H] == KEYBOARD_MASK_KEY_H) {
 		/* H = hibernate */
 		CPRINTS("KB hibernate");
-		system_hibernate(0, 0);
+		system_enter_hibernate(0, 0);
 		return 1;
 	}
+#else
+	/* Check individual keys */
+	if (state[key_typ.col_key_r] == KEYBOARD_MASK_KEY_R) {
+		/* R = reboot */
+		CPRINTS("KB warm reboot");
+		keyboard_clear_buffer();
+		chipset_reset(CHIPSET_RESET_KB_WARM_REBOOT);
+		return 1;
+	} else if (state[key_typ.col_key_h] == KEYBOARD_MASK_KEY_H) {
+		/* H = hibernate */
+		CPRINTS("KB hibernate");
+		system_enter_hibernate(0, 0);
+		return 1;
+	}
+#endif
 
 	return 0;
 }
@@ -500,6 +542,16 @@ static int has_ghosting(const uint8_t *state)
 	return 0;
 }
 
+/* Inform keyboard module if scanning is enabled */
+test_mockable_static void key_state_changed(int row, int col, uint8_t state)
+{
+	if (!keyboard_scan_is_enabled())
+		return;
+
+	/* No-op for protocols that require full keyboard matrix (e.g. MKBP). */
+	keyboard_state_changed(row, col, !!(state & BIT(row)));
+}
+
 /**
  * Update keyboard state using low-level interface to read keyboard.
  *
@@ -512,7 +564,7 @@ static int check_keys_changed(uint8_t *state)
 	int any_pressed = 0;
 	int c, i;
 	int any_change = 0;
-	static uint8_t __bss_slow new_state[KEYBOARD_COLS_MAX];
+	static uint8_t new_state[KEYBOARD_COLS_MAX];
 	uint32_t tnow = get_time().le.lo;
 
 	/* Save the current scan time */
@@ -521,15 +573,17 @@ static int check_keys_changed(uint8_t *state)
 	scan_time[scan_time_index] = tnow;
 
 	/* Read the raw key state */
-	any_pressed = read_matrix(new_state);
+	any_pressed = read_matrix(new_state, false);
 
-	/* Ignore if so many keys are pressed that we're ghosting. */
-	if (has_ghosting(new_state))
-		return any_pressed;
+	if (!IS_ENABLED(CONFIG_KEYBOARD_SCAN_ADC)) {
+		/* Ignore if so many keys are pressed that we're ghosting. */
+		if (has_ghosting(new_state))
+			return any_pressed;
+	}
 
 	/* Check for changes between previous scan and this one */
 	for (c = 0; c < keyboard_cols; c++) {
-		int diff;
+		int diff = new_state[c] ^ state[c];
 
 		/* Clear debouncing flag, if sufficient time has elapsed. */
 		for (i = 0; i < KEYBOARD_ROWS && debouncing[c]; i++) {
@@ -538,8 +592,22 @@ static int check_keys_changed(uint8_t *state)
 			if (tnow - scan_time[scan_edge_index[c][i]] <
 			    (state[c] ? keyscan_config.debounce_down_us :
 					keyscan_config.debounce_up_us))
-				continue;  /* Not done debouncing */
+				continue; /* Not done debouncing */
 			debouncing[c] &= ~BIT(i);
+
+			if (!IS_ENABLED(CONFIG_KEYBOARD_STRICT_DEBOUNCE))
+				continue;
+			if (!(diff & BIT(i)))
+				/* Debounced but no difference. */
+				continue;
+			any_change = 1;
+			key_state_changed(i, c, new_state[c]);
+			/*
+			 * This makes state[c] == new_state[c] for row i.
+			 * Thus, when diff is calculated below, it won't
+			 * be asserted (for row i).
+			 */
+			state[c] ^= diff & BIT(i);
 		}
 
 		/* Recognize change in state, unless debounce in effect. */
@@ -550,15 +618,10 @@ static int check_keys_changed(uint8_t *state)
 			if (!(diff & BIT(i)))
 				continue;
 			scan_edge_index[c][i] = scan_time_index;
-			any_change = 1;
 
-			/* Inform keyboard module if scanning is enabled */
-			if (keyboard_scan_is_enabled()) {
-				/* This is no-op for protocols that require a
-				 * full keyboard matrix (e.g., MKBP).
-				 */
-				keyboard_state_changed(
-					i, c, !!(new_state[c] & BIT(i)));
+			if (!IS_ENABLED(CONFIG_KEYBOARD_STRICT_DEBOUNCE)) {
+				any_change = 1;
+				key_state_changed(i, c, new_state[c]);
 			}
 		}
 
@@ -569,26 +632,24 @@ static int check_keys_changed(uint8_t *state)
 		 * (up or down), the state bits are only updated if the
 		 * edge was not suppressed due to debouncing.
 		 */
-		state[c] ^= diff;
+		if (!IS_ENABLED(CONFIG_KEYBOARD_STRICT_DEBOUNCE))
+			state[c] ^= diff;
 	}
 
 	if (any_change) {
-
-#ifdef CONFIG_KEYBOARD_SUPPRESS_NOISE
-		/* Suppress keyboard noise */
-		keyboard_suppress_noise();
-#endif
-
 		if (print_state_changes)
 			print_state(state, "state");
 
 #ifdef CONFIG_KEYBOARD_PRINT_SCAN_TIMES
 		/* Print delta times from now back to each previous scan */
-		CPRINTF("[%pT kb deltaT", PRINTF_TIMESTAMP_NOW);
+		char ts_str[PRINTF_TIMESTAMP_BUF_SIZE];
+
+		snprintf_timestamp_now(ts_str, sizeof(ts_str));
+		CPRINTF("[%s kb deltaT", ts_str);
 		for (i = 0; i < SCAN_TIME_COUNT; i++) {
-			int tnew = scan_time[
-				(SCAN_TIME_COUNT + scan_time_index - i) %
-				SCAN_TIME_COUNT];
+			int tnew = scan_time[(SCAN_TIME_COUNT +
+					      scan_time_index - i) %
+					     SCAN_TIME_COUNT];
 			CPRINTF(" %d", tnow - tnew);
 		}
 		CPRINTF("]\n");
@@ -601,7 +662,7 @@ static int check_keys_changed(uint8_t *state)
 #endif
 
 #ifdef CONFIG_KEYBOARD_PROTOCOL_MKBP
-		keyboard_fifo_add(state);
+		mkbp_keyboard_add(state);
 #endif
 	}
 
@@ -610,6 +671,15 @@ static int check_keys_changed(uint8_t *state)
 	return any_pressed;
 }
 
+static uint8_t keyboard_mask_refresh;
+__overridable uint8_t board_keyboard_row_refresh(void)
+{
+	if (IS_ENABLED(CONFIG_KEYBOARD_REFRESH_ROW3))
+		return 3;
+	else
+		return 2;
+}
+
 #ifdef CONFIG_KEYBOARD_BOOT_KEYS
 /*
  * Returns mask of the boot keys that are pressed, with at most the keys used
@@ -625,29 +695,18 @@ static uint32_t check_key_list(const uint8_t *state)
 	/* Make copy of current debounced state. */
 	memcpy(curr_state, state, sizeof(curr_state));
 
-#ifdef KEYBOARD_MASK_PWRBTN
-	/*
-	 * Check if KSI2 or KSI3 is asserted for all columns due to power
-	 * button hold, and ignore it if so.
-	 */
-	for (c = 0; c < keyboard_cols; c++)
-		if ((keyscan_config.actual_key_mask[c] & KEYBOARD_MASK_PWRBTN)
-		    && !(curr_state[c] & KEYBOARD_MASK_PWRBTN))
-			break;
-
-	if (c == keyboard_cols)
-		for (c = 0; c < keyboard_cols; c++)
-			curr_state[c] &= ~KEYBOARD_MASK_PWRBTN;
+#ifndef CONFIG_KEYBOARD_MULTIPLE
+	curr_state[KEYBOARD_COL_REFRESH] &= ~keyboard_mask_refresh;
+#else
+	curr_state[key_typ.col_refresh] &= ~keyboard_mask_refresh;
 #endif
 
-	curr_state[KEYBOARD_COL_REFRESH] &= ~KEYBOARD_MASK_REFRESH;
-
 	/* Update mask with all boot keys that were pressed. */
 	k = boot_key_list;
 	for (c = 0; c < ARRAY_SIZE(boot_key_list); c++, k++) {
-		if (curr_state[k->mask_index] & k->mask_value) {
+		if (curr_state[k->col] & BIT(k->row)) {
 			boot_key_mask |= BIT(c);
-			curr_state[k->mask_index] &= ~k->mask_value;
+			curr_state[k->col] &= ~BIT(k->row);
 		}
 	}
 
@@ -661,6 +720,31 @@ static uint32_t check_key_list(const uint8_t *state)
 	return boot_key_mask;
 }
 
+#ifdef CONFIG_KEYBOARD_SCAN_ADC
+static void read_adc_boot_keys(uint8_t *state)
+{
+	int k;
+
+	for (k = 0; k < ARRAY_SIZE(boot_key_list); k++) {
+		int c = boot_key_list[k].col;
+		int r = boot_key_list[k].row;
+
+		/* Select column, then wait a bit for it to settle */
+		keyboard_raw_drive_column(c);
+		udelay(keyscan_config.output_settle_us);
+
+		if (adc_read_channel(ADC_KSI_00 + r) >
+		    keyscan_config.ksi_threshold_mv)
+			state[c] |= BIT(r);
+	}
+
+	/* Read refresh key */
+	keyboard_read_refresh_key(state);
+
+	keyboard_raw_drive_column(KEYBOARD_COLUMN_NONE);
+}
+#endif
+
 /**
  * Check what boot key is down, if any.
  *
@@ -680,10 +764,16 @@ static uint32_t check_boot_key(const uint8_t *state)
 	if (system_jumped_late())
 		return BOOT_KEY_NONE;
 
-	/* If reset was not caused by reset pin, refresh must be held down */
+/* If reset was not caused by reset pin, refresh must be held down */
+#ifndef CONFIG_KEYBOARD_MULTIPLE
+	if (!(system_get_reset_flags() & EC_RESET_FLAG_RESET_PIN) &&
+	    !(state[KEYBOARD_COL_REFRESH] & keyboard_mask_refresh))
+		return BOOT_KEY_NONE;
+#else
 	if (!(system_get_reset_flags() & EC_RESET_FLAG_RESET_PIN) &&
-	    !(state[KEYBOARD_COL_REFRESH] & KEYBOARD_MASK_REFRESH))
+	    !(state[key_typ.col_refresh] & keyboard_mask_refresh))
 		return BOOT_KEY_NONE;
+#endif
 
 	return check_key_list(state);
 }
@@ -692,7 +782,7 @@ static uint32_t check_boot_key(const uint8_t *state)
 static void keyboard_freq_change(void)
 {
 	post_scan_clock_us = (CONFIG_KEYBOARD_POST_SCAN_CLOCKS * 1000) /
-		(clock_get_freq() / 1000);
+			     (clock_get_freq() / 1000);
 }
 DECLARE_HOOK(HOOK_FREQ_CHANGE, keyboard_freq_change, HOOK_PRIO_DEFAULT);
 
@@ -718,18 +808,31 @@ const uint8_t *keyboard_scan_get_state(void)
 
 void keyboard_scan_init(void)
 {
-	/* Configure GPIO */
-	keyboard_raw_init();
+	if (IS_ENABLED(CONFIG_KEYBOARD_STRICT_DEBOUNCE) &&
+	    keyscan_config.debounce_down_us != keyscan_config.debounce_up_us) {
+		/*
+		 * Strict debouncer is prone to keypress reordering if debounce
+		 * durations for down and up are not equal. crbug.com/547131
+		 */
+		CPRINTS("KB WARN: Debounce durations not equal");
+	}
+
+	/* Configure refresh key matrix */
+	keyboard_mask_refresh =
+		KEYBOARD_ROW_TO_MASK(board_keyboard_row_refresh());
+
+	if (!IS_ENABLED(CONFIG_KEYBOARD_SCAN_ADC))
+		/* Configure GPIO */
+		keyboard_raw_init();
 
 	/* Tri-state the columns */
 	keyboard_raw_drive_column(KEYBOARD_COLUMN_NONE);
 
 	/* Initialize raw state */
-	read_matrix(debounced_state);
-
-#ifdef CONFIG_KEYBOARD_LANGUAGE_ID
-	/* Check keyboard ID state */
-	read_matrix_id(keyboard_id);
+#ifndef CONFIG_KEYBOARD_SCAN_ADC
+	read_matrix(debounced_state, true);
+#else
+	read_adc_boot_keys(debounced_state);
 #endif
 
 #ifdef CONFIG_KEYBOARD_BOOT_KEYS
@@ -771,6 +874,7 @@ void keyboard_scan_task(void *u)
 	uint32_t local_disable_scanning = 0;
 
 	print_state(debounced_state, "init state");
+	poll_deadline.val = 0;
 
 	keyboard_raw_task_start();
 
@@ -792,7 +896,8 @@ void keyboard_scan_task(void *u)
 
 			if (local_disable_scanning != new_disable_scanning)
 				CPRINTS("KB disable_scanning_mask changed: "
-					"0x%08x", new_disable_scanning);
+					"0x%08x",
+					new_disable_scanning);
 
 			if (!new_disable_scanning) {
 				/* Enabled now */
@@ -820,9 +925,16 @@ void keyboard_scan_task(void *u)
 			 * user pressing a key and enable_interrupt()
 			 * starting to pay attention to edges.
 			 */
+#ifndef CONFIG_KEYBOARD_SCAN_ADC
 			if (!local_disable_scanning &&
 			    (keyboard_raw_read_rows() || force_poll))
 				break;
+#else
+			if (!local_disable_scanning &&
+			    (keyboard_read_adc_rows() || force_poll ||
+			     !gpio_get_level(GPIO_RFR_KEY_L)))
+				break;
+#endif
 			else
 				task_wait_event(-1);
 		}
@@ -841,15 +953,16 @@ void keyboard_scan_task(void *u)
 
 			/* Check for keys down */
 			if (check_keys_changed(debounced_state)) {
-				poll_deadline.val = start.val
-					+ keyscan_config.poll_timeout_us;
+				poll_deadline.val =
+					start.val +
+					keyscan_config.poll_timeout_us;
 			} else if (timestamp_expired(poll_deadline, &start)) {
 				break;
 			}
 
 			/* Delay between scans */
 			wait_time = keyscan_config.scan_period_us -
-				(get_time().val - start.val);
+				    (get_time().val - start.val);
 
 			if (wait_time < keyscan_config.min_post_scan_delay_us)
 				wait_time =
@@ -873,7 +986,7 @@ static void keyboard_lid_change(void)
 		keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_CLOSED);
 }
 DECLARE_HOOK(HOOK_LID_CHANGE, keyboard_lid_change, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_INIT, keyboard_lid_change, HOOK_PRIO_INIT_LID + 1);
+DECLARE_HOOK(HOOK_INIT, keyboard_lid_change, HOOK_PRIO_POST_LID);
 
 #endif
 
@@ -911,8 +1024,7 @@ mkbp_command_simulate_key(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_MKBP_SIMULATE_KEY,
-		     mkbp_command_simulate_key,
+DECLARE_HOST_COMMAND(EC_CMD_MKBP_SIMULATE_KEY, mkbp_command_simulate_key,
 		     EC_VER_MASK(0));
 
 #ifdef CONFIG_KEYBOARD_FACTORY_TEST
@@ -928,19 +1040,23 @@ int keyboard_factory_test_scan(void)
 	keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_CLOSED);
 	flags = gpio_get_default_flags(GPIO_KBD_KSO2);
 
+	if (IS_ENABLED(CONFIG_ZEPHYR))
+		/* set all KSI/KSO pins to GPIO_ALT_FUNC_NONE */
+		keybaord_raw_config_alt(0);
+
 	/* Set all of KSO/KSI pins to internal pull-up and input */
 	for (i = 0; i < keyboard_factory_scan_pins_used; i++) {
-
 		if (keyboard_factory_scan_pins[i][0] < 0)
 			continue;
 
 		port = keyboard_factory_scan_pins[i][0];
 		id = keyboard_factory_scan_pins[i][1];
 
-		gpio_set_alternate_function(port, 1 << id,
-					GPIO_ALT_FUNC_NONE);
+		if (!IS_ENABLED(CONFIG_ZEPHYR))
+			gpio_set_alternate_function(port, 1 << id,
+						    GPIO_ALT_FUNC_NONE);
 		gpio_set_flags_by_mask(port, 1 << id,
-			GPIO_INPUT | GPIO_PULL_UP);
+				       GPIO_INPUT | GPIO_PULL_UP);
 	}
 
 	/*
@@ -948,7 +1064,6 @@ int keyboard_factory_test_scan(void)
 	 * going to low level, it indicate the two pins are shorted.
 	 */
 	for (i = 0; i < keyboard_factory_scan_pins_used; i++) {
-
 		if (keyboard_factory_scan_pins[i][0] < 0)
 			continue;
 
@@ -957,23 +1072,25 @@ int keyboard_factory_test_scan(void)
 
 		gpio_set_flags_by_mask(port, 1 << id, GPIO_OUT_LOW);
 
-		for (j = 0; j < i; j++) {
-
-			if (keyboard_factory_scan_pins[j][0] < 0)
+		for (j = 0; j < keyboard_factory_scan_pins_used; j++) {
+			if (keyboard_factory_scan_pins[j][0] < 0 || i == j)
 				continue;
 
 			if (keyboard_raw_is_input_low(
-					keyboard_factory_scan_pins[j][0],
-					keyboard_factory_scan_pins[j][1])) {
+				    keyboard_factory_scan_pins[j][0],
+				    keyboard_factory_scan_pins[j][1])) {
 				shorted = i << 8 | j;
 				goto done;
 			}
 		}
 		gpio_set_flags_by_mask(port, 1 << id,
-			GPIO_INPUT | GPIO_PULL_UP);
+				       GPIO_INPUT | GPIO_PULL_UP);
 	}
 done:
-	gpio_config_module(MODULE_KEYBOARD_SCAN, 1);
+	if (IS_ENABLED(CONFIG_ZEPHYR))
+		keybaord_raw_config_alt(1);
+	else
+		gpio_config_module(MODULE_KEYBOARD_SCAN, 1);
 	gpio_set_flags(GPIO_KBD_KSO2, flags);
 	keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_CLOSED);
 
@@ -998,35 +1115,14 @@ static enum ec_status keyboard_factory_test(struct host_cmd_handler_args *args)
 	return EC_RES_SUCCESS;
 }
 
-DECLARE_HOST_COMMAND(EC_CMD_KEYBOARD_FACTORY_TEST,
-		     keyboard_factory_test,
+DECLARE_HOST_COMMAND(EC_CMD_KEYBOARD_FACTORY_TEST, keyboard_factory_test,
 		     EC_VER_MASK(0));
 #endif
 
-#ifdef CONFIG_KEYBOARD_LANGUAGE_ID
-int keyboard_get_keyboard_id(void)
-{
-	int c;
-	uint32_t id = 0;
-
-	BUILD_ASSERT(sizeof(id) >= KEYBOARD_IDS);
-
-	for (c = 0; c < KEYBOARD_IDS; c++) {
-		/* Check ID ghosting if more than one bit in any KSIs was set */
-		if (keyboard_id[c] & (keyboard_id[c] - 1))
-			/* ID ghosting is found */
-			return KEYBOARD_ID_UNREADABLE;
-		else
-			id |= keyboard_id[c] << (c * 8);
-	}
-	return id;
-}
-#endif
-
 /*****************************************************************************/
 /* Console commands */
 #ifdef CONFIG_CMD_KEYBOARD
-static int command_ksstate(int argc, char **argv)
+static int command_ksstate(int argc, const char **argv)
 {
 	if (argc > 1) {
 		if (!strcasecmp(argv[1], "force")) {
@@ -1040,17 +1136,15 @@ static int command_ksstate(int argc, char **argv)
 	print_state(debounced_state, "debounced ");
 	print_state(debouncing, "debouncing");
 
-	ccprintf("Keyboard scan disable mask: 0x%08x\n",
-		 disable_scanning_mask);
+	ccprintf("Keyboard scan disable mask: 0x%08x\n", disable_scanning_mask);
 	ccprintf("Keyboard scan state printing %s\n",
 		 print_state_changes ? "on" : "off");
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(ksstate, command_ksstate,
-			"ksstate [on | off | force]",
+DECLARE_CONSOLE_COMMAND(ksstate, command_ksstate, "ksstate [on | off | force]",
 			"Show or toggle printing keyboard scan state");
 
-static int command_keyboard_press(int argc, char **argv)
+static int command_keyboard_press(int argc, const char **argv)
 {
 	if (argc == 1) {
 		int i, j;
@@ -1091,7 +1185,29 @@ static int command_keyboard_press(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(kbpress, command_keyboard_press,
-			"[col row [0 | 1]]",
+DECLARE_CONSOLE_COMMAND(kbpress, command_keyboard_press, "[col row [0 | 1]]",
 			"Simulate keypress");
 #endif
+
+#ifdef TEST_BUILD
+__test_only int keyboard_scan_get_print_state_changes(void)
+{
+	return print_state_changes;
+}
+
+__test_only void keyboard_scan_set_print_state_changes(int val)
+{
+	print_state_changes = val;
+}
+
+__test_only void test_keyboard_scan_debounce_reset(void)
+{
+	memset(&debouncing, 0, sizeof(debouncing));
+	memset(&debounced_state, 0, sizeof(debounced_state));
+	memset(&scan_time, 0, sizeof(scan_time));
+	memset(&scan_edge_index, 0, sizeof(scan_edge_index));
+
+	scan_time_index = 0;
+	post_scan_clock_us = 0;
+}
+#endif /* TEST_BUILD */
diff --git a/common/keyboard_test.c b/common/keyboard_test.c
index e7b1dfe501..eb6fc11bdd 100644
--- a/common/keyboard_test.c
+++ b/common/keyboard_test.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2013 The Chromium OS Authors. All rights reserved.
+ * Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,8 +13,8 @@
 #include <util.h>
 
 enum {
-	KEYSCAN_MAX_LENGTH		= 20,
-	KEYSCAN_SEQ_START_DELAY_US	= 10000,
+	KEYSCAN_MAX_LENGTH = 20,
+	KEYSCAN_SEQ_START_DELAY_US = 10000,
 };
 
 static uint8_t keyscan_seq_count;
@@ -151,8 +151,8 @@ static int keyscan_seq_collect(struct ec_params_keyscan_seq_ctrl *req,
 	resp->collect.num_items = end - start;
 
 	for (i = start, ksi = keyscan_items; i < end; i++, ksi++)
-		resp->collect.item[i].flags = ksi->done ?
-						EC_KEYSCAN_SEQ_FLAG_DONE : 0;
+		resp->collect.item[i].flags =
+			ksi->done ? EC_KEYSCAN_SEQ_FLAG_DONE : 0;
 
 	return sizeof(*resp) + resp->collect.num_items;
 }
@@ -186,7 +186,8 @@ static enum ec_status keyscan_seq_ctrl(struct host_cmd_handler_args *args)
 		keyscan_seq_start();
 		break;
 	case EC_KEYSCAN_SEQ_COLLECT:
-		args->response_size = keyscan_seq_collect(&req,
+		args->response_size = keyscan_seq_collect(
+			&req,
 			(struct ec_result_keyscan_seq_ctrl *)args->response);
 		break;
 	default:
@@ -196,6 +197,4 @@ static enum ec_status keyscan_seq_ctrl(struct host_cmd_handler_args *args)
 	return EC_RES_SUCCESS;
 }
 
-DECLARE_HOST_COMMAND(EC_CMD_KEYSCAN_SEQ_CTRL,
-		     keyscan_seq_ctrl,
-		     EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_KEYSCAN_SEQ_CTRL, keyscan_seq_ctrl, EC_VER_MASK(0));
diff --git a/common/keyboard_vivaldi.c b/common/keyboard_vivaldi.c
index 6a614ef87b..44bbff2c11 100644
--- a/common/keyboard_vivaldi.c
+++ b/common/keyboard_vivaldi.c
@@ -1,44 +1,47 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Vivali Keyboard code for Chrome EC */
 
+#include "builtin/assert.h"
+#include "ec_commands.h"
+#include "gpio.h"
 #include "keyboard_8042_sharedlib.h"
 #include "keyboard_scan.h"
-#include "ec_commands.h"
+
+#include <hooks.h>
 #include <host_command.h>
 #include <util.h>
-#include <hooks.h>
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_KEYBOARD, outstr)
-#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ##args)
 
 /*
  * Row Column info for Top row keys T1 - T15. This has been sourced from
  * go/vivaldi-matrix (internal link for vivaldi scan matrix spec).
  */
-static const struct key {
+__overridable const struct key {
 	uint8_t row;
 	uint8_t col;
 } vivaldi_keys[] = {
-	{.row = 0, .col = 2},	/* T1 */
-	{.row = 3, .col = 2},	/* T2 */
-	{.row = 2, .col = 2},	/* T3 */
-	{.row = 1, .col = 2},	/* T4 */
-	{.row = 3, .col = 4},	/* T5 */
-	{.row = 2, .col = 4},	/* T6 */
-	{.row = 1, .col = 4},	/* T7 */
-	{.row = 2, .col = 9},	/* T8 */
-	{.row = 1, .col = 9},	/* T9 */
-	{.row = 0, .col = 4},	/* T10 */
-	{.row = 0, .col = 1},	/* T11 */
-	{.row = 1, .col = 5},	/* T12 */
-	{.row = 3, .col = 5},	/* T13 */
-	{.row = 0, .col = 9},	/* T14 */
-	{.row = 0, .col = 11},	/* T15 */
+	{ .row = 0, .col = 2 }, /* T1 */
+	{ .row = 3, .col = 2 }, /* T2 */
+	{ .row = 2, .col = 2 }, /* T3 */
+	{ .row = 1, .col = 2 }, /* T4 */
+	{ .row = 3, .col = 4 }, /* T5 */
+	{ .row = 2, .col = 4 }, /* T6 */
+	{ .row = 1, .col = 4 }, /* T7 */
+	{ .row = 2, .col = 9 }, /* T8 */
+	{ .row = 1, .col = 9 }, /* T9 */
+	{ .row = 0, .col = 4 }, /* T10 */
+	{ .row = 0, .col = 1 }, /* T11 */
+	{ .row = 1, .col = 5 }, /* T12 */
+	{ .row = 3, .col = 5 }, /* T13 */
+	{ .row = 0, .col = 9 }, /* T14 */
+	{ .row = 0, .col = 11 }, /* T15 */
 };
 BUILD_ASSERT(ARRAY_SIZE(vivaldi_keys) == MAX_TOP_ROW_KEYS);
 
@@ -61,12 +64,15 @@ static const uint16_t action_scancodes[] = {
 	[TK_KBD_BKLIGHT_DOWN] = SCANCODE_KBD_BKLIGHT_DOWN,
 	[TK_KBD_BKLIGHT_UP] = SCANCODE_KBD_BKLIGHT_UP,
 	[TK_PRIVACY_SCRN_TOGGLE] = SCANCODE_PRIVACY_SCRN_TOGGLE,
+	[TK_MICMUTE] = SCANCODE_MICMUTE,
+	[TK_KBD_BKLIGHT_TOGGLE] = SCANCODE_KBD_BKLIGHT_TOGGLE,
+	[TK_MENU] = SCANCODE_MENU,
 };
 
 static const struct ec_response_keybd_config *vivaldi_keybd;
 
-static enum
-ec_status get_vivaldi_keybd_config(struct host_cmd_handler_args *args)
+static enum ec_status
+get_vivaldi_keybd_config(struct host_cmd_handler_args *args)
 {
 	struct ec_response_keybd_config *resp = args->response;
 
@@ -86,8 +92,8 @@ DECLARE_HOST_COMMAND(EC_CMD_GET_KEYBD_CONFIG, get_vivaldi_keybd_config,
  * Boards selecting CONFIG_KEYBOARD_CUSTOMIZATION are likely to not
  * want vivaldi code messing with their customized keyboards.
  */
-__overridable
-const struct ec_response_keybd_config *board_vivaldi_keybd_config(void)
+__overridable const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	return NULL;
 }
@@ -113,8 +119,8 @@ static const struct ec_response_keybd_config default_keybd = {
 	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
 };
 
-__overridable
-const struct ec_response_keybd_config *board_vivaldi_keybd_config(void)
+__overridable const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	return &default_keybd;
 }
@@ -145,7 +151,6 @@ static void vivaldi_init(void)
 	}
 
 	for (i = 0; i < ARRAY_SIZE(vivaldi_keys); i++) {
-
 		uint8_t row, col, *mask;
 		enum action_key key;
 
@@ -153,8 +158,8 @@ static void vivaldi_init(void)
 		col = vivaldi_keys[i].col;
 
 		if (col >= KEYBOARD_COLS_MAX || row >= KEYBOARD_ROWS) {
-			CPRINTS("VIVALDI: Bad (row,col) for T-%u: (%u,%u)",
-				i, row, col);
+			CPRINTS("VIVALDI: Bad (row,col) for T-%u: (%u,%u)", i,
+				row, col);
 			ASSERT(false);
 		}
 
@@ -167,18 +172,16 @@ static void vivaldi_init(void)
 		key = vivaldi_keybd->action_keys[i];
 
 		if (i < vivaldi_keybd->num_top_row_keys && key != TK_ABSENT) {
-
 			/* Enable the mask */
 			*mask |= BIT(row);
 
 			/* Populate the scancode */
 			set_scancode_set2(row, col, action_scancodes[key]);
-			CPRINTS("VIVALDI key-%u (r-%u, c-%u) = scancode-%X",
-				i, row, col, action_scancodes[key]);
+			CPRINTS("VIVALDI key-%u (r-%u, c-%u) = scancode-%X", i,
+				row, col, action_scancodes[key]);
 
 			if (key == TK_VOL_UP)
 				set_vol_up_key(row, col);
-
 		}
 	}
 }
diff --git a/common/lb_common.c b/common/lb_common.c
index 08783997fa..eca21bfb03 100644
--- a/common/lb_common.c
+++ b/common/lb_common.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -97,12 +97,13 @@
 #include "ec_commands.h"
 #include "i2c.h"
 #include "lb_common.h"
+#include "printf.h"
 #include "util.h"
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_LIGHTBAR, outstr)
-#define CPRINTF(format, args...) cprintf(CC_LIGHTBAR, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_LIGHTBAR, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_LIGHTBAR, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_LIGHTBAR, format, ##args)
 
 /******************************************************************************/
 /* How to talk to the controller */
@@ -120,9 +121,8 @@ static inline void controller_write(int ctrl_num, uint8_t reg, uint8_t val)
 	buf[0] = reg;
 	buf[1] = val;
 	ctrl_num = ctrl_num % ARRAY_SIZE(i2c_addr_flags);
-	i2c_xfer_unlocked(I2C_PORT_LIGHTBAR, i2c_addr_flags[ctrl_num],
-			buf, 2, 0, 0,
-			I2C_XFER_SINGLE);
+	i2c_xfer_unlocked(I2C_PORT_LIGHTBAR, i2c_addr_flags[ctrl_num], buf, 2,
+			  0, 0, I2C_XFER_SINGLE);
 }
 
 static inline uint8_t controller_read(int ctrl_num, uint8_t reg)
@@ -132,7 +132,7 @@ static inline uint8_t controller_read(int ctrl_num, uint8_t reg)
 
 	ctrl_num = ctrl_num % ARRAY_SIZE(i2c_addr_flags);
 	rv = i2c_xfer_unlocked(I2C_PORT_LIGHTBAR, i2c_addr_flags[ctrl_num],
-			&reg, 1, buf, 1, I2C_XFER_SINGLE);
+			       &reg, 1, buf, 1, I2C_XFER_SINGLE);
 	return rv ? 0 : buf[0];
 }
 
@@ -149,24 +149,15 @@ static inline uint8_t controller_read(int ctrl_num, uint8_t reg)
  * I've lowered the other colors until they all appear approximately equal
  * brightness when full on. That's still pretty bright and a lot of current
  * drain on the battery, so we'll probably rarely go that high. */
-#define MAX_RED   0x5c
+#define MAX_RED 0x5c
 #define MAX_GREEN 0x30
-#define MAX_BLUE  0x67
-#endif
-#if defined(BOARD_SAMUS)
-/* Samus uses completely different LEDs, so the numbers are different. The
- * Samus LEDs can handle much higher currents, but these constants were
- * calibrated to provide uniform intensity at the level used by Link.
- * See crosbug.com/p/33017 before making any changes. */
-#define MAX_RED   0x34
-#define MAX_GREEN 0x2c
-#define MAX_BLUE  0x40
+#define MAX_BLUE 0x67
 #endif
 #ifdef BOARD_HOST
 /* For testing only */
-#define MAX_RED   0xff
+#define MAX_RED 0xff
 #define MAX_GREEN 0xff
-#define MAX_BLUE  0xff
+#define MAX_BLUE 0xff
 #endif
 
 /* How we'd like to see the driver chips initialized. The controllers have some
@@ -178,20 +169,20 @@ struct initdata_s {
 };
 
 static const struct initdata_s init_vals[] = {
-	{0x04, 0x00},				/* no backlight function */
-	{0x05, 0x3f},				/* xRGBRGB per chip */
-	{0x0f, 0x01},				/* square law looks better */
-	{0x10, 0x3f},				/* enable independent LEDs */
-	{0x11, 0x00},				/* no auto cycling */
-	{0x12, 0x00},				/* no auto cycling */
-	{0x13, 0x00},				/* instant fade in/out */
-	{0x14, 0x00},				/* not using LED 7 */
-	{0x15, 0x00},				/* current for LED 6 (blue) */
-	{0x16, 0x00},				/* current for LED 5 (red) */
-	{0x17, 0x00},				/* current for LED 4 (green) */
-	{0x18, 0x00},				/* current for LED 3 (blue) */
-	{0x19, 0x00},				/* current for LED 2 (red) */
-	{0x1a, 0x00},				/* current for LED 1 (green) */
+	{ 0x04, 0x00 }, /* no backlight function */
+	{ 0x05, 0x3f }, /* xRGBRGB per chip */
+	{ 0x0f, 0x01 }, /* square law looks better */
+	{ 0x10, 0x3f }, /* enable independent LEDs */
+	{ 0x11, 0x00 }, /* no auto cycling */
+	{ 0x12, 0x00 }, /* no auto cycling */
+	{ 0x13, 0x00 }, /* instant fade in/out */
+	{ 0x14, 0x00 }, /* not using LED 7 */
+	{ 0x15, 0x00 }, /* current for LED 6 (blue) */
+	{ 0x16, 0x00 }, /* current for LED 5 (red) */
+	{ 0x17, 0x00 }, /* current for LED 4 (green) */
+	{ 0x18, 0x00 }, /* current for LED 3 (blue) */
+	{ 0x19, 0x00 }, /* current for LED 2 (red) */
+	{ 0x1a, 0x00 }, /* current for LED 1 (green) */
 };
 
 /* Controller register lookup tables. */
@@ -199,9 +190,6 @@ static const uint8_t led_to_ctrl[] = { 1, 1, 0, 0 };
 #ifdef BOARD_BDS
 static const uint8_t led_to_isc[] = { 0x18, 0x15, 0x18, 0x15 };
 #endif
-#ifdef BOARD_SAMUS
-static const uint8_t led_to_isc[] = { 0x15, 0x18, 0x15, 0x18 };
-#endif
 #ifdef BOARD_HOST
 /* For testing only */
 static const uint8_t led_to_isc[] = { 0x15, 0x18, 0x15, 0x18 };
@@ -210,7 +198,7 @@ static const uint8_t led_to_isc[] = { 0x15, 0x18, 0x15, 0x18 };
 /* Scale 0-255 into max value */
 static inline uint8_t scale_abs(int val, int max)
 {
-	return (val * max)/255;
+	return (val * max) / 255;
 }
 
 /* This is the overall brightness control. */
@@ -223,7 +211,7 @@ static uint8_t current[NUM_LEDS][3];
 /* Scale 0-255 by brightness */
 static inline uint8_t scale(int val, int max)
 {
-	return scale_abs((val * brightness)/255, max);
+	return scale_abs((val * brightness) / 255, max);
 }
 
 /* Helper function to set one LED color and remember it for later */
@@ -237,8 +225,8 @@ static void setrgb(int led, int red, int green, int blue)
 	bank = led_to_isc[led];
 	i2c_lock(I2C_PORT_LIGHTBAR, 1);
 	controller_write(ctrl, bank, scale(blue, MAX_BLUE));
-	controller_write(ctrl, bank+1, scale(red, MAX_RED));
-	controller_write(ctrl, bank+2, scale(green, MAX_GREEN));
+	controller_write(ctrl, bank + 1, scale(red, MAX_RED));
+	controller_write(ctrl, bank + 2, scale(green, MAX_GREEN));
 	i2c_lock(I2C_PORT_LIGHTBAR, 0);
 }
 
@@ -287,8 +275,10 @@ uint8_t lb_get_brightness(void)
 void lb_init(int use_lock)
 {
 	int i;
+	char ts_str[PRINTF_TIMESTAMP_BUF_SIZE];
 
-	CPRINTF("[%pT LB_init_vals ", PRINTF_TIMESTAMP_NOW);
+	snprintf_timestamp_now(ts_str, sizeof(ts_str));
+	CPRINTF("[%s LB_init_vals ", ts_str);
 	for (i = 0; i < ARRAY_SIZE(init_vals); i++) {
 		CPRINTF("%c", '0' + i % 10);
 		if (use_lock)
@@ -322,12 +312,10 @@ void lb_on(void)
 	i2c_lock(I2C_PORT_LIGHTBAR, 0);
 }
 
-static const uint8_t dump_reglist[] = {
-	0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
-	0x08, 0x09, 0x0a,			  0x0f,
-	0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
-	0x18, 0x19, 0x1a
-};
+static const uint8_t dump_reglist[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
+					0x06, 0x07, 0x08, 0x09, 0x0a, 0x0f,
+					0x10, 0x11, 0x12, 0x13, 0x14, 0x15,
+					0x16, 0x17, 0x18, 0x19, 0x1a };
 
 /* Helper for host command to dump controller registers */
 void lb_hc_cmd_dump(struct ec_response_lightbar *out)
@@ -335,8 +323,7 @@ void lb_hc_cmd_dump(struct ec_response_lightbar *out)
 	int i;
 	uint8_t reg;
 
-	BUILD_ASSERT(ARRAY_SIZE(dump_reglist) ==
-		     ARRAY_SIZE(out->dump.vals));
+	BUILD_ASSERT(ARRAY_SIZE(dump_reglist) == ARRAY_SIZE(out->dump.vals));
 
 	for (i = 0; i < ARRAY_SIZE(dump_reglist); i++) {
 		reg = dump_reglist[i];
diff --git a/common/led_common.c b/common/led_common.c
index 85879b148f..cabaf22e10 100644
--- a/common/led_common.c
+++ b/common/led_common.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -16,7 +16,7 @@
 
 static uint32_t led_auto_control_flags = ~0x00;
 
-static int led_is_supported(enum ec_led_id led_id)
+__overridable int led_is_supported(enum ec_led_id led_id)
 {
 	int i;
 	static int supported_leds = -1;
@@ -47,6 +47,21 @@ int led_auto_control_is_enabled(enum ec_led_id led_id)
 	return (led_auto_control_flags & LED_AUTO_CONTROL_FLAG(led_id)) != 0;
 }
 
+/* Empty functions cannot be verified in testing to not have had any
+ * side-effects, remove from coverage.
+ * LCOV_EXCL_START
+ */
+__attribute__((weak)) void board_led_auto_control(void)
+{
+	/*
+	 * The projects have only power led won't change the led
+	 * state immediately as the auto command is called for
+	 * they only check the led state while the power state
+	 * is changed.
+	 */
+}
+/* LCOV_EXCL_STOP */
+
 static enum ec_status led_command_control(struct host_cmd_handler_args *args)
 {
 	const struct ec_params_led_control *p = args->params;
@@ -69,6 +84,8 @@ static enum ec_status led_command_control(struct host_cmd_handler_args *args)
 
 	if (p->flags & EC_LED_FLAGS_AUTO) {
 		led_auto_control(p->led_id, 1);
+		if (!IS_ENABLED(CONFIG_LED_ONOFF_STATES))
+			board_led_auto_control();
 	} else {
 		if (led_set_brightness(p->led_id, p->brightness) != EC_SUCCESS)
 			return EC_RES_INVALID_PARAM;
@@ -79,11 +96,13 @@ static enum ec_status led_command_control(struct host_cmd_handler_args *args)
 }
 DECLARE_HOST_COMMAND(EC_CMD_LED_CONTROL, led_command_control, EC_VER_MASK(1));
 
-__attribute__((weak))
-void led_control(enum ec_led_id led_id, enum ec_led_state state)
+#ifndef CONFIG_ZEPHYR
+__attribute__((weak)) void led_control(enum ec_led_id led_id,
+				       enum ec_led_state state)
 {
 	/*
 	 * Default weak implementation that does not affect the state of
 	 * LED. Boards can provide their own implementation.
 	 */
 }
+#endif
diff --git a/common/led_onoff_states.c b/common/led_onoff_states.c
index c82cc2d17c..aa35a127b1 100644
--- a/common/led_onoff_states.c
+++ b/common/led_onoff_states.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -14,30 +14,56 @@
 #include "hooks.h"
 #include "led_common.h"
 #include "led_onoff_states.h"
+#include "system.h"
+#include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
+
+/*
+ * In order to support the battery LED being optional (ex. for Chromeboxes),
+ * set up default battery table, setter, and variables.
+ */
+__overridable struct led_descriptor led_bat_state_table[LED_NUM_STATES]
+						       [LED_NUM_PHASES];
+__overridable const int led_charge_lvl_1;
+__overridable const int led_charge_lvl_2;
+__overridable void led_set_color_battery(enum ec_led_colors color)
+{
+}
+
+#ifndef CONFIG_CHARGER
+/* Include for the sake of compilation */
+int charge_get_percent(void);
+#endif
+
+static int led_get_charge_percent(void)
+{
+	return DIV_ROUND_NEAREST(charge_get_display_charge(), 10);
+}
 
 static enum led_states led_get_state(void)
 {
-	int  charge_lvl;
+	int charge_lvl;
 	enum led_states new_state = LED_NUM_STATES;
 
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
+	if (!IS_ENABLED(CONFIG_CHARGER))
+		return new_state;
+
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
 		/* Get percent charge */
-		charge_lvl = charge_get_percent();
+		charge_lvl = led_get_charge_percent();
 		/* Determine which charge state to use */
 		if (charge_lvl < led_charge_lvl_1)
 			new_state = STATE_CHARGING_LVL_1;
 		else if (charge_lvl < led_charge_lvl_2)
 			new_state = STATE_CHARGING_LVL_2;
+		else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+			new_state = STATE_CHARGING_FULL_S5;
 		else
-			if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-				new_state = STATE_CHARGING_FULL_S5;
-			else
-				new_state = STATE_CHARGING_FULL_CHARGE;
+			new_state = STATE_CHARGING_FULL_CHARGE;
 		break;
-	case PWR_STATE_DISCHARGE_FULL:
+	case LED_PWRS_DISCHARGE_FULL:
 		if (extpower_is_present()) {
 			if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
 				new_state = STATE_CHARGING_FULL_S5;
@@ -45,12 +71,12 @@ static enum led_states led_get_state(void)
 				new_state = STATE_CHARGING_FULL_CHARGE;
 			break;
 		}
-		/* Intentional fall-through */
-	case PWR_STATE_DISCHARGE /* and PWR_STATE_DISCHARGE_FULL */:
+		__fallthrough;
+	case LED_PWRS_DISCHARGE /* and LED_PWRS_DISCHARGE_FULL */:
 		if (chipset_in_state(CHIPSET_STATE_ON)) {
 #ifdef CONFIG_LED_ONOFF_STATES_BAT_LOW
-			if (charge_get_percent() <
-				CONFIG_LED_ONOFF_STATES_BAT_LOW)
+			if (led_get_charge_percent() <
+			    CONFIG_LED_ONOFF_STATES_BAT_LOW)
 				new_state = STATE_DISCHARGE_S0_BAT_LOW;
 			else
 #endif
@@ -60,21 +86,24 @@ static enum led_states led_get_state(void)
 		else
 			new_state = STATE_DISCHARGE_S5;
 		break;
-	case PWR_STATE_ERROR:
+	case LED_PWRS_ERROR:
 		new_state = STATE_BATTERY_ERROR;
 		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
+	case LED_PWRS_CHARGE_NEAR_FULL:
 		if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
 			new_state = STATE_CHARGING_FULL_S5;
 		else
 			new_state = STATE_CHARGING_FULL_CHARGE;
 		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (charge_get_flags() & CHARGE_FLAG_FORCE_IDLE)
-			new_state = STATE_FACTORY_TEST;
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+			new_state = STATE_DISCHARGE_S5;
 		else
 			new_state = STATE_DISCHARGE_S0;
 		break;
+	case LED_PWRS_FORCED_IDLE:
+		new_state = STATE_FACTORY_TEST;
+		break;
 	default:
 		/* Other states don't alter LED behavior */
 		break;
@@ -83,6 +112,11 @@ static enum led_states led_get_state(void)
 	return new_state;
 }
 
+__overridable enum led_states board_led_get_state(enum led_states desired_state)
+{
+	return desired_state;
+}
+
 static void led_update_battery(void)
 {
 	static uint8_t ticks, period;
@@ -90,6 +124,8 @@ static void led_update_battery(void)
 	int phase;
 	enum led_states desired_state = led_get_state();
 
+	desired_state = board_led_get_state(desired_state);
+
 	/*
 	 * We always need to check the current state since the value could
 	 * have been manually overwritten. If we're in a new valid state,
@@ -111,14 +147,14 @@ static void led_update_battery(void)
 		ticks = 0;
 
 		period = led_bat_state_table[led_state][LED_PHASE_0].time +
-			led_bat_state_table[led_state][LED_PHASE_1].time;
-
+			 led_bat_state_table[led_state][LED_PHASE_1].time;
 	}
 
 	/* If this state is undefined, turn the LED off */
 	if (period == 0) {
 		CPRINTS("Undefined LED behavior for battery state %d,"
-			"turning off LED", led_state);
+			"turning off LED",
+			led_state);
 		led_set_color_battery(LED_OFF);
 		return;
 	}
@@ -127,15 +163,24 @@ static void led_update_battery(void)
 	 * Determine which phase of the state table to use. The phase is
 	 * determined if it falls within first phase time duration.
 	 */
-	phase = ticks < led_bat_state_table[led_state][LED_PHASE_0].time ?
-									0 : 1;
+	phase = ticks < led_bat_state_table[led_state][LED_PHASE_0].time ? 0 :
+									   1;
 	ticks = (ticks + 1) % period;
 
 	/* Set the color for the given state and phase */
 	led_set_color_battery(led_bat_state_table[led_state][phase].color);
 }
 
-#ifdef CONFIG_LED_POWER_LED
+/*
+ * In order to support the power LED being optional, set up default power LED
+ * table and setter
+ */
+__overridable const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES];
+__overridable void led_set_color_power(enum ec_led_colors color)
+{
+}
+
 static enum pwr_led_states pwr_led_get_state(void)
 {
 	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
@@ -144,7 +189,10 @@ static enum pwr_led_states pwr_led_get_state(void)
 		else
 			return PWR_LED_STATE_SUSPEND_NO_AC;
 	} else if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
-		return PWR_LED_STATE_OFF;
+		if (system_can_boot_ap())
+			return PWR_LED_STATE_OFF;
+		else
+			return PWR_LED_STATE_OFF_LOW_POWER;
 	} else if (chipset_in_state(CHIPSET_STATE_ON)) {
 		return PWR_LED_STATE_ON;
 	}
@@ -164,20 +212,28 @@ static void led_update_power(void)
 	 * Otherwise, continue to use old state
 	 */
 	if (desired_state != led_state && desired_state < PWR_LED_NUM_STATES) {
+		/*
+		 * Allow optional OFF_LOW_POWER state to fall back to
+		 * OFF not defined, as indicated by no specified phase 0 time.
+		 */
+		if (desired_state == PWR_LED_STATE_OFF_LOW_POWER &&
+		    led_pwr_state_table[desired_state][LED_PHASE_0].time == 0)
+			desired_state = PWR_LED_STATE_OFF;
+
 		/* State is changing */
 		led_state = desired_state;
 		/* Reset ticks and period when state changes */
 		ticks = 0;
 
 		period = led_pwr_state_table[led_state][LED_PHASE_0].time +
-			led_pwr_state_table[led_state][LED_PHASE_1].time;
-
+			 led_pwr_state_table[led_state][LED_PHASE_1].time;
 	}
 
 	/* If this state is undefined, turn the LED off */
 	if (period == 0) {
 		CPRINTS("Undefined LED behavior for power state %d,"
-			"turning off LED", led_state);
+			"turning off LED",
+			led_state);
 		led_set_color_power(LED_OFF);
 		return;
 	}
@@ -186,15 +242,13 @@ static void led_update_power(void)
 	 * Determine which phase of the state table to use. The phase is
 	 * determined if it falls within first phase time duration.
 	 */
-	phase = ticks < led_pwr_state_table[led_state][LED_PHASE_0].time ?
-									0 : 1;
+	phase = ticks < led_pwr_state_table[led_state][LED_PHASE_0].time ? 0 :
+									   1;
 	ticks = (ticks + 1) % period;
 
 	/* Set the color for the given state and phase */
 	led_set_color_power(led_pwr_state_table[led_state][phase].color);
-
 }
-#endif
 
 static void led_init(void)
 {
@@ -203,11 +257,8 @@ static void led_init(void)
 		led_set_color_battery(LED_OFF);
 
 	/* If power LED is enabled, set it to "off" to start with */
-#ifdef CONFIG_LED_POWER_LED
 	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
 		led_set_color_power(LED_OFF);
-#endif /* CONFIG_LED_POWER_LED */
-
 }
 DECLARE_HOOK(HOOK_INIT, led_init, HOOK_PRIO_DEFAULT);
 
@@ -220,9 +271,7 @@ static void led_update(void)
 	 */
 	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
 		led_update_battery();
-#ifdef CONFIG_LED_POWER_LED
 	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
 		led_update_power();
-#endif
 }
 DECLARE_HOOK(HOOK_TICK, led_update, HOOK_PRIO_DEFAULT);
diff --git a/common/led_policy_std.c b/common/led_policy_std.c
index e9fe4568a2..776935f663 100644
--- a/common/led_policy_std.c
+++ b/common/led_policy_std.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -6,14 +6,14 @@
  * This assumes a red/green battery led and a single power led.
  */
 
-#include "gpio.h"
-#include "hooks.h"
 #include "battery.h"
 #include "charge_state.h"
 #include "chipset.h"
+#include "gpio.h"
+#include "hooks.h"
 #include "led_common.h"
-#include "util.h"
 #include "lid_switch.h"
+#include "util.h"
 
 #ifdef CONFIG_LED_BAT_ACTIVE_LOW
 #define BAT_LED_ON 0
@@ -31,8 +31,8 @@
 #define POWER_LED_OFF 0
 #endif
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED, EC_LED_ID_POWER_LED};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -42,7 +42,7 @@ enum led_color {
 	LED_AMBER,
 	LED_GREEN,
 	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static int bat_led_set_color(enum led_color color)
@@ -108,15 +108,18 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 	case EC_LED_ID_BATTERY_LED:
 		gpio_set_level(GPIO_BAT_LED_RED,
 			       (brightness[EC_LED_COLOR_RED] != 0) ?
-					BAT_LED_ON : BAT_LED_OFF);
+				       BAT_LED_ON :
+				       BAT_LED_OFF);
 		gpio_set_level(GPIO_BAT_LED_GREEN,
 			       (brightness[EC_LED_COLOR_GREEN] != 0) ?
-					BAT_LED_ON : BAT_LED_OFF);
+				       BAT_LED_ON :
+				       BAT_LED_OFF);
 		break;
 	case EC_LED_ID_POWER_LED:
 		gpio_set_level(GPIO_POWER_LED,
 			       (brightness[EC_LED_COLOR_WHITE] != 0) ?
-					POWER_LED_ON : POWER_LED_OFF);
+				       POWER_LED_ON :
+				       POWER_LED_OFF);
 		break;
 	default:
 		return EC_ERROR_UNKNOWN;
@@ -124,7 +127,7 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 	return EC_SUCCESS;
 }
 
-#ifdef HAS_TASK_CHIPSET
+#ifdef CONFIG_AP_POWER_CONTROL
 static void std_led_shutdown(void)
 {
 	pwr_led_set_color(LED_OFF);
@@ -149,7 +152,6 @@ static void std_led_set_power(void)
 static void std_led_set_battery(void)
 {
 	static int battery_second;
-	uint32_t chflags = charge_get_flags();
 
 	battery_second++;
 
@@ -157,32 +159,32 @@ static void std_led_set_battery(void)
 	 * Same as the chromeos spec
 	 * Green/Amber for CHARGE_FLAG_FORCE_IDLE
 	 */
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
 		bat_led_set_color(LED_AMBER);
 		break;
-	case PWR_STATE_DISCHARGE:
+	case LED_PWRS_DISCHARGE:
 		if (charge_get_percent() < 3)
-			bat_led_set_color((battery_second & 1)
-					? LED_OFF : LED_AMBER);
+			bat_led_set_color((battery_second & 1) ? LED_OFF :
+								 LED_AMBER);
 		else if (charge_get_percent() < 10)
-			bat_led_set_color((battery_second & 3)
-					? LED_OFF : LED_AMBER);
+			bat_led_set_color((battery_second & 3) ? LED_OFF :
+								 LED_AMBER);
 		else
 			bat_led_set_color(LED_OFF);
 		break;
-	case PWR_STATE_ERROR:
+	case LED_PWRS_ERROR:
 		bat_led_set_color((battery_second & 1) ? LED_OFF : LED_RED);
 		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
+	case LED_PWRS_CHARGE_NEAR_FULL:
 		bat_led_set_color(LED_GREEN);
 		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE. */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			bat_led_set_color(
-				(battery_second & 0x2) ? LED_GREEN : LED_AMBER);
-		else
-			bat_led_set_color(LED_GREEN);
+	case LED_PWRS_IDLE: /* External power connected in IDLE. */
+		bat_led_set_color(LED_GREEN);
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		bat_led_set_color((battery_second & 0x2) ? LED_GREEN :
+							   LED_AMBER);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
@@ -199,4 +201,3 @@ static void led_second(void)
 		std_led_set_battery();
 }
 DECLARE_HOOK(HOOK_SECOND, led_second, HOOK_PRIO_DEFAULT);
-
diff --git a/common/led_pwm.c b/common/led_pwm.c
index cc946ba522..c8c6e72e9f 100644
--- a/common/led_pwm.c
+++ b/common/led_pwm.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -31,7 +31,9 @@
 
 #define PULSE_TICK (250 * MSEC)
 
+#ifndef CONFIG_LED_PWM_TASK_DISABLED
 static uint8_t led_is_pulsing;
+#endif /* CONFIG_LED_PWM_TASK_DISABLED */
 
 static int get_led_id_color(enum pwm_led_id id, int color)
 {
@@ -54,7 +56,7 @@ static int get_led_id_color(enum pwm_led_id id, int color)
 
 void set_pwm_led_color(enum pwm_led_id id, int color)
 {
-	struct pwm_led duty = { 0 };
+	struct pwm_led_color_map duty = { 0 };
 	const struct pwm_led *led = &pwm_leds[id];
 
 	if ((id >= CONFIG_LED_PWM_COUNT) || (id < 0) ||
@@ -67,11 +69,11 @@ void set_pwm_led_color(enum pwm_led_id id, int color)
 		duty.ch2 = led_color_map[color].ch2;
 	}
 
-	if (led->ch0 != (enum pwm_channel)PWM_LED_NO_CHANNEL)
+	if (led->ch0 != PWM_LED_NO_CHANNEL)
 		led->set_duty(led->ch0, duty.ch0);
-	if (led->ch1 != (enum pwm_channel)PWM_LED_NO_CHANNEL)
+	if (led->ch1 != PWM_LED_NO_CHANNEL)
 		led->set_duty(led->ch1, duty.ch1);
-	if (led->ch2 != (enum pwm_channel)PWM_LED_NO_CHANNEL)
+	if (led->ch2 != PWM_LED_NO_CHANNEL)
 		led->set_duty(led->ch2, duty.ch2);
 }
 
@@ -93,17 +95,19 @@ static void set_led_color(int color)
 
 static void set_pwm_led_enable(enum pwm_led_id id, int enable)
 {
+#ifndef CONFIG_ZEPHYR
 	const struct pwm_led *led = &pwm_leds[id];
 
 	if ((id >= CONFIG_LED_PWM_COUNT) || (id < 0))
 		return;
 
-	if (led->ch0 != (enum pwm_channel)PWM_LED_NO_CHANNEL)
+	if (led->ch0 != PWM_LED_NO_CHANNEL)
 		led->enable(led->ch0, enable);
-	if (led->ch1 != (enum pwm_channel)PWM_LED_NO_CHANNEL)
+	if (led->ch1 != PWM_LED_NO_CHANNEL)
 		led->enable(led->ch1, enable);
-	if (led->ch2 != (enum pwm_channel)PWM_LED_NO_CHANNEL)
+	if (led->ch2 != PWM_LED_NO_CHANNEL)
 		led->enable(led->ch2, enable);
+#endif
 }
 
 static void init_leds_off(void)
@@ -118,8 +122,9 @@ static void init_leds_off(void)
 	set_pwm_led_enable(PWM_LED1, 1);
 #endif /* CONFIG_LED_PWM_COUNT >= 2 */
 }
-DECLARE_HOOK(HOOK_INIT, init_leds_off, HOOK_PRIO_INIT_PWM + 1);
+DECLARE_HOOK(HOOK_INIT, init_leds_off, HOOK_PRIO_POST_PWM);
 
+#ifndef CONFIG_LED_PWM_TASK_DISABLED
 static uint8_t pulse_period;
 static uint8_t pulse_ontime;
 static enum ec_led_colors pulse_color;
@@ -160,9 +165,10 @@ static void pulse_leds(enum ec_led_colors color, int ontime, int period)
 	pulse_leds_deferred();
 }
 
+#ifdef CONFIG_BATTERY
 static int show_charge_state(void)
 {
-	enum charge_state chg_st = charge_get_state();
+	enum led_pwr_state chg_st = led_pwr_get_state();
 
 	/*
 	 * The colors listed below are the default, but can be overridden.
@@ -171,17 +177,18 @@ static int show_charge_state(void)
 	 * Solid Green == Charging (near full)
 	 * Fast Flash Red == Charging error or battery not present
 	 */
-	if (chg_st == PWR_STATE_CHARGE) {
+	if (chg_st == LED_PWRS_CHARGE) {
 		led_is_pulsing = 0;
 		set_led_color(CONFIG_LED_PWM_CHARGE_COLOR);
-	} else if (chg_st == PWR_STATE_CHARGE_NEAR_FULL ||
-		   chg_st == PWR_STATE_DISCHARGE_FULL) {
+	} else if (chg_st == LED_PWRS_CHARGE_NEAR_FULL ||
+		   chg_st == LED_PWRS_DISCHARGE_FULL) {
 		led_is_pulsing = 0;
 		set_led_color(CONFIG_LED_PWM_NEAR_FULL_COLOR);
 	} else if ((battery_is_present() != BP_YES) ||
-		   (chg_st == PWR_STATE_ERROR)) {
-		/* 500 ms period, 50% duty cycle. */
-		pulse_leds(CONFIG_LED_PWM_CHARGE_ERROR_COLOR, 1, 2);
+		   (chg_st == LED_PWRS_ERROR)) {
+		/* Ontime and period in PULSE_TICK units. */
+		pulse_leds(CONFIG_LED_PWM_CHARGE_ERROR_COLOR,
+			   LED_CHARGER_ERROR_ON_TIME, LED_CHARGER_ERROR_PERIOD);
 	} else {
 		/* Discharging or not charging. */
 #ifdef CONFIG_LED_PWM_CHARGE_STATE_ONLY
@@ -196,8 +203,10 @@ static int show_charge_state(void)
 	}
 	return 1;
 }
+#endif /* CONFIG_BATTERY */
 
 #ifndef CONFIG_LED_PWM_CHARGE_STATE_ONLY
+#ifdef CONFIG_BATTERY
 static int show_battery_state(void)
 {
 	int batt_percentage = charge_get_percent();
@@ -220,6 +229,7 @@ static int show_battery_state(void)
 	}
 	return 1;
 }
+#endif /* CONFIG_BATTERY */
 
 static int show_chipset_state(void)
 {
@@ -241,13 +251,17 @@ static int show_chipset_state(void)
 
 static void update_leds(void)
 {
+#ifdef CONFIG_BATTERY
 	/* Reflecting the charge state is the highest priority. */
 	if (show_charge_state())
 		return;
+#endif /* CONFIG_BATTERY */
 
 #ifndef CONFIG_LED_PWM_CHARGE_STATE_ONLY
+#ifdef CONFIG_BATTERY
 	if (show_battery_state())
 		return;
+#endif /* CONFIG_BATTERY */
 
 	if (show_chipset_state())
 		return;
@@ -257,8 +271,10 @@ static void update_leds(void)
 }
 DECLARE_HOOK(HOOK_TICK, update_leds, HOOK_PRIO_DEFAULT);
 
+#endif /* CONFIG_LED_PWM_TASK_DISABLED */
+
 #ifdef CONFIG_CMD_LEDTEST
-int command_ledtest(int argc, char **argv)
+static int command_ledtest(int argc, const char **argv)
 {
 	int enable;
 	int pwm_led_id;
@@ -273,9 +289,8 @@ int command_ledtest(int argc, char **argv)
 	led_id = supported_led_ids[pwm_led_id];
 
 	if (argc == 2) {
-		ccprintf("PWM LED %d: led_id=%d, auto_control=%d\n",
-			 pwm_led_id, led_id,
-			 led_auto_control_is_enabled(led_id) != 0);
+		ccprintf("PWM LED %d: led_id=%d, auto_control=%d\n", pwm_led_id,
+			 led_id, led_auto_control_is_enabled(led_id) != 0);
 		return EC_SUCCESS;
 	}
 	if (!parse_bool(argv[2], &enable))
diff --git a/common/lid_angle.c b/common/lid_angle.c
index 295f5486ac..86b6884058 100644
--- a/common/lid_angle.c
+++ b/common/lid_angle.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,7 +19,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_LIDANGLE, outstr)
-#define CPRINTS(format, args...) cprints(CC_LIDANGLE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_LIDANGLE, format, ##args)
 
 /*
  * Define the number of previous lid angle measurements to keep for determining
@@ -50,7 +50,7 @@ static int wake_large_angle = 180;
 static const int wake_small_angle = 13;
 
 /* Define hysteresis value to add stability to the flags. */
-#define LID_ANGLE_HYSTERESIS_DEG  2
+#define LID_ANGLE_HYSTERESIS_DEG 2
 
 /* Define max and min values for wake_large_angle. */
 #define LID_ANGLE_MIN_LARGE_ANGLE 0
@@ -74,8 +74,8 @@ static int lid_in_range_to_enable_peripherals(int ang)
 	else if (wake_large_angle == LID_ANGLE_MAX_LARGE_ANGLE)
 		return 1;
 
-	return  (ang >= (wake_small_angle + LID_ANGLE_HYSTERESIS_DEG)) &&
-		(ang <= (wake_large_angle - LID_ANGLE_HYSTERESIS_DEG));
+	return (ang >= (wake_small_angle + LID_ANGLE_HYSTERESIS_DEG)) &&
+	       (ang <= (wake_large_angle - LID_ANGLE_HYSTERESIS_DEG));
 }
 
 /**
@@ -96,11 +96,10 @@ static int lid_in_range_to_ignore_peripherals(int ang)
 	else if (wake_large_angle == LID_ANGLE_MAX_LARGE_ANGLE)
 		return 0;
 
-	return  (ang <= (wake_small_angle - LID_ANGLE_HYSTERESIS_DEG)) ||
-		(ang >= (wake_large_angle + LID_ANGLE_HYSTERESIS_DEG));
+	return (ang <= (wake_small_angle - LID_ANGLE_HYSTERESIS_DEG)) ||
+	       (ang >= (wake_large_angle + LID_ANGLE_HYSTERESIS_DEG));
 }
 
-
 int lid_angle_get_wake_angle(void)
 {
 	return wake_large_angle;
@@ -125,7 +124,7 @@ void lid_angle_update(int lid_ang)
 
 	/* Record most recent lid angle in circular buffer. */
 	lidangle_buffer[index] = lid_ang;
-	index = (index == LID_ANGLE_BUFFER_SIZE-1) ? 0 : index+1;
+	index = (index == LID_ANGLE_BUFFER_SIZE - 1) ? 0 : index + 1;
 
 	/*
 	 * Manage whether or not peripherals are enabled based on lid angle
@@ -178,9 +177,25 @@ static void suspend_peripherals(void)
 DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, suspend_peripherals, HOOK_PRIO_DEFAULT);
 #endif /* CONFIG_TABLET_MODE */
 
-/* Board level callback was not linked in test build, implement it here. */
 #ifdef TEST_BUILD
-void lid_angle_peripheral_enable(int enable)
+__overridable void lid_angle_peripheral_enable(int enable)
+{
+}
+#else
+__overridable void lid_angle_peripheral_enable(int enable)
 {
+	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
+
+	if (enable) {
+		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
+	} else {
+		/*
+		 * Ensure that the chipset is off before disabling the keyboard.
+		 * When the chipset is on, the EC keeps the keyboard enabled and
+		 * the AP decides whether to ignore input devices or not.
+		 */
+		if (!chipset_in_s0)
+			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
+	}
 }
-#endif
+#endif /* TEST_BUILD */
diff --git a/common/lid_switch.c b/common/lid_switch.c
index 2528e00092..f0231b1ee7 100644
--- a/common/lid_switch.c
+++ b/common/lid_switch.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,17 +16,15 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_SWITCH, outstr)
-#define CPRINTS(format, args...) cprints(CC_SWITCH, format, ## args)
-
-#define LID_DEBOUNCE_US    (30 * MSEC)  /* Debounce time for lid switch */
+#define CPRINTS(format, args...) cprints(CC_SWITCH, format, ##args)
 
 /* if no X-macro is defined for LID switch GPIO, use GPIO_LID_OPEN as default */
 #ifndef CONFIG_LID_SWITCH_GPIO_LIST
 #define CONFIG_LID_SWITCH_GPIO_LIST LID_GPIO(GPIO_LID_OPEN)
 #endif
 
-static int debounced_lid_open;		/* Debounced lid state */
-static int forced_lid_open;	/* Forced lid open */
+static int debounced_lid_open; /* Debounced lid state */
+static int forced_lid_open; /* Forced lid open */
 
 /**
  * Get raw lid switch state.
@@ -89,7 +87,7 @@ static void lid_init(void)
 	if (raw_lid_open())
 		debounced_lid_open = 1;
 
-	/* Enable interrupts, now that we've initialized */
+		/* Enable interrupts, now that we've initialized */
 #define LID_GPIO(gpio) gpio_enable_interrupt(gpio);
 	CONFIG_LID_SWITCH_GPIO_LIST
 #undef LID_GPIO
@@ -120,33 +118,42 @@ void lid_interrupt(enum gpio_signal signal)
 	hook_call_deferred(&lid_change_deferred_data, LID_DEBOUNCE_US);
 }
 
-static int command_lidopen(int argc, char **argv)
+void enable_lid_detect(bool enable)
+{
+	CPRINTS("lid detect %sabled", enable ? "en" : "dis");
+	if (enable) {
+#define LID_GPIO(gpio) gpio_enable_interrupt(gpio);
+		CONFIG_LID_SWITCH_GPIO_LIST
+#undef LID_GPIO
+	} else {
+#define LID_GPIO(gpio) gpio_disable_interrupt(gpio);
+		CONFIG_LID_SWITCH_GPIO_LIST
+#undef LID_GPIO
+		lid_switch_open();
+	}
+}
+
+static int command_lidopen(int argc, const char **argv)
 {
 	lid_switch_open();
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(lidopen, command_lidopen,
-			NULL,
-			"Simulate lid open");
+DECLARE_CONSOLE_COMMAND(lidopen, command_lidopen, NULL, "Simulate lid open");
 
-static int command_lidclose(int argc, char **argv)
+static int command_lidclose(int argc, const char **argv)
 {
 	lid_switch_close();
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(lidclose, command_lidclose,
-			NULL,
-			"Simulate lid close");
+DECLARE_CONSOLE_COMMAND(lidclose, command_lidclose, NULL, "Simulate lid close");
 
-static int command_lidstate(int argc, char **argv)
+static int command_lidstate(int argc, const char **argv)
 {
 	ccprintf("lid state: %s\n", debounced_lid_open ? "open" : "closed");
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(lidstate, command_lidstate,
-			NULL,
-			"Get state of lid");
+DECLARE_CONSOLE_COMMAND(lidstate, command_lidstate, NULL, "Get state of lid");
 
 /**
  * Host command to enable/disable lid opened.
@@ -154,14 +161,15 @@ DECLARE_CONSOLE_COMMAND(lidstate, command_lidstate,
 static enum ec_status hc_force_lid_open(struct host_cmd_handler_args *args)
 {
 	const struct ec_params_force_lid_open *p = args->params;
+	int old_state = forced_lid_open;
 
 	/* Override lid open if necessary */
 	forced_lid_open = p->enabled ? 1 : 0;
 
 	/* Make this take effect immediately; no debounce time */
-	hook_call_deferred(&lid_change_deferred_data, 0);
+	if (forced_lid_open != old_state)
+		hook_call_deferred(&lid_change_deferred_data, 0);
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_FORCE_LID_OPEN, hc_force_lid_open,
-		     EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_FORCE_LID_OPEN, hc_force_lid_open, EC_VER_MASK(0));
diff --git a/common/lightbar.c b/common/lightbar.c
index 03b6fe5ca1..fbc16c80d9 100644
--- a/common/lightbar.c
+++ b/common/lightbar.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2012 The Chromium OS Authors. All rights reserved.
+ * Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -17,8 +17,8 @@
 #include "hooks.h"
 #include "host_command.h"
 #include "lb_common.h"
-#include "lightbar.h"
 #include "lid_switch.h"
+#include "lightbar.h"
 #include "motion_sense.h"
 #include "pwm.h"
 #include "system.h"
@@ -33,11 +33,11 @@
  * optional features in the current version should be marked with flags.
  */
 #define LIGHTBAR_IMPLEMENTATION_VERSION 1
-#define LIGHTBAR_IMPLEMENTATION_FLAGS   0
+#define LIGHTBAR_IMPLEMENTATION_FLAGS 0
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_LIGHTBAR, outstr)
-#define CPRINTS(format, args...) cprints(CC_LIGHTBAR, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_LIGHTBAR, format, ##args)
 
 #define FP_SCALE 10000
 
@@ -61,10 +61,10 @@ static struct p_state {
 	int battery_is_power_on_prevented;
 
 	/* Pattern variables for state S0. */
-	uint16_t w0;				/* primary phase */
-	uint8_t ramp;				/* ramp-in for S3->S0 */
+	uint16_t w0; /* primary phase */
+	uint8_t ramp; /* ramp-in for S3->S0 */
 
-	uint8_t _pad0;				/* next item is __packed */
+	uint8_t _pad0; /* next item is __packed */
 
 	/* Tweakable parameters. */
 	union {
@@ -162,7 +162,7 @@ static const struct lightbar_params_v1 default_params = {
 	},
 };
 
-#define LB_SYSJUMP_TAG 0x4c42			/* "LB" */
+#define LB_SYSJUMP_TAG 0x4c42 /* "LB" */
 static void lightbar_preserve_state(void)
 {
 	system_add_jump_tag(LB_SYSJUMP_TAG, 0, sizeof(st), &st);
@@ -177,10 +177,8 @@ static void lightbar_restore_state(void)
 	old_state = system_get_jump_tag(LB_SYSJUMP_TAG, 0, &size);
 	if (old_state && size == sizeof(st)) {
 		memcpy(&st, old_state, size);
-		CPRINTS("LB state restored: %d %d - %d %d/%d",
-			st.cur_seq, st.prev_seq,
-			st.battery_is_charging,
-			st.battery_percent,
+		CPRINTS("LB state restored: %d %d - %d %d/%d", st.cur_seq,
+			st.prev_seq, st.battery_is_charging, st.battery_percent,
 			st.battery_level);
 	} else {
 		st.cur_seq = st.prev_seq = LIGHTBAR_S5;
@@ -234,7 +232,7 @@ test_export_static int lux_level_to_google_color(const int lux)
 	}
 
 	/* See if we need to decrease brightness */
-	for (i = google_color_id; i < lb_brightness_levels_count ; i++)
+	for (i = google_color_id; i < lb_brightness_levels_count; i++)
 		if (lux >= lb_brightness_levels[i].lux_down)
 			break;
 	if (i > google_color_id) {
@@ -242,7 +240,7 @@ test_export_static int lux_level_to_google_color(const int lux)
 		return 1;
 	}
 	/* See if we need to increase brightness */
-	for (i = google_color_id; i > 0;  i--)
+	for (i = google_color_id; i > 0; i--)
 		if (lux < lb_brightness_levels[i - 1].lux_up)
 			break;
 	if (i < google_color_id) {
@@ -267,7 +265,7 @@ static int get_battery_level(void)
 
 #ifdef HAS_TASK_CHARGER
 	st.battery_percent = pct = charge_get_percent();
-	st.battery_is_charging = (PWR_STATE_DISCHARGE != charge_get_state());
+	st.battery_is_charging = (LED_PWRS_DISCHARGE != led_pwr_get_state());
 	st.battery_is_power_on_prevented = charge_prevent_power_on(0);
 #endif
 
@@ -276,8 +274,8 @@ static int get_battery_level(void)
 
 	/* Use some hysteresis to avoid flickering */
 	if (bl < st.battery_level ||
-	    (bl > st.battery_level
-	     && pct >= (st.p.battery_threshold[st.battery_level] + 1))) {
+	    (bl > st.battery_level &&
+	     pct >= (st.p.battery_threshold[st.battery_level] + 1))) {
 		st.battery_level = bl;
 		change = 1;
 	}
@@ -294,7 +292,7 @@ static int get_battery_level(void)
 	 */
 	if (pwm_get_enabled(PWM_CH_KBLIGHT)) {
 		pct = pwm_get_duty(PWM_CH_KBLIGHT);
-		pct = (255 * pct) / 100;  /* 00 - FF */
+		pct = (255 * pct) / 100; /* 00 - FF */
 		if (pct > st.p.bright_bl_on_max[st.battery_is_charging])
 			pct = st.p.bright_bl_on_max[st.battery_is_charging];
 		else if (pct < st.p.bright_bl_on_min[st.battery_is_charging])
@@ -350,8 +348,7 @@ void demo_is_charging(int ischarge)
 		return;
 
 	st.battery_is_charging = ischarge;
-	CPRINTS("LB demo: battery_is_charging=%d",
-		st.battery_is_charging);
+	CPRINTS("LB demo: battery_is_charging=%d", st.battery_is_charging);
 }
 
 /* Bright/Dim keys */
@@ -409,7 +406,7 @@ static inline int cycle_010(uint8_t i)
 	index = i & 0x3;
 
 	return _ramp_table[bucket] +
-		((_ramp_table[bucket + 1] - _ramp_table[bucket]) * index >> 2);
+	       ((_ramp_table[bucket + 1] - _ramp_table[bucket]) * index >> 2);
 }
 
 /******************************************************************************/
@@ -421,12 +418,12 @@ static uint32_t pending_msg;
 #define PENDING_MSG TASK_EVENT_CUSTOM_BIT(0)
 
 /* Interruptible delay. */
-#define WAIT_OR_RET(A)                                                         \
-	do {                                                                   \
-		uint32_t msg = task_wait_event(A);                             \
-		uint32_t p_msg = pending_msg;                                  \
-		if (msg & PENDING_MSG && p_msg != st.cur_seq)                  \
-			return p_msg;                                          \
+#define WAIT_OR_RET(A)                                        \
+	do {                                                  \
+		uint32_t msg = task_wait_event(A);            \
+		uint32_t p_msg = pending_msg;                 \
+		if (msg & PENDING_MSG && p_msg != st.cur_seq) \
+			return p_msg;                         \
 	} while (0)
 
 /******************************************************************************/
@@ -501,7 +498,7 @@ static uint32_t sequence_S3S0(void)
 	}
 
 	/* Initial conditions */
-	st.w0 = -256;				/* start cycle_npn() quietly */
+	st.w0 = -256; /* start cycle_npn() quietly */
 	st.ramp = 0;
 
 	/* Ready for S0 */
@@ -583,7 +580,7 @@ static uint32_t sequence_S0(void)
 	return 0;
 }
 
-#else  /* just simple google colors */
+#else /* just simple google colors */
 
 static uint32_t sequence_S0(void)
 {
@@ -711,7 +708,6 @@ static uint32_t sequence_S3(void)
 	return 0;
 }
 
-
 /* CPU is powering up. We generally boot fast enough that we don't have time
  * to do anything interesting in the S3 state, but go straight on to S0. */
 static uint32_t sequence_S5S3(void)
@@ -817,12 +813,10 @@ static uint32_t sequence_STOP(void)
 	do {
 		msg = task_wait_event(-1);
 		CPRINTS("LB %s() got pending_msg %d", __func__, pending_msg);
-	} while (msg != PENDING_MSG || (
-			 pending_msg != LIGHTBAR_RUN &&
-			 pending_msg != LIGHTBAR_S0S3 &&
-			 pending_msg != LIGHTBAR_S3 &&
-			 pending_msg != LIGHTBAR_S3S5 &&
-			 pending_msg != LIGHTBAR_S5));
+	} while (msg != PENDING_MSG ||
+		 (pending_msg != LIGHTBAR_RUN && pending_msg != LIGHTBAR_S0S3 &&
+		  pending_msg != LIGHTBAR_S3 && pending_msg != LIGHTBAR_S3S5 &&
+		  pending_msg != LIGHTBAR_S5));
 	return 0;
 }
 
@@ -856,73 +850,47 @@ static const struct {
 	unsigned int delay;
 } konami[] = {
 
-	{1, 0xff, 0xff, 0x00, 0},
-	{2, 0xff, 0xff, 0x00, 100000},
-	{1, 0x00, 0x00, 0x00, 0},
-	{2, 0x00, 0x00, 0x00, 100000},
-
-	{1, 0xff, 0xff, 0x00, 0},
-	{2, 0xff, 0xff, 0x00, 100000},
-	{1, 0x00, 0x00, 0x00, 0},
-	{2, 0x00, 0x00, 0x00, 100000},
-
-	{0, 0x00, 0x00, 0xff, 0},
-	{3, 0x00, 0x00, 0xff, 100000},
-	{0, 0x00, 0x00, 0x00, 0},
-	{3, 0x00, 0x00, 0x00, 100000},
-
-	{0, 0x00, 0x00, 0xff, 0},
-	{3, 0x00, 0x00, 0xff, 100000},
-	{0, 0x00, 0x00, 0x00, 0},
-	{3, 0x00, 0x00, 0x00, 100000},
-
-	{0, 0xff, 0x00, 0x00, 0},
-	{1, 0xff, 0x00, 0x00, 100000},
-	{0, 0x00, 0x00, 0x00, 0},
-	{1, 0x00, 0x00, 0x00, 100000},
-
-	{2, 0x00, 0xff, 0x00, 0},
-	{3, 0x00, 0xff, 0x00, 100000},
-	{2, 0x00, 0x00, 0x00, 0},
-	{3, 0x00, 0x00, 0x00, 100000},
-
-	{0, 0xff, 0x00, 0x00, 0},
-	{1, 0xff, 0x00, 0x00, 100000},
-	{0, 0x00, 0x00, 0x00, 0},
-	{1, 0x00, 0x00, 0x00, 100000},
-
-	{2, 0x00, 0xff, 0x00, 0},
-	{3, 0x00, 0xff, 0x00, 100000},
-	{2, 0x00, 0x00, 0x00, 0},
-	{3, 0x00, 0x00, 0x00, 100000},
-
-	{0, 0x00, 0xff, 0xff, 0},
-	{2, 0x00, 0xff, 0xff, 100000},
-	{0, 0x00, 0x00, 0x00, 0},
-	{2, 0x00, 0x00, 0x00, 150000},
-
-	{1, 0xff, 0x00, 0xff, 0},
-	{3, 0xff, 0x00, 0xff, 100000},
-	{1, 0x00, 0x00, 0x00, 0},
-	{3, 0x00, 0x00, 0x00, 250000},
-
-	{4, 0xff, 0xff, 0xff, 100000},
-	{4, 0x00, 0x00, 0x00, 100000},
-
-	{4, 0xff, 0xff, 0xff, 100000},
-	{4, 0x00, 0x00, 0x00, 100000},
-
-	{4, 0xff, 0xff, 0xff, 100000},
-	{4, 0x00, 0x00, 0x00, 100000},
-
-	{4, 0xff, 0xff, 0xff, 100000},
-	{4, 0x00, 0x00, 0x00, 100000},
-
-	{4, 0xff, 0xff, 0xff, 100000},
-	{4, 0x00, 0x00, 0x00, 100000},
-
-	{4, 0xff, 0xff, 0xff, 100000},
-	{4, 0x00, 0x00, 0x00, 100000},
+	{ 1, 0xff, 0xff, 0x00, 0 },	 { 2, 0xff, 0xff, 0x00, 100000 },
+	{ 1, 0x00, 0x00, 0x00, 0 },	 { 2, 0x00, 0x00, 0x00, 100000 },
+
+	{ 1, 0xff, 0xff, 0x00, 0 },	 { 2, 0xff, 0xff, 0x00, 100000 },
+	{ 1, 0x00, 0x00, 0x00, 0 },	 { 2, 0x00, 0x00, 0x00, 100000 },
+
+	{ 0, 0x00, 0x00, 0xff, 0 },	 { 3, 0x00, 0x00, 0xff, 100000 },
+	{ 0, 0x00, 0x00, 0x00, 0 },	 { 3, 0x00, 0x00, 0x00, 100000 },
+
+	{ 0, 0x00, 0x00, 0xff, 0 },	 { 3, 0x00, 0x00, 0xff, 100000 },
+	{ 0, 0x00, 0x00, 0x00, 0 },	 { 3, 0x00, 0x00, 0x00, 100000 },
+
+	{ 0, 0xff, 0x00, 0x00, 0 },	 { 1, 0xff, 0x00, 0x00, 100000 },
+	{ 0, 0x00, 0x00, 0x00, 0 },	 { 1, 0x00, 0x00, 0x00, 100000 },
+
+	{ 2, 0x00, 0xff, 0x00, 0 },	 { 3, 0x00, 0xff, 0x00, 100000 },
+	{ 2, 0x00, 0x00, 0x00, 0 },	 { 3, 0x00, 0x00, 0x00, 100000 },
+
+	{ 0, 0xff, 0x00, 0x00, 0 },	 { 1, 0xff, 0x00, 0x00, 100000 },
+	{ 0, 0x00, 0x00, 0x00, 0 },	 { 1, 0x00, 0x00, 0x00, 100000 },
+
+	{ 2, 0x00, 0xff, 0x00, 0 },	 { 3, 0x00, 0xff, 0x00, 100000 },
+	{ 2, 0x00, 0x00, 0x00, 0 },	 { 3, 0x00, 0x00, 0x00, 100000 },
+
+	{ 0, 0x00, 0xff, 0xff, 0 },	 { 2, 0x00, 0xff, 0xff, 100000 },
+	{ 0, 0x00, 0x00, 0x00, 0 },	 { 2, 0x00, 0x00, 0x00, 150000 },
+
+	{ 1, 0xff, 0x00, 0xff, 0 },	 { 3, 0xff, 0x00, 0xff, 100000 },
+	{ 1, 0x00, 0x00, 0x00, 0 },	 { 3, 0x00, 0x00, 0x00, 250000 },
+
+	{ 4, 0xff, 0xff, 0xff, 100000 }, { 4, 0x00, 0x00, 0x00, 100000 },
+
+	{ 4, 0xff, 0xff, 0xff, 100000 }, { 4, 0x00, 0x00, 0x00, 100000 },
+
+	{ 4, 0xff, 0xff, 0xff, 100000 }, { 4, 0x00, 0x00, 0x00, 100000 },
+
+	{ 4, 0xff, 0xff, 0xff, 100000 }, { 4, 0x00, 0x00, 0x00, 100000 },
+
+	{ 4, 0xff, 0xff, 0xff, 100000 }, { 4, 0x00, 0x00, 0x00, 100000 },
+
+	{ 4, 0xff, 0xff, 0xff, 100000 }, { 4, 0x00, 0x00, 0x00, 100000 },
 };
 
 static uint32_t sequence_KONAMI_inner(void)
@@ -930,8 +898,8 @@ static uint32_t sequence_KONAMI_inner(void)
 	int i;
 
 	for (i = 0; i < ARRAY_SIZE(konami); i++) {
-		lb_set_rgb(konami[i].led,
-			   konami[i].r, konami[i].g, konami[i].b);
+		lb_set_rgb(konami[i].led, konami[i].r, konami[i].g,
+			   konami[i].b);
 		if (konami[i].delay)
 			WAIT_OR_RET(konami[i].delay);
 	}
@@ -961,7 +929,7 @@ static int range(int val, int min, int ofs)
 {
 	if (val <= min)
 		return 0;
-	if (val >= min+ofs)
+	if (val >= min + ofs)
 		return FP_SCALE;
 	return (val - min) * FP_SCALE / ofs;
 }
@@ -977,7 +945,7 @@ static uint32_t sequence_TAP_inner(int dir)
 	uint32_t elapsed_time = 0;
 	int i, l, ci, max_led;
 	int f_osc, f_mult;
-	int gi, gr, gate[NUM_LEDS] = {0, 0, 0, 0};
+	int gi, gr, gate[NUM_LEDS] = { 0, 0, 0, 0 };
 	uint8_t w = 0;
 #ifdef CONFIG_LIGHTBAR_TAP_DIM_LAST_SEGMENT
 	int f_min, f_delta, f_power;
@@ -1010,7 +978,6 @@ static uint32_t sequence_TAP_inner(int dir)
 			gate[gi - 1] = FP_SCALE;
 
 		for (i = 0; i < NUM_LEDS; i++) {
-
 #ifdef CONFIG_LIGHTBAR_TAP_DIM_LAST_SEGMENT
 			if (max_led > i) {
 				f_mult = FP_SCALE;
@@ -1019,7 +986,8 @@ static uint32_t sequence_TAP_inner(int dir)
 			} else {
 				switch (base_color) {
 				case RED:
-					f_power = range(st.battery_percent, 0,
+					f_power = range(
+						st.battery_percent, 0,
 						st.p.battery_threshold[0] - 1);
 					break;
 				case YELLOW:
@@ -1174,9 +1142,9 @@ static inline uint32_t decode_32(uint32_t *dest)
 		CPRINTS("pc 0x%02x near or out of bounds", pc);
 		return EC_RES_INVALID_PARAM;
 	}
-	*dest  = cur_prog.data[pc++] << 24;
+	*dest = cur_prog.data[pc++] << 24;
 	*dest |= cur_prog.data[pc++] << 16;
-	*dest |= cur_prog.data[pc++] <<  8;
+	*dest |= cur_prog.data[pc++] << 8;
 	*dest |= cur_prog.data[pc++];
 	return EC_SUCCESS;
 }
@@ -1307,7 +1275,6 @@ static uint32_t lightbyte_SET_BRIGHTNESS(void)
  */
 static uint32_t lightbyte_SET_COLOR_SINGLE(void)
 {
-
 	uint8_t packed_loc, led, control, color, value;
 	int i;
 	if (decode_8(&packed_loc) != EC_SUCCESS)
@@ -1369,8 +1336,8 @@ static uint32_t lightbyte_GET_COLORS(void)
 	int i;
 	for (i = 0; i < NUM_LEDS; i++)
 		lb_get_rgb(i, &led_desc[i][LB_CONT_COLOR0][LB_COL_RED],
-			      &led_desc[i][LB_CONT_COLOR0][LB_COL_GREEN],
-			      &led_desc[i][LB_CONT_COLOR0][LB_COL_BLUE]);
+			   &led_desc[i][LB_CONT_COLOR0][LB_COL_GREEN],
+			   &led_desc[i][LB_CONT_COLOR0][LB_COL_BLUE]);
 
 	return EC_SUCCESS;
 }
@@ -1481,15 +1448,21 @@ static uint32_t lightbyte_CYCLE(void)
 
 	for (w = 0;; w++) {
 		for (i = 0; i < NUM_LEDS; i++) {
-			r = get_interp_value(i, LB_COL_RED,
-				cycle_010((w & 0xff) +
-				led_desc[i][LB_CONT_PHASE][LB_COL_RED]));
-			g = get_interp_value(i, LB_COL_GREEN,
+			r = get_interp_value(
+				i, LB_COL_RED,
+				cycle_010(
+					(w & 0xff) +
+					led_desc[i][LB_CONT_PHASE][LB_COL_RED]));
+			g = get_interp_value(
+				i, LB_COL_GREEN,
 				cycle_010((w & 0xff) +
-				led_desc[i][LB_CONT_PHASE][LB_COL_GREEN]));
-			b = get_interp_value(i, LB_COL_BLUE,
+					  led_desc[i][LB_CONT_PHASE]
+						  [LB_COL_GREEN]));
+			b = get_interp_value(
+				i, LB_COL_BLUE,
 				cycle_010((w & 0xff) +
-				led_desc[i][LB_CONT_PHASE][LB_COL_BLUE]));
+					  led_desc[i][LB_CONT_PHASE]
+						  [LB_COL_BLUE]));
 			lb_set_rgb(i, r, g, b);
 		}
 		WAIT_OR_RET(lb_ramp_delay);
@@ -1509,24 +1482,17 @@ static uint32_t lightbyte_HALT(void)
 
 #define OP(NAME, BYTES, MNEMONIC) NAME,
 #include "lightbar_opcode_list.h"
-enum lightbyte_opcode {
-	LIGHTBAR_OPCODE_TABLE
-	MAX_OPCODE
-};
+enum lightbyte_opcode { LIGHTBAR_OPCODE_TABLE MAX_OPCODE };
 #undef OP
 
-#define OP(NAME, BYTES, MNEMONIC) lightbyte_ ## NAME,
+#define OP(NAME, BYTES, MNEMONIC) lightbyte_##NAME,
 #include "lightbar_opcode_list.h"
-static uint32_t (*lightbyte_dispatch[])(void) = {
-	LIGHTBAR_OPCODE_TABLE
-};
+static uint32_t (*lightbyte_dispatch[])(void) = { LIGHTBAR_OPCODE_TABLE };
 #undef OP
 
 #define OP(NAME, BYTES, MNEMONIC) MNEMONIC,
 #include "lightbar_opcode_list.h"
-static const char * const lightbyte_names[] = {
-	LIGHTBAR_OPCODE_TABLE
-};
+static const char *const lightbyte_names[] = { LIGHTBAR_OPCODE_TABLE };
 #undef OP
 
 static uint32_t sequence_PROGRAM(void)
@@ -1563,7 +1529,7 @@ static uint32_t sequence_PROGRAM(void)
 			return EC_RES_INVALID_PARAM;
 		} else {
 			CPRINTS("LB PROGRAM pc: 0x%02x, opcode 0x%02x -> %s",
-				 old_pc, next_inst, lightbyte_names[next_inst]);
+				old_pc, next_inst, lightbyte_names[next_inst]);
 			rc = lightbyte_dispatch[next_inst]();
 			if (rc) {
 				lb_set_brightness(saved_brightness);
@@ -1588,15 +1554,16 @@ static inline int is_normal_sequence(enum lightbar_sequence seq)
 
 /* Link each sequence with a command to invoke it. */
 struct lightbar_cmd_t {
-	const char * const string;
+	const char *const string;
 	uint32_t (*sequence)(void);
 };
 
-#define LBMSG(state) { #state, sequence_##state }
+#define LBMSG(state)                     \
+	{                                \
+		#state, sequence_##state \
+	}
 #include "lightbar_msg_list.h"
-static struct lightbar_cmd_t lightbar_cmds[] = {
-	LIGHTBAR_MSG_LIST
-};
+static struct lightbar_cmd_t lightbar_cmds[] = { LIGHTBAR_MSG_LIST };
 #undef LBMSG
 
 void lightbar_task(void)
@@ -1608,9 +1575,9 @@ void lightbar_task(void)
 	lightbar_restore_state();
 
 	while (1) {
-		CPRINTS("LB running cur_seq %d %s. prev_seq %d %s",
-			st.cur_seq, lightbar_cmds[st.cur_seq].string,
-			st.prev_seq, lightbar_cmds[st.prev_seq].string);
+		CPRINTS("LB running cur_seq %d %s. prev_seq %d %s", st.cur_seq,
+			lightbar_cmds[st.cur_seq].string, st.prev_seq,
+			lightbar_cmds[st.prev_seq].string);
 		next_seq = lightbar_cmds[st.cur_seq].sequence();
 		if (next_seq) {
 			CPRINTS("LB cur_seq %d %s returned pending msg %d %s",
@@ -1622,8 +1589,8 @@ void lightbar_task(void)
 				st.cur_seq = next_seq;
 			}
 		} else {
-			CPRINTS("LB cur_seq %d %s returned value 0",
-				st.cur_seq, lightbar_cmds[st.cur_seq].string);
+			CPRINTS("LB cur_seq %d %s returned value 0", st.cur_seq,
+				lightbar_cmds[st.cur_seq].string);
 			switch (st.cur_seq) {
 			case LIGHTBAR_S5S3:
 				st.cur_seq = LIGHTBAR_S3;
@@ -1644,6 +1611,7 @@ void lightbar_task(void)
 			case LIGHTBAR_TAP:
 			case LIGHTBAR_PROGRAM:
 				st.cur_seq = st.prev_seq;
+				break;
 			default:
 				break;
 			}
@@ -1658,7 +1626,7 @@ void lightbar_sequence_f(enum lightbar_sequence num, const char *f)
 		CPRINTS("LB %s() requests %d %s", f, num,
 			lightbar_cmds[num].string);
 		pending_msg = num;
-		task_set_event(TASK_ID_LIGHTBAR, PENDING_MSG, 0);
+		task_set_event(TASK_ID_LIGHTBAR, PENDING_MSG);
 	} else
 		CPRINTS("LB %s() requests %d - ignored", f, num);
 }
@@ -1733,16 +1701,12 @@ static enum ec_status lpc_cmd_lightbar(struct host_cmd_handler_args *args)
 		lb_hc_cmd_reg(in);
 		break;
 	case LIGHTBAR_CMD_SET_RGB:
-		lb_set_rgb(in->set_rgb.led,
-			   in->set_rgb.red,
-			   in->set_rgb.green,
+		lb_set_rgb(in->set_rgb.led, in->set_rgb.red, in->set_rgb.green,
 			   in->set_rgb.blue);
 		break;
 	case LIGHTBAR_CMD_GET_RGB:
-		rv = lb_get_rgb(in->get_rgb.led,
-				&out->get_rgb.red,
-				&out->get_rgb.green,
-				&out->get_rgb.blue);
+		rv = lb_get_rgb(in->get_rgb.led, &out->get_rgb.red,
+				&out->get_rgb.green, &out->get_rgb.blue);
 		if (rv == EC_RES_SUCCESS)
 			args->response_size = sizeof(out->get_rgb);
 		return rv;
@@ -1777,8 +1741,7 @@ static enum ec_status lpc_cmd_lightbar(struct host_cmd_handler_args *args)
 		break;
 	case LIGHTBAR_CMD_SET_PROGRAM:
 		CPRINTS("LB_set_program");
-		memcpy(&next_prog,
-		       &in->set_program,
+		memcpy(&next_prog, &in->set_program,
 		       sizeof(struct lightbar_program));
 		break;
 	case LIGHTBAR_CMD_VERSION:
@@ -1801,28 +1764,24 @@ static enum ec_status lpc_cmd_lightbar(struct host_cmd_handler_args *args)
 		break;
 	case LIGHTBAR_CMD_GET_PARAMS_V2_TIMING:
 		CPRINTS("LB_get_params_v2_timing");
-		memcpy(&out->get_params_v2_timing,
-		       &st.p_v2.timing,
+		memcpy(&out->get_params_v2_timing, &st.p_v2.timing,
 		       sizeof(st.p_v2.timing));
 		args->response_size = sizeof(out->get_params_v2_timing);
 		break;
 	case LIGHTBAR_CMD_SET_PARAMS_V2_TIMING:
 		CPRINTS("LB_set_params_v2_timing");
-		memcpy(&st.p_v2.timing,
-		       &in->set_v2par_timing,
+		memcpy(&st.p_v2.timing, &in->set_v2par_timing,
 		       sizeof(struct lightbar_params_v2_timing));
 		break;
 	case LIGHTBAR_CMD_GET_PARAMS_V2_TAP:
 		CPRINTS("LB_get_params_v2_tap");
-		memcpy(&out->get_params_v2_tap,
-		       &st.p_v2.tap,
+		memcpy(&out->get_params_v2_tap, &st.p_v2.tap,
 		       sizeof(struct lightbar_params_v2_tap));
 		args->response_size = sizeof(out->get_params_v2_tap);
 		break;
 	case LIGHTBAR_CMD_SET_PARAMS_V2_TAP:
 		CPRINTS("LB_set_params_v2_tap");
-		memcpy(&st.p_v2.tap,
-		       &in->set_v2par_tap,
+		memcpy(&st.p_v2.tap, &in->set_v2par_tap,
 		       sizeof(struct lightbar_params_v2_tap));
 		break;
 	case LIGHTBAR_CMD_GET_PARAMS_V2_OSCILLATION:
@@ -1833,47 +1792,40 @@ static enum ec_status lpc_cmd_lightbar(struct host_cmd_handler_args *args)
 		break;
 	case LIGHTBAR_CMD_SET_PARAMS_V2_OSCILLATION:
 		CPRINTS("LB_set_params_v2_oscillation");
-		memcpy(&st.p_v2.osc,
-		       &in->set_v2par_osc,
+		memcpy(&st.p_v2.osc, &in->set_v2par_osc,
 		       sizeof(struct lightbar_params_v2_oscillation));
 		break;
 	case LIGHTBAR_CMD_GET_PARAMS_V2_BRIGHTNESS:
 		CPRINTS("LB_get_params_v2_brightness");
-		memcpy(&out->get_params_v2_bright,
-		       &st.p_v2.bright,
+		memcpy(&out->get_params_v2_bright, &st.p_v2.bright,
 		       sizeof(struct lightbar_params_v2_brightness));
 		args->response_size = sizeof(out->get_params_v2_bright);
 		break;
 	case LIGHTBAR_CMD_SET_PARAMS_V2_BRIGHTNESS:
 		CPRINTS("LB_set_params_v2_brightness");
-		memcpy(&st.p_v2.bright,
-		       &in->set_v2par_bright,
+		memcpy(&st.p_v2.bright, &in->set_v2par_bright,
 		       sizeof(struct lightbar_params_v2_brightness));
 		break;
 	case LIGHTBAR_CMD_GET_PARAMS_V2_THRESHOLDS:
 		CPRINTS("LB_get_params_v2_thlds");
-		memcpy(&out->get_params_v2_thlds,
-		       &st.p_v2.thlds,
+		memcpy(&out->get_params_v2_thlds, &st.p_v2.thlds,
 		       sizeof(struct lightbar_params_v2_thresholds));
 		args->response_size = sizeof(out->get_params_v2_thlds);
 		break;
 	case LIGHTBAR_CMD_SET_PARAMS_V2_THRESHOLDS:
 		CPRINTS("LB_set_params_v2_thlds");
-		memcpy(&st.p_v2.thlds,
-		       &in->set_v2par_thlds,
+		memcpy(&st.p_v2.thlds, &in->set_v2par_thlds,
 		       sizeof(struct lightbar_params_v2_thresholds));
 		break;
 	case LIGHTBAR_CMD_GET_PARAMS_V2_COLORS:
 		CPRINTS("LB_get_params_v2_colors");
-		memcpy(&out->get_params_v2_colors,
-		       &st.p_v2.colors,
+		memcpy(&out->get_params_v2_colors, &st.p_v2.colors,
 		       sizeof(struct lightbar_params_v2_colors));
 		args->response_size = sizeof(out->get_params_v2_colors);
 		break;
 	case LIGHTBAR_CMD_SET_PARAMS_V2_COLORS:
 		CPRINTS("LB_set_params_v2_colors");
-		memcpy(&st.p_v2.colors,
-		       &in->set_v2par_colors,
+		memcpy(&st.p_v2.colors, &in->set_v2par_colors,
 		       sizeof(struct lightbar_params_v2_colors));
 		break;
 	default:
@@ -1884,9 +1836,7 @@ static enum ec_status lpc_cmd_lightbar(struct host_cmd_handler_args *args)
 	return EC_RES_SUCCESS;
 }
 
-DECLARE_HOST_COMMAND(EC_CMD_LIGHTBAR_CMD,
-		     lpc_cmd_lightbar,
-		     EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_LIGHTBAR_CMD, lpc_cmd_lightbar, EC_VER_MASK(0));
 
 /****************************************************************************/
 /* EC console commands */
@@ -1902,10 +1852,12 @@ static int help(const char *cmd)
 	ccprintf("  %s init                  - load default vals\n", cmd);
 	ccprintf("  %s brightness [NUM]      - set intensity (0-ff)\n", cmd);
 	ccprintf("  %s seq [NUM|SEQUENCE]    - run given pattern"
-		 " (no arg for list)\n", cmd);
+		 " (no arg for list)\n",
+		 cmd);
 	ccprintf("  %s CTRL REG VAL          - set LED controller regs\n", cmd);
 	ccprintf("  %s LED RED GREEN BLUE    - set color manually"
-		 " (LED=%d for all)\n", cmd, NUM_LEDS);
+		 " (LED=%d for all)\n",
+		 cmd, NUM_LEDS);
 	ccprintf("  %s LED                   - get current LED color\n", cmd);
 	ccprintf("  %s demo [0|1]            - turn demo mode on & off\n", cmd);
 #ifdef LIGHTBAR_SIMULATION
@@ -1936,19 +1888,18 @@ static void show_msg_names(void)
 		 lightbar_cmds[st.cur_seq].string);
 }
 
-static int command_lightbar(int argc, char **argv)
+static int command_lightbar(int argc, const char **argv)
 {
 	int i;
 	uint8_t num, led, r = 0, g = 0, b = 0;
 	struct ec_response_lightbar out;
 	char *e;
 
-	if (argc == 1) {			/* no args = dump 'em all */
+	if (argc == 1) { /* no args = dump 'em all */
 		lb_hc_cmd_dump(&out);
 		for (i = 0; i < ARRAY_SIZE(out.dump.vals); i++)
 			ccprintf(" %02x     %02x     %02x\n",
-				 out.dump.vals[i].reg,
-				 out.dump.vals[i].ic0,
+				 out.dump.vals[i].reg, out.dump.vals[i].ic0,
 				 out.dump.vals[i].ic1);
 
 		return EC_SUCCESS;
@@ -1987,8 +1938,7 @@ static int command_lightbar(int argc, char **argv)
 
 	if (!strcasecmp(argv[1], "demo")) {
 		if (argc > 2) {
-			if (!strcasecmp(argv[2], "on") ||
-			    argv[2][0] == '1')
+			if (!strcasecmp(argv[2], "on") || argv[2][0] == '1')
 				demo_mode = 1;
 			else if (!strcasecmp(argv[2], "off") ||
 				 argv[2][0] == '0')
@@ -2010,7 +1960,7 @@ static int command_lightbar(int argc, char **argv)
 			num = find_msg_by_name(argv[2]);
 		if (num >= LIGHTBAR_NUM_SEQUENCES)
 			return EC_ERROR_PARAM2;
-		if (argc > 3)			/* for testing TAP direction */
+		if (argc > 3) /* for testing TAP direction */
 			force_dir = strtoi(argv[3], 0, 0);
 		lightbar_sequence(num);
 		return EC_SUCCESS;
@@ -2056,13 +2006,11 @@ static int command_lightbar(int argc, char **argv)
 		return EC_SUCCESS;
 	}
 
-
 #ifdef CONFIG_CONSOLE_CMDHELP
 	help(argv[0]);
 #endif
 
 	return EC_ERROR_INVAL;
 }
-DECLARE_CONSOLE_COMMAND(lightbar, command_lightbar,
-			"[help | COMMAND [ARGS]]",
+DECLARE_CONSOLE_COMMAND(lightbar, command_lightbar, "[help | COMMAND [ARGS]]",
 			"Get/set lightbar state");
diff --git a/common/mag_cal.c b/common/mag_cal.c
index 13beb93af2..2ad89c48df 100644
--- a/common/mag_cal.c
+++ b/common/mag_cal.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,23 +8,22 @@
 #include "mag_cal.h"
 #include "mat33.h"
 #include "mat44.h"
-
 #include "math.h"
 #include "math_util.h"
 #include "util.h"
 
 /* Data from sensor is in 16th of uT, 0.0625 uT/LSB */
-#define MAG_CAL_RAW_UT      16
+#define MAG_CAL_RAW_UT 16
 
-#define MAX_EIGEN_RATIO     FLOAT_TO_FP(25.0f)
-#define MAX_EIGEN_MAG       FLOAT_TO_FP(80.0f * MAG_CAL_RAW_UT)
-#define MIN_EIGEN_MAG       FLOAT_TO_FP(10.0f * MAG_CAL_RAW_UT)
+#define MAX_EIGEN_RATIO FLOAT_TO_FP(25.0f)
+#define MAX_EIGEN_MAG FLOAT_TO_FP(80.0f * MAG_CAL_RAW_UT)
+#define MIN_EIGEN_MAG FLOAT_TO_FP(10.0f * MAG_CAL_RAW_UT)
 
-#define MAX_FIT_MAG         MAX_EIGEN_MAG
-#define MIN_FIT_MAG         MIN_EIGEN_MAG
+#define MAX_FIT_MAG MAX_EIGEN_MAG
+#define MIN_FIT_MAG MIN_EIGEN_MAG
 
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
-#define PRINTF_FLOAT(x)  ((int)((x) * 100.0f))
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
+#define PRINTF_FLOAT(x) ((int)((x)*100.0f))
 
 /**
  * Compute the covariance element: (avg(ab) - avg(a)*avg(b))
@@ -51,34 +50,25 @@ static int moc_eigen_test(struct mag_cal_t *moc)
 	mat33_fp_t eigenvecs;
 	fp_t evmax, evmin, evmag;
 	fp_t inv = fp_div_dbz(FLOAT_TO_FP(1.0f),
-			      INT_TO_FP((int) moc->kasa_fit.nsamples));
+			      INT_TO_FP((int)moc->kasa_fit.nsamples));
 	int eigen_pass;
 
 	/* covariance matrix */
-	S[0][0] = covariance_element(moc->kasa_fit.acc_xx,
-				     moc->kasa_fit.acc_x,
-				     moc->kasa_fit.acc_x,
-				     inv);
+	S[0][0] = covariance_element(moc->kasa_fit.acc_xx, moc->kasa_fit.acc_x,
+				     moc->kasa_fit.acc_x, inv);
 	S[0][1] = S[1][0] = covariance_element(moc->kasa_fit.acc_xy,
 					       moc->kasa_fit.acc_x,
-					       moc->kasa_fit.acc_y,
-					       inv);
+					       moc->kasa_fit.acc_y, inv);
 	S[0][2] = S[2][0] = covariance_element(moc->kasa_fit.acc_xz,
 					       moc->kasa_fit.acc_x,
-					       moc->kasa_fit.acc_z,
-					       inv);
-	S[1][1] = covariance_element(moc->kasa_fit.acc_yy,
-				     moc->kasa_fit.acc_y,
-				     moc->kasa_fit.acc_y,
-				     inv);
+					       moc->kasa_fit.acc_z, inv);
+	S[1][1] = covariance_element(moc->kasa_fit.acc_yy, moc->kasa_fit.acc_y,
+				     moc->kasa_fit.acc_y, inv);
 	S[1][2] = S[2][1] = covariance_element(moc->kasa_fit.acc_yz,
 					       moc->kasa_fit.acc_y,
-					       moc->kasa_fit.acc_z,
-					       inv);
-	S[2][2] = covariance_element(moc->kasa_fit.acc_zz,
-				     moc->kasa_fit.acc_z,
-				     moc->kasa_fit.acc_z,
-				     inv);
+					       moc->kasa_fit.acc_z, inv);
+	S[2][2] = covariance_element(moc->kasa_fit.acc_zz, moc->kasa_fit.acc_z,
+				     moc->kasa_fit.acc_z, inv);
 
 	mat33_fp_get_eigenbasis(S, eigenvals, eigenvecs);
 
@@ -90,9 +80,8 @@ static int moc_eigen_test(struct mag_cal_t *moc)
 
 	evmag = fp_sqrtf(eigenvals[X] + eigenvals[Y] + eigenvals[Z]);
 
-	eigen_pass = (fp_mul(evmin, MAX_EIGEN_RATIO) > evmax)
-		&& (evmag > MIN_EIGEN_MAG)
-		&& (evmag < MAX_EIGEN_MAG);
+	eigen_pass = (fp_mul(evmin, MAX_EIGEN_RATIO) > evmax) &&
+		     (evmag > MIN_EIGEN_MAG) && (evmag < MAX_EIGEN_MAG);
 
 #if 0
 	CPRINTF("mag eigenvalues: (%.02d %.02d %.02d), ",
diff --git a/common/main.c b/common/main.c
index e749c3e21f..fde91a2ed3 100644
--- a/common/main.c
+++ b/common/main.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -6,24 +6,30 @@
  */
 
 #include "board_config.h"
+#ifdef CONFIG_KEYBOARD_SCAN_ADC
+#include "adc.h"
+#endif
 #include "button.h"
 #include "chipset.h"
 #include "clock.h"
 #include "common.h"
 #include "console.h"
 #include "cpu.h"
+#include "cros_board_info.h"
 #include "dma.h"
 #include "eeprom.h"
 #include "flash.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "i2c.h"
+#include "i2c_bitbang.h"
 #include "keyboard_scan.h"
 #include "link_defs.h"
 #include "lpc.h"
 #ifdef CONFIG_MPU
 #include "mpu.h"
 #endif
+#include "panic.h"
 #include "rwsig.h"
 #include "system.h"
 #include "task.h"
@@ -35,8 +41,8 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 test_mockable __keep int main(void)
 {
@@ -109,7 +115,7 @@ test_mockable __keep int main(void)
 	 * Initialize flash and apply write protect if necessary.  Requires
 	 * the reset flags calculated by system initialization.
 	 */
-	flash_pre_init();
+	crec_flash_pre_init();
 #endif
 
 	/* Set the CPU clocks / PLLs.  System is now running at full speed. */
@@ -124,10 +130,14 @@ test_mockable __keep int main(void)
 	 */
 	timer_init();
 
+	/* Compensate the elapsed time for the RTC. */
+	if (IS_ENABLED(CONFIG_HIBERNATE_PSL_COMPENSATE_RTC))
+		system_compensate_rtc();
+
 	/* Main initialization stage.  Modules may enable interrupts here. */
 	cpu_init();
 
-#ifdef CONFIG_DMA
+#ifdef CONFIG_DMA_CROS
 	/* Initialize DMA.  Must be before UART. */
 	dma_init();
 #endif
@@ -139,20 +149,7 @@ test_mockable __keep int main(void)
 	if (mpu_pre_init_rv != EC_SUCCESS)
 		panic("MPU init failed");
 
-	/* be less verbose if we boot for USB resume to meet spec timings */
-	if (!(system_get_reset_flags() & EC_RESET_FLAG_USB_RESUME)) {
-		CPUTS("\n");
-		if (system_jumped_to_this_image())
-			CPRINTS("UART initialized after sysjump");
-		else
-			CPUTS("\n--- UART initialized after reboot ---\n");
-		CPRINTF("[Image: %s, %s]\n",
-			 system_get_image_copy_string(),
-			 system_get_build_info());
-		CPUTS("[Reset cause: ");
-		system_print_reset_flags();
-		CPUTS("]\n");
-	}
+	system_print_banner();
 
 #ifdef CONFIG_BRINGUP
 	ccprintf("\n\nWARNING: BRINGUP BUILD\n\n\n");
@@ -179,32 +176,62 @@ test_mockable __keep int main(void)
 #endif
 
 	/*
-	 * Keyboard scan init/Button init can set recovery events to
-	 * indicate to host entry into recovery mode. Before this is
-	 * done, lpc always report mask needs to be initialized
-	 * correctly.
+	 * If the EC has exclusive control over the CBI EEPROM WP signal, have
+	 * the EC set the WP if appropriate.  Note that once the WP is set, the
+	 * EC must be reset via EC_RST_ODL in order for the WP to become unset.
 	 */
+	if (IS_ENABLED(CONFIG_EEPROM_CBI_WP) && system_is_locked())
+		cbi_latch_eeprom_wp();
+
+		/*
+		 * Keyboard scan init/Button init can set recovery events to
+		 * indicate to host entry into recovery mode. Before this is
+		 * done, LPC_HOST_EVENT_ALWAYS_REPORT mask needs to be
+		 * initialized correctly.
+		 */
 #ifdef CONFIG_HOSTCMD_X86
 	lpc_init_mask();
 #endif
-	if (IS_ENABLED(CONFIG_I2C_MASTER)) {
+	if (IS_ENABLED(CONFIG_I2C_CONTROLLER)) {
 		/*
 		 * Some devices (like the I2C keyboards, CBI) need I2C access
 		 * pretty early, so let's initialize the controller now.
 		 */
 		i2c_init();
+
+		if (IS_ENABLED(CONFIG_I2C_BITBANG)) {
+			/*
+			 * Enable I2C raw mode for the ports which need
+			 * pre-task i2c transactions.
+			 */
+			enable_i2c_raw_mode(true);
+
+			/* Board level pre-task I2C peripheral initialization */
+			board_pre_task_i2c_peripheral_init();
+		}
 	}
+
 #ifdef HAS_TASK_KEYSCAN
-	keyboard_scan_init();
+
+#ifdef CONFIG_KEYBOARD_SCAN_ADC
+	/*
+	 * Initialize adc here as we need to use it during keyboard_scan_init
+	 * to scan boot keys
+	 */
+	adc_init();
 #endif
+
+	keyboard_scan_init();
+#endif /* HAS_TASK_KEYSCAN */
+
 #if defined(CONFIG_DEDICATED_RECOVERY_BUTTON) || defined(CONFIG_VOLUME_BUTTONS)
 	button_init();
 #endif /* defined(CONFIG_DEDICATED_RECOVERY_BUTTON | CONFIG_VOLUME_BUTTONS) */
 
 	/* Make sure recovery boot won't be paused. */
-	if (IS_ENABLED(CONFIG_POWER_BUTTON_INIT_IDLE)
-			&& system_is_manual_recovery()
-			&& (system_get_reset_flags() & EC_RESET_FLAG_AP_IDLE)) {
+	if (IS_ENABLED(CONFIG_POWER_BUTTON_INIT_IDLE) &&
+	    system_is_manual_recovery() &&
+	    (system_get_reset_flags() & EC_RESET_FLAG_AP_IDLE)) {
 		CPRINTS("Clear AP_IDLE for recovery mode");
 		system_clear_reset_flags(EC_RESET_FLAG_AP_IDLE);
 	}
@@ -244,7 +271,15 @@ test_mockable __keep int main(void)
 				rwsig_jump_now();
 		}
 	}
-#endif  /* !CONFIG_VBOOT_EFS && CONFIG_RWSIG && !HAS_TASK_RWSIG */
+#endif /* !CONFIG_VBOOT_EFS && CONFIG_RWSIG && !HAS_TASK_RWSIG */
+
+	/*
+	 * Disable I2C raw mode for the ports which needed pre-task i2c
+	 * transactions as the task is about to start and the I2C can resume
+	 * to event based transactions.
+	 */
+	if (IS_ENABLED(CONFIG_I2C_BITBANG) && IS_ENABLED(CONFIG_I2C_CONTROLLER))
+		enable_i2c_raw_mode(false);
 
 	/*
 	 * Print the init time.  Not completely accurate because it can't take
diff --git a/common/mat33.c b/common/mat33.c
index 87e335db26..844fd0b8cc 100644
--- a/common/mat33.c
+++ b/common/mat33.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -59,8 +59,7 @@ void mat33_fp_swap_rows(mat33_fp_t A, const size_t i, const size_t j)
  * The i-th eigenvalue corresponds to the eigenvector in the i-th _row_ of
  * "eigenvecs".
  */
-void mat33_fp_get_eigenbasis(mat33_fp_t S, fpv3_t e_vals,
-			     mat33_fp_t e_vecs)
+void mat33_fp_get_eigenbasis(mat33_fp_t S, fpv3_t e_vals, mat33_fp_t e_vecs)
 {
 	const size_t N = 3;
 	sizev3_t ind;
@@ -176,8 +175,8 @@ size_t mat33_fp_maxind(mat33_fp_t A, size_t k)
 	return m;
 }
 
-void mat33_fp_rotate(mat33_fp_t A, fp_t c, fp_t s,
-		     size_t k, size_t l, size_t i, size_t j)
+void mat33_fp_rotate(mat33_fp_t A, fp_t c, fp_t s, size_t k, size_t l, size_t i,
+		     size_t j)
 {
 	fp_t tmp = fp_mul(c, A[k][l]) - fp_mul(s, A[i][j]);
 	A[i][j] = fp_mul(s, A[k][l]) + fp_mul(c, A[i][j]);
diff --git a/common/mat44.c b/common/mat44.c
index a4232bf8d4..d48ca4f596 100644
--- a/common/mat44.c
+++ b/common/mat44.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/common/math_util.c b/common/math_util.c
index dc52729c65..4f5eb8b877 100644
--- a/common/math_util.c
+++ b/common/math_util.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,18 +11,18 @@
 #include "util.h"
 
 /* For cosine lookup table, define the increment and the size of the table. */
-#define COSINE_LUT_INCR_DEG	5
-#define COSINE_LUT_SIZE		((180 / COSINE_LUT_INCR_DEG) + 1)
+#define COSINE_LUT_INCR_DEG 5
+#define COSINE_LUT_SIZE ((180 / COSINE_LUT_INCR_DEG) + 1)
 
 /* Lookup table for the value of cosine from 0 degrees to 180 degrees. */
 static const fp_t cos_lut[] = {
-	FLOAT_TO_FP( 1.00000), FLOAT_TO_FP( 0.99619), FLOAT_TO_FP( 0.98481),
-	FLOAT_TO_FP( 0.96593), FLOAT_TO_FP( 0.93969), FLOAT_TO_FP( 0.90631),
-	FLOAT_TO_FP( 0.86603), FLOAT_TO_FP( 0.81915), FLOAT_TO_FP( 0.76604),
-	FLOAT_TO_FP( 0.70711), FLOAT_TO_FP( 0.64279), FLOAT_TO_FP( 0.57358),
-	FLOAT_TO_FP( 0.50000), FLOAT_TO_FP( 0.42262), FLOAT_TO_FP( 0.34202),
-	FLOAT_TO_FP( 0.25882), FLOAT_TO_FP( 0.17365), FLOAT_TO_FP( 0.08716),
-	FLOAT_TO_FP( 0.00000), FLOAT_TO_FP(-0.08716), FLOAT_TO_FP(-0.17365),
+	FLOAT_TO_FP(1.00000),  FLOAT_TO_FP(0.99619),  FLOAT_TO_FP(0.98481),
+	FLOAT_TO_FP(0.96593),  FLOAT_TO_FP(0.93969),  FLOAT_TO_FP(0.90631),
+	FLOAT_TO_FP(0.86603),  FLOAT_TO_FP(0.81915),  FLOAT_TO_FP(0.76604),
+	FLOAT_TO_FP(0.70711),  FLOAT_TO_FP(0.64279),  FLOAT_TO_FP(0.57358),
+	FLOAT_TO_FP(0.50000),  FLOAT_TO_FP(0.42262),  FLOAT_TO_FP(0.34202),
+	FLOAT_TO_FP(0.25882),  FLOAT_TO_FP(0.17365),  FLOAT_TO_FP(0.08716),
+	FLOAT_TO_FP(0.00000),  FLOAT_TO_FP(-0.08716), FLOAT_TO_FP(-0.17365),
 	FLOAT_TO_FP(-0.25882), FLOAT_TO_FP(-0.34202), FLOAT_TO_FP(-0.42262),
 	FLOAT_TO_FP(-0.50000), FLOAT_TO_FP(-0.57358), FLOAT_TO_FP(-0.64279),
 	FLOAT_TO_FP(-0.70711), FLOAT_TO_FP(-0.76604), FLOAT_TO_FP(-0.81915),
@@ -32,7 +32,6 @@ static const fp_t cos_lut[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(cos_lut) == COSINE_LUT_SIZE);
 
-
 fp_t arc_cos(fp_t x)
 {
 	int i;
@@ -48,8 +47,8 @@ fp_t arc_cos(fp_t x)
 	 * interpolate for precision.
 	 */
 	/* TODO(crosbug.com/p/25600): Optimize with binary search. */
-	for (i = 0; i < COSINE_LUT_SIZE-1; i++) {
-		if (x >= cos_lut[i+1]) {
+	for (i = 0; i < COSINE_LUT_SIZE - 1; i++) {
+		if (x >= cos_lut[i + 1]) {
 			const fp_t interp = fp_div(cos_lut[i] - x,
 						   cos_lut[i] - cos_lut[i + 1]);
 
@@ -60,12 +59,9 @@ fp_t arc_cos(fp_t x)
 
 	/*
 	 * Shouldn't be possible to get here because inputs are clipped to
-	 * [-1, 1] and the cos_lut[] table goes over the same range. If we
-	 * are here, throw an assert.
+	 * [-1, 1] and the cos_lut[] table goes over the same range.
 	 */
-	ASSERT(0);
-
-	return 0;
+	__builtin_unreachable(); /* LCOV_EXCL_LINE */
 }
 
 /**
@@ -79,7 +75,7 @@ fp_t arc_cos(fp_t x)
  * except when the floating point representation of the square root rounds up
  * to an integer.
  */
-static inline int int_sqrtf(fp_inter_t x)
+inline int int_sqrtf(fp_inter_t x)
 {
 	return sqrtf(x);
 }
@@ -90,26 +86,29 @@ fp_t fp_sqrtf(fp_t x)
 	return sqrtf(x);
 }
 #else
-static int int_sqrtf(fp_inter_t x)
+int int_sqrtf(fp_inter_t x)
 {
 	int rmax = INT32_MAX;
 	int rmin = 0;
 
-	/* Short cut if x is 32-bit value */
-	if (x < rmax)
-		rmax = 0x7fff;
+	/*
+	 * Short cut if x is 32-bit value
+	 * sqrt(INT32_MAX) ~= 46340.95
+	 */
+	if (x < INT32_MAX)
+		rmax = 46341;
 
 	/*
 	 * Just binary-search.  There are better algorithms, but we call this
 	 * infrequently enough it doesn't matter.
 	 */
 	if (x <= 0)
-		return 0;  /* Yeah, for imaginary numbers too */
-	else if (x > (fp_inter_t)rmax * rmax)
+		return 0; /* Yeah, for imaginary numbers too */
+	else if (x >= (fp_inter_t)rmax * rmax)
 		return rmax;
 
 	while (1) {
-		int r = (rmax + rmin) / 2;
+		int r = rmin + (rmax - rmin) / 2;
 		fp_inter_t r2 = (fp_inter_t)r * r;
 
 		if (r2 > x) {
@@ -138,9 +137,8 @@ fp_t fp_sqrtf(fp_t x)
 
 int vector_magnitude(const intv3_t v)
 {
-	fp_inter_t sum =   (fp_inter_t)v[0] * v[0] +
-			(fp_inter_t)v[1] * v[1] +
-			(fp_inter_t)v[2] * v[2];
+	fp_inter_t sum = (fp_inter_t)v[0] * v[0] + (fp_inter_t)v[1] * v[1] +
+			 (fp_inter_t)v[2] * v[2];
 
 	return int_sqrtf(sum);
 }
@@ -155,8 +153,7 @@ void cross_product(const intv3_t v1, const intv3_t v2, intv3_t v)
 
 fp_inter_t dot_product(const intv3_t v1, const intv3_t v2)
 {
-	return (fp_inter_t)v1[X] * v2[X] +
-	       (fp_inter_t)v1[Y] * v2[Y] +
+	return (fp_inter_t)v1[X] * v2[X] + (fp_inter_t)v1[Y] * v2[Y] +
 	       (fp_inter_t)v1[Z] * v2[Z];
 }
 
@@ -215,17 +212,13 @@ void rotate(const intv3_t v, const mat33_fp_t R, intv3_t res)
 		return;
 	}
 
-
 	/* Rotate */
-	t[0] =	(fp_inter_t)v[0] * R[0][0] +
-		(fp_inter_t)v[1] * R[1][0] +
-		(fp_inter_t)v[2] * R[2][0];
-	t[1] =	(fp_inter_t)v[0] * R[0][1] +
-		(fp_inter_t)v[1] * R[1][1] +
-		(fp_inter_t)v[2] * R[2][1];
-	t[2] =	(fp_inter_t)v[0] * R[0][2] +
-		(fp_inter_t)v[1] * R[1][2] +
-		(fp_inter_t)v[2] * R[2][2];
+	t[0] = (fp_inter_t)v[0] * R[0][0] + (fp_inter_t)v[1] * R[1][0] +
+	       (fp_inter_t)v[2] * R[2][0];
+	t[1] = (fp_inter_t)v[0] * R[0][1] + (fp_inter_t)v[1] * R[1][1] +
+	       (fp_inter_t)v[2] * R[2][1];
+	t[2] = (fp_inter_t)v[0] * R[0][2] + (fp_inter_t)v[1] * R[1][2] +
+	       (fp_inter_t)v[2] * R[2][2];
 
 	/* Scale by fixed point shift when writing back to result */
 	res[0] = FP_TO_INT(t[0]);
@@ -244,38 +237,39 @@ void rotate_inv(const intv3_t v, const mat33_fp_t R, intv3_t res)
 		return;
 	}
 
-	deter = fp_mul(R[0][0], (fp_mul(R[1][1], R[2][2]) -
-				 fp_mul(R[2][1], R[1][2]))) -
-		fp_mul(R[0][1], (fp_mul(R[1][0], R[2][2]) -
-				 fp_mul(R[1][2], R[2][0]))) +
-		fp_mul(R[0][2], (fp_mul(R[1][0], R[2][1]) -
-				 fp_mul(R[1][1], R[2][0])));
+	deter = fp_mul(R[0][0],
+		       (fp_mul(R[1][1], R[2][2]) - fp_mul(R[2][1], R[1][2]))) -
+		fp_mul(R[0][1],
+		       (fp_mul(R[1][0], R[2][2]) - fp_mul(R[1][2], R[2][0]))) +
+		fp_mul(R[0][2],
+		       (fp_mul(R[1][0], R[2][1]) - fp_mul(R[1][1], R[2][0])));
 
 	/*
 	 * invert the matrix: from
 	 * http://stackoverflow.com/questions/983999/
 	 * simple-3x3-matrix-inverse-code-c
 	 */
-	t[0] =  (fp_inter_t)v[0] * (fp_mul(R[1][1], R[2][2]) -
-				 fp_mul(R[2][1], R[1][2])) -
-		(fp_inter_t)v[1] * (fp_mul(R[1][0], R[2][2]) -
-				 fp_mul(R[1][2], R[2][0])) +
-		(fp_inter_t)v[2] * (fp_mul(R[1][0], R[2][1]) -
-				 fp_mul(R[2][0], R[1][1]));
-
-	t[1] =	(fp_inter_t)v[0] * (fp_mul(R[0][1], R[2][2]) -
-				 fp_mul(R[0][2], R[2][1])) * -1 +
-		(fp_inter_t)v[1] * (fp_mul(R[0][0], R[2][2]) -
-				 fp_mul(R[0][2], R[2][0])) -
-		(fp_inter_t)v[2] * (fp_mul(R[0][0], R[2][1]) -
-				 fp_mul(R[2][0], R[0][1]));
-
-	t[2] =	(fp_inter_t)v[0] * (fp_mul(R[0][1], R[1][2]) -
-				 fp_mul(R[0][2], R[1][1])) -
-		(fp_inter_t)v[1] * (fp_mul(R[0][0], R[1][2]) -
-				 fp_mul(R[1][0], R[0][2])) +
-		(fp_inter_t)v[2] * (fp_mul(R[0][0], R[1][1]) -
-				 fp_mul(R[1][0], R[0][1]));
+	t[0] = (fp_inter_t)v[0] *
+		       (fp_mul(R[1][1], R[2][2]) - fp_mul(R[2][1], R[1][2])) -
+	       (fp_inter_t)v[1] *
+		       (fp_mul(R[1][0], R[2][2]) - fp_mul(R[1][2], R[2][0])) +
+	       (fp_inter_t)v[2] *
+		       (fp_mul(R[1][0], R[2][1]) - fp_mul(R[2][0], R[1][1]));
+
+	t[1] = (fp_inter_t)v[0] *
+		       (fp_mul(R[0][1], R[2][2]) - fp_mul(R[0][2], R[2][1])) *
+		       -1 +
+	       (fp_inter_t)v[1] *
+		       (fp_mul(R[0][0], R[2][2]) - fp_mul(R[0][2], R[2][0])) -
+	       (fp_inter_t)v[2] *
+		       (fp_mul(R[0][0], R[2][1]) - fp_mul(R[2][0], R[0][1]));
+
+	t[2] = (fp_inter_t)v[0] *
+		       (fp_mul(R[0][1], R[1][2]) - fp_mul(R[0][2], R[1][1])) -
+	       (fp_inter_t)v[1] *
+		       (fp_mul(R[0][0], R[1][2]) - fp_mul(R[1][0], R[0][2])) +
+	       (fp_inter_t)v[2] *
+		       (fp_mul(R[0][0], R[1][1]) - fp_mul(R[1][0], R[0][1]));
 
 	/* Scale by fixed point shift when writing back to result */
 	res[0] = FP_TO_INT(fp_div(t[0], deter));
@@ -287,6 +281,43 @@ void rotate_inv(const intv3_t v, const mat33_fp_t R, intv3_t res)
 int round_divide(int64_t dividend, int divisor)
 {
 	return (dividend > 0) ^ (divisor > 0) ?
-		(dividend - divisor / 2) / divisor :
-		(dividend + divisor / 2) / divisor;
+		       (dividend - divisor / 2) / divisor :
+		       (dividend + divisor / 2) / divisor;
+}
+
+#if ULONG_MAX == 0xFFFFFFFFUL
+/*
+ * 32 bit processor
+ *
+ * Some 32 bit processors do not include a 64 bit shift
+ * operation. So fall back to 32 bit operations on a
+ * union.
+ */
+uint64_t bitmask_uint64(int offset)
+{
+	union mask64_t {
+		struct {
+#if (__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__)
+			uint32_t lo;
+			uint32_t hi;
+#elif (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__)
+			uint32_t hi;
+			uint32_t lo;
+#endif
+		};
+		uint64_t val;
+	} mask = { 0 };
+
+	/*
+	 * If the shift is out of range the result should
+	 * remain 0, otherwise perform the shift
+	 */
+	if (offset >= 0 && offset < 64) {
+		if (offset < 32)
+			mask.lo = BIT(offset);
+		else
+			mask.hi = BIT(offset - 32);
+	}
+	return mask.val;
 }
+#endif
diff --git a/common/memory_commands.c b/common/memory_commands.c
index 98c64d918b..163460a2d1 100644
--- a/common/memory_commands.c
+++ b/common/memory_commands.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,7 +10,6 @@
 #include "util.h"
 #include "watchdog.h"
 
-
 enum format {
 	FMT_WORD,
 	FMT_HALF,
@@ -56,7 +55,7 @@ static void show_val(uint32_t address, uint32_t index, enum format fmt)
 	cflush();
 }
 
-static int command_mem_dump(int argc, char **argv)
+static int command_mem_dump(int argc, const char **argv)
 {
 	uint32_t address, i, num = 1;
 	char *e;
@@ -106,20 +105,19 @@ static int command_mem_dump(int argc, char **argv)
 	return EC_SUCCESS;
 }
 
-DECLARE_CONSOLE_COMMAND_FLAGS
-	(md, command_mem_dump,
-	 "[.b|.h|.s] addr [count]",
-	 "dump memory values, optionally specifying the format",
-	 CMD_FLAG_RESTRICTED);
+DECLARE_CONSOLE_COMMAND_FLAGS(
+	md, command_mem_dump, "[.b|.h|.s] addr [count]",
+	"dump memory values, optionally specifying the format",
+	CMD_FLAG_RESTRICTED);
 #endif /* CONFIG_CMD_MD */
 
 #ifdef CONFIG_CMD_RW
-static int command_read_word(int argc, char **argv)
+static int command_read_word(int argc, const char **argv)
 {
 	volatile uint32_t *address;
 	uint32_t value;
-	unsigned access_size = 4;
-	unsigned argc_offs = 0;
+	unsigned int access_size = 4;
+	unsigned int argc_offs = 0;
 	char *e;
 
 	if (argc < 2)
@@ -149,16 +147,16 @@ static int command_read_word(int argc, char **argv)
 	if ((argc - argc_offs) < 3) {
 		switch (access_size) {
 		case 1:
-			ccprintf("read 0x%pP = 0x%02x\n",
-				 address, *((uint8_t *)address));
+			ccprintf("read 0x%p = 0x%02x\n", address,
+				 *((uint8_t *)address));
 			break;
 		case 2:
-			ccprintf("read 0x%pP = 0x%04x\n",
-				 address, *((uint16_t *)address));
+			ccprintf("read 0x%p = 0x%04x\n", address,
+				 *((uint16_t *)address));
 			break;
 
 		default:
-			ccprintf("read 0x%pP = 0x%08x\n",  address, *address);
+			ccprintf("read 0x%p = 0x%08x\n", address, *address);
 			break;
 		}
 		return EC_SUCCESS;
@@ -171,17 +169,17 @@ static int command_read_word(int argc, char **argv)
 
 	switch (access_size) {
 	case 1:
-		ccprintf("write 0x%pP = 0x%02x\n", address, (uint8_t)value);
-		cflush();  /* Flush before writing in case this crashes */
+		ccprintf("write 0x%p = 0x%02x\n", address, (uint8_t)value);
+		cflush(); /* Flush before writing in case this crashes */
 		*((uint8_t *)address) = (uint8_t)value;
 		break;
 	case 2:
-		ccprintf("write 0x%pP = 0x%04x\n", address, (uint16_t)value);
+		ccprintf("write 0x%p = 0x%04x\n", address, (uint16_t)value);
 		cflush();
 		*((uint16_t *)address) = (uint16_t)value;
 		break;
 	default:
-		ccprintf("write 0x%pP = 0x%02x\n", address, value);
+		ccprintf("write 0x%p = 0x%02x\n", address, value);
 		cflush();
 		*address = value;
 		break;
@@ -190,9 +188,8 @@ static int command_read_word(int argc, char **argv)
 	return EC_SUCCESS;
 }
 
-DECLARE_CONSOLE_COMMAND_FLAGS
-	(rw, command_read_word,
-	 "[.b|.h] addr [value]",
-	 "Read or write a word in memory optionally specifying the size",
-	 CMD_FLAG_RESTRICTED);
-#endif	/* CONFIG_CMD_RW */
+DECLARE_CONSOLE_COMMAND_FLAGS(
+	rw, command_read_word, "[.b|.h] addr [value]",
+	"Read or write a word in memory optionally specifying the size",
+	CMD_FLAG_RESTRICTED);
+#endif /* CONFIG_CMD_RW */
diff --git a/common/mkbp_event.c b/common/mkbp_event.c
index f640a9340c..ee706e549a 100644
--- a/common/mkbp_event.c
+++ b/common/mkbp_event.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,15 +11,15 @@
 #include "host_command.h"
 #include "host_command_heci.h"
 #include "hwtimer.h"
-#include "timer.h"
 #include "link_defs.h"
 #include "mkbp_event.h"
 #include "power.h"
+#include "timer.h"
 #include "util.h"
 
 #define CPUTS(outstr) cputs(CC_COMMAND, outstr)
-#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ##args)
 
 /*
  * Tracks the current state of the MKBP interrupt send from the EC to the AP.
@@ -48,7 +48,7 @@ enum interrupt_state {
 };
 
 struct mkbp_state {
-	struct mutex lock;
+	mutex_t lock;
 	uint32_t events;
 	enum interrupt_state interrupt;
 	/*
@@ -68,6 +68,9 @@ struct mkbp_state {
 static struct mkbp_state state;
 uint32_t mkbp_last_event_time;
 
+static const int ap_comm_failure_threshold = 2;
+static int ap_comm_failure_count;
+
 #ifdef CONFIG_MKBP_EVENT_WAKEUP_MASK
 static uint32_t mkbp_event_wake_mask = CONFIG_MKBP_EVENT_WAKEUP_MASK;
 #endif /* CONFIG_MKBP_EVENT_WAKEUP_MASK */
@@ -76,10 +79,21 @@ static uint32_t mkbp_event_wake_mask = CONFIG_MKBP_EVENT_WAKEUP_MASK;
 static uint32_t mkbp_host_event_wake_mask = CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK;
 #endif /* CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK */
 
+#ifdef CONFIG_ZEPHYR
+static int init_mkbp_mutex(void)
+{
+	k_mutex_init(&state.lock);
+
+	return 0;
+}
+SYS_INIT(init_mkbp_mutex, POST_KERNEL, 50);
+#endif /* CONFIG_ZEPHYR */
+
 #if defined(CONFIG_MKBP_USE_GPIO) || \
 	defined(CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT)
 static int mkbp_set_host_active_via_gpio(int active, uint32_t *timestamp)
 {
+	uint32_t lock_key;
 	/*
 	 * If we want to take a timestamp, then disable interrupts temporarily
 	 * to ensure that the timestamp is as close as possible to the setting
@@ -87,14 +101,17 @@ static int mkbp_set_host_active_via_gpio(int active, uint32_t *timestamp)
 	 * taking the timestamp and setting the gpio)
 	 */
 	if (timestamp) {
-		interrupt_disable();
+		lock_key = irq_lock();
 		*timestamp = __hw_clock_source_read();
 	}
 
-	gpio_set_level(GPIO_EC_INT_L, !active);
+	if (IS_ENABLED(CONFIG_MKBP_USE_GPIO_ACTIVE_HIGH))
+		gpio_set_level(GPIO_EC_INT_L, active);
+	else
+		gpio_set_level(GPIO_EC_INT_L, !active);
 
 	if (timestamp)
-		interrupt_enable();
+		irq_unlock(lock_key);
 
 #ifdef CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT
 	/*
@@ -152,7 +169,7 @@ static int mkbp_set_host_active(int active, uint32_t *timestamp)
 	return mkbp_set_host_active_via_custom(active, timestamp);
 #elif defined(CONFIG_MKBP_USE_HOST_EVENT)
 	return mkbp_set_host_active_via_event(active, timestamp);
-#elif defined(CONFIG_MKBP_USE_GPIO) ||\
+#elif defined(CONFIG_MKBP_USE_GPIO) || \
 	defined(CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT)
 	return mkbp_set_host_active_via_gpio(active, timestamp);
 #elif defined(CONFIG_MKBP_USE_HECI)
@@ -172,10 +189,9 @@ static inline int host_is_sleeping(void)
 
 #ifdef CONFIG_POWER_TRACK_HOST_SLEEP_STATE
 	enum host_sleep_event sleep_state = power_get_host_sleep_state();
-	is_sleeping |=
-		(sleep_state == HOST_SLEEP_EVENT_S0IX_SUSPEND ||
-		 sleep_state == HOST_SLEEP_EVENT_S3_SUSPEND ||
-		 sleep_state == HOST_SLEEP_EVENT_S3_WAKEABLE_SUSPEND);
+	is_sleeping |= (sleep_state == HOST_SLEEP_EVENT_S0IX_SUSPEND ||
+			sleep_state == HOST_SLEEP_EVENT_S3_SUSPEND ||
+			sleep_state == HOST_SLEEP_EVENT_S3_WAKEABLE_SUSPEND);
 #endif
 	return is_sleeping;
 }
@@ -184,12 +200,12 @@ static inline int host_is_sleeping(void)
 /*
  * This is the deferred function that ensures that we attempt to set the MKBP
  * interrupt again if there was a failure in the system (EC or AP) and the AP
- * never called get_next_event.
+ * never called mkbp_fifo_get_next_event.
  */
 static void force_mkbp_if_events(void);
 DECLARE_DEFERRED(force_mkbp_if_events);
 
-static void activate_mkbp_with_events(uint32_t events_to_add)
+test_export_static void activate_mkbp_with_events(uint32_t events_to_add)
 {
 	int interrupt_id = -1;
 	int skip_interrupt = 0;
@@ -203,16 +219,16 @@ static void activate_mkbp_with_events(uint32_t events_to_add)
 	 */
 	if (events_to_add == BIT(EC_MKBP_EVENT_HOST_EVENT) ||
 	    events_to_add == BIT(EC_MKBP_EVENT_HOST_EVENT64))
-		skip_interrupt = host_is_sleeping() &&
-				!(host_get_events() &
-				mkbp_host_event_wake_mask);
+		skip_interrupt =
+			host_is_sleeping() &&
+			!(host_get_events() & mkbp_host_event_wake_mask);
 #endif /* CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK */
 
 #ifdef CONFIG_MKBP_EVENT_WAKEUP_MASK
 	/* Check to see if this MKBP event should wake the system. */
 	if (!skip_interrupt)
 		skip_interrupt = host_is_sleeping() &&
-			!(events_to_add & mkbp_event_wake_mask);
+				 !(events_to_add & mkbp_event_wake_mask);
 #endif /* CONFIG_MKBP_EVENT_WAKEUP_MASK */
 
 	mutex_lock(&state.lock);
@@ -244,8 +260,8 @@ static void activate_mkbp_with_events(uint32_t events_to_add)
 	if (state.interrupt == INTERRUPT_INACTIVE_TO_ACTIVE &&
 	    interrupt_id == state.interrupt_id) {
 		schedule_deferred = 1;
-		state.interrupt = rv == EC_SUCCESS ? INTERRUPT_ACTIVE
-						   : INTERRUPT_INACTIVE;
+		state.interrupt = rv == EC_SUCCESS ? INTERRUPT_ACTIVE :
+						     INTERRUPT_INACTIVE;
 	}
 	mutex_unlock(&state.lock);
 
@@ -259,25 +275,80 @@ static void activate_mkbp_with_events(uint32_t events_to_add)
 /*
  * This is the deferred function that ensures that we attempt to set the MKBP
  * interrupt again if there was a failure in the system (EC or AP) and the AP
- * never called get_next_event.
+ * never called mkbp_fifo_get_next_event.
  */
 static void force_mkbp_if_events(void)
 {
 	int toggled = 0;
+	int send_mkbp_interrupt = 0;
 
 	mutex_lock(&state.lock);
-	if (state.interrupt == INTERRUPT_ACTIVE) {
+	if (state.interrupt == INTERRUPT_INACTIVE) {
+		/*
+		 * When this function is called with state of interrupt set
+		 * to INACTIVE, it means that EC failed to send MKBP interrupt
+		 * to AP. In this case we are going to send interrupt once
+		 * again (without limits).
+		 */
+		send_mkbp_interrupt = 1;
+	} else if (state.interrupt == INTERRUPT_ACTIVE) {
+		/*
+		 * When this function is called with state of interrupt set
+		 * to ACTIVE, it means that AP failed to respond.
+		 *
+		 * It is safe to mark interrupt state as INACTIVE, because
+		 * force_mkbp_with_events() function can be only scheduled by
+		 * activate_mkbp_with_event() which will set interrupt state
+		 * to ACTIVE (and allow to increment failed_attempts counter).
+		 * After 3 attempts, we are setting interrupt state to INACTIVE
+		 * but we are not going to call activate_mkbp_with_events().
+		 * This was meant to unblock MKBP interrupt mechanism for new
+		 * events.
+		 */
+		state.interrupt = INTERRUPT_INACTIVE;
+		/*
+		 * Failed attempts counter is cleared only when AP pulls all
+		 * of events or we exceed number of attempts, so marking
+		 * interrupt as INACTIVE doesn't affect failed_attempts counter.
+		 * If we need to send interrupt once again
+		 * activate_mkbp_with_events() will set interrupt state to
+		 * ACTIVE before this function will be called.
+		 */
+		++ap_comm_failure_count;
 		if (++state.failed_attempts < 3) {
-			state.interrupt = INTERRUPT_INACTIVE;
+			send_mkbp_interrupt = 1;
 			toggled = 1;
+		} else {
+			/*
+			 * If we exceed maximum number of failed attempts we
+			 * will stop trying to send MKBP interrupt for current
+			 * event (send_mkbp_interrupt == 0), but leaving
+			 * possibility to send MKBP interrupts for future
+			 * events (state of interrupt makred as inactive).
+			 * Future events should have a chance to be sent
+			 * 3 times, so we should clear failed attempts
+			 * counter now
+			 */
+			state.failed_attempts = 0;
 		}
 	}
 	mutex_unlock(&state.lock);
 
-	if (toggled)
-		CPRINTS("MKBP not cleared within threshold, toggling.");
+	if (toggled) {
+		/**
+		 * Don't spam the EC logs when the AP is hung. Instead, log the
+		 * first few failures, and then indicate the AP is likely hung.
+		 */
+		if (ap_comm_failure_count < ap_comm_failure_threshold) {
+			CPRINTS("MKBP not cleared within threshold, toggling.");
+		} else if (ap_comm_failure_count == ap_comm_failure_threshold) {
+			CPRINTS("MKBP: The AP is failing to respond despite "
+				"being powered on.");
+		}
+	}
 
-	activate_mkbp_with_events(0);
+	if (send_mkbp_interrupt)
+		activate_mkbp_with_events(0);
 }
 
 test_mockable int mkbp_send_event(uint8_t event_type)
@@ -302,8 +373,14 @@ static int set_inactive_if_no_events(void)
 	mutex_unlock(&state.lock);
 
 	/* Cancel our safety net since the events were cleared. */
-	if (interrupt_cleared)
+	if (interrupt_cleared) {
 		hook_call_deferred(&force_mkbp_if_events_data, -1);
+		/**
+		 * This AP communication was successful.
+		 * Reset the count to log the next AP communication failure.
+		 */
+		ap_comm_failure_count = 0;
+	}
 
 	return interrupt_cleared;
 }
@@ -319,11 +396,29 @@ static int take_event_if_set(uint8_t event_type)
 	return taken;
 }
 
+static const struct mkbp_event_source *find_mkbp_event_source(uint8_t type)
+{
+#ifdef CONFIG_ZEPHYR
+	return zephyr_find_mkbp_event_source(type);
+#else
+	const struct mkbp_event_source *src;
+
+	for (src = __mkbp_evt_srcs; src < __mkbp_evt_srcs_end; ++src)
+		if (src->event_type == type)
+			break;
+
+	if (src == __mkbp_evt_srcs_end)
+		return NULL;
+
+	return src;
+#endif
+}
+
 static enum ec_status mkbp_get_next_event(struct host_cmd_handler_args *args)
 {
 	static int last;
 	int i, evt;
-	uint8_t *resp = args->response;
+	struct ec_response_get_next_event *r = args->response;
 	const struct mkbp_event_source *src;
 
 	int data_size = -EC_ERROR_BUSY;
@@ -349,14 +444,11 @@ static enum ec_status mkbp_get_next_event(struct host_cmd_handler_args *args)
 		evt = (i + last) % EC_MKBP_EVENT_COUNT;
 		last = evt + 1;
 
-		for (src = __mkbp_evt_srcs; src < __mkbp_evt_srcs_end; ++src)
-			if (src->event_type == evt)
-				break;
-
-		if (src == __mkbp_evt_srcs_end)
+		src = find_mkbp_event_source(evt);
+		if (src == NULL)
 			return EC_RES_ERROR;
 
-		resp[0] = evt; /* Event type */
+		r->event_type = evt;
 
 		/*
 		 * get_data() can return -EC_ERROR_BUSY which indicates that the
@@ -366,7 +458,7 @@ static enum ec_status mkbp_get_next_event(struct host_cmd_handler_args *args)
 		 * event instead.  Therefore, we have to service that button
 		 * event first.
 		 */
-		data_size = src->get_data(resp + 1);
+		data_size = src->get_data((uint8_t *)&r->data);
 		if (data_size == -EC_ERROR_BUSY) {
 			mutex_lock(&state.lock);
 			state.events |= BIT(evt);
@@ -376,7 +468,7 @@ static enum ec_status mkbp_get_next_event(struct host_cmd_handler_args *args)
 
 	/* If there are no more events and we support the "more" flag, set it */
 	if (!set_inactive_if_no_events() && args->version >= 2)
-		resp[0] |= EC_MKBP_HAS_MORE_EVENTS;
+		r->event_type |= EC_MKBP_HAS_MORE_EVENTS;
 
 	if (data_size < 0)
 		return EC_RES_ERROR;
@@ -384,8 +476,7 @@ static enum ec_status mkbp_get_next_event(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_GET_NEXT_EVENT,
-		     mkbp_get_next_event,
+DECLARE_HOST_COMMAND(EC_CMD_GET_NEXT_EVENT, mkbp_get_next_event,
 		     EC_VER_MASK(0) | EC_VER_MASK(1) | EC_VER_MASK(2));
 
 #ifdef CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK
@@ -401,12 +492,11 @@ mkbp_get_host_event_wake_mask(struct host_cmd_handler_args *args)
 	return EC_RES_SUCCESS;
 }
 DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_GET_WAKE_MASK,
-		     mkbp_get_host_event_wake_mask,
-		     EC_VER_MASK(0));
+		     mkbp_get_host_event_wake_mask, EC_VER_MASK(0));
 #endif /* CONFIG_MKBP_USE_HOST_EVENT */
 #endif /* CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK */
 
-#if defined(CONFIG_MKBP_EVENT_WAKEUP_MASK) ||	\
+#if defined(CONFIG_MKBP_EVENT_WAKEUP_MASK) || \
 	defined(CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK)
 static enum ec_status hc_mkbp_wake_mask(struct host_cmd_handler_args *args)
 {
@@ -445,8 +535,7 @@ static enum ec_status hc_mkbp_wake_mask(struct host_cmd_handler_args *args)
 		case EC_MKBP_HOST_EVENT_WAKE_MASK:
 			CPRINTF("MKBP hostevent mask updated to: 0x%08x "
 				"(was 0x%08x)\n",
-				p->new_wake_mask,
-				mkbp_host_event_wake_mask);
+				p->new_wake_mask, mkbp_host_event_wake_mask);
 			mkbp_host_event_wake_mask = p->new_wake_mask;
 			break;
 #endif /* CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK */
@@ -471,15 +560,13 @@ static enum ec_status hc_mkbp_wake_mask(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_MKBP_WAKE_MASK,
-		     hc_mkbp_wake_mask,
-		     EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_MKBP_WAKE_MASK, hc_mkbp_wake_mask, EC_VER_MASK(0));
 
-static int command_mkbp_wake_mask(int argc, char **argv)
+static int command_mkbp_wake_mask(int argc, const char **argv)
 {
 	if (argc == 3) {
 		char *e;
-		uint32_t new_mask = strtoul(argv[2], &e, 0);
+		uint32_t new_mask = strtoull(argv[2], &e, 0);
 
 		if (*e)
 			return EC_ERROR_PARAM2;
@@ -510,3 +597,22 @@ DECLARE_CONSOLE_COMMAND(mkbpwakemask, command_mkbp_wake_mask,
 			"[event | hostevent] [new_mask]",
 			"Show or set MKBP event/hostevent wake mask");
 #endif /* CONFIG_MKBP_(HOST)?EVENT_WAKEUP_MASK */
+
+#ifdef TEST_BUILD
+void mkbp_event_clear_all(void)
+{
+	mutex_lock(&state.lock);
+	state.events = 0;
+	mutex_unlock(&state.lock);
+
+	/* Reset the interrupt line */
+	mkbp_set_host_active(0, NULL);
+#ifdef CONFIG_MKBP_EVENT_WAKEUP_MASK
+	mkbp_event_wake_mask = CONFIG_MKBP_EVENT_WAKEUP_MASK;
+#endif /* CONFIG_MKBP_EVENT_WAKEUP_MASK */
+
+#ifdef CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK
+	mkbp_host_event_wake_mask = CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK;
+#endif /* CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK */
+}
+#endif
diff --git a/common/mkbp_fifo.c b/common/mkbp_fifo.c
new file mode 100644
index 0000000000..8aaf1a5940
--- /dev/null
+++ b/common/mkbp_fifo.c
@@ -0,0 +1,239 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Matrix KeyBoard Protocol FIFO buffer implementation
+ */
+
+#include "atomic.h"
+#include "common.h"
+#include "keyboard_config.h"
+#include "mkbp_event.h"
+#include "mkbp_fifo.h"
+#include "system.h"
+#include "task.h"
+#include "util.h"
+
+/* Console output macros */
+#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ##args)
+
+/*
+ * Common FIFO depth.  This needs to be big enough not to overflow if a
+ * series of keys is pressed in rapid succession and the kernel is too busy
+ * to read them out right away.
+ *
+ * RAM usage is (depth * #cols); A 16-entry FIFO will consume 16x16=256 bytes,
+ * which is non-trivial but not horrible.
+ */
+
+static uint32_t fifo_start; /* first entry */
+static uint32_t fifo_end; /* last entry */
+static atomic_t fifo_entries; /* number of existing entries */
+static uint8_t fifo_max_depth = FIFO_DEPTH;
+static struct ec_response_get_next_event_v1 fifo[FIFO_DEPTH];
+
+BUILD_ASSERT(sizeof(fifo[0].data) >= KEYBOARD_COLS_MAX);
+
+/*
+ * Mutex for critical sections of mkbp_fifo_add(), which is called
+ * from various tasks.
+ */
+K_MUTEX_DEFINE(fifo_add_mutex);
+/*
+ * Mutex for critical sections of fifo_remove(), which is called from the
+ * hostcmd task and from keyboard_clear_buffer().
+ */
+K_MUTEX_DEFINE(fifo_remove_mutex);
+
+static int get_data_size(enum ec_mkbp_event e)
+{
+	switch (e) {
+	case EC_MKBP_EVENT_KEY_MATRIX:
+		return KEYBOARD_COLS_MAX;
+
+	case EC_MKBP_EVENT_HOST_EVENT64:
+		return sizeof(uint64_t);
+
+	case EC_MKBP_EVENT_HOST_EVENT:
+	case EC_MKBP_EVENT_BUTTON:
+	case EC_MKBP_EVENT_SWITCH:
+	case EC_MKBP_EVENT_SYSRQ:
+		return sizeof(uint32_t);
+	default:
+		/* For unknown types, say it's 0. */
+		return 0;
+	}
+}
+
+/**
+ * Pop MKBP event data from FIFO
+ *
+ * @return EC_SUCCESS if entry popped, EC_ERROR_UNKNOWN if FIFO is empty
+ */
+static int fifo_remove(uint8_t *buffp)
+{
+	int size;
+
+	mutex_lock(&fifo_remove_mutex);
+	if (!fifo_entries) {
+		/* no entry remaining in FIFO : return last known state */
+		int last = (fifo_start + FIFO_DEPTH - 1) % FIFO_DEPTH;
+
+		size = get_data_size(fifo[last].event_type);
+
+		memcpy(buffp, &fifo[last].data, size);
+		mutex_unlock(&fifo_remove_mutex);
+
+		/*
+		 * Bail out without changing any FIFO indices and let the
+		 * caller know something strange happened. The buffer will
+		 * will contain the last known state of the keyboard.
+		 */
+		return EC_ERROR_UNKNOWN;
+	}
+
+	/* Return just the event data. */
+	if (buffp) {
+		size = get_data_size(fifo[fifo_start].event_type);
+		/* skip over event_type. */
+		memcpy(buffp, &fifo[fifo_start].data, size);
+	}
+
+	fifo_start = (fifo_start + 1) % FIFO_DEPTH;
+	atomic_sub(&fifo_entries, 1);
+	mutex_unlock(&fifo_remove_mutex);
+
+	return EC_SUCCESS;
+}
+
+/*****************************************************************************/
+/* Interface */
+
+void mkbp_fifo_depth_update(uint8_t new_max_depth)
+{
+	fifo_max_depth = new_max_depth;
+}
+
+void mkbp_fifo_clear_keyboard(void)
+{
+	int i, new_fifo_entries = 0;
+
+	CPRINTS("clear keyboard MKBP fifo");
+
+	/*
+	 * Order of these locks is important to prevent deadlock since
+	 * mkbp_fifo_add() may call fifo_remove().
+	 */
+	mutex_lock(&fifo_add_mutex);
+	mutex_lock(&fifo_remove_mutex);
+
+	/* Reset the end position */
+	fifo_end = fifo_start;
+
+	for (i = 0; i < fifo_entries; i++) {
+		int cur = (fifo_start + i) % FIFO_DEPTH;
+
+		/* Drop keyboard events */
+		if (fifo[cur].event_type == EC_MKBP_EVENT_KEY_MATRIX)
+			continue;
+
+		/* And move other events to the front */
+		memmove(&fifo[fifo_end], &fifo[cur], sizeof(fifo[cur]));
+		fifo_end = (fifo_end + 1) % FIFO_DEPTH;
+		++new_fifo_entries;
+	}
+	fifo_entries = new_fifo_entries;
+
+	mutex_unlock(&fifo_remove_mutex);
+	mutex_unlock(&fifo_add_mutex);
+}
+
+void mkbp_clear_fifo(void)
+{
+	int i;
+
+	CPRINTS("clear MKBP fifo");
+
+	/*
+	 * Order of these locks is important to prevent deadlock since
+	 * mkbp_fifo_add() may call fifo_remove().
+	 */
+	mutex_lock(&fifo_add_mutex);
+	mutex_lock(&fifo_remove_mutex);
+
+	fifo_start = 0;
+	fifo_end = 0;
+	/* This assignment is safe since both mutexes are held. */
+	fifo_entries = 0;
+	for (i = 0; i < FIFO_DEPTH; i++)
+		memset(&fifo[i], 0, sizeof(struct ec_response_get_next_event));
+
+	mutex_unlock(&fifo_remove_mutex);
+	mutex_unlock(&fifo_add_mutex);
+}
+
+test_mockable int mkbp_fifo_add(uint8_t event_type, const uint8_t *buffp)
+{
+	uint8_t size;
+
+	mutex_lock(&fifo_add_mutex);
+	if (fifo_entries >= fifo_max_depth) {
+		mutex_unlock(&fifo_add_mutex);
+		CPRINTS("MKBP common FIFO depth %d reached", fifo_max_depth);
+
+		return EC_ERROR_OVERFLOW;
+	}
+
+	size = get_data_size(event_type);
+	fifo[fifo_end].event_type = event_type;
+	memcpy(&fifo[fifo_end].data, buffp, size);
+	fifo_end = (fifo_end + 1) % FIFO_DEPTH;
+	atomic_add(&fifo_entries, 1);
+
+	/*
+	 * If our event didn't generate an interrupt then the host is still
+	 * asleep. In this case, we don't want to queue our event, except if
+	 * another event just woke the host (and wake is already in progress).
+	 */
+	if (!mkbp_send_event(event_type) && fifo_entries == 1)
+		fifo_remove(NULL);
+
+	mutex_unlock(&fifo_add_mutex);
+	return EC_SUCCESS;
+}
+
+int mkbp_fifo_get_next_event(uint8_t *out, enum ec_mkbp_event evt)
+{
+	uint8_t t = fifo[fifo_start].event_type;
+	uint8_t size;
+
+	if (!fifo_entries)
+		return -1;
+
+	/*
+	 * We need to peek at the next event to check that we were called with
+	 * the correct event.
+	 */
+	if (t != (uint8_t)evt) {
+		/*
+		 * We were called with the wrong event.  The next element in the
+		 * FIFO's event type doesn't match with what we were called
+		 * with.  Return an error that we're busy.  The caller will need
+		 * to call us with the correct event first.
+		 */
+		return -EC_ERROR_BUSY;
+	}
+
+	fifo_remove(out);
+
+	/* Keep sending events if FIFO is not empty */
+	if (fifo_entries)
+		mkbp_send_event(fifo[fifo_start].event_type);
+
+	/* Return the correct size of the data. */
+	size = get_data_size(t);
+	if (size)
+		return size;
+	else
+		return -EC_ERROR_UNKNOWN;
+}
diff --git a/common/mkbp_info.c b/common/mkbp_info.c
new file mode 100644
index 0000000000..c8cc6e7f58
--- /dev/null
+++ b/common/mkbp_info.c
@@ -0,0 +1,155 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* MKBP info host command */
+
+#include "common.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "host_command.h"
+#include "keyboard_config.h"
+#include "keyboard_mkbp.h"
+#include "keyboard_scan.h"
+#include "mkbp_info.h"
+#include "mkbp_input_devices.h"
+#include "util.h"
+
+__overridable int mkbp_support_volume_buttons(void)
+{
+#ifdef CONFIG_VOLUME_BUTTONS
+	return 1;
+#else
+	return 0;
+#endif
+}
+
+test_export_static uint32_t get_supported_buttons(void)
+{
+	uint32_t val = 0;
+
+	if (mkbp_support_volume_buttons()) {
+		val |= BIT(EC_MKBP_VOL_UP) | BIT(EC_MKBP_VOL_DOWN);
+	}
+
+#ifdef CONFIG_DEDICATED_RECOVERY_BUTTON
+	val |= BIT(EC_MKBP_RECOVERY);
+#endif /* defined(CONFIG_DEDICATED_RECOVERY_BUTTON) */
+
+#ifdef CONFIG_POWER_BUTTON
+	val |= BIT(EC_MKBP_POWER_BUTTON);
+#endif /* defined(CONFIG_POWER_BUTTON) */
+
+	return val;
+}
+
+test_export_static uint32_t get_supported_switches(void)
+{
+	uint32_t val = 0;
+
+#ifdef CONFIG_LID_SWITCH
+	val |= BIT(EC_MKBP_LID_OPEN);
+#endif
+#ifdef CONFIG_TABLET_MODE_SWITCH
+	val |= BIT(EC_MKBP_TABLET_MODE);
+#endif
+#ifdef CONFIG_BASE_ATTACHED_SWITCH
+	val |= BIT(EC_MKBP_BASE_ATTACHED);
+#endif
+#ifdef CONFIG_FRONT_PROXIMITY_SWITCH
+	val |= BIT(EC_MKBP_FRONT_PROXIMITY);
+#endif
+	return val;
+}
+
+static enum ec_status mkbp_get_info(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_mkbp_info *p = args->params;
+
+	if (args->params_size == 0 || p->info_type == EC_MKBP_INFO_KBD) {
+		struct ec_response_mkbp_info *r = args->response;
+
+#ifdef CONFIG_KEYBOARD_PROTOCOL_MKBP
+		/* Version 0 just returns info about the keyboard. */
+		r->rows = KEYBOARD_ROWS;
+		r->cols = KEYBOARD_COLS_MAX;
+#else
+		r->rows = 0;
+		r->cols = 0;
+#endif /* CONFIG_KEYBOARD_PROTOCOL_MKBP */
+
+		/* This used to be "switches" which was previously 0. */
+		r->reserved = 0;
+
+		args->response_size = sizeof(struct ec_response_mkbp_info);
+	} else {
+		union ec_response_get_next_data *r = args->response;
+
+		/* Version 1 (other than EC_MKBP_INFO_KBD) */
+		switch (p->info_type) {
+		case EC_MKBP_INFO_SUPPORTED:
+			switch (p->event_type) {
+			case EC_MKBP_EVENT_BUTTON:
+				r->buttons = get_supported_buttons();
+				args->response_size = sizeof(r->buttons);
+				break;
+
+			case EC_MKBP_EVENT_SWITCH:
+				r->switches = get_supported_switches();
+				args->response_size = sizeof(r->switches);
+				break;
+
+			default:
+				/* Don't care for now for other types. */
+				return EC_RES_INVALID_PARAM;
+			}
+			break;
+
+		case EC_MKBP_INFO_CURRENT:
+			switch (p->event_type) {
+#ifdef HAS_TASK_KEYSCAN
+			case EC_MKBP_EVENT_KEY_MATRIX:
+				memcpy(r->key_matrix, keyboard_scan_get_state(),
+				       sizeof(r->key_matrix));
+				args->response_size = sizeof(r->key_matrix);
+				break;
+#endif
+			case EC_MKBP_EVENT_HOST_EVENT:
+				r->host_event = (uint32_t)host_get_events();
+				args->response_size = sizeof(r->host_event);
+				break;
+
+			case EC_MKBP_EVENT_HOST_EVENT64:
+				r->host_event64 = host_get_events();
+				args->response_size = sizeof(r->host_event64);
+				break;
+
+#ifdef CONFIG_MKBP_INPUT_DEVICES
+			case EC_MKBP_EVENT_BUTTON:
+				r->buttons = mkbp_get_button_state();
+				args->response_size = sizeof(r->buttons);
+				break;
+
+			case EC_MKBP_EVENT_SWITCH:
+				r->switches = mkbp_get_switch_state();
+				args->response_size = sizeof(r->switches);
+				break;
+#endif /* CONFIG_MKBP_INPUT_DEVICES */
+
+			default:
+				/* Doesn't make sense for other event types. */
+				return EC_RES_INVALID_PARAM;
+			}
+			break;
+
+		default:
+			/* Unsupported query. */
+			return EC_RES_ERROR;
+		}
+	}
+	return EC_RES_SUCCESS;
+}
+
+DECLARE_HOST_COMMAND(EC_CMD_MKBP_INFO, mkbp_get_info,
+		     EC_VER_MASK(0) | EC_VER_MASK(1));
diff --git a/common/mkbp_input_devices.c b/common/mkbp_input_devices.c
new file mode 100644
index 0000000000..f2fad5da21
--- /dev/null
+++ b/common/mkbp_input_devices.c
@@ -0,0 +1,243 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Input devices using Matrix Keyboard Protocol [MKBP] events for Chrome EC */
+
+#include "base_state.h"
+#include "body_detection.h"
+#include "button.h"
+#include "console.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "keyboard_mkbp.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "mkbp_event.h"
+#include "mkbp_fifo.h"
+#include "mkbp_input_devices.h"
+#include "power_button.h"
+#include "tablet_mode.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ##args)
+
+/* Buttons state. */
+static uint32_t mkbp_button_state;
+
+static bool mkbp_init_done;
+
+uint32_t mkbp_get_switch_state(void)
+{
+	uint32_t mkbp_switch_state = 0;
+
+	/*
+	 * These all read already debounced states and cause no side effects
+	 * or latency.
+	 */
+	if (IS_ENABLED(CONFIG_LID_SWITCH))
+		mkbp_switch_state |= lid_is_open() << EC_MKBP_LID_OPEN;
+	if (IS_ENABLED(CONFIG_TABLET_MODE_SWITCH))
+		mkbp_switch_state |= tablet_get_mode() << EC_MKBP_TABLET_MODE;
+	if (IS_ENABLED(CONFIG_BASE_ATTACHED_SWITCH))
+		mkbp_switch_state |= base_get_state() << EC_MKBP_BASE_ATTACHED;
+	if (IS_ENABLED(CONFIG_BODY_DETECTION_NOTIFY_MKBP))
+		mkbp_switch_state |= body_detect_get_state()
+				     << EC_MKBP_FRONT_PROXIMITY;
+	return mkbp_switch_state;
+};
+
+uint32_t mkbp_get_button_state(void)
+{
+	return mkbp_button_state;
+};
+
+void mkbp_button_update(enum keyboard_button_type button, int is_pressed)
+{
+	switch (button) {
+	case KEYBOARD_BUTTON_POWER:
+		mkbp_button_state &= ~BIT(EC_MKBP_POWER_BUTTON);
+		mkbp_button_state |= (is_pressed << EC_MKBP_POWER_BUTTON);
+		break;
+
+	case KEYBOARD_BUTTON_VOLUME_UP:
+		mkbp_button_state &= ~BIT(EC_MKBP_VOL_UP);
+		mkbp_button_state |= (is_pressed << EC_MKBP_VOL_UP);
+		break;
+
+	case KEYBOARD_BUTTON_VOLUME_DOWN:
+		mkbp_button_state &= ~BIT(EC_MKBP_VOL_DOWN);
+		mkbp_button_state |= (is_pressed << EC_MKBP_VOL_DOWN);
+		break;
+
+	case KEYBOARD_BUTTON_RECOVERY:
+		mkbp_button_state &= ~BIT(EC_MKBP_RECOVERY);
+		mkbp_button_state |= (is_pressed << EC_MKBP_RECOVERY);
+		break;
+
+	default:
+		/* ignored. */
+		return;
+	}
+
+	CPRINTS("mkbp buttons: %x", mkbp_button_state);
+
+	mkbp_fifo_add(EC_MKBP_EVENT_BUTTON,
+		      (const uint8_t *)&mkbp_button_state);
+};
+
+void mkbp_update_switches(void)
+{
+	/*
+	 * Only inform AP mkbp changes when all switches initialized, in case
+	 * of the middle states causing the weird behaviour in the AP side,
+	 * especially when sysjumped while AP up.
+	 */
+	if (mkbp_init_done) {
+		uint32_t mkbp_switch_state = mkbp_get_switch_state();
+
+		CPRINTS("mkbp switches: %x", mkbp_switch_state);
+		mkbp_fifo_add(EC_MKBP_EVENT_SWITCH,
+			      (const uint8_t *)&mkbp_switch_state);
+	}
+}
+
+/*****************************************************************************/
+/* Hooks */
+
+#ifdef CONFIG_POWER_BUTTON
+/**
+ * Handle power button changing state.
+ */
+static void keyboard_power_button(void)
+{
+	mkbp_button_update(KEYBOARD_BUTTON_POWER, power_button_is_pressed());
+}
+DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, keyboard_power_button,
+	     HOOK_PRIO_DEFAULT);
+#endif /* defined(CONFIG_POWER_BUTTON) */
+
+#ifdef CONFIG_LID_SWITCH
+/**
+ * Handle lid changing state.
+ */
+DECLARE_HOOK(HOOK_LID_CHANGE, mkbp_update_switches, HOOK_PRIO_LAST);
+#endif
+
+#ifdef CONFIG_TABLET_MODE_SWITCH
+DECLARE_HOOK(HOOK_TABLET_MODE_CHANGE, mkbp_update_switches, HOOK_PRIO_LAST);
+#endif
+
+#ifdef CONFIG_BASE_ATTACHED_SWITCH
+DECLARE_HOOK(HOOK_BASE_ATTACHED_CHANGE, mkbp_update_switches, HOOK_PRIO_LAST);
+#endif
+
+#ifdef CONFIG_BODY_DETECTION_NOTIFY_MKBP
+DECLARE_HOOK(HOOK_BODY_DETECT_CHANGE, mkbp_update_switches, HOOK_PRIO_LAST);
+#endif
+
+static void mkbp_report_switch_on_init(void)
+{
+	/* All switches initialized, report switch state to AP */
+	mkbp_init_done = true;
+	mkbp_update_switches();
+}
+DECLARE_HOOK(HOOK_INIT, mkbp_report_switch_on_init, HOOK_PRIO_LAST);
+
+#ifdef CONFIG_EMULATED_SYSRQ
+void host_send_sysrq(uint8_t key)
+{
+	uint32_t value = key;
+
+	mkbp_fifo_add(EC_MKBP_EVENT_SYSRQ, (const uint8_t *)&value);
+}
+#endif
+
+/*****************************************************************************/
+/* Events */
+
+static int mkbp_button_get_next_event(uint8_t *out)
+{
+	return mkbp_fifo_get_next_event(out, EC_MKBP_EVENT_BUTTON);
+}
+DECLARE_EVENT_SOURCE(EC_MKBP_EVENT_BUTTON, mkbp_button_get_next_event);
+
+static int switch_get_next_event(uint8_t *out)
+{
+	return mkbp_fifo_get_next_event(out, EC_MKBP_EVENT_SWITCH);
+}
+DECLARE_EVENT_SOURCE(EC_MKBP_EVENT_SWITCH, switch_get_next_event);
+
+#ifdef CONFIG_EMULATED_SYSRQ
+static int sysrq_get_next_event(uint8_t *out)
+{
+	return mkbp_fifo_get_next_event(out, EC_MKBP_EVENT_SYSRQ);
+}
+DECLARE_EVENT_SOURCE(EC_MKBP_EVENT_SYSRQ, sysrq_get_next_event);
+#endif
+
+/************************ Keyboard press simulation ************************/
+#ifndef HAS_TASK_KEYSCAN
+/* Keys simulated-pressed */
+static uint8_t simulated_key[KEYBOARD_COLS_MAX];
+uint8_t keyboard_cols = KEYBOARD_COLS_MAX;
+
+/* For boards without a keyscan task, try and simulate keyboard presses. */
+static void simulate_key(int row, int col, int pressed)
+{
+	if ((simulated_key[col] & BIT(row)) == ((pressed ? 1 : 0) << row))
+		return; /* No change */
+
+	simulated_key[col] &= ~BIT(row);
+	if (pressed)
+		simulated_key[col] |= BIT(row);
+
+	mkbp_fifo_add((uint8_t)EC_MKBP_EVENT_KEY_MATRIX, simulated_key);
+}
+
+static int command_mkbp_keyboard_press(int argc, const char **argv)
+{
+	if (argc == 1) {
+		int i, j;
+
+		ccputs("Simulated keys:\n");
+		for (i = 0; i < keyboard_cols; ++i) {
+			if (simulated_key[i] == 0)
+				continue;
+			for (j = 0; j < KEYBOARD_ROWS; ++j)
+				if (simulated_key[i] & BIT(j))
+					ccprintf("\t%d %d\n", i, j);
+		}
+
+	} else if (argc == 3 || argc == 4) {
+		int r, c, p;
+		char *e;
+
+		c = strtoi(argv[1], &e, 0);
+		if (*e || c < 0 || c >= keyboard_cols)
+			return EC_ERROR_PARAM1;
+
+		r = strtoi(argv[2], &e, 0);
+		if (*e || r < 0 || r >= KEYBOARD_ROWS)
+			return EC_ERROR_PARAM2;
+
+		if (argc == 3) {
+			/* Simulate a press and release */
+			simulate_key(r, c, 1);
+			simulate_key(r, c, 0);
+		} else {
+			p = strtoi(argv[3], &e, 0);
+			if (*e || p < 0 || p > 1)
+				return EC_ERROR_PARAM3;
+
+			simulate_key(r, c, p);
+		}
+	}
+
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(kbpress, command_mkbp_keyboard_press,
+			"[col row [0 | 1]]", "Simulate keypress");
+
+#endif /* !defined(HAS_TASK_KEYSCAN) */
diff --git a/common/mock/README.md b/common/mock/README.md
index bb85217bde..ab91f9f927 100644
--- a/common/mock/README.md
+++ b/common/mock/README.md
@@ -1,25 +1,24 @@
 # Common Mocks
+
 This directory holds mock implementations for use in fuzzers and tests.
 
-Each mock is given some friendly build name, like ROLLBACK or FP_SENSOR.
-This name is defined in [common/mock/build.mk](build.mk) and referenced
-from unit tests and fuzzers' `.mocklist` file.
+Each mock is given some friendly build name, like ROLLBACK or FP_SENSOR. This
+name is defined in [common/mock/build.mk](build.mk) and referenced from unit
+tests and fuzzers' `.mocklist` file.
 
 ## Creating a new mock
 
-* Add the mock source to [common/mock](/common/mock) and the
-  optional header file to [include/mock](/include/mock).
-  Header files are only necessary if you want to expose additional
-  [mock control](#mock-controls) functions/variables.
-  See the [Design Patterns](#design-patterns) section
-  for more detail on design patterns.
-* Add a new entry in [common/mock/build.mk](build.mk)
-  that is conditioned on your mock's name.
+*   Add the mock source to [common/mock](/common/mock) and the optional header
+    file to [include/mock](/include/mock). Header files are only necessary if
+    you want to expose additional [mock control](#mock-controls)
+    functions/variables. See the [Design Patterns](#design-patterns) section for
+    more detail on design patterns.
+*   Add a new entry in [common/mock/build.mk](build.mk) that is conditioned on
+    your mock's name.
 
-If a unit test or fuzzer requests this mock, the build system will
-set the variable `HAS_MOCK_<BUILD_NAME>` to `y` at build time.
-This variable is used to conditionally include the mock source
-in [common/mock/build.mk](build.mk).
+If a unit test or fuzzer requests this mock, the build system will set the
+variable `HAS_MOCK_<BUILD_NAME>` to `y` at build time. This variable is used to
+conditionally include the mock source in [common/mock/build.mk](build.mk).
 
 Example line from [common/mock/build.mk](build.mk):
 
@@ -29,28 +28,29 @@ mock-$(HAS_MOCK_ROLLBACK) += mock/rollback_mock.o
 ```
 
 ## Using a mock
-Unit tests and fuzzers can request a particular mock by adding an entry to
-their `.mocklist` file. The mocklist file is similar to a `.tasklist`
-file, where it is named according to the test/fuzz's name followed by
-`.mocklist`, like `fpsensor.mocklist`.
-The mocklist file is optional, so you may need to create one.
+
+Unit tests and fuzzers can request a particular mock by adding an entry to their
+`.mocklist` file. The mocklist file is similar to a `.tasklist` file, where it
+is named according to the test/fuzz's name followed by `.mocklist`, like
+`fpsensor.mocklist`. The mocklist file is optional, so you may need to create
+one.
 
 Example `.mocklist`:
 
 ```c
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
  #define CONFIG_TEST_MOCK_LIST \
-	MOCK(ROLLBACK)         \
-	MOCK(FP_SENSOR)
+    MOCK(ROLLBACK)             \
+    MOCK(FPSENSOR)
 ```
 
-If you need additional [mock control](#mock-controls) functionality,
-you may need to include the mock's header file, which is prepended
-with `mock/` in the include line.
+If you need additional [mock control](#mock-controls) functionality, you may
+need to include the mock's header file, which is prepended with `mock/` in the
+include line.
 
 For example, to control the return values of the rollback mock:
 
@@ -58,30 +58,31 @@ For example, to control the return values of the rollback mock:
 #include "mock/rollback_mock.h"
 
 void yourfunction() {
-	mock_ctrl_rollback.get_secret_fail = true;
+    mock_ctrl_rollback.get_secret_fail = true;
 }
 ```
 
 ## Mock Controls
+
 Mocks can change their behavior by exposing "mock controls".
 
-We do this, most commonly, by exposing an additional global struct
-per mock that acts as the settings for the mock implementation.
-The mock user can then modify fields of the struct to change the mock's behavior.
-For example, the `fp_sensor_init_return` field may control what value
-the mocked `fp_sensor_init` function returns.
+We do this, most commonly, by exposing an additional global struct per mock that
+acts as the settings for the mock implementation. The mock user can then modify
+fields of the struct to change the mock's behavior. For example, the
+`fp_sensor_init_return` field may control what value the mocked `fp_sensor_init`
+function returns.
 
 The declaration for these controls are specified in the mock's header file,
 which resides in [include/mock](/include/mock).
 
 ## Design Patterns
-* When creating mock controls, consider placing all your mock parameters in
-  one externally facing struct, like in
-  [fp_sensor_mock.h](/include/mock/fp_sensor_mock.h).
-  The primary reason for this is to allow the mock to be easily used
-  by a fuzzer (write random bytes into the struct with memcpy).
-* When following the above pattern, please provide a macro for resetting
-  default values for this struct, like in
-  [fp_sensor_mock.h](/include/mock/fp_sensor_mock.h).
-  This allows unit tests to quickly reset the mock state/parameters
-  before each unrelated unit test.
+
+*   When creating mock controls, consider placing all your mock parameters in
+    one externally facing struct, like in
+    [fpsensor_mock.h](/include/mock/fpsensor_mock.h). The primary reason for
+    this is to allow the mock to be easily used by a fuzzer (write random bytes
+    into the struct with memcpy).
+*   When following the above pattern, please provide a macro for resetting
+    default values for this struct, like in
+    [fpsensor_mock.h](/include/mock/fpsensor_mock.h). This allows unit tests
+    to quickly reset the mock state/parameters before each unrelated unit test.
diff --git a/common/mock/adc_mock.c b/common/mock/adc_mock.c
new file mode 100644
index 0000000000..35cf4aadb5
--- /dev/null
+++ b/common/mock/adc_mock.c
@@ -0,0 +1,11 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc.h"
+
+int adc_read_channel(enum adc_channel ch)
+{
+	return 0;
+}
diff --git a/common/mock/battery_mock.c b/common/mock/battery_mock.c
new file mode 100644
index 0000000000..7bf15fb60a
--- /dev/null
+++ b/common/mock/battery_mock.c
@@ -0,0 +1,223 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "string.h"
+
+/*****************************************************************************
+ * Battery functions needed to enable CONFIG_BATTERY
+ */
+static int battery_soc_value = 100;
+int board_get_battery_soc(void)
+{
+	return battery_soc_value;
+}
+void set_battery_soc(int new_value)
+{
+	battery_soc_value = new_value;
+}
+
+static int battery_status_value;
+int battery_status(int *status)
+{
+	*status = battery_status_value;
+	return EC_SUCCESS;
+}
+void set_battery_status(int new_value)
+{
+	battery_status_value = new_value;
+}
+
+static int battery_serial_number_value;
+int battery_serial_number(int *serial)
+{
+	*serial = battery_serial_number_value;
+	return EC_SUCCESS;
+}
+void set_battery_serial_number(int new_value)
+{
+	battery_serial_number_value = new_value;
+}
+
+static int battery_cycle_count_value;
+int battery_cycle_count(int *count)
+{
+	*count = battery_cycle_count_value;
+	return EC_SUCCESS;
+}
+void set_battery_cycle_count(int new_value)
+{
+	battery_cycle_count_value = new_value;
+}
+
+static int battery_design_voltage_value = 5000;
+int battery_design_voltage(int *voltage)
+{
+	*voltage = battery_design_voltage_value;
+	return EC_SUCCESS;
+}
+void set_battery_design_voltage(int new_value)
+{
+	battery_design_voltage_value = new_value;
+}
+
+static int battery_mode_value;
+int battery_get_mode(int *mode)
+{
+	*mode = battery_mode_value;
+	return EC_SUCCESS;
+}
+void set_battery_mode(int new_value)
+{
+	battery_mode_value = new_value;
+}
+
+static int battery_soc_abs_value = 100;
+int battery_state_of_charge_abs(int *percent)
+{
+	*percent = battery_soc_abs_value;
+	return EC_SUCCESS;
+}
+void set_battery_soc_abs(int new_value)
+{
+	battery_soc_abs_value = new_value;
+}
+
+static int battery_remaining_capacity_value = 100;
+int battery_remaining_capacity(int *capacity)
+{
+	*capacity = battery_remaining_capacity_value;
+	return EC_SUCCESS;
+}
+void set_battery_remaining_capacity(int new_value)
+{
+	battery_remaining_capacity_value = new_value;
+}
+
+static int battery_full_charge_capacity_value = 100;
+int battery_full_charge_capacity(int *capacity)
+{
+	*capacity = battery_full_charge_capacity_value;
+	return EC_SUCCESS;
+}
+void set_battery_full_charge_capacity(int new_value)
+{
+	battery_full_charge_capacity_value = new_value;
+}
+
+static int battery_design_capacity_value = 100;
+int battery_design_capacity(int *capacity)
+{
+	*capacity = battery_design_capacity_value;
+	return EC_SUCCESS;
+}
+void set_battery_design_capacity(int new_value)
+{
+	battery_design_capacity_value = new_value;
+}
+
+static int battery_time_to_empty_value = 60;
+int battery_time_to_empty(int *minutes)
+{
+	*minutes = battery_time_to_empty_value;
+	return EC_SUCCESS;
+}
+void set_battery_time_to_empty(int new_value)
+{
+	battery_time_to_empty_value = new_value;
+}
+
+static int battery_run_time_to_empty_value = 60;
+int battery_run_time_to_empty(int *minutes)
+{
+	*minutes = battery_run_time_to_empty_value;
+	return EC_SUCCESS;
+}
+void set_battery_run_time_to_empty(int new_value)
+{
+	battery_run_time_to_empty_value = new_value;
+}
+
+static int battery_time_to_full_value;
+int battery_time_to_full(int *minutes)
+{
+	*minutes = battery_time_to_full_value;
+	return EC_SUCCESS;
+}
+void set_battery_time_to_full(int new_value)
+{
+	battery_time_to_full_value = new_value;
+}
+
+#define MAX_DEVICE_NAME_LENGTH 40
+static char battery_device_name_value[MAX_DEVICE_NAME_LENGTH + 1] = "?";
+int battery_device_name(char *dest, int size)
+{
+	int i;
+
+	for (i = 0; i < size && i < MAX_DEVICE_NAME_LENGTH; ++i)
+		dest[i] = battery_device_name_value[i];
+	for (; i < size; ++i)
+		dest[i] = '\0';
+	return EC_SUCCESS;
+}
+void set_battery_device_name(char *new_value)
+{
+	int i;
+	int size = strlen(new_value);
+
+	for (i = 0; i < size && i < MAX_DEVICE_NAME_LENGTH; ++i)
+		battery_device_name_value[i] = new_value[i];
+	for (; i < MAX_DEVICE_NAME_LENGTH + 1; ++i)
+		battery_device_name_value[i] = '\0';
+}
+
+#define MAX_DEVICE_CHEMISTRY_LENGTH 40
+static char battery_device_chemistry_value[MAX_DEVICE_CHEMISTRY_LENGTH + 1] =
+	"?";
+int battery_device_chemistry(char *dest, int size)
+{
+	int i;
+
+	for (i = 0; i < size && i < MAX_DEVICE_CHEMISTRY_LENGTH; ++i)
+		dest[i] = battery_device_chemistry_value[i];
+	for (; i < size; ++i)
+		dest[i] = '\0';
+	return EC_SUCCESS;
+}
+void set_battery_device_chemistry(char *new_value)
+{
+	int i;
+	int size = strlen(new_value);
+
+	for (i = 0; i < size && i < MAX_DEVICE_CHEMISTRY_LENGTH; ++i)
+		battery_device_chemistry_value[i] = new_value[i];
+	for (; i < MAX_DEVICE_CHEMISTRY_LENGTH + 1; ++i)
+		battery_device_chemistry_value[i] = '\0';
+}
+
+static int battery_current_value = 3000;
+static int battery_desired_current_value = 3000;
+static int battery_desired_voltage_value = 5000;
+static int battery_is_present_value = BP_YES;
+static int battery_temperature_value = 20;
+static int battery_voltage_value = 5000;
+void battery_get_params(struct batt_params *batt)
+{
+	struct batt_params batt_new = { 0 };
+
+	batt_new.temperature = battery_temperature_value;
+	batt_new.state_of_charge = battery_soc_value;
+	batt_new.voltage = battery_voltage_value;
+	batt_new.current = battery_current_value;
+	batt_new.desired_voltage = battery_desired_voltage_value;
+	batt_new.desired_current = battery_desired_current_value;
+	batt_new.remaining_capacity = battery_remaining_capacity_value;
+	batt_new.full_capacity = battery_full_charge_capacity_value;
+	batt_new.status = battery_status_value;
+	batt_new.is_present = battery_is_present_value;
+
+	memcpy(batt, &batt_new, sizeof(*batt));
+}
diff --git a/common/mock/build.mk b/common/mock/build.mk
index 5f2d548825..1293f23f4d 100644
--- a/common/mock/build.mk
+++ b/common/mock/build.mk
@@ -1,22 +1,28 @@
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 # See common/mock/README.md for more information.
 
-mock-$(HAS_MOCK_FP_SENSOR) += fp_sensor_mock.o
+mock-$(HAS_MOCK_ADC) += adc_mock.o
+mock-$(HAS_MOCK_BATTERY) += battery_mock.o
+mock-$(HAS_MOCK_CHARGE_MANAGER) += charge_manager_mock.o
+mock-$(HAS_MOCK_CLOCK) += clock_mock.o
+mock-$(HAS_MOCK_FPSENSOR) += fpsensor_mock.o
+mock-$(HAS_MOCK_FPSENSOR_CRYPTO) += fpsensor_crypto_mock.o
 mock-$(HAS_MOCK_FPSENSOR_DETECT) += fpsensor_detect_mock.o
 mock-$(HAS_MOCK_FPSENSOR_STATE) += fpsensor_state_mock.o
 mock-$(HAS_MOCK_MKBP_EVENTS) += mkbp_events_mock.o
 mock-$(HAS_MOCK_ROLLBACK) += rollback_mock.o
+mock-$(HAS_MOCK_ROLLBACK_LATEST) += rollback_latest_mock.o
 mock-$(HAS_MOCK_TCPC) += tcpc_mock.o
 mock-$(HAS_MOCK_TCPM) += tcpm_mock.o
 mock-$(HAS_MOCK_TCPCI_I2C) += tcpci_i2c_mock.o
 mock-$(HAS_MOCK_TIMER) += timer_mock.o
 mock-$(HAS_MOCK_USB_MUX) += usb_mux_mock.o
-mock-$(HAS_MOCK_USB_PD) += usb_pd_mock.o
 mock-$(HAS_MOCK_USB_PE_SM) += usb_pe_sm_mock.o
 mock-$(HAS_MOCK_USB_TC_SM) += usb_tc_sm_mock.o
 mock-$(HAS_MOCK_USB_PD_DPM) += usb_pd_dpm_mock.o
 mock-$(HAS_MOCK_DP_ALT_MODE) += dp_alt_mode_mock.o
 mock-$(HAS_MOCK_USB_PRL) += usb_prl_mock.o
+mock-$(HAS_MOCK_USB_PE_DRP_SM) += usb_pe_drp_sm_mock.o
diff --git a/common/mock/charge_manager_mock.c b/common/mock/charge_manager_mock.c
new file mode 100644
index 0000000000..745b37efa7
--- /dev/null
+++ b/common/mock/charge_manager_mock.c
@@ -0,0 +1,64 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ * @brief Mock charge_manager
+ */
+
+#include "charge_manager.h"
+#include "common.h"
+#include "mock/charge_manager_mock.h"
+
+#include <stdlib.h>
+
+#ifndef TEST_BUILD
+#error "Mocks should only be in the test build."
+#endif
+
+void charge_manager_update_dualrole(int port, enum dualrole_capabilities cap)
+{
+}
+
+void charge_manager_set_ceil(int port, enum ceil_requestor requestor, int ceil)
+{
+}
+
+int charge_manager_get_selected_charge_port(void)
+{
+	return 0;
+}
+
+int charge_manager_get_active_charge_port(void)
+{
+	return 0;
+}
+
+int charge_manager_get_charger_voltage(void)
+{
+	return 0;
+}
+
+void charge_manager_force_ceil(int port, int ceil)
+{
+}
+
+enum charge_supplier charge_manager_get_supplier(void)
+{
+	return CHARGE_SUPPLIER_NONE;
+}
+
+int charge_manager_get_vbus_voltage(int port)
+{
+	return mock_ctrl_charge_manager.vbus_voltage_mv;
+}
+
+void mock_charge_manager_set_vbus_voltage(int voltage_mv)
+{
+	mock_ctrl_charge_manager.vbus_voltage_mv = voltage_mv;
+}
+
+struct mock_ctrl_charge_manager mock_ctrl_charge_manager =
+	MOCK_CTRL_DEFAULT_CHARGE_MANAGER;
diff --git a/common/mock/clock_mock.c b/common/mock/clock_mock.c
new file mode 100644
index 0000000000..876e691b57
--- /dev/null
+++ b/common/mock/clock_mock.c
@@ -0,0 +1,24 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "mock/clock_mock.h"
+
+#ifndef TEST_BUILD
+#error "Mocks should only be in the test build."
+#endif
+
+static int fast_cpu_state;
+
+void clock_enable_module(enum module_id module, int enable)
+{
+	if (module == MODULE_FAST_CPU) {
+		fast_cpu_state = enable;
+	}
+}
+
+int get_mock_fast_cpu_status(void)
+{
+	return fast_cpu_state;
+}
diff --git a/common/mock/dp_alt_mode_mock.c b/common/mock/dp_alt_mode_mock.c
index bc67d57a31..98f14949ed 100644
--- a/common/mock/dp_alt_mode_mock.c
+++ b/common/mock/dp_alt_mode_mock.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,12 +9,17 @@
  * section 5.2
  */
 
-#include "usb_dp_alt_mode.h"
+#include "console.h"
 #include "mock/dp_alt_mode_mock.h"
+#include "usb_dp_alt_mode.h"
+
+#ifndef TEST_BUILD
+#error "Mocks should only be in the test build."
+#endif
 
 #ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 #else
 #define CPRINTF(format, args...)
 #define CPRINTS(format, args...)
@@ -24,14 +29,3 @@ void mock_dp_alt_mode_reset(void)
 {
 	/* Nothing to do right now, but in the future ... */
 }
-
-void dp_init(int port)
-{
-	CPRINTS("C%d: DP init", port);
-}
-
-void dp_teardown(int port)
-{
-	CPRINTS("C%d: DP teardown", port);
-}
-
diff --git a/common/mock/fp_sensor_mock.c b/common/mock/fp_sensor_mock.c
deleted file mode 100644
index 18e6d656be..0000000000
--- a/common/mock/fp_sensor_mock.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- * @brief Mock fpsensor private driver
- */
-
-#include <stdlib.h>
-
-#include "common.h"
-#include "fpsensor.h"
-#include "mock/fp_sensor_mock.h"
-
-struct mock_ctrl_fp_sensor mock_ctrl_fp_sensor = MOCK_CTRL_DEFAULT_FP_SENSOR;
-
-int fp_sensor_init(void)
-{
-	return mock_ctrl_fp_sensor.fp_sensor_init_return;
-}
-
-int fp_sensor_deinit(void)
-{
-	return mock_ctrl_fp_sensor.fp_sensor_deinit_return;
-}
-
-int fp_sensor_get_info(struct ec_response_fp_info *resp)
-{
-	resp->version = 0;
-	return mock_ctrl_fp_sensor.fp_sensor_get_info_return;
-}
-
-void fp_sensor_low_power(void)
-{
-}
-
-void fp_sensor_configure_detect(void)
-{
-}
-
-enum finger_state fp_sensor_finger_status(void)
-{
-	return mock_ctrl_fp_sensor.fp_sensor_finger_status_return;
-}
-
-int fp_sensor_acquire_image(uint8_t *image_data)
-{
-	return mock_ctrl_fp_sensor.fp_sensor_acquire_image_return;
-}
-
-int fp_sensor_acquire_image_with_mode(uint8_t *image_data, int mode)
-{
-	return mock_ctrl_fp_sensor.fp_sensor_acquire_image_with_mode_return;
-}
-
-int fp_finger_match(void *templ, uint32_t templ_count,
-		    uint8_t *image, int32_t *match_index,
-		    uint32_t *update_bitmap)
-{
-	return mock_ctrl_fp_sensor.fp_finger_match_return;
-}
-
-int fp_enrollment_begin(void)
-{
-	return mock_ctrl_fp_sensor.fp_enrollment_begin_return;
-}
-
-int fp_enrollment_finish(void *templ)
-{
-	return mock_ctrl_fp_sensor.fp_enrollment_finish_return;
-}
-
-int fp_finger_enroll(uint8_t *image, int *completion)
-{
-	return mock_ctrl_fp_sensor.fp_finger_enroll_return;
-}
-
-int fp_maintenance(void)
-{
-	return mock_ctrl_fp_sensor.fp_maintenance_return;
-}
diff --git a/common/mock/fpsensor_crypto_mock.c b/common/mock/fpsensor_crypto_mock.c
new file mode 100644
index 0000000000..df88615e63
--- /dev/null
+++ b/common/mock/fpsensor_crypto_mock.c
@@ -0,0 +1,64 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file fpsensor_crypto_mock.c
+ * @brief Mock fpsensor_crypto library
+ */
+#include "assert.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "fpsensor_utils.h"
+#include "mock/fpsensor_crypto_mock.h"
+#include "sha256.h"
+
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+
+#ifndef TEST_BUILD
+#error "Mocks should only be in the test build."
+#endif
+
+struct mock_ctrl_fpsensor_crypto mock_ctrl_fpsensor_crypto =
+	MOCK_CTRL_DEFAULT_FPSENSOR_CRYPTO;
+
+#define MESSAGE_ZERO_IDX 0
+#define MESSAGE_FF_IDX 1
+typedef uint8_t key_message_pair[FP_POSITIVE_MATCH_SECRET_BYTES];
+
+key_message_pair fake_fpsensor_crypto[] = {
+	{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+	{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+};
+
+BUILD_ASSERT(sizeof(key_message_pair) == FP_POSITIVE_MATCH_SECRET_BYTES);
+
+/* Mock compute_hmac_sha256 for unit or fuzz tests. */
+void compute_hmac_sha256(uint8_t *output, const uint8_t *key, const int key_len,
+			 const uint8_t *message, const int message_len)
+{
+	switch (mock_ctrl_fpsensor_crypto.output_type) {
+	case MOCK_CTRL_FPSENSOR_CRYPTO_SHA256_TYPE_REAL:
+		hmac_SHA256(output, key, key_len, message, message_len);
+		break;
+	case MOCK_CTRL_FPSENSOR_CRYPTO_SHA256_TYPE_ZEROS:
+		memcpy(output, fake_fpsensor_crypto[MESSAGE_ZERO_IDX],
+		       FP_POSITIVE_MATCH_SECRET_BYTES);
+		break;
+	case MOCK_CTRL_FPSENSOR_CRYPTO_SHA256_TYPE_FF:
+		memcpy(output, fake_fpsensor_crypto[MESSAGE_FF_IDX],
+		       FP_POSITIVE_MATCH_SECRET_BYTES);
+		break;
+	default:
+		assert(0);
+		break;
+	};
+}
diff --git a/common/mock/fpsensor_detect_mock.c b/common/mock/fpsensor_detect_mock.c
index af1d7f5103..928c2fe6ec 100644
--- a/common/mock/fpsensor_detect_mock.c
+++ b/common/mock/fpsensor_detect_mock.c
@@ -1,19 +1,28 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "mock/fpsensor_detect_mock.h"
 
+#ifndef TEST_BUILD
+#error "Mocks should only be in the test build."
+#endif
+
 struct mock_ctrl_fpsensor_detect mock_ctrl_fpsensor_detect =
 	MOCK_CTRL_DEFAULT_FPSENSOR_DETECT;
 
-enum fp_sensor_type get_fp_sensor_type(void)
+enum fp_sensor_type fpsensor_detect_get_type(void)
 {
-	return mock_ctrl_fpsensor_detect.get_fp_sensor_type_return;
+	return mock_ctrl_fpsensor_detect.fpsensor_detect_get_type_return;
 }
 
 enum fp_transport_type get_fp_transport_type(void)
 {
 	return mock_ctrl_fpsensor_detect.get_fp_transport_type_return;
 }
+
+enum fp_sensor_spi_select fpsensor_detect_get_spi_select(void)
+{
+	return mock_ctrl_fpsensor_detect.get_fp_sensor_spi_select_return;
+}
diff --git a/common/mock/fpsensor_mock.c b/common/mock/fpsensor_mock.c
new file mode 100644
index 0000000000..8540d30f1c
--- /dev/null
+++ b/common/mock/fpsensor_mock.c
@@ -0,0 +1,86 @@
+/* Copyright 2019 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ * @brief Mock fpsensor private driver
+ */
+
+#include "common.h"
+#include "fpsensor.h"
+#include "mock/fpsensor_mock.h"
+
+#include <stdlib.h>
+
+#ifndef TEST_BUILD
+#error "Mocks should only be in the test build."
+#endif
+
+struct mock_ctrl_fp_sensor mock_ctrl_fp_sensor = MOCK_CTRL_DEFAULT_FP_SENSOR;
+
+int fp_sensor_init(void)
+{
+	return mock_ctrl_fp_sensor.fp_sensor_init_return;
+}
+
+int fp_sensor_deinit(void)
+{
+	return mock_ctrl_fp_sensor.fp_sensor_deinit_return;
+}
+
+int fp_sensor_get_info(struct ec_response_fp_info *resp)
+{
+	resp->version = 0;
+	return mock_ctrl_fp_sensor.fp_sensor_get_info_return;
+}
+
+void fp_sensor_low_power(void)
+{
+}
+
+void fp_sensor_configure_detect(void)
+{
+}
+
+enum finger_state fp_sensor_finger_status(void)
+{
+	return mock_ctrl_fp_sensor.fp_sensor_finger_status_return;
+}
+
+int fp_sensor_acquire_image(uint8_t *image_data)
+{
+	return mock_ctrl_fp_sensor.fp_sensor_acquire_image_return;
+}
+
+int fp_sensor_acquire_image_with_mode(uint8_t *image_data, int mode)
+{
+	return mock_ctrl_fp_sensor.fp_sensor_acquire_image_with_mode_return;
+}
+
+int fp_finger_match(void *templ, uint32_t templ_count, uint8_t *image,
+		    int32_t *match_index, uint32_t *update_bitmap)
+{
+	return mock_ctrl_fp_sensor.fp_finger_match_return;
+}
+
+int fp_enrollment_begin(void)
+{
+	return mock_ctrl_fp_sensor.fp_enrollment_begin_return;
+}
+
+int fp_enrollment_finish(void *templ)
+{
+	return mock_ctrl_fp_sensor.fp_enrollment_finish_return;
+}
+
+int fp_finger_enroll(uint8_t *image, int *completion)
+{
+	return mock_ctrl_fp_sensor.fp_finger_enroll_return;
+}
+
+int fp_maintenance(void)
+{
+	return mock_ctrl_fp_sensor.fp_maintenance_return;
+}
diff --git a/common/mock/fpsensor_state_mock.c b/common/mock/fpsensor_state_mock.c
index 629b9a90a6..56b1fa23e7 100644
--- a/common/mock/fpsensor_state_mock.c
+++ b/common/mock/fpsensor_state_mock.c
@@ -1,15 +1,20 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <stddef.h>
-#include <string.h>
-
 #include "common.h"
 #include "ec_commands.h"
+#include "fpsensor_driver.h"
 #include "test_util.h"
 
+#include <stddef.h>
+#include <string.h>
+
+#ifndef TEST_BUILD
+#error "Mocks should only be in the test build."
+#endif
+
 const uint8_t default_fake_tpm_seed[] = {
 	0xd9, 0x71, 0xaf, 0xc4, 0xcd, 0x36, 0xe3, 0x60, 0xf8, 0x5a, 0xa0,
 	0xa6, 0x2c, 0xb3, 0xf5, 0xe2, 0xeb, 0xb9, 0xd8, 0x2f, 0xb5, 0x78,
@@ -17,6 +22,38 @@ const uint8_t default_fake_tpm_seed[] = {
 };
 BUILD_ASSERT(sizeof(default_fake_tpm_seed) == FP_CONTEXT_TPM_BYTES);
 
+const uint8_t default_fake_fp_positive_match_salt
+	[FP_MAX_FINGER_COUNT][FP_POSITIVE_MATCH_SALT_BYTES] = {
+		{ 0x04, 0x1f, 0x5a, 0xac, 0x5f, 0x79, 0x10, 0xaf, 0x04, 0x1d,
+		  0x46, 0x3a, 0x5f, 0x08, 0xee, 0xcb },
+		{ 0x04, 0x1f, 0x5a, 0xac, 0x5f, 0x79, 0x10, 0xaf, 0x04, 0x1d,
+		  0x46, 0x3a, 0x5f, 0x08, 0xee, 0xcb },
+		{ 0x04, 0x1f, 0x5a, 0xac, 0x5f, 0x79, 0x10, 0xaf, 0x04, 0x1d,
+		  0x46, 0x3a, 0x5f, 0x08, 0xee, 0xcb },
+		{ 0x04, 0x1f, 0x5a, 0xac, 0x5f, 0x79, 0x10, 0xaf, 0x04, 0x1d,
+		  0x46, 0x3a, 0x5f, 0x08, 0xee, 0xcb },
+		{ 0x04, 0x1f, 0x5a, 0xac, 0x5f, 0x79, 0x10, 0xaf, 0x04, 0x1d,
+		  0x46, 0x3a, 0x5f, 0x08, 0xee, 0xcb }
+	};
+BUILD_ASSERT(sizeof(default_fake_fp_positive_match_salt) ==
+	     FP_MAX_FINGER_COUNT * FP_POSITIVE_MATCH_SALT_BYTES);
+
+const uint8_t trivial_fp_positive_match_salt
+	[FP_MAX_FINGER_COUNT][FP_POSITIVE_MATCH_SALT_BYTES] = {
+		{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		  0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+		{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		  0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+		{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		  0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+		{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		  0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+		{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		  0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }
+	};
+BUILD_ASSERT(sizeof(trivial_fp_positive_match_salt) ==
+	     FP_MAX_FINGER_COUNT * FP_POSITIVE_MATCH_SALT_BYTES);
+
 int fpsensor_state_mock_set_tpm_seed(
 	const uint8_t tpm_seed[FP_CONTEXT_TPM_BYTES])
 {
diff --git a/common/mock/mkbp_events_mock.c b/common/mock/mkbp_events_mock.c
index fdab664c39..559cb1494d 100644
--- a/common/mock/mkbp_events_mock.c
+++ b/common/mock/mkbp_events_mock.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,12 +8,16 @@
  * @brief Mock event handling for MKBP keyboard protocol
  */
 
-#include <stdint.h>
-
 #include "common.h"
 #include "mock/mkbp_events_mock.h"
 
-struct mock_ctrl_mkbp_events mock_ctrl_mkbp_events = \
+#include <stdint.h>
+
+#ifndef TEST_BUILD
+#error "Mocks should only be in the test build."
+#endif
+
+struct mock_ctrl_mkbp_events mock_ctrl_mkbp_events =
 	MOCK_CTRL_DEFAULT_MKBP_EVENTS;
 
 int mkbp_send_event(uint8_t event_type)
diff --git a/common/mock/rollback_latest_mock.c b/common/mock/rollback_latest_mock.c
new file mode 100644
index 0000000000..b3433246d7
--- /dev/null
+++ b/common/mock/rollback_latest_mock.c
@@ -0,0 +1,61 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ * @brief Mock rollback block library
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "mock/rollback_latest_mock.h"
+#include "rollback_private.h"
+#include "util.h"
+
+#include <string.h>
+
+#ifndef TEST_BUILD
+#error "Mocks should only be in the test build."
+#endif
+
+struct mock_ctrl_latest_rollback mock_ctrl_latest_rollback =
+	MOCK_CTRL_DEFAULT_LATEST_ROLLBACK;
+
+const struct rollback_data fake_latest_rollback_zeros = {
+	.cookie = 0,
+	.secret = {
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,},
+
+	.id = 0,
+	.rollback_min_version = 0,
+};
+
+const struct rollback_data fake_latest_rollback_real = {
+	.cookie = 9,
+	.secret = {
+	0xcf, 0xe3, 0x23, 0x76, 0x35, 0x04, 0xc2, 0x0f, 0x0d, 0xb6, 0x02,
+	0xa9, 0x68, 0xba, 0x2a, 0x61, 0x86, 0x2a, 0x85, 0xd1, 0xca, 0x09,
+	0x54, 0x8a, 0x6b, 0xe2, 0xe3, 0x38, 0xde, 0x5d, 0x59, 0x14,},
+	.id = 2,
+	.rollback_min_version = 1,
+};
+
+/* Mock the rollback for unit or fuzz tests. */
+int get_latest_rollback(struct rollback_data *data)
+{
+	switch (mock_ctrl_latest_rollback.output_type) {
+	case GET_LATEST_ROLLBACK_FAIL:
+		return -5;
+	case GET_LATEST_ROLLBACK_ZEROS:
+		*data = fake_latest_rollback_zeros;
+		break;
+	case GET_LATEST_ROLLBACK_REAL:
+		*data = fake_latest_rollback_real;
+		break;
+	}
+	return EC_SUCCESS;
+}
diff --git a/common/mock/rollback_mock.c b/common/mock/rollback_mock.c
index 84e9c4aa43..5b1be063c6 100644
--- a/common/mock/rollback_mock.c
+++ b/common/mock/rollback_mock.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,27 +8,30 @@
  * @brief Mock rollback block library
  */
 
-#include <stdint.h>
-#include <string.h>
-
 #include "common.h"
 #include "compile_time_macros.h"
-#include "util.h"
 #include "mock/rollback_mock.h"
+#include "util.h"
+
+#include <stdint.h>
+#include <string.h>
+
+#ifndef TEST_BUILD
+#error "Mocks should only be in the test build."
+#endif
 
 struct mock_ctrl_rollback mock_ctrl_rollback = MOCK_CTRL_DEFAULT_ROLLBACK;
 
 static const uint8_t fake_rollback_secret[] = {
-	0xcf, 0xe3, 0x23, 0x76, 0x35, 0x04, 0xc2, 0x0f,
-	0x0d, 0xb6, 0x02, 0xa9, 0x68, 0xba, 0x2a, 0x61,
-	0x86, 0x2a, 0x85, 0xd1, 0xca, 0x09, 0x54, 0x8a,
-	0x6b, 0xe2, 0xe3, 0x38, 0xde, 0x5d, 0x59, 0x14,
+	0xcf, 0xe3, 0x23, 0x76, 0x35, 0x04, 0xc2, 0x0f, 0x0d, 0xb6, 0x02,
+	0xa9, 0x68, 0xba, 0x2a, 0x61, 0x86, 0x2a, 0x85, 0xd1, 0xca, 0x09,
+	0x54, 0x8a, 0x6b, 0xe2, 0xe3, 0x38, 0xde, 0x5d, 0x59, 0x14,
 };
 
 BUILD_ASSERT(sizeof(fake_rollback_secret) == CONFIG_ROLLBACK_SECRET_SIZE);
 
 /* Mock the rollback for unit or fuzz tests. */
-int rollback_get_secret(uint8_t *secret)
+enum ec_error_list rollback_get_secret(uint8_t *secret)
 {
 	if (mock_ctrl_rollback.get_secret_fail)
 		return EC_ERROR_UNKNOWN;
diff --git a/common/mock/tcpc_mock.c b/common/mock/tcpc_mock.c
index 457868c96a..31dda7eba1 100644
--- a/common/mock/tcpc_mock.c
+++ b/common/mock/tcpc_mock.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,6 +17,10 @@
 #define cprints(format, args...)
 #endif
 
+#ifndef TEST_BUILD
+#error "Mocks should only be in the test build."
+#endif
+
 /* Public API for controlling/inspecting this mock */
 struct mock_tcpc_ctrl mock_tcpc;
 
@@ -121,8 +125,7 @@ static int mock_set_msg_header(int port, int power_role, int data_role)
 		return EC_SUCCESS;
 
 	ccprints("[TCPC] Setting TCPM-side header to %s %s",
-		 from_pd_power_role(power_role),
-		 from_pd_data_role(data_role));
+		 from_pd_power_role(power_role), from_pd_data_role(data_role));
 
 	return EC_SUCCESS;
 }
@@ -137,8 +140,8 @@ static int mock_get_message_raw(int port, uint32_t *payload, int *head)
 	return EC_SUCCESS;
 }
 
-static int mock_transmit(int port, enum tcpm_transmit_type type,
-			 uint16_t header, const uint32_t *data)
+static int mock_transmit(int port, enum tcpci_msg_type type, uint16_t header,
+			 const uint32_t *data)
 {
 	return EC_SUCCESS;
 }
@@ -183,9 +186,15 @@ __maybe_unused static int mock_set_src_ctrl(int port, int enable)
 
 __maybe_unused static int mock_enter_low_power_mode(int port)
 {
+	mock_tcpc.lpm_wake_requested = false;
 	return EC_SUCCESS;
 }
 
+__maybe_unused static void mock_wake_low_power_mode(int port)
+{
+	mock_tcpc.lpm_wake_requested = true;
+}
+
 int mock_set_frs_enable(int port, int enable)
 {
 	return EC_SUCCESS;
@@ -210,12 +219,11 @@ const struct tcpm_drv mock_tcpc_driver = {
 	.drp_toggle = &mock_drp_toggle,
 #endif
 	.get_chip_info = &mock_get_chip_info,
-#ifdef CONFIG_USBC_PPC
 	.set_snk_ctrl = &mock_set_snk_ctrl,
 	.set_src_ctrl = &mock_set_src_ctrl,
-#endif
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
 	.enter_low_power_mode = &mock_enter_low_power_mode,
+	.wake_low_power_mode = &mock_wake_low_power_mode,
 #endif
 #ifdef CONFIG_USB_PD_FRS_TCPC
 	.set_frs_enable = &mock_set_frs_enable,
diff --git a/common/mock/tcpci_i2c_mock.c b/common/mock/tcpci_i2c_mock.c
index fa7268ddf4..a0e59ecc44 100644
--- a/common/mock/tcpci_i2c_mock.c
+++ b/common/mock/tcpci_i2c_mock.c
@@ -1,27 +1,36 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "mock/tcpci_i2c_mock.h"
 #include "task.h"
-#include "tcpci.h"
+#include "tcpm/tcpci.h"
 #include "test_util.h"
 #include "timer.h"
+#include "usb_pd_tcpm.h"
+
+#ifndef TEST_BUILD
+#error "Mocks should only be in the test build."
+#endif
 
 #define BUFFER_SIZE 100
 #define VERIFY_TIMEOUT (5 * SECOND)
 
 struct tcpci_reg {
-	uint8_t		offset;
-	uint8_t		size;
-	uint16_t	value;
-	const char	*name;
+	uint8_t offset;
+	uint8_t size;
+	uint16_t value;
+	const char *name;
 };
 
-#define TCPCI_REG(reg_name, reg_size)					\
-	[reg_name] = { .offset = (reg_name), .size = (reg_size),	\
-			.value = 0, .name = #reg_name, }
+#define TCPCI_REG(reg_name, reg_size) \
+	[reg_name] = {                \
+		.offset = (reg_name), \
+		.size = (reg_size),   \
+		.value = 0,           \
+		.name = #reg_name,    \
+	}
 
 static struct tcpci_reg tcpci_regs[] = {
 	TCPCI_REG(TCPC_REG_VENDOR_ID, 2),
@@ -66,97 +75,150 @@ static struct tcpci_reg tcpci_regs[] = {
 
 static uint8_t tx_buffer[BUFFER_SIZE];
 static int tx_pos = -1;
+static int tx_msg_cnt;
+static int tx_retry_cnt = -1;
 static uint8_t rx_buffer[BUFFER_SIZE];
 static int rx_pos = -1;
 
-static const char * const ctrl_msg_name[] = {
-	[0]                      = "RSVD-C0",
-	[PD_CTRL_GOOD_CRC]       = "GOODCRC",
-	[PD_CTRL_GOTO_MIN]       = "GOTOMIN",
-	[PD_CTRL_ACCEPT]         = "ACCEPT",
-	[PD_CTRL_REJECT]         = "REJECT",
-	[PD_CTRL_PING]           = "PING",
-	[PD_CTRL_PS_RDY]         = "PSRDY",
-	[PD_CTRL_GET_SOURCE_CAP] = "GSRCCAP",
-	[PD_CTRL_GET_SINK_CAP]   = "GSNKCAP",
-	[PD_CTRL_DR_SWAP]        = "DRSWAP",
-	[PD_CTRL_PR_SWAP]        = "PRSWAP",
-	[PD_CTRL_VCONN_SWAP]     = "VCONNSW",
-	[PD_CTRL_WAIT]           = "WAIT",
-	[PD_CTRL_SOFT_RESET]     = "SFT-RST",
-	[14]                     = "RSVD-C14",
-	[15]                     = "RSVD-C15",
-	[PD_CTRL_NOT_SUPPORTED]  = "NOT-SUPPORTED",
-	[PD_CTRL_GET_SOURCE_CAP_EXT] = "GSRCCAP-EXT",
-	[PD_CTRL_GET_STATUS]     = "GET-STATUS",
-	[PD_CTRL_FR_SWAP]        = "FRSWAP",
-	[PD_CTRL_GET_PPS_STATUS] = "GET-PPS-STATUS",
-	[PD_CTRL_GET_COUNTRY_CODES] = "GET-COUNTRY-CODES",
+static const char *const ctrl_msg_name[] = {
+	[0] = "C-RSVD_0",
+	[PD_CTRL_GOOD_CRC] = "C-GOODCRC",
+	[PD_CTRL_GOTO_MIN] = "C-GOTOMIN",
+	[PD_CTRL_ACCEPT] = "C-ACCEPT",
+	[PD_CTRL_REJECT] = "C-REJECT",
+	[PD_CTRL_PING] = "C-PING",
+	[PD_CTRL_PS_RDY] = "C-PSRDY",
+	[PD_CTRL_GET_SOURCE_CAP] = "C-GET_SRC_CAP",
+	[PD_CTRL_GET_SINK_CAP] = "C-GET_SNK_CAP",
+	[PD_CTRL_DR_SWAP] = "C-DR_SWAP",
+	[PD_CTRL_PR_SWAP] = "C-PR_SWAP",
+	[PD_CTRL_VCONN_SWAP] = "C-VCONN_SW",
+	[PD_CTRL_WAIT] = "C-WAIT",
+	[PD_CTRL_SOFT_RESET] = "C-SOFT-RESET",
+	[14] = "C-RSVD_14",
+	[15] = "C-RSVD_15",
+	[PD_CTRL_NOT_SUPPORTED] = "C-NOT_SUPPORTED",
+	[PD_CTRL_GET_SOURCE_CAP_EXT] = "C-GET_SRC_CAP-EXT",
+	[PD_CTRL_GET_STATUS] = "C-GET-STATUS",
+	[PD_CTRL_FR_SWAP] = "C-FR_SWAP",
+	[PD_CTRL_GET_PPS_STATUS] = "C-GET_PPS_STATUS",
+	[PD_CTRL_GET_COUNTRY_CODES] = "C-GET_COUNTRY_CODES",
+	[PD_CTRL_GET_SINK_CAP_EXT] = "C-GET_SINK_CAP_EXT",
+	[PD_CTRL_GET_SOURCE_INFO] = "C-GET_SOURCE_INFO",
+	[PD_CTRL_GET_REVISION] = "C-GET_REVISION",
+};
+
+static const char *const data_msg_name[] = {
+	[0] = "D-RSVD_0",
+	[PD_DATA_SOURCE_CAP] = "D-SRC_CAP",
+	[PD_DATA_REQUEST] = "D-REQUEST",
+	[PD_DATA_BIST] = "D-BIST",
+	[PD_DATA_SINK_CAP] = "D-SNK_CAP",
+	/* 5-14 Reserved for REV 2.0 */
+	[PD_DATA_BATTERY_STATUS] = "D-BATTERY_STATUS",
+	[PD_DATA_ALERT] = "D-ALERT",
+	[PD_DATA_GET_COUNTRY_INFO] = "D-GET_COUNTRY_CODES",
+	/* 8-14 Reserved for REV 3.0 */
+	[PD_DATA_ENTER_USB] = "D-ENTER_USB",
+	[PD_DATA_EPR_REQUEST] = "D-EPR_REQUEST",
+	[PD_DATA_EPR_MODE] = "D-EPR_MODE",
+	[PD_DATA_SOURCE_INFO] = "D-EPR_SOURCE_INFO",
+	[PD_DATA_REVISION] = "D-REVISION",
+	/* 13-14 Reserved for REV 3.0 */
+	[PD_DATA_VENDOR_DEF] = "D-VDM",
 };
 
-static const char * const data_msg_name[] = {
-	[0]                      = "RSVD-D0",
-	[PD_DATA_SOURCE_CAP]     = "SRCCAP",
-	[PD_DATA_REQUEST]        = "REQUEST",
-	[PD_DATA_BIST]           = "BIST",
-	[PD_DATA_SINK_CAP]       = "SNKCAP",
-	/* 5-14 Reserved */
-	[PD_DATA_VENDOR_DEF]     = "VDM",
+static const char *const ext_msg_name[] = {
+	[0] = "X-RSVD_0",
+	[PD_EXT_SOURCE_CAP] = "X-SRC_CAP",
+	[PD_EXT_STATUS] = "X-STATUS",
+	[PD_EXT_GET_BATTERY_CAP] = "X-GET_BATTERY_CAP",
+	[PD_EXT_GET_BATTERY_STATUS] = "X-GET_BATTERY_STATUS",
+	[PD_EXT_BATTERY_CAP] = "X-BATTERY_CAP",
+	[PD_EXT_GET_MANUFACTURER_INFO] = "X-GET_MFR_INFO",
+	[PD_EXT_MANUFACTURER_INFO] = "X-MFR_INFO",
+	[PD_EXT_SECURITY_REQUEST] = "X-SECURITY_REQ",
+	[PD_EXT_SECURITY_RESPONSE] = "X-SECURITY_RESP",
+	[PD_EXT_FIRMWARE_UPDATE_REQUEST] = "X-FW_UP_REQ",
+	[PD_EXT_FIRMWARE_UPDATE_RESPONSE] = "X-FW_UP_RESP",
+	[PD_EXT_PPS_STATUS] = "X-PPS_STATUS",
+	[PD_EXT_COUNTRY_INFO] = "X-COUNTRY_INFO",
+	[PD_EXT_COUNTRY_CODES] = "X-COUNTRY_CODES",
+	[PD_EXT_SINK_CAP] = "X-SNK_CAP",
+	[PD_EXT_CONTROL] = "X-CONTROL",
+	[PD_EXT_EPR_SOURCE_CAP] = "X-EPR_SRC_CAP",
+	[PD_EXT_EPR_SINK_CAP] = "X-EPR_SNK_CAP",
 };
 
-static const char * const rev_name[] = {
+static const char *const rev_name[] = {
 	[PD_REV10] = "1.0",
 	[PD_REV20] = "2.0",
 	[PD_REV30] = "3.0",
 	[3] = "RSVD",
 };
 
-static const char * const drole_name[] = {
+static const char *const drole_name[] = {
 	[PD_ROLE_UFP] = "UFP",
 	[PD_ROLE_DFP] = "DFP",
 };
 
-static const char * const prole_name[] = {
+static const char *const prole_name[] = {
 	[PD_ROLE_SINK] = "SNK",
 	[PD_ROLE_SOURCE] = "SRC",
 };
 
 static void print_header(const char *prefix, uint16_t header)
 {
-	int type  = PD_HEADER_TYPE(header);
+	int type = PD_HEADER_TYPE(header);
 	int drole = PD_HEADER_DROLE(header);
-	int rev   = PD_HEADER_REV(header);
+	int rev = PD_HEADER_REV(header);
 	int prole = PD_HEADER_PROLE(header);
-	int id    = PD_HEADER_ID(header);
-	int cnt   = PD_HEADER_CNT(header);
-	int ext   = PD_HEADER_EXT(header);
-	const char *name = cnt ? data_msg_name[type] : ctrl_msg_name[type];
-
-	ccprints("%s header=0x%x [%s %s %s %s id=%d cnt=%d ext=%d]",
-		 prefix, header,
-		 name, drole_name[drole], rev_name[rev], prole_name[prole],
-		 id, cnt, ext);
+	int id = PD_HEADER_ID(header);
+	int cnt = PD_HEADER_CNT(header);
+	int ext = PD_HEADER_EXT(header);
+	const char *name = ext ? ext_msg_name[type] :
+			   cnt ? data_msg_name[type] :
+				 ctrl_msg_name[type];
+
+	ccprints("%s header=0x%x [%s %s %s %s id=%d cnt=%d ext=%d]", prefix,
+		 header, name, drole_name[drole], rev_name[rev],
+		 prole_name[prole], id, cnt, ext);
 }
 
-static int verify_transmit(enum tcpm_transmit_type want_tx_type,
-			   int want_tx_retry,
+static bool dead_battery(void)
+{
+	return false;
+}
+
+static bool debug_accessory_indicator_supported(void)
+{
+	return true;
+}
+
+static int verify_transmit(enum tcpci_msg_type want_tx_type, int want_tx_retry,
 			   enum pd_ctrl_msg_type want_ctrl_msg,
-			   enum pd_data_msg_type want_data_msg,
-			   int timeout)
+			   enum pd_data_msg_type want_data_msg, int timeout)
 {
 	uint64_t end_time = get_time().val + timeout;
 
+	/*
+	 * Check that nothing was already transmitted. This ensures that all
+	 * transmits are checked, and the test stays in sync with the code
+	 * being tested.
+	 */
 	TEST_EQ(tcpci_regs[TCPC_REG_TRANSMIT].value, 0, "%d");
+
+	/* Now wait for the expected message to be transmitted. */
 	while (get_time().val < end_time) {
 		if (tcpci_regs[TCPC_REG_TRANSMIT].value != 0) {
 			int tx_type = TCPC_REG_TRANSMIT_TYPE(
 				tcpci_regs[TCPC_REG_TRANSMIT].value);
 			int tx_retry = TCPC_REG_TRANSMIT_RETRY(
 				tcpci_regs[TCPC_REG_TRANSMIT].value);
-			uint16_t header = UINT16_FROM_BYTE_ARRAY_LE(
-						tx_buffer, 1);
-			int pd_type  = PD_HEADER_TYPE(header);
-			int pd_cnt   = PD_HEADER_CNT(header);
+			uint16_t header =
+				UINT16_FROM_BYTE_ARRAY_LE(tx_buffer, 1);
+			int pd_type = PD_HEADER_TYPE(header);
+			int pd_cnt = PD_HEADER_CNT(header);
 
 			TEST_EQ(tx_type, want_tx_type, "%d");
 			if (want_tx_retry >= 0)
@@ -170,6 +232,7 @@ static int verify_transmit(enum tcpm_transmit_type want_tx_type,
 				TEST_EQ(pd_type, want_data_msg, "0x%x");
 				TEST_GE(pd_cnt, 1, "%d");
 			}
+
 			tcpci_regs[TCPC_REG_TRANSMIT].value = 0;
 			return EC_SUCCESS;
 		}
@@ -179,28 +242,123 @@ static int verify_transmit(enum tcpm_transmit_type want_tx_type,
 	return EC_ERROR_UNKNOWN;
 }
 
-int verify_tcpci_transmit(enum tcpm_transmit_type tx_type,
+int verify_tcpci_transmit(enum tcpci_msg_type tx_type,
 			  enum pd_ctrl_msg_type ctrl_msg,
 			  enum pd_data_msg_type data_msg)
 {
 	return verify_transmit(tx_type, -1, ctrl_msg, data_msg, VERIFY_TIMEOUT);
 }
 
-int verify_tcpci_tx_timeout(enum tcpm_transmit_type tx_type,
+int verify_tcpci_tx_timeout(enum tcpci_msg_type tx_type,
 			    enum pd_ctrl_msg_type ctrl_msg,
-			    enum pd_data_msg_type data_msg,
-			    int timeout)
+			    enum pd_data_msg_type data_msg, int timeout)
 {
 	return verify_transmit(tx_type, -1, ctrl_msg, data_msg, timeout);
 }
 
-int verify_tcpci_tx_retry_count(enum tcpm_transmit_type tx_type,
-				int retry_count)
+int verify_tcpci_tx_retry_count(enum tcpci_msg_type tx_type,
+				enum pd_ctrl_msg_type ctrl_msg,
+				enum pd_data_msg_type data_msg, int retry_count)
 {
-	return verify_transmit(tx_type, retry_count, 0, 0, VERIFY_TIMEOUT);
+	return verify_transmit(tx_type, retry_count, ctrl_msg, data_msg,
+			       VERIFY_TIMEOUT);
+}
+
+int verify_tcpci_tx_with_data(enum tcpci_msg_type tx_type,
+			      enum pd_data_msg_type data_msg, uint8_t *data,
+			      int data_bytes, int *msg_len, int timeout)
+{
+	int rv;
+
+	if (timeout <= 0)
+		timeout = VERIFY_TIMEOUT;
+
+	rv = verify_transmit(tx_type, -1, 0, data_msg, timeout);
+	if (!rv) {
+		TEST_NE(data, NULL, "%p");
+		TEST_GE(data_bytes, tx_msg_cnt, "%d");
+		memcpy(data, tx_buffer, tx_msg_cnt);
+		if (msg_len)
+			*msg_len = tx_msg_cnt;
+	}
+	return rv;
 }
 
-void mock_tcpci_receive(enum pd_msg_type sop, uint16_t header,
+int verify_tcpci_possible_tx(struct possible_tx possible[], int possible_cnt,
+			     int *found_index, uint8_t *data, int data_bytes,
+			     int *msg_len, int timeout)
+{
+	bool assert_on_timeout = true;
+	uint64_t end_time;
+
+	*found_index = -1;
+
+	if (timeout <= 0) {
+		timeout = VERIFY_TIMEOUT;
+		assert_on_timeout = false;
+	}
+	end_time = get_time().val + timeout;
+
+	/*
+	 * Check that nothing was already transmitted. This ensures that all
+	 * transmits are checked, and the test stays in sync with the code
+	 * being tested.
+	 */
+	TEST_EQ(tcpci_regs[TCPC_REG_TRANSMIT].value, 0, "%d");
+
+	/* Now wait for the expected message to be transmitted. */
+	while (get_time().val < end_time) {
+		if (tcpci_regs[TCPC_REG_TRANSMIT].value != 0) {
+			int i;
+			int tx_type = TCPC_REG_TRANSMIT_TYPE(
+				tcpci_regs[TCPC_REG_TRANSMIT].value);
+			uint16_t header =
+				UINT16_FROM_BYTE_ARRAY_LE(tx_buffer, 1);
+			int pd_type = PD_HEADER_TYPE(header);
+			int pd_cnt = PD_HEADER_CNT(header);
+
+			for (i = 0; i < possible_cnt; ++i) {
+				int want_tx_type = possible[i].tx_type;
+				int want_ctrl_msg = possible[i].ctrl_msg;
+				int want_data_msg = possible[i].data_msg;
+
+				if (tx_type != want_tx_type)
+					continue;
+
+				if (want_ctrl_msg != 0) {
+					if (pd_type != want_ctrl_msg ||
+					    pd_cnt != 0)
+						continue;
+				}
+				if (want_data_msg != 0) {
+					if (pd_type != want_data_msg ||
+					    pd_cnt == 0)
+						continue;
+
+					if (data != NULL) {
+						TEST_GE(data_bytes, tx_msg_cnt,
+							"%d");
+						memcpy(data, tx_buffer,
+						       tx_msg_cnt);
+					}
+					if (msg_len != NULL)
+						*msg_len = tx_msg_cnt;
+				}
+				*found_index = i;
+				tcpci_regs[TCPC_REG_TRANSMIT].value = 0;
+				return EC_SUCCESS;
+			}
+			return EC_ERROR_UNKNOWN;
+		}
+		task_wait_event(5 * MSEC);
+	}
+	if (assert_on_timeout)
+		TEST_ASSERT(0);
+
+	return EC_ERROR_TIMEOUT;
+}
+
+void mock_tcpci_receive(enum tcpci_msg_type sop, uint16_t header,
 			uint32_t *payload)
 {
 	int i;
@@ -217,21 +375,112 @@ void mock_tcpci_receive(enum pd_msg_type sop, uint16_t header,
 
 	for (i = 4; i < rx_buffer[0]; i += 4) {
 		rx_buffer[i] = *payload & 0xFF;
-		rx_buffer[i+1] = (*payload >> 8) & 0xFF;
-		rx_buffer[i+2] = (*payload >> 16) & 0xFF;
-		rx_buffer[i+3] = (*payload >> 24) & 0xFF;
+		rx_buffer[i + 1] = (*payload >> 8) & 0xFF;
+		rx_buffer[i + 2] = (*payload >> 16) & 0xFF;
+		rx_buffer[i + 3] = (*payload >> 24) & 0xFF;
 		payload++;
 	}
 
 	rx_pos = 0;
 }
 
-void mock_tcpci_reset(void)
+/*****************************************************************************
+ * TCPCI register reset values
+ *
+ * These values are from USB Type-C Port Controller Interface Specification
+ * Revision 2.0, Version 1.2,
+ */
+static void tcpci_reset_register_masks(void)
+{
+	/*
+	 * Using table 4-1 for default mask values
+	 */
+	tcpci_regs[TCPC_REG_ALERT_MASK].value = 0x7FFF;
+	tcpci_regs[TCPC_REG_POWER_STATUS_MASK].value = 0xFF;
+	tcpci_regs[TCPC_REG_FAULT_STATUS_MASK].value = 0xFF;
+	tcpci_regs[TCPC_REG_EXT_STATUS_MASK].value = 0x01;
+	tcpci_regs[TCPC_REG_ALERT_EXTENDED_MASK].value = 0x07;
+}
+
+static void tcpci_reset_register_defaults(void)
 {
 	int i;
 
+	/* Default all registers to 0 and then overwrite if they are not */
 	for (i = 0; i < ARRAY_SIZE(tcpci_regs); i++)
 		tcpci_regs[i].value = 0;
+
+	/* Type-C Release 1,3 */
+	tcpci_regs[TCPC_REG_TC_REV].value = 0x0013;
+	/* PD Revision 3.0 Version 1.2 */
+	tcpci_regs[TCPC_REG_PD_REV].value = 0x3012;
+	/* PD Interface Revision 2.0, Version 1.1 */
+	tcpci_regs[TCPC_REG_PD_INT_REV].value = 0x2011;
+
+	tcpci_reset_register_masks();
+
+	tcpci_regs[TCPC_REG_CONFIG_STD_OUTPUT].value =
+		TCPC_REG_CONFIG_STD_OUTPUT_AUDIO_CONN_N |
+		TCPC_REG_CONFIG_STD_OUTPUT_DBG_ACC_CONN_N;
+
+	tcpci_regs[TCPC_REG_POWER_CTRL].value =
+		TCPC_REG_POWER_CTRL_VOLT_ALARM_DIS |
+		TCPC_REG_POWER_CTRL_VBUS_VOL_MONITOR_DIS;
+
+	tcpci_regs[TCPC_REG_FAULT_STATUS].value =
+		TCPC_REG_FAULT_STATUS_ALL_REGS_RESET;
+
+	tcpci_regs[TCPC_REG_DEV_CAP_1].value =
+		TCPC_REG_DEV_CAP_1_SOURCE_VBUS | TCPC_REG_DEV_CAP_1_SINK_VBUS |
+		TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP |
+		TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_3P0_1P5_DEF;
+
+	/*
+	 * Using table 4-17 to get the default Role Control and
+	 * Message Header Info register values.
+	 */
+	switch (mock_tcpci_get_reg(TCPC_REG_DEV_CAP_1) &
+		TCPC_REG_DEV_CAP_1_PWRROLE_MASK) {
+	case TCPC_REG_DEV_CAP_1_PWRROLE_SRC_OR_SNK:
+	case TCPC_REG_DEV_CAP_1_PWRROLE_SNK:
+	case TCPC_REG_DEV_CAP_1_PWRROLE_SNK_ACC:
+		tcpci_regs[TCPC_REG_ROLE_CTRL].value = 0x0A;
+		tcpci_regs[TCPC_REG_MSG_HDR_INFO].value = 0x04;
+		break;
+
+	case TCPC_REG_DEV_CAP_1_PWRROLE_DRP:
+		if (dead_battery())
+			tcpci_regs[TCPC_REG_ROLE_CTRL].value = 0x0A;
+		else if (debug_accessory_indicator_supported())
+			tcpci_regs[TCPC_REG_ROLE_CTRL].value = 0x4A;
+		else
+			tcpci_regs[TCPC_REG_ROLE_CTRL].value = 0x0F;
+		tcpci_regs[TCPC_REG_MSG_HDR_INFO].value = 0x04;
+		break;
+
+	case TCPC_REG_DEV_CAP_1_PWRROLE_SRC:
+		if (!dead_battery())
+			tcpci_regs[TCPC_REG_ROLE_CTRL].value = 0x05;
+		tcpci_regs[TCPC_REG_MSG_HDR_INFO].value = 0x0D;
+		break;
+
+	case TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP_ADPT_CBL:
+	case TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP:
+		if (dead_battery())
+			tcpci_regs[TCPC_REG_ROLE_CTRL].value = 0x0A;
+		else if (debug_accessory_indicator_supported())
+			tcpci_regs[TCPC_REG_ROLE_CTRL].value = 0x4A;
+		else
+			tcpci_regs[TCPC_REG_ROLE_CTRL].value = 0x0F;
+		tcpci_regs[TCPC_REG_MSG_HDR_INFO].value = 0x04;
+		break;
+	}
+}
+/*****************************************************************************/
+
+void mock_tcpci_reset(void)
+{
+	tcpci_reset_register_defaults();
 }
 
 void mock_tcpci_set_reg(int reg_offset, uint16_t value)
@@ -239,7 +488,27 @@ void mock_tcpci_set_reg(int reg_offset, uint16_t value)
 	struct tcpci_reg *reg = tcpci_regs + reg_offset;
 
 	reg->value = value;
-	ccprints("TCPCI mock set %s = 0x%x",  reg->name, reg->value);
+	ccprints("TCPCI mock set %s = 0x%x", reg->name, reg->value);
+}
+
+void mock_tcpci_set_reg_bits(int reg_offset, uint16_t mask)
+{
+	struct tcpci_reg *reg = tcpci_regs + reg_offset;
+	uint16_t old_value = reg->value;
+
+	reg->value |= mask;
+	ccprints("TCPCI mock set bits %s (mask=0x%x) = 0x%x -> 0x%x", reg->name,
+		 mask, old_value, reg->value);
+}
+
+void mock_tcpci_clr_reg_bits(int reg_offset, uint16_t mask)
+{
+	struct tcpci_reg *reg = tcpci_regs + reg_offset;
+	uint16_t old_value = reg->value;
+
+	reg->value &= ~mask;
+	ccprints("TCPCI mock clr bits %s (mask=0x%x) = 0x%x -> 0x%x", reg->name,
+		 mask, old_value, reg->value);
 }
 
 uint16_t mock_tcpci_get_reg(int reg_offset)
@@ -247,9 +516,8 @@ uint16_t mock_tcpci_get_reg(int reg_offset)
 	return tcpci_regs[reg_offset].value;
 }
 
-int tcpci_i2c_xfer(int port, uint16_t slave_addr_flags,
-		const uint8_t *out, int out_size,
-		uint8_t *in, int in_size, int flags)
+int tcpci_i2c_xfer(int port, uint16_t addr_flags, const uint8_t *out,
+		   int out_size, uint8_t *in, int in_size, int flags)
 {
 	struct tcpci_reg *reg;
 
@@ -257,8 +525,8 @@ int tcpci_i2c_xfer(int port, uint16_t slave_addr_flags,
 		ccprints("ERROR: wrong I2C port %d", port);
 		return EC_ERROR_UNKNOWN;
 	}
-	if (slave_addr_flags != MOCK_TCPCI_I2C_ADDR_FLAGS) {
-		ccprints("ERROR: wrong I2C address 0x%x", slave_addr_flags);
+	if (addr_flags != MOCK_TCPCI_I2C_ADDR_FLAGS) {
+		ccprints("ERROR: wrong I2C address 0x%x", addr_flags);
 		return EC_ERROR_UNKNOWN;
 	}
 
@@ -268,10 +536,10 @@ int tcpci_i2c_xfer(int port, uint16_t slave_addr_flags,
 			return EC_ERROR_UNKNOWN;
 		}
 		memcpy(in, rx_buffer + rx_pos, in_size);
-		rx_pos	+= in_size;
+		rx_pos += in_size;
 		if (rx_pos == rx_buffer[0] + 1) {
-			print_header("RX", UINT16_FROM_BYTE_ARRAY_LE(
-						rx_buffer, 2));
+			print_header("RX",
+				     UINT16_FROM_BYTE_ARRAY_LE(rx_buffer, 2));
 			rx_pos = -1;
 		}
 		return EC_SUCCESS;
@@ -288,10 +556,12 @@ int tcpci_i2c_xfer(int port, uint16_t slave_addr_flags,
 		}
 		memcpy(tx_buffer + tx_pos, out, out_size);
 		tx_pos += out_size;
+		tx_msg_cnt = tx_pos;
 		if (tx_pos > 0 && tx_pos == tx_buffer[0] + 1) {
-			print_header("TX", UINT16_FROM_BYTE_ARRAY_LE(
-						tx_buffer, 1));
+			print_header("TX",
+				     UINT16_FROM_BYTE_ARRAY_LE(tx_buffer, 1));
 			tx_pos = -1;
+			tx_retry_cnt = -1;
 		}
 		return EC_SUCCESS;
 	}
@@ -306,6 +576,7 @@ int tcpci_i2c_xfer(int port, uint16_t slave_addr_flags,
 			return EC_ERROR_UNKNOWN;
 		}
 		tx_pos = 0;
+		tx_msg_cnt = 0;
 		if (out_size != 1) {
 			ccprints("ERROR: TCPC_REG_TX_BUFFER out_size != 1");
 			return EC_ERROR_UNKNOWN;
@@ -349,8 +620,7 @@ int tcpci_i2c_xfer(int port, uint16_t slave_addr_flags,
 		else if (reg->size == 2)
 			value = out[1] + (out[2] << 8);
 		ccprints("%s TCPCI write %s = 0x%x",
-			 task_get_name(task_get_current()),
-			 reg->name, value);
+			 task_get_name(task_get_current()), reg->name, value);
 		if (reg->offset == TCPC_REG_ALERT)
 			reg->value &= ~value;
 		else
@@ -359,3 +629,369 @@ int tcpci_i2c_xfer(int port, uint16_t slave_addr_flags,
 	return EC_SUCCESS;
 }
 DECLARE_TEST_I2C_XFER(tcpci_i2c_xfer);
+
+void tcpci_register_dump(void)
+{
+	int reg;
+	int cc1, cc2;
+
+	ccprints("********* TCPCI Register Dump ***********");
+	reg = mock_tcpci_get_reg(TCPC_REG_ALERT);
+	ccprints("TCPC_REG_ALERT        = 0x%08X", reg);
+	if (reg) {
+		if (reg & BIT(0))
+			ccprints("\t0001: CC Status");
+		if (reg & BIT(1))
+			ccprints("\t0002: Power Status");
+		if (reg & BIT(2))
+			ccprints("\t0004: Received SOP* Message Status");
+		if (reg & BIT(3))
+			ccprints("\t0008: Received Hard Reset");
+		if (reg & BIT(4))
+			ccprints("\t0010: Transmit SOP* Message Failed");
+		if (reg & BIT(5))
+			ccprints("\t0020: Transmit SOP* Message Discarded");
+		if (reg & BIT(6))
+			ccprints("\t0040: Transmit SOP* Message Successful");
+		if (reg & BIT(7))
+			ccprints("\t0080: Vbus Voltage Alarm Hi");
+		if (reg & BIT(8))
+			ccprints("\t0100: Vbus Voltage Alarm Lo");
+		if (reg & BIT(9))
+			ccprints("\t0200: Fault");
+		if (reg & BIT(10))
+			ccprints("\t0400: Rx Buffer Overflow");
+		if (reg & BIT(11))
+			ccprints("\t0800: Vbus Sink Disconnect Detected");
+		if (reg & BIT(12))
+			ccprints("\t1000: Beginning SOP* Message Status");
+		if (reg & BIT(13))
+			ccprints("\t2000: Extended Status");
+		if (reg & BIT(14))
+			ccprints("\t4000: Alert Extended");
+		if (reg & BIT(15))
+			ccprints("\t8000: Vendor Defined Alert");
+	}
+
+	reg = mock_tcpci_get_reg(TCPC_REG_TCPC_CTRL);
+	ccprints("TCPC_REG_TCPC_CTRL    = 0x%04X", reg);
+	if (reg & BIT(0))
+		ccprints("\t01: Plug Orientation FLIP");
+	if (reg & BIT(1))
+		ccprints("\t02: BIST Test Mode");
+	if (reg & (BIT(2) | BIT(3))) {
+		switch ((reg >> 2) & 3) {
+		case 2:
+			ccprints("\t08: Enable Clock Stretching");
+			break;
+		case 3:
+			ccprints("\t0C: Enable Clock Stretching if !Alert");
+			break;
+		}
+	}
+	if (reg & BIT(4))
+		ccprints("\t10: Debug Accessory controlled by TCPM");
+	if (reg & BIT(5))
+		ccprints("\t20: Watchdog Timer enabled");
+	if (reg & BIT(6))
+		ccprints("\t40: Looking4Connection Alert enabled");
+	if (reg & BIT(7))
+		ccprints("\t80: SMBus PEC enabled");
+
+	reg = mock_tcpci_get_reg(TCPC_REG_ROLE_CTRL);
+	ccprints("TCPC_REG_ROLE_CTRL    = 0x%04X", reg);
+	cc1 = (reg >> 0) & 3;
+	switch (cc1) {
+	case 0:
+		ccprints("\t00: CC1 == Ra");
+		break;
+	case 1:
+		ccprints("\t01: CC1 == Rp");
+		break;
+	case 2:
+		ccprints("\t02: CC1 == Rd");
+		break;
+	case 3:
+		ccprints("\t03: CC1 == OPEN");
+		break;
+	}
+	cc2 = (reg >> 2) & 3;
+	switch (cc2) {
+	case 0:
+		ccprints("\t00: CC2 == Ra");
+		break;
+	case 1:
+		ccprints("\t04: CC2 == Rp");
+		break;
+	case 2:
+		ccprints("\t08: CC2 == Rd");
+		break;
+	case 3:
+		ccprints("\t0C: CC2 == OPEN");
+		break;
+	}
+	switch ((reg >> 4) & 3) {
+	case 0:
+		ccprints("\t00: Rp Value == default");
+		break;
+	case 1:
+		ccprints("\t10: Rp Value == 1.5A");
+		break;
+	case 2:
+		ccprints("\t20: Rp Value == 3A");
+		break;
+	}
+	if (reg & BIT(6))
+		ccprints("\t40: DRP");
+
+	reg = mock_tcpci_get_reg(TCPC_REG_FAULT_CTRL);
+	ccprints("TCPC_REG_FAULT_CTRL   = 0x%04X", reg);
+	if (reg & BIT(0))
+		ccprints("\t01: Vconn Over Current Fault");
+	if (reg & BIT(1))
+		ccprints("\t02: Vbus OVP Fault");
+	if (reg & BIT(2))
+		ccprints("\t04: Vbus OCP Fault");
+	if (reg & BIT(3))
+		ccprints("\t08: Vbus Discharge Fault");
+	if (reg & BIT(4))
+		ccprints("\t10: Force OFF Vbus");
+
+	reg = mock_tcpci_get_reg(TCPC_REG_POWER_CTRL);
+	ccprints("TCPC_REG_POWER_CTRL   = 0x%04X", reg);
+	if (reg & BIT(0))
+		ccprints("\t01: Enable Vconn");
+	if (reg & BIT(1))
+		ccprints("\t02: Vconn Power Supported");
+	if (reg & BIT(2))
+		ccprints("\t04: Force Discharge");
+	if (reg & BIT(3))
+		ccprints("\t08: Enable Bleed Discharge");
+	if (reg & BIT(4))
+		ccprints("\t10: Auto Discharge Disconnect");
+	if (reg & BIT(5))
+		ccprints("\t20: Disable Voltage Alarms");
+	if (reg & BIT(6))
+		ccprints("\t40: VBUS_VOLTAGE monitor disabled");
+	if (reg & BIT(7))
+		ccprints("\t80: Fast Role Swap enabled");
+
+	reg = mock_tcpci_get_reg(TCPC_REG_CC_STATUS);
+	ccprints("TCPC_REG_CC_STATUS    = 0x%04X", reg);
+	switch ((reg >> 0) & 3) {
+	case 0:
+		switch (cc1) {
+		case 1:
+			ccprints("\t00: CC1-Rp SRC.Open");
+			break;
+		case 2:
+			ccprints("\t00: CC1-Rd SNK.Open");
+			break;
+		}
+		break;
+	case 1:
+		switch (cc1) {
+		case 1:
+			ccprints("\t01: CC1-Rp SRC.Ra");
+			break;
+		case 2:
+			ccprints("\t01: CC1-Rd SNK.Default");
+			break;
+		}
+		break;
+	case 2:
+		switch (cc1) {
+		case 1:
+			ccprints("\t02: CC1-Rp SRC.Rd");
+			break;
+		case 2:
+			ccprints("\t02: CC1-Rd SNK.Power1.5");
+			break;
+		}
+		break;
+	case 3:
+		switch (cc1) {
+		case 2:
+			ccprints("\t03: CC1-Rd SNK.Power3.0");
+			break;
+		}
+		break;
+	}
+	switch ((reg >> 2) & 3) {
+	case 0:
+		switch (cc2) {
+		case 1:
+			ccprints("\t00: CC2-Rp SRC.Open");
+			break;
+		case 2:
+			ccprints("\t00: CC2-Rd SNK.Open");
+			break;
+		}
+		break;
+	case 1:
+		switch (cc2) {
+		case 1:
+			ccprints("\t04: CC2-Rp SRC.Ra");
+			break;
+		case 2:
+			ccprints("\t04: CC2-Rd SNK.Default");
+			break;
+		}
+		break;
+	case 2:
+		switch (cc2) {
+		case 1:
+			ccprints("\t08: CC2-Rp SRC.Rd");
+			break;
+		case 2:
+			ccprints("\t08: CC2-Rd SNK.Power1.5");
+			break;
+		}
+		break;
+	case 3:
+		switch (cc2) {
+		case 2:
+			ccprints("\t0C: CC2-Rd SNK.Power3.0");
+			break;
+		}
+		break;
+	}
+	if (reg & BIT(4))
+		ccprints("\t10: Presenting Rd");
+	else
+		ccprints("\t00: Presenting Rp");
+	if (reg & BIT(5))
+		ccprints("\t20: Looking4Connection");
+
+	reg = mock_tcpci_get_reg(TCPC_REG_POWER_STATUS);
+	ccprints("TCPC_REG_POWER_STATUS = 0x%04X", reg);
+	if (reg & BIT(0))
+		ccprints("\t01: Sinking Vbus");
+	if (reg & BIT(1))
+		ccprints("\t02: Vconn Present");
+	if (reg & BIT(2))
+		ccprints("\t04: Vbus Present");
+	if (reg & BIT(3))
+		ccprints("\t08: Vbus Detect enabled");
+	if (reg & BIT(4))
+		ccprints("\t10: Sourcing Vbus");
+	if (reg & BIT(5))
+		ccprints("\t20: Sourcing non-default voltage");
+	if (reg & BIT(6))
+		ccprints("\t40: TCPC Initialization");
+	if (reg & BIT(7))
+		ccprints("\t80: Debug Accessory Connected");
+
+	reg = mock_tcpci_get_reg(TCPC_REG_FAULT_STATUS);
+	ccprints("TCPC_REG_FAULT_STATUS = 0x%04X", reg);
+	if (reg & BIT(0))
+		ccprints("\t01: I2C Interface Error");
+	if (reg & BIT(1))
+		ccprints("\t02: Vconn Over Current Fault");
+	if (reg & BIT(2))
+		ccprints("\t04: Vbus OVP Fault");
+	if (reg & BIT(3))
+		ccprints("\t08: Vbus OCP Fault");
+	if (reg & BIT(4))
+		ccprints("\t10: Forced Discharge Failed");
+	if (reg & BIT(5))
+		ccprints("\t20: Auto Discharge Failed");
+	if (reg & BIT(6))
+		ccprints("\t40: Force OFF Vbus");
+	if (reg & BIT(7))
+		ccprints("\t80: TCPCI Registers Reset2Default");
+
+	reg = mock_tcpci_get_reg(TCPC_REG_EXT_STATUS);
+	ccprints("TCPC_REG_EXT_STATUS   = 0x%04X", reg);
+	if (reg & BIT(0))
+		ccprints("\t01: Vbus is at vSafe0V");
+
+	reg = mock_tcpci_get_reg(TCPC_REG_ALERT_EXT);
+	ccprints("TCPC_REG_ALERT_EXT    = 0x%04X", reg);
+	if (reg & BIT(0))
+		ccprints("\t01: SNK Fast Role Swap");
+	if (reg & BIT(1))
+		ccprints("\t02: SRC Fast Role Swap");
+	if (reg & BIT(2))
+		ccprints("\t04: Timer Expired");
+
+	reg = mock_tcpci_get_reg(TCPC_REG_COMMAND);
+	ccprints("TCPC_REG_COMMAND      = 0x%04X", reg);
+	switch (reg) {
+	case 0x11:
+		ccprints("\t11: WakeI2C");
+		break;
+	case 0x22:
+		ccprints("\t22: DisableVbusDetect");
+		break;
+	case 0x33:
+		ccprints("\t33: EnableVbusDetect");
+		break;
+	case 0x44:
+		ccprints("\t44: DisableSinkVbus");
+		break;
+	case 0x55:
+		ccprints("\t55: SinkVbus");
+		break;
+	case 0x66:
+		ccprints("\t66: DisableSourceVbus");
+		break;
+	case 0x77:
+		ccprints("\t77: SourceVbusDefaultVoltage");
+		break;
+	case 0x88:
+		ccprints("\t88: SourceVbusNondefaultVoltage");
+		break;
+	case 0x99:
+		ccprints("\t99: Looking4Connection");
+		break;
+	case 0xAA:
+		ccprints("\tAA: RxOneMore");
+		break;
+	case 0xCC:
+		ccprints("\tCC: SendFRSwapSignal");
+		break;
+	case 0xDD:
+		ccprints("\tDD: ResetTransmitBuffer");
+		break;
+	case 0xEE:
+		ccprints("\tEE: ResetReceiveBuffer");
+		break;
+	case 0xFF:
+		ccprints("\tFF: I2C Idle");
+		break;
+	}
+
+	reg = mock_tcpci_get_reg(TCPC_REG_MSG_HDR_INFO);
+	ccprints("TCPC_REG_MSG_HDR_INFO = 0x%04X", reg);
+	if (reg & BIT(0))
+		ccprints("\t01: Power Role SRC");
+	else
+		ccprints("\t00: Power Role SNK");
+	switch ((reg >> 1) & 3) {
+	case 0:
+		ccprints("\t00: PD Revision 1.0");
+		break;
+	case 1:
+		ccprints("\t02: PD Revision 2.0");
+		break;
+	case 2:
+		ccprints("\t04: PD Revision 3.0");
+		break;
+	}
+	if (reg & BIT(3))
+		ccprints("\t08: Data Role DFP");
+	else
+		ccprints("\t00: Data Role UFP");
+	if (reg & BIT(4))
+		ccprints("\t10: Message originating from Cable Plug");
+	else
+		ccprints("\t00: Message originating from SRC/SNK/DRP");
+
+	reg = mock_tcpci_get_reg(TCPC_REG_RX_BUFFER);
+	ccprints("TCPC_REG_RX_BUFFER    = 0x%04X", reg);
+
+	reg = mock_tcpci_get_reg(TCPC_REG_TRANSMIT);
+	ccprints("TCPC_REG_TRANSMIT     = 0x%04X", reg);
+	ccprints("*****************************************");
+}
diff --git a/common/mock/tcpm_mock.c b/common/mock/tcpm_mock.c
index 81534ad8be..a54b31839b 100644
--- a/common/mock/tcpm_mock.c
+++ b/common/mock/tcpm_mock.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,6 +9,10 @@
 #include "memory.h"
 #include "mock/tcpm_mock.h"
 
+#ifndef TEST_BUILD
+#error "Mocks should only be in the test build."
+#endif
+
 struct mock_tcpm_t mock_tcpm[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 /**
@@ -27,7 +31,7 @@ int tcpm_dequeue_message(int port, uint32_t *payload, int *header)
 
 	*header = mock_tcpm[port].mock_header;
 	memcpy(payload, mock_tcpm[port].mock_rx_chk_buf,
-		sizeof(mock_tcpm[port].mock_rx_chk_buf));
+	       sizeof(mock_tcpm[port].mock_rx_chk_buf));
 
 	return EC_SUCCESS;
 }
@@ -47,7 +51,7 @@ void mock_tcpm_reset(void)
 {
 	int port;
 
-	for (port = 0 ; port < CONFIG_USB_PD_PORT_MAX_COUNT ; ++port)
+	for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
 		mock_tcpm[port].mock_has_pending_message = 0;
 }
 
@@ -61,7 +65,7 @@ void mock_tcpm_rx_msg(int port, uint16_t header, int cnt, const uint32_t *data)
 	if (cnt > 0) {
 		int idx;
 
-		for (idx = 0 ; (idx < cnt) && (idx < MOCK_CHK_BUF_SIZE) ; ++idx)
+		for (idx = 0; (idx < cnt) && (idx < MOCK_CHK_BUF_SIZE); ++idx)
 			mock_tcpm[port].mock_rx_chk_buf[idx] = data[idx];
 	}
 	mock_tcpm[port].mock_has_pending_message = 1;
diff --git a/common/mock/timer_mock.c b/common/mock/timer_mock.c
index 21408b7fe6..0504578412 100644
--- a/common/mock/timer_mock.c
+++ b/common/mock/timer_mock.c
@@ -1,10 +1,14 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "mock/timer_mock.h"
 
+#ifndef TEST_BUILD
+#error "Mocks should only be in the test build."
+#endif
+
 static timestamp_t now;
 
 void set_time(timestamp_t now_)
diff --git a/common/mock/usb_mux_mock.c b/common/mock/usb_mux_mock.c
index 2b9a5296fc..b612f47d4f 100644
--- a/common/mock/usb_mux_mock.c
+++ b/common/mock/usb_mux_mock.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,14 +6,18 @@
 
 #include "common.h"
 #include "console.h"
-#include "usb_mux.h"
-#include "mock/usb_mux_mock.h"
 #include "memory.h"
+#include "mock/usb_mux_mock.h"
+#include "usb_mux.h"
 
 #ifndef CONFIG_COMMON_RUNTIME
 #define cprints(format, args...)
 #endif
 
+#ifndef TEST_BUILD
+#error "Mocks should only be in the test build."
+#endif
+
 /* Public API for controlling/inspecting this mock */
 struct mock_usb_mux_ctrl mock_usb_mux;
 
@@ -27,8 +31,12 @@ static int mock_init(const struct usb_mux *me)
 	return EC_SUCCESS;
 }
 
-static int mock_set(const struct usb_mux *me, mux_state_t mux_state)
+static int mock_set(const struct usb_mux *me, mux_state_t mux_state,
+		    bool *ack_required)
 {
+	/* Mock does not use host command ACKs */
+	*ack_required = false;
+
 	mock_usb_mux.state = mux_state;
 	++mock_usb_mux.num_set_calls;
 	ccprints("[MUX] Set to 0x%02x", mux_state);
diff --git a/common/mock/usb_pd_dpm_mock.c b/common/mock/usb_pd_dpm_mock.c
index 344d53576d..fee51b3e15 100644
--- a/common/mock/usb_pd_dpm_mock.c
+++ b/common/mock/usb_pd_dpm_mock.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,9 +8,20 @@
  * Refer to USB PD 3.0 spec, version 2.0, sections 8.2 and 8.3
  */
 
-#include "usb_pd.h"
-#include "mock/usb_pd_dpm_mock.h"
 #include "memory.h"
+#include "mock/usb_pd_dpm_mock.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+
+#ifndef TEST_BUILD
+#error "Mocks should only be in the test build."
+#endif
+
+__overridable const struct svdm_response svdm_rsp = {
+	.identity = NULL,
+	.svids = NULL,
+	.modes = NULL,
+};
 
 struct mock_dpm_port_t dpm[CONFIG_USB_PD_PORT_MAX_COUNT];
 
@@ -20,23 +31,35 @@ void mock_dpm_reset(void)
 	memset(dpm, 0, sizeof(dpm));
 }
 
+void dfp_consume_attention(int port, uint32_t *payload)
+{
+}
+
+void pd_prepare_sysjump(void)
+{
+}
+
 void dpm_init(int port)
 {
 	dpm[port].mode_entry_done = false;
 	dpm[port].mode_exit_request = false;
 }
 
-void dpm_vdm_acked(int port, enum tcpm_transmit_type type, int vdo_count,
-		uint32_t *vdm)
+void dpm_mode_exit_complete(int port)
 {
 }
 
-void dpm_vdm_naked(int port, enum tcpm_transmit_type type, uint16_t svid,
-		uint8_t vdm_cmd)
+void dpm_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count,
+		   uint32_t *vdm)
 {
 }
 
-void dpm_set_mode_entry_done(int port)
+void dpm_vdm_naked(int port, enum tcpci_msg_type type, uint16_t svid,
+		   uint8_t vdm_cmd, uint32_t vdm_header)
+{
+}
+
+void dpm_notify_attention(int port, size_t vdo_objects, uint32_t *buf)
 {
 }
 
@@ -44,6 +67,53 @@ void dpm_set_mode_exit_request(int port)
 {
 }
 
-void dpm_run(int port)
+void dpm_run(int port, int evt, int en)
+{
+}
+
+void dpm_evaluate_sink_fixed_pdo(int port, uint32_t vsafe5v_pdo)
+{
+}
+
+void dpm_add_non_pd_sink(int port)
+{
+}
+
+void dpm_evaluate_request_rdo(int port, uint32_t rdo)
+{
+}
+
+void dpm_remove_sink(int port)
+{
+}
+
+void dpm_remove_source(int port)
+{
+}
+
+void dpm_bist_shared_mode_enter(int port)
+{
+}
+
+void dpm_bist_shared_mode_exit(int port)
+{
+}
+
+int dpm_get_source_pdo(const uint32_t **src_pdo, const int port)
+{
+	*src_pdo = pd_src_pdo;
+	return pd_src_pdo_cnt;
+}
+
+int dpm_get_status_msg(int port, uint8_t *msg, uint32_t *len)
+{
+	return EC_SUCCESS;
+}
+
+void dpm_handle_alert(int port, uint32_t ado)
+{
+}
+
+void dpm_set_pe_ready(int port, bool enable)
 {
 }
diff --git a/common/mock/usb_pd_mock.c b/common/mock/usb_pd_mock.c
deleted file mode 100644
index 653c98c78e..0000000000
--- a/common/mock/usb_pd_mock.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Mock USB Type-C PD */
-
-#include "common.h"
-#include "console.h"
-#include "usb_pd.h"
-#include "mock/usb_pd_mock.h"
-#include "memory.h"
-
-struct mock_pd_port_t mock_pd_port[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-void mock_pd_reset(void)
-{
-	/* Reset all values to 0. */
-	memset(mock_pd_port, 0, sizeof(mock_pd_port));
-}
-
-enum pd_dual_role_states pd_get_dual_role(int port)
-{
-	return PD_DRP_TOGGLE_ON;
-}
-
-enum pd_data_role pd_get_data_role(int port)
-{
-	return mock_pd_port[port].data_role;
-}
-
-enum pd_power_role pd_get_power_role(int port)
-{
-	return mock_pd_port[port].power_role;
-}
-
-enum pd_cc_states pd_get_task_cc_state(int port)
-{
-	return PD_CC_NONE;
-}
-
-int pd_is_connected(int port)
-{
-	return 1;
-}
-
-bool pd_is_disconnected(int port)
-{
-	return false;
-}
-
-__overridable const uint32_t * const pd_get_src_caps(int port)
-{
-	return NULL;
-}
-
-__overridable uint8_t pd_get_src_cap_cnt(int port)
-{
-	return 0;
-}
-
-__overridable void pd_set_src_caps(int port, int cnt, uint32_t *src_caps)
-{
-}
-
-bool pd_get_partner_usb_comm_capable(int port)
-{
-	return true;
-}
-
-inline uint8_t board_get_usb_pd_port_count(void)
-{
-	return CONFIG_USB_PD_PORT_MAX_COUNT;
-}
-
-void pd_set_suspend(int port, int suspend)
-{
-}
-
-enum tcpc_cc_polarity pd_get_polarity(int port)
-{
-	return POLARITY_CC1;
-}
-
-void pd_request_data_swap(int port)
-{}
-
-void pd_request_vconn_swap_off(int port)
-{}
-
-void pd_request_vconn_swap_on(int port)
-{}
-
-bool pd_alt_mode_capable(int port)
-{
-	return false;
-}
diff --git a/common/mock/usb_pe_sm_mock.c b/common/mock/usb_pe_sm_mock.c
index a62f9709f5..38df938c46 100644
--- a/common/mock/usb_pe_sm_mock.c
+++ b/common/mock/usb_pe_sm_mock.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,18 +7,22 @@
 
 #include "common.h"
 #include "console.h"
-#include "usb_pe_sm.h"
-#include "mock/usb_pe_sm_mock.h"
 #include "memory.h"
+#include "mock/usb_pe_sm_mock.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usb_pe_sm.h"
 
 #ifndef CONFIG_COMMON_RUNTIME
 #define cprints(format, args...)
 #endif
 
+#ifndef TEST_BUILD
+#error "Mocks should only be in the test build."
+#endif
 
 struct mock_pe_port_t mock_pe_port[CONFIG_USB_PD_PORT_MAX_COUNT];
 
-
 /**
  * Resets all mock PE ports to initial values
  */
@@ -26,7 +30,7 @@ void mock_pe_port_reset(void)
 {
 	int port;
 
-	for (port = 0 ; port < CONFIG_USB_PD_PORT_MAX_COUNT ; ++port) {
+	for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) {
 		mock_pe_port[port].mock_pe_error = -1;
 		/* These mock variable only get set to 1 by various functions,
 		 * so initialize them to 0. Tests can verify they are still 0
@@ -41,7 +45,7 @@ void mock_pe_port_reset(void)
 	}
 }
 
-void pe_report_error(int port, enum pe_error e, enum tcpm_transmit_type type)
+void pe_report_error(int port, enum pe_error e, enum tcpci_msg_type type)
 {
 	mock_pe_port[port].mock_pe_error = e;
 	mock_pe_port[port].sop = type;
@@ -77,9 +81,40 @@ void pe_got_soft_reset(int port)
 	mock_pe_port[port].mock_got_soft_reset = 1;
 }
 
+bool pe_in_frs_mode(int port)
+{
+	return false;
+}
+
 bool pe_in_local_ams(int port)
 {
 	/* We will probably want to change this in the future */
 	return false;
 }
 
+const uint32_t *const pd_get_src_caps(int port)
+{
+	return NULL;
+}
+
+uint8_t pd_get_src_cap_cnt(int port)
+{
+	return 0;
+}
+
+void pd_set_src_caps(int port, int cnt, uint32_t *src_caps)
+{
+}
+
+void pd_request_power_swap(int port)
+{
+}
+
+int pd_get_rev(int port, enum tcpci_msg_type type)
+{
+	return IS_ENABLED(CONFIG_USB_PD_REV30) ? PD_REV30 : PD_REV20;
+}
+
+void pe_invalidate_explicit_contract(int port)
+{
+}
diff --git a/common/mock/usb_prl_mock.c b/common/mock/usb_prl_mock.c
index b682e67f80..e69ad38712 100644
--- a/common/mock/usb_prl_mock.c
+++ b/common/mock/usb_prl_mock.c
@@ -1,15 +1,24 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
- * Fake Protocol Layer module.
+ * Mock Protocol Layer module.
  */
-#include <string.h>
 #include "common.h"
+#include "mock/usb_prl_mock.h"
+#include "task.h"
+#include "test_util.h"
+#include "timer.h"
 #include "usb_emsg.h"
+#include "usb_pd_tcpm.h"
 #include "usb_pe_sm.h"
 #include "usb_prl_sm.h"
-#include "mock/usb_prl_mock.h"
+
+#include <string.h>
+
+#ifndef TEST_BUILD
+#error "Mocks should only be in the test build."
+#endif
 
 /* Defaults should all be 0 values. */
 struct extended_msg rx_emsg[CONFIG_USB_PD_PORT_MAX_COUNT];
@@ -17,10 +26,12 @@ struct extended_msg tx_emsg[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 struct mock_prl_port_t {
 	enum pd_ctrl_msg_type last_ctrl_msg;
-	enum pd_data_msg_type last_data_msg_type;
+	enum pd_data_msg_type last_data_msg;
+	enum tcpci_msg_type last_tx_type;
 	bool message_sent;
 	bool message_received;
-	int pe_error;
+	enum pe_error error;
+	enum tcpci_msg_type error_tx_type;
 };
 
 struct mock_prl_port_t mock_prl_port[CONFIG_USB_PD_PORT_MAX_COUNT];
@@ -35,23 +46,35 @@ void mock_prl_reset(void)
 
 	memset(mock_prl_port, 0, sizeof(mock_prl_port));
 
-	for (port = 0 ; port < CONFIG_USB_PD_PORT_MAX_COUNT ; ++port)
-		mock_prl_port[port].pe_error = -1;
+	for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) {
+		mock_prl_port[port].last_tx_type = TCPCI_MSG_INVALID;
+		mock_prl_port[port].error_tx_type = TCPCI_MSG_INVALID;
+	}
 }
 
 void prl_end_ams(int port)
-{}
+{
+}
 
 void prl_execute_hard_reset(int port)
-{}
+{
+	mock_prl_port[port].last_ctrl_msg = 0;
+	mock_prl_port[port].last_data_msg = 0;
+	mock_prl_port[port].last_tx_type = TCPCI_MSG_TX_HARD_RESET;
+}
 
-enum pd_rev_type prl_get_rev(int port, enum tcpm_transmit_type partner)
+void prl_set_data_role_check(int port, bool enable)
+{
+}
+
+enum pd_rev_type prl_get_rev(int port, enum tcpci_msg_type partner)
 {
 	return PD_REV30;
 }
 
 void prl_hard_reset_complete(int port)
-{}
+{
+}
 
 int prl_is_running(int port)
 {
@@ -63,72 +86,101 @@ __overridable bool prl_is_busy(int port)
 	return false;
 }
 
-void prl_reset(int port)
-{}
-
 void prl_reset_soft(int port)
-{}
+{
+}
 
-void prl_send_ctrl_msg(int port, enum tcpm_transmit_type type,
-	enum pd_ctrl_msg_type msg)
+void prl_send_ctrl_msg(int port, enum tcpci_msg_type type,
+		       enum pd_ctrl_msg_type msg)
 {
 	mock_prl_port[port].last_ctrl_msg = msg;
+	mock_prl_port[port].last_data_msg = 0;
+	mock_prl_port[port].last_tx_type = type;
 }
 
-void prl_send_data_msg(int port, enum tcpm_transmit_type type,
-	enum pd_data_msg_type msg)
+void prl_send_data_msg(int port, enum tcpci_msg_type type,
+		       enum pd_data_msg_type msg)
 {
-	mock_prl_port[port].last_data_msg_type = msg;
+	mock_prl_port[port].last_data_msg = msg;
+	mock_prl_port[port].last_ctrl_msg = 0;
+	mock_prl_port[port].last_tx_type = type;
 }
 
-void prl_send_ext_data_msg(int port, enum tcpm_transmit_type type,
-	enum pd_ext_msg_type msg)
-{}
+void prl_send_ext_data_msg(int port, enum tcpci_msg_type type,
+			   enum pd_ext_msg_type msg)
+{
+}
 
-void prl_set_rev(int port, enum tcpm_transmit_type partner,
-	enum pd_rev_type rev)
-{}
+void prl_set_rev(int port, enum tcpci_msg_type partner, enum pd_rev_type rev)
+{
+}
 
+int mock_prl_wait_for_tx_msg(int port, enum tcpci_msg_type tx_type,
+			     enum pd_ctrl_msg_type ctrl_msg,
+			     enum pd_data_msg_type data_msg, int timeout)
+{
+	uint64_t end_time = get_time().val + timeout;
+
+	while (get_time().val < end_time) {
+		if (mock_prl_port[port].last_tx_type != TCPCI_MSG_INVALID) {
+			TEST_EQ(mock_prl_port[port].last_tx_type, tx_type,
+				"%d");
+			TEST_EQ(mock_prl_port[port].last_ctrl_msg, ctrl_msg,
+				"%d");
+			TEST_EQ(mock_prl_port[port].last_data_msg, data_msg,
+				"%d");
+			mock_prl_clear_last_sent_msg(port);
+			return EC_SUCCESS;
+		}
+		task_wait_event(5 * MSEC);
+	}
+	/* A message of the expected type should have been sent by end_time. */
+	TEST_ASSERT(0);
+	return EC_ERROR_UNKNOWN;
+}
 
-enum pd_ctrl_msg_type fake_prl_get_last_sent_ctrl_msg(int port)
+enum pd_ctrl_msg_type mock_prl_get_last_sent_ctrl_msg(int port)
 {
 	enum pd_ctrl_msg_type last = mock_prl_port[port].last_ctrl_msg;
 
-	fake_prl_clear_last_sent_ctrl_msg(port);
+	mock_prl_clear_last_sent_msg(port);
 	return last;
 }
 
-void fake_prl_clear_last_sent_ctrl_msg(int port)
-{
-	mock_prl_port[port].last_ctrl_msg = 0;
-}
-
-enum pd_data_msg_type fake_prl_get_last_sent_data_msg_type(int port)
+enum pd_data_msg_type mock_prl_get_last_sent_data_msg(int port)
 {
-	enum pd_data_msg_type last = mock_prl_port[port].last_data_msg_type;
+	enum pd_data_msg_type last = mock_prl_port[port].last_data_msg;
 
-	fake_prl_clear_last_sent_data_msg(port);
+	mock_prl_clear_last_sent_msg(port);
 	return last;
 }
 
-void fake_prl_clear_last_sent_data_msg(int port)
+void mock_prl_clear_last_sent_msg(int port)
 {
-	mock_prl_port[port].last_data_msg_type = 0;
+	mock_prl_port[port].last_data_msg = 0;
+	mock_prl_port[port].last_ctrl_msg = 0;
+	mock_prl_port[port].last_tx_type = TCPCI_MSG_INVALID;
 }
 
-void fake_prl_message_sent(int port)
+timestamp_t prl_get_tcpc_tx_success_ts(int port)
+{
+	return get_time();
+}
+void mock_prl_message_sent(int port)
 {
 	mock_prl_port[port].message_sent = 1;
 }
 
-void fake_prl_message_received(int port)
+void mock_prl_message_received(int port)
 {
 	mock_prl_port[port].message_received = 1;
 }
 
-void fake_prl_report_error(int port, enum pe_error e)
+void mock_prl_report_error(int port, enum pe_error e,
+			   enum tcpci_msg_type tx_type)
 {
-	mock_prl_port[port].pe_error = e;
+	mock_prl_port[port].error = e;
+	mock_prl_port[port].error_tx_type = tx_type;
 }
 
 void prl_run(int port, int evt, int en)
@@ -143,11 +195,11 @@ void prl_run(int port, int evt, int en)
 		pe_message_received(port);
 		mock_prl_port[port].message_received = 0;
 	}
-	if (mock_prl_port[port].pe_error >= 0) {
-		ccprints("pe_error %d", mock_prl_port[port].pe_error);
-		pe_report_error(port,
-				mock_prl_port[port].pe_error,
-				TCPC_TX_SOP);
-		mock_prl_port[port].pe_error = -1;
+	if (mock_prl_port[port].error_tx_type != TCPCI_MSG_INVALID) {
+		ccprints("pe_error %d", mock_prl_port[port].error);
+		pe_report_error(port, mock_prl_port[port].error,
+				mock_prl_port[port].error_tx_type);
+		mock_prl_port[port].error = 0;
+		mock_prl_port[port].error_tx_type = TCPCI_MSG_INVALID;
 	}
 }
diff --git a/common/mock/usb_tc_sm_mock.c b/common/mock/usb_tc_sm_mock.c
index dfe8eeef48..6adf6b3246 100644
--- a/common/mock/usb_tc_sm_mock.c
+++ b/common/mock/usb_tc_sm_mock.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,29 +7,37 @@
 
 #include "common.h"
 #include "console.h"
-#include "usb_tc_sm.h"
-#include "mock/usb_tc_sm_mock.h"
+#include "ec_commands.h"
 #include "memory.h"
+#include "mock/usb_tc_sm_mock.h"
+#include "usb_tc_sm.h"
 
 #ifndef CONFIG_COMMON_RUNTIME
 #define cprints(format, args...)
 #endif
 
+#ifndef TEST_BUILD
+#error "Mocks should only be in the test build."
+#endif
+
 struct mock_tc_port_t mock_tc_port[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 void mock_tc_port_reset(void)
 {
 	int port;
 
-	for (port = 0 ; port < CONFIG_USB_PD_PORT_MAX_COUNT ; ++port) {
+	for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) {
 		mock_tc_port[port].rev = PD_REV30;
 		mock_tc_port[port].pd_enable = 0;
 		mock_tc_port[port].msg_tx_id = 0;
 		mock_tc_port[port].msg_rx_id = 0;
-		mock_tc_port[port].sop = TCPC_TX_INVALID;
+		mock_tc_port[port].sop = TCPCI_MSG_INVALID;
 		mock_tc_port[port].lcl_rp = TYPEC_RP_RESERVED;
 		mock_tc_port[port].attached_snk = 0;
 		mock_tc_port[port].attached_src = 0;
+		mock_tc_port[port].vconn_src = false;
+		mock_tc_port[port].data_role = PD_ROLE_UFP;
+		mock_tc_port[port].power_role = PD_ROLE_SINK;
 	}
 }
 
@@ -48,6 +56,10 @@ void typec_select_src_collision_rp(int port, enum tcpc_rp_value rp)
 	mock_tc_port[port].lcl_rp = rp;
 }
 
+void typec_select_src_current_limit_rp(int port, enum tcpc_rp_value rp)
+{
+}
+
 int tc_is_attached_src(int port)
 {
 	return mock_tc_port[port].attached_src;
@@ -81,11 +93,12 @@ int tc_check_vconn_swap(int port)
 }
 
 void tc_ctvpd_detected(int port)
-{}
+{
+}
 
 int tc_is_vconn_src(int port)
 {
-	return 0;
+	return mock_tc_port[port].vconn_src;
 }
 
 void tc_hard_reset_request(int port)
@@ -94,32 +107,121 @@ void tc_hard_reset_request(int port)
 }
 
 void tc_partner_dr_data(int port, int en)
-{}
+{
+}
 
 void tc_partner_dr_power(int port, int en)
-{}
+{
+}
 
 void tc_partner_unconstrainedpower(int port, int en)
-{}
+{
+}
 
 void tc_partner_usb_comm(int port, int en)
-{}
+{
+}
 
 void tc_pd_connection(int port, int en)
-{}
+{
+}
 
 void tc_pr_swap_complete(int port, bool success)
-{}
+{
+}
 
 void tc_src_power_off(int port)
-{}
+{
+}
 
 void tc_start_error_recovery(int port)
-{}
+{
+}
 
 void tc_snk_power_off(int port)
-{}
+{
+}
 
 void tc_request_power_swap(int port)
 {
 }
+
+enum pd_dual_role_states pd_get_dual_role(int port)
+{
+	return PD_DRP_TOGGLE_ON;
+}
+
+enum pd_data_role pd_get_data_role(int port)
+{
+	return mock_tc_port[port].data_role;
+}
+
+enum pd_power_role pd_get_power_role(int port)
+{
+	return mock_tc_port[port].power_role;
+}
+
+enum pd_cc_states pd_get_task_cc_state(int port)
+{
+	return PD_CC_NONE;
+}
+
+int pd_is_connected(int port)
+{
+	return 1;
+}
+
+bool pd_is_disconnected(int port)
+{
+	return false;
+}
+
+bool pd_get_partner_usb_comm_capable(int port)
+{
+	return true;
+}
+
+bool pd_get_partner_dual_role_power(int port)
+{
+	return true;
+}
+
+bool pd_capable(int port)
+{
+	return true;
+}
+
+bool pd_waiting_on_partner_src_caps(int port)
+{
+	return false;
+}
+
+void pd_set_suspend(int port, int suspend)
+{
+}
+
+void pd_set_error_recovery(int port)
+{
+}
+
+enum tcpc_cc_polarity pd_get_polarity(int port)
+{
+	return POLARITY_CC1;
+}
+
+void pd_request_data_swap(int port)
+{
+}
+
+void pd_request_vconn_swap_off(int port)
+{
+}
+
+void pd_request_vconn_swap_on(int port)
+{
+}
+
+bool pd_alt_mode_capable(int port)
+{
+	return false;
+}
diff --git a/common/motion_lid.c b/common/motion_lid.c
index bdef89f3b7..878d471ed4 100644
--- a/common/motion_lid.c
+++ b/common/motion_lid.c
@@ -1,12 +1,12 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Motion sense module to read from various motion sensors. */
 
-#include "acpi.h"
 #include "accelgyro.h"
+#include "acpi.h"
 #include "chipset.h"
 #include "common.h"
 #include "console.h"
@@ -20,14 +20,14 @@
 #include "motion_sense.h"
 #include "power.h"
 #include "tablet_mode.h"
-#include "timer.h"
 #include "task.h"
+#include "timer.h"
 #include "util.h"
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_MOTION_LID, outstr)
-#define CPRINTS(format, args...) cprints(CC_MOTION_LID, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_MOTION_LID, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_MOTION_LID, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_MOTION_LID, format, ##args)
 
 #ifdef CONFIG_TABLET_MODE
 /* Previous lid_angle. */
@@ -50,7 +50,7 @@ static int lid_angle_is_reliable;
 static intv3_t smoothed_base, smoothed_lid;
 
 /* 8.7 m/s^2 is the the maximum acceleration parallel to the hinge */
-#define SCALED_HINGE_VERTICAL_MAXIMUM  \
+#define SCALED_HINGE_VERTICAL_MAXIMUM \
 	((int)((8.7f * MOTION_SCALING_FACTOR) / MOTION_ONE_G))
 
 #define SCALED_HINGE_VERTICAL_SMOOTHING_START \
@@ -78,7 +78,7 @@ static intv3_t smoothed_base, smoothed_lid;
  * is less than 1<<31, so magnitude is less sqrt(2)*(1<<15), less than ~40% over
  * 1g. This is way above any usable noise. Assume noise is less than 10%.
  */
-#define MOTION_SCALING_AXIS_MAX (MOTION_SCALING_FACTOR * 110)
+#define MOTION_SCALING_AXIS_MAX ((MOTION_SCALING_FACTOR * 110) / 100)
 
 #define MOTION_SCALING_FACTOR2 (MOTION_SCALING_FACTOR * MOTION_SCALING_FACTOR)
 
@@ -88,18 +88,27 @@ static intv3_t smoothed_base, smoothed_lid;
  * frame before calculating lid angle).
  */
 #ifdef CONFIG_ACCEL_STD_REF_FRAME_OLD
-static const intv3_t hinge_axis = { 0, 1, 0};
+static const intv3_t hinge_axis = { 0, 1, 0 };
 #define HINGE_AXIS Y
 #else
-static const intv3_t hinge_axis = { 1, 0, 0};
+static const intv3_t hinge_axis = { 1, 0, 0 };
 #define HINGE_AXIS X
 #endif
 
-static const struct motion_sensor_t * const accel_base =
+static const struct motion_sensor_t *const accel_base =
 	&motion_sensors[CONFIG_LID_ANGLE_SENSOR_BASE];
-static const struct motion_sensor_t * const accel_lid =
+static const struct motion_sensor_t *const accel_lid =
 	&motion_sensors[CONFIG_LID_ANGLE_SENSOR_LID];
 
+STATIC_IF(CONFIG_TABLET_MODE) void motion_lid_set_tablet_mode(int reliable);
+STATIC_IF(CONFIG_TABLET_MODE)
+int lid_angle_set_tablet_mode_threshold(int angle, int hys);
+
+STATIC_IF(CONFIG_TABLET_MODE) fp_t tablet_zone_lid_angle;
+STATIC_IF(CONFIG_TABLET_MODE) fp_t laptop_zone_lid_angle;
+STATIC_IF(CONFIG_TABLET_MODE) int tablet_mode_lid_angle;
+STATIC_IF(CONFIG_TABLET_MODE) int tablet_mode_hys_degree;
+
 #ifdef CONFIG_TABLET_MODE
 __attribute__((weak)) int board_is_lid_angle_tablet_mode(void)
 {
@@ -133,18 +142,16 @@ __attribute__((weak)) int board_is_lid_angle_tablet_mode(void)
  * by using MOTIONSENSE_CMD_TABLET_MODE_LID_ANGLE.
  */
 
-#define DEFAULT_TABLET_MODE_ANGLE	(180)
-#define DEFAULT_TABLET_MODE_HYS	(20)
+#define DEFAULT_TABLET_MODE_ANGLE (180)
+#define DEFAULT_TABLET_MODE_HYS (20)
 
-#define TABLET_ZONE_ANGLE(a, h)	((a) + (h))
-#define LAPTOP_ZONE_ANGLE(a, h)	((a) - (h))
+#define TABLET_ZONE_ANGLE(a, h) ((a) + (h))
+#define LAPTOP_ZONE_ANGLE(a, h) ((a) - (h))
 
-static fp_t tablet_zone_lid_angle =
-	FLOAT_TO_FP(TABLET_ZONE_ANGLE(DEFAULT_TABLET_MODE_ANGLE,
-				      DEFAULT_TABLET_MODE_HYS));
-static fp_t laptop_zone_lid_angle =
-	FLOAT_TO_FP(LAPTOP_ZONE_ANGLE(DEFAULT_TABLET_MODE_ANGLE,
-				      DEFAULT_TABLET_MODE_HYS));
+static fp_t tablet_zone_lid_angle = FLOAT_TO_FP(
+	TABLET_ZONE_ANGLE(DEFAULT_TABLET_MODE_ANGLE, DEFAULT_TABLET_MODE_HYS));
+static fp_t laptop_zone_lid_angle = FLOAT_TO_FP(
+	LAPTOP_ZONE_ANGLE(DEFAULT_TABLET_MODE_ANGLE, DEFAULT_TABLET_MODE_HYS));
 
 static int tablet_mode_lid_angle = DEFAULT_TABLET_MODE_ANGLE;
 static int tablet_mode_hys_degree = DEFAULT_TABLET_MODE_HYS;
@@ -167,7 +174,7 @@ static void motion_lid_set_tablet_mode(int reliable)
 				/* Alright, we're convinced. */
 				tablet_mode_debounce_cnt =
 					TABLET_MODE_DEBOUNCE_COUNT;
-				tablet_set_mode(new_mode);
+				tablet_set_mode(new_mode, TABLET_TRIGGER_LID);
 				return;
 			}
 			tablet_mode_debounce_cnt--;
@@ -208,7 +215,13 @@ static int lid_angle_set_tablet_mode_threshold(int angle, int hys)
 
 #if defined(CONFIG_DPTF_MULTI_PROFILE) && \
 	defined(CONFIG_DPTF_MOTION_LID_NO_GMR_SENSOR)
+#define MOTION_LID_SET_DPTF_PROFILE
+#endif
+
+STATIC_IF(MOTION_LID_SET_DPTF_PROFILE)
+void motion_lid_set_dptf_profile(int reliable);
 
+#ifdef MOTION_LID_SET_DPTF_PROFILE
 /*
  * If CONFIG_DPTF_MULTI_PROFILE is defined by a board, then lid motion driver
  * sets different profile numbers depending upon the current lid
@@ -264,7 +277,7 @@ static void motion_lid_set_dptf_profile(int reliable)
 	debounce_cnt = DPTF_MODE_DEBOUNCE_COUNT;
 }
 
-#endif /* CONFIG_DPTF_MULTI_PROFILE && CONFIG_DPTF_MOTION_LID_NO_GMR_SENSOR */
+#endif /* MOTION_LID_SET_DPTF_PROFILE */
 
 /**
  * Calculate the lid angle using two acceleration vectors, one recorded in
@@ -292,10 +305,8 @@ static int calculate_lid_angle(const intv3_t base, const intv3_t lid,
 	 * possible.
 	 */
 	for (i = X; i <= Z; i++) {
-		scaled_base[i] = base[i] *
-			accel_base->drv->get_range(accel_base);
-		scaled_lid[i] = lid[i] *
-			accel_lid->drv->get_range(accel_lid);
+		scaled_base[i] = base[i] * accel_base->current_range;
+		scaled_lid[i] = lid[i] * accel_lid->current_range;
 		if (ABS(scaled_base[i]) > MOTION_SCALING_AXIS_MAX ||
 		    ABS(scaled_lid[i]) > MOTION_SCALING_AXIS_MAX) {
 			reliable = 0;
@@ -309,11 +320,11 @@ static int calculate_lid_angle(const intv3_t base, const intv3_t lid,
 	 * less than 1<<30.
 	 */
 	base_magnitude2 = scaled_base[X] * scaled_base[X] +
-		scaled_base[Y] * scaled_base[Y] +
-		scaled_base[Z] * scaled_base[Z];
+			  scaled_base[Y] * scaled_base[Y] +
+			  scaled_base[Z] * scaled_base[Z];
 	lid_magnitude2 = scaled_lid[X] * scaled_lid[X] +
-		scaled_lid[Y] * scaled_lid[Y] +
-		scaled_lid[Z] * scaled_lid[Z];
+			 scaled_lid[Y] * scaled_lid[Y] +
+			 scaled_lid[Z] * scaled_lid[Z];
 
 	/*
 	 * Check to see if they differ than more than NOISY_MAGNITUDE_DEVIATION.
@@ -345,14 +356,16 @@ static int calculate_lid_angle(const intv3_t base, const intv3_t lid,
 		goto end_calculate_lid_angle;
 	}
 
-	largest_hinge_accel = MAX(ABS(scaled_base[HINGE_AXIS]),
-				  ABS(scaled_lid[HINGE_AXIS]));
+	largest_hinge_accel =
+		MAX(ABS(scaled_base[HINGE_AXIS]), ABS(scaled_lid[HINGE_AXIS]));
 
-	smoothed_ratio = MAX(INT_TO_FP(0), MIN(INT_TO_FP(1),
-		fp_div(INT_TO_FP(largest_hinge_accel -
-				 SCALED_HINGE_VERTICAL_SMOOTHING_START),
-		       INT_TO_FP(SCALED_HINGE_VERTICAL_MAXIMUM -
-				 SCALED_HINGE_VERTICAL_SMOOTHING_START))));
+	smoothed_ratio = MAX(
+		INT_TO_FP(0),
+		MIN(INT_TO_FP(1),
+		    fp_div(INT_TO_FP(largest_hinge_accel -
+				     SCALED_HINGE_VERTICAL_SMOOTHING_START),
+			   INT_TO_FP(SCALED_HINGE_VERTICAL_MAXIMUM -
+				     SCALED_HINGE_VERTICAL_SMOOTHING_START))));
 
 	/* Check hinge is not too vertical */
 	if (largest_hinge_accel > SCALED_HINGE_VERTICAL_MAXIMUM) {
@@ -389,15 +402,14 @@ static int calculate_lid_angle(const intv3_t base, const intv3_t lid,
 	if (dot_product(cross, hinge_axis) > 0)
 		lid_to_base_fp = FLOAT_TO_FP(360) - lid_to_base_fp;
 
-#ifndef CONFIG_ACCEL_STD_REF_FRAME_OLD
 	/*
 	 * Angle is between the keyboard and the front of screen: we need to
 	 * anlge between keyboard and back of screen:
 	 * 180 instead of 0 when lid and base are flat on surface.
 	 * 0 instead of 180 when lid is closed on keyboard.
 	 */
-	lid_to_base_fp = FLOAT_TO_FP(180) - lid_to_base_fp;
-#endif
+	if (!IS_ENABLED(CONFIG_ACCEL_STD_REF_FRAME_OLD))
+		lid_to_base_fp = FLOAT_TO_FP(180) - lid_to_base_fp;
 
 	/* Place lid angle between 0 and 360 degrees. */
 	if (lid_to_base_fp < 0)
@@ -405,8 +417,7 @@ static int calculate_lid_angle(const intv3_t base, const intv3_t lid,
 
 #ifdef CONFIG_TABLET_MODE
 	/* Ignore large angles when the lid is closed. */
-	if (!lid_is_open() &&
-	    (lid_to_base_fp > SMALL_LID_ANGLE_RANGE)) {
+	if (!lid_is_open() && (lid_to_base_fp > SMALL_LID_ANGLE_RANGE)) {
 		reliable = 0;
 		goto end_calculate_lid_angle;
 	}
@@ -422,8 +433,7 @@ static int calculate_lid_angle(const intv3_t base, const intv3_t lid,
 	 * may wake us up.  This is because we require at least 4 consecutive
 	 * reliable readings over a threshold to disable key scanning.
 	 */
-	if (lid_is_open() &&
-	    (lid_to_base_fp <= SMALL_LID_ANGLE_RANGE)) {
+	if (lid_is_open() && (lid_to_base_fp <= SMALL_LID_ANGLE_RANGE)) {
 		reliable = 0;
 		goto end_calculate_lid_angle;
 	}
@@ -439,10 +449,8 @@ static int calculate_lid_angle(const intv3_t base, const intv3_t lid,
 	 * prove the small angle we see is correct so we take the angle
 	 * as is.
 	 */
-	if ((last_lid_angle_fp >=
-	     FLOAT_TO_FP(360) - DEBOUNCE_ANGLE_DELTA) &&
-	     (lid_to_base_fp <= DEBOUNCE_ANGLE_DELTA) &&
-	     (lid_is_open()))
+	if ((last_lid_angle_fp >= FLOAT_TO_FP(360) - DEBOUNCE_ANGLE_DELTA) &&
+	    (lid_to_base_fp <= DEBOUNCE_ANGLE_DELTA) && (lid_is_open()))
 		last_lid_angle_fp = FLOAT_TO_FP(360) - lid_to_base_fp;
 	else
 		last_lid_angle_fp = lid_to_base_fp;
@@ -457,12 +465,9 @@ static int calculate_lid_angle(const intv3_t base, const intv3_t lid,
 	if (board_is_lid_angle_tablet_mode())
 		motion_lid_set_tablet_mode(reliable);
 
-#if defined(CONFIG_DPTF_MULTI_PROFILE) && \
-	defined(CONFIG_DPTF_MOTION_LID_NO_GMR_SENSOR)
-	motion_lid_set_dptf_profile(reliable);
-#endif /* CONFIG_DPTF_MULTI_PROFILE && CONFIG_DPTF_MOTION_LID_NO_GMR_SENSOR */
-
-#else    /* CONFIG_TABLET_MODE */
+	if (IS_ENABLED(MOTION_LID_SET_DPTF_PROFILE))
+		motion_lid_set_dptf_profile(reliable);
+#else /* CONFIG_TABLET_MODE */
 end_calculate_lid_angle:
 	if (reliable)
 		*lid_angle = FP_TO_INT(lid_to_base_fp + FLOAT_TO_FP(0.5));
@@ -485,18 +490,22 @@ void motion_lid_calc(void)
 {
 	/* Calculate angle of lid accel. */
 	lid_angle_is_reliable = calculate_lid_angle(
-			accel_base->xyz, accel_lid->xyz,
-			&lid_angle_deg);
+		accel_base->xyz, accel_lid->xyz, &lid_angle_deg);
 
-#ifdef CONFIG_LID_ANGLE_UPDATE
-	lid_angle_update(motion_lid_get_angle());
-#endif
+	if (IS_ENABLED(CONFIG_LID_ANGLE_UPDATE))
+		lid_angle_update(motion_lid_get_angle());
 }
 
 /*****************************************************************************/
 /* Host commands */
 
-
+/**
+ * @brief This is a "sub"-host command accessed through EC_CMD_MOTION_SENSE_CMD,
+ *        defined in `common/motion_sense.c`
+ *
+ * @param args Hot command args
+ * @return enum ec_status Exit status
+ */
 enum ec_status host_cmd_motion_lid(struct host_cmd_handler_args *args)
 {
 	const struct ec_params_motion_sense *in = args->params;
@@ -504,35 +513,38 @@ enum ec_status host_cmd_motion_lid(struct host_cmd_handler_args *args)
 
 	switch (in->cmd) {
 	case MOTIONSENSE_CMD_KB_WAKE_ANGLE:
-#ifdef CONFIG_LID_ANGLE_UPDATE
-		/* Set new keyboard wake lid angle if data arg has value. */
-		if (in->kb_wake_angle.data != EC_MOTION_SENSE_NO_VALUE)
-			lid_angle_set_wake_angle(in->kb_wake_angle.data);
-
-		out->kb_wake_angle.ret = lid_angle_get_wake_angle();
-#else
-		out->kb_wake_angle.ret = 0;
-#endif
+		if (IS_ENABLED(CONFIG_LID_ANGLE_UPDATE)) {
+			/*
+			 * Set new keyboard wake lid angle if data arg has
+			 * value.
+			 */
+			if (in->kb_wake_angle.data != EC_MOTION_SENSE_NO_VALUE)
+				lid_angle_set_wake_angle(
+					in->kb_wake_angle.data);
+
+			out->kb_wake_angle.ret = lid_angle_get_wake_angle();
+		} else {
+			out->kb_wake_angle.ret = 0;
+		}
 		args->response_size = sizeof(out->kb_wake_angle);
 
 		break;
 
 	case MOTIONSENSE_CMD_LID_ANGLE:
-#ifdef CONFIG_LID_ANGLE
-		out->lid_angle.value = motion_lid_get_angle();
-		args->response_size = sizeof(out->lid_angle);
-#else
-		return EC_RES_INVALID_PARAM;
-#endif
+		if (IS_ENABLED(CONFIG_LID_ANGLE)) {
+			out->lid_angle.value = motion_lid_get_angle();
+			args->response_size = sizeof(out->lid_angle);
+		} else {
+			return EC_RES_INVALID_PARAM;
+		}
 		break;
 
 	case MOTIONSENSE_CMD_TABLET_MODE_LID_ANGLE:
-		{
-#ifdef CONFIG_TABLET_MODE
+		if (IS_ENABLED(CONFIG_TABLET_MODE)) {
 			int ret;
 			ret = lid_angle_set_tablet_mode_threshold(
-					in->tablet_mode_threshold.lid_angle,
-					in->tablet_mode_threshold.hys_degree);
+				in->tablet_mode_threshold.lid_angle,
+				in->tablet_mode_threshold.hys_degree);
 
 			if (ret != EC_RES_SUCCESS)
 				return ret;
@@ -544,9 +556,8 @@ enum ec_status host_cmd_motion_lid(struct host_cmd_handler_args *args)
 
 			args->response_size =
 				sizeof(out->tablet_mode_threshold);
-#else
+		} else {
 			return EC_RES_INVALID_PARAM;
-#endif
 		}
 		break;
 	default:
@@ -555,4 +566,3 @@ enum ec_status host_cmd_motion_lid(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-
diff --git a/common/motion_orientation.c b/common/motion_orientation.c
new file mode 100644
index 0000000000..1c52fe847e
--- /dev/null
+++ b/common/motion_orientation.c
@@ -0,0 +1,38 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Implement an orientation sensor. */
+
+#include "motion_orientation.h"
+
+/*
+ * Orientation mode vectors, must match sequential ordering of
+ * known orientations from enum motionsensor_orientation
+ */
+static const intv3_t orientation_modes[] = {
+	[MOTIONSENSE_ORIENTATION_LANDSCAPE] = { 0, -1, 0 },
+	[MOTIONSENSE_ORIENTATION_PORTRAIT] = { 1, 0, 0 },
+	[MOTIONSENSE_ORIENTATION_UPSIDE_DOWN_PORTRAIT] = { -1, 0, 0 },
+	[MOTIONSENSE_ORIENTATION_UPSIDE_DOWN_LANDSCAPE] = { 0, 1, 0 },
+};
+
+enum motionsensor_orientation
+motion_orientation_remap(const struct motion_sensor_t *s,
+			 enum motionsensor_orientation orientation)
+{
+	enum motionsensor_orientation rotated_orientation;
+	const intv3_t *orientation_v;
+	intv3_t rotated_orientation_v;
+
+	if (orientation == MOTIONSENSE_ORIENTATION_UNKNOWN)
+		return MOTIONSENSE_ORIENTATION_UNKNOWN;
+
+	orientation_v = &orientation_modes[orientation];
+	rotate(*orientation_v, *s->rot_standard_ref, rotated_orientation_v);
+	rotated_orientation =
+		((2 * rotated_orientation_v[1] + rotated_orientation_v[0] + 4) %
+		 5);
+	return rotated_orientation;
+}
diff --git a/common/motion_sense.c b/common/motion_sense.c
index e739bc8f75..546034c7e2 100644
--- a/common/motion_sense.c
+++ b/common/motion_sense.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,6 +8,7 @@
 #include "accelgyro.h"
 #include "atomic.h"
 #include "body_detection.h"
+#include "builtin/assert.h"
 #include "chipset.h"
 #include "common.h"
 #include "console.h"
@@ -19,72 +20,80 @@
 #include "lightbar.h"
 #include "math_util.h"
 #include "mkbp_event.h"
+#include "motion_lid.h"
+#include "motion_orientation.h"
 #include "motion_sense.h"
 #include "motion_sense_fifo.h"
-#include "motion_lid.h"
 #include "online_calibration.h"
 #include "power.h"
+#include "printf.h"
 #include "queue.h"
 #include "tablet_mode.h"
-#include "timer.h"
 #include "task.h"
+#include "timer.h"
 #include "util.h"
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_MOTION_SENSE, outstr)
-#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_MOTION_SENSE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_MOTION_SENSE, format, ##args)
 
-#ifdef CONFIG_ORIENTATION_SENSOR
-/*
- * Orientation mode vectors, must match sequential ordering of
- * known orientations from enum motionsensor_orientation
- */
-const intv3_t orientation_modes[] = {
-	[MOTIONSENSE_ORIENTATION_LANDSCAPE] = { 0, -1, 0 },
-	[MOTIONSENSE_ORIENTATION_PORTRAIT] = { 1, 0, 0 },
-	[MOTIONSENSE_ORIENTATION_UPSIDE_DOWN_PORTRAIT] = { -1, 0, 0 },
-	[MOTIONSENSE_ORIENTATION_UPSIDE_DOWN_LANDSCAPE] = { 0, 1, 0 },
-};
-#endif
+/* Number of times we ran motion_sense_task; for stats printing */
+static atomic_t motion_sense_task_loops;
 
-/* Delay between FIFO interruption. */
-static unsigned int ap_event_interval;
+/* When we started the task the last time */
+static timestamp_t ts_begin_task;
 
 /* Minimum time in between running motion sense task loop. */
 unsigned int motion_min_interval = CONFIG_MOTION_MIN_SENSE_WAIT_TIME * MSEC;
-#ifdef CONFIG_CMD_ACCEL_INFO
-static int accel_disp;
-#endif
+STATIC_IF(CONFIG_CMD_ACCEL_INFO) int accel_disp;
 
 #define SENSOR_ACTIVE(_sensor) (sensor_active & (_sensor)->active_mask)
 
-/*
- * Adjustment in us to ec rate when calculating interrupt interval:
- * To be sure the EC will send an interrupt even if it finishes processing
- * events slightly earlier than the previous period.
- */
-#define MOTION_SENSOR_INT_ADJUSTMENT_US 10
-
-struct mutex g_sensor_mutex;
+mutex_t g_sensor_mutex;
 
 /*
  * Current power level (S0, S3, S5, ...)
  */
 test_export_static enum chipset_state_mask sensor_active;
 
-#ifdef CONFIG_ACCEL_SPOOF_MODE
-static void print_spoof_mode_status(int id);
-#endif /* defined(CONFIG_ACCEL_SPOOF_MODE) */
+/*
+ * Motion task interval. It does not have to be a global variable,
+ * but it allows to be tested.
+ */
+test_export_static int wait_us;
+
+STATIC_IF(CONFIG_ACCEL_SPOOF_MODE) void print_spoof_mode_status(int id);
+STATIC_IF(CONFIG_GESTURE_DETECTION)
+void check_and_queue_gestures(uint32_t *event);
+STATIC_IF(CONFIG_MOTION_FILL_LPC_SENSE_DATA)
+void update_sense_data(uint8_t *lpc_status, int *psample_id);
 
 /* Flags to control whether to send an ODR change event for a sensor */
-static uint32_t odr_event_required;
+static atomic_t odr_event_required;
 
 /* Whether or not the FIFO interrupt should be enabled (set from the AP). */
 __maybe_unused static int fifo_int_enabled;
 
-static inline int motion_sensor_in_forced_mode(
-		const struct motion_sensor_t *sensor)
+#ifdef CONFIG_ZEPHYR
+static int init_sensor_mutex(void)
+{
+	k_mutex_init(&g_sensor_mutex);
+
+	return 0;
+}
+SYS_INIT(init_sensor_mutex, POST_KERNEL, 50);
+#endif /* CONFIG_ZEPHYR */
+
+#ifdef CONFIG_LID_ANGLE
+__attribute__((weak)) int sensor_board_is_lid_angle_available(void)
+{
+	return 1;
+}
+#endif
+
+static inline int
+motion_sensor_in_forced_mode(const struct motion_sensor_t *sensor)
 {
 #ifdef CONFIG_ACCEL_FORCE_MODE_MASK
 	/* Sensor not in force mode, its irq_handler is getting data. */
@@ -98,8 +107,9 @@ static inline int motion_sensor_in_forced_mode(
 }
 
 /* Minimal amount of time since last collection before triggering a new one */
-static inline int motion_sensor_time_to_read(const timestamp_t *ts,
-		const struct motion_sensor_t *sensor)
+static inline int
+motion_sensor_time_to_read(const timestamp_t *ts,
+			   const struct motion_sensor_t *sensor)
 {
 	if (sensor->collection_rate == 0)
 		return 0;
@@ -112,7 +122,8 @@ static inline int motion_sensor_time_to_read(const timestamp_t *ts,
 			  sensor->next_collection - motion_min_interval);
 }
 
-static enum sensor_config motion_sense_get_ec_config(void)
+STATIC_IF_NOT(CONFIG_ZTEST)
+enum sensor_config motion_sense_get_ec_config(void)
 {
 	switch (sensor_active) {
 	case SENSOR_ACTIVE_S0:
@@ -124,13 +135,15 @@ static enum sensor_config motion_sense_get_ec_config(void)
 	default:
 		CPRINTS("get_ec_config: Invalid active state: %x",
 			sensor_active);
-		return SENSOR_CONFIG_MAX;
+		return SENSOR_CONFIG_EC_S5;
 	}
 }
 /* motion_sense_set_data_rate
  *
  * Set the sensor data rate. It is altered when the AP change the data
  * rate or when the power state changes.
+ *
+ * NOTE: Always run in TASK_ID_MOTIONSENSE task.
  */
 int motion_sense_set_data_rate(struct motion_sensor_t *sensor)
 {
@@ -156,26 +169,27 @@ int motion_sense_set_data_rate(struct motion_sensor_t *sensor)
 	roundup = !!(sensor->config[config_id].odr & ROUND_UP_FLAG);
 
 	ret = sensor->drv->set_data_rate(sensor, odr, roundup);
+
+	if (IS_ENABLED(CONFIG_CONSOLE_VERBOSE))
+		CPRINTS("%s ODR: %d - roundup %d from config %d [AP %d]: %d",
+			sensor->name, odr, roundup, config_id,
+			BASE_ODR(sensor->config[SENSOR_CONFIG_AP].odr), ret);
+	else
+		CPRINTS("%c%d ODR %d rup %d cfg %d AP %d: %d", sensor->name[0],
+			sensor->type, odr, roundup, config_id,
+			BASE_ODR(sensor->config[SENSOR_CONFIG_AP].odr), ret);
+
 	if (ret)
 		return ret;
 
-#ifdef CONFIG_CONSOLE_VERBOSE
-	CPRINTS("%s ODR: %d - roundup %d from config %d [AP %d]",
-		sensor->name, odr, roundup, config_id,
-		BASE_ODR(sensor->config[SENSOR_CONFIG_AP].odr));
-#else
-	CPRINTS("%c%d ODR %d rup %d cfg %d AP %d",
-		sensor->name[0], sensor->type, odr, roundup, config_id,
-		BASE_ODR(sensor->config[SENSOR_CONFIG_AP].odr));
-#endif
 	mutex_lock(&g_sensor_mutex);
+	odr = sensor->drv->get_data_rate(sensor);
 	if (ap_odr_mhz)
 		/*
 		 * In case the AP want to run the sensors faster than it can,
 		 * be sure we don't see the ratio to 0.
 		 */
-		sensor->oversampling_ratio = MAX(1,
-			sensor->drv->get_data_rate(sensor) / ap_odr_mhz);
+		sensor->oversampling_ratio = MAX(1, odr / ap_odr_mhz);
 	else
 		sensor->oversampling_ratio = 0;
 
@@ -183,152 +197,33 @@ int motion_sense_set_data_rate(struct motion_sensor_t *sensor)
 	 * Reset last collection: the last collection may be so much in the past
 	 * it may appear to be in the future.
 	 */
-	odr = sensor->drv->get_data_rate(sensor);
 	sensor->collection_rate = odr > 0 ? SECOND * 1000 / odr : 0;
 	sensor->next_collection = ts.le.lo + sensor->collection_rate;
 	sensor->oversampling = 0;
+	if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
+		motion_sense_set_data_period(sensor - motion_sensors,
+					     sensor->collection_rate);
+	}
 	mutex_unlock(&g_sensor_mutex);
-#ifdef CONFIG_BODY_DETECTION
-	if (sensor - motion_sensors == CONFIG_BODY_DETECTION_SENSOR)
+	if (IS_ENABLED(CONFIG_BODY_DETECTION) &&
+	    (sensor - motion_sensors == CONFIG_BODY_DETECTION_SENSOR))
 		body_detect_reset();
-#endif
-	return 0;
-}
-
-static int motion_sense_set_ec_rate_from_ap(
-		const struct motion_sensor_t *sensor,
-		unsigned int new_rate_us)
-{
-	int odr_mhz = sensor->drv->get_data_rate(sensor);
-
-	if (new_rate_us == 0)
-		return 0;
-	if (motion_sensor_in_forced_mode(sensor))
-		/*
-		 * AP EC sampling rate does not matter: we will collect at the
-		 * requested sensor frequency.
-		 */
-		goto end_set_ec_rate_from_ap;
-	if (odr_mhz == 0)
-		goto end_set_ec_rate_from_ap;
-
-	/*
-	 * If the EC collection rate is close to the sensor data rate,
-	 * given variation from the EC scheduler, it is possible that a sensor
-	 * will not present any measurement for a given time slice, and then 2
-	 * measurement for the next. That will create a large interval between
-	 * 2 measurements.
-	 * To prevent that, increase the EC period by 5% to be sure to get at
-	 * least one measurement at every collection time.
-	 * We will apply that correction only if the ec rate is within 10% of
-	 * the data rate.
-	 */
-	if (SECOND * 1100 / odr_mhz > new_rate_us)
-		new_rate_us = new_rate_us / 100 * 105;
-
-end_set_ec_rate_from_ap:
-	return MAX(new_rate_us, motion_min_interval);
-}
-
-
-/*
- * motion_sense_select_ec_rate
- *
- * Calculate the ec_rate for a given sensor.
- * - sensor: sensor to use
- * - config_id: determine the requester (AP or EC).
- * - interrupt:
- * If interrupt is set: return the sampling rate requested by AP or EC.
- * If interrupt is not set and the sensor is in forced mode,
- * we return the rate needed to probe the sensor at the right ODR.
- * otherwise return the sampling rate requested by AP or EC.
- *
- * return rate in us.
- */
-static int motion_sense_select_ec_rate(
-		const struct motion_sensor_t *sensor,
-		enum sensor_config config_id,
-		int interrupt)
-{
-	if (interrupt == 0 && motion_sensor_in_forced_mode(sensor)) {
-		int rate_mhz = BASE_ODR(sensor->config[config_id].odr);
-		/* we have to run ec at the sensor frequency rate.*/
-		if (rate_mhz > 0)
-			return SECOND * 1000 / rate_mhz;
-		else
-			return 0;
-	} else {
-		return sensor->config[config_id].ec_rate;
-	}
-}
-
-/* motion_sense_ec_rate
- *
- * Calculate the sensor ec rate. It will be use to set the motion task polling
- * rate.
- *
- * Return the EC rate, in us.
- */
-static int motion_sense_ec_rate(struct motion_sensor_t *sensor)
-{
-	int ec_rate = 0, ec_rate_from_cfg;
-
-	/* Check the AP setting first. */
-	if (sensor_active != SENSOR_ACTIVE_S5)
-		ec_rate = motion_sense_select_ec_rate(
-			sensor, SENSOR_CONFIG_AP, 0);
 
-	ec_rate_from_cfg = motion_sense_select_ec_rate(
-			sensor, motion_sense_get_ec_config(), 0);
-
-	if (ec_rate_from_cfg != 0)
-		if (ec_rate == 0 || ec_rate_from_cfg < ec_rate)
-			ec_rate = ec_rate_from_cfg;
-	return ec_rate;
-}
-
-/*
- * motion_sense_set_motion_intervals
- *
- * Set the wake up interval for the motion sense thread.
- * It is set to the highest frequency one of the sensors need to be polled at.
- *
- * Note: Not static to be tested.
- */
-static void motion_sense_set_motion_intervals(void)
-{
-	int i, sensor_ec_rate, ec_int_rate = 0;
-	struct motion_sensor_t *sensor;
-	for (i = 0; i < motion_sensor_count; ++i) {
-		sensor = &motion_sensors[i];
-		/*
-		 * If the sensor is sleeping, no need to check it periodically.
-		 */
-		if ((sensor->state != SENSOR_INITIALIZED) ||
-		    (sensor->drv->get_data_rate(sensor) == 0))
-			continue;
-
-		sensor_ec_rate = motion_sense_select_ec_rate(
-				sensor, SENSOR_CONFIG_AP, 1);
-		if (ec_int_rate == 0 ||
-		    (sensor_ec_rate && sensor_ec_rate < ec_int_rate))
-			ec_int_rate = sensor_ec_rate;
-	}
-
-	ap_event_interval =
-		MAX(0, ec_int_rate - MOTION_SENSOR_INT_ADJUSTMENT_US);
-	/*
-	 * Wake up the motion sense task: we want to sensor task to take
-	 * in account the new period right away.
-	 */
-	task_wake(TASK_ID_MOTIONSENSE);
+	return 0;
 }
 
+/* Note: Always run on HOOK task, trigger by events from CHIPSET task. */
 static inline int motion_sense_init(struct motion_sensor_t *sensor)
 {
 	int ret, cnt = 3;
 
 	BUILD_ASSERT(SENSOR_COUNT < 32);
+#if defined(HAS_TASK_CONSOLE)
+	ASSERT((in_deferred_context()) ||
+	       (task_get_current() == TASK_ID_CONSOLE));
+#elif !defined(CONFIG_ZTEST)
+	ASSERT(in_deferred_context());
+#endif /* HAS_TASK_CONSOLE */
 
 	/* Initialize accelerometers. */
 	do {
@@ -339,7 +234,6 @@ static inline int motion_sense_init(struct motion_sensor_t *sensor)
 		sensor->state = SENSOR_INIT_ERROR;
 	} else {
 		sensor->state = SENSOR_INITIALIZED;
-		motion_sense_set_data_rate(sensor);
 	}
 
 	return ret;
@@ -350,20 +244,19 @@ static inline int motion_sense_init(struct motion_sensor_t *sensor)
  *
  * Called by init routine of each sensors when successful.
  */
-int sensor_init_done(const struct motion_sensor_t *s)
+int sensor_init_done(struct motion_sensor_t *s)
 {
 	int ret;
 
-	ret = s->drv->set_range(s, BASE_RANGE(s->default_range),
-				!!(s->default_range & ROUND_UP_FLAG));
+	ret = s->drv->set_range(s, BASE_RANGE(s->current_range),
+				!!(s->current_range & ROUND_UP_FLAG));
 	if (ret == EC_RES_SUCCESS) {
-#ifdef CONFIG_CONSOLE_VERBOSE
-		CPRINTS("%s: MS Done Init type:0x%X range:%d",
-				s->name, s->type, s->drv->get_range(s));
-#else
-		CPRINTS("%c%d InitDone r:%d", s->name[0], s->type,
-				s->drv->get_range(s));
-#endif
+		if (IS_ENABLED(CONFIG_CONSOLE_VERBOSE))
+			CPRINTS("%s: MS Done Init type:0x%X range:%d", s->name,
+				s->type, s->current_range);
+		else
+			CPRINTS("%c%d InitDone r:%d", s->name[0], s->type,
+				s->current_range);
 	}
 	return ret;
 }
@@ -378,46 +271,136 @@ static void motion_sense_switch_sensor_rate(void)
 {
 	int i, ret;
 	struct motion_sensor_t *sensor;
+	unsigned int sensor_setup_mask = 0;
+
+	ASSERT(in_deferred_context());
+
 	for (i = 0; i < motion_sensor_count; ++i) {
 		sensor = &motion_sensors[i];
 		if (SENSOR_ACTIVE(sensor)) {
-			/* Initialize or just back the odr previously set. */
+			/*
+			 * Initialize or just back the odr/range previously
+			 * set.
+			 */
 			if (sensor->state == SENSOR_INITIALIZED) {
-				motion_sense_set_data_rate(sensor);
+				sensor->drv->set_range(
+					sensor, sensor->current_range, 1);
+				sensor_setup_mask |= BIT(i);
 			} else {
 				ret = motion_sense_init(sensor);
-				if (ret != EC_SUCCESS) {
+				if (ret != EC_SUCCESS)
 					CPRINTS("%s: %d: init failed: %d",
 						sensor->name, i, ret);
-#if defined(CONFIG_TABLET_MODE) && defined(CONFIG_LID_ANGLE)
-					/*
-					 * No tablet mode allowed if an accel
-					 * is not working.
-					 */
-					if (i == CONFIG_LID_ANGLE_SENSOR_BASE ||
-					    i == CONFIG_LID_ANGLE_SENSOR_LID) {
-						tablet_set_mode(0);
-					}
-#endif
-				}
+				else
+					sensor_setup_mask |= BIT(i);
+				/*
+				 * No tablet mode allowed if an accel
+				 * is not working.
+				 */
+				if (IS_ENABLED(CONFIG_TABLET_MODE) &&
+				    IS_ENABLED(CONFIG_LID_ANGLE) &&
+				    (ret != EC_SUCCESS) &&
+				    (i == CONFIG_LID_ANGLE_SENSOR_BASE ||
+				     i == CONFIG_LID_ANGLE_SENSOR_LID))
+					tablet_set_mode(0, TABLET_TRIGGER_LID);
 			}
 		} else {
 			/* The sensors are being powered off */
-			if (sensor->state == SENSOR_INITIALIZED)
+			if (sensor->state == SENSOR_INITIALIZED) {
+				/*
+				 * Use mutex to be sure we are not changing the
+				 * ODR in MOTIONSENSE, in case it is running.
+				 */
+				mutex_lock(&g_sensor_mutex);
+				sensor->collection_rate = 0;
+				mutex_unlock(&g_sensor_mutex);
 				sensor->state = SENSOR_NOT_INITIALIZED;
+			}
+		}
+	}
+	if (sensor_setup_mask) {
+		atomic_or(&odr_event_required, sensor_setup_mask);
+		task_set_event(TASK_ID_MOTIONSENSE,
+			       TASK_EVENT_MOTION_ODR_CHANGE);
+	}
+
+	/* disable the body detection since AP is suspended */
+	if (IS_ENABLED(CONFIG_BODY_DETECTION)) {
+		static bool was_enabled;
+
+		switch (sensor_active) {
+		case SENSOR_ACTIVE_S3:
+			was_enabled = body_detect_get_enable();
+			body_detect_set_enable(false);
+			break;
+		case SENSOR_ACTIVE_S0:
+			/* force to enable the body detection in S0 */
+			if (IS_ENABLED(
+				    CONFIG_BODY_DETECTION_ALWAYS_ENABLE_IN_S0))
+				body_detect_set_enable(true);
+			else
+				body_detect_set_enable(was_enabled);
+			break;
+		default:
+			break;
+		}
+	}
+	/* Forget activities set by the AP */
+	if (IS_ENABLED(CONFIG_GESTURE_DETECTION) &&
+	    (sensor_active == SENSOR_ACTIVE_S5)) {
+		uint32_t enabled = 0, disabled, mask;
+
+		mask = CONFIG_GESTURE_DETECTION_MASK;
+		while (mask) {
+			i = get_next_bit(&mask);
+			sensor = &motion_sensors[i];
+			if (sensor->state != SENSOR_INITIALIZED)
+				continue;
+			sensor->drv->list_activities(sensor, &enabled,
+						     &disabled);
+			/* exclude double tap, it is used internally. */
+			enabled &= ~BIT(MOTIONSENSE_ACTIVITY_DOUBLE_TAP);
+			while (enabled) {
+				int activity = get_next_bit(&enabled);
+
+				sensor->drv->manage_activity(sensor, activity,
+							     0, NULL);
+			}
+			/* Re-enable double tap in case AP disabled it */
+			if (IS_ENABLED(CONFIG_GESTURE_SENSOR_DOUBLE_TAP))
+				sensor->drv->manage_activity(
+					sensor, MOTIONSENSE_ACTIVITY_DOUBLE_TAP,
+					1, NULL);
 		}
 	}
-	motion_sense_set_motion_intervals();
 }
 DECLARE_DEFERRED(motion_sense_switch_sensor_rate);
 
+static void motion_sense_print_stats(const char *event)
+{
+	unsigned int active = 0;
+	unsigned int states = 0;
+	int i;
+
+	for (i = 0; i < motion_sensor_count; i++) {
+		if (motion_sensors[i].active_mask)
+			active |= BIT(i);
+		/* States fit in 2 bits but we'll give them 4 for readbility */
+		states |= motion_sensors[i].state << (4 * i);
+	}
+
+	CPRINTS("Motion pre-%s; loops %u; last %u ms ago; a=0x%x, s=0x%x",
+		event, (unsigned int)motion_sense_task_loops,
+		(unsigned int)(get_time().val - ts_begin_task.val) / 1000,
+		active, states);
+}
+
 static void motion_sense_shutdown(void)
 {
 	int i;
 	struct motion_sensor_t *sensor;
-#ifdef CONFIG_GESTURE_DETECTION_MASK
-	uint32_t enabled = 0, disabled, mask;
-#endif
+
+	motion_sense_print_stats("shutdown");
 
 	sensor_active = SENSOR_ACTIVE_S5;
 	for (i = 0; i < motion_sensor_count; i++) {
@@ -425,40 +408,22 @@ static void motion_sense_shutdown(void)
 		/* Forget about changes made by the AP */
 		sensor->config[SENSOR_CONFIG_AP].odr = 0;
 		sensor->config[SENSOR_CONFIG_AP].ec_rate = 0;
+		sensor->current_range = sensor->default_range;
 	}
-	motion_sense_switch_sensor_rate();
 
-	/* Forget activities set by the AP */
-#ifdef CONFIG_GESTURE_DETECTION_MASK
-	mask = CONFIG_GESTURE_DETECTION_MASK;
-	while (mask) {
-		i = get_next_bit(&mask);
-		sensor = &motion_sensors[i];
-		if (sensor->state != SENSOR_INITIALIZED)
-			continue;
-		sensor->drv->list_activities(sensor,
-				&enabled, &disabled);
-		/* exclude double tap, it is used internally. */
-		enabled &= ~BIT(MOTIONSENSE_ACTIVITY_DOUBLE_TAP);
-		while (enabled) {
-			int activity = get_next_bit(&enabled);
-			sensor->drv->manage_activity(sensor, activity, 0, NULL);
-		}
-		/* Re-enable double tap in case AP disabled it */
-		sensor->drv->manage_activity(sensor,
-				MOTIONSENSE_ACTIVITY_DOUBLE_TAP, 1, NULL);
-	}
-#endif
-#ifdef CONFIG_BODY_DETECTION
-	/* disable the body detection since motion sensor is down */
-	body_detect_set_enable(false);
-#endif
+	/*
+	 * Run motion_sense_switch_sensor_rate_data in the HOOK task,
+	 * To be sure no 2 rate changes happens in parralell.
+	 */
+	hook_call_deferred(&motion_sense_switch_sensor_rate_data, 0);
 }
 DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, motion_sense_shutdown,
 	     MOTION_SENSE_HOOK_PRIO);
 
 static void motion_sense_suspend(void)
 {
+	motion_sense_print_stats("suspend");
+
 	/*
 	 *  If we are coming from S5, don't enter suspend:
 	 *  We will go in SO almost immediately.
@@ -468,10 +433,6 @@ static void motion_sense_suspend(void)
 
 	sensor_active = SENSOR_ACTIVE_S3;
 
-#ifdef CONFIG_BODY_DETECTION
-	/* disable the body detection since motion sensor is suspended */
-	body_detect_set_enable(false);
-#endif
 	/*
 	 * During shutdown sequence sensor rails can be powered down
 	 * asynchronously to the EC hence EC cannot interlock the sensor
@@ -492,12 +453,13 @@ DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, motion_sense_suspend,
 
 static void motion_sense_resume(void)
 {
+	motion_sense_print_stats("resume");
+
 	sensor_active = SENSOR_ACTIVE_S0;
 	hook_call_deferred(&motion_sense_switch_sensor_rate_data,
 			   CONFIG_MOTION_SENSE_RESUME_DELAY_US);
 }
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, motion_sense_resume,
-	     MOTION_SENSE_HOOK_PRIO);
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, motion_sense_resume, MOTION_SENSE_HOOK_PRIO);
 
 static void motion_sense_startup(void)
 {
@@ -513,8 +475,7 @@ static void motion_sense_startup(void)
 	if (chipset_in_state(SENSOR_ACTIVE_S0))
 		motion_sense_resume();
 }
-DECLARE_HOOK(HOOK_INIT, motion_sense_startup,
-	     MOTION_SENSE_HOOK_PRIO);
+DECLARE_HOOK(HOOK_INIT, motion_sense_startup, MOTION_SENSE_HOOK_PRIO);
 
 /* Write to LPC status byte to represent that accelerometers are present. */
 static inline void set_present(uint8_t *lpc_status)
@@ -524,13 +485,10 @@ static inline void set_present(uint8_t *lpc_status)
 
 #ifdef CONFIG_MOTION_FILL_LPC_SENSE_DATA
 /* Update/Write LPC data */
-static inline void update_sense_data(uint8_t *lpc_status, int *psample_id)
+static void update_sense_data(uint8_t *lpc_status, int *psample_id)
 {
 	int s, d, i;
 	int16_t *lpc_data = (int16_t *)host_get_memmap(EC_MEMMAP_ACC_DATA);
-#if (!defined HAS_TASK_ALS) && (defined CONFIG_ALS)
-	uint16_t *lpc_als = (uint16_t *)host_get_memmap(EC_MEMMAP_ALS);
-#endif
 	struct motion_sensor_t *sensor;
 	/*
 	 * Set the busy bit before writing the sensor data. Increment
@@ -549,11 +507,11 @@ static inline void update_sense_data(uint8_t *lpc_status, int *psample_id)
 	 * with uncalibrated accelerometers. The AP calculates a separate,
 	 * more accurate lid angle.
 	 */
-#ifdef CONFIG_LID_ANGLE
-	lpc_data[0] = motion_lid_get_angle();
-#else
-	lpc_data[0] = LID_ANGLE_UNRELIABLE;
-#endif
+	if (IS_ENABLED(CONFIG_LID_ANGLE))
+		lpc_data[0] = motion_lid_get_angle();
+	else
+		lpc_data[0] = LID_ANGLE_UNRELIABLE;
+
 	/*
 	 * The first 2 entries must be accelerometers, then gyroscope.
 	 * If there is only one accel and one gyro, the entry for the second
@@ -570,45 +528,40 @@ static inline void update_sense_data(uint8_t *lpc_status, int *psample_id)
 			lpc_data[1 + i + 3 * d] =
 				ec_motion_sensor_clamp_i16(sensor->xyz[i]);
 	}
+	if (!IS_ENABLED(HAS_TASK_ALS) && IS_ENABLED(CONFIG_ALS)) {
+		uint16_t *lpc_als = (uint16_t *)host_get_memmap(EC_MEMMAP_ALS);
 
-#if (!defined HAS_TASK_ALS) && (defined CONFIG_ALS)
-	for (i = 0; i < EC_ALS_ENTRIES && i < ALS_COUNT; i++)
-		lpc_als[i] = ec_motion_sensor_clamp_u16(
+		for (i = 0; i < EC_ALS_ENTRIES && i < ALS_COUNT; i++)
+			lpc_als[i] = ec_motion_sensor_clamp_u16(
 				motion_als_sensors[i]->xyz[X]);
-#endif
+	}
 
 	/*
 	 * Increment sample id and clear busy bit to signal we finished
 	 * updating data.
 	 */
-	*psample_id = (*psample_id + 1) &
-			EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK;
+	*psample_id = (*psample_id + 1) & EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK;
 	*lpc_status = EC_MEMMAP_ACC_STATUS_PRESENCE_BIT | *psample_id;
 }
 #endif
 
 static int motion_sense_read(struct motion_sensor_t *sensor)
 {
-	if (sensor->state != SENSOR_INITIALIZED)
-		return EC_ERROR_UNKNOWN;
-
-	if (sensor->drv->get_data_rate(sensor) == 0)
-		return EC_ERROR_NOT_POWERED;
+	ASSERT(sensor->state == SENSOR_INITIALIZED);
+	ASSERT(sensor->drv->get_data_rate(sensor) != 0);
 
-#ifdef CONFIG_ACCEL_SPOOF_MODE
 	/*
 	 * If the sensor is in spoof mode, the readings are already present in
 	 * spoof_xyz.
 	 */
-	if (sensor->flags & MOTIONSENSE_FLAG_IN_SPOOF_MODE)
+	if (IS_ENABLED(CONFIG_ACCEL_SPOOF_MODE) &&
+	    (sensor->flags & MOTIONSENSE_FLAG_IN_SPOOF_MODE))
 		return EC_SUCCESS;
-#endif /* defined(CONFIG_ACCEL_SPOOF_MODE) */
 
 	/* Otherwise, read all raw X,Y,Z accelerations. */
 	return sensor->drv->read(sensor, sensor->raw_xyz);
 }
 
-
 static inline void increment_sensor_collection(struct motion_sensor_t *sensor,
 					       const timestamp_t *ts)
 {
@@ -638,7 +591,7 @@ static inline void increment_sensor_collection(struct motion_sensor_t *sensor,
  *
  * @param s Pointer to the sensor.
  */
-static void motion_sense_push_raw_xyz(struct motion_sensor_t *s)
+void motion_sense_push_raw_xyz(struct motion_sensor_t *s)
 {
 	if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
 		struct ec_response_motion_sensor_data vector;
@@ -666,8 +619,7 @@ static void motion_sense_push_raw_xyz(struct motion_sensor_t *s)
 	}
 }
 
-static int motion_sense_process(struct motion_sensor_t *sensor,
-				uint32_t *event,
+static int motion_sense_process(struct motion_sensor_t *sensor, uint32_t *event,
 				const timestamp_t *ts)
 {
 	int ret = EC_SUCCESS;
@@ -675,28 +627,33 @@ static int motion_sense_process(struct motion_sensor_t *sensor,
 	int has_data_read = 0;
 	int sensor_num = sensor - motion_sensors;
 
+	ASSERT(task_get_current() == TASK_ID_MOTIONSENSE);
+
 	if (*event & TASK_EVENT_MOTION_ODR_CHANGE) {
 		const int sensor_bit = 1 << sensor_num;
-		int odr_pending =
-			deprecated_atomic_read_clear(&odr_event_required);
+		int odr_pending = atomic_clear(&odr_event_required);
 
 		is_odr_pending = odr_pending & sensor_bit;
 		odr_pending &= ~sensor_bit;
-		deprecated_atomic_or(&odr_event_required, odr_pending);
+		atomic_or(&odr_event_required, odr_pending);
 	}
 
-#ifdef CONFIG_ACCEL_INTERRUPTS
 	if ((*event & TASK_EVENT_MOTION_INTERRUPT_MASK || is_odr_pending) &&
 	    (sensor->drv->irq_handler != NULL)) {
 		ret = sensor->drv->irq_handler(sensor, event);
 		if (ret == EC_SUCCESS)
 			has_data_read = 1;
 	}
-#endif /* CONFIG_ACCEL_INTERRUPTS */
 	if (motion_sensor_in_forced_mode(sensor)) {
 		if (motion_sensor_time_to_read(ts, sensor)) {
-			ret = motion_sense_read(sensor);
+			/*
+			 * Since motion_sense_read can sleep, other task may be
+			 * scheduled. In particular if suspend is called by
+			 * HOOKS task, it may set colleciton_rate to 0 and we
+			 * would crash in increment_sensor_collection.
+			 */
 			increment_sensor_collection(sensor, ts);
+			ret = motion_sense_read(sensor);
 		} else {
 			ret = EC_ERROR_BUSY;
 		}
@@ -708,148 +665,123 @@ static int motion_sense_process(struct motion_sensor_t *sensor,
 	}
 	if (IS_ENABLED(CONFIG_ACCEL_FIFO) &&
 	    *event & TASK_EVENT_MOTION_FLUSH_PENDING) {
-		int flush_pending =
-			deprecated_atomic_read_clear(&sensor->flush_pending);
+		int flush_pending = atomic_clear(&sensor->flush_pending);
 
 		for (; flush_pending > 0; flush_pending--) {
-			motion_sense_fifo_insert_async_event(
-				sensor, ASYNC_EVENT_FLUSH);
+			motion_sense_fifo_insert_async_event(sensor,
+							     ASYNC_EVENT_FLUSH);
 		}
 	}
 
 	/* ODR change was requested. */
 	if (is_odr_pending) {
 		motion_sense_set_data_rate(sensor);
-		motion_sense_set_motion_intervals();
 		if (IS_ENABLED(CONFIG_ACCEL_FIFO))
-			motion_sense_fifo_insert_async_event(
-				sensor, ASYNC_EVENT_ODR);
+			motion_sense_fifo_insert_async_event(sensor,
+							     ASYNC_EVENT_ODR);
 	}
 	if (has_data_read) {
-#ifdef CONFIG_GESTURE_SW_DETECTION
 		/* Run gesture recognition engine */
-		if (sensor_num == CONFIG_GESTURE_SENSOR_DOUBLE_TAP)
+		if (IS_ENABLED(CONFIG_GESTURE_SW_DETECTION) &&
+		    (sensor_num == CONFIG_GESTURE_TAP_SENSOR))
 			gesture_calc(event);
-#endif
-#ifdef CONFIG_BODY_DETECTION
-		if (sensor_num == CONFIG_BODY_DETECTION_SENSOR)
+		if (IS_ENABLED(CONFIG_BODY_DETECTION) &&
+		    (sensor_num == CONFIG_BODY_DETECTION_SENSOR))
 			body_detect();
-#endif
 	}
 	return ret;
 }
 
-#ifdef CONFIG_ORIENTATION_SENSOR
-enum motionsensor_orientation motion_sense_remap_orientation(
-		const struct motion_sensor_t *s,
-		enum motionsensor_orientation orientation)
-{
-	enum motionsensor_orientation rotated_orientation;
-	const intv3_t *orientation_v;
-	intv3_t rotated_orientation_v;
-
-	if (orientation == MOTIONSENSE_ORIENTATION_UNKNOWN)
-		return MOTIONSENSE_ORIENTATION_UNKNOWN;
-
-	orientation_v = &orientation_modes[orientation];
-	rotate(*orientation_v, *s->rot_standard_ref, rotated_orientation_v);
-	rotated_orientation = ((2 * rotated_orientation_v[1] +
-			rotated_orientation_v[0] + 4) % 5);
-	return rotated_orientation;
-}
-#endif
-
 #ifdef CONFIG_GESTURE_DETECTION
 static void check_and_queue_gestures(uint32_t *event)
 {
-#ifdef CONFIG_ORIENTATION_SENSOR
-	const struct motion_sensor_t *sensor;
-#endif
+	if (IS_ENABLED(CONFIG_GESTURE_SENSOR_DOUBLE_TAP) &&
+	    (*event & TASK_EVENT_MOTION_ACTIVITY_INTERRUPT(
+			      MOTIONSENSE_ACTIVITY_DOUBLE_TAP))) {
+		if (IS_ENABLED(CONFIG_GESTURE_HOST_DETECTION)) {
+			struct ec_response_motion_sensor_data vector;
 
-#ifdef CONFIG_GESTURE_SENSOR_DOUBLE_TAP
-	if (*event & TASK_EVENT_MOTION_ACTIVITY_INTERRUPT(
-				MOTIONSENSE_ACTIVITY_DOUBLE_TAP)) {
-#ifdef CONFIG_GESTURE_HOST_DETECTION
-		struct ec_response_motion_sensor_data vector;
-
-		/*
-		 * Send events to the FIFO
-		 * AP is ignoring double tap event, do no wake up and no
-		 * automatic disable.
-		 */
-#ifdef CONFIG_GESTURE_SENSOR_DOUBLE_TAP_FOR_HOST
-		vector.flags = MOTIONSENSE_SENSOR_FLAG_WAKEUP;
-#else
-		vector.flags = 0;
-#endif
-		vector.activity = MOTIONSENSE_ACTIVITY_DOUBLE_TAP;
-		vector.state = 1; /* triggered */
-		vector.sensor_num = MOTION_SENSE_ACTIVITY_SENSOR_ID;
-		motion_sense_fifo_stage_data(&vector, NULL, 0,
-					     __hw_clock_source_read());
-		motion_sense_fifo_commit_data();
-#endif
+			vector.flags = MOTIONSENSE_SENSOR_FLAG_BYPASS_FIFO;
+			/*
+			 * Send events to the FIFO
+			 * AP is ignoring double tap event, do no wake up and no
+			 * automatic disable.
+			 */
+			if (IS_ENABLED(
+				    CONFIG_GESTURE_SENSOR_DOUBLE_TAP_FOR_HOST))
+				vector.flags |= MOTIONSENSE_SENSOR_FLAG_WAKEUP;
+			vector.activity_data.activity =
+				MOTIONSENSE_ACTIVITY_DOUBLE_TAP;
+			vector.activity_data.state = 1 /* triggered */;
+			vector.sensor_num = MOTION_SENSE_ACTIVITY_SENSOR_ID;
+			motion_sense_fifo_stage_data(&vector, NULL, 0,
+						     __hw_clock_source_read());
+			motion_sense_fifo_commit_data();
+		}
 		/* Call board specific function to process tap */
 		sensor_board_proc_double_tap();
 	}
-#endif
-#ifdef CONFIG_GESTURE_SIGMO
-	if (*event & TASK_EVENT_MOTION_ACTIVITY_INTERRUPT(
-				MOTIONSENSE_ACTIVITY_SIG_MOTION)) {
+	if (IS_ENABLED(CONFIG_GESTURE_SIGMO) &&
+	    (*event & TASK_EVENT_MOTION_ACTIVITY_INTERRUPT(
+			      MOTIONSENSE_ACTIVITY_SIG_MOTION))) {
 		struct motion_sensor_t *activity_sensor;
-#ifdef CONFIG_GESTURE_HOST_DETECTION
-		struct ec_response_motion_sensor_data vector;
-
-		/* Send events to the FIFO */
-		vector.flags = MOTIONSENSE_SENSOR_FLAG_WAKEUP;
-		vector.activity = MOTIONSENSE_ACTIVITY_SIG_MOTION;
-		vector.state = 1; /* triggered */
-		vector.sensor_num = MOTION_SENSE_ACTIVITY_SENSOR_ID;
-		motion_sense_fifo_stage_data(&vector, NULL, 0,
-				__hw_clock_source_read());
-		motion_sense_fifo_commit_data();
-#endif
+		if (IS_ENABLED(CONFIG_GESTURE_HOST_DETECTION)) {
+			struct ec_response_motion_sensor_data vector;
+
+			/* Send events to the FIFO */
+			vector.flags = MOTIONSENSE_SENSOR_FLAG_WAKEUP |
+				       MOTIONSENSE_SENSOR_FLAG_BYPASS_FIFO;
+			vector.activity_data.activity =
+				MOTIONSENSE_ACTIVITY_SIG_MOTION;
+			vector.activity_data.state = 1 /* triggered */;
+			vector.sensor_num = MOTION_SENSE_ACTIVITY_SENSOR_ID;
+			motion_sense_fifo_stage_data(&vector, NULL, 0,
+						     __hw_clock_source_read());
+			motion_sense_fifo_commit_data();
+		}
 		/* Disable further detection */
-		activity_sensor = &motion_sensors[CONFIG_GESTURE_SIGMO];
+		activity_sensor = &motion_sensors[CONFIG_GESTURE_SIGMO_SENSOR];
 		activity_sensor->drv->manage_activity(
-				activity_sensor,
-				MOTIONSENSE_ACTIVITY_SIG_MOTION,
-				0, NULL);
+			activity_sensor, MOTIONSENSE_ACTIVITY_SIG_MOTION, 0,
+			NULL);
 	}
-#endif
-
-#ifdef CONFIG_ORIENTATION_SENSOR
-	sensor = &motion_sensors[LID_ACCEL];
-	if (SENSOR_ACTIVE(sensor) && (sensor->state == SENSOR_INITIALIZED)) {
-		struct ec_response_motion_sensor_data vector = {
-			.flags = 0,
-			.activity = MOTIONSENSE_ACTIVITY_ORIENTATION,
-			.sensor_num = MOTION_SENSE_ACTIVITY_SENSOR_ID,
-		};
-
-		mutex_lock(sensor->mutex);
-		if (ORIENTATION_CHANGED(sensor) && (GET_ORIENTATION(sensor) !=
-				MOTIONSENSE_ORIENTATION_UNKNOWN)) {
-			SET_ORIENTATION_UPDATED(sensor);
-			vector.state = GET_ORIENTATION(sensor);
-			motion_sense_fifo_add_data(&vector, NULL, 0,
-						   __hw_clock_source_read());
-#ifdef CONFIG_DEBUG_ORIENTATION
-			{
-				static const char * const mode_strs[] = {
-						"Landscape",
-						"Portrait",
-						"Inv_Portrait",
-						"Inv_Landscape",
+	if (IS_ENABLED(CONFIG_ORIENTATION_SENSOR)) {
+		const struct motion_sensor_t *sensor =
+			&motion_sensors[LID_ACCEL];
+
+		if (SENSOR_ACTIVE(sensor) &&
+		    (sensor->state == SENSOR_INITIALIZED)) {
+			struct ec_response_motion_sensor_data vector = {
+				.flags = 0,
+				.activity_data.activity =
+					MOTIONSENSE_ACTIVITY_ORIENTATION,
+				.sensor_num = MOTION_SENSE_ACTIVITY_SENSOR_ID,
+			};
+
+			mutex_lock(sensor->mutex);
+			if (motion_orientation_changed(sensor) &&
+			    (*motion_orientation_ptr(sensor) !=
+			     MOTIONSENSE_ORIENTATION_UNKNOWN)) {
+				motion_orientation_update(sensor);
+				vector.activity_data.state =
+					*motion_orientation_ptr(sensor);
+				motion_sense_fifo_stage_data(
+					&vector, NULL, 0,
+					__hw_clock_source_read());
+				motion_sense_fifo_commit_data();
+				if (IS_ENABLED(CONFIG_DEBUG_ORIENTATION)) {
+					static const char *const mode[] = {
+						"Landscape", "Portrait",
+						"Inv_Portrait", "Inv_Landscape",
 						"Unknown"
-				};
-				CPRINTS(mode_strs[GET_ORIENTATION(sensor)]);
+					};
+					CPRINTS("%s",
+						mode[vector.activity_data.state]);
+				}
 			}
-#endif
+			mutex_unlock(sensor->mutex);
 		}
-		mutex_unlock(sensor->mutex);
 	}
-#endif
 }
 #endif
 
@@ -862,34 +794,27 @@ static void check_and_queue_gestures(uint32_t *event)
  */
 void motion_sense_task(void *u)
 {
-	int i, ret, wait_us;
-	timestamp_t ts_begin_task, ts_end_task;
+	int i, ret, sample_id = 0;
+	timestamp_t ts_end_task;
 	int32_t time_diff;
 	uint32_t event = 0;
 	uint16_t ready_status = 0;
 	struct motion_sensor_t *sensor;
-#ifdef CONFIG_LID_ANGLE
-	const uint16_t lid_angle_sensors = (BIT(CONFIG_LID_ANGLE_SENSOR_BASE)|
-					    BIT(CONFIG_LID_ANGLE_SENSOR_LID));
-#endif
-	timestamp_t ts_last_int;
-#ifdef CONFIG_MOTION_FILL_LPC_SENSE_DATA
-	int sample_id = 0;
 	uint8_t *lpc_status;
 
-	lpc_status = host_get_memmap(EC_MEMMAP_ACC_STATUS);
-	set_present(lpc_status);
-#endif
+	if (IS_ENABLED(CONFIG_MOTION_FILL_LPC_SENSE_DATA)) {
+		lpc_status = host_get_memmap(EC_MEMMAP_ACC_STATUS);
+		set_present(lpc_status);
+	}
 
 	if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
 		motion_sense_fifo_init();
-		ts_last_int = get_time();
 	}
 
 	while (1) {
 		ts_begin_task = get_time();
+		atomic_add(&motion_sense_task_loops, 1);
 		for (i = 0; i < motion_sensor_count; ++i) {
-
 			sensor = &motion_sensors[i];
 
 			/* if the sensor is active in the current power state */
@@ -899,46 +824,46 @@ void motion_sense_task(void *u)
 				}
 
 				ret = motion_sense_process(sensor, &event,
-						&ts_begin_task);
+							   &ts_begin_task);
 				if (ret != EC_SUCCESS)
 					continue;
 				ready_status |= BIT(i);
 			}
 		}
-#ifdef CONFIG_GESTURE_DETECTION
-		check_and_queue_gestures(&event);
-#endif
-#ifdef CONFIG_LID_ANGLE
-		/*
-		 * Check to see that the sensors required for lid angle
-		 * calculation are ready.
-		 */
-		ready_status &= lid_angle_sensors;
-		if (ready_status == lid_angle_sensors) {
-			motion_lid_calc();
-			ready_status = 0;
+		if (IS_ENABLED(CONFIG_GESTURE_DETECTION))
+			check_and_queue_gestures(&event);
+		if (IS_ENABLED(CONFIG_LID_ANGLE)) {
+			const uint16_t lid_angle_sensors =
+				BIT(CONFIG_LID_ANGLE_SENSOR_BASE) |
+				BIT(CONFIG_LID_ANGLE_SENSOR_LID);
+
+			/*
+			 * Check to see that the sensors required for lid angle
+			 * calculation are ready.
+			 */
+			ready_status &= lid_angle_sensors;
+			if (ready_status == lid_angle_sensors) {
+				motion_lid_calc();
+				ready_status = 0;
+			}
 		}
-#endif
-#ifdef CONFIG_CMD_ACCEL_INFO
-		if (accel_disp) {
-			CPRINTF("[%pT event 0x%08x ",
-				PRINTF_TIMESTAMP_NOW, event);
+		if (IS_ENABLED(CONFIG_CMD_ACCEL_INFO) && (accel_disp)) {
+			char ts_str[PRINTF_TIMESTAMP_BUF_SIZE];
+
+			snprintf_timestamp_now(ts_str, sizeof(ts_str));
+			CPRINTF("[%s event 0x%08x ", ts_str, event);
 			for (i = 0; i < motion_sensor_count; ++i) {
 				sensor = &motion_sensors[i];
 				CPRINTF("%s=%-5d, %-5d, %-5d ", sensor->name,
-					sensor->xyz[X],
-					sensor->xyz[Y],
+					sensor->xyz[X], sensor->xyz[Y],
 					sensor->xyz[Z]);
 			}
-#ifdef CONFIG_LID_ANGLE
-			CPRINTF("a=%-4d", motion_lid_get_angle());
-#endif
+			if (IS_ENABLED(CONFIG_LID_ANGLE))
+				CPRINTF("a=%-4d", motion_lid_get_angle());
 			CPRINTF("]\n");
 		}
-#endif
-#ifdef CONFIG_MOTION_FILL_LPC_SENSE_DATA
-		update_sense_data(lpc_status, &sample_id);
-#endif
+		if (IS_ENABLED(CONFIG_MOTION_FILL_LPC_SENSE_DATA))
+			update_sense_data(lpc_status, &sample_id);
 
 		/*
 		 * Ask the host to flush the queue if
@@ -947,32 +872,28 @@ void motion_sense_task(void *u)
 		 * - we haven't done it for a while.
 		 */
 		if (IS_ENABLED(CONFIG_ACCEL_FIFO) &&
-		    (motion_sense_fifo_wake_up_needed() ||
+		    (motion_sense_fifo_bypass_needed() ||
+		     motion_sense_fifo_interrupt_needed() ||
 		     event & (TASK_EVENT_MOTION_ODR_CHANGE |
 			      TASK_EVENT_MOTION_FLUSH_PENDING) ||
-		     motion_sense_fifo_over_thres() ||
-		     (ap_event_interval > 0 &&
-		      time_after(ts_begin_task.le.lo,
-				 ts_last_int.le.lo + ap_event_interval)))) {
+		     motion_sense_fifo_over_thres())) {
 			if ((event & TASK_EVENT_MOTION_FLUSH_PENDING) == 0) {
 				motion_sense_fifo_add_timestamp(
 					__hw_clock_source_read());
 			}
-			ts_last_int = ts_begin_task;
-#ifdef CONFIG_MKBP_EVENT
 			/*
 			 * Send an event if we know we are in S0 and the kernel
 			 * driver is listening, or the AP needs to be waken up.
 			 * In the latter case, the driver pulls the event and
 			 * will resume listening until it is suspended again.
 			 */
-			if ((fifo_int_enabled &&
-			     sensor_active == SENSOR_ACTIVE_S0) ||
-			    motion_sense_fifo_wake_up_needed()) {
+			if ((IS_ENABLED(CONFIG_MKBP_EVENT) &&
+			     ((fifo_int_enabled &&
+			       sensor_active == SENSOR_ACTIVE_S0) ||
+			      motion_sense_fifo_wake_up_needed()))) {
 				mkbp_send_event(EC_MKBP_EVENT_SENSOR_FIFO);
-				motion_sense_fifo_reset_wake_up_needed();
 			}
-#endif /* CONFIG_MKBP_EVENT */
+			motion_sense_fifo_reset_needed_flags();
 		}
 
 		ts_end_task = get_time();
@@ -982,7 +903,7 @@ void motion_sense_task(void *u)
 			struct motion_sensor_t *sensor = &motion_sensors[i];
 
 			if (!motion_sensor_in_forced_mode(sensor) ||
-			   sensor->collection_rate == 0)
+			    sensor->collection_rate == 0)
 				continue;
 
 			time_diff = time_until(ts_end_task.le.lo,
@@ -1000,9 +921,9 @@ void motion_sense_task(void *u)
 
 		if (wait_us >= 0 && wait_us < motion_min_interval) {
 			/*
-			* Guarantee some minimum delay to allow other lower
-			* priority tasks to run.
-			*/
+			 * Guarantee some minimum delay to allow other lower
+			 * priority tasks to run.
+			 */
 			wait_us = motion_min_interval;
 		}
 
@@ -1014,8 +935,7 @@ void motion_sense_task(void *u)
 /* Host commands */
 
 /* Function to map host sensor IDs to motion sensor. */
-static struct motion_sensor_t
-	*host_sensor_id_to_real_sensor(int host_id)
+static struct motion_sensor_t *host_sensor_id_to_real_sensor(int host_id)
 {
 	struct motion_sensor_t *sensor;
 
@@ -1031,18 +951,13 @@ static struct motion_sensor_t
 	return NULL;
 }
 
-static struct motion_sensor_t
-	*host_sensor_id_to_motion_sensor(int host_id)
+static struct motion_sensor_t *host_sensor_id_to_motion_sensor(int host_id)
 {
-#ifdef CONFIG_GESTURE_HOST_DETECTION
-	if (host_id == MOTION_SENSE_ACTIVITY_SENSOR_ID)
-		/*
-		 * Return the info for the first sensor that
-		 * support some gestures.
-		 */
+	/* Return the info for the first sensor that support some gestures. */
+	if (IS_ENABLED(CONFIG_GESTURE_HOST_DETECTION) &&
+	    (host_id == MOTION_SENSE_ACTIVITY_SENSOR_ID))
 		return host_sensor_id_to_real_sensor(
 			__builtin_ctz(CONFIG_GESTURE_DETECTION_MASK));
-#endif
 	return host_sensor_id_to_real_sensor(host_id);
 }
 
@@ -1052,13 +967,20 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 	struct ec_response_motion_sense *out = args->response;
 	struct motion_sensor_t *sensor;
 	int i, ret = EC_RES_INVALID_PARAM, reported;
+	const void *in_offset;
+	const void *in_scale;
+	void *out_calib_read;
+	void *out_scale;
+	void *out_offset;
+	int16_t out_temp;
 
 	switch (in->cmd) {
 	case MOTIONSENSE_CMD_DUMP:
 		out->dump.module_flags =
 			(*(host_get_memmap(EC_MEMMAP_ACC_STATUS)) &
 			 EC_MEMMAP_ACC_STATUS_PRESENCE_BIT) ?
-			MOTIONSENSE_MODULE_FLAG_ACTIVE : 0;
+				MOTIONSENSE_MODULE_FLAG_ACTIVE :
+				0;
 		out->dump.sensor_count = ALL_MOTION_SENSORS;
 		args->response_size = sizeof(out->dump);
 		reported = MIN(ALL_MOTION_SENSORS, in->dump.max_sensor_count);
@@ -1076,13 +998,14 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 			}
 		}
 		mutex_unlock(&g_sensor_mutex);
-		args->response_size += reported *
+		args->response_size +=
+			reported *
 			sizeof(struct ec_response_motion_sensor_data);
 		break;
 
 	case MOTIONSENSE_CMD_DATA:
 		sensor = host_sensor_id_to_real_sensor(
-				in->sensor_odr.sensor_num);
+			in->sensor_odr.sensor_num);
 		if (sensor == NULL)
 			return EC_RES_INVALID_PARAM;
 
@@ -1097,16 +1020,16 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 
 	case MOTIONSENSE_CMD_INFO:
 		sensor = host_sensor_id_to_motion_sensor(
-				in->sensor_odr.sensor_num);
+			in->sensor_odr.sensor_num);
 		if (sensor == NULL)
 			return EC_RES_INVALID_PARAM;
 
-#ifdef CONFIG_GESTURE_HOST_DETECTION
-		if (in->sensor_odr.sensor_num ==
-		    MOTION_SENSE_ACTIVITY_SENSOR_ID)
+		if (IS_ENABLED(CONFIG_GESTURE_HOST_DETECTION) &&
+		    MOTION_SENSE_ACTIVITY_SENSOR_ID >= 0 &&
+		    (in->sensor_odr.sensor_num ==
+		     MOTION_SENSE_ACTIVITY_SENSOR_ID))
 			out->info.type = MOTIONSENSE_TYPE_ACTIVITY;
 		else
-#endif
 			out->info.type = sensor->type;
 
 		out->info.location = sensor->location;
@@ -1116,7 +1039,8 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 		if (args->version >= 3) {
 			out->info_3.min_frequency = sensor->min_frequency;
 			out->info_3.max_frequency = sensor->max_frequency;
-			out->info_3.fifo_max_event_count = MAX_FIFO_EVENT_COUNT;
+			out->info_3.fifo_max_event_count =
+				CONFIG_ACCEL_FIFO_SIZE;
 			args->response_size = sizeof(out->info_3);
 		}
 		if (args->version >= 4) {
@@ -1129,8 +1053,7 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 		break;
 
 	case MOTIONSENSE_CMD_EC_RATE:
-		sensor = host_sensor_id_to_real_sensor(
-				in->sensor_odr.sensor_num);
+		sensor = host_sensor_id_to_real_sensor(in->ec_rate.sensor_num);
 		if (sensor == NULL)
 			return EC_RES_INVALID_PARAM;
 
@@ -1139,18 +1062,20 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 		 * has a value.
 		 */
 		if (in->ec_rate.data != EC_MOTION_SENSE_NO_VALUE) {
-			sensor->config[SENSOR_CONFIG_AP].ec_rate =
-				motion_sense_set_ec_rate_from_ap(
-					sensor, in->ec_rate.data * MSEC);
-			/* Bound the new sampling rate. */
-			motion_sense_set_motion_intervals();
+			int new_ec_rate = in->ec_rate.data * MSEC;
+
+			if (new_ec_rate > 0)
+				new_ec_rate =
+					MAX(new_ec_rate, motion_min_interval);
+			sensor->config[SENSOR_CONFIG_AP].ec_rate = new_ec_rate;
 
 			/* Force a collection to purge old events.  */
 			task_set_event(TASK_ID_MOTIONSENSE,
-					TASK_EVENT_MOTION_ODR_CHANGE, 0);
+				       TASK_EVENT_MOTION_ODR_CHANGE);
 		}
 
-		out->ec_rate.ret = motion_sense_ec_rate(sensor) / MSEC;
+		out->ec_rate.ret =
+			sensor->config[SENSOR_CONFIG_AP].ec_rate / MSEC;
 
 		args->response_size = sizeof(out->ec_rate);
 		break;
@@ -1158,7 +1083,7 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 	case MOTIONSENSE_CMD_SENSOR_ODR:
 		/* Verify sensor number is valid. */
 		sensor = host_sensor_id_to_real_sensor(
-				in->sensor_odr.sensor_num);
+			in->sensor_odr.sensor_num);
 		if (sensor == NULL)
 			return EC_RES_INVALID_PARAM;
 
@@ -1172,10 +1097,10 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 			 * The new ODR may suspend sensor, leaving samples
 			 * in the FIFO. Flush it explicitly.
 			 */
-			deprecated_atomic_or(&odr_event_required,
-					     1 << (sensor - motion_sensors));
+			atomic_or(&odr_event_required,
+				  BIT(sensor - motion_sensors));
 			task_set_event(TASK_ID_MOTIONSENSE,
-					TASK_EVENT_MOTION_ODR_CHANGE, 0);
+				       TASK_EVENT_MOTION_ODR_CHANGE);
 		}
 
 		out->sensor_odr.ret = sensor->drv->get_data_rate(sensor);
@@ -1187,7 +1112,7 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 	case MOTIONSENSE_CMD_SENSOR_RANGE:
 		/* Verify sensor number is valid. */
 		sensor = host_sensor_id_to_real_sensor(
-				in->sensor_range.sensor_num);
+			in->sensor_range.sensor_num);
 		if (sensor == NULL)
 			return EC_RES_INVALID_PARAM;
 		/* Set new range if the data arg has a value. */
@@ -1195,25 +1120,21 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 			if (!sensor->drv->set_range)
 				return EC_RES_INVALID_COMMAND;
 
-			if (sensor->drv->set_range(sensor,
-						   in->sensor_range.data,
-						   in->sensor_range.roundup)
-					!= EC_SUCCESS) {
+			if (sensor->drv->set_range(
+				    sensor, in->sensor_range.data,
+				    in->sensor_range.roundup) != EC_SUCCESS) {
 				return EC_RES_INVALID_PARAM;
 			}
 		}
 
-		if (!sensor->drv->get_range)
-			return EC_RES_INVALID_COMMAND;
-
-		out->sensor_range.ret = sensor->drv->get_range(sensor);
+		out->sensor_range.ret = sensor->current_range;
 		args->response_size = sizeof(out->sensor_range);
 		break;
 
 	case MOTIONSENSE_CMD_SENSOR_OFFSET:
 		/* Verify sensor number is valid. */
 		sensor = host_sensor_id_to_real_sensor(
-				in->sensor_offset.sensor_num);
+			in->sensor_offset.sensor_num);
 		if (sensor == NULL)
 			return EC_RES_INVALID_PARAM;
 		/* Set new range if the data arg has a value. */
@@ -1221,9 +1142,9 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 			if (!sensor->drv->set_offset)
 				return EC_RES_INVALID_COMMAND;
 
-			ret = sensor->drv->set_offset(sensor,
-						in->sensor_offset.offset,
-						in->sensor_offset.temp);
+			in_offset = in->sensor_offset.offset;
+			ret = sensor->drv->set_offset(sensor, in_offset,
+						      in->sensor_offset.temp);
 			if (ret != EC_SUCCESS)
 				return ret;
 		}
@@ -1231,17 +1152,19 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 		if (!sensor->drv->get_offset)
 			return EC_RES_INVALID_COMMAND;
 
-		ret = sensor->drv->get_offset(sensor, out->sensor_offset.offset,
-				&out->sensor_offset.temp);
+		out_offset = out->sensor_offset.offset;
+		ret = sensor->drv->get_offset(sensor, out_offset, &out_temp);
 		if (ret != EC_SUCCESS)
 			return ret;
+
+		out->sensor_offset.temp = out_temp;
 		args->response_size = sizeof(out->sensor_offset);
 		break;
 
 	case MOTIONSENSE_CMD_SENSOR_SCALE:
 		/* Verify sensor number is valid. */
 		sensor = host_sensor_id_to_real_sensor(
-				in->sensor_scale.sensor_num);
+			in->sensor_scale.sensor_num);
 		if (sensor == NULL)
 			return EC_RES_INVALID_PARAM;
 		/* Set new range if the data arg has a value. */
@@ -1249,9 +1172,9 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 			if (!sensor->drv->set_scale)
 				return EC_RES_INVALID_COMMAND;
 
-			ret = sensor->drv->set_scale(sensor,
-						in->sensor_scale.scale,
-						in->sensor_scale.temp);
+			in_scale = in->sensor_scale.scale;
+			ret = sensor->drv->set_scale(sensor, in_scale,
+						     in->sensor_scale.temp);
 			if (ret != EC_SUCCESS)
 				return ret;
 		}
@@ -1259,46 +1182,56 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 		if (!sensor->drv->get_scale)
 			return EC_RES_INVALID_COMMAND;
 
-		ret = sensor->drv->get_scale(sensor, out->sensor_scale.scale,
-				&out->sensor_scale.temp);
+		out_scale = out->sensor_scale.scale;
+		ret = sensor->drv->get_scale(sensor, out_scale, &out_temp);
 		if (ret != EC_SUCCESS)
 			return ret;
+
+		out->sensor_scale.temp = out_temp;
 		args->response_size = sizeof(out->sensor_scale);
 		break;
 
 	case MOTIONSENSE_CMD_PERFORM_CALIB:
 		/* Verify sensor number is valid. */
 		sensor = host_sensor_id_to_real_sensor(
-				in->perform_calib.sensor_num);
+			in->perform_calib.sensor_num);
 		if (sensor == NULL)
 			return EC_RES_INVALID_PARAM;
 		if (!sensor->drv->perform_calib)
 			return EC_RES_INVALID_COMMAND;
 
-		ret = sensor->drv->perform_calib(
-				sensor, in->perform_calib.enable);
+		ret = sensor->drv->perform_calib(sensor,
+						 in->perform_calib.enable);
 		if (ret != EC_SUCCESS)
 			return ret;
-		ret = sensor->drv->get_offset(sensor, out->perform_calib.offset,
-				&out->perform_calib.temp);
+
+		out_offset = out->perform_calib.offset;
+		ret = sensor->drv->get_offset(sensor, out_offset, &out_temp);
 		if (ret != EC_SUCCESS)
 			return ret;
+
+		out->perform_calib.temp = out_temp;
 		args->response_size = sizeof(out->perform_calib);
 		break;
 
 	case MOTIONSENSE_CMD_FIFO_FLUSH:
-		if (!IS_ENABLED(CONFIG_ACCEL_FIFO))
-			return EC_RES_INVALID_PARAM;
+/* TODO (http://b/255967867) Can't use the IS_ENABLED macro here because
+ *   __fallthrough fails in clang as unreachable code.
+ */
+#ifndef CONFIG_ACCEL_FIFO
+		return EC_RES_INVALID_PARAM;
+#else
 		sensor = host_sensor_id_to_real_sensor(
-				in->sensor_odr.sensor_num);
+			in->sensor_odr.sensor_num);
 		if (sensor == NULL)
 			return EC_RES_INVALID_PARAM;
 
-		deprecated_atomic_add(&sensor->flush_pending, 1);
+		atomic_add(&sensor->flush_pending, 1);
 
 		task_set_event(TASK_ID_MOTIONSENSE,
-			       TASK_EVENT_MOTION_FLUSH_PENDING, 0);
-		/* pass-through */
+			       TASK_EVENT_MOTION_FLUSH_PENDING);
+		__fallthrough;
+#endif
 	case MOTIONSENSE_CMD_FIFO_INFO:
 		if (!IS_ENABLED(CONFIG_ACCEL_FIFO)) {
 			/*
@@ -1310,12 +1243,8 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 			break;
 		}
 		motion_sense_fifo_get_info(&out->fifo_info, 1);
-		for (i = 0; i < motion_sensor_count; i++) {
-			out->fifo_info.lost[i] = motion_sensors[i].lost;
-			motion_sensors[i].lost = 0;
-		}
 		args->response_size = sizeof(out->fifo_info) +
-			sizeof(uint16_t) * motion_sensor_count;
+				      sizeof(uint16_t) * motion_sensor_count;
 		break;
 
 	case MOTIONSENSE_CMD_FIFO_READ:
@@ -1323,8 +1252,7 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 			return EC_RES_INVALID_PARAM;
 		out->fifo_read.number_data = motion_sense_fifo_read(
 			args->response_max - sizeof(out->fifo_read),
-			in->fifo_read.max_data_vector,
-			out->fifo_read.data,
+			in->fifo_read.max_data_vector, out->fifo_read.data,
 			&(args->response_size));
 		args->response_size += sizeof(out->fifo_read);
 		break;
@@ -1335,7 +1263,7 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 		case 0:
 		case 1:
 			fifo_int_enabled = in->fifo_int_enable.enable;
-			/* fallthrough */
+			__fallthrough;
 		case EC_MOTION_SENSE_NO_VALUE:
 			out->fifo_int_enable.ret = fifo_int_enabled;
 			args->response_size = sizeof(out->fifo_int_enable);
@@ -1352,13 +1280,11 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 		if (sensor == NULL)
 			return EC_RES_INVALID_PARAM;
 
-
+		out_calib_read = &out->online_calib_read;
 		args->response_size =
-			online_calibration_read(
-				(int)(sensor - motion_sensors),
-				out->online_calib_read.data)
-			? sizeof(struct ec_response_online_calibration_data)
-			: 0;
+			online_calibration_read(sensor, out_calib_read) ?
+				sizeof(struct ec_response_online_calibration_data) :
+				0;
 		break;
 #ifdef CONFIG_GESTURE_HOST_DETECTION
 	case MOTIONSENSE_CMD_LIST_ACTIVITIES: {
@@ -1371,22 +1297,22 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 		while (mask && ret == EC_RES_SUCCESS) {
 			i = get_next_bit(&mask);
 			sensor = &motion_sensors[i];
-			ret = sensor->drv->list_activities(sensor,
-					&enabled, &disabled);
+			ret = sensor->drv->list_activities(sensor, &enabled,
+							   &disabled);
 			if (ret == EC_RES_SUCCESS) {
 				out->list_activities.enabled |= enabled;
 				out->list_activities.disabled |= disabled;
 			}
 		}
-#ifdef CONFIG_BODY_DETECTION
-		if (body_detect_get_enable()) {
-			out->list_activities.enabled |=
-				BIT(MOTIONSENSE_ACTIVITY_BODY_DETECTION);
-		} else {
-			out->list_activities.disabled |=
-				BIT(MOTIONSENSE_ACTIVITY_BODY_DETECTION);
+		if (IS_ENABLED(CONFIG_BODY_DETECTION)) {
+			if (body_detect_get_enable()) {
+				out->list_activities.enabled |= BIT(
+					MOTIONSENSE_ACTIVITY_BODY_DETECTION);
+			} else {
+				out->list_activities.disabled |= BIT(
+					MOTIONSENSE_ACTIVITY_BODY_DETECTION);
+			}
 		}
-#endif
 		if (ret != EC_RES_SUCCESS)
 			return ret;
 		args->response_size = sizeof(out->list_activities);
@@ -1400,35 +1326,32 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 		while (mask && ret == EC_RES_SUCCESS) {
 			i = get_next_bit(&mask);
 			sensor = &motion_sensors[i];
-			sensor->drv->list_activities(sensor,
-					&enabled, &disabled);
+			sensor->drv->list_activities(sensor, &enabled,
+						     &disabled);
 			if ((1 << in->set_activity.activity) &
 			    (enabled | disabled))
-				ret = sensor->drv->manage_activity(sensor,
-						in->set_activity.activity,
-						in->set_activity.enable,
-						&in->set_activity);
+				ret = sensor->drv->manage_activity(
+					sensor, in->set_activity.activity,
+					in->set_activity.enable,
+					&in->set_activity);
 		}
-#ifdef CONFIG_BODY_DETECTION
-		if (in->set_activity.activity ==
-		    MOTIONSENSE_ACTIVITY_BODY_DETECTION)
+		if (IS_ENABLED(CONFIG_BODY_DETECTION) &&
+		    (in->set_activity.activity ==
+		     MOTIONSENSE_ACTIVITY_BODY_DETECTION))
 			body_detect_set_enable(in->set_activity.enable);
-#endif
 		if (ret != EC_RES_SUCCESS)
 			return ret;
 		args->response_size = 0;
 		break;
 	}
 	case MOTIONSENSE_CMD_GET_ACTIVITY: {
-		switch (in->get_activity.activity) {
-#ifdef CONFIG_BODY_DETECTION
-		case MOTIONSENSE_ACTIVITY_BODY_DETECTION:
-			out->get_activity.state = (uint8_t)
-					body_detect_get_state();
+		if (IS_ENABLED(CONFIG_BODY_DETECTION) &&
+		    (in->get_activity.activity ==
+		     MOTIONSENSE_ACTIVITY_BODY_DETECTION)) {
+			out->get_activity.state =
+				(uint8_t)body_detect_get_state();
 			ret = EC_RES_SUCCESS;
-			break;
-#endif
-		default:
+		} else {
 			ret = EC_RES_INVALID_PARAM;
 		}
 		if (ret != EC_RES_SUCCESS)
@@ -1440,6 +1363,56 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 
 #ifdef CONFIG_ACCEL_SPOOF_MODE
 	case MOTIONSENSE_CMD_SPOOF: {
+		/* spoof activity if it is activity sensor */
+		if (IS_ENABLED(CONFIG_GESTURE_HOST_DETECTION) &&
+		    MOTION_SENSE_ACTIVITY_SENSOR_ID >= 0 &&
+		    in->spoof.sensor_id == MOTION_SENSE_ACTIVITY_SENSOR_ID) {
+			switch (in->spoof.activity_num) {
+#ifdef CONFIG_BODY_DETECTION
+			case MOTIONSENSE_ACTIVITY_BODY_DETECTION:
+				switch (in->spoof.spoof_enable) {
+				case MOTIONSENSE_SPOOF_MODE_DISABLE:
+					/* Disable spoofing. */
+					body_detect_set_spoof(false);
+					break;
+				case MOTIONSENSE_SPOOF_MODE_CUSTOM:
+					/*
+					 * Enable spoofing, but use provided
+					 * state
+					 */
+					body_detect_set_spoof(true);
+					body_detect_change_state(
+						in->spoof.activity_state, true);
+					break;
+				case MOTIONSENSE_SPOOF_MODE_LOCK_CURRENT:
+					/*
+					 * Enable spoofing, but lock to current
+					 * state
+					 */
+					body_detect_set_spoof(true);
+					break;
+				case MOTIONSENSE_SPOOF_MODE_QUERY:
+					/*
+					 * Query the spoof status of the
+					 * activity
+					 */
+					out->spoof.ret =
+						body_detect_get_spoof();
+					args->response_size =
+						sizeof(out->spoof);
+					break;
+				default:
+					return EC_RES_INVALID_PARAM;
+				}
+				break;
+#endif
+			default:
+				return EC_RES_INVALID_PARAM;
+			}
+			break;
+		}
+
+		/* spoof accel data */
 		sensor = host_sensor_id_to_real_sensor(in->spoof.sensor_id);
 		if (sensor == NULL)
 			return EC_RES_INVALID_PARAM;
@@ -1474,7 +1447,7 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 		case MOTIONSENSE_SPOOF_MODE_QUERY:
 			/* Querying the spoof status of the sensor. */
 			out->spoof.ret = !!(sensor->flags &
-					MOTIONSENSE_FLAG_IN_SPOOF_MODE);
+					    MOTIONSENSE_FLAG_IN_SPOOF_MODE);
 			args->response_size = sizeof(out->spoof);
 			break;
 
@@ -1494,10 +1467,10 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 
 	default:
 		/* Call other users of the motion task */
-#ifdef CONFIG_LID_ANGLE
-		if (ret == EC_RES_INVALID_PARAM)
+		if (IS_ENABLED(CONFIG_LID_ANGLE) &&
+		    (ret == EC_RES_INVALID_PARAM) &&
+		    sensor_board_is_lid_angle_available())
 			ret = host_cmd_motion_lid(args);
-#endif
 		return ret;
 	}
 
@@ -1506,12 +1479,12 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 
 DECLARE_HOST_COMMAND(EC_CMD_MOTION_SENSE_CMD, host_cmd_motion_sense,
 		     EC_VER_MASK(1) | EC_VER_MASK(2) | EC_VER_MASK(3) |
-		     EC_VER_MASK(4));
+			     EC_VER_MASK(4));
 
 /*****************************************************************************/
 /* Console commands */
 #ifdef CONFIG_CMD_ACCELS
-static int command_accelrange(int argc, char **argv)
+static int command_accelrange(int argc, const char **argv)
 {
 	char *e;
 	int id, data, round = 1;
@@ -1544,22 +1517,19 @@ static int command_accelrange(int argc, char **argv)
 		 * Write new range, if it returns invalid arg, then return
 		 * a parameter error.
 		 */
-		if (sensor->drv->set_range(sensor,
-					   data,
-					   round) == EC_ERROR_INVAL)
+		if (sensor->drv->set_range(sensor, data, round) ==
+		    EC_ERROR_INVAL)
 			return EC_ERROR_PARAM2;
 	} else {
-		ccprintf("Range for sensor %d: %d\n", id,
-			 sensor->drv->get_range(sensor));
+		ccprintf("Sensor %d range: %d\n", id, sensor->current_range);
 	}
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(accelrange, command_accelrange,
-	"id [data [roundup]]",
-	"Read or write accelerometer range");
+DECLARE_CONSOLE_COMMAND(accelrange, command_accelrange, "id [data [roundup]]",
+			"Read or write accelerometer range");
 
-static int command_accelresolution(int argc, char **argv)
+static int command_accelresolution(int argc, const char **argv)
 {
 	char *e;
 	int id, data, round = 1;
@@ -1593,8 +1563,8 @@ static int command_accelresolution(int argc, char **argv)
 		 * return a parameter error.
 		 */
 		if (sensor->drv->set_resolution &&
-		    sensor->drv->set_resolution(sensor, data, round)
-			== EC_ERROR_INVAL)
+		    sensor->drv->set_resolution(sensor, data, round) ==
+			    EC_ERROR_INVAL)
 			return EC_ERROR_PARAM2;
 	} else {
 		ccprintf("Resolution for sensor %d: %d\n", id,
@@ -1604,10 +1574,10 @@ static int command_accelresolution(int argc, char **argv)
 	return EC_SUCCESS;
 }
 DECLARE_CONSOLE_COMMAND(accelres, command_accelresolution,
-	"id [data [roundup]]",
-	"Read or write accelerometer resolution");
+			"id [data [roundup]]",
+			"Read or write accelerometer resolution");
 
-static int command_accel_data_rate(int argc, char **argv)
+static int command_accel_data_rate(int argc, const char **argv)
 {
 	char *e;
 	int id, data, round = 1;
@@ -1644,28 +1614,26 @@ static int command_accel_data_rate(int argc, char **argv)
 		 */
 		config_id = motion_sense_get_ec_config();
 		sensor->config[SENSOR_CONFIG_AP].odr = 0;
-		sensor->config[config_id].odr =
-			data | (round ? ROUND_UP_FLAG : 0);
+		sensor->config[config_id].odr = data |
+						(round ? ROUND_UP_FLAG : 0);
 
-		deprecated_atomic_or(&odr_event_required,
-				     1 << (sensor - motion_sensors));
+		atomic_or(&odr_event_required, 1 << (sensor - motion_sensors));
 		task_set_event(TASK_ID_MOTIONSENSE,
-				TASK_EVENT_MOTION_ODR_CHANGE, 0);
+			       TASK_EVENT_MOTION_ODR_CHANGE);
 	} else {
 		ccprintf("Data rate for sensor %d: %d\n", id,
 			 sensor->drv->get_data_rate(sensor));
 		ccprintf("EC rate for sensor %d: %d\n", id,
-			 motion_sense_ec_rate(sensor));
-		ccprintf("Current Interrupt rate: %d\n", ap_event_interval);
+			 sensor->config[SENSOR_CONFIG_AP].ec_rate);
 	}
 
 	return EC_SUCCESS;
 }
 DECLARE_CONSOLE_COMMAND(accelrate, command_accel_data_rate,
-	"id [data [roundup]]",
-	"Read or write accelerometer ODR");
+			"id [data [roundup]]",
+			"Read or write accelerometer ODR");
 
-static int command_accel_read_xyz(int argc, char **argv)
+static int command_accel_read_xyz(int argc, const char **argv)
 {
 	char *e;
 	int id, n = 1, ret;
@@ -1686,25 +1654,24 @@ static int command_accel_read_xyz(int argc, char **argv)
 
 	sensor = &motion_sensors[id];
 
-	while ((n == -1) || (n-- > 0)) {
+	while ((n-- > 0)) {
 		ret = sensor->drv->read(sensor, v);
 		if (ret == 0)
-			ccprintf("Current data %d: %-5d %-5d %-5d\n",
-				 id, v[X], v[Y], v[Z]);
+			ccprintf("Current data %d: %-5d %-5d %-5d\n", id, v[X],
+				 v[Y], v[Z]);
 		else
 			ccprintf("vector not ready\n");
-		ccprintf("Last calib. data %d: %-5d %-5d %-5d\n",
-			 id, sensor->xyz[X], sensor->xyz[Y], sensor->xyz[Z]);
+		ccprintf("Last calib. data %d: %-5d %-5d %-5d\n", id,
+			 sensor->xyz[X], sensor->xyz[Y], sensor->xyz[Z]);
 		task_wait_event(motion_min_interval);
 	}
 	return EC_SUCCESS;
 }
 
-DECLARE_CONSOLE_COMMAND(accelread, command_accel_read_xyz,
-	"id [n]",
-	"Read sensor x/y/z");
+DECLARE_CONSOLE_COMMAND(accelread, command_accel_read_xyz, "id [n]",
+			"Read sensor x/y/z");
 
-static int command_accel_init(int argc, char **argv)
+static int command_accel_init(int argc, const char **argv)
 {
 	char *e;
 	int id, ret;
@@ -1725,16 +1692,14 @@ static int command_accel_init(int argc, char **argv)
 	ccprintf("%s: state %d - %d\n", sensor->name, sensor->state, ret);
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(accelinit, command_accel_init,
-	"id",
-	"Init sensor");
+DECLARE_CONSOLE_COMMAND(accelinit, command_accel_init, "id", "Init sensor");
 
 #ifdef CONFIG_CMD_ACCEL_INFO
-static int command_display_accel_info(int argc, char **argv)
+static int command_display_accel_info(int argc, const char **argv)
 {
 	int val, i, j;
 
-	if (argc > 3)
+	if (argc >= 3)
 		return EC_ERROR_PARAM_COUNT;
 
 	ccprintf("Motion sensors count = %d\n", motion_sensor_count);
@@ -1747,17 +1712,17 @@ static int command_display_accel_info(int argc, char **argv)
 		ccprintf("type: %d\n", motion_sensors[i].type);
 		ccprintf("location: %d\n", motion_sensors[i].location);
 		ccprintf("port: %d\n", motion_sensors[i].port);
-		ccprintf("addr: %d\n", I2C_GET_ADDR(motion_sensors[i]
-						    .i2c_spi_addr_flags));
-		ccprintf("range: %d\n", motion_sensors[i].default_range);
+		ccprintf("addr: %d\n",
+			 I2C_STRIP_FLAGS(motion_sensors[i].i2c_spi_addr_flags));
+		ccprintf("range: %d\n", motion_sensors[i].current_range);
 		ccprintf("min_freq: %d\n", motion_sensors[i].min_frequency);
 		ccprintf("max_freq: %d\n", motion_sensors[i].max_frequency);
 		ccprintf("config:\n");
 		for (j = 0; j < SENSOR_CONFIG_MAX; j++) {
 			ccprintf("%d - odr: %umHz, ec_rate: %uus\n", j,
-				motion_sensors[i].config[j].odr &
-				~ROUND_UP_FLAG,
-				motion_sensors[i].config[j].ec_rate);
+				 motion_sensors[i].config[j].odr &
+					 ~ROUND_UP_FLAG,
+				 motion_sensors[i].config[j].ec_rate);
 		}
 	}
 
@@ -1771,59 +1736,26 @@ static int command_display_accel_info(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(accelinfo, command_display_accel_info,
-	"on/off [interval]",
-	"Print motion sensor info, lid angle calculations"
-	" and set calculation frequency.");
+DECLARE_CONSOLE_COMMAND(accelinfo, command_display_accel_info, "on/off",
+			"Print motion sensor info, lid angle calculations.");
 #endif /* CONFIG_CMD_ACCEL_INFO */
 
-#ifdef CONFIG_CMD_ACCEL_FIFO
-static int motion_sense_read_fifo(int argc, char **argv)
-{
-	int count, i;
-	struct ec_response_motion_sensor_data v;
-
-	if (argc < 1)
-		return EC_ERROR_PARAM_COUNT;
-
-	/* Limit the amount of data to avoid saturating the UART buffer */
-	count = MIN(queue_count(&motion_sense_fifo), 16);
-	for (i = 0; i < count; i++) {
-		queue_peek_units(&motion_sense_fifo, &v, i, 1);
-		if (v.flags & (MOTIONSENSE_SENSOR_FLAG_TIMESTAMP |
-			       MOTIONSENSE_SENSOR_FLAG_FLUSH)) {
-			uint64_t timestamp;
-			memcpy(&timestamp, v.data, sizeof(v.data));
-			ccprintf("Timestamp: 0x%016llx%s\n", timestamp,
-				 (v.flags & MOTIONSENSE_SENSOR_FLAG_FLUSH ?
-				  " - Flush" : ""));
-		} else {
-			ccprintf("%d %d: %-5d %-5d %-5d\n", i, v.sensor_num,
-				 v.data[X], v.data[Y], v.data[Z]);
-		}
-	}
-	return EC_SUCCESS;
-}
-
-DECLARE_CONSOLE_COMMAND(fiforead, motion_sense_read_fifo,
-	"id",
-	"Read Fifo sensor");
-#endif /* defined(CONFIG_CMD_ACCEL_FIFO) */
 #endif /* CONFIG_CMD_ACCELS */
 
 #ifdef CONFIG_ACCEL_SPOOF_MODE
 static void print_spoof_mode_status(int id)
 {
 	CPRINTS("Sensor %d spoof mode is %s. <%d, %d, %d>", id,
-		(motion_sensors[id].flags & MOTIONSENSE_FLAG_IN_SPOOF_MODE)
-				? "enabled" : "disabled",
+		(motion_sensors[id].flags & MOTIONSENSE_FLAG_IN_SPOOF_MODE) ?
+			"enabled" :
+			"disabled",
 		motion_sensors[id].spoof_xyz[X],
 		motion_sensors[id].spoof_xyz[Y],
 		motion_sensors[id].spoof_xyz[Z]);
 }
 
 #ifdef CONFIG_CMD_ACCELSPOOF
-static int command_accelspoof(int argc, char **argv)
+static int command_accelspoof(int argc, const char **argv)
 {
 	char *e;
 	int id, enable, i;
@@ -1858,8 +1790,8 @@ static int command_accelspoof(int argc, char **argv)
 			 */
 			if (argc == 6) {
 				for (i = 0; i < 3; i++)
-					s->spoof_xyz[i] = strtoi(argv[3 + i],
-								 &e, 0);
+					s->spoof_xyz[i] =
+						strtoi(argv[3 + i], &e, 0);
 			} else if (argc == 3) {
 				for (i = X; i <= Z; i++)
 					s->spoof_xyz[i] = s->raw_xyz[i];
diff --git a/common/motion_sense_fifo.c b/common/motion_sense_fifo.c
index 2325de4c87..1a7303bc79 100644
--- a/common/motion_sense_fifo.c
+++ b/common/motion_sense_fifo.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,16 +6,24 @@
 #include "accelgyro.h"
 #include "console.h"
 #include "hwtimer.h"
+#include "math_util.h"
 #include "mkbp_event.h"
 #include "motion_sense_fifo.h"
+#include "online_calibration.h"
+#include "stdbool.h"
 #include "tablet_mode.h"
 #include "task.h"
 #include "util.h"
-#include "math_util.h"
-#include "online_calibration.h"
-#include "stdbool.h"
 
-#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ##args)
+
+/*
+ * Adjustment in us to ec rate when calculating interrupt interval:
+ * To be sure the EC will send an interrupt even if it finishes processing
+ * events slightly earlier than the previous period.
+ */
+#define MOTION_SENSOR_INT_ADJUSTMENT_US \
+	(CONFIG_MOTION_MIN_SENSE_WAIT_TIME * MSEC / 10)
 
 /**
  * Staged metadata for the fifo queue.
@@ -50,6 +58,12 @@ static struct queue fifo = QUEUE_NULL(CONFIG_ACCEL_FIFO_SIZE,
 				      struct ec_response_motion_sensor_data);
 /** Count of the number of entries lost due to a small queue. */
 static int fifo_lost;
+/*
+ * How many vector events are lost in the FIFO since last time
+ * FIFO info has been transmitted.
+ */
+static uint16_t fifo_sensor_lost[MAX_MOTION_SENSORS];
+
 /** Metadata for the fifo, used for staging and spreading data. */
 static struct fifo_staged fifo_staged;
 
@@ -59,22 +73,46 @@ static struct fifo_staged fifo_staged;
  */
 static struct timestamp_state next_timestamp[MAX_MOTION_SENSORS];
 
+/**
+ * Expected data periods:
+ * copy of collection rate, updated when ODR changes.
+ */
+static uint32_t expected_data_periods[MAX_MOTION_SENSORS];
+
+/**
+ * Calculated data periods:
+ * can be different from collection rate when spreading.
+ */
+static uint32_t data_periods[MAX_MOTION_SENSORS];
+
 /**
  * Bitmap telling which sensors have valid entries in the next_timestamp array.
  */
 static uint32_t next_timestamp_initialized;
 
+/** Need to bypass the FIFO for an important message. */
+static int bypass_needed;
+
 /** Need to wake up the AP. */
 static int wake_up_needed;
 
+/** Need to interrupt the AP. */
+static int ap_interrupt_needed;
+
+/**
+ * Timestamp of the first event put in the fifo during the
+ * last motion_task invocation.
+ */
+uint32_t ts_last_int[MAX_MOTION_SENSORS];
+
 /**
  * Check whether or not a give sensor data entry is a timestamp or not.
  *
  * @param data The data entry to check.
  * @return 1 if the entry is a timestamp, 0 otherwise.
  */
-static inline int is_timestamp(
-	const struct ec_response_motion_sensor_data *data)
+static inline int
+is_timestamp(const struct ec_response_motion_sensor_data *data)
 {
 	return data->flags & MOTIONSENSE_SENSOR_FLAG_TIMESTAMP;
 }
@@ -99,8 +137,8 @@ static inline bool is_data(const struct ec_response_motion_sensor_data *data)
  */
 static inline struct ec_response_motion_sensor_data *get_fifo_head(void)
 {
-	return ((struct ec_response_motion_sensor_data *) fifo.buffer) +
-		(fifo.state->head & fifo.buffer_units_mask);
+	return ((struct ec_response_motion_sensor_data *)fifo.buffer) +
+	       (fifo.state->head & fifo.buffer_units_mask);
 }
 
 /**
@@ -146,7 +184,7 @@ static void fifo_pop(void)
 
 	/* Increment lost counter if we have valid data. */
 	if (!is_timestamp(head))
-		motion_sensors[head->sensor_num].lost++;
+		fifo_sensor_lost[head->sensor_num]++;
 
 	/*
 	 * We're done if the initial count was non-zero and we only advanced the
@@ -225,15 +263,17 @@ static inline bool is_new_timestamp(uint8_t sensor_num)
  * @param data The data to stage.
  * @param sensor The sensor that generated the data
  * @param valid_data The number of readable data entries in the data.
+ *   sensor can be NULL (for activity sensors). valid_data must be 0 then.
  */
-static void fifo_stage_unit(
-	struct ec_response_motion_sensor_data *data,
-	struct motion_sensor_t *sensor,
-	int valid_data)
+static void fifo_stage_unit(struct ec_response_motion_sensor_data *data,
+			    struct motion_sensor_t *sensor, int valid_data)
 {
 	struct queue_chunk chunk;
 	int i;
 
+	if (valid_data > 0 && !sensor)
+		return;
+
 	mutex_lock(&g_sensor_mutex);
 
 	for (i = 0; i < valid_data; i++)
@@ -263,7 +303,7 @@ static void fifo_stage_unit(
 		if (removed) {
 			mutex_unlock(&g_sensor_mutex);
 			if (IS_ENABLED(CONFIG_ONLINE_CALIB) &&
-			    next_timestamp_initialized & BIT(data->sensor_num))
+			    !is_new_timestamp(data->sensor_num))
 				online_calibration_process_data(
 					data, sensor,
 					next_timestamp[data->sensor_num].next);
@@ -276,7 +316,8 @@ static void fifo_stage_unit(
 
 	if (IS_ENABLED(CONFIG_TABLET_MODE))
 		data->flags |= (tablet_get_mode() ?
-				MOTIONSENSE_SENSOR_FLAG_TABLET_MODE : 0);
+					MOTIONSENSE_SENSOR_FLAG_TABLET_MODE :
+					0);
 
 	/*
 	 * Get the next writable block in the fifo. We don't need to lock this
@@ -313,8 +354,7 @@ static void fifo_stage_unit(
 	 * If the new per-sensor sample count is greater than 1, we'll need to
 	 * spread.
 	 */
-	if (IS_ENABLED(CONFIG_SENSOR_TIGHT_TIMESTAMPS) &&
-	    !is_timestamp(data) &&
+	if (IS_ENABLED(CONFIG_SENSOR_TIGHT_TIMESTAMPS) && !is_timestamp(data) &&
 	    ++fifo_staged.sample_count[data->sensor_num] > 1)
 		fifo_staged.requires_spreading = 1;
 
@@ -348,8 +388,9 @@ static void fifo_stage_timestamp(uint32_t timestamp, uint8_t sensor_num)
 static inline struct ec_response_motion_sensor_data *
 peek_fifo_staged(size_t offset)
 {
-	return (struct ec_response_motion_sensor_data *)
-		queue_get_write_chunk(&fifo, offset).buffer;
+	return (struct ec_response_motion_sensor_data *)queue_get_write_chunk(
+		       &fifo, offset)
+		.buffer;
 }
 
 void motion_sense_fifo_init(void)
@@ -358,26 +399,41 @@ void motion_sense_fifo_init(void)
 		online_calibration_init();
 }
 
-int motion_sense_fifo_wake_up_needed(void)
+int motion_sense_fifo_interrupt_needed(void)
 {
-	int res;
+	return ap_interrupt_needed;
+}
 
-	mutex_lock(&g_sensor_mutex);
-	res = wake_up_needed;
-	mutex_unlock(&g_sensor_mutex);
-	return res;
+int motion_sense_fifo_bypass_needed(void)
+{
+	return bypass_needed;
 }
 
-void motion_sense_fifo_reset_wake_up_needed(void)
+int motion_sense_fifo_wake_up_needed(void)
 {
-	mutex_lock(&g_sensor_mutex);
+	return wake_up_needed;
+}
+
+void motion_sense_fifo_reset_needed_flags(void)
+{
+	int i;
+
+	if (ap_interrupt_needed) {
+		ap_interrupt_needed = 0;
+		/*
+		 * The FIFO is emptied, note timestamp of the last event sent
+		 * as we start counting the delay based on that timestamp.
+		 */
+		for (i = 0; i < MAX_MOTION_SENSORS; i++)
+			if (!is_new_timestamp(i))
+				ts_last_int[i] = next_timestamp[i].prev;
+	}
 	wake_up_needed = 0;
-	mutex_unlock(&g_sensor_mutex);
+	bypass_needed = 0;
 }
 
-void motion_sense_fifo_insert_async_event(
-	struct motion_sensor_t *sensor,
-	enum motion_sense_async_event event)
+void motion_sense_fifo_insert_async_event(struct motion_sensor_t *sensor,
+					  enum motion_sense_async_event event)
 {
 	struct ec_response_motion_sensor_data vector;
 
@@ -395,25 +451,29 @@ inline void motion_sense_fifo_add_timestamp(uint32_t timestamp)
 	motion_sense_fifo_commit_data();
 }
 
-void motion_sense_fifo_stage_data(
-	struct ec_response_motion_sensor_data *data,
-	struct motion_sensor_t *sensor,
-	int valid_data,
-	uint32_t time)
+void motion_sense_fifo_stage_data(struct ec_response_motion_sensor_data *data,
+				  struct motion_sensor_t *sensor,
+				  int valid_data, uint32_t time)
 {
+	int id = data->sensor_num;
+
 	if (IS_ENABLED(CONFIG_SENSOR_TIGHT_TIMESTAMPS)) {
 		/* First entry, save the time for spreading later. */
 		if (!fifo_staged.count)
 			fifo_staged.read_ts = __hw_clock_source_read();
 		fifo_stage_timestamp(time, data->sensor_num);
 	}
+	if (sensor && sensor->config[SENSOR_CONFIG_AP].ec_rate > 0 &&
+	    time_after(time, ts_last_int[id] +
+				     sensor->config[SENSOR_CONFIG_AP].ec_rate -
+				     MOTION_SENSOR_INT_ADJUSTMENT_US)) {
+		ap_interrupt_needed = 1;
+	}
 	fifo_stage_unit(data, sensor, valid_data);
 }
 
 void motion_sense_fifo_commit_data(void)
 {
-	/* Cached data periods, static to store off stack. */
-	static uint32_t data_periods[MAX_MOTION_SENSORS];
 	struct ec_response_motion_sensor_data *data;
 	int i, window, sensor_num;
 
@@ -454,15 +514,15 @@ void motion_sense_fifo_commit_data(void)
 		if (!fifo_staged.sample_count[i])
 			continue;
 
-		period = motion_sensors[i].collection_rate;
+		period = expected_data_periods[i];
 		/*
 		 * Clamp the sample period to the MIN of collection_rate and the
 		 * window length / (sample count - 1).
 		 */
 		if (window && fifo_staged.sample_count[i] > 1)
-			period = MIN(
-				period,
-				window / (fifo_staged.sample_count[i] - 1));
+			period =
+				MIN(period,
+				    window / (fifo_staged.sample_count[i] - 1));
 		data_periods[i] = period;
 	}
 
@@ -478,6 +538,8 @@ void motion_sense_fifo_commit_data(void)
 	 */
 	for (i = 0; i < fifo_staged.count; i++) {
 		data = peek_fifo_staged(i);
+		if (data->flags & MOTIONSENSE_SENSOR_FLAG_BYPASS_FIFO)
+			bypass_needed = 1;
 		if (data->flags & MOTIONSENSE_SENSOR_FLAG_WAKEUP)
 			wake_up_needed = 1;
 
@@ -503,7 +565,7 @@ void motion_sense_fifo_commit_data(void)
 		 * sensor or the timestamp is after our computed next, skip
 		 * ahead.
 		 */
-		if (!(next_timestamp_initialized & BIT(sensor_num)) ||
+		if (is_new_timestamp(sensor_num) ||
 		    time_after(data->timestamp,
 			       next_timestamp[sensor_num].prev)) {
 			next_timestamp[sensor_num].next = data->timestamp;
@@ -515,9 +577,9 @@ void motion_sense_fifo_commit_data(void)
 		next_timestamp[sensor_num].prev =
 			next_timestamp[sensor_num].next;
 		next_timestamp[sensor_num].next +=
-			fifo_staged.requires_spreading
-			? data_periods[sensor_num]
-			: motion_sensors[sensor_num].collection_rate;
+			fifo_staged.requires_spreading ?
+				data_periods[sensor_num] :
+				expected_data_periods[sensor_num];
 
 		/* Update online calibration if enabled. */
 		data = peek_fifo_staged(i);
@@ -537,22 +599,29 @@ void motion_sense_fifo_commit_data(void)
 }
 
 void motion_sense_fifo_get_info(
-	struct ec_response_motion_sense_fifo_info *fifo_info,
-	int reset)
+	struct ec_response_motion_sense_fifo_info *fifo_info, int reset)
 {
+	int i;
+
 	mutex_lock(&g_sensor_mutex);
 	fifo_info->size = fifo.buffer_units;
 	fifo_info->count = queue_count(&fifo);
 	fifo_info->total_lost = fifo_lost;
+	for (i = 0; i < MAX_MOTION_SENSORS; i++) {
+		fifo_info->lost[i] = fifo_sensor_lost[i];
+	}
 	mutex_unlock(&g_sensor_mutex);
 #ifdef CONFIG_MKBP_EVENT
 	fifo_info->timestamp = mkbp_last_event_time;
 #endif
 
-	if (reset)
+	if (reset) {
 		fifo_lost = 0;
+		memset(fifo_sensor_lost, 0, sizeof(fifo_sensor_lost));
+	}
 }
 
+/* LCOV_EXCL_START - function cannot be tested due to limitations with mkbp */
 static int motion_sense_get_next_event(uint8_t *out)
 {
 	union ec_response_get_next_data *data =
@@ -561,7 +630,7 @@ static int motion_sense_get_next_event(uint8_t *out)
 	motion_sense_fifo_get_info(&data->sensor_fifo.info, 0);
 	return sizeof(data->sensor_fifo);
 }
-
+/* LCOV_EXCL_STOP */
 DECLARE_EVENT_SOURCE(EC_MKBP_EVENT_SENSOR_FIFO, motion_sense_get_next_event);
 
 inline int motion_sense_fifo_over_thres(void)
@@ -592,8 +661,64 @@ int motion_sense_fifo_read(int capacity_bytes, int max_count, void *out,
 
 void motion_sense_fifo_reset(void)
 {
+	static uint8_t fifo_info_buffer
+		[sizeof(struct ec_response_motion_sense_fifo_info) +
+		 sizeof(uint16_t) * MAX_MOTION_SENSORS];
+	struct ec_response_motion_sense_fifo_info *fifo_info =
+		(void *)fifo_info_buffer;
+
 	next_timestamp_initialized = 0;
 	memset(&fifo_staged, 0, sizeof(fifo_staged));
 	motion_sense_fifo_init();
 	queue_init(&fifo);
+	motion_sense_fifo_get_info(fifo_info, /*reset=*/true);
+}
+
+void motion_sense_set_data_period(int sensor_num, uint32_t data_period)
+{
+	expected_data_periods[sensor_num] = data_period;
+	/*
+	 * Reset the timestamp:
+	 * - Avoid overflow when the sensor has been disabled for a long
+	 * time.
+	 * - First ODR setting.
+	 * We may not send the first sample on time, but that is acceptable
+	 * for CTS.
+	 */
+	ts_last_int[sensor_num] = __hw_clock_source_read();
+	next_timestamp_initialized &= ~BIT(sensor_num);
 }
+
+#ifdef CONFIG_CMD_ACCEL_FIFO
+static int motion_sense_read_fifo(int argc, char **argv)
+{
+	int count, i;
+	struct ec_response_motion_sensor_data v;
+
+	if (argc < 1)
+		return EC_ERROR_PARAM_COUNT;
+
+	/* Limit the amount of data to avoid saturating the UART buffer */
+	count = MIN(queue_count(&fifo), 16);
+	for (i = 0; i < count; i++) {
+		queue_peek_units(&fifo, &v, i, 1);
+		if (v.flags & (MOTIONSENSE_SENSOR_FLAG_TIMESTAMP |
+			       MOTIONSENSE_SENSOR_FLAG_FLUSH)) {
+			uint64_t timestamp;
+
+			memcpy(&timestamp, v.data, sizeof(v.data));
+			ccprintf("Timestamp: 0x%016llx%s\n", timestamp,
+				 (v.flags & MOTIONSENSE_SENSOR_FLAG_FLUSH ?
+					  " - Flush" :
+					  ""));
+		} else {
+			ccprintf("%d %d: %-5d %-5d %-5d\n", i, v.sensor_num,
+				 v.data[X], v.data[Y], v.data[Z]);
+		}
+	}
+	return EC_SUCCESS;
+}
+
+DECLARE_CONSOLE_COMMAND(fiforead, motion_sense_read_fifo, "id",
+			"Read Fifo sensor");
+#endif /* defined(CONFIG_CMD_ACCEL_FIFO) */
diff --git a/common/newton_fit.c b/common/newton_fit.c
index ae81a45f07..3ba01dbd90 100644
--- a/common/newton_fit.c
+++ b/common/newton_fit.c
@@ -1,13 +1,14 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "common.h"
 #include "console.h"
-#include "newton_fit.h"
 #include "math.h"
 #include "math_util.h"
+#include "newton_fit.h"
+
 #include <string.h>
 
 #define CPRINTS(fmt, args...) cprints(CC_MOTION_SENSE, fmt, ##args)
@@ -32,7 +33,7 @@ static fp_t compute_error(struct newton_fit *fit, fpv3_t center)
 
 		_it = (struct newton_fit_orientation *)it.ptr;
 		e = FLOAT_TO_FP(1.0f) -
-			distance_squared(_it->orientation, center);
+		    distance_squared(_it->orientation, center);
 		error += fp_mul(e, e);
 	}
 
@@ -138,8 +139,8 @@ void newton_fit_compute(struct newton_fit *fit, fpv3_t bias, fp_t *radius)
 	if (queue_is_empty(fit->orientations))
 		return;
 
-	inv_orient_count = fp_div(FLOAT_TO_FP(1.0f),
-				  queue_count(fit->orientations));
+	inv_orient_count =
+		fp_div(FLOAT_TO_FP(1.0f), queue_count(fit->orientations));
 
 	memcpy(new_bias, bias, sizeof(fpv3_t));
 	new_error = compute_error(fit, new_bias);
diff --git a/common/ocpc.c b/common/ocpc.c
index 75876457c4..39e13dc046 100644
--- a/common/ocpc.c
+++ b/common/ocpc.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,7 +7,8 @@
 
 #include "battery.h"
 #include "battery_fuel_gauge.h"
-#include "charge_state_v2.h"
+#include "charge_manager.h"
+#include "charge_state.h"
 #include "charger.h"
 #include "common.h"
 #include "console.h"
@@ -15,6 +16,7 @@
 #include "math_util.h"
 #include "ocpc.h"
 #include "timer.h"
+#include "usb_pd.h"
 #include "util.h"
 
 /*
@@ -30,17 +32,22 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CHARGER, outstr)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-#define CPRINT_VIZ(format, args...) \
-do {							\
-	if (viz_output)				\
-		cprintf(CC_CHARGER, format, ## args);	\
-} while (0)
-#define CPRINTS_DBG(format, args...) \
-do {							\
-	if (debug_output)				\
-		cprints(CC_CHARGER, format, ## args);	\
-} while (0)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+#define CPRINT_VIZ(format, args...)                          \
+	do {                                                 \
+		if (viz_output)                              \
+			cprintf(CC_CHARGER, format, ##args); \
+	} while (0)
+#define CPRINTS_DBG(format, args...)                         \
+	do {                                                 \
+		if (debug_output)                            \
+			cprints(CC_CHARGER, format, ##args); \
+	} while (0)
+#define CPRINTF_DBG(format, args...)                         \
+	do {                                                 \
+		if (debug_output)                            \
+			cprintf(CC_CHARGER, format, ##args); \
+	} while (0)
 
 /* Code refactor will be needed if more than 2 charger chips are present */
 BUILD_ASSERT(CHARGER_NUM == 2);
@@ -51,11 +58,34 @@ static int k_d = KD;
 static int k_p_div = KP_DIV;
 static int k_i_div = KI_DIV;
 static int k_d_div = KD_DIV;
+static int drive_limit = CONFIG_OCPC_DEF_DRIVELIMIT_MILLIVOLTS;
 static int debug_output;
 static int viz_output;
 
+#define NUM_RESISTANCE_SAMPLES 8
+#define COMBINED_IDX 0
+#define RBATT_IDX 1
+#define RSYS_IDX 2
+static int resistance_tbl[NUM_RESISTANCE_SAMPLES][3] = {
+	/* Rsys+Rbatt                   Rbatt                    Rsys */
+	{ CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0 },
+	{ CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0 },
+	{ CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0 },
+	{ CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0 },
+	{ CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0 },
+	{ CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0 },
+	{ CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0 },
+	{ CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0 },
+};
+static int resistance_tbl_idx;
+static int mean_resistance[3];
+static int stddev_resistance[3];
+static int ub[3];
+static int lb[3];
+
 enum phase {
 	PHASE_UNKNOWN = -1,
+	PHASE_PRECHARGE,
 	PHASE_CC,
 	PHASE_CV_TRIP,
 	PHASE_CV_COMPLETE,
@@ -65,16 +95,104 @@ __overridable void board_ocpc_init(struct ocpc_data *ocpc)
 {
 }
 
+static enum ec_error_list ocpc_precharge_enable(bool enable);
+
+static void calc_resistance_stats(struct ocpc_data *ocpc)
+{
+	int i;
+	int j;
+	int sum;
+	int cols = 3;
+	int act_chg = ocpc->active_chg_chip;
+
+	/* Only perform separate stats on Rsys and Rbatt if necessary. */
+	if ((ocpc->chg_flags[act_chg] & OCPC_NO_ISYS_MEAS_CAP))
+		cols = 1;
+
+	/* Calculate mean */
+	for (i = 0; i < cols; i++) {
+		sum = 0;
+		for (j = 0; j < NUM_RESISTANCE_SAMPLES; j++) {
+			sum += resistance_tbl[j][i];
+			CPRINTF_DBG("%d ", resistance_tbl[j][i]);
+		}
+		CPRINTF_DBG("\n");
+
+		mean_resistance[i] = sum / NUM_RESISTANCE_SAMPLES;
+
+		/* Calculate standard deviation */
+		sum = 0;
+		for (j = 0; j < NUM_RESISTANCE_SAMPLES; j++)
+			sum += POW2(resistance_tbl[j][i] - mean_resistance[i]);
+
+		stddev_resistance[i] =
+			fp_sqrtf(INT_TO_FP(sum / NUM_RESISTANCE_SAMPLES));
+		stddev_resistance[i] = FP_TO_INT(stddev_resistance[i]);
+		/*
+		 * Don't let our stddev collapse to 0 to continually consider
+		 * new values.
+		 */
+		stddev_resistance[i] = MAX(stddev_resistance[i], 1);
+		CPRINTS_DBG("%d: mean: %d stddev: %d", i, mean_resistance[i],
+			    stddev_resistance[i]);
+		lb[i] = MAX(0, mean_resistance[i] - (3 * stddev_resistance[i]));
+		ub[i] = mean_resistance[i] + (3 * stddev_resistance[i]);
+	}
+}
+
+static bool is_within_range(struct ocpc_data *ocpc, int combined, int rbatt,
+			    int rsys)
+{
+	int act_chg = ocpc->active_chg_chip;
+	bool valid;
+
+	/* Discard measurements not within a 6 std. dev. window. */
+	if ((ocpc->chg_flags[act_chg] & OCPC_NO_ISYS_MEAS_CAP)) {
+		/* We only know the combined Rsys+Rbatt */
+		valid = (combined > 0) && (combined <= ub[COMBINED_IDX]) &&
+			(combined >= lb[COMBINED_IDX]);
+	} else {
+		valid = (rsys <= ub[RSYS_IDX]) && (rsys >= lb[RSYS_IDX]) &&
+			(rbatt <= ub[RBATT_IDX]) && (rbatt >= lb[RBATT_IDX]) &&
+			(rsys > 0) && (rbatt > 0);
+	}
+
+	if (!valid)
+		CPRINTS_DBG("Discard Rc:%d Rb:%d Rs:%d", combined, rbatt, rsys);
+
+	return valid;
+}
+
 enum ec_error_list ocpc_calc_resistances(struct ocpc_data *ocpc,
 					 struct batt_params *battery)
 {
-	int act_chg = ocpc->active_chg_chip;
+	int act_chg;
+	static bool seeded;
+	static int initial_samples;
+	int combined;
+	int rsys = -1;
+	int rbatt = -1;
+
+#ifdef TEST_BUILD
+	/* Mechanism for resetting static vars in tests */
+	if (!ocpc && !battery) {
+		seeded = false;
+		initial_samples = 0;
+
+		return EC_SUCCESS;
+	}
+#endif
+
+	act_chg = ocpc->active_chg_chip;
 
 	/*
 	 * In order to actually calculate the resistance, we need to make sure
-	 * we're actually charging the battery at a significant rate.
+	 * we're actually charging the battery at a significant rate.  The LSB
+	 * of a charger IC can be as high as 96mV.  Assuming a resistance of 60
+	 * mOhms, we would need a current of 1666mA to have a voltage delta of
+	 * 100mV.
 	 */
-	if ((battery->current <= 1000) ||
+	if ((battery->current <= 1666) ||
 	    (!(ocpc->chg_flags[act_chg] & OCPC_NO_ISYS_MEAS_CAP) &&
 	     (ocpc->isys_ma <= 0)) ||
 	    (ocpc->vsys_aux_mv < ocpc->vsys_mv)) {
@@ -93,25 +211,59 @@ enum ec_error_list ocpc_calc_resistances(struct ocpc_data *ocpc,
 		 * There's no provision to measure Isys, so we cannot separate
 		 * out Rsys from Rbatt.
 		 */
-		ocpc->combined_rsys_rbatt_mo = ((ocpc->vsys_aux_mv -
-						 battery->voltage) * 1000) /
-						 battery->current;
+		combined = ((ocpc->vsys_aux_mv - battery->voltage) * 1000) /
+			   battery->current;
+	} else {
+		rsys = ((ocpc->vsys_aux_mv - ocpc->vsys_mv) * 1000) /
+		       ocpc->isys_ma;
+		rbatt = ((ocpc->vsys_mv - battery->voltage) * 1000) /
+			battery->current;
+		combined = rsys + rbatt;
+	}
+
+	/* Discard measurements not within a 6 std dev window. */
+	if ((!seeded) ||
+	    (seeded && is_within_range(ocpc, combined, rbatt, rsys))) {
+		if (!(ocpc->chg_flags[act_chg] & OCPC_NO_ISYS_MEAS_CAP)) {
+			resistance_tbl[resistance_tbl_idx][RSYS_IDX] =
+				MAX(rsys, 0);
+			resistance_tbl[resistance_tbl_idx][RBATT_IDX] =
+				MAX(rbatt, CONFIG_OCPC_DEF_RBATT_MOHMS);
+		}
+		resistance_tbl[resistance_tbl_idx][COMBINED_IDX] =
+			MAX(combined, CONFIG_OCPC_DEF_RBATT_MOHMS);
+		calc_resistance_stats(ocpc);
+		resistance_tbl_idx =
+			(resistance_tbl_idx + 1) % NUM_RESISTANCE_SAMPLES;
+	}
+
+	if (seeded) {
+		ocpc->combined_rsys_rbatt_mo =
+			MAX(mean_resistance[COMBINED_IDX],
+			    CONFIG_OCPC_DEF_RBATT_MOHMS);
+
+		if (!(ocpc->chg_flags[act_chg] & OCPC_NO_ISYS_MEAS_CAP)) {
+			ocpc->rsys_mo = mean_resistance[RSYS_IDX];
+			ocpc->rbatt_mo = MAX(mean_resistance[RBATT_IDX],
+					     CONFIG_OCPC_DEF_RBATT_MOHMS);
+			CPRINTS_DBG("Rsys: %dmOhm Rbatt: %dmOhm", ocpc->rsys_mo,
+				    ocpc->rbatt_mo);
+		}
+
 		CPRINTS_DBG("Rsys+Rbatt: %dmOhm", ocpc->combined_rsys_rbatt_mo);
 	} else {
-		ocpc->rsys_mo = ((ocpc->vsys_aux_mv - ocpc->vsys_mv) * 1000) /
-				 ocpc->isys_ma;
-		ocpc->rbatt_mo = ((ocpc->vsys_mv - battery->voltage) * 1000) /
-				 battery->current;
-		ocpc->combined_rsys_rbatt_mo = ocpc->rsys_mo + ocpc->rbatt_mo;
-		CPRINTS_DBG("Rsys: %dmOhm Rbatt: %dmOhm", ocpc->rsys_mo,
-			    ocpc->rbatt_mo);
+		seeded = ++initial_samples >= (2 * NUM_RESISTANCE_SAMPLES) ?
+				 true :
+				 false;
 	}
+
 	return EC_SUCCESS;
 }
 
-int ocpc_config_secondary_charger(int *desired_input_current,
+int ocpc_config_secondary_charger(int *desired_charger_input_current,
 				  struct ocpc_data *ocpc,
-				  int voltage_mv, int current_ma)
+				  int desired_batt_voltage_mv,
+				  int desired_batt_current_ma)
 {
 	int rv = EC_SUCCESS;
 	struct batt_params batt;
@@ -120,6 +272,7 @@ int ocpc_config_secondary_charger(int *desired_input_current,
 	int vsys_target = 0;
 	int drive = 0;
 	int i_ma = 0;
+	static int i_ma_CC_CV;
 	int min_vsys_target;
 	int error = 0;
 	int derivative = 0;
@@ -131,6 +284,8 @@ int ocpc_config_secondary_charger(int *desired_input_current,
 	int i_step;
 	static timestamp_t delay;
 	int i, step, loc;
+	bool icl_reached = false;
+	static timestamp_t precharge_exit;
 
 	/*
 	 * There's nothing to do if we're not using this charger.  Should
@@ -144,8 +299,8 @@ int ocpc_config_secondary_charger(int *desired_input_current,
 
 	batt_info = battery_get_info();
 
-	if (current_ma == 0) {
-		vsys_target = voltage_mv;
+	if (desired_batt_current_ma == 0) {
+		vsys_target = desired_batt_voltage_mv;
 		goto set_vsys;
 	}
 
@@ -176,8 +331,8 @@ int ocpc_config_secondary_charger(int *desired_input_current,
 	if (!timestamp_expired(delay, NULL))
 		return EC_ERROR_BUSY;
 
-	result = charger_set_vsys_compensation(chgnum, ocpc, current_ma,
-					       voltage_mv);
+	result = charger_set_vsys_compensation(
+		chgnum, ocpc, desired_batt_current_ma, desired_batt_voltage_mv);
 	switch (result) {
 	case EC_SUCCESS:
 		/* No further action required, so we're done here. */
@@ -196,10 +351,10 @@ int ocpc_config_secondary_charger(int *desired_input_current,
 
 	if (ocpc->last_vsys == OCPC_UNINIT) {
 		ph = PHASE_UNKNOWN;
+		precharge_exit.val = 0;
 		iterations = 0;
 	}
 
-
 	/*
 	 * We need to induce a current flow that matches the requested current
 	 * by raising VSYS.  Let's start by getting the latest data that we
@@ -210,12 +365,12 @@ int ocpc_config_secondary_charger(int *desired_input_current,
 	ocpc_get_adcs(ocpc);
 	charger_get_params(&charger);
 
-
 	/*
 	 * If the system is in S5/G3, we can calculate the board and battery
 	 * resistances.
 	 */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF |
+			     CHIPSET_STATE_ANY_SUSPEND)) {
 		/*
 		 * In the first few iterations of the loop, charging isn't
 		 * stable/correct so making the calculation then leads to some
@@ -233,11 +388,58 @@ int ocpc_config_secondary_charger(int *desired_input_current,
 
 	/* Set our current target accordingly. */
 	if (batt.desired_voltage) {
-		if (batt.voltage < batt.desired_voltage) {
-			if (ph < PHASE_CV_TRIP)
+		if (((batt.voltage < batt_info->voltage_min) ||
+		     ((batt.voltage < batt_info->voltage_normal) &&
+		      (desired_batt_current_ma >= 0) &&
+		      (desired_batt_current_ma <=
+		       batt_info->precharge_current))) &&
+		    (ph != PHASE_PRECHARGE)) {
+			/*
+			 * If the charger IC doesn't support the linear charge
+			 * feature, proceed to the CC phase.
+			 */
+			result = ocpc_precharge_enable(true);
+			if (result == EC_ERROR_UNIMPLEMENTED) {
+				ph = PHASE_CC;
+			} else if (result == EC_SUCCESS) {
+				CPRINTS("OCPC: Enabling linear precharge");
+				ph = PHASE_PRECHARGE;
+				i_ma = desired_batt_current_ma;
+			}
+		} else if (batt.voltage < batt.desired_voltage) {
+			if ((ph == PHASE_PRECHARGE) &&
+			    (desired_batt_current_ma >
+			     batt_info->precharge_current)) {
+				/*
+				 * Precharge phase is complete.  Now set the
+				 * target VSYS to the battery voltage to prevent
+				 * a large current spike during the transition.
+				 */
+				/*
+				 * If we'd like to exit precharge, let's wait a
+				 * short delay.
+				 */
+				if (!precharge_exit.val) {
+					CPRINTS("OCPC: Preparing to exit "
+						"precharge");
+					precharge_exit = get_time();
+					precharge_exit.val += 3 * SECOND;
+				}
+				if (timestamp_expired(precharge_exit, NULL)) {
+					CPRINTS("OCPC: Precharge complete");
+					charger_set_voltage(CHARGER_SECONDARY,
+							    batt.voltage);
+					ocpc->last_vsys = batt.voltage;
+					ocpc_precharge_enable(false);
+					ph = PHASE_CC;
+					precharge_exit.val = 0;
+				}
+			}
+
+			if ((ph != PHASE_PRECHARGE) && (ph < PHASE_CV_TRIP))
 				ph = PHASE_CC;
-			i_ma = batt.desired_current;
-		} else{
+			i_ma = desired_batt_current_ma;
+		} else {
 			/*
 			 * Once the battery voltage reaches the desired voltage,
 			 * we should note that we've reached the CV step and set
@@ -245,7 +447,8 @@ int ocpc_config_secondary_charger(int *desired_input_current,
 			 */
 			i_ma = batt.current;
 			ph = ph == PHASE_CC ? PHASE_CV_TRIP : PHASE_CV_COMPLETE;
-
+			if (ph == PHASE_CV_TRIP)
+				i_ma_CC_CV = batt.current;
 		}
 	}
 
@@ -265,8 +468,18 @@ int ocpc_config_secondary_charger(int *desired_input_current,
 	 */
 	if (ocpc->last_vsys != OCPC_UNINIT) {
 		error = i_ma - batt.current;
+
+		/* Uses charger input error if controller is proportional only.
+		 */
+		if ((k_i == 0) && (k_d == 0)) {
+			int charger_input_error =
+				(*desired_charger_input_current -
+				 ocpc->secondary_ibus_ma);
+			error = MIN(error, charger_input_error);
+		}
+
 		/* Add some hysteresis. */
-		if (ABS(error) < i_step)
+		if (ABS(error) < (i_step / 2))
 			error = 0;
 
 		/* Make a note if we're significantly over target. */
@@ -275,7 +488,7 @@ int ocpc_config_secondary_charger(int *desired_input_current,
 
 		derivative = error - ocpc->last_error;
 		ocpc->last_error = error;
-		ocpc->integral +=  error;
+		ocpc->integral += error;
 		if (ocpc->integral > 500)
 			ocpc->integral = 500;
 	}
@@ -294,50 +507,80 @@ int ocpc_config_secondary_charger(int *desired_input_current,
 	CPRINTS_DBG("min_vsys_target = %d", min_vsys_target);
 
 	/* Obtain the drive from our PID controller. */
-	if (ocpc->last_vsys != OCPC_UNINIT) {
+	if ((ocpc->last_vsys != OCPC_UNINIT) && (ph > PHASE_PRECHARGE)) {
 		drive = (k_p * error / k_p_div) +
 			(k_i * ocpc->integral / k_i_div) +
 			(k_d * derivative / k_d_div);
 		/*
-		 * Let's limit upward transitions to 200mV.  It's okay to reduce
+		 * Let's limit upward transitions to 10mV.  It's okay to reduce
 		 * VSYS rather quickly, but we'll be conservative on
 		 * increasing VSYS.
 		 */
-		if (drive > 200)
-			drive = 200;
+		if (drive > drive_limit)
+			drive = drive_limit;
 		CPRINTS_DBG("drive = %d", drive);
 	}
 
+	CPRINTS_DBG("##DATA = %d %d %d %d %d %d %d", batt.desired_current,
+		    batt.current, *desired_charger_input_current,
+		    ocpc->secondary_ibus_ma, error, ocpc->last_vsys, drive);
+
+	/*
+	 * For the pre-charge phase, simply keep the VSYS target at the desired
+	 * voltage.
+	 */
+	if (ph == PHASE_PRECHARGE)
+		vsys_target = batt.desired_voltage;
+
 	/*
 	 * Adjust our VSYS target by applying the calculated drive.  Note that
 	 * we won't apply our drive the first time through this function such
 	 * that we can determine our initial error.
 	 */
-	if (ocpc->last_vsys != OCPC_UNINIT)
+	if ((ocpc->last_vsys != OCPC_UNINIT) && (ph > PHASE_PRECHARGE))
 		vsys_target = ocpc->last_vsys + drive;
 
 	/*
 	 * Once we're in the CV region, all we need to do is keep VSYS at the
 	 * desired voltage.
 	 */
-	if (ph >= PHASE_CV_TRIP)
-		vsys_target = batt.desired_voltage +
-				((batt_info->precharge_current *
-				  ocpc->combined_rsys_rbatt_mo) / 1000);
+	if (ph == PHASE_CV_TRIP) {
+		vsys_target =
+			batt.desired_voltage +
+			((i_ma_CC_CV * ocpc->combined_rsys_rbatt_mo) / 1000);
+		CPRINTS_DBG("i_ma_CC_CV = %d", i_ma_CC_CV);
+	}
+	if (ph == PHASE_CV_COMPLETE)
+		vsys_target =
+			batt.desired_voltage + ((batt_info->precharge_current *
+						 ocpc->combined_rsys_rbatt_mo) /
+						1000);
 
 	/*
 	 * Ensure VSYS is no higher than the specified maximum battery voltage
 	 * plus the voltage drop across the system.
 	 */
-	vsys_target = CLAMP(vsys_target, min_vsys_target,
-			    batt_info->voltage_max +
-			    (i_ma * ocpc->combined_rsys_rbatt_mo / 1000));
+	vsys_target =
+		CLAMP(vsys_target, min_vsys_target,
+		      batt_info->voltage_max +
+			      (i_ma * ocpc->combined_rsys_rbatt_mo / 1000));
 
 	/* If we're input current limited, we cannot increase VSYS any more. */
 	CPRINTS_DBG("OCPC: Inst. Input Current: %dmA (Limit: %dmA)",
-		    ocpc->secondary_ibus_ma, *desired_input_current);
-	if ((ocpc->secondary_ibus_ma >= (*desired_input_current * 95 / 100)) &&
-	    (vsys_target > ocpc->last_vsys) &&
+		    ocpc->secondary_ibus_ma, *desired_charger_input_current);
+
+	if (charger_is_icl_reached(chgnum, &icl_reached) != EC_SUCCESS) {
+		/*
+		 * If the charger doesn't support telling us, assume that the
+		 * input current limit is reached if we're consuming more than
+		 * 95% of the limit.
+		 */
+		if (ocpc->secondary_ibus_ma >=
+		    (*desired_charger_input_current * 95 / 100))
+			icl_reached = true;
+	}
+
+	if (icl_reached && (vsys_target > ocpc->last_vsys) &&
 	    (ocpc->last_vsys != OCPC_UNINIT)) {
 		if (!prev_limited)
 			CPRINTS("Input limited! Not increasing VSYS");
@@ -371,7 +614,7 @@ int ocpc_config_secondary_charger(int *desired_input_current,
 				CPRINT_VIZ(i == loc ? "o" : "-");
 		}
 		CPRINT_VIZ("] (actual)%dmA (desired)%dmA\n", batt.current,
-			   batt.desired_current);
+			   i_ma);
 	}
 
 	return rv;
@@ -390,7 +633,7 @@ void ocpc_get_adcs(struct ocpc_data *ocpc)
 		ocpc->primary_ibus_ma = val;
 
 	val = 0;
-	if (!charger_get_voltage(CHARGER_PRIMARY, &val))
+	if (!charger_get_actual_voltage(CHARGER_PRIMARY, &val))
 		ocpc->vsys_mv = val;
 
 	if (board_get_charger_chip_count() <= CHARGER_SECONDARY) {
@@ -410,21 +653,67 @@ void ocpc_get_adcs(struct ocpc_data *ocpc)
 		ocpc->secondary_ibus_ma = val;
 
 	val = 0;
-	if (!charger_get_voltage(CHARGER_SECONDARY, &val))
+	if (!charger_get_actual_voltage(CHARGER_SECONDARY, &val))
 		ocpc->vsys_aux_mv = val;
 
 	val = 0;
-	if (!charger_get_current(CHARGER_SECONDARY, &val))
+	if (!charger_get_actual_current(CHARGER_SECONDARY, &val))
 		ocpc->isys_ma = val;
 }
 
-__overridable void ocpc_get_pid_constants(int *kp, int *kp_div,
-					  int *ki, int *ki_div,
-					  int *kd, int *kd_div)
+__overridable void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+					  int *ki_div, int *kd, int *kd_div)
+{
+}
+
+static enum ec_error_list ocpc_precharge_enable(bool enable)
+{
+	/* Enable linear charging on the primary charger IC. */
+	int rv = charger_enable_linear_charge(CHARGER_PRIMARY, enable);
+
+	if (rv)
+		CPRINTS("OCPC: Failed to %sble linear charge!",
+			enable ? "ena" : "dis");
+
+	return rv;
+}
+
+void ocpc_reset(struct ocpc_data *ocpc)
 {
+	struct batt_params batt;
+	int voltage;
+
+	battery_get_params(&batt);
+	ocpc->integral = 0;
+	ocpc->last_error = 0;
+	ocpc->last_vsys = OCPC_UNINIT;
+
+	/*
+	 * Initialize the VSYS target on the aux chargers to the current battery
+	 * voltage to avoid a large spike.
+	 */
+	if (ocpc->active_chg_chip > CHARGER_PRIMARY) {
+		voltage = (batt.voltage > 0 &&
+			   !(batt.flags & BATT_FLAG_BAD_VOLTAGE)) ?
+				  batt.voltage :
+				  battery_get_info()->voltage_normal;
+#ifdef CONFIG_CHARGER_NARROW_VDC
+		if (voltage < battery_get_info()->voltage_min)
+			voltage = battery_get_info()->voltage_min;
+#endif
+		CPRINTS("OCPC: C%d Init VSYS to %dmV", ocpc->active_chg_chip,
+			voltage);
+		charger_set_voltage(ocpc->active_chg_chip, voltage);
+	}
+	/*
+	 * See(b:191347747) When linear precharge is enabled, it may affect
+	 * the charging behavior from the primary charger IC. Therefore as
+	 * a part of the reset process, we need to disable linear precharge.
+	 */
+	ocpc_precharge_enable(false);
 }
 
-static void ocpc_set_pid_constants(void)
+test_export_static void ocpc_set_pid_constants(void)
 {
 	ocpc_get_pid_constants(&k_p, &k_p_div, &k_i, &k_i_div, &k_d, &k_d_div);
 }
@@ -443,7 +732,7 @@ void ocpc_init(struct ocpc_data *ocpc)
 	board_ocpc_init(ocpc);
 }
 
-static int command_ocpcdebug(int argc, char **argv)
+static int command_ocpcdebug(int argc, const char **argv)
 {
 	if (argc < 2)
 		return EC_ERROR_PARAM_COUNT;
@@ -473,7 +762,7 @@ DECLARE_SAFE_CONSOLE_COMMAND(ocpcdebug, command_ocpcdebug,
 			     "Each segment is 5% of current target. All shows"
 			     " both. Disable shows no debug output.");
 
-static int command_ocpcpid(int argc, char **argv)
+static int command_ocpcpid(int argc, const char **argv)
 {
 	int *num, *denom;
 
@@ -510,3 +799,42 @@ static int command_ocpcpid(int argc, char **argv)
 DECLARE_SAFE_CONSOLE_COMMAND(ocpcpid, command_ocpcpid,
 			     "[<k/p/d> <numerator> <denominator>]",
 			     "Show/Set PID constants for OCPC PID loop");
+
+static int command_ocpcdrvlmt(int argc, const char **argv)
+{
+	if (argc == 2) {
+		drive_limit = atoi(argv[1]);
+	}
+
+	/* Print the current constants */
+	ccprintf("Drive Limit = %d\n", drive_limit);
+	return EC_SUCCESS;
+}
+DECLARE_SAFE_CONSOLE_COMMAND(ocpcdrvlmt, command_ocpcdrvlmt, "[<drive_limit>]",
+			     "Show/Set drive limit for OCPC PID loop");
+
+#ifdef TEST_BUILD
+int test_ocpc_get_viz_output(void)
+{
+	return viz_output;
+}
+int test_ocpc_get_debug_output(void)
+{
+	return debug_output;
+}
+void test_ocpc_reset_resistance_state(void)
+{
+	for (int i = 0; i < NUM_RESISTANCE_SAMPLES; i++) {
+		resistance_tbl[i][0] = CONFIG_OCPC_DEF_RBATT_MOHMS;
+		resistance_tbl[i][1] = CONFIG_OCPC_DEF_RBATT_MOHMS;
+		resistance_tbl[i][2] = 0;
+	}
+
+	resistance_tbl_idx = 0;
+
+	memset(mean_resistance, 0, sizeof(mean_resistance));
+	memset(stddev_resistance, 0, sizeof(stddev_resistance));
+	memset(ub, 0, sizeof(ub));
+	memset(lb, 0, sizeof(lb));
+}
+#endif
diff --git a/common/onewire.c b/common/onewire.c
index 43080d096e..0b109bbdcd 100644
--- a/common/onewire.c
+++ b/common/onewire.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,16 +16,19 @@
  * Note that these timing are actually _longer_ than legacy 1-wire standard
  * speed because we're running the 1-wire bus at 3.3V instead of 5V.
  */
-#define T_RSTL 602  /* Reset low pulse; 600-960 us */
-#define T_MSP   72  /* Presence detect sample time; 70-75 us */
-#define T_RSTH (68 + 260 + 5 + 2) /* Reset high; tPDHmax + tPDLmax + tRECmin */
-#define T_SLOT  70  /* Timeslot; >67 us */
-#define T_W0L   63  /* Write 0 low; 62-120 us */
-#define T_W1L    7  /* Write 1 low; 5-15 us */
-#define T_RL     7  /* Read low; 5-15 us */
-#define T_MSR    9  /* Read sample time; <15 us.  Must be at least 200 ns after
-		     * T_RL since that's how long the signal takes to be pulled
-		     * up on our board.  */
+#define T_RSTL 602 /* Reset low pulse; 600-960 us */
+#define T_MSP 72 /* Presence detect sample time; 70-75 us */
+#define T_RSTH                                                        \
+	(68 + 260 + 5 + 2) /* Reset high; tPDHmax + tPDLmax + tRECmin \
+			    */
+#define T_SLOT 70 /* Timeslot; >67 us */
+#define T_W0L 63 /* Write 0 low; 62-120 us */
+#define T_W1L 7 /* Write 1 low; 5-15 us */
+#define T_RL 7 /* Read low; 5-15 us */
+#define T_MSR                                                         \
+	9 /* Read sample time; <15 us.  Must be at least 200 ns after \
+	   * T_RL since that's how long the signal takes to be pulled \
+	   * up on our board.  */
 
 /**
  * Output low on the bus for <usec> us, then switch back to open-drain input.
@@ -54,7 +57,10 @@ static int readbit(void)
 	/* Output low */
 	output0(T_RL);
 
-	/* Delay to let slave release the line if it wants to send a 1-bit */
+	/*
+	 * Delay to let peripheral release the line if it wants to send
+	 * a 1-bit
+	 */
 	udelay(T_MSR - T_RL);
 
 	/* Read bit */
@@ -95,19 +101,18 @@ static void writebit(int bit)
 		interrupt_enable();
 		udelay(T_SLOT - T_W0L);
 	}
-
 }
 
 int onewire_reset(void)
 {
-	/* Start transaction with master reset pulse */
+	/* Start transaction with controller reset pulse */
 	output0(T_RSTL);
 
 	/* Wait for presence detect sample time.
 	 *
 	 * (Alternately, we could poll waiting for a 1-bit indicating our pulse
 	 * has let go, then poll up to max time waiting for a 0-bit indicating
-	 * the slave has responded.)
+	 * the peripheral has responded.)
 	 */
 	udelay(T_MSP);
 
@@ -130,7 +135,7 @@ int onewire_read(void)
 	int i;
 
 	for (i = 0; i < 8; i++)
-		data |= readbit() << i;  /* LSB first */
+		data |= readbit() << i; /* LSB first */
 
 	return data;
 }
@@ -140,5 +145,5 @@ void onewire_write(int data)
 	int i;
 
 	for (i = 0; i < 8; i++)
-		writebit((data >> i) & 0x01);  /* LSB first */
+		writebit((data >> i) & 0x01); /* LSB first */
 }
diff --git a/common/online_calibration.c b/common/online_calibration.c
index ca7a5a620d..a56aa0dce7 100644
--- a/common/online_calibration.c
+++ b/common/online_calibration.c
@@ -1,21 +1,21 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "accel_cal.h"
 #include "accelgyro.h"
 #include "atomic.h"
-#include "hwtimer.h"
-#include "online_calibration.h"
 #include "common.h"
+#include "ec_commands.h"
+#include "gyro_cal.h"
+#include "hwtimer.h"
 #include "mag_cal.h"
+#include "mkbp_event.h"
+#include "online_calibration.h"
+#include "task.h"
 #include "util.h"
 #include "vec3.h"
-#include "task.h"
-#include "ec_commands.h"
-#include "accel_cal.h"
-#include "mkbp_event.h"
-#include "gyro_cal.h"
 
 #define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ##args)
 
@@ -61,7 +61,7 @@ static void data_int16_to_fp(const struct motion_sensor_t *s,
 			     const int16_t *data, fpv3_t out)
 {
 	int i;
-	fp_t range = INT_TO_FP(s->drv->get_range(s));
+	fp_t range = INT_TO_FP(s->current_range);
 
 	for (i = 0; i < 3; ++i) {
 		fp_t v = INT_TO_FP((int32_t)data[i]);
@@ -77,17 +77,16 @@ static void data_fp_to_int16(const struct motion_sensor_t *s, const fpv3_t data,
 			     int16_t *out)
 {
 	int i;
-	fp_t range = INT_TO_FP(s->drv->get_range(s));
+	fp_t range = INT_TO_FP(s->current_range);
 
 	for (i = 0; i < 3; ++i) {
 		int32_t iv;
 		fp_t v = fp_div(data[i], range);
 
-		v = fp_mul(v, INT_TO_FP((data[i] >= INT_TO_FP(0)) ? 0x7fff :
-								    0x8000));
+		v = fp_mul(v, INT_TO_FP(0x7fff));
 		iv = FP_TO_INT(v);
 		/* Check for overflow */
-		out[i] = CLAMP(iv, (int32_t)0xffff8000, (int32_t)0x00007fff);
+		out[i] = ec_motion_sensor_clamp_i16(iv);
 	}
 }
 
@@ -98,28 +97,36 @@ static void data_fp_to_int16(const struct motion_sensor_t *s, const fpv3_t data,
  *
  * @param sensor Pointer to the gyroscope sensor to check.
  */
-static void check_gyro_cal_new_bias(struct motion_sensor_t *sensor)
+static bool check_gyro_cal_new_bias(struct motion_sensor_t *sensor,
+				    fpv3_t bias_out)
 {
 	struct online_calib_data *calib_data =
 		(struct online_calib_data *)sensor->online_calib_data;
 	struct gyro_cal_data *data =
 		(struct gyro_cal_data *)calib_data->type_specific_data;
-	size_t sensor_num = motion_sensors - sensor;
 	int temp_out;
-	fpv3_t bias_out;
 	uint32_t timestamp_out;
 
 	/* Check that we have a new bias. */
 	if (data == NULL || calib_data == NULL ||
 	    !gyro_cal_new_bias_available(&data->gyro_cal))
-		return;
+		return false;
 
 	/* Read the calibration values. */
 	gyro_cal_get_bias(&data->gyro_cal, bias_out, &temp_out, &timestamp_out);
+	return true;
+}
+
+static void set_gyro_cal_cache_values(struct motion_sensor_t *sensor,
+				      fpv3_t bias)
+{
+	size_t sensor_num = sensor - motion_sensors;
+	struct online_calib_data *calib_data =
+		(struct online_calib_data *)sensor->online_calib_data;
 
 	mutex_lock(&g_calib_cache_mutex);
-	/* Convert result to the right scale. */
-	data_fp_to_int16(sensor, bias_out, calib_data->cache);
+	/* Convert result to the right scale and save to cache. */
+	data_fp_to_int16(sensor, bias, calib_data->cache);
 	/* Set valid and dirty. */
 	sensor_calib_cache_valid_map |= BIT(sensor_num);
 	sensor_calib_cache_dirty_map |= BIT(sensor_num);
@@ -140,6 +147,7 @@ static void update_gyro_cal(struct motion_sensor_t *sensor, fpv3_t data,
 			    uint32_t timestamp)
 {
 	int i;
+	fpv3_t gyro_cal_data_out;
 
 	/*
 	 * Find gyroscopes, while we don't currently have instance where more
@@ -151,6 +159,7 @@ static void update_gyro_cal(struct motion_sensor_t *sensor, fpv3_t data,
 		struct gyro_cal_data *gyro_cal_data =
 			(struct gyro_cal_data *)
 				s->online_calib_data->type_specific_data;
+		bool has_new_gyro_cal_bias = false;
 
 		/*
 		 * If we're not looking at a gyroscope OR if the calibration
@@ -168,14 +177,19 @@ static void update_gyro_cal(struct motion_sensor_t *sensor, fpv3_t data,
 			gyro_cal_update_accel(&gyro_cal_data->gyro_cal,
 					      timestamp, data[X], data[Y],
 					      data[Z]);
-			check_gyro_cal_new_bias(s);
+			has_new_gyro_cal_bias =
+				check_gyro_cal_new_bias(s, gyro_cal_data_out);
 		} else if (sensor->type == MOTIONSENSE_TYPE_MAG &&
 			   gyro_cal_data->mag_sensor_id ==
 				   sensor - motion_sensors) {
 			gyro_cal_update_mag(&gyro_cal_data->gyro_cal, timestamp,
 					    data[X], data[Y], data[Z]);
-			check_gyro_cal_new_bias(s);
+			has_new_gyro_cal_bias =
+				check_gyro_cal_new_bias(s, gyro_cal_data_out);
 		}
+
+		if (has_new_gyro_cal_bias)
+			set_gyro_cal_cache_values(s, gyro_cal_data_out);
 	}
 }
 
@@ -187,11 +201,8 @@ void online_calibration_init(void)
 		struct motion_sensor_t *s = motion_sensors + i;
 		void *type_specific_data = NULL;
 
-		if (s->online_calib_data) {
-			s->online_calib_data->last_temperature = -1;
-			type_specific_data =
-				s->online_calib_data->type_specific_data;
-		}
+		s->online_calib_data->last_temperature = -1;
+		type_specific_data = s->online_calib_data->type_specific_data;
 
 		if (!type_specific_data)
 			continue;
@@ -228,16 +239,18 @@ bool online_calibration_has_new_values(void)
 	return has_dirty;
 }
 
-bool online_calibration_read(int sensor_num, int16_t out[3])
+bool online_calibration_read(struct motion_sensor_t *sensor,
+			     struct ec_response_online_calibration_data *out)
 {
+	int sensor_num = sensor - motion_sensors;
 	bool has_valid;
 
 	mutex_lock(&g_calib_cache_mutex);
 	has_valid = (sensor_calib_cache_valid_map & BIT(sensor_num)) != 0;
 	if (has_valid) {
 		/* Update data in out */
-		memcpy(out, motion_sensors[sensor_num].online_calib_data->cache,
-		       sizeof(out));
+		memcpy(out->data, sensor->online_calib_data->cache,
+		       sizeof(out->data));
 		/* Clear dirty bit */
 		sensor_calib_cache_dirty_map &= ~(1 << sensor_num);
 	}
@@ -250,31 +263,48 @@ int online_calibration_process_data(struct ec_response_motion_sensor_data *data,
 				    struct motion_sensor_t *sensor,
 				    uint32_t timestamp)
 {
-	size_t sensor_num = motion_sensors - sensor;
+	int sensor_num = sensor - motion_sensors;
 	int rc;
 	int temperature;
 	struct online_calib_data *calib_data;
+	fpv3_t fdata;
+	bool is_spoofed = IS_ENABLED(CONFIG_ONLINE_CALIB_SPOOF_MODE) &&
+			  (sensor->flags & MOTIONSENSE_FLAG_IN_SPOOF_MODE);
+	bool has_new_calibration_values = false;
+
+	/* Convert data to fp. */
+	data_int16_to_fp(sensor, data->data, fdata);
 
 	calib_data = sensor->online_calib_data;
 	switch (sensor->type) {
 	case MOTIONSENSE_TYPE_ACCEL: {
 		struct accel_cal *cal =
 			(struct accel_cal *)(calib_data->type_specific_data);
-		fpv3_t fdata;
 
-		/* Convert data to fp. */
-		data_int16_to_fp(sensor, data->data, fdata);
-
-		/* Possibly update the gyroscope calibration. */
-		update_gyro_cal(sensor, fdata, timestamp);
-
-		/* Temperature is required for accelerometer calibration. */
-		rc = get_temperature(sensor, &temperature);
-		if (rc != EC_SUCCESS)
-			return rc;
+		if (is_spoofed) {
+			/* Copy the data to the calibration result. */
+			cal->bias[X] = fdata[X];
+			cal->bias[Y] = fdata[Y];
+			cal->bias[Z] = fdata[Z];
+			has_new_calibration_values = true;
+		} else {
+			/* Possibly update the gyroscope calibration. */
+			update_gyro_cal(sensor, fdata, timestamp);
+
+			/*
+			 * Temperature is required for accelerometer
+			 * calibration.
+			 */
+			rc = get_temperature(sensor, &temperature);
+			if (rc != EC_SUCCESS)
+				return rc;
+
+			has_new_calibration_values = accel_cal_accumulate(
+				cal, timestamp, fdata[X], fdata[Y], fdata[Z],
+				temperature);
+		}
 
-		if (accel_cal_accumulate(cal, timestamp, fdata[X], fdata[Y],
-					 fdata[Z], temperature)) {
+		if (has_new_calibration_values) {
 			mutex_lock(&g_calib_cache_mutex);
 			/* Convert result to the right scale. */
 			data_fp_to_int16(sensor, cal->bias, calib_data->cache);
@@ -295,15 +325,21 @@ int online_calibration_process_data(struct ec_response_motion_sensor_data *data,
 			(int)data->data[Y],
 			(int)data->data[Z],
 		};
-		fpv3_t fdata;
 
-		/* Convert data to fp. */
-		data_int16_to_fp(sensor, data->data, fdata);
+		if (is_spoofed) {
+			/* Copy the data to the calibration result. */
+			cal->bias[X] = INT_TO_FP(idata[X]);
+			cal->bias[Y] = INT_TO_FP(idata[Y]);
+			cal->bias[Z] = INT_TO_FP(idata[Z]);
+			has_new_calibration_values = true;
+		} else {
+			/* Possibly update the gyroscope calibration. */
+			update_gyro_cal(sensor, fdata, timestamp);
 
-		/* Possibly update the gyroscope calibration. */
-		update_gyro_cal(sensor, fdata, timestamp);
+			has_new_calibration_values = mag_cal_update(cal, idata);
+		}
 
-		if (mag_cal_update(cal, idata)) {
+		if (has_new_calibration_values) {
 			mutex_lock(&g_calib_cache_mutex);
 			/* Copy the values */
 			calib_data->cache[X] = cal->bias[X];
@@ -319,21 +355,32 @@ int online_calibration_process_data(struct ec_response_motion_sensor_data *data,
 		break;
 	}
 	case MOTIONSENSE_TYPE_GYRO: {
-		fpv3_t fdata;
-
-		/* Temperature is required for gyro calibration. */
-		rc = get_temperature(sensor, &temperature);
-		if (rc != EC_SUCCESS)
-			return rc;
-
-		/* Convert data to fp. */
-		data_int16_to_fp(sensor, data->data, fdata);
+		if (is_spoofed) {
+			/*
+			 * Gyroscope uses fdata to store the calibration
+			 * result, so there's no need to copy anything.
+			 */
+			has_new_calibration_values = true;
+		} else {
+			struct gyro_cal_data *gyro_cal_data =
+				(struct gyro_cal_data *)
+					calib_data->type_specific_data;
+			struct gyro_cal *gyro_cal = &gyro_cal_data->gyro_cal;
+
+			/* Temperature is required for gyro calibration. */
+			rc = get_temperature(sensor, &temperature);
+			if (rc != EC_SUCCESS)
+				return rc;
+
+			/* Update gyroscope calibration. */
+			gyro_cal_update_gyro(gyro_cal, timestamp, fdata[X],
+					     fdata[Y], fdata[Z], temperature);
+			has_new_calibration_values =
+				check_gyro_cal_new_bias(sensor, fdata);
+		}
 
-		/* Update gyroscope calibration. */
-		gyro_cal_update_gyro(
-			&((struct gyro_cal_data *)calib_data->type_specific_data)->gyro_cal,
-			timestamp, fdata[X], fdata[Y], fdata[Z], temperature);
-		check_gyro_cal_new_bias(sensor);
+		if (has_new_calibration_values)
+			set_gyro_cal_cache_values(sensor, fdata);
 		break;
 	}
 	default:
diff --git a/common/panic_output.c b/common/panic_output.c
index 75c94223ce..5c2dce25d8 100644
--- a/common/panic_output.c
+++ b/common/panic_output.c
@@ -1,8 +1,9 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
 #include "cpu.h"
@@ -19,20 +20,24 @@
 #include "usb_console.h"
 #include "util.h"
 
+/*
+ * For host tests, use a static area for panic data.
+ */
+#ifdef CONFIG_BOARD_NATIVE_POSIX
+static struct panic_data zephyr_panic_data;
+#undef PANIC_DATA_PTR
+#undef CONFIG_PANIC_DATA_BASE
+#define PANIC_DATA_PTR (&zephyr_panic_data)
+#define CONFIG_PANIC_DATA_BASE (&zephyr_panic_data)
+#endif
 /* Panic data goes at the end of RAM. */
-static struct panic_data * const pdata_ptr = PANIC_DATA_PTR;
+static struct panic_data *const pdata_ptr = PANIC_DATA_PTR;
 
 /* Common SW Panic reasons strings */
-const char * const panic_sw_reasons[] = {
-#ifdef CONFIG_SOFTWARE_PANIC
-	"PANIC_SW_DIV_ZERO",
-	"PANIC_SW_STACK_OVERFLOW",
-	"PANIC_SW_PD_CRASH",
-	"PANIC_SW_ASSERT",
-	"PANIC_SW_WATCHDOG",
-	"PANIC_SW_RNG",
+const char *const panic_sw_reasons[] = {
+	"PANIC_SW_DIV_ZERO",   "PANIC_SW_STACK_OVERFLOW", "PANIC_SW_PD_CRASH",
+	"PANIC_SW_ASSERT",     "PANIC_SW_WATCHDOG",	  "PANIC_SW_RNG",
 	"PANIC_SW_PMIC_FAULT",
-#endif
 };
 
 /**
@@ -42,8 +47,7 @@ const char * const panic_sw_reasons[] = {
  */
 int panic_sw_reason_is_valid(uint32_t reason)
 {
-	return (IS_ENABLED(CONFIG_SOFTWARE_PANIC) &&
-		reason >= PANIC_SW_BASE &&
+	return (reason >= PANIC_SW_BASE &&
 		(reason - PANIC_SW_BASE) < ARRAY_SIZE(panic_sw_reasons));
 }
 
@@ -114,31 +118,32 @@ void panic_reboot(void)
 	system_reset(0);
 }
 
-#ifdef CONFIG_DEBUG_ASSERT_REBOOTS
+/* Complete the processing of a panic, after the initial message is shown */
+test_mockable_static
+#if !(defined(TEST_FUZZ) || defined(CONFIG_ZTEST))
+	noreturn
+#endif
+	void
+	complete_panic(int linenum)
+{
+	software_panic(PANIC_SW_ASSERT, linenum);
+}
+
 #ifdef CONFIG_DEBUG_ASSERT_BRIEF
 void panic_assert_fail(const char *fname, int linenum)
 {
 	panic_printf("\nASSERTION FAILURE at %s:%d\n", fname, linenum);
-#ifdef CONFIG_SOFTWARE_PANIC
-	software_panic(PANIC_SW_ASSERT, linenum);
-#else
-	panic_reboot();
-#endif
+	complete_panic(linenum);
 }
 #else
 void panic_assert_fail(const char *msg, const char *func, const char *fname,
 		       int linenum)
 {
-	panic_printf("\nASSERTION FAILURE '%s' in %s() at %s:%d\n",
-		     msg, func, fname, linenum);
-#ifdef CONFIG_SOFTWARE_PANIC
-	software_panic(PANIC_SW_ASSERT, linenum);
-#else
-	panic_reboot();
-#endif
+	panic_printf("\nASSERTION FAILURE '%s' in %s() at %s:%d\n", msg, func,
+		     fname, linenum);
+	complete_panic(linenum);
 }
 #endif
-#endif
 
 void panic(const char *msg)
 {
@@ -167,9 +172,13 @@ uintptr_t get_panic_data_start(void)
 	if (pdata_ptr->magic != PANIC_DATA_MAGIC)
 		return 0;
 
-	return ((uintptr_t)CONFIG_PANIC_DATA_BASE
-			   + CONFIG_PANIC_DATA_SIZE
-			   - pdata_ptr->struct_size);
+	if (IS_ENABLED(CONFIG_BOARD_NATIVE_POSIX))
+		return (uintptr_t)pdata_ptr;
+
+	/* LCOV_EXCL_START - Can't cover non posix lines (yet) */
+	return ((uintptr_t)CONFIG_PANIC_DATA_BASE + CONFIG_PANIC_DATA_SIZE -
+		pdata_ptr->struct_size);
+	/* LCOV_EXCL_STOP */
 }
 
 static uint32_t get_panic_data_size(void)
@@ -186,7 +195,20 @@ static uint32_t get_panic_data_size(void)
  * It can also delete panic data from previous boot, so this function
  * should be used when we are sure that we don't need it.
  */
-struct panic_data *get_panic_data_write(void)
+#ifdef CONFIG_BOARD_NATIVE_POSIX
+struct panic_data *test_get_panic_data_pointer(void)
+{
+	return pdata_ptr;
+}
+#endif
+
+__overridable uint32_t get_panic_stack_pointer(const struct panic_data *pdata)
+{
+	/* Not Implemented */
+	return 0;
+}
+
+test_mockable struct panic_data *get_panic_data_write(void)
 {
 	/*
 	 * Pointer to panic_data structure. It may not point to
@@ -194,8 +216,8 @@ struct panic_data *get_panic_data_write(void)
 	 * and magic is safe because it is always placed at the
 	 * end of RAM.
 	 */
-	struct panic_data * const pdata_ptr = PANIC_DATA_PTR;
-	const struct jump_data *jdata_ptr;
+	struct panic_data *const pdata_ptr = PANIC_DATA_PTR;
+	struct jump_data *jdata_ptr;
 	uintptr_t data_begin;
 	size_t move_size;
 	int delta;
@@ -231,8 +253,8 @@ struct panic_data *get_panic_data_write(void)
 	 * anything and can just return pdata_ptr (clear memory, set magic
 	 * and struct_size first).
 	 */
-	if (jdata_ptr->magic != JUMP_DATA_MAGIC ||
-	    jdata_ptr->version < 1 || jdata_ptr->version > 3) {
+	if (jdata_ptr->magic != JUMP_DATA_MAGIC || jdata_ptr->version < 1 ||
+	    jdata_ptr->version > 3) {
 		memset(pdata_ptr, 0, CONFIG_PANIC_DATA_SIZE);
 		pdata_ptr->magic = PANIC_DATA_MAGIC;
 		pdata_ptr->struct_size = CONFIG_PANIC_DATA_SIZE;
@@ -240,22 +262,34 @@ struct panic_data *get_panic_data_write(void)
 		return pdata_ptr;
 	}
 
+	move_size = 0;
 	if (jdata_ptr->version == 1)
 		move_size = JUMP_DATA_SIZE_V1;
 	else if (jdata_ptr->version == 2)
 		move_size = JUMP_DATA_SIZE_V2 + jdata_ptr->jump_tag_total;
 	else if (jdata_ptr->version == 3)
 		move_size = jdata_ptr->struct_size + jdata_ptr->jump_tag_total;
-	else {
-		/* Unknown jump data version - set move size to 0 */
-		move_size = 0;
+
+	/* Check if there's enough space for jump tags after move */
+	if (data_begin - move_size < JUMP_DATA_MIN_ADDRESS) {
+		/* Not enough room for jump tags, clear tags.
+		 * TODO(b/251190975): This failure should be reported
+		 * in the panic data structure for more visibility.
+		 */
+		/* LCOV_EXCL_START - JUMP_DATA_MIN_ADDRESS is 0 in test builds
+		 * and we cannot go negative by subtracting unsigned ints.
+		 */
+		move_size -= jdata_ptr->jump_tag_total;
+		jdata_ptr->jump_tag_total = 0;
+		/* LCOV_EXCL_STOP */
 	}
 
 	data_begin -= move_size;
 
 	if (move_size != 0) {
 		/* Move jump_tags and jump_data */
-		memmove((void *)(data_begin - delta), (void *)data_begin, move_size);
+		memmove((void *)(data_begin - delta), (void *)data_begin,
+			move_size);
 	}
 
 	/*
@@ -284,10 +318,18 @@ static void panic_init(void)
 DECLARE_HOOK(HOOK_INIT, panic_init, HOOK_PRIO_LAST);
 DECLARE_HOOK(HOOK_CHIPSET_RESET, panic_init, HOOK_PRIO_LAST);
 
-#ifdef CONFIG_CMD_STACKOVERFLOW
+#ifdef CONFIG_CMD_CRASH
+/*
+ * Disable infinite recursion warning, since we're intentionally doing that
+ * here.
+ */
+DISABLE_CLANG_WARNING("-Winfinite-recursion")
+#if __GNUC__ >= 12
+DISABLE_GCC_WARNING("-Winfinite-recursion")
+#endif
 static void stack_overflow_recurse(int n)
 {
-	ccprintf("+%d", n);
+	panic_printf("+%d", n);
 
 	/*
 	 * Force task context switch, since that's where we do stack overflow
@@ -295,20 +337,22 @@ static void stack_overflow_recurse(int n)
 	 */
 	msleep(10);
 
-	stack_overflow_recurse(n+1);
+	stack_overflow_recurse(n + 1);
 
 	/*
 	 * Do work after the recursion, or else the compiler uses tail-chaining
 	 * and we don't actually consume additional stack.
 	 */
-	ccprintf("-%d", n);
+	panic_printf("-%d", n);
 }
-#endif /* CONFIG_CMD_STACKOVERFLOW */
+ENABLE_CLANG_WARNING("-Winfinite-recursion")
+#if __GNUC__ >= 12
+ENABLE_GCC_WARNING("-Winfinite-recursion")
+#endif
 
 /*****************************************************************************/
 /* Console commands */
-#ifdef CONFIG_CMD_CRASH
-static int command_crash(int argc, char **argv)
+static int command_crash(int argc, const char **argv)
 {
 	if (argc < 2)
 		return EC_ERROR_PARAM1;
@@ -324,22 +368,36 @@ static int command_crash(int argc, char **argv)
 		volatile int zero = 0;
 
 		cflush();
-		ccprintf("%08x", 1 / zero);
-#ifdef CONFIG_CMD_STACKOVERFLOW
+		ccprintf("%08x", 1U / zero);
 	} else if (!strcasecmp(argv[1], "stack")) {
 		stack_overflow_recurse(1);
-#endif
 	} else if (!strcasecmp(argv[1], "unaligned")) {
 		volatile intptr_t unaligned_ptr = 0xcdef;
 		cflush();
 		ccprintf("%08x", *(volatile int *)unaligned_ptr);
 	} else if (!strcasecmp(argv[1], "watchdog")) {
-		while (1)
-			;
+		while (1) {
+/* Yield on native posix to avoid locking up the simulated sys clock */
+#ifdef CONFIG_ARCH_POSIX
+			k_cpu_idle();
+#endif
+		}
 	} else if (!strcasecmp(argv[1], "hang")) {
-		interrupt_disable();
-		while (1)
-			;
+		uint32_t lock_key = irq_lock();
+
+		while (1) {
+/* Yield on native posix to avoid locking up the simulated sys clock */
+#ifdef CONFIG_ARCH_POSIX
+			k_cpu_idle();
+#endif
+		}
+
+		/* Unreachable, but included for consistency */
+		irq_unlock(lock_key);
+	} else if (!strcasecmp(argv[1], "null")) {
+		volatile uintptr_t null_ptr = 0x0;
+		cflush();
+		ccprintf("%08x\n", *(volatile unsigned int *)null_ptr);
 	} else {
 		return EC_ERROR_PARAM1;
 	}
@@ -347,23 +405,41 @@ static int command_crash(int argc, char **argv)
 	/* Everything crashes, so shouldn't get back here */
 	return EC_ERROR_UNKNOWN;
 }
+
 DECLARE_CONSOLE_COMMAND(crash, command_crash,
-		"[assert | divzero | udivzero"
-#ifdef CONFIG_CMD_STACKOVERFLOW
-			" | stack"
-#endif
-			" | unaligned | watchdog | hang]",
-		"Crash the system (for testing)");
-#endif
+			"[assert | divzero | udivzero | stack"
+			" | unaligned | watchdog | hang | null]",
+			"Crash the system (for testing)");
+
+#ifdef TEST_BUILD
+int test_command_crash(int argc, const char **argv)
+{
+	return command_crash(argc, argv);
+}
+#endif /* TEST_BUILD*/
+#endif /* CONFIG_CMD_CRASH */
 
-static int command_panicinfo(int argc, char **argv)
+static int command_panicinfo(int argc, const char **argv)
 {
-	struct panic_data * const pdata_ptr = panic_get_data();
+	struct panic_data *const pdata_ptr = panic_get_data();
+
+	if (argc == 2) {
+		if (!strcasecmp(argv[1], "clear")) {
+			memset(get_panic_data_write(), 0,
+			       CONFIG_PANIC_DATA_SIZE);
+			ccprintf("Panic info cleared\n");
+			return EC_SUCCESS;
+		} else {
+			return EC_ERROR_PARAM1;
+		}
+	} else if (argc != 1)
+		return EC_ERROR_PARAM_COUNT;
 
 	if (pdata_ptr) {
-		ccprintf("Saved panic data:%s\n",
+		ccprintf("Saved panic data: 0x%02X %s\n", pdata_ptr->flags,
 			 (pdata_ptr->flags & PANIC_DATA_FLAG_OLD_CONSOLE ?
-			  "" : " (NEW)"));
+				  "" :
+				  "(NEW)"));
 
 		panic_data_print(pdata_ptr);
 
@@ -371,29 +447,36 @@ static int command_panicinfo(int argc, char **argv)
 		pdata_ptr->flags |= PANIC_DATA_FLAG_OLD_CONSOLE;
 	} else {
 		ccprintf("No saved panic data available "
-		    "or panic data can't be safely interpreted.\n");
+			 "or panic data can't be safely interpreted.\n");
 	}
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(panicinfo, command_panicinfo,
-			NULL,
+DECLARE_CONSOLE_COMMAND(panicinfo, command_panicinfo, "[clear]",
 			"Print info from a previous panic");
 
 /*****************************************************************************/
 /* Host commands */
 
-enum ec_status host_command_panic_info(struct host_cmd_handler_args *args)
+static enum ec_status
+host_command_panic_info(struct host_cmd_handler_args *args)
 {
 	uint32_t pdata_size = get_panic_data_size();
 	uintptr_t pdata_start = get_panic_data_start();
-	struct panic_data * pdata;
+	struct panic_data *pdata = panic_get_data();
 
 	if (pdata_start && pdata_size > 0) {
-		ASSERT(pdata_size <= args->response_max);
+		if (pdata_size > args->response_max) {
+			panic_printf("Panic data size %d is too "
+				     "large, truncating to %d\n",
+				     pdata_size, args->response_max);
+			pdata_size = args->response_max;
+			if (pdata) {
+				pdata->flags |= PANIC_DATA_FLAG_TRUNCATED;
+			}
+		}
 		memcpy(args->response, (void *)pdata_start, pdata_size);
 		args->response_size = pdata_size;
 
-		pdata = panic_get_data();
 		if (pdata) {
 			/* Data has now been returned */
 			pdata->flags |= PANIC_DATA_FLAG_OLD_HOSTCMD;
@@ -402,6 +485,5 @@ enum ec_status host_command_panic_info(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_GET_PANIC_INFO,
-		     host_command_panic_info,
+DECLARE_HOST_COMMAND(EC_CMD_GET_PANIC_INFO, host_command_panic_info,
 		     EC_VER_MASK(0));
diff --git a/common/pd_log.c b/common/pd_log.c
index 3708aad72e..477f8327eb 100644
--- a/common/pd_log.c
+++ b/common/pd_log.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,8 +21,7 @@ BUILD_ASSERT(PD_LOG_SIZE_MASK == EVENT_LOG_SIZE_MASK);
 BUILD_ASSERT(PD_LOG_TIMESTAMP_SHIFT == EVENT_LOG_TIMESTAMP_SHIFT);
 BUILD_ASSERT(PD_EVENT_NO_ENTRY == EVENT_LOG_NO_ENTRY);
 
-void pd_log_event(uint8_t type, uint8_t size_port,
-		  uint16_t data, void *payload)
+void pd_log_event(uint8_t type, uint8_t size_port, uint16_t data, void *payload)
 {
 	uint32_t timestamp = get_time().val >> PD_LOG_TIMESTAMP_SHIFT;
 
@@ -48,8 +47,8 @@ void pd_log_recv_vdm(int port, int cnt, uint32_t *payload)
 		return;
 
 	if (r->type != PD_EVENT_NO_ENTRY) {
-		timestamp = (get_time().val >> PD_LOG_TIMESTAMP_SHIFT)
-			  - r->timestamp;
+		timestamp = (get_time().val >> PD_LOG_TIMESTAMP_SHIFT) -
+			    r->timestamp;
 		log_add_event(r->type, size_port, r->data, r->payload,
 			      timestamp);
 		/* record that we have enqueued new content */
@@ -84,8 +83,7 @@ static enum ec_status hc_pd_get_log_entry(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_PD_GET_LOG_ENTRY,
-		     hc_pd_get_log_entry,
+DECLARE_HOST_COMMAND(EC_CMD_PD_GET_LOG_ENTRY, hc_pd_get_log_entry,
 		     EC_VER_MASK(0));
 
 static enum ec_status hc_pd_write_log_entry(struct host_cmd_handler_args *args)
@@ -117,8 +115,7 @@ static enum ec_status hc_pd_write_log_entry(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_PD_WRITE_LOG_ENTRY,
-		     hc_pd_write_log_entry,
+DECLARE_HOST_COMMAND(EC_CMD_PD_WRITE_LOG_ENTRY, hc_pd_write_log_entry,
 		     EC_VER_MASK(0));
 #else /* !HAS_TASK_HOSTCMD */
 /* we are a PD accessory, send back the events as a VDM (VDO_CMD_GET_LOG) */
diff --git a/common/peci.c b/common/peci.c
index e0f03c95dd..b124d6b67b 100644
--- a/common/peci.c
+++ b/common/peci.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,12 +8,13 @@
 #include "chipset.h"
 #include "console.h"
 #include "peci.h"
+#include "printf.h"
 #include "util.h"
 
 static int peci_get_cpu_temp(int *cpu_temp)
 {
 	int rv;
-	uint8_t r_buf[PECI_GET_TEMP_READ_LENGTH] = {0};
+	uint8_t r_buf[PECI_GET_TEMP_READ_LENGTH] = { 0 };
 	struct peci_data peci = {
 		.cmd_code = PECI_CMD_GET_TEMP,
 		.addr = PECI_TARGET_ADDRESS,
@@ -72,10 +73,10 @@ int peci_temp_sensor_get_val(int idx, int *temp_ptr)
 /*****************************************************************************/
 /* Console commands */
 #ifdef CONFIG_CMD_PECI
-static int peci_cmd(int argc, char **argv)
+static int peci_cmd(int argc, const char **argv)
 {
-	uint8_t r_buf[PECI_READ_DATA_FIFO_SIZE] = {0};
-	uint8_t w_buf[PECI_WRITE_DATA_FIFO_SIZE] = {0};
+	uint8_t r_buf[PECI_READ_DATA_FIFO_SIZE] = { 0 };
+	uint8_t w_buf[PECI_WRITE_DATA_FIFO_SIZE] = { 0 };
 	struct peci_data peci = {
 		.w_buf = w_buf,
 		.r_buf = r_buf,
@@ -139,15 +140,20 @@ static int peci_cmd(int argc, char **argv)
 	if (peci_transaction(&peci)) {
 		ccprintf("PECI transaction error\n");
 		return EC_ERROR_UNKNOWN;
+	} else {
+		char str_buf[hex_str_buf_size(peci.r_len)];
+
+		snprintf_hex_buffer(str_buf, sizeof(str_buf),
+				    HEX_BUF(r_buf, sizeof(str_buf)));
+		ccprintf("PECI read data: %s\n", str_buf);
+
+		return EC_SUCCESS;
 	}
-	ccprintf("PECI read data: %ph\n", HEX_BUF(r_buf, peci.r_len));
-	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(peci, peci_cmd,
-			"addr wlen rlen cmd timeout(us)",
+DECLARE_CONSOLE_COMMAND(peci, peci_cmd, "addr wlen rlen cmd timeout(us)",
 			"PECI command");
 
-static int command_peci_temp(int argc, char **argv)
+static int command_peci_temp(int argc, const char **argv)
 {
 	int t;
 
@@ -159,7 +165,6 @@ static int command_peci_temp(int argc, char **argv)
 	ccprintf("CPU temp: %d K, %d C\n", t, K_TO_C(t));
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(pecitemp, command_peci_temp,
-			NULL,
+DECLARE_CONSOLE_COMMAND(pecitemp, command_peci_temp, NULL,
 			"Print CPU temperature");
 #endif /* CONFIG_CMD_PECI */
diff --git a/common/peripheral.c b/common/peripheral.c
index 79a80b0ef9..0d54bc9bee 100644
--- a/common/peripheral.c
+++ b/common/peripheral.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,7 +18,7 @@ static enum ec_status hc_locate_chip(struct host_cmd_handler_args *args)
 
 	switch (params->type) {
 	case EC_CHIP_TYPE_CBI_EEPROM:
-#ifdef CONFIG_CROS_BOARD_INFO
+#ifdef CONFIG_CBI_EEPROM
 		if (params->index >= 1)
 			return EC_RES_OVERFLOW;
 		resp->bus_type = EC_BUS_TYPE_I2C;
@@ -27,10 +27,11 @@ static enum ec_status hc_locate_chip(struct host_cmd_handler_args *args)
 #else
 		/* Lookup type is supported, but not present on system. */
 		return EC_RES_UNAVAILABLE;
-#endif /* CONFIG_CROS_BOARD_INFO */
+#endif /* CONFIG_CBI_EEPROM */
 		break;
 	case EC_CHIP_TYPE_TCPC:
-#if defined(CONFIG_USB_PD_PORT_MAX_COUNT) && !defined(CONFIG_USB_PD_TCPC)
+#if defined(CONFIG_USB_POWER_DELIVERY) && \
+	defined(CONFIG_USB_PD_PORT_MAX_COUNT) && !defined(CONFIG_USB_PD_TCPC)
 		if (params->index >= board_get_usb_pd_port_count())
 			return EC_RES_OVERFLOW;
 		resp->bus_type = tcpc_config[params->index].bus_type;
@@ -40,11 +41,9 @@ static enum ec_status hc_locate_chip(struct host_cmd_handler_args *args)
 			resp->i2c_info.addr_flags =
 				tcpc_config[params->index].i2c_info.addr_flags;
 		}
-#ifdef CONFIG_INTEL_VIRTUAL_MUX
-		resp->reserved = tcpc_config[params->index].usb23;
-#endif
 #else
-		return EC_RES_UNAVAILABLE;
+		/* Not reachable in new boards. */
+		return EC_RES_UNAVAILABLE; /* LCOV_EXCL_LINE */
 #endif /* CONFIG_USB_PD_PORT_MAX_COUNT */
 		break;
 	default:
diff --git a/common/peripheral_charger.c b/common/peripheral_charger.c
new file mode 100644
index 0000000000..d07ca042dd
--- /dev/null
+++ b/common/peripheral_charger.c
@@ -0,0 +1,1076 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "atomic.h"
+#include "chipset.h"
+#include "common.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "lid_switch.h"
+#include "mkbp_event.h"
+#include "peripheral_charger.h"
+#include "queue.h"
+#include "stdbool.h"
+#include "task.h"
+#include "timer.h"
+#include "util.h"
+
+/* Peripheral Charge Manager */
+
+#define CPRINTS(fmt, args...) cprints(CC_PCHG, "PCHG: " fmt, ##args)
+
+/* Host event queue. Shared by all ports. */
+static struct queue const host_events =
+	QUEUE_NULL(PCHG_EVENT_QUEUE_SIZE, uint32_t);
+struct mutex host_event_mtx;
+
+static int pchg_count;
+
+/*
+ * Events and errors to be reported to the host in each chipset state.
+ *
+ * Off:     None
+ * Suspend: Device attach or detach (for wake-up)
+ * On:      SoC change and all other events and new errors except FW update.
+ *          FW update events are separately reported.
+ *
+ * TODO:Allow the host to update the masks.
+ */
+struct pchg_policy_t pchg_policy_on = {
+	.evt_mask =
+		BIT(PCHG_EVENT_IRQ) | BIT(PCHG_EVENT_RESET) |
+		BIT(PCHG_EVENT_INITIALIZED) | BIT(PCHG_EVENT_ENABLED) |
+		BIT(PCHG_EVENT_DISABLED) | BIT(PCHG_EVENT_DEVICE_DETECTED) |
+		BIT(PCHG_EVENT_DEVICE_CONNECTED) | BIT(PCHG_EVENT_DEVICE_LOST) |
+		BIT(PCHG_EVENT_CHARGE_STARTED) | BIT(PCHG_EVENT_CHARGE_UPDATE) |
+		BIT(PCHG_EVENT_CHARGE_ENDED) | BIT(PCHG_EVENT_CHARGE_STOPPED) |
+		BIT(PCHG_EVENT_ERROR) | BIT(PCHG_EVENT_IN_NORMAL) |
+		BIT(PCHG_EVENT_ENABLE) | BIT(PCHG_EVENT_DISABLE),
+	.err_mask = GENMASK(0, PCHG_ERROR_COUNT - 1),
+};
+
+struct pchg_policy_t pchg_policy_suspend = {
+	.evt_mask = BIT(PCHG_EVENT_DEVICE_DETECTED) |
+		    BIT(PCHG_EVENT_DEVICE_LOST),
+	.err_mask = 0,
+};
+
+static const char *_text_mode(enum pchg_mode mode)
+{
+	static const char *const mode_names[] = {
+		[PCHG_MODE_NORMAL] = "NORMAL",
+		[PCHG_MODE_DOWNLOAD] = "DOWNLOAD",
+		[PCHG_MODE_PASSTHRU] = "PASSTHRU",
+		[PCHG_MODE_BIST] = "BIST",
+	};
+	BUILD_ASSERT(ARRAY_SIZE(mode_names) == PCHG_MODE_COUNT);
+
+	if (mode < 0 || mode >= PCHG_MODE_COUNT)
+		return "UNDEF";
+
+	return mode_names[mode];
+}
+
+static const char *_text_event(enum pchg_event event)
+{
+	/* TODO: Use "S%d" for normal build. */
+	static const char *const event_names[] = {
+		[PCHG_EVENT_NONE] = "NONE",
+		[PCHG_EVENT_IRQ] = "IRQ",
+		[PCHG_EVENT_RESET] = "RESET",
+		[PCHG_EVENT_INITIALIZED] = "INITIALIZED",
+		[PCHG_EVENT_ENABLED] = "ENABLED",
+		[PCHG_EVENT_DISABLED] = "DISABLED",
+		[PCHG_EVENT_DEVICE_DETECTED] = "DEVICE_DETECTED",
+		[PCHG_EVENT_DEVICE_CONNECTED] = "DEVICE_CONNECTED",
+		[PCHG_EVENT_DEVICE_LOST] = "DEVICE_LOST",
+		[PCHG_EVENT_CHARGE_STARTED] = "CHARGE_STARTED",
+		[PCHG_EVENT_CHARGE_UPDATE] = "CHARGE_UPDATE",
+		[PCHG_EVENT_CHARGE_ENDED] = "CHARGE_ENDED",
+		[PCHG_EVENT_CHARGE_STOPPED] = "CHARGE_STOPPED",
+		[PCHG_EVENT_UPDATE_OPENED] = "UPDATE_OPENED",
+		[PCHG_EVENT_UPDATE_CLOSED] = "UPDATE_CLOSED",
+		[PCHG_EVENT_UPDATE_WRITTEN] = "UPDATE_WRITTEN",
+		[PCHG_EVENT_IN_NORMAL] = "IN_NORMAL",
+		[PCHG_EVENT_ERROR] = "ERROR",
+		[PCHG_EVENT_ENABLE] = "ENABLE",
+		[PCHG_EVENT_DISABLE] = "DISABLE",
+		[PCHG_EVENT_BIST_RUN] = "BIST_RUN",
+		[PCHG_EVENT_BIST_DONE] = "BIST_DONE",
+		[PCHG_EVENT_UPDATE_OPEN] = "UPDATE_OPEN",
+		[PCHG_EVENT_UPDATE_WRITE] = "UPDATE_WRITE",
+		[PCHG_EVENT_UPDATE_CLOSE] = "UPDATE_CLOSE",
+		[PCHG_EVENT_UPDATE_ERROR] = "UPDATE_ERROR",
+	};
+	BUILD_ASSERT(ARRAY_SIZE(event_names) == PCHG_EVENT_COUNT);
+
+	if (event >= sizeof(event_names))
+		return "UNDEF";
+
+	return event_names[event];
+}
+
+static const char *_text_error(uint32_t error)
+{
+	static const char *const error_names[] = {
+		[PCHG_ERROR_COMMUNICATION] = "COMMUNICATION",
+		[PCHG_ERROR_OVER_TEMPERATURE] = "OVER_TEMPERATURE",
+		[PCHG_ERROR_OVER_CURRENT] = "OVER_CURRENT",
+		[PCHG_ERROR_FOREIGN_OBJECT] = "FOREIGN_OBJECT",
+		[PCHG_ERROR_RESPONSE] = "RESPONSE",
+		[PCHG_ERROR_FW_VERSION] = "FW_VERSION",
+		[PCHG_ERROR_INVALID_FW] = "INVALID_FW",
+		[PCHG_ERROR_WRITE_FLASH] = "WRITE_FLASH",
+		[PCHG_ERROR_OTHER] = "OTHER",
+	};
+	BUILD_ASSERT(ARRAY_SIZE(error_names) == PCHG_ERROR_COUNT);
+	int ffs = __builtin_ffs(error) - 1;
+
+	if (0 <= ffs && ffs < PCHG_ERROR_COUNT)
+		return error_names[ffs];
+
+	return "UNDEF";
+}
+
+static void pchg_queue_event(struct pchg *ctx, enum pchg_event event)
+{
+	mutex_lock(&ctx->mtx);
+	if (queue_add_unit(&ctx->events, &event) == 0) {
+		ctx->dropped_event_count++;
+		CPRINTS("WARN: Queue is full.");
+	}
+	mutex_unlock(&ctx->mtx);
+}
+
+static void pchg_queue_host_event(struct pchg *ctx, uint32_t event)
+{
+	int len;
+	size_t i;
+	uint32_t last_event;
+
+	event |= EC_MKBP_PCHG_PORT_TO_EVENT(PCHG_CTX_TO_PORT(ctx));
+
+	mutex_lock(&host_event_mtx);
+	i = queue_count(&host_events);
+	if (i > 0) {
+		queue_peek_units(&host_events, &last_event, i - 1, 1);
+		if (last_event != event)
+			/* New event */
+			len = queue_add_unit(&host_events, &event);
+		else
+			/* Same event already in a queue. */
+			len = -1;
+	} else {
+		len = queue_add_unit(&host_events, &event);
+	}
+	mutex_unlock(&host_event_mtx);
+
+	if (len < 0) {
+		CPRINTS("INFO: Skipped back-to-back host event");
+	} else if (len == 0) {
+		ctx->dropped_host_event_count++;
+		CPRINTS("WARN: Host event queue is full");
+	}
+
+	mkbp_send_event(EC_MKBP_EVENT_PCHG);
+}
+
+static const char *_text_state(enum pchg_state state)
+{
+	/* TODO: Use "S%d" for normal build. */
+	static const char *const state_names[] = EC_PCHG_STATE_TEXT;
+
+	BUILD_ASSERT(ARRAY_SIZE(state_names) == PCHG_STATE_COUNT);
+
+	if (state >= sizeof(state_names))
+		return "UNDEF";
+
+	return state_names[state];
+}
+
+static void pchg_print_status(const struct pchg *ctx)
+{
+	int port = PCHG_CTX_TO_PORT(ctx);
+	enum pchg_event event = PCHG_EVENT_NONE;
+
+	queue_peek_units(&ctx->events, &event, 0, 1);
+	ccprintf("P%d STATE_%s EVENT_%s SOC=%d%%\n", port,
+		 _text_state(ctx->state), _text_event(ctx->event),
+		 ctx->battery_percent);
+	ccprintf("mode=%s\n", _text_mode(ctx->mode));
+	ccprintf("error=0x%x dropped=%u fw_version=0x%x\n", ctx->error,
+		 ctx->dropped_event_count, ctx->fw_version);
+	ccprintf("bist_cmd=0x%02x next_event=%s\n", ctx->bist_cmd,
+		 _text_event(event));
+}
+
+static void _clear_port(struct pchg *ctx)
+{
+	mutex_lock(&ctx->mtx);
+	queue_init(&ctx->events);
+	mutex_unlock(&ctx->mtx);
+	atomic_clear(&ctx->irq);
+	ctx->battery_percent = 0;
+	ctx->error = 0;
+	ctx->update.data_ready = 0;
+}
+
+static void reset_bist_cmd(struct pchg *ctx)
+{
+	ctx->bist_cmd = (ctx->cfg->rf_charge_msec) ?
+				PCHG_BIST_CMD_RF_CHARGE_ON :
+				PCHG_BIST_CMD_NONE;
+}
+
+__overridable void board_pchg_power_on(int port, bool on)
+{
+}
+
+/*
+ * This handles two cases: asynchronous reset and synchronous reset.
+ *
+ * Asynchronous resets are those triggered by charger chips. When a charger chip
+ * resets for some reason (e.g. WDT), it's expected to send PCHG_EVENT_RESET.
+ * This hook allows PCHG to reset its internal states (i.e. pchgs[port]). A
+ * reset here (by init) could be redundant for an asynchronous reset but it adds
+ * robustness.
+ *
+ * Synchronous resets are those triggered by the AP or PCHG itself.
+ */
+static enum pchg_state pchg_reset(struct pchg *ctx)
+{
+	enum pchg_state state = PCHG_STATE_RESET;
+	int rv;
+
+	_clear_port(ctx);
+
+	if (ctx->mode == PCHG_MODE_NORMAL || ctx->mode == PCHG_MODE_BIST) {
+		rv = ctx->cfg->drv->init(ctx);
+		if (rv == EC_SUCCESS) {
+			state = PCHG_STATE_INITIALIZED;
+			pchg_queue_event(ctx, PCHG_EVENT_ENABLE);
+		} else if (rv != EC_SUCCESS_IN_PROGRESS) {
+			ctx->event = PCHG_EVENT_ERROR;
+			ctx->error |= PCHG_ERROR_MASK(PCHG_ERROR_COMMUNICATION);
+			CPRINTS("ERR: Failed to reset to normal mode");
+		}
+	} else if (ctx->mode == PCHG_MODE_DOWNLOAD) {
+		state = PCHG_STATE_DOWNLOAD;
+		pchg_queue_event(ctx, PCHG_EVENT_UPDATE_OPEN);
+	} /* No-op for passthru mode */
+
+	return state;
+}
+
+static enum pchg_state reset_to_normal(struct pchg *ctx)
+{
+	ctx->mode = PCHG_MODE_NORMAL;
+	reset_bist_cmd(ctx);
+	return pchg_reset(ctx);
+}
+
+static void bist_timer_completion(void)
+{
+	/* Initializing ctx isn't needed if compiler is smart enough. */
+	struct pchg *ctx = &pchgs[0];
+	int i;
+
+	for (i = 0; i < pchg_count; i++) {
+		ctx = &pchgs[i];
+		if (ctx->state == PCHG_STATE_BIST)
+			break;
+	}
+	if (i == pchg_count)
+		return;
+
+	pchg_queue_event(ctx, PCHG_EVENT_BIST_DONE);
+	task_wake(TASK_ID_PCHG);
+}
+DECLARE_DEFERRED(bist_timer_completion);
+
+static void pchg_state_reset(struct pchg *ctx)
+{
+	switch (ctx->event) {
+	case PCHG_EVENT_RESET:
+		ctx->state = pchg_reset(ctx);
+		break;
+	case PCHG_EVENT_IN_NORMAL:
+		ctx->state = PCHG_STATE_INITIALIZED;
+		pchg_queue_event(ctx, PCHG_EVENT_ENABLE);
+		break;
+	default:
+		break;
+	}
+}
+
+static void pchg_state_initialized(struct pchg *ctx)
+{
+	int rv;
+
+	switch (ctx->event) {
+	case PCHG_EVENT_RESET:
+		ctx->state = pchg_reset(ctx);
+		break;
+	case PCHG_EVENT_ENABLE:
+		if (ctx->mode == PCHG_MODE_BIST) {
+			ctx->state = PCHG_STATE_BIST;
+			pchg_queue_event(ctx, PCHG_EVENT_BIST_RUN);
+			break;
+		}
+
+		rv = ctx->cfg->drv->enable(ctx, true);
+		if (rv == EC_SUCCESS)
+			ctx->state = PCHG_STATE_ENABLED;
+		else if (rv != EC_SUCCESS_IN_PROGRESS) {
+			ctx->event = PCHG_EVENT_ERROR;
+			ctx->error |= PCHG_ERROR_MASK(PCHG_ERROR_COMMUNICATION);
+			CPRINTS("ERR: Failed to enable");
+		}
+		break;
+	case PCHG_EVENT_ENABLED:
+		ctx->state = PCHG_STATE_ENABLED;
+		break;
+	default:
+		break;
+	}
+}
+
+static void pchg_state_bist(struct pchg *ctx)
+{
+	int rv;
+
+	switch (ctx->event) {
+	case PCHG_EVENT_BIST_RUN:
+		if (!ctx->cfg->drv->bist) {
+			CPRINTS("WARN: BIST not implemented");
+			ctx->state = reset_to_normal(ctx);
+			break;
+		}
+		rv = ctx->cfg->drv->bist(ctx, ctx->bist_cmd);
+		if (rv != EC_SUCCESS && rv != EC_SUCCESS_IN_PROGRESS) {
+			CPRINTS("ERR: Failed to run BIST 0x%02x for %d",
+				ctx->bist_cmd, rv);
+			ctx->state = reset_to_normal(ctx);
+			break;
+		}
+		CPRINTS("INFO: BIST 0x%02x executed", ctx->bist_cmd);
+		if (ctx->bist_cmd == PCHG_BIST_CMD_RF_CHARGE_ON)
+			/* Schedule timer for turning off RF charge. */
+			hook_call_deferred(&bist_timer_completion_data,
+					   ctx->cfg->rf_charge_msec * MSEC);
+		break;
+	case PCHG_EVENT_BIST_DONE:
+		ctx->mode = PCHG_MODE_NORMAL;
+		ctx->bist_cmd = PCHG_BIST_CMD_NONE;
+		ctx->state = pchg_reset(ctx);
+		break;
+	case PCHG_EVENT_DEVICE_LOST:
+		/*
+		 * DEVICE_LOST isn't generated in STATE_BIST, which is basically
+		 * STATE_INITIALIZED. If a stylus is removed during RF_CHARGE,
+		 * BIST_DONE will still be fired on timer expiration. Then, PCHG
+		 * will be left in NORMAL bist_cmd= NONE. Thus, the next stylus
+		 * (possibly a different stylus) won't be RF-charged.
+		 *
+		 * To avoid this, BIST_DONE should check if the stylus is still
+		 * attached or not. If not, it should set bist_cmd=RF_CHARGE.
+		 */
+	case PCHG_EVENT_RESET:
+		ctx->state = reset_to_normal(ctx);
+		break;
+	default:
+		break;
+	}
+}
+
+static void pchg_state_enabled(struct pchg *ctx)
+{
+	int rv;
+
+	switch (ctx->event) {
+	case PCHG_EVENT_RESET:
+		ctx->state = pchg_reset(ctx);
+		break;
+	case PCHG_EVENT_DISABLE:
+		rv = ctx->cfg->drv->enable(ctx, false);
+		if (rv == EC_SUCCESS)
+			ctx->state = PCHG_STATE_INITIALIZED;
+		else if (rv != EC_SUCCESS_IN_PROGRESS) {
+			ctx->event = PCHG_EVENT_ERROR;
+			ctx->error |= PCHG_ERROR_MASK(PCHG_ERROR_COMMUNICATION);
+			CPRINTS("ERR: Failed to disable");
+		}
+		break;
+	case PCHG_EVENT_DISABLED:
+		ctx->state = PCHG_STATE_INITIALIZED;
+		break;
+	case PCHG_EVENT_DEVICE_DETECTED:
+		if (ctx->bist_cmd != PCHG_BIST_CMD_NONE) {
+			ctx->mode = PCHG_MODE_BIST;
+			ctx->state = pchg_reset(ctx);
+		} else {
+			ctx->state = PCHG_STATE_DETECTED;
+		}
+		break;
+	case PCHG_EVENT_DEVICE_CONNECTED:
+		/*
+		 * Proactively query SOC in case charging info won't be sent
+		 * because device is already charged.
+		 */
+		ctx->cfg->drv->get_soc(ctx);
+		ctx->state = PCHG_STATE_CONNECTED;
+		break;
+	case PCHG_EVENT_ERROR:
+		if (ctx->error & PCHG_ERROR_MASK(PCHG_ERROR_FOREIGN_OBJECT)) {
+			if (ctx->bist_cmd != PCHG_BIST_CMD_NONE) {
+				ctx->mode = PCHG_MODE_BIST;
+				pchg_queue_event(ctx, PCHG_EVENT_RESET);
+			}
+		}
+		break;
+	default:
+		break;
+	}
+}
+
+static void pchg_state_detected(struct pchg *ctx)
+{
+	int rv;
+
+	switch (ctx->event) {
+	case PCHG_EVENT_RESET:
+		ctx->state = pchg_reset(ctx);
+		break;
+	case PCHG_EVENT_DISABLE:
+		rv = ctx->cfg->drv->enable(ctx, false);
+		if (rv == EC_SUCCESS)
+			ctx->state = PCHG_STATE_INITIALIZED;
+		else if (rv != EC_SUCCESS_IN_PROGRESS) {
+			ctx->event = PCHG_EVENT_ERROR;
+			ctx->error |= PCHG_ERROR_MASK(PCHG_ERROR_COMMUNICATION);
+			CPRINTS("ERR: Failed to disable");
+		}
+		break;
+	case PCHG_EVENT_DISABLED:
+		ctx->state = PCHG_STATE_INITIALIZED;
+		break;
+	case PCHG_EVENT_DEVICE_CONNECTED:
+		/*
+		 * Proactively query SOC in case charging info won't be sent
+		 * because device is already charged.
+		 */
+		ctx->cfg->drv->get_soc(ctx);
+		ctx->state = PCHG_STATE_CONNECTED;
+		break;
+	case PCHG_EVENT_DEVICE_LOST:
+		ctx->battery_percent = 0;
+		ctx->state = PCHG_STATE_ENABLED;
+		reset_bist_cmd(ctx);
+		break;
+	default:
+		break;
+	}
+}
+
+static void pchg_state_connected(struct pchg *ctx)
+{
+	int rv;
+
+	switch (ctx->event) {
+	case PCHG_EVENT_RESET:
+		ctx->state = pchg_reset(ctx);
+		break;
+	case PCHG_EVENT_DISABLE:
+		rv = ctx->cfg->drv->enable(ctx, false);
+		if (rv == EC_SUCCESS)
+			ctx->state = PCHG_STATE_INITIALIZED;
+		else if (rv != EC_SUCCESS_IN_PROGRESS) {
+			ctx->event = PCHG_EVENT_ERROR;
+			ctx->error |= PCHG_ERROR_MASK(PCHG_ERROR_COMMUNICATION);
+			CPRINTS("ERR: Failed to disable");
+		}
+		break;
+	case PCHG_EVENT_DISABLED:
+		ctx->state = PCHG_STATE_INITIALIZED;
+		break;
+	case PCHG_EVENT_CHARGE_STARTED:
+		ctx->state = PCHG_STATE_CHARGING;
+		break;
+	case PCHG_EVENT_DEVICE_LOST:
+		ctx->battery_percent = 0;
+		ctx->state = PCHG_STATE_ENABLED;
+		reset_bist_cmd(ctx);
+		break;
+	default:
+		break;
+	}
+}
+
+static void pchg_state_charging(struct pchg *ctx)
+{
+	int rv;
+
+	switch (ctx->event) {
+	case PCHG_EVENT_RESET:
+		ctx->state = pchg_reset(ctx);
+		break;
+	case PCHG_EVENT_DISABLE:
+		rv = ctx->cfg->drv->enable(ctx, false);
+		if (rv == EC_SUCCESS)
+			ctx->state = PCHG_STATE_INITIALIZED;
+		else if (rv != EC_SUCCESS_IN_PROGRESS) {
+			ctx->event = PCHG_EVENT_ERROR;
+			ctx->error |= PCHG_ERROR_MASK(PCHG_ERROR_COMMUNICATION);
+			CPRINTS("ERR: Failed to disable");
+		}
+		break;
+	case PCHG_EVENT_DISABLED:
+		ctx->state = PCHG_STATE_INITIALIZED;
+		break;
+	case PCHG_EVENT_CHARGE_UPDATE:
+		break;
+	case PCHG_EVENT_DEVICE_LOST:
+		ctx->battery_percent = 0;
+		ctx->state = PCHG_STATE_ENABLED;
+		reset_bist_cmd(ctx);
+		break;
+	case PCHG_EVENT_CHARGE_ENDED:
+	case PCHG_EVENT_CHARGE_STOPPED:
+		ctx->state = PCHG_STATE_CONNECTED;
+		break;
+	default:
+		break;
+	}
+}
+
+static void pchg_state_download(struct pchg *ctx)
+{
+	int rv;
+
+	switch (ctx->event) {
+	case PCHG_EVENT_RESET:
+		ctx->state = pchg_reset(ctx);
+		break;
+	case PCHG_EVENT_UPDATE_OPEN:
+		rv = ctx->cfg->drv->update_open(ctx);
+		if (rv == EC_SUCCESS) {
+			pchg_queue_event(ctx, PCHG_EVENT_UPDATE_OPENED);
+		} else if (rv != EC_SUCCESS_IN_PROGRESS) {
+			pchg_queue_host_event(ctx, EC_MKBP_PCHG_UPDATE_ERROR);
+			CPRINTS("ERR: Failed to open");
+		}
+		break;
+	case PCHG_EVENT_UPDATE_OPENED:
+		ctx->state = PCHG_STATE_DOWNLOADING;
+		pchg_queue_host_event(ctx, EC_MKBP_PCHG_UPDATE_OPENED);
+		break;
+	case PCHG_EVENT_UPDATE_ERROR:
+		pchg_queue_host_event(ctx, EC_MKBP_PCHG_UPDATE_ERROR);
+		break;
+	default:
+		break;
+	}
+}
+
+static void pchg_state_downloading(struct pchg *ctx)
+{
+	int rv;
+
+	switch (ctx->event) {
+	case PCHG_EVENT_RESET:
+		ctx->state = pchg_reset(ctx);
+		break;
+	case PCHG_EVENT_UPDATE_WRITE:
+		if (ctx->update.data_ready == 0)
+			break;
+		rv = ctx->cfg->drv->update_write(ctx);
+		if (rv == EC_SUCCESS) {
+			pchg_queue_event(ctx, PCHG_EVENT_UPDATE_WRITTEN);
+		} else if (rv != EC_SUCCESS_IN_PROGRESS) {
+			pchg_queue_host_event(ctx, EC_MKBP_PCHG_UPDATE_ERROR);
+			CPRINTS("ERR: Failed to write");
+		}
+		break;
+	case PCHG_EVENT_UPDATE_WRITTEN:
+		ctx->update.data_ready = 0;
+		pchg_queue_host_event(ctx, EC_MKBP_PCHG_WRITE_COMPLETE);
+		break;
+	case PCHG_EVENT_UPDATE_CLOSE:
+		rv = ctx->cfg->drv->update_close(ctx);
+		if (rv == EC_SUCCESS) {
+			pchg_queue_event(ctx, PCHG_EVENT_UPDATE_CLOSED);
+		} else if (rv != EC_SUCCESS_IN_PROGRESS) {
+			pchg_queue_host_event(ctx, EC_MKBP_PCHG_UPDATE_ERROR);
+			CPRINTS("ERR: Failed to close");
+		}
+		break;
+	case PCHG_EVENT_UPDATE_CLOSED:
+		ctx->state = PCHG_STATE_DOWNLOAD;
+		if (ctx->cfg->flags & PCHG_CFG_FW_UPDATE_SYNC) {
+			gpio_enable_interrupt(ctx->cfg->irq_pin);
+			ctx->state = reset_to_normal(ctx);
+		}
+		pchg_queue_host_event(ctx, EC_MKBP_PCHG_UPDATE_CLOSED);
+		break;
+	case PCHG_EVENT_UPDATE_ERROR:
+		CPRINTS("ERR: Failed to update");
+		pchg_queue_host_event(ctx, EC_MKBP_PCHG_UPDATE_ERROR);
+		break;
+	default:
+		break;
+	}
+}
+
+static int pchg_should_notify(struct pchg *ctx, enum pchg_chipset_state state,
+			      uint32_t prev_error, uint8_t prev_battery)
+{
+	if (ctx->event == PCHG_EVENT_ERROR) {
+		uint32_t err = ctx->error & ctx->policy[state]->err_mask;
+		/* Report only 0->1. */
+		return ((err ^ prev_error) & err) ? 1 : 0;
+	}
+
+	if (BIT(ctx->event) & ctx->policy[state]->evt_mask) {
+		if (ctx->event == PCHG_EVENT_CHARGE_UPDATE)
+			/* Report only new SoC. */
+			return ctx->battery_percent != prev_battery;
+		return 1;
+	}
+
+	return 0;
+}
+
+/**
+ * Process an event.
+ *
+ * The handler of the current state processes one event. If the event is IRQ,
+ * the driver is called (get_event), which translates the event to an actual
+ * event. Note that state handlers themselves may enqueue a new event.
+ *
+ * It returns 1 if the processed event needs to be reported to the host. This is
+ * notified as EC_MKBP_PCHG_DEVICE_EVENT. The host will call EC_CMD_PCHG to get
+ * updated status including the SoC and errors.
+ *
+ * State handlers may send a host event separately. For example, FW update
+ * events are reported as EC_MKBP_PCHG_UPDATE_*.
+ *
+ * @param ctx
+ * @return 1: Notify host of EC_MKBP_PCHG_DEVICE_EVENT.
+ */
+static int pchg_run(struct pchg *ctx)
+{
+	enum pchg_state previous_state = ctx->state;
+	uint8_t previous_battery = ctx->battery_percent;
+	uint32_t previous_error = ctx->error;
+	int port = PCHG_CTX_TO_PORT(ctx);
+	int rv;
+
+	mutex_lock(&ctx->mtx);
+	if (!queue_remove_unit(&ctx->events, &ctx->event)) {
+		mutex_unlock(&ctx->mtx);
+		CPRINTS("P%d No event in queue", port);
+		return 0;
+	}
+	mutex_unlock(&ctx->mtx);
+
+	CPRINTS("P%d(MODE_%s) Run in STATE_%s for EVENT_%s", port,
+		_text_mode(ctx->mode), _text_state(ctx->state),
+		_text_event(ctx->event));
+
+	/*
+	 * IRQ event is further translated to an actual event unless we're
+	 * in passthru mode, where IRQ events will be passed to the host.
+	 */
+	if (ctx->event == PCHG_EVENT_IRQ) {
+		if (ctx->mode != PCHG_MODE_PASSTHRU) {
+			rv = ctx->cfg->drv->get_event(ctx);
+			if (rv) {
+				CPRINTS("ERR: Failed to get event (%d)", rv);
+				return 0;
+			}
+		}
+		CPRINTS("  EVENT_%s", _text_event(ctx->event));
+	}
+
+	if (ctx->event == PCHG_EVENT_NONE)
+		return 0;
+
+	switch (ctx->state) {
+	case PCHG_STATE_RESET:
+		pchg_state_reset(ctx);
+		break;
+	case PCHG_STATE_INITIALIZED:
+		pchg_state_initialized(ctx);
+		break;
+	case PCHG_STATE_BIST:
+		pchg_state_bist(ctx);
+		break;
+	case PCHG_STATE_ENABLED:
+		pchg_state_enabled(ctx);
+		break;
+	case PCHG_STATE_DETECTED:
+		pchg_state_detected(ctx);
+		break;
+	case PCHG_STATE_CONNECTED:
+		pchg_state_connected(ctx);
+		break;
+	case PCHG_STATE_CHARGING:
+		pchg_state_charging(ctx);
+		break;
+	case PCHG_STATE_DOWNLOAD:
+		pchg_state_download(ctx);
+		break;
+	case PCHG_STATE_DOWNLOADING:
+		pchg_state_downloading(ctx);
+		break;
+	default:
+		CPRINTS("ERR: Unknown state (%d)", ctx->state);
+		return 0;
+	}
+
+	if (previous_state != ctx->state)
+		CPRINTS("->STATE_%s", _text_state(ctx->state));
+
+	if (ctx->battery_percent != previous_battery)
+		CPRINTS("Battery %u%%", ctx->battery_percent);
+
+	if (ctx->event == PCHG_EVENT_ERROR) {
+		/* Print (only one) new error. */
+		uint32_t err = (ctx->error ^ previous_error) & ctx->error;
+
+		if (err)
+			CPRINTS("ERROR_%s", _text_error(err));
+	}
+
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		/* Chipset off */
+		return 0;
+	else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
+		/* Chipset in suspend */
+		if (IS_ENABLED(CONFIG_LID_SWITCH) && !lid_is_open())
+			/* Don't wake up if the lid is closed. */
+			return 0;
+		return pchg_should_notify(ctx, PCHG_CHIPSET_STATE_SUSPEND,
+					  previous_error, previous_battery);
+	} else {
+		/* Chipset on */
+		return pchg_should_notify(ctx, PCHG_CHIPSET_STATE_ON,
+					  previous_error, previous_battery);
+	}
+}
+
+void pchg_irq(enum gpio_signal signal)
+{
+	struct pchg *ctx;
+	int i;
+
+	for (i = 0; i < pchg_count; i++) {
+		ctx = &pchgs[i];
+		if (signal == ctx->cfg->irq_pin) {
+			ctx->irq = 1;
+			task_wake(TASK_ID_PCHG);
+			return;
+		}
+	}
+}
+
+static void pchg_startup(void)
+{
+	struct pchg *ctx;
+	int p;
+	int active_pchg_count = 0;
+	int rv;
+
+	CPRINTS("%s", __func__);
+	queue_init(&host_events);
+
+	pchg_count = board_get_pchg_count();
+
+	for (p = 0; p < pchg_count; p++) {
+		rv = EC_SUCCESS;
+		ctx = &pchgs[p];
+		_clear_port(ctx);
+		ctx->mode = PCHG_MODE_NORMAL;
+		reset_bist_cmd(ctx);
+		gpio_disable_interrupt(ctx->cfg->irq_pin);
+		board_pchg_power_on(p, 1);
+		ctx->cfg->drv->reset(ctx);
+		if (ctx->cfg->drv->get_chip_info)
+			rv = ctx->cfg->drv->get_chip_info(ctx);
+		if (rv == EC_SUCCESS) {
+			gpio_enable_interrupt(ctx->cfg->irq_pin);
+			active_pchg_count++;
+		} else {
+			CPRINTS("ERR: Failed to probe P%d", p);
+			board_pchg_power_on(p, 0);
+		}
+	}
+
+	if (active_pchg_count)
+		task_wake(TASK_ID_PCHG);
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, pchg_startup, HOOK_PRIO_DEFAULT);
+
+static void pchg_shutdown(void)
+{
+	struct pchg *ctx;
+	int p;
+
+	CPRINTS("%s", __func__);
+
+	for (p = 0; p < pchg_count; p++) {
+		ctx = &pchgs[0];
+		gpio_disable_interrupt(ctx->cfg->irq_pin);
+		board_pchg_power_on(p, 0);
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, pchg_shutdown, HOOK_PRIO_DEFAULT);
+
+void pchg_task(void *u)
+{
+	struct pchg *ctx;
+	int p;
+
+	if (chipset_in_state(CHIPSET_STATE_ON))
+		/* We are here after power-on (because of late sysjump). */
+		pchg_startup();
+
+	while (true) {
+		/* Process pending events for all ports. */
+		for (p = 0; p < pchg_count; p++) {
+			ctx = &pchgs[p];
+			do {
+				if (atomic_clear(&ctx->irq))
+					pchg_queue_event(ctx, PCHG_EVENT_IRQ);
+				if (pchg_run(ctx))
+					pchg_queue_host_event(
+						ctx, EC_MKBP_PCHG_DEVICE_EVENT);
+			} while (queue_count(&ctx->events));
+		}
+
+		task_wait_event(-1);
+	}
+}
+
+static enum ec_status hc_pchg_count(struct host_cmd_handler_args *args)
+{
+	struct ec_response_pchg_count *r = args->response;
+
+	r->port_count = pchg_count;
+	args->response_size = sizeof(*r);
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_PCHG_COUNT, hc_pchg_count, EC_VER_MASK(0));
+
+#define HCPRINTS(fmt, args...) cprints(CC_PCHG, "HC:PCHG: " fmt, ##args)
+
+static enum ec_status hc_pchg(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_pchg_v3 *p = args->params;
+	struct ec_response_pchg_v2 *r = args->response;
+	int port = p->port;
+	struct pchg *ctx;
+
+	/* Version 0 shouldn't exist. */
+	if (args->version == 0)
+		return EC_RES_INVALID_VERSION;
+
+	if (port >= pchg_count)
+		return EC_RES_INVALID_PARAM;
+
+	ctx = &pchgs[port];
+	mutex_lock(&ctx->mtx);
+
+	if (ctx->state == PCHG_STATE_CONNECTED &&
+	    ctx->battery_percent >= ctx->cfg->full_percent)
+		r->state = PCHG_STATE_FULL;
+	else
+		r->state = ctx->state;
+
+	r->battery_percentage = ctx->battery_percent;
+	r->error = ctx->error;
+	r->fw_version = ctx->fw_version;
+	r->dropped_event_count = ctx->dropped_event_count;
+	r->dropped_host_event_count = ctx->dropped_host_event_count;
+
+	/* Clear error flags acked by the host. */
+	if (args->version > 2)
+		ctx->error &= ~p->error;
+
+	/* v2 and v3 have the same response struct. */
+	args->response_size = args->version == 1 ?
+				      sizeof(struct ec_response_pchg) :
+				      sizeof(*r);
+
+	mutex_unlock(&ctx->mtx);
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_PCHG, hc_pchg,
+		     EC_VER_MASK(1) | EC_VER_MASK(2) | EC_VER_MASK(3));
+
+int pchg_get_next_event(uint8_t *out)
+{
+	uint32_t event;
+	size_t len;
+
+	mutex_lock(&host_event_mtx);
+	len = queue_remove_unit(&host_events, &event);
+	mutex_unlock(&host_event_mtx);
+	if (len == 0)
+		return 0;
+
+	memcpy(out, &event, sizeof(event));
+
+	/* Ping host again if there are more events to send. */
+	if (queue_count(&host_events))
+		mkbp_send_event(EC_MKBP_EVENT_PCHG);
+
+	return sizeof(event);
+}
+DECLARE_EVENT_SOURCE(EC_MKBP_EVENT_PCHG, pchg_get_next_event);
+
+static enum ec_status hc_pchg_update(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_pchg_update *p = args->params;
+	struct ec_response_pchg_update *r = args->response;
+	int port = p->port;
+	struct pchg *ctx;
+
+	if (port >= pchg_count)
+		return EC_RES_INVALID_PARAM;
+
+	ctx = &pchgs[port];
+
+	switch (p->cmd) {
+	case EC_PCHG_UPDATE_CMD_RESET_TO_NORMAL:
+		HCPRINTS("Resetting to normal mode");
+
+		gpio_disable_interrupt(ctx->cfg->irq_pin);
+		_clear_port(ctx);
+		ctx->mode = PCHG_MODE_NORMAL;
+		ctx->cfg->drv->reset(ctx);
+		gpio_enable_interrupt(ctx->cfg->irq_pin);
+		break;
+
+	case EC_PCHG_UPDATE_CMD_OPEN:
+		HCPRINTS("Resetting to download mode");
+
+		gpio_disable_interrupt(ctx->cfg->irq_pin);
+		_clear_port(ctx);
+		ctx->mode = PCHG_MODE_DOWNLOAD;
+		ctx->cfg->drv->reset(ctx);
+		if (ctx->cfg->flags & PCHG_CFG_FW_UPDATE_SYNC) {
+			pchg_queue_event(ctx, PCHG_EVENT_RESET);
+		} else {
+			gpio_enable_interrupt(ctx->cfg->irq_pin);
+		}
+		ctx->update.version = p->version;
+		r->block_size = ctx->cfg->block_size;
+		args->response_size = sizeof(*r);
+		break;
+
+	case EC_PCHG_UPDATE_CMD_WRITE:
+		if (ctx->state != PCHG_STATE_DOWNLOADING)
+			return EC_RES_ERROR;
+		if (p->size > sizeof(ctx->update.data))
+			return EC_RES_OVERFLOW;
+		if (ctx->update.data_ready)
+			return EC_RES_BUSY;
+
+		HCPRINTS("Writing %u bytes to 0x%x", p->size, p->addr);
+		ctx->update.addr = p->addr;
+		ctx->update.size = p->size;
+		memcpy(ctx->update.data, p->data, p->size);
+		pchg_queue_event(ctx, PCHG_EVENT_UPDATE_WRITE);
+		ctx->update.data_ready = 1;
+		break;
+
+	case EC_PCHG_UPDATE_CMD_CLOSE:
+		if (ctx->state != PCHG_STATE_DOWNLOADING)
+			return EC_RES_ERROR;
+		if (ctx->update.data_ready)
+			return EC_RES_BUSY;
+
+		HCPRINTS("Closing update session (crc=0x%x)", p->crc32);
+		ctx->update.crc32 = p->crc32;
+		pchg_queue_event(ctx, PCHG_EVENT_UPDATE_CLOSE);
+		break;
+
+	case EC_PCHG_UPDATE_CMD_RESET:
+		HCPRINTS("Resetting");
+
+		gpio_disable_interrupt(ctx->cfg->irq_pin);
+		_clear_port(ctx);
+		ctx->cfg->drv->reset(ctx);
+		gpio_enable_interrupt(ctx->cfg->irq_pin);
+		break;
+
+	case EC_PCHG_UPDATE_CMD_ENABLE_PASSTHRU:
+		HCPRINTS("Enabling passthru mode");
+		mutex_lock(&ctx->mtx);
+		ctx->mode = PCHG_MODE_PASSTHRU;
+		mutex_unlock(&ctx->mtx);
+		break;
+
+	default:
+		return EC_RES_INVALID_PARAM;
+	}
+
+	task_wake(TASK_ID_PCHG);
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_PCHG_UPDATE, hc_pchg_update, EC_VER_MASK(0));
+
+static int cc_pchg(int argc, const char **argv)
+{
+	int port;
+	char *end;
+	struct pchg *ctx;
+
+	if (argc < 2 || 4 < argc)
+		return EC_ERROR_PARAM_COUNT;
+
+	port = strtoi(argv[1], &end, 0);
+	if (*end || port < 0 || port >= pchg_count)
+		return EC_ERROR_PARAM1;
+	ctx = &pchgs[port];
+
+	if (argc == 2) {
+		pchg_print_status(ctx);
+		return EC_SUCCESS;
+	}
+
+	if (!strcasecmp(argv[2], "reset")) {
+		if (argc == 3)
+			ctx->mode = PCHG_MODE_NORMAL;
+		else if (!strcasecmp(argv[3], "download"))
+			ctx->mode = PCHG_MODE_DOWNLOAD;
+		else
+			return EC_ERROR_PARAM3;
+		gpio_disable_interrupt(ctx->cfg->irq_pin);
+		_clear_port(ctx);
+		ctx->cfg->drv->reset(ctx);
+		gpio_enable_interrupt(ctx->cfg->irq_pin);
+	} else if (!strcasecmp(argv[2], "enable")) {
+		pchg_queue_event(ctx, PCHG_EVENT_ENABLE);
+	} else if (!strcasecmp(argv[2], "disable")) {
+		pchg_queue_event(ctx, PCHG_EVENT_DISABLE);
+	} else {
+		return EC_ERROR_PARAM2;
+	}
+
+	task_wake(TASK_ID_PCHG);
+
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(pchg, cc_pchg,
+			"\n\t<port>"
+			"\n\t<port> reset [download]"
+			"\n\t<port> enable"
+			"\n\t<port> disable",
+			"Control peripheral chargers");
diff --git a/common/port80.c b/common/port80.c
index 52264cc446..715d748ee9 100644
--- a/common/port80.c
+++ b/common/port80.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,20 +7,27 @@
 
 #include "common.h"
 #include "console.h"
+#include "chipset.h"
 #include "display_7seg.h"
 #include "hooks.h"
 #include "host_command.h"
 #include "port80.h"
+#include "printf.h"
 #include "task.h"
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_PORT80, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_PORT80, format, ##args)
 
-static uint16_t __bss_slow history[CONFIG_PORT80_HISTORY_LEN];
-static int __bss_slow writes;    /* Number of port 80 writes so far */
-static int last_boot; /* Last code from previous boot */
-static int __bss_slow scroll;
+#ifdef CONFIG_PORT80_4_BYTE
+typedef uint32_t port80_code_t;
+#else
+typedef uint16_t port80_code_t;
+#endif
+static port80_code_t history[CONFIG_PORT80_HISTORY_LEN];
+static int writes; /* Number of port 80 writes so far */
+static uint16_t last_boot; /* Last code from previous boot */
+static int scroll;
 
 #ifdef CONFIG_BRINGUP
 #undef CONFIG_PORT80_PRINT_IN_INT
@@ -32,8 +39,37 @@ static int print_in_int = CONFIG_PORT80_PRINT_IN_INT;
 static void port80_dump_buffer(void);
 DECLARE_DEFERRED(port80_dump_buffer);
 
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+static int ddr_initialized_fail;
+static int has_port_80_data;
+
+int port_80_last(void)
+{
+	return (uint16_t)history[(writes-1) % ARRAY_SIZE(history)];
+}
+
+int amd_ddr_initialized_check(void)
+{
+	return ddr_initialized_fail;
+}
+
+void port_80_read_customized(int index);
+DECLARE_DEFERRED(port_80_read_customized);
+
+void port_80_read_customized(int index)
+{
+	if (has_port_80_data) {
+		CPRINTF("PORT80: %04X\n", (history[(writes-1) % ARRAY_SIZE(history)] & 0xFFFF));
+		has_port_80_data = 0;
+	}
+}
+#endif
+
 void port_80_write(int data)
 {
+#ifndef CONFIG_CUSTOMIZED_DESIGN
+	char ts_str[PRINTF_TIMESTAMP_BUF_SIZE];
+
 	/*
 	 * By default print_in_int is disabled if:
 	 * 1. CONFIG_BRINGUP is not defined
@@ -47,22 +83,36 @@ void port_80_write(int data)
 	 * schedule a deferred call 4 seconds after the last port80 write to
 	 * dump the current port80 buffer to EC console. This is to allow
 	 * developers to help debug BIOS progress by tracing port80 messages.
-	 *
-	 * P.S.: Deferred call is not scheduled for special event codes (data >=
-	 * 0x100). This is because only 8-bit port80 messages are assumed to be
-	 * coming from the host.
 	 */
-	if (print_in_int)
-		CPRINTF("%c[%pT Port 80: 0x%02x]",
-			scroll ? '\n' : '\r', PRINTF_TIMESTAMP_NOW, data);
-	else if (data < 0x100)
+
+	if (print_in_int) {
+		snprintf_timestamp_now(ts_str, sizeof(ts_str));
+		CPRINTF("%c[%s Port 80: 0x%02x]", scroll ? '\n' : '\r', ts_str,
+			data);
+	}
+
+	if (!IS_ENABLED(CONFIG_PORT80_QUIET)) {
 		hook_call_deferred(&port80_dump_buffer_data, 4 * SECOND);
+	}
+#else
+	if (!has_port_80_data) {
+		has_port_80_data = 1;
+		hook_call_deferred(&port_80_read_customized_data, 10 * MSEC);
+	}
+
+	if (data == 0x12344321)
+		ddr_initialized_fail = 1;
+#endif
 
 	/* Save current port80 code if system is resetting */
 	if (data == PORT_80_EVENT_RESET && writes) {
-		int prev = history[(writes-1) % ARRAY_SIZE(history)];
+		port80_code_t prev =
+			history[(writes - 1) % ARRAY_SIZE(history)];
 
-		/* Ignore special event codes */
+		/*
+		 * last_boot only reports 8-bit codes.
+		 * Ignore special event codes and 4-byte codes.
+		 */
 		if (prev < 0x100)
 			last_boot = prev;
 	}
@@ -123,7 +173,7 @@ static void port80_dump_buffer(void)
 /*****************************************************************************/
 /* Console commands */
 
-static int command_port80(int argc, char **argv)
+static int command_port80(int argc, const char **argv)
 {
 	/*
 	 * 'port80 scroll' toggles whether port 80 output begins with a newline
@@ -150,8 +200,7 @@ static int command_port80(int argc, char **argv)
 	port80_dump_buffer();
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(port80, command_port80,
-			"[scroll | intprint | flush]",
+DECLARE_CONSOLE_COMMAND(port80, command_port80, "[scroll | intprint | flush]",
 			"Print port80 writes or toggle port80 scrolling");
 
 enum ec_status port80_last_boot(struct host_cmd_handler_args *args)
@@ -164,7 +213,7 @@ enum ec_status port80_last_boot(struct host_cmd_handler_args *args)
 	return EC_RES_SUCCESS;
 }
 
-enum ec_status port80_command_read(struct host_cmd_handler_args *args)
+static enum ec_status port80_command_read(struct host_cmd_handler_args *args)
 {
 	const struct ec_params_port80_read *p = args->params;
 	uint32_t offset = p->read_buffer.offset;
@@ -183,24 +232,23 @@ enum ec_status port80_command_read(struct host_cmd_handler_args *args)
 	} else if (p->subcmd == EC_PORT80_READ_BUFFER) {
 		/* do not allow bad offset or size */
 		if (offset >= ARRAY_SIZE(history) || entries == 0 ||
-			entries > args->response_max)
+		    entries > args->response_max)
 			return EC_RES_INVALID_PARAM;
 
 		for (i = 0; i < entries; i++) {
-			uint16_t e = history[(i + offset) %
-				ARRAY_SIZE(history)];
+			uint16_t e =
+				history[(i + offset) % ARRAY_SIZE(history)];
 			rsp->data.codes[i] = e;
 		}
 
-		args->response_size = entries*sizeof(uint16_t);
+		args->response_size = entries * sizeof(uint16_t);
 		return EC_RES_SUCCESS;
 	}
 
 	return EC_RES_INVALID_PARAM;
 }
-DECLARE_HOST_COMMAND(EC_CMD_PORT80_READ,
-		port80_command_read,
-		EC_VER_MASK(0) | EC_VER_MASK(1));
+DECLARE_HOST_COMMAND(EC_CMD_PORT80_READ, port80_command_read,
+		     EC_VER_MASK(0) | EC_VER_MASK(1));
 
 static void port80_log_resume(void)
 {
diff --git a/common/power_button.c b/common/power_button.c
index 1ac3893492..484d25154a 100644
--- a/common/power_button.c
+++ b/common/power_button.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,6 +6,7 @@
 /* Power button module for Chrome EC */
 
 #include "button.h"
+#include "chipset.h"
 #include "common.h"
 #include "console.h"
 #include "gpio.h"
@@ -21,14 +22,14 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_SWITCH, outstr)
-#define CPRINTS(format, args...) cprints(CC_SWITCH, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SWITCH, format, ##args)
 
 /* By default the power button is active low */
 #ifndef CONFIG_POWER_BUTTON_FLAGS
 #define CONFIG_POWER_BUTTON_FLAGS 0
 #endif
 
-static int debounced_power_pressed;	/* Debounced power button state */
+static int debounced_power_pressed; /* Debounced power button state */
 static int simulate_power_pressed;
 static volatile int power_button_is_stable = 1;
 
@@ -41,8 +42,11 @@ static const struct button_config power_button = {
 
 int power_button_signal_asserted(void)
 {
-	return !!(gpio_get_level(power_button.gpio)
-		== (power_button.flags & BUTTON_FLAG_ACTIVE_HIGH) ? 1 : 0);
+	return !!(
+		gpio_get_level(power_button.gpio) ==
+				(power_button.flags & BUTTON_FLAG_ACTIVE_HIGH) ?
+			1 :
+			0);
 }
 
 /**
@@ -93,8 +97,8 @@ int power_button_wait_for_release(int timeout_us)
 		 * the power button is debounced but not changed, or the power
 		 * button has not been debounced.
 		 */
-		task_wait_event(MIN(power_button.debounce_us,
-				    deadline.val - now.val));
+		task_wait_event(
+			MIN(power_button.debounce_us, deadline.val - now.val));
 	}
 
 	CPRINTS("%s released in time", power_button.name);
@@ -132,6 +136,10 @@ DECLARE_HOOK(HOOK_CHIPSET_STARTUP, pb_chipset_startup, HOOK_PRIO_DEFAULT);
 
 static void pb_chipset_shutdown(void)
 {
+	/* Don't set AP_IDLE if shutting down due to power failure. */
+	if (chipset_get_shutdown_reason() == CHIPSET_SHUTDOWN_POWERFAIL)
+		return;
+
 	chip_save_reset_flags(chip_read_reset_flags() | EC_RESET_FLAG_AP_IDLE);
 	system_set_reset_flags(EC_RESET_FLAG_AP_IDLE);
 	CPRINTS("Saved AP_IDLE flag");
@@ -141,7 +149,7 @@ DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, pb_chipset_shutdown,
 	      * Slightly higher than handle_pending_reboot because
 	      * it may clear AP_IDLE flag.
 	      */
-	     HOOK_PRIO_DEFAULT - 1);
+	     HOOK_PRIO_PRE_DEFAULT);
 #endif
 
 /**
@@ -164,8 +172,8 @@ static void power_button_change_deferred(void)
 	debounced_power_pressed = new_pressed;
 	power_button_is_stable = 1;
 
-	CPRINTS("%s %s",
-		power_button.name, new_pressed ? "pressed" : "released");
+	CPRINTS("%s %s", power_button.name,
+		new_pressed ? "pressed" : "released");
 
 	/* Call hooks */
 	hook_notify(HOOK_POWER_BUTTON_CHANGE);
@@ -176,6 +184,15 @@ static void power_button_change_deferred(void)
 }
 DECLARE_DEFERRED(power_button_change_deferred);
 
+static void power_button_simulate_deferred(void)
+{
+	ccprintf("Simulating %s release.\n", power_button.name);
+	simulate_power_pressed = 0;
+	power_button_is_stable = 0;
+	power_button_change_deferred();
+}
+DECLARE_DEFERRED(power_button_simulate_deferred);
+
 void power_button_interrupt(enum gpio_signal signal)
 {
 	/*
@@ -192,36 +209,32 @@ void power_button_interrupt(enum gpio_signal signal)
 			   power_button.debounce_us);
 }
 
+void power_button_simulate_press(unsigned int duration)
+{
+	ccprintf("Simulating %d ms %s press.\n", duration, power_button.name);
+	simulate_power_pressed = 1;
+	power_button_is_stable = 0;
+	power_button_change_deferred();
+	hook_call_deferred(&power_button_simulate_deferred_data,
+			   duration * MSEC);
+}
+
 /*****************************************************************************/
 /* Console commands */
 
-static int command_powerbtn(int argc, char **argv)
+static int command_powerbtn(int argc, const char **argv)
 {
-	int ms = 200;  /* Press duration in ms */
+	int ms = 200; /* Press duration in ms */
 	char *e;
 
 	if (argc > 1) {
 		ms = strtoi(argv[1], &e, 0);
-		if (*e)
+		if (*e || ms < 0)
 			return EC_ERROR_PARAM1;
 	}
 
-	ccprintf("Simulating %d ms %s press.\n", ms, power_button.name);
-	simulate_power_pressed = 1;
-	power_button_is_stable = 0;
-	hook_call_deferred(&power_button_change_deferred_data, 0);
-
-	if (ms > 0)
-		msleep(ms);
-
-	ccprintf("Simulating %s release.\n", power_button.name);
-	simulate_power_pressed = 0;
-	power_button_is_stable = 0;
-	hook_call_deferred(&power_button_change_deferred_data, 0);
-
+	power_button_simulate_press(ms);
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(powerbtn, command_powerbtn,
-			"[msec]",
+DECLARE_CONSOLE_COMMAND(powerbtn, command_powerbtn, "[msec]",
 			"Simulate power button press");
-
diff --git a/common/power_button_x86.c b/common/power_button_x86.c
index 661f9b2a3d..f0e43a80c3 100644
--- a/common/power_button_x86.c
+++ b/common/power_button_x86.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,7 +23,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_SWITCH, outstr)
-#define CPRINTS(format, args...) cprints(CC_SWITCH, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SWITCH, format, ##args)
 
 /*
  * x86 chipsets have a hardware timer on the power button input which causes
@@ -54,14 +54,14 @@
  *    to host    v                      v
  *     @S0   make code             break code
  */
-#define PWRBTN_DELAY_T0    (32 * MSEC)  /* 32ms (PCH requires >16ms) */
-#define PWRBTN_DELAY_T1    (4 * SECOND - PWRBTN_DELAY_T0)  /* 4 secs - t0 */
+#define PWRBTN_DELAY_T0 (32 * MSEC) /* 32ms (PCH requires >16ms) */
+#define PWRBTN_DELAY_T1 (4 * SECOND - PWRBTN_DELAY_T0) /* 4 secs - t0 */
 /*
  * Length of time to stretch initial power button press to give chipset a
  * chance to wake up (~100ms) and react to the press (~16ms).  Also used as
  * pulse length for simulated power button presses when the system is off.
  */
-#define PWRBTN_INITIAL_US  (200 * MSEC)
+#define PWRBTN_INITIAL_US (200 * MSEC)
 
 enum power_button_state {
 	/* Button up; state machine idle */
@@ -92,18 +92,9 @@ enum power_button_state {
 };
 static enum power_button_state pwrbtn_state = PWRBTN_STATE_IDLE;
 
-static const char * const state_names[] = {
-	"idle",
-	"pressed",
-	"t0",
-	"t1",
-	"held",
-	"lid-open",
-	"released",
-	"eat-release",
-	"init-on",
-	"recovery",
-	"was-off",
+static const char *const state_names[] = {
+	"idle",	    "pressed",	   "t0",      "t1",	  "held",    "lid-open",
+	"released", "eat-release", "init-on", "recovery", "was-off",
 };
 
 /*
@@ -139,7 +130,7 @@ static void set_pwrbtn_to_pch(int high, int init)
 	 */
 #ifdef CONFIG_CHARGER
 	if (chipset_in_state(CHIPSET_STATE_ANY_OFF) && !high &&
-	   (charge_want_shutdown() || charge_prevent_power_on(!init))) {
+	    (charge_want_shutdown() || charge_prevent_power_on(!init))) {
 		CPRINTS("PB PCH pwrbtn ignored due to battery level");
 		high = 1;
 	}
@@ -211,7 +202,7 @@ static void power_button_released(uint64_t tnow)
 /**
  * Set initial power button state.
  */
-static void set_initial_pwrbtn_state(void)
+test_export_static void set_initial_pwrbtn_state(void)
 {
 	uint32_t reset_flags = system_get_reset_flags();
 
@@ -346,8 +337,8 @@ static void state_machine(uint64_t tnow)
 
 		if (!IS_ENABLED(CONFIG_CHARGER) || charge_prevent_power_on(0)) {
 			if (tnow >
-				(tpb_task_start +
-				 CONFIG_POWER_BUTTON_INIT_TIMEOUT * SECOND)) {
+			    (tpb_task_start +
+			     CONFIG_POWER_BUTTON_INIT_TIMEOUT * SECOND)) {
 				pwrbtn_state = PWRBTN_STATE_IDLE;
 				break;
 			}
@@ -366,9 +357,9 @@ static void state_machine(uint64_t tnow)
 #ifdef CONFIG_DELAY_DSW_PWROK_TO_PWRBTN
 		/* Check if power button is ready. If not, we'll come back. */
 		if (get_time().val - get_time_dsw_pwrok() <
-				CONFIG_DSW_PWROK_TO_PWRBTN_US) {
+		    CONFIG_DSW_PWROK_TO_PWRBTN_US) {
 			tnext_state = get_time_dsw_pwrok() +
-					CONFIG_DSW_PWROK_TO_PWRBTN_US;
+				      CONFIG_DSW_PWROK_TO_PWRBTN_US;
 			break;
 		}
 #endif
@@ -434,17 +425,18 @@ void power_button_task(void *u)
 			tsleep = tnext_state;
 		t = get_time().val;
 		if (tsleep > t) {
-			unsigned d = tsleep == -1 ? -1 : (unsigned)(tsleep - t);
+			unsigned int d =
+				tsleep == -1 ? -1 : (unsigned int)(tsleep - t);
 			/*
-			 * (Yes, the conversion from uint64_t to unsigned could
-			 * theoretically overflow if we wanted to sleep for
-			 * more than 2^32 us, but our timeouts are small enough
-			 * that can't happen - and even if it did, we'd just go
-			 * back to sleep after deciding that we woke up too
-			 * early.)
+			 * (Yes, the conversion from uint64_t to unsigned int
+			 * could theoretically overflow if we wanted to sleep
+			 * for more than 2^32 us, but our timeouts are small
+			 * enough that can't happen - and even if it did, we'd
+			 * just go back to sleep after deciding that we woke up
+			 * too early.)
 			 */
 			CPRINTS("PB task %d = %s, wait %d", pwrbtn_state,
-			state_names[pwrbtn_state], d);
+				state_names[pwrbtn_state], d);
 			task_wait_event(d);
 		}
 	}
@@ -459,6 +451,14 @@ static void powerbtn_x86_init(void)
 }
 DECLARE_HOOK(HOOK_INIT, powerbtn_x86_init, HOOK_PRIO_DEFAULT);
 
+void chipset_power_on(void)
+{
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
+	    pwrbtn_state != PWRBTN_STATE_INIT_ON) {
+		power_button_pch_pulse();
+	}
+}
+
 #ifdef CONFIG_LID_SWITCH
 /**
  * Handle switch changes based on lid event.
@@ -466,9 +466,9 @@ DECLARE_HOOK(HOOK_INIT, powerbtn_x86_init, HOOK_PRIO_DEFAULT);
 static void powerbtn_x86_lid_change(void)
 {
 	/* If chipset is off, pulse the power button on lid open to wake it. */
-	if (lid_is_open() && chipset_in_state(CHIPSET_STATE_ANY_OFF)
-	    && pwrbtn_state != PWRBTN_STATE_INIT_ON)
-		power_button_pch_pulse();
+	if (lid_is_open()) {
+		chipset_power_on();
+	}
 }
 DECLARE_HOOK(HOOK_LID_CHANGE, powerbtn_x86_lid_change, HOOK_PRIO_DEFAULT);
 #endif
@@ -520,12 +520,11 @@ static enum ec_status hc_config_powerbtn_x86(struct host_cmd_handler_args *args)
 	power_button_pulse_enabled =
 		!!(p->flags & EC_POWER_BUTTON_ENABLE_PULSE);
 
-	return EC_SUCCESS;
+	return EC_RES_SUCCESS;
 }
 DECLARE_HOST_COMMAND(EC_CMD_CONFIG_POWER_BUTTON, hc_config_powerbtn_x86,
 		     EC_VER_MASK(0));
 
-
 /*
  * Currently, the only reason why we disable power button pulse is to allow
  * detachable menu on AP to use power button for selection purpose without
@@ -546,8 +545,8 @@ DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, power_button_pulse_setting_reset,
 DECLARE_HOOK(HOOK_CHIPSET_RESUME, power_button_pulse_setting_reset,
 	     HOOK_PRIO_DEFAULT);
 
-#define POWER_BUTTON_SYSJUMP_TAG		0x5042 /* PB */
-#define POWER_BUTTON_HOOK_VERSION		1
+#define POWER_BUTTON_SYSJUMP_TAG 0x5042 /* PB */
+#define POWER_BUTTON_HOOK_VERSION 1
 
 static void power_button_pulse_setting_restore_state(void)
 {
@@ -562,12 +561,11 @@ static void power_button_pulse_setting_restore_state(void)
 		power_button_pulse_enabled = *state;
 }
 DECLARE_HOOK(HOOK_INIT, power_button_pulse_setting_restore_state,
-	     HOOK_PRIO_INIT_POWER_BUTTON + 1);
+	     HOOK_PRIO_POST_POWER_BUTTON);
 
 static void power_button_pulse_setting_preserve_state(void)
 {
-	system_add_jump_tag(POWER_BUTTON_SYSJUMP_TAG,
-			    POWER_BUTTON_HOOK_VERSION,
+	system_add_jump_tag(POWER_BUTTON_SYSJUMP_TAG, POWER_BUTTON_HOOK_VERSION,
 			    sizeof(power_button_pulse_enabled),
 			    &power_button_pulse_enabled);
 }
diff --git a/common/printf.c b/common/printf.c
index f876a1da19..d2cc78f5aa 100644
--- a/common/printf.c
+++ b/common/printf.c
@@ -1,10 +1,11 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Printf-like functionality for Chrome EC */
 
+#include "builtin/assert.h"
 #include "console.h"
 #include "printf.h"
 #include "timer.h"
@@ -12,24 +13,7 @@
 
 static const char error_str[] = "ERROR";
 
-#define MAX_FORMAT 1024  /* Maximum chars in a single format field */
-
-#ifndef CONFIG_DEBUG_PRINTF
-static inline int divmod(uint64_t *n, int d)
-{
-	return uint64divmod(n, d);
-}
-
-#else /* CONFIG_DEBUG_PRINTF */
-/* if we are optimizing for size, remove the 64-bit support */
-#define NO_UINT64_SUPPORT
-static inline int divmod(uint32_t *n, int d)
-{
-	int r = *n % d;
-	*n /= d;
-	return r;
-}
-#endif
+#define MAX_FORMAT 1024 /* Maximum chars in a single format field */
 
 /**
  * Convert the lowest nibble of a number to hex
@@ -47,27 +31,118 @@ static int hexdigit(int c)
 }
 
 /* Flags for vfnprintf() flags */
-#define PF_LEFT		BIT(0)  /* Left-justify */
-#define PF_PADZERO	BIT(1)  /* Pad with 0's not spaces */
-#define PF_SIGN		BIT(2)  /* Add sign (+) for a positive number */
+#define PF_LEFT BIT(0) /* Left-justify */
+#define PF_PADZERO BIT(1) /* Pad with 0's not spaces */
+#define PF_SIGN BIT(2) /* Add sign (+) for a positive number */
+#define PF_64BIT BIT(3) /* Number is 64-bit */
+
+test_export_static char *uint64_to_str(char *buf, int buf_len, uint64_t val,
+				       int precision, int base, bool uppercase)
+{
+	int i;
+	char *str;
+
+	if (buf_len <= 1)
+		return NULL;
+
+	if (base <= 1)
+		return NULL;
+
+	/*
+	 * Convert integer to string, starting at end of
+	 * buffer and working backwards.
+	 */
+	str = buf + buf_len - 1;
+	*(str) = '\0';
+
+	/*
+	 * Fixed-point precision must fit in our buffer.
+	 * Leave space for "0." and the terminating null.
+	 */
+	if (precision > buf_len - 3) {
+		precision = buf_len - 3;
+		if (precision < 0)
+			return NULL;
+	}
+
+	/*
+	 * Handle digits to right of decimal for fixed point numbers.
+	 */
+	for (i = 0; i < precision; i++)
+		*(--str) = '0' + uint64divmod(&val, 10);
+	if (precision >= 0)
+		*(--str) = '.';
+
+	if (!val)
+		*(--str) = '0';
+
+	while (val) {
+		int digit;
+
+		if (str <= buf)
+			return NULL;
+
+		digit = uint64divmod(&val, base);
+		if (digit < 10)
+			*(--str) = '0' + digit;
+		else if (uppercase)
+			*(--str) = 'A' + digit - 10;
+		else
+			*(--str) = 'a' + digit - 10;
+	}
+
+	return str;
+}
+
+int snprintf_timestamp_now(char *str, size_t size)
+{
+	return snprintf_timestamp(str, size, get_time().val);
+}
+
+int snprintf_timestamp(char *str, size_t size, uint64_t timestamp)
+{
+	int len;
+	int precision;
+	char *tmp_str;
+	char tmp_buf[PRINTF_TIMESTAMP_BUF_SIZE];
+	int base = 10;
 
-/* Deactivate the PF_64BIT flag is 64-bit support is disabled. */
-#ifdef NO_UINT64_SUPPORT
-#define PF_64BIT	0
-#else
-#define PF_64BIT	BIT(3)  /* Number is 64-bit */
-#endif
+	if (size == 0)
+		return -EC_ERROR_INVAL;
+
+	/* Ensure string has terminating '\0' in error cases. */
+	str[0] = '\0';
+
+	if (IS_ENABLED(CONFIG_CONSOLE_VERBOSE)) {
+		precision = 6;
+	} else {
+		precision = 3;
+		timestamp /= 1000;
+	}
+
+	tmp_str = uint64_to_str(tmp_buf, sizeof(tmp_buf), timestamp, precision,
+				base, false);
+	if (!tmp_str)
+		return -EC_ERROR_OVERFLOW;
+
+	len = strlen(tmp_str);
+	if (len + 1 > size)
+		return -EC_ERROR_OVERFLOW;
+
+	memcpy(str, tmp_str, len + 1);
+
+	return len;
+}
 
 /*
  * Print the buffer as a string of bytes in hex.
  * Returns 0 on success or an error on failure.
  */
-static int print_hex_buffer(int (*addchar)(void *context, int c),
-			    void *context, const char *vstr, int precision,
-			    int pad_width, int flags)
+static int print_hex_buffer(int (*addchar)(void *context, int c), void *context,
+			    const char *vstr, int precision, int pad_width,
+			    int flags)
 
 {
-
 	/*
 	 * Divide pad_width instead of multiplying precision to avoid overflow
 	 * error in the condition. The "/2" and "2*" can be optimized by
@@ -100,6 +175,54 @@ static int print_hex_buffer(int (*addchar)(void *context, int c),
 	return EC_SUCCESS;
 }
 
+struct hex_char_context {
+	struct hex_buffer_params hex_buf_params;
+	char *str;
+	size_t size;
+};
+
+int add_hex_char(void *context, int c)
+{
+	struct hex_char_context *ctx = context;
+
+	if (ctx->size == 0)
+		return EC_ERROR_OVERFLOW;
+
+	*(ctx->str++) = c;
+	ctx->size--;
+
+	return EC_SUCCESS;
+}
+
+size_t hex_str_buf_size(size_t num_bytes)
+{
+	return 2 * num_bytes + 1;
+}
+
+int snprintf_hex_buffer(char *str, size_t size,
+			const struct hex_buffer_params *params)
+{
+	int rv;
+	struct hex_char_context context = {
+		.hex_buf_params = *params,
+		.str = str,
+		/*
+		 * Reserve space for terminating '\0'.
+		 */
+		.size = size - 1,
+	};
+
+	if (size == 0)
+		return -EC_ERROR_INVAL;
+
+	rv = print_hex_buffer(add_hex_char, &context, params->buffer,
+			      params->size, 0, 0);
+
+	*context.str = '\0';
+
+	return (rv == EC_SUCCESS) ? (context.str - str) : -rv;
+}
+
 int vfnprintf(int (*addchar)(void *context, int c), void *context,
 	      const char *format, va_list args)
 {
@@ -215,17 +338,15 @@ int vfnprintf(int (*addchar)(void *context, int c), void *context,
 
 		} else {
 			int base = 10;
-#ifdef NO_UINT64_SUPPORT
-			uint32_t v;
-#else
 			uint64_t v;
-#endif
-			int ptrspec;
+
 			void *ptrval;
 
 			/*
 			 * Handle length:
-			 * %l - DEPRECATED (see below)
+			 * %l - supports 64-bit longs, 32-bit longs are
+			 *      supported with a config flag, see comment
+			 *      below for more details
 			 * %ll - long long
 			 * %z - size_t
 			 */
@@ -240,18 +361,23 @@ int vfnprintf(int (*addchar)(void *context, int c), void *context,
 				}
 
 				/*
-				 * %l on 32-bit systems is deliberately
-				 * deprecated. It was originally used as
-				 * shorthand for 64-bit values. When
+				 * The CONFIG_PRINTF_LONG_IS_32BITS flag is
+				 * required to enable the %l flag on systems
+				 * where it would signify a 32-bit value.
+				 * Otherwise, %l on 32-bit systems is
+				 * deliberately deprecated. %l was originally
+				 * used as shorthand for 64-bit values. When
 				 * compile-time printf format checking was
 				 * enabled, it had to be cleaned up to be
 				 * sizeof(long), which is 32 bits on today's
 				 * ECs. This presents a mismatch which can be
 				 * dangerous if a new-style printf call is
 				 * cherry-picked into an old firmware branch.
-				 * See crbug.com/984041 for more context.
+				 * For more context, see
+				 * https://issuetracker.google.com/issues/172210614
 				 */
-				if (!(flags & PF_64BIT)) {
+				if (!IS_ENABLED(CONFIG_PRINTF_LONG_IS_32BITS) &&
+				    !(flags & PF_64BIT)) {
 					format = error_str;
 					continue;
 				}
@@ -264,72 +390,11 @@ int vfnprintf(int (*addchar)(void *context, int c), void *context,
 
 			if (c == 'p') {
 				c = -1;
-				ptrspec = *format++;
 				ptrval = va_arg(args, void *);
-				/*
-				 * Avoid null pointer dereference for %ph and
-				 * %pb. %pT and %pP can accept null.
-				 */
-				if (ptrval == NULL
-				    && ptrspec != 'T' && ptrspec != 'P')
-					continue;
-				/* %pT - print a timestamp. */
-				if (ptrspec == 'T' &&
-				    !IS_ENABLED(NO_UINT64_SUPPORT)) {
+				v = (unsigned long)ptrval;
+				base = 16;
+				if (sizeof(unsigned long) == sizeof(uint64_t))
 					flags |= PF_64BIT;
-					if (ptrval == PRINTF_TIMESTAMP_NOW)
-						v = get_time().val;
-					else
-						v = *(uint64_t *)ptrval;
-
-					if (IS_ENABLED(
-						CONFIG_CONSOLE_VERBOSE)) {
-						precision = 6;
-					} else {
-						precision = 3;
-						v /= 1000;
-					}
-
-				} else if (ptrspec == 'h') {
-					/* %ph - Print a hex byte buffer. */
-					struct hex_buffer_params *hexbuf =
-						ptrval;
-					int rc;
-
-					rc = print_hex_buffer(addchar,
-							      context,
-							      hexbuf->buffer,
-							      hexbuf->size,
-							      0,
-							      0);
-
-					if (rc != EC_SUCCESS)
-						return rc;
-
-					continue;
-
-				} else if (ptrspec == 'P') {
-					/* %pP - Print a raw pointer. */
-					v = (unsigned long)ptrval;
-					base = 16;
-					if (sizeof(unsigned long) ==
-					    sizeof(uint64_t))
-						flags |= PF_64BIT;
-
-				} else if (ptrspec == 'b') {
-					/* %pb - Print a binary integer */
-					struct binary_print_params *binary =
-						ptrval;
-
-					v = binary->value;
-					pad_width = binary->count;
-					flags |= PF_PADZERO;
-					base = 2;
-
-				} else {
-					return EC_ERROR_INVAL;
-				}
-
 			} else if (flags & PF_64BIT) {
 				v = va_arg(args, uint64_t);
 			} else {
@@ -337,12 +402,9 @@ int vfnprintf(int (*addchar)(void *context, int c), void *context,
 			}
 
 			switch (c) {
-#ifdef CONFIG_PRINTF_LEGACY_LI_FORMAT
+#ifdef CONFIG_PRINTF_LONG_IS_32BITS
 			case 'i':
-				/* force 32-bit for compatibility */
-				flags &= ~PF_64BIT;
-				/* fall-through */
-#endif /* CONFIG_PRINTF_LEGACY_LI_FORMAT */
+#endif /* CONFIG_PRINTF_LONG_IS_32BITS */
 			case 'd':
 				if (flags & PF_64BIT) {
 					if ((int64_t)v < 0) {
@@ -379,41 +441,9 @@ int vfnprintf(int (*addchar)(void *context, int c), void *context,
 			if (format == error_str)
 				continue; /* Bad format specifier */
 
-			/*
-			 * Convert integer to string, starting at end of
-			 * buffer and working backwards.
-			 */
-			vstr = intbuf + sizeof(intbuf) - 1;
-			*(vstr) = '\0';
-
-			/*
-			 * Fixed-point precision must fit in our buffer.
-			 * Leave space for "0." and the terminating null.
-			 */
-			if (precision > (int)(sizeof(intbuf) - 3))
-				precision = sizeof(intbuf) - 3;
-
-			/*
-			 * Handle digits to right of decimal for fixed point
-			 * numbers.
-			 */
-			for (vlen = 0; vlen < precision; vlen++)
-				*(--vstr) = '0' + divmod(&v, 10);
-			if (precision >= 0)
-				*(--vstr) = '.';
-
-			if (!v)
-				*(--vstr) = '0';
-
-			while (v) {
-				int digit = divmod(&v, base);
-				if (digit < 10)
-					*(--vstr) = '0' + digit;
-				else if (c == 'X')
-					*(--vstr) = 'A' + digit - 10;
-				else
-					*(--vstr) = 'a' + digit - 10;
-			}
+			vstr = uint64_to_str(intbuf, sizeof(intbuf), v,
+					     precision, base, c == 'X');
+			ASSERT(vstr);
 
 			if (sign)
 				*(--vstr) = sign;
@@ -441,7 +471,6 @@ int vfnprintf(int (*addchar)(void *context, int c), void *context,
 			vlen = strnlen(vstr, precision);
 		}
 
-
 		while (vlen < pad_width && !(flags & PF_LEFT)) {
 			if (addchar(context, flags & PF_PADZERO ? '0' : ' '))
 				return EC_ERROR_OVERFLOW;
@@ -460,59 +489,3 @@ int vfnprintf(int (*addchar)(void *context, int c), void *context,
 	/* If we're still here, we consumed all output */
 	return EC_SUCCESS;
 }
-
-/* Context for snprintf() */
-struct snprintf_context {
-	char *str;
-	int size;
-};
-
-/**
- * Add a character to the string context.
- *
- * @param context	Context receiving character
- * @param c		Character to add
- * @return 0 if character added, 1 if character dropped because no space.
- */
-static int snprintf_addchar(void *context, int c)
-{
-	struct snprintf_context *ctx = (struct snprintf_context *)context;
-
-	if (!ctx->size)
-		return 1;
-
-	*(ctx->str++) = c;
-	ctx->size--;
-	return 0;
-}
-
-int snprintf(char *str, int size, const char *format, ...)
-{
-	va_list args;
-	int rv;
-
-	va_start(args, format);
-	rv = vsnprintf(str, size, format, args);
-	va_end(args);
-
-	return rv;
-}
-
-int vsnprintf(char *str, int size, const char *format, va_list args)
-{
-	struct snprintf_context ctx;
-	int rv;
-
-	if (!str || !format || size <= 0)
-		return -EC_ERROR_INVAL;
-
-	ctx.str = str;
-	ctx.size = size - 1;  /* Reserve space for terminating '\0' */
-
-	rv = vfnprintf(snprintf_addchar, &ctx, format, args);
-
-	/* Terminate string */
-	*ctx.str = '\0';
-
-	return (rv == EC_SUCCESS) ? (ctx.str - str) : -rv;
-}
diff --git a/common/pstore_commands.c b/common/pstore_commands.c
index 52270cd1cf..89c996379c 100644
--- a/common/pstore_commands.c
+++ b/common/pstore_commands.c
@@ -1,16 +1,18 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Persistent storage commands for Chrome EC */
 
+#include "builtin/assert.h"
 #include "common.h"
 #include "eeprom.h"
 #include "host_command.h"
 #include "util.h"
 
-enum ec_status pstore_command_get_info(struct host_cmd_handler_args *args)
+static enum ec_status
+pstore_command_get_info(struct host_cmd_handler_args *args)
 {
 	struct ec_response_pstore_info *r = args->response;
 
@@ -22,11 +24,10 @@ enum ec_status pstore_command_get_info(struct host_cmd_handler_args *args)
 	args->response_size = sizeof(*r);
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_PSTORE_INFO,
-		     pstore_command_get_info,
+DECLARE_HOST_COMMAND(EC_CMD_PSTORE_INFO, pstore_command_get_info,
 		     EC_VER_MASK(0));
 
-enum ec_status pstore_command_read(struct host_cmd_handler_args *args)
+static enum ec_status pstore_command_read(struct host_cmd_handler_args *args)
 {
 	const struct ec_params_pstore_read *p = args->params;
 	char *dest = args->response;
@@ -59,11 +60,9 @@ enum ec_status pstore_command_read(struct host_cmd_handler_args *args)
 	args->response_size = p->size;
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_PSTORE_READ,
-		     pstore_command_read,
-		     EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_PSTORE_READ, pstore_command_read, EC_VER_MASK(0));
 
-enum ec_status pstore_command_write(struct host_cmd_handler_args *args)
+static enum ec_status pstore_command_write(struct host_cmd_handler_args *args)
 {
 	const struct ec_params_pstore_write *p = args->params;
 
@@ -96,6 +95,4 @@ enum ec_status pstore_command_write(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_PSTORE_WRITE,
-		     pstore_command_write,
-		     EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_PSTORE_WRITE, pstore_command_write, EC_VER_MASK(0));
diff --git a/common/pwm.c b/common/pwm.c
index 73b12fc20c..e630ddd58e 100644
--- a/common/pwm.c
+++ b/common/pwm.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -45,13 +45,13 @@ __attribute__((weak)) void pwm_set_raw_duty(enum pwm_channel ch, uint16_t duty)
 	int percent;
 
 	/* Convert 16 bit duty to percent on [0, 100] */
-	percent = DIV_ROUND_NEAREST((uint32_t)duty * 100, 65535);
+	percent = PWM_RAW_TO_PERCENT(duty);
 	pwm_set_duty(ch, percent);
 }
 
 __attribute__((weak)) uint16_t pwm_get_raw_duty(enum pwm_channel ch)
 {
-	return (pwm_get_duty(ch) * 65535) / 100;
+	return PWM_PERCENT_TO_RAW(pwm_get_duty(ch));
 }
 
 static enum ec_status
@@ -62,14 +62,12 @@ host_command_pwm_set_duty(struct host_cmd_handler_args *args)
 
 	if (get_target_channel(&channel, p->pwm_type, p->index))
 		return EC_RES_INVALID_PARAM;
-
 	pwm_set_raw_duty(channel, p->duty);
 	pwm_enable(channel, p->duty > 0);
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_DUTY,
-		     host_command_pwm_set_duty,
+DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_DUTY, host_command_pwm_set_duty,
 		     EC_VER_MASK(0));
 
 static enum ec_status
@@ -84,12 +82,12 @@ host_command_pwm_get_duty(struct host_cmd_handler_args *args)
 		return EC_RES_INVALID_PARAM;
 
 	r->duty = pwm_get_raw_duty(channel);
+
 	args->response_size = sizeof(*r);
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_DUTY,
-		     host_command_pwm_get_duty,
+DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_DUTY, host_command_pwm_get_duty,
 		     EC_VER_MASK(0));
 
 /**
@@ -108,13 +106,13 @@ static void print_channel(enum pwm_channel ch, int max_duty)
 		ccprintf("  %d: disabled\n", ch);
 }
 
-static int cc_pwm_duty(int argc, char **argv)
+static int cc_pwm_duty(int argc, const char **argv)
 {
 	int value = 0;
 	int max_duty = 100;
 	int ch;
 	char *e;
-	char *raw;
+	const char *raw;
 
 	if (argc < 2) {
 		ccprintf("PWM channels:\n");
@@ -149,7 +147,7 @@ static int cc_pwm_duty(int argc, char **argv)
 			ccprintf("Setting channel %d to %d\n", ch, value);
 			pwm_enable(ch, 1);
 			(max_duty == 100) ? pwm_set_duty(ch, value) :
-				pwm_set_raw_duty(ch, value);
+					    pwm_set_raw_duty(ch, value);
 		}
 	}
 
@@ -162,7 +160,10 @@ DECLARE_CONSOLE_COMMAND(pwmduty, cc_pwm_duty,
 			"Get/set PWM duty cycles ");
 #endif /* CONFIG_PWM */
 
-/* Initialize all PWM pins as functional */
+/*
+ * Initialize all PWM pins as functional.  This is not required under
+ * Zephyr as pin configuration is automatically performed by chip driver
+ */
 static void pwm_pin_init(void)
 {
 	gpio_config_module(MODULE_PWM, 1);
diff --git a/common/pwm_kblight.c b/common/pwm_kblight.c
index 4967d36df5..bd7e07644d 100644
--- a/common/pwm_kblight.c
+++ b/common/pwm_kblight.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,11 +19,6 @@ static int kblight_pwm_set(int percent)
 	return EC_SUCCESS;
 }
 
-static int kblight_pwm_get(void)
-{
-	return pwm_get_duty(kblight_pwm_ch);
-}
-
 static int kblight_pwm_init(void)
 {
 	/* dnojiri: Why do we need save/restore setting over sysjump? */
@@ -38,9 +33,14 @@ static int kblight_pwm_enable(int enable)
 	return EC_SUCCESS;
 }
 
+static int kblight_pwm_get_enabled(void)
+{
+	return pwm_get_enabled(kblight_pwm_ch);
+}
+
 const struct kblight_drv kblight_pwm = {
 	.init = kblight_pwm_init,
 	.set = kblight_pwm_set,
-	.get = kblight_pwm_get,
 	.enable = kblight_pwm_enable,
+	.get_enabled = kblight_pwm_get_enabled,
 };
diff --git a/common/queue.c b/common/queue.c
index 7b083233ad..ebe9d8b63d 100644
--- a/common/queue.c
+++ b/common/queue.c
@@ -1,21 +1,23 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Queue data structure implementation.
  */
+
+#include "builtin/assert.h"
 #include "console.h"
 #include "queue.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ##args)
 
 static void queue_action_null(struct queue_policy const *policy, size_t count)
 {
 }
 
 struct queue_policy const queue_policy_null = {
-	.add    = queue_action_null,
+	.add = queue_action_null,
 	.remove = queue_action_null,
 };
 
@@ -74,17 +76,17 @@ struct queue_chunk queue_get_write_chunk(struct queue const *q, size_t offset)
 {
 	size_t head = q->state->head & q->buffer_units_mask;
 	size_t tail = (q->state->tail + offset) & q->buffer_units_mask;
-	size_t last = (tail < head) ? head :   /* Wrapped        */
-			q->buffer_units;       /* Normal | Empty */
+	size_t last = (tail < head) ? head : /* Wrapped        */
+				      q->buffer_units; /* Normal | Empty */
 
 	/* Make sure that the offset doesn't exceed free space. */
 	if (queue_space(q) <= offset)
-		return ((struct queue_chunk) {
+		return ((struct queue_chunk){
 			.count = 0,
 			.buffer = NULL,
 		});
 
-	return ((struct queue_chunk) {
+	return ((struct queue_chunk){
 		.count = last - tail,
 		.buffer = q->buffer + (tail * q->unit_bytes),
 	});
@@ -95,10 +97,10 @@ struct queue_chunk queue_get_read_chunk(struct queue const *q)
 	size_t head = q->state->head & q->buffer_units_mask;
 	size_t tail = q->state->tail & q->buffer_units_mask;
 	size_t last = (queue_is_empty(q) ? head : /* Empty          */
-		       ((head < tail) ? tail :    /* Normal         */
-			q->buffer_units));        /* Wrapped | Full */
+			       ((head < tail) ? tail : /* Normal         */
+					q->buffer_units)); /* Wrapped | Full */
 
-	return ((struct queue_chunk) {
+	return ((struct queue_chunk){
 		.count = (last - head),
 		.buffer = q->buffer + (head * q->unit_bytes),
 	});
@@ -134,7 +136,7 @@ size_t queue_add_unit(struct queue const *q, const void *src)
 		return 0;
 
 	if (q->unit_bytes == 1)
-		q->buffer[tail] = *((uint8_t *) src);
+		q->buffer[tail] = *((uint8_t *)src);
 	else
 		memcpy(q->buffer + tail * q->unit_bytes, src, q->unit_bytes);
 
@@ -146,46 +148,33 @@ size_t queue_add_units(struct queue const *q, const void *src, size_t count)
 	return queue_add_memcpy(q, src, count, memcpy);
 }
 
-size_t queue_add_memcpy(struct queue const *q,
-			const void *src,
-			size_t count,
-			void *(*memcpy)(void *dest,
-					const void *src,
-					size_t n))
+size_t queue_add_memcpy(struct queue const *q, const void *src, size_t count,
+			void *(*memcpy)(void *dest, const void *src, size_t n))
 {
 	size_t transfer = MIN(count, queue_space(q));
-	size_t tail     = q->state->tail & q->buffer_units_mask;
-	size_t first    = MIN(transfer, q->buffer_units - tail);
+	size_t tail = q->state->tail & q->buffer_units_mask;
+	size_t first = MIN(transfer, q->buffer_units - tail);
 
-	memcpy(q->buffer + tail * q->unit_bytes,
-	       src,
-	       first * q->unit_bytes);
+	memcpy(q->buffer + tail * q->unit_bytes, src, first * q->unit_bytes);
 
 	if (first < transfer)
 		memcpy(q->buffer,
-		       ((uint8_t const *) src) + first * q->unit_bytes,
+		       ((uint8_t const *)src) + first * q->unit_bytes,
 		       (transfer - first) * q->unit_bytes);
 
 	return queue_advance_tail(q, transfer);
 }
 
-static void queue_read_safe(struct queue const *q,
-			    void *dest,
-			    size_t head,
-			    size_t transfer,
-			    void *(*memcpy)(void *dest,
-					    const void *src,
-					    size_t n))
+static void
+queue_read_safe(struct queue const *q, void *dest, size_t head, size_t transfer,
+		void *(*memcpy)(void *dest, const void *src, size_t n))
 {
 	size_t first = MIN(transfer, q->buffer_units - head);
 
-	memcpy(dest,
-	       q->buffer + head * q->unit_bytes,
-	       first * q->unit_bytes);
+	memcpy(dest, q->buffer + head * q->unit_bytes, first * q->unit_bytes);
 
 	if (first < transfer)
-		memcpy(((uint8_t *) dest) + first * q->unit_bytes,
-		       q->buffer,
+		memcpy(((uint8_t *)dest) + first * q->unit_bytes, q->buffer,
 		       (transfer - first) * q->unit_bytes);
 }
 
@@ -197,7 +186,7 @@ size_t queue_remove_unit(struct queue const *q, void *dest)
 		return 0;
 
 	if (q->unit_bytes == 1)
-		*((uint8_t *) dest) = q->buffer[head];
+		*((uint8_t *)dest) = q->buffer[head];
 	else
 		memcpy(dest, q->buffer + head * q->unit_bytes, q->unit_bytes);
 
@@ -209,39 +198,30 @@ size_t queue_remove_units(struct queue const *q, void *dest, size_t count)
 	return queue_remove_memcpy(q, dest, count, memcpy);
 }
 
-size_t queue_remove_memcpy(struct queue const *q,
-			   void *dest,
-			   size_t count,
-			   void *(*memcpy)(void *dest,
-					   const void *src,
+size_t queue_remove_memcpy(struct queue const *q, void *dest, size_t count,
+			   void *(*memcpy)(void *dest, const void *src,
 					   size_t n))
 {
 	size_t transfer = MIN(count, queue_count(q));
-	size_t head     = q->state->head & q->buffer_units_mask;
+	size_t head = q->state->head & q->buffer_units_mask;
 
 	queue_read_safe(q, dest, head, transfer, memcpy);
 
 	return queue_advance_head(q, transfer);
 }
 
-size_t queue_peek_units(struct queue const *q,
-			void *dest,
-			size_t i,
+size_t queue_peek_units(struct queue const *q, void *dest, size_t i,
 			size_t count)
 {
 	return queue_peek_memcpy(q, dest, i, count, memcpy);
 }
 
-size_t queue_peek_memcpy(struct queue const *q,
-			 void *dest,
-			 size_t i,
+size_t queue_peek_memcpy(struct queue const *q, void *dest, size_t i,
 			 size_t count,
-			 void *(*memcpy)(void *dest,
-				const void *src,
-				size_t n))
+			 void *(*memcpy)(void *dest, const void *src, size_t n))
 {
 	size_t available = queue_count(q);
-	size_t transfer  = MIN(count, available - i);
+	size_t transfer = MIN(count, available - i);
 
 	if (i < available) {
 		size_t head = (q->state->head + i) & q->buffer_units_mask;
@@ -258,7 +238,7 @@ void queue_begin(struct queue const *q, struct queue_iterator *it)
 		it->ptr = NULL;
 	else
 		it->ptr = q->buffer + (q->state->head & q->buffer_units_mask) *
-			q->unit_bytes;
+					      q->unit_bytes;
 	it->_state.offset = 0;
 	it->_state.head = q->state->head;
 	it->_state.tail = q->state->tail;
diff --git a/common/queue_policies.c b/common/queue_policies.c
index 090c837fae..6646d49cf4 100644
--- a/common/queue_policies.c
+++ b/common/queue_policies.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -29,14 +29,14 @@ void queue_remove_direct(struct queue_policy const *policy, size_t count)
 
 struct producer const null_producer = {
 	.queue = NULL,
-	.ops   = &((struct producer_ops const) {
-		 .read = NULL,
+	.ops = &((struct producer_ops const){
+		.read = NULL,
 	}),
 };
 
 struct consumer const null_consumer = {
 	.queue = NULL,
-	.ops   = &((struct consumer_ops const) {
+	.ops = &((struct consumer_ops const){
 		.written = NULL,
 	}),
 };
diff --git a/common/regulator.c b/common/regulator.c
index c3f5d0b99d..5b8da2adc8 100644
--- a/common/regulator.c
+++ b/common/regulator.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,27 +11,28 @@
 #include "host_command.h"
 #include "regulator.h"
 
-static enum ec_status
-hc_regulator_get_info(struct host_cmd_handler_args *args)
+static enum ec_status hc_regulator_get_info(struct host_cmd_handler_args *args)
 {
 	const struct ec_params_regulator_get_info *p = args->params;
 	struct ec_response_regulator_get_info *r = args->response;
+	void *voltages_mv = r->voltages_mv;
+	uint16_t num_voltages;
 	int rv;
 
-	rv = board_regulator_get_info(p->index, r->name, &r->num_voltages,
-				      r->voltages_mv);
+	rv = board_regulator_get_info(p->index, r->name, &num_voltages,
+				      voltages_mv);
 
 	if (rv)
 		return EC_RES_ERROR;
 
+	r->num_voltages = num_voltages;
 	args->response_size = sizeof(*r);
 	return EC_RES_SUCCESS;
 }
 DECLARE_HOST_COMMAND(EC_CMD_REGULATOR_GET_INFO, hc_regulator_get_info,
 		     EC_VER_MASK(0));
 
-static enum ec_status
-hc_regulator_enable(struct host_cmd_handler_args *args)
+static enum ec_status hc_regulator_enable(struct host_cmd_handler_args *args)
 {
 	const struct ec_params_regulator_enable *p = args->params;
 	int rv;
@@ -69,13 +70,15 @@ hc_regulator_get_voltage(struct host_cmd_handler_args *args)
 {
 	const struct ec_params_regulator_get_voltage *p = args->params;
 	struct ec_response_regulator_get_voltage *r = args->response;
+	uint32_t voltage_mv;
 	int rv;
 
-	rv = board_regulator_get_voltage(p->index, &r->voltage_mv);
+	rv = board_regulator_get_voltage(p->index, &voltage_mv);
 
 	if (rv)
 		return EC_RES_ERROR;
 
+	r->voltage_mv = voltage_mv;
 	args->response_size = sizeof(*r);
 	return EC_RES_SUCCESS;
 }
diff --git a/common/rgb_keyboard.c b/common/rgb_keyboard.c
new file mode 100644
index 0000000000..0036cdcd16
--- /dev/null
+++ b/common/rgb_keyboard.c
@@ -0,0 +1,687 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "atomic.h"
+#include "common.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "keyboard_backlight.h"
+#include "registers.h"
+#include "rgb_keyboard.h"
+#include "task.h"
+#include "timer.h"
+#include "util.h"
+
+#include <stdbool.h>
+
+/* Console output macros */
+#define CPUTS(outstr) cputs(CC_RGBKBD, outstr)
+#define CPRINTF(fmt, args...) cprintf(CC_RGBKBD, "RGBKBD: " fmt, ##args)
+#define CPRINTS(fmt, args...) cprints(CC_RGBKBD, "RGBKBD: " fmt, ##args)
+
+test_export_static enum ec_rgbkbd_demo demo =
+#if defined(CONFIG_RGBKBD_DEMO_FLOW)
+	EC_RGBKBD_DEMO_FLOW;
+#elif defined(CONFIG_RGBKBD_DEMO_DOT)
+	EC_RGBKBD_DEMO_DOT;
+#else
+	EC_RGBKBD_DEMO_OFF;
+#endif
+
+const int default_demo_interval_ms = 250;
+test_export_static int demo_interval_ms = -1;
+
+test_export_static uint8_t rgbkbd_table[EC_RGBKBD_MAX_KEY_COUNT];
+
+static enum rgbkbd_state rgbkbd_state;
+
+const struct rgbkbd_init rgbkbd_init_default = {
+	.gcc = RGBKBD_MAX_GCC_LEVEL / 2,
+	.scale = { RGBKBD_MAX_SCALE, RGBKBD_MAX_SCALE, RGBKBD_MAX_SCALE },
+	.color = { .r = 0x0, .g = 0x0, .b = 0x0 },
+};
+
+const struct rgbkbd_init *rgbkbd_init_setting = &rgbkbd_init_default;
+
+void rgbkbd_register_init_setting(const struct rgbkbd_init *setting)
+{
+	rgbkbd_init_setting = setting;
+}
+
+/* Search the grid where x belongs to. */
+static struct rgbkbd *find_grid_from_x(int x, uint8_t *col)
+{
+	struct rgbkbd *ctx = NULL;
+	uint8_t grid;
+
+	*col = 0;
+	for (grid = 0; grid < rgbkbd_count; grid++) {
+		ctx = &rgbkbds[grid];
+		if (x < *col + ctx->cfg->col_len)
+			break;
+		*col += ctx->cfg->col_len;
+	}
+
+	return ctx;
+}
+
+static int set_color_single(struct rgb_s color, int x, int y)
+{
+	struct rgbkbd *ctx = &rgbkbds[0];
+	uint8_t grid, col, offset;
+	int rv;
+
+	if (rgbkbd_hsize <= x || rgbkbd_vsize <= y) {
+		return EC_ERROR_OVERFLOW;
+	}
+
+	ctx = find_grid_from_x(x, &col);
+	grid = RGBKBD_CTX_TO_GRID(ctx);
+	offset = ctx->cfg->row_len * (x - col) + y;
+	ctx->buf[offset] = color;
+
+	rv = ctx->cfg->drv->set_color(ctx, offset, &ctx->buf[offset], 1);
+
+	CPRINTS("%set (%d,%d) to color=(%d,%d,%d) grid=%u offset=%u (%d)",
+		rv ? "Failed to s" : "S", x, y, color.r, color.g, color.b, grid,
+		offset, rv);
+
+	return rv;
+}
+
+test_export_static uint8_t get_grid_size(const struct rgbkbd *ctx)
+{
+	return ctx->cfg->col_len * ctx->cfg->row_len;
+}
+
+static void sync_grids(void)
+{
+	struct rgbkbd *ctx;
+	uint8_t len;
+	int i;
+
+	for (i = 0; i < rgbkbd_count; i++) {
+		ctx = &rgbkbds[i];
+		len = get_grid_size(ctx);
+		ctx->cfg->drv->set_color(ctx, 0, ctx->buf, len);
+	}
+}
+
+test_export_static struct rgb_s rotate_color(struct rgb_s color, int step)
+{
+	color.r += step;
+	if (color.r == 0) {
+		color.g += step;
+		if (color.g == 0) {
+			color.b += step;
+		}
+	}
+
+	return color;
+}
+
+static void rgbkbd_reset_color(struct rgb_s color)
+{
+	struct rgbkbd *ctx;
+	int i, j;
+
+	for (i = 0; i < rgbkbd_count; i++) {
+		ctx = &rgbkbds[i];
+		for (j = 0; j < get_grid_size(ctx); j++)
+			ctx->buf[j] = color;
+	}
+
+	sync_grids();
+}
+
+static void rgbkbd_demo_flow(void)
+{
+	struct rgbkbd *ctx = &rgbkbds[0];
+	static struct rgb_s color;
+	uint8_t len;
+	int i, g;
+
+	for (g = rgbkbd_count - 1; g >= 0; g--) {
+		ctx = &rgbkbds[g];
+		len = get_grid_size(ctx);
+		for (i = len - 1; i > 0; i--)
+			ctx->buf[i] = ctx->buf[i - 1];
+		if (g > 0) {
+			/* Copy the last dot of the g-1 grid to the 1st. */
+			len = get_grid_size(&rgbkbds[g - 1]);
+			ctx->buf[0] = rgbkbds[g - 1].buf[len - 1];
+		}
+	}
+
+	/* Create a new color by shifting R by <step>. */
+	color = rotate_color(color, 32);
+
+	/* Finally, insert a new color to (0, 0). */
+	ctx->buf[0] = color;
+
+	sync_grids();
+
+#ifdef TEST_BUILD
+	task_wake(TASK_ID_TEST_RUNNER);
+#endif
+}
+
+static void rgbkbd_demo_dot(void)
+{
+	static struct rgb_s color = { 0x80, 0, 0 };
+	const struct rgb_s off = { 0, 0, 0 };
+	static uint8_t x, y;
+
+	/* Turn off previous dot. */
+	set_color_single(off, x, y);
+
+	/* Move position. */
+	y++;
+	if (y >= rgbkbd_vsize) {
+		y = 0;
+		x++;
+		if (x >= rgbkbd_hsize) {
+			x = 0;
+			color = rotate_color(color, 0x80);
+		}
+	}
+
+	/* Turn on next dot. */
+	set_color_single(color, x, y);
+
+#ifdef TEST_BUILD
+	task_wake(TASK_ID_TEST_RUNNER);
+#endif
+}
+
+static void rgbkbd_demo_run(enum ec_rgbkbd_demo id)
+{
+	switch (id) {
+	case EC_RGBKBD_DEMO_FLOW:
+		rgbkbd_demo_flow();
+		break;
+	case EC_RGBKBD_DEMO_DOT:
+		rgbkbd_demo_dot();
+		break;
+	case EC_RGBKBD_DEMO_OFF:
+	default:
+		break;
+	}
+}
+
+test_export_static void rgbkbd_init_lookup_table(void)
+{
+	bool add = true;
+	int i, k = 0;
+
+	if (rgbkbd_map[0] != RGBKBD_DELM ||
+	    rgbkbd_map[rgbkbd_map_size - 1] != RGBKBD_DELM) {
+		CPRINTS("Invalid Key-LED map");
+		return;
+	}
+
+	/*
+	 * rgbkbd_map[] consists of LED IDs separated by a delimiter (0xff).
+	 * When 'add' is true, the next byte will be the beginning of a new LED
+	 * group, thus, its index will be added to rgbkbd_table. If the next
+	 * byte is a back-to-back 0xff, it's an empty group and still added to
+	 * rgbkbd_table.
+	 */
+	for (i = 0; i < rgbkbd_map_size && k < EC_RGBKBD_MAX_KEY_COUNT; i++) {
+		if (rgbkbd_map[i] != RGBKBD_DELM) {
+			if (add)
+				rgbkbd_table[k++] = i;
+			/* Don't add next LED ID or TERM. */
+			add = false;
+			continue;
+		}
+		if (add)
+			rgbkbd_table[k++] = i;
+		add = true;
+	}
+
+	/* A valid map should have exactly as many entries as MAX_KEY_ID. */
+	if (k < EC_RGBKBD_MAX_KEY_COUNT)
+		CPRINTS("Key-LED map is too short (found %d)", k);
+
+	/*
+	 * Whether k is equal to or shorter than EC_RGBKBD_MAX_KEY_COUNT, the
+	 * LED group pointed by rgbkbd_table[k-1] is guaranteed to be properly
+	 * terminated. The rest of the table entries remain non-existent (0).
+	 */
+}
+
+static int rgbkbd_set_global_brightness(uint8_t gcc)
+{
+	int e, grid;
+	int rv = EC_SUCCESS;
+
+	for (grid = 0; grid < rgbkbd_count; grid++) {
+		struct rgbkbd *ctx = &rgbkbds[grid];
+
+		e = ctx->cfg->drv->set_gcc(ctx, gcc);
+		if (e) {
+			CPRINTS("Failed to set GCC to %u for grid=%d (%d)", gcc,
+				grid, e);
+			rv = e;
+			continue;
+		}
+	}
+
+	CPRINTS("Set GCC to %u", gcc);
+
+	/* Return EC_SUCCESS or the last error. */
+	return rv;
+}
+
+static int rgbkbd_reset_scale(struct rgb_s scale)
+{
+	int e, i, rv = EC_SUCCESS;
+
+	for (i = 0; i < rgbkbd_count; i++) {
+		struct rgbkbd *ctx = &rgbkbds[i];
+
+		e = ctx->cfg->drv->set_scale(ctx, 0, scale, get_grid_size(ctx));
+		if (e) {
+			CPRINTS("Failed to set scale to [%d,%d,%d] Grid%d (%d)",
+				scale.r, scale.g, scale.b, i, e);
+			rv = e;
+		}
+	}
+
+	return rv;
+}
+
+static int rgbkbd_set_scale(struct rgb_s scale, uint8_t key)
+{
+	struct rgbkbd *ctx;
+	uint8_t j, col, grid, offset;
+	union rgbkbd_coord_u8 led;
+	int rv = EC_SUCCESS;
+
+	j = rgbkbd_table[key];
+	if (j == RGBKBD_NONE)
+		return rv;
+
+	do {
+		led.u8 = rgbkbd_map[j++];
+		if (led.u8 == RGBKBD_DELM)
+			/* Reached end of the group. */
+			break;
+		ctx = find_grid_from_x(led.coord.x, &col);
+		grid = RGBKBD_CTX_TO_GRID(ctx);
+		/*
+		 * offset is the relative position in our buffer where LED
+		 * colors are cached. RGB is grouped as one. Note this differs
+		 * from the external buffer (LED drivers' buffer) where RGB is
+		 * individually counted.
+		 *
+		 * offset can be calculated by multiplying the horizontal
+		 * position (x) by the size of the rows, then, adding the
+		 * vertical position (y).
+		 */
+		offset = ctx->cfg->row_len * (led.coord.x - col) + led.coord.y;
+		rv = ctx->cfg->drv->set_scale(ctx, offset, scale, 1);
+		if (rv) {
+			CPRINTS("Failed to set scale to [%d,%d,%d] Grid%d (%d)",
+				scale.r, scale.g, scale.b, grid, rv);
+			return rv;
+		}
+	} while (led.u8 != RGBKBD_DELM);
+
+	return rv;
+}
+
+static int rgbkbd_init(void)
+{
+	int rv = EC_SUCCESS;
+	int e, i;
+
+	for (i = 0; i < rgbkbd_count; i++) {
+		struct rgbkbd *ctx = &rgbkbds[i];
+		uint8_t gcc = rgbkbd_init_setting->gcc;
+
+		e = ctx->cfg->drv->init(ctx);
+		if (e) {
+			CPRINTS("Failed to init GRID%d (%d)", i, e);
+			rv = e;
+			continue;
+		}
+
+		e = ctx->cfg->drv->set_gcc(ctx, gcc);
+		if (e) {
+			CPRINTS("Failed to set GCC to %u for grid=%d (%d)", gcc,
+				i, e);
+			rv = e;
+			continue;
+		}
+
+		CPRINTS("Initialized GRID%d", i);
+	}
+
+	rv |= rgbkbd_reset_scale(rgbkbd_init_setting->scale);
+	rgbkbd_reset_color(rgbkbd_init_setting->color);
+
+	if (rv == EC_SUCCESS)
+		rgbkbd_state = RGBKBD_STATE_INITIALIZED;
+
+	return rv;
+}
+
+/* This is used to re-init on the first enable. */
+static bool reinitialized;
+static int rgbkbd_late_init(void)
+{
+	if (IS_ENABLED(CONFIG_IS31FL3743B_LATE_INIT)) {
+		if (!reinitialized) {
+			int rv;
+
+			CPRINTS("Re-initializing");
+			rv = rgbkbd_init();
+			if (rv)
+				return rv;
+			reinitialized = true;
+		}
+	}
+	return EC_SUCCESS;
+}
+
+static int rgbkbd_enable(int enable)
+{
+	int rv = EC_SUCCESS;
+	int e, i;
+
+	if (enable) {
+		if (rgbkbd_state == RGBKBD_STATE_ENABLED)
+			return EC_SUCCESS;
+		rv = rgbkbd_late_init();
+		if (rv)
+			return rv;
+	} else {
+		if (rgbkbd_state == RGBKBD_STATE_DISABLED)
+			return EC_SUCCESS;
+	}
+
+	for (i = 0; i < rgbkbd_count; i++) {
+		struct rgbkbd *ctx = &rgbkbds[i];
+
+		e = ctx->cfg->drv->enable(ctx, enable);
+		if (e) {
+			CPRINTS("Failed to %s GRID%d (%d)",
+				enable ? "enable" : "disable", i, e);
+			rv = e;
+			continue;
+		}
+
+		CPRINTS("%s GRID%d", enable ? "Enabled" : "Disabled", i);
+	}
+
+	if (rv == EC_SUCCESS) {
+		rgbkbd_state = enable ? RGBKBD_STATE_ENABLED :
+					RGBKBD_STATE_DISABLED;
+	}
+
+	/* Return EC_SUCCESS or the last error. */
+	return rv;
+}
+
+static void rgbkbd_demo_set(enum ec_rgbkbd_demo new_demo)
+{
+	CPRINTS("Setting demo %d with %d ms interval", demo, demo_interval_ms);
+
+	demo = new_demo;
+
+	/* suspend demo task */
+	demo_interval_ms = -1;
+	rgbkbd_init();
+	rgbkbd_enable(1);
+
+	if (demo == EC_RGBKBD_DEMO_OFF)
+		return;
+
+	demo_interval_ms = default_demo_interval_ms;
+
+	/* start demo */
+	task_wake(TASK_ID_RGBKBD);
+}
+
+static int rgbkbd_kblight_set(int percent)
+{
+	uint8_t gcc = DIV_ROUND_NEAREST(percent * RGBKBD_MAX_GCC_LEVEL, 100);
+	int rv = rgbkbd_late_init();
+
+	if (rv)
+		return rv;
+
+	return rgbkbd_set_global_brightness(gcc);
+}
+
+static int rgbkbd_get_enabled(void)
+{
+	return rgbkbd_state >= RGBKBD_STATE_ENABLED;
+}
+
+static void rgbkbd_reset(void)
+{
+	board_kblight_shutdown();
+	board_kblight_init();
+	rgbkbd_state = RGBKBD_STATE_RESET;
+	reinitialized = false;
+}
+
+const struct kblight_drv kblight_rgbkbd = {
+	.init = rgbkbd_init,
+	.set = rgbkbd_kblight_set,
+	.enable = rgbkbd_enable,
+	.get_enabled = rgbkbd_get_enabled,
+};
+
+void rgbkbd_task(void *u)
+{
+	rgbkbd_init_lookup_table();
+
+	while (1) {
+		task_wait_event(demo_interval_ms * MSEC);
+		if (demo)
+			rgbkbd_demo_run(demo);
+	}
+}
+
+static enum ec_status hc_rgbkbd_set_color(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_rgbkbd_set_color *p = args->params;
+	int i;
+
+	if (p->start_key + p->length > EC_RGBKBD_MAX_KEY_COUNT)
+		return EC_RES_INVALID_PARAM;
+
+	if (rgbkbd_late_init())
+		return EC_RES_ERROR;
+
+	for (i = 0; i < p->length; i++) {
+		uint8_t j = rgbkbd_table[p->start_key + i];
+		union rgbkbd_coord_u8 led;
+
+		if (j == RGBKBD_NONE)
+			/* Null or uninitialized entry */
+			continue;
+
+		do {
+			led.u8 = rgbkbd_map[j++];
+			if (led.u8 == RGBKBD_DELM)
+				/* Reached end of the group. */
+				break;
+			if (set_color_single(p->color[i], led.coord.x,
+					     led.coord.y))
+				return EC_RES_ERROR;
+		} while (led.u8 != RGBKBD_DELM);
+	}
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_RGBKBD_SET_COLOR, hc_rgbkbd_set_color,
+		     EC_VER_MASK(0));
+
+static enum ec_status hc_rgbkbd(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_rgbkbd *p = args->params;
+	struct ec_response_rgbkbd *r = args->response;
+	enum ec_status rv = EC_RES_SUCCESS;
+
+	args->response_size = sizeof(*r);
+
+	if (rgbkbd_late_init())
+		return EC_RES_ERROR;
+
+	switch (p->subcmd) {
+	case EC_RGBKBD_SUBCMD_CLEAR:
+		rgbkbd_reset_color(p->color);
+		break;
+	case EC_RGBKBD_SUBCMD_DEMO:
+		if (p->demo >= EC_RGBKBD_DEMO_COUNT)
+			return EC_RES_INVALID_PARAM;
+		rgbkbd_demo_set(p->demo);
+		break;
+	case EC_RGBKBD_SUBCMD_SET_SCALE:
+		if (rgbkbd_set_scale(p->set_scale.scale, p->set_scale.key))
+			rv = EC_RES_ERROR;
+		break;
+	case EC_RGBKBD_SUBCMD_GET_CONFIG:
+		r->rgbkbd_type = rgbkbd_type;
+		break;
+	default:
+		rv = EC_RES_INVALID_PARAM;
+		break;
+	}
+
+	return rv;
+}
+DECLARE_HOST_COMMAND(EC_CMD_RGBKBD, hc_rgbkbd, EC_VER_MASK(0));
+
+static int int_to_rgb(const char *code, struct rgb_s *rgb)
+{
+	int val;
+	char *end;
+
+	val = strtoi(code, &end, 0);
+	if (*end || val > EC_RGBKBD_MAX_RGB_COLOR)
+		return EC_ERROR_INVAL;
+
+	rgb->r = (val >> 16) & 0xff;
+	rgb->g = (val >> 8) & 0xff;
+	rgb->b = (val >> 0) & 0xff;
+
+	return EC_SUCCESS;
+}
+
+test_export_static int cc_rgb(int argc, const char **argv)
+{
+	char *end, *comma;
+	struct rgb_s rgb, scale;
+	int gcc, x, y, val;
+	int i, rv = EC_SUCCESS;
+
+	if (argc < 2 || 5 < argc) {
+		return EC_ERROR_PARAM_COUNT;
+	}
+
+	comma = strstr(argv[1], ",");
+	if (comma && strlen(comma) > 1) {
+		/* Usage 2 */
+		/* Found ',' and more string after that. Split it into two. */
+		*comma = '\0';
+		x = strtoi(argv[1], &end, 0);
+		if (*end || x >= rgbkbd_hsize)
+			return EC_ERROR_PARAM1;
+		y = strtoi(comma + 1, &end, 0);
+		if (*end || y >= rgbkbd_vsize)
+			return EC_ERROR_PARAM1;
+
+		rv = int_to_rgb(argv[2], &rgb);
+		if (rv)
+			return EC_ERROR_PARAM2;
+
+		rgbkbd_demo_set(EC_RGBKBD_DEMO_OFF);
+
+		if (y < 0) {
+			/* Set all LEDs on column x. */
+			ccprintf("Set column %d to 0x%02x%02x%02x\n", x, rgb.r,
+				 rgb.g, rgb.b);
+			for (i = 0; i < rgbkbd_vsize; i++)
+				rv = set_color_single(rgb, x, i);
+		} else if (x < 0) {
+			/* Set all LEDs on row y. */
+			ccprintf("Set row %d to 0x%02x%02x%02x\n", y, rgb.r,
+				 rgb.g, rgb.b);
+			for (i = 0; i < rgbkbd_hsize; i++)
+				rv = set_color_single(rgb, i, y);
+		} else {
+			ccprintf("Set (%d,%d) to 0x%02x%02x%02x\n", x, y, rgb.r,
+				 rgb.g, rgb.b);
+			rv = set_color_single(rgb, x, y);
+		}
+	} else if (!strcasecmp(argv[1], "all")) {
+		/* Usage 3 */
+		rv = int_to_rgb(argv[2], &rgb);
+		if (rv)
+			return EC_ERROR_PARAM2;
+
+		rgbkbd_demo_set(EC_RGBKBD_DEMO_OFF);
+		rgbkbd_reset_color(rgb);
+	} else if (!strcasecmp(argv[1], "demo")) {
+		/* Usage 4 */
+		val = strtoi(argv[2], &end, 0);
+		if (*end || val >= EC_RGBKBD_DEMO_COUNT)
+			return EC_ERROR_PARAM1;
+		rgbkbd_demo_set(val);
+	} else if (!strcasecmp(argv[1], "reset")) {
+		/* Usage 5: Reset */
+		rgbkbd_reset();
+		rv = rgbkbd_init();
+		if (rv)
+			return rv;
+		rv = rgbkbd_enable(0);
+	} else if (!strcasecmp(argv[1], "enable")) {
+		/* Usage 5: Enable */
+		rv = rgbkbd_enable(1);
+	} else if (!strcasecmp(argv[1], "disable")) {
+		/* Usage 5: Disable */
+		rv = rgbkbd_enable(0);
+	} else if (!strcasecmp(argv[1], "scale")) {
+		/* Usage 6 */
+		rv = int_to_rgb(argv[2], &scale);
+		if (rv)
+			return EC_ERROR_PARAM2;
+		rv = rgbkbd_reset_scale(scale);
+	} else if (!strcasecmp(argv[1], "red")) {
+		rgb.r = 255;
+		rgb.g = 0;
+		rgb.b = 0;
+		rgbkbd_reset_color(rgb);
+	} else {
+		/* Usage 1 */
+		if (argc != 2)
+			return EC_ERROR_PARAM_COUNT;
+		gcc = strtoi(argv[1], &end, 0);
+		if (*end || gcc < 0 || gcc > UINT8_MAX)
+			return EC_ERROR_PARAM1;
+		rv = rgbkbd_set_global_brightness(gcc);
+	}
+
+	return rv;
+}
+#ifndef TEST_BUILD
+DECLARE_CONSOLE_COMMAND(rgb, cc_rgb,
+			"\n"
+			"1. rgb <global-brightness>\n"
+			"2. rgb <col,row> <24-bit RGB code>\n"
+			"3. rgb all <24-bit RGB code>\n"
+			"4. rgb demo <id>\n"
+			"5. rgb reset/enable/disable/red\n"
+			"6. rgb scale <24-bit RGB scale>\n",
+			"Control RGB keyboard");
+#endif
diff --git a/common/rollback.c b/common/rollback.c
index d4f206b2b6..2ff7b3f40b 100644
--- a/common/rollback.c
+++ b/common/rollback.c
@@ -1,15 +1,13 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Rollback protection logic. */
 
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
-#ifdef CONFIG_LIBCRYPTOC
-#include "cryptoc/util.h"
-#endif
 #include "flash.h"
 #include "hooks.h"
 #include "host_command.h"
@@ -24,8 +22,20 @@
 #include "trng.h"
 #include "util.h"
 
+#ifdef CONFIG_ROLLBACK_SECRET_SIZE
+#ifdef CONFIG_BORINGSSL_CRYPTO
+#include "openssl/mem.h"
+#define secure_clear(buffer, size) OPENSSL_cleanse(buffer, size)
+#elif defined(CONFIG_LIBCRYPTOC)
+#include "cryptoc/util.h"
+#define secure_clear(buffer, size) always_memset(buffer, 0, size)
+#else
+#error One of CONFIG_BORINGSSL_CRYPTO or CONFIG_LIBCRYPTOC should be defined
+#endif
+#endif
+
 /* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 /* Number of rollback regions */
 #define ROLLBACK_REGIONS 2
@@ -34,9 +44,9 @@ static int get_rollback_offset(int region)
 {
 #ifdef CONFIG_FLASH_MULTIPLE_REGION
 	int rv;
-	int rollback_start_bank = flash_bank_index(CONFIG_ROLLBACK_OFF);
+	int rollback_start_bank = crec_flash_bank_index(CONFIG_ROLLBACK_OFF);
 
-	rv = flash_bank_start_offset(rollback_start_bank + region);
+	rv = crec_flash_bank_start_offset(rollback_start_bank + region);
 	ASSERT(rv >= 0);
 	return rv;
 #else
@@ -44,49 +54,35 @@ static int get_rollback_offset(int region)
 #endif
 }
 
-#ifdef SECTION_IS_RO
-static int get_rollback_erase_size_bytes(int region)
-{
-	int erase_size;
-
-#ifndef CONFIG_FLASH_MULTIPLE_REGION
-	erase_size = CONFIG_FLASH_ERASE_SIZE;
-#else
-	int rollback_start_bank = flash_bank_index(CONFIG_ROLLBACK_OFF);
-
-	erase_size = flash_bank_erase_size(rollback_start_bank + region);
-#endif
-	ASSERT(erase_size > 0);
-	ASSERT(ROLLBACK_REGIONS * erase_size <= CONFIG_ROLLBACK_SIZE);
-	ASSERT(sizeof(struct rollback_data) <= erase_size);
-	return erase_size;
-}
-#endif
-
 /*
  * When MPU is available, read rollback with interrupts disabled, to minimize
  * time protection is left open.
  */
-static void lock_rollback(void)
+static void lock_rollback(uint32_t key)
 {
 #ifdef CONFIG_ROLLBACK_MPU_PROTECT
 	mpu_lock_rollback(1);
-	interrupt_enable();
+	irq_unlock(key);
 #endif
 }
 
-static void unlock_rollback(void)
+static uint32_t unlock_rollback(void)
 {
 #ifdef CONFIG_ROLLBACK_MPU_PROTECT
-	interrupt_disable();
+	uint32_t key;
+
+	key = irq_lock();
 	mpu_lock_rollback(0);
+	return key;
+#else
+	return 0;
 #endif
 }
 
 static void clear_rollback(struct rollback_data *data)
 {
 #ifdef CONFIG_ROLLBACK_SECRET_SIZE
-	always_memset(data->secret, 0, sizeof(data->secret));
+	secure_clear(data->secret, sizeof(data->secret));
 #endif
 }
 
@@ -94,13 +90,14 @@ int read_rollback(int region, struct rollback_data *data)
 {
 	int offset;
 	int ret = EC_SUCCESS;
+	uint32_t key;
 
 	offset = get_rollback_offset(region);
 
-	unlock_rollback();
-	if (flash_read(offset, sizeof(*data), (char *)data))
+	key = unlock_rollback();
+	if (crec_flash_read(offset, sizeof(*data), (char *)data))
 		ret = EC_ERROR_UNKNOWN;
-	lock_rollback();
+	lock_rollback(key);
 
 	return ret;
 }
@@ -114,7 +111,7 @@ int read_rollback(int region, struct rollback_data *data)
  * Return most recent region index on success (>= 0, or 0 if no rollback
  * region is valid), negative value on error.
  */
-static int get_latest_rollback(struct rollback_data *data)
+test_mockable_static int get_latest_rollback(struct rollback_data *data)
 {
 	int ret = -1;
 	int region;
@@ -165,9 +162,9 @@ int32_t rollback_get_minimum_version(void)
 }
 
 #ifdef CONFIG_ROLLBACK_SECRET_SIZE
-test_mockable int rollback_get_secret(uint8_t *secret)
+test_mockable enum ec_error_list rollback_get_secret(uint8_t *secret)
 {
-	int ret = EC_ERROR_UNKNOWN;
+	enum ec_error_list ret = EC_ERROR_UNKNOWN;
 	struct rollback_data data;
 
 	if (get_latest_rollback(&data) < 0)
@@ -186,27 +183,41 @@ test_mockable int rollback_get_secret(uint8_t *secret)
 #endif
 
 #ifdef CONFIG_ROLLBACK_UPDATE
+static int get_rollback_erase_size_bytes(int region)
+{
+	int erase_size;
+
+#ifndef CONFIG_FLASH_MULTIPLE_REGION
+	erase_size = CONFIG_FLASH_ERASE_SIZE;
+#else
+	int rollback_start_bank = crec_flash_bank_index(CONFIG_ROLLBACK_OFF);
+
+	erase_size = crec_flash_bank_erase_size(rollback_start_bank + region);
+#endif
+	ASSERT(erase_size > 0);
+	ASSERT(ROLLBACK_REGIONS * erase_size <= CONFIG_ROLLBACK_SIZE);
+	ASSERT(sizeof(struct rollback_data) <= erase_size);
+	return erase_size;
+}
 
 #ifdef CONFIG_ROLLBACK_SECRET_SIZE
-static int add_entropy(uint8_t *dst, const uint8_t *src,
-		       const uint8_t *add, unsigned int add_len)
+#ifdef CONFIG_SHA256
+static int add_entropy(uint8_t *dst, const uint8_t *src, const uint8_t *add,
+		       unsigned int add_len)
 {
 	int ret = 0;
-#ifdef CONFIG_SHA256
-BUILD_ASSERT(SHA256_DIGEST_SIZE == CONFIG_ROLLBACK_SECRET_SIZE);
+	BUILD_ASSERT(SHA256_DIGEST_SIZE == CONFIG_ROLLBACK_SECRET_SIZE);
 	struct sha256_ctx ctx;
 	uint8_t *hash;
-#ifdef CONFIG_ROLLBACK_SECRET_LOCAL_ENTROPY_SIZE
-	uint8_t extra;
-	int i;
-#endif
 
 	SHA256_init(&ctx);
 	SHA256_update(&ctx, src, CONFIG_ROLLBACK_SECRET_SIZE);
 	SHA256_update(&ctx, add, add_len);
 #ifdef CONFIG_ROLLBACK_SECRET_LOCAL_ENTROPY_SIZE
 	/* Add some locally produced entropy */
-	for (i = 0; i < CONFIG_ROLLBACK_SECRET_LOCAL_ENTROPY_SIZE; i++) {
+	for (int i = 0; i < CONFIG_ROLLBACK_SECRET_LOCAL_ENTROPY_SIZE; i++) {
+		uint8_t extra;
+
 		if (!board_get_entropy(&extra, 1))
 			goto failed;
 		SHA256_update(&ctx, &extra, 1);
@@ -220,12 +231,12 @@ BUILD_ASSERT(SHA256_DIGEST_SIZE == CONFIG_ROLLBACK_SECRET_SIZE);
 #ifdef CONFIG_ROLLBACK_SECRET_LOCAL_ENTROPY_SIZE
 failed:
 #endif
-	always_memset(&ctx, 0, sizeof(ctx));
-#else
-#error "Adding entropy to secret in rollback region requires SHA256."
-#endif
+	secure_clear(&ctx, sizeof(ctx));
 	return ret;
 }
+#else
+#error "Adding entropy to secret in rollback region requires SHA256."
+#endif /* CONFIG_SHA256 */
 #endif /* CONFIG_ROLLBACK_SECRET_SIZE */
 
 /**
@@ -240,27 +251,28 @@ BUILD_ASSERT(SHA256_DIGEST_SIZE == CONFIG_ROLLBACK_SECRET_SIZE);
  *
  * @return EC_SUCCESS on success, EC_ERROR_* on error.
  */
-static int rollback_update(int32_t next_min_version,
-			   const uint8_t *entropy, unsigned int length)
+static int rollback_update(int32_t next_min_version, const uint8_t *entropy,
+			   unsigned int length)
 {
 	/*
 	 * When doing flash_write operation, the data needs to be in blocks
 	 * of CONFIG_FLASH_WRITE_SIZE, pad rollback_data as required.
 	 */
 	uint8_t block[CONFIG_FLASH_WRITE_SIZE *
-		DIV_ROUND_UP(sizeof(struct rollback_data),
-			CONFIG_FLASH_WRITE_SIZE)];
+		      DIV_ROUND_UP(sizeof(struct rollback_data),
+				   CONFIG_FLASH_WRITE_SIZE)];
 	struct rollback_data *data = (struct rollback_data *)block;
 	BUILD_ASSERT(sizeof(block) >= sizeof(*data));
 	int erase_size, offset, region, ret;
+	uint32_t key;
 
-	if (flash_get_protect() & EC_FLASH_PROTECT_ROLLBACK_NOW) {
+	if (crec_flash_get_protect() & EC_FLASH_PROTECT_ROLLBACK_NOW) {
 		ret = EC_ERROR_ACCESS_DENIED;
 		goto out;
 	}
 
 	/* Initialize the rest of the block. */
-	memset(&block[sizeof(*data)], 0xff, sizeof(block)-sizeof(*data));
+	memset(&block[sizeof(*data)], 0xff, sizeof(block) - sizeof(*data));
 
 	region = get_latest_rollback(data);
 
@@ -324,15 +336,15 @@ static int rollback_update(int32_t next_min_version,
 		goto out;
 	}
 
-	unlock_rollback();
-	if (flash_erase(offset, erase_size)) {
+	key = unlock_rollback();
+	if (crec_flash_erase(offset, erase_size)) {
 		ret = EC_ERROR_UNKNOWN;
-		lock_rollback();
+		lock_rollback(key);
 		goto out;
 	}
 
-	ret = flash_write(offset, sizeof(block), block);
-	lock_rollback();
+	ret = crec_flash_write(offset, sizeof(block), block);
+	lock_rollback(key);
 
 out:
 	clear_rollback(data);
@@ -349,7 +361,7 @@ int rollback_add_entropy(const uint8_t *data, unsigned int len)
 	return rollback_update(-1, data, len);
 }
 
-static int command_rollback_update(int argc, char **argv)
+static int command_rollback_update(int argc, const char **argv)
 {
 	int32_t min_version;
 	char *e;
@@ -364,24 +376,34 @@ static int command_rollback_update(int argc, char **argv)
 
 	return rollback_update_version(min_version);
 }
-DECLARE_CONSOLE_COMMAND(rollbackupdate, command_rollback_update,
-			"min_version",
+DECLARE_CONSOLE_COMMAND(rollbackupdate, command_rollback_update, "min_version",
 			"Update rollback info");
 
 #ifdef CONFIG_ROLLBACK_SECRET_SIZE
-static int command_rollback_add_entropy(int argc, char **argv)
+static int command_rollback_add_entropy(int argc, const char **argv)
 {
+	uint8_t rand[CONFIG_ROLLBACK_SECRET_SIZE];
+	const uint8_t *data;
 	int len;
 
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
+	if (argc < 2) {
+		if (!IS_ENABLED(CONFIG_RNG))
+			return EC_ERROR_PARAM_COUNT;
 
-	len = strlen(argv[1]);
+		trng_init();
+		trng_rand_bytes(rand, sizeof(rand));
+		trng_exit();
+
+		data = rand;
+		len = sizeof(rand);
+	} else {
+		data = argv[1];
+		len = strlen(argv[1]);
+	}
 
-	return rollback_add_entropy(argv[1], len);
+	return rollback_add_entropy(data, len);
 }
-DECLARE_CONSOLE_COMMAND(rollbackaddent, command_rollback_add_entropy,
-			"data",
+DECLARE_CONSOLE_COMMAND(rollbackaddent, command_rollback_add_entropy, "[data]",
 			"Add entropy to rollback block");
 
 #ifdef CONFIG_RNG
@@ -400,9 +422,9 @@ static void add_entropy_deferred(void)
 	if (add_entropy_action == ADD_ENTROPY_RESET_ASYNC)
 		repeat = ROLLBACK_REGIONS;
 
-	init_trng();
+	trng_init();
 	do {
-		rand_bytes(rand, sizeof(rand));
+		trng_rand_bytes(rand, sizeof(rand));
 		if (rollback_add_entropy(rand, sizeof(rand)) != EC_SUCCESS) {
 			add_entropy_rv = EC_RES_ERROR;
 			goto out;
@@ -411,7 +433,7 @@ static void add_entropy_deferred(void)
 
 	add_entropy_rv = EC_RES_SUCCESS;
 out:
-	exit_trng();
+	trng_exit();
 }
 DECLARE_DEFERRED(add_entropy_deferred);
 
@@ -438,14 +460,13 @@ hc_rollback_add_entropy(struct host_cmd_handler_args *args)
 
 	return EC_RES_INVALID_PARAM;
 }
-DECLARE_HOST_COMMAND(EC_CMD_ADD_ENTROPY,
-		     hc_rollback_add_entropy,
+DECLARE_HOST_COMMAND(EC_CMD_ADD_ENTROPY, hc_rollback_add_entropy,
 		     EC_VER_MASK(0));
 #endif /* CONFIG_RNG */
 #endif /* CONFIG_ROLLBACK_SECRET_SIZE */
 #endif /* CONFIG_ROLLBACK_UPDATE */
 
-static int command_rollback_info(int argc, char **argv)
+static int command_rollback_info(int argc, const char **argv)
 {
 	int ret = EC_ERROR_UNKNOWN;
 	int region, min_region;
@@ -467,14 +488,13 @@ static int command_rollback_info(int argc, char **argv)
 		if (ret)
 			goto failed;
 
-		ccprintf("rollback %d: %08x %08x %08x",
-			region, data.id, data.rollback_min_version,
-			data.cookie);
+		ccprintf("rollback %d: %08x %08x %08x", region, data.id,
+			 data.rollback_min_version, data.cookie);
 #ifdef CONFIG_ROLLBACK_SECRET_SIZE
 		if (!system_is_locked()) {
 			/* If system is unlocked, show some of the secret. */
 			ccprintf(" [%02x..%02x]", data.secret[0],
-				data.secret[CONFIG_ROLLBACK_SECRET_SIZE-1]);
+				 data.secret[CONFIG_ROLLBACK_SECRET_SIZE - 1]);
 		}
 #endif
 		if (min_region == region)
@@ -487,8 +507,7 @@ static int command_rollback_info(int argc, char **argv)
 	clear_rollback(&data);
 	return ret;
 }
-DECLARE_SAFE_CONSOLE_COMMAND(rollbackinfo, command_rollback_info,
-			     NULL,
+DECLARE_SAFE_CONSOLE_COMMAND(rollbackinfo, command_rollback_info, NULL,
 			     "Print rollback info");
 
 static enum ec_status
@@ -515,6 +534,5 @@ host_command_rollback_info(struct host_cmd_handler_args *args)
 	clear_rollback(&data);
 	return ret;
 }
-DECLARE_HOST_COMMAND(EC_CMD_ROLLBACK_INFO,
-		     host_command_rollback_info,
+DECLARE_HOST_COMMAND(EC_CMD_ROLLBACK_INFO, host_command_rollback_info,
 		     EC_VER_MASK(0));
diff --git a/common/rollback_private.h b/common/rollback_private.h
index c757882f4f..1dbbd4f430 100644
--- a/common/rollback_private.h
+++ b/common/rollback_private.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/common/rsa.c b/common/rsa.c
index 10f0afa4b4..4df6fc136a 100644
--- a/common/rsa.c
+++ b/common/rsa.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -39,16 +39,14 @@ static int ge_mod(const struct rsa_public_key *key, const uint32_t *a)
 		if (a[i] > key->n[i])
 			return 1;
 	}
-	return 1;  /* equal */
+	return 1; /* equal */
 }
 
 /**
  * Montgomery c[] += a * b[] / R % mod
  */
-static void mont_mul_add(const struct rsa_public_key *key,
-			 uint32_t *c,
-			 const uint32_t a,
-			 const uint32_t *b)
+static void mont_mul_add(const struct rsa_public_key *key, uint32_t *c,
+			 const uint32_t a, const uint32_t *b)
 {
 	uint64_t A = mula32(a, b[0], c[0]);
 	uint32_t d0 = (uint32_t)A * key->n0inv;
@@ -73,9 +71,8 @@ static void mont_mul_add(const struct rsa_public_key *key,
 /**
  * Montgomery c[] += 0 * b[] / R % mod
  */
-static void mont_mul_add_0(const struct rsa_public_key *key,
-			 uint32_t *c,
-			 const uint32_t *b)
+static void mont_mul_add_0(const struct rsa_public_key *key, uint32_t *c,
+			   const uint32_t *b)
 {
 	uint32_t d0 = c[0] * key->n0inv;
 	uint64_t B = mula32(d0, key->n[0], c[0]);
@@ -90,8 +87,7 @@ static void mont_mul_add_0(const struct rsa_public_key *key,
 }
 
 /* Montgomery c[] = a[] * 1 / R % key. */
-static void mont_mul_1(const struct rsa_public_key *key,
-		       uint32_t *c,
+static void mont_mul_1(const struct rsa_public_key *key, uint32_t *c,
 		       const uint32_t *a)
 {
 	int i;
@@ -108,10 +104,8 @@ static void mont_mul_1(const struct rsa_public_key *key,
 /**
  * Montgomery c[] = a[] * b[] / R % mod
  */
-static void mont_mul(const struct rsa_public_key *key,
-		     uint32_t *c,
-		     const uint32_t *a,
-		     const uint32_t *b)
+static void mont_mul(const struct rsa_public_key *key, uint32_t *c,
+		     const uint32_t *a, const uint32_t *b)
 {
 	uint32_t i;
 	for (i = 0; i < RSANUMWORDS; ++i)
@@ -136,21 +130,20 @@ static void mod_pow(const struct rsa_public_key *key, uint8_t *inout,
 	uint32_t *a = workbuf32;
 	uint32_t *a_r = a + RSANUMWORDS;
 	uint32_t *aa_r = a_r + RSANUMWORDS;
-	uint32_t *aaa = aa_r;  /* Re-use location. */
+	uint32_t *aaa = aa_r; /* Re-use location. */
 	int i;
 
 	/* Convert from big endian byte array to little endian word array. */
 	for (i = 0; i < RSANUMWORDS; ++i) {
-		uint32_t tmp =
-			(inout[((RSANUMWORDS - 1 - i) * 4) + 0] << 24) |
-			(inout[((RSANUMWORDS - 1 - i) * 4) + 1] << 16) |
-			(inout[((RSANUMWORDS - 1 - i) * 4) + 2] << 8) |
-			(inout[((RSANUMWORDS - 1 - i) * 4) + 3] << 0);
+		uint32_t tmp = (inout[((RSANUMWORDS - 1 - i) * 4) + 0] << 24) |
+			       (inout[((RSANUMWORDS - 1 - i) * 4) + 1] << 16) |
+			       (inout[((RSANUMWORDS - 1 - i) * 4) + 2] << 8) |
+			       (inout[((RSANUMWORDS - 1 - i) * 4) + 3] << 0);
 		a[i] = tmp;
 	}
 
 	/* TODO(drinkcat): This operation could be precomputed to save time. */
-	mont_mul(key, a_r, a, key->rr);  /* a_r = a * RR / R mod M */
+	mont_mul(key, a_r, a, key->rr); /* a_r = a * RR / R mod M */
 #ifdef CONFIG_RSA_EXPONENT_3
 	mont_mul(key, aa_r, a_r, a_r);
 	mont_mul(key, a, aa_r, a_r);
@@ -159,9 +152,10 @@ static void mod_pow(const struct rsa_public_key *key, uint8_t *inout,
 	/* Exponent 65537 */
 	for (i = 0; i < 16; i += 2) {
 		mont_mul(key, aa_r, a_r, a_r); /* aa_r = a_r * a_r / R mod M */
-		mont_mul(key, a_r, aa_r, aa_r);/* a_r = aa_r * aa_r / R mod M */
+		mont_mul(key, a_r, aa_r, aa_r); /* a_r = aa_r * aa_r / R mod M
+						 */
 	}
-	mont_mul(key, aaa, a_r, a);  /* aaa = a_r * a / R mod M */
+	mont_mul(key, aaa, a_r, a); /* aaa = a_r * a / R mod M */
 #endif
 
 	/* Make sure aaa < mod; aaa is at most 1x mod too large. */
@@ -173,8 +167,8 @@ static void mod_pow(const struct rsa_public_key *key, uint8_t *inout,
 		uint32_t tmp = aaa[i];
 		*inout++ = (uint8_t)(tmp >> 24);
 		*inout++ = (uint8_t)(tmp >> 16);
-		*inout++ = (uint8_t)(tmp >>  8);
-		*inout++ = (uint8_t)(tmp >>  0);
+		*inout++ = (uint8_t)(tmp >> 8);
+		*inout++ = (uint8_t)(tmp >> 0);
 	}
 }
 
@@ -192,11 +186,9 @@ static void mod_pow(const struct rsa_public_key *key, uint8_t *inout,
  *
  * PS: octet string consisting of {Length(RSA Key) - Length(T) - 3} 0xFF
  */
-static const uint8_t sha256_tail[] = {
-	0x00, 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60,
-	0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01,
-	0x05, 0x00, 0x04, 0x20
-};
+static const uint8_t sha256_tail[] = { 0x00, 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09,
+				       0x60, 0x86, 0x48, 0x01, 0x65, 0x03, 0x04,
+				       0x02, 0x01, 0x05, 0x00, 0x04, 0x20 };
 
 #define PKCS_PAD_SIZE (RSANUMBYTES - SHA256_DIGEST_SIZE)
 
@@ -255,5 +247,5 @@ int rsa_verify(const struct rsa_public_key *key, const uint8_t *signature,
 	if (memcmp(buf + PKCS_PAD_SIZE, sha, SHA256_DIGEST_SIZE) != 0)
 		return 0;
 
-	return 1;  /* All checked out OK. */
+	return 1; /* All checked out OK. */
 }
diff --git a/common/rtc.c b/common/rtc.c
index 8a2fbc7139..82bdae0aec 100644
--- a/common/rtc.c
+++ b/common/rtc.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,8 +8,8 @@
 
 #include "rtc.h"
 
-static uint16_t days_since_year_start[12] = {
-0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334};
+static uint16_t days_since_year_start[12] = { 0,   31,	59,  90,  120, 151,
+					      181, 212, 243, 273, 304, 334 };
 
 /* Conversion between calendar date and seconds eclapsed since 1970-01-01 */
 uint32_t date_to_sec(struct calendar_date time)
@@ -24,8 +24,8 @@ uint32_t date_to_sec(struct calendar_date time)
 	}
 
 	sec += (days_since_year_start[time.month - 1] +
-		(IS_LEAP_YEAR(time.year) && time.month > 2) +
-		(time.day - 1)) * SECS_PER_DAY;
+		(IS_LEAP_YEAR(time.year) && time.month > 2) + (time.day - 1)) *
+	       SECS_PER_DAY;
 
 	/* add the accumulated time in seconds from 1970 to 2000 */
 	return sec + SECS_TILL_YEAR_2K;
@@ -53,9 +53,15 @@ struct calendar_date sec_to_date(uint32_t sec)
 		day_tmp += IS_LEAP_YEAR(time.year) ? 366 : 365;
 	}
 	for (i = 1; i < 12; i++) {
-		if (days_since_year_start[i] +
-		    (IS_LEAP_YEAR(time.year) && (i >= 2)) >= day_tmp)
+		int month_offset = days_since_year_start[i];
+
+		if (IS_LEAP_YEAR(time.year) && (i >= 2)) {
+			month_offset++;
+		}
+
+		if (month_offset >= day_tmp) {
 			break;
+		}
 	}
 	time.month = i;
 
diff --git a/common/rwsig.c b/common/rwsig.c
index e23ca23293..e3689abc85 100644
--- a/common/rwsig.c
+++ b/common/rwsig.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,6 +8,7 @@
  */
 
 #include "console.h"
+#include "cros_version.h"
 #include "ec_commands.h"
 #include "flash.h"
 #include "host_command.h"
@@ -22,38 +23,36 @@
 #include "util.h"
 #include "vb21_struct.h"
 #include "vboot.h"
-#include "version.h"
 
 /* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 #if !defined(CONFIG_MAPPED_STORAGE)
 #error rwsig implementation assumes mem-mapped storage.
 #endif
 
 /* RW firmware reset vector */
-static uint32_t * const rw_rst =
+static uint32_t *const rw_rst =
 	(uint32_t *)(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RW_MEM_OFF + 4);
 
-
 void rwsig_jump_now(void)
 {
 	/* Protect all flash before jumping to RW. */
 
 	/* This may do nothing if WP is not enabled, RO is not protected. */
-	flash_set_protect(EC_FLASH_PROTECT_ALL_NOW, -1);
+	crec_flash_set_protect(EC_FLASH_PROTECT_ALL_NOW, -1);
 
 	/*
 	 * For chips that does not support EC_FLASH_PROTECT_ALL_NOW, use
 	 * EC_FLASH_PROTECT_ALL_AT_BOOT.
 	 */
 	if (system_is_locked() &&
-	    !(flash_get_protect() & EC_FLASH_PROTECT_ALL_NOW)) {
-		flash_set_protect(EC_FLASH_PROTECT_ALL_AT_BOOT, -1);
+	    !(crec_flash_get_protect() & EC_FLASH_PROTECT_ALL_NOW)) {
+		crec_flash_set_protect(EC_FLASH_PROTECT_ALL_AT_BOOT, -1);
 
-		if (!(flash_get_protect() & EC_FLASH_PROTECT_ALL_NOW) &&
-		    flash_get_protect() & EC_FLASH_PROTECT_ALL_AT_BOOT) {
+		if (!(crec_flash_get_protect() & EC_FLASH_PROTECT_ALL_NOW) &&
+		    crec_flash_get_protect() & EC_FLASH_PROTECT_ALL_AT_BOOT) {
 			/*
 			 * If flash protection is still not enabled (some chips
 			 * may be able to enable it immediately), reboot.
@@ -66,7 +65,7 @@ void rwsig_jump_now(void)
 
 	/* When system is locked, only boot to RW if all flash is protected. */
 	if (!system_is_locked() ||
-	    flash_get_protect() & EC_FLASH_PROTECT_ALL_NOW)
+	    crec_flash_get_protect() & EC_FLASH_PROTECT_ALL_NOW)
 		system_run_image_copy(EC_IMAGE_RW);
 }
 
@@ -74,8 +73,8 @@ void rwsig_jump_now(void)
  * Check that memory between rwdata[start] and rwdata[len-1] is filled
  * with ones. data, start and len must be aligned on 4-byte boundary.
  */
-static int check_padding(const uint8_t *data,
-			 unsigned int start, unsigned int len)
+static int check_padding(const uint8_t *data, unsigned int start,
+			 unsigned int len)
 {
 	unsigned int i;
 	const uint32_t *data32 = (const uint32_t *)data;
@@ -83,7 +82,7 @@ static int check_padding(const uint8_t *data,
 	if ((start % 4) != 0 || (len % 4) != 0)
 		return 0;
 
-	for (i = start/4; i < len/4; i++) {
+	for (i = start / 4; i < len / 4; i++) {
 		if (data32[i] != 0xffffffff)
 			return 0;
 	}
@@ -99,8 +98,8 @@ int rwsig_check_signature(void)
 	const uint8_t *sig;
 	uint8_t *hash;
 	uint32_t *rsa_workbuf = NULL;
-	const uint8_t *rwdata = (uint8_t *)CONFIG_PROGRAM_MEMORY_BASE
-					+ CONFIG_RW_MEM_OFF;
+	const uint8_t *rwdata = (uint8_t *)CONFIG_MAPPED_STORAGE_BASE +
+				CONFIG_EC_WRITABLE_STORAGE_OFF;
 	int good = 0;
 
 	unsigned int rwlen;
@@ -125,8 +124,8 @@ int rwsig_check_signature(void)
 
 	if (rw_rollback_version < 0 || min_rollback_version < 0 ||
 	    rw_rollback_version < min_rollback_version) {
-		CPRINTS("Rollback error (%d < %d)",
-			rw_rollback_version, min_rollback_version);
+		CPRINTS("Rollback error (%d < %d)", rw_rollback_version,
+			min_rollback_version);
 		goto out;
 	}
 #endif
@@ -144,7 +143,7 @@ int rwsig_check_signature(void)
 	rwlen = CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE;
 #elif defined(CONFIG_RWSIG_TYPE_RWSIG)
 	vb21_key = vb21_get_packed_key();
-	vb21_sig = (const struct vb21_signature *)CONFIG_RW_SIG_ADDR;
+	vb21_sig = (const struct vb21_signature *)CONFIG_RWSIG_READ_ADDR;
 
 	if (vb21_key->c.magic != VB21_MAGIC_PACKED_KEY ||
 	    vb21_key->key_size != sizeof(struct rsa_public_key)) {
@@ -152,8 +151,8 @@ int rwsig_check_signature(void)
 		goto out;
 	}
 
-	key = (const struct rsa_public_key *)
-		((const uint8_t *)vb21_key + vb21_key->key_offset);
+	key = (const struct rsa_public_key *)((const uint8_t *)vb21_key +
+					      vb21_key->key_offset);
 
 	/*
 	 * TODO(crbug.com/690773): We could verify other parameters such
@@ -179,7 +178,7 @@ int rwsig_check_signature(void)
 	 * Check that unverified RW region is actually filled with ones.
 	 */
 	good = check_padding(rwdata, rwlen,
-			CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE);
+			     CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE);
 	if (!good) {
 		CPRINTS("Invalid padding.");
 		goto out;
@@ -207,10 +206,10 @@ int rwsig_check_signature(void)
 	 */
 	if (rw_rollback_version != min_rollback_version
 #ifdef CONFIG_FLASH_PROTECT_RW
-		&& ((!system_is_locked() ||
-				flash_get_protect() & EC_FLASH_PROTECT_RW_NOW))
+	    && ((!system_is_locked() ||
+		 crec_flash_get_protect() & EC_FLASH_PROTECT_RW_NOW))
 #endif
-			) {
+	) {
 		/*
 		 * This will fail if the rollback block is protected (RW image
 		 * will unprotect that block later on).
@@ -218,8 +217,7 @@ int rwsig_check_signature(void)
 		int ret = rollback_update_version(rw_rollback_version);
 
 		if (ret == 0) {
-			CPRINTS("Rollback updated to %d",
-				rw_rollback_version);
+			CPRINTS("Rollback updated to %d", rw_rollback_version);
 		} else if (ret != EC_ERROR_ACCESS_DENIED) {
 			CPRINTS("Rollback update error %d", ret);
 			good = 0;
@@ -254,12 +252,12 @@ enum rwsig_status rwsig_get_status(void)
 
 void rwsig_abort(void)
 {
-	task_set_event(TASK_ID_RWSIG, TASK_EVENT_ABORT, 0);
+	task_set_event(TASK_ID_RWSIG, TASK_EVENT_ABORT);
 }
 
 void rwsig_continue(void)
 {
-	task_set_event(TASK_ID_RWSIG, TASK_EVENT_CONTINUE, 0);
+	task_set_event(TASK_ID_RWSIG, TASK_EVENT_CONTINUE);
 }
 
 void rwsig_task(void *u)
@@ -297,7 +295,7 @@ void rwsig_task(void *u)
 		task_wait_event(-1);
 }
 
-enum ec_status rwsig_cmd_action(struct host_cmd_handler_args *args)
+static enum ec_status rwsig_cmd_action(struct host_cmd_handler_args *args)
 {
 	const struct ec_params_rwsig_action *p = args->params;
 
@@ -314,12 +312,10 @@ enum ec_status rwsig_cmd_action(struct host_cmd_handler_args *args)
 	args->response_size = 0;
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_RWSIG_ACTION,
-		     rwsig_cmd_action,
-		     EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_RWSIG_ACTION, rwsig_cmd_action, EC_VER_MASK(0));
 
 #else /* !HAS_TASK_RWSIG */
-enum ec_status rwsig_cmd_check_status(struct host_cmd_handler_args *args)
+static enum ec_status rwsig_cmd_check_status(struct host_cmd_handler_args *args)
 {
 	struct ec_response_rwsig_check_status *r = args->response;
 
@@ -329,7 +325,6 @@ enum ec_status rwsig_cmd_check_status(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_RWSIG_CHECK_STATUS,
-		     rwsig_cmd_check_status,
+DECLARE_HOST_COMMAND(EC_CMD_RWSIG_CHECK_STATUS, rwsig_cmd_check_status,
 		     EC_VER_MASK(0));
 #endif
diff --git a/common/sha256.c b/common/sha256.c
deleted file mode 120000
index 8c0778c3e6..0000000000
--- a/common/sha256.c
+++ /dev/null
@@ -1 +0,0 @@
-../third_party/sha2//sha256.c
\ No newline at end of file
diff --git a/common/sha256.c b/common/sha256.c
new file mode 100644
index 0000000000..2826f6c68d
--- /dev/null
+++ b/common/sha256.c
@@ -0,0 +1,296 @@
+/* SHA-256 and SHA-512 implementation based on code by Oliver Gay
+ * <olivier.gay@a3.epfl.ch> under a BSD-style license. See below.
+ */
+
+/*
+ * FIPS 180-2 SHA-224/256/384/512 implementation
+ * Last update: 02/02/2007
+ * Issue date:  04/30/2005
+ *
+ * Copyright (C) 2005, 2007 Olivier Gay <olivier.gay@a3.epfl.ch>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the project nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "builtin/assert.h"
+#include "sha256.h"
+#include "util.h"
+
+#define SHFR(x, n) (x >> n)
+#define ROTR(x, n) ((x >> n) | (x << ((sizeof(x) << 3) - n)))
+#define ROTL(x, n) ((x << n) | (x >> ((sizeof(x) << 3) - n)))
+#define CH(x, y, z) ((x & y) ^ (~x & z))
+#define MAJ(x, y, z) ((x & y) ^ (x & z) ^ (y & z))
+
+#define SHA256_F1(x) (ROTR(x, 2) ^ ROTR(x, 13) ^ ROTR(x, 22))
+#define SHA256_F2(x) (ROTR(x, 6) ^ ROTR(x, 11) ^ ROTR(x, 25))
+#define SHA256_F3(x) (ROTR(x, 7) ^ ROTR(x, 18) ^ SHFR(x, 3))
+#define SHA256_F4(x) (ROTR(x, 17) ^ ROTR(x, 19) ^ SHFR(x, 10))
+
+#define UNPACK32(x, str)                             \
+	{                                            \
+		*((str) + 3) = (uint8_t)((x));       \
+		*((str) + 2) = (uint8_t)((x) >> 8);  \
+		*((str) + 1) = (uint8_t)((x) >> 16); \
+		*((str) + 0) = (uint8_t)((x) >> 24); \
+	}
+
+#define PACK32(str, x)                                    \
+	{                                                 \
+		*(x) = ((uint32_t) * ((str) + 3)) |       \
+		       ((uint32_t) * ((str) + 2) << 8) |  \
+		       ((uint32_t) * ((str) + 1) << 16) | \
+		       ((uint32_t) * ((str) + 0) << 24);  \
+	}
+
+/* Macros used for loops unrolling */
+
+#define SHA256_SCR(i)                                                          \
+	{                                                                      \
+		w[i] = SHA256_F4(w[i - 2]) + w[i - 7] + SHA256_F3(w[i - 15]) + \
+		       w[i - 16];                                              \
+	}
+
+#define SHA256_EXP(a, b, c, d, e, f, g, h, j)                             \
+	{                                                                 \
+		t1 = wv[h] + SHA256_F2(wv[e]) + CH(wv[e], wv[f], wv[g]) + \
+		     sha256_k[j] + w[j];                                  \
+		t2 = SHA256_F1(wv[a]) + MAJ(wv[a], wv[b], wv[c]);         \
+		wv[d] += t1;                                              \
+		wv[h] = t1 + t2;                                          \
+	}
+
+static const uint32_t sha256_h0[8] = { 0x6a09e667, 0xbb67ae85, 0x3c6ef372,
+				       0xa54ff53a, 0x510e527f, 0x9b05688c,
+				       0x1f83d9ab, 0x5be0cd19 };
+
+static const uint32_t sha256_k[64] = {
+	0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5, 0x3956c25b, 0x59f111f1,
+	0x923f82a4, 0xab1c5ed5, 0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3,
+	0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174, 0xe49b69c1, 0xefbe4786,
+	0x0fc19dc6, 0x240ca1cc, 0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da,
+	0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7, 0xc6e00bf3, 0xd5a79147,
+	0x06ca6351, 0x14292967, 0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13,
+	0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85, 0xa2bfe8a1, 0xa81a664b,
+	0xc24b8b70, 0xc76c51a3, 0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070,
+	0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5, 0x391c0cb3, 0x4ed8aa4a,
+	0x5b9cca4f, 0x682e6ff3, 0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208,
+	0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2
+};
+
+void SHA256_init(struct sha256_ctx *ctx)
+{
+	int i;
+
+	for (i = 0; i < 8; i++)
+		ctx->h[i] = sha256_h0[i];
+
+	ctx->len = 0;
+	ctx->tot_len = 0;
+}
+
+static void SHA256_transform(struct sha256_ctx *ctx, const uint8_t *message,
+			     unsigned int block_nb)
+{
+	/* Note: this function requires a considerable amount of stack */
+	uint32_t w[64];
+	uint32_t wv[8];
+	uint32_t t1, t2;
+	const unsigned char *sub_block;
+	int i, j;
+
+	for (i = 0; i < (int)block_nb; i++) {
+		sub_block = message + (i << 6);
+
+		for (j = 0; j < 16; j++)
+			PACK32(&sub_block[j << 2], &w[j]);
+
+#ifdef CONFIG_SHA256_UNROLLED
+		for (j = 16; j < 64; j += 8) {
+			SHA256_SCR(j);
+			SHA256_SCR(j + 1);
+			SHA256_SCR(j + 2);
+			SHA256_SCR(j + 3);
+			SHA256_SCR(j + 4);
+			SHA256_SCR(j + 5);
+			SHA256_SCR(j + 6);
+			SHA256_SCR(j + 7);
+		}
+#else
+		for (j = 16; j < 64; j++)
+			SHA256_SCR(j);
+#endif
+
+		for (j = 0; j < 8; j++)
+			wv[j] = ctx->h[j];
+
+#ifdef CONFIG_SHA256_UNROLLED
+		for (j = 0; j < 64; j += 8) {
+			SHA256_EXP(0, 1, 2, 3, 4, 5, 6, 7, j);
+			SHA256_EXP(7, 0, 1, 2, 3, 4, 5, 6, j + 1);
+			SHA256_EXP(6, 7, 0, 1, 2, 3, 4, 5, j + 2);
+			SHA256_EXP(5, 6, 7, 0, 1, 2, 3, 4, j + 3);
+			SHA256_EXP(4, 5, 6, 7, 0, 1, 2, 3, j + 4);
+			SHA256_EXP(3, 4, 5, 6, 7, 0, 1, 2, j + 5);
+			SHA256_EXP(2, 3, 4, 5, 6, 7, 0, 1, j + 6);
+			SHA256_EXP(1, 2, 3, 4, 5, 6, 7, 0, j + 7);
+		}
+#else
+		for (j = 0; j < 64; j++) {
+			t1 = wv[7] + SHA256_F2(wv[4]) +
+			     CH(wv[4], wv[5], wv[6]) + sha256_k[j] + w[j];
+			t2 = SHA256_F1(wv[0]) + MAJ(wv[0], wv[1], wv[2]);
+			wv[7] = wv[6];
+			wv[6] = wv[5];
+			wv[5] = wv[4];
+			wv[4] = wv[3] + t1;
+			wv[3] = wv[2];
+			wv[2] = wv[1];
+			wv[1] = wv[0];
+			wv[0] = t1 + t2;
+		}
+#endif
+
+		for (j = 0; j < 8; j++)
+			ctx->h[j] += wv[j];
+	}
+}
+
+void SHA256_update(struct sha256_ctx *ctx, const uint8_t *data, uint32_t len)
+{
+	unsigned int block_nb;
+	unsigned int new_len, rem_len, tmp_len;
+	const uint8_t *shifted_data;
+
+	tmp_len = SHA256_BLOCK_SIZE - ctx->len;
+	rem_len = len < tmp_len ? len : tmp_len;
+
+	memcpy(&ctx->block[ctx->len], data, rem_len);
+
+	if (ctx->len + len < SHA256_BLOCK_SIZE) {
+		ctx->len += len;
+		return;
+	}
+
+	new_len = len - rem_len;
+	block_nb = new_len / SHA256_BLOCK_SIZE;
+
+	shifted_data = data + rem_len;
+
+	SHA256_transform(ctx, ctx->block, 1);
+	SHA256_transform(ctx, shifted_data, block_nb);
+
+	rem_len = new_len % SHA256_BLOCK_SIZE;
+
+	memcpy(ctx->block, &shifted_data[block_nb << 6], rem_len);
+
+	ctx->len = rem_len;
+	ctx->tot_len += (block_nb + 1) << 6;
+}
+
+/*
+ * Specialized SHA256_init + SHA256_update that takes the first data block of
+ * size SHA256_BLOCK_SIZE as input.
+ */
+static void SHA256_init_1b(struct sha256_ctx *ctx, const uint8_t *data)
+{
+	int i;
+
+	for (i = 0; i < 8; i++)
+		ctx->h[i] = sha256_h0[i];
+
+	SHA256_transform(ctx, data, 1);
+
+	ctx->len = 0;
+	ctx->tot_len = SHA256_BLOCK_SIZE;
+}
+
+uint8_t *SHA256_final(struct sha256_ctx *ctx)
+{
+	unsigned int block_nb;
+	unsigned int pm_len;
+	unsigned int len_b;
+	int i;
+
+	block_nb = (1 +
+		    ((SHA256_BLOCK_SIZE - 9) < (ctx->len % SHA256_BLOCK_SIZE)));
+
+	len_b = (ctx->tot_len + ctx->len) << 3;
+	pm_len = block_nb << 6;
+
+	memset(ctx->block + ctx->len, 0, pm_len - ctx->len);
+	ctx->block[ctx->len] = 0x80;
+	UNPACK32(len_b, ctx->block + pm_len - 4);
+
+	SHA256_transform(ctx, ctx->block, block_nb);
+
+	for (i = 0; i < 8; i++)
+		UNPACK32(ctx->h[i], &ctx->buf[i << 2]);
+
+	return ctx->buf;
+}
+
+static void hmac_SHA256_step(uint8_t *output, uint8_t mask, const uint8_t *key,
+			     const int key_len, const uint8_t *data,
+			     const int data_len)
+{
+	struct sha256_ctx ctx;
+	uint8_t *key_pad = ctx.block;
+	uint8_t *tmp;
+	int i;
+
+	/* key_pad = key (zero-padded) ^ mask */
+	memset(key_pad, mask, SHA256_BLOCK_SIZE);
+	for (i = 0; i < key_len; i++)
+		key_pad[i] ^= key[i];
+
+	/* tmp = hash(key_pad || message) */
+	SHA256_init_1b(&ctx, key_pad);
+	SHA256_update(&ctx, data, data_len);
+	tmp = SHA256_final(&ctx);
+	memcpy(output, tmp, SHA256_DIGEST_SIZE);
+}
+
+void hmac_SHA256(uint8_t *output, const uint8_t *key, const int key_len,
+		 const uint8_t *message, const int message_len)
+{
+	/* This code does not support key_len > block_size. */
+	ASSERT(key_len <= SHA256_BLOCK_SIZE);
+
+	/*
+	 * i_key_pad = key (zero-padded) ^ 0x36
+	 * output = hash(i_key_pad || message)
+	 * (Use output as temporary buffer)
+	 */
+	hmac_SHA256_step(output, 0x36, key, key_len, message, message_len);
+
+	/*
+	 * o_key_pad = key (zero-padded) ^ 0x5c
+	 * output = hash(o_key_pad || output)
+	 */
+	hmac_SHA256_step(output, 0x5c, key, key_len, output,
+			 SHA256_DIGEST_SIZE);
+}
diff --git a/common/shared_mem.c b/common/shared_mem.c
index be420f60a6..c1b206f143 100644
--- a/common/shared_mem.c
+++ b/common/shared_mem.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,8 +15,14 @@
 static int buf_in_use;
 static int max_used;
 
+/* 1 MB buffer for fake shared memory implementation */
+STATIC_IF(CONFIG_FAKE_SHMEM) char fake_shmem_buf[BIT(20)];
+
 int shared_mem_size(void)
 {
+	if (IS_ENABLED(CONFIG_FAKE_SHMEM))
+		return sizeof(fake_shmem_buf);
+
 	/*
 	 * Use all the RAM we can.  The shared memory buffer is the last thing
 	 * allocated from the start of RAM, so we can use everything up to the
@@ -39,7 +45,10 @@ int shared_mem_acquire(int size, char **dest_ptr)
 	 */
 
 	buf_in_use = size;
-	*dest_ptr = __shared_mem_buf;
+	if (IS_ENABLED(CONFIG_FAKE_SHMEM))
+		*dest_ptr = fake_shmem_buf;
+	else
+		*dest_ptr = __shared_mem_buf;
 
 	if (max_used < size)
 		max_used = size;
@@ -49,18 +58,20 @@ int shared_mem_acquire(int size, char **dest_ptr)
 
 void shared_mem_release(void *ptr)
 {
+	if (ptr == NULL)
+		return;
+
 	buf_in_use = 0;
 }
 
 #ifdef CONFIG_CMD_SHMEM
-static int command_shmem(int argc, char **argv)
+static int command_shmem(int argc, const char **argv)
 {
 	ccprintf("Size:%6d\n", shared_mem_size());
 	ccprintf("Used:%6d\n", buf_in_use);
 	ccprintf("Max: %6d\n", max_used);
 	return EC_SUCCESS;
 }
-DECLARE_SAFE_CONSOLE_COMMAND(shmem, command_shmem,
-			     NULL,
+DECLARE_SAFE_CONSOLE_COMMAND(shmem, command_shmem, NULL,
 			     "Print shared memory stats");
 #endif
diff --git a/common/shared_mem_libc.c b/common/shared_mem_libc.c
new file mode 100644
index 0000000000..9361ba48a0
--- /dev/null
+++ b/common/shared_mem_libc.c
@@ -0,0 +1,61 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @brief Shared mem implementation that uses malloc/free from libc.
+ */
+
+#include "common.h"
+#include "console.h"
+#include "link_defs.h"
+#include "shared_mem.h"
+#include "system.h"
+#include "task.h"
+
+#include <stdlib.h>
+
+#include <malloc.h>
+
+int shared_mem_size(void)
+{
+	return system_usable_ram_end() - (uintptr_t)__shared_mem_buf;
+}
+
+int shared_mem_acquire(int size, char **dest_ptr)
+{
+	*dest_ptr = NULL;
+
+	if (in_interrupt_context())
+		return EC_ERROR_INVAL;
+
+	*dest_ptr = malloc(size);
+	if (!*dest_ptr)
+		return EC_ERROR_BUSY;
+
+	return EC_SUCCESS;
+}
+
+void shared_mem_release(void *ptr)
+{
+	if (in_interrupt_context())
+		return;
+
+	free(ptr);
+}
+
+#ifdef CONFIG_CMD_SHMEM
+static int command_shmem(int argc, const char **argv)
+{
+	struct mallinfo info = mallinfo();
+
+	ccprintf("Total:         %d\n", shared_mem_size());
+	ccprintf("Allocated:     %d\n", info.uordblks);
+	ccprintf("Free:          %d\n", info.fordblks + info.fsmblks);
+
+	return EC_SUCCESS;
+}
+DECLARE_SAFE_CONSOLE_COMMAND(shmem, command_shmem, NULL,
+			     "Print shared memory stats");
+#endif /* CONFIG_CMD_SHMEM */
diff --git a/common/shmalloc.c b/common/shmalloc.c
index b1705b52d1..de2c4f4e86 100644
--- a/common/shmalloc.c
+++ b/common/shmalloc.c
@@ -1,12 +1,10 @@
 /*
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Malloc/free memory module for Chrome EC */
-#include <stdint.h>
-
 #include "common.h"
 #include "hooks.h"
 #include "link_defs.h"
@@ -15,6 +13,8 @@
 #include "task.h"
 #include "util.h"
 
+#include <stdint.h>
+
 static struct mutex shmem_lock;
 
 #ifndef TEST_SHMALLOC
@@ -47,8 +47,8 @@ static void shared_mem_init(void)
 	free_buf_chain = (struct shm_buffer *)__shared_mem_buf;
 	free_buf_chain->next_buffer = NULL;
 	free_buf_chain->prev_buffer = NULL;
-	free_buf_chain->buffer_size = system_usable_ram_end() -
-		(uintptr_t)__shared_mem_buf;
+	free_buf_chain->buffer_size =
+		system_usable_ram_end() - (uintptr_t)__shared_mem_buf;
 }
 DECLARE_HOOK(HOOK_INIT, shared_mem_init, HOOK_PRIO_FIRST);
 
@@ -73,8 +73,7 @@ static void do_release(struct shm_buffer *ptr)
 		 * Saninty check: verify that the buffer is in the allocated
 		 * buffers chain.
 		 */
-		for (pfb = allocced_buf_chain->next_buffer;
-		     pfb;
+		for (pfb = allocced_buf_chain->next_buffer; pfb;
 		     pfb = pfb->next_buffer)
 			if (pfb == ptr)
 				break;
@@ -117,10 +116,9 @@ static void do_release(struct shm_buffer *ptr)
 		if (pfb == free_buf_chain) {
 			set_map_bit(BIT(1));
 			/* Merge the two buffers. */
-			ptr->buffer_size = free_buf_chain->buffer_size +
-				released_size;
-			ptr->next_buffer =
-				free_buf_chain->next_buffer;
+			ptr->buffer_size =
+				free_buf_chain->buffer_size + released_size;
+			ptr->next_buffer = free_buf_chain->next_buffer;
 		} else {
 			set_map_bit(BIT(2));
 			ptr->buffer_size = released_size;
@@ -163,8 +161,7 @@ static void do_release(struct shm_buffer *ptr)
 		if (top == pfb->next_buffer) {
 			/* Yes, it is. */
 			pfb->buffer_size += pfb->next_buffer->buffer_size;
-			pfb->next_buffer =
-				pfb->next_buffer->next_buffer;
+			pfb->next_buffer = pfb->next_buffer->next_buffer;
 			if (pfb->next_buffer) {
 				set_map_bit(BIT(5));
 				pfb->next_buffer->prev_buffer = pfb;
@@ -179,8 +176,8 @@ static void do_release(struct shm_buffer *ptr)
 	if (top == pfb->next_buffer) {
 		/* The new buffer is adjacent with the one right above it. */
 		set_map_bit(BIT(7));
-		ptr->buffer_size = released_size +
-			pfb->next_buffer->buffer_size;
+		ptr->buffer_size =
+			released_size + pfb->next_buffer->buffer_size;
 		ptr->next_buffer = pfb->next_buffer->next_buffer;
 	} else {
 		/* Just include the new free buffer into the chain. */
@@ -345,6 +342,9 @@ void shared_mem_release(void *ptr)
 	if (in_interrupt_context())
 		return;
 
+	if (ptr == NULL)
+		return;
+
 	mutex_lock(&shmem_lock);
 	do_release((struct shm_buffer *)ptr - 1);
 	mutex_unlock(&shmem_lock);
@@ -352,7 +352,7 @@ void shared_mem_release(void *ptr)
 
 #ifdef CONFIG_CMD_SHMEM
 
-static int command_shmem(int argc, char **argv)
+static int command_shmem(int argc, const char **argv)
 {
 	size_t allocated_size;
 	size_t free_size;
@@ -373,8 +373,7 @@ static int command_shmem(int argc, char **argv)
 			max_free = buf_room;
 	}
 
-	for (buf = allocced_buf_chain; buf;
-	     buf = buf->next_buffer)
+	for (buf = allocced_buf_chain; buf; buf = buf->next_buffer)
 		allocated_size += buf->buffer_size;
 
 	mutex_unlock(&shmem_lock);
@@ -386,8 +385,7 @@ static int command_shmem(int argc, char **argv)
 	ccprintf("Max allocated: %6d\n", max_allocated_size);
 	return EC_SUCCESS;
 }
-DECLARE_SAFE_CONSOLE_COMMAND(shmem, command_shmem,
-			     NULL,
+DECLARE_SAFE_CONSOLE_COMMAND(shmem, command_shmem, NULL,
 			     "Print shared memory stats");
 
-#endif  /* CONFIG_CMD_SHMEM  ^^^^^^^ defined */
+#endif /* CONFIG_CMD_SHMEM  ^^^^^^^ defined */
diff --git a/common/spi/CMakeLists.txt b/common/spi/CMakeLists.txt
new file mode 100644
index 0000000000..356a0ef16a
--- /dev/null
+++ b/common/spi/CMakeLists.txt
@@ -0,0 +1,5 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+add_subdirectory_ifdef(CONFIG_PLATFORM_EC_SPI_FLASH_REGS flash_reg)
diff --git a/common/spi/Kconfig b/common/spi/Kconfig
new file mode 100644
index 0000000000..e8408a01f5
--- /dev/null
+++ b/common/spi/Kconfig
@@ -0,0 +1,5 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+rsource "flash_reg/Kconfig.module"
diff --git a/common/spi/build.mk b/common/spi/build.mk
new file mode 100644
index 0000000000..ad5c728db7
--- /dev/null
+++ b/common/spi/build.mk
@@ -0,0 +1,8 @@
+# -*- makefile -*-
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+SELF_DIR := $(dir $(lastword $(MAKEFILE_LIST)))
+
+include $(SELF_DIR)flash_reg/build.mk
diff --git a/common/spi/flash_reg/CMakeLists.txt b/common/spi/flash_reg/CMakeLists.txt
new file mode 100644
index 0000000000..55708ac57e
--- /dev/null
+++ b/common/spi/flash_reg/CMakeLists.txt
@@ -0,0 +1,75 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.20.0)
+
+# Create the library
+if(BOARD STREQUAL unit_testing)
+  find_package(Zephyr COMPONENTS unittest REQUIRED HINTS $ENV{ZEPHYR_BASE})
+  add_library(spi_flash_reg)
+else()
+  zephyr_library_named(spi_flash_reg)
+  target_link_libraries(spi_flash_reg PRIVATE cros_ec_interface)
+  # When LTO is enabled, enable only for the "app" library, which compiles
+  # and links all Chromium OS sources.
+  # TODO: Enable LTO for all sources when Zephyr supports it.
+  # See https://github.com/zephyrproject-rtos/zephyr/issues/2112
+  if (DEFINED CONFIG_LTO)
+    # The Zephyr toolchain generates linker errors if both CONFIG_LTO and
+    # CONFIG_FPU are used. See b/184302085.
+    if(("${ZEPHYR_TOOLCHAIN_VARIANT}" STREQUAL "zephyr") AND
+     (DEFINED CONFIG_FPU))
+      message(STATUS "Zephyr toolchain and CONFIG_FPU detected: disabling LTO")
+    else()
+      set_property(
+        TARGET
+          spi_flash_reg
+        PROPERTY
+          INTERPROCEDURAL_OPTIMIZATION True
+      )
+    endif()
+  endif()
+endif()
+
+# Add the sources
+target_sources(spi_flash_reg
+  PRIVATE
+    src/spi_flash_reg.c
+  PUBLIC
+    public/spi_flash_reg.h
+)
+
+# Include the public directory
+target_include_directories(spi_flash_reg PUBLIC public)
+
+if(BOARD STREQUAL unit_testing)
+  project(flash_reg)
+
+  # Set the sources for the test
+  target_sources(testbinary PRIVATE src/spi_flash_reg_test.c)
+
+  # Link the library being tested
+  target_link_libraries(testbinary PRIVATE spi_flash_reg)
+
+  # Add the private directory used to mock components of the EC
+  target_include_directories(testbinary PRIVATE private)
+  target_include_directories(spi_flash_reg PRIVATE private)
+
+  # Zephyr's unittest also generates a test_interface which we need in the
+  # library (not just in the test binary)
+  target_link_libraries(spi_flash_reg PRIVATE test_interface)
+  string(TOLOWER "${CMAKE_C_COMPILER_ID}" lowercase_compiler_id)
+  if("${lowercase_compiler_id}" STREQUAL "clang")
+    target_link_options(testbinary PRIVATE -fprofile-instr-generate)
+  endif()
+
+  # W25Q64 has 0x400000 bytes as the first section, setting
+  # CONFIG_FLASH_SIZE_BYTES to that allows us to test every branch of
+  # spi_flash_reg.c
+  add_compile_definitions(spi_flash_reg
+    PUBLIC
+      CONFIG_SPI_FLASH_W25Q64
+      CONFIG_FLASH_SIZE_BYTES=4194304
+  )
+endif()
\ No newline at end of file
diff --git a/common/spi/flash_reg/Kconfig.module b/common/spi/flash_reg/Kconfig.module
new file mode 100644
index 0000000000..04a306c8d0
--- /dev/null
+++ b/common/spi/flash_reg/Kconfig.module
@@ -0,0 +1,12 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config PLATFORM_EC_SPI_FLASH_REGS
+	bool
+	help
+	  Enables flash registers for SPI flash (both internal and external).
+	  When enabled, two new functions will become available: (1) a function
+	  to compute the block write protection range from a set of status
+	  registers, and (2) the inverse function to set the status registers
+	  based on the desired protection offset/length.
diff --git a/common/spi/flash_reg/build.mk b/common/spi/flash_reg/build.mk
new file mode 100644
index 0000000000..5d6c9f10bf
--- /dev/null
+++ b/common/spi/flash_reg/build.mk
@@ -0,0 +1,11 @@
+# -*- makefile -*-
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+SELF_DIR := $(dir $(lastword $(MAKEFILE_LIST)))
+REL_PATH := $(shell realpath --relative-to $(_common_dir) $(SELF_DIR))
+
+includes+=$(REL_PATH)public
+common-$(CONFIG_SPI_FLASH)+=$(REL_PATH)/src/spi_flash_reg.o
+common-$(CONFIG_SPI_FLASH_REGS)+=$(REL_PATH)/src/spi_flash_reg.o
diff --git a/common/spi/flash_reg/private/common.h b/common/spi/flash_reg/private/common.h
new file mode 100644
index 0000000000..9737e2f889
--- /dev/null
+++ b/common/spi/flash_reg/private/common.h
@@ -0,0 +1,16 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef ZEPHYR_TEST_SPI_FLASH_REG_INCLUDE_COMMON_H_
+#define ZEPHYR_TEST_SPI_FLASH_REG_INCLUDE_COMMON_H_
+
+#include <stdint.h>
+
+enum ec_error_list {
+	EC_SUCCESS,
+	EC_ERROR_INVAL,
+};
+
+#endif /* ZEPHYR_TEST_SPI_FLASH_REG_INCLUDE_COMMON_H_ */
diff --git a/common/spi/flash_reg/private/util.h b/common/spi/flash_reg/private/util.h
new file mode 100644
index 0000000000..119d3f10cc
--- /dev/null
+++ b/common/spi/flash_reg/private/util.h
@@ -0,0 +1,12 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef ZEPHYR_TEST_SPI_FLASH_REG_INCLUDE_UTIL_H_
+#define ZEPHYR_TEST_SPI_FLASH_REG_INCLUDE_UTIL_H_
+
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/util_macro.h>
+
+#endif /* ZEPHYR_TEST_SPI_FLASH_REG_INCLUDE_UTIL_H_ */
diff --git a/common/spi/flash_reg/prj.conf b/common/spi/flash_reg/prj.conf
new file mode 100644
index 0000000000..6ec8f4d2a9
--- /dev/null
+++ b/common/spi/flash_reg/prj.conf
@@ -0,0 +1,6 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_ZTEST=y
+CONFIG_ZTEST_NEW_API=y
diff --git a/common/spi/flash_reg/public/spi_flash_reg.h b/common/spi/flash_reg/public/spi_flash_reg.h
new file mode 100644
index 0000000000..0d70d6982d
--- /dev/null
+++ b/common/spi/flash_reg/public/spi_flash_reg.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright 2015 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * SPI flash protection register translation functions for Chrome OS EC.
+ */
+
+#ifndef __CROS_EC_SPI_FLASH_REG_H
+#define __CROS_EC_SPI_FLASH_REG_H
+
+#include "common.h"
+
+/*
+ * Common register bits for SPI flash. All registers / bits may not be valid
+ * for all parts.
+ */
+#define SPI_FLASH_SR2_SUS BIT(7)
+#define SPI_FLASH_SR2_CMP BIT(6)
+#define SPI_FLASH_SR2_LB3 BIT(5)
+#define SPI_FLASH_SR2_LB2 BIT(4)
+#define SPI_FLASH_SR2_LB1 BIT(3)
+#define SPI_FLASH_SR2_QE BIT(1)
+#define SPI_FLASH_SR2_SRP1 BIT(0)
+#define SPI_FLASH_SR1_SRP0 BIT(7)
+#define SPI_FLASH_SR1_SEC BIT(6)
+#define SPI_FLASH_SR1_TB BIT(5)
+#define SPI_FLASH_SR1_BP2 BIT(4)
+#define SPI_FLASH_SR1_BP1 BIT(3)
+#define SPI_FLASH_SR1_BP0 BIT(2)
+#define SPI_FLASH_SR1_WEL BIT(1)
+#define SPI_FLASH_SR1_BUSY BIT(0)
+
+/* SR2 register existence based upon chip */
+#ifdef CONFIG_SPI_FLASH_W25X40
+#undef CONFIG_SPI_FLASH_HAS_SR2
+#elif defined(CONFIG_SPI_FLASH_W25Q64) || defined(CONFIG_SPI_FLASH_GD25Q41B)
+#define CONFIG_SPI_FLASH_HAS_SR2
+#endif
+
+/* W25Q128 16 Mbyte SPI flash for testing */
+#ifdef CONFIG_SPI_FLASH_W25Q128
+#define CONFIG_SPI_FLASH_HAS_SR2
+#endif
+
+/**
+ * Computes block write protection range from registers
+ * Returns start == len == 0 for no protection
+ *
+ * @param sr1 Status register 1
+ * @param sr2 Status register 2
+ * @param start Output pointer for protection start offset
+ * @param len Output pointer for protection length
+ *
+ * @return EC_SUCCESS, or non-zero if any error.
+ */
+int spi_flash_reg_to_protect(uint8_t sr1, uint8_t sr2, unsigned int *start,
+			     unsigned int *len);
+
+/**
+ * Computes block write protection registers from range
+ *
+ * @param start Desired protection start offset
+ * @param len Desired protection length
+ * @param sr1 Output pointer for status register 1
+ * @param sr2 Output pointer for status register 2
+ *
+ * @return EC_SUCCESS, or non-zero if any error.
+ */
+int spi_flash_protect_to_reg(unsigned int start, unsigned int len, uint8_t *sr1,
+			     uint8_t *sr2);
+
+#endif /* __CROS_EC_SPI_FLASH_REG_H */
diff --git a/common/spi_flash_reg.c b/common/spi/flash_reg/src/spi_flash_reg.c
similarity index 83%
rename from common/spi_flash_reg.c
rename to common/spi/flash_reg/src/spi_flash_reg.c
index 3cee0f3bd4..fa71ab5eb6 100644
--- a/common/spi_flash_reg.c
+++ b/common/spi/flash_reg/src/spi_flash_reg.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -21,7 +21,7 @@ struct protect_range {
 	enum bit_state cmp;
 	enum bit_state sec;
 	enum bit_state tb;
-	enum bit_state bp[3];    /* Ordered {BP2, BP1, BP0} */
+	enum bit_state bp[3]; /* Ordered {BP2, BP1, BP0} */
 	uint32_t protect_start;
 	uint32_t protect_len;
 };
@@ -39,7 +39,7 @@ struct protect_range {
  */
 #if defined(CONFIG_SPI_FLASH_W25X40) || defined(CONFIG_SPI_FLASH_GD25Q41B)
 static const struct protect_range spi_flash_protect_ranges[] = {
-	{ IGN, IGN, IGN, { 0, 0, 0 }, 0, 0 },     /* No protection */
+	{ IGN, IGN, IGN, { 0, 0, 0 }, 0, 0 }, /* No protection */
 	{ IGN, IGN, 1, { 0, 1, 1 }, 0, 0x40000 }, /* Lower 1/2 */
 	{ IGN, IGN, 1, { 0, 1, 0 }, 0, 0x20000 }, /* Lower 1/4 */
 };
@@ -49,17 +49,17 @@ static const struct protect_range spi_flash_protect_ranges[] = {
 /* For GD25LQ40, BP3 and BP4 have same meaning as TB and SEC */
 static const struct protect_range spi_flash_protect_ranges[] = {
 	/* CMP = 0 */
-	{ 0, IGN, IGN, { 0, 0, 0 }, 0, 0 },         /* No protection */
-	{ 0, 0, 1, { 0, 1, 0 }, 0, 0x20000 },       /* Lower 1/4 */
-	{ 0, 0, 1, { 0, 1, 1 }, 0, 0x40000 },       /* Lower 1/2 */
+	{ 0, IGN, IGN, { 0, 0, 0 }, 0, 0 }, /* No protection */
+	{ 0, 0, 1, { 0, 1, 0 }, 0, 0x20000 }, /* Lower 1/4 */
+	{ 0, 0, 1, { 0, 1, 1 }, 0, 0x40000 }, /* Lower 1/2 */
 	/* CMP = 1 */
-	{ 1, 0, 0, { 0, 1, 1 }, 0, 0x40000 },       /* Lower 1/2 */
-	{ 1, 0, IGN, { 1, IGN, IGN }, 0, 0 },       /* None (W25Q40EW only) */
+	{ 1, 0, 0, { 0, 1, 1 }, 0, 0x40000 }, /* Lower 1/2 */
+	{ 1, 0, IGN, { 1, IGN, IGN }, 0, 0 }, /* None (W25Q40EW only) */
 };
 
 #elif defined(CONFIG_SPI_FLASH_W25Q64)
 static const struct protect_range spi_flash_protect_ranges[] = {
-	{ 0, IGN, IGN, { 0, 0, 0 }, 0, 0 },    /* No protection */
+	{ 0, IGN, IGN, { 0, 0, 0 }, 0, 0 }, /* No protection */
 	{ 0, 0, 1, { 1, 1, 0 }, 0, 0x400000 }, /* Lower 1/2 */
 	{ 0, 0, 1, { 1, 0, 1 }, 0, 0x200000 }, /* Lower 1/4 */
 };
@@ -67,7 +67,7 @@ static const struct protect_range spi_flash_protect_ranges[] = {
 #elif defined(CONFIG_SPI_FLASH_W25Q80)
 static const struct protect_range spi_flash_protect_ranges[] = {
 	/* CMP = 0 */
-	{ 0, IGN, IGN, { 0, 0, 0 }, 0, 0 },   /* No protection */
+	{ 0, IGN, IGN, { 0, 0, 0 }, 0, 0 }, /* No protection */
 	{ 0, 0, 1, { 0, 1, 0 }, 0, 0x20000 }, /* Lower 1/8 */
 	{ 0, 0, 1, { 0, 1, 1 }, 0, 0x40000 }, /* Lower 1/4 */
 	{ 0, 0, 1, { 1, 0, 0 }, 0, 0x80000 }, /* Lower 1/2 */
@@ -75,7 +75,7 @@ static const struct protect_range spi_flash_protect_ranges[] = {
 #elif defined(CONFIG_SPI_FLASH_W25Q128)
 static const struct protect_range spi_flash_protect_ranges[] = {
 	/* CMP = 0 */
-	{ 0, IGN, IGN, { 0, 0, 0 }, 0, 0 },   /* No protection */
+	{ 0, IGN, IGN, { 0, 0, 0 }, 0, 0 }, /* No protection */
 	{ 0, 0, 1, { 1, 0, 0 }, 0, 0x20000 }, /* Lower 1/8 */
 	{ 0, 0, 1, { 1, 0, 1 }, 0, 0x40000 }, /* Lower 1/4 */
 	{ 0, 0, 1, { 1, 1, 0 }, 0, 0x80000 }, /* Lower 1/2 */
@@ -107,8 +107,9 @@ int spi_flash_reg_to_protect(uint8_t sr1, uint8_t sr2, unsigned int *start,
 	cmp = (sr2 & SPI_FLASH_SR2_CMP) ? 1 : 0;
 	sec = (sr1 & SPI_FLASH_SR1_SEC) ? 1 : 0;
 	tb = (sr1 & SPI_FLASH_SR1_TB) ? 1 : 0;
-	bp = (sr1 & (SPI_FLASH_SR1_BP2 | SPI_FLASH_SR1_BP1 | SPI_FLASH_SR1_BP0))
-		 >> 2;
+	bp = (sr1 &
+	      (SPI_FLASH_SR1_BP2 | SPI_FLASH_SR1_BP1 | SPI_FLASH_SR1_BP0)) >>
+	     2;
 
 	/* Bad pointers or invalid data */
 	if (!start || !len || sr1 == 0xff || sr2 == 0xff)
@@ -163,7 +164,7 @@ int spi_flash_protect_to_reg(unsigned int start, unsigned int len, uint8_t *sr1,
 		return EC_ERROR_INVAL;
 
 	/* Invalid data */
-	if ((start && !len) || start + len > CONFIG_FLASH_SIZE)
+	if ((start && !len) || start + len > CONFIG_FLASH_SIZE_BYTES)
 		return EC_ERROR_INVAL;
 
 	for (i = 0; i < ARRAY_SIZE(spi_flash_protect_ranges); ++i) {
@@ -174,12 +175,10 @@ int spi_flash_protect_to_reg(unsigned int start, unsigned int len, uint8_t *sr1,
 			sec = GET_BIT(range->sec);
 			tb = GET_BIT(range->tb);
 			bp = GET_BIT(range->bp[0]) << 2 |
-			     GET_BIT(range->bp[1]) << 1 |
-			     GET_BIT(range->bp[2]);
+			     GET_BIT(range->bp[1]) << 1 | GET_BIT(range->bp[2]);
 
 			*sr1 = (sec ? SPI_FLASH_SR1_SEC : 0) |
-			       (tb ? SPI_FLASH_SR1_TB : 0) |
-			       (bp << 2);
+			       (tb ? SPI_FLASH_SR1_TB : 0) | (bp << 2);
 			*sr2 = (cmp ? SPI_FLASH_SR2_CMP : 0);
 			return EC_SUCCESS;
 		}
diff --git a/common/spi/flash_reg/src/spi_flash_reg_test.c b/common/spi/flash_reg/src/spi_flash_reg_test.c
new file mode 100644
index 0000000000..b9a45476b1
--- /dev/null
+++ b/common/spi/flash_reg/src/spi_flash_reg_test.c
@@ -0,0 +1,98 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "spi_flash_reg.h"
+
+#include <zephyr/ztest.h>
+
+ZTEST_SUITE(flash_reg_to_protect, NULL, NULL, NULL, NULL, NULL);
+
+ZTEST(flash_reg_to_protect, test_invalid_args)
+{
+	unsigned int start = 0;
+	unsigned int len = 0;
+
+	zassert_equal(EC_ERROR_INVAL,
+		      spi_flash_reg_to_protect(0, 0, NULL, &len));
+	zassert_equal(EC_ERROR_INVAL,
+		      spi_flash_reg_to_protect(0, 0, &start, NULL));
+	zassert_equal(EC_ERROR_INVAL,
+		      spi_flash_reg_to_protect(0xff, 0, &start, &len));
+	zassert_equal(EC_ERROR_INVAL,
+		      spi_flash_reg_to_protect(0, 0xff, &start, &len));
+}
+
+ZTEST(flash_reg_to_protect, test_no_matching_range)
+{
+	unsigned int start = 0;
+	unsigned int len = 0;
+
+	/* Bad SR1 */
+	zassert_equal(EC_ERROR_INVAL,
+		      spi_flash_reg_to_protect(SPI_FLASH_SR1_BP0, 0, &start,
+					       &len));
+	zassert_equal(EC_ERROR_INVAL,
+		      spi_flash_reg_to_protect(SPI_FLASH_SR1_BP1, 0, &start,
+					       &len));
+	zassert_equal(EC_ERROR_INVAL,
+		      spi_flash_reg_to_protect(SPI_FLASH_SR1_BP2, 0, &start,
+					       &len));
+
+	/* BAD SR2 */
+	zassert_equal(EC_ERROR_INVAL, spi_flash_reg_to_protect(
+					      SPI_FLASH_SR1_BP0,
+					      SPI_FLASH_SR2_CMP, &start, &len));
+	zassert_equal(EC_ERROR_INVAL,
+		      spi_flash_reg_to_protect(SPI_FLASH_SR1_SEC |
+						       SPI_FLASH_SR1_BP0,
+					       0, &start, &len));
+}
+
+ZTEST(flash_reg_to_protect, test_matching_range)
+{
+	unsigned int start = 0;
+	unsigned int len = 0;
+
+	zassert_equal(EC_SUCCESS, spi_flash_reg_to_protect(0, 0, &start, &len));
+	zassert_equal(0, start);
+	zassert_equal(0, len);
+}
+
+ZTEST_SUITE(flash_protect_to_reg, NULL, NULL, NULL, NULL, NULL);
+
+ZTEST(flash_protect_to_reg, test_invalid_args)
+{
+	uint8_t sr1;
+	uint8_t sr2;
+
+	zassert_equal(EC_ERROR_INVAL,
+		      spi_flash_protect_to_reg(0, 0, NULL, &sr2));
+	zassert_equal(EC_ERROR_INVAL,
+		      spi_flash_protect_to_reg(0, 0, &sr1, NULL));
+	zassert_equal(EC_ERROR_INVAL,
+		      spi_flash_protect_to_reg(128, 0, &sr1, &sr2));
+	zassert_equal(EC_ERROR_INVAL,
+		      spi_flash_protect_to_reg(128, CONFIG_FLASH_SIZE_BYTES,
+					       &sr1, &sr2));
+	zassert_equal(EC_ERROR_INVAL,
+		      spi_flash_protect_to_reg(128, 128, &sr1, &sr2));
+}
+
+ZTEST(flash_protect_to_reg, test_matching_range)
+{
+	uint8_t sr1;
+	uint8_t sr2;
+
+	zassert_equal(EC_SUCCESS,
+		      spi_flash_protect_to_reg(0, 0x400000, &sr1, &sr2));
+	zassert_equal(0x38, sr1, "Expected 0x38, but got 0x%02x", sr1);
+	zassert_equal(0x00, sr2, "Expected 0x00, but got 0x%02x", sr2);
+
+	zassert_equal(EC_SUCCESS,
+		      spi_flash_protect_to_reg(0, 0x200000, &sr1, &sr2));
+	zassert_equal(0x34, sr1, "Expected 0x38, but got 0x%02x", sr1);
+	zassert_equal(0x00, sr2, "Expected 0x00, but got 0x%02x", sr2);
+}
diff --git a/common/spi/flash_reg/testcase.yaml b/common/spi/flash_reg/testcase.yaml
new file mode 100644
index 0000000000..95a71b1aae
--- /dev/null
+++ b/common/spi/flash_reg/testcase.yaml
@@ -0,0 +1,8 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+tests:
+  spi.flash_reg:
+    tags: spi
+    type: unit
diff --git a/common/spi_commands.c b/common/spi_commands.c
index 1a70a5be82..9810039ede 100644
--- a/common/spi_commands.c
+++ b/common/spi_commands.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,11 +8,12 @@
 
 #include "common.h"
 #include "console.h"
+#include "printf.h"
 #include "spi.h"
 #include "timer.h"
 #include "util.h"
 
-static int command_spixfer(int argc, char **argv)
+static int command_spixfer(int argc, const char **argv)
 {
 	int dev_id;
 	uint8_t offset;
@@ -45,8 +46,13 @@ static int command_spixfer(int argc, char **argv)
 
 		rv = spi_transaction(&spi_devices[dev_id], &cmd, 1, data, v);
 
-		if (!rv)
-			ccprintf("Data: %ph\n", HEX_BUF(data, v));
+		if (!rv) {
+			char str_buf[hex_str_buf_size(v)];
+
+			snprintf_hex_buffer(str_buf, sizeof(str_buf),
+					    HEX_BUF(data, v));
+			ccprintf("Data: %s\n", str_buf);
+		}
 
 	} else if (strcasecmp(argv[1], "w") == 0) {
 		/* 8-bit write */
@@ -68,4 +74,3 @@ static int command_spixfer(int argc, char **argv)
 DECLARE_CONSOLE_COMMAND(spixfer, command_spixfer,
 			"rlen/w id offset [value | len]",
 			"Read write spi. id is spi_devices array index");
-
diff --git a/common/spi_flash.c b/common/spi_flash.c
index 3f003052bf..1540c7bb33 100644
--- a/common/spi_flash.c
+++ b/common/spi_flash.c
@@ -1,13 +1,16 @@
 /*
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
+ * Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * SPI flash driver for Chrome EC.
  */
 
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
+#include "ec_commands.h"
+#include "flash.h"
 #include "host_command.h"
 #include "shared_mem.h"
 #include "spi.h"
@@ -16,18 +19,16 @@
 #include "timer.h"
 #include "util.h"
 #include "watchdog.h"
-#include "ec_commands.h"
-#include "flash.h"
 
 /*
  * Time to sleep when chip is busy
  */
-#define SPI_FLASH_SLEEP_USEC	100
+#define SPI_FLASH_SLEEP_USEC 100
 
 /*
  * This is the max time for 32kb flash erase
  */
-#define SPI_FLASH_TIMEOUT_USEC	(800*MSEC)
+#define SPI_FLASH_TIMEOUT_USEC (800 * MSEC)
 
 /* Internal buffer used by SPI flash driver */
 static uint8_t buf[SPI_FLASH_MAX_MESSAGE_SIZE];
@@ -109,12 +110,12 @@ uint8_t spi_flash_get_status2(void)
  */
 int spi_flash_set_status(int reg1, int reg2)
 {
-	uint8_t cmd[3] = {SPI_FLASH_WRITE_SR, reg1, reg2};
+	uint8_t cmd[3] = { SPI_FLASH_WRITE_SR, reg1, reg2 };
 	int rv = EC_SUCCESS;
 
 	/* fail if both HW pin is asserted and SRP(s) is 1 */
 	if (spi_flash_check_wp() != SPI_WP_NONE &&
-		(flash_get_protect() & EC_FLASH_PROTECT_GPIO_ASSERTED) != 0)
+	    (crec_flash_get_protect() & EC_FLASH_PROTECT_GPIO_ASSERTED) != 0)
 		return EC_ERROR_ACCESS_DENIED;
 
 	/* Enable writing to SPI flash */
@@ -122,7 +123,7 @@ int spi_flash_set_status(int reg1, int reg2)
 	if (rv)
 		return rv;
 
-	/* Second status register not present */
+		/* Second status register not present */
 #ifndef CONFIG_SPI_FLASH_HAS_SR2
 	reg2 = -1;
 #endif
@@ -153,7 +154,7 @@ int spi_flash_read(uint8_t *buf_usr, unsigned int offset, unsigned int bytes)
 {
 	int i, read_size, ret, spi_addr;
 	uint8_t cmd[4];
-	if (offset + bytes > CONFIG_FLASH_SIZE)
+	if (offset + bytes > CONFIG_FLASH_SIZE_BYTES)
 		return EC_ERROR_INVAL;
 	cmd[0] = SPI_FLASH_READ;
 	for (i = 0; i < bytes; i += read_size) {
@@ -162,14 +163,11 @@ int spi_flash_read(uint8_t *buf_usr, unsigned int offset, unsigned int bytes)
 		cmd[2] = (spi_addr >> 8) & 0xFF;
 		cmd[3] = spi_addr & 0xFF;
 		read_size = MIN((bytes - i), SPI_FLASH_MAX_READ_SIZE);
-		ret = spi_transaction(SPI_FLASH_DEVICE,
-			cmd,
-			4,
-			buf_usr + i,
-			read_size);
+		ret = spi_transaction(SPI_FLASH_DEVICE, cmd, 4, buf_usr + i,
+				      read_size);
 		if (ret != EC_SUCCESS)
 			break;
-		msleep(1);
+		msleep(CONFIG_SPI_FLASH_READ_WAIT_MS);
 	}
 	return ret;
 }
@@ -227,7 +225,7 @@ int spi_flash_erase(unsigned int offset, unsigned int bytes)
 	int rv = EC_SUCCESS;
 
 	/* Invalid input */
-	if (offset + bytes > CONFIG_FLASH_SIZE)
+	if (offset + bytes > CONFIG_FLASH_SIZE_BYTES)
 		return EC_ERROR_INVAL;
 
 	/* Not aligned to sector (4kb) */
@@ -275,20 +273,22 @@ int spi_flash_erase(unsigned int offset, unsigned int bytes)
  * @return EC_SUCCESS, or non-zero if any error.
  */
 int spi_flash_write(unsigned int offset, unsigned int bytes,
-	const uint8_t *data)
+		    const uint8_t *data)
 {
 	int rv, write_size;
 
 	/* Invalid input */
-	if (!data || offset + bytes > CONFIG_FLASH_SIZE ||
+	if (!data || offset + bytes > CONFIG_FLASH_SIZE_BYTES ||
 	    bytes > SPI_FLASH_MAX_WRITE_SIZE)
 		return EC_ERROR_INVAL;
 
 	while (bytes > 0) {
 		watchdog_reload();
 		/* Write length can not go beyond the end of the flash page */
-		write_size = MIN(bytes, SPI_FLASH_MAX_WRITE_SIZE -
-		(offset & (SPI_FLASH_MAX_WRITE_SIZE - 1)));
+		write_size =
+			MIN(bytes,
+			    SPI_FLASH_MAX_WRITE_SIZE -
+				    (offset & (SPI_FLASH_MAX_WRITE_SIZE - 1)));
 
 		/* Wait for previous operation to complete */
 		rv = spi_flash_wait();
@@ -309,8 +309,8 @@ int spi_flash_write(unsigned int offset, unsigned int bytes,
 		buf[2] = (offset) >> 8;
 		buf[3] = offset;
 
-		rv = spi_transaction(SPI_FLASH_DEVICE,
-				     buf, 4 + write_size, NULL, 0);
+		rv = spi_transaction(SPI_FLASH_DEVICE, buf, 4 + write_size,
+				     NULL, 0);
 		if (rv)
 			return rv;
 
@@ -344,7 +344,7 @@ int spi_flash_get_jedec_id(uint8_t *dest)
  */
 int spi_flash_get_mfr_dev_id(uint8_t *dest)
 {
-	uint8_t cmd[4] = {SPI_FLASH_MFR_DEV_ID, 0, 0, 0};
+	uint8_t cmd[4] = { SPI_FLASH_MFR_DEV_ID, 0, 0, 0 };
 
 	return spi_transaction(SPI_FLASH_DEVICE, cmd, sizeof(cmd), dest, 2);
 }
@@ -357,7 +357,7 @@ int spi_flash_get_mfr_dev_id(uint8_t *dest)
  */
 int spi_flash_get_unique_id(uint8_t *dest)
 {
-	uint8_t cmd[5] = {SPI_FLASH_UNIQUE_ID, 0, 0, 0, 0};
+	uint8_t cmd[5] = { SPI_FLASH_UNIQUE_ID, 0, 0, 0, 0 };
 
 	return spi_transaction(SPI_FLASH_DEVICE, cmd, sizeof(cmd), dest, 8);
 }
@@ -435,7 +435,8 @@ int spi_flash_check_protect(unsigned int offset, unsigned int bytes)
 	int rv = EC_SUCCESS;
 
 	/* Invalid value */
-	if (sr1 == 0xff || sr2 == 0xff || offset + bytes > CONFIG_FLASH_SIZE)
+	if (sr1 == 0xff || sr2 == 0xff ||
+	    offset + bytes > CONFIG_FLASH_SIZE_BYTES)
 		return EC_ERROR_INVAL;
 
 	/* Compute current protect range */
@@ -466,7 +467,8 @@ int spi_flash_set_protect(unsigned int offset, unsigned int bytes)
 	uint8_t sr2 = spi_flash_get_status2();
 
 	/* Invalid values */
-	if (sr1 == 0xff || sr2 == 0xff || offset + bytes > CONFIG_FLASH_SIZE)
+	if (sr1 == 0xff || sr2 == 0xff ||
+	    offset + bytes > CONFIG_FLASH_SIZE_BYTES)
 		return EC_ERROR_INVAL;
 
 	/* Compute desired protect range */
@@ -477,13 +479,14 @@ int spi_flash_set_protect(unsigned int offset, unsigned int bytes)
 	return spi_flash_set_status(sr1, sr2);
 }
 
-static int command_spi_flashinfo(int argc, char **argv)
+static int command_spi_flashinfo(int argc, const char **argv)
 {
 	uint8_t jedec[3];
 	uint8_t unique[8];
 	int rv;
 
-	spi_enable(CONFIG_SPI_FLASH_PORT, 1);
+	/* TODO(tomhughes): use board function to get devices. */
+	spi_enable(SPI_FLASH_DEVICE, 1);
 
 	/* Wait for previous operation to complete */
 	rv = spi_flash_wait();
@@ -493,18 +496,17 @@ static int command_spi_flashinfo(int argc, char **argv)
 	spi_flash_get_jedec_id(jedec);
 	spi_flash_get_unique_id(unique);
 
-	ccprintf("Manufacturer ID: %02x\nDevice ID: %02x %02x\n",
-		 jedec[0], jedec[1], jedec[2]);
+	ccprintf("Manufacturer ID: %02x\nDevice ID: %02x %02x\n", jedec[0],
+		 jedec[1], jedec[2]);
 	ccprintf("Unique ID: %02x %02x %02x %02x %02x %02x %02x %02x\n",
-		 unique[0], unique[1], unique[2], unique[3],
-		 unique[4], unique[5], unique[6], unique[7]);
+		 unique[0], unique[1], unique[2], unique[3], unique[4],
+		 unique[5], unique[6], unique[7]);
 	ccprintf("Capacity: %4d kB\n", SPI_FLASH_SIZE(jedec[2]) / 1024);
 
 	return rv;
 }
-DECLARE_CONSOLE_COMMAND(spi_flashinfo, command_spi_flashinfo,
-	NULL,
-	"Print SPI flash info");
+DECLARE_CONSOLE_COMMAND(spi_flashinfo, command_spi_flashinfo, NULL,
+			"Print SPI flash info");
 
 #ifdef CONFIG_HOSTCMD_FLASH_SPI_INFO
 static enum ec_status flash_command_spi_info(struct host_cmd_handler_args *args)
@@ -520,13 +522,12 @@ static enum ec_status flash_command_spi_info(struct host_cmd_handler_args *args)
 	args->response_size = sizeof(*r);
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_FLASH_SPI_INFO,
-		     flash_command_spi_info,
+DECLARE_HOST_COMMAND(EC_CMD_FLASH_SPI_INFO, flash_command_spi_info,
 		     EC_VER_MASK(0));
-#endif  /* CONFIG_HOSTCMD_FLASH_SPI_INFO */
+#endif /* CONFIG_HOSTCMD_FLASH_SPI_INFO */
 
 #ifdef CONFIG_CMD_SPI_FLASH
-static int command_spi_flasherase(int argc, char **argv)
+static int command_spi_flasherase(int argc, const char **argv)
 {
 	int offset = -1;
 	int bytes = 4096;
@@ -535,7 +536,7 @@ static int command_spi_flasherase(int argc, char **argv)
 	if (rv)
 		return rv;
 
-	spi_enable(CONFIG_SPI_FLASH_PORT, 1);
+	spi_enable(SPI_FLASH_DEVICE, 1);
 
 	/* Chip has protection */
 	if (spi_flash_check_protect(offset, bytes))
@@ -545,10 +546,9 @@ static int command_spi_flasherase(int argc, char **argv)
 	return spi_flash_erase(offset, bytes);
 }
 DECLARE_CONSOLE_COMMAND(spi_flasherase, command_spi_flasherase,
-	"offset [bytes]",
-	"Erase flash");
+			"offset [bytes]", "Erase flash");
 
-static int command_spi_flashwrite(int argc, char **argv)
+static int command_spi_flashwrite(int argc, const char **argv)
 {
 	int offset = -1;
 	int bytes = SPI_FLASH_MAX_WRITE_SIZE;
@@ -560,7 +560,7 @@ static int command_spi_flashwrite(int argc, char **argv)
 	if (rv)
 		return rv;
 
-	spi_enable(CONFIG_SPI_FLASH_PORT, 1);
+	spi_enable(SPI_FLASH_DEVICE, 1);
 
 	/* Chip has protection */
 	if (spi_flash_check_protect(offset, bytes))
@@ -574,7 +574,8 @@ static int command_spi_flashwrite(int argc, char **argv)
 	while (bytes > 0) {
 		/* First write multiples of 256, then (bytes % 256) last */
 		write_len = ((bytes % SPI_FLASH_MAX_WRITE_SIZE) == bytes) ?
-					bytes : SPI_FLASH_MAX_WRITE_SIZE;
+				    bytes :
+				    SPI_FLASH_MAX_WRITE_SIZE;
 
 		/* Perform write */
 		rv = spi_flash_write(offset, write_len, buf);
@@ -590,10 +591,9 @@ static int command_spi_flashwrite(int argc, char **argv)
 	return rv;
 }
 DECLARE_CONSOLE_COMMAND(spi_flashwrite, command_spi_flashwrite,
-	"offset [bytes]",
-	"Write pattern to flash");
+			"offset [bytes]", "Write pattern to flash");
 
-static int command_spi_flashread(int argc, char **argv)
+static int command_spi_flashread(int argc, const char **argv)
 {
 	int i;
 	int offset = -1;
@@ -605,10 +605,10 @@ static int command_spi_flashread(int argc, char **argv)
 	if (rv)
 		return rv;
 
-	spi_enable(CONFIG_SPI_FLASH_PORT, 1);
+	spi_enable(SPI_FLASH_DEVICE, 1);
 
 	/* Can't read past size of memory */
-	if (offset + bytes > CONFIG_FLASH_SIZE)
+	if (offset + bytes > CONFIG_FLASH_SIZE_BYTES)
 		return EC_ERROR_INVAL;
 
 	/* Wait for previous operation to complete */
@@ -623,8 +623,8 @@ static int command_spi_flashread(int argc, char **argv)
 
 		/* First read (bytes % 256), then in multiples of 256 */
 		read_len = (bytes % SPI_FLASH_MAX_READ_SIZE) ?
-					(bytes % SPI_FLASH_MAX_READ_SIZE) :
-					SPI_FLASH_MAX_READ_SIZE;
+				   (bytes % SPI_FLASH_MAX_READ_SIZE) :
+				   SPI_FLASH_MAX_READ_SIZE;
 
 		rv = spi_flash_read(buf, offset, read_len);
 		if (rv)
@@ -647,24 +647,22 @@ static int command_spi_flashread(int argc, char **argv)
 	ASSERT(bytes == 0);
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(spi_flashread, command_spi_flashread,
-	"offset bytes",
-	"Read flash");
+DECLARE_CONSOLE_COMMAND(spi_flashread, command_spi_flashread, "offset bytes",
+			"Read flash");
 
-static int command_spi_flashread_sr(int argc, char **argv)
+static int command_spi_flashread_sr(int argc, const char **argv)
 {
-	spi_enable(CONFIG_SPI_FLASH_PORT, 1);
+	spi_enable(SPI_FLASH_DEVICE, 1);
 
 	ccprintf("Status Register 1: 0x%02x\n", spi_flash_get_status1());
 	ccprintf("Status Register 2: 0x%02x\n", spi_flash_get_status2());
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(spi_flash_rsr, command_spi_flashread_sr,
-	NULL,
-	"Read status registers");
+DECLARE_CONSOLE_COMMAND(spi_flash_rsr, command_spi_flashread_sr, NULL,
+			"Read status registers");
 
-static int command_spi_flashwrite_sr(int argc, char **argv)
+static int command_spi_flashwrite_sr(int argc, const char **argv)
 {
 	int val1 = 0;
 	int val2 = 0;
@@ -673,17 +671,16 @@ static int command_spi_flashwrite_sr(int argc, char **argv)
 	if (rv)
 		return rv;
 
-	spi_enable(CONFIG_SPI_FLASH_PORT, 1);
+	spi_enable(SPI_FLASH_DEVICE, 1);
 
 	ccprintf("Writing 0x%02x to status register 1, ", val1);
 	ccprintf("0x%02x to status register 2...\n", val2);
 	return spi_flash_set_status(val1, val2);
 }
 DECLARE_CONSOLE_COMMAND(spi_flash_wsr, command_spi_flashwrite_sr,
-	"value1 value2",
-	"Write to status registers");
+			"value1 value2", "Write to status registers");
 
-static int command_spi_flashprotect(int argc, char **argv)
+static int command_spi_flashprotect(int argc, const char **argv)
 {
 	int val1 = 0;
 	int val2 = 0;
@@ -692,12 +689,12 @@ static int command_spi_flashprotect(int argc, char **argv)
 	if (rv)
 		return rv;
 
-	spi_enable(CONFIG_SPI_FLASH_PORT, 1);
+	spi_enable(SPI_FLASH_DEVICE, 1);
 
-	ccprintf("Setting protection for 0x%06x to 0x%06x\n", val1, val1+val2);
+	ccprintf("Setting protection for 0x%06x to 0x%06x\n", val1,
+		 val1 + val2);
 	return spi_flash_set_protect(val1, val2);
 }
-DECLARE_CONSOLE_COMMAND(spi_flash_prot, command_spi_flashprotect,
-	"offset len",
-	"Set block protection");
+DECLARE_CONSOLE_COMMAND(spi_flash_prot, command_spi_flashprotect, "offset len",
+			"Set block protection");
 #endif
diff --git a/common/spi_nor.c b/common/spi_nor.c
index 4fda9f41e1..1eca5d806f 100644
--- a/common/spi_nor.c
+++ b/common/spi_nor.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,18 +7,18 @@
 
 #include "common.h"
 #include "console.h"
-#include "spi_nor.h"
+#include "sfdp.h"
 #include "shared_mem.h"
-#include "util.h"
-#include "task.h"
 #include "spi.h"
-#include "sfdp.h"
+#include "spi_nor.h"
+#include "task.h"
 #include "timer.h"
+#include "util.h"
 #include "watchdog.h"
 
 #ifdef CONFIG_SPI_NOR_DEBUG
 #define CPRINTS(dev, string, args...) \
-	cprints(CC_SPI, "SPI NOR %s: " string, (dev)->name, ## args)
+	cprints(CC_SPI, "SPI NOR %s: " string, (dev)->name, ##args)
 #else
 #define CPRINTS(dev, string, args...)
 #endif
@@ -60,7 +60,7 @@ static int spi_nor_read_status(const struct spi_nor_device_t *spi_nor_device,
 {
 	uint8_t cmd = SPI_NOR_OPCODE_READ_STATUS;
 
-	return spi_transaction(&spi_devices[spi_nor_device->spi_master],
+	return spi_transaction(&spi_devices[spi_nor_device->spi_controller],
 			       &cmd, 1, status_register_value, 1);
 }
 
@@ -74,8 +74,8 @@ static int spi_nor_write_enable(const struct spi_nor_device_t *spi_nor_device)
 	int rv = EC_SUCCESS;
 
 	/* Set the write enable latch. */
-	rv = spi_transaction(&spi_devices[spi_nor_device->spi_master],
-			     &cmd, 1, NULL, 0);
+	rv = spi_transaction(&spi_devices[spi_nor_device->spi_controller], &cmd,
+			     1, NULL, 0);
 	if (rv)
 		return rv;
 
@@ -84,7 +84,7 @@ static int spi_nor_write_enable(const struct spi_nor_device_t *spi_nor_device)
 	if (rv)
 		return rv;
 	if ((status_register_value & SPI_NOR_STATUS_REGISTER_WEL) == 0)
-		return EC_ERROR_UNKNOWN;  /* WEL not set but should be. */
+		return EC_ERROR_UNKNOWN; /* WEL not set but should be. */
 
 	return rv;
 }
@@ -100,8 +100,8 @@ static int spi_nor_read_ear(const struct spi_nor_device_t *spi_nor_device,
 {
 	uint8_t command = SPI_NOR_OPCODE_RDEAR;
 
-	return spi_transaction(&spi_devices[spi_nor_device->spi_master],
-			&command, sizeof(command), value, 1);
+	return spi_transaction(&spi_devices[spi_nor_device->spi_controller],
+			       &command, sizeof(command), value, 1);
 }
 
 int spi_nor_write_ear(const struct spi_nor_device_t *spi_nor_device,
@@ -122,8 +122,8 @@ int spi_nor_write_ear(const struct spi_nor_device_t *spi_nor_device,
 	buf[0] = SPI_NOR_OPCODE_WREAR;
 	buf[1] = value;
 
-	rv = spi_transaction(&spi_devices[spi_nor_device->spi_master],
-			     buf, sizeof(buf), NULL, 0);
+	rv = spi_transaction(&spi_devices[spi_nor_device->spi_controller], buf,
+			     sizeof(buf), NULL, 0);
 	if (rv) {
 		CPRINTS(spi_nor_device, "Failed to write EAR, rv=%d", rv);
 		goto err_free;
@@ -134,9 +134,9 @@ int spi_nor_write_ear(const struct spi_nor_device_t *spi_nor_device,
 		goto err_free;
 
 	if (ear != value) {
-		CPRINTS(spi_nor_device,
-			"Write EAR error: write=%d, read=%d", value, ear);
-		rv = EC_ERROR_UNKNOWN;  /* WEL not set but should be. */
+		CPRINTS(spi_nor_device, "Write EAR error: write=%d, read=%d",
+			value, ear);
+		rv = EC_ERROR_UNKNOWN; /* WEL not set but should be. */
 		goto err_free;
 	}
 
@@ -157,8 +157,7 @@ static int spi_nor_wait(const struct spi_nor_device_t *spi_nor_device)
 	rv = spi_nor_read_status(spi_nor_device, &status_register_value);
 	if (rv)
 		return rv;
-	timeout.val =
-		get_time().val + spi_nor_device->timeout_usec;
+	timeout.val = get_time().val + spi_nor_device->timeout_usec;
 	while (status_register_value & SPI_NOR_STATUS_REGISTER_WIP) {
 		/* Reload the watchdog before sleeping. */
 		watchdog_reload();
@@ -181,10 +180,9 @@ static int spi_nor_wait(const struct spi_nor_device_t *spi_nor_device)
 /**
  * Read the Manufacturer bank and ID out of the JEDEC ID.
  */
-static int spi_nor_read_jedec_mfn_id(
-		const struct spi_nor_device_t *spi_nor_device,
-		uint8_t *out_mfn_bank,
-		uint8_t *out_mfn_id)
+static int
+spi_nor_read_jedec_mfn_id(const struct spi_nor_device_t *spi_nor_device,
+			  uint8_t *out_mfn_bank, uint8_t *out_mfn_id)
 {
 	int rv = EC_SUCCESS;
 	uint8_t jedec_id[SPI_NOR_JEDEC_ID_BANKS];
@@ -192,8 +190,8 @@ static int spi_nor_read_jedec_mfn_id(
 	uint8_t cmd = SPI_NOR_OPCODE_JEDEC_ID;
 
 	/* Read the standardized part of the JEDEC ID. */
-	rv = spi_transaction(&spi_devices[spi_nor_device->spi_master],
-			     &cmd, 1, jedec_id, SPI_NOR_JEDEC_ID_BANKS);
+	rv = spi_transaction(&spi_devices[spi_nor_device->spi_controller], &cmd,
+			     1, jedec_id, SPI_NOR_JEDEC_ID_BANKS);
 	if (rv)
 		return rv;
 
@@ -214,11 +212,11 @@ static int spi_nor_read_jedec_mfn_id(
 /**
  * Read a doubleword out of a SFDP table (DWs are 1-based like the SFDP spec).
  */
-static int spi_nor_read_sfdp_dword(
-		const struct spi_nor_device_t *spi_nor_device,
-		uint32_t table_offset,
-		uint8_t table_double_word,
-		uint32_t *out_dw) {
+static int
+spi_nor_read_sfdp_dword(const struct spi_nor_device_t *spi_nor_device,
+			uint32_t table_offset, uint8_t table_double_word,
+			uint32_t *out_dw)
+{
 	uint8_t sfdp_cmd[5];
 	/* Calculate the byte offset based on the double word. */
 	uint32_t sfdp_offset = table_offset + ((table_double_word - 1) * 4);
@@ -228,8 +226,8 @@ static int spi_nor_read_sfdp_dword(
 	sfdp_cmd[1] = (sfdp_offset & 0xFF0000) >> 16;
 	sfdp_cmd[2] = (sfdp_offset & 0xFF00) >> 8;
 	sfdp_cmd[3] = (sfdp_offset & 0xFF);
-	sfdp_cmd[4] = 0;  /* Required extra cycle. */
-	return spi_transaction(&spi_devices[spi_nor_device->spi_master],
+	sfdp_cmd[4] = 0; /* Required extra cycle. */
+	return spi_transaction(&spi_devices[spi_nor_device->spi_controller],
 			       sfdp_cmd, 5, (uint8_t *)out_dw, 4);
 }
 
@@ -248,10 +246,10 @@ static int is_basic_flash_parameter_table(uint8_t sfdp_major_rev,
 			BASIC_FLASH_PARAMETER_TABLE_1_0_ID);
 	} else if (sfdp_major_rev == 1 && sfdp_minor_rev >= 5) {
 		return ((SFDP_GET_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW1_ID_LSB,
-					  parameter_header_dw1) ==
+					   parameter_header_dw1) ==
 			 BASIC_FLASH_PARAMETER_TABLE_1_5_ID_LSB) &&
 			(SFDP_GET_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW2_ID_MSB,
-					  parameter_header_dw2) ==
+					   parameter_header_dw2) ==
 			 BASIC_FLASH_PARAMETER_TABLE_1_5_ID_MSB));
 	}
 
@@ -262,13 +260,10 @@ static int is_basic_flash_parameter_table(uint8_t sfdp_major_rev,
  * Helper function to locate the SFDP Basic SPI Flash NOR Parameter Table.
  */
 static int locate_sfdp_basic_parameter_table(
-		const struct spi_nor_device_t *spi_nor_device,
-		uint8_t *out_sfdp_major_rev,
-		uint8_t *out_sfdp_minor_rev,
-		uint8_t *out_table_major_rev,
-		uint8_t *out_table_minor_rev,
-		uint32_t *out_table_offset,
-		size_t *out_table_size)
+	const struct spi_nor_device_t *spi_nor_device,
+	uint8_t *out_sfdp_major_rev, uint8_t *out_sfdp_minor_rev,
+	uint8_t *out_table_major_rev, uint8_t *out_table_minor_rev,
+	uint32_t *out_table_offset, size_t *out_table_size)
 {
 	int rv = EC_SUCCESS;
 	uint8_t number_parameter_headers;
@@ -296,8 +291,8 @@ static int locate_sfdp_basic_parameter_table(
 		SFDP_GET_BITFIELD(SFDP_HEADER_DW2_SFDP_MAJOR, dw2);
 	*out_sfdp_minor_rev =
 		SFDP_GET_BITFIELD(SFDP_HEADER_DW2_SFDP_MINOR, dw2);
-	CPRINTS(spi_nor_device, "SFDP v%d.%d discovered",
-		*out_sfdp_major_rev, *out_sfdp_minor_rev);
+	CPRINTS(spi_nor_device, "SFDP v%d.%d discovered", *out_sfdp_major_rev,
+		*out_sfdp_minor_rev);
 
 	/* NPH is 0-based, so add 1. */
 	number_parameter_headers =
@@ -315,17 +310,16 @@ static int locate_sfdp_basic_parameter_table(
 		number_parameter_headers--;
 
 		/* Read this parameter header's two dwords. */
-		rv = spi_nor_read_sfdp_dword(
-			spi_nor_device, table_offset, 1, &dw1);
-		rv |= spi_nor_read_sfdp_dword(
-			spi_nor_device, table_offset, 2, &dw2);
+		rv = spi_nor_read_sfdp_dword(spi_nor_device, table_offset, 1,
+					     &dw1);
+		rv |= spi_nor_read_sfdp_dword(spi_nor_device, table_offset, 2,
+					      &dw2);
 		if (rv)
 			return rv;
 
 		/* Ensure it's the basic flash parameter table. */
-		if (!is_basic_flash_parameter_table(*out_sfdp_major_rev,
-						    *out_sfdp_minor_rev,
-						    dw1, dw2))
+		if (!is_basic_flash_parameter_table(
+			    *out_sfdp_major_rev, *out_sfdp_minor_rev, dw1, dw2))
 			continue;
 
 		/* The parameter header major and minor versioning is still the
@@ -352,8 +346,10 @@ static int locate_sfdp_basic_parameter_table(
 		*out_table_offset = SFDP_GET_BITFIELD(
 			SFDP_1_0_PARAMETER_HEADER_DW2_PTP, dw2);
 		/* Convert the size from DW to Bytes. */
-		*out_table_size = SFDP_GET_BITFIELD(
-			SFDP_1_0_PARAMETER_HEADER_DW1_PTL, dw1) * 4;
+		*out_table_size =
+			SFDP_GET_BITFIELD(SFDP_1_0_PARAMETER_HEADER_DW1_PTL,
+					  dw1) *
+			4;
 	}
 
 	if (!table_found) {
@@ -376,8 +372,7 @@ static int spi_nor_device_discover_sfdp_page_size(
 	struct spi_nor_device_t *spi_nor_device,
 	uint8_t basic_parameter_table_major_version,
 	uint8_t basic_parameter_table_minor_version,
-	uint32_t basic_parameter_table_offset,
-	size_t *page_size)
+	uint32_t basic_parameter_table_offset, size_t *page_size)
 {
 	int rv = EC_SUCCESS;
 	uint32_t dw;
@@ -397,12 +392,12 @@ static int spi_nor_device_discover_sfdp_page_size(
 	} else if (basic_parameter_table_major_version == 1 &&
 		   basic_parameter_table_minor_version >= 5) {
 		/* Use the Basic Flash Parameter v1.5 page size reporting. */
-		rv = spi_nor_read_sfdp_dword(spi_nor_device,
-				     basic_parameter_table_offset, 11, &dw);
+		rv = spi_nor_read_sfdp_dword(
+			spi_nor_device, basic_parameter_table_offset, 11, &dw);
 		if (rv)
 			return rv;
-		*page_size =
-			1 << SFDP_GET_BITFIELD(BFPT_1_5_DW11_PAGE_SIZE, dw);
+		*page_size = 1
+			     << SFDP_GET_BITFIELD(BFPT_1_5_DW11_PAGE_SIZE, dw);
 	}
 
 	return EC_SUCCESS;
@@ -413,11 +408,10 @@ static int spi_nor_device_discover_sfdp_page_size(
  * NOR Parameter Table.
  */
 static int spi_nor_device_discover_sfdp_capacity(
-		struct spi_nor_device_t *spi_nor_device,
-		uint8_t basic_parameter_table_major_version,
-		uint8_t basic_parameter_table_minor_version,
-		uint32_t basic_parameter_table_offset,
-		uint32_t *capacity)
+	struct spi_nor_device_t *spi_nor_device,
+	uint8_t basic_parameter_table_major_version,
+	uint8_t basic_parameter_table_minor_version,
+	uint32_t basic_parameter_table_offset, uint32_t *capacity)
 {
 	int rv = EC_SUCCESS;
 	uint32_t dw;
@@ -425,15 +419,16 @@ static int spi_nor_device_discover_sfdp_capacity(
 	/* First attempt to discover the device's capacity. */
 	if (basic_parameter_table_major_version == 1) {
 		/* Use the Basic Flash Parameter v1.0 capacity reporting. */
-		rv = spi_nor_read_sfdp_dword(spi_nor_device,
-				     basic_parameter_table_offset, 2, &dw);
+		rv = spi_nor_read_sfdp_dword(
+			spi_nor_device, basic_parameter_table_offset, 2, &dw);
 		if (rv)
 			return rv;
 
 		if (SFDP_GET_BITFIELD(BFPT_1_0_DW2_GT_2_GIBIBITS, dw)) {
 			/* Ensure the capacity is less than 4GiB. */
-			uint64_t tmp_capacity = 1 <<
-				(SFDP_GET_BITFIELD(BFPT_1_0_DW2_N, dw) - 3);
+			uint64_t tmp_capacity =
+				1
+				<< (SFDP_GET_BITFIELD(BFPT_1_0_DW2_N, dw) - 3);
 			if (tmp_capacity > UINT32_MAX)
 				return EC_ERROR_OVERFLOW;
 			*capacity = tmp_capacity;
@@ -456,8 +451,7 @@ static int spi_nor_read_internal(const struct spi_nor_device_t *spi_nor_device,
 	 * is larger than the maximum read size.
 	 */
 	while (size > 0) {
-		size_t read_size =
-			MIN(size, CONFIG_SPI_NOR_MAX_READ_SIZE);
+		size_t read_size = MIN(size, CONFIG_SPI_NOR_MAX_READ_SIZE);
 		size_t read_command_size;
 
 		/* Set up the read command in the TX buffer. */
@@ -468,15 +462,16 @@ static int spi_nor_read_internal(const struct spi_nor_device_t *spi_nor_device,
 			buf[3] = (offset & 0xFF00) >> 8;
 			buf[4] = (offset & 0xFF);
 			read_command_size = 5;
-		} else {  /* in 3 byte addressing mode */
+		} else { /* in 3 byte addressing mode */
 			buf[1] = (offset & 0xFF0000) >> 16;
 			buf[2] = (offset & 0xFF00) >> 8;
 			buf[3] = (offset & 0xFF);
 			read_command_size = 4;
 		}
 
-		rv = spi_transaction(&spi_devices[spi_nor_device->spi_master],
-				     buf, read_command_size, data, read_size);
+		rv = spi_transaction(
+			&spi_devices[spi_nor_device->spi_controller], buf,
+			read_command_size, data, read_size);
 		if (rv)
 			return rv;
 
@@ -512,16 +507,12 @@ int spi_nor_init(void)
 		uint8_t table_major_rev, table_minor_rev;
 		uint32_t table_offset;
 		size_t table_size;
-		struct spi_nor_device_t *spi_nor_device =
-			&spi_nor_devices[i];
+		struct spi_nor_device_t *spi_nor_device = &spi_nor_devices[i];
 
-		rv |= locate_sfdp_basic_parameter_table(spi_nor_device,
-							&sfdp_major_rev,
-							&sfdp_minor_rev,
-							&table_major_rev,
-							&table_minor_rev,
-							&table_offset,
-							&table_size);
+		rv |= locate_sfdp_basic_parameter_table(
+			spi_nor_device, &sfdp_major_rev, &sfdp_minor_rev,
+			&table_major_rev, &table_minor_rev, &table_offset,
+			&table_size);
 
 		/* If we failed to find a compatible SFDP Basic Flash Parameter
 		 * table, use the default capacity, page size, and addressing
@@ -531,13 +522,11 @@ int spi_nor_init(void)
 			uint32_t capacity = 0;
 
 			rv |= spi_nor_device_discover_sfdp_page_size(
-				spi_nor_device,
-				table_major_rev, table_minor_rev, table_offset,
-				&page_size);
+				spi_nor_device, table_major_rev,
+				table_minor_rev, table_offset, &page_size);
 			rv |= spi_nor_device_discover_sfdp_capacity(
-				spi_nor_device,
-				table_major_rev, table_minor_rev, table_offset,
-				&capacity);
+				spi_nor_device, table_major_rev,
+				table_minor_rev, table_offset, &capacity);
 			if (rv == EC_SUCCESS) {
 				mutex_lock(&driver_mutex);
 				spi_nor_device->capacity = capacity;
@@ -566,9 +555,9 @@ int spi_nor_init(void)
  *
  * WARNING:
  * 1) In 3 Byte addressing mode only 16MiB of Serial NOR Flash is accessible.
- * 2) If there's a second SPI master communicating with this Serial NOR Flash
- *    part on the board, the user is responsible for ensuring addressing mode
- *    compatibility and cooperation.
+ * 2) If there's a second SPI controller communicating with this Serial
+ *    NOR Flash part on the board, the user is responsible for ensuring
+ *    addressing mode compatibility and cooperation.
  * 3) The user must ensure that multiple users do not trample on each other
  *    by having multiple parties changing the device's addressing mode.
  *
@@ -594,8 +583,8 @@ int spi_nor_set_4b_mode(struct spi_nor_device_t *spi_nor_device,
 	/* Claim the driver mutex to modify the device state. */
 	mutex_lock(&driver_mutex);
 
-	rv = spi_transaction(&spi_devices[spi_nor_device->spi_master],
-			     &cmd, 1, NULL, 0);
+	rv = spi_transaction(&spi_devices[spi_nor_device->spi_controller], &cmd,
+			     1, NULL, 0);
 	if (rv == EC_SUCCESS) {
 		spi_nor_device->in_4b_addressing_mode =
 			enter_4b_addressing_mode;
@@ -618,7 +607,8 @@ int spi_nor_set_4b_mode(struct spi_nor_device_t *spi_nor_device,
  * @return ec_error_list (non-zero on error and timeout).
  */
 int spi_nor_read_jedec_id(const struct spi_nor_device_t *spi_nor_device,
-			  size_t size, uint8_t *data) {
+			  size_t size, uint8_t *data)
+{
 	int rv;
 	uint8_t cmd = SPI_NOR_OPCODE_JEDEC_ID;
 
@@ -627,8 +617,8 @@ int spi_nor_read_jedec_id(const struct spi_nor_device_t *spi_nor_device,
 	/* Claim the driver mutex. */
 	mutex_lock(&driver_mutex);
 	/* Read the JEDEC ID. */
-	rv = spi_transaction(&spi_devices[spi_nor_device->spi_master],
-			     &cmd, 1, data, size);
+	rv = spi_transaction(&spi_devices[spi_nor_device->spi_controller], &cmd,
+			     1, data, size);
 	/* Release the driver mutex. */
 	mutex_unlock(&driver_mutex);
 
@@ -644,8 +634,8 @@ int spi_nor_read_jedec_id(const struct spi_nor_device_t *spi_nor_device,
  * @param data Destination buffer for data.
  * @return ec_error_list (non-zero on error and timeout).
  */
-int spi_nor_read(const struct spi_nor_device_t *spi_nor_device,
-		 uint32_t offset, size_t size, uint8_t *data)
+int spi_nor_read(const struct spi_nor_device_t *spi_nor_device, uint32_t offset,
+		 size_t size, uint8_t *data)
 {
 	int rv;
 
@@ -707,8 +697,8 @@ int spi_nor_erase(const struct spi_nor_device_t *spi_nor_device,
 		read_offset = offset;
 		read_left = erase_size;
 		while (read_left) {
-			read_size = MIN(read_left,
-					CONFIG_SPI_NOR_MAX_READ_SIZE);
+			read_size =
+				MIN(read_left, CONFIG_SPI_NOR_MAX_READ_SIZE);
 			/* Since CONFIG_SPI_NOR_MAX_READ_SIZE & erase_size are
 			 * both guaranteed to be multiples of 4.
 			 */
@@ -730,8 +720,8 @@ int spi_nor_erase(const struct spi_nor_device_t *spi_nor_device,
 			 */
 			verify_offset = 0;
 			while (verify_offset <= read_size - 4) {
-				if (*(uint32_t *)(buffer + verify_offset)
-				    != 0xffffffff) {
+				if (*(uint32_t *)(buffer + verify_offset) !=
+				    0xffffffff) {
 					break;
 				}
 				verify_offset += 4;
@@ -766,7 +756,7 @@ int spi_nor_erase(const struct spi_nor_device_t *spi_nor_device,
 			buf[3] = (offset & 0xFF00) >> 8;
 			buf[4] = (offset & 0xFF);
 			erase_command_size = 5;
-		} else {  /* in 3 byte addressing mode */
+		} else { /* in 3 byte addressing mode */
 			buf[1] = (offset & 0xFF0000) >> 16;
 			buf[2] = (offset & 0xFF00) >> 8;
 			buf[3] = (offset & 0xFF);
@@ -774,8 +764,8 @@ int spi_nor_erase(const struct spi_nor_device_t *spi_nor_device,
 		}
 
 		rv = spi_transaction(
-			&spi_devices[spi_nor_device->spi_master],
-			buf, erase_command_size, NULL, 0);
+			&spi_devices[spi_nor_device->spi_controller], buf,
+			erase_command_size, NULL, 0);
 		if (rv)
 			goto err_free;
 
@@ -813,8 +803,8 @@ int spi_nor_write(const struct spi_nor_device_t *spi_nor_device,
 
 	/* Ensure the device's page size fits in the driver's buffer, if not
 	 * emulate a smaller page size based on the buffer size. */
-	effective_page_size = MIN(spi_nor_device->page_size,
-			       CONFIG_SPI_NOR_MAX_WRITE_SIZE);
+	effective_page_size =
+		MIN(spi_nor_device->page_size, CONFIG_SPI_NOR_MAX_WRITE_SIZE);
 
 	/* Split the write into multiple writes if the size is too large. */
 	while (size > 0) {
@@ -842,7 +832,7 @@ int spi_nor_write(const struct spi_nor_device_t *spi_nor_device,
 			buf[3] = (offset & 0xFF00) >> 8;
 			buf[4] = (offset & 0xFF);
 			prefix_size = 5;
-		} else {  /* in 3 byte addressing mode */
+		} else { /* in 3 byte addressing mode */
 			buf[1] = (offset & 0xFF0000) >> 16;
 			buf[2] = (offset & 0xFF00) >> 8;
 			buf[3] = (offset & 0xFF);
@@ -851,8 +841,9 @@ int spi_nor_write(const struct spi_nor_device_t *spi_nor_device,
 		/* Copy data to write into the buffer after the prefix. */
 		memmove(buf + prefix_size, data, write_size);
 
-		rv = spi_transaction(&spi_devices[spi_nor_device->spi_master],
-				     buf, prefix_size + write_size, NULL, 0);
+		rv = spi_transaction(
+			&spi_devices[spi_nor_device->spi_controller], buf,
+			prefix_size + write_size, NULL, 0);
 		if (rv)
 			goto err_free;
 
@@ -875,7 +866,7 @@ int spi_nor_write(const struct spi_nor_device_t *spi_nor_device,
 /* Serial NOR Flash console commands. */
 
 #ifdef CONFIG_CMD_SPI_NOR
-static int command_spi_nor_info(int argc, char **argv)
+static int command_spi_nor_info(int argc, const char **argv)
 {
 	int rv = EC_SUCCESS;
 
@@ -904,16 +895,15 @@ static int command_spi_nor_info(int argc, char **argv)
 
 		ccprintf("Serial NOR Flash Device %d:\n", spi_nor_device_index);
 		ccprintf("\tName: %s\n", spi_nor_device->name);
-		ccprintf("\tSPI master index: %d\n",
-			 spi_nor_device->spi_master);
-		ccprintf("\tTimeout: %d uSec\n",
-			 spi_nor_device->timeout_usec);
+		ccprintf("\tSPI controller index: %d\n",
+			 spi_nor_device->spi_controller);
+		ccprintf("\tTimeout: %d uSec\n", spi_nor_device->timeout_usec);
 		ccprintf("\tCapacity: %d KiB\n",
 			 spi_nor_device->capacity >> 10),
-		ccprintf("\tAddressing: %s addressing mode\n",
-			 spi_nor_device->in_4b_addressing_mode ? "4B" : "3B");
-		ccprintf("\tPage Size: %d Bytes\n",
-			 spi_nor_device->page_size);
+			ccprintf("\tAddressing: %s addressing mode\n",
+				 spi_nor_device->in_4b_addressing_mode ? "4B" :
+									 "3B");
+		ccprintf("\tPage Size: %d Bytes\n", spi_nor_device->page_size);
 
 		/* Get JEDEC ID info. */
 		rv = spi_nor_read_jedec_mfn_id(spi_nor_device, &mfn_bank,
@@ -925,27 +915,26 @@ static int command_spi_nor_info(int argc, char **argv)
 
 		/* Get SFDP info. */
 		if (locate_sfdp_basic_parameter_table(
-			spi_nor_device, &sfdp_major_rev, &sfdp_minor_rev,
-			&table_major_rev, &table_minor_rev, &table_offset,
-			&table_size) != EC_SUCCESS) {
+			    spi_nor_device, &sfdp_major_rev, &sfdp_minor_rev,
+			    &table_major_rev, &table_minor_rev, &table_offset,
+			    &table_size) != EC_SUCCESS) {
 			ccputs("\tNo JEDEC SFDP support detected\n");
-			continue;  /* Go on to the next device. */
+			continue; /* Go on to the next device. */
 		}
 		ccprintf("\tSFDP v%d.%d\n", sfdp_major_rev, sfdp_minor_rev);
 		ccprintf("\tFlash Parameter Table v%d.%d (%dB @ 0x%x)\n",
-			 table_major_rev, table_minor_rev,
-			 table_size, table_offset);
+			 table_major_rev, table_minor_rev, table_size,
+			 table_offset);
 	}
 
 	return rv;
 }
-DECLARE_CONSOLE_COMMAND(spinorinfo, command_spi_nor_info,
-			"[device]",
+DECLARE_CONSOLE_COMMAND(spinorinfo, command_spi_nor_info, "[device]",
 			"Report Serial NOR Flash device information");
-#endif  /* CONFIG_CMD_SPI_NOR */
+#endif /* CONFIG_CMD_SPI_NOR */
 
 #ifdef CONFIG_CMD_SPI_NOR
-static int command_spi_nor_erase(int argc, char **argv)
+static int command_spi_nor_erase(int argc, const char **argv)
 {
 	const struct spi_nor_device_t *spi_nor_device;
 	int spi_nor_device_index;
@@ -965,17 +954,16 @@ static int command_spi_nor_erase(int argc, char **argv)
 	if (rv)
 		return rv;
 
-	ccprintf("Erasing %d bytes at 0x%x on %s...\n",
-		 size, offset, spi_nor_device->name);
+	ccprintf("Erasing %d bytes at 0x%x on %s...\n", size, offset,
+		 spi_nor_device->name);
 	return spi_nor_erase(spi_nor_device, offset, size);
 }
 DECLARE_CONSOLE_COMMAND(spinorerase, command_spi_nor_erase,
-			"device [offset] [size]",
-			"Erase flash");
-#endif  /* CONFIG_CMD_SPI_NOR */
+			"device [offset] [size]", "Erase flash");
+#endif /* CONFIG_CMD_SPI_NOR */
 
 #ifdef CONFIG_CMD_SPI_NOR
-static int command_spi_nor_write(int argc, char **argv)
+static int command_spi_nor_write(int argc, const char **argv)
 {
 	const struct spi_nor_device_t *spi_nor_device;
 	int spi_nor_device_index;
@@ -1011,8 +999,8 @@ static int command_spi_nor_write(int argc, char **argv)
 	for (i = 0; i < size; i++)
 		data[i] = i;
 
-	ccprintf("Writing %d bytes to 0x%x on %s...\n",
-		 size, offset, spi_nor_device->name);
+	ccprintf("Writing %d bytes to 0x%x on %s...\n", size, offset,
+		 spi_nor_device->name);
 	rv = spi_nor_write(spi_nor_device, offset, size, data);
 
 	/* Free the buffer */
@@ -1021,12 +1009,11 @@ static int command_spi_nor_write(int argc, char **argv)
 	return rv;
 }
 DECLARE_CONSOLE_COMMAND(spinorwrite, command_spi_nor_write,
-			"device [offset] [size]",
-			"Write pattern to flash");
-#endif  /* CONFIG_CMD_SPI_NOR */
+			"device [offset] [size]", "Write pattern to flash");
+#endif /* CONFIG_CMD_SPI_NOR */
 
 #ifdef CONFIG_CMD_SPI_NOR
-static int command_spi_nor_read(int argc, char **argv)
+static int command_spi_nor_read(int argc, const char **argv)
 {
 	const struct spi_nor_device_t *spi_nor_device;
 	int spi_nor_device_index;
@@ -1059,8 +1046,7 @@ static int command_spi_nor_read(int argc, char **argv)
 	}
 
 	/* Read the data */
-	ccprintf("Reading %d bytes from %s...",
-		 size, spi_nor_device->name);
+	ccprintf("Reading %d bytes from %s...", size, spi_nor_device->name);
 	if (spi_nor_read(spi_nor_device, offset, size, data)) {
 		rv = EC_ERROR_INVAL;
 		goto err_free;
@@ -1084,6 +1070,5 @@ static int command_spi_nor_read(int argc, char **argv)
 	return rv;
 }
 DECLARE_CONSOLE_COMMAND(spinorread, command_spi_nor_read,
-			"device [offset] [size]",
-			"Read flash");
-#endif  /* CONFIG_CMD_SPI_NOR */
+			"device [offset] [size]", "Read flash");
+#endif /* CONFIG_CMD_SPI_NOR */
diff --git a/common/stillness_detector.c b/common/stillness_detector.c
index c33472aa22..f81c51ef3a 100644
--- a/common/stillness_detector.c
+++ b/common/stillness_detector.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,6 +6,7 @@
 #include "common.h"
 #include "stillness_detector.h"
 #include "timer.h"
+
 #include <string.h>
 
 static void still_det_reset(struct still_det *still_det)
@@ -23,8 +24,8 @@ static bool stillness_batch_complete(struct still_det *still_det,
 				     uint32_t sample_time)
 {
 	bool complete = false;
-	uint32_t batch_window = time_until(still_det->window_start_time,
-					   sample_time);
+	uint32_t batch_window =
+		time_until(still_det->window_start_time, sample_time);
 
 	/* Checking if enough data is accumulated */
 	if (batch_window >= still_det->min_batch_window &&
@@ -51,8 +52,8 @@ static inline fp_t compute_variance(fp_t acc_squared, fp_t acc, fp_t inv)
 	return fp_mul((acc_squared - fp_mul(fp_sq(acc), inv)), inv);
 }
 
-bool still_det_update(struct still_det *still_det, uint32_t sample_time,
-		      fp_t x, fp_t y, fp_t z)
+bool still_det_update(struct still_det *still_det, uint32_t sample_time, fp_t x,
+		      fp_t y, fp_t z)
 {
 	fp_t inv = FLOAT_TO_FP(0.0f), var_x, var_y, var_z;
 	bool complete = false;
@@ -88,12 +89,12 @@ bool still_det_update(struct still_det *still_det, uint32_t sample_time,
 			return complete;
 		}
 		/* Calculating the VAR = sum(x^2)/n - sum(x)^2/n^2 */
-		var_x = compute_variance(
-			still_det->acc_xx, still_det->acc_x, inv);
-		var_y = compute_variance(
-			still_det->acc_yy, still_det->acc_y, inv);
-		var_z = compute_variance(
-			still_det->acc_zz, still_det->acc_z, inv);
+		var_x = compute_variance(still_det->acc_xx, still_det->acc_x,
+					 inv);
+		var_y = compute_variance(still_det->acc_yy, still_det->acc_y,
+					 inv);
+		var_z = compute_variance(still_det->acc_zz, still_det->acc_z,
+					 inv);
 		/* Checking if sensor is still */
 		if (var_x < still_det->var_threshold &&
 		    var_y < still_det->var_threshold &&
diff --git a/common/switch.c b/common/switch.c
index ea07efbca0..f2a3266ed0 100644
--- a/common/switch.c
+++ b/common/switch.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,10 +15,11 @@
 #include "power_button.h"
 #include "switch.h"
 #include "util.h"
+#include "write_protect.h"
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_SWITCH, outstr)
-#define CPRINTS(format, args...) cprints(CC_SWITCH, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SWITCH, format, ##args)
 
 static uint8_t *memmap_switches;
 
@@ -43,17 +44,12 @@ static void switch_update(void)
 	else
 		*memmap_switches &= ~EC_SWITCH_POWER_BUTTON_PRESSED;
 
-#ifdef CONFIG_LID_SWITCH
-	if (lid_is_open())
+	if (!IS_ENABLED(CONFIG_LID_SWITCH) || lid_is_open())
 		*memmap_switches |= EC_SWITCH_LID_OPEN;
 	else
 		*memmap_switches &= ~EC_SWITCH_LID_OPEN;
-#else
-	/* For lid-less systems, lid looks always open */
-	*memmap_switches |= EC_SWITCH_LID_OPEN;
-#endif
 
-	if ((flash_get_protect() & EC_FLASH_PROTECT_GPIO_ASSERTED) == 0)
+	if ((crec_flash_get_protect() & EC_FLASH_PROTECT_GPIO_ASSERTED) == 0)
 		*memmap_switches |= EC_SWITCH_WRITE_PROTECT_DISABLED;
 	else
 		*memmap_switches &= ~EC_SWITCH_WRITE_PROTECT_DISABLED;
@@ -93,11 +89,7 @@ static void switch_init(void)
 	 * reading the write protect signal, but we enable the interrupt for it
 	 * here.  Take ownership of WP back, or refactor it to its own module.
 	 */
-#ifdef CONFIG_WP_ACTIVE_HIGH
-	gpio_enable_interrupt(GPIO_WP);
-#else
-	gpio_enable_interrupt(GPIO_WP_L);
-#endif
+	write_protect_enable_interrupt();
 }
 DECLARE_HOOK(HOOK_INIT, switch_init, HOOK_PRIO_INIT_SWITCH);
 
@@ -107,18 +99,14 @@ void switch_interrupt(enum gpio_signal signal)
 }
 
 #ifdef CONFIG_CMD_MMAPINFO
-static int command_mmapinfo(int argc, char **argv)
+static int command_mmapinfo(int argc, const char **argv)
 {
 	uint8_t *memmap_switches = host_get_memmap(EC_MEMMAP_SWITCHES);
 	uint8_t val = *memmap_switches;
 	int i;
 	const char *explanation[] = {
-		"lid_open",
-		"powerbtn",
-		"wp_off",
-		"kbd_rec",
-		"gpio_rec",
-		"fake_dev",
+		"lid_open", "powerbtn", "wp_off",
+		"kbd_rec",  "gpio_rec", "fake_dev",
 	};
 	ccprintf("memmap switches = 0x%x\n", val);
 	for (i = 0; i < ARRAY_SIZE(explanation); i++)
@@ -127,7 +115,6 @@ static int command_mmapinfo(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(mmapinfo, command_mmapinfo,
-			NULL,
+DECLARE_CONSOLE_COMMAND(mmapinfo, command_mmapinfo, NULL,
 			"Print memmap switch state");
 #endif
diff --git a/common/system.c b/common/system.c
index 206f74181c..6c2acc3bfc 100644
--- a/common/system.c
+++ b/common/system.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,6 +13,7 @@
 #include "cpu.h"
 #include "cros_board_info.h"
 #include "dma.h"
+#include "extpower.h"
 #include "flash.h"
 #include "gpio.h"
 #include "hooks.h"
@@ -26,31 +27,32 @@
 #ifdef CONFIG_MPU
 #include "mpu.h"
 #endif
+#include "cros_version.h"
 #include "panic.h"
 #include "sysjump.h"
 #include "system.h"
+#include "system_boot_time.h"
 #include "task.h"
 #include "timer.h"
 #include "uart.h"
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 #include "util.h"
-#include "version.h"
 #include "watchdog.h"
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 /* Round up to a multiple of 4 */
 #define ROUNDUP4(x) (((x) + 3) & ~3)
 
 /* Data for an individual jump tag */
 struct jump_tag {
-	uint16_t tag;		/* Tag ID */
-	uint8_t data_size;	/* Size of data which follows */
-	uint8_t data_version;	/* Data version */
+	uint16_t tag; /* Tag ID */
+	uint8_t data_size; /* Size of data which follows */
+	uint8_t data_version; /* Data version */
 
 	/* Followed by data_size bytes of data */
 };
@@ -58,33 +60,37 @@ struct jump_tag {
 /* Jump data (at end of RAM, or preceding panic data) */
 static struct jump_data *jdata;
 
-static uint32_t reset_flags;
+static uint32_t reset_flags; /* EC_RESET_FLAG_* */
 static int jumped_to_image;
-static int disable_jump;  /* Disable ALL jumps if system is locked */
-static int force_locked;  /* Force system locked even if WP isn't enabled */
-static enum ec_reboot_cmd reboot_at_shutdown;
+static int disable_jump; /* Disable ALL jumps if system is locked */
+static int force_locked; /* Force system locked even if WP isn't enabled */
+static struct ec_params_reboot_ec reboot_at_shutdown;
+
+static enum sysinfo_flags system_info_flags;
+
+/* Ensure enough space for panic_data, jump_data and at least one jump tag */
+BUILD_ASSERT((sizeof(struct panic_data) + sizeof(struct jump_data) +
+	      JUMP_TAG_MAX_SIZE) <= CONFIG_PRESERVED_END_OF_RAM_SIZE,
+	     "End of ram data size is too small for panic and jump data");
 
 STATIC_IF(CONFIG_HIBERNATE) uint32_t hibernate_seconds;
 STATIC_IF(CONFIG_HIBERNATE) uint32_t hibernate_microseconds;
 
 /* On-going actions preventing going into deep-sleep mode */
-uint32_t sleep_mask;
+atomic_t sleep_mask;
 
 #ifdef CONFIG_LOW_POWER_IDLE_LIMITED
 /* Set it to prevent going into idle mode */
-uint32_t idle_disabled;
+atomic_t idle_disabled;
 #endif
 
-#ifdef CONFIG_HOSTCMD_AP_SET_SKUID
+/* SKU ID sourced from AP */
 static uint32_t ap_sku_id;
 
-uint32_t system_get_sku_id(void)
-{
-	return ap_sku_id;
-}
+#ifdef CONFIG_HOSTCMD_AP_SET_SKUID
 
-#define AP_SKUID_SYSJUMP_TAG		0x4153 /* AS */
-#define AP_SKUID_HOOK_VERSION		1
+#define AP_SKUID_SYSJUMP_TAG 0x4153 /* AS */
+#define AP_SKUID_HOOK_VERSION 1
 
 /**
  * Preserve AP SKUID across a sysjump.
@@ -109,13 +115,26 @@ static void ap_sku_id_restore_state(void)
 		AP_SKUID_SYSJUMP_TAG, &version, &size);
 
 	if (prev_ap_sku_id && version == AP_SKUID_HOOK_VERSION &&
-		size == sizeof(prev_ap_sku_id)) {
+	    size == sizeof(prev_ap_sku_id)) {
 		memcpy(&ap_sku_id, prev_ap_sku_id, sizeof(ap_sku_id));
 	}
 }
 DECLARE_HOOK(HOOK_INIT, ap_sku_id_restore_state, HOOK_PRIO_DEFAULT);
 #endif
 
+__overridable uint32_t board_get_sku_id(void)
+{
+	return 0;
+}
+
+uint32_t system_get_sku_id(void)
+{
+	if (IS_ENABLED(CONFIG_HOSTCMD_AP_SET_SKUID))
+		return ap_sku_id;
+
+	return board_get_sku_id();
+}
+
 /**
  * Return the program memory address where the image `copy` begins or should
  * begin. In the case of external storage, the image may or may not currently
@@ -162,7 +181,7 @@ static uint32_t __attribute__((unused)) get_size(enum ec_image copy)
 	}
 }
 
-int system_is_locked(void)
+test_mockable int system_is_locked(void)
 {
 	static int is_locked = -1;
 
@@ -176,13 +195,13 @@ int system_is_locked(void)
 	is_locked = 0;
 	return 0;
 
-#elif defined(CONFIG_FLASH)
+#elif defined(CONFIG_FLASH_CROS)
 	/*
 	 * Unlocked if write protect pin deasserted or read-only firmware
 	 * is not protected.
 	 */
 	if ((EC_FLASH_PROTECT_GPIO_ASSERTED | EC_FLASH_PROTECT_RO_NOW) &
-	    ~flash_get_protect()) {
+	    ~crec_flash_get_protect()) {
 		is_locked = 0;
 		return 0;
 	}
@@ -209,26 +228,32 @@ test_mockable uintptr_t system_usable_ram_end(void)
 	return (uintptr_t)jdata - jdata->jump_tag_total;
 }
 
-void system_encode_save_flags(int reset_flags, uint32_t *save_flags)
+void system_encode_save_flags(int flags, uint32_t *save_flags)
 {
 	*save_flags = 0;
 
 	/* Save current reset reasons if necessary */
-	if (reset_flags & SYSTEM_RESET_PRESERVE_FLAGS)
+	if (flags & SYSTEM_RESET_PRESERVE_FLAGS)
 		*save_flags = system_get_reset_flags() |
 			      EC_RESET_FLAG_PRESERVED;
 
 	/* Add in AP off flag into saved flags. */
-	if (reset_flags & SYSTEM_RESET_LEAVE_AP_OFF)
+	if (flags & SYSTEM_RESET_LEAVE_AP_OFF)
 		*save_flags |= EC_RESET_FLAG_AP_OFF;
 
 	/* Add in stay in RO flag into saved flags. */
-	if (reset_flags & SYSTEM_RESET_STAY_IN_RO)
+	if (flags & SYSTEM_RESET_STAY_IN_RO)
 		*save_flags |= EC_RESET_FLAG_STAY_IN_RO;
 
+	/* Add in watchdog flag into saved flags. */
+	if (flags & SYSTEM_RESET_AP_WATCHDOG)
+		*save_flags |= EC_RESET_FLAG_AP_WATCHDOG;
+
 	/* Save reset flag */
-	if (reset_flags & (SYSTEM_RESET_HARD | SYSTEM_RESET_WAIT_EXT))
+	if (flags & (SYSTEM_RESET_HARD | SYSTEM_RESET_WAIT_EXT))
 		*save_flags |= EC_RESET_FLAG_HARD;
+	else if (flags & SYSTEM_RESET_HIBERNATE)
+		*save_flags |= EC_RESET_FLAG_HIBERNATE;
 	else
 		*save_flags |= EC_RESET_FLAG_SOFT;
 }
@@ -252,8 +277,8 @@ static void print_reset_flags(uint32_t flags)
 {
 	int count = 0;
 	int i;
-	static const char * const reset_flag_descs[] = {
-		#include "reset_flag_desc.inc"
+	static const char *const reset_flag_descs[] = {
+#include "reset_flag_desc.inc"
 	};
 
 	if (!flags) {
@@ -283,12 +308,46 @@ void system_print_reset_flags(void)
 	print_reset_flags(reset_flags);
 }
 
-int system_jumped_to_this_image(void)
+void system_print_banner(void)
+{
+	/* be less verbose if we boot for USB resume to meet spec timings */
+	if (!(system_get_reset_flags() & EC_RESET_FLAG_USB_RESUME)) {
+		CPUTS("\n");
+		if (system_jumped_to_this_image())
+			CPRINTS("UART initialized after sysjump");
+		else
+			CPUTS("\n--- UART initialized after reboot ---\n");
+		CPRINTF("[Image: %s, %s]\n", system_get_image_copy_string(),
+			system_get_build_info());
+		CPUTS("[Reset cause: ");
+		system_print_reset_flags();
+		CPUTS("]\n");
+	}
+}
+
+#ifdef CONFIG_RAM_SIZE
+struct jump_data *get_jump_data(void)
+{
+	uintptr_t addr;
+
+	/*
+	 * Put the jump data before the panic data, or at the end of RAM if
+	 * panic data is not present.
+	 */
+	addr = get_panic_data_start();
+	if (!addr)
+		addr = CONFIG_RAM_BASE + CONFIG_RAM_SIZE;
+
+	return (struct jump_data *)(addr - sizeof(struct jump_data));
+}
+#endif
+
+test_mockable int system_jumped_to_this_image(void)
 {
 	return jumped_to_image;
 }
 
-int system_jumped_late(void)
+test_mockable int system_jumped_late(void)
 {
 	return !(reset_flags & EC_RESET_FLAG_EFS) && jumped_to_image;
 }
@@ -296,15 +355,24 @@ int system_jumped_late(void)
 int system_add_jump_tag(uint16_t tag, int version, int size, const void *data)
 {
 	struct jump_tag *t;
+	size_t new_entry_size;
 
 	/* Only allowed during a sysjump */
 	if (!jdata || jdata->magic != JUMP_DATA_MAGIC)
 		return EC_ERROR_UNKNOWN;
 
 	/* Make room for the new tag */
-	if (size > 255)
+	if (size > JUMP_TAG_MAX_SIZE)
 		return EC_ERROR_INVAL;
-	jdata->jump_tag_total += ROUNDUP4(size) + sizeof(struct jump_tag);
+
+	new_entry_size = ROUNDUP4(size) + sizeof(struct jump_tag);
+
+	if (system_usable_ram_end() - new_entry_size < JUMP_DATA_MIN_ADDRESS) {
+		ccprintf("ERROR: out of space for jump tags\n");
+		return EC_ERROR_INVAL;
+	}
+
+	jdata->jump_tag_total += new_entry_size;
 
 	t = (struct jump_tag *)system_usable_ram_end();
 	t->tag = tag;
@@ -316,7 +384,8 @@ int system_add_jump_tag(uint16_t tag, int version, int size, const void *data)
 	return EC_SUCCESS;
 }
 
-const uint8_t *system_get_jump_tag(uint16_t tag, int *version, int *size)
+test_mockable const uint8_t *system_get_jump_tag(uint16_t tag, int *version,
+						 int *size)
 {
 	const struct jump_tag *t;
 	int used = 0;
@@ -324,6 +393,10 @@ const uint8_t *system_get_jump_tag(uint16_t tag, int *version, int *size)
 	if (!jdata)
 		return NULL;
 
+	/* Ensure system_usable_ram_end() is within bounds */
+	if (system_usable_ram_end() < JUMP_DATA_MIN_ADDRESS)
+		return NULL;
+
 	/* Search through tag data for a match */
 	while (used < jdata->jump_tag_total) {
 		/* Check the next tag */
@@ -345,12 +418,13 @@ const uint8_t *system_get_jump_tag(uint16_t tag, int *version, int *size)
 	return NULL;
 }
 
-void system_disable_jump(void)
+test_mockable void system_disable_jump(void)
 {
 	disable_jump = 1;
 
 #ifdef CONFIG_MPU
 	if (system_is_locked()) {
+#ifndef CONFIG_ZEPHYR
 		int ret;
 		enum ec_image __attribute__((unused)) copy;
 
@@ -360,9 +434,8 @@ void system_disable_jump(void)
 		 */
 		ret = mpu_protect_data_ram();
 		if (ret == EC_SUCCESS) {
-			CPRINTS("data RAM locked. Exclusion %pP-%pP",
-				&__iram_text_start,
-				&__iram_text_end);
+			CPRINTS("data RAM locked. Exclusion %p-%p",
+				&__iram_text_start, &__iram_text_end);
 		} else {
 			CPRINTS("Failed to lock data RAM (%d)", ret);
 			return;
@@ -386,11 +459,11 @@ void system_disable_jump(void)
 		 */
 		switch (system_get_image_copy()) {
 		case EC_IMAGE_RO:
-			ret =  mpu_lock_rw_flash();
+			ret = mpu_lock_rw_flash();
 			copy = EC_IMAGE_RW;
 			break;
 		case EC_IMAGE_RW:
-			ret =  mpu_lock_ro_flash();
+			ret = mpu_lock_ro_flash();
 			copy = EC_IMAGE_RO;
 			break;
 		default:
@@ -398,14 +471,14 @@ void system_disable_jump(void)
 			ret = !EC_SUCCESS;
 		}
 		if (ret == EC_SUCCESS) {
-			CPRINTS("%s image locked",
-				ec_image_to_string(copy));
+			CPRINTS("%s image locked", ec_image_to_string(copy));
 		} else {
 			CPRINTS("Failed to lock %s image (%d)",
 				ec_image_to_string(copy), ret);
 			return;
 		}
 #endif /* !CONFIG_EXTERNAL_STORAGE */
+#endif /* !CONFIG_ZEPHYR */
 
 		/* All regions were configured successfully, enable MPU */
 		mpu_enable();
@@ -421,8 +494,8 @@ test_mockable enum ec_image system_get_image_copy(void)
 	/* Return which region is used in program memory */
 	return system_get_shrspi_image_copy();
 #else
-	uintptr_t my_addr = (uintptr_t)system_get_image_copy -
-			    CONFIG_PROGRAM_MEMORY_BASE;
+	uintptr_t my_addr =
+		(uintptr_t)system_get_image_copy - CONFIG_PROGRAM_MEMORY_BASE;
 
 	if (my_addr >= CONFIG_RO_MEM_OFF &&
 	    my_addr < (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE))
@@ -485,12 +558,18 @@ const char *system_get_image_copy_string(void)
 
 const char *ec_image_to_string(enum ec_image copy)
 {
-	static const char * const image_names[] = {
-		"unknown", "RO", "RW", "RO_B", "RW_B"
-	};
+	static const char *const image_names[] = { "unknown", "RO", "RW",
+						   "RO_B", "RW_B" };
 	return image_names[copy < ARRAY_SIZE(image_names) ? copy : 0];
 }
 
+__overridable void board_pulse_entering_rw(void)
+{
+	gpio_set_level(GPIO_ENTERING_RW, 1);
+	usleep(MSEC);
+	gpio_set_level(GPIO_ENTERING_RW, 0);
+}
+
 /**
  * Jump to what we hope is the init address of an image.
  *
@@ -498,7 +577,7 @@ const char *ec_image_to_string(enum ec_image copy)
  *
  * @param init_addr	Init address of target image
  */
-static void jump_to_image(uintptr_t init_addr)
+test_mockable_static void jump_to_image(uintptr_t init_addr)
 {
 	void (*resetvec)(void);
 
@@ -511,9 +590,7 @@ static void jump_to_image(uintptr_t init_addr)
 	 * drop it again so we don't leak power through the pulldown in the
 	 * Silego.
 	 */
-	gpio_set_level(GPIO_ENTERING_RW, 1);
-	usleep(MSEC);
-	gpio_set_level(GPIO_ENTERING_RW, 0);
+	board_pulse_entering_rw();
 
 	/*
 	 * Since in EFS2, USB/PD won't be enabled in RO or if it's enabled in
@@ -526,11 +603,11 @@ static void jump_to_image(uintptr_t init_addr)
 	 *  check whether PD tasks have started (instead of VBOOT_EFS2, which
 	 *  is static).
 	 */
-	if (task_start_called() && IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP))
+	if (IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP) && task_start_called())
 		/* Note: must be before i2c module is locked down */
 		pd_prepare_sysjump();
 
-#ifdef CONFIG_I2C_MASTER
+#ifdef CONFIG_I2C_CONTROLLER
 	/* Prepare I2C module for sysjump */
 	i2c_prepare_sysjump();
 #endif
@@ -543,22 +620,22 @@ static void jump_to_image(uintptr_t init_addr)
 	jdata->magic = JUMP_DATA_MAGIC;
 	jdata->version = JUMP_DATA_VERSION;
 	jdata->reset_flags = reset_flags;
-	jdata->jump_tag_total = 0;  /* Reset tags */
+	jdata->jump_tag_total = 0; /* Reset tags */
 	jdata->struct_size = sizeof(struct jump_data);
 
 	/* Call other hooks; these may add tags */
 	hook_notify(HOOK_SYSJUMP);
 
 	/* Disable interrupts before jump */
-	interrupt_disable();
+	interrupt_disable_all();
 
-#ifdef CONFIG_DMA
+#ifdef CONFIG_DMA_CROS
 	/* Disable all DMA channels to avoid memory corruption */
 	dma_disable_all();
-#endif /* CONFIG_DMA */
+#endif /* CONFIG_DMA_CROS */
 
 	/* Jump to the reset vector */
-	resetvec = (void(*)(void))init_addr;
+	resetvec = (void (*)(void))init_addr;
 	resetvec();
 }
 
@@ -572,8 +649,8 @@ int system_is_in_rw(void)
 	return is_rw_image(system_get_image_copy());
 }
 
-static int system_run_image_copy_with_flags(enum ec_image copy,
-					    uint32_t add_reset_flags)
+test_mockable_static int
+system_run_image_copy_with_flags(enum ec_image copy, uint32_t add_reset_flags)
 {
 	uintptr_t base;
 	uintptr_t init_addr;
@@ -613,11 +690,6 @@ static int system_run_image_copy_with_flags(enum ec_image copy,
 		init_addr = system_get_fw_reset_vector(base);
 	} else {
 		uintptr_t init = base + 4;
-
-		/* Skip any head room in the RO image */
-		if (copy == EC_IMAGE_RO)
-			init += CONFIG_RO_HEAD_ROOM;
-
 		init_addr = *(uintptr_t *)(init);
 
 		/* Make sure the reset vector is inside the destination image */
@@ -628,7 +700,12 @@ static int system_run_image_copy_with_flags(enum ec_image copy,
 
 	system_set_reset_flags(add_reset_flags);
 
-	CPRINTS("Jumping to image %s", ec_image_to_string(copy));
+	/* If jumping back to RO, we're no longer in the EFS context. */
+	if (copy == EC_IMAGE_RO)
+		system_clear_reset_flags(EC_RESET_FLAG_EFS);
+
+	CPRINTS("Jumping to image %s (0x%08x)", ec_image_to_string(copy),
+		system_get_reset_flags());
 
 	jump_to_image(init_addr);
 
@@ -654,9 +731,9 @@ enum ec_image system_get_active_copy(void)
 
 enum ec_image system_get_update_copy(void)
 {
-#ifdef CONFIG_VBOOT_EFS		/* Not needed for EFS2, which is single-slot. */
-	return system_get_active_copy() == EC_IMAGE_RW_A ?
-			EC_IMAGE_RW_B : EC_IMAGE_RW_A;
+#ifdef CONFIG_VBOOT_EFS /* Not needed for EFS2, which is single-slot. */
+	return system_get_active_copy() == EC_IMAGE_RW_A ? EC_IMAGE_RW_B :
+							   EC_IMAGE_RW_A;
 #else
 	return EC_IMAGE_RW_A;
 #endif
@@ -667,6 +744,7 @@ int system_set_active_copy(enum ec_image copy)
 	return system_set_bbram(SYSTEM_BBRAM_IDX_TRY_SLOT, copy);
 }
 
+#ifdef CONFIG_EC_PROTECTED_STORAGE_OFF
 /*
  * This is defined in system.c instead of flash.c because it's called even
  * on the boards which don't include flash.o. (e.g. hadoken, stm32l476g-eval)
@@ -682,6 +760,7 @@ uint32_t flash_get_rw_offset(enum ec_image copy)
 
 	return CONFIG_EC_PROTECTED_STORAGE_OFF + CONFIG_RO_STORAGE_OFF;
 }
+#endif
 
 const struct image_data *system_get_image_data(enum ec_image copy)
 {
@@ -701,7 +780,7 @@ const struct image_data *system_get_image_data(enum ec_image copy)
 	 * it's the same offset as in the current image.  Find that offset.
 	 */
 	addr = ((uintptr_t)&current_image_data -
-	       get_program_memory_addr(active_copy));
+		get_program_memory_addr(active_copy));
 
 	/*
 	 * Read the version information from the proper location
@@ -711,12 +790,12 @@ const struct image_data *system_get_image_data(enum ec_image copy)
 
 #ifdef CONFIG_MAPPED_STORAGE
 	addr += CONFIG_MAPPED_STORAGE_BASE;
-	flash_lock_mapped_storage(1);
+	crec_flash_lock_mapped_storage(1);
 	memcpy(&data, (const void *)addr, sizeof(data));
-	flash_lock_mapped_storage(0);
+	crec_flash_lock_mapped_storage(0);
 #else
 	/* Read the version struct from flash into a buffer. */
-	if (flash_read(addr, sizeof(data), (char *)&data))
+	if (crec_flash_read(addr, sizeof(data), (char *)&data))
 		return NULL;
 #endif
 
@@ -729,14 +808,30 @@ const struct image_data *system_get_image_data(enum ec_image copy)
 	return NULL;
 }
 
-__attribute__((weak))	   /* Weird chips may need their own implementations */
-const char *system_get_version(enum ec_image copy)
+__attribute__((weak)) /* Weird chips may need their own implementations */
+const char *
+system_get_version(enum ec_image copy)
 {
 	const struct image_data *data = system_get_image_data(copy);
 
 	return data ? data->version : "";
 }
 
+const char *system_get_cros_fwid(enum ec_image copy)
+{
+	const struct image_data *data;
+
+	if (IS_ENABLED(CONFIG_CROS_FWID_VERSION)) {
+		data = system_get_image_data(copy);
+		if (data && (data->cookie3 & CROS_EC_IMAGE_DATA_COOKIE3_MASK) ==
+				    CROS_EC_IMAGE_DATA_COOKIE3)
+			return data->cros_fwid;
+		else
+			return CROS_FWID_MISSING_STR;
+	}
+	return "";
+}
+
 #ifdef CONFIG_ROLLBACK
 int32_t system_get_rollback_version(enum ec_image copy)
 {
@@ -753,45 +848,52 @@ int system_get_image_used(enum ec_image copy)
 	return data ? MAX((int)data->size, 0) : 0;
 }
 
+/*
+ * Overwrite it in board directory in case that we want to read board version
+ * in our own way.
+ */
+__overridable int board_get_version(void)
+{
+#ifdef CONFIG_BOARD_VERSION_GPIO
+	return (!!gpio_get_level(GPIO_BOARD_VERSION1) << 0) |
+	       (!!gpio_get_level(GPIO_BOARD_VERSION2) << 1) |
+	       (!!gpio_get_level(GPIO_BOARD_VERSION3) << 2);
+#else
+	return 0;
+#endif
+}
+
 /*
  * Returns positive board version if successfully retrieved. Otherwise the
  * value is a negative version of an EC return code. Without this optimization
  * multiple boards run out of flash size.
  */
-int system_get_board_version(void)
+test_mockable int system_get_board_version(void)
 {
-#if defined(CONFIG_BOARD_VERSION_CUSTOM)
+	int board_id;
+
+	if (IS_ENABLED(CONFIG_BOARD_VERSION_CBI)) {
+		int error;
+
+		error = cbi_get_board_version(&board_id);
+		if (error)
+			return -error;
+
+		return board_id;
+	};
+
 	return board_get_version();
-#elif defined(CONFIG_BOARD_VERSION_GPIO)
-	return
-		(!!gpio_get_level(GPIO_BOARD_VERSION1) << 0) |
-		(!!gpio_get_level(GPIO_BOARD_VERSION2) << 1) |
-		(!!gpio_get_level(GPIO_BOARD_VERSION3) << 2);
-#elif defined(CONFIG_BOARD_VERSION_CBI)
-	int error;
-	int32_t version;
-
-	error = cbi_get_board_version(&version);
-	if (error)
-		return -error;
-	else
-		return version;
-#else
-	return 0;
-#endif
 }
 
-__attribute__((weak))	   /* Weird chips may need their own implementations */
-const char *system_get_build_info(void)
+__attribute__((weak)) /* Weird chips may need their own implementations */
+const char *
+system_get_build_info(void)
 {
 	return build_info;
 }
 
 void system_common_pre_init(void)
 {
-	uintptr_t addr;
-
-#ifdef CONFIG_SOFTWARE_PANIC
 	/*
 	 * Log panic cause if watchdog caused reset and panic cause
 	 * was not already logged. This must happen before calculating
@@ -801,22 +903,21 @@ void system_common_pre_init(void)
 		uint32_t reason;
 		uint32_t info;
 		uint8_t exception;
+		struct panic_data *pdata;
 
 		panic_get_reason(&reason, &info, &exception);
-		if (reason != PANIC_SW_WATCHDOG)
+		pdata = panic_get_data();
+		/* The watchdog panic info may have already been initialized by
+		 * the watchdog handler, so only set it here if the panic reason
+		 * is not a watchdog or the panic info has already been read,
+		 * i.e. an old watchdog panic.
+		 */
+		if (reason != PANIC_SW_WATCHDOG || !pdata ||
+		    pdata->flags & PANIC_DATA_FLAG_OLD_HOSTCMD)
 			panic_set_reason(PANIC_SW_WATCHDOG, 0, 0);
 	}
-#endif
-
-	/*
-	 * Put the jump data before the panic data, or at the end of RAM if
-	 * panic data is not present.
-	 */
-	addr = get_panic_data_start();
-	if (!addr)
-		addr = CONFIG_RAM_BASE + CONFIG_RAM_SIZE;
 
-	jdata = (struct jump_data *)(addr - sizeof(struct jump_data));
+	jdata = get_jump_data();
 
 	/*
 	 * Check jump data if this is a jump between images.
@@ -838,12 +939,24 @@ void system_common_pre_init(void)
 		 * the new fields below.
 		 */
 		if (jdata->version == 1)
-			delta = 0;  /* No tags in v1, so no need for move */
+			delta = 0; /* No tags in v1, so no need for move */
 		else if (jdata->version == 2)
 			delta = sizeof(struct jump_data) - JUMP_DATA_SIZE_V2;
 		else
 			delta = sizeof(struct jump_data) - jdata->struct_size;
 
+		/*
+		 * Check if enough space for jump data.
+		 * Clear jump data and return if not.
+		 */
+		if (system_usable_ram_end() < JUMP_DATA_MIN_ADDRESS) {
+			/* TODO(b/251190975): This failure should be reported
+			 * in the panic data structure for more visibility.
+			 */
+			memset(jdata, 0, sizeof(struct jump_data));
+			return;
+		}
+
 		if (delta && jdata->jump_tag_total) {
 			uint8_t *d = (uint8_t *)system_usable_ram_end();
 			memmove(d, d + delta, jdata->jump_tag_total);
@@ -872,25 +985,44 @@ void system_common_pre_init(void)
 	}
 }
 
+void system_enter_manual_recovery(void)
+{
+	system_info_flags |= SYSTEM_IN_MANUAL_RECOVERY;
+}
+
+void system_exit_manual_recovery(void)
+{
+	system_info_flags &= ~SYSTEM_IN_MANUAL_RECOVERY;
+}
+
 int system_is_manual_recovery(void)
 {
-	return host_is_event_set(EC_HOST_EVENT_KEYBOARD_RECOVERY);
+	return system_info_flags & SYSTEM_IN_MANUAL_RECOVERY;
 }
 
 /**
  * Handle a pending reboot command.
  */
-static int handle_pending_reboot(enum ec_reboot_cmd cmd)
+static int handle_pending_reboot(struct ec_params_reboot_ec p)
 {
-	switch (cmd) {
+	if (IS_ENABLED(CONFIG_POWER_BUTTON_INIT_IDLE) &&
+	    (p.flags & EC_REBOOT_FLAG_CLEAR_AP_IDLE)) {
+		CPRINTS("Clearing AP_IDLE");
+		chip_save_reset_flags(chip_read_reset_flags() &
+				      ~EC_RESET_FLAG_AP_IDLE);
+	}
+
+	switch (p.cmd) {
 	case EC_REBOOT_CANCEL:
+	case EC_REBOOT_NO_OP:
 		return EC_SUCCESS;
 	case EC_REBOOT_JUMP_RO:
-		return system_run_image_copy_with_flags(EC_IMAGE_RO,
-						EC_RESET_FLAG_STAY_IN_RO);
+		return system_run_image_copy_with_flags(
+			EC_IMAGE_RO, EC_RESET_FLAG_STAY_IN_RO);
 	case EC_REBOOT_JUMP_RW:
 		return system_run_image_copy(system_get_active_copy());
 	case EC_REBOOT_COLD:
+	case EC_REBOOT_COLD_AP_OFF:
 		/*
 		 * Reboot the PD chip(s) as well, but first suspend the ports
 		 * if this board has PD tasks running so they don't query the
@@ -916,26 +1048,27 @@ static int handle_pending_reboot(enum ec_reboot_cmd cmd)
 			board_reset_pd_mcu();
 
 		cflush();
-		system_reset(SYSTEM_RESET_HARD);
+		if (p.cmd == EC_REBOOT_COLD_AP_OFF)
+			system_reset(SYSTEM_RESET_HARD |
+				     SYSTEM_RESET_LEAVE_AP_OFF);
+		else
+			system_reset(SYSTEM_RESET_HARD);
 		/* That shouldn't return... */
 		return EC_ERROR_UNKNOWN;
 	case EC_REBOOT_DISABLE_JUMP:
 		system_disable_jump();
 		return EC_SUCCESS;
-	case EC_REBOOT_HIBERNATE_CLEAR_AP_OFF:
-		if (!IS_ENABLED(CONFIG_HIBERNATE))
-			return EC_ERROR_INVAL;
-
-		if (IS_ENABLED(CONFIG_POWER_BUTTON_INIT_IDLE)) {
-			CPRINTS("Clearing AP_IDLE");
-			chip_save_reset_flags(chip_read_reset_flags() &
-					      ~EC_RESET_FLAG_AP_IDLE);
-		}
-		/* Intentional fall-through */
 	case EC_REBOOT_HIBERNATE:
 		if (!IS_ENABLED(CONFIG_HIBERNATE))
 			return EC_ERROR_INVAL;
 
+		/*
+		 * Allow some time for the system to quiesce before entering EC
+		 * hibernate.  Otherwise, some stray signals may cause an
+		 * immediate wake up.
+		 */
+		CPRINTS("Waiting 1s before hibernating...");
+		msleep(1000);
 		CPRINTS("system hibernating");
 		system_hibernate(hibernate_seconds, hibernate_microseconds);
 		/* That shouldn't return... */
@@ -945,14 +1078,54 @@ static int handle_pending_reboot(enum ec_reboot_cmd cmd)
 	}
 }
 
+test_mockable void system_enter_hibernate(uint32_t seconds,
+					  uint32_t microseconds)
+{
+	if (!IS_ENABLED(CONFIG_HIBERNATE))
+		return;
+
+	/*
+	 * On ChromeOS devices, if AC is present, don't hibernate.
+	 * It might trigger an immediate wake up (since AC is present),
+	 * resulting in an AP reboot.
+	 * Hibernate when AC is present never occurs in normal circumstances,
+	 * this is to prevent an action triggered by developers.
+	 * See: b/192259035
+	 */
+	if (IS_ENABLED(CONFIG_EXTPOWER) &&
+	    IS_ENABLED(CONFIG_AP_POWER_CONTROL) && extpower_is_present()) {
+		CPRINTS("AC on, skip hibernate");
+		return;
+	}
+
+	/*
+	 * If chipset is already off, then call system_hibernate directly. Else,
+	 * let chipset_task bring down the power rails and transition to proper
+	 * state before system_hibernate is called.
+	 */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		system_hibernate(seconds, microseconds);
+	else {
+		reboot_at_shutdown.cmd = EC_REBOOT_HIBERNATE;
+		hibernate_seconds = seconds;
+		hibernate_microseconds = microseconds;
+
+		chipset_force_shutdown(CHIPSET_SHUTDOWN_CONSOLE_CMD);
+	}
+}
+
 /*****************************************************************************/
 /* Hooks */
 
 static void system_common_shutdown(void)
 {
-	if (reboot_at_shutdown)
-		CPRINTF("Reboot at shutdown: %d\n", reboot_at_shutdown);
+	system_exit_manual_recovery();
+	if (reboot_at_shutdown.cmd)
+		CPRINTF("Reboot at shutdown: %d\n", reboot_at_shutdown.cmd);
 	handle_pending_reboot(reboot_at_shutdown);
+
+	/* Reset cnt on cold boot */
+	update_ap_boot_time(RESET_CNT);
 }
 DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN_COMPLETE, system_common_shutdown,
 	     HOOK_PRIO_DEFAULT);
@@ -970,23 +1143,25 @@ static int sysinfo(struct ec_response_sysinfo *info)
 	info->current_image = system_get_image_copy();
 
 	if (system_jumped_to_this_image())
-		info->flags |= SYSTEM_JUMPED_TO_CURRENT_IMAGE;
+		system_info_flags |= SYSTEM_JUMPED_TO_CURRENT_IMAGE;
 
 	if (system_is_locked()) {
-		info->flags |= SYSTEM_IS_LOCKED;
+		system_info_flags |= SYSTEM_IS_LOCKED;
 		if (force_locked)
-			info->flags |= SYSTEM_IS_FORCE_LOCKED;
+			system_info_flags |= SYSTEM_IS_FORCE_LOCKED;
 		if (!disable_jump)
-			info->flags |= SYSTEM_JUMP_ENABLED;
+			system_info_flags |= SYSTEM_JUMP_ENABLED;
 	}
 
-	if (reboot_at_shutdown)
-		info->flags |= SYSTEM_REBOOT_AT_SHUTDOWN;
+	if (reboot_at_shutdown.cmd)
+		system_info_flags |= SYSTEM_REBOOT_AT_SHUTDOWN;
+
+	info->flags = system_info_flags;
 
 	return EC_SUCCESS;
 }
 
-static int command_sysinfo(int argc, char **argv)
+static int command_sysinfo(int argc, const char **argv)
 {
 	struct ec_response_sysinfo info;
 	int rv;
@@ -1001,6 +1176,8 @@ static int command_sysinfo(int argc, char **argv)
 	ccprintf("Copy:   %s\n", ec_image_to_string(info.current_image));
 	ccprintf("Jumped: %s\n",
 		 (info.flags & SYSTEM_JUMPED_TO_CURRENT_IMAGE) ? "yes" : "no");
+	ccprintf("Recovery: %s\n",
+		 (info.flags & SYSTEM_IN_MANUAL_RECOVERY) ? "yes" : "no");
 
 	ccputs("Flags: ");
 	if (info.flags & SYSTEM_IS_LOCKED) {
@@ -1019,8 +1196,7 @@ static int command_sysinfo(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_SAFE_CONSOLE_COMMAND(sysinfo, command_sysinfo,
-			     NULL,
+DECLARE_SAFE_CONSOLE_COMMAND(sysinfo, command_sysinfo, NULL,
 			     "Print system info");
 
 static enum ec_status host_command_sysinfo(struct host_cmd_handler_args *args)
@@ -1040,9 +1216,10 @@ DECLARE_HOST_COMMAND(EC_CMD_SYSINFO, host_command_sysinfo,
 #endif
 
 #ifdef CONFIG_CMD_SCRATCHPAD
-static int command_scratchpad(int argc, char **argv)
+static int command_scratchpad(int argc, const char **argv)
 {
 	int rv = EC_SUCCESS;
+	uint32_t scratchpad_value;
 
 	if (argc == 2) {
 		char *e;
@@ -1050,17 +1227,26 @@ static int command_scratchpad(int argc, char **argv)
 		if (*e)
 			return EC_ERROR_PARAM1;
 		rv = system_set_scratchpad(s);
+
+		if (rv) {
+			ccprintf("Error setting scratchpad register (%d)\b",
+				 rv);
+			return rv;
+		}
 	}
 
-	ccprintf("Scratchpad: 0x%08x\n", system_get_scratchpad());
+	rv = system_get_scratchpad(&scratchpad_value);
+	if (rv)
+		ccprintf("Error reading scratchpad register (%d)\n", rv);
+	else
+		ccprintf("Scratchpad: 0x%08x\n", scratchpad_value);
 	return rv;
 }
-DECLARE_CONSOLE_COMMAND(scratchpad, command_scratchpad,
-			"[val]",
+DECLARE_CONSOLE_COMMAND(scratchpad, command_scratchpad, "[val]",
 			"Get or set scratchpad value");
 #endif /* CONFIG_CMD_SCRATCHPAD */
 
-__maybe_unused static int command_hibernate(int argc, char **argv)
+__maybe_unused static int command_hibernate(int argc, const char **argv)
 {
 	int seconds = 0;
 	int microseconds = 0;
@@ -1071,7 +1257,8 @@ __maybe_unused static int command_hibernate(int argc, char **argv)
 		microseconds = strtoi(argv[2], NULL, 0);
 
 	if (seconds || microseconds) {
-		if (IS_ENABLED(CONFIG_HIBERNATE_PSL)) {
+		if (IS_ENABLED(CONFIG_HIBERNATE_PSL) &&
+		    !IS_ENABLED(NPCX_LCT_SUPPORT)) {
 			ccprintf("Hibernating with timeout not supported "
 				 "when PSL is enabled.\n");
 			return EC_ERROR_INVAL;
@@ -1080,26 +1267,12 @@ __maybe_unused static int command_hibernate(int argc, char **argv)
 	} else
 		ccprintf("Hibernating until wake pin asserted.\n");
 
-	/*
-	 * If chipset is already off, then call system_hibernate directly. Else,
-	 * let chipset_task bring down the power rails and transition to proper
-	 * state before system_hibernate is called.
-	 */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		system_hibernate(seconds, microseconds);
-	else {
-		reboot_at_shutdown = EC_REBOOT_HIBERNATE;
-		hibernate_seconds = seconds;
-		hibernate_microseconds = microseconds;
-
-		chipset_force_shutdown(CHIPSET_SHUTDOWN_CONSOLE_CMD);
-	}
+	system_enter_hibernate(seconds, microseconds);
 
 	return EC_SUCCESS;
 }
 #ifdef CONFIG_HIBERNATE
-DECLARE_CONSOLE_COMMAND(hibernate, command_hibernate,
-			"[sec] [usec]",
+DECLARE_CONSOLE_COMMAND(hibernate, command_hibernate, "[sec] [usec]",
 			"Hibernate the EC");
 #endif /* CONFIG_HIBERNATE */
 
@@ -1114,106 +1287,109 @@ DECLARE_CONSOLE_COMMAND(hibernate, command_hibernate,
  *
  * cr50_v1.1.4979-0061603+ private-cr51:v0.0.66-bd9a0fe tpm2:v0.0.259-2b...
  *
- * Each subcomponent in this case includes the ":v" substring. For these
- * combined version strings this function prints each version or subcomponent
- * version on a different line.
  */
 static void print_build_string(void)
 {
 	const char *full_build_string;
 	const char *p;
-	char symbol;
-	int seen_colonv;
+	size_t next_token_len;
+	size_t line_len = 0;
+	const size_t max_line_len = 50;
 
-	ccprintf("Build:   ");
+	ccprintf("Build:\t");
 	full_build_string = system_get_build_info();
-
-	/* 50 characters or less, will fit into the terminal line. */
-	if (strlen(full_build_string) < 50) {
-		ccprintf("%s\n", full_build_string);
-		return;
-	}
-
-	/*
-	 * Build version string needs splitting, let's split it at the first
-	 * space (this is where the main version ends), and then on each space
-	 * after the ":v" substring, this is where subcomponent versions are
-	 * separated.
-	 */
 	p = full_build_string;
-	seen_colonv = 1;
-
-	symbol = *p++;
-	while (symbol) {
-		if ((symbol == ' ') && seen_colonv) {
-			seen_colonv = 0;
-			/* Indent each line under 'Build:    ' */
-			ccprintf("\n         ");
-		} else {
-			if ((symbol == ':') && (*p == 'v'))
-				seen_colonv = 1;
-			ccprintf("%c", symbol);
+
+	while (*p) {
+		/* Print first token */
+		if (*p == ' ') {
+			next_token_len = strcspn(p + 1, " \0");
+			if (next_token_len + line_len > max_line_len) {
+				line_len = 0;
+				p++;
+				ccprintf("\n\t\t");
+				continue;
+			}
 		}
-		symbol = *p++;
+		ccprintf("%c", *p++);
+		line_len++;
 	}
 	ccprintf("\n");
 }
 
-static int command_version(int argc, char **argv)
+static int command_version(int argc, const char **argv)
 {
 	int board_version;
+	const char *fw_version;
+	const char *cros_fwid;
+	bool __maybe_unused is_active;
 
-	ccprintf("Chip:    %s %s %s\n", system_get_chip_vendor(),
+	ccprintf("Chip:\t%s %s %s\n", system_get_chip_vendor(),
 		 system_get_chip_name(), system_get_chip_revision());
 
 	board_version = system_get_board_version();
 	if (board_version < 0)
-		ccprintf("Board:   Error %d\n", -board_version);
+		ccprintf("Board:\tError %d\n", -board_version);
 	else
-		ccprintf("Board:   %d\n", board_version);
-
-#ifdef CHIP_HAS_RO_B
-	{
-		enum ec_image active;
-
-		active = system_get_ro_image_copy();
-		ccprintf("RO_A:  %c %s\n",
-			 (active == EC_IMAGE_RO ? '*' : ' '),
-			 system_get_version(EC_IMAGE_RO));
-		ccprintf("RO_B:  %c %s\n",
-			 (active == EC_IMAGE_RO_B ? '*' : ' '),
-			 system_get_version(EC_IMAGE_RO_B));
+		ccprintf("Board:\t%d\n", board_version);
+
+	fw_version = system_get_version(EC_IMAGE_RO);
+	cros_fwid = system_get_cros_fwid(EC_IMAGE_RO);
+	if (IS_ENABLED(CHIP_HAS_RO_B)) {
+		is_active = system_get_ro_image_copy() == EC_IMAGE_RO;
+
+		ccprintf("RO_A:\t%s%s\n", is_active ? "* " : "", fw_version);
+		if (IS_NONEMPTY_STRING(cros_fwid))
+			ccprintf("\t\t%s%s\n", is_active ? "* " : "",
+				 cros_fwid);
+
+		is_active = system_get_ro_image_copy() == EC_IMAGE_RO_B;
+		fw_version = system_get_version(EC_IMAGE_RO_B);
+		cros_fwid = system_get_cros_fwid(EC_IMAGE_RO_B);
+
+		ccprintf("RO_B:\t%s%s\n", is_active ? "* " : "", fw_version);
+		if (IS_NONEMPTY_STRING(cros_fwid))
+			ccprintf("\t\t%s%s\n", is_active ? "* " : "",
+				 cros_fwid);
+	} else {
+		ccprintf("RO:\t%s\n", fw_version);
+		if (IS_NONEMPTY_STRING(cros_fwid))
+			ccprintf("\t\t%s\n", cros_fwid);
 	}
-#else
-	ccprintf("RO:      %s\n", system_get_version(EC_IMAGE_RO));
-#endif
-#ifdef CONFIG_RW_B
-	{
-		enum ec_image active;
-
-		active = system_get_image_copy();
-		ccprintf("RW_A:  %c %s\n",
-			 (active == EC_IMAGE_RW ? '*' : ' '),
-			 system_get_version(EC_IMAGE_RW));
-		ccprintf("RW_B:  %c %s\n",
-			 (active == EC_IMAGE_RW_B ? '*' : ' '),
-			 system_get_version(EC_IMAGE_RW_B));
+
+	fw_version = system_get_version(EC_IMAGE_RW);
+	cros_fwid = system_get_cros_fwid(EC_IMAGE_RW);
+	if (IS_ENABLED(CONFIG_RW_B)) {
+		is_active = system_get_active_copy() == EC_IMAGE_RW;
+
+		ccprintf("RW_A:\t%s%s\n", is_active ? "* " : "", fw_version);
+		if (IS_NONEMPTY_STRING(cros_fwid))
+			ccprintf("\t\t%s%s\n", is_active ? "* " : "",
+				 cros_fwid);
+
+		fw_version = system_get_version(EC_IMAGE_RW_B);
+		cros_fwid = system_get_cros_fwid(EC_IMAGE_RW_B);
+		is_active = system_get_active_copy() == EC_IMAGE_RW_B;
+
+		ccprintf("RW_B:\t%s%s\n", is_active ? "* " : "", fw_version);
+		if (IS_NONEMPTY_STRING(cros_fwid))
+			ccprintf("\t\t%s%s\n", is_active ? "* " : "",
+				 cros_fwid);
+	} else {
+		ccprintf("RW:\t%s\n", fw_version);
+		if (IS_NONEMPTY_STRING(cros_fwid))
+			ccprintf("\t\t%s\n", cros_fwid);
 	}
-#else
-	ccprintf("RW:      %s\n", system_get_version(EC_IMAGE_RW));
-#endif
 
 	system_print_extended_version_info();
 	print_build_string();
 
 	return EC_SUCCESS;
 }
-DECLARE_SAFE_CONSOLE_COMMAND(version, command_version,
-			     NULL,
-			     "Print versions");
+DECLARE_SAFE_CONSOLE_COMMAND(version, command_version, NULL, "Print versions");
 
 #ifdef CONFIG_CMD_SYSJUMP
-static int command_sysjump(int argc, char **argv)
+static int command_sysjump(int argc, const char **argv)
 {
 	uint32_t addr;
 	char *e;
@@ -1223,8 +1399,8 @@ static int command_sysjump(int argc, char **argv)
 
 	/* Handle named images */
 	if (!strcasecmp(argv[1], "RO"))
-		return system_run_image_copy_with_flags(EC_IMAGE_RO,
-						EC_RESET_FLAG_STAY_IN_RO);
+		return system_run_image_copy_with_flags(
+			EC_IMAGE_RO, EC_RESET_FLAG_STAY_IN_RO);
 	else if (!strcasecmp(argv[1], "RW") || !strcasecmp(argv[1], "A"))
 		return system_run_image_copy(EC_IMAGE_RW);
 	else if (!strcasecmp(argv[1], "B")) {
@@ -1257,7 +1433,7 @@ DECLARE_CONSOLE_COMMAND(sysjump, command_sysjump,
 			"Jump to a system image or address");
 #endif
 
-static int command_reboot(int argc, char **argv)
+static int command_reboot(int argc, const char **argv)
 {
 	int flags = SYSTEM_RESET_MANUALLY_TRIGGERED;
 	int i;
@@ -1276,7 +1452,7 @@ static int command_reboot(int argc, char **argv)
 		} else if (!strcasecmp(argv[i], "ro")) {
 			flags |= SYSTEM_RESET_STAY_IN_RO;
 		} else if (!strcasecmp(argv[i], "cancel")) {
-			reboot_at_shutdown = EC_REBOOT_CANCEL;
+			reboot_at_shutdown.cmd = EC_REBOOT_CANCEL;
 			return EC_SUCCESS;
 		} else if (!strcasecmp(argv[i], "preserve")) {
 			flags |= SYSTEM_RESET_PRESERVE_FLAGS;
@@ -1304,13 +1480,12 @@ DECLARE_CONSOLE_COMMAND(
 	"Reboot the EC");
 
 #ifdef CONFIG_CMD_SYSLOCK
-static int command_system_lock(int argc, char **argv)
+static int command_system_lock(int argc, const char **argv)
 {
 	force_locked = 1;
 	return EC_SUCCESS;
 }
-DECLARE_SAFE_CONSOLE_COMMAND(syslock, command_system_lock,
-			     NULL,
+DECLARE_SAFE_CONSOLE_COMMAND(syslock, command_system_lock, NULL,
 			     "Lock the system, even if WP is disabled");
 #endif
 
@@ -1319,7 +1494,7 @@ DECLARE_SAFE_CONSOLE_COMMAND(syslock, command_system_lock,
  * Modify and print the sleep mask which controls access to deep sleep
  * mode in the idle task.
  */
-static int command_sleepmask(int argc, char **argv)
+static int command_sleepmask(int argc, const char **argv)
 {
 #ifdef CONFIG_CMD_SLEEPMASK_SET
 	int v;
@@ -1341,7 +1516,7 @@ static int command_sleepmask(int argc, char **argv)
 		}
 	}
 #endif
-	ccprintf("sleep mask: %08x\n", sleep_mask);
+	ccprintf("sleep mask: %08x\n", (int)sleep_mask);
 
 	return EC_SUCCESS;
 }
@@ -1351,7 +1526,7 @@ DECLARE_SAFE_CONSOLE_COMMAND(sleepmask, command_sleepmask,
 #endif
 
 #ifdef CONFIG_CMD_JUMPTAGS
-static int command_jumptags(int argc, char **argv)
+static int command_jumptags(int argc, const char **argv)
 {
 	const struct jump_tag *t;
 	int used = 0;
@@ -1365,21 +1540,18 @@ static int command_jumptags(int argc, char **argv)
 		t = (const struct jump_tag *)(system_usable_ram_end() + used);
 		used += sizeof(struct jump_tag) + ROUNDUP4(t->data_size);
 
-		ccprintf("%08x: 0x%04x %c%c.%d %3d\n",
-			 (uintptr_t)t,
-			 t->tag, t->tag >> 8, (uint8_t)t->tag,
-			 t->data_version, t->data_size);
+		ccprintf("%08x: 0x%04x %c%c.%d %3d\n", (uintptr_t)t, t->tag,
+			 t->tag >> 8, (uint8_t)t->tag, t->data_version,
+			 t->data_size);
 	}
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(jumptags, command_jumptags,
-			NULL,
-			"List jump tags");
+DECLARE_CONSOLE_COMMAND(jumptags, command_jumptags, NULL, "List jump tags");
 #endif /* CONFIG_CMD_JUMPTAGS */
 
 #ifdef CONFIG_EMULATED_SYSRQ
-static int command_sysrq(int argc, char **argv)
+static int command_sysrq(int argc, const char **argv)
 {
 	char key = 'x';
 
@@ -1390,20 +1562,18 @@ static int command_sysrq(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(sysrq, command_sysrq,
-			"[key]",
+DECLARE_CONSOLE_COMMAND(sysrq, command_sysrq, "[key]",
 			"Simulate sysrq press (default: x)");
 #endif /* CONFIG_EMULATED_SYSRQ */
 
 #ifdef CONFIG_CMD_RESET_FLAGS
-static int command_rflags(int argc, char **argv)
+static int command_rflags(int argc, const char **argv)
 {
 	print_reset_flags(chip_read_reset_flags());
 	ccprintf("\n");
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(rflags, command_rflags,
-			NULL,
+DECLARE_CONSOLE_COMMAND(rflags, command_rflags, NULL,
 			"Print reset flags saved in non-volatile memory");
 #endif
 
@@ -1413,13 +1583,12 @@ DECLARE_CONSOLE_COMMAND(rflags, command_rflags,
 static enum ec_status
 host_command_get_version(struct host_cmd_handler_args *args)
 {
-	struct ec_response_get_version *r = args->response;
+	struct ec_response_get_version_v1 *r = args->response;
 	enum ec_image active_slot = system_get_active_copy();
 
 	strzcpy(r->version_string_ro, system_get_version(EC_IMAGE_RO),
 		sizeof(r->version_string_ro));
-	strzcpy(r->version_string_rw,
-		system_get_version(active_slot),
+	strzcpy(r->version_string_rw, system_get_version(active_slot),
 		sizeof(r->version_string_rw));
 
 	switch (system_get_image_copy()) {
@@ -1435,13 +1604,38 @@ host_command_get_version(struct host_cmd_handler_args *args)
 		break;
 	}
 
-	args->response_size = sizeof(*r);
+	/*
+	 * Assuming args->response is zero'd in host_command_process, so no need
+	 * to zero uninitialized fields here.
+	 */
+	if (args->version > 0 && IS_ENABLED(CONFIG_CROS_FWID_VERSION)) {
+		if (args->response_max < sizeof(*r))
+			return EC_RES_RESPONSE_TOO_BIG;
+
+		strzcpy(r->cros_fwid_ro, system_get_cros_fwid(EC_IMAGE_RO),
+			sizeof(r->cros_fwid_ro));
+		strzcpy(r->cros_fwid_rw, system_get_cros_fwid(EC_IMAGE_RW),
+			sizeof(r->cros_fwid_rw));
+	}
+
+	/*
+	 * By convention, ec_response_get_version_v1 is a strict superset of
+	 * ec_response_get_version(v0). The v1 response changes the semantics
+	 * of one field (reserved to cros_fwid_ro) and adds one additional field
+	 * (cros_fwid_rw). So simply adjusting the response size here is safe.
+	 */
+	if (args->version == 0)
+		args->response_size = sizeof(struct ec_response_get_version);
+	else if (args->version == 1)
+		args->response_size = sizeof(struct ec_response_get_version_v1);
+	else
+		/* Shouldn't happen because of EC_VER_MASK */
+		return EC_RES_INVALID_VERSION;
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_GET_VERSION,
-		     host_command_get_version,
-		     EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_GET_VERSION, host_command_get_version,
+		     EC_VER_MASK(0) | EC_VER_MASK(1));
 
 #ifdef CONFIG_HOSTCMD_SKUID
 static enum ec_status
@@ -1454,8 +1648,7 @@ host_command_get_sku_id(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_GET_SKU_ID,
-		     host_command_get_sku_id,
+DECLARE_HOST_COMMAND(EC_CMD_GET_SKU_ID, host_command_get_sku_id,
 		     EC_VER_MASK(0));
 #endif
 
@@ -1469,24 +1662,7 @@ host_command_set_sku_id(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_SET_SKU_ID,
-		     host_command_set_sku_id,
-		     EC_VER_MASK(0));
-#endif
-
-#ifdef CONFIG_KEYBOARD_LANGUAGE_ID
-static enum ec_status
-host_command_get_keyboard_id(struct host_cmd_handler_args *args)
-{
-	struct ec_response_keyboard_id *r = args->response;
-
-	r->keyboard_id = keyboard_get_keyboard_id();
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_GET_KEYBOARD_ID,
-		     host_command_get_keyboard_id,
+DECLARE_HOST_COMMAND(EC_CMD_SET_SKU_ID, host_command_set_sku_id,
 		     EC_VER_MASK(0));
 #endif
 
@@ -1498,8 +1674,7 @@ host_command_build_info(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_GET_BUILD_INFO,
-		     host_command_build_info,
+DECLARE_HOST_COMMAND(EC_CMD_GET_BUILD_INFO, host_command_build_info,
 		     EC_VER_MASK(0));
 
 static enum ec_status
@@ -1515,12 +1690,10 @@ host_command_get_chip_info(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_GET_CHIP_INFO,
-		     host_command_get_chip_info,
+DECLARE_HOST_COMMAND(EC_CMD_GET_CHIP_INFO, host_command_get_chip_info,
 		     EC_VER_MASK(0));
 
-#ifdef CONFIG_BOARD_VERSION
-enum ec_status
+static enum ec_status
 host_command_get_board_version(struct host_cmd_handler_args *args)
 {
 	struct ec_response_board_version *r = args->response;
@@ -1537,45 +1710,10 @@ host_command_get_board_version(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_GET_BOARD_VERSION,
-		     host_command_get_board_version,
+DECLARE_HOST_COMMAND(EC_CMD_GET_BOARD_VERSION, host_command_get_board_version,
 		     EC_VER_MASK(0));
-#endif
 
-#ifdef CONFIG_HOSTCMD_VBNV_CONTEXT
-enum ec_status host_command_vbnvcontext(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_vbnvcontext *p = args->params;
-	struct ec_response_vbnvcontext *r;
-	int i;
-
-	switch (p->op) {
-	case EC_VBNV_CONTEXT_OP_READ:
-		r = args->response;
-		for (i = 0; i < EC_VBNV_BLOCK_SIZE; ++i)
-			if (system_get_bbram(SYSTEM_BBRAM_IDX_VBNVBLOCK0 + i,
-					     r->block + i))
-				return EC_RES_ERROR;
-		args->response_size = sizeof(*r);
-		break;
-	case EC_VBNV_CONTEXT_OP_WRITE:
-		for (i = 0; i < EC_VBNV_BLOCK_SIZE; ++i)
-			if (system_set_bbram(SYSTEM_BBRAM_IDX_VBNVBLOCK0 + i,
-					     p->block[i]))
-				return EC_RES_ERROR;
-		break;
-	default:
-		return EC_RES_ERROR;
-	}
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_VBNV_CONTEXT,
-		     host_command_vbnvcontext,
-		     EC_VER_MASK(EC_VER_VBNV_CONTEXT));
-#endif /* CONFIG_HOSTCMD_VBNV_CONTEXT */
-
-enum ec_status host_command_reboot(struct host_cmd_handler_args *args)
+static enum ec_status host_command_reboot(struct host_cmd_handler_args *args)
 {
 	struct ec_params_reboot_ec p;
 
@@ -1587,7 +1725,8 @@ enum ec_status host_command_reboot(struct host_cmd_handler_args *args)
 
 	if (p.cmd == EC_REBOOT_CANCEL) {
 		/* Cancel pending reboot */
-		reboot_at_shutdown = EC_REBOOT_CANCEL;
+		reboot_at_shutdown.cmd = EC_REBOOT_CANCEL;
+		reboot_at_shutdown.flags = 0;
 		return EC_RES_SUCCESS;
 	}
 
@@ -1601,15 +1740,15 @@ enum ec_status host_command_reboot(struct host_cmd_handler_args *args)
 	}
 	if (p.flags & EC_REBOOT_FLAG_ON_AP_SHUTDOWN) {
 		/* Store request for processing at chipset shutdown */
-		reboot_at_shutdown = p.cmd;
+		p.flags &= ~(EC_REBOOT_FLAG_ON_AP_SHUTDOWN);
+		reboot_at_shutdown = p;
 		return EC_RES_SUCCESS;
 	}
 
 #ifdef HAS_TASK_HOSTCMD
-	if (p.cmd == EC_REBOOT_JUMP_RO ||
-	    p.cmd == EC_REBOOT_JUMP_RW ||
-	    p.cmd == EC_REBOOT_COLD ||
-	    p.cmd == EC_REBOOT_HIBERNATE) {
+	if (p.cmd == EC_REBOOT_JUMP_RO || p.cmd == EC_REBOOT_JUMP_RW ||
+	    p.cmd == EC_REBOOT_COLD || p.cmd == EC_REBOOT_HIBERNATE ||
+	    p.cmd == EC_REBOOT_COLD_AP_OFF) {
 		/* Clean busy bits on host for commands that won't return */
 		args->result = EC_RES_SUCCESS;
 		host_send_response(args);
@@ -1617,7 +1756,7 @@ enum ec_status host_command_reboot(struct host_cmd_handler_args *args)
 #endif
 
 	CPRINTS("Executing host reboot command %d", p.cmd);
-	switch (handle_pending_reboot(p.cmd)) {
+	switch (handle_pending_reboot(p)) {
 	case EC_SUCCESS:
 		return EC_RES_SUCCESS;
 	case EC_ERROR_INVAL:
@@ -1628,21 +1767,18 @@ enum ec_status host_command_reboot(struct host_cmd_handler_args *args)
 		return EC_RES_ERROR;
 	}
 }
-DECLARE_HOST_COMMAND(EC_CMD_REBOOT_EC,
-		     host_command_reboot,
-		     EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_REBOOT_EC, host_command_reboot, EC_VER_MASK(0));
 
-int system_can_boot_ap(void)
+test_mockable int system_can_boot_ap(void)
 {
 	int soc = -1;
 	int pow = -1;
 
-#if defined(CONFIG_BATTERY) && \
-	defined(CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON)
+#if defined(CONFIG_BATTERY) && defined(CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON)
 	/* Require a minimum battery level to power on. If battery isn't
 	 * present, battery_state_of_charge_abs returns false. */
 	if (battery_state_of_charge_abs(&soc) == EC_SUCCESS &&
-			soc >= CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON)
+	    soc >= CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON)
 		return 1;
 #endif
 
@@ -1666,7 +1802,7 @@ __overridable const char *board_read_serial(void)
 {
 	if (IS_ENABLED(CONFIG_FLASH_PSTATE) &&
 	    IS_ENABLED(CONFIG_FLASH_PSTATE_BANK))
-		return flash_read_pstate_serial();
+		return crec_flash_read_pstate_serial();
 	else if (IS_ENABLED(CONFIG_OTP))
 		return otp_read_serial();
 	else
@@ -1677,13 +1813,13 @@ __overridable int board_write_serial(const char *serialno)
 {
 	if (IS_ENABLED(CONFIG_FLASH_PSTATE) &&
 	    IS_ENABLED(CONFIG_FLASH_PSTATE_BANK))
-		return flash_write_pstate_serial(serialno);
+		return crec_flash_write_pstate_serial(serialno);
 	else if (IS_ENABLED(CONFIG_OTP))
 		return otp_write_serial(serialno);
 	else
 		return EC_ERROR_UNIMPLEMENTED;
 }
-#endif  /* CONFIG_SERIALNO_LEN */
+#endif /* CONFIG_SERIALNO_LEN */
 
 #ifdef CONFIG_MAC_ADDR_LEN
 /* By default, read MAC address from flash, can be overridden. */
@@ -1691,7 +1827,7 @@ __overridable const char *board_read_mac_addr(void)
 {
 	if (IS_ENABLED(CONFIG_FLASH_PSTATE) &&
 	    IS_ENABLED(CONFIG_FLASH_PSTATE_BANK))
-		return flash_read_pstate_mac_addr();
+		return crec_flash_read_pstate_mac_addr();
 	else
 		return "";
 }
@@ -1701,24 +1837,25 @@ __overridable int board_write_mac_addr(const char *mac_addr)
 {
 	if (IS_ENABLED(CONFIG_FLASH_PSTATE) &&
 	    IS_ENABLED(CONFIG_FLASH_PSTATE_BANK))
-		return flash_write_pstate_mac_addr(mac_addr);
+		return crec_flash_write_pstate_mac_addr(mac_addr);
 	else
 		return EC_ERROR_UNIMPLEMENTED;
 }
-#endif  /* CONFIG_MAC_ADDR_LEN */
-
-__attribute__((weak))
-void clock_enable_module(enum module_id module, int enable)
-{
-	/*
-	 * Default weak implementation - for chips that don't support this
-	 * function.
-	 */
-}
+#endif /* CONFIG_MAC_ADDR_LEN */
 
 __test_only void system_common_reset_state(void)
 {
 	jdata = 0;
 	reset_flags = 0;
 	jumped_to_image = 0;
+	system_info_flags = 0;
+}
+
+__test_only enum ec_reboot_cmd system_common_get_reset_reboot_at_shutdown(void)
+{
+	int ret = reboot_at_shutdown.cmd;
+
+	reboot_at_shutdown.cmd = EC_REBOOT_CANCEL;
+
+	return ret;
 }
diff --git a/common/system_boot_time.c b/common/system_boot_time.c
new file mode 100644
index 0000000000..62ce39be7e
--- /dev/null
+++ b/common/system_boot_time.c
@@ -0,0 +1,96 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "console.h"
+#include "host_command.h"
+#include "system.h"
+#include "util.h"
+
+#include <stdbool.h>
+
+#ifdef CONFIG_SYSTEM_BOOT_TIME_LOGGING
+/* Content of ap_boot_time will be lost on sysjump */
+static struct ec_response_get_boot_time ap_boot_time;
+#endif
+
+/* This function updates timestamp for ap boot time params */
+void update_ap_boot_time(enum boot_time_param param)
+{
+#ifdef CONFIG_SYSTEM_BOOT_TIME_LOGGING
+	static bool ap_booted; /* tracks AP booted after #PLTRST */
+	static bool pltrst_transition; /* tracks #PLTRST transtion */
+
+	if (param > RESET_CNT) {
+		ccprintf("invalid boot_time_param: %d\n", param);
+		return;
+	}
+	if (param < RESET_CNT) {
+		ap_boot_time.timestamp[param] = get_time().val;
+		ccprintf("Boot Time: %d, %llu\n", param,
+			 ap_boot_time.timestamp[param]);
+	}
+
+	/* warm reboot counter set to 1 only when #PLTRST transtion is complete
+	 * and AP is already booted (ap_booted = 1).
+	 * In initial boot or cold reboot scenario (ap_booted = 0) warm reboot
+	 * counter will be set to 0.
+	 */
+	switch (param) {
+	case PLTRST_HIGH:
+		/* warm reboot happened */
+		if (ap_booted && pltrst_transition)
+			ap_boot_time.cnt = 1;
+		else /* cold reboot happened */
+			ap_boot_time.cnt = 0;
+
+		if (pltrst_transition) {
+			ap_booted = true;
+			pltrst_transition = false;
+		}
+		break;
+	case PLTRST_LOW:
+		/* #PLTRST is in transition state */
+		pltrst_transition = true;
+		break;
+	case RESET_CNT:
+		ap_boot_time.cnt = 0;
+
+		if (ap_booted)
+			pltrst_transition = false;
+
+		ap_booted = false;
+		break;
+	default:
+		break;
+	}
+#endif
+}
+
+#ifdef CONFIG_SYSTEM_BOOT_TIME_LOGGING
+/* Returns system boot time data */
+static enum ec_status
+host_command_get_boot_time(struct host_cmd_handler_args *args)
+{
+	struct ec_response_get_boot_time *boot_time = args->response;
+
+	if (args->response_max < sizeof(*boot_time)) {
+		return EC_RES_RESPONSE_TOO_BIG;
+	}
+
+	/* update current time */
+	update_ap_boot_time(EC_CUR_TIME);
+
+	/* copy data from ap_boot_time struct */
+	memcpy(boot_time, &ap_boot_time, sizeof(*boot_time));
+
+	args->response_size = sizeof(*boot_time);
+
+	return EC_RES_SUCCESS;
+}
+
+DECLARE_HOST_COMMAND(EC_CMD_GET_BOOT_TIME, host_command_get_boot_time,
+		     EC_VER_MASK(0));
+#endif
diff --git a/common/system_safe_mode.c b/common/system_safe_mode.c
new file mode 100644
index 0000000000..33be2622f5
--- /dev/null
+++ b/common/system_safe_mode.c
@@ -0,0 +1,186 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "console.h"
+#include "cpu.h"
+#include "ec_commands.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "panic.h"
+#include "stddef.h"
+#include "system.h"
+#include "system_safe_mode.h"
+#include "task.h"
+#include "timer.h"
+#include "watchdog.h"
+
+#define STACK_PRINT_SIZE_WORDS 32
+
+#define CANNOT_ENTER_SAFE_MODE_FMT "Cannot start SSM: %s\n"
+
+static bool in_safe_mode;
+
+static const int safe_mode_allowed_hostcmds[] = {
+	EC_CMD_CONSOLE_READ,
+	EC_CMD_CONSOLE_SNAPSHOT,
+	EC_CMD_GET_NEXT_EVENT,
+	EC_CMD_GET_PANIC_INFO,
+	EC_CMD_GET_PROTOCOL_INFO,
+	EC_CMD_GET_UPTIME_INFO,
+	EC_CMD_GET_VERSION,
+	EC_CMD_MEMORY_DUMP_GET_ENTRY_INFO,
+	EC_CMD_MEMORY_DUMP_GET_METADATA,
+	EC_CMD_MEMORY_DUMP_READ_MEMORY,
+	EC_CMD_SYSINFO,
+};
+
+bool is_task_safe_mode_critical(task_id_t task_id)
+{
+	const task_id_t safe_mode_critical_tasks[] = {
+#ifdef HAS_TASK_HOOKS
+		TASK_ID_HOOKS,
+#endif
+		TASK_ID_IDLE,
+#ifdef HAS_TASK_HOSTCMD
+		TASK_ID_HOSTCMD,
+#endif
+#ifdef HAS_TASK_MAIN
+		TASK_ID_MAIN,
+#endif
+#ifdef HAS_TASK_SYSWORKQ
+		TASK_ID_SYSWORKQ,
+#endif
+	};
+	for (int i = 0; i < ARRAY_SIZE(safe_mode_critical_tasks); i++)
+		if (safe_mode_critical_tasks[i] == task_id)
+			return true;
+	return false;
+}
+
+bool is_current_task_safe_mode_critical(void)
+{
+	return is_task_safe_mode_critical(task_get_current());
+}
+
+#ifndef CONFIG_ZEPHYR
+
+int disable_non_safe_mode_critical_tasks(void)
+{
+	for (task_id_t task_id = 0; task_id < TASK_ID_COUNT; task_id++) {
+		/* Do not disable current task,
+		 * that is the responsibility of the panic handler.
+		 * If the current task is disabled while outside an interrupt
+		 * context, execution will halt.
+		 */
+		if (!is_task_safe_mode_critical(task_id) &&
+		    task_id != task_get_current())
+			task_disable_task(task_id);
+	}
+	return EC_SUCCESS;
+}
+
+#endif /* CONFIG_ZEPHYR */
+
+void handle_system_safe_mode_timeout(void)
+{
+	panic_printf("SSM timeout\n");
+	panic_reboot();
+}
+DECLARE_DEFERRED(handle_system_safe_mode_timeout);
+
+bool system_is_in_safe_mode(void)
+{
+	return !!in_safe_mode;
+}
+
+/*
+ * Print contents of stack to console buffer.
+ */
+static void print_panic_stack(void)
+{
+	uint32_t sp;
+	const struct panic_data *pdata = panic_get_data();
+
+	ccprintf("\nStack Contents");
+	sp = get_panic_stack_pointer(pdata);
+	for (int i = 0; i < STACK_PRINT_SIZE_WORDS; i++) {
+		if (sp == 0 ||
+		    sp + sizeof(uint32_t) > CONFIG_RAM_BASE + CONFIG_RAM_SIZE) {
+			ccprintf("\nSP(%x) out of range", sp);
+			break;
+		}
+		if (i % 4 == 0)
+			ccprintf("\n%08x:", sp);
+		ccprintf(" %08x", *(uint32_t *)sp);
+		sp += sizeof(uint32_t);
+	}
+	ccprintf("\n");
+	/* Flush so dump isn't mixed with other output */
+	cflush();
+}
+
+bool command_is_allowed_in_safe_mode(int command)
+{
+	for (int i = 0; i < ARRAY_SIZE(safe_mode_allowed_hostcmds); i++)
+		if (command == safe_mode_allowed_hostcmds[i])
+			return true;
+	return false;
+}
+
+static void system_safe_mode_start(void)
+{
+	ccprintf("Post Panic SSM\n");
+	if (IS_ENABLED(CONFIG_SYSTEM_SAFE_MODE_PRINT_STACK))
+		print_panic_stack();
+	if (IS_ENABLED(CONFIG_HOSTCMD_EVENTS))
+		host_set_single_event(EC_HOST_EVENT_PANIC);
+}
+DECLARE_DEFERRED(system_safe_mode_start);
+
+int start_system_safe_mode(void)
+{
+	if (!system_is_in_rw()) {
+		panic_printf(CANNOT_ENTER_SAFE_MODE_FMT, "RO image");
+		return EC_ERROR_INVAL;
+	}
+
+	if (system_is_in_safe_mode()) {
+		panic_printf(CANNOT_ENTER_SAFE_MODE_FMT, "Already in SSM");
+		return EC_ERROR_INVAL;
+	}
+
+	if (is_current_task_safe_mode_critical()) {
+		/* TODO: Restart critical tasks */
+		panic_printf(CANNOT_ENTER_SAFE_MODE_FMT,
+			     "Panic in critical task");
+		return EC_ERROR_INVAL;
+	}
+
+	hook_call_deferred(&handle_system_safe_mode_timeout_data,
+			   CONFIG_SYSTEM_SAFE_MODE_TIMEOUT_MSEC * MSEC);
+
+	/*
+	 * Schedule a deferred function to run immediately
+	 * after returning from fault handler. Defer operations that
+	 * must not run in an ISR to this function.
+	 */
+	hook_call_deferred(&system_safe_mode_start_data, 0);
+
+	disable_non_safe_mode_critical_tasks();
+
+	in_safe_mode = true;
+
+	panic_printf("Starting SSM\n");
+
+	return EC_SUCCESS;
+}
+
+#ifdef TEST_BUILD
+void set_system_safe_mode(bool mode)
+{
+	in_safe_mode = mode;
+}
+#endif
diff --git a/common/tablet_mode.c b/common/tablet_mode.c
index 5486ffc668..1fdf698a1d 100644
--- a/common/tablet_mode.c
+++ b/common/tablet_mode.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,18 +9,25 @@
 #include "hooks.h"
 #include "host_command.h"
 #include "lid_angle.h"
+#include "lid_switch.h"
 #include "stdbool.h"
 #include "tablet_mode.h"
 #include "timer.h"
 
-#define CPRINTS(format, args...) cprints(CC_MOTION_LID, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_MOTION_LID, format, ## args)
+#include <string.h>
+
+#define CPRINTS(format, args...) cprints(CC_MOTION_LID, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_MOTION_LID, format, ##args)
 
 /*
- * Other code modules assume that notebook mode (i.e. tablet_mode = false) at
- * startup
+ * Other code modules assume that notebook mode (i.e. tablet_mode = 0) at
+ * startup.
+ * tablet_mode is mask, one bit for each source that can trigger a change to
+ * tablet mode:
+ * - TABLET_TRIGGER_LID: the lid angle is over the threshold.
+ * - TABLET_TRIGGER_BASE: the detachable keyboard is disconnected.
  */
-static bool tablet_mode;
+static uint32_t tablet_mode;
 
 /*
  * Console command can force the value of tablet_mode. If tablet_mode_force is
@@ -28,8 +35,17 @@ static bool tablet_mode;
  */
 static bool tablet_mode_forced;
 
-/* True if GMR sensor is reporting 360 degrees. */
-static bool gmr_sensor_at_360;
+/*
+ * Console command can force the value of tablet_mode. If tablet_mode_force is
+ * false, use stored tablet mode value before it was (possibly) overridden.
+ */
+static uint32_t tablet_mode_store;
+
+/* True if the tablet GMR sensor is reporting 360 degrees. */
+STATIC_IF(CONFIG_GMR_TABLET_MODE) bool gmr_sensor_at_360;
+
+/* True if the lid GMR sensor is reporting 0 degrees. */
+STATIC_IF(CONFIG_GMR_TABLET_MODE) bool gmr_sensor_at_0;
 
 /*
  * True: all calls to tablet_set_mode are ignored and tablet_mode if forced to 0
@@ -37,14 +53,25 @@ static bool gmr_sensor_at_360;
  */
 static bool disabled;
 
+static const char *const tablet_mode_names[] = {
+	"clamshell",
+	"tablet",
+};
+BUILD_ASSERT(ARRAY_SIZE(tablet_mode_names) == 2);
+
 int tablet_get_mode(void)
 {
-	return tablet_mode;
+	return !!tablet_mode;
+}
+
+static inline void print_tablet_mode(void)
+{
+	CPRINTS("%s mode", tablet_mode_names[tablet_get_mode()]);
 }
 
 static void notify_tablet_mode_change(void)
 {
-	CPRINTS("tablet mode %sabled", tablet_mode ? "en" : "dis");
+	print_tablet_mode();
 	hook_notify(HOOK_TABLET_MODE_CHANGE);
 
 	/*
@@ -53,53 +80,98 @@ static void notify_tablet_mode_change(void)
 	 */
 	if (IS_ENABLED(CONFIG_HOSTCMD_EVENTS))
 		host_set_single_event(EC_HOST_EVENT_MODE_CHANGE);
-
 }
 
-void tablet_set_mode(int mode)
+void tablet_set_mode(int mode, uint32_t trigger)
 {
-	/* If tablet_mode is forced via a console command, ignore set. */
-	if (tablet_mode_forced)
-		return;
+	uint32_t new_mode = tablet_mode_forced ? tablet_mode_store :
+						 tablet_mode;
+	uint32_t old_mode = 0;
 
-	if (tablet_mode == !!mode)
+	if (disabled) {
+		/*
+		 * If tablet mode is being forced by the user, then this logging
+		 * would be misleading since the mode wouldn't change anyway, so
+		 * skip it.
+		 */
+		if (!tablet_mode_forced)
+			CPRINTS("Tablet mode set while disabled (ignoring)!");
 		return;
+	}
 
-	if (disabled) {
-		CPRINTS("Tablet mode set while disabled (ignoring)!");
+	if (IS_ENABLED(CONFIG_GMR_TABLET_MODE) &&
+	    ((gmr_sensor_at_360 && !mode) || (gmr_sensor_at_0 && mode))) {
+		/*
+		 * If tablet mode is being forced by the user, then this logging
+		 * would be misleading since the mode wouldn't change anyway, so
+		 * skip it.
+		 */
+		if (!tablet_mode_forced)
+			CPRINTS("Ignoring %s mode entry while gmr sensors "
+				"reports lid %s",
+				tablet_mode_names[mode],
+				(gmr_sensor_at_360 ? "flipped" : "closed"));
 		return;
 	}
 
-	if (gmr_sensor_at_360 && !mode) {
-		CPRINTS("Ignoring tablet mode exit while gmr sensor "
-			"reports 360-degree tablet mode.");
+	if (mode)
+		new_mode |= trigger;
+	else
+		new_mode &= ~trigger;
+
+	if (tablet_mode_forced) {
+		/*
+		 * Save the current mode based on the HW orientation, so we
+		 * apply the correct mode if tablet mode no longer forced in the
+		 * future. Don't notify of the tablet mode change yet, since
+		 * that will be done as part of handling 'tabletmode reset'.
+		 */
+		tablet_mode_store = new_mode;
 		return;
 	}
 
-	tablet_mode = !!mode;
+	old_mode = tablet_mode;
+	tablet_mode = new_mode;
+
+	/* Boolean comparison */
+	if (!tablet_mode == !old_mode)
+		return;
 
 	notify_tablet_mode_change();
 }
 
 void tablet_disable(void)
 {
-	tablet_mode = false;
+	bool need_to_notify = false;
+
+	/* Already disabled, nothing to do. */
+	if (disabled)
+		return;
+
 	disabled = true;
+	/*
+	 * We may have already transition to tablet mode:
+	 * At board init time, while the sensors are not running yet, we may
+	 * have read the Tablet GMR GPIO already, and transitioned to tablet
+	 * mode, especially if the GMR is not stuffed and the GPIO is floating.
+	 */
+	if (tablet_get_mode())
+		need_to_notify = true;
+	tablet_mode = 0;
+	if (need_to_notify)
+		notify_tablet_mode_change();
 }
 
 /* This ifdef can be removed once we clean up past projects which do own init */
 #ifdef CONFIG_GMR_TABLET_MODE
-#ifndef GMR_TABLET_MODE_GPIO_L
-#error  GMR_TABLET_MODE_GPIO_L must be defined
-#endif
 #ifdef CONFIG_DPTF_MOTION_LID_NO_GMR_SENSOR
 #error The board has GMR sensor
 #endif
 static void gmr_tablet_switch_interrupt_debounce(void)
 {
-	gmr_sensor_at_360 = IS_ENABLED(CONFIG_GMR_TABLET_MODE_CUSTOM)
-				     ? board_sensor_at_360()
-				     : !gpio_get_level(GMR_TABLET_MODE_GPIO_L);
+	gmr_sensor_at_360 = IS_ENABLED(CONFIG_GMR_TABLET_MODE_CUSTOM) ?
+				    board_sensor_at_360() :
+				    !gpio_get_level(GPIO_TABLET_MODE_L);
 
 	/*
 	 * DPTF table is updated only when the board enters/exits completely
@@ -108,10 +180,18 @@ static void gmr_tablet_switch_interrupt_debounce(void)
 	 * calculation and update DPTF table when lid angle > 300 degrees.
 	 */
 	if (IS_ENABLED(CONFIG_HOSTCMD_X86) && IS_ENABLED(CONFIG_DPTF)) {
-		acpi_dptf_set_profile_num(gmr_sensor_at_360 ?
-					  DPTF_PROFILE_FLIPPED_360_MODE :
-					  DPTF_PROFILE_CLAMSHELL);
+		acpi_dptf_set_profile_num(
+			gmr_sensor_at_360 ? DPTF_PROFILE_FLIPPED_360_MODE :
+					    DPTF_PROFILE_CLAMSHELL);
 	}
+
+	/*
+	 * When tablet mode is only decided by the GMR sensor (or
+	 * or substitute, send the tablet_mode change request.
+	 */
+	if (!IS_ENABLED(CONFIG_LID_ANGLE))
+		tablet_set_mode(gmr_sensor_at_360, TABLET_TRIGGER_LID);
+
 	/*
 	 * 1. Peripherals are disabled only when lid reaches 360 position (It's
 	 * probably already disabled by motion_sense task). We deliberately do
@@ -123,18 +203,37 @@ static void gmr_tablet_switch_interrupt_debounce(void)
 	 * deliberately do not clear tablet mode when lid is leaving 360
 	 * position(if motion lid driver is used). Instead, we let motion lid
 	 * driver to clear it when lid goes into laptop zone.
+	 * 3. However, there is a potential race condition with
+	 * tablet_mode_lid_event() which can be triggered before this debounce
+	 * function is called, with |gmr_sensor_at_360| still true.
+	 * When we notice the lid is closed when the this function is called and
+	 * |gmr_sensor_at_360| false, send a transition to go in clamshell mode.
+	 * It would mean the user was able to transition in less than ~10ms...
 	 */
-
-	if (!IS_ENABLED(CONFIG_LID_ANGLE) || gmr_sensor_at_360)
-		tablet_set_mode(gmr_sensor_at_360);
+	if (IS_ENABLED(CONFIG_LID_ANGLE)) {
+		if (gmr_sensor_at_360)
+			tablet_set_mode(1, TABLET_TRIGGER_LID);
+		else if (gmr_sensor_at_0)
+			tablet_set_mode(0, TABLET_TRIGGER_LID);
+	}
 
 	if (IS_ENABLED(CONFIG_LID_ANGLE_UPDATE) && gmr_sensor_at_360)
 		lid_angle_peripheral_enable(0);
 }
 DECLARE_DEFERRED(gmr_tablet_switch_interrupt_debounce);
 
-/* Debounce time for gmr sensor tablet mode interrupt */
-#define GMR_SENSOR_DEBOUNCE_US    (30 * MSEC)
+/*
+ * Debounce time for gmr sensor tablet mode interrupt
+ * There could be a race between the GMR sensor for the tablet and
+ * the GMR sensor for the lid changes state at the same time.
+ * We let the lid sensor GMR debouce first. We would be able to go in tablet
+ * mode when LID_OPEN goes from low to high and TABLET_MODE_L goes from high
+ * to low.
+ * However, in the opposite case, the debouce lid angle interrupt will request
+ * the tablet_mode to be clamshell, but |gmr_sensor_at_360| will still be true,
+ * the request will be ignored.
+ */
+#define GMR_SENSOR_DEBOUNCE_US (LID_DEBOUNCE_US + 10 * MSEC)
 
 void gmr_tablet_switch_isr(enum gpio_signal signal)
 {
@@ -142,42 +241,113 @@ void gmr_tablet_switch_isr(enum gpio_signal signal)
 			   GMR_SENSOR_DEBOUNCE_US);
 }
 
+/*
+ * tablet gmr sensor() calls tablet_set_mode() to go in tablet mode
+ * when we know for sure the tablet is in tablet mode,
+ *
+ * It would call tablet_set_mode() to get out only when there are not
+ * accelerometer, as we want to get out at ~180 degree.
+ * But if for some reason the accelerometers are not working, we won't get
+ * out of tablet mode. Therefore, we need a similar function to go in
+ * clamshell mode when the lid is closed.
+ */
+static __maybe_unused void tablet_mode_lid_event(void)
+{
+	if (!lid_is_open()) {
+		gmr_sensor_at_0 = true;
+		tablet_set_mode(0, TABLET_TRIGGER_LID);
+		if (IS_ENABLED(CONFIG_LID_ANGLE_UPDATE))
+			lid_angle_peripheral_enable(1);
+	} else {
+		gmr_sensor_at_0 = false;
+	}
+}
+#if defined(CONFIG_LID_ANGLE) && defined(CONFIG_LID_SWITCH)
+DECLARE_HOOK(HOOK_LID_CHANGE, tablet_mode_lid_event, HOOK_PRIO_DEFAULT);
+#endif
+
 static void gmr_tablet_switch_init(void)
 {
 	/* If this sub-system was disabled before initializing, honor that. */
 	if (disabled)
 		return;
 
-	gpio_enable_interrupt(GMR_TABLET_MODE_GPIO_L);
+	gpio_enable_interrupt(GPIO_TABLET_MODE_L);
 	/*
 	 * Ensure tablet mode is initialized according to the hardware state
 	 * so that the cached state reflects reality.
 	 */
 	gmr_tablet_switch_interrupt_debounce();
+	if (IS_ENABLED(CONFIG_LID_ANGLE) && IS_ENABLED(CONFIG_LID_SWITCH))
+		tablet_mode_lid_event();
 }
-DECLARE_HOOK(HOOK_INIT, gmr_tablet_switch_init, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_INIT, gmr_tablet_switch_init, HOOK_PRIO_POST_LID);
 
 void gmr_tablet_switch_disable(void)
 {
-	gpio_disable_interrupt(GMR_TABLET_MODE_GPIO_L);
+	gpio_disable_interrupt(GPIO_TABLET_MODE_L);
 	/* Cancel any pending debounce calls */
 	hook_call_deferred(&gmr_tablet_switch_interrupt_debounce_data, -1);
 	tablet_disable();
 }
-#endif
+#endif /* CONFIG_GMR_TABLET_MODE */
+
+static enum ec_status tablet_mode_command(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_set_tablet_mode *p = args->params;
+
+	if (tablet_mode_forced == false)
+		tablet_mode_store = tablet_mode;
+
+	switch (p->tablet_mode) {
+	case TABLET_MODE_DEFAULT:
+		tablet_mode = tablet_mode_store;
+		tablet_mode_forced = false;
+		break;
+	case TABLET_MODE_FORCE_TABLET:
+		tablet_mode = TABLET_TRIGGER_LID;
+		tablet_mode_forced = true;
+		break;
+	case TABLET_MODE_FORCE_CLAMSHELL:
+		tablet_mode = 0;
+		tablet_mode_forced = true;
+		break;
+	default:
+		CPRINTS("Invalid EC_CMD_SET_TABLET_MODE parameter: %d",
+			p->tablet_mode);
+		return EC_RES_INVALID_PARAM;
+	}
+
+	notify_tablet_mode_change();
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_SET_TABLET_MODE, tablet_mode_command,
+		     EC_VER_MASK(0) | EC_VER_MASK(1));
 
-static int command_settabletmode(int argc, char **argv)
+#ifdef CONFIG_TABLET_MODE
+static int command_settabletmode(int argc, const char **argv)
 {
+	if (argc == 1) {
+		print_tablet_mode();
+		return EC_SUCCESS;
+	}
+
 	if (argc != 2)
 		return EC_ERROR_PARAM_COUNT;
 
-	if (argv[1][0] == 'o' && argv[1][1] == 'n') {
-		tablet_mode = true;
+	if (tablet_mode_forced == false)
+		tablet_mode_store = tablet_mode;
+
+	/* |+1| to also make sure the strings the same length. */
+	if (strncmp(argv[1], "on", strlen("on") + 1) == 0) {
+		tablet_mode = TABLET_TRIGGER_LID;
 		tablet_mode_forced = true;
-	} else if (argv[1][0] == 'o' && argv[1][1] == 'f') {
-		tablet_mode = false;
+	} else if (strncmp(argv[1], "off", strlen("off") + 1) == 0) {
+		tablet_mode = 0;
 		tablet_mode_forced = true;
-	} else if (argv[1][0] == 'r') {
+	} else if (strncmp(argv[1], "reset", strlen("reset") + 1) == 0) {
+		tablet_mode = tablet_mode_store;
 		tablet_mode_forced = false;
 	} else {
 		return EC_ERROR_PARAM1;
@@ -186,6 +356,13 @@ static int command_settabletmode(int argc, char **argv)
 	notify_tablet_mode_change();
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(tabletmode, command_settabletmode,
-	"[on | off | reset]",
-	"Manually force tablet mode to on, off or reset.");
+DECLARE_CONSOLE_COMMAND(tabletmode, command_settabletmode, "[on | off | reset]",
+			"Manually force tablet mode to on, off or reset.");
+#endif
+
+__test_only void tablet_reset(void)
+{
+	tablet_mode = 0;
+	tablet_mode_forced = false;
+	disabled = false;
+}
diff --git a/common/temp_sensor.c b/common/temp_sensor.c
index 0f687bb2a2..ccd9b3bc26 100644
--- a/common/temp_sensor.c
+++ b/common/temp_sensor.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,6 +15,11 @@
 #include "timer.h"
 #include "util.h"
 
+#ifdef CONFIG_ZEPHYR
+#include "temp_sensor/temp_sensor.h"
+#endif
+
+#ifndef CONFIG_ZEPHYR
 int temp_sensor_read(enum temp_sensor_id id, int *temp_ptr)
 {
 	const struct temp_sensor_t *sensor;
@@ -25,6 +30,7 @@ int temp_sensor_read(enum temp_sensor_id id, int *temp_ptr)
 
 	return sensor->read(sensor->idx, temp_ptr);
 }
+#endif
 
 static void update_mapped_memory(void)
 {
@@ -38,8 +44,7 @@ static void update_mapped_memory(void)
 		 */
 		if (i == EC_TEMP_SENSOR_ENTRIES)
 			mptr = host_get_memmap(EC_MEMMAP_TEMP_SENSOR_B);
-		else if (i >= EC_TEMP_SENSOR_ENTRIES +
-			 EC_TEMP_SENSOR_B_ENTRIES)
+		else if (i >= EC_TEMP_SENSOR_ENTRIES + EC_TEMP_SENSOR_B_ENTRIES)
 			break;
 
 		switch (temp_sensor_read(i, &t)) {
@@ -94,31 +99,30 @@ static void temp_sensor_init(void)
 }
 DECLARE_HOOK(HOOK_INIT, temp_sensor_init, HOOK_PRIO_DEFAULT);
 
-/*****************************************************************************/
-/* Console commands */
-
-static int command_temps(int argc, char **argv)
+int print_temps(void)
 {
 	int t, i;
 	int rv, rv1 = EC_SUCCESS;
 
 	for (i = 0; i < TEMP_SENSOR_COUNT; ++i) {
-		ccprintf("  %-20s: ", temp_sensors[i].name);
+		ccprintf("  %-20s  ", temp_sensors[i].name);
 		rv = temp_sensor_read(i, &t);
 		if (rv)
 			rv1 = rv;
 
 		switch (rv) {
 		case EC_SUCCESS:
-			ccprintf("%d K = %d C", t, K_TO_C(t));
+			ccprintf("%d K (= %d C)", t, K_TO_C(t));
 #ifdef CONFIG_THROTTLE_AP
 			if (thermal_params[i].temp_fan_off &&
 			    thermal_params[i].temp_fan_max)
-				ccprintf("  %d%%",
+				ccprintf("  %11d%% (%d K and %d K)",
 					 thermal_fan_percent(
 						 thermal_params[i].temp_fan_off,
 						 thermal_params[i].temp_fan_max,
-						 t));
+						 t),
+					 thermal_params[i].temp_fan_off,
+					 thermal_params[i].temp_fan_max);
 #endif
 			ccprintf("\n");
 			break;
@@ -135,14 +139,24 @@ static int command_temps(int argc, char **argv)
 
 	return rv1;
 }
-DECLARE_CONSOLE_COMMAND(temps, command_temps,
-			NULL,
-			"Print temp sensors");
+
+/*****************************************************************************/
+/* Console commands */
+
+#ifdef CONFIG_CMD_TEMP_SENSOR
+static int command_temps(int argc, const char **argv)
+{
+	return print_temps();
+}
+DECLARE_CONSOLE_COMMAND(temps, command_temps, NULL,
+			"Print temp sensors and temp ratio.");
+#endif
 
 /*****************************************************************************/
 /* Host commands */
 
-enum ec_status temp_sensor_command_get_info(struct host_cmd_handler_args *args)
+static enum ec_status
+temp_sensor_command_get_info(struct host_cmd_handler_args *args)
 {
 	const struct ec_params_temp_sensor_get_info *p = args->params;
 	struct ec_response_temp_sensor_get_info *r = args->response;
@@ -158,6 +172,5 @@ enum ec_status temp_sensor_command_get_info(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_TEMP_SENSOR_GET_INFO,
-		     temp_sensor_command_get_info,
+DECLARE_HOST_COMMAND(EC_CMD_TEMP_SENSOR_GET_INFO, temp_sensor_command_get_info,
 		     EC_VER_MASK(0));
diff --git a/common/test_util.c b/common/test_util.c
index 704fa1d018..9316b36bf1 100644
--- a/common/test_util.c
+++ b/common/test_util.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,6 +19,8 @@
 #include "test_util.h"
 #include "util.h"
 
+#include <assert.h>
+
 struct test_util_tag {
 	uint8_t error_count;
 };
@@ -29,23 +31,42 @@ struct test_util_tag {
 int __test_error_count;
 
 /* Weak reference function as an entry point for unit test */
-test_mockable void run_test(int argc, char **argv) { }
+test_mockable void run_test(int argc, const char **argv)
+{
+	/* This function should always be replaced by a real implementation of
+	 * run_test().
+	 * If this assertion is failing, it means your test was not linked
+	 * correctly. Check the signature of run_test() defined in your test
+	 * matches the one above.
+	 */
+	ccprintf("%s:%d: ASSERTION failed: ran weakly linked fallback test\n",
+		 __FILE__, __LINE__);
+	assert(0);
+}
 
 /* Default mock test init */
-test_mockable void test_init(void) { }
+test_mockable void test_init(void)
+{
+}
 
 /* Default mock before test */
-test_mockable void before_test(void) { }
+test_mockable void before_test(void)
+{
+}
 
 /* Default mock after test */
-test_mockable void after_test(void) { }
+test_mockable void after_test(void)
+{
+}
 
 #ifdef TEST_COVERAGE
-extern void __gcov_flush(void);
+extern void __gcov_dump(void);
+extern void __gcov_reset(void);
 
 void emulator_flush(void)
 {
-	__gcov_flush();
+	__gcov_dump();
+	__gcov_reset();
 }
 #else
 void emulator_flush(void)
@@ -102,18 +123,26 @@ int test_get_error_count(void)
 
 uint32_t test_get_state(void)
 {
-	return system_get_scratchpad();
+	uint32_t state;
+
+	system_get_scratchpad(&state);
+	return state;
 }
 
 test_mockable void test_clean_up(void)
 {
 }
 
+void test_set_next_step(enum test_state_t step)
+{
+	system_set_scratchpad(TEST_STATE_MASK(step));
+}
+
 void test_reboot_to_next_step(enum test_state_t step)
 {
 	ccprintf("Rebooting to next test step...\n");
 	cflush();
-	system_set_scratchpad(TEST_STATE_MASK(step));
+	test_set_next_step(step);
 	system_reset(SYSTEM_RESET_HARD);
 }
 
@@ -144,8 +173,9 @@ void test_run_multistep(void)
 }
 
 #ifdef HAS_TASK_HOSTCMD
-int test_send_host_command(int command, int version, const void *params,
-			   int params_size, void *resp, int resp_size)
+enum ec_status test_send_host_command(int command, int version,
+				      const void *params, int params_size,
+				      void *resp, int resp_size)
 {
 	struct host_cmd_handler_args args;
 
@@ -159,7 +189,7 @@ int test_send_host_command(int command, int version, const void *params,
 
 	return host_command_process(&args);
 }
-#endif  /* TASK_HAS_HOSTCMD */
+#endif /* TASK_HAS_HOSTCMD */
 
 /* Linear congruential pseudo random number generator */
 uint32_t prng(uint32_t seed)
@@ -180,8 +210,7 @@ static void restore_state(void)
 
 	tag = (const struct test_util_tag *)system_get_jump_tag(
 		TEST_UTIL_SYSJUMP_TAG, &version, &size);
-	if (tag && version == TEST_UTIL_SYSJUMP_VERSION &&
-	    size == sizeof(*tag))
+	if (tag && version == TEST_UTIL_SYSJUMP_VERSION && size == sizeof(*tag))
 		__test_error_count = tag->error_count;
 	else
 		__test_error_count = 0;
@@ -197,10 +226,30 @@ static void preserve_state(void)
 }
 DECLARE_HOOK(HOOK_SYSJUMP, preserve_state, HOOK_PRIO_DEFAULT);
 
-static int command_run_test(int argc, char **argv)
+static int command_run_test(int argc, const char **argv)
 {
 	run_test(argc, argv);
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(runtest, command_run_test,
-			NULL, NULL);
+DECLARE_CONSOLE_COMMAND(runtest, command_run_test, NULL, NULL);
+
+#ifndef CONFIG_ZEPHYR
+void z_ztest_run_test_suite(const char *name, struct unit_test *suite)
+{
+	test_reset();
+
+	while (suite->test) {
+		suite->setup();
+		RUN_TEST(suite->test);
+		suite->teardown();
+		suite++;
+	}
+
+	/* Sometimes the console task doesn't start until the test is done. */
+	sleep(1);
+
+	ccprintf("%s: ", name);
+
+	test_print_result();
+}
+#endif /* CONFIG_ZEPHYR */
diff --git a/common/thermal.c b/common/thermal.c
index d1cc47e924..89c145556e 100644
--- a/common/thermal.c
+++ b/common/thermal.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,15 +19,31 @@
 #include "timer.h"
 #include "util.h"
 
+#ifdef CONFIG_ZEPHYR
+#include "temp_sensor/temp_sensor.h"
+#endif
+
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_THERMAL, outstr)
-#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
 
 /*****************************************************************************/
 /* EC-specific thermal controls */
 
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+__overridable int board_temp_smi_evet(void)
+{
+	/* Do nothing by default. Boards can modify the temps condition */
+	return true;
+}
+#endif
+
 test_mockable_static void smi_sensor_failure_warning(void)
 {
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+	if (!board_temp_smi_evet())
+		return;
+#endif
 	CPRINTS("can't read any temp sensors!");
 	host_set_single_event(EC_HOST_EVENT_THERMAL);
 }
@@ -48,36 +64,54 @@ BUILD_ASSERT(EC_TEMP_THRESH_COUNT == 3);
 
 /* Keep track of which thresholds have triggered */
 static cond_t cond_hot[EC_TEMP_THRESH_COUNT];
+#ifdef CONFIG_PLATFORM_EC_CUSTOMIZED_DESIGN
+static bool thermal_warn_active;
+#endif
+
+/* thermal sensor read delay */
+#if defined(CONFIG_TEMP_SENSOR_POWER) && \
+	defined(CONFIG_TEMP_SENSOR_FIRST_READ_DELAY_MS)
+static int first_read_delay = CONFIG_TEMP_SENSOR_FIRST_READ_DELAY_MS;
+#endif
 
 static void thermal_control(void)
 {
-	int i, j, t, rv, f;
+	int i, j, t, rv;
 	int count_over[EC_TEMP_THRESH_COUNT];
 	int count_under[EC_TEMP_THRESH_COUNT];
 	int num_valid_limits[EC_TEMP_THRESH_COUNT];
 	int num_sensors_read;
-	int fmax;
-	int temp_fan_configured;
-
-#ifdef CONFIG_CUSTOM_FAN_CONTROL
+#ifdef CONFIG_FANS
+#ifndef CONFIG_CUSTOM_FAN_CONTROL
+	int f = 0;
+	int fmax = 0;
+	int temp_fan_configured = 0;
+#else
 	int temp[TEMP_SENSOR_COUNT];
 #endif
+#endif
+
+	/* add delay to ensure thermal sensor is ready when EC boot */
+#if defined(CONFIG_TEMP_SENSOR_POWER) && \
+	defined(CONFIG_TEMP_SENSOR_FIRST_READ_DELAY_MS)
+	if (first_read_delay != 0) {
+		msleep(first_read_delay);
+		first_read_delay = 0;
+	}
+#endif
 
 	/* Get ready to count things */
 	memset(count_over, 0, sizeof(count_over));
 	memset(count_under, 0, sizeof(count_under));
 	memset(num_valid_limits, 0, sizeof(num_valid_limits));
 	num_sensors_read = 0;
-	fmax = 0;
-	temp_fan_configured = 0;
 
 	/* go through all the sensors */
 	for (i = 0; i < TEMP_SENSOR_COUNT; ++i) {
-
 		/* read one */
 		rv = temp_sensor_read(i, &t);
 
-#ifdef CONFIG_CUSTOM_FAN_CONTROL
+#if defined(CONFIG_FANS) && defined(CONFIG_CUSTOM_FAN_CONTROL)
 		/* Store all sensors value */
 		temp[i] = K_TO_C(t);
 #endif
@@ -104,6 +138,8 @@ static void thermal_control(void)
 			}
 		}
 
+#ifdef CONFIG_FANS
+#ifndef CONFIG_CUSTOM_FAN_CONTROL
 		/* figure out the max fan needed, too */
 		if (thermal_params[i].temp_fan_off &&
 		    thermal_params[i].temp_fan_max) {
@@ -115,6 +151,8 @@ static void thermal_control(void)
 
 			temp_fan_configured = 1;
 		}
+#endif
+#endif
 	}
 
 	if (!num_sensors_read) {
@@ -156,6 +194,13 @@ static void thermal_control(void)
 
 	if (cond_went_true(&cond_hot[EC_TEMP_THRESH_HALT])) {
 		CPRINTS("thermal SHUTDOWN");
+
+		/* Print temperature sensor values before shutting down AP */
+		if (IS_ENABLED(CONFIG_CMD_TEMP_SENSOR)) {
+			print_temps();
+			cflush();
+		}
+
 		chipset_force_shutdown(CHIPSET_SHUTDOWN_THERMAL);
 	} else if (cond_went_false(&cond_hot[EC_TEMP_THRESH_HALT])) {
 		/* We don't reboot automatically - the user has to push
@@ -177,21 +222,27 @@ static void thermal_control(void)
 	if (cond_went_true(&cond_hot[EC_TEMP_THRESH_WARN])) {
 		CPRINTS("thermal WARN");
 		throttle_ap(THROTTLE_ON, THROTTLE_SOFT, THROTTLE_SRC_THERMAL);
+#ifdef CONFIG_PLATFORM_EC_CUSTOMIZED_DESIGN
+		thermal_warn_active = true;
+#endif
 	} else if (cond_went_false(&cond_hot[EC_TEMP_THRESH_WARN])) {
 		CPRINTS("thermal no longer warn");
 		throttle_ap(THROTTLE_OFF, THROTTLE_SOFT, THROTTLE_SRC_THERMAL);
+#ifdef CONFIG_PLATFORM_EC_CUSTOMIZED_DESIGN
+		thermal_warn_active = false;
+#endif
 	}
 
-	if (temp_fan_configured) {
 #ifdef CONFIG_FANS
 #ifdef CONFIG_CUSTOM_FAN_CONTROL
-		for (i = 0; i < fan_get_count(); i++) {
-			if (!is_thermal_control_enabled(i))
-				continue;
+	for (i = 0; i < fan_get_count(); i++) {
+		if (!is_thermal_control_enabled(i))
+			continue;
 
-			board_override_fan_control(i, temp);
-		}
+		board_override_fan_control(i, temp);
+	}
 #else
+	if (temp_fan_configured) {
 		/* TODO(crosbug.com/p/23797): For now, we just treat all
 		 * fans the same. It would be better if we could assign
 		 * different thermal profiles to each fan - in case one
@@ -200,41 +251,44 @@ static void thermal_control(void)
 		 */
 		for (i = 0; i < fan_get_count(); i++)
 			fan_set_percent_needed(i, fmax);
+	}
 #endif
 #endif
-	}
 }
 
 /* Wait until after the sensors have been read */
 DECLARE_HOOK(HOOK_SECOND, thermal_control, HOOK_PRIO_TEMP_SENSOR_DONE);
 
+/*****************************************************************************/
+/* Project */
+bool thermal_warn_trigger(void)
+{
+	return thermal_warn_active;
+}
+
 /*****************************************************************************/
 /* Console commands */
 
-static int command_thermalget(int argc, char **argv)
+static int command_thermalget(int argc, const char **argv)
 {
 	int i;
 
 	ccprintf("sensor  warn  high  halt   fan_off fan_max   name\n");
 	for (i = 0; i < TEMP_SENSOR_COUNT; i++) {
 		ccprintf(" %2d      %3d   %3d    %3d    %3d     %3d     %s\n",
-			 i,
-			 thermal_params[i].temp_host[EC_TEMP_THRESH_WARN],
+			 i, thermal_params[i].temp_host[EC_TEMP_THRESH_WARN],
 			 thermal_params[i].temp_host[EC_TEMP_THRESH_HIGH],
 			 thermal_params[i].temp_host[EC_TEMP_THRESH_HALT],
 			 thermal_params[i].temp_fan_off,
-			 thermal_params[i].temp_fan_max,
-			 temp_sensors[i].name);
+			 thermal_params[i].temp_fan_max, temp_sensors[i].name);
 	}
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(thermalget, command_thermalget,
-			NULL,
+DECLARE_CONSOLE_COMMAND(thermalget, command_thermalget, NULL,
 			"Print thermal parameters (degrees Kelvin)");
 
-
-static int command_thermalset(int argc, char **argv)
+static int command_thermalset(int argc, const char **argv)
 {
 	unsigned int n;
 	int i, val;
@@ -298,8 +352,7 @@ thermal_command_set_threshold(struct host_cmd_handler_args *args)
 	return EC_RES_SUCCESS;
 }
 DECLARE_HOST_COMMAND(EC_CMD_THERMAL_SET_THRESHOLD,
-		     thermal_command_set_threshold,
-		     EC_VER_MASK(1));
+		     thermal_command_set_threshold, EC_VER_MASK(1));
 
 static enum ec_status
 thermal_command_get_threshold(struct host_cmd_handler_args *args)
@@ -315,5 +368,4 @@ thermal_command_get_threshold(struct host_cmd_handler_args *args)
 	return EC_RES_SUCCESS;
 }
 DECLARE_HOST_COMMAND(EC_CMD_THERMAL_GET_THRESHOLD,
-		     thermal_command_get_threshold,
-		     EC_VER_MASK(1));
+		     thermal_command_get_threshold, EC_VER_MASK(1));
diff --git a/common/throttle_ap.c b/common/throttle_ap.c
index 8a4314db4d..77c3f83969 100644
--- a/common/throttle_ap.c
+++ b/common/throttle_ap.c
@@ -1,14 +1,16 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Common chipset throttling code for Chrome EC */
 
+#include "builtin/assert.h"
 #include "chipset.h"
 #include "common.h"
 #include "console.h"
 #include "dptf.h"
+#include "gpio.h"
 #include "hooks.h"
 #include "host_command.h"
 #include "task.h"
@@ -18,19 +20,23 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_THERMAL, outstr)
-#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
 
-#define PROCHOT_IN_DEBOUNCE_US		(100 * MSEC)
+/*
+ * When C10 deasserts, PROCHOT may also change state when the corresponding
+ * power rail is turned back on. Recheck PROCHOT directly from the C10 exit
+ * using a shorter debounce than the PROCHOT interrupt.
+ */
+#define C10_IN_DEBOUNCE_US (10 * MSEC)
 
 /*****************************************************************************/
 /* This enforces the virtual OR of all throttling sources. */
-static struct mutex throttle_mutex;
+K_MUTEX_DEFINE(throttle_mutex);
 static uint32_t throttle_request[NUM_THROTTLE_TYPES];
 static int debounced_prochot_in;
-static enum gpio_signal gpio_prochot_in = GPIO_COUNT;
+static const struct prochot_cfg *prochot_cfg;
 
-void throttle_ap(enum throttle_level level,
-		 enum throttle_type type,
+void throttle_ap(enum throttle_level level, enum throttle_type type,
 		 enum throttle_sources source)
 {
 	uint32_t tmpval, bitmask;
@@ -48,7 +54,7 @@ void throttle_ap(enum throttle_level level,
 		break;
 	}
 
-	tmpval = throttle_request[type];	/* save for printing */
+	tmpval = throttle_request[type]; /* save for printing */
 
 	switch (type) {
 	case THROTTLE_SOFT:
@@ -72,9 +78,32 @@ void throttle_ap(enum throttle_level level,
 	mutex_unlock(&throttle_mutex);
 
 	/* print outside the mutex */
-	CPRINTS("set AP throttling type %d to %s (0x%08x)",
-		type, tmpval ? "on" : "off", tmpval);
+	CPRINTS("set AP throttling type %d to %s (0x%08x)", type,
+		tmpval ? "on" : "off", tmpval);
+}
+
+void throttle_ap_config_prochot(const struct prochot_cfg *cfg)
+{
+	prochot_cfg = cfg;
 
+	if (IS_ENABLED(CONFIG_THROTTLE_AP_SINGLE_PIN)) {
+		gpio_set_flags(prochot_cfg->gpio_prochot_in, GPIO_INPUT);
+	}
+}
+
+__maybe_unused static bool prochot_is_gated_by_c10(int prochot_in)
+{
+#ifdef CONFIG_CPU_PROCHOT_GATE_ON_C10
+	int c10_in = gpio_get_level(prochot_cfg->gpio_c10_in);
+
+	if (!prochot_cfg->c10_active_high)
+		c10_in = !c10_in;
+
+	if (c10_in && prochot_in) {
+		return true;
+	}
+#endif
+	return false;
 }
 
 static void prochot_input_deferred(void)
@@ -82,12 +111,11 @@ static void prochot_input_deferred(void)
 	int prochot_in;
 
 	/*
-	 * Shouldn't be possible, but better to protect against buffer
-	 * overflow
+	 * Validate board called throttle_ap_config_prochot().
 	 */
-	ASSERT(signal_is_gpio(gpio_prochot_in));
+	ASSERT(prochot_cfg);
 
-	prochot_in = gpio_get_level(gpio_prochot_in);
+	prochot_in = gpio_get_level(prochot_cfg->gpio_prochot_in);
 
 	if (IS_ENABLED(CONFIG_CPU_PROCHOT_ACTIVE_LOW))
 		prochot_in = !prochot_in;
@@ -95,44 +123,71 @@ static void prochot_input_deferred(void)
 	if (prochot_in == debounced_prochot_in)
 		return;
 
+	/*
+	 * b/173180788 Confirmed from Intel internal that SLP_S3# asserts low
+	 * about 10us before PROCHOT# asserts low, which means that
+	 * the CPU is already in reset and therefore the PROCHOT#
+	 * asserting low is normal behavior and not a concern
+	 * for PROCHOT# event.  Ignore all PROCHOT changes while the AP is off
+	 */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF | CHIPSET_STATE_ANY_SUSPEND))
+		return;
+
+	/*
+	 * b/185810479 When the AP enters C10, the PROCHOT signal may not be
+	 * valid. Refer to the CONFIG_CPU_PROCHOT_GATE_ON_C10 documentation
+	 * for details.
+	 */
+	if (prochot_is_gated_by_c10(prochot_in))
+		return;
+
 	debounced_prochot_in = prochot_in;
 
 	if (debounced_prochot_in) {
 		CPRINTS("External PROCHOT assertion detected");
-#ifdef CONFIG_FANS
+#if defined(CONFIG_FANS) && !defined(CONFIG_THROTTLE_AP_NO_FAN)
 		dptf_set_fan_duty_target(100);
 #endif
 	} else {
 		CPRINTS("External PROCHOT condition cleared");
-#ifdef CONFIG_FANS
+#if defined(CONFIG_FANS) && !defined(CONFIG_THROTTLE_AP_NO_FAN)
 		/* Revert to automatic control of the fan */
 		dptf_set_fan_duty_target(-1);
 #endif
 	}
+
+	if (prochot_cfg->callback)
+		prochot_cfg->callback(debounced_prochot_in,
+				      prochot_cfg->callback_data);
 }
 DECLARE_DEFERRED(prochot_input_deferred);
 
 void throttle_ap_prochot_input_interrupt(enum gpio_signal signal)
 {
-	/*
-	 * Save the PROCHOT signal that generated the interrupt so we don't
-	 * rely on a specific pin name.
-	 */
-	if (gpio_prochot_in == GPIO_COUNT)
-		gpio_prochot_in = signal;
-
 	/*
 	 * Trigger deferred notification of PROCHOT change so we can ignore
 	 * any pulses that are too short.
 	 */
 	hook_call_deferred(&prochot_input_deferred_data,
-		PROCHOT_IN_DEBOUNCE_US);
+			   PROCHOT_IN_DEBOUNCE_US);
 }
 
+#ifdef CONFIG_CPU_PROCHOT_GATE_ON_C10
+void throttle_ap_c10_input_interrupt(enum gpio_signal signal)
+{
+	/*
+	 * This interrupt is configured to fire only when the AP exits C10
+	 * and de-asserts the C10 signal. Recheck the PROCHOT signal in case
+	 * another PROCHOT source is active when the AP exits C10.
+	 */
+	hook_call_deferred(&prochot_input_deferred_data, C10_IN_DEBOUNCE_US);
+}
+#endif
+
 /*****************************************************************************/
 /* Console commands */
 #ifdef CONFIG_CMD_APTHROTTLE
-static int command_apthrottle(int argc, char **argv)
+static int command_apthrottle(int argc, const char **argv)
 {
 	int i;
 	uint32_t tmpval;
@@ -148,7 +203,6 @@ static int command_apthrottle(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(apthrottle, command_apthrottle,
-			NULL,
+DECLARE_CONSOLE_COMMAND(apthrottle, command_apthrottle, NULL,
 			"Display the AP throttling state");
 #endif
diff --git a/common/timer.c b/common/timer.c
index c359efb541..9d45e4faf3 100644
--- a/common/timer.c
+++ b/common/timer.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,56 +6,56 @@
 /* Timer module for Chrome EC operating system */
 
 #include "atomic.h"
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
 #include "hooks.h"
 #include "hwtimer.h"
 #include "system.h"
-#include "util.h"
 #include "task.h"
 #include "timer.h"
+#include "util.h"
 #include "watchdog.h"
 
 #ifdef CONFIG_ZEPHYR
-#include <kernel.h> /* For k_usleep() */
+#include <zephyr/kernel.h> /* For k_usleep() */
 #else
-extern __error("k_usleep() should only be called from Zephyr code")
-int32_t k_usleep(int32_t);
+extern __error("k_usleep() should only be called from Zephyr code") int32_t
+	k_usleep(int32_t);
 #endif /* CONFIG_ZEPHYR */
 
-#define TIMER_SYSJUMP_TAG 0x4d54  /* "TM" */
+#ifdef CONFIG_COMMON_RUNTIME
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+#else
+#define CPRINTS(format, args...)
+#define CPRINTF(format, args...)
+#endif
+
+#define TIMER_SYSJUMP_TAG 0x4d54 /* "TM" */
 
 /* High 32-bits of the 64-bit timestamp counter. */
-STATIC_IF_NOT(CONFIG_HWTIMER_64BIT) uint32_t clksrc_high;
+STATIC_IF_NOT(CONFIG_HWTIMER_64BIT) volatile uint32_t clksrc_high;
 
+/* Hardware timer routine IRQ number */
+static int timer_irq;
+
+#ifndef CONFIG_ZEPHYR
 /* Bitmap of currently running timers */
 static uint32_t timer_running;
 
+BUILD_ASSERT((sizeof(timer_running) * 8) > TASK_ID_COUNT);
+
 /* Deadlines of all timers */
 static timestamp_t timer_deadline[TASK_ID_COUNT];
 static uint32_t next_deadline = 0xffffffff;
 
-/* Hardware timer routine IRQ number */
-static int timer_irq;
-
 static void expire_timer(task_id_t tskid)
 {
 	/* we are done with this timer */
-	deprecated_atomic_clear_bits(&timer_running, 1 << tskid);
+	atomic_clear_bits((atomic_t *)&timer_running, 1 << tskid);
 	/* wake up the taks waiting for this timer */
-	task_set_event(tskid, TASK_EVENT_TIMER, 0);
-}
-
-int timestamp_expired(timestamp_t deadline, const timestamp_t *now)
-{
-	timestamp_t now_val;
-
-	if (!now) {
-		now_val = get_time();
-		now = &now_val;
-	}
-
-	return ((int64_t)(now->val - deadline.val) >= 0);
+	task_set_event(tskid, TASK_EVENT_TIMER);
 }
 
 void process_timers(int overflow)
@@ -74,7 +74,6 @@ void process_timers(int overflow)
 			/* read atomically the current state of timer running */
 			check_timer = running_t0 = timer_running;
 			while (check_timer) {
-
 				int tskid = __fls(check_timer);
 				/* timer has expired ? */
 				if (timer_deadline[tskid].val <= now.val)
@@ -87,7 +86,7 @@ void process_timers(int overflow)
 
 				check_timer &= ~BIT(tskid);
 			}
-		/* if there is a new timer, let's retry */
+			/* if there is a new timer, let's retry */
 		} while (timer_running & ~running_t0);
 
 		if (next.le.hi == 0xffffffff) {
@@ -101,11 +100,24 @@ void process_timers(int overflow)
 		next_deadline = next.le.lo;
 	} while (next.val <= get_time().val);
 }
+#endif /* !defined(CONFIG_ZEPHYR) */
+
+int timestamp_expired(timestamp_t deadline, const timestamp_t *now)
+{
+	timestamp_t now_val;
+
+	if (!now) {
+		now_val = get_time();
+		now = &now_val;
+	}
+
+	return ((int64_t)(now->val - deadline.val) >= 0);
+}
 
 #ifndef CONFIG_HW_SPECIFIC_UDELAY
-void udelay(unsigned us)
+void udelay(unsigned int us)
 {
-	unsigned t0 = __hw_clock_source_read();
+	unsigned int t0 = __hw_clock_source_read();
 
 	/*
 	 * udelay() may be called with interrupts disabled, so we can't rely on
@@ -122,6 +134,8 @@ void udelay(unsigned us)
 }
 #endif
 
+/* Zephyr provides its own implementation in task shim */
+#ifndef CONFIG_ZEPHYR
 int timer_arm(timestamp_t event, task_id_t tskid)
 {
 	timestamp_t now = get_time();
@@ -132,7 +146,7 @@ int timer_arm(timestamp_t event, task_id_t tskid)
 		return EC_ERROR_BUSY;
 
 	timer_deadline[tskid] = event;
-	deprecated_atomic_or(&timer_running, BIT(tskid));
+	atomic_or((atomic_t *)&timer_running, BIT(tskid));
 
 	/* Modify the next event if needed */
 	if ((event.le.hi < now.le.hi) ||
@@ -146,12 +160,13 @@ void timer_cancel(task_id_t tskid)
 {
 	ASSERT(tskid < TASK_ID_COUNT);
 
-	deprecated_atomic_clear_bits(&timer_running, BIT(tskid));
+	atomic_clear_bits((atomic_t *)&timer_running, BIT(tskid));
 	/*
 	 * Don't need to cancel the hardware timer interrupt, instead do
 	 * timer-related housekeeping when the next timer interrupt fires.
 	 */
 }
+#endif
 
 /*
  * For us < (2^31 - task scheduling latency)(~ 2147 sec), this function will
@@ -159,11 +174,15 @@ void timer_cancel(task_id_t tskid)
  * probability of delay longer than 2*us (and possibly infinite delay)
  * increases.
  */
-void usleep(unsigned us)
+void usleep(unsigned int us)
 {
 	uint32_t evt = 0;
 	uint32_t t0;
 
+	/* If a wait is 0, return immediately. */
+	if (!us)
+		return;
+
 	if (IS_ENABLED(CONFIG_ZEPHYR)) {
 		while (us)
 			us = k_usleep(us);
@@ -178,27 +197,47 @@ void usleep(unsigned us)
 		return;
 	}
 
-	ASSERT(us);
+	/* If in interrupt context or interrupts are disabled, use udelay() */
+	if (!is_interrupt_enabled() || in_interrupt_context()) {
+		CPRINTS("Sleeping not allowed");
+		udelay(us);
+		return;
+	}
+
 	do {
 		evt |= task_wait_event(us);
 	} while (!(evt & TASK_EVENT_TIMER) &&
-		((__hw_clock_source_read() - t0) < us));
+		 ((__hw_clock_source_read() - t0) < us));
 
 	/* Re-queue other events which happened in the meanwhile */
 	if (evt)
-		deprecated_atomic_or(task_get_event_bitmap(task_get_current()),
-				     evt & ~TASK_EVENT_TIMER);
+		atomic_or(task_get_event_bitmap(task_get_current()),
+			  evt & ~TASK_EVENT_TIMER);
 }
 
+#ifdef CONFIG_ZTEST
+timestamp_t *get_time_mock;
+#endif /* CONFIG_ZTEST */
+
 timestamp_t get_time(void)
 {
 	timestamp_t ts;
 
+#ifdef CONFIG_ZTEST
+	if (get_time_mock != NULL)
+		return *get_time_mock;
+#endif /* CONFIG_ZTEST */
+
 	if (IS_ENABLED(CONFIG_HWTIMER_64BIT)) {
 		ts.val = __hw_clock_source_read64();
 	} else {
 		ts.le.hi = clksrc_high;
 		ts.le.lo = __hw_clock_source_read();
+		/*
+		 * TODO(b/213342294) If statement below doesn't catch overflows
+		 * when interrupts are disabled or currently processed interrupt
+		 * has higher priority.
+		 */
 		if (ts.le.hi != clksrc_high) {
 			ts.le.hi = clksrc_high;
 			ts.le.lo = __hw_clock_source_read();
@@ -211,7 +250,7 @@ timestamp_t get_time(void)
 clock_t clock(void)
 {
 	/* __hw_clock_source_read() returns a microsecond resolution timer.*/
-	return (clock_t) __hw_clock_source_read() / 1000;
+	return (clock_t)__hw_clock_source_read() / 1000;
 }
 
 void force_time(timestamp_t ts)
@@ -219,8 +258,24 @@ void force_time(timestamp_t ts)
 	if (IS_ENABLED(CONFIG_HWTIMER_64BIT)) {
 		__hw_clock_source_set64(ts.val);
 	} else {
+		/* Save current interrupt state */
+		bool interrupt_enabled = is_interrupt_enabled();
+
+		/*
+		 * Updating timer shouldn't be interrupted (eg. when counter
+		 * overflows) because it could lead to some unintended
+		 * consequences. Please note that this function can be called
+		 * with disabled or enabled interrupts so we need to restore
+		 * the original state later.
+		 */
+		interrupt_disable();
+
 		clksrc_high = ts.le.hi;
 		__hw_clock_source_set(ts.le.lo);
+
+		/* Restore original interrupt state */
+		if (interrupt_enabled)
+			interrupt_enable();
 	}
 
 	/* some timers might be already expired : process them */
@@ -248,9 +303,7 @@ void __hw_clock_source_set(uint32_t ts)
 void timer_print_info(void)
 {
 	timestamp_t t = get_time();
-	uint64_t deadline = (uint64_t)t.le.hi << 32 |
-		__hw_clock_event_get();
-	int tskid;
+	uint64_t deadline = (uint64_t)t.le.hi << 32 | __hw_clock_event_get();
 
 	ccprintf("Time:     0x%016llx us, %11.6lld s\n"
 		 "Deadline: 0x%016llx -> %11.6lld s from now\n"
@@ -258,7 +311,8 @@ void timer_print_info(void)
 		 t.val, t.val, deadline, deadline - t.val);
 	cflush();
 
-	for (tskid = 0; tskid < TASK_ID_COUNT; tskid++) {
+#ifndef CONFIG_ZEPHYR
+	for (int tskid = 0; tskid < TASK_ID_COUNT; tskid++) {
 		if (timer_running & BIT(tskid)) {
 			ccprintf("  Tsk %2d  0x%016llx -> %11.6lld\n", tskid,
 				 timer_deadline[tskid].val,
@@ -266,6 +320,7 @@ void timer_print_info(void)
 			cflush();
 		}
 	}
+#endif /* !defined(CONFIG_ZEPHYR) */
 }
 
 void timer_init(void)
@@ -273,8 +328,6 @@ void timer_init(void)
 	const timestamp_t *ts;
 	int size, version;
 
-	BUILD_ASSERT(TASK_ID_COUNT < sizeof(timer_running) * 8);
-
 	/* Restore time from before sysjump */
 	ts = (const timestamp_t *)system_get_jump_tag(TIMER_SYSJUMP_TAG,
 						      &version, &size);
@@ -303,7 +356,7 @@ static void timer_sysjump(void)
 DECLARE_HOOK(HOOK_SYSJUMP, timer_sysjump, HOOK_PRIO_DEFAULT);
 
 #ifdef CONFIG_CMD_WAITMS
-static int command_wait(int argc, char **argv)
+static int command_wait(int argc, const char **argv)
 {
 	char *e;
 	int i;
@@ -315,6 +368,9 @@ static int command_wait(int argc, char **argv)
 	if (*e)
 		return EC_ERROR_PARAM1;
 
+	if (i < 0)
+		return EC_ERROR_PARAM1;
+
 	/*
 	 * Reload the watchdog so that issuing multiple small waitms commands
 	 * quickly one after the other will not cause a reset.
@@ -333,8 +389,7 @@ static int command_wait(int argc, char **argv)
 	return EC_SUCCESS;
 }
 /* Typically a large delay (e.g. 3s) will cause a reset */
-DECLARE_CONSOLE_COMMAND(waitms, command_wait,
-			"msec",
+DECLARE_CONSOLE_COMMAND(waitms, command_wait, "msec",
 			"Busy-wait for msec (large delays will reset)");
 #endif
 
@@ -344,7 +399,7 @@ DECLARE_CONSOLE_COMMAND(waitms, command_wait,
  * especially when going "backward" in time, because task deadlines are
  * left un-adjusted.
  */
-static int command_force_time(int argc, char **argv)
+static int command_force_time(int argc, const char **argv)
 {
 	char *e;
 	timestamp_t new;
@@ -365,32 +420,29 @@ static int command_force_time(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(forcetime, command_force_time,
-			"hi lo",
+DECLARE_CONSOLE_COMMAND(forcetime, command_force_time, "hi lo",
 			"Force current time");
 #endif
 
 #ifdef CONFIG_CMD_GETTIME
-static int command_get_time(int argc, char **argv)
+static int command_get_time(int argc, const char **argv)
 {
 	timestamp_t ts = get_time();
 	ccprintf("Time: 0x%016llx = %.6lld s\n", ts.val, ts.val);
 
 	return EC_SUCCESS;
 }
-DECLARE_SAFE_CONSOLE_COMMAND(gettime, command_get_time,
-			     NULL,
+DECLARE_SAFE_CONSOLE_COMMAND(gettime, command_get_time, NULL,
 			     "Print current time");
 #endif
 
 #ifdef CONFIG_CMD_TIMERINFO
-int command_timer_info(int argc, char **argv)
+static int command_timer_info(int argc, const char **argv)
 {
 	timer_print_info();
 
 	return EC_SUCCESS;
 }
-DECLARE_SAFE_CONSOLE_COMMAND(timerinfo, command_timer_info,
-			     NULL,
+DECLARE_SAFE_CONSOLE_COMMAND(timerinfo, command_timer_info, NULL,
 			     "Print timer info");
 #endif
diff --git a/common/trng.c b/common/trng.c
new file mode 100644
index 0000000000..273a078d7a
--- /dev/null
+++ b/common/trng.c
@@ -0,0 +1,82 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Common Random Number Generation (RNG) routines */
+
+#include "common.h"
+#include "console.h"
+#include "cpu.h"
+#include "host_command.h"
+#include "panic.h"
+#include "printf.h"
+#include "registers.h"
+#include "system.h"
+#include "task.h"
+#include "trng.h"
+#include "util.h"
+
+test_mockable void trng_rand_bytes(void *buffer, size_t len)
+{
+	while (len) {
+		uint32_t number = trng_rand();
+		size_t cnt = 4;
+		/* deal with the lack of alignment guarantee in the API */
+		uintptr_t align = (uintptr_t)buffer & 3;
+
+		if (len < 4 || align) {
+			cnt = MIN(4 - align, len);
+			memcpy(buffer, &number, cnt);
+		} else {
+			*(uint32_t *)buffer = number;
+		}
+		len -= cnt;
+		buffer += cnt;
+	}
+}
+
+#if defined(CONFIG_CMD_RAND)
+/*
+ * We want to avoid accidentally exposing debug commands in RO since we can't
+ * update RO once in production.
+ */
+#if defined(SECTION_IS_RW)
+static int command_rand(int argc, const char **argv)
+{
+	uint8_t data[32];
+	char str_buf[hex_str_buf_size(sizeof(data))];
+
+	trng_init();
+	trng_rand_bytes(data, sizeof(data));
+	trng_exit();
+	snprintf_hex_buffer(str_buf, sizeof(str_buf),
+			    HEX_BUF(data, sizeof(data)));
+	ccprintf("rand %s\n", str_buf);
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(rand, command_rand, NULL,
+			"Output random bytes to console.");
+
+static enum ec_status host_command_rand(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_rand_num *p = args->params;
+	struct ec_response_rand_num *r = args->response;
+	uint16_t num_rand_bytes = p->num_rand_bytes;
+
+	if (system_is_locked())
+		return EC_RES_ACCESS_DENIED;
+	if (num_rand_bytes > args->response_max)
+		return EC_RES_OVERFLOW;
+	trng_init();
+	trng_rand_bytes(r->rand, num_rand_bytes);
+	trng_exit();
+	args->response_size = num_rand_bytes;
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_RAND_NUM, host_command_rand,
+		     EC_VER_MASK(EC_VER_RAND_NUM));
+#endif /* SECTION_IS_RW */
+#endif /* CONFIG_CMD_RAND */
diff --git a/common/typec_control.c b/common/typec_control.c
new file mode 100644
index 0000000000..94070d47df
--- /dev/null
+++ b/common/typec_control.c
@@ -0,0 +1,76 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Type-C control logic source */
+
+#include "tcpm/tcpm.h"
+#include "usbc_ocp.h"
+#include "usbc_ppc.h"
+
+void typec_set_polarity(int port, enum tcpc_cc_polarity polarity)
+{
+	tcpm_set_polarity(port, polarity);
+
+	if (IS_ENABLED(CONFIG_USBC_PPC_POLARITY))
+		ppc_set_polarity(port, polarity);
+}
+
+void typec_set_sbu(int port, bool enable)
+{
+	if (IS_ENABLED(CONFIG_USBC_PPC_SBU))
+		ppc_set_sbu(port, enable);
+
+#ifdef CONFIG_USB_PD_TCPM_SBU
+	tcpc_set_sbu(port, enable);
+#endif
+}
+
+__overridable void typec_set_source_current_limit(int port,
+						  enum tcpc_rp_value rp)
+{
+	if (IS_ENABLED(CONFIG_USBC_PPC))
+		ppc_set_vbus_source_current_limit(port, rp);
+}
+
+void typec_set_vconn(int port, bool enable)
+{
+	if (!IS_ENABLED(CONFIG_USBC_VCONN))
+		return;
+
+	/*
+	 * Check our OC event counter.  If we've exceeded our threshold, then
+	 * let's latch our source path off to prevent continuous cycling.  When
+	 * the PD state machine detects a disconnection on the CC lines, we will
+	 * reset our OC event counter.
+	 */
+	if (IS_ENABLED(CONFIG_USBC_OCP) && enable &&
+	    usbc_ocp_is_port_latched_off(port))
+		return;
+
+	/*
+	 * Disable PPC Vconn first then TCPC in case the voltage feeds back
+	 * to TCPC and damages.
+	 */
+	if (IS_ENABLED(CONFIG_USBC_PPC_VCONN) && !enable)
+		ppc_set_vconn(port, false);
+
+	/*
+	 * Some TCPCs/PPC combinations can trigger OVP if the TCPC doesn't
+	 * source VCONN. This happens if the TCPC will trip OVP with 5V, and the
+	 * PPC doesn't isolate the TCPC from VCONN when sourcing. But, some PPCs
+	 * which do isolate the TCPC can't handle 5V on its host-side CC pins,
+	 * so the TCPC shouldn't source VCONN in those cases.
+	 *
+	 * In the first case, both TCPC and PPC will potentially source Vconn,
+	 * but that should be okay since Vconn has "make before break"
+	 * electrical requirements when swapping anyway.
+	 *
+	 * See b/72961003 and b/180973460
+	 */
+	tcpm_set_vconn(port, enable);
+
+	if (IS_ENABLED(CONFIG_USBC_PPC_VCONN) && enable)
+		ppc_set_vconn(port, true);
+}
diff --git a/common/uart_buffering.c b/common/uart_buffering.c
index 1c0db3b151..f3d150dfda 100644
--- a/common/uart_buffering.c
+++ b/common/uart_buffering.c
@@ -1,12 +1,10 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Common code to do UART buffering and printing */
 
-#include <stdarg.h>
-
 #include "common.h"
 #include "console.h"
 #include "hooks.h"
@@ -19,10 +17,12 @@
 #include "uart.h"
 #include "util.h"
 
+#include <stdarg.h>
+
 /* Macros to advance in the circular buffers */
 #define TX_BUF_NEXT(i) (((i) + 1) & (CONFIG_UART_TX_BUF_SIZE - 1))
 #define RX_BUF_NEXT(i) (((i) + 1) & (CONFIG_UART_RX_BUF_SIZE - 1))
-#define RX_BUF_PREV(i) (((i) - 1) & (CONFIG_UART_RX_BUF_SIZE - 1))
+#define RX_BUF_PREV(i) (((i)-1) & (CONFIG_UART_RX_BUF_SIZE - 1))
 
 /* Macros to calculate difference of pointers in the circular buffers. */
 #define TX_BUF_DIFF(i, j) (((i) - (j)) & (CONFIG_UART_TX_BUF_SIZE - 1))
@@ -37,12 +37,12 @@ BUILD_ASSERT((CONFIG_UART_RX_BUF_SIZE & (CONFIG_UART_RX_BUF_SIZE - 1)) == 0);
  * of input has been detected by the normal tick task.  There will be
  * CONFIG_UART_RX_DMA_RECHECKS rechecks between this tick and the next tick.
  */
-#define RX_DMA_RECHECK_INTERVAL (HOOK_TICK_INTERVAL /			\
-				 (CONFIG_UART_RX_DMA_RECHECKS + 1))
+#define RX_DMA_RECHECK_INTERVAL \
+	(HOOK_TICK_INTERVAL / (CONFIG_UART_RX_DMA_RECHECKS + 1))
 
 /* Transmit and receive buffers */
-static volatile char tx_buf[CONFIG_UART_TX_BUF_SIZE]
-			__uncached __preserved_logs(tx_buf);
+static volatile char tx_buf[CONFIG_UART_TX_BUF_SIZE] __uncached
+	__preserved_logs(tx_buf);
 static volatile int tx_buf_head __preserved_logs(tx_buf_head);
 static volatile int tx_buf_tail __preserved_logs(tx_buf_tail);
 static volatile char rx_buf[CONFIG_UART_RX_BUF_SIZE] __uncached;
@@ -59,34 +59,29 @@ static int uart_buffer_calc_checksum(void)
 	return tx_buf_head ^ tx_buf_tail;
 }
 
-
 void uart_init_buffer(void)
 {
 	if (tx_checksum != uart_buffer_calc_checksum() ||
-	    !IN_RANGE(tx_buf_head, 0, CONFIG_UART_TX_BUF_SIZE) ||
-	    !IN_RANGE(tx_buf_tail, 0, CONFIG_UART_TX_BUF_SIZE)) {
+	    !IN_RANGE(tx_buf_head, 0, CONFIG_UART_TX_BUF_SIZE - 1) ||
+	    !IN_RANGE(tx_buf_tail, 0, CONFIG_UART_TX_BUF_SIZE - 1)) {
+		/*
+		 * NOTE:
+		 * We are here because EC cold reset or RO/RW's preserve_logs
+		 * section are different.
+		 */
 		tx_buf_head = 0;
 		tx_buf_tail = 0;
 		tx_checksum = 0;
 	}
 }
 
-/**
- * Put a single character into the transmit buffer.
- *
- * Does not enable the transmit interrupt; assumes that happens elsewhere.
- *
- * @param context	Context; ignored.
- * @param c		Character to write.
- * @return 0 if the character was transmitted, 1 if it was dropped.
- */
-static int __tx_char_raw(void *context, int c)
+int uart_tx_char_raw(void *context, int c)
 {
 	int tx_buf_next, tx_buf_new_tail;
 
 #if defined CONFIG_POLLING_UART
-	(void) tx_buf_next;
-	(void) tx_buf_new_tail;
+	(void)tx_buf_next;
+	(void)tx_buf_new_tail;
 	uart_write_char(c);
 #else
 
@@ -118,14 +113,6 @@ static int __tx_char_raw(void *context, int c)
 	return 0;
 }
 
-static int __tx_char(void *context, int c)
-{
-	/* Translate '\n' to '\r\n' */
-	if (c == '\n' && __tx_char_raw(NULL, '\r'))
-		return 1;
-	return __tx_char_raw(context, c);
-}
-
 #ifdef CONFIG_UART_TX_DMA
 
 /**
@@ -149,7 +136,7 @@ void uart_process_output(void)
 	/* If a previous DMA transfer completed, free up the buffer it used */
 	if (tx_dma_in_progress) {
 		tx_buf_tail = (tx_buf_tail + tx_dma_in_progress) &
-			(CONFIG_UART_TX_BUF_SIZE - 1);
+			      (CONFIG_UART_TX_BUF_SIZE - 1);
 		tx_dma_in_progress = 0;
 
 		if (IS_ENABLED(CONFIG_PRESERVE_LOGS))
@@ -166,8 +153,9 @@ void uart_process_output(void)
 	 * Get the largest contiguous block of output.  If the transmit buffer
 	 * wraps, only use the part before the wrap.
 	 */
-	tx_dma_in_progress = (head > tx_buf_tail ? head :
-			      CONFIG_UART_TX_BUF_SIZE) - tx_buf_tail;
+	tx_dma_in_progress =
+		(head > tx_buf_tail ? head : CONFIG_UART_TX_BUF_SIZE) -
+		tx_buf_tail;
 
 	uart_tx_dma_start((char *)(tx_buf + tx_buf_tail), tx_dma_in_progress);
 }
@@ -193,7 +181,7 @@ void uart_process_output(void)
 #endif /* !CONFIG_UART_TX_DMA */
 
 #ifdef CONFIG_UART_RX_DMA
-#ifdef CONFIG_UART_INPUT_FILTER  /* TODO(crosbug.com/p/36745): */
+#ifdef CONFIG_UART_INPUT_FILTER /* TODO(crosbug.com/p/36745): */
 #error "Filtering the UART input with DMA enabled is NOT SUPPORTED!"
 #endif
 
@@ -257,7 +245,7 @@ void uart_process_input(void)
 
 void uart_clear_input(void)
 {
-	int scratch __attribute__ ((unused));
+	int scratch __attribute__((unused));
 	while (uart_rx_available())
 		scratch = uart_read_char();
 	rx_buf_head = rx_buf_tail = 0;
@@ -265,77 +253,6 @@ void uart_clear_input(void)
 
 #endif /* !CONFIG_UART_RX_DMA */
 
-int uart_putc(int c)
-{
-	int rv = __tx_char(NULL, c);
-
-	uart_tx_start();
-
-	return rv ? EC_ERROR_OVERFLOW : EC_SUCCESS;
-}
-
-int uart_puts(const char *outstr)
-{
-	/* Put all characters in the output buffer */
-	while (*outstr) {
-		if (__tx_char(NULL, *outstr++) != 0)
-			break;
-	}
-
-	uart_tx_start();
-
-	/* Successful if we consumed all output */
-	return *outstr ? EC_ERROR_OVERFLOW : EC_SUCCESS;
-}
-
-int uart_put(const char *out, int len)
-{
-	/* Put all characters in the output buffer */
-	while (len--) {
-		if (__tx_char(NULL, *out++) != 0)
-			break;
-	}
-
-	uart_tx_start();
-
-	/* Successful if we consumed all output */
-	return len ? EC_ERROR_OVERFLOW : EC_SUCCESS;
-}
-
-int uart_put_raw(const char *out, int len)
-{
-	/* Put all characters in the output buffer */
-	while (len--) {
-		if (__tx_char_raw(NULL, *out++) != 0)
-			break;
-	}
-
-	uart_tx_start();
-
-	/* Successful if we consumed all output */
-	return len ? EC_ERROR_OVERFLOW : EC_SUCCESS;
-}
-
-int uart_vprintf(const char *format, va_list args)
-{
-	int rv = vfnprintf(__tx_char, NULL, format, args);
-
-	uart_tx_start();
-
-	return rv;
-}
-
-int uart_printf(const char *format, ...)
-{
-	int rv;
-	va_list args;
-
-	va_start(args, format);
-	rv = uart_vprintf(format, args);
-	va_end(args);
-	return rv;
-}
-
 void uart_flush_output(void)
 {
 	/* If UART not initialized ignore flush request. */
@@ -344,7 +261,7 @@ void uart_flush_output(void)
 
 	/* Loop until buffer is empty */
 	while (tx_buf_head != tx_buf_tail) {
-		if (in_interrupt_context()) {
+		if (in_interrupt_context() || !is_interrupt_enabled()) {
 			/*
 			 * Explicitly process UART output, since the UART
 			 * interrupt may not be able to preempt the interrupt
@@ -402,55 +319,6 @@ static void uart_rx_dma_init(void)
 DECLARE_HOOK(HOOK_INIT, uart_rx_dma_init, HOOK_PRIO_DEFAULT);
 #endif
 
-/*****************************************************************************/
-/* Host commands */
-
-static enum ec_status
-host_command_console_snapshot(struct host_cmd_handler_args *args)
-{
-	return uart_console_read_buffer_init();
-}
-DECLARE_HOST_COMMAND(EC_CMD_CONSOLE_SNAPSHOT,
-		     host_command_console_snapshot,
-		     EC_VER_MASK(0));
-
-static enum ec_status
-host_command_console_read(struct host_cmd_handler_args *args)
-{
-	if (args->version == 0) {
-		/*
-		 * Prior versions of this command only support reading from
-		 * an entire snapshot, not just the output since the last
-		 * snapshot.
-		 */
-		return uart_console_read_buffer(
-				CONSOLE_READ_NEXT,
-				(char *)args->response,
-				args->response_max,
-				&args->response_size);
-#ifdef CONFIG_CONSOLE_ENABLE_READ_V1
-	} else if (args->version == 1) {
-		const struct ec_params_console_read_v1 *p;
-
-		/* Check the params to figure out where to start reading. */
-		p = args->params;
-		return uart_console_read_buffer(
-				p->subcmd,
-				(char *)args->response,
-				args->response_max,
-				&args->response_size);
-#endif
-	}
-	return EC_RES_INVALID_PARAM;
-}
-DECLARE_HOST_COMMAND(EC_CMD_CONSOLE_READ,
-		     host_command_console_read,
-		     EC_VER_MASK(0)
-#ifdef CONFIG_CONSOLE_ENABLE_READ_V1
-		     | EC_VER_MASK(1)
-#endif
-		     );
-
 enum ec_status uart_console_read_buffer_init(void)
 {
 	/* Assume the whole circular buffer is full */
@@ -479,9 +347,7 @@ enum ec_status uart_console_read_buffer_init(void)
 	return EC_RES_SUCCESS;
 }
 
-int uart_console_read_buffer(uint8_t type,
-			     char *dest,
-			     uint16_t dest_size,
+int uart_console_read_buffer(uint8_t type, char *dest, uint16_t dest_size,
 			     uint16_t *write_count)
 {
 	int *tail;
@@ -503,7 +369,6 @@ int uart_console_read_buffer(uint8_t type,
 
 	/* Copy data to response */
 	while (*tail != tx_snapshot_head && *write_count < dest_size - 1) {
-
 		/*
 		 * Copy only non-zero bytes, so that we don't copy unused
 		 * bytes if the buffer hasn't completely rolled at boot.
diff --git a/common/uart_hostcmd.c b/common/uart_hostcmd.c
new file mode 100644
index 0000000000..506a49221d
--- /dev/null
+++ b/common/uart_hostcmd.c
@@ -0,0 +1,54 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "config.h"
+#include "ec_commands.h"
+#include "host_command.h"
+#include "uart.h"
+
+static enum ec_status
+host_command_console_snapshot(struct host_cmd_handler_args *args)
+{
+	return uart_console_read_buffer_init();
+}
+DECLARE_HOST_COMMAND(EC_CMD_CONSOLE_SNAPSHOT, host_command_console_snapshot,
+		     EC_VER_MASK(0));
+
+static enum ec_status
+host_command_console_read(struct host_cmd_handler_args *args)
+{
+	if (args->version == 0) {
+		/*
+		 * Prior versions of this command only support reading from
+		 * an entire snapshot, not just the output since the last
+		 * snapshot.
+		 */
+		return uart_console_read_buffer(CONSOLE_READ_NEXT,
+						(char *)args->response,
+						args->response_max,
+						&args->response_size);
+	} else if (IS_ENABLED(CONFIG_CONSOLE_ENABLE_READ_V1) &&
+		   args->version == 1) {
+		const struct ec_params_console_read_v1 *p;
+
+		/* Check the params to figure out where to start reading. */
+		p = args->params;
+		return uart_console_read_buffer(p->subcmd,
+						(char *)args->response,
+						args->response_max,
+						&args->response_size);
+	}
+	return EC_RES_INVALID_PARAM;
+}
+
+#ifdef CONFIG_CONSOLE_ENABLE_READ_V1
+#define READ_V1_MASK EC_VER_MASK(1)
+#else
+#define READ_V1_MASK 0
+#endif
+
+DECLARE_HOST_COMMAND(EC_CMD_CONSOLE_READ, host_command_console_read,
+		     EC_VER_MASK(0) | READ_V1_MASK);
diff --git a/common/uart_printf.c b/common/uart_printf.c
new file mode 100644
index 0000000000..55b8a40cde
--- /dev/null
+++ b/common/uart_printf.c
@@ -0,0 +1,96 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "printf.h"
+#include "uart.h"
+
+#include <stddef.h>
+
+static int __tx_char(void *context, int c)
+{
+	/*
+	 * Translate '\n' to '\r\n'.
+	 */
+	if (c == '\n' && uart_tx_char_raw(context, '\r'))
+		return 1;
+	return uart_tx_char_raw(context, c);
+}
+
+int uart_putc(int c)
+{
+	int rv = __tx_char(NULL, c);
+
+	uart_tx_start();
+
+	return rv ? EC_ERROR_OVERFLOW : EC_SUCCESS;
+}
+
+int uart_puts(const char *outstr)
+{
+	/* Put all characters in the output buffer */
+	for (; *outstr != '\0'; ++outstr) {
+		if (__tx_char(NULL, *outstr) != 0) {
+			break;
+		}
+	}
+
+	uart_tx_start();
+
+	/* Successful if we consumed all output */
+	return *outstr ? EC_ERROR_OVERFLOW : EC_SUCCESS;
+}
+
+int uart_put(const char *out, int len)
+{
+	int written;
+
+	/* Put all characters in the output buffer */
+	for (written = 0; written < len; written++) {
+		if (__tx_char(NULL, *out++) != 0) {
+			break;
+		}
+	}
+
+	uart_tx_start();
+
+	return written;
+}
+
+int uart_put_raw(const char *out, int len)
+{
+	int written;
+
+	/* Put all characters in the output buffer */
+	for (written = 0; written < len; written++) {
+		if (uart_tx_char_raw(NULL, *out++) != 0) {
+			break;
+		}
+	}
+
+	uart_tx_start();
+
+	return written;
+}
+
+int uart_vprintf(const char *format, va_list args)
+{
+	int rv = vfnprintf(__tx_char, NULL, format, args);
+
+	uart_tx_start();
+
+	return rv;
+}
+
+int uart_printf(const char *format, ...)
+{
+	int rv;
+	va_list args;
+
+	va_start(args, format);
+	rv = uart_vprintf(format, args);
+	va_end(args);
+	return rv;
+}
diff --git a/common/update_fw.c b/common/update_fw.c
index bdb432acd6..85b805191c 100644
--- a/common/update_fw.c
+++ b/common/update_fw.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,13 +25,13 @@
 #include "touchpad_fw_hash.h"
 
 BUILD_ASSERT(sizeof(touchpad_fw_hashes) ==
-		(CONFIG_TOUCHPAD_FW_CHUNKS * SHA256_DIGEST_SIZE));
+	     (CONFIG_TOUCHPAD_FW_CHUNKS * SHA256_DIGEST_SIZE));
 BUILD_ASSERT(sizeof(touchpad_fw_hashes[0]) == SHA256_DIGEST_SIZE);
 
 BUILD_ASSERT(sizeof(touchpad_fw_full_hash) == SHA256_DIGEST_SIZE);
 #endif
 
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args)
 
 /* Section to be updated (i.e. not the current section). */
 struct {
@@ -47,9 +47,8 @@ struct {
 static int is_touchpad_block(uint32_t block_offset, size_t body_size)
 {
 	return (block_offset >= CONFIG_TOUCHPAD_VIRTUAL_OFF) &&
-	       (block_offset + body_size) <=
-			(CONFIG_TOUCHPAD_VIRTUAL_OFF +
-				CONFIG_TOUCHPAD_VIRTUAL_SIZE);
+	       (block_offset + body_size) <= (CONFIG_TOUCHPAD_VIRTUAL_OFF +
+					      CONFIG_TOUCHPAD_VIRTUAL_SIZE);
 }
 #endif
 
@@ -71,16 +70,15 @@ static uint8_t check_update_chunk(uint32_t block_offset, size_t body_size)
 	if (update_section.base_offset != update_section.top_offset &&
 	    (block_offset >= update_section.base_offset) &&
 	    ((block_offset + body_size) <= update_section.top_offset)) {
-
 		base = update_section.base_offset;
-		size = update_section.top_offset -
-			 update_section.base_offset;
+		size = update_section.top_offset - update_section.base_offset;
 		/*
 		 * If this is the first chunk for this section, it needs to
 		 * be erased.
 		 */
 		if (block_offset == base) {
-			if (flash_physical_erase(base, size) != EC_SUCCESS) {
+			if (crec_flash_physical_erase(base, size) !=
+			    EC_SUCCESS) {
 				CPRINTF("%s:%d erase failure of 0x%x..+0x%x\n",
 					__func__, __LINE__, base, size);
 				return UPDATE_ERASE_FAILURE;
@@ -95,14 +93,11 @@ static uint8_t check_update_chunk(uint32_t block_offset, size_t body_size)
 		return UPDATE_SUCCESS;
 #endif
 
-	CPRINTF("%s:%d %x, %d section base %x top %x\n",
-		__func__, __LINE__,
-		block_offset, body_size,
-		update_section.base_offset,
+	CPRINTF("%s:%d %x, %d section base %x top %x\n", __func__, __LINE__,
+		block_offset, body_size, update_section.base_offset,
 		update_section.top_offset);
 
 	return UPDATE_BAD_ADDR;
-
 }
 
 int update_pdu_valid(struct update_command *cmd_body, size_t cmd_size)
@@ -119,8 +114,8 @@ static void new_chunk_written(uint32_t block_offset)
 {
 }
 
-static int contents_allowed(uint32_t block_offset,
-			    size_t body_size, void *update_data)
+static int contents_allowed(uint32_t block_offset, size_t body_size,
+			    void *update_data)
 {
 #if defined(CONFIG_TOUCHPAD_VIRTUAL_OFF) && defined(CONFIG_TOUCHPAD_HASH_FW)
 	if (is_touchpad_block(block_offset, body_size)) {
@@ -131,9 +126,9 @@ static int contents_allowed(uint32_t block_offset,
 		int good = 0;
 
 		if (chunk >= CONFIG_TOUCHPAD_FW_CHUNKS ||
-				(fw_offset % CONFIG_UPDATE_PDU_SIZE) != 0) {
-			CPRINTF("%s: TP invalid offset %08x\n",
-				__func__, fw_offset);
+		    (fw_offset % CONFIG_UPDATE_PDU_SIZE) != 0) {
+			CPRINTF("%s: TP invalid offset %08x\n", __func__,
+				fw_offset);
 			return 0;
 		}
 
@@ -142,10 +137,10 @@ static int contents_allowed(uint32_t block_offset,
 		tmp = SHA256_final(&ctx);
 
 		good = !memcmp(tmp, touchpad_fw_hashes[chunk],
-				SHA256_DIGEST_SIZE);
+			       SHA256_DIGEST_SIZE);
 
-		CPRINTF("%s: TP %08x %02x..%02x (%s)\n", __func__,
-			fw_offset, tmp[0], tmp[31], good ? "GOOD" : "BAD");
+		CPRINTF("%s: TP %08x %02x..%02x (%s)\n", __func__, fw_offset,
+			tmp[0], tmp[31], good ? "GOOD" : "BAD");
 
 		return good;
 	}
@@ -189,11 +184,11 @@ void fw_update_start(struct first_response_pdu *rpdu)
 	}
 
 	rpdu->common.maximum_pdu_size = htobe32(CONFIG_UPDATE_PDU_SIZE);
-	rpdu->common.flash_protection = htobe32(flash_get_protect());
+	rpdu->common.flash_protection = htobe32(crec_flash_get_protect());
 	rpdu->common.offset = htobe32(update_section.base_offset);
 	if (version)
 		memcpy(rpdu->common.version, version,
-			sizeof(rpdu->common.version));
+		       sizeof(rpdu->common.version));
 
 #ifdef CONFIG_ROLLBACK
 	rpdu->common.min_rollback = htobe32(rollback_get_minimum_version());
@@ -215,13 +210,12 @@ void fw_update_start(struct first_response_pdu *rpdu)
 #endif
 }
 
-void fw_update_command_handler(void *body,
-			       size_t cmd_size,
+void fw_update_command_handler(void *body, size_t cmd_size,
 			       size_t *response_size)
 {
 	struct update_command *cmd_body = body;
 	void *update_data;
-	uint8_t *error_code = body;  /* Cache the address for code clarity. */
+	uint8_t *error_code = body; /* Cache the address for code clarity. */
 	size_t body_size;
 	uint32_t block_offset;
 
@@ -284,11 +278,11 @@ void fw_update_command_handler(void *body,
 #ifdef CONFIG_TOUCHPAD_VIRTUAL_OFF
 	if (is_touchpad_block(block_offset, body_size)) {
 		if (touchpad_update_write(
-				block_offset - CONFIG_TOUCHPAD_VIRTUAL_OFF,
-				body_size, update_data)	!= EC_SUCCESS) {
+			    block_offset - CONFIG_TOUCHPAD_VIRTUAL_OFF,
+			    body_size, update_data) != EC_SUCCESS) {
 			*error_code = UPDATE_WRITE_FAILURE;
-			CPRINTF("%s:%d update write error\n",
-				__func__, __LINE__);
+			CPRINTF("%s:%d update write error\n", __func__,
+				__LINE__);
 			return;
 		}
 
@@ -300,8 +294,8 @@ void fw_update_command_handler(void *body,
 #endif
 
 	CPRINTF("update: 0x%x\n", block_offset + CONFIG_PROGRAM_MEMORY_BASE);
-	if (flash_physical_write(block_offset, body_size, update_data)
-	    != EC_SUCCESS) {
+	if (crec_flash_physical_write(block_offset, body_size, update_data) !=
+	    EC_SUCCESS) {
 		*error_code = UPDATE_WRITE_FAILURE;
 		CPRINTF("%s:%d update write error\n", __func__, __LINE__);
 		return;
@@ -310,12 +304,12 @@ void fw_update_command_handler(void *body,
 	new_chunk_written(block_offset);
 
 	/* Verify that data was written properly. */
-	if (memcmp(update_data, (void *)
-		   (block_offset + CONFIG_PROGRAM_MEMORY_BASE),
+	if (memcmp(update_data,
+		   (void *)(block_offset + CONFIG_PROGRAM_MEMORY_BASE),
 		   body_size)) {
 		*error_code = UPDATE_VERIFY_ERROR;
-		CPRINTF("%s:%d update verification error\n",
-			__func__, __LINE__);
+		CPRINTF("%s:%d update verification error\n", __func__,
+			__LINE__);
 		return;
 	}
 
diff --git a/common/uptime.c b/common/uptime.c
index 2fdd8bdb19..1ce7e2a329 100644
--- a/common/uptime.c
+++ b/common/uptime.c
@@ -1,14 +1,14 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
-#include <stddef.h>
-
 #include "chipset.h"
-#include "system.h"
 #include "host_command.h"
+#include "system.h"
 #include "util.h"
 
+#include <stddef.h>
+
 static enum ec_status
 host_command_get_uptime_info(struct host_cmd_handler_args *args)
 {
@@ -24,19 +24,20 @@ host_command_get_uptime_info(struct host_cmd_handler_args *args)
 	struct ec_response_uptime_info *r = args->response;
 	timestamp_t now = get_time();
 	uint32_t now_ms = (uint32_t)(now.val / MSEC);
+	void *recent_ap_reset = r->recent_ap_reset;
+	uint32_t ap_resets_since_ec_boot = 0;
 	enum ec_error_list rc;
 
 	r->time_since_ec_boot_ms = now_ms;
 	r->ec_reset_flags = system_get_reset_flags();
 
 	memset(r->recent_ap_reset, 0, sizeof(r->recent_ap_reset));
-	rc = get_ap_reset_stats(r->recent_ap_reset,
-				ARRAY_SIZE(r->recent_ap_reset),
-				&r->ap_resets_since_ec_boot);
+	rc = get_ap_reset_stats(recent_ap_reset, ARRAY_SIZE(r->recent_ap_reset),
+				&ap_resets_since_ec_boot);
 
+	r->ap_resets_since_ec_boot = ap_resets_since_ec_boot;
 	args->response_size = sizeof(*r);
 	return rc == EC_SUCCESS ? EC_RES_SUCCESS : EC_RES_ERROR;
 }
-DECLARE_HOST_COMMAND(EC_CMD_GET_UPTIME_INFO,
-	host_command_get_uptime_info,
-	EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_GET_UPTIME_INFO, host_command_get_uptime_info,
+		     EC_VER_MASK(0));
diff --git a/common/usb_charger.c b/common/usb_charger.c
index a8396b47bd..1452ada079 100644
--- a/common/usb_charger.c
+++ b/common/usb_charger.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,6 +12,7 @@
  * is necessary to update charge_manager with detected charger attributes.
  */
 
+#include "builtin/assert.h"
 #include "charge_manager.h"
 #include "charger.h"
 #include "common.h"
@@ -22,12 +23,33 @@
 #include "task.h"
 #include "usb_charge.h"
 #include "usb_pd.h"
+#include "usb_pd_flags.h"
 #include "usbc_ppc.h"
 #include "util.h"
 
+#ifdef CONFIG_PLATFORM_EC_USB_CHARGER_SINGLE_TASK
+
+/* Hold the event bits for all ports, 1 byte per port. */
+static atomic_t usb_charger_port_events;
+
+/* Convert event bits for port so it can be stored in a 32 bit value. */
+#define PORT_EVENT_PACK(port, event) ((event & 0xff) << (8 * port))
+
+/* Extract the event bits for port from a 32 bit value. */
+#define PORT_EVENT_UNPACK(port, event_packed) \
+	((event_packed >> (8 * port)) & 0xff)
+
+/* Ensure port event bits are valid. */
+BUILD_ASSERT(BIT(0) == TASK_EVENT_CUSTOM_BIT(0));
+BUILD_ASSERT(BIT(1) == TASK_EVENT_CUSTOM_BIT(1));
+BUILD_ASSERT(BIT(2) == TASK_EVENT_CUSTOM_BIT(2));
+BUILD_ASSERT(BIT(3) == TASK_EVENT_CUSTOM_BIT(3));
+
+#endif /* CONFIG_PLATFORM_EC_USB_CHARGER_SINGLE_TASK */
+
 static void update_vbus_supplier(int port, int vbus_level)
 {
-	struct charge_port_info charge = {0};
+	struct charge_port_info charge = { 0 };
 
 	if (vbus_level && !usb_charger_port_is_sourcing_vbus(port)) {
 		charge.voltage = USB_CHARGER_VOLTAGE_MV;
@@ -41,6 +63,8 @@ static void update_vbus_supplier(int port, int vbus_level)
 #define USB_5V_EN(port) board_is_sourcing_vbus(port)
 #elif defined(CONFIG_USBC_PPC)
 #define USB_5V_EN(port) ppc_is_sourcing_vbus(port)
+#elif defined(CONFIG_USB_PD_PPC)
+#define USB_5V_EN(port) tcpci_tcpm_get_src_ctrl(port)
 #elif defined(CONFIG_USB_PD_5V_CHARGER_CTRL)
 #define USB_5V_EN(port) charger_is_sourcing_otg_power(port)
 #elif defined(CONFIG_USB_PD_5V_EN_ACTIVE_LOW)
@@ -70,43 +94,52 @@ void usb_charger_vbus_change(int port, int vbus_level)
 	/* Update VBUS supplier and signal VBUS change to USB_CHG task */
 	update_vbus_supplier(port, vbus_level);
 
-#ifdef HAS_TASK_USB_CHG_P0
+#if defined(HAS_TASK_USB_CHG_P0) || \
+	defined(CONFIG_PLATFORM_EC_USB_CHARGER_SINGLE_TASK)
 	/* USB Charger task(s) */
-	task_set_event(USB_CHG_PORT_TO_TASK_ID(port), USB_CHG_EVENT_VBUS, 0);
-#endif
+	usb_charger_task_set_event(port, USB_CHG_EVENT_VBUS);
 
-#if (defined(CONFIG_USB_PD_VBUS_DETECT_CHARGER) \
-	|| defined(CONFIG_USB_PD_VBUS_DETECT_PPC))
-	/* USB PD task */
-	task_wake(PD_PORT_TO_TASK_ID(port));
+	/* If we swapped to sourcing, drop any related charge suppliers */
+	if (usb_charger_port_is_sourcing_vbus(port))
+		usb_charger_reset_charge(port);
 #endif
+
+	if ((get_usb_pd_vbus_detect() == USB_PD_VBUS_DETECT_CHARGER) ||
+	    (get_usb_pd_vbus_detect() == USB_PD_VBUS_DETECT_PPC)) {
+		/* USB PD task */
+		task_wake(PD_PORT_TO_TASK_ID(port));
+	}
 }
 
 void usb_charger_reset_charge(int port)
 {
-	charge_manager_update_charge(CHARGE_SUPPLIER_PROPRIETARY,
-				     port, NULL);
-	charge_manager_update_charge(CHARGE_SUPPLIER_BC12_CDP,
-				     port, NULL);
-	charge_manager_update_charge(CHARGE_SUPPLIER_BC12_DCP,
-				     port, NULL);
-	charge_manager_update_charge(CHARGE_SUPPLIER_BC12_SDP,
-				     port, NULL);
-	charge_manager_update_charge(CHARGE_SUPPLIER_OTHER,
-				     port, NULL);
+	charge_manager_update_charge(CHARGE_SUPPLIER_PROPRIETARY, port, NULL);
+	charge_manager_update_charge(CHARGE_SUPPLIER_BC12_CDP, port, NULL);
+	charge_manager_update_charge(CHARGE_SUPPLIER_BC12_DCP, port, NULL);
+	charge_manager_update_charge(CHARGE_SUPPLIER_BC12_SDP, port, NULL);
+	charge_manager_update_charge(CHARGE_SUPPLIER_OTHER, port, NULL);
 #if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
-	charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED,
-				     port, NULL);
+	charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED, port, NULL);
 #endif
-#ifdef CONFIG_WIRELESS_CHARGER_P9221_R7
-	charge_manager_update_charge(CHARGE_SUPPLIER_WPC_BPP,
-				     port, NULL);
-	charge_manager_update_charge(CHARGE_SUPPLIER_WPC_EPP,
-				     port, NULL);
-	charge_manager_update_charge(CHARGE_SUPPLIER_WPC_GPP,
-				     port, NULL);
+}
+
+void usb_charger_task_set_event(int port, uint8_t event)
+{
+#ifdef CONFIG_PLATFORM_EC_USB_CHARGER_SINGLE_TASK
+	atomic_or(&usb_charger_port_events, PORT_EVENT_PACK(port, event));
+	task_set_event(TASK_ID_USB_CHG, BIT(port));
+#else
+	task_set_event(USB_CHG_PORT_TO_TASK_ID(port), event);
 #endif
+}
 
+void usb_charger_task_set_event_sync(int port, uint8_t event)
+{
+	struct bc12_config *bc12_port;
+
+	bc12_port = &bc12_ports[port];
+
+	bc12_port->drv->usb_charger_task_event(port, event);
 }
 
 static void usb_charger_init(void)
@@ -118,12 +151,71 @@ static void usb_charger_init(void)
 		update_vbus_supplier(i, pd_is_vbus_present(i));
 	}
 }
-DECLARE_HOOK(HOOK_INIT, usb_charger_init, HOOK_PRIO_CHARGE_MANAGER_INIT + 1);
+DECLARE_HOOK(HOOK_INIT, usb_charger_init, HOOK_PRIO_POST_CHARGE_MANAGER);
+
+#ifdef CONFIG_PLATFORM_EC_USB_CHARGER_SINGLE_TASK
+
+void usb_charger_task_shared(void *u)
+{
+	int port;
+	uint32_t evt;
+	uint32_t port_evt;
+	struct bc12_config *bc12_port;
+
+	for (port = 0; port < board_get_usb_pd_port_count(); port++) {
+		bc12_port = &bc12_ports[port];
+
+		ASSERT(bc12_port->drv->usb_charger_task_init);
+		ASSERT(bc12_port->drv->usb_charger_task_event);
+
+		bc12_port->drv->usb_charger_task_init(port);
+	}
+
+	while (1) {
+		evt = task_wait_event(-1);
+
+		for (port = 0; port < board_get_usb_pd_port_count(); port++) {
+			if (!(evt & BIT(port))) {
+				continue;
+			}
+
+			port_evt = PORT_EVENT_UNPACK(
+				port, atomic_get(&usb_charger_port_events));
+			atomic_and(&usb_charger_port_events,
+				   ~PORT_EVENT_PACK(port, port_evt));
+
+			usb_charger_task_set_event_sync(port, port_evt);
+		}
+	}
+}
+
+#else /* CONFIG_PLATFORM_EC_USB_CHARGER_SINGLE_TASK */
 
 void usb_charger_task(void *u)
 {
 	int port = TASK_ID_TO_USB_CHG_PORT(task_get_current());
+	uint32_t evt;
+	struct bc12_config *bc12_port;
+
+	/*
+	 * The actual number of ports may be less than the maximum
+	 * configured, so only run the task if the port exists.
+	 */
+	if (port >= board_get_usb_pd_port_count())
+		return;
+
+	bc12_port = &bc12_ports[port];
+
+	ASSERT(bc12_port->drv->usb_charger_task_init);
+	ASSERT(bc12_port->drv->usb_charger_task_event);
 
-	ASSERT(bc12_ports[port].drv->usb_charger_task);
-	bc12_ports[port].drv->usb_charger_task(port);
+	bc12_port->drv->usb_charger_task_init(port);
+
+	while (1) {
+		evt = task_wait_event(-1);
+
+		usb_charger_task_set_event_sync(port, evt);
+	}
 }
+
+#endif /* CONFIG_PLATFORM_EC_USB_CHARGER_SINGLE_TASK */
diff --git a/common/usb_common.c b/common/usb_common.c
index 47b0bc9454..259b503b16 100644
--- a/common/usb_common.c
+++ b/common/usb_common.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,110 +15,83 @@
 #include "common.h"
 #include "console.h"
 #include "ec_commands.h"
+#include "gpio.h"
 #include "hooks.h"
-#include "stdbool.h"
 #include "host_command.h"
+#include "mkbp_event.h"
+#include "stdbool.h"
 #include "system.h"
 #include "task.h"
+#include "typec_control.h"
 #include "usb_api.h"
 #include "usb_common.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
+#include "usb_pd_dpm_sm.h"
+#include "usb_pd_flags.h"
 #include "usb_pd_tcpm.h"
+#include "usb_pe_sm.h"
+#include "usbc_ocp.h"
 #include "usbc_ppc.h"
 #include "util.h"
 
+/*
+ * TODO(b/272518464): Work around coreboot GCC preprocessor bug.
+ * #line marks the *next* line, so it is off by one.
+ */
+#line 43
+
 #ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
 #else
 #define CPRINTS(format, args...)
 #define CPRINTF(format, args...)
 #endif
 
-__overridable void board_vbus_present_change(void)
-{
-}
-
-#if defined(CONFIG_CMD_PD) && defined(CONFIG_CMD_PD_FLASH)
-int hex8tou32(char *str, uint32_t *val)
-{
-	char *ptr = str;
-	uint32_t tmp = 0;
-
-	while (*ptr) {
-		char c = *ptr++;
+/*
+ * If we are trying to upgrade PD firmwares (TCPC chips, retimer, etc), we
+ * need to ensure the battery has enough charge for this process. Set the
+ * threshold to 10%, and it should be enough charge to get us
+ * through the EC jump to RW and PD upgrade.
+ */
+#define MIN_BATTERY_FOR_PD_UPGRADE_PERCENT 10 /* % */
 
-		if (c >= '0' && c <= '9')
-			tmp = (tmp << 4) + (c - '0');
-		else if (c >= 'A' && c <= 'F')
-			tmp = (tmp << 4) + (c - 'A' + 10);
-		else if (c >= 'a' && c <= 'f')
-			tmp = (tmp << 4) + (c - 'a' + 10);
-		else
-			return EC_ERROR_INVAL;
-	}
-	if (ptr != str + 8)
-		return EC_ERROR_INVAL;
-	*val = tmp;
-	return EC_SUCCESS;
-}
+#ifdef CONFIG_COMMON_RUNTIME
+struct ec_params_usb_pd_rw_hash_entry rw_hash_table[RW_HASH_ENTRIES];
+#endif /* CONFIG_COMMON_RUNTIME */
 
-int remote_flashing(int argc, char **argv)
+bool pd_firmware_upgrade_check_power_readiness(int port)
 {
-	int port, cnt, cmd;
-	uint32_t data[VDO_MAX_SIZE-1];
-	char *e;
-	static int flash_offset[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-	if (argc < 4 || argc > (VDO_MAX_SIZE + 4 - 1))
-		return EC_ERROR_PARAM_COUNT;
-
-	port = strtoi(argv[1], &e, 10);
-	if (*e || port >= board_get_usb_pd_port_count())
-		return EC_ERROR_PARAM2;
-
-	cnt = 0;
-	if (!strcasecmp(argv[3], "erase")) {
-		cmd = VDO_CMD_FLASH_ERASE;
-		flash_offset[port] = 0;
-		ccprintf("ERASE ...");
-	} else if (!strcasecmp(argv[3], "reboot")) {
-		cmd = VDO_CMD_REBOOT;
-		ccprintf("REBOOT ...");
-	} else if (!strcasecmp(argv[3], "signature")) {
-		cmd = VDO_CMD_ERASE_SIG;
-		ccprintf("ERASE SIG ...");
-	} else if (!strcasecmp(argv[3], "info")) {
-		cmd = VDO_CMD_READ_INFO;
-		ccprintf("INFO...");
-	} else if (!strcasecmp(argv[3], "version")) {
-		cmd = VDO_CMD_VERSION;
-		ccprintf("VERSION...");
+	if (IS_ENABLED(HAS_TASK_CHARGER)) {
+		struct batt_params batt = { 0 };
+		/*
+		 * Cannot rely on the EC's active charger data as the
+		 * EC may just rebooted into RW and has not necessarily
+		 * picked the active charger yet. Charger task may not
+		 * initialized, so check battery directly.
+		 * Prevent the upgrade if the battery doesn't have enough
+		 * charge to finish the upgrade.
+		 */
+		battery_get_params(&batt);
+		if (batt.flags & BATT_FLAG_BAD_STATE_OF_CHARGE ||
+		    batt.state_of_charge < MIN_BATTERY_FOR_PD_UPGRADE_PERCENT) {
+			CPRINTS("C%d: Cannot suspend for upgrade, not "
+				"enough battery (%d%%)!",
+				port, batt.state_of_charge);
+			return false;
+		}
 	} else {
-		int i;
-
-		argc -= 3;
-		for (i = 0; i < argc; i++)
-			if (hex8tou32(argv[i+3], data + i))
-				return EC_ERROR_INVAL;
-		cmd = VDO_CMD_FLASH_WRITE;
-		cnt = argc;
-		ccprintf("WRITE %d @%04x ...", argc * 4,
-			 flash_offset[port]);
-		flash_offset[port] += argc * 4;
+		/* VBUS is present on the port (it is either a
+		 * source or sink) to provide power, so don't allow
+		 * PD firmware upgrade on the port.
+		 */
+		if (pd_is_vbus_present(port))
+			return false;
 	}
 
-	pd_send_vdm(port, USB_VID_GOOGLE, cmd, data, cnt);
-
-	/* Wait until VDM is done */
-	while (pd[port].vdm_state > 0)
-		task_wait_event(100*MSEC);
-
-	ccprintf("DONE %d\n", pd[port].vdm_state);
-	return EC_SUCCESS;
+	return true;
 }
-#endif /* defined(CONFIG_CMD_PD) && defined(CONFIG_CMD_PD_FLASH) */
 
 int usb_get_battery_soc(void)
 {
@@ -131,8 +104,8 @@ int usb_get_battery_soc(void)
 #endif
 }
 
-#if defined(CONFIG_USB_PD_PREFER_MV) && defined(PD_PREFER_LOW_VOLTAGE) + \
-	defined(PD_PREFER_HIGH_VOLTAGE) > 1
+#if defined(CONFIG_USB_PD_PREFER_MV) && \
+	defined(PD_PREFER_LOW_VOLTAGE) + defined(PD_PREFER_HIGH_VOLTAGE) > 1
 #error "PD preferred voltage strategy should be mutually exclusive."
 #endif
 
@@ -150,7 +123,8 @@ int usb_get_battery_soc(void)
  */
 
 typec_current_t usb_get_typec_current_limit(enum tcpc_cc_polarity polarity,
-	enum tcpc_cc_voltage_status cc1, enum tcpc_cc_voltage_status cc2)
+					    enum tcpc_cc_voltage_status cc1,
+					    enum tcpc_cc_voltage_status cc2)
 {
 	typec_current_t charge = 0;
 	enum tcpc_cc_voltage_status cc;
@@ -186,7 +160,7 @@ typec_current_t usb_get_typec_current_limit(enum tcpc_cc_polarity polarity,
 }
 
 enum tcpc_cc_polarity get_snk_polarity(enum tcpc_cc_voltage_status cc1,
-	enum tcpc_cc_voltage_status cc2)
+				       enum tcpc_cc_voltage_status cc2)
 {
 	/* The following assumes:
 	 *
@@ -201,13 +175,13 @@ enum tcpc_cc_polarity get_snk_polarity(enum tcpc_cc_voltage_status cc1,
 }
 
 enum tcpc_cc_polarity get_src_polarity(enum tcpc_cc_voltage_status cc1,
-	enum tcpc_cc_voltage_status cc2)
+				       enum tcpc_cc_voltage_status cc2)
 {
 	return (cc1 == TYPEC_CC_VOLT_RD) ? POLARITY_CC1 : POLARITY_CC2;
 }
 
-enum pd_cc_states pd_get_cc_state(
-	enum tcpc_cc_voltage_status cc1, enum tcpc_cc_voltage_status cc2)
+enum pd_cc_states pd_get_cc_state(enum tcpc_cc_voltage_status cc1,
+				  enum tcpc_cc_voltage_status cc2)
 {
 	/* Port partner is a SNK */
 	if (cc_is_snk_dbg_acc(cc1, cc2))
@@ -230,29 +204,27 @@ enum pd_cc_states pd_get_cc_state(
 	return PD_CC_NONE;
 }
 
-/**
- * This function checks the current CC status of the port partner
- * and returns true if the attached partner is debug accessory.
- */
-bool pd_is_debug_acc(int port)
+__overridable int pd_board_check_request(uint32_t rdo, int pdo_cnt)
 {
-	enum pd_cc_states cc_state = pd_get_task_cc_state(port);
-
-	return cc_state == PD_CC_UFP_DEBUG_ACC ||
-		cc_state == PD_CC_DFP_DEBUG_ACC;
+	return EC_SUCCESS;
 }
 
-void pd_set_polarity(int port, enum tcpc_cc_polarity polarity)
+int pd_get_source_pdo(const uint32_t **src_pdo_p, const int port)
 {
-	tcpm_set_polarity(port, polarity);
-
-	if (IS_ENABLED(CONFIG_USBC_PPC_POLARITY))
-		ppc_set_polarity(port, polarity);
-}
+#if defined(CONFIG_USB_PD_TCPMV2) && defined(CONFIG_USB_PE_SM)
+	const uint32_t *src_pdo;
+	const int pdo_cnt = dpm_get_source_pdo(&src_pdo, port);
+#elif defined(CONFIG_USB_PD_DYNAMIC_SRC_CAP) || \
+	defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT)
+	const uint32_t *src_pdo;
+	const int pdo_cnt = charge_manager_get_source_pdo(&src_pdo, port);
+#else
+	const uint32_t *src_pdo = pd_src_pdo;
+	const int pdo_cnt = pd_src_pdo_cnt;
+#endif
 
-__overridable int pd_board_check_request(uint32_t rdo, int pdo_cnt)
-{
-	return EC_SUCCESS;
+	*src_pdo_p = src_pdo;
+	return pdo_cnt;
 }
 
 int pd_check_requested_voltage(uint32_t rdo, const int port)
@@ -262,14 +234,10 @@ int pd_check_requested_voltage(uint32_t rdo, const int port)
 	int idx = RDO_POS(rdo);
 	uint32_t pdo;
 	uint32_t pdo_ma;
-#if defined(CONFIG_USB_PD_DYNAMIC_SRC_CAP) || \
-		defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT)
 	const uint32_t *src_pdo;
-	const int pdo_cnt = charge_manager_get_source_pdo(&src_pdo, port);
-#else
-	const uint32_t *src_pdo = pd_src_pdo;
-	const int pdo_cnt = pd_src_pdo_cnt;
-#endif
+	int pdo_cnt;
+
+	pdo_cnt = pd_get_source_pdo(&src_pdo, port);
 
 	/* Check for invalid index */
 	if (!idx || idx > pdo_cnt)
@@ -290,8 +258,8 @@ int pd_check_requested_voltage(uint32_t rdo, const int port)
 		return EC_ERROR_INVAL; /* too much max current */
 
 	CPRINTF("Requested %d mV %d mA (for %d/%d mA)\n",
-		 ((pdo >> 10) & 0x3ff) * 50, (pdo & 0x3ff) * 10,
-		 op_ma * 10, max_ma * 10);
+		((pdo >> 10) & 0x3ff) * 50, (pdo & 0x3ff) * 10, op_ma * 10,
+		max_ma * 10);
 
 	/* Accept the requested voltage */
 	return EC_SUCCESS;
@@ -302,20 +270,39 @@ __overridable uint8_t board_get_usb_pd_port_count(void)
 	return CONFIG_USB_PD_PORT_MAX_COUNT;
 }
 
+__overridable bool board_is_usb_pd_port_present(int port)
+{
+	/*
+	 * Use board_get_usb_pd_port_count() instead of checking
+	 * CONFIG_USB_PD_PORT_MAX_COUNT directly here for legacy boards
+	 * that implement board_get_usb_pd_port_count() but do not
+	 * implement board_is_usb_pd_port_present().
+	 */
+
+	return (port >= 0) && (port < board_get_usb_pd_port_count());
+}
+
+__overridable bool board_is_dts_port(int port)
+{
+	return true;
+}
+
+int pd_get_retry_count(int port, enum tcpci_msg_type type)
+{
+	/* PD 3.0 6.7.7: nRetryCount = 2; PD 2.0 6.6.9: nRetryCount = 3 */
+	return pd_get_rev(port, type) == PD_REV30 ? 2 : 3;
+}
+
 enum pd_drp_next_states drp_auto_toggle_next_state(
-	uint64_t *drp_sink_time,
-	enum pd_power_role power_role,
-	enum pd_dual_role_states drp_state,
-	enum tcpc_cc_voltage_status cc1,
-	enum tcpc_cc_voltage_status cc2,
-	bool auto_toggle_supported)
+	uint64_t *drp_sink_time, enum pd_power_role power_role,
+	enum pd_dual_role_states drp_state, enum tcpc_cc_voltage_status cc1,
+	enum tcpc_cc_voltage_status cc2, bool auto_toggle_supported)
 {
 	const bool hardware_debounced_unattached =
-				((drp_state == PD_DRP_TOGGLE_ON) &&
-				 auto_toggle_supported);
+		((drp_state == PD_DRP_TOGGLE_ON) && auto_toggle_supported);
 
 	/* Set to appropriate port state */
-	if (cc_is_open(cc1, cc2)) {
+	if (cc_is_open(cc1, cc2) || cc_is_pwred_cbl_without_snk(cc1, cc2)) {
 		/*
 		 * If nothing is attached then use drp_state to determine next
 		 * state. If DRP auto toggle is still on, then remain in the
@@ -346,13 +333,13 @@ enum pd_drp_next_states drp_auto_toggle_next_state(
 			return DRP_TC_DRP_AUTO_TOGGLE;
 		}
 	} else if ((cc_is_rp(cc1) || cc_is_rp(cc2)) &&
-		drp_state != PD_DRP_FORCE_SOURCE) {
+		   drp_state != PD_DRP_FORCE_SOURCE) {
 		/* SNK allowed unless ForceSRC */
 		if (hardware_debounced_unattached)
 			return DRP_TC_ATTACHED_WAIT_SNK;
 		return DRP_TC_UNATTACHED_SNK;
 	} else if (cc_is_at_least_one_rd(cc1, cc2) ||
-					cc_is_audio_acc(cc1, cc2)) {
+		   cc_is_audio_acc(cc1, cc2)) {
 		/*
 		 * SRC allowed unless ForceSNK or Toggle Off
 		 *
@@ -368,10 +355,10 @@ enum pd_drp_next_states drp_auto_toggle_next_state(
 		 * ready for a new connection.
 		 */
 		if (drp_state == PD_DRP_TOGGLE_OFF ||
-			drp_state == PD_DRP_FORCE_SINK) {
-			if (get_time().val > *drp_sink_time + 200*MSEC)
+		    drp_state == PD_DRP_FORCE_SINK) {
+			if (get_time().val > *drp_sink_time + 200 * MSEC)
 				*drp_sink_time = get_time().val;
-			if (get_time().val < *drp_sink_time + 100*MSEC)
+			if (get_time().val < *drp_sink_time + 100 * MSEC)
 				return DRP_TC_UNATTACHED_SNK;
 			else
 				return DRP_TC_DRP_AUTO_TOGGLE;
@@ -393,13 +380,18 @@ enum pd_drp_next_states drp_auto_toggle_next_state(
 	}
 }
 
+__overridable bool usb_ufp_check_usb3_enable(int port)
+{
+	return false;
+}
+
 mux_state_t get_mux_mode_to_set(int port)
 {
 	/*
 	 * If the SoC is down, then we disconnect the MUX to save power since
 	 * no one cares about the data lines.
 	 */
-	if (IS_ENABLED(CONFIG_POWER_COMMON) &&
+	if (IS_ENABLED(CONFIG_AP_POWER_CONTROL) &&
 	    chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF))
 		return USB_PD_MUX_NONE;
 
@@ -412,18 +404,42 @@ mux_state_t get_mux_mode_to_set(int port)
 	if (pd_is_disconnected(port))
 		return USB_PD_MUX_NONE;
 
+	/*
+	 * For type-c only connections, there may be a need to enable USB3.1
+	 * mode when the port is in a UFP data role, independent of any other
+	 * conditions which are checked below. The default function returns
+	 * false, so only boards that override this check will be affected.
+	 */
+	if (usb_ufp_check_usb3_enable(port) &&
+	    pd_get_data_role(port) == PD_ROLE_UFP)
+		return USB_PD_MUX_USB_ENABLED;
+
 	/* If new data role isn't DFP & we only support DFP, also disconnect. */
 	if (IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE) &&
 	    IS_ENABLED(CONFIG_USBC_SS_MUX_DFP_ONLY) &&
 	    pd_get_data_role(port) != PD_ROLE_DFP)
 		return USB_PD_MUX_NONE;
 
+	/* If new data role isn't UFP & we only support UFP then disconnect. */
+	if (IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE) &&
+	    IS_ENABLED(CONFIG_USBC_SS_MUX_UFP_ONLY) &&
+	    pd_get_data_role(port) != PD_ROLE_UFP)
+		return USB_PD_MUX_NONE;
+
 	/*
-	 * If the power role is sink and the partner device is not capable
+	 * If the power role is sink and the PD partner device is not capable
 	 * of USB communication then disconnect.
+	 *
+	 * On an entry into Unattached.SNK, the partner may be PD capable but
+	 * hasn't yet sent source capabilities. In this case, hold off enabling
+	 * USB3 termination until the PD capability is resolved.
+	 *
+	 * TODO(b/188588458): TCPMv2: Delay enabling USB3 termination when USB4
+	 * is supported.
 	 */
 	if (IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE) &&
 	    pd_get_power_role(port) == PD_ROLE_SINK &&
+	    (pd_capable(port) || pd_waiting_on_partner_src_caps(port)) &&
 	    !pd_get_partner_usb_comm_capable(port))
 		return USB_PD_MUX_NONE;
 
@@ -436,85 +452,66 @@ void set_usb_mux_with_current_data_role(int port)
 	if (IS_ENABLED(CONFIG_USBC_SS_MUX)) {
 		mux_state_t mux_mode = get_mux_mode_to_set(port);
 		enum usb_switch usb_switch_mode =
-				(mux_mode == USB_PD_MUX_NONE) ?
-				USB_SWITCH_DISCONNECT : USB_SWITCH_CONNECT;
+			(mux_mode == USB_PD_MUX_NONE) ? USB_SWITCH_DISCONNECT :
+							USB_SWITCH_CONNECT;
 
 		usb_mux_set(port, mux_mode, usb_switch_mode,
-				pd_get_polarity(port));
+			    polarity_rm_dts(pd_get_polarity(port)));
 	}
 }
 
 void usb_mux_set_safe_mode(int port)
 {
 	if (IS_ENABLED(CONFIG_USBC_SS_MUX)) {
-		usb_mux_set(port, IS_ENABLED(CONFIG_USB_MUX_VIRTUAL) ?
-			USB_PD_MUX_SAFE_MODE : USB_PD_MUX_NONE,
-			USB_SWITCH_CONNECT, pd_get_polarity(port));
+		usb_mux_set(port, USB_PD_MUX_SAFE_MODE, USB_SWITCH_CONNECT,
+			    polarity_rm_dts(pd_get_polarity(port)));
 	}
 
 	/* Isolate the SBU lines. */
-	if (IS_ENABLED(CONFIG_USBC_PPC_SBU))
-		ppc_set_sbu(port, 0);
+	typec_set_sbu(port, false);
 }
 
-static void pd_send_hard_reset(int port)
+void usb_mux_set_safe_mode_exit(int port)
 {
-	task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_SEND_HARD_RESET, 0);
-}
-
-#ifdef CONFIG_USBC_PPC
+	if (IS_ENABLED(CONFIG_USBC_SS_MUX))
+		usb_mux_set(port, USB_PD_MUX_NONE, USB_SWITCH_CONNECT,
+			    polarity_rm_dts(pd_get_polarity(port)));
 
-static uint32_t port_oc_reset_req;
+	/* Isolate the SBU lines. */
+	typec_set_sbu(port, false);
+}
 
-static void re_enable_ports(void)
+void pd_send_hard_reset(int port)
 {
-	uint32_t ports = deprecated_atomic_read_clear(&port_oc_reset_req);
-
-	while (ports) {
-		int port = __fls(ports);
-
-		ports &= ~BIT(port);
-
-		/*
-		 * Let the board know that the overcurrent is
-		 * over since we're going to attempt re-enabling
-		 * the port.
-		 */
-		board_overcurrent_event(port, 0);
-
-		pd_send_hard_reset(port);
-		/*
-		 * TODO(b/117854867): PD3.0 to send an alert message
-		 * indicating OCP after explicit contract.
-		 */
-	}
+	task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_SEND_HARD_RESET);
 }
-DECLARE_DEFERRED(re_enable_ports);
 
+#ifdef CONFIG_USBC_OCP
 void pd_handle_overcurrent(int port)
 {
+	if ((port < 0) || (port >= board_get_usb_pd_port_count())) {
+		CPRINTS("%s(%d) Invalid port!", __func__, port);
+		return;
+	}
+
 	CPRINTS("C%d: overcurrent!", port);
 
 	if (IS_ENABLED(CONFIG_USB_PD_LOGGING))
 		pd_log_event(PD_EVENT_PS_FAULT, PD_LOG_PORT_SIZE(port, 0),
-			PS_FAULT_OCP, NULL);
+			     PS_FAULT_OCP, NULL);
 
 	/* No action to take if disconnected, just log. */
 	if (pd_is_disconnected(port))
 		return;
 
-	/* Keep track of the overcurrent events. */
-	ppc_add_oc_event(port);
-
-	/* Let the board specific code know about the OC event. */
-	board_overcurrent_event(port, 1);
-
-	/* Wait 1s before trying to re-enable the port. */
-	deprecated_atomic_or(&port_oc_reset_req, BIT(port));
-	hook_call_deferred(&re_enable_ports_data, SECOND);
+	/*
+	 * Keep track of the overcurrent events and allow the module to perform
+	 * the spec-dictated recovery actions.
+	 */
+	usbc_ocp_add_event(port);
 }
 
-#endif /* CONFIG_USBC_PPC */
+#endif /* CONFIG_USBC_OCP */
 
 __maybe_unused void pd_handle_cc_overvoltage(int port)
 {
@@ -526,8 +523,7 @@ __overridable int pd_board_checks(void)
 	return EC_SUCCESS;
 }
 
-__overridable int pd_check_data_swap(int port,
-	enum pd_data_role data_role)
+__overridable int pd_check_data_swap(int port, enum pd_data_role data_role)
 {
 	/* Allow data swap if we are a UFP, otherwise don't allow. */
 	return (data_role == PD_ROLE_UFP) ? 1 : 0;
@@ -535,6 +531,16 @@ __overridable int pd_check_data_swap(int port,
 
 __overridable int pd_check_power_swap(int port)
 {
+#ifdef CONFIG_CHARGE_MANAGER
+	/*
+	 * If the Type-C port is our active charge port and we don't have a
+	 * battery, don't allow power role swap (to source).
+	 */
+	if (!IS_ENABLED(CONFIG_BATTERY) &&
+	    port == charge_manager_get_active_charge_port())
+		return 0;
+#endif
+
 	/*
 	 * Allow power swap if we are acting as a dual role device.  If we are
 	 * not acting as dual role (ex. suspended), then only allow power swap
@@ -548,8 +554,7 @@ __overridable int pd_check_power_swap(int port)
 	return 0;
 }
 
-__overridable void pd_execute_data_swap(int port,
-	enum pd_data_role data_role)
+__overridable void pd_execute_data_swap(int port, enum pd_data_role data_role)
 {
 }
 
@@ -559,6 +564,12 @@ __overridable enum pd_dual_role_states pd_get_drp_state_in_suspend(void)
 	return PD_DRP_TOGGLE_OFF;
 }
 
+__overridable enum pd_dual_role_states pd_get_drp_state_in_s0(void)
+{
+	/* Enable dual role when chipset on */
+	return PD_DRP_TOGGLE_ON;
+}
+
 __overridable void pd_try_execute_vconn_swap(int port, int flags)
 {
 	/*
@@ -580,101 +591,6 @@ __overridable void pd_transition_voltage(int idx)
 	/* Most devices are fixed 5V output. */
 }
 
-__overridable void typec_set_source_current_limit(int p, enum tcpc_rp_value rp)
-{
-	if (IS_ENABLED(CONFIG_USBC_PPC))
-		ppc_set_vbus_source_current_limit(p, rp);
-}
-
-/* ---------------- Power Data Objects (PDOs) ----------------- */
-#ifndef CONFIG_USB_PD_CUSTOM_PDO
-#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\
-			 PDO_FIXED_COMM_CAP)
-
-const uint32_t pd_src_pdo[] = {
-	PDO_FIXED(5000, 1500, PDO_FIXED_FLAGS),
-};
-const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
-const uint32_t pd_src_pdo_max[] = {
-	PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS),
-};
-const int pd_src_pdo_max_cnt = ARRAY_SIZE(pd_src_pdo_max);
-
-const uint32_t pd_snk_pdo[] = {
-	PDO_FIXED(5000, 500, PDO_FIXED_FLAGS),
-	PDO_BATT(4750, PD_MAX_VOLTAGE_MV, PD_OPERATING_POWER_MW),
-	PDO_VAR(4750, PD_MAX_VOLTAGE_MV, PD_MAX_CURRENT_MA),
-};
-const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
-#endif /* CONFIG_USB_PD_CUSTOM_PDO */
-
-/* ----------------- Vendor Defined Messages ------------------ */
-#if defined(CONFIG_USB_PE_SM) && !defined(CONFIG_USB_VPD) && \
-	!defined(CONFIG_USB_CTVPD)
-__overridable int pd_custom_vdm(int port, int cnt, uint32_t *payload,
-				uint32_t **rpayload)
-{
-	int cmd = PD_VDO_CMD(payload[0]);
-	uint16_t dev_id = 0;
-	int is_rw, is_latest;
-
-	/* make sure we have some payload */
-	if (cnt == 0)
-		return 0;
-
-	switch (cmd) {
-	case VDO_CMD_VERSION:
-		/* guarantee last byte of payload is null character */
-		*(payload + cnt - 1) = 0;
-		CPRINTF("version: %s\n", (char *)(payload+1));
-		break;
-	case VDO_CMD_READ_INFO:
-	case VDO_CMD_SEND_INFO:
-		/* copy hash */
-		if (cnt == 7) {
-			dev_id = VDO_INFO_HW_DEV_ID(payload[6]);
-			is_rw = VDO_INFO_IS_RW(payload[6]);
-
-			is_latest = pd_dev_store_rw_hash(
-				port, dev_id, payload + 1,
-				is_rw ? EC_IMAGE_RW : EC_IMAGE_RO);
-
-			/*
-			 * Send update host event unless our RW hash is
-			 * already known to be the latest update RW.
-			 */
-			if (!is_rw || !is_latest)
-				pd_send_host_event(PD_EVENT_UPDATE_DEVICE);
-
-			CPRINTF("DevId:%d.%d SW:%d RW:%d\n",
-				HW_DEV_ID_MAJ(dev_id),
-				HW_DEV_ID_MIN(dev_id),
-				VDO_INFO_SW_DBG_VER(payload[6]),
-				is_rw);
-		} else if (cnt == 6) {
-			/* really old devices don't have last byte */
-			pd_dev_store_rw_hash(port, dev_id, payload + 1,
-					     EC_IMAGE_UNKNOWN);
-		}
-		break;
-	case VDO_CMD_CURRENT:
-		CPRINTF("Current: %dmA\n", payload[1]);
-		break;
-	case VDO_CMD_FLIP:
-		if (IS_ENABLED(CONFIG_USBC_SS_MUX))
-			usb_mux_flip(port);
-		break;
-#ifdef CONFIG_USB_PD_LOGGING
-	case VDO_CMD_GET_LOG:
-		pd_log_recv_vdm(port, cnt, payload);
-		break;
-#endif /* CONFIG_USB_PD_LOGGING */
-	}
-
-	return 0;
-}
-#endif /* CONFIG_USB_PE_SM && !CONFIG_USB_VPD && !CONFIG_USB_CTVPD */
-
 __overridable bool vboot_allow_usb_pd(void)
 {
 	return false;
@@ -684,15 +600,15 @@ __overridable bool vboot_allow_usb_pd(void)
 static void pd_usb_billboard_deferred(void)
 {
 	if (IS_ENABLED(CONFIG_USB_PD_ALT_MODE) &&
-		!IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP) &&
-		!IS_ENABLED(CONFIG_USB_PD_SIMPLE_DFP) &&
-		IS_ENABLED(CONFIG_USB_BOS)) {
+	    !IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP) &&
+	    !IS_ENABLED(CONFIG_USB_PD_SIMPLE_DFP) &&
+	    IS_ENABLED(CONFIG_USB_BOS)) {
 		/*
 		 * TODO(tbroch)
 		 * 1. Will we have multiple type-C port UFPs
 		 * 2. Will there be other modes applicable to DFPs besides DP
 		 */
-		if (!pd_alt_mode(0, TCPC_TX_SOP, USB_SID_DISPLAYPORT))
+		if (!pd_alt_mode(0, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT))
 			usb_connect();
 	}
 }
@@ -719,32 +635,45 @@ static void gpio_discharge_vbus(int port, int enable)
 
 void pd_set_vbus_discharge(int port, int enable)
 {
-	static struct mutex discharge_lock[CONFIG_USB_PD_PORT_MAX_COUNT];
+	static mutex_t discharge_lock[CONFIG_USB_PD_PORT_MAX_COUNT];
+#ifdef CONFIG_ZEPHYR
+	static bool inited[CONFIG_USB_PD_PORT_MAX_COUNT];
+#endif
 
 	if (port >= board_get_usb_pd_port_count())
 		return;
 
+#ifdef CONFIG_ZEPHYR
+	if (!inited[port]) {
+		(void)k_mutex_init(&discharge_lock[port]);
+		inited[port] = true;
+	}
+#endif
 	mutex_lock(&discharge_lock[port]);
 	enable &= !board_vbus_source_enabled(port);
 
-	if (IS_ENABLED(CONFIG_USB_PD_DISCHARGE_GPIO))
+	if (get_usb_pd_discharge() == USB_PD_DISCHARGE_GPIO) {
 		gpio_discharge_vbus(port, enable);
-	else if (IS_ENABLED(CONFIG_USB_PD_DISCHARGE_TCPC))
+	} else if (get_usb_pd_discharge() == USB_PD_DISCHARGE_TCPC) {
+#ifdef CONFIG_USB_PD_DISCHARGE_TCPC
 		tcpc_discharge_vbus(port, enable);
-	else if (IS_ENABLED(CONFIG_USB_PD_DISCHARGE_PPC))
+#endif
+	} else if (get_usb_pd_discharge() == USB_PD_DISCHARGE_PPC) {
+#ifdef CONFIG_USB_PD_DISCHARGE_PPC
 		ppc_discharge_vbus(port, enable);
+#endif
+	}
 
 	mutex_unlock(&discharge_lock[port]);
 }
 #endif /* CONFIG_USB_PD_DISCHARGE */
 
 #ifdef CONFIG_USB_PD_TCPM_TCPCI
-static uint32_t pd_ports_to_resume;
+static atomic_t pd_ports_to_resume;
 static void resume_pd_port(void)
 {
 	uint32_t port;
-	uint32_t suspended_ports =
-		deprecated_atomic_read_clear(&pd_ports_to_resume);
+	uint32_t suspended_ports = atomic_clear(&pd_ports_to_resume);
 
 	while (suspended_ports) {
 		port = __builtin_ctz(suspended_ports);
@@ -756,11 +685,15 @@ DECLARE_DEFERRED(resume_pd_port);
 
 void pd_deferred_resume(int port)
 {
-	deprecated_atomic_or(&pd_ports_to_resume, 1 << port);
+	atomic_or(&pd_ports_to_resume, 1 << port);
 	hook_call_deferred(&resume_pd_port_data, 5 * SECOND);
 }
 #endif /* CONFIG_USB_PD_TCPM_TCPCI */
 
+__overridable int pd_snk_is_vbus_provided(int port)
+{
+	return EC_SUCCESS;
+}
 
 /*
  * Check the specified Vbus level
@@ -770,9 +703,10 @@ void pd_deferred_resume(int port)
  */
 __overridable bool pd_check_vbus_level(int port, enum vbus_level level)
 {
-	if (IS_ENABLED(CONFIG_USB_PD_VBUS_DETECT_TCPC))
+	if (IS_ENABLED(CONFIG_USB_PD_VBUS_DETECT_TCPC) &&
+	    (get_usb_pd_vbus_detect() == USB_PD_VBUS_DETECT_TCPC)) {
 		return tcpm_check_vbus_level(port, level);
-	else if (level == VBUS_PRESENT)
+	} else if (level == VBUS_PRESENT)
 		return pd_snk_is_vbus_provided(port);
 	else
 		return !pd_snk_is_vbus_provided(port);
@@ -795,7 +729,8 @@ int pd_set_frs_enable(int port, int enable)
 
 	if (IS_ENABLED(CONFIG_USB_PD_FRS_PPC))
 		rv = ppc_set_frs_enable(port, enable);
-	if (rv == EC_SUCCESS && IS_ENABLED(CONFIG_USB_PD_FRS_TCPC))
+	if ((rv == EC_SUCCESS || rv == EC_ERROR_UNIMPLEMENTED) &&
+	    tcpm_tcpc_has_frs_control(port))
 		rv = tcpm_set_frs_enable(port, enable);
 	if (rv == EC_SUCCESS)
 		rv = board_pd_set_frs_enable(port, enable);
@@ -808,7 +743,7 @@ int pd_set_frs_enable(int port, int enable)
  * Dump TCPC registers.
  */
 void tcpc_dump_registers(int port, const struct tcpc_reg_dump_map *reg,
-			  int count)
+			 int count)
 {
 	int i, val;
 
@@ -816,21 +751,20 @@ void tcpc_dump_registers(int port, const struct tcpc_reg_dump_map *reg,
 		switch (reg->size) {
 		case 1:
 			tcpc_read(port, reg->addr, &val);
-			ccprintf("  %-30s(0x%02x) =   0x%02x\n",
-				reg->name, reg->addr, (uint8_t)val);
+			ccprintf("  %-30s(0x%02x) =   0x%02x\n", reg->name,
+				 reg->addr, (uint8_t)val);
 			break;
 		case 2:
 			tcpc_read16(port, reg->addr, &val);
-			ccprintf("  %-30s(0x%02x) = 0x%04x\n",
-				reg->name, reg->addr, (uint16_t)val);
+			ccprintf("  %-30s(0x%02x) = 0x%04x\n", reg->name,
+				 reg->addr, (uint16_t)val);
 			break;
 		}
 		cflush();
 	}
-
 }
 
-static int command_tcpc_dump(int argc, char **argv)
+static int command_tcpc_dump(int argc, const char **argv)
 {
 	int port;
 
@@ -851,22 +785,136 @@ DECLARE_CONSOLE_COMMAND(tcpci_dump, command_tcpc_dump, "<Type-C port>",
 			"dump the TCPC regs");
 #endif /* defined(CONFIG_CMD_TCPC_DUMP) */
 
-int pd_build_alert_msg(uint32_t *msg, uint32_t *len, enum pd_power_role pr)
+void pd_srccaps_dump(int port)
 {
-	if (msg == NULL || len == NULL)
-		return EC_ERROR_INVAL;
+	int i;
+	const uint32_t *const srccaps = pd_get_src_caps(port);
+
+	for (i = 0; i < pd_get_src_cap_cnt(port); ++i) {
+		uint32_t max_ma, max_mv, min_mv;
+
+#ifdef CONFIG_CMD_PD_SRCCAPS_REDUCED_SIZE
+		pd_extract_pdo_power(srccaps[i], &max_ma, &max_mv, &min_mv);
+
+		if ((srccaps[i] & PDO_TYPE_MASK) == PDO_TYPE_AUGMENTED) {
+			if (IS_ENABLED(CONFIG_USB_PD_REV30))
+				ccprintf("%d: %dmV-%dmV/%dmA\n", i, min_mv,
+					 max_mv, max_ma);
+		} else {
+			ccprintf("%d: %dmV/%dmA\n", i, max_mv, max_ma);
+		}
+#else
+		const uint32_t pdo = srccaps[i];
+		const uint32_t pdo_mask = pdo & PDO_TYPE_MASK;
+		const char *pdo_type = "?";
+		bool range_flag = true;
+
+		pd_extract_pdo_power(pdo, &max_ma, &max_mv, &min_mv);
+
+		switch (pdo_mask) {
+		case PDO_TYPE_FIXED:
+			pdo_type = "Fixed";
+			range_flag = false;
+			break;
+		case PDO_TYPE_BATTERY:
+			pdo_type = "Battery";
+			break;
+		case PDO_TYPE_VARIABLE:
+			pdo_type = "Variable";
+			break;
+		case PDO_TYPE_AUGMENTED:
+			pdo_type = "Augmnt";
+			if (!IS_ENABLED(CONFIG_USB_PD_REV30)) {
+				pdo_type = "Aug3.0";
+				range_flag = false;
+			}
+			break;
+		}
+
+		ccprintf("Src %d: (%s) %dmV", i, pdo_type, max_mv);
+		if (range_flag)
+			ccprintf("-%dmV", min_mv);
+		ccprintf("/%dm%c", max_ma,
+			 pdo_mask == PDO_TYPE_BATTERY ? 'W' : 'A');
+
+		if (pdo & PDO_FIXED_DUAL_ROLE)
+			ccprintf(" DRP");
+		if (pdo & PDO_FIXED_UNCONSTRAINED)
+			ccprintf(" UP");
+		if (pdo & PDO_FIXED_COMM_CAP)
+			ccprintf(" USB");
+		if (pdo & PDO_FIXED_DATA_SWAP)
+			ccprintf(" DRD");
+		/* Note from ectool.c: FRS bits are reserved in PD 2.0 spec */
+		if (pdo & PDO_FIXED_FRS_CURR_MASK)
+			ccprintf(" FRS");
+		ccprintf("\n");
+#endif
+	}
+}
+
+int pd_broadcast_alert_msg(uint32_t ado)
+{
+#if defined(CONFIG_USB_PD_TCPMV2) && defined(CONFIG_USB_PE_SM) && \
+	!defined(CONFIG_USB_VPD) && !defined(CONFIG_USB_CTVPD)
+	int ret = EC_SUCCESS;
+
+	for (int i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		if (pd_send_alert_msg(i, ado) != EC_SUCCESS)
+			ret = EC_ERROR_BUSY;
+	}
+
+	return ret;
+#else
+	return EC_ERROR_INVALID_CONFIG;
+#endif
+}
+
+int pd_send_alert_msg(int port, uint32_t ado)
+{
+#if defined(CONFIG_USB_PD_TCPMV2) && defined(CONFIG_USB_PE_SM) && \
+	!defined(CONFIG_USB_VPD) && !defined(CONFIG_USB_CTVPD)
+	struct rmdo partner_rmdo;
 
 	/*
-	 * SOURCE: currently only supports OCP
-	 * SINK:   currently only supports OVP
+	 * The Alert Data Object (ADO) definition changed between USB PD
+	 * Revision 3.0 and 3.1. Clear reserved bits from the USB PD 3.0
+	 * ADO before sending to a USB PD 3.0 partner and block the
+	 * message if the ADO is empty.
 	 */
-	if (pr == PD_ROLE_SOURCE)
-		*msg = ADO_OCP_EVENT;
-	else
-		*msg = ADO_OVP_EVENT;
+	partner_rmdo = pd_get_partner_rmdo(port);
+	if (partner_rmdo.major_rev == 0) {
+		ado &= ~(ADO_EXTENDED_ALERT_EVENT |
+			 ADO_EXTENDED_ALERT_EVENT_TYPE);
+	}
+
+	if (!ado)
+		return EC_ERROR_INVAL;
 
-	/* Alert data is 4 bytes */
-	*len = 4;
+	if (pe_set_ado(port, ado) != EC_SUCCESS)
+		return EC_ERROR_BUSY;
 
+	pd_dpm_request(port, DPM_REQUEST_SEND_ALERT);
 	return EC_SUCCESS;
+#else
+	return EC_ERROR_INVALID_CONFIG;
+#endif
+}
+
+#ifdef CONFIG_MKBP_EVENT
+static int dp_alt_mode_entry_get_next_event(uint8_t *data)
+{
+	return EC_SUCCESS;
+}
+DECLARE_EVENT_SOURCE(EC_MKBP_EVENT_DP_ALT_MODE_ENTERED,
+		     dp_alt_mode_entry_get_next_event);
+#endif /* CONFIG_MKBP_EVENT */
+
+__overridable void pd_notify_dp_alt_mode_entry(int port)
+{
+	if (IS_ENABLED(CONFIG_MKBP_EVENT)) {
+		(void)port;
+		CPRINTS("Notifying AP of DP Alt Mode Entry...");
+		mkbp_send_event(EC_MKBP_EVENT_DP_ALT_MODE_ENTERED);
+	}
 }
diff --git a/common/usb_console_stream.c b/common/usb_console_stream.c
index 13dd7f8264..629e7ba1f8 100644
--- a/common/usb_console_stream.c
+++ b/common/usb_console_stream.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,13 +25,12 @@
 /* Console output macro */
 #define USB_CONSOLE_TIMEOUT_US (30 * MSEC)
 
-#define QUEUE_SIZE_USB_TX     CONFIG_USB_CONSOLE_TX_BUF_SIZE
-#define QUEUE_SIZE_USB_RX     USB_MAX_PACKET_SIZE
+#define QUEUE_SIZE_USB_TX CONFIG_USB_CONSOLE_TX_BUF_SIZE
+#define QUEUE_SIZE_USB_RX USB_MAX_PACKET_SIZE
 
 static void usb_console_wr(struct queue_policy const *policy, size_t count);
 static void uart_console_rd(struct queue_policy const *policy, size_t count);
 
-
 static int last_tx_ok = 1;
 
 /*
@@ -52,24 +51,19 @@ static int is_readonly = 1;
  * usb-stream.c.
  */
 static struct queue_policy const usb_console_policy = {
-	.add    = usb_console_wr,
+	.add = usb_console_wr,
 	.remove = uart_console_rd,
 };
 
 static struct queue const tx_q = QUEUE_NULL(QUEUE_SIZE_USB_TX, uint8_t);
-static struct queue const rx_q = QUEUE(QUEUE_SIZE_USB_RX, uint8_t,
-				       usb_console_policy);
+static struct queue const rx_q =
+	QUEUE(QUEUE_SIZE_USB_RX, uint8_t, usb_console_policy);
 
 struct usb_stream_config const usb_console;
 
-USB_STREAM_CONFIG(usb_console,
-		  USB_IFACE_CONSOLE,
-		  USB_STR_CONSOLE_NAME,
-		  USB_EP_CONSOLE,
-		  USB_MAX_PACKET_SIZE,
-		  USB_MAX_PACKET_SIZE,
-		  rx_q,
-		  tx_q)
+USB_STREAM_CONFIG(usb_console, USB_IFACE_CONSOLE, USB_STR_CONSOLE_NAME,
+		  USB_EP_CONSOLE, USB_MAX_PACKET_SIZE, USB_MAX_PACKET_SIZE,
+		  rx_q, tx_q)
 
 static void usb_console_wr(struct queue_policy const *policy, size_t count)
 {
@@ -185,7 +179,7 @@ int usb_puts(const char *outstr)
 	if (!is_enabled)
 		return EC_SUCCESS;
 
-	ret  = usb_wait_console();
+	ret = usb_wait_console();
 	if (ret)
 		return ret;
 
diff --git a/common/usb_host_command.c b/common/usb_host_command.c
new file mode 100644
index 0000000000..0aeff40d39
--- /dev/null
+++ b/common/usb_host_command.c
@@ -0,0 +1,264 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "console.h"
+#include "consumer.h"
+#include "ec_commands.h"
+#include "host_command.h"
+#include "printf.h"
+#include "queue_policies.h"
+#include "system.h"
+#include "usb-stream.h"
+#include "usb_api.h"
+#include "usb_hw.h"
+#include "util.h"
+
+#define CPUTS(outstr) cputs(CC_USB, outstr)
+#define CPRINTS(format, args...) cprints(CC_HOSTCMD, "USBHC: " format, ##args)
+
+enum usbhc_state {
+	/* Initial State - Ready to receive next request */
+	USBHC_STATE_READY_TO_RX = 0,
+	/* Receiving request */
+	USBHC_STATE_RECEIVING,
+	/* Processing request */
+	USBHC_STATE_PROCESSING,
+	/* Sending response */
+	USBHC_STATE_SENDING,
+	/* Received bad data */
+	USBHC_STATE_RX_BAD,
+} state;
+
+struct consumer const hostcmd_consumer;
+struct producer const hostcmd_producer;
+struct usb_stream_config const usbhc_stream;
+
+/* RX (Host->EC) queue */
+static struct queue const usb_to_hostcmd =
+	QUEUE_DIRECT(64, uint8_t, usbhc_stream.producer, hostcmd_consumer);
+/* TX (EC->Host) queue */
+static struct queue const hostcmd_to_usb =
+	QUEUE_DIRECT(64, uint8_t, hostcmd_producer, usbhc_stream.consumer);
+
+USB_STREAM_CONFIG_FULL(usbhc_stream, USB_IFACE_HOSTCMD, USB_CLASS_VENDOR_SPEC,
+		       USB_SUBCLASS_GOOGLE_HOSTCMD, USB_PROTOCOL_GOOGLE_HOSTCMD,
+		       USB_STR_HOSTCMD_NAME, USB_EP_HOSTCMD,
+		       USB_MAX_PACKET_SIZE, USB_MAX_PACKET_SIZE, usb_to_hostcmd,
+		       hostcmd_to_usb)
+
+static uint8_t in_msg[USBHC_MAX_REQUEST_SIZE];
+static uint8_t out_msg[USBHC_MAX_RESPONSE_SIZE];
+static uint32_t out_size;
+static struct host_packet usbhc_packet;
+static struct ec_host_request *header = (struct ec_host_request *)in_msg;
+
+static void usbhc_read(struct producer const *producer, size_t count)
+{
+	static uint32_t out_index;
+	size_t len;
+
+	len = MIN(producer->queue->buffer_units, out_size - out_index);
+	len = MIN(count, len);
+
+	/* If we're not sending, what's going on? */
+	if (state != USBHC_STATE_SENDING)
+		return;
+
+	/* Put a piece of a response in the Tx queue. */
+	QUEUE_ADD_UNITS(producer->queue, out_msg + out_index, len);
+	out_index += len;
+
+	if (out_index < out_size)
+		/* More data to send. */
+		return;
+
+	if (IS_ENABLED(DEBUG))
+		CPRINTS("Tx complete (%u bytes)", out_index);
+	out_index = 0;
+	state = USBHC_STATE_READY_TO_RX;
+}
+
+struct producer const hostcmd_producer = {
+	.queue = &hostcmd_to_usb,
+	.ops = &((struct producer_ops const){
+		.read = usbhc_read,
+	}),
+};
+
+/*
+ * Called when a command handler finished execution and prepared a response.
+ * It's supposed returns a response back to the host.
+ */
+static void usbhc_send_response_packet(struct host_packet *pkt)
+{
+	/*
+	 * If we're not processing, then the AP has already terminated the
+	 * transaction and won't be listening to a response.
+	 */
+	if (state != USBHC_STATE_PROCESSING)
+		return;
+
+	if (sizeof(out_msg) < pkt->response_size) {
+		CPRINTS("Reponse size (%u) exceeds Tx buffer",
+			pkt->response_size);
+		return;
+	}
+
+	memcpy(out_msg, pkt->response, pkt->response_size);
+	out_size = pkt->response_size;
+	state = USBHC_STATE_SENDING;
+
+	usbhc_read(&hostcmd_producer, hostcmd_to_usb.buffer_units);
+}
+
+/*
+ * Pass a complete packet to the host command protocol subsystem.
+ */
+static void usbhc_process_packet(uint32_t pkt_size)
+{
+	usbhc_packet.send_response = usbhc_send_response_packet;
+	usbhc_packet.request = in_msg;
+	usbhc_packet.request_temp = NULL;
+	usbhc_packet.request_max = sizeof(in_msg);
+	usbhc_packet.request_size = pkt_size;
+
+	usbhc_packet.response = out_msg;
+	usbhc_packet.response_max = sizeof(out_msg);
+	usbhc_packet.response_size = 0;
+	usbhc_packet.driver_result = EC_RES_SUCCESS;
+
+	host_packet_receive(&usbhc_packet);
+}
+
+/*
+ * Called when usb-stream copies incoming data to the USBHC's Rx queue.
+ */
+static void usbhc_written(struct consumer const *consumer, size_t count)
+{
+	static uint32_t block_index;
+	static uint32_t expected_size;
+	static uint64_t prev_activity_timestamp;
+	uint64_t delta_time;
+
+	/* How much time since the previous USB callback? */
+	delta_time = get_time().val - prev_activity_timestamp;
+	prev_activity_timestamp += delta_time;
+
+	/* If a session lasts more than 5 seconds, let's start over. */
+	if ((delta_time > 5 * SECOND) && state != USBHC_STATE_READY_TO_RX) {
+		state = USBHC_STATE_READY_TO_RX;
+		CPRINTS("Recovering after timeout");
+	}
+
+	switch (state) {
+	case USBHC_STATE_READY_TO_RX:
+		if (IS_ENABLED(DEBUG))
+			CPRINTS("Rx start. (count=%d)", count);
+		block_index = 0;
+		/* Only version 3 is supported. Using in_msg as a courtesy. */
+		QUEUE_REMOVE_UNITS(consumer->queue, in_msg, count);
+		if (IS_ENABLED(DEBUG)) {
+			char str_buf[hex_str_buf_size(count)];
+
+			snprintf_hex_buffer(str_buf, sizeof(str_buf),
+					    HEX_BUF(in_msg, count));
+			CPRINTS("%s", str_buf);
+		}
+		if (in_msg[0] != EC_HOST_REQUEST_VERSION) {
+			CPRINTS("Unsupported version: %u", in_msg[0]);
+			return;
+		}
+		block_index += count;
+		expected_size = host_request_expected_size(header);
+		if (block_index < expected_size) {
+			state = USBHC_STATE_RECEIVING;
+		} else if (sizeof(in_msg) < expected_size) {
+			CPRINTS("Expected data size (%d) is too large",
+				expected_size);
+			state = USBHC_STATE_RX_BAD;
+		} else {
+			if (IS_ENABLED(DEBUG))
+				CPRINTS("Rx complete (%d bytes)", block_index);
+			state = USBHC_STATE_PROCESSING;
+			usbhc_process_packet(block_index);
+		}
+		return;
+	case USBHC_STATE_RECEIVING:
+		/* Continue to receive the remaining data. */
+		break;
+	case USBHC_STATE_RX_BAD:
+		/*
+		 * Once we're in RX_BAD, we'll discard the incoming data for 5
+		 * seconds. We don't want to be READY too soon because most
+		 * likely more anomalous data will come, hopefully the host will
+		 * fix the situation.
+		 */
+		queue_advance_head(consumer->queue, count);
+		return;
+	case USBHC_STATE_PROCESSING:
+	case USBHC_STATE_SENDING:
+		/*
+		 * Take no action and return though we may have resource to
+		 * receive a new request. Host will get a buffer full error or
+		 * timeout.
+		 */
+		return;
+	}
+
+	/* Receive the remaining packet. */
+
+	if (IS_ENABLED(DEBUG))
+		CPRINTS("Received %d bytes", count);
+
+	if (sizeof(in_msg) < block_index + count) {
+		CPRINTS("Rx buffer overflow");
+		state = USBHC_STATE_RX_BAD;
+		return;
+	}
+	QUEUE_REMOVE_UNITS(consumer->queue, in_msg + block_index, count);
+	block_index += count;
+
+	if (block_index < expected_size)
+		return; /* More to come. */
+
+	if (IS_ENABLED(DEBUG))
+		CPRINTS("Rx complete (%d bytes)", block_index);
+
+	if (expected_size < block_index) {
+		CPRINTS("Packet is larger than expected (%d)", expected_size);
+		state = USBHC_STATE_RX_BAD;
+		return;
+	}
+
+	/* Ok, the entire packet has been received and assembled. */
+	state = USBHC_STATE_PROCESSING;
+	usbhc_process_packet(block_index);
+}
+
+struct consumer const hostcmd_consumer = {
+	.queue = &usb_to_hostcmd,
+	.ops = &((struct consumer_ops const){
+		.written = usbhc_written,
+	}),
+};
+
+static enum ec_status
+host_command_protocol_info(struct host_cmd_handler_args *args)
+{
+	struct ec_response_get_protocol_info *r = args->response;
+
+	memset(r, 0, sizeof(*r));
+	r->protocol_versions |= BIT(3);
+	r->max_request_packet_size = USBHC_MAX_REQUEST_SIZE;
+	r->max_response_packet_size = USBHC_MAX_RESPONSE_SIZE;
+	r->flags = EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED;
+
+	args->response_size = sizeof(*r);
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, host_command_protocol_info,
+		     EC_VER_MASK(0));
diff --git a/common/usb_i2c.c b/common/usb_i2c.c
index ace2e7139c..b1cd45c76a 100644
--- a/common/usb_i2c.c
+++ b/common/usb_i2c.c
@@ -1,46 +1,41 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include "common.h"
-#include "link_defs.h"
-#include "registers.h"
-#include "i2c.h"
-#include "usb_descriptor.h"
-#include "util.h"
-
 #include "common.h"
 #include "console.h"
 #include "consumer.h"
+#include "i2c.h"
+#include "link_defs.h"
 #include "producer.h"
 #include "queue.h"
 #include "queue_policies.h"
+#include "registers.h"
 #include "task.h"
 #include "usb-stream.h"
+#include "usb_descriptor.h"
 #include "usb_i2c.h"
+#include "util.h"
 
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
 
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-
-
-USB_I2C_CONFIG(i2c,
-	       USB_IFACE_I2C,
-	       USB_STR_I2C_NAME,
-	       USB_EP_I2C)
+USB_I2C_CONFIG(i2c, USB_IFACE_I2C, USB_STR_I2C_NAME, USB_EP_I2C)
 
-static int (*cros_cmd_handler)(void *data_in,
-			       size_t in_size,
-			       void *data_out,
+static int (*cros_cmd_handler)(void *data_in, size_t in_size, void *data_out,
 			       size_t out_size);
 
 static int16_t usb_i2c_map_error(int error)
 {
 	switch (error) {
-	case EC_SUCCESS:       return USB_I2C_SUCCESS;
-	case EC_ERROR_TIMEOUT: return USB_I2C_TIMEOUT;
-	case EC_ERROR_BUSY:    return USB_I2C_BUSY;
-	default:               return USB_I2C_UNKNOWN_ERROR | (error & 0x7fff);
+	case EC_SUCCESS:
+		return USB_I2C_SUCCESS;
+	case EC_ERROR_TIMEOUT:
+		return USB_I2C_TIMEOUT;
+	case EC_ERROR_BUSY:
+		return USB_I2C_BUSY;
+	default:
+		return USB_I2C_UNKNOWN_ERROR | (error & 0x7fff);
 	}
 }
 
@@ -52,7 +47,7 @@ static int16_t usb_i2c_map_error(int error)
 static uint32_t usb_i2c_read_packet(struct usb_i2c_config const *config)
 {
 	return QUEUE_REMOVE_UNITS(config->consumer.queue, config->buffer,
-		queue_count(config->consumer.queue));
+				  queue_count(config->consumer.queue));
 }
 
 static void usb_i2c_write_packet(struct usb_i2c_config const *config,
@@ -72,9 +67,8 @@ static uint8_t usb_i2c_executable(struct usb_i2c_config const *config)
 		 * In order to support larger write payload, we need to peek
 		 * the queue to see if we need to wait for more data.
 		 */
-		if (queue_peek_units(config->consumer.queue,
-				     peek, 0, sizeof(peek))
-		    != sizeof(peek)) {
+		if (queue_peek_units(config->consumer.queue, peek, 0,
+				     sizeof(peek)) != sizeof(peek)) {
 			/* Not enough data to calculate expected_size. */
 			return 0;
 		}
@@ -92,7 +86,6 @@ static uint8_t usb_i2c_executable(struct usb_i2c_config const *config)
 		expected_size += (((size_t)peek[0] & 0xf0) << 4) | peek[2];
 	}
 
-
 	if (queue_count(config->consumer.queue) >= expected_size) {
 		expected_size = 0;
 		return 1;
@@ -104,20 +97,20 @@ static uint8_t usb_i2c_executable(struct usb_i2c_config const *config)
 static void usb_i2c_execute(struct usb_i2c_config const *config)
 {
 	/* Payload is ready to execute. */
-	uint32_t count      = usb_i2c_read_packet(config);
-	int portindex       = (config->buffer[0] >> 0) & 0xf;
+	uint32_t count = usb_i2c_read_packet(config);
+	int portindex = (config->buffer[0] >> 0) & 0xf;
 	uint16_t addr_flags = (config->buffer[0] >> 8) & 0x7f;
-	int write_count     = ((config->buffer[0] << 4) & 0xf00) |
-		((config->buffer[1] >> 0) & 0xff);
-	int read_count      = (config->buffer[1] >> 8) & 0xff;
-	int offset          = 0;    /* Offset for extended reading header. */
+	int write_count = ((config->buffer[0] << 4) & 0xf00) |
+			  ((config->buffer[1] >> 0) & 0xff);
+	int read_count = (config->buffer[1] >> 8) & 0xff;
+	int offset = 0; /* Offset for extended reading header. */
 
 	config->buffer[0] = 0;
 	config->buffer[1] = 0;
 
 	if (read_count & 0x80) {
 		read_count = ((config->buffer[2] & 0xff) << 7) |
-			(read_count & 0x7f);
+			     (read_count & 0x7f);
 		offset = 2;
 	}
 
@@ -127,7 +120,7 @@ static void usb_i2c_execute(struct usb_i2c_config const *config)
 	if (!usb_i2c_board_is_enabled()) {
 		config->buffer[0] = USB_I2C_DISABLED;
 	} else if (write_count > CONFIG_USB_I2C_MAX_WRITE_COUNT ||
-		write_count != (count - 4 - offset)) {
+		   write_count != (count - 4 - offset)) {
 		config->buffer[0] = USB_I2C_WRITE_COUNT_INVALID;
 	} else if (read_count > CONFIG_USB_I2C_MAX_READ_COUNT) {
 		config->buffer[0] = USB_I2C_READ_COUNT_INVALID;
@@ -156,8 +149,7 @@ static void usb_i2c_execute(struct usb_i2c_config const *config)
 		 */
 		ret = i2c_xfer(i2c_ports[portindex].port, addr_flags,
 			       (uint8_t *)(config->buffer + 2) + offset,
-			       write_count,
-			       (uint8_t *)(config->buffer + 2),
+			       write_count, (uint8_t *)(config->buffer + 2),
 			       read_count);
 		config->buffer[0] = usb_i2c_map_error(ret);
 	}
@@ -183,11 +175,8 @@ struct consumer_ops const usb_i2c_consumer_ops = {
 	.written = usb_i2c_written,
 };
 
-int usb_i2c_register_cros_cmd_handler(int (*cmd_handler)
-				      (void *data_in,
-				       size_t in_size,
-				       void *data_out,
-				       size_t out_size))
+int usb_i2c_register_cros_cmd_handler(int (*cmd_handler)(
+	void *data_in, size_t in_size, void *data_out, size_t out_size))
 {
 	if (cros_cmd_handler)
 		return -1;
diff --git a/common/usb_pd_alt_mode_dfp.c b/common/usb_pd_alt_mode_dfp.c
deleted file mode 100644
index 75d7744597..0000000000
--- a/common/usb_pd_alt_mode_dfp.c
+++ /dev/null
@@ -1,1287 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Alternate Mode Downstream Facing Port (DFP) USB-PD module.
- */
-
-#include "chipset.h"
-#include "console.h"
-#include "task.h"
-#include "task_id.h"
-#include "timer.h"
-#include "usb_common.h"
-#include "usb_charge.h"
-#include "usb_dp_alt_mode.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "usb_tbt_alt_mode.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#else
-#define CPRINTS(format, args...)
-#define CPRINTF(format, args...)
-#endif
-
-#ifndef PORT_TO_HPD
-#define PORT_TO_HPD(port) ((port) ? GPIO_USB_C1_DP_HPD : GPIO_USB_C0_DP_HPD)
-#endif /* PORT_TO_HPD */
-
-/* Tracker for which task is waiting on sysjump prep to finish */
-static volatile task_id_t sysjump_task_waiting = TASK_ID_INVALID;
-
-/*
- * timestamp of the next possible toggle to ensure the 2-ms spacing
- * between IRQ_HPD.  Since this is used in overridable functions, this
- * has to be global.
- */
-uint64_t svdm_hpd_deadline[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-int dp_flags[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-uint32_t dp_status[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-__overridable const struct svdm_response svdm_rsp = {
-	.identity = NULL,
-	.svids = NULL,
-	.modes = NULL,
-};
-
-static int pd_get_mode_idx(int port, enum tcpm_transmit_type type,
-		uint16_t svid)
-{
-	int amode_idx;
-	struct partner_active_modes *active =
-		pd_get_partner_active_modes(port, type);
-
-	for (amode_idx = 0; amode_idx < PD_AMODE_COUNT; amode_idx++) {
-		if (active->amodes[amode_idx].fx &&
-		    (active->amodes[amode_idx].fx->svid == svid))
-			return amode_idx;
-	}
-	return -1;
-}
-
-static int pd_allocate_mode(int port, enum tcpm_transmit_type type,
-		uint16_t svid)
-{
-	int i, j;
-	struct svdm_amode_data *modep;
-	int mode_idx = pd_get_mode_idx(port, type, svid);
-	struct pd_discovery *disc = pd_get_am_discovery(port, type);
-	struct partner_active_modes *active =
-		pd_get_partner_active_modes(port, type);
-	assert(active);
-
-	if (mode_idx != -1)
-		return mode_idx;
-
-	/* There's no space to enter another mode */
-	if (active->amode_idx == PD_AMODE_COUNT) {
-		CPRINTF("ERR:NO AMODE SPACE\n");
-		return -1;
-	}
-
-	/* Allocate ...  if SVID == 0 enter default supported policy */
-	for (i = 0; i < supported_modes_cnt; i++) {
-		for (j = 0; j < disc->svid_cnt; j++) {
-			struct svid_mode_data *svidp = &disc->svids[j];
-
-			/*
-			 * Looking for a match between supported_modes and
-			 * discovered SVIDs; must also match the passed-in SVID
-			 * if that was non-zero. Otherwise, go to the next
-			 * discovered SVID.
-			 * TODO(b/155890173): Support AP-directed mode entry
-			 * where the mode is unknown to the TCPM.
-			 */
-			if ((svidp->svid != supported_modes[i].svid) ||
-			    (svid && (svidp->svid != svid)))
-				continue;
-
-			modep = &active->amodes[active->amode_idx];
-			modep->fx = &supported_modes[i];
-			modep->data = &disc->svids[j];
-			active->amode_idx++;
-			return active->amode_idx - 1;
-		}
-	}
-	return -1;
-}
-
-static int validate_mode_request(struct svdm_amode_data *modep,
-				 uint16_t svid, int opos)
-{
-	if (!modep->fx)
-		return 0;
-
-	if (svid != modep->fx->svid) {
-		CPRINTF("ERR:svid r:0x%04x != c:0x%04x\n",
-			svid, modep->fx->svid);
-		return 0;
-	}
-
-	if (opos != modep->opos) {
-		CPRINTF("ERR:opos r:%d != c:%d\n",
-			opos, modep->opos);
-		return 0;
-	}
-
-	return 1;
-}
-
-void pd_prepare_sysjump(void)
-{
-	int i;
-
-	/* Exit modes before sysjump so we can cleanly enter again later */
-	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
-		/*
-		 * If the port is not capable of Alternate mode no need to
-		 * send the event.
-		 */
-		if (!pd_alt_mode_capable(i))
-			continue;
-
-		sysjump_task_waiting = task_get_current();
-		task_set_event(PD_PORT_TO_TASK_ID(i), PD_EVENT_SYSJUMP, 0);
-		task_wait_event_mask(TASK_EVENT_SYSJUMP_READY, -1);
-		sysjump_task_waiting = TASK_ID_INVALID;
-	}
-}
-
-/*
- * This algorithm defaults to choosing higher pin config over lower ones in
- * order to prefer multi-function if desired.
- *
- *  NAME | SIGNALING | OUTPUT TYPE | MULTI-FUNCTION | PIN CONFIG
- * -------------------------------------------------------------
- *  A    |  USB G2   |  ?          | no             | 00_0001
- *  B    |  USB G2   |  ?          | yes            | 00_0010
- *  C    |  DP       |  CONVERTED  | no             | 00_0100
- *  D    |  PD       |  CONVERTED  | yes            | 00_1000
- *  E    |  DP       |  DP         | no             | 01_0000
- *  F    |  PD       |  DP         | yes            | 10_0000
- *
- * if UFP has NOT asserted multi-function preferred code masks away B/D/F
- * leaving only A/C/E.  For single-output dongles that should leave only one
- * possible pin config depending on whether its a converter DP->(VGA|HDMI) or DP
- * output.  If UFP is a USB-C receptacle it may assert C/D/E/F.  The DFP USB-C
- * receptacle must always choose C/D in those cases.
- */
-int pd_dfp_dp_get_pin_mode(int port, uint32_t status)
-{
-	struct svdm_amode_data *modep =
-		pd_get_amode_data(port, TCPC_TX_SOP, USB_SID_DISPLAYPORT);
-	uint32_t mode_caps;
-	uint32_t pin_caps;
-
-	if (!modep)
-		return 0;
-
-	mode_caps = modep->data->mode_vdo[modep->opos - 1];
-
-	/* TODO(crosbug.com/p/39656) revisit with DFP that can be a sink */
-	pin_caps = PD_DP_PIN_CAPS(mode_caps);
-
-	/* if don't want multi-function then ignore those pin configs */
-	if (!PD_VDO_DPSTS_MF_PREF(status))
-		pin_caps &= ~MODE_DP_PIN_MF_MASK;
-
-	/* TODO(crosbug.com/p/39656) revisit if DFP drives USB Gen 2 signals */
-	pin_caps &= ~MODE_DP_PIN_BR2_MASK;
-
-	/* if C/D present they have precedence over E/F for USB-C->USB-C */
-	if (pin_caps & (MODE_DP_PIN_C | MODE_DP_PIN_D))
-		pin_caps &= ~(MODE_DP_PIN_E | MODE_DP_PIN_F);
-
-	/* get_next_bit returns undefined for zero */
-	if (!pin_caps)
-		return 0;
-
-	return 1 << get_next_bit(&pin_caps);
-}
-
-struct svdm_amode_data *pd_get_amode_data(int port,
-		enum tcpm_transmit_type type, uint16_t svid)
-{
-	int idx = pd_get_mode_idx(port, type, svid);
-	struct partner_active_modes *active =
-		pd_get_partner_active_modes(port, type);
-	assert(active);
-
-	return (idx == -1) ? NULL : &active->amodes[idx];
-}
-
-/*
- * Enter default mode ( payload[0] == 0 ) or attempt to enter mode via svid &
- * opos
- */
-uint32_t pd_dfp_enter_mode(int port, enum tcpm_transmit_type type,
-		uint16_t svid, int opos)
-{
-	int mode_idx = pd_allocate_mode(port, type, svid);
-	struct svdm_amode_data *modep;
-	uint32_t mode_caps;
-
-	if (mode_idx == -1)
-		return 0;
-	modep = &pd_get_partner_active_modes(port, type)->amodes[mode_idx];
-
-	if (!opos) {
-		/* choose the lowest as default */
-		modep->opos = 1;
-	} else if (opos <= modep->data->mode_cnt) {
-		modep->opos = opos;
-	} else {
-		CPRINTS("C%d: Invalid opos %d for SVID %x", port, opos, svid);
-		return 0;
-	}
-
-	mode_caps = modep->data->mode_vdo[modep->opos - 1];
-	if (modep->fx->enter(port, mode_caps) == -1)
-		return 0;
-
-	/*
-	 * Strictly speaking, this should only happen when the request
-	 * has been ACKed.
-	 * TODO(b/159854667): Redo setting the enter mode flag to incorporate
-	 * it into the DP state machine.
-	 */
-	pd_set_dfp_enter_mode_flag(port, true);
-
-	/* SVDM to send to UFP for mode entry */
-	return VDO(modep->fx->svid, 1, CMD_ENTER_MODE | VDO_OPOS(modep->opos));
-}
-
-int pd_dfp_exit_mode(int port, enum tcpm_transmit_type type, uint16_t svid,
-		int opos)
-{
-	struct svdm_amode_data *modep;
-	struct partner_active_modes *active =
-		pd_get_partner_active_modes(port, type);
-	int idx;
-
-	/*
-	 * Empty svid signals we should reset DFP VDM state by exiting all
-	 * entered modes then clearing state.  This occurs when we've
-	 * disconnected or for hard reset.
-	 */
-	if (!svid) {
-		for (idx = 0; idx < PD_AMODE_COUNT; idx++)
-			if (active->amodes[idx].fx)
-				active->amodes[idx].fx->exit(port);
-
-		pd_dfp_discovery_init(port);
-		return 0;
-	}
-
-	/*
-	 * TODO(crosbug.com/p/33946) : below needs revisited to allow multiple
-	 * mode exit.  Additionally it should honor OPOS == 7 as DFP's request
-	 * to exit all modes.  We currently don't have any UFPs that support
-	 * multiple modes on one SVID.
-	 */
-	modep = pd_get_amode_data(port, type, svid);
-	if (!modep || !validate_mode_request(modep, svid, opos))
-		return 0;
-
-	/* call DFPs exit function */
-	modep->fx->exit(port);
-
-	pd_set_dfp_enter_mode_flag(port, false);
-
-	/* exit the mode */
-	modep->opos = 0;
-	return 1;
-}
-
-void dfp_consume_attention(int port, uint32_t *payload)
-{
-	uint16_t svid = PD_VDO_VID(payload[0]);
-	int opos = PD_VDO_OPOS(payload[0]);
-	struct svdm_amode_data *modep =
-		pd_get_amode_data(port, TCPC_TX_SOP, svid);
-
-	if (!modep || !validate_mode_request(modep, svid, opos))
-		return;
-
-	if (modep->fx->attention)
-		modep->fx->attention(port, payload);
-}
-
-void dfp_consume_identity(int port, enum tcpm_transmit_type type, int cnt,
-		uint32_t *payload)
-{
-	int ptype;
-	struct pd_discovery *disc;
-	size_t identity_size;
-
-	if (type == TCPC_TX_SOP_PRIME &&
-	    !IS_ENABLED(CONFIG_USB_PD_DECODE_SOP)) {
-		CPRINTF("ERR:Unexpected cable response\n");
-		return;
-	}
-
-	ptype = PD_IDH_PTYPE(payload[VDO_I(IDH)]);
-	disc = pd_get_am_discovery(port, type);
-	identity_size = MIN(sizeof(union disc_ident_ack),
-				   (cnt - 1) * sizeof(uint32_t));
-
-	/* Note: only store VDOs, not the VDM header */
-	memcpy(disc->identity.raw_value, payload + 1, identity_size);
-	disc->identity_cnt = identity_size / sizeof(uint32_t);
-
-	switch (ptype) {
-	case IDH_PTYPE_AMA:
-		/* Leave vbus ON if the following macro is false */
-		if (IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE) &&
-			IS_ENABLED(CONFIG_USBC_VCONN_SWAP)) {
-			/* Adapter is requesting vconn, try to supply it */
-			if (PD_VDO_AMA_VCONN_REQ(payload[VDO_I(AMA)]))
-				pd_try_vconn_src(port);
-
-			/* Only disable vbus if vconn was requested */
-			if (PD_VDO_AMA_VCONN_REQ(payload[VDO_I(AMA)]) &&
-				!PD_VDO_AMA_VBUS_REQ(payload[VDO_I(AMA)]))
-				pd_power_supply_reset(port);
-		}
-		break;
-	default:
-		break;
-	}
-	pd_set_identity_discovery(port, type, PD_DISC_COMPLETE);
-}
-
-void dfp_consume_svids(int port, enum tcpm_transmit_type type, int cnt,
-		uint32_t *payload)
-{
-	int i;
-	uint32_t *ptr = payload + 1;
-	int vdo = 1;
-	uint16_t svid0, svid1;
-	struct pd_discovery *disc = pd_get_am_discovery(port, type);
-
-	for (i = disc->svid_cnt; i < disc->svid_cnt + 12; i += 2) {
-		if (i >= SVID_DISCOVERY_MAX) {
-			CPRINTF("ERR:SVIDCNT\n");
-			break;
-		}
-		/*
-		 * Verify we're still within the valid packet (count will be one
-		 * for the VDM header + xVDOs)
-		 */
-		if (vdo >= cnt)
-			break;
-
-		svid0 = PD_VDO_SVID_SVID0(*ptr);
-		if (!svid0)
-			break;
-		disc->svids[i].svid = svid0;
-		disc->svid_cnt++;
-
-		svid1 = PD_VDO_SVID_SVID1(*ptr);
-		if (!svid1)
-			break;
-		disc->svids[i + 1].svid = svid1;
-		disc->svid_cnt++;
-		ptr++;
-		vdo++;
-	}
-	/* TODO(tbroch) need to re-issue discover svids if > 12 */
-	if (i && ((i % 12) == 0))
-		CPRINTF("ERR:SVID+12\n");
-
-	pd_set_svids_discovery(port, type, PD_DISC_COMPLETE);
-}
-
-void dfp_consume_modes(int port, enum tcpm_transmit_type type, int cnt,
-		uint32_t *payload)
-{
-	int svid_idx;
-	struct svid_mode_data *mode_discovery = NULL;
-	struct pd_discovery *disc = pd_get_am_discovery(port, type);
-	uint16_t response_svid = (uint16_t) PD_VDO_VID(payload[0]);
-
-	for (svid_idx = 0; svid_idx < disc->svid_cnt; ++svid_idx) {
-		uint16_t svid = disc->svids[svid_idx].svid;
-
-		if (svid == response_svid) {
-			mode_discovery = &disc->svids[svid_idx];
-			break;
-		}
-	}
-	if (!mode_discovery) {
-		const struct svid_mode_data *requested_mode_data =
-			pd_get_next_mode(port, type);
-		CPRINTF("C%d: Mode response for undiscovered SVID %x, but TCPM "
-				"requested SVID %x\n",
-				port, response_svid, requested_mode_data->svid);
-		/*
-		 * Although SVIDs discovery seemed like it succeeded before, the
-		 * partner is now responding with undiscovered SVIDs. Discovery
-		 * cannot reasonably continue under these circumstances.
-		 */
-		pd_set_modes_discovery(port, type, requested_mode_data->svid,
-				PD_DISC_FAIL);
-		return;
-	}
-
-	mode_discovery->mode_cnt = cnt - 1;
-	if (mode_discovery->mode_cnt < 1) {
-		CPRINTF("ERR:NOMODE\n");
-		pd_set_modes_discovery(port, type, mode_discovery->svid,
-				PD_DISC_FAIL);
-		return;
-	}
-
-	memcpy(mode_discovery->mode_vdo, &payload[1],
-			sizeof(uint32_t) * mode_discovery->mode_cnt);
-	disc->svid_idx++;
-	pd_set_modes_discovery(port, type, mode_discovery->svid,
-			PD_DISC_COMPLETE);
-}
-
-int pd_alt_mode(int port, enum tcpm_transmit_type type, uint16_t svid)
-{
-	struct svdm_amode_data *modep = pd_get_amode_data(port, type, svid);
-
-	return (modep) ? modep->opos : -1;
-}
-
-void pd_set_identity_discovery(int port, enum tcpm_transmit_type type,
-			       enum pd_discovery_state disc)
-{
-	struct pd_discovery *pd = pd_get_am_discovery(port, type);
-
-	pd->identity_discovery = disc;
-}
-
-enum pd_discovery_state pd_get_identity_discovery(int port,
-						  enum tcpm_transmit_type type)
-{
-	struct pd_discovery *disc = pd_get_am_discovery(port, type);
-
-	return disc->identity_discovery;
-}
-
-const union disc_ident_ack *pd_get_identity_response(int port,
-					       enum tcpm_transmit_type type)
-{
-	if (type >= DISCOVERY_TYPE_COUNT)
-		return NULL;
-
-	return &pd_get_am_discovery(port, type)->identity;
-}
-
-uint16_t pd_get_identity_vid(int port)
-{
-	const union disc_ident_ack *resp = pd_get_identity_response(port,
-								TCPC_TX_SOP);
-
-	return resp->idh.usb_vendor_id;
-}
-
-uint16_t pd_get_identity_pid(int port)
-{
-	const union disc_ident_ack *resp = pd_get_identity_response(port,
-								TCPC_TX_SOP);
-
-	return resp->product.product_id;
-}
-
-uint8_t pd_get_product_type(int port)
-{
-	const union disc_ident_ack *resp = pd_get_identity_response(port,
-								TCPC_TX_SOP);
-
-	return resp->idh.product_type;
-}
-
-void pd_set_svids_discovery(int port, enum tcpm_transmit_type type,
-			       enum pd_discovery_state disc)
-{
-	struct pd_discovery *pd = pd_get_am_discovery(port, type);
-
-	pd->svids_discovery = disc;
-}
-
-enum pd_discovery_state pd_get_svids_discovery(int port,
-		enum tcpm_transmit_type type)
-{
-	struct pd_discovery *disc = pd_get_am_discovery(port, type);
-
-	return disc->svids_discovery;
-}
-
-int pd_get_svid_count(int port, enum tcpm_transmit_type type)
-{
-	struct pd_discovery *disc = pd_get_am_discovery(port, type);
-
-	return disc->svid_cnt;
-}
-
-uint16_t pd_get_svid(int port, uint16_t svid_idx, enum tcpm_transmit_type type)
-{
-	struct pd_discovery *disc = pd_get_am_discovery(port, type);
-
-	return disc->svids[svid_idx].svid;
-}
-
-void pd_set_modes_discovery(int port, enum tcpm_transmit_type type,
-		uint16_t svid, enum pd_discovery_state disc)
-{
-	struct pd_discovery *pd = pd_get_am_discovery(port, type);
-	int svid_idx;
-
-	for (svid_idx = 0; svid_idx < pd->svid_cnt; ++svid_idx) {
-		struct svid_mode_data *mode_data = &pd->svids[svid_idx];
-
-		if (mode_data->svid != svid)
-			continue;
-
-		mode_data->discovery = disc;
-		return;
-	}
-}
-
-enum pd_discovery_state pd_get_modes_discovery(int port,
-		enum tcpm_transmit_type type)
-{
-	const struct svid_mode_data *mode_data = pd_get_next_mode(port, type);
-
-	/*
-	 * If there are no SVIDs for which to discover modes, mode discovery is
-	 * trivially complete.
-	 */
-	if (!mode_data)
-		return PD_DISC_COMPLETE;
-
-	return mode_data->discovery;
-}
-
-int pd_get_mode_vdo_for_svid(int port, enum tcpm_transmit_type type,
-		uint16_t svid, uint32_t *vdo_out)
-{
-	int idx;
-	struct pd_discovery *disc;
-
-	if (type >= DISCOVERY_TYPE_COUNT)
-		return 0;
-
-	disc = pd_get_am_discovery(port, type);
-
-	for (idx = 0; idx < disc->svid_cnt; ++idx) {
-		if (pd_get_svid(port, idx, type) == svid) {
-			memcpy(vdo_out, disc->svids[idx].mode_vdo,
-			       sizeof(uint32_t) * disc->svids[idx].mode_cnt);
-			return disc->svids[idx].mode_cnt;
-		}
-	}
-	return 0;
-}
-
-struct svid_mode_data *pd_get_next_mode(int port,
-		enum tcpm_transmit_type type)
-{
-	struct pd_discovery *disc = pd_get_am_discovery(port, type);
-	struct svid_mode_data *failed_mode_data = NULL;
-	bool svid_good_discovery = false;
-	int svid_idx;
-
-	/* Walk through all of the discovery mode entries */
-	for (svid_idx = 0; svid_idx < disc->svid_cnt; ++svid_idx) {
-		struct svid_mode_data *mode_data = &disc->svids[svid_idx];
-
-		/* Discovery is needed, so send this one back now */
-		if (mode_data->discovery == PD_DISC_NEEDED)
-			return mode_data;
-
-		/* Discovery already succeeded, save that it was seen */
-		if (mode_data->discovery == PD_DISC_COMPLETE)
-			svid_good_discovery = true;
-		/* Discovery already failed, save first failure */
-		else if (!failed_mode_data)
-			failed_mode_data = mode_data;
-	}
-
-	/* If no good entries were located, then return last failed */
-	if (!svid_good_discovery)
-		return failed_mode_data;
-
-	/*
-	 * Mode discovery has been attempted for every discovered SVID (if
-	 * any exist)
-	 */
-	return NULL;
-}
-
-uint32_t *pd_get_mode_vdo(int port, uint16_t svid_idx,
-		enum tcpm_transmit_type type)
-{
-	struct pd_discovery *disc = pd_get_am_discovery(port, type);
-
-	return disc->svids[svid_idx].mode_vdo;
-}
-
-bool pd_is_mode_discovered_for_svid(int port, enum tcpm_transmit_type type,
-		uint16_t svid)
-{
-	const struct pd_discovery *disc = pd_get_am_discovery(port, type);
-	const struct svid_mode_data *mode_data;
-
-	for (mode_data = disc->svids; mode_data < disc->svids + disc->svid_cnt;
-			++mode_data) {
-		if (mode_data->svid == svid &&
-				mode_data->discovery == PD_DISC_COMPLETE)
-			return true;
-	}
-
-	return false;
-}
-
-void notify_sysjump_ready(void)
-{
-	/*
-	 * If event was set from pd_prepare_sysjump, wake the
-	 * task waiting on us to complete.
-	 */
-	if (sysjump_task_waiting != TASK_ID_INVALID)
-		task_set_event(sysjump_task_waiting,
-				TASK_EVENT_SYSJUMP_READY, 0);
-}
-
-static inline bool is_rev3_vdo(int port, enum tcpm_transmit_type type)
-{
-	return pd_get_vdo_ver(port, type) == PD_REV30;
-}
-
-/*
- * ############################################################################
- *
- * Cable communication functions
- *
- * ############################################################################
- */
-enum idh_ptype get_usb_pd_cable_type(int port)
-{
-	struct pd_discovery *disc =
-		pd_get_am_discovery(port, TCPC_TX_SOP_PRIME);
-
-	return disc->identity.idh.product_type;
-}
-
-bool is_usb2_cable_support(int port)
-{
-	struct pd_discovery *disc =
-		pd_get_am_discovery(port, TCPC_TX_SOP_PRIME);
-
-	return disc->identity.idh.product_type == IDH_PTYPE_PCABLE ||
-	       disc->identity.product_t2.a2_rev30.usb_20_support ==
-							USB2_SUPPORTED;
-}
-
-bool is_cable_speed_gen2_capable(int port)
-{
-	struct pd_discovery *disc =
-		pd_get_am_discovery(port, TCPC_TX_SOP_PRIME);
-
-	switch (pd_get_vdo_ver(port, TCPC_TX_SOP_PRIME)) {
-	case PD_REV20:
-		return disc->identity.product_t1.p_rev20.ss ==
-						USB_R20_SS_U31_GEN1_GEN2;
-
-	case PD_REV30:
-		return disc->identity.product_t1.p_rev30.ss ==
-						USB_R30_SS_U32_U40_GEN2 ||
-		       disc->identity.product_t1.p_rev30.ss ==
-						USB_R30_SS_U40_GEN3;
-	default:
-		return false;
-	}
-}
-
-bool is_active_cable_element_retimer(int port)
-{
-	struct pd_discovery *disc =
-		pd_get_am_discovery(port, TCPC_TX_SOP_PRIME);
-
-	/* Ref: USB PD Spec 2.0 Table 6-29 Active Cable VDO
-	 * Revision 2 Active cables do not have Active element support.
-	 */
-	return is_rev3_vdo(port, TCPC_TX_SOP_PRIME) &&
-		disc->identity.idh.product_type == IDH_PTYPE_ACABLE &&
-		disc->identity.product_t2.a2_rev30.active_elem ==
-							ACTIVE_RETIMER;
-}
-
-/*
- * ############################################################################
- *
- * Thunderbolt-Compatible functions
- *
- * ############################################################################
- */
-
-uint32_t pd_get_tbt_mode_vdo(int port, enum tcpm_transmit_type type)
-{
-	uint32_t tbt_mode_vdo[PDO_MODES];
-
-	return pd_get_mode_vdo_for_svid(port, type, USB_VID_INTEL,
-					tbt_mode_vdo) ? tbt_mode_vdo[0] : 0;
-}
-
-/* TODO (b/148528713): Need to enable Thunderbolt-compatible mode on TCPMv2 */
-void set_tbt_compat_mode_ready(int port)
-{
-	if (IS_ENABLED(CONFIG_USBC_SS_MUX) &&
-	    IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE)) {
-		/* Connect the SBU and USB lines to the connector. */
-		if (IS_ENABLED(CONFIG_USBC_PPC_SBU))
-			ppc_set_sbu(port, 1);
-
-		/* Set usb mux to Thunderbolt-compatible mode */
-		usb_mux_set(port, USB_PD_MUX_TBT_COMPAT_ENABLED,
-			USB_SWITCH_CONNECT, pd_get_polarity(port));
-	}
-}
-
-/*
- * Ref: USB Type-C Cable and Connector Specification
- * Figure F-1 TBT3 Discovery Flow
- */
-bool is_tbt_cable_superspeed(int port)
-{
-	struct pd_discovery *disc;
-
-	if (!IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE) ||
-	    !IS_ENABLED(CONFIG_USB_PD_DECODE_SOP))
-		return false;
-
-	disc = pd_get_am_discovery(port, TCPC_TX_SOP_PRIME);
-
-	/* Product type is Active cable, hence don't check for speed */
-	if (disc->identity.idh.product_type == IDH_PTYPE_ACABLE)
-		return true;
-
-	if (disc->identity.idh.product_type != IDH_PTYPE_PCABLE)
-		return false;
-
-	if (IS_ENABLED(CONFIG_USB_PD_REV30) &&
-	   is_rev3_vdo(port, TCPC_TX_SOP_PRIME))
-		return  disc->identity.product_t1.p_rev30.ss ==
-						USB_R30_SS_U32_U40_GEN1 ||
-			disc->identity.product_t1.p_rev30.ss ==
-						USB_R30_SS_U32_U40_GEN2 ||
-			disc->identity.product_t1.p_rev30.ss ==
-						USB_R30_SS_U40_GEN3;
-
-	return  disc->identity.product_t1.p_rev20.ss ==
-						USB_R20_SS_U31_GEN1 ||
-		disc->identity.product_t1.p_rev20.ss ==
-						USB_R20_SS_U31_GEN1_GEN2;
-}
-
-enum tbt_compat_cable_speed get_tbt_cable_speed(int port)
-{
-	union tbt_mode_resp_cable cable_mode_resp = {
-		.raw_value = pd_get_tbt_mode_vdo(port, TCPC_TX_SOP_PRIME) };
-	enum tbt_compat_cable_speed max_tbt_speed =
-				board_get_max_tbt_speed(port);
-
-	/*
-	 * Ref: USB Type-C Cable and Connector Specification,
-	 * figure F-1 TBT3 Discovery Flow.
-	 * If cable doesn't have Intel SVID, limit Thunderbolt cable speed to
-	 * Passive Gen 2 cable speed.
-	 */
-	if (!cable_mode_resp.raw_value)
-		return max_tbt_speed < TBT_SS_U32_GEN1_GEN2 ?
-			max_tbt_speed : TBT_SS_U32_GEN1_GEN2;
-
-	return max_tbt_speed < cable_mode_resp.tbt_cable_speed ?
-		max_tbt_speed : cable_mode_resp.tbt_cable_speed;
-}
-
-int enter_tbt_compat_mode(int port, enum tcpm_transmit_type sop,
-			uint32_t *payload)
-{
-	union tbt_dev_mode_enter_cmd enter_dev_mode = { .raw_value = 0 };
-	union tbt_mode_resp_device dev_mode_resp;
-	union tbt_mode_resp_cable cable_mode_resp;
-	enum tcpm_transmit_type enter_mode_sop =
-					sop == TCPC_TX_SOP_PRIME_PRIME ?
-						TCPC_TX_SOP_PRIME : sop;
-
-	/* Table F-12 TBT3 Cable Enter Mode Command */
-	/*
-	 * The port doesn't query Discover SOP'' to the cable so, the port
-	 * doesn't have opos for SOP''. Hence, send Enter Mode SOP'' with same
-	 * opos and revision as SOP'.
-	 */
-	payload[0] = pd_dfp_enter_mode(port, enter_mode_sop, USB_VID_INTEL, 0) |
-		     VDO_CMDT(CMDT_INIT) |
-		     VDO_SVDM_VERS(pd_get_vdo_ver(port, enter_mode_sop));
-
-	/* For TBT3 Cable Enter Mode Command, number of Objects is 1 */
-	if ((sop == TCPC_TX_SOP_PRIME) ||
-	    (sop == TCPC_TX_SOP_PRIME_PRIME))
-		return 1;
-
-	usb_mux_set_safe_mode(port);
-
-	dev_mode_resp.raw_value = pd_get_tbt_mode_vdo(port, TCPC_TX_SOP);
-	cable_mode_resp.raw_value =
-			pd_get_tbt_mode_vdo(port, TCPC_TX_SOP_PRIME);
-
-	/* Table F-13 TBT3 Device Enter Mode Command */
-	enter_dev_mode.vendor_spec_b1 = dev_mode_resp.vendor_spec_b1;
-	enter_dev_mode.vendor_spec_b0 = dev_mode_resp.vendor_spec_b0;
-	enter_dev_mode.intel_spec_b0 = dev_mode_resp.intel_spec_b0;
-	enter_dev_mode.cable =
-		get_usb_pd_cable_type(port) == IDH_PTYPE_PCABLE ?
-			TBT_ENTER_PASSIVE_CABLE : TBT_ENTER_ACTIVE_CABLE;
-
-	if (get_tbt_cable_speed(port) == TBT_SS_TBT_GEN3) {
-		enter_dev_mode.lsrx_comm =
-			cable_mode_resp.lsrx_comm;
-		enter_dev_mode.retimer_type =
-			cable_mode_resp.retimer_type;
-		enter_dev_mode.tbt_cable =
-			cable_mode_resp.tbt_cable;
-		enter_dev_mode.tbt_rounded =
-			cable_mode_resp.tbt_rounded;
-		enter_dev_mode.tbt_cable_speed =
-			cable_mode_resp.tbt_cable_speed;
-	} else {
-		enter_dev_mode.tbt_cable_speed = TBT_SS_U32_GEN1_GEN2;
-	}
-	enter_dev_mode.tbt_alt_mode = TBT_ALTERNATE_MODE;
-
-	payload[1] = enter_dev_mode.raw_value;
-
-	/* For TBT3 Device Enter Mode Command, number of Objects are 2 */
-	return 2;
-}
-
-enum tbt_compat_rounded_support get_tbt_rounded_support(int port)
-{
-	union tbt_mode_resp_cable cable_mode_resp = {
-		.raw_value = pd_get_tbt_mode_vdo(port, TCPC_TX_SOP_PRIME) };
-
-	/* tbt_rounded_support is zero when uninitialized */
-	return cable_mode_resp.tbt_rounded;
-}
-
-/* Return the current cable speed received from Cable Discover Mode command */
-__overridable enum tbt_compat_cable_speed board_get_max_tbt_speed(int port)
-{
-	union tbt_mode_resp_cable cable_mode_resp = {
-		.raw_value = pd_get_tbt_mode_vdo(port, TCPC_TX_SOP_PRIME) };
-
-	return cable_mode_resp.tbt_cable_speed;
-}
-/*
- * ############################################################################
- *
- * USB4 functions
- *
- * ############################################################################
- */
-
-/*
- * For Cable rev 3.0: USB4 cable speed is set according to speed supported by
- * the port and the response received from the cable, whichever is least.
- *
- * For Cable rev 2.0: If get_tbt_cable_speed() is less than
- * TBT_SS_U32_GEN1_GEN2, return USB_R30_SS_U2_ONLY speed since the board
- * doesn't support superspeed else the USB4 cable speed is set according to
- * the cable response.
- */
-enum usb_rev30_ss get_usb4_cable_speed(int port)
-{
-	struct pd_discovery *disc;
-	enum tbt_compat_cable_speed tbt_speed = get_tbt_cable_speed(port);
-	enum usb_rev30_ss max_usb4_speed;
-
-
-	if (tbt_speed < TBT_SS_U32_GEN1_GEN2)
-		return USB_R30_SS_U2_ONLY;
-
-	/*
-	 * Converting Thunderbolt-Compatible board speed to equivalent USB4
-	 * speed.
-	 */
-	max_usb4_speed = tbt_speed == TBT_SS_TBT_GEN3 ?
-		USB_R30_SS_U40_GEN3 : USB_R30_SS_U32_U40_GEN2;
-
-	if (is_rev3_vdo(port, TCPC_TX_SOP_PRIME)) {
-		disc = pd_get_am_discovery(port, TCPC_TX_SOP_PRIME);
-
-		return max_usb4_speed <  disc->identity.product_t1.p_rev30.ss ?
-		       max_usb4_speed :  disc->identity.product_t1.p_rev30.ss;
-	}
-
-	return max_usb4_speed;
-}
-
-uint32_t get_enter_usb_msg_payload(int port)
-{
-	/*
-	 * Ref: USB Power Delivery Specification Revision 3.0, Version 2.0
-	 * Table 6-47 Enter_USB Data Object
-	 */
-	union enter_usb_data_obj eudo;
-	struct pd_discovery *disc;
-
-	if (!IS_ENABLED(CONFIG_USB_PD_USB4))
-		return 0;
-
-	disc = pd_get_am_discovery(port, TCPC_TX_SOP_PRIME);
-	eudo.mode = USB_PD_40;
-	eudo.usb4_drd_cap = IS_ENABLED(CONFIG_USB_PD_USB4_DRD);
-	eudo.usb3_drd_cap = IS_ENABLED(CONFIG_USB_PD_USB32_DRD);
-	eudo.cable_speed = get_usb4_cable_speed(port);
-
-	if (is_rev3_vdo(port, TCPC_TX_SOP_PRIME) &&
-	    (disc->identity.idh.product_type == IDH_PTYPE_ACABLE)) {
-		eudo.cable_type =
-			(disc->identity.product_t2.a2_rev30.active_elem ==
-			ACTIVE_RETIMER) ? CABLE_TYPE_ACTIVE_RETIMER :
-			CABLE_TYPE_ACTIVE_REDRIVER;
-	/* TODO: Add eudo.cable_type for Revisiosn 2 active cables */
-	} else {
-		eudo.cable_type = CABLE_TYPE_PASSIVE;
-	}
-
-	switch (disc->identity.product_t1.p_rev20.vbus_cur) {
-	case USB_VBUS_CUR_3A:
-		eudo.cable_current = USB4_CABLE_CURRENT_3A;
-		break;
-	case USB_VBUS_CUR_5A:
-		eudo.cable_current = USB4_CABLE_CURRENT_5A;
-		break;
-	default:
-		eudo.cable_current = USB4_CABLE_CURRENT_INVALID;
-		break;
-	}
-	eudo.pcie_supported = IS_ENABLED(CONFIG_USB_PD_PCIE_TUNNELING);
-	eudo.dp_supported = IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP);
-	eudo.tbt_supported = IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE);
-	eudo.host_present = 1;
-
-	return eudo.raw_value;
-}
-
-__overridable bool board_is_tbt_usb4_port(int port)
-{
-	return true;
-}
-
-__overridable void svdm_safe_dp_mode(int port)
-{
-	/* make DP interface safe until configure */
-	dp_flags[port] = 0;
-	dp_status[port] = 0;
-
-	usb_mux_set_safe_mode(port);
-}
-
-__overridable int svdm_enter_dp_mode(int port, uint32_t mode_caps)
-{
-	/*
-	 * Don't enter the mode if the SoC is off.
-	 *
-	 * There's no need to enter the mode while the SoC is off; we'll
-	 * actually enter the mode on the chipset resume hook.  Entering DP Alt
-	 * Mode twice will confuse some monitors and require and unplug/replug
-	 * to get them to work again.  The DP Alt Mode on USB-C spec says that
-	 * if we don't need to maintain HPD connectivity info in a low power
-	 * mode, then we shall exit DP Alt Mode.  (This is why we don't enter
-	 * when the SoC is off as opposed to suspend where adding a display
-	 * could cause a wake up.)
-	 */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return -1;
-
-	/* Only enter mode if device is DFP_D capable */
-	if (mode_caps & MODE_DP_SNK) {
-		svdm_safe_dp_mode(port);
-
-		if (IS_ENABLED(CONFIG_MKBP_EVENT) &&
-		    chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-			/*
-			 * Wake the system up since we're entering DP AltMode.
-			 */
-			pd_notify_dp_alt_mode_entry();
-
-		return 0;
-	}
-
-	return -1;
-}
-
-__overridable int svdm_dp_status(int port, uint32_t *payload)
-{
-	int opos = pd_alt_mode(port, TCPC_TX_SOP, USB_SID_DISPLAYPORT);
-
-	payload[0] = VDO(USB_SID_DISPLAYPORT, 1,
-			 CMD_DP_STATUS | VDO_OPOS(opos));
-	payload[1] = VDO_DP_STATUS(0, /* HPD IRQ  ... not applicable */
-				   0, /* HPD level ... not applicable */
-				   0, /* exit DP? ... no */
-				   0, /* usb mode? ... no */
-				   0, /* multi-function ... no */
-				   (!!(dp_flags[port] & DP_FLAGS_DP_ON)),
-				   0, /* power low? ... no */
-				   (!!DP_FLAGS_DP_ON));
-	return 2;
-};
-
-__overridable uint8_t get_dp_pin_mode(int port)
-{
-	return pd_dfp_dp_get_pin_mode(port, dp_status[port]);
-}
-
-__overridable int svdm_dp_config(int port, uint32_t *payload)
-{
-	int opos = pd_alt_mode(port, TCPC_TX_SOP, USB_SID_DISPLAYPORT);
-	int mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]);
-	uint8_t pin_mode = get_dp_pin_mode(port);
-	mux_state_t mux_mode;
-
-	if (!pin_mode)
-		return 0;
-
-	/*
-	 * Multi-function operation is only allowed if that pin config is
-	 * supported.
-	 */
-	mux_mode = ((pin_mode & MODE_DP_PIN_MF_MASK) && mf_pref) ?
-		USB_PD_MUX_DOCK : USB_PD_MUX_DP_ENABLED;
-	CPRINTS("pin_mode: %x, mf: %d, mux: %d", pin_mode, mf_pref, mux_mode);
-
-	/* Connect the SBU and USB lines to the connector. */
-	if (IS_ENABLED(CONFIG_USBC_PPC_SBU))
-		ppc_set_sbu(port, 1);
-	usb_mux_set(port, mux_mode, USB_SWITCH_CONNECT, pd_get_polarity(port));
-
-	payload[0] = VDO(USB_SID_DISPLAYPORT, 1,
-			 CMD_DP_CONFIG | VDO_OPOS(opos));
-	payload[1] = VDO_DP_CFG(pin_mode,      /* pin mode */
-				1,	       /* DPv1.3 signaling */
-				2);	       /* UFP connected */
-	return 2;
-};
-
-#if defined(CONFIG_USB_PD_DP_HPD_GPIO) && \
-	!defined(CONFIG_USB_PD_DP_HPD_GPIO_CUSTOM)
-void svdm_set_hpd_gpio(int port, int en)
-{
-	gpio_set_level(PORT_TO_HPD(port), en);
-}
-
-int svdm_get_hpd_gpio(int port)
-{
-	return gpio_get_level(PORT_TO_HPD(port));
-}
-#endif
-
-__overridable void svdm_dp_post_config(int port)
-{
-	dp_flags[port] |= DP_FLAGS_DP_ON;
-	if (!(dp_flags[port] & DP_FLAGS_HPD_HI_PENDING))
-		return;
-
-#ifdef CONFIG_USB_PD_DP_HPD_GPIO
-	svdm_set_hpd_gpio(port, 1);
-
-	/* set the minimum time delay (2ms) for the next HPD IRQ */
-	svdm_hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
-#endif /* CONFIG_USB_PD_DP_HPD_GPIO */
-
-	usb_mux_hpd_update(port, 1, 0);
-
-#ifdef USB_PD_PORT_TCPC_MST
-	if (port == USB_PD_PORT_TCPC_MST)
-		baseboard_mst_enable_control(port, 1);
-#endif
-}
-
-__overridable int svdm_dp_attention(int port, uint32_t *payload)
-{
-	int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]);
-	int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]);
-#ifdef CONFIG_USB_PD_DP_HPD_GPIO
-	int cur_lvl = svdm_get_hpd_gpio(port);
-#endif /* CONFIG_USB_PD_DP_HPD_GPIO */
-
-	dp_status[port] = payload[1];
-
-	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
-	    (irq || lvl))
-		/*
-		 * Wake up the AP.  IRQ or level high indicates a DP sink is now
-		 * present.
-		 */
-		if (IS_ENABLED(CONFIG_MKBP_EVENT))
-			pd_notify_dp_alt_mode_entry();
-
-	/* Its initial DP status message prior to config */
-	if (!(dp_flags[port] & DP_FLAGS_DP_ON)) {
-		if (lvl)
-			dp_flags[port] |= DP_FLAGS_HPD_HI_PENDING;
-		return 1;
-	}
-
-#ifdef CONFIG_USB_PD_DP_HPD_GPIO
-	if (irq & !lvl) {
-		/*
-		 * IRQ can only be generated when the level is high, because
-		 * the IRQ is signaled by a short low pulse from the high level.
-		 */
-		CPRINTF("ERR:HPD:IRQ&LOW\n");
-		return 0; /* nak */
-	}
-
-	if (irq & cur_lvl) {
-		uint64_t now = get_time().val;
-		/* wait for the minimum spacing between IRQ_HPD if needed */
-		if (now < svdm_hpd_deadline[port])
-			usleep(svdm_hpd_deadline[port] - now);
-
-		/* generate IRQ_HPD pulse */
-		svdm_set_hpd_gpio(port, 0);
-		usleep(HPD_DSTREAM_DEBOUNCE_IRQ);
-		svdm_set_hpd_gpio(port, 1);
-	} else {
-		svdm_set_hpd_gpio(port, lvl);
-	}
-
-	/* set the minimum time delay (2ms) for the next HPD IRQ */
-	svdm_hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
-#endif /* CONFIG_USB_PD_DP_HPD_GPIO */
-
-	usb_mux_hpd_update(port, lvl, irq);
-
-#ifdef USB_PD_PORT_TCPC_MST
-	if (port == USB_PD_PORT_TCPC_MST)
-		baseboard_mst_enable_control(port, lvl);
-#endif
-
-	/* ack */
-	return 1;
-}
-
-__overridable void svdm_exit_dp_mode(int port)
-{
-	svdm_safe_dp_mode(port);
-#ifdef CONFIG_USB_PD_DP_HPD_GPIO
-	svdm_set_hpd_gpio(port, 0);
-#endif /* CONFIG_USB_PD_DP_HPD_GPIO */
-	usb_mux_hpd_update(port, 0, 0);
-#ifdef USB_PD_PORT_TCPC_MST
-	if (port == USB_PD_PORT_TCPC_MST)
-		baseboard_mst_enable_control(port, 0);
-#endif
-#ifdef CONFIG_USB_PD_TCPMV2
-	dp_teardown(port);
-#endif
-}
-
-__overridable int svdm_enter_gfu_mode(int port, uint32_t mode_caps)
-{
-	/* Always enter GFU mode */
-	return 0;
-}
-
-__overridable void svdm_exit_gfu_mode(int port)
-{
-}
-
-__overridable int svdm_gfu_status(int port, uint32_t *payload)
-{
-	/*
-	 * This is called after enter mode is successful, send unstructured
-	 * VDM to read info.
-	 */
-	pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_READ_INFO, NULL, 0);
-	return 0;
-}
-
-__overridable int svdm_gfu_config(int port, uint32_t *payload)
-{
-	return 0;
-}
-
-__overridable int svdm_gfu_attention(int port, uint32_t *payload)
-{
-	return 0;
-}
-
-#ifdef CONFIG_USB_PD_TBT_COMPAT_MODE
-__overridable int svdm_tbt_compat_enter_mode(int port, uint32_t mode_caps)
-{
-	return 0;
-}
-
-__overridable void svdm_tbt_compat_exit_mode(int port)
-{
-	if (IS_ENABLED(CONFIG_USB_PD_TCPMV2)) {
-		usb_mux_set_safe_mode(port);
-		tbt_teardown(port);
-	}
-}
-
-__overridable int svdm_tbt_compat_status(int port, uint32_t *payload)
-{
-	return 0;
-}
-
-__overridable int svdm_tbt_compat_config(int port, uint32_t *payload)
-{
-	return 0;
-}
-
-__overridable int svdm_tbt_compat_attention(int port, uint32_t *payload)
-{
-	return 0;
-}
-#endif /* CONFIG_USB_PD_TBT_COMPAT_MODE */
-
-const struct svdm_amode_fx supported_modes[] = {
-	{
-		.svid = USB_SID_DISPLAYPORT,
-		.enter = &svdm_enter_dp_mode,
-		.status = &svdm_dp_status,
-		.config = &svdm_dp_config,
-		.post_config = &svdm_dp_post_config,
-		.attention = &svdm_dp_attention,
-		.exit = &svdm_exit_dp_mode,
-	},
-
-	{
-		.svid = USB_VID_GOOGLE,
-		.enter = &svdm_enter_gfu_mode,
-		.status = &svdm_gfu_status,
-		.config = &svdm_gfu_config,
-		.attention = &svdm_gfu_attention,
-		.exit = &svdm_exit_gfu_mode,
-	},
-#ifdef CONFIG_USB_PD_TBT_COMPAT_MODE
-	{
-		.svid = USB_VID_INTEL,
-		.enter = &svdm_tbt_compat_enter_mode,
-		.status = &svdm_tbt_compat_status,
-		.config = &svdm_tbt_compat_config,
-		.attention = &svdm_tbt_compat_attention,
-		.exit = &svdm_tbt_compat_exit_mode,
-	},
-#endif /* CONFIG_USB_PD_TBT_COMPAT_MODE */
-};
-const int supported_modes_cnt = ARRAY_SIZE(supported_modes);
diff --git a/common/usb_pd_alt_mode_ufp.c b/common/usb_pd_alt_mode_ufp.c
new file mode 100644
index 0000000000..5585056b58
--- /dev/null
+++ b/common/usb_pd_alt_mode_ufp.c
@@ -0,0 +1,22 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Alternate Mode Upstream Facing Port (UFP) USB-PD module.
+ */
+#include "usb_pd.h"
+#include "usb_tbt_alt_mode.h"
+
+static uint32_t ufp_enter_mode[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+/* Save port partner's enter mode message */
+void pd_ufp_set_enter_mode(int port, uint32_t *payload)
+{
+	ufp_enter_mode[port] = payload[1];
+}
+
+/* Return port partner's enter mode message */
+uint32_t pd_ufp_get_enter_mode(int port)
+{
+	return ufp_enter_mode[port];
+}
diff --git a/common/usb_pd_console_cmd.c b/common/usb_pd_console_cmd.c
index c155a59077..9d03bdf9aa 100644
--- a/common/usb_pd_console_cmd.c
+++ b/common/usb_pd_console_cmd.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -7,6 +7,7 @@
 
 #include "console.h"
 #include "usb_pd.h"
+#include "usb_pd_tcpm.h"
 #include "util.h"
 
 #ifdef CONFIG_USB_PD_ALT_MODE_DFP
@@ -14,32 +15,30 @@
 static void dump_pe(int port)
 {
 	int i, j, idh_ptype;
-	struct svdm_amode_data *modep;
-	uint32_t mode_caps;
 	const union disc_ident_ack *resp;
-	enum tcpm_transmit_type type;
+	enum tcpci_msg_type type;
 	/* TODO(b/152417597): Output SOP' discovery results */
 	const struct pd_discovery *disc =
-		pd_get_am_discovery(port, TCPC_TX_SOP);
+		pd_get_am_discovery(port, TCPCI_MSG_SOP);
 
-	static const char * const idh_ptype_names[]  = {
-		"UNDEF", "Hub", "Periph", "PCable", "ACable", "AMA",
-		"RSV6", "RSV7"};
-	static const char * const tx_names[] = {"SOP", "SOP'", "SOP''"};
+	static const char *const idh_ptype_names[] = { "UNDEF",	 "Hub",
+						       "Periph", "PCable",
+						       "ACable", "AMA",
+						       "RSV6",	 "RSV7" };
+	static const char *const tx_names[] = { "SOP", "SOP'", "SOP''" };
 
-	for (type = TCPC_TX_SOP; type < DISCOVERY_TYPE_COUNT; type++) {
+	for (type = TCPCI_MSG_SOP; type < DISCOVERY_TYPE_COUNT; type++) {
 		resp = pd_get_identity_response(port, type);
 		if (pd_get_identity_discovery(port, type) != PD_DISC_COMPLETE) {
 			ccprintf("No %s identity discovered yet.\n",
-								tx_names[type]);
+				 tx_names[type]);
 			continue;
 		}
 
 		idh_ptype = resp->idh.product_type;
 		ccprintf("IDENT %s:\n", tx_names[type]);
 		ccprintf("\t[ID Header] %08x :: %s, VID:%04x\n",
-			 resp->raw_value[0],
-			 idh_ptype_names[idh_ptype],
+			 resp->raw_value[0], idh_ptype_names[idh_ptype],
 			 resp->idh.usb_vendor_id);
 
 		ccprintf("\t[Cert Stat] %08x\n", resp->cert.xid);
@@ -51,30 +50,22 @@ static void dump_pe(int port)
 		ccprintf("\n");
 	}
 
-	if (pd_get_svid_count(port, TCPC_TX_SOP) < 1) {
+	if (pd_get_svid_count(port, TCPCI_MSG_SOP) < 1) {
 		ccprintf("No SVIDS discovered yet.\n");
 		return;
 	}
 
 	/* TODO(b/152418267): Display discovered SVIDs and modes for SOP' */
-	for (i = 0; i < pd_get_svid_count(port, TCPC_TX_SOP); i++) {
+	for (i = 0; i < pd_get_svid_count(port, TCPCI_MSG_SOP); i++) {
 		ccprintf("SVID[%d]: %04x MODES:", i, disc->svids[i].svid);
 		for (j = 0; j < disc->svids[j].mode_cnt; j++)
 			ccprintf(" [%d] %08x", j + 1,
-					disc->svids[i].mode_vdo[j]);
+				 disc->svids[i].mode_vdo[j]);
 		ccprintf("\n");
-
-		modep = pd_get_amode_data(port, TCPC_TX_SOP,
-				disc->svids[i].svid);
-		if (modep) {
-			mode_caps = modep->data->mode_vdo[modep->opos - 1];
-			ccprintf("MODE[%d]: svid:%04x caps:%08x\n", modep->opos,
-				 modep->fx->svid, mode_caps);
-		}
 	}
 }
 
-static int command_pe(int argc, char **argv)
+static int command_pe(int argc, const char **argv)
 {
 	int port;
 	char *e;
@@ -91,29 +82,28 @@ static int command_pe(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(pe, command_pe,
-			"<port> dump",
-			"USB PE");
+DECLARE_CONSOLE_COMMAND(pe, command_pe, "<port> dump", "USB PE");
 #endif /* CONFIG_CMD_USB_PD_PE */
 
 #ifdef CONFIG_CMD_USB_PD_CABLE
-static const char * const cable_type[] = {
+static const char *const cable_type[] = {
 	[IDH_PTYPE_PCABLE] = "Passive",
 	[IDH_PTYPE_ACABLE] = "Active",
 };
 
-static const char * const cable_curr[] = {
+static const char *const cable_curr[] = {
 	[USB_VBUS_CUR_3A] = "3A",
 	[USB_VBUS_CUR_5A] = "5A",
 };
 
-static int command_cable(int argc, char **argv)
+static int command_cable(int argc, const char **argv)
 {
 	int port;
 	char *e;
-	struct pd_discovery *disc;
+	const struct pd_discovery *disc;
 	enum idh_ptype ptype;
 	int cable_rev;
+	union tbt_mode_resp_cable cable_mode_resp;
 
 	if (argc < 2)
 		return EC_ERROR_PARAM_COUNT;
@@ -125,15 +115,18 @@ static int command_cable(int argc, char **argv)
 	ptype = get_usb_pd_cable_type(port);
 
 	ccprintf("Cable Type: ");
-	if (ptype != IDH_PTYPE_PCABLE &&
-		ptype != IDH_PTYPE_ACABLE) {
+	if (ptype != IDH_PTYPE_PCABLE && ptype != IDH_PTYPE_ACABLE) {
 		ccprintf("Not Emark Cable\n");
 		return EC_SUCCESS;
 	}
 	ccprintf("%s\n", cable_type[ptype]);
 
-	cable_rev = pd_get_vdo_ver(port, TCPC_TX_SOP_PRIME);
-	disc = pd_get_am_discovery(port, TCPC_TX_SOP_PRIME);
+	cable_rev = pd_get_rev(port, TCPCI_MSG_SOP_PRIME);
+	disc = pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
+	cable_mode_resp.raw_value =
+		IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE) ?
+			pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME) :
+			0;
 
 	/* Cable revision */
 	ccprintf("Cable Rev: %d.0\n", cable_rev + 1);
@@ -143,13 +136,15 @@ static int command_cable(int argc, char **argv)
 	 * connector type (Bit 19:18) and current handling capability bit 6:5
 	 */
 	ccprintf("Connector Type: %d\n",
-				disc->identity.product_t1.p_rev20.connector);
+		 disc->identity.product_t1.p_rev20.connector);
 
 	if (disc->identity.product_t1.p_rev20.vbus_cur) {
 		ccprintf("Cable Current: %s\n",
-		   disc->identity.product_t1.p_rev20.vbus_cur >
-		      ARRAY_SIZE(cable_curr) ? "Invalid" :
-		      cable_curr[disc->identity.product_t1.p_rev20.vbus_cur]);
+			 disc->identity.product_t1.p_rev20.vbus_cur >
+					 ARRAY_SIZE(cable_curr) ?
+				 "Invalid" :
+				 cable_curr[disc->identity.product_t1.p_rev20
+						    .vbus_cur]);
 	} else
 		ccprintf("Cable Current: Invalid\n");
 
@@ -159,7 +154,7 @@ static int command_cable(int argc, char **argv)
 	 */
 	if (ptype == IDH_PTYPE_PCABLE)
 		ccprintf("USB Superspeed Signaling support: %d\n",
-			disc->identity.product_t1.p_rev20.ss);
+			 disc->identity.product_t1.p_rev20.ss);
 
 	/*
 	 * For Rev 3.0 active cables and Rev 2.0 active and passive cables,
@@ -167,7 +162,8 @@ static int command_cable(int argc, char **argv)
 	 */
 	if (ptype == IDH_PTYPE_ACABLE)
 		ccprintf("SOP'' Controller: %s present\n",
-		      disc->identity.product_t1.a_rev20.sop_p_p ? "" : "Not");
+			 disc->identity.product_t1.a_rev20.sop_p_p ? "" :
+								     "Not");
 
 	if (cable_rev == PD_REV30) {
 		/*
@@ -175,22 +171,46 @@ static int command_cable(int argc, char **argv)
 		 * same bits 10:9.
 		 */
 		ccprintf("Max vbus voltage: %d\n",
-			20 + 10 * disc->identity.product_t1.p_rev30.vbus_max);
+			 20 + 10 * disc->identity.product_t1.p_rev30.vbus_max);
 
 		/* For Rev 3.0 Active cables */
 		if (ptype == IDH_PTYPE_ACABLE) {
 			ccprintf("SS signaling: USB_SS_GEN%u\n",
-				disc->identity.product_t2.a2_rev30.usb_gen ?
-									2 : 1);
+				 disc->identity.product_t2.a2_rev30.usb_gen ?
+					 2 :
+					 1);
 			ccprintf("Number of SS lanes supported: %u\n",
-				disc->identity.product_t2.a2_rev30.usb_lanes);
+				 disc->identity.product_t2.a2_rev30.usb_lanes);
 		}
 	}
+
+	if (!cable_mode_resp.raw_value)
+		return EC_SUCCESS;
+
+	ccprintf("Rounded support: %s\n",
+		 cable_mode_resp.tbt_rounded ==
+				 TBT_GEN3_GEN4_ROUNDED_NON_ROUNDED ?
+			 "Yes" :
+			 "No");
+
+	ccprintf("Optical cable: %s\n",
+		 cable_mode_resp.tbt_cable == TBT_CABLE_OPTICAL ? "Yes" : "No");
+
+	ccprintf("Retimer support: %s\n",
+		 cable_mode_resp.retimer_type == USB_RETIMER ? "Yes" : "No");
+
+	ccprintf("Link training: %s-directional\n",
+		 cable_mode_resp.lsrx_comm == BIDIR_LSRX_COMM ? "Bi" : "Uni");
+
+	ccprintf("Thunderbolt cable type: %s\n",
+		 cable_mode_resp.tbt_active_passive == TBT_CABLE_ACTIVE ?
+			 "Active" :
+			 "Passive");
+
 	return EC_SUCCESS;
 }
 
-DECLARE_CONSOLE_COMMAND(pdcable, command_cable,
-			"<port>",
+DECLARE_CONSOLE_COMMAND(pdcable, command_cable, "<port>",
 			"Cable Characteristics");
 #endif /* CONFIG_CMD_USB_PD_CABLE */
 
diff --git a/common/usb_pd_discovery.c b/common/usb_pd_discovery.c
new file mode 100644
index 0000000000..589be657b5
--- /dev/null
+++ b/common/usb_pd_discovery.c
@@ -0,0 +1,452 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Alternate Mode Discovery storage, access, and helpers
+ */
+
+#include "builtin/assert.h"
+#include "chipset.h"
+#include "console.h"
+#include "gpio.h"
+#include "task.h"
+#include "task_id.h"
+#include "timer.h"
+#include "typec_control.h"
+#include "usb_charge.h"
+#include "usb_common.h"
+#include "usb_dp_alt_mode.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usb_tbt_alt_mode.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#ifdef CONFIG_COMMON_RUNTIME
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#else
+#define CPRINTS(format, args...)
+#define CPRINTF(format, args...)
+#endif
+
+/*
+ * Check if the SVID has been recorded previously. Some peripherals provide
+ * duplicated SVID.
+ */
+static bool is_svid_duplicated(const struct pd_discovery *disc, uint16_t svid)
+{
+	int i;
+
+	for (i = 0; i < disc->svid_cnt; ++i)
+		if (disc->svids[i].svid == svid) {
+			CPRINTF("ERR:SVIDDUP\n");
+			return true;
+		}
+
+	return false;
+}
+
+void dfp_consume_identity(int port, enum tcpci_msg_type type, int cnt,
+			  uint32_t *payload)
+{
+	int ptype;
+	struct pd_discovery *disc;
+	size_t identity_size;
+
+	if (type == TCPCI_MSG_SOP_PRIME &&
+	    !IS_ENABLED(CONFIG_USB_PD_DECODE_SOP)) {
+		CPRINTF("ERR:Unexpected cable response\n");
+		return;
+	}
+
+	ptype = PD_IDH_PTYPE(payload[VDO_I(IDH)]);
+	disc = pd_get_am_discovery_and_notify_access(port, type);
+	identity_size =
+		MIN(sizeof(union disc_ident_ack), (cnt - 1) * sizeof(uint32_t));
+
+	/* Note: only store VDOs, not the VDM header */
+	memcpy(disc->identity.raw_value, payload + 1, identity_size);
+	disc->identity_cnt = identity_size / sizeof(uint32_t);
+
+	switch (ptype) {
+	case IDH_PTYPE_AMA:
+		/* Leave vbus ON if the following macro is false */
+		if (IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE) &&
+		    IS_ENABLED(CONFIG_USBC_VCONN_SWAP)) {
+			/* Adapter is requesting vconn, try to supply it */
+			if (PD_VDO_AMA_VCONN_REQ(payload[VDO_I(AMA)]))
+				pd_try_vconn_src(port);
+
+			/* Only disable vbus if vconn was requested */
+			if (PD_VDO_AMA_VCONN_REQ(payload[VDO_I(AMA)]) &&
+			    !PD_VDO_AMA_VBUS_REQ(payload[VDO_I(AMA)]))
+				pd_power_supply_reset(port);
+		}
+		break;
+	default:
+		break;
+	}
+	pd_set_identity_discovery(port, type, PD_DISC_COMPLETE);
+}
+
+void dfp_consume_svids(int port, enum tcpci_msg_type type, int cnt,
+		       uint32_t *payload)
+{
+	int i;
+	uint32_t *ptr = payload + 1;
+	int vdo = 1;
+	uint16_t svid0, svid1;
+	struct pd_discovery *disc =
+		pd_get_am_discovery_and_notify_access(port, type);
+
+	for (i = disc->svid_cnt; i < disc->svid_cnt + 12; i += 2) {
+		if (i >= SVID_DISCOVERY_MAX) {
+			CPRINTF("ERR:SVIDCNT\n");
+			break;
+		}
+		/*
+		 * Verify we're still within the valid packet (count will be one
+		 * for the VDM header + xVDOs)
+		 */
+		if (vdo >= cnt)
+			break;
+
+		svid0 = PD_VDO_SVID_SVID0(*ptr);
+		if (!svid0)
+			break;
+
+		if (!is_svid_duplicated(disc, svid0))
+			disc->svids[disc->svid_cnt++].svid = svid0;
+
+		svid1 = PD_VDO_SVID_SVID1(*ptr);
+		if (!svid1)
+			break;
+
+		if (!is_svid_duplicated(disc, svid1))
+			disc->svids[disc->svid_cnt++].svid = svid1;
+
+		ptr++;
+		vdo++;
+	}
+	/* TODO(tbroch) need to re-issue discover svids if > 12 */
+	if (i && ((i % 12) == 0))
+		CPRINTF("ERR:SVID+12\n");
+
+	pd_set_svids_discovery(port, type, PD_DISC_COMPLETE);
+}
+
+void dfp_consume_modes(int port, enum tcpci_msg_type type, int cnt,
+		       uint32_t *payload)
+{
+	int svid_idx;
+	struct svid_mode_data *mode_discovery = NULL;
+	struct pd_discovery *disc =
+		pd_get_am_discovery_and_notify_access(port, type);
+	uint16_t response_svid = (uint16_t)PD_VDO_VID(payload[0]);
+	const struct svid_mode_data *requested_mode_data =
+		pd_get_next_mode(port, type);
+
+	for (svid_idx = 0; svid_idx < disc->svid_cnt; ++svid_idx) {
+		uint16_t svid = disc->svids[svid_idx].svid;
+
+		if (svid == response_svid) {
+			mode_discovery = &disc->svids[svid_idx];
+			break;
+		}
+	}
+	if (!mode_discovery || (requested_mode_data->svid != response_svid)) {
+		CPRINTF("C%d: Unexpected mode repsonse for SVID %x, but TCPM "
+			"requested SVID %x\n",
+			port, response_svid, requested_mode_data->svid);
+		/*
+		 * Although SVIDs discovery seemed like it succeeded before, the
+		 * partner is now responding with undiscovered SVIDs. Discovery
+		 * cannot reasonably continue under these circumstances.
+		 */
+		pd_set_modes_discovery(port, type, requested_mode_data->svid,
+				       PD_DISC_FAIL);
+		return;
+	}
+
+	mode_discovery->mode_cnt = cnt - 1;
+	if (mode_discovery->mode_cnt < 1) {
+		CPRINTF("ERR:NOMODE\n");
+		pd_set_modes_discovery(port, type, mode_discovery->svid,
+				       PD_DISC_FAIL);
+		return;
+	}
+
+	memcpy(mode_discovery->mode_vdo, &payload[1],
+	       sizeof(uint32_t) * mode_discovery->mode_cnt);
+	disc->svid_idx++;
+	pd_set_modes_discovery(port, type, mode_discovery->svid,
+			       PD_DISC_COMPLETE);
+}
+
+void pd_disable_discovery(int port)
+{
+	/* Mark identity and SVIDs for the port partner and cable as failed.
+	 * With no discovered SVIDs, there are no modes to mark as failed.
+	 */
+	pd_set_identity_discovery(port, TCPCI_MSG_SOP, PD_DISC_FAIL);
+	pd_set_svids_discovery(port, TCPCI_MSG_SOP, PD_DISC_FAIL);
+	pd_set_identity_discovery(port, TCPCI_MSG_SOP_PRIME, PD_DISC_FAIL);
+	pd_set_svids_discovery(port, TCPCI_MSG_SOP_PRIME, PD_DISC_FAIL);
+}
+
+void pd_set_identity_discovery(int port, enum tcpci_msg_type type,
+			       enum pd_discovery_state disc)
+{
+	struct pd_discovery *pd =
+		pd_get_am_discovery_and_notify_access(port, type);
+
+	pd->identity_discovery = disc;
+}
+
+enum pd_discovery_state pd_get_identity_discovery(int port,
+						  enum tcpci_msg_type type)
+{
+	const struct pd_discovery *disc = pd_get_am_discovery(port, type);
+
+	return disc->identity_discovery;
+}
+
+const union disc_ident_ack *pd_get_identity_response(int port,
+						     enum tcpci_msg_type type)
+{
+	if (type >= DISCOVERY_TYPE_COUNT)
+		return NULL;
+
+	return &pd_get_am_discovery(port, type)->identity;
+}
+
+uint16_t pd_get_identity_vid(int port)
+{
+	const union disc_ident_ack *resp =
+		pd_get_identity_response(port, TCPCI_MSG_SOP);
+
+	return resp->idh.usb_vendor_id;
+}
+
+uint16_t pd_get_identity_pid(int port)
+{
+	const union disc_ident_ack *resp =
+		pd_get_identity_response(port, TCPCI_MSG_SOP);
+
+	return resp->product.product_id;
+}
+
+uint8_t pd_get_product_type(int port)
+{
+	const union disc_ident_ack *resp =
+		pd_get_identity_response(port, TCPCI_MSG_SOP);
+
+	return resp->idh.product_type;
+}
+
+void pd_set_svids_discovery(int port, enum tcpci_msg_type type,
+			    enum pd_discovery_state disc)
+{
+	struct pd_discovery *pd =
+		pd_get_am_discovery_and_notify_access(port, type);
+
+	pd->svids_discovery = disc;
+}
+
+enum pd_discovery_state pd_get_svids_discovery(int port,
+					       enum tcpci_msg_type type)
+{
+	const struct pd_discovery *disc = pd_get_am_discovery(port, type);
+
+	return disc->svids_discovery;
+}
+
+int pd_get_svid_count(int port, enum tcpci_msg_type type)
+{
+	const struct pd_discovery *disc = pd_get_am_discovery(port, type);
+
+	return disc->svid_cnt;
+}
+
+uint16_t pd_get_svid(int port, uint16_t svid_idx, enum tcpci_msg_type type)
+{
+	const struct pd_discovery *disc = pd_get_am_discovery(port, type);
+
+	return disc->svids[svid_idx].svid;
+}
+
+void pd_set_modes_discovery(int port, enum tcpci_msg_type type, uint16_t svid,
+			    enum pd_discovery_state disc)
+{
+	struct pd_discovery *pd =
+		pd_get_am_discovery_and_notify_access(port, type);
+	int svid_idx;
+
+	for (svid_idx = 0; svid_idx < pd->svid_cnt; ++svid_idx) {
+		struct svid_mode_data *mode_data = &pd->svids[svid_idx];
+
+		if (mode_data->svid != svid)
+			continue;
+
+		mode_data->discovery = disc;
+		return;
+	}
+}
+
+enum pd_discovery_state pd_get_modes_discovery(int port,
+					       enum tcpci_msg_type type)
+{
+	const struct svid_mode_data *mode_data = pd_get_next_mode(port, type);
+
+	/*
+	 * If there are no SVIDs for which to discover modes, mode discovery is
+	 * trivially complete.
+	 */
+	if (!mode_data)
+		return PD_DISC_COMPLETE;
+
+	return mode_data->discovery;
+}
+
+int pd_get_mode_vdo_for_svid(int port, enum tcpci_msg_type type, uint16_t svid,
+			     uint32_t *vdo_out)
+{
+	int idx;
+	const struct pd_discovery *disc;
+
+	if (type >= DISCOVERY_TYPE_COUNT)
+		return 0;
+
+	disc = pd_get_am_discovery(port, type);
+
+	for (idx = 0; idx < disc->svid_cnt; ++idx) {
+		if (pd_get_svid(port, idx, type) == svid) {
+			memcpy(vdo_out, disc->svids[idx].mode_vdo,
+			       sizeof(uint32_t) * disc->svids[idx].mode_cnt);
+			return disc->svids[idx].mode_cnt;
+		}
+	}
+	return 0;
+}
+
+const struct svid_mode_data *pd_get_next_mode(int port,
+					      enum tcpci_msg_type type)
+{
+	const struct pd_discovery *disc = pd_get_am_discovery(port, type);
+	const struct svid_mode_data *failed_mode_data = NULL;
+	bool svid_good_discovery = false;
+	int svid_idx;
+
+	/* Walk through all of the discovery mode entries */
+	for (svid_idx = 0; svid_idx < disc->svid_cnt; ++svid_idx) {
+		const struct svid_mode_data *mode_data = &disc->svids[svid_idx];
+
+		/* Discovery is needed, so send this one back now */
+		if (mode_data->discovery == PD_DISC_NEEDED)
+			return mode_data;
+
+		/* Discovery already succeeded, save that it was seen */
+		if (mode_data->discovery == PD_DISC_COMPLETE)
+			svid_good_discovery = true;
+		/* Discovery already failed, save first failure */
+		else if (!failed_mode_data)
+			failed_mode_data = mode_data;
+	}
+
+	/* If no good entries were located, then return last failed */
+	if (!svid_good_discovery)
+		return failed_mode_data;
+
+	/*
+	 * Mode discovery has been attempted for every discovered SVID (if
+	 * any exist)
+	 */
+	return NULL;
+}
+
+bool pd_is_mode_discovered_for_svid(int port, enum tcpci_msg_type type,
+				    uint16_t svid)
+{
+	const struct pd_discovery *disc = pd_get_am_discovery(port, type);
+	const struct svid_mode_data *mode_data;
+
+	for (mode_data = disc->svids; mode_data < disc->svids + disc->svid_cnt;
+	     ++mode_data) {
+		if (mode_data->svid == svid &&
+		    mode_data->discovery == PD_DISC_COMPLETE)
+			return true;
+	}
+
+	return false;
+}
+
+static inline bool is_pd_rev3(int port, enum tcpci_msg_type type)
+{
+	return pd_get_rev(port, type) == PD_REV30;
+}
+
+/*
+ * ############################################################################
+ *
+ * (Charge Through) Vconn Powered Device functions
+ *
+ * ############################################################################
+ */
+bool is_vpd_ct_supported(int port)
+{
+	const struct pd_discovery *disc =
+		pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
+	union vpd_vdo vpd = disc->identity.product_t1.vpd;
+
+	return vpd.ct_support;
+}
+
+/*
+ * ############################################################################
+ *
+ * Cable communication functions
+ *
+ * ############################################################################
+ */
+enum idh_ptype get_usb_pd_cable_type(int port)
+{
+	const struct pd_discovery *disc =
+		pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
+
+	return disc->identity.idh.product_type;
+}
+
+bool is_cable_speed_gen2_capable(int port)
+{
+	const struct pd_discovery *disc =
+		pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
+
+	switch (pd_get_rev(port, TCPCI_MSG_SOP_PRIME)) {
+	case PD_REV20:
+		return disc->identity.product_t1.p_rev20.ss ==
+		       USB_R20_SS_U31_GEN1_GEN2;
+
+	case PD_REV30:
+		return disc->identity.product_t1.p_rev30.ss ==
+			       USB_R30_SS_U32_U40_GEN2 ||
+		       disc->identity.product_t1.p_rev30.ss ==
+			       USB_R30_SS_U40_GEN3;
+	default:
+		return false;
+	}
+}
+
+bool is_active_cable_element_retimer(int port)
+{
+	const struct pd_discovery *disc =
+		pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
+
+	/* Ref: USB PD Spec 2.0 Table 6-29 Active Cable VDO
+	 * Revision 2 Active cables do not have Active element support.
+	 */
+	return is_pd_rev3(port, TCPCI_MSG_SOP_PRIME) &&
+	       disc->identity.idh.product_type == IDH_PTYPE_ACABLE &&
+	       disc->identity.product_t2.a2_rev30.active_elem == ACTIVE_RETIMER;
+}
diff --git a/common/usb_pd_dual_role.c b/common/usb_pd_dual_role.c
index aad8d56768..a15b764cd2 100644
--- a/common/usb_pd_dual_role.c
+++ b/common/usb_pd_dual_role.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -7,11 +7,17 @@
 
 #include "charge_manager.h"
 #include "charge_state.h"
+#include "dps.h"
 #include "system.h"
 #include "usb_common.h"
 #include "usb_pd.h"
 #include "util.h"
 
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+/* The macro is used to prevent a DBZ exception while decoding PDOs. */
+#define PROCESS_ZERO_DIVISOR(x) ((x) == 0 ? 1 : (x))
+
 #if defined(PD_MAX_VOLTAGE_MV) && defined(PD_OPERATING_POWER_MW)
 /*
  * As a sink, this is the max voltage (in millivolts) we can request
@@ -19,6 +25,7 @@
  */
 static unsigned int max_request_mv = PD_MAX_VOLTAGE_MV;
 
+/* TODO(b:169532537): deprecate CONFIG_USB_PD_PREFER_MV */
 STATIC_IF_NOT(CONFIG_USB_PD_PREFER_MV)
 struct pd_pref_config_t __maybe_unused pd_pref_config;
 
@@ -32,13 +39,35 @@ unsigned int pd_get_max_voltage(void)
 	return max_request_mv;
 }
 
+/**
+ * Return true if port is capable of communication over USB data lines.
+ *
+ * @param port USB-C port number
+ */
+static bool pd_get_usb_comm_capable(int port)
+{
+	uint32_t fixed_pdo;
+
+	/* the fixed PDO is always the first entry */
+	if (pd_get_power_role(port) == PD_ROLE_SINK) {
+		fixed_pdo = pd_snk_pdo[0];
+	} else {
+		const uint32_t *pdo;
+
+		pd_get_source_pdo(&pdo, port);
+		fixed_pdo = pdo[0];
+	}
+
+	return !!(fixed_pdo & PDO_FIXED_COMM_CAP);
+}
+
 /*
  * Zinger implements a board specific usb policy that does not define
  * PD_MAX_VOLTAGE_MV and PD_OPERATING_POWER_MW. And in turn, does not
  * use the following functions.
  */
-int pd_find_pdo_index(uint32_t src_cap_cnt, const uint32_t * const src_caps,
-					int max_mv, uint32_t *selected_pdo)
+int pd_find_pdo_index(uint32_t src_cap_cnt, const uint32_t *const src_caps,
+		      int max_mv, uint32_t *selected_pdo)
 {
 	int i, uw, mv;
 	int ret = 0;
@@ -59,14 +88,23 @@ int pd_find_pdo_index(uint32_t src_cap_cnt, const uint32_t * const src_caps,
 
 	/* Get max power that is under our max voltage input */
 	for (i = 0; i < src_cap_cnt; i++) {
+		if (IS_ENABLED(CONFIG_USB_PD_ONLY_FIXED_PDOS) &&
+		    (src_caps[i] & PDO_TYPE_MASK) != PDO_TYPE_FIXED)
+			continue;
 		/* its an unsupported Augmented PDO (PD3.0) */
 		if ((src_caps[i] & PDO_TYPE_MASK) == PDO_TYPE_AUGMENTED)
 			continue;
 
-		mv = ((src_caps[i] >> 10) & 0x3FF) * 50;
+		mv = PDO_FIXED_GET_VOLT(src_caps[i]);
 		/* Skip invalid voltage */
 		if (!mv)
 			continue;
+		/*
+		 * It's illegal to have EPR PDO in 1...7.
+		 * TODO: This is supposed to be a hard reset (8.3.3.3.8)
+		 */
+		if (i < 7 && mv > PD_MAX_SPR_VOLTAGE)
+			continue;
 		/* Skip any voltage not supported by this board */
 		if (!pd_is_valid_input_voltage(mv))
 			continue;
@@ -74,7 +112,7 @@ int pd_find_pdo_index(uint32_t src_cap_cnt, const uint32_t * const src_caps,
 		if ((src_caps[i] & PDO_TYPE_MASK) == PDO_TYPE_BATTERY) {
 			uw = 250000 * (src_caps[i] & 0x3FF);
 		} else {
-			int ma = (src_caps[i] & 0x3FF) * 10;
+			int ma = PDO_FIXED_GET_CURR(src_caps[i]);
 
 			ma = MIN(ma, PD_MAX_CURRENT_MA);
 			uw = ma * mv;
@@ -125,10 +163,10 @@ int pd_find_pdo_index(uint32_t src_cap_cnt, const uint32_t * const src_caps,
 						 mv < cur_mv)
 						prefer_cur = 1;
 				}
-			/*
-			 * pick the largest power if we don't see one staisfy
-			 * desired power
-			 */
+				/*
+				 * pick the largest power if we don't see one
+				 * staisfy desired power
+				 */
 			} else if (cur_uw == 0 || uw > cur_uw) {
 				prefer_cur = 1;
 			}
@@ -152,30 +190,48 @@ int pd_find_pdo_index(uint32_t src_cap_cnt, const uint32_t * const src_caps,
 	return ret;
 }
 
-void pd_extract_pdo_power(uint32_t pdo, uint32_t *ma, uint32_t *mv)
+void pd_extract_pdo_power(uint32_t pdo, uint32_t *ma, uint32_t *max_mv,
+			  uint32_t *min_mv)
 {
-	int max_ma, uw;
-
-	*mv = ((pdo >> 10) & 0x3FF) * 50;
+	int max_ma, mw;
+
+	if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_FIXED) {
+		*max_mv = PDO_FIXED_VOLTAGE(pdo);
+		*min_mv = *max_mv;
+	} else if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_AUGMENTED) {
+		*max_mv = PDO_AUG_MAX_VOLTAGE(pdo);
+		*min_mv = PDO_AUG_MIN_VOLTAGE(pdo);
+	} else if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_VARIABLE) {
+		*max_mv = PDO_VAR_MAX_VOLTAGE(pdo);
+		*min_mv = PDO_VAR_MIN_VOLTAGE(pdo);
+	} else {
+		*max_mv = PDO_BATT_MAX_VOLTAGE(pdo);
+		*min_mv = PDO_BATT_MIN_VOLTAGE(pdo);
+	}
 
-	if (*mv == 0) {
+	if (*max_mv == 0) {
 		*ma = 0;
+		*min_mv = 0;
 		return;
 	}
 
-	if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_BATTERY) {
-		uw = 250000 * (pdo & 0x3FF);
-		max_ma = 1000 * MIN(1000 * uw, PD_MAX_POWER_MW) / *mv;
+	if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_FIXED) {
+		max_ma = PDO_FIXED_CURRENT(pdo);
+	} else if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_AUGMENTED) {
+		max_ma = PDO_AUG_MAX_CURRENT(pdo);
+	} else if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_VARIABLE) {
+		max_ma = PDO_VAR_MAX_CURRENT(pdo);
 	} else {
-		max_ma = 10 * (pdo & 0x3FF);
-		max_ma = MIN(max_ma, PD_MAX_POWER_MW * 1000 / *mv);
+		mw = PDO_BATT_MAX_POWER(pdo);
+		max_ma = 1000 * mw / PROCESS_ZERO_DIVISOR(*min_mv);
 	}
-
+	max_ma = MIN(max_ma,
+		     PD_MAX_POWER_MW * 1000 / PROCESS_ZERO_DIVISOR(*min_mv));
 	*ma = MIN(max_ma, PD_MAX_CURRENT_MA);
 }
 
 void pd_build_request(int32_t vpd_vdo, uint32_t *rdo, uint32_t *ma,
-			uint32_t *mv, int port)
+		      uint32_t *mv, int port)
 {
 	uint32_t pdo;
 	int pdo_index, flags = 0;
@@ -186,10 +242,11 @@ void pd_build_request(int32_t vpd_vdo, uint32_t *rdo, uint32_t *ma,
 	int vpd_vbus_dcr;
 	int vpd_gnd_dcr;
 	uint32_t src_cap_cnt = pd_get_src_cap_cnt(port);
-	const uint32_t * const src_caps = pd_get_src_caps(port);
+	const uint32_t *const src_caps = pd_get_src_caps(port);
 	int charging_allowed;
 	int max_request_allowed;
 	uint32_t max_request_mv = pd_get_max_voltage();
+	uint32_t unused;
 
 	/*
 	 * If this port is the current charge port, or if there isn't an active
@@ -213,6 +270,9 @@ void pd_build_request(int32_t vpd_vdo, uint32_t *rdo, uint32_t *ma,
 	else
 		max_request_allowed = 1;
 
+	if (IS_ENABLED(CONFIG_USB_PD_DPS) && dps_is_enabled())
+		max_request_mv = MIN(max_request_mv, dps_get_dynamic_voltage());
+
 	/*
 	 * If currently charging on a different port, or we are not allowed to
 	 * request the max voltage, then select vSafe5V
@@ -220,14 +280,14 @@ void pd_build_request(int32_t vpd_vdo, uint32_t *rdo, uint32_t *ma,
 	if (charging_allowed && max_request_allowed) {
 		/* find pdo index for max voltage we can request */
 		pdo_index = pd_find_pdo_index(src_cap_cnt, src_caps,
-						max_request_mv, &pdo);
+					      max_request_mv, &pdo);
 	} else {
 		/* src cap 0 should be vSafe5V */
 		pdo_index = 0;
 		pdo = src_caps[0];
 	}
 
-	pd_extract_pdo_power(pdo, ma, mv);
+	pd_extract_pdo_power(pdo, ma, mv, &unused);
 
 	/*
 	 * Adjust VBUS current if CTVPD device was detected.
@@ -263,29 +323,33 @@ void pd_build_request(int32_t vpd_vdo, uint32_t *rdo, uint32_t *ma,
 	if (uw < (1000 * PD_OPERATING_POWER_MW))
 		flags |= RDO_CAP_MISMATCH;
 
+	/* b:271612382S has more details. */
+	if (IS_ENABLED(CONFIG_USB_PD_EPR))
+		flags |= RDO_EPR_MODE_CAPABLE;
+
 #ifdef CONFIG_USB_PD_GIVE_BACK
-		/* Tell source we are give back capable. */
-		flags |= RDO_GIVE_BACK;
+	/* Tell source we are give back capable. */
+	flags |= RDO_GIVE_BACK;
 
-		/*
-		 * BATTERY PDO: Inform the source that the sink will reduce
-		 * power to this minimum level on receipt of a GotoMin Request.
-		 */
-		max_or_min_mw = PD_MIN_POWER_MW;
+	/*
+	 * BATTERY PDO: Inform the source that the sink will reduce
+	 * power to this minimum level on receipt of a GotoMin Request.
+	 */
+	max_or_min_mw = PD_MIN_POWER_MW;
 
-		/*
-		 * FIXED or VARIABLE PDO: Inform the source that the sink will
-		 * reduce current to this minimum level on receipt of a GotoMin
-		 * Request.
-		 */
-		max_or_min_ma = PD_MIN_CURRENT_MA;
+	/*
+	 * FIXED or VARIABLE PDO: Inform the source that the sink will
+	 * reduce current to this minimum level on receipt of a GotoMin
+	 * Request.
+	 */
+	max_or_min_ma = PD_MIN_CURRENT_MA;
 #else
-		/*
-		 * Can't give back, so set maximum current and power to
-		 * operating level.
-		 */
-		max_or_min_ma = *ma;
-		max_or_min_mw = uw / 1000;
+	/*
+	 * Can't give back, so set maximum current and power to
+	 * operating level.
+	 */
+	max_or_min_ma = *ma;
+	max_or_min_mw = uw / 1000;
 #endif
 
 	if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_BATTERY) {
@@ -301,12 +365,12 @@ void pd_build_request(int32_t vpd_vdo, uint32_t *rdo, uint32_t *ma,
 	 * 6.4.2.4 USB Communications Capable
 	 * 6.4.2.5 No USB Suspend
 	 *
-	 * If the port partner is capable of USB communication set the
-	 * USB Communications Capable flag.
+	 * If the port is capable of USB communication, set the USB
+	 * Communications Capable flag.
 	 * If the port partner is sink device do not suspend USB as the
 	 * power can be used for charging.
 	 */
-	if (pd_get_partner_usb_comm_capable(port)) {
+	if (pd_get_usb_comm_capable(port)) {
 		*rdo |= RDO_COMM_CAP;
 		if (pd_get_power_role(port) == PD_ROLE_SINK)
 			*rdo |= RDO_NO_SUSPEND;
@@ -318,31 +382,48 @@ void pd_process_source_cap(int port, int cnt, uint32_t *src_caps)
 	pd_set_src_caps(port, cnt, src_caps);
 
 	if (IS_ENABLED(CONFIG_CHARGE_MANAGER)) {
-		uint32_t ma, mv, pdo;
+		uint32_t ma, mv, pdo, unused;
+		uint32_t max_mv = pd_get_max_voltage();
+
+		if (IS_ENABLED(CONFIG_USB_PD_DPS) && dps_is_enabled())
+			max_mv = MIN(max_mv, dps_get_dynamic_voltage());
 
 		/* Get max power info that we could request */
 		pd_find_pdo_index(pd_get_src_cap_cnt(port),
-					pd_get_src_caps(port),
-					PD_MAX_VOLTAGE_MV, &pdo);
-		pd_extract_pdo_power(pdo, &ma, &mv);
+				  pd_get_src_caps(port), max_mv, &pdo);
+		pd_extract_pdo_power(pdo, &ma, &mv, &unused);
 
-		/* Set max. limit, but apply 500mA ceiling */
-		charge_manager_set_ceil(port, CEIL_REQUESTOR_PD, PD_MIN_MA);
+		/* Set max. limit, but 2.5 W ceiling will be applied later. */
 		pd_set_input_current_limit(port, ma, mv);
 	}
 }
 #endif /* defined(PD_MAX_VOLTAGE_MV) && defined(PD_OPERATING_POWER_MW) */
 
-int pd_charge_from_device(uint16_t vid, uint16_t pid)
+bool pd_is_battery_capable(void)
 {
-	/* TODO: rewrite into table if we get more of these */
+	bool capable;
+
+	/* Battery is present and at some minimum percentage. */
+	capable = (usb_get_battery_soc() >= CONFIG_USB_PD_TRY_SRC_MIN_BATT_SOC);
+
+#ifdef CONFIG_BATTERY_REVIVE_DISCONNECT
 	/*
-	 * Allow the Apple charge-through accessory since it doesn't set
-	 * unconstrained bit, but we still need to charge from it when
-	 * we are a sink.
+	 * Not capable if the battery is in the disconnect state. The discharge
+	 * FET may not be enabled and so attempting being a SRC may cut off
+	 * our only power source at the time.
 	 */
-	return (vid == USB_VID_APPLE &&
-		(pid == USB_PID1_APPLE || pid == USB_PID2_APPLE));
+	capable &= (battery_get_disconnect_state() == BATTERY_NOT_DISCONNECTED);
+#elif defined(CONFIG_BATTERY_PRESENT_CUSTOM) || \
+	defined(CONFIG_BATTERY_PRESENT_GPIO)
+	/*
+	 * When battery is cutoff in ship mode it may not be reliable to
+	 * check if battery is present with its state of charge.
+	 * Also check if battery is initialized and ready to provide power.
+	 */
+	capable &= (battery_is_present() == BP_YES);
+#endif /* CONFIG_BATTERY_PRESENT_[CUSTOM|GPIO] */
+
+	return capable;
 }
 
 #ifdef CONFIG_USB_PD_TRY_SRC
@@ -356,37 +437,18 @@ bool pd_is_try_source_capable(void)
 		try_src |= (pd_get_dual_role(i) == PD_DRP_TOGGLE_ON);
 
 	/*
-	 * Enable try source when dual-role toggling AND battery is present
-	 * and at some minimum percentage.
-	 */
-	new_try_src = (try_src &&
-		usb_get_battery_soc() >= CONFIG_USB_PD_TRY_SRC_MIN_BATT_SOC);
-
-#ifdef CONFIG_BATTERY_REVIVE_DISCONNECT
-	/*
-	 * Don't attempt Try.Src if the battery is in the disconnect state.  The
-	 * discharge FET may not be enabled and so attempting Try.Src may cut
-	 * off our only power source at the time.
+	 * Enable try source when dual-role toggling AND battery is capable
+	 * of powering the whole system.
 	 */
-	new_try_src &= (battery_get_disconnect_state() ==
-			      BATTERY_NOT_DISCONNECTED);
-#elif defined(CONFIG_BATTERY_PRESENT_CUSTOM) ||	\
-	defined(CONFIG_BATTERY_PRESENT_GPIO)
-	/*
-	 * When battery is cutoff in ship mode it may not be reliable to
-	 * check if battery is present with its state of charge.
-	 * Also check if battery is initialized and ready to provide power.
-	 */
-	new_try_src &= (battery_is_present() == BP_YES);
-#endif /* CONFIG_BATTERY_PRESENT_[CUSTOM|GPIO] */
+	new_try_src = (try_src && pd_is_battery_capable());
 
 #if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
 	/*
 	 * If a dedicated supplier is present, power is not a concern and
-	 * therefore always allow Try.Src.
+	 * therefore allow Try.Src if we're toggling.
 	 */
-	new_try_src |= (charge_manager_get_supplier() ==
-			     CHARGE_SUPPLIER_DEDICATED);
+	new_try_src = try_src && (charge_manager_get_supplier() ==
+				  CHARGE_SUPPLIER_DEDICATED);
 #endif /* CONFIG_DEDICATED_CHARGE_PORT_COUNT */
 
 	return new_try_src;
diff --git a/common/usb_pd_flags.c b/common/usb_pd_flags.c
new file mode 100644
index 0000000000..fdd7a6f2af
--- /dev/null
+++ b/common/usb_pd_flags.c
@@ -0,0 +1,66 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Contains USB PD accessors definition
+ */
+
+#include "common.h"
+#include "usb_pd_flags.h"
+
+static union usb_pd_runtime_flags usb_pd_flags;
+BUILD_ASSERT(sizeof(usb_pd_flags) == sizeof(uint32_t));
+
+enum usb_pd_vbus_detect get_usb_pd_vbus_detect(void)
+{
+	if (IS_ENABLED(CONFIG_USB_PD_RUNTIME_FLAGS))
+		return (enum usb_pd_vbus_detect)usb_pd_flags.vbus_detect;
+	else if (IS_ENABLED(CONFIG_USB_PD_VBUS_DETECT_TCPC))
+		return (enum usb_pd_vbus_detect)USB_PD_VBUS_DETECT_TCPC;
+	else if (IS_ENABLED(CONFIG_USD_PD_VBUS_DETECT_GPIO))
+		return (enum usb_pd_vbus_detect)USB_PD_VBUS_DETECT_GPIO;
+	else if (IS_ENABLED(CONFIG_USB_PD_VBUS_DETECT_PPC))
+		return (enum usb_pd_vbus_detect)USB_PD_VBUS_DETECT_PPC;
+	else if (IS_ENABLED(CONFIG_USB_PD_VBUS_DETECT_CHARGER))
+		return (enum usb_pd_vbus_detect)USB_PD_VBUS_DETECT_CHARGER;
+	else if (IS_ENABLED(CONFIG_USB_PD_VBUS_DETECT_NONE))
+		return (enum usb_pd_vbus_detect)USB_PD_VBUS_DETECT_NONE;
+	else
+		return (enum usb_pd_vbus_detect)USB_PD_VBUS_DETECT_UNKNOWN;
+}
+
+enum usb_pd_discharge get_usb_pd_discharge(void)
+{
+	if (IS_ENABLED(CONFIG_USB_PD_RUNTIME_FLAGS))
+		return (enum usb_pd_discharge)usb_pd_flags.discharge;
+	else if (IS_ENABLED(CONFIG_USB_PD_DISCHARGE_TCPC))
+		return (enum usb_pd_discharge)USB_PD_DISCHARGE_TCPC;
+	else if (IS_ENABLED(CONFIG_USD_PD_DISCHARGE_GPIO))
+		return (enum usb_pd_discharge)USB_PD_DISCHARGE_GPIO;
+	else if (IS_ENABLED(CONFIG_USB_PD_DISCHARGE_PPC))
+		return (enum usb_pd_discharge)USB_PD_DISCHARGE_PPC;
+	else
+		return (enum usb_pd_discharge)USB_PD_DISCHARGE_NONE;
+}
+
+enum usb_pd_charger_otg get_usb_pd_charger_otg(void)
+{
+	return usb_pd_flags.charger_otg;
+}
+
+void set_usb_pd_vbus_detect(enum usb_pd_vbus_detect vbus_detect)
+{
+	usb_pd_flags.vbus_detect = vbus_detect;
+}
+
+void set_usb_pd_discharge(enum usb_pd_discharge discharge)
+{
+	usb_pd_flags.discharge = discharge;
+}
+
+void set_usb_pd_charger_otg(enum usb_pd_charger_otg charger_otg)
+{
+	usb_pd_flags.charger_otg = charger_otg;
+}
diff --git a/common/usb_pd_host_cmd.c b/common/usb_pd_host_cmd.c
index 8bdc50a0e3..d051a8f2e7 100644
--- a/common/usb_pd_host_cmd.c
+++ b/common/usb_pd_host_cmd.c
@@ -1,36 +1,27 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Host commands for USB-PD module.
  */
 
-#include <string.h>
-
 #include "atomic.h"
 #include "battery.h"
 #include "charge_manager.h"
 #include "console.h"
 #include "ec_commands.h"
 #include "host_command.h"
-#include "tcpm.h"
+#include "mkbp_event.h"
+#include "tcpm/tcpm.h"
+#include "usb_common.h"
 #include "usb_mux.h"
-#include "usb_pd_tcpm.h"
 #include "usb_pd.h"
+#include "usb_pd_tcpm.h"
 
+#include <string.h>
 #ifdef CONFIG_COMMON_RUNTIME
-/*
- * If we are trying to upgrade the TCPC port that is supplying power, then we
- * need to ensure that the battery has enough charge for the upgrade. 100mAh
- * is about 5% of most batteries, and it should be enough charge to get us
- * through the EC jump to RW and PD upgrade.
- */
-#define MIN_BATTERY_FOR_TCPC_UPGRADE_MAH 100 /* mAH */
-
-struct ec_params_usb_pd_rw_hash_entry rw_hash_table[RW_HASH_ENTRIES];
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 #else /* CONFIG_COMMON_RUNTIME */
 #define CPRINTF(format, args...)
 #define CPRINTS(format, args...)
@@ -47,9 +38,7 @@ static enum ec_status hc_pd_ports(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_USB_PD_PORTS,
-		     hc_pd_ports,
-		     EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_USB_PD_PORTS, hc_pd_ports, EC_VER_MASK(0));
 
 #ifdef CONFIG_HOSTCMD_RWHASHPD
 static enum ec_status
@@ -80,8 +69,7 @@ hc_remote_rw_hash_entry(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_USB_PD_RW_HASH_ENTRY,
-		     hc_remote_rw_hash_entry,
+DECLARE_HOST_COMMAND(EC_CMD_USB_PD_RW_HASH_ENTRY, hc_remote_rw_hash_entry,
 		     EC_VER_MASK(0));
 #endif /* CONFIG_HOSTCMD_RWHASHPD */
 
@@ -102,145 +90,55 @@ static enum ec_status hc_remote_pd_chip_info(struct host_cmd_handler_args *args)
 	 * same layout for v0 data. (v1 just appends data)
 	 */
 	args->response_size =
-		args->version ? sizeof(struct ec_response_pd_chip_info_v1)
-			      : sizeof(struct ec_response_pd_chip_info);
+		args->version ? sizeof(struct ec_response_pd_chip_info_v1) :
+				sizeof(struct ec_response_pd_chip_info);
 
 	memcpy(args->response, &info, args->response_size);
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_PD_CHIP_INFO,
-		     hc_remote_pd_chip_info,
+DECLARE_HOST_COMMAND(EC_CMD_PD_CHIP_INFO, hc_remote_pd_chip_info,
 		     EC_VER_MASK(0) | EC_VER_MASK(1));
 #endif /* CONFIG_EC_CMD_PD_CHIP_INFO && !CONFIG_USB_PD_TCPC */
 
 #ifdef CONFIG_USB_PD_ALT_MODE_DFP
-static enum ec_status hc_remote_pd_set_amode(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_usb_pd_set_mode_request *p = args->params;
-
-	if ((p->port >= board_get_usb_pd_port_count()) ||
-	    (!p->svid) || (!p->opos))
-		return EC_RES_INVALID_PARAM;
-
-	switch (p->cmd) {
-	case PD_EXIT_MODE:
-		if (pd_dfp_exit_mode(p->port, TCPC_TX_SOP, p->svid, p->opos))
-			pd_send_vdm(p->port, p->svid,
-				    CMD_EXIT_MODE | VDO_OPOS(p->opos), NULL, 0);
-		else {
-			CPRINTF("Failed exit mode\n");
-			return EC_RES_ERROR;
-		}
-		break;
-	case PD_ENTER_MODE:
-		if (pd_dfp_enter_mode(p->port, TCPC_TX_SOP, p->svid, p->opos))
-			pd_send_vdm(p->port, p->svid, CMD_ENTER_MODE |
-				    VDO_OPOS(p->opos), NULL, 0);
-		break;
-	default:
-		return EC_RES_INVALID_PARAM;
-	}
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_USB_PD_SET_AMODE,
-		     hc_remote_pd_set_amode,
-		     EC_VER_MASK(0));
-
 static enum ec_status hc_remote_pd_discovery(struct host_cmd_handler_args *args)
 {
-	const uint8_t *port = args->params;
+	const struct ec_params_usb_pd_info_request *p = args->params;
 	struct ec_params_usb_pd_discovery_entry *r = args->response;
 
-	if (*port >= board_get_usb_pd_port_count())
+	if (p->port >= board_get_usb_pd_port_count())
 		return EC_RES_INVALID_PARAM;
 
-	r->vid = pd_get_identity_vid(*port);
-	r->ptype = pd_get_product_type(*port);
+	r->vid = pd_get_identity_vid(p->port);
+	r->ptype = pd_get_product_type(p->port);
 
 	/* pid only included if vid is assigned */
 	if (r->vid)
-		r->pid = pd_get_identity_pid(*port);
-
-	args->response_size = sizeof(*r);
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_USB_PD_DISCOVERY,
-		     hc_remote_pd_discovery,
-		     EC_VER_MASK(0));
-
-static enum ec_status hc_remote_pd_get_amode(struct host_cmd_handler_args *args)
-{
-	struct svdm_amode_data *modep;
-	const struct ec_params_usb_pd_get_mode_request *p = args->params;
-	struct ec_params_usb_pd_get_mode_response *r = args->response;
-
-	if (p->port >= board_get_usb_pd_port_count())
-		return EC_RES_INVALID_PARAM;
-
-	/* no more to send */
-	/* TODO(b/148528713): Use TCPMv2's separate storage for SOP'. */
-	if (p->svid_idx >= pd_get_svid_count(p->port, TCPC_TX_SOP)) {
-		r->svid = 0;
-		args->response_size = sizeof(r->svid);
-		return EC_RES_SUCCESS;
-	}
-
-	r->svid = pd_get_svid(p->port, p->svid_idx, TCPC_TX_SOP);
-	r->opos = 0;
-	memcpy(r->vdo, pd_get_mode_vdo(p->port, p->svid_idx, TCPC_TX_SOP),
-		sizeof(uint32_t) * PDO_MODES);
-	modep = pd_get_amode_data(p->port, TCPC_TX_SOP, r->svid);
-
-	if (modep)
-		r->opos = pd_alt_mode(p->port, TCPC_TX_SOP, r->svid);
+		r->pid = pd_get_identity_pid(p->port);
 
 	args->response_size = sizeof(*r);
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_USB_PD_GET_AMODE,
-		     hc_remote_pd_get_amode,
+DECLARE_HOST_COMMAND(EC_CMD_USB_PD_DISCOVERY, hc_remote_pd_discovery,
 		     EC_VER_MASK(0));
 
 #endif /* CONFIG_USB_PD_ALT_MODE_DFP */
 
 #ifdef CONFIG_COMMON_RUNTIME
-static enum ec_status hc_remote_pd_dev_info(struct host_cmd_handler_args *args)
-{
-	const uint8_t *port = args->params;
-	struct ec_params_usb_pd_rw_hash_entry *r = args->response;
-	uint16_t dev_id;
-	uint32_t current_image;
-
-	if (*port >= board_get_usb_pd_port_count())
-		return EC_RES_INVALID_PARAM;
-
-	pd_dev_get_rw_hash(*port, &dev_id, r->dev_rw_hash, &current_image);
-
-	r->dev_id = dev_id;
-	r->current_image = current_image;
-
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_USB_PD_DEV_INFO,
-		     hc_remote_pd_dev_info,
-		     EC_VER_MASK(0));
-
 static const enum pd_dual_role_states dual_role_map[USB_PD_CTRL_ROLE_COUNT] = {
-	[USB_PD_CTRL_ROLE_TOGGLE_ON]    = PD_DRP_TOGGLE_ON,
-	[USB_PD_CTRL_ROLE_TOGGLE_OFF]   = PD_DRP_TOGGLE_OFF,
-	[USB_PD_CTRL_ROLE_FORCE_SINK]   = PD_DRP_FORCE_SINK,
+	[USB_PD_CTRL_ROLE_TOGGLE_ON] = PD_DRP_TOGGLE_ON,
+	[USB_PD_CTRL_ROLE_TOGGLE_OFF] = PD_DRP_TOGGLE_OFF,
+	[USB_PD_CTRL_ROLE_FORCE_SINK] = PD_DRP_FORCE_SINK,
 	[USB_PD_CTRL_ROLE_FORCE_SOURCE] = PD_DRP_FORCE_SOURCE,
-	[USB_PD_CTRL_ROLE_FREEZE]       = PD_DRP_FREEZE,
+	[USB_PD_CTRL_ROLE_FREEZE] = PD_DRP_FREEZE,
 };
 
 static const mux_state_t typec_mux_map[USB_PD_CTRL_MUX_COUNT] = {
 	[USB_PD_CTRL_MUX_NONE] = USB_PD_MUX_NONE,
-	[USB_PD_CTRL_MUX_USB]  = USB_PD_MUX_USB_ENABLED,
+	[USB_PD_CTRL_MUX_USB] = USB_PD_MUX_USB_ENABLED,
 	[USB_PD_CTRL_MUX_AUTO] = USB_PD_MUX_DP_ENABLED,
-	[USB_PD_CTRL_MUX_DP]   = USB_PD_MUX_DP_ENABLED,
+	[USB_PD_CTRL_MUX_DP] = USB_PD_MUX_DP_ENABLED,
 	[USB_PD_CTRL_MUX_DOCK] = USB_PD_MUX_DOCK,
 };
 
@@ -250,49 +148,66 @@ static const mux_state_t typec_mux_map[USB_PD_CTRL_MUX_COUNT] = {
  * Bit 1: Optical/Non-optical cable
  * Bit 2: Legacy Thunderbolt adapter
  * Bit 3: Active Link Uni-Direction/Bi-Direction
+ * Bit 4: Retimer/Rediriver cable
  */
 static uint8_t get_pd_control_flags(int port)
 {
 	union tbt_mode_resp_cable cable_resp;
 	union tbt_mode_resp_device device_resp;
+	uint8_t control_flags = 0;
 
-	if (!IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP))
+	if (!IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP) ||
+	    !IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE))
 		return 0;
 
-	cable_resp.raw_value = pd_get_tbt_mode_vdo(port, TCPC_TX_SOP_PRIME);
-	device_resp.raw_value = pd_get_tbt_mode_vdo(port, TCPC_TX_SOP);
+	cable_resp.raw_value = pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME);
+	device_resp.raw_value = pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP);
 
 	/*
 	 * Ref: USB Type-C Cable and Connector Specification
 	 * Table F-11 TBT3 Cable Discover Mode VDO Responses
 	 * For Passive cables, Active Cable Plug link training is set to 0
 	 */
-	return (cable_resp.lsrx_comm == UNIDIR_LSRX_COMM ?
-			USB_PD_CTRL_ACTIVE_LINK_UNIDIR : 0) |
-		(device_resp.tbt_adapter == TBT_ADAPTER_TBT2_LEGACY ?
-			USB_PD_CTRL_TBT_LEGACY_ADAPTER : 0) |
-		(cable_resp.tbt_cable == TBT_CABLE_OPTICAL ?
-			USB_PD_CTRL_OPTICAL_CABLE : 0) |
-		(cable_resp.retimer_type == USB_RETIMER ?
-			USB_PD_CTRL_ACTIVE_CABLE : 0);
+	control_flags |= (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE ||
+			  cable_resp.tbt_active_passive == TBT_CABLE_ACTIVE) ?
+				 USB_PD_CTRL_ACTIVE_CABLE :
+				 0;
+	control_flags |= cable_resp.tbt_cable == TBT_CABLE_OPTICAL ?
+				 USB_PD_CTRL_OPTICAL_CABLE :
+				 0;
+	control_flags |= device_resp.tbt_adapter == TBT_ADAPTER_TBT2_LEGACY ?
+				 USB_PD_CTRL_TBT_LEGACY_ADAPTER :
+				 0;
+	control_flags |= cable_resp.lsrx_comm == UNIDIR_LSRX_COMM ?
+				 USB_PD_CTRL_ACTIVE_LINK_UNIDIR :
+				 0;
+	control_flags |= cable_resp.retimer_type == USB_RETIMER ?
+				 USB_PD_CTRL_RETIMER_CABLE :
+				 0;
+
+	return control_flags;
 }
 
 static uint8_t pd_get_role_flags(int port)
 {
 	return (pd_get_power_role(port) == PD_ROLE_SOURCE ?
-			PD_CTRL_RESP_ROLE_POWER : 0) |
-		(pd_get_data_role(port) == PD_ROLE_DFP ?
-			PD_CTRL_RESP_ROLE_DATA : 0) |
-		(pd_get_vconn_state(port) ?
-			PD_CTRL_RESP_ROLE_VCONN : 0) |
-		(pd_get_partner_dual_role_power(port) ?
-			PD_CTRL_RESP_ROLE_DR_POWER : 0) |
-		(pd_get_partner_data_swap_capable(port) ?
-			PD_CTRL_RESP_ROLE_DR_DATA : 0) |
-		(pd_get_partner_usb_comm_capable(port) ?
-			PD_CTRL_RESP_ROLE_USB_COMM : 0) |
-		(pd_get_partner_unconstr_power(port) ?
-			PD_CTRL_RESP_ROLE_UNCONSTRAINED : 0);
+			PD_CTRL_RESP_ROLE_POWER :
+			0) |
+	       (pd_get_data_role(port) == PD_ROLE_DFP ? PD_CTRL_RESP_ROLE_DATA :
+							0) |
+	       (pd_get_vconn_state(port) ? PD_CTRL_RESP_ROLE_VCONN : 0) |
+	       (pd_get_partner_dual_role_power(port) ?
+			PD_CTRL_RESP_ROLE_DR_POWER :
+			0) |
+	       (pd_get_partner_data_swap_capable(port) ?
+			PD_CTRL_RESP_ROLE_DR_DATA :
+			0) |
+	       (pd_get_partner_usb_comm_capable(port) ?
+			PD_CTRL_RESP_ROLE_USB_COMM :
+			0) |
+	       (pd_get_partner_unconstr_power(port) ?
+			PD_CTRL_RESP_ROLE_UNCONSTRAINED :
+			0);
 }
 
 static enum ec_status hc_usb_pd_control(struct host_cmd_handler_args *args)
@@ -302,7 +217,6 @@ static enum ec_status hc_usb_pd_control(struct host_cmd_handler_args *args)
 	struct ec_response_usb_pd_control_v1 *r_v1 = args->response;
 	struct ec_response_usb_pd_control *r = args->response;
 	const char *task_state_name;
-	mux_state_t mux_state;
 
 	if (p->port >= board_get_usb_pd_port_count())
 		return EC_RES_INVALID_PARAM;
@@ -319,12 +233,12 @@ static enum ec_status hc_usb_pd_control(struct host_cmd_handler_args *args)
 	}
 
 	if (IS_ENABLED(CONFIG_USBC_SS_MUX) &&
-		p->mux != USB_PD_CTRL_MUX_NO_CHANGE)
+	    p->mux != USB_PD_CTRL_MUX_NO_CHANGE)
 		usb_mux_set(p->port, typec_mux_map[p->mux],
 			    typec_mux_map[p->mux] == USB_PD_MUX_NONE ?
-			    USB_SWITCH_DISCONNECT :
-			    USB_SWITCH_CONNECT,
-			    pd_get_polarity(p->port));
+				    USB_SWITCH_DISCONNECT :
+				    USB_SWITCH_CONNECT,
+			    polarity_rm_dts(pd_get_polarity(p->port)));
 
 	if (p->swap == USB_PD_CTRL_SWAP_DATA) {
 		pd_request_data_swap(p->port);
@@ -332,7 +246,7 @@ static enum ec_status hc_usb_pd_control(struct host_cmd_handler_args *args)
 		if (p->swap == USB_PD_CTRL_SWAP_POWER)
 			pd_request_power_swap(p->port);
 		else if (IS_ENABLED(CONFIG_USBC_VCONN_SWAP) &&
-			p->swap == USB_PD_CTRL_SWAP_VCONN)
+			 p->swap == USB_PD_CTRL_SWAP_VCONN)
 			pd_request_vconn_swap(p->port);
 	}
 
@@ -346,17 +260,19 @@ static enum ec_status hc_usb_pd_control(struct host_cmd_handler_args *args)
 		break;
 	case 1:
 	case 2:
-		r_v2->enabled =
-			(pd_comm_is_enabled(p->port) ?
-				PD_CTRL_RESP_ENABLED_COMMS : 0) |
-			(pd_is_connected(p->port) ?
-				PD_CTRL_RESP_ENABLED_CONNECTED : 0) |
-			(pd_capable(p->port) ?
-				PD_CTRL_RESP_ENABLED_PD_CAPABLE : 0);
+		r_v2->enabled = (pd_comm_is_enabled(p->port) ?
+					 PD_CTRL_RESP_ENABLED_COMMS :
+					 0) |
+				(pd_is_connected(p->port) ?
+					 PD_CTRL_RESP_ENABLED_CONNECTED :
+					 0) |
+				(pd_capable(p->port) ?
+					 PD_CTRL_RESP_ENABLED_PD_CAPABLE :
+					 0);
 		r_v2->role = pd_get_role_flags(p->port);
 		r_v2->polarity = pd_get_polarity(p->port);
 
-		r_v2->cc_state =  pd_get_task_cc_state(p->port);
+		r_v2->cc_state = pd_get_task_cc_state(p->port);
 		task_state_name = pd_get_task_state_name(p->port);
 		if (task_state_name)
 			strzcpy(r_v2->state, task_state_name,
@@ -365,18 +281,12 @@ static enum ec_status hc_usb_pd_control(struct host_cmd_handler_args *args)
 			r_v2->state[0] = '\0';
 
 		r_v2->control_flags = get_pd_control_flags(p->port);
-		if (IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP)) {
-			r_v2->dp_mode = get_dp_pin_mode(p->port);
-			mux_state = usb_mux_get(p->port);
-			if (mux_state & USB_PD_MUX_USB4_ENABLED) {
-				r_v2->cable_speed =
-					get_usb4_cable_speed(p->port);
-			} else if (mux_state & USB_PD_MUX_TBT_COMPAT_ENABLED) {
-				r_v2->cable_speed =
-					get_tbt_cable_speed(p->port);
-				r_v2->cable_gen =
-					get_tbt_rounded_support(p->port);
-			}
+
+		r_v2->dp_mode = get_dp_pin_mode(p->port);
+
+		if (IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE)) {
+			r_v2->cable_speed = get_tbt_cable_speed(p->port);
+			r_v2->cable_gen = get_tbt_rounded_support(p->port);
 		}
 
 		if (args->version == 1)
@@ -390,99 +300,10 @@ static enum ec_status hc_usb_pd_control(struct host_cmd_handler_args *args)
 	}
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_USB_PD_CONTROL,
-		     hc_usb_pd_control,
+DECLARE_HOST_COMMAND(EC_CMD_USB_PD_CONTROL, hc_usb_pd_control,
 		     EC_VER_MASK(0) | EC_VER_MASK(1) | EC_VER_MASK(2));
 #endif /* CONFIG_COMMON_RUNTIME */
 
-#if defined(CONFIG_HOSTCMD_FLASHPD) && defined(CONFIG_USB_PD_TCPMV2)
-static enum ec_status hc_remote_flash(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_usb_pd_fw_update *p = args->params;
-	int port = p->port;
-	int rv = EC_RES_SUCCESS;
-	const uint32_t *data = &(p->size) + 1;
-	int i, size;
-
-	if (port >= board_get_usb_pd_port_count())
-		return EC_RES_INVALID_PARAM;
-
-	if (p->size + sizeof(*p) > args->params_size)
-		return EC_RES_INVALID_PARAM;
-
-#if defined(CONFIG_CHARGE_MANAGER) && defined(CONFIG_BATTERY) && \
-	(defined(CONFIG_BATTERY_PRESENT_CUSTOM) ||   \
-	 defined(CONFIG_BATTERY_PRESENT_GPIO))
-	/*
-	 * Do not allow PD firmware update if no battery and this port
-	 * is sinking power, because we will lose power.
-	 */
-	if (battery_is_present() != BP_YES &&
-			charge_manager_get_active_charge_port() == port)
-		return EC_RES_UNAVAILABLE;
-#endif
-
-	switch (p->cmd) {
-	case USB_PD_FW_REBOOT:
-		pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_REBOOT, NULL, 0);
-		/*
-		 * Return immediately to free pending i2c bus.  Host needs to
-		 * manage this delay.
-		 */
-		return EC_RES_SUCCESS;
-
-	case USB_PD_FW_FLASH_ERASE:
-		pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_FLASH_ERASE, NULL, 0);
-		/*
-		 * Return immediately.  Host needs to manage delays here which
-		 * can be as long as 1.2 seconds on 64KB RW flash.
-		 */
-		return EC_RES_SUCCESS;
-
-	case USB_PD_FW_ERASE_SIG:
-		pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_ERASE_SIG, NULL, 0);
-		break;
-
-	case USB_PD_FW_FLASH_WRITE:
-		/* Data size must be a multiple of 4 */
-		if (!p->size || p->size % 4)
-			return EC_RES_INVALID_PARAM;
-
-		size = p->size / 4;
-		for (i = 0; i < size; i += VDO_MAX_SIZE - 1) {
-			pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_FLASH_WRITE,
-				data + i, MIN(size - i, VDO_MAX_SIZE - 1));
-		}
-		return EC_RES_SUCCESS;
-
-	default:
-		return EC_RES_INVALID_PARAM;
-	}
-
-	return rv;
-}
-DECLARE_HOST_COMMAND(EC_CMD_USB_PD_FW_UPDATE,
-			hc_remote_flash,
-			EC_VER_MASK(0));
-#endif /* CONFIG_HOSTCMD_FLASHPD && CONFIG_USB_PD_TCPMV2 */
-
-#ifdef CONFIG_HOSTCMD_EVENTS
-void pd_notify_dp_alt_mode_entry(void)
-{
-	/*
-	 * Note: EC_HOST_EVENT_PD_MCU may be a more appropriate host event to
-	 * send, but we do not send that here because there are other cases
-	 * where we send EC_HOST_EVENT_PD_MCU such as charger insertion or
-	 * removal.  Currently, those do not wake the system up, but
-	 * EC_HOST_EVENT_MODE_CHANGE does.  If we made the system wake up on
-	 * EC_HOST_EVENT_PD_MCU, we would be turning the internal display on on
-	 * every charger insertion/removal, which is not desired.
-	 */
-	CPRINTS("Notifying AP of DP Alt Mode Entry...");
-	host_set_single_event(EC_HOST_EVENT_MODE_CHANGE);
-}
-#endif /* CONFIG_HOSTCMD_EVENTS */
-
 __overridable enum ec_pd_port_location board_get_pd_port_location(int port)
 {
 	(void)port;
@@ -509,8 +330,7 @@ static enum ec_status hc_get_pd_port_caps(struct host_cmd_handler_args *args)
 	else
 		r->pd_try_power_role_cap = EC_PD_TRY_POWER_ROLE_NONE;
 
-	if (IS_ENABLED(CONFIG_USB_VPD) ||
-	    IS_ENABLED(CONFIG_USB_CTVPD))
+	if (IS_ENABLED(CONFIG_USB_VPD) || IS_ENABLED(CONFIG_USB_CTVPD))
 		r->pd_data_role_cap = EC_PD_DATA_ROLE_UFP;
 	else
 		r->pd_data_role_cap = EC_PD_DATA_ROLE_DUAL;
@@ -522,14 +342,22 @@ static enum ec_status hc_get_pd_port_caps(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_GET_PD_PORT_CAPS,
-		     hc_get_pd_port_caps,
+DECLARE_HOST_COMMAND(EC_CMD_GET_PD_PORT_CAPS, hc_get_pd_port_caps,
 		     EC_VER_MASK(0));
 
 #ifdef CONFIG_HOSTCMD_PD_CONTROL
+static int pd_control_disabled[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+/* Only allow port re-enable in unit tests */
+#ifdef TEST_BUILD
+void pd_control_port_enable(int port)
+{
+	pd_control_disabled[port] = 0;
+}
+#endif /* TEST_BUILD */
+
 static enum ec_status pd_control(struct host_cmd_handler_args *args)
 {
-	static int pd_control_disabled[CONFIG_USB_PD_PORT_MAX_COUNT];
 	const struct ec_params_pd_control *cmd = args->params;
 	int enable = 0;
 
@@ -546,49 +374,13 @@ static enum ec_status pd_control(struct host_cmd_handler_args *args)
 		return EC_RES_ACCESS_DENIED;
 
 	if (cmd->subcmd == PD_SUSPEND) {
-		/*
-		 * The AP is requesting to suspend PD traffic on the EC so it
-		 * can perform a firmware upgrade. If Vbus is present on the
-		 * connector (it is either a source or sink), then we will
-		 * prevent the upgrade if there is not enough battery to finish
-		 * the upgrade. We cannot rely on the EC's active charger data
-		 * as the EC just rebooted into RW and has not necessarily
-		 * picked the active charger yet.
-		 */
-#ifdef HAS_TASK_CHARGER
-		if (pd_is_vbus_present(cmd->chip)) {
-			struct batt_params batt = { 0 };
-			/*
-			 * The charger task has not re-initialized, so we need
-			 * to ask the battery directly.
-			 */
-			battery_get_params(&batt);
-			if (batt.remaining_capacity <
-				    MIN_BATTERY_FOR_TCPC_UPGRADE_MAH ||
-			    batt.flags & BATT_FLAG_BAD_REMAINING_CAPACITY) {
-				CPRINTS("C%d: Cannot suspend for upgrade, not "
-					"enough battery (%dmAh)!",
-					cmd->chip, batt.remaining_capacity);
-				return EC_RES_BUSY;
-			}
-		}
-#else
-		if (pd_is_vbus_present(cmd->chip)) {
-			CPRINTS("C%d: Cannot suspend for upgrade, Vbus "
-				"present!",
-				cmd->chip);
+		if (!pd_firmware_upgrade_check_power_readiness(cmd->chip))
 			return EC_RES_BUSY;
-		}
-#endif
 		enable = 0;
 	} else if (cmd->subcmd == PD_RESUME) {
 		enable = 1;
 	} else if (cmd->subcmd == PD_RESET) {
-#ifdef HAS_TASK_PDCMD
 		board_reset_pd_mcu();
-#else
-		return EC_RES_INVALID_COMMAND;
-#endif
 	} else if (cmd->subcmd == PD_CHIP_ON && board_set_tcpc_power_mode) {
 		board_set_tcpc_power_mode(cmd->chip, 1);
 		return EC_RES_SUCCESS;
@@ -604,13 +396,24 @@ static enum ec_status pd_control(struct host_cmd_handler_args *args)
 DECLARE_HOST_COMMAND(EC_CMD_PD_CONTROL, pd_control, EC_VER_MASK(0));
 #endif /* CONFIG_HOSTCMD_PD_CONTROL */
 
-#if !defined(CONFIG_USB_PD_TCPM_STUB) && !defined(TEST_BUILD)
+#if !defined(CONFIG_USB_PD_TCPM_STUB)
 /*
  * PD host event status for host command
  * Note: this variable must be aligned on 4-byte boundary because we pass the
- * address to deprecated_atomic_ functions which use assembly to access them.
+ * address to atomic_ functions which use assembly to access them.
  */
-static uint32_t pd_host_event_status __aligned(4);
+static atomic_t pd_host_event_status __aligned(4);
+
+void pd_send_host_event(int mask)
+{
+	/* mask must be set */
+	if (!mask)
+		return;
+
+	atomic_or(&pd_host_event_status, mask);
+	/* interrupt the AP */
+	host_set_single_event(EC_HOST_EVENT_PD_MCU);
+}
 
 static enum ec_status
 hc_pd_host_event_status(struct host_cmd_handler_args *args)
@@ -618,25 +421,13 @@ hc_pd_host_event_status(struct host_cmd_handler_args *args)
 	struct ec_response_host_event_status *r = args->response;
 
 	/* Read and clear the host event status to return to AP */
-	r->status = deprecated_atomic_read_clear(&pd_host_event_status);
+	r->status = atomic_clear(&pd_host_event_status);
 
 	args->response_size = sizeof(*r);
 	return EC_RES_SUCCESS;
 }
 DECLARE_HOST_COMMAND(EC_CMD_PD_HOST_EVENT_STATUS, hc_pd_host_event_status,
 		     EC_VER_MASK(0));
-
-/* Send host event up to AP */
-void pd_send_host_event(int mask)
-{
-	/* mask must be set */
-	if (!mask)
-		return;
-
-	deprecated_atomic_or(&pd_host_event_status, mask);
-	/* interrupt the AP */
-	host_set_single_event(EC_HOST_EVENT_PD_MCU);
-}
-#endif /* ! CONFIG_USB_PD_TCPM_STUB && ! TEST_BUILD */
+#endif /* ! CONFIG_USB_PD_TCPM_STUB */
 
 #endif /* HAS_TASK_HOSTCMD */
diff --git a/common/usb_pd_pdo.c b/common/usb_pd_pdo.c
new file mode 100644
index 0000000000..66f5f3feac
--- /dev/null
+++ b/common/usb_pd_pdo.c
@@ -0,0 +1,33 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "usb_pd.h"
+#include "usb_pd_pdo.h"
+#include "util.h"
+
+#ifndef CONFIG_USB_PD_CUSTOM_PDO
+
+#define PDO_FIXED_FLAGS \
+	(PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP | PDO_FIXED_COMM_CAP)
+
+const uint32_t pd_src_pdo[] = {
+	PDO_FIXED(5000, 1500, PDO_FIXED_FLAGS),
+};
+const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
+const uint32_t pd_src_pdo_max[] = {
+	PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS),
+};
+const int pd_src_pdo_max_cnt = ARRAY_SIZE(pd_src_pdo_max);
+
+const uint32_t pd_snk_pdo[] = {
+	PDO_FIXED(5000,
+		  GENERIC_MIN((PD_OPERATING_POWER_MW / 5), PD_MAX_CURRENT_MA),
+		  PDO_FIXED_FLAGS),
+	PDO_BATT(4750, PD_MAX_VOLTAGE_MV, PD_OPERATING_POWER_MW),
+	PDO_VAR(4750, PD_MAX_VOLTAGE_MV, PD_MAX_CURRENT_MA),
+};
+const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
+
+#endif /* CONFIG_USB_PD_CUSTOM_PDO */
diff --git a/common/usb_pd_policy.c b/common/usb_pd_policy.c
index 5ad4188e54..feb30db440 100644
--- a/common/usb_pd_policy.c
+++ b/common/usb_pd_policy.c
@@ -1,12 +1,15 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "atomic.h"
+#include "builtin/assert.h"
 #include "charge_manager.h"
+#include "chipset.h"
 #include "common.h"
 #include "console.h"
+#include "cros_version.h"
 #include "ec_commands.h"
 #include "flash.h"
 #include "gpio.h"
@@ -18,19 +21,20 @@
 #include "sha256.h"
 #include "system.h"
 #include "task.h"
-#include "tcpm.h"
+#include "tcpm/tcpm.h"
 #include "timer.h"
-#include "util.h"
+#include "typec_control.h"
 #include "usb_api.h"
 #include "usb_common.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
+#include "usb_pd_tcpm.h"
 #include "usbc_ppc.h"
-#include "version.h"
+#include "util.h"
 
 #ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
 #else
 #define CPRINTS(format, args...)
 #define CPRINTF(format, args...)
@@ -44,10 +48,42 @@
 #error This file must only be used with TCPMv1
 #endif
 
+#ifdef CONFIG_USB_PD_ALT_MODE_DFP
+#ifndef PORT_TO_HPD
+#define PORT_TO_HPD(port) ((port) ? GPIO_USB_C1_DP_HPD : GPIO_USB_C0_DP_HPD)
+#endif /* PORT_TO_HPD */
+
+/* Tracker for which task is waiting on sysjump prep to finish */
+static volatile task_id_t sysjump_task_waiting = TASK_ID_INVALID;
+
+/*
+ * timestamp of the next possible toggle to ensure the 2-ms spacing
+ * between IRQ_HPD.  Since this is used in overridable functions, this
+ * has to be global.
+ */
+uint64_t svdm_hpd_deadline[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+int dp_flags[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+uint32_t dp_status[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+/* Console command multi-function preference set for a PD port. */
+
+__maybe_unused bool dp_port_mf_allow[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	[0 ... CONFIG_USB_PD_PORT_MAX_COUNT - 1] = true
+};
+
+__overridable const struct svdm_response svdm_rsp = {
+	.identity = NULL,
+	.svids = NULL,
+	.modes = NULL,
+};
+#endif /* CONFIG_USB_PD_ALT_MODE_DFP */
+
 static int rw_flash_changed = 1;
 
-__overridable void pd_check_pr_role(int port,
-	enum pd_power_role pr_role, int flags)
+__overridable void pd_check_pr_role(int port, enum pd_power_role pr_role,
+				    int flags)
 {
 	/*
 	 * If partner is dual-role power and dualrole toggling is on, consider
@@ -63,34 +99,24 @@ __overridable void pd_check_pr_role(int port,
 		int partner_unconstrained = flags & PD_FLAGS_PARTNER_UNCONSTR;
 
 		if ((!partner_unconstrained && pr_role == PD_ROLE_SINK) ||
-		     (partner_unconstrained && pr_role == PD_ROLE_SOURCE))
+		    (partner_unconstrained && pr_role == PD_ROLE_SOURCE))
 			pd_request_power_swap(port);
 	}
 }
 
-__overridable void pd_check_dr_role(int port,
-	enum pd_data_role dr_role, int flags)
+__overridable void pd_check_dr_role(int port, enum pd_data_role dr_role,
+				    int flags)
 {
 	/* If UFP, try to switch to DFP */
 	if ((flags & PD_FLAGS_PARTNER_DR_DATA) && dr_role == PD_ROLE_UFP)
 		pd_request_data_swap(port);
 }
 
-#ifdef CONFIG_MKBP_EVENT
-static int dp_alt_mode_entry_get_next_event(uint8_t *data)
-{
-	return EC_SUCCESS;
-}
-DECLARE_EVENT_SOURCE(EC_MKBP_EVENT_DP_ALT_MODE_ENTERED,
-		     dp_alt_mode_entry_get_next_event);
-#endif /* CONFIG_MKBP_EVENT */
-
-#ifdef CONFIG_USB_PD_DUAL_ROLE
 /* Last received source cap */
 static uint32_t pd_src_caps[CONFIG_USB_PD_PORT_MAX_COUNT][PDO_MAX_OBJECTS];
 static uint8_t pd_src_cap_cnt[CONFIG_USB_PD_PORT_MAX_COUNT];
 
-const uint32_t * const pd_get_src_caps(int port)
+const uint32_t *const pd_get_src_caps(int port)
 {
 	return pd_src_caps[port];
 }
@@ -109,261 +135,24 @@ uint8_t pd_get_src_cap_cnt(int port)
 {
 	return pd_src_cap_cnt[port];
 }
-#endif /* CONFIG_USB_PD_DUAL_ROLE */
-
-static struct pd_cable cable[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-enum pd_rev_type get_usb_pd_cable_revision(int port)
-{
-	return cable[port].rev;
-}
-
-bool consume_sop_prime_repeat_msg(int port, uint8_t msg_id)
-{
-
-	if (cable[port].last_sop_p_msg_id != msg_id) {
-		cable[port].last_sop_p_msg_id = msg_id;
-		return false;
-	}
-	CPRINTF("C%d SOP Prime repeat msg_id %d\n", port, msg_id);
-	return true;
-}
-
-bool consume_sop_prime_prime_repeat_msg(int port, uint8_t msg_id)
-{
-
-	if (cable[port].last_sop_p_p_msg_id != msg_id) {
-		cable[port].last_sop_p_p_msg_id = msg_id;
-		return false;
-	}
-	CPRINTF("C%d SOP Prime Prime repeat msg_id %d\n", port, msg_id);
-	return true;
-}
-
-__maybe_unused static uint8_t is_sop_prime_ready(int port)
-{
-	/*
-	 * Ref: USB PD 3.0 sec 2.5.4: When an Explicit Contract is in place the
-	 * VCONN Source (either the DFP or the UFP) can communicate with the
-	 * Cable Plug(s) using SOP’/SOP’’ Packets
-	 *
-	 * Ref: USB PD 2.0 sec 2.4.4: When an Explicit Contract is in place the
-	 * DFP (either the Source or the Sink) can communicate with the
-	 * Cable Plug(s) using SOP’/SOP” Packets.
-	 * Sec 3.6.11 : Before communicating with a Cable Plug a Port Should
-	 * ensure that it is the Vconn Source
-	 */
-	return (pd_get_vconn_state(port) && (IS_ENABLED(CONFIG_USB_PD_REV30)
-		|| (pd_get_data_role(port) == PD_ROLE_DFP)));
-}
-
-void reset_pd_cable(int port)
-{
-	memset(&cable[port], 0, sizeof(cable[port]));
-	cable[port].last_sop_p_msg_id = INVALID_MSG_ID_COUNTER;
-	cable[port].last_sop_p_p_msg_id = INVALID_MSG_ID_COUNTER;
-}
-
-bool should_enter_usb4_mode(int port)
-{
-	return IS_ENABLED(CONFIG_USB_PD_USB4) &&
-		cable[port].flags & CABLE_FLAGS_ENTER_USB_MODE;
-}
-
-void enable_enter_usb4_mode(int port)
-{
-	if (IS_ENABLED(CONFIG_USB_PD_USB4))
-		cable[port].flags |= CABLE_FLAGS_ENTER_USB_MODE;
-}
-
-void disable_enter_usb4_mode(int port)
-{
-	if (IS_ENABLED(CONFIG_USB_PD_USB4))
-		cable[port].flags &= ~CABLE_FLAGS_ENTER_USB_MODE;
-}
 
 #ifdef CONFIG_USB_PD_ALT_MODE
 
 #ifdef CONFIG_USB_PD_ALT_MODE_DFP
 
-static struct pd_discovery
-	discovery[CONFIG_USB_PD_PORT_MAX_COUNT][DISCOVERY_TYPE_COUNT];
-static struct partner_active_modes
-	partner_amodes[CONFIG_USB_PD_PORT_MAX_COUNT][AMODE_TYPE_COUNT];
-
-static bool is_vdo_present(int cnt, int index)
-{
-	return cnt > index;
-}
-
-static bool is_modal(int port, int cnt, const uint32_t *payload)
-{
-	return is_vdo_present(cnt, VDO_INDEX_IDH) &&
-		PD_IDH_IS_MODAL(payload[VDO_INDEX_IDH]);
-}
-
-static bool is_tbt_compat_mode(int port, int cnt, const uint32_t *payload)
-{
-	/*
-	 * Ref: USB Type-C cable and connector specification
-	 * F.2.5 TBT3 Device Discover Mode Responses
-	 */
-	return is_vdo_present(cnt, VDO_INDEX_IDH) &&
-		PD_VDO_RESP_MODE_INTEL_TBT(payload[VDO_INDEX_IDH]);
-}
-
-static bool cable_supports_tbt_speed(int port)
-{
-	enum tbt_compat_cable_speed tbt_cable_speed =
-				get_tbt_cable_speed(port);
-
-	return (tbt_cable_speed == TBT_SS_TBT_GEN3 ||
-		tbt_cable_speed == TBT_SS_U32_GEN1_GEN2);
-}
-
-static bool is_tbt_compat_enabled(int port)
-{
-	return (IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE) &&
-	       (cable[port].flags & CABLE_FLAGS_TBT_COMPAT_ENABLE));
-}
-
-static void enable_tbt_compat_mode(int port)
-{
-	if (IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE))
-		cable[port].flags |= CABLE_FLAGS_TBT_COMPAT_ENABLE;
-}
-
-static inline void disable_tbt_compat_mode(int port)
-{
-	if (IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE))
-		cable[port].flags &= ~CABLE_FLAGS_TBT_COMPAT_ENABLE;
-}
-
-static inline void limit_tbt_cable_speed(int port)
-{
-	/* Cable flags are cleared when cable reset is called */
-	cable[port].flags |= CABLE_FLAGS_TBT_COMPAT_LIMIT_SPEED;
-}
-
-static inline bool is_limit_tbt_cable_speed(int port)
-{
-	return !!(cable[port].flags & CABLE_FLAGS_TBT_COMPAT_LIMIT_SPEED);
-}
-
-static bool is_intel_svid(int port, enum tcpm_transmit_type type)
-{
-	int i;
-
-	for (i = 0; i < discovery[port][type].svid_cnt; i++) {
-		if (pd_get_svid(port, i, type) == USB_VID_INTEL)
-			return true;
-	}
-
-	return false;
-}
-
-static inline bool is_usb4_mode_enabled(int port)
-{
-	return (IS_ENABLED(CONFIG_USB_PD_USB4) &&
-	       (cable[port].flags & CABLE_FLAGS_USB4_CAPABLE));
-}
-
-static inline void enable_usb4_mode(int port)
-{
-	if (IS_ENABLED(CONFIG_USB_PD_USB4))
-		cable[port].flags |= CABLE_FLAGS_USB4_CAPABLE;
-}
-
-static inline void disable_usb4_mode(int port)
-{
-	if (IS_ENABLED(CONFIG_USB_PD_USB4))
-		cable[port].flags &= ~CABLE_FLAGS_USB4_CAPABLE;
-}
-
-/*
- * Ref: USB Type-C Cable and Connector Specification
- * Figure 5-1 USB4 Discovery and Entry Flow Model.
- *
- * Note: USB Type-C Cable and Connector Specification
- * doesn't include details for Revision 2 cables.
- *
- *                         Passive Cable
- *                                |
- *                -----------------------------------
- *                |                                 |
- *           Revision 2                        Revision 3
- *          USB Signalling                   USB Signalling
- *             |                                     |
- *     ------------------            -------------------------
- *     |       |        |            |       |       |       |
- * USB2.0   USB3.1    USB3.1       USB3.2   USB4   USB3.2   USB2
- *   |      Gen1      Gen1 Gen2    Gen2     Gen3   Gen1       |
- *   |       |          |           |        |       |       Exit
- *   --------           ------------         --------        USB4
- *      |                    |                  |          Discovery.
- *    Exit          Is DFP Gen3 Capable?     Enter USB4
- *    USB4                  |                with respective
- *   Discovery.   --- No ---|--- Yes ---     cable speed.
- *                |                    |
- *    Enter USB4 with             Is Cable TBT3
- *    respective cable                 |
- *    speed.                 --- No ---|--- Yes ---
- *                           |                    |
- *                   Enter USB4 with        Enter USB4 with
- *                   TBT Gen2 passive       TBT Gen3 passive
- *                   cable.                 cable.
- *
- */
-static bool is_cable_ready_to_enter_usb4(int port, int cnt)
-{
-	/* TODO: USB4 enter mode for Active cables */
-	struct pd_discovery *disc = &discovery[port][TCPC_TX_SOP_PRIME];
-	if (IS_ENABLED(CONFIG_USB_PD_USB4) &&
-	   (get_usb_pd_cable_type(port) == IDH_PTYPE_PCABLE) &&
-	    is_vdo_present(cnt, VDO_INDEX_PTYPE_CABLE1)) {
-		switch (cable[port].rev) {
-		case PD_REV30:
-			switch (disc->identity.product_t1.p_rev30.ss) {
-			case USB_R30_SS_U40_GEN3:
-			case USB_R30_SS_U32_U40_GEN1:
-				return true;
-			case USB_R30_SS_U32_U40_GEN2:
-				/* Check if DFP is Gen 3 capable */
-				if (IS_ENABLED(CONFIG_USB_PD_TBT_GEN3_CAPABLE))
-					return false;
-				return true;
-			default:
-				disable_usb4_mode(port);
-				return false;
-			}
-		case PD_REV20:
-			switch (disc->identity.product_t1.p_rev20.ss) {
-			case USB_R20_SS_U31_GEN1_GEN2:
-				/* Check if DFP is Gen 3 capable */
-				if (IS_ENABLED(CONFIG_USB_PD_TBT_GEN3_CAPABLE))
-					return false;
-				return true;
-			default:
-				disable_usb4_mode(port);
-				return false;
-		}
-		default:
-			disable_usb4_mode(port);
-		}
-	}
-	return false;
-}
+static struct pd_discovery discovery[CONFIG_USB_PD_PORT_MAX_COUNT]
+				    [DISCOVERY_TYPE_COUNT];
+static struct partner_active_modes partner_amodes[CONFIG_USB_PD_PORT_MAX_COUNT]
+						 [AMODE_TYPE_COUNT];
 
 void pd_dfp_discovery_init(int port)
 {
 	memset(&discovery[port], 0, sizeof(struct pd_discovery));
-	memset(&partner_amodes[port], 0, sizeof(partner_amodes[0]));
 }
 
-static int dfp_discover_ident(uint32_t *payload)
+void pd_dfp_mode_init(int port)
 {
-	payload[0] = VDO(USB_SID_PD, 1, CMD_DISCOVER_IDENT);
-	return 1;
+	memset(&partner_amodes[port], 0, sizeof(partner_amodes[0]));
 }
 
 static int dfp_discover_svids(uint32_t *payload)
@@ -372,13 +161,20 @@ static int dfp_discover_svids(uint32_t *payload)
 	return 1;
 }
 
-struct pd_discovery *pd_get_am_discovery(int port, enum tcpm_transmit_type type)
+struct pd_discovery *
+pd_get_am_discovery_and_notify_access(int port, enum tcpci_msg_type type)
+{
+	return (struct pd_discovery *)pd_get_am_discovery(port, type);
+}
+
+const struct pd_discovery *pd_get_am_discovery(int port,
+					       enum tcpci_msg_type type)
 {
 	return &discovery[port][type];
 }
 
-struct partner_active_modes *pd_get_partner_active_modes(int port,
-		enum tcpm_transmit_type type)
+struct partner_active_modes *
+pd_get_partner_active_modes(int port, enum tcpci_msg_type type)
 {
 	assert(type < AMODE_TYPE_COUNT);
 	return &partner_amodes[port][type];
@@ -398,7 +194,8 @@ void pd_set_dfp_enter_mode_flag(int port, bool set)
  */
 static int dfp_discover_modes(int port, uint32_t *payload)
 {
-	struct pd_discovery *disc = pd_get_am_discovery(port, TCPC_TX_SOP);
+	const struct pd_discovery *disc =
+		pd_get_am_discovery(port, TCPCI_MSG_SOP);
 	uint16_t svid = disc->svids[disc->svid_idx].svid;
 
 	if (disc->svid_idx >= disc->svid_cnt)
@@ -409,231 +206,34 @@ static int dfp_discover_modes(int port, uint32_t *payload)
 	return 1;
 }
 
-static bool is_usb4_vdo(int port, int cnt, uint32_t *payload)
-{
-	enum idh_ptype ptype = PD_IDH_PTYPE(payload[VDO_I(IDH)]);
-
-	if (IS_PD_IDH_UFP_PTYPE(ptype)) {
-		/*
-		 * Ref: USB Type-C Cable and Connector Specification
-		 * Figure 5-1 USB4 Discovery and Entry Flow Model
-		 * Device USB4 VDO detection.
-		 */
-		return IS_ENABLED(CONFIG_USB_PD_USB4) &&
-			is_vdo_present(cnt, VDO_INDEX_PTYPE_UFP1_VDO) &&
-			PD_PRODUCT_IS_USB4(payload[VDO_INDEX_PTYPE_UFP1_VDO]);
-	}
-	return false;
-}
-
-static int process_am_discover_ident_sop(int port, int cnt,
-					uint32_t head, uint32_t *payload,
-					enum tcpm_transmit_type *rtype)
+static int process_am_discover_ident_sop(int port, int cnt, uint32_t head,
+					 uint32_t *payload,
+					 enum tcpci_msg_type *rtype)
 {
 	pd_dfp_discovery_init(port);
-	dfp_consume_identity(port, TCPC_TX_SOP, cnt, payload);
-
-	if (IS_ENABLED(CONFIG_USB_PD_DECODE_SOP) && is_sop_prime_ready(port) &&
-	    board_is_tbt_usb4_port(port)) {
-
-		/* Enable USB4 mode if USB4 VDO present and port partner
-		 * supports USB Rev 3.0.
-		 */
-		if (is_usb4_vdo(port, cnt, payload) &&
-		    PD_HEADER_REV(head) == PD_REV30)
-			enable_usb4_mode(port);
-
-		/*
-		 * Enable Thunderbolt-compatible mode if the modal operation is
-		 * supported.
-		 */
-		if (is_modal(port, cnt, payload))
-			enable_tbt_compat_mode(port);
-
-		if (is_modal(port, cnt, payload) ||
-		    is_usb4_vdo(port, cnt, payload)) {
-			*rtype = TCPC_TX_SOP_PRIME;
-			return dfp_discover_ident(payload);
-		}
-	}
-
-	return dfp_discover_svids(payload);
-}
-
-static int process_am_discover_ident_sop_prime(int port, int cnt,
-					uint32_t head, uint32_t *payload)
-{
-	dfp_consume_identity(port, TCPC_TX_SOP_PRIME, cnt, payload);
-	cable[port].rev = PD_HEADER_REV(head);
-
-	/*
-	 * Enter USB4 mode if the cable supports USB4 operation and has USB4
-	 * VDO.
-	 */
-	if (is_usb4_mode_enabled(port) &&
-	    is_cable_ready_to_enter_usb4(port, cnt)) {
-		enable_enter_usb4_mode(port);
-		usb_mux_set_safe_mode(port);
-		/*
-		 * To change the mode of operation from USB4 the port needs to
-		 * be reconfigured.
-		 * Ref: USB Type-C Cable and Connectot Spec section 5.4.4.
-		 */
-		disable_tbt_compat_mode(port);
-		return 0;
-	}
-
-	/*
-	 * Disable Thunderbolt-compatible mode if the cable does not support
-	 * superspeed.
-	 */
-	if (is_tbt_compat_enabled(port) && !is_tbt_cable_superspeed(port))
-		disable_tbt_compat_mode(port);
+	pd_dfp_mode_init(port);
+	dfp_consume_identity(port, TCPCI_MSG_SOP, cnt, payload);
 
 	return dfp_discover_svids(payload);
 }
 
 static int process_am_discover_svids(int port, int cnt, uint32_t *payload,
-				enum tcpm_transmit_type sop,
-				enum tcpm_transmit_type *rtype)
+				     enum tcpci_msg_type sop,
+				     enum tcpci_msg_type *rtype)
 {
 	/*
 	 * The pd_discovery structure stores SOP and SOP' discovery results
 	 * separately, but TCPMv1 depends on one-dimensional storage of SVIDs
-	 * and modes. Therefore, always use TCPC_TX_SOP in TCPMv1.
+	 * and modes. Therefore, always use TCPCI_MSG_SOP in TCPMv1.
 	 */
 	dfp_consume_svids(port, sop, cnt, payload);
 
-	/*
-	 * Ref: USB Type-C Cable and Connector Specification,
-	 * figure F-1: TBT3 Discovery Flow
-	 *
-	 * For USB4 mode if device or cable doesn't have Intel SVID,
-	 * disable Thunderbolt-Compatible mode directly enter USB4 mode
-	 * with USB3.2 Gen1/Gen2 speed.
-	 *
-	 * For Thunderbolt-compatible, check if 0x8087 is received for
-	 * Discover SVID SOP. If not, disable Thunderbolt-compatible mode
-	 *
-	 * If 0x8087 is not received for Discover SVID SOP' limit to TBT
-	 * passive Gen 2 cable.
-	 */
-	if (is_tbt_compat_enabled(port)) {
-		bool intel_svid = is_intel_svid(port, sop);
-		if (!intel_svid) {
-			if (is_usb4_mode_enabled(port)) {
-				disable_tbt_compat_mode(port);
-				cable[port].cable_mode_resp.tbt_cable_speed =
-					TBT_SS_U32_GEN1_GEN2;
-				enable_enter_usb4_mode(port);
-				usb_mux_set_safe_mode(port);
-				return 0;
-			}
-
-			if (sop == TCPC_TX_SOP_PRIME)
-				limit_tbt_cable_speed(port);
-			else
-				disable_tbt_compat_mode(port);
-		} else if (sop == TCPC_TX_SOP) {
-			*rtype = TCPC_TX_SOP_PRIME;
-			return dfp_discover_svids(payload);
-		}
-	}
-
 	return dfp_discover_modes(port, payload);
 }
-
-static int process_tbt_compat_discover_modes(int port,
-				enum tcpm_transmit_type sop, uint32_t *payload,
-				enum tcpm_transmit_type *rtype)
-{
-	int rsize;
-
-	/* Initialize transmit type to SOP */
-	*rtype = TCPC_TX_SOP;
-
-	/*
-	 * For active cables, Enter mode: SOP', SOP'', SOP
-	 * Ref: USB Type-C Cable and Connector Specification, figure F-1: TBT3
-	 * Discovery Flow and Section F.2.7 TBT3 Cable Enter Mode Command.
-	 */
-	if (sop == TCPC_TX_SOP_PRIME) {
-		/* Store Discover Mode SOP' response */
-		cable[port].cable_mode_resp.raw_value = payload[1];
-
-		if (is_usb4_mode_enabled(port)) {
-			/*
-			 * If Cable is not Thunderbolt Gen 3
-			 * capable or Thunderbolt Gen1_Gen2
-			 * capable, disable USB4 mode and
-			 * continue flow for
-			 * Thunderbolt-compatible mode
-			 */
-			if (cable_supports_tbt_speed(port)) {
-				enable_enter_usb4_mode(port);
-				usb_mux_set_safe_mode(port);
-				return 0;
-			}
-			disable_usb4_mode(port);
-		}
-
-		/*
-		 * Send TBT3 Cable Enter Mode (SOP') for active cables,
-		 * otherwise send TBT3 Device Enter Mode (SOP).
-		 */
-		if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE)
-			*rtype = TCPC_TX_SOP_PRIME;
-
-		rsize = enter_tbt_compat_mode(port, *rtype, payload);
-	} else {
-		/* Store Discover Mode SOP response */
-		cable[port].dev_mode_resp.raw_value = payload[1];
-
-		if (is_limit_tbt_cable_speed(port)) {
-			/*
-			 * Passive cable has Nacked for Discover SVID.
-			 * No need to do Discover modes of cable.
-			 * Enter into device Thunderbolt-compatible mode.
-			 */
-			rsize = enter_tbt_compat_mode(port, *rtype, payload);
-		} else {
-			/* Discover modes for SOP' */
-			discovery[port][TCPC_TX_SOP].svid_idx--;
-			rsize = dfp_discover_modes(port, payload);
-			*rtype = TCPC_TX_SOP_PRIME;
-		}
-	}
-
-	return rsize;
-}
-
-static int obj_cnt_enter_tbt_compat_mode(int port,
-		enum tcpm_transmit_type sop, uint32_t *payload,
-		enum tcpm_transmit_type *rtype)
-{
-	struct pd_discovery *disc = &discovery[port][TCPC_TX_SOP_PRIME];
-
-	/* Enter mode SOP' for active cables */
-	if (sop == TCPC_TX_SOP_PRIME) {
-		/* Check if the cable has a SOP'' controller */
-		if (disc->identity.product_t1.a_rev20.sop_p_p)
-			*rtype = TCPC_TX_SOP_PRIME_PRIME;
-		return enter_tbt_compat_mode(port, *rtype, payload);
-	}
-
-	/* Enter Mode SOP'' for active cables with SOP'' controller */
-	if (sop == TCPC_TX_SOP_PRIME_PRIME)
-		return enter_tbt_compat_mode(port, *rtype, payload);
-
-	/* Update Mux state to Thunderbolt-compatible mode. */
-	set_tbt_compat_mode_ready(port);
-	/* No response once device (and cable) acks */
-	return 0;
-}
 #endif /* CONFIG_USB_PD_ALT_MODE_DFP */
 
 int pd_svdm(int port, int cnt, uint32_t *payload, uint32_t **rpayload,
-		uint32_t head, enum tcpm_transmit_type *rtype)
+	    uint32_t head, enum tcpci_msg_type *rtype)
 {
 	int cmd = PD_VDO_CMD(payload[0]);
 	int cmd_type = PD_VDO_CMDT(payload[0]);
@@ -642,11 +242,11 @@ int pd_svdm(int port, int cnt, uint32_t *payload, uint32_t **rpayload,
 	int rsize = 1; /* VDM header at a minimum */
 
 #ifdef CONFIG_USB_PD_ALT_MODE_DFP
-	enum tcpm_transmit_type sop = PD_HEADER_GET_SOP(head);
+	enum tcpci_msg_type sop = PD_HEADER_GET_SOP(head);
 #endif
 
 	/* Transmit SOP messages by default */
-	*rtype = TCPC_TX_SOP;
+	*rtype = TCPCI_MSG_SOP;
 
 	payload[0] &= ~VDO_CMDT_MASK;
 	*rpayload = payload;
@@ -702,32 +302,21 @@ int pd_svdm(int port, int cnt, uint32_t *payload, uint32_t **rpayload,
 			payload[0] |= VDO_CMDT(CMDT_RSP_BUSY);
 			rsize = 1;
 		}
-		payload[0] |= VDO_SVDM_VERS(pd_get_vdo_ver(port, TCPC_TX_SOP));
+		payload[0] |=
+			VDO_SVDM_VERS(pd_get_vdo_ver(port, TCPCI_MSG_SOP));
 	} else if (cmd_type == CMDT_RSP_ACK) {
 #ifdef CONFIG_USB_PD_ALT_MODE_DFP
 		struct svdm_amode_data *modep;
 
-		modep = pd_get_amode_data(port, TCPC_TX_SOP,
-				PD_VDO_VID(payload[0]));
+		modep = pd_get_amode_data(port, TCPCI_MSG_SOP,
+					  PD_VDO_VID(payload[0]));
 #endif
 		switch (cmd) {
 #ifdef CONFIG_USB_PD_ALT_MODE_DFP
 		case CMD_DISCOVER_IDENT:
-			/* Received a SOP' Discover Ident msg */
-			if (sop == TCPC_TX_SOP_PRIME) {
-				rsize = process_am_discover_ident_sop_prime(
-						port, cnt, head, payload);
 			/* Received a SOP Discover Ident Message */
-			} else {
-				rsize = process_am_discover_ident_sop(port,
-						cnt, head, payload, rtype);
-			}
-#ifdef CONFIG_CHARGE_MANAGER
-			if (pd_charge_from_device(pd_get_identity_vid(port),
-						  pd_get_identity_pid(port)))
-				charge_manager_update_dualrole(port,
-							       CAP_DEDICATED);
-#endif
+			rsize = process_am_discover_ident_sop(port, cnt, head,
+							      payload, rtype);
 			break;
 		case CMD_DISCOVER_SVID:
 			rsize = process_am_discover_svids(port, cnt, payload,
@@ -735,42 +324,23 @@ int pd_svdm(int port, int cnt, uint32_t *payload, uint32_t **rpayload,
 			break;
 		case CMD_DISCOVER_MODES:
 			dfp_consume_modes(port, sop, cnt, payload);
-			if (is_tbt_compat_enabled(port) &&
-				is_tbt_compat_mode(port, cnt, payload)) {
-				rsize = process_tbt_compat_discover_modes(
-					      port, sop, payload, rtype);
-				break;
-			}
 
 			rsize = dfp_discover_modes(port, payload);
 			/* enter the default mode for DFP */
 			if (!rsize) {
-				/*
-				 * Disabling Thunderbolt-Compatible mode if
-				 * discover mode response doesn't include Intel
-				 * SVID.
-				 */
-				disable_tbt_compat_mode(port);
-				payload[0] = pd_dfp_enter_mode(port,
-						TCPC_TX_SOP, 0, 0);
+				payload[0] = pd_dfp_enter_mode(
+					port, TCPCI_MSG_SOP, 0, 0);
 				if (payload[0])
 					rsize = 1;
 			}
 			break;
 		case CMD_ENTER_MODE:
-			if (is_tbt_compat_enabled(port)) {
-				rsize = obj_cnt_enter_tbt_compat_mode(port,
-							sop, payload, rtype);
-			/*
-			 * Continue with PD flow if Thunderbolt-compatible mode
-			 * is disabled.
-			 */
-			} else if (!modep) {
+			if (!modep) {
 				rsize = 0;
 			} else {
 				if (!modep->opos)
-					pd_dfp_enter_mode(port, TCPC_TX_SOP, 0,
-							0);
+					pd_dfp_enter_mode(port, TCPCI_MSG_SOP,
+							  0, 0);
 
 				if (modep->opos) {
 					rsize = modep->fx->status(port,
@@ -780,13 +350,31 @@ int pd_svdm(int port, int cnt, uint32_t *payload, uint32_t **rpayload,
 			}
 			break;
 		case CMD_DP_STATUS:
-			/* DP status response & UFP's DP attention have same
-			   payload */
+			/*
+			 * Note: DP status response & UFP's DP attention have
+			 * the same payload
+			 */
 			dfp_consume_attention(port, payload);
-			if (modep && modep->opos)
+
+			if (modep && modep->opos) {
+				/*
+				 * Place the USB Type-C pins that are to be
+				 * re-configured to DisplayPort Configuration
+				 * into the Safe state. For USB_PD_MUX_DOCK,
+				 * the superspeed signals can remain connected.
+				 * For USB_PD_MUX_DP_ENABLED, disconnect the
+				 * superspeed signals here, before the pins are
+				 * re-configured to DisplayPort (in
+				 * svdm_dp_post_config, when we receive the
+				 * config ack).
+				 */
+				if (svdm_dp_get_mux_mode(port) ==
+				    USB_PD_MUX_DP_ENABLED)
+					usb_mux_set_safe_mode(port);
 				rsize = modep->fx->config(port, payload);
-			else
+			} else {
 				rsize = 0;
+			}
 			break;
 		case CMD_DP_CONFIG:
 			if (modep && modep->opos && modep->fx->post_config)
@@ -809,7 +397,8 @@ int pd_svdm(int port, int cnt, uint32_t *payload, uint32_t **rpayload,
 		}
 
 		payload[0] |= VDO_CMDT(CMDT_INIT);
-		payload[0] |= VDO_SVDM_VERS(pd_get_vdo_ver(port, TCPC_TX_SOP));
+		payload[0] |=
+			VDO_SVDM_VERS(pd_get_vdo_ver(port, TCPCI_MSG_SOP));
 #ifdef CONFIG_USB_PD_ALT_MODE_DFP
 	} else if (cmd_type == CMDT_RSP_BUSY) {
 		switch (cmd) {
@@ -831,15 +420,7 @@ int pd_svdm(int port, int cnt, uint32_t *payload, uint32_t **rpayload,
 			rsize = 0;
 		}
 	} else if (cmd_type == CMDT_RSP_NAK) {
-		/* Passive cable Nacked for Discover SVID */
-		if (cmd == CMD_DISCOVER_SVID && is_tbt_compat_enabled(port) &&
-		    sop == TCPC_TX_SOP_PRIME &&
-		    get_usb_pd_cable_type(port) == IDH_PTYPE_PCABLE) {
-			limit_tbt_cable_speed(port);
-			rsize = dfp_discover_modes(port, payload);
-		} else {
-			rsize = 0;
-		}
+		rsize = 0;
 #endif /* CONFIG_USB_PD_ALT_MODE_DFP */
 	} else {
 		CPRINTF("ERR:CMDT:%d\n", cmd);
@@ -852,15 +433,16 @@ int pd_svdm(int port, int cnt, uint32_t *payload, uint32_t **rpayload,
 #else
 
 int pd_svdm(int port, int cnt, uint32_t *payload, uint32_t **rpayload,
-		uint32_t head, enum tcpm_transmit_type *rtype)
+	    uint32_t head, enum tcpci_msg_type *rtype)
 {
 	return 0;
 }
 
 #endif /* CONFIG_USB_PD_ALT_MODE */
 
-#define FW_RW_END (CONFIG_EC_WRITABLE_STORAGE_OFF + \
-		   CONFIG_RW_STORAGE_OFF + CONFIG_RW_SIZE)
+#define FW_RW_END                                                 \
+	(CONFIG_EC_WRITABLE_STORAGE_OFF + CONFIG_RW_STORAGE_OFF + \
+	 CONFIG_RW_SIZE)
 
 uint8_t *flash_hash_rw(void)
 {
@@ -870,8 +452,9 @@ uint8_t *flash_hash_rw(void)
 	if (rw_flash_changed) {
 		rw_flash_changed = 0;
 		SHA256_init(&ctx);
-		SHA256_update(&ctx, (void *)CONFIG_PROGRAM_MEMORY_BASE +
-			      CONFIG_RW_MEM_OFF,
+		SHA256_update(&ctx,
+			      (void *)CONFIG_PROGRAM_MEMORY_BASE +
+				      CONFIG_RW_MEM_OFF,
 			      CONFIG_RW_SIZE - RSANUMBYTES);
 		return SHA256_final(&ctx);
 	} else {
@@ -922,21 +505,22 @@ int pd_custom_flash_vdm(int port, int cnt, uint32_t *payload)
 		if (system_get_image_copy() != EC_IMAGE_RO)
 			break;
 		pd_log_event(PD_EVENT_ACC_RW_ERASE, 0, 0, NULL);
-		flash_offset = CONFIG_EC_WRITABLE_STORAGE_OFF +
-			       CONFIG_RW_STORAGE_OFF;
-		flash_physical_erase(CONFIG_EC_WRITABLE_STORAGE_OFF +
-				     CONFIG_RW_STORAGE_OFF, CONFIG_RW_SIZE);
+		flash_offset =
+			CONFIG_EC_WRITABLE_STORAGE_OFF + CONFIG_RW_STORAGE_OFF;
+		crec_flash_physical_erase(CONFIG_EC_WRITABLE_STORAGE_OFF +
+						  CONFIG_RW_STORAGE_OFF,
+					  CONFIG_RW_SIZE);
 		rw_flash_changed = 1;
 		break;
 	case VDO_CMD_FLASH_WRITE:
 		/* do not kill the code under our feet */
 		if ((system_get_image_copy() != EC_IMAGE_RO) ||
-		    (flash_offset < CONFIG_EC_WRITABLE_STORAGE_OFF +
-				    CONFIG_RW_STORAGE_OFF))
+		    (flash_offset <
+		     CONFIG_EC_WRITABLE_STORAGE_OFF + CONFIG_RW_STORAGE_OFF))
 			break;
-		flash_physical_write(flash_offset, 4*(cnt - 1),
-				     (const char *)(payload+1));
-		flash_offset += 4*(cnt - 1);
+		crec_flash_physical_write(flash_offset, 4 * (cnt - 1),
+					  (const char *)(payload + 1));
+		flash_offset += 4 * (cnt - 1);
 		rw_flash_changed = 1;
 		break;
 	case VDO_CMD_ERASE_SIG:
@@ -947,8 +531,8 @@ int pd_custom_flash_vdm(int port, int cnt, uint32_t *payload)
 			/* zeroes the area containing the RSA signature */
 			for (offset = FW_RW_END - RSANUMBYTES;
 			     offset < FW_RW_END; offset += 4)
-				flash_physical_write(offset, 4,
-						     (const char *)&zero);
+				crec_flash_physical_write(offset, 4,
+							  (const char *)&zero);
 		}
 		break;
 	default:
@@ -957,3 +541,736 @@ int pd_custom_flash_vdm(int port, int cnt, uint32_t *payload)
 	}
 	return rsize;
 }
+
+#ifdef CONFIG_USB_PD_ALT_MODE_DFP
+static enum ec_status hc_remote_pd_set_amode(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_usb_pd_set_mode_request *p = args->params;
+
+	if ((p->port >= board_get_usb_pd_port_count()) || (!p->svid) ||
+	    (!p->opos))
+		return EC_RES_INVALID_PARAM;
+
+	switch (p->cmd) {
+	case PD_EXIT_MODE:
+		if (pd_dfp_exit_mode(p->port, TCPCI_MSG_SOP, p->svid, p->opos))
+			pd_send_vdm(p->port, p->svid,
+				    CMD_EXIT_MODE | VDO_OPOS(p->opos), NULL, 0);
+		else {
+			CPRINTF("Failed exit mode\n");
+			return EC_RES_ERROR;
+		}
+		break;
+	case PD_ENTER_MODE:
+		if (pd_dfp_enter_mode(p->port, TCPCI_MSG_SOP, p->svid, p->opos))
+			pd_send_vdm(p->port, p->svid,
+				    CMD_ENTER_MODE | VDO_OPOS(p->opos), NULL,
+				    0);
+		break;
+	default:
+		return EC_RES_INVALID_PARAM;
+	}
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_USB_PD_SET_AMODE, hc_remote_pd_set_amode,
+		     EC_VER_MASK(0));
+
+const uint32_t *pd_get_mode_vdo(int port, uint16_t svid_idx,
+				enum tcpci_msg_type type)
+{
+	const struct pd_discovery *disc = pd_get_am_discovery(port, type);
+
+	return disc->svids[svid_idx].mode_vdo;
+}
+
+static enum ec_status hc_remote_pd_get_amode(struct host_cmd_handler_args *args)
+{
+	struct svdm_amode_data *modep;
+	const struct ec_params_usb_pd_get_mode_request *p = args->params;
+	struct ec_params_usb_pd_get_mode_response *r = args->response;
+
+	if (p->port >= board_get_usb_pd_port_count())
+		return EC_RES_INVALID_PARAM;
+
+	/* no more to send */
+	/* TODO(b/148528713): Use TCPMv2's separate storage for SOP'. */
+	if (p->svid_idx >= pd_get_svid_count(p->port, TCPCI_MSG_SOP)) {
+		r->svid = 0;
+		args->response_size = sizeof(r->svid);
+		return EC_RES_SUCCESS;
+	}
+
+	r->svid = pd_get_svid(p->port, p->svid_idx, TCPCI_MSG_SOP);
+	r->opos = 0;
+	memcpy(r->vdo, pd_get_mode_vdo(p->port, p->svid_idx, TCPCI_MSG_SOP),
+	       sizeof(uint32_t) * VDO_MAX_OBJECTS);
+	modep = pd_get_amode_data(p->port, TCPCI_MSG_SOP, r->svid);
+
+	if (modep)
+		r->opos = pd_alt_mode(p->port, TCPCI_MSG_SOP, r->svid);
+
+	args->response_size = sizeof(*r);
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_USB_PD_GET_AMODE, hc_remote_pd_get_amode,
+		     EC_VER_MASK(0));
+
+static int pd_get_mode_idx(int port, enum tcpci_msg_type type, uint16_t svid)
+{
+	int amode_idx;
+	struct partner_active_modes *active =
+		pd_get_partner_active_modes(port, type);
+
+	for (amode_idx = 0; amode_idx < PD_AMODE_COUNT; amode_idx++) {
+		if (active->amodes[amode_idx].fx &&
+		    (active->amodes[amode_idx].fx->svid == svid))
+			return amode_idx;
+	}
+	return -1;
+}
+
+static int pd_allocate_mode(int port, enum tcpci_msg_type type, uint16_t svid)
+{
+	int i, j;
+	struct svdm_amode_data *modep;
+	int mode_idx = pd_get_mode_idx(port, type, svid);
+	const struct pd_discovery *disc = pd_get_am_discovery(port, type);
+	struct partner_active_modes *active =
+		pd_get_partner_active_modes(port, type);
+	assert(active);
+
+	if (mode_idx != -1)
+		return mode_idx;
+
+	/* There's no space to enter another mode */
+	if (active->amode_idx == PD_AMODE_COUNT) {
+		CPRINTF("ERR:NO AMODE SPACE\n");
+		return -1;
+	}
+
+	/* Allocate ...  if SVID == 0 enter default supported policy */
+	for (i = 0; i < supported_modes_cnt; i++) {
+		for (j = 0; j < disc->svid_cnt; j++) {
+			const struct svid_mode_data *svidp = &disc->svids[j];
+
+			/*
+			 * Looking for a match between supported_modes and
+			 * discovered SVIDs; must also match the passed-in SVID
+			 * if that was non-zero. Otherwise, go to the next
+			 * discovered SVID.
+			 * TODO(b/155890173): Support AP-directed mode entry
+			 * where the mode is unknown to the TCPM.
+			 */
+			if ((svidp->svid != supported_modes[i].svid) ||
+			    (svid && (svidp->svid != svid)))
+				continue;
+
+			modep = &active->amodes[active->amode_idx];
+			modep->fx = &supported_modes[i];
+			modep->data = &disc->svids[j];
+			active->amode_idx++;
+			return active->amode_idx - 1;
+		}
+	}
+	return -1;
+}
+
+static int validate_mode_request(struct svdm_amode_data *modep, uint16_t svid,
+				 int opos)
+{
+	if (!modep->fx)
+		return 0;
+
+	if (svid != modep->fx->svid) {
+		CPRINTF("ERR:svid r:0x%04x != c:0x%04x\n", svid,
+			modep->fx->svid);
+		return 0;
+	}
+
+	if (opos != modep->opos) {
+		CPRINTF("ERR:opos r:%d != c:%d\n", opos, modep->opos);
+		return 0;
+	}
+
+	return 1;
+}
+
+void pd_prepare_sysjump(void)
+{
+	int i;
+
+	/* Exit modes before sysjump so we can cleanly enter again later */
+	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+		/*
+		 * If the port is not capable of Alternate mode no need to
+		 * send the event.
+		 */
+		if (!pd_alt_mode_capable(i))
+			continue;
+
+		sysjump_task_waiting = task_get_current();
+		task_set_event(PD_PORT_TO_TASK_ID(i), PD_EVENT_SYSJUMP);
+		task_wait_event_mask(TASK_EVENT_SYSJUMP_READY, -1);
+		sysjump_task_waiting = TASK_ID_INVALID;
+	}
+}
+
+#ifdef CONFIG_USB_PD_DP_MODE
+/*
+ * This algorithm defaults to choosing higher pin config over lower ones in
+ * order to prefer multi-function if desired.
+ *
+ *  NAME | SIGNALING | OUTPUT TYPE | MULTI-FUNCTION | PIN CONFIG
+ * -------------------------------------------------------------
+ *  A    |  USB G2   |  ?          | no             | 00_0001
+ *  B    |  USB G2   |  ?          | yes            | 00_0010
+ *  C    |  DP       |  CONVERTED  | no             | 00_0100
+ *  D    |  PD       |  CONVERTED  | yes            | 00_1000
+ *  E    |  DP       |  DP         | no             | 01_0000
+ *  F    |  PD       |  DP         | yes            | 10_0000
+ *
+ * if UFP has NOT asserted multi-function preferred code masks away B/D/F
+ * leaving only A/C/E.  For single-output dongles that should leave only one
+ * possible pin config depending on whether its a converter DP->(VGA|HDMI) or DP
+ * output.  If UFP is a USB-C receptacle it may assert C/D/E/F.  The DFP USB-C
+ * receptacle must always choose C/D in those cases.
+ */
+int pd_dfp_dp_get_pin_mode(int port, uint32_t status)
+{
+	struct svdm_amode_data *modep =
+		pd_get_amode_data(port, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT);
+	uint32_t mode_caps;
+	uint32_t pin_caps;
+	int mf_pref;
+
+	/*
+	 * Default dp_port_mf_allow is true, we allow mf operation
+	 * if UFP_D supports it.
+	 */
+
+	if (IS_ENABLED(CONFIG_CMD_MFALLOW))
+		mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]) &&
+			  dp_port_mf_allow[port];
+	else
+		mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]);
+
+	if (!modep)
+		return 0;
+
+	mode_caps = modep->data->mode_vdo[modep->opos - 1];
+
+	/* TODO(crosbug.com/p/39656) revisit with DFP that can be a sink */
+	pin_caps = PD_DP_PIN_CAPS(mode_caps);
+
+	/* if don't want multi-function then ignore those pin configs */
+	if (!mf_pref)
+		pin_caps &= ~MODE_DP_PIN_MF_MASK;
+
+	/* TODO(crosbug.com/p/39656) revisit if DFP drives USB Gen 2 signals */
+	pin_caps &= ~MODE_DP_PIN_BR2_MASK;
+
+	/* if C/D present they have precedence over E/F for USB-C->USB-C */
+	if (pin_caps & (MODE_DP_PIN_C | MODE_DP_PIN_D))
+		pin_caps &= ~(MODE_DP_PIN_E | MODE_DP_PIN_F);
+
+	/* get_next_bit returns undefined for zero */
+	if (!pin_caps)
+		return 0;
+
+	return 1 << get_next_bit(&pin_caps);
+}
+#endif /* CONFIG_USB_PD_DP_MODE */
+
+struct svdm_amode_data *pd_get_amode_data(int port, enum tcpci_msg_type type,
+					  uint16_t svid)
+{
+	int idx = pd_get_mode_idx(port, type, svid);
+	struct partner_active_modes *active =
+		pd_get_partner_active_modes(port, type);
+	assert(active);
+
+	return (idx == -1) ? NULL : &active->amodes[idx];
+}
+
+/*
+ * Enter default mode ( payload[0] == 0 ) or attempt to enter mode via svid &
+ * opos
+ */
+uint32_t pd_dfp_enter_mode(int port, enum tcpci_msg_type type, uint16_t svid,
+			   int opos)
+{
+	int mode_idx = pd_allocate_mode(port, type, svid);
+	struct svdm_amode_data *modep;
+	uint32_t mode_caps;
+
+	if (mode_idx == -1)
+		return 0;
+	modep = &pd_get_partner_active_modes(port, type)->amodes[mode_idx];
+
+	if (!opos) {
+		/* choose the lowest as default */
+		modep->opos = 1;
+	} else if (opos <= modep->data->mode_cnt) {
+		modep->opos = opos;
+	} else {
+		CPRINTS("C%d: Invalid opos %d for SVID %x", port, opos, svid);
+		return 0;
+	}
+
+	mode_caps = modep->data->mode_vdo[modep->opos - 1];
+	if (modep->fx->enter(port, mode_caps) == -1)
+		return 0;
+
+	/*
+	 * Strictly speaking, this should only happen when the request
+	 * has been ACKed.
+	 * For TCPMV1, still set modal flag pre-emptively. For TCPMv2, the modal
+	 * flag is set when the ENTER command is ACK'd for each alt mode that is
+	 * supported.
+	 */
+	if (IS_ENABLED(CONFIG_USB_PD_TCPMV1))
+		pd_set_dfp_enter_mode_flag(port, true);
+
+	/* SVDM to send to UFP for mode entry */
+	return VDO(modep->fx->svid, 1, CMD_ENTER_MODE | VDO_OPOS(modep->opos));
+}
+
+int pd_dfp_exit_mode(int port, enum tcpci_msg_type type, uint16_t svid,
+		     int opos)
+{
+	struct svdm_amode_data *modep;
+	struct partner_active_modes *active =
+		pd_get_partner_active_modes(port, type);
+	int idx;
+
+	/*
+	 * Empty svid signals we should reset DFP VDM state by exiting all
+	 * entered modes then clearing state.  This occurs when we've
+	 * disconnected or for hard reset.
+	 */
+	if (!svid) {
+		for (idx = 0; idx < PD_AMODE_COUNT; idx++)
+			if (active->amodes[idx].fx)
+				active->amodes[idx].fx->exit(port);
+
+		pd_dfp_mode_init(port);
+		return 0;
+	}
+
+	/*
+	 * TODO(crosbug.com/p/33946) : below needs revisited to allow multiple
+	 * mode exit.  Additionally it should honor OPOS == 7 as DFP's request
+	 * to exit all modes.  We currently don't have any UFPs that support
+	 * multiple modes on one SVID.
+	 */
+	modep = pd_get_amode_data(port, type, svid);
+	if (!modep || !validate_mode_request(modep, svid, opos))
+		return 0;
+
+	/* call DFPs exit function */
+	modep->fx->exit(port);
+
+	pd_set_dfp_enter_mode_flag(port, false);
+
+	/* exit the mode */
+	modep->opos = 0;
+	return 1;
+}
+
+void dfp_consume_attention(int port, uint32_t *payload)
+{
+	uint16_t svid = PD_VDO_VID(payload[0]);
+	int opos = PD_VDO_OPOS(payload[0]);
+	struct svdm_amode_data *modep =
+		pd_get_amode_data(port, TCPCI_MSG_SOP, svid);
+
+	if (!modep || !validate_mode_request(modep, svid, opos))
+		return;
+
+	if (modep->fx->attention)
+		modep->fx->attention(port, payload);
+}
+
+int pd_alt_mode(int port, enum tcpci_msg_type type, uint16_t svid)
+{
+	struct svdm_amode_data *modep = pd_get_amode_data(port, type, svid);
+
+	return (modep) ? modep->opos : -1;
+}
+
+void notify_sysjump_ready(void)
+{
+	/*
+	 * If event was set from pd_prepare_sysjump, wake the
+	 * task waiting on us to complete.
+	 */
+	if (sysjump_task_waiting != TASK_ID_INVALID)
+		task_set_event(sysjump_task_waiting, TASK_EVENT_SYSJUMP_READY);
+}
+
+#ifdef CONFIG_USB_PD_DP_MODE
+__overridable void svdm_safe_dp_mode(int port)
+{
+	/* make DP interface safe until configure */
+	dp_flags[port] = 0;
+	dp_status[port] = 0;
+
+	usb_mux_set_safe_mode(port);
+}
+
+__overridable int svdm_enter_dp_mode(int port, uint32_t mode_caps)
+{
+	/*
+	 * Don't enter the mode if the SoC is off.
+	 *
+	 * There's no need to enter the mode while the SoC is off; we'll
+	 * actually enter the mode on the chipset resume hook.  Entering DP Alt
+	 * Mode twice will confuse some monitors and require and unplug/replug
+	 * to get them to work again.  The DP Alt Mode on USB-C spec says that
+	 * if we don't need to maintain HPD connectivity info in a low power
+	 * mode, then we shall exit DP Alt Mode.  (This is why we don't enter
+	 * when the SoC is off as opposed to suspend where adding a display
+	 * could cause a wake up.)  When in S5->S3 transition state, we
+	 * should treat it as a SoC off state.
+	 */
+#ifdef CONFIG_AP_POWER_CONTROL
+	if (!chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON))
+		return -1;
+#endif
+
+		/*
+		 * TCPMv2: Enable logging of CCD line state CCD_MODE_ODL.
+		 * DisplayPort Alternate mode requires that the SBU lines are
+		 * used for AUX communication. However, in Chromebooks SBU
+		 * signals are repurposed as USB2 signals for CCD. This
+		 * functionality is accomplished by override fets whose state is
+		 * controlled by CCD_MODE_ODL.
+		 *
+		 * This condition helps in debugging unexpected AUX timeout
+		 * issues by indicating the state of the CCD override fets.
+		 */
+#ifdef GPIO_CCD_MODE_ODL
+	if (!gpio_get_level(GPIO_CCD_MODE_ODL))
+		CPRINTS("WARNING: Tried to EnterMode DP with [CCD on AUX/SBU]");
+#endif
+
+	/* Only enter mode if device is DFP_D capable */
+	if (mode_caps & MODE_DP_SNK) {
+		svdm_safe_dp_mode(port);
+
+		if (IS_ENABLED(CONFIG_MKBP_EVENT) &&
+		    chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
+			/*
+			 * Wake the system up since we're entering DP AltMode.
+			 */
+			pd_notify_dp_alt_mode_entry(port);
+
+		return 0;
+	}
+
+	return -1;
+}
+
+__overridable int svdm_dp_status(int port, uint32_t *payload)
+{
+	int opos = pd_alt_mode(port, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT);
+
+	payload[0] =
+		VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_STATUS | VDO_OPOS(opos));
+	payload[1] = VDO_DP_STATUS(0, /* HPD IRQ  ... not applicable */
+				   0, /* HPD level ... not applicable */
+				   0, /* exit DP? ... no */
+				   0, /* usb mode? ... no */
+				   0, /* multi-function ... no */
+				   (!!(dp_flags[port] & DP_FLAGS_DP_ON)),
+				   0, /* power low? ... no */
+				   (!!DP_FLAGS_DP_ON));
+	return 2;
+};
+
+__overridable uint8_t get_dp_pin_mode(int port)
+{
+	return pd_dfp_dp_get_pin_mode(port, dp_status[port]);
+}
+
+mux_state_t svdm_dp_get_mux_mode(int port)
+{
+	int pin_mode = get_dp_pin_mode(port);
+	/* Default dp_port_mf_allow is true */
+	int mf_pref;
+
+	if (IS_ENABLED(CONFIG_CMD_MFALLOW))
+		mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]) &&
+			  dp_port_mf_allow[port];
+	else
+		mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]);
+
+	/*
+	 * Multi-function operation is only allowed if that pin config is
+	 * supported.
+	 */
+	if ((pin_mode & MODE_DP_PIN_MF_MASK) && mf_pref)
+		return USB_PD_MUX_DOCK;
+	else
+		return USB_PD_MUX_DP_ENABLED;
+}
+
+/* Note: Assumes that pins have already been set in safe state if necessary */
+__overridable int svdm_dp_config(int port, uint32_t *payload)
+{
+	int opos = pd_alt_mode(port, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT);
+	uint8_t pin_mode = get_dp_pin_mode(port);
+	mux_state_t mux_mode = svdm_dp_get_mux_mode(port);
+	/* Default dp_port_mf_allow is true */
+	int mf_pref;
+
+	if (IS_ENABLED(CONFIG_CMD_MFALLOW))
+		mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]) &&
+			  dp_port_mf_allow[port];
+	else
+		mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]);
+
+	if (!pin_mode)
+		return 0;
+
+	CPRINTS("pin_mode: %x, mf: %d, mux: %d", pin_mode, mf_pref, mux_mode);
+
+	payload[0] =
+		VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_CONFIG | VDO_OPOS(opos));
+	payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */
+				1, /* DPv1.3 signaling */
+				2); /* UFP connected */
+	return 2;
+};
+
+#if defined(CONFIG_USB_PD_DP_HPD_GPIO) && \
+	!defined(CONFIG_USB_PD_DP_HPD_GPIO_CUSTOM)
+void svdm_set_hpd_gpio(int port, int en)
+{
+	gpio_set_level(PORT_TO_HPD(port), en);
+}
+
+int svdm_get_hpd_gpio(int port)
+{
+	return gpio_get_level(PORT_TO_HPD(port));
+}
+#endif
+
+__overridable void svdm_dp_post_config(int port)
+{
+	mux_state_t mux_mode = svdm_dp_get_mux_mode(port);
+	/* Connect the SBU and USB lines to the connector. */
+	typec_set_sbu(port, true);
+
+	usb_mux_set(port, mux_mode, USB_SWITCH_CONNECT,
+		    polarity_rm_dts(pd_get_polarity(port)));
+
+	dp_flags[port] |= DP_FLAGS_DP_ON;
+	if (!(dp_flags[port] & DP_FLAGS_HPD_HI_PENDING))
+		return;
+
+#ifdef CONFIG_USB_PD_DP_HPD_GPIO
+	svdm_set_hpd_gpio(port, 1);
+
+	/* set the minimum time delay (2ms) for the next HPD IRQ */
+	svdm_hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
+#endif /* CONFIG_USB_PD_DP_HPD_GPIO */
+
+	usb_mux_hpd_update(port,
+			   USB_PD_MUX_HPD_LVL | USB_PD_MUX_HPD_IRQ_DEASSERTED);
+
+#ifdef USB_PD_PORT_TCPC_MST
+	if (port == USB_PD_PORT_TCPC_MST)
+		baseboard_mst_enable_control(port, 1);
+#endif
+}
+
+__overridable int svdm_dp_attention(int port, uint32_t *payload)
+{
+	int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]);
+	int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]);
+#ifdef CONFIG_USB_PD_DP_HPD_GPIO
+	int cur_lvl = svdm_get_hpd_gpio(port);
+#endif /* CONFIG_USB_PD_DP_HPD_GPIO */
+	mux_state_t mux_state;
+
+	dp_status[port] = payload[1];
+
+	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && (irq || lvl))
+		/*
+		 * Wake up the AP.  IRQ or level high indicates a DP sink is now
+		 * present.
+		 */
+		if (IS_ENABLED(CONFIG_MKBP_EVENT))
+			pd_notify_dp_alt_mode_entry(port);
+
+	/* Its initial DP status message prior to config */
+	if (!(dp_flags[port] & DP_FLAGS_DP_ON)) {
+		if (lvl)
+			dp_flags[port] |= DP_FLAGS_HPD_HI_PENDING;
+		return 1;
+	}
+
+#ifdef CONFIG_USB_PD_DP_HPD_GPIO
+	if (irq && !lvl) {
+		/*
+		 * IRQ can only be generated when the level is high, because
+		 * the IRQ is signaled by a short low pulse from the high level.
+		 */
+		CPRINTF("ERR:HPD:IRQ&LOW\n");
+		return 0; /* nak */
+	}
+
+	if (irq && cur_lvl) {
+		uint64_t now = get_time().val;
+		/* wait for the minimum spacing between IRQ_HPD if needed */
+		if (now < svdm_hpd_deadline[port])
+			usleep(svdm_hpd_deadline[port] - now);
+
+		/* generate IRQ_HPD pulse */
+		svdm_set_hpd_gpio(port, 0);
+		usleep(HPD_DSTREAM_DEBOUNCE_IRQ);
+		svdm_set_hpd_gpio(port, 1);
+	} else {
+		svdm_set_hpd_gpio(port, lvl);
+	}
+
+	/* set the minimum time delay (2ms) for the next HPD IRQ */
+	svdm_hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
+#endif /* CONFIG_USB_PD_DP_HPD_GPIO */
+
+	mux_state = (lvl ? USB_PD_MUX_HPD_LVL : USB_PD_MUX_HPD_LVL_DEASSERTED) |
+		    (irq ? USB_PD_MUX_HPD_IRQ : USB_PD_MUX_HPD_IRQ_DEASSERTED);
+	usb_mux_hpd_update(port, mux_state);
+
+#ifdef USB_PD_PORT_TCPC_MST
+	if (port == USB_PD_PORT_TCPC_MST)
+		baseboard_mst_enable_control(port, lvl);
+#endif
+
+	/* ack */
+	return 1;
+}
+
+__overridable void svdm_exit_dp_mode(int port)
+{
+	dp_flags[port] = 0;
+	dp_status[port] = 0;
+#ifdef CONFIG_USB_PD_DP_HPD_GPIO
+	svdm_set_hpd_gpio(port, 0);
+#endif /* CONFIG_USB_PD_DP_HPD_GPIO */
+	usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
+					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+#ifdef USB_PD_PORT_TCPC_MST
+	if (port == USB_PD_PORT_TCPC_MST)
+		baseboard_mst_enable_control(port, 0);
+#endif
+}
+#endif /* CONFIG_USB_PD_DP_MODE */
+
+__overridable int svdm_enter_gfu_mode(int port, uint32_t mode_caps)
+{
+	/* Always enter GFU mode */
+	return 0;
+}
+
+__overridable void svdm_exit_gfu_mode(int port)
+{
+}
+
+__overridable int svdm_gfu_status(int port, uint32_t *payload)
+{
+	/*
+	 * This is called after enter mode is successful, send unstructured
+	 * VDM to read info.
+	 */
+	pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_READ_INFO, NULL, 0);
+	return 0;
+}
+
+__overridable int svdm_gfu_config(int port, uint32_t *payload)
+{
+	return 0;
+}
+
+__overridable int svdm_gfu_attention(int port, uint32_t *payload)
+{
+	return 0;
+}
+
+const struct svdm_amode_fx supported_modes[] = {
+#ifdef CONFIG_USB_PD_DP_MODE
+	{
+		.svid = USB_SID_DISPLAYPORT,
+		.enter = &svdm_enter_dp_mode,
+		.status = &svdm_dp_status,
+		.config = &svdm_dp_config,
+		.post_config = &svdm_dp_post_config,
+		.attention = &svdm_dp_attention,
+		.exit = &svdm_exit_dp_mode,
+	},
+#endif /* CONFIG_USB_PD_DP_MODE */
+	{
+		.svid = USB_VID_GOOGLE,
+		.enter = &svdm_enter_gfu_mode,
+		.status = &svdm_gfu_status,
+		.config = &svdm_gfu_config,
+		.attention = &svdm_gfu_attention,
+		.exit = &svdm_exit_gfu_mode,
+	},
+};
+const int supported_modes_cnt = ARRAY_SIZE(supported_modes);
+
+#if defined(CONFIG_CMD_MFALLOW)
+static int command_mfallow(int argc, const char **argv)
+{
+	char *e;
+	int port;
+
+	if (argc < 3)
+		return EC_ERROR_PARAM_COUNT;
+
+	port = strtoi(argv[1], &e, 10);
+	if (*e || port >= board_get_usb_pd_port_count())
+		return EC_ERROR_PARAM1;
+
+	if (!strcasecmp(argv[2], "true"))
+		dp_port_mf_allow[port] = true;
+	else if (!strcasecmp(argv[2], "false"))
+		dp_port_mf_allow[port] = false;
+	else
+		return EC_ERROR_PARAM2;
+
+	ccprintf("Port: %d multi function allowed is %s ", port, argv[2]);
+	return EC_SUCCESS;
+}
+
+DECLARE_CONSOLE_COMMAND(mfallow, command_mfallow, "port [true | false]",
+			"Controls Multifunction choice during DP Altmode.");
+#endif /* CONFIG_CMD_MFALLOW */
+
+#ifdef CONFIG_COMMON_RUNTIME
+static enum ec_status hc_remote_pd_dev_info(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_usb_pd_info_request *p = args->params;
+	struct ec_params_usb_pd_rw_hash_entry *r = args->response;
+	uint16_t dev_id;
+	uint32_t current_image;
+
+	if (p->port >= board_get_usb_pd_port_count())
+		return EC_RES_INVALID_PARAM;
+
+	pd_dev_get_rw_hash(p->port, &dev_id, r->dev_rw_hash, &current_image);
+
+	r->dev_id = dev_id;
+	r->current_image = current_image;
+
+	args->response_size = sizeof(*r);
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_USB_PD_DEV_INFO, hc_remote_pd_dev_info,
+		     EC_VER_MASK(0));
+#endif /* CONFIG_COMMON_RUNTIME */
+
+#endif /* CONFIG_USB_PD_ALT_MODE_DFP */
diff --git a/common/usb_pd_protocol.c b/common/usb_pd_protocol.c
index 1fe963f1fc..9179e53be3 100644
--- a/common/usb_pd_protocol.c
+++ b/common/usb_pd_protocol.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,11 +7,13 @@
 #include "battery.h"
 #include "battery_smart.h"
 #include "board.h"
+#include "builtin/assert.h"
 #include "charge_manager.h"
 #include "charge_state.h"
 #include "chipset.h"
 #include "common.h"
 #include "console.h"
+#include "cros_version.h"
 #include "ec_commands.h"
 #include "gpio.h"
 #include "hooks.h"
@@ -20,42 +22,36 @@
 #include "registers.h"
 #include "system.h"
 #include "task.h"
-#include "tcpci.h"
-#include "tcpm.h"
+#include "tcpm/tcpci.h"
+#include "tcpm/tcpm.h"
 #include "timer.h"
-#include "util.h"
+#include "typec_control.h"
 #include "usb_charge.h"
 #include "usb_common.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
-#include "usb_pd_tcpm.h"
+#include "usb_pd_flags.h"
 #include "usb_pd_tcpc.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_ocp.h"
 #include "usbc_ppc.h"
-#include "version.h"
+#include "util.h"
 #include "vboot.h"
 
 /* Flags to clear on a disconnect */
-#define PD_FLAGS_RESET_ON_DISCONNECT_MASK (PD_FLAGS_PARTNER_DR_POWER | \
-					   PD_FLAGS_PARTNER_DR_DATA | \
-					   PD_FLAGS_CHECK_IDENTITY | \
-					   PD_FLAGS_SNK_CAP_RECVD | \
-					   PD_FLAGS_TCPC_DRP_TOGGLE | \
-					   PD_FLAGS_EXPLICIT_CONTRACT | \
-					   PD_FLAGS_PREVIOUS_PD_CONN | \
-					   PD_FLAGS_CHECK_PR_ROLE | \
-					   PD_FLAGS_CHECK_DR_ROLE | \
-					   PD_FLAGS_PARTNER_UNCONSTR | \
-					   PD_FLAGS_VCONN_ON | \
-					   PD_FLAGS_TRY_SRC | \
-					   PD_FLAGS_PARTNER_USB_COMM | \
-					   PD_FLAGS_UPDATE_SRC_CAPS | \
-					   PD_FLAGS_TS_DTS_PARTNER | \
-					   PD_FLAGS_SNK_WAITING_BATT | \
-					   PD_FLAGS_CHECK_VCONN_STATE)
+#define PD_FLAGS_RESET_ON_DISCONNECT_MASK                                   \
+	(PD_FLAGS_PARTNER_DR_POWER | PD_FLAGS_PARTNER_DR_DATA |             \
+	 PD_FLAGS_CHECK_IDENTITY | PD_FLAGS_SNK_CAP_RECVD |                 \
+	 PD_FLAGS_TCPC_DRP_TOGGLE | PD_FLAGS_EXPLICIT_CONTRACT |            \
+	 PD_FLAGS_PREVIOUS_PD_CONN | PD_FLAGS_CHECK_PR_ROLE |               \
+	 PD_FLAGS_CHECK_DR_ROLE | PD_FLAGS_PARTNER_UNCONSTR |               \
+	 PD_FLAGS_VCONN_ON | PD_FLAGS_TRY_SRC | PD_FLAGS_PARTNER_USB_COMM | \
+	 PD_FLAGS_UPDATE_SRC_CAPS | PD_FLAGS_TS_DTS_PARTNER |               \
+	 PD_FLAGS_SNK_WAITING_BATT | PD_FLAGS_CHECK_VCONN_STATE)
 
 #ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 static int tcpc_prints(const char *string, int port)
 {
@@ -102,11 +98,11 @@ static const int debug_level;
 #define DUAL_ROLE_IF_ELSE(port, sink_clause, src_clause) (src_clause)
 #endif
 
-#define READY_RETURN_STATE(port) DUAL_ROLE_IF_ELSE(port, PD_STATE_SNK_READY, \
-							 PD_STATE_SRC_READY)
+#define READY_RETURN_STATE(port) \
+	DUAL_ROLE_IF_ELSE(port, PD_STATE_SNK_READY, PD_STATE_SRC_READY)
 
 /* Type C supply voltage (mV) */
-#define TYPE_C_VOLTAGE	5000 /* mV */
+#define TYPE_C_VOLTAGE 5000 /* mV */
 
 /* PD counter definitions */
 #define PD_MESSAGE_ID_COUNT 7
@@ -150,8 +146,9 @@ enum vdm_states {
 #ifdef CONFIG_USB_PD_DUAL_ROLE
 /* Port dual-role state */
 enum pd_dual_role_states drp_state[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[0 ... (CONFIG_USB_PD_PORT_MAX_COUNT - 1)] =
-		CONFIG_USB_PD_INITIAL_DRP_STATE};
+	[0 ...(CONFIG_USB_PD_PORT_MAX_COUNT - 1)] =
+		CONFIG_USB_PD_INITIAL_DRP_STATE
+};
 
 /* Enable variable for Try.SRC states */
 static bool pd_try_src_enable;
@@ -180,8 +177,7 @@ static bool pd_try_src_enable;
  *  Rev 1 (VDO 1.0) - return VDM_VER10
  *  Rev 2 (VDO 2.0) - return VDM_VER20
  */
-static const uint8_t vdo_ver[] = {
-	VDM_VER10, VDM_VER10, VDM_VER20};
+static const uint8_t vdo_ver[] = { VDM_VER10, VDM_VER10, VDM_VER20 };
 #define VDO_VER(v) vdo_ver[v]
 #else
 #define VDO_VER(v) VDM_VER10
@@ -241,9 +237,9 @@ static struct pd_protocol {
 	/* Time to debounce exit low power mode */
 	uint64_t low_power_exit_time;
 	/* Tasks to notify after TCPC has been reset */
-	int tasks_waiting_on_reset;
+	atomic_t tasks_waiting_on_reset;
 	/* Tasks preventing TCPC from entering low power mode */
-	int tasks_preventing_lpm;
+	atomic_t tasks_preventing_lpm;
 #endif
 
 #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
@@ -267,14 +263,14 @@ static struct pd_protocol {
 	/* next Vendor Defined Message to send */
 	uint32_t vdo_data[VDO_MAX_SIZE];
 	/* type of transmit message (SOP/SOP'/SOP'') */
-	enum tcpm_transmit_type xmit_type;
+	enum tcpci_msg_type xmit_type;
 	uint8_t vdo_count;
 	/* VDO to retry if UFP responder replied busy. */
 	uint32_t vdo_retry;
 
 	/* Attached ChromeOS device id, RW hash, and current RO / RW image */
 	uint16_t dev_id;
-	uint32_t dev_rw_hash[PD_RW_HASH_SIZE/4];
+	uint32_t dev_rw_hash[PD_RW_HASH_SIZE / 4];
 	enum ec_image current_image;
 #ifdef CONFIG_USB_PD_REV30
 	/* protocol revision */
@@ -295,24 +291,46 @@ static struct pd_protocol {
 } pd[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 #ifdef CONFIG_USB_PD_TCPMV1_DEBUG
-static const char * const pd_state_names[] = {
-	"DISABLED", "SUSPENDED",
-	"SNK_DISCONNECTED", "SNK_DISCONNECTED_DEBOUNCE",
+static const char *const pd_state_names[] = {
+	"DISABLED",
+	"SUSPENDED",
+	"SNK_DISCONNECTED",
+	"SNK_DISCONNECTED_DEBOUNCE",
 	"SNK_HARD_RESET_RECOVER",
-	"SNK_DISCOVERY", "SNK_REQUESTED", "SNK_TRANSITION", "SNK_READY",
-	"SNK_SWAP_INIT", "SNK_SWAP_SNK_DISABLE",
-	"SNK_SWAP_SRC_DISABLE", "SNK_SWAP_STANDBY", "SNK_SWAP_COMPLETE",
-	"SRC_DISCONNECTED", "SRC_DISCONNECTED_DEBOUNCE",
-	"SRC_HARD_RESET_RECOVER", "SRC_STARTUP",
-	"SRC_DISCOVERY", "SRC_NEGOCIATE", "SRC_ACCEPTED", "SRC_POWERED",
-	"SRC_TRANSITION", "SRC_READY", "SRC_GET_SNK_CAP", "DR_SWAP",
-	"SRC_SWAP_INIT", "SRC_SWAP_SNK_DISABLE", "SRC_SWAP_SRC_DISABLE",
+	"SNK_DISCOVERY",
+	"SNK_REQUESTED",
+	"SNK_TRANSITION",
+	"SNK_READY",
+	"SNK_SWAP_INIT",
+	"SNK_SWAP_SNK_DISABLE",
+	"SNK_SWAP_SRC_DISABLE",
+	"SNK_SWAP_STANDBY",
+	"SNK_SWAP_COMPLETE",
+	"SRC_DISCONNECTED",
+	"SRC_DISCONNECTED_DEBOUNCE",
+	"SRC_HARD_RESET_RECOVER",
+	"SRC_STARTUP",
+	"SRC_DISCOVERY",
+	"SRC_NEGOCIATE",
+	"SRC_ACCEPTED",
+	"SRC_POWERED",
+	"SRC_TRANSITION",
+	"SRC_READY",
+	"SRC_GET_SNK_CAP",
+	"DR_SWAP",
+	"SRC_SWAP_INIT",
+	"SRC_SWAP_SNK_DISABLE",
+	"SRC_SWAP_SRC_DISABLE",
 	"SRC_SWAP_STANDBY",
-	"VCONN_SWAP_SEND", "VCONN_SWAP_INIT", "VCONN_SWAP_READY",
-	"SOFT_RESET", "HARD_RESET_SEND", "HARD_RESET_EXECUTE", "BIST_RX",
+	"VCONN_SWAP_SEND",
+	"VCONN_SWAP_INIT",
+	"VCONN_SWAP_READY",
+	"SOFT_RESET",
+	"HARD_RESET_SEND",
+	"HARD_RESET_EXECUTE",
+	"BIST_RX",
 	"BIST_TX",
 	"DRP_AUTO_TOGGLE",
-	"ENTER_USB",
 };
 BUILD_ASSERT(ARRAY_SIZE(pd_state_names) == PD_STATE_COUNT);
 #endif
@@ -333,38 +351,31 @@ bool pd_alt_mode_capable(int port)
 	 * the port is not suspended.
 	 */
 	return pd_comm_is_enabled(port) &&
-		!(pd[port].task_state == PD_STATE_SUSPENDED);
+	       !(pd[port].task_state == PD_STATE_SUSPENDED);
 }
 
-static inline void set_state_timeout(int port,
-				     uint64_t timeout,
+static inline void set_state_timeout(int port, uint64_t timeout,
 				     enum pd_states timeout_state)
 {
 	pd[port].timeout = timeout;
 	pd[port].timeout_state = timeout_state;
 }
 
-int pd_get_rev(int port, enum tcpm_transmit_type type)
+int pd_get_rev(int port, enum tcpci_msg_type type)
 {
 #ifdef CONFIG_USB_PD_REV30
 	/* TCPMv1 Only stores PD revision for SOP and SOP' types */
 	ASSERT(type < NUM_SOP_STAR_TYPES - 1);
 
-	if (type == TCPC_TX_SOP_PRIME)
-		return get_usb_pd_cable_revision(port);
-
 	return pd[port].rev;
 #else
 	return PD_REV20;
 #endif
 }
 
-int pd_get_vdo_ver(int port, enum tcpm_transmit_type type)
+int pd_get_vdo_ver(int port, enum tcpci_msg_type type)
 {
 #ifdef CONFIG_USB_PD_REV30
-	if (type == TCPC_TX_SOP_PRIME)
-		return vdo_ver[get_usb_pd_cable_revision(port)];
-
 	return vdo_ver[pd[port].rev];
 #else
 	return VDM_VER10;
@@ -382,22 +393,16 @@ int pd_is_connected(int port)
 		return 0;
 #endif
 
-	return DUAL_ROLE_IF_ELSE(port,
+	return DUAL_ROLE_IF_ELSE(
+		port,
 		/* sink */
 		pd[port].task_state != PD_STATE_SNK_DISCONNECTED &&
-		pd[port].task_state != PD_STATE_SNK_DISCONNECTED_DEBOUNCE,
+			pd[port].task_state !=
+				PD_STATE_SNK_DISCONNECTED_DEBOUNCE,
 		/* source */
 		pd[port].task_state != PD_STATE_SRC_DISCONNECTED &&
-		pd[port].task_state != PD_STATE_SRC_DISCONNECTED_DEBOUNCE);
-}
-
-/*
- * Return true if partner port is a DTS or TS capable of entering debug
- * mode (eg. is presenting Rp/Rp or Rd/Rd).
- */
-int pd_ts_dts_plugged(int port)
-{
-	return pd[port].flags & PD_FLAGS_TS_DTS_PARTNER;
+			pd[port].task_state !=
+				PD_STATE_SRC_DISCONNECTED_DEBOUNCE);
 }
 
 /* Return true if partner port is known to be PD capable. */
@@ -406,6 +411,15 @@ bool pd_capable(int port)
 	return !!(pd[port].flags & PD_FLAGS_PREVIOUS_PD_CONN);
 }
 
+/*
+ * For TCPMv1, this routine always returns false so that the USB3 signals
+ * are connected without delay when the initial connection is UFP.
+ */
+bool pd_waiting_on_partner_src_caps(int port)
+{
+	return false;
+}
+
 /*
  * Return true if partner port is capable of communication over USB data
  * lines.
@@ -422,7 +436,6 @@ void pd_vbus_low(int port)
 }
 #endif
 
-
 #ifdef CONFIG_USBC_VCONN
 static void set_vconn(int port, int enable)
 {
@@ -434,11 +447,17 @@ static void set_vconn(int port, int enable)
 		ppc_set_vconn(port, 0);
 
 	/*
-	 * We always need to tell the TCPC to enable Vconn first, otherwise some
-	 * TCPCs get confused when a PPC sets secondary CC line to 5V and TCPC
-	 * immediately disconnect. If there is a PPC, both devices will
-	 * potentially source Vconn, but that should be okay since Vconn has
-	 * "make before break" electrical requirements when swapping anyway.
+	 * Some TCPCs/PPC combinations can trigger OVP if the TCPC doesn't
+	 * source VCONN. This happens if the TCPC will trip OVP with 5V, and the
+	 * PPC doesn't isolate the TCPC from VCONN when sourcing. But, some PPCs
+	 * which do isolate the TCPC can't handle 5V on its host-side CC pins,
+	 * so the TCPC shouldn't source VCONN in those cases.
+	 *
+	 * In the first case, both TCPC and PPC will potentially source Vconn,
+	 * but that should be okay since Vconn has "make before break"
+	 * electrical requirements when swapping anyway.
+	 *
+	 * See b/72961003 and b/180973460
 	 */
 	tcpm_set_vconn(port, enable);
 
@@ -476,12 +495,12 @@ static void handle_device_access(int port)
 	pd[port].low_power_time = get_time().val + PD_LPM_DEBOUNCE_US;
 	if (pd[port].flags & PD_FLAGS_LPM_ENGAGED) {
 		tcpc_prints("Exit Low Power Mode", port);
-		pd[port].flags &= ~(PD_FLAGS_LPM_ENGAGED |
-				    PD_FLAGS_LPM_REQUESTED);
+		pd[port].flags &=
+			~(PD_FLAGS_LPM_ENGAGED | PD_FLAGS_LPM_REQUESTED);
 		pd[port].flags |= PD_FLAGS_LPM_EXIT;
 
-		pd[port].low_power_exit_time = get_time().val
-			+ PD_LPM_EXIT_DEBOUNCE_US;
+		pd[port].low_power_exit_time =
+			get_time().val + PD_LPM_EXIT_DEBOUNCE_US;
 		/*
 		 * Wake to ensure we make another pass through the main task
 		 * loop after clearing the flags.
@@ -531,11 +550,10 @@ static int reset_device_and_notify(int port)
 	 * waking the TCPC, but it has also set PD_EVENT_TCPC_RESET again, which
 	 * would result in a second, unnecessary init.
 	 */
-	deprecated_atomic_clear_bits(task_get_event_bitmap(task_get_current()),
-				     PD_EVENT_TCPC_RESET);
+	atomic_clear_bits(task_get_event_bitmap(task_get_current()),
+			  PD_EVENT_TCPC_RESET);
 
-	waiting_tasks =
-		deprecated_atomic_read_clear(&pd[port].tasks_waiting_on_reset);
+	waiting_tasks = atomic_clear(&pd[port].tasks_waiting_on_reset);
 
 	/*
 	 * Now that we are done waking up the device, handle device access
@@ -550,7 +568,7 @@ static int reset_device_and_notify(int port)
 	while (waiting_tasks) {
 		task = __fls(waiting_tasks);
 		waiting_tasks &= ~BIT(task);
-		task_set_event(task, TASK_EVENT_PD_AWAKE, 0);
+		task_set_event(task, TASK_EVENT_PD_AWAKE);
 	}
 
 	return rv;
@@ -563,8 +581,8 @@ static void pd_wait_for_wakeup(int port)
 		reset_device_and_notify(port);
 	} else {
 		/* Otherwise, we need to wait for the TCPC reset to complete */
-		deprecated_atomic_or(&pd[port].tasks_waiting_on_reset,
-				     1 << task_get_current());
+		atomic_or(&pd[port].tasks_waiting_on_reset,
+			  1 << task_get_current());
 		/*
 		 * NOTE: We could be sending the PD task the reset event while
 		 * it is already processing the reset event. If that occurs,
@@ -573,8 +591,7 @@ static void pd_wait_for_wakeup(int port)
 		 * happen much, but it if starts occurring, we can add a guard
 		 * to prevent/reduce it.
 		 */
-		task_set_event(PD_PORT_TO_TASK_ID(port),
-			       PD_EVENT_TCPC_RESET, 0);
+		task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_TCPC_RESET);
 		task_wait_event_mask(TASK_EVENT_PD_AWAKE, -1);
 	}
 }
@@ -599,7 +616,7 @@ void pd_device_accessed(int port)
 		handle_device_access(port);
 	} else {
 		task_set_event(PD_PORT_TO_TASK_ID(port),
-			       PD_EVENT_DEVICE_ACCESSED, 0);
+			       PD_EVENT_DEVICE_ACCESSED);
 	}
 }
 
@@ -608,11 +625,10 @@ void pd_prevent_low_power_mode(int port, int prevent)
 	const int current_task_mask = (1 << task_get_current());
 
 	if (prevent)
-		deprecated_atomic_or(&pd[port].tasks_preventing_lpm,
-				     current_task_mask);
+		atomic_or(&pd[port].tasks_preventing_lpm, current_task_mask);
 	else
-		deprecated_atomic_clear_bits(&pd[port].tasks_preventing_lpm,
-					     current_task_mask);
+		atomic_clear_bits(&pd[port].tasks_preventing_lpm,
+				  current_task_mask);
 }
 
 /* This is only called from the PD tasks that owns the port. */
@@ -669,28 +685,18 @@ static bool consume_sop_repeat_message(int port, uint8_t msg_id)
  * @param port USB PD TCPC port number
  * @param msg_header Message Header containing the RX message ID
  * @return True if the received message is a duplicate one, False otherwise.
- *
- * From USB PD version 1.3 section 6.7.1, the port which communicates
- * using SOP* Packets Shall maintain copies of the last MessageID for
- * each type of SOP* it uses.
  */
 static bool consume_repeat_message(int port, uint32_t msg_header)
 {
 	uint8_t msg_id = PD_HEADER_ID(msg_header);
-	enum tcpm_transmit_type sop = PD_HEADER_GET_SOP(msg_header);
 
 	/* If repeat message ignore, except softreset control request. */
 	if (PD_HEADER_TYPE(msg_header) == PD_CTRL_SOFT_RESET &&
 	    PD_HEADER_CNT(msg_header) == 0) {
 		return false;
-	} else if (sop == TCPC_TX_SOP_PRIME) {
-		return consume_sop_prime_repeat_msg(port, msg_id);
-	} else if (sop == TCPC_TX_SOP_PRIME_PRIME) {
-		return consume_sop_prime_prime_repeat_msg(port, msg_id);
 	} else {
 		return consume_sop_repeat_message(port, msg_id);
 	}
-
 }
 
 /**
@@ -718,14 +724,18 @@ static inline void set_state(int port, enum pd_states next_state)
 #if defined(CONFIG_USBC_PPC) && defined(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE)
 	/* If we're entering DRP_AUTO_TOGGLE, there is no sink connected. */
 	if (next_state == PD_STATE_DRP_AUTO_TOGGLE) {
-		ppc_sink_is_connected(port, 0);
-		/*
-		 * Clear the overcurrent event counter
-		 * since we've detected a disconnect.
-		 */
-		ppc_clear_oc_event_counter(port);
+		ppc_dev_is_connected(port, PPC_DEV_DISCONNECTED);
 		/* Disable Auto Discharge Disconnect */
 		tcpm_enable_auto_discharge_disconnect(port, 0);
+
+		if (IS_ENABLED(CONFIG_USBC_OCP)) {
+			usbc_ocp_snk_is_connected(port, false);
+			/*
+			 * Clear the overcurrent event counter
+			 * since we've detected a disconnect.
+			 */
+			usbc_ocp_clear_event_counter(port);
+		}
 	}
 #endif /* CONFIG_USBC_PPC &&  CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE */
 
@@ -754,17 +764,22 @@ static inline void set_state(int port, enum pd_states next_state)
 		tcpm_get_cc(port, &cc1, &cc2);
 		/*
 		 * Neither a debug accessory nor UFP attached.
-		 * Tell the PPC module that there is no sink connected.
+		 * Tell the PPC module that there is no device connected.
 		 */
 		if (!cc_is_at_least_one_rd(cc1, cc2)) {
-			ppc_sink_is_connected(port, 0);
-			/*
-			 * Clear the overcurrent event counter
-			 * since we've detected a disconnect.
-			 */
-			ppc_clear_oc_event_counter(port);
+			ppc_dev_is_connected(port, PPC_DEV_DISCONNECTED);
+
+			if (IS_ENABLED(CONFIG_USBC_OCP)) {
+				usbc_ocp_snk_is_connected(port, false);
+				/*
+				 * Clear the overcurrent event counter
+				 * since we've detected a disconnect.
+				 */
+				usbc_ocp_clear_event_counter(port);
+			}
 		}
 #endif /* CONFIG_USBC_PPC */
+
 		/* Clear the holdoff timer since the port is disconnected. */
 		pd[port].ready_state_holdoff_timer = 0;
 
@@ -776,15 +791,13 @@ static inline void set_state(int port, enum pd_states next_state)
 		if (last_state != PD_STATE_SNK_DISCONNECTED_DEBOUNCE &&
 		    last_state != PD_STATE_SRC_DISCONNECTED_DEBOUNCE) {
 			pd[port].flags &= ~PD_FLAGS_RESET_ON_DISCONNECT_MASK;
-			reset_pd_cable(port);
 		}
 
 		/* Clear the input current limit */
 		pd_set_input_current_limit(port, 0, 0);
 #ifdef CONFIG_CHARGE_MANAGER
 		typec_set_input_current_limit(port, 0, 0);
-		charge_manager_set_ceil(port,
-					CEIL_REQUESTOR_PD,
+		charge_manager_set_ceil(port, CEIL_REQUESTOR_PD,
 					CHARGE_CEIL_NONE);
 #endif
 #ifdef CONFIG_BC12_DETECT_DATA_ROLE_TRIGGER
@@ -793,8 +806,7 @@ static inline void set_state(int port, enum pd_states next_state)
 		 * detach events are used to notify BC1.2 that it can be powered
 		 * down.
 		 */
-		task_set_event(USB_CHG_PORT_TO_TASK_ID(port),
-			       USB_CHG_EVENT_CC_OPEN, 0);
+		usb_charger_task_set_event(port, USB_CHG_EVENT_CC_OPEN);
 #endif /* CONFIG_BC12_DETECT_DATA_ROLE_TRIGGER */
 #ifdef CONFIG_USBC_VCONN
 		set_vconn(port, 0);
@@ -822,7 +834,8 @@ static inline void set_state(int port, enum pd_states next_state)
 		charge_manager_update_dualrole(port, CAP_UNKNOWN);
 #endif
 #ifdef CONFIG_USB_PD_ALT_MODE_DFP
-		pd_dfp_exit_mode(port, TCPC_TX_SOP, 0, 0);
+		if (pd_dfp_exit_mode(port, TCPCI_MSG_SOP, 0, 0))
+			usb_mux_set_safe_mode(port);
 #endif
 		/*
 		 * Indicate that the port is disconnected by setting role to
@@ -853,7 +866,7 @@ static inline void set_state(int port, enum pd_states next_state)
 	/* Upon entering SRC_READY, it is safe for the sink to transmit */
 	if (next_state == PD_STATE_SRC_READY) {
 		if (pd[port].rev == PD_REV30 &&
-			pd[port].flags & PD_FLAGS_EXPLICIT_CONTRACT)
+		    pd[port].flags & PD_FLAGS_EXPLICIT_CONTRACT)
 			sink_can_xmit(port, SINK_TX_OK);
 	}
 #endif
@@ -873,7 +886,7 @@ static inline void set_state(int port, enum pd_states next_state)
 #ifdef CONFIG_USB_PD_TCPMV1_DEBUG
 	if (debug_level > 0)
 		CPRINTF("C%d st%d %s\n", port, next_state,
-					 pd_state_names[next_state]);
+			pd_state_names[next_state]);
 	else
 #endif
 		CPRINTF("C%d st%d\n", port, next_state);
@@ -891,11 +904,11 @@ void pd_transmit_complete(int port, int status)
 		inc_id(port);
 
 	pd[port].tx_status = status;
-	task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_TX, 0);
+	task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_TX);
 }
 
-static int pd_transmit(int port, enum tcpm_transmit_type type,
-		       uint16_t header, const uint32_t *data, enum ams_seq ams)
+static int pd_transmit(int port, enum tcpci_msg_type type, uint16_t header,
+		       const uint32_t *data, enum ams_seq ams)
 {
 	int evt;
 	int res;
@@ -907,9 +920,9 @@ static int pd_transmit(int port, enum tcpm_transmit_type type,
 	if (!pd_comm_is_enabled(port))
 		return -1;
 
-	 /* Don't try to transmit anything until we have processed
-	  * all RX messages.
-	  */
+	/* Don't try to transmit anything until we have processed
+	 * all RX messages.
+	 */
 	if (tcpm_has_pending_message(port))
 		return -1;
 
@@ -936,7 +949,7 @@ static int pd_transmit(int port, enum tcpm_transmit_type type,
 	 * Note: a Sink can still send Hard Reset signaling at any time.
 	 */
 	if ((pd[port].rev == PD_REV30) && ams == AMS_START &&
-		(pd[port].flags & PD_FLAGS_EXPLICIT_CONTRACT)) {
+	    (pd[port].flags & PD_FLAGS_EXPLICIT_CONTRACT)) {
 		if (pd[port].power_role == PD_ROLE_SOURCE) {
 			/*
 			 * Inform Sink that it can't transmit. If a sink
@@ -947,12 +960,12 @@ static int pd_transmit(int port, enum tcpm_transmit_type type,
 			 */
 			sink_can_xmit(port, SINK_TX_NG);
 			sink_ng = 1;
-		} else if (type != TCPC_TX_HARD_RESET) {
+		} else if (type != TCPCI_MSG_TX_HARD_RESET) {
 			enum tcpc_cc_voltage_status cc1, cc2;
 
 			tcpm_get_cc(port, &cc1, &cc2);
 			if (cc1 == TYPEC_CC_VOLT_RP_1_5 ||
-				cc2 == TYPEC_CC_VOLT_RP_1_5) {
+			    cc2 == TYPEC_CC_VOLT_RP_1_5) {
 				/* Sink can't transmit now. */
 				/* Return failure, pd_task can retry later */
 				return -1;
@@ -989,17 +1002,17 @@ static int send_control(int port, int type)
 {
 	int bit_len;
 	uint16_t header = PD_HEADER(type, pd[port].power_role,
-				pd[port].data_role, pd[port].msg_id, 0,
-				pd_get_rev(port, TCPC_TX_SOP), 0);
+				    pd[port].data_role, pd[port].msg_id, 0,
+				    pd_get_rev(port, TCPCI_MSG_SOP), 0);
 	/*
 	 * For PD 3.0, collision avoidance logic needs to know if this message
 	 * will begin a new Atomic Message Sequence (AMS)
 	 */
-	enum ams_seq ams = ((1 << type) & PD_CTRL_AMS_START_MASK)
-			    ? AMS_START : AMS_RESPONSE;
+	enum ams_seq ams = ((1 << type) & PD_CTRL_AMS_START_MASK) ?
+				   AMS_START :
+				   AMS_RESPONSE;
 
-
-	bit_len = pd_transmit(port, TCPC_TX_SOP, header, NULL, ams);
+	bit_len = pd_transmit(port, TCPCI_MSG_SOP, header, NULL, ams);
 	if (debug_level >= 2)
 		CPRINTF("C%d CTRL[%d]>%d\n", port, type, bit_len);
 
@@ -1015,7 +1028,7 @@ static int send_source_cap(int port, enum ams_seq ams)
 {
 	int bit_len;
 #if defined(CONFIG_USB_PD_DYNAMIC_SRC_CAP) || \
-		defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT)
+	defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT)
 	const uint32_t *src_pdo;
 	const int src_pdo_cnt = charge_manager_get_source_pdo(&src_pdo, port);
 #else
@@ -1027,14 +1040,15 @@ static int send_source_cap(int port, enum ams_seq ams)
 	if (src_pdo_cnt == 0)
 		/* No source capabilities defined, sink only */
 		header = PD_HEADER(PD_CTRL_REJECT, pd[port].power_role,
-			pd[port].data_role, pd[port].msg_id, 0,
-			pd_get_rev(port, TCPC_TX_SOP), 0);
+				   pd[port].data_role, pd[port].msg_id, 0,
+				   pd_get_rev(port, TCPCI_MSG_SOP), 0);
 	else
 		header = PD_HEADER(PD_DATA_SOURCE_CAP, pd[port].power_role,
-			pd[port].data_role, pd[port].msg_id, src_pdo_cnt,
-			pd_get_rev(port, TCPC_TX_SOP), 0);
+				   pd[port].data_role, pd[port].msg_id,
+				   src_pdo_cnt, pd_get_rev(port, TCPCI_MSG_SOP),
+				   0);
 
-	bit_len = pd_transmit(port, TCPC_TX_SOP, header, src_pdo, ams);
+	bit_len = pd_transmit(port, TCPCI_MSG_SOP, header, src_pdo, ams);
 	if (debug_level >= 2)
 		CPRINTF("C%d srcCAP>%d\n", port, bit_len);
 
@@ -1045,21 +1059,19 @@ static int send_source_cap(int port, enum ams_seq ams)
 static int send_battery_cap(int port, uint32_t *payload)
 {
 	int bit_len;
-	uint16_t msg[6] = {0, 0, 0, 0, 0, 0};
-	uint16_t header = PD_HEADER(PD_EXT_BATTERY_CAP,
-				    pd[port].power_role,
-				    pd[port].data_role,
-				    pd[port].msg_id,
+	uint16_t msg[6] = { 0, 0, 0, 0, 0, 0 };
+	uint16_t header = PD_HEADER(PD_EXT_BATTERY_CAP, pd[port].power_role,
+				    pd[port].data_role, pd[port].msg_id,
 				    3, /* Number of Data Objects */
-				    pd[port].rev,
-				    1  /* This is an exteded message */
-				   );
+				    pd[port].rev, 1 /* This is an exteded
+						       message */
+	);
 
 	/* Set extended header */
 	msg[0] = PD_EXT_HEADER(0, /* Chunk Number */
 			       0, /* Request Chunk */
-			       9  /* Data Size in bytes */
-			      );
+			       9 /* Data Size in bytes */
+	);
 	/* Set VID */
 	msg[1] = USB_VID_GOOGLE;
 
@@ -1106,7 +1118,7 @@ static int send_battery_cap(int port, uint32_t *payload)
 					 * 10th of a Wh = Wh * 10
 					 */
 					msg[3] = DIV_ROUND_NEAREST((c * v),
-								100000);
+								   100000);
 				}
 
 				if (battery_full_charge_capacity(&c) == 0) {
@@ -1115,31 +1127,29 @@ static int send_battery_cap(int port, uint32_t *payload)
 					 * 10th of a Wh = Wh * 10
 					 */
 					msg[4] = DIV_ROUND_NEAREST((c * v),
-								100000);
+								   100000);
 				}
 			}
 		}
 	}
 
-	bit_len = pd_transmit(port, TCPC_TX_SOP, header, (uint32_t *)msg,
+	bit_len = pd_transmit(port, TCPCI_MSG_SOP, header, (uint32_t *)msg,
 			      AMS_RESPONSE);
 	if (debug_level >= 2)
 		CPRINTF("C%d batCap>%d\n", port, bit_len);
 	return bit_len;
 }
 
-static int send_battery_status(int port,  uint32_t *payload)
+static int send_battery_status(int port, uint32_t *payload)
 {
 	int bit_len;
 	uint32_t msg = 0;
-	uint16_t header = PD_HEADER(PD_DATA_BATTERY_STATUS,
-				    pd[port].power_role,
-				    pd[port].data_role,
-				    pd[port].msg_id,
+	uint16_t header = PD_HEADER(PD_DATA_BATTERY_STATUS, pd[port].power_role,
+				    pd[port].data_role, pd[port].msg_id,
 				    1, /* Number of Data Objects */
-				    pd[port].rev,
-				    0 /* This is NOT an extended message */
-				  );
+				    pd[port].rev, 0 /* This is NOT an extended
+						       message */
+	);
 
 	if (battery_is_present()) {
 		/*
@@ -1154,15 +1164,15 @@ static int send_battery_status(int port,  uint32_t *payload)
 			uint32_t c;
 
 			if (battery_design_voltage(&v) != 0 ||
-					battery_remaining_capacity(&c) != 0) {
+			    battery_remaining_capacity(&c) != 0) {
 				msg |= BSDO_CAP(BSDO_CAP_UNKNOWN);
 			} else {
 				/*
 				 * Wh = (c * v) / 1000000
 				 * 10th of a Wh = Wh * 10
 				 */
-				msg |= BSDO_CAP(DIV_ROUND_NEAREST((c * v),
-								100000));
+				msg |= BSDO_CAP(
+					DIV_ROUND_NEAREST((c * v), 100000));
 			}
 
 			/* Battery is present */
@@ -1189,7 +1199,7 @@ static int send_battery_status(int port,  uint32_t *payload)
 		msg = BSDO_CAP(BSDO_CAP_UNKNOWN);
 	}
 
-	bit_len = pd_transmit(port, TCPC_TX_SOP, header, &msg, AMS_RESPONSE);
+	bit_len = pd_transmit(port, TCPCI_MSG_SOP, header, &msg, AMS_RESPONSE);
 	if (debug_level >= 2)
 		CPRINTF("C%d batStat>%d\n", port, bit_len);
 
@@ -1202,10 +1212,11 @@ static void send_sink_cap(int port)
 {
 	int bit_len;
 	uint16_t header = PD_HEADER(PD_DATA_SINK_CAP, pd[port].power_role,
-			pd[port].data_role, pd[port].msg_id, pd_snk_pdo_cnt,
-			pd_get_rev(port, TCPC_TX_SOP), 0);
+				    pd[port].data_role, pd[port].msg_id,
+				    pd_snk_pdo_cnt,
+				    pd_get_rev(port, TCPCI_MSG_SOP), 0);
 
-	bit_len = pd_transmit(port, TCPC_TX_SOP, header, pd_snk_pdo,
+	bit_len = pd_transmit(port, TCPCI_MSG_SOP, header, pd_snk_pdo,
 			      AMS_RESPONSE);
 	if (debug_level >= 2)
 		CPRINTF("C%d snkCAP>%d\n", port, bit_len);
@@ -1215,11 +1226,11 @@ static int send_request(int port, uint32_t rdo)
 {
 	int bit_len;
 	uint16_t header = PD_HEADER(PD_DATA_REQUEST, pd[port].power_role,
-			pd[port].data_role, pd[port].msg_id, 1,
-			pd_get_rev(port, TCPC_TX_SOP), 0);
+				    pd[port].data_role, pd[port].msg_id, 1,
+				    pd_get_rev(port, TCPCI_MSG_SOP), 0);
 
 	/* Note: ams will need to be AMS_START if used for PPS keep alive */
-	bit_len = pd_transmit(port, TCPC_TX_SOP, header, &rdo, AMS_RESPONSE);
+	bit_len = pd_transmit(port, TCPCI_MSG_SOP, header, &rdo, AMS_RESPONSE);
 	if (debug_level >= 2)
 		CPRINTF("C%d REQ>%d\n", port, bit_len);
 
@@ -1235,10 +1246,10 @@ static int send_bist_cmd(int port)
 	uint32_t bdo = BDO(BDO_MODE_CARRIER2, 0);
 	int bit_len;
 	uint16_t header = PD_HEADER(PD_DATA_BIST, pd[port].power_role,
-			pd[port].data_role, pd[port].msg_id, 1,
-			pd_get_rev(port, TCPC_TX_SOP), 0);
+				    pd[port].data_role, pd[port].msg_id, 1,
+				    pd_get_rev(port, TCPCI_MSG_SOP), 0);
 
-	bit_len = pd_transmit(port, TCPC_TX_SOP, header, &bdo, AMS_START);
+	bit_len = pd_transmit(port, TCPCI_MSG_SOP, header, &bdo, AMS_START);
 	CPRINTF("C%d BIST>%d\n", port, bit_len);
 
 	return bit_len;
@@ -1246,32 +1257,97 @@ static int send_bist_cmd(int port)
 #endif
 
 static void queue_vdm(int port, uint32_t *header, const uint32_t *data,
-			     int data_cnt, enum tcpm_transmit_type type)
+		      int data_cnt, enum tcpci_msg_type type)
 {
 	pd[port].vdo_count = data_cnt + 1;
 	pd[port].vdo_data[0] = header[0];
 	pd[port].xmit_type = type;
-	memcpy(&pd[port].vdo_data[1], data,
-		sizeof(uint32_t) * data_cnt);
+	memcpy(&pd[port].vdo_data[1], data, sizeof(uint32_t) * data_cnt);
 	/* Set ready, pd task will actually send */
 	pd[port].vdm_state = VDM_STATE_READY;
 }
 
+/* ----------------- Vendor Defined Messages ------------------ */
+__overridable int pd_custom_vdm(int port, int cnt, uint32_t *payload,
+				uint32_t **rpayload)
+{
+	int cmd = PD_VDO_CMD(payload[0]);
+	uint16_t dev_id = 0;
+	int is_rw, is_latest;
+
+	/* make sure we have some payload */
+	if (cnt == 0)
+		return 0;
+
+	/* Only handle custom requests for SVID Google */
+	if (PD_VDO_VID(*payload) != USB_VID_GOOGLE)
+		return 0;
+
+	switch (cmd) {
+	case VDO_CMD_VERSION:
+		/* guarantee last byte of payload is null character */
+		*(payload + cnt - 1) = 0;
+		CPRINTF("version: %s\n", (char *)(payload + 1));
+		break;
+	case VDO_CMD_READ_INFO:
+	case VDO_CMD_SEND_INFO:
+		/* copy hash */
+		if (cnt == 7) {
+			dev_id = VDO_INFO_HW_DEV_ID(payload[6]);
+			is_rw = VDO_INFO_IS_RW(payload[6]);
+
+			is_latest = pd_dev_store_rw_hash(
+				port, dev_id, payload + 1,
+				is_rw ? EC_IMAGE_RW : EC_IMAGE_RO);
+
+			/*
+			 * Send update host event unless our RW hash is
+			 * already known to be the latest update RW.
+			 */
+			if (!is_rw || !is_latest)
+				pd_send_host_event(PD_EVENT_UPDATE_DEVICE);
+
+			CPRINTF("DevId:%d.%d SW:%d RW:%d\n",
+				HW_DEV_ID_MAJ(dev_id), HW_DEV_ID_MIN(dev_id),
+				VDO_INFO_SW_DBG_VER(payload[6]), is_rw);
+		} else if (cnt == 6) {
+			/* really old devices don't have last byte */
+			pd_dev_store_rw_hash(port, dev_id, payload + 1,
+					     EC_IMAGE_UNKNOWN);
+		}
+		break;
+	case VDO_CMD_CURRENT:
+		CPRINTF("Current: %dmA\n", payload[1]);
+		break;
+	case VDO_CMD_FLIP:
+		if (IS_ENABLED(CONFIG_USBC_SS_MUX))
+			usb_mux_flip(port);
+		break;
+#ifdef CONFIG_USB_PD_LOGGING
+	case VDO_CMD_GET_LOG:
+		pd_log_recv_vdm(port, cnt, payload);
+		break;
+#endif /* CONFIG_USB_PD_LOGGING */
+	}
+
+	return 0;
+}
+
 static void handle_vdm_request(int port, int cnt, uint32_t *payload,
-				uint32_t head)
+			       uint32_t head)
 {
 	int rlen = 0;
 	uint32_t *rdata;
-	enum tcpm_transmit_type rtype = TCPC_TX_SOP;
+	enum tcpci_msg_type rtype = TCPCI_MSG_SOP;
 
 	if (pd[port].vdm_state == VDM_STATE_BUSY) {
 		/* If UFP responded busy retry after timeout */
 		if (PD_VDO_CMDT(payload[0]) == CMDT_RSP_BUSY) {
-			pd[port].vdm_timeout.val = get_time().val +
-				PD_T_VDM_BUSY;
+			pd[port].vdm_timeout.val =
+				get_time().val + PD_T_VDM_BUSY;
 			pd[port].vdm_state = VDM_STATE_WAIT_RSP_BUSY;
 			pd[port].vdo_retry = (payload[0] & ~VDO_CMDT_MASK) |
-				CMDT_INIT;
+					     CMDT_INIT;
 			return;
 		} else {
 			pd[port].vdm_state = VDM_STATE_DONE;
@@ -1295,8 +1371,8 @@ static void handle_vdm_request(int port, int cnt, uint32_t *payload,
 	}
 
 	if (debug_level >= 2)
-		CPRINTF("C%d Unhandled VDM VID %04x CMD %04x\n",
-			port, PD_VDO_VID(payload[0]), payload[0] & 0xFFFF);
+		CPRINTF("C%d Unhandled VDM VID %04x CMD %04x\n", port,
+			PD_VDO_VID(payload[0]), payload[0] & 0xFFFF);
 }
 
 bool pd_is_disconnected(int port)
@@ -1325,11 +1401,9 @@ static void pd_set_data_role(int port, enum pd_data_role role)
 	 * task and indicate the current data role.
 	 */
 	if (role == PD_ROLE_UFP)
-		task_set_event(USB_CHG_PORT_TO_TASK_ID(port),
-			       USB_CHG_EVENT_DR_UFP, 0);
+		usb_charger_task_set_event(port, USB_CHG_EVENT_DR_UFP);
 	else if (role == PD_ROLE_DFP)
-		task_set_event(USB_CHG_PORT_TO_TASK_ID(port),
-			       USB_CHG_EVENT_DR_DFP, 0);
+		usb_charger_task_set_event(port, USB_CHG_EVENT_DR_DFP);
 #endif /* CONFIG_BC12_DETECT_DATA_ROLE_TRIGGER */
 }
 
@@ -1357,7 +1431,8 @@ void pd_execute_hard_reset(int port)
 	invalidate_last_message_id(port);
 	tcpm_set_rx_enable(port, 0);
 #ifdef CONFIG_USB_PD_ALT_MODE_DFP
-	pd_dfp_exit_mode(port, TCPC_TX_SOP, 0, 0);
+	if (pd_dfp_exit_mode(port, TCPCI_MSG_SOP, 0, 0))
+		usb_mux_set_safe_mode(port);
 #endif
 
 #ifdef CONFIG_USB_PD_REV30
@@ -1387,8 +1462,7 @@ void pd_execute_hard_reset(int port)
 		/* Clear the input current limit */
 		pd_set_input_current_limit(port, 0, 0);
 #ifdef CONFIG_CHARGE_MANAGER
-		charge_manager_set_ceil(port,
-					CEIL_REQUESTOR_PD,
+		charge_manager_set_ceil(port, CEIL_REQUESTOR_PD,
 					CHARGE_CEIL_NONE);
 #endif /* CONFIG_CHARGE_MANAGER */
 
@@ -1428,7 +1502,7 @@ static void execute_soft_reset(int port)
 {
 	invalidate_last_message_id(port);
 	set_state(port, DUAL_ROLE_IF_ELSE(port, PD_STATE_SNK_DISCOVERY,
-						PD_STATE_SRC_DISCOVERY));
+					  PD_STATE_SRC_DISCOVERY));
 	CPRINTF("C%d Soft Rst\n", port);
 }
 
@@ -1470,8 +1544,8 @@ static int pd_send_request_msg(int port, int always_send_request)
 #endif
 	}
 
-	CPRINTF("C%d Req [%d] %dmV %dmA", port, RDO_POS(rdo),
-		supply_voltage, curr_limit);
+	CPRINTF("C%d Req [%d] %dmV %dmA", port, RDO_POS(rdo), supply_voltage,
+		curr_limit);
 	if (rdo & RDO_CAP_MISMATCH)
 		CPRINTF(" Mismatch");
 	CPRINTF("\n");
@@ -1487,63 +1561,62 @@ static int pd_send_request_msg(int port, int always_send_request)
 }
 #endif
 
-static void pd_update_pdo_flags(int port, uint32_t pdo)
+static void pd_update_pdo_flags(int port, int pdo_cnt, uint32_t *pdos)
 {
-#ifdef CONFIG_CHARGE_MANAGER
-#ifdef CONFIG_USB_PD_ALT_MODE_DFP
-	int charge_allowlisted =
-		(pd[port].power_role == PD_ROLE_SINK &&
-		 pd_charge_from_device(pd_get_identity_vid(port),
-				       pd_get_identity_pid(port)));
-#else
-	const int charge_allowlisted = 0;
-#endif
-#endif
-
 	/* can only parse PDO flags if type is fixed */
-	if ((pdo & PDO_TYPE_MASK) != PDO_TYPE_FIXED)
+	if ((pdos[0] & PDO_TYPE_MASK) != PDO_TYPE_FIXED)
 		return;
 
 #ifdef CONFIG_USB_PD_DUAL_ROLE
-	if (pdo & PDO_FIXED_DUAL_ROLE)
+	if (pdos[0] & PDO_FIXED_DUAL_ROLE)
 		pd[port].flags |= PD_FLAGS_PARTNER_DR_POWER;
 	else
 		pd[port].flags &= ~PD_FLAGS_PARTNER_DR_POWER;
 
-	if (pdo & PDO_FIXED_UNCONSTRAINED)
+	if (pdos[0] & PDO_FIXED_UNCONSTRAINED)
 		pd[port].flags |= PD_FLAGS_PARTNER_UNCONSTR;
 	else
 		pd[port].flags &= ~PD_FLAGS_PARTNER_UNCONSTR;
 
-	if (pdo & PDO_FIXED_COMM_CAP)
+	if (pdos[0] & PDO_FIXED_COMM_CAP)
 		pd[port].flags |= PD_FLAGS_PARTNER_USB_COMM;
 	else
 		pd[port].flags &= ~PD_FLAGS_PARTNER_USB_COMM;
 #endif
 
-	if (pdo & PDO_FIXED_DATA_SWAP)
+	if (pdos[0] & PDO_FIXED_DATA_SWAP)
 		pd[port].flags |= PD_FLAGS_PARTNER_DR_DATA;
 	else
 		pd[port].flags &= ~PD_FLAGS_PARTNER_DR_DATA;
 
-#ifdef CONFIG_CHARGE_MANAGER
 	/*
 	 * Treat device as a dedicated charger (meaning we should charge
-	 * from it) if it does not support power swap, or has unconstrained
-	 * power, or if we are a sink and the device identity matches a
-	 * charging allow-list.
+	 * from it) if:
+	 *   - it does not support power swap, or
+	 *   - it is unconstrained power, or
+	 *   - it presents at least 27 W of available power
 	 */
-	if (!(pd[port].flags & PD_FLAGS_PARTNER_DR_POWER) ||
-	    (pd[port].flags & PD_FLAGS_PARTNER_UNCONSTR) ||
-	    charge_allowlisted)
-		charge_manager_update_dualrole(port, CAP_DEDICATED);
-	else
-		charge_manager_update_dualrole(port, CAP_DUALROLE);
-#endif
+	if (IS_ENABLED(CONFIG_CHARGE_MANAGER)) {
+		uint32_t max_ma, max_mv, max_pdo, max_mw, unused;
+
+		/*
+		 * Get max power that the partner offers (not necessarily what
+		 * this board will request)
+		 */
+		pd_find_pdo_index(pdo_cnt, pdos, PD_REV3_MAX_VOLTAGE, &max_pdo);
+		pd_extract_pdo_power(max_pdo, &max_ma, &max_mv, &unused);
+		max_mw = max_ma * max_mv / 1000;
+
+		if (!(pdos[0] & PDO_FIXED_DUAL_ROLE) ||
+		    (pdos[0] & PDO_FIXED_UNCONSTRAINED) ||
+		    max_mw >= PD_DRP_CHARGE_POWER_MIN)
+			charge_manager_update_dualrole(port, CAP_DEDICATED);
+		else
+			charge_manager_update_dualrole(port, CAP_DUALROLE);
+	}
 }
 
-static void handle_data_request(int port, uint32_t head,
-		uint32_t *payload)
+static void handle_data_request(int port, uint32_t head, uint32_t *payload)
 {
 	int type = PD_HEADER_TYPE(head);
 	int cnt = PD_HEADER_CNT(head);
@@ -1551,14 +1624,12 @@ static void handle_data_request(int port, uint32_t head,
 	switch (type) {
 #ifdef CONFIG_USB_PD_DUAL_ROLE
 	case PD_DATA_SOURCE_CAP:
-		if ((pd[port].task_state == PD_STATE_SNK_DISCOVERY)
-			|| (pd[port].task_state == PD_STATE_SNK_TRANSITION)
-			|| (pd[port].task_state == PD_STATE_SNK_REQUESTED)
-#ifdef CONFIG_USB_PD_VBUS_DETECT_NONE
-			|| (pd[port].task_state ==
-			    PD_STATE_SNK_HARD_RESET_RECOVER)
-#endif
-			|| (pd[port].task_state == PD_STATE_SNK_READY)) {
+		if ((pd[port].task_state == PD_STATE_SNK_DISCOVERY) ||
+		    (pd[port].task_state == PD_STATE_SNK_TRANSITION) ||
+		    (pd[port].task_state == PD_STATE_SNK_REQUESTED) ||
+		    ((get_usb_pd_vbus_detect() == USB_PD_VBUS_DETECT_NONE) &&
+		     (pd[port].task_state == PD_STATE_SNK_HARD_RESET_RECOVER)) ||
+		    (pd[port].task_state == PD_STATE_SNK_READY)) {
 #ifdef CONFIG_USB_PD_REV30
 			/*
 			 * Only adjust sink rev if source rev is higher.
@@ -1570,7 +1641,7 @@ static void handle_data_request(int port, uint32_t head,
 			pd[port].flags |= PD_FLAGS_PREVIOUS_PD_CONN;
 
 			/* src cap 0 should be fixed PDO */
-			pd_update_pdo_flags(port, payload[0]);
+			pd_update_pdo_flags(port, cnt, payload);
 
 			pd_process_source_cap(port, cnt, payload);
 
@@ -1615,37 +1686,33 @@ static void handle_data_request(int port, uint32_t head,
 		break;
 	case PD_DATA_BIST:
 		/* If not in READY state, then don't start BIST */
-		if (DUAL_ROLE_IF_ELSE(port,
-				pd[port].task_state == PD_STATE_SNK_READY,
-				pd[port].task_state == PD_STATE_SRC_READY)) {
+		if (DUAL_ROLE_IF_ELSE(
+			    port, pd[port].task_state == PD_STATE_SNK_READY,
+			    pd[port].task_state == PD_STATE_SRC_READY)) {
 			/* currently only support sending bist carrier mode 2 */
 			if ((payload[0] >> 28) == 5) {
 				/* bist data object mode is 2 */
-				pd_transmit(port, TCPC_TX_BIST_MODE_2, 0,
+				pd_transmit(port, TCPCI_MSG_TX_BIST_MODE_2, 0,
 					    NULL, AMS_RESPONSE);
 				/* Set to appropriate port disconnected state */
-				set_state(port, DUAL_ROLE_IF_ELSE(port,
-						PD_STATE_SNK_DISCONNECTED,
-						PD_STATE_SRC_DISCONNECTED));
+				set_state(port,
+					  DUAL_ROLE_IF_ELSE(
+						  port,
+						  PD_STATE_SNK_DISCONNECTED,
+						  PD_STATE_SRC_DISCONNECTED));
 			}
 		}
 		break;
 	case PD_DATA_SINK_CAP:
 		pd[port].flags |= PD_FLAGS_SNK_CAP_RECVD;
 		/* snk cap 0 should be fixed PDO */
-		pd_update_pdo_flags(port, payload[0]);
+		pd_update_pdo_flags(port, cnt, payload);
 		if (pd[port].task_state == PD_STATE_SRC_GET_SINK_CAP)
 			set_state(port, PD_STATE_SRC_READY);
 		break;
 #ifdef CONFIG_USB_PD_REV30
 	case PD_DATA_BATTERY_STATUS:
 		break;
-	/* TODO : Add case PD_DATA_RESET for exiting USB4 */
-
-	/*
-	 * TODO : Add case PD_DATA_ENTER_USB to accept or reject
-	 * Enter_USB request from port partner.
-	 */
 #endif
 	case PD_DATA_VENDOR_DEF:
 		handle_vdm_request(port, cnt, payload, head);
@@ -1690,9 +1757,8 @@ void pd_try_vconn_src(int port)
 
 void pd_request_data_swap(int port)
 {
-	if (DUAL_ROLE_IF_ELSE(port,
-				pd[port].task_state == PD_STATE_SNK_READY,
-				pd[port].task_state == PD_STATE_SRC_READY))
+	if (DUAL_ROLE_IF_ELSE(port, pd[port].task_state == PD_STATE_SNK_READY,
+			      pd[port].task_state == PD_STATE_SRC_READY))
 		set_state(port, PD_STATE_DR_SWAP);
 	task_wake(PD_PORT_TO_TASK_ID(port));
 }
@@ -1711,8 +1777,7 @@ static void pd_dr_swap(int port)
 	pd[port].flags |= PD_FLAGS_CHECK_IDENTITY;
 }
 
-static void handle_ctrl_request(int port, uint32_t head,
-		uint32_t *payload)
+static void handle_ctrl_request(int port, uint32_t head, uint32_t *payload)
 {
 	int type = PD_HEADER_TYPE(head);
 	int res;
@@ -1753,7 +1818,7 @@ static void handle_ctrl_request(int port, uint32_t head,
 			 * later time.
 			 */
 			pd_snk_give_back(port, &pd[port].curr_limit,
-				&pd[port].supply_voltage);
+					 &pd[port].supply_voltage);
 			set_state(port, PD_STATE_SNK_TRANSITION);
 		}
 #endif
@@ -1798,37 +1863,21 @@ static void handle_ctrl_request(int port, uint32_t head,
 			 */
 			if (pd[port].task_state == PD_STATE_SNK_TRANSITION)
 				pd[port].ready_state_holdoff_timer =
-					get_time().val + SNK_READY_HOLD_OFF_US
-					+ (get_time().le.lo & 0xf) * 12 * MSEC;
+					get_time().val + SNK_READY_HOLD_OFF_US +
+					(get_time().le.lo & 0xf) * 12 * MSEC;
 
 			set_state(port, PD_STATE_SNK_READY);
 			pd_set_input_current_limit(port, pd[port].curr_limit,
 						   pd[port].supply_voltage);
 #ifdef CONFIG_CHARGE_MANAGER
 			/* Set ceiling based on what's negotiated */
-			charge_manager_set_ceil(port,
-						CEIL_REQUESTOR_PD,
+			charge_manager_set_ceil(port, CEIL_REQUESTOR_PD,
 						pd[port].curr_limit);
 #endif
 		}
 		break;
 #endif
 	case PD_CTRL_REJECT:
-		if (pd[port].task_state == PD_STATE_ENTER_USB) {
-			if (!IS_ENABLED(CONFIG_USBC_SS_MUX))
-				break;
-
-			/*
-			 * Since Enter USB sets the mux state to SAFE mode,
-			 * resetting the mux state back to USB mode on
-			 * recieveing a NACK.
-			 */
-			usb_mux_set(port, USB_PD_MUX_USB_ENABLED,
-				USB_SWITCH_CONNECT, pd[port].polarity);
-
-			set_state(port, READY_RETURN_STATE(port));
-			break;
-		}
 	case PD_CTRL_WAIT:
 		if (pd[port].task_state == PD_STATE_DR_SWAP) {
 			if (type == PD_CTRL_WAIT) /* try again ... */
@@ -1883,28 +1932,15 @@ static void handle_ctrl_request(int port, uint32_t head,
 				const int in_contract =
 					pd[port].flags &
 					PD_FLAGS_EXPLICIT_CONTRACT;
-				set_state(port,
-					  in_contract ? PD_STATE_SNK_READY
-						      : PD_STATE_SNK_DISCOVERY);
+				set_state(port, in_contract ?
+							PD_STATE_SNK_READY :
+							PD_STATE_SNK_DISCOVERY);
 			}
 		}
 #endif
 		break;
 	case PD_CTRL_ACCEPT:
-		if (pd[port].task_state == PD_STATE_ENTER_USB) {
-			if (!IS_ENABLED(CONFIG_USBC_SS_MUX))
-				break;
-
-			/* Connect the SBU and USB lines to the connector */
-			if (IS_ENABLED(CONFIG_USBC_PPC_SBU))
-				ppc_set_sbu(port, 1);
-
-			/* Set usb mux to USB4 mode */
-			usb_mux_set(port, USB_PD_MUX_USB4_ENABLED,
-				USB_SWITCH_CONNECT, pd[port].polarity);
-
-			set_state(port, READY_RETURN_STATE(port));
-		} else if (pd[port].task_state == PD_STATE_SOFT_RESET) {
+		if (pd[port].task_state == PD_STATE_SOFT_RESET) {
 			/*
 			 * For the case that we sent soft reset in SNK_DISCOVERY
 			 * on startup due to VBUS never low, clear the flag.
@@ -1924,23 +1960,20 @@ static void handle_ctrl_request(int port, uint32_t head,
 		} else if (pd[port].task_state == PD_STATE_SRC_SWAP_INIT) {
 			/* explicit contract goes away for power swap */
 			pd[port].flags &= ~PD_FLAGS_EXPLICIT_CONTRACT;
-			pd_update_saved_port_flags(port,
-						   PD_BBRMFLG_EXPLICIT_CONTRACT,
-						   0);
+			pd_update_saved_port_flags(
+				port, PD_BBRMFLG_EXPLICIT_CONTRACT, 0);
 			set_state(port, PD_STATE_SRC_SWAP_SNK_DISABLE);
 		} else if (pd[port].task_state == PD_STATE_SNK_SWAP_INIT) {
 			/* explicit contract goes away for power swap */
 			pd[port].flags &= ~PD_FLAGS_EXPLICIT_CONTRACT;
-			pd_update_saved_port_flags(port,
-						   PD_BBRMFLG_EXPLICIT_CONTRACT,
-						   0);
+			pd_update_saved_port_flags(
+				port, PD_BBRMFLG_EXPLICIT_CONTRACT, 0);
 			set_state(port, PD_STATE_SNK_SWAP_SNK_DISABLE);
 		} else if (pd[port].task_state == PD_STATE_SNK_REQUESTED) {
 			/* explicit contract is now in place */
 			pd[port].flags |= PD_FLAGS_EXPLICIT_CONTRACT;
-			pd_update_saved_port_flags(port,
-						   PD_BBRMFLG_EXPLICIT_CONTRACT,
-						   1);
+			pd_update_saved_port_flags(
+				port, PD_BBRMFLG_EXPLICIT_CONTRACT, 1);
 			set_state(port, PD_STATE_SNK_TRANSITION);
 #endif
 		}
@@ -1961,9 +1994,9 @@ static void handle_ctrl_request(int port, uint32_t head,
 			 */
 			pd[port].flags &= ~PD_FLAGS_CHECK_PR_ROLE;
 			set_state(port,
-				  DUAL_ROLE_IF_ELSE(port,
-					PD_STATE_SNK_SWAP_SNK_DISABLE,
-					PD_STATE_SRC_SWAP_SNK_DISABLE));
+				  DUAL_ROLE_IF_ELSE(
+					  port, PD_STATE_SNK_SWAP_SNK_DISABLE,
+					  PD_STATE_SRC_SWAP_SNK_DISABLE));
 		} else {
 			send_control(port, PD_CTRL_REJECT);
 		}
@@ -1983,7 +2016,6 @@ static void handle_ctrl_request(int port, uint32_t head,
 				pd_dr_swap(port);
 		} else {
 			send_control(port, PD_CTRL_REJECT);
-
 		}
 		break;
 	case PD_CTRL_VCONN_SWAP:
@@ -2030,8 +2062,7 @@ static void handle_ext_request(int port, uint16_t head, uint32_t *payload)
 }
 #endif
 
-static void handle_request(int port, uint32_t head,
-		uint32_t *payload)
+static void handle_request(int port, uint32_t head, uint32_t *payload)
 {
 	int cnt = PD_HEADER_CNT(head);
 	int data_role = PD_HEADER_DROLE(head);
@@ -2076,8 +2107,7 @@ static void handle_request(int port, uint32_t head,
 							    TYPEC_CC_RP));
 		}
 		set_state(port,
-			  DUAL_ROLE_IF_ELSE(port,
-					    PD_STATE_SNK_DISCONNECTED,
+			  DUAL_ROLE_IF_ELSE(port, PD_STATE_SNK_DISCONNECTED,
 					    PD_STATE_SRC_DISCONNECTED));
 		return;
 	}
@@ -2104,12 +2134,15 @@ void pd_send_vdm(int port, uint32_t vid, int cmd, const uint32_t *data,
 	}
 
 	/* set VDM header with VID & CMD */
-	pd[port].vdo_data[0] = VDO(vid, ((vid & USB_SID_PD) == USB_SID_PD) ?
-				   1 : (PD_VDO_CMD(cmd) <= CMD_ATTENTION), cmd);
+	pd[port].vdo_data[0] = VDO(vid,
+				   ((vid & USB_SID_PD) == USB_SID_PD) ?
+					   1 :
+					   (PD_VDO_CMD(cmd) <= CMD_ATTENTION),
+				   cmd);
 #ifdef CONFIG_USB_PD_REV30
 	pd[port].vdo_data[0] |= VDO_SVDM_VERS(vdo_ver[pd[port].rev]);
 #endif
-	queue_vdm(port, pd[port].vdo_data, data, count, TCPC_TX_SOP);
+	queue_vdm(port, pd[port].vdo_data, data, count, TCPCI_MSG_SOP);
 
 	task_wake(PD_PORT_TO_TASK_ID(port));
 }
@@ -2135,7 +2168,7 @@ static uint64_t vdm_get_ready_timeout(uint32_t vdm_hdr)
 
 	/* its not a structured VDM command */
 	if (!PD_VDO_SVDM(vdm_hdr))
-		return 500*MSEC;
+		return 500 * MSEC;
 
 	switch (PD_VDO_CMDT(vdm_hdr)) {
 	case CMDT_INIT:
@@ -2154,48 +2187,10 @@ static uint64_t vdm_get_ready_timeout(uint32_t vdm_hdr)
 	return timeout;
 }
 
-static void exit_tbt_mode_sop_prime(int port)
-{
-	/* Exit Thunderbolt-Compatible mode SOP' */
-	uint16_t header;
-	int opos;
-
-	if (!IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE))
-		return;
-
-	opos = pd_alt_mode(port, TCPC_TX_SOP, USB_VID_INTEL);
-	if (opos <= 0)
-		return;
-
-	CPRINTS("C%d Cable exiting TBT Compat mode", port);
-	/*
-	 * Note: TCPMv2 contemplates separate discovery structures for each SOP
-	 * type. TCPMv1 only uses one discovery structure, so all accesses
-	 * specify TCPC_TX_SOP.
-	 */
-	if (!pd_dfp_exit_mode(port, TCPC_TX_SOP, USB_VID_INTEL, opos))
-		return;
-
-	header = PD_HEADER(PD_DATA_VENDOR_DEF, pd[port].power_role,
-			pd[port].data_role, pd[port].msg_id,
-			(int)pd[port].vdo_count,
-			pd_get_rev(port, TCPC_TX_SOP), 0);
-
-	pd[port].vdo_data[0] = VDO(USB_VID_INTEL, 1,
-				   CMD_EXIT_MODE | VDO_OPOS(opos));
-
-	pd_transmit(port, TCPC_TX_SOP_PRIME, header, pd[port].vdo_data,
-		    AMS_START);
-
-	usb_mux_set(port, USB_PD_MUX_USB_ENABLED, USB_SWITCH_CONNECT,
-		   pd_get_polarity(port));
-}
-
 static void pd_vdm_send_state_machine(int port)
 {
 	int res;
 	uint16_t header;
-	enum tcpm_transmit_type msg_type = pd[port].xmit_type;
 
 	switch (pd[port].vdm_state) {
 	case VDM_STATE_READY:
@@ -2212,82 +2207,20 @@ static void pd_vdm_send_state_machine(int port)
 		if (pdo_busy(port))
 			break;
 
-		/*
-		 * To communicate with the cable plug, an explicit contract
-		 * should be established, VCONN should be enabled and data role
-		 * that can communicate with the cable plug should be in place.
-		 * For USB3.0, UFP/DFP can communicate whereas in case of
-		 * USB2.0 only DFP can talk to the cable plug.
-		 *
-		 * For communication between USB2.0 UFP and cable plug,
-		 * data role swap takes place during source and sink
-		 * negotiation and in case of failure, a soft reset is issued.
-		 */
-		if ((msg_type == TCPC_TX_SOP_PRIME) ||
-		    (msg_type == TCPC_TX_SOP_PRIME_PRIME)) {
-			/* Prepare SOP'/SOP'' header and send VDM */
-			header = PD_HEADER(
-				PD_DATA_VENDOR_DEF,
-				PD_PLUG_FROM_DFP_UFP,
-				0,
-				pd[port].msg_id,
-				(int)pd[port].vdo_count,
-				pd_get_rev(port, TCPC_TX_SOP),
-				0);
-			res = pd_transmit(port, msg_type, header,
-					  pd[port].vdo_data, AMS_START);
-			/*
-			 * In the case of SOP', if there is no response from
-			 * the cable, it's a non-emark cable and therefore the
-			 * pd flow should continue irrespective of cable
-			 * response, sending discover_identity so the pd flow
-			 * remains intact.
-			 *
-			 * In the case of SOP'', if there is no response from
-			 * the cable, exit Thunderbolt-Compatible mode
-			 * discovery, reset the mux state since, the mux will
-			 * be set to a safe state before entering
-			 * Thunderbolt-Compatible mode and enter the default
-			 * mode.
-			 */
-			if (res < 0) {
-				header = PD_HEADER(PD_DATA_VENDOR_DEF,
-						   pd[port].power_role,
-						   pd[port].data_role,
-						   pd[port].msg_id,
-						   (int)pd[port].vdo_count,
-						   pd_get_rev
-							(port, TCPC_TX_SOP),
-						   0);
-
-				if ((msg_type == TCPC_TX_SOP_PRIME_PRIME) &&
-				     IS_ENABLED(CONFIG_USBC_SS_MUX)) {
-					exit_tbt_mode_sop_prime(port);
-				} else if (msg_type == TCPC_TX_SOP_PRIME) {
-					pd[port].vdo_data[0] = VDO(USB_SID_PD,
-						1, CMD_DISCOVER_SVID);
-				}
-				res = pd_transmit(port, TCPC_TX_SOP, header,
-						  pd[port].vdo_data, AMS_START);
-				reset_pd_cable(port);
-			}
-		} else {
-			/* Prepare SOP header and send VDM */
-			header = PD_HEADER(PD_DATA_VENDOR_DEF,
-					   pd[port].power_role,
-					   pd[port].data_role,
-					   pd[port].msg_id,
-					   (int)pd[port].vdo_count,
-					   pd_get_rev(port, TCPC_TX_SOP), 0);
-			res = pd_transmit(port, TCPC_TX_SOP, header,
-					  pd[port].vdo_data, AMS_START);
-		}
+		/* Prepare SOP header and send VDM */
+		header = PD_HEADER(PD_DATA_VENDOR_DEF, pd[port].power_role,
+				   pd[port].data_role, pd[port].msg_id,
+				   (int)pd[port].vdo_count,
+				   pd_get_rev(port, TCPCI_MSG_SOP), 0);
+		res = pd_transmit(port, TCPCI_MSG_SOP, header,
+				  pd[port].vdo_data, AMS_START);
 
 		if (res < 0) {
 			pd[port].vdm_state = VDM_STATE_ERR_SEND;
 		} else {
 			pd[port].vdm_state = VDM_STATE_BUSY;
-			pd[port].vdm_timeout.val = get_time().val +
+			pd[port].vdm_timeout.val =
+				get_time().val +
 				vdm_get_ready_timeout(pd[port].vdo_data[0]);
 		}
 		break;
@@ -2349,15 +2282,14 @@ int pd_dev_store_rw_hash(int port, uint16_t dev_id, uint32_t *rw_hash,
 	/* Search table for matching device / hash */
 	for (i = 0; i < RW_HASH_ENTRIES; i++)
 		if (dev_id == rw_hash_table[i].dev_id)
-			return !memcmp(rw_hash,
-				       rw_hash_table[i].dev_rw_hash,
+			return !memcmp(rw_hash, rw_hash_table[i].dev_rw_hash,
 				       PD_RW_HASH_SIZE);
 #endif
 	return 0;
 }
 
 void pd_dev_get_rw_hash(int port, uint16_t *dev_id, uint8_t *rw_hash,
-			 uint32_t *current_image)
+			uint32_t *current_image)
 {
 	*dev_id = pd[port].dev_id;
 	*current_image = pd[port].current_image;
@@ -2373,14 +2305,15 @@ __maybe_unused static void exit_supported_alt_mode(int port)
 		return;
 
 	for (i = 0; i < supported_modes_cnt; i++) {
-		int opos = pd_alt_mode(port, TCPC_TX_SOP,
-				supported_modes[i].svid);
+		int opos = pd_alt_mode(port, TCPCI_MSG_SOP,
+				       supported_modes[i].svid);
 
 		if (opos > 0 &&
-		    pd_dfp_exit_mode(
-			    port, TCPC_TX_SOP, supported_modes[i].svid, opos)) {
+		    pd_dfp_exit_mode(port, TCPCI_MSG_SOP,
+				     supported_modes[i].svid, opos)) {
 			CPRINTS("C%d Exiting ALT mode with SVID = 0x%x", port,
 				supported_modes[i].svid);
+			usb_mux_set_safe_mode(port);
 			pd_send_vdm(port, supported_modes[i].svid,
 				    CMD_EXIT_MODE | VDO_OPOS(opos), NULL, 0);
 			/* Wait for an ACK from port-partner */
@@ -2389,10 +2322,9 @@ __maybe_unused static void exit_supported_alt_mode(int port)
 	}
 }
 
-#ifdef CONFIG_POWER_COMMON
+#ifdef CONFIG_AP_POWER_CONTROL
 static void handle_new_power_state(int port)
 {
-
 	if (chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF)) {
 		/*
 		 * The SoC will negotiate the alternate mode again when
@@ -2409,7 +2341,7 @@ static void handle_new_power_state(int port)
 	/* Ensure mux is set properly after chipset transition */
 	set_usb_mux_with_current_data_role(port);
 }
-#endif /* CONFIG_POWER_COMMON */
+#endif /* CONFIG_AP_POWER_CONTROL */
 
 #ifdef CONFIG_USB_PD_DUAL_ROLE
 enum pd_dual_role_states pd_get_dual_role(int port)
@@ -2456,8 +2388,8 @@ static void pd_update_snk_reset(void)
 
 			if (pd[i].task_state == PD_STATE_SNK_DISCOVERY) {
 				CPRINTS("C%d: Starting soft reset timer", i);
-				set_state_timeout(i,
-					get_time().val + PD_T_SINK_WAIT_CAP,
+				set_state_timeout(
+					i, get_time().val + PD_T_SINK_WAIT_CAP,
 					PD_STATE_SOFT_RESET);
 			}
 		}
@@ -2495,8 +2427,19 @@ void pd_set_dual_role(int port, enum pd_dual_role_states state)
 	pd_set_dual_role_no_wakeup(port, state);
 
 	/* Wake task up to process change */
-	task_set_event(PD_PORT_TO_TASK_ID(port),
-		       PD_EVENT_UPDATE_DUAL_ROLE, 0);
+	task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_UPDATE_DUAL_ROLE);
+}
+
+static int pd_is_power_swapping(int port)
+{
+	/* return true if in the act of swapping power roles */
+	return pd[port].task_state == PD_STATE_SNK_SWAP_SNK_DISABLE ||
+	       pd[port].task_state == PD_STATE_SNK_SWAP_SRC_DISABLE ||
+	       pd[port].task_state == PD_STATE_SNK_SWAP_STANDBY ||
+	       pd[port].task_state == PD_STATE_SNK_SWAP_COMPLETE ||
+	       pd[port].task_state == PD_STATE_SRC_SWAP_SNK_DISABLE ||
+	       pd[port].task_state == PD_STATE_SRC_SWAP_SRC_DISABLE ||
+	       pd[port].task_state == PD_STATE_SRC_SWAP_STANDBY;
 }
 
 /* This must only be called from the PD task */
@@ -2504,14 +2447,13 @@ static void pd_update_dual_role_config(int port)
 {
 	/*
 	 * Change to sink if port is currently a source AND (new DRP
-	 * state is force sink OR new DRP state is either toggle off
-	 * or debug accessory toggle only and we are in the source
-	 * disconnected state).
+	 * state is force sink OR new DRP state is toggle off and we are in the
+	 * source disconnected state).
 	 */
 	if (pd[port].power_role == PD_ROLE_SOURCE &&
-	    ((drp_state[port] == PD_DRP_FORCE_SINK && !pd_ts_dts_plugged(port))
-	     || (drp_state[port] == PD_DRP_TOGGLE_OFF
-		 && pd[port].task_state == PD_STATE_SRC_DISCONNECTED))) {
+	    (drp_state[port] == PD_DRP_FORCE_SINK ||
+	     (drp_state[port] == PD_DRP_TOGGLE_OFF &&
+	      pd[port].task_state == PD_STATE_SRC_DISCONNECTED))) {
 		pd_set_power_role(port, PD_ROLE_SINK);
 		set_state(port, PD_STATE_SNK_DISCONNECTED);
 		tcpm_set_cc(port, TYPEC_CC_RD);
@@ -2521,28 +2463,20 @@ static void pd_update_dual_role_config(int port)
 
 	/*
 	 * Change to source if port is currently a sink and the
-	 * new DRP state is force source.
+	 * new DRP state is force source. If we are performing
+	 * power swap we won't change anything because
+	 * changing state will disrupt power swap process
+	 * and we are power swapping to desired power role.
 	 */
 	if (pd[port].power_role == PD_ROLE_SINK &&
-	    drp_state[port] == PD_DRP_FORCE_SOURCE) {
+	    drp_state[port] == PD_DRP_FORCE_SOURCE &&
+	    !pd_is_power_swapping(port)) {
 		pd_set_power_role(port, PD_ROLE_SOURCE);
 		set_state(port, PD_STATE_SRC_DISCONNECTED);
 		tcpm_set_cc(port, TYPEC_CC_RP);
 	}
 }
 
-static int pd_is_power_swapping(int port)
-{
-	/* return true if in the act of swapping power roles */
-	return  pd[port].task_state == PD_STATE_SNK_SWAP_SNK_DISABLE ||
-		pd[port].task_state == PD_STATE_SNK_SWAP_SRC_DISABLE ||
-		pd[port].task_state == PD_STATE_SNK_SWAP_STANDBY ||
-		pd[port].task_state == PD_STATE_SNK_SWAP_COMPLETE ||
-		pd[port].task_state == PD_STATE_SRC_SWAP_SNK_DISABLE ||
-		pd[port].task_state == PD_STATE_SRC_SWAP_SRC_DISABLE ||
-		pd[port].task_state == PD_STATE_SRC_SWAP_STANDBY;
-}
-
 /*
  * Provide Rp to ensure the partner port is in a known state (eg. not
  * PD negotiated, not sourcing 20V).
@@ -2613,6 +2547,18 @@ uint8_t pd_get_task_state(int port)
 	return pd[port].task_state;
 }
 
+#ifdef CONFIG_USB_PD_DUAL_ROLE
+uint32_t pd_get_requested_voltage(int port)
+{
+	return pd[port].supply_voltage;
+}
+
+uint32_t pd_get_requested_current(int port)
+{
+	return pd[port].curr_limit;
+}
+#endif
+
 const char *pd_get_task_state_name(int port)
 {
 #ifdef CONFIG_USB_PD_TCPMV1_DEBUG
@@ -2664,8 +2610,7 @@ void pd_comm_enable(int port, int enable)
 	 * any port in PD_SNK_DISCOVERY.
 	 */
 	if (enable && pd[port].task_state == PD_STATE_SNK_DISCOVERY)
-		set_state_timeout(port,
-				  get_time().val + PD_T_SINK_WAIT_CAP,
+		set_state_timeout(port, get_time().val + PD_T_SINK_WAIT_CAP,
 				  PD_STATE_HARD_RESET_SEND);
 #endif
 }
@@ -2723,7 +2668,7 @@ static void pd_init_tasks(void)
 	if (initialized)
 		return;
 
-#if defined(HAS_TASK_CHIPSET) && defined(CONFIG_USB_PD_DUAL_ROLE)
+#if defined(CONFIG_AP_POWER_CONTROL) && defined(CONFIG_USB_PD_DUAL_ROLE)
 	/* Set dual-role state based on chipset power state */
 	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
 		for (i = 0; i < board_get_usb_pd_port_count(); i++)
@@ -2763,56 +2708,12 @@ static int pd_restart_tcpc(int port)
 }
 #endif
 
-static void pd_send_enter_usb(int port, int *timeout)
-{
-	uint32_t usb4_payload;
-	uint16_t header;
-	int res;
-
-	/*
-	 * TODO: Enable Enter USB for cables (SOP').
-	 * This is needed for active cables
-	 */
-	if (!IS_ENABLED(CONFIG_USBC_SS_MUX) ||
-	    !IS_ENABLED(CONFIG_USB_PD_USB4) ||
-	    !IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP))
-		return;
-
-	usb4_payload = get_enter_usb_msg_payload(port);
-
-	header = PD_HEADER(PD_DATA_ENTER_USB,
-		pd[port].power_role,
-		pd[port].data_role,
-		pd[port].msg_id,
-		1,
-		PD_REV30,
-		0);
-
-	res = pd_transmit(port, TCPC_TX_SOP, header, &usb4_payload, AMS_START);
-	if (res < 0) {
-		*timeout = 10*MSEC;
-		/*
-		 * If failed to get goodCRC, send soft reset, otherwise ignore
-		 * failure.
-		 */
-		set_state(port, res == -1 ?
-			   PD_STATE_SOFT_RESET :
-			   READY_RETURN_STATE(port));
-		return;
-	}
-
-	/* Disable Enter USB4 mode prevent re-entry */
-	disable_enter_usb4_mode(port);
-
-	set_state(port, PD_STATE_ENTER_USB);
-}
-
 void pd_task(void *u)
 {
 	uint32_t head;
 	int port = TASK_ID_TO_PD_PORT(task_get_current());
 	uint32_t payload[7];
-	int timeout = 10*MSEC;
+	int timeout = 10 * MSEC;
 	enum tcpc_cc_voltage_status cc1, cc2;
 	int res, incoming_packet = 0;
 	int hard_reset_count = 0;
@@ -2890,8 +2791,7 @@ void pd_task(void *u)
 	if (!res) {
 		struct ec_response_pd_chip_info_v1 info;
 
-		if (tcpm_get_chip_info(port, 0, &info) ==
-		    EC_SUCCESS) {
+		if (tcpm_get_chip_info(port, 0, &info) == EC_SUCCESS) {
 			CPRINTS("TCPC p%d VID:0x%x PID:0x%x DID:0x%x "
 				"FWV:0x%" PRIx64,
 				port, info.vendor_id, info.product_id,
@@ -2911,8 +2811,8 @@ void pd_task(void *u)
 	 * present. This flag is used to maintain a PD connection after a
 	 * reset by sending a soft reset.
 	 */
-	pd[port].flags |=
-		pd_is_vbus_present(port) ? PD_FLAGS_VBUS_NEVER_LOW : 0;
+	pd[port].flags |= pd_is_vbus_present(port) ? PD_FLAGS_VBUS_NEVER_LOW :
+						     0;
 #endif
 
 	/* Disable TCPC RX until connection is established */
@@ -2936,14 +2836,17 @@ void pd_task(void *u)
 		if ((saved_flgs & PD_BBRMFLG_POWER_ROLE) == PD_ROLE_SINK) {
 			pd_set_power_role(port,
 					  (saved_flgs & PD_BBRMFLG_POWER_ROLE) ?
-					  PD_ROLE_SOURCE : PD_ROLE_SINK);
+						  PD_ROLE_SOURCE :
+						  PD_ROLE_SINK);
 			pd_set_data_role(port,
 					 (saved_flgs & PD_BBRMFLG_DATA_ROLE) ?
-					 PD_ROLE_DFP : PD_ROLE_UFP);
+						 PD_ROLE_DFP :
+						 PD_ROLE_UFP);
 #ifdef CONFIG_USBC_VCONN
 			pd_set_vconn_role(port,
 					  (saved_flgs & PD_BBRMFLG_VCONN_ROLE) ?
-					  PD_ROLE_VCONN_ON : PD_ROLE_VCONN_OFF);
+						  PD_ROLE_VCONN_ON :
+						  PD_ROLE_VCONN_OFF);
 #endif /* CONFIG_USBC_VCONN */
 
 			/*
@@ -2965,9 +2868,8 @@ void pd_task(void *u)
 			 * earlier, so clear the contract flag and re-start as
 			 * default role
 			 */
-			pd_update_saved_port_flags(port,
-					PD_BBRMFLG_EXPLICIT_CONTRACT, 0);
-
+			pd_update_saved_port_flags(
+				port, PD_BBRMFLG_EXPLICIT_CONTRACT, 0);
 		}
 		/*
 		 * Set the TCPC reset event such that we can set our CC
@@ -2975,7 +2877,7 @@ void pd_task(void *u)
 		 * can hear back from our port partner if maintaining our old
 		 * connection.
 		 */
-		task_set_event(task_get_current(), PD_EVENT_TCPC_RESET, 0);
+		task_set_event(task_get_current(), PD_EVENT_TCPC_RESET);
 	}
 #endif /* defined(CONFIG_USB_PD_DUAL_ROLE) */
 	/* Set the power role if we haven't already. */
@@ -2994,7 +2896,8 @@ void pd_task(void *u)
 	if (!(saved_flgs & PD_BBRMFLG_EXPLICIT_CONTRACT))
 #endif /* CONFIG_USB_PD_DUAL_ROLE */
 		tcpm_set_cc(port, PD_ROLE_DEFAULT(port) == PD_ROLE_SOURCE ?
-			    TYPEC_CC_RP : TYPEC_CC_RD);
+					  TYPEC_CC_RP :
+					  TYPEC_CC_RD);
 
 #ifdef CONFIG_USBC_PPC
 	/*
@@ -3009,6 +2912,7 @@ void pd_task(void *u)
 #ifdef CONFIG_USB_PD_ALT_MODE_DFP
 	/* Initialize PD Policy engine */
 	pd_dfp_discovery_init(port);
+	pd_dfp_mode_init(port);
 #endif
 
 #ifdef CONFIG_CHARGE_MANAGER
@@ -3038,7 +2942,7 @@ void pd_task(void *u)
 			/* cut the power */
 			pd_execute_hard_reset(port);
 			/* notify the other side of the issue */
-			pd_transmit(port, TCPC_TX_HARD_RESET, 0, NULL,
+			pd_transmit(port, TCPCI_MSG_TX_HARD_RESET, 0, NULL,
 				    AMS_START);
 		}
 
@@ -3051,7 +2955,7 @@ void pd_task(void *u)
 		if (evt & PD_EVENT_DEVICE_ACCESSED)
 			handle_device_access(port);
 #endif
-#ifdef CONFIG_POWER_COMMON
+#ifdef CONFIG_AP_POWER_CONTROL
 		if (evt & PD_EVENT_POWER_STATE_CHANGE)
 			handle_new_power_state(port);
 #endif
@@ -3093,7 +2997,8 @@ void pd_task(void *u)
 				 * role.
 				 */
 				tcpm_set_cc(port, pd[port].power_role ?
-					    TYPEC_CC_RP : TYPEC_CC_RD);
+							  TYPEC_CC_RP :
+							  TYPEC_CC_RD);
 
 				/* Determine the polarity. */
 				tcpm_get_cc(port, &cc1, &cc2);
@@ -3103,7 +3008,7 @@ void pd_task(void *u)
 				} else if (cc_is_snk_dbg_acc(cc1, cc2)) {
 					pd[port].polarity =
 						board_get_src_dts_polarity(
-								port);
+							port);
 				} else {
 					pd[port].polarity =
 						get_src_polarity(cc1, cc2);
@@ -3112,9 +3017,11 @@ void pd_task(void *u)
 #endif /* CONFIG_USB_PD_DUAL_ROLE */
 			{
 				/* Ensure CC termination is default */
-				tcpm_set_cc(port, PD_ROLE_DEFAULT(port) ==
-					    PD_ROLE_SOURCE ? TYPEC_CC_RP :
-					    TYPEC_CC_RD);
+				tcpm_set_cc(port,
+					    PD_ROLE_DEFAULT(port) ==
+							    PD_ROLE_SOURCE ?
+						    TYPEC_CC_RP :
+						    TYPEC_CC_RD);
 			}
 
 			/*
@@ -3124,15 +3031,19 @@ void pd_task(void *u)
 			 * Otherwise, go to the default disconnected state
 			 * and force renegotiation.
 			 */
-			if (pd[port].vdm_state == VDM_STATE_DONE && (
+			if (pd[port].vdm_state == VDM_STATE_DONE &&
+			    (
 #ifdef CONFIG_USB_PD_DUAL_ROLE
-			     (PD_ROLE_DEFAULT(port) == PD_ROLE_SINK &&
-			     pd[port].task_state == PD_STATE_SNK_READY) ||
-			     (pd[port].task_state == PD_STATE_SOFT_RESET) ||
-#endif
-			     (PD_ROLE_DEFAULT(port) == PD_ROLE_SOURCE &&
-			     pd[port].task_state == PD_STATE_SRC_READY))) {
-				pd_set_polarity(port, pd[port].polarity);
+				    (PD_ROLE_DEFAULT(port) == PD_ROLE_SINK &&
+				     pd[port].task_state ==
+					     PD_STATE_SNK_READY) ||
+				    (pd[port].task_state ==
+				     PD_STATE_SOFT_RESET) ||
+#endif
+				    (PD_ROLE_DEFAULT(port) == PD_ROLE_SOURCE &&
+				     pd[port].task_state ==
+					     PD_STATE_SRC_READY))) {
+				typec_set_polarity(port, pd[port].polarity);
 				tcpm_set_msg_header(port, pd[port].power_role,
 						    pd[port].data_role);
 				tcpm_set_rx_enable(port, 1);
@@ -3165,15 +3076,14 @@ void pd_task(void *u)
 		if (incoming_packet) {
 			/* Dequeue and consume duplicate message ID. */
 			if (tcpm_dequeue_message(port, payload, &head) ==
-								EC_SUCCESS
-			    && !consume_repeat_message(port, head)
-			   )
+				    EC_SUCCESS &&
+			    !consume_repeat_message(port, head))
 				handle_request(port, head, payload);
 
 			/* Check if there are any more messages */
 			if (tcpm_has_pending_message(port))
 				task_set_event(PD_PORT_TO_TASK_ID(port),
-					       TASK_EVENT_WAKE, 0);
+					       TASK_EVENT_WAKE);
 		}
 
 		if (pd[port].req_suspend_state)
@@ -3181,14 +3091,14 @@ void pd_task(void *u)
 
 		/* if nothing to do, verify the state of the world in 500ms */
 		this_state = pd[port].task_state;
-		timeout = 500*MSEC;
+		timeout = 500 * MSEC;
 		switch (this_state) {
 		case PD_STATE_DISABLED:
 			/* Nothing to do */
 			break;
 		case PD_STATE_SRC_DISCONNECTED:
-			timeout = 10*MSEC;
-
+			timeout = 10 * MSEC;
+			pd_set_src_caps(port, 0, NULL);
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
 			/*
 			 * If SW decided we should be in a low power state and
@@ -3209,10 +3119,9 @@ void pd_task(void *u)
 			 */
 			if (auto_toggle_supported &&
 			    !(pd[port].flags & PD_FLAGS_TCPC_DRP_TOGGLE) &&
-			    !is_try_src(port) &&
-			    cc_is_open(cc1, cc2)) {
+			    !is_try_src(port) && cc_is_open(cc1, cc2)) {
 				set_state(port, PD_STATE_DRP_AUTO_TOGGLE);
-				timeout = 2*MSEC;
+				timeout = 2 * MSEC;
 				break;
 			}
 #endif
@@ -3242,7 +3151,7 @@ void pd_task(void *u)
 #endif
 				pd[port].cc_state = PD_CC_NONE;
 				set_state(port,
-					PD_STATE_SRC_DISCONNECTED_DEBOUNCE);
+					  PD_STATE_SRC_DISCONNECTED_DEBOUNCE);
 				break;
 			}
 #if defined(CONFIG_USB_PD_DUAL_ROLE)
@@ -3298,7 +3207,7 @@ void pd_task(void *u)
 #endif
 			break;
 		case PD_STATE_SRC_DISCONNECTED_DEBOUNCE:
-			timeout = 20*MSEC;
+			timeout = 20 * MSEC;
 			tcpm_get_cc(port, &cc1, &cc2);
 
 			if (cc_is_snk_dbg_acc(cc1, cc2)) {
@@ -3313,7 +3222,7 @@ void pd_task(void *u)
 			} else {
 				/* No UFP */
 				set_state(port, PD_STATE_SRC_DISCONNECTED);
-				timeout = 5*MSEC;
+				timeout = 5 * MSEC;
 				break;
 			}
 
@@ -3321,8 +3230,8 @@ void pd_task(void *u)
 			if (new_cc_state != pd[port].cc_state) {
 				pd[port].cc_debounce =
 					get_time().val +
-					(is_try_src(port) ? PD_T_DEBOUNCE
-							  : PD_T_CC_DEBOUNCE);
+					(is_try_src(port) ? PD_T_DEBOUNCE :
+							    PD_T_CC_DEBOUNCE);
 				pd[port].cc_state = new_cc_state;
 				break;
 			}
@@ -3340,7 +3249,7 @@ void pd_task(void *u)
 			 * If the port is latched off, just continue to
 			 * monitor for a detach.
 			 */
-			if (ppc_is_port_latched_off(port))
+			if (usbc_ocp_is_port_latched_off(port))
 				break;
 #endif /* CONFIG_USBC_PPC */
 
@@ -3349,8 +3258,10 @@ void pd_task(void *u)
 			    new_cc_state == PD_CC_UFP_DEBUG_ACC) {
 #ifdef CONFIG_USBC_PPC
 				/* Inform PPC that a sink is connected. */
-				ppc_sink_is_connected(port, 1);
+				ppc_dev_is_connected(port, PPC_DEV_SNK);
 #endif /* CONFIG_USBC_PPC */
+				if (IS_ENABLED(CONFIG_USBC_OCP))
+					usbc_ocp_snk_is_connected(port, true);
 				if (new_cc_state == PD_CC_UFP_DEBUG_ACC) {
 					pd[port].polarity =
 						board_get_src_dts_polarity(
@@ -3359,7 +3270,7 @@ void pd_task(void *u)
 					pd[port].polarity =
 						get_src_polarity(cc1, cc2);
 				}
-				pd_set_polarity(port, pd[port].polarity);
+				typec_set_polarity(port, pd[port].polarity);
 
 				/* initial data role for source is DFP */
 				pd_set_data_role(port, PD_ROLE_DFP);
@@ -3420,7 +3331,7 @@ void pd_task(void *u)
 				pd[port].flags |= PD_FLAGS_CHECK_PR_ROLE |
 						  PD_FLAGS_CHECK_DR_ROLE;
 				hard_reset_count = 0;
-				timeout = 5*MSEC;
+				timeout = 5 * MSEC;
 
 				set_state(port, PD_STATE_SRC_STARTUP);
 			}
@@ -3432,7 +3343,7 @@ void pd_task(void *u)
 		case PD_STATE_SRC_HARD_RESET_RECOVER:
 			/* Do not continue until hard reset recovery time */
 			if (get_time().val < pd[port].src_recover) {
-				timeout = 50*MSEC;
+				timeout = 50 * MSEC;
 				break;
 			}
 
@@ -3446,12 +3357,12 @@ void pd_task(void *u)
 #endif
 
 			/* Enable VBUS */
-			timeout = 10*MSEC;
+			timeout = 10 * MSEC;
 			if (pd_set_power_supply_ready(port)) {
 				set_state(port, PD_STATE_SRC_DISCONNECTED);
 				break;
 			}
-#ifdef CONFIG_USB_PD_TCPM_TCPCI
+#if defined(CONFIG_USB_PD_TCPM_TCPCI) || defined(CONFIG_USB_PD_TCPM_STUB)
 			/*
 			 * After transmitting hard reset, TCPM writes
 			 * to RECEIVE_DETECT register to enable
@@ -3459,13 +3370,13 @@ void pd_task(void *u)
 			 */
 			if (pd_comm_is_enabled(port))
 				tcpm_set_rx_enable(port, 1);
-#endif /* CONFIG_USB_PD_TCPM_TCPCI */
+#endif /* CONFIG_USB_PD_TCPM_TCPCI  || CONFIG_USB_PD_TCPM_STUB */
 
+			pd[port].flags |= PD_FLAGS_CHECK_PR_ROLE |
+					  PD_FLAGS_CHECK_DR_ROLE;
 			set_state(port, PD_STATE_SRC_STARTUP);
 			break;
 		case PD_STATE_SRC_STARTUP:
-			/* Reset cable attributes and flags */
-			reset_pd_cable(port);
 			/* Wait for power source to enable */
 			if (pd[port].last_state != pd[port].task_state) {
 				pd[port].flags |= PD_FLAGS_CHECK_IDENTITY;
@@ -3483,13 +3394,14 @@ void pd_task(void *u)
 					 * on during debounce.
 					 */
 					get_time().val +
-					PD_POWER_SUPPLY_TURN_ON_DELAY -
-					  (pd[port].last_state ==
-					   PD_STATE_SRC_DISCONNECTED_DEBOUNCE
-						? PD_T_CC_DEBOUNCE : 0),
+						PD_POWER_SUPPLY_TURN_ON_DELAY -
+						(pd[port].last_state ==
+								 PD_STATE_SRC_DISCONNECTED_DEBOUNCE ?
+							 PD_T_CC_DEBOUNCE :
+							 0),
 #else
 					get_time().val +
-					PD_POWER_SUPPLY_TURN_ON_DELAY,
+						PD_POWER_SUPPLY_TURN_ON_DELAY,
 #endif
 					PD_STATE_SRC_DISCOVERY);
 			}
@@ -3504,25 +3416,25 @@ void pd_task(void *u)
 				 * partner, then start NoResponseTimer.
 				 */
 				if (pd_capable(port))
-					set_state_timeout(port,
+					set_state_timeout(
+						port,
 						get_time().val +
-						PD_T_NO_RESPONSE,
+							PD_T_NO_RESPONSE,
 						hard_reset_count <
-						  PD_HARD_RESET_COUNT ?
-						    PD_STATE_HARD_RESET_SEND :
-						    PD_STATE_SRC_DISCONNECTED);
+								PD_HARD_RESET_COUNT ?
+							PD_STATE_HARD_RESET_SEND :
+							PD_STATE_SRC_DISCONNECTED);
 			}
 
 			/* Send source cap some minimum number of times */
-			if (caps_count < PD_CAPS_COUNT  &&
-						next_src_cap <= now.val) {
+			if (caps_count < PD_CAPS_COUNT &&
+			    next_src_cap <= now.val) {
 				/* Query capabilities of the other side */
 				res = send_source_cap(port, AMS_START);
 				/* packet was acked => PD capable device) */
 				if (res >= 0) {
-					set_state(port,
-						  PD_STATE_SRC_NEGOCIATE);
-					timeout = 10*MSEC;
+					set_state(port, PD_STATE_SRC_NEGOCIATE);
+					timeout = 10 * MSEC;
 					hard_reset_count = 0;
 					caps_count = 0;
 					/* Port partner is PD capable */
@@ -3530,8 +3442,8 @@ void pd_task(void *u)
 						PD_FLAGS_PREVIOUS_PD_CONN;
 				} else { /* failed, retry later */
 					timeout = PD_T_SEND_SOURCE_CAP;
-					next_src_cap = now.val +
-							PD_T_SEND_SOURCE_CAP;
+					next_src_cap =
+						now.val + PD_T_SEND_SOURCE_CAP;
 					caps_count++;
 				}
 			} else if (caps_count < PD_CAPS_COUNT) {
@@ -3543,17 +3455,16 @@ void pd_task(void *u)
 			if (pd[port].last_state != pd[port].task_state)
 				set_state_timeout(port,
 						  get_time().val +
-						  PD_T_SENDER_RESPONSE,
+							  PD_T_SENDER_RESPONSE,
 						  PD_STATE_HARD_RESET_SEND);
 			break;
 		case PD_STATE_SRC_ACCEPTED:
 			/* Accept sent, wait for enabling the new voltage */
 			if (pd[port].last_state != pd[port].task_state)
-				set_state_timeout(
-					port,
-					get_time().val +
-					PD_T_SINK_TRANSITION,
-					PD_STATE_SRC_POWERED);
+				set_state_timeout(port,
+						  get_time().val +
+							  PD_T_SINK_TRANSITION,
+						  PD_STATE_SRC_POWERED);
 			break;
 		case PD_STATE_SRC_POWERED:
 			/* Switch to the new requested voltage */
@@ -3563,7 +3474,7 @@ void pd_task(void *u)
 				set_state_timeout(
 					port,
 					get_time().val +
-					PD_POWER_SUPPLY_TURN_ON_DELAY,
+						PD_POWER_SUPPLY_TURN_ON_DELAY,
 					PD_STATE_SRC_TRANSITION);
 			}
 			break;
@@ -3571,7 +3482,7 @@ void pd_task(void *u)
 			/* the voltage output is good, notify the source */
 			res = send_control(port, PD_CTRL_PS_RDY);
 			if (res >= 0) {
-				timeout = 10*MSEC;
+				timeout = 10 * MSEC;
 
 				/*
 				 * Give the sink some time to send any messages
@@ -3584,8 +3495,8 @@ void pd_task(void *u)
 				 * SRC_READY state.
 				 */
 				pd[port].ready_state_holdoff_timer =
-					get_time().val + SRC_READY_HOLD_OFF_US
-					+ (get_time().le.lo & 0xf) * 12 * MSEC;
+					get_time().val + SRC_READY_HOLD_OFF_US +
+					(get_time().le.lo & 0xf) * 12 * MSEC;
 
 				/* it's time to ping regularly the sink */
 				set_state(port, PD_STATE_SRC_READY);
@@ -3621,8 +3532,7 @@ void pd_task(void *u)
 			if (pd[port].flags & PD_FLAGS_UPDATE_SRC_CAPS) {
 				res = send_source_cap(port, AMS_START);
 				if (res >= 0) {
-					set_state(port,
-						  PD_STATE_SRC_NEGOCIATE);
+					set_state(port, PD_STATE_SRC_NEGOCIATE);
 					pd[port].flags &=
 						~PD_FLAGS_UPDATE_SRC_CAPS;
 				}
@@ -3632,12 +3542,16 @@ void pd_task(void *u)
 			/* Send get sink cap if haven't received it yet */
 			if (!(pd[port].flags & PD_FLAGS_SNK_CAP_RECVD)) {
 				if (++snk_cap_count <= PD_SNK_CAP_RETRIES) {
-					/* Get sink cap to know if dual-role device */
-					send_control(port, PD_CTRL_GET_SINK_CAP);
-					set_state(port, PD_STATE_SRC_GET_SINK_CAP);
+					/* Get sink cap to know if dual-role
+					 * device */
+					send_control(port,
+						     PD_CTRL_GET_SINK_CAP);
+					set_state(port,
+						  PD_STATE_SRC_GET_SINK_CAP);
 					break;
 				} else if (debug_level >= 2 &&
-					   snk_cap_count == PD_SNK_CAP_RETRIES+1) {
+					   snk_cap_count ==
+						   PD_SNK_CAP_RETRIES + 1) {
 					CPRINTF("C%d ERR SNK_CAP\n", port);
 				}
 			}
@@ -3649,7 +3563,6 @@ void pd_task(void *u)
 				pd[port].flags &= ~PD_FLAGS_CHECK_PR_ROLE;
 			}
 
-
 			/* Check data role policy, which may trigger a swap */
 			if (pd[port].flags & PD_FLAGS_CHECK_DR_ROLE) {
 				pd_check_dr_role(port, pd[port].data_role,
@@ -3668,8 +3581,7 @@ void pd_task(void *u)
 				 * initiate or receive a request an exchange
 				 * of VCONN Source.
 				 */
-				pd_try_execute_vconn_swap(port,
-							  pd[port].flags);
+				pd_try_execute_vconn_swap(port, pd[port].flags);
 				pd[port].flags &= ~PD_FLAGS_CHECK_VCONN_STATE;
 				break;
 			}
@@ -3685,15 +3597,6 @@ void pd_task(void *u)
 				break;
 			}
 
-			/*
-			 * Enter_USB if port partner and cable are
-			 * USB4 compatible.
-			 */
-			if (should_enter_usb4_mode(port)) {
-				pd_send_enter_usb(port, &timeout);
-				break;
-			}
-
 			if (!(pd[port].flags & PD_FLAGS_PING_ENABLED))
 				break;
 
@@ -3710,28 +3613,30 @@ void pd_task(void *u)
 			if (pd[port].last_state != pd[port].task_state)
 				set_state_timeout(port,
 						  get_time().val +
-						  PD_T_SENDER_RESPONSE,
+							  PD_T_SENDER_RESPONSE,
 						  PD_STATE_SRC_READY);
 			break;
 		case PD_STATE_DR_SWAP:
 			if (pd[port].last_state != pd[port].task_state) {
 				res = send_control(port, PD_CTRL_DR_SWAP);
 				if (res < 0) {
-					timeout = 10*MSEC;
+					timeout = 10 * MSEC;
 					/*
 					 * If failed to get goodCRC, send
 					 * soft reset, otherwise ignore
 					 * failure.
 					 */
-					set_state(port, res == -1 ?
-						   PD_STATE_SOFT_RESET :
-						   READY_RETURN_STATE(port));
+					set_state(port,
+						  res == -1 ?
+							  PD_STATE_SOFT_RESET :
+							  READY_RETURN_STATE(
+								  port));
 					break;
 				}
 				/* Wait for accept or reject */
 				set_state_timeout(port,
 						  get_time().val +
-						  PD_T_SENDER_RESPONSE,
+							  PD_T_SENDER_RESPONSE,
 						  READY_RETURN_STATE(port));
 			}
 			break;
@@ -3740,31 +3645,32 @@ void pd_task(void *u)
 			if (pd[port].last_state != pd[port].task_state) {
 				res = send_control(port, PD_CTRL_PR_SWAP);
 				if (res < 0) {
-					timeout = 10*MSEC;
+					timeout = 10 * MSEC;
 					/*
 					 * If failed to get goodCRC, send
 					 * soft reset, otherwise ignore
 					 * failure.
 					 */
-					set_state(port, res == -1 ?
-						   PD_STATE_SOFT_RESET :
-						   PD_STATE_SRC_READY);
+					set_state(port,
+						  res == -1 ?
+							  PD_STATE_SOFT_RESET :
+							  PD_STATE_SRC_READY);
 					break;
 				}
 				/* Wait for accept or reject */
 				set_state_timeout(port,
 						  get_time().val +
-						  PD_T_SENDER_RESPONSE,
+							  PD_T_SENDER_RESPONSE,
 						  PD_STATE_SRC_READY);
 			}
 			break;
 		case PD_STATE_SRC_SWAP_SNK_DISABLE:
 			/* Give time for sink to stop drawing current */
 			if (pd[port].last_state != pd[port].task_state)
-				set_state_timeout(port,
-						  get_time().val +
-						  PD_T_SINK_TRANSITION,
-						  PD_STATE_SRC_SWAP_SRC_DISABLE);
+				set_state_timeout(
+					port,
+					get_time().val + PD_T_SINK_TRANSITION,
+					PD_STATE_SRC_SWAP_SRC_DISABLE);
 			break;
 		case PD_STATE_SRC_SWAP_SRC_DISABLE:
 			if (pd[port].last_state != pd[port].task_state) {
@@ -3787,10 +3693,11 @@ void pd_task(void *u)
 				/* Inform TCPC of power role update. */
 				pd_update_roles(port);
 
-				set_state_timeout(port,
-						  get_time().val +
-						  PD_POWER_SUPPLY_TURN_OFF_DELAY,
-						  PD_STATE_SRC_SWAP_STANDBY);
+				set_state_timeout(
+					port,
+					get_time().val +
+						PD_POWER_SUPPLY_TURN_OFF_DELAY,
+					PD_STATE_SRC_SWAP_STANDBY);
 			}
 			break;
 		case PD_STATE_SRC_SWAP_STANDBY:
@@ -3799,7 +3706,7 @@ void pd_task(void *u)
 				/* Send PS_RDY */
 				res = send_control(port, PD_CTRL_PS_RDY);
 				if (res < 0) {
-					timeout = 10*MSEC;
+					timeout = 10 * MSEC;
 					set_state(port,
 						  PD_STATE_SRC_DISCONNECTED);
 					break;
@@ -3807,7 +3714,7 @@ void pd_task(void *u)
 				/* Wait for PS_RDY from new source */
 				set_state_timeout(port,
 						  get_time().val +
-						  PD_T_PS_SOURCE_ON,
+							  PD_T_PS_SOURCE_ON,
 						  PD_STATE_SNK_DISCONNECTED);
 			}
 			break;
@@ -3858,8 +3765,8 @@ void pd_task(void *u)
 			/* Set the CC termination and state back to default */
 			tcpm_set_cc(port,
 				    PD_ROLE_DEFAULT(port) == PD_ROLE_SOURCE ?
-					TYPEC_CC_RP :
-					TYPEC_CC_RD);
+					    TYPEC_CC_RP :
+					    TYPEC_CC_RD);
 			set_state(port, PD_DEFAULT_STATE(port));
 			tcpc_prints("resumed!", port);
 #endif
@@ -3867,12 +3774,13 @@ void pd_task(void *u)
 		}
 		case PD_STATE_SNK_DISCONNECTED:
 #ifdef CONFIG_USB_PD_LOW_POWER
-			timeout = (drp_state[port] !=
-				PD_DRP_TOGGLE_ON ? SECOND : 10*MSEC);
+			timeout = (drp_state[port] != PD_DRP_TOGGLE_ON ?
+					   SECOND :
+					   10 * MSEC);
 #else
-			timeout = 10*MSEC;
+			timeout = 10 * MSEC;
 #endif
-
+			pd_set_src_caps(port, 0, NULL);
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
 			/*
 			 * If SW decided we should be in a low power state and
@@ -3894,11 +3802,10 @@ void pd_task(void *u)
 			 */
 			if (auto_toggle_supported &&
 			    !(pd[port].flags & PD_FLAGS_TCPC_DRP_TOGGLE) &&
-			    !is_try_src(port) &&
-			    cc_is_open(cc1, cc2) &&
-				(drp_state[port] == PD_DRP_TOGGLE_ON)) {
+			    !is_try_src(port) && cc_is_open(cc1, cc2) &&
+			    (drp_state[port] == PD_DRP_TOGGLE_ON)) {
 				set_state(port, PD_STATE_DRP_AUTO_TOGGLE);
-				timeout = 2*MSEC;
+				timeout = 2 * MSEC;
 				break;
 			}
 #endif
@@ -3908,11 +3815,11 @@ void pd_task(void *u)
 				pd[port].cc_state = PD_CC_NONE;
 				hard_reset_count = 0;
 				new_cc_state = PD_CC_NONE;
-				pd[port].cc_debounce = get_time().val +
-							PD_T_CC_DEBOUNCE;
+				pd[port].cc_debounce =
+					get_time().val + PD_T_CC_DEBOUNCE;
 				set_state(port,
-					PD_STATE_SNK_DISCONNECTED_DEBOUNCE);
-				timeout = 10*MSEC;
+					  PD_STATE_SNK_DISCONNECTED_DEBOUNCE);
+				timeout = 10 * MSEC;
 				break;
 			}
 
@@ -3946,7 +3853,7 @@ void pd_task(void *u)
 #endif
 
 				/* Swap states quickly */
-				timeout = 2*MSEC;
+				timeout = 2 * MSEC;
 				break;
 			}
 
@@ -3957,7 +3864,7 @@ void pd_task(void *u)
 			 * CC status.
 			 */
 			pd[port].flags |= PD_FLAGS_LPM_REQUESTED;
-#endif/* CONFIG_USB_PD_TCPC_LOW_POWER */
+#endif /* CONFIG_USB_PD_TCPC_LOW_POWER */
 			break;
 
 		case PD_STATE_SNK_DISCONNECTED_DEBOUNCE:
@@ -3971,16 +3878,16 @@ void pd_task(void *u)
 			} else {
 				/* No connection any more */
 				set_state(port, PD_STATE_SNK_DISCONNECTED);
-				timeout = 5*MSEC;
+				timeout = 5 * MSEC;
 				break;
 			}
 
-			timeout = 20*MSEC;
+			timeout = 20 * MSEC;
 
 			/* Debounce the cc state */
 			if (new_cc_state != pd[port].cc_state) {
-				pd[port].cc_debounce = get_time().val +
-					PD_T_CC_DEBOUNCE;
+				pd[port].cc_debounce =
+					get_time().val + PD_T_CC_DEBOUNCE;
 				pd[port].cc_state = new_cc_state;
 				break;
 			}
@@ -3995,14 +3902,14 @@ void pd_task(void *u)
 				 * If TRY_SRC is enabled, but not active,
 				 * then force attempt to connect as source.
 				 */
-				pd[port].try_src_marker = get_time().val
-					+ PD_T_DRP_TRY;
-				pd[port].try_timeout = get_time().val
-					+ PD_T_TRY_TIMEOUT;
+				pd[port].try_src_marker =
+					get_time().val + PD_T_DRP_TRY;
+				pd[port].try_timeout =
+					get_time().val + PD_T_TRY_TIMEOUT;
 				/* Swap roles to source */
 				pd_set_power_role(port, PD_ROLE_SOURCE);
 				tcpm_set_cc(port, TYPEC_CC_RP);
-				timeout = 2*MSEC;
+				timeout = 2 * MSEC;
 				set_state(port, PD_STATE_SRC_DISCONNECTED);
 				/* Set flag after the state change */
 				pd[port].flags |= PD_FLAGS_TRY_SRC;
@@ -4013,7 +3920,7 @@ void pd_task(void *u)
 			if (IS_ENABLED(CONFIG_COMMON_RUNTIME))
 				hook_notify(HOOK_USB_PD_CONNECT);
 			pd[port].polarity = get_snk_polarity(cc1, cc2);
-			pd_set_polarity(port, pd[port].polarity);
+			typec_set_polarity(port, pd[port].polarity);
 			/* reset message ID  on connection */
 			pd[port].msg_id = 0;
 			/* initial data role for sink is UFP */
@@ -4023,9 +3930,17 @@ void pd_task(void *u)
 #if defined(CONFIG_CHARGE_MANAGER)
 			typec_curr = usb_get_typec_current_limit(
 				pd[port].polarity, cc1, cc2);
-			typec_set_input_current_limit(
-				port, typec_curr, TYPE_C_VOLTAGE);
+			typec_set_input_current_limit(port, typec_curr,
+						      TYPE_C_VOLTAGE);
 #endif
+
+#ifdef CONFIG_USBC_PPC
+			/* Inform PPC that a source is connected. */
+			ppc_dev_is_connected(port, PPC_DEV_SRC);
+#endif /* CONFIG_USBC_PPC */
+			if (IS_ENABLED(CONFIG_USBC_OCP))
+				usbc_ocp_snk_is_connected(port, false);
+
 			/* If PD comm is enabled, enable TCPC RX */
 			if (pd_comm_is_enabled(port))
 				tcpm_set_rx_enable(port, 1);
@@ -4036,14 +3951,11 @@ void pd_task(void *u)
 				pd[port].flags |= PD_FLAGS_CHECK_PR_ROLE |
 						  PD_FLAGS_CHECK_DR_ROLE |
 						  PD_FLAGS_CHECK_IDENTITY;
-				/* Reset cable attributes and flags */
-				reset_pd_cable(port);
-
 				if (new_cc_state == PD_CC_DFP_DEBUG_ACC)
 					pd[port].flags |=
 						PD_FLAGS_TS_DTS_PARTNER;
 				set_state(port, PD_STATE_SNK_DISCOVERY);
-				timeout = 10*MSEC;
+				timeout = 10 * MSEC;
 				hook_call_deferred(
 					&pd_usb_billboard_deferred_data,
 					PD_T_AME);
@@ -4052,58 +3964,66 @@ void pd_task(void *u)
 		case PD_STATE_SNK_HARD_RESET_RECOVER:
 			if (pd[port].last_state != pd[port].task_state)
 				pd[port].flags |= PD_FLAGS_CHECK_IDENTITY;
-#ifdef CONFIG_USB_PD_VBUS_DETECT_NONE
-			/*
-			 * Can't measure vbus state so this is the maximum
-			 * recovery time for the source.
-			 */
-			if (pd[port].last_state != pd[port].task_state)
-				set_state_timeout(port, get_time().val +
-						  PD_T_SAFE_0V +
-						  PD_T_SRC_RECOVER_MAX +
-						  PD_T_SRC_TURN_ON,
-						  PD_STATE_SNK_DISCONNECTED);
-#else
-			/* Wait for VBUS to go low and then high*/
-			if (pd[port].last_state != pd[port].task_state) {
-				snk_hard_reset_vbus_off = 0;
-				set_state_timeout(port,
-						  get_time().val +
-						  PD_T_SAFE_0V,
-						  hard_reset_count <
-						    PD_HARD_RESET_COUNT ?
-						     PD_STATE_HARD_RESET_SEND :
-						     PD_STATE_SNK_DISCOVERY);
-			}
 
-			if (!pd_is_vbus_present(port) &&
-			    !snk_hard_reset_vbus_off) {
-				/* VBUS has gone low, reset timeout */
-				snk_hard_reset_vbus_off = 1;
-				set_state_timeout(port,
-						  get_time().val +
-						  PD_T_SRC_RECOVER_MAX +
-						  PD_T_SRC_TURN_ON,
-						  PD_STATE_SNK_DISCONNECTED);
-			}
-			if (pd_is_vbus_present(port) &&
-			    snk_hard_reset_vbus_off) {
-				/* VBUS went high again */
-				set_state(port, PD_STATE_SNK_DISCOVERY);
-				timeout = 10*MSEC;
-			}
+			if (get_usb_pd_vbus_detect() ==
+			    USB_PD_VBUS_DETECT_NONE) {
+				/*
+				 * Can't measure vbus state so this is the
+				 * maximum recovery time for the source.
+				 */
+				if (pd[port].last_state != pd[port].task_state)
+					set_state_timeout(
+						port,
+						get_time().val + PD_T_SAFE_0V +
+							PD_T_SRC_RECOVER_MAX +
+							PD_T_SRC_TURN_ON,
+						PD_STATE_SNK_DISCONNECTED);
+			} else {
+#ifndef CONFIG_USB_PD_VBUS_DETECT_NONE
+				/* Wait for VBUS to go low and then high*/
+				if (pd[port].last_state !=
+				    pd[port].task_state) {
+					snk_hard_reset_vbus_off = 0;
+					set_state_timeout(
+						port,
+						get_time().val + PD_T_SAFE_0V,
+						hard_reset_count <
+								PD_HARD_RESET_COUNT ?
+							PD_STATE_HARD_RESET_SEND :
+							PD_STATE_SNK_DISCOVERY);
+				}
 
-			/*
-			 * Don't need to set timeout because VBUS changing
-			 * will trigger an interrupt and wake us up.
-			 */
+				if (!pd_is_vbus_present(port) &&
+				    !snk_hard_reset_vbus_off) {
+					/* VBUS has gone low, reset timeout */
+					snk_hard_reset_vbus_off = 1;
+					set_state_timeout(
+						port,
+						get_time().val +
+							PD_T_SRC_RECOVER_MAX +
+							PD_T_SRC_TURN_ON,
+						PD_STATE_SNK_DISCONNECTED);
+				}
+				if (pd_is_vbus_present(port) &&
+				    snk_hard_reset_vbus_off) {
+					/* VBUS went high again */
+					set_state(port, PD_STATE_SNK_DISCOVERY);
+					timeout = 10 * MSEC;
+				}
+
+				/*
+				 * Don't need to set timeout because VBUS
+				 * changing will trigger an interrupt and
+				 * wake us up.
+				 */
 #endif
+			}
 			break;
 		case PD_STATE_SNK_DISCOVERY:
 			/* Wait for source cap expired only if we are enabled */
-			if ((pd[port].last_state != pd[port].task_state)
-			    && pd_comm_is_enabled(port)) {
-#ifdef CONFIG_USB_PD_TCPM_TCPCI
+			if ((pd[port].last_state != pd[port].task_state) &&
+			    pd_comm_is_enabled(port)) {
+#if defined(CONFIG_USB_PD_TCPM_TCPCI) || defined(CONFIG_USB_PD_TCPM_STUB)
 				/*
 				 * If we come from hard reset recover state,
 				 * then we can process the source capabilities
@@ -4113,7 +4033,7 @@ void pd_task(void *u)
 				if (pd[port].last_state ==
 				    PD_STATE_SNK_HARD_RESET_RECOVER)
 					tcpm_set_rx_enable(port, 1);
-#endif /* CONFIG_USB_PD_TCPM_TCPCI */
+#endif /* CONFIG_USB_PD_TCPM_TCPCI  || CONFIG_USB_PD_TCPM_STUB */
 #ifdef CONFIG_USB_PD_RESET_MIN_BATT_SOC
 				/*
 				 * If the battery has not met a configured safe
@@ -4125,57 +4045,64 @@ void pd_task(void *u)
 				 */
 				int batt_soc = usb_get_battery_soc();
 
-				if (batt_soc < CONFIG_USB_PD_RESET_MIN_BATT_SOC ||
-				    battery_get_disconnect_state() != BATTERY_NOT_DISCONNECTED)
+				if (batt_soc <
+					    CONFIG_USB_PD_RESET_MIN_BATT_SOC ||
+				    battery_get_disconnect_state() !=
+					    BATTERY_NOT_DISCONNECTED)
 					pd[port].flags |=
-						    PD_FLAGS_SNK_WAITING_BATT;
+						PD_FLAGS_SNK_WAITING_BATT;
 				else
 					pd[port].flags &=
-						    ~PD_FLAGS_SNK_WAITING_BATT;
+						~PD_FLAGS_SNK_WAITING_BATT;
 #endif
 
 				if (pd[port].flags &
-						    PD_FLAGS_SNK_WAITING_BATT) {
+				    PD_FLAGS_SNK_WAITING_BATT) {
 #ifdef CONFIG_CHARGE_MANAGER
 					/*
 					 * Configure this port as dedicated for
 					 * now, so it won't be de-selected by
 					 * the charge manager leaving safe mode.
 					 */
-					charge_manager_update_dualrole(port,
-								CAP_DEDICATED);
+					charge_manager_update_dualrole(
+						port, CAP_DEDICATED);
 #endif
 					CPRINTS("C%d: Battery low. "
-						"Hold reset timer", port);
-				/*
-				 * If VBUS has never been low, and we timeout
-				 * waiting for source cap, try a soft reset
-				 * first, in case we were already in a stable
-				 * contract before this boot.
-				 */
+						"Hold reset timer",
+						port);
+					/*
+					 * If VBUS has never been low, and we
+					 * timeout waiting for source cap, try a
+					 * soft reset first, in case we were
+					 * already in a stable contract before
+					 * this boot.
+					 */
 				} else if (pd[port].flags &
-						PD_FLAGS_VBUS_NEVER_LOW) {
-					set_state_timeout(port,
-						  get_time().val +
-						  PD_T_SINK_WAIT_CAP,
-						  PD_STATE_SOFT_RESET);
-				/*
-				 * If we haven't passed hard reset counter,
-				 * start SinkWaitCapTimer, otherwise start
-				 * NoResponseTimer.
-				 */
+					   PD_FLAGS_VBUS_NEVER_LOW) {
+					set_state_timeout(
+						port,
+						get_time().val +
+							PD_T_SINK_WAIT_CAP,
+						PD_STATE_SOFT_RESET);
+					/*
+					 * If we haven't passed hard reset
+					 * counter, start SinkWaitCapTimer,
+					 * otherwise start NoResponseTimer.
+					 */
 				} else if (hard_reset_count <
-						PD_HARD_RESET_COUNT) {
-					set_state_timeout(port,
-						  get_time().val +
-						  PD_T_SINK_WAIT_CAP,
-						  PD_STATE_HARD_RESET_SEND);
+					   PD_HARD_RESET_COUNT) {
+					set_state_timeout(
+						port,
+						get_time().val +
+							PD_T_SINK_WAIT_CAP,
+						PD_STATE_HARD_RESET_SEND);
 				} else if (pd_capable(port)) {
 					/* ErrorRecovery */
-					set_state_timeout(port,
-						  get_time().val +
-						  PD_T_NO_RESPONSE,
-						  PD_STATE_SNK_DISCONNECTED);
+					set_state_timeout(
+						port,
+						get_time().val +
+							PD_T_NO_RESPONSE,
+						PD_STATE_SNK_DISCONNECTED);
 				}
 #if defined(CONFIG_CHARGE_MANAGER)
 				/*
@@ -4195,17 +4122,17 @@ void pd_task(void *u)
 
 			/* Check if CC pull-up has changed */
 			tcpm_get_cc(port, &cc1, &cc2);
-			if (typec_curr != usb_get_typec_current_limit(
-						pd[port].polarity, cc1, cc2)) {
+			if (typec_curr !=
+			    usb_get_typec_current_limit(pd[port].polarity, cc1,
+							cc2)) {
 				/* debounce signal by requiring two reads */
 				if (typec_curr_change) {
 					/* set new input current limit */
-					typec_curr =
-						usb_get_typec_current_limit(
-							pd[port].polarity,
-							cc1, cc2);
+					typec_curr = usb_get_typec_current_limit(
+						pd[port].polarity, cc1, cc2);
 					typec_set_input_current_limit(
-					  port, typec_curr, TYPE_C_VOLTAGE);
+						port, typec_curr,
+						TYPE_C_VOLTAGE);
 				} else {
 					/* delay for debounce */
 					timeout = PD_T_DEBOUNCE;
@@ -4223,7 +4150,7 @@ void pd_task(void *u)
 				hard_reset_count = 0;
 				set_state_timeout(port,
 						  get_time().val +
-						  PD_T_SENDER_RESPONSE,
+							  PD_T_SENDER_RESPONSE,
 						  PD_STATE_HARD_RESET_SEND);
 			}
 			break;
@@ -4232,11 +4159,11 @@ void pd_task(void *u)
 			if (pd[port].last_state != pd[port].task_state)
 				set_state_timeout(port,
 						  get_time().val +
-						  PD_T_PS_TRANSITION,
+							  PD_T_PS_TRANSITION,
 						  PD_STATE_HARD_RESET_SEND);
 			break;
 		case PD_STATE_SNK_READY:
-			timeout = 20*MSEC;
+			timeout = 20 * MSEC;
 
 			/*
 			 * Don't send any traffic yet until our holdoff timer
@@ -4291,52 +4218,43 @@ void pd_task(void *u)
 				 * initiate or receive a request an exchange
 				 * of VCONN Source.
 				 */
-				pd_try_execute_vconn_swap(port,
-							  pd[port].flags);
+				pd_try_execute_vconn_swap(port, pd[port].flags);
 				pd[port].flags &= ~PD_FLAGS_CHECK_VCONN_STATE;
 				break;
 			}
 
 			/* If DFP, send discovery SVDMs */
 			if (pd[port].data_role == PD_ROLE_DFP &&
-			     (pd[port].flags & PD_FLAGS_CHECK_IDENTITY)) {
+			    (pd[port].flags & PD_FLAGS_CHECK_IDENTITY)) {
 				pd_send_vdm(port, USB_SID_PD,
 					    CMD_DISCOVER_IDENT, NULL, 0);
 				pd[port].flags &= ~PD_FLAGS_CHECK_IDENTITY;
 				break;
 			}
 
-			/*
-			 * Enter_USB if port partner and cable are
-			 * USB4 compatible.
-			 */
-			if (should_enter_usb4_mode(port)) {
-				pd_send_enter_usb(port, &timeout);
-				break;
-			}
-
 			/* Sent all messages, don't need to wake very often */
-			timeout = 200*MSEC;
+			timeout = 200 * MSEC;
 			break;
 		case PD_STATE_SNK_SWAP_INIT:
 			if (pd[port].last_state != pd[port].task_state) {
 				res = send_control(port, PD_CTRL_PR_SWAP);
 				if (res < 0) {
-					timeout = 10*MSEC;
+					timeout = 10 * MSEC;
 					/*
 					 * If failed to get goodCRC, send
 					 * soft reset, otherwise ignore
 					 * failure.
 					 */
-					set_state(port, res == -1 ?
-						   PD_STATE_SOFT_RESET :
-						   PD_STATE_SNK_READY);
+					set_state(port,
+						  res == -1 ?
+							  PD_STATE_SOFT_RESET :
+							  PD_STATE_SNK_READY);
 					break;
 				}
 				/* Wait for accept or reject */
 				set_state_timeout(port,
 						  get_time().val +
-						  PD_T_SENDER_RESPONSE,
+							  PD_T_SENDER_RESPONSE,
 						  PD_STATE_SNK_READY);
 			}
 			break;
@@ -4345,19 +4263,18 @@ void pd_task(void *u)
 			pd_set_input_current_limit(port, 0, 0);
 #ifdef CONFIG_CHARGE_MANAGER
 			typec_set_input_current_limit(port, 0, 0);
-			charge_manager_set_ceil(port,
-						CEIL_REQUESTOR_PD,
+			charge_manager_set_ceil(port, CEIL_REQUESTOR_PD,
 						CHARGE_CEIL_NONE);
 #endif
 			set_state(port, PD_STATE_SNK_SWAP_SRC_DISABLE);
-			timeout = 10*MSEC;
+			timeout = 10 * MSEC;
 			break;
 		case PD_STATE_SNK_SWAP_SRC_DISABLE:
 			/* Wait for PS_RDY */
 			if (pd[port].last_state != pd[port].task_state)
 				set_state_timeout(port,
 						  get_time().val +
-						  PD_T_PS_SOURCE_OFF,
+							  PD_T_PS_SOURCE_OFF,
 						  PD_STATE_HARD_RESET_SEND);
 			break;
 		case PD_STATE_SNK_SWAP_STANDBY:
@@ -4367,7 +4284,7 @@ void pd_task(void *u)
 				if (pd_set_power_supply_ready(port)) {
 					/* Restore Rd */
 					tcpm_set_cc(port, TYPEC_CC_RD);
-					timeout = 10*MSEC;
+					timeout = 10 * MSEC;
 					set_state(port,
 						  PD_STATE_SNK_DISCONNECTED);
 					break;
@@ -4376,7 +4293,7 @@ void pd_task(void *u)
 				set_state_timeout(
 					port,
 					get_time().val +
-					PD_POWER_SUPPLY_TURN_ON_DELAY,
+						PD_POWER_SUPPLY_TURN_ON_DELAY,
 					PD_STATE_SNK_SWAP_COMPLETE);
 			}
 			break;
@@ -4393,34 +4310,36 @@ void pd_task(void *u)
 			}
 
 			/* Don't send GET_SINK_CAP on swap */
-			snk_cap_count = PD_SNK_CAP_RETRIES+1;
+			snk_cap_count = PD_SNK_CAP_RETRIES + 1;
 			caps_count = 0;
 			pd[port].msg_id = 0;
 			pd_set_power_role(port, PD_ROLE_SOURCE);
 			pd_update_roles(port);
 			set_state(port, PD_STATE_SRC_DISCOVERY);
-			timeout = 10*MSEC;
+			timeout = 10 * MSEC;
 			break;
 #ifdef CONFIG_USBC_VCONN_SWAP
 		case PD_STATE_VCONN_SWAP_SEND:
 			if (pd[port].last_state != pd[port].task_state) {
 				res = send_control(port, PD_CTRL_VCONN_SWAP);
 				if (res < 0) {
-					timeout = 10*MSEC;
+					timeout = 10 * MSEC;
 					/*
 					 * If failed to get goodCRC, send
 					 * soft reset, otherwise ignore
 					 * failure.
 					 */
-					set_state(port, res == -1 ?
-						   PD_STATE_SOFT_RESET :
-						   READY_RETURN_STATE(port));
+					set_state(port,
+						  res == -1 ?
+							  PD_STATE_SOFT_RESET :
+							  READY_RETURN_STATE(
+								  port));
 					break;
 				}
 				/* Wait for accept or reject */
 				set_state_timeout(port,
 						  get_time().val +
-						  PD_T_SENDER_RESPONSE,
+							  PD_T_SENDER_RESPONSE,
 						  READY_RETURN_STATE(port));
 			}
 			break;
@@ -4429,13 +4348,17 @@ void pd_task(void *u)
 				if (!(pd[port].flags & PD_FLAGS_VCONN_ON)) {
 					/* Turn VCONN on and wait for it */
 					set_vconn(port, 1);
-					set_state_timeout(port,
-					  get_time().val + PD_VCONN_SWAP_DELAY,
-					  PD_STATE_VCONN_SWAP_READY);
+					set_state_timeout(
+						port,
+						get_time().val +
+							CONFIG_USBC_VCONN_SWAP_DELAY_US,
+						PD_STATE_VCONN_SWAP_READY);
 				} else {
-					set_state_timeout(port,
-					  get_time().val + PD_T_VCONN_SOURCE_ON,
-					  READY_RETURN_STATE(port));
+					set_state_timeout(
+						port,
+						get_time().val +
+							PD_T_VCONN_SOURCE_ON,
+						READY_RETURN_STATE(port));
 				}
 			}
 			break;
@@ -4448,7 +4371,7 @@ void pd_task(void *u)
 					res = send_control(port,
 							   PD_CTRL_PS_RDY);
 					if (res == -1) {
-						timeout = 10*MSEC;
+						timeout = 10 * MSEC;
 						/*
 						 * If failed to get goodCRC,
 						 * send soft reset
@@ -4464,9 +4387,11 @@ void pd_task(void *u)
 					set_vconn(port, 0);
 					pd_set_vconn_role(port,
 							  PD_ROLE_VCONN_OFF);
-					set_state_timeout(port,
-					  get_time().val + PD_VCONN_SWAP_DELAY,
-					  READY_RETURN_STATE(port));
+					set_state_timeout(
+						port,
+						get_time().val +
+							CONFIG_USBC_VCONN_SWAP_DELAY_US,
+						READY_RETURN_STATE(port));
 				}
 			}
 			break;
@@ -4483,14 +4408,14 @@ void pd_task(void *u)
 				if (res < 0) {
 					set_state(port,
 						  PD_STATE_HARD_RESET_SEND);
-					timeout = 5*MSEC;
+					timeout = 5 * MSEC;
 					break;
 				}
 
-				set_state_timeout(
-					port,
-					get_time().val + PD_T_SENDER_RESPONSE,
-					PD_STATE_HARD_RESET_SEND);
+				set_state_timeout(port,
+						  get_time().val +
+							  PD_T_SENDER_RESPONSE,
+						  PD_STATE_HARD_RESET_SEND);
 			}
 			break;
 		case PD_STATE_HARD_RESET_SEND:
@@ -4521,8 +4446,8 @@ void pd_task(void *u)
 			if (hard_reset_sent)
 				break;
 
-			if (pd_transmit(port, TCPC_TX_HARD_RESET, 0, NULL,
-				AMS_START) < 0) {
+			if (pd_transmit(port, TCPCI_MSG_TX_HARD_RESET, 0, NULL,
+					AMS_START) < 0) {
 				/*
 				 * likely a non-idle channel
 				 * TCPCI r2.0 v1.0 4.4.15:
@@ -4559,7 +4484,8 @@ void pd_task(void *u)
 			 */
 			if (pd[port].power_role == PD_ROLE_SOURCE) {
 				set_state_timeout(port,
-					get_time().val + PD_T_PS_HARD_RESET,
+						  get_time().val +
+							  PD_T_PS_HARD_RESET,
 						  PD_STATE_HARD_RESET_EXECUTE);
 			} else {
 				set_state(port, PD_STATE_HARD_RESET_EXECUTE);
@@ -4578,32 +4504,31 @@ void pd_task(void *u)
 
 			/* reset our own state machine */
 			pd_execute_hard_reset(port);
-			timeout = 10*MSEC;
+			timeout = 10 * MSEC;
 			break;
 #ifdef CONFIG_COMMON_RUNTIME
 		case PD_STATE_BIST_RX:
 			send_bist_cmd(port);
 			/* Delay at least enough for partner to finish BIST */
-			timeout = PD_T_BIST_RECEIVE + 20*MSEC;
+			timeout = PD_T_BIST_RECEIVE + 20 * MSEC;
 			/* Set to appropriate port disconnected state */
-			set_state(port, DUAL_ROLE_IF_ELSE(port,
-						PD_STATE_SNK_DISCONNECTED,
+			set_state(port, DUAL_ROLE_IF_ELSE(
+						port, PD_STATE_SNK_DISCONNECTED,
 						PD_STATE_SRC_DISCONNECTED));
 			break;
 		case PD_STATE_BIST_TX:
-			pd_transmit(port, TCPC_TX_BIST_MODE_2, 0, NULL,
+			pd_transmit(port, TCPCI_MSG_TX_BIST_MODE_2, 0, NULL,
 				    AMS_START);
 			/* Delay at least enough to finish sending BIST */
-			timeout = PD_T_BIST_TRANSMIT + 20*MSEC;
+			timeout = PD_T_BIST_TRANSMIT + 20 * MSEC;
 			/* Set to appropriate port disconnected state */
-			set_state(port, DUAL_ROLE_IF_ELSE(port,
-						PD_STATE_SNK_DISCONNECTED,
+			set_state(port, DUAL_ROLE_IF_ELSE(
+						port, PD_STATE_SNK_DISCONNECTED,
 						PD_STATE_SRC_DISCONNECTED));
 			break;
 #endif
 #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-		case PD_STATE_DRP_AUTO_TOGGLE:
-		{
+		case PD_STATE_DRP_AUTO_TOGGLE: {
 			enum pd_drp_next_states next_state;
 
 			assert(auto_toggle_supported);
@@ -4646,10 +4571,8 @@ void pd_task(void *u)
 			tcpm_get_cc(port, &cc1, &cc2);
 
 			next_state = drp_auto_toggle_next_state(
-						&pd[port].drp_sink_time,
-						pd[port].power_role,
-						drp_state[port],
-						cc1, cc2, false);
+				&pd[port].drp_sink_time, pd[port].power_role,
+				drp_state[port], cc1, cc2, false);
 
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
 			/*
@@ -4663,7 +4586,7 @@ void pd_task(void *u)
 #endif
 			if (next_state == DRP_TC_DEFAULT) {
 				if (PD_DEFAULT_STATE(port) ==
-						PD_STATE_SNK_DISCONNECTED)
+				    PD_STATE_SNK_DISCONNECTED)
 					next_state = DRP_TC_UNATTACHED_SNK;
 				else
 					next_state = DRP_TC_UNATTACHED_SRC;
@@ -4682,7 +4605,7 @@ void pd_task(void *u)
 
 				tcpm_set_cc(port, TYPEC_CC_RD);
 				pd_set_power_role(port, PD_ROLE_SINK);
-				timeout = 2*MSEC;
+				timeout = 2 * MSEC;
 				set_state(port, PD_STATE_SNK_DISCONNECTED);
 			} else if (next_state == DRP_TC_UNATTACHED_SRC) {
 				/*
@@ -4697,7 +4620,7 @@ void pd_task(void *u)
 
 				tcpm_set_cc(port, TYPEC_CC_RP);
 				pd_set_power_role(port, PD_ROLE_SOURCE);
-				timeout = 2*MSEC;
+				timeout = 2 * MSEC;
 				set_state(port, PD_STATE_SRC_DISCONNECTED);
 			} else {
 				/*
@@ -4712,13 +4635,6 @@ void pd_task(void *u)
 			break;
 		}
 #endif
-		case PD_STATE_ENTER_USB:
-			if (pd[port].last_state != pd[port].task_state) {
-				set_state_timeout(port,
-					get_time().val + PD_T_SENDER_RESPONSE,
-					READY_RETURN_STATE(port));
-			}
-			break;
 		default:
 			break;
 		}
@@ -4734,7 +4650,8 @@ void pd_task(void *u)
 			if (now.val >= pd[port].timeout) {
 				set_state(port, pd[port].timeout_state);
 				/* On a state timeout, run next state soon */
-				timeout = timeout < 10*MSEC ? timeout : 10*MSEC;
+				timeout = timeout < 10 * MSEC ? timeout :
+								10 * MSEC;
 			} else if (pd[port].timeout - now.val < timeout) {
 				timeout = pd[port].timeout - now.val;
 			}
@@ -4776,12 +4693,12 @@ void pd_task(void *u)
 		if (pd[port].power_role == PD_ROLE_SOURCE) {
 			/* Source: detect disconnect by monitoring CC */
 			tcpm_get_cc(port, &cc1, &cc2);
-			if (pd[port].polarity)
+			if (polarity_rm_dts(pd[port].polarity))
 				cc1 = cc2;
 			if (cc1 == TYPEC_CC_VOLT_OPEN) {
 				set_state(port, PD_STATE_SRC_DISCONNECTED);
 				/* Debouncing */
-				timeout = 10*MSEC;
+				timeout = 10 * MSEC;
 #ifdef CONFIG_USB_PD_DUAL_ROLE
 				/*
 				 * If Try.SRC is configured, then ATTACHED_SRC
@@ -4793,8 +4710,8 @@ void pd_task(void *u)
 					pd_set_power_role(port, PD_ROLE_SINK);
 					tcpm_set_cc(port, TYPEC_CC_RD);
 					/* Set timer for TryWait.SNK state */
-					pd[port].try_src_marker = get_time().val
-						+ PD_T_DEBOUNCE;
+					pd[port].try_src_marker =
+						get_time().val + PD_T_DEBOUNCE;
 					/* Advance to TryWait.SNK state */
 					set_state(port,
 						  PD_STATE_SNK_DISCONNECTED);
@@ -4819,7 +4736,7 @@ void pd_task(void *u)
 			/* Sink: detect disconnect by monitoring VBUS */
 			set_state(port, PD_STATE_SNK_DISCONNECTED);
 			/* set timeout small to reconnect fast */
-			timeout = 5*MSEC;
+			timeout = 5 * MSEC;
 		}
 #endif /* CONFIG_USB_PD_DUAL_ROLE */
 	}
@@ -4860,12 +4777,9 @@ static void pd_chipset_startup(void)
 	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
 		pd_set_dual_role_no_wakeup(i, PD_DRP_TOGGLE_OFF);
 		pd[i].flags |= PD_FLAGS_CHECK_IDENTITY;
-		/* Reset cable attributes and flags */
-		reset_pd_cable(i);
 		task_set_event(PD_PORT_TO_TASK_ID(i),
 			       PD_EVENT_POWER_STATE_CHANGE |
-				       PD_EVENT_UPDATE_DUAL_ROLE,
-			       0);
+				       PD_EVENT_UPDATE_DUAL_ROLE);
 	}
 	CPRINTS("PD:S5->S3");
 }
@@ -4879,8 +4793,7 @@ static void pd_chipset_shutdown(void)
 		pd_set_dual_role_no_wakeup(i, PD_DRP_FORCE_SINK);
 		task_set_event(PD_PORT_TO_TASK_ID(i),
 			       PD_EVENT_POWER_STATE_CHANGE |
-				       PD_EVENT_UPDATE_DUAL_ROLE,
-			       0);
+				       PD_EVENT_UPDATE_DUAL_ROLE);
 	}
 	CPRINTS("PD:S3->S5");
 }
@@ -4947,24 +4860,29 @@ int pd_is_port_enabled(int port)
 	}
 }
 
+void pd_set_error_recovery(int port)
+{
+	/* No-op for linking.  Can be implemented later if necessary */
+}
+
 #if defined(CONFIG_USB_PD_ALT_MODE) && !defined(CONFIG_USB_PD_ALT_MODE_DFP)
 void pd_send_hpd(int port, enum hpd_event hpd)
 {
 	uint32_t data[1];
-	int opos = pd_alt_mode(port, TCPC_TX_SOP, USB_SID_DISPLAYPORT);
+	int opos = pd_alt_mode(port, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT);
 	if (!opos)
 		return;
 
-	data[0] = VDO_DP_STATUS((hpd == hpd_irq),  /* IRQ_HPD */
-				(hpd != hpd_low),  /* HPD_HI|LOW */
-				0,		      /* request exit DP */
-				0,		      /* request exit USB */
-				0,		      /* MF pref */
-				1,                    /* enabled */
-				0,		      /* power low */
+	data[0] = VDO_DP_STATUS((hpd == hpd_irq), /* IRQ_HPD */
+				(hpd != hpd_low), /* HPD_HI|LOW */
+				0, /* request exit DP */
+				0, /* request exit USB */
+				0, /* MF pref */
+				1, /* enabled */
+				0, /* power low */
 				0x2);
-	pd_send_vdm(port, USB_SID_DISPLAYPORT,
-		    VDO_OPOS(opos) | CMD_ATTENTION, data, 1);
+	pd_send_vdm(port, USB_SID_DISPLAYPORT, VDO_OPOS(opos) | CMD_ATTENTION,
+		    data, 1);
 	/* Wait until VDM is done. */
 	while (pd[0].vdm_state > 0)
 		task_wait_event(USB_PD_RX_TMOUT_US *
@@ -4979,15 +4897,15 @@ int pd_fetch_acc_log_entry(int port)
 	/* Cannot send a VDM now, the host should retry */
 	if (pd[port].vdm_state > 0)
 		return pd[port].vdm_state == VDM_STATE_BUSY ?
-				EC_RES_BUSY : EC_RES_UNAVAILABLE;
+			       EC_RES_BUSY :
+			       EC_RES_UNAVAILABLE;
 
 	pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_GET_LOG, NULL, 0);
-	timeout.val = get_time().val + 75*MSEC;
+	timeout.val = get_time().val + 75 * MSEC;
 
 	/* Wait until VDM is done */
-	while ((pd[port].vdm_state > 0) &&
-	       (get_time().val < timeout.val))
-		task_wait_event(10*MSEC);
+	while ((pd[port].vdm_state > 0) && (get_time().val < timeout.val))
+		task_wait_event(10 * MSEC);
 
 	if (pd[port].vdm_state > 0)
 		return EC_RES_TIMEOUT;
@@ -5038,7 +4956,99 @@ void pd_update_contract(int port)
 
 #endif /* CONFIG_USB_PD_DUAL_ROLE */
 
-static int command_pd(int argc, char **argv)
+#if defined(CONFIG_CMD_PD) && defined(CONFIG_CMD_PD_FLASH)
+int hex8tou32(char *str, uint32_t *val)
+{
+	char *ptr = str;
+	uint32_t tmp = 0;
+
+	while (*ptr) {
+		char c = *ptr++;
+
+		if (c >= '0' && c <= '9')
+			tmp = (tmp << 4) + (c - '0');
+		else if (c >= 'A' && c <= 'F')
+			tmp = (tmp << 4) + (c - 'A' + 10);
+		else if (c >= 'a' && c <= 'f')
+			tmp = (tmp << 4) + (c - 'a' + 10);
+		else
+			return EC_ERROR_INVAL;
+	}
+	if (ptr != str + 8)
+		return EC_ERROR_INVAL;
+	*val = tmp;
+	return EC_SUCCESS;
+}
+
+/*
+ * Flash a USB PD device using the ChromeOS Vendor Defined Command.
+ *
+ * @param argc number arguments in argv. Must be greater than 3.
+ * @param argv [1] is the usb port
+ *             [2] unused
+ *             [3] is the command {"erase", "rebooot", "signature",
+ *                                 "info", "version", "write"}
+ *             [4] if command was "write", then this will be the
+ *                 start of the data that will be written.
+ * @return EC_SUCCESS on success, else EC_ERROR_PARAM_COUNT or EC_ERROR_PARAM2
+ *         on failure.
+ */
+static int remote_flashing(int argc, char **argv)
+{
+	int port, cnt, cmd;
+	uint32_t data[VDO_MAX_SIZE - 1];
+	char *e;
+	static int flash_offset[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+	if (argc < 4 || argc > (VDO_MAX_SIZE + 4 - 1))
+		return EC_ERROR_PARAM_COUNT;
+
+	port = strtoi(argv[1], &e, 10);
+	if (*e || port >= board_get_usb_pd_port_count())
+		return EC_ERROR_PARAM2;
+
+	cnt = 0;
+	if (!strcasecmp(argv[3], "erase")) {
+		cmd = VDO_CMD_FLASH_ERASE;
+		flash_offset[port] = 0;
+		ccprintf("ERASE ...");
+	} else if (!strcasecmp(argv[3], "reboot")) {
+		cmd = VDO_CMD_REBOOT;
+		ccprintf("REBOOT ...");
+	} else if (!strcasecmp(argv[3], "signature")) {
+		cmd = VDO_CMD_ERASE_SIG;
+		ccprintf("ERASE SIG ...");
+	} else if (!strcasecmp(argv[3], "info")) {
+		cmd = VDO_CMD_READ_INFO;
+		ccprintf("INFO...");
+	} else if (!strcasecmp(argv[3], "version")) {
+		cmd = VDO_CMD_VERSION;
+		ccprintf("VERSION...");
+	} else {
+		int i;
+
+		argc -= 3;
+		for (i = 0; i < argc; i++)
+			if (hex8tou32(argv[i + 3], data + i))
+				return EC_ERROR_INVAL;
+		cmd = VDO_CMD_FLASH_WRITE;
+		cnt = argc;
+		ccprintf("WRITE %d @%04x ...", argc * 4, flash_offset[port]);
+		flash_offset[port] += argc * 4;
+	}
+
+	pd_send_vdm(port, USB_VID_GOOGLE, cmd, data, cnt);
+
+	/* Wait until VDM is done */
+	while (pd[port].vdm_state > 0)
+		task_wait_event(100 * MSEC);
+
+	ccprintf("DONE %d\n", pd[port].vdm_state);
+	return EC_SUCCESS;
+}
+#endif /* defined(CONFIG_CMD_PD) && defined(CONFIG_CMD_PD_FLASH) */
+
+static int command_pd(int argc, const char **argv)
 {
 	int port;
 	char *e;
@@ -5061,7 +5071,6 @@ static int command_pd(int argc, char **argv)
 
 		return EC_SUCCESS;
 	}
-
 #ifdef CONFIG_CMD_PD
 #ifdef CONFIG_CMD_PD_DEV_DUMP_INFO
 	else if (!strncasecmp(argv[1], "rwhashtable", 3)) {
@@ -5163,6 +5172,8 @@ static int command_pd(int argc, char **argv)
 #endif
 		else
 			return EC_ERROR_PARAM3;
+	} else if (!strncasecmp(argv[2], "srccaps", 7)) {
+		pd_srccaps_dump(port);
 	} else if (!strncasecmp(argv[2], "ping", 4)) {
 		int enable;
 
@@ -5174,8 +5185,8 @@ static int command_pd(int argc, char **argv)
 		}
 
 		ccprintf("Pings %s\n",
-			 (pd[port].flags & PD_FLAGS_PING_ENABLED) ?
-			 "on" : "off");
+			 (pd[port].flags & PD_FLAGS_PING_ENABLED) ? "on" :
+								    "off");
 	} else if (!strncasecmp(argv[2], "vdm", 3)) {
 		if (argc < 4)
 			return EC_ERROR_PARAM_COUNT;
@@ -5190,11 +5201,11 @@ static int command_pd(int argc, char **argv)
 			pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_PING_ENABLE,
 				    &enable, 1);
 		} else if (!strncasecmp(argv[3], "curr", 4)) {
-			pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_CURRENT,
-				    NULL, 0);
+			pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_CURRENT, NULL,
+				    0);
 		} else if (!strncasecmp(argv[3], "vers", 4)) {
-			pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_VERSION,
-				    NULL, 0);
+			pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_VERSION, NULL,
+				    0);
 		} else {
 			return EC_ERROR_PARAM_COUNT;
 		}
@@ -5233,8 +5244,7 @@ static int command_pd(int argc, char **argv)
 			else if (!strcasecmp(argv[3], "sink"))
 				pd_set_dual_role(port, PD_DRP_FORCE_SINK);
 			else if (!strcasecmp(argv[3], "source"))
-				pd_set_dual_role(port,
-					PD_DRP_FORCE_SOURCE);
+				pd_set_dual_role(port, PD_DRP_FORCE_SOURCE);
 			else
 				return EC_ERROR_PARAM4;
 		}
@@ -5242,17 +5252,17 @@ static int command_pd(int argc, char **argv)
 #endif
 	} else
 #endif
-	if (!strncasecmp(argv[2], "state", 5)) {
+		if (!strncasecmp(argv[2], "state", 5)) {
 		ccprintf("Port C%d CC%d, %s - Role: %s-%s%s "
 			 "State: %d(%s), Flags: 0x%04x\n",
-			port, pd[port].polarity + 1,
-			pd_comm_is_enabled(port) ? "Ena" : "Dis",
-			pd[port].power_role == PD_ROLE_SOURCE ? "SRC" : "SNK",
-			pd[port].data_role == PD_ROLE_DFP ? "DFP" : "UFP",
-			(pd[port].flags & PD_FLAGS_VCONN_ON) ? "-VC" : "",
-			pd[port].task_state,
-			debug_level > 0 ? pd_get_task_state_name(port) : "",
-			pd[port].flags);
+			 port, pd[port].polarity + 1,
+			 pd_comm_is_enabled(port) ? "Ena" : "Dis",
+			 pd[port].power_role == PD_ROLE_SOURCE ? "SRC" : "SNK",
+			 pd[port].data_role == PD_ROLE_DFP ? "DFP" : "UFP",
+			 (pd[port].flags & PD_FLAGS_VCONN_ON) ? "-VC" : "",
+			 pd[port].task_state,
+			 debug_level > 0 ? pd_get_task_state_name(port) : "",
+			 pd[port].flags);
 	} else {
 		return EC_ERROR_PARAM1;
 	}
@@ -5280,7 +5290,7 @@ DECLARE_CONSOLE_COMMAND(pd, command_pd,
 			"\n\t<port> flash [erase|reboot|signature|info|version]"
 #endif /* CONFIG_CMD_PD_FLASH */
 #endif /* CONFIG_USB_PD_DUAL_ROLE */
-			,
+			"\n\t<port> srccaps",
 			"USB PD");
 
 #ifdef HAS_TASK_HOSTCMD
@@ -5300,9 +5310,8 @@ static enum ec_status hc_remote_flash(struct host_cmd_handler_args *args)
 	if (p->size + sizeof(*p) > args->params_size)
 		return EC_RES_INVALID_PARAM;
 
-#if defined(CONFIG_BATTERY) && \
-	(defined(CONFIG_BATTERY_PRESENT_CUSTOM) ||	\
-	 defined(CONFIG_BATTERY_PRESENT_GPIO))
+#if defined(CONFIG_BATTERY) && (defined(CONFIG_BATTERY_PRESENT_CUSTOM) || \
+				defined(CONFIG_BATTERY_PRESENT_GPIO))
 	/*
 	 * Do not allow PD firmware update if no battery and this port
 	 * is sinking power, because we will lose power.
@@ -5340,7 +5349,7 @@ static enum ec_status hc_remote_flash(struct host_cmd_handler_args *args)
 
 	case USB_PD_FW_ERASE_SIG:
 		pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_ERASE_SIG, NULL, 0);
-		timeout.val = get_time().val + 500*MSEC;
+		timeout.val = get_time().val + 500 * MSEC;
 		break;
 
 	case USB_PD_FW_FLASH_WRITE:
@@ -5352,12 +5361,12 @@ static enum ec_status hc_remote_flash(struct host_cmd_handler_args *args)
 		for (i = 0; i < size; i += VDO_MAX_SIZE - 1) {
 			pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_FLASH_WRITE,
 				    data + i, MIN(size - i, VDO_MAX_SIZE - 1));
-			timeout.val = get_time().val + 500*MSEC;
+			timeout.val = get_time().val + 500 * MSEC;
 
 			/* Wait until VDM is done */
 			while ((pd[port].vdm_state > 0) &&
 			       (get_time().val < timeout.val))
-				task_wait_event(10*MSEC);
+				task_wait_event(10 * MSEC);
 
 			if (pd[port].vdm_state > 0)
 				return EC_RES_TIMEOUT;
@@ -5371,7 +5380,7 @@ static enum ec_status hc_remote_flash(struct host_cmd_handler_args *args)
 
 	/* Wait until VDM is done or timeout */
 	while ((pd[port].vdm_state > 0) && (get_time().val < timeout.val))
-		task_wait_event(50*MSEC);
+		task_wait_event(50 * MSEC);
 
 	if ((pd[port].vdm_state > 0) ||
 	    (pd[port].vdm_state == VDM_STATE_ERR_TMOUT))
@@ -5381,12 +5390,8 @@ static enum ec_status hc_remote_flash(struct host_cmd_handler_args *args)
 
 	return rv;
 }
-DECLARE_HOST_COMMAND(EC_CMD_USB_PD_FW_UPDATE,
-		     hc_remote_flash,
-		     EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_USB_PD_FW_UPDATE, hc_remote_flash, EC_VER_MASK(0));
 #endif /* CONFIG_HOSTCMD_FLASHPD */
 
 #endif /* HAS_TASK_HOSTCMD */
-
-
 #endif /* CONFIG_COMMON_RUNTIME */
diff --git a/common/usb_pd_tcpc.c b/common/usb_pd_tcpc.c
index 2878e53574..a9a4d1d5a5 100644
--- a/common/usb_pd_tcpc.c
+++ b/common/usb_pd_tcpc.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,17 +15,17 @@
 #include "registers.h"
 #include "system.h"
 #include "task.h"
-#include "tcpci.h"
-#include "tcpm.h"
+#include "tcpm/tcpci.h"
+#include "tcpm/tcpm.h"
 #include "timer.h"
-#include "util.h"
 #include "usb_pd.h"
 #include "usb_pd_config.h"
 #include "usb_pd_tcpm.h"
+#include "util.h"
 
 #ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 /*
  * Debug log level - higher number == more log
@@ -45,93 +45,93 @@ static const int debug_level;
 #endif
 
 /* Encode 5 bits using Biphase Mark Coding */
-#define BMC(x)   ((x &  1 ? 0x001 : 0x3FF) \
-		^ (x &  2 ? 0x004 : 0x3FC) \
-		^ (x &  4 ? 0x010 : 0x3F0) \
-		^ (x &  8 ? 0x040 : 0x3C0) \
-		^ (x & 16 ? 0x100 : 0x300))
+#define BMC(x)                                               \
+	((x & 1 ? 0x001 : 0x3FF) ^ (x & 2 ? 0x004 : 0x3FC) ^ \
+	 (x & 4 ? 0x010 : 0x3F0) ^ (x & 8 ? 0x040 : 0x3C0) ^ \
+	 (x & 16 ? 0x100 : 0x300))
 
 /* 4b/5b + Bimark Phase encoding */
 static const uint16_t bmc4b5b[] = {
-/* 0 = 0000 */ BMC(0x1E) /* 11110 */,
-/* 1 = 0001 */ BMC(0x09) /* 01001 */,
-/* 2 = 0010 */ BMC(0x14) /* 10100 */,
-/* 3 = 0011 */ BMC(0x15) /* 10101 */,
-/* 4 = 0100 */ BMC(0x0A) /* 01010 */,
-/* 5 = 0101 */ BMC(0x0B) /* 01011 */,
-/* 6 = 0110 */ BMC(0x0E) /* 01110 */,
-/* 7 = 0111 */ BMC(0x0F) /* 01111 */,
-/* 8 = 1000 */ BMC(0x12) /* 10010 */,
-/* 9 = 1001 */ BMC(0x13) /* 10011 */,
-/* A = 1010 */ BMC(0x16) /* 10110 */,
-/* B = 1011 */ BMC(0x17) /* 10111 */,
-/* C = 1100 */ BMC(0x1A) /* 11010 */,
-/* D = 1101 */ BMC(0x1B) /* 11011 */,
-/* E = 1110 */ BMC(0x1C) /* 11100 */,
-/* F = 1111 */ BMC(0x1D) /* 11101 */,
-/* Sync-1      K-code       11000 Startsynch #1 */
-/* Sync-2      K-code       10001 Startsynch #2 */
-/* RST-1       K-code       00111 Hard Reset #1 */
-/* RST-2       K-code       11001 Hard Reset #2 */
-/* EOP         K-code       01101 EOP End Of Packet */
-/* Reserved    Error        00000 */
-/* Reserved    Error        00001 */
-/* Reserved    Error        00010 */
-/* Reserved    Error        00011 */
-/* Reserved    Error        00100 */
-/* Reserved    Error        00101 */
-/* Reserved    Error        00110 */
-/* Reserved    Error        01000 */
-/* Reserved    Error        01100 */
-/* Reserved    Error        10000 */
-/* Reserved    Error        11111 */
+	/* 0 = 0000 */ BMC(0x1E) /* 11110 */,
+	/* 1 = 0001 */ BMC(0x09) /* 01001 */,
+	/* 2 = 0010 */ BMC(0x14) /* 10100 */,
+	/* 3 = 0011 */ BMC(0x15) /* 10101 */,
+	/* 4 = 0100 */ BMC(0x0A) /* 01010 */,
+	/* 5 = 0101 */ BMC(0x0B) /* 01011 */,
+	/* 6 = 0110 */ BMC(0x0E) /* 01110 */,
+	/* 7 = 0111 */ BMC(0x0F) /* 01111 */,
+	/* 8 = 1000 */ BMC(0x12) /* 10010 */,
+	/* 9 = 1001 */ BMC(0x13) /* 10011 */,
+	/* A = 1010 */ BMC(0x16) /* 10110 */,
+	/* B = 1011 */ BMC(0x17) /* 10111 */,
+	/* C = 1100 */ BMC(0x1A) /* 11010 */,
+	/* D = 1101 */ BMC(0x1B) /* 11011 */,
+	/* E = 1110 */ BMC(0x1C) /* 11100 */,
+	/* F = 1111 */ BMC(0x1D) /* 11101 */,
+	/* Sync-1      K-code       11000 Startsynch #1 */
+	/* Sync-2      K-code       10001 Startsynch #2 */
+	/* RST-1       K-code       00111 Hard Reset #1 */
+	/* RST-2       K-code       11001 Hard Reset #2 */
+	/* EOP         K-code       01101 EOP End Of Packet */
+	/* Reserved    Error        00000 */
+	/* Reserved    Error        00001 */
+	/* Reserved    Error        00010 */
+	/* Reserved    Error        00011 */
+	/* Reserved    Error        00100 */
+	/* Reserved    Error        00101 */
+	/* Reserved    Error        00110 */
+	/* Reserved    Error        01000 */
+	/* Reserved    Error        01100 */
+	/* Reserved    Error        10000 */
+	/* Reserved    Error        11111 */
 };
 
 static const uint8_t dec4b5b[] = {
-/* Error    */ 0x10 /* 00000 */,
-/* Error    */ 0x10 /* 00001 */,
-/* Error    */ 0x10 /* 00010 */,
-/* Error    */ 0x10 /* 00011 */,
-/* Error    */ 0x10 /* 00100 */,
-/* Error    */ 0x10 /* 00101 */,
-/* Error    */ 0x10 /* 00110 */,
-/* RST-1    */ 0x13 /* 00111 K-code: Hard Reset #1 */,
-/* Error    */ 0x10 /* 01000 */,
-/* 1 = 0001 */ 0x01 /* 01001 */,
-/* 4 = 0100 */ 0x04 /* 01010 */,
-/* 5 = 0101 */ 0x05 /* 01011 */,
-/* Error    */ 0x10 /* 01100 */,
-/* EOP      */ 0x15 /* 01101 K-code: EOP End Of Packet */,
-/* 6 = 0110 */ 0x06 /* 01110 */,
-/* 7 = 0111 */ 0x07 /* 01111 */,
-/* Error    */ 0x10 /* 10000 */,
-/* Sync-2   */ 0x12 /* 10001 K-code: Startsynch #2 */,
-/* 8 = 1000 */ 0x08 /* 10010 */,
-/* 9 = 1001 */ 0x09 /* 10011 */,
-/* 2 = 0010 */ 0x02 /* 10100 */,
-/* 3 = 0011 */ 0x03 /* 10101 */,
-/* A = 1010 */ 0x0A /* 10110 */,
-/* B = 1011 */ 0x0B /* 10111 */,
-/* Sync-1   */ 0x11 /* 11000 K-code: Startsynch #1 */,
-/* RST-2    */ 0x14 /* 11001 K-code: Hard Reset #2 */,
-/* C = 1100 */ 0x0C /* 11010 */,
-/* D = 1101 */ 0x0D /* 11011 */,
-/* E = 1110 */ 0x0E /* 11100 */,
-/* F = 1111 */ 0x0F /* 11101 */,
-/* 0 = 0000 */ 0x00 /* 11110 */,
-/* Error    */ 0x10 /* 11111 */,
+	/* Error    */ 0x10 /* 00000 */,
+	/* Error    */ 0x10 /* 00001 */,
+	/* Error    */ 0x10 /* 00010 */,
+	/* Error    */ 0x10 /* 00011 */,
+	/* Error    */ 0x10 /* 00100 */,
+	/* Error    */ 0x10 /* 00101 */,
+	/* Error    */ 0x10 /* 00110 */,
+	/* RST-1    */ 0x13 /* 00111 K-code: Hard Reset #1 */,
+	/* Error    */ 0x10 /* 01000 */,
+	/* 1 = 0001 */ 0x01 /* 01001 */,
+	/* 4 = 0100 */ 0x04 /* 01010 */,
+	/* 5 = 0101 */ 0x05 /* 01011 */,
+	/* Error    */ 0x10 /* 01100 */,
+	/* EOP      */ 0x15 /* 01101 K-code: EOP End Of Packet */,
+	/* 6 = 0110 */ 0x06 /* 01110 */,
+	/* 7 = 0111 */ 0x07 /* 01111 */,
+	/* Error    */ 0x10 /* 10000 */,
+	/* Sync-2   */ 0x12 /* 10001 K-code: Startsynch #2 */,
+	/* 8 = 1000 */ 0x08 /* 10010 */,
+	/* 9 = 1001 */ 0x09 /* 10011 */,
+	/* 2 = 0010 */ 0x02 /* 10100 */,
+	/* 3 = 0011 */ 0x03 /* 10101 */,
+	/* A = 1010 */ 0x0A /* 10110 */,
+	/* B = 1011 */ 0x0B /* 10111 */,
+	/* Sync-1   */ 0x11 /* 11000 K-code: Startsynch #1 */,
+	/* RST-2    */ 0x14 /* 11001 K-code: Hard Reset #2 */,
+	/* C = 1100 */ 0x0C /* 11010 */,
+	/* D = 1101 */ 0x0D /* 11011 */,
+	/* E = 1110 */ 0x0E /* 11100 */,
+	/* F = 1111 */ 0x0F /* 11101 */,
+	/* 0 = 0000 */ 0x00 /* 11110 */,
+	/* Error    */ 0x10 /* 11111 */,
 };
 
 /* Start of Packet sequence : three Sync-1 K-codes, then one Sync-2 K-code */
-#define PD_SOP (PD_SYNC1 | (PD_SYNC1<<5) | (PD_SYNC1<<10) | (PD_SYNC2<<15))
-#define PD_SOP_PRIME	(PD_SYNC1 | (PD_SYNC1<<5) | \
-			(PD_SYNC3<<10) | (PD_SYNC3<<15))
-#define PD_SOP_PRIME_PRIME	(PD_SYNC1 | (PD_SYNC3<<5) | \
-				(PD_SYNC1<<10) | (PD_SYNC3<<15))
+#define PD_SOP \
+	(PD_SYNC1 | (PD_SYNC1 << 5) | (PD_SYNC1 << 10) | (PD_SYNC2 << 15))
+#define PD_SOP_PRIME \
+	(PD_SYNC1 | (PD_SYNC1 << 5) | (PD_SYNC3 << 10) | (PD_SYNC3 << 15))
+#define PD_SOP_PRIME_PRIME \
+	(PD_SYNC1 | (PD_SYNC3 << 5) | (PD_SYNC1 << 10) | (PD_SYNC3 << 15))
 
 /* Hard Reset sequence : three RST-1 K-codes, then one RST-2 K-code */
-#define PD_HARD_RESET (PD_RST1 | (PD_RST1 << 5) |\
-		      (PD_RST1 << 10) | (PD_RST2 << 15))
+#define PD_HARD_RESET \
+	(PD_RST1 | (PD_RST1 << 5) | (PD_RST1 << 10) | (PD_RST2 << 15))
 
 /*
  * Polarity based on 'DFP Perspective' (see table USB Type-C Cable and Connector
@@ -159,11 +159,11 @@ static const uint8_t dec4b5b[] = {
 #endif
 
 #ifndef CC_RA
-#define CC_RA(port, cc, sel)  (cc < PD_SRC_RD_THRESHOLD)
+#define CC_RA(port, cc, sel) (cc < PD_SRC_RD_THRESHOLD)
 #endif
 #define CC_RD(cc) ((cc >= PD_SRC_RD_THRESHOLD) && (cc < PD_SRC_VNC))
 #ifndef CC_NC
-#define CC_NC(port, cc, sel)  (cc >= PD_SRC_VNC)
+#define CC_NC(port, cc, sel) (cc >= PD_SRC_VNC)
 #endif
 
 /*
@@ -180,16 +180,16 @@ static const uint8_t dec4b5b[] = {
 #define PD_SNK_VA PD_SNK_VA_MV
 #endif
 
-#define CC_RP(cc)  (cc >= PD_SNK_VA)
+#define CC_RP(cc) (cc >= PD_SNK_VA)
 
 /*
  * Type C power source charge current limits are identified by their cc
  * voltage (set by selecting the proper Rd resistor). Any voltage below
  * TYPE_C_SRC_500_THRESHOLD will not be identified as a type C charger.
  */
-#define TYPE_C_SRC_500_THRESHOLD	PD_SRC_RD_THRESHOLD
-#define TYPE_C_SRC_1500_THRESHOLD	660  /* mV */
-#define TYPE_C_SRC_3000_THRESHOLD	1230 /* mV */
+#define TYPE_C_SRC_500_THRESHOLD PD_SRC_RD_THRESHOLD
+#define TYPE_C_SRC_1500_THRESHOLD 660 /* mV */
+#define TYPE_C_SRC_3000_THRESHOLD 1230 /* mV */
 
 /* Convert TCPC Alert register to index into pd.alert[] */
 #define ALERT_REG_TO_INDEX(reg) (reg - TCPC_REG_ALERT)
@@ -254,12 +254,12 @@ static struct pd_port_controller {
 #endif
 
 	/* Last received */
-	int rx_head[RX_BUFFER_SIZE+1];
-	uint32_t rx_payload[RX_BUFFER_SIZE+1][7];
+	int rx_head[RX_BUFFER_SIZE + 1];
+	uint32_t rx_payload[RX_BUFFER_SIZE + 1][7];
 	int rx_buf_head, rx_buf_tail;
 
 	/* Next transmit */
-	enum tcpm_transmit_type tx_type;
+	enum tcpci_msg_type tx_type;
 	uint16_t tx_head;
 	uint32_t tx_payload[7];
 	const uint32_t *tx_data;
@@ -309,7 +309,7 @@ int encode_word(int port, int off, uint32_t val32)
 
 /* prepare a 4b/5b-encoded PD message to send */
 int prepare_message(int port, uint16_t header, uint8_t cnt,
-		   const uint32_t *data)
+		    const uint32_t *data)
 {
 	int off, i;
 	/* 64-bit preamble */
@@ -387,8 +387,8 @@ static int send_validate_message(int port, uint16_t header,
 	uint8_t expected_msg_id = PD_HEADER_ID(header);
 	uint8_t cnt = PD_HEADER_CNT(header);
 	int retries = PD_HEADER_TYPE(header) == PD_DATA_SOURCE_CAP ?
-				    0 :
-				    CONFIG_PD_RETRY_COUNT;
+			      0 :
+			      CONFIG_PD_RETRY_COUNT;
 
 	/* retry 3 times if we are not getting a valid answer */
 	for (r = 0; r <= retries; r++) {
@@ -464,7 +464,7 @@ static int send_validate_message(int port, uint16_t header,
 static void send_goodcrc(int port, int id)
 {
 	uint16_t header = PD_HEADER(PD_CTRL_GOOD_CRC, pd[port].power_role,
-			pd[port].data_role, id, 0, 0, 0);
+				    pd[port].data_role, id, 0, 0, 0);
 	int bit_len = prepare_message(port, header, 0, NULL);
 
 	if (pd_start_tx(port, pd[port].polarity, bit_len) < 0)
@@ -536,7 +536,7 @@ static void bist_mode_2_tx(int port)
 	 * build context buffer with 5 bytes, where the data is
 	 * alternating 1's and 0's.
 	 */
-	bit = pd_write_sym(port, 0,   BMC(0x15));
+	bit = pd_write_sym(port, 0, BMC(0x15));
 	bit = pd_write_sym(port, bit, BMC(0x0a));
 	bit = pd_write_sym(port, bit, BMC(0x15));
 	bit = pd_write_sym(port, bit, BMC(0x0a));
@@ -566,10 +566,9 @@ static inline int decode_short(int port, int off, uint16_t *val16)
 		dec4b5b[(w >> 15) & 0x1f], dec4b5b[(w >> 10) & 0x1f],
 		dec4b5b[(w >>  5) & 0x1f], dec4b5b[(w >>  0) & 0x1f]);
 #endif
-	*val16 = dec4b5b[w & 0x1f] |
-		(dec4b5b[(w >>  5) & 0x1f] << 4) |
-		(dec4b5b[(w >> 10) & 0x1f] << 8) |
-		(dec4b5b[(w >> 15) & 0x1f] << 12);
+	*val16 = dec4b5b[w & 0x1f] | (dec4b5b[(w >> 5) & 0x1f] << 4) |
+		 (dec4b5b[(w >> 10) & 0x1f] << 8) |
+		 (dec4b5b[(w >> 15) & 0x1f] << 12);
 	return end;
 }
 
@@ -674,7 +673,7 @@ int pd_analyze_rx(int port, uint32_t *payload)
 #else /* CONFIG_USB_VPD || CONFIG_USB_CTVPD */
 #ifdef CONFIG_USB_PD_DECODE_SOP
 		if (val == PD_SOP || val == PD_SOP_PRIME ||
-						val == PD_SOP_PRIME_PRIME)
+		    val == PD_SOP_PRIME_PRIME)
 			break;
 #else
 		if (val == PD_SOP) {
@@ -721,11 +720,11 @@ int pd_analyze_rx(int port, uint32_t *payload)
 #ifdef CONFIG_USB_PD_DECODE_SOP
 	/* Encode message address */
 	if (val == PD_SOP) {
-		phs.head |= PD_HEADER_SOP(PD_MSG_SOP);
+		phs.head |= PD_HEADER_SOP(TCPCI_MSG_SOP);
 	} else if (val == PD_SOP_PRIME) {
-		phs.head |= PD_HEADER_SOP(PD_MSG_SOP_PRIME);
+		phs.head |= PD_HEADER_SOP(TCPCI_MSG_SOP_PRIME);
 	} else if (val == PD_SOP_PRIME_PRIME) {
-		phs.head |= PD_HEADER_SOP(PD_MSG_SOP_PRIME_PRIME);
+		phs.head |= PD_HEADER_SOP(TCPCI_MSG_SOP_PRIME_PRIME);
 	} else {
 		msg = "SOP*";
 		goto packet_err;
@@ -734,7 +733,7 @@ int pd_analyze_rx(int port, uint32_t *payload)
 
 	/* read payload data */
 	for (p = 0; p < cnt && bit > 0; p++) {
-		bit = decode_word(port, bit, payload+p);
+		bit = decode_word(port, bit, payload + p);
 		crc32_hash32(payload[p]);
 	}
 	ccrc = crc32_result();
@@ -801,7 +800,7 @@ static int cc_voltage_to_status(int port, int cc_volt, int cc_sel)
 			return TYPEC_CC_VOLT_RA;
 		else
 			return TYPEC_CC_VOLT_RD;
-	/* If we have a pull-down, then we are sink, check for Rp. */
+		/* If we have a pull-down, then we are sink, check for Rp. */
 	}
 #ifdef CONFIG_USB_PD_DUAL_ROLE
 	else if (pd[port].cc_pull == TYPEC_CC_RD) {
@@ -843,9 +842,8 @@ int tcpc_run(int port, int evt)
 	/* incoming packet ? */
 	if (pd_rx_started(port) && pd[port].rx_enabled) {
 		/* Get message and place at RX buffer head */
-		res = pd[port].rx_head[pd[port].rx_buf_head] =
-			pd_analyze_rx(port,
-				pd[port].rx_payload[pd[port].rx_buf_head]);
+		res = pd[port].rx_head[pd[port].rx_buf_head] = pd_analyze_rx(
+			port, pd[port].rx_payload[pd[port].rx_buf_head]);
 		pd_rx_complete(port);
 
 		/*
@@ -868,19 +866,18 @@ int tcpc_run(int port, int evt)
 	if ((evt & PD_EVENT_TX) && pd[port].rx_enabled) {
 		switch (pd[port].tx_type) {
 #if defined(CONFIG_USB_VPD) || defined(CONFIG_USB_CTVPD)
-		case TCPC_TX_SOP_PRIME:
+		case TCPCI_MSG_SOP_PRIME:
 #else
-		case TCPC_TX_SOP:
+		case TCPCI_MSG_SOP:
 #endif
-			res = send_validate_message(port,
-					pd[port].tx_head,
-					pd[port].tx_data);
+			res = send_validate_message(port, pd[port].tx_head,
+						    pd[port].tx_data);
 			break;
-		case TCPC_TX_BIST_MODE_2:
+		case TCPCI_MSG_TX_BIST_MODE_2:
 			bist_mode_2_tx(port);
 			res = 0;
 			break;
-		case TCPC_TX_HARD_RESET:
+		case TCPCI_MSG_TX_HARD_RESET:
 			res = send_hard_reset(port);
 			break;
 		default:
@@ -929,11 +926,11 @@ int tcpc_run(int port, int evt)
 	 */
 	return (get_time().val >= pd[port].low_power_ts.val &&
 		pd[port].cc_pull == TYPEC_CC_RD &&
-		cc_is_open(pd[port].cc_status[0], pd[port].cc_status[1]))
-		       ? 200 * MSEC
-		       : 10 * MSEC;
+		cc_is_open(pd[port].cc_status[0], pd[port].cc_status[1])) ?
+		       200 * MSEC :
+		       10 * MSEC;
 #else
-	return 10*MSEC;
+	return 10 * MSEC;
 #endif
 }
 
@@ -941,7 +938,7 @@ int tcpc_run(int port, int evt)
 void pd_task(void *u)
 {
 	int port = TASK_ID_TO_PD_PORT(task_get_current());
-	int timeout = 10*MSEC;
+	int timeout = 10 * MSEC;
 	int evt;
 
 	/* initialize phy task */
@@ -962,7 +959,7 @@ void pd_task(void *u)
 
 void pd_rx_event(int port)
 {
-	task_set_event(PD_PORT_TO_TASK_ID(port), TASK_EVENT_WAKE, 0);
+	task_set_event(PD_PORT_TO_TASK_ID(port), TASK_EVENT_WAKE);
 }
 
 int tcpc_alert_status(int port, int *alert)
@@ -1024,8 +1021,8 @@ int tcpc_set_cc(int port, int pull)
 	 * because we only want to go into low power mode when we are not
 	 * dual-role toggling.
 	 */
-	pd[port].low_power_ts.val = get_time().val +
-					2*(PD_T_DRP_SRC + PD_T_DRP_SNK);
+	pd[port].low_power_ts.val =
+		get_time().val + 2 * (PD_T_DRP_SRC + PD_T_DRP_SNK);
 #endif
 
 	/*
@@ -1041,13 +1038,13 @@ int tcpc_set_cc(int port, int pull)
 #ifdef CONFIG_USB_POWER_DELIVERY
 	tcpc_run(port, PD_EVENT_CC);
 #else
-	task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_CC, 0);
+	task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_CC);
 #endif
 	return EC_SUCCESS;
 }
 
 int tcpc_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2)
+		enum tcpc_cc_voltage_status *cc2)
 {
 	*cc2 = pd[port].cc_status[1];
 	*cc1 = pd[port].cc_status[0];
@@ -1128,7 +1125,7 @@ int tcpc_set_rx_enable(int port, int enable)
 	return EC_SUCCESS;
 }
 
-int tcpc_transmit(int port, enum tcpm_transmit_type type, uint16_t header,
+int tcpc_transmit(int port, enum tcpci_msg_type type, uint16_t header,
 		  const uint32_t *data)
 {
 	/* Store data to transmit and wake task to send it */
@@ -1139,7 +1136,7 @@ int tcpc_transmit(int port, enum tcpm_transmit_type type, uint16_t header,
 #ifdef CONFIG_USB_POWER_DELIVERY
 	tcpc_run(port, PD_EVENT_TX);
 #else
-	task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_TX, 0);
+	task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_TX);
 #endif
 	return EC_SUCCESS;
 }
@@ -1184,8 +1181,9 @@ void tcpc_init(int port)
 
 	/* Initialize physical layer */
 	pd_hw_init(port, PD_ROLE_DEFAULT(port));
-	pd[port].cc_pull = PD_ROLE_DEFAULT(port) ==
-		PD_ROLE_SOURCE ? TYPEC_CC_RP : TYPEC_CC_RD;
+	pd[port].cc_pull = PD_ROLE_DEFAULT(port) == PD_ROLE_SOURCE ?
+				   TYPEC_CC_RP :
+				   TYPEC_CC_RD;
 #ifdef TCPC_LOW_POWER
 	/* Don't use low power immediately after boot */
 	pd[port].low_power_ts.val = get_time().val + SECOND;
@@ -1196,16 +1194,15 @@ void tcpc_init(int port)
 
 	/* make initial readings of CC voltages */
 	for (i = 0; i < 2; i++) {
-		pd[port].cc_status[i] = cc_voltage_to_status(port,
-							     pd_adc_read(port, i),
-							     i);
+		pd[port].cc_status[i] =
+			cc_voltage_to_status(port, pd_adc_read(port, i), i);
 	}
 
 #ifdef CONFIG_USB_PD_TCPC_TRACK_VBUS
 #if CONFIG_USB_PD_PORT_MAX_COUNT >= 2
-	tcpc_set_power_status(port, !gpio_get_level(port ?
-			      GPIO_USB_C1_VBUS_WAKE_L :
-			      GPIO_USB_C0_VBUS_WAKE_L));
+	tcpc_set_power_status(port,
+			      !gpio_get_level(port ? GPIO_USB_C1_VBUS_WAKE_L :
+						     GPIO_USB_C0_VBUS_WAKE_L));
 #else
 	tcpc_set_power_status(port, !gpio_get_level(GPIO_USB_C0_VBUS_WAKE_L));
 #endif /* CONFIG_USB_PD_PORT_MAX_COUNT >= 2 */
@@ -1223,7 +1220,7 @@ void tcpc_init(int port)
 void pd_vbus_evt_p0(enum gpio_signal signal)
 {
 	tcpc_set_power_status(TASK_ID_TO_PD_PORT(TASK_ID_PD_C0),
-				 !gpio_get_level(GPIO_USB_C0_VBUS_WAKE_L));
+			      !gpio_get_level(GPIO_USB_C0_VBUS_WAKE_L));
 	task_wake(TASK_ID_PD_C0);
 }
 
@@ -1234,7 +1231,7 @@ void pd_vbus_evt_p1(enum gpio_signal signal)
 		return;
 
 	tcpc_set_power_status(TASK_ID_TO_PD_PORT(TASK_ID_PD_C1),
-				 !gpio_get_level(GPIO_USB_C1_VBUS_WAKE_L));
+			      !gpio_get_level(GPIO_USB_C1_VBUS_WAKE_L));
 	task_wake(TASK_ID_PD_C1);
 }
 #endif /* PD_PORT_COUNT >= 2 */
@@ -1277,8 +1274,8 @@ static void tcpc_i2c_write(int port, int reg, int len, uint8_t *payload)
 		tcpc_alert_mask_set(port, alert);
 		break;
 	case TCPC_REG_RX_DETECT:
-		tcpc_set_rx_enable(port, payload[1] &
-					 TCPC_REG_RX_DETECT_SOP_HRST_MASK);
+		tcpc_set_rx_enable(
+			port, payload[1] & TCPC_REG_RX_DETECT_SOP_HRST_MASK);
 		break;
 	case TCPC_REG_POWER_STATUS_MASK:
 		tcpc_set_power_status_mask(port, payload[1]);
@@ -1308,12 +1305,11 @@ static int tcpc_i2c_read(int port, int reg, uint8_t *payload)
 	case TCPC_REG_CC_STATUS:
 		tcpc_get_cc(port, &cc1, &cc2);
 		payload[0] = TCPC_REG_CC_STATUS_SET(
-				pd[port].cc_pull == TYPEC_CC_RD,
-				pd[port].cc_status[0], pd[port].cc_status[1]);
+			pd[port].cc_pull == TYPEC_CC_RD, pd[port].cc_status[0],
+			pd[port].cc_status[1]);
 		return 1;
 	case TCPC_REG_ROLE_CTRL:
-		payload[0] = TCPC_REG_ROLE_CTRL_SET(0, 0,
-						    pd[port].cc_pull,
+		payload[0] = TCPC_REG_ROLE_CTRL_SET(0, 0, pd[port].cc_pull,
 						    pd[port].cc_pull);
 		return 1;
 	case TCPC_REG_TCPC_CTRL:
@@ -1325,7 +1321,8 @@ static int tcpc_i2c_read(int port, int reg, uint8_t *payload)
 		return 1;
 	case TCPC_REG_RX_DETECT:
 		payload[0] = pd[port].rx_enabled ?
-				TCPC_REG_RX_DETECT_SOP_HRST_MASK : 0;
+				     TCPC_REG_RX_DETECT_SOP_HRST_MASK :
+				     0;
 		return 1;
 	case TCPC_REG_ALERT:
 		tcpc_alert_status(port, &alert);
@@ -1337,13 +1334,14 @@ static int tcpc_i2c_read(int port, int reg, uint8_t *payload)
 		payload[1] = (pd[port].alert_mask >> 8) & 0xff;
 		return 2;
 	case TCPC_REG_RX_BYTE_CNT:
-		payload[0] = 3 + 4 *
-			PD_HEADER_CNT(pd[port].rx_head[pd[port].rx_buf_tail]);
+		payload[0] =
+			3 + 4 * PD_HEADER_CNT(
+					pd[port].rx_head[pd[port].rx_buf_tail]);
 		return 1;
 	case TCPC_REG_RX_HDR:
 		payload[0] = pd[port].rx_head[pd[port].rx_buf_tail] & 0xff;
-		payload[1] =
-			(pd[port].rx_head[pd[port].rx_buf_tail] >> 8) & 0xff;
+		payload[1] = (pd[port].rx_head[pd[port].rx_buf_tail] >> 8) &
+			     0xff;
 		return 2;
 	case TCPC_REG_RX_DATA:
 		memcpy(payload, pd[port].rx_payload[pd[port].rx_buf_tail],
@@ -1408,7 +1406,7 @@ void tcpc_i2c_process(int read, int port, int len, uint8_t *payload,
 #endif
 
 #ifdef CONFIG_COMMON_RUNTIME
-static int command_tcpc(int argc, char **argv)
+static int command_tcpc(int argc, const char **argv)
 {
 	int port;
 	char *e;
@@ -1452,12 +1450,12 @@ static int command_tcpc(int argc, char **argv)
 	} else if (!strncasecmp(argv[2], "state", 5)) {
 		ccprintf("Port C%d, %s - CC:%d, CC0:%d, CC1:%d\n"
 			 "Alert: 0x%02x Mask: 0x%04x\n"
-			 "Power Status: 0x%02x Mask: 0x%02x\n", port,
-			 pd[port].rx_enabled ? "Ena" : "Dis",
-			 pd[port].cc_pull,
-			 pd[port].cc_status[0], pd[port].cc_status[1],
-			 pd[port].alert, pd[port].alert_mask,
-			 pd[port].power_status, pd[port].power_status_mask);
+			 "Power Status: 0x%02x Mask: 0x%02x\n",
+			 port, pd[port].rx_enabled ? "Ena" : "Dis",
+			 pd[port].cc_pull, pd[port].cc_status[0],
+			 pd[port].cc_status[1], pd[port].alert,
+			 pd[port].alert_mask, pd[port].power_status,
+			 pd[port].power_status_mask);
 	}
 
 	return EC_SUCCESS;
diff --git a/common/usb_port_power_dumb.c b/common/usb_port_power_dumb.c
index be60f6727f..cfdc016662 100644
--- a/common/usb_port_power_dumb.c
+++ b/common/usb_port_power_dumb.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,17 +16,22 @@
 #include "util.h"
 
 #define CPUTS(outstr) cputs(CC_USBCHARGE, outstr)
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
 
 static uint8_t charge_mode[USB_PORT_COUNT];
 
 static void usb_port_set_enabled(int port_id, int en)
 {
-	gpio_set_level(usb_port_enable[port_id], en);
-	charge_mode[port_id] = en;
+	/*
+	 * Only enable valid ports.
+	 */
+	if (usb_port_enable[port_id] >= 0) {
+		gpio_or_ioex_set_level(usb_port_enable[port_id], en);
+		charge_mode[port_id] = en;
+	}
 }
 
-static void usb_port_all_ports_on(void)
+__maybe_unused static void usb_port_all_ports_on(void)
 {
 	int i;
 	for (i = 0; i < USB_PORT_COUNT; i++)
@@ -70,20 +75,19 @@ usb_port_command_set_mode(struct host_cmd_handler_args *args)
 {
 	const struct ec_params_usb_charge_set_mode *p = args->params;
 
-	if (usb_charge_set_mode(p->usb_port_id, p->mode,
-		p->inhibit_charge) != EC_SUCCESS)
+	if (usb_charge_set_mode(p->usb_port_id, p->mode, p->inhibit_charge) !=
+	    EC_SUCCESS)
 		return EC_RES_ERROR;
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_USB_CHARGE_SET_MODE,
-		     usb_port_command_set_mode,
+DECLARE_HOST_COMMAND(EC_CMD_USB_CHARGE_SET_MODE, usb_port_command_set_mode,
 		     EC_VER_MASK(0));
 
 /*****************************************************************************/
 /* Console commands */
 
-static int command_set_mode(int argc, char **argv)
+static int command_set_mode(int argc, const char **argv)
 {
 	int port_id = -1;
 	int mode = -1;
@@ -100,21 +104,19 @@ static int command_set_mode(int argc, char **argv)
 			return EC_ERROR_PARAM2;
 
 		usb_port_set_enabled(port_id, mode);
-		/* fallthrough */
+		__fallthrough;
 	case 1:
 		for (i = 0; i < USB_PORT_COUNT; i++)
-			ccprintf("Port %d: %s\n",
-				 i, charge_mode[i] ? "on" : "off");
+			ccprintf("Port %d: %s\n", i,
+				 charge_mode[i] ? "on" : "off");
 		return EC_SUCCESS;
 	}
 
 	return EC_ERROR_PARAM_COUNT;
 }
-DECLARE_CONSOLE_COMMAND(usbchargemode, command_set_mode,
-			"[<port> <on | off>]",
+DECLARE_CONSOLE_COMMAND(usbchargemode, command_set_mode, "[<port> <on | off>]",
 			"Set USB charge mode");
 
-
 /*****************************************************************************/
 /* Hooks */
 
@@ -130,10 +132,10 @@ static void usb_port_init(void)
 	const uint8_t *prev;
 	int version, size, i;
 
-	prev = (const uint8_t *)system_get_jump_tag(USB_SYSJUMP_TAG,
-						    &version, &size);
+	prev = (const uint8_t *)system_get_jump_tag(USB_SYSJUMP_TAG, &version,
+						    &size);
 	if (!prev || version != USB_HOOK_VERSION ||
-			size != sizeof(charge_mode)) {
+	    size != sizeof(charge_mode)) {
 		usb_port_all_ports_off();
 		return;
 	}
@@ -143,6 +145,7 @@ static void usb_port_init(void)
 }
 DECLARE_HOOK(HOOK_INIT, usb_port_init, HOOK_PRIO_DEFAULT);
 
+#ifndef CONFIG_USB_PORT_POWER_DUMB_CUSTOM_HOOK
 static void usb_port_startup(void)
 {
 	/* Turn on USB ports on as we go into S0 from S5. */
@@ -156,3 +159,4 @@ static void usb_port_shutdown(void)
 	usb_port_all_ports_off();
 }
 DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, usb_port_shutdown, HOOK_PRIO_DEFAULT);
+#endif /* CONFIG_USB_PORT_POWER_DUMB_CUSTOM_HOOK */
diff --git a/common/usb_port_power_smart.c b/common/usb_port_power_smart.c
index 170180cbab..42fbc7dd64 100644
--- a/common/usb_port_power_smart.c
+++ b/common/usb_port_power_smart.c
@@ -1,10 +1,11 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* USB charging control module for Chrome EC */
 
+#include "builtin/assert.h"
 #include "chipset.h"
 #include "common.h"
 #include "console.h"
@@ -16,15 +17,15 @@
 #include "util.h"
 
 #define CPUTS(outstr) cputs(CC_USBCHARGE, outstr)
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
 
 #ifndef CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE
 #define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_SDP2
 #endif
 
 struct charge_mode_t {
-	uint8_t mode:7;
-	uint8_t inhibit_charging_in_suspend:1;
+	uint8_t mode : 7;
+	uint8_t inhibit_charging_in_suspend : 1;
 } __pack;
 
 static struct charge_mode_t charge_mode[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT];
@@ -34,7 +35,9 @@ static struct charge_mode_t charge_mode[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT];
  * If we only support CDP and SDP, the control signals are hard-wired so
  * there's nothing to do.  The only to do is set ILIM_SEL.
  */
-static void usb_charge_set_control_mode(int port_id, int mode) {}
+static void usb_charge_set_control_mode(int port_id, int mode)
+{
+}
 #else /* !defined(CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY) */
 static void usb_charge_set_control_mode(int port_id, int mode)
 {
@@ -62,14 +65,19 @@ static void usb_charge_set_control_mode(int port_id, int mode)
 static void usb_charge_set_enabled(int port_id, int en)
 {
 	ASSERT(port_id < CONFIG_USB_PORT_POWER_SMART_PORT_COUNT);
-	gpio_or_ioex_set_level(usb_port_enable[port_id], en);
+	/*
+	 * Only enable valid ports.
+	 */
+	if (usb_port_enable[port_id] >= 0) {
+		gpio_or_ioex_set_level(usb_port_enable[port_id], en);
+	}
 }
 
 static void usb_charge_set_ilim(int port_id, int sel)
 {
 	int ilim_sel;
 
-#if defined(CONFIG_USB_PORT_POWER_SMART_SIMPLE) ||	\
+#if defined(CONFIG_USB_PORT_POWER_SMART_SIMPLE) || \
 	defined(CONFIG_USB_PORT_POWER_SMART_INVERTED)
 	/* ILIM_SEL is inverted. */
 	sel = !sel;
@@ -137,7 +145,7 @@ int usb_charge_set_mode(int port_id, enum usb_charge_mode mode,
 /*****************************************************************************/
 /* Console commands */
 
-static int command_set_mode(int argc, char **argv)
+static int command_set_mode(int argc, const char **argv)
 {
 	int port_id = -1;
 	int mode = -1, inhibit_charge = 0;
@@ -147,7 +155,7 @@ static int command_set_mode(int argc, char **argv)
 	if (argc == 1) {
 		for (i = 0; i < CONFIG_USB_PORT_POWER_SMART_PORT_COUNT; i++)
 			ccprintf("Port %d: %d,%d\n", i, charge_mode[i].mode,
-				charge_mode[i].inhibit_charging_in_suspend);
+				 charge_mode[i].inhibit_charging_in_suspend);
 		return EC_SUCCESS;
 	}
 
@@ -183,14 +191,13 @@ usb_charge_command_set_mode(struct host_cmd_handler_args *args)
 {
 	const struct ec_params_usb_charge_set_mode *p = args->params;
 
-	if (usb_charge_set_mode(p->usb_port_id, p->mode,
-				p->inhibit_charge) != EC_SUCCESS)
+	if (usb_charge_set_mode(p->usb_port_id, p->mode, p->inhibit_charge) !=
+	    EC_SUCCESS)
 		return EC_RES_ERROR;
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_USB_CHARGE_SET_MODE,
-		     usb_charge_command_set_mode,
+DECLARE_HOST_COMMAND(EC_CMD_USB_CHARGE_SET_MODE, usb_charge_command_set_mode,
 		     EC_VER_MASK(0));
 
 /*****************************************************************************/
@@ -208,18 +215,18 @@ static void usb_charge_init(void)
 	const struct charge_mode_t *prev;
 	int version, size, i;
 
-	prev = (const struct charge_mode_t *)system_get_jump_tag(USB_SYSJUMP_TAG,
-						    &version, &size);
+	prev = (const struct charge_mode_t *)system_get_jump_tag(
+		USB_SYSJUMP_TAG, &version, &size);
 
 	if (!prev || version != USB_HOOK_VERSION ||
-			size != sizeof(charge_mode)) {
+	    size != sizeof(charge_mode)) {
 		usb_charge_all_ports_ctrl(USB_CHARGE_MODE_DISABLED);
 		return;
 	}
 
 	for (i = 0; i < CONFIG_USB_PORT_POWER_SMART_PORT_COUNT; i++)
 		usb_charge_set_mode(i, prev[i].mode,
-			prev[i].inhibit_charging_in_suspend);
+				    prev[i].inhibit_charging_in_suspend);
 }
 DECLARE_HOOK(HOOK_INIT, usb_charge_init, HOOK_PRIO_DEFAULT);
 
@@ -229,9 +236,8 @@ static void usb_charge_resume(void)
 
 	/* Turn on USB ports on as we go into S0 from S3 or S5. */
 	for (i = 0; i < CONFIG_USB_PORT_POWER_SMART_PORT_COUNT; i++)
-		usb_charge_set_mode(i,
-			CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE,
-			charge_mode[i].inhibit_charging_in_suspend);
+		usb_charge_set_mode(i, CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE,
+				    charge_mode[i].inhibit_charging_in_suspend);
 }
 DECLARE_HOOK(HOOK_CHIPSET_RESUME, usb_charge_resume, HOOK_PRIO_DEFAULT);
 
diff --git a/common/usb_update.c b/common/usb_update.c
index cc443163ba..2e9a681fed 100644
--- a/common/usb_update.c
+++ b/common/usb_update.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,8 +9,8 @@
 #include "consumer.h"
 #include "curve25519.h"
 #include "flash.h"
-#include "queue_policies.h"
 #include "host_command.h"
+#include "queue_policies.h"
 #include "rollback.h"
 #include "rwsig.h"
 #include "sha256.h"
@@ -20,8 +20,8 @@
 #include "usb-stream.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USB, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args)
 
 /*
  * This file is an adaptation layer between the USB interface and the firmware
@@ -47,37 +47,27 @@
 struct consumer const update_consumer;
 struct usb_stream_config const usb_update;
 
-static struct queue const update_to_usb = QUEUE_DIRECT(64, uint8_t,
-						     null_producer,
-						     usb_update.consumer);
-static struct queue const usb_to_update = QUEUE_DIRECT(64, uint8_t,
-						     usb_update.producer,
-						     update_consumer);
-
-USB_STREAM_CONFIG_FULL(usb_update,
-		       USB_IFACE_UPDATE,
-		       USB_CLASS_VENDOR_SPEC,
-		       USB_SUBCLASS_GOOGLE_UPDATE,
-		       USB_PROTOCOL_GOOGLE_UPDATE,
-		       USB_STR_UPDATE_NAME,
-		       USB_EP_UPDATE,
-		       USB_MAX_PACKET_SIZE,
-		       USB_MAX_PACKET_SIZE,
-		       usb_to_update,
-		       update_to_usb)
+static struct queue const update_to_usb =
+	QUEUE_DIRECT(64, uint8_t, null_producer, usb_update.consumer);
+static struct queue const usb_to_update =
+	QUEUE_DIRECT(64, uint8_t, usb_update.producer, update_consumer);
 
+USB_STREAM_CONFIG_FULL(usb_update, USB_IFACE_UPDATE, USB_CLASS_VENDOR_SPEC,
+		       USB_SUBCLASS_GOOGLE_UPDATE, USB_PROTOCOL_GOOGLE_UPDATE,
+		       USB_STR_UPDATE_NAME, USB_EP_UPDATE, USB_MAX_PACKET_SIZE,
+		       USB_MAX_PACKET_SIZE, usb_to_update, update_to_usb)
 
 /* The receiver can be in one of the states below. */
 enum rx_state {
-	rx_idle,	   /* Nothing happened yet. */
-	rx_inside_block,   /* Assembling a block to pass to the programmer. */
-	rx_outside_block,  /* Waiting for the next block to start or for the
-			      reset command. */
+	rx_idle, /* Nothing happened yet. */
+	rx_inside_block, /* Assembling a block to pass to the programmer. */
+	rx_outside_block, /* Waiting for the next block to start or for the
+			     reset command. */
 };
 
 enum rx_state rx_state_ = rx_idle;
-static uint8_t block_buffer[sizeof(struct update_command) +
-			    CONFIG_UPDATE_PDU_SIZE];
+static uint8_t
+	block_buffer[sizeof(struct update_command) + CONFIG_UPDATE_PDU_SIZE];
 static uint32_t block_size;
 static uint32_t block_index;
 
@@ -117,8 +107,8 @@ static int pair_challenge(struct pair_challenge *challenge)
 	 * tmp2 = device_private
 	 *      = HMAC_SHA256(device_secret, "device-identity")
 	 */
-	hmac_SHA256(tmp2, tmp, CONFIG_ROLLBACK_SECRET_SIZE,
-		    KEY_CONTEXT, sizeof(KEY_CONTEXT) - 1);
+	hmac_SHA256(tmp2, tmp, CONFIG_ROLLBACK_SECRET_SIZE, KEY_CONTEXT,
+		    sizeof(KEY_CONTEXT) - 1);
 
 	/* tmp = device_public = x25519(device_private, x25519_base_point) */
 	X25519_public_from_private(tmp, tmp2);
@@ -128,10 +118,11 @@ static int pair_challenge(struct pair_challenge *challenge)
 	X25519(tmp, tmp2, challenge->host_public);
 
 	/* tmp2 = authenticator = HMAC_SHA256(shared_secret, nonce) */
-	hmac_SHA256(tmp2, tmp, sizeof(tmp),
-		    challenge->nonce, sizeof(challenge->nonce));
+	hmac_SHA256(tmp2, tmp, sizeof(tmp), challenge->nonce,
+		    sizeof(challenge->nonce));
 	QUEUE_ADD_UNITS(&update_to_usb, tmp2,
-		member_size(struct pair_challenge_response, authenticator));
+			member_size(struct pair_challenge_response,
+				    authenticator));
 	return 1;
 }
 #endif
@@ -198,7 +189,8 @@ static int try_vendor_command(struct consumer const *consumer, size_t count)
 
 	/* Looks like this is a vendor command, let's verify it. */
 	if (update_pdu_valid(&cmd_buffer->cmd,
-			  count - offsetof(struct update_frame_header, cmd))) {
+			     count - offsetof(struct update_frame_header,
+					      cmd))) {
 		enum update_extra_command subcommand;
 		uint8_t response;
 		size_t response_size = sizeof(response);
@@ -262,12 +254,13 @@ static int try_vendor_command(struct consumer const *consumer, size_t count)
 			break;
 #endif
 		case UPDATE_EXTRA_CMD_UNLOCK_RW:
-			flash_set_protect(EC_FLASH_PROTECT_RW_AT_BOOT, 0);
+			crec_flash_set_protect(EC_FLASH_PROTECT_RW_AT_BOOT, 0);
 			response = EC_RES_SUCCESS;
 			break;
 #ifdef CONFIG_ROLLBACK
 		case UPDATE_EXTRA_CMD_UNLOCK_ROLLBACK:
-			flash_set_protect(EC_FLASH_PROTECT_ROLLBACK_AT_BOOT, 0);
+			crec_flash_set_protect(
+				EC_FLASH_PROTECT_ROLLBACK_AT_BOOT, 0);
 			response = EC_RES_SUCCESS;
 			break;
 #ifdef CONFIG_ROLLBACK_SECRET_SIZE
@@ -294,8 +287,8 @@ static int try_vendor_command(struct consumer const *consumer, size_t count)
 			}
 
 			/* pair_challenge takes care of answering */
-			return pair_challenge((struct pair_challenge *)
-						(buffer + header_size));
+			return pair_challenge((
+				struct pair_challenge *)(buffer + header_size));
 		}
 #endif
 #endif /* CONFIG_ROLLBACK_SECRET_SIZE */
@@ -321,11 +314,10 @@ static int try_vendor_command(struct consumer const *consumer, size_t count)
 
 #ifdef CONFIG_TOUCHPAD_HASH_FW
 			memcpy(tp.allowed_fw_hash, touchpad_fw_full_hash,
-				sizeof(tp.allowed_fw_hash));
+			       sizeof(tp.allowed_fw_hash));
 #endif
 #endif /* CONFIG_TOUCHPAD_VIRTUAL_OFF */
-			QUEUE_ADD_UNITS(&update_to_usb,
-					&tp, response_size);
+			QUEUE_ADD_UNITS(&update_to_usb, &tp, response_size);
 			return 1;
 		}
 		case UPDATE_EXTRA_CMD_TOUCHPAD_DEBUG: {
@@ -337,7 +329,8 @@ static int try_vendor_command(struct consumer const *consumer, size_t count)
 			 * with the payload data, and put the response in data.
 			 */
 			response = touchpad_debug(buffer + header_size,
-					data_count, &data, &write_count);
+						  data_count, &data,
+						  &write_count);
 
 			/*
 			 * On error, or if there is no data to write back, just
@@ -373,11 +366,10 @@ static int try_vendor_command(struct consumer const *consumer, size_t count)
 			}
 
 			response = uart_console_read_buffer(
-					data[0],
-					(char *)output,
-					MIN(sizeof(output),
-					    queue_space(&update_to_usb)),
-					&write_count);
+				data[0], (char *)output,
+				MIN(sizeof(output),
+				    queue_space(&update_to_usb)),
+				&write_count);
 			if (response != EC_RES_SUCCESS || write_count == 0)
 				break;
 
@@ -405,7 +397,7 @@ static uint64_t prev_activity_timestamp;
  * A flag indicating that at least one valid PDU containing flash update block
  * has been received in the current transfer session.
  */
-static uint8_t  data_was_transferred;
+static uint8_t data_was_transferred;
 
 /* Reply with an error to remote side, reset state. */
 static void send_error_reset(uint8_t resp_value)
@@ -458,10 +450,10 @@ static void update_out_handler(struct consumer const *consumer, size_t count)
 		 * digest = 0, and base = 0.
 		 */
 		if (!fetch_transfer_start(consumer, count, &u.upfr) ||
-			be32toh(u.upfr.block_size) !=
-					sizeof(struct update_frame_header) ||
-				u.upfr.cmd.block_digest != 0 ||
-				u.upfr.cmd.block_base != 0) {
+		    be32toh(u.upfr.block_size) !=
+			    sizeof(struct update_frame_header) ||
+		    u.upfr.cmd.block_digest != 0 ||
+		    u.upfr.cmd.block_base != 0) {
 			/*
 			 * Something is wrong, this payload is not a valid
 			 * update start PDU. Let'w indicate this by returning
@@ -473,14 +465,14 @@ static void update_out_handler(struct consumer const *consumer, size_t count)
 		}
 
 		CPRINTS("FW update: starting...");
-		fw_update_command_handler(&u.upfr.cmd, count -
-					   offsetof(struct update_frame_header,
-						    cmd),
-					   &resp_size);
+		fw_update_command_handler(
+			&u.upfr.cmd,
+			count - offsetof(struct update_frame_header, cmd),
+			&resp_size);
 
 		if (!u.startup_resp.return_value) {
-			rx_state_ = rx_outside_block;  /* We're in business. */
-			data_was_transferred = 0;   /* No data received yet. */
+			rx_state_ = rx_outside_block; /* We're in business. */
+			data_was_transferred = 0; /* No data received yet. */
 		}
 
 		/* Let the host know what updater had to say. */
@@ -508,8 +500,7 @@ static void update_out_handler(struct consumer const *consumer, size_t count)
 				}
 
 				resp_value = 0;
-				QUEUE_ADD_UNITS(&update_to_usb,
-						&resp_value, 1);
+				QUEUE_ADD_UNITS(&update_to_usb, &resp_value, 1);
 				rx_state_ = rx_idle;
 				return;
 			}
@@ -527,7 +518,7 @@ static void update_out_handler(struct consumer const *consumer, size_t count)
 
 		/* Let's allocate a large enough buffer. */
 		block_size = be32toh(upfr.block_size) -
-			offsetof(struct update_frame_header, cmd);
+			     offsetof(struct update_frame_header, cmd);
 
 		/*
 		 * Only update start PDU is allowed to have a size 0 payload.
@@ -544,7 +535,7 @@ static void update_out_handler(struct consumer const *consumer, size_t count)
 		 * to the updater.
 		 */
 		block_index = sizeof(upfr) -
-			offsetof(struct update_frame_header, cmd);
+			      offsetof(struct update_frame_header, cmd);
 		memcpy(block_buffer, &upfr.cmd, block_index);
 		block_size -= block_index;
 		rx_state_ = rx_inside_block;
@@ -566,7 +557,7 @@ static void update_out_handler(struct consumer const *consumer, size_t count)
 			send_error_reset(UPDATE_GEN_ERROR);
 			return;
 		}
-		return;	/* More to come. */
+		return; /* More to come. */
 	}
 
 	/*
@@ -587,7 +578,7 @@ static void update_out_handler(struct consumer const *consumer, size_t count)
 
 struct consumer const update_consumer = {
 	.queue = &usb_to_update,
-	.ops   = &((struct consumer_ops const) {
+	.ops = &((struct consumer_ops const){
 		.written = update_out_handler,
 	}),
 };
diff --git a/common/usbc/ap_vdm_control.c b/common/usbc/ap_vdm_control.c
new file mode 100644
index 0000000000..7941b852e8
--- /dev/null
+++ b/common/usbc/ap_vdm_control.c
@@ -0,0 +1,301 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * AP VDM control support
+ * Note: this is mutually exclusive with EC VDM control
+ */
+
+#include "builtin/assert.h"
+#include "chipset.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "hooks.h"
+#include "queue.h"
+#include "system.h"
+#include "task.h"
+#include "tcpm/tcpm.h"
+#include "temp_sensor.h"
+#include "usb_pd.h"
+#include "usb_pd_dp_hpd_gpio.h"
+#include "usb_pd_dpm_sm.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#ifdef CONFIG_COMMON_RUNTIME
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+#else
+#define CPRINTF(format, args...)
+#define CPRINTS(format, args...)
+#endif
+
+/*
+ * VDM:Attention queue for boards using AP-driven VDMs
+ *
+ * Depth must be a power of 2, which is normally enforced by the queue init
+ * code, but must be manually enforced here.
+ */
+#define DPM_ATTENTION_QUEUE_DEPTH 8
+BUILD_ASSERT(POWER_OF_TWO(DPM_ATTENTION_QUEUE_DEPTH));
+
+/*
+ * timestamp of the next possible toggle to ensure the 2-ms spacing
+ * between IRQ_HPD.  Note, other boards use the DP module to store this
+ * variable so it's globally accessible for board code.
+ *
+ * Note: This is also defined in the EC-driven DP module, and it's assumed
+ * that these modules are mutually exclusive and will not be compiled
+ * for the same board.
+ */
+uint64_t svdm_hpd_deadline[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+struct attention_queue_entry {
+	int objects;
+	uint32_t attention[PD_ATTENTION_MAX_VDO];
+};
+
+static struct {
+	uint32_t vdm_reply[VDO_MAX_SIZE];
+	uint8_t vdm_reply_cnt;
+	enum tcpci_msg_type vdm_reply_type;
+	struct queue attention_queue;
+	struct queue_state queue_state;
+	struct attention_queue_entry queue_buffer[DPM_ATTENTION_QUEUE_DEPTH];
+	mutex_t queue_lock;
+	/* Have we seen the DP:Configure ACK? */
+	bool dp_configured;
+	/* Did we get a HPD high signal before DP:Configure completed? */
+	bool hpd_pending;
+} ap_storage[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+#ifdef CONFIG_ZEPHYR
+static int init_ap_vdm_mutexes(void)
+{
+	int port;
+
+	for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++) {
+		k_mutex_init(&ap_storage[port].queue_lock);
+	}
+
+	return 0;
+}
+SYS_INIT(init_ap_vdm_mutexes, POST_KERNEL, 50);
+#endif /* CONFIG_ZEPHYR */
+
+static void init_attention_queue_structs(void)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		ap_storage[i].attention_queue.state =
+			&ap_storage[i].queue_state;
+		ap_storage[i].attention_queue.policy = &queue_policy_null;
+		ap_storage[i].attention_queue.buffer_units =
+			DPM_ATTENTION_QUEUE_DEPTH;
+		ap_storage[i].attention_queue.buffer_units_mask =
+			DPM_ATTENTION_QUEUE_DEPTH - 1;
+		ap_storage[i].attention_queue.unit_bytes =
+			sizeof(struct attention_queue_entry);
+		ap_storage[i].attention_queue.buffer =
+			(uint8_t *)&ap_storage[i].queue_buffer[0];
+	}
+}
+DECLARE_HOOK(HOOK_INIT, init_attention_queue_structs, HOOK_PRIO_FIRST);
+
+/* Process HPD signals from the DP:Status or Attention contents */
+static void attention_hpd_process(int port, uint32_t vdo)
+{
+	bool hpd_level = PD_VDO_DPSTS_HPD_LVL(vdo);
+	bool hpd_irq = PD_VDO_DPSTS_HPD_IRQ(vdo);
+
+	if (!ap_storage[port].dp_configured && hpd_level)
+		ap_storage[port].hpd_pending = true;
+	else
+		dp_hpd_gpio_set(port, hpd_level, hpd_irq);
+
+	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
+	    (hpd_irq || hpd_level))
+		/*
+		 * Wake up the AP.  IRQ or level high indicates a DP
+		 * sink is now present.
+		 */
+		if (IS_ENABLED(CONFIG_MKBP_EVENT))
+			pd_notify_dp_alt_mode_entry(port);
+}
+
+void ap_vdm_attention_enqueue(int port, int length, uint32_t *buf)
+{
+	struct attention_queue_entry new_entry;
+
+	/*
+	 * Process HPD from the message if we're configured
+	 * Note: the IRQ toggles are time critical and should be done before
+	 * sending the VDM to the queue
+	 */
+	if (PD_VDO_VID(buf[0]) == USB_SID_DISPLAYPORT && length > 1)
+		attention_hpd_process(port, buf[1]);
+
+	new_entry.objects = length;
+	memcpy(new_entry.attention, buf, length * sizeof(uint32_t));
+
+	mutex_lock(&ap_storage[port].queue_lock);
+
+	/* If the queue is already full, discard the last entry */
+	if (queue_is_full(&ap_storage[port].attention_queue))
+		queue_advance_head(&ap_storage[port].attention_queue, 1);
+
+	/* Note: this should not happen, but log anyway */
+	if (queue_add_unit(&ap_storage[port].attention_queue, &new_entry) == 0)
+		CPRINTS("Error: Dropping port %d Attention", port);
+	else
+		pd_notify_event(port, PD_STATUS_EVENT_VDM_ATTENTION);
+
+	mutex_unlock(&ap_storage[port].queue_lock);
+}
+
+static uint8_t ap_vdm_attention_pop(int port, uint32_t *buf,
+				    uint8_t *items_left)
+{
+	int length = 0;
+	struct attention_queue_entry popped_entry;
+
+	mutex_lock(&ap_storage[port].queue_lock);
+
+	if (!queue_is_empty(&ap_storage[port].attention_queue)) {
+		queue_remove_unit(&ap_storage[port].attention_queue,
+				  &popped_entry);
+
+		length = popped_entry.objects;
+		memcpy(buf, popped_entry.attention, length * sizeof(buf[0]));
+	}
+	*items_left = queue_count(&ap_storage[port].attention_queue);
+
+	mutex_unlock(&ap_storage[port].queue_lock);
+
+	return length;
+}
+
+void ap_vdm_init(int port)
+{
+	/* Clear any stored AP messages */
+	ap_storage[port].vdm_reply_cnt = 0;
+	queue_init(&ap_storage[port].attention_queue);
+	ap_storage[port].dp_configured = false;
+	ap_storage[port].hpd_pending = false;
+	dp_hpd_gpio_set(port, false, false);
+}
+
+void ap_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count,
+		  uint32_t *vdm)
+{
+	assert(vdo_count >= 1);
+	assert(vdo_count <= VDO_MAX_SIZE);
+
+	/* Store and notify the AP */
+	ap_storage[port].vdm_reply_cnt = vdo_count;
+	memcpy(ap_storage[port].vdm_reply, vdm, vdo_count * sizeof(uint32_t));
+	ap_storage[port].vdm_reply_type = type;
+	pd_notify_event(port, PD_STATUS_EVENT_VDM_REQ_REPLY);
+
+	/* Clear the flag now that reply fields are updated */
+	dpm_clear_vdm_request(port);
+
+	if ((PD_VDO_VID(vdm[0]) == USB_SID_DISPLAYPORT) &&
+	    PD_VDO_SVDM(vdm[0]) && (PD_VDO_CMD(vdm[0]) == CMD_DP_CONFIG)) {
+		/*
+		 * If this was a DP:Configure ACK, register it so we can start
+		 * sending HPD signals
+		 */
+		ap_storage[port].dp_configured = true;
+		if (ap_storage[port].hpd_pending)
+			dp_hpd_gpio_set(port, true, false);
+	} else if ((PD_VDO_VID(vdm[0]) == USB_SID_DISPLAYPORT) &&
+		   PD_VDO_SVDM(vdm[0]) &&
+		   (PD_VDO_CMD(vdm[0]) == CMD_DP_STATUS) && vdo_count > 1) {
+		/*
+		 * If this was a DP:Status ACK, register if the HPD signal was
+		 * set in it.  According to 3.9.2.2 USB PD-to-HPD Timing in
+		 * VESA DisplayPort Alt Mode on USB Type-C Standard Version
+		 * 2.0:
+		 * "A USB PD-to-HPD converter shall drive a low level on its
+		 * HPD driver whenever DisplayPort Configuration on the USB-C
+		 * interface is not enabled"
+		 *
+		 * So we may not transmit this HPD high until DP:Configure ACK
+		 */
+		attention_hpd_process(port, vdm[1]);
+	}
+}
+
+void ap_vdm_naked(int port, enum tcpci_msg_type type, uint16_t svid,
+		  uint8_t vdm_cmd, uint32_t vdm_header)
+{
+	/* Store and notify the AP */
+	ap_storage[port].vdm_reply_type = type;
+
+	if (vdm_header != 0) {
+		ap_storage[port].vdm_reply_cnt = 1;
+		ap_storage[port].vdm_reply[0] = vdm_header;
+		pd_notify_event(port, PD_STATUS_EVENT_VDM_REQ_REPLY);
+	} else {
+		ap_storage[port].vdm_reply_cnt = 0;
+		pd_notify_event(port, PD_STATUS_EVENT_VDM_REQ_FAILED);
+	}
+
+	/* Clear the flag now that reply fields are updated */
+	dpm_clear_vdm_request(port);
+}
+
+static enum ec_status ap_vdm_copy_reply(int port, uint8_t *type, uint8_t *size,
+					uint32_t *buf)
+{
+	if (dpm_check_vdm_request(port))
+		return EC_RES_BUSY;
+
+	if (ap_storage[port].vdm_reply_cnt == 0)
+		return EC_RES_UNAVAILABLE;
+
+	*type = ap_storage[port].vdm_reply_type;
+	*size = ap_storage[port].vdm_reply_cnt;
+	memcpy(buf, ap_storage[port].vdm_reply, *size * sizeof(uint32_t));
+
+	return EC_RES_SUCCESS;
+}
+
+/* Feature-specific host commands */
+static enum ec_status hc_typec_vdm_response(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_typec_vdm_response *p = args->params;
+	struct ec_response_typec_vdm_response *r = args->response;
+	uint32_t data[VDO_MAX_SIZE];
+
+	if (p->port >= board_get_usb_pd_port_count())
+		return EC_RES_INVALID_PARAM;
+
+	if (args->response_max < sizeof(*r))
+		return EC_RES_RESPONSE_TOO_BIG;
+
+	args->response_size = sizeof(*r);
+
+	r->vdm_response_err = ap_vdm_copy_reply(p->port, &r->partner_type,
+						&r->vdm_data_objects, data);
+
+	if (r->vdm_data_objects > 0)
+		memcpy(r->vdm_response, data,
+		       r->vdm_data_objects * sizeof(uint32_t));
+
+	r->vdm_attention_objects =
+		ap_vdm_attention_pop(p->port, data, &r->vdm_attention_left);
+	if (r->vdm_attention_objects > 0)
+		memcpy(r->vdm_attention, data,
+		       r->vdm_attention_objects * sizeof(uint32_t));
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_TYPEC_VDM_RESPONSE, hc_typec_vdm_response,
+		     EC_VER_MASK(0));
diff --git a/common/usbc/build.mk b/common/usbc/build.mk
index c39d1a57e6..159ce05e0b 100644
--- a/common/usbc/build.mk
+++ b/common/usbc/build.mk
@@ -1,4 +1,4 @@
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -8,8 +8,9 @@
 _usbc_dir:=$(dir $(lastword $(MAKEFILE_LIST)))
 
 ifneq ($(CONFIG_USB_PD_TCPMV2),)
-all-obj-y+=$(_usbc_dir)usb_sm.o
-all-obj-y+=$(_usbc_dir)usbc_task.o
+all-obj-$(CONFIG_USB_PD_TCPMV2)+=$(_usbc_dir)usb_pd_timer.o
+all-obj-$(CONFIG_USB_PD_TCPMV2)+=$(_usbc_dir)usb_sm.o
+all-obj-$(CONFIG_USB_PD_TCPMV2)+=$(_usbc_dir)usbc_task.o
 
 # Type-C state machines
 ifneq ($(CONFIG_USB_TYPEC_SM),)
@@ -20,24 +21,34 @@ endif # CONFIG_USB_TYPEC_SM
 
 # Protocol state machine
 ifneq ($(CONFIG_USB_PRL_SM),)
-all-obj-y+=$(_usbc_dir)usb_prl_sm.o
+all-obj-$(CONFIG_USB_PD_TCPMV2)+=$(_usbc_dir)usb_prl_sm.o
 endif # CONFIG_USB_PRL_SM
 
 # Policy Engine state machines
 ifneq ($(CONFIG_USB_PE_SM),)
 all-obj-$(CONFIG_USB_VPD)+=$(_usbc_dir)usb_pe_ctvpd_sm.o
 all-obj-$(CONFIG_USB_CTVPD)+=$(_usbc_dir)usb_pe_ctvpd_sm.o
+all-obj-$(CONFIG_USB_DRP_ACC_TRYSRC)+=$(_usbc_dir)usbc_pd_policy.o
 all-obj-$(CONFIG_USB_DRP_ACC_TRYSRC)+=$(_usbc_dir)usb_pe_drp_sm.o
 all-obj-$(CONFIG_USB_DRP_ACC_TRYSRC)+=$(_usbc_dir)usb_pd_dpm.o
-all-obj-$(CONFIG_USB_DRP_ACC_TRYSRC)+=$(_usbc_dir)dp_alt_mode.o
+all-obj-$(CONFIG_USB_PD_VDM_AP_CONTROL)+=$(_usbc_dir)ap_vdm_control.o
+all-obj-$(CONFIG_USB_PD_DP_MODE)+=$(_usbc_dir)dp_alt_mode.o
+all-obj-$(CONFIG_USB_PD_DP_HPD_GPIO)+=$(_usbc_dir)dp_hpd_gpio.o
 all-obj-$(CONFIG_USB_PD_TBT_COMPAT_MODE)+=$(_usbc_dir)tbt_alt_mode.o
 all-obj-$(CONFIG_USB_PD_USB4)+=$(_usbc_dir)usb_mode.o
 all-obj-$(CONFIG_CMD_PD)+=$(_usbc_dir)usb_pd_console.o
 all-obj-$(CONFIG_USB_PD_HOST_CMD)+=$(_usbc_dir)usb_pd_host.o
 endif # CONFIG_USB_PE_SM
 
+# Retimer firmware update
+all-obj-$(CONFIG_USBC_RETIMER_FW_UPDATE)+=$(_usbc_dir)usb_retimer_fw_update.o
+
+# ALT-DP mode for UFP ports
+all-obj-$(CONFIG_USB_PD_ALT_MODE_UFP_DP)+=$(_usbc_dir)usb_pd_dp_ufp.o
 endif # CONFIG_USB_PD_TCPMV2
 
 # For testing
+all-obj-$(CONFIG_TEST_USB_PD_TIMER)+=$(_usbc_dir)usb_pd_timer.o
+all-obj-$(CONFIG_TEST_USB_PE_SM)+=$(_usbc_dir)usbc_pd_policy.o
 all-obj-$(CONFIG_TEST_USB_PE_SM)+=$(_usbc_dir)usb_pe_drp_sm.o
 all-obj-$(CONFIG_TEST_SM)+=$(_usbc_dir)usb_sm.o
diff --git a/common/usbc/dp_alt_mode.c b/common/usbc/dp_alt_mode.c
index cc5305c0c3..dbccd9b0fd 100644
--- a/common/usbc/dp_alt_mode.c
+++ b/common/usbc/dp_alt_mode.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,30 +9,67 @@
  * section 5.2
  */
 
-#include <stdbool.h>
-#include <stdint.h>
-#include "assert.h"
-#include "usb_pd.h"
+#include "atomic.h"
+#include "builtin/assert.h"
+#include "chipset.h"
+#include "console.h"
+#include "gpio.h"
+#include "timer.h"
+#include "typec_control.h"
+#include "usb_common.h"
 #include "usb_dp_alt_mode.h"
-#include "usb_pd_dpm.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_dp_hpd_gpio.h"
 #include "usb_pd_tcpm.h"
 
+#include <stdbool.h>
+#include <stdint.h>
+
 #ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 #else
 #define CPRINTF(format, args...)
 #define CPRINTS(format, args...)
 #endif
 
+/*
+ * Note: the following DP-related variables must be kept as-is since
+ * some boards are using them in their board-specific code.
+ * TODO(b/267545470): Fold board DP code into the DP module
+ */
+
+/*
+ * timestamp of the next possible toggle to ensure the 2-ms spacing
+ * between IRQ_HPD.  Since this is used in overridable functions, this
+ * has to be global.
+ *
+ * Note: This variable is also defined in the AP VDM control module and it
+ * is assumed that the two will never be compiled together, as the modules are
+ * mutually exclusive.
+ */
+uint64_t svdm_hpd_deadline[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+int dp_flags[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+uint32_t dp_status[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+/* Console command multi-function preference set for a PD port. */
+__maybe_unused bool dp_port_mf_allow[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	[0 ... CONFIG_USB_PD_PORT_MAX_COUNT - 1] = true
+};
+
 /* The state of the DP negotiation */
 enum dp_states {
 	DP_START = 0,
 	DP_ENTER_ACKED,
 	DP_ENTER_NAKED,
 	DP_STATUS_ACKED,
+	DP_PREPARE_CONFIG,
 	DP_ACTIVE,
 	DP_ENTER_RETRY,
+	DP_PREPARE_EXIT,
 	DP_INACTIVE,
 	DP_STATE_COUNT
 };
@@ -43,39 +80,55 @@ static enum dp_states dp_state[CONFIG_USB_PD_PORT_MAX_COUNT];
  * Default of 0 indicates no command expected.
  */
 static const uint8_t state_vdm_cmd[DP_STATE_COUNT] = {
-	[DP_START] = CMD_ENTER_MODE,
-	[DP_ENTER_ACKED] = CMD_DP_STATUS,
-	[DP_STATUS_ACKED] = CMD_DP_CONFIG,
-	[DP_ACTIVE] = CMD_EXIT_MODE,
-	[DP_ENTER_NAKED] = CMD_EXIT_MODE,
+	[DP_START] = CMD_ENTER_MODE,	     [DP_ENTER_ACKED] = CMD_DP_STATUS,
+	[DP_PREPARE_CONFIG] = CMD_DP_CONFIG, [DP_PREPARE_EXIT] = CMD_EXIT_MODE,
 	[DP_ENTER_RETRY] = CMD_ENTER_MODE,
 };
 
+/*
+ * Track if we're retrying due to an Enter Mode NAK
+ */
+#define DP_FLAG_RETRY BIT(0)
+
+static atomic_t dpm_dp_flags[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+#define DP_SET_FLAG(port, flag) atomic_or(&dpm_dp_flags[port], (flag))
+#define DP_CLR_FLAG(port, flag) atomic_clear_bits(&dpm_dp_flags[port], (flag))
+#define DP_CHK_FLAG(port, flag) (dpm_dp_flags[port] & (flag))
+
+/* Note: There is only one DP mode currently specified */
+static const int dp_opos = 1;
+
 bool dp_is_active(int port)
 {
-	return dp_state[port] == DP_ACTIVE;
+	return dp_state[port] == DP_ACTIVE || dp_state[port] == DP_PREPARE_EXIT;
+}
+
+bool dp_is_idle(int port)
+{
+	return dp_state[port] == DP_INACTIVE || dp_state[port] == DP_START;
 }
 
 void dp_init(int port)
 {
 	dp_state[port] = DP_START;
+	dpm_dp_flags[port] = 0;
 }
 
-void dp_teardown(int port)
+bool dp_entry_is_done(int port)
 {
-	CPRINTS("C%d: DP teardown", port);
-	dp_state[port] = DP_INACTIVE;
+	return dp_state[port] == DP_ACTIVE || dp_state[port] == DP_INACTIVE;
 }
 
 static void dp_entry_failed(int port)
 {
 	CPRINTS("C%d: DP alt mode protocol failed!", port);
 	dp_state[port] = DP_INACTIVE;
-	dpm_set_mode_entry_done(port);
+	dpm_dp_flags[port] = 0;
 }
 
-static bool dp_response_valid(int port, enum tcpm_transmit_type type,
-			     char *cmdt, int vdm_cmd)
+static bool dp_response_valid(int port, enum tcpci_msg_type type, char *cmdt,
+			      int vdm_cmd)
 {
 	enum dp_states st = dp_state[port];
 
@@ -83,11 +136,12 @@ static bool dp_response_valid(int port, enum tcpm_transmit_type type,
 	 * Check for an unexpected response.
 	 * If DP is inactive, ignore the command.
 	 */
-	if (type != TCPC_TX_SOP ||
+	if (type != TCPCI_MSG_SOP ||
 	    (st != DP_INACTIVE && state_vdm_cmd[st] != vdm_cmd)) {
 		CPRINTS("C%d: Received unexpected DP VDM %s (cmd %d) from"
-			" %s in state %d", port, cmdt, vdm_cmd,
-			type == TCPC_TX_SOP ? "port partner" : "cable plug",
+			" %s in state %d",
+			port, cmdt, vdm_cmd,
+			type == TCPCI_MSG_SOP ? "port partner" : "cable plug",
 			st);
 		dp_entry_failed(port);
 		return false;
@@ -95,11 +149,26 @@ static bool dp_response_valid(int port, enum tcpm_transmit_type type,
 	return true;
 }
 
-void dp_vdm_acked(int port, enum tcpm_transmit_type type, int vdo_count,
-		uint32_t *vdm)
+static void dp_exit_to_usb_mode(int port)
+{
+	svdm_exit_dp_mode(port);
+	pd_set_dfp_enter_mode_flag(port, false);
+
+	set_usb_mux_with_current_data_role(port);
+
+	CPRINTS("C%d: Exited DP mode", port);
+	/*
+	 * If the EC exits an alt mode autonomously, don't try to enter it
+	 * again. If the AP commands the EC to exit DP mode, it might command
+	 * the EC to enter again later, so leave the state machine ready for
+	 * that possibility.
+	 */
+	dp_state[port] = DP_INACTIVE;
+}
+
+void dp_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count,
+		  uint32_t *vdm)
 {
-	const struct svdm_amode_data *modep =
-		pd_get_amode_data(port, type, USB_SID_DISPLAYPORT);
 	const uint8_t vdm_cmd = PD_VDO_CMD(vdm[0]);
 
 	if (!dp_response_valid(port, type, "ACK", vdm_cmd))
@@ -111,33 +180,30 @@ void dp_vdm_acked(int port, enum tcpm_transmit_type type, int vdo_count,
 	case DP_START:
 	case DP_ENTER_RETRY:
 		dp_state[port] = DP_ENTER_ACKED;
+		/* Inform PE layer that alt mode is now active */
+		pd_set_dfp_enter_mode_flag(port, true);
 		break;
 	case DP_ENTER_ACKED:
 		/* DP status response & UFP's DP attention have same payload. */
 		dfp_consume_attention(port, vdm);
 		dp_state[port] = DP_STATUS_ACKED;
 		break;
-	case DP_STATUS_ACKED:
-		if (modep && modep->opos && modep->fx->post_config)
-			modep->fx->post_config(port);
-		dpm_set_mode_entry_done(port);
+	case DP_PREPARE_CONFIG:
+		svdm_dp_post_config(port);
 		dp_state[port] = DP_ACTIVE;
 		CPRINTS("C%d: Entered DP mode", port);
 		break;
-	case DP_ACTIVE:
-		/*
-		 * Request to exit mode successful, so put it in
-		 * inactive state.
-		 */
-		CPRINTS("C%d: Exited DP mode", port);
-		dp_state[port] = DP_INACTIVE;
-		break;
-	case DP_ENTER_NAKED:
+	case DP_PREPARE_EXIT:
 		/*
-		 * The request to exit the mode was successful,
-		 * so try to enter the mode again.
+		 * Request to exit mode successful, so put the module in an
+		 * inactive state or give entry another shot.
 		 */
-		dp_state[port] = DP_ENTER_RETRY;
+		if (DP_CHK_FLAG(port, DP_FLAG_RETRY)) {
+			dp_state[port] = DP_ENTER_RETRY;
+			DP_CLR_FLAG(port, DP_FLAG_RETRY);
+		} else {
+			dp_exit_to_usb_mode(port);
+		}
 		break;
 	case DP_INACTIVE:
 		/*
@@ -148,14 +214,14 @@ void dp_vdm_acked(int port, enum tcpm_transmit_type type, int vdo_count,
 		break;
 	default:
 		/* Invalid or unexpected negotiation state */
-		CPRINTF("%s called with invalid state %d\n",
-				__func__, dp_state[port]);
+		CPRINTF("%s called with invalid state %d\n", __func__,
+			dp_state[port]);
 		dp_entry_failed(port);
 		break;
 	}
 }
 
-void dp_vdm_naked(int port, enum tcpm_transmit_type type, uint8_t vdm_cmd)
+void dp_vdm_naked(int port, enum tcpci_msg_type type, uint8_t vdm_cmd)
 {
 	if (!dp_response_valid(port, type, "NAK", vdm_cmd))
 		return;
@@ -179,60 +245,86 @@ void dp_vdm_naked(int port, enum tcpm_transmit_type type, uint8_t vdm_cmd)
 		 */
 		dp_entry_failed(port);
 		break;
+	case DP_PREPARE_EXIT:
+		/* Treat an Exit Mode NAK the same as an Exit Mode ACK. */
+		dp_exit_to_usb_mode(port);
+		break;
 	default:
-		CPRINTS("C%d: NAK for cmd %d in state %d", port,
-			vdm_cmd, dp_state[port]);
+		CPRINTS("C%d: NAK for cmd %d in state %d", port, vdm_cmd,
+			dp_state[port]);
 		dp_entry_failed(port);
 		break;
 	}
 }
 
-int dp_setup_next_vdm(int port, int vdo_count, uint32_t *vdm)
+enum dpm_msg_setup_status dp_setup_next_vdm(int port, int *vdo_count,
+					    uint32_t *vdm)
 {
-	const struct svdm_amode_data *modep = pd_get_amode_data(port,
-			TCPC_TX_SOP, USB_SID_DISPLAYPORT);
+	uint32_t mode_vdos[VDO_MAX_OBJECTS];
 	int vdo_count_ret;
 
-	if (vdo_count < VDO_MAX_SIZE)
-		return -1;
+	if (*vdo_count < VDO_MAX_SIZE)
+		return MSG_SETUP_ERROR;
 
 	switch (dp_state[port]) {
 	case DP_START:
 	case DP_ENTER_RETRY:
 		/* Enter the first supported mode for DisplayPort. */
-		vdm[0] = pd_dfp_enter_mode(port, TCPC_TX_SOP,
-				USB_SID_DISPLAYPORT, 0);
-		if (vdm[0] == 0)
-			return -1;
+		if (pd_get_mode_vdo_for_svid(port, TCPCI_MSG_SOP,
+					     USB_SID_DISPLAYPORT,
+					     mode_vdos) == 0)
+			return MSG_SETUP_ERROR;
+		if (svdm_enter_dp_mode(port, mode_vdos[dp_opos - 1]) < 0)
+			return MSG_SETUP_ERROR;
+		vdm[0] = VDO(USB_SID_DISPLAYPORT, 1,
+			     CMD_ENTER_MODE | VDO_OPOS(dp_opos));
 		/* CMDT_INIT is 0, so this is a no-op */
 		vdm[0] |= VDO_CMDT(CMDT_INIT);
-		vdm[0] |= VDO_SVDM_VERS(pd_get_vdo_ver(port, TCPC_TX_SOP));
+		vdm[0] |= VDO_SVDM_VERS(pd_get_vdo_ver(port, TCPCI_MSG_SOP));
 		vdo_count_ret = 1;
 		if (dp_state[port] == DP_START)
 			CPRINTS("C%d: Attempting to enter DP mode", port);
 		break;
 	case DP_ENTER_ACKED:
-		if (!(modep && modep->opos))
-			return -1;
-
-		vdo_count_ret = modep->fx->status(port, vdm);
+		vdo_count_ret = svdm_dp_status(port, vdm);
 		if (vdo_count_ret == 0)
-			return -1;
-		vdm[0] |= PD_VDO_OPOS(modep->opos);
+			return MSG_SETUP_ERROR;
+		vdm[0] |= PD_VDO_OPOS(dp_opos);
 		vdm[0] |= VDO_CMDT(CMDT_INIT);
-		vdm[0] |= VDO_SVDM_VERS(pd_get_vdo_ver(port, TCPC_TX_SOP));
+		vdm[0] |= VDO_SVDM_VERS(pd_get_vdo_ver(port, TCPCI_MSG_SOP));
 		break;
 	case DP_STATUS_ACKED:
-		if (!(modep && modep->opos))
-			return -1;
+		if (!get_dp_pin_mode(port))
+			return MSG_SETUP_ERROR;
+
+		dp_state[port] = DP_PREPARE_CONFIG;
 
-		vdo_count_ret = modep->fx->config(port, vdm);
+		/*
+		 * Place the USB Type-C pins that are to be re-configured to
+		 * DisplayPort Configuration into the Safe state. For
+		 * USB_PD_MUX_DOCK, the superspeed signals can remain
+		 * connected. For USB_PD_MUX_DP_ENABLED, disconnect the
+		 * superspeed signals here, before the pins are re-configured
+		 * to DisplayPort (in svdm_dp_post_config, when we receive
+		 * the config ack).
+		 */
+		if (svdm_dp_get_mux_mode(port) == USB_PD_MUX_DP_ENABLED) {
+			usb_mux_set_safe_mode(port);
+			return MSG_SETUP_MUX_WAIT;
+		}
+		/* Fall through if no mux set is needed */
+		__fallthrough;
+	case DP_PREPARE_CONFIG:
+		vdo_count_ret = svdm_dp_config(port, vdm);
 		if (vdo_count_ret == 0)
-			return -1;
+			return MSG_SETUP_ERROR;
 		vdm[0] |= VDO_CMDT(CMDT_INIT);
-		vdm[0] |= VDO_SVDM_VERS(pd_get_vdo_ver(port, TCPC_TX_SOP));
+		vdm[0] |= VDO_SVDM_VERS(pd_get_vdo_ver(port, TCPCI_MSG_SOP));
 		break;
 	case DP_ENTER_NAKED:
+		DP_SET_FLAG(port, DP_FLAG_RETRY);
+		/* Fall through to send exit mode */
+		__fallthrough;
 	case DP_ACTIVE:
 		/*
 		 * Called to exit DP alt mode, either when the mode
@@ -240,31 +332,339 @@ int dp_setup_next_vdm(int port, int vdo_count, uint32_t *vdm)
 		 * when an initial request to enter the mode is NAK'ed.
 		 * This can happen if the EC is restarted (e.g to go
 		 * into recovery mode) while DP alt mode is active.
-		 * It would be good to invoke modep->fx->exit but
-		 * this doesn't set up the VDM, it clears state.
-		 * TODO(b/159856063): Clean up the API to the fx functions.
 		 */
-		if (!(modep && modep->opos))
-			return -1;
-
-		vdm[0] = VDO(USB_SID_DISPLAYPORT,
-			     1, /* structured */
+		usb_mux_set_safe_mode_exit(port);
+		dp_state[port] = DP_PREPARE_EXIT;
+		return MSG_SETUP_MUX_WAIT;
+	case DP_PREPARE_EXIT:
+		/* DPM should call setup only after safe state is set */
+		vdm[0] = VDO(USB_SID_DISPLAYPORT, 1, /* structured */
 			     CMD_EXIT_MODE);
 
-		vdm[0] |= VDO_OPOS(modep->opos);
+		vdm[0] |= VDO_OPOS(dp_opos);
 		vdm[0] |= VDO_CMDT(CMDT_INIT);
-		vdm[0] |= VDO_SVDM_VERS(pd_get_vdo_ver(port, TCPC_TX_SOP));
+		vdm[0] |= VDO_SVDM_VERS(pd_get_vdo_ver(port, TCPCI_MSG_SOP));
 		vdo_count_ret = 1;
 		break;
 	case DP_INACTIVE:
 		/*
 		 * DP mode is inactive.
 		 */
-		return -1;
+		return MSG_SETUP_ERROR;
 	default:
-		CPRINTF("%s called with invalid state %d\n",
-				__func__, dp_state[port]);
+		CPRINTF("%s called with invalid state %d\n", __func__,
+			dp_state[port]);
+		return MSG_SETUP_ERROR;
+	}
+
+	if (vdo_count_ret) {
+		*vdo_count = vdo_count_ret;
+		return MSG_SETUP_SUCCESS;
+	}
+
+	return MSG_SETUP_UNSUPPORTED;
+}
+
+int svdm_dp_status(int port, uint32_t *payload)
+{
+	payload[0] =
+		VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_STATUS | VDO_OPOS(dp_opos));
+	payload[1] = VDO_DP_STATUS(0, /* HPD IRQ  ... not applicable */
+				   0, /* HPD level ... not applicable */
+				   0, /* exit DP? ... no */
+				   0, /* usb mode? ... no */
+				   0, /* multi-function ... no */
+				   (!!(dp_flags[port] & DP_FLAGS_DP_ON)),
+				   0, /* power low? ... no */
+				   (!!DP_FLAGS_DP_ON));
+	return 2;
+};
+
+/*
+ * This algorithm defaults to choosing higher pin config over lower ones in
+ * order to prefer multi-function if desired.
+ *
+ *  NAME | SIGNALING | OUTPUT TYPE | MULTI-FUNCTION | PIN CONFIG
+ * -------------------------------------------------------------
+ *  A    |  USB G2   |  ?          | no             | 00_0001
+ *  B    |  USB G2   |  ?          | yes            | 00_0010
+ *  C    |  DP       |  CONVERTED  | no             | 00_0100
+ *  D    |  PD       |  CONVERTED  | yes            | 00_1000
+ *  E    |  DP       |  DP         | no             | 01_0000
+ *  F    |  PD       |  DP         | yes            | 10_0000
+ *
+ * if UFP has NOT asserted multi-function preferred code masks away B/D/F
+ * leaving only A/C/E.  For single-output dongles that should leave only one
+ * possible pin config depending on whether its a converter DP->(VGA|HDMI) or DP
+ * output.  If UFP is a USB-C receptacle it may assert C/D/E/F.  The DFP USB-C
+ * receptacle must always choose C/D in those cases.
+ */
+int pd_dfp_dp_get_pin_mode(int port, uint32_t status)
+{
+	uint32_t mode_vdos[VDO_MAX_OBJECTS];
+	uint32_t mode_caps;
+	uint32_t pin_caps;
+	int mf_pref;
+
+	/*
+	 * Default dp_port_mf_allow is true, we allow mf operation
+	 * if UFP_D supports it.
+	 */
+
+	if (IS_ENABLED(CONFIG_CMD_MFALLOW))
+		mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]) &&
+			  dp_port_mf_allow[port];
+	else
+		mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]);
+
+	if (pd_get_mode_vdo_for_svid(port, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT,
+				     mode_vdos) == 0)
+		return 0;
+
+	mode_caps = mode_vdos[dp_opos - 1];
+
+	/* TODO(crosbug.com/p/39656) revisit with DFP that can be a sink */
+	pin_caps = PD_DP_PIN_CAPS(mode_caps);
+
+	/* if don't want multi-function then ignore those pin configs */
+	if (!mf_pref)
+		pin_caps &= ~MODE_DP_PIN_MF_MASK;
+
+	/* TODO(crosbug.com/p/39656) revisit if DFP drives USB Gen 2 signals */
+	pin_caps &= ~MODE_DP_PIN_BR2_MASK;
+
+	/* if C/D present they have precedence over E/F for USB-C->USB-C */
+	if (pin_caps & (MODE_DP_PIN_C | MODE_DP_PIN_D))
+		pin_caps &= ~(MODE_DP_PIN_E | MODE_DP_PIN_F);
+
+	/* get_next_bit returns undefined for zero */
+	if (!pin_caps)
+		return 0;
+
+	return 1 << get_next_bit(&pin_caps);
+}
+
+mux_state_t svdm_dp_get_mux_mode(int port)
+{
+	int pin_mode = get_dp_pin_mode(port);
+	/* Default dp_port_mf_allow is true */
+	int mf_pref;
+
+	if (IS_ENABLED(CONFIG_CMD_MFALLOW))
+		mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]) &&
+			  dp_port_mf_allow[port];
+	else
+		mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]);
+
+	/*
+	 * Multi-function operation is only allowed if that pin config is
+	 * supported.
+	 */
+	if ((pin_mode & MODE_DP_PIN_MF_MASK) && mf_pref)
+		return USB_PD_MUX_DOCK;
+	else
+		return USB_PD_MUX_DP_ENABLED;
+}
+
+/*
+ * Note: the following DP-related overridables must be kept as-is since
+ * some boards are using them in their board-specific code.
+ * TODO(b/267545470): Fold board DP code into the DP module
+ */
+__overridable void svdm_safe_dp_mode(int port)
+{
+	/* make DP interface safe until configure */
+	dp_flags[port] = 0;
+	dp_status[port] = 0;
+
+	usb_mux_set_safe_mode(port);
+}
+
+__overridable int svdm_enter_dp_mode(int port, uint32_t mode_caps)
+{
+	/*
+	 * Don't enter the mode if the SoC is off.
+	 *
+	 * There's no need to enter the mode while the SoC is off; we'll
+	 * actually enter the mode on the chipset resume hook.  Entering DP Alt
+	 * Mode twice will confuse some monitors and require and unplug/replug
+	 * to get them to work again.  The DP Alt Mode on USB-C spec says that
+	 * if we don't need to maintain HPD connectivity info in a low power
+	 * mode, then we shall exit DP Alt Mode.  (This is why we don't enter
+	 * when the SoC is off as opposed to suspend where adding a display
+	 * could cause a wake up.)  When in S5->S3 transition state, we
+	 * should treat it as a SoC off state.
+	 */
+#ifdef CONFIG_AP_POWER_CONTROL
+	if (!chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON))
 		return -1;
+#endif
+
+		/*
+		 * TCPMv2: Enable logging of CCD line state CCD_MODE_ODL.
+		 * DisplayPort Alternate mode requires that the SBU lines are
+		 * used for AUX communication. However, in Chromebooks SBU
+		 * signals are repurposed as USB2 signals for CCD. This
+		 * functionality is accomplished by override fets whose state is
+		 * controlled by CCD_MODE_ODL.
+		 *
+		 * This condition helps in debugging unexpected AUX timeout
+		 * issues by indicating the state of the CCD override fets.
+		 */
+#ifdef GPIO_CCD_MODE_ODL
+	if (!gpio_get_level(GPIO_CCD_MODE_ODL))
+		CPRINTS("WARNING: Tried to EnterMode DP with [CCD on AUX/SBU]");
+#endif
+
+	/* Only enter mode if device is DFP_D capable */
+	if (mode_caps & MODE_DP_SNK) {
+		svdm_safe_dp_mode(port);
+
+		if (IS_ENABLED(CONFIG_MKBP_EVENT) &&
+		    chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
+			/*
+			 * Wake the system up since we're entering DP AltMode.
+			 */
+			pd_notify_dp_alt_mode_entry(port);
+
+		return 0;
 	}
-	return vdo_count_ret;
+
+	return -1;
+}
+
+__overridable uint8_t get_dp_pin_mode(int port)
+{
+	return pd_dfp_dp_get_pin_mode(port, dp_status[port]);
 }
+
+/* Note: Assumes that pins have already been set in safe state if necessary */
+__overridable int svdm_dp_config(int port, uint32_t *payload)
+{
+	uint8_t pin_mode = get_dp_pin_mode(port);
+	mux_state_t mux_mode = svdm_dp_get_mux_mode(port);
+	/* Default dp_port_mf_allow is true */
+	int mf_pref;
+
+	if (IS_ENABLED(CONFIG_CMD_MFALLOW))
+		mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]) &&
+			  dp_port_mf_allow[port];
+	else
+		mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]);
+
+	if (!pin_mode)
+		return 0;
+
+	CPRINTS("pin_mode: %x, mf: %d, mux: %d", pin_mode, mf_pref, mux_mode);
+
+	payload[0] =
+		VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_CONFIG | VDO_OPOS(dp_opos));
+	payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */
+				1, /* DPv1.3 signaling */
+				2); /* UFP connected */
+	return 2;
+};
+
+__overridable void svdm_dp_post_config(int port)
+{
+	mux_state_t mux_mode = svdm_dp_get_mux_mode(port);
+	/* Connect the SBU and USB lines to the connector. */
+	typec_set_sbu(port, true);
+
+	usb_mux_set(port, mux_mode, USB_SWITCH_CONNECT,
+		    polarity_rm_dts(pd_get_polarity(port)));
+
+	dp_flags[port] |= DP_FLAGS_DP_ON;
+	if (!(dp_flags[port] & DP_FLAGS_HPD_HI_PENDING))
+		return;
+
+	dp_hpd_gpio_set(port, true, false);
+
+	usb_mux_hpd_update(port,
+			   USB_PD_MUX_HPD_LVL | USB_PD_MUX_HPD_IRQ_DEASSERTED);
+
+#ifdef USB_PD_PORT_TCPC_MST
+	if (port == USB_PD_PORT_TCPC_MST)
+		baseboard_mst_enable_control(port, 1);
+#endif
+}
+
+__overridable int svdm_dp_attention(int port, uint32_t *payload)
+{
+	int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]);
+	int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]);
+	mux_state_t mux_state;
+
+	dp_status[port] = payload[1];
+
+	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && (irq || lvl))
+		/*
+		 * Wake up the AP.  IRQ or level high indicates a DP sink is now
+		 * present.
+		 */
+		if (IS_ENABLED(CONFIG_MKBP_EVENT))
+			pd_notify_dp_alt_mode_entry(port);
+
+	/* Its initial DP status message prior to config */
+	if (!(dp_flags[port] & DP_FLAGS_DP_ON)) {
+		if (lvl)
+			dp_flags[port] |= DP_FLAGS_HPD_HI_PENDING;
+		return 1;
+	}
+
+	if (dp_hpd_gpio_set(port, lvl, irq) != EC_SUCCESS)
+		return 0;
+
+	mux_state = (lvl ? USB_PD_MUX_HPD_LVL : USB_PD_MUX_HPD_LVL_DEASSERTED) |
+		    (irq ? USB_PD_MUX_HPD_IRQ : USB_PD_MUX_HPD_IRQ_DEASSERTED);
+	usb_mux_hpd_update(port, mux_state);
+
+#ifdef USB_PD_PORT_TCPC_MST
+	if (port == USB_PD_PORT_TCPC_MST)
+		baseboard_mst_enable_control(port, lvl);
+#endif
+
+	/* ack */
+	return 1;
+}
+
+__overridable void svdm_exit_dp_mode(int port)
+{
+	dp_flags[port] = 0;
+	dp_status[port] = 0;
+	dp_hpd_gpio_set(port, false, false);
+	usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
+					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+#ifdef USB_PD_PORT_TCPC_MST
+	if (port == USB_PD_PORT_TCPC_MST)
+		baseboard_mst_enable_control(port, 0);
+#endif
+}
+
+#ifdef CONFIG_CMD_MFALLOW
+static int command_mfallow(int argc, const char **argv)
+{
+	char *e;
+	int port;
+
+	if (argc < 3)
+		return EC_ERROR_PARAM_COUNT;
+
+	port = strtoi(argv[1], &e, 10);
+	if (*e || port >= board_get_usb_pd_port_count())
+		return EC_ERROR_PARAM1;
+
+	if (!strcasecmp(argv[2], "true"))
+		dp_port_mf_allow[port] = true;
+	else if (!strcasecmp(argv[2], "false"))
+		dp_port_mf_allow[port] = false;
+	else
+		return EC_ERROR_PARAM2;
+
+	ccprintf("Port: %d multi function allowed is %s ", port, argv[2]);
+	return EC_SUCCESS;
+}
+
+DECLARE_CONSOLE_COMMAND(mfallow, command_mfallow, "port [true | false]",
+			"Controls Multifunction choice during DP Altmode.");
+#endif
diff --git a/common/usbc/dp_hpd_gpio.c b/common/usbc/dp_hpd_gpio.c
new file mode 100644
index 0000000000..3a3e75da00
--- /dev/null
+++ b/common/usbc/dp_hpd_gpio.c
@@ -0,0 +1,83 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Support for setting the Hot Plug Detect indication to the AP
+ */
+
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "gpio.h"
+#include "timer.h"
+#include "usb_pd.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#ifdef CONFIG_COMMON_RUNTIME
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+#else
+#define CPRINTF(format, args...)
+#define CPRINTS(format, args...)
+#endif
+
+/* TODO(b/270409742): Remove this macro system for determining the GPIO */
+#ifndef PORT_TO_HPD
+#define PORT_TO_HPD(port) ((port) ? GPIO_USB_C1_DP_HPD : GPIO_USB_C0_DP_HPD)
+#endif /* PORT_TO_HPD */
+
+/*
+ * Note: the following DP-related variables and functions must be kept
+ * as-is since some boards are using them in their board-specific code.
+ * TODO(b/267545470): Fold board DP code into the DP module
+ */
+
+#if defined(CONFIG_USB_PD_DP_HPD_GPIO) && \
+	!defined(CONFIG_USB_PD_DP_HPD_GPIO_CUSTOM)
+void svdm_set_hpd_gpio(int port, int en)
+{
+	gpio_set_level(PORT_TO_HPD(port), en);
+}
+
+int svdm_get_hpd_gpio(int port)
+{
+	return gpio_get_level(PORT_TO_HPD(port));
+}
+#endif
+
+enum ec_error_list dp_hpd_gpio_set(int port, bool level, bool irq)
+{
+	int cur_level = svdm_get_hpd_gpio(port);
+
+	if (irq && !level) {
+		/*
+		 * IRQ can only be generated when the level is high, because
+		 * the IRQ is signaled by a short low pulse from the high level.
+		 */
+		CPRINTF("ERR:HPD:IRQ&LOW\n");
+		return EC_ERROR_INVAL;
+	}
+
+	if (irq && cur_level) {
+		uint64_t now = get_time().val;
+		/* wait for the minimum spacing between IRQ_HPD if needed */
+		if (now < svdm_hpd_deadline[port])
+			usleep(svdm_hpd_deadline[port] - now);
+
+		/* generate IRQ_HPD pulse */
+		svdm_set_hpd_gpio(port, 0);
+		usleep(HPD_DSTREAM_DEBOUNCE_IRQ);
+		svdm_set_hpd_gpio(port, 1);
+	} else {
+		svdm_set_hpd_gpio(port, level);
+	}
+
+	/* set the minimum time delay (2ms) for the next HPD IRQ */
+	svdm_hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
+
+	return EC_SUCCESS;
+}
diff --git a/common/usbc/svdm_rsp_dfp_only.c b/common/usbc/svdm_rsp_dfp_only.c
new file mode 100644
index 0000000000..ee2b11a379
--- /dev/null
+++ b/common/usbc/svdm_rsp_dfp_only.c
@@ -0,0 +1,50 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * SVDM identity support for DFP-only devices.
+ *
+ * This file is only supported for Zephyr builds, enabled by
+ * CONFIG_SVDM_RSP_DFP_ONLY. No equivalent config exists for EC-OS.
+ */
+
+#include "usb_pd.h"
+
+static int svdm_identity(int port, uint32_t *payload)
+{
+	if (pd_get_rev(port, TCPCI_MSG_SOP) < PD_REV30) {
+		/*
+		 * PD 2 requires that DFPs nack received SVDM requests when no
+		 * modes are supported. PD 3 allows a response.
+		 */
+		return 0;
+	}
+
+	payload[VDO_I(CSTAT)] = VDO_CSTAT(CONFIG_USB_PD_XID);
+	payload[VDO_I(PRODUCT)] =
+		VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV);
+
+	payload[VDO_I(IDH)] = VDO_IDH_REV30(1, /* USB host */
+					    0, /* Not a USB device */
+					    IDH_PTYPE_UNDEF, /* Not a UFP */
+					    0, /* No alt modes (not a UFP) */
+					    IDH_PTYPE_DFP_HOST, /* PDUSB host */
+					    USB_TYPEC_RECEPTACLE,
+					    CONFIG_USB_VID);
+	/* Single VDO for DFP product type */
+	payload[VDO_I(PRODUCT) + 1] = VDO_DFP(VDO_DFP_HOST_CAPABILITY_USB32,
+					      USB_TYPEC_RECEPTACLE, port);
+	return VDO_I(PRODUCT) + 2;
+}
+
+__override const struct svdm_response svdm_rsp = {
+	.identity = svdm_identity,
+	/*
+	 * Discover Identity support is required for devices with more than one
+	 * DFP, but other SVDM commands are optional. We don't support operating
+	 * as Responder in any mode, so leave them unimplemented. See 6.13.5,
+	 * Applicability of Structured VDM Commands.
+	 */
+};
diff --git a/common/usbc/tbt_alt_mode.c b/common/usbc/tbt_alt_mode.c
index 4b79f26efb..5c02eb30fb 100644
--- a/common/usbc/tbt_alt_mode.c
+++ b/common/usbc/tbt_alt_mode.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,18 +8,22 @@
  * Refer to USB Type-C Cable and Connector Specification Release 2.0 Section F
  */
 
-#include <stdbool.h>
-#include <stdint.h>
+#include "atomic.h"
 #include "compile_time_macros.h"
 #include "console.h"
-#include "tcpm.h"
+#include "tcpm/tcpm.h"
+#include "typec_control.h"
+#include "usb_common.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
-#include "usb_pd_dpm.h"
 #include "usb_pd_tbt.h"
+#include "usb_pd_tcpm.h"
 #include "usb_pe_sm.h"
 #include "usb_tbt_alt_mode.h"
 
+#include <stdbool.h>
+#include <stdint.h>
+
 /*
  * Enter/Exit TBT mode with active cable
  *
@@ -55,8 +59,8 @@
  */
 
 #ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 #else
 #define CPRINTF(format, args...)
 #define CPRINTS(format, args...)
@@ -68,7 +72,18 @@
  * with a partner. It may be fixed in b/159495742, in which case this
  * logic is unneeded.
  */
-static bool retry_done;
+#define TBT_FLAG_RETRY_DONE BIT(0)
+#define TBT_FLAG_EXIT_DONE BIT(1)
+#define TBT_FLAG_CABLE_ENTRY_DONE BIT(2)
+
+static uint8_t tbt_flags[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+#define TBT_SET_FLAG(port, flag) (tbt_flags[port] |= (flag))
+#define TBT_CLR_FLAG(port, flag) (tbt_flags[port] &= (~flag))
+#define TBT_CHK_FLAG(port, flag) (tbt_flags[port] & (flag))
+
+/* Note: there is currently only one defined TBT mode */
+static const int tbt_opos = 1;
 
 static int tbt_prints(const char *string, int port)
 {
@@ -80,6 +95,8 @@ enum tbt_states {
 	TBT_START = 0,
 	TBT_ENTER_SOP,
 	TBT_ACTIVE,
+	/* Set to force Exit mode from non-Active states */
+	TBT_PREPARE_EXIT_MODE,
 	TBT_EXIT_SOP,
 	TBT_INACTIVE,
 	/* Active cable only */
@@ -93,7 +110,6 @@ static enum tbt_states tbt_state[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 static const uint8_t state_vdm_cmd[TBT_STATE_COUNT] = {
 	[TBT_ENTER_SOP] = CMD_ENTER_MODE,
-	[TBT_ACTIVE] = CMD_EXIT_MODE,
 	[TBT_EXIT_SOP] = CMD_EXIT_MODE,
 	/* Active cable only */
 	[TBT_ENTER_SOP_PRIME] = CMD_ENTER_MODE,
@@ -105,33 +121,117 @@ static const uint8_t state_vdm_cmd[TBT_STATE_COUNT] = {
 void tbt_init(int port)
 {
 	tbt_state[port] = TBT_START;
-	retry_done = false;
+	TBT_CLR_FLAG(port, TBT_FLAG_RETRY_DONE);
+	TBT_SET_FLAG(port, TBT_FLAG_EXIT_DONE);
+	TBT_CLR_FLAG(port, TBT_FLAG_CABLE_ENTRY_DONE);
 }
 
 bool tbt_is_active(int port)
 {
-	return tbt_state[port] == TBT_ACTIVE;
+	return tbt_state[port] != TBT_INACTIVE && tbt_state[port] != TBT_START;
+}
+
+bool tbt_entry_is_done(int port)
+{
+	return tbt_state[port] == TBT_ACTIVE || tbt_state[port] == TBT_INACTIVE;
 }
 
-void tbt_teardown(int port)
+bool tbt_cable_entry_is_done(int port)
 {
-	 tbt_prints("teardown", port);
-	 tbt_state[port] = TBT_INACTIVE;
-	 retry_done = false;
+	return TBT_CHK_FLAG(port, TBT_FLAG_CABLE_ENTRY_DONE);
 }
 
-static void tbt_entry_failed(int port)
+static void tbt_exit_done(int port)
 {
+	/*
+	 * If the EC exits an alt mode autonomously, don't try to enter it
+	 * again. If the AP commands the EC to exit DP mode, it might command
+	 * the EC to enter again later, so leave the state machine ready for
+	 * that possibility.
+	 */
+	tbt_state[port] = IS_ENABLED(CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY) ?
+				  TBT_START :
+				  TBT_INACTIVE;
+	TBT_CLR_FLAG(port, TBT_FLAG_RETRY_DONE);
+	TBT_CLR_FLAG(port, TBT_FLAG_CABLE_ENTRY_DONE);
+
+	if (!TBT_CHK_FLAG(port, TBT_FLAG_EXIT_DONE)) {
+		TBT_SET_FLAG(port, TBT_FLAG_EXIT_DONE);
+		tbt_prints("Exited alternate mode", port);
+		return;
+	}
+
 	tbt_prints("alt mode protocol failed!", port);
-	tbt_state[port] = TBT_INACTIVE;
-	retry_done = false;
-	dpm_set_mode_entry_done(port);
 }
 
-static bool tbt_response_valid(int port, enum tcpm_transmit_type type,
-				char *cmdt, int vdm_cmd)
+static bool tbt_is_lrd_active_cable(int port)
+{
+	union tbt_mode_resp_cable cable_mode_resp;
+
+	cable_mode_resp.raw_value =
+		pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME);
+	if (get_usb_pd_cable_type(port) == IDH_PTYPE_PCABLE &&
+	    cable_mode_resp.tbt_active_passive == TBT_CABLE_ACTIVE)
+		return true;
+
+	return false;
+}
+
+/* Check if this port requires SOP' mode entry and exit */
+static bool tbt_sop_prime_needed(int port)
+{
+	/*
+	 * We require SOP' entry if cable is
+	 * active cable, or
+	 * an LRD cable (passive in DiscoverIdentity, active in TBT mode)
+	 */
+	if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE ||
+	    tbt_is_lrd_active_cable(port))
+		return true;
+	return false;
+}
+
+/* Check if this port requires SOP'' mode entry and exit */
+static bool tbt_sop_prime_prime_needed(int port)
+{
+	const struct pd_discovery *disc;
+
+	disc = pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
+	if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE &&
+	    disc->identity.product_t1.a_rev20.sop_p_p)
+		return true;
+	return false;
+}
+
+void tbt_exit_mode_request(int port)
+{
+	TBT_SET_FLAG(port, TBT_FLAG_RETRY_DONE);
+	TBT_CLR_FLAG(port, TBT_FLAG_EXIT_DONE);
+	/*
+	 * If the port has entered USB4 mode with Thunderbolt mode for the
+	 * cable, on request to exit, only exit Thunderbolt mode for the
+	 * cable.
+	 * TODO (b/156749387): Remove once data reset feature is in place.
+	 */
+	if (tbt_state[port] == TBT_ENTER_SOP) {
+		/*
+		 * For Linear re-driver cables, the port enters USB4 mode
+		 * with Thunderbolt mode for SOP prime. Hence, on request to
+		 * exit, only exit Thunderbolt mode SOP prime
+		 */
+		tbt_state[port] = tbt_sop_prime_prime_needed(port) ?
+					  TBT_EXIT_SOP_PRIME_PRIME :
+					  TBT_EXIT_SOP_PRIME;
+	}
+}
+
+static bool tbt_response_valid(int port, enum tcpci_msg_type type, char *cmdt,
+			       int vdm_cmd)
 {
 	enum tbt_states st = tbt_state[port];
+	union tbt_mode_resp_cable cable_mode_resp = {
+		.raw_value = pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME)
+	};
 
 	/*
 	 * Check for an unexpected response.
@@ -141,8 +241,9 @@ static bool tbt_response_valid(int port, enum tcpm_transmit_type type,
 	 */
 	if ((st != TBT_INACTIVE && state_vdm_cmd[st] != vdm_cmd) ||
 	    (get_usb_pd_cable_type(port) == IDH_PTYPE_PCABLE &&
-	     type != TCPC_TX_SOP)) {
-		tbt_entry_failed(port);
+	     cable_mode_resp.tbt_active_passive == TBT_CABLE_PASSIVE &&
+	     type != TCPCI_MSG_SOP)) {
+		tbt_exit_done(port);
 		return false;
 	}
 	return true;
@@ -152,83 +253,101 @@ static bool tbt_response_valid(int port, enum tcpm_transmit_type type,
 static void tbt_retry_enter_mode(int port)
 {
 	tbt_state[port] = TBT_START;
-	retry_done = true;
+	TBT_SET_FLAG(port, TBT_FLAG_RETRY_DONE);
 }
 
-/* Send Exit Mode to SOP''(if supported), or SOP' */
-static void tbt_active_cable_exit_mode(int port)
+bool tbt_cable_entry_required_for_usb4(int port)
 {
-	struct pd_discovery *disc;
+	const struct pd_discovery *disc_sop_prime;
 
-	disc = pd_get_am_discovery(port, TCPC_TX_SOP_PRIME);
+	if (tbt_cable_entry_is_done(port))
+		return false;
 
-	if (disc->identity.product_t1.a_rev20.sop_p_p)
-		tbt_state[port] = TBT_EXIT_SOP_PRIME_PRIME;
-	else
-		tbt_state[port] = TBT_EXIT_SOP_PRIME;
+	/*
+	 * For some cables, the TCPM may need to enter TBT mode with the
+	 * cable to support USB4 mode with the partner. Request to enter
+	 * Thunderbolt mode for the cable prior to entering USB4 for
+	 * the port partner if
+	 * 1. The cable advertises itself as passive in its Identity VDO
+	 * but active in its TBT mode VDO, or
+	 * 2. The cable advertises itself as active, but its PD support
+	 * is not new enough to support Enter_USB.
+	 */
+	if (tbt_is_lrd_active_cable(port))
+		return true;
+
+	if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE) {
+		disc_sop_prime = pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
+		if (pd_get_vdo_ver(port, TCPCI_MSG_SOP_PRIME) < VDM_VER20 ||
+		    disc_sop_prime->identity.product_t1.a_rev30.vdo_ver <
+			    VDO_VERSION_1_3)
+			return true;
+	}
+	return false;
 }
 
-void intel_vdm_acked(int port, enum tcpm_transmit_type type, int vdo_count,
-		uint32_t *vdm)
+void intel_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count,
+		     uint32_t *vdm)
 {
-	struct pd_discovery *disc;
 	const uint8_t vdm_cmd = PD_VDO_CMD(vdm[0]);
 
 	if (!tbt_response_valid(port, type, "ACK", vdm_cmd))
 		return;
 
-	disc = pd_get_am_discovery(port, TCPC_TX_SOP_PRIME);
-
 	switch (tbt_state[port]) {
 	case TBT_ENTER_SOP_PRIME:
-		if (disc->identity.product_t1.a_rev20.sop_p_p)
+		tbt_prints("enter mode SOP'", port);
+		/* For LRD cables, Enter mode SOP' -> Enter mode SOP */
+		if (tbt_sop_prime_prime_needed(port)) {
 			tbt_state[port] = TBT_ENTER_SOP_PRIME_PRIME;
-		else
+		} else {
+			TBT_SET_FLAG(port, TBT_FLAG_CABLE_ENTRY_DONE);
 			tbt_state[port] = TBT_ENTER_SOP;
+		}
 		break;
 	case TBT_ENTER_SOP_PRIME_PRIME:
+		tbt_prints("enter mode SOP''", port);
+		TBT_SET_FLAG(port, TBT_FLAG_CABLE_ENTRY_DONE);
 		tbt_state[port] = TBT_ENTER_SOP;
 		break;
 	case TBT_ENTER_SOP:
 		set_tbt_compat_mode_ready(port);
-		dpm_set_mode_entry_done(port);
 		tbt_state[port] = TBT_ACTIVE;
-		retry_done = true;
 		tbt_prints("enter mode SOP", port);
-		break;
-	case TBT_ACTIVE:
-		if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE)
-			tbt_active_cable_exit_mode(port);
-		else {
-			/*
-			 * Exit Mode process is complete; go to inactive state.
-			 */
-			tbt_prints("exit mode SOP", port);
-			tbt_state[port] = TBT_INACTIVE;
-			retry_done = false;
-		}
+		TBT_SET_FLAG(port, TBT_FLAG_RETRY_DONE);
+		/* Indicate to PE layer that alt mode is active */
+		pd_set_dfp_enter_mode_flag(port, true);
 		break;
 	case TBT_EXIT_SOP:
-		if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE)
-			tbt_active_cable_exit_mode(port);
-		else {
-			if (retry_done)
+		tbt_prints("exit mode SOP", port);
+		pd_set_dfp_enter_mode_flag(port, false);
+
+		if (tbt_sop_prime_prime_needed(port)) {
+			tbt_state[port] = TBT_EXIT_SOP_PRIME_PRIME;
+		} else if (tbt_sop_prime_needed(port)) {
+			tbt_state[port] = TBT_EXIT_SOP_PRIME;
+		} else {
+			set_usb_mux_with_current_data_role(port);
+			if (TBT_CHK_FLAG(port, TBT_FLAG_RETRY_DONE))
 				/* retried enter mode, still failed, give up */
-				tbt_entry_failed(port);
+				tbt_exit_done(port);
 			else
 				tbt_retry_enter_mode(port);
 		}
 		break;
 	case TBT_EXIT_SOP_PRIME_PRIME:
+		tbt_prints("exit mode SOP''", port);
 		tbt_state[port] = TBT_EXIT_SOP_PRIME;
 		break;
 	case TBT_EXIT_SOP_PRIME:
-		if (retry_done) {
+		tbt_prints("exit mode SOP'", port);
+		if (TBT_CHK_FLAG(port, TBT_FLAG_RETRY_DONE)) {
 			/*
 			 * Exit mode process is complete; go to inactive state.
 			 */
-			tbt_prints("exit mode SOP'", port);
-			tbt_entry_failed(port);
+			tbt_exit_done(port);
+			/* Clear Thunderbolt related signals */
+			set_usb_mux_with_current_data_role(port);
 		} else {
 			tbt_retry_enter_mode(port);
 		}
@@ -242,14 +361,14 @@ void intel_vdm_acked(int port, enum tcpm_transmit_type type, int vdo_count,
 		break;
 	default:
 		/* Invalid or unexpected negotiation state */
-		 CPRINTF("%s called with invalid state %d\n",
-				__func__, tbt_state[port]);
-		tbt_entry_failed(port);
+		CPRINTF("%s called with invalid state %d\n", __func__,
+			tbt_state[port]);
+		tbt_exit_done(port);
 		break;
 	}
 }
 
-void intel_vdm_naked(int port, enum tcpm_transmit_type type, uint8_t vdm_cmd)
+void intel_vdm_naked(int port, enum tcpci_msg_type type, uint8_t vdm_cmd)
 {
 	if (!tbt_response_valid(port, type, "NAK", vdm_cmd))
 		return;
@@ -264,26 +383,21 @@ void intel_vdm_naked(int port, enum tcpm_transmit_type type, uint8_t vdm_cmd)
 		 * so request to exit the mode first before retrying the enter
 		 * command. This can happen if the EC is restarted
 		 */
-		tbt_state[port] = TBT_EXIT_SOP;
-		break;
-	case TBT_ACTIVE:
-		/* Exit SOP got NAK'ed */
-		if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE)
-			tbt_active_cable_exit_mode(port);
-		else {
-			tbt_prints("exit mode SOP failed", port);
-			tbt_state[port] = TBT_INACTIVE;
-			retry_done = false;
-		}
+		tbt_state[port] = TBT_PREPARE_EXIT_MODE;
 		break;
 	case TBT_EXIT_SOP:
 		/* Exit SOP got NAK'ed */
-		if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE)
-			tbt_active_cable_exit_mode(port);
-		else {
-			if (retry_done)
+		tbt_prints("exit mode SOP failed", port);
+
+		if (tbt_sop_prime_prime_needed(port)) {
+			tbt_state[port] = TBT_EXIT_SOP_PRIME_PRIME;
+		} else if (tbt_sop_prime_needed(port)) {
+			tbt_state[port] = TBT_EXIT_SOP_PRIME;
+		} else {
+			set_usb_mux_with_current_data_role(port);
+			if (TBT_CHK_FLAG(port, TBT_FLAG_RETRY_DONE))
 				/* Retried enter mode, still failed, give up */
-				tbt_entry_failed(port);
+				tbt_exit_done(port);
 			else
 				tbt_retry_enter_mode(port);
 		}
@@ -293,20 +407,21 @@ void intel_vdm_naked(int port, enum tcpm_transmit_type type, uint8_t vdm_cmd)
 		tbt_state[port] = TBT_EXIT_SOP_PRIME;
 		break;
 	case TBT_EXIT_SOP_PRIME:
-		if (retry_done) {
+		set_usb_mux_with_current_data_role(port);
+		if (TBT_CHK_FLAG(port, TBT_FLAG_RETRY_DONE)) {
 			/*
 			 * Exit mode process is complete; go to inactive state.
 			 */
 			tbt_prints("exit mode SOP' failed", port);
-			tbt_entry_failed(port);
+			tbt_exit_done(port);
 		} else {
 			tbt_retry_enter_mode(port);
 		}
 		break;
 	default:
-		CPRINTS("C%d: NAK for cmd %d in state %d", port,
-			vdm_cmd, tbt_state[port]);
-		tbt_entry_failed(port);
+		CPRINTS("C%d: NAK for cmd %d in state %d", port, vdm_cmd,
+			tbt_state[port]);
+		tbt_exit_done(port);
 		break;
 	}
 }
@@ -314,117 +429,306 @@ void intel_vdm_naked(int port, enum tcpm_transmit_type type, uint8_t vdm_cmd)
 static bool tbt_mode_is_supported(int port, int vdo_count)
 {
 	const struct pd_discovery *disc =
-			pd_get_am_discovery(port, TCPC_TX_SOP);
+		pd_get_am_discovery(port, TCPCI_MSG_SOP);
+
+	if (!disc->identity.idh.modal_support)
+		return false;
+
+	if (get_tbt_cable_speed(port) < TBT_SS_U31_GEN1)
+		return false;
+
+	/*
+	 * TBT4 PD Discovery Flow Application Notes Revision 0.9:
+	 * Figure 2: for active cable, SOP' should support
+	 * SVID USB_VID_INTEL to enter Thunderbolt alt mode
+	 */
+	if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE &&
+	    !pd_is_mode_discovered_for_svid(port, TCPCI_MSG_SOP_PRIME,
+					    USB_VID_INTEL))
+		return false;
 
-	return disc->identity.idh.modal_support &&
-		is_tbt_cable_superspeed(port) &&
-		get_tbt_cable_speed(port) >= TBT_SS_U31_GEN1;
+	return true;
 }
 
-int tbt_setup_next_vdm(int port, int vdo_count, uint32_t *vdm,
-		enum tcpm_transmit_type *tx_type)
+enum dpm_msg_setup_status tbt_setup_next_vdm(int port, int *vdo_count,
+					     uint32_t *vdm,
+					     enum tcpci_msg_type *tx_type)
 {
-	struct svdm_amode_data *modep;
 	int vdo_count_ret = 0;
 
-	*tx_type = TCPC_TX_SOP;
+	*tx_type = TCPCI_MSG_SOP;
 
-	if (vdo_count < VDO_MAX_SIZE)
-		return -1;
+	if (*vdo_count < VDO_MAX_SIZE)
+		return MSG_SETUP_ERROR;
 
 	switch (tbt_state[port]) {
 	case TBT_START:
-		if (!tbt_mode_is_supported(port, vdo_count))
-			return 0;
+		if (!tbt_mode_is_supported(port, *vdo_count))
+			return MSG_SETUP_UNSUPPORTED;
 
-		if (!retry_done)
+		if (!TBT_CHK_FLAG(port, TBT_FLAG_RETRY_DONE))
 			tbt_prints("attempt to enter mode", port);
 		else
 			tbt_prints("retry to enter mode", port);
-		/* Active cable send Enter Mode SOP' first */
-		if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE) {
-			vdo_count_ret =
-				enter_tbt_compat_mode(
-					port, TCPC_TX_SOP_PRIME, vdm);
-			*tx_type = TCPC_TX_SOP_PRIME;
+
+		/*
+		 * Enter safe mode before sending Enter mode SOP/SOP'/SOP''
+		 * Ref: Tiger Lake Platform PD Controller Interface
+		 * Requirements for Integrated USB C, section A.1.2 TBT as DFP.
+		 */
+		usb_mux_set_safe_mode(port);
+
+		/* Active cable and LRD cables send Enter Mode SOP' first */
+		if (tbt_sop_prime_needed(port)) {
 			tbt_state[port] = TBT_ENTER_SOP_PRIME;
 		} else {
 			/* Passive cable send Enter Mode SOP */
-			vdo_count_ret =
-				enter_tbt_compat_mode(port, TCPC_TX_SOP, vdm);
 			tbt_state[port] = TBT_ENTER_SOP;
 		}
-		break;
+
+		return MSG_SETUP_MUX_WAIT;
 	case TBT_ENTER_SOP_PRIME:
 		vdo_count_ret =
-			enter_tbt_compat_mode(port, TCPC_TX_SOP_PRIME, vdm);
-		*tx_type = TCPC_TX_SOP_PRIME;
+			enter_tbt_compat_mode(port, TCPCI_MSG_SOP_PRIME, vdm);
+		*tx_type = TCPCI_MSG_SOP_PRIME;
 		break;
 	case TBT_ENTER_SOP_PRIME_PRIME:
-		vdo_count_ret =
-			enter_tbt_compat_mode(
-				port, TCPC_TX_SOP_PRIME_PRIME, vdm);
-		*tx_type = TCPC_TX_SOP_PRIME_PRIME;
+		vdo_count_ret = enter_tbt_compat_mode(
+			port, TCPCI_MSG_SOP_PRIME_PRIME, vdm);
+		*tx_type = TCPCI_MSG_SOP_PRIME_PRIME;
 		break;
 	case TBT_ENTER_SOP:
-		vdo_count_ret =
-			enter_tbt_compat_mode(port, TCPC_TX_SOP, vdm);
+		vdo_count_ret = enter_tbt_compat_mode(port, TCPCI_MSG_SOP, vdm);
 		break;
-	case TBT_EXIT_SOP:
 	case TBT_ACTIVE:
+		/*
+		 * Since we had successfully entered mode, consider ourselves
+		 * done with any retires.
+		 */
+		TBT_SET_FLAG(port, TBT_FLAG_RETRY_DONE);
+		__fallthrough;
+	case TBT_PREPARE_EXIT_MODE:
 		/*
 		 * Called to exit Thunderbolt alt mode, either when the mode is
 		 * active and the system is shutting down, or when an initial
 		 * request to enter the mode is NAK'ed. This can happen if EC
 		 * is restarted while Thunderbolt mode is active.
 		 */
-		modep = pd_get_amode_data(port,
-					  TCPC_TX_SOP, USB_VID_INTEL);
-		if (!(modep && modep->opos))
-			return -1;
+		usb_mux_set_safe_mode_exit(port);
 
+		tbt_state[port] = TBT_EXIT_SOP;
+		return MSG_SETUP_MUX_WAIT;
+	case TBT_EXIT_SOP:
+		/* DPM will only call this after safe state set is done */
 		vdm[0] = VDO(USB_VID_INTEL, 1, CMD_EXIT_MODE) |
-			VDO_OPOS(modep->opos) |
-			VDO_CMDT(CMDT_INIT) |
-			VDO_SVDM_VERS(
-				pd_get_vdo_ver(port, TCPC_TX_SOP));
+			 VDO_OPOS(tbt_opos) | VDO_CMDT(CMDT_INIT) |
+			 VDO_SVDM_VERS(pd_get_vdo_ver(port, TCPCI_MSG_SOP));
 		vdo_count_ret = 1;
 		break;
 	case TBT_EXIT_SOP_PRIME_PRIME:
-		modep = pd_get_amode_data(port,
-			TCPC_TX_SOP_PRIME, USB_VID_INTEL);
-		if (!(modep && modep->opos))
-			return -1;
-
 		vdm[0] = VDO(USB_VID_INTEL, 1, CMD_EXIT_MODE) |
-			VDO_OPOS(modep->opos) |
-			VDO_CMDT(CMDT_INIT) |
-			VDO_SVDM_VERS(pd_get_vdo_ver(port,
-				TCPC_TX_SOP_PRIME_PRIME));
+			 VDO_OPOS(tbt_opos) | VDO_CMDT(CMDT_INIT) |
+			 VDO_SVDM_VERS(pd_get_vdo_ver(
+				 port, TCPCI_MSG_SOP_PRIME_PRIME));
 		vdo_count_ret = 1;
-		*tx_type = TCPC_TX_SOP_PRIME_PRIME;
+		*tx_type = TCPCI_MSG_SOP_PRIME_PRIME;
 		break;
 	case TBT_EXIT_SOP_PRIME:
-		modep = pd_get_amode_data(port,
-				TCPC_TX_SOP_PRIME, USB_VID_INTEL);
-		if (!(modep && modep->opos))
-			return -1;
-
 		vdm[0] = VDO(USB_VID_INTEL, 1, CMD_EXIT_MODE) |
-			VDO_OPOS(modep->opos) |
-			VDO_CMDT(CMDT_INIT) |
-			VDO_SVDM_VERS(pd_get_vdo_ver(port, TCPC_TX_SOP_PRIME));
+			 VDO_OPOS(tbt_opos) | VDO_CMDT(CMDT_INIT) |
+			 VDO_SVDM_VERS(
+				 pd_get_vdo_ver(port, TCPCI_MSG_SOP_PRIME));
 		vdo_count_ret = 1;
-		*tx_type = TCPC_TX_SOP_PRIME;
+		*tx_type = TCPCI_MSG_SOP_PRIME;
 		break;
 	case TBT_INACTIVE:
 		/* Thunderbolt mode is inactive */
-		return 0;
+		return MSG_SETUP_UNSUPPORTED;
 	default:
-		 CPRINTF("%s called with invalid state %d\n",
-				__func__, tbt_state[port]);
-		return -1;
+		CPRINTF("%s called with invalid state %d\n", __func__,
+			tbt_state[port]);
+		return MSG_SETUP_ERROR;
 	}
 
-	return vdo_count_ret;
+	if (vdo_count_ret) {
+		*vdo_count = vdo_count_ret;
+		return MSG_SETUP_SUCCESS;
+	}
+
+	return MSG_SETUP_UNSUPPORTED;
+}
+
+uint32_t pd_get_tbt_mode_vdo(int port, enum tcpci_msg_type type)
+{
+	uint32_t tbt_mode_vdo[VDO_MAX_OBJECTS];
+
+	return pd_get_mode_vdo_for_svid(port, type, USB_VID_INTEL,
+					tbt_mode_vdo) ?
+		       tbt_mode_vdo[0] :
+		       0;
+}
+
+void set_tbt_compat_mode_ready(int port)
+{
+	if (IS_ENABLED(CONFIG_USBC_SS_MUX) &&
+	    IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE)) {
+		/* Connect the SBU and USB lines to the connector. */
+		typec_set_sbu(port, true);
+
+		/* Set usb mux to Thunderbolt-compatible mode */
+		usb_mux_set(port, USB_PD_MUX_TBT_COMPAT_ENABLED,
+			    USB_SWITCH_CONNECT,
+			    polarity_rm_dts(pd_get_polarity(port)));
+	}
+}
+
+/*
+ * Ref: USB Type-C Cable and Connector Specification
+ * Figure F-1 TBT3 Discovery Flow
+ */
+static bool is_tbt_cable_superspeed(int port)
+{
+	const struct pd_discovery *disc;
+
+	if (!IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE) ||
+	    !IS_ENABLED(CONFIG_USB_PD_DECODE_SOP))
+		return false;
+
+	disc = pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
+
+	/* Product type is Active cable, hence don't check for speed */
+	if (disc->identity.idh.product_type == IDH_PTYPE_ACABLE)
+		return true;
+
+	if (disc->identity.idh.product_type != IDH_PTYPE_PCABLE)
+		return false;
+
+	if (IS_ENABLED(CONFIG_USB_PD_REV30) &&
+	    pd_get_rev(port, TCPCI_MSG_SOP_PRIME) == PD_REV30)
+		return disc->identity.product_t1.p_rev30.ss ==
+			       USB_R30_SS_U32_U40_GEN1 ||
+		       disc->identity.product_t1.p_rev30.ss ==
+			       USB_R30_SS_U32_U40_GEN2 ||
+		       disc->identity.product_t1.p_rev30.ss ==
+			       USB_R30_SS_U40_GEN3;
+
+	return disc->identity.product_t1.p_rev20.ss == USB_R20_SS_U31_GEN1 ||
+	       disc->identity.product_t1.p_rev20.ss == USB_R20_SS_U31_GEN1_GEN2;
+}
+
+static enum tbt_compat_cable_speed usb_rev30_to_tbt_speed(enum usb_rev30_ss ss)
+{
+	switch (ss) {
+	case USB_R30_SS_U32_U40_GEN1:
+		return TBT_SS_U31_GEN1;
+	case USB_R30_SS_U32_U40_GEN2:
+		return TBT_SS_U32_GEN1_GEN2;
+	case USB_R30_SS_U40_GEN3:
+		return TBT_SS_TBT_GEN3;
+	default:
+		return TBT_SS_U32_GEN1_GEN2;
+	}
+}
+
+enum tbt_compat_cable_speed get_tbt_cable_speed(int port)
+{
+	union tbt_mode_resp_cable cable_mode_resp;
+	enum tbt_compat_cable_speed max_tbt_speed;
+	enum tbt_compat_cable_speed cable_tbt_speed;
+
+	if (!is_tbt_cable_superspeed(port))
+		return TBT_SS_RES_0;
+
+	cable_mode_resp.raw_value =
+		pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME);
+	max_tbt_speed = board_get_max_tbt_speed(port);
+
+	/*
+	 * Ref: TBT4 PD Discovery Flow Application Notes Revision 0.9, Figure 2
+	 * For passive cable, if cable doesn't support USB_VID_INTEL, enter
+	 * Thunderbolt alternate mode with speed from USB Highest Speed field of
+	 * the Passive Cable VDO
+	 * For active cable, if the cable doesn't support USB_VID_INTEL, do not
+	 * enter Thunderbolt alternate mode.
+	 */
+	if (!cable_mode_resp.raw_value) {
+		const struct pd_discovery *disc;
+
+		if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE)
+			return TBT_SS_RES_0;
+
+		disc = pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
+		cable_tbt_speed = usb_rev30_to_tbt_speed(
+			disc->identity.product_t1.p_rev30.ss);
+	} else {
+		cable_tbt_speed = cable_mode_resp.tbt_cable_speed;
+	}
+
+	return max_tbt_speed < cable_tbt_speed ? max_tbt_speed :
+						 cable_tbt_speed;
+}
+
+/* Note: Assumes that pins have already been set in safe state */
+int enter_tbt_compat_mode(int port, enum tcpci_msg_type sop, uint32_t *payload)
+{
+	union tbt_dev_mode_enter_cmd enter_dev_mode = { .raw_value = 0 };
+	union tbt_mode_resp_device dev_mode_resp;
+	union tbt_mode_resp_cable cable_mode_resp;
+	enum tcpci_msg_type enter_mode_sop =
+		sop == TCPCI_MSG_SOP_PRIME_PRIME ? TCPCI_MSG_SOP_PRIME : sop;
+
+	/* Table F-12 TBT3 Cable Enter Mode Command */
+	/*
+	 * The port doesn't query Discover SOP'' to the cable so, the port
+	 * doesn't have opos for SOP''. Hence, send Enter Mode SOP'' with same
+	 * opos and revision as SOP'.
+	 */
+	payload[0] =
+		VDO(USB_VID_INTEL, 1, CMD_ENTER_MODE | VDO_OPOS(tbt_opos)) |
+		VDO_CMDT(CMDT_INIT) |
+		VDO_SVDM_VERS(pd_get_vdo_ver(port, enter_mode_sop));
+
+	/* For TBT3 Cable Enter Mode Command, number of Objects is 1 */
+	if ((sop == TCPCI_MSG_SOP_PRIME) || (sop == TCPCI_MSG_SOP_PRIME_PRIME))
+		return 1;
+
+	dev_mode_resp.raw_value = pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP);
+	cable_mode_resp.raw_value =
+		pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME);
+
+	/* Table F-13 TBT3 Device Enter Mode Command */
+	enter_dev_mode.vendor_spec_b1 = dev_mode_resp.vendor_spec_b1;
+	enter_dev_mode.vendor_spec_b0 = dev_mode_resp.vendor_spec_b0;
+	enter_dev_mode.intel_spec_b0 = dev_mode_resp.intel_spec_b0;
+
+	if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE ||
+	    cable_mode_resp.tbt_active_passive == TBT_CABLE_ACTIVE)
+		enter_dev_mode.cable = TBT_ENTER_ACTIVE_CABLE;
+
+	enter_dev_mode.lsrx_comm = cable_mode_resp.lsrx_comm;
+	enter_dev_mode.retimer_type = cable_mode_resp.retimer_type;
+	enter_dev_mode.tbt_cable = cable_mode_resp.tbt_cable;
+	enter_dev_mode.tbt_rounded = cable_mode_resp.tbt_rounded;
+	enter_dev_mode.tbt_cable_speed = get_tbt_cable_speed(port);
+	enter_dev_mode.tbt_alt_mode = TBT_ALTERNATE_MODE;
+
+	payload[1] = enter_dev_mode.raw_value;
+
+	/* For TBT3 Device Enter Mode Command, number of Objects are 2 */
+	return 2;
+}
+
+enum tbt_compat_rounded_support get_tbt_rounded_support(int port)
+{
+	union tbt_mode_resp_cable cable_mode_resp = {
+		.raw_value = pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME)
+	};
+
+	/* tbt_rounded_support is zero when uninitialized */
+	return cable_mode_resp.tbt_rounded;
+}
+
+__overridable enum tbt_compat_cable_speed board_get_max_tbt_speed(int port)
+{
+	return TBT_SS_TBT_GEN3;
 }
diff --git a/common/usbc/usb_mode.c b/common/usbc/usb_mode.c
index fcbb58cd6f..b41a05a520 100644
--- a/common/usbc/usb_mode.c
+++ b/common/usbc/usb_mode.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,23 +9,27 @@
  * USB Power Delivery Specification Revision 3.0, Version 2.0 Section 6.4.8
  */
 
-#include <stdbool.h>
-#include <stdint.h>
 #include "compile_time_macros.h"
 #include "console.h"
-#include "tcpm.h"
+#include "tcpm/tcpm.h"
+#include "typec_control.h"
 #include "usb_common.h"
 #include "usb_mode.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
-#include "usb_pd_dpm.h"
-#include "usb_pd_tbt.h"
+#include "usb_pd_dpm_sm.h"
+#include "usb_pd_tcpm.h"
 #include "usb_pe_sm.h"
+#include "usb_prl_sm.h"
+#include "usb_tbt_alt_mode.h"
 #include "usbc_ppc.h"
 
+#include <stdbool.h>
+#include <stdint.h>
+
 #ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 #else
 #define CPRINTF(format, args...)
 #define CPRINTS(format, args...)
@@ -37,11 +41,73 @@ enum usb4_mode_status {
 };
 
 enum usb4_states {
+	USB4_START,
 	USB4_ENTER_SOP,
+	USB4_ENTER_SOP_PRIME,
+	USB4_ENTER_SOP_PRIME_PRIME,
 	USB4_ACTIVE,
 	USB4_INACTIVE,
 	USB4_STATE_COUNT,
 };
+
+/*
+ * USB4 PD flow:
+ *
+ *                            Cable type
+ *                                 |
+ *            |-------- Passive ---|---- Active -----|
+ *            |                                      |
+ *      USB Highest Speed         Structured VDM version
+ *            |                   (cable revision)-- <2.0---->|
+ *    --------|--------|------|       |                       |
+ *    |       |        |      |       >=2.0                   |
+ *  >=Gen3   Gen2    Gen1  USB2.0     |                       |
+ *    |       |        |      |   VDO version--- <1.3 ---> Modal op? -- N --|
+ * Enter USB  |        |      |   (B21:23 of                  |             |
+ * SOP  with  |        |      |    Discover ID SOP'-          y             |
+ * Gen3 cable |        |    Skip   Active cable VDO1)         |             |
+ * speed      |        |    USB4      |                    TBT SVID? -- N --|
+ *            |        |    mode      >=1.3                   |             |
+ *    Is modal op?     |    entry     |                       y             |
+ *            |        |            Cable USB4  - N           |             |
+ *            y        |            support?      |       Gen4 cable? - N - Skip
+ *            |        |               |      Skip USB4       |             USB4
+ *    Is TBT SVID? -N- Enter           |      mode entry      |             mode
+ *            |       USB4 SOP         |                      |            entry
+ *            y       with Gen2        y                      |
+ *            |       cable speed      |                      |
+ *            |                        |                      |
+ *    Is Discover mode                 |                      |
+ *    SOP' B25? - N - Enter      Enter USB4 mode              |
+ *            |     USB4 SOP     (SOP, SOP', SOP'')           |
+ *            |     with speed                                |
+ *            y     from TBT mode                             |
+ *            |     SOP' VDO                                  |
+ *            |                           |<-- NAK -- Enter mode TBT SOP'<---|
+ * |---->Enter TBT SOP'-------NAK------>| |                   |              |
+ * |          |                         | |                  ACK             |
+ * |         ACK                        | |                   |              |
+ * |          |                         | |<-- NAK -- Enter mode TBT SOP''   |
+ * |     Enter USB4 SOP                 | |                   |              |
+ * |     with speed from         Exit TBT mode SOP           ACK             |
+ * |     TBT mode SOP' VDO              | |                   |              |
+ * |                                  ACK/NAK          Enter USB4 SOP        |
+ * |                                    | |            with speed from       |
+ * |                             Exit TBT mode SOP''   TBT mode SOP' VDO     |
+ * |                                    | |                                  |
+ * |                                  ACK/NAK                                |
+ * |                                    | |                                  |
+ * |                             Exit TBT mode SOP'                          |
+ * |                                    | |                                  |
+ * |                                   ACK/NAK                               |
+ * |                                    | |                                  |
+ * |---- N ----Retry done? -------------| |--------Retry done? ---- N -------|
+ *                  |                                   |
+ *                  y                                   y
+ *                  |                                   |
+ *           Skip USB4 mode entry                 Skip USB4 mode entry
+ */
+
 static enum usb4_states usb4_state[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 static void usb4_debug_prints(int port, enum usb4_mode_status usb4_status)
@@ -50,9 +116,24 @@ static void usb4_debug_prints(int port, enum usb4_mode_status usb4_status)
 		usb4_status);
 }
 
+bool enter_usb_entry_is_done(int port)
+{
+	return usb4_state[port] == USB4_ACTIVE ||
+	       usb4_state[port] == USB4_INACTIVE;
+}
+
+void usb4_exit_mode_request(int port)
+{
+	usb4_state[port] = USB4_START;
+	usb_mux_set_safe_mode_exit(port);
+	/* If TBT mode is active, leave safe state for mode exit VDMs */
+	if (!tbt_is_active(port))
+		set_usb_mux_with_current_data_role(port);
+}
+
 void enter_usb_init(int port)
 {
-	usb4_state[port] = USB4_ENTER_SOP;
+	usb4_state[port] = USB4_START;
 }
 
 void enter_usb_failed(int port)
@@ -62,61 +143,119 @@ void enter_usb_failed(int port)
 	 * to USB mode on receiving a NAK.
 	 */
 	usb_mux_set(port, USB_PD_MUX_USB_ENABLED, USB_SWITCH_CONNECT,
-		    pd_get_polarity(port));
+		    polarity_rm_dts(pd_get_polarity(port)));
 
 	usb4_debug_prints(port, USB4_MODE_FAILURE);
 	usb4_state[port] = USB4_INACTIVE;
 }
 
-static bool enter_usb_response_valid(int port, enum tcpm_transmit_type type)
+static bool enter_usb_response_valid(int port, enum tcpci_msg_type type)
 {
 	/*
 	 * Check for an unexpected response.
 	 */
 	if (get_usb_pd_cable_type(port) == IDH_PTYPE_PCABLE &&
-	     type != TCPC_TX_SOP) {
+	    type != TCPCI_MSG_SOP) {
 		enter_usb_failed(port);
 		return false;
 	}
 	return true;
 }
 
-bool enter_usb_is_capable(int port)
+bool enter_usb_port_partner_is_capable(int port)
 {
 	const struct pd_discovery *disc =
-			pd_get_am_discovery(port, TCPC_TX_SOP);
-	/*
-	 * TODO: b/156749387 Add support for entering the USB4 mode with an
-	 * active cable.
-	 */
-	if (!IS_ENABLED(CONFIG_USB_PD_USB4) ||
-	    !PD_PRODUCT_IS_USB4(disc->identity.product_t1.raw_value) ||
-	    get_usb4_cable_speed(port) < USB_R30_SS_U32_U40_GEN1 ||
-	    usb4_state[port] == USB4_INACTIVE ||
-	    get_usb_pd_cable_type(port) != IDH_PTYPE_PCABLE)
+		pd_get_am_discovery(port, TCPCI_MSG_SOP);
+
+	if (usb4_state[port] == USB4_INACTIVE)
 		return false;
 
+	if (prl_get_rev(port, TCPCI_MSG_SOP) < PD_REV30)
+		return false;
+
+	if (!PD_PRODUCT_IS_USB4(disc->identity.product_t1.raw_value))
+		return false;
+
+	return true;
+}
+
+bool enter_usb_cable_is_capable(int port)
+{
+	if (get_usb_pd_cable_type(port) == IDH_PTYPE_PCABLE) {
+		if (get_usb4_cable_speed(port) < USB_R30_SS_U32_U40_GEN1)
+			return false;
+	} else if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE) {
+		const struct pd_discovery *disc_sop_prime =
+			pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
+
+		if (pd_get_vdo_ver(port, TCPCI_MSG_SOP_PRIME) >= VDM_VER20 &&
+		    disc_sop_prime->identity.product_t1.a_rev30.vdo_ver >=
+			    VDO_VERSION_1_3) {
+			union active_cable_vdo2_rev30 a2_rev30 =
+				disc_sop_prime->identity.product_t2.a2_rev30;
+			/*
+			 * For VDM version >= 2.0 and VD0 version is >= 1.3,
+			 * do not enter USB4 mode if the cable isn't USB4
+			 * capable.
+			 */
+			if (a2_rev30.usb_40_support == USB4_NOT_SUPPORTED)
+				return false;
+			/*
+			 * For VDM version < 2.0 or VDO version < 1.3, do not
+			 * enter USB4 mode if the cable - doesn't support modal
+			 * operation or doesn't support Intel SVID or doesn't
+			 * have rounded support.
+			 */
+		} else {
+			const struct pd_discovery *disc =
+				pd_get_am_discovery(port, TCPCI_MSG_SOP);
+			union tbt_mode_resp_cable cable_mode_resp = {
+				.raw_value = pd_get_tbt_mode_vdo(
+					port, TCPCI_MSG_SOP_PRIME)
+			};
+
+			if (!disc->identity.idh.modal_support ||
+			    !pd_is_mode_discovered_for_svid(
+				    port, TCPCI_MSG_SOP_PRIME, USB_VID_INTEL) ||
+			    cable_mode_resp.tbt_rounded !=
+				    TBT_GEN3_GEN4_ROUNDED_NON_ROUNDED)
+				return false;
+		}
+	} else {
+		/* Not Emark cable */
+		return false;
+	}
+
 	return true;
 }
 
-void enter_usb_accepted(int port, enum tcpm_transmit_type type)
+void enter_usb_accepted(int port, enum tcpci_msg_type type)
 {
+	const struct pd_discovery *disc;
+
 	if (!enter_usb_response_valid(port, type))
 		return;
 
 	switch (usb4_state[port]) {
+	case USB4_ENTER_SOP_PRIME:
+		disc = pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
+		if (disc->identity.product_t1.a_rev20.sop_p_p)
+			usb4_state[port] = USB4_ENTER_SOP_PRIME_PRIME;
+		else
+			usb4_state[port] = USB4_ENTER_SOP;
+		break;
+	case USB4_ENTER_SOP_PRIME_PRIME:
+		usb4_state[port] = USB4_ENTER_SOP;
+		break;
 	case USB4_ENTER_SOP:
 		/* Connect the SBU and USB lines to the connector */
-		if (IS_ENABLED(CONFIG_USBC_PPC_SBU))
-			ppc_set_sbu(port, 1);
-
-		dpm_set_mode_entry_done(port);
+		typec_set_sbu(port, true);
 
 		usb4_state[port] = USB4_ACTIVE;
 
 		/* Set usb mux to USB4 mode */
 		usb_mux_set(port, USB_PD_MUX_USB4_ENABLED, USB_SWITCH_CONNECT,
-			    pd_get_polarity(port));
+			    polarity_rm_dts(pd_get_polarity(port)));
 
 		usb4_debug_prints(port, USB4_MODE_SUCCESS);
 		break;
@@ -127,7 +266,7 @@ void enter_usb_accepted(int port, enum tcpm_transmit_type type)
 	}
 }
 
-void enter_usb_rejected(int port, enum tcpm_transmit_type type)
+void enter_usb_rejected(int port, enum tcpci_msg_type type)
 {
 	if (!enter_usb_response_valid(port, type) ||
 	    usb4_state[port] == USB4_ACTIVE)
@@ -136,24 +275,147 @@ void enter_usb_rejected(int port, enum tcpm_transmit_type type)
 	enter_usb_failed(port);
 }
 
-uint32_t enter_usb_setup_next_msg(int port)
+uint32_t enter_usb_setup_next_msg(int port, enum tcpci_msg_type *type)
 {
+	const struct pd_discovery *disc_sop_prime;
+
 	switch (usb4_state[port]) {
-	case USB4_ENTER_SOP:
+	case USB4_START:
+		disc_sop_prime = pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
 		/*
-		 * Set the USB mux to safe state to avoid damaging the mux pins
-		 * since, they are being re-purposed for USB4.
-		 *
-		 * TODO: b/141363146 Remove once data reset feature is in place
+		 * Ref: Tiger Lake Platform PD Controller Interface Requirements
+		 * for Integrated USBC, section A.2.2: USB4 as DFP.
+		 * Enter safe mode before sending Enter USB SOP/SOP'/SOP''
 		 */
 		usb_mux_set_safe_mode(port);
 
-		usb4_state[port] = USB4_ENTER_SOP;
-		return get_enter_usb_msg_payload(port);
+		if (pd_get_vdo_ver(port, TCPCI_MSG_SOP_PRIME) < VDM_VER20 ||
+		    disc_sop_prime->identity.product_t1.a_rev30.vdo_ver <
+			    VDO_VERSION_1_3 ||
+		    get_usb_pd_cable_type(port) == IDH_PTYPE_PCABLE) {
+			usb4_state[port] = USB4_ENTER_SOP;
+		} else {
+			usb4_state[port] = USB4_ENTER_SOP_PRIME;
+			*type = TCPCI_MSG_SOP_PRIME;
+		}
+		break;
+	case USB4_ENTER_SOP_PRIME:
+		*type = TCPCI_MSG_SOP_PRIME;
+		break;
+	case USB4_ENTER_SOP_PRIME_PRIME:
+		*type = TCPCI_MSG_SOP_PRIME_PRIME;
+		break;
+	case USB4_ENTER_SOP:
+		*type = TCPCI_MSG_SOP;
+		break;
 	case USB4_ACTIVE:
 		return -1;
 	default:
+		return 0;
+	}
+	return get_enter_usb_msg_payload(port);
+}
+
+/*
+ * For Cable rev 3.0: USB4 cable speed is set according to speed supported by
+ * the port and the response received from the cable, whichever is least.
+ *
+ * For Cable rev 2.0: If get_tbt_cable_speed() is less than
+ * TBT_SS_U31_GEN1, return USB_R30_SS_U2_ONLY speed since the board
+ * doesn't support superspeed else the USB4 cable speed is set according to
+ * the cable response.
+ */
+enum usb_rev30_ss get_usb4_cable_speed(int port)
+{
+	enum tbt_compat_cable_speed tbt_speed = get_tbt_cable_speed(port);
+	enum usb_rev30_ss max_usb4_speed;
+
+	if (tbt_speed < TBT_SS_U31_GEN1)
+		return USB_R30_SS_U2_ONLY;
+
+	/*
+	 * Converting Thunderbolt-Compatible board speed to equivalent USB4
+	 * speed.
+	 */
+	max_usb4_speed = tbt_speed == TBT_SS_TBT_GEN3 ? USB_R30_SS_U40_GEN3 :
+							USB_R30_SS_U32_U40_GEN2;
+
+	if ((get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE) &&
+	    pd_get_rev(port, TCPCI_MSG_SOP_PRIME) == PD_REV30) {
+		const struct pd_discovery *disc =
+			pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
+		union active_cable_vdo1_rev30 a_rev30 =
+			disc->identity.product_t1.a_rev30;
+
+		if (a_rev30.vdo_ver >= VDO_VERSION_1_3) {
+			return max_usb4_speed < a_rev30.ss ? max_usb4_speed :
+							     a_rev30.ss;
+		}
+	}
+
+	return max_usb4_speed;
+}
+
+uint32_t get_enter_usb_msg_payload(int port)
+{
+	/*
+	 * Ref: USB Power Delivery Specification Revision 3.0, Version 2.0
+	 * Table 6-47 Enter_USB Data Object
+	 */
+	union enter_usb_data_obj eudo;
+	const struct pd_discovery *disc;
+	union tbt_mode_resp_cable cable_mode_resp;
+
+	if (!IS_ENABLED(CONFIG_USB_PD_USB4))
+		return 0;
+
+	disc = pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
+	eudo.mode = USB_PD_40;
+	eudo.usb4_drd_cap = IS_ENABLED(CONFIG_USB_PD_USB4_DRD);
+	eudo.usb3_drd_cap = IS_ENABLED(CONFIG_USB_PD_USB32_DRD);
+	eudo.cable_speed = get_usb4_cable_speed(port);
+
+	if (disc->identity.idh.product_type == IDH_PTYPE_ACABLE) {
+		if (pd_get_rev(port, TCPCI_MSG_SOP_PRIME) == PD_REV30) {
+			enum retimer_active_element active_element =
+				disc->identity.product_t2.a2_rev30.active_elem;
+			eudo.cable_type = active_element == ACTIVE_RETIMER ?
+						  CABLE_TYPE_ACTIVE_RETIMER :
+						  CABLE_TYPE_ACTIVE_REDRIVER;
+		} else {
+			cable_mode_resp.raw_value =
+				pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME);
+
+			eudo.cable_type = cable_mode_resp.retimer_type ==
+							  USB_RETIMER ?
+						  CABLE_TYPE_ACTIVE_RETIMER :
+						  CABLE_TYPE_ACTIVE_REDRIVER;
+		}
+	} else {
+		cable_mode_resp.raw_value =
+			pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME);
+
+		eudo.cable_type = cable_mode_resp.tbt_active_passive ==
+						  TBT_CABLE_ACTIVE ?
+					  CABLE_TYPE_ACTIVE_REDRIVER :
+					  CABLE_TYPE_PASSIVE;
+	}
+
+	switch (disc->identity.product_t1.p_rev20.vbus_cur) {
+	case USB_VBUS_CUR_3A:
+		eudo.cable_current = USB4_CABLE_CURRENT_3A;
+		break;
+	case USB_VBUS_CUR_5A:
+		eudo.cable_current = USB4_CABLE_CURRENT_5A;
+		break;
+	default:
+		eudo.cable_current = USB4_CABLE_CURRENT_INVALID;
 		break;
 	}
-	return 0;
+	eudo.pcie_supported = IS_ENABLED(CONFIG_USB_PD_PCIE_TUNNELING);
+	eudo.dp_supported = IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP);
+	eudo.tbt_supported = IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE);
+	eudo.host_present = 1;
+
+	return eudo.raw_value;
 }
diff --git a/common/usbc/usb_pd_console.c b/common/usbc/usb_pd_console.c
index e183f0852b..ae6527b601 100644
--- a/common/usbc/usb_pd_console.c
+++ b/common/usbc/usb_pd_console.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,16 +6,23 @@
 #include "common.h"
 #include "console.h"
 #include "usb_common.h"
+#include "usb_pd.h"
+#include "usb_pd_dpm_sm.h"
+#include "usb_pd_timer.h"
 #include "usb_pe_sm.h"
 #include "usb_prl_sm.h"
 #include "usb_tc_sm.h"
-#include "usb_pd.h"
 #include "util.h"
 
-test_export_static int command_pd(int argc, char **argv)
+#ifndef TEST_USB_PD_CONSOLE
+static
+#endif
+	int
+	command_pd(int argc, const char **argv)
 {
 	int port;
 	char *e;
+	int rv = EC_SUCCESS;
 
 	if (argc < 2)
 		return EC_ERROR_PARAM_COUNT;
@@ -32,6 +39,7 @@ test_export_static int command_pd(int argc, char **argv)
 			else if (level > DEBUG_LEVEL_MAX)
 				level = DEBUG_LEVEL_MAX;
 
+			dpm_set_debug_level(level);
 			prl_set_debug_level(level);
 			pe_set_debug_level(level);
 			tc_set_debug_level(level);
@@ -39,7 +47,7 @@ test_export_static int command_pd(int argc, char **argv)
 			return EC_SUCCESS;
 		}
 	} else if (IS_ENABLED(CONFIG_USB_PD_TRY_SRC) &&
-				!strcasecmp(argv[1], "trysrc")) {
+		   !strcasecmp(argv[1], "trysrc")) {
 		enum try_src_override_t ov = tc_get_try_src_override();
 
 		if (argc >= 3) {
@@ -58,6 +66,14 @@ test_export_static int command_pd(int argc, char **argv)
 	} else if (!strcasecmp(argv[1], "version")) {
 		ccprintf("%d\n", PD_STACK_VERSION);
 		return EC_SUCCESS;
+	} else if (!strcasecmp(argv[1], "bistsharemode")) {
+		if (!strcasecmp(argv[2], "disable"))
+			rv = pd_set_bist_share_mode(0);
+		else if (!strcasecmp(argv[2], "enable"))
+			rv = pd_set_bist_share_mode(1);
+		else
+			rv = EC_ERROR_PARAM2;
+		return rv;
 	}
 
 	/* command: pd <port> <subcmd> [args] */
@@ -107,12 +123,13 @@ test_export_static int command_pd(int argc, char **argv)
 			else if (!strcasecmp(argv[3], "data"))
 				pd_dpm_request(port, DPM_REQUEST_DR_SWAP);
 			else if (IS_ENABLED(CONFIG_USBC_VCONN_SWAP) &&
-					!strcasecmp(argv[3], "vconn"))
+				 !strcasecmp(argv[3], "vconn"))
 				pd_dpm_request(port, DPM_REQUEST_VCONN_SWAP);
 			else
 				return EC_ERROR_PARAM3;
 		} else if (!strcasecmp(argv[2], "dualrole")) {
 			if (argc < 4) {
+				cflush();
 				ccprintf("dual-role toggling: ");
 				switch (pd_get_dual_role(port)) {
 				case PD_DRP_TOGGLE_ON:
@@ -131,65 +148,125 @@ test_export_static int command_pd(int argc, char **argv)
 					ccprintf("force source\n");
 					break;
 				}
+				cflush();
 			} else {
 				if (!strcasecmp(argv[3], "on"))
 					pd_set_dual_role(port,
-							PD_DRP_TOGGLE_ON);
+							 PD_DRP_TOGGLE_ON);
 				else if (!strcasecmp(argv[3], "off"))
 					pd_set_dual_role(port,
-							PD_DRP_TOGGLE_OFF);
+							 PD_DRP_TOGGLE_OFF);
 				else if (!strcasecmp(argv[3], "freeze"))
 					pd_set_dual_role(port, PD_DRP_FREEZE);
 				else if (!strcasecmp(argv[3], "sink"))
 					pd_set_dual_role(port,
-							PD_DRP_FORCE_SINK);
+							 PD_DRP_FORCE_SINK);
 				else if (!strcasecmp(argv[3], "source"))
 					pd_set_dual_role(port,
-							PD_DRP_FORCE_SOURCE);
+							 PD_DRP_FORCE_SOURCE);
 				else
 					return EC_ERROR_PARAM4;
 			}
 			return EC_SUCCESS;
+		} else if (!strcasecmp(argv[2], "suspend")) {
+			pd_comm_enable(port, 0);
+			pd_set_suspend(port, 1);
+		} else if (!strcasecmp(argv[2], "resume")) {
+			pd_comm_enable(port, 1);
+			pd_set_suspend(port, 0);
 		}
 	}
 
 	if (!strcasecmp(argv[2], "state")) {
-		ccprintf("Port C%d CC%d, %s - Role: %s-%s",
-		port, pd_get_polarity(port) + 1,
-		pd_comm_is_enabled(port) ? "Enable" : "Disable",
-		pd_get_power_role(port) ==
-					PD_ROLE_SOURCE ? "SRC" : "SNK",
-		pd_get_data_role(port) == PD_ROLE_DFP ? "DFP" : "UFP");
+		cflush();
+		ccprintf("Port C%d CC%d, %s - Role: %s-%s", port,
+			 pd_get_polarity(port) + 1,
+			 pd_comm_is_enabled(port) ? "Enable" : "Disable",
+			 pd_get_power_role(port) == PD_ROLE_SOURCE ? "SRC" :
+								     "SNK",
+			 pd_get_data_role(port) == PD_ROLE_DFP ? "DFP" : "UFP");
 
 		if (IS_ENABLED(CONFIG_USBC_VCONN))
 			ccprintf("%s ", tc_is_vconn_src(port) ? "-VC" : "");
 
 		ccprintf("TC State: %s, Flags: 0x%04x",
-			tc_get_current_state(port),
-			tc_get_flags(port));
+			 tc_get_current_state(port), tc_get_flags(port));
 
-		if (IS_ENABLED(CONFIG_USB_PE_SM))
-			ccprintf(" PE State: %s, Flags: 0x%04x\n",
-				pe_get_current_state(port),
-				pe_get_flags(port));
-		else
-			ccprintf("\n");
+		if (IS_ENABLED(CONFIG_USB_PE_SM)) {
+			ccprintf(" PE State: %s, Flags: 0x%04x",
+				 pe_get_current_state(port),
+				 pe_get_flags(port));
+			if (pe_is_explicit_contract(port)) {
+				if (pe_snk_in_epr_mode(port))
+					ccprintf(" EPR");
+				else
+					ccprintf(" SPR");
+			}
+		}
+		ccprintf("\n");
+
+		cflush();
+	} else if (!strcasecmp(argv[2], "srccaps")) {
+		pd_srccaps_dump(port);
+	} else if (!strcasecmp(argv[2], "cc")) {
+		ccprintf("Port C%d CC%d\n", port, pd_get_task_cc_state(port));
+#ifdef CONFIG_USB_PD_EPR
+	} else if (!strcasecmp(argv[2], "epr")) {
+		enum pd_dpm_request req;
+
+		if (argc < 4) {
+			return EC_ERROR_PARAM_COUNT;
+		}
+		if (pd_get_power_role(port) != PD_ROLE_SINK) {
+			ccprintf("EPR is currently supported only for sink\n");
+			/* Suppress (long) help message */
+			return EC_SUCCESS;
+		}
+		if (!strcasecmp(argv[3], "enter")) {
+			req = DPM_REQUEST_EPR_MODE_ENTRY;
+		} else if (!strcasecmp(argv[3], "exit")) {
+			req = DPM_REQUEST_EPR_MODE_EXIT;
+			/* Prevent snk_ready from repeatedly entering EPR. */
+			pe_snk_epr_explicit_exit(port);
+		} else {
+			return EC_ERROR_PARAM3;
+		}
+		pd_dpm_request(port, req);
+		ccprintf("EPR %s requested\n", argv[3]);
+		return EC_SUCCESS;
+#endif
+	}
+
+	if (IS_ENABLED(CONFIG_CMD_PD_TIMER) && !strcasecmp(argv[2], "timer")) {
+		pd_timer_dump(port);
 	}
 
 	return EC_SUCCESS;
 }
+#ifndef TEST_USB_PD_CONSOLE
 DECLARE_CONSOLE_COMMAND(pd, command_pd,
-	 "version"
-	 "\ndump [0|1|2|3]"
+			"version"
+			"\ndump [0|1|2|3]"
 #ifdef CONFIG_USB_PD_TRY_SRC
-	"\ntrysrc [0|1|2]"
+			"\ntrysrc [0|1|2]"
 #endif
-	"\n\t<port> state"
+			"\nbistsharemode [disable|enable]"
+			"\n\t<port> state"
+			"\n\t<port> srccaps"
+			"\n\t<port> cc"
+#ifdef CONFIG_CMD_PD_TIMER
+			"\n\t<port> timer"
+#endif /* CONFIG_CMD_PD_TIMER */
 #ifdef CONFIG_USB_PD_DUAL_ROLE
-	"|tx|charger|dev"
-	"\n\t<port> disable|enable|soft|hard"
-	"\n\t<port> dualrole [on|off|freeze|sink|source]"
-	"\n\t<port> swap [power|data|vconn]"
+			"|tx|charger|dev"
+			"\n\t<port> disable|enable|soft|hard"
+			"\n\t<port> suspend|resume"
+			"\n\t<port> dualrole [on|off|freeze|sink|source]"
+			"\n\t<port> swap [power|data|vconn]"
+#ifdef CONFIG_USB_PD_EPR
+			"\n\t<port> epr [enter|exit]"
+#endif
 #endif /* CONFIG_USB_PD_DUAL_ROLE */
-	,
-	"USB PD");
+			,
+			"USB PD");
+#endif
diff --git a/common/usbc/usb_pd_dp_ufp.c b/common/usbc/usb_pd_dp_ufp.c
new file mode 100644
index 0000000000..1d375c5e2b
--- /dev/null
+++ b/common/usbc/usb_pd_dp_ufp.c
@@ -0,0 +1,446 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Functions required for UFP_D operation
+ */
+
+#include "console.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "system.h"
+#include "task.h"
+#include "usb_pd.h"
+#include "usb_pd_dp_ufp.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+enum hpd_state {
+	LOW_WAIT,
+	HIGH_CHECK,
+	HIGH_WAIT,
+	LOW_CHECK,
+	IRQ_CHECK,
+};
+
+#define EDGE_QUEUE_DEPTH BIT(3)
+#define EDGE_QUEUE_MASK (EDGE_QUEUE_DEPTH - 1)
+#define HPD_QUEUE_DEPTH BIT(2)
+#define HPD_QUEUE_MASK (HPD_QUEUE_DEPTH - 1)
+#define HPD_T_IRQ_MIN_PULSE 250
+#define HPD_T_IRQ_MAX_PULSE (2 * MSEC)
+#define HPD_T_MIN_DP_ATTEN (10 * MSEC)
+
+struct hpd_mark {
+	int level;
+	uint64_t ts;
+};
+
+struct hpd_edge {
+	int overflow;
+	uint32_t head;
+	uint32_t tail;
+	struct hpd_mark buffer[EDGE_QUEUE_DEPTH];
+};
+
+struct hpd_info {
+	enum hpd_state state;
+	int count;
+	int send_enable;
+	uint64_t timer;
+	uint64_t last_send_ts;
+	enum hpd_event queue[HPD_QUEUE_DEPTH];
+	struct hpd_edge edges;
+};
+
+static struct hpd_info hpd;
+static struct mutex hpd_mutex;
+
+static int alt_dp_mode_opos[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+void pd_ufp_set_dp_opos(int port, int opos)
+{
+	alt_dp_mode_opos[port] = opos;
+}
+
+int pd_ufp_get_dp_opos(int port)
+{
+	return alt_dp_mode_opos[port];
+}
+
+void pd_ufp_enable_hpd_send(int port)
+{
+	/*
+	 * This control is used ensure that a DP_ATTENTION message is not sent
+	 * to the DFP-D before a DP_CONFIG messaage has been received. This
+	 * control is not strictly required by the spec, but some port partners
+	 * will get confused if DP_ATTENTION is sent prior to DP_CONFIG.
+	 */
+	hpd.send_enable = 1;
+}
+
+static void hpd_to_dp_attention(void)
+{
+	int port = hpd_config.port;
+	int evt_index = hpd.count - 1;
+	uint32_t vdm[2];
+	uint32_t svdm_header;
+	enum hpd_event evt;
+	int opos = pd_ufp_get_dp_opos(port);
+
+	if (!opos)
+		return;
+
+	/* Get the next hpd event from the queue */
+	evt = hpd.queue[evt_index];
+	/* Save timestamp of when most recent DP attention message was sent */
+	hpd.last_send_ts = get_time().val;
+
+	/*
+	 * Construct DP Attention message. This consists of the VDM header and
+	 * the DP_STATUS VDO.
+	 */
+	svdm_header = VDO_SVDM_VERS(pd_get_vdo_ver(port, TCPCI_MSG_SOP)) |
+		      VDO_OPOS(opos) | CMD_ATTENTION;
+	vdm[0] = VDO(USB_SID_DISPLAYPORT, 1, svdm_header);
+
+	vdm[1] = VDO_DP_STATUS((evt == hpd_irq), /* IRQ_HPD */
+			       (evt != hpd_low), /* HPD_HI|LOW */
+			       0, /* request exit DP */
+			       0, /* request exit USB */
+			       dock_get_mf_preference(), /* MF pref */
+			       1, /* enabled */
+			       0, /* power low */
+			       0x2);
+
+	/* Send request to DPM to send an attention VDM */
+	pd_request_vdm(port, vdm, ARRAY_SIZE(vdm), TCPCI_MSG_SOP);
+
+	/* If there are still events, need to shift the buffer */
+	if (--hpd.count) {
+		int i;
+
+		for (i = 0; i < hpd.count; i++)
+			hpd.queue[i] = hpd.queue[i + 1];
+	}
+}
+
+static void hpd_queue_event(enum hpd_event evt)
+{
+	/*
+	 * HPD events are put into a queue. However, this queue is not a typical
+	 * FIFO queue. Instead there are special rules based on which type of
+	 * event is being added.
+	 *     HPD_LOW -> always resets the queue and must be in slot 0
+	 *     HPD_HIGH -> must follow a HPD_LOW, so can only be in slot 0 or
+	 *                 slot 1.
+	 *     HPD_IRQ  -> There shall never be more than 2 HPD_IRQ events
+	 *                 stored in the queue and HPD_IRQ must follow HPD_HIGH
+	 *
+	 * Worst case for queueing HPD events is 4 events in the queue:
+	 *    0 - HPD_LOW
+	 *    1 - HPD_HIGH
+	 *    2 - HPD_IRQ
+	 *    3 - HPD_IRQ
+	 *
+	 * The above rules mean that HPD_LOW and HPD_HIGH events can always be
+	 * added to the queue since high must follow low and a low event resets
+	 * the queue. HPD_IRQ events are checked to make sure that they don't
+	 * overflow the queue and to ensure that no more than 2 hpd_irq events
+	 * are kept in the queue.
+	 */
+	if (evt == hpd_irq) {
+		if ((hpd.count >= HPD_QUEUE_DEPTH) ||
+		    ((hpd.count >= 2) &&
+		     (hpd.queue[hpd.count - 2] == hpd_irq))) {
+			CPRINTS("hpd: discard hpd: count - %d", hpd.count);
+			return;
+		}
+	}
+
+	if (evt == hpd_low) {
+		hpd.count = 0;
+	}
+
+	/* Add event to the queue */
+	hpd.queue[hpd.count++] = evt;
+}
+
+static void hpd_to_pd_converter(int level, uint64_t ts)
+{
+	/*
+	 * HPD edges are marked in the irq routine. The converter state machine
+	 * runs in the hooks task and so there will be some delay between when
+	 * the edge was captured and when that edge is processed here in the
+	 * state machine. This means that the delitch timer (250 uSec) may have
+	 * already expired or is about to expire.
+	 *
+	 * If transitioning to timing dependent state, need to ensure the state
+	 * machine is executed again. All timers are relative to the ts value
+	 * passed into this routine. The timestamps passed into this routine
+	 * are either the values latched in the irq routine, or the current
+	 * time latched by the calling function. From the perspective of the
+	 * state machine, ts represents the current time.
+	 *
+	 * Note that all hpd queue events are contingent on detecting edges
+	 * on the incoming hpd gpio signal. The hpd->dp attention converter is
+	 * enabled/disabled as part of the svdm dp enter/exit response handler
+	 * functions. When the converter is disabled, gpio interrupts for the
+	 * hpd gpio signal are disabled so it will never execute, unless the
+	 * converter is enabled, and the converter is only enabled when the
+	 * UFP-D is actively in ALT-DP mode.
+	 */
+	switch (hpd.state) {
+	case LOW_WAIT:
+		/*
+		 * In this state only expected event is a level change from low
+		 * to high.
+		 */
+		if (level) {
+			hpd.state = HIGH_CHECK;
+			hpd.timer = ts + HPD_T_IRQ_MIN_PULSE;
+		}
+		break;
+	case HIGH_CHECK:
+		/*
+		 * In this state if level is high and deglitch timer is
+		 * exceeded, then state advances to HIGH_WAIT, otherwise return
+		 * to LOW_WAIT state.
+		 */
+		if (!level || (ts <= hpd.timer)) {
+			hpd.state = LOW_WAIT;
+		} else {
+			hpd.state = HIGH_WAIT;
+			hpd_queue_event(hpd_high);
+		}
+		break;
+	case HIGH_WAIT:
+		/*
+		 * In this state, only expected event is a level change from
+		 * high to low. If current level is low, then advance to
+		 * LOW_CHECK for deglitch checking.
+		 */
+		if (!level) {
+			hpd.state = LOW_CHECK;
+			hpd.timer = ts + HPD_T_IRQ_MIN_PULSE;
+		}
+		break;
+	case LOW_CHECK:
+		/*
+		 * This state is used to deglitch high->low level
+		 * change. However, due to processing latency, it's possible to
+		 * detect hpd_irq event if level is high and low pulse width was
+		 * valid.
+		 */
+		if (!level) {
+			/* Still low, now wait for IRQ or LOW determination */
+			hpd.timer = ts +
+				    (HPD_T_IRQ_MAX_PULSE - HPD_T_IRQ_MIN_PULSE);
+			hpd.state = IRQ_CHECK;
+
+		} else {
+			uint64_t irq_ts = hpd.timer + HPD_T_IRQ_MAX_PULSE -
+					  HPD_T_IRQ_MIN_PULSE;
+			/*
+			 * If hpd is high now, this must have been an edge
+			 * event, but still need to determine if the pulse width
+			 * is longer than hpd_irq min pulse width. State will
+			 * advance to HIGH_WAIT, but if pulse width is < 2 msec,
+			 * must send hpd_irq event.
+			 */
+			if ((ts >= hpd.timer) && (ts <= irq_ts)) {
+				/* hpd irq detected */
+				hpd_queue_event(hpd_irq);
+			}
+			hpd.state = HIGH_WAIT;
+		}
+		break;
+	case IRQ_CHECK:
+		/*
+		 * In this state deglitch time has already passed. If current
+		 * level is low and hpd_irq timer has expired, then go to
+		 * LOW_WAIT as hpd_low event has been detected. If level is high
+		 * and low pulse is < hpd_irq, hpd_irq event has been detected.
+		 */
+		if (level) {
+			hpd.state = HIGH_WAIT;
+			if (ts <= hpd.timer) {
+				hpd_queue_event(hpd_irq);
+			}
+		} else if (ts > hpd.timer) {
+			hpd.state = LOW_WAIT;
+			hpd_queue_event(hpd_low);
+		}
+		break;
+	}
+}
+
+static void manage_hpd(void);
+DECLARE_DEFERRED(manage_hpd);
+
+static void manage_hpd(void)
+{
+	int level;
+	uint64_t ts = get_time().val;
+	uint32_t num_hpd_events = (hpd.edges.head - hpd.edges.tail) &
+				  EDGE_QUEUE_MASK;
+
+	/*
+	 * HPD edges are detected via GPIO interrupts. The ISR routine adds edge
+	 * info to a queue and scheudles this routine. If this routine is called
+	 * without a new edge detected, then it is being called due to a timer
+	 * event.
+	 */
+
+	/* First check to see overflow condition has occurred */
+	if (hpd.edges.overflow) {
+		/* Disable hpd interrupts */
+		usb_pd_hpd_converter_enable(0);
+		/* Re-enable hpd converter */
+		usb_pd_hpd_converter_enable(1);
+	}
+
+	if (num_hpd_events) {
+		while (num_hpd_events-- > 0) {
+			int idx = hpd.edges.tail;
+
+			level = hpd.edges.buffer[idx].level;
+			ts = hpd.edges.buffer[idx].ts;
+
+			hpd_to_pd_converter(level, ts);
+			hpd.edges.tail = (hpd.edges.tail + 1) & EDGE_QUEUE_MASK;
+		}
+	} else {
+		/* no new edge event, so get current time and level */
+		level = gpio_get_level(hpd_config.signal);
+		ts = get_time().val;
+		hpd_to_pd_converter(level, ts);
+	}
+
+	/*
+	 * If min time spacing requirement is exceeded and a hpd_event is
+	 * queued, then send DP_ATTENTION message.
+	 */
+	if (hpd.count > 0) {
+		/*
+		 * If at least one hpd event is pending in the queue, send
+		 * a DP_ATTENTION message if a DP_CONFIG message has been
+		 * received and have passed the minimum spacing interval.
+		 */
+		if (hpd.send_enable && ((get_time().val - hpd.last_send_ts) >
+					HPD_T_MIN_DP_ATTEN)) {
+			/* Generate DP_ATTENTION event pending in queue */
+			hpd_to_dp_attention();
+		} else {
+			uint32_t callback_us;
+
+			/*
+			 * Need to wait until until min spacing requirement of
+			 * DP attention messages. Set callback time to the min
+			 * value required. This callback time could be changed
+			 * based on hpd interrupts.
+			 *
+			 * This wait is also used to prevent a DP_ATTENTION
+			 * message from being sent before at least one DP_CONFIG
+			 * message has been received. If DP_ATTENTION messages
+			 * need to be delayed for this reason, then just wait
+			 * the minimum time spacing.
+			 */
+			callback_us = HPD_T_MIN_DP_ATTEN -
+				      (get_time().val - hpd.last_send_ts);
+			if (callback_us <= 0 ||
+			    callback_us > HPD_T_MIN_DP_ATTEN)
+				callback_us = HPD_T_MIN_DP_ATTEN;
+			hook_call_deferred(&manage_hpd_data, callback_us);
+		}
+	}
+
+	/*
+	 * Because of the delay between gpio edge irq, and when those edge
+	 * events are processed here, all timers must be done relative to the
+	 * timing marker stored in the hpd edge queue. If the state machine
+	 * required a new timer, then hpd.timer will be advanced relative to the
+	 * ts that was passed into the state machine.
+	 *
+	 * If the deglitch timer is active, then it can likely already have been
+	 * expired when the edge gets processed. So if the timer is active the
+	 * deferred callback must be requested.
+	 *.
+	 */
+	if (hpd.timer > ts) {
+		uint64_t callback_us = 0;
+		uint64_t now = get_time().val;
+
+		/* If timer is in the future, adjust the callback timer */
+		if (now < hpd.timer)
+			callback_us = (hpd.timer - now) & 0xffffffff;
+
+		hook_call_deferred(&manage_hpd_data, callback_us);
+	}
+}
+
+void usb_pd_hpd_converter_enable(int enable)
+{
+	/*
+	 * The hpd converter should be enabled as part of the UFP-D enter mode
+	 * response function. Likewise, the converter should be disabled by the
+	 * exit mode function. In addition, the coverter may get disabled so
+	 * that it can be reset in the case that the input gpio edges queue
+	 * overflows. A muxtex must be used here since this function may be
+	 * called from the PD task (enter/exit response mode functions) or from
+	 * the hpd event handler state machine (hook task).
+	 */
+	mutex_lock(&hpd_mutex);
+
+	if (enable) {
+		gpio_disable_interrupt(hpd_config.signal);
+		/* Reset HPD event queue */
+		hpd.state = LOW_WAIT;
+		hpd.count = 0;
+		hpd.timer = 0;
+		hpd.last_send_ts = 0;
+		hpd.send_enable = 0;
+
+		/* Reset hpd signal edges queue */
+		hpd.edges.head = 0;
+		hpd.edges.tail = 0;
+		hpd.edges.overflow = 0;
+
+		/* If signal is high, need to ensure state machine executes */
+		if (gpio_get_level(hpd_config.signal))
+			hook_call_deferred(&manage_hpd_data, 0);
+
+		/* Enable hpd edge detection */
+		gpio_enable_interrupt(hpd_config.signal);
+	} else {
+		gpio_disable_interrupt(hpd_config.signal);
+		hook_call_deferred(&manage_hpd_data, -1);
+	}
+
+	mutex_unlock(&hpd_mutex);
+}
+
+void usb_pd_hpd_edge_event(int signal)
+{
+	int next_head = (hpd.edges.head + 1) & EDGE_QUEUE_MASK;
+	struct hpd_mark mark;
+
+	/* Get current timestamp and level */
+	mark.ts = get_time().val;
+	mark.level = gpio_get_level(hpd_config.signal);
+
+	/* Add this edge to the buffer if there is space */
+	if (next_head != hpd.edges.tail) {
+		hpd.edges.buffer[hpd.edges.head].ts = mark.ts;
+		hpd.edges.buffer[hpd.edges.head].level = mark.level;
+		hpd.edges.head = next_head;
+	} else {
+		/* Edge queue is overflowing, need to reset the converter */
+		hpd.edges.overflow = 1;
+	}
+	/* Schedule HPD state machine to run ASAP */
+	hook_call_deferred(&manage_hpd_data, 0);
+}
diff --git a/common/usbc/usb_pd_dpm.c b/common/usbc/usb_pd_dpm.c
index e9c7782512..022d81109b 100644
--- a/common/usbc/usb_pd_dpm.c
+++ b/common/usbc/usb_pd_dpm.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,103 +8,1176 @@
  * Refer to USB PD 3.0 spec, version 2.0, sections 8.2 and 8.3
  */
 
+#include "builtin/assert.h"
 #include "charge_state.h"
+#include "chipset.h"
 #include "compile_time_macros.h"
 #include "console.h"
+#include "ec_commands.h"
+#include "hooks.h"
+#include "power.h"
+#include "power_button.h"
+#include "queue.h"
+#include "system.h"
+#include "task.h"
+#include "tcpm/tcpm.h"
+#include "temp_sensor.h"
 #include "usb_dp_alt_mode.h"
 #include "usb_mode.h"
+#include "usb_mux.h"
 #include "usb_pd.h"
-#include "usb_pd_dpm.h"
+#include "usb_pd_ap_vdm_control.h"
+#include "usb_pd_dpm_sm.h"
+#include "usb_pd_pdo.h"
+#include "usb_pd_tcpm.h"
+#include "usb_pd_timer.h"
+#include "usb_pe_sm.h"
 #include "usb_tbt_alt_mode.h"
-#include "tcpm.h"
+#include "usb_tc_sm.h"
+
+/*
+ * TODO(b/272518464): Work around coreboot GCC preprocessor bug.
+ * #line marks the *next* line, so it is off by one.
+ */
+#line 43
+
+#ifdef CONFIG_ZEPHYR
+#include "temp_sensor/temp_sensor.h"
+#endif
+
+#ifdef CONFIG_USB_PD_DEBUG_LEVEL
+static const enum debug_level dpm_debug_level = CONFIG_USB_PD_DEBUG_LEVEL;
+#elif defined(CONFIG_USB_PD_INITIAL_DEBUG_LEVEL)
+static enum debug_level dpm_debug_level = CONFIG_USB_PD_INITIAL_DEBUG_LEVEL;
+#else
+static enum debug_level dpm_debug_level = DEBUG_LEVEL_1;
+#endif
 
 #ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 #else
 #define CPRINTF(format, args...)
 #define CPRINTS(format, args...)
 #endif
 
 static struct {
-	bool mode_entry_done;
-	bool mode_exit_request;
+	/* state machine context */
+	struct sm_ctx ctx;
+	atomic_t flags;
+	uint32_t vdm_req[VDO_MAX_SIZE];
+	int vdm_req_cnt;
+	enum tcpci_msg_type req_type;
+	mutex_t vdm_req_mutex;
+	enum dpm_pd_button_state pd_button_state;
 } dpm[CONFIG_USB_PD_PORT_MAX_COUNT];
 
+__overridable const struct svdm_response svdm_rsp = {
+	.identity = NULL,
+	.svids = NULL,
+	.modes = NULL,
+};
+
+/* Tracker for which task is waiting on sysjump prep to finish */
+static volatile task_id_t sysjump_task_waiting = TASK_ID_INVALID;
+
+#define DPM_SET_FLAG(port, flag) atomic_or(&dpm[(port)].flags, (flag))
+#define DPM_CLR_FLAG(port, flag) atomic_clear_bits(&dpm[(port)].flags, (flag))
+#define DPM_CHK_FLAG(port, flag) (dpm[(port)].flags & (flag))
+
+/* Flags for internal DPM state */
+#define DPM_FLAG_MODE_ENTRY_DONE BIT(0)
+#define DPM_FLAG_EXIT_REQUEST BIT(1)
+#define DPM_FLAG_ENTER_DP BIT(2)
+#define DPM_FLAG_ENTER_TBT BIT(3)
+#define DPM_FLAG_ENTER_USB4 BIT(4)
+#define DPM_FLAG_ENTER_ANY \
+	(DPM_FLAG_ENTER_DP | DPM_FLAG_ENTER_TBT | DPM_FLAG_ENTER_USB4)
+#define DPM_FLAG_SEND_VDM_REQ BIT(5)
+#define DPM_FLAG_DATA_RESET_DONE BIT(6)
+#define DPM_FLAG_PD_BUTTON_PRESSED BIT(7)
+#define DPM_FLAG_PD_BUTTON_RELEASED BIT(8)
+#define DPM_FLAG_PE_READY BIT(9)
+
+/* List of all Device Policy Manager level states */
+enum usb_dpm_state {
+	/* Normal States */
+	DPM_WAITING,
+	DPM_DFP_READY,
+	DPM_UFP_READY,
+	DPM_DATA_RESET,
+};
+
+/* Forward declare the full list of states. This is indexed by usb_pd_state */
+static const struct usb_state dpm_states[];
+
+/* List of human readable state names for console debugging */
+__maybe_unused static __const_data const char *const dpm_state_names[] = {
+	/* Normal States */
+	[DPM_WAITING] = "DPM Waiting",
+	[DPM_DFP_READY] = "DPM DFP Ready",
+	[DPM_UFP_READY] = "DPM UFP Ready",
+	[DPM_DATA_RESET] = "DPM Data Reset",
+};
+
+static enum sm_local_state local_state[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+void dpm_set_debug_level(enum debug_level debug_level)
+{
+#ifndef CONFIG_USB_PD_DEBUG_LEVEL
+	dpm_debug_level = debug_level;
+#endif
+}
+
+/* Set the DPM state machine to a new state. */
+static void set_state_dpm(const int port, const enum usb_dpm_state new_state)
+{
+	set_state(port, &dpm[port].ctx, &dpm_states[new_state]);
+}
+
+/* Get the current TypeC state. */
+__maybe_unused test_export_static enum usb_dpm_state
+get_state_dpm(const int port)
+{
+	return dpm[port].ctx.current - &dpm_states[0];
+}
+
+static void print_current_state(const int port)
+{
+	CPRINTS("C%d: %s", port, dpm_state_names[get_state_dpm(port)]);
+}
+
+#ifdef CONFIG_ZEPHYR
+static int init_dpm_mutexes(void)
+{
+	int port;
+
+	for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++) {
+		k_mutex_init(&dpm[port].vdm_req_mutex);
+	}
+
+	return 0;
+}
+SYS_INIT(init_dpm_mutexes, POST_KERNEL, 50);
+#endif /* CONFIG_ZEPHYR */
+
+void pd_prepare_sysjump(void)
+{
+#ifndef CONFIG_ZEPHYR
+	int i;
+
+	/* Exit modes before sysjump so we can cleanly enter again later */
+	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+		/*
+		 * If the port is not capable of alternate mode, then there's no
+		 * need to send the event.
+		 */
+		if (!pd_alt_mode_capable(i))
+			continue;
+
+		sysjump_task_waiting = task_get_current();
+		task_set_event(PD_PORT_TO_TASK_ID(i), PD_EVENT_SYSJUMP);
+		task_wait_event_mask(TASK_EVENT_SYSJUMP_READY, -1);
+		sysjump_task_waiting = TASK_ID_INVALID;
+	}
+#endif /* CONFIG_ZEPHYR */
+}
+
+void notify_sysjump_ready(void)
+{
+	/*
+	 * If event was set from pd_prepare_sysjump, wake the
+	 * task waiting on us to complete.
+	 */
+	if (sysjump_task_waiting != TASK_ID_INVALID)
+		task_set_event(sysjump_task_waiting, TASK_EVENT_SYSJUMP_READY);
+}
+
+/*
+ * TODO(b/270409939): Refactor this function
+ */
+int pd_dfp_exit_mode(int port, enum tcpci_msg_type type, uint16_t svid,
+		     int opos)
+{
+	/*
+	 * Empty svid signals we should reset DFP VDM state by exiting all
+	 * entered modes then clearing state.  This occurs when we've
+	 * disconnected or for hard reset.
+	 */
+	if (!svid) {
+		if (IS_ENABLED(CONFIG_USB_PD_DP_MODE) && dp_is_active(port))
+			svdm_exit_dp_mode(port);
+		pd_dfp_mode_init(port);
+	}
+
+	/*
+	 * Return 0 indicating no message is needed.  All modules should be
+	 * handling their SVID-specific cases themselves.
+	 */
+	return 0;
+}
+
+/*
+ * Note: this interface is used in board code, but should be obsoleted
+ * TODO(b/267545470): Fold board DP code into the DP module
+ */
+int pd_alt_mode(int port, enum tcpci_msg_type type, uint16_t svid)
+{
+	if (svid == USB_SID_DISPLAYPORT && !dp_is_idle(port))
+		return 1;
+	else if (IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE) &&
+		 svid == USB_VID_INTEL && tbt_is_active(port))
+		return 1;
+
+	return -1;
+}
+
+void dfp_consume_attention(int port, uint32_t *payload)
+{
+	uint16_t svid = PD_VDO_VID(payload[0]);
+
+	if (IS_ENABLED(CONFIG_USB_PD_DP_MODE) && svid == USB_SID_DISPLAYPORT) {
+		/*
+		 * Attention is only valid after EnterMode, so drop if this is
+		 * out of sequence
+		 */
+		if (!dp_is_idle(port))
+			svdm_dp_attention(port, payload);
+	}
+}
+
+__overridable bool board_is_tbt_usb4_port(int port)
+{
+	return true;
+}
+
+enum ec_status pd_request_vdm(int port, const uint32_t *data, int vdo_count,
+			      enum tcpci_msg_type tx_type)
+{
+	mutex_lock(&dpm[port].vdm_req_mutex);
+
+	/* Only one VDM REQ message may be pending */
+	if (DPM_CHK_FLAG(port, DPM_FLAG_SEND_VDM_REQ)) {
+		mutex_unlock(&dpm[port].vdm_req_mutex);
+		return EC_RES_BUSY;
+	}
+
+	/* VDM header is required and we cannot exceed standard message size*/
+	if (!vdo_count || vdo_count > VDO_MAX_SIZE) {
+		mutex_unlock(&dpm[port].vdm_req_mutex);
+		return EC_RES_INVALID_PARAM;
+	}
+
+	/* SVDM Attention message must be 1 or 2 VDOs in length */
+	if (PD_VDO_SVDM(data[0]) && (PD_VDO_CMD(data[0]) == CMD_ATTENTION) &&
+	    vdo_count > PD_ATTENTION_MAX_VDO) {
+		mutex_unlock(&dpm[port].vdm_req_mutex);
+		return EC_RES_INVALID_PARAM;
+	}
+
+	/* Save contents of VDM REQ message */
+	memcpy(dpm[port].vdm_req, data, vdo_count * sizeof(uint32_t));
+	dpm[port].vdm_req_cnt = vdo_count;
+	dpm[port].req_type = tx_type;
+
+	/*
+	 * Indicate to DPM that a REQ message needs to be sent. This flag
+	 * will be cleared when the REQ message is sent to the policy
+	 * engine (VDM:Attention), or when the reply is received (all others).
+	 */
+	DPM_SET_FLAG(port, DPM_FLAG_SEND_VDM_REQ);
+
+	mutex_unlock(&dpm[port].vdm_req_mutex);
+
+	return EC_RES_SUCCESS;
+}
+
+void dpm_clear_vdm_request(int port)
+{
+	DPM_CLR_FLAG(port, DPM_FLAG_SEND_VDM_REQ);
+}
+
+bool dpm_check_vdm_request(int port)
+{
+	return DPM_CHK_FLAG(port, DPM_FLAG_SEND_VDM_REQ);
+}
+
+enum ec_status pd_request_enter_mode(int port, enum typec_mode mode)
+{
+	if (port >= board_get_usb_pd_port_count())
+		return EC_RES_INVALID_PARAM;
+
+	/* Only one enter request may be active at a time. */
+	if (DPM_CHK_FLAG(port, DPM_FLAG_ENTER_DP | DPM_FLAG_ENTER_TBT |
+				       DPM_FLAG_ENTER_USB4))
+		return EC_RES_BUSY;
+
+	if (IS_ENABLED(CONFIG_USB_PD_DP_MODE) && mode == TYPEC_MODE_DP) {
+		if (dp_is_idle(port))
+			dp_init(port);
+		DPM_SET_FLAG(port, DPM_FLAG_ENTER_DP);
+	} else if (IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE) &&
+		   mode == TYPEC_MODE_TBT) {
+		/* TODO(b/235984702#comment21): Refactor alt mode modules
+		 * to better support mode reentry. */
+		if (dp_is_idle(port))
+			dp_init(port);
+		DPM_SET_FLAG(port, DPM_FLAG_ENTER_TBT);
+	} else if (IS_ENABLED(CONFIG_USB_PD_USB4) && mode == TYPEC_MODE_USB4) {
+		DPM_SET_FLAG(port, DPM_FLAG_ENTER_USB4);
+	} else {
+		return EC_RES_INVALID_PARAM;
+	}
+
+	DPM_CLR_FLAG(port, DPM_FLAG_MODE_ENTRY_DONE);
+	DPM_CLR_FLAG(port, DPM_FLAG_EXIT_REQUEST);
+	DPM_CLR_FLAG(port, DPM_FLAG_DATA_RESET_DONE);
+
+	return EC_RES_SUCCESS;
+}
+
 void dpm_init(int port)
 {
-	dpm[port].mode_entry_done = false;
-	dpm[port].mode_exit_request = false;
+	dpm[port].flags = 0;
+	dpm[port].pd_button_state = DPM_PD_BUTTON_IDLE;
+	ap_vdm_init(port);
+
+	/* Ensure that DPM state machine gets reset */
+	set_state_dpm(port, DPM_WAITING);
+}
+
+void dpm_mode_exit_complete(int port)
+{
+	DPM_CLR_FLAG(port, DPM_FLAG_MODE_ENTRY_DONE | DPM_FLAG_EXIT_REQUEST |
+				   DPM_FLAG_SEND_VDM_REQ);
 }
 
-void dpm_set_mode_entry_done(int port)
+static void dpm_set_mode_entry_done(int port)
 {
-	dpm[port].mode_entry_done = true;
+	DPM_SET_FLAG(port, DPM_FLAG_MODE_ENTRY_DONE);
+	DPM_CLR_FLAG(port, DPM_FLAG_ENTER_DP | DPM_FLAG_ENTER_TBT |
+				   DPM_FLAG_ENTER_USB4);
 }
 
 void dpm_set_mode_exit_request(int port)
 {
-	dpm[port].mode_exit_request = true;
+	DPM_SET_FLAG(port, DPM_FLAG_EXIT_REQUEST);
+	DPM_CLR_FLAG(port, DPM_FLAG_DATA_RESET_DONE);
+}
+
+void dpm_data_reset_complete(int port)
+{
+	DPM_SET_FLAG(port, DPM_FLAG_DATA_RESET_DONE);
+	DPM_CLR_FLAG(port, DPM_FLAG_MODE_ENTRY_DONE);
 }
 
-static inline void dpm_clear_mode_exit_request(int port)
+void dpm_set_pe_ready(int port, bool enable)
 {
-	dpm[port].mode_exit_request = false;
+	/*
+	 * DPM should remain DPM_WAITING state until the PE is in its ready
+	 * state and is able to accept requests from the DPM layer.
+	 */
+	if (enable)
+		DPM_SET_FLAG(port, DPM_FLAG_PE_READY);
+	else
+		DPM_CLR_FLAG(port, DPM_FLAG_PE_READY);
+}
+
+static void dpm_clear_mode_exit_request(int port)
+{
+	DPM_CLR_FLAG(port, DPM_FLAG_EXIT_REQUEST);
+}
+
+/*
+ * Returns true if the current policy requests that the EC try to enter this
+ * mode on this port. If the EC is in charge of policy, the answer is always
+ * yes.
+ */
+static bool dpm_mode_entry_requested(int port, enum typec_mode mode)
+{
+	/* If the AP isn't controlling policy, the EC is. */
+	if (!IS_ENABLED(CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY))
+		return true;
+
+	switch (mode) {
+	case TYPEC_MODE_DP:
+		return !!DPM_CHK_FLAG(port, DPM_FLAG_ENTER_DP);
+	case TYPEC_MODE_TBT:
+		return !!DPM_CHK_FLAG(port, DPM_FLAG_ENTER_TBT);
+	case TYPEC_MODE_USB4:
+		return !!DPM_CHK_FLAG(port, DPM_FLAG_ENTER_USB4);
+	default:
+		return false;
+	}
 }
 
-void dpm_vdm_acked(int port, enum tcpm_transmit_type type, int vdo_count,
-		uint32_t *vdm)
+void dpm_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count,
+		   uint32_t *vdm)
 {
-	const uint16_t svid = PD_VDO_VID(vdm[0]);
+	__maybe_unused const uint16_t svid = PD_VDO_VID(vdm[0]);
 
 	assert(vdo_count >= 1);
+	assert(vdo_count <= VDO_MAX_SIZE);
+
+	if (IS_ENABLED(CONFIG_USB_PD_VDM_AP_CONTROL)) {
+		ap_vdm_acked(port, type, vdo_count, vdm);
+		return;
+	}
 
 	switch (svid) {
 	case USB_SID_DISPLAYPORT:
 		dp_vdm_acked(port, type, vdo_count, vdm);
 		break;
 	case USB_VID_INTEL:
-		if (IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE)) {
-			intel_vdm_acked(port, type, vdo_count, vdm);
-			break;
-		}
+/* TODO (http://b/255967867) Can't use the IS_ENABLED macro here because
+ *   __fallthrough fails in clang as unreachable code.
+ */
+#ifdef CONFIG_USB_PD_TBT_COMPAT_MODE
+		intel_vdm_acked(port, type, vdo_count, vdm);
+		break;
+#else
+		__fallthrough;
+#endif /* CONFIG_USB_PD_TBT_COMPAT_MODE */
 	default:
 		CPRINTS("C%d: Received unexpected VDM ACK for SVID %d", port,
-				svid);
+			svid);
 	}
 }
 
-void dpm_vdm_naked(int port, enum tcpm_transmit_type type, uint16_t svid,
-		uint8_t vdm_cmd)
+void dpm_vdm_naked(int port, enum tcpci_msg_type type, uint16_t svid,
+		   uint8_t vdm_cmd, uint32_t vdm_header)
 {
+	if (IS_ENABLED(CONFIG_USB_PD_VDM_AP_CONTROL)) {
+		ap_vdm_naked(port, type, svid, vdm_cmd, vdm_header);
+		return;
+	}
+
 	switch (svid) {
 	case USB_SID_DISPLAYPORT:
 		dp_vdm_naked(port, type, vdm_cmd);
 		break;
 	case USB_VID_INTEL:
-		if (IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE)) {
-			intel_vdm_naked(port, type, vdm_cmd);
-			break;
-		}
+/* TODO (http://b/255967867) Can't use the IS_ENABLED macro here because
+ *   __fallthrough fails in clang as unreachable code.
+ */
+#ifdef CONFIG_USB_PD_TBT_COMPAT_MODE
+		intel_vdm_naked(port, type, vdm_cmd);
+		break;
+#else
+		__fallthrough;
+#endif /* CONFIG_USB_PD_TBT_COMPAT_MODE */
 	default:
 		CPRINTS("C%d: Received unexpected VDM NAK for SVID %d", port,
-				svid);
+			svid);
+	}
+}
+
+static void dpm_send_req_vdm(int port)
+{
+	/* Set up VDM REQ msg that was passed in previously */
+	if (pd_setup_vdm_request(port, dpm[port].req_type, dpm[port].vdm_req,
+				 dpm[port].vdm_req_cnt) == true)
+		/* Trigger PE to start a VDM command run */
+		pd_dpm_request(port, DPM_REQUEST_VDM);
+
+	/*
+	 * Clear flag after message is sent to PE layer if it was Attention,
+	 * which generates no reply.
+	 *
+	 * Otherwise, clear flag after message is ACK'd or NAK'd.  The flag
+	 * will serve as a guard to indicate that the VDM reply buffer is not
+	 * yet ready to read.
+	 *
+	 */
+	if (PD_VDO_SVDM(dpm[port].vdm_req[0]) &&
+	    (PD_VDO_CMD(dpm[port].vdm_req[0]) == CMD_ATTENTION))
+		DPM_CLR_FLAG(port, DPM_FLAG_SEND_VDM_REQ);
+}
+
+void dpm_notify_attention(int port, size_t vdo_objects, uint32_t *buf)
+{
+	/*
+	 * Note: legacy code just assumes 1 VDO, but the spec allows 0
+	 * This should be fine because baked-in EC logic will only be
+	 * handling DP:Attention messages, which are defined to have 1
+	 * VDO
+	 */
+	dfp_consume_attention(port, buf);
+	ap_vdm_attention_enqueue(port, vdo_objects, buf);
+}
+
+void dpm_handle_alert(int port, uint32_t ado)
+{
+	if (ado & ADO_EXTENDED_ALERT_EVENT) {
+		/* Extended Alert */
+		if (pd_get_data_role(port) == PD_ROLE_DFP &&
+		    (ADO_EXTENDED_ALERT_EVENT_TYPE & ado) ==
+			    ADO_POWER_BUTTON_PRESS) {
+			DPM_SET_FLAG(port, DPM_FLAG_PD_BUTTON_PRESSED);
+		} else if (pd_get_data_role(port) == PD_ROLE_DFP &&
+			   (ADO_EXTENDED_ALERT_EVENT_TYPE & ado) ==
+				   ADO_POWER_BUTTON_RELEASE) {
+			DPM_SET_FLAG(port, DPM_FLAG_PD_BUTTON_RELEASED);
+		}
+	}
+}
+
+static void dpm_run_pd_button_sm(int port)
+{
+#ifdef CONFIG_AP_POWER_CONTROL
+	if (!IS_ENABLED(CONFIG_POWER_BUTTON_X86) &&
+	    !IS_ENABLED(CONFIG_CHIPSET_SC7180) &&
+	    !IS_ENABLED(CONFIG_CHIPSET_SC7280)) {
+		/* Insufficient chipset API support for USB PD power button. */
+		DPM_CLR_FLAG(port, DPM_FLAG_PD_BUTTON_PRESSED);
+		DPM_CLR_FLAG(port, DPM_FLAG_PD_BUTTON_RELEASED);
+		return;
+	}
+
+	/*
+	 * Check for invalid flag combination. Alerts can only send a press or
+	 * release event at once and only one flag should be set. If press and
+	 * release flags are both set, we cannot know the order they were
+	 * received. Clear the flags, disable the timer and return to an idle
+	 * state.
+	 */
+	if (DPM_CHK_FLAG(port, DPM_FLAG_PD_BUTTON_PRESSED) &&
+	    DPM_CHK_FLAG(port, DPM_FLAG_PD_BUTTON_RELEASED)) {
+		DPM_CLR_FLAG(port, DPM_FLAG_PD_BUTTON_PRESSED |
+					   DPM_FLAG_PD_BUTTON_RELEASED);
+		pd_timer_disable(port, DPM_TIMER_PD_BUTTON_SHORT_PRESS);
+		pd_timer_disable(port, DPM_TIMER_PD_BUTTON_LONG_PRESS);
+		dpm[port].pd_button_state = DPM_PD_BUTTON_IDLE;
+		return;
+	}
+
+	switch (dpm[port].pd_button_state) {
+	case DPM_PD_BUTTON_IDLE:
+		if (DPM_CHK_FLAG(port, DPM_FLAG_PD_BUTTON_PRESSED)) {
+			pd_timer_enable(port, DPM_TIMER_PD_BUTTON_SHORT_PRESS,
+					CONFIG_USB_PD_SHORT_PRESS_MAX_MS *
+						MSEC);
+			pd_timer_enable(port, DPM_TIMER_PD_BUTTON_LONG_PRESS,
+					CONFIG_USB_PD_LONG_PRESS_MAX_MS * MSEC);
+			dpm[port].pd_button_state = DPM_PD_BUTTON_PRESSED;
+		}
+		break;
+	case DPM_PD_BUTTON_PRESSED:
+		if (DPM_CHK_FLAG(port, DPM_FLAG_PD_BUTTON_PRESSED)) {
+			pd_timer_enable(port, DPM_TIMER_PD_BUTTON_SHORT_PRESS,
+					CONFIG_USB_PD_SHORT_PRESS_MAX_MS *
+						MSEC);
+			pd_timer_enable(port, DPM_TIMER_PD_BUTTON_LONG_PRESS,
+					CONFIG_USB_PD_LONG_PRESS_MAX_MS * MSEC);
+		} else if (pd_timer_is_expired(
+				   port, DPM_TIMER_PD_BUTTON_LONG_PRESS)) {
+			pd_timer_disable(port, DPM_TIMER_PD_BUTTON_SHORT_PRESS);
+			pd_timer_disable(port, DPM_TIMER_PD_BUTTON_LONG_PRESS);
+			dpm[port].pd_button_state = DPM_PD_BUTTON_IDLE;
+		} else if (DPM_CHK_FLAG(port, DPM_FLAG_PD_BUTTON_RELEASED)) {
+			if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
+				/*
+				 * Wake chipset on any button press when the
+				 * system is off.
+				 */
+				chipset_power_on();
+			} else if (chipset_in_state(
+					   CHIPSET_STATE_ANY_SUSPEND) ||
+				   chipset_in_state(CHIPSET_STATE_ON)) {
+				if (pd_timer_is_expired(
+					    port,
+					    DPM_TIMER_PD_BUTTON_SHORT_PRESS)) {
+					/*
+					 * Shutdown chipset on long USB PD power
+					 * button press.
+					 */
+					chipset_force_shutdown(
+						CHIPSET_SHUTDOWN_BUTTON);
+				} else {
+					/*
+					 * Simulate a short power button press
+					 * on short USB PD power button press.
+					 * This will wake the system from
+					 * suspend, or bring up the power UI
+					 * when the system is on.
+					 */
+					power_button_simulate_press(
+						USB_PD_SHORT_BUTTON_PRESS_MS);
+				}
+			}
+			pd_timer_disable(port, DPM_TIMER_PD_BUTTON_SHORT_PRESS);
+			pd_timer_disable(port, DPM_TIMER_PD_BUTTON_LONG_PRESS);
+			dpm[port].pd_button_state = DPM_PD_BUTTON_IDLE;
+		}
+		break;
+	}
+#endif /* CONFIG_AP_POWER_CONTROL */
+
+	/* After checking flags, clear them. */
+	DPM_CLR_FLAG(port, DPM_FLAG_PD_BUTTON_PRESSED);
+	DPM_CLR_FLAG(port, DPM_FLAG_PD_BUTTON_RELEASED);
+}
+
+/*
+ * Source-out policy variables and APIs
+ *
+ * Priority for the available 3.0 A ports is given in the following order:
+ * - sink partners which report requiring > 1.5 A in their Sink_Capabilities
+ */
+
+/*
+ * Bitmasks of port numbers in each following category
+ *
+ * Note: request bitmasks should be accessed atomically as other ports may alter
+ * them
+ */
+static uint32_t max_current_claimed;
+K_MUTEX_DEFINE(max_current_claimed_lock);
+
+/* Ports with PD sink needing > 1.5 A */
+static atomic_t sink_max_pdo_requested;
+/* Ports with FRS source needing > 1.5 A */
+static atomic_t source_frs_max_requested;
+/* Ports with non-PD sinks, so current requirements are unknown */
+static atomic_t non_pd_sink_max_requested;
+
+/* BIST shared test mode */
+static bool bist_shared_mode_enabled;
+
+#define LOWEST_PORT(p) __builtin_ctz(p) /* Undefined behavior if p == 0 */
+
+static int count_port_bits(uint32_t bitmask)
+{
+	int i, total = 0;
+
+	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+		if (bitmask & BIT(i))
+			total++;
 	}
+
+	return total;
 }
 
 /*
- * The call to this function requests that the PE send one VDM, whichever is
- * next in the mode entry sequence. This only happens if preconditions for mode
- * entry are met.
+ * Centralized, mutex-controlled updates to the claimed 3.0 A ports
  */
-static void dpm_attempt_mode_entry(int port)
+static void balance_source_ports(void);
+DECLARE_DEFERRED(balance_source_ports);
+
+static void balance_source_ports(void)
+{
+	uint32_t removed_ports, new_ports;
+	static bool deferred_waiting;
+
+	if (in_deferred_context())
+		deferred_waiting = false;
+
+	/*
+	 * Ignore balance attempts while we're waiting for a downgraded port to
+	 * finish the downgrade.
+	 */
+	if (deferred_waiting)
+		return;
+
+	/*
+	 * Turn off all shared power logic while BIST shared test mode is active
+	 * on the system.
+	 */
+	if (bist_shared_mode_enabled)
+		return;
+
+	mutex_lock(&max_current_claimed_lock);
+
+	/* Remove any ports which no longer require 3.0 A */
+	removed_ports = max_current_claimed &
+			~(sink_max_pdo_requested | source_frs_max_requested |
+			  non_pd_sink_max_requested);
+	max_current_claimed &= ~removed_ports;
+
+	/* Allocate 3.0 A to new PD sink ports that need it */
+	new_ports = sink_max_pdo_requested & ~max_current_claimed;
+	while (new_ports) {
+		int new_max_port = LOWEST_PORT(new_ports);
+
+		if (count_port_bits(max_current_claimed) <
+		    CONFIG_USB_PD_3A_PORTS) {
+			max_current_claimed |= BIT(new_max_port);
+			typec_select_src_current_limit_rp(new_max_port,
+							  TYPEC_RP_3A0);
+		} else if (non_pd_sink_max_requested & max_current_claimed) {
+			/* Always downgrade non-PD ports first */
+			int rem_non_pd = LOWEST_PORT(non_pd_sink_max_requested &
+						     max_current_claimed);
+			typec_select_src_current_limit_rp(
+				rem_non_pd,
+				typec_get_default_current_limit_rp(rem_non_pd));
+			max_current_claimed &= ~BIT(rem_non_pd);
+
+			/* Wait tSinkAdj before using current */
+			deferred_waiting = true;
+			hook_call_deferred(&balance_source_ports_data,
+					   PD_T_SINK_ADJ);
+			goto unlock;
+		} else if (source_frs_max_requested & max_current_claimed) {
+			/* Downgrade lowest FRS port from 3.0 A slot */
+			int rem_frs = LOWEST_PORT(source_frs_max_requested &
+						  max_current_claimed);
+			pd_dpm_request(rem_frs, DPM_REQUEST_FRS_DET_DISABLE);
+			max_current_claimed &= ~BIT(rem_frs);
+
+			/* Give 20 ms for the PD task to process DPM flag */
+			deferred_waiting = true;
+			hook_call_deferred(&balance_source_ports_data,
+					   20 * MSEC);
+			goto unlock;
+		} else {
+			/* No lower priority ports to downgrade */
+			goto unlock;
+		}
+		new_ports &= ~BIT(new_max_port);
+	}
+
+	/* Allocate 3.0 A to any new FRS ports that need it */
+	new_ports = source_frs_max_requested & ~max_current_claimed;
+	while (new_ports) {
+		int new_frs_port = LOWEST_PORT(new_ports);
+
+		if (count_port_bits(max_current_claimed) <
+		    CONFIG_USB_PD_3A_PORTS) {
+			max_current_claimed |= BIT(new_frs_port);
+			pd_dpm_request(new_frs_port,
+				       DPM_REQUEST_FRS_DET_ENABLE);
+		} else if (non_pd_sink_max_requested & max_current_claimed) {
+			int rem_non_pd = LOWEST_PORT(non_pd_sink_max_requested &
+						     max_current_claimed);
+			typec_select_src_current_limit_rp(
+				rem_non_pd,
+				typec_get_default_current_limit_rp(rem_non_pd));
+			max_current_claimed &= ~BIT(rem_non_pd);
+
+			/* Wait tSinkAdj before using current */
+			deferred_waiting = true;
+			hook_call_deferred(&balance_source_ports_data,
+					   PD_T_SINK_ADJ);
+			goto unlock;
+		} else {
+			/* No lower priority ports to downgrade */
+			goto unlock;
+		}
+		new_ports &= ~BIT(new_frs_port);
+	}
+
+	/* Allocate 3.0 A to any non-PD ports which could need it */
+	new_ports = non_pd_sink_max_requested & ~max_current_claimed;
+	while (new_ports) {
+		int new_max_port = LOWEST_PORT(new_ports);
+
+		if (count_port_bits(max_current_claimed) <
+		    CONFIG_USB_PD_3A_PORTS) {
+			max_current_claimed |= BIT(new_max_port);
+			typec_select_src_current_limit_rp(new_max_port,
+							  TYPEC_RP_3A0);
+		} else {
+			/* No lower priority ports to downgrade */
+			goto unlock;
+		}
+		new_ports &= ~BIT(new_max_port);
+	}
+unlock:
+	mutex_unlock(&max_current_claimed_lock);
+}
+
+/* Process port's first Sink_Capabilities PDO for port current consideration */
+void dpm_evaluate_sink_fixed_pdo(int port, uint32_t vsafe5v_pdo)
+{
+	/* Verify partner supplied valid vSafe5V fixed object first */
+	if ((vsafe5v_pdo & PDO_TYPE_MASK) != PDO_TYPE_FIXED)
+		return;
+
+	if (PDO_FIXED_VOLTAGE(vsafe5v_pdo) != 5000)
+		return;
+
+	if (pd_get_power_role(port) == PD_ROLE_SOURCE) {
+		if (CONFIG_USB_PD_3A_PORTS == 0)
+			return;
+
+		/* Valid PDO to process, so evaluate whether >1.5A is needed */
+		if (PDO_FIXED_CURRENT(vsafe5v_pdo) <= 1500)
+			return;
+
+		atomic_or(&sink_max_pdo_requested, BIT(port));
+	} else {
+		int frs_current = vsafe5v_pdo & PDO_FIXED_FRS_CURR_MASK;
+
+		if (!IS_ENABLED(CONFIG_USB_PD_FRS))
+			return;
+
+		/* FRS is only supported in PD 3.0 and higher */
+		if (pd_get_rev(port, TCPCI_MSG_SOP) == PD_REV20)
+			return;
+
+		if ((vsafe5v_pdo & PDO_FIXED_DUAL_ROLE) && frs_current) {
+			/* Always enable FRS when 3.0 A is not needed */
+			if (frs_current == PDO_FIXED_FRS_CURR_DFLT_USB_POWER ||
+			    frs_current == PDO_FIXED_FRS_CURR_1A5_AT_5V) {
+				pd_dpm_request(port,
+					       DPM_REQUEST_FRS_DET_ENABLE);
+				return;
+			}
+
+			if (CONFIG_USB_PD_3A_PORTS == 0)
+				return;
+
+			atomic_or(&source_frs_max_requested, BIT(port));
+		} else {
+			return;
+		}
+	}
+
+	balance_source_ports();
+}
+
+void dpm_add_non_pd_sink(int port)
+{
+	if (CONFIG_USB_PD_3A_PORTS == 0)
+		return;
+
+	atomic_or(&non_pd_sink_max_requested, BIT(port));
+
+	balance_source_ports();
+}
+
+void dpm_evaluate_request_rdo(int port, uint32_t rdo)
+{
+	int idx;
+	int op_ma;
+
+	if (CONFIG_USB_PD_3A_PORTS == 0)
+		return;
+
+	idx = RDO_POS(rdo);
+	/* Check for invalid index */
+	if (!idx)
+		return;
+
+	op_ma = (rdo >> 10) & 0x3FF;
+	if ((BIT(port) & sink_max_pdo_requested) && (op_ma <= 150)) {
+		/*
+		 * sink_max_pdo_requested will be set when we get 5V/3A sink
+		 * capability from port partner. If port partner only request
+		 * 5V/1.5A, we need to provide 5V/1.5A.
+		 */
+		atomic_clear_bits(&sink_max_pdo_requested, BIT(port));
+
+		balance_source_ports();
+	}
+}
+
+void dpm_remove_sink(int port)
+{
+	if (CONFIG_USB_PD_3A_PORTS == 0)
+		return;
+
+	if (!(BIT(port) & (uint32_t)sink_max_pdo_requested) &&
+	    !(BIT(port) & (uint32_t)non_pd_sink_max_requested))
+		return;
+
+	atomic_clear_bits(&sink_max_pdo_requested, BIT(port));
+	atomic_clear_bits(&non_pd_sink_max_requested, BIT(port));
+
+	/* Restore selected default Rp on the port */
+	typec_select_src_current_limit_rp(
+		port, typec_get_default_current_limit_rp(port));
+
+	balance_source_ports();
+}
+
+void dpm_remove_source(int port)
+{
+	if (CONFIG_USB_PD_3A_PORTS == 0)
+		return;
+
+	if (!IS_ENABLED(CONFIG_USB_PD_FRS))
+		return;
+
+	if (!(BIT(port) & (uint32_t)source_frs_max_requested))
+		return;
+
+	atomic_clear_bits(&source_frs_max_requested, BIT(port));
+
+	balance_source_ports();
+}
+
+void dpm_bist_shared_mode_enter(int port)
+{
+	/*
+	 * From 6.4.3.3.1 BIST Shared Test Mode Entry:
+	 *
+	 * "When any Master Port in a shared capacity group receives a BIST
+	 * Message with a BIST Shared Test Mode Entry BIST Data Object, while
+	 * in the PE_SRC_Ready State, the UUT Shall enter a compliance test
+	 * mode where the maximum source capability is always offered on every
+	 * port, regardless of the availability of shared power i.e. all shared
+	 * power management is disabled.
+	 * . . .
+	 * On entering this mode, the UUT Shall send a new Source_Capabilities
+	 * Message from each Port in the shared capacity group within
+	 * tBISTSharedTestMode. The Tester will not exceed the shared capacity
+	 * during this mode."
+	 */
+
+	/* Shared mode is unnecessary without at least one 3.0 A port */
+	if (CONFIG_USB_PD_3A_PORTS == 0)
+		return;
+
+	/* Enter mode only if this port had been in PE_SRC_Ready */
+	if (pd_get_power_role(port) != PD_ROLE_SOURCE)
+		return;
+
+	bist_shared_mode_enabled = true;
+
+	/* Trigger new source caps on all source ports */
+	for (int i = 0; i < board_get_usb_pd_port_count(); i++) {
+		if (pd_get_power_role(i) == PD_ROLE_SOURCE)
+			typec_select_src_current_limit_rp(i, TYPEC_RP_3A0);
+	}
+}
+
+void dpm_bist_shared_mode_exit(int port)
+{
+	/*
+	 * From 6.4.3.3.2 BIST Shared Test Mode Exit:
+	 *
+	 * "Upon receipt of a BIST Message, with a BIST Shared Test Mode Exit
+	 * BIST Data Object, the UUT Shall return a GoodCRC Message and Shall
+	 * exit the BIST Shared Capacity Test Mode.
+	 * . . .
+	 * On exiting the mode, the UUT May send a new Source_Capabilities
+	 * Message to each port in the shared capacity group or the UUT May
+	 * perform ErrorRecovery on each port."
+	 */
+
+	/* Shared mode is unnecessary without at least one 3.0 A port */
+	if (CONFIG_USB_PD_3A_PORTS == 0)
+		return;
+
+	/* Do nothing if Exit was received with no Entry */
+	if (!bist_shared_mode_enabled)
+		return;
+
+	bist_shared_mode_enabled = false;
+
+	/* Declare error recovery bankruptcy */
+	for (int i = 0; i < board_get_usb_pd_port_count(); i++) {
+		pd_set_error_recovery(i);
+	}
+}
+
+/*
+ * Note: all ports receive the 1.5 A source offering until they are found to
+ * match a criteria on the 3.0 A priority list (ex. through sink capability
+ * probing), at which point they will be offered a new 3.0 A source capability.
+ *
+ * All ports must be offered our full capability while in BIST shared test mode.
+ */
+__overridable int dpm_get_source_pdo(const uint32_t **src_pdo, const int port)
+{
+	/* Max PDO may not exist on boards which don't offer 3 A */
+#if CONFIG_USB_PD_3A_PORTS > 0
+	if (max_current_claimed & BIT(port) || bist_shared_mode_enabled) {
+		*src_pdo = pd_src_pdo_max;
+		return pd_src_pdo_max_cnt;
+	}
+#endif
+
+	*src_pdo = pd_src_pdo;
+	return pd_src_pdo_cnt;
+}
+
+int dpm_get_source_current(const int port)
+{
+	if (pd_get_power_role(port) == PD_ROLE_SINK)
+		return 0;
+
+	if (max_current_claimed & BIT(port) || bist_shared_mode_enabled)
+		return 3000;
+	else if (typec_get_default_current_limit_rp(port) == TYPEC_RP_1A5)
+		return 1500;
+	else
+		return 500;
+}
+
+__overridable enum pd_sdb_power_indicator
+board_get_pd_sdb_power_indicator(enum pd_sdb_power_state power_state)
+{
+	/*
+	 *  LED on for S0 and blinking for S0ix/S3.
+	 *  LED off for all other power states (S4, S5, G3, NOT_SUPPORTED)
+	 */
+	switch (power_state) {
+	case PD_SDB_POWER_STATE_S0:
+		return PD_SDB_POWER_INDICATOR_ON;
+	case PD_SDB_POWER_STATE_MODERN_STANDBY:
+	case PD_SDB_POWER_STATE_S3:
+		return PD_SDB_POWER_INDICATOR_BLINKING;
+	default:
+		return PD_SDB_POWER_INDICATOR_OFF;
+	}
+}
+
+static uint8_t get_status_internal_temp(void)
+{
+	/*
+	 * Internal Temp
+	 */
+#ifdef CONFIG_TEMP_SENSOR
+	int temp_k, temp_c;
+
+	if (temp_sensor_read(CONFIG_USB_PD_TEMP_SENSOR, &temp_k) != EC_SUCCESS)
+		return 0;
+
+	/* Check temp is in expected range (<255°C) */
+	temp_c = K_TO_C(temp_k);
+	if (temp_c > 255)
+		return 0;
+	else if (temp_c < 2)
+		temp_c = 1;
+
+	return (uint8_t)temp_c;
+#else
+	return 0;
+#endif
+}
+
+static enum pd_sdb_temperature_status get_status_temp_status(void)
+{
+	/*
+	 * Temperature Status
+	 *
+	 * OTP events are currently unsupported by the EC, the temperature
+	 * status will be reported as "not supported" on temp sensor read
+	 * failures and "Normal" otherwise.
+	 */
+#ifdef CONFIG_TEMP_SENSOR
+	int temp_k;
+
+	if (temp_sensor_read(CONFIG_USB_PD_TEMP_SENSOR, &temp_k) != EC_SUCCESS)
+		return PD_SDB_TEMPERATURE_STATUS_NOT_SUPPORTED;
+
+	return PD_SDB_TEMPERATURE_STATUS_NORMAL;
+#else
+	return PD_SDB_TEMPERATURE_STATUS_NOT_SUPPORTED;
+#endif
+}
+
+static uint8_t get_status_power_state_change(void)
+{
+	enum pd_sdb_power_state ret = PD_SDB_POWER_STATE_NOT_SUPPORTED;
+
+#ifdef CONFIG_AP_POWER_CONTROL
+	if (chipset_in_or_transitioning_to_state(CHIPSET_STATE_HARD_OFF)) {
+		ret = PD_SDB_POWER_STATE_G3;
+	} else if (chipset_in_or_transitioning_to_state(
+			   CHIPSET_STATE_SOFT_OFF)) {
+		/*
+		 * SOFT_OFF includes S4; chipset_state API doesn't support S4
+		 * specifically, so fold S4 to S5
+		 */
+		ret = PD_SDB_POWER_STATE_S5;
+	} else if (chipset_in_or_transitioning_to_state(
+			   CHIPSET_STATE_SUSPEND)) {
+		ret = PD_SDB_POWER_STATE_S3;
+	} else if (chipset_in_or_transitioning_to_state(CHIPSET_STATE_ON)) {
+		ret = PD_SDB_POWER_STATE_S0;
+	} else if (chipset_in_or_transitioning_to_state(
+			   CHIPSET_STATE_STANDBY)) {
+		ret = PD_SDB_POWER_STATE_MODERN_STANDBY;
+	}
+#endif /* CONFIG_AP_POWER_CONTROL */
+
+	return ret | board_get_pd_sdb_power_indicator(ret);
+}
+
+int dpm_get_status_msg(int port, uint8_t *msg, uint32_t *len)
+{
+	struct pd_sdb sdb;
+	struct rmdo partner_rmdo;
+
+	/* TODO(b/227236917): Fill in fields of Status message */
+
+	/* Internal Temp */
+	sdb.internal_temp = get_status_internal_temp();
+
+	/* Present Input */
+	sdb.present_input = 0x0;
+
+	/* Present Battery Input */
+	sdb.present_battery_input = 0x0;
+
+	/* Event Flags */
+	sdb.event_flags = 0x0;
+
+	/* Temperature Status */
+	sdb.temperature_status = get_status_temp_status();
+
+	/* Power Status */
+	sdb.power_status = 0x0;
+
+	partner_rmdo = pd_get_partner_rmdo(port);
+	if ((partner_rmdo.major_rev == 3 && partner_rmdo.minor_rev >= 1) ||
+	    partner_rmdo.major_rev > 3) {
+		/* USB PD Rev 3.1: 6.5.2 Status Message */
+		sdb.power_state_change = get_status_power_state_change();
+		*len = 7;
+	} else {
+		/* USB PD Rev 3.0: 6.5.2 Status Message */
+		sdb.power_state_change = 0;
+		*len = 6;
+	}
+
+	memcpy(msg, &sdb, *len);
+	return EC_SUCCESS;
+}
+
+enum ec_status pd_set_bist_share_mode(uint8_t enable)
+{
+	/*
+	 * This command is not allowed if system is locked.
+	 */
+	if (CONFIG_USB_PD_3A_PORTS == 0 || system_is_locked())
+		return EC_RES_ACCESS_DENIED;
+
+	if (enable)
+		bist_shared_mode_enabled = true;
+	else
+		bist_shared_mode_enabled = false;
+
+	return EC_RES_SUCCESS;
+}
+
+uint8_t pd_get_bist_share_mode(void)
+{
+	return bist_shared_mode_enabled;
+}
+
+/*
+ * Requests that the PE send one VDM, whichever is next in the mode entry
+ * sequence. This only happens if preconditions for mode entry are met. If
+ * CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY is enabled, this function waits for the
+ * AP to direct mode entry.
+ *
+ * Returns true when the DPM state is changed in this function.
+ */
+static bool dpm_dfp_enter_mode_msg(int port)
 {
 	int vdo_count = 0;
 	uint32_t vdm[VDO_MAX_SIZE];
-	enum tcpm_transmit_type tx_type = TCPC_TX_SOP;
+	enum tcpci_msg_type tx_type = TCPCI_MSG_SOP;
+	bool enter_mode_requested =
+		IS_ENABLED(CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY) ? false : true;
+	enum dpm_msg_setup_status status = MSG_SETUP_UNSUPPORTED;
 
-	if (pd_get_data_role(port) != PD_ROLE_DFP)
-		return;
+#ifdef CONFIG_AP_POWER_CONTROL
 	/*
 	 * Do not try to enter mode while CPU is off.
 	 * CPU transitions (e.g b/158634281) can occur during the discovery
@@ -112,48 +1185,107 @@ static void dpm_attempt_mode_entry(int port)
 	 * of the modes can get out of sync, causing the attempt to
 	 * enter the mode to fail prematurely.
 	 */
-	if (chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF))
-		return;
+	if (!chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON))
+		return false;
+#endif
 	/*
 	 * If discovery has not occurred for modes, do not attempt to switch
 	 * to alt mode.
 	 */
-	if (pd_get_svids_discovery(port, TCPC_TX_SOP) != PD_DISC_COMPLETE ||
-	    pd_get_modes_discovery(port, TCPC_TX_SOP) != PD_DISC_COMPLETE)
-		return;
+	if (pd_get_svids_discovery(port, TCPCI_MSG_SOP) != PD_DISC_COMPLETE ||
+	    pd_get_modes_discovery(port, TCPCI_MSG_SOP) != PD_DISC_COMPLETE)
+		return false;
 
-	/* Check if the device and cable support USB4. */
-	if (IS_ENABLED(CONFIG_USB_PD_USB4) && enter_usb_is_capable(port)) {
-		pd_dpm_request(port, DPM_REQUEST_ENTER_USB);
-		return;
+	if (dp_entry_is_done(port) ||
+	    (IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE) &&
+	     tbt_entry_is_done(port)) ||
+	    (IS_ENABLED(CONFIG_USB_PD_USB4) && enter_usb_entry_is_done(port))) {
+		dpm_set_mode_entry_done(port);
+		return false;
+	}
+
+	/*
+	 * If AP mode entry is enabled, and a Data Reset has not been done, then
+	 * first request Data Reset prior to attempting to enter any modes.
+	 */
+	if (IS_ENABLED(CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY) &&
+	    IS_ENABLED(CONFIG_USB_PD_DATA_RESET_MSG) &&
+	    DPM_CHK_FLAG(port, DPM_FLAG_ENTER_ANY) &&
+	    !DPM_CHK_FLAG(port, DPM_FLAG_DATA_RESET_DONE)) {
+		set_state_dpm(port, DPM_DATA_RESET);
+		return true;
+	}
+
+	/* Check if port, port partner and cable support USB4. */
+	if (IS_ENABLED(CONFIG_USB_PD_USB4) && board_is_tbt_usb4_port(port) &&
+	    enter_usb_port_partner_is_capable(port) &&
+	    enter_usb_cable_is_capable(port) &&
+	    dpm_mode_entry_requested(port, TYPEC_MODE_USB4)) {
+		/*
+		 * For certain cables, enter Thunderbolt alt mode with the
+		 * cable and USB4 mode with the port partner.
+		 */
+		if (tbt_cable_entry_required_for_usb4(port)) {
+			vdo_count = ARRAY_SIZE(vdm);
+			status = tbt_setup_next_vdm(port, &vdo_count, vdm,
+						    &tx_type);
+		} else {
+			pd_dpm_request(port, DPM_REQUEST_ENTER_USB);
+			return false;
+		}
 	}
 
 	/* If not, check if they support Thunderbolt alt mode. */
 	if (IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE) &&
-	    pd_is_mode_discovered_for_svid(port, TCPC_TX_SOP, USB_VID_INTEL))
-		vdo_count = tbt_setup_next_vdm(port,
-			ARRAY_SIZE(vdm), vdm, &tx_type);
+	    board_is_tbt_usb4_port(port) &&
+	    pd_is_mode_discovered_for_svid(port, TCPCI_MSG_SOP,
+					   USB_VID_INTEL) &&
+	    dpm_mode_entry_requested(port, TYPEC_MODE_TBT)) {
+		enter_mode_requested = true;
+		vdo_count = ARRAY_SIZE(vdm);
+		status = tbt_setup_next_vdm(port, &vdo_count, vdm, &tx_type);
+	}
 
 	/* If not, check if they support DisplayPort alt mode. */
-	if (vdo_count == 0 && !dpm[port].mode_entry_done &&
-	    pd_is_mode_discovered_for_svid(port, TCPC_TX_SOP,
-				USB_SID_DISPLAYPORT))
-		vdo_count = dp_setup_next_vdm(port, ARRAY_SIZE(vdm), vdm);
+	if (status == MSG_SETUP_UNSUPPORTED &&
+	    !DPM_CHK_FLAG(port, DPM_FLAG_MODE_ENTRY_DONE) &&
+	    pd_is_mode_discovered_for_svid(port, TCPCI_MSG_SOP,
+					   USB_SID_DISPLAYPORT) &&
+	    dpm_mode_entry_requested(port, TYPEC_MODE_DP)) {
+		enter_mode_requested = true;
+		vdo_count = ARRAY_SIZE(vdm);
+		status = dp_setup_next_vdm(port, &vdo_count, vdm);
+	}
+
+	/* Not ready to send a VDM, check again next cycle */
+	if (status == MSG_SETUP_MUX_WAIT)
+		return false;
 
 	/*
-	 * If the PE didn't discover any supported alternate mode, just mark
-	 * setup done and get out of here.
+	 * If the PE didn't discover any supported (requested) alternate mode,
+	 * just mark setup done and get out of here.
 	 */
-	if (vdo_count == 0 && !dpm[port].mode_entry_done) {
-		CPRINTS("C%d: No supported alt mode discovered", port);
+	if (status != MSG_SETUP_SUCCESS &&
+	    !DPM_CHK_FLAG(port, DPM_FLAG_MODE_ENTRY_DONE)) {
+		if (enter_mode_requested) {
+			/*
+			 * TODO(b/168030639): Notify the AP that mode entry
+			 * failed.
+			 */
+			CPRINTS("C%d: No supported alt mode discovered", port);
+		}
+		/*
+		 * If the AP did not request mode entry, it may do so in the
+		 * future, but the DPM is done trying for now.
+		 */
 		dpm_set_mode_entry_done(port);
-		return;
+		return false;
 	}
 
-	if (vdo_count < 0) {
+	if (status != MSG_SETUP_SUCCESS) {
 		dpm_set_mode_entry_done(port);
 		CPRINTS("C%d: Couldn't construct alt mode VDM", port);
-		return;
+		return false;
 	}
 
 	/*
@@ -162,59 +1294,246 @@ static void dpm_attempt_mode_entry(int port)
 	 */
 	if (!pd_setup_vdm_request(port, tx_type, vdm, vdo_count)) {
 		dpm_set_mode_entry_done(port);
-		return;
+		return false;
 	}
 
+	/* Wait for PE to handle VDM request */
 	pd_dpm_request(port, DPM_REQUEST_VDM);
+	set_state_dpm(port, DPM_WAITING);
+
+	return true;
 }
 
-static void dpm_attempt_mode_exit(int port)
+/*
+ * Checks to see if either USB4 or ALT-DP/TBT modes need to be exited. If the
+ * DPM is requesting the PE to send an exit message, then this function will
+ * return true to indicate that the DPM state has been changed.
+ */
+static bool dpm_dfp_exit_mode_msg(int port)
 {
-	int opos;
-	uint16_t svid;
-	uint32_t vdm;
+	uint32_t vdm[VDO_MAX_SIZE];
+	int vdo_count = ARRAY_SIZE(vdm);
+	enum dpm_msg_setup_status status = MSG_SETUP_ERROR;
+	enum tcpci_msg_type tx_type = TCPCI_MSG_SOP;
 
-	/* TODO(b/156749387): Support Data Reset for exiting USB4. */
-	if (IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE) &&
-	    tbt_is_active(port))
-		svid = USB_VID_INTEL;
-	else if (dp_is_active(port))
-		svid = USB_SID_DISPLAYPORT;
-	else {
+	/* First, try Data Reset. If Data Reset completes, all the alt mode
+	 * state checked below will reset to its inactive state. If Data Reset
+	 * is not supported, exit active modes individually.
+	 */
+	if (IS_ENABLED(CONFIG_USB_PD_DATA_RESET_MSG) &&
+	    !DPM_CHK_FLAG(port, DPM_FLAG_DATA_RESET_DONE)) {
+		set_state_dpm(port, DPM_DATA_RESET);
+		return true;
+	}
+
+	/* TODO(b/209625351): Data Reset is the only real way to exit from USB4
+	 * mode. If that failed, the TCPM shouldn't try anything else.
+	 */
+	if (IS_ENABLED(CONFIG_USB_PD_USB4) && enter_usb_entry_is_done(port)) {
+		CPRINTS("C%d: USB4 teardown", port);
+		usb4_exit_mode_request(port);
+	}
+
+	if (IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE) && tbt_is_active(port)) {
+		/*
+		 * When the port is in USB4 mode and receives an exit request,
+		 * it leaves USB4 SOP in active state.
+		 */
+		CPRINTS("C%d: TBT teardown", port);
+		tbt_exit_mode_request(port);
+		status = tbt_setup_next_vdm(port, &vdo_count, vdm, &tx_type);
+	} else if (dp_is_active(port)) {
+		CPRINTS("C%d: DP teardown", port);
+		status = dp_setup_next_vdm(port, &vdo_count, vdm);
+	} else {
 		/* Clear exit mode request */
 		dpm_clear_mode_exit_request(port);
+		return false;
+	}
+
+	/* This covers error, wait mux, and unsupported cases */
+	if (status != MSG_SETUP_SUCCESS)
+		return false;
+
+	if (!pd_setup_vdm_request(port, tx_type, vdm, vdo_count)) {
+		dpm_clear_mode_exit_request(port);
+		return false;
+	}
+
+	pd_dpm_request(port, DPM_REQUEST_VDM);
+	set_state_dpm(port, DPM_WAITING);
+
+	return true;
+}
+
+void dpm_run(int port, int evt, int en)
+{
+	switch (local_state[port]) {
+	case SM_PAUSED:
+		if (!en)
+			break;
+		__fallthrough;
+	case SM_INIT:
+		dpm_init(port);
+		local_state[port] = SM_RUN;
+		__fallthrough;
+	case SM_RUN:
+		if (!en) {
+			local_state[port] = SM_PAUSED;
+			/*
+			 * While we are paused, exit all states and wait until
+			 * initialized again.
+			 */
+			set_state(port, &dpm[port].ctx, NULL);
+			break;
+		}
+
+		/* Run state machine */
+		run_state(port, &dpm[port].ctx);
+
+		break;
+	}
+}
+
+/*
+ * DPM_WAITING
+ */
+static void dpm_waiting_entry(const int port)
+{
+	DPM_CLR_FLAG(port, DPM_FLAG_PE_READY);
+	if (dpm_debug_level >= DEBUG_LEVEL_2) {
+		print_current_state(port);
+	}
+}
+
+static void dpm_waiting_run(const int port)
+{
+	enum pd_data_role dr = pd_get_data_role(port);
+
+	if (DPM_CHK_FLAG(port, DPM_FLAG_PE_READY)) {
+		if (dr == PD_ROLE_UFP) {
+			set_state_dpm(port, DPM_UFP_READY);
+		} else if (dr == PD_ROLE_DFP) {
+			set_state_dpm(port, DPM_DFP_READY);
+		}
+	}
+}
+
+/*
+ * DPM_DFP_READY
+ */
+static void dpm_dfp_ready_entry(const int port)
+{
+	if (dpm_debug_level >= DEBUG_LEVEL_2) {
+		print_current_state(port);
+	}
+}
+
+static void dpm_dfp_ready_run(const int port)
+{
+	if (!DPM_CHK_FLAG(port, DPM_FLAG_PE_READY)) {
+		set_state_dpm(port, DPM_WAITING);
 		return;
 	}
 
+	/* Run power button state machine */
+	dpm_run_pd_button_sm(port);
+
 	/*
-	 * TODO(b/148528713): Support cable plug Exit Mode (probably outsource
-	 * VDM construction to alt mode modules).
+	 * If muxes are still settling, then wait on our next VDM.  We must
+	 * ensure we correctly sequence actions such as USB safe state with TBT
+	 * or DP mode exit.
 	 */
-	opos = pd_alt_mode(port, TCPC_TX_SOP, svid);
-	if (opos > 0 && pd_dfp_exit_mode(port, TCPC_TX_SOP, svid, opos)) {
-		/*
-		 * TODO b/159717794: Delay deleting the data until after the
-		 * EXIT_MODE message is has ACKed. Unfortunately the callers
-		 * of this function expect the mode to be cleaned up before
-		 * return.
-		 */
-		vdm = VDO(svid, 1, /* Structured */
-			  VDO_SVDM_VERS(pd_get_vdo_ver(port, TCPC_TX_SOP)) |
-			  VDO_OPOS(opos) | VDO_CMDT(CMDT_INIT) | CMD_EXIT_MODE);
+	if (IS_ENABLED(CONFIG_USBC_SS_MUX) && !usb_mux_set_completed(port))
+		return;
 
-		if (!pd_setup_vdm_request(port, TCPC_TX_SOP, &vdm, 1)) {
-			dpm_clear_mode_exit_request(port);
+	/* Run DFP related DPM requests */
+	if (DPM_CHK_FLAG(port, DPM_FLAG_EXIT_REQUEST)) {
+		if (dpm_dfp_exit_mode_msg(port))
 			return;
-		}
+	} else if (!DPM_CHK_FLAG(port, DPM_FLAG_MODE_ENTRY_DONE)) {
+		if (dpm_dfp_enter_mode_msg(port))
+			return;
+	}
 
-		pd_dpm_request(port, DPM_REQUEST_VDM);
+	/* Run any VDM REQ messages */
+	if (DPM_CHK_FLAG(port, DPM_FLAG_SEND_VDM_REQ)) {
+		dpm_send_req_vdm(port);
+		set_state_dpm(port, DPM_WAITING);
+		return;
+	}
+}
+
+/*
+ * DPM_UFP_READY
+ */
+static void dpm_ufp_ready_entry(const int port)
+{
+	if (dpm_debug_level >= DEBUG_LEVEL_2) {
+		print_current_state(port);
+	}
+}
+
+static void dpm_ufp_ready_run(const int port)
+{
+	if (!DPM_CHK_FLAG(port, DPM_FLAG_PE_READY)) {
+		set_state_dpm(port, DPM_WAITING);
+		return;
+	}
+
+	if (DPM_CHK_FLAG(port, DPM_FLAG_ENTER_ANY)) {
+		DPM_CLR_FLAG(port, DPM_FLAG_ENTER_DP | DPM_FLAG_ENTER_TBT |
+					   DPM_FLAG_ENTER_USB4);
+		/*
+		 * TODO(b/168030639): Notify the AP that the
+		 * enter mode request failed.
+		 */
+		return;
+	}
+
+	/* Run any VDM REQ messages */
+	if (DPM_CHK_FLAG(port, DPM_FLAG_SEND_VDM_REQ)) {
+		dpm_send_req_vdm(port);
+		set_state_dpm(port, DPM_WAITING);
+		return;
 	}
 }
 
-void dpm_run(int port)
+/*
+ * DPM_DATA_RESET
+ */
+static void dpm_data_reset_entry(const int port)
 {
-	if (dpm[port].mode_exit_request)
-		dpm_attempt_mode_exit(port);
-	else if (!dpm[port].mode_entry_done)
-		dpm_attempt_mode_entry(port);
+	print_current_state(port);
+
+	pd_dpm_request(port, DPM_REQUEST_DATA_RESET);
 }
+
+static void dpm_data_reset_run(const int port)
+{
+	/* Wait for Data Reset to Complete */
+	if (!DPM_CHK_FLAG(port, DPM_FLAG_DATA_RESET_DONE))
+		return;
+
+	set_state_dpm(port, DPM_DFP_READY);
+}
+
+static __const_data const struct usb_state dpm_states[] = {
+	/* Normal States */
+	[DPM_WAITING] = {
+		.entry = dpm_waiting_entry,
+		.run   = dpm_waiting_run,
+	},
+	[DPM_DFP_READY] = {
+		.entry = dpm_dfp_ready_entry,
+		.run   = dpm_dfp_ready_run,
+	},
+	[DPM_UFP_READY] = {
+		.entry = dpm_ufp_ready_entry,
+		.run   = dpm_ufp_ready_run,
+	},
+	[DPM_DATA_RESET] = {
+		.entry = dpm_data_reset_entry,
+		.run   = dpm_data_reset_run,
+	},
+};
diff --git a/common/usbc/usb_pd_host.c b/common/usbc/usb_pd_host.c
index 61c1c69966..81cdc4fc49 100644
--- a/common/usbc/usb_pd_host.c
+++ b/common/usbc/usb_pd_host.c
@@ -1,21 +1,23 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Host commands for TCPMv2 USB PD module
  */
 
-#include <string.h>
-
 #include "console.h"
 #include "ec_commands.h"
 #include "host_command.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
+#include "usb_pd_dpm_sm.h"
+#include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#include <string.h>
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 /* Retrieve all discovery results for the given port and transmit type */
 static enum ec_status hc_typec_discovery(struct host_cmd_handler_args *args)
@@ -23,7 +25,7 @@ static enum ec_status hc_typec_discovery(struct host_cmd_handler_args *args)
 	const struct ec_params_typec_discovery *p = args->params;
 	struct ec_response_typec_discovery *r = args->response;
 	const struct pd_discovery *disc;
-	enum tcpm_transmit_type type;
+	enum tcpci_msg_type type;
 
 	/* Confirm the number of HC VDOs matches our stored VDOs */
 	BUILD_ASSERT(sizeof(r->discovery_vdo) == sizeof(union disc_ident_ack));
@@ -34,8 +36,8 @@ static enum ec_status hc_typec_discovery(struct host_cmd_handler_args *args)
 	if (p->partner_type > TYPEC_PARTNER_SOP_PRIME)
 		return EC_RES_INVALID_PARAM;
 
-	type = p->partner_type == TYPEC_PARTNER_SOP ?
-		TCPC_TX_SOP : TCPC_TX_SOP_PRIME;
+	type = p->partner_type == TYPEC_PARTNER_SOP ? TCPCI_MSG_SOP :
+						      TCPCI_MSG_SOP_PRIME;
 
 	/*
 	 * Clear out access mask so we can track if tasks have touched data
@@ -43,7 +45,7 @@ static enum ec_status hc_typec_discovery(struct host_cmd_handler_args *args)
 	 */
 	pd_discovery_access_clear(p->port, type);
 
-	disc = pd_get_am_discovery(p->port, type);
+	disc = pd_get_am_discovery_and_notify_access(p->port, type);
 
 	/* Initialize return size to that of discovery with no SVIDs */
 	args->response_size = sizeof(*r);
@@ -60,8 +62,9 @@ static enum ec_status hc_typec_discovery(struct host_cmd_handler_args *args)
 
 	if (pd_get_modes_discovery(p->port, type) == PD_DISC_COMPLETE) {
 		int svid_i;
-		int max_resp_svids = (args->response_max - args->response_size)/
-				      sizeof(struct svid_mode_info);
+		int max_resp_svids =
+			(args->response_max - args->response_size) /
+			sizeof(struct svid_mode_info);
 
 		if (disc->svid_cnt > max_resp_svids) {
 			CPRINTS("Warn: SVIDS exceeded HC response");
@@ -73,7 +76,7 @@ static enum ec_status hc_typec_discovery(struct host_cmd_handler_args *args)
 		for (svid_i = 0; svid_i < r->svid_count; svid_i++) {
 			r->svids[svid_i].svid = disc->svids[svid_i].svid;
 			r->svids[svid_i].mode_count =
-						disc->svids[svid_i].mode_cnt;
+				disc->svids[svid_i].mode_cnt;
 			memcpy(r->svids[svid_i].mode_vdo,
 			       disc->svids[svid_i].mode_vdo,
 			       sizeof(r->svids[svid_i].mode_vdo));
@@ -88,18 +91,29 @@ static enum ec_status hc_typec_discovery(struct host_cmd_handler_args *args)
 	 * of the copy.  If the data was accessed, return BUSY so the AP will
 	 * try retrieving again and get the updated data.
 	 */
-	if (!pd_discovery_access_validate(p->port, type))
+	if (!pd_discovery_access_validate(p->port, type)) {
+		CPRINTS("[C%d] %s returns EC_RES_BUSY!!", p->port, __func__);
 		return EC_RES_BUSY;
+	}
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_TYPEC_DISCOVERY,
-		     hc_typec_discovery,
+DECLARE_HOST_COMMAND(EC_CMD_TYPEC_DISCOVERY, hc_typec_discovery,
 		     EC_VER_MASK(0));
 
+/* Default to feature unavailable, with boards supporting it overriding */
+__overridable enum ec_status
+board_set_tbt_ufp_reply(int port, enum typec_tbt_ufp_reply reply)
+{
+	return EC_RES_UNAVAILABLE;
+}
+
 static enum ec_status hc_typec_control(struct host_cmd_handler_args *args)
 {
 	const struct ec_params_typec_control *p = args->params;
+	mux_state_t mode;
+	uint32_t data[VDO_MAX_SIZE];
+	enum tcpci_msg_type tx_type;
 
 	if (p->port >= board_get_usb_pd_port_count())
 		return EC_RES_INVALID_PARAM;
@@ -111,49 +125,163 @@ static enum ec_status hc_typec_control(struct host_cmd_handler_args *args)
 	case TYPEC_CONTROL_COMMAND_CLEAR_EVENTS:
 		pd_clear_events(p->port, p->clear_events_mask);
 		break;
+	case TYPEC_CONTROL_COMMAND_ENTER_MODE:
+		return pd_request_enter_mode(p->port, p->mode_to_enter);
+	case TYPEC_CONTROL_COMMAND_TBT_UFP_REPLY:
+		return board_set_tbt_ufp_reply(p->port, p->tbt_ufp_reply);
+	case TYPEC_CONTROL_COMMAND_USB_MUX_SET:
+		/* The EC will fill in polarity, so filter flip out */
+		mode = p->mux_params.mux_flags & ~USB_PD_MUX_POLARITY_INVERTED;
+
+		if (!IS_ENABLED(CONFIG_USB_MUX_AP_CONTROL))
+			return EC_RES_INVALID_PARAM;
+
+		usb_mux_set_single(p->port, p->mux_params.mux_index, mode,
+				   USB_SWITCH_CONNECT,
+				   polarity_rm_dts(pd_get_polarity(p->port)));
+		return EC_RES_SUCCESS;
+	case TYPEC_CONTROL_COMMAND_BIST_SHARE_MODE:
+		return pd_set_bist_share_mode(p->bist_share_mode);
+	case TYPEC_CONTROL_COMMAND_SEND_VDM_REQ:
+		if (!IS_ENABLED(CONFIG_USB_PD_VDM_AP_CONTROL))
+			return EC_RES_INVALID_PARAM;
+
+		if (p->vdm_req_params.vdm_data_objects <= 0 ||
+		    p->vdm_req_params.vdm_data_objects > VDO_MAX_SIZE)
+			return EC_RES_INVALID_PARAM;
+
+		memcpy(data, p->vdm_req_params.vdm_data,
+		       sizeof(uint32_t) * p->vdm_req_params.vdm_data_objects);
+
+		switch (p->vdm_req_params.partner_type) {
+		case TYPEC_PARTNER_SOP:
+			tx_type = TCPCI_MSG_SOP;
+			break;
+		case TYPEC_PARTNER_SOP_PRIME:
+			tx_type = TCPCI_MSG_SOP_PRIME;
+			break;
+		case TYPEC_PARTNER_SOP_PRIME_PRIME:
+			tx_type = TCPCI_MSG_SOP_PRIME_PRIME;
+			break;
+		default:
+			return EC_RES_INVALID_PARAM;
+		}
+
+		return pd_request_vdm(p->port, data,
+				      p->vdm_req_params.vdm_data_objects,
+				      tx_type);
 	default:
 		return EC_RES_INVALID_PARAM;
 	}
 
-
 	return EC_RES_SUCCESS;
 }
 DECLARE_HOST_COMMAND(EC_CMD_TYPEC_CONTROL, hc_typec_control, EC_VER_MASK(0));
 
+/*
+ * Validate ec_response_typec_status_v0's binary compatibility with
+ * ec_response_typec_status, which is being deprecated.
+ */
+BUILD_ASSERT(offsetof(struct ec_response_typec_status_v0,
+		      typec_status.sop_prime_revision) ==
+	     offsetof(struct ec_response_typec_status, sop_prime_revision));
+BUILD_ASSERT(offsetof(struct ec_response_typec_status_v0, source_cap_pdos) ==
+	     offsetof(struct ec_response_typec_status, source_cap_pdos));
+BUILD_ASSERT(sizeof(struct ec_response_typec_status_v0) ==
+	     sizeof(struct ec_response_typec_status));
+
+/*
+ * Validate ec_response_typec_status_v0's binary compatibility with
+ * ec_response_typec_status_v1 with respect to typec_status.
+ */
+BUILD_ASSERT(offsetof(struct ec_response_typec_status_v0,
+		      typec_status.pd_enabled) ==
+	     offsetof(struct ec_response_typec_status_v1,
+		      typec_status.pd_enabled));
+BUILD_ASSERT(offsetof(struct ec_response_typec_status_v0,
+		      typec_status.sop_prime_revision) ==
+	     offsetof(struct ec_response_typec_status_v1,
+		      typec_status.sop_prime_revision));
+
 static enum ec_status hc_typec_status(struct host_cmd_handler_args *args)
 {
 	const struct ec_params_typec_status *p = args->params;
-	struct ec_response_typec_status *r = args->response;
+	struct ec_response_typec_status_v1 *r1 = args->response;
+	struct ec_response_typec_status_v0 *r0 = args->response;
+	struct cros_ec_typec_status *cs = &r1->typec_status;
 	const char *tc_state_name;
 
 	if (p->port >= board_get_usb_pd_port_count())
 		return EC_RES_INVALID_PARAM;
 
-	if (args->response_max < sizeof(*r))
-		return EC_RES_RESPONSE_TOO_BIG;
+	args->response_size = args->version == 0 ? sizeof(*r0) : sizeof(*r1);
 
-	args->response_size = sizeof(*r);
+	if (args->response_max < args->response_size)
+		return EC_RES_RESPONSE_TOO_BIG;
 
-	r->pd_enabled = pd_comm_is_enabled(p->port);
-	r->dev_connected = pd_is_connected(p->port);
-	r->sop_connected = pd_capable(p->port);
+	cs->pd_enabled = pd_comm_is_enabled(p->port);
+	cs->dev_connected = pd_is_connected(p->port);
+	cs->sop_connected = pd_capable(p->port);
 
-	r->power_role = pd_get_power_role(p->port);
-	r->data_role = pd_get_data_role(p->port);
-	r->vconn_role = pd_get_vconn_state(p->port) ? PD_ROLE_VCONN_SRC :
-						      PD_ROLE_VCONN_OFF;
-	r->polarity = pd_get_polarity(p->port);
-	r->cc_state = pd_get_task_cc_state(p->port);
-	r->dp_pin = get_dp_pin_mode(p->port);
-	r->mux_state = usb_mux_get(p->port);
+	cs->power_role = pd_get_power_role(p->port);
+	cs->data_role = pd_get_data_role(p->port);
+	cs->vconn_role = pd_get_vconn_state(p->port) ? PD_ROLE_VCONN_SRC :
+						       PD_ROLE_VCONN_OFF;
+	cs->polarity = pd_get_polarity(p->port);
+	cs->cc_state = pd_get_task_cc_state(p->port);
+	cs->dp_pin = get_dp_pin_mode(p->port);
+	cs->mux_state = usb_mux_get(p->port);
 
 	tc_state_name = pd_get_task_state_name(p->port);
-	strzcpy(r->tc_state, tc_state_name, sizeof(r->tc_state));
-
-	r->events = pd_get_events(p->port);
+	strzcpy(cs->tc_state, tc_state_name, sizeof(cs->tc_state));
+
+	cs->events = pd_get_events(p->port);
+
+	if (pd_get_partner_rmdo(p->port).major_rev != 0) {
+		cs->sop_revision =
+			PD_STATUS_RMDO_REV_SET_MAJOR(
+				pd_get_partner_rmdo(p->port).major_rev) |
+			PD_STATUS_RMDO_REV_SET_MINOR(
+				pd_get_partner_rmdo(p->port).minor_rev) |
+			PD_STATUS_RMDO_VER_SET_MAJOR(
+				pd_get_partner_rmdo(p->port).major_ver) |
+			PD_STATUS_RMDO_VER_SET_MINOR(
+				pd_get_partner_rmdo(p->port).minor_ver);
+	} else if (cs->sop_connected) {
+		cs->sop_revision = PD_STATUS_REV_SET_MAJOR(
+			pd_get_rev(p->port, TCPCI_MSG_SOP));
+	} else {
+		cs->sop_revision = 0;
+	}
 
-	/* TODO(b/167700356): Add revisions and source cap PDOs */
+	cs->sop_prime_revision =
+		pd_get_identity_discovery(p->port, TCPCI_MSG_SOP_PRIME) ==
+				PD_DISC_COMPLETE ?
+			PD_STATUS_REV_SET_MAJOR(
+				pd_get_rev(p->port, TCPCI_MSG_SOP_PRIME)) :
+			0;
+
+	if (args->version == 0) {
+		cs->source_cap_count = MIN(pd_get_src_cap_cnt(p->port),
+					   ARRAY_SIZE(r0->source_cap_pdos));
+		memcpy(r0->source_cap_pdos, pd_get_src_caps(p->port),
+		       cs->source_cap_count * sizeof(uint32_t));
+		cs->sink_cap_count = MIN(pd_get_snk_cap_cnt(p->port),
+					 ARRAY_SIZE(r0->sink_cap_pdos));
+		memcpy(r0->sink_cap_pdos, pd_get_snk_caps(p->port),
+		       cs->sink_cap_count * sizeof(uint32_t));
+	} else {
+		cs->source_cap_count = MIN(pd_get_src_cap_cnt(p->port),
+					   ARRAY_SIZE(r1->source_cap_pdos));
+		memcpy(r1->source_cap_pdos, pd_get_src_caps(p->port),
+		       cs->source_cap_count * sizeof(uint32_t));
+		cs->sink_cap_count = MIN(pd_get_snk_cap_cnt(p->port),
+					 ARRAY_SIZE(r1->sink_cap_pdos));
+		memcpy(r1->sink_cap_pdos, pd_get_snk_caps(p->port),
+		       cs->sink_cap_count * sizeof(uint32_t));
+	}
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_TYPEC_STATUS, hc_typec_status, EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_TYPEC_STATUS, hc_typec_status,
+		     EC_VER_MASK(0) | EC_VER_MASK(1));
diff --git a/common/usbc/usb_pd_timer.c b/common/usbc/usb_pd_timer.c
new file mode 100644
index 0000000000..a6ec07125d
--- /dev/null
+++ b/common/usbc/usb_pd_timer.c
@@ -0,0 +1,282 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "assert.h"
+#include "atomic.h"
+#include "atomic_bit.h"
+#include "common.h"
+#include "console.h"
+#include "limits.h"
+#include "math_util.h"
+#include "system.h"
+#include "usb_pd_timer.h"
+#include "usb_tc_sm.h"
+
+#define MAX_PD_PORTS CONFIG_USB_PD_PORT_MAX_COUNT
+#define MAX_PD_TIMERS PD_TIMER_COUNT
+#define PD_TIMERS_ALL_MASK (UINT64_MAX >> (64 - PD_TIMER_COUNT))
+
+#define MAX_EXPIRE (0x7FFFFFFF)
+#define NO_TIMEOUT (-1)
+#define EXPIRE_NOW (0)
+
+#define PD_SET_ACTIVE(p, bit) \
+	atomic_set_bit(timer_active, (p)*PD_TIMER_COUNT + (bit))
+
+#define PD_CLR_ACTIVE(p, bit) \
+	atomic_clear_bit(timer_active, (p)*PD_TIMER_COUNT + (bit))
+
+#define PD_CHK_ACTIVE(p, bit) \
+	atomic_test_bit(timer_active, (p)*PD_TIMER_COUNT + (bit))
+
+#define PD_SET_DISABLED(p, bit) \
+	atomic_set_bit(timer_disabled, (p)*PD_TIMER_COUNT + (bit))
+
+#define PD_CLR_DISABLED(p, bit) \
+	atomic_clear_bit(timer_disabled, (p)*PD_TIMER_COUNT + (bit))
+
+#define PD_CHK_DISABLED(p, bit) \
+	atomic_test_bit(timer_disabled, (p)*PD_TIMER_COUNT + (bit))
+
+test_mockable_static ATOMIC_DEFINE(timer_active, PD_TIMER_COUNT *MAX_PD_PORTS);
+test_mockable_static ATOMIC_DEFINE(timer_disabled,
+				   PD_TIMER_COUNT *MAX_PD_PORTS);
+static uint64_t timer_expires[MAX_PD_PORTS][PD_TIMER_COUNT];
+
+/*
+ * CONFIG_CMD_PD_TIMER debug variables
+ */
+static int count[MAX_PD_PORTS];
+static int max_count[MAX_PD_PORTS];
+
+__maybe_unused static __const_data const char *const pd_timer_names[] = {
+	[DPM_TIMER_PD_BUTTON_LONG_PRESS] = "DPM-PD_BUTTON_LONG_PRESS",
+	[DPM_TIMER_PD_BUTTON_SHORT_PRESS] = "DPM-PD_BUTTON_SHORT_PRESS",
+	[PE_TIMER_BIST_CONT_MODE] = "PE-BIST_CONT_MODE",
+	[PE_TIMER_CHUNKING_NOT_SUPPORTED] = "PE-CHUNKING_NOT_SUPPORTED",
+	[PE_TIMER_DISCOVER_IDENTITY] = "PE-DISCOVER_IDENTITY",
+	[PE_TIMER_NO_RESPONSE] = "PE-NO_RESPONSE",
+	[PE_TIMER_PR_SWAP_WAIT] = "PE-PR_SWAP_WAIT",
+	[PE_TIMER_PS_HARD_RESET] = "PE-PS_HARD_RESET",
+	[PE_TIMER_PS_SOURCE] = "PE-PS_SOURCE",
+	[PE_TIMER_PS_TRANSITION] = "PE-PS_TRANSITION",
+	[PE_TIMER_SENDER_RESPONSE] = "PE-SENDER_RESPONSE",
+	[PE_TIMER_SINK_REQUEST] = "PE-SINK_REQUEST",
+	[PE_TIMER_SOURCE_CAP] = "PE-SOURCE_CAP",
+	[PE_TIMER_SRC_TRANSITION] = "PE-SRC_TRANSITION",
+	[PE_TIMER_SWAP_SOURCE_START] = "PE-SWAP_SOURCE_START",
+	[PE_TIMER_TIMEOUT] = "PE-TIMEOUT",
+	[PE_TIMER_VCONN_ON] = "PE-VCONN_ON",
+	[PE_TIMER_VDM_RESPONSE] = "PE-VDM_RESPONSE",
+	[PE_TIMER_WAIT_AND_ADD_JITTER] = "PE-WAIT_AND_ADD_JITTER",
+	[PE_TIMER_VCONN_DISCHARGE] = "PE-VCONN_DISCHARGE",
+	[PE_TIMER_VCONN_REAPPLIED] = "PE-VCONN_REAPPLIED",
+	[PE_TIMER_DATA_RESET_FAIL] = "PE-DATA_RESET_FAIL",
+
+	[PR_TIMER_CHUNK_SENDER_REQUEST] = "PR-CHUNK_SENDER_REQUEST",
+	[PR_TIMER_CHUNK_SENDER_RESPONSE] = "PR-CHUNK_SENDER_RESPONSE",
+	[PR_TIMER_HARD_RESET_COMPLETE] = "PR-HARD_RESET_COMPLETE",
+	[PR_TIMER_SINK_TX] = "PR-SINK_TX",
+	[PR_TIMER_TCPC_TX_TIMEOUT] = "PR-TCPC_TX_TIMEOUT",
+	[TC_TIMER_CC_DEBOUNCE] = "TC-CC_DEBOUNCE",
+	[TC_TIMER_LOW_POWER_EXIT_TIME] = "TC-LOW_POWER_EXIT_TIME",
+	[TC_TIMER_LOW_POWER_TIME] = "TC-LOW_POWER_TIME",
+	[TC_TIMER_NEXT_ROLE_SWAP] = "TC-NEXT_ROLE_SWAP",
+	[TC_TIMER_PD_DEBOUNCE] = "TC-PD_DEBOUNCE",
+	[TC_TIMER_TIMEOUT] = "TC-TIMEOUT",
+	[TC_TIMER_TRY_WAIT_DEBOUNCE] = "TC-TRY_WAIT_DEBOUNCE",
+	[TC_TIMER_VBUS_DEBOUNCE] = "TC-VBUS_DEBOUNCE",
+};
+
+/*****************************************************************************
+ * PD_TIMER private functions
+ *
+ * The view of timers to the outside world is enabled and disabled. Internally
+ * timers that are enabled are in the active and inactive states. An active
+ * timer has a valid timeout value that gets checked for expiration and can
+ * adjust the task wakeup time.  An inactive timer is assumed to have expired
+ * already and will always return that it is still expired.  This timer state
+ * will not adjust the task scheduling timeout value.
+ */
+
+static void pd_timer_inactive(int port, enum pd_task_timer timer)
+{
+	if (PD_CHK_ACTIVE(port, timer)) {
+		PD_CLR_ACTIVE(port, timer);
+
+		if (IS_ENABLED(CONFIG_CMD_PD_TIMER))
+			count[port]--;
+	}
+	PD_CLR_DISABLED(port, timer);
+}
+
+static bool pd_timer_is_active(int port, enum pd_task_timer timer)
+{
+	return PD_CHK_ACTIVE(port, timer);
+}
+
+static bool pd_timer_is_inactive(int port, enum pd_task_timer timer)
+{
+	return !PD_CHK_ACTIVE(port, timer) && !PD_CHK_DISABLED(port, timer);
+}
+
+/*****************************************************************************
+ * PD_TIMER public functions
+ */
+void pd_timer_init(int port)
+{
+	if (IS_ENABLED(CONFIG_CMD_PD_TIMER))
+		count[port] = 0;
+
+	/*
+	 * Set timers to init state for "port".
+	 */
+	for (int bit = 0; bit < PD_TIMER_COUNT; bit++) {
+		PD_CLR_ACTIVE(port, bit);
+		PD_SET_DISABLED(port, bit);
+	}
+}
+
+void pd_timer_enable(int port, enum pd_task_timer timer, uint32_t expires_us)
+{
+	if (!PD_CHK_ACTIVE(port, timer)) {
+		PD_SET_ACTIVE(port, timer);
+
+		if (IS_ENABLED(CONFIG_CMD_PD_TIMER)) {
+			count[port]++;
+			if (count[port] > max_count[port])
+				max_count[port] = count[port];
+		}
+	}
+	PD_CLR_DISABLED(port, timer);
+	timer_expires[port][timer] = get_time().val + expires_us;
+}
+
+void pd_timer_disable(int port, enum pd_task_timer timer)
+{
+	if (PD_CHK_ACTIVE(port, timer)) {
+		PD_CLR_ACTIVE(port, timer);
+
+		if (IS_ENABLED(CONFIG_CMD_PD_TIMER))
+			count[port]--;
+	}
+	PD_SET_DISABLED(port, timer);
+}
+
+void pd_timer_disable_range(int port, enum pd_timer_range range)
+{
+	int start, end;
+	enum pd_task_timer timer;
+
+	switch (range) {
+	case DPM_TIMER_RANGE:
+		start = DPM_TIMER_START;
+		end = DPM_TIMER_END;
+		break;
+	case PE_TIMER_RANGE:
+		start = PE_TIMER_START;
+		end = PE_TIMER_END;
+		break;
+	case PR_TIMER_RANGE:
+		start = PR_TIMER_START;
+		end = PR_TIMER_END;
+		break;
+	case TC_TIMER_RANGE:
+		start = TC_TIMER_START;
+		end = TC_TIMER_END;
+		break;
+	default:
+		return;
+	}
+
+	for (timer = start; timer <= end; ++timer)
+		pd_timer_disable(port, timer);
+}
+
+bool pd_timer_is_disabled(int port, enum pd_task_timer timer)
+{
+	return PD_CHK_DISABLED(port, timer);
+}
+
+bool pd_timer_is_expired(int port, enum pd_task_timer timer)
+{
+	if (pd_timer_is_active(port, timer)) {
+		if (get_time().val >= timer_expires[port][timer]) {
+			pd_timer_inactive(port, timer);
+			return true;
+		}
+		return false;
+	}
+	return pd_timer_is_inactive(port, timer);
+}
+
+void pd_timer_manage_expired(int port)
+{
+	int timer;
+
+	for (timer = 0; timer < PD_TIMER_COUNT; ++timer)
+		if (pd_timer_is_active(port, timer) &&
+		    pd_timer_is_expired(port, timer))
+			pd_timer_inactive(port, timer);
+}
+
+int pd_timer_next_expiration(int port)
+{
+	int timer;
+	int ret_value = MAX_EXPIRE;
+	uint64_t now = get_time().val;
+
+	for (timer = 0; timer < PD_TIMER_COUNT; ++timer) {
+		/* Only use active timers for the next expired value */
+		if (pd_timer_is_active(port, timer)) {
+			int delta;
+			uint64_t t_value = timer_expires[port][timer];
+
+			if (t_value <= now) {
+				ret_value = EXPIRE_NOW;
+				break;
+			}
+
+			delta = t_value - now;
+			if (ret_value > delta)
+				ret_value = delta;
+		}
+	}
+
+	if (ret_value == MAX_EXPIRE)
+		ret_value = NO_TIMEOUT;
+
+	return ret_value;
+}
+
+#ifdef CONFIG_CMD_PD_TIMER
+test_mockable_static void pd_timer_dump(int port)
+{
+	int timer;
+	uint64_t now = get_time().val;
+
+	ccprints("Timers(%d): cur=%d max=%d", port, count[port],
+		 max_count[port]);
+
+	for (timer = 0; timer < PD_TIMER_COUNT; ++timer) {
+		if (pd_timer_is_disabled(port, timer)) {
+			continue;
+		} else if (pd_timer_is_active(port, timer)) {
+			uint32_t delta = 0;
+
+			if (now < timer_expires[port][timer])
+				delta = timer_expires[port][timer] - now;
+
+			ccprints("[%2d] Active:   %s (%d%s)", timer,
+				 pd_timer_names[timer], (uint32_t)delta,
+				 tc_event_loop_is_paused(port) ? "-PAUSED" :
+								 "");
+		} else {
+			ccprints("[%2d] Inactive: %s", timer,
+				 pd_timer_names[timer]);
+		}
+	}
+}
+#endif /* CONFIG_CMD_PD_TIMER */
diff --git a/common/usbc/usb_pe_ctvpd_sm.c b/common/usbc/usb_pe_ctvpd_sm.c
index ee5c10aca1..223c40c71d 100644
--- a/common/usbc/usb_pe_ctvpd_sm.c
+++ b/common/usbc/usb_pe_ctvpd_sm.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,14 +6,14 @@
 #include "common.h"
 #include "console.h"
 #include "task.h"
-#include "util.h"
+#include "usb_emsg.h"
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 #include "usb_pe_sm.h"
 #include "usb_prl_sm.h"
-#include "usb_tc_sm.h"
-#include "usb_emsg.h"
 #include "usb_sm.h"
+#include "usb_tc_sm.h"
+#include "util.h"
 
 /* USB Policy Engine Charge-Through VCONN Powered Device module */
 
@@ -53,6 +53,12 @@ static void pe_init(int port)
 	set_state_pe(port, PE_REQUEST);
 }
 
+bool pe_in_frs_mode(int port)
+{
+	/* Will never be in FRS mode */
+	return false;
+}
+
 bool pe_in_local_ams(int port)
 {
 	/* We never start a local AMS */
@@ -67,11 +73,11 @@ void pe_run(int port, int evt, int en)
 	case SM_PAUSED:
 		if (!en)
 			break;
-		/* fall through */
+		__fallthrough;
 	case SM_INIT:
 		pe_init(port);
 		local_state[port] = SM_RUN;
-		/* fall through */
+		__fallthrough;
 	case SM_RUN:
 		if (en)
 			run_state(port, &pe[port].ctx);
@@ -104,7 +110,7 @@ void pe_got_hard_reset(int port)
 	/* No implementation needed by this policy engine */
 }
 
-void pe_report_error(int port, enum pe_error e, enum tcpm_transmit_type type)
+void pe_report_error(int port, enum pe_error e, enum tcpci_msg_type type)
 {
 	/* No implementation needed by this policy engine */
 }
@@ -160,53 +166,48 @@ static void pe_request_run(const int port)
 		/* Prepare to send ACK */
 
 		/* VDM Header */
-		payload[0] = VDO(
-			USB_VID_GOOGLE,
-			1, /* Structured VDM */
-			VDO_SVDM_VERS(1) |
-			VDO_CMDT(CMDT_RSP_ACK) |
-			CMD_DISCOVER_IDENT);
+		payload[0] = VDO(USB_VID_GOOGLE, 1, /* Structured VDM */
+				 VDO_SVDM_VERS(1) | VDO_CMDT(CMDT_RSP_ACK) |
+					 CMD_DISCOVER_IDENT);
 
 		/* ID Header VDO */
-		payload[1] = VDO_IDH(
-			0, /* Not a USB Host */
-			1, /* Capable of being enumerated as USB Device */
-			IDH_PTYPE_VPD,
-			0, /* Modal Operation Not Supported */
-			USB_VID_GOOGLE);
+		payload[1] = VDO_IDH(0, /* Not a USB Host */
+				     1, /* Capable of being enumerated as USB
+					   Device */
+				     IDH_PTYPE_VPD, 0, /* Modal Operation Not
+							  Supported */
+				     USB_VID_GOOGLE);
 
 		/* Cert State VDO */
 		payload[2] = 0;
 
 		/* Product VDO */
-		payload[3] = VDO_PRODUCT(
-			CONFIG_USB_PID,
-			USB_BCD_DEVICE);
+		payload[3] = VDO_PRODUCT(CONFIG_USB_PID, USB_BCD_DEVICE);
 
 		/* VPD VDO */
 		payload[4] = VDO_VPD(
-			VPD_HW_VERSION,
-			VPD_FW_VERSION,
-			VPD_MAX_VBUS_20V,
-			VPD_VBUS_IMP(VPD_VBUS_IMPEDANCE),
-			VPD_GND_IMP(VPD_GND_IMPEDANCE),
-#ifdef CONFIG_USB_CTVPD
-			VPD_CTS_SUPPORTED
-#else
-			VPD_CTS_NOT_SUPPORTED
-#endif
-		);
+			VPD_HW_VERSION, VPD_FW_VERSION, VPD_MAX_VBUS_20V,
+			IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_CT_CURRENT : 0,
+			IS_ENABLED(CONFIG_USB_CTVPD) ?
+				VPD_VBUS_IMP(VPD_VBUS_IMPEDANCE) :
+				0,
+			IS_ENABLED(CONFIG_USB_CTVPD) ?
+				VPD_GND_IMP(VPD_GND_IMPEDANCE) :
+				0,
+			IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_CTS_SUPPORTED :
+						       VPD_CTS_NOT_SUPPORTED);
 
 		/* 20 bytes, 5 data objects */
 		tx_emsg[port].len = 20;
 
 		/* Set to highest revision supported by both ports. */
-		prl_set_rev(port, TCPC_TX_SOP_PRIME,
-					(PD_HEADER_REV(header) > PD_REV30) ?
-					PD_REV30 : PD_HEADER_REV(header));
+		prl_set_rev(port, TCPCI_MSG_SOP_PRIME,
+			    (PD_HEADER_REV(header) > PD_REV30) ?
+				    PD_REV30 :
+				    PD_HEADER_REV(header));
 		/* Send the ACK */
-		prl_send_data_msg(port, TCPC_TX_SOP_PRIME,
-					PD_DATA_VENDOR_DEF);
+		prl_send_data_msg(port, TCPCI_MSG_SOP_PRIME,
+				  PD_DATA_VENDOR_DEF);
 	}
 }
 
diff --git a/common/usbc/usb_pe_drp_sm.c b/common/usbc/usb_pe_drp_sm.c
index 19fb59d0a2..dba06dfbfb 100644
--- a/common/usbc/usb_pe_drp_sm.c
+++ b/common/usbc/usb_pe_drp_sm.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,29 +6,40 @@
 #include "atomic.h"
 #include "battery.h"
 #include "battery_smart.h"
+#include "builtin/assert.h"
 #include "charge_manager.h"
 #include "charge_state.h"
 #include "common.h"
 #include "console.h"
+#include "dps.h"
+#include "driver/tcpm/tcpm.h"
+#include "ec_commands.h"
 #include "hooks.h"
 #include "host_command.h"
+#include "power_button.h"
 #include "stdbool.h"
+#include "system.h"
 #include "task.h"
-#include "tcpm.h"
-#include "util.h"
+#include "tcpm/tcpm.h"
+#include "usb_charge.h"
 #include "usb_common.h"
 #include "usb_dp_alt_mode.h"
+#include "usb_emsg.h"
 #include "usb_mode.h"
-#include "usb_pd_dpm.h"
+#include "usb_mux.h"
 #include "usb_pd.h"
+#include "usb_pd_dpm_sm.h"
+#include "usb_pd_policy.h"
 #include "usb_pd_tcpm.h"
+#include "usb_pd_timer.h"
+#include "usb_pe_private.h"
 #include "usb_pe_sm.h"
-#include "usb_tbt_alt_mode.h"
 #include "usb_prl_sm.h"
-#include "usb_tc_sm.h"
-#include "usb_emsg.h"
 #include "usb_sm.h"
+#include "usb_tbt_alt_mode.h"
+#include "usb_tc_sm.h"
 #include "usbc_ppc.h"
+#include "util.h"
 
 /*
  * USB Policy Engine Sink / Source module
@@ -38,123 +49,64 @@
  */
 
 #ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 #else
 #define CPRINTF(format, args...)
 #define CPRINTS(format, args...)
 #endif
 
-#define CPRINTF_LX(x, format, args...) \
-	do { \
-		if (pe_debug_level >= x) \
-			CPRINTF(format, ## args); \
+#define CPRINTF_LX(x, format, args...)           \
+	do {                                     \
+		if (pe_debug_level >= x)         \
+			CPRINTF(format, ##args); \
 	} while (0)
-#define CPRINTF_L1(format, args...) CPRINTF_LX(1, format, ## args)
-#define CPRINTF_L2(format, args...) CPRINTF_LX(2, format, ## args)
-#define CPRINTF_L3(format, args...) CPRINTF_LX(3, format, ## args)
-
-#define CPRINTS_LX(x, format, args...) \
-	do { \
-		if (pe_debug_level >= x) \
-			CPRINTS(format, ## args); \
+#define CPRINTF_L1(format, args...) CPRINTF_LX(1, format, ##args)
+#define CPRINTF_L2(format, args...) CPRINTF_LX(2, format, ##args)
+#define CPRINTF_L3(format, args...) CPRINTF_LX(3, format, ##args)
+
+#define CPRINTS_LX(x, format, args...)           \
+	do {                                     \
+		if (pe_debug_level >= x)         \
+			CPRINTS(format, ##args); \
 	} while (0)
-#define CPRINTS_L1(format, args...) CPRINTS_LX(1, format, ## args)
-#define CPRINTS_L2(format, args...) CPRINTS_LX(2, format, ## args)
-#define CPRINTS_L3(format, args...) CPRINTS_LX(3, format, ## args)
+#define CPRINTS_L1(format, args...) CPRINTS_LX(1, format, ##args)
+#define CPRINTS_L2(format, args...) CPRINTS_LX(2, format, ##args)
+#define CPRINTS_L3(format, args...) CPRINTS_LX(3, format, ##args)
+
+#define PE_SET_FN(port, _fn) \
+	atomic_or(ATOMIC_ELEM(pe[port].flags_a, (_fn)), ATOMIC_MASK(_fn))
+#define PE_CLR_FN(port, _fn)                                    \
+	atomic_clear_bits(ATOMIC_ELEM(pe[port].flags_a, (_fn)), \
+			  ATOMIC_MASK(_fn))
+#define PE_CHK_FN(port, _fn) \
+	(pe[port].flags_a[ATOMIC_ELEM(0, (_fn))] & ATOMIC_MASK(_fn))
+
+#define PE_SET_FLAG(port, name) PE_SET_FN(port, (name##_FN))
+#define PE_CLR_FLAG(port, name) PE_CLR_FN(port, (name##_FN))
+#define PE_CHK_FLAG(port, name) PE_CHK_FN(port, (name##_FN))
 
-
-#define PE_SET_FLAG(port, flag) deprecated_atomic_or(&pe[port].flags, (flag))
-#define PE_CLR_FLAG(port, flag) \
-	deprecated_atomic_clear_bits(&pe[port].flags, (flag))
-#define PE_CHK_FLAG(port, flag) (pe[port].flags & (flag))
+/*
+ * TODO(b/229655319): support more than 32 bits
+ */
+#define PE_SET_MASK(port, mask) atomic_or(&pe[port].flags_a[0], (mask))
+#define PE_CLR_MASK(port, mask) atomic_clear_bits(&pe[port].flags_a[0], (mask))
 
 /*
  * These macros SET, CLEAR, and CHECK, a DPM (Device Policy Manager)
  * Request. The Requests are listed in usb_pe_sm.h.
  */
-#define PE_SET_DPM_REQUEST(port, req) \
-	deprecated_atomic_or(&pe[port].dpm_request, (req))
+#define PE_SET_DPM_REQUEST(port, req) atomic_or(&pe[port].dpm_request, (req))
 #define PE_CLR_DPM_REQUEST(port, req) \
-	deprecated_atomic_clear_bits(&pe[port].dpm_request, (req))
+	atomic_clear_bits(&pe[port].dpm_request, (req))
 #define PE_CHK_DPM_REQUEST(port, req) (pe[port].dpm_request & (req))
 
-/*
- * Policy Engine Layer Flags
- * These are reproduced in test/usb_pe.h. If they change here, they must change
- * there.
- */
-
-/* At least one successful PD communication packet received from port partner */
-#define PE_FLAGS_PD_CONNECTION               BIT(0)
-/* Accept message received from port partner */
-#define PE_FLAGS_ACCEPT                      BIT(1)
-/* Power Supply Ready message received from port partner */
-#define PE_FLAGS_PS_READY                    BIT(2)
-/* Protocol Error was determined based on error recovery current state */
-#define PE_FLAGS_PROTOCOL_ERROR              BIT(3)
-/* Set if we are in Modal Operation */
-#define PE_FLAGS_MODAL_OPERATION             BIT(4)
-/* A message we requested to be sent has been transmitted */
-#define PE_FLAGS_TX_COMPLETE                 BIT(5)
-/* A message sent by a port partner has been received */
-#define PE_FLAGS_MSG_RECEIVED                BIT(6)
-/* A hard reset has been requested but has not been sent, not currently used */
-#define PE_FLAGS_HARD_RESET_PENDING          BIT(7)
-/* Port partner sent a Wait message. Wait before we resend our message */
-#define PE_FLAGS_WAIT                        BIT(8)
-/* An explicit contract is in place with our port partner */
-#define PE_FLAGS_EXPLICIT_CONTRACT           BIT(9)
-/* Waiting for Sink Capabailities timed out.  Used for retry error handling */
-#define PE_FLAGS_SNK_WAIT_CAP_TIMEOUT        BIT(10)
-/* Power Supply voltage/current transition timed out */
-#define PE_FLAGS_PS_TRANSITION_TIMEOUT       BIT(11)
-/* Flag to note current Atomic Message Sequence is interruptible */
-#define PE_FLAGS_INTERRUPTIBLE_AMS           BIT(12)
-/* Flag to note Power Supply reset has completed */
-#define PE_FLAGS_PS_RESET_COMPLETE           BIT(13)
-/* VCONN swap operation has completed */
-#define PE_FLAGS_VCONN_SWAP_COMPLETE         BIT(14)
-/* Flag to note no more setup VDMs (discovery, etc.) should be sent */
-#define PE_FLAGS_VDM_SETUP_DONE              BIT(15)
-/* Flag to note PR Swap just completed for Startup entry */
-#define PE_FLAGS_PR_SWAP_COMPLETE	     BIT(16)
-/* Flag to note Port Discovery port partner replied with BUSY */
-#define PE_FLAGS_VDM_REQUEST_BUSY            BIT(17)
-/* Flag to note Port Discovery port partner replied with NAK */
-#define PE_FLAGS_VDM_REQUEST_NAKED           BIT(18)
-/* Flag to note FRS/PRS context in shared state machine path */
-#define PE_FLAGS_FAST_ROLE_SWAP_PATH         BIT(19)
-/* Flag to note if FRS listening is enabled */
-#define PE_FLAGS_FAST_ROLE_SWAP_ENABLED      BIT(20)
-/* Flag to note TCPC passed on FRS signal from port partner */
-#define PE_FLAGS_FAST_ROLE_SWAP_SIGNALED     BIT(21)
-/* TODO: POLICY decision: Triggers a DR SWAP attempt from UFP to DFP */
-#define PE_FLAGS_DR_SWAP_TO_DFP              BIT(22)
-/*
- * TODO: POLICY decision
- * Flag to trigger a message resend after receiving a WAIT from port partner
- */
-#define PE_FLAGS_WAITING_PR_SWAP             BIT(23)
-/* FLAG to track if port partner is dualrole capable */
-#define PE_FLAGS_PORT_PARTNER_IS_DUALROLE    BIT(24)
-/* FLAG is set when an AMS is initiated locally. ie. AP requested a PR_SWAP */
-#define PE_FLAGS_LOCALLY_INITIATED_AMS       BIT(25)
-/* Flag to note the first message sent in PE_SRC_READY and PE_SNK_READY */
-#define PE_FLAGS_FIRST_MSG                   BIT(26)
-/* Flag to continue a VDM request if it was interrupted */
-#define PE_FLAGS_VDM_REQUEST_CONTINUE        BIT(27)
-/* TODO: POLICY decision: Triggers a Vconn SWAP attempt to on */
-#define PE_FLAGS_VCONN_SWAP_TO_ON	     BIT(28)
-/* FLAG to track that VDM request to port partner timed out */
-#define PE_FLAGS_VDM_REQUEST_TIMEOUT	     BIT(29)
-/* FLAG to note message was discarded due to incoming message */
-#define PE_FLAGS_MSG_DISCARDED		     BIT(30)
-
 /* Message flags which should not persist on returning to ready state */
-#define PE_FLAGS_READY_CLR		     (PE_FLAGS_LOCALLY_INITIATED_AMS \
-					     | PE_FLAGS_MSG_DISCARDED \
-					     | PE_FLAGS_VDM_REQUEST_TIMEOUT)
+#define PE_MASK_READY_CLR                         \
+	(BIT(PE_FLAGS_LOCALLY_INITIATED_AMS_FN) | \
+	 BIT(PE_FLAGS_MSG_DISCARDED_FN) |         \
+	 BIT(PE_FLAGS_VDM_REQUEST_TIMEOUT_FN) |   \
+	 BIT(PE_FLAGS_INTERRUPTIBLE_AMS_FN))
 
 /*
  * Combination to check whether a reply to a message was received.  Our message
@@ -165,9 +117,9 @@
  * on the same run cycle.  With chunking, received message will take an
  * additional cycle to be flagged.
  */
-#define PE_CHK_REPLY(port)	(PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED) && \
-				 !PE_CHK_FLAG(port, PE_FLAGS_MSG_DISCARDED))
-
+#define PE_CHK_REPLY(port)                           \
+	(PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED) && \
+	 !PE_CHK_FLAG(port, PE_FLAGS_MSG_DISCARDED))
 /* 6.7.3 Hard Reset Counter */
 #define N_HARD_RESET_COUNT 2
 
@@ -184,13 +136,25 @@
 #define N_DISCOVER_IDENTITY_COUNT 6
 
 /*
- * tDiscoverIdentity is only defined while an explicit contract is in place.
- * To support captive cable devices that power the SOP' responder from VBUS
- * instead of VCONN stretch out the SOP' Discover Identity messages when
- * no contract is present. 200 ms provides about 1 second for the cable
- * to power up (200 * 5 retries).
+ * It is permitted to send SOP' Discover Identity messages before a PD contract
+ * is in place. However, this is only beneficial if the cable powers up quickly
+ * solely from VCONN. Limit the number of retries without a contract to
+ * ensure we attempt some cable discovery after a contract is in place.
+ */
+#define N_DISCOVER_IDENTITY_PRECONTRACT_LIMIT 2
+
+/*
+ * Once this limit of SOP' Discover Identity messages has been set, downgrade
+ * to PD 2.0 in case the cable is non-compliant about GoodCRC-ing higher
+ * revisions.  This limit should be higher than the precontract limit.
+ */
+#define N_DISCOVER_IDENTITY_PD3_0_LIMIT 4
+
+/*
+ * tDiscoverIdentity is only defined while an explicit contract is in place, so
+ * extend the interval between retries pre-contract.
  */
-#define PE_T_DISCOVER_IDENTITY_NO_CONTRACT	(200*MSEC)
+#define PE_T_DISCOVER_IDENTITY_NO_CONTRACT (200 * MSEC)
 
 /*
  * Only VCONN source can communicate with the cable plug. Hence, try VCONN swap
@@ -221,12 +185,13 @@
 
 /*
  * The time that we allow the port partner to send any messages after an
- * explicit contract is established.  400ms was chosen somewhat arbitrarily as
+ * explicit contract is established.  200ms was chosen somewhat arbitrarily as
  * it should be long enough for sources to decide to send a message if they were
  * going to, but not so long that a "low power charger connected" notification
- * would be shown in the chrome OS UI.
+ * would be shown in the chrome OS UI. Setting t0o large a delay can cause
+ * problems if the PD discovery time exceeds 1s (tAMETimeout)
  */
-#define SRC_SNK_READY_HOLD_OFF_US (400 * MSEC)
+#define SRC_SNK_READY_HOLD_OFF_US (200 * MSEC)
 
 /*
  * Function pointer to a Structured Vendor Defined Message (SVDM) response
@@ -237,77 +202,98 @@ typedef int (*svdm_rsp_func)(int port, uint32_t *payload);
 /* List of all Policy Engine level states */
 enum usb_pe_state {
 	/* Super States */
-	PE_PRS_FRS_SHARED,
-	PE_VDM_SEND_REQUEST,
+	PE_PRS_FRS_SHARED, /* pe-st0 */
+	PE_VDM_SEND_REQUEST, /* pe-st1 */
 
 	/* Normal States */
-	PE_SRC_STARTUP,
-	PE_SRC_DISCOVERY,
-	PE_SRC_SEND_CAPABILITIES,
-	PE_SRC_NEGOTIATE_CAPABILITY,
-	PE_SRC_TRANSITION_SUPPLY,
-	PE_SRC_READY,
-	PE_SRC_DISABLED,
-	PE_SRC_CAPABILITY_RESPONSE,
-	PE_SRC_HARD_RESET,
-	PE_SRC_HARD_RESET_RECEIVED,
-	PE_SRC_TRANSITION_TO_DEFAULT,
-	PE_SNK_STARTUP,
-	PE_SNK_DISCOVERY,
-	PE_SNK_WAIT_FOR_CAPABILITIES,
-	PE_SNK_EVALUATE_CAPABILITY,
-	PE_SNK_SELECT_CAPABILITY,
-	PE_SNK_READY,
-	PE_SNK_HARD_RESET,
-	PE_SNK_TRANSITION_TO_DEFAULT,
-	PE_SNK_GIVE_SINK_CAP,
-	PE_SNK_GET_SOURCE_CAP,
-	PE_SNK_TRANSITION_SINK,
-	PE_SEND_SOFT_RESET,
-	PE_SOFT_RESET,
-	PE_SEND_NOT_SUPPORTED,
-	PE_SRC_PING,
-	PE_DRS_EVALUATE_SWAP,
-	PE_DRS_CHANGE,
-	PE_DRS_SEND_SWAP,
-	PE_PRS_SRC_SNK_EVALUATE_SWAP,
-	PE_PRS_SRC_SNK_TRANSITION_TO_OFF,
-	PE_PRS_SRC_SNK_ASSERT_RD,
-	PE_PRS_SRC_SNK_WAIT_SOURCE_ON,
-	PE_PRS_SRC_SNK_SEND_SWAP,
-	PE_PRS_SNK_SRC_EVALUATE_SWAP,
-	PE_PRS_SNK_SRC_TRANSITION_TO_OFF,
-	PE_PRS_SNK_SRC_ASSERT_RP,
-	PE_PRS_SNK_SRC_SOURCE_ON,
-	PE_PRS_SNK_SRC_SEND_SWAP,
-	PE_VCS_EVALUATE_SWAP,
-	PE_VCS_SEND_SWAP,
-	PE_VCS_WAIT_FOR_VCONN_SWAP,
-	PE_VCS_TURN_ON_VCONN_SWAP,
-	PE_VCS_TURN_OFF_VCONN_SWAP,
-	PE_VCS_SEND_PS_RDY_SWAP,
-	PE_VDM_IDENTITY_REQUEST_CBL,
-	PE_INIT_PORT_VDM_IDENTITY_REQUEST,
-	PE_INIT_VDM_SVIDS_REQUEST,
-	PE_INIT_VDM_MODES_REQUEST,
-	PE_VDM_REQUEST_DPM,
-	PE_VDM_RESPONSE,
-	PE_HANDLE_CUSTOM_VDM_REQUEST,
-	PE_WAIT_FOR_ERROR_RECOVERY,
-	PE_BIST_TX,
-	PE_BIST_RX,
-	PE_DEU_SEND_ENTER_USB,
-	PE_DR_SNK_GET_SINK_CAP,
-	PE_DR_SNK_GIVE_SOURCE_CAP,
-	PE_DR_SRC_GET_SOURCE_CAP,
+	PE_SRC_STARTUP, /* pe-st2 */
+	PE_SRC_DISCOVERY, /* pe-st3 */
+	PE_SRC_SEND_CAPABILITIES, /* pe-st4 */
+	PE_SRC_NEGOTIATE_CAPABILITY, /* pe-st5 */
+	PE_SRC_TRANSITION_SUPPLY, /* pe-st6 */
+	PE_SRC_READY, /* pe-st7 */
+	PE_SRC_DISABLED, /* pe-st8 */
+	PE_SRC_CAPABILITY_RESPONSE, /* pe-st9 */
+	PE_SRC_HARD_RESET, /* pe-st10 */
+	PE_SRC_HARD_RESET_RECEIVED, /* pe-st11 */
+	PE_SRC_TRANSITION_TO_DEFAULT, /* pe-st12 */
+	PE_SNK_STARTUP, /* pe-st13 */
+	PE_SNK_DISCOVERY, /* pe-st14 */
+	PE_SNK_WAIT_FOR_CAPABILITIES, /* pe-st15 */
+	PE_SNK_EVALUATE_CAPABILITY, /* pe-st16 */
+	PE_SNK_SELECT_CAPABILITY, /* pe-st17 */
+	PE_SNK_READY, /* pe-st18 */
+	PE_SNK_HARD_RESET, /* pe-st19 */
+	PE_SNK_TRANSITION_TO_DEFAULT, /* pe-st20 */
+	PE_SNK_GIVE_SINK_CAP, /* pe-st21 */
+	PE_SNK_GET_SOURCE_CAP, /* pe-st22 */
+	PE_SNK_TRANSITION_SINK, /* pe-st23 */
+	PE_SEND_SOFT_RESET, /* pe-st24 */
+	PE_SOFT_RESET, /* pe-st25 */
+	PE_SEND_NOT_SUPPORTED, /* pe-st26 */
+	PE_SRC_PING, /* pe-st27 */
+	PE_DRS_EVALUATE_SWAP, /* pe-st28 */
+	PE_DRS_CHANGE, /* pe-st29 */
+	PE_DRS_SEND_SWAP, /* pe-st30 */
+	PE_PRS_SRC_SNK_EVALUATE_SWAP, /* pe-st31 */
+	PE_PRS_SRC_SNK_TRANSITION_TO_OFF, /* pe-st32 */
+	PE_PRS_SRC_SNK_ASSERT_RD, /* pe-st33 */
+	PE_PRS_SRC_SNK_WAIT_SOURCE_ON, /* pe-st34 */
+	PE_PRS_SRC_SNK_SEND_SWAP, /* pe-st35 */
+	PE_PRS_SNK_SRC_EVALUATE_SWAP, /* pe-st36 */
+	PE_PRS_SNK_SRC_TRANSITION_TO_OFF, /* pe-st37 */
+	PE_PRS_SNK_SRC_ASSERT_RP, /* pe-st38 */
+	PE_PRS_SNK_SRC_SOURCE_ON, /* pe-st39 */
+	PE_PRS_SNK_SRC_SEND_SWAP, /* pe-st40 */
+	PE_VCS_EVALUATE_SWAP, /* pe-st41 */
+	PE_VCS_SEND_SWAP, /* pe-st42 */
+	PE_VCS_WAIT_FOR_VCONN_SWAP, /* pe-st43 */
+	PE_VCS_TURN_ON_VCONN_SWAP, /* pe-st44 */
+	PE_VCS_TURN_OFF_VCONN_SWAP, /* pe-st45 */
+	PE_VCS_SEND_PS_RDY_SWAP, /* pe-st46 */
+	PE_VCS_CBL_SEND_SOFT_RESET, /* pe-st47 */
+	PE_VDM_IDENTITY_REQUEST_CBL, /* pe-st48 */
+	PE_INIT_PORT_VDM_IDENTITY_REQUEST, /* pe-st49 */
+	PE_INIT_VDM_SVIDS_REQUEST, /* pe-st50 */
+	PE_INIT_VDM_MODES_REQUEST, /* pe-st51 */
+	PE_VDM_REQUEST_DPM, /* pe-st52 */
+	PE_VDM_RESPONSE, /* pe-st53 */
+	PE_WAIT_FOR_ERROR_RECOVERY, /* pe-st54 */
+	PE_BIST_TX, /* pe-st55 */
+	PE_DEU_SEND_ENTER_USB, /* pe-st56 */
+	PE_DR_GET_SINK_CAP, /* pe-st57 */
+	PE_DR_SNK_GIVE_SOURCE_CAP, /* pe-st58 */
+	PE_DR_SRC_GET_SOURCE_CAP, /* pe-st59 */
 
 	/* PD3.0 only states below here*/
-	PE_FRS_SNK_SRC_START_AMS,
-	PE_GIVE_BATTERY_CAP,
-	PE_GIVE_BATTERY_STATUS,
-	PE_SEND_ALERT,
-	PE_SRC_CHUNK_RECEIVED,
-	PE_SNK_CHUNK_RECEIVED,
+	/* UFP Data Reset States */
+	PE_UDR_SEND_DATA_RESET, /* pe-st60 */
+	PE_UDR_DATA_RESET_RECEIVED, /* pe-st61 */
+	PE_UDR_TURN_OFF_VCONN, /* pe-st62 */
+	PE_UDR_SEND_PS_RDY, /* pe-st63 */
+	PE_UDR_WAIT_FOR_DATA_RESET_COMPLETE, /* pe-st64 */
+	/* DFP Data Reset States */
+	PE_DDR_SEND_DATA_RESET, /* pe-st65 */
+	PE_DDR_DATA_RESET_RECEIVED, /* pe-st66 */
+	PE_DDR_WAIT_FOR_VCONN_OFF, /* pe-st67 */
+	PE_DDR_PERFORM_DATA_RESET, /* pe-st68 */
+	PE_FRS_SNK_SRC_START_AMS, /* pe-st69 */
+	PE_GIVE_BATTERY_CAP, /* pe-st70 */
+	PE_GIVE_BATTERY_STATUS, /* pe-st71 */
+	PE_GIVE_STATUS, /* pe-st72 */
+	PE_SEND_ALERT, /* pe-st73 */
+	PE_ALERT_RECEIVED, /* pe-st74 */
+	PE_SRC_CHUNK_RECEIVED, /* pe-st75 */
+	PE_SNK_CHUNK_RECEIVED, /* pe-st76 */
+	PE_VCS_FORCE_VCONN, /* pe-st77 */
+	PE_GET_REVISION, /* pe-st78 */
+
+	/* EPR states */
+	PE_SNK_SEND_EPR_MODE_ENTRY,
+	PE_SNK_EPR_MODE_ENTRY_WAIT_FOR_RESPONSE,
+	PE_SNK_EPR_KEEP_ALIVE,
+	PE_SNK_SEND_EPR_MODE_EXIT,
+	PE_SNK_EPR_MODE_EXIT_RECEIVED,
 };
 
 /*
@@ -342,21 +328,18 @@ static const struct usb_state pe_states[];
  * If we can't print or the CONFIG_USB_PD_DEBUG_LEVEL is defined to be 0
  * then the DEBUG LABELS will be removed from the build.
  */
-#if defined(CONFIG_COMMON_RUNTIME) && \
-	(!defined(CONFIG_USB_PD_DEBUG_LEVEL) || \
-	 (CONFIG_USB_PD_DEBUG_LEVEL > 0))
+#if defined(CONFIG_COMMON_RUNTIME) && (!defined(CONFIG_USB_PD_DEBUG_LEVEL) || \
+				       (CONFIG_USB_PD_DEBUG_LEVEL > 0))
 #define USB_PD_DEBUG_LABELS
 #endif
 
-#ifdef USB_PD_DEBUG_LABELS
 /* List of human readable state names for console debugging */
-static const char * const pe_state_names[] = {
-	/* Super States */
+__maybe_unused static __const_data const char *const pe_state_names[] = {
+/* Super States */
 #ifdef CONFIG_USB_PD_REV30
 	[PE_PRS_FRS_SHARED] = "SS:PE_PRS_FRS_SHARED",
 #endif
 	[PE_VDM_SEND_REQUEST] = "SS:PE_VDM_Send_Request",
-	[PE_VDM_RESPONSE] = "SS:PE_VDM_Response",
 
 	/* Normal States */
 	[PE_SRC_STARTUP] = "PE_SRC_Startup",
@@ -405,44 +388,61 @@ static const char * const pe_state_names[] = {
 	[PE_VCS_TURN_ON_VCONN_SWAP] = "PE_VCS_Turn_On_Vconn_Swap",
 	[PE_VCS_TURN_OFF_VCONN_SWAP] = "PE_VCS_Turn_Off_Vconn_Swap",
 	[PE_VCS_SEND_PS_RDY_SWAP] = "PE_VCS_Send_Ps_Rdy_Swap",
+	[PE_VCS_CBL_SEND_SOFT_RESET] = "PE_VCS_CBL_Send_Soft_Reset",
 #endif
 	[PE_VDM_IDENTITY_REQUEST_CBL] = "PE_VDM_Identity_Request_Cbl",
 	[PE_INIT_PORT_VDM_IDENTITY_REQUEST] =
-					   "PE_INIT_PORT_VDM_Identity_Request",
+		"PE_INIT_PORT_VDM_Identity_Request",
 	[PE_INIT_VDM_SVIDS_REQUEST] = "PE_INIT_VDM_SVIDs_Request",
 	[PE_INIT_VDM_MODES_REQUEST] = "PE_INIT_VDM_Modes_Request",
 	[PE_VDM_REQUEST_DPM] = "PE_VDM_Request_DPM",
-	[PE_HANDLE_CUSTOM_VDM_REQUEST] = "PE_Handle_Custom_Vdm_Request",
+	[PE_VDM_RESPONSE] = "PE_VDM_Response",
 	[PE_WAIT_FOR_ERROR_RECOVERY] = "PE_Wait_For_Error_Recovery",
 	[PE_BIST_TX] = "PE_Bist_TX",
-	[PE_BIST_RX] = "PE_Bist_RX",
-	[PE_DEU_SEND_ENTER_USB]  = "PE_DEU_Send_Enter_USB",
-#ifdef CONFIG_USB_PD_FRS
-	[PE_DR_SNK_GET_SINK_CAP] = "PE_DR_SNK_Get_Sink_Cap",
-#endif
+	[PE_DEU_SEND_ENTER_USB] = "PE_DEU_Send_Enter_USB",
+	[PE_DR_GET_SINK_CAP] = "PE_DR_Get_Sink_Cap",
 	[PE_DR_SNK_GIVE_SOURCE_CAP] = "PE_DR_SNK_Give_Source_Cap",
 	[PE_DR_SRC_GET_SOURCE_CAP] = "PE_DR_SRC_Get_Source_Cap",
 
-	/* PD3.0 only states below here*/
+/* PD3.0 only states below here*/
 #ifdef CONFIG_USB_PD_REV30
 	[PE_FRS_SNK_SRC_START_AMS] = "PE_FRS_SNK_SRC_Start_Ams",
+	[PE_GET_REVISION] = "PE_Get_Revision",
 #ifdef CONFIG_USB_PD_EXTENDED_MESSAGES
 	[PE_GIVE_BATTERY_CAP] = "PE_Give_Battery_Cap",
 	[PE_GIVE_BATTERY_STATUS] = "PE_Give_Battery_Status",
+	[PE_GIVE_STATUS] = "PE_Give_Status",
 	[PE_SEND_ALERT] = "PE_Send_Alert",
+	[PE_ALERT_RECEIVED] = "PE_Alert_Received",
 #else
 	[PE_SRC_CHUNK_RECEIVED] = "PE_SRC_Chunk_Received",
 	[PE_SNK_CHUNK_RECEIVED] = "PE_SNK_Chunk_Received",
 #endif
+#ifdef CONFIG_USBC_VCONN
+	[PE_VCS_FORCE_VCONN] = "PE_VCS_Force_Vconn",
+#endif
+#ifdef CONFIG_USB_PD_DATA_RESET_MSG
+	[PE_UDR_SEND_DATA_RESET] = "PE_UDR_Send_Data_Reset",
+	[PE_UDR_DATA_RESET_RECEIVED] = "PE_UDR_Data_Reset_Received",
+	[PE_UDR_TURN_OFF_VCONN] = "PE_UDR_Turn_Off_VCONN",
+	[PE_UDR_SEND_PS_RDY] = "PE_UDR_Send_Ps_Rdy",
+	[PE_UDR_WAIT_FOR_DATA_RESET_COMPLETE] =
+		"PE_UDR_Wait_For_Data_Reset_Complete",
+	[PE_DDR_SEND_DATA_RESET] = "PE_DDR_Send_Data_Reset",
+	[PE_DDR_DATA_RESET_RECEIVED] = "PE_DDR_Data_Reset_Received",
+	[PE_DDR_WAIT_FOR_VCONN_OFF] = "PE_DDR_Wait_For_VCONN_Off",
+	[PE_DDR_PERFORM_DATA_RESET] = "PE_DDR_Perform_Data_Reset",
+#endif /* CONFIG_USB_PD_DATA_RESET_MSG */
+#ifdef CONFIG_USB_PD_EPR
+	[PE_SNK_SEND_EPR_MODE_ENTRY] = "PE_SNK_Send_EPR_Mode_Entry",
+	[PE_SNK_EPR_MODE_ENTRY_WAIT_FOR_RESPONSE] =
+		"PE_SNK_EPR_Mode_Entry_Wait_For_Response",
+	[PE_SNK_EPR_KEEP_ALIVE] = "PE_SNK_EPR_Keep_Alive",
+	[PE_SNK_SEND_EPR_MODE_EXIT] = "PE_SNK_Send_EPR_Mode_Exit",
+	[PE_SNK_EPR_MODE_EXIT_RECEIVED] = "PE_SNK_EPR_Mode_Exit_Received",
+#endif
 #endif /* CONFIG_USB_PD_REV30 */
 };
-#else
-/*
- * Here and below, ensure that invalid states don't link properly. This lets us
- * use guard code with IS_ENABLED instead of ifdefs and still save flash space.
- */
-STATIC_IF(USB_PD_DEBUG_LABELS) const char **pe_state_names;
-#endif
 
 #ifndef CONFIG_USBC_VCONN
 GEN_NOT_SUPPORTED(PE_VCS_EVALUATE_SWAP);
@@ -468,19 +468,24 @@ GEN_NOT_SUPPORTED(PE_SRC_CHUNK_RECEIVED);
 #define PE_SRC_CHUNK_RECEIVED PE_SRC_CHUNK_RECEIVED_NOT_SUPPORTED
 GEN_NOT_SUPPORTED(PE_SNK_CHUNK_RECEIVED);
 #define PE_SNK_CHUNK_RECEIVED PE_SNK_CHUNK_RECEIVED_NOT_SUPPORTED
-void pe_set_frs_enable(int port, int enable);
+GEN_NOT_SUPPORTED(PE_GET_REVISION);
+#define PE_GET_REVISION PE_GET_REVISION_NOT_SUPPORTED
+GEN_NOT_SUPPORTED(PE_ALERT_RECEIVED);
+#define PE_ALERT_RECEIVED PE_ALERT_RECEIVED_NOT_SUPPORTED
 #endif /* CONFIG_USB_PD_REV30 */
 
-#ifndef CONFIG_USB_PD_FRS
-GEN_NOT_SUPPORTED(PE_DR_SNK_GET_SINK_CAP);
-#define PE_DR_SNK_GET_SINK_CAP PE_DR_SNK_GET_SINK_CAP_NOT_SUPPORTED
-#endif /* CONFIG_USB_PD_FRS */
+#if !defined(CONFIG_USBC_VCONN) || !defined(CONFIG_USB_PD_REV30)
+GEN_NOT_SUPPORTED(PE_VCS_FORCE_VCONN);
+#define PE_VCS_FORCE_VCONN PE_VCS_FORCE_VCONN_NOT_SUPPORTED
+#endif
 
 #ifndef CONFIG_USB_PD_EXTENDED_MESSAGES
 GEN_NOT_SUPPORTED(PE_GIVE_BATTERY_CAP);
 #define PE_GIVE_BATTERY_CAP PE_GIVE_BATTERY_CAP_NOT_SUPPORTED
 GEN_NOT_SUPPORTED(PE_GIVE_BATTERY_STATUS);
 #define PE_GIVE_BATTERY_STATUS PE_GIVE_BATTERY_STATUS_NOT_SUPPORTED
+GEN_NOT_SUPPORTED(PE_GIVE_STATUS);
+#define PE_GIVE_STATUS PE_GIVE_STATUS_NOT_SUPPORTED
 GEN_NOT_SUPPORTED(PE_SEND_ALERT);
 #define PE_SEND_ALERT PE_SEND_ALERT_NOT_SUPPORTED
 #endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
@@ -492,15 +497,27 @@ GEN_NOT_SUPPORTED(PE_SNK_CHUNK_RECEIVED);
 #define PE_SNK_CHUNK_RECEIVED PE_SNK_CHUNK_RECEIVED_NOT_SUPPORTED
 #endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
 
-/*
- * This enum is used to implement a state machine consisting of at most
- * 3 states, inside a Policy Engine State.
- */
-enum sub_state {
-	PE_SUB0,
-	PE_SUB1,
-	PE_SUB2
-};
+#ifndef CONFIG_USB_PD_DATA_RESET_MSG
+GEN_NOT_SUPPORTED(PE_UDR_SEND_DATA_RESET);
+#define PE_UDR_SEND_DATA_RESET PE_UDR_SEND_DATA_RESET_NOT_SUPPORTED
+GEN_NOT_SUPPORTED(PE_UDR_DATA_RESET_RECEIVED);
+#define PE_UDR_DATA_RESET_RECEIVED PE_UDR_DATA_RESET_RECEIVED_NOT_SUPPORTED
+GEN_NOT_SUPPORTED(PE_UDR_TURN_OFF_VCONN);
+#define PE_UDR_TURN_OFF_VCONN PE_UDR_TURN_OFF_VCONN_NOT_SUPPORTED
+GEN_NOT_SUPPORTED(PE_UDR_SEND_PS_RDY);
+#define PE_UDR_SEND_PS_RDY PE_UDR_SEND_PS_RDY_NOT_SUPPORTED
+GEN_NOT_SUPPORTED(PE_UDR_WAIT_FOR_DATA_RESET_COMPLETE);
+#define PE_UDR_WAIT_FOR_DATA_RESET_COMPLETE \
+	PE_UDR_WAIT_FOR_DATA_RESET_COMPLETE_NOT_SUPPORTED
+GEN_NOT_SUPPORTED(PE_DDR_SEND_DATA_RESET);
+#define PE_DDR_SEND_DATA_RESET PE_DDR_SEND_DATA_RESET_NOT_SUPPORTED
+GEN_NOT_SUPPORTED(PE_DDR_DATA_RESET_RECEIVED);
+#define PE_DDR_DATA_RESET_RECEIVED PE_DDR_DATA_RESET_RECEIVED_NOT_SUPPORTED
+GEN_NOT_SUPPORTED(PE_DDR_WAIT_FOR_VCONN_OFF);
+#define PE_DDR_WAIT_FOR_VCONN_OFF PE_DDR_WAIT_FOR_VCONN_OFF_NOT_SUPPORTED
+GEN_NOT_SUPPORTED(PE_DDR_PERFORM_DATA_RESET);
+#define PE_DDR_PERFORM_DATA_RESET PE_DDR_PERFORM_DATA_RESET_NOT_SUPPORTED
+#endif /* CONFIG_USB_PD_DATA_RESET_MSG */
 
 static enum sm_local_state local_state[CONFIG_USB_PD_PORT_MAX_COUNT];
 
@@ -533,19 +550,22 @@ static enum sm_local_state local_state[CONFIG_USB_PD_PORT_MAX_COUNT];
  *                        what ever is needed to handle the Discard.
  */
 enum pe_msg_check {
-	PE_MSG_SEND_PENDING	= BIT(0),
-	PE_MSG_SENT		= BIT(1),
-	PE_MSG_DISCARDED	= BIT(2),
+	PE_MSG_SEND_PENDING = BIT(0),
+	PE_MSG_SENT = BIT(1),
+	PE_MSG_DISCARDED = BIT(2),
 
-	PE_MSG_SEND_COMPLETED	= BIT(3) | PE_MSG_SENT,
-	PE_MSG_DPM_DISCARDED	= BIT(4) | PE_MSG_DISCARDED,
+	PE_MSG_SEND_COMPLETED = BIT(3) | PE_MSG_SENT,
+	PE_MSG_DPM_DISCARDED = BIT(4) | PE_MSG_DISCARDED,
 };
 static void pe_sender_response_msg_entry(const int port);
 static enum pe_msg_check pe_sender_response_msg_run(const int port);
+static void pe_sender_response_msg_exit(const int port);
 
 /* Debug log level - higher number == more log */
 #ifdef CONFIG_USB_PD_DEBUG_LEVEL
 static const enum debug_level pe_debug_level = CONFIG_USB_PD_DEBUG_LEVEL;
+#elif defined(CONFIG_USB_PD_INITIAL_DEBUG_LEVEL)
+static enum debug_level pe_debug_level = CONFIG_USB_PD_INITIAL_DEBUG_LEVEL;
 #else
 static enum debug_level pe_debug_level = DEBUG_LEVEL_1;
 #endif
@@ -561,12 +581,10 @@ static struct policy_engine {
 	/* current port data role (DFP or UFP) */
 	enum pd_data_role data_role;
 	/* state machine flags */
-	uint32_t flags;
+	ATOMIC_DEFINE(flags_a, PE_FLAGS_COUNT);
 	/* Device Policy Manager Request */
-	uint32_t dpm_request;
+	atomic_t dpm_request;
 	uint32_t dpm_curr_request;
-	/* state timeout timer */
-	uint64_t timeout;
 	/* last requested voltage PDO index */
 	int requested_idx;
 
@@ -574,150 +592,32 @@ static struct policy_engine {
 	 * Port events - PD_STATUS_EVENT_* values
 	 * Set from PD task but may be cleared by host command
 	 */
-	uint32_t events;
+	atomic_t events;
 
 	/* port address where soft resets are sent */
-	enum tcpm_transmit_type soft_reset_sop;
+	enum tcpci_msg_type soft_reset_sop;
 
 	/* Current limit / voltage based on the last request message */
 	uint32_t curr_limit;
 	uint32_t supply_voltage;
 
-	/* state specific state machine variable */
-	enum sub_state sub;
-
 	/* PD_VDO_INVALID is used when there is an invalid VDO */
 	int32_t ama_vdo;
 	int32_t vpd_vdo;
 	/* Alternate mode discovery results */
 	struct pd_discovery discovery[DISCOVERY_TYPE_COUNT];
-	/* Active alternate modes */
-	struct partner_active_modes partner_amodes[AMODE_TYPE_COUNT];
 
 	/* Partner type to send */
-	enum tcpm_transmit_type tx_type;
+	enum tcpci_msg_type tx_type;
 
 	/* VDM - used to send information to shared VDM Request state */
 	uint32_t vdm_cnt;
 	uint32_t vdm_data[VDO_HDR_SIZE + VDO_MAX_SIZE];
 	uint8_t vdm_ack_min_data_objects;
 
-	/* Timers */
-
-	/*
-	 * The NoResponseTimer is used by the Policy Engine in a Source
-	 * to determine that its Port Partner is not responding after a
-	 * Hard Reset.
-	 */
-	uint64_t no_response_timer;
-
-	/*
-	 * Prior to a successful negotiation, a Source Shall use the
-	 * SourceCapabilityTimer to periodically send out a
-	 * Source_Capabilities Message.
-	 */
-	uint64_t source_cap_timer;
-
-	/*
-	 * This timer is started when a request for a new Capability has been
-	 * accepted and will timeout after PD_T_PS_TRANSITION if a PS_RDY
-	 * Message has not been received.
-	 */
-	uint64_t ps_transition_timer;
-
-	/*
-	 * This timer is used to ensure that a Message requesting a response
-	 * (e.g. Get_Source_Cap Message) is responded to within a bounded time
-	 * of PD_T_SENDER_RESPONSE.
-	 */
-	uint64_t sender_response_timer;
-
-	/*
-	 * This timer is used during an Explicit Contract when discovering
-	 * whether a Port Partner is PD Capable using SOP'.
-	 */
-	uint64_t discover_identity_timer;
-
-	/*
-	 * This timer is used in a Source to ensure that the Sink has had
-	 * sufficient time to process Hard Reset Signaling before turning
-	 * off its power supply to VBUS.
-	 */
-	uint64_t ps_hard_reset_timer;
-
-	/*
-	 * This timer is used to ensure that the time before the next Sink
-	 * Request Message, after a Wait Message has been received from the
-	 * Source in response to a Sink Request Message.
-	 */
-	uint64_t sink_request_timer;
-
-	/*
-	 * This timer tracks the time after receiving a Wait message in response
-	 * to a PR_Swap message.
-	 */
-	uint64_t pr_swap_wait_timer;
-
-	/*
-	 * This timer combines the PSSourceOffTimer and PSSourceOnTimer timers.
-	 * For PSSourceOffTimer, when this DRP device is currently acting as a
-	 * Sink, this timer times out on a PS_RDY Message during a Power Role
-	 * Swap sequence.
-	 *
-	 * For PSSourceOnTimer, when this DRP device is currently acting as a
-	 * Source that has just stopped sourcing power and is waiting to start
-	 * sinking power to timeout on a PS_RDY Message during a Power Role
-	 * Swap.
-	 */
-	uint64_t ps_source_timer;
-
-	/*
-	 * In BIST_TX mode, this timer is used by a UUT to ensure that a
-	 * Continuous BIST Mode (i.e. BIST Carrier Mode) is exited in a timely
-	 * fashion.
-	 *
-	 * In BIST_RX mode, this timer is used to give the port partner time
-	 * to respond.
-	 */
-	uint64_t bist_cont_mode_timer;
-	/*
-	 * This timer is used by the new Source, after a Power Role Swap or
-	 * Fast Role Swap, to ensure that it does not send Source_Capabilities
-	 * Message before the new Sink is ready to receive the
-	 * Source_Capabilities Message.
-	 */
-	uint64_t swap_source_start_timer;
-
-	/*
-	 * This timer is used by the Initiator’s Policy Engine to ensure that
-	 * a Structured VDM Command request needing a response (e.g. Discover
-	 * Identity Command request) is responded to within a bounded time of
-	 * tVDMSenderResponse.
-	 */
-	uint64_t vdm_response_timer;
-
-	/*
-	 * This timer is used during a VCONN Swap.
-	 */
-	uint64_t vconn_on_timer;
-
-	/*
-	 * For PD2.0, this timer is used to wait 400ms and add some
-	 * jitter of up to 100ms before sending a message.
-	 * NOTE: This timer is not part of the TypeC/PD spec.
-	 */
-	uint64_t wait_and_add_jitter_timer;
-
-	/*
-	 * PD 3.0, version 2.0, section 6.6.18.1: The ChunkingNotSupportedTimer
-	 * is used by a Source or Sink which does not support multi-chunk
-	 * Chunking but has received a Message Chunk. The
-	 * ChunkingNotSupportedTimer Shall be started when the last bit of the
-	 * EOP of a Message Chunk of a multi-chunk Message is received. The
-	 * Policy Engine Shall Not send its Not_Supported Message before the
-	 * ChunkingNotSupportedTimer expires.
-	 */
-	uint64_t chunking_not_supported_timer;
+	/* ADO - Used to store information about alert messages */
+	uint32_t ado;
+	mutex_t ado_lock;
 
 	/* Counters */
 
@@ -764,17 +664,20 @@ static struct policy_engine {
 
 	/* Last received source cap */
 	uint32_t src_caps[PDO_MAX_OBJECTS];
-	int src_cap_cnt;
+	int src_cap_cnt; /* -1 on error retrieving source caps */
 
-	/* Attached ChromeOS device id, RW hash, and current RO / RW image */
-	uint16_t dev_id;
-	uint32_t dev_rw_hash[PD_RW_HASH_SIZE/4];
-	enum ec_image current_image;
+	/* Last received sink cap */
+	uint32_t snk_caps[PDO_MAX_OBJECTS];
+	int snk_cap_cnt;
+
+	/* Last received Revision Message Data Object (RMDO) from the partner */
+	struct rmdo partner_rmdo;
 } pe[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 test_export_static enum usb_pe_state get_state_pe(const int port);
 test_export_static void set_state_pe(const int port,
 				     const enum usb_pe_state new_state);
+static void pe_set_dpm_curr_request(const int port, const int request);
 /*
  * The spec. revision is used to index into this array.
  *  PD 1.0 (VDO 1.0) - return VDM_VER10
@@ -787,12 +690,12 @@ static const uint8_t vdo_ver[] = {
 	[PD_REV30] = VDM_VER20,
 };
 
-int pd_get_rev(int port, enum tcpm_transmit_type type)
+int pd_get_rev(int port, enum tcpci_msg_type type)
 {
 	return prl_get_rev(port, type);
 }
 
-int pd_get_vdo_ver(int port, enum tcpm_transmit_type type)
+int pd_get_vdo_ver(int port, enum tcpci_msg_type type)
 {
 	enum pd_rev_type rev = prl_get_rev(port, type);
 
@@ -810,7 +713,15 @@ static void pe_set_ready_state(int port)
 		set_state_pe(port, PE_SNK_READY);
 }
 
-static inline void send_data_msg(int port, enum tcpm_transmit_type type,
+static void pe_set_hard_reset(int port)
+{
+	if (pe[port].power_role == PD_ROLE_SOURCE)
+		set_state_pe(port, PE_SRC_HARD_RESET);
+	else
+		set_state_pe(port, PE_SNK_HARD_RESET);
+}
+
+static inline void send_data_msg(int port, enum tcpci_msg_type type,
 				 enum pd_data_msg_type msg)
 {
 	/* Clear any previous TX status before sending a new message */
@@ -818,15 +729,15 @@ static inline void send_data_msg(int port, enum tcpm_transmit_type type,
 	prl_send_data_msg(port, type, msg);
 }
 
-static __maybe_unused inline void send_ext_data_msg(
-	int port, enum tcpm_transmit_type type, enum pd_ext_msg_type msg)
+static __maybe_unused inline void
+send_ext_data_msg(int port, enum tcpci_msg_type type, enum pd_ext_msg_type msg)
 {
 	/* Clear any previous TX status before sending a new message */
 	PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
 	prl_send_ext_data_msg(port, type, msg);
 }
 
-static inline void send_ctrl_msg(int port, enum tcpm_transmit_type type,
+static inline void send_ctrl_msg(int port, enum tcpci_msg_type type,
 				 enum pd_ctrl_msg_type msg)
 {
 	/* Clear any previous TX status before sending a new message */
@@ -834,6 +745,35 @@ static inline void send_ctrl_msg(int port, enum tcpm_transmit_type type,
 	prl_send_ctrl_msg(port, type, msg);
 }
 
+/* Set both the SOP' and SOP'' revisions to the given value */
+static void set_cable_rev(int port, enum pd_rev_type rev)
+{
+	prl_set_rev(port, TCPCI_MSG_SOP_PRIME, rev);
+	prl_set_rev(port, TCPCI_MSG_SOP_PRIME_PRIME, rev);
+}
+
+/* Initialize the cable revision based only on the partner SOP revision */
+static void init_cable_rev(int port)
+{
+	/*
+	 * If port partner runs PD 2.0, cable communication must
+	 * also be PD 2.0
+	 */
+	if (prl_get_rev(port, TCPCI_MSG_SOP) == PD_REV20) {
+		/*
+		 * If the cable supports PD 3.0, but the port partner supports
+		 * PD 2.0, redo the cable discover with PD 2.0
+		 */
+		if (prl_get_rev(port, TCPCI_MSG_SOP_PRIME) == PD_REV30 &&
+		    pd_get_identity_discovery(port, TCPCI_MSG_SOP_PRIME) ==
+			    PD_DISC_COMPLETE) {
+			pd_set_identity_discovery(port, TCPCI_MSG_SOP_PRIME,
+						  PD_DISC_NEEDED);
+		}
+		set_cable_rev(port, PD_REV20);
+	}
+}
+
 /* Compile-time insurance to ensure this code does not call into prl directly */
 #define prl_send_data_msg DO_NOT_USE
 #define prl_send_ext_data_msg DO_NOT_USE
@@ -841,13 +781,12 @@ static inline void send_ctrl_msg(int port, enum tcpm_transmit_type type,
 
 static void pe_init(int port)
 {
-	pe[port].flags = 0;
+	memset(&pe[port].flags_a, 0, sizeof(pe[port].flags_a));
 	pe[port].dpm_request = 0;
 	pe[port].dpm_curr_request = 0;
-	pe[port].source_cap_timer = TIMER_DISABLED;
-	pe[port].no_response_timer = TIMER_DISABLED;
+	pd_timer_disable_range(port, PE_TIMER_RANGE);
 	pe[port].data_role = pd_get_data_role(port);
-	pe[port].tx_type = TCPC_TX_INVALID;
+	pe[port].tx_type = TCPCI_MSG_INVALID;
 	pe[port].events = 0;
 
 	tc_pd_connection(port, 0);
@@ -863,6 +802,11 @@ int pe_is_running(int port)
 	return local_state[port] == SM_RUN;
 }
 
+bool pe_in_frs_mode(int port)
+{
+	return PE_CHK_FLAG(port, PE_FLAGS_FAST_ROLE_SWAP_PATH);
+}
+
 bool pe_in_local_ams(int port)
 {
 	return !!PE_CHK_FLAG(port, PE_FLAGS_LOCALLY_INITIATED_AMS);
@@ -881,11 +825,11 @@ void pe_run(int port, int evt, int en)
 	case SM_PAUSED:
 		if (!en)
 			break;
-		/* fall through */
+		__fallthrough;
 	case SM_INIT:
 		pe_init(port);
 		local_state[port] = SM_RUN;
-		/* fall through */
+		__fallthrough;
 	case SM_RUN:
 		if (!en) {
 			local_state[port] = SM_PAUSED;
@@ -897,6 +841,37 @@ void pe_run(int port, int evt, int en)
 			break;
 		}
 
+		/*
+		 * 8.3.3.3.8 PE_SNK_Hard_Reset State
+		 * The Policy Engine Shall transition to the PE_SNK_Hard_Reset
+		 * state from any state when:
+		 * - Hard Reset request from Device Policy Manager
+		 *
+		 * USB PD specification clearly states that we should go to
+		 * PE_SNK_Hard_Reset from ANY state (including states in which
+		 * port is source) when DPM requests that. This can lead to
+		 * execute Hard Reset path for sink when actually our power
+		 * role is source. In our implementation we will choose Hard
+		 * Reset path depending on current power role.
+		 */
+		if (PE_CHK_DPM_REQUEST(port, DPM_REQUEST_HARD_RESET_SEND)) {
+			/*
+			 * If a hard reset condition came up during FRS, we must
+			 * go into ErrorRecovery.  Performing a hard reset could
+			 * leave us assuming our own FRS Vbus is coming from the
+			 * partner and leave the port stuck as Attached.SNK
+			 */
+			if (pe_in_frs_mode(port)) {
+				PE_CLR_DPM_REQUEST(port,
+						   DPM_REQUEST_HARD_RESET_SEND);
+				set_state_pe(port, PE_WAIT_FOR_ERROR_RECOVERY);
+			} else {
+				pe_set_dpm_curr_request(
+					port, DPM_REQUEST_HARD_RESET_SEND);
+				pe_set_hard_reset(port);
+			}
+		}
+
 		/*
 		 * Check for Fast Role Swap signal
 		 * This is not a typical pattern for adding state changes.
@@ -905,7 +880,7 @@ void pe_run(int port, int evt, int en)
 		 * make sure to handle it immediately.
 		 */
 		if (IS_ENABLED(CONFIG_USB_PD_REV30) &&
-		PE_CHK_FLAG(port, PE_FLAGS_FAST_ROLE_SWAP_SIGNALED)) {
+		    PE_CHK_FLAG(port, PE_FLAGS_FAST_ROLE_SWAP_SIGNALED)) {
 			PE_CLR_FLAG(port, PE_FLAGS_FAST_ROLE_SWAP_SIGNALED);
 			set_state_pe(port, PE_FRS_SNK_SRC_START_AMS);
 		}
@@ -927,6 +902,7 @@ void pe_message_received(int port)
 	assert(port == TASK_ID_TO_PD_PORT(task_get_current()));
 
 	PE_SET_FLAG(port, PE_FLAGS_MSG_RECEIVED);
+	task_wake(PD_PORT_TO_TASK_ID(port));
 }
 
 void pe_hard_reset_sent(int port)
@@ -942,6 +918,15 @@ void pe_got_hard_reset(int port)
 	/* This should only be called from the PD task */
 	assert(port == TASK_ID_TO_PD_PORT(task_get_current()));
 
+	/*
+	 * If we're in the middle of an FRS, any error should cause us to follow
+	 * the ErrorRecovery path
+	 */
+	if (pe_in_frs_mode(port)) {
+		set_state_pe(port, PE_WAIT_FOR_ERROR_RECOVERY);
+		return;
+	}
+
 	/*
 	 * Transition from any state to the PE_SRC_Hard_Reset_Received or
 	 *  PE_SNK_Transition_to_default state when:
@@ -949,6 +934,9 @@ void pe_got_hard_reset(int port)
 	 */
 	pe[port].power_role = pd_get_power_role(port);
 
+	/* Exit BIST Test mode, in case the TCPC entered it. */
+	tcpc_set_bist_test_mode(port, false);
+
 	if (pe[port].power_role == PD_ROLE_SOURCE)
 		set_state_pe(port, PE_SRC_HARD_RESET_RECEIVED);
 	else
@@ -962,12 +950,20 @@ void pe_got_hard_reset(int port)
  * Called by the handler that detects the FRS signal in order to
  * switch PE states to complete the FRS that the hardware has
  * started.
+ *
+ * If the PE is not running, generate an error recovery to turn off
+ * Vbus and get the port back into a known state.
  */
 void pd_got_frs_signal(int port)
 {
-	PE_SET_FLAG(port, PE_FLAGS_FAST_ROLE_SWAP_SIGNALED);
-	task_set_event(PD_PORT_TO_TASK_ID(port), TASK_EVENT_WAKE, 0);
+	if (pe_is_running(port))
+		PE_SET_FLAG(port, PE_FLAGS_FAST_ROLE_SWAP_SIGNALED);
+	else
+		pd_set_error_recovery(port);
+
+	task_wake(PD_PORT_TO_TASK_ID(port));
 }
+#endif /* CONFIG_USB_PD_REV30 */
 
 /*
  * PE_Set_FRS_Enable
@@ -982,26 +978,33 @@ void pd_got_frs_signal(int port)
  */
 static void pe_set_frs_enable(int port, int enable)
 {
+	int current = PE_CHK_FLAG(port, PE_FLAGS_FAST_ROLE_SWAP_ENABLED);
+
 	/* This should only be called from the PD task */
-	assert(port == TASK_ID_TO_PD_PORT(task_get_current()));
+	if (!IS_ENABLED(TEST_BUILD))
+		assert(port == TASK_ID_TO_PD_PORT(task_get_current()));
+
+	if (!IS_ENABLED(CONFIG_USB_PD_FRS) || !IS_ENABLED(CONFIG_USB_PD_REV30))
+		return;
 
-	if (IS_ENABLED(CONFIG_USB_PD_FRS)) {
-		int current = PE_CHK_FLAG(port,
-					  PE_FLAGS_FAST_ROLE_SWAP_ENABLED);
+	/* Request an FRS change, only if the state has changed */
+	if (!!current == !!enable)
+		return;
 
-		/* Request an FRS change, only if the state has changed */
-		if (!!current != !!enable) {
-			pd_set_frs_enable(port, enable);
-			if (enable)
-				PE_SET_FLAG(port,
-					    PE_FLAGS_FAST_ROLE_SWAP_ENABLED);
-			else
-				PE_CLR_FLAG(port,
-					    PE_FLAGS_FAST_ROLE_SWAP_ENABLED);
-		}
+	pd_set_frs_enable(port, enable);
+	if (enable) {
+		int curr_limit = *pd_get_snk_caps(port) &
+				 PDO_FIXED_FRS_CURR_MASK;
+
+		typec_select_src_current_limit_rp(
+			port, curr_limit == PDO_FIXED_FRS_CURR_3A0_AT_5V ?
+				      TYPEC_RP_3A0 :
+				      TYPEC_RP_1A5);
+		PE_SET_FLAG(port, PE_FLAGS_FAST_ROLE_SWAP_ENABLED);
+	} else {
+		PE_CLR_FLAG(port, PE_FLAGS_FAST_ROLE_SWAP_ENABLED);
 	}
 }
-#endif /* CONFIG_USB_PD_REV30 */
 
 void pe_set_explicit_contract(int port)
 {
@@ -1014,22 +1017,18 @@ void pe_set_explicit_contract(int port)
 
 void pe_invalidate_explicit_contract(int port)
 {
-	if (IS_ENABLED(CONFIG_USB_PD_REV30))
-		pe_set_frs_enable(port, 0);
+	pe_set_frs_enable(port, 0);
 
 	PE_CLR_FLAG(port, PE_FLAGS_EXPLICIT_CONTRACT);
 
-	/* Set Rp for current limit */
-	if (IS_ENABLED(CONFIG_USB_PD_REV30))
+	/* Set Rp for current limit if still attached */
+	if (IS_ENABLED(CONFIG_USB_PD_REV30) && pd_is_connected(port))
 		typec_update_cc(port);
 }
 
-void pe_notify_event(int port, uint32_t event_mask)
+void pd_notify_event(int port, uint32_t event_mask)
 {
-	/* Events may only be set from the PD task */
-	assert(port == TASK_ID_TO_PD_PORT(task_get_current()));
-
-	deprecated_atomic_or(&pe[port].events, event_mask);
+	atomic_or(&pe[port].events, event_mask);
 
 	/* Notify the host that new events are available to read */
 	pd_send_host_event(PD_EVENT_TYPEC);
@@ -1037,7 +1036,7 @@ void pe_notify_event(int port, uint32_t event_mask)
 
 void pd_clear_events(int port, uint32_t clear_mask)
 {
-	deprecated_atomic_clear_bits(&pe[port].events, clear_mask);
+	atomic_clear_bits(&pe[port].events, clear_mask);
 }
 
 uint32_t pd_get_events(int port)
@@ -1045,6 +1044,45 @@ uint32_t pd_get_events(int port)
 	return pe[port].events;
 }
 
+void pe_set_snk_caps(int port, int cnt, uint32_t *snk_caps)
+{
+	pe[port].snk_cap_cnt = cnt;
+
+	memcpy(pe[port].snk_caps, snk_caps, sizeof(uint32_t) * cnt);
+}
+
+const uint32_t *const pd_get_snk_caps(int port)
+{
+	return pe[port].snk_caps;
+}
+
+uint8_t pd_get_snk_cap_cnt(int port)
+{
+	return pe[port].snk_cap_cnt;
+}
+
+uint32_t pd_get_requested_voltage(int port)
+{
+	return pe[port].supply_voltage;
+}
+
+uint32_t pd_get_requested_current(int port)
+{
+	return pe[port].curr_limit;
+}
+
+#ifdef CONFIG_USB_PD_EPR
+/**
+ * Return true if we're in an SPR contract. Note that before exiting EPR mode,
+ * port partners are required first to drop to SPR. Thus, we can be still in
+ * EPR mode (with a SPR contract).
+ */
+static int pe_in_spr_contract(int port)
+{
+	return pd_get_requested_voltage(port) <= PD_MAX_SPR_VOLTAGE;
+}
+#endif /* CONFIG_USB_PD_EPR */
+
 /*
  * Determine if this port may communicate with the cable plug.
  *
@@ -1063,14 +1101,14 @@ static bool pe_can_send_sop_prime(int port)
 {
 	if (IS_ENABLED(CONFIG_USBC_VCONN)) {
 		if (PE_CHK_FLAG(port, PE_FLAGS_EXPLICIT_CONTRACT)) {
-			if (prl_get_rev(port, TCPC_TX_SOP) == PD_REV20)
+			if (prl_get_rev(port, TCPCI_MSG_SOP) == PD_REV20)
 				return tc_is_vconn_src(port) &&
-					pe[port].data_role == PD_ROLE_DFP;
+				       pe[port].data_role == PD_ROLE_DFP;
 			else
 				return tc_is_vconn_src(port);
 		} else {
 			return tc_is_vconn_src(port) &&
-				pe[port].power_role == PD_ROLE_SOURCE;
+			       pe[port].power_role == PD_ROLE_SOURCE;
 		}
 	} else {
 		return false;
@@ -1093,7 +1131,7 @@ static bool pe_can_send_sop_prime(int port)
 static bool pe_can_send_sop_vdm(int port, int vdm_cmd)
 {
 	if (PE_CHK_FLAG(port, PE_FLAGS_EXPLICIT_CONTRACT)) {
-		if (prl_get_rev(port, TCPC_TX_SOP) == PD_REV20) {
+		if (prl_get_rev(port, TCPCI_MSG_SOP) == PD_REV20) {
 			if (pe[port].data_role == PD_ROLE_UFP &&
 			    vdm_cmd != CMD_ATTENTION) {
 				return false;
@@ -1111,7 +1149,47 @@ static bool pe_can_send_sop_vdm(int port, int vdm_cmd)
 	return false;
 }
 
-static void pe_send_soft_reset(const int port, enum tcpm_transmit_type type)
+static const uint32_t pd_get_fixed_pdo(int port)
+{
+	return pe[port].src_caps[0];
+}
+
+bool pe_snk_in_epr_mode(int port)
+{
+	return PE_CHK_FLAG(port, PE_FLAGS_IN_EPR);
+}
+
+void pe_snk_epr_explicit_exit(int port)
+{
+	PE_SET_FLAG(port, PE_FLAGS_EPR_EXPLICIT_EXIT);
+}
+
+bool pe_snk_can_enter_epr_mode(int port)
+{
+	/*
+	 * 6.4.10.1 of USB PD R3.1 V1.6
+	 *
+	 * 1. A Sink Shall Not be Connected to the Source through a CT-VPD.
+	 * 2. The Source and Sink Shall be in an SPR Explicit Contract.
+	 * 3. The EPR Mode capable bit Shall have been set in the 5V fixed PDO
+	 *    in the last Source_Capabilities Message the Sink received.
+	 * 4. The EPR Mode capable bit Shall have been set in the RDO in the
+	 *    last Request Message the Source received.
+	 */
+	if (is_vpd_ct_supported(port)) {
+		return false;
+	}
+
+	if (!pe_is_explicit_contract(port))
+		return false;
+
+	if (!(pd_get_fixed_pdo(port) & PDO_FIXED_EPR_MODE_CAPABLE))
+		return false;
+
+	return true;
+}
+
+static void pe_send_soft_reset(const int port, enum tcpci_msg_type type)
 {
 	pe[port].soft_reset_sop = type;
 	set_state_pe(port, PE_SEND_SOFT_RESET);
@@ -1129,20 +1207,54 @@ void pe_report_discard(int port)
 	/* TODO(b/157228506): Ensure all states are checking discard */
 }
 
-void pe_report_error(int port, enum pe_error e, enum tcpm_transmit_type type)
+/*
+ * Utility function to check for an outgoing message discard during states which
+ * send a message as a part of an AMS and wait for the transmit to complete.
+ * Note these states should not be power transitioning.
+ *
+ * In these states, discard due to an incoming message is a protocol error.
+ */
+static bool pe_check_outgoing_discard(int port)
+{
+	/*
+	 * On outgoing discard, soft reset with SOP* of incoming message
+	 *
+	 * See Table 6-65 Response to an incoming Message (except VDM) in PD 3.0
+	 * Version 2.0 Specification.
+	 */
+	if (PE_CHK_FLAG(port, PE_FLAGS_MSG_DISCARDED) &&
+	    PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
+		enum tcpci_msg_type sop =
+			PD_HEADER_GET_SOP(rx_emsg[port].header);
+
+		PE_CLR_FLAG(port, PE_FLAGS_MSG_DISCARDED);
+		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
+
+		pe_send_soft_reset(port, sop);
+		return true;
+	}
+
+	return false;
+}
+
+void pe_report_error(int port, enum pe_error e, enum tcpci_msg_type type)
 {
 	/* This should only be called from the PD task */
 	assert(port == TASK_ID_TO_PD_PORT(task_get_current()));
 
+	/*
+	 * If there is a timeout error while waiting for a chunk of a chunked
+	 * message, there is no requirement to trigger a soft reset.
+	 */
+	if (e == ERR_RCH_CHUNK_WAIT_TIMEOUT)
+		return;
+
 	/*
 	 * Generate Hard Reset if Protocol Error occurred
 	 * while in PE_Send_Soft_Reset state.
 	 */
 	if (get_state_pe(port) == PE_SEND_SOFT_RESET) {
-		if (pe[port].power_role == PD_ROLE_SINK)
-			set_state_pe(port, PE_SNK_HARD_RESET);
-		else
-			set_state_pe(port, PE_SRC_HARD_RESET);
+		pe_set_hard_reset(port);
 		return;
 	}
 
@@ -1155,15 +1267,28 @@ void pe_report_error(int port, enum pe_error e, enum tcpm_transmit_type type)
 	 * TODO(b/150774779): TCPMv2: Improve pe_error documentation
 	 */
 	if ((get_state_pe(port) == PE_SRC_SEND_CAPABILITIES ||
-			get_state_pe(port) == PE_SRC_TRANSITION_SUPPLY ||
-			get_state_pe(port) == PE_PRS_SRC_SNK_WAIT_SOURCE_ON ||
-			get_state_pe(port) == PE_SRC_DISABLED ||
-			get_state_pe(port) == PE_SRC_DISCOVERY ||
-			get_state_pe(port) == PE_VDM_IDENTITY_REQUEST_CBL) ||
-			(IS_ENABLED(CONFIG_USBC_VCONN) &&
-				get_state_pe(port) == PE_VCS_SEND_PS_RDY_SWAP)
-			) {
+	     get_state_pe(port) == PE_SRC_TRANSITION_SUPPLY ||
+	     get_state_pe(port) == PE_PRS_SNK_SRC_EVALUATE_SWAP ||
+	     get_state_pe(port) == PE_PRS_SNK_SRC_SOURCE_ON ||
+	     get_state_pe(port) == PE_PRS_SRC_SNK_WAIT_SOURCE_ON ||
+	     get_state_pe(port) == PE_SRC_DISABLED ||
+	     get_state_pe(port) == PE_SRC_DISCOVERY ||
+	     get_state_pe(port) == PE_VCS_CBL_SEND_SOFT_RESET ||
+	     get_state_pe(port) == PE_VDM_IDENTITY_REQUEST_CBL) ||
+	    (IS_ENABLED(CONFIG_USB_PD_DATA_RESET_MSG) &&
+	     (get_state_pe(port) == PE_UDR_SEND_DATA_RESET ||
+	      get_state_pe(port) == PE_UDR_DATA_RESET_RECEIVED ||
+	      get_state_pe(port) == PE_UDR_TURN_OFF_VCONN ||
+	      get_state_pe(port) == PE_UDR_SEND_PS_RDY ||
+	      get_state_pe(port) == PE_UDR_WAIT_FOR_DATA_RESET_COMPLETE ||
+	      get_state_pe(port) == PE_DDR_SEND_DATA_RESET ||
+	      get_state_pe(port) == PE_DDR_DATA_RESET_RECEIVED ||
+	      get_state_pe(port) == PE_DDR_WAIT_FOR_VCONN_OFF ||
+	      get_state_pe(port) == PE_DDR_PERFORM_DATA_RESET)) ||
+	    (pe_in_frs_mode(port) &&
+	     get_state_pe(port) == PE_PRS_SNK_SRC_SEND_SWAP)) {
 		PE_SET_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
+		task_wake(PD_PORT_TO_TASK_ID(port));
 		return;
 	}
 
@@ -1171,14 +1296,23 @@ void pe_report_error(int port, enum pe_error e, enum tcpm_transmit_type type)
 	 * See section 8.3.3.4.1.1 PE_SRC_Send_Soft_Reset State:
 	 *
 	 * The PE_Send_Soft_Reset state shall be entered from
-	 * any state when a Protocol Error is detected by
-	 * Protocol Layer during a Non-Interruptible AMS or when
-	 * Message has not been sent after retries. When an explicit
-	 * contract is not in effect.  Otherwise go to PE_Snk/Src_Ready
-	 */
-	if (!PE_CHK_FLAG(port, PE_FLAGS_EXPLICIT_CONTRACT) &&
-			(!PE_CHK_FLAG(port, PE_FLAGS_INTERRUPTIBLE_AMS)
-			 || (e == ERR_TCH_XMIT))) {
+	 * any state when
+	 * * A Protocol Error is detected by Protocol Layer during a
+	 *   Non-Interruptible AMS or
+	 * * A message has not been sent after retries or
+	 * * When not in an explicit contract and
+	 *   * Protocol Errors occurred on SOP during an Interruptible AMS or
+	 *   * Protocol Errors occurred on SOP during any AMS where the first
+	 *     Message in the sequence has not yet been sent i.e. an unexpected
+	 *     Message is received instead of the expected GoodCRC Message
+	 *     response.
+	 */
+	/* All error types besides transmit errors are Protocol Errors. */
+	if ((e != ERR_TCH_XMIT &&
+	     !PE_CHK_FLAG(port, PE_FLAGS_INTERRUPTIBLE_AMS)) ||
+	    e == ERR_TCH_XMIT ||
+	    (!PE_CHK_FLAG(port, PE_FLAGS_EXPLICIT_CONTRACT) &&
+	     type == TCPCI_MSG_SOP)) {
 		pe_send_soft_reset(port, type);
 	}
 	/*
@@ -1198,8 +1332,70 @@ void pe_got_soft_reset(int port)
 	/*
 	 * The PE_SRC_Soft_Reset state Shall be entered from any state when a
 	 * Soft_Reset Message is received from the Protocol Layer.
+	 *
+	 * However, if we're in the middle of an FRS sequence, we need to go to
+	 * ErrorRecovery instead.
+	 */
+	set_state_pe(port, pe_in_frs_mode(port) ? PE_WAIT_FOR_ERROR_RECOVERY :
+						  PE_SOFT_RESET);
+}
+
+__overridable bool pd_can_charge_from_device(int port, const int pdo_cnt,
+					     const uint32_t *pdos)
+{
+	/*
+	 * Don't attempt to charge from a device we have no SrcCaps from. Or, if
+	 * drp_state is FORCE_SOURCE then don't attempt a PRS.
+	 */
+	if (pdo_cnt == 0 || pd_get_dual_role(port) == PD_DRP_FORCE_SOURCE)
+		return false;
+
+	/*
+	 * Treat device as a dedicated charger (meaning we should charge
+	 * from it) if:
+	 *   - it does not support power swap, or
+	 *   - it is unconstrained power, or
+	 *   - it presents at least 27 W of available power
 	 */
-	set_state_pe(port, PE_SOFT_RESET);
+
+	/* Unconstrained Power or NOT Dual Role Power we can charge from */
+	if (pdos[0] & PDO_FIXED_UNCONSTRAINED ||
+	    (pdos[0] & PDO_FIXED_DUAL_ROLE) == 0)
+		return true;
+
+	/* [virtual] allow_list */
+	if (IS_ENABLED(CONFIG_CHARGE_MANAGER)) {
+		uint32_t max_ma, max_mv, max_pdo, max_mw, unused;
+
+		/*
+		 * Get max power that the partner offers (not necessarily what
+		 * this board will request)
+		 */
+		pd_find_pdo_index(pdo_cnt, pdos, pd_get_max_voltage(),
+				  &max_pdo);
+		pd_extract_pdo_power(max_pdo, &max_ma, &max_mv, &unused);
+		max_mw = max_ma * max_mv / 1000;
+
+		if (max_mw >= PD_DRP_CHARGE_POWER_MIN)
+			return true;
+	}
+	return false;
+}
+
+void pd_resume_check_pr_swap_needed(int port)
+{
+	/*
+	 * Explicit contract, current power role of SNK, the device
+	 * indicates it should not power us, and device isn't selected
+	 * as the charging port (ex. through the GUI) then trigger a PR_Swap
+	 */
+	if (pe_is_explicit_contract(port) &&
+	    pd_get_power_role(port) == PD_ROLE_SINK &&
+	    !pd_can_charge_from_device(port, pd_get_src_cap_cnt(port),
+				       pd_get_src_caps(port)) &&
+	    (!IS_ENABLED(CONFIG_CHARGE_MANAGER) ||
+	     charge_manager_get_active_charge_port() != port))
+		pd_dpm_request(port, DPM_REQUEST_PR_SWAP);
 }
 
 void pd_dpm_request(int port, enum pd_dpm_request req)
@@ -1229,29 +1425,49 @@ void pe_message_sent(int port)
 	assert(port == TASK_ID_TO_PD_PORT(task_get_current()));
 
 	PE_SET_FLAG(port, PE_FLAGS_TX_COMPLETE);
+	task_wake(PD_PORT_TO_TASK_ID(port));
 }
 
 void pd_send_vdm(int port, uint32_t vid, int cmd, const uint32_t *data,
-						int count)
+		 int count)
 {
 	/* Copy VDM Header */
-	pe[port].vdm_data[0] = VDO(vid, ((vid & USB_SID_PD) == USB_SID_PD) ?
-				1 : (PD_VDO_CMD(cmd) <= CMD_ATTENTION),
-				VDO_SVDM_VERS(pd_get_vdo_ver(port, TCPC_TX_SOP))
-				| cmd);
+	pe[port].vdm_data[0] =
+		VDO(vid,
+		    ((vid & USB_SID_PD) == USB_SID_PD) ?
+			    1 :
+			    (PD_VDO_CMD(cmd) <= CMD_ATTENTION),
+		    VDO_SVDM_VERS(pd_get_vdo_ver(port, TCPCI_MSG_SOP)) | cmd);
 
-	/* Copy Data after VDM Header */
-	memcpy((pe[port].vdm_data + 1), data, count);
+	/*
+	 * Copy VDOs after the VDM Header. Note that the count refers to VDO
+	 * count.
+	 */
+	memcpy((pe[port].vdm_data + 1), data, count * sizeof(uint32_t));
 
 	pe[port].vdm_cnt = count + 1;
 
+	/*
+	 * The PE transmit routine assumes that tx_type was set already. Note,
+	 * that this function is likely called from outside the PD task.
+	 * (b/180465870)
+	 */
+	pe[port].tx_type = TCPCI_MSG_SOP;
+	pd_dpm_request(port, DPM_REQUEST_VDM);
+
 	task_wake(PD_PORT_TO_TASK_ID(port));
 }
 
-static void pe_handle_detach(void)
+#ifdef TEST_BUILD
+/*
+ * Allow unit tests to access this function to clear internal state data between
+ * runs
+ */
+void pe_clear_port_data(int port)
+#else
+static void pe_clear_port_data(int port)
+#endif /* TEST_BUILD */
 {
-	const int port = TASK_ID_TO_PD_PORT(task_get_current());
-
 	/*
 	 * PD 3.0 Section 8.3.3.3.8
 	 * Note: The HardResetCounter is reset on a power cycle or Detach.
@@ -1260,14 +1476,110 @@ static void pe_handle_detach(void)
 
 	/* Reset port events */
 	pd_clear_events(port, GENMASK(31, 0));
-}
-DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, pe_handle_detach, HOOK_PRIO_DEFAULT);
 
-/*
- * Private functions
+	/* But then set disconnected event */
+	pd_notify_event(port, PD_STATUS_EVENT_DISCONNECTED);
+
+	/* Tell Policy Engine to invalidate the explicit contract */
+	pe_invalidate_explicit_contract(port);
+
+	/*
+	 * Saved Source and Sink Capabilities are no longer valid on disconnect
+	 */
+	pd_set_src_caps(port, 0, NULL);
+	pe_set_snk_caps(port, 0, NULL);
+
+	/*
+	 * Saved Revision responses are no longer valid on disconnect
+	 */
+	pe[port].partner_rmdo.reserved = 0;
+	pe[port].partner_rmdo.minor_ver = 0;
+	pe[port].partner_rmdo.major_ver = 0;
+	pe[port].partner_rmdo.minor_rev = 0;
+	pe[port].partner_rmdo.major_rev = 0;
+
+	/* Clear any stored discovery data, but leave modes for alt mode exit */
+	pd_dfp_discovery_init(port);
+
+	/* Clear any pending alerts */
+	pe_clear_ado(port);
+
+	dpm_remove_sink(port);
+	dpm_remove_source(port);
+	dpm_init(port);
+
+	/* Exit BIST Test mode, in case the TCPC entered it. */
+	tcpc_set_bist_test_mode(port, false);
+}
+
+int pe_set_ado(int port, uint32_t data)
+{
+	/* return busy error if unable to set ado */
+	int ret = EC_ERROR_BUSY;
+
+	mutex_lock(&pe[port].ado_lock);
+	if (pe[port].ado == 0x0) {
+		pe[port].ado = data;
+		ret = EC_SUCCESS;
+	}
+
+	mutex_unlock(&pe[port].ado_lock);
+	return ret;
+}
+
+void pe_clear_ado(int port)
+{
+	mutex_lock(&pe[port].ado_lock);
+	pe[port].ado = 0x0;
+	mutex_unlock(&pe[port].ado_lock);
+}
+
+struct rmdo pd_get_partner_rmdo(int port)
+{
+	return pe[port].partner_rmdo;
+}
+
+static void pe_handle_detach(void)
+{
+	const int port = TASK_ID_TO_PD_PORT(task_get_current());
+
+	pe_clear_port_data(port);
+}
+DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, pe_handle_detach, HOOK_PRIO_DEFAULT);
+
+#ifdef CONFIG_USB_PD_RESET_MIN_BATT_SOC
+static void pe_update_waiting_batt_flag(void)
+{
+	int i;
+	int batt_soc = usb_get_battery_soc();
+
+	if (batt_soc < CONFIG_USB_PD_RESET_MIN_BATT_SOC ||
+	    battery_get_disconnect_state() != BATTERY_NOT_DISCONNECTED)
+		return;
+
+	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+		if (PE_CHK_FLAG(i, PE_FLAGS_SNK_WAITING_BATT)) {
+			/*
+			 * Battery has gained sufficient charge to kick off PD
+			 * negotiation and withstand a hard reset. Clear the
+			 * flag and perform Hard Reset.
+			 */
+			PE_CLR_FLAG(i, PE_FLAGS_SNK_WAITING_BATT);
+			CPRINTS("C%d: Battery has enough charge (%d%%) "
+				"to withstand a hard reset",
+				i, batt_soc);
+			pd_dpm_request(i, DPM_REQUEST_HARD_RESET_SEND);
+		}
+	}
+}
+DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, pe_update_waiting_batt_flag,
+	     HOOK_PRIO_DEFAULT);
+#endif
+
+/*
+ * Private functions
  */
-static void pe_set_dpm_curr_request(const int port,
-				    const int request)
+static void pe_set_dpm_curr_request(const int port, const int request)
 {
 	PE_CLR_DPM_REQUEST(port, request);
 	pe[port].dpm_curr_request = request;
@@ -1286,57 +1598,56 @@ test_export_static enum usb_pe_state get_state_pe(const int port)
 	return pe[port].ctx.current - &pe_states[0];
 }
 
+/*
+ * Handle common DPM requests to both source and sink.
+ *
+ * Note: it is assumed the calling state set PE_FLAGS_LOCALLY_INITIATED_AMS
+ *
+ * Returns true if state was set and calling run state should now return.
+ */
 static bool common_src_snk_dpm_requests(int port)
 {
-	if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES) &&
-			PE_CHK_DPM_REQUEST(port, DPM_REQUEST_SEND_ALERT)) {
-		pe_set_dpm_curr_request(port, DPM_REQUEST_SEND_ALERT);
-		set_state_pe(port, PE_SEND_ALERT);
-		return true;
-	} else if (IS_ENABLED(CONFIG_USBC_VCONN) &&
-			PE_CHK_DPM_REQUEST(port, DPM_REQUEST_VCONN_SWAP)) {
+	if (IS_ENABLED(CONFIG_USBC_VCONN) &&
+	    PE_CHK_DPM_REQUEST(port, DPM_REQUEST_VCONN_SWAP)) {
 		pe_set_dpm_curr_request(port, DPM_REQUEST_VCONN_SWAP);
 		set_state_pe(port, PE_VCS_SEND_SWAP);
 		return true;
-	} else if (PE_CHK_DPM_REQUEST(port,
-					DPM_REQUEST_BIST_RX)) {
-		pe_set_dpm_curr_request(port, DPM_REQUEST_BIST_RX);
-		set_state_pe(port, PE_BIST_RX);
-		return true;
-	} else if (PE_CHK_DPM_REQUEST(port,
-					DPM_REQUEST_BIST_TX)) {
+	} else if (PE_CHK_DPM_REQUEST(port, DPM_REQUEST_BIST_TX)) {
 		pe_set_dpm_curr_request(port, DPM_REQUEST_BIST_TX);
 		set_state_pe(port, PE_BIST_TX);
 		return true;
-	} else if (PE_CHK_DPM_REQUEST(port,
-					DPM_REQUEST_SNK_STARTUP)) {
+	} else if (PE_CHK_DPM_REQUEST(port, DPM_REQUEST_SNK_STARTUP)) {
 		pe_set_dpm_curr_request(port, DPM_REQUEST_SNK_STARTUP);
 		set_state_pe(port, PE_SNK_STARTUP);
 		return true;
-	} else if (PE_CHK_DPM_REQUEST(port,
-					DPM_REQUEST_SRC_STARTUP)) {
+	} else if (PE_CHK_DPM_REQUEST(port, DPM_REQUEST_SRC_STARTUP)) {
 		pe_set_dpm_curr_request(port, DPM_REQUEST_SRC_STARTUP);
 		set_state_pe(port, PE_SRC_STARTUP);
 		return true;
-	} else if (PE_CHK_DPM_REQUEST(port,
-					DPM_REQUEST_SOFT_RESET_SEND)) {
+	} else if (PE_CHK_DPM_REQUEST(port, DPM_REQUEST_SOFT_RESET_SEND)) {
 		pe_set_dpm_curr_request(port, DPM_REQUEST_SOFT_RESET_SEND);
 		/* Currently only support sending soft reset to SOP */
-		pe_send_soft_reset(port, TCPC_TX_SOP);
+		pe_send_soft_reset(port, TCPCI_MSG_SOP);
 		return true;
-	} else if (PE_CHK_DPM_REQUEST(port,
-					DPM_REQUEST_PORT_DISCOVERY)) {
+	} else if (PE_CHK_DPM_REQUEST(port, DPM_REQUEST_PORT_DISCOVERY)) {
 		pe_set_dpm_curr_request(port, DPM_REQUEST_PORT_DISCOVERY);
 		if (!PE_CHK_FLAG(port, PE_FLAGS_MODAL_OPERATION)) {
 			/*
 			 * Clear counters and reset timer to trigger a
-			 * port discovery.
+			 * port discovery, and also clear any pending VDM send
+			 * requests.
 			 */
 			pd_dfp_discovery_init(port);
+			/*
+			 * TODO(b/189353401): Do not reinitialize modes when no
+			 * longer required.
+			 */
+			pd_dfp_mode_init(port);
 			pe[port].dr_swap_attempt_counter = 0;
 			pe[port].discover_identity_counter = 0;
-			pe[port].discover_identity_timer = get_time().val +
-						PD_T_DISCOVER_IDENTITY;
+			pd_timer_enable(port, PE_TIMER_DISCOVER_IDENTITY,
+					PD_T_DISCOVER_IDENTITY);
+			PE_CLR_DPM_REQUEST(port, DPM_REQUEST_VDM);
 		}
 		return true;
 	} else if (PE_CHK_DPM_REQUEST(port, DPM_REQUEST_VDM)) {
@@ -1352,11 +1663,242 @@ static bool common_src_snk_dpm_requests(int port)
 		pe_set_dpm_curr_request(port, DPM_REQUEST_EXIT_MODES);
 		dpm_set_mode_exit_request(port);
 		return true;
+	} else if (PE_CHK_DPM_REQUEST(port, DPM_REQUEST_GET_SNK_CAPS)) {
+		pe_set_dpm_curr_request(port, DPM_REQUEST_GET_SNK_CAPS);
+		set_state_pe(port, PE_DR_GET_SINK_CAP);
+		return true;
+	} else if (PE_CHK_DPM_REQUEST(port,
+				      DPM_REQUEST_SOP_PRIME_SOFT_RESET_SEND)) {
+		pe_set_dpm_curr_request(port,
+					DPM_REQUEST_SOP_PRIME_SOFT_RESET_SEND);
+		pe[port].tx_type = TCPCI_MSG_SOP_PRIME;
+		set_state_pe(port, PE_VCS_CBL_SEND_SOFT_RESET);
+		return true;
+	} else if (PE_CHK_DPM_REQUEST(port, DPM_REQUEST_DR_SWAP)) {
+		pe_set_dpm_curr_request(port, DPM_REQUEST_DR_SWAP);
+		/* 6.3.9 DR_Swap Message in Revision 3.1, Version 1.3
+		 * If there are any Active Modes between the Port Partners when
+		 * a DR_Swap Message is a received, then a Hard Reset Shall be
+		 * performed
+		 */
+		if (PE_CHK_FLAG(port, PE_FLAGS_MODAL_OPERATION))
+			pe_set_hard_reset(port);
+		else
+			set_state_pe(port, PE_DRS_SEND_SWAP);
+		return true;
+	} else if (IS_ENABLED(CONFIG_USB_PD_DATA_RESET_MSG) &&
+		   PE_CHK_DPM_REQUEST(port, DPM_REQUEST_DATA_RESET)) {
+		if (prl_get_rev(port, TCPCI_MSG_SOP) < PD_REV30) {
+			PE_CLR_DPM_REQUEST(port, DPM_REQUEST_DATA_RESET);
+			dpm_data_reset_complete(port);
+			return false;
+		}
+
+		pe_set_dpm_curr_request(port, DPM_REQUEST_DATA_RESET);
+		if (pe[port].data_role == PD_ROLE_DFP)
+			set_state_pe(port, PE_DDR_SEND_DATA_RESET);
+		else
+			set_state_pe(port, PE_UDR_SEND_DATA_RESET);
+		return true;
+	} else if (IS_ENABLED(CONFIG_USB_PD_REV30) &&
+		   PE_CHK_DPM_REQUEST(port, DPM_REQUEST_GET_REVISION)) {
+		if (prl_get_rev(port, TCPCI_MSG_SOP) < PD_REV30) {
+			PE_CLR_DPM_REQUEST(port, DPM_REQUEST_GET_REVISION);
+			return false;
+		}
+		pe_set_dpm_curr_request(port, DPM_REQUEST_GET_REVISION);
+		set_state_pe(port, PE_GET_REVISION);
+		return true;
+	} else if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES) &&
+		   PE_CHK_DPM_REQUEST(port, DPM_REQUEST_SEND_ALERT)) {
+		if (prl_get_rev(port, TCPCI_MSG_SOP) < PD_REV30) {
+			PE_CLR_DPM_REQUEST(port, DPM_REQUEST_SEND_ALERT);
+			return false;
+		}
+		pe_set_dpm_curr_request(port, DPM_REQUEST_SEND_ALERT);
+		set_state_pe(port, PE_SEND_ALERT);
+		return true;
+	}
+
+	return false;
+}
+
+/*
+ * Handle source-specific DPM requests
+ *
+ * Returns true if state was set and calling run state should now return.
+ */
+static bool source_dpm_requests(int port)
+{
+	/*
+	 * Ignore sink-specific request:
+	 *   DPM_REQUEST_NEW_POWER_LEVEL
+	 *   DPM_REQUEST_SOURCE_CAP
+	 *   DPM_REQUEST_FRS_DET_ENABLE
+	 *   DPM_REQURST_FRS_DET_DISABLE
+	 */
+	PE_CLR_DPM_REQUEST(port, DPM_REQUEST_NEW_POWER_LEVEL |
+					 DPM_REQUEST_SOURCE_CAP |
+					 DPM_REQUEST_FRS_DET_ENABLE |
+					 DPM_REQUEST_FRS_DET_DISABLE);
+
+	if (pe[port].dpm_request) {
+		uint32_t dpm_request = pe[port].dpm_request;
+
+		PE_SET_FLAG(port, PE_FLAGS_LOCALLY_INITIATED_AMS);
+
+		if (PE_CHK_DPM_REQUEST(port, DPM_REQUEST_PR_SWAP)) {
+			pe_set_dpm_curr_request(port, DPM_REQUEST_PR_SWAP);
+			set_state_pe(port, PE_PRS_SRC_SNK_SEND_SWAP);
+			return true;
+		} else if (PE_CHK_DPM_REQUEST(port, DPM_REQUEST_GOTO_MIN)) {
+			pe_set_dpm_curr_request(port, DPM_REQUEST_GOTO_MIN);
+			set_state_pe(port, PE_SRC_TRANSITION_SUPPLY);
+			return true;
+		} else if (PE_CHK_DPM_REQUEST(port,
+					      DPM_REQUEST_SRC_CAP_CHANGE)) {
+			pe_set_dpm_curr_request(port,
+						DPM_REQUEST_SRC_CAP_CHANGE);
+			set_state_pe(port, PE_SRC_SEND_CAPABILITIES);
+			return true;
+		} else if (PE_CHK_DPM_REQUEST(port, DPM_REQUEST_GET_SRC_CAPS)) {
+			pe_set_dpm_curr_request(port, DPM_REQUEST_GET_SRC_CAPS);
+			set_state_pe(port, PE_DR_SRC_GET_SOURCE_CAP);
+			return true;
+		} else if (PE_CHK_DPM_REQUEST(port, DPM_REQUEST_SEND_PING)) {
+			pe_set_dpm_curr_request(port, DPM_REQUEST_SEND_PING);
+			set_state_pe(port, PE_SRC_PING);
+			return true;
+		} else if (common_src_snk_dpm_requests(port)) {
+			return true;
+		}
+
+		CPRINTF("Unhandled DPM Request %x received\n", dpm_request);
+		PE_CLR_DPM_REQUEST(port, dpm_request);
+		PE_CLR_FLAG(port, PE_FLAGS_LOCALLY_INITIATED_AMS);
+	}
+	return false;
+}
+
+/*
+ * Handle sink-specific DPM requests
+ *
+ * Returns true if state was set and calling run state should now return.
+ */
+static bool sink_dpm_requests(int port)
+{
+	/*
+	 * Ignore source specific requests:
+	 *   DPM_REQUEST_GOTO_MIN
+	 *   DPM_REQUEST_SRC_CAP_CHANGE,
+	 *   DPM_REQUEST_SEND_PING
+	 */
+	PE_CLR_DPM_REQUEST(port, DPM_REQUEST_GOTO_MIN |
+					 DPM_REQUEST_SRC_CAP_CHANGE |
+					 DPM_REQUEST_SEND_PING);
+
+	if (pe[port].dpm_request) {
+		uint32_t dpm_request = pe[port].dpm_request;
+
+		PE_SET_FLAG(port, PE_FLAGS_LOCALLY_INITIATED_AMS);
+
+		if (PE_CHK_DPM_REQUEST(port, DPM_REQUEST_PR_SWAP)) {
+			pe_set_dpm_curr_request(port, DPM_REQUEST_PR_SWAP);
+			set_state_pe(port, PE_PRS_SNK_SRC_SEND_SWAP);
+			return true;
+		} else if (PE_CHK_DPM_REQUEST(port, DPM_REQUEST_SOURCE_CAP)) {
+			pe_set_dpm_curr_request(port, DPM_REQUEST_SOURCE_CAP);
+			set_state_pe(port, PE_SNK_GET_SOURCE_CAP);
+			return true;
+		} else if (PE_CHK_DPM_REQUEST(port,
+					      DPM_REQUEST_NEW_POWER_LEVEL)) {
+			pe_set_dpm_curr_request(port,
+						DPM_REQUEST_NEW_POWER_LEVEL);
+			set_state_pe(port, PE_SNK_SELECT_CAPABILITY);
+			return true;
+		} else if (PE_CHK_DPM_REQUEST(port,
+					      DPM_REQUEST_FRS_DET_ENABLE)) {
+			pe_set_frs_enable(port, 1);
+
+			/* Requires no state change, fall through to false */
+			PE_CLR_DPM_REQUEST(port, DPM_REQUEST_FRS_DET_ENABLE);
+		} else if (PE_CHK_DPM_REQUEST(port,
+					      DPM_REQUEST_FRS_DET_DISABLE)) {
+			pe_set_frs_enable(port, 0);
+			/* Restore a default port current limit */
+			typec_select_src_current_limit_rp(port,
+							  CONFIG_USB_PD_PULLUP);
+
+			/* Requires no state change, fall through to false */
+			PE_CLR_DPM_REQUEST(port, DPM_REQUEST_FRS_DET_DISABLE);
+		} else if (common_src_snk_dpm_requests(port)) {
+			return true;
+#ifdef CONFIG_USB_PD_EPR
+		} else if (PE_CHK_DPM_REQUEST(port,
+					      DPM_REQUEST_EPR_MODE_ENTRY)) {
+			if (pe_snk_in_epr_mode(port)) {
+				PE_CLR_DPM_REQUEST(port,
+						   DPM_REQUEST_EPR_MODE_ENTRY);
+				CPRINTS("C%d: Already in EPR mode", port);
+				return false;
+			}
+
+			if (!pe_snk_can_enter_epr_mode(port)) {
+				PE_CLR_DPM_REQUEST(port,
+						   DPM_REQUEST_EPR_MODE_ENTRY);
+				CPRINTS("C%d: Not allowed to enter EPR", port);
+				return false;
+			}
+
+			pe_set_dpm_curr_request(port,
+						DPM_REQUEST_EPR_MODE_ENTRY);
+			pd_set_max_voltage(PD_MAX_VOLTAGE_MV);
+			set_state_pe(port, PE_SNK_SEND_EPR_MODE_ENTRY);
+			return true;
+		} else if (PE_CHK_DPM_REQUEST(port,
+					      DPM_REQUEST_EPR_MODE_EXIT)) {
+			if (!pe_snk_in_epr_mode(port)) {
+				PE_CLR_DPM_REQUEST(port,
+						   DPM_REQUEST_EPR_MODE_EXIT);
+				CPRINTS("C%d: Not in EPR mode", port);
+				return false;
+			}
+
+			/*
+			 * If we're already in an SPR contract, send an exit
+			 * message. Figure 8-217.
+			 */
+			if (pe_in_spr_contract(port)) {
+				pe_set_dpm_curr_request(
+					port, DPM_REQUEST_EPR_MODE_EXIT);
+				set_state_pe(port, PE_SNK_SEND_EPR_MODE_EXIT);
+				return true;
+			}
+
+			/*
+			 * Can't exit yet because we're still in EPR contract.
+			 * Send an SPR RDO to negotiate an SPR contract.
+			 * Keep DPM_REQUEST_EPR_MODE_EXIT so that we can retry.
+			 */
+			CPRINTS("C%d: Request SPR before EPR exit", port);
+			pd_set_max_voltage(PD_MAX_SPR_VOLTAGE);
+			pe_set_dpm_curr_request(port,
+						DPM_REQUEST_NEW_POWER_LEVEL);
+			set_state_pe(port, PE_SNK_SELECT_CAPABILITY);
+			return true;
+#endif /* CONFIG_USB_PD_EPR */
+		} else {
+			CPRINTF("Unhandled DPM Request %x received\n",
+				dpm_request);
+			PE_CLR_DPM_REQUEST(port, dpm_request);
+		}
+
+		PE_CLR_FLAG(port, PE_FLAGS_LOCALLY_INITIATED_AMS);
 	}
 	return false;
 }
 
-/* Get the previous TypeC state. */
+/* Get the previous PE state. */
 static enum usb_pe_state get_last_state_pe(const int port)
 {
 	return pe[port].ctx.previous - &pe_states[0];
@@ -1366,37 +1908,30 @@ static void print_current_state(const int port)
 {
 	const char *mode = "";
 
-	if (IS_ENABLED(CONFIG_USB_PD_REV30) &&
-			PE_CHK_FLAG(port, PE_FLAGS_FAST_ROLE_SWAP_PATH))
+	if (IS_ENABLED(CONFIG_USB_PD_REV30) && pe_in_frs_mode(port))
 		mode = " FRS-MODE";
 
 	if (IS_ENABLED(USB_PD_DEBUG_LABELS))
 		CPRINTS_L1("C%d: %s%s", port,
-			pe_state_names[get_state_pe(port)], mode);
+			   pe_state_names[get_state_pe(port)], mode);
 	else
-		CPRINTS("C%d: pe-st%d", port, get_state_pe(port));
+		CPRINTS_L1("C%d: pe-st%d", port, get_state_pe(port));
 }
 
 static void send_source_cap(int port)
 {
-#if defined(CONFIG_USB_PD_DYNAMIC_SRC_CAP) || \
-		defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT)
 	const uint32_t *src_pdo;
-	const int src_pdo_cnt = charge_manager_get_source_pdo(&src_pdo, port);
-#else
-	const uint32_t *src_pdo = pd_src_pdo;
-	const int src_pdo_cnt = pd_src_pdo_cnt;
-#endif
+	const int src_pdo_cnt = dpm_get_source_pdo(&src_pdo, port);
 
 	if (src_pdo_cnt == 0) {
 		/* No source capabilities defined, sink only */
-		send_ctrl_msg(port, TCPC_TX_SOP, PD_CTRL_REJECT);
+		send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_REJECT);
 	}
 
 	tx_emsg[port].len = src_pdo_cnt * 4;
 	memcpy(tx_emsg[port].buf, (uint8_t *)src_pdo, tx_emsg[port].len);
 
-	send_data_msg(port, TCPC_TX_SOP, PD_DATA_SOURCE_CAP);
+	send_data_msg(port, TCPCI_MSG_SOP, PD_DATA_SOURCE_CAP);
 }
 
 /*
@@ -1404,16 +1939,31 @@ static void send_source_cap(int port)
  */
 static void pe_send_request_msg(int port)
 {
+	uint32_t vpd_vdo = 0;
 	uint32_t rdo;
 	uint32_t curr_limit;
 	uint32_t supply_voltage;
+	enum pd_data_msg_type msg;
+
+	/*
+	 * If we are charging through a VPD, the requested voltage and current
+	 * might need adjusting.
+	 */
+	if ((get_usb_pd_cable_type(port) == IDH_PTYPE_VPD) &&
+	    is_vpd_ct_supported(port)) {
+		union vpd_vdo vpd =
+			pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME)
+				->identity.product_t1.vpd;
+
+		/* The raw vpd_vdo is passed to pd_build_request */
+		vpd_vdo = vpd.raw_value;
+	}
 
 	/* Build and send request RDO */
-	pd_build_request(pe[port].vpd_vdo, &rdo, &curr_limit,
-			&supply_voltage, port);
+	pd_build_request(vpd_vdo, &rdo, &curr_limit, &supply_voltage, port);
 
-	CPRINTF("C%d: Req [%d] %dmV %dmA", port, RDO_POS(rdo),
-					supply_voltage, curr_limit);
+	CPRINTF("C%d: Req [%d] %dmV %dmA", port, RDO_POS(rdo), supply_voltage,
+		curr_limit);
 	if (rdo & RDO_CAP_MISMATCH)
 		CPRINTF(" Mismatch");
 	CPRINTF("\n");
@@ -1421,72 +1971,72 @@ static void pe_send_request_msg(int port)
 	pe[port].curr_limit = curr_limit;
 	pe[port].supply_voltage = supply_voltage;
 
-	tx_emsg[port].len = 4;
+	if (IS_ENABLED(CONFIG_USB_PD_EPR) && pe_snk_in_epr_mode(port)) {
+		const uint32_t *src_caps = pd_get_src_caps(port);
+
+		tx_emsg[port].len = 8;
+		memcpy(tx_emsg[port].buf, (uint8_t *)&rdo, sizeof(rdo));
+		memcpy(tx_emsg[port].buf + sizeof(rdo),
+		       (uint8_t *)&src_caps[RDO_POS(rdo) - 1],
+		       sizeof(src_caps[0]));
+		msg = PD_DATA_EPR_REQUEST;
+	} else {
+		tx_emsg[port].len = 4;
+		memcpy(tx_emsg[port].buf, (uint8_t *)&rdo, tx_emsg[port].len);
+		msg = PD_DATA_REQUEST;
+	}
 
-	memcpy(tx_emsg[port].buf, (uint8_t *)&rdo, tx_emsg[port].len);
-	send_data_msg(port, TCPC_TX_SOP, PD_DATA_REQUEST);
+	send_data_msg(port, TCPCI_MSG_SOP, msg);
 }
 
-static void pe_update_pdo_flags(int port, uint32_t pdo)
+static void pe_update_src_pdo_flags(int port, int pdo_cnt, uint32_t *pdos)
 {
-#ifdef CONFIG_CHARGE_MANAGER
-#ifdef CONFIG_USB_PD_ALT_MODE_DFP
-	int charge_allowlisted =
-		(pd_get_power_role(port) == PD_ROLE_SINK &&
-			pd_charge_from_device(pd_get_identity_vid(port),
-			pd_get_identity_pid(port)));
-#else
-	const int charge_allowlisted = 0;
-#endif
-#endif
-
-	/* can only parse PDO flags if type is fixed */
-	if ((pdo & PDO_TYPE_MASK) != PDO_TYPE_FIXED)
+	/*
+	 * Only parse PDO flags if type is fixed
+	 *
+	 * Note: From 6.4.1 Capabilities Message "The vSafe5V Fixed Supply
+	 * Object Shall always be the first object." so hitting this condition
+	 * would mean the partner is voilating spec.
+	 */
+	if ((pdos[0] & PDO_TYPE_MASK) != PDO_TYPE_FIXED)
 		return;
 
-	if (pdo & PDO_FIXED_DUAL_ROLE)
-		tc_partner_dr_power(port, 1);
-	else
-		tc_partner_dr_power(port, 0);
-
-	if (pdo & PDO_FIXED_UNCONSTRAINED)
-		tc_partner_unconstrainedpower(port, 1);
-	else
-		tc_partner_unconstrainedpower(port, 0);
-
-	/* Do not set USB comm if we are in an alt-mode */
-	if (pe[port].partner_amodes[TCPC_TX_SOP].amode_idx == 0) {
-		if (pdo & PDO_FIXED_COMM_CAP)
-			tc_partner_usb_comm(port, 1);
-		else
-			tc_partner_usb_comm(port, 0);
+	if (IS_ENABLED(CONFIG_CHARGE_MANAGER)) {
+		if (pd_can_charge_from_device(port, pdo_cnt, pdos)) {
+			charge_manager_update_dualrole(port, CAP_DEDICATED);
+		} else {
+			charge_manager_update_dualrole(port, CAP_DUALROLE);
+		}
 	}
+}
 
-	if (pdo & PDO_FIXED_DATA_SWAP)
-		tc_partner_dr_data(port, 1);
-	else
-		tc_partner_dr_data(port, 0);
+/*
+ * Evaluate whether our PR role is in the middle of changing, meaning we our
+ * current PR role is not the one we expect to have very shortly.
+ */
+bool pe_is_pr_swapping(int port)
+{
+	enum usb_pe_state cur_state = get_state_pe(port);
 
-#ifdef CONFIG_CHARGE_MANAGER
-	/*
-	 * Treat device as a dedicated charger (meaning we should charge
-	 * from it) if it does not support power swap, or if it is unconstrained
-	 * power, or if we are a sink and the device identity matches a
-	 * charging allow-list.
-	 */
-	if (!(pdo & PDO_FIXED_DUAL_ROLE) || (pdo & PDO_FIXED_UNCONSTRAINED) ||
-		charge_allowlisted) {
-		PE_CLR_FLAG(port, PE_FLAGS_PORT_PARTNER_IS_DUALROLE);
-		charge_manager_update_dualrole(port, CAP_DEDICATED);
-	} else {
-		PE_SET_FLAG(port, PE_FLAGS_PORT_PARTNER_IS_DUALROLE);
-		charge_manager_update_dualrole(port, CAP_DUALROLE);
-	}
-#endif
+	if (cur_state == PE_PRS_SRC_SNK_EVALUATE_SWAP ||
+	    cur_state == PE_PRS_SRC_SNK_TRANSITION_TO_OFF ||
+	    cur_state == PE_PRS_SNK_SRC_EVALUATE_SWAP ||
+	    cur_state == PE_PRS_SNK_SRC_TRANSITION_TO_OFF)
+		return true;
+
+	return false;
 }
 
 void pd_request_power_swap(int port)
 {
+	/* Ignore requests when the board does not wish to swap */
+	if (!pd_check_power_swap(port))
+		return;
+
+	/* Ignore requests when our power role is transitioning */
+	if (pe_is_pr_swapping(port))
+		return;
+
 	/*
 	 * Always reset the SRC to SNK PR swap counter when a PR swap is
 	 * requested by policy.
@@ -1495,29 +2045,17 @@ void pd_request_power_swap(int port)
 	pd_dpm_request(port, DPM_REQUEST_PR_SWAP);
 }
 
-int pd_is_port_partner_dualrole(int port)
-{
-	return PE_CHK_FLAG(port, PE_FLAGS_PORT_PARTNER_IS_DUALROLE);
-}
-
-static void pe_prl_execute_hard_reset(int port)
-{
-	prl_execute_hard_reset(port);
-}
-
 /* The function returns true if there is a PE state change, false otherwise */
 static bool port_try_vconn_swap(int port)
 {
 	if (pe[port].vconn_swap_counter < N_VCONN_SWAP_COUNT) {
-		pe[port].vconn_swap_counter++;
-		PE_SET_FLAG(port, PE_FLAGS_VCONN_SWAP_TO_ON);
+		pd_dpm_request(port, DPM_REQUEST_VCONN_SWAP);
 		set_state_pe(port, get_last_state_pe(port));
 		return true;
 	}
 	return false;
 }
 
-#ifdef CONFIG_USB_PD_ALT_MODE_DFP
 /*
  * Run discovery at our leisure from PE_SNK_Ready or PE_SRC_Ready, after
  * attempting to get into the desired default policy of DFP/Vconn source
@@ -1525,96 +2063,105 @@ static bool port_try_vconn_swap(int port)
  * Return indicates whether set_state was called, in which case the calling
  * function should return as well.
  */
-static bool pe_attempt_port_discovery(int port)
+__maybe_unused static bool pe_attempt_port_discovery(int port)
 {
-	/*
-	 * DONE set once modal entry is successful, discovery completes, or
-	 * discovery results in a NAK
+	if (!IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP))
+		assert(0);
+
+	/* TODO(b/272827504): Gate discovery via a DPM request and remove this
+	 * flag.
 	 */
-	if (PE_CHK_FLAG(port, PE_FLAGS_VDM_SETUP_DONE))
+	if (PE_CHK_FLAG(port, PE_FLAGS_DISCOVERY_DISABLED))
 		return false;
 
-	/*
-	 * TODO: POLICY decision: move policy functionality out to a separate
-	 * file.  For now, try once to become DFP/Vconn source
-	 */
-	if (PE_CHK_FLAG(port, PE_FLAGS_DR_SWAP_TO_DFP)) {
+	/* Apply Port Discovery DR Swap Policy */
+	if (port_discovery_dr_swap_policy(
+		    port, pe[port].data_role,
+		    PE_CHK_FLAG(port, PE_FLAGS_DR_SWAP_TO_DFP))) {
+		PE_SET_FLAG(port, PE_FLAGS_LOCALLY_INITIATED_AMS);
 		PE_CLR_FLAG(port, PE_FLAGS_DR_SWAP_TO_DFP);
+		set_state_pe(port, PE_DRS_SEND_SWAP);
+		return true;
+	}
 
-		if (pe[port].data_role == PD_ROLE_UFP) {
-			PE_SET_FLAG(port, PE_FLAGS_LOCALLY_INITIATED_AMS);
-			set_state_pe(port, PE_DRS_SEND_SWAP);
-			return true;
-		}
+	/*
+	 * An edge case of DR Swap fail (port still UFP) and partner in PD 2.0.
+	 * PD 2.0 allows only DFP to initiate Discover Identity, but partner may
+	 * reject a DR Swap.
+	 */
+	if (pe[port].data_role == PD_ROLE_UFP &&
+	    prl_get_rev(port, TCPCI_MSG_SOP) == PD_REV20) {
+		/* Although, logically, "pd_disable_discovery" should set
+		 * "PE_FLAGS_DISCOVERY_DISABLED," set it here to make its
+		 * limited purpose obvious: When discovery is impossible, send
+		 * discovery-done events exactly once.
+		 */
+		PE_SET_FLAG(port, PE_FLAGS_DISCOVERY_DISABLED);
+		pd_disable_discovery(port);
+		pd_notify_event(port, PD_STATUS_EVENT_SOP_DISC_DONE);
+		pd_notify_event(port, PD_STATUS_EVENT_SOP_PRIME_DISC_DONE);
+		return false;
 	}
 
+	/* Apply Port Discovery VCONN Swap Policy */
 	if (IS_ENABLED(CONFIG_USBC_VCONN) &&
-			PE_CHK_FLAG(port, PE_FLAGS_VCONN_SWAP_TO_ON)) {
+	    port_discovery_vconn_swap_policy(
+		    port, PE_CHK_FLAG(port, PE_FLAGS_VCONN_SWAP_TO_ON))) {
+		PE_SET_FLAG(port, PE_FLAGS_LOCALLY_INITIATED_AMS);
 		PE_CLR_FLAG(port, PE_FLAGS_VCONN_SWAP_TO_ON);
-
-		if (!tc_is_vconn_src(port)) {
-			PE_SET_FLAG(port, PE_FLAGS_LOCALLY_INITIATED_AMS);
-			set_state_pe(port, PE_VCS_SEND_SWAP);
-			return true;
-		}
-	}
-
-	/* If mode entry was successful, disable the timer */
-	if (PE_CHK_FLAG(port, PE_FLAGS_VDM_SETUP_DONE)) {
-		pe[port].discover_identity_timer = TIMER_DISABLED;
-		return false;
+		set_state_pe(port, PE_VCS_SEND_SWAP);
+		return true;
 	}
 
 	/*
 	 * Run discovery functions when the timer indicating either cable
 	 * discovery spacing or BUSY spacing runs out.
 	 */
-	if (get_time().val > pe[port].discover_identity_timer) {
-		if (pd_get_identity_discovery(port, TCPC_TX_SOP_PRIME) ==
-				PD_DISC_NEEDED && pe_can_send_sop_prime(port)) {
-			pe[port].tx_type = TCPC_TX_SOP_PRIME;
+	if (pd_timer_is_expired(port, PE_TIMER_DISCOVER_IDENTITY)) {
+		if (pd_get_identity_discovery(port, TCPCI_MSG_SOP_PRIME) ==
+		    PD_DISC_NEEDED) {
+			pe[port].tx_type = TCPCI_MSG_SOP_PRIME;
 			set_state_pe(port, PE_VDM_IDENTITY_REQUEST_CBL);
 			return true;
-		} else if (pd_get_identity_discovery(port, TCPC_TX_SOP) ==
-				PD_DISC_NEEDED &&
-				pe_can_send_sop_vdm(port, CMD_DISCOVER_IDENT)) {
-			pe[port].tx_type = TCPC_TX_SOP;
-			set_state_pe(port,
-				     PE_INIT_PORT_VDM_IDENTITY_REQUEST);
+		} else if (pd_get_identity_discovery(port, TCPCI_MSG_SOP) ==
+				   PD_DISC_NEEDED &&
+			   pe_can_send_sop_vdm(port, CMD_DISCOVER_IDENT)) {
+			pe[port].tx_type = TCPCI_MSG_SOP;
+			set_state_pe(port, PE_INIT_PORT_VDM_IDENTITY_REQUEST);
 			return true;
-		} else if (pd_get_svids_discovery(port, TCPC_TX_SOP) ==
-				PD_DISC_NEEDED &&
-				pe_can_send_sop_vdm(port, CMD_DISCOVER_SVID)) {
-			pe[port].tx_type = TCPC_TX_SOP;
+		} else if (pd_get_svids_discovery(port, TCPCI_MSG_SOP) ==
+				   PD_DISC_NEEDED &&
+			   pe_can_send_sop_vdm(port, CMD_DISCOVER_SVID)) {
+			pe[port].tx_type = TCPCI_MSG_SOP;
 			set_state_pe(port, PE_INIT_VDM_SVIDS_REQUEST);
 			return true;
-		} else if (pd_get_modes_discovery(port, TCPC_TX_SOP) ==
-				PD_DISC_NEEDED &&
-				pe_can_send_sop_vdm(port, CMD_DISCOVER_MODES)) {
-			pe[port].tx_type = TCPC_TX_SOP;
+		} else if (pd_get_modes_discovery(port, TCPCI_MSG_SOP) ==
+				   PD_DISC_NEEDED &&
+			   pe_can_send_sop_vdm(port, CMD_DISCOVER_MODES)) {
+			pe[port].tx_type = TCPCI_MSG_SOP;
 			set_state_pe(port, PE_INIT_VDM_MODES_REQUEST);
 			return true;
-		} else if (pd_get_svids_discovery(port, TCPC_TX_SOP_PRIME)
-				== PD_DISC_NEEDED &&
-				pe_can_send_sop_prime(port)) {
-			pe[port].tx_type = TCPC_TX_SOP_PRIME;
+		} else if (pd_get_svids_discovery(port, TCPCI_MSG_SOP_PRIME) ==
+			   PD_DISC_NEEDED) {
+			pe[port].tx_type = TCPCI_MSG_SOP_PRIME;
 			set_state_pe(port, PE_INIT_VDM_SVIDS_REQUEST);
 			return true;
-		} else if (pd_get_modes_discovery(port, TCPC_TX_SOP_PRIME) ==
-				PD_DISC_NEEDED &&
-				pe_can_send_sop_prime(port)) {
-			pe[port].tx_type = TCPC_TX_SOP_PRIME;
+		} else if (pd_get_modes_discovery(port, TCPCI_MSG_SOP_PRIME) ==
+			   PD_DISC_NEEDED) {
+			pe[port].tx_type = TCPCI_MSG_SOP_PRIME;
 			set_state_pe(port, PE_INIT_VDM_MODES_REQUEST);
 			return true;
+		} else {
+			pd_timer_disable(port, PE_TIMER_DISCOVER_IDENTITY);
+			return false;
 		}
 	}
 
 	return false;
 }
-#endif
 
-bool pd_setup_vdm_request(int port, enum tcpm_transmit_type tx_type,
-		uint32_t *vdm, uint32_t vdo_cnt)
+bool pd_setup_vdm_request(int port, enum tcpci_msg_type tx_type, uint32_t *vdm,
+			  uint32_t vdo_cnt)
 {
 	if (vdo_cnt < VDO_HDR_SIZE || vdo_cnt > VDO_MAX_SIZE)
 		return false;
@@ -1626,42 +2173,13 @@ bool pd_setup_vdm_request(int port, enum tcpm_transmit_type tx_type,
 	return true;
 }
 
-int pd_dev_store_rw_hash(int port, uint16_t dev_id, uint32_t *rw_hash,
-					uint32_t current_image)
-{
-	pe[port].dev_id = dev_id;
-	memcpy(pe[port].dev_rw_hash, rw_hash, PD_RW_HASH_SIZE);
-#ifdef CONFIG_CMD_PD_DEV_DUMP_INFO
-	pd_dev_dump_info(dev_id, rw_hash);
-#endif
-	pe[port].current_image = current_image;
-
-	if (IS_ENABLED(CONFIG_USB_PD_HOST_CMD)) {
-		int i;
-
-		/* Search table for matching device / hash */
-		for (i = 0; i < RW_HASH_ENTRIES; i++)
-			if (dev_id == rw_hash_table[i].dev_id)
-				return !memcmp(rw_hash,
-					       rw_hash_table[i].dev_rw_hash,
-					       PD_RW_HASH_SIZE);
-	}
-
-	return 0;
-}
-
-void pd_dev_get_rw_hash(int port, uint16_t *dev_id, uint8_t *rw_hash,
-			 uint32_t *current_image)
-{
-	*dev_id = pe[port].dev_id;
-	*current_image = pe[port].current_image;
-	if (*dev_id)
-		memcpy(rw_hash, pe[port].dev_rw_hash, PD_RW_HASH_SIZE);
-}
-
 /*
  * This function must only be called from the PE_SNK_READY entry and
  * PE_SRC_READY entry State.
+ *
+ * TODO(b:181339670) Rethink jitter timer restart if this is the first
+ * message but the partner gets a message in first, may not want to
+ * disable and restart it.
  */
 static void pe_update_wait_and_add_jitter_timer(int port)
 {
@@ -1683,11 +2201,12 @@ static void pe_update_wait_and_add_jitter_timer(int port)
 	 * we start our interrogation.  Add some jitter of up to
 	 * ~345ms to prevent multiple collisions.
 	 */
-	if (prl_get_rev(port, TCPC_TX_SOP) == PD_REV20 &&
-			PE_CHK_FLAG(port, PE_FLAGS_FIRST_MSG)) {
-		pe[port].wait_and_add_jitter_timer = get_time().val +
+	if (prl_get_rev(port, TCPCI_MSG_SOP) == PD_REV20 &&
+	    PE_CHK_FLAG(port, PE_FLAGS_FIRST_MSG) &&
+	    pd_timer_is_disabled(port, PE_TIMER_WAIT_AND_ADD_JITTER)) {
+		pd_timer_enable(port, PE_TIMER_WAIT_AND_ADD_JITTER,
 				SRC_SNK_READY_HOLD_OFF_US +
-				(get_time().le.lo & 0xf) * 23 * MSEC;
+					(get_time().le.lo & 0xf) * 23 * MSEC);
 	}
 }
 
@@ -1700,14 +2219,14 @@ static void pe_update_wait_and_add_jitter_timer(int port)
  */
 /*
  * pe_sender_response_msg_entry
- * Initiallization for handling sender response messages.
+ * Initialization for handling sender response messages.
  *
  * @param port USB-C Port number
  */
 static void pe_sender_response_msg_entry(const int port)
 {
 	/* Stop sender response timer */
-	pe[port].sender_response_timer = TIMER_DISABLED;
+	pd_timer_disable(port, PE_TIMER_SENDER_RESPONSE);
 }
 
 /*
@@ -1730,7 +2249,9 @@ static void pe_sender_response_msg_entry(const int port)
  */
 static enum pe_msg_check pe_sender_response_msg_run(const int port)
 {
-	if (pe[port].sender_response_timer == TIMER_DISABLED) {
+	timestamp_t tx_success_ts;
+	uint32_t offset;
+	if (pd_timer_is_disabled(port, PE_TIMER_SENDER_RESPONSE)) {
 		/* Check for Discard */
 		if (PE_CHK_FLAG(port, PE_FLAGS_MSG_DISCARDED)) {
 			int dpm_request = pe[port].dpm_curr_request;
@@ -1748,9 +2269,19 @@ static enum pe_msg_check pe_sender_response_msg_run(const int port)
 		if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
 			PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
 
-			/* Initialize and run the SenderResponseTimer */
-			pe[port].sender_response_timer = get_time().val +
-							PD_T_SENDER_RESPONSE;
+			/* TCPC TX success time stamp */
+			tx_success_ts = prl_get_tcpc_tx_success_ts(port);
+			/* Calculate the delay from TX success to PE */
+			offset = time_since32(tx_success_ts);
+
+			/*
+			 * Initialize and run the SenderResponseTimer by
+			 * offsetting it with TX transmit success time.
+			 * This would remove the effect of the latency from
+			 * propagating the TX status.
+			 */
+			pd_timer_enable(port, PE_TIMER_SENDER_RESPONSE,
+					PD_T_SENDER_RESPONSE - offset);
 			return PE_MSG_SEND_COMPLETED;
 		}
 		return PE_MSG_SEND_PENDING;
@@ -1758,6 +2289,17 @@ static enum pe_msg_check pe_sender_response_msg_run(const int port)
 	return PE_MSG_SENT;
 }
 
+/*
+ * pe_sender_response_msg_exit
+ * Exit cleanup for handling sender response messages.
+ *
+ * @param port USB-C Port number
+ */
+static void pe_sender_response_msg_exit(int port)
+{
+	pd_timer_disable(port, PE_TIMER_SENDER_RESPONSE);
+}
+
 /**
  * PE_SRC_Startup
  */
@@ -1769,7 +2311,7 @@ static void pe_src_startup_entry(int port)
 	pe[port].caps_counter = 0;
 
 	/* Reset the protocol layer */
-	prl_reset(port);
+	prl_reset_soft(port);
 
 	/* Set initial data role */
 	pe[port].data_role = pd_get_data_role(port);
@@ -1780,29 +2322,62 @@ static void pe_src_startup_entry(int port)
 	/* Clear explicit contract. */
 	pe_invalidate_explicit_contract(port);
 
+	/* Clear any pending PD events */
+	pe_clear_ado(port);
+
 	if (PE_CHK_FLAG(port, PE_FLAGS_PR_SWAP_COMPLETE)) {
 		PE_CLR_FLAG(port, PE_FLAGS_PR_SWAP_COMPLETE);
+		/*
+		 * Protocol layer reset clears the message IDs for all SOP
+		 * types. Indicate that a SOP' soft reset is required before any
+		 * other messages are sent to the cable.
+		 *
+		 * Note that other paths into this state are for the initial
+		 * connection and for a hard reset. In both cases the cable
+		 * should also automatically clear the message IDs so don't
+		 * generate an SOP' soft reset for those cases. Sending
+		 * unnecessary SOP' soft resets causes bad behavior with
+		 * some devices. See b/179325862.
+		 */
+		pd_dpm_request(port, DPM_REQUEST_SOP_PRIME_SOFT_RESET_SEND);
 
 		/* Start SwapSourceStartTimer */
-		pe[port].swap_source_start_timer = get_time().val +
-			PD_T_SWAP_SOURCE_START;
-	} else {
+		pd_timer_enable(port, PE_TIMER_SWAP_SOURCE_START,
+				PD_T_SWAP_SOURCE_START);
+
+		/*
+		 * Evaluate port's sink caps for preferred current, if
+		 * already available
+		 */
+		if (pd_get_snk_cap_cnt(port) > 0)
+			dpm_evaluate_sink_fixed_pdo(port,
+						    *pd_get_snk_caps(port));
+
+		/*
+		 * Remove prior FRS claims to 3.0 A now that sink current has
+		 * been claimed, to avoid issues with lower priority ports
+		 * potentially receiving a 3.0 A claim between calls.
+		 */
+		dpm_remove_source(port);
+	} else {
 		/*
 		 * SwapSourceStartTimer delay is not needed, so trigger now.
 		 * We can't use set_state_pe here, since we need to ensure that
 		 * the protocol layer is running again (done in run function).
 		 */
-		pe[port].swap_source_start_timer = get_time().val;
+		pd_timer_enable(port, PE_TIMER_SWAP_SOURCE_START, 0);
 
 		/*
 		 * Set DiscoverIdentityTimer to trigger when we enter
 		 * src_discovery for the first time.  After initial startup
 		 * set, vdm_identity_request_cbl will handle the timer updates.
 		 */
-		pe[port].discover_identity_timer = get_time().val;
+		pd_timer_enable(port, PE_TIMER_DISCOVER_IDENTITY, 0);
 
-		/* Clear port discovery flags */
+		/* Clear port discovery/mode flags */
 		pd_dfp_discovery_init(port);
+		pd_dfp_mode_init(port);
+		dpm_init(port);
 		pe[port].ama_vdo = PD_VDO_INVALID;
 		pe[port].vpd_vdo = PD_VDO_INVALID;
 		pe[port].discover_identity_counter = 0;
@@ -1812,6 +2387,18 @@ static void pe_src_startup_entry(int port)
 
 		/* Reset VCONN swap counter */
 		pe[port].vconn_swap_counter = 0;
+
+		/* Request partner sink caps if a feature requires them */
+		if (IS_ENABLED(CONFIG_USB_PD_HOST_CMD) ||
+		    CONFIG_USB_PD_3A_PORTS > 0 || IS_ENABLED(CONFIG_USB_PD_FRS))
+			pd_dpm_request(port, DPM_REQUEST_GET_SNK_CAPS);
+
+		/*
+		 * Request partner's revision information. The PE_Get_Revision
+		 * state will only send Get_Revision to partners with major
+		 * revision 3.0
+		 */
+		pd_dpm_request(port, DPM_REQUEST_GET_REVISION);
 	}
 }
 
@@ -1821,10 +2408,15 @@ static void pe_src_startup_run(int port)
 	if (!prl_is_running(port))
 		return;
 
-	if (get_time().val > pe[port].swap_source_start_timer)
+	if (pd_timer_is_expired(port, PE_TIMER_SWAP_SOURCE_START))
 		set_state_pe(port, PE_SRC_SEND_CAPABILITIES);
 }
 
+static void pe_src_startup_exit(int port)
+{
+	pd_timer_disable(port, PE_TIMER_SWAP_SOURCE_START);
+}
+
 /**
  * PE_SRC_Discovery
  */
@@ -1844,8 +2436,8 @@ static void pe_src_discovery_entry(int port)
 	 * is in place.  All other probing must happen from ready states.
 	 */
 	if (get_last_state_pe(port) != PE_VDM_IDENTITY_REQUEST_CBL)
-		pe[port].source_cap_timer =
-				get_time().val + PD_T_SEND_SOURCE_CAP;
+		pd_timer_enable(port, PE_TIMER_SOURCE_CAP,
+				PD_T_SEND_SOURCE_CAP);
 }
 
 static void pe_src_discovery_run(int port)
@@ -1864,11 +2456,24 @@ static void pe_src_discovery_run(int port)
 	 *   1) DPM requests the identity of the cable plug and
 	 *   2) DiscoverIdentityCounter < nDiscoverIdentityCount
 	 */
-	if (get_time().val > pe[port].source_cap_timer) {
+	if (pd_timer_is_expired(port, PE_TIMER_SOURCE_CAP)) {
 		if (pe[port].caps_counter <= N_CAPS_COUNT) {
 			set_state_pe(port, PE_SRC_SEND_CAPABILITIES);
 			return;
 		} else if (!PE_CHK_FLAG(port, PE_FLAGS_PD_CONNECTION)) {
+			/*
+			 * Cable identity may be discovered without a PD
+			 * contract in place. If it has been discovered, notify
+			 * the AP.
+			 */
+			if (pd_get_identity_discovery(port,
+						      TCPCI_MSG_SOP_PRIME) ==
+			    PD_DISC_COMPLETE) {
+				pd_notify_event(
+					port,
+					PD_STATUS_EVENT_SOP_PRIME_DISC_DONE);
+			}
+
 			set_state_pe(port, PE_SRC_DISABLED);
 			return;
 		}
@@ -1879,10 +2484,13 @@ static void pe_src_discovery_run(int port)
 	 * contract, we use it here to ensure we space any potential BUSY
 	 * requests properly.
 	 */
-	if (pd_get_identity_discovery(port, TCPC_TX_SOP_PRIME) == PD_DISC_NEEDED
-			&& get_time().val > pe[port].discover_identity_timer
-			&& pe_can_send_sop_prime(port)) {
-		pe[port].tx_type = TCPC_TX_SOP_PRIME;
+	if (pd_get_identity_discovery(port, TCPCI_MSG_SOP_PRIME) ==
+		    PD_DISC_NEEDED &&
+	    pd_timer_is_expired(port, PE_TIMER_DISCOVER_IDENTITY) &&
+	    pe_can_send_sop_prime(port) &&
+	    (pe[port].discover_identity_counter <
+	     N_DISCOVER_IDENTITY_PRECONTRACT_LIMIT)) {
+		pe[port].tx_type = TCPCI_MSG_SOP_PRIME;
 		set_state_pe(port, PE_VDM_IDENTITY_REQUEST_CBL);
 		return;
 	}
@@ -1894,8 +2502,8 @@ static void pe_src_discovery_run(int port)
 	 *   3) And the HardResetCounter > nHardResetCount.
 	 */
 	if (!PE_CHK_FLAG(port, PE_FLAGS_PD_CONNECTION) &&
-			get_time().val > pe[port].no_response_timer &&
-			pe[port].hard_reset_counter > N_HARD_RESET_COUNT) {
+	    pd_timer_is_expired(port, PE_TIMER_NO_RESPONSE) &&
+	    pe[port].hard_reset_counter > N_HARD_RESET_COUNT) {
 		set_state_pe(port, PE_SRC_DISABLED);
 		return;
 	}
@@ -1934,7 +2542,7 @@ static void pe_src_send_capabilities_run(int port)
 		set_state_pe(port, PE_SRC_READY);
 		return;
 	} else if (msg_check == PE_MSG_DISCARDED) {
-		pe_send_soft_reset(port, TCPC_TX_SOP);
+		pe_send_soft_reset(port, TCPCI_MSG_SOP);
 		return;
 	}
 
@@ -1950,7 +2558,7 @@ static void pe_src_send_capabilities_run(int port)
 		 *  3) Initialize and run the SenderResponseTimer.
 		 */
 		/* Stop the NoResponseTimer */
-		pe[port].no_response_timer = TIMER_DISABLED;
+		pd_timer_disable(port, PE_TIMER_NO_RESPONSE);
 
 		/* Reset the HardResetCounter to zero */
 		pe[port].hard_reset_counter = 0;
@@ -1971,22 +2579,16 @@ static void pe_src_send_capabilities_run(int port)
 		 * Request Message Received?
 		 */
 		if (PD_HEADER_CNT(rx_emsg[port].header) > 0 &&
-			PD_HEADER_TYPE(rx_emsg[port].header) ==
-							PD_DATA_REQUEST) {
-
+		    PD_HEADER_TYPE(rx_emsg[port].header) == PD_DATA_REQUEST) {
 			/*
 			 * Set to highest revision supported by both
 			 * ports.
 			 */
-			prl_set_rev(port, TCPC_TX_SOP,
-			MIN(PD_REVISION, PD_HEADER_REV(rx_emsg[port].header)));
+			prl_set_rev(port, TCPCI_MSG_SOP,
+				    MIN(PD_REVISION,
+					PD_HEADER_REV(rx_emsg[port].header)));
 
-			/*
-			 * If port partner runs PD 2.0, cable communication must
-			 * also be PD 2.0
-			 */
-			if (prl_get_rev(port, TCPC_TX_SOP) == PD_REV20)
-				prl_set_rev(port, TCPC_TX_SOP_PRIME, PD_REV20);
+			init_cable_rev(port);
 
 			/* We are PD connected */
 			PE_SET_FLAG(port, PE_FLAGS_PD_CONNECTION);
@@ -2029,7 +2631,7 @@ static void pe_src_send_capabilities_run(int port)
 		if (!PE_CHK_FLAG(port, PE_FLAGS_PD_CONNECTION))
 			set_state_pe(port, PE_SRC_DISCOVERY);
 		else
-			pe_send_soft_reset(port, TCPC_TX_SOP);
+			pe_send_soft_reset(port, TCPCI_MSG_SOP);
 		return;
 	}
 
@@ -2044,9 +2646,9 @@ static void pe_src_send_capabilities_run(int port)
 	 *  2) The NoResponseTimer times out
 	 *  3) And the HardResetCounter > nHardResetCount.
 	 */
-	if (get_time().val > pe[port].no_response_timer) {
+	if (pd_timer_is_expired(port, PE_TIMER_NO_RESPONSE)) {
 		if (pe[port].hard_reset_counter <= N_HARD_RESET_COUNT)
-			set_state_pe(port, PE_SRC_HARD_RESET);
+			pe_set_hard_reset(port);
 		else if (PE_CHK_FLAG(port, PE_FLAGS_PD_CONNECTION))
 			set_state_pe(port, PE_WAIT_FOR_ERROR_RECOVERY);
 		else
@@ -2058,12 +2660,17 @@ static void pe_src_send_capabilities_run(int port)
 	 * Transition to the PE_SRC_Hard_Reset state when:
 	 *  1) The SenderResponseTimer times out.
 	 */
-	if (get_time().val > pe[port].sender_response_timer) {
-		set_state_pe(port, PE_SRC_HARD_RESET);
+	if (pd_timer_is_expired(port, PE_TIMER_SENDER_RESPONSE)) {
+		pe_set_hard_reset(port);
 		return;
 	}
 }
 
+static void pe_src_send_capabilities_exit(int port)
+{
+	pe_sender_response_msg_exit(port);
+}
+
 /**
  * PE_SRC_Negotiate_Capability
  */
@@ -2080,6 +2687,7 @@ static void pe_src_negotiate_capability_entry(int port)
 	 * Evaluate the Request from the Attached Sink
 	 */
 
+	dpm_evaluate_request_rdo(port, payload);
 	/*
 	 * Transition to the PE_SRC_Capability_Response state when:
 	 *  1) The Request cannot be met.
@@ -2105,17 +2713,13 @@ static void pe_src_transition_supply_entry(int port)
 {
 	print_current_state(port);
 
-	/* Transition Power Supply */
-	pd_transition_voltage(pe[port].requested_idx);
-
 	/* Send a GotoMin Message or otherwise an Accept Message */
 	if (PE_CHK_FLAG(port, PE_FLAGS_ACCEPT)) {
 		PE_CLR_FLAG(port, PE_FLAGS_ACCEPT);
-		send_ctrl_msg(port, TCPC_TX_SOP, PD_CTRL_ACCEPT);
+		send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_ACCEPT);
 	} else {
-		send_ctrl_msg(port, TCPC_TX_SOP, PD_CTRL_GOTO_MIN);
+		send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_GOTO_MIN);
 	}
-
 }
 
 static void pe_src_transition_supply_run(int port)
@@ -2144,45 +2748,66 @@ static void pe_src_transition_supply_run(int port)
 
 		if (PE_CHK_FLAG(port, PE_FLAGS_PS_READY)) {
 			PE_CLR_FLAG(port, PE_FLAGS_PS_READY);
-			/* NOTE: Second pass through this code block */
-			/* Explicit Contract is now in place */
-			pe_set_explicit_contract(port);
 
 			/*
 			 * Set first message flag to trigger a wait and add
-			 * jitter delay when operating in PD2.0 mode.
+			 * jitter delay when operating in PD2.0 mode. Skip
+			 * if we already have a contract.
 			 */
-			PE_SET_FLAG(port, PE_FLAGS_FIRST_MSG);
+			if (!pe_is_explicit_contract(port)) {
+				PE_SET_FLAG(port, PE_FLAGS_FIRST_MSG);
+				pd_timer_disable(port,
+						 PE_TIMER_WAIT_AND_ADD_JITTER);
+			}
+
+			/* NOTE: Second pass through this code block */
+			/* Explicit Contract is now in place */
+			pe_set_explicit_contract(port);
 
 			/*
 			 * Setup to get Device Policy Manager to request
 			 * Source Capabilities, if needed, for possible
-			 * PR_Swap
+			 * PR_Swap.  Get the number directly to avoid re-probing
+			 * if the partner generated an error and left -1 for the
+			 * count.
 			 */
-			if (pd_get_src_cap_cnt(port) == 0)
+			if (pe[port].src_cap_cnt == 0)
 				pd_dpm_request(port, DPM_REQUEST_GET_SRC_CAPS);
 
 			set_state_pe(port, PE_SRC_READY);
 		} else {
 			/* NOTE: First pass through this code block */
-			/* Send PS_RDY message */
-			send_ctrl_msg(port, TCPC_TX_SOP, PD_CTRL_PS_RDY);
-			PE_SET_FLAG(port, PE_FLAGS_PS_READY);
+			/* Wait for tSrcTransition before changing supply. */
+			pd_timer_enable(port, PE_TIMER_SRC_TRANSITION,
+					PD_T_SRC_TRANSITION);
 		}
 
 		return;
 	}
 
+	if (pd_timer_is_expired(port, PE_TIMER_SRC_TRANSITION)) {
+		pd_timer_disable(port, PE_TIMER_SRC_TRANSITION);
+		/* Transition power supply and send PS_RDY. */
+		pd_transition_voltage(pe[port].requested_idx);
+		send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_PS_RDY);
+		PE_SET_FLAG(port, PE_FLAGS_PS_READY);
+	}
+
 	/*
 	 * Transition to the PE_SRC_Hard_Reset state when:
 	 *  1) A Protocol Error occurs.
 	 */
 	if (PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) {
 		PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
-		set_state_pe(port, PE_SRC_HARD_RESET);
+		pe_set_hard_reset(port);
 	}
 }
 
+static void pe_src_transition_supply_exit(int port)
+{
+	pd_timer_disable(port, PE_TIMER_SRC_TRANSITION);
+}
+
 /*
  * Transitions state after receiving a Not Supported extended message. Under
  * appropriate conditions, transitions to a PE_{SRC,SNK}_Chunk_Received.
@@ -2192,13 +2817,13 @@ static void extended_message_not_supported(int port, uint32_t *payload)
 	uint16_t ext_header = GET_EXT_HEADER(*payload);
 
 	if (IS_ENABLED(CONFIG_USB_PD_REV30) &&
-			!IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES) &&
-			PD_EXT_HEADER_CHUNKED(ext_header) &&
-			PD_EXT_HEADER_DATA_SIZE(ext_header) >
-			PD_MAX_EXTENDED_MSG_CHUNK_LEN) {
-		set_state_pe(port,
-				pe[port].power_role == PD_ROLE_SOURCE ?
-				PE_SRC_CHUNK_RECEIVED : PE_SNK_CHUNK_RECEIVED);
+	    !IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES) &&
+	    PD_EXT_HEADER_CHUNKED(ext_header) &&
+	    PD_EXT_HEADER_DATA_SIZE(ext_header) >
+		    PD_MAX_EXTENDED_MSG_CHUNK_LEN) {
+		set_state_pe(port, pe[port].power_role == PD_ROLE_SOURCE ?
+					   PE_SRC_CHUNK_RECEIVED :
+					   PE_SNK_CHUNK_RECEIVED);
 		return;
 	}
 
@@ -2213,7 +2838,11 @@ static void pe_src_ready_entry(int port)
 	print_current_state(port);
 
 	/* Ensure any message send flags are cleaned up */
-	PE_CLR_FLAG(port, PE_FLAGS_READY_CLR);
+	PE_CLR_MASK(port, PE_MASK_READY_CLR);
+
+	/* If configured, clear any stale hard reset events */
+	if (IS_ENABLED(CONFIG_USB_PD_CLEAR_HARD_RESET_STATUS))
+		pd_clear_events(port, PD_STATUS_EVENT_HARD_RESET);
 
 	/* Clear DPM Current Request */
 	pe[port].dpm_curr_request = 0;
@@ -2227,15 +2856,6 @@ static void pe_src_ready_entry(int port)
 
 static void pe_src_ready_run(int port)
 {
-	/*
-	 * Don't delay handling a hard reset from the device policy manager.
-	 */
-	if (PE_CHK_DPM_REQUEST(port, DPM_REQUEST_HARD_RESET_SEND)) {
-		pe_set_dpm_curr_request(port, DPM_REQUEST_HARD_RESET_SEND);
-		set_state_pe(port, PE_SRC_HARD_RESET);
-		return;
-	}
-
 	/*
 	 * Handle incoming messages before discovery and DPMs other than hard
 	 * reset
@@ -2258,7 +2878,7 @@ static void pe_src_ready_run(int port)
 			case PD_EXT_GET_BATTERY_STATUS:
 				set_state_pe(port, PE_GIVE_BATTERY_STATUS);
 				break;
-#endif /* CONFIG_USB_PD_EXTENDED_MESSAGES && CONFIG_BATTERY*/
+#endif /* CONFIG_USB_PD_EXTENDED_MESSAGES && CONFIG_BATTERY */
 			default:
 				extended_message_not_supported(port, payload);
 			}
@@ -2273,19 +2893,25 @@ static void pe_src_ready_run(int port)
 			case PD_DATA_SINK_CAP:
 				break;
 			case PD_DATA_VENDOR_DEF:
-				if (PD_HEADER_TYPE(rx_emsg[port].header) ==
-							PD_DATA_VENDOR_DEF) {
-					if (PD_VDO_SVDM(*payload)) {
-						set_state_pe(port,
-							PE_VDM_RESPONSE);
-					} else
-						set_state_pe(port,
-						PE_HANDLE_CUSTOM_VDM_REQUEST);
-				}
+				if (PD_VDO_SVDM(*payload))
+					set_state_pe(port, PE_VDM_RESPONSE);
+				/* The TCPM does not support any unstructured
+				 * VDMs. For PD 3.x, send Not Supported. For
+				 * PD 2.0, ignore.
+				 */
+				else if (prl_get_rev(port, TCPCI_MSG_SOP) >
+					 PD_REV20)
+					set_state_pe(port,
+						     PE_SEND_NOT_SUPPORTED);
 				return;
 			case PD_DATA_BIST:
 				set_state_pe(port, PE_BIST_TX);
 				return;
+#ifdef CONFIG_USB_PD_REV30
+			case PD_DATA_ALERT:
+				set_state_pe(port, PE_ALERT_RECEIVED);
+				return;
+#endif /* CONFIG_USB_PD_REV30 */
 			default:
 				set_state_pe(port, PE_SEND_NOT_SUPPORTED);
 				return;
@@ -2310,12 +2936,12 @@ static void pe_src_ready_run(int port)
 				break;
 			case PD_CTRL_PR_SWAP:
 				set_state_pe(port,
-					PE_PRS_SRC_SNK_EVALUATE_SWAP);
+					     PE_PRS_SRC_SNK_EVALUATE_SWAP);
 				return;
 			case PD_CTRL_DR_SWAP:
 				if (PE_CHK_FLAG(port,
 						PE_FLAGS_MODAL_OPERATION)) {
-					set_state_pe(port, PE_SRC_HARD_RESET);
+					pe_set_hard_reset(port);
 					return;
 				}
 
@@ -2324,10 +2950,10 @@ static void pe_src_ready_run(int port)
 			case PD_CTRL_VCONN_SWAP:
 				if (IS_ENABLED(CONFIG_USBC_VCONN))
 					set_state_pe(port,
-							PE_VCS_EVALUATE_SWAP);
+						     PE_VCS_EVALUATE_SWAP);
 				else
 					set_state_pe(port,
-							PE_SEND_NOT_SUPPORTED);
+						     PE_SEND_NOT_SUPPORTED);
 				return;
 			/*
 			 * USB PD 3.0 6.8.1:
@@ -2338,13 +2964,33 @@ static void pe_src_ready_run(int port)
 			case PD_CTRL_REJECT:
 			case PD_CTRL_WAIT:
 			case PD_CTRL_PS_RDY:
-				pe_send_soft_reset(port,
-				  PD_HEADER_GET_SOP(rx_emsg[port].header));
+				pe_send_soft_reset(
+					port, PD_HEADER_GET_SOP(
+						      rx_emsg[port].header));
 				return;
-			/*
-			 * Receiving an unknown or unsupported message
-			 * shall be responded to with a not supported message.
-			 */
+#ifdef CONFIG_USB_PD_DATA_RESET_MSG
+			case PD_CTRL_DATA_RESET:
+				if (pe[port].data_role == PD_ROLE_DFP)
+					set_state_pe(
+						port,
+						PE_DDR_DATA_RESET_RECEIVED);
+				else
+					set_state_pe(
+						port,
+						PE_UDR_DATA_RESET_RECEIVED);
+				return;
+#endif /* CONFIG_USB_PD_DATA_RESET_MSG */
+#ifdef CONFIG_USB_PD_EXTENDED_MESSAGES
+			case PD_CTRL_GET_STATUS:
+				set_state_pe(port, PE_GIVE_STATUS);
+				return;
+#endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
+				/*
+				 * Receiving an unknown or unsupported message
+				 * shall be responded to with a not supported
+				 * message.
+				 */
+
 			default:
 				set_state_pe(port, PE_SEND_NOT_SUPPORTED);
 				return;
@@ -2366,91 +3012,40 @@ static void pe_src_ready_run(int port)
 	}
 
 	if (PE_CHK_FLAG(port, PE_FLAGS_WAITING_PR_SWAP) &&
-		get_time().val > pe[port].pr_swap_wait_timer) {
+	    pd_timer_is_expired(port, PE_TIMER_PR_SWAP_WAIT)) {
 		PE_CLR_FLAG(port, PE_FLAGS_WAITING_PR_SWAP);
 		PE_SET_DPM_REQUEST(port, DPM_REQUEST_PR_SWAP);
 	}
 
-	if (pe[port].wait_and_add_jitter_timer == TIMER_DISABLED ||
-		get_time().val > pe[port].wait_and_add_jitter_timer) {
-
+	if (pd_timer_is_disabled(port, PE_TIMER_WAIT_AND_ADD_JITTER) ||
+	    pd_timer_is_expired(port, PE_TIMER_WAIT_AND_ADD_JITTER)) {
 		PE_CLR_FLAG(port, PE_FLAGS_FIRST_MSG);
-		pe[port].wait_and_add_jitter_timer = TIMER_DISABLED;
-
-		/*
-		 * Attempt discovery if possible, and return if state was
-		 * changed for that discovery.
-		 */
-		if (pe_attempt_port_discovery(port))
-			return;
+		pd_timer_disable(port, PE_TIMER_WAIT_AND_ADD_JITTER);
 
 		/*
 		 * Handle Device Policy Manager Requests
 		 */
+		if (source_dpm_requests(port))
+			return;
 
 		/*
-		 * Ignore sink specific request:
-		 *   DPM_REQUEST_NEW_POWER_LEVEL
-		 *   DPM_REQUEST_SOURCE_CAP
+		 * Attempt discovery if possible, and return if state was
+		 * changed for that discovery.
 		 */
-
-		PE_CLR_DPM_REQUEST(port, DPM_REQUEST_NEW_POWER_LEVEL |
-					DPM_REQUEST_SOURCE_CAP);
-
-		if (pe[port].dpm_request) {
-			uint32_t dpm_request = pe[port].dpm_request;
-
-			PE_SET_FLAG(port, PE_FLAGS_LOCALLY_INITIATED_AMS);
-
-			if (PE_CHK_DPM_REQUEST(port,
-						DPM_REQUEST_DR_SWAP)) {
-				pe_set_dpm_curr_request(port,
-						DPM_REQUEST_DR_SWAP);
-				if (PE_CHK_FLAG(port, PE_FLAGS_MODAL_OPERATION))
-					set_state_pe(port, PE_SRC_HARD_RESET);
-				else
-					set_state_pe(port, PE_DRS_SEND_SWAP);
-			} else if (PE_CHK_DPM_REQUEST(port,
-						DPM_REQUEST_PR_SWAP)) {
-				pe_set_dpm_curr_request(port,
-						DPM_REQUEST_PR_SWAP);
-				set_state_pe(port, PE_PRS_SRC_SNK_SEND_SWAP);
-			} else if (PE_CHK_DPM_REQUEST(port,
-						DPM_REQUEST_GOTO_MIN)) {
-				pe_set_dpm_curr_request(port,
-						DPM_REQUEST_GOTO_MIN);
-				set_state_pe(port, PE_SRC_TRANSITION_SUPPLY);
-			} else if (PE_CHK_DPM_REQUEST(port,
-						DPM_REQUEST_SRC_CAP_CHANGE)) {
-				pe_set_dpm_curr_request(port,
-						DPM_REQUEST_SRC_CAP_CHANGE);
-				set_state_pe(port, PE_SRC_SEND_CAPABILITIES);
-			} else if (PE_CHK_DPM_REQUEST(port,
-						DPM_REQUEST_GET_SRC_CAPS)) {
-				pe_set_dpm_curr_request(port,
-						DPM_REQUEST_GET_SRC_CAPS);
-				set_state_pe(port, PE_DR_SRC_GET_SOURCE_CAP);
-			} else if (PE_CHK_DPM_REQUEST(port,
-						DPM_REQUEST_SEND_PING)) {
-				pe_set_dpm_curr_request(port,
-						DPM_REQUEST_SEND_PING);
-				set_state_pe(port, PE_SRC_PING);
-			} else if (!common_src_snk_dpm_requests(port)) {
-				CPRINTF("Unhandled DPM Request %x received\n",
-					dpm_request);
-				PE_CLR_DPM_REQUEST(port, dpm_request);
-				PE_CLR_FLAG(port,
-					PE_FLAGS_LOCALLY_INITIATED_AMS);
-			}
-
+		if (pe_attempt_port_discovery(port))
 			return;
-		}
 
-		/* No DPM requests; attempt mode entry/exit if needed */
-		dpm_run(port);
+		/* Inform DPM state machine that PE is set for messages */
+		dpm_set_pe_ready(port, true);
 	}
 }
 
+static void pe_src_ready_exit(int port)
+{
+	/* Inform DPM state machine that PE is in ready state */
+	dpm_set_pe_ready(port, false);
+}
+
 /**
  * PE_SRC_Disabled
  */
@@ -2458,7 +3053,8 @@ static void pe_src_disabled_entry(int port)
 {
 	print_current_state(port);
 
-	if ((pe[port].vpd_vdo >= 0) && VPD_VDO_CTS(pe[port].vpd_vdo)) {
+	if ((get_usb_pd_cable_type(port) == IDH_PTYPE_VPD) &&
+	    is_vpd_ct_supported(port)) {
 		/*
 		 * Inform the Device Policy Manager that a Charge-Through VCONN
 		 * Powered Device was detected.
@@ -2466,6 +3062,9 @@ static void pe_src_disabled_entry(int port)
 		tc_ctvpd_detected(port);
 	}
 
+	if (pd_get_power_role(port) == PD_ROLE_SOURCE)
+		dpm_add_non_pd_sink(port);
+
 	/*
 	 * Unresponsive to USB Power Delivery messaging, but not to Hard Reset
 	 * Signaling. See pe_got_hard_reset
@@ -2481,7 +3080,7 @@ static void pe_src_capability_response_entry(int port)
 
 	/* NOTE: Wait messaging should be implemented. */
 
-	send_ctrl_msg(port, TCPC_TX_SOP, PD_CTRL_REJECT);
+	send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_REJECT);
 }
 
 static void pe_src_capability_response_run(int port)
@@ -2539,15 +3138,13 @@ static void pe_src_hard_reset_entry(int port)
 	pe[port].hard_reset_counter++;
 
 	/* Start NoResponseTimer */
-	pe[port].no_response_timer = get_time().val + PD_T_NO_RESPONSE;
+	pd_timer_enable(port, PE_TIMER_NO_RESPONSE, PD_T_NO_RESPONSE);
 
 	/* Start PSHardResetTimer */
-	pe[port].ps_hard_reset_timer = get_time().val + PD_T_PS_HARD_RESET;
+	pd_timer_enable(port, PE_TIMER_PS_HARD_RESET, PD_T_PS_HARD_RESET);
 
 	/* Clear error flags */
-	PE_CLR_FLAG(port, PE_FLAGS_VDM_REQUEST_NAKED |
-			  PE_FLAGS_PROTOCOL_ERROR |
-			  PE_FLAGS_VDM_REQUEST_BUSY);
+	PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
 }
 
 static void pe_src_hard_reset_run(int port)
@@ -2556,10 +3153,15 @@ static void pe_src_hard_reset_run(int port)
 	 * Transition to the PE_SRC_Transition_to_default state when:
 	 *  1) The PSHardResetTimer times out.
 	 */
-	if (get_time().val > pe[port].ps_hard_reset_timer)
+	if (pd_timer_is_expired(port, PE_TIMER_PS_HARD_RESET))
 		set_state_pe(port, PE_SRC_TRANSITION_TO_DEFAULT);
 }
 
+static void pe_src_hard_reset_exit(int port)
+{
+	pd_timer_disable(port, PE_TIMER_PS_HARD_RESET);
+}
+
 /**
  * PE_SRC_Hard_Reset_Received
  */
@@ -2568,10 +3170,10 @@ static void pe_src_hard_reset_received_entry(int port)
 	print_current_state(port);
 
 	/* Start NoResponseTimer */
-	pe[port].no_response_timer = get_time().val + PD_T_NO_RESPONSE;
+	pd_timer_enable(port, PE_TIMER_NO_RESPONSE, PD_T_NO_RESPONSE);
 
 	/* Start PSHardResetTimer */
-	pe[port].ps_hard_reset_timer = get_time().val + PD_T_PS_HARD_RESET;
+	pd_timer_enable(port, PE_TIMER_PS_HARD_RESET, PD_T_PS_HARD_RESET);
 }
 
 static void pe_src_hard_reset_received_run(int port)
@@ -2580,10 +3182,15 @@ static void pe_src_hard_reset_received_run(int port)
 	 * Transition to the PE_SRC_Transition_to_default state when:
 	 *  1) The PSHardResetTimer times out.
 	 */
-	if (get_time().val > pe[port].ps_hard_reset_timer)
+	if (pd_timer_is_expired(port, PE_TIMER_PS_HARD_RESET))
 		set_state_pe(port, PE_SRC_TRANSITION_TO_DEFAULT);
 }
 
+static void pe_src_hard_reset_received_exit(int port)
+{
+	pd_timer_disable(port, PE_TIMER_PS_HARD_RESET);
+}
+
 /**
  * PE_SRC_Transition_To_Default
  */
@@ -2592,7 +3199,7 @@ static void pe_src_transition_to_default_entry(int port)
 	print_current_state(port);
 
 	/* Reset flags */
-	pe[port].flags = 0;
+	memset(&pe[port].flags_a, 0, sizeof(pe[port].flags_a));
 
 	/* Reset DPM Request */
 	pe[port].dpm_request = 0;
@@ -2629,7 +3236,7 @@ static void pe_snk_startup_entry(int port)
 	print_current_state(port);
 
 	/* Reset the protocol layer */
-	prl_reset(port);
+	prl_reset_soft(port);
 
 	/* Set initial data role */
 	pe[port].data_role = pd_get_data_role(port);
@@ -2640,17 +3247,47 @@ static void pe_snk_startup_entry(int port)
 	/* Invalidate explicit contract */
 	pe_invalidate_explicit_contract(port);
 
+	/* Clear any pending PD events */
+	pe_clear_ado(port);
+
 	if (PE_CHK_FLAG(port, PE_FLAGS_PR_SWAP_COMPLETE)) {
 		PE_CLR_FLAG(port, PE_FLAGS_PR_SWAP_COMPLETE);
+		/*
+		 * Protocol layer reset clears the message IDs for all SOP
+		 * types. Indicate that a SOP' soft reset is required before any
+		 * other messages are sent to the cable.
+		 *
+		 * Note that other paths into this state are for the initial
+		 * connection and for a hard reset. In both cases the cable
+		 * should also automatically clear the message IDs so don't
+		 * generate an SOP' soft reset for those cases. Sending
+		 * unnecessary SOP' soft resets causes bad behavior with
+		 * some devices. See b/179325862.
+		 */
+		pd_dpm_request(port, DPM_REQUEST_SOP_PRIME_SOFT_RESET_SEND);
+
+		/*
+		 * Some port partners may violate spec and attempt to
+		 * communicate with the cable after power role swaps, despite
+		 * not being Vconn source.  Disable our SOP' receiving here to
+		 * avoid GoodCRC-ing any erroneous cable probes, and re-enable
+		 * after our contract is in place.
+		 */
+		if (tc_is_vconn_src(port))
+			tcpm_sop_prime_enable(port, false);
+
+		dpm_remove_sink(port);
 	} else {
 		/*
 		 * Set DiscoverIdentityTimer to trigger when we enter
 		 * snk_ready for the first time.
 		 */
-		pe[port].discover_identity_timer = get_time().val;
+		pd_timer_enable(port, PE_TIMER_DISCOVER_IDENTITY, 0);
 
-		/* Clear port discovery flags */
+		/* Clear port discovery/mode flags */
 		pd_dfp_discovery_init(port);
+		pd_dfp_mode_init(port);
+		dpm_init(port);
 		pe[port].discover_identity_counter = 0;
 
 		/* Reset dr swap attempt counter */
@@ -2665,6 +3302,25 @@ static void pe_snk_startup_entry(int port)
 		PE_SET_FLAG(port, PE_FLAGS_DR_SWAP_TO_DFP);
 		PE_SET_FLAG(port, PE_FLAGS_VCONN_SWAP_TO_ON);
 	}
+
+	/*
+	 * Request sink caps for FRS, output power consideration, or reporting
+	 * to the AP through host commands.
+	 *
+	 * On entry to the PE_SNK_Ready state if the Sink supports Fast Role
+	 * Swap, then the Policy Engine Shall do the following:
+	 * - Send a Get_Sink_Cap Message
+	 */
+	if (IS_ENABLED(CONFIG_USB_PD_HOST_CMD) || CONFIG_USB_PD_3A_PORTS > 0 ||
+	    IS_ENABLED(CONFIG_USB_PD_FRS))
+		pd_dpm_request(port, DPM_REQUEST_GET_SNK_CAPS);
+
+	/*
+	 * Request partner's revision information. The PE_Get_Revision
+	 * state will only send Get_Revision to partners with major
+	 * revision 3.0
+	 */
+	pd_dpm_request(port, DPM_REQUEST_GET_REVISION);
 }
 
 static void pe_snk_startup_run(int port)
@@ -2694,7 +3350,7 @@ static void pe_snk_discovery_run(int port)
 	 * Transition to the PE_SNK_Wait_for_Capabilities state when:
 	 *   1) VBUS has been detected
 	 */
-	if (pd_is_vbus_present(port))
+	if (!pd_check_vbus_level(port, VBUS_REMOVED))
 		set_state_pe(port, PE_SNK_WAIT_FOR_CAPABILITIES);
 }
 
@@ -2706,7 +3362,7 @@ static void pe_snk_wait_for_capabilities_entry(int port)
 	print_current_state(port);
 
 	/* Initialize and start the SinkWaitCapTimer */
-	pe[port].timeout = get_time().val + PD_T_SINK_WAIT_CAP;
+	pd_timer_enable(port, PE_TIMER_TIMEOUT, PD_T_SINK_WAIT_CAP);
 }
 
 static void pe_snk_wait_for_capabilities_run(int port)
@@ -2714,6 +3370,7 @@ static void pe_snk_wait_for_capabilities_run(int port)
 	uint8_t type;
 	uint8_t cnt;
 	uint8_t ext;
+	uint32_t *payload;
 
 	/*
 	 * Transition to the PE_SNK_Evaluate_Capability state when:
@@ -2725,20 +3382,39 @@ static void pe_snk_wait_for_capabilities_run(int port)
 		type = PD_HEADER_TYPE(rx_emsg[port].header);
 		cnt = PD_HEADER_CNT(rx_emsg[port].header);
 		ext = PD_HEADER_EXT(rx_emsg[port].header);
+		payload = (uint32_t *)rx_emsg[port].buf;
 
 		if ((ext == 0) && (cnt > 0) && (type == PD_DATA_SOURCE_CAP)) {
 			set_state_pe(port, PE_SNK_EVALUATE_CAPABILITY);
 			return;
+		} else if (ext > 0) {
+			switch (type) {
+#ifdef CONFIG_USB_PD_EPR
+			case PD_EXT_EPR_SOURCE_CAP:
+				if (!pe_snk_in_epr_mode(port))
+					break;
+				set_state_pe(port, PE_SNK_EVALUATE_CAPABILITY);
+				break;
+#endif /* CONFIG_USB_PD_EPR */
+			default:
+				extended_message_not_supported(port, payload);
+			}
+			return;
 		}
 	}
 
 	/* When the SinkWaitCapTimer times out, perform a Hard Reset. */
-	if (get_time().val > pe[port].timeout) {
+	if (pd_timer_is_expired(port, PE_TIMER_TIMEOUT)) {
 		PE_SET_FLAG(port, PE_FLAGS_SNK_WAIT_CAP_TIMEOUT);
-		set_state_pe(port, PE_SNK_HARD_RESET);
+		pe_set_hard_reset(port);
 	}
 }
 
+static void pe_snk_wait_for_capabilities_exit(int port)
+{
+	pd_timer_disable(port, PE_TIMER_TIMEOUT);
+}
+
 /**
  * PE_SNK_Evaluate_Capability State
  */
@@ -2753,26 +3429,38 @@ static void pe_snk_evaluate_capability_entry(int port)
 	pe[port].hard_reset_counter = 0;
 
 	/* Set to highest revision supported by both ports. */
-	prl_set_rev(port, TCPC_TX_SOP,
-			MIN(PD_REVISION, PD_HEADER_REV(rx_emsg[port].header)));
+	prl_set_rev(port, TCPCI_MSG_SOP,
+		    MIN(PD_REVISION, PD_HEADER_REV(rx_emsg[port].header)));
 
-	/*
-	 * If port partner runs PD 2.0, cable communication must
-	 * also be PD 2.0
-	 */
-	if (prl_get_rev(port, TCPC_TX_SOP) == PD_REV20)
-		prl_set_rev(port, TCPC_TX_SOP_PRIME, PD_REV20);
+	init_cable_rev(port);
 
-	pd_set_src_caps(port, num, pdo);
+	/* Parse source caps if they have changed */
+	if (pe[port].src_cap_cnt != num ||
+	    memcmp(pdo, pe[port].src_caps, num << 2)) {
+		/*
+		 * If port policy preference is to be a power role source,
+		 * then request a power role swap.  If we'd previously queued a
+		 * PR swap but can now charge from this device, clear it.
+		 */
+		if (!pd_can_charge_from_device(port, num, pdo))
+			pd_request_power_swap(port);
+		else
+			PE_CLR_DPM_REQUEST(port, DPM_REQUEST_PR_SWAP);
+	}
 
-	/* src cap 0 should be fixed PDO */
-	pe_update_pdo_flags(port, pdo[0]);
+	pe_update_src_pdo_flags(port, num, pdo);
+	pd_set_src_caps(port, num, pdo);
 
 	/* Evaluate the options based on supplied capabilities */
 	pd_process_source_cap(port, pe[port].src_cap_cnt, pe[port].src_caps);
 
 	/* Device Policy Response Received */
 	set_state_pe(port, PE_SNK_SELECT_CAPABILITY);
+
+#ifdef HAS_TASK_DPS
+	/* Wake DPS task to evaluate the SrcCaps */
+	task_wake(TASK_ID_DPS);
+#endif
 }
 
 /**
@@ -2791,11 +3479,31 @@ static void pe_snk_select_capability_entry(int port)
 	tc_pd_connection(port, 1);
 }
 
+static void pe_snk_apply_psnkstdby(int port)
+{
+	uint32_t mv = pd_get_requested_voltage(port);
+	uint32_t high;
+
+	/*
+	 * Apply 2.5W ceiling during transition. We need choose the larger of
+	 * the current input voltage and the new PDO voltage because during a
+	 * transition, both voltages can be applied to the device. If the
+	 * current source isn't PD, we don't need to care about drawing more
+	 * than pSnkStdby. Thus, it's not considered (in the else clause).
+	 */
+	if (charge_manager_get_supplier() == CHARGE_SUPPLIER_PD)
+		high = MAX(charge_manager_get_charger_voltage(), mv);
+	else
+		high = mv;
+	charge_manager_force_ceil(
+		port, high > 0 ? PD_SNK_STDBY_MW * 1000 / high : PD_MIN_MA);
+}
+
 static void pe_snk_select_capability_run(int port)
 {
 	uint8_t type;
 	uint8_t cnt;
-	enum tcpm_transmit_type sop;
+	enum tcpci_msg_type sop;
 	enum pe_msg_check msg_check;
 
 	/*
@@ -2815,7 +3523,7 @@ static void pe_snk_select_capability_run(int port)
 		 * 2) SE_SNK_READY: goes back to SNK Ready
 		 */
 		if (get_last_state_pe(port) == PE_SNK_EVALUATE_CAPABILITY)
-			pe_send_soft_reset(port, TCPC_TX_SOP);
+			pe_send_soft_reset(port, TCPCI_MSG_SOP);
 		else
 			set_state_pe(port, PE_SNK_READY);
 		return;
@@ -2855,25 +3563,23 @@ static void pe_snk_select_capability_run(int port)
 				/* explicit contract is now in place */
 				pe_set_explicit_contract(port);
 
+				if (IS_ENABLED(CONFIG_CHARGE_MANAGER))
+					pe_snk_apply_psnkstdby(port);
+
 				set_state_pe(port, PE_SNK_TRANSITION_SINK);
 
-				/*
-				 * Setup to get Device Policy Manager to
-				 * request Sink Capabilities for possible FRS
-				 */
-				if (IS_ENABLED(CONFIG_USB_PD_FRS))
-					pd_dpm_request(port,
-						DPM_REQUEST_GET_SNK_CAPS);
 				return;
 			}
 			/*
 			 * Reject or Wait Message Received
 			 */
 			else if (type == PD_CTRL_REJECT ||
-							type == PD_CTRL_WAIT) {
+				 type == PD_CTRL_WAIT) {
 				if (type == PD_CTRL_WAIT)
 					PE_SET_FLAG(port, PE_FLAGS_WAIT);
 
+				pd_timer_disable(port, PE_TIMER_SINK_REQUEST);
+
 				/*
 				 * We had a previous explicit contract, so
 				 * transition to PE_SNK_Ready
@@ -2886,7 +3592,8 @@ static void pe_snk_select_capability_run(int port)
 				 * to PE_SNK_Wait_For_Capabilities
 				 */
 				else
-					set_state_pe(port,
+					set_state_pe(
+						port,
 						PE_SNK_WAIT_FOR_CAPABILITIES);
 				return;
 			}
@@ -2910,8 +3617,13 @@ static void pe_snk_select_capability_run(int port)
 	}
 
 	/* SenderResponsetimer timeout */
-	if (get_time().val > pe[port].sender_response_timer)
-		set_state_pe(port, PE_SNK_HARD_RESET);
+	if (pd_timer_is_expired(port, PE_TIMER_SENDER_RESPONSE))
+		pe_set_hard_reset(port);
+}
+
+void pe_snk_select_capability_exit(int port)
+{
+	pe_sender_response_msg_exit(port);
 }
 
 /**
@@ -2922,7 +3634,7 @@ static void pe_snk_transition_sink_entry(int port)
 	print_current_state(port);
 
 	/* Initialize and run PSTransitionTimer */
-	pe[port].ps_transition_timer = get_time().val + PD_T_PS_TRANSITION;
+	pd_timer_enable(port, PE_TIMER_PS_TRANSITION, PD_T_PS_TRANSITION);
 }
 
 static void pe_snk_transition_sink_run(int port)
@@ -2942,57 +3654,86 @@ static void pe_snk_transition_sink_run(int port)
 		 * PS_RDY message received
 		 */
 		if ((PD_HEADER_CNT(rx_emsg[port].header) == 0) &&
-			   (PD_HEADER_TYPE(rx_emsg[port].header) ==
-			   PD_CTRL_PS_RDY)) {
+		    (PD_HEADER_TYPE(rx_emsg[port].header) == PD_CTRL_PS_RDY)) {
 			/*
 			 * Set first message flag to trigger a wait and add
 			 * jitter delay when operating in PD2.0 mode.
 			 */
 			PE_SET_FLAG(port, PE_FLAGS_FIRST_MSG);
+			pd_timer_disable(port, PE_TIMER_WAIT_AND_ADD_JITTER);
+
+			/*
+			 * If we've successfully completed our new power
+			 * contract, ensure SOP' communication is enabled before
+			 * entering PE_SNK_READY.  It may have been disabled
+			 * during a power role swap to avoid interoperability
+			 * issues with out-of-spec partners.
+			 */
+			if (tc_is_vconn_src(port))
+				tcpm_sop_prime_enable(port, true);
+
+			/*
+			 * Evaluate port's sink caps for FRS current, if
+			 * already available
+			 */
+			if (pd_get_snk_cap_cnt(port) > 0)
+				dpm_evaluate_sink_fixed_pdo(
+					port, *pd_get_snk_caps(port));
 
 			set_state_pe(port, PE_SNK_READY);
-			return;
+		} else {
+			/*
+			 * Protocol Error
+			 */
+			pe_set_hard_reset(port);
 		}
-
-		/*
-		 * Protocol Error
-		 */
-		set_state_pe(port, PE_SNK_HARD_RESET);
+		return;
 	}
 
 	/*
 	 * Timeout will lead to a Hard Reset
 	 */
-	if (get_time().val > pe[port].ps_transition_timer &&
-			pe[port].hard_reset_counter <= N_HARD_RESET_COUNT) {
+	if (pd_timer_is_expired(port, PE_TIMER_PS_TRANSITION) &&
+	    pe[port].hard_reset_counter <= N_HARD_RESET_COUNT) {
 		PE_SET_FLAG(port, PE_FLAGS_PS_TRANSITION_TIMEOUT);
 
-		set_state_pe(port, PE_SNK_HARD_RESET);
+		pe_set_hard_reset(port);
 	}
 }
 
 static void pe_snk_transition_sink_exit(int port)
 {
 	/* Transition Sink's power supply to the new power level */
-	pd_set_input_current_limit(port,
-				pe[port].curr_limit, pe[port].supply_voltage);
+	pd_set_input_current_limit(port, pe[port].curr_limit,
+				   pe[port].supply_voltage);
 
 	if (IS_ENABLED(CONFIG_CHARGE_MANAGER))
 		/* Set ceiling based on what's negotiated */
-		charge_manager_set_ceil(port,
-				CEIL_REQUESTOR_PD, pe[port].curr_limit);
-}
+		charge_manager_set_ceil(port, CEIL_REQUESTOR_PD,
+					pe[port].curr_limit);
+
+	pd_timer_disable(port, PE_TIMER_PS_TRANSITION);
 
+	if (IS_ENABLED(CONFIG_USB_PD_DPS))
+		if (charge_manager_get_active_charge_port() == port)
+			dps_update_stabilized_time(port);
+}
 
 /**
  * PE_SNK_Ready State
  */
 static void pe_snk_ready_entry(int port)
 {
-	print_current_state(port);
+	if (get_last_state_pe(port) != PE_SNK_EPR_KEEP_ALIVE) {
+		print_current_state(port);
+	}
 
 	/* Ensure any message send flags are cleaned up */
-	PE_CLR_FLAG(port, PE_FLAGS_READY_CLR);
+	PE_CLR_MASK(port, PE_MASK_READY_CLR);
+
+	/* If configured, clear any stale hard reset events */
+	if (IS_ENABLED(CONFIG_USB_PD_CLEAR_HARD_RESET_STATUS))
+		pd_clear_events(port, PD_STATUS_EVENT_HARD_RESET);
 
 	/* Clear DPM Current Request */
 	pe[port].dpm_curr_request = 0;
@@ -3004,10 +3745,7 @@ static void pe_snk_ready_entry(int port)
 	 */
 	if (PE_CHK_FLAG(port, PE_FLAGS_WAIT)) {
 		PE_CLR_FLAG(port, PE_FLAGS_WAIT);
-		pe[port].sink_request_timer =
-				get_time().val + PD_T_SINK_REQUEST;
-	} else {
-		pe[port].sink_request_timer = TIMER_DISABLED;
+		pd_timer_enable(port, PE_TIMER_SINK_REQUEST, PD_T_SINK_REQUEST);
 	}
 
 	/*
@@ -3015,19 +3753,18 @@ static void pe_snk_ready_entry(int port)
 	 * have been sent since enter this state.
 	 */
 	pe_update_wait_and_add_jitter_timer(port);
+
+	if (IS_ENABLED(CONFIG_USB_PD_EPR)) {
+		if (pe_snk_in_epr_mode(port))
+			pd_timer_enable(port, PE_TIMER_SINK_EPR_KEEP_ALIVE,
+					PD_T_SINK_EPR_KEEP_ALIVE);
+		else if (!PE_CHK_FLAG(port, PE_FLAGS_EPR_EXPLICIT_EXIT))
+			pd_dpm_request(port, DPM_REQUEST_EPR_MODE_ENTRY);
+	}
 }
 
 static void pe_snk_ready_run(int port)
 {
-	/*
-	 * Don't delay handling a hard reset from the device policy manager.
-	 */
-	if (PE_CHK_DPM_REQUEST(port, DPM_REQUEST_HARD_RESET_SEND)) {
-		pe_set_dpm_curr_request(port, DPM_REQUEST_HARD_RESET_SEND);
-		set_state_pe(port, PE_SNK_HARD_RESET);
-		return;
-	}
-
 	/*
 	 * Handle incoming messages before discovery and DPMs other than hard
 	 * reset
@@ -3050,6 +3787,13 @@ static void pe_snk_ready_run(int port)
 			case PD_EXT_GET_BATTERY_STATUS:
 				set_state_pe(port, PE_GIVE_BATTERY_STATUS);
 				break;
+#ifdef CONFIG_USB_PD_EPR
+			case PD_EXT_EPR_SOURCE_CAP:
+				if (!pe_snk_in_epr_mode(port))
+					break;
+				set_state_pe(port, PE_SNK_EVALUATE_CAPABILITY);
+				break;
+#endif /* CONFIG_USB_PD_EPR */
 #endif /* CONFIG_USB_PD_EXTENDED_MESSAGES && CONFIG_BATTERY */
 			default:
 				extended_message_not_supported(port, payload);
@@ -3060,27 +3804,43 @@ static void pe_snk_ready_run(int port)
 		else if (cnt > 0) {
 			switch (type) {
 			case PD_DATA_SOURCE_CAP:
-				set_state_pe(port,
-					PE_SNK_EVALUATE_CAPABILITY);
-				break;
+				set_state_pe(port, PE_SNK_EVALUATE_CAPABILITY);
+				return;
 			case PD_DATA_VENDOR_DEF:
-				if (PD_HEADER_TYPE(rx_emsg[port].header) ==
-							PD_DATA_VENDOR_DEF) {
-					if (PD_VDO_SVDM(*payload))
-						set_state_pe(port,
-							PE_VDM_RESPONSE);
-					else
-						set_state_pe(port,
-						PE_HANDLE_CUSTOM_VDM_REQUEST);
-				}
-				break;
+				if (PD_VDO_SVDM(*payload))
+					set_state_pe(port, PE_VDM_RESPONSE);
+				/* The TCPM does not support any unstructured
+				 * VDMs. For PD 3.x, send Not Supported. For
+				 * PD 2.0, ignore.
+				 */
+				else if (prl_get_rev(port, TCPCI_MSG_SOP) >
+					 PD_REV20)
+					set_state_pe(port,
+						     PE_SEND_NOT_SUPPORTED);
+				return;
 			case PD_DATA_BIST:
 				set_state_pe(port, PE_BIST_TX);
-				break;
+				return;
+#ifdef CONFIG_USB_PD_REV30
+			case PD_DATA_ALERT:
+				set_state_pe(port, PE_ALERT_RECEIVED);
+				return;
+#ifdef CONFIG_USB_PD_EPR
+			case PD_DATA_EPR_MODE:
+				struct eprmdo *mdo = (void *)payload;
+
+				if (mdo->action == PD_EPRMDO_ACTION_EXIT) {
+					set_state_pe(
+						port,
+						PE_SNK_EPR_MODE_EXIT_RECEIVED);
+				}
+				return;
+#endif /* CONFIG_USB_PD_EPR */
+#endif /* CONFIG_USB_PD_REV30 */
 			default:
 				set_state_pe(port, PE_SEND_NOT_SUPPORTED);
+				return;
 			}
-			return;
 		}
 		/* Control Messages */
 		else {
@@ -3102,23 +3862,40 @@ static void pe_snk_ready_run(int port)
 				return;
 			case PD_CTRL_PR_SWAP:
 				set_state_pe(port,
-						PE_PRS_SNK_SRC_EVALUATE_SWAP);
+					     PE_PRS_SNK_SRC_EVALUATE_SWAP);
 				return;
 			case PD_CTRL_DR_SWAP:
 				if (PE_CHK_FLAG(port, PE_FLAGS_MODAL_OPERATION))
-					set_state_pe(port, PE_SNK_HARD_RESET);
+					pe_set_hard_reset(port);
 				else
 					set_state_pe(port,
-							PE_DRS_EVALUATE_SWAP);
+						     PE_DRS_EVALUATE_SWAP);
 				return;
 			case PD_CTRL_VCONN_SWAP:
 				if (IS_ENABLED(CONFIG_USBC_VCONN))
 					set_state_pe(port,
-							PE_VCS_EVALUATE_SWAP);
+						     PE_VCS_EVALUATE_SWAP);
 				else
 					set_state_pe(port,
-							PE_SEND_NOT_SUPPORTED);
+						     PE_SEND_NOT_SUPPORTED);
+				return;
+#ifdef CONFIG_USB_PD_DATA_RESET_MSG
+			case PD_CTRL_DATA_RESET:
+				if (pe[port].data_role == PD_ROLE_DFP)
+					set_state_pe(
+						port,
+						PE_DDR_DATA_RESET_RECEIVED);
+				else
+					set_state_pe(
+						port,
+						PE_UDR_DATA_RESET_RECEIVED);
+				return;
+#endif /* CONFIG_USB_PD_DATA_RESET_MSG */
+#ifdef CONFIG_USB_PD_EXTENDED_MESSAGES
+			case PD_CTRL_GET_STATUS:
+				set_state_pe(port, PE_GIVE_STATUS);
 				return;
+#endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
 			case PD_CTRL_NOT_SUPPORTED:
 				/* Do nothing */
 				break;
@@ -3131,8 +3908,9 @@ static void pe_snk_ready_run(int port)
 			case PD_CTRL_REJECT:
 			case PD_CTRL_WAIT:
 			case PD_CTRL_PS_RDY:
-				pe_send_soft_reset(port,
-				  PD_HEADER_GET_SOP(rx_emsg[port].header));
+				pe_send_soft_reset(
+					port, PD_HEADER_GET_SOP(
+						      rx_emsg[port].header));
 				return;
 			/*
 			 * Receiving an unknown or unsupported message
@@ -3158,84 +3936,47 @@ static void pe_snk_ready_run(int port)
 		return;
 	}
 
-	if (pe[port].wait_and_add_jitter_timer == TIMER_DISABLED ||
-		get_time().val > pe[port].wait_and_add_jitter_timer) {
+	if (pd_timer_is_disabled(port, PE_TIMER_WAIT_AND_ADD_JITTER) ||
+	    pd_timer_is_expired(port, PE_TIMER_WAIT_AND_ADD_JITTER)) {
 		PE_CLR_FLAG(port, PE_FLAGS_FIRST_MSG);
-		pe[port].wait_and_add_jitter_timer = TIMER_DISABLED;
+		pd_timer_disable(port, PE_TIMER_WAIT_AND_ADD_JITTER);
 
-		if (get_time().val > pe[port].sink_request_timer) {
+		if (pd_timer_is_expired(port, PE_TIMER_SINK_REQUEST)) {
+			pd_timer_disable(port, PE_TIMER_SINK_REQUEST);
 			set_state_pe(port, PE_SNK_SELECT_CAPABILITY);
 			return;
 		}
 
 		/*
-		 * Attempt discovery if possible, and return if state was
-		 * changed for that discovery.
+		 * Handle Device Policy Manager Requests
 		 */
-		if (pe_attempt_port_discovery(port))
+		if (sink_dpm_requests(port))
 			return;
 
 		/*
-		 * Handle Device Policy Manager Requests
-		 */
-		/*
-		 * Ignore source specific requests:
-		 *   DPM_REQUEST_GOTO_MIN
-		 *   DPM_REQUEST_SRC_CAP_CHANGE,
-		 *   DPM_REQUEST_SEND_PING
+		 * Attempt discovery if possible, and return if state was
+		 * changed for that discovery.
 		 */
-		PE_CLR_DPM_REQUEST(port, DPM_REQUEST_GOTO_MIN |
-					DPM_REQUEST_SRC_CAP_CHANGE |
-					DPM_REQUEST_SEND_PING);
-
-		if (pe[port].dpm_request) {
-			uint32_t dpm_request = pe[port].dpm_request;
-
-			PE_SET_FLAG(port, PE_FLAGS_LOCALLY_INITIATED_AMS);
+		if (pe_attempt_port_discovery(port))
+			return;
 
-			if (PE_CHK_DPM_REQUEST(port,
-						DPM_REQUEST_DR_SWAP)) {
-				pe_set_dpm_curr_request(port,
-						DPM_REQUEST_DR_SWAP);
-				if (PE_CHK_FLAG(port, PE_FLAGS_MODAL_OPERATION))
-					set_state_pe(port, PE_SNK_HARD_RESET);
-				else
-					set_state_pe(port, PE_DRS_SEND_SWAP);
-			} else if (PE_CHK_DPM_REQUEST(port,
-						DPM_REQUEST_PR_SWAP)) {
-				pe_set_dpm_curr_request(port,
-						DPM_REQUEST_PR_SWAP);
-				set_state_pe(port, PE_PRS_SNK_SRC_SEND_SWAP);
-			} else if (PE_CHK_DPM_REQUEST(port,
-						DPM_REQUEST_SOURCE_CAP)) {
-				pe_set_dpm_curr_request(port,
-						DPM_REQUEST_SOURCE_CAP);
-				set_state_pe(port, PE_SNK_GET_SOURCE_CAP);
-			} else if (PE_CHK_DPM_REQUEST(port,
-						DPM_REQUEST_NEW_POWER_LEVEL)) {
-				pe_set_dpm_curr_request(port,
-						DPM_REQUEST_NEW_POWER_LEVEL);
-				set_state_pe(port, PE_SNK_SELECT_CAPABILITY);
-			} else if (IS_ENABLED(CONFIG_USB_PD_FRS) &&
-				   PE_CHK_DPM_REQUEST(port,
-						DPM_REQUEST_GET_SNK_CAPS)) {
-				pe_set_dpm_curr_request(port,
-						DPM_REQUEST_GET_SNK_CAPS);
-				set_state_pe(port, PE_DR_SNK_GET_SINK_CAP);
-			} else if (!common_src_snk_dpm_requests(port)) {
-				CPRINTF("Unhandled DPM Request %x received\n",
-					dpm_request);
-				PE_CLR_DPM_REQUEST(port, dpm_request);
-				PE_CLR_FLAG(port,
-					PE_FLAGS_LOCALLY_INITIATED_AMS);
-			}
+		/* Inform DPM state machine that PE is set for messages */
+		dpm_set_pe_ready(port, true);
 
+		if (pd_timer_is_expired(port, PE_TIMER_SINK_EPR_KEEP_ALIVE)) {
+			set_state_pe(port, PE_SNK_EPR_KEEP_ALIVE);
 			return;
 		}
+	}
+}
 
-		/* No DPM requests; attempt mode entry/exit if needed */
-		dpm_run(port);
+static void pe_snk_ready_exit(int port)
+{
+	/* Inform DPM state machine that PE is in ready state */
+	dpm_set_pe_ready(port, false);
 
+	if (IS_ENABLED(CONFIG_USB_PD_EPR) && pe_snk_in_epr_mode(port)) {
+		pd_timer_disable(port, PE_TIMER_SINK_EPR_KEEP_ALIVE);
 	}
 }
 
@@ -3244,6 +3985,10 @@ static void pe_snk_ready_run(int port)
  */
 static void pe_snk_hard_reset_entry(int port)
 {
+#ifdef CONFIG_USB_PD_RESET_MIN_BATT_SOC
+	int batt_soc;
+#endif
+
 	print_current_state(port);
 
 	/*
@@ -3252,17 +3997,66 @@ static void pe_snk_hard_reset_entry(int port)
 	 *       Source is non-responsive.
 	 */
 	if (PE_CHK_FLAG(port, PE_FLAGS_SNK_WAIT_CAP_TIMEOUT) &&
-			pe[port].hard_reset_counter > N_HARD_RESET_COUNT) {
+	    pe[port].hard_reset_counter > N_HARD_RESET_COUNT) {
+		set_state_pe(port, PE_SRC_DISABLED);
+		return;
+	}
+
+	/*
+	 * If we're about to kill our active charge port and have no battery to
+	 * supply power, disable the PE layer instead.  If we have no battery,
+	 * but we haven't determined our active charge port yet, also avoid
+	 * performing the HardReset.  It might be that this port was our active
+	 * charge port.
+	 *
+	 * Note: On systems without batteries (ex. chromeboxes), it's preferable
+	 * to brown out rather than leave the port only semi-functional for a
+	 * customer.  For systems which should have a battery, this condition is
+	 * not expected to be encountered by a customer.
+	 */
+	if (IS_ENABLED(CONFIG_BATTERY) && (battery_is_present() == BP_NO) &&
+	    IS_ENABLED(CONFIG_CHARGE_MANAGER) &&
+	    ((port == charge_manager_get_active_charge_port() ||
+	      (charge_manager_get_active_charge_port() == CHARGE_PORT_NONE))) &&
+	    system_get_reset_flags() & EC_RESET_FLAG_SYSJUMP) {
+		CPRINTS("C%d: Disabling port to avoid brown out, "
+			"please reboot EC to enable port again",
+			port);
 		set_state_pe(port, PE_SRC_DISABLED);
+		return;
+	}
+
+#ifdef CONFIG_USB_PD_RESET_MIN_BATT_SOC
+	/*
+	 * If the battery has not met a configured safe level for hard
+	 * resets, set state to PE_SRC_Disabled as a hard
+	 * reset could brown out the board.
+	 * Note this may mean that high-power chargers will stay at
+	 * 15W until a reset is sent, depending on boot timing.
+	 *
+	 * PE_FLAGS_SNK_WAITING_BATT flags will be cleared and
+	 * PE state will be switched to PE_SNK_Startup when
+	 * battery reaches CONFIG_USB_PD_RESET_MIN_BATT_SOC.
+	 * See pe_update_waiting_batt_flag() for more details.
+	 */
+	batt_soc = usb_get_battery_soc();
+
+	if (batt_soc < CONFIG_USB_PD_RESET_MIN_BATT_SOC ||
+	    battery_get_disconnect_state() != BATTERY_NOT_DISCONNECTED) {
+		PE_SET_FLAG(port, PE_FLAGS_SNK_WAITING_BATT);
+		CPRINTS("C%d: Battery low %d%%! Stay in disabled state "
+			"until battery level reaches %d%%",
+			port, batt_soc, CONFIG_USB_PD_RESET_MIN_BATT_SOC);
+		set_state_pe(port, PE_SRC_DISABLED);
+		return;
 	}
+#endif
 
-	PE_CLR_FLAG(port, PE_FLAGS_SNK_WAIT_CAP_TIMEOUT |
-			  PE_FLAGS_VDM_REQUEST_NAKED |
-			  PE_FLAGS_PROTOCOL_ERROR |
-			  PE_FLAGS_VDM_REQUEST_BUSY);
+	PE_CLR_MASK(port, BIT(PE_FLAGS_SNK_WAIT_CAP_TIMEOUT_FN) |
+				  BIT(PE_FLAGS_PROTOCOL_ERROR_FN));
 
 	/* Request the generation of Hard Reset Signaling by the PHY Layer */
-	pe_prl_execute_hard_reset(port);
+	prl_execute_hard_reset(port);
 
 	/* Increment the HardResetCounter */
 	pe[port].hard_reset_counter++;
@@ -3276,11 +4070,11 @@ static void pe_snk_hard_reset_entry(int port)
 
 		/* Transition Sink's power supply to the new power level */
 		pd_set_input_current_limit(port, pe[port].curr_limit,
-						pe[port].supply_voltage);
+					   pe[port].supply_voltage);
 		if (IS_ENABLED(CONFIG_CHARGE_MANAGER))
 			/* Set ceiling based on what's negotiated */
 			charge_manager_set_ceil(port, CEIL_REQUESTOR_PD,
-							pe[port].curr_limit);
+						pe[port].curr_limit);
 	}
 }
 
@@ -3303,6 +4097,12 @@ static void pe_snk_transition_to_default_entry(int port)
 {
 	print_current_state(port);
 
+	/* Reset flags */
+	memset(&pe[port].flags_a, 0, sizeof(pe[port].flags_a));
+
+	/* Reset DPM Request */
+	pe[port].dpm_request = 0;
+
 	/* Inform the TC Layer of Hard Reset */
 	tc_hard_reset_request(port);
 }
@@ -3310,8 +4110,7 @@ static void pe_snk_transition_to_default_entry(int port)
 static void pe_snk_transition_to_default_run(int port)
 {
 	if (PE_CHK_FLAG(port, PE_FLAGS_PS_RESET_COMPLETE)) {
-		/* PE_SNK_Startup clears all flags */
-
+		PE_CLR_FLAG(port, PE_FLAGS_PS_RESET_COMPLETE);
 		/* Inform the Protocol Layer that the Hard Reset is complete */
 		prl_hard_reset_complete(port);
 		set_state_pe(port, PE_SNK_STARTUP);
@@ -3327,7 +4126,7 @@ static void pe_snk_get_source_cap_entry(int port)
 
 	/* Send a Get_Source_Cap Message */
 	tx_emsg[port].len = 0;
-	send_ctrl_msg(port, TCPC_TX_SOP, PD_CTRL_GET_SOURCE_CAP);
+	send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_GET_SOURCE_CAP);
 }
 
 static void pe_snk_get_source_cap_run(int port)
@@ -3346,10 +4145,19 @@ static void pe_send_soft_reset_entry(int port)
 {
 	print_current_state(port);
 
+	PE_CLR_FLAG(port, PE_FLAGS_ENTERING_EPR);
+	PE_CLR_FLAG(port, PE_FLAGS_EPR_EXPLICIT_EXIT);
+
 	/* Reset Protocol Layer (softly) */
 	prl_reset_soft(port);
 
-	pe[port].sender_response_timer = TIMER_DISABLED;
+	pe_sender_response_msg_entry(port);
+
+	/*
+	 * Mark the temporary timer PE_TIMER_TIMEOUT as expired to limit
+	 * to sending a single SoftReset message.
+	 */
+	pd_timer_enable(port, PE_TIMER_TIMEOUT, 0);
 }
 
 static void pe_send_soft_reset_run(int port)
@@ -3357,23 +4165,42 @@ static void pe_send_soft_reset_run(int port)
 	int type;
 	int cnt;
 	int ext;
+	enum pe_msg_check msg_check;
 
 	/* Wait until protocol layer is running */
 	if (!prl_is_running(port))
 		return;
 
-	if (pe[port].sender_response_timer == TIMER_DISABLED) {
+	/*
+	 * Protocol layer is running, so need to send a single SoftReset.
+	 * Use temporary timer to act as a flag to keep this as a single
+	 * message send.
+	 */
+	if (!pd_timer_is_disabled(port, PE_TIMER_TIMEOUT)) {
+		pd_timer_disable(port, PE_TIMER_TIMEOUT);
+
 		/*
 		 * TODO(b/150614211): Soft reset type should match
 		 * unexpected incoming message type
 		 */
 		/* Send Soft Reset message */
-		send_ctrl_msg(port,
-			pe[port].soft_reset_sop, PD_CTRL_SOFT_RESET);
+		send_ctrl_msg(port, pe[port].soft_reset_sop,
+			      PD_CTRL_SOFT_RESET);
+
+		return;
+	}
+
+	/*
+	 * Check the state of the message sent
+	 */
+	msg_check = pe_sender_response_msg_run(port);
 
-		/* Initialize and run SenderResponseTimer */
-		pe[port].sender_response_timer =
-					get_time().val + PD_T_SENDER_RESPONSE;
+	/*
+	 * Handle discarded message
+	 */
+	if (msg_check == PE_MSG_DISCARDED) {
+		pe_set_ready_state(port);
+		return;
 	}
 
 	/*
@@ -3381,7 +4208,8 @@ static void pe_send_soft_reset_run(int port)
 	 * PE_SRC_Send_Capabilities state when:
 	 *   1) An Accept Message has been received.
 	 */
-	if (PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
+	if (msg_check == PE_MSG_SENT &&
+	    PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
 		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
 
 		type = PD_HEADER_TYPE(rx_emsg[port].header);
@@ -3391,10 +4219,9 @@ static void pe_send_soft_reset_run(int port)
 		if ((ext == 0) && (cnt == 0) && (type == PD_CTRL_ACCEPT)) {
 			if (pe[port].power_role == PD_ROLE_SINK)
 				set_state_pe(port,
-						PE_SNK_WAIT_FOR_CAPABILITIES);
+					     PE_SNK_WAIT_FOR_CAPABILITIES);
 			else
-				set_state_pe(port,
-						PE_SRC_SEND_CAPABILITIES);
+				set_state_pe(port, PE_SRC_SEND_CAPABILITIES);
 			return;
 		}
 	}
@@ -3403,17 +4230,18 @@ static void pe_send_soft_reset_run(int port)
 	 * Transition to PE_SNK_Hard_Reset or PE_SRC_Hard_Reset on Sender
 	 * Response Timer Timeout or Protocol Layer or Protocol Error
 	 */
-	if (get_time().val > pe[port].sender_response_timer ||
-			PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) {
+	if (pd_timer_is_expired(port, PE_TIMER_SENDER_RESPONSE) ||
+	    PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) {
 		PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
-
-		if (pe[port].power_role == PD_ROLE_SINK)
-			set_state_pe(port, PE_SNK_HARD_RESET);
-		else
-			set_state_pe(port, PE_SRC_HARD_RESET);
+		pe_set_hard_reset(port);
 		return;
 	}
+}
 
+static void pe_send_soft_reset_exit(int port)
+{
+	pe_sender_response_msg_exit(port);
+	pd_timer_disable(port, PE_TIMER_TIMEOUT);
 }
 
 /**
@@ -3423,12 +4251,10 @@ static void pe_soft_reset_entry(int port)
 {
 	print_current_state(port);
 
-	pe[port].sender_response_timer = TIMER_DISABLED;
-
-	send_ctrl_msg(port, TCPC_TX_SOP, PD_CTRL_ACCEPT);
+	send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_ACCEPT);
 }
 
-static void  pe_soft_reset_run(int port)
+static void pe_soft_reset_run(int port)
 {
 	if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
 		PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
@@ -3439,11 +4265,7 @@ static void  pe_soft_reset_run(int port)
 			set_state_pe(port, PE_SRC_SEND_CAPABILITIES);
 	} else if (PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) {
 		PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
-
-		if (pe[port].power_role == PD_ROLE_SINK)
-			set_state_pe(port, PE_SNK_HARD_RESET);
-		else
-			set_state_pe(port, PE_SRC_HARD_RESET);
+		pe_set_hard_reset(port);
 	}
 }
 
@@ -3461,10 +4283,10 @@ static void pe_send_not_supported_entry(int port)
 	print_current_state(port);
 
 	/* Request the Protocol Layer to send a Not_Supported Message. */
-	if (prl_get_rev(port, TCPC_TX_SOP) > PD_REV20)
-		send_ctrl_msg(port, TCPC_TX_SOP, PD_CTRL_NOT_SUPPORTED);
+	if (prl_get_rev(port, TCPCI_MSG_SOP) > PD_REV20)
+		send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_NOT_SUPPORTED);
 	else
-		send_ctrl_msg(port, TCPC_TX_SOP, PD_CTRL_REJECT);
+		send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_REJECT);
 }
 
 static void pe_send_not_supported_run(int port)
@@ -3472,11 +4294,9 @@ static void pe_send_not_supported_run(int port)
 	if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
 		PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
 		pe_set_ready_state(port);
-
 	}
 }
 
-#if defined(CONFIG_USB_PD_REV30) && !defined(CONFIG_USB_PD_EXTENDED_MESSAGES)
 /**
  * PE_SRC_Chunk_Received and PE_SNK_Chunk_Received
  *
@@ -3491,19 +4311,31 @@ static void pe_send_not_supported_run(int port)
  * 6.6.18.1 ChunkingNotSupportedTimer
  * 8.3.3.6  Not Supported Message State Diagrams
  */
-static void pe_chunk_received_entry(int port)
+__maybe_unused static void pe_chunk_received_entry(int port)
 {
+	if (!IS_ENABLED(CONFIG_USB_PD_REV30) ||
+	    IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES))
+		assert(0);
+
 	print_current_state(port);
-	pe[port].chunking_not_supported_timer =
-		get_time().val + PD_T_CHUNKING_NOT_SUPPORTED;
+	pd_timer_enable(port, PE_TIMER_CHUNKING_NOT_SUPPORTED,
+			PD_T_CHUNKING_NOT_SUPPORTED);
 }
 
-static void pe_chunk_received_run(int port)
+__maybe_unused static void pe_chunk_received_run(int port)
 {
-	if (get_time().val > pe[port].chunking_not_supported_timer)
+	if (!IS_ENABLED(CONFIG_USB_PD_REV30) ||
+	    IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES))
+		assert(0);
+
+	if (pd_timer_is_expired(port, PE_TIMER_CHUNKING_NOT_SUPPORTED))
 		set_state_pe(port, PE_SEND_NOT_SUPPORTED);
 }
-#endif
+
+__maybe_unused static void pe_chunk_received_exit(int port)
+{
+	pd_timer_disable(port, PE_TIMER_CHUNKING_NOT_SUPPORTED);
+}
 
 /**
  * PE_SRC_Ping
@@ -3511,7 +4343,7 @@ static void pe_chunk_received_run(int port)
 static void pe_src_ping_entry(int port)
 {
 	print_current_state(port);
-	send_ctrl_msg(port, TCPC_TX_SOP, PD_CTRL_PING);
+	send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_PING);
 }
 
 static void pe_src_ping_run(int port)
@@ -3528,55 +4360,86 @@ static void pe_src_ping_run(int port)
  */
 static void pe_give_battery_cap_entry(int port)
 {
-	uint32_t payload = *(uint32_t *)(&rx_emsg[port].buf);
+	uint8_t *payload = rx_emsg[port].buf;
 	uint16_t *msg = (uint16_t *)tx_emsg[port].buf;
 
 	if (!IS_ENABLED(CONFIG_BATTERY))
 		return;
 	print_current_state(port);
 
-	/* msg[0] - extended header is set by Protocol Layer */
-
 	/* Set VID */
-	msg[1] = USB_VID_GOOGLE;
+	msg[BCDB_VID] = USB_VID_GOOGLE;
 
 	/* Set PID */
-	msg[2] = CONFIG_USB_PID;
+	msg[BCDB_PID] = CONFIG_USB_PID;
 
-	if (battery_is_present()) {
+	/*
+	 * We only have one fixed battery,
+	 * so make sure batt cap ref is 0.
+	 * This value is the first byte after the headers.
+	 */
+	if (payload[0] != 0) {
 		/*
-		 * We only have one fixed battery,
-		 * so make sure batt cap ref is 0.
+		 * If the Battery Cap Ref field in the Get_Battery_Cap
+		 * Message is Invalid, this VID field Shall be 0xFFFF.
+		 *
+		 * When the VID Is 0xFFFF the PID field Shall be set to
+		 * 0x0000.
 		 */
-		if (BATT_CAP_REF(payload) != 0) {
-			/* Invalid battery reference */
-			msg[3] = 0;
-			msg[4] = 0;
-			msg[5] = 1;
-		} else {
-			uint32_t v;
-			uint32_t c;
+		msg[BCDB_VID] = 0xffff;
+		msg[BCDB_PID] = 0;
+		/* Invalid battery reference */
+		msg[BCDB_DESIGN_CAP] = 0;
+		msg[BCDB_FULL_CAP] = 0;
+		/* Set invalid battery bit in response bit 0, byte 8 */
+		msg[BCDB_BATT_TYPE] = 1;
+	} else if (battery_is_present()) {
+		/*
+		 * The Battery Design Capacity field shall return the
+		 * Battery’s design capacity in tenths of Wh. If the
+		 * Battery is Hot Swappable and is not present, the
+		 * Battery Design Capacity field shall be set to 0. If
+		 * the Battery is unable to report its Design Capacity,
+		 * it shall return 0xFFFF
+		 */
+		msg[BCDB_DESIGN_CAP] = 0xffff;
+
+		/*
+		 * The Battery Last Full Charge Capacity field shall
+		 * return the Battery’s last full charge capacity in
+		 * tenths of Wh. If the Battery is Hot Swappable and
+		 * is not present, the Battery Last Full Charge Capacity
+		 * field shall be set to 0. If the Battery is unable to
+		 * report its Design Capacity, the Battery Last Full
+		 * Charge Capacity field shall be set to 0xFFFF.
+		 */
+		msg[BCDB_FULL_CAP] = 0xffff;
+
+		if (IS_ENABLED(HAS_TASK_HOSTCMD) &&
+		    *host_get_memmap(EC_MEMMAP_BATTERY_VERSION) != 0) {
+			int design_volt, design_cap, full_cap;
+
+			design_volt =
+				*(int *)host_get_memmap(EC_MEMMAP_BATT_DVLT);
+			design_cap =
+				*(int *)host_get_memmap(EC_MEMMAP_BATT_DCAP);
+			full_cap = *(int *)host_get_memmap(EC_MEMMAP_BATT_LFCC);
 
 			/*
-			 * The Battery Design Capacity field shall return the
-			 * Battery’s design capacity in tenths of Wh. If the
-			 * Battery is Hot Swappable and is not present, the
-			 * Battery Design Capacity field shall be set to 0. If
-			 * the Battery is unable to report its Design Capacity,
-			 * it shall return 0xFFFF
+			 * Wh = (c * v) / 1000000
+			 * 10th of a Wh = Wh * 10
 			 */
-			msg[3] = 0xffff;
-
+			msg[BCDB_DESIGN_CAP] = DIV_ROUND_NEAREST(
+				(design_cap * design_volt), 100000);
 			/*
-			 * The Battery Last Full Charge Capacity field shall
-			 * return the Battery’s last full charge capacity in
-			 * tenths of Wh. If the Battery is Hot Swappable and
-			 * is not present, the Battery Last Full Charge Capacity
-			 * field shall be set to 0. If the Battery is unable to
-			 * report its Design Capacity, the Battery Last Full
-			 * Charge Capacity field shall be set to 0xFFFF.
+			 * Wh = (c * v) / 1000000
+			 * 10th of a Wh = Wh * 10
 			 */
-			msg[4] = 0xffff;
+			msg[BCDB_FULL_CAP] = DIV_ROUND_NEAREST(
+				(design_cap * full_cap), 100000);
+		} else {
+			uint32_t v;
+			uint32_t c;
 
 			if (battery_design_voltage(&v) == 0) {
 				if (battery_design_capacity(&c) == 0) {
@@ -3584,8 +4447,9 @@ static void pe_give_battery_cap_entry(int port)
 					 * Wh = (c * v) / 1000000
 					 * 10th of a Wh = Wh * 10
 					 */
-					msg[3] = DIV_ROUND_NEAREST((c * v),
-								100000);
+					msg[BCDB_DESIGN_CAP] =
+						DIV_ROUND_NEAREST((c * v),
+								  100000);
 				}
 
 				if (battery_full_charge_capacity(&c) == 0) {
@@ -3593,17 +4457,24 @@ static void pe_give_battery_cap_entry(int port)
 					 * Wh = (c * v) / 1000000
 					 * 10th of a Wh = Wh * 10
 					 */
-					msg[4] = DIV_ROUND_NEAREST((c * v),
-								100000);
+					msg[BCDB_FULL_CAP] = DIV_ROUND_NEAREST(
+						(c * v), 100000);
 				}
 			}
 		}
+		/* Valid battery selected */
+		msg[BCDB_BATT_TYPE] = 0;
+	} else {
+		/* Battery not present indicated by 0's in the capacity */
+		msg[BCDB_DESIGN_CAP] = 0;
+		msg[BCDB_FULL_CAP] = 0;
+		msg[BCDB_BATT_TYPE] = 0;
 	}
 
 	/* Extended Battery Cap data is 9 bytes */
 	tx_emsg[port].len = 9;
 
-	send_ext_data_msg(port, TCPC_TX_SOP, PD_EXT_BATTERY_CAP);
+	send_ext_data_msg(port, TCPCI_MSG_SOP, PD_EXT_BATTERY_CAP);
 }
 
 static void pe_give_battery_cap_run(int port)
@@ -3619,7 +4490,7 @@ static void pe_give_battery_cap_run(int port)
  */
 static void pe_give_battery_status_entry(int port)
 {
-	uint32_t payload = *(uint32_t *)(&rx_emsg[port].buf);
+	uint8_t *payload = rx_emsg[port].buf;
 	uint32_t *msg = (uint32_t *)tx_emsg[port].buf;
 
 	if (!IS_ENABLED(CONFIG_BATTERY))
@@ -3630,24 +4501,38 @@ static void pe_give_battery_status_entry(int port)
 		/*
 		 * We only have one fixed battery,
 		 * so make sure batt cap ref is 0.
+		 * This value is the first byte after the headers.
 		 */
-		if (BATT_CAP_REF(payload) != 0) {
+		if (payload[0] != 0) {
 			/* Invalid battery reference */
+			*msg = BSDO_CAP(BSDO_CAP_UNKNOWN);
 			*msg |= BSDO_INVALID;
 		} else {
 			uint32_t v;
 			uint32_t c;
 
-			if (battery_design_voltage(&v) != 0 ||
-					battery_remaining_capacity(&c) != 0) {
-				*msg |= BSDO_CAP(BSDO_CAP_UNKNOWN);
-			} else {
+			*msg = BSDO_CAP(BSDO_CAP_UNKNOWN);
+
+			if (IS_ENABLED(HAS_TASK_HOSTCMD) &&
+			    *host_get_memmap(EC_MEMMAP_BATTERY_VERSION) != 0) {
+				v = *(int *)host_get_memmap(
+					EC_MEMMAP_BATT_DVLT);
+				c = *(int *)host_get_memmap(EC_MEMMAP_BATT_CAP);
+
 				/*
 				 * Wh = (c * v) / 1000000
 				 * 10th of a Wh = Wh * 10
 				 */
-				*msg |= BSDO_CAP(DIV_ROUND_NEAREST((c * v),
-								100000));
+				*msg = BSDO_CAP(
+					DIV_ROUND_NEAREST((c * v), 100000));
+			} else if (battery_design_voltage(&v) == 0 &&
+				   battery_remaining_capacity(&c) == 0) {
+				/*
+				 * Wh = (c * v) / 1000000
+				 * 10th of a Wh = Wh * 10
+				 */
+				*msg = BSDO_CAP(
+					DIV_ROUND_NEAREST((c * v), 100000));
 			}
 
 			/* Battery is present */
@@ -3672,12 +4557,14 @@ static void pe_give_battery_status_entry(int port)
 		}
 	} else {
 		*msg = BSDO_CAP(BSDO_CAP_UNKNOWN);
+		if (payload[0] != 0)
+			*msg |= BSDO_INVALID;
 	}
 
 	/* Battery Status data is 4 bytes */
 	tx_emsg[port].len = 4;
 
-	send_data_msg(port, TCPC_TX_SOP, PD_DATA_BATTERY_STATUS);
+	send_data_msg(port, TCPCI_MSG_SOP, PD_DATA_BATTERY_STATUS);
 }
 
 static void pe_give_battery_status_run(int port)
@@ -3688,6 +4575,37 @@ static void pe_give_battery_status_run(int port)
 	}
 }
 
+/**
+ * PE_SRC_Give_Source_Status and
+ * PE_SNK_Give_Sink_Status
+ */
+static void pe_give_status_entry(int port)
+{
+	uint8_t *msg = (uint8_t *)tx_emsg[port].buf;
+	uint32_t *len = &tx_emsg[port].len;
+
+	print_current_state(port);
+	if (dpm_get_status_msg(port, msg, len) != EC_SUCCESS) {
+		pe_set_ready_state(port);
+		return;
+	}
+
+	send_ext_data_msg(port, TCPCI_MSG_SOP, PD_EXT_STATUS);
+}
+
+static void pe_give_status_run(int port)
+{
+	if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
+		PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
+		pe_set_ready_state(port);
+	} else if (PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR) ||
+		   PE_CHK_FLAG(port, PE_FLAGS_MSG_DISCARDED)) {
+		PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
+		PE_CLR_FLAG(port, PE_FLAGS_MSG_DISCARDED);
+		pe_send_soft_reset(port, TCPCI_MSG_SOP);
+	}
+}
+
 /**
  * PE_SRC_Send_Source_Alert and
  * PE_SNK_Send_Sink_Alert
@@ -3699,24 +4617,53 @@ static void pe_send_alert_entry(int port)
 
 	print_current_state(port);
 
-	if (pd_build_alert_msg(msg, len, pe[port].power_role) != EC_SUCCESS)
+	if (msg == NULL || len == NULL) {
 		pe_set_ready_state(port);
+	} else {
+		/* Get ADO from PE state, the ADO is a uint32_t */
+		mutex_lock(&pe[port].ado_lock);
+		*msg = pe[port].ado;
+		*len = sizeof(pe[port].ado);
+		mutex_unlock(&pe[port].ado_lock);
+	}
 
 	/* Request the Protocol Layer to send Alert Message. */
-	send_data_msg(port, TCPC_TX_SOP, PD_DATA_ALERT);
+	send_data_msg(port, TCPCI_MSG_SOP, PD_DATA_ALERT);
 }
 
 static void pe_send_alert_run(int port)
 {
 	if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
 		PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
+		pe_clear_ado(port);
+		pe_set_ready_state(port);
+		return;
+	} else if (PE_CHK_FLAG(port, PE_FLAGS_MSG_DISCARDED)) {
+		PE_CLR_FLAG(port, PE_FLAGS_MSG_DISCARDED);
+		pd_dpm_request(port, DPM_REQUEST_SEND_ALERT);
 		pe_set_ready_state(port);
+		return;
 	}
 }
+
+/**
+ * PE_SNK_Source_Alert_Received and
+ * PE_SRC_Sink_Alert_Received
+ */
+static void pe_alert_received_entry(int port)
+{
+	uint32_t *ado = (uint32_t *)rx_emsg[port].buf;
+
+	print_current_state(port);
+	dpm_handle_alert(port, *ado);
+	pe_set_ready_state(port);
+}
+
 #endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
 
 /**
  * PE_DRS_Evaluate_Swap
+ * PE_DRS_UFP_DFP_Evaluate_Swap and PE_DRS_DFP_UFP_Evaluate_Swap embedded here.
  */
 static void pe_drs_evaluate_swap_entry(int port)
 {
@@ -3726,16 +4673,24 @@ static void pe_drs_evaluate_swap_entry(int port)
 	if (pd_check_data_swap(port, pe[port].data_role)) {
 		PE_SET_FLAG(port, PE_FLAGS_ACCEPT);
 		/*
-		 * PE_DRS_UFP_DFP_Evaluate_Swap and
-		 * PE_DRS_DFP_UFP_Evaluate_Swap states embedded here.
+		 * PE_DRS_UFP_DFP_Accept_Swap and
+		 * PE_DRS_DFP_UFP_Accept_Swap states embedded here.
 		 */
-		send_ctrl_msg(port, TCPC_TX_SOP, PD_CTRL_ACCEPT);
+		send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_ACCEPT);
+		/*
+		 * The PD spec implies that the PE transitions through
+		 * PE_DRS_*_Accept_Swap and PE_DRS_Change and updates the data
+		 * role instantaneously, but this PE doesn't. During the
+		 * transition, do not validate the data role of incoming
+		 * messages, in case the port partner transitioned faster.
+		 */
+		prl_set_data_role_check(port, false);
 	} else {
 		/*
 		 * PE_DRS_UFP_DFP_Reject_Swap and PE_DRS_DFP_UFP_Reject_Swap
 		 * states embedded here.
 		 */
-		send_ctrl_msg(port, TCPC_TX_SOP, PD_CTRL_REJECT);
+		send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_REJECT);
 	}
 }
 
@@ -3781,6 +4736,7 @@ static void pe_drs_change_run(int port)
 
 	/* Update the data role */
 	pe[port].data_role = pd_get_data_role(port);
+	prl_set_data_role_check(port, true);
 
 	if (pe[port].data_role == PD_ROLE_DFP)
 		PE_CLR_FLAG(port, PE_FLAGS_DR_SWAP_TO_DFP);
@@ -3804,7 +4760,7 @@ static void pe_drs_send_swap_entry(int port)
 	 * states embedded here.
 	 */
 	/* Request the Protocol Layer to send a DR_Swap Message */
-	send_ctrl_msg(port, TCPC_TX_SOP, PD_CTRL_DR_SWAP);
+	send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_DR_SWAP);
 	pe_sender_response_msg_entry(port);
 }
 
@@ -3841,8 +4797,8 @@ static void pe_drs_send_swap_run(int port)
 				set_state_pe(port, PE_DRS_CHANGE);
 				return;
 			} else if ((type == PD_CTRL_REJECT) ||
-					(type == PD_CTRL_WAIT) ||
-					(type == PD_CTRL_NOT_SUPPORTED)) {
+				   (type == PD_CTRL_WAIT) ||
+				   (type == PD_CTRL_NOT_SUPPORTED)) {
 				pe_set_ready_state(port);
 				return;
 			}
@@ -3855,10 +4811,15 @@ static void pe_drs_send_swap_run(int port)
 	 *   2) Message was discarded.
 	 */
 	if ((msg_check & PE_MSG_DISCARDED) ||
-	    get_time().val > pe[port].sender_response_timer)
+	    pd_timer_is_expired(port, PE_TIMER_SENDER_RESPONSE))
 		pe_set_ready_state(port);
 }
 
+static void pe_drs_send_swap_exit(int port)
+{
+	pe_sender_response_msg_exit(port);
+}
+
 /**
  * PE_PRS_SRC_SNK_Evaluate_Swap
  */
@@ -3868,12 +4829,12 @@ static void pe_prs_src_snk_evaluate_swap_entry(int port)
 
 	if (!pd_check_power_swap(port)) {
 		/* PE_PRS_SRC_SNK_Reject_PR_Swap state embedded here */
-		send_ctrl_msg(port, TCPC_TX_SOP, PD_CTRL_REJECT);
+		send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_REJECT);
 	} else {
 		tc_request_power_swap(port);
 		/* PE_PRS_SRC_SNK_Accept_Swap state embedded here */
 		PE_SET_FLAG(port, PE_FLAGS_ACCEPT);
-		send_ctrl_msg(port, TCPC_TX_SOP, PD_CTRL_ACCEPT);
+		send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_ACCEPT);
 	}
 }
 
@@ -3885,6 +4846,12 @@ static void pe_prs_src_snk_evaluate_swap_run(int port)
 		if (PE_CHK_FLAG(port, PE_FLAGS_ACCEPT)) {
 			PE_CLR_FLAG(port, PE_FLAGS_ACCEPT);
 
+			/*
+			 * Clear any pending DPM power role swap request so we
+			 * don't trigger a power role swap request back to src
+			 * power role.
+			 */
+			PE_CLR_DPM_REQUEST(port, DPM_REQUEST_PR_SWAP);
 			/*
 			 * Power Role Swap OK, transition to
 			 * PE_PRS_SRC_SNK_Transition_to_off
@@ -3907,21 +4874,50 @@ static void pe_prs_src_snk_transition_to_off_entry(int port)
 	/* Contract is invalid */
 	pe_invalidate_explicit_contract(port);
 
-	/* Tell TypeC to power off the source */
-	tc_src_power_off(port);
-
-	pe[port].ps_source_timer =
-			get_time().val + PD_POWER_SUPPLY_TURN_OFF_DELAY;
+	pd_timer_enable(port, PE_TIMER_SRC_TRANSITION, PD_T_SRC_TRANSITION);
 }
 
 static void pe_prs_src_snk_transition_to_off_run(int port)
 {
+	/*
+	 * This is a non-interruptible AMS and power is transitioning - hard
+	 * reset on interruption.
+	 */
+	if (PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
+		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
+
+		tc_pr_swap_complete(port, 0);
+		pe_set_hard_reset(port);
+		return;
+	}
+
+	/* Wait tSrcTransition (~ 25ms) before turning off VBUS */
+	if (!pd_timer_is_expired(port, PE_TIMER_SRC_TRANSITION))
+		return;
+
+	if (!PE_CHK_FLAG(port, PE_FLAGS_SRC_SNK_SETTLE)) {
+		PE_SET_FLAG(port, PE_FLAGS_SRC_SNK_SETTLE);
+		/* Tell TypeC to power off the source */
+		tc_src_power_off(port);
+
+		pd_timer_enable(port, PE_TIMER_PS_SOURCE,
+				PD_POWER_SUPPLY_TURN_OFF_DELAY);
+		return;
+	}
+
 	/* Give time for supply to power off */
-	if (get_time().val > pe[port].ps_source_timer &&
+	if (pd_timer_is_expired(port, PE_TIMER_PS_SOURCE) &&
 	    pd_check_vbus_level(port, VBUS_SAFE0V))
 		set_state_pe(port, PE_PRS_SRC_SNK_ASSERT_RD);
 }
 
+static void pe_prs_src_snk_transition_to_off_exit(int port)
+{
+	PE_CLR_FLAG(port, PE_FLAGS_SRC_SNK_SETTLE);
+	pd_timer_disable(port, PE_TIMER_SRC_TRANSITION);
+	pd_timer_disable(port, PE_TIMER_PS_SOURCE);
+}
+
 /**
  * PE_PRS_SRC_SNK_Assert_Rd
  */
@@ -3946,44 +4942,45 @@ static void pe_prs_src_snk_assert_rd_run(int port)
 static void pe_prs_src_snk_wait_source_on_entry(int port)
 {
 	print_current_state(port);
-	send_ctrl_msg(port, TCPC_TX_SOP, PD_CTRL_PS_RDY);
-	pe[port].ps_source_timer = TIMER_DISABLED;
+	send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_PS_RDY);
 }
 
 static void pe_prs_src_snk_wait_source_on_run(int port)
 {
-	int type;
-	int cnt;
-	int ext;
-
-	if (pe[port].ps_source_timer == TIMER_DISABLED &&
-			PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
+	if (pd_timer_is_disabled(port, PE_TIMER_PS_SOURCE) &&
+	    PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
 		PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
 
 		/* Update pe power role */
 		pe[port].power_role = pd_get_power_role(port);
-		pe[port].ps_source_timer = get_time().val + PD_T_PS_SOURCE_ON;
+		pd_timer_enable(port, PE_TIMER_PS_SOURCE, PD_T_PS_SOURCE_ON);
 	}
 
 	/*
 	 * Transition to PE_SNK_Startup when:
 	 *   1) A PS_RDY Message is received.
 	 */
-	if (pe[port].ps_source_timer != TIMER_DISABLED &&
-			PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
-		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
+	if (!pd_timer_is_disabled(port, PE_TIMER_PS_SOURCE) &&
+	    PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
+		int type = PD_HEADER_TYPE(rx_emsg[port].header);
+		int cnt = PD_HEADER_CNT(rx_emsg[port].header);
+		int ext = PD_HEADER_EXT(rx_emsg[port].header);
 
-		type = PD_HEADER_TYPE(rx_emsg[port].header);
-		cnt = PD_HEADER_CNT(rx_emsg[port].header);
-		ext = PD_HEADER_EXT(rx_emsg[port].header);
+		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
 
 		if ((ext == 0) && (cnt == 0) && (type == PD_CTRL_PS_RDY)) {
-			pe[port].ps_source_timer = TIMER_DISABLED;
-
 			PE_SET_FLAG(port, PE_FLAGS_PR_SWAP_COMPLETE);
 			set_state_pe(port, PE_SNK_STARTUP);
-			return;
+		} else {
+			int sop = PD_HEADER_GET_SOP(rx_emsg[port].header);
+			/*
+			 * USB PD 3.0 6.8.1:
+			 * Receiving an unexpected message shall be responded
+			 * to with a soft reset message.
+			 */
+			pe_send_soft_reset(port, sop);
 		}
+		return;
 	}
 
 	/*
@@ -3991,7 +4988,7 @@ static void pe_prs_src_snk_wait_source_on_run(int port)
 	 *   1) The PSSourceOnTimer times out.
 	 *   2) PS_RDY not sent after retries.
 	 */
-	if (get_time().val > pe[port].ps_source_timer ||
+	if (pd_timer_is_expired(port, PE_TIMER_PS_SOURCE) ||
 	    PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) {
 		PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
 
@@ -4002,8 +4999,8 @@ static void pe_prs_src_snk_wait_source_on_run(int port)
 
 static void pe_prs_src_snk_wait_source_on_exit(int port)
 {
-	tc_pr_swap_complete(port,
-			    PE_CHK_FLAG(port, PE_FLAGS_PR_SWAP_COMPLETE));
+	pd_timer_disable(port, PE_TIMER_PS_SOURCE);
+	tc_pr_swap_complete(port, PE_CHK_FLAG(port, PE_FLAGS_PR_SWAP_COMPLETE));
 }
 
 /**
@@ -4013,8 +5010,11 @@ static void pe_prs_src_snk_send_swap_entry(int port)
 {
 	print_current_state(port);
 
+	/* Making an attempt to PR_Swap, clear we were possibly waiting */
+	pd_timer_disable(port, PE_TIMER_PR_SWAP_WAIT);
+
 	/* Request the Protocol Layer to send a PR_Swap Message. */
-	send_ctrl_msg(port, TCPC_TX_SOP, PD_CTRL_PR_SWAP);
+	send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_PR_SWAP);
 	pe_sender_response_msg_entry(port);
 }
 
@@ -4051,7 +5051,7 @@ static void pe_prs_src_snk_send_swap_run(int port)
 				pe[port].src_snk_pr_swap_counter = 0;
 				tc_request_power_swap(port);
 				set_state_pe(port,
-					PE_PRS_SRC_SNK_TRANSITION_TO_OFF);
+					     PE_PRS_SRC_SNK_TRANSITION_TO_OFF);
 			} else if (type == PD_CTRL_REJECT) {
 				pe[port].src_snk_pr_swap_counter = 0;
 				set_state_pe(port, PE_SRC_READY);
@@ -4059,10 +5059,10 @@ static void pe_prs_src_snk_send_swap_run(int port)
 				if (pe[port].src_snk_pr_swap_counter <
 				    N_SNK_SRC_PR_SWAP_COUNT) {
 					PE_SET_FLAG(port,
-						PE_FLAGS_WAITING_PR_SWAP);
-					pe[port].pr_swap_wait_timer =
-						get_time().val +
-						PD_T_PR_SWAP_WAIT;
+						    PE_FLAGS_WAITING_PR_SWAP);
+					pd_timer_enable(port,
+							PE_TIMER_PR_SWAP_WAIT,
+							PD_T_PR_SWAP_WAIT);
 				}
 				pe[port].src_snk_pr_swap_counter++;
 				set_state_pe(port, PE_SRC_READY);
@@ -4077,10 +5077,15 @@ static void pe_prs_src_snk_send_swap_run(int port)
 	 *   2) Message was discarded.
 	 */
 	if ((msg_check & PE_MSG_DISCARDED) ||
-	    get_time().val > pe[port].sender_response_timer)
+	    pd_timer_is_expired(port, PE_TIMER_SENDER_RESPONSE))
 		set_state_pe(port, PE_SRC_READY);
 }
 
+static void pe_prs_src_snk_send_swap_exit(int port)
+{
+	pe_sender_response_msg_exit(port);
+}
+
 /**
  * PE_PRS_SNK_SRC_Evaluate_Swap
  */
@@ -4097,12 +5102,12 @@ static void pe_prs_snk_src_evaluate_swap_entry(int port)
 
 	if (!pd_check_power_swap(port)) {
 		/* PE_PRS_SNK_SRC_Reject_Swap state embedded here */
-		send_ctrl_msg(port, TCPC_TX_SOP, PD_CTRL_REJECT);
+		send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_REJECT);
 	} else {
 		tc_request_power_swap(port);
 		/* PE_PRS_SNK_SRC_Accept_Swap state embedded here */
 		PE_SET_FLAG(port, PE_FLAGS_ACCEPT);
-		send_ctrl_msg(port, TCPC_TX_SOP, PD_CTRL_ACCEPT);
+		send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_ACCEPT);
 	}
 }
 
@@ -4113,6 +5118,12 @@ static void pe_prs_snk_src_evaluate_swap_run(int port)
 		if (PE_CHK_FLAG(port, PE_FLAGS_ACCEPT)) {
 			PE_CLR_FLAG(port, PE_FLAGS_ACCEPT);
 
+			/*
+			 * Clear any pending DPM power role swap request so we
+			 * don't trigger a power role swap request back to sink
+			 * power role.
+			 */
+			PE_CLR_DPM_REQUEST(port, DPM_REQUEST_PR_SWAP);
 			/*
 			 * Accept message sent, transition to
 			 * PE_PRS_SNK_SRC_Transition_to_off
@@ -4123,6 +5134,19 @@ static void pe_prs_snk_src_evaluate_swap_run(int port)
 			set_state_pe(port, PE_SNK_READY);
 		}
 	}
+
+	if (PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) {
+		PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
+		/*
+		 * Protocol Error occurs while PR swap, this may
+		 * brown out if the port-parnter can't hold VBUS
+		 * for tSrcTransition. Notify TC that we end the PR
+		 * swap and start to watch VBUS.
+		 *
+		 * TODO(b:155181980): issue soft reset on protocol error.
+		 */
+		tc_pr_swap_complete(port, 0);
+	}
 }
 
 /**
@@ -4135,11 +5159,10 @@ static void pe_prs_snk_src_transition_to_off_entry(int port)
 {
 	print_current_state(port);
 
-	if (!IS_ENABLED(CONFIG_USB_PD_REV30) ||
-			!PE_CHK_FLAG(port, PE_FLAGS_FAST_ROLE_SWAP_PATH))
+	if (!IS_ENABLED(CONFIG_USB_PD_REV30) || !pe_in_frs_mode(port))
 		tc_snk_power_off(port);
 
-	pe[port].ps_source_timer = get_time().val + PD_T_PS_SOURCE_OFF;
+	pd_timer_enable(port, PE_TIMER_PS_SOURCE, PD_T_PS_SOURCE_OFF);
 }
 
 static void pe_prs_snk_src_transition_to_off_run(int port)
@@ -4152,7 +5175,7 @@ static void pe_prs_snk_src_transition_to_off_run(int port)
 	 * Transition to ErrorRecovery state when:
 	 *   1) The PSSourceOffTimer times out.
 	 */
-	if (get_time().val > pe[port].ps_source_timer)
+	if (pd_timer_is_expired(port, PE_TIMER_PS_SOURCE))
 		set_state_pe(port, PE_WAIT_FOR_ERROR_RECOVERY);
 
 	/*
@@ -4177,6 +5200,11 @@ static void pe_prs_snk_src_transition_to_off_run(int port)
 	}
 }
 
+static void pe_prs_snk_src_transition_to_off_exit(int port)
+{
+	pd_timer_disable(port, PE_TIMER_PS_SOURCE);
+}
+
 /**
  * PE_PRS_SNK_SRC_Assert_Rp
  * PE_FRS_SNK_SRC_Assert_Rp
@@ -4198,8 +5226,7 @@ static void pe_prs_snk_src_assert_rp_run(int port)
 {
 	/* Wait until TypeC is in the Attached.SRC state */
 	if (tc_is_attached_src(port)) {
-		if (!IS_ENABLED(CONFIG_USB_PD_REV30) ||
-			!PE_CHK_FLAG(port, PE_FLAGS_FAST_ROLE_SWAP_PATH)) {
+		if (!IS_ENABLED(CONFIG_USB_PD_REV30) || !pe_in_frs_mode(port)) {
 			/* Contract is invalid now */
 			pe_invalidate_explicit_contract(port);
 		}
@@ -4221,22 +5248,22 @@ static void pe_prs_snk_src_source_on_entry(int port)
 	 * VBUS was enabled when the TypeC state machine entered
 	 * Attached.SRC state
 	 */
-	pe[port].ps_source_timer = get_time().val +
-					PD_POWER_SUPPLY_TURN_ON_DELAY;
+	pd_timer_enable(port, PE_TIMER_PS_SOURCE,
+			PD_POWER_SUPPLY_TURN_ON_DELAY);
 }
 
 static void pe_prs_snk_src_source_on_run(int port)
 {
 	/* Wait until power supply turns on */
-	if (pe[port].ps_source_timer != TIMER_DISABLED) {
-		if (get_time().val < pe[port].ps_source_timer)
+	if (!pd_timer_is_disabled(port, PE_TIMER_PS_SOURCE)) {
+		if (!pd_timer_is_expired(port, PE_TIMER_PS_SOURCE))
 			return;
 
 		/* update pe power role */
 		pe[port].power_role = pd_get_power_role(port);
-		send_ctrl_msg(port, TCPC_TX_SOP, PD_CTRL_PS_RDY);
+		send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_PS_RDY);
 		/* reset timer so PD_CTRL_PS_RDY isn't sent again */
-		pe[port].ps_source_timer = TIMER_DISABLED;
+		pd_timer_disable(port, PE_TIMER_PS_SOURCE);
 	}
 
 	/*
@@ -4259,8 +5286,8 @@ static void pe_prs_snk_src_source_on_run(int port)
 
 static void pe_prs_snk_src_source_on_exit(int port)
 {
-	tc_pr_swap_complete(port,
-			    PE_CHK_FLAG(port, PE_FLAGS_PR_SWAP_COMPLETE));
+	pd_timer_disable(port, PE_TIMER_PS_SOURCE);
+	tc_pr_swap_complete(port, PE_CHK_FLAG(port, PE_FLAGS_PR_SWAP_COMPLETE));
 }
 
 /**
@@ -4283,13 +5310,11 @@ static void pe_prs_snk_src_send_swap_entry(int port)
 	 *     Request the Protocol Layer to send a FR_Swap Message.
 	 */
 	if (IS_ENABLED(CONFIG_USB_PD_REV30)) {
-		send_ctrl_msg(port,
-			TCPC_TX_SOP,
-			PE_CHK_FLAG(port, PE_FLAGS_FAST_ROLE_SWAP_PATH)
-				? PD_CTRL_FR_SWAP
-				: PD_CTRL_PR_SWAP);
+		send_ctrl_msg(port, TCPCI_MSG_SOP,
+			      pe_in_frs_mode(port) ? PD_CTRL_FR_SWAP :
+						     PD_CTRL_PR_SWAP);
 	} else {
-		send_ctrl_msg(port, TCPC_TX_SOP, PD_CTRL_PR_SWAP);
+		send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_PR_SWAP);
 	}
 	pe_sender_response_msg_entry(port);
 }
@@ -4310,10 +5335,9 @@ static void pe_prs_snk_src_send_swap_run(int port)
 	 * Handle discarded message
 	 */
 	if (msg_check & PE_MSG_DISCARDED) {
-		if (PE_CHK_FLAG(port, PE_FLAGS_FAST_ROLE_SWAP_PATH))
-			set_state_pe(port, PE_SNK_HARD_RESET);
-		else
-			set_state_pe(port, PE_SNK_READY);
+		set_state_pe(port, pe_in_frs_mode(port) ?
+					   PE_WAIT_FOR_ERROR_RECOVERY :
+					   PE_SNK_READY);
 		return;
 	}
 
@@ -4340,13 +5364,13 @@ static void pe_prs_snk_src_send_swap_run(int port)
 				set_state_pe(port,
 					     PE_PRS_SNK_SRC_TRANSITION_TO_OFF);
 			} else if ((type == PD_CTRL_REJECT) ||
-						(type == PD_CTRL_WAIT)) {
+				   (type == PD_CTRL_WAIT)) {
 				if (IS_ENABLED(CONFIG_USB_PD_REV30))
-					set_state_pe(port,
-						PE_CHK_FLAG(port,
-						PE_FLAGS_FAST_ROLE_SWAP_PATH)
-					   ? PE_WAIT_FOR_ERROR_RECOVERY
-					   : PE_SNK_READY);
+					set_state_pe(
+						port,
+						pe_in_frs_mode(port) ?
+							PE_WAIT_FOR_ERROR_RECOVERY :
+							PE_SNK_READY);
 				else
 					set_state_pe(port, PE_SNK_READY);
 			}
@@ -4359,41 +5383,66 @@ static void pe_prs_snk_src_send_swap_run(int port)
 	 * FRS: Transition to ErrorRecovery state when:
 	 *   1) The SenderResponseTimer times out.
 	 */
-	if (get_time().val > pe[port].sender_response_timer) {
+	if (pd_timer_is_expired(port, PE_TIMER_SENDER_RESPONSE)) {
 		if (IS_ENABLED(CONFIG_USB_PD_REV30))
-			set_state_pe(port,
-				PE_CHK_FLAG(port, PE_FLAGS_FAST_ROLE_SWAP_PATH)
-				? PE_WAIT_FOR_ERROR_RECOVERY
-				: PE_SNK_READY);
+			set_state_pe(port, pe_in_frs_mode(port) ?
+						   PE_WAIT_FOR_ERROR_RECOVERY :
+						   PE_SNK_READY);
 		else
 			set_state_pe(port, PE_SNK_READY);
+		return;
+	}
+	/*
+	 * FRS Only: Transition to ErrorRecovery state when:
+	 *   2) The FR_Swap Message is not sent after retries (a GoodCRC Message
+	 *      has not been received). A soft reset Shall Not be initiated in
+	 *      this case.
+	 */
+	if (IS_ENABLED(CONFIG_USB_PD_REV30) && pe_in_frs_mode(port) &&
+	    PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) {
+		PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
+		set_state_pe(port, PE_WAIT_FOR_ERROR_RECOVERY);
 	}
 }
 
-#ifdef CONFIG_USB_PD_REV30
+static void pe_prs_snk_src_send_swap_exit(int port)
+{
+	pe_sender_response_msg_exit(port);
+}
+
 /**
  * PE_FRS_SNK_SRC_Start_AMS
  */
-static void pe_frs_snk_src_start_ams_entry(int port)
+__maybe_unused static void pe_frs_snk_src_start_ams_entry(int port)
 {
-	print_current_state(port);
+	if (!IS_ENABLED(CONFIG_USB_PD_REV30))
+		assert(0);
 
-	/* Contract is invalid now */
-	pe_invalidate_explicit_contract(port);
+	print_current_state(port);
 
 	/* Inform Protocol Layer this is start of AMS */
 	PE_SET_FLAG(port, PE_FLAGS_LOCALLY_INITIATED_AMS);
 
 	/* Shared PRS/FRS code, indicate FRS path */
 	PE_SET_FLAG(port, PE_FLAGS_FAST_ROLE_SWAP_PATH);
+
+	/*
+	 * Invalidate the contract after the FRS flags set so the
+	 * flags can be propagated to this function.
+	 */
+	pe_invalidate_explicit_contract(port);
+
 	set_state_pe(port, PE_PRS_SNK_SRC_SEND_SWAP);
 }
 
 /**
  * PE_PRS_FRS_SHARED
  */
-static void pe_prs_frs_shared_entry(int port)
+__maybe_unused static void pe_prs_frs_shared_entry(int port)
 {
+	if (!IS_ENABLED(CONFIG_USB_PD_REV30))
+		assert(0);
+
 	/*
 	 * Shared PRS/FRS code, assume PRS path
 	 *
@@ -4405,52 +5454,99 @@ static void pe_prs_frs_shared_entry(int port)
 	PE_CLR_FLAG(port, PE_FLAGS_FAST_ROLE_SWAP_PATH);
 }
 
-static void pe_prs_frs_shared_exit(int port)
+__maybe_unused static void pe_prs_frs_shared_exit(int port)
 {
+	if (!IS_ENABLED(CONFIG_USB_PD_REV30))
+		assert(0);
+
 	/*
 	 * Shared PRS/FRS code, when not in shared path
 	 * indicate PRS path
 	 */
 	PE_CLR_FLAG(port, PE_FLAGS_FAST_ROLE_SWAP_PATH);
 }
-#endif /* CONFIG_USB_PD_REV30 */
 
 /**
- * BIST TX
+ * PE_BIST_TX
  */
 static void pe_bist_tx_entry(int port)
 {
 	uint32_t *payload = (uint32_t *)rx_emsg[port].buf;
 	uint8_t mode = BIST_MODE(payload[0]);
+	int vbus_mv;
+	int ibus_ma;
 
 	print_current_state(port);
 
-	/*
-	 * See section 6.4.3.6 BIST Carrier Mode 2:
-	 * With a BIST Carrier Mode 2 BIST Data Object, the UUT Shall send out
-	 * a continuous string of alternating "1"s and “0”s.
-	 * The UUT Shall exit the Continuous BIST Mode within tBISTContMode of
-	 * this Continuous BIST Mode being enabled.
-	 */
+	/* Get the current nominal VBUS value */
+	if (pe[port].power_role == PD_ROLE_SOURCE) {
+		const uint32_t *src_pdo;
+		uint32_t unused;
+
+		dpm_get_source_pdo(&src_pdo, port);
+		pd_extract_pdo_power(src_pdo[pe[port].requested_idx - 1],
+				     &ibus_ma, &vbus_mv, &unused);
+	} else {
+		vbus_mv = pe[port].supply_voltage;
+	}
+
+	/* If VBUS is not at vSafe5V, then don't enter BIST test mode */
+	if (vbus_mv != PD_V_SAFE5V_NOM) {
+		pe_set_ready_state(port);
+		return;
+	}
+
 	if (mode == BIST_CARRIER_MODE_2) {
-		send_ctrl_msg(port, TCPC_TX_BIST_MODE_2, 0);
-		pe[port].bist_cont_mode_timer =
-					get_time().val + PD_T_BIST_CONT_MODE;
+		/*
+		 * PE_BIST_Carrier_Mode embedded here.
+		 * See PD 3.0 section 6.4.3.1 BIST Carrier Mode 2: With a BIST
+		 * Carrier Mode 2 BIST Data Object, the UUT Shall send out a
+		 * continuous string of BMC-encoded alternating "1"s and “0”s.
+		 * The UUT Shall exit the Continuous BIST Mode within
+		 * tBISTContMode of this Continuous BIST Mode being enabled.
+		 */
+		send_ctrl_msg(port, TCPCI_MSG_TX_BIST_MODE_2, 0);
+		pd_timer_enable(port, PE_TIMER_BIST_CONT_MODE,
+				PD_T_BIST_CONT_MODE);
+	} else if (mode == BIST_TEST_DATA) {
+		/*
+		 * See PD 3.0 section 6.4.3.2 BIST Test Data:
+		 * With a BIST Test Data BIST Data Object, the UUT Shall return
+		 * a GoodCRC Message and Shall enter a test mode in which it
+		 * sends no further Messages except for GoodCRC Messages in
+		 * response to received Messages.... The test Shall be ended by
+		 * sending Hard Reset Signaling to reset the UUT.
+		 */
+		if (tcpc_set_bist_test_mode(port, true) != EC_SUCCESS)
+			CPRINTS("C%d: Failed to enter BIST Test Mode", port);
+	} else if (IS_ENABLED(CONFIG_USB_PD_REV30) &&
+		   mode == BIST_SHARED_MODE_ENTER) {
+		/* Notify the DPM and return to ready */
+		dpm_bist_shared_mode_enter(port);
+		pe_set_ready_state(port);
+		return;
+	} else if (IS_ENABLED(CONFIG_USB_PD_REV30) &&
+		   mode == BIST_SHARED_MODE_EXIT) {
+		/* Notify the DPM and return to ready */
+		dpm_bist_shared_mode_exit(port);
+		pe_set_ready_state(port);
+		return;
+	} else {
+		/* Ignore unsupported BIST messages. */
+		pe_set_ready_state(port);
+		return;
 	}
-	/*
-	 * See section 6.4.3.9 BIST Test Data:
-	 * With a BIST Test Data BIST Data Object, the UUT Shall return a
-	 * GoodCRC Message and Shall enter a test mode in which it sends no
-	 * further Messages except for GoodCRC Messages in response to received
-	 * Messages.
-	 */
-	else if (mode == BIST_TEST_DATA)
-		pe[port].bist_cont_mode_timer = TIMER_DISABLED;
 }
 
 static void pe_bist_tx_run(int port)
 {
-	if (get_time().val > pe[port].bist_cont_mode_timer) {
+	if (pd_timer_is_expired(port, PE_TIMER_BIST_CONT_MODE)) {
+		/*
+		 * Entry point to disable BIST in TCPC if that's not already
+		 * handled automatically by the TCPC. Unless this method is
+		 * implemented in a TCPM driver, this function does nothing.
+		 */
+		tcpm_reset_bist_type_2(port);
 
 		if (pe[port].power_role == PD_ROLE_SOURCE)
 			set_state_pe(port, PE_SRC_TRANSITION_TO_DEFAULT);
@@ -4467,34 +5563,9 @@ static void pe_bist_tx_run(int port)
 	}
 }
 
-/**
- * BIST RX
- */
-static void pe_bist_rx_entry(int port)
-{
-	/* currently only support bist carrier 2 */
-	uint32_t bdo = BDO(BDO_MODE_CARRIER2, 0);
-
-	print_current_state(port);
-
-	tx_emsg[port].len = sizeof(bdo);
-	memcpy(tx_emsg[port].buf, (uint8_t *)&bdo, tx_emsg[port].len);
-	send_data_msg(port, TCPC_TX_SOP, PD_DATA_BIST);
-
-	/* Delay at least enough for partner to finish BIST */
-	pe[port].bist_cont_mode_timer =
-				get_time().val + PD_T_BIST_RECEIVE;
-}
-
-static void pe_bist_rx_run(int port)
+static void pe_bist_tx_exit(int port)
 {
-	if (get_time().val < pe[port].bist_cont_mode_timer)
-		return;
-
-	if (pe[port].power_role == PD_ROLE_SOURCE)
-		set_state_pe(port, PE_SRC_TRANSITION_TO_DEFAULT);
-	else
-		set_state_pe(port, PE_SNK_TRANSITION_TO_DEFAULT);
+	pd_timer_disable(port, PE_TIMER_BIST_CONT_MODE);
 }
 
 /**
@@ -4507,7 +5578,7 @@ static void pe_snk_give_sink_cap_entry(int port)
 	/* Send a Sink_Capabilities Message */
 	tx_emsg[port].len = pd_snk_pdo_cnt * 4;
 	memcpy(tx_emsg[port].buf, (uint8_t *)pd_snk_pdo, tx_emsg[port].len);
-	send_data_msg(port, TCPC_TX_SOP, PD_DATA_SINK_CAP);
+	send_data_msg(port, TCPCI_MSG_SOP, PD_DATA_SINK_CAP);
 }
 
 static void pe_snk_give_sink_cap_run(int port)
@@ -4515,7 +5586,11 @@ static void pe_snk_give_sink_cap_run(int port)
 	if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
 		PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
 		pe_set_ready_state(port);
+		return;
 	}
+
+	if (pe_check_outgoing_discard(port))
+		return;
 }
 
 /**
@@ -4532,51 +5607,7 @@ static void pe_wait_for_error_recovery_run(int port)
 	/* Stay here until error recovery is complete */
 }
 
-/**
- * PE_Handle_Custom_Vdm_Request
- */
-static void pe_handle_custom_vdm_request_entry(int port)
-{
-	/* Get the message */
-	uint32_t *payload = (uint32_t *)rx_emsg[port].buf;
-	int cnt = PD_HEADER_CNT(rx_emsg[port].header);
-	int sop = PD_HEADER_GET_SOP(rx_emsg[port].header);
-	int rlen = 0;
-	uint32_t *rdata;
-
-	print_current_state(port);
-
-	/* This is an Interruptible AMS */
-	PE_SET_FLAG(port, PE_FLAGS_INTERRUPTIBLE_AMS);
-
-	rlen = pd_custom_vdm(port, cnt, payload, &rdata);
-	if (rlen > 0) {
-		tx_emsg[port].len = rlen * 4;
-		memcpy(tx_emsg[port].buf, (uint8_t *)rdata, tx_emsg[port].len);
-		send_data_msg(port, sop, PD_DATA_VENDOR_DEF);
-	}
-}
-
-static void pe_handle_custom_vdm_request_run(int port)
-{
-	/* Wait for ACCEPT, WAIT or Reject message to send. */
-	if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
-		PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
-
-		/*
-		 * Message sent. Transition back to
-		 * PE_SRC_Ready or PE_SINK_Ready
-		 */
-		pe_set_ready_state(port);
-	}
-}
-
-static void pe_handle_custom_vdm_request_exit(int port)
-{
-	PE_CLR_FLAG(port, PE_FLAGS_INTERRUPTIBLE_AMS);
-}
-
-static enum vdm_response_result parse_vdm_response_common(int port)
+static enum vdm_response_result parse_vdm_response_common(int port)
 {
 	/* Retrieve the message information */
 	uint32_t *payload;
@@ -4595,10 +5626,10 @@ static enum vdm_response_result parse_vdm_response_common(int port)
 	cnt = PD_HEADER_CNT(rx_emsg[port].header);
 	ext = PD_HEADER_EXT(rx_emsg[port].header);
 
-	if (sop == pe[port].tx_type && type == PD_DATA_VENDOR_DEF && cnt >= 1
-			&& ext == 0) {
+	if (sop == pe[port].tx_type && type == PD_DATA_VENDOR_DEF && cnt >= 1 &&
+	    ext == 0) {
 		if (PD_VDO_CMDT(payload[0]) == CMDT_RSP_ACK &&
-				cnt >= pe[port].vdm_ack_min_data_objects) {
+		    cnt >= pe[port].vdm_ack_min_data_objects) {
 			/* Handle ACKs in state-specific code. */
 			return VDM_RESULT_ACK;
 		} else if (PD_VDO_CMDT(payload[0]) == CMDT_RSP_NAK) {
@@ -4610,9 +5641,9 @@ static enum vdm_response_result parse_vdm_response_common(int port)
 			 * tVDMBusy
 			 */
 			CPRINTS("C%d: Partner BUSY, request will be retried",
-					port);
-			pe[port].discover_identity_timer =
-					get_time().val + PD_T_VDM_BUSY;
+				port);
+			pd_timer_enable(port, PE_TIMER_DISCOVER_IDENTITY,
+					PD_T_VDM_BUSY);
 
 			return VDM_RESULT_NO_ACTION;
 		} else if (PD_VDO_CMDT(payload[0]) == CMDT_INIT) {
@@ -4628,11 +5659,11 @@ static enum vdm_response_result parse_vdm_response_common(int port)
 		 * Partner gave us an incorrect size or command; mark discovery
 		 * as failed.
 		 */
-		CPRINTS("C%d: Unexpected VDM response: 0x%04x 0x%04x",
-				port, rx_emsg[port].header, payload[0]);
+		CPRINTS("C%d: Unexpected VDM response: 0x%04x 0x%04x", port,
+			rx_emsg[port].header, payload[0]);
 		return VDM_RESULT_NAK;
 	} else if (sop == pe[port].tx_type && ext == 0 && cnt == 0 &&
-			type == PD_CTRL_NOT_SUPPORTED) {
+		   type == PD_CTRL_NOT_SUPPORTED) {
 		/*
 		 * A NAK would be more expected here, but Not Supported is still
 		 * allowed with the same meaning.
@@ -4652,7 +5683,7 @@ static enum vdm_response_result parse_vdm_response_common(int port)
  */
 static void pe_vdm_send_request_entry(int port)
 {
-	if (pe[port].tx_type == TCPC_TX_INVALID) {
+	if (pe[port].tx_type == TCPCI_MSG_INVALID) {
 		if (IS_ENABLED(USB_PD_DEBUG_LABELS))
 			CPRINTS("C%d: %s: Tx type expected to be set, "
 				"returning",
@@ -4661,31 +5692,30 @@ static void pe_vdm_send_request_entry(int port)
 		return;
 	}
 
-	if ((pe[port].tx_type == TCPC_TX_SOP_PRIME ||
-	     pe[port].tx_type == TCPC_TX_SOP_PRIME_PRIME) &&
-	     !tc_is_vconn_src(port)) {
+	if ((pe[port].tx_type == TCPCI_MSG_SOP_PRIME ||
+	     pe[port].tx_type == TCPCI_MSG_SOP_PRIME_PRIME) &&
+	    !tc_is_vconn_src(port) &&
+	    port_discovery_vconn_swap_policy(
+		    port, BIT(PE_FLAGS_VCONN_SWAP_TO_ON_FN))) {
 		if (port_try_vconn_swap(port))
 			return;
 	}
 
 	/* All VDM sequences are Interruptible */
-	PE_SET_FLAG(port, PE_FLAGS_LOCALLY_INITIATED_AMS |
-			PE_FLAGS_INTERRUPTIBLE_AMS);
-
-	pe[port].vdm_response_timer = TIMER_DISABLED;
+	PE_SET_MASK(port, BIT(PE_FLAGS_LOCALLY_INITIATED_AMS_FN) |
+				  BIT(PE_FLAGS_INTERRUPTIBLE_AMS_FN));
 }
 
 static void pe_vdm_send_request_run(int port)
 {
-	if (pe[port].vdm_response_timer == TIMER_DISABLED &&
-			PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
+	if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE) &&
+	    pd_timer_is_disabled(port, PE_TIMER_VDM_RESPONSE)) {
 		/* Message was sent */
 		PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
 
 		/* Start no response timer */
 		/* TODO(b/155890173): Support DPM-supplied timeout */
-		pe[port].vdm_response_timer =
-			get_time().val + PD_T_VDM_SNDR_RSP;
+		pd_timer_enable(port, PE_TIMER_VDM_RESPONSE, PD_T_VDM_SNDR_RSP);
 	}
 
 	if (PE_CHK_FLAG(port, PE_FLAGS_MSG_DISCARDED)) {
@@ -4701,10 +5731,9 @@ static void pe_vdm_send_request_run(int port)
 	 * Check the VDM timer, child will be responsible for processing
 	 * messages and reacting appropriately to unexpected messages.
 	 */
-	if (get_time().val > pe[port].vdm_response_timer) {
+	if (pd_timer_is_expired(port, PE_TIMER_VDM_RESPONSE)) {
 		CPRINTF("VDM %s Response Timeout\n",
-				pe[port].tx_type == TCPC_TX_SOP ?
-				"Port" : "Cable");
+			pe[port].tx_type == TCPCI_MSG_SOP ? "Port" : "Cable");
 		/*
 		 * Flag timeout so child state can mark appropriate discovery
 		 * item as failed.
@@ -4724,7 +5753,9 @@ static void pe_vdm_send_request_exit(int port)
 	PE_CLR_FLAG(port, PE_FLAGS_INTERRUPTIBLE_AMS);
 
 	/* Invalidate TX type so it must be set before next call */
-	pe[port].tx_type = TCPC_TX_INVALID;
+	pe[port].tx_type = TCPCI_MSG_INVALID;
+
+	pd_timer_disable(port, PE_TIMER_VDM_RESPONSE);
 }
 
 /**
@@ -4739,15 +5770,19 @@ static void pe_vdm_identity_request_cbl_entry(int port)
 
 	print_current_state(port);
 
-	if (!tc_is_vconn_src(port)) {
+	if (!pe_can_send_sop_prime(port)) {
+		/*
+		 * The parent state already tried to enable SOP' traffic. If it
+		 * is still disabled, there's nothing left to try.
+		 */
 		pd_set_identity_discovery(port, pe[port].tx_type, PD_DISC_FAIL);
 		set_state_pe(port, get_last_state_pe(port));
 		return;
 	}
 
 	msg[0] = VDO(USB_SID_PD, 1,
-			VDO_SVDM_VERS(pd_get_vdo_ver(port, pe[port].tx_type)) |
-			CMD_DISCOVER_IDENT);
+		     VDO_SVDM_VERS(pd_get_vdo_ver(port, pe[port].tx_type)) |
+			     CMD_DISCOVER_IDENT);
 	tx_emsg[port].len = sizeof(uint32_t);
 
 	send_data_msg(port, pe[port].tx_type, PD_DATA_VENDOR_DEF);
@@ -4764,7 +5799,7 @@ static void pe_vdm_identity_request_cbl_entry(int port)
 static void pe_vdm_identity_request_cbl_run(int port)
 {
 	/* Retrieve the message information */
-	uint32_t *payload = (uint32_t *) rx_emsg[port].buf;
+	uint32_t *payload = (uint32_t *)rx_emsg[port].buf;
 	int sop = PD_HEADER_GET_SOP(rx_emsg[port].header);
 	uint8_t type = PD_HEADER_TYPE(rx_emsg[port].header);
 	uint8_t cnt = PD_HEADER_CNT(rx_emsg[port].header);
@@ -4797,9 +5832,8 @@ static void pe_vdm_identity_request_cbl_run(int port)
 		 * state.
 		 */
 		if (get_last_state_pe(port) == PE_SRC_DISCOVERY &&
-					(sop != pe[port].tx_type ||
-					 type != PD_DATA_VENDOR_DEF ||
-					 cnt == 0 || ext != 0)) {
+		    (sop != pe[port].tx_type || type != PD_DATA_VENDOR_DEF ||
+		     cnt == 0 || ext != 0)) {
 			/*
 			 * Unexpected non-VDM received: Before an explicit
 			 * contract, an unexpected message shall generate a soft
@@ -4820,9 +5854,9 @@ static void pe_vdm_identity_request_cbl_run(int port)
 		 * PD Spec Table 6-2: Revision Interoperability during an
 		 * Explicit Contract
 		 */
-		if (prl_get_rev(port, TCPC_TX_SOP) != PD_REV20)
-			prl_set_rev(port, sop,
-					PD_HEADER_REV(rx_emsg[port].header));
+		if (prl_get_rev(port, TCPCI_MSG_SOP) != PD_REV20)
+			set_cable_rev(port,
+				      PD_HEADER_REV(rx_emsg[port].header));
 		break;
 	case VDM_RESULT_NAK:
 		/* PE_INIT_PORT_VDM_IDENTITY_NAKed embedded here */
@@ -4850,7 +5884,7 @@ static void pe_vdm_identity_request_cbl_exit(int port)
 	 */
 	if (PE_CHK_FLAG(port, PE_FLAGS_VDM_REQUEST_TIMEOUT)) {
 		PE_CLR_FLAG(port, PE_FLAGS_VDM_REQUEST_TIMEOUT);
-		prl_set_rev(port, TCPC_TX_SOP_PRIME, PD_REV20);
+		set_cable_rev(port, PD_REV20);
 	}
 
 	/*
@@ -4863,24 +5897,22 @@ static void pe_vdm_identity_request_cbl_exit(int port)
 	 * Not send any further SOP’/SOP’’ Messages.
 	 */
 	if (pe[port].discover_identity_counter >= N_DISCOVER_IDENTITY_COUNT)
-		pd_set_identity_discovery(port, pe[port].tx_type,
-				PD_DISC_FAIL);
+		pd_set_identity_discovery(port, pe[port].tx_type, PD_DISC_FAIL);
 	else if (pe[port].discover_identity_counter ==
-					(N_DISCOVER_IDENTITY_COUNT / 2))
+		 N_DISCOVER_IDENTITY_PD3_0_LIMIT)
 		/*
-		 * Downgrade to PD 2.0 if the partner hasn't replied halfway
-		 * through discovery as well, in case the cable is
+		 * Downgrade to PD 2.0 if the partner hasn't replied before
+		 * all retries are exhausted in case the cable is
 		 * non-compliant about GoodCRC-ing higher revisions
 		 */
-		prl_set_rev(port, TCPC_TX_SOP_PRIME, PD_REV20);
+		set_cable_rev(port, PD_REV20);
 
 	/*
 	 * Set discover identity timer unless BUSY case already did so.
 	 */
-	if (pd_get_identity_discovery(port, pe[port].tx_type) == PD_DISC_NEEDED
-	    && pe[port].discover_identity_timer < get_time().val) {
-		uint64_t timer;
-
+	if (pd_get_identity_discovery(port, pe[port].tx_type) ==
+		    PD_DISC_NEEDED &&
+	    pd_timer_is_expired(port, PE_TIMER_DISCOVER_IDENTITY)) {
 		/*
 		 * The tDiscoverIdentity timer is used during an explicit
 		 * contract when discovering whether a cable is PD capable.
@@ -4889,17 +5921,20 @@ static void pe_vdm_identity_request_cbl_exit(int port)
 		 * sent. This permits operation with captive cable devices that
 		 * power the SOP' responder from VBUS instead of VCONN.
 		 */
-		if (pe_is_explicit_contract(port))
-			timer = PD_T_DISCOVER_IDENTITY;
-		else
-			timer = PE_T_DISCOVER_IDENTITY_NO_CONTRACT;
-
-		pe[port].discover_identity_timer = get_time().val + timer;
+		pd_timer_enable(port, PE_TIMER_DISCOVER_IDENTITY,
+				pe_is_explicit_contract(port) ?
+					PD_T_DISCOVER_IDENTITY :
+					PE_T_DISCOVER_IDENTITY_NO_CONTRACT);
 	}
 
 	/* Do not attempt further discovery if identity discovery failed. */
-	if (pd_get_identity_discovery(port, pe[port].tx_type) == PD_DISC_FAIL)
+	if (pd_get_identity_discovery(port, pe[port].tx_type) == PD_DISC_FAIL) {
 		pd_set_svids_discovery(port, pe[port].tx_type, PD_DISC_FAIL);
+		pd_notify_event(port,
+				pe[port].tx_type == TCPCI_MSG_SOP ?
+					PD_STATUS_EVENT_SOP_DISC_DONE :
+					PD_STATUS_EVENT_SOP_PRIME_DISC_DONE);
+	}
 }
 
 /**
@@ -4917,8 +5952,8 @@ static void pe_init_port_vdm_identity_request_entry(int port)
 	print_current_state(port);
 
 	msg[0] = VDO(USB_SID_PD, 1,
-			VDO_SVDM_VERS(pd_get_vdo_ver(port, pe[port].tx_type)) |
-			CMD_DISCOVER_IDENT);
+		     VDO_SVDM_VERS(pd_get_vdo_ver(port, pe[port].tx_type)) |
+			     CMD_DISCOVER_IDENT);
 	tx_emsg[port].len = sizeof(uint32_t);
 
 	send_data_msg(port, pe[port].tx_type, PD_DATA_VENDOR_DEF);
@@ -4945,21 +5980,18 @@ static void pe_init_port_vdm_identity_request_run(int port)
 		break;
 	case VDM_RESULT_ACK: {
 		/* Retrieve the message information. */
-		uint32_t *payload = (uint32_t *) rx_emsg[port].buf;
+		uint32_t *payload = (uint32_t *)rx_emsg[port].buf;
 		int sop = PD_HEADER_GET_SOP(rx_emsg[port].header);
 		uint8_t cnt = PD_HEADER_CNT(rx_emsg[port].header);
 
 		/* PE_INIT_PORT_VDM_Identity_ACKed embedded here */
 		dfp_consume_identity(port, sop, cnt, payload);
+
 		break;
-		}
+	}
 	case VDM_RESULT_NAK:
 		/* PE_INIT_PORT_VDM_IDENTITY_NAKed embedded here */
 		pd_set_identity_discovery(port, pe[port].tx_type, PD_DISC_FAIL);
-		/*
-		 * Note: AP is only notified of discovery complete when
-		 * something was found (at least one ACK)
-		 */
 		break;
 	}
 
@@ -4984,8 +6016,13 @@ static void pe_init_port_vdm_identity_request_exit(int port)
 	}
 
 	/* Do not attempt further discovery if identity discovery failed. */
-	if (pd_get_identity_discovery(port, pe[port].tx_type) == PD_DISC_FAIL)
+	if (pd_get_identity_discovery(port, pe[port].tx_type) == PD_DISC_FAIL) {
 		pd_set_svids_discovery(port, pe[port].tx_type, PD_DISC_FAIL);
+		pd_notify_event(port,
+				pe[port].tx_type == TCPCI_MSG_SOP ?
+					PD_STATUS_EVENT_SOP_DISC_DONE :
+					PD_STATUS_EVENT_SOP_PRIME_DISC_DONE);
+	}
 }
 
 /**
@@ -4999,16 +6036,20 @@ static void pe_init_vdm_svids_request_entry(int port)
 
 	print_current_state(port);
 
-	if (pe[port].tx_type == TCPC_TX_SOP_PRIME &&
-	    !tc_is_vconn_src(port)) {
+	if (pe[port].tx_type == TCPCI_MSG_SOP_PRIME &&
+	    !pe_can_send_sop_prime(port)) {
+		/*
+		 * The parent state already tried to enable SOP' traffic. If it
+		 * is still disabled, there's nothing left to try.
+		 */
 		pd_set_svids_discovery(port, pe[port].tx_type, PD_DISC_FAIL);
 		set_state_pe(port, get_last_state_pe(port));
 		return;
 	}
 
 	msg[0] = VDO(USB_SID_PD, 1,
-			VDO_SVDM_VERS(pd_get_vdo_ver(port, pe[port].tx_type)) |
-			CMD_DISCOVER_SVID);
+		     VDO_SVDM_VERS(pd_get_vdo_ver(port, pe[port].tx_type)) |
+			     CMD_DISCOVER_SVID);
 	tx_emsg[port].len = sizeof(uint32_t);
 
 	send_data_msg(port, pe[port].tx_type, PD_DATA_VENDOR_DEF);
@@ -5035,14 +6076,14 @@ static void pe_init_vdm_svids_request_run(int port)
 		break;
 	case VDM_RESULT_ACK: {
 		/* Retrieve the message information. */
-		uint32_t *payload = (uint32_t *) rx_emsg[port].buf;
+		uint32_t *payload = (uint32_t *)rx_emsg[port].buf;
 		int sop = PD_HEADER_GET_SOP(rx_emsg[port].header);
 		uint8_t cnt = PD_HEADER_CNT(rx_emsg[port].header);
 
 		/* PE_INIT_VDM_SVIDs_ACKed embedded here */
 		dfp_consume_svids(port, sop, cnt, payload);
 		break;
-		}
+	}
 	case VDM_RESULT_NAK:
 		/* PE_INIT_VDM_SVIDs_NAKed embedded here */
 		pd_set_svids_discovery(port, pe[port].tx_type, PD_DISC_FAIL);
@@ -5071,9 +6112,10 @@ static void pe_init_vdm_svids_request_exit(int port)
 
 	/* If SVID discovery failed, discovery is done at this point */
 	if (pd_get_svids_discovery(port, pe[port].tx_type) == PD_DISC_FAIL)
-		pe_notify_event(port, pe[port].tx_type == TCPC_TX_SOP ?
-				PD_STATUS_EVENT_SOP_DISC_DONE :
-				PD_STATUS_EVENT_SOP_PRIME_DISC_DONE);
+		pd_notify_event(port,
+				pe[port].tx_type == TCPCI_MSG_SOP ?
+					PD_STATUS_EVENT_SOP_DISC_DONE :
+					PD_STATUS_EVENT_SOP_PRIME_DISC_DONE);
 }
 
 /**
@@ -5097,17 +6139,21 @@ static void pe_init_vdm_modes_request_entry(int port)
 
 	print_current_state(port);
 
-	if (pe[port].tx_type == TCPC_TX_SOP_PRIME &&
-	    !tc_is_vconn_src(port)) {
+	if (pe[port].tx_type == TCPCI_MSG_SOP_PRIME &&
+	    !pe_can_send_sop_prime(port)) {
+		/*
+		 * The parent state already tried to enable SOP' traffic. If it
+		 * is still disabled, there's nothing left to try.
+		 */
 		pd_set_modes_discovery(port, pe[port].tx_type, svid,
-				PD_DISC_FAIL);
+				       PD_DISC_FAIL);
 		set_state_pe(port, get_last_state_pe(port));
 		return;
 	}
 
-	msg[0] = VDO((uint16_t) svid, 1,
-			VDO_SVDM_VERS(pd_get_vdo_ver(port, pe[port].tx_type)) |
-			CMD_DISCOVER_MODES);
+	msg[0] = VDO((uint16_t)svid, 1,
+		     VDO_SVDM_VERS(pd_get_vdo_ver(port, pe[port].tx_type)) |
+			     CMD_DISCOVER_MODES);
 	tx_emsg[port].len = sizeof(uint32_t);
 
 	send_data_msg(port, pe[port].tx_type, PD_DATA_VENDOR_DEF);
@@ -5121,7 +6167,7 @@ static void pe_init_vdm_modes_request_entry(int port)
 
 static void pe_init_vdm_modes_request_run(int port)
 {
-	struct svid_mode_data *mode_data;
+	const struct svid_mode_data *mode_data;
 	uint16_t requested_svid;
 
 	mode_data = pd_get_next_mode(port, pe[port].tx_type);
@@ -5143,29 +6189,22 @@ static void pe_init_vdm_modes_request_run(int port)
 		break;
 	case VDM_RESULT_ACK: {
 		/* Retrieve the message information. */
-		uint32_t *payload = (uint32_t *) rx_emsg[port].buf;
+		uint32_t *payload = (uint32_t *)rx_emsg[port].buf;
 		int sop = PD_HEADER_GET_SOP(rx_emsg[port].header);
 		uint8_t cnt = PD_HEADER_CNT(rx_emsg[port].header);
-		uint16_t response_svid = (uint16_t) PD_VDO_VID(payload[0]);
 
 		/*
 		 * Accept ACK if the request and response SVIDs are equal;
 		 * otherwise, treat this as a NAK of the request SVID.
-		 *
-		 * TODO(b:169242812): support valid mode checking in
-		 * dfp_consume_modes.
 		 */
-		if (requested_svid == response_svid) {
-			/* PE_INIT_VDM_Modes_ACKed embedded here */
-			dfp_consume_modes(port, sop, cnt, payload);
-			break;
-		}
-		}
-		/* Fall Through */
+		/* PE_INIT_VDM_Modes_ACKed embedded here */
+		dfp_consume_modes(port, sop, cnt, payload);
+		break;
+	}
 	case VDM_RESULT_NAK:
 		/* PE_INIT_VDM_Modes_NAKed embedded here */
 		pd_set_modes_discovery(port, pe[port].tx_type, requested_svid,
-				PD_DISC_FAIL);
+				       PD_DISC_FAIL);
 		break;
 	}
 
@@ -5177,10 +6216,10 @@ static void pe_init_vdm_modes_request_exit(int port)
 {
 	if (pd_get_modes_discovery(port, pe[port].tx_type) != PD_DISC_NEEDED)
 		/* Mode discovery done, notify the AP */
-		pe_notify_event(port, pe[port].tx_type == TCPC_TX_SOP ?
-				PD_STATUS_EVENT_SOP_DISC_DONE :
-				PD_STATUS_EVENT_SOP_PRIME_DISC_DONE);
-
+		pd_notify_event(port,
+				pe[port].tx_type == TCPCI_MSG_SOP ?
+					PD_STATUS_EVENT_SOP_DISC_DONE :
+					PD_STATUS_EVENT_SOP_PRIME_DISC_DONE);
 }
 
 /**
@@ -5193,12 +6232,16 @@ static void pe_vdm_request_dpm_entry(int port)
 {
 	print_current_state(port);
 
-	if ((pe[port].tx_type == TCPC_TX_SOP_PRIME ||
-	     pe[port].tx_type == TCPC_TX_SOP_PRIME_PRIME) &&
-	     !tc_is_vconn_src(port)) {
+	if ((pe[port].tx_type == TCPCI_MSG_SOP_PRIME ||
+	     pe[port].tx_type == TCPCI_MSG_SOP_PRIME_PRIME) &&
+	    !pe_can_send_sop_prime(port)) {
+		/*
+		 * The parent state already tried to enable SOP' traffic. If it
+		 * is still disabled, there's nothing left to try.
+		 */
 		dpm_vdm_naked(port, pe[port].tx_type,
 			      PD_VDO_VID(pe[port].vdm_data[0]),
-			      PD_VDO_CMD(pe[port].vdm_data[0]));
+			      PD_VDO_CMD(pe[port].vdm_data[0]), 0);
 		set_state_pe(port, get_last_state_pe(port));
 		return;
 	}
@@ -5206,20 +6249,12 @@ static void pe_vdm_request_dpm_entry(int port)
 	/* Copy Vendor Data Objects (VDOs) into message buffer */
 	if (pe[port].vdm_cnt > 0) {
 		/* Copy data after header */
-		memcpy(&tx_emsg[port].buf,
-			(uint8_t *)pe[port].vdm_data,
-			pe[port].vdm_cnt * 4);
+		memcpy(&tx_emsg[port].buf, (uint8_t *)pe[port].vdm_data,
+		       pe[port].vdm_cnt * 4);
 		/* Update len with the number of VDO bytes */
 		tx_emsg[port].len = pe[port].vdm_cnt * 4;
 	}
 
-	/*
-	 * Clear the VDM nak'ed flag so that each request is
-	 * treated separately (NAKs are handled by the
-	 * DPM layer). Otherwise previous NAKs received will
-	 * cause the state to exit early.
-	 */
-	PE_CLR_FLAG(port, PE_FLAGS_VDM_REQUEST_NAKED);
 	send_data_msg(port, pe[port].tx_type, PD_DATA_VENDOR_DEF);
 
 	/*
@@ -5231,54 +6266,80 @@ static void pe_vdm_request_dpm_entry(int port)
 
 static void pe_vdm_request_dpm_run(int port)
 {
+	uint32_t vdm_hdr;
+
 	switch (parse_vdm_response_common(port)) {
 	case VDM_RESULT_WAITING:
-		/* If common code didn't parse a message, continue waiting. */
+		/*
+		 * USB-PD 3.0 Rev 1.1 - 6.4.4.2.5
+		 * Structured VDM command consists of a command request and a
+		 * command response (ACK, NAK, or BUSY). An exception is made
+		 * for the Attention command which shall have no response.
+		 *
+		 * Since Attention commands do not have an expected reply,
+		 * the SVDM command is complete once the Attention command
+		 * transmit is complete.
+		 */
+		vdm_hdr = pe[port].vdm_data[0];
+		if (PD_VDO_SVDM(vdm_hdr) &&
+		    (PD_VDO_CMD(vdm_hdr) == CMD_ATTENTION)) {
+			if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
+				PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
+				break;
+			}
+		}
+		/*
+		 * If common code didn't parse a message, and the VDM
+		 * just sent was not an Attention message, then continue
+		 * waiting.
+		 */
 		return;
 	case VDM_RESULT_NO_ACTION:
 		/*
 		 * If the received message doesn't change the discovery state,
 		 * there is nothing to do but return to the previous ready
-		 * state.
+		 * state. This includes Attention commands which have no
+		 * expected SVDM response.
 		 */
 		break;
 	case VDM_RESULT_ACK: {
 		/* Retrieve the message information. */
-		uint32_t *payload = (uint32_t *) rx_emsg[port].buf;
+		uint32_t *payload = (uint32_t *)rx_emsg[port].buf;
 		int sop = PD_HEADER_GET_SOP(rx_emsg[port].header);
 		uint8_t cnt = PD_HEADER_CNT(rx_emsg[port].header);
-		uint16_t svid = PD_VDO_VID(payload[0]);
-		uint8_t vdm_cmd = PD_VDO_CMD(payload[0]);
 
 		/*
 		 * PE initiator VDM-ACKed state for requested VDM, like
 		 * PE_INIT_VDM_FOO_ACKed, embedded here.
 		 */
 		dpm_vdm_acked(port, sop, cnt, payload);
-
-		if (sop == TCPC_TX_SOP && svid == USB_SID_DISPLAYPORT &&
-				vdm_cmd == CMD_DP_CONFIG) {
-			PE_SET_FLAG(port, PE_FLAGS_VDM_SETUP_DONE);
-		}
 		break;
-		}
-	case VDM_RESULT_NAK:
+	}
+	case VDM_RESULT_NAK: {
+		uint32_t vdm_header = 0;
+
 		/*
 		 * PE initiator VDM-NAKed state for requested VDM, like
 		 * PE_INIT_VDM_FOO_NAKed, embedded here.
 		 */
-		PE_SET_FLAG(port, PE_FLAGS_VDM_SETUP_DONE);
 
 		/*
 		 * Because Not Supported messages or response timeouts are
 		 * treated as NAKs, there may not be a NAK message to parse.
-		 * Extract the needed information from the sent VDM.
+		 * Extract the needed information from the sent VDM, and send
+		 * the NAK if present.
 		 */
+		if (PD_HEADER_TYPE(rx_emsg[port].header) ==
+			    PD_DATA_VENDOR_DEF &&
+		    PD_HEADER_CNT(rx_emsg[port].header) > 0)
+			vdm_header = ((uint32_t *)rx_emsg[port].buf)[0];
+
 		dpm_vdm_naked(port, pe[port].tx_type,
-				PD_VDO_VID(pe[port].vdm_data[0]),
-				PD_VDO_CMD(pe[port].vdm_data[0]));
+			      PD_VDO_VID(pe[port].vdm_data[0]),
+			      PD_VDO_CMD(pe[port].vdm_data[0]), vdm_header);
 		break;
 	}
+	}
 
 	/* Return to calling state (PE_{SRC,SNK}_Ready) */
 	set_state_pe(port, get_last_state_pe(port));
@@ -5286,12 +6347,29 @@ static void pe_vdm_request_dpm_run(int port)
 
 static void pe_vdm_request_dpm_exit(int port)
 {
+	if (PE_CHK_FLAG(port, PE_FLAGS_VDM_REQUEST_TIMEOUT)) {
+		PE_CLR_FLAG(port, PE_FLAGS_VDM_REQUEST_TIMEOUT);
+
+		/*
+		 * Mark failure to respond as discovery failure.
+		 *
+		 * For PD 2.0 partners (6.10.3 Applicability of Structured VDM
+		 * Commands Note 3):
+		 *
+		 * If Structured VDMs are not supported, a Structured VDM
+		 * Command received by a DFP or UFP Shall be Ignored.
+		 */
+		dpm_vdm_naked(port, pe[port].tx_type,
+			      PD_VDO_VID(pe[port].vdm_data[0]),
+			      PD_VDO_CMD(pe[port].vdm_data[0]), 0);
+	}
+
 	/*
 	 * Force Tx type to be reset before reentering a VDM state, unless the
 	 * current VDM request will be resumed.
 	 */
 	if (!PE_CHK_FLAG(port, PE_FLAGS_VDM_REQUEST_CONTINUE))
-		pe[port].tx_type = TCPC_TX_INVALID;
+		pe[port].tx_type = TCPCI_MSG_INVALID;
 }
 
 /**
@@ -5299,13 +6377,10 @@ static void pe_vdm_request_dpm_exit(int port)
  */
 static void pe_vdm_response_entry(int port)
 {
-	int response_size_bytes = 0;
+	int vdo_len = 0;
 	uint32_t *rx_payload;
 	uint32_t *tx_payload;
-	uint16_t vdo_vdm_svid;
 	uint8_t vdo_cmd;
-	uint8_t vdo_opos = 0;
-	int cmd_type;
 	svdm_rsp_func func = NULL;
 
 	print_current_state(port);
@@ -5316,18 +6391,48 @@ static void pe_vdm_response_entry(int port)
 	/* Get the message */
 	rx_payload = (uint32_t *)rx_emsg[port].buf;
 
-	vdo_vdm_svid = PD_VDO_VID(rx_payload[0]);
+	/* Extract VDM command from the VDM header */
 	vdo_cmd = PD_VDO_CMD(rx_payload[0]);
-	cmd_type = PD_VDO_CMDT(rx_payload[0]);
-	rx_payload[0] &= ~VDO_CMDT_MASK;
-
-	if (cmd_type != CMDT_INIT) {
-		CPRINTF("ERR:CMDT:%d:%d\n", cmd_type, vdo_cmd);
+	/* This must be a command request to proceed further */
+	if (PD_VDO_CMDT(rx_payload[0]) != CMDT_INIT) {
+		CPRINTF("ERR:CMDT:%d:%d\n", PD_VDO_CMDT(rx_payload[0]),
+			vdo_cmd);
 
 		pe_set_ready_state(port);
 		return;
 	}
 
+	tx_payload = (uint32_t *)tx_emsg[port].buf;
+	/*
+	 * Designed in TCPMv1, svdm_response functions use same
+	 * buffer to take received data and overwrite with response
+	 * data. To work with this interface, here copy rx data to
+	 * tx buffer and pass tx_payload to func.
+	 * TODO(b/166455363): change the interface to pass both rx
+	 * and tx buffer.
+	 *
+	 * The SVDM header is dependent on both VDM command request being
+	 * replied to and the result of response function. The SVDM command
+	 * message is copied into tx_payload. tx_payload[0] is the VDM header
+	 * for the response message. The SVDM response function takes the role
+	 * of the DPM layer and will indicate the response type (ACK/NAK/BUSY)
+	 * by its return value (vdo_len)
+	 *    vdo_len > 0  --> ACK
+	 *    vdo_len == 0 --> NAK
+	 *    vdo_len < 0  --> BUSY
+	 */
+	memcpy(tx_payload, rx_payload, PD_HEADER_CNT(rx_emsg[port].header) * 4);
+	/*
+	 * Clear fields in SVDM response message that will be set based on the
+	 * result of the svdm response function.
+	 */
+	tx_payload[0] &= ~VDO_CMDT_MASK;
+	tx_payload[0] &= ~VDO_SVDM_VERS(0x3);
+
+	/* Add SVDM structured version being used */
+	tx_payload[0] |= VDO_SVDM_VERS(pd_get_vdo_ver(port, TCPCI_MSG_SOP));
+
+	/* Use VDM command to select the response handler function */
 	switch (vdo_cmd) {
 	case CMD_DISCOVER_IDENT:
 		func = svdm_rsp.identity;
@@ -5339,7 +6444,6 @@ static void pe_vdm_response_entry(int port)
 		func = svdm_rsp.modes;
 		break;
 	case CMD_ENTER_MODE:
-		vdo_opos = PD_VDO_OPOS(rx_payload[0]);
 		func = svdm_rsp.enter_mode;
 		break;
 	case CMD_DP_STATUS:
@@ -5351,7 +6455,6 @@ static void pe_vdm_response_entry(int port)
 			func = svdm_rsp.amode->config;
 		break;
 	case CMD_EXIT_MODE:
-		vdo_opos = PD_VDO_OPOS(rx_payload[0]);
 		func = svdm_rsp.exit_mode;
 		break;
 #ifdef CONFIG_USB_PD_ALT_MODE_DFP
@@ -5360,7 +6463,8 @@ static void pe_vdm_response_entry(int port)
 		 * attention is only SVDM with no response
 		 * (just goodCRC) return zero here.
 		 */
-		dfp_consume_attention(port, rx_payload);
+		dpm_notify_attention(port, PD_HEADER_CNT(rx_emsg[port].header),
+				     rx_payload);
 		pe_set_ready_state(port);
 		return;
 #endif
@@ -5368,77 +6472,75 @@ static void pe_vdm_response_entry(int port)
 		CPRINTF("VDO ERR:CMD:%d\n", vdo_cmd);
 	}
 
-	tx_payload = (uint32_t *)tx_emsg[port].buf;
-
-	if (func) {
+	/*
+	 * If the port partner is PD_REV20 and our data role is DFP, we must
+	 * reply to any SVDM command with a NAK. If the SVDM was an Attention
+	 * command, it does not have a response, and exits the function above.
+	 */
+	if (func && (prl_get_rev(port, TCPCI_MSG_SOP) != PD_REV20 ||
+		     pe[port].data_role == PD_ROLE_UFP)) {
 		/*
-		 * Designed in TCPMv1, svdm_response functions use same
-		 * buffer to take received data and overwrite with response
-		 * data. To work with this interface, here copy rx data to
-		 * tx buffer and pass tx_payload to func.
-		 * TODO(b/166455363): change the interface to pass both rx
-		 * and tx buffer
+		 * Execute SVDM response function selected above and set the
+		 * correct response type in the VDM header.
 		 */
-		memcpy(tx_payload, rx_payload, rx_emsg[port].len);
+		vdo_len = func(port, tx_payload);
+		if (vdo_len > 0) {
+			tx_payload[0] |= VDO_CMDT(CMDT_RSP_ACK);
+			/*
+			 * If command response is an ACK and if the command was
+			 * either enter/exit mode, then update the PE modal flag
+			 * accordingly and cancel any DFP swap attempts.
+			 */
+			if (vdo_cmd == CMD_ENTER_MODE) {
+				PE_CLR_FLAG(port, PE_FLAGS_DR_SWAP_TO_DFP);
+				PE_SET_FLAG(port, PE_FLAGS_MODAL_OPERATION);
+			}
+			if (vdo_cmd == CMD_EXIT_MODE)
+				PE_CLR_FLAG(port, PE_FLAGS_MODAL_OPERATION);
+		} else if (!vdo_len) {
+			tx_payload[0] |= VDO_CMDT(CMDT_RSP_NAK);
+			vdo_len = 1;
+		} else {
+			tx_payload[0] |= VDO_CMDT(CMDT_RSP_BUSY);
+			vdo_len = 1;
+		}
+	} else {
 		/*
-		 * Return value of func is the data objects count in payload.
-		 * return 1 means only VDM header, no VDO.
+		 * Received at VDM command which is not supported.  PD 2.0 may
+		 * NAK or ignore the message (see TD.PD.VNDI.E1. VDM Identity
+		 * steps), but PD 3.0 must send Not_Supported (PD 3.0 Ver 2.0 +
+		 * ECNs 2020-12-10 Table 6-64 Response to an incoming
+		 * VDM or TD.PD.VNDI3.E3 VDM Identity steps)
 		 */
-		response_size_bytes =
-				func(port, tx_payload) * sizeof(*tx_payload);
-		if (response_size_bytes > 0)
-			/* ACK */
-			tx_payload[0] = VDO(
-				vdo_vdm_svid,
-				1, /* Structured VDM */
-				VDO_SVDM_VERS(pd_get_vdo_ver(port, TCPC_TX_SOP))
-				| VDO_CMDT(CMDT_RSP_ACK) |
-				VDO_OPOS(vdo_opos) |
-				vdo_cmd);
-		else if (response_size_bytes == 0)
-			/* NAK */
-			tx_payload[0] = VDO(
-				vdo_vdm_svid,
-				1, /* Structured VDM */
-				VDO_SVDM_VERS(pd_get_vdo_ver(port, TCPC_TX_SOP))
-				| VDO_CMDT(CMDT_RSP_NAK) |
-				VDO_OPOS(vdo_opos) |
-				vdo_cmd);
-		else
-			/* BUSY */
-			tx_payload[0] = VDO(
-				vdo_vdm_svid,
-				1, /* Structured VDM */
-				VDO_SVDM_VERS(pd_get_vdo_ver(port, TCPC_TX_SOP))
-				| VDO_CMDT(CMDT_RSP_BUSY) |
-				VDO_OPOS(vdo_opos) |
-				vdo_cmd);
-
-		if (response_size_bytes <= 0)
-			response_size_bytes = 4;
-	} else {
-		/* not supported : NAK it */
-		tx_payload[0] = VDO(
-			vdo_vdm_svid,
-			1, /* Structured VDM */
-			VDO_SVDM_VERS(pd_get_vdo_ver(port, TCPC_TX_SOP)) |
-			VDO_CMDT(CMDT_RSP_NAK) |
-			VDO_OPOS(vdo_opos) |
-			vdo_cmd);
-		response_size_bytes = 4;
+		if (prl_get_rev(port, TCPCI_MSG_SOP) == PD_REV30) {
+			set_state_pe(port, PE_SEND_NOT_SUPPORTED);
+			return;
+		}
+		tx_payload[0] |= VDO_CMDT(CMDT_RSP_NAK);
+		vdo_len = 1;
 	}
 
-	/* Send ACK, NAK, or BUSY */
-	tx_emsg[port].len = response_size_bytes;
-	send_data_msg(port, TCPC_TX_SOP, PD_DATA_VENDOR_DEF);
+	/* Send response message. Note len is in bytes, not VDO objects */
+	tx_emsg[port].len = (vdo_len * sizeof(uint32_t));
+	send_data_msg(port, TCPCI_MSG_SOP, PD_DATA_VENDOR_DEF);
 }
 
 static void pe_vdm_response_run(int port)
 {
+	/*
+	 * This state waits for a VDM response message to be sent. Return to the
+	 * ready state once the message has been sent, a protocol error was
+	 * detected, or if the VDM response msg was discarded based on being
+	 * interrupted by another rx message. Since VDM sequences are AMS
+	 * interruptible, there is no need to soft reset regardless of exit
+	 * reason.
+	 */
 	if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE) ||
-			PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) {
-		PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE |
-						PE_FLAGS_PROTOCOL_ERROR);
+	    PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR) ||
+	    PE_CHK_FLAG(port, PE_FLAGS_MSG_DISCARDED)) {
+		PE_CLR_MASK(port, BIT(PE_FLAGS_TX_COMPLETE_FN) |
+					  BIT(PE_FLAGS_PROTOCOL_ERROR_FN) |
+					  BIT(PE_FLAGS_MSG_DISCARDED_FN));
 
 		pe_set_ready_state(port);
 	}
@@ -5463,28 +6565,32 @@ static void pe_enter_usb_entry(int port)
 		return;
 	}
 
-	usb4_payload = enter_usb_setup_next_msg(port);
-
 	/* Port is already in USB4 mode, do not send enter USB message again */
-	if (usb4_payload < 0) {
+	if (enter_usb_entry_is_done(port)) {
 		pe_set_ready_state(port);
 		return;
 	}
 
+	if ((pe[port].tx_type == TCPCI_MSG_SOP_PRIME ||
+	     pe[port].tx_type == TCPCI_MSG_SOP_PRIME_PRIME) &&
+	    !tc_is_vconn_src(port)) {
+		if (port_try_vconn_swap(port))
+			return;
+	}
+
+	pe[port].tx_type = TCPCI_MSG_SOP;
+	usb4_payload = enter_usb_setup_next_msg(port, &pe[port].tx_type);
+
 	if (!usb4_payload) {
 		enter_usb_failed(port);
 		pe_set_ready_state(port);
 		return;
 	}
 
-	/*
-	 * TODO: b/156749387 In case of Enter USB SOP'/SOP'', check if the port
-	 * is the VCONN source, if not, request for a VCONN swap.
-	 */
 	tx_emsg[port].len = sizeof(usb4_payload);
 
 	memcpy(tx_emsg[port].buf, &usb4_payload, tx_emsg[port].len);
-	send_data_msg(port, TCPC_TX_SOP, PD_DATA_ENTER_USB);
+	send_data_msg(port, pe[port].tx_type, PD_DATA_ENTER_USB);
 	pe_sender_response_msg_entry(port);
 }
 
@@ -5513,7 +6619,7 @@ static void pe_enter_usb_run(int port)
 		return;
 	}
 
-	if (get_time().val > pe[port].sender_response_timer) {
+	if (pd_timer_is_expired(port, PE_TIMER_SENDER_RESPONSE)) {
 		pe_set_ready_state(port);
 		enter_usb_failed(port);
 		return;
@@ -5550,6 +6656,11 @@ static void pe_enter_usb_run(int port)
 	}
 }
 
+static void pe_enter_usb_exit(int port)
+{
+	pe_sender_response_msg_exit(port);
+}
+
 #ifdef CONFIG_USBC_VCONN
 /*
  * PE_VCS_Evaluate_Swap
@@ -5575,37 +6686,20 @@ static void pe_vcs_evaluate_swap_entry(int port)
 	 */
 
 	/* DPM rejects a VCONN Swap and port is not a VCONN source*/
-	if (!tc_check_vconn_swap(port) && tc_is_vconn_src(port) < 1) {
+	if (!tc_check_vconn_swap(port) || tc_is_vconn_src(port) < 1) {
 		/* NOTE: PE_VCS_Reject_Swap State embedded here */
-		send_ctrl_msg(port, TCPC_TX_SOP, PD_CTRL_REJECT);
+		send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_REJECT);
 	}
 	/* Port is not ready to perform a VCONN swap */
 	else if (tc_is_vconn_src(port) < 0) {
 		/* NOTE: PE_VCS_Reject_Swap State embedded here */
-		send_ctrl_msg(port, TCPC_TX_SOP, PD_CTRL_WAIT);
+		send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_WAIT);
 	}
 	/* Port is ready to perform a VCONN swap */
 	else {
 		/* NOTE: PE_VCS_Accept_Swap State embedded here */
 		PE_SET_FLAG(port, PE_FLAGS_ACCEPT);
-		send_ctrl_msg(port, TCPC_TX_SOP, PD_CTRL_ACCEPT);
-
-		/*
-		 * The USB PD 3.0 spec indicates that the initial VCONN source
-		 * shall cease sourcing VCONN within tVCONNSourceOff (25ms)
-		 * after receiving the PS_RDY message. However, some partners
-		 * begin sending SOP' messages only 1 ms after sending PS_RDY
-		 * during VCONN swap.
-		 *
-		 * Preemptively disable receipt of SOP' and SOP'' messages while
-		 * we wait for PS_RDY so we don't attempt to process messages
-		 * directed at the cable. If the partner fails to send PS_RDY we
-		 * perform a hard reset so no need to re-enable SOP' messages.
-		 *
-		 * We continue to source VCONN while we wait as required by the
-		 * spec.
-		 */
-		tcpm_sop_prime_disable(port);
+		send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_ACCEPT);
 	}
 }
 
@@ -5630,7 +6724,11 @@ static void pe_vcs_evaluate_swap_run(int port)
 			 */
 			pe_set_ready_state(port);
 		}
+		return;
 	}
+
+	if (pe_check_outgoing_discard(port))
+		return;
 }
 
 /*
@@ -5641,7 +6739,7 @@ static void pe_vcs_send_swap_entry(int port)
 	print_current_state(port);
 
 	/* Send a VCONN_Swap Message */
-	send_ctrl_msg(port, TCPC_TX_SOP, PD_CTRL_VCONN_SWAP);
+	send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_VCONN_SWAP);
 	pe_sender_response_msg_entry(port);
 }
 
@@ -5649,7 +6747,7 @@ static void pe_vcs_send_swap_run(int port)
 {
 	uint8_t type;
 	uint8_t cnt;
-	enum tcpm_transmit_type sop;
+	enum tcpci_msg_type sop;
 	enum pe_msg_check msg_check;
 
 	/*
@@ -5661,6 +6759,9 @@ static void pe_vcs_send_swap_run(int port)
 	    PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
 		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
 
+		/* Increment once message has successfully sent */
+		pe[port].vconn_swap_counter++;
+
 		type = PD_HEADER_TYPE(rx_emsg[port].header);
 		cnt = PD_HEADER_CNT(rx_emsg[port].header);
 		sop = PD_HEADER_GET_SOP(rx_emsg[port].header);
@@ -5677,18 +6778,13 @@ static void pe_vcs_send_swap_run(int port)
 			 *   2) The Port is not presently the VCONN Source.
 			 */
 			if (type == PD_CTRL_ACCEPT) {
-				pe[port].vconn_swap_counter = 0;
 				if (tc_is_vconn_src(port)) {
-					/*
-					 * Prevent receiving any SOP' and SOP''
-					 * messages while a swap is in progress.
-					 */
-					tcpm_sop_prime_disable(port);
-					set_state_pe(port,
+					set_state_pe(
+						port,
 						PE_VCS_WAIT_FOR_VCONN_SWAP);
 				} else {
 					set_state_pe(port,
-						PE_VCS_TURN_ON_VCONN_SWAP);
+						     PE_VCS_TURN_ON_VCONN_SWAP);
 				}
 				return;
 			}
@@ -5702,15 +6798,28 @@ static void pe_vcs_send_swap_run(int port)
 				pe_set_ready_state(port);
 				return;
 			}
+
+			/*
+			 * The Policy Engine May transition to the
+			 * PE_VCS_Force_Vconn state when:
+			 * - A Not_Supported Message is received and
+			 * - The Port is not presently the VCONN Source
+			 */
+			if (type == PD_CTRL_NOT_SUPPORTED) {
+				if (IS_ENABLED(CONFIG_USB_PD_REV30) &&
+				    !tc_is_vconn_src(port))
+					set_state_pe(port, PE_VCS_FORCE_VCONN);
+				else
+					pe_set_ready_state(port);
+				return;
+			}
 		}
 		/*
-		 * Unexpected Data Message Received
+		 * Unexpected Message Received, send soft reset with SOP* of
+		 * incoming message.
 		 */
-		else {
-			/* Send Soft Reset */
-			pe_send_soft_reset(port, sop);
-			return;
-		}
+		pe_send_soft_reset(port, sop);
+		return;
 	}
 
 	/*
@@ -5720,10 +6829,15 @@ static void pe_vcs_send_swap_run(int port)
 	 *   2) Message was discarded.
 	 */
 	if ((msg_check & PE_MSG_DISCARDED) ||
-	    get_time().val > pe[port].sender_response_timer)
+	    pd_timer_is_expired(port, PE_TIMER_SENDER_RESPONSE))
 		pe_set_ready_state(port);
 }
 
+static void pe_vcs_send_swap_exit(int port)
+{
+	pe_sender_response_msg_exit(port);
+}
+
 /*
  * PE_VCS_Wait_for_VCONN_Swap
  */
@@ -5732,7 +6846,23 @@ static void pe_vcs_wait_for_vconn_swap_entry(int port)
 	print_current_state(port);
 
 	/* Start the VCONNOnTimer */
-	pe[port].vconn_on_timer = get_time().val + PD_T_VCONN_SOURCE_ON;
+	pd_timer_enable(port, PE_TIMER_VCONN_ON, PD_T_VCONN_SOURCE_ON);
+
+	/*
+	 * The USB PD 3.0 spec indicates that the initial VCONN source
+	 * shall cease sourcing VCONN within tVCONNSourceOff (25ms)
+	 * after receiving the PS_RDY message. However, some partners
+	 * begin sending SOP' messages only 1 ms after sending PS_RDY
+	 * during VCONN swap.
+	 *
+	 * Preemptively disable receipt of SOP' and SOP'' messages while
+	 * we wait for PS_RDY so we don't attempt to process messages
+	 * directed at the cable.
+	 *
+	 * We continue to source VCONN while we wait as required by the
+	 * spec.
+	 */
+	tcpm_sop_prime_enable(port, false);
 }
 
 static void pe_vcs_wait_for_vconn_swap_run(int port)
@@ -5742,15 +6872,26 @@ static void pe_vcs_wait_for_vconn_swap_run(int port)
 	 *  1) A PS_RDY Message is received.
 	 */
 	if (PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
-		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
 		/*
 		 * PS_RDY message received
+		 *
+		 * Note: intentionally leave the receive flag set to indicate
+		 * our route on exit when PS_RDY is received.
 		 */
 		if ((PD_HEADER_CNT(rx_emsg[port].header) == 0) &&
-				(PD_HEADER_TYPE(rx_emsg[port].header) ==
-						PD_CTRL_PS_RDY)) {
+		    (PD_HEADER_EXT(rx_emsg[port].header) == 0) &&
+		    (PD_HEADER_TYPE(rx_emsg[port].header) == PD_CTRL_PS_RDY)) {
 			set_state_pe(port, PE_VCS_TURN_OFF_VCONN_SWAP);
 			return;
+		} else {
+			/*
+			 * Unexpected message received - reset with the SOP* of
+			 * the incoming message.
+			 */
+			PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
+			pe_send_soft_reset(
+				port, PD_HEADER_GET_SOP(rx_emsg[port].header));
+			return;
 		}
 	}
 
@@ -5759,14 +6900,25 @@ static void pe_vcs_wait_for_vconn_swap_run(int port)
 	 * PE_SNK_Hard_Reset state when:
 	 *   1) The VCONNOnTimer times out.
 	 */
-	if (get_time().val > pe[port].vconn_on_timer) {
-		if (pe[port].power_role == PD_ROLE_SOURCE)
-			set_state_pe(port, PE_SRC_HARD_RESET);
-		else
-			set_state_pe(port, PE_SNK_HARD_RESET);
+	if (pd_timer_is_expired(port, PE_TIMER_VCONN_ON)) {
+		pe_set_hard_reset(port);
 	}
 }
 
+static void pe_vcs_wait_for_vconn_swap_exit(int port)
+{
+	/*
+	 * If we exited without getting PS_RDY, re-enable SOP' messaging since
+	 * we are still the Vconn source.
+	 */
+	if (PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED))
+		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
+	else
+		tcpm_sop_prime_enable(port, true);
+
+	pd_timer_disable(port, PE_TIMER_VCONN_ON);
+}
+
 /*
  * PE_VCS_Turn_On_VCONN_Swap
  */
@@ -5776,26 +6928,30 @@ static void pe_vcs_turn_on_vconn_swap_entry(int port)
 
 	/* Request DPM to turn on VCONN */
 	pd_request_vconn_swap_on(port);
-	pe[port].timeout = 0;
 }
 
 static void pe_vcs_turn_on_vconn_swap_run(int port)
 {
-
 	/*
 	 * Transition to the PE_VCS_Send_Ps_Rdy state when:
 	 *  1) The Port’s VCONN is on.
 	 */
-	if (pe[port].timeout == 0 &&
-			PE_CHK_FLAG(port, PE_FLAGS_VCONN_SWAP_COMPLETE)) {
+	if (pd_timer_is_disabled(port, PE_TIMER_TIMEOUT) &&
+	    PE_CHK_FLAG(port, PE_FLAGS_VCONN_SWAP_COMPLETE)) {
 		PE_CLR_FLAG(port, PE_FLAGS_VCONN_SWAP_COMPLETE);
-		pe[port].timeout = get_time().val + PD_VCONN_SWAP_DELAY;
+		pd_timer_enable(port, PE_TIMER_TIMEOUT,
+				CONFIG_USBC_VCONN_SWAP_DELAY_US);
 	}
 
-	if (pe[port].timeout > 0 && get_time().val > pe[port].timeout)
+	if (pd_timer_is_expired(port, PE_TIMER_TIMEOUT))
 		set_state_pe(port, PE_VCS_SEND_PS_RDY_SWAP);
 }
 
+static void pe_vcs_turn_on_vconn_swap_exit(int port)
+{
+	pd_timer_disable(port, PE_TIMER_TIMEOUT);
+}
+
 /*
  * PE_VCS_Turn_Off_VCONN_Swap
  */
@@ -5805,321 +6961,1251 @@ static void pe_vcs_turn_off_vconn_swap_entry(int port)
 
 	/* Request DPM to turn off VCONN */
 	pd_request_vconn_swap_off(port);
-	pe[port].timeout = 0;
 }
 
 static void pe_vcs_turn_off_vconn_swap_run(int port)
 {
 	/* Wait for VCONN to turn off */
-	if (pe[port].timeout == 0 &&
-			PE_CHK_FLAG(port, PE_FLAGS_VCONN_SWAP_COMPLETE)) {
+	if (PE_CHK_FLAG(port, PE_FLAGS_VCONN_SWAP_COMPLETE)) {
 		PE_CLR_FLAG(port, PE_FLAGS_VCONN_SWAP_COMPLETE);
-		pe[port].timeout = get_time().val + PD_VCONN_SWAP_DELAY;
+
+		/*
+		 * A VCONN Swap Shall reset the DiscoverIdentityCounter
+		 * to zero
+		 */
+		pe[port].discover_identity_counter = 0;
+		pe[port].dr_swap_attempt_counter = 0;
+
+		if (PE_CHK_FLAG(port, PE_FLAGS_ENTERING_EPR))
+			set_state_pe(port,
+				     PE_SNK_EPR_MODE_ENTRY_WAIT_FOR_RESPONSE);
+		else
+			pe_set_ready_state(port);
+		return;
+	}
+}
+
+/*
+ * PE_VCS_Send_PS_Rdy_Swap
+ */
+static void pe_vcs_send_ps_rdy_swap_entry(int port)
+{
+	print_current_state(port);
+
+	/* Check for any interruptions to this non-interruptible AMS */
+	if (PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
+		enum tcpci_msg_type sop =
+			PD_HEADER_GET_SOP(rx_emsg[port].header);
+
+		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
+
+		/* Soft reset with the SOP* of the incoming message */
+		pe_send_soft_reset(port, sop);
+		return;
+	}
+
+	/* Send a PS_RDY Message */
+	send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_PS_RDY);
+}
+
+static void pe_vcs_send_ps_rdy_swap_run(int port)
+{
+	/*
+	 * After a VCONN Swap the VCONN Source needs to reset
+	 * the Cable Plug’s Protocol Layer in order to ensure
+	 * MessageID synchronization.
+	 */
+	if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
+		PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
+		/*
+		 * A VCONN Swap Shall reset the
+		 * DiscoverIdentityCounter to zero
+		 */
+		pe[port].discover_identity_counter = 0;
+		pe[port].dr_swap_attempt_counter = 0;
+
+		/* A SOP' soft reset is required after VCONN swap */
+		pd_dpm_request(port, DPM_REQUEST_SOP_PRIME_SOFT_RESET_SEND);
+		pe_set_ready_state(port);
+	}
+
+	if (pe_check_outgoing_discard(port))
+		return;
+
+	if (PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) {
+		PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
+		/* PS_RDY didn't send, soft reset */
+		pe_send_soft_reset(port, TCPCI_MSG_SOP);
 	}
+}
+
+/*
+ * PE_VCS_Force_Vconn
+ */
+__maybe_unused static void pe_vcs_force_vconn_entry(int port)
+{
+	print_current_state(port);
+
+	/* Request DPM to turn on VCONN */
+	pd_request_vconn_swap_on(port);
+}
+
+__maybe_unused static void pe_vcs_force_vconn_run(int port)
+{
+	/*
+	 * The Policy Engine Shall transition back to either the PE_SRC_Ready
+	 * or PE_SNK_Ready state when:
+	 *  1) The Port’s VCONN is on.
+	 *
+	 *  Note we'll wait CONFIG_USBC_VCONN_SWAP_DELAY_US, as defined by the
+	 *  board, to ensure Vconn is on.
+	 */
+	if (pd_timer_is_disabled(port, PE_TIMER_TIMEOUT) &&
+	    PE_CHK_FLAG(port, PE_FLAGS_VCONN_SWAP_COMPLETE)) {
+		PE_CLR_FLAG(port, PE_FLAGS_VCONN_SWAP_COMPLETE);
+		pd_timer_enable(port, PE_TIMER_TIMEOUT,
+				CONFIG_USBC_VCONN_SWAP_DELAY_US);
+	}
+
+	if (pd_timer_is_expired(port, PE_TIMER_TIMEOUT)) {
+		/*
+		 * Note: A cable soft reset shouldn't be necessary as a
+		 * Not_Supported reply means the partner doesn't support
+		 * sourcing Vconn and did not communicate with the cable.
+		 */
+		pe_set_ready_state(port);
+		return;
+	}
+}
+
+__maybe_unused static void pe_vcs_force_vconn_exit(int port)
+{
+	pd_timer_disable(port, PE_TIMER_TIMEOUT);
+}
+
+/*
+ * PE_VCS_CBL_SEND_SOFT_RESET
+ * Note - Entry is only when directed by the DPM. Protocol errors are handled
+ * by the PE_SEND_SOFT_RESET state.
+ */
+static void pe_vcs_cbl_send_soft_reset_entry(int port)
+{
+	print_current_state(port);
+
+	if (!pe_can_send_sop_prime(port)) {
+		/*
+		 * If we're not VCONN source, return the appropriate state.
+		 * A VCONN swap re-triggers sending SOP' soft reset
+		 */
+		if (pe_is_explicit_contract(port)) {
+			/* Return to PE_{SRC,SNK}_Ready state */
+			pe_set_ready_state(port);
+		} else {
+			/*
+			 * Not in Explicit Contract, so we must be a SRC,
+			 * return to PE_Src_Send_Capabilities.
+			 */
+			set_state_pe(port, PE_SRC_SEND_CAPABILITIES);
+		}
+		return;
+	}
+
+	send_ctrl_msg(port, TCPCI_MSG_SOP_PRIME, PD_CTRL_SOFT_RESET);
+	pe_sender_response_msg_entry(port);
+}
+
+static void pe_vcs_cbl_send_soft_reset_run(int port)
+{
+	bool cable_soft_reset_complete = false;
+	enum pe_msg_check msg_check;
+
+	msg_check = pe_sender_response_msg_run(port);
+
+	/* Got ACCEPT or REJECT from Cable Plug */
+	if ((msg_check & PE_MSG_SENT) &&
+	    PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
+		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
+		cable_soft_reset_complete = true;
+
+		/*
+		 * Note: If port partner runs PD 2.0, we must use PD 2.0 to
+		 * communicate with the cable plug when in an explicit contract.
+		 *
+		 * PD Spec Table 6-2: Revision Interoperability during an
+		 * Explicit Contract
+		 */
+		if (prl_get_rev(port, TCPCI_MSG_SOP) != PD_REV20)
+			set_cable_rev(port,
+				      PD_HEADER_REV(rx_emsg[port].header));
+	}
+
+	/* No GoodCRC received, cable is not present */
+	if (PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) {
+		PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
+		/*
+		 * TODO(b/171823328): TCPMv2: Implement cable reset
+		 * Cable reset will only be done here if we know for certain
+		 * a cable is present (we've received the SOP' DiscId response).
+		 */
+		cable_soft_reset_complete = true;
+	}
+
+	if (cable_soft_reset_complete ||
+	    pd_timer_is_expired(port, PE_TIMER_SENDER_RESPONSE) ||
+	    (msg_check & PE_MSG_DISCARDED)) {
+		if (pe_is_explicit_contract(port)) {
+			/* Return to PE_{SRC,SNK}_Ready state */
+			pe_set_ready_state(port);
+		} else {
+			/*
+			 * Not in Explicit Contract, so we must be a SRC,
+			 * return to PE_Src_Send_Capabilities.
+			 */
+			set_state_pe(port, PE_SRC_SEND_CAPABILITIES);
+		}
+	}
+}
+
+static void pe_vcs_cbl_send_soft_reset_exit(int port)
+{
+	pe_sender_response_msg_exit(port);
+}
+
+#endif /* CONFIG_USBC_VCONN */
+
+/*
+ * PE_DR_SNK_Get_Sink_Cap and PE_SRC_Get_Sink_Cap State (shared)
+ */
+static void pe_dr_get_sink_cap_entry(int port)
+{
+	print_current_state(port);
+
+	/* Send a Get Sink Cap Message */
+	send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_GET_SINK_CAP);
+	pe_sender_response_msg_entry(port);
+}
+
+static void pe_dr_get_sink_cap_run(int port)
+{
+	int type;
+	int cnt;
+	int ext;
+	enum pe_msg_check msg_check;
+	enum tcpci_msg_type sop;
+
+	/*
+	 * Check the state of the message sent
+	 */
+	msg_check = pe_sender_response_msg_run(port);
+
+	/*
+	 * Transition to PE_[SRC,SNK]_Ready when:
+	 *   1) A Sink_Capabilities Message is received
+	 *   2) Or SenderResponseTimer times out
+	 *   3) Or a Reject Message is received.
+	 *
+	 * Transition to PE_SEND_SOFT_RESET state when:
+	 *   1) An unexpected message is received
+	 */
+	if ((msg_check & PE_MSG_SENT) &&
+	    PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
+		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
+
+		type = PD_HEADER_TYPE(rx_emsg[port].header);
+		cnt = PD_HEADER_CNT(rx_emsg[port].header);
+		ext = PD_HEADER_EXT(rx_emsg[port].header);
+		sop = PD_HEADER_GET_SOP(rx_emsg[port].header);
+
+		if (ext == 0 && sop == TCPCI_MSG_SOP) {
+			if ((cnt > 0) && (type == PD_DATA_SINK_CAP)) {
+				uint32_t *payload =
+					(uint32_t *)rx_emsg[port].buf;
+				uint8_t cap_cnt =
+					rx_emsg[port].len / sizeof(uint32_t);
+
+				pe_set_snk_caps(port, cap_cnt, payload);
+
+				dpm_evaluate_sink_fixed_pdo(port, payload[0]);
+				pe_set_ready_state(port);
+				return;
+			} else if (cnt == 0 &&
+				   (type == PD_CTRL_REJECT ||
+				    type == PD_CTRL_NOT_SUPPORTED)) {
+				pe_set_ready_state(port);
+				return;
+			}
+			/* Unexpected messages fall through to soft reset */
+		}
+
+		pe_send_soft_reset(port, sop);
+		return;
+	}
+
+	/*
+	 * Transition to PE_[SRC,SNK]_Ready state when:
+	 *   1) SenderResponseTimer times out.
+	 *   2) Message was discarded.
+	 */
+	if ((msg_check & PE_MSG_DISCARDED) ||
+	    pd_timer_is_expired(port, PE_TIMER_SENDER_RESPONSE))
+		pe_set_ready_state(port);
+}
+
+static void pe_dr_get_sink_cap_exit(int port)
+{
+	pe_sender_response_msg_exit(port);
+}
+
+/*
+ * PE_DR_SNK_Give_Source_Cap
+ */
+static void pe_dr_snk_give_source_cap_entry(int port)
+{
+	print_current_state(port);
+
+	/* Send source capabilities. */
+	send_source_cap(port);
+}
+
+static void pe_dr_snk_give_source_cap_run(int port)
+{
+	/*
+	 * Transition back to PE_SNK_Ready when the Source_Capabilities message
+	 * has been successfully sent.
+	 *
+	 * Get Source Capabilities AMS is uninterruptible, but in case the
+	 * partner violates the spec then send a soft reset rather than get
+	 * stuck here.
+	 */
+	if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
+		PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
+		set_state_pe(port, PE_SNK_READY);
+	} else if (PE_CHK_FLAG(port, PE_FLAGS_MSG_DISCARDED)) {
+		pe_send_soft_reset(port, TCPCI_MSG_SOP);
+	}
+}
+
+/*
+ * PE_DR_SRC_Get_Source_Cap
+ */
+static void pe_dr_src_get_source_cap_entry(int port)
+{
+	print_current_state(port);
+
+	/* Send a Get_Source_Cap Message */
+	tx_emsg[port].len = 0;
+	send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_GET_SOURCE_CAP);
+	pe_sender_response_msg_entry(port);
+}
+
+static void pe_dr_src_get_source_cap_run(int port)
+{
+	int type;
+	int cnt;
+	int ext;
+	enum pe_msg_check msg_check;
+
+	/*
+	 * Check the state of the message sent
+	 */
+	msg_check = pe_sender_response_msg_run(port);
+
+	/*
+	 * Transition to PE_SRC_Ready when:
+	 *   1) A Source Capabilities Message is received.
+	 *   2) A Reject Message is received.
+	 */
+	if ((msg_check & PE_MSG_SENT) &&
+	    PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
+		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
+
+		type = PD_HEADER_TYPE(rx_emsg[port].header);
+		cnt = PD_HEADER_CNT(rx_emsg[port].header);
+		ext = PD_HEADER_EXT(rx_emsg[port].header);
+
+		if (ext == 0) {
+			if ((cnt > 0) && (type == PD_DATA_SOURCE_CAP)) {
+				uint32_t *payload =
+					(uint32_t *)rx_emsg[port].buf;
+
+				pd_set_src_caps(port, cnt, payload);
+
+				/*
+				 * If we'd prefer to charge from this partner,
+				 * then propose a PR swap.
+				 */
+				if (pd_can_charge_from_device(port, cnt,
+							      payload))
+					pd_request_power_swap(port);
+
+				/*
+				 * Report dual role power capability to the
+				 * charge manager if present
+				 */
+				if (IS_ENABLED(CONFIG_CHARGE_MANAGER) &&
+				    pd_get_partner_dual_role_power(port))
+					charge_manager_update_dualrole(
+						port, CAP_DUALROLE);
+
+				set_state_pe(port, PE_SRC_READY);
+			} else if ((cnt == 0) &&
+				   (type == PD_CTRL_REJECT ||
+				    type == PD_CTRL_NOT_SUPPORTED)) {
+				pd_set_src_caps(port, -1, NULL);
+				set_state_pe(port, PE_SRC_READY);
+			} else {
+				/*
+				 * On protocol error, consider source cap
+				 * retrieval a failure
+				 */
+				pd_set_src_caps(port, -1, NULL);
+				set_state_pe(port, PE_SEND_SOFT_RESET);
+			}
+			return;
+		} else {
+			pd_set_src_caps(port, -1, NULL);
+			set_state_pe(port, PE_SEND_SOFT_RESET);
+			return;
+		}
+	}
+
+	/*
+	 * Transition to PE_SRC_Ready state when:
+	 *   1) the SenderResponseTimer times out.
+	 *   2) Message was discarded.
+	 */
+	if ((msg_check & PE_MSG_DISCARDED) ||
+	    pd_timer_is_expired(port, PE_TIMER_SENDER_RESPONSE))
+		set_state_pe(port, PE_SRC_READY);
+}
+
+static void pe_dr_src_get_source_cap_exit(int port)
+{
+	pe_sender_response_msg_exit(port);
+}
+
+/*
+ * PE_Get_Revision
+ */
+__maybe_unused static void pe_get_revision_entry(int port)
+{
+	print_current_state(port);
+
+	/* Send a Get_Revision message */
+	send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_GET_REVISION);
+	pe_sender_response_msg_entry(port);
+}
+
+__maybe_unused static void pe_get_revision_run(int port)
+{
+	int type;
+	int cnt;
+	int ext;
+	enum pe_msg_check msg_check;
+
+	/* Check the state of the message sent */
+	msg_check = pe_sender_response_msg_run(port);
+
+	if ((msg_check & PE_MSG_SENT) &&
+	    PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
+		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
+
+		type = PD_HEADER_TYPE(rx_emsg[port].header);
+		cnt = PD_HEADER_CNT(rx_emsg[port].header);
+		ext = PD_HEADER_EXT(rx_emsg[port].header);
+
+		if (ext == 0 && cnt == 1 && type == PD_DATA_REVISION) {
+			/* Revision returned by partner */
+			pe[port].partner_rmdo =
+				*((struct rmdo *)rx_emsg[port].buf);
+		} else if (type != PD_CTRL_NOT_SUPPORTED) {
+			/*
+			 * If the partner response with a message other than
+			 * Revision or Not_Supported, there was an interrupt.
+			 * Setting PE_FLAGS_MSG_RECEIVED to handle unexpected
+			 * message.
+			 */
+			PE_SET_FLAG(port, PE_FLAGS_MSG_RECEIVED);
+		}
+
+		/*
+		 * Get_Revision is an interruptible AMS. Return to ready state
+		 * after response whether or not there was a protocol error.
+		 */
+		pe_set_ready_state(port);
+		return;
+	}
+
+	/*
+	 * Return to ready state if the message was discarded or timer expires
+	 */
+	if ((msg_check & PE_MSG_DISCARDED) ||
+	    pd_timer_is_expired(port, PE_TIMER_SENDER_RESPONSE))
+		pe_set_ready_state(port);
+}
+
+__maybe_unused static void pe_get_revision_exit(int port)
+{
+	pe_sender_response_msg_exit(port);
+}
+
+#ifdef CONFIG_USB_PD_DATA_RESET_MSG
+/*
+ * PE_UDR_Send_Data_Reset
+ * See PD r. 3.1, v. 1.3, Figure 8-89.
+ */
+static void pe_udr_send_data_reset_entry(int port)
+{
+	print_current_state(port);
+	/* Send Data Reset Message */
+	send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_DATA_RESET);
+	pe_sender_response_msg_entry(port);
+}
+
+static void pe_udr_send_data_reset_run(int port)
+{
+	enum pe_msg_check msg_check = pe_sender_response_msg_run(port);
+
+	/* Handle Discarded message, return to PE_SNK/SRC_READY */
+	if (msg_check & PE_MSG_DISCARDED) {
+		pe_set_ready_state(port);
+		return;
+	} else if (msg_check == PE_MSG_SEND_PENDING) {
+		/* Wait until message is sent */
+		return;
+	}
+
+	/*
+	 * Transition to the next Data Reset state after receiving Accept.
+	 * Return to the ready state after receiving Not Supported. After
+	 * receiving Reject or any other message type (Protocol Error),
+	 * transition to Error Recovery.
+	 */
+	if (PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
+		const uint32_t hdr = rx_emsg[port].header;
+
+		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
+
+		if (PD_HEADER_GET_SOP(hdr) == TCPCI_MSG_SOP &&
+		    PD_HEADER_CNT(hdr) == 0 && !PD_HEADER_EXT(hdr) &&
+		    PD_HEADER_TYPE(hdr) == PD_CTRL_ACCEPT) {
+			set_state_pe(
+				port,
+				tc_is_vconn_src(port) ?
+					PE_UDR_TURN_OFF_VCONN :
+					PE_UDR_WAIT_FOR_DATA_RESET_COMPLETE);
+			return;
+		} else if (PD_HEADER_GET_SOP(hdr) == TCPCI_MSG_SOP &&
+			   PD_HEADER_CNT(hdr) == 0 && !PD_HEADER_EXT(hdr) &&
+			   PD_HEADER_TYPE(hdr) == PD_CTRL_NOT_SUPPORTED) {
+			/* Just pretend it worked. */
+			dpm_data_reset_complete(port);
+			pe_set_ready_state(port);
+			return;
+		}
+
+		/* Otherwise, it's a protocol error. */
+		PE_SET_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
+	}
+
+	if (pd_timer_is_expired(port, PE_TIMER_SENDER_RESPONSE) ||
+	    PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) {
+		PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
+		set_state_pe(port, PE_WAIT_FOR_ERROR_RECOVERY);
+		return;
+	}
+}
+
+static void pe_udr_send_data_reset_exit(int port)
+{
+	pe_sender_response_msg_exit(port);
+}
+
+/* PE_UDR_Data_Reset_Received */
+static void pe_udr_data_reset_received_entry(int port)
+{
+	print_current_state(port);
+	/* send accept message */
+	send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_ACCEPT);
+}
+
+static void pe_udr_data_reset_received_run(int port)
+{
+	if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
+		PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
+		if (tc_is_vconn_src(port))
+			set_state_pe(port, PE_UDR_TURN_OFF_VCONN);
+		else
+			set_state_pe(port, PE_UDR_WAIT_FOR_DATA_RESET_COMPLETE);
+	} else if (PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR) ||
+		   PE_CHK_FLAG(port, PE_FLAGS_MSG_DISCARDED)) {
+		PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
+		PE_CLR_FLAG(port, PE_FLAGS_MSG_DISCARDED);
+		set_state_pe(port, PE_WAIT_FOR_ERROR_RECOVERY);
+	}
+}
+
+/* PE_UDR_Turn_Off_VCONN */
+static void pe_udr_turn_off_vconn_entry(int port)
+{
+	print_current_state(port);
+	/* Tell device policy manager to turn off VCONN */
+	pd_request_vconn_swap_off(port);
+}
+
+static void pe_udr_turn_off_vconn_run(int port)
+{
+	/* Wait until VCONN is fully discharged */
+	if (pd_timer_is_disabled(port, PE_TIMER_TIMEOUT) &&
+	    PE_CHK_FLAG(port, PE_FLAGS_VCONN_SWAP_COMPLETE)) {
+		PE_CLR_FLAG(port, PE_FLAGS_VCONN_SWAP_COMPLETE);
+		pd_timer_enable(port, PE_TIMER_TIMEOUT,
+				CONFIG_USBC_VCONN_SWAP_DELAY_US);
+	}
+
+	if (pd_timer_is_expired(port, PE_TIMER_TIMEOUT))
+		set_state_pe(port, PE_UDR_SEND_PS_RDY);
+}
+
+/* PE_UDR_Send_Ps_Rdy */
+static void pe_udr_send_ps_rdy_entry(int port)
+{
+	print_current_state(port);
+	/* Send PS Ready message */
+	send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_PS_RDY);
+}
+
+static void pe_udr_send_ps_rdy_run(int port)
+{
+	if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
+		PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
+		set_state_pe(port, PE_UDR_WAIT_FOR_DATA_RESET_COMPLETE);
+	} else if (PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR) ||
+		   PE_CHK_FLAG(port, PE_FLAGS_MSG_DISCARDED)) {
+		PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
+		PE_CLR_FLAG(port, PE_FLAGS_MSG_DISCARDED);
+		set_state_pe(port, PE_WAIT_FOR_ERROR_RECOVERY);
+	}
+}
+
+/* PE_UDR_Wait_For_Data_Reset_Complete */
+static void pe_udr_wait_for_data_reset_complete_entry(int port)
+{
+	print_current_state(port);
+}
+
+static void pe_udr_wait_for_data_reset_complete_run(int port)
+{
+	if (PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
+		const uint32_t hdr = rx_emsg[port].header;
+
+		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
+
+		/* Expecting Data_Reset_Complete. */
+		if (PD_HEADER_GET_SOP(hdr) == TCPCI_MSG_SOP &&
+		    PD_HEADER_CNT(hdr) == 0 && !PD_HEADER_EXT(hdr) &&
+		    PD_HEADER_TYPE(hdr) == PD_CTRL_DATA_RESET_COMPLETE) {
+			pe_set_ready_state(port);
+			return;
+		}
+
+		/*
+		 * Any other message is a protocol error. The spec doesn't
+		 * provide a timeout for the Data Reset process to be enforced
+		 * by the UFP. The DFP should enforce DataResetFailTimer.
+		 */
+		set_state_pe(port, PE_WAIT_FOR_ERROR_RECOVERY);
+	} else if (PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) {
+		PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
+		set_state_pe(port, PE_WAIT_FOR_ERROR_RECOVERY);
+	}
+}
+
+static void pe_udr_wait_for_data_reset_complete_exit(int port)
+{
+	dpm_data_reset_complete(port);
+}
+
+/*
+ * PE_DDR_Send_Data_Reset
+ * See PD rev 3.1, v. 1.2, Figure 8-88.
+ */
+static void pe_ddr_send_data_reset_entry(int port)
+{
+	print_current_state(port);
+	/* Send Data Reset message */
+	send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_DATA_RESET);
+	pe_sender_response_msg_entry(port);
+}
+
+static void pe_ddr_send_data_reset_run(int port)
+{
+	enum pe_msg_check msg_check = pe_sender_response_msg_run(port);
+
+	/* Handle Discarded message, return to PE_SNK/SRC_READY */
+	if (msg_check & PE_MSG_DISCARDED) {
+		pe_set_ready_state(port);
+		return;
+	} else if (msg_check == PE_MSG_SEND_PENDING) {
+		/* Wait until message is sent */
+		return;
+	}
+
+	/*
+	 * Transition to the next Data Reset state after receiving Accept.
+	 * Return to the ready state after receiving Not Supported. After
+	 * receiving Reject or any other message type (Protocol Error),
+	 * transition to Error Recovery.
+	 */
+	if (PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
+		const uint32_t hdr = rx_emsg[port].header;
+
+		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
+
+		if (PD_HEADER_GET_SOP(hdr) == TCPCI_MSG_SOP &&
+		    PD_HEADER_CNT(hdr) == 0 && !PD_HEADER_EXT(hdr) &&
+		    PD_HEADER_TYPE(hdr) == PD_CTRL_ACCEPT) {
+			/*
+			 * Start DataResetFailTimer NOTE: This timer continues
+			 * to run in every state until it is stopped or it times
+			 * out.
+			 */
+			pd_timer_enable(port, PE_TIMER_DATA_RESET_FAIL,
+					PD_T_DATA_RESET_FAIL);
+			set_state_pe(port, tc_is_vconn_src(port) ?
+						   PE_DDR_PERFORM_DATA_RESET :
+						   PE_DDR_WAIT_FOR_VCONN_OFF);
+			return;
+		} else if (PD_HEADER_GET_SOP(hdr) == TCPCI_MSG_SOP &&
+			   PD_HEADER_CNT(hdr) == 0 && !PD_HEADER_EXT(hdr) &&
+			   PD_HEADER_TYPE(hdr) == PD_CTRL_NOT_SUPPORTED) {
+			/* Just pretend it worked. */
+			dpm_data_reset_complete(port);
+			pe_set_ready_state(port);
+			return;
+		}
+
+		/* Otherwise, it's a protocol error. */
+		PE_SET_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
+	}
+
+	if (pd_timer_is_expired(port, PE_TIMER_SENDER_RESPONSE) ||
+	    PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) {
+		PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
+		set_state_pe(port, PE_WAIT_FOR_ERROR_RECOVERY);
+		return;
+	}
+}
+
+static void pe_ddr_send_data_reset_exit(int port)
+{
+	pe_sender_response_msg_exit(port);
+}
+
+/*
+ * PE_DDR_Data_Reset_Received
+ */
+static void pe_ddr_data_reset_received_entry(int port)
+{
+	print_current_state(port);
+	/* Send Data Reset message */
+	send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_ACCEPT);
+}
+
+static void pe_ddr_data_reset_received_run(int port)
+{
+	if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
+		PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
+		if (tc_is_vconn_src(port))
+			set_state_pe(port, PE_DDR_PERFORM_DATA_RESET);
+		else
+			set_state_pe(port, PE_DDR_WAIT_FOR_VCONN_OFF);
+	} else if (PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) {
+		PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
+		set_state_pe(port, PE_WAIT_FOR_ERROR_RECOVERY);
+	}
+}
+
+static void pe_ddr_data_reset_received_exit(int port)
+{
+	/*
+	 * Start DataResetFailTimer
+	 * NOTE: This timer continues to run in every state until it is stopped
+	 *	or it times out.
+	 */
+	pd_timer_enable(port, PE_TIMER_DATA_RESET_FAIL, PD_T_DATA_RESET_FAIL);
+}
+
+/*
+ * PE_DDR_Wait_For_VCONN_Off
+ */
+static void pe_ddr_wait_for_vconn_off_entry(int port)
+{
+	print_current_state(port);
+	/* Initialize and start VCONNDischargeTimer */
+	pd_timer_enable(port, PE_TIMER_VCONN_DISCHARGE, PD_T_VCONN_DISCHARGE);
+}
+
+static void pe_ddr_wait_for_vconn_off_run(int port)
+{
+	if (PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
+		const uint32_t hdr = rx_emsg[port].header;
+
+		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
+
+		if (PD_HEADER_GET_SOP(hdr) == TCPCI_MSG_SOP &&
+		    PD_HEADER_CNT(hdr) == 0 && !PD_HEADER_EXT(hdr) &&
+		    PD_HEADER_TYPE(hdr) == PD_CTRL_PS_RDY) {
+			/* PS_RDY message received */
+			pd_timer_enable(port, PE_TIMER_VCONN_REAPPLIED,
+					PD_T_VCONN_REAPPLIED);
+			set_state_pe(port, PE_DDR_PERFORM_DATA_RESET);
+			return;
+		}
+
+		/* Otherwise, it's a protocol error. */
+		PE_SET_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
+	}
+
+	if (pd_timer_is_expired(port, PE_TIMER_VCONN_DISCHARGE) ||
+	    PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) {
+		PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
+		set_state_pe(port, PE_WAIT_FOR_ERROR_RECOVERY);
+		return;
+	}
+}
+
+static void pe_ddr_wait_for_vconn_off_exit(int port)
+{
+	pd_timer_disable(port, PE_TIMER_VCONN_DISCHARGE);
+}
+
+/*
+ * PE_DDR_Perform_Data_Reset
+ * See PD rev 3.1, v. 1.2, section 6.3.14.
+ */
+static void pe_ddr_perform_data_reset_entry(int port)
+{
+	print_current_state(port);
+
+	/*
+	 * 1) The DFP shall:
+	 *    a) Disconnect the Port’s USB 2.0 D+/D- signals.
+	 *    b) If operating in USB 3.2 remove the port’s Rx Terminations.
+	 *    c) If operating in [USB4] drive the port’s SBTX to a logic low.
+	 */
+	usb_mux_set(port, USB_PD_MUX_NONE, USB_SWITCH_DISCONNECT,
+		    polarity_rm_dts(pd_get_polarity(port)));
+
+	/* 2) Both the DFP and UFP Shall exit all Alternate Modes if any. */
+	if (IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP)) {
+		pd_dfp_exit_mode(port, TCPCI_MSG_SOP, 0, 0);
+		pd_dfp_exit_mode(port, TCPCI_MSG_SOP_PRIME, 0, 0);
+		pd_dfp_exit_mode(port, TCPCI_MSG_SOP_PRIME_PRIME, 0, 0);
+	}
+
+	/* 3) Reset the cable */
+	/*
+	 * TODO(b/141363146): The PD spec is ambiguous about which state the PE
+	 * should be in during the cable reset (step 3 in section 6.3.14). If
+	 * the DFP is not the initial VCONN Source, the cable reset presumably
+	 * starts in PE_DDR_Wait_for_VCONN_Off and finishes in
+	 * PE_DDR_Perform_Data_Reset. To be consistent with the steps in 6.3.14,
+	 * that would imply that steps 1 and 2 take place in
+	 * PE_DDR_Send_Data_Reset. However, this would be inconsistent with the,
+	 * "Tell the Policy Manager to Perform Data Reset," action in
+	 * PE_DDR_Perform_Data_Reset in figure 8-88, DFP Data_Reset Message
+	 * State Diagram, since the Data Reset process would have had to start
+	 * before then. Resolve this ambiguity and update this implementation.
+	 */
+	if (IS_ENABLED(CONFIG_USBC_VCONN) && tc_is_vconn_src(port))
+		pd_request_vconn_swap_off(port);
+}
+
+static void pe_ddr_perform_data_reset_run(int port)
+{
+	/*
+	 * PE_FLAGS_VCONN_SWAP_COMPLETE may be set in 2 cases:
+	 * a) If the PE requested to turn VCONN off while entering this state,
+	 * i.e.  if the TCPM was VCONN Source at that time. If the TCPM did not
+	 * start out as VCONN Source, then PE_DDR_Wait_For_VCONN_Off will have
+	 * already started the VCONN reapplied timer.
+	 * b) When this state requests to turn VCONN on after tVCONNReapplied
+	 * expires. At this point, the Data Reset process is complete.
+	 */
+	if (IS_ENABLED(CONFIG_USBC_VCONN) && !tc_is_vconn_src(port) &&
+	    PE_CHK_FLAG(port, PE_FLAGS_VCONN_SWAP_COMPLETE)) {
+		PE_CLR_FLAG(port, PE_FLAGS_VCONN_SWAP_COMPLETE);
+		/* Wait until VCONN has discharged to start tVconnReapplied. */
+		pd_timer_enable(port, PE_TIMER_TIMEOUT,
+				CONFIG_USBC_VCONN_SWAP_DELAY_US);
+	} else if (IS_ENABLED(CONFIG_USBC_VCONN) &&
+		   pd_timer_is_expired(port, PE_TIMER_TIMEOUT)) {
+		pd_timer_disable(port, PE_TIMER_TIMEOUT);
+		pd_timer_enable(port, PE_TIMER_VCONN_REAPPLIED,
+				PD_T_VCONN_REAPPLIED);
+	} else if (IS_ENABLED(CONFIG_USBC_VCONN) &&
+		   pd_timer_is_expired(port, PE_TIMER_VCONN_REAPPLIED)) {
+		pd_request_vconn_swap_on(port);
+		pd_timer_disable(port, PE_TIMER_VCONN_REAPPLIED);
+
+		/*
+		 * 4) After tDataReset the DFP shall:
+		 *    a) Reconnect the USB 2.0 D+/D- signals.
+		 *    b) If the Port was operating in USB 3.2 or USB4 reapply
+		 *       the port’s Rx Terminations.
+		 * TODO: Section 6.3.14 implies that tDataReset is a minimum
+		 * time for the DFP to leave the lines disconnected during Data
+		 * Reset, possibly starting after the cable reset. Section
+		 * 6.6.10.2 implies that tDataReset is the maximum time for the
+		 * DFP to send Data_Reset_Complete after receiving Accept. These
+		 * interpretations are mutually exclusive. Resolve that
+		 * ambiguity and update this implementation.
+		 */
+		set_usb_mux_with_current_data_role(port);
+	} else if (IS_ENABLED(CONFIG_USBC_VCONN) &&
+		   PE_CHK_FLAG(port, PE_FLAGS_VCONN_SWAP_COMPLETE) &&
+		   tc_is_vconn_src(port)) {
+		PE_CLR_FLAG(port, PE_FLAGS_VCONN_SWAP_COMPLETE);
+		PE_SET_FLAG(port, PE_FLAGS_DATA_RESET_COMPLETE);
+	} else if (PE_CHK_FLAG(port, PE_FLAGS_DATA_RESET_COMPLETE) &&
+		   !pd_timer_is_disabled(port, PE_TIMER_DATA_RESET_FAIL)) {
+		pd_timer_disable(port, PE_TIMER_DATA_RESET_FAIL);
+		/*
+		 * Because the cable power-cycled, reset the Tx (optional) and
+		 * cached Rx (mandatory) message IDs.
+		 */
+		prl_reset_msg_ids(port, TCPCI_MSG_SOP_PRIME);
+		prl_reset_msg_ids(port, TCPCI_MSG_SOP_PRIME_PRIME);
+		send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_DATA_RESET_COMPLETE);
+	} else if (PE_CHK_FLAG(port, PE_FLAGS_DATA_RESET_COMPLETE)) {
+		/*
+		 * There is no specified response to Data_Reset_Complete, but
+		 * make sure the port partner receives it before returning to a
+		 * ready state.
+		 */
+		if (PE_CHK_FLAG(port, PE_FLAGS_MSG_DISCARDED)) {
+			PE_CLR_FLAG(port, PE_FLAGS_MSG_DISCARDED);
+			set_state_pe(port, PE_WAIT_FOR_ERROR_RECOVERY);
+		} else if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
+			PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
+			pe_set_ready_state(port);
+		}
+		return;
+	} else if (pd_timer_is_expired(port, PE_TIMER_DATA_RESET_FAIL) ||
+		   PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) {
+		PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
+		set_state_pe(port, PE_WAIT_FOR_ERROR_RECOVERY);
+		return;
+	}
+
+	/*
+	 * No messages are expected, so any received would be a protocol error.
+	 */
+	if (PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
+		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
+		set_state_pe(port, PE_WAIT_FOR_ERROR_RECOVERY);
+	}
+}
+
+static void pe_ddr_perform_data_reset_exit(int port)
+{
+	pd_timer_disable(port, PE_TIMER_VCONN_REAPPLIED);
+	pd_timer_disable(port, PE_TIMER_DATA_RESET_FAIL);
+	PE_CLR_FLAG(port, PE_FLAGS_DATA_RESET_COMPLETE);
+	pd_dpm_request(port, DPM_REQUEST_PORT_DISCOVERY);
+	dpm_data_reset_complete(port);
+}
+#endif /* CONFIG_USB_PD_DATA_RESET_MSG */
+
+#ifdef CONFIG_USB_PD_EPR
+static void pe_enter_epr_mode(int port)
+{
+	PE_CLR_FLAG(port, PE_FLAGS_ENTERING_EPR);
+	PE_CLR_FLAG(port, PE_FLAGS_EPR_EXPLICIT_EXIT);
+	PE_SET_FLAG(port, PE_FLAGS_IN_EPR);
+	CPRINTS("C%d: Entered EPR", port);
+}
+
+static void pe_exit_epr_mode(int port)
+{
+	PE_CLR_FLAG(port, PE_FLAGS_IN_EPR);
+	PE_CLR_DPM_REQUEST(port, DPM_REQUEST_EPR_MODE_EXIT);
+	CPRINTS("C%d: Exited EPR", port);
+}
+
+/*
+ * PE_SNK_EPR_KEEP_ALIVE
+ */
+static void pe_snk_epr_keep_alive_entry(int port)
+{
+	struct pd_ecdb *ecdb = (void *)tx_emsg[port].buf;
+
+	if (pe_debug_level >= DEBUG_LEVEL_2) {
+		print_current_state(port);
+	}
+
+	ecdb->type = PD_EXT_CTRL_EPR_KEEPALIVE;
+	ecdb->data = 0;
+	tx_emsg[port].len = sizeof(*ecdb);
+
+	send_ext_data_msg(port, TCPCI_MSG_SOP, PD_EXT_CONTROL);
+	pe_sender_response_msg_entry(port);
+}
+
+static void pe_snk_epr_keep_alive_run(int port)
+{
+	enum pe_msg_check msg_check = pe_sender_response_msg_run(port);
+
+	if (msg_check & PE_MSG_DISCARDED) {
+		/*
+		 * An EPR_KeepAlive was discarded due to an incoming message
+		 * from the source. Both ends know the partnership is alive. We
+		 * go back to SNK_Ready and restart the KeepAlive timer.
+		 */
+		set_state_pe(port, PE_SNK_READY);
+		return;
+	}
+
+	if (msg_check & PE_MSG_SENT &&
+	    PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
+		int type = PD_HEADER_TYPE(rx_emsg[port].header);
+		int cnt = PD_HEADER_CNT(rx_emsg[port].header);
+		int ext = PD_HEADER_EXT(rx_emsg[port].header);
+		struct pd_ecdb *ecdb = (void *)rx_emsg[port].buf;
 
-	if (pe[port].timeout > 0 && get_time().val > pe[port].timeout) {
-		/*
-		 * A VCONN Swap Shall reset the DiscoverIdentityCounter
-		 * to zero
-		 */
-		pe[port].discover_identity_counter = 0;
-		pe[port].dr_swap_attempt_counter = 0;
+		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
 
-		if (pe[port].power_role == PD_ROLE_SOURCE)
-			set_state_pe(port, PE_SRC_READY);
-		else
+		if (cnt == 0 || ext == 0 || type != PD_EXT_CONTROL) {
+			CPRINTS("C%d: Protocol Error: 0x%04x", port,
+				rx_emsg[port].header);
+			pe_send_soft_reset(port, TCPCI_MSG_SOP);
+		} else if (ecdb->type == PD_EXT_CTRL_EPR_KEEPALIVE_ACK) {
+			pe_sender_response_msg_exit(port);
 			set_state_pe(port, PE_SNK_READY);
+		}
+
+		return;
 	}
+
+	if (pd_timer_is_expired(port, PE_TIMER_SENDER_RESPONSE))
+		pe_set_hard_reset(port);
 }
 
 /*
- * PE_VCS_Send_PS_Rdy_Swap
+ * PE_SNK_SEND_EPR_MODE_ENTRY
  */
-static void pe_vcs_send_ps_rdy_swap_entry(int port)
+static void pe_snk_send_epr_mode_entry_entry(int port)
 {
+	struct eprmdo *eprmdo = (void *)tx_emsg[port].buf;
+
 	print_current_state(port);
 
-	/* Send a PS_RDY Message */
-	send_ctrl_msg(port, TCPC_TX_SOP, PD_CTRL_PS_RDY);
-	pe[port].sub = PE_SUB0;
+	PE_SET_FLAG(port, PE_FLAGS_ENTERING_EPR);
+
+	/* Send EPR mode entry message */
+	eprmdo->action = PD_EPRMDO_ACTION_ENTER;
+	eprmdo->data = 0; /* EPR Sink Operational PDP */
+	eprmdo->reserved = 0;
+	tx_emsg[port].len = sizeof(*eprmdo);
+
+	send_data_msg(port, TCPCI_MSG_SOP, PD_DATA_EPR_MODE);
+	pe_sender_response_msg_entry(port);
+
+	pd_timer_enable(port, PE_TIMER_SINK_EPR_ENTER, PD_T_ENTER_EPR);
 }
 
-static void pe_vcs_send_ps_rdy_swap_run(int port)
+static void pe_snk_send_epr_mode_entry_run(int port)
 {
-	/* TODO(b/152058087): TCPMv2: Break up pe_vcs_send_ps_rdy_swap */
-	switch (pe[port].sub) {
-	case PE_SUB0:
-		/*
-		 * After a VCONN Swap the VCONN Source needs to reset
-		 * the Cable Plug’s Protocol Layer in order to ensure
-		 * MessageID synchronization.
-		 */
-		if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
-			PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
-
-			send_ctrl_msg(port, TCPC_TX_SOP_PRIME,
-					  PD_CTRL_SOFT_RESET);
-			pe[port].sub = PE_SUB1;
-		}
-		break;
-	case PE_SUB1:
-		if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
-			PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
-			pe[port].sender_response_timer = get_time().val +
-							PD_T_SENDER_RESPONSE;
-		}
+	enum pe_msg_check msg_check;
 
-		/* Got ACCEPT or REJECT from Cable Plug */
-		if (PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED) ||
-		    get_time().val > pe[port].sender_response_timer) {
-			PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
-			/*
-			 * A VCONN Swap Shall reset the
-			 * DiscoverIdentityCounter to zero
-			 */
-			pe[port].discover_identity_counter = 0;
-			pe[port].dr_swap_attempt_counter = 0;
+	/* Check the state of the message sent */
+	msg_check = pe_sender_response_msg_run(port);
 
-			if (pe[port].power_role == PD_ROLE_SOURCE)
-				set_state_pe(port, PE_SRC_READY);
-			else
-				set_state_pe(port, PE_SNK_READY);
-		}
-		break;
-	case PE_SUB2:
-		/* Do nothing */
-		break;
+	if (msg_check & PE_MSG_DISCARDED) {
+		PE_CLR_FLAG(port, PE_FLAGS_ENTERING_EPR);
+		set_state_pe(port, PE_SNK_READY);
+		return;
 	}
 
-	if (PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) {
-		PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
+	if ((msg_check & PE_MSG_SENT) &&
+	    PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
+		uint8_t type = PD_HEADER_TYPE(rx_emsg[port].header);
+		uint8_t cnt = PD_HEADER_CNT(rx_emsg[port].header);
+		uint8_t ext = PD_HEADER_EXT(rx_emsg[port].header);
 
-		if (pe[port].sub == PE_SUB0) {
-			/* PS_RDY didn't send, soft reset */
-			pe_send_soft_reset(port, TCPC_TX_SOP);
-		} else {
+		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
+		if ((ext == 0) && (cnt > 0) && (type == PD_DATA_EPR_MODE)) {
+			struct eprmdo *eprmdo = (void *)rx_emsg[port].buf;
+
+			if (eprmdo->action == PD_EPRMDO_ACTION_ENTER_ACK) {
+				/* EPR Enter Mode Acknowledge received */
+				set_state_pe(
+					port,
+					PE_SNK_EPR_MODE_ENTRY_WAIT_FOR_RESPONSE);
+				return;
+			}
 			/*
-			 * Cable plug wasn't present,
-			 * return to ready state
+			 * Other actions should result in soft reset but not
+			 * clear from the spec. So, we just let it time out.
 			 */
-			pe_set_ready_state(port);
 		}
 	}
+
+	/* When the SinkEPREnterTimer times out, send a soft reset. */
+	if (pd_timer_is_expired(port, PE_TIMER_SINK_EPR_ENTER)) {
+		pe_send_soft_reset(port, TCPCI_MSG_SOP);
+	} else if (pd_timer_is_expired(port, PE_TIMER_SENDER_RESPONSE)) {
+		pe_send_soft_reset(port, TCPCI_MSG_SOP);
+	}
+}
+
+static void pe_snk_send_epr_mode_entry_exit(int port)
+{
+	pe_sender_response_msg_exit(port);
 }
-#endif /* CONFIG_USBC_VCONN */
 
 /*
- * PE_DR_SNK_Get_Sink_Cap
+ * PE_SNK_EPR_MODE_ENTRY_WAIT_FOR_RESPONSE
  */
-static __maybe_unused void pe_dr_snk_get_sink_cap_entry(int port)
+static void pe_snk_epr_mode_entry_wait_for_response_entry(int port)
 {
 	print_current_state(port);
-
-	/* Send a Get Sink Cap Message */
-	send_ctrl_msg(port, TCPC_TX_SOP, PD_CTRL_GET_SINK_CAP);
-	pe_sender_response_msg_entry(port);
+	/* Wait for EPR Enter Mode response */
 }
 
-static __maybe_unused void pe_dr_snk_get_sink_cap_run(int port)
+static void pe_snk_epr_mode_entry_wait_for_response_run(int port)
 {
-	int type;
-	int cnt;
-	int ext;
-	int rev;
-	enum pe_msg_check msg_check;
-
-	/*
-	 * Check the state of the message sent
-	 */
-	msg_check = pe_sender_response_msg_run(port);
+	if (PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
+		uint8_t type = PD_HEADER_TYPE(rx_emsg[port].header);
+		uint8_t cnt = PD_HEADER_CNT(rx_emsg[port].header);
+		uint8_t ext = PD_HEADER_EXT(rx_emsg[port].header);
 
-	/*
-	 * Determine if FRS is possible based on the returned Sink Caps
-	 *
-	 * Transition to PE_SNK_Ready when:
-	 *   1) A Sink_Capabilities Message is received
-	 *   2) Or SenderResponseTimer times out
-	 *   3) Or a Reject Message is received.
-	 *
-	 * Transition to PE_SEND_SOFT_RESET state when:
-	 *   1) An unexpected message is received
-	 */
-	if ((msg_check & PE_MSG_SENT) &&
-	    PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
 		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
+		if ((ext == 0) && (cnt > 0) && (type == PD_DATA_EPR_MODE)) {
+			struct eprmdo *eprmdo = (void *)rx_emsg[port].buf;
 
-		type = PD_HEADER_TYPE(rx_emsg[port].header);
-		cnt = PD_HEADER_CNT(rx_emsg[port].header);
-		ext = PD_HEADER_EXT(rx_emsg[port].header);
-		rev = PD_HEADER_REV(rx_emsg[port].header);
-
-		if (ext == 0) {
-			if ((cnt > 0) && (type == PD_DATA_SINK_CAP)) {
-				uint32_t payload =
-					*(uint32_t *)rx_emsg[port].buf;
-
-				/*
-				 * Check message to see if we can handle
-				 * FRS for this connection. Multiple PDOs
-				 * may be returned, for FRS only Fixed PDOs
-				 * shall be used, and this shall be the 1st
-				 * PDO returned.
-				 *
-				 * TODO(b/14191267): Make sure we can handle
-				 * the required current before we enable FRS.
-				 */
-				if (IS_ENABLED(CONFIG_USB_PD_REV30) &&
-					(rev > PD_REV20) &&
-					(payload & PDO_FIXED_DUAL_ROLE)) {
-					switch (payload &
-						PDO_FIXED_FRS_CURR_MASK) {
-					case PDO_FIXED_FRS_CURR_NOT_SUPPORTED:
-						break;
-					case PDO_FIXED_FRS_CURR_DFLT_USB_POWER:
-					case PDO_FIXED_FRS_CURR_1A5_AT_5V:
-					case PDO_FIXED_FRS_CURR_3A0_AT_5V:
-						typec_set_source_current_limit(
-							port, TYPEC_RP_3A0);
-						pe_set_frs_enable(port, 1);
-						break;
-					}
-				}
-				set_state_pe(port, PE_SNK_READY);
-			} else if (type == PD_CTRL_REJECT ||
-				   type == PD_CTRL_NOT_SUPPORTED) {
-				set_state_pe(port, PE_SNK_READY);
-			} else {
-				set_state_pe(port, PE_SEND_SOFT_RESET);
+			if (eprmdo->action == PD_EPRMDO_ACTION_ENTER_SUCCESS) {
+				pe_enter_epr_mode(port);
+				set_state_pe(port,
+					     PE_SNK_WAIT_FOR_CAPABILITIES);
+				return;
+			} else if (eprmdo->action ==
+				   PD_EPRMDO_ACTION_ENTER_FAILED) {
+				PE_CLR_FLAG(port, PE_FLAGS_ENTERING_EPR);
+				/* Table 6-50 EPR Mode Data Object */
+				CPRINTS("C%d: Failed to enter EPR for 0x%x",
+					port, eprmdo->data);
 			}
+			/* Fall through to soft reset. */
+		} else if ((ext == 0) && (cnt == 0) &&
+			   (type == PD_CTRL_VCONN_SWAP)) {
+			set_state_pe(port, PE_VCS_EVALUATE_SWAP);
 			return;
 		}
+		/*
+		 * 6.4.10.1 Process to enter EPR Mode
+		 * "3. If the Sink receives any Message, other than an
+		 * EPR_ModeMessage with ENTER_SUCCESS, the Sink Shall initiate a
+		 * Soft Reset."
+		 */
+		pe_send_soft_reset(port, TCPCI_MSG_SOP);
+		return;
+	}
+
+	/* When the SinkEPREnterTimer times out, send a soft reset. */
+	if (pd_timer_is_expired(port, PE_TIMER_SINK_EPR_ENTER)) {
+		PE_SET_FLAG(port, PE_FLAGS_SNK_WAIT_CAP_TIMEOUT);
+		pe_send_soft_reset(port, TCPCI_MSG_SOP);
 	}
+}
 
+static void pe_snk_epr_mode_entry_wait_for_response_exit(int port)
+{
+	pd_timer_disable(port, PE_TIMER_SINK_EPR_ENTER);
 	/*
-	 * Transition to PE_SNK_Ready state when:
-	 *   1) SenderResponseTimer times out.
-	 *   2) Message was discarded.
+	 * Figure 8-215 indicates a sink shall enter EPR Mode on exit but Figure
+	 * 6-34 indicates we enter EPR mode only on success (and soft reset
+	 * otherwise). Since the later makes sense, we don't enter EPR here.
 	 */
-	if ((msg_check & PE_MSG_DISCARDED) ||
-	    get_time().val > pe[port].sender_response_timer)
-		set_state_pe(port, PE_SNK_READY);
 }
 
 /*
- * PE_DR_SNK_Give_Source_Cap
+ * PE_SNK_SEND_EPR_MODE_EXIT
  */
-static void pe_dr_snk_give_source_cap_entry(int port)
+static void pe_snk_send_epr_mode_exit_entry(int port)
 {
+	struct eprmdo *eprmdo = (void *)tx_emsg[port].buf;
+
 	print_current_state(port);
 
-	/* Send source capabilities. */
-	send_source_cap(port);
+	/* Send EPR mode entry message */
+	eprmdo->action = PD_EPRMDO_ACTION_EXIT;
+	eprmdo->data = 0;
+	eprmdo->reserved = 0;
+	tx_emsg[port].len = sizeof(*eprmdo);
+
+	send_data_msg(port, TCPCI_MSG_SOP, PD_DATA_EPR_MODE);
+	pe_sender_response_msg_entry(port);
 }
 
-static void pe_dr_snk_give_source_cap_run(int port)
+static void pe_snk_send_epr_mode_exit_run(int port)
 {
-	/*
-	 * Transition back to PE_SNK_Ready when the Source_Capabilities message
-	 * has been successfully sent.
-	 *
-	 * Get Source Capabilities AMS is uninterruptible, but in case the
-	 * partner violates the spec then send a soft reset rather than get
-	 * stuck here.
-	 */
-	if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
-		PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
+	enum pe_msg_check msg_check = pe_sender_response_msg_run(port);
+
+	if (msg_check & PE_MSG_DISCARDED) {
 		set_state_pe(port, PE_SNK_READY);
-	} else if (PE_CHK_FLAG(port, PE_FLAGS_MSG_DISCARDED)) {
-		pe_send_soft_reset(port, TCPC_TX_SOP);
+		return;
+	}
+
+	if (msg_check & PE_MSG_SENT) {
+		pe_sender_response_msg_exit(port);
+		pe_exit_epr_mode(port);
+		set_state_pe(port, PE_SNK_WAIT_FOR_CAPABILITIES);
 	}
 }
 
 /*
- * PE_DR_SRC_Get_Source_Cap
+ * PE_SNK_EPR_MODE_EXIT_RECEIVED
  */
-static void pe_dr_src_get_source_cap_entry(int port)
+static void pe_snk_epr_mode_exit_received_entry(int port)
 {
 	print_current_state(port);
 
-	/* Send a Get_Source_Cap Message */
-	tx_emsg[port].len = 0;
-	send_ctrl_msg(port, TCPC_TX_SOP, PD_CTRL_GET_SOURCE_CAP);
-	pe_sender_response_msg_entry(port);
-}
-
-static void pe_dr_src_get_source_cap_run(int port)
-{
-	int type;
-	int cnt;
-	int ext;
-	enum pe_msg_check msg_check;
-
-	/*
-	 * Check the state of the message sent
-	 */
-	msg_check = pe_sender_response_msg_run(port);
-
 	/*
-	 * Transition to PE_SRC_Ready when:
-	 *   1) A Source Capabilities Message is received.
-	 *   2) A Reject Message is received.
+	 * Table 8-22 Steps for Exiting EPR Mode (Source Initiated) states 'The
+	 * Port Partners are in an Explicit Contract using an SPR PDO.' Thus,
+	 * it's expected Source already has sent new SPR PDOs (and we switched
+	 * to a SPR contract) before it sent EPR mode exit. Violation of this
+	 * results in a hard reset (6.4.10.3.3 Exits due to errors).
 	 */
-	if ((msg_check & PE_MSG_SENT) &&
-	    PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
-		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
-
-		type = PD_HEADER_TYPE(rx_emsg[port].header);
-		cnt = PD_HEADER_CNT(rx_emsg[port].header);
-		ext = PD_HEADER_EXT(rx_emsg[port].header);
-
-		if (ext == 0) {
-			if ((cnt > 0) && (type == PD_DATA_SOURCE_CAP)) {
-				uint32_t *payload =
-					(uint32_t *)rx_emsg[port].buf;
-
-				/*
-				 * Unconstrained power by the partner should
-				 * be enough to request a PR_Swap to use their
-				 * power instead of our battery
-				 */
-				pd_set_src_caps(port, cnt, payload);
-				if (pe[port].src_caps[0] &
-						PDO_FIXED_UNCONSTRAINED) {
-					pe[port].src_snk_pr_swap_counter = 0;
-					PE_SET_DPM_REQUEST(port,
-							DPM_REQUEST_PR_SWAP);
-				}
-
-				set_state_pe(port, PE_SRC_READY);
-			} else if (type == PD_CTRL_REJECT ||
-				   type == PD_CTRL_NOT_SUPPORTED) {
-				set_state_pe(port, PE_SRC_READY);
-			} else {
-				set_state_pe(port, PE_SEND_SOFT_RESET);
-			}
-			return;
-		}
+	if (!pe_in_spr_contract(port)) {
+		CPRINTS("C%d: Received EPR exit while in EPR contract", port);
+		pe_set_hard_reset(port);
+		return;
 	}
 
-	/*
-	 * Transition to PE_SRC_Ready state when:
-	 *   1) the SenderResponseTimer times out.
-	 *   2) Message was discarded.
-	 */
-	if ((msg_check & PE_MSG_DISCARDED) ||
-	    get_time().val > pe[port].sender_response_timer)
-		set_state_pe(port, PE_SRC_READY);
+	pe_exit_epr_mode(port);
+	set_state_pe(port, PE_SNK_WAIT_FOR_CAPABILITIES);
 }
+#endif /* CONFIG_USB_PD_EPR */
 
-const uint32_t * const pd_get_src_caps(int port)
+const uint32_t *const pd_get_src_caps(int port)
 {
 	return pe[port].src_caps;
 }
 
 void pd_set_src_caps(int port, int cnt, uint32_t *src_caps)
 {
+	const int limit = ARRAY_SIZE(pe[port].src_caps);
 	int i;
 
+	if (cnt > limit) {
+		CPRINTS("C%d: Trim PDOs (%d) exceeding limit (%d)", port, cnt,
+			limit);
+		cnt = limit;
+	}
+
 	pe[port].src_cap_cnt = cnt;
 
 	for (i = 0; i < cnt; i++)
@@ -6128,32 +8214,30 @@ void pd_set_src_caps(int port, int cnt, uint32_t *src_caps)
 
 uint8_t pd_get_src_cap_cnt(int port)
 {
-	return pe[port].src_cap_cnt;
-}
+	if (pe[port].src_cap_cnt > 0)
+		return pe[port].src_cap_cnt;
 
+	return 0;
+}
 
 /* Track access to the PD discovery structures during HC execution */
-uint32_t task_access[CONFIG_USB_PD_PORT_MAX_COUNT][DISCOVERY_TYPE_COUNT];
+atomic_t task_access[CONFIG_USB_PD_PORT_MAX_COUNT][DISCOVERY_TYPE_COUNT];
 
 void pd_dfp_discovery_init(int port)
 {
-	/*
-	 * Clear the VDM Setup Done and Modal Operation flags so we will
-	 * have a fresh discovery
-	 */
-	PE_CLR_FLAG(port, PE_FLAGS_VDM_SETUP_DONE |
-			  PE_FLAGS_MODAL_OPERATION);
-
-	deprecated_atomic_or(&task_access[port][TCPC_TX_SOP],
-			     BIT(task_get_current()));
-	deprecated_atomic_or(&task_access[port][TCPC_TX_SOP_PRIME],
-			     BIT(task_get_current()));
+	atomic_or(&task_access[port][TCPCI_MSG_SOP], BIT(task_get_current()));
+	atomic_or(&task_access[port][TCPCI_MSG_SOP_PRIME],
+		  BIT(task_get_current()));
 
 	memset(pe[port].discovery, 0, sizeof(pe[port].discovery));
-	memset(pe[port].partner_amodes, 0, sizeof(pe[port].partner_amodes));
+}
+
+void pd_dfp_mode_init(int port)
+{
+	PE_CLR_FLAG(port, PE_FLAGS_MODAL_OPERATION);
 
 	/* Reset the DPM and DP modules to enable alternate mode entry. */
-	dpm_init(port);
+	dpm_mode_exit_complete(port);
 	dp_init(port);
 
 	if (IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE))
@@ -6161,43 +8245,56 @@ void pd_dfp_discovery_init(int port)
 
 	if (IS_ENABLED(CONFIG_USB_PD_USB4))
 		enter_usb_init(port);
-}
 
-#ifdef CONFIG_USB_PD_ALT_MODE_DFP
+	if (IS_ENABLED(CONFIG_USB_PD_ALT_MODE_UFP_DP))
+		pd_ufp_set_dp_opos(port, 0);
+}
 
-void pd_discovery_access_clear(int port, enum tcpm_transmit_type type)
+__maybe_unused void pd_discovery_access_clear(int port,
+					      enum tcpci_msg_type type)
 {
-	deprecated_atomic_clear_bits(&task_access[port][type], 0xFFFFFFFF);
+	if (!IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP))
+		assert(0);
+
+	atomic_clear_bits(&task_access[port][type], 0xFFFFFFFF);
 }
 
-bool pd_discovery_access_validate(int port, enum tcpm_transmit_type type)
+__maybe_unused bool pd_discovery_access_validate(int port,
+						 enum tcpci_msg_type type)
 {
+	if (!IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP))
+		assert(0);
+
 	return !(task_access[port][type] & ~BIT(task_get_current()));
 }
 
-struct pd_discovery *pd_get_am_discovery(int port, enum tcpm_transmit_type type)
+__maybe_unused struct pd_discovery *
+pd_get_am_discovery_and_notify_access(int port, enum tcpci_msg_type type)
 {
+	atomic_or(&task_access[port][type], BIT(task_get_current()));
+	return (struct pd_discovery *)pd_get_am_discovery(port, type);
+}
+
+__maybe_unused const struct pd_discovery *
+pd_get_am_discovery(int port, enum tcpci_msg_type type)
+{
+	if (!IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP))
+		assert(0);
 	ASSERT(type < DISCOVERY_TYPE_COUNT);
 
-	deprecated_atomic_or(&task_access[port][type], BIT(task_get_current()));
 	return &pe[port].discovery[type];
 }
 
-struct partner_active_modes *pd_get_partner_active_modes(int port,
-		enum tcpm_transmit_type type)
+__maybe_unused void pd_set_dfp_enter_mode_flag(int port, bool set)
 {
-	ASSERT(type < AMODE_TYPE_COUNT);
-	return &pe[port].partner_amodes[type];
-}
+	if (!IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP))
+		assert(0);
 
-void pd_set_dfp_enter_mode_flag(int port, bool set)
-{
 	if (set)
 		PE_SET_FLAG(port, PE_FLAGS_MODAL_OPERATION);
 	else
 		PE_CLR_FLAG(port, PE_FLAGS_MODAL_OPERATION);
 }
-#endif /* CONFIG_USB_PD_ALT_MODE_DFP */
 
 const char *pe_get_current_state(int port)
 {
@@ -6209,12 +8306,14 @@ const char *pe_get_current_state(int port)
 
 uint32_t pe_get_flags(int port)
 {
-	return pe[port].flags;
+	/*
+	 * TODO(b/229655319): support more than 32 bits
+	 */
+	return pe[port].flags_a[0];
 }
 
-
-static const struct usb_state pe_states[] = {
-	/* Super States */
+static __const_data const struct usb_state pe_states[] = {
+/* Super States */
 #ifdef CONFIG_USB_PD_REV30
 	[PE_PRS_FRS_SHARED] = {
 		.entry = pe_prs_frs_shared_entry,
@@ -6231,6 +8330,7 @@ static const struct usb_state pe_states[] = {
 	[PE_SRC_STARTUP] = {
 		.entry = pe_src_startup_entry,
 		.run   = pe_src_startup_run,
+		.exit  = pe_src_startup_exit,
 	},
 	[PE_SRC_DISCOVERY] = {
 		.entry = pe_src_discovery_entry,
@@ -6239,6 +8339,7 @@ static const struct usb_state pe_states[] = {
 	[PE_SRC_SEND_CAPABILITIES] = {
 		.entry = pe_src_send_capabilities_entry,
 		.run   = pe_src_send_capabilities_run,
+		.exit  = pe_src_send_capabilities_exit,
 	},
 	[PE_SRC_NEGOTIATE_CAPABILITY] = {
 		.entry = pe_src_negotiate_capability_entry,
@@ -6246,10 +8347,12 @@ static const struct usb_state pe_states[] = {
 	[PE_SRC_TRANSITION_SUPPLY] = {
 		.entry = pe_src_transition_supply_entry,
 		.run   = pe_src_transition_supply_run,
+		.exit  = pe_src_transition_supply_exit,
 	},
 	[PE_SRC_READY] = {
 		.entry = pe_src_ready_entry,
 		.run   = pe_src_ready_run,
+		.exit   = pe_src_ready_exit,
 	},
 	[PE_SRC_DISABLED] = {
 		.entry = pe_src_disabled_entry,
@@ -6261,10 +8364,12 @@ static const struct usb_state pe_states[] = {
 	[PE_SRC_HARD_RESET] = {
 		.entry = pe_src_hard_reset_entry,
 		.run   = pe_src_hard_reset_run,
+		.exit  = pe_src_hard_reset_exit,
 	},
 	[PE_SRC_HARD_RESET_RECEIVED] = {
 		.entry = pe_src_hard_reset_received_entry,
 		.run = pe_src_hard_reset_received_run,
+		.exit = pe_src_hard_reset_received_exit,
 	},
 	[PE_SRC_TRANSITION_TO_DEFAULT] = {
 		.entry = pe_src_transition_to_default_entry,
@@ -6281,6 +8386,7 @@ static const struct usb_state pe_states[] = {
 	[PE_SNK_WAIT_FOR_CAPABILITIES] = {
 		.entry = pe_snk_wait_for_capabilities_entry,
 		.run = pe_snk_wait_for_capabilities_run,
+		.exit = pe_snk_wait_for_capabilities_exit,
 	},
 	[PE_SNK_EVALUATE_CAPABILITY] = {
 		.entry = pe_snk_evaluate_capability_entry,
@@ -6288,10 +8394,12 @@ static const struct usb_state pe_states[] = {
 	[PE_SNK_SELECT_CAPABILITY] = {
 		.entry = pe_snk_select_capability_entry,
 		.run = pe_snk_select_capability_run,
+		.exit = pe_snk_select_capability_exit,
 	},
 	[PE_SNK_READY] = {
 		.entry = pe_snk_ready_entry,
 		.run   = pe_snk_ready_run,
+		.exit   = pe_snk_ready_exit,
 	},
 	[PE_SNK_HARD_RESET] = {
 		.entry = pe_snk_hard_reset_entry,
@@ -6317,6 +8425,7 @@ static const struct usb_state pe_states[] = {
 	[PE_SEND_SOFT_RESET] = {
 		.entry = pe_send_soft_reset_entry,
 		.run = pe_send_soft_reset_run,
+		.exit = pe_send_soft_reset_exit,
 	},
 	[PE_SOFT_RESET] = {
 		.entry = pe_soft_reset_entry,
@@ -6341,6 +8450,7 @@ static const struct usb_state pe_states[] = {
 	[PE_DRS_SEND_SWAP] = {
 		.entry = pe_drs_send_swap_entry,
 		.run   = pe_drs_send_swap_run,
+		.exit  = pe_drs_send_swap_exit,
 	},
 	[PE_PRS_SRC_SNK_EVALUATE_SWAP] = {
 		.entry = pe_prs_src_snk_evaluate_swap_entry,
@@ -6349,6 +8459,7 @@ static const struct usb_state pe_states[] = {
 	[PE_PRS_SRC_SNK_TRANSITION_TO_OFF] = {
 		.entry = pe_prs_src_snk_transition_to_off_entry,
 		.run   = pe_prs_src_snk_transition_to_off_run,
+		.exit  = pe_prs_src_snk_transition_to_off_exit,
 	},
 	[PE_PRS_SRC_SNK_ASSERT_RD] = {
 		.entry = pe_prs_src_snk_assert_rd_entry,
@@ -6362,6 +8473,7 @@ static const struct usb_state pe_states[] = {
 	[PE_PRS_SRC_SNK_SEND_SWAP] = {
 		.entry = pe_prs_src_snk_send_swap_entry,
 		.run   = pe_prs_src_snk_send_swap_run,
+		.exit  = pe_prs_src_snk_send_swap_exit,
 	},
 	[PE_PRS_SNK_SRC_EVALUATE_SWAP] = {
 		.entry = pe_prs_snk_src_evaluate_swap_entry,
@@ -6375,6 +8487,7 @@ static const struct usb_state pe_states[] = {
 	[PE_PRS_SNK_SRC_TRANSITION_TO_OFF] = {
 		.entry = pe_prs_snk_src_transition_to_off_entry,
 		.run   = pe_prs_snk_src_transition_to_off_run,
+		.exit  = pe_prs_snk_src_transition_to_off_exit,
 #ifdef CONFIG_USB_PD_REV30
 		.parent = &pe_states[PE_PRS_FRS_SHARED],
 #endif /* CONFIG_USB_PD_REV30 */
@@ -6400,6 +8513,7 @@ static const struct usb_state pe_states[] = {
 	[PE_PRS_SNK_SRC_SEND_SWAP] = {
 		.entry = pe_prs_snk_src_send_swap_entry,
 		.run   = pe_prs_snk_src_send_swap_run,
+		.exit  = pe_prs_snk_src_send_swap_exit,
 #ifdef CONFIG_USB_PD_REV30
 		.parent = &pe_states[PE_PRS_FRS_SHARED],
 #endif /* CONFIG_USB_PD_REV30 */
@@ -6412,14 +8526,17 @@ static const struct usb_state pe_states[] = {
 	[PE_VCS_SEND_SWAP] = {
 		.entry = pe_vcs_send_swap_entry,
 		.run   = pe_vcs_send_swap_run,
+		.exit  = pe_vcs_send_swap_exit,
 	},
 	[PE_VCS_WAIT_FOR_VCONN_SWAP] = {
 		.entry = pe_vcs_wait_for_vconn_swap_entry,
 		.run   = pe_vcs_wait_for_vconn_swap_run,
+		.exit  = pe_vcs_wait_for_vconn_swap_exit,
 	},
 	[PE_VCS_TURN_ON_VCONN_SWAP] = {
 		.entry = pe_vcs_turn_on_vconn_swap_entry,
 		.run   = pe_vcs_turn_on_vconn_swap_run,
+		.exit  = pe_vcs_turn_on_vconn_swap_exit,
 	},
 	[PE_VCS_TURN_OFF_VCONN_SWAP] = {
 		.entry = pe_vcs_turn_off_vconn_swap_entry,
@@ -6429,6 +8546,11 @@ static const struct usb_state pe_states[] = {
 		.entry = pe_vcs_send_ps_rdy_swap_entry,
 		.run   = pe_vcs_send_ps_rdy_swap_run,
 	},
+	[PE_VCS_CBL_SEND_SOFT_RESET] = {
+		.entry  = pe_vcs_cbl_send_soft_reset_entry,
+		.run    = pe_vcs_cbl_send_soft_reset_run,
+		.exit   = pe_vcs_cbl_send_soft_reset_exit,
+	},
 #endif /* CONFIG_USBC_VCONN */
 	[PE_VDM_IDENTITY_REQUEST_CBL] = {
 		.entry  = pe_vdm_identity_request_cbl_entry,
@@ -6465,14 +8587,10 @@ static const struct usb_state pe_states[] = {
 		.run   = pe_vdm_response_run,
 		.exit  = pe_vdm_response_exit,
 	},
-	[PE_HANDLE_CUSTOM_VDM_REQUEST] = {
-		.entry = pe_handle_custom_vdm_request_entry,
-		.run   = pe_handle_custom_vdm_request_run,
-		.exit  = pe_handle_custom_vdm_request_exit,
-	},
 	[PE_DEU_SEND_ENTER_USB] = {
 		.entry = pe_enter_usb_entry,
 		.run = pe_enter_usb_run,
+		.exit = pe_enter_usb_exit,
 	},
 	[PE_WAIT_FOR_ERROR_RECOVERY] = {
 		.entry = pe_wait_for_error_recovery_entry,
@@ -6481,17 +8599,13 @@ static const struct usb_state pe_states[] = {
 	[PE_BIST_TX] = {
 		.entry = pe_bist_tx_entry,
 		.run   = pe_bist_tx_run,
+		.exit  = pe_bist_tx_exit,
 	},
-	[PE_BIST_RX] = {
-		.entry = pe_bist_rx_entry,
-		.run   = pe_bist_rx_run,
-	},
-#ifdef CONFIG_USB_PD_FRS
-	[PE_DR_SNK_GET_SINK_CAP] = {
-		.entry = pe_dr_snk_get_sink_cap_entry,
-		.run   = pe_dr_snk_get_sink_cap_run,
+	[PE_DR_GET_SINK_CAP] = {
+		.entry = pe_dr_get_sink_cap_entry,
+		.run   = pe_dr_get_sink_cap_run,
+		.exit  = pe_dr_get_sink_cap_exit,
 	},
-#endif
 	[PE_DR_SNK_GIVE_SOURCE_CAP] = {
 		.entry = pe_dr_snk_give_source_cap_entry,
 		.run = pe_dr_snk_give_source_cap_run,
@@ -6499,12 +8613,18 @@ static const struct usb_state pe_states[] = {
 	[PE_DR_SRC_GET_SOURCE_CAP] = {
 		.entry = pe_dr_src_get_source_cap_entry,
 		.run   = pe_dr_src_get_source_cap_run,
+		.exit  = pe_dr_src_get_source_cap_exit,
 	},
 #ifdef CONFIG_USB_PD_REV30
 	[PE_FRS_SNK_SRC_START_AMS] = {
 		.entry = pe_frs_snk_src_start_ams_entry,
 		.parent = &pe_states[PE_PRS_FRS_SHARED],
 	},
+	[PE_GET_REVISION] = {
+		.entry = pe_get_revision_entry,
+		.run   = pe_get_revision_run,
+		.exit  = pe_get_revision_exit,
+	},
 #ifdef CONFIG_USB_PD_EXTENDED_MESSAGES
 	[PE_GIVE_BATTERY_CAP] = {
 		.entry = pe_give_battery_cap_entry,
@@ -6514,24 +8634,108 @@ static const struct usb_state pe_states[] = {
 		.entry = pe_give_battery_status_entry,
 		.run   = pe_give_battery_status_run,
 	},
+	[PE_GIVE_STATUS] = {
+		.entry = pe_give_status_entry,
+		.run   = pe_give_status_run,
+	},
 	[PE_SEND_ALERT] = {
 		.entry = pe_send_alert_entry,
 		.run   = pe_send_alert_run,
 	},
+	[PE_ALERT_RECEIVED] = {
+		.entry = pe_alert_received_entry,
+	},
 #else
 	[PE_SRC_CHUNK_RECEIVED] = {
 		.entry = pe_chunk_received_entry,
 		.run   = pe_chunk_received_run,
+		.exit  = pe_chunk_received_exit,
 	},
 	[PE_SNK_CHUNK_RECEIVED] = {
 		.entry = pe_chunk_received_entry,
 		.run   = pe_chunk_received_run,
+		.exit  = pe_chunk_received_exit,
 	},
 #endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
+#ifdef CONFIG_USBC_VCONN
+	[PE_VCS_FORCE_VCONN] = {
+		.entry = pe_vcs_force_vconn_entry,
+		.run   = pe_vcs_force_vconn_run,
+		.exit  = pe_vcs_force_vconn_exit,
+	},
+#endif /* CONFIG_USBC_VCONN */
+#ifdef CONFIG_USB_PD_DATA_RESET_MSG
+	[PE_UDR_SEND_DATA_RESET] = {
+		.entry = pe_udr_send_data_reset_entry,
+		.run   = pe_udr_send_data_reset_run,
+		.exit  = pe_udr_send_data_reset_exit,
+	},
+	[PE_UDR_DATA_RESET_RECEIVED] = {
+		.entry = pe_udr_data_reset_received_entry,
+		.run   = pe_udr_data_reset_received_run,
+	},
+	[PE_UDR_TURN_OFF_VCONN] = {
+		.entry = pe_udr_turn_off_vconn_entry,
+		.run   = pe_udr_turn_off_vconn_run,
+	},
+	[PE_UDR_SEND_PS_RDY] = {
+		.entry = pe_udr_send_ps_rdy_entry,
+		.run   = pe_udr_send_ps_rdy_run,
+	},
+	[PE_UDR_WAIT_FOR_DATA_RESET_COMPLETE] = {
+		.entry = pe_udr_wait_for_data_reset_complete_entry,
+		.run   = pe_udr_wait_for_data_reset_complete_run,
+		.exit  = pe_udr_wait_for_data_reset_complete_exit,
+	},
+	[PE_DDR_SEND_DATA_RESET] = {
+		.entry = pe_ddr_send_data_reset_entry,
+		.run   = pe_ddr_send_data_reset_run,
+		.exit  = pe_ddr_send_data_reset_exit,
+	},
+	[PE_DDR_DATA_RESET_RECEIVED] = {
+		.entry = pe_ddr_data_reset_received_entry,
+		.run   = pe_ddr_data_reset_received_run,
+		.exit  = pe_ddr_data_reset_received_exit,
+	},
+	[PE_DDR_WAIT_FOR_VCONN_OFF] = {
+		.entry = pe_ddr_wait_for_vconn_off_entry,
+		.run   = pe_ddr_wait_for_vconn_off_run,
+		.exit  = pe_ddr_wait_for_vconn_off_exit,
+	},
+	[PE_DDR_PERFORM_DATA_RESET] = {
+		.entry = pe_ddr_perform_data_reset_entry,
+		.run   = pe_ddr_perform_data_reset_run,
+		.exit  = pe_ddr_perform_data_reset_exit,
+	},
+#endif /* CONFIG_USB_PD_DATA_RESET_MSG */
+#ifdef CONFIG_USB_PD_EPR
+	[PE_SNK_EPR_KEEP_ALIVE] = {
+		.entry = pe_snk_epr_keep_alive_entry,
+		.run = pe_snk_epr_keep_alive_run,
+	},
+	[PE_SNK_SEND_EPR_MODE_ENTRY] = {
+		.entry = pe_snk_send_epr_mode_entry_entry,
+		.run = pe_snk_send_epr_mode_entry_run,
+		.exit = pe_snk_send_epr_mode_entry_exit,
+	},
+	[PE_SNK_EPR_MODE_ENTRY_WAIT_FOR_RESPONSE] = {
+		.entry = pe_snk_epr_mode_entry_wait_for_response_entry,
+		.run = pe_snk_epr_mode_entry_wait_for_response_run,
+		.exit = pe_snk_epr_mode_entry_wait_for_response_exit,
+	},
+	[PE_SNK_SEND_EPR_MODE_EXIT] = {
+		.entry = pe_snk_send_epr_mode_exit_entry,
+		.run = pe_snk_send_epr_mode_exit_run,
+	},
+	[PE_SNK_EPR_MODE_EXIT_RECEIVED] = {
+		.entry = pe_snk_epr_mode_exit_received_entry,
+	},
+#endif /* CONFIG_USB_PD_EPR */
 #endif /* CONFIG_USB_PD_REV30 */
 };
 
 #ifdef TEST_BUILD
+/* TODO(b/173791979): Unit tests shouldn't need to access internal states */
 const struct test_sm_data test_pe_sm_data[] = {
 	{
 		.base = pe_states,
@@ -6543,24 +8747,20 @@ const struct test_sm_data test_pe_sm_data[] = {
 BUILD_ASSERT(ARRAY_SIZE(pe_states) == ARRAY_SIZE(pe_state_names));
 const int test_pe_sm_data_size = ARRAY_SIZE(test_pe_sm_data);
 
-void pe_set_flag(int port, int flag)
-{
-	PE_SET_FLAG(port, flag);
-}
-void pe_clr_flag(int port, int flag)
+void pe_set_fn(int port, int fn)
 {
-	PE_CLR_FLAG(port, flag);
+	PE_SET_FN(port, fn);
 }
-int pe_chk_flag(int port, int flag)
+void pe_clr_fn(int port, int fn)
 {
-	return PE_CHK_FLAG(port, flag);
+	PE_CLR_FN(port, fn);
 }
-int pe_get_all_flags(int port)
+int pe_chk_fn(int port, int fn)
 {
-	return pe[port].flags;
+	return PE_CHK_FN(port, fn);
 }
-void pe_set_all_flags(int port, int flags)
+void pe_clr_dpm_requests(int port)
 {
-	pe[port].flags = flags;
+	pe[port].dpm_request = 0;
 }
 #endif
diff --git a/common/usbc/usb_pe_private.h b/common/usbc/usb_pe_private.h
new file mode 100644
index 0000000000..b71cfced86
--- /dev/null
+++ b/common/usbc/usb_pe_private.h
@@ -0,0 +1,113 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_USB_PE_PRIVATE_H
+#define __CROS_EC_USB_PE_PRIVATE_H
+
+/** Internal header file for usb_pe.
+ *
+ * EC code should not normally include this. These are exposed so they can be
+ * used by unit test code.
+ */
+
+enum {
+	/* At least one successful PD communication packet received from port
+	   partner */
+	PE_FLAGS_PD_CONNECTION_FN = 0,
+	/* Accept message received from port partner */
+	PE_FLAGS_ACCEPT_FN,
+	/* Power Supply Ready message received from port partner */
+	PE_FLAGS_PS_READY_FN,
+	/* Protocol Error was determined based on error recovery current state
+	 */
+	PE_FLAGS_PROTOCOL_ERROR_FN,
+	/* Set if we are in Modal Operation */
+	PE_FLAGS_MODAL_OPERATION_FN,
+	/* A message we requested to be sent has been transmitted */
+	PE_FLAGS_TX_COMPLETE_FN,
+	/* A message sent by a port partner has been received */
+	PE_FLAGS_MSG_RECEIVED_FN,
+	/* A hard reset has been requested but has not been sent, not currently
+	   used */
+	PE_FLAGS_HARD_RESET_PENDING_FN,
+	/* Port partner sent a Wait message. Wait before we resend our message
+	 */
+	PE_FLAGS_WAIT_FN,
+	/* An explicit contract is in place with our port partner */
+	PE_FLAGS_EXPLICIT_CONTRACT_FN,
+	/* Waiting for Sink Capabailities timed out.  Used for retry error
+	   handling */
+	PE_FLAGS_SNK_WAIT_CAP_TIMEOUT_FN,
+	/* Power Supply voltage/current transition timed out */
+	PE_FLAGS_PS_TRANSITION_TIMEOUT_FN,
+	/* Flag to note current Atomic Message Sequence is interruptible */
+	PE_FLAGS_INTERRUPTIBLE_AMS_FN,
+	/* Flag to note Power Supply reset has completed */
+	PE_FLAGS_PS_RESET_COMPLETE_FN,
+	/* VCONN swap operation has completed */
+	PE_FLAGS_VCONN_SWAP_COMPLETE_FN,
+	/* Flag to note PR Swap just completed for Startup entry */
+	PE_FLAGS_PR_SWAP_COMPLETE_FN,
+	/* Flag to note FRS/PRS context in shared state machine path */
+	PE_FLAGS_FAST_ROLE_SWAP_PATH_FN,
+	/* Flag to note if FRS listening is enabled */
+	PE_FLAGS_FAST_ROLE_SWAP_ENABLED_FN,
+	/* Flag to note TCPC passed on FRS signal from port partner */
+	PE_FLAGS_FAST_ROLE_SWAP_SIGNALED_FN,
+	/* TODO: POLICY decision: Triggers a DR SWAP attempt from UFP to DFP */
+	PE_FLAGS_DR_SWAP_TO_DFP_FN,
+	/*
+	 * TODO: POLICY decision
+	 * Flag to trigger a message resend after receiving a WAIT from port
+	 * partner
+	 */
+	PE_FLAGS_WAITING_PR_SWAP_FN,
+	/* FLAG is set when an AMS is initiated locally. ie. AP requested a
+	   PR_SWAP */
+	PE_FLAGS_LOCALLY_INITIATED_AMS_FN,
+	/* Flag to note the first message sent in PE_SRC_READY and PE_SNK_READY
+	 */
+	PE_FLAGS_FIRST_MSG_FN,
+	/* Flag to continue a VDM request if it was interrupted */
+	PE_FLAGS_VDM_REQUEST_CONTINUE_FN,
+	/* TODO: POLICY decision: Triggers a Vconn SWAP attempt to on */
+	PE_FLAGS_VCONN_SWAP_TO_ON_FN,
+	/* FLAG to track that VDM request to port partner timed out */
+	PE_FLAGS_VDM_REQUEST_TIMEOUT_FN,
+	/* FLAG to note message was discarded due to incoming message */
+	PE_FLAGS_MSG_DISCARDED_FN,
+	/* FLAG to note that hard reset can't be performed due to battery low */
+	PE_FLAGS_SNK_WAITING_BATT_FN,
+	/* FLAG to note that a data reset is complete */
+	PE_FLAGS_DATA_RESET_COMPLETE_FN,
+	/* Waiting for SRC to SNK settle time */
+	PE_FLAGS_SRC_SNK_SETTLE_FN,
+	/*
+	 * Indicates the port is in the process of entering EPR mode. For a
+	 * sink, the SM is in and after PE_SNK_EPR_Mode_Entry. For a source,
+	 * the SM is in and after PE_SRC_EPR_Mode_Entery_ACK.
+	 */
+	PE_FLAGS_ENTERING_EPR_FN,
+	/* In EPR mode */
+	PE_FLAGS_IN_EPR_FN,
+	/*
+	 * Indicate the port exited EPR mode explicitly. If this is set, the
+	 * port wouldn't enter EPR mode automatically.
+	 */
+	PE_FLAGS_EPR_EXPLICIT_EXIT_FN,
+	/* Discovery disabled due to UFP/PD 2.0 constraint. */
+	PE_FLAGS_DISCOVERY_DISABLED_FN,
+	/* Last element */
+	PE_FLAGS_COUNT
+};
+
+#ifdef TEST_BUILD
+void pe_set_fn(int port, int fn);
+void pe_clr_fn(int port, int fn);
+int pe_chk_fn(int port, int fn);
+void pe_clr_dpm_requests(int port);
+#endif /* TEST_BUILD */
+
+#endif /* __CROS_EC_USB_PE_PRIVATE_H */
diff --git a/common/usbc/usb_prl_sm.c b/common/usbc/usb_prl_sm.c
index 69861fb482..6fa3011fa7 100644
--- a/common/usbc/usb_prl_sm.c
+++ b/common/usbc/usb_prl_sm.c
@@ -1,16 +1,18 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "battery.h"
 #include "battery_smart.h"
-#include "board.h"
+#include "builtin/assert.h"
 #include "charge_manager.h"
 #include "charge_state.h"
 #include "chipset.h"
 #include "common.h"
+#include "compile_time_macros.h"
 #include "console.h"
+#include "cros_version.h"
 #include "ec_commands.h"
 #include "gpio.h"
 #include "hooks.h"
@@ -18,54 +20,74 @@
 #include "registers.h"
 #include "system.h"
 #include "task.h"
-#include "timer.h"
-#include "tcpm.h"
-#include "util.h"
+#include "tcpm/tcpm.h"
 #include "usb_charge.h"
+#include "usb_emsg.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
+#include "usb_pd_timer.h"
 #include "usb_pe_sm.h"
 #include "usb_prl_sm.h"
-#include "usb_tc_sm.h"
-#include "usb_emsg.h"
 #include "usb_sm.h"
+#include "usb_tc_sm.h"
+#include "util.h"
 #include "vpd_api.h"
-#include "version.h"
 
 #ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 #else
 #define CPRINTF(format, args...)
 #define CPRINTS(format, args...)
 #endif
 
-#define RCH_SET_FLAG(port, flag) deprecated_atomic_or(&rch[port].flags, (flag))
-#define RCH_CLR_FLAG(port, flag) \
-	deprecated_atomic_clear_bits(&rch[port].flags, (flag))
+/*
+ * Define DEBUG_PRINT_FLAG_NAMES to print flag names when set and cleared.
+ */
+#undef DEBUG_PRINT_FLAG_NAMES
+
+#ifdef DEBUG_PRINT_FLAG_NAMES
+__maybe_unused static void print_flag(const char *group, int set_or_clear,
+				      int flag);
+#define SET_FLAG(group, flags, flag)        \
+	do {                                \
+		print_flag(group, 1, flag); \
+		atomic_or(flags, (flag));   \
+	} while (0)
+#define CLR_FLAG(group, flags, flag)                \
+	do {                                        \
+		int before = *flags;                \
+		atomic_clear_bits(flags, (flag));   \
+		if (*flags != before)               \
+			print_flag(group, 0, flag); \
+	} while (0)
+#else
+#define SET_FLAG(group, flags, flag) atomic_or(flags, (flag))
+#define CLR_FLAG(group, flags, flag) atomic_clear_bits(flags, (flag))
+#endif
+
+#define RCH_SET_FLAG(port, flag) SET_FLAG("RCH", &rch[port].flags, (flag))
+#define RCH_CLR_FLAG(port, flag) CLR_FLAG("RCH", &rch[port].flags, (flag))
 #define RCH_CHK_FLAG(port, flag) (rch[port].flags & (flag))
 
-#define TCH_SET_FLAG(port, flag) deprecated_atomic_or(&tch[port].flags, (flag))
-#define TCH_CLR_FLAG(port, flag) \
-	deprecated_atomic_clear_bits(&tch[port].flags, (flag))
+#define TCH_SET_FLAG(port, flag) SET_FLAG("TCH", &tch[port].flags, (flag))
+#define TCH_CLR_FLAG(port, flag) CLR_FLAG("TCH", &tch[port].flags, (flag))
 #define TCH_CHK_FLAG(port, flag) (tch[port].flags & (flag))
 
 #define PRL_TX_SET_FLAG(port, flag) \
-	deprecated_atomic_or(&prl_tx[port].flags, (flag))
+	SET_FLAG("PRL_TX", &prl_tx[port].flags, (flag))
 #define PRL_TX_CLR_FLAG(port, flag) \
-	deprecated_atomic_clear_bits(&prl_tx[port].flags, (flag))
+	CLR_FLAG("PRL_TX", &prl_tx[port].flags, (flag))
 #define PRL_TX_CHK_FLAG(port, flag) (prl_tx[port].flags & (flag))
 
 #define PRL_HR_SET_FLAG(port, flag) \
-	deprecated_atomic_or(&prl_hr[port].flags, (flag))
+	SET_FLAG("PRL_HR", &prl_hr[port].flags, (flag))
 #define PRL_HR_CLR_FLAG(port, flag) \
-	deprecated_atomic_clear_bits(&prl_hr[port].flags, (flag))
+	CLR_FLAG("PRL_HR", &prl_hr[port].flags, (flag))
 #define PRL_HR_CHK_FLAG(port, flag) (prl_hr[port].flags & (flag))
 
-#define PDMSG_SET_FLAG(port, flag) \
-	deprecated_atomic_or(&pdmsg[port].flags, (flag))
-#define PDMSG_CLR_FLAG(port, flag) \
-	deprecated_atomic_clear_bits(&pdmsg[port].flags, (flag))
+#define PDMSG_SET_FLAG(port, flag) SET_FLAG("PDMSG", &pdmsg[port].flags, (flag))
+#define PDMSG_CLR_FLAG(port, flag) CLR_FLAG("PDMSG", &pdmsg[port].flags, (flag))
 #define PDMSG_CHK_FLAG(port, flag) (pdmsg[port].flags & (flag))
 
 /* Protocol Layer Flags */
@@ -75,30 +97,81 @@
  *	different meanings in each state machine.
  */
 /* Flag to note message transmission completed */
-#define PRL_FLAGS_TX_COMPLETE             BIT(0)
+#define PRL_FLAGS_TX_COMPLETE BIT(0)
 /* Flag to note that PRL requested to set SINK_NG CC state */
-#define PRL_FLAGS_SINK_NG                 BIT(1)
+#define PRL_FLAGS_SINK_NG BIT(1)
 /* Flag to note PRL waited for SINK_OK CC state before transmitting */
-#define PRL_FLAGS_WAIT_SINK_OK            BIT(2)
+#define PRL_FLAGS_WAIT_SINK_OK BIT(2)
 /* Flag to note transmission error occurred */
-#define PRL_FLAGS_TX_ERROR                BIT(3)
+#define PRL_FLAGS_TX_ERROR BIT(3)
 /* Flag to note PE triggered a hard reset */
-#define PRL_FLAGS_PE_HARD_RESET           BIT(4)
+#define PRL_FLAGS_PE_HARD_RESET BIT(4)
 /* Flag to note hard reset has completed */
-#define PRL_FLAGS_HARD_RESET_COMPLETE     BIT(5)
+#define PRL_FLAGS_HARD_RESET_COMPLETE BIT(5)
 /* Flag to note port partner sent a hard reset */
 #define PRL_FLAGS_PORT_PARTNER_HARD_RESET BIT(6)
 /*
  * Flag to note a message transmission has been requested. It is only cleared
  * when we send the message to the TCPC layer.
  */
-#define PRL_FLAGS_MSG_XMIT                BIT(7)
+#define PRL_FLAGS_MSG_XMIT BIT(7)
 /* Flag to note a message was received */
-#define PRL_FLAGS_MSG_RECEIVED            BIT(8)
+#define PRL_FLAGS_MSG_RECEIVED BIT(8)
 /* Flag to note aborting current TX message, not currently set */
-#define PRL_FLAGS_ABORT                   BIT(9)
+#define PRL_FLAGS_ABORT BIT(9)
 /* Flag to note current TX message uses chunking */
-#define PRL_FLAGS_CHUNKING                BIT(10)
+#define PRL_FLAGS_CHUNKING BIT(10)
+/* Flag to disable checking data role on incoming messages. */
+#define PRL_FLAGS_IGNORE_DATA_ROLE BIT(11)
+
+/* For checking flag_bit_names[] */
+#define PRL_FLAGS_COUNT 12
+
+struct bit_name {
+	int value;
+	const char *name;
+};
+
+static __const_data const struct bit_name flag_bit_names[] = {
+	{ PRL_FLAGS_TX_COMPLETE, "PRL_FLAGS_TX_COMPLETE" },
+	{ PRL_FLAGS_SINK_NG, "PRL_FLAGS_SINK_NG" },
+	{ PRL_FLAGS_WAIT_SINK_OK, "PRL_FLAGS_WAIT_SINK_OK" },
+	{ PRL_FLAGS_TX_ERROR, "PRL_FLAGS_TX_ERROR" },
+	{ PRL_FLAGS_PE_HARD_RESET, "PRL_FLAGS_PE_HARD_RESET" },
+	{ PRL_FLAGS_HARD_RESET_COMPLETE, "PRL_FLAGS_HARD_RESET_COMPLETE" },
+	{ PRL_FLAGS_PORT_PARTNER_HARD_RESET,
+	  "PRL_FLAGS_PORT_PARTNER_HARD_RESET" },
+	{ PRL_FLAGS_MSG_XMIT, "PRL_FLAGS_MSG_XMIT" },
+	{ PRL_FLAGS_MSG_RECEIVED, "PRL_FLAGS_MSG_RECEIVED" },
+	{ PRL_FLAGS_ABORT, "PRL_FLAGS_ABORT" },
+	{ PRL_FLAGS_CHUNKING, "PRL_FLAGS_CHUNKING" },
+	{ PRL_FLAGS_IGNORE_DATA_ROLE, "PRL_FLAGS_IGNORE_DATA_ROLE" },
+};
+BUILD_ASSERT(ARRAY_SIZE(flag_bit_names) == PRL_FLAGS_COUNT);
+
+__maybe_unused static void print_bits(const char *group, const char *desc,
+				      int value, const struct bit_name *names,
+				      int names_size)
+{
+	int i;
+
+	CPRINTF("%s %s 0x%x : ", group, desc, value);
+	for (i = 0; i < names_size; i++) {
+		if (value & names[i].value)
+			CPRINTF("%s | ", names[i].name);
+		value &= ~names[i].value;
+	}
+	if (value != 0)
+		CPRINTF("0x%x", value);
+	CPRINTF("\n");
+}
+
+__maybe_unused static void print_flag(const char *group, int set_or_clear,
+				      int flag)
+{
+	print_bits(group, set_or_clear ? "Set" : "Clr", flag, flag_bit_names,
+		   ARRAY_SIZE(flag_bit_names));
+}
 
 /* PD counter definitions */
 #define PD_MESSAGE_ID_COUNT 7
@@ -119,6 +192,8 @@
  */
 #ifdef CONFIG_USB_PD_DEBUG_LEVEL
 static const enum debug_level prl_debug_level = CONFIG_USB_PD_DEBUG_LEVEL;
+#elif defined(CONFIG_USB_PD_INITIAL_DEBUG_LEVEL)
+static enum debug_level prl_debug_level = CONFIG_USB_PD_INITIAL_DEBUG_LEVEL;
 #else
 static enum debug_level prl_debug_level = DEBUG_LEVEL_1;
 #endif
@@ -168,7 +243,7 @@ enum usb_tch_state {
 	TCH_REPORT_ERROR,
 };
 
-static const char * const prl_tx_state_names[] = {
+static const char *const prl_tx_state_names[] = {
 	[PRL_TX_PHY_LAYER_RESET] = "PRL_TX_PHY_LAYER_RESET",
 	[PRL_TX_WAIT_FOR_MESSAGE_REQUEST] = "PRL_TX_WAIT_FOR_MESSAGE_REQUEST",
 	[PRL_TX_LAYER_RESET_FOR_TRANSMIT] = "PRL_TX_LAYER_RESET_FOR_TRANSMIT",
@@ -180,19 +255,18 @@ static const char * const prl_tx_state_names[] = {
 	[PRL_TX_DISCARD_MESSAGE] = "PRL_TX_DISCARD_MESSAGE",
 };
 
-static const char * const prl_hr_state_names[] = {
+static const char *const prl_hr_state_names[] = {
 	[PRL_HR_WAIT_FOR_REQUEST] = "PRL_HR_WAIT_FOR_REQUEST",
 	[PRL_HR_RESET_LAYER] = "PRL_HR_RESET_LAYER",
-	[PRL_HR_WAIT_FOR_PHY_HARD_RESET_COMPLETE]
-		= "PRL_HR_WAIT_FOR_PHY_HARD_RESET_COMPLETE",
-	[PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE]
-		= "PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE",
+	[PRL_HR_WAIT_FOR_PHY_HARD_RESET_COMPLETE] =
+		"PRL_HR_WAIT_FOR_PHY_HARD_RESET_COMPLETE",
+	[PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE] =
+		"PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE",
 };
 
-#ifdef CONFIG_USB_PD_EXTENDED_MESSAGES
-static const char * const rch_state_names[] = {
-	[RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER]
-		= "RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER",
+__maybe_unused static const char *const rch_state_names[] = {
+	[RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER] =
+		"RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER",
 	[RCH_PASS_UP_MESSAGE] = "RCH_PASS_UP_MESSAGE",
 	[RCH_PROCESSING_EXTENDED_MESSAGE] = "RCH_PROCESSING_EXTENDED_MESSAGE",
 	[RCH_REQUESTING_CHUNK] = "RCH_REQUESTING_CHUNK",
@@ -200,11 +274,11 @@ static const char * const rch_state_names[] = {
 	[RCH_REPORT_ERROR] = "RCH_REPORT_ERROR",
 };
 
-static const char * const tch_state_names[] = {
-	[TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE]
-		= "TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE",
-	[TCH_WAIT_FOR_TRANSMISSION_COMPLETE]
-		= "TCH_WAIT_FOR_TRANSMISSION_COMPLETE",
+__maybe_unused static const char *const tch_state_names[] = {
+	[TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE] =
+		"TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE",
+	[TCH_WAIT_FOR_TRANSMISSION_COMPLETE] =
+		"TCH_WAIT_FOR_TRANSMISSION_COMPLETE",
 	[TCH_CONSTRUCT_CHUNKED_MESSAGE] = "TCH_CONSTRUCT_CHUNKED_MESSAGE",
 	[TCH_SENDING_CHUNKED_MESSAGE] = "TCH_SENDING_CHUNKED_MESSAGE",
 	[TCH_WAIT_CHUNK_REQUEST] = "TCH_WAIT_CHUNK_REQUEST",
@@ -212,25 +286,22 @@ static const char * const tch_state_names[] = {
 	[TCH_MESSAGE_SENT] = "TCH_MESSAGE_SENT",
 	[TCH_REPORT_ERROR] = "TCH_REPORT_ERROR",
 };
-#endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
 
 /* Forward declare full list of states. Index by above enums. */
 static const struct usb_state prl_tx_states[];
 static const struct usb_state prl_hr_states[];
 
-#ifdef CONFIG_USB_PD_EXTENDED_MESSAGES
-static const struct usb_state rch_states[];
-static const struct usb_state tch_states[];
-#endif /* CONFIG_USB_PD_REV30 */
+__maybe_unused static const struct usb_state rch_states[];
+__maybe_unused static const struct usb_state tch_states[];
 
 /* Chunked Rx State Machine Object */
 static struct rx_chunked {
 	/* state machine context */
 	struct sm_ctx ctx;
 	/* PRL_FLAGS */
-	uint32_t flags;
-	/* protocol timer */
-	uint64_t chunk_sender_response_timer;
+	atomic_t flags;
+	/* error to report when moving to rch_report_error state */
+	enum pe_error error;
 } rch[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 /* Chunked Tx State Machine Object */
@@ -238,9 +309,7 @@ static struct tx_chunked {
 	/* state machine context */
 	struct sm_ctx ctx;
 	/* state machine flags */
-	uint32_t flags;
-	/* protocol timer */
-	uint64_t chunk_sender_request_timer;
+	atomic_t flags;
 	/* error to report when moving to tch_report_error state */
 	enum pe_error error;
 } tch[CONFIG_USB_PD_PORT_MAX_COUNT];
@@ -248,7 +317,7 @@ static struct tx_chunked {
 /* Message Reception State Machine Object */
 static struct protocol_layer_rx {
 	/* received message type */
-	enum tcpm_transmit_type sop;
+	enum tcpci_msg_type sop;
 	/* message ids for all valid port partners */
 	int msg_id[NUM_SOP_STAR_TYPES];
 } prl_rx[CONFIG_USB_PD_PORT_MAX_COUNT];
@@ -258,13 +327,9 @@ static struct protocol_layer_tx {
 	/* state machine context */
 	struct sm_ctx ctx;
 	/* state machine flags */
-	uint32_t flags;
-	/* protocol timer */
-	uint64_t sink_tx_timer;
-	/* timeout to limit waiting on TCPC response (not in spec) */
-	uint64_t tcpc_tx_timeout;
+	atomic_t flags;
 	/* last message type we transmitted */
-	enum tcpm_transmit_type last_xmit_type;
+	enum tcpci_msg_type last_xmit_type;
 	/* message id counters for all 6 port partners */
 	uint32_t msg_id_counter[NUM_SOP_STAR_TYPES];
 	/* transmit status */
@@ -276,17 +341,15 @@ static struct protocol_hard_reset {
 	/* state machine context */
 	struct sm_ctx ctx;
 	/* state machine flags */
-	uint32_t flags;
-	/* protocol timer */
-	uint64_t hard_reset_complete_timer;
+	atomic_t flags;
 } prl_hr[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 /* Chunking Message Object */
 static struct pd_message {
 	/* message status flags */
-	uint32_t flags;
+	atomic_t flags;
 	/* SOP* */
-	enum tcpm_transmit_type xmit_type;
+	enum tcpci_msg_type xmit_type;
 	/* type of message */
 	uint8_t msg_type;
 	/* PD revision */
@@ -303,12 +366,24 @@ static struct pd_message {
 	uint8_t ext;
 	uint32_t chunk_number_to_send;
 	uint32_t send_offset;
-#endif /* CONFIG_USB_PD_REV30 */
+#endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
 } pdmsg[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 struct extended_msg rx_emsg[CONFIG_USB_PD_PORT_MAX_COUNT];
 struct extended_msg tx_emsg[CONFIG_USB_PD_PORT_MAX_COUNT];
 
+enum prl_event_log_state_kind {
+	/* Identifies uninitialized entries */
+	PRL_EVENT_LOG_STATE_NONE,
+	PRL_EVENT_LOG_STATE_TX,
+	PRL_EVENT_LOG_STATE_HR,
+	PRL_EVENT_LOG_STATE_RCH,
+	PRL_EVENT_LOG_STATE_TCH,
+};
+
+__maybe_unused static void
+prl_event_log_append(enum prl_event_log_state_kind kind, int port);
+
 /* Common Protocol Layer Message Transmission */
 static void prl_tx_construct_message(int port);
 static void prl_rx_wait_for_phy_message(const int port, int evt);
@@ -322,12 +397,12 @@ GEN_NOT_SUPPORTED(PRL_TX_SNK_START_AMS);
 
 GEN_NOT_SUPPORTED(RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER);
 #define RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER \
-		RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER_NOT_SUPPORTED
+	RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER_NOT_SUPPORTED
 GEN_NOT_SUPPORTED(RCH_PASS_UP_MESSAGE);
 #define RCH_PASS_UP_MESSAGE RCH_PASS_UP_MESSAGE_NOT_SUPPORTED
 GEN_NOT_SUPPORTED(RCH_PROCESSING_EXTENDED_MESSAGE);
 #define RCH_PROCESSING_EXTENDED_MESSAGE \
-		RCH_PROCESSING_EXTENDED_MESSAGE_NOT_SUPPORTED
+	RCH_PROCESSING_EXTENDED_MESSAGE_NOT_SUPPORTED
 GEN_NOT_SUPPORTED(RCH_REQUESTING_CHUNK);
 #define RCH_REQUESTING_CHUNK RCH_REQUESTING_CHUNK_NOT_SUPPORTED
 GEN_NOT_SUPPORTED(RCH_WAITING_CHUNK);
@@ -337,13 +412,13 @@ GEN_NOT_SUPPORTED(RCH_REPORT_ERROR);
 
 GEN_NOT_SUPPORTED(TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE);
 #define TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE \
-		TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE_NOT_SUPPORTED
+	TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE_NOT_SUPPORTED
 GEN_NOT_SUPPORTED(TCH_WAIT_FOR_TRANSMISSION_COMPLETE);
 #define TCH_WAIT_FOR_TRANSMISSION_COMPLETE \
-		TCH_WAIT_FOR_TRANSMISSION_COMPLETE_NOT_SUPPORTED
+	TCH_WAIT_FOR_TRANSMISSION_COMPLETE_NOT_SUPPORTED
 GEN_NOT_SUPPORTED(TCH_CONSTRUCT_CHUNKED_MESSAGE);
 #define TCH_CONSTRUCT_CHUNKED_MESSAGE \
-		TCH_CONSTRUCT_CHUNKED_MESSAGE_NOT_SUPPORTED
+	TCH_CONSTRUCT_CHUNKED_MESSAGE_NOT_SUPPORTED
 GEN_NOT_SUPPORTED(TCH_SENDING_CHUNKED_MESSAGE);
 #define TCH_SENDING_CHUNKED_MESSAGE TCH_SENDING_CHUNKED_MESSAGE_NOT_SUPPORTED
 GEN_NOT_SUPPORTED(TCH_WAIT_CHUNK_REQUEST);
@@ -356,6 +431,8 @@ GEN_NOT_SUPPORTED(TCH_REPORT_ERROR);
 #define TCH_REPORT_ERROR TCH_REPORT_ERROR_NOT_SUPPORTED
 #endif /* !CONFIG_USB_PD_REV30 */
 
+/* To store the time stamp when TCPC sets TX Complete Success */
+static timestamp_t tcpc_tx_success_ts[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 /* Set the protocol transmit statemachine to a new state. */
 static void set_state_prl_tx(const int port,
@@ -373,9 +450,10 @@ test_export_static enum usb_prl_tx_state prl_tx_get_state(const int port)
 /* Print the protocol transmit statemachine's current state. */
 static void print_current_prl_tx_state(const int port)
 {
+	prl_event_log_append(PRL_EVENT_LOG_STATE_TX, port);
 	if (prl_debug_level >= DEBUG_LEVEL_3)
 		CPRINTS("C%d: %s", port,
-				prl_tx_state_names[prl_tx_get_state(port)]);
+			prl_tx_state_names[prl_tx_get_state(port)]);
 }
 
 /* Set the hard reset statemachine to a new state. */
@@ -394,17 +472,17 @@ enum usb_prl_hr_state prl_hr_get_state(const int port)
 /* Print the hard reset statemachine's current state. */
 static void print_current_prl_hr_state(const int port)
 {
+	prl_event_log_append(PRL_EVENT_LOG_STATE_HR, port);
 	if (prl_debug_level >= DEBUG_LEVEL_3)
 		CPRINTS("C%d: %s", port,
-				prl_hr_state_names[prl_hr_get_state(port)]);
+			prl_hr_state_names[prl_hr_get_state(port)]);
 }
 
 /* Set the chunked Rx statemachine to a new state. */
 static void set_state_rch(const int port, const enum usb_rch_state new_state)
 {
-#ifdef CONFIG_USB_PD_EXTENDED_MESSAGES
-	set_state(port, &rch[port].ctx, &rch_states[new_state]);
-#endif /* CONFIG_USB_PD_REV30 */
+	if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES))
+		set_state(port, &rch[port].ctx, &rch_states[new_state]);
 }
 
 #ifdef CONFIG_USB_PD_EXTENDED_MESSAGES
@@ -417,42 +495,53 @@ test_export_static enum usb_rch_state rch_get_state(const int port)
 /* Print the chunked Rx statemachine's current state. */
 static void print_current_rch_state(const int port)
 {
+	prl_event_log_append(PRL_EVENT_LOG_STATE_RCH, port);
 	if (prl_debug_level >= DEBUG_LEVEL_3)
-		CPRINTS("C%d: %s", port,
-				rch_state_names[rch_get_state(port)]);
+		CPRINTS("C%d: %s", port, rch_state_names[rch_get_state(port)]);
 }
 #endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
 
 /* Set the chunked Tx statemachine to a new state. */
 static void set_state_tch(const int port, const enum usb_tch_state new_state)
 {
-#ifdef CONFIG_USB_PD_EXTENDED_MESSAGES
-	set_state(port, &tch[port].ctx, &tch_states[new_state]);
-#endif /* CONFIG_USB_PD_REV30 */
+	if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES))
+		set_state(port, &tch[port].ctx, &tch_states[new_state]);
 }
 
 /* Get the chunked Tx statemachine's current state. */
 test_export_static enum usb_tch_state tch_get_state(const int port)
 {
-#ifdef CONFIG_USB_PD_EXTENDED_MESSAGES
-	return tch[port].ctx.current - &tch_states[0];
-#else
-	return 0;
-#endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
+	if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES))
+		return tch[port].ctx.current - &tch_states[0];
+	else
+		return 0;
 }
 
 #ifdef CONFIG_USB_PD_EXTENDED_MESSAGES
 /* Print the chunked Tx statemachine's current state. */
 static void print_current_tch_state(const int port)
 {
+	prl_event_log_append(PRL_EVENT_LOG_STATE_TCH, port);
 	if (prl_debug_level >= DEBUG_LEVEL_3)
-		CPRINTS("C%d: %s", port,
-				tch_state_names[tch_get_state(port)]);
+		CPRINTS("C%d: %s", port, tch_state_names[tch_get_state(port)]);
 }
 #endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
 
+timestamp_t prl_get_tcpc_tx_success_ts(int port)
+{
+	return tcpc_tx_success_ts[port];
+}
+
+/* Sets the time stamp when TCPC reports TX success. */
+static void set_tcpc_tx_success_ts(int port)
+{
+	tcpc_tx_success_ts[port] = get_time();
+}
+
 void pd_transmit_complete(int port, int status)
 {
+	if (status == TCPC_TX_COMPLETE_SUCCESS)
+		set_tcpc_tx_success_ts(port);
 	prl_tx[port].xmit_status = status;
 }
 
@@ -478,6 +567,14 @@ void prl_execute_hard_reset(int port)
 	task_wake(PD_PORT_TO_TASK_ID(port));
 }
 
+void prl_set_data_role_check(int port, bool enable)
+{
+	if (enable)
+		RCH_CLR_FLAG(port, PRL_FLAGS_IGNORE_DATA_ROLE);
+	else
+		RCH_SET_FLAG(port, PRL_FLAGS_IGNORE_DATA_ROLE);
+}
+
 int prl_is_running(int port)
 {
 	return local_state[port] == SM_RUN;
@@ -495,34 +592,34 @@ static void prl_init(int port)
 	prl_tx[port].flags = 0;
 	if (IS_ENABLED(CONFIG_USB_PD_REV30))
 		typec_select_src_collision_rp(port, SINK_TX_OK);
-	prl_tx[port].last_xmit_type = TCPC_TX_SOP;
+	prl_tx[port].last_xmit_type = TCPCI_MSG_SOP;
 	prl_tx[port].xmit_status = TCPC_TX_UNSET;
 
-#ifdef CONFIG_USB_PD_REV30
-	tch[port].flags = 0;
-	rch[port].flags = 0;
-#endif /* CONFIG_USB_PD_REV30 */
+	if (IS_ENABLED(CONFIG_USB_PD_REV30)) {
+		tch[port].flags = 0;
+		rch[port].flags = 0;
+	}
 
 	pdmsg[port].flags = 0;
 
 	prl_hr[port].flags = 0;
 
-	for (i = 0; i < NUM_SOP_STAR_TYPES; i++) {
-		prl_rx[port].msg_id[i] = -1;
-		prl_tx[port].msg_id_counter[i] = 0;
-	}
+	for (i = 0; i < NUM_SOP_STAR_TYPES; i++)
+		prl_reset_msg_ids(port, i);
+
+	pd_timer_disable_range(port, PR_TIMER_RANGE);
 
 	/* Clear state machines and set initial states */
 	prl_tx[port].ctx = cleared;
 	set_state_prl_tx(port, PRL_TX_PHY_LAYER_RESET);
 
-#ifdef CONFIG_USB_PD_EXTENDED_MESSAGES
-	rch[port].ctx = cleared;
-	set_state_rch(port, RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER);
+	if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES)) {
+		rch[port].ctx = cleared;
+		set_state_rch(port, RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER);
 
-	tch[port].ctx = cleared;
-	set_state_tch(port, TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE);
-#endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
+		tch[port].ctx = cleared;
+		set_state_tch(port, TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE);
+	}
 
 	prl_hr[port].ctx = cleared;
 	set_state_prl_hr(port, PRL_HR_WAIT_FOR_REQUEST);
@@ -532,9 +629,8 @@ bool prl_is_busy(int port)
 {
 #ifdef CONFIG_USB_PD_EXTENDED_MESSAGES
 	return rch_get_state(port) !=
-			RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER ||
-		tch_get_state(port) !=
-			TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE;
+		       RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER ||
+	       tch_get_state(port) != TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE;
 #else
 	return false;
 #endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
@@ -553,9 +649,8 @@ void prl_hard_reset_complete(int port)
 	task_wake(PD_PORT_TO_TASK_ID(port));
 }
 
-void prl_send_ctrl_msg(int port,
-		      enum tcpm_transmit_type type,
-		      enum pd_ctrl_msg_type msg)
+void prl_send_ctrl_msg(int port, enum tcpci_msg_type type,
+		       enum pd_ctrl_msg_type msg)
 {
 	pdmsg[port].xmit_type = type;
 	pdmsg[port].msg_type = msg;
@@ -568,14 +663,13 @@ void prl_send_ctrl_msg(int port,
 	TCH_SET_FLAG(port, PRL_FLAGS_MSG_XMIT);
 #else
 	PRL_TX_SET_FLAG(port, PRL_FLAGS_MSG_XMIT);
-#endif /* CONFIG_USB_PD_REV30 */
+#endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
 
 	task_wake(PD_PORT_TO_TASK_ID(port));
 }
 
-void prl_send_data_msg(int port,
-		      enum tcpm_transmit_type type,
-		      enum pd_data_msg_type msg)
+void prl_send_data_msg(int port, enum tcpci_msg_type type,
+		       enum pd_data_msg_type msg)
 {
 	pdmsg[port].xmit_type = type;
 	pdmsg[port].msg_type = msg;
@@ -587,15 +681,14 @@ void prl_send_data_msg(int port,
 #else
 	prl_copy_msg_to_buffer(port);
 	PRL_TX_SET_FLAG(port, PRL_FLAGS_MSG_XMIT);
-#endif /* CONFIG_USB_PD_REV30 */
+#endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
 
 	task_wake(PD_PORT_TO_TASK_ID(port));
 }
 
 #ifdef CONFIG_USB_PD_EXTENDED_MESSAGES
-void prl_send_ext_data_msg(int port,
-			  enum tcpm_transmit_type type,
-			  enum pd_ext_msg_type msg)
+void prl_send_ext_data_msg(int port, enum tcpci_msg_type type,
+			   enum pd_ext_msg_type msg)
 {
 	pdmsg[port].xmit_type = type;
 	pdmsg[port].msg_type = msg;
@@ -606,17 +699,18 @@ void prl_send_ext_data_msg(int port,
 }
 #endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
 
-static void prl_set_default_pd_revision(int port) {
+void prl_set_default_pd_revision(int port)
+{
 	/*
 	 * Initialize to highest revision supported. If the port or cable
 	 * partner doesn't support this revision, the Protocol Engine will
 	 * lower this value to the revision supported by the partner.
 	 */
-	pdmsg[port].rev[TCPC_TX_SOP] = PD_REVISION;
-	pdmsg[port].rev[TCPC_TX_SOP_PRIME] = PD_REVISION;
-	pdmsg[port].rev[TCPC_TX_SOP_PRIME_PRIME] = PD_REVISION;
-	pdmsg[port].rev[TCPC_TX_SOP_DEBUG_PRIME] = PD_REVISION;
-	pdmsg[port].rev[TCPC_TX_SOP_DEBUG_PRIME_PRIME] = PD_REVISION;
+	pdmsg[port].rev[TCPCI_MSG_SOP] = PD_REVISION;
+	pdmsg[port].rev[TCPCI_MSG_SOP_PRIME] = PD_REVISION;
+	pdmsg[port].rev[TCPCI_MSG_SOP_PRIME_PRIME] = PD_REVISION;
+	pdmsg[port].rev[TCPCI_MSG_SOP_DEBUG_PRIME] = PD_REVISION;
+	pdmsg[port].rev[TCPCI_MSG_SOP_DEBUG_PRIME_PRIME] = PD_REVISION;
 }
 
 void prl_reset_soft(int port)
@@ -628,27 +722,17 @@ void prl_reset_soft(int port)
 	task_wake(PD_PORT_TO_TASK_ID(port));
 }
 
-void prl_reset(int port)
-{
-	prl_set_default_pd_revision(port);
-	local_state[port] = SM_INIT;
-
-	/* Ensure we process the reset quickly */
-	task_wake(PD_PORT_TO_TASK_ID(port));
-}
-
 void prl_run(int port, int evt, int en)
 {
 	switch (local_state[port]) {
 	case SM_PAUSED:
 		if (!en)
 			break;
-		prl_set_default_pd_revision(port);
-		/* fall through */
+		__fallthrough;
 	case SM_INIT:
 		prl_init(port);
 		local_state[port] = SM_RUN;
-		/* fall through */
+		__fallthrough;
 	case SM_RUN:
 		if (!en) {
 			/* Disable RX */
@@ -662,43 +746,51 @@ void prl_run(int port, int evt, int en)
 			break;
 		}
 
-		/* Run Protocol Layer Message Reception */
-		prl_rx_wait_for_phy_message(port, evt);
+		/* Run Protocol Layer Hard Reset state machine */
+		run_state(port, &prl_hr[port].ctx);
 
-#ifdef CONFIG_USB_PD_EXTENDED_MESSAGES
 		/*
-		 * Run RX Chunked state machine after prl_rx. This is what
-		 * informs the PE of incoming message. Its input is prl_rx
+		 * If the Hard Reset state machine is active, then there is no
+		 * need to execute any other PRL state machines. When the hard
+		 * reset is complete, all PRL state machines will have been
+		 * reset.
 		 */
-		run_state(port, &rch[port].ctx);
+		if (prl_hr_get_state(port) == PRL_HR_WAIT_FOR_REQUEST) {
+			/* Run Protocol Layer Message Reception */
+			prl_rx_wait_for_phy_message(port, evt);
 
-		/*
-		 * Run TX Chunked state machine before prl_tx in case we need
-		 * to split an extended message and prl_tx can send it for us
-		 */
-		run_state(port, &tch[port].ctx);
-#endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
+			if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES)) {
+				/*
+				 * Run RX Chunked state machine after prl_rx.
+				 * This is what informs the PE of incoming
+				 * message. Its input is prl_rx
+				 */
+				run_state(port, &rch[port].ctx);
 
-		/* Run Protocol Layer Message Transmission state machine */
-		run_state(port, &prl_tx[port].ctx);
+				/*
+				 * Run TX Chunked state machine before prl_tx
+				 * in case we need to split an extended message
+				 * and prl_tx can send it for us
+				 */
+				run_state(port, &tch[port].ctx);
+			}
 
-#ifdef CONFIG_USB_PD_EXTENDED_MESSAGES
-		/*
-		 * Run TX Chunked state machine again after prl_tx so we can
-		 * handle passing TX_COMPLETE (or failure) up to PE in a single
-		 * iteration.
-		 */
-		run_state(port, &tch[port].ctx);
-#endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
+			/* Run Protocol Layer Message Tx state machine */
+			run_state(port, &prl_tx[port].ctx);
 
-		/* Run Protocol Layer Hard Reset state machine */
-		run_state(port, &prl_hr[port].ctx);
+			if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES))
+				/*
+				 * Run TX Chunked state machine again after
+				 * prl_tx so we can handle passing TX_COMPLETE
+				 * (or failure) up to PE in a single iteration.
+				 */
+				run_state(port, &tch[port].ctx);
+		}
 		break;
 	}
 }
 
-void prl_set_rev(int port, enum tcpm_transmit_type type,
-						enum pd_rev_type rev)
+void prl_set_rev(int port, enum tcpci_msg_type type, enum pd_rev_type rev)
 {
 	/* We only store revisions for SOP* types. */
 	ASSERT(type < NUM_SOP_STAR_TYPES);
@@ -706,7 +798,7 @@ void prl_set_rev(int port, enum tcpm_transmit_type type,
 	pdmsg[port].rev[type] = rev;
 }
 
-enum pd_rev_type prl_get_rev(int port, enum tcpm_transmit_type type)
+enum pd_rev_type prl_get_rev(int port, enum tcpci_msg_type type)
 {
 	/* We only store revisions for SOP* types. */
 	ASSERT(type < NUM_SOP_STAR_TYPES);
@@ -714,6 +806,12 @@ enum pd_rev_type prl_get_rev(int port, enum tcpm_transmit_type type)
 	return pdmsg[port].rev[type];
 }
 
+void prl_reset_msg_ids(int port, enum tcpci_msg_type type)
+{
+	prl_tx[port].msg_id_counter[type] = 0;
+	prl_rx[port].msg_id[type] = -1;
+}
+
 static void prl_copy_msg_to_buffer(int port)
 {
 	/*
@@ -739,7 +837,7 @@ static void prl_copy_msg_to_buffer(int port)
 	/* Copy message to chunked buffer */
 	memset((uint8_t *)pdmsg[port].tx_chk_buf, 0, CHK_BUF_SIZE_BYTES);
 	memcpy((uint8_t *)pdmsg[port].tx_chk_buf, (uint8_t *)tx_emsg[port].buf,
-		tx_emsg[port].len);
+	       tx_emsg[port].len);
 	/*
 	 * Pad length to 4-byte boundary and
 	 * convert to number of 32-bit objects.
@@ -753,8 +851,8 @@ static void prl_copy_msg_to_buffer(int port)
 static __maybe_unused int pdmsg_xmit_type_is_rev30(const int port)
 {
 	if (IS_ENABLED(CONFIG_USB_PD_REV30))
-		return ((pdmsg[port].xmit_type < NUM_SOP_STAR_TYPES)
-		&& (prl_get_rev(port, pdmsg[port].xmit_type) == PD_REV30));
+		return ((pdmsg[port].xmit_type < NUM_SOP_STAR_TYPES) &&
+			(prl_get_rev(port, pdmsg[port].xmit_type) == PD_REV30));
 	else
 		return 0;
 }
@@ -763,7 +861,7 @@ static __maybe_unused int pdmsg_xmit_type_is_rev30(const int port)
 static bool is_sop_rev30(const int port)
 {
 	return IS_ENABLED(CONFIG_USB_PD_REV30) &&
-	       prl_get_rev(port, TCPC_TX_SOP) == PD_REV30;
+	       prl_get_rev(port, TCPCI_MSG_SOP) == PD_REV30;
 }
 
 /* Common Protocol Layer Message Transmission */
@@ -771,8 +869,7 @@ static void prl_tx_phy_layer_reset_entry(const int port)
 {
 	print_current_prl_tx_state(port);
 
-	if (IS_ENABLED(CONFIG_USB_CTVPD)
-	 || IS_ENABLED(CONFIG_USB_VPD)) {
+	if (IS_ENABLED(CONFIG_USB_CTVPD) || IS_ENABLED(CONFIG_USB_VPD)) {
 		vpd_rx_enable(pd_is_connected(port));
 	} else {
 		/* Note: can't clear PHY messages due to TCPC architecture */
@@ -784,6 +881,8 @@ static void prl_tx_phy_layer_reset_entry(const int port)
 
 static void prl_tx_wait_for_message_request_entry(const int port)
 {
+	/* No phy layer response is pending */
+	prl_tx[port].xmit_status = TCPC_TX_UNSET;
 	print_current_prl_tx_state(port);
 }
 
@@ -807,7 +906,7 @@ static void prl_tx_wait_for_message_request_run(const int port)
 	if (IS_ENABLED(CONFIG_USB_PD_REV30) && is_sop_rev30(port) &&
 	    pe_in_local_ams(port)) {
 		if (PRL_TX_CHK_FLAG(port, PRL_FLAGS_SINK_NG |
-					  PRL_FLAGS_WAIT_SINK_OK)) {
+						  PRL_FLAGS_WAIT_SINK_OK)) {
 			/*
 			 * If we are already in an AMS then allow the
 			 * multi-message AMS to continue, even if we
@@ -838,7 +937,7 @@ static void prl_tx_wait_for_message_request_run(const int port)
 		 * Soft Reset Message Message pending
 		 */
 		if ((pdmsg[port].msg_type == PD_CTRL_SOFT_RESET) &&
-						(tx_emsg[port].len == 0)) {
+		    (tx_emsg[port].len == 0)) {
 			set_state_prl_tx(port, PRL_TX_LAYER_RESET_FOR_TRANSMIT);
 		}
 		/*
@@ -876,8 +975,17 @@ static void prl_tx_discard_message_entry(const int port)
 	 * Discard queued message
 	 * Note: We differ from spec here, which allows us to not discard on
 	 * incoming SOP' or SOP''.  However this would get the TCH out of sync.
+	 *
+	 * prl_tx will be set to this state following message reception in
+	 * prl_rx. So this path will be entered following each rx message. If
+	 * this state is entered, and there is either a message from the PE
+	 * pending, or if a message was passed to the phy and there is either no
+	 * response yet, or it was discarded in the phy layer, then a tx message
+	 * discard event has been detected.
 	 */
-	if (PRL_TX_CHK_FLAG(port, PRL_FLAGS_MSG_XMIT)) {
+	if (PRL_TX_CHK_FLAG(port, PRL_FLAGS_MSG_XMIT) ||
+	    prl_tx[port].xmit_status == TCPC_TX_WAIT ||
+	    prl_tx[port].xmit_status == TCPC_TX_COMPLETE_DISCARDED) {
 		PRL_TX_CLR_FLAG(port, PRL_FLAGS_MSG_XMIT);
 		increment_msgid_counter(port);
 		pe_report_discard(port);
@@ -935,13 +1043,25 @@ static void prl_tx_snk_start_ams_run(const int port)
  */
 static void prl_tx_layer_reset_for_transmit_entry(const int port)
 {
-	int i;
-
 	print_current_prl_tx_state(port);
 
-	/* Reset MessageIdCounters */
-	for (i = 0; i < NUM_SOP_STAR_TYPES; i++)
-		prl_tx[port].msg_id_counter[i] = 0;
+	if (pdmsg[port].xmit_type < NUM_SOP_STAR_TYPES) {
+		/*
+		 * This state is only used during soft resets. Reset only the
+		 * matching message type.
+		 *
+		 * From section 6.3.13 Soft Reset Message in the USB PD 3.0
+		 * v2.0 spec, Soft_Reset Message Shall be targeted at a
+		 * specific entity depending on the type of SOP* Packet used.
+		 *
+		 *
+		 * From section 6.11.2.3.2, the MessageID should be cleared
+		 * from the PRL_Rx_Layer_Reset_for_Receive state. However, we
+		 * don't implement a full state machine for PRL RX states so
+		 * clear the MessageID here.
+		 */
+		prl_reset_msg_ids(port, pdmsg[port].xmit_type);
+	}
 }
 
 static void prl_tx_layer_reset_for_transmit_run(const int port)
@@ -953,7 +1073,7 @@ static void prl_tx_layer_reset_for_transmit_run(const int port)
 
 static uint32_t get_sop_star_header(const int port)
 {
-	const int is_sop_packet = pdmsg[port].xmit_type == TCPC_TX_SOP;
+	const int is_sop_packet = pdmsg[port].xmit_type == TCPCI_MSG_SOP;
 	int ext;
 
 #ifdef CONFIG_USB_PD_EXTENDED_MESSAGES
@@ -963,33 +1083,32 @@ static uint32_t get_sop_star_header(const int port)
 #endif
 
 	/* SOP vs SOP'/SOP" headers are different. Replace fields as needed */
-	return PD_HEADER(
-		pdmsg[port].msg_type,
-		is_sop_packet ?
-			pd_get_power_role(port) : tc_get_cable_plug(port),
-		is_sop_packet ?
-			pd_get_data_role(port) : 0,
-		prl_tx[port].msg_id_counter[pdmsg[port].xmit_type],
-		pdmsg[port].data_objs,
-		pdmsg[port].rev[pdmsg[port].xmit_type],
-		ext);
+	return PD_HEADER(pdmsg[port].msg_type,
+			 is_sop_packet ? pd_get_power_role(port) :
+					 tc_get_cable_plug(port),
+			 is_sop_packet ? pd_get_data_role(port) : 0,
+			 prl_tx[port].msg_id_counter[pdmsg[port].xmit_type],
+			 pdmsg[port].data_objs,
+			 pdmsg[port].rev[pdmsg[port].xmit_type], ext);
 }
 
 static void prl_tx_construct_message(const int port)
 {
 	/* The header is unused for hard reset, etc. */
 	const uint32_t header = pdmsg[port].xmit_type < NUM_SOP_STAR_TYPES ?
-		get_sop_star_header(port) : 0;
+					get_sop_star_header(port) :
+					0;
 
 	/* Save SOP* so the correct msg_id_counter can be incremented */
 	prl_tx[port].last_xmit_type = pdmsg[port].xmit_type;
 
+	/* Indicate that a tx message is being passed to the phy layer */
+	prl_tx[port].xmit_status = TCPC_TX_WAIT;
 	/*
-	 * These flags could be set if this function is called before the
-	 * Policy Engine is informed of the previous transmission. Clear the
-	 * flags so that this message can be sent.
+	 * PRL_FLAGS_TX_COMPLETE could be set if this function is called before
+	 * the Policy Engine is informed of the previous transmission. Clear the
+	 * flag so that this message can be sent.
 	 */
-	prl_tx[port].xmit_status = TCPC_TX_UNSET;
 	PDMSG_CLR_FLAG(port, PRL_FLAGS_TX_COMPLETE);
 
 	/*
@@ -1011,18 +1130,11 @@ static void prl_tx_wait_for_phy_response_entry(const int port)
 {
 	print_current_prl_tx_state(port);
 
-	prl_tx[port].tcpc_tx_timeout = get_time().val + PD_T_TCPC_TX_TIMEOUT;
+	pd_timer_enable(port, PR_TIMER_TCPC_TX_TIMEOUT, PD_T_TCPC_TX_TIMEOUT);
 }
 
 static void prl_tx_wait_for_phy_response_run(const int port)
 {
-	/*
-	 * TODO(b/164154200): Revert Change-Id
-	 * If6dce35dfd78ee3a70e6216a7b6bf62d3ded5646 workaround to support
-	 * validation for Delbin build.
-	 */
-	const bool timed_out = get_time().val > prl_tx[port].tcpc_tx_timeout;
-
 	/* Wait until TX is complete */
 
 	/*
@@ -1032,8 +1144,7 @@ static void prl_tx_wait_for_phy_response_run(const int port)
 	 *       requirement.
 	 */
 
-	if ((IS_ENABLED(BOARD_DELBIN) && timed_out) ||
-	    prl_tx[port].xmit_status == TCPC_TX_COMPLETE_SUCCESS) {
+	if (prl_tx[port].xmit_status == TCPC_TX_COMPLETE_SUCCESS) {
 		/* NOTE: PRL_TX_Message_Sent State embedded here. */
 		/* Increment messageId counter */
 		increment_msgid_counter(port);
@@ -1050,9 +1161,8 @@ static void prl_tx_wait_for_phy_response_run(const int port)
 		 */
 		task_wake(PD_PORT_TO_TASK_ID(port));
 		set_state_prl_tx(port, PRL_TX_WAIT_FOR_MESSAGE_REQUEST);
-	} else if ((!IS_ENABLED(BOARD_DELBIN) && timed_out) ||
-		   prl_tx[port].xmit_status == TCPC_TX_COMPLETE_FAILED ||
-		   prl_tx[port].xmit_status == TCPC_TX_COMPLETE_DISCARDED) {
+	} else if (pd_timer_is_expired(port, PR_TIMER_TCPC_TX_TIMEOUT) ||
+		   prl_tx[port].xmit_status == TCPC_TX_COMPLETE_FAILED) {
 		/*
 		 * NOTE: PRL_Tx_Transmission_Error State embedded
 		 * here.
@@ -1078,7 +1188,7 @@ static void prl_tx_wait_for_phy_response_run(const int port)
 
 static void prl_tx_wait_for_phy_response_exit(const int port)
 {
-	prl_tx[port].xmit_status = TCPC_TX_UNSET;
+	pd_timer_disable(port, PR_TIMER_TCPC_TX_TIMEOUT);
 }
 
 /* Source Protocol Layer Message Transmission */
@@ -1090,12 +1200,12 @@ static void prl_tx_src_pending_entry(const int port)
 	print_current_prl_tx_state(port);
 
 	/* Start SinkTxTimer */
-	prl_tx[port].sink_tx_timer = get_time().val + PD_T_SINK_TX;
+	pd_timer_enable(port, PR_TIMER_SINK_TX, PD_T_SINK_TX);
 }
 
 static void prl_tx_src_pending_run(const int port)
 {
-	if (get_time().val > prl_tx[port].sink_tx_timer) {
+	if (pd_timer_is_expired(port, PR_TIMER_SINK_TX)) {
 		/*
 		 * We clear the pending XMIT flag here right before we send so
 		 * we can detect if we discarded this message or not
@@ -1107,7 +1217,7 @@ static void prl_tx_src_pending_run(const int port)
 		 * SinkTxTimer timeout
 		 */
 		if ((tx_emsg[port].len == 0) &&
-			(pdmsg[port].msg_type == PD_CTRL_SOFT_RESET)) {
+		    (pdmsg[port].msg_type == PD_CTRL_SOFT_RESET)) {
 			set_state_prl_tx(port, PRL_TX_LAYER_RESET_FOR_TRANSMIT);
 		}
 		/* Message pending (except Soft Reset) &
@@ -1122,6 +1232,11 @@ static void prl_tx_src_pending_run(const int port)
 	}
 }
 
+static void prl_tx_src_pending_exit(int port)
+{
+	pd_timer_disable(port, PR_TIMER_SINK_TX);
+}
+
 /*
  * PrlTxSnkPending
  */
@@ -1132,11 +1247,25 @@ static void prl_tx_snk_pending_entry(const int port)
 
 static void prl_tx_snk_pending_run(const int port)
 {
-	enum tcpc_cc_voltage_status cc1, cc2;
+	bool start_tx = false;
+
+	/*
+	 * Wait unit the SRC applies SINK_TX_OK so we can transmit. In FRS mode,
+	 * don't wait for SINK_TX_OK since either the source (and Rp) could be
+	 * gone or the TCPC CC_STATUS update time could be too long to meet
+	 * tFRSwapInit.
+	 */
+	if (pe_in_frs_mode(port)) {
+		/* shortcut to save some i2c_xfer calls on the FRS path. */
+		start_tx = true;
+	} else {
+		enum tcpc_cc_voltage_status cc1, cc2;
 
-	/* Wait unit the SRC applies SINK_TX_OK so we can transmit */
-	tcpm_get_cc(port, &cc1, &cc2);
-	if (cc1 == TYPEC_CC_VOLT_RP_3_0 || cc2 == TYPEC_CC_VOLT_RP_3_0) {
+		tcpm_get_cc(port, &cc1, &cc2);
+		start_tx = (cc1 == TYPEC_CC_VOLT_RP_3_0 ||
+			    cc2 == TYPEC_CC_VOLT_RP_3_0);
+	}
+	if (start_tx) {
 		/*
 		 * We clear the pending XMIT flag here right before we send so
 		 * we can detect if we discarded this message or not
@@ -1148,7 +1277,7 @@ static void prl_tx_snk_pending_run(const int port)
 		 * Rp = SinkTxOk
 		 */
 		if ((pdmsg[port].msg_type == PD_CTRL_SOFT_RESET) &&
-					(tx_emsg[port].len == 0)) {
+		    (tx_emsg[port].len == 0)) {
 			set_state_prl_tx(port, PRL_TX_LAYER_RESET_FOR_TRANSMIT);
 		}
 		/*
@@ -1164,6 +1293,25 @@ static void prl_tx_snk_pending_run(const int port)
 }
 
 /* Hard Reset Operation */
+void prl_hr_send_msg_to_phy(const int port)
+{
+	/* Header is not used for hard reset */
+	const uint32_t header = 0;
+
+	pdmsg[port].xmit_type = TCPCI_MSG_TX_HARD_RESET;
+
+	/*
+	 * These flags could be set if this function is called before the
+	 * Policy Engine is informed of the previous transmission. Clear the
+	 * flags so that this message can be sent.
+	 */
+	prl_tx[port].xmit_status = TCPC_TX_UNSET;
+	PDMSG_CLR_FLAG(port, PRL_FLAGS_TX_COMPLETE);
+
+	/* Pass message to PHY Layer */
+	tcpm_transmit(port, pdmsg[port].xmit_type, header,
+		      pdmsg[port].tx_chk_buf);
+}
 
 static void prl_hr_wait_for_request_entry(const int port)
 {
@@ -1175,7 +1323,7 @@ static void prl_hr_wait_for_request_entry(const int port)
 static void prl_hr_wait_for_request_run(const int port)
 {
 	if (PRL_HR_CHK_FLAG(port, PRL_FLAGS_PE_HARD_RESET |
-				PRL_FLAGS_PORT_PARTNER_HARD_RESET))
+					  PRL_FLAGS_PORT_PARTNER_HARD_RESET))
 		set_state_prl_hr(port, PRL_HR_RESET_LAYER);
 }
 
@@ -1188,35 +1336,46 @@ static void prl_hr_reset_layer_entry(const int port)
 
 	print_current_prl_hr_state(port);
 
-	/* reset messageIDCounters */
-	for (i = 0; i < NUM_SOP_STAR_TYPES; i++)
-		prl_tx[port].msg_id_counter[i] = 0;
-	/*
-	 * Protocol Layer message transmission transitions to
-	 * PRL_Tx_Wait_For_Message_Request state.
-	 */
-	set_state_prl_tx(port, PRL_TX_WAIT_FOR_MESSAGE_REQUEST);
-
-#ifdef CONFIG_USB_PD_EXTENDED_MESSAGES
-	tch[port].flags = 0;
-	rch[port].flags = 0;
-#endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
+	if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES)) {
+		tch[port].flags = 0;
+		rch[port].flags = 0;
+	}
 
 	pdmsg[port].flags = 0;
 
-	/* Reset message ids */
+	/* Hard reset resets messageIDCounters for all TX types */
 	for (i = 0; i < NUM_SOP_STAR_TYPES; i++) {
-		prl_rx[port].msg_id[i] = -1;
-		prl_tx[port].msg_id_counter[i] = 0;
+		prl_reset_msg_ids(port, i);
 	}
 
 	/* Disable RX */
-	if (IS_ENABLED(CONFIG_USB_CTVPD) ||
-	    IS_ENABLED(CONFIG_USB_VPD))
+	if (IS_ENABLED(CONFIG_USB_CTVPD) || IS_ENABLED(CONFIG_USB_VPD))
 		vpd_rx_enable(0);
 	else
 		tcpm_set_rx_enable(port, 0);
 
+	/*
+	 * PD r3.0 v2.0, ss6.2.1.1.5:
+	 * After a physical or logical (USB Type-C Error Recovery) Attach, a
+	 * Port discovers the common Specification Revision level between itself
+	 * and its Port Partner and/or the Cable Plug(s), and uses this
+	 * Specification Revision level until a Detach, Hard Reset or Error
+	 * Recovery happens.
+	 *
+	 * This covers the Hard Reset case.
+	 */
+	prl_set_default_pd_revision(port);
+
+	/* Inform the AP of Hard Reset */
+	if (IS_ENABLED(CONFIG_USB_PD_HOST_CMD))
+		pd_notify_event(port, PD_STATUS_EVENT_HARD_RESET);
+
+	/*
+	 * Protocol Layer message transmission transitions to
+	 * PRL_Tx_Wait_For_Message_Request state.
+	 */
+	set_state_prl_tx(port, PRL_TX_WAIT_FOR_MESSAGE_REQUEST);
+
 	return;
 }
 
@@ -1227,8 +1386,11 @@ static void prl_hr_reset_layer_run(const int port)
 	 * Hard Reset was initiated by Policy Engine
 	 */
 	if (PRL_HR_CHK_FLAG(port, PRL_FLAGS_PE_HARD_RESET)) {
-		/* Request PHY to perform a Hard Reset */
-		prl_send_ctrl_msg(port, TCPC_TX_HARD_RESET, 0);
+		/*
+		 * Request PHY to perform a Hard Reset. Note
+		 * PRL_HR_Request_Reset state is embedded here.
+		 */
+		prl_hr_send_msg_to_phy(port);
 		set_state_prl_hr(port, PRL_HR_WAIT_FOR_PHY_HARD_RESET_COMPLETE);
 	}
 	/*
@@ -1250,8 +1412,7 @@ static void prl_hr_wait_for_phy_hard_reset_complete_entry(const int port)
 	print_current_prl_hr_state(port);
 
 	/* Start HardResetCompleteTimer */
-	prl_hr[port].hard_reset_complete_timer =
-			get_time().val + PD_T_PS_HARD_RESET;
+	pd_timer_enable(port, PR_TIMER_HARD_RESET_COMPLETE, PD_T_PS_HARD_RESET);
 }
 
 static void prl_hr_wait_for_phy_hard_reset_complete_run(const int port)
@@ -1261,7 +1422,7 @@ static void prl_hr_wait_for_phy_hard_reset_complete_run(const int port)
 	 * or timeout
 	 */
 	if (PDMSG_CHK_FLAG(port, PRL_FLAGS_TX_COMPLETE) ||
-	    (get_time().val > prl_hr[port].hard_reset_complete_timer)) {
+	    pd_timer_is_expired(port, PR_TIMER_HARD_RESET_COMPLETE)) {
 		/* PRL_HR_PHY_Hard_Reset_Requested */
 
 		/* Inform Policy Engine Hard Reset was sent */
@@ -1272,6 +1433,11 @@ static void prl_hr_wait_for_phy_hard_reset_complete_run(const int port)
 	}
 }
 
+static void prl_hr_wait_for_phy_hard_reset_complete_exit(int port)
+{
+	pd_timer_disable(port, PR_TIMER_HARD_RESET_COMPLETE);
+}
+
 /*
  * PrlHrWaitForPeHardResetComplete
  */
@@ -1304,11 +1470,11 @@ static void copy_chunk_to_ext(int port)
 {
 	/* Calculate number of bytes */
 	pdmsg[port].num_bytes_received =
-				(PD_HEADER_CNT(rx_emsg[port].header) * 4);
+		(PD_HEADER_CNT(rx_emsg[port].header) * 4);
 
 	/* Copy chunk into extended message */
 	memcpy((uint8_t *)rx_emsg[port].buf, (uint8_t *)pdmsg[port].rx_chk_buf,
-		pdmsg[port].num_bytes_received);
+	       pdmsg[port].num_bytes_received);
 
 	/* Set extended message length */
 	rx_emsg[port].len = pdmsg[port].num_bytes_received;
@@ -1340,10 +1506,10 @@ static void rch_wait_for_message_from_protocol_layer_run(const int port)
 		 * Are we communicating with a PD3.0 device and is
 		 * this an extended message?
 		 */
-		if (pdmsg_xmit_type_is_rev30(port)
-		    && PD_HEADER_EXT(rx_emsg[port].header)) {
+		if (pdmsg_xmit_type_is_rev30(port) &&
+		    PD_HEADER_EXT(rx_emsg[port].header)) {
 			uint16_t exhdr =
-					GET_EXT_HEADER(*pdmsg[port].rx_chk_buf);
+				GET_EXT_HEADER(*pdmsg[port].rx_chk_buf);
 			uint8_t chunked = PD_EXT_HEADER_CHUNKED(exhdr);
 
 			/*
@@ -1351,7 +1517,7 @@ static void rch_wait_for_message_from_protocol_layer_run(const int port)
 			 * (Chunking = 1 & Chunked = 1)
 			 */
 			if ((RCH_CHK_FLAG(port, PRL_FLAGS_CHUNKING)) &&
-								chunked) {
+			    chunked) {
 				/*
 				 * RCH_Processing_Extended_Message first chunk
 				 * entry processing embedded here
@@ -1373,7 +1539,7 @@ static void rch_wait_for_message_from_protocol_layer_run(const int port)
 			 * (Chunking = 0 & Chunked = 0))
 			 */
 			else if (!RCH_CHK_FLAG(port, PRL_FLAGS_CHUNKING) &&
-								!chunked) {
+				 !chunked) {
 				/* Copy chunk to extended buffer */
 				copy_chunk_to_ext(port);
 				set_state_rch(port, RCH_PASS_UP_MESSAGE);
@@ -1382,6 +1548,7 @@ static void rch_wait_for_message_from_protocol_layer_run(const int port)
 			 * Chunked != Chunking
 			 */
 			else {
+				rch[port].error = ERR_RCH_CHUNKED;
 				set_state_rch(port, RCH_REPORT_ERROR);
 			}
 		}
@@ -1398,6 +1565,7 @@ static void rch_wait_for_message_from_protocol_layer_run(const int port)
 		 * revision lower than PD3.0
 		 */
 		else {
+			rch[port].error = ERR_RCH_CHUNKED;
 			set_state_rch(port, RCH_REPORT_ERROR);
 		}
 	}
@@ -1449,8 +1617,9 @@ static void rch_processing_extended_message_run(const int port)
 			byte_num = PD_MAX_EXTENDED_MSG_CHUNK_LEN;
 
 		/* Make sure extended message buffer does not overflow */
-		if (pdmsg[port].num_bytes_received +
-					byte_num > EXTENDED_BUFFER_SIZE) {
+		if (pdmsg[port].num_bytes_received + byte_num >
+		    EXTENDED_BUFFER_SIZE) {
+			rch[port].error = ERR_RCH_CHUNKED;
 			set_state_rch(port, RCH_REPORT_ERROR);
 			return;
 		}
@@ -1458,9 +1627,8 @@ static void rch_processing_extended_message_run(const int port)
 		/* Append data */
 		/* Add 2 to chk_buf to skip over extended message header */
 		memcpy(((uint8_t *)rx_emsg[port].buf +
-				pdmsg[port].num_bytes_received),
-				(uint8_t *)pdmsg[port].rx_chk_buf + 2,
-				byte_num);
+			pdmsg[port].num_bytes_received),
+		       (uint8_t *)pdmsg[port].rx_chk_buf + 2, byte_num);
 		/* increment chunk number expected */
 		pdmsg[port].chunk_number_expected++;
 		/* adjust num bytes received */
@@ -1469,7 +1637,7 @@ static void rch_processing_extended_message_run(const int port)
 		/* Was that the last chunk? */
 		if (pdmsg[port].num_bytes_received >= data_size) {
 			rx_emsg[port].len = pdmsg[port].num_bytes_received;
-			 /* Pass Message to Policy Engine */
+			/* Pass Message to Policy Engine */
 			set_state_rch(port, RCH_PASS_UP_MESSAGE);
 		}
 		/*
@@ -1481,8 +1649,10 @@ static void rch_processing_extended_message_run(const int port)
 	/*
 	 * Unexpected Chunk Number
 	 */
-	else
+	else {
+		rch[port].error = ERR_RCH_CHUNKED;
 		set_state_rch(port, RCH_REPORT_ERROR);
+	}
 }
 
 /*
@@ -1496,16 +1666,17 @@ static void rch_requesting_chunk_entry(const int port)
 	 * Send Chunk Request to Protocol Layer
 	 * with chunk number = Chunk_Number_Expected
 	 */
-	pdmsg[port].tx_chk_buf[0] = PD_EXT_HEADER(
-				pdmsg[port].chunk_number_expected,
-				1, /* Request Chunk */
-				0 /* Data Size */
-				);
+	pdmsg[port].tx_chk_buf[0] =
+		PD_EXT_HEADER(pdmsg[port].chunk_number_expected, 1, /* Request
+								       Chunk */
+			      0 /* Data Size */
+		);
 
 	pdmsg[port].data_objs = 1;
 	pdmsg[port].ext = 1;
+	pdmsg[port].xmit_type = prl_rx[port].sop;
 	PRL_TX_SET_FLAG(port, PRL_FLAGS_MSG_XMIT);
-	task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_TX, 0);
+	task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_TX);
 }
 
 static void rch_requesting_chunk_run(const int port)
@@ -1516,18 +1687,20 @@ static void rch_requesting_chunk_run(const int port)
 	if (PDMSG_CHK_FLAG(port, PRL_FLAGS_TX_COMPLETE)) {
 		PDMSG_CLR_FLAG(port, PRL_FLAGS_TX_COMPLETE);
 		set_state_rch(port, RCH_WAITING_CHUNK);
-	}
-	/*
-	 * Transmission Error from Protocol Layer or
-	 * Message Received From Protocol Layer
-	 */
-	else if (RCH_CHK_FLAG(port, PRL_FLAGS_MSG_RECEIVED) ||
-			PDMSG_CHK_FLAG(port, PRL_FLAGS_TX_ERROR)) {
+	} else if (PDMSG_CHK_FLAG(port, PRL_FLAGS_TX_ERROR)) {
+		/* Transmission Error from Protocol Layer detetected */
+		rch[port].error = ERR_RCH_CHUNKED;
+		set_state_rch(port, RCH_REPORT_ERROR);
+	} else if (RCH_CHK_FLAG(port, PRL_FLAGS_MSG_RECEIVED)) {
 		/*
-		 * Leave PRL_FLAGS_MSG_RECEIVED flag set. It'll be
-		 * cleared in rch_report_error state
+		 * It is possible to have both message received and the chunk
+		 * request transmit complete before a full PRL SM run. But, the
+		 * PRL_RX state machine runs prior to RCH, but before PRL_TX, so
+		 * PRL_FLAGS_MSG_RECEIVED can be set without
+		 * PRL_FLAGS_TX_COMPLETE set at this point (though it will be
+		 * set as soon as PRL_TX is executed next.
 		 */
-		set_state_rch(port, RCH_REPORT_ERROR);
+		set_state_rch(port, RCH_WAITING_CHUNK);
 	}
 }
 
@@ -1541,13 +1714,23 @@ static void rch_waiting_chunk_entry(const int port)
 	/*
 	 * Start ChunkSenderResponseTimer
 	 */
-	rch[port].chunk_sender_response_timer =
-		get_time().val + PD_T_CHUNK_SENDER_RESPONSE;
+	pd_timer_enable(port, PR_TIMER_CHUNK_SENDER_RESPONSE,
+			PD_T_CHUNK_SENDER_RESPONSE);
 }
 
 static void rch_waiting_chunk_run(const int port)
 {
 	if (RCH_CHK_FLAG(port, PRL_FLAGS_MSG_RECEIVED)) {
+		/*
+		 * Because of the 5 msec tick time, it is possible to have both
+		 * msg_received and tx_complete flags set for a given PRL sm
+		 * run. Since prl_rx runs prior to the tx state machines, clear
+		 * the tx_complete flag as the next chunk has already been
+		 * received.
+		 */
+		if (PDMSG_CHK_FLAG(port, PRL_FLAGS_TX_COMPLETE))
+			PDMSG_CLR_FLAG(port, PRL_FLAGS_TX_COMPLETE);
+
 		/*
 		 * Leave PRL_FLAGS_MSG_RECEIVED flag set just in case an error
 		 * is detected. If an error is detected, PRL_FLAGS_MSG_RECEIVED
@@ -1562,6 +1745,7 @@ static void rch_waiting_chunk_run(const int port)
 			 */
 			if (PD_EXT_HEADER_REQ_CHUNK(exhdr) ||
 			    !PD_EXT_HEADER_CHUNKED(exhdr)) {
+				rch[port].error = ERR_RCH_CHUNKED;
 				set_state_rch(port, RCH_REPORT_ERROR);
 			}
 			/*
@@ -1569,7 +1753,7 @@ static void rch_waiting_chunk_run(const int port)
 			 */
 			else {
 				/*
-				 * No error wad detected, so clear
+				 * No error was detected, so clear
 				 * PRL_FLAGS_MSG_RECEIVED flag.
 				 */
 				RCH_CLR_FLAG(port, PRL_FLAGS_MSG_RECEIVED);
@@ -1581,11 +1765,17 @@ static void rch_waiting_chunk_run(const int port)
 	/*
 	 * ChunkSenderResponseTimer Timeout
 	 */
-	else if (get_time().val > rch[port].chunk_sender_response_timer) {
+	else if (pd_timer_is_expired(port, PR_TIMER_CHUNK_SENDER_RESPONSE)) {
+		rch[port].error = ERR_RCH_CHUNK_WAIT_TIMEOUT;
 		set_state_rch(port, RCH_REPORT_ERROR);
 	}
 }
 
+static void rch_waiting_chunk_exit(int port)
+{
+	pd_timer_disable(port, PR_TIMER_CHUNK_SENDER_RESPONSE);
+}
+
 /*
  * RchReportError
  */
@@ -1607,8 +1797,7 @@ static void rch_report_error_entry(const int port)
 		/* Report error */
 		pe_report_error(port, ERR_RCH_MSG_REC, prl_rx[port].sop);
 	} else {
-		/* Report error */
-		pe_report_error(port, ERR_RCH_CHUNKED, prl_rx[port].sop);
+		pe_report_error(port, rch[port].error, prl_rx[port].sop);
 	}
 }
 
@@ -1632,7 +1821,7 @@ static void tch_wait_for_message_request_from_pe_entry(const int port)
 	PDMSG_CLR_FLAG(port, PRL_FLAGS_ABORT);
 
 	/* All Messages are chunked */
-	tch[port].flags = PRL_FLAGS_CHUNKING;
+	TCH_SET_FLAG(port, PRL_FLAGS_CHUNKING);
 }
 
 static void tch_wait_for_message_request_from_pe_run(const int port)
@@ -1652,16 +1841,15 @@ static void tch_wait_for_message_request_from_pe_run(const int port)
 		 * Discard the Message
 		 */
 		if (rch_get_state(port) !=
-				RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER) {
+		    RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER) {
 			tch[port].error = ERR_TCH_XMIT;
 			set_state_tch(port, TCH_REPORT_ERROR);
 		} else {
 			/*
 			 * Extended Message Request & Chunking
 			 */
-			if (pdmsg_xmit_type_is_rev30(port)
-			    && pdmsg[port].ext
-			    && TCH_CHK_FLAG(port, PRL_FLAGS_CHUNKING)) {
+			if (pdmsg_xmit_type_is_rev30(port) && pdmsg[port].ext &&
+			    TCH_CHK_FLAG(port, PRL_FLAGS_CHUNKING)) {
 				/*
 				 * NOTE: TCH_Prepare_To_Send_Chunked_Message
 				 * embedded here.
@@ -1680,7 +1868,8 @@ static void tch_wait_for_message_request_from_pe_run(const int port)
 
 				/* Pass Message to Protocol Layer */
 				PRL_TX_SET_FLAG(port, PRL_FLAGS_MSG_XMIT);
-				set_state_tch(port,
+				set_state_tch(
+					port,
 					TCH_WAIT_FOR_TRANSMISSION_COMPLETE);
 			}
 		}
@@ -1715,13 +1904,17 @@ static void tch_wait_for_transmission_complete_run(const int port)
 		return;
 	}
 	/*
-	 * Any message received and not in state TCH_Wait_Chunk_Request
-	 * MUST be checked after transmission status due to our TCPC
-	 * architecture, and should not be checked if prl_tx is still waiting on
-	 * the TCPC.
+	 * A message was received while TCH is waiting for the phy to complete
+	 * sending a tx message.
+	 *
+	 * Because of our prl_sm architecture and I2C access delays for TCPCs,
+	 * it's possible to have a message received and the prl_tx state not be
+	 * in its default waiting state. To avoid a false protocol error, only
+	 * jump to TCH_MESSAGE_RECEIVED if the phy layer has not indicated that
+	 * the tx message was sent successfully.
 	 */
 	if (TCH_CHK_FLAG(port, PRL_FLAGS_MSG_RECEIVED) &&
-	     prl_tx_get_state(port) !=  PRL_TX_WAIT_FOR_PHY_RESPONSE) {
+	    prl_tx[port].xmit_status != TCPC_TX_COMPLETE_SUCCESS) {
 		TCH_CLR_FLAG(port, PRL_FLAGS_MSG_RECEIVED);
 		set_state_tch(port, TCH_MESSAGE_RECEIVED);
 		return;
@@ -1758,8 +1951,9 @@ static void tch_construct_chunked_message_entry(const int port)
 		num = PD_MAX_EXTENDED_MSG_CHUNK_LEN;
 
 	/* Set the chunks extended header */
-	*ext_hdr = PD_EXT_HEADER(pdmsg[port].chunk_number_to_send,
-				 0, /* Chunk Request */
+	*ext_hdr = PD_EXT_HEADER(pdmsg[port].chunk_number_to_send, 0, /* Chunk
+									 Request
+								       */
 				 tx_emsg[port].len);
 
 	/* Copy the message chunk into chk_buf */
@@ -1837,8 +2031,8 @@ static void tch_wait_chunk_request_entry(const int port)
 	/* Increment Chunk Number to Send */
 	pdmsg[port].chunk_number_to_send++;
 	/* Start Chunk Sender Request Timer */
-	tch[port].chunk_sender_request_timer =
-		get_time().val + PD_T_CHUNK_SENDER_REQUEST;
+	pd_timer_enable(port, PR_TIMER_CHUNK_SENDER_REQUEST,
+			PD_T_CHUNK_SENDER_REQUEST);
 }
 
 static void tch_wait_chunk_request_run(const int port)
@@ -1857,7 +2051,8 @@ static void tch_wait_chunk_request_run(const int port)
 				 */
 				if (PD_EXT_HEADER_CHUNK_NUM(exthdr) ==
 				    pdmsg[port].chunk_number_to_send) {
-					set_state_tch(port,
+					set_state_tch(
+						port,
 						TCH_CONSTRUCT_CHUNKED_MESSAGE);
 				}
 				/*
@@ -1880,10 +2075,13 @@ static void tch_wait_chunk_request_run(const int port)
 	/*
 	 * ChunkSenderRequestTimer timeout
 	 */
-	else if (get_time().val >=
-			tch[port].chunk_sender_request_timer) {
+	else if (pd_timer_is_expired(port, PR_TIMER_CHUNK_SENDER_REQUEST))
 		set_state_tch(port, TCH_MESSAGE_SENT);
-	}
+}
+
+static void tch_wait_chunk_request_exit(int port)
+{
+	pd_timer_disable(port, PR_TIMER_CHUNK_SENDER_REQUEST);
 }
 
 /*
@@ -1929,8 +2127,6 @@ static void tch_message_sent_entry(const int port)
 		return;
 	}
 
-
-
 	set_state_tch(port, TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE);
 }
 
@@ -1954,7 +2150,6 @@ static void tch_report_error_entry(const int port)
 		return;
 	}
 
-
 	set_state_tch(port, TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE);
 }
 #endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
@@ -1994,7 +2189,7 @@ static void prl_rx_wait_for_phy_message(const int port, int evt)
 
 	/* dump received packet content (only dump ping at debug level MAX) */
 	if ((prl_debug_level >= DEBUG_LEVEL_2 && type != PD_CTRL_PING) ||
-		prl_debug_level >= DEBUG_LEVEL_3) {
+	    prl_debug_level >= DEBUG_LEVEL_3) {
 		int p;
 
 		ccprintf("C%d: RECV %04x/%d ", port, header, cnt);
@@ -2007,31 +2202,44 @@ static void prl_rx_wait_for_phy_message(const int port, int evt)
 	 * Ignore messages sent to the cable from our
 	 * port partner if we aren't Vconn powered device.
 	 */
-	if (!IS_ENABLED(CONFIG_USB_CTVPD) &&
-	    !IS_ENABLED(CONFIG_USB_VPD) &&
-	    PD_HEADER_GET_SOP(header) != PD_MSG_SOP &&
+	if (!IS_ENABLED(CONFIG_USB_CTVPD) && !IS_ENABLED(CONFIG_USB_VPD) &&
+	    PD_HEADER_GET_SOP(header) != TCPCI_MSG_SOP &&
 	    PD_HEADER_PROLE(header) == PD_PLUG_FROM_DFP_UFP)
 		return;
 
+	/*
+	 * From 6.2.1.1.6 Port Data Role in USB PD Rev 3.1, Ver 1.3
+	 * "If a USB Type-C Port receives a Message with the Port Data Role
+	 * field set to the same Data Role as its current Data Role, except
+	 * for the GoodCRC Message, USB Type-C Error Recovery actions as
+	 * defined in [USB Type-C 2.0] Shall be performed."
+	 *
+	 * The spec lists no required state for this check, so centralize it by
+	 * processing this requirement in the PRL RX. Because the TCPM does not
+	 * swap data roles instantaneously, disable this check during the
+	 * transition.
+	 */
+	if (!RCH_CHK_FLAG(port, PRL_FLAGS_IGNORE_DATA_ROLE) &&
+	    PD_HEADER_GET_SOP(header) == TCPCI_MSG_SOP &&
+	    PD_HEADER_DROLE(header) == pd_get_data_role(port)) {
+		CPRINTS("C%d Error: Data role mismatch (0x%08x)", port, header);
+		tc_start_error_recovery(port);
+		return;
+	}
+
 	/* Handle incoming soft reset as special case */
 	if (cnt == 0 && type == PD_CTRL_SOFT_RESET) {
-		int i;
-
-		for (i = 0; i < NUM_SOP_STAR_TYPES; i++) {
-			/* Clear MessageIdCounter */
-			prl_tx[port].msg_id_counter[i] = 0;
-			/* Clear stored MessageID value */
-			prl_rx[port].msg_id[i] = -1;
-		}
+		/* Clear MessageIdCounter and stored MessageID value. */
+		prl_reset_msg_ids(port, prl_rx[port].sop);
 
 		/* Soft Reset occurred */
 		set_state_prl_tx(port, PRL_TX_PHY_LAYER_RESET);
 
 		if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES)) {
 			set_state_rch(port,
-				RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER);
+				      RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER);
 			set_state_tch(port,
-				TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE);
+				      TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE);
 		}
 
 		/*
@@ -2063,7 +2271,7 @@ static void prl_rx_wait_for_phy_message(const int port, int evt)
 		 * complete at the same time as a response so only do this if a
 		 * message is pending.
 		 */
-		if (prl_tx_get_state(port) != PRL_TX_WAIT_FOR_PHY_RESPONSE ||
+		if (prl_tx[port].xmit_status != TCPC_TX_COMPLETE_SUCCESS ||
 		    PRL_TX_CHK_FLAG(port, PRL_FLAGS_MSG_XMIT))
 			set_state_prl_tx(port, PRL_TX_DISCARD_MESSAGE);
 	}
@@ -2091,7 +2299,7 @@ static void prl_rx_wait_for_phy_message(const int port, int evt)
 		 * tch_wait_for_message_request_from_pe has been run
 		 */
 		else if (tch_get_state(port) !=
-				TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE ||
+				 TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE ||
 			 TCH_CHK_FLAG(port, PRL_FLAGS_MSG_XMIT)) {
 			/* NOTE: RTR_TX_CHUNKS State embedded here. */
 			/*
@@ -2123,7 +2331,7 @@ static void prl_rx_wait_for_phy_message(const int port, int evt)
 }
 
 /* All necessary Protocol Transmit States (Section 6.11.2.2) */
-static const struct usb_state prl_tx_states[] = {
+static __const_data const struct usb_state prl_tx_states[] = {
 	[PRL_TX_PHY_LAYER_RESET] = {
 		.entry  = prl_tx_phy_layer_reset_entry,
 	},
@@ -2153,6 +2361,7 @@ static const struct usb_state prl_tx_states[] = {
 	[PRL_TX_SRC_PENDING] = {
 		.entry  = prl_tx_src_pending_entry,
 		.run    = prl_tx_src_pending_run,
+		.exit	= prl_tx_src_pending_exit,
 	},
 	[PRL_TX_SNK_PENDING] = {
 		.entry  = prl_tx_snk_pending_entry,
@@ -2164,7 +2373,7 @@ static const struct usb_state prl_tx_states[] = {
 };
 
 /* All necessary Protocol Hard Reset States (Section 6.11.2.4) */
-static const struct usb_state prl_hr_states[] = {
+static __const_data const struct usb_state prl_hr_states[] = {
 	[PRL_HR_WAIT_FOR_REQUEST] = {
 		.entry  = prl_hr_wait_for_request_entry,
 		.run    = prl_hr_wait_for_request_run,
@@ -2176,6 +2385,7 @@ static const struct usb_state prl_hr_states[] = {
 	[PRL_HR_WAIT_FOR_PHY_HARD_RESET_COMPLETE] = {
 		.entry  = prl_hr_wait_for_phy_hard_reset_complete_entry,
 		.run    = prl_hr_wait_for_phy_hard_reset_complete_run,
+		.exit	= prl_hr_wait_for_phy_hard_reset_complete_exit,
 	},
 	[PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE] = {
 		.entry  = prl_hr_wait_for_pe_hard_reset_complete_entry,
@@ -2184,9 +2394,9 @@ static const struct usb_state prl_hr_states[] = {
 	},
 };
 
-#ifdef CONFIG_USB_PD_EXTENDED_MESSAGES
 /* All necessary Chunked Rx states (Section 6.11.2.1.2) */
-static const struct usb_state rch_states[] = {
+__maybe_unused static const struct usb_state rch_states[] = {
+#ifdef CONFIG_USB_PD_EXTENDED_MESSAGES
 	[RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER] = {
 		.entry  = rch_wait_for_message_from_protocol_layer_entry,
 		.run    = rch_wait_for_message_from_protocol_layer_run,
@@ -2205,15 +2415,18 @@ static const struct usb_state rch_states[] = {
 	[RCH_WAITING_CHUNK] = {
 		.entry  = rch_waiting_chunk_entry,
 		.run    = rch_waiting_chunk_run,
+		.exit	= rch_waiting_chunk_exit,
 	},
 	[RCH_REPORT_ERROR] = {
 		.entry  = rch_report_error_entry,
 		.run    = rch_report_error_run,
 	},
+#endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
 };
 
 /* All necessary Chunked Tx states (Section 6.11.2.1.3) */
-static const struct usb_state tch_states[] = {
+__maybe_unused static const struct usb_state tch_states[] = {
+#ifdef CONFIG_USB_PD_EXTENDED_MESSAGES
 	[TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE] = {
 		.entry  = tch_wait_for_message_request_from_pe_entry,
 		.run    = tch_wait_for_message_request_from_pe_run,
@@ -2233,6 +2446,7 @@ static const struct usb_state tch_states[] = {
 	[TCH_WAIT_CHUNK_REQUEST] = {
 		.entry  = tch_wait_chunk_request_entry,
 		.run    = tch_wait_chunk_request_run,
+		.exit	= tch_wait_chunk_request_exit,
 	},
 	[TCH_MESSAGE_RECEIVED] = {
 		.entry  = tch_message_received_entry,
@@ -2244,8 +2458,155 @@ static const struct usb_state tch_states[] = {
 	[TCH_REPORT_ERROR] = {
 		.entry  = tch_report_error_entry,
 	},
-};
 #endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
+};
+
+#ifdef CONFIG_USB_PD_PRL_EVENT_LOG
+struct prl_event_log_entry {
+	/*
+	 * Truncating to 32 bits still covers a time range of about an hour and
+	 * saves 4 bytes of RAM per entry, which is significant.
+	 */
+	uint32_t timestamp;
+	uint16_t flags;
+	uint8_t port;
+	enum prl_event_log_state_kind kind;
+	union {
+		enum usb_prl_tx_state tx;
+		enum usb_prl_hr_state hr;
+		enum usb_rch_state rch;
+		enum usb_tch_state tch;
+	};
+};
+BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT <= UINT8_MAX);
+
+static struct prl_event_log_entry
+	prl_event_log_buffer[CONFIG_USB_PD_PRL_EVENT_LOG_CAPACITY];
+static atomic_t prl_event_log_next;
+
+static void prl_event_log_append(enum prl_event_log_state_kind kind, int port)
+{
+	struct prl_event_log_entry entry = {
+		.timestamp = get_time().val,
+		.port = port,
+		.kind = kind,
+	};
+
+	switch (kind) {
+	case PRL_EVENT_LOG_STATE_TX:
+		entry.flags = prl_tx[port].flags;
+		entry.tx = prl_tx_get_state(port);
+		break;
+	case PRL_EVENT_LOG_STATE_HR:
+		entry.flags = prl_hr[port].flags;
+		entry.hr = prl_hr_get_state(port);
+		break;
+	case PRL_EVENT_LOG_STATE_RCH:
+		entry.flags = rch[port].flags;
+		entry.rch = rch_get_state(port);
+		break;
+	case PRL_EVENT_LOG_STATE_TCH:
+		entry.flags = tch[port].flags;
+		entry.tch = tch_get_state(port);
+		break;
+	case PRL_EVENT_LOG_STATE_NONE:
+		/* Should never be written to the log */
+		return;
+	}
+
+	prl_event_log_buffer[atomic_add(&prl_event_log_next, 1) %
+			     ARRAY_SIZE(prl_event_log_buffer)] = entry;
+}
+
+static int command_prllog(int argc, const char **argv)
+{
+	if (argc == 2 && strcmp("clear", argv[1]) == 0) {
+		/* Clear buffer contents */
+		for (int i = 0; i < ARRAY_SIZE(prl_event_log_buffer); i++) {
+			memset(prl_event_log_buffer, 0,
+			       sizeof(prl_event_log_buffer));
+		}
+		return EC_SUCCESS;
+	} else if (argc != 1) {
+		return EC_ERROR_PARAM1;
+	}
+
+	/* Locate the oldest entry in the buffer, to start output there. */
+	unsigned int oldest_index = INT_MAX;
+
+	for (int i = 0; i < ARRAY_SIZE(prl_event_log_buffer); i++) {
+		const struct prl_event_log_entry *entry =
+			&prl_event_log_buffer[i];
+		if (entry->kind == PRL_EVENT_LOG_STATE_NONE) {
+			continue;
+		}
+
+		if (oldest_index == INT_MAX) {
+			oldest_index = i;
+		} else if (entry->timestamp <
+			   prl_event_log_buffer[oldest_index].timestamp) {
+			oldest_index = i;
+			/*
+			 * Timestamps increase monotonically, so any decrease in
+			 * time indicates we rolled over to old entries and any
+			 * after this will always be newer.
+			 */
+			break;
+		}
+	}
+	if (oldest_index == INT_MAX) {
+		/* No valid entries in the buffer. */
+		return EC_SUCCESS;
+	}
+
+	/* Dump buffer contents */
+	for (unsigned int i = 0; i < ARRAY_SIZE(prl_event_log_buffer); i++) {
+		const struct prl_event_log_entry *entry =
+			&prl_event_log_buffer[(oldest_index + i) %
+					      ARRAY_SIZE(prl_event_log_buffer)];
+
+		if (entry->kind == PRL_EVENT_LOG_STATE_NONE) {
+			/*
+			 * oldest_index refers to the oldest non-empty entry, so
+			 * if we find an empty one later we know the buffer is
+			 * empty past that point.
+			 */
+			break;
+		}
+
+		CPRINTF("%" PRIu32 " C%d ", entry->timestamp, entry->port);
+		switch (entry->kind) {
+		case PRL_EVENT_LOG_STATE_TX:
+			CPRINTF("%s ", prl_tx_state_names[entry->tx]);
+			print_flag("PRL_TX", 1, entry->flags);
+			break;
+		case PRL_EVENT_LOG_STATE_HR:
+			CPRINTF("%s ", prl_hr_state_names[entry->hr]);
+			print_flag("PRL_HR", 1, entry->flags);
+			break;
+		case PRL_EVENT_LOG_STATE_RCH:
+			CPRINTF("%s ", rch_state_names[entry->rch]);
+			print_flag("RCH", 1, entry->flags);
+			break;
+		case PRL_EVENT_LOG_STATE_TCH:
+			CPRINTF("%s ", tch_state_names[entry->tch]);
+			print_flag("TCH", 1, entry->flags);
+			break;
+		default:
+			CPRINTF("unrecognized event kind\n");
+			continue;
+		}
+	}
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(prllog, command_prllog, "[clear]",
+			"Dump USB-PD PRL state log");
+#else
+__maybe_unused static void
+prl_event_log_append(enum prl_event_log_state_kind kind, int port)
+{
+}
+#endif
 
 #ifdef TEST_BUILD
 
@@ -2285,4 +2646,3 @@ BUILD_ASSERT(ARRAY_SIZE(tch_states) == ARRAY_SIZE(tch_state_names));
 #endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
 const int test_prl_sm_data_size = ARRAY_SIZE(test_prl_sm_data);
 #endif
-
diff --git a/common/usbc/usb_retimer_fw_update.c b/common/usbc/usb_retimer_fw_update.c
new file mode 100644
index 0000000000..a8cabf00a2
--- /dev/null
+++ b/common/usbc/usb_retimer_fw_update.c
@@ -0,0 +1,401 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "builtin/assert.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "hooks.h"
+#include "timer.h"
+#include "usb_common.h"
+#include "usb_mux.h"
+#include "usb_tc_sm.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#ifdef CONFIG_COMMON_RUNTIME
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#else
+#define CPRINTS(format, args...)
+#define CPRINTF(format, args...)
+#endif
+
+/*
+ * Update retimer firmware of no device attached (NDA) ports
+ *
+ * https://docs.kernel.org/admin-guide/thunderbolt.html#
+ * upgrading-on-board-retimer-nvm-when-there-is-no-cable-connected
+ *
+ * On EC side:
+ * Retimer firmware update is initiated by AP.
+ * The operations requested by AP are:
+ * 0 - USB_RETIMER_FW_UPDATE_QUERY_PORT
+ * 1 - USB_RETIMER_FW_UPDATE_SUSPEND_PD
+ * 2 - USB_RETIMER_FW_UPDATE_RESUME_PD
+ * 3 - USB_RETIMER_FW_UPDATE_GET_MUX
+ * 4 - USB_RETIMER_FW_UPDATE_SET_USB
+ * 5 - USB_RETIMER_FW_UPDATE_SET_SAFE
+ * 6 - USB_RETIMER_FW_UPDATE_SET_TBT
+ * 7 - USB_RETIMER_FW_UPDATE_DISCONNECT
+ *
+ * Operation 0 is processed immediately.
+ * Operations 1 to 7 are deferred and processed inside tc_run().
+ * Operations 1/2/3 can be processed any time; while 4/5/6/7 have
+ * to be processed when PD task is suspended.
+ * Two TC flags are created for this situation.
+ * If Op 1/2/3 is received, TC_FLAGS_USB_RETIMER_FW_UPDATE_RUN
+ * is set, PD task will be waken up and process it.
+ * If 4/5/6/7 is received, TC_FLAGS_USB_RETIMER_FW_UPDATE_LTD_RUN is
+ * set, PD task should be in suspended mode and process it.
+ *
+ * On host side:
+ * 1. Put NDA ports into offline mode.
+ *    This forces retimer to power on, and requests EC to suspend
+ *    PD port, set USB mux to USB, Safe then TBT.
+ * 2. Scan for retimers
+ * 3. Update retimer NVM firmware.
+ * 4. Authenticate.
+ * 5. Wait 5 or more seconds for retimer to come back.
+ * 6. Put NDA ports into online mode -- the functional state.
+ *    This requestes EC to disconnect(set USB mux to 0), resume PD port.
+ *
+ * Error recovery:
+ * As mentioned above, to put port online, host sends two requests to EC
+ * 1. Disconnect USB MUX: USB_RETIMER_FW_UPDATE_DISCONNECT
+ * if step 1 is successful, then
+ * 2. Resume PD port: USB_RETIMER_FW_UPDATE_RESUME_PD
+ *
+ * If step 1 fails, host will not send step 2. This means no
+ * resume request from host. PD port stays in suspended state.
+ * EC needs an error recovery to resume PD port by itself.
+ *
+ * Below is how error recovery works:
+ * PD port state is set to RETIMER_ONLINE_REQUESTED when receives
+ * "Disconnect USB MUX"; a deferred call is set up too. When EC resumes
+ * port upon host's request, port state will be set to RETIMER_ONLINE;
+ * or port state stays RETIMER_ONLINE_REQUESTED if host doesn't request.
+ * By the time the deferrred call is fired, it will check if any port is
+ * still in RETIMER_ONLINE_REQUESTED state. If true, EC will put the
+ * port online by itself. That is, retry disconnect and unconditionally
+ * resume the port.
+ */
+
+#define SUSPEND 1
+#define RESUME 0
+
+enum retimer_port_state {
+	RETIMER_ONLINE,
+	RETIMER_OFFLINE,
+	RETIMER_ONLINE_REQUESTED
+};
+
+/*
+ * Two seconds buffer is added on top of required 5 seconds;
+ * to cover the time to disconnect and resume.
+ */
+#define RETIMTER_ONLINE_DELAY (7 * SECOND)
+
+/* Track current port AP requested to update retimer firmware */
+static int cur_port;
+static int last_op; /* Operation received from AP via ACPI_WRITE */
+/* Operation result returned to ACPI_READ */
+static int last_result;
+/* Track port state: SUSPEND or RESUME */
+static enum retimer_port_state port_state[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+int usb_retimer_fw_update_get_result(void)
+{
+	int result = 0;
+
+	switch (last_op) {
+	case USB_RETIMER_FW_UPDATE_SUSPEND_PD:
+		if (last_result == USB_RETIMER_FW_UPDATE_ERR) {
+			result = last_result;
+			break;
+		}
+		__fallthrough;
+	case USB_RETIMER_FW_UPDATE_RESUME_PD:
+		result = pd_is_port_enabled(cur_port);
+		break;
+	case USB_RETIMER_FW_UPDATE_QUERY_PORT:
+		result = usb_mux_retimer_fw_update_port_info();
+		break;
+	case USB_RETIMER_FW_UPDATE_GET_MUX:
+	case USB_RETIMER_FW_UPDATE_SET_USB:
+	case USB_RETIMER_FW_UPDATE_SET_SAFE:
+	case USB_RETIMER_FW_UPDATE_SET_TBT:
+	case USB_RETIMER_FW_UPDATE_DISCONNECT:
+		result = last_result;
+		break;
+	default:
+		break;
+	}
+
+	return result;
+}
+
+static void retimer_fw_update_set_port_state(int port,
+					     enum retimer_port_state state)
+{
+	port_state[port] = state;
+}
+
+static enum retimer_port_state retimer_fw_update_get_port_state(int port)
+{
+	return port_state[port];
+}
+
+/**
+ * @brief Suspend or resume PD task and update the state of the port.
+ *
+ * @param port PD port
+ * @param suspend
+ * SUSPEND: suspend PD task; set state to RETIMER_OFFLINE
+ * RESUME: resume PD task; set state to RETIMER_ONLINE.
+ *
+ */
+static void retimer_fw_update_port_handler(int port, bool suspend)
+{
+	pd_set_suspend(port, suspend);
+	retimer_fw_update_set_port_state(
+		port, suspend == SUSPEND ? RETIMER_OFFLINE : RETIMER_ONLINE);
+}
+
+static void deferred_pd_suspend(void)
+{
+	retimer_fw_update_port_handler(cur_port, SUSPEND);
+}
+DECLARE_DEFERRED(deferred_pd_suspend);
+
+static inline mux_state_t retimer_fw_update_usb_mux_get(int port)
+{
+	return usb_mux_get(port) & USB_RETIMER_FW_UPDATE_MUX_MASK;
+}
+
+/*
+ * Host will wait maximum 300ms for result; otherwise it's error.
+ * so the polling takes 300ms too.
+ */
+#define POLLING_CYCLE 15
+#define POLLING_TIME_MS 20
+
+static bool query_usb_mux_set_completed_timeout(int port)
+{
+	int i;
+
+	for (i = 0; i < POLLING_CYCLE; i++) {
+		if (!usb_mux_set_completed(port))
+			msleep(POLLING_TIME_MS);
+		else
+			return false;
+	}
+
+	return true;
+}
+
+static void retry_online(int port)
+{
+	usb_mux_set(port, USB_PD_MUX_NONE, USB_SWITCH_DISCONNECT,
+		    pd_get_polarity(port));
+	/* Wait maximum 300 ms for USB mux to be set */
+	query_usb_mux_set_completed_timeout(port);
+	/* Resume the port unconditionally */
+	retimer_fw_update_port_handler(port, RESUME);
+}
+
+/*
+ * After NVM update, if AP skips step 5, not wait 5+ seconds for retimer
+ * to come back; then do step 6 immediately, requesting EC to put
+ * retimer online. Step 6 will fail; port is still offline afterwards.
+ *
+ * This deferred function monitors if any port has this problem and retry
+ * online one more time.
+ */
+static void retimer_check_online(void)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		if (retimer_fw_update_get_port_state(i) ==
+		    RETIMER_ONLINE_REQUESTED) {
+			/*
+			 * Now the time has passed RETIMTER_ONLINE_DELAY;
+			 * retry online.
+			 * The port is suspended; if the port is not
+			 * suspended, DISCONNECT request won't go through,
+			 * we couldn't be here.
+			 */
+			retry_online(i);
+			/* PD port is resumed */
+		}
+	}
+}
+DECLARE_DEFERRED(retimer_check_online);
+
+/* Allow mux results to be filled in during HOOKS if needed */
+static void last_result_mux_get(void);
+DECLARE_DEFERRED(last_result_mux_get);
+
+static void last_result_mux_get(void)
+{
+	if (query_usb_mux_set_completed_timeout(cur_port)) {
+		last_result = USB_RETIMER_FW_UPDATE_ERR;
+		return;
+	}
+
+	last_result = retimer_fw_update_usb_mux_get(cur_port);
+}
+
+void usb_retimer_fw_update_process_op_cb(int port)
+{
+	bool result_mux_get = false;
+
+	if (port != cur_port) {
+		CPRINTS("Unexpected FW op: port %d, cur %d", port, cur_port);
+		return;
+	}
+
+	switch (last_op) {
+	case USB_RETIMER_FW_UPDATE_SUSPEND_PD:
+		last_result = 0;
+		/*
+		 * Do not perform retimer firmware update process
+		 * if battery is not present, or battery level is low.
+		 */
+		if (!pd_firmware_upgrade_check_power_readiness(port)) {
+			last_result = USB_RETIMER_FW_UPDATE_ERR;
+			break;
+		}
+
+		/*
+		 * If the port has entered low power mode, the PD task
+		 * is paused and will not complete processing of
+		 * pd_set_suspend(). Move pd_set_suspend() into a deferred
+		 * call so that it runs from the HOOKS task and can generate
+		 * a wake event to the PD task and enter suspended mode.
+		 */
+		hook_call_deferred(&deferred_pd_suspend_data, 0);
+		break;
+	case USB_RETIMER_FW_UPDATE_RESUME_PD:
+		retimer_fw_update_port_handler(port, RESUME);
+		break;
+	case USB_RETIMER_FW_UPDATE_GET_MUX:
+		result_mux_get = true;
+		break;
+	case USB_RETIMER_FW_UPDATE_SET_USB:
+		usb_mux_set(port, USB_PD_MUX_USB_ENABLED, USB_SWITCH_CONNECT,
+			    pd_get_polarity(port));
+		result_mux_get = true;
+		break;
+	case USB_RETIMER_FW_UPDATE_SET_SAFE:
+		usb_mux_set_safe_mode(port);
+		result_mux_get = true;
+		break;
+	case USB_RETIMER_FW_UPDATE_SET_TBT:
+		usb_mux_set(port, USB_PD_MUX_TBT_COMPAT_ENABLED,
+			    USB_SWITCH_CONNECT, pd_get_polarity(port));
+		result_mux_get = true;
+		break;
+	case USB_RETIMER_FW_UPDATE_DISCONNECT:
+		usb_mux_set(port, USB_PD_MUX_NONE, USB_SWITCH_DISCONNECT,
+			    pd_get_polarity(port));
+		result_mux_get = true;
+		/*
+		 * Host decides to put retimer online; now disconnects USB MUX
+		 * and sets port state to "RETIMER_ONLINE_REQUESTED".
+		 */
+		retimer_fw_update_set_port_state(port,
+						 RETIMER_ONLINE_REQUESTED);
+		hook_call_deferred(&retimer_check_online_data,
+				   RETIMTER_ONLINE_DELAY);
+		break;
+	default:
+		break;
+	}
+
+	/*
+	 * Fill in our mux result if available, or set up a deferred retrieval
+	 * if the set is still pending.
+	 */
+	if (result_mux_get)
+		last_result_mux_get();
+}
+
+void usb_retimer_fw_update_process_op(int port, int op)
+{
+	ASSERT(port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
+
+	/*
+	 * The order of requests from host are:
+	 *
+	 * Port 0 offline
+	 * Port 0 rescan retimers
+	 * Port 1 offline
+	 * Port 1 rescan retimers
+	 * ...
+	 * Port 0 online
+	 * Port 1 online
+	 * ...
+	 */
+	last_op = op;
+	cur_port = port;
+
+	/*
+	 * Host has requested to put this port back online, and haven't
+	 * finished online process. During this period, don't accept any
+	 * requests, except USB_RETIMER_FW_UPDATE_RESUME_PD.
+	 */
+	if (port_state[port] == RETIMER_ONLINE_REQUESTED) {
+		if (op != USB_RETIMER_FW_UPDATE_RESUME_PD) {
+			last_result = USB_RETIMER_FW_UPDATE_ERR;
+			return;
+		}
+	}
+
+	switch (op) {
+	case USB_RETIMER_FW_UPDATE_QUERY_PORT:
+		break;
+	/* Operations can't be processed in ISR, defer to later */
+	case USB_RETIMER_FW_UPDATE_GET_MUX:
+		last_result = USB_RETIMER_FW_UPDATE_INVALID_MUX;
+		tc_usb_firmware_fw_update_run(port);
+		break;
+	case USB_RETIMER_FW_UPDATE_SUSPEND_PD:
+	case USB_RETIMER_FW_UPDATE_RESUME_PD:
+		tc_usb_firmware_fw_update_run(port);
+		break;
+	case USB_RETIMER_FW_UPDATE_SET_USB:
+	case USB_RETIMER_FW_UPDATE_SET_SAFE:
+	case USB_RETIMER_FW_UPDATE_SET_TBT:
+	case USB_RETIMER_FW_UPDATE_DISCONNECT:
+		if (pd_is_port_enabled(port)) {
+			last_result = USB_RETIMER_FW_UPDATE_ERR;
+		} else {
+			last_result = USB_RETIMER_FW_UPDATE_INVALID_MUX;
+			tc_usb_firmware_fw_update_limited_run(port);
+		}
+		break;
+	default:
+		break;
+	}
+}
+
+/*
+ * If due to any reason system shuts down during firmware update, resume
+ * the PD port; otherwise, PD port is suspended even system powers up again.
+ * In normal case, system should not allow shutdown during firmware update.
+ */
+static void restore_port(void)
+{
+	int port;
+
+	for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++) {
+		if (retimer_fw_update_get_port_state(port))
+			retimer_fw_update_port_handler(port, RESUME);
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, restore_port, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_RESET, restore_port, HOOK_PRIO_DEFAULT);
diff --git a/common/usbc/usb_sm.c b/common/usbc/usb_sm.c
index 04b7193c0f..96b0b81e33 100644
--- a/common/usbc/usb_sm.c
+++ b/common/usbc/usb_sm.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,8 +12,8 @@
 #include "util.h"
 
 #ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USB, format, ##args)
 #else /* CONFIG_COMMON_RUNTIME */
 #define CPRINTF(format, args...)
 #define CPRINTS(format, args...)
@@ -23,8 +23,8 @@
 struct internal_ctx {
 	usb_state_ptr last_entered;
 	uint32_t running : 1;
-	uint32_t enter	 : 1;
-	uint32_t exit	 : 1;
+	uint32_t enter : 1;
+	uint32_t exit : 1;
 };
 BUILD_ASSERT(sizeof(struct internal_ctx) ==
 	     member_size(struct sm_ctx, internal));
@@ -65,9 +65,9 @@ static usb_state_ptr shared_parent_state(usb_state_ptr a, usb_state_ptr b)
  * functions.
  */
 static void call_entry_functions(const int port,
-			       struct internal_ctx *const internal,
-			       const usb_state_ptr stop,
-			       const usb_state_ptr current)
+				 struct internal_ctx *const internal,
+				 const usb_state_ptr stop,
+				 const usb_state_ptr current)
 {
 	if (current == stop)
 		return;
@@ -92,7 +92,7 @@ static void call_entry_functions(const int port,
  * during an exit function.
  */
 static void call_exit_functions(const int port, const usb_state_ptr stop,
-			      const usb_state_ptr current)
+				const usb_state_ptr current)
 {
 	if (current == stop)
 		return;
@@ -106,7 +106,7 @@ static void call_exit_functions(const int port, const usb_state_ptr stop,
 void set_state(const int port, struct sm_ctx *const ctx,
 	       const usb_state_ptr new_state)
 {
-	struct internal_ctx * const internal = (void *) ctx->internal;
+	struct internal_ctx *const internal = (void *)ctx->internal;
 	usb_state_ptr last_state;
 	usb_state_ptr shared_parent;
 
@@ -116,8 +116,8 @@ void set_state(const int port, struct sm_ctx *const ctx,
 	 * intended state to transition into.
 	 */
 	if (internal->exit) {
-		CPRINTF("C%d: Ignoring set state to 0x%pP within 0x%pP",
-			port, new_state, ctx->current);
+		CPRINTF("C%d: Ignoring set state to 0x%p within 0x%p", port,
+			new_state, ctx->current);
 		return;
 	}
 
@@ -176,8 +176,8 @@ void set_state(const int port, struct sm_ctx *const ctx,
  * functions.
  */
 static void call_run_functions(const int port,
-			     const struct internal_ctx *const internal,
-			     const usb_state_ptr current)
+			       const struct internal_ctx *const internal,
+			       const usb_state_ptr current)
 {
 	if (!current)
 		return;
@@ -194,7 +194,7 @@ static void call_run_functions(const int port,
 
 void run_state(const int port, struct sm_ctx *const ctx)
 {
-	struct internal_ctx * const internal = (void *) ctx->internal;
+	struct internal_ctx *const internal = (void *)ctx->internal;
 
 	internal->running = true;
 	call_run_functions(port, internal, ctx->current);
diff --git a/common/usbc/usb_tc_ctvpd_sm.c b/common/usbc/usb_tc_ctvpd_sm.c
index f6aab7dec3..045cca55c4 100644
--- a/common/usbc/usb_tc_ctvpd_sm.c
+++ b/common/usbc/usb_tc_ctvpd_sm.c
@@ -1,13 +1,15 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
 #include "system.h"
 #include "task.h"
-#include "tcpm.h"
+#include "tcpm/tcpm.h"
+#include "typec_control.h"
 #include "usb_pd.h"
 #include "usb_tc_sm.h"
 #include "vpd_api.h"
@@ -15,18 +17,18 @@
 /* USB Type-C CTVPD module */
 
 #ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 #else /* CONFIG_COMMON_RUNTIME */
 #define CPRINTF(format, args...)
 #define CPRINTS(format, args...)
 #endif
 
 /* Type-C Layer Flags */
-#define TC_FLAGS_VCONN_ON           BIT(0)
+#define TC_FLAGS_VCONN_ON BIT(0)
 
-#define SUPPORT_TIMER_RESET_INIT     0
-#define SUPPORT_TIMER_RESET_REQUEST  1
+#define SUPPORT_TIMER_RESET_INIT 0
+#define SUPPORT_TIMER_RESET_REQUEST 1
 #define SUPPORT_TIMER_RESET_COMPLETE 2
 
 /**
@@ -104,10 +106,9 @@ enum usb_tc_state {
 /* Forward declare the full list of states. This is indexed by usb_tc_state */
 static const struct usb_state tc_states[];
 
-
-#ifdef CONFIG_COMMON_RUNTIME
 /* List of human readable state names for console debugging */
-const char * const tc_state_names[] = {
+__maybe_unused const char *const tc_state_names[] = {
+#ifdef CONFIG_COMMON_RUNTIME
 	[TC_DISABLED] = "Disabled",
 	[TC_UNATTACHED_SNK] = "Unattached.SNK",
 	[TC_ATTACH_WAIT_SNK] = "AttachWait.SNK",
@@ -126,8 +127,8 @@ const char * const tc_state_names[] = {
 	[TC_CT_DISABLED_VPD] = "CTDisabled.VPD",
 	[TC_CT_ATTACHED_VPD] = "CTAttached.VPD",
 	[TC_CT_ATTACH_WAIT_VPD] = "CTAttachWait.VPD",
-};
 #endif
+};
 
 /* Forward declare private, common functions */
 static void set_state_tc(const int port, enum usb_tc_state new_state);
@@ -170,6 +171,17 @@ void tc_reset_support_timer(int port)
 	tc[port].support_timer_reset |= SUPPORT_TIMER_RESET_REQUEST;
 }
 
+void tc_start_error_recovery(int port)
+{
+	assert(port == TASK_ID_TO_PD_PORT(task_get_current()));
+
+	/*
+	 *   The port should transition to the ErrorRecovery state
+	 *   from any other state when directed.
+	 */
+	set_state_tc(port, TC_ERROR_RECOVERY);
+}
+
 /*
  * TCPC CC/Rp management
  *
@@ -245,9 +257,9 @@ test_mockable_static void print_current_state(const int port)
 int pd_is_connected(int port)
 {
 	return (get_state_tc(port) == TC_ATTACHED_SNK) ||
-			(get_state_tc(port) == TC_ATTACHED_SRC) ||
-			(get_state_tc(port) == TC_CT_ATTACHED_UNSUPPORTED) ||
-			(get_state_tc(port) == TC_CT_ATTACHED_VPD);
+	       (get_state_tc(port) == TC_ATTACHED_SRC) ||
+	       (get_state_tc(port) == TC_CT_ATTACHED_UNSUPPORTED) ||
+	       (get_state_tc(port) == TC_CT_ATTACHED_VPD);
 }
 
 bool pd_is_disconnected(int port)
@@ -386,7 +398,7 @@ static void tc_unattached_snk_run(const int port)
 	 *   2) VBUS is detected
 	 */
 	if (vpd_is_ct_vbus_present() &&
-				tc[port].cc_state == PD_CC_DFP_ATTACHED) {
+	    tc[port].cc_state == PD_CC_DFP_ATTACHED) {
 		set_state_tc(port, TC_UNATTACHED_SRC);
 		return;
 	}
@@ -424,11 +436,11 @@ static void tc_attach_wait_snk_run(const int port)
 	if (tc[port].host_cc_state != host_new_cc_state) {
 		tc[port].host_cc_state = host_new_cc_state;
 		if (host_new_cc_state == PD_CC_DFP_ATTACHED)
-			tc[port].host_cc_debounce = get_time().val +
-							PD_T_CC_DEBOUNCE;
+			tc[port].host_cc_debounce =
+				get_time().val + PD_T_CC_DEBOUNCE;
 		else
-			tc[port].host_cc_debounce = get_time().val +
-							PD_T_PD_DEBOUNCE;
+			tc[port].host_cc_debounce =
+				get_time().val + PD_T_PD_DEBOUNCE;
 		return;
 	}
 
@@ -446,7 +458,7 @@ static void tc_attach_wait_snk_run(const int port)
 	 * CC2 pins is SNK.Open for at least tPDDebounce.
 	 */
 	if (tc[port].host_cc_state == PD_CC_DFP_ATTACHED &&
-			(vpd_is_vconn_present() || vpd_is_host_vbus_present()))
+	    (vpd_is_vconn_present() || vpd_is_host_vbus_present()))
 		set_state_tc(port, TC_ATTACHED_SNK);
 	else if (tc[port].host_cc_state == PD_CC_NONE)
 		set_state_tc(port, TC_UNATTACHED_SNK);
@@ -461,7 +473,7 @@ static void tc_attached_snk_entry(const int port)
 
 	/* Enable PD */
 	tc[port].pd_enable = 1;
-	pd_set_polarity(port, 0);
+	typec_set_polarity(port, 0);
 
 	/*
 	 * This state can only be entered from states AttachWait.SNK
@@ -539,7 +551,7 @@ static void tc_attached_snk_run(const int port)
 
 	/* Check the Support Timer */
 	if (get_time().val > tc[port].support_timer &&
-					!tc[port].billboard_presented) {
+	    !tc[port].billboard_presented) {
 		/*
 		 * Present USB Billboard Device Class interface
 		 * indicating that Charge-Through is not supported
@@ -642,7 +654,7 @@ static void tc_unattached_src_run(const int port)
 	 * if Charge-Through VBUS is removed.
 	 */
 	if (!vpd_is_ct_vbus_present() ||
-				get_time().val > tc[port].next_role_swap) {
+	    get_time().val > tc[port].next_role_swap) {
 		set_state_tc(port, TC_UNATTACHED_SNK);
 		return;
 	}
@@ -707,7 +719,7 @@ static void tc_attach_wait_src_run(const int port)
 	 * state is on the Host-side port’s CC pin for at least tCCDebounce.
 	 */
 	if (tc[port].host_cc_state == PD_CC_UFP_ATTACHED &&
-						!vpd_is_host_vbus_present()) {
+	    !vpd_is_host_vbus_present()) {
 		set_state_tc(port, TC_TRY_SNK);
 		return;
 	}
@@ -722,7 +734,7 @@ static void tc_attached_src_entry(const int port)
 
 	/* Enable PD */
 	tc[port].pd_enable = 1;
-	pd_set_polarity(port, 0);
+	typec_set_polarity(port, 0);
 
 	/* Connect Charge-Through VBUS to Host VBUS */
 	vpd_vbus_pass_en(1);
@@ -835,7 +847,7 @@ static void tc_try_snk_run(const int port)
 	 * for tTryCCDebounce.
 	 */
 	if (tc[port].host_cc_state == PD_CC_DFP_ATTACHED &&
-			(vpd_is_host_vbus_present() || vpd_is_vconn_present()))
+	    (vpd_is_host_vbus_present() || vpd_is_vconn_present()))
 		set_state_tc(port, TC_ATTACHED_SNK);
 	else if (tc[port].host_cc_state == PD_CC_NONE)
 		set_state_tc(port, TC_TRY_WAIT_SRC);
@@ -875,7 +887,7 @@ static void tc_try_wait_src_run(const int port)
 	if (tc[port].host_cc_state != host_new_cc_state) {
 		tc[port].host_cc_state = host_new_cc_state;
 		tc[port].host_cc_debounce =
-					get_time().val + PD_T_TRY_CC_DEBOUNCE;
+			get_time().val + PD_T_TRY_CC_DEBOUNCE;
 		return;
 	}
 
@@ -887,7 +899,7 @@ static void tc_try_wait_src_run(const int port)
 		 * at least tTryCCDebounce.
 		 */
 		if (tc[port].host_cc_state == PD_CC_UFP_ATTACHED &&
-						!vpd_is_host_vbus_present()) {
+		    !vpd_is_host_vbus_present()) {
 			set_state_tc(port, TC_ATTACHED_SRC);
 			return;
 		}
@@ -922,7 +934,7 @@ static void tc_ct_try_snk_entry(const int port)
 
 	/* Enable PD */
 	tc[port].pd_enable = 1;
-	pd_set_polarity(port, 0);
+	typec_set_polarity(port, 0);
 
 	tc[port].cc_state = PD_CC_UNSET;
 	tc[port].next_role_swap = get_time().val + PD_T_DRP_TRY;
@@ -976,7 +988,7 @@ static void tc_ct_try_snk_run(const int port)
 		 * Charge-Through port.
 		 */
 		if (tc[port].cc_state == PD_CC_DFP_ATTACHED &&
-				vpd_is_ct_vbus_present()) {
+		    vpd_is_ct_vbus_present()) {
 			set_state_tc(port, TC_CT_ATTACHED_VPD);
 			return;
 		}
@@ -989,8 +1001,7 @@ static void tc_ct_try_snk_run(const int port)
 		 * for tDRPTryWait.
 		 */
 		if (tc[port].cc_state == PD_CC_NONE) {
-			set_state_tc(port,
-					TC_CT_ATTACHED_UNSUPPORTED);
+			set_state_tc(port, TC_CT_ATTACHED_UNSUPPORTED);
 			return;
 		}
 	}
@@ -1018,7 +1029,7 @@ static void tc_ct_attach_wait_unsupported_entry(const int port)
 
 	/* Enable PD */
 	tc[port].pd_enable = 1;
-	pd_set_polarity(port, 0);
+	typec_set_polarity(port, 0);
 
 	tc[port].cc_state = PD_CC_UNSET;
 }
@@ -1148,7 +1159,7 @@ static void tc_ct_unattached_unsupported_entry(const int port)
 
 	/* Enable PD */
 	tc[port].pd_enable = 1;
-	pd_set_polarity(port, 0);
+	typec_set_polarity(port, 0);
 
 	tc[port].next_role_swap = get_time().val + PD_T_DRP_SRC;
 }
@@ -1169,8 +1180,7 @@ static void tc_ct_unattached_unsupported_run(const int port)
 	 * on both the CC1 and CC2 pins.
 	 */
 	if (cc_is_at_least_one_rd(cc1, cc2) || cc_is_audio_acc(cc1, cc2)) {
-		set_state_tc(port,
-				TC_CT_ATTACH_WAIT_UNSUPPORTED);
+		set_state_tc(port, TC_CT_ATTACH_WAIT_UNSUPPORTED);
 		return;
 	}
 
@@ -1216,7 +1226,7 @@ static void tc_ct_unattached_vpd_entry(const int port)
 
 	/* Enable PD */
 	tc[port].pd_enable = 1;
-	pd_set_polarity(port, 0);
+	typec_set_polarity(port, 0);
 
 	tc[port].cc_state = PD_CC_UNSET;
 }
@@ -1331,7 +1341,7 @@ static void tc_ct_attached_vpd_entry(const int port)
 	 * pins is connected through the cable
 	 */
 	vpd_ct_get_cc(&cc1, &cc2);
-	tc[port].ct_cc  = cc_is_rp(cc2) ? CT_CC2 : CT_CC1;
+	tc[port].ct_cc = cc_is_rp(cc2) ? CT_CC2 : CT_CC1;
 
 	/*
 	 * 1. Remove or reduce any additional capacitance on the
@@ -1423,7 +1433,7 @@ static void tc_ct_attach_wait_vpd_entry(const int port)
 
 	/* Enable PD */
 	tc[port].pd_enable = 1;
-	pd_set_polarity(port, 0);
+	typec_set_polarity(port, 0);
 
 	tc[port].cc_state = PD_CC_UNSET;
 }
@@ -1456,10 +1466,8 @@ static void tc_ct_attach_wait_vpd_run(const int port)
 	/* Debounce the cc state */
 	if (new_cc_state != tc[port].cc_state) {
 		tc[port].cc_state = new_cc_state;
-		tc[port].cc_debounce = get_time().val +
-						PD_T_CC_DEBOUNCE;
-		tc[port].pd_debounce = get_time().val +
-						PD_T_PD_DEBOUNCE;
+		tc[port].cc_debounce = get_time().val + PD_T_CC_DEBOUNCE;
+		tc[port].pd_debounce = get_time().val + PD_T_PD_DEBOUNCE;
 		return;
 	}
 
@@ -1470,7 +1478,7 @@ static void tc_ct_attach_wait_vpd_run(const int port)
 		 * port’s CC1 and CC2 pins are SNK.Open for at least
 		 * tPDDebounce.
 		 */
-		if (tc[port].cc_state  == PD_CC_NONE) {
+		if (tc[port].cc_state == PD_CC_NONE) {
 			set_state_tc(port, TC_CT_UNATTACHED_VPD);
 			return;
 		}
@@ -1484,8 +1492,8 @@ static void tc_ct_attach_wait_vpd_run(const int port)
 		 * least tCCDebounce and VBUS on the Charge-Through port is
 		 * detected.
 		 */
-		if (tc[port].cc_state  == PD_CC_DFP_ATTACHED &&
-						vpd_is_ct_vbus_present()) {
+		if (tc[port].cc_state == PD_CC_DFP_ATTACHED &&
+		    vpd_is_ct_vbus_present()) {
 			set_state_tc(port, TC_CT_ATTACHED_VPD);
 			return;
 		}
diff --git a/common/usbc/usb_tc_drp_acc_trysrc_sm.c b/common/usbc/usb_tc_drp_acc_trysrc_sm.c
index 1756f39c4a..a43a9ffa2a 100644
--- a/common/usbc/usb_tc_drp_acc_trysrc_sm.c
+++ b/common/usbc/usb_tc_drp_acc_trysrc_sm.c
@@ -1,24 +1,30 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "builtin/assert.h"
 #include "charge_manager.h"
 #include "charge_state.h"
 #include "common.h"
 #include "console.h"
+#include "gpio.h"
 #include "hooks.h"
 #include "system.h"
 #include "task.h"
-#include "tcpm.h"
+#include "tcpm/tcpm.h"
+#include "typec_control.h"
 #include "usb_common.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
-#include "usb_pd_dpm.h"
+#include "usb_pd_dpm_sm.h"
+#include "usb_pd_tcpm.h"
+#include "usb_pd_timer.h"
 #include "usb_pe_sm.h"
 #include "usb_prl_sm.h"
 #include "usb_sm.h"
 #include "usb_tc_sm.h"
+#include "usbc_ocp.h"
 #include "usbc_ppc.h"
 #include "vboot.h"
 
@@ -27,30 +33,30 @@
  *   See Figure 4-16 in Release 1.4 of USB Type-C Spec.
  */
 #ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 #else /* CONFIG_COMMON_RUNTIME */
 #define CPRINTF(format, args...)
 #define CPRINTS(format, args...)
 #endif
 
-#define CPRINTF_LX(x, format, args...) \
-	do { \
-		if (tc_debug_level >= x) \
-			CPRINTF(format, ## args); \
+#define CPRINTF_LX(x, format, args...)           \
+	do {                                     \
+		if (tc_debug_level >= x)         \
+			CPRINTF(format, ##args); \
 	} while (0)
-#define CPRINTF_L1(format, args...) CPRINTF_LX(1, format, ## args)
-#define CPRINTF_L2(format, args...) CPRINTF_LX(2, format, ## args)
-#define CPRINTF_L3(format, args...) CPRINTF_LX(3, format, ## args)
-
-#define CPRINTS_LX(x, format, args...) \
-	do { \
-		if (tc_debug_level >= x) \
-			CPRINTS(format, ## args); \
+#define CPRINTF_L1(format, args...) CPRINTF_LX(1, format, ##args)
+#define CPRINTF_L2(format, args...) CPRINTF_LX(2, format, ##args)
+#define CPRINTF_L3(format, args...) CPRINTF_LX(3, format, ##args)
+
+#define CPRINTS_LX(x, format, args...)           \
+	do {                                     \
+		if (tc_debug_level >= x)         \
+			CPRINTS(format, ##args); \
 	} while (0)
-#define CPRINTS_L1(format, args...) CPRINTS_LX(1, format, ## args)
-#define CPRINTS_L2(format, args...) CPRINTS_LX(2, format, ## args)
-#define CPRINTS_L3(format, args...) CPRINTS_LX(3, format, ## args)
+#define CPRINTS_L1(format, args...) CPRINTS_LX(1, format, ##args)
+#define CPRINTS_L2(format, args...) CPRINTS_LX(2, format, ##args)
+#define CPRINTS_L3(format, args...) CPRINTS_LX(3, format, ##args)
 
 /*
  * Define DEBUG_PRINT_FLAG_AND_EVENT_NAMES to print flag names when set and
@@ -59,78 +65,85 @@
 #undef DEBUG_PRINT_FLAG_AND_EVENT_NAMES
 
 #ifdef DEBUG_PRINT_FLAG_AND_EVENT_NAMES
-void print_flag(int set_or_clear, int flag);
-#define TC_SET_FLAG(port, flag)                                \
-	do {                                                   \
-		print_flag(1, flag);                           \
-		deprecated_atomic_or(&tc[port].flags, (flag)); \
+void print_flag(int port, int set_or_clear, int flag);
+#define TC_SET_FLAG(port, flag)                     \
+	do {                                        \
+		print_flag(port, 1, flag);          \
+		atomic_or(&tc[port].flags, (flag)); \
 	} while (0)
-#define TC_CLR_FLAG(port, flag)                                        \
-	do {                                                           \
-		print_flag(0, flag);                                   \
-		deprecated_atomic_clear_bits(&tc[port].flags, (flag)); \
+#define TC_CLR_FLAG(port, flag)                             \
+	do {                                                \
+		print_flag(port, 0, flag);                  \
+		atomic_clear_bits(&tc[port].flags, (flag)); \
 	} while (0)
 #else
-#define TC_SET_FLAG(port, flag) deprecated_atomic_or(&tc[port].flags, (flag))
-#define TC_CLR_FLAG(port, flag) \
-	deprecated_atomic_clear_bits(&tc[port].flags, (flag))
+#define TC_SET_FLAG(port, flag) atomic_or(&tc[port].flags, (flag))
+#define TC_CLR_FLAG(port, flag) atomic_clear_bits(&tc[port].flags, (flag))
 #endif
 #define TC_CHK_FLAG(port, flag) (tc[port].flags & (flag))
 
 /* Type-C Layer Flags */
 /* Flag to note we are sourcing VCONN */
-#define TC_FLAGS_VCONN_ON               BIT(0)
+#define TC_FLAGS_VCONN_ON BIT(0)
 /* Flag to note port partner has Rp/Rp or Rd/Rd */
-#define TC_FLAGS_TS_DTS_PARTNER         BIT(1)
+#define TC_FLAGS_TS_DTS_PARTNER BIT(1)
 /* Flag to note VBus input has never been low */
-#define TC_FLAGS_VBUS_NEVER_LOW         BIT(2)
+#define TC_FLAGS_VBUS_NEVER_LOW BIT(2)
 /* Flag to note Low Power Mode transition is currently happening */
-#define TC_FLAGS_LPM_TRANSITION         BIT(3)
+#define TC_FLAGS_LPM_TRANSITION BIT(3)
 /* Flag to note Low Power Mode is currently on */
-#define TC_FLAGS_LPM_ENGAGED            BIT(4)
+#define TC_FLAGS_LPM_ENGAGED BIT(4)
 /* Flag to note CVTPD has been detected */
-#define TC_FLAGS_CTVPD_DETECTED         BIT(5)
+#define TC_FLAGS_CTVPD_DETECTED BIT(5)
 /* Flag to note request to swap to VCONN on */
-#define TC_FLAGS_REQUEST_VC_SWAP_ON     BIT(6)
+#define TC_FLAGS_REQUEST_VC_SWAP_ON BIT(6)
 /* Flag to note request to swap to VCONN off */
-#define TC_FLAGS_REQUEST_VC_SWAP_OFF    BIT(7)
+#define TC_FLAGS_REQUEST_VC_SWAP_OFF BIT(7)
 /* Flag to note request to swap VCONN is being rejected */
-#define TC_FLAGS_REJECT_VCONN_SWAP      BIT(8)
+#define TC_FLAGS_REJECT_VCONN_SWAP BIT(8)
 /* Flag to note request to power role swap */
-#define TC_FLAGS_REQUEST_PR_SWAP        BIT(9)
+#define TC_FLAGS_REQUEST_PR_SWAP BIT(9)
 /* Flag to note request to data role swap */
-#define TC_FLAGS_REQUEST_DR_SWAP        BIT(10)
+#define TC_FLAGS_REQUEST_DR_SWAP BIT(10)
 /* Flag to note request to power off sink */
-#define TC_FLAGS_POWER_OFF_SNK          BIT(11)
-/* Flag to note port partner has unconstrained power */
-#define TC_FLAGS_PARTNER_UNCONSTRAINED  BIT(12)
-/* Flag to note port partner is Dual Role Data */
-#define TC_FLAGS_PARTNER_DR_DATA        BIT(13)
-/* Flag to note port partner is Dual Role Power */
-#define TC_FLAGS_PARTNER_DR_POWER       BIT(14)
+#define TC_FLAGS_POWER_OFF_SNK BIT(11)
 /* Flag to note port partner is Power Delivery capable */
-#define TC_FLAGS_PARTNER_PD_CAPABLE     BIT(15)
+#define TC_FLAGS_PARTNER_PD_CAPABLE BIT(12)
 /* Flag to note hard reset has been requested */
-#define TC_FLAGS_HARD_RESET_REQUESTED   BIT(16)
-/* Flag to note port partner is USB comms capable */
-#define TC_FLAGS_PARTNER_USB_COMM       BIT(17)
+#define TC_FLAGS_HARD_RESET_REQUESTED BIT(13)
 /* Flag to note we are currently performing PR Swap */
-#define TC_FLAGS_PR_SWAP_IN_PROGRESS    BIT(18)
-/* Flag to note we are performing Discover Identity */
-#define TC_FLAGS_DISC_IDENT_IN_PROGRESS BIT(19)
+#define TC_FLAGS_PR_SWAP_IN_PROGRESS BIT(14)
 /* Flag to note we should check for connection */
-#define TC_FLAGS_CHECK_CONNECTION       BIT(20)
-/* Flag to note pd_set_suspend SUSPEND state */
-#define TC_FLAGS_SUSPEND                BIT(21)
+#define TC_FLAGS_CHECK_CONNECTION BIT(15)
+/* Flag to note request from pd_set_suspend to enter TC_DISABLED state */
+#define TC_FLAGS_REQUEST_SUSPEND BIT(16)
+/* Flag to note we are in TC_DISABLED state */
+#define TC_FLAGS_SUSPENDED BIT(17)
+/* Flag to indicate the port current limit has changed */
+#define TC_FLAGS_UPDATE_CURRENT BIT(18)
+/* Flag to indicate USB mux should be updated */
+#define TC_FLAGS_UPDATE_USB_MUX BIT(19)
+/* Flag for retimer firmware update */
+#define TC_FLAGS_USB_RETIMER_FW_UPDATE_RUN BIT(20)
+#define TC_FLAGS_USB_RETIMER_FW_UPDATE_LTD_RUN BIT(21)
+/* Flag for asynchronous call to request Error Recovery */
+#define TC_FLAGS_REQUEST_ERROR_RECOVERY BIT(22)
+
+/* For checking flag_bit_names[] array */
+#define TC_FLAGS_COUNT 23
+
+/* On disconnect, clear most of the flags. */
+#define CLR_FLAGS_ON_DISCONNECT(port)                                         \
+	TC_CLR_FLAG(port, ~(TC_FLAGS_LPM_ENGAGED | TC_FLAGS_REQUEST_SUSPEND | \
+			    TC_FLAGS_SUSPENDED))
 
 /*
- * Clear all flags except TC_FLAGS_LPM_ENGAGED and TC_FLAGS_SUSPEND.
+ * 10 ms is enough time for any TCPC transaction to complete
+ *
+ * This value must be below ~39.7 ms to put ANX7447 into LPM due to bug in
+ * silicon (see b/77544959 and b/149761477 for more details).
  */
-#define CLR_ALL_BUT_LPM_FLAGS(port) TC_CLR_FLAG(port, \
-	~(TC_FLAGS_LPM_ENGAGED | TC_FLAGS_SUSPEND))
-
-/* 100 ms is enough time for any TCPC transaction to complete. */
-#define PD_LPM_DEBOUNCE_US (100 * MSEC)
+#define PD_LPM_DEBOUNCE_US (10 * MSEC)
 
 /*
  * This delay is not part of the USB Type-C specification or the USB port
@@ -142,20 +155,27 @@ void print_flag(int set_or_clear, int flag);
  *
  * TODO(b/162347811): TCPMv2: Wait for debounce on Vbus and CC lines
  */
+#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
 #define PD_LPM_EXIT_DEBOUNCE_US CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
+#else
+/*
+ * Define this value regardless so it is not missing at compile time.
+ */
+#define PD_LPM_EXIT_DEBOUNCE_US 0
+#endif
 
 /*
  * The TypeC state machine uses this bit to disable/enable PD
  * This bit corresponds to bit-0 of pd_disabled_mask
  */
-#define PD_DISABLED_NO_CONNECTION  BIT(0)
+#define PD_DISABLED_NO_CONNECTION BIT(0)
 /*
  * Console and Host commands use this bit to override the
  * PD_DISABLED_NO_CONNECTION bit that was set by the TypeC
  * state machine.
  * This bit corresponds to bit-1 of pd_disabled_mask
  */
-#define PD_DISABLED_BY_POLICY       BIT(1)
+#define PD_DISABLED_BY_POLICY BIT(1)
 
 /* Unreachable time in future */
 #define TIMER_DISABLED 0xffffffffffffffff
@@ -187,6 +207,8 @@ enum usb_tc_state {
 	TC_LOW_POWER_MODE,
 	TC_CT_UNATTACHED_SNK,
 	TC_CT_ATTACHED_SNK,
+
+	TC_STATE_COUNT,
 };
 /* Forward declare the full list of states. This is indexed by usb_tc_state */
 static const struct usb_state tc_states[];
@@ -212,6 +234,16 @@ GEN_NOT_SUPPORTED(TC_CT_ATTACHED_SNK);
 #define TC_CT_ATTACHED_SNK TC_CT_ATTACHED_SNK_NOT_SUPPORTED
 #endif /* CONFIG_USB_PE_SM */
 
+/*
+ * If CONFIG_ASSERT_CCD_MODE_ON_DTS_CONNECT is not defined then
+ * _GPIO_CCD_MODE_ODL is not needed. Declare as extern so IS_ENABLED will work.
+ */
+#ifndef CONFIG_ASSERT_CCD_MODE_ON_DTS_CONNECT
+extern int _GPIO_CCD_MODE_ODL;
+#else
+#define _GPIO_CCD_MODE_ODL GPIO_CCD_MODE_ODL
+#endif /* CONFIG_ASSERT_CCD_MODE_ON_DTS_CONNECT */
+
 /*
  * We will use DEBUG LABELS if we will be able to print (COMMON RUNTIME)
  * and either CONFIG_USB_PD_DEBUG_LEVEL is not defined (no override) or
@@ -220,9 +252,8 @@ GEN_NOT_SUPPORTED(TC_CT_ATTACHED_SNK);
  * If we can't print or the CONFIG_USB_PD_DEBUG_LEVEL is defined to be 0
  * then the DEBUG LABELS will be removed from the build.
  */
-#if defined(CONFIG_COMMON_RUNTIME) && \
-	(!defined(CONFIG_USB_PD_DEBUG_LEVEL) || \
-	 (CONFIG_USB_PD_DEBUG_LEVEL > 0))
+#if defined(CONFIG_COMMON_RUNTIME) && (!defined(CONFIG_USB_PD_DEBUG_LEVEL) || \
+				       (CONFIG_USB_PD_DEBUG_LEVEL > 0))
 #define USB_PD_DEBUG_LABELS
 #endif
 
@@ -238,10 +269,9 @@ GEN_NOT_SUPPORTED(TC_CT_ATTACHED_SNK);
  */
 #define IS_ATTACHED_SNK(port) (get_state_tc(port) == TC_ATTACHED_SNK)
 
-
-#ifdef USB_PD_DEBUG_LABELS
 /* List of human readable state names for console debugging */
-static const char * const tc_state_names[] = {
+__maybe_unused static __const_data const char *const tc_state_names[] = {
+#ifdef USB_PD_DEBUG_LABELS
 	[TC_DISABLED] = "Disabled",
 	[TC_ERROR_RECOVERY] = "ErrorRecovery",
 	[TC_UNATTACHED_SNK] = "Unattached.SNK",
@@ -259,33 +289,31 @@ static const char * const tc_state_names[] = {
 	[TC_LOW_POWER_MODE] = "LowPowerMode",
 #endif
 #ifdef CONFIG_USB_PE_SM
-	[TC_CT_UNATTACHED_SNK] =  "CTUnattached.SNK",
+	[TC_CT_UNATTACHED_SNK] = "CTUnattached.SNK",
 	[TC_CT_ATTACHED_SNK] = "CTAttached.SNK",
 #endif
 	/* Super States */
 	[TC_CC_OPEN] = "SS:CC_OPEN",
 	[TC_CC_RD] = "SS:CC_RD",
 	[TC_CC_RP] = "SS:CC_RP",
-};
-#else
-/*
- * Reference so IS_ENABLED section below that references the names
- * will compile and the optimizer will remove it.
- */
-extern const char **tc_state_names;
+
+	[TC_STATE_COUNT] = "",
 #endif
+};
 
 /* Debug log level - higher number == more log */
 #ifdef CONFIG_USB_PD_DEBUG_LEVEL
 static const enum debug_level tc_debug_level = CONFIG_USB_PD_DEBUG_LEVEL;
+#elif defined(CONFIG_USB_PD_INITIAL_DEBUG_LEVEL)
+static enum debug_level tc_debug_level = CONFIG_USB_PD_INITIAL_DEBUG_LEVEL;
 #else
 static enum debug_level tc_debug_level = DEBUG_LEVEL_1;
 #endif
 
 #ifdef DEBUG_PRINT_FLAG_AND_EVENT_NAMES
 struct bit_name {
-	int		value;
-	const char	*name;
+	int value;
+	const char *name;
 };
 
 static struct bit_name flag_bit_names[] = {
@@ -301,17 +329,20 @@ static struct bit_name flag_bit_names[] = {
 	{ TC_FLAGS_REQUEST_PR_SWAP, "REQUEST_PR_SWAP" },
 	{ TC_FLAGS_REQUEST_DR_SWAP, "REQUEST_DR_SWAP" },
 	{ TC_FLAGS_POWER_OFF_SNK, "POWER_OFF_SNK" },
-	{ TC_FLAGS_PARTNER_UNCONSTRAINED, "PARTNER_UNCONSTRAINED" },
-	{ TC_FLAGS_PARTNER_DR_DATA, "PARTNER_DR_DATA" },
-	{ TC_FLAGS_PARTNER_DR_POWER, "PARTNER_DR_POWER" },
 	{ TC_FLAGS_PARTNER_PD_CAPABLE, "PARTNER_PD_CAPABLE" },
 	{ TC_FLAGS_HARD_RESET_REQUESTED, "HARD_RESET_REQUESTED" },
-	{ TC_FLAGS_PARTNER_USB_COMM, "PARTNER_USB_COMM" },
 	{ TC_FLAGS_PR_SWAP_IN_PROGRESS, "PR_SWAP_IN_PROGRESS" },
-	{ TC_FLAGS_DISC_IDENT_IN_PROGRESS, "DISC_IDENT_IN_PROGRESS" },
 	{ TC_FLAGS_CHECK_CONNECTION, "CHECK_CONNECTION" },
-	{ TC_FLAGS_SUSPEND, "SUSPEND" },
+	{ TC_FLAGS_REQUEST_SUSPEND, "REQUEST_SUSPEND" },
+	{ TC_FLAGS_SUSPENDED, "SUSPENDED" },
+	{ TC_FLAGS_UPDATE_CURRENT, "UPDATE_CURRENT" },
+	{ TC_FLAGS_UPDATE_USB_MUX, "UPDATE_USB_MUX" },
+	{ TC_FLAGS_USB_RETIMER_FW_UPDATE_RUN, "USB_RETIMER_FW_UPDATE_RUN" },
+	{ TC_FLAGS_USB_RETIMER_FW_UPDATE_LTD_RUN,
+	  "USB_RETIMER_FW_UPDATE_LTD_RUN" },
+	{ TC_FLAGS_REQUEST_ERROR_RECOVERY, "REQUEST_ERROR_RECOCVERY" },
 };
+BUILD_ASSERT(ARRAY_SIZE(flag_bit_names) == TC_FLAGS_COUNT);
 
 static struct bit_name event_bit_names[] = {
 	{ TASK_EVENT_SYSJUMP_READY, "SYSJUMP_READY" },
@@ -319,7 +350,9 @@ static struct bit_name event_bit_names[] = {
 	{ TASK_EVENT_PD_AWAKE, "PD_AWAKE" },
 	{ TASK_EVENT_PECI_DONE, "PECI_DONE" },
 	{ TASK_EVENT_I2C_IDLE, "I2C_IDLE" },
+#ifdef TASK_EVENT_PS2_DONE
 	{ TASK_EVENT_PS2_DONE, "PS2_DONE" },
+#endif
 	{ TASK_EVENT_DMA_TC, "DMA_TC" },
 	{ TASK_EVENT_ADC_DONE, "ADC_DONE" },
 	{ TASK_EVENT_RESET_DONE, "RESET_DONE" },
@@ -336,12 +369,12 @@ static struct bit_name event_bit_names[] = {
 	{ PD_EVENT_SYSJUMP, "SYSJUMP" },
 };
 
-static void print_bits(const char *desc, int value,
+static void print_bits(int port, const char *desc, int value,
 		       struct bit_name *names, int names_size)
 {
 	int i;
 
-	CPRINTF("%s 0x%x : ", desc, value);
+	CPRINTF("C%d: %s 0x%x : ", port, desc, value);
 	for (i = 0; i < names_size; i++) {
 		if (value & names[i].value)
 			CPRINTF("%s | ", names[i].name);
@@ -352,17 +385,18 @@ static void print_bits(const char *desc, int value,
 	CPRINTF("\n");
 }
 
-void print_flag(int set_or_clear, int flag)
+void print_flag(int port, int set_or_clear, int flag)
 {
-	print_bits(set_or_clear ? "Set" : "Clr", flag, flag_bit_names,
+	print_bits(port, set_or_clear ? "Set" : "Clr", flag, flag_bit_names,
 		   ARRAY_SIZE(flag_bit_names));
 }
 #endif /* DEBUG_PRINT_FLAG_AND_EVENT_NAMES */
 
-/* Generate a compiler error if invalid states are referenced */
 #ifndef CONFIG_USB_PD_TRY_SRC
-#define TC_TRY_SRC	TC_TRY_SRC_UNDEFINED
-#define TC_TRY_WAIT_SNK	TC_TRY_WAIT_SNK_UNDEFINED
+extern int TC_TRY_SRC_UNDEFINED;
+extern int TC_TRY_WAIT_SNK_UNDEFINED;
+#define TC_TRY_SRC TC_TRY_SRC_UNDEFINED
+#define TC_TRY_WAIT_SNK TC_TRY_WAIT_SNK_UNDEFINED
 #endif
 
 static struct type_c {
@@ -377,7 +411,7 @@ static struct type_c {
 	 * else they're disabled if bits PD_DISABLED_NO_CONNECTION or
 	 * PD_DISABLED_BY_POLICY are set.
 	 */
-	uint32_t pd_disabled_mask;
+	atomic_t pd_disabled_mask;
 	/*
 	 * Timer for handling TOGGLE_OFF/FORCE_SINK mode when auto-toggle
 	 * enabled. See drp_auto_toggle_next_state() for details.
@@ -390,41 +424,13 @@ static struct type_c {
 	/* Port polarity */
 	enum tcpc_cc_polarity polarity;
 	/* port flags, see TC_FLAGS_* */
-	uint32_t flags;
-	/* Time a port shall wait before it can determine it is attached */
-	uint64_t cc_debounce;
-	/*
-	 * Time a Sink port shall wait before it can determine it is detached
-	 * due to the potential for USB PD signaling on CC as described in
-	 * the state definitions.
-	 */
-	uint64_t pd_debounce;
-	/*
-	 * Time to ignore Vbus absence due to external IC debounce detection
-	 * logic immediately after a power role swap.
-	 */
-	uint64_t vbus_debounce_time;
-#ifdef CONFIG_USB_PD_TRY_SRC
-	/*
-	 * Time a port shall wait before it can determine it is
-	 * re-attached during the try-wait process.
-	 */
-	uint64_t try_wait_debounce;
-#endif
+	atomic_t flags;
 	/* The cc state */
 	enum pd_cc_states cc_state;
-	/* Role toggle timer */
-	uint64_t next_role_swap;
-	/* Generic timer */
-	uint64_t timeout;
-	/* Time to enter low power mode */
-	uint64_t low_power_time;
-	/* Time to debounce exit low power mode */
-	uint64_t low_power_exit_time;
 	/* Tasks to notify after TCPC has been reset */
-	int tasks_waiting_on_reset;
+	atomic_t tasks_waiting_on_reset;
 	/* Tasks preventing TCPC from entering low power mode */
-	int tasks_preventing_lpm;
+	atomic_t tasks_preventing_lpm;
 	/* Voltage on CC pin */
 	enum tcpc_cc_voltage_status cc_voltage;
 	/* Type-C current */
@@ -439,10 +445,11 @@ static struct type_c {
 } tc[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 /* Port dual-role state */
-static volatile __maybe_unused
-enum pd_dual_role_states drp_state[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[0 ... (CONFIG_USB_PD_PORT_MAX_COUNT - 1)] =
-		CONFIG_USB_PD_INITIAL_DRP_STATE};
+static volatile __maybe_unused enum pd_dual_role_states
+	drp_state[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+		[0 ...(CONFIG_USB_PD_PORT_MAX_COUNT - 1)] =
+			CONFIG_USB_PD_INITIAL_DRP_STATE
+	};
 
 static void set_vconn(int port, int enable);
 
@@ -450,10 +457,9 @@ static void set_vconn(int port, int enable);
 static __maybe_unused int reset_device_and_notify(int port);
 static __maybe_unused void check_drp_connection(const int port);
 static void sink_power_sub_states(int port);
+static void set_ccd_mode(int port, bool enable);
 
-#ifdef CONFIG_POWER_COMMON
-static void handle_new_power_state(int port);
-#endif /* CONFIG_POWER_COMMON */
+__maybe_unused static void handle_new_power_state(int port);
 
 static void pd_update_dual_role_config(int port);
 
@@ -461,19 +467,19 @@ static void pd_update_dual_role_config(int port);
 static void set_state_tc(const int port, const enum usb_tc_state new_state);
 test_export_static enum usb_tc_state get_state_tc(const int port);
 
-#ifdef CONFIG_USB_PD_TRY_SRC
 /* Enable variable for Try.SRC states */
-static uint32_t pd_try_src;
+static atomic_t pd_try_src;
 static volatile enum try_src_override_t pd_try_src_override;
 static void pd_update_try_source(void);
-#endif
 
 static void sink_stop_drawing_current(int port);
 
-static bool is_try_src_enabled(int port)
+__maybe_unused static bool is_try_src_enabled(int port)
 {
-	return IS_ENABLED(CONFIG_USB_PD_TRY_SRC) &&
-		((pd_try_src_override == TRY_SRC_OVERRIDE_ON) ||
+	if (!IS_ENABLED(CONFIG_USB_PD_TRY_SRC))
+		assert(0);
+
+	return ((pd_try_src_override == TRY_SRC_OVERRIDE_ON) ||
 		(pd_try_src_override == TRY_SRC_NO_OVERRIDE && pd_try_src));
 }
 
@@ -500,18 +506,60 @@ void pd_execute_hard_reset(int port)
 	/* DO NOTHING */
 }
 
-void pd_set_vbus_discharge(int port, int enable)
+__overridable void pd_set_vbus_discharge(int port, int enable)
 {
 	/* DO NOTHING */
 }
 
-uint16_t pd_get_identity_vid(int port)
+#endif /* !CONFIG_USB_PRL_SM */
+
+#ifndef CONFIG_USB_PE_SM
+
+/*
+ * These pd_ functions are implemented in the PE layer
+ */
+const uint32_t *const pd_get_src_caps(int port)
+{
+	return NULL;
+}
+
+uint8_t pd_get_src_cap_cnt(int port)
 {
-	/* DO NOTHING */
 	return 0;
 }
 
-#endif /* !CONFIG_USB_PRL_SM */
+const uint32_t *const pd_get_snk_caps(int port)
+{
+	return NULL;
+}
+
+uint8_t pd_get_snk_cap_cnt(int port)
+{
+	return 0;
+}
+
+void pd_set_src_caps(int port, int cnt, uint32_t *src_caps)
+{
+}
+
+int pd_get_rev(int port, enum tcpci_msg_type type)
+{
+	return PD_REV30;
+}
+
+#endif /* !CONFIG_USB_PR_SM */
+
+#ifndef CONFIG_AP_POWER_CONTROL
+__overridable enum pd_dual_role_states board_tc_get_initial_drp_mode(int port)
+{
+	/*
+	 * DRP state is typically adjusted as the chipset state is changed. For
+	 * projects which don't include an AP this function can be used for to
+	 * specify what the starting DRP state should be.
+	 */
+	return PD_DRP_FORCE_SINK;
+}
+#endif
 
 void pd_update_contract(int port)
 {
@@ -567,7 +615,7 @@ void tc_request_power_swap(int port)
 			TC_SET_FLAG(port, TC_FLAGS_PR_SWAP_IN_PROGRESS);
 
 			/* Let tc_pr_swap_complete start the Vbus debounce */
-			tc[port].vbus_debounce_time = TIMER_DISABLED;
+			pd_timer_disable(port, TC_TIMER_VBUS_DEBOUNCE);
 		}
 
 		/*
@@ -584,6 +632,26 @@ void tc_request_power_swap(int port)
 	}
 }
 
+/* Flag to indicate PD comm is disabled on init */
+static int pd_disabled_on_init;
+
+static void pd_update_pd_comm(void)
+{
+	int i;
+
+	/*
+	 * Some batteries take much longer time to report its SOC.
+	 * The init function disabled PD comm on startup. Need this
+	 * hook to enable PD comm when the battery level is enough.
+	 */
+	if (pd_disabled_on_init && pd_is_battery_capable()) {
+		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
+			pd_comm_enable(i, 1);
+		pd_disabled_on_init = 0;
+	}
+}
+DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, pd_update_pd_comm, HOOK_PRIO_DEFAULT);
+
 static bool pd_comm_allowed_by_policy(void)
 {
 	if (system_is_in_rw())
@@ -597,10 +665,15 @@ static bool pd_comm_allowed_by_policy(void)
 	 * when sysjump to RW that makes the device brownout on the dead-battery
 	 * case. Disable PD for this special case as a workaround.
 	 */
-	if (IS_ENABLED(CONFIG_SYSTEM_UNLOCKED) &&
-	    (IS_ENABLED(CONFIG_VBOOT_EFS2) ||
-	     usb_get_battery_soc() >= CONFIG_USB_PD_TRY_SRC_MIN_BATT_SOC))
-		return true;
+	if (!system_is_locked()) {
+		if (IS_ENABLED(CONFIG_VBOOT_EFS2))
+			return true;
+
+		if (pd_is_battery_capable())
+			return true;
+
+		pd_disabled_on_init = 1;
+	}
 
 	return false;
 }
@@ -608,11 +681,10 @@ static bool pd_comm_allowed_by_policy(void)
 static void tc_policy_pd_enable(int port, int en)
 {
 	if (en)
-		deprecated_atomic_clear_bits(&tc[port].pd_disabled_mask,
-					     PD_DISABLED_BY_POLICY);
+		atomic_clear_bits(&tc[port].pd_disabled_mask,
+				  PD_DISABLED_BY_POLICY);
 	else
-		deprecated_atomic_or(&tc[port].pd_disabled_mask,
-				     PD_DISABLED_BY_POLICY);
+		atomic_or(&tc[port].pd_disabled_mask, PD_DISABLED_BY_POLICY);
 
 	CPRINTS("C%d: PD comm policy %sabled", port, en ? "en" : "dis");
 }
@@ -620,31 +692,62 @@ static void tc_policy_pd_enable(int port, int en)
 static void tc_enable_pd(int port, int en)
 {
 	if (en)
-		deprecated_atomic_clear_bits(&tc[port].pd_disabled_mask,
-					     PD_DISABLED_NO_CONNECTION);
+		atomic_clear_bits(&tc[port].pd_disabled_mask,
+				  PD_DISABLED_NO_CONNECTION);
 	else
-		deprecated_atomic_or(&tc[port].pd_disabled_mask,
-				     PD_DISABLED_NO_CONNECTION);
+		atomic_or(&tc[port].pd_disabled_mask,
+			  PD_DISABLED_NO_CONNECTION);
 }
 
-static void tc_enable_try_src(int en)
+__maybe_unused static void tc_enable_try_src(int en)
 {
+	if (!IS_ENABLED(CONFIG_USB_PD_TRY_SRC))
+		assert(0);
+
 	if (en)
-		deprecated_atomic_or(&pd_try_src, 1);
+		atomic_or(&pd_try_src, 1);
 	else
-		deprecated_atomic_clear_bits(&pd_try_src, 1);
+		atomic_clear_bits(&pd_try_src, 1);
+}
+
+/*
+ * Exit all modes due to a detach event or hard reset
+ *
+ * Note: this skips the ExitMode VDM steps in the PE because it is assumed the
+ * partner is not present to receive them, and the PE will no longer be running,
+ * or we've forced an abrupt mode exit through a hard reset.
+ */
+static void tc_set_modes_exit(int port)
+{
+	if (IS_ENABLED(CONFIG_USB_PE_SM) &&
+	    IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP)) {
+		pd_dfp_exit_mode(port, TCPCI_MSG_SOP, 0, 0);
+		pd_dfp_exit_mode(port, TCPCI_MSG_SOP_PRIME, 0, 0);
+		pd_dfp_exit_mode(port, TCPCI_MSG_SOP_PRIME_PRIME, 0, 0);
+	}
 }
 
 static void tc_detached(int port)
 {
 	TC_CLR_FLAG(port, TC_FLAGS_TS_DTS_PARTNER);
 	hook_notify(HOOK_USB_PD_DISCONNECT);
+	tc_enable_pd(port, 0);
 	tc_pd_connection(port, 0);
 	tcpm_debug_accessory(port, 0);
+	set_ccd_mode(port, 0);
+	tc_set_modes_exit(port);
+	if (IS_ENABLED(CONFIG_USB_PRL_SM))
+		prl_set_default_pd_revision(port);
+
+	/* Clear any mux connection on detach */
+	if (IS_ENABLED(CONFIG_USBC_SS_MUX))
+		usb_mux_set(port, USB_PD_MUX_NONE, USB_SWITCH_DISCONNECT,
+			    tc[port].polarity);
 }
 
 static inline void pd_set_dual_role_and_event(int port,
-				enum pd_dual_role_states state, uint32_t event)
+					      enum pd_dual_role_states state,
+					      uint32_t event)
 {
 	drp_state[port] = state;
 
@@ -652,7 +755,7 @@ static inline void pd_set_dual_role_and_event(int port,
 		pd_update_try_source();
 
 	if (event != 0)
-		task_set_event(PD_PORT_TO_TASK_ID(port), event, 0);
+		task_set_event(PD_PORT_TO_TASK_ID(port), event);
 }
 
 void pd_set_dual_role(int port, enum pd_dual_role_states state)
@@ -660,12 +763,6 @@ void pd_set_dual_role(int port, enum pd_dual_role_states state)
 	pd_set_dual_role_and_event(port, state, PD_EVENT_UPDATE_DUAL_ROLE);
 }
 
-bool pd_get_partner_data_swap_capable(int port)
-{
-	/* return data swap capable status of port partner */
-	return !!TC_CHK_FLAG(port, TC_FLAGS_PARTNER_DR_DATA);
-}
-
 int pd_comm_is_enabled(int port)
 {
 	return tc_get_pd_enabled(port);
@@ -684,15 +781,6 @@ void pd_request_data_swap(int port)
 	}
 }
 
-/*
- * Return true if partner port is a DTS or TS capable of entering debug
- * mode (eg. is presenting Rp/Rp or Rd/Rd).
- */
-int pd_ts_dts_plugged(int port)
-{
-	return TC_CHK_FLAG(port, TC_FLAGS_TS_DTS_PARTNER);
-}
-
 /* Return true if partner port is known to be PD capable. */
 bool pd_capable(int port)
 {
@@ -700,12 +788,13 @@ bool pd_capable(int port)
 }
 
 /*
- * Return true if partner port is capable of communication over USB data
- * lines.
+ * Return true if we transition through Unattached.SNK, but we're still waiting
+ * to receive source caps from the partner. This indicates that the PD
+ * capabilities are not yet known.
  */
-bool pd_get_partner_usb_comm_capable(int port)
+bool pd_waiting_on_partner_src_caps(int port)
 {
-	return !!TC_CHK_FLAG(port, TC_FLAGS_PARTNER_USB_COMM);
+	return !pd_get_src_cap_cnt(port);
 }
 
 enum pd_dual_role_states pd_get_dual_role(int port)
@@ -713,19 +802,6 @@ enum pd_dual_role_states pd_get_dual_role(int port)
 	return drp_state[port];
 }
 
-#ifdef CONFIG_CMD_PD_DEV_DUMP_INFO
-static inline void pd_dev_dump_info(uint16_t dev_id, uint32_t *hash)
-{
-	int j;
-
-	ccprintf("DevId:%d.%d Hash:", HW_DEV_ID_MAJ(dev_id),
-		 HW_DEV_ID_MIN(dev_id));
-	for (j = 0; j < PD_RW_HASH_SIZE / 4; j++)
-		ccprintf(" %08x ", hash[i]);
-	ccprintf("\n");
-}
-#endif /* CONFIG_CMD_PD_DEV_DUMP_INFO */
-
 const char *tc_get_current_state(int port)
 {
 	if (IS_ENABLED(USB_PD_DEBUG_LABELS))
@@ -749,52 +825,41 @@ int tc_is_attached_snk(int port)
 	return IS_ATTACHED_SNK(port);
 }
 
-void tc_partner_dr_power(int port, int en)
+__overridable void tc_update_pd_sleep_mask(int port)
 {
-	if (en)
-		TC_SET_FLAG(port, TC_FLAGS_PARTNER_DR_POWER);
-	else
-		TC_CLR_FLAG(port, TC_FLAGS_PARTNER_DR_POWER);
-}
-
-void tc_partner_unconstrainedpower(int port, int en)
-{
-	if (en)
-		TC_SET_FLAG(port, TC_FLAGS_PARTNER_UNCONSTRAINED);
-	else
-		TC_CLR_FLAG(port, TC_FLAGS_PARTNER_UNCONSTRAINED);
-}
-
-void tc_partner_usb_comm(int port, int en)
-{
-	if (en)
-		TC_SET_FLAG(port, TC_FLAGS_PARTNER_USB_COMM);
-	else
-		TC_CLR_FLAG(port, TC_FLAGS_PARTNER_USB_COMM);
-}
-
-void tc_partner_dr_data(int port, int en)
-{
-	if (en)
-		TC_SET_FLAG(port, TC_FLAGS_PARTNER_DR_DATA);
-	else
-		TC_CLR_FLAG(port, TC_FLAGS_PARTNER_DR_DATA);
 }
 
 void tc_pd_connection(int port, int en)
 {
 	if (en) {
+		bool new_pd_capable = false;
+
+		if (!TC_CHK_FLAG(port, TC_FLAGS_PARTNER_PD_CAPABLE))
+			new_pd_capable = true;
+
 		TC_SET_FLAG(port, TC_FLAGS_PARTNER_PD_CAPABLE);
 		/* If a PD device is attached then disable deep sleep */
 		if (IS_ENABLED(CONFIG_LOW_POWER_IDLE) &&
-		    !IS_ENABLED(CONFIG_USB_PD_TCPC_ON_CHIP)) {
+		    IS_ENABLED(CONFIG_USB_PD_TCPC_ON_CHIP))
+			tc_update_pd_sleep_mask(port);
+		else if (IS_ENABLED(CONFIG_LOW_POWER_IDLE))
 			disable_sleep(SLEEP_MASK_USB_PD);
-		}
+
+		/*
+		 * Update the mux state, only when the PD capable flag
+		 * transitions from 0 to 1. This ensures that PD charger
+		 * devices, without data capability are not marked as having
+		 * USB.
+		 */
+		if (new_pd_capable)
+			set_usb_mux_with_current_data_role(port);
 	} else {
 		TC_CLR_FLAG(port, TC_FLAGS_PARTNER_PD_CAPABLE);
 		/* If a PD device isn't attached then enable deep sleep */
 		if (IS_ENABLED(CONFIG_LOW_POWER_IDLE) &&
-		    !IS_ENABLED(CONFIG_USB_PD_TCPC_ON_CHIP)) {
+		    IS_ENABLED(CONFIG_USB_PD_TCPC_ON_CHIP))
+			tc_update_pd_sleep_mask(port);
+		else if (IS_ENABLED(CONFIG_LOW_POWER_IDLE)) {
 			int i;
 
 			/* If all ports are not connected, allow the sleep */
@@ -820,14 +885,13 @@ void pd_try_vconn_src(int port)
 
 int tc_check_vconn_swap(int port)
 {
-#ifdef CONFIG_USBC_VCONN
-	if (TC_CHK_FLAG(port, TC_FLAGS_REJECT_VCONN_SWAP))
-		return 0;
+	if (IS_ENABLED(CONFIG_USBC_VCONN)) {
+		if (TC_CHK_FLAG(port, TC_FLAGS_REJECT_VCONN_SWAP))
+			return 0;
 
-	return pd_check_vconn_swap(port);
-#else
-	return 0;
-#endif
+		return pd_check_vconn_swap(port);
+	} else
+		return 0;
 }
 
 void tc_pr_swap_complete(int port, bool success)
@@ -841,7 +905,7 @@ void tc_pr_swap_complete(int port, bool success)
 		 * Note: Swap in progress should not be cleared until the
 		 * debounce is completed.
 		 */
-		tc[port].vbus_debounce_time = get_time().val + PD_T_DEBOUNCE;
+		pd_timer_enable(port, TC_TIMER_VBUS_DEBOUNCE, PD_T_DEBOUNCE);
 	} else {
 		/* PR Swap is no longer in progress */
 		TC_CLR_FLAG(port, TC_FLAGS_PR_SWAP_IN_PROGRESS);
@@ -908,18 +972,11 @@ void tc_hard_reset_request(int port)
 	task_wake(PD_PORT_TO_TASK_ID(port));
 }
 
-void tc_disc_ident_in_progress(int port)
-{
-	TC_SET_FLAG(port, TC_FLAGS_DISC_IDENT_IN_PROGRESS);
-}
-
-void tc_disc_ident_complete(int port)
-{
-	TC_CLR_FLAG(port, TC_FLAGS_DISC_IDENT_IN_PROGRESS);
-}
-
 void tc_try_src_override(enum try_src_override_t ov)
 {
+	if (!IS_ENABLED(CONFIG_USB_PD_TRY_SRC))
+		assert(0);
+
 	if (IS_ENABLED(CONFIG_USB_PD_TRY_SRC)) {
 		switch (ov) {
 		case TRY_SRC_OVERRIDE_OFF: /* 0 */
@@ -936,6 +993,9 @@ void tc_try_src_override(enum try_src_override_t ov)
 
 enum try_src_override_t tc_get_try_src_override(void)
 {
+	if (!IS_ENABLED(CONFIG_USB_PD_TRY_SRC))
+		assert(0);
+
 	return pd_try_src_override;
 }
 
@@ -949,6 +1009,15 @@ void tc_snk_power_off(int port)
 
 int tc_src_power_on(int port)
 {
+	/*
+	 * Check our OC event counter.  If we've exceeded our threshold, then
+	 * let's latch our source path off to prevent continuous cycling.  When
+	 * the PD state machine detects a disconnection on the CC lines, we will
+	 * reset our OC event counter.
+	 */
+	if (IS_ENABLED(CONFIG_USBC_OCP) && usbc_ocp_is_port_latched_off(port))
+		return EC_ERROR_ACCESS_DENIED;
+
 	if (IS_ATTACHED_SRC(port))
 		return pd_set_power_supply_ready(port);
 
@@ -965,14 +1034,37 @@ void tc_src_power_off(int port)
 					CHARGE_CEIL_NONE);
 }
 
+enum ocp_action {
+	OCP_CLEAR,
+	OCP_NO_ACTION,
+};
+
+/* Set what role the partner is right now, for the PPC and OCP module */
+static void tc_set_partner_role(int port, enum ppc_device_role role,
+				enum ocp_action ocp_command)
+{
+	if (IS_ENABLED(CONFIG_USBC_PPC))
+		ppc_dev_is_connected(port, role);
+
+	if (IS_ENABLED(CONFIG_USBC_OCP)) {
+		usbc_ocp_snk_is_connected(port, role == PPC_DEV_SNK);
+		/*
+		 * Clear the overcurrent event counter
+		 * if we're not in ErrorRecovery due to OCP
+		 */
+		if (ocp_command == OCP_CLEAR)
+			usbc_ocp_clear_event_counter(port);
+	}
+}
+
 /*
  * Depending on the load on the processor and the tasks running
  * it can take a while for the task associated with this port
  * to run.  So build in 1ms delays, for up to 300ms, to wait for
  * the suspend to actually happen.
  */
-#define SUSPEND_SLEEP_DELAY	1
-#define SUSPEND_SLEEP_RETRIES	300
+#define SUSPEND_SLEEP_DELAY 1
+#define SUSPEND_SLEEP_RETRIES 300
 
 void pd_set_suspend(int port, int suspend)
 {
@@ -983,7 +1075,7 @@ void pd_set_suspend(int port, int suspend)
 	if (suspend) {
 		int wait = 0;
 
-		TC_SET_FLAG(port, TC_FLAGS_SUSPEND);
+		TC_SET_FLAG(port, TC_FLAGS_REQUEST_SUSPEND);
 
 		/*
 		 * Avoid deadlock when running from task
@@ -997,21 +1089,31 @@ void pd_set_suspend(int port, int suspend)
 		/* Sleep this task if we are not suspended */
 		while (pd_is_port_enabled(port)) {
 			if (++wait > SUSPEND_SLEEP_RETRIES) {
-				CPRINTS("C%d: NOT SUSPENDED after %dms",
-					port, wait * SUSPEND_SLEEP_DELAY);
+				CPRINTS("C%d: NOT SUSPENDED after %dms", port,
+					wait * SUSPEND_SLEEP_DELAY);
 				return;
 			}
 			msleep(SUSPEND_SLEEP_DELAY);
 		}
 	} else {
-		TC_CLR_FLAG(port, TC_FLAGS_SUSPEND);
+		TC_CLR_FLAG(port, TC_FLAGS_REQUEST_SUSPEND);
 		task_wake(PD_PORT_TO_TASK_ID(port));
 	}
 }
 
+void pd_set_error_recovery(int port)
+{
+	TC_SET_FLAG(port, TC_FLAGS_REQUEST_ERROR_RECOVERY);
+}
+
 int pd_is_port_enabled(int port)
 {
-	return get_state_tc(port) != TC_DISABLED;
+	/*
+	 * Checking get_state_tc(port) from another task isn't safe since it
+	 * can return TC_DISABLED before tc_cc_open_entry and tc_disabled_entry
+	 * are complete. So check TC_FLAGS_SUSPENDED instead.
+	 */
+	return !TC_CHK_FLAG(port, TC_FLAGS_SUSPENDED);
 }
 
 int pd_fetch_acc_log_entry(int port)
@@ -1052,16 +1154,6 @@ bool pd_get_vconn_state(int port)
 	return !!TC_CHK_FLAG(port, TC_FLAGS_VCONN_ON);
 }
 
-bool pd_get_partner_dual_role_power(int port)
-{
-	return !!TC_CHK_FLAG(port, TC_FLAGS_PARTNER_DR_POWER);
-}
-
-bool pd_get_partner_unconstr_power(int port)
-{
-	return !!TC_CHK_FLAG(port, TC_FLAGS_PARTNER_UNCONSTRAINED);
-}
-
 const char *pd_get_task_state_name(int port)
 {
 	return tc_get_current_state(port);
@@ -1075,9 +1167,9 @@ void pd_vbus_low(int port)
 int pd_is_connected(int port)
 {
 	return (IS_ATTACHED_SRC(port) ||
-#ifdef CONFIG_USB_PE_SM
-		(get_state_tc(port) == TC_CT_ATTACHED_SNK) ||
-#endif
+		(IS_ENABLED(CONFIG_USB_PE_SM) &&
+		 ((get_state_tc(port) == TC_CT_UNATTACHED_SNK) ||
+		  (get_state_tc(port) == TC_CT_ATTACHED_SNK))) ||
 		IS_ATTACHED_SNK(port));
 }
 
@@ -1086,18 +1178,73 @@ bool pd_is_disconnected(int port)
 	return !pd_is_connected(port);
 }
 
-static __maybe_unused void bc12_role_change_handler(int port)
+/*
+ * PD functions which query our fixed PDO flags.  Both the source and sink
+ * capabilities can present these values, and they should match between the two
+ * for compliant partners.
+ */
+static bool pd_check_fixed_flag(int port, uint32_t flag)
+{
+	uint32_t fixed_pdo;
+
+	if (pd_get_src_cap_cnt(port) != 0)
+		fixed_pdo = *pd_get_src_caps(port);
+	else if (pd_get_snk_cap_cnt(port) != 0)
+		fixed_pdo = *pd_get_snk_caps(port);
+	else
+		return false;
+
+	/*
+	 * Error check that first PDO is fixed, as 6.4.1 Capabilities requires
+	 * in the Power Delivery Specification.
+	 * "The vSafe5V Fixed Supply Object Shall always be the first object"
+	 */
+	if ((fixed_pdo & PDO_TYPE_MASK) != PDO_TYPE_FIXED)
+		return false;
+
+	return fixed_pdo & flag;
+}
+
+bool pd_get_partner_data_swap_capable(int port)
+{
+	return pd_check_fixed_flag(port, PDO_FIXED_DATA_SWAP);
+}
+
+bool pd_get_partner_usb_comm_capable(int port)
 {
-	int event;
-	int task_id = USB_CHG_PORT_TO_TASK_ID(port);
+	return pd_check_fixed_flag(port, PDO_FIXED_COMM_CAP);
+}
+
+bool pd_get_partner_dual_role_power(int port)
+{
+	return pd_check_fixed_flag(port, PDO_FIXED_DUAL_ROLE);
+}
+
+bool pd_get_partner_unconstr_power(int port)
+{
+	return pd_check_fixed_flag(port, PDO_FIXED_UNCONSTRAINED);
+}
+
+static void bc12_role_change_handler(int port, enum pd_data_role prev_data_role,
+				     enum pd_data_role data_role)
+{
+	int event = 0;
+	bool role_changed = (data_role != prev_data_role);
+
+	if (!IS_ENABLED(CONFIG_BC12_DETECT_DATA_ROLE_TRIGGER))
+		return;
 
 	/* Get the data role of our device */
-	switch (pd_get_data_role(port)) {
+	switch (data_role) {
 	case PD_ROLE_UFP:
-		event = USB_CHG_EVENT_DR_UFP;
+		/* Only trigger BC12 detection on a role change */
+		if (role_changed)
+			event = USB_CHG_EVENT_DR_UFP;
 		break;
 	case PD_ROLE_DFP:
-		event = USB_CHG_EVENT_DR_DFP;
+		/* Only trigger BC12 host mode on a role change */
+		if (role_changed)
+			event = USB_CHG_EVENT_DR_DFP;
 		break;
 	case PD_ROLE_DISCONNECTED:
 		event = USB_CHG_EVENT_CC_OPEN;
@@ -1105,7 +1252,9 @@ static __maybe_unused void bc12_role_change_handler(int port)
 	default:
 		return;
 	}
-	task_set_event(task_id, event, 0);
+
+	if (event)
+		usb_charger_task_set_event(port, event);
 }
 
 /*
@@ -1118,6 +1267,17 @@ static void typec_select_pull(int port, enum tcpc_cc_pull pull)
 void typec_select_src_current_limit_rp(int port, enum tcpc_rp_value rp)
 {
 	tc[port].select_current_limit_rp = rp;
+	if (IS_ATTACHED_SRC(port))
+		TC_SET_FLAG(port, TC_FLAGS_UPDATE_CURRENT);
+}
+__overridable int typec_get_default_current_limit_rp(int port)
+{
+	int rp = CONFIG_USB_PD_PULLUP;
+
+	if (pd_get_bist_share_mode())
+		rp = TYPEC_RP_3A0;
+
+	return rp;
 }
 void typec_select_src_collision_rp(int port, enum tcpc_rp_value rp)
 {
@@ -1126,8 +1286,7 @@ void typec_select_src_collision_rp(int port, enum tcpc_rp_value rp)
 static enum tcpc_rp_value typec_get_active_select_rp(int port)
 {
 	/* Explicit contract will use the collision Rp */
-	if (IS_ENABLED(CONFIG_USB_PD_REV30) &&
-	    pe_is_explicit_contract(port))
+	if (IS_ENABLED(CONFIG_USB_PD_REV30) && pe_is_explicit_contract(port))
 		return tc[port].select_collision_rp;
 	return tc[port].select_current_limit_rp;
 }
@@ -1163,8 +1322,15 @@ static bool tc_perform_src_hard_reset(int port)
 		/* Set role to DFP */
 		tc_set_data_role(port, PD_ROLE_DFP);
 
+		/*
+		 * USB PD Rev 3.0 Ver 2.0 6.8.3.2: "A Hard Reset Shall cause
+		 * all Active Modes to be exited by both Port Partners and any
+		 * Cable Plugs"
+		 */
+		tc_set_modes_exit(port);
+
 		tc[port].ps_reset_state = PS_STATE1;
-		tc[port].timeout = get_time().val + PD_T_SRC_RECOVER;
+		pd_timer_enable(port, TC_TIMER_TIMEOUT, PD_T_SRC_RECOVER);
 		return false;
 	case PS_STATE1:
 		/* Enable VBUS */
@@ -1177,8 +1343,8 @@ static bool tc_perform_src_hard_reset(int port)
 		set_vconn(port, 1);
 
 		tc[port].ps_reset_state = PS_STATE2;
-		tc[port].timeout = get_time().val +
-				PD_POWER_SUPPLY_TURN_ON_DELAY;
+		pd_timer_enable(port, TC_TIMER_TIMEOUT,
+				PD_POWER_SUPPLY_TURN_ON_DELAY);
 		return false;
 	case PS_STATE2:
 		/* Tell Policy Engine Hard Reset is complete */
@@ -1204,39 +1370,64 @@ static bool tc_perform_snk_hard_reset(int port)
 {
 	switch (tc[port].ps_reset_state) {
 	case PS_STATE0:
-		/* Shutting off power, Disable AutoDischargeDisconnect */
-		tcpm_enable_auto_discharge_disconnect(port, 0);
-
 		/* Hard reset sets us back to default data role */
 		tc_set_data_role(port, PD_ROLE_UFP);
 
-		/* Clear the input current limit */
-		sink_stop_drawing_current(port);
+		/*
+		 * USB PD Rev 3.0 Ver 2.0 6.8.3.2: "A Hard Reset Shall cause
+		 * all Active Modes to be exited by both Port Partners and any
+		 * Cable Plugs"
+		 */
+		tc_set_modes_exit(port);
 
 		/*
 		 * When VCONN is supported, the Hard Reset Shall cause
 		 * the Port with the Rd resistor asserted to turn off
 		 * VCONN.
 		 */
-#ifdef CONFIG_USBC_VCONN
-		if (TC_CHK_FLAG(port, TC_FLAGS_VCONN_ON))
+		if (IS_ENABLED(CONFIG_USBC_VCONN) &&
+		    TC_CHK_FLAG(port, TC_FLAGS_VCONN_ON))
 			set_vconn(port, 0);
-#endif
-		/* Wait tSafe0V + tSrcRecover, then check for Vbus presence */
+
+		/* Wait up to tVSafe0V for Vbus to disappear */
 		tc[port].ps_reset_state = PS_STATE1;
-		tc[port].timeout = get_time().val + PD_T_SAFE_0V +
-							PD_T_SRC_RECOVER_MAX;
+		pd_timer_enable(port, TC_TIMER_TIMEOUT, PD_T_SAFE_0V);
 		return false;
 	case PS_STATE1:
-		if (get_time().val < tc[port].timeout)
-			return false;
+		if (pd_check_vbus_level(port, VBUS_SAFE0V)) {
+			/*
+			 * Partner dropped Vbus, reduce our current consumption
+			 * and await its return.
+			 */
+			sink_stop_drawing_current(port);
 
-		/* Watch for Vbus to return */
-		tc[port].ps_reset_state = PS_STATE2;
-		tc[port].timeout = get_time().val + PD_T_SRC_TURN_ON;
+			tcpm_enable_auto_discharge_disconnect(port, 0);
+
+			/* Move on to waiting for the return of Vbus */
+			tc[port].ps_reset_state = PS_STATE2;
+			pd_timer_enable(port, TC_TIMER_TIMEOUT,
+					PD_T_SRC_RECOVER_MAX +
+						PD_T_SRC_TURN_ON);
+		}
+
+		if (pd_timer_is_expired(port, TC_TIMER_TIMEOUT)) {
+			/*
+			 * No Vbus drop likely indicates a non-PD port partner,
+			 * move to the next stage anyway.
+			 */
+			tc[port].ps_reset_state = PS_STATE2;
+			pd_timer_enable(port, TC_TIMER_TIMEOUT,
+					PD_T_SRC_RECOVER_MAX +
+						PD_T_SRC_TURN_ON);
+		}
 		return false;
 	case PS_STATE2:
-		if (pd_is_vbus_present(port)) {
+		/*
+		 * Look for the voltage to be above disconnect.  Since we didn't
+		 * drop our draw on non-PD partners, they may have dipped below
+		 * vSafe5V but still be in a valid connected voltage.
+		 */
+		if (!pd_check_vbus_level(port, VBUS_REMOVED)) {
 			/*
 			 * Inform policy engine that power supply
 			 * reset is complete
@@ -1254,7 +1445,7 @@ static bool tc_perform_snk_hard_reset(int port)
 			 * now, such that we'll actually reset the correct input
 			 * current limit.
 			 */
-			tc[port].cc_debounce = get_time().val;
+			pd_timer_enable(port, TC_TIMER_CC_DEBOUNCE, 0);
 			sink_power_sub_states(port);
 
 			/* Power is back, Enable AutoDischargeDisconnect */
@@ -1264,7 +1455,7 @@ static bool tc_perform_snk_hard_reset(int port)
 		/*
 		 * If Vbus isn't back after wait + tSrcTurnOn, go unattached
 		 */
-		if (get_time().val > tc[port].timeout) {
+		if (pd_timer_is_expired(port, TC_TIMER_TIMEOUT)) {
 			tc[port].ps_reset_state = PS_STATE0;
 			set_state_tc(port, TC_UNATTACHED_SNK);
 			return true;
@@ -1301,7 +1492,8 @@ static void restart_tc_sm(int port, enum usb_tc_state start_state)
 	 * Update the Rp Value. We don't need to update CC lines though as that
 	 * happens in below set_state transition.
 	 */
-	typec_select_src_current_limit_rp(port, CONFIG_USB_PD_PULLUP);
+	typec_select_src_current_limit_rp(
+		port, typec_get_default_current_limit_rp(port));
 
 	/* Disable if restart failed, otherwise start in default state. */
 	set_state_tc(port, res ? TC_DISABLED : start_state);
@@ -1322,12 +1514,31 @@ static void restart_tc_sm(int port, enum usb_tc_state start_state)
 	}
 
 	if (IS_ENABLED(CONFIG_CHARGE_MANAGER)) {
-		/* Initialize PD and type-C supplier current limits to 0 */
+		/*
+		 * Only initialize PD supplier current limit to 0.
+		 * Defer initializing type-C supplier current limit
+		 * to Unattached.SNK or Attached.SNK.
+		 */
 		pd_set_input_current_limit(port, 0, 0);
-		typec_set_input_current_limit(port, 0, 0);
 		charge_manager_update_dualrole(port, CAP_UNKNOWN);
 	}
 
+	/*
+	 * PD r3.0 v2.0, ss6.2.1.1.5:
+	 * After a physical or logical (USB Type-C Error Recovery) Attach, a
+	 * Port discovers the common Specification Revision level between itself
+	 * and its Port Partner and/or the Cable Plug(s), and uses this
+	 * Specification Revision level until a Detach, Hard Reset or Error
+	 * Recovery happens.
+	 *
+	 * This covers the Error Recovery case, because TC_ERROR_RECOVERY
+	 * reinitializes the TC state machine. This also covers the implicit
+	 * case when PD is suspended and resumed or when the state machine is
+	 * first initialized.
+	 */
+	if (IS_ENABLED(CONFIG_USB_PRL_SM))
+		prl_set_default_pd_revision(port);
+
 #ifdef CONFIG_USB_PE_SM
 	tc_enable_pd(port, 0);
 	tc[port].ps_reset_state = PS_STATE0;
@@ -1338,39 +1549,51 @@ void tc_state_init(int port)
 {
 	enum usb_tc_state first_state;
 
+	if (port >= CONFIG_USB_PD_PORT_MAX_COUNT)
+		return;
+
 	/* For test builds, replicate static initialization */
 	if (IS_ENABLED(TEST_BUILD)) {
-		int i;
-
-		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; ++i) {
-			memset(&tc[i], 0, sizeof(tc[i]));
-			drp_state[i] = CONFIG_USB_PD_INITIAL_DRP_STATE;
-		}
+		memset(&tc[port], 0, sizeof(tc[port]));
+		drp_state[port] = CONFIG_USB_PD_INITIAL_DRP_STATE;
 	}
 
 	/* If port is not available, there is nothing to initialize */
 	if (port >= board_get_usb_pd_port_count()) {
 		tc_enable_pd(port, 0);
-		tc_pause_event_loop(port);
-		TC_SET_FLAG(port, TC_FLAGS_SUSPEND);
+		TC_SET_FLAG(port, TC_FLAGS_REQUEST_SUSPEND);
 		return;
 	}
 
 	/* Allow system to set try src enable */
-	tc_try_src_override(TRY_SRC_NO_OVERRIDE);
+	if (IS_ENABLED(CONFIG_USB_PD_TRY_SRC))
+		tc_try_src_override(TRY_SRC_NO_OVERRIDE);
 
 	/*
 	 * Set initial PD communication policy.
 	 */
 	tc_policy_pd_enable(port, pd_comm_allowed_by_policy());
 
+#ifdef CONFIG_AP_POWER_CONTROL
 	/* Set dual-role state based on chipset power state */
 	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
 		pd_set_dual_role_and_event(port, PD_DRP_FORCE_SINK, 0);
 	else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-		pd_set_dual_role_and_event(port, pd_get_drp_state_in_suspend(), 0);
+		pd_set_dual_role_and_event(port, pd_get_drp_state_in_suspend(),
+					   0);
 	else /* CHIPSET_STATE_ON */
-		pd_set_dual_role_and_event(port, PD_DRP_TOGGLE_ON, 0);
+		pd_set_dual_role_and_event(port, pd_get_drp_state_in_s0(), 0);
+#else
+	pd_set_dual_role_and_event(port, board_tc_get_initial_drp_mode(port),
+				   0);
+#endif
+
+	/*
+	 * We are going to apply CC open (start with ErrorRecovery state)
+	 * unless there is something which forbids us to do that (one of
+	 * conditions below is true)
+	 */
+	first_state = TC_ERROR_RECOVERY;
 
 	/*
 	 * If we just lost power, don't apply CC open. Otherwise we would boot
@@ -1380,12 +1603,28 @@ void tc_state_init(int port)
 	if (system_get_reset_flags() &
 	    (EC_RESET_FLAG_BROWNOUT | EC_RESET_FLAG_POWER_ON)) {
 		first_state = TC_UNATTACHED_SNK;
+	}
+
+	/*
+	 * If this is non-EFS2 device, battery is not present or at some minimum
+	 * voltage and EC RO doesn't keep power-on reset flag after reset caused
+	 * by H1, then don't apply CC open because it will cause brown out.
+	 *
+	 * Please note that we are checking if CONFIG_BOARD_RESET_AFTER_POWER_ON
+	 * is defined now, but actually we need to know if it was enabled in
+	 * EC RO! It was assumed that if CONFIG_BOARD_RESET_AFTER_POWER_ON is
+	 * defined now it was defined in EC RO too.
+	 */
+	if (!IS_ENABLED(CONFIG_BOARD_RESET_AFTER_POWER_ON) &&
+	    !IS_ENABLED(CONFIG_VBOOT_EFS2) && IS_ENABLED(CONFIG_BATTERY) &&
+	    !pd_is_battery_capable()) {
+		first_state = TC_UNATTACHED_SNK;
+	}
 
+	if (first_state == TC_UNATTACHED_SNK) {
 		/* Turn off any previous sourcing */
 		tc_src_power_off(port);
 		set_vconn(port, 0);
-	} else {
-		first_state = TC_ERROR_RECOVERY;
 	}
 
 #ifdef CONFIG_USB_PD_TCPC_BOARD_INIT
@@ -1438,6 +1677,17 @@ void tc_set_power_role(int port, enum pd_power_role role)
  * Private Functions
  */
 
+/* Set GPIO_CCD_MODE_ODL gpio */
+static void set_ccd_mode(const int port, const bool enable)
+{
+	if (IS_ENABLED(CONFIG_ASSERT_CCD_MODE_ON_DTS_CONNECT) &&
+	    port == CONFIG_CCD_USBC_PORT_NUMBER) {
+		if (enable)
+			CPRINTS("Asserting GPIO_CCD_MODE_ODL");
+		gpio_set_level(_GPIO_CCD_MODE_ODL, !enable);
+	}
+}
+
 /* Set the TypeC state machine to a new state. */
 static void set_state_tc(const int port, const enum usb_tc_state new_state)
 {
@@ -1449,7 +1699,11 @@ static void set_state_tc(const int port, const enum usb_tc_state new_state)
 /* Get the current TypeC state. */
 test_export_static enum usb_tc_state get_state_tc(const int port)
 {
-	return tc[port].ctx.current - &tc_states[0];
+	/* Default to returning TC_STATE_COUNT if no state has been set */
+	if (tc[port].ctx.current == NULL)
+		return TC_STATE_COUNT;
+	else
+		return tc[port].ctx.current - &tc_states[0];
 }
 
 /* Get the previous TypeC state. */
@@ -1463,19 +1717,24 @@ static void print_current_state(const int port)
 	if (IS_ENABLED(USB_PD_DEBUG_LABELS))
 		CPRINTS_L1("C%d: %s", port, tc_state_names[get_state_tc(port)]);
 	else
-		CPRINTS("C%d: tc-st%d", port, get_state_tc(port));
+		CPRINTS_L1("C%d: tc-st%d", port, get_state_tc(port));
 }
 
 static void handle_device_access(int port)
 {
-	tc[port].low_power_time = get_time().val + PD_LPM_DEBOUNCE_US;
+	if (IS_ENABLED(CONFIG_USB_PD_TCPC_LOW_POWER) &&
+	    get_state_tc(port) == TC_LOW_POWER_MODE) {
+		tc_start_event_loop(port);
+		pd_timer_enable(port, TC_TIMER_LOW_POWER_TIME,
+				PD_LPM_DEBOUNCE_US);
+	}
 }
 
 void tc_event_check(int port, int evt)
 {
 #ifdef DEBUG_PRINT_FLAG_AND_EVENT_NAMES
 	if (evt != TASK_EVENT_TIMER)
-		print_bits("Event", evt, event_bit_names,
+		print_bits(port, "Event", evt, event_bit_names,
 			   ARRAY_SIZE(event_bit_names));
 #endif
 
@@ -1491,36 +1750,38 @@ void tc_event_check(int port, int evt)
 	if (evt & PD_EVENT_RX_HARD_RESET)
 		pd_execute_hard_reset(port);
 
-	if (evt & PD_EVENT_SEND_HARD_RESET)
-		tc_hard_reset_request(port);
+	if (evt & PD_EVENT_SEND_HARD_RESET) {
+		/* Pass Hard Reset request to PE layer if available */
+		if (IS_ENABLED(CONFIG_USB_PE_SM) && tc_get_pd_enabled(port))
+			pd_dpm_request(port, DPM_REQUEST_HARD_RESET_SEND);
+	}
 
-#ifdef CONFIG_POWER_COMMON
-	if (IS_ENABLED(CONFIG_POWER_COMMON)) {
+	if (IS_ENABLED(CONFIG_AP_POWER_CONTROL)) {
 		if (evt & PD_EVENT_POWER_STATE_CHANGE)
 			handle_new_power_state(port);
 	}
-#endif /* CONFIG_POWER_COMMON */
 
-#ifdef CONFIG_USB_PD_ALT_MODE_DFP
-	{
+	if (IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP)) {
 		int i;
 
-		if (IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP)) {
-			/*
-			 * Notify all ports of sysjump
-			 */
-			if (evt & PD_EVENT_SYSJUMP) {
-				for (i = 0; i <
-					CONFIG_USB_PD_PORT_MAX_COUNT; i++)
-					dpm_set_mode_exit_request(i);
-				notify_sysjump_ready();
-			}
+		/*
+		 * Notify all ports of sysjump
+		 */
+		if (evt & PD_EVENT_SYSJUMP) {
+			for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
+				dpm_set_mode_exit_request(i);
+			notify_sysjump_ready();
 		}
 	}
-#endif
 
-	if (evt & PD_EVENT_UPDATE_DUAL_ROLE)
+	if (evt & PD_EVENT_UPDATE_DUAL_ROLE) {
+		/* If TCPC is idle, start the wake process */
+		if (IS_ENABLED(CONFIG_USB_PD_TCPC_LOW_POWER) &&
+		    get_state_tc(port) == TC_LOW_POWER_MODE)
+			tcpm_wake_low_power_mode(port);
+
 		pd_update_dual_role_config(port);
+	}
 }
 
 /*
@@ -1538,6 +1799,9 @@ void tc_event_check(int port, int evt)
 
 void tc_set_data_role(int port, enum pd_data_role role)
 {
+	enum pd_data_role prev_data_role;
+
+	prev_data_role = tc[port].data_role;
 	tc[port].data_role = role;
 
 	if (IS_ENABLED(CONFIG_USBC_SS_MUX))
@@ -1554,8 +1818,7 @@ void tc_set_data_role(int port, enum pd_data_role role)
 	 * instead of VBUS changes, need to set an event to wake up the USB_CHG
 	 * task and indicate the current data role.
 	 */
-	if (IS_ENABLED(CONFIG_BC12_DETECT_DATA_ROLE_TRIGGER))
-		bc12_role_change_handler(port);
+	bc12_role_change_handler(port, prev_data_role, tc[port].data_role);
 
 	/* Notify TCPC of role update */
 	tcpm_set_msg_header(port, tc[port].power_role, tc[port].data_role);
@@ -1567,18 +1830,18 @@ static void sink_stop_drawing_current(int port)
 
 	if (IS_ENABLED(CONFIG_CHARGE_MANAGER)) {
 		typec_set_input_current_limit(port, 0, 0);
-		charge_manager_set_ceil(port,
-				CEIL_REQUESTOR_PD, CHARGE_CEIL_NONE);
+		charge_manager_set_ceil(port, CEIL_REQUESTOR_PD,
+					CHARGE_CEIL_NONE);
 	}
 }
 
-#ifdef CONFIG_USB_PD_TRY_SRC
 static void pd_update_try_source(void)
 {
+#ifdef CONFIG_USB_PD_TRY_SRC
 	tc_enable_try_src(pd_is_try_source_capable());
+#endif
 }
 DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, pd_update_try_source, HOOK_PRIO_DEFAULT);
-#endif /* CONFIG_USB_PD_TRY_SRC */
 
 static void set_vconn(int port, int enable)
 {
@@ -1587,43 +1850,24 @@ static void set_vconn(int port, int enable)
 	else
 		TC_CLR_FLAG(port, TC_FLAGS_VCONN_ON);
 
-	/*
-	 * Disable PPC Vconn first then TCPC in case the voltage feeds back
-	 * to TCPC and damages.
-	 */
-	if (IS_ENABLED(CONFIG_USBC_PPC_VCONN) && !enable)
-		ppc_set_vconn(port, 0);
-
-	/*
-	 * We always need to tell the TCPC to enable Vconn first, otherwise some
-	 * TCPCs get confused and think the CC line is in over voltage mode and
-	 * immediately disconnects. If there is a PPC, both devices will
-	 * potentially source Vconn, but that should be okay since Vconn has
-	 * "make before break" electrical requirements when swapping anyway.
-	 */
-	tcpm_set_vconn(port, enable);
-
-	if (IS_ENABLED(CONFIG_USBC_PPC_VCONN) && enable)
-		ppc_set_vconn(port, 1);
+	typec_set_vconn(port, enable);
 }
 
 /* This must only be called from the PD task */
 static void pd_update_dual_role_config(int port)
 {
 	if (tc[port].power_role == PD_ROLE_SOURCE &&
-			((drp_state[port] == PD_DRP_FORCE_SINK &&
-			!pd_ts_dts_plugged(port)) ||
-			(drp_state[port] == PD_DRP_TOGGLE_OFF &&
-			get_state_tc(port) == TC_UNATTACHED_SRC))) {
+	    (drp_state[port] == PD_DRP_FORCE_SINK ||
+	     (drp_state[port] == PD_DRP_TOGGLE_OFF &&
+	      get_state_tc(port) == TC_UNATTACHED_SRC))) {
 		/*
 		 * Change to sink if port is currently a source AND (new DRP
-		 * state is force sink OR new DRP state is either toggle off
-		 * or debug accessory toggle only and we are in the source
-		 * disconnected state).
+		 * state is force sink OR new DRP state is toggle off and we are
+		 * in the source disconnected state).
 		 */
 		set_state_tc(port, TC_UNATTACHED_SNK);
 	} else if (tc[port].power_role == PD_ROLE_SINK &&
-			drp_state[port] == PD_DRP_FORCE_SOURCE) {
+		   drp_state[port] == PD_DRP_FORCE_SOURCE) {
 		/*
 		 * Change to source if port is currently a sink and the
 		 * new DRP state is force source.
@@ -1632,56 +1876,54 @@ static void pd_update_dual_role_config(int port)
 	}
 }
 
-#ifdef CONFIG_POWER_COMMON
-static void handle_new_power_state(int port)
+__maybe_unused static void handle_new_power_state(int port)
 {
-	if (IS_ENABLED(CONFIG_POWER_COMMON) &&
+	if (!IS_ENABLED(CONFIG_AP_POWER_CONTROL))
+		assert(0);
+
+	if (IS_ENABLED(CONFIG_AP_POWER_CONTROL) &&
 	    IS_ENABLED(CONFIG_USB_PE_SM)) {
 		if (chipset_in_or_transitioning_to_state(
-					CHIPSET_STATE_ANY_OFF)) {
+			    CHIPSET_STATE_ANY_OFF)) {
 			/*
 			 * The SoC will negotiate alternate mode again when it
 			 * boots up
 			 */
 			dpm_set_mode_exit_request(port);
-
-			/*
-			 * The following function will disconnect both USB and
-			 * DP mux, as the chipset is transitioning to OFF.
-			 */
-			set_usb_mux_with_current_data_role(port);
 		}
 	}
-}
-#endif /* CONFIG_POWER_COMMON */
 
-#if defined(CONFIG_USB_PD_ALT_MODE) && !defined(CONFIG_USB_PD_ALT_MODE_DFP)
-void pd_send_hpd(int port, enum hpd_event hpd)
-{
-	uint32_t data[1];
-	int opos = pd_alt_mode(port, TCPC_TX_SOP, USB_SID_DISPLAYPORT);
-
-	if (!opos)
-		return;
+	/*
+	 * If the sink port was sourcing Vconn, and can no longer, request a
+	 * hard reset on this port to restore Vconn to the source.  If we do not
+	 * have sufficient battery to withstand Vbus loss, then continue with
+	 * the inconsistent Vconn state in order to keep the board powered.
+	 */
+	if (IS_ENABLED(CONFIG_USB_PE_SM)) {
+		if (tc_is_vconn_src(port) && tc_is_attached_snk(port) &&
+		    !pd_check_vconn_swap(port) && pd_is_battery_capable())
+			pd_dpm_request(port, DPM_REQUEST_HARD_RESET_SEND);
+	}
 
-	data[0] = VDO_DP_STATUS((hpd == hpd_irq), /* IRQ_HPD */
-				(hpd != hpd_low), /* HPD_HI|LOW */
-				0, /* request exit DP */
-				0, /* request exit USB */
-				0, /* MF pref */
-				1, /* enabled */
-				0, /* power low */
-				0x2);
-	pd_send_vdm(port, USB_SID_DISPLAYPORT, VDO_OPOS(opos) | CMD_ATTENTION,
-		    data, 1);
+	/*
+	 * TC_FLAGS_UPDATE_USB_MUX is set on chipset startup and shutdown.
+	 * Set the USB mux according to the new power state.  If the chipset
+	 * is transitioning to OFF, this disconnects USB and DP mux.
+	 *
+	 * Transitions to and from suspend states do not change the USB mux
+	 * or the alternate mode configuration.
+	 */
+	if (TC_CHK_FLAG(port, TC_FLAGS_UPDATE_USB_MUX)) {
+		TC_CLR_FLAG(port, TC_FLAGS_UPDATE_USB_MUX);
+		set_usb_mux_with_current_data_role(port);
+	}
 }
-#endif
 
 #ifdef CONFIG_USBC_VCONN_SWAP
 void pd_request_vconn_swap_off(int port)
 {
 	if (get_state_tc(port) == TC_ATTACHED_SRC ||
-			get_state_tc(port) == TC_ATTACHED_SNK) {
+	    get_state_tc(port) == TC_ATTACHED_SNK) {
 		TC_SET_FLAG(port, TC_FLAGS_REQUEST_VC_SWAP_OFF);
 		task_wake(PD_PORT_TO_TASK_ID(port));
 	}
@@ -1690,7 +1932,7 @@ void pd_request_vconn_swap_off(int port)
 void pd_request_vconn_swap_on(int port)
 {
 	if (get_state_tc(port) == TC_ATTACHED_SRC ||
-			get_state_tc(port) == TC_ATTACHED_SNK) {
+	    get_state_tc(port) == TC_ATTACHED_SNK) {
 		TC_SET_FLAG(port, TC_FLAGS_REQUEST_VC_SWAP_ON);
 		task_wake(PD_PORT_TO_TASK_ID(port));
 	}
@@ -1724,10 +1966,7 @@ static __maybe_unused int reset_device_and_notify(int port)
 	TC_CLR_FLAG(port, TC_FLAGS_LPM_ENGAGED);
 	tc_start_event_loop(port);
 
-	if (rv == EC_SUCCESS)
-		CPRINTS("C%d: TCPC init ready", port);
-	else
-		CPRINTS("C%d: TCPC init failed!", port);
+	CPRINTS("C%d: TCPC init %s", port, rv ? "failed!" : "ready");
 
 	/*
 	 * Before getting the other tasks that are waiting, clear the reset
@@ -1740,17 +1979,16 @@ static __maybe_unused int reset_device_and_notify(int port)
 	 * waking the TCPC, but it has also set PD_EVENT_TCPC_RESET again, which
 	 * would result in a second, unnecessary init.
 	 */
-	deprecated_atomic_clear_bits(task_get_event_bitmap(task_get_current()),
-				     PD_EVENT_TCPC_RESET);
+	atomic_clear_bits(task_get_event_bitmap(task_get_current()),
+			  PD_EVENT_TCPC_RESET);
 
-	waiting_tasks =
-		deprecated_atomic_read_clear(&tc[port].tasks_waiting_on_reset);
+	waiting_tasks = atomic_clear(&tc[port].tasks_waiting_on_reset);
 
 	/* Wake up all waiting tasks. */
 	while (waiting_tasks) {
 		task = __fls(waiting_tasks);
 		waiting_tasks &= ~BIT(task);
-		task_set_event(task, TASK_EVENT_PD_AWAKE, 0);
+		task_set_event(task, TASK_EVENT_PD_AWAKE);
 	}
 
 	return rv;
@@ -1767,8 +2005,8 @@ void pd_wait_exit_low_power(int port)
 			reset_device_and_notify(port);
 	} else {
 		/* Otherwise, we need to wait for the TCPC reset to complete */
-		deprecated_atomic_or(&tc[port].tasks_waiting_on_reset,
-				     1 << task_get_current());
+		atomic_or(&tc[port].tasks_waiting_on_reset,
+			  1 << task_get_current());
 		/*
 		 * NOTE: We could be sending the PD task the reset event while
 		 * it is already processing the reset event. If that occurs,
@@ -1777,8 +2015,7 @@ void pd_wait_exit_low_power(int port)
 		 * happen much, but it if starts occurring, we can add a guard
 		 * to prevent/reduce it.
 		 */
-		task_set_event(PD_PORT_TO_TASK_ID(port),
-			       PD_EVENT_TCPC_RESET, 0);
+		task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_TCPC_RESET);
 		task_wait_event_mask(TASK_EVENT_PD_AWAKE, -1);
 	}
 }
@@ -1793,7 +2030,7 @@ void pd_device_accessed(int port)
 		handle_device_access(port);
 	else
 		task_set_event(PD_PORT_TO_TASK_ID(port),
-			PD_EVENT_DEVICE_ACCESSED, 0);
+			       PD_EVENT_DEVICE_ACCESSED);
 }
 
 /*
@@ -1804,15 +2041,11 @@ void pd_prevent_low_power_mode(int port, int prevent)
 {
 	const int current_task_mask = (1 << task_get_current());
 
-	if (!IS_ENABLED(CONFIG_USB_PD_TCPC_LOW_POWER))
-		return;
-
 	if (prevent)
-		deprecated_atomic_or(&tc[port].tasks_preventing_lpm,
-				     current_task_mask);
+		atomic_or(&tc[port].tasks_preventing_lpm, current_task_mask);
 	else
-		deprecated_atomic_clear_bits(&tc[port].tasks_preventing_lpm,
-					     current_task_mask);
+		atomic_clear_bits(&tc[port].tasks_preventing_lpm,
+				  current_task_mask);
 }
 #endif /* CONFIG_USB_PD_TCPC_LOW_POWER */
 
@@ -1823,7 +2056,7 @@ static void sink_power_sub_states(int port)
 
 	tcpm_get_cc(port, &cc1, &cc2);
 
-	cc = tc[port].polarity ? cc2 : cc1;
+	cc = polarity_rm_dts(tc[port].polarity) ? cc2 : cc1;
 
 	if (cc == TYPEC_CC_VOLT_RP_DEF)
 		new_cc_voltage = TYPEC_CC_VOLT_RP_DEF;
@@ -1837,28 +2070,28 @@ static void sink_power_sub_states(int port)
 	/* Debounce the cc state */
 	if (new_cc_voltage != tc[port].cc_voltage) {
 		tc[port].cc_voltage = new_cc_voltage;
-		tc[port].cc_debounce =
-				get_time().val + PD_T_RP_VALUE_CHANGE;
+		pd_timer_enable(port, TC_TIMER_CC_DEBOUNCE,
+				PD_T_RP_VALUE_CHANGE);
 		return;
 	}
 
-	if (tc[port].cc_debounce == 0 ||
-				get_time().val < tc[port].cc_debounce)
-		return;
+	if (!pd_timer_is_disabled(port, TC_TIMER_CC_DEBOUNCE)) {
+		if (!pd_timer_is_expired(port, TC_TIMER_CC_DEBOUNCE))
+			return;
 
-	tc[port].cc_debounce = 0;
+		pd_timer_disable(port, TC_TIMER_CC_DEBOUNCE);
 
-	if (IS_ENABLED(CONFIG_CHARGE_MANAGER)) {
-		tc[port].typec_curr = usb_get_typec_current_limit(
-			tc[port].polarity, cc1, cc2);
+		if (IS_ENABLED(CONFIG_CHARGE_MANAGER)) {
+			tc[port].typec_curr = usb_get_typec_current_limit(
+				tc[port].polarity, cc1, cc2);
 
-		typec_set_input_current_limit(port,
-			tc[port].typec_curr, TYPE_C_VOLTAGE);
-		charge_manager_update_dualrole(port, CAP_DEDICATED);
+			typec_set_input_current_limit(port, tc[port].typec_curr,
+						      TYPE_C_VOLTAGE);
+			charge_manager_update_dualrole(port, CAP_DEDICATED);
+		}
 	}
 }
 
-
 /*
  * TYPE-C State Implementations
  */
@@ -1868,36 +2101,50 @@ static void sink_power_sub_states(int port)
  *
  * Super State Entry Actions:
  *   Remove the terminations from CC
- *   Set's VBUS and VCONN off
+ *   Set VBUS and VCONN off
  */
 static void tc_disabled_entry(const int port)
 {
 	print_current_state(port);
+	/*
+	 * We have completed tc_cc_open_entry (our super state), so set flag
+	 * to indicate to pd_is_port_enabled that we are now suspended.
+	 */
+	TC_SET_FLAG(port, TC_FLAGS_SUSPENDED);
+	tcpm_release(port);
 }
 
 static void tc_disabled_run(const int port)
 {
-	/*
-	 * If pd_set_suspend SUSPEND state changes to
-	 * no longer be suspended then we need to exit
-	 * our current state and go UNATTACHED_SNK
-	 */
-	if (!TC_CHK_FLAG(port, TC_FLAGS_SUSPEND))
-		set_state_tc(port, TC_UNATTACHED_SNK);
-
-	task_wait_event(-1);
+	/* If pd_set_suspend clears the request, go to TC_UNATTACHED_SNK/SRC. */
+	if (!TC_CHK_FLAG(port, TC_FLAGS_REQUEST_SUSPEND)) {
+		set_state_tc(port, drp_state[port] == PD_DRP_FORCE_SOURCE ?
+					   TC_UNATTACHED_SRC :
+					   TC_UNATTACHED_SNK);
+	} else {
+		if (IS_ENABLED(CONFIG_USBC_RETIMER_FW_UPDATE)) {
+			if (TC_CHK_FLAG(
+				    port,
+				    TC_FLAGS_USB_RETIMER_FW_UPDATE_LTD_RUN)) {
+				TC_CLR_FLAG(
+					port,
+					TC_FLAGS_USB_RETIMER_FW_UPDATE_LTD_RUN);
+				usb_retimer_fw_update_process_op_cb(port);
+			}
+		}
+		tc_pause_event_loop(port);
+	}
 }
 
 static void tc_disabled_exit(const int port)
 {
-	if (!IS_ENABLED(CONFIG_USB_PD_TCPC)) {
-		if (tcpm_init(port) != 0) {
-			CPRINTS("C%d: TCPC restart failed!", port);
-			return;
-		}
-	}
+	int rv;
+
+	tc_start_event_loop(port);
+	TC_CLR_FLAG(port, TC_FLAGS_SUSPENDED);
 
-	CPRINTS("C%d: TCPC resumed!", port);
+	rv = tcpm_init(port);
+	CPRINTS("C%d: TCPC init %s", port, rv ? "failed!" : "ready");
 }
 
 /**
@@ -1911,12 +2158,16 @@ static void tc_error_recovery_entry(const int port)
 {
 	print_current_state(port);
 
-	tc[port].timeout = get_time().val + PD_T_ERROR_RECOVERY;
+	pd_timer_enable(port, TC_TIMER_TIMEOUT, PD_T_ERROR_RECOVERY);
+
+	TC_CLR_FLAG(port, TC_FLAGS_REQUEST_ERROR_RECOVERY);
 }
 
 static void tc_error_recovery_run(const int port)
 {
-	if (get_time().val < tc[port].timeout)
+	enum usb_tc_state start_state;
+
+	if (!pd_timer_is_expired(port, TC_TIMER_TIMEOUT))
 		return;
 
 	/*
@@ -1925,7 +2176,9 @@ static void tc_error_recovery_run(const int port)
 	 * because we just did that. So transition to the state directly.
 	 */
 	if (tc[port].ctx.previous == NULL) {
-		set_state_tc(port, TC_UNATTACHED_SNK);
+		set_state_tc(port, drp_state[port] == PD_DRP_FORCE_SOURCE ?
+					   TC_UNATTACHED_SRC :
+					   TC_UNATTACHED_SNK);
 		return;
 	}
 
@@ -1933,8 +2186,18 @@ static void tc_error_recovery_run(const int port)
 	 * If try src support is active (e.g. in S0). Then try to become the
 	 * SRC, otherwise we should try to be the sink.
 	 */
-	restart_tc_sm(port, is_try_src_enabled(port) ? TC_UNATTACHED_SRC :
-						       TC_UNATTACHED_SNK);
+	start_state = TC_UNATTACHED_SNK;
+	if (IS_ENABLED(CONFIG_USB_PD_TRY_SRC))
+		if (is_try_src_enabled(port) ||
+		    drp_state[port] == PD_DRP_FORCE_SOURCE)
+			start_state = TC_UNATTACHED_SRC;
+
+	restart_tc_sm(port, start_state);
+}
+
+static void tc_error_recovery_exit(const int port)
+{
+	pd_timer_disable(port, TC_TIMER_TIMEOUT);
 }
 
 /**
@@ -1942,6 +2205,8 @@ static void tc_error_recovery_run(const int port)
  */
 static void tc_unattached_snk_entry(const int port)
 {
+	enum pd_data_role prev_data_role;
+
 	if (get_last_state_tc(port) != TC_UNATTACHED_SRC) {
 		tc_detached(port);
 		print_current_state(port);
@@ -1955,58 +2220,44 @@ static void tc_unattached_snk_entry(const int port)
 	 *
 	 * Both CC1 and CC2 pins shall be independently terminated to
 	 * ground through Rd.
+	 *
+	 * Restore default current limit Rp in case we swap to source
+	 *
+	 * Run any debug detaches needed before setting CC, as some TCPCs may
+	 * require we set CC Open before changing power roles with a debug
+	 * accessory.
 	 */
+	tcpm_debug_detach(port);
 	typec_select_pull(port, TYPEC_CC_RD);
+	typec_select_src_current_limit_rp(
+		port, typec_get_default_current_limit_rp(port));
 	typec_update_cc(port);
 
-	/*
-	 * Tell Policy Engine to invalidate the explicit contract.
-	 * This mainly used to clear the BB Ram Explicit Contract
-	 * value.
-	 */
-	pe_invalidate_explicit_contract(port);
-
+	prev_data_role = tc[port].data_role;
 	tc[port].data_role = PD_ROLE_DISCONNECTED;
-
-	/*
-	 * Saved SRC_Capabilities are no longer valid on disconnect
-	 */
-	pd_set_src_caps(port, 0, NULL);
-
 	/*
 	 * When data role set events are used to enable BC1.2, then CC
 	 * detach events are used to notify BC1.2 that it can be powered
 	 * down.
 	 */
-	if (IS_ENABLED(CONFIG_BC12_DETECT_DATA_ROLE_TRIGGER))
-		bc12_role_change_handler(port);
+	bc12_role_change_handler(port, prev_data_role, tc[port].data_role);
 
 	if (IS_ENABLED(CONFIG_CHARGE_MANAGER))
 		charge_manager_update_dualrole(port, CAP_UNKNOWN);
 
-	if (IS_ENABLED(CONFIG_USBC_PPC)) {
-		/*
-		 * Clear the overcurrent event counter
-		 * since we've detected a disconnect.
-		 */
-		ppc_clear_oc_event_counter(port);
-	}
+	tc_set_partner_role(port, PPC_DEV_DISCONNECTED, OCP_CLEAR);
 
 	/*
 	 * Indicate that the port is disconnected so the board
 	 * can restore state from any previous data swap.
 	 */
 	pd_execute_data_swap(port, PD_ROLE_DISCONNECTED);
-	tc[port].next_role_swap = get_time().val + PD_T_DRP_SNK;
+	pd_timer_enable(port, TC_TIMER_NEXT_ROLE_SWAP, PD_T_DRP_SNK);
 
-	if (IS_ENABLED(CONFIG_USBC_SS_MUX))
-		usb_mux_set(port, USB_PD_MUX_NONE,
-			USB_SWITCH_DISCONNECT, tc[port].polarity);
-
-	if (IS_ENABLED(CONFIG_USB_PE_SM)) {
-		CLR_ALL_BUT_LPM_FLAGS(port);
-		tc_enable_pd(port, 0);
-	}
+#ifdef CONFIG_USB_PE_SM
+	CLR_FLAGS_ON_DISCONNECT(port);
+	tc[port].ps_reset_state = PS_STATE0;
+#endif
 }
 
 static void tc_unattached_snk_run(const int port)
@@ -2030,17 +2281,6 @@ static void tc_unattached_snk_run(const int port)
 	/* Check for connection */
 	tcpm_get_cc(port, &cc1, &cc2);
 
-	/*
-	 * Attempt TCPC auto DRP toggle if it is
-	 * not already auto toggling.
-	 */
-	if (IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE) &&
-	    drp_state[port] == PD_DRP_TOGGLE_ON &&
-	    tcpm_auto_toggle_supported(port) && cc_is_open(cc1, cc2)) {
-		set_state_tc(port, TC_DRP_AUTO_TOGGLE);
-		return;
-	}
-
 	/*
 	 * The port shall transition to AttachWait.SNK when a Source
 	 * connection is detected, as indicated by the SNK.Rp state
@@ -2053,9 +2293,34 @@ static void tc_unattached_snk_run(const int port)
 	if (cc_is_rp(cc1) || cc_is_rp(cc2)) {
 		/* Connection Detected */
 		set_state_tc(port, TC_ATTACH_WAIT_SNK);
-	} else if (get_time().val > tc[port].next_role_swap &&
-		   drp_state[port] == PD_DRP_TOGGLE_ON) {
-		/* DRP Toggle */
+		return;
+	}
+
+	/*
+	 * Debounce the CC open status. Some TCPC needs time to get the CC
+	 * status valid. Before that, CC open is reported by default. Wait
+	 * to make sure the CC is really open. Reuse the role toggle timer.
+	 */
+	if (!pd_timer_is_expired(port, TC_TIMER_NEXT_ROLE_SWAP))
+		return;
+
+	/*
+	 * Initialize type-C supplier current limits to 0. The charge
+	 * manage is now seeded if it was not.
+	 */
+	if (IS_ENABLED(CONFIG_CHARGE_MANAGER))
+		typec_set_input_current_limit(port, 0, 0);
+
+	/*
+	 * Attempt TCPC auto DRP toggle if it is
+	 * not already auto toggling.
+	 */
+	if (IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE) &&
+	    drp_state[port] == PD_DRP_TOGGLE_ON &&
+	    tcpm_auto_toggle_supported(port)) {
+		set_state_tc(port, TC_DRP_AUTO_TOGGLE);
+	} else if (drp_state[port] == PD_DRP_TOGGLE_ON) {
+		/* DRP Toggle. The timer was checked above. */
 		set_state_tc(port, TC_UNATTACHED_SRC);
 	} else if (IS_ENABLED(CONFIG_USB_PD_TCPC_LOW_POWER) &&
 		   (drp_state[port] == PD_DRP_FORCE_SINK ||
@@ -2064,6 +2329,11 @@ static void tc_unattached_snk_run(const int port)
 	}
 }
 
+static void tc_unattached_snk_exit(const int port)
+{
+	pd_timer_disable(port, TC_TIMER_NEXT_ROLE_SWAP);
+}
+
 /**
  * AttachWait.SNK
  *
@@ -2087,7 +2357,7 @@ static void tc_attach_wait_snk_run(const int port)
 	/* Check for connection */
 	tcpm_get_cc(port, &cc1, &cc2);
 
-	if (cc_is_rp(cc1) && cc_is_rp(cc2))
+	if (cc_is_rp(cc1) && cc_is_rp(cc2) && board_is_dts_port(port))
 		new_cc_state = PD_CC_DFP_DEBUG_ACC;
 	else if (cc_is_rp(cc1) || cc_is_rp(cc2))
 		new_cc_state = PD_CC_DFP_ATTACHED;
@@ -2096,8 +2366,8 @@ static void tc_attach_wait_snk_run(const int port)
 
 	/* Debounce the cc state */
 	if (new_cc_state != tc[port].cc_state) {
-		tc[port].cc_debounce = get_time().val + PD_T_CC_DEBOUNCE;
-		tc[port].pd_debounce = get_time().val + PD_T_PD_DEBOUNCE;
+		pd_timer_enable(port, TC_TIMER_CC_DEBOUNCE, PD_T_CC_DEBOUNCE);
+		pd_timer_enable(port, TC_TIMER_PD_DEBOUNCE, PD_T_PD_DEBOUNCE);
 		tc[port].cc_state = new_cc_state;
 		return;
 	}
@@ -2109,18 +2379,11 @@ static void tc_attach_wait_snk_run(const int port)
 	 * Unattached.SNK.
 	 */
 	if (new_cc_state == PD_CC_NONE &&
-				get_time().val > tc[port].pd_debounce) {
-		if (IS_ENABLED(CONFIG_USB_PE_SM) &&
-				IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP)) {
-			pd_dfp_exit_mode(port, TCPC_TX_SOP, 0, 0);
-			pd_dfp_exit_mode(port, TCPC_TX_SOP_PRIME, 0, 0);
-			pd_dfp_exit_mode(port, TCPC_TX_SOP_PRIME_PRIME, 0, 0);
-		}
-
+	    pd_timer_is_expired(port, TC_TIMER_PD_DEBOUNCE)) {
 		/* We are detached */
-		if (drp_state[port] == PD_DRP_TOGGLE_OFF
-		    || drp_state[port] == PD_DRP_FREEZE
-		    || drp_state[port] == PD_DRP_FORCE_SINK)
+		if (drp_state[port] == PD_DRP_TOGGLE_OFF ||
+		    drp_state[port] == PD_DRP_FREEZE ||
+		    drp_state[port] == PD_DRP_FORCE_SINK)
 			set_state_tc(port, TC_UNATTACHED_SNK);
 		else
 			set_state_tc(port, TC_UNATTACHED_SRC);
@@ -2128,7 +2391,7 @@ static void tc_attach_wait_snk_run(const int port)
 	}
 
 	/* Wait for CC debounce */
-	if (get_time().val < tc[port].cc_debounce)
+	if (!pd_timer_is_expired(port, TC_TIMER_CC_DEBOUNCE))
 		return;
 
 	/*
@@ -2147,7 +2410,8 @@ static void tc_attach_wait_snk_run(const int port)
 	 */
 	if (pd_is_vbus_present(port)) {
 		if (new_cc_state == PD_CC_DFP_ATTACHED) {
-			if (is_try_src_enabled(port))
+			if (IS_ENABLED(CONFIG_USB_PD_TRY_SRC) &&
+			    is_try_src_enabled(port))
 				set_state_tc(port, TC_TRY_SRC);
 			else
 				set_state_tc(port, TC_ATTACHED_SNK);
@@ -2159,13 +2423,19 @@ static void tc_attach_wait_snk_run(const int port)
 		}
 
 		if (IS_ENABLED(CONFIG_USB_PE_SM) &&
-				IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP)) {
+		    IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP)) {
 			hook_call_deferred(&pd_usb_billboard_deferred_data,
-								PD_T_AME);
+					   PD_T_AME);
 		}
 	}
 }
 
+static void tc_attach_wait_snk_exit(const int port)
+{
+	pd_timer_disable(port, TC_TIMER_CC_DEBOUNCE);
+	pd_timer_disable(port, TC_TIMER_PD_DEBOUNCE);
+}
+
 /**
  * Attached.SNK, shared with Debug Accessory.SNK
  */
@@ -2185,8 +2455,11 @@ static void tc_attached_snk_entry(const int port)
 	 */
 	typec_select_pull(port, TYPEC_CC_RD);
 
-#ifdef CONFIG_USB_PE_SM
-	if (TC_CHK_FLAG(port, TC_FLAGS_PR_SWAP_IN_PROGRESS)) {
+	/* Inform the PPC and OCP module that a source is connected */
+	tc_set_partner_role(port, PPC_DEV_SRC, OCP_NO_ACTION);
+
+	if (IS_ENABLED(CONFIG_USB_PE_SM) &&
+	    TC_CHK_FLAG(port, TC_FLAGS_PR_SWAP_IN_PROGRESS)) {
 		/* Flipping power role - Disable AutoDischargeDisconnect */
 		tcpm_enable_auto_discharge_disconnect(port, 0);
 
@@ -2196,7 +2469,7 @@ static void tc_attached_snk_entry(const int port)
 		/* Change role to sink */
 		tc_set_power_role(port, PD_ROLE_SINK);
 		tcpm_set_msg_header(port, tc[port].power_role,
-							tc[port].data_role);
+				    tc[port].data_role);
 
 		/*
 		 * Maintain VCONN supply state, whether ON or OFF, and its
@@ -2204,44 +2477,90 @@ static void tc_attached_snk_entry(const int port)
 		 * AutoDischargeDisconnect until the swap is completed
 		 * and tc_pr_swap_complete is called.
 		 */
-	} else
-#endif
-	{
+	} else {
 		/* Get connector orientation */
 		tcpm_get_cc(port, &cc1, &cc2);
 		tc[port].polarity = get_snk_polarity(cc1, cc2);
-		pd_set_polarity(port, tc[port].polarity);
+		typec_set_polarity(port, tc[port].polarity);
 
 		tc_set_data_role(port, PD_ROLE_UFP);
 
 		hook_notify(HOOK_USB_PD_CONNECT);
 
 		if (IS_ENABLED(CONFIG_CHARGE_MANAGER)) {
-			tc[port].typec_curr =
-			usb_get_typec_current_limit(tc[port].polarity,
-								cc1, cc2);
-			typec_set_input_current_limit(port,
-					tc[port].typec_curr, TYPE_C_VOLTAGE);
-			charge_manager_update_dualrole(port,
-				pd_is_port_partner_dualrole(port) ?
-				CAP_DUALROLE : CAP_DEDICATED);
+			tc[port].typec_curr = usb_get_typec_current_limit(
+				tc[port].polarity, cc1, cc2);
+			typec_set_input_current_limit(port, tc[port].typec_curr,
+						      TYPE_C_VOLTAGE);
+			/*
+			 * Start new connections as dedicated until source caps
+			 * are received, at which point the PE will update the
+			 * flag.
+			 */
+			charge_manager_update_dualrole(port, CAP_DEDICATED);
+		}
+
+		/* Apply Rd */
+		typec_update_cc(port);
+
+		/*
+		 * Attached.SNK - enable AutoDischargeDisconnect
+		 * Do this after applying Rd to CC lines to avoid
+		 * TCPC_REG_FAULT_STATUS_AUTO_DISCHARGE_FAIL (b/171567398)
+		 */
+		tcpm_enable_auto_discharge_disconnect(port, 1);
+	}
+
+	pd_timer_disable(port, TC_TIMER_CC_DEBOUNCE);
+
+	/* Enable PD */
+	if (IS_ENABLED(CONFIG_USB_PE_SM))
+		tc_enable_pd(port, 1);
+
+	if (TC_CHK_FLAG(port, TC_FLAGS_TS_DTS_PARTNER)) {
+		tcpm_debug_accessory(port, 1);
+		set_ccd_mode(port, 1);
+	}
+}
+
+/*
+ * Check whether Vbus has been removed on this port, accounting for some Vbus
+ * debounce if FRS is enabled.
+ *
+ * Returns true if a new state was set and the calling run should exit.
+ */
+static bool tc_snk_check_vbus_removed(const int port)
+{
+	if (IS_ENABLED(CONFIG_USB_PD_FRS)) {
+		/*
+		 * Debounce Vbus presence when FRS is enabled. Note that we may
+		 * lose Vbus before the FRS signal comes in to let us know
+		 * we're PR swapping, but we must still transition to unattached
+		 * within tSinkDisconnect.
+		 *
+		 * We may safely re-use the Vbus debounce timer here
+		 * since a PR swap would no longer be in progress when Vbus
+		 * removal is checked.
+		 */
+		if (pd_check_vbus_level(port, VBUS_REMOVED)) {
+			if (pd_timer_is_disabled(port,
+						 TC_TIMER_VBUS_DEBOUNCE)) {
+				pd_timer_enable(port, TC_TIMER_VBUS_DEBOUNCE,
+						PD_T_FRS_VBUS_DEBOUNCE);
+			} else if (pd_timer_is_expired(
+					   port, TC_TIMER_VBUS_DEBOUNCE)) {
+				set_state_tc(port, TC_UNATTACHED_SNK);
+				return true;
+			}
+		} else {
+			pd_timer_disable(port, TC_TIMER_VBUS_DEBOUNCE);
 		}
-
-		/* Attached.SNK - enable AutoDischargeDisconnect */
-		tcpm_enable_auto_discharge_disconnect(port, 1);
-
-		/* Apply Rd */
-		typec_update_cc(port);
+	} else if (pd_check_vbus_level(port, VBUS_REMOVED)) {
+		set_state_tc(port, TC_UNATTACHED_SNK);
+		return true;
 	}
 
-	tc[port].cc_debounce = 0;
-
-	/* Enable PD */
-	if (IS_ENABLED(CONFIG_USB_PE_SM))
-		tc_enable_pd(port, 1);
-
-	if (TC_CHK_FLAG(port, TC_FLAGS_TS_DTS_PARTNER))
-		tcpm_debug_accessory(port, 1);
+	return false;
 }
 
 static void tc_attached_snk_run(const int port)
@@ -2279,9 +2598,10 @@ static void tc_attached_snk_run(const int port)
 	 * Debounce Vbus before we drop that we are doing a PR_Swap
 	 */
 	if (TC_CHK_FLAG(port, TC_FLAGS_PR_SWAP_IN_PROGRESS) &&
-	    tc[port].vbus_debounce_time < get_time().val) {
+	    pd_timer_is_expired(port, TC_TIMER_VBUS_DEBOUNCE)) {
 		/* PR Swap is no longer in progress */
 		TC_CLR_FLAG(port, TC_FLAGS_PR_SWAP_IN_PROGRESS);
+		pd_timer_disable(port, TC_TIMER_VBUS_DEBOUNCE);
 
 		/*
 		 * AutoDischargeDisconnect was turned off when we
@@ -2302,17 +2622,8 @@ static void tc_attached_snk_run(const int port)
 		/*
 		 * Detach detection
 		 */
-		if (pd_check_vbus_level(port, VBUS_REMOVED)) {
-			if (IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP)) {
-				pd_dfp_exit_mode(port, TCPC_TX_SOP, 0, 0);
-				pd_dfp_exit_mode(port, TCPC_TX_SOP_PRIME, 0, 0);
-				pd_dfp_exit_mode(port, TCPC_TX_SOP_PRIME_PRIME,
-						0, 0);
-			}
-
-			set_state_tc(port, TC_UNATTACHED_SNK);
+		if (tc_snk_check_vbus_removed(port))
 			return;
-		}
 
 		if (!pe_is_explicit_contract(port))
 			sink_power_sub_states(port);
@@ -2344,16 +2655,17 @@ static void tc_attached_snk_run(const int port)
 
 			/* Perform Data Role Swap */
 			tc_set_data_role(port,
-				tc[port].data_role == PD_ROLE_UFP ?
-					PD_ROLE_DFP : PD_ROLE_UFP);
+					 tc[port].data_role == PD_ROLE_UFP ?
+						 PD_ROLE_DFP :
+						 PD_ROLE_UFP);
 		}
 
-#ifdef CONFIG_USBC_VCONN
 		/*
 		 * VCONN Swap
 		 * UnorientedDebugAccessory.SRC shall not drive Vconn
 		 */
-		if (!TC_CHK_FLAG(port, TC_FLAGS_TS_DTS_PARTNER)) {
+		if (IS_ENABLED(CONFIG_USBC_VCONN) &&
+		    !TC_CHK_FLAG(port, TC_FLAGS_TS_DTS_PARTNER)) {
 			if (TC_CHK_FLAG(port, TC_FLAGS_REQUEST_VC_SWAP_ON)) {
 				TC_CLR_FLAG(port, TC_FLAGS_REQUEST_VC_SWAP_ON);
 
@@ -2375,7 +2687,7 @@ static void tc_attached_snk_run(const int port)
 				pe_vconn_swap_complete(port);
 			}
 		}
-#endif
+
 		if (!TC_CHK_FLAG(port, TC_FLAGS_TS_DTS_PARTNER)) {
 			/*
 			 * If the port supports Charge-Through VCONN-Powered USB
@@ -2401,10 +2713,8 @@ static void tc_attached_snk_run(const int port)
 #else /* CONFIG_USB_PE_SM */
 
 	/* Detach detection */
-	if (pd_check_vbus_level(port, VBUS_REMOVED)) {
-		set_state_tc(port, TC_UNATTACHED_SNK);
+	if (tc_snk_check_vbus_removed(port))
 		return;
-	}
 
 	/* Run Sink Power Sub-State */
 	sink_power_sub_states(port);
@@ -2428,7 +2738,7 @@ static void tc_attached_snk_exit(const int port)
 		 * happen in tc_cc_open_entry if that is the path we are
 		 * taking.
 		 */
-		if (!TC_CHK_FLAG(port, TC_FLAGS_SUSPEND))
+		if (!TC_CHK_FLAG(port, TC_FLAGS_REQUEST_SUSPEND))
 			tcpm_enable_auto_discharge_disconnect(port, 0);
 	}
 
@@ -2437,6 +2747,13 @@ static void tc_attached_snk_exit(const int port)
 
 	/* Stop drawing power */
 	sink_stop_drawing_current(port);
+
+	if (TC_CHK_FLAG(port, TC_FLAGS_TS_DTS_PARTNER))
+		tcpm_debug_detach(port);
+
+	pd_timer_disable(port, TC_TIMER_CC_DEBOUNCE);
+	pd_timer_disable(port, TC_TIMER_TIMEOUT);
+	pd_timer_disable(port, TC_TIMER_VBUS_DEBOUNCE);
 }
 
 /**
@@ -2444,6 +2761,8 @@ static void tc_attached_snk_exit(const int port)
  */
 static void tc_unattached_src_entry(const int port)
 {
+	enum pd_data_role prev_data_role;
+
 	if (get_last_state_tc(port) != TC_UNATTACHED_SNK) {
 		tc_detached(port);
 		print_current_state(port);
@@ -2457,46 +2776,40 @@ static void tc_unattached_src_entry(const int port)
 	 *
 	 * Both CC1 and CC2 pins shall be independently terminated to
 	 * ground through Rp.
+	 *
+	 * Restore default current limit Rp.
+	 *
+	 * Run any debug detaches needed before setting CC, as some TCPCs may
+	 * require we set CC Open before changing power roles with a debug
+	 * accessory.
 	 */
+	tcpm_debug_detach(port);
 	typec_select_pull(port, TYPEC_CC_RP);
-	typec_select_src_current_limit_rp(port, CONFIG_USB_PD_PULLUP);
+	typec_select_src_current_limit_rp(
+		port, typec_get_default_current_limit_rp(port));
 	typec_update_cc(port);
 
+	prev_data_role = tc[port].data_role;
 	tc[port].data_role = PD_ROLE_DISCONNECTED;
 
-	/*
-	 * Saved SRC_Capabilities are no longer valid on disconnect
-	 */
-	pd_set_src_caps(port, 0, NULL);
-
 	/*
 	 * When data role set events are used to enable BC1.2, then CC
 	 * detach events are used to notify BC1.2 that it can be powered
 	 * down.
 	 */
-	if (IS_ENABLED(CONFIG_BC12_DETECT_DATA_ROLE_TRIGGER))
-		bc12_role_change_handler(port);
-
-	if (IS_ENABLED(CONFIG_USBC_PPC)) {
-		/* There is no sink connected. */
-		ppc_sink_is_connected(port, 0);
+	bc12_role_change_handler(port, prev_data_role, tc[port].data_role);
 
-		/*
-		 * Clear the overcurrent event counter
-		 * since we've detected a disconnect.
-		 */
-		ppc_clear_oc_event_counter(port);
-	}
+	tc_set_partner_role(port, PPC_DEV_DISCONNECTED, OCP_CLEAR);
 
 	if (IS_ENABLED(CONFIG_CHARGE_MANAGER))
 		charge_manager_update_dualrole(port, CAP_UNKNOWN);
 
-	if (IS_ENABLED(CONFIG_USB_PE_SM)) {
-		CLR_ALL_BUT_LPM_FLAGS(port);
-		tc_enable_pd(port, 0);
-	}
+#ifdef CONFIG_USB_PE_SM
+	CLR_FLAGS_ON_DISCONNECT(port);
+	tc[port].ps_reset_state = PS_STATE0;
+#endif
 
-	tc[port].next_role_swap = get_time().val + PD_T_DRP_SRC;
+	pd_timer_enable(port, TC_TIMER_NEXT_ROLE_SWAP, PD_T_DRP_SRC);
 }
 
 static void tc_unattached_src_run(const int port)
@@ -2512,12 +2825,12 @@ static void tc_unattached_src_run(const int port)
 		}
 	}
 
-	if (IS_ENABLED(CONFIG_USBC_PPC)) {
+	if (IS_ENABLED(CONFIG_USBC_OCP)) {
 		/*
 		 * If the port is latched off, just continue to
 		 * monitor for a detach.
 		 */
-		if (ppc_is_port_latched_off(port))
+		if (usbc_ocp_is_port_latched_off(port))
 			return;
 	}
 
@@ -2534,7 +2847,7 @@ static void tc_unattached_src_run(const int port)
 	 */
 	if (cc_is_at_least_one_rd(cc1, cc2) || cc_is_audio_acc(cc1, cc2))
 		set_state_tc(port, TC_ATTACH_WAIT_SRC);
-	else if (get_time().val > tc[port].next_role_swap &&
+	else if (pd_timer_is_expired(port, TC_TIMER_NEXT_ROLE_SWAP) &&
 		 drp_state[port] != PD_DRP_FORCE_SOURCE &&
 		 drp_state[port] != PD_DRP_FREEZE)
 		set_state_tc(port, TC_UNATTACHED_SNK);
@@ -2551,6 +2864,11 @@ static void tc_unattached_src_run(const int port)
 		set_state_tc(port, TC_LOW_POWER_MODE);
 }
 
+static void tc_unattached_src_exit(const int port)
+{
+	pd_timer_disable(port, TC_TIMER_NEXT_ROLE_SWAP);
+}
+
 /**
  * AttachWait.SRC
  *
@@ -2574,9 +2892,12 @@ static void tc_attach_wait_src_run(const int port)
 	/* Check for connection */
 	tcpm_get_cc(port, &cc1, &cc2);
 
-	/* Debug accessory */
-	if (cc_is_snk_dbg_acc(cc1, cc2)) {
-		/* Debug accessory */
+	if (cc_is_snk_dbg_acc(cc1, cc2) && board_is_dts_port(port)) {
+		/*
+		 * Debug accessory.
+		 * A debug accessory in a non-DTS port will be
+		 * recognized by at_least_one_rd as UFP attached.
+		 */
 		new_cc_state = PD_CC_UFP_DEBUG_ACC;
 	} else if (cc_is_at_least_one_rd(cc1, cc2)) {
 		/* UFP attached */
@@ -2586,19 +2907,22 @@ static void tc_attach_wait_src_run(const int port)
 		new_cc_state = PD_CC_UFP_AUDIO_ACC;
 	} else {
 		/* No UFP */
-		set_state_tc(port, TC_UNATTACHED_SNK);
+		if (drp_state[port] == PD_DRP_FORCE_SOURCE)
+			set_state_tc(port, TC_UNATTACHED_SRC);
+		else
+			set_state_tc(port, TC_UNATTACHED_SNK);
 		return;
 	}
 
 	/* Debounce the cc state */
 	if (new_cc_state != tc[port].cc_state) {
-		tc[port].cc_debounce = get_time().val + PD_T_CC_DEBOUNCE;
+		pd_timer_enable(port, TC_TIMER_CC_DEBOUNCE, PD_T_CC_DEBOUNCE);
 		tc[port].cc_state = new_cc_state;
 		return;
 	}
 
 	/* Wait for CC debounce */
-	if (get_time().val < tc[port].cc_debounce)
+	if (!pd_timer_is_expired(port, TC_TIMER_CC_DEBOUNCE))
 		return;
 
 	/*
@@ -2624,6 +2948,11 @@ static void tc_attach_wait_src_run(const int port)
 	}
 }
 
+static void tc_attach_wait_src_exit(const int port)
+{
+	pd_timer_disable(port, TC_TIMER_CC_DEBOUNCE);
+}
+
 /**
  * Attached.SRC, shared with UnorientedDebugAccessory.SRC
  */
@@ -2633,8 +2962,7 @@ static void tc_attached_src_entry(const int port)
 
 	print_current_state(port);
 
-	/* Run function relies on timeout being 0 or meaningful */
-	tc[port].timeout = 0;
+	pd_timer_disable(port, TC_TIMER_TIMEOUT);
 
 	/*
 	 * Known state of attach is SRC.  We need to apply this pull value
@@ -2643,34 +2971,99 @@ static void tc_attached_src_entry(const int port)
 	 *
 	 * Both CC1 and CC2 pins shall be independently terminated to
 	 * pulled up through Rp.
+	 *
+	 * Set selected current limit in the hardware.
 	 */
 	typec_select_pull(port, TYPEC_CC_RP);
-	typec_select_src_current_limit_rp(port, CONFIG_USB_PD_PULLUP);
+	typec_set_source_current_limit(port, tc[port].select_current_limit_rp);
+
+	if (IS_ENABLED(CONFIG_USB_PE_SM)) {
+		if (TC_CHK_FLAG(port, TC_FLAGS_PR_SWAP_IN_PROGRESS)) {
+			/* Change role to source */
+			tc_set_power_role(port, PD_ROLE_SOURCE);
+			tcpm_set_msg_header(port, tc[port].power_role,
+					    tc[port].data_role);
 
-#if defined(CONFIG_USB_PE_SM)
-	if (TC_CHK_FLAG(port, TC_FLAGS_PR_SWAP_IN_PROGRESS)) {
-		/* Change role to source */
-		tc_set_power_role(port, PD_ROLE_SOURCE);
-		tcpm_set_msg_header(port,
-				tc[port].power_role, tc[port].data_role);
+			/* Enable VBUS */
+			tc_src_power_on(port);
 
-		/* Enable VBUS */
-		tc_src_power_on(port);
+			/* Apply Rp */
+			typec_update_cc(port);
 
-		/* Apply Rp */
-		typec_update_cc(port);
+			/*
+			 * Maintain VCONN supply state, whether ON or OFF, and
+			 * its data role / usb mux connections. Do not
+			 * re-enable AutoDischargeDisconnect until the swap is
+			 * completed and tc_pr_swap_complete is called.
+			 */
+		} else {
+			/*
+			 * Set up CC's, Vconn, and ADD before Vbus, as per
+			 * Figure 4-24. DRP Initialization and Connection
+			 * Detection in TCPCI r2 v1.2 specification.
+			 */
+
+			/* Get connector orientation */
+			tcpm_get_cc(port, &cc1, &cc2);
+			tc[port].polarity = get_src_polarity(cc1, cc2);
+			typec_set_polarity(port, tc[port].polarity);
+
+			/* Attached.SRC - enable AutoDischargeDisconnect */
+			tcpm_enable_auto_discharge_disconnect(port, 1);
+
+			/* Apply Rp */
+			typec_update_cc(port);
+
+			/*
+			 * Initial data role for sink is DFP
+			 * This also sets the usb mux
+			 */
+			tc_set_data_role(port, PD_ROLE_DFP);
+
+			/*
+			 * Start sourcing Vconn before Vbus to ensure
+			 * we are within USB Type-C Spec 1.4 tVconnON
+			 *
+			 * UnorientedDebugAccessory.SRC shall not drive Vconn
+			 */
+			if (IS_ENABLED(CONFIG_USBC_VCONN) &&
+			    !TC_CHK_FLAG(port, TC_FLAGS_TS_DTS_PARTNER))
+				set_vconn(port, 1);
+
+			/* Enable VBUS */
+			if (tc_src_power_on(port)) {
+				/* Stop sourcing Vconn if Vbus failed */
+				if (IS_ENABLED(CONFIG_USBC_VCONN))
+					set_vconn(port, 0);
+
+				if (IS_ENABLED(CONFIG_USBC_SS_MUX))
+					usb_mux_set(port, USB_PD_MUX_NONE,
+						    USB_SWITCH_DISCONNECT,
+						    tc[port].polarity);
+			}
 
+			tc_enable_pd(port, 0);
+			pd_timer_enable(port, TC_TIMER_TIMEOUT,
+					MAX(PD_POWER_SUPPLY_TURN_ON_DELAY,
+					    PD_T_VCONN_STABLE));
+		}
+	} else {
 		/*
-		 * Maintain VCONN supply state, whether ON or OFF, and its
-		 * data role / usb mux connections. Do not re-enable
-		 * AutoDischargeDisconnect until the swap is completed
-		 * and tc_pr_swap_complete is called.
+		 * Set up CC's, Vconn, and ADD before Vbus, as per
+		 * Figure 4-24. DRP Initialization and Connection
+		 * Detection in TCPCI r2 v1.2 specification.
 		 */
-	} else {
+
 		/* Get connector orientation */
 		tcpm_get_cc(port, &cc1, &cc2);
 		tc[port].polarity = get_src_polarity(cc1, cc2);
-		pd_set_polarity(port, tc[port].polarity);
+		typec_set_polarity(port, tc[port].polarity);
+
+		/* Attached.SRC - enable AutoDischargeDisconnect */
+		tcpm_enable_auto_discharge_disconnect(port, 1);
+
+		/* Apply Rp */
+		typec_update_cc(port);
 
 		/*
 		 * Initial data role for sink is DFP
@@ -2685,7 +3078,7 @@ static void tc_attached_src_entry(const int port)
 		 * UnorientedDebugAccessory.SRC shall not drive Vconn
 		 */
 		if (IS_ENABLED(CONFIG_USBC_VCONN) &&
-				!TC_CHK_FLAG(port, TC_FLAGS_TS_DTS_PARTNER))
+		    !TC_CHK_FLAG(port, TC_FLAGS_TS_DTS_PARTNER))
 			set_vconn(port, 1);
 
 		/* Enable VBUS */
@@ -2696,63 +3089,17 @@ static void tc_attached_src_entry(const int port)
 
 			if (IS_ENABLED(CONFIG_USBC_SS_MUX))
 				usb_mux_set(port, USB_PD_MUX_NONE,
-				USB_SWITCH_DISCONNECT, tc[port].polarity);
+					    USB_SWITCH_DISCONNECT,
+					    tc[port].polarity);
 		}
-
-		/* Attached.SRC - enable AutoDischargeDisconnect */
-		tcpm_enable_auto_discharge_disconnect(port, 1);
-
-		/* Apply Rp */
-		typec_update_cc(port);
-
-		tc_enable_pd(port, 0);
-		tc[port].timeout = get_time().val +
-			MAX(PD_POWER_SUPPLY_TURN_ON_DELAY, PD_T_VCONN_STABLE);
-	}
-#else
-	/* Get connector orientation */
-	tcpm_get_cc(port, &cc1, &cc2);
-	tc[port].polarity = get_src_polarity(cc1, cc2);
-	pd_set_polarity(port, tc[port].polarity);
-
-	/*
-	 * Initial data role for sink is DFP
-	 * This also sets the usb mux
-	 */
-	tc_set_data_role(port, PD_ROLE_DFP);
-
-	/*
-	 * Start sourcing Vconn before Vbus to ensure
-	 * we are within USB Type-C Spec 1.4 tVconnON
-	 *
-	 * UnorientedDebugAccessory.SRC shall not drive Vconn
-	 */
-	if (IS_ENABLED(CONFIG_USBC_VCONN) &&
-				!TC_CHK_FLAG(port, TC_FLAGS_TS_DTS_PARTNER))
-		set_vconn(port, 1);
-
-	/* Enable VBUS */
-	if (tc_src_power_on(port)) {
-		/* Stop sourcing Vconn if Vbus failed */
-		if (IS_ENABLED(CONFIG_USBC_VCONN))
-			set_vconn(port, 0);
-
-		if (IS_ENABLED(CONFIG_USBC_SS_MUX))
-			usb_mux_set(port, USB_PD_MUX_NONE,
-			USB_SWITCH_DISCONNECT, tc[port].polarity);
 	}
 
-	/* Attached.SRC - enable AutoDischargeDisconnect */
-	tcpm_enable_auto_discharge_disconnect(port, 1);
-
-	/* Apply Rp */
-	typec_update_cc(port);
-
-#endif /* CONFIG_USB_PE_SM */
+	/* Inform PPC and OCP module that a sink is connected. */
+	tc_set_partner_role(port, PPC_DEV_SNK, OCP_NO_ACTION);
 
-	/* Inform PPC that a sink is connected. */
-	if (IS_ENABLED(CONFIG_USBC_PPC))
-		ppc_sink_is_connected(port, 1);
+	/* Initialize type-C supplier to seed the charge manger */
+	if (IS_ENABLED(CONFIG_CHARGE_MANAGER))
+		typec_set_input_current_limit(port, 0, 0);
 
 	/*
 	 * Only notify if we're not performing a power role swap.  During a
@@ -2762,8 +3109,21 @@ static void tc_attached_src_entry(const int port)
 		hook_notify(HOOK_USB_PD_CONNECT);
 	}
 
-	if (TC_CHK_FLAG(port, TC_FLAGS_TS_DTS_PARTNER))
+	if (TC_CHK_FLAG(port, TC_FLAGS_TS_DTS_PARTNER)) {
 		tcpm_debug_accessory(port, 1);
+		set_ccd_mode(port, 1);
+	}
+
+	/*
+	 * Some TCPCs require time to correctly return CC status after
+	 * changing the ROLE_CONTROL register. Due to that, we have to ignore
+	 * CC_NONE state until PD_T_SRC_DISCONNECT delay has elapsed.
+	 * From the "Universal Serial Bus Type-C Cable and Connector
+	 * Specification" Release 2.0 paragraph 4.5.2.2.9.2:
+	 * The Source shall detect the SRC.Open state within tSRCDisconnect,
+	 * but should detect it as quickly as possible
+	 */
+	pd_timer_enable(port, TC_TIMER_CC_DEBOUNCE, PD_T_SRC_DISCONNECT);
 }
 
 static void tc_attached_src_run(const int port)
@@ -2773,7 +3133,7 @@ static void tc_attached_src_run(const int port)
 	/* Check for connection */
 	tcpm_get_cc(port, &cc1, &cc2);
 
-	if (tc[port].polarity)
+	if (polarity_rm_dts(tc[port].polarity))
 		cc1 = cc2;
 
 	if (cc1 == TYPEC_CC_VOLT_OPEN)
@@ -2792,22 +3152,21 @@ static void tc_attached_src_run(const int port)
 	 * Attached.SRC.
 	 */
 	if (tc[port].cc_state == PD_CC_NONE &&
-			!TC_CHK_FLAG(port, TC_FLAGS_PR_SWAP_IN_PROGRESS) &&
-			!TC_CHK_FLAG(port, TC_FLAGS_DISC_IDENT_IN_PROGRESS)) {
+	    pd_timer_is_expired(port, TC_TIMER_CC_DEBOUNCE)) {
+		bool tryWait;
+		enum usb_tc_state new_tc_state = TC_UNATTACHED_SNK;
 
-		const bool tryWait = is_try_src_enabled(port) &&
-				!TC_CHK_FLAG(port, TC_FLAGS_TS_DTS_PARTNER);
+		if (IS_ENABLED(CONFIG_USB_PD_TRY_SRC))
+			tryWait = is_try_src_enabled(port) &&
+				  !TC_CHK_FLAG(port, TC_FLAGS_TS_DTS_PARTNER);
 
-		if (IS_ENABLED(CONFIG_USB_PE_SM))
-			if (IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP)) {
-				pd_dfp_exit_mode(port, TCPC_TX_SOP, 0, 0);
-				pd_dfp_exit_mode(port, TCPC_TX_SOP_PRIME, 0, 0);
-				pd_dfp_exit_mode(port, TCPC_TX_SOP_PRIME_PRIME,
-						0, 0);
-			}
+		if (drp_state[port] == PD_DRP_FORCE_SOURCE)
+			new_tc_state = TC_UNATTACHED_SRC;
+		else if (IS_ENABLED(CONFIG_USB_PD_TRY_SRC))
+			new_tc_state = tryWait ? TC_TRY_WAIT_SNK :
+						 TC_UNATTACHED_SNK;
 
-		set_state_tc(port, tryWait ?
-					TC_TRY_WAIT_SNK : TC_UNATTACHED_SNK);
+		set_state_tc(port, new_tc_state);
 		return;
 	}
 
@@ -2816,9 +3175,9 @@ static void tc_attached_src_run(const int port)
 	 * Enable PD communications after power supply has fully
 	 * turned on
 	 */
-	if (tc[port].timeout > 0 && get_time().val > tc[port].timeout) {
+	if (pd_timer_is_expired(port, TC_TIMER_TIMEOUT)) {
 		tc_enable_pd(port, 1);
-		tc[port].timeout = 0;
+		pd_timer_disable(port, TC_TIMER_TIMEOUT);
 	}
 
 	if (!tc_get_pd_enabled(port))
@@ -2829,7 +3188,8 @@ static void tc_attached_src_run(const int port)
 	 */
 	if (TC_CHK_FLAG(port, TC_FLAGS_HARD_RESET_REQUESTED)) {
 		/* Ignoring Hard Resets while the power supply is resetting.*/
-		if (get_time().val < tc[port].timeout)
+		if (!pd_timer_is_disabled(port, TC_TIMER_TIMEOUT) &&
+		    !pd_timer_is_expired(port, TC_TIMER_TIMEOUT))
 			return;
 
 		if (tc_perform_src_hard_reset(port))
@@ -2858,8 +3218,9 @@ static void tc_attached_src_run(const int port)
 
 			/* Perform Data Role Swap */
 			tc_set_data_role(port,
-				tc[port].data_role == PD_ROLE_DFP ?
-					PD_ROLE_UFP : PD_ROLE_DFP);
+					 tc[port].data_role == PD_ROLE_DFP ?
+						 PD_ROLE_UFP :
+						 PD_ROLE_DFP);
 		}
 
 		/*
@@ -2867,7 +3228,7 @@ static void tc_attached_src_run(const int port)
 		 * UnorientedDebugAccessory.SRC shall not drive Vconn
 		 */
 		if (IS_ENABLED(CONFIG_USBC_VCONN) &&
-				!TC_CHK_FLAG(port, TC_FLAGS_TS_DTS_PARTNER)) {
+		    !TC_CHK_FLAG(port, TC_FLAGS_TS_DTS_PARTNER)) {
 			/*
 			 * VCONN Swap Request
 			 */
@@ -2876,7 +3237,7 @@ static void tc_attached_src_run(const int port)
 				set_vconn(port, 1);
 				pe_vconn_swap_complete(port);
 			} else if (TC_CHK_FLAG(port,
-						TC_FLAGS_REQUEST_VC_SWAP_OFF)) {
+					       TC_FLAGS_REQUEST_VC_SWAP_OFF)) {
 				TC_CLR_FLAG(port, TC_FLAGS_REQUEST_VC_SWAP_OFF);
 				set_vconn(port, 0);
 				pe_vconn_swap_complete(port);
@@ -2902,16 +3263,23 @@ static void tc_attached_src_run(const int port)
 		 * applied.
 		 */
 		if (!TC_CHK_FLAG(port, TC_FLAGS_TS_DTS_PARTNER) &&
-			TC_CHK_FLAG(port, TC_FLAGS_CTVPD_DETECTED)) {
-			TC_CLR_FLAG(port, TC_FLAGS_CTVPD_DETECTED);
-
-			/* Clear TC_FLAGS_DISC_IDENT_IN_PROGRESS */
-			TC_CLR_FLAG(port, TC_FLAGS_DISC_IDENT_IN_PROGRESS);
-
+		    TC_CHK_FLAG(port, TC_FLAGS_CTVPD_DETECTED)) {
 			set_state_tc(port, TC_CT_UNATTACHED_SNK);
 		}
 	}
 #endif
+
+	if (TC_CHK_FLAG(port, TC_FLAGS_UPDATE_CURRENT)) {
+		TC_CLR_FLAG(port, TC_FLAGS_UPDATE_CURRENT);
+		typec_set_source_current_limit(
+			port, tc[port].select_current_limit_rp);
+		pd_update_contract(port);
+
+		/* Update Rp if no contract is present */
+		if (!IS_ENABLED(CONFIG_USB_PE_SM) ||
+		    !pe_is_explicit_contract(port))
+			typec_update_cc(port);
+	}
 }
 
 static void tc_attached_src_exit(const int port)
@@ -2926,13 +3294,26 @@ static void tc_attached_src_exit(const int port)
 		/* Attached.SRC exit - disable AutoDischargeDisconnect */
 		tcpm_enable_auto_discharge_disconnect(port, 0);
 
-		/* Disable VCONN if not power role swapping */
-		if (TC_CHK_FLAG(port, TC_FLAGS_VCONN_ON))
+		/*
+		 * Disable VCONN if not power role swapping and
+		 * a CTVPD was not detected
+		 */
+		if (TC_CHK_FLAG(port, TC_FLAGS_VCONN_ON) &&
+		    !TC_CHK_FLAG(port, TC_FLAGS_CTVPD_DETECTED))
 			set_vconn(port, 0);
 	}
 
+	/* Clear CTVPD detected after checking for Vconn */
+	TC_CLR_FLAG(port, TC_FLAGS_CTVPD_DETECTED);
+
 	/* Clear PR swap flag after checking for Vconn */
 	TC_CLR_FLAG(port, TC_FLAGS_REQUEST_PR_SWAP);
+
+	if (TC_CHK_FLAG(port, TC_FLAGS_TS_DTS_PARTNER))
+		tcpm_debug_detach(port);
+
+	pd_timer_disable(port, TC_TIMER_CC_DEBOUNCE);
+	pd_timer_disable(port, TC_TIMER_TIMEOUT);
 }
 
 static __maybe_unused void check_drp_connection(const int port)
@@ -2948,14 +3329,14 @@ static __maybe_unused void check_drp_connection(const int port)
 	tc[port].drp_sink_time = get_time().val;
 
 	/* Get the next toggle state */
-	next_state = drp_auto_toggle_next_state(&tc[port].drp_sink_time,
-		tc[port].power_role, drp_state[port], cc1, cc2,
-		tcpm_auto_toggle_supported(port));
+	next_state = drp_auto_toggle_next_state(
+		&tc[port].drp_sink_time, tc[port].power_role, drp_state[port],
+		cc1, cc2, tcpm_auto_toggle_supported(port));
 
 	if (next_state == DRP_TC_DEFAULT)
-		next_state = (PD_ROLE_DEFAULT(port) == PD_ROLE_SOURCE)
-				? DRP_TC_UNATTACHED_SRC
-				: DRP_TC_UNATTACHED_SNK;
+		next_state = (PD_ROLE_DEFAULT(port) == PD_ROLE_SOURCE) ?
+				     DRP_TC_UNATTACHED_SRC :
+				     DRP_TC_UNATTACHED_SNK;
 
 	switch (next_state) {
 	case DRP_TC_UNATTACHED_SNK:
@@ -2983,12 +3364,14 @@ static __maybe_unused void check_drp_connection(const int port)
 	}
 }
 
-#ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
 /**
  * DrpAutoToggle
  */
-static void tc_drp_auto_toggle_entry(const int port)
+__maybe_unused static void tc_drp_auto_toggle_entry(const int port)
 {
+	if (!IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE))
+		assert(0);
+
 	print_current_state(port);
 
 	/*
@@ -2996,11 +3379,15 @@ static void tc_drp_auto_toggle_entry(const int port)
 	 * for the minimum of DRP SNK or SRC so the first toggle cause by
 	 * transition into auto toggle doesn't violate spec timing.
 	 */
-	tc[port].timeout = get_time().val + MAX(PD_T_DRP_SNK, PD_T_DRP_SRC);
+	pd_timer_enable(port, TC_TIMER_TIMEOUT,
+			MAX(PD_T_DRP_SNK, PD_T_DRP_SRC));
 }
 
-static void tc_drp_auto_toggle_run(const int port)
+__maybe_unused static void tc_drp_auto_toggle_run(const int port)
 {
+	if (!IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE))
+		assert(0);
+
 	/*
 	 * A timer is running, but if a connection comes in while waiting
 	 * then allow that to take higher priority.
@@ -3008,11 +3395,11 @@ static void tc_drp_auto_toggle_run(const int port)
 	if (TC_CHK_FLAG(port, TC_FLAGS_CHECK_CONNECTION))
 		check_drp_connection(port);
 
-	else if (tc[port].timeout != TIMER_DISABLED) {
-		if (tc[port].timeout > get_time().val)
+	else if (!pd_timer_is_disabled(port, TC_TIMER_TIMEOUT)) {
+		if (!pd_timer_is_expired(port, TC_TIMER_TIMEOUT))
 			return;
 
-		tc[port].timeout = TIMER_DISABLED;
+		pd_timer_disable(port, TC_TIMER_TIMEOUT);
 		tcpm_enable_drp_toggle(port);
 
 		if (IS_ENABLED(CONFIG_USB_PD_TCPC_LOW_POWER)) {
@@ -3020,26 +3407,33 @@ static void tc_drp_auto_toggle_run(const int port)
 		}
 	}
 }
-#endif /* CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE */
 
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-static void tc_low_power_mode_entry(const int port)
+__maybe_unused static void tc_drp_auto_toggle_exit(const int port)
+{
+	pd_timer_disable(port, TC_TIMER_TIMEOUT);
+}
+
+__maybe_unused static void tc_low_power_mode_entry(const int port)
 {
+	if (!IS_ENABLED(CONFIG_USB_PD_TCPC_LOW_POWER))
+		assert(0);
+
 	print_current_state(port);
-	tc[port].low_power_time = get_time().val + PD_LPM_DEBOUNCE_US;
-	tc[port].low_power_exit_time = 0;
+	pd_timer_enable(port, TC_TIMER_LOW_POWER_TIME, PD_LPM_DEBOUNCE_US);
 }
 
-static void tc_low_power_mode_run(const int port)
+__maybe_unused static void tc_low_power_mode_run(const int port)
 {
-	if (TC_CHK_FLAG(port, TC_FLAGS_CHECK_CONNECTION)) {
-		uint64_t now = get_time().val;
+	if (!IS_ENABLED(CONFIG_USB_PD_TCPC_LOW_POWER))
+		assert(0);
 
+	if (TC_CHK_FLAG(port, TC_FLAGS_CHECK_CONNECTION)) {
 		tc_start_event_loop(port);
-		if (tc[port].low_power_exit_time == 0) {
-			tc[port].low_power_exit_time = now
-				+ PD_LPM_EXIT_DEBOUNCE_US;
-		} else if (now > tc[port].low_power_exit_time) {
+		if (pd_timer_is_disabled(port, TC_TIMER_LOW_POWER_EXIT_TIME)) {
+			pd_timer_enable(port, TC_TIMER_LOW_POWER_EXIT_TIME,
+					PD_LPM_EXIT_DEBOUNCE_US);
+		} else if (pd_timer_is_expired(port,
+					       TC_TIMER_LOW_POWER_EXIT_TIME)) {
 			CPRINTS("C%d: Exit Low Power Mode", port);
 			check_drp_connection(port);
 		}
@@ -3047,9 +3441,10 @@ static void tc_low_power_mode_run(const int port)
 	}
 
 	if (tc[port].tasks_preventing_lpm)
-		tc[port].low_power_time = get_time().val + PD_LPM_DEBOUNCE_US;
+		pd_timer_enable(port, TC_TIMER_LOW_POWER_TIME,
+				PD_LPM_DEBOUNCE_US);
 
-	if (get_time().val > tc[port].low_power_time) {
+	if (pd_timer_is_expired(port, TC_TIMER_LOW_POWER_TIME)) {
 		CPRINTS("C%d: TCPC Enter Low Power Mode", port);
 		TC_SET_FLAG(port, TC_FLAGS_LPM_ENGAGED);
 		TC_SET_FLAG(port, TC_FLAGS_LPM_TRANSITION);
@@ -3057,11 +3452,15 @@ static void tc_low_power_mode_run(const int port)
 		TC_CLR_FLAG(port, TC_FLAGS_LPM_TRANSITION);
 		tc_pause_event_loop(port);
 
-		tc[port].low_power_exit_time = 0;
+		pd_timer_disable(port, TC_TIMER_LOW_POWER_EXIT_TIME);
 	}
 }
-#endif /* CONFIG_USB_PD_TCPC_LOW_POWER */
 
+__maybe_unused static void tc_low_power_mode_exit(const int port)
+{
+	pd_timer_disable(port, TC_TIMER_LOW_POWER_TIME);
+	pd_timer_disable(port, TC_TIMER_LOW_POWER_EXIT_TIME);
+}
 
 /**
  * Try.SRC
@@ -3077,8 +3476,8 @@ static void tc_try_src_entry(const int port)
 	print_current_state(port);
 
 	tc[port].cc_state = PD_CC_UNSET;
-	tc[port].try_wait_debounce = get_time().val + PD_T_DRP_TRY;
-	tc[port].timeout = get_time().val + PD_T_TRY_TIMEOUT;
+	pd_timer_enable(port, TC_TIMER_TRY_WAIT_DEBOUNCE, PD_T_DRP_TRY);
+	pd_timer_enable(port, TC_TIMER_TIMEOUT, PD_T_TRY_TIMEOUT);
 
 	/*
 	 * We are a SNK but would prefer to be a SRC.  Set the pull to
@@ -3088,7 +3487,9 @@ static void tc_try_src_entry(const int port)
 	 * ground through Rp.
 	 */
 	typec_select_pull(port, TYPEC_CC_RP);
-	typec_select_src_current_limit_rp(port, CONFIG_USB_PD_PULLUP);
+
+	typec_select_src_current_limit_rp(
+		port, typec_get_default_current_limit_rp(port));
 
 	/* Apply Rp */
 	typec_update_cc(port);
@@ -3103,7 +3504,7 @@ static void tc_try_src_run(const int port)
 	tcpm_get_cc(port, &cc1, &cc2);
 
 	if ((cc1 == TYPEC_CC_VOLT_RD && cc2 != TYPEC_CC_VOLT_RD) ||
-	     (cc1 != TYPEC_CC_VOLT_RD && cc2 == TYPEC_CC_VOLT_RD))
+	    (cc1 != TYPEC_CC_VOLT_RD && cc2 == TYPEC_CC_VOLT_RD))
 		new_cc_state = PD_CC_UFP_ATTACHED;
 	else
 		new_cc_state = PD_CC_NONE;
@@ -3111,7 +3512,7 @@ static void tc_try_src_run(const int port)
 	/* Debounce the cc state */
 	if (new_cc_state != tc[port].cc_state) {
 		tc[port].cc_state = new_cc_state;
-		tc[port].cc_debounce = get_time().val + PD_T_CC_DEBOUNCE;
+		pd_timer_enable(port, TC_TIMER_CC_DEBOUNCE, PD_T_CC_DEBOUNCE);
 	}
 
 	/*
@@ -3119,8 +3520,8 @@ static void tc_try_src_run(const int port)
 	 * detected on exactly one of the CC1 or CC2 pins for at least
 	 * tTryCCDebounce.
 	 */
-	if (get_time().val > tc[port].cc_debounce &&
-	    new_cc_state == PD_CC_UFP_ATTACHED)
+	if (new_cc_state == PD_CC_UFP_ATTACHED &&
+	    pd_timer_is_expired(port, TC_TIMER_CC_DEBOUNCE))
 		set_state_tc(port, TC_ATTACHED_SRC);
 
 	/*
@@ -3129,14 +3530,21 @@ static void tc_try_src_run(const int port)
 	 * or after tTryTimeout and the SRC.Rd state has not been detected.
 	 */
 	if (new_cc_state == PD_CC_NONE) {
-		if ((get_time().val > tc[port].try_wait_debounce &&
+		if ((pd_timer_is_expired(port, TC_TIMER_TRY_WAIT_DEBOUNCE) &&
 		     pd_check_vbus_level(port, VBUS_SAFE0V)) ||
-		    get_time().val > tc[port].timeout) {
+		    pd_timer_is_expired(port, TC_TIMER_TIMEOUT)) {
 			set_state_tc(port, TC_TRY_WAIT_SNK);
 		}
 	}
 }
 
+static void tc_try_src_exit(const int port)
+{
+	pd_timer_disable(port, TC_TIMER_CC_DEBOUNCE);
+	pd_timer_disable(port, TC_TIMER_TIMEOUT);
+	pd_timer_disable(port, TC_TIMER_TRY_WAIT_DEBOUNCE);
+}
+
 /**
  * TryWait.SNK
  *
@@ -3151,7 +3559,7 @@ static void tc_try_wait_snk_entry(const int port)
 
 	tc_enable_pd(port, 0);
 	tc[port].cc_state = PD_CC_UNSET;
-	tc[port].try_wait_debounce = get_time().val + PD_T_CC_DEBOUNCE;
+	pd_timer_enable(port, TC_TIMER_TRY_WAIT_DEBOUNCE, PD_T_CC_DEBOUNCE);
 
 	/*
 	 * We were a SNK, tried to be a SRC and it didn't work out. Try to
@@ -3184,15 +3592,15 @@ static void tc_try_wait_snk_run(const int port)
 	/* Debounce the cc state */
 	if (new_cc_state != tc[port].cc_state) {
 		tc[port].cc_state = new_cc_state;
-		tc[port].pd_debounce = get_time().val + PD_T_PD_DEBOUNCE;
+		pd_timer_enable(port, TC_TIMER_PD_DEBOUNCE, PD_T_PD_DEBOUNCE);
 	}
 
 	/*
 	 * The port shall transition to Unattached.SNK when the state of both
 	 * of the CC1 and CC2 pins is SNK.Open for at least tPDDebounce.
 	 */
-	if ((get_time().val > tc[port].pd_debounce) &&
-						(new_cc_state == PD_CC_NONE)) {
+	if (new_cc_state == PD_CC_NONE &&
+	    pd_timer_is_expired(port, TC_TIMER_PD_DEBOUNCE)) {
 		set_state_tc(port, TC_UNATTACHED_SNK);
 		return;
 	}
@@ -3201,19 +3609,26 @@ static void tc_try_wait_snk_run(const int port)
 	 * The port shall transition to Attached.SNK after tCCDebounce if or
 	 * when VBUS is detected.
 	 */
-	if (get_time().val > tc[port].try_wait_debounce &&
+	if (pd_timer_is_expired(port, TC_TIMER_TRY_WAIT_DEBOUNCE) &&
 	    pd_is_vbus_present(port))
 		set_state_tc(port, TC_ATTACHED_SNK);
 }
 
+static void tc_try_wait_snk_exit(const int port)
+{
+	pd_timer_disable(port, TC_TIMER_PD_DEBOUNCE);
+	pd_timer_disable(port, TC_TIMER_TRY_WAIT_DEBOUNCE);
+}
 #endif
 
-#if defined(CONFIG_USB_PE_SM)
 /*
  * CTUnattached.SNK
  */
-static void tc_ct_unattached_snk_entry(int port)
+__maybe_unused static void tc_ct_unattached_snk_entry(int port)
 {
+	if (!IS_ENABLED(CONFIG_USB_PE_SM))
+		assert(0);
+
 	print_current_state(port);
 
 	/*
@@ -3221,7 +3636,6 @@ static void tc_ct_unattached_snk_entry(int port)
 	 * ground through Rd.
 	 */
 	typec_select_pull(port, TYPEC_CC_RD);
-	typec_select_src_current_limit_rp(port, CONFIG_USB_PD_PULLUP);
 	typec_update_cc(port);
 
 	tc[port].cc_state = PD_CC_UNSET;
@@ -3236,22 +3650,26 @@ static void tc_ct_unattached_snk_entry(int port)
 	 */
 	tc_enable_pd(port, 0);
 
-	tc[port].timeout = get_time().val + PD_POWER_SUPPLY_TURN_ON_DELAY;
+	pd_timer_enable(port, TC_TIMER_TIMEOUT, PD_POWER_SUPPLY_TURN_ON_DELAY);
 }
 
-static void tc_ct_unattached_snk_run(int port)
+__maybe_unused static void tc_ct_unattached_snk_run(int port)
 {
 	enum tcpc_cc_voltage_status cc1;
 	enum tcpc_cc_voltage_status cc2;
 	enum pd_cc_states new_cc_state;
 
-	if (tc[port].timeout > 0 && get_time().val > tc[port].timeout) {
-		tc_enable_pd(port, 1);
-		tc[port].timeout = 0;
-	}
+	if (!IS_ENABLED(CONFIG_USB_PE_SM))
+		assert(0);
 
-	if (tc[port].timeout > 0)
-		return;
+	if (!pd_timer_is_disabled(port, TC_TIMER_TIMEOUT)) {
+		if (pd_timer_is_expired(port, TC_TIMER_TIMEOUT)) {
+			tc_enable_pd(port, 1);
+			pd_timer_disable(port, TC_TIMER_TIMEOUT);
+		} else {
+			return;
+		}
+	}
 
 	/* Wait until Protocol Layer is ready */
 	if (!prl_is_running(port))
@@ -3279,23 +3697,16 @@ static void tc_ct_unattached_snk_run(int port)
 	/* Debounce the cc state */
 	if (new_cc_state != tc[port].cc_state) {
 		tc[port].cc_state = new_cc_state;
-		tc[port].cc_debounce = get_time().val + PD_T_VPDDETACH;
+		pd_timer_enable(port, TC_TIMER_CC_DEBOUNCE, PD_T_VPDDETACH);
 	}
 
 	/*
 	 * The port shall transition to Unattached.SNK if the state of
 	 * the CC pin is SNK.Open for tVPDDetach after VBUS is vSafe0V.
 	 */
-	if (get_time().val > tc[port].cc_debounce) {
+	else if (pd_timer_is_expired(port, TC_TIMER_CC_DEBOUNCE)) {
 		if (new_cc_state == PD_CC_NONE &&
 		    pd_check_vbus_level(port, VBUS_SAFE0V)) {
-			if (IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP)) {
-				pd_dfp_exit_mode(port, TCPC_TX_SOP, 0, 0);
-				pd_dfp_exit_mode(port, TCPC_TX_SOP_PRIME, 0, 0);
-				pd_dfp_exit_mode(port, TCPC_TX_SOP_PRIME_PRIME,
-						0, 0);
-			}
-
 			set_state_tc(port, TC_UNATTACHED_SNK);
 			return;
 		}
@@ -3308,19 +3719,38 @@ static void tc_ct_unattached_snk_run(int port)
 		set_state_tc(port, TC_CT_ATTACHED_SNK);
 }
 
+__maybe_unused static void tc_ct_unattached_snk_exit(int port)
+{
+	pd_timer_disable(port, TC_TIMER_CC_DEBOUNCE);
+	pd_timer_disable(port, TC_TIMER_TIMEOUT);
+}
+
 /**
  * CTAttached.SNK
  */
-static void tc_ct_attached_snk_entry(int port)
+__maybe_unused static void tc_ct_attached_snk_entry(int port)
 {
+	if (!IS_ENABLED(CONFIG_USB_PE_SM))
+		assert(0);
+
 	print_current_state(port);
 
 	/* The port shall reject a VCONN swap request. */
 	TC_SET_FLAG(port, TC_FLAGS_REJECT_VCONN_SWAP);
+
+	/*
+	 * Type-C r 2.2: The Host shall not advertise dual-role data or
+	 * dual-role power in its SourceCapability or SinkCapability messages -
+	 * Host changes its advertised capabilities to UFP role/sink only role.
+	 */
+	tc_set_data_role(port, PD_ROLE_UFP);
 }
 
-static void tc_ct_attached_snk_run(int port)
+__maybe_unused static void tc_ct_attached_snk_run(int port)
 {
+	if (!IS_ENABLED(CONFIG_USB_PE_SM))
+		assert(0);
+
 	/*
 	 * Hard Reset is sent when the PE layer is disabled due to a
 	 * CTVPD connection.
@@ -3350,14 +3780,16 @@ static void tc_ct_attached_snk_run(int port)
 		sink_power_sub_states(port);
 }
 
-static void tc_ct_attached_snk_exit(int port)
+__maybe_unused static void tc_ct_attached_snk_exit(int port)
 {
+	if (!IS_ENABLED(CONFIG_USB_PE_SM))
+		assert(0);
+
 	/* Stop drawing power */
 	sink_stop_drawing_current(port);
 
 	TC_CLR_FLAG(port, TC_FLAGS_REJECT_VCONN_SWAP);
 }
-#endif /* CONFIG_USB_PE_SM */
 
 /**
  * Super State CC_RD
@@ -3373,7 +3805,6 @@ static void tc_cc_rd_entry(const int port)
 	tcpm_set_msg_header(port, tc[port].power_role, tc[port].data_role);
 }
 
-
 /**
  * Super State CC_RP
  */
@@ -3412,24 +3843,26 @@ static void tc_cc_open_entry(const int port)
 	if (battery_is_present())
 		tcpm_enable_auto_discharge_disconnect(port, 0);
 
-	/* We may brown out after applying CC open, so flush console first. */
+	/*
+	 * We may brown out after applying CC open, so flush console first.
+	 * Console flush can take a long time, so if we aren't in danger of
+	 * browning out, don't do it so we can meet certain compliance timing
+	 * requirements.
+	 */
 	CPRINTS("C%d: Applying CC Open!", port);
-	cflush();
+	if (!battery_is_present())
+		cflush();
 
 	/* Remove terminations from CC */
 	typec_select_pull(port, TYPEC_CC_OPEN);
 	typec_update_cc(port);
 
-	if (IS_ENABLED(CONFIG_USBC_PPC)) {
-		/* There is no sink connected. */
-		ppc_sink_is_connected(port, 0);
-
-		/*
-		 * Clear the overcurrent event counter
-		 * since we've detected a disconnect.
-		 */
-		ppc_clear_oc_event_counter(port);
-	}
+	/*
+	 * While we've disconnected the partner, leave any OCP counts in place
+	 * to persist over ErrorRecovery
+	 */
+	tc_set_partner_role(port, PPC_DEV_DISCONNECTED, OCP_NO_ACTION);
+	tc_detached(port);
 }
 
 void tc_set_debug_level(enum debug_level debug_level)
@@ -3439,20 +3872,47 @@ void tc_set_debug_level(enum debug_level debug_level)
 #endif
 }
 
+void tc_usb_firmware_fw_update_limited_run(int port)
+{
+	TC_SET_FLAG(port, TC_FLAGS_USB_RETIMER_FW_UPDATE_LTD_RUN);
+	task_wake(PD_PORT_TO_TASK_ID(port));
+}
+
+void tc_usb_firmware_fw_update_run(int port)
+{
+	TC_SET_FLAG(port, TC_FLAGS_USB_RETIMER_FW_UPDATE_RUN);
+	task_wake(PD_PORT_TO_TASK_ID(port));
+}
+
 void tc_run(const int port)
 {
 	/*
-	 * If pd_set_suspend SUSPEND state changes to
-	 * be suspended then we need to go directly to
-	 * DISABLED
+	 * If pd_set_suspend set TC_FLAGS_REQUEST_SUSPEND, go directly to
+	 * TC_DISABLED.
 	 */
-	if (TC_CHK_FLAG(port, TC_FLAGS_SUSPEND)) {
+	if (get_state_tc(port) != TC_DISABLED &&
+	    TC_CHK_FLAG(port, TC_FLAGS_REQUEST_SUSPEND)) {
 		/* Invalidate a contract, if there is one */
-		pe_invalidate_explicit_contract(port);
+		if (IS_ENABLED(CONFIG_USB_PE_SM))
+			pe_invalidate_explicit_contract(port);
 
 		set_state_tc(port, TC_DISABLED);
 	}
 
+	/* If error recovery has been requested, transition now */
+	if (TC_CHK_FLAG(port, TC_FLAGS_REQUEST_ERROR_RECOVERY)) {
+		if (IS_ENABLED(CONFIG_USB_PE_SM))
+			pe_invalidate_explicit_contract(port);
+		set_state_tc(port, TC_ERROR_RECOVERY);
+	}
+
+	if (IS_ENABLED(CONFIG_USBC_RETIMER_FW_UPDATE)) {
+		if (TC_CHK_FLAG(port, TC_FLAGS_USB_RETIMER_FW_UPDATE_RUN)) {
+			TC_CLR_FLAG(port, TC_FLAGS_USB_RETIMER_FW_UPDATE_RUN);
+			usb_retimer_fw_update_process_op_cb(port);
+		}
+	}
+
 	run_state(port, &tc[port].ctx);
 }
 
@@ -3461,10 +3921,17 @@ static void pd_chipset_resume(void)
 	int i;
 
 	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		pd_set_dual_role_and_event(i,
-					   PD_DRP_TOGGLE_ON,
-					   PD_EVENT_UPDATE_DUAL_ROLE
-					   | PD_EVENT_POWER_STATE_CHANGE);
+		if (IS_ENABLED(CONFIG_USB_PE_SM))
+			pd_resume_check_pr_swap_needed(i);
+
+		pd_set_dual_role_and_event(i, pd_get_drp_state_in_s0(),
+					   PD_EVENT_UPDATE_DUAL_ROLE |
+						   PD_EVENT_POWER_STATE_CHANGE);
+
+		if (tc[i].data_role == PD_ROLE_DFP) {
+			pd_send_alert_msg(i, ADO_EXTENDED_ALERT_EVENT |
+						     ADO_POWER_STATE_CHANGE);
+		}
 	}
 
 	CPRINTS("PD:S3->S0");
@@ -3476,26 +3943,65 @@ static void pd_chipset_suspend(void)
 	int i;
 
 	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		pd_set_dual_role_and_event(i,
-					   pd_get_drp_state_in_suspend(),
-					   PD_EVENT_UPDATE_DUAL_ROLE
-					   | PD_EVENT_POWER_STATE_CHANGE);
+		pd_set_dual_role_and_event(i, pd_get_drp_state_in_suspend(),
+					   PD_EVENT_UPDATE_DUAL_ROLE |
+						   PD_EVENT_POWER_STATE_CHANGE);
+
+		if (tc[i].data_role == PD_ROLE_DFP) {
+			pd_send_alert_msg(i, ADO_EXTENDED_ALERT_EVENT |
+						     ADO_POWER_STATE_CHANGE);
+		}
 	}
 
 	CPRINTS("PD:S0->S3");
 }
 DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, pd_chipset_suspend, HOOK_PRIO_DEFAULT);
 
+static void pd_chipset_reset(void)
+{
+	int i;
+
+	if (!IS_ENABLED(CONFIG_USB_PE_SM))
+		return;
+
+	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+		enum tcpci_msg_type tx;
+
+		/* Do not notify the AP of irrelevant past Hard Resets. */
+		pd_clear_events(i, PD_STATUS_EVENT_HARD_RESET);
+
+		/*
+		 * Re-set events for SOP and SOP' discovery complete so the
+		 * kernel knows to consume discovery information for them.
+		 */
+		for (tx = TCPCI_MSG_SOP; tx <= TCPCI_MSG_SOP_PRIME; tx++) {
+			if (pd_get_identity_discovery(i, tx) !=
+				    PD_DISC_NEEDED &&
+			    pd_get_svids_discovery(i, tx) != PD_DISC_NEEDED &&
+			    pd_get_modes_discovery(i, tx) != PD_DISC_NEEDED)
+				pd_notify_event(
+					i,
+					tx == TCPCI_MSG_SOP ?
+						PD_STATUS_EVENT_SOP_DISC_DONE :
+						PD_STATUS_EVENT_SOP_PRIME_DISC_DONE);
+		}
+
+		/* Exit mode so AP can enter mode again after reset */
+		if (IS_ENABLED(CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY))
+			dpm_set_mode_exit_request(i);
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESET, pd_chipset_reset, HOOK_PRIO_DEFAULT);
+
 static void pd_chipset_startup(void)
 {
 	int i;
 
 	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		set_usb_mux_with_current_data_role(i);
-		pd_set_dual_role_and_event(i,
-					   pd_get_drp_state_in_suspend(),
-					   PD_EVENT_UPDATE_DUAL_ROLE
-					   | PD_EVENT_POWER_STATE_CHANGE);
+		TC_SET_FLAG(i, TC_FLAGS_UPDATE_USB_MUX);
+		pd_set_dual_role_and_event(i, pd_get_drp_state_in_suspend(),
+					   PD_EVENT_UPDATE_DUAL_ROLE |
+						   PD_EVENT_POWER_STATE_CHANGE);
 		/*
 		 * Request port discovery to restore any
 		 * alt modes.
@@ -3504,6 +4010,11 @@ static void pd_chipset_startup(void)
 		 */
 		if (IS_ENABLED(CONFIG_USB_PE_SM))
 			pd_dpm_request(i, DPM_REQUEST_PORT_DISCOVERY);
+
+		if (tc[i].data_role == PD_ROLE_DFP) {
+			pd_send_alert_msg(i, ADO_EXTENDED_ALERT_EVENT |
+						     ADO_POWER_STATE_CHANGE);
+		}
 	}
 
 	CPRINTS("PD:S5->S3");
@@ -3515,16 +4026,42 @@ static void pd_chipset_shutdown(void)
 	int i;
 
 	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		pd_set_dual_role_and_event(i,
-					   PD_DRP_FORCE_SINK,
-					   PD_EVENT_UPDATE_DUAL_ROLE
-					   | PD_EVENT_POWER_STATE_CHANGE);
+		TC_SET_FLAG(i, TC_FLAGS_UPDATE_USB_MUX);
+		pd_set_dual_role_and_event(i, PD_DRP_FORCE_SINK,
+					   PD_EVENT_UPDATE_DUAL_ROLE |
+						   PD_EVENT_POWER_STATE_CHANGE);
+
+		if (tc[i].data_role == PD_ROLE_DFP) {
+			pd_send_alert_msg(i, ADO_EXTENDED_ALERT_EVENT |
+						     ADO_POWER_STATE_CHANGE);
+		}
 	}
 
 	CPRINTS("PD:S3->S5");
 }
 DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, pd_chipset_shutdown, HOOK_PRIO_DEFAULT);
 
+static void pd_set_power_change(void)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		task_set_event(PD_PORT_TO_TASK_ID(i),
+			       PD_EVENT_POWER_STATE_CHANGE);
+	}
+}
+DECLARE_DEFERRED(pd_set_power_change);
+
+static void pd_chipset_hard_off(void)
+{
+	/*
+	 * Wait 1 second to check our Vconn sourcing status, as the power rails
+	 * which were supporting it may take some time to change after entering
+	 * G3.
+	 */
+	hook_call_deferred(&pd_set_power_change_data, 1 * SECOND);
+}
+DECLARE_HOOK(HOOK_CHIPSET_HARD_OFF, pd_chipset_hard_off, HOOK_PRIO_DEFAULT);
 
 /*
  * Type-C State Hierarchy (Sub-States are listed inside the boxes)
@@ -3545,7 +4082,7 @@ DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, pd_chipset_shutdown, HOOK_PRIO_DEFAULT);
  * TC_ATTACHED_SNK    TC_ATTACHED_SRC    TC_DRP_AUTO_TOGGLE    TC_LOW_POWER_MODE
  *
  */
-static const struct usb_state tc_states[] = {
+static __const_data const struct usb_state tc_states[] = {
 	/* Super States */
 	[TC_CC_OPEN] = {
 		.entry	= tc_cc_open_entry,
@@ -3566,16 +4103,19 @@ static const struct usb_state tc_states[] = {
 	[TC_ERROR_RECOVERY] = {
 		.entry	= tc_error_recovery_entry,
 		.run	= tc_error_recovery_run,
+		.exit   = tc_error_recovery_exit,
 		.parent = &tc_states[TC_CC_OPEN],
 	},
 	[TC_UNATTACHED_SNK] = {
 		.entry	= tc_unattached_snk_entry,
 		.run	= tc_unattached_snk_run,
+		.exit	= tc_unattached_snk_exit,
 		.parent = &tc_states[TC_CC_RD],
 	},
 	[TC_ATTACH_WAIT_SNK] = {
 		.entry	= tc_attach_wait_snk_entry,
 		.run	= tc_attach_wait_snk_run,
+		.exit	= tc_attach_wait_snk_exit,
 		.parent = &tc_states[TC_CC_RD],
 	},
 	[TC_ATTACHED_SNK] = {
@@ -3586,11 +4126,13 @@ static const struct usb_state tc_states[] = {
 	[TC_UNATTACHED_SRC] = {
 		.entry	= tc_unattached_src_entry,
 		.run	= tc_unattached_src_run,
+		.exit	= tc_unattached_src_exit,
 		.parent = &tc_states[TC_CC_RP],
 	},
 	[TC_ATTACH_WAIT_SRC] = {
 		.entry	= tc_attach_wait_src_entry,
 		.run	= tc_attach_wait_src_run,
+		.exit	= tc_attach_wait_src_exit,
 		.parent = &tc_states[TC_CC_RP],
 	},
 	[TC_ATTACHED_SRC] = {
@@ -3602,11 +4144,13 @@ static const struct usb_state tc_states[] = {
 	[TC_TRY_SRC] = {
 		.entry	= tc_try_src_entry,
 		.run	= tc_try_src_run,
+		.exit	= tc_try_src_exit,
 		.parent = &tc_states[TC_CC_RP],
 	},
 	[TC_TRY_WAIT_SNK] = {
 		.entry	= tc_try_wait_snk_entry,
 		.run	= tc_try_wait_snk_run,
+		.exit	= tc_try_wait_snk_exit,
 		.parent = &tc_states[TC_CC_RD],
 	},
 #endif /* CONFIG_USB_PD_TRY_SRC */
@@ -3614,18 +4158,21 @@ static const struct usb_state tc_states[] = {
 	[TC_DRP_AUTO_TOGGLE] = {
 		.entry = tc_drp_auto_toggle_entry,
 		.run   = tc_drp_auto_toggle_run,
+		.exit  = tc_drp_auto_toggle_exit,
 	},
 #endif /* CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE */
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
 	[TC_LOW_POWER_MODE] = {
 		.entry = tc_low_power_mode_entry,
 		.run   = tc_low_power_mode_run,
+		.exit  = tc_low_power_mode_exit,
 	},
 #endif /* CONFIG_USB_PD_TCPC_LOW_POWER */
 #ifdef CONFIG_USB_PE_SM
 	[TC_CT_UNATTACHED_SNK] = {
 		.entry = tc_ct_unattached_snk_entry,
 		.run   = tc_ct_unattached_snk_run,
+		.exit  = tc_ct_unattached_snk_exit,
 	},
 	[TC_CT_ATTACHED_SNK] = {
 		.entry = tc_ct_attached_snk_entry,
@@ -3644,6 +4191,5 @@ const struct test_sm_data test_tc_sm_data[] = {
 		.names_size = ARRAY_SIZE(tc_state_names),
 	},
 };
-BUILD_ASSERT(ARRAY_SIZE(tc_states) == ARRAY_SIZE(tc_state_names));
 const int test_tc_sm_data_size = ARRAY_SIZE(test_tc_sm_data);
 #endif
diff --git a/common/usbc/usb_tc_vpd_sm.c b/common/usbc/usb_tc_vpd_sm.c
index 7d25001813..1a820c4003 100644
--- a/common/usbc/usb_tc_vpd_sm.c
+++ b/common/usbc/usb_tc_vpd_sm.c
@@ -1,30 +1,32 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
 #include "system.h"
 #include "task.h"
-#include "tcpm.h"
+#include "tcpm/tcpm.h"
+#include "typec_control.h"
 #include "usb_pd.h"
-#include "usb_tc_sm.h"
 #include "usb_sm.h"
+#include "usb_tc_sm.h"
 #include "vpd_api.h"
 
 /* USB Type-C VCONN Powered Device module */
 
 #ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USB, format, ##args)
 #else /* CONFIG_COMMON_RUNTIME */
 #define CPRINTF(format, args...)
 #define CPRINTS(format, args...)
 #endif
 
 /* Type-C Layer Flags */
-#define TC_FLAGS_VCONN_ON           BIT(0)
+#define TC_FLAGS_VCONN_ON BIT(0)
 
 /**
  * This is the Type-C Port object that contains information needed to
@@ -59,15 +61,15 @@ enum usb_tc_state {
 /* Forward declare the full list of states. This is indexed by usb_tc_state */
 static const struct usb_state tc_states[];
 
-#ifdef CONFIG_COMMON_RUNTIME
 /* List of human readable state names for console debugging */
-static const char * const tc_state_names[] = {
+__maybe_unused static const char *const tc_state_names[] = {
+#ifdef CONFIG_COMMON_RUNTIME
 	[TC_DISABLED] = "Disabled",
 	[TC_UNATTACHED_SNK] = "Unattached.SNK",
 	[TC_ATTACH_WAIT_SNK] = "AttachWait.SNK",
 	[TC_ATTACHED_SNK] = "Attached.SNK",
-};
 #endif
+};
 
 /* Forward declare private, common functions */
 static void set_state_tc(const int port, enum usb_tc_state new_state);
@@ -269,11 +271,11 @@ static void tc_attach_wait_snk_run(const int port)
 	if (tc[port].host_cc_state != host_new_cc_state) {
 		tc[port].host_cc_state = host_new_cc_state;
 		if (host_new_cc_state == PD_CC_DFP_ATTACHED)
-			tc[port].cc_debounce = get_time().val +
-							PD_T_CC_DEBOUNCE;
+			tc[port].cc_debounce =
+				get_time().val + PD_T_CC_DEBOUNCE;
 		else
-			tc[port].cc_debounce = get_time().val +
-							PD_T_PD_DEBOUNCE;
+			tc[port].cc_debounce =
+				get_time().val + PD_T_PD_DEBOUNCE;
 
 		return;
 	}
@@ -292,7 +294,7 @@ static void tc_attach_wait_snk_run(const int port)
 	 * CC2 pins is SNK.Open for at least tPDDebounce.
 	 */
 	if (tc[port].host_cc_state == PD_CC_DFP_ATTACHED &&
-			(vpd_is_vconn_present() || vpd_is_host_vbus_present()))
+	    (vpd_is_vconn_present() || vpd_is_host_vbus_present()))
 		set_state_tc(port, TC_ATTACHED_SNK);
 	else if (tc[port].host_cc_state == PD_CC_NONE)
 		set_state_tc(port, TC_UNATTACHED_SNK);
@@ -307,7 +309,7 @@ static void tc_attached_snk_entry(const int port)
 
 	/* Enable PD */
 	tc[port].pd_enable = 1;
-	pd_set_polarity(port, 0);
+	typec_set_polarity(port, 0);
 }
 
 static void tc_attached_snk_run(const int port)
diff --git a/common/usbc/usbc_pd_policy.c b/common/usbc/usbc_pd_policy.c
new file mode 100644
index 0000000000..6d82ed114c
--- /dev/null
+++ b/common/usbc/usbc_pd_policy.c
@@ -0,0 +1,48 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "ec_commands.h"
+#include "usb_pe_sm.h"
+#include "usb_tc_sm.h"
+
+/*
+ * TODO(b:159715784): Implement a more robust solution
+ * to managing PD Policies.
+ */
+
+/*
+ * Default Port Discovery DR Swap Policy.
+ *
+ * 1) If dr_swap_to_dfp_flag == true and port data role is UFP,
+ *    transition to pe_drs_send_swap
+ */
+__overridable bool port_discovery_dr_swap_policy(int port, enum pd_data_role dr,
+						 bool dr_swap_flag)
+{
+	if (dr_swap_flag && dr == PD_ROLE_UFP)
+		return true;
+
+	/* Do not perform a DR swap */
+	return false;
+}
+
+/*
+ * Default Port Discovery VCONN Swap Policy.
+ *
+ * 1) If vconn_swap_to_on_flag == true, and vconn is currently off,
+ * 2) Sourcing VCONN is possible
+ *    then transition to pe_vcs_send_swap
+ */
+__overridable bool port_discovery_vconn_swap_policy(int port,
+						    bool vconn_swap_flag)
+{
+	if (IS_ENABLED(CONFIG_USBC_VCONN) && vconn_swap_flag &&
+	    !tc_is_vconn_src(port) && tc_check_vconn_swap(port))
+		return true;
+
+	/* Do not perform a VCONN swap */
+	return false;
+}
diff --git a/common/usbc/usbc_task.c b/common/usbc/usbc_task.c
index 624c55a651..5d68221b3e 100644
--- a/common/usbc/usbc_task.c
+++ b/common/usbc/usbc_task.c
@@ -1,16 +1,17 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "battery.h"
 #include "battery_smart.h"
-#include "board.h"
+#include "builtin/assert.h"
 #include "charge_manager.h"
 #include "charge_state.h"
 #include "chipset.h"
 #include "common.h"
 #include "console.h"
+#include "cros_version.h"
 #include "ec_commands.h"
 #include "gpio.h"
 #include "hooks.h"
@@ -18,24 +19,35 @@
 #include "registers.h"
 #include "system.h"
 #include "task.h"
+#include "tcpm/tcpm.h"
 #include "timer.h"
-#include "util.h"
 #include "usb_charge.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
-#include "usb_prl_sm.h"
-#include "tcpm.h"
+#include "usb_pd_dpm_sm.h"
+#include "usb_pd_timer.h"
 #include "usb_pe_sm.h"
 #include "usb_prl_sm.h"
 #include "usb_sm.h"
 #include "usb_tc_sm.h"
 #include "usbc_ppc.h"
-#include "version.h"
+#include "util.h"
 
 #define USBC_EVENT_TIMEOUT (5 * MSEC)
+#define USBC_MIN_EVENT_TIMEOUT (1 * MSEC)
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+/*
+ * If CONFIG_ASSERT_CCD_MODE_ON_DTS_CONNECT is not defined then
+ * _GPIO_CCD_MODE_ODL is not needed. Declare as extern so IS_ENABLED will work.
+ */
+#ifndef CONFIG_ASSERT_CCD_MODE_ON_DTS_CONNECT
+extern int _GPIO_CCD_MODE_ODL;
+#else
+#define _GPIO_CCD_MODE_ODL GPIO_CCD_MODE_ODL
+#endif /* CONFIG_ASSERT_CCD_MODE_ON_DTS_CONNECT */
 
 static uint8_t paused[CONFIG_USB_PD_PORT_MAX_COUNT];
 
@@ -44,6 +56,11 @@ void tc_pause_event_loop(int port)
 	paused[port] = 1;
 }
 
+bool tc_event_loop_is_paused(int port)
+{
+	return paused[port];
+}
+
 void tc_start_event_loop(int port)
 {
 	/*
@@ -52,7 +69,7 @@ void tc_start_event_loop(int port)
 	 */
 	if (paused[port]) {
 		paused[port] = 0;
-		task_set_event(PD_PORT_TO_TASK_ID(port), TASK_EVENT_WAKE, 0);
+		task_set_event(PD_PORT_TO_TASK_ID(port), TASK_EVENT_WAKE);
 	}
 }
 
@@ -71,15 +88,40 @@ static void pd_task_init(int port)
 	 */
 	if (IS_ENABLED(CONFIG_HAS_TASK_PD_INT))
 		schedule_deferred_pd_interrupt(port);
+
+	/*
+	 * GPIO_CCD_MODE_ODL must be initialized with GPIO_ODR_HIGH
+	 * when CONFIG_ASSERT_CCD_MODE_ON_DTS_CONNECT is enabled
+	 */
+	if (IS_ENABLED(CONFIG_ASSERT_CCD_MODE_ON_DTS_CONNECT))
+		ASSERT(gpio_get_default_flags(_GPIO_CCD_MODE_ODL) &
+		       GPIO_ODR_HIGH);
+}
+
+static int pd_task_timeout(int port)
+{
+	int timeout;
+
+	if (paused[port])
+		timeout = -1;
+	else {
+		timeout = pd_timer_next_expiration(port);
+		if (timeout < 0 || timeout > USBC_EVENT_TIMEOUT)
+			timeout = USBC_EVENT_TIMEOUT;
+		else if (timeout < USBC_MIN_EVENT_TIMEOUT)
+			timeout = USBC_MIN_EVENT_TIMEOUT;
+	}
+	return timeout;
 }
 
 static bool pd_task_loop(int port)
 {
 	/* wait for next event/packet or timeout expiration */
-	const uint32_t evt =
-		task_wait_event(paused[port]
-					? -1
-					: USBC_EVENT_TIMEOUT);
+	const uint32_t evt = task_wait_event(pd_task_timeout(port));
+
+	/* Manage expired PD Timers on timeouts */
+	if (evt & TASK_EVENT_TIMER)
+		pd_timer_manage_expired(port);
 
 	/*
 	 * Re-use TASK_EVENT_RESET_DONE in tests to restart the USB task
@@ -99,6 +141,10 @@ static bool pd_task_loop(int port)
 	if (IS_ENABLED(CONFIG_USB_PD_TCPC))
 		tcpc_run(port, evt);
 
+	/* Run Device Policy Manager */
+	if (IS_ENABLED(CONFIG_USB_DPM_SM))
+		dpm_run(port, evt, tc_get_pd_enabled(port));
+
 	/* Run policy engine state machine */
 	if (IS_ENABLED(CONFIG_USB_PE_SM))
 		pe_run(port, evt, tc_get_pd_enabled(port));
@@ -124,7 +170,12 @@ void pd_task(void *u)
 	if (port >= board_get_usb_pd_port_count())
 		return;
 
+#if CONFIG_USB_PD_STARTUP_DELAY_MS > 0
+	msleep(CONFIG_USB_PD_STARTUP_DELAY_MS);
+#endif
+
 	while (1) {
+		pd_timer_init(port);
 		pd_task_init(port);
 
 		/* As long as pd_task_loop returns true, keep running the loop.
diff --git a/common/usbc_intr_task.c b/common/usbc_intr_task.c
index ca410363f1..68190aff4b 100644
--- a/common/usbc_intr_task.c
+++ b/common/usbc_intr_task.c
@@ -1,51 +1,103 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* High-priority interrupt tasks implementations */
 
+/*
+ * TODO(b/272518464): Work around coreboot GCC preprocessor bug.
+ * #line marks the *next* line, so it is off by one.
+ */
+#line 13
+
+#include "builtin/assert.h"
+#include "common.h"
+#include "compile_time_macros.h"
 #include "console.h"
+#include "ec_commands.h"
 #include "task.h"
+#include "tcpm/tcpm.h"
 #include "timer.h"
-#include "usb_mux.h"
 #include "usb_pd.h"
+#include "usb_pd_tcpm.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#include <stdint.h>
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 /* Events for pd_interrupt_handler_task */
-#define PD_PROCESS_INTERRUPT  BIT(0)
+#define PD_PROCESS_INTERRUPT BIT(0)
 
 /*
- * Theoretically, we may need to support up to 480 USB-PD packets per second for
- * intensive operations such as FW update over PD. This value has tested well
- * preventing watchdog resets with a single bad port partner plugged in.
+ * Theoretically, we may need to support up to 1800 USB-PD packets per second
+ * for intensive operations such as BIST compliance tests. This value has tested
+ * well preventing watchdog resets with a single bad port partner plugged in.
  */
-#define ALERT_STORM_MAX_COUNT   480
-#define ALERT_STORM_INTERVAL    SECOND
+#define ALERT_STORM_MAX_COUNT 1800
+#define ALERT_STORM_INTERVAL SECOND
 
 static uint8_t pd_int_task_id[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 void schedule_deferred_pd_interrupt(const int port)
 {
-	task_set_event(pd_int_task_id[port], PD_PROCESS_INTERRUPT, 0);
+	/*
+	 * Don't set event to idle task if task id is 0. This happens when
+	 * not all the port have pd int task, the pd_int_task_id of port
+	 * that doesn't have pd int task is 0.
+	 */
+	if (pd_int_task_id[port] != 0)
+		task_set_event(pd_int_task_id[port], PD_PROCESS_INTERRUPT);
+}
+
+static struct {
+	int count;
+	timestamp_t time;
+} storm_tracker[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+static void service_one_port(int port)
+{
+	timestamp_t now;
+
+	tcpc_alert(port);
+
+	now = get_time();
+	if (timestamp_expired(storm_tracker[port].time, &now)) {
+		/* Reset timer into future */
+		storm_tracker[port].time.val = now.val + ALERT_STORM_INTERVAL;
+
+		/*
+		 * Start at 1 since we are processing an interrupt right
+		 * now
+		 */
+		storm_tracker[port].count = 1;
+	} else if (++storm_tracker[port].count > ALERT_STORM_MAX_COUNT) {
+		CPRINTS("C%d: Interrupt storm detected."
+			" Disabling port temporarily",
+			port);
+
+		pd_set_suspend(port, 1);
+		pd_deferred_resume(port);
+	}
+}
+
+__overridable void board_process_pd_alert(int port)
+{
 }
 
 /*
- * Main task entry point that handles PD interrupts for a single port
+ * Main task entry point that handles PD interrupts for a single port.  These
+ * interrupts usually come from a TCPC, but may also come from PD-related chips
+ * sharing the TCPC interrupt line.
  *
  * @param p The PD port number for which to handle interrupts (pointer is
  * reinterpreted as an integer directly).
  */
 void pd_interrupt_handler_task(void *p)
 {
-	const int port = (int) ((intptr_t) p);
+	const int port = (int)((intptr_t)p);
 	const int port_mask = (PD_STATUS_TCPC_ALERT_0 << port);
-	struct {
-		int count;
-		timestamp_t time;
-	} storm_tracker[CONFIG_USB_PD_PORT_MAX_COUNT] = {};
 
 	ASSERT(port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 
@@ -60,46 +112,108 @@ void pd_interrupt_handler_task(void *p)
 	while (1) {
 		const int evt = task_wait_event(-1);
 
-		if (evt & PD_PROCESS_INTERRUPT) {
-			/*
-			 * While the interrupt signal is asserted; we have more
-			 * work to do. This effectively makes the interrupt a
-			 * level-interrupt instead of an edge-interrupt without
-			 * having to enable/disable a real level-interrupt in
-			 * multiple locations.
-			 *
-			 * Also, if the port is disabled do not process
-			 * interrupts. Upon existing suspend, we schedule a
-			 * PD_PROCESS_INTERRUPT to check if we missed anything.
-			 */
-			while ((tcpc_get_alert_status() & port_mask) &&
-					pd_is_port_enabled(port)) {
-				timestamp_t now;
-
-				tcpc_alert(port);
-
-				now = get_time();
-				if (timestamp_expired(storm_tracker[port].time,
-						      &now)) {
-					/* Reset timer into future */
-					storm_tracker[port].time.val =
-						now.val + ALERT_STORM_INTERVAL;
-
-					/*
-					 * Start at 1 since we are processing an
-					 * interrupt right now
-					 */
-					storm_tracker[port].count = 1;
-				} else if (++storm_tracker[port].count >
-							ALERT_STORM_MAX_COUNT) {
-					CPRINTS("C%d: Interrupt storm detected."
-						" Disabling port temporarily",
-						port);
-
-					pd_set_suspend(port, 1);
-					pd_deferred_resume(port);
+		if ((evt & PD_PROCESS_INTERRUPT) == 0)
+			continue;
+		/*
+		 * While the interrupt signal is asserted; we have more
+		 * work to do. This effectively makes the interrupt a
+		 * level-interrupt instead of an edge-interrupt without
+		 * having to enable/disable a real level-interrupt in
+		 * multiple locations.
+		 *
+		 * Also, if the port is disabled do not process
+		 * interrupts. Upon existing suspend, we schedule a
+		 * PD_PROCESS_INTERRUPT to check if we missed anything.
+		 */
+		while ((tcpc_get_alert_status() & port_mask) &&
+		       pd_is_port_enabled(port)) {
+			service_one_port(port);
+		}
+
+		board_process_pd_alert(port);
+	}
+}
+
+/*
+ * This code assumes port alert masks are adjacent to each other.
+ */
+BUILD_ASSERT(PD_STATUS_TCPC_ALERT_3 == (PD_STATUS_TCPC_ALERT_0 << 3));
+
+/*
+ * Shared TCPC interrupt handler. The function argument in ec.tasklist
+ * is the mask of ports to handle. For example:
+ *
+ *    BIT(USBC_PORT_C2) | BIT(USBC_PORT_C0)
+ *
+ * Note that this bitmask is 0-based while PD_STATUS_TCPC_ALERT_<port>
+ * is not.
+ */
+
+#if !defined(CONFIG_ZEPHYR) || defined(CONFIG_HAS_TASK_PD_INT_SHARED)
+void pd_shared_alert_task(void *p)
+{
+	const int sources_mask = (int)((intptr_t)p);
+	int want_alerts = 0;
+	int port;
+	int port_mask;
+
+	CPRINTS("%s: port mask 0x%02x", __func__, sources_mask);
+
+	for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) {
+		if ((sources_mask & BIT(port)) == 0)
+			continue;
+		if (!board_is_usb_pd_port_present(port))
+			continue;
+
+		port_mask = PD_STATUS_TCPC_ALERT_0 << port;
+		want_alerts |= port_mask;
+		pd_int_task_id[port] = task_get_current();
+	}
+
+	if (want_alerts == 0) {
+		/*
+		 * None of the configured alert sources are available.
+		 */
+		return;
+	}
+
+	while (1) {
+		const int evt = task_wait_event(-1);
+		int have_alerts;
+
+		if ((evt & PD_PROCESS_INTERRUPT) == 0)
+			continue;
+
+		/*
+		 * While the interrupt signal is asserted; we have more
+		 * work to do. This effectively makes the interrupt a
+		 * level-interrupt instead of an edge-interrupt without
+		 * having to enable/disable a real level-interrupt in
+		 * multiple locations.
+		 *
+		 * Also, if the port is disabled do not process
+		 * interrupts. Upon existing suspend, we schedule a
+		 * PD_PROCESS_INTERRUPT to check if we missed anything.
+		 */
+		do {
+			have_alerts = tcpc_get_alert_status();
+			have_alerts &= want_alerts;
+
+			for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT;
+			     ++port) {
+				port_mask = PD_STATUS_TCPC_ALERT_0 << port;
+				if ((have_alerts & port_mask) == 0) {
+					/* skip quiet port */
+					continue;
 				}
+				if (!pd_is_port_enabled(port)) {
+					/* filter out disabled port */
+					have_alerts &= ~port_mask;
+					continue;
+				}
+				service_one_port(port);
 			}
-		}
+		} while (have_alerts != 0);
 	}
 }
+#endif /* !CONFIG_ZEPHYR || CONFIG_HAS_TASK_PD_INT_SHARED */
diff --git a/common/usbc_ocp.c b/common/usbc_ocp.c
new file mode 100644
index 0000000000..406deb2b20
--- /dev/null
+++ b/common/usbc_ocp.c
@@ -0,0 +1,171 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* USB-C Overcurrent Protection Common Code */
+
+#include "atomic.h"
+#include "common.h"
+#include "console.h"
+#include "hooks.h"
+#include "timer.h"
+#include "usb_common.h"
+#include "usb_pd.h"
+#include "usbc_ocp.h"
+#include "util.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+/*
+ * Number of seconds until a latched-off port is re-enabled for sourcing after
+ * detecting a physical disconnect.
+ */
+#define OCP_COOLDOWN_DELAY_US (2 * SECOND)
+
+/*
+ * A per-port table that indicates how many VBUS overcurrent events have
+ * occurred.  This table is cleared after detecting a physical disconnect of the
+ * sink.
+ */
+static uint8_t oc_event_cnt_tbl[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+/* A flag for ports with sink device connected. */
+static atomic_t snk_connected_ports;
+
+static void clear_oc_tbl(void)
+{
+	int port;
+
+	for (port = 0; port < board_get_usb_pd_port_count(); port++)
+		/*
+		 * Only clear the table if the port partner is no longer
+		 * attached after debouncing.
+		 */
+		if ((!(BIT(port) & (uint32_t)snk_connected_ports)) &&
+		    oc_event_cnt_tbl[port]) {
+			oc_event_cnt_tbl[port] = 0;
+			CPRINTS("C%d: OC events cleared", port);
+		}
+}
+DECLARE_DEFERRED(clear_oc_tbl);
+
+static atomic_t port_oc_reset_req;
+
+static void re_enable_ports(void)
+{
+	uint32_t ports = atomic_clear(&port_oc_reset_req);
+
+	while (ports) {
+		int port = __fls(ports);
+
+		ports &= ~BIT(port);
+
+		/*
+		 * Let the board know that the overcurrent is
+		 * over since we've completed our recovery actions by now.
+		 */
+		board_overcurrent_event(port, 0);
+
+		/* Queue up an Alert message for the partner */
+		pd_send_alert_msg(port, ADO_OCP_EVENT);
+	}
+}
+DECLARE_DEFERRED(re_enable_ports);
+
+int usbc_ocp_add_event(int port)
+{
+	int delay = 0;
+
+	if ((port < 0) || (port >= board_get_usb_pd_port_count())) {
+		CPRINTS("%s(%d) Invalid port!", __func__, port);
+		return EC_ERROR_INVAL;
+	}
+
+	/* Let the board specific code know about the OC event. */
+	board_overcurrent_event(port, 1);
+
+	oc_event_cnt_tbl[port]++;
+
+	/* The port overcurrented, so don't clear it's OC events. */
+	atomic_clear_bits(&snk_connected_ports, 1 << port);
+
+	if (oc_event_cnt_tbl[port] >= OCP_MAX_CNT) {
+		CPRINTS("C%d: OC event limit reached! "
+			"Source path disabled until physical disconnect.",
+			port);
+		pd_power_supply_reset(port);
+	} else if (oc_event_cnt_tbl[port] <= OCP_HR_CNT) {
+		/*
+		 * Hard reset for the first few offenses, sending an alert after
+		 * at least the time we need to hard reset and make a new
+		 * contract.
+		 */
+		pd_send_hard_reset(port);
+		delay = PD_T_SRC_RECOVER + 100 * MSEC;
+	} else {
+		/*
+		 * ErrorRecovery must be performed past the third OCP event,
+		 * queueing up the alert for after it completes and a new
+		 * contract is in place
+		 */
+		pd_set_error_recovery(port);
+		delay = PD_T_ERROR_RECOVERY + 100 * MSEC;
+	}
+
+	if (delay) {
+		atomic_or(&port_oc_reset_req, BIT(port));
+		hook_call_deferred(&re_enable_ports_data, delay);
+	}
+
+	return EC_SUCCESS;
+}
+
+int usbc_ocp_clear_event_counter(int port)
+{
+	if ((port < 0) || (port >= board_get_usb_pd_port_count())) {
+		CPRINTS("%s(%d) Invalid port!", __func__, port);
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * If we are clearing our event table in quick succession, we may be in
+	 * an overcurrent loop where we are also detecting a disconnect on the
+	 * CC pins.  Therefore, let's not clear it just yet and the let the
+	 * limit be reached.  This way, we won't send the hard reset and
+	 * actually detect the physical disconnect.
+	 */
+	if (oc_event_cnt_tbl[port]) {
+		hook_call_deferred(&clear_oc_tbl_data, OCP_COOLDOWN_DELAY_US);
+	}
+	return EC_SUCCESS;
+}
+
+int usbc_ocp_is_port_latched_off(int port)
+{
+	if ((port < 0) || (port >= board_get_usb_pd_port_count())) {
+		CPRINTS("%s(%d) Invalid port!", __func__, port);
+		return 0;
+	}
+
+	return oc_event_cnt_tbl[port] >= OCP_MAX_CNT;
+}
+
+void usbc_ocp_snk_is_connected(int port, bool connected)
+{
+	if ((port < 0) || (port >= board_get_usb_pd_port_count())) {
+		CPRINTS("%s(%d) Invalid port!", __func__, port);
+		return;
+	}
+
+	if (connected)
+		atomic_or(&snk_connected_ports, 1 << port);
+	else
+		atomic_clear_bits(&snk_connected_ports, 1 << port);
+}
+
+__overridable void board_overcurrent_event(int port, int is_overcurrented)
+{
+	/* Do nothing by default.  Boards with overcurrent GPIOs may override */
+}
diff --git a/common/usbc_ppc.c b/common/usbc_ppc.c
index 7a334ae439..7063dfb93a 100644
--- a/common/usbc_ppc.c
+++ b/common/usbc_ppc.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,43 +10,44 @@
 #include "console.h"
 #include "hooks.h"
 #include "timer.h"
+#include "usb_pd.h"
 #include "usbc_ppc.h"
 #include "util.h"
 
-#ifndef TEST_BUILD
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#ifndef TEST_LEGACY_BUILD
+/*
+ * We limit the CPRINTF/S invocations to all builds that are not
+ * legacy test builds because they dont build otherwise.
+ */
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 #else
-#define CPRINTF(args...)
-#define CPRINTS(args...)
+#define CPRINTF(format, args...)
+#define CPRINTS(format, args...)
 #endif
 
 int ppc_prints(const char *string, int port)
 {
-#ifndef TEST_BUILD
-	return CPRINTS("ppc p%d %s", port, string);
-#else
+#if defined(TEST_LEGACY_BUILD) || !defined(CONFIG_USBC_PPC_LOGGING)
 	return 0;
-#endif
+#else
+	return CPRINTS("ppc p%d %s", port, string);
+#endif /* defined(TEST_LEGACY_BUILD) || !defined(CONFIG_USBC_PPC_LOGGING) */
 }
 
 int ppc_err_prints(const char *string, int port, int error)
 {
-#ifndef TEST_BUILD
-	return CPRINTS("ppc p%d %s (%d)", port, string, error);
-#else
+#if defined(TEST_LEGACY_BUILD) || !defined(CONFIG_USBC_PPC_LOGGING)
 	return 0;
-#endif
+#else
+	return CPRINTS("ppc p%d %s (%d)", port, string, error);
+#endif /* defined(TEST_LEGACY_BUILD) || !defined(CONFIG_USBC_PPC_LOGGING) */
 }
 
-/*
- * A per-port table that indicates how many VBUS overcurrent events have
- * occurred.  This table is cleared after detecting a physical disconnect of the
- * sink.
- */
-static uint8_t oc_event_cnt_tbl[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-static uint32_t connected_ports;
+__overridable bool board_port_has_ppc(int port)
+{
+	return true;
+}
 
 /* Simple wrappers to dispatch to the drivers. */
 
@@ -55,6 +56,9 @@ int ppc_init(int port)
 	int rv = EC_ERROR_UNIMPLEMENTED;
 	const struct ppc_config_t *ppc;
 
+	if (!board_port_has_ppc(port))
+		return EC_SUCCESS;
+
 	if ((port < 0) || (port >= ppc_cnt)) {
 		CPRINTS("%s(%d) Invalid port!", __func__, port);
 		return EC_ERROR_INVAL;
@@ -72,64 +76,7 @@ int ppc_init(int port)
 	return rv;
 }
 
-int ppc_add_oc_event(int port)
-{
-	if ((port < 0) || (port >= ppc_cnt)) {
-		CPRINTS("%s(%d) Invalid port!", __func__, port);
-		return EC_ERROR_INVAL;
-	}
-
-	oc_event_cnt_tbl[port]++;
-
-	/* The port overcurrented, so don't clear it's OC events. */
-	deprecated_atomic_clear_bits(&connected_ports, 1 << port);
-
-	if (oc_event_cnt_tbl[port] >= PPC_OC_CNT_THRESH)
-		ppc_prints("OC event limit reached! "
-			"Source path disabled until physical disconnect.",
-			port);
-	return EC_SUCCESS;
-}
-
-static void clear_oc_tbl(void)
-{
-	int port;
-
-	for (port = 0; port < ppc_cnt; port++)
-		/*
-		 * Only clear the table if the port partner is no longer
-		 * attached after debouncing.
-		 */
-		if ((!(BIT(port) & connected_ports)) &&
-		    oc_event_cnt_tbl[port]) {
-			oc_event_cnt_tbl[port] = 0;
-			ppc_prints("OC events cleared", port);
-		}
-}
-DECLARE_DEFERRED(clear_oc_tbl);
-
-int ppc_clear_oc_event_counter(int port)
-{
-	if ((port < 0) || (port >= ppc_cnt)) {
-		CPRINTS("%s(%d) Invalid port!", __func__, port);
-		return EC_ERROR_INVAL;
-	}
-
-	/*
-	 * If we are clearing our event table in quick succession, we may be in
-	 * an overcurrent loop where we are also detecting a disconnect on the
-	 * CC pins.  Therefore, let's not clear it just yet and the let the
-	 * limit be reached.  This way, we won't send the hard reset and
-	 * actually detect the physical disconnect.
-	 */
-	if (oc_event_cnt_tbl[port]) {
-		hook_call_deferred(&clear_oc_tbl_data,
-				   PPC_OC_COOLDOWN_DELAY_US);
-	}
-	return EC_SUCCESS;
-}
-
-int ppc_is_sourcing_vbus(int port)
+test_mockable int ppc_is_sourcing_vbus(int port)
 {
 	int rv = 0;
 	const struct ppc_config_t *ppc;
@@ -152,6 +99,9 @@ int ppc_set_polarity(int port, int polarity)
 	int rv = EC_ERROR_UNIMPLEMENTED;
 	const struct ppc_config_t *ppc;
 
+	if (!board_port_has_ppc(port))
+		return EC_SUCCESS;
+
 	if ((port < 0) || (port >= ppc_cnt)) {
 		CPRINTS("%s(%d) Invalid port!", __func__, port);
 		return EC_ERROR_INVAL;
@@ -170,6 +120,9 @@ int ppc_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp)
 	int rv = EC_ERROR_UNIMPLEMENTED;
 	const struct ppc_config_t *ppc;
 
+	if (!board_port_has_ppc(port))
+		return EC_SUCCESS;
+
 	if ((port < 0) || (port >= ppc_cnt)) {
 		CPRINTS("%s(%d) Invalid port!", __func__, port);
 		return EC_ERROR_INVAL;
@@ -199,22 +152,15 @@ int ppc_discharge_vbus(int port, int enable)
 	return rv;
 }
 
-int ppc_is_port_latched_off(int port)
-{
-	if ((port < 0) || (port >= ppc_cnt)) {
-		CPRINTS("%s(%d) Invalid port!", __func__, port);
-		return 0;
-	}
-
-	return oc_event_cnt_tbl[port] >= PPC_OC_CNT_THRESH;
-}
-
 #ifdef CONFIG_USBC_PPC_SBU
 int ppc_set_sbu(int port, int enable)
 {
 	int rv = EC_ERROR_UNIMPLEMENTED;
 	const struct ppc_config_t *ppc;
 
+	if (!board_port_has_ppc(port))
+		return EC_SUCCESS;
+
 	if ((port < 0) || (port >= ppc_cnt)) {
 		CPRINTS("%s(%d) Invalid port!", __func__, port);
 		return EC_ERROR_INVAL;
@@ -234,20 +180,14 @@ int ppc_set_vconn(int port, int enable)
 	int rv = EC_ERROR_UNIMPLEMENTED;
 	const struct ppc_config_t *ppc;
 
+	if (!board_port_has_ppc(port))
+		return EC_SUCCESS;
+
 	if ((port < 0) || (port >= ppc_cnt)) {
 		CPRINTS("%s(%d) Invalid port!", __func__, port);
 		return EC_ERROR_INVAL;
 	}
 
-	/*
-	 * Check our OC event counter.  If we've exceeded our threshold, then
-	 * let's latch our source path off to prevent continuous cycling.  When
-	 * the PD state machine detects a disconnection on the CC lines, we will
-	 * reset our OC event counter.
-	 */
-	if (enable && ppc_is_port_latched_off(port))
-		return EC_ERROR_ACCESS_DENIED;
-
 	ppc = &ppc_chips[port];
 	if (ppc->drv->set_vconn)
 		rv = ppc->drv->set_vconn(port, enable);
@@ -256,17 +196,24 @@ int ppc_set_vconn(int port, int enable)
 }
 #endif
 
-void ppc_sink_is_connected(int port, int is_connected)
+int ppc_dev_is_connected(int port, enum ppc_device_role dev)
 {
+	int rv = EC_SUCCESS;
+	const struct ppc_config_t *ppc;
+
+	if (!board_port_has_ppc(port))
+		return EC_SUCCESS;
+
 	if ((port < 0) || (port >= ppc_cnt)) {
 		CPRINTS("%s(%d) Invalid port!", __func__, port);
-		return;
+		return EC_ERROR_INVAL;
 	}
 
-	if (is_connected)
-		deprecated_atomic_or(&connected_ports, 1 << port);
-	else
-		deprecated_atomic_clear_bits(&connected_ports, 1 << port);
+	ppc = &ppc_chips[port];
+	if (ppc->drv->dev_is_connected)
+		rv = ppc->drv->dev_is_connected(port, dev);
+
+	return rv;
 }
 
 int ppc_vbus_sink_enable(int port, int enable)
@@ -313,15 +260,6 @@ int ppc_vbus_source_enable(int port, int enable)
 		return EC_ERROR_INVAL;
 	}
 
-	/*
-	 * Check our OC event counter.  If we've exceeded our threshold, then
-	 * let's latch our source path off to prevent continuous cycling.  When
-	 * the PD state machine detects a disconnection on the CC lines, we will
-	 * reset our OC event counter.
-	 */
-	if (enable && ppc_is_port_latched_off(port))
-		return EC_ERROR_ACCESS_DENIED;
-
 	ppc = &ppc_chips[port];
 	if (ppc->drv->vbus_source_enable)
 		rv = ppc->drv->vbus_source_enable(port, enable);
@@ -343,7 +281,7 @@ int ppc_set_frs_enable(int port, int enable)
 	ppc = &ppc_chips[port];
 
 	if (ppc->drv->set_frs_enable)
-		rv = ppc->drv->set_frs_enable(port,enable);
+		rv = ppc->drv->set_frs_enable(port, enable);
 
 	return rv;
 }
@@ -370,7 +308,7 @@ int ppc_is_vbus_present(int port)
 #endif /* defined(CONFIG_USB_PD_VBUS_DETECT_PPC) */
 
 #ifdef CONFIG_CMD_PPC_DUMP
-static int command_ppc_dump(int argc, char **argv)
+static int command_ppc_dump(int argc, const char **argv)
 {
 	int port;
 	int rv = EC_ERROR_UNIMPLEMENTED;
diff --git a/common/util.c b/common/util.c
index ed5b87c2c9..7672dc1325 100644
--- a/common/util.c
+++ b/common/util.c
@@ -1,149 +1,19 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Utility functions for Chrome EC */
 
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
 #include "util.h"
 
-__stdlib_compat size_t strlen(const char *s)
+int find_base(int base, int *c, const char **nptr)
 {
-	int len = 0;
-
-	while (*s++)
-		len++;
-
-	return len;
-}
-
-
-__stdlib_compat size_t strnlen(const char *s, size_t maxlen)
-{
-	size_t len = 0;
-
-	while (len < maxlen && *s) {
-		s++;
-		len++;
-	}
-	return len;
-}
-
-
-__stdlib_compat int isspace(int c)
-{
-	return c == ' ' || c == '\t' || c == '\r' || c == '\n';
-}
-
-
-__stdlib_compat int isdigit(int c)
-{
-	return c >= '0' && c <= '9';
-}
-
-
-__stdlib_compat int isalpha(int c)
-{
-	return (c >= 'A' && c <= 'Z') || (c >= 'a' && c <= 'z');
-}
-
-__stdlib_compat int isupper(int c)
-{
-	return c >= 'A' && c <= 'Z';
-}
-
-__stdlib_compat int isprint(int c)
-{
-	return c >= ' ' && c <= '~';
-}
-
-__stdlib_compat int tolower(int c)
-{
-	return c >= 'A' && c <= 'Z' ? c + 'a' - 'A' : c;
-}
-
-
-__stdlib_compat int strcasecmp(const char *s1, const char *s2)
-{
-	int diff;
-
-	do {
-		diff = tolower(*s1) - tolower(*s2);
-		if (diff)
-			return diff;
-	} while (*(s1++) && *(s2++));
-	return 0;
-}
-
-
-__stdlib_compat int strncasecmp(const char *s1, const char *s2, size_t size)
-{
-	int diff;
-
-	if (!size)
-		return 0;
-
-	do {
-		diff = tolower(*s1) - tolower(*s2);
-		if (diff)
-			return diff;
-	} while (*(s1++) && *(s2++) && --size);
-	return 0;
-}
-
-
-__stdlib_compat char *strstr(const char *s1, const char *s2)
-{
-	const char *p, *q, *r;
-	size_t len1 = strlen(s1);
-	size_t len2 = strlen(s2);
-
-	if (len1 == 0 || len2 == 0 || len1 < len2)
-		return NULL;
-
-	r = s1 + len1 - len2 + 1;
-	for (; s1 < r; s1++) {
-		if (*s1 == *s2) {
-			p = s1 + 1;
-			q = s2 + 1;
-			for (; q < s2 + len2;) {
-				if (*p++ != *q++)
-					break;
-			}
-			if (*q == '\0')
-				return (char *)s1;
-		}
-	}
-	return NULL;
-}
-
-__stdlib_compat int atoi(const char *nptr)
-{
-	int result = 0;
-	int neg = 0;
-	char c = '\0';
-
-	while ((c = *nptr++) && isspace(c))
-		;
-
-	if (c == '-') {
-		neg = 1;
-		c = *nptr++;
-	}
-
-	while (isdigit(c)) {
-		result = result * 10 + (c - '0');
-		c = *nptr++;
-	}
-
-	return neg ? -result : result;
-}
-
-static int find_base(int base, int *c, const char **nptr) {
-	if ((base == 0 || base == 16) && *c == '0'
-	    && (**nptr == 'x' || **nptr == 'X')) {
+	if ((base == 0 || base == 16) && *c == '0' &&
+	    (**nptr == 'x' || **nptr == 'X')) {
 		*c = (*nptr)[1];
 		(*nptr) += 2;
 		base = 16;
@@ -153,9 +23,8 @@ static int find_base(int base, int *c, const char **nptr) {
 	return base;
 }
 
-
 /* Like strtol(), but for integers */
-__stdlib_compat int strtoi(const char *nptr, char **endptr, int base)
+int strtoi(const char *nptr, char **endptr, int base)
 {
 	int result = 0;
 	int neg = 0;
@@ -191,54 +60,20 @@ __stdlib_compat int strtoi(const char *nptr, char **endptr, int base)
 	return neg ? -result : result;
 }
 
-__stdlib_compat uint64_t strtoul(const char *nptr, char **endptr, int base)
-{
-	uint64_t result = 0;
-	int c = '\0';
-
-	while ((c = *nptr++) && isspace(c))
-		;
-
-	if (c == '+') {
-		c = *nptr++;
-	} else if (c == '-') {
-		if (endptr)
-			*endptr = (char *)nptr - 1;
-		return result;
-	}
-	
-	base = find_base(base, &c, &nptr);
-
-	while (c) {
-		if (c >= '0' && c < '0' + MIN(base, 10))
-			result = result * base + (c - '0');
-		else if (c >= 'A' && c < 'A' + base - 10)
-			result = result * base + (c - 'A' + 10);
-		else if (c >= 'a' && c < 'a' + base - 10)
-			result = result * base + (c - 'a' + 10);
-		else
-			break;
-
-		c = *nptr++;
-	}
-
-	if (endptr)
-		*endptr = (char *)nptr - 1;
-	return result;
-}
-
-__stdlib_compat int parse_bool(const char *s, int *dest)
+int parse_bool(const char *s, int *dest)
 {
 	/* off, disable, false, no */
 	if (!strcasecmp(s, "off") || !strncasecmp(s, "dis", 3) ||
-	    tolower(*s) == 'f' || tolower(*s) == 'n') {
+	    tolower((unsigned char)*s) == 'f' ||
+	    tolower((unsigned char)*s) == 'n') {
 		*dest = 0;
 		return 1;
 	}
 
 	/* on, enable, true, yes */
 	if (!strcasecmp(s, "on") || !strncasecmp(s, "ena", 3) ||
-	    tolower(*s) == 't' || tolower(*s) == 'y') {
+	    tolower((unsigned char)*s) == 't' ||
+	    tolower((unsigned char)*s) == 'y') {
 		*dest = 1;
 		return 1;
 	}
@@ -247,21 +82,6 @@ __stdlib_compat int parse_bool(const char *s, int *dest)
 	return 0;
 }
 
-__stdlib_compat int memcmp(const void *s1, const void *s2, size_t len)
-{
-	const char *sa = s1;
-	const char *sb = s2;
-
-	int diff = 0;
-	while (len-- > 0) {
-		diff = *(sa++) - *(sb++);
-		if (diff)
-			return diff;
-	}
-
-	return 0;
-}
-
 /* Constant-time memory comparison */
 int safe_memcmp(const void *s1, const void *s2, size_t size)
 {
@@ -282,160 +102,6 @@ int safe_memcmp(const void *s1, const void *s2, size_t size)
 	return result != 0;
 }
 
-#if !(__has_feature(address_sanitizer) || __has_feature(memory_sanitizer))
-__stdlib_compat void *memcpy(void *dest, const void *src, size_t len)
-{
-	char *d = (char *)dest;
-	const char *s = (const char *)src;
-	uint32_t *dw;
-	const uint32_t *sw;
-	char *head;
-	char * const tail = (char *)dest + len;
-	/* Set 'body' to the last word boundary */
-	uint32_t * const body = (uint32_t *)((uintptr_t)tail & ~3);
-
-	if (((uintptr_t)dest & 3) != ((uintptr_t)src & 3)) {
-		/* Misaligned. no body, no tail. */
-		head = tail;
-	} else {
-		/* Aligned */
-		if ((uintptr_t)tail < (((uintptr_t)d + 3) & ~3))
-			/* len is shorter than the first word boundary */
-			head = tail;
-		else
-			/* Set 'head' to the first word boundary */
-			head = (char *)(((uintptr_t)d + 3) & ~3);
-	}
-
-	/* Copy head */
-	while (d < head)
-		*(d++) = *(s++);
-
-	/* Copy body */
-	dw = (uint32_t *)d;
-	sw = (uint32_t *)s;
-	while (dw < body)
-		*(dw++) = *(sw++);
-
-	/* Copy tail */
-	d = (char *)dw;
-	s = (const char *)sw;
-	while (d < tail)
-		*(d++) = *(s++);
-
-	return dest;
-}
-#endif /* address_sanitizer || memory_sanitizer */
-
-
-#if !(__has_feature(address_sanitizer) || __has_feature(memory_sanitizer))
-__stdlib_compat __visible void *memset(void *dest, int c, size_t len)
-{
-	char *d = (char *)dest;
-	uint32_t cccc;
-	uint32_t *dw;
-	char *head;
-	char * const tail = (char *)dest + len;
-	/* Set 'body' to the last word boundary */
-	uint32_t * const body = (uint32_t *)((uintptr_t)tail & ~3);
-
-	c &= 0xff;	/* Clear upper bits before ORing below */
-	cccc = c | (c << 8) | (c << 16) | (c << 24);
-
-	if ((uintptr_t)tail < (((uintptr_t)d + 3) & ~3))
-		/* len is shorter than the first word boundary */
-		head = tail;
-	else
-		/* Set 'head' to the first word boundary */
-		head = (char *)(((uintptr_t)d + 3) & ~3);
-
-	/* Copy head */
-	while (d < head)
-		*(d++) = c;
-
-	/* Copy body */
-	dw = (uint32_t *)d;
-	while (dw < body)
-		*(dw++) = cccc;
-
-	/* Copy tail */
-	d = (char *)dw;
-	while (d < tail)
-		*(d++) = c;
-
-	return dest;
-}
-#endif /* address_sanitizer || memory_sanitizer */
-
-
-#if !(__has_feature(address_sanitizer) || __has_feature(memory_sanitizer))
-__stdlib_compat void *memmove(void *dest, const void *src, size_t len)
-{
-	if ((uintptr_t)dest <= (uintptr_t)src ||
-	    (uintptr_t)dest >= (uintptr_t)src + len) {
-		/* Start of destination doesn't overlap source, so just use
-		 * memcpy(). */
-		return memcpy(dest, src, len);
-	} else {
-		/* Need to copy from tail because there is overlap. */
-		char *d = (char *)dest + len;
-		const char *s = (const char *)src + len;
-		uint32_t *dw;
-		const uint32_t *sw;
-		char *head;
-		char * const tail = (char *)dest;
-		/* Set 'body' to the last word boundary */
-		uint32_t * const body = (uint32_t *)(((uintptr_t)tail+3) & ~3);
-
-		if (((uintptr_t)dest & 3) != ((uintptr_t)src & 3)) {
-			/* Misaligned. no body, no tail. */
-			head = tail;
-		} else {
-			/* Aligned */
-			if ((uintptr_t)tail > ((uintptr_t)d & ~3))
-				/* Shorter than the first word boundary */
-				head = tail;
-			else
-				/* Set 'head' to the first word boundary */
-				head = (char *)((uintptr_t)d & ~3);
-		}
-
-		/* Copy head */
-		while (d > head)
-			*(--d) = *(--s);
-
-		/* Copy body */
-		dw = (uint32_t *)d;
-		sw = (uint32_t *)s;
-		while (dw > body)
-			*(--dw) = *(--sw);
-
-		/* Copy tail */
-		d = (char *)dw;
-		s = (const char *)sw;
-		while (d > tail)
-			*(--d) = *(--s);
-
-		return dest;
-	}
-}
-#endif /* address_sanitizer || memory_sanitizer */
-
-
-__stdlib_compat void *memchr(const void *buffer, int c, size_t n)
-{
-	char *current = (char *)buffer;
-	char *end = current + n;
-
-	while (current != end) {
-		if (*current == c)
-			return current;
-		current++;
-	}
-	return NULL;
-}
-
-
 void reverse(void *dest, size_t len)
 {
 	int i;
@@ -450,8 +116,7 @@ void reverse(void *dest, size_t len)
 	}
 }
 
-
-__stdlib_compat char *strzcpy(char *dest, const char *src, int len)
+char *strzcpy(char *dest, const char *src, int len)
 {
 	char *d = dest;
 	if (len <= 0)
@@ -464,36 +129,6 @@ __stdlib_compat char *strzcpy(char *dest, const char *src, int len)
 	return dest;
 }
 
-
-__stdlib_compat char *strncpy(char *dest, const char *src, size_t n)
-{
-	char *d = dest;
-
-	while (n && *src) {
-		*d++ = *src++;
-		n--;
-	}
-	if (n)
-		*d = '\0';
-	return dest;
-}
-
-
-__stdlib_compat int strncmp(const char *s1, const char *s2, size_t n)
-{
-	while (n--) {
-		if (*s1 != *s2)
-			return *s1 - *s2;
-		if (!*s1)
-			break;
-		s1++;
-		s2++;
-
-	}
-	return 0;
-}
-
-
 int uint64divmod(uint64_t *n, int d)
 {
 	uint64_t q = 0, mask;
@@ -566,13 +201,19 @@ bool is_aligned(uint32_t addr, uint32_t align)
 	return (addr & (align - 1)) == 0;
 }
 
+int alignment_log2(unsigned int x)
+{
+	ASSERT(x != 0); /* ctz(0) is undefined */
+	return __builtin_ctz(x);
+}
+
 /****************************************************************************/
 /* stateful conditional stuff */
 
 enum cond_internal_bits {
-	COND_CURR_MASK = BIT(0),		/* current value */
-	COND_RISE_MASK = BIT(1),		/* set if 0->1 */
-	COND_FALL_MASK = BIT(2),		/* set if 1->0 */
+	COND_CURR_MASK = BIT(0), /* current value */
+	COND_RISE_MASK = BIT(1), /* set if 0->1 */
+	COND_FALL_MASK = BIT(2), /* set if 1->0 */
 };
 
 void cond_init(cond_t *c, int val)
@@ -591,7 +232,6 @@ int cond_is(cond_t *c, int val)
 		return !(*c & COND_CURR_MASK);
 }
 
-
 void cond_set(cond_t *c, int val)
 {
 	if (val && cond_is(c, 0))
@@ -604,7 +244,6 @@ void cond_set(cond_t *c, int val)
 		*c &= ~COND_CURR_MASK;
 }
 
-
 int cond_went(cond_t *c, int val)
 {
 	int ret;
@@ -630,8 +269,8 @@ int cond_went(cond_t *c, int val)
  * *offset<0.  If argc<shift+1, leaves size unchanged, returning error if
  * *size<0.
  */
-int parse_offset_size(int argc, char **argv, int shift,
-			     int *offset, int *size)
+int parse_offset_size(int argc, const char **argv, int shift, int *offset,
+		      int *size)
 {
 	char *e;
 	int i;
@@ -691,3 +330,80 @@ void wait_for_ready(volatile uint32_t *reg, uint32_t enable, uint32_t ready)
 	while (!(*reg & ready))
 		;
 }
+
+int binary_first_base3_from_bits(int *bits, int nbits)
+{
+	int binary_below = 0;
+	int has_z = 0;
+	int base3 = 0;
+	int i;
+
+	/* Loop through every ternary digit, from MSB to LSB. */
+	for (i = nbits - 1; i >= 0; i--) {
+		/*
+		 * We keep track of the normal ternary result and whether
+		 * we found any bit that was a Z. We also determine the
+		 * amount of numbers that can be represented with only binary
+		 * digits (no Z) whose value in the normal ternary system
+		 * is lower than the one we are parsing. Counting from the left,
+		 * we add 2^i for any '1' digit to account for the binary
+		 * numbers whose values would be below it if all following
+		 * digits we parsed would be '0'. As soon as we find a '2' digit
+		 * we can total the remaining binary numbers below as 2^(i+1)
+		 * because we know that all binary representations counting only
+		 * this and following digits must have values below our number
+		 * (since 1xxx is always smaller than 2xxx).
+		 *
+		 * Example: 1 0 2 1 (counting from the left / most significant)
+		 * '1' at 3^3: Add 2^3 = 8 to account for binaries 0000-0111
+		 * '0' at 3^2: Ignore (not all binaries 1000-1100 are below us)
+		 * '2' at 3^1: Add 2^(1+1) = 4 to account for binaries 1000-1011
+		 * Stop adding for lower digits (3^0), all already accounted
+		 * now. We know that there can be no binary numbers 1020-102X.
+		 */
+		base3 = (base3 * 3) + bits[i];
+
+		if (!has_z) {
+			switch (bits[i]) {
+			case 0: /* Ignore '0' digits. */
+				break;
+			case 1: /* Account for binaries 0 to 2^i - 1. */
+				binary_below += 1 << i;
+				break;
+			case 2: /* Account for binaries 0 to 2^(i+1) - 1. */
+				binary_below += 1 << (i + 1);
+				has_z = 1;
+			}
+		}
+	}
+
+	if (has_z)
+		return base3 + (1 << nbits) - binary_below;
+
+	/* binary_below is normal binary system value if !has_z. */
+	return binary_below;
+}
+
+int binary_from_bits(int *bits, int nbits)
+{
+	int value = 0;
+	int i;
+
+	/* Loop through every binary digit, from MSB to LSB. */
+	for (i = nbits - 1; i >= 0; i--)
+		value = (value << 1) | bits[i];
+
+	return value;
+}
+
+int ternary_from_bits(int *bits, int nbits)
+{
+	int value = 0;
+	int i;
+
+	/* Loop through every ternary digit, from MSB to LSB. */
+	for (i = nbits - 1; i >= 0; i--)
+		value = (value * 3) + bits[i];
+
+	return value;
+}
diff --git a/common/vboot/common.c b/common/vboot/common.c
index 39f8c193c7..a92652364b 100644
--- a/common/vboot/common.c
+++ b/common/vboot/common.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,8 +10,8 @@
 #include "shared_mem.h"
 #include "vboot.h"
 
-#define CPRINTS(format, args...) cprints(CC_VBOOT, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_VBOOT, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_VBOOT, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_VBOOT, format, ##args)
 
 int vboot_is_padding_valid(const uint8_t *data, uint32_t start, uint32_t end)
 {
@@ -32,8 +32,8 @@ int vboot_is_padding_valid(const uint8_t *data, uint32_t start, uint32_t end)
 	return EC_SUCCESS;
 }
 
-int vboot_verify(const uint8_t *data, int len,
-		 const struct rsa_public_key *key, const uint8_t *sig)
+int vboot_verify(const uint8_t *data, int len, const struct rsa_public_key *key,
+		 const uint8_t *sig)
 {
 	struct sha256_ctx ctx;
 	uint8_t *hash;
diff --git a/common/vboot/efs2.c b/common/vboot/efs2.c
index e608fd5841..3346a2c76b 100644
--- a/common/vboot/efs2.c
+++ b/common/vboot/efs2.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,28 +16,33 @@
 #include "console.h"
 #include "crc8.h"
 #include "flash.h"
+#include "gpio.h"
 #include "hooks.h"
 #include "sha256.h"
 #include "system.h"
 #include "task.h"
-#include "usb_pd.h"
 #include "uart.h"
+#include "usb_pd.h"
 #include "vboot.h"
 #include "vboot_hash.h"
 
-#define CPRINTS(format, args...) cprints(CC_VBOOT,"VB " format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_VBOOT,"VB " format, ## args)
+#define CPRINTS(format, args...) cprints(CC_VBOOT, "VB " format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_VBOOT, "VB " format, ##args)
 
+/* LCOV_EXCL_START - TODO(b/172210316) implement is_battery_ready(), and remove
+ * this lcov excl.
+ */
 static const char *boot_mode_to_string(uint8_t mode)
 {
 	static const char *boot_mode_str[] = {
-		[BOOT_MODE_NORMAL] =		"NORMAL",
-		[BOOT_MODE_NO_BOOT] =		"NO_BOOT",
+		[BOOT_MODE_NORMAL] = "NORMAL",
+		[BOOT_MODE_NO_BOOT] = "NO_BOOT",
 	};
 	if (mode < ARRAY_SIZE(boot_mode_str))
 		return boot_mode_str[mode];
 	return "UNDEF";
 }
+/* LCOV_EXCL_STOP */
 
 /*
  * Check whether the session has successfully ended or not. ERR_TIMEOUT is
@@ -45,11 +50,11 @@ static const char *boot_mode_to_string(uint8_t mode)
  */
 static bool is_valid_cr50_response(enum cr50_comm_err code)
 {
-	return code != CR50_COMM_ERR_TIMEOUT
-			&& (code >> 8) == CR50_COMM_ERR_PREFIX;
+	return code != CR50_COMM_ERR_TIMEOUT &&
+	       (code >> 8) == CR50_COMM_ERR_PREFIX;
 }
 
-static void enable_packet_mode(bool enable)
+__overridable void board_enable_packet_mode(bool enable)
 {
 	/*
 	 * This can be done by set_flags(INPUT|PULL_UP). We don't need it now
@@ -62,14 +67,26 @@ static enum cr50_comm_err send_to_cr50(const uint8_t *data, size_t size)
 {
 	timestamp_t until;
 	int i, timeout = 0;
+	uint32_t lock_key;
 	struct cr50_comm_response res = {};
 
 	/* This will wake up (if it's sleeping) and interrupt Cr50. */
-	enable_packet_mode(true);
+	board_enable_packet_mode(true);
 
 	uart_flush_output();
 	uart_clear_input();
 
+	if (uart_shell_stop()) {
+		/* Failed to stop the shell. */
+		/* LCOV_EXCL_START - At least on posix systems, uart_shell_stop
+		 * will never fail, it will crash the binary or hang forever on
+		 * error.
+		 */
+		board_enable_packet_mode(false);
+		return CR50_COMM_ERR_UNKNOWN;
+		/* LCOV_EXCL_STOP */
+	}
+
 	/*
 	 * Send packet. No traffic control, assuming Cr50 consumes stream much
 	 * faster. TX buffer shouldn't overflow because it's cleared above and
@@ -78,24 +95,29 @@ static enum cr50_comm_err send_to_cr50(const uint8_t *data, size_t size)
 	 * Disable interrupts so that the data frame will be stored in the Tx
 	 * buffer in one piece.
 	 */
-	interrupt_disable();
+	lock_key = irq_lock();
 	uart_put_raw(data, size);
-	interrupt_enable();
+	irq_unlock(lock_key);
 
 	uart_flush_output();
 
 	until.val = get_time().val + CR50_COMM_TIMEOUT;
 
-	/* Make sure console task won't steal the response (in case in the
-	 * future we should exchange packets after tasks start). */
-	task_disable_task(TASK_ID_CONSOLE);
+	/*
+	 * Make sure console task won't steal the response in case we exchange
+	 * packets after tasks start.
+	 */
+#ifndef CONFIG_ZEPHYR
+	if (task_start_called())
+		task_disable_task(TASK_ID_CONSOLE);
+#endif /* !CONFIG_ZEPHYR */
 
 	/* Wait for response from Cr50 */
 	for (i = 0; i < sizeof(res); i++) {
 		while (!timeout) {
 			int c = uart_getc();
 			if (c != -1) {
-				res.error = res.error | c << (i*8);
+				res.error = res.error | c << (i * 8);
 				break;
 			}
 			msleep(1);
@@ -103,18 +125,22 @@ static enum cr50_comm_err send_to_cr50(const uint8_t *data, size_t size)
 		}
 	}
 
-	task_enable_task(TASK_ID_CONSOLE);
+	uart_shell_start();
+#ifndef CONFIG_ZEPHYR
+	if (task_start_called())
+		task_enable_task(TASK_ID_CONSOLE);
+#endif /* CONFIG_ZEPHYR */
 
 	/* Exit packet mode */
-	enable_packet_mode(false);
+	board_enable_packet_mode(false);
+
+	CPRINTS("Received 0x%04x", res.error);
 
 	if (timeout) {
 		CPRINTS("Timeout");
 		return CR50_COMM_ERR_TIMEOUT;
 	}
 
-	CPRINTS("Received 0x%04x", res.error);
-
 	return res.error;
 }
 
@@ -141,8 +167,8 @@ static enum cr50_comm_err cmd_to_cr50(enum cr50_comm_cmd cmd,
 	p->type = cmd;
 	p->size = size;
 	memcpy(p->data, data, size);
-	p->crc = crc8((uint8_t *)&p->type,
-		      sizeof(p->type) + sizeof(p->size) + size);
+	p->crc = cros_crc8((uint8_t *)&p->type,
+			   sizeof(p->type) + sizeof(p->size) + size);
 
 	do {
 		rv = send_to_cr50((uint8_t *)&s,
@@ -161,10 +187,10 @@ static enum cr50_comm_err verify_hash(void)
 	int rv;
 
 	/* Wake up Cr50 beforehand in case it's asleep. */
-	enable_packet_mode(true);
+	board_enable_packet_mode(true);
 	CPRINTS("Ping Cr50");
 	msleep(1);
-	enable_packet_mode(false);
+	board_enable_packet_mode(false);
 
 	rv = vboot_get_rw_hash(&hash);
 	if (rv)
@@ -174,17 +200,21 @@ static enum cr50_comm_err verify_hash(void)
 	return cmd_to_cr50(CR50_COMM_CMD_VERIFY_HASH, hash, SHA256_DIGEST_SIZE);
 }
 
+/* LCOV_EXCL_START - TODO(b/172210316) implement is_battery_ready(), and remove
+ * this lcov excl.
+ */
 static enum cr50_comm_err set_boot_mode(uint8_t mode)
 {
 	enum cr50_comm_err rv;
 
 	CPRINTS("Setting boot mode to %s(%d)", boot_mode_to_string(mode), mode);
-	rv = cmd_to_cr50(CR50_COMM_CMD_SET_BOOT_MODE,
-			 &mode, sizeof(enum boot_mode));
+	rv = cmd_to_cr50(CR50_COMM_CMD_SET_BOOT_MODE, &mode,
+			 sizeof(enum boot_mode));
 	if (rv != CR50_COMM_SUCCESS)
 		CPRINTS("Failed to set boot mode");
 	return rv;
 }
+/* LCOV_EXCL_STOP */
 
 static bool pd_comm_enabled;
 
@@ -199,10 +229,19 @@ bool vboot_allow_usb_pd(void)
 	return pd_comm_enabled;
 }
 
+#ifdef TEST_BUILD
+void vboot_disable_pd(void)
+{
+	pd_comm_enabled = false;
+}
+#endif
+
+/* LCOV_EXCL_START - This is just a stub intended to be overridden */
 __overridable void show_critical_error(void)
 {
 	CPRINTS("%s", __func__);
 }
+/* LCOV_EXCL_STOP */
 
 static void verify_and_jump(void)
 {
@@ -227,14 +266,16 @@ static void verify_and_jump(void)
 	}
 }
 
+/* LCOV_EXCL_START - This is just a stub intended to be overridden */
 __overridable void show_power_shortage(void)
 {
 	CPRINTS("%s", __func__);
 }
+/* LCOV_EXCL_STOP */
 
 static bool is_battery_ready(void)
 {
-	/* TODO: Add battery check (https://crbug.com/1045216) */
+	/* TODO(b/172210316): Add battery check */
 	return true;
 }
 
@@ -257,8 +298,8 @@ void vboot_main(void)
 	    (system_get_reset_flags() & EC_RESET_FLAG_STAY_IN_RO)) {
 		if (system_is_manual_recovery())
 			CPRINTS("In recovery mode");
-		if (!IS_ENABLED(CONFIG_BATTERY)
-				&& !IS_ENABLED(HAS_TASK_KEYSCAN)) {
+		if (!IS_ENABLED(CONFIG_BATTERY) &&
+		    !IS_ENABLED(HAS_TASK_KEYSCAN)) {
 			/*
 			 * For Chromeboxes, we relax security by allowing PD in
 			 * RO. Attackers don't gain meaningful advantage on
@@ -276,12 +317,16 @@ void vboot_main(void)
 		 * If battery is drained or bad, we will boot in NO_BOOT mode to
 		 * inform the user of the problem.
 		 */
+		/* LCOV_EXCL_START - TODO(b/172210316) implement
+		 * is_battery_ready(), and remove this lcov excl.
+		 */
 		if (!is_battery_ready()) {
 			CPRINTS("Battery not ready or bad");
 			if (set_boot_mode(BOOT_MODE_NO_BOOT) ==
-					CR50_COMM_SUCCESS)
+			    CR50_COMM_SUCCESS)
 				enable_pd();
 		}
+		/* LCOV_EXCL_STOP */
 
 		/* We'll enter recovery mode immediately, later, or never. */
 		return;
diff --git a/common/vboot/vb21_lib.c b/common/vboot/vb21_lib.c
index 4e215c14e5..3a380c24eb 100644
--- a/common/vboot/vb21_lib.c
+++ b/common/vboot/vb21_lib.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -47,12 +47,11 @@ int vb21_is_signature_valid(const struct vb21_signature *sig,
 
 const struct vb21_packed_key *vb21_get_packed_key(void)
 {
-	return (const struct vb21_packed_key *)(CONFIG_RO_PUBKEY_ADDR);
+	return (const struct vb21_packed_key *)(CONFIG_RO_PUBKEY_READ_ADDR);
 }
 
 static void read_rwsig_info(struct ec_response_rwsig_info *r)
 {
-
 	const struct vb21_packed_key *vb21_key;
 	int rv;
 
@@ -61,17 +60,21 @@ static void read_rwsig_info(struct ec_response_rwsig_info *r)
 	r->sig_alg = vb21_key->sig_alg;
 	r->hash_alg = vb21_key->hash_alg;
 	r->key_version = vb21_key->key_version;
-	{ BUILD_ASSERT(sizeof(r->key_id) == sizeof(vb21_key->id),
-		       "key ID sizes must match"); }
-	{ BUILD_ASSERT(sizeof(vb21_key->id) == sizeof(vb21_key->id.raw),
-		       "key ID sizes must match"); }
+	{
+		BUILD_ASSERT(sizeof(r->key_id) == sizeof(vb21_key->id),
+			     "key ID sizes must match");
+	}
+	{
+		BUILD_ASSERT(sizeof(vb21_key->id) == sizeof(vb21_key->id.raw),
+			     "key ID sizes must match");
+	}
 	memcpy(r->key_id, vb21_key->id.raw, sizeof(r->key_id));
 
 	rv = vb21_is_packed_key_valid(vb21_key);
 	r->key_is_valid = (rv == EC_SUCCESS);
 }
 
-static int command_rwsig_info(int argc, char **argv)
+static int command_rwsig_info(int argc, const char **argv)
 {
 	int i;
 	struct ec_response_rwsig_info r;
diff --git a/common/vboot/vboot.c b/common/vboot/vboot.c
index 1cf9cf7d80..162b396ba5 100644
--- a/common/vboot/vboot.c
+++ b/common/vboot/vboot.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,16 +17,16 @@
 #include "host_command.h"
 #include "rsa.h"
 #include "rwsig.h"
-#include "stdbool.h"
 #include "sha256.h"
 #include "shared_mem.h"
+#include "stdbool.h"
 #include "system.h"
 #include "usb_pd.h"
-#include "vboot.h"
 #include "vb21_struct.h"
+#include "vboot.h"
 
-#define CPRINTS(format, args...) cprints(CC_VBOOT,"VB " format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_VBOOT,"VB " format, ## args)
+#define CPRINTS(format, args...) cprints(CC_VBOOT, "VB " format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_VBOOT, "VB " format, ##args)
 
 static int has_matrix_keyboard(void)
 {
@@ -45,34 +45,34 @@ static int verify_slot(enum ec_image slot)
 
 	CPRINTS("Verifying %s", ec_image_to_string(slot));
 
-	vb21_key = (const struct vb21_packed_key *)(
-			CONFIG_MAPPED_STORAGE_BASE +
-			CONFIG_EC_PROTECTED_STORAGE_OFF +
-			CONFIG_RO_PUBKEY_STORAGE_OFF);
+	vb21_key =
+		(const struct vb21_packed_key *)(CONFIG_MAPPED_STORAGE_BASE +
+						 CONFIG_EC_PROTECTED_STORAGE_OFF +
+						 CONFIG_RO_PUBKEY_STORAGE_OFF);
 	rv = vb21_is_packed_key_valid(vb21_key);
 	if (rv) {
 		CPRINTS("Invalid key (%d)", rv);
 		return EC_ERROR_VBOOT_KEY;
 	}
-	key = (const struct rsa_public_key *)
-		((const uint8_t *)vb21_key + vb21_key->key_offset);
+	key = (const struct rsa_public_key *)((const uint8_t *)vb21_key +
+					      vb21_key->key_offset);
 
 	if (slot == EC_IMAGE_RW_A) {
 		data = (const uint8_t *)(CONFIG_MAPPED_STORAGE_BASE +
-				CONFIG_EC_WRITABLE_STORAGE_OFF +
-				CONFIG_RW_A_STORAGE_OFF);
-		vb21_sig = (const struct vb21_signature *)(
-				CONFIG_MAPPED_STORAGE_BASE +
-				CONFIG_EC_WRITABLE_STORAGE_OFF +
-				CONFIG_RW_A_SIGN_STORAGE_OFF);
+					 CONFIG_EC_WRITABLE_STORAGE_OFF +
+					 CONFIG_RW_A_STORAGE_OFF);
+		vb21_sig = (const struct vb21_signature
+				    *)(CONFIG_MAPPED_STORAGE_BASE +
+				       CONFIG_EC_WRITABLE_STORAGE_OFF +
+				       CONFIG_RW_A_SIGN_STORAGE_OFF);
 	} else {
 		data = (const uint8_t *)(CONFIG_MAPPED_STORAGE_BASE +
-				CONFIG_EC_WRITABLE_STORAGE_OFF +
-				CONFIG_RW_B_STORAGE_OFF);
-		vb21_sig = (const struct vb21_signature *)(
-				CONFIG_MAPPED_STORAGE_BASE +
-				CONFIG_EC_WRITABLE_STORAGE_OFF +
-				CONFIG_RW_B_SIGN_STORAGE_OFF);
+					 CONFIG_EC_WRITABLE_STORAGE_OFF +
+					 CONFIG_RW_B_STORAGE_OFF);
+		vb21_sig = (const struct vb21_signature
+				    *)(CONFIG_MAPPED_STORAGE_BASE +
+				       CONFIG_EC_WRITABLE_STORAGE_OFF +
+				       CONFIG_RW_B_SIGN_STORAGE_OFF);
 	}
 
 	rv = vb21_is_signature_valid(vb21_sig, vb21_key);
@@ -187,7 +187,7 @@ void vboot_main(void)
 		return;
 	}
 
-	if (!(flash_get_protect() & EC_FLASH_PROTECT_GPIO_ASSERTED)) {
+	if (!(crec_flash_get_protect() & EC_FLASH_PROTECT_GPIO_ASSERTED)) {
 		/*
 		 * If hardware WP is disabled, PD communication is enabled.
 		 * We can return and wait for more power.
diff --git a/common/vboot_hash.c b/common/vboot_hash.c
index a08c707630..944092a12d 100644
--- a/common/vboot_hash.c
+++ b/common/vboot_hash.c
@@ -1,19 +1,22 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Verified boot hash computing module for Chrome EC */
 
+#include "builtin/assert.h"
 #include "clock.h"
 #include "common.h"
 #include "console.h"
 #include "flash.h"
 #include "hooks.h"
 #include "host_command.h"
+#include "printf.h"
 #include "sha256.h"
 #include "shared_mem.h"
 #include "stdbool.h"
+#include "stdint.h"
 #include "system.h"
 #include "task.h"
 #include "timer.h"
@@ -22,7 +25,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_VBOOT, outstr)
-#define CPRINTS(format, args...) cprints(CC_VBOOT, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_VBOOT, format, ##args)
 
 struct vboot_hash_tag {
 	uint8_t hash[SHA256_DIGEST_SIZE];
@@ -30,11 +33,8 @@ struct vboot_hash_tag {
 	uint32_t size;
 };
 
-#define VBOOT_HASH_SYSJUMP_TAG 0x5648 /* "VH" */
-#define VBOOT_HASH_SYSJUMP_VERSION 1
-
-#define CHUNK_SIZE 1024       /* Bytes to hash per deferred call */
-#define WORK_INTERVAL_US 100  /* Delay between deferred calls */
+#define CHUNK_SIZE 1024 /* Bytes to hash per deferred call */
+#define WORK_INTERVAL_US 100 /* Delay between deferred calls */
 
 /* Check that CHUNK_SIZE fits in shared memory. */
 SHARED_MEM_CHECK_SIZE(CHUNK_SIZE);
@@ -42,13 +42,17 @@ SHARED_MEM_CHECK_SIZE(CHUNK_SIZE);
 static uint32_t data_offset;
 static uint32_t data_size;
 static uint32_t curr_pos;
-static const uint8_t *hash;   /* Hash, or NULL if not valid */
+static const uint8_t *hash; /* Hash, or NULL if not valid */
 static int want_abort;
 static int in_progress;
-#define VBOOT_HASH_DEFERRED	true
-#define VBOOT_HASH_BLOCKING	false
+#define VBOOT_HASH_DEFERRED true
+#define VBOOT_HASH_BLOCKING false
 
-static struct sha256_ctx ctx;
+static
+#ifdef CONFIG_SOC_IT8XXX2_SHA256_HW_ACCELERATE
+	__attribute__((section(".__sha256_ram_block")))
+#endif
+	struct sha256_ctx ctx;
 
 int vboot_hash_in_progress(void)
 {
@@ -67,6 +71,9 @@ void vboot_hash_abort(void)
 		want_abort = 0;
 		data_size = 0;
 		hash = NULL;
+#ifdef CONFIG_SHA256_HW_ACCELERATE
+		SHA256_abort(&ctx);
+#endif
 	}
 }
 
@@ -94,7 +101,7 @@ static int read_and_hash_chunk(int offset, int size)
 		return rv;
 	}
 
-	rv = flash_read(offset, size, buf);
+	rv = crec_flash_read(offset, size, buf);
 	if (rv == EC_SUCCESS)
 		SHA256_update(&ctx, (const uint8_t *)buf, size);
 	else
@@ -115,10 +122,12 @@ static int read_and_hash_chunk(int offset, int size)
 static void hash_next_chunk(size_t size)
 {
 #ifdef CONFIG_MAPPED_STORAGE
-	flash_lock_mapped_storage(1);
-	SHA256_update(&ctx, (const uint8_t *)(CONFIG_MAPPED_STORAGE_BASE +
-					      data_offset + curr_pos), size);
-	flash_lock_mapped_storage(0);
+	crec_flash_lock_mapped_storage(1);
+	SHA256_update(&ctx,
+		      (const uint8_t *)((uintptr_t)CONFIG_MAPPED_STORAGE_BASE +
+					data_offset + curr_pos),
+		      size);
+	crec_flash_lock_mapped_storage(0);
 #else
 	if (read_and_hash_chunk(data_offset + curr_pos, size) != EC_SUCCESS)
 		return;
@@ -127,6 +136,8 @@ static void hash_next_chunk(size_t size)
 
 static void vboot_hash_all_chunks(void)
 {
+	char str_buf[hex_str_buf_size(SHA256_PRINT_SIZE)];
+
 	do {
 		size_t size = MIN(CHUNK_SIZE, data_size - curr_pos);
 		hash_next_chunk(size);
@@ -134,7 +145,9 @@ static void vboot_hash_all_chunks(void)
 	} while (curr_pos < data_size);
 
 	hash = SHA256_final(&ctx);
-	CPRINTS("hash done %ph", HEX_BUF(hash, SHA256_PRINT_SIZE));
+	snprintf_hex_buffer(str_buf, sizeof(str_buf),
+			    HEX_BUF(hash, SHA256_PRINT_SIZE));
+	CPRINTS("hash done %s", str_buf);
 	in_progress = 0;
 	clock_enable_module(MODULE_FAST_CPU, 0);
 
@@ -162,9 +175,14 @@ static void vboot_hash_next_chunk(void)
 
 	curr_pos += size;
 	if (curr_pos >= data_size) {
+		char str_buf[hex_str_buf_size(SHA256_PRINT_SIZE)];
+
 		/* Store the final hash */
 		hash = SHA256_final(&ctx);
-		CPRINTS("hash done %ph", HEX_BUF(hash, SHA256_PRINT_SIZE));
+
+		snprintf_hex_buffer(str_buf, sizeof(str_buf),
+				    HEX_BUF(hash, SHA256_PRINT_SIZE));
+		CPRINTS("hash done %s", str_buf);
 
 		in_progress = 0;
 
@@ -208,8 +226,9 @@ static int vboot_hash_start(uint32_t offset, uint32_t size,
 	 * Make sure request fits inside flash.  That is, you can't use this
 	 * command to peek at other memory.
 	 */
-	if (offset > CONFIG_FLASH_SIZE || size > CONFIG_FLASH_SIZE ||
-	    offset + size > CONFIG_FLASH_SIZE || nonce_size < 0) {
+	if (offset > CONFIG_FLASH_SIZE_BYTES ||
+	    size > CONFIG_FLASH_SIZE_BYTES ||
+	    offset + size > CONFIG_FLASH_SIZE_BYTES || nonce_size < 0) {
 		return EC_ERROR_INVAL;
 	}
 
@@ -268,9 +287,9 @@ int vboot_hash_invalidate(int offset, int size)
  */
 static uint32_t get_rw_size(void)
 {
-#ifdef CONFIG_VBOOT_EFS		/* Only needed for EFS, which signs and verifies
-				 * entire RW, thus not needed for EFS2, which
-				 * verifies only the used image size. */
+#ifdef CONFIG_VBOOT_EFS /* Only needed for EFS, which signs and verifies \
+			 * entire RW, thus not needed for EFS2, which    \
+			 * verifies only the used image size. */
 	return CONFIG_RW_SIZE;
 #else
 	return system_get_image_used(EC_IMAGE_RW);
@@ -279,21 +298,6 @@ static uint32_t get_rw_size(void)
 
 static void vboot_hash_init(void)
 {
-#ifdef CONFIG_SAVE_VBOOT_HASH
-	const struct vboot_hash_tag *tag;
-	int version, size;
-
-	tag = (const struct vboot_hash_tag *)system_get_jump_tag(
-		VBOOT_HASH_SYSJUMP_TAG, &version, &size);
-	if (tag && version == VBOOT_HASH_SYSJUMP_VERSION &&
-	    size == sizeof(*tag)) {
-		/* Already computed a hash, so don't recompute */
-		CPRINTS("hash precomputed");
-		hash = tag->hash;
-		data_offset = tag->offset;
-		data_size = tag->size;
-	} else
-#endif
 #ifdef CONFIG_HOSTCMD_EVENTS
 	/*
 	 * Don't auto-start hash computation if we've asked the host to enter
@@ -306,9 +310,18 @@ static void vboot_hash_init(void)
 	      EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)))
 #endif
 	{
-		/* Start computing the hash of RW firmware */
-		vboot_hash_start(flash_get_rw_offset(system_get_active_copy()),
-				 get_rw_size(), NULL, 0, VBOOT_HASH_DEFERRED);
+		/*
+		 * At this point, it's likely that EFS2 vboot_main() already
+		 * requested the RW hash calculation once.
+		 *
+		 * Start computing the hash of RW firmware only if we haven't
+		 * done it before.
+		 */
+		if (!hash) {
+			vboot_hash_start(
+				flash_get_rw_offset(system_get_active_copy()),
+				get_rw_size(), NULL, 0, VBOOT_HASH_DEFERRED);
+		}
 	}
 }
 DECLARE_HOOK(HOOK_INIT, vboot_hash_init, HOOK_PRIO_INIT_VBOOT_HASH);
@@ -321,27 +334,15 @@ int vboot_get_rw_hash(const uint8_t **dst)
 	return rv;
 }
 
-#ifdef CONFIG_SAVE_VBOOT_HASH
-
-static int vboot_hash_preserve_state(void)
+int vboot_get_ro_hash(const uint8_t **dst)
 {
-	struct vboot_hash_tag tag;
-
-	/* If we haven't finished our hash, nothing to save */
-	if (!hash)
-		return EC_SUCCESS;
-
-	memcpy(tag.hash, hash, sizeof(tag.hash));
-	tag.offset = data_offset;
-	tag.size = data_size;
-	system_add_jump_tag(VBOOT_HASH_SYSJUMP_TAG,
-			    VBOOT_HASH_SYSJUMP_VERSION,
-			    sizeof(tag), &tag);
-	return EC_SUCCESS;
+	int rv = vboot_hash_start(CONFIG_EC_PROTECTED_STORAGE_OFF +
+					  CONFIG_RO_STORAGE_OFF,
+				  system_get_image_used(EC_IMAGE_RO), NULL, 0,
+				  VBOOT_HASH_BLOCKING);
+	*dst = hash;
+	return rv;
 }
-DECLARE_HOOK(HOOK_SYSJUMP, vboot_hash_preserve_state, HOOK_PRIO_DEFAULT);
-
-#endif
 
 /**
  * Returns the offset of RO or RW image if the either region is specifically
@@ -361,10 +362,10 @@ static int get_offset(int offset)
 /****************************************************************************/
 /* Console commands */
 #ifdef CONFIG_CMD_HASH
-static int command_hash(int argc, char **argv)
+static int command_hash(int argc, const char **argv)
 {
-	uint32_t offset = CONFIG_EC_WRITABLE_STORAGE_OFF +
-			  CONFIG_RW_STORAGE_OFF;
+	uint32_t offset =
+		CONFIG_EC_WRITABLE_STORAGE_OFF + CONFIG_RW_STORAGE_OFF;
 	uint32_t size = CONFIG_RW_SIZE;
 	char *e;
 
@@ -376,9 +377,13 @@ static int command_hash(int argc, char **argv)
 			ccprintf("(aborting)\n");
 		else if (in_progress)
 			ccprintf("(in progress)\n");
-		else if (hash)
-			ccprintf("%ph\n", HEX_BUF(hash, SHA256_DIGEST_SIZE));
-		else
+		else if (hash) {
+			char str_buf[hex_str_buf_size(SHA256_DIGEST_SIZE)];
+
+			snprintf_hex_buffer(str_buf, sizeof(str_buf),
+					    HEX_BUF(hash, SHA256_DIGEST_SIZE));
+			ccprintf("%s\n", str_buf);
+		} else
 			ccprintf("(invalid)\n");
 
 		return EC_SUCCESS;
@@ -390,15 +395,14 @@ static int command_hash(int argc, char **argv)
 			return EC_SUCCESS;
 		} else if (!strcasecmp(argv[1], "rw")) {
 			return vboot_hash_start(
-					get_offset(EC_VBOOT_HASH_OFFSET_ACTIVE),
-					get_rw_size(),
-					NULL, 0, VBOOT_HASH_DEFERRED);
+				get_offset(EC_VBOOT_HASH_OFFSET_ACTIVE),
+				get_rw_size(), NULL, 0, VBOOT_HASH_DEFERRED);
 		} else if (!strcasecmp(argv[1], "ro")) {
 			return vboot_hash_start(
 				CONFIG_EC_PROTECTED_STORAGE_OFF +
-				CONFIG_RO_STORAGE_OFF,
-				system_get_image_used(EC_IMAGE_RO),
-				NULL, 0, VBOOT_HASH_DEFERRED);
+					CONFIG_RO_STORAGE_OFF,
+				system_get_image_used(EC_IMAGE_RO), NULL, 0,
+				VBOOT_HASH_DEFERRED);
 		}
 		return EC_ERROR_PARAM2;
 	}
@@ -418,12 +422,11 @@ static int command_hash(int argc, char **argv)
 		if (*e)
 			return EC_ERROR_PARAM3;
 
-		return vboot_hash_start(offset, size,
-					(const uint8_t *)&nonce,
+		return vboot_hash_start(offset, size, (const uint8_t *)&nonce,
 					sizeof(nonce), VBOOT_HASH_DEFERRED);
 	} else
-		return vboot_hash_start(offset, size,
-					NULL, 0, VBOOT_HASH_DEFERRED);
+		return vboot_hash_start(offset, size, NULL, 0,
+					VBOOT_HASH_DEFERRED);
 }
 DECLARE_CONSOLE_COMMAND(hash, command_hash,
 			"[abort | ro | rw] | [<offset> <size> [<nonce>]]",
@@ -433,8 +436,7 @@ DECLARE_CONSOLE_COMMAND(hash, command_hash,
 /* Host commands */
 
 /* Fill in the response with the current hash status */
-static void fill_response(struct ec_response_vboot_hash *r,
-			  int request_offset)
+static void fill_response(struct ec_response_vboot_hash *r, int request_offset)
 {
 	if (in_progress)
 		r->status = EC_VBOOT_HASH_STATUS_BUSY;
@@ -473,7 +475,7 @@ static int host_start_hash(const struct ec_params_vboot_hash *p)
 	if (offset == EC_VBOOT_HASH_OFFSET_RO)
 		size = system_get_image_used(EC_IMAGE_RO);
 	else if ((offset == EC_VBOOT_HASH_OFFSET_ACTIVE) ||
-			(offset == EC_VBOOT_HASH_OFFSET_UPDATE))
+		 (offset == EC_VBOOT_HASH_OFFSET_UPDATE))
 		size = get_rw_size();
 	offset = get_offset(offset);
 	rv = vboot_hash_start(offset, size, p->nonce_data, p->nonce_size,
@@ -527,6 +529,5 @@ host_command_vboot_hash(struct host_cmd_handler_args *args)
 		return EC_RES_INVALID_PARAM;
 	}
 }
-DECLARE_HOST_COMMAND(EC_CMD_VBOOT_HASH,
-		     host_command_vboot_hash,
+DECLARE_HOST_COMMAND(EC_CMD_VBOOT_HASH, host_command_vboot_hash,
 		     EC_VER_MASK(0));
diff --git a/common/vec3.c b/common/vec3.c
index dadf7715ff..4cf26ebf4c 100644
--- a/common/vec3.c
+++ b/common/vec3.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,12 +6,11 @@
 #include "common.h"
 #include "math.h"
 #include "math_util.h"
-#include "vec3.h"
 #include "util.h"
+#include "vec3.h"
 
-static fpv3_t zero_initialized_vector = {
-	FLOAT_TO_FP(0.0f), FLOAT_TO_FP(0.0f), FLOAT_TO_FP(0.0f)
-};
+static fpv3_t zero_initialized_vector = { FLOAT_TO_FP(0.0f), FLOAT_TO_FP(0.0f),
+					  FLOAT_TO_FP(0.0f) };
 
 void fpv3_zero(fpv3_t v)
 {
diff --git a/common/version.c b/common/version.c
index 1888fc0aef..fe082abbe0 100644
--- a/common/version.c
+++ b/common/version.c
@@ -1,24 +1,24 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Embed firmware version number in the binary */
 
-#include <stdint.h>
 #include "common.h"
 #include "compile_time_macros.h"
+#include "cros_version.h"
 #include "ec_commands.h"
 #include "ec_version.h"
 #include "stddef.h"
 #include "system.h"
-#include "version.h"
+
+#include <stdint.h>
 
 BUILD_ASSERT(CONFIG_ROLLBACK_VERSION >= 0);
 BUILD_ASSERT(CONFIG_ROLLBACK_VERSION <= INT32_MAX);
 
-const struct image_data __keep current_image_data
-	__attribute__((section(".rodata.ver"))) = {
+const struct image_data __keep current_image_data FIXED_SECTION("ver") = {
 	.cookie1 = CROS_EC_IMAGE_DATA_COOKIE1,
 	.version = CROS_EC_VERSION32,
 #ifndef TEST_BUILD
@@ -26,12 +26,21 @@ const struct image_data __keep current_image_data
 #endif
 	.rollback_version = CONFIG_ROLLBACK_VERSION,
 	.cookie2 = CROS_EC_IMAGE_DATA_COOKIE2,
+	.cros_fwid = CROS_FWID32,
+	.cookie3 = CROS_EC_IMAGE_DATA_COOKIE3,
 };
 BUILD_ASSERT(sizeof(CROS_EC_VERSION32) <= 32);
+BUILD_ASSERT(sizeof(CROS_FWID32) <= 32);
 
+#ifdef CONFIG_CROS_FWID_VERSION
+const char build_info[] __keep __attribute__((section(".rodata.buildinfo"))) =
+	VERSION " " CROS_FWID32 " " DATE " " BUILDER;
+#else
 const char build_info[] __keep __attribute__((section(".rodata.buildinfo"))) =
 	VERSION " " DATE " " BUILDER;
+#endif
 
+/* LCOV_EXCL_START - this function doesn't work in GitLab */
 static int get_num_commits(const struct image_data *data)
 {
 	int numperiods = 0;
@@ -60,9 +69,10 @@ static int get_num_commits(const struct image_data *data)
 	}
 
 	return (i == sizeof(data->version) ? 0 : ret);
-
 }
+/* LCOV_EXCL_STOP */
 
+/* LCOV_EXCL_START - this function doesn't work in GitLab */
 int ver_get_num_commits(enum ec_image copy)
 {
 	const struct image_data *data;
@@ -72,3 +82,4 @@ int ver_get_num_commits(enum ec_image copy)
 		data = &current_image_data;
 	return data ? get_num_commits(data) : 0;
 }
+/* LCOV_EXCL_STOP */
diff --git a/common/virtual_battery.c b/common/virtual_battery.c
index ef33a4c67a..743f2a8801 100644
--- a/common/virtual_battery.c
+++ b/common/virtual_battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,7 +14,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
 
 #define BATT_MODE_UNINITIALIZED -1
 
@@ -25,8 +25,8 @@
 enum batt_cmd_parse_state {
 	IDLE = 0, /* initial state */
 	START = 1, /* received the register address (command code) */
-	WRITE_VB, /* writing data bytes to the slave */
-	READ_VB, /* reading data bytes to the slave */
+	WRITE_VB, /* writing data bytes to the peripheral */
+	READ_VB, /* reading data bytes to the peripheral */
 };
 
 static enum batt_cmd_parse_state sb_cmd_state;
@@ -34,12 +34,10 @@ static uint8_t cache_hit;
 static const uint8_t *batt_cmd_head;
 static int acc_write_len;
 
-int virtual_battery_handler(struct ec_response_i2c_passthru *resp,
-				   int in_len, int *err_code, int xferflags,
-				   int read_len, int write_len,
-				   const uint8_t *out)
+int virtual_battery_handler(struct ec_response_i2c_passthru *resp, int in_len,
+			    int *err_code, int xferflags, int read_len,
+			    int write_len, const uint8_t *out)
 {
-
 #if defined(CONFIG_BATTERY_PRESENT_GPIO) || \
 	defined(CONFIG_BATTERY_PRESENT_CUSTOM)
 	/*
@@ -74,7 +72,7 @@ int virtual_battery_handler(struct ec_response_i2c_passthru *resp,
 		} else {
 			sb_cmd_state = READ_VB;
 			*err_code = virtual_battery_operation(batt_cmd_head,
-						NULL, 0, 0);
+							      NULL, 0, 0);
 			/*
 			 * If the reg is not handled by virtual battery, we
 			 * do not support it.
@@ -105,9 +103,6 @@ int virtual_battery_handler(struct ec_response_i2c_passthru *resp,
 		if (cache_hit)
 			*err_code = 0;
 		break;
-	default:
-		reset_parse_state();
-		return EC_ERROR_INVAL;
 	}
 
 	acc_write_len += write_len;
@@ -118,10 +113,8 @@ int virtual_battery_handler(struct ec_response_i2c_passthru *resp,
 		/* write to virtual battery */
 		case START:
 		case WRITE_VB:
-			virtual_battery_operation(batt_cmd_head,
-						NULL,
-						0,
-						acc_write_len);
+			virtual_battery_operation(batt_cmd_head, NULL, 0,
+						  acc_write_len);
 			break;
 		/* read from virtual battery */
 		case READ_VB:
@@ -129,16 +122,19 @@ int virtual_battery_handler(struct ec_response_i2c_passthru *resp,
 				read_len += in_len;
 				memset(&resp->data[0], 0, read_len);
 				virtual_battery_operation(batt_cmd_head,
-							&resp->data[0],
-							read_len,
-							0);
+							  &resp->data[0],
+							  read_len, 0);
 			}
 			break;
+		/* LCOV_EXCL_START - Unreachable in IDLE state and remaining
+		 * states covered above.
+		 */
 		default:
 			reset_parse_state();
 			return EC_ERROR_INVAL;
-
 		}
+		/* LCOV_EXCL_STOP */
+
 		/* Reset the state in the end of messages */
 		reset_parse_state();
 	}
@@ -166,18 +162,29 @@ void copy_memmap_string(uint8_t *dest, int offset, int len)
 	memmap_str = host_get_memmap(offset);
 	/* memmap_str might not be NULL terminated */
 	memmap_strlen = *(memmap_str + EC_MEMMAP_TEXT_MAX - 1) == '\0' ?
-			strlen(memmap_str) : EC_MEMMAP_TEXT_MAX;
+				strlen(memmap_str) :
+				EC_MEMMAP_TEXT_MAX;
 	dest[0] = memmap_strlen;
 	memcpy(dest + 1, memmap_str, MIN(memmap_strlen, len - 1));
 }
 
-int virtual_battery_operation(const uint8_t *batt_cmd_head,
-			      uint8_t *dest,
-			      int read_len,
-			      int write_len)
+static void copy_battery_info_string(uint8_t *dst, const uint8_t *src, int len)
+{
+	if (len == 0)
+		return;
+
+	dst[0] = strlen(src);
+	strncpy(dst + 1, src, len - 1);
+}
+
+int virtual_battery_operation(const uint8_t *batt_cmd_head, uint8_t *dest,
+			      int read_len, int write_len)
 {
 	int val;
 	int year, month, day;
+#ifdef CONFIG_BATTERY_SMART
+	char str[32];
+#endif
 	/*
 	 * We cache battery operational mode locally for both read and write
 	 * commands. If MODE_CAPACITY bit is set, battery capacity will be
@@ -192,6 +199,14 @@ int virtual_battery_operation(const uint8_t *batt_cmd_head,
 	 * are two bytes.
 	 */
 	int bounded_read_len = MIN(read_len, 2);
+	const struct battery_static_info *bs;
+
+	if (IS_ENABLED(CONFIG_BATTERY_V2))
+		/*
+		 * TODO: To support multiple batteries, we need to translate
+		 * i2c address to a battery index.
+		 */
+		bs = &battery_static[BATT_IDX_MAIN];
 
 	curr_batt = charger_current_battery_params();
 	switch (*batt_cmd_head) {
@@ -213,9 +228,8 @@ int virtual_battery_operation(const uint8_t *batt_cmd_head,
 					 * typical SB defaults.
 					 */
 					batt_mode_cache =
-					   MODE_INTERNAL_CHARGE_CONTROLLER |
-					   MODE_ALARM |
-					   MODE_CHARGER;
+						MODE_INTERNAL_CHARGE_CONTROLLER |
+						MODE_ALARM | MODE_CHARGER;
 
 			memcpy(dest, &batt_mode_cache, bounded_read_len);
 		}
@@ -244,9 +258,21 @@ int virtual_battery_operation(const uint8_t *batt_cmd_head,
 			return EC_ERROR_BUSY;
 		memcpy(dest, &(curr_batt->current), bounded_read_len);
 		break;
+	case SB_AVERAGE_CURRENT:
+		/* This may cause an i2c transaction */
+		if (curr_batt->flags & BATT_FLAG_BAD_AVERAGE_CURRENT)
+			return EC_ERROR_BUSY;
+		val = battery_get_avg_current();
+		memcpy(dest, &val, bounded_read_len);
+		break;
+	case SB_MAX_ERROR:
+		/* report as 3% to make kernel happy */
+		val = BATTERY_LEVEL_SHUTDOWN;
+		memcpy(dest, &val, bounded_read_len);
+		break;
 	case SB_FULL_CHARGE_CAPACITY:
 		if (curr_batt->flags & BATT_FLAG_BAD_FULL_CAPACITY ||
-				curr_batt->flags & BATT_FLAG_BAD_VOLTAGE)
+		    curr_batt->flags & BATT_FLAG_BAD_VOLTAGE)
 			return EC_ERROR_BUSY;
 		val = curr_batt->full_capacity;
 		if (batt_mode_cache & MODE_CAPACITY)
@@ -276,7 +302,7 @@ int virtual_battery_operation(const uint8_t *batt_cmd_head,
 		break;
 	case SB_REMAINING_CAPACITY:
 		if (curr_batt->flags & BATT_FLAG_BAD_REMAINING_CAPACITY ||
-				curr_batt->flags & BATT_FLAG_BAD_VOLTAGE)
+		    curr_batt->flags & BATT_FLAG_BAD_VOLTAGE)
 			return EC_ERROR_BUSY;
 		val = curr_batt->remaining_capacity;
 		if (batt_mode_cache & MODE_CAPACITY)
@@ -284,10 +310,24 @@ int virtual_battery_operation(const uint8_t *batt_cmd_head,
 		memcpy(dest, &val, bounded_read_len);
 		break;
 	case SB_MANUFACTURER_NAME:
-		copy_memmap_string(dest, EC_MEMMAP_BATT_MFGR, read_len);
+		if (IS_ENABLED(CONFIG_BATTERY_V2))
+			copy_battery_info_string(dest, bs->manufacturer_ext,
+						 read_len);
+		else
+			copy_memmap_string(dest, EC_MEMMAP_BATT_MFGR, read_len);
 		break;
 	case SB_DEVICE_NAME:
-		copy_memmap_string(dest, EC_MEMMAP_BATT_MODEL, read_len);
+		if (IS_ENABLED(CONFIG_BATTERY_V2))
+			copy_battery_info_string(dest, bs->model_ext, read_len);
+		else
+			copy_memmap_string(dest, EC_MEMMAP_BATT_MODEL,
+					   read_len);
+		break;
+	case SB_DEVICE_CHEMISTRY:
+		if (IS_ENABLED(CONFIG_BATTERY_V2))
+			copy_battery_info_string(dest, bs->type_ext, read_len);
+		else
+			copy_memmap_string(dest, EC_MEMMAP_BATT_TYPE, read_len);
 		break;
 	case SB_AVERAGE_TIME_TO_FULL:
 		/* This may cause an i2c transaction */
@@ -301,6 +341,30 @@ int virtual_battery_operation(const uint8_t *batt_cmd_head,
 			return EC_ERROR_INVAL;
 		memcpy(dest, &val, bounded_read_len);
 		break;
+#ifdef CONFIG_BATTERY_SMART
+	/*
+	 * Only supports sb for now, respective gauges should implement their
+	 * function.
+	 */
+	case SB_RUN_TIME_TO_EMPTY:
+		/* This may cause an i2c transaction */
+		if (battery_run_time_to_empty(&val))
+			return EC_ERROR_INVAL;
+		memcpy(dest, &val, bounded_read_len);
+		break;
+#endif
+	case SB_CHARGING_CURRENT:
+		if (curr_batt->flags & BATT_FLAG_BAD_DESIRED_CURRENT)
+			return EC_ERROR_BUSY;
+		val = curr_batt->desired_current;
+		memcpy(dest, &val, bounded_read_len);
+		break;
+	case SB_CHARGING_VOLTAGE:
+		if (curr_batt->flags & BATT_FLAG_BAD_DESIRED_VOLTAGE)
+			return EC_ERROR_BUSY;
+		val = curr_batt->desired_voltage;
+		memcpy(dest, &val, bounded_read_len);
+		break;
 	case SB_MANUFACTURE_DATE:
 		/* This may cause an i2c transaction */
 		if (!battery_manufacture_date(&year, &month, &day)) {
@@ -315,13 +379,50 @@ int virtual_battery_operation(const uint8_t *batt_cmd_head,
 		}
 		memcpy(dest, &val, bounded_read_len);
 		break;
+#ifdef CONFIG_BATTERY_SMART
+	case SB_MANUFACTURER_DATA:
+		if (read_len > ARRAY_SIZE(str))
+			return EC_ERROR_INVAL;
+		/* This may cause an i2c transaction */
+		if (battery_manufacturer_data(str, ARRAY_SIZE(str)))
+			return EC_ERROR_INVAL;
+		memcpy(dest, &str, read_len);
+		break;
+
+	case SB_MANUFACTURE_INFO:
+		if (sb_read_string(*batt_cmd_head, str, sizeof(str)))
+			return EC_ERROR_INVAL;
+		memcpy(dest, &str, MIN(read_len, sizeof(str)));
+		break;
+#endif
 	case SB_MANUFACTURER_ACCESS:
-		/* No manuf. access reg access allowed over VB interface */
+#ifdef CONFIG_BATTERY_SMART
+		if ((write_len >= 2) && (write_len <= 3)) {
+			val = batt_cmd_head[1] | batt_cmd_head[2] << 8;
+			/* This may cause an i2c transaction */
+			if (!battery_manufacturer_access(val))
+				return EC_SUCCESS;
+		}
+#endif
 		return EC_ERROR_INVAL;
+	case SB_SPECIFICATION_INFO:
+		/* v1.1 without PEC, no scale factor to voltage and current */
+		val = 0x0011;
+		memcpy(dest, &val, bounded_read_len);
+		break;
+#ifdef CONFIG_SMART_BATTERY_OPTIONAL_MFG_FUNC
+	case SB_OPTIONAL_MFG_FUNC1:
+	case SB_OPTIONAL_MFG_FUNC2:
+	case SB_OPTIONAL_MFG_FUNC3:
+	case SB_OPTIONAL_MFG_FUNC4:
+		if (sb_read(*batt_cmd_head, &val))
+			return EC_ERROR_INVAL;
+		memcpy(dest, &val, bounded_read_len);
+		break;
+#endif
 	default:
 		CPRINTS("Unhandled VB reg %x", *batt_cmd_head);
 		return EC_ERROR_INVAL;
 	}
 	return EC_SUCCESS;
 }
-
diff --git a/common/vstore.c b/common/vstore.c
index 9b4636397c..254a515b48 100644
--- a/common/vstore.c
+++ b/common/vstore.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,7 +22,7 @@
 #include "system.h"
 #include "util.h"
 
-#define VSTORE_SYSJUMP_TAG  0x5653 /* "VS" */
+#define VSTORE_SYSJUMP_TAG 0x5653 /* "VS" */
 #define VSTORE_HOOK_VERSION 1
 
 struct vstore_slot {
@@ -32,7 +32,7 @@ struct vstore_slot {
 
 static struct vstore_slot vstore_slots[CONFIG_VSTORE_SLOT_COUNT];
 static const int vstore_size =
-		sizeof(struct vstore_slot) * CONFIG_VSTORE_SLOT_COUNT;
+	sizeof(struct vstore_slot) * CONFIG_VSTORE_SLOT_COUNT;
 BUILD_ASSERT(ARRAY_SIZE(vstore_slots) <= EC_VSTORE_SLOT_MAX);
 
 /*
@@ -97,7 +97,7 @@ static enum ec_status vstore_write(struct host_cmd_handler_args *args)
 }
 DECLARE_HOST_COMMAND(EC_CMD_VSTORE_WRITE, vstore_write, EC_VER_MASK(0));
 
-static void vstore_clear_lock(void)
+test_export_static void vstore_clear_lock(void)
 {
 	int i;
 
diff --git a/common/webusb_desc.c b/common/webusb_desc.c
index 41d39006e0..e2f51b4c0f 100644
--- a/common/webusb_desc.c
+++ b/common/webusb_desc.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/common/wireless.c b/common/wireless.c
index d1f5cad645..dfc2d4843e 100644
--- a/common/wireless.c
+++ b/common/wireless.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -34,13 +34,11 @@ static int suspend_flags = CONFIG_WIRELESS_SUSPEND;
 static void wireless_enable(int flags)
 {
 #ifdef WIRELESS_GPIO_WLAN
-	gpio_set_level(WIRELESS_GPIO_WLAN,
-		       flags & EC_WIRELESS_SWITCH_WLAN);
+	gpio_set_level(WIRELESS_GPIO_WLAN, flags & EC_WIRELESS_SWITCH_WLAN);
 #endif
 
 #ifdef WIRELESS_GPIO_WWAN
-	gpio_set_level(WIRELESS_GPIO_WWAN,
-		       flags & EC_WIRELESS_SWITCH_WWAN);
+	gpio_set_level(WIRELESS_GPIO_WWAN, flags & EC_WIRELESS_SWITCH_WWAN);
 #endif
 
 #ifdef WIRELESS_GPIO_BLUETOOTH
@@ -57,7 +55,6 @@ static void wireless_enable(int flags)
 		       !(flags & EC_WIRELESS_SWITCH_WLAN_POWER));
 #endif /* CONFIG_WLAN_POWER_ACTIVE_LOW */
 #endif
-
 }
 
 static int wireless_get(void)
@@ -126,7 +123,7 @@ static enum ec_status wireless_enable_cmd(struct host_cmd_handler_args *args)
 			(p->now_flags & p->now_mask));
 
 	suspend_flags = (suspend_flags & ~p->suspend_mask) |
-		(p->suspend_flags & p->suspend_mask);
+			(p->suspend_flags & p->suspend_mask);
 
 	/* And return the current flags */
 	r->now_flags = wireless_get();
@@ -134,11 +131,10 @@ static enum ec_status wireless_enable_cmd(struct host_cmd_handler_args *args)
 	args->response_size = sizeof(*r);
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_SWITCH_ENABLE_WIRELESS,
-		     wireless_enable_cmd,
+DECLARE_HOST_COMMAND(EC_CMD_SWITCH_ENABLE_WIRELESS, wireless_enable_cmd,
 		     EC_VER_MASK(0) | EC_VER_MASK(1));
 
-static int command_wireless(int argc, char **argv)
+static int command_wireless(int argc, const char **argv)
 {
 	char *e;
 	int i;
@@ -164,6 +160,5 @@ static int command_wireless(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(wireless, command_wireless,
-			"[now [suspend]]",
+DECLARE_CONSOLE_COMMAND(wireless, command_wireless, "[now [suspend]]",
 			"Get/set wireless flags");
diff --git a/core/build.mk b/core/build.mk
new file mode 100644
index 0000000000..407550bf7c
--- /dev/null
+++ b/core/build.mk
@@ -0,0 +1,20 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CORE_RW_OUT:=$(out)/RW/core/$(CORE)
+CORE_RO_OUT:=$(out)/RO/core/$(CORE)
+
+cmd_asm_define_to_h = grep ASM_DEFINE $< \
+	| sed 's/.*__ASM_DEFINE__\s\(.*\)\s\#\(.*\)"/\#define \1 \2/g' > $@
+
+$(CORE_RO_OUT)/asm_offsets.h:$(CORE_RO_OUT)/asm_offsets.s
+	$(call quiet,asm_define_to_h,     )
+$(CORE_RW_OUT)/asm_offsets.h:$(CORE_RW_OUT)/asm_offsets.s
+	$(call quiet,asm_define_to_h,     )
+
+$(CORE_RW_OUT)/asm_offsets.s: core/$(CORE)/asm_offsets.c
+$(CORE_RW_OUT)/asm_offsets.h: $(CORE_RW_OUT)/asm_offsets.s
+
+$(CORE_RO_OUT)/asm_offsets.s: core/$(CORE)/asm_offsets.c
+$(CORE_RO_OUT)/asm_offsets.h: $(CORE_RO_OUT)/asm_offsets.s
diff --git a/core/cortex-m/aes.S b/core/cortex-m/aes.S
deleted file mode 120000
index 39d1286943..0000000000
--- a/core/cortex-m/aes.S
+++ /dev/null
@@ -1 +0,0 @@
-../../third_party/boringssl/core/cortex-m/aes.S
\ No newline at end of file
diff --git a/core/cortex-m/atomic.h b/core/cortex-m/atomic.h
index 736d5887b4..92ecdd96e5 100644
--- a/core/cortex-m/atomic.h
+++ b/core/cortex-m/atomic.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,69 +8,37 @@
 #ifndef __CROS_EC_ATOMIC_H
 #define __CROS_EC_ATOMIC_H
 
+#include "atomic_t.h"
 #include "common.h"
 
-/**
- * Implements atomic arithmetic operations on 32-bit integers.
- *
- * It used load/store exclusive.
- * If you write directly the integer used as an atomic variable,
- * you must either clear explicitly the exclusive monitor (using clrex)
- * or do it in exception context (which clears the monitor).
- */
-#define ATOMIC_OP(asm_op, a, v) do {				\
-	uint32_t reg0, reg1;                                    \
-								\
-	__asm__ __volatile__("1: ldrex   %0, [%2]\n"            \
-			     #asm_op" %0, %0, %3\n"		\
-			     "   strex   %1, %0, [%2]\n"        \
-			     "   teq     %1, #0\n"              \
-			     "   bne     1b"                    \
-			     : "=&r" (reg0), "=&r" (reg1)       \
-			     : "r" (a), "r" (v) : "cc");        \
-} while (0)
-
-/*
- * The atomic_* functions are marked as deprecated as a part of the process of
- * transaction to Zephyr compatible atomic functions. These prefixes will be
- * removed in the following patches. Please see b:169151160 for more details.
- */
-
-static inline void deprecated_atomic_clear_bits(uint32_t volatile *addr,
-						uint32_t bits)
+static inline atomic_val_t atomic_clear_bits(atomic_t *addr, atomic_val_t bits)
 {
-	ATOMIC_OP(bic, addr, bits);
+	return __atomic_fetch_and(addr, ~bits, __ATOMIC_SEQ_CST);
 }
 
-static inline void deprecated_atomic_or(uint32_t volatile *addr, uint32_t bits)
+static inline atomic_val_t atomic_or(atomic_t *addr, atomic_val_t bits)
 {
-	ATOMIC_OP(orr, addr, bits);
+	return __atomic_fetch_or(addr, bits, __ATOMIC_SEQ_CST);
 }
 
-static inline void deprecated_atomic_add(uint32_t volatile *addr,
-					 uint32_t value)
+static inline atomic_val_t atomic_add(atomic_t *addr, atomic_val_t value)
 {
-	ATOMIC_OP(add, addr, value);
+	return __atomic_fetch_add(addr, value, __ATOMIC_SEQ_CST);
 }
 
-static inline void deprecated_atomic_sub(uint32_t volatile *addr,
-					 uint32_t value)
+static inline atomic_val_t atomic_sub(atomic_t *addr, atomic_val_t value)
 {
-	ATOMIC_OP(sub, addr, value);
+	return __atomic_fetch_sub(addr, value, __ATOMIC_SEQ_CST);
 }
 
-static inline uint32_t deprecated_atomic_read_clear(uint32_t volatile *addr)
+static inline atomic_val_t atomic_clear(atomic_t *addr)
 {
-	uint32_t ret, tmp;
-
-	__asm__ __volatile__("   mov     %3, #0\n"
-			     "1: ldrex   %0, [%2]\n"
-			     "   strex   %1, %3, [%2]\n"
-			     "   teq     %1, #0\n"
-			     "   bne     1b"
-			     : "=&r" (ret), "=&r" (tmp)
-			     : "r" (addr), "r" (0) : "cc");
+	return __atomic_exchange_n(addr, 0, __ATOMIC_SEQ_CST);
+}
 
-	return ret;
+static inline atomic_val_t atomic_and(atomic_t *addr, atomic_val_t bits)
+{
+	return __atomic_fetch_and(addr, bits, __ATOMIC_SEQ_CST);
 }
-#endif  /* __CROS_EC_ATOMIC_H */
+
+#endif /* __CROS_EC_ATOMIC_H */
diff --git a/core/cortex-m/build.mk b/core/cortex-m/build.mk
index 2bcf32317d..9562a31ec4 100644
--- a/core/cortex-m/build.mk
+++ b/core/cortex-m/build.mk
@@ -1,21 +1,38 @@
 # -*- makefile -*-
-# Copyright 2012 The Chromium OS Authors. All rights reserved.
+# Copyright 2012 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
 # Cortex-M4 core OS files build
 #
 
-# Use coreboot-sdk
-$(call set-option,CROSS_COMPILE,\
-	$(CROSS_COMPILE_arm),\
-	/opt/coreboot-sdk/bin/arm-eabi-)
-
 # FPU compilation flags
-CFLAGS_FPU-$(CONFIG_FPU)=-mfpu=fpv4-sp-d16 -mfloat-abi=hard
+CFLAGS_FPU-$(CONFIG_FPU)=-mfloat-abi=hard
+ifeq ($(cc-name),gcc)
+# -mfpu=auto will choose correct hardware based on settings of -mcpu and -march
+# https://gcc.gnu.org/onlinedocs/gcc/ARM-Options.html.
+#
+# According to the above doc "-mfpu=auto" is the default and shouldn't be
+# required, but compilation using gcc fails without the flag.
+#
+# clang does not support "-mfpu=auto" flag, but will choose the correct floating
+# point unit based on the -mcpu flag:
+# https://lists.llvm.org/pipermail/llvm-dev/2018-September/126468.html
+CFLAGS_FPU-$(CONFIG_FPU)+=-mfpu=auto
+endif
 
 # CPU specific compilation flags
-CFLAGS_CPU+=-mthumb -Os -mno-sched-prolog
+CFLAGS_CPU+=-mthumb
+ifeq ($(cc-name),clang)
+CFLAGS_CPU+=-Oz		# Like -Os (and thus -O2), but reduces code size further.
+# b/256193799: Reduce inline threshold to decrease code size.
+CFLAGS_CPU+=-Wl,-mllvm -Wl,-inline-threshold=-10
+# Link compiler-rt when using clang, so clang finds the builtins it provides.
+LDFLAGS_EXTRA+=-lclang_rt.builtins-armv7m
+else
+CFLAGS_CPU+=-Os
+CFLAGS_CPU+=-mno-sched-prolog
+endif
 CFLAGS_CPU+=-mno-unaligned-access
 CFLAGS_CPU+=$(CFLAGS_FPU-y)
 
@@ -24,11 +41,14 @@ CFLAGS_CPU+=-flto
 LDFLAGS_EXTRA+=-flto
 endif
 
-core-y=cpu.o init.o ldivmod.o llsr.o uldivmod.o vecttable.o
-core-$(CONFIG_AES)+=aes.o
-core-$(CONFIG_AES_GCM)+=ghash.o
+core-y=cpu.o debug.o init.o vecttable.o
+# When using clang, we get these as builtins from compiler-rt.
+ifneq ($(cc-name),clang)
+core-y+=ldivmod.o llsr.o uldivmod.o
+endif
 core-$(CONFIG_ARMV7M_CACHE)+=cache.o
 core-$(CONFIG_COMMON_PANIC_OUTPUT)+=panic.o
 core-$(CONFIG_COMMON_RUNTIME)+=switch.o task.o
+core-$(CONFIG_FPU)+=fpu.o
 core-$(CONFIG_WATCHDOG)+=watchdog.o
 core-$(CONFIG_MPU)+=mpu.o
diff --git a/core/cortex-m/cache.S b/core/cortex-m/cache.S
index 0a3d3bb67d..d5089a920e 100644
--- a/core/cortex-m/cache.S
+++ b/core/cortex-m/cache.S
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/cortex-m/config_core.h b/core/cortex-m/config_core.h
index 0665b28852..3b9ccb89e6 100644
--- a/core/cortex-m/config_core.h
+++ b/core/cortex-m/config_core.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,6 +10,4 @@
 #define BFD_ARCH arm
 #define BFD_FORMAT "elf32-littlearm"
 
-#define CONFIG_SOFTWARE_PANIC
-
 #endif /* __CROS_EC_CONFIG_CORE_H */
diff --git a/core/cortex-m/cpu.c b/core/cortex-m/cpu.c
index 96ac96a016..5a882bb532 100644
--- a/core/cortex-m/cpu.c
+++ b/core/cortex-m/cpu.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -9,6 +9,10 @@
 #include "cpu.h"
 #include "hooks.h"
 
+#define STACK_IDX_REG_LR 5
+#define STACK_IDX_REG_PC 6
+#define STACK_IDX_REG_PSR 7
+
 void cpu_init(void)
 {
 	/* Catch divide by 0 and unaligned access */
@@ -16,7 +20,42 @@ void cpu_init(void)
 
 	/* Enable reporting of memory faults, bus faults and usage faults */
 	CPU_NVIC_SHCSR |= CPU_NVIC_SHCSR_MEMFAULTENA |
-		CPU_NVIC_SHCSR_BUSFAULTENA | CPU_NVIC_SHCSR_USGFAULTENA;
+			  CPU_NVIC_SHCSR_BUSFAULTENA |
+			  CPU_NVIC_SHCSR_USGFAULTENA;
+}
+
+void cpu_return_from_exception_msp(void (*func)(void))
+{
+	uint32_t *msp;
+
+	__asm__ volatile("mrs %0, msp" : "=r"(msp));
+
+	msp[STACK_IDX_REG_LR] = 0; /* Will never return */
+	msp[STACK_IDX_REG_PC] = (uint32_t)func; /* Return to this function */
+	msp[STACK_IDX_REG_PSR] = (1 << 24); /* Just set thumb mode */
+
+	/* Return from exception using main stack */
+	__asm__ volatile("bx %0" : : "r"(0xFFFFFFF9));
+
+	/* should not reach here */
+	__builtin_unreachable();
+}
+
+void cpu_return_from_exception_psp(void (*func)(void))
+{
+	uint32_t *psp;
+
+	__asm__ volatile("mrs %0, psp" : "=r"(psp));
+
+	psp[STACK_IDX_REG_LR] = 0; /* Will never return */
+	psp[STACK_IDX_REG_PC] = (uint32_t)func; /* Return to this function */
+	psp[STACK_IDX_REG_PSR] = (1 << 24); /* Just set thumb mode */
+
+	/* Return from exception using main stack */
+	__asm__ volatile("bx %0" : : "r"(0xFFFFFFFD));
+
+	/* should not reach here */
+	__builtin_unreachable();
 }
 
 #ifdef CONFIG_ARMV7M_CACHE
@@ -50,16 +89,16 @@ void cpu_enable_caches(void)
 	}
 }
 
-static void cpu_sysjump_cache(void)
+void cpu_disable_caches(void)
 {
 	/*
 	 * Disable the I-cache and the D-cache
-	 * The I-cache will be invalidated after the sysjump if needed
+	 * The I-cache will be invalidated after the reboot/sysjump if needed
 	 * (e.g after a flash update).
 	 */
 	cpu_clean_invalidate_dcache();
 	CPU_NVIC_CCR &= ~(CPU_NVIC_CCR_ICACHE | CPU_NVIC_CCR_DCACHE);
 	asm volatile("dsb; isb");
 }
-DECLARE_HOOK(HOOK_SYSJUMP, cpu_sysjump_cache, HOOK_PRIO_LAST);
+DECLARE_HOOK(HOOK_SYSJUMP, cpu_disable_caches, HOOK_PRIO_LAST);
 #endif /* CONFIG_ARMV7M_CACHE */
diff --git a/core/cortex-m/cpu.h b/core/cortex-m/cpu.h
index 5f7dd02801..d3144006f6 100644
--- a/core/cortex-m/cpu.h
+++ b/core/cortex-m/cpu.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,72 +8,115 @@
 #ifndef __CROS_EC_CPU_H
 #define __CROS_EC_CPU_H
 
-#include <stdint.h>
 #include "compile_time_macros.h"
+#include "debug.h"
+
+#include <stdint.h>
 
 /* Macro to access 32-bit registers */
-#define CPUREG(addr) (*(volatile uint32_t*)(addr))
+#define CPUREG(addr) (*(volatile uint32_t *)(addr))
 
-#define CPU_NVIC_ST_CTRL       CPUREG(0xE000E010)
-#define ST_ENABLE              BIT(0)
-#define ST_TICKINT             BIT(1)
-#define ST_CLKSOURCE           BIT(2)
-#define ST_COUNTFLAG           BIT(16)
+#define CPU_NVIC_ST_CTRL CPUREG(0xE000E010)
+#define ST_ENABLE BIT(0)
+#define ST_TICKINT BIT(1)
+#define ST_CLKSOURCE BIT(2)
+#define ST_COUNTFLAG BIT(16)
 
 /* Nested Vectored Interrupt Controller */
-#define CPU_NVIC_EN(x)         CPUREG(0xe000e100 + 4 * (x))
-#define CPU_NVIC_DIS(x)        CPUREG(0xe000e180 + 4 * (x))
-#define CPU_NVIC_UNPEND(x)     CPUREG(0xe000e280 + 4 * (x))
-#define CPU_NVIC_PRI(x)        CPUREG(0xe000e400 + 4 * (x))
+#define CPU_NVIC_EN(x) CPUREG(0xe000e100 + 4 * (x))
+#define CPU_NVIC_DIS(x) CPUREG(0xe000e180 + 4 * (x))
+#define CPU_NVIC_UNPEND(x) CPUREG(0xe000e280 + 4 * (x))
+#define CPU_NVIC_PRI(x) CPUREG(0xe000e400 + 4 * (x))
 /* SCB AIRCR : Application interrupt and reset control register */
-#define CPU_NVIC_APINT         CPUREG(0xe000ed0c)
-#define  CPU_NVIC_APINT_SYSRST  BIT(2)            /* System reset request */
-#define  CPU_NVIC_APINT_PRIOGRP (BIT(8)|BIT(9)|BIT(10))
-#define  CPU_NVIC_APINT_ENDIAN  BIT(15)           /* Endianness */
-#define  CPU_NVIC_APINT_KEY_RD  (0xFA05U << 16)
-#define  CPU_NVIC_APINT_KEY_WR  (0x05FAU << 16)
+#define CPU_NVIC_APINT CPUREG(0xe000ed0c)
+#define CPU_NVIC_APINT_SYSRST BIT(2) /* System reset request */
+#define CPU_NVIC_APINT_PRIOGRP (BIT(8) | BIT(9) | BIT(10))
+#define CPU_NVIC_APINT_ENDIAN BIT(15) /* Endianness */
+#define CPU_NVIC_APINT_KEY_RD (0xFA05U << 16)
+#define CPU_NVIC_APINT_KEY_WR (0x05FAU << 16)
 /* NVIC STIR : Software Trigger Interrupt Register */
-#define CPU_NVIC_SWTRIG        CPUREG(0xe000ef00)
+#define CPU_NVIC_SWTRIG CPUREG(0xe000ef00)
 /* SCB SCR : System Control Register */
-#define CPU_SCB_SYSCTRL        CPUREG(0xe000ed10)
+#define CPU_SCB_SYSCTRL CPUREG(0xe000ed10)
 
-#define CPU_NVIC_CCR           CPUREG(0xe000ed14)
-#define CPU_NVIC_SHCSR         CPUREG(0xe000ed24)
-#define CPU_NVIC_CFSR          CPUREG(0xe000ed28)
-#define CPU_NVIC_HFSR          CPUREG(0xe000ed2c)
-#define CPU_NVIC_DFSR          CPUREG(0xe000ed30)
-#define CPU_NVIC_MFAR          CPUREG(0xe000ed34)
-#define CPU_NVIC_BFAR          CPUREG(0xe000ed38)
+#define CPU_NVIC_CCR CPUREG(0xe000ed14)
+#define CPU_NVIC_SHCSR CPUREG(0xe000ed24)
+#define CPU_NVIC_CFSR CPUREG(0xe000ed28)
+#define CPU_NVIC_HFSR CPUREG(0xe000ed2c)
+#define CPU_NVIC_DFSR CPUREG(0xe000ed30)
+#define CPU_NVIC_MFAR CPUREG(0xe000ed34)
+#define CPU_NVIC_BFAR CPUREG(0xe000ed38)
 
 enum {
-	CPU_NVIC_CFSR_BFARVALID		= BIT(15),
-	CPU_NVIC_CFSR_MFARVALID		= BIT(7),
+	CPU_NVIC_CFSR_BFARVALID = BIT(15),
+	CPU_NVIC_CFSR_MFARVALID = BIT(7),
 
-	CPU_NVIC_CCR_ICACHE		= BIT(17),
-	CPU_NVIC_CCR_DCACHE		= BIT(16),
-	CPU_NVIC_CCR_DIV_0_TRAP		= BIT(4),
-	CPU_NVIC_CCR_UNALIGN_TRAP	= BIT(3),
+	CPU_NVIC_CCR_ICACHE = BIT(17),
+	CPU_NVIC_CCR_DCACHE = BIT(16),
+	CPU_NVIC_CCR_DIV_0_TRAP = BIT(4),
+	CPU_NVIC_CCR_UNALIGN_TRAP = BIT(3),
 
-	CPU_NVIC_HFSR_DEBUGEVT		= 1UL << 31,
-	CPU_NVIC_HFSR_FORCED		= BIT(30),
-	CPU_NVIC_HFSR_VECTTBL		= BIT(1),
+	CPU_NVIC_HFSR_DEBUGEVT = 1UL << 31,
+	CPU_NVIC_HFSR_FORCED = BIT(30),
+	CPU_NVIC_HFSR_VECTTBL = BIT(1),
 
-	CPU_NVIC_SHCSR_MEMFAULTENA	= BIT(16),
-	CPU_NVIC_SHCSR_BUSFAULTENA	= BIT(17),
-	CPU_NVIC_SHCSR_USGFAULTENA	= BIT(18),
+	CPU_NVIC_SHCSR_MEMFAULTENA = BIT(16),
+	CPU_NVIC_SHCSR_BUSFAULTENA = BIT(17),
+	CPU_NVIC_SHCSR_USGFAULTENA = BIT(18),
 };
 
 /* System Control Block: cache registers */
-#define CPU_SCB_CCSIDR         CPUREG(0xe000ed80)
-#define CPU_SCB_CCSELR         CPUREG(0xe000ed84)
-#define CPU_SCB_ICIALLU        CPUREG(0xe000ef50)
-#define CPU_SCB_DCISW          CPUREG(0xe000ef60)
-#define CPU_SCB_DCCISW         CPUREG(0xe000ef74)
+#define CPU_SCB_CCSIDR CPUREG(0xe000ed80)
+#define CPU_SCB_CCSELR CPUREG(0xe000ed84)
+#define CPU_SCB_ICIALLU CPUREG(0xe000ef50)
+#define CPU_SCB_DCISW CPUREG(0xe000ef60)
+#define CPU_SCB_DCCISW CPUREG(0xe000ef74)
+
+/* Floating Point Context Address Register */
+#define CPU_FPU_FPCAR CPUREG(0xe000ef38)
+
+/*
+ * As defined by Armv7-M Reference Manual B1.5.7 "Context state stacking on
+ * exception entry with the FP extension" the structure of the FPU state is:
+ * s0, s1, ..., s14, s15, fpscr.
+ */
+#define FPU_IDX_REG_FPSCR 16
+#define FPU_FPSCR_IOC BIT(0) /* Invalid operation */
+#define FPU_FPSCR_DZC BIT(1) /* Division by zero */
+#define FPU_FPSCR_OFC BIT(2) /* Overflow */
+#define FPU_FPSCR_UFC BIT(3) /* Underflow */
+#define FPU_FPSCR_IXC BIT(4) /* Inexact */
+#define FPU_FPSCR_IDC BIT(7) /* Input denormal */
+#define FPU_FPSCR_EXC_FLAGS                                              \
+	(FPU_FPSCR_IOC | FPU_FPSCR_DZC | FPU_FPSCR_OFC | FPU_FPSCR_UFC | \
+	 FPU_FPSCR_IXC | FPU_FPSCR_IDC)
+
+/* Bitfield values for EXC_RETURN. */
+#define EXC_RETURN_ES_MASK BIT(0)
+#define EXC_RETURN_ES_NON_SECURE 0
+#define EXC_RETURN_ES_SECURE BIT(0)
+#define EXC_RETURN_SPSEL_MASK BIT(2)
+#define EXC_RETURN_SPSEL_MSP 0
+#define EXC_RETURN_SPSEL_PSP BIT(2)
+#define EXC_RETURN_MODE_MASK BIT(3)
+#define EXC_RETURN_MODE_HANDLER 0
+#define EXC_RETURN_MODE_THREAD BIT(3)
+#define EXC_RETURN_FTYPE_MASK BIT(4)
+#define EXC_RETURN_FTYPE_ON 0
+#define EXC_RETURN_FTYPE_OFF BIT(4)
+#define EXC_RETURN_DCRS_MASK BIT(5)
+#define EXC_RETURN_DCRS_OFF 0
+#define EXC_RETURN_DCRS_ON BIT(5)
+#define EXC_RETURN_S_MASK BIT(6)
+#define EXC_RETURN_S_NON_SECURE 0
+#define EXC_RETURN_S_SECURE BIT(6)
 
 /* Set up the cpu to detect faults */
 void cpu_init(void);
 /* Enable the CPU I-cache and D-cache if they are not already enabled */
 void cpu_enable_caches(void);
+/* Disable the CPU I-cache and D-cache */
+void cpu_disable_caches(void);
 /* Invalidate the D-cache */
 void cpu_invalidate_dcache(void);
 /* Clean and Invalidate the D-cache to the Point of Coherency */
@@ -84,6 +127,11 @@ void cpu_invalidate_dcache_range(uintptr_t base, unsigned int length);
 /* Clean and Invalidate a single range of the D-cache */
 void cpu_clean_invalidate_dcache_range(uintptr_t base, unsigned int length);
 
+/* Return to specified function from exception handler using main stack. */
+void cpu_return_from_exception_msp(void (*func)(void));
+/* Return to specified function from exception handler using process stack. */
+void cpu_return_from_exception_psp(void (*func)(void));
+
 /* Set the priority of the given IRQ in the NVIC (0 is highest). */
 static inline void cpu_set_interrupt_priority(uint8_t irq, uint8_t priority)
 {
@@ -92,10 +140,16 @@ static inline void cpu_set_interrupt_priority(uint8_t irq, uint8_t priority)
 	if (priority > 7)
 		priority = 7;
 
-	CPU_NVIC_PRI(irq / 4) =
-		(CPU_NVIC_PRI(irq / 4) &
-		 ~(7 << prio_shift)) |
-		(priority << prio_shift);
+	CPU_NVIC_PRI(irq / 4) = (CPU_NVIC_PRI(irq / 4) & ~(7 << prio_shift)) |
+				(priority << prio_shift);
+}
+
+static inline void cpu_enter_suspend_mode(void)
+{
+	/* Preserve debug sessions by not suspending when connected */
+	if (!debugger_is_connected()) {
+		asm("wfi");
+	}
 }
 
 #endif /* __CROS_EC_CPU_H */
diff --git a/core/cortex-m/debug.c b/core/cortex-m/debug.c
new file mode 100644
index 0000000000..214e8dd177
--- /dev/null
+++ b/core/cortex-m/debug.c
@@ -0,0 +1,12 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "debug.h"
+#include "stdbool.h"
+
+bool debugger_is_connected(void)
+{
+	return CPU_DHCSR & DHCSR_C_DEBUGEN;
+}
diff --git a/core/cortex-m/debug.h b/core/cortex-m/debug.h
new file mode 100644
index 0000000000..30643268cb
--- /dev/null
+++ b/core/cortex-m/debug.h
@@ -0,0 +1,37 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_DEBUG_H
+#define __CROS_EC_DEBUG_H
+
+#include "common.h"
+#include "stdbool.h"
+
+/* For Cortex-M0, see "C1.6.3 Debug Halting Control and Status Register, DHCSR"
+ * in the ARMv6-M Architecture Reference Manual.
+ *
+ * For other Cortex-M, see
+ * "C1.6.2 Debug Halting Control and Status Register, DHCSR" in the ARMv7-M
+ * Architecture Reference Manual or
+ * https://developer.arm.com/documentation/ddi0337/e/core-debug/core-debug-registers/debug-halting-control-and-status-register.
+ */
+#define CPU_DHCSR REG32(0xE000EDF0)
+#define DHCSR_C_DEBUGEN BIT(0)
+#define DHCSR_C_HALT BIT(1)
+#define DHCSR_C_STEP BIT(2)
+#define DHCSR_C_MASKINTS BIT(3)
+#ifndef CHIP_CORE_CORTEX_M0
+#define DHCSR_C_SNAPSTALL BIT(5) /* Not available on Cortex-M0 */
+#endif
+#define DHCSR_S_REGRDY BIT(16)
+#define DHCSR_S_HALT BIT(17)
+#define DHCSR_S_SLEEP BIT(18)
+#define DHCSR_S_LOCKUP BIT(19)
+#define DHCSR_S_RETIRE_ST BIT(24)
+#define DHCSR_S_RESET_ST BIT(25)
+
+bool debugger_is_connected(void);
+
+#endif /* __CROS_EC_DEBUG_H */
diff --git a/core/cortex-m/ec.lds.S b/core/cortex-m/ec.lds.S
index fc24d181b5..6fb3b48568 100644
--- a/core/cortex-m/ec.lds.S
+++ b/core/cortex-m/ec.lds.S
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -145,12 +145,6 @@ SECTIONS
 	} > SHARED_LIB
 #endif
 	.text : {
-#ifdef SECTION_IS_RO
-		. = . +  CONFIG_RO_HEAD_ROOM;
-#endif
-#ifdef SECTION_IS_RW
-		. = . +  CONFIG_RW_HEAD_ROOM;
-#endif
 		*(.text.vecttable)
 		. = ALIGN(4);
 		__image_data_offset = .;
@@ -261,6 +255,10 @@ SECTIONS
 		KEEP(*(.rodata.HOOK_CHIPSET_SHUTDOWN_COMPLETE))
 		__hooks_chipset_shutdown_complete_end = .;
 
+		__hooks_chipset_hard_off = .;
+		KEEP(*(.rodata.HOOK_CHIPSET_HARD_OFF))
+		__hooks_chipset_hard_off_end = .;
+
 		__hooks_chipset_reset = .;
 		KEEP(*(.rodata.HOOK_CHIPSET_RESET))
 		__hooks_chipset_reset_end = .;
@@ -277,6 +275,12 @@ SECTIONS
 		KEEP(*(.rodata.HOOK_TABLET_MODE_CHANGE))
 		__hooks_tablet_mode_change_end = .;
 
+#ifdef CONFIG_BODY_DETECTION
+		__hooks_body_detect_change = .;
+		KEEP(*(.rodata.HOOK_BODY_DETECT_CHANGE))
+		__hooks_body_detect_change_end = .;
+#endif
+
 		__hooks_base_attached_change = .;
 		KEEP(*(.rodata.HOOK_BASE_ATTACHED_CHANGE))
 		__hooks_base_attached_change_end = .;
@@ -311,6 +315,10 @@ SECTIONS
 		KEEP(*(.rodata.HOOK_USB_PD_CONNECT))
 		__hooks_usb_pd_connect_end = .;
 
+		__hooks_power_supply_change = .;
+		KEEP(*(.rodata.HOOK_POWER_SUPPLY_CHANGE))
+		__hooks_power_supply_change_end = .;
+
 		__deferred_funcs = .;
 		KEEP(*(.rodata.deferred))
 		__deferred_funcs_end = .;
@@ -341,22 +349,66 @@ SECTIONS
 		__init_rom_end = .;
 #endif /* CONFIG_CHIP_INIT_ROM_REGION */
 
-#if defined(SECTION_IS_RO) && defined(CONFIG_FLASH)
+#if defined(SECTION_IS_RO) && defined(CONFIG_FLASH_CROS)
 		. = ALIGN(64);
 		KEEP(*(.google))
 #endif
 
+		/*
+		 * https://developer.arm.com/documentation/dui0475/c/the-arm-c-and-c---libraries/c---initialization--construction-and-destruction
+		 */
+		. = ALIGN(4);
+		__init_array_start = .;
+		*(.init_array*)
+		__init_array_end = .;
+
+		/*
+		 * Empty C++ exception index table. The exception index
+		 * table is described in more detail in "Exception Handling
+		 * ABI for ARM Architecture":
+		 * https://github.com/ARM-software/abi-aa/blob/60a8eb8c55e999d74dac5e368fc9d7e36e38dda4/ehabi32/ehabi32.rst#54the-object-producer-interface
+		 */
+		__exidx_start = 0;
+		__exidx_end = 0;
+
 		. = ALIGN(4);
 	} > EC_IMAGE_VMA_MEM_REGION AT > EC_IMAGE_LMA_MEM_REGION
 
 #ifdef CONFIG_CHIP_DATA_IN_INIT_ROM
 	__data_lma_start = ORIGIN(ROM_RESIDENT_VMA);
 	#define INIT_ROM_LMA	(ORIGIN(ROM_RESIDENT_VMA) + SIZEOF(.data))
+#else
+/*
+ * TODO(b/202863352): Unify clang and gcc behavior.
+ */
+#ifdef __clang__
+#if defined(SECTION_IS_RO) && defined(NPCX_RO_HEADER)
+	__data_lma_start = LOADADDR(.data) - SIZEOF(.header);
+#else
+	__data_lma_start = LOADADDR(.data);
+#endif
 #else
 	__data_lma_start = .;
+#endif
 	#define INIT_ROM_LMA	ORIGIN(ROM_RESIDENT_VMA)
 #endif
 
+	/*
+	 * This SRAM section is not used by common/ or chip/stm32/, but
+	 * available if particular boards want to move the vector table
+	 * into SRAM for performance or mutability.
+	 */
+	.vtable : {
+		/*
+		 * Vector table must be at the base of SRAM. The vector
+		 * table section contains a RAM copy of the vector table used on
+		 * STM chips for relocating the vector table.
+		 */
+		. = ALIGN(8);
+		*(.bss.vector_table)
+		. = ALIGN(8);
+	} > IRAM
+
 #ifdef CONFIG_PRESERVE_LOGS
 	.preserve_logs(NOLOAD) : {
 		. = ALIGN(8);
@@ -391,7 +443,7 @@ SECTIONS
 			*(.bss.Tpm2_common)
 		__bss_libtpm2_end = .;
 
-		*(.bss)
+		*(.bss*)
 
 		/*
 		 * Reserve space for deferred function firing times.
@@ -403,16 +455,7 @@ SECTIONS
 		__deferred_until = .;
 		. += (__deferred_funcs_end - __deferred_funcs) * (8 / 4);
 		__deferred_until_end = .;
-	} > IRAM
 
-	.bss.slow : {
-		/* Region of RAM reclaimed from the little firmware(LFW). */
-		*(.bss.slow)
-		/*
-		 * Not replacing the loader, so .bss.slow is part of .bss.
-		 * It needs to be followed by __bss_end so that .bss.slow
-		 * will be zeroed by init.
-		 */
 		. = ALIGN(4);
 		__bss_end = .;
 	} > IRAM
@@ -476,6 +519,17 @@ SECTIONS
 	__ram_free = (CONFIG_RAM_BASE + CONFIG_RAM_SIZE) -
 		     (__shared_mem_buf + CONFIG_SHAREDMEM_MINIMUM_SIZE);
 
+	/*
+	 * Relocations are not supported, so make sure that there is no GOT
+	 * section. See http://issuetracker.google.com/234507656#comment15.
+	 */
+	.got (NOLOAD) :
+	{
+		KEEP(*(.got*));
+	}
+	ASSERT(SIZEOF(.got) == 0, "GOT section found, but not supported.\
+ Make sure that all code is compiled without -fPIC.")
+
 #ifdef CONFIG_CHIP_DATA_IN_INIT_ROM
 	/*
 	 * .data is ROM resident, last section in the EC image is the .rodata
@@ -490,20 +544,39 @@ SECTIONS
 #endif
 
 	/*
-	 * __flash_used is used in flash free calculations by the makefile.
+	 * __flash_used and __flash_size is used in flash free calculations by
+	 * the makefile. Note the difference between __flash_size and
+	 * __config_flash_size. __flash_size is the flash size for the given
+	 * image (RW, RO, etc.), while __config_flash_size is the *total*
+	 * flash size.
 	 * __image_size is stored in the struct image_data header and used
-	 * in hash calcuations.
+	 * in hash calculations.
 	 */
 	__flash_used = FLASH_USED_END - ORIGIN(EC_IMAGE_LMA_MEM_REGION);
+	__flash_size = LENGTH(EC_IMAGE_LMA_MEM_REGION);
 #ifndef CONFIG_CHIP_INIT_ROM_REGION
+#if defined(SECTION_IS_RW) && (CONFIG_FLASH_WRITE_SIZE > 4)
+	.rw_image_size_alignment FLASH_USED_END : AT(FLASH_USED_END)
+	{
+		. = ALIGN (CONFIG_FLASH_WRITE_SIZE);
+	} > FLASH = 0xFF
+
+	__image_size = __flash_used + SIZEOF(.rw_image_size_alignment);
+#else
 	__image_size = __flash_used;
+#endif
+#if defined(SECTION_IS_RW) && (CONFIG_FLASH_WRITE_SIZE > 0)
+	/* Alignment is needed by flash_command_write() for RW update. */
+	ASSERT(__image_size % CONFIG_FLASH_WRITE_SIZE == 0,
+	       "Error: RW image is not aligned to CONFIG_FLASH_WRITE_SIZE")
+#endif
 #endif /* CONFIG_CHIP_INIT_ROM_REGION */
 
-#ifdef CONFIG_FLASH
+#ifdef CONFIG_FLASH_CROS
         /*
          * These linker labels are just for analysis and not used in the code.
          */
-	__config_flash_size = CONFIG_FLASH_SIZE;
+	__config_flash_size = CONFIG_FLASH_SIZE_BYTES;
 	__config_ro_size = CONFIG_RO_SIZE;
 	__config_ec_protected_storage_size = CONFIG_EC_PROTECTED_STORAGE_SIZE;
 	__config_rw_size = CONFIG_RW_SIZE;
@@ -699,7 +772,7 @@ SECTIONS
 	} > DRAM
 #endif
 
-#if !(defined(SECTION_IS_RO) && defined(CONFIG_FLASH))
+#if !(defined(SECTION_IS_RO) && defined(CONFIG_FLASH_CROS))
 	/DISCARD/ : { *(.google) }
 #endif
 	/DISCARD/ : { *(.ARM.*) }
diff --git a/core/cortex-m/fpu.c b/core/cortex-m/fpu.c
new file mode 100644
index 0000000000..6e897a5266
--- /dev/null
+++ b/core/cortex-m/fpu.c
@@ -0,0 +1,108 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "atomic.h"
+#include "console.h"
+#include "cpu.h"
+#include "hooks.h"
+#include "task.h"
+
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+#define CPUTS(format, args...) cputs(CC_SYSTEM, format, ##args)
+
+/* Floating point unit common code */
+
+/*
+ * As defined by Armv7-M Reference Manual B1.5.6 "Exception Entry Behavior",
+ * the structure of the saved context on the stack is:
+ * r0, r1, r2, r3, r12, lr, pc, psr, ...
+ */
+#define STACK_IDX_REG_LR 5
+#define STACK_IDX_REG_PC 6
+
+static atomic_t fpu_exc_present;
+static uint32_t fpu_pc;
+static uint32_t fpu_lr;
+static uint32_t fpu_fpscr;
+static int fpu_task;
+
+static void fpu_warn(void)
+{
+	if (!IS_ENABLED(CONFIG_FPU_WARNINGS) || !fpu_exc_present)
+		return;
+
+	CPRINTF("\n### FPU exception at PC=0x%08x LR=0x%08x ", fpu_pc, fpu_lr);
+	if (fpu_task == -1)
+		CPUTS("(exc) ###\n");
+	else
+		CPRINTF("(task %d) ###\n", fpu_task);
+
+	CPRINTF("### FPSCR=0x%08x => ", fpu_fpscr);
+	if (fpu_fpscr & FPU_FPSCR_IOC)
+		CPUTS("Invalid Operation ");
+
+	if (fpu_fpscr & FPU_FPSCR_DZC)
+		CPUTS("Division By Zero ");
+
+	if (fpu_fpscr & FPU_FPSCR_OFC)
+		CPUTS("Overflow ");
+
+	if (fpu_fpscr & FPU_FPSCR_UFC)
+		CPUTS("Underflow ");
+
+	if (fpu_fpscr & FPU_FPSCR_IXC)
+		CPUTS("Inexact ");
+
+	if (fpu_fpscr & FPU_FPSCR_IDC)
+		CPUTS("Input Denormal ");
+
+	CPUTS("###\n");
+
+	atomic_clear(&fpu_exc_present);
+}
+
+DECLARE_DEFERRED(fpu_warn);
+
+test_mockable void __keep fpu_irq(uint32_t excep_lr, uint32_t excep_sp)
+{
+	/*
+	 * Get address of exception FPU exception frame. FPCAR register points
+	 * to the beginning of allocated FPU exception frame on the stack.
+	 */
+	uint32_t *fpu_state = (uint32_t *)CPU_FPU_FPCAR;
+
+	if (IS_ENABLED(CONFIG_FPU_WARNINGS)) {
+		uint32_t *stack;
+
+		if (!fpu_exc_present) {
+			/*
+			 * Examine least significant 4 bits from exception LR
+			 * to find which stack should be used to find the
+			 * exception frame:
+			 * - 0xd - CPU was in Thread Mode and PSP was used
+			 * - 0x9 - CPU was in Thread Mode and MSP was used
+			 * - 0x1 - CPU was in Handler Mode and MSP was used
+			 */
+			if ((excep_lr & 0xf) == 0xd)
+				asm("mrs %0, psp" : "=r"(stack));
+			else
+				stack = (uint32_t *)excep_sp;
+
+			fpu_pc = stack[STACK_IDX_REG_PC];
+			fpu_lr = stack[STACK_IDX_REG_LR];
+			fpu_fpscr = fpu_state[FPU_IDX_REG_FPSCR];
+			fpu_task = -1;
+
+			if ((excep_lr & 0xf) != 0x1)
+				fpu_task = task_get_current();
+
+			atomic_add(&fpu_exc_present, 1);
+		}
+		hook_call_deferred(&fpu_warn_data, 0);
+	}
+
+	/* Clear FPSCR on stack */
+	fpu_state[FPU_IDX_REG_FPSCR] &= ~FPU_FPSCR_EXC_FLAGS;
+}
diff --git a/core/cortex-m/ghash.S b/core/cortex-m/ghash.S
deleted file mode 120000
index e9acbf4b25..0000000000
--- a/core/cortex-m/ghash.S
+++ /dev/null
@@ -1 +0,0 @@
-../../third_party/boringssl/core/cortex-m/ghash.S
\ No newline at end of file
diff --git a/core/cortex-m/include/fpu.h b/core/cortex-m/include/fpu.h
new file mode 100644
index 0000000000..74862d00ab
--- /dev/null
+++ b/core/cortex-m/include/fpu.h
@@ -0,0 +1,27 @@
+/* Copyright 2012 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Math utility functions for ARMv7 */
+
+#ifndef __CROS_EC_FPU_H
+#define __CROS_EC_FPU_H
+
+#ifdef CONFIG_FPU
+static inline float sqrtf(float v)
+{
+	float root;
+	asm volatile("fsqrts %0, %1" : "=w"(root) : "w"(v));
+	return root;
+}
+
+static inline float fabsf(float v)
+{
+	float root;
+	asm volatile("fabss %0, %1" : "=w"(root) : "w"(v));
+	return root;
+}
+#endif /* CONFIG_FPU */
+
+#endif /* __CROS_EC_FPU_H */
diff --git a/core/cortex-m/include/math.h b/core/cortex-m/include/math.h
deleted file mode 100644
index 1b336eb2aa..0000000000
--- a/core/cortex-m/include/math.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Math utility functions for ARMv7 */
-
-#ifndef __CROS_EC_MATH_H
-#define __CROS_EC_MATH_H
-
-#ifdef CONFIG_FPU
-static inline float sqrtf(float v)
-{
-	float root;
-	asm volatile(
-		"fsqrts %0, %1"
-		: "=w" (root)
-		: "w" (v)
-	);
-	return root;
-}
-
-static inline float fabsf(float v)
-{
-	float root;
-	asm volatile(
-		"fabss %0, %1"
-		: "=w" (root)
-		: "w" (v)
-	);
-	return root;
-}
-#endif  /* CONFIG_FPU */
-
-#endif  /* __CROS_EC_MATH_H */
diff --git a/core/cortex-m/include/mpu.h b/core/cortex-m/include/mpu.h
index 610728b501..75f95e7000 100644
--- a/core/cortex-m/include/mpu.h
+++ b/core/cortex-m/include/mpu.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,7 +14,7 @@
 /*
  * ARMv7-M SRAM region
  */
-#define CORTEX_M_SRAM_BASE	0x20000000
+#define CORTEX_M_SRAM_BASE 0x20000000
 
 /*
  * Region assignment. 7 as the highest, a higher index has a higher priority.
@@ -26,64 +26,64 @@
  * made mutually exclusive.
  */
 enum mpu_region {
-	REGION_DATA_RAM = 0,		/* For internal data RAM */
-	REGION_DATA_RAM2 = 1,		/* Second region for unaligned size */
-	REGION_CODE_RAM = 2,		/* For internal code RAM */
-	REGION_CODE_RAM2 = 3,		/* Second region for unaligned size */
-	REGION_STORAGE = 4,		/* For mapped internal storage */
-	REGION_STORAGE2 = 5,		/* Second region for unaligned size */
-	REGION_DATA_RAM_TEXT = 6,	/* Exempt region of data RAM */
-	REGION_CHIP_RESERVED = 7,	/* Reserved for use in chip/ */
+	REGION_DATA_RAM = 0, /* For internal data RAM */
+	REGION_DATA_RAM2 = 1, /* Second region for unaligned size */
+	REGION_CODE_RAM = 2, /* For internal code RAM */
+	REGION_CODE_RAM2 = 3, /* Second region for unaligned size */
+	REGION_STORAGE = 4, /* For mapped internal storage */
+	REGION_STORAGE2 = 5, /* Second region for unaligned size */
+	REGION_DATA_RAM_TEXT = 6, /* Exempt region of data RAM */
+	REGION_CHIP_RESERVED = 7, /* Reserved for use in chip/ */
 	/* only for chips with MPU supporting 16 regions */
-	REGION_UNCACHED_RAM = 8,        /* For uncached data RAM */
-	REGION_UNCACHED_RAM2 = 9,       /* Second region for unaligned size */
-	REGION_ROLLBACK = 10,           /* For rollback */
+	REGION_UNCACHED_RAM = 8, /* For uncached data RAM */
+	REGION_UNCACHED_RAM2 = 9, /* Second region for unaligned size */
+	REGION_ROLLBACK = 10, /* For rollback */
 };
 
-#define MPU_TYPE		REG32(0xe000ed90)
-#define MPU_CTRL		REG32(0xe000ed94)
-#define MPU_NUMBER		REG32(0xe000ed98)
-#define MPU_BASE		REG32(0xe000ed9c)
-#define MPU_SIZE		REG16(0xe000eda0)
-#define MPU_ATTR		REG16(0xe000eda2)
+#define MPU_TYPE REG32(0xe000ed90)
+#define MPU_CTRL REG32(0xe000ed94)
+#define MPU_NUMBER REG32(0xe000ed98)
+#define MPU_BASE REG32(0xe000ed9c)
+#define MPU_SIZE REG16(0xe000eda0)
+#define MPU_ATTR REG16(0xe000eda2)
 
 /*
  * See ARM v7-M Architecture Reference Manual
  * Section B3.5.5 MPU Type Register, MPU_TYPE
  */
-#define MPU_TYPE_UNIFIED_MASK	0x00FF0001
-#define MPU_TYPE_REG_COUNT(t)	(((t) >> 8) & 0xFF)
+#define MPU_TYPE_UNIFIED_MASK 0x00FF0001
+#define MPU_TYPE_REG_COUNT(t) (((t) >> 8) & 0xFF)
 
-#define MPU_CTRL_PRIVDEFEN	BIT(2)
-#define MPU_CTRL_HFNMIENA	BIT(1)
-#define MPU_CTRL_ENABLE		BIT(0)
+#define MPU_CTRL_PRIVDEFEN BIT(2)
+#define MPU_CTRL_HFNMIENA BIT(1)
+#define MPU_CTRL_ENABLE BIT(0)
 
 /*
  * Minimum region size is 32 bytes, 5 bits of address space
  */
-#define MPU_SIZE_BITS_MIN	5
+#define MPU_SIZE_BITS_MIN 5
 
 /*
  * XN (execute never) bit. It's bit 12 if accessed by halfword.
  *   0: XN off
  *   1: XN on
  */
-#define MPU_ATTR_XN		BIT(12)
+#define MPU_ATTR_XN BIT(12)
 
 /* AP bit. See table 3-5 of Stellaris LM4F232H5QC datasheet for details */
-#define MPU_ATTR_NO_NO (0 << 8)  /* previleged no access, unprev no access */
-#define MPU_ATTR_RW_NO (1 << 8)  /* previleged ReadWrite, unprev no access */
-#define MPU_ATTR_RW_RO (2 << 8)  /* previleged ReadWrite, unprev Read-only */
-#define MPU_ATTR_RW_RW (3 << 8)  /* previleged ReadWrite, unprev ReadWrite */
-#define MPU_ATTR_RO_NO (5 << 8)  /* previleged Read-only, unprev no access */
+#define MPU_ATTR_NO_NO (0 << 8) /* previleged no access, unprev no access */
+#define MPU_ATTR_RW_NO (1 << 8) /* previleged ReadWrite, unprev no access */
+#define MPU_ATTR_RW_RO (2 << 8) /* previleged ReadWrite, unprev Read-only */
+#define MPU_ATTR_RW_RW (3 << 8) /* previleged ReadWrite, unprev ReadWrite */
+#define MPU_ATTR_RO_NO (5 << 8) /* previleged Read-only, unprev no access */
 
 /* Suggested value for TEX S/C/B bit. See table 3-6 of Stellaris LM4F232H5QC
  * datasheet and table 38 of STM32F10xxx Cortex-M3 programming manual. */
 #ifndef MPU_ATTR_INTERNAL_SRAM
-#define MPU_ATTR_INTERNAL_SRAM  6  /* for Internal SRAM */
+#define MPU_ATTR_INTERNAL_SRAM 6 /* for Internal SRAM */
 #endif
 #ifndef MPU_ATTR_FLASH_MEMORY
-#define MPU_ATTR_FLASH_MEMORY   2  /* for flash memory */
+#define MPU_ATTR_FLASH_MEMORY 2 /* for flash memory */
 #endif
 
 /* Represent RW with at most 2 MPU regions. */
diff --git a/core/cortex-m/include/mpu_private.h b/core/cortex-m/include/mpu_private.h
index e6030114c2..fc7617da66 100644
--- a/core/cortex-m/include/mpu_private.h
+++ b/core/cortex-m/include/mpu_private.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,6 +12,9 @@
 #ifndef __CROS_EC_MPU_PRIVATE_H
 #define __CROS_EC_MPU_PRIVATE_H
 
+#include <stdbool.h>
+#include <stdint.h>
+
 int mpu_num_regions(void);
 bool has_mpu(void);
 bool mpu_is_unified(void);
@@ -21,5 +24,6 @@ int mpu_update_region(uint8_t region, uint32_t addr, uint8_t size_bit,
 int mpu_config_region(uint8_t region, uint32_t addr, uint32_t size,
 		      uint16_t attr, uint8_t enable);
 struct mpu_rw_regions mpu_get_rw_regions(void);
+uint32_t align_down_to_bits(uint32_t addr, uint8_t addr_bits);
 
 #endif /* __CROS_EC_MPU_PRIVATE_H */
diff --git a/core/cortex-m/init.S b/core/cortex-m/init.S
index bc650c4c64..a947b2e9d1 100644
--- a/core/cortex-m/init.S
+++ b/core/cortex-m/init.S
@@ -1,4 +1,4 @@
-/* Copyright 2011 The Chromium OS Authors. All rights reserved.
+/* Copyright 2011 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -98,6 +98,14 @@ data_loop:
 	isb                 /* Reset pipeline */
 #endif /* CONFIG_DEBUG_DISABLE_WRITE_BUFFER */
 
+#if !defined(USE_BUILTIN_STDLIB)
+	/*
+	 * Constructors of global objects.
+	 * https://developer.arm.com/documentation/dui0475/c/the-arm-c-and-c---libraries/c---initialization--construction-and-destruction
+	 */
+	bl __libc_init_array
+#endif
+
 	/* Jump to C code */
 	bl main
 
@@ -117,19 +125,9 @@ _data_end:
 _data_lma_start:
 .long __data_lma_start
 
-/* Mock functions to avoid linker complaints */
-.global __aeabi_unwind_cpp_pr0
-.global __aeabi_unwind_cpp_pr1
-.global __aeabi_unwind_cpp_pr2
-__aeabi_unwind_cpp_pr0:
-__aeabi_unwind_cpp_pr1:
-__aeabi_unwind_cpp_pr2:
-	bx lr
-
 /* Reserve space for system stack */
 .section .bss.system_stack
 stack_start:
 .space CONFIG_STACK_SIZE, 0
 stack_end:
 .global stack_end
-
diff --git a/core/cortex-m/irq_handler.h b/core/cortex-m/irq_handler.h
index ae5d95cd94..b510064652 100644
--- a/core/cortex-m/irq_handler.h
+++ b/core/cortex-m/irq_handler.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,9 +9,10 @@
 #define __CROS_EC_IRQ_HANDLER_H
 
 #ifdef CONFIG_TASK_PROFILING
-#define bl_task_start_irq_handler "bl task_start_irq_handler\n"
+#define TASK_START_IRQ_HANDLER(excep_return) \
+	task_start_irq_handler(excep_return)
 #else
-#define bl_task_start_irq_handler ""
+#define TASK_START_IRQ_HANDLER(excep_return)
 #endif
 
 /* Helper macros to build the IRQ handler and priority struct names */
@@ -22,23 +23,19 @@
  * ensure it is enabled in the interrupt controller with the right priority.
  */
 #define DECLARE_IRQ(irq, routine, priority) DECLARE_IRQ_(irq, routine, priority)
-#define DECLARE_IRQ_(irq, routine, priority)                    \
-	void IRQ_HANDLER(irq)(void) __attribute__((naked));	\
-	typedef struct {					\
-		int fake[irq >= CONFIG_IRQ_COUNT ? -1 : 1];	\
-	} irq_num_check_##irq;					\
-	void __keep routine(void);				\
-	void IRQ_HANDLER(irq)(void)				\
-	{							\
-		asm volatile("mov r0, lr\n"			\
-			     "push {r0, lr}\n"			\
-			     bl_task_start_irq_handler		\
-			     "bl "#routine"\n"			\
-			     "pop {r0, lr}\n"			\
-			     "b task_resched_if_needed\n"	\
-			    );					\
-	}							\
-	const struct irq_priority __keep IRQ_PRIORITY(irq)	\
-	__attribute__((section(".rodata.irqprio")))		\
-			= {irq, priority}
-#endif  /* __CROS_EC_IRQ_HANDLER_H */
+#define DECLARE_IRQ_(irq, routine, priority)                               \
+	void IRQ_HANDLER(irq)(void);                                       \
+	typedef struct {                                                   \
+		int fake[irq >= CONFIG_IRQ_COUNT ? -1 : 1];                \
+	} irq_num_check_##irq;                                             \
+	static void __keep routine(void);                                  \
+	void IRQ_HANDLER(irq)(void)                                        \
+	{                                                                  \
+		void *ret = __builtin_return_address(0);                   \
+		TASK_START_IRQ_HANDLER(ret);                               \
+		routine();                                                 \
+		task_resched_if_needed(ret);                               \
+	}                                                                  \
+	const struct irq_priority __keep IRQ_PRIORITY(irq) __attribute__(( \
+		weak, section(".rodata.irqprio"))) = { irq, priority }
+#endif /* __CROS_EC_IRQ_HANDLER_H */
diff --git a/core/cortex-m/llsr.c b/core/cortex-m/llsr.c
index 0827121e97..933382034b 100644
--- a/core/cortex-m/llsr.c
+++ b/core/cortex-m/llsr.c
@@ -1,20 +1,21 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Enable the use of right shift for uint64_t. */
 
-#include <console.h>
-#include <compile_time_macros.h>
 #include <stdint.h>
 
+#include <compile_time_macros.h>
+#include <console.h>
+
 union words {
 	uint64_t u64;
 	uint32_t w[2];
 };
 
-uint64_t __attribute__((used)) __aeabi_llsr(uint64_t v, uint32_t shift)
+uint64_t __keep __aeabi_llsr(uint64_t v, uint32_t shift)
 {
 	union words val;
 	union words res;
@@ -29,7 +30,7 @@ uint64_t __attribute__((used)) __aeabi_llsr(uint64_t v, uint32_t shift)
 
 #ifdef CONFIG_LLSR_TEST
 
-static int command_llsr(int argc, char **argv)
+static int command_llsr(int argc, const char **argv)
 {
 	/* Volatile to prevent compilier optimization from interfering. */
 	volatile uint64_t start = 0x123456789ABCDEF0ull;
@@ -38,13 +39,11 @@ static int command_llsr(int argc, char **argv)
 	const struct {
 		uint32_t shift_by;
 		uint64_t result;
-	} cases[] = {
-		{0, start},
-		{16, 0x123456789ABCull},
-		{32, 0x12345678u},
-		{48, 0x1234u},
-		{64, 0u}
-	};
+	} cases[] = { { 0, start },
+		      { 16, 0x123456789ABCull },
+		      { 32, 0x12345678u },
+		      { 48, 0x1234u },
+		      { 64, 0u } };
 
 	for (x = 0; x < ARRAY_SIZE(cases); ++x) {
 		if ((start >> cases[x].shift_by) != cases[x].result) {
@@ -58,8 +57,7 @@ static int command_llsr(int argc, char **argv)
 }
 
 DECLARE_CONSOLE_COMMAND(
-		llsrtest, command_llsr,
-		"",
-		"Run tests against the LLSR ABI. Prints SUCCESS or FAILURE.");
+	llsrtest, command_llsr, "",
+	"Run tests against the LLSR ABI. Prints SUCCESS or FAILURE.");
 
-#endif  /* CONFIG_LLSR_TEST */
+#endif /* CONFIG_LLSR_TEST */
diff --git a/core/cortex-m/mpu.c b/core/cortex-m/mpu.c
index d1db27d78e..953cbb7393 100644
--- a/core/cortex-m/mpu.c
+++ b/core/cortex-m/mpu.c
@@ -1,13 +1,14 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* MPU module for Chrome EC */
 
-#include "mpu.h"
+#include "builtin/assert.h"
 #include "console.h"
 #include "cpu.h"
+#include "mpu.h"
 #include "registers.h"
 #include "task.h"
 #include "util.h"
@@ -37,7 +38,6 @@ bool mpu_is_unified(void)
 	return (mpu_get_type() & MPU_TYPE_UNIFIED_MASK) == 0;
 }
 
-
 /**
  * Update a memory region.
  *
@@ -74,7 +74,7 @@ int mpu_update_region(uint8_t region, uint32_t addr, uint8_t size_bit,
 	asm volatile("isb; dsb;");
 
 	MPU_NUMBER = region;
-	MPU_SIZE &= ~1;					/* Disable */
+	MPU_SIZE &= ~1; /* Disable */
 	if (enable) {
 		MPU_BASE = addr;
 		/*
@@ -85,8 +85,8 @@ int mpu_update_region(uint8_t region, uint32_t addr, uint8_t size_bit,
 		 * according to the doc, but they don't ..., do a single 32-bit
 		 * one.
 		 */
-		REG32(&MPU_SIZE) = ((uint32_t)attr << 16)
-				 | (srd << 8) | ((size_bit - 1) << 1) | 1;
+		REG32(&MPU_SIZE) = ((uint32_t)attr << 16) | (srd << 8) |
+				   ((size_bit - 1) << 1) | 1;
 	}
 
 	asm volatile("isb; dsb;");
@@ -94,6 +94,88 @@ int mpu_update_region(uint8_t region, uint32_t addr, uint8_t size_bit,
 	return EC_SUCCESS;
 }
 
+/*
+ * Align address to a maximum of 31 bits
+ */
+uint32_t align_down_to_bits(uint32_t addr, uint8_t addr_bits)
+{
+	if (addr_bits < 32)
+		return addr & ~((1u << addr_bits) - 1);
+	else
+		return addr;
+}
+
+/*
+ * Greedily configure the largest possible part of the given region from the
+ * base address.
+ *
+ * Returns EC_SUCCESS on success and sets *consumed to the number of bytes
+ * mapped from the base address. In case of error, the value of *consumed is
+ * unpredictable.
+ *
+ * For instance, if addr is 0x10070000 and size is 0x30000 then memory in the
+ * range 0x10070000-0x10080000 will be configured and *consumed will be set to
+ * 0x10000.
+ */
+static int mpu_config_region_greedy(uint8_t region, uint32_t addr,
+				    uint32_t size, uint16_t attr,
+				    uint8_t enable, uint32_t *consumed)
+{
+	/*
+	 * Compute candidate alignment to be used for the MPU region.
+	 *
+	 * This is the minimum of the base address and size alignment, since
+	 * regions must be naturally aligned to their size.
+	 */
+	uint8_t natural_alignment = MIN(addr == 0 ? 32 : alignment_log2(addr),
+					alignment_log2(size));
+	uint8_t subregion_disable = 0;
+
+	if (natural_alignment >= 5) {
+		int sr_idx;
+		uint32_t subregion_base, subregion_size;
+		/*
+		 * For MPU regions larger than 256 bytes we can use subregions,
+		 * (which are a minimum of 32 bytes in size) making the actual
+		 * MPU region 8x larger. Depending on the address alignment this
+		 * can allow us to cover a larger area (and never a smaller
+		 * one).
+		 */
+		natural_alignment += 3;
+		/* Region size cannot exceed 4GB. */
+		if (natural_alignment > 32)
+			natural_alignment = 32;
+
+		/*
+		 * Generate the subregion mask by walking through each,
+		 * disabling if it is not completely contained in the requested
+		 * range.
+		 */
+		subregion_base = align_down_to_bits(addr, natural_alignment);
+		subregion_size = 1 << (natural_alignment - 3);
+		*consumed = 0;
+		for (sr_idx = 0; sr_idx < 8; sr_idx++) {
+			if (subregion_base < addr ||
+			    (subregion_base + subregion_size) > (addr + size))
+				/* lsb of subregion mask is lowest address */
+				subregion_disable |= 1 << sr_idx;
+			else
+				/* not disabled means consumed */
+				*consumed += subregion_size;
+
+			subregion_base += subregion_size;
+		}
+	} else {
+		/* Not using subregions; all enabled */
+		*consumed = 1 << natural_alignment;
+	}
+
+	return mpu_update_region(region,
+				 align_down_to_bits(addr, natural_alignment),
+				 natural_alignment, attr, enable,
+				 subregion_disable);
+}
+
 /**
  * Configure a region
  *
@@ -103,76 +185,42 @@ int mpu_update_region(uint8_t region, uint32_t addr, uint8_t size_bit,
  * attr: Attribute bits. Current value will be overwritten if enable is set.
  * enable: Enables the region if non zero. Otherwise, disables the region.
  *
- * Returns EC_SUCCESS on success or -EC_ERROR_INVAL if a parameter is invalid.
+ * Returns EC_SUCCESS on success, -EC_ERROR_OVERFLOW if it is not possible to
+ * fully configure the given region, or -EC_ERROR_INVAL if a parameter is
+ * invalid (such as the address or size having unsupported alignment).
  */
 int mpu_config_region(uint8_t region, uint32_t addr, uint32_t size,
 		      uint16_t attr, uint8_t enable)
 {
 	int rv;
-	int size_bit = 0;
-	uint8_t blocks, srd1, srd2;
+	uint32_t consumed;
 
-	if (!size)
+	/* Zero size doesn't require configuration */
+	if (size == 0)
 		return EC_SUCCESS;
 
-	/* Bit position of first '1' in size */
-	size_bit = 31 - __builtin_clz(size);
-	/* Min. region size is 32 bytes */
-	if (size_bit < 5)
-		return -EC_ERROR_INVAL;
-
-	/* If size is a power of 2 then represent it with a single MPU region */
-	if (POWER_OF_TWO(size))
-		return mpu_update_region(region, addr, size_bit, attr, enable,
-					 0);
-
-	/* Sub-regions are not supported for region <= 128 bytes */
-	if (size_bit < 7)
-		return -EC_ERROR_INVAL;
-	/* Verify we can represent range with <= 2 regions */
-	if (size & ~(0x3f << (size_bit - 5)))
-		return -EC_ERROR_INVAL;
-
-	/*
-	 * Round up size of first region to power of 2.
-	 * Calculate the number of fully occupied blocks (block size =
-	 * region size / 8) in the first region.
-	 */
-	blocks = size >> (size_bit - 2);
-
-	/* Represent occupied blocks of two regions with srd mask. */
-	srd1 = BIT(blocks) - 1;
-	srd2 = (1 << ((size >> (size_bit - 5)) & 0x7)) - 1;
-
-	/*
-	 * Second region not supported for DATA_RAM_TEXT, also verify size of
-	 * second region is sufficient to support sub-regions.
-	 */
-	if (srd2 && (region == REGION_DATA_RAM_TEXT || size_bit < 10))
-		return -EC_ERROR_INVAL;
-
-	/* Write first region. */
-	rv = mpu_update_region(region, addr, size_bit + 1, attr, enable, ~srd1);
+	rv = mpu_config_region_greedy(region, addr, size, attr, enable,
+				      &consumed);
 	if (rv != EC_SUCCESS)
 		return rv;
+	ASSERT(consumed <= size);
+	addr += consumed;
+	size -= consumed;
+
+	/* Regions other than DATA_RAM_TEXT may use two MPU regions */
+	if (size > 0 && region != REGION_DATA_RAM_TEXT) {
+		rv = mpu_config_region_greedy(region + 1, addr, size, attr,
+					      enable, &consumed);
+		if (rv != EC_SUCCESS)
+			return rv;
+		ASSERT(consumed <= size);
+		addr += consumed;
+		size -= consumed;
+	}
 
-	/*
-	 * Second protection region (if necessary) begins at the first block
-	 * we marked unoccupied in the first region.
-	 * Size of the second region is the block size of first region.
-	 */
-	addr += (1 << (size_bit - 2)) * blocks;
-
-	/*
-	 * Now represent occupied blocks in the second region. It's possible
-	 * that the first region completely represented the occupied area, if
-	 * so then no second protection region is required.
-	 */
-	if (srd2)
-		rv = mpu_update_region(region + 1, addr, size_bit - 2, attr,
-				       enable, ~srd2);
-
-	return rv;
+	if (size > 0)
+		return EC_ERROR_OVERFLOW;
+	return EC_SUCCESS;
 }
 
 /**
@@ -186,8 +234,8 @@ int mpu_config_region(uint8_t region, uint32_t addr, uint32_t size,
 static int mpu_unlock_region(uint8_t region, uint32_t addr, uint32_t size,
 			     uint8_t texscb)
 {
-	return mpu_config_region(region, addr, size,
-				 MPU_ATTR_RW_RW | texscb, 1);
+	return mpu_config_region(region, addr, size, MPU_ATTR_RW_RW | texscb,
+				 1);
 }
 
 void mpu_enable(void)
@@ -210,13 +258,9 @@ int mpu_protect_data_ram(void)
 	int ret;
 
 	/* Prevent code execution from data RAM */
-	ret = mpu_config_region(REGION_DATA_RAM,
-				CONFIG_RAM_BASE,
-				CONFIG_DATA_RAM_SIZE,
-				MPU_ATTR_XN |
-				MPU_ATTR_RW_RW |
-				MPU_ATTR_INTERNAL_SRAM,
-				1);
+	ret = mpu_config_region(
+		REGION_DATA_RAM, CONFIG_RAM_BASE, CONFIG_DATA_RAM_SIZE,
+		MPU_ATTR_XN | MPU_ATTR_RW_RW | MPU_ATTR_INTERNAL_SRAM, 1);
 	if (ret != EC_SUCCESS)
 		return ret;
 
@@ -234,18 +278,16 @@ int mpu_protect_code_ram(void)
 	return mpu_config_region(REGION_STORAGE,
 				 CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RO_MEM_OFF,
 				 CONFIG_CODE_RAM_SIZE,
-				 MPU_ATTR_RO_NO | MPU_ATTR_INTERNAL_SRAM,
-				 1);
+				 MPU_ATTR_RO_NO | MPU_ATTR_INTERNAL_SRAM, 1);
 }
 #else
 int mpu_lock_ro_flash(void)
 {
 	/* Prevent execution from internal mapped RO flash */
-	return mpu_config_region(REGION_STORAGE,
-				 CONFIG_MAPPED_STORAGE_BASE + CONFIG_RO_MEM_OFF,
-				 CONFIG_RO_SIZE,
-				 MPU_ATTR_XN | MPU_ATTR_RW_RW |
-				 MPU_ATTR_FLASH_MEMORY, 1);
+	return mpu_config_region(
+		REGION_STORAGE, CONFIG_MAPPED_STORAGE_BASE + CONFIG_RO_MEM_OFF,
+		CONFIG_RO_SIZE,
+		MPU_ATTR_XN | MPU_ATTR_RW_RW | MPU_ATTR_FLASH_MEMORY, 1);
 }
 
 /* Represent RW with at most 2 MPU regions. */
@@ -261,8 +303,7 @@ struct mpu_rw_regions mpu_get_rw_regions(void)
 	 * the region because on the Cortex-M3, Cortex-M4 and Cortex-M7, the
 	 * address used for an MPU region must be aligned to the size.
 	 */
-	aligned_size_bit =
-		__fls(regions.addr[0] & -regions.addr[0]);
+	aligned_size_bit = __fls(regions.addr[0] & -regions.addr[0]);
 	regions.size[0] = MIN(BIT(aligned_size_bit), CONFIG_RW_SIZE);
 	regions.addr[1] = regions.addr[0] + regions.size[0];
 	regions.size[1] = CONFIG_RW_SIZE - regions.size[0];
@@ -349,10 +390,10 @@ int mpu_lock_rollback(int lock)
 
 #ifdef CONFIG_CHIP_UNCACHED_REGION
 /* Store temporarily the regions ranges to use them for the MPU configuration */
-#define REGION(_name, _flag, _start, _size) \
-	static const uint32_t CONCAT2(_region_start_, _name) \
+#define REGION(_name, _flag, _start, _size)                           \
+	static const uint32_t CONCAT2(_region_start_, _name)          \
 		__attribute__((unused, section(".unused"))) = _start; \
-	static const uint32_t CONCAT2(_region_size_, _name) \
+	static const uint32_t CONCAT2(_region_size_, _name)           \
 		__attribute__((unused, section(".unused"))) = _size;
 #include "memory_regions.inc"
 #undef REGION
@@ -387,7 +428,7 @@ int mpu_pre_init(void)
 		 * to the region size.
 		 */
 		rv = mpu_update_region(i, CORTEX_M_SRAM_BASE, MPU_SIZE_BITS_MIN,
-			0, 0, 0);
+				       0, 0, 0);
 		if (rv != EC_SUCCESS)
 			return rv;
 	}
diff --git a/core/cortex-m/panic-internal.h b/core/cortex-m/panic-internal.h
index 1a58afa8a2..6fa6440006 100644
--- a/core/cortex-m/panic-internal.h
+++ b/core/cortex-m/panic-internal.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,4 +8,4 @@
 
 void exception_panic(void) __attribute__((naked));
 
-#endif  /* __CROS_EC_PANIC_INTERNAL_H */
+#endif /* __CROS_EC_PANIC_INTERNAL_H */
diff --git a/core/cortex-m/panic.c b/core/cortex-m/panic.c
index 8fabaf4b21..e8d21a6866 100644
--- a/core/cortex-m/panic.c
+++ b/core/cortex-m/panic.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,26 +7,28 @@
 #include "console.h"
 #include "cpu.h"
 #include "host_command.h"
-#include "panic.h"
 #include "panic-internal.h"
+#include "panic.h"
 #include "printf.h"
 #include "system.h"
+#include "system_safe_mode.h"
 #include "task.h"
 #include "timer.h"
 #include "uart.h"
 #include "util.h"
 #include "watchdog.h"
 
+#define BASE_EXCEPTION_FRAME_SIZE_BYTES (8 * sizeof(uint32_t))
+#define FPU_EXCEPTION_FRAME_SIZE_BYTES (18 * sizeof(uint32_t))
+
 /* Whether bus fault is ignored */
 static int bus_fault_ignored;
 
-
 /* Panic data goes at the end of RAM. */
-static struct panic_data * const pdata_ptr = PANIC_DATA_PTR;
+static struct panic_data *const pdata_ptr = PANIC_DATA_PTR;
 
 /* Preceded by stack, rounded down to nearest 64-bit-aligned boundary */
-static const uint32_t pstack_addr = (CONFIG_RAM_BASE + CONFIG_RAM_SIZE
-				     - sizeof(struct panic_data)) & ~7;
+static const uint32_t pstack_addr = ((uint32_t)pdata_ptr) & ~7;
 
 /**
  * Print the name and value of a register
@@ -76,9 +78,56 @@ static int32_t is_frame_in_handler_stack(const uint32_t exc_return)
 	return (exc_return & 0xf) == 1 || (exc_return & 0xf) == 9;
 }
 
+/*
+ * Returns the size of the exception frame.
+ *
+ * See B1.5.7 "Stack alignment on exception entry" of ARM DDI 0403D for details.
+ * In short, the exception frame size can be either 0x20, 0x24, 0x68, or 0x6c
+ * depending on FPU context and padding for 8-byte alignment.
+ */
+static uint32_t get_exception_frame_size(const struct panic_data *pdata)
+{
+	uint32_t frame_size = 0;
+
+	/* base exception frame */
+	frame_size += BASE_EXCEPTION_FRAME_SIZE_BYTES;
+
+	/* CPU uses xPSR[9] to indicate whether it padded the stack for
+	 * alignment or not.
+	 */
+	if (pdata->cm.frame[CORTEX_PANIC_FRAME_REGISTER_PSR] & BIT(9))
+		frame_size += sizeof(uint32_t);
+
+#ifdef CONFIG_FPU
+	/* CPU uses EXC_RETURN[4] to indicate whether it stored extended
+	 * frame for FPU or not.
+	 */
+	if (!(pdata->cm.regs[CORTEX_PANIC_REGISTER_LR] & BIT(4)))
+		frame_size += FPU_EXCEPTION_FRAME_SIZE_BYTES;
+#endif
+
+	return frame_size;
+}
+
+/*
+ * Returns the position of the process stack before the exception frame.
+ * It computes the size of the exception frame and adds it to psp.
+ * If the exception happened in the exception context, it returns psp as is.
+ */
+uint32_t get_panic_stack_pointer(const struct panic_data *pdata)
+{
+	uint32_t psp = pdata->cm.regs[CORTEX_PANIC_REGISTER_PSP];
+
+	if (!is_frame_in_handler_stack(
+		    pdata->cm.regs[CORTEX_PANIC_REGISTER_LR]))
+		psp += get_exception_frame_size(pdata);
+
+	return psp;
+}
+
 #ifdef CONFIG_DEBUG_EXCEPTIONS
 /* Names for each of the bits in the cfs register, starting at bit 0 */
-static const char * const cfsr_name[32] = {
+static const char *const cfsr_name[32] = {
 	/* MMFSR */
 	[0] = "Instruction access violation",
 	[1] = "Data access violation",
@@ -102,11 +151,9 @@ static const char * const cfsr_name[32] = {
 };
 
 /* Names for the first 5 bits in the DFSR */
-static const char * const dfsr_name[] = {
-	"Halt request",
-	"Breakpoint",
-	"Data watchpoint/trace",
-	"Vector catch",
+static const char *const dfsr_name[] = {
+	"Halt request",		  "Breakpoint",
+	"Data watchpoint/trace",  "Vector catch",
 	"External debug request",
 };
 
@@ -167,50 +214,6 @@ static void show_fault(uint32_t cfsr, uint32_t hfsr, uint32_t dfsr)
 	}
 }
 
-/*
- * Returns the size of the exception frame.
- *
- * See B1.5.7 "Stack alignment on exception entry" of ARM DDI 0403D for details.
- * In short, the exception frame size can be either 0x20, 0x24, 0x68, or 0x6c
- * depending on FPU context and padding for 8-byte alignment.
- */
-static uint32_t get_exception_frame_size(const struct panic_data *pdata)
-{
-	uint32_t frame_size = 0;
-
-	/* base exception frame */
-	frame_size += 8 * sizeof(uint32_t);
-
-	/* CPU uses xPSR[9] to indicate whether it padded the stack for
-	 * alignment or not. */
-	if (pdata->cm.frame[7] & BIT(9))
-		frame_size += sizeof(uint32_t);
-
-#ifdef CONFIG_FPU
-	/* CPU uses EXC_RETURN[4] to indicate whether it stored extended
-	 * frame for FPU or not. */
-	if (!(pdata->cm.regs[11] & BIT(4)))
-		frame_size += 18 * sizeof(uint32_t);
-#endif
-
-	return frame_size;
-}
-
-/*
- * Returns the position of the process stack before the exception frame.
- * It computes the size of the exception frame and adds it to psp.
- * If the exception happened in the exception context, it returns psp as is.
- */
-static uint32_t get_process_stack_position(const struct panic_data *pdata)
-{
-	uint32_t psp = pdata->cm.regs[0];
-
-	if (!is_frame_in_handler_stack(pdata->cm.regs[11]))
-		psp += get_exception_frame_size(pdata);
-
-	return psp;
-}
-
 /*
  * Show extra information that might be useful to understand a panic()
  *
@@ -237,7 +240,7 @@ static void panic_show_process_stack(const struct panic_data *pdata)
 {
 	panic_printf("\n=========== Process Stack Contents ===========");
 	if (pdata->flags & PANIC_DATA_FLAG_FRAME_VALID) {
-		uint32_t psp = get_process_stack_position(pdata);
+		uint32_t psp = get_panic_stack_pointer(pdata);
 		int i;
 		for (i = 0; i < 16; i++) {
 			if (psp + sizeof(uint32_t) >
@@ -261,8 +264,8 @@ void panic_data_print(const struct panic_data *pdata)
 {
 	const uint32_t *lregs = pdata->cm.regs;
 	const uint32_t *sregs = NULL;
-	const int32_t in_handler =
-		is_frame_in_handler_stack(pdata->cm.regs[11]);
+	const int32_t in_handler = is_frame_in_handler_stack(
+		pdata->cm.regs[CORTEX_PANIC_REGISTER_LR]);
 	int i;
 
 	if (pdata->flags & PANIC_DATA_FLAG_FRAME_VALID)
@@ -270,23 +273,36 @@ void panic_data_print(const struct panic_data *pdata)
 
 	panic_printf("\n=== %s EXCEPTION: %02x ====== xPSR: %08x ===\n",
 		     in_handler ? "HANDLER" : "PROCESS",
-		     lregs[1] & 0xff, sregs ? sregs[7] : -1);
+		     lregs[CORTEX_PANIC_REGISTER_IPSR] & 0xff,
+		     sregs ? sregs[CORTEX_PANIC_FRAME_REGISTER_PSR] : -1);
 	for (i = 0; i < 4; i++)
 		print_reg(i, sregs, i);
 	for (i = 4; i < 10; i++)
 		print_reg(i, lregs, i - 1);
-	print_reg(10, lregs, 9);
-	print_reg(11, lregs, 10);
-	print_reg(12, sregs, 4);
-	print_reg(13, lregs, in_handler ? 2 : 0);
-	print_reg(14, sregs, 5);
-	print_reg(15, sregs, 6);
+	print_reg(10, lregs, CORTEX_PANIC_REGISTER_R10);
+	print_reg(11, lregs, CORTEX_PANIC_REGISTER_R11);
+	print_reg(12, sregs, CORTEX_PANIC_FRAME_REGISTER_R12);
+	print_reg(13, lregs,
+		  in_handler ? CORTEX_PANIC_REGISTER_MSP :
+			       CORTEX_PANIC_REGISTER_PSP);
+	print_reg(14, sregs, CORTEX_PANIC_FRAME_REGISTER_LR);
+	print_reg(15, sregs, CORTEX_PANIC_FRAME_REGISTER_PC);
 
 #ifdef CONFIG_DEBUG_EXCEPTIONS
 	panic_show_extra(pdata);
 #endif
 }
 
+/* This is just a placeholder function for returning from exception.
+ * It's not expected to actually be executed.
+ */
+static void exception_return_placeholder(void)
+{
+	panic_printf("Unexpected return from exception\n");
+	panic_reboot();
+	__builtin_unreachable();
+}
+
 void __keep report_panic(void)
 {
 	/*
@@ -304,16 +320,29 @@ void __keep report_panic(void)
 	pdata->reserved = 0;
 
 	/* Choose the right sp (psp or msp) based on EXC_RETURN value */
-	sp = is_frame_in_handler_stack(pdata->cm.regs[11])
-		? pdata->cm.regs[2] : pdata->cm.regs[0];
+	sp = is_frame_in_handler_stack(
+		     pdata->cm.regs[CORTEX_PANIC_REGISTER_LR]) ?
+		     pdata->cm.regs[CORTEX_PANIC_REGISTER_MSP] :
+		     pdata->cm.regs[CORTEX_PANIC_REGISTER_PSP];
 	/* If stack is valid, copy exception frame to pdata */
-	if ((sp & 3) == 0 &&
-	    sp >= CONFIG_RAM_BASE &&
-	    sp <= CONFIG_RAM_BASE + CONFIG_RAM_SIZE - 8 * sizeof(uint32_t)) {
+	if ((sp & 3) == 0 && sp >= CONFIG_RAM_BASE &&
+	    sp <= CONFIG_RAM_BASE + CONFIG_RAM_SIZE -
+			    BASE_EXCEPTION_FRAME_SIZE_BYTES) {
 		const uint32_t *sregs = (const uint32_t *)sp;
 		int i;
-		for (i = 0; i < 8; i++)
+
+		/* Skip r0-r3 and r12 registers if necessary */
+		for (i = CORTEX_PANIC_FRAME_REGISTER_R0;
+		     i <= CORTEX_PANIC_FRAME_REGISTER_R12; i++)
+			if (IS_ENABLED(CONFIG_PANIC_STRIP_GPR))
+				pdata->cm.frame[i] = 0;
+			else
+				pdata->cm.frame[i] = sregs[i];
+
+		for (i = CORTEX_PANIC_FRAME_REGISTER_LR;
+		     i < NUM_CORTEX_PANIC_FRAME_REGISTERS; i++)
 			pdata->cm.frame[i] = sregs[i];
+
 		pdata->flags |= PANIC_DATA_FLAG_FRAME_VALID;
 	}
 
@@ -336,6 +365,36 @@ void __keep report_panic(void)
 	 * exception happened in a handler's context.
 	 */
 #endif
+
+	/* Make sure that all changes are saved into RAM */
+	if (IS_ENABLED(CONFIG_ARMV7M_CACHE))
+		cpu_clean_invalidate_dcache();
+
+	/* Start safe mode if possible */
+	if (IS_ENABLED(CONFIG_SYSTEM_SAFE_MODE)) {
+		/* TODO: check for nested exceptions */
+		if (start_system_safe_mode() == EC_SUCCESS) {
+			pdata->flags |= PANIC_DATA_FLAG_SAFE_MODE_STARTED;
+			/* If not in an interrupt context (e.g. software_panic),
+			 * the next highest priority task will immediately
+			 * execute when the current task is disabled on the
+			 * following line.
+			 */
+			task_disable_task(task_get_current());
+			/* Return from exception on process stack.
+			 * We should not actually land in
+			 * exception_return_placeholder function. Instead the
+			 * scheduler should interrupt and schedule
+			 * a different task since the current task has
+			 * been disabled.
+			 */
+			cpu_return_from_exception_psp(
+				exception_return_placeholder);
+			__builtin_unreachable();
+		}
+		pdata->flags |= PANIC_DATA_FLAG_SAFE_MODE_FAIL_PRECONDITIONS;
+	}
+
 	panic_reboot();
 }
 
@@ -348,35 +407,72 @@ void exception_panic(void)
 {
 	/* Save registers and branch directly to panic handler */
 	asm volatile(
-		"mov r0, %[pregs]\n"
 		"mrs r1, psp\n"
 		"mrs r2, ipsr\n"
 		"mov r3, sp\n"
-		"stmia r0, {r1-r11, lr}\n"
+#ifdef CONFIG_PANIC_STRIP_GPR
+		/*
+		 * Check if we are in exception. This is similar to
+		 * in_interrupt_context(). Exception bits are 9 LSB, so
+		 * we can perform left shift for 23 bits and check if result
+		 * is 0 (lsls instruction is setting appropriate flags).
+		 */
+		"lsls r6, r2, #23\n"
+		/*
+		 * If this is software panic (shift result == 0) then register
+		 * r4 and r5 contain additional info about panic.
+		 * Clear r6-r11 always and r4, r5 only if this is exception
+		 * panic. To clear r4 and r5, 'movne' conditional instruction
+		 * is used. It works only when flags contain information that
+		 * result was != 0. Itt is pseudo instruction which is used
+		 * to make sure we are using correct conditional instructions.
+		 */
+		"itt ne\n"
+		"movne r4, #0\n"
+		"movne r5, #0\n"
+		"mov r6, #0\n"
+		"mov r7, #0\n"
+		"mov r8, #0\n"
+		"mov r9, #0\n"
+		"mov r10, #0\n"
+		"mov r11, #0\n"
+#endif
+		"stmia %[pregs], {r1-r11, lr}\n"
 		"mov sp, %[pstack]\n"
-		"bl report_panic\n" : :
-			[pregs] "r" (pdata_ptr->cm.regs),
-			[pstack] "r" (pstack_addr) :
-			/* Constraints protecting these from being clobbered.
-			 * Gcc should be using r0 & r12 for pregs and pstack. */
-			"r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9",
-			"r10", "r11", "cc", "memory"
-		);
+		"bl report_panic\n"
+		:
+		: [pregs] "r"(pdata_ptr->cm.regs), [pstack] "r"(pstack_addr)
+		:
+		/* Constraints protecting these from being clobbered.
+		 * Gcc should be using r0 & r12 for pregs and pstack. */
+		"r1", "r2", "r3", "r4", "r5", "r6",
+	/* clang warns that we're clobbering a reserved register:
+	 * inline asm clobber list contains reserved registers: R7
+	 * [-Werror,-Winline-asm]. The intent of the clobber list is
+	 * to force pregs and pstack to be in R0 and R12, which
+	 * still holds.
+	 */
+#ifndef __clang__
+		"r7",
+#endif
+		"r8", "r9", "r10", "r11", "cc", "memory");
 }
 
-#ifdef CONFIG_SOFTWARE_PANIC
 void software_panic(uint32_t reason, uint32_t info)
 {
-	__asm__("mov " STRINGIFY(SOFTWARE_PANIC_INFO_REG) ", %0\n"
-		"mov " STRINGIFY(SOFTWARE_PANIC_REASON_REG) ", %1\n"
-		"bl exception_panic\n"
-		: : "r"(info), "r"(reason));
+	__asm__("mov " STRINGIFY(
+			SOFTWARE_PANIC_INFO_REG) ", %0\n"
+						 "mov " STRINGIFY(
+							 SOFTWARE_PANIC_REASON_REG) ", %1\n"
+										    "bl exception_panic\n"
+		:
+		: "r"(info), "r"(reason));
 	__builtin_unreachable();
 }
 
 void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
 {
-	struct panic_data * const pdata = get_panic_data_write();
+	struct panic_data *const pdata = get_panic_data_write();
 	uint32_t *lregs;
 
 	lregs = pdata->cm.regs;
@@ -389,26 +485,25 @@ void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
 	pdata->arch = PANIC_ARCH_CORTEX_M;
 
 	/* Log panic cause */
-	lregs[1] = exception;
-	lregs[3] = reason;
-	lregs[4] = info;
+	lregs[CORTEX_PANIC_REGISTER_IPSR] = exception;
+	lregs[CORTEX_PANIC_REGISTER_R4] = reason;
+	lregs[CORTEX_PANIC_REGISTER_R5] = info;
 }
 
 void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception)
 {
-	struct panic_data * const pdata = panic_get_data();
+	struct panic_data *const pdata = panic_get_data();
 	uint32_t *lregs;
 
 	if (pdata && pdata->struct_version == 2) {
 		lregs = pdata->cm.regs;
-		*exception = lregs[1];
-		*reason = lregs[3];
-		*info = lregs[4];
+		*exception = lregs[CORTEX_PANIC_REGISTER_IPSR];
+		*reason = lregs[CORTEX_PANIC_REGISTER_R4];
+		*info = lregs[CORTEX_PANIC_REGISTER_R5];
 	} else {
 		*exception = *reason = *info = 0;
 	}
 }
-#endif
 
 void bus_fault_handler(void)
 {
@@ -418,6 +513,17 @@ void bus_fault_handler(void)
 
 void ignore_bus_fault(int ignored)
 {
+	/*
+	 * According to
+	 * https://developer.arm.com/documentation/ddi0403/d/System-Level-Architecture/System-Level-Programmers--Model/Overview-of-system-level-terminology-and-operation/Exceptions?lang=en,
+	 * the Imprecise BusFault is an asynchronous fault in ARMv7-M.
+	 *
+	 * Before re-enabling the bus fault, we use a barrier to make sure that
+	 * the fault has been processed.
+	 */
+	if (ignored == 0)
+		asm volatile("dsb; isb");
+
 	/*
 	 * Flash code might call this before cpu_init(),
 	 * ensure that the bus faults really go through our handler.
diff --git a/core/cortex-m/switch.S b/core/cortex-m/switch.S
index f56c5e4c74..512b48036f 100644
--- a/core/cortex-m/switch.S
+++ b/core/cortex-m/switch.S
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -98,4 +98,3 @@ __task_start:
   /* we should never return here */
   mov r0, #1             @ set to EC_ERROR_UNKNOWN
   bx lr
-
diff --git a/core/cortex-m/task.c b/core/cortex-m/task.c
index 510d18fca0..f42b4f9dc0 100644
--- a/core/cortex-m/task.c
+++ b/core/cortex-m/task.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,9 +6,11 @@
 /* Task scheduling / events module for Chrome EC operating system */
 
 #include "atomic.h"
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
 #include "cpu.h"
+#include "debug.h"
 #include "link_defs.h"
 #include "panic.h"
 #include "task.h"
@@ -21,10 +23,10 @@ typedef union {
 		 * Note that sp must be the first element in the task struct
 		 * for __switchto() to work.
 		 */
-		uint32_t sp;       /* Saved stack pointer for context switch */
-		uint32_t events;   /* Bitmaps of received events */
-		uint64_t runtime;  /* Time spent in task */
-		uint32_t *stack;   /* Start of stack */
+		uint32_t sp; /* Saved stack pointer for context switch */
+		atomic_t events; /* Bitmaps of received events */
+		uint64_t runtime; /* Time spent in task */
+		uint32_t *stack; /* Start of stack */
 	};
 } task_;
 
@@ -40,12 +42,10 @@ CONFIG_CTS_TASK_LIST
 #undef TASK
 
 /* Task names for easier debugging */
-#define TASK(n, r, d, s)  #n,
-static const char * const task_names[] = {
+#define TASK(n, r, d, s) #n,
+static const char *const task_names[] = {
 	"<< idle >>",
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
-	CONFIG_CTS_TASK_LIST
+	CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST CONFIG_CTS_TASK_LIST
 };
 #undef TASK
 
@@ -55,12 +55,12 @@ static uint64_t task_start_time; /* Time task scheduling started */
  * We only keep 32-bit values for exception start/end time, to avoid
  * accounting errors when we service interrupt when the timer wraps around.
  */
-static uint32_t exc_start_time;  /* Time of task->exception transition */
-static uint32_t exc_end_time;    /* Time of exception->task transition */
-static uint64_t exc_total_time;  /* Total time in exceptions */
-static uint32_t svc_calls;       /* Number of service calls */
-static uint32_t task_switches;   /* Number of times active task changed */
-static uint32_t irq_dist[CONFIG_IRQ_COUNT];  /* Distribution of IRQ calls */
+static uint32_t exc_start_time; /* Time of task->exception transition */
+static uint32_t exc_end_time; /* Time of exception->task transition */
+static uint64_t exc_total_time; /* Total time in exceptions */
+static uint32_t svc_calls; /* Number of service calls */
+static uint32_t task_switches; /* Number of times active task changed */
+static uint32_t irq_dist[CONFIG_IRQ_COUNT]; /* Distribution of IRQ calls */
 #endif
 
 extern void __switchto(task_ *from, task_ *to);
@@ -79,7 +79,7 @@ void __idle(void)
 		 * CSAE bit is set. Please notice this symptom only
 		 * occurs at npcx5.
 		 */
-#if defined(CHIP_FAMILY_NPCX5) && defined(CONFIG_HOSTCMD_ESPI)
+#if defined(CHIP_FAMILY_NPCX5) && defined(CONFIG_HOST_INTERFACE_ESPI)
 		/* Enable Host access wakeup */
 		SET_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6);
 #endif
@@ -91,21 +91,20 @@ void __idle(void)
 		 * shortly therefore, resumes execution on exiting idle mode.
 		 * Workaround: Replace the idle function with the followings
 		 */
-		asm (
-			"cpsid i\n"             /* Disable interrupt */
-			"push {r0-r5}\n"        /* Save needed registers */
-			"wfi\n"                 /* Wait for int to enter idle */
-			"ldm %0, {r0-r5}\n"     /* Add a delay after WFI */
-			"pop {r0-r5}\n" /* Restore regs before enabling ints */
-			"isb\n"                 /* Flush the cpu pipeline */
-			"cpsie i\n" :: "r" (0x100A8000)  /* Enable interrupts */
+		asm("cpsid i\n" /* Disable interrupt */
+		    "push {r0-r5}\n" /* Save needed registers */
+		    "wfi\n" /* Wait for int to enter idle */
+		    "ldm %0, {r0-r5}\n" /* Add a delay after WFI */
+		    "pop {r0-r5}\n" /* Restore regs before enabling ints */
+		    "isb\n" /* Flush the cpu pipeline */
+		    "cpsie i\n" ::"r"(0x100A8000) /* Enable interrupts */
 		);
 #else
 		/*
 		 * Wait for the next irq event.  This stops the CPU clock
 		 * (sleep / deep sleep, depending on chip config).
 		 */
-		asm("wfi");
+		cpu_enter_suspend_mode();
 #endif
 	}
 }
@@ -121,20 +120,19 @@ static void task_exit_trap(void)
 }
 
 /* Startup parameters for all tasks. */
-#define TASK(n, r, d, s)  {	\
-	.r0 = (uint32_t)d,	\
-	.pc = (uint32_t)r,	\
-	.stack_size = s,	\
-},
+#define TASK(n, r, d, s)           \
+	{                          \
+		.r0 = (uint32_t)d, \
+		.pc = (uint32_t)r, \
+		.stack_size = s,   \
+	},
 static const struct {
 	uint32_t r0;
 	uint32_t pc;
 	uint16_t stack_size;
 } tasks_init[] = {
 	TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
-	CONFIG_CTS_TASK_LIST
+		CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST CONFIG_CTS_TASK_LIST
 };
 #undef TASK
 
@@ -142,17 +140,16 @@ static const struct {
 static task_ tasks[TASK_ID_COUNT];
 
 /* Reset constants and state for all tasks */
-#define TASK_RESET_SUPPORTED		BIT(31)
-#define TASK_RESET_LOCK			BIT(30)
-#define TASK_RESET_STATE_MASK		(TASK_RESET_SUPPORTED | TASK_RESET_LOCK)
-#define TASK_RESET_WAITERS_MASK		~TASK_RESET_STATE_MASK
-#define TASK_RESET_UNSUPPORTED		0
-#define TASK_RESET_STATE_LOCKED		(TASK_RESET_SUPPORTED | TASK_RESET_LOCK)
-#define TASK_RESET_STATE_UNLOCKED	TASK_RESET_SUPPORTED
+#define TASK_RESET_SUPPORTED BIT(31)
+#define TASK_RESET_LOCK BIT(30)
+#define TASK_RESET_STATE_MASK (TASK_RESET_SUPPORTED | TASK_RESET_LOCK)
+#define TASK_RESET_WAITERS_MASK ~TASK_RESET_STATE_MASK
+#define TASK_RESET_UNSUPPORTED 0
+#define TASK_RESET_STATE_LOCKED (TASK_RESET_SUPPORTED | TASK_RESET_LOCK)
+#define TASK_RESET_STATE_UNLOCKED TASK_RESET_SUPPORTED
 
 #ifdef CONFIG_TASK_RESET_LIST
-#define ENABLE_RESET(n) \
-	[TASK_ID_##n] = TASK_RESET_SUPPORTED,
+#define ENABLE_RESET(n) [TASK_ID_##n] = TASK_RESET_SUPPORTED,
 static uint32_t task_reset_state[TASK_ID_COUNT] = {
 #ifdef CONFIG_TASK_RESET_LIST
 	CONFIG_TASK_RESET_LIST
@@ -162,18 +159,15 @@ static uint32_t task_reset_state[TASK_ID_COUNT] = {
 #endif /* CONFIG_TASK_RESET_LIST */
 
 /* Validity checks about static task invariants */
-BUILD_ASSERT(TASK_ID_COUNT <= sizeof(unsigned) * 8);
+BUILD_ASSERT(TASK_ID_COUNT <= sizeof(unsigned int) * 8);
 BUILD_ASSERT(TASK_ID_COUNT < (1 << (sizeof(task_id_t) * 8)));
 BUILD_ASSERT(BIT(TASK_ID_COUNT) < TASK_RESET_LOCK);
 
 /* Stacks for all tasks */
-#define TASK(n, r, d, s)  + s
-uint8_t task_stacks[0
-		    TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
-		    CONFIG_TASK_LIST
-		    CONFIG_TEST_TASK_LIST
-		    CONFIG_CTS_TASK_LIST
-] __aligned(8);
+#define TASK(n, r, d, s) +s
+uint8_t task_stacks[0 TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
+			    CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST
+				    CONFIG_CTS_TASK_LIST] __aligned(8);
 
 #undef TASK
 
@@ -202,15 +196,15 @@ static int need_resched_or_profiling;
  * can do their init within a task switching context.  The hooks task will then
  * make a call to enable all tasks.
  */
-static uint32_t tasks_ready = BIT(TASK_ID_HOOKS);
+static atomic_t tasks_ready = BIT(TASK_ID_HOOKS);
 /*
  * Initially allow only the HOOKS and IDLE task to run, regardless of ready
  * status, in order for HOOK_INIT to complete before other tasks.
  * task_enable_all_tasks() will open the flood gates.
  */
-static uint32_t tasks_enabled = BIT(TASK_ID_HOOKS) | BIT(TASK_ID_IDLE);
+static atomic_t tasks_enabled = BIT(TASK_ID_HOOKS) | BIT(TASK_ID_IDLE);
 
-static int start_called;  /* Has task swapping started */
+static int start_called; /* Has task swapping started */
 
 static inline task_ *__task_id_to_ptr(task_id_t id)
 {
@@ -227,11 +221,22 @@ void interrupt_enable(void)
 	asm("cpsie i");
 }
 
-inline int in_interrupt_context(void)
+inline bool is_interrupt_enabled(void)
+{
+	int primask;
+
+	/* Interrupts are enabled when PRIMASK bit is 0 */
+	asm("mrs %0, primask" : "=r"(primask));
+
+	return !(primask & 0x1);
+}
+
+inline bool in_interrupt_context(void)
 {
 	int ret;
-	asm("mrs %0, ipsr \n"             /* read exception number */
-	    "lsl %0, #23  \n":"=r"(ret)); /* exception bits are the 9 LSB */
+	asm("mrs %0, ipsr \n" /* read exception number */
+	    "lsl %0, #23  \n"
+	    : "=r"(ret)); /* exception bits are the 9 LSB */
 	return ret;
 }
 
@@ -239,8 +244,8 @@ inline int in_interrupt_context(void)
 static inline int get_interrupt_context(void)
 {
 	int ret;
-	asm("mrs %0, ipsr \n":"=r"(ret)); /* read exception number */
-	return ret & 0x1ff;               /* exception bits are the 9 LSB */
+	asm("mrs %0, ipsr \n" : "=r"(ret)); /* read exception number */
+	return ret & 0x1ff; /* exception bits are the 9 LSB */
 }
 #endif
 
@@ -253,7 +258,7 @@ task_id_t task_get_current(void)
 	return current_task - tasks;
 }
 
-uint32_t *task_get_event_bitmap(task_id_t tskid)
+atomic_t *task_get_event_bitmap(task_id_t tskid)
 {
 	task_ *tsk = __task_id_to_ptr(tskid);
 	return &tsk->events;
@@ -296,12 +301,11 @@ void svc_handler(int desched, task_id_t resched)
 	current = current_task;
 
 #ifdef CONFIG_DEBUG_STACK_OVERFLOW
-	if (*current->stack != STACK_UNUSED_VALUE) {
+	if (*current->stack != STACK_UNUSED_VALUE &&
+	    task_enabled(current - tasks)) {
 		panic_printf("\n\nStack overflow in %s task!\n",
 			     task_names[current - tasks]);
-#ifdef CONFIG_SOFTWARE_PANIC
 		software_panic(PANIC_SW_STACK_OVERFLOW, current - tasks);
-#endif
 	}
 #endif
 
@@ -341,7 +345,7 @@ void svc_handler(int desched, task_id_t resched)
 	if (next == current)
 		return;
 
-	/* Switch to new task */
+		/* Switch to new task */
 #ifdef CONFIG_TASK_PROFILING
 	task_switches++;
 #endif
@@ -354,7 +358,7 @@ void __schedule(int desched, int resched)
 	register int p0 asm("r0") = desched;
 	register int p1 asm("r1") = resched;
 
-	asm("svc 0"::"r"(p0),"r"(p1));
+	asm("svc 0" ::"r"(p0), "r"(p1));
 }
 
 #ifdef CONFIG_TASK_PROFILING
@@ -379,7 +383,9 @@ void __keep task_start_irq_handler(void *excep_return)
 	 * and we are not called from another exception (this must match the
 	 * logic for when we chain to svc_handler() below).
 	 */
-	if (!need_resched_or_profiling || (((uint32_t)excep_return & 0xf) == 1))
+	if (!need_resched_or_profiling ||
+	    (((uint32_t)excep_return & EXC_RETURN_MODE_MASK) ==
+	     EXC_RETURN_MODE_HANDLER))
 		return;
 
 	exc_start_time = t;
@@ -392,7 +398,9 @@ void __keep task_resched_if_needed(void *excep_return)
 	 * Continue iff a rescheduling event happened or profiling is active,
 	 * and we are not called from another exception.
 	 */
-	if (!need_resched_or_profiling || (((uint32_t)excep_return & 0xf) == 1))
+	if (!need_resched_or_profiling ||
+	    (((uint32_t)excep_return & EXC_RETURN_MODE_MASK) ==
+	     EXC_RETURN_MODE_HANDLER))
 		return;
 
 	svc_handler(0, 0);
@@ -405,6 +413,15 @@ static uint32_t __wait_evt(int timeout_us, task_id_t resched)
 	uint32_t evt;
 	int ret __attribute__((unused));
 
+	/*
+	 * Scheduling task when interrupts are disabled will result in Forced
+	 * Hard Fault because:
+	 * - Disabling interrupt using 'cpsid i' also disables SVCall handler
+	 *   (because it has configurable priority)
+	 * - Escalation to Hard Fault (also known as 'priority escalation')
+	 *   occurs when handler for that fault is not enabled
+	 */
+	ASSERT(is_interrupt_enabled());
 	ASSERT(!in_interrupt_context());
 
 	if (timeout_us > 0) {
@@ -413,7 +430,7 @@ static uint32_t __wait_evt(int timeout_us, task_id_t resched)
 		ret = timer_arm(deadline, me);
 		ASSERT(ret == EC_SUCCESS);
 	}
-	while (!(evt = deprecated_atomic_read_clear(&tsk->events))) {
+	while (!(evt = atomic_clear(&tsk->events))) {
 		/* Remove ourself and get the next task in the scheduler */
 		__schedule(1, resched);
 		resched = TASK_ID_IDLE;
@@ -421,35 +438,30 @@ static uint32_t __wait_evt(int timeout_us, task_id_t resched)
 	if (timeout_us > 0) {
 		timer_cancel(me);
 		/* Ensure timer event is clear, we no longer care about it */
-		deprecated_atomic_clear_bits(&tsk->events, TASK_EVENT_TIMER);
+		atomic_clear_bits(&tsk->events, TASK_EVENT_TIMER);
 	}
 	return evt;
 }
 
-uint32_t task_set_event(task_id_t tskid, uint32_t event, int wait)
+void task_set_event(task_id_t tskid, uint32_t event)
 {
 	task_ *receiver = __task_id_to_ptr(tskid);
 	ASSERT(receiver);
 
 	/* Set the event bit in the receiver message bitmap */
-	deprecated_atomic_or(&receiver->events, event);
+	atomic_or(&receiver->events, event);
 
 	/* Re-schedule if priorities have changed */
-	if (in_interrupt_context()) {
+	if (in_interrupt_context() || !is_interrupt_enabled()) {
 		/* The receiver might run again */
-		deprecated_atomic_or(&tasks_ready, 1 << tskid);
+		atomic_or(&tasks_ready, 1 << tskid);
 #ifndef CONFIG_TASK_PROFILING
 		if (start_called)
 			need_resched_or_profiling = 1;
 #endif
 	} else {
-		if (wait)
-			return __wait_evt(-1, tskid);
-		else
-			__schedule(0, tskid);
+		__schedule(0, tskid);
 	}
-
-	return 0;
 }
 
 uint32_t task_wait_event(int timeout_us)
@@ -480,8 +492,7 @@ uint32_t task_wait_event_mask(uint32_t event_mask, int timeout_us)
 
 	/* Re-post any other events collected */
 	if (events & ~event_mask)
-		deprecated_atomic_or(&current_task->events,
-				     events & ~event_mask);
+		atomic_or(&current_task->events, events & ~event_mask);
 
 	return events & event_mask;
 }
@@ -491,19 +502,26 @@ void task_enable_all_tasks(void)
 	/* Mark all tasks as ready and able to run. */
 	tasks_ready = tasks_enabled = BIT(TASK_ID_COUNT) - 1;
 	/* Reschedule the highest priority task. */
-	__schedule(0, 0);
+	if (is_interrupt_enabled())
+		__schedule(0, 0);
 }
 
 void task_enable_task(task_id_t tskid)
 {
-	deprecated_atomic_or(&tasks_enabled, BIT(tskid));
+	atomic_or(&tasks_enabled, BIT(tskid));
+}
+
+bool task_enabled(task_id_t tskid)
+{
+	return tasks_enabled & BIT(tskid);
 }
 
 void task_disable_task(task_id_t tskid)
 {
-	deprecated_atomic_clear_bits(&tasks_enabled, BIT(tskid));
+	atomic_clear_bits(&tasks_enabled, BIT(tskid));
 
-	if (!in_interrupt_context() && tskid == task_get_current())
+	if (!in_interrupt_context() && is_interrupt_enabled() &&
+	    tskid == task_get_current())
 		__schedule(0, 0);
 }
 
@@ -522,6 +540,15 @@ void task_clear_pending_irq(int irq)
 	CPU_NVIC_UNPEND(irq / 32) = 1 << (irq % 32);
 }
 
+/*
+ * Reading interrupt clear-pending register gives us information if interrupt
+ * is pending.
+ */
+bool task_is_irq_pending(int irq)
+{
+	return CPU_NVIC_UNPEND(irq / 32) & (1 << (irq % 32));
+}
+
 void task_trigger_irq(int irq)
 {
 	CPU_NVIC_SWTRIG = irq;
@@ -542,10 +569,10 @@ static uint32_t init_task_context(task_id_t id)
 	tasks[id].sp = (uint32_t)sp;
 
 	/* Initial context on stack (see __switchto()) */
-	sp[8] = tasks_init[id].r0;          /* r0 */
-	sp[13] = (uint32_t)task_exit_trap;  /* lr */
-	sp[14] = tasks_init[id].pc;         /* pc */
-	sp[15] = 0x01000000;                /* psr */
+	sp[8] = tasks_init[id].r0; /* r0 */
+	sp[13] = (uint32_t)task_exit_trap; /* lr */
+	sp[14] = tasks_init[id].pc; /* pc */
+	sp[15] = 0x01000000; /* psr */
 
 	/* Fill unused stack; also used to detect stack overflow. */
 	for (sp = tasks[id].stack; sp < (uint32_t *)tasks[id].sp; sp++)
@@ -579,8 +606,7 @@ static void deferred_task_reset(void)
 	while (deferred_reset_task_ids) {
 		task_id_t reset_id = __fls(deferred_reset_task_ids);
 
-		deprecated_atomic_clear_bits(&deferred_reset_task_ids,
-					     1 << reset_id);
+		atomic_clear_bits(&deferred_reset_task_ids, 1 << reset_id);
 		do_task_reset(reset_id);
 	}
 }
@@ -591,8 +617,7 @@ DECLARE_DEFERRED(deferred_task_reset);
  * and if it matches if_value, updates the state to new_value, and returns
  * TRUE.
  */
-static int update_reset_state(uint32_t *state,
-			      uint32_t if_value,
+static int update_reset_state(uint32_t *state, uint32_t if_value,
 			      uint32_t to_value)
 {
 	int update;
@@ -648,8 +673,7 @@ void task_enable_resets(void)
 	uint32_t *state = &task_reset_state[id];
 
 	if (*state == TASK_RESET_UNSUPPORTED) {
-		cprints(CC_TASK,
-			"%s called from non-resettable task, id: %d",
+		cprints(CC_TASK, "%s called from non-resettable task, id: %d",
 			__func__, id);
 		return;
 	}
@@ -675,7 +699,7 @@ void task_enable_resets(void)
 		return;
 
 	/* People are waiting for us to reset; schedule a reset. */
-	deprecated_atomic_or(&deferred_reset_task_ids, 1 << id);
+	atomic_or(&deferred_reset_task_ids, 1 << id);
 	/*
 	 * This will always trigger a deferred call after our new ID was
 	 * written. If the hook call is currently executing, it will run
@@ -692,8 +716,7 @@ void task_disable_resets(void)
 	uint32_t *state = &task_reset_state[id];
 
 	if (*state == TASK_RESET_UNSUPPORTED) {
-		cprints(CC_TASK,
-			"%s called from non-resettable task, id %d",
+		cprints(CC_TASK, "%s called from non-resettable task, id %d",
 			__func__, id);
 		return;
 	}
@@ -748,8 +771,8 @@ int task_reset_cleanup(void)
 	if (cleanup_req) {
 		while (!try_release_reset_lock(state)) {
 			/* Find the first waiter to notify. */
-			task_id_t notify_id = __fls(
-			    *state & TASK_RESET_WAITERS_MASK);
+			task_id_t notify_id =
+				__fls(*state & TASK_RESET_WAITERS_MASK);
 			/*
 			 * Remove the task from waiters first, so that
 			 * when it wakes after being notified, it is in
@@ -760,15 +783,14 @@ int task_reset_cleanup(void)
 			 * itself back to the list of tasks to notify,
 			 * and we will notify it again.
 			 */
-			deprecated_atomic_clear_bits(state, 1 << notify_id);
+			atomic_clear_bits(state, 1 << notify_id);
 			/*
 			 * Skip any invalid ids set by tasks that
 			 * requested a non-blocking reset.
 			 */
 			if (notify_id < TASK_ID_COUNT)
 				task_set_event(notify_id,
-					       TASK_EVENT_RESET_DONE,
-					       0);
+					       TASK_EVENT_RESET_DONE);
 		}
 	}
 
@@ -878,7 +900,7 @@ void mutex_lock(struct mutex *mtx)
 
 	id = 1 << task_get_current();
 
-	deprecated_atomic_or(&mtx->waiters, id);
+	atomic_or(&mtx->waiters, id);
 
 	do {
 		/* Try to get the lock (set 1 into the lock field) */
@@ -886,8 +908,9 @@ void mutex_lock(struct mutex *mtx)
 				     "   teq     %0, #0\n"
 				     "   it eq\n"
 				     "   strexeq %0, %2, [%1]\n"
-				     : "=&r" (value)
-				     : "r" (&mtx->lock), "r" (2) : "cc");
+				     : "=&r"(value)
+				     : "r"(&mtx->lock), "r"(2)
+				     : "cc");
 		/*
 		 * "value" is equals to 1 if the store conditional failed,
 		 * 2 if somebody else owns the mutex, 0 else.
@@ -897,7 +920,7 @@ void mutex_lock(struct mutex *mtx)
 			task_wait_event_mask(TASK_EVENT_MUTEX, 0);
 	} while (value);
 
-	deprecated_atomic_clear_bits(&mtx->waiters, id);
+	atomic_clear_bits(&mtx->waiters, id);
 }
 
 void mutex_unlock(struct mutex *mtx)
@@ -919,11 +942,11 @@ void mutex_unlock(struct mutex *mtx)
 		waiters &= ~BIT(id);
 
 		/* Somebody is waiting on the mutex */
-		task_set_event(id, TASK_EVENT_MUTEX, 0);
+		task_set_event(id, TASK_EVENT_MUTEX);
 	}
 
 	/* Ensure no event is remaining from mutex wake-up */
-	deprecated_atomic_clear_bits(&tsk->events, TASK_EVENT_MUTEX);
+	atomic_clear_bits(&tsk->events, TASK_EVENT_MUTEX);
 }
 
 void task_print_list(void)
@@ -933,7 +956,7 @@ void task_print_list(void)
 	ccputs("Task Ready Name         Events      Time (s)  StkUsed\n");
 
 	for (i = 0; i < TASK_ID_COUNT; i++) {
-		char is_ready = (tasks_ready & (1<<i)) ? 'R' : ' ';
+		char is_ready = ((uint32_t)tasks_ready & BIT(i)) ? 'R' : ' ';
 		uint32_t *sp;
 
 		int stackused = tasks_init[i].stack_size;
@@ -944,13 +967,13 @@ void task_print_list(void)
 			stackused -= sizeof(uint32_t);
 
 		ccprintf("%4d %c %-16s %08x %11.6lld  %3d/%3d\n", i, is_ready,
-			 task_names[i], tasks[i].events, tasks[i].runtime,
+			 task_names[i], (int)tasks[i].events, tasks[i].runtime,
 			 stackused, tasks_init[i].stack_size);
 		cflush();
 	}
 }
 
-int command_task_info(int argc, char **argv)
+static int command_task_info(int argc, const char **argv)
 {
 #ifdef CONFIG_TASK_PROFILING
 	int total = 0;
@@ -979,25 +1002,23 @@ int command_task_info(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_SAFE_CONSOLE_COMMAND(taskinfo, command_task_info,
-			     NULL,
+DECLARE_SAFE_CONSOLE_COMMAND(taskinfo, command_task_info, NULL,
 			     "Print task info");
 
 #ifdef CONFIG_CMD_TASKREADY
-static int command_task_ready(int argc, char **argv)
+static int command_task_ready(int argc, const char **argv)
 {
 	if (argc < 2) {
-		ccprintf("tasks_ready: 0x%08x\n", tasks_ready);
+		ccprintf("tasks_ready: 0x%08x\n", (int)tasks_ready);
 	} else {
 		tasks_ready = strtoi(argv[1], NULL, 16);
-		ccprintf("Setting tasks_ready to 0x%08x\n", tasks_ready);
+		ccprintf("Setting tasks_ready to 0x%08x\n", (int)tasks_ready);
 		__schedule(0, 0);
 	}
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(taskready, command_task_ready,
-			"[setmask]",
+DECLARE_CONSOLE_COMMAND(taskready, command_task_ready, "[setmask]",
 			"Print/set ready tasks");
 #endif
 
@@ -1052,7 +1073,7 @@ int task_start(void)
 }
 
 #ifdef CONFIG_CMD_TASK_RESET
-static int command_task_reset(int argc, char **argv)
+static int command_task_reset(int argc, const char **argv)
 {
 	task_id_t id;
 	char *e;
@@ -1067,7 +1088,6 @@ static int command_task_reset(int argc, char **argv)
 
 	return EC_ERROR_PARAM_COUNT;
 }
-DECLARE_CONSOLE_COMMAND(taskreset, command_task_reset,
-			"task_id",
+DECLARE_CONSOLE_COMMAND(taskreset, command_task_reset, "task_id",
 			"Reset a task");
-#endif  /* CONFIG_CMD_TASK_RESET */
+#endif /* CONFIG_CMD_TASK_RESET */
diff --git a/core/cortex-m/toolchain.mk b/core/cortex-m/toolchain.mk
new file mode 100644
index 0000000000..d52461bf3a
--- /dev/null
+++ b/core/cortex-m/toolchain.mk
@@ -0,0 +1,18 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+ifeq ($(cc-name),gcc)
+# coreboot sdk
+CROSS_COMPILE_ARM_DEFAULT:=/opt/coreboot-sdk/bin/arm-eabi-
+else
+# llvm sdk
+CROSS_COMPILE_ARM_DEFAULT:=armv7m-cros-eabi-
+endif
+CMAKE_SYSTEM_PROCESSOR ?= armv7
+# TODO(b/275450331): Enable the asm after we fix the crash.
+OPENSSL_NO_ASM ?= 1
+
+$(call set-option,CROSS_COMPILE,\
+	$(CROSS_COMPILE_arm),\
+	$(CROSS_COMPILE_ARM_DEFAULT))
diff --git a/core/cortex-m/vecttable.c b/core/cortex-m/vecttable.c
index d27962a7d8..aea4bf3dc7 100644
--- a/core/cortex-m/vecttable.c
+++ b/core/cortex-m/vecttable.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -7,7 +7,9 @@
 
 #ifndef ___INIT
 #define ___INIT
+#include "compiler.h"
 #include "config.h"
+
 #include <task.h>
 #endif
 
@@ -20,20 +22,18 @@ typedef void (*func)(void);
 #if PASS == 1
 /* Default exception handler */
 void __attribute__((used, naked)) default_handler(void);
-void default_handler()
+void default_handler(void)
 {
-	asm(
-	".thumb_func\n"
-	"	b exception_panic"
-	);
+	asm(".thumb_func\n"
+	    "	b exception_panic");
 }
 
 #define table(x) x
 
-#define weak_with_default __attribute__((used,weak,alias("default_handler")))
+#define weak_with_default __attribute__((used, weak, alias("default_handler")))
 
-#define vec(name) extern void weak_with_default name ## _handler(void);
-#define irq(num) vec(irq_ ## num)
+#define vec(name) extern void weak_with_default name##_handler(void);
+#define irq(num) vec(irq_##num)
 
 #define item(name) extern void name(void);
 #define null
@@ -41,13 +41,10 @@ void default_handler()
 extern void stack_end(void); /* not technically correct, it's just a pointer */
 extern void reset(void);
 
-#pragma GCC diagnostic push
-#if __GNUC__ >= 8
-#pragma GCC diagnostic ignored "-Wattribute-alias"
-#endif
+DISABLE_GCC_WARNING("-Wattribute-alias")
 /* Call default_handler if svc_handler is not found (task.c is not built) */
 void weak_with_default svc_handler(int desched, task_id_t resched);
-#pragma GCC diagnostic pop
+ENABLE_GCC_WARNING("-Wattribute-alias")
 
 /*
  * SVC handler helper
@@ -59,21 +56,19 @@ void weak_with_default svc_handler(int desched, task_id_t resched);
  * This approach differs slightly from the one in the document,
  * it only loads r0 (desched) and r1 (resched) for svc_handler.
  */
-void __attribute__((used,naked)) svc_helper_handler(void);
-void svc_helper_handler()
+void __attribute__((used, naked)) svc_helper_handler(void);
+void svc_helper_handler(void)
 {
-	asm(
-	".thumb_func\n"
-	"	tst lr, #4		/* see if called from supervisor mode */\n"
-	"	mrs r2, msp		/* get the correct stack pointer into r2 */\n"
-	"	it ne\n"
-	"	mrsne r2, psp\n"
-	"	ldr r1, [r2, #4]	/* get regs from stack frame */\n"
-	"	ldr r0, [r2]\n"
-	"	b %0			/* call svc_handler */\n"
-	:
-	: "i"(svc_handler)
-	);
+	asm(".thumb_func\n"
+	    "	tst lr, #4		/* see if called from supervisor mode */\n"
+	    "	mrs r2, msp		/* get the correct stack pointer into r2 */\n"
+	    "	it ne\n"
+	    "	mrsne r2, psp\n"
+	    "	ldr r1, [r2, #4]	/* get regs from stack frame */\n"
+	    "	ldr r0, [r2]\n"
+	    "	b %0			/* call svc_handler */\n"
+	    :
+	    : "i"(svc_handler));
 }
 
 #endif /* PASS 1 */
@@ -92,292 +87,73 @@ void svc_helper_handler()
  */
 #define IRQ_UNUSED_OFFSET 8
 
-#define table(x)								\
-	const func vectors[] __attribute__((section(".text.vecttable"))) = {	\
-		x								\
-		[IRQ_UNUSED_OFFSET] = null					\
-	};
+/* Disable warning that "initializer overrides prior initialization of this
+ * subobject", since we are explicitly doing this to handle the unused IRQs.
+ */
+DISABLE_CLANG_WARNING("-Winitializer-overrides")
+
+#define table(x)                                     \
+	const func vectors[] __attribute__((section( \
+		".text.vecttable"))) = { x[IRQ_UNUSED_OFFSET] = null };
 
-#define vec(name) name ## _handler,
-#define irq(num) [num < CONFIG_IRQ_COUNT ? num + IRQ_OFFSET : IRQ_UNUSED_OFFSET] = vec(irq_ ## num)
+#define vec(name) name##_handler,
+#define irq(num)                                                          \
+	[num < CONFIG_IRQ_COUNT ? num + IRQ_OFFSET : IRQ_UNUSED_OFFSET] = \
+		vec(irq_##num)
 
 #define item(name) name,
-#define null (void*)0,
+#define null (void *)0,
 #endif /* PASS 2 */
 
-table(
-	item(stack_end)
-	item(reset)
-	vec(nmi)
-	vec(hard_fault)
-	vec(mpu_fault)
-	vec(bus_fault)
-	vec(usage_fault)
-	null
-	null
-	null
-	null
-	item(svc_helper_handler)
-	vec(debug)
-	null
-	vec(pendsv)
-	vec(sys_tick)
-	irq(0)
-	irq(1)
-	irq(2)
-	irq(3)
-	irq(4)
-	irq(5)
-	irq(6)
-	irq(7)
-	irq(8)
-	irq(9)
-	irq(10)
-	irq(11)
-	irq(12)
-	irq(13)
-	irq(14)
-	irq(15)
-	irq(16)
-	irq(17)
-	irq(18)
-	irq(19)
-	irq(20)
-	irq(21)
-	irq(22)
-	irq(23)
-	irq(24)
-	irq(25)
-	irq(26)
-	irq(27)
-	irq(28)
-	irq(29)
-	irq(30)
-	irq(31)
-	irq(32)
-	irq(33)
-	irq(34)
-	irq(35)
-	irq(36)
-	irq(37)
-	irq(38)
-	irq(39)
-	irq(40)
-	irq(41)
-	irq(42)
-	irq(43)
-	irq(44)
-	irq(45)
-	irq(46)
-	irq(47)
-	irq(48)
-	irq(49)
-	irq(50)
-	irq(51)
-	irq(52)
-	irq(53)
-	irq(54)
-	irq(55)
-	irq(56)
-	irq(57)
-	irq(58)
-	irq(59)
-	irq(60)
-	irq(61)
-	irq(62)
-	irq(63)
-	irq(64)
-	irq(65)
-	irq(66)
-	irq(67)
-	irq(68)
-	irq(69)
-	irq(70)
-	irq(71)
-	irq(72)
-	irq(73)
-	irq(74)
-	irq(75)
-	irq(76)
-	irq(77)
-	irq(78)
-	irq(79)
-	irq(80)
-	irq(81)
-	irq(82)
-	irq(83)
-	irq(84)
-	irq(85)
-	irq(86)
-	irq(87)
-	irq(88)
-	irq(89)
-	irq(90)
-	irq(91)
-	irq(92)
-	irq(93)
-	irq(94)
-	irq(95)
-	irq(96)
-	irq(97)
-	irq(98)
-	irq(99)
-	irq(100)
-	irq(101)
-	irq(102)
-	irq(103)
-	irq(104)
-	irq(105)
-	irq(106)
-	irq(107)
-	irq(108)
-	irq(109)
-	irq(110)
-	irq(111)
-	irq(112)
-	irq(113)
-	irq(114)
-	irq(115)
-	irq(116)
-	irq(117)
-	irq(118)
-	irq(119)
-	irq(120)
-	irq(121)
-	irq(122)
-	irq(123)
-	irq(124)
-	irq(125)
-	irq(126)
-	irq(127)
-	irq(128)
-	irq(129)
-	irq(130)
-	irq(131)
-	irq(132)
-	irq(133)
-	irq(134)
-	irq(135)
-	irq(136)
-	irq(137)
-	irq(138)
-	irq(139)
-	irq(140)
-	irq(141)
-	irq(142)
-	irq(143)
-	irq(144)
-	irq(145)
-	irq(146)
-	irq(147)
-	irq(148)
-	irq(149)
-	irq(150)
-	irq(151)
-	irq(152)
-	irq(153)
-	irq(154)
-	irq(155)
-	irq(156)
-	irq(157)
-	irq(158)
-	irq(159)
-	irq(160)
-	irq(161)
-	irq(162)
-	irq(163)
-	irq(164)
-	irq(165)
-	irq(166)
-	irq(167)
-	irq(168)
-	irq(169)
-	irq(170)
-	irq(171)
-	irq(172)
-	irq(173)
-	irq(174)
-	irq(175)
-	irq(176)
-	irq(177)
-	irq(178)
-	irq(179)
-	irq(180)
-	irq(181)
-	irq(182)
-	irq(183)
-	irq(184)
-	irq(185)
-	irq(186)
-	irq(187)
-	irq(188)
-	irq(189)
-	irq(190)
-	irq(191)
-	irq(192)
-	irq(193)
-	irq(194)
-	irq(195)
-	irq(196)
-	irq(197)
-	irq(198)
-	irq(199)
-	irq(200)
-	irq(201)
-	irq(202)
-	irq(203)
-	irq(204)
-	irq(205)
-	irq(206)
-	irq(207)
-	irq(208)
-	irq(209)
-	irq(210)
-	irq(211)
-	irq(212)
-	irq(213)
-	irq(214)
-	irq(215)
-	irq(216)
-	irq(217)
-	irq(218)
-	irq(219)
-	irq(220)
-	irq(221)
-	irq(222)
-	irq(223)
-	irq(224)
-	irq(225)
-	irq(226)
-	irq(227)
-	irq(228)
-	irq(229)
-	irq(230)
-	irq(231)
-	irq(232)
-	irq(233)
-	irq(234)
-	irq(235)
-	irq(236)
-	irq(237)
-	irq(238)
-	irq(239)
-	irq(240)
-	irq(241)
-	irq(242)
-	irq(243)
-	irq(244)
-	irq(245)
-	irq(246)
-	irq(247)
-	irq(248)
-	irq(249)
-	irq(250)
-	irq(251)
-	irq(252)
-	irq(253)
-	irq(254)
-)
+table(item(stack_end) item(reset) vec(nmi) vec(hard_fault) vec(mpu_fault) vec(
+	bus_fault) vec(usage_fault) null null null null item(svc_helper_handler) vec(debug)
+	      null vec(pendsv) vec(sys_tick) irq(0) irq(1) irq(2) irq(3) irq(4) irq(
+		      5) irq(6) irq(7) irq(8) irq(9) irq(10) irq(11) irq(12) irq(13)
+		      irq(14) irq(15) irq(16) irq(17) irq(18) irq(19) irq(20) irq(
+			      21) irq(22) irq(23) irq(24) irq(25) irq(26) irq(27)
+			      irq(28) irq(29) irq(30) irq(31) irq(32) irq(33) irq(
+				      34) irq(35) irq(36) irq(37) irq(38) irq(39)
+				      irq(40) irq(41) irq(42) irq(43) irq(44) irq(
+					      45) irq(46) irq(47) irq(48) irq(49)
+					      irq(50) irq(51) irq(52) irq(53) irq(
+						      54) irq(55) irq(56) irq(57)
+						      irq(58) irq(59) irq(60) irq(
+							      61) irq(62) irq(63)
+							      irq(64) irq(65) irq(
+								      66) irq(67)
+								      irq(68) irq(
+									      69) irq(70)
+									      irq(71) irq(72) irq(73) irq(74) irq(75) irq(76) irq(77) irq(78) irq(79) irq(80) irq(81) irq(82) irq(83) irq(84) irq(85) irq(86) irq(87) irq(88) irq(89) irq(90) irq(91) irq(92) irq(93) irq(94) irq(95) irq(96) irq(97) irq(
+										      98) irq(99)
+										      irq(100) irq(101) irq(102) irq(103) irq(104) irq(105) irq(106) irq(
+											      107) irq(108) irq(109) irq(110) irq(111) irq(112) irq(113) irq(114) irq(115)
+											      irq(116) irq(117) irq(118) irq(119) irq(120) irq(121) irq(122) irq(
+												      123) irq(124) irq(125) irq(126) irq(127) irq(128) irq(129) irq(130) irq(131)
+												      irq(132) irq(133) irq(134) irq(135) irq(136) irq(137) irq(138) irq(
+													      139) irq(140) irq(141) irq(142) irq(143) irq(144) irq(145) irq(146) irq(147)
+													      irq(148) irq(149) irq(150) irq(151) irq(152) irq(153) irq(154) irq(
+														      155) irq(156) irq(157) irq(158) irq(159) irq(160) irq(161) irq(162) irq(163)
+														      irq(164) irq(165) irq(166) irq(167) irq(168) irq(169) irq(170) irq(
+															      171) irq(172) irq(173) irq(174) irq(175) irq(176) irq(177) irq(178)
+															      irq(179) irq(180) irq(181) irq(182) irq(183) irq(184) irq(185) irq(
+																      186) irq(187) irq(188) irq(189) irq(190) irq(191) irq(192)
+																      irq(193) irq(194) irq(195) irq(196) irq(197) irq(198) irq(
+																	      199) irq(200) irq(201) irq(202) irq(203) irq(204)
+																	      irq(205) irq(206) irq(207) irq(208) irq(209) irq(
+																		      210) irq(211) irq(212) irq(213) irq(214)
+																		      irq(215) irq(216) irq(217) irq(218) irq(
+																			      219) irq(220) irq(221) irq(222)
+																			      irq(223) irq(224) irq(225) irq(
+																				      226) irq(227) irq(228)
+																				      irq(229) irq(230) irq(231) irq(
+																					      232) irq(233) irq(234)
+																					      irq(235) irq(236) irq(
+																						      237) irq(238)
+																						      irq(239))
+
+#if PASS == 2
+	ENABLE_CLANG_WARNING("-Winitializer-overrides")
+#endif
 
 #if PASS == 1
 #undef PASS
diff --git a/core/cortex-m/watchdog.c b/core/cortex-m/watchdog.c
index 3e62b5f4c5..a94c6a9c25 100644
--- a/core/cortex-m/watchdog.c
+++ b/core/cortex-m/watchdog.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,11 +6,20 @@
 /* Watchdog common code */
 
 #include "common.h"
+#include "cpu.h"
 #include "panic.h"
 #include "task.h"
 #include "timer.h"
 #include "watchdog.h"
 
+/*
+ * As defined by Armv7-M Reference Manual B1.5.6 "Exception Entry Behavior",
+ * the structure of the saved context on the stack is:
+ * r0, r1, r2, r3, r12, lr, pc, psr, ...
+ */
+#define STACK_IDX_REG_LR 5
+#define STACK_IDX_REG_PC 6
+
 void __keep watchdog_trace(uint32_t excep_lr, uint32_t excep_sp)
 {
 	uint32_t psp;
@@ -25,11 +34,18 @@ void __keep watchdog_trace(uint32_t excep_lr, uint32_t excep_sp)
 		stack = (uint32_t *)psp;
 	}
 
-	panic_set_reason(PANIC_SW_WATCHDOG, stack[6],
+	panic_set_reason(PANIC_SW_WATCHDOG, stack[STACK_IDX_REG_PC],
 			 (excep_lr & 0xf) == 1 ? 0xff : task_get_current());
 
+	/*
+	 * This is our last breath, the last opportunity to sort out all
+	 * matters. Flush and invalidate D-cache if cache enabled.
+	 */
+	if (IS_ENABLED(CONFIG_ARMV7M_CACHE))
+		cpu_clean_invalidate_dcache();
+
 	panic_printf("### WATCHDOG PC=%08x / LR=%08x / pSP=%08x ",
-		     stack[6], stack[5], psp);
+		     stack[STACK_IDX_REG_PC], stack[STACK_IDX_REG_LR], psp);
 	if ((excep_lr & 0xf) == 1)
 		panic_puts("(exc) ###\n");
 	else
diff --git a/core/cortex-m0/__builtin.c b/core/cortex-m0/__builtin.c
index 4bf495a011..8e2bf984ff 100644
--- a/core/cortex-m0/__builtin.c
+++ b/core/cortex-m0/__builtin.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/core/cortex-m0/asm_offsets.c b/core/cortex-m0/asm_offsets.c
new file mode 100644
index 0000000000..8bf44007bc
--- /dev/null
+++ b/core/cortex-m0/asm_offsets.c
@@ -0,0 +1,16 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "asm_define.h"
+#include "config.h"
+#include "panic.h"
+
+void unused(void)
+{
+	ASM_DEFINE_OFFSET("ASM_PANIC_DATA_CM_REGS_OFFSET", struct panic_data,
+			  cm.regs);
+	ASM_DEFINE("ASM_PANIC_DATA_PTR", PANIC_DATA_PTR);
+	ASM_DEFINE("ASM_PANIC_STACK_ADDR", ((uint32_t)PANIC_DATA_PTR) & ~7);
+}
diff --git a/core/cortex-m0/atomic.h b/core/cortex-m0/atomic.h
index 78ac91a676..9fd3ab849b 100644
--- a/core/cortex-m0/atomic.h
+++ b/core/cortex-m0/atomic.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,6 +8,7 @@
 #ifndef __CROS_EC_ATOMIC_H
 #define __CROS_EC_ATOMIC_H
 
+#include "atomic_t.h"
 #include "common.h"
 
 /**
@@ -15,59 +16,62 @@
  *
  * There is no load/store exclusive on ARMv6-M, just disable interrupts
  */
-#define ATOMIC_OP(asm_op, a, v) do {				\
-	uint32_t reg0;						\
-								\
-	__asm__ __volatile__("   cpsid i\n"			\
-			     "   ldr  %0, [%1]\n"		\
-			     #asm_op" %0, %0, %2\n"		\
-			     "   str  %0, [%1]\n"		\
-			     "   cpsie i\n"			\
-			     : "=&b" (reg0)			\
-			     : "b" (a), "r" (v) : "cc");	\
-} while (0)
+#define ATOMIC_OP(asm_op, a, v)                                 \
+	({                                                      \
+		uint32_t reg0, reg1;                            \
+                                                                \
+		__asm__ __volatile__(".syntax unified\n"        \
+				     "   cpsid i\n"             \
+				     "   ldr  %0, [%2]\n"       \
+				     "   mov  %1, %0\n" #asm_op \
+				     " %0, %0, %3\n"            \
+				     "   str  %0, [%2]\n"       \
+				     "   cpsie i\n"             \
+				     : "=&l"(reg0), "=&l"(reg1) \
+				     : "l"(a), "r"(v)           \
+				     : "cc", "memory");         \
+		reg1;                                           \
+	})
 
-/*
- * The atomic_* functions are marked as deprecated as a part of the process of
- * transaction to Zephyr compatible atomic functions. These prefixes will be
- * removed in the following patches. Please see b:169151160 for more details.
- */
-
-static inline void deprecated_atomic_clear_bits(uint32_t volatile *addr,
-						uint32_t bits)
+static inline atomic_val_t atomic_clear_bits(atomic_t *addr, atomic_val_t bits)
 {
-	ATOMIC_OP(bic, addr, bits);
+	return ATOMIC_OP(bics, addr, bits);
 }
 
-static inline void deprecated_atomic_or(uint32_t volatile *addr, uint32_t bits)
+static inline atomic_val_t atomic_or(atomic_t *addr, atomic_val_t bits)
 {
-	ATOMIC_OP(orr, addr, bits);
+	return ATOMIC_OP(orrs, addr, bits);
 }
 
-static inline void deprecated_atomic_add(uint32_t volatile *addr,
-					 uint32_t value)
+static inline atomic_val_t atomic_add(atomic_t *addr, atomic_val_t value)
 {
-	ATOMIC_OP(add, addr, value);
+	return ATOMIC_OP(add, addr, value);
 }
 
-static inline void deprecated_atomic_sub(uint32_t volatile *addr,
-					 uint32_t value)
+static inline atomic_val_t atomic_sub(atomic_t *addr, atomic_val_t value)
 {
-	ATOMIC_OP(sub, addr, value);
+	return ATOMIC_OP(subs, addr, value);
 }
 
-static inline uint32_t deprecated_atomic_read_clear(uint32_t volatile *addr)
+static inline atomic_val_t atomic_clear(atomic_t *addr)
 {
-	uint32_t ret;
+	atomic_t ret;
 
-	__asm__ __volatile__("   mov     %2, #0\n"
+	__asm__ __volatile__("   movs    %2, #0\n"
 			     "   cpsid   i\n"
 			     "   ldr     %0, [%1]\n"
 			     "   str     %2, [%1]\n"
 			     "   cpsie   i\n"
-			     : "=&b" (ret)
-			     : "b" (addr), "r" (0) : "cc");
+			     : "=&l"(ret)
+			     : "l"(addr), "r"(0)
+			     : "cc", "memory");
 
 	return ret;
 }
-#endif  /* __CROS_EC_ATOMIC_H */
+
+static inline atomic_val_t atomic_and(atomic_t *addr, atomic_val_t bits)
+{
+	return ATOMIC_OP(ands, addr, bits);
+}
+
+#endif /* __CROS_EC_ATOMIC_H */
diff --git a/core/cortex-m0/build.mk b/core/cortex-m0/build.mk
index a314976bce..9fef30668d 100644
--- a/core/cortex-m0/build.mk
+++ b/core/cortex-m0/build.mk
@@ -1,18 +1,31 @@
 # -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
+# Copyright 2014 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
 # Cortex-M0 core OS files build
 #
 
-# Use coreboot-sdk
-$(call set-option,CROSS_COMPILE,\
-	$(CROSS_COMPILE_arm),\
-	/opt/coreboot-sdk/bin/arm-eabi-)
+# When set to 1, exclusively use builtins from compiler-rt.
+# When set to 0, use EC's builtins.
+USE_LLVM_COMPILER_RT:=0
+
+ifeq ($(USE_LLVM_COMPILER_RT),1)
+CFLAGS_CPU+=-DUSE_LLVM_COMPILER_RT
+endif
 
 # CPU specific compilation flags
-CFLAGS_CPU+=-mthumb -Os -mno-sched-prolog
+CFLAGS_CPU+=-mthumb
+ifeq ($(cc-name),clang)
+CFLAGS_CPU+=-Oz		# Like -Os (and thus -O2), but reduces code size further.
+# b/256193799: Reduce inline threshold to decrease code size.
+CFLAGS_CPU+=-Wl,-mllvm -Wl,-inline-threshold=-10
+# Link compiler-rt when using clang, so clang finds the builtins it provides.
+LDFLAGS_EXTRA+=-lclang_rt.builtins-armv6m
+else
+CFLAGS_CPU+=-Os
+CFLAGS_CPU+=-mno-sched-prolog
+endif
 CFLAGS_CPU+=-mno-unaligned-access
 
 ifneq ($(CONFIG_LTO),)
@@ -20,8 +33,15 @@ CFLAGS_CPU+=-flto
 LDFLAGS_EXTRA+=-flto
 endif
 
-core-y=cpu.o init.o thumb_case.o div.o lmul.o ldivmod.o mula.o uldivmod.o
-core-y+=vecttable.o __builtin.o
+core-y=cpu.o debug.o init.o thumb_case.o mula.o
+ifeq ($(USE_LLVM_COMPILER_RT),0)
+core-y+=div.o lmul.o ldivmod.o uldivmod.o
+endif
+
+core-y+=vecttable.o
+ifeq ($(USE_LLVM_COMPILER_RT),0)
+core-y+=__builtin.o
+endif
 core-$(CONFIG_COMMON_PANIC_OUTPUT)+=panic.o
 core-$(CONFIG_COMMON_RUNTIME)+=switch.o task.o
 
@@ -34,3 +54,11 @@ core-$(CONFIG_CURVE25519)+=curve25519/scalarmult.o
 core-$(CONFIG_CURVE25519)+=curve25519/sqr.o
 
 core-$(CONFIG_WATCHDOG)+=watchdog.o
+
+core-$(CONFIG_COMMON_PANIC_OUTPUT)+=exception_panic.o
+
+$(CORE_RW_OUT)/exception_panic.o: $(CORE_RW_OUT)/asm_offsets.h
+$(CORE_RW_OUT)/exception_panic.o: CFLAGS+=-I$(CORE_RW_OUT)
+
+$(CORE_RO_OUT)/exception_panic.o: $(CORE_RO_OUT)/asm_offsets.h
+$(CORE_RO_OUT)/exception_panic.o: CFLAGS+=-I$(CORE_RO_OUT)
diff --git a/core/cortex-m0/config_core.h b/core/cortex-m0/config_core.h
index c31adc471c..63e6da8972 100644
--- a/core/cortex-m0/config_core.h
+++ b/core/cortex-m0/config_core.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,10 +10,13 @@
 #define BFD_ARCH arm
 #define BFD_FORMAT "elf32-littlearm"
 
-/* Emulate the CLZ/CTZ instructions since the CPU core is lacking support */
+/*
+ * Emulate the CLZ/CTZ instructions since the CPU core is lacking support.
+ */
+#ifndef USE_LLVM_COMPILER_RT
 #define CONFIG_SOFTWARE_CLZ
 #define CONFIG_SOFTWARE_CTZ
-#define CONFIG_SOFTWARE_PANIC
+#endif /* USE_LLVM_COMPILER_RT */
 
 #define CONFIG_ASSEMBLY_MULA32
 
diff --git a/core/cortex-m0/cpu.c b/core/cortex-m0/cpu.c
index b354cc03e2..e180570863 100644
--- a/core/cortex-m0/cpu.c
+++ b/core/cortex-m0/cpu.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/cortex-m0/cpu.h b/core/cortex-m0/cpu.h
index ac184090f9..bdb7a3c6f5 100644
--- a/core/cortex-m0/cpu.h
+++ b/core/cortex-m0/cpu.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,36 +8,46 @@
 #ifndef __CROS_EC_CPU_H
 #define __CROS_EC_CPU_H
 
-#include <stdint.h>
 #include "compile_time_macros.h"
+#include "debug.h"
+
+#include <stdint.h>
 
 /* Macro to access 32-bit registers */
-#define CPUREG(addr) (*(volatile uint32_t*)(addr))
+#define CPUREG(addr) (*(volatile uint32_t *)(addr))
 
 /* Nested Vectored Interrupt Controller */
-#define CPU_NVIC_EN(x)         CPUREG(0xe000e100)
-#define CPU_NVIC_DIS(x)        CPUREG(0xe000e180)
-#define CPU_NVIC_UNPEND(x)     CPUREG(0xe000e280)
-#define CPU_NVIC_ISPR(x)       CPUREG(0xe000e200)
-#define CPU_NVIC_PRI(x)        CPUREG(0xe000e400 + 4 * (x))
+#define CPU_NVIC_EN(x) CPUREG(0xe000e100)
+#define CPU_NVIC_DIS(x) CPUREG(0xe000e180)
+#define CPU_NVIC_UNPEND(x) CPUREG(0xe000e280)
+#define CPU_NVIC_ISPR(x) CPUREG(0xe000e200)
+#define CPU_NVIC_PRI(x) CPUREG(0xe000e400 + 4 * (x))
 
 /* System Control Block */
-#define CPU_SCB_ICSR           CPUREG(0xe000ed04)
+#define CPU_SCB_ICSR CPUREG(0xe000ed04)
 
 /* SCB AIRCR : Application interrupt and reset control register */
-#define CPU_NVIC_APINT         CPUREG(0xe000ed0c)
-#define  CPU_NVIC_APINT_SYSRST  BIT(2)            /* System reset request */
-#define  CPU_NVIC_APINT_ENDIAN  BIT(15)           /* Endianness */
-#define  CPU_NVIC_APINT_KEY_RD  (0U)
-#define  CPU_NVIC_APINT_KEY_WR  (0x05FAU << 16)
+#define CPU_NVIC_APINT CPUREG(0xe000ed0c)
+#define CPU_NVIC_APINT_SYSRST BIT(2) /* System reset request */
+#define CPU_NVIC_APINT_ENDIAN BIT(15) /* Endianness */
+#define CPU_NVIC_APINT_KEY_RD (0U)
+#define CPU_NVIC_APINT_KEY_WR (0x05FAU << 16)
 /* SCB SCR : System Control Register */
-#define CPU_SCB_SYSCTRL        CPUREG(0xe000ed10)
-#define CPU_NVIC_CCR           CPUREG(0xe000ed14)
-#define CPU_NVIC_SHCSR2        CPUREG(0xe000ed1c)
-#define CPU_NVIC_SHCSR3        CPUREG(0xe000ed20)
+#define CPU_SCB_SYSCTRL CPUREG(0xe000ed10)
+#define CPU_NVIC_CCR CPUREG(0xe000ed14)
+#define CPU_NVIC_SHCSR2 CPUREG(0xe000ed1c)
+#define CPU_NVIC_SHCSR3 CPUREG(0xe000ed20)
 
 #define CPU_NVIC_CCR_UNALIGN_TRAP BIT(3)
 
+/* Bitfield values for EXC_RETURN. */
+#define EXC_RETURN_SPSEL_MASK BIT(2)
+#define EXC_RETURN_SPSEL_MSP 0
+#define EXC_RETURN_SPSEL_PSP BIT(2)
+#define EXC_RETURN_MODE_MASK BIT(3)
+#define EXC_RETURN_MODE_HANDLER 0
+#define EXC_RETURN_MODE_THREAD BIT(3)
+
 /* Set up the cpu to detect faults */
 void cpu_init(void);
 
@@ -49,10 +59,16 @@ static inline void cpu_set_interrupt_priority(uint8_t irq, uint8_t priority)
 	if (priority > 3)
 		priority = 3;
 
-	CPU_NVIC_PRI(irq / 4) =
-		(CPU_NVIC_PRI(irq / 4) &
-		 ~(3 << prio_shift)) |
-		(priority << prio_shift);
+	CPU_NVIC_PRI(irq / 4) = (CPU_NVIC_PRI(irq / 4) & ~(3 << prio_shift)) |
+				(priority << prio_shift);
+}
+
+static inline void cpu_enter_suspend_mode(void)
+{
+	/* Preserve debug sessions by not suspending when connected */
+	if (!debugger_is_connected()) {
+		asm("wfi");
+	}
 }
 
 #endif /* __CROS_EC_CPU_H */
diff --git a/core/cortex-m0/debug.c b/core/cortex-m0/debug.c
new file mode 120000
index 0000000000..3cada87897
--- /dev/null
+++ b/core/cortex-m0/debug.c
@@ -0,0 +1 @@
+../cortex-m/debug.c
\ No newline at end of file
diff --git a/core/cortex-m0/debug.h b/core/cortex-m0/debug.h
new file mode 120000
index 0000000000..d79be16190
--- /dev/null
+++ b/core/cortex-m0/debug.h
@@ -0,0 +1 @@
+../cortex-m/debug.h
\ No newline at end of file
diff --git a/core/cortex-m0/ec.lds.S b/core/cortex-m0/ec.lds.S
index 6839b37778..6e8206e311 100644
--- a/core/cortex-m0/ec.lds.S
+++ b/core/cortex-m0/ec.lds.S
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -135,6 +135,10 @@ SECTIONS
 		KEEP(*(.rodata.HOOK_CHIPSET_SHUTDOWN_COMPLETE))
 		__hooks_chipset_shutdown_complete_end = .;
 
+		__hooks_chipset_hard_off = .;
+		KEEP(*(.rodata.HOOK_CHIPSET_HARD_OFF))
+		__hooks_chipset_hard_off_end = .;
+
 		__hooks_chipset_reset = .;
 		KEEP(*(.rodata.HOOK_CHIPSET_RESET))
 		__hooks_chipset_reset_end = .;
@@ -151,6 +155,12 @@ SECTIONS
 		KEEP(*(.rodata.HOOK_TABLET_MODE_CHANGE))
 		__hooks_tablet_mode_change_end = .;
 
+#ifdef CONFIG_BODY_DETECTION
+		__hooks_body_detect_change = .;
+		KEEP(*(.rodata.HOOK_BODY_DETECT_CHANGE))
+		__hooks_body_detect_change_end = .;
+#endif
+
 		__hooks_base_attached_change = .;
 		KEEP(*(.rodata.HOOK_BASE_ATTACHED_CHANGE))
 		__hooks_base_attached_change_end = .;
@@ -185,6 +195,10 @@ SECTIONS
 		KEEP(*(.rodata.HOOK_USB_PD_CONNECT))
 		__hooks_usb_pd_connect_end = .;
 
+		__hooks_power_supply_change = .;
+		KEEP(*(.rodata.HOOK_POWER_SUPPLY_CHANGE))
+		__hooks_power_supply_change_end = .;
+
 		__deferred_funcs = .;
 		KEEP(*(.rodata.deferred))
 		__deferred_funcs_end = .;
@@ -216,7 +230,7 @@ SECTIONS
 		*(.init.rom)
 		__init_rom_end = .;
 
-#if defined(SECTION_IS_RO) && defined(CONFIG_FLASH)
+#if defined(SECTION_IS_RO) && defined(CONFIG_FLASH_CROS)
 		. = ALIGN(64);
 		KEEP(*(.google))
 #endif
@@ -259,8 +273,7 @@ SECTIONS
 		. = ALIGN(8);
 		*(.bss.system_stack)
 		/* Rest of .bss takes care of its own alignment */
-		*(.bss)
-		*(.bss.slow)
+		*(.bss*)
 
 		/*
 		 * Reserve space for deferred function firing times.
@@ -281,7 +294,7 @@ SECTIONS
 		. = ALIGN(4);
 		__data_start = .;
 		*(.data.tasks)
-		*(.data)
+		*(.data*)
 		. = ALIGN(4);
 		*(.iram.text)
 		. = ALIGN(4);
@@ -304,18 +317,40 @@ SECTIONS
 		     (__shared_mem_buf + CONFIG_SHAREDMEM_MINIMUM_SIZE);
 
 	/*
-	 * __flash_used is used in flash free calculations by the makefile.
+	 * Relocations are not supported, so make sure that there is no GOT
+	 * section. See http://issuetracker.google.com/234507656#comment15.
+	 */
+	.got (NOLOAD) :
+	{
+		KEEP(*(.got*));
+	}
+	ASSERT(SIZEOF(.got) == 0, "GOT section found, but not supported.\
+ Make sure that all code is compiled without -fPIC.")
+
+	/*
+	 * __flash_used and __flash_size is used in flash free calculations by
+	 * the makefile. Note the difference between __flash_size and
+	 * __config_flash_size. __flash_size is the flash size for the given
+	 * image (RW, RO, etc.), while __config_flash_size is the *total*
+	 * flash size.
 	 * __image_size is stored in the struct image_data header and used
-	 * in hash calcuations.
+	 * in hash calculations.
 	 */
 	__flash_used = LOADADDR(.data) + SIZEOF(.data) - ORIGIN(FLASH);
+	__flash_size = LENGTH(FLASH);
 	__image_size = __flash_used;
 
-#ifdef CONFIG_FLASH
+#if defined(SECTION_IS_RW) && (CONFIG_FLASH_WRITE_SIZE > 0)
+	/* Alignment is needed by flash_command_write() for RW update. */
+	ASSERT(__image_size % CONFIG_FLASH_WRITE_SIZE == 0,
+	       "Error: RW image is not aligned to CONFIG_FLASH_WRITE_SIZE")
+#endif
+
+#ifdef CONFIG_FLASH_CROS
         /*
          * These linker labels are just for analysis and not used in the code.
          */
-	__config_flash_size = CONFIG_FLASH_SIZE;
+	__config_flash_size = CONFIG_FLASH_SIZE_BYTES;
 	__config_ro_size = CONFIG_RO_SIZE;
 	__config_ec_protected_storage_size = CONFIG_EC_PROTECTED_STORAGE_SIZE;
 	__config_rw_size = CONFIG_RW_SIZE;
@@ -349,7 +384,7 @@ SECTIONS
 #undef REGION
 #endif /* CONFIG_CHIP_MEMORY_REGIONS */
 
-#if !(defined(SECTION_IS_RO) && defined(CONFIG_FLASH))
+#if !(defined(SECTION_IS_RO) && defined(CONFIG_FLASH_CROS))
     /DISCARD/ : { *(.google) }
 #endif
     /DISCARD/ : { *(.ARM.*) }
diff --git a/core/cortex-m0/exception_panic.S b/core/cortex-m0/exception_panic.S
new file mode 100644
index 0000000000..73585bb6d9
--- /dev/null
+++ b/core/cortex-m0/exception_panic.S
@@ -0,0 +1,38 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "asm_offsets.h"
+
+.syntax unified
+.text
+.thumb
+.cpu cortex-m0
+
+.global exception_panic
+.thumb_func
+.align 2
+exception_panic:
+	ldr r3, pstack
+	ldr r0, pregs
+	mov ip, r3
+	mrs r1, psp
+	mrs r2, ipsr
+	mov r3, sp
+	stmia r0!, {r1-r7}
+	mov r1, r8
+	mov r2, r9
+	mov r3, r10
+	mov r4, r11
+	mov r5, lr
+	stmia r0!, {r1-r5}
+	mov sp, ip
+	bl report_panic
+
+pstack:
+	.word ASM_PANIC_STACK_ADDR
+
+.equ PREGS, (ASM_PANIC_DATA_CM_REGS_OFFSET + ASM_PANIC_DATA_PTR)
+pregs:
+	.word PREGS
diff --git a/core/cortex-m0/include/fpu.h b/core/cortex-m0/include/fpu.h
new file mode 100644
index 0000000000..1054f388b0
--- /dev/null
+++ b/core/cortex-m0/include/fpu.h
@@ -0,0 +1,11 @@
+/* Copyright 2017 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Math utility functions for ARMv6-M */
+
+#ifndef __CROS_EC_FPU_H
+#define __CROS_EC_FPU_H
+
+#endif /* __CROS_EC_FPU_H */
diff --git a/core/cortex-m0/include/math.h b/core/cortex-m0/include/math.h
deleted file mode 100644
index 4c8955e74d..0000000000
--- a/core/cortex-m0/include/math.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Math utility functions for ARMv6-M */
-
-#ifndef __CROS_EC_MATH_H
-#define __CROS_EC_MATH_H
-
-#endif  /* __CROS_EC_MATH_H */
diff --git a/core/cortex-m0/init.S b/core/cortex-m0/init.S
index 5047d18380..58316e92d6 100644
--- a/core/cortex-m0/init.S
+++ b/core/cortex-m0/init.S
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -111,19 +111,9 @@ _data_end:
 _data_lma_start:
 .long __data_lma_start
 
-/* Mock functions to avoid linker complaints */
-.global __aeabi_unwind_cpp_pr0
-.global __aeabi_unwind_cpp_pr1
-.global __aeabi_unwind_cpp_pr2
-__aeabi_unwind_cpp_pr0:
-__aeabi_unwind_cpp_pr1:
-__aeabi_unwind_cpp_pr2:
-	bx lr
-
 /* Reserve space for system stack */
 .section .bss.system_stack
 stack_start:
 .space CONFIG_STACK_SIZE, 0
 stack_end:
 .global stack_end
-
diff --git a/core/cortex-m0/irq_handler.h b/core/cortex-m0/irq_handler.h
index 1ad033ab2d..f2f6a220e4 100644
--- a/core/cortex-m0/irq_handler.h
+++ b/core/cortex-m0/irq_handler.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,23 +20,26 @@
  */
 #define DECLARE_IRQ(irq, routine, priority) DECLARE_IRQ_(irq, routine, priority)
 #ifdef CONFIG_TASK_PROFILING
-#define DECLARE_IRQ_(irq, routine, priority)                    \
-	void IRQ_HANDLER(irq)(void)				\
-	{							\
-		void *ret = __builtin_return_address(0);	\
-		task_start_irq_handler(ret);			\
-		routine();					\
-		task_end_irq_handler(ret);			\
-	}							\
-	const struct irq_priority __keep IRQ_PRIORITY(irq)	\
-	__attribute__((section(".rodata.irqprio")))		\
-			= {irq, priority}
+#define DECLARE_IRQ_(irq, routine, priority)                         \
+	static void routine(void);                                   \
+	void IRQ_HANDLER(irq)(void)                                  \
+	{                                                            \
+		void *ret = __builtin_return_address(0);             \
+		task_start_irq_handler(ret);                         \
+		routine();                                           \
+		task_end_irq_handler(ret);                           \
+	}                                                            \
+	const struct irq_priority __keep IRQ_PRIORITY(irq)           \
+		__attribute__((section(".rodata.irqprio"))) = { irq, \
+								priority }
 #else /* CONFIG_TASK_PROFILING */
 /* No Profiling : connect directly the IRQ vector */
-#define DECLARE_IRQ_(irq, routine, priority)                    \
-	void IRQ_HANDLER(irq)(void) __attribute__((alias(STRINGIFY(routine))));\
-	const struct irq_priority __keep IRQ_PRIORITY(irq)	\
-	__attribute__((section(".rodata.irqprio")))		\
-			= {irq, priority}
+#define DECLARE_IRQ_(irq, routine, priority)                         \
+	static void __keep routine(void);                            \
+	void IRQ_HANDLER(irq)(void)                                  \
+		__attribute__((alias(STRINGIFY(routine))));          \
+	const struct irq_priority __keep IRQ_PRIORITY(irq)           \
+		__attribute__((section(".rodata.irqprio"))) = { irq, \
+								priority }
 #endif /* CONFIG_TASK_PROFILING */
-#endif  /* __CROS_EC_IRQ_HANDLER_H */
+#endif /* __CROS_EC_IRQ_HANDLER_H */
diff --git a/core/cortex-m0/mula.S b/core/cortex-m0/mula.S
index 02e617c328..7bb54263b4 100644
--- a/core/cortex-m0/mula.S
+++ b/core/cortex-m0/mula.S
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/cortex-m0/panic-internal.h b/core/cortex-m0/panic-internal.h
index 51c12f65b2..9f831495ff 100644
--- a/core/cortex-m0/panic-internal.h
+++ b/core/cortex-m0/panic-internal.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,4 +10,4 @@
 
 noreturn void exception_panic(void) __attribute__((naked));
 
-#endif  /* __CROS_EC_PANIC_INTERNAL_H */
+#endif /* __CROS_EC_PANIC_INTERNAL_H */
diff --git a/core/cortex-m0/panic.c b/core/cortex-m0/panic.c
index 4fe69fddb1..533e45713d 100644
--- a/core/cortex-m0/panic.c
+++ b/core/cortex-m0/panic.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,8 +7,8 @@
 #include "console.h"
 #include "cpu.h"
 #include "host_command.h"
-#include "panic.h"
 #include "panic-internal.h"
+#include "panic.h"
 #include "printf.h"
 #include "system.h"
 #include "task.h"
@@ -19,13 +19,8 @@
 /* Whether bus fault is ignored */
 static int bus_fault_ignored;
 
-
 /* Panic data goes at the end of RAM. */
-static struct panic_data * const pdata_ptr = PANIC_DATA_PTR;
-
-/* Preceded by stack, rounded down to nearest 64-bit-aligned boundary */
-static const uint32_t pstack_addr = (CONFIG_RAM_BASE + CONFIG_RAM_SIZE
-				     - sizeof(struct panic_data)) & ~7;
+static struct panic_data *const pdata_ptr = PANIC_DATA_PTR;
 
 /**
  * Print the name and value of a register
@@ -82,8 +77,8 @@ void panic_data_print(const struct panic_data *pdata)
 {
 	const uint32_t *lregs = pdata->cm.regs;
 	const uint32_t *sregs = NULL;
-	const int32_t in_handler =
-		is_frame_in_handler_stack(pdata->cm.regs[11]);
+	const int32_t in_handler = is_frame_in_handler_stack(
+		pdata->cm.regs[CORTEX_PANIC_REGISTER_LR]);
 	int i;
 
 	if (pdata->flags & PANIC_DATA_FLAG_FRAME_VALID)
@@ -91,17 +86,20 @@ void panic_data_print(const struct panic_data *pdata)
 
 	panic_printf("\n=== %s EXCEPTION: %02x ====== xPSR: %08x ===\n",
 		     in_handler ? "HANDLER" : "PROCESS",
-		     lregs[1] & 0xff, sregs ? sregs[7] : -1);
+		     lregs[CORTEX_PANIC_REGISTER_IPSR] & 0xff,
+		     sregs ? sregs[CORTEX_PANIC_FRAME_REGISTER_PSR] : -1);
 	for (i = 0; i < 4; i++)
 		print_reg(i, sregs, i);
 	for (i = 4; i < 10; i++)
 		print_reg(i, lregs, i - 1);
-	print_reg(10, lregs, 9);
-	print_reg(11, lregs, 10);
-	print_reg(12, sregs, 4);
-	print_reg(13, lregs, in_handler ? 2 : 0);
-	print_reg(14, sregs, 5);
-	print_reg(15, sregs, 6);
+	print_reg(10, lregs, CORTEX_PANIC_REGISTER_R10);
+	print_reg(11, lregs, CORTEX_PANIC_REGISTER_R11);
+	print_reg(12, sregs, CORTEX_PANIC_FRAME_REGISTER_R12);
+	print_reg(13, lregs,
+		  in_handler ? CORTEX_PANIC_REGISTER_MSP :
+			       CORTEX_PANIC_REGISTER_PSP);
+	print_reg(14, sregs, CORTEX_PANIC_FRAME_REGISTER_LR);
+	print_reg(15, sregs, CORTEX_PANIC_FRAME_REGISTER_PC);
 }
 
 void __keep report_panic(void)
@@ -121,11 +119,12 @@ void __keep report_panic(void)
 	pdata->reserved = 0;
 
 	/* Choose the right sp (psp or msp) based on EXC_RETURN value */
-	sp = is_frame_in_handler_stack(pdata->cm.regs[11])
-		? pdata->cm.regs[2] : pdata->cm.regs[0];
+	sp = is_frame_in_handler_stack(
+		     pdata->cm.regs[CORTEX_PANIC_REGISTER_LR]) ?
+		     pdata->cm.regs[CORTEX_PANIC_REGISTER_MSP] :
+		     pdata->cm.regs[CORTEX_PANIC_REGISTER_PSP];
 	/* If stack is valid, copy exception frame to pdata */
-	if ((sp & 3) == 0 &&
-	    sp >= CONFIG_RAM_BASE &&
+	if ((sp & 3) == 0 && sp >= CONFIG_RAM_BASE &&
 	    sp <= CONFIG_RAM_BASE + CONFIG_RAM_SIZE - 8 * sizeof(uint32_t)) {
 		const uint32_t *sregs = (const uint32_t *)sp;
 		int i;
@@ -138,50 +137,21 @@ void __keep report_panic(void)
 	panic_reboot();
 }
 
-/**
- * Default exception handler, which reports a panic.
- *
- * Declare this as a naked call so we can extract raw LR and IPSR values.
- */
-void exception_panic(void)
-{
-	/* Save registers and branch directly to panic handler */
-	asm volatile(
-		"mov r0, %[pregs]\n"
-		"mrs r1, psp\n"
-		"mrs r2, ipsr\n"
-		"mov r3, sp\n"
-		"stmia r0!, {r1-r7}\n"
-		"mov r1, r8\n"
-		"mov r2, r9\n"
-		"mov r3, r10\n"
-		"mov r4, r11\n"
-		"mov r5, lr\n"
-		"stmia r0!, {r1-r5}\n"
-		"mov sp, %[pstack]\n"
-		"bl report_panic\n" : :
-			[pregs] "r" (pdata_ptr->cm.regs),
-			[pstack] "r" (pstack_addr) :
-			/* Constraints protecting these from being clobbered.
-			 * Gcc should be using r0 & r12 for pregs and pstack. */
-			"r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9",
-			"r10", "r11", "cc", "memory"
-		);
-}
-
-#ifdef CONFIG_SOFTWARE_PANIC
 void software_panic(uint32_t reason, uint32_t info)
 {
-	__asm__("mov " STRINGIFY(SOFTWARE_PANIC_INFO_REG) ", %0\n"
-		"mov " STRINGIFY(SOFTWARE_PANIC_REASON_REG) ", %1\n"
-		"bl exception_panic\n"
-		: : "r"(info), "r"(reason));
+	__asm__("mov " STRINGIFY(
+			SOFTWARE_PANIC_INFO_REG) ", %0\n"
+						 "mov " STRINGIFY(
+							 SOFTWARE_PANIC_REASON_REG) ", %1\n"
+										    "bl exception_panic\n"
+		:
+		: "r"(info), "r"(reason));
 	__builtin_unreachable();
 }
 
 void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
 {
-	struct panic_data * const pdata = get_panic_data_write();
+	struct panic_data *const pdata = get_panic_data_write();
 	uint32_t *lregs;
 
 	lregs = pdata->cm.regs;
@@ -194,26 +164,25 @@ void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
 	pdata->arch = PANIC_ARCH_CORTEX_M;
 
 	/* Log panic cause */
-	lregs[1] = exception;
-	lregs[3] = reason;
-	lregs[4] = info;
+	lregs[CORTEX_PANIC_REGISTER_IPSR] = exception;
+	lregs[CORTEX_PANIC_REGISTER_R4] = reason;
+	lregs[CORTEX_PANIC_REGISTER_R5] = info;
 }
 
 void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception)
 {
-	struct panic_data * const pdata = panic_get_data();
+	struct panic_data *const pdata = panic_get_data();
 	uint32_t *lregs;
 
 	if (pdata && pdata->struct_version == 2) {
 		lregs = pdata->cm.regs;
-		*exception = lregs[1];
-		*reason = lregs[3];
-		*info = lregs[4];
+		*exception = lregs[CORTEX_PANIC_REGISTER_IPSR];
+		*reason = lregs[CORTEX_PANIC_REGISTER_R4];
+		*info = lregs[CORTEX_PANIC_REGISTER_R5];
 	} else {
 		*exception = *reason = *info = 0;
 	}
 }
-#endif
 
 void bus_fault_handler(void)
 {
diff --git a/core/cortex-m0/switch.S b/core/cortex-m0/switch.S
index a27d929816..4914788460 100644
--- a/core/cortex-m0/switch.S
+++ b/core/cortex-m0/switch.S
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -104,7 +104,7 @@ svc_handler_return:
 .thumb_func
 pendsv_handler:
   push {r3, lr}              @ save link register and keep stack aligned
-  ldr r0, =#CPU_SCB_ICSR     @ load CPU_SCB_ICSR's address
+  ldr r0, =CPU_SCB_ICSR      @ load CPU_SCB_ICSR's address
   movs r1, #1                @ prepare left shift (1 << 27)
   lsls r1, #27               @ shift the bit
   str r1, [r0]               @ clear pending flag
diff --git a/core/cortex-m0/task.c b/core/cortex-m0/task.c
index 3e54630ab2..315b8d6d16 100644
--- a/core/cortex-m0/task.c
+++ b/core/cortex-m0/task.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,6 +6,7 @@
 /* Task scheduling / events module for Chrome EC operating system */
 
 #include "atomic.h"
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
 #include "cpu.h"
@@ -21,10 +22,10 @@ typedef union {
 		 * Note that sp must be the first element in the task struct
 		 * for __switchto() to work.
 		 */
-		uint32_t sp;       /* Saved stack pointer for context switch */
-		uint32_t events;   /* Bitmaps of received events */
-		uint64_t runtime;  /* Time spent in task */
-		uint32_t *stack;   /* Start of stack */
+		uint32_t sp; /* Saved stack pointer for context switch */
+		atomic_t events; /* Bitmaps of received events */
+		uint64_t runtime; /* Time spent in task */
+		uint32_t *stack; /* Start of stack */
 	};
 } task_;
 
@@ -40,12 +41,10 @@ CONFIG_CTS_TASK_LIST
 #undef TASK
 
 /* Task names for easier debugging */
-#define TASK(n, r, d, s)  #n,
-static const char * const task_names[] = {
+#define TASK(n, r, d, s) #n,
+static const char *const task_names[] = {
 	"<< idle >>",
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
-	CONFIG_CTS_TASK_LIST
+	CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST CONFIG_CTS_TASK_LIST
 };
 #undef TASK
 
@@ -55,12 +54,12 @@ static uint64_t task_start_time; /* Time task scheduling started */
  * We only keep 32-bit values for exception start/end time, to avoid
  * accounting errors when we service interrupt when the timer wraps around.
  */
-static uint32_t exc_start_time;  /* Time of task->exception transition */
-static uint32_t exc_end_time;    /* Time of exception->task transition */
-static uint64_t exc_total_time;  /* Total time in exceptions */
-static uint32_t svc_calls;       /* Number of service calls */
-static uint32_t task_switches;   /* Number of times active task changed */
-static uint32_t irq_dist[CONFIG_IRQ_COUNT];  /* Distribution of IRQ calls */
+static uint32_t exc_start_time; /* Time of task->exception transition */
+static uint32_t exc_end_time; /* Time of exception->task transition */
+static uint64_t exc_total_time; /* Total time in exceptions */
+static uint32_t svc_calls; /* Number of service calls */
+static uint32_t task_switches; /* Number of times active task changed */
+static uint32_t irq_dist[CONFIG_IRQ_COUNT]; /* Distribution of IRQ calls */
 #endif
 
 extern int __task_start(int *task_stack_ready);
@@ -74,7 +73,7 @@ void __idle(void)
 		 * Wait for the next irq event.  This stops the CPU clock
 		 * (sleep / deep sleep, depending on chip config).
 		 */
-		asm("wfi");
+		cpu_enter_suspend_mode();
 	}
 }
 #endif /* !CONFIG_LOW_POWER_IDLE */
@@ -89,38 +88,33 @@ static void task_exit_trap(void)
 }
 
 /* Startup parameters for all tasks. */
-#define TASK(n, r, d, s)  {	\
-	.r0 = (uint32_t)d,	\
-	.pc = (uint32_t)r,	\
-	.stack_size = s,	\
-},
+#define TASK(n, r, d, s)           \
+	{                          \
+		.r0 = (uint32_t)d, \
+		.pc = (uint32_t)r, \
+		.stack_size = s,   \
+	},
 static const struct {
 	uint32_t r0;
 	uint32_t pc;
 	uint16_t stack_size;
 } tasks_init[] = {
 	TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
-	CONFIG_CTS_TASK_LIST
+		CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST CONFIG_CTS_TASK_LIST
 };
 #undef TASK
 
 /* Contexts for all tasks */
 static task_ tasks[TASK_ID_COUNT];
 /* Validity checks about static task invariants */
-BUILD_ASSERT(TASK_ID_COUNT <= sizeof(unsigned) * 8);
+BUILD_ASSERT(TASK_ID_COUNT <= sizeof(unsigned int) * 8);
 BUILD_ASSERT(TASK_ID_COUNT < (1 << (sizeof(task_id_t) * 8)));
 
-
 /* Stacks for all tasks */
-#define TASK(n, r, d, s)  + s
-uint8_t task_stacks[0
-		    TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
-		    CONFIG_TASK_LIST
-		    CONFIG_TEST_TASK_LIST
-		    CONFIG_CTS_TASK_LIST
-] __aligned(8);
+#define TASK(n, r, d, s) +s
+uint8_t task_stacks[0 TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
+			    CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST
+				    CONFIG_CTS_TASK_LIST] __aligned(8);
 
 #undef TASK
 
@@ -136,15 +130,15 @@ task_ *current_task = (task_ *)scratchpad;
  * can do their init within a task switching context.  The hooks task will then
  * make a call to enable all tasks.
  */
-static uint32_t tasks_ready = BIT(TASK_ID_HOOKS);
+static atomic_t tasks_ready = BIT(TASK_ID_HOOKS);
 /*
  * Initially allow only the HOOKS and IDLE task to run, regardless of ready
  * status, in order for HOOK_INIT to complete before other tasks.
  * task_enable_all_tasks() will open the flood gates.
  */
-static uint32_t tasks_enabled = BIT(TASK_ID_HOOKS) | BIT(TASK_ID_IDLE);
+static atomic_t tasks_enabled = BIT(TASK_ID_HOOKS) | BIT(TASK_ID_IDLE);
 
-static int start_called;  /* Has task swapping started */
+static int start_called; /* Has task swapping started */
 
 static inline task_ *__task_id_to_ptr(task_id_t id)
 {
@@ -161,20 +155,32 @@ void interrupt_enable(void)
 	asm("cpsie i");
 }
 
-inline int in_interrupt_context(void)
+inline bool is_interrupt_enabled(void)
+{
+	int primask;
+
+	/* Interrupts are enabled when PRIMASK bit is 0 */
+	asm("mrs %0, primask" : "=r"(primask));
+
+	return !(primask & 0x1);
+}
+
+inline bool in_interrupt_context(void)
 {
 	int ret;
-	asm("mrs %0, ipsr\n"              /* read exception number */
-	    "lsl %0, #23\n" : "=r"(ret)); /* exception bits are the 9 LSB */
-	return ret;
+	asm("mrs %0, ipsr\n" /* read exception number */
+	    : "=r"(ret));
+	return ret & GENMASK(8, 0); /* exception bits are the 9 LSB */
 }
 
+#ifdef CONFIG_TASK_PROFILING
 static inline int get_interrupt_context(void)
 {
 	int ret;
 	asm("mrs %0, ipsr\n" : "=r"(ret)); /* read exception number */
-	return ret & 0x1ff;                /* exception bits are the 9 LSB */
+	return ret & 0x1ff; /* exception bits are the 9 LSB */
 }
+#endif
 
 task_id_t task_get_current(void)
 {
@@ -185,7 +191,7 @@ task_id_t task_get_current(void)
 	return current_task - tasks;
 }
 
-uint32_t *task_get_event_bitmap(task_id_t tskid)
+atomic_t *task_get_event_bitmap(task_id_t tskid)
 {
 	task_ *tsk = __task_id_to_ptr(tskid);
 	return &tsk->events;
@@ -199,7 +205,7 @@ int task_start_called(void)
 /**
  * Scheduling system call
  */
-task_  __attribute__((noinline)) *__svc_handler(int desched, task_id_t resched)
+task_ __attribute__((noinline)) * __svc_handler(int desched, task_id_t resched)
 {
 	task_ *current, *next;
 #ifdef CONFIG_TASK_PROFILING
@@ -225,12 +231,11 @@ task_  __attribute__((noinline)) *__svc_handler(int desched, task_id_t resched)
 	current = current_task;
 
 #ifdef CONFIG_DEBUG_STACK_OVERFLOW
-	if (*current->stack != STACK_UNUSED_VALUE) {
+	if (*current->stack != STACK_UNUSED_VALUE &&
+	    task_enabled(current - tasks)) {
 		panic_printf("\n\nStack overflow in %s task!\n",
 			     task_names[current - tasks]);
-#ifdef CONFIG_SOFTWARE_PANIC
 		software_panic(PANIC_SW_STACK_OVERFLOW, current - tasks);
-#endif
 	}
 #endif
 
@@ -292,7 +297,8 @@ void task_start_irq_handler(void *excep_return)
 	 * Continue iff the tasks are ready and we are not called from another
 	 * exception (as the time accouting is done in the outer irq).
 	 */
-	if (!start_called || ((uint32_t)excep_return & 0xf) == 1)
+	if (!start_called || (((uint32_t)excep_return & EXC_RETURN_MODE_MASK) ==
+			      EXC_RETURN_MODE_HANDLER))
 		return;
 
 	exc_start_time = t;
@@ -310,7 +316,8 @@ void task_end_irq_handler(void *excep_return)
 	 * Continue iff the tasks are ready and we are not called from another
 	 * exception (as the time accouting is done in the outer irq).
 	 */
-	if (!start_called || ((uint32_t)excep_return & 0xf) == 1)
+	if (!start_called || (((uint32_t)excep_return & EXC_RETURN_MODE_MASK) ==
+			      EXC_RETURN_MODE_HANDLER))
 		return;
 
 	/* Track time in interrupts */
@@ -326,6 +333,12 @@ static uint32_t __wait_evt(int timeout_us, task_id_t resched)
 	uint32_t evt;
 	int ret __attribute__((unused));
 
+	/*
+	 * Scheduling task when interrupts are disabled will result in Forced
+	 * Hard Fault because disabling interrupt using 'cpsid i' also disables
+	 * SVCall handler (because it has configurable priority)
+	 */
+	ASSERT(is_interrupt_enabled());
 	ASSERT(!in_interrupt_context());
 
 	if (timeout_us > 0) {
@@ -334,7 +347,7 @@ static uint32_t __wait_evt(int timeout_us, task_id_t resched)
 		ret = timer_arm(deadline, me);
 		ASSERT(ret == EC_SUCCESS);
 	}
-	while (!(evt = deprecated_atomic_read_clear(&tsk->events))) {
+	while (!(evt = atomic_clear(&tsk->events))) {
 		/*
 		 * We need to ensure that the execution priority is actually
 		 * decreased after the "cpsie i" in the atomic operation above
@@ -349,23 +362,23 @@ static uint32_t __wait_evt(int timeout_us, task_id_t resched)
 	if (timeout_us > 0) {
 		timer_cancel(me);
 		/* Ensure timer event is clear, we no longer care about it */
-		deprecated_atomic_clear_bits(&tsk->events, TASK_EVENT_TIMER);
+		atomic_clear_bits(&tsk->events, TASK_EVENT_TIMER);
 	}
 	return evt;
 }
 
-uint32_t task_set_event(task_id_t tskid, uint32_t event, int wait)
+void task_set_event(task_id_t tskid, uint32_t event)
 {
 	task_ *receiver = __task_id_to_ptr(tskid);
 	ASSERT(receiver);
 
 	/* Set the event bit in the receiver message bitmap */
-	deprecated_atomic_or(&receiver->events, event);
+	atomic_or(&receiver->events, event);
 
 	/* Re-schedule if priorities have changed */
-	if (in_interrupt_context()) {
+	if (in_interrupt_context() || !is_interrupt_enabled()) {
 		/* The receiver might run again */
-		deprecated_atomic_or(&tasks_ready, 1 << tskid);
+		atomic_or(&tasks_ready, 1 << tskid);
 		if (start_called) {
 			/*
 			 * Trigger the scheduler when there's
@@ -374,22 +387,16 @@ uint32_t task_set_event(task_id_t tskid, uint32_t event, int wait)
 			CPU_SCB_ICSR = BIT(28);
 		}
 	} else {
-		if (wait) {
-			return __wait_evt(-1, tskid);
-		} else {
-			/*
-			 * We need to ensure that the execution priority is
-			 * actually decreased after the "cpsie i" in the atomic
-			 * operation above else the "svc" in the __schedule
-			 * call below will trigger a HardFault.
-			 * Use a barrier to force it at that point.
-			 */
-			asm volatile("isb");
-			__schedule(0, tskid);
-		}
+		/*
+		 * We need to ensure that the execution priority is
+		 * actually decreased after the "cpsie i" in the atomic
+		 * operation above else the "svc" in the __schedule
+		 * call below will trigger a HardFault.
+		 * Use a barrier to force it at that point.
+		 */
+		asm volatile("isb");
+		__schedule(0, tskid);
 	}
-
-	return 0;
 }
 
 uint32_t task_wait_event(int timeout_us)
@@ -420,8 +427,7 @@ uint32_t task_wait_event_mask(uint32_t event_mask, int timeout_us)
 
 	/* Re-post any other events collected */
 	if (events & ~event_mask)
-		deprecated_atomic_or(&current_task->events,
-				     events & ~event_mask);
+		atomic_or(&current_task->events, events & ~event_mask);
 
 	return events & event_mask;
 }
@@ -431,19 +437,26 @@ void task_enable_all_tasks(void)
 	/* Mark all tasks as ready and able to run. */
 	tasks_ready = tasks_enabled = BIT(TASK_ID_COUNT) - 1;
 	/* Reschedule the highest priority task. */
-	__schedule(0, 0);
+	if (is_interrupt_enabled())
+		__schedule(0, 0);
 }
 
 void task_enable_task(task_id_t tskid)
 {
-	deprecated_atomic_or(&tasks_enabled, BIT(tskid));
+	atomic_or(&tasks_enabled, BIT(tskid));
+}
+
+bool task_enabled(task_id_t tskid)
+{
+	return tasks_enabled & BIT(tskid);
 }
 
 void task_disable_task(task_id_t tskid)
 {
-	deprecated_atomic_clear_bits(&tasks_enabled, BIT(tskid));
+	atomic_clear_bits(&tasks_enabled, BIT(tskid));
 
-	if (!in_interrupt_context() && tskid == task_get_current())
+	if (!in_interrupt_context() && is_interrupt_enabled() &&
+	    tskid == task_get_current())
 		__schedule(0, 0);
 }
 
@@ -500,7 +513,7 @@ void mutex_lock(struct mutex *mtx)
 	uint32_t id = 1 << task_get_current();
 
 	ASSERT(id != TASK_ID_INVALID);
-	deprecated_atomic_or(&mtx->waiters, id);
+	atomic_or(&mtx->waiters, id);
 
 	while (1) {
 		/* Try to get the lock (set 2 into the lock field) */
@@ -514,7 +527,7 @@ void mutex_lock(struct mutex *mtx)
 	mtx->lock = 2;
 	__asm__ __volatile__("cpsie i");
 
-	deprecated_atomic_clear_bits(&mtx->waiters, id);
+	atomic_clear_bits(&mtx->waiters, id);
 }
 
 void mutex_unlock(struct mutex *mtx)
@@ -536,11 +549,11 @@ void mutex_unlock(struct mutex *mtx)
 		waiters &= ~BIT(id);
 
 		/* Somebody is waiting on the mutex */
-		task_set_event(id, TASK_EVENT_MUTEX, 0);
+		task_set_event(id, TASK_EVENT_MUTEX);
 	}
 
 	/* Ensure no event is remaining from mutex wake-up */
-	deprecated_atomic_clear_bits(&tsk->events, TASK_EVENT_MUTEX);
+	atomic_clear_bits(&tsk->events, TASK_EVENT_MUTEX);
 }
 
 void task_print_list(void)
@@ -550,7 +563,7 @@ void task_print_list(void)
 	ccputs("Task Ready Name         Events      Time (s)  StkUsed\n");
 
 	for (i = 0; i < TASK_ID_COUNT; i++) {
-		char is_ready = (tasks_ready & (1<<i)) ? 'R' : ' ';
+		char is_ready = ((uint32_t)tasks_ready & BIT(i)) ? 'R' : ' ';
 		uint32_t *sp;
 
 		int stackused = tasks_init[i].stack_size;
@@ -561,13 +574,13 @@ void task_print_list(void)
 			stackused -= sizeof(uint32_t);
 
 		ccprintf("%4d %c %-16s %08x %11.6lld  %3d/%3d\n", i, is_ready,
-			 task_names[i], tasks[i].events, tasks[i].runtime,
+			 task_names[i], (int)tasks[i].events, tasks[i].runtime,
 			 stackused, tasks_init[i].stack_size);
 		cflush();
 	}
 }
 
-int command_task_info(int argc, char **argv)
+static int command_task_info(int argc, const char **argv)
 {
 #ifdef CONFIG_TASK_PROFILING
 	int total = 0;
@@ -596,25 +609,22 @@ int command_task_info(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(taskinfo, command_task_info,
-			NULL,
-			"Print task info");
+DECLARE_CONSOLE_COMMAND(taskinfo, command_task_info, NULL, "Print task info");
 
 #ifdef CONFIG_CMD_TASKREADY
-static int command_task_ready(int argc, char **argv)
+static int command_task_ready(int argc, const char **argv)
 {
 	if (argc < 2) {
-		ccprintf("tasks_ready: 0x%08x\n", tasks_ready);
+		ccprintf("tasks_ready: 0x%08x\n", (int)tasks_ready);
 	} else {
 		tasks_ready = strtoi(argv[1], NULL, 16);
-		ccprintf("Setting tasks_ready to 0x%08x\n", tasks_ready);
+		ccprintf("Setting tasks_ready to 0x%08x\n", (int)tasks_ready);
 		__schedule(0, 0);
 	}
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(taskready, command_task_ready,
-			"[setmask]",
+DECLARE_CONSOLE_COMMAND(taskready, command_task_ready, "[setmask]",
 			"Print/set ready tasks");
 #endif
 
@@ -640,10 +650,10 @@ void task_pre_init(void)
 		tasks[i].sp = (uint32_t)sp;
 
 		/* Initial context on stack (see __switchto()) */
-		sp[8] = tasks_init[i].r0;           /* r0 */
-		sp[13] = (uint32_t)task_exit_trap;  /* lr */
-		sp[14] = tasks_init[i].pc;          /* pc */
-		sp[15] = 0x01000000;                /* psr */
+		sp[8] = tasks_init[i].r0; /* r0 */
+		sp[13] = (uint32_t)task_exit_trap; /* lr */
+		sp[14] = tasks_init[i].pc; /* pc */
+		sp[15] = 0x01000000; /* psr */
 
 		/* Fill unused stack; also used to detect stack overflow. */
 		for (sp = stack_next; sp < (uint32_t *)tasks[i].sp; sp++)
diff --git a/core/cortex-m0/thumb_case.S b/core/cortex-m0/thumb_case.S
index 5628361a94..9148a33427 100644
--- a/core/cortex-m0/thumb_case.S
+++ b/core/cortex-m0/thumb_case.S
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/cortex-m0/toolchain.mk b/core/cortex-m0/toolchain.mk
new file mode 100644
index 0000000000..6b5f07ccf6
--- /dev/null
+++ b/core/cortex-m0/toolchain.mk
@@ -0,0 +1,15 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+ifeq ($(cc-name),gcc)
+# coreboot sdk
+CROSS_COMPILE_ARM_DEFAULT:=/opt/coreboot-sdk/bin/arm-eabi-
+else
+# llvm sdk
+CROSS_COMPILE_ARM_DEFAULT:=arm-none-eabi-
+endif
+
+$(call set-option,CROSS_COMPILE,\
+	$(CROSS_COMPILE_arm),\
+	$(CROSS_COMPILE_ARM_DEFAULT))
diff --git a/core/cortex-m0/vecttable.c b/core/cortex-m0/vecttable.c
index b1eaa957e0..050a7d318a 100644
--- a/core/cortex-m0/vecttable.c
+++ b/core/cortex-m0/vecttable.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -7,13 +7,14 @@
 
 #ifndef ___INIT
 #define ___INIT
-#include <stddef.h>
-#include <stdint.h>
-
+#include "compiler.h"
 #include "config.h"
 #include "panic-internal.h"
 #include "task.h"
-#endif  /* __INIT */
+
+#include <stddef.h>
+#include <stdint.h>
+#endif /* __INIT */
 
 typedef void (*func)(void);
 
@@ -30,7 +31,7 @@ void __attribute__((naked)) default_handler(void)
 	 * restricting the relative placement of default_handler and
 	 * exception_panic.
 	 */
-	asm volatile("bx %0\n" : : "r" (exception_panic));
+	asm volatile("bx %0\n" : : "r"(exception_panic));
 }
 
 #define table(x) x
@@ -38,8 +39,8 @@ void __attribute__((naked)) default_handler(void)
 /* Note: the alias target must be defined in this translation unit */
 #define weak_with_default __attribute__((used, weak, alias("default_handler")))
 
-#define vec(name) extern void weak_with_default name ## _handler(void);
-#define irq(num) vec(irq_ ## num)
+#define vec(name) extern void weak_with_default name##_handler(void);
+#define irq(num) vec(irq_##num)
 
 #define item(name) extern void name(void);
 #define null
@@ -47,12 +48,6 @@ void __attribute__((naked)) default_handler(void)
 extern void stack_end(void); /* not technically correct, it's just a pointer */
 extern void reset(void);
 
-#pragma GCC diagnostic push
-#if __GNUC__ >= 8
-#pragma GCC diagnostic ignored "-Wattribute-alias"
-#endif
-#pragma GCC diagnostic pop
-
 #endif /* PASS 1 */
 
 #if PASS == 2
@@ -69,65 +64,37 @@ extern void reset(void);
  */
 #define IRQ_UNUSED_OFFSET 8
 
-#define table(x) func vectors[] __attribute__((section(".text.vecttable,\"a\" @"))) = { x[IRQ_UNUSED_OFFSET] = null };
+/* Disable warning that "initializer overrides prior initialization of this
+ * subobject", since we are explicitly doing this to handle the unused IRQs.
+ */
+DISABLE_CLANG_WARNING("-Winitializer-overrides")
+
+#define table(x)                             \
+	const func vectors[] __attribute__(( \
+		section(".text.vecttable"))) = { x[IRQ_UNUSED_OFFSET] = null }
 
-#define vec(name) name ## _handler,
-#define irq(num) [num < CONFIG_IRQ_COUNT ? num + IRQ_OFFSET : IRQ_UNUSED_OFFSET] = vec(irq_ ## num)
+#define vec(name) name##_handler,
+#define irq(num)                                                          \
+	[num < CONFIG_IRQ_COUNT ? num + IRQ_OFFSET : IRQ_UNUSED_OFFSET] = \
+		vec(irq_##num)
 
 #define item(name) name,
 #define null (void *)0,
 #endif /* PASS 2 */
 
-table(
-	item(stack_end)
-	item(reset)
-	vec(nmi)
-	vec(hard_fault)
-	vec(mpu_fault)
-	vec(bus_fault)
-	vec(usage_fault)
-	null
-	null
-	null
-	null
-	vec(svc)
-	vec(debug)
-	null
-	vec(pendsv)
-	vec(sys_tick)
-	irq(0)
-	irq(1)
-	irq(2)
-	irq(3)
-	irq(4)
-	irq(5)
-	irq(6)
-	irq(7)
-	irq(8)
-	irq(9)
-	irq(10)
-	irq(11)
-	irq(12)
-	irq(13)
-	irq(14)
-	irq(15)
-	irq(16)
-	irq(17)
-	irq(18)
-	irq(19)
-	irq(20)
-	irq(21)
-	irq(22)
-	irq(23)
-	irq(24)
-	irq(25)
-	irq(26)
-	irq(27)
-	irq(28)
-	irq(29)
-	irq(30)
-	irq(31)
-)
+table(item(stack_end) item(reset) vec(nmi) vec(hard_fault) vec(mpu_fault) vec(
+	bus_fault) vec(usage_fault) null null null null vec(svc) vec(debug)
+	      null vec(pendsv) vec(sys_tick) irq(0) irq(1) irq(2) irq(3) irq(4)
+		      irq(5) irq(6) irq(7) irq(8) irq(9) irq(10) irq(11) irq(12)
+			      irq(13) irq(14) irq(15) irq(16) irq(17) irq(18)
+				      irq(19) irq(20) irq(21) irq(22) irq(23)
+					      irq(24) irq(25) irq(26) irq(27)
+						      irq(28) irq(29) irq(30)
+							      irq(31));
+
+#if PASS == 2
+ENABLE_CLANG_WARNING("-Winitializer-overrides")
+#endif
 
 #if PASS == 1
 #undef PASS
diff --git a/core/cortex-m0/watchdog.c b/core/cortex-m0/watchdog.c
index 20fcc2ab35..0b5a038168 100644
--- a/core/cortex-m0/watchdog.c
+++ b/core/cortex-m0/watchdog.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,6 +11,14 @@
 #include "timer.h"
 #include "watchdog.h"
 
+/*
+ * As defined by Armv7-M Reference Manual B1.5.6 "Exception Entry Behavior",
+ * the structure of the saved context on the stack is:
+ * r0, r1, r2, r3, r12, lr, pc, psr, ...
+ */
+#define STACK_IDX_REG_LR 5
+#define STACK_IDX_REG_PC 6
+
 void watchdog_trace(uint32_t excep_lr, uint32_t excep_sp)
 {
 	uint32_t psp;
@@ -26,13 +34,11 @@ void watchdog_trace(uint32_t excep_lr, uint32_t excep_sp)
 	}
 
 	/* Log PC. If we were in task context, log task id too. */
-#ifdef CONFIG_SOFTWARE_PANIC
-	panic_set_reason(PANIC_SW_WATCHDOG, stack[6],
+	panic_set_reason(PANIC_SW_WATCHDOG, stack[STACK_IDX_REG_PC],
 			 (excep_lr & 0xf) == 1 ? 0xff : task_get_current());
-#endif
 
 	panic_printf("### WATCHDOG PC=%08x / LR=%08x / pSP=%08x ",
-		     stack[6], stack[5], psp);
+		     stack[STACK_IDX_REG_PC], stack[STACK_IDX_REG_LR], psp);
 	if ((excep_lr & 0xf) == 1)
 		panic_puts("(exc) ###\n");
 	else
diff --git a/core/host/atomic.h b/core/host/atomic.h
index 7f2e0ba16f..0d27e1bc6f 100644
--- a/core/host/atomic.h
+++ b/core/host/atomic.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,39 +8,36 @@
 #ifndef __CROS_EC_ATOMIC_H
 #define __CROS_EC_ATOMIC_H
 
+#include "atomic_t.h"
 #include "common.h"
 
-/*
- * The atomic_* functions are marked as deprecated as a part of the process of
- * transaction to Zephyr compatible atomic functions. These prefixes will be
- * removed in the following patches. Please see b:169151160 for more details.
- */
+static inline atomic_val_t atomic_clear_bits(atomic_t *addr, atomic_val_t bits)
+{
+	return __atomic_fetch_and(addr, ~bits, __ATOMIC_SEQ_CST);
+}
 
-static inline void deprecated_atomic_clear_bits(uint32_t volatile *addr,
-						uint32_t bits)
+static inline atomic_val_t atomic_or(atomic_t *addr, atomic_val_t bits)
 {
-	__sync_and_and_fetch(addr, ~bits);
+	return __atomic_fetch_or(addr, bits, __ATOMIC_SEQ_CST);
 }
 
-static inline void deprecated_atomic_or(uint32_t volatile *addr, uint32_t bits)
+static inline atomic_val_t atomic_add(atomic_t *addr, atomic_val_t value)
 {
-	__sync_or_and_fetch(addr, bits);
+	return __atomic_fetch_add(addr, value, __ATOMIC_SEQ_CST);
 }
 
-static inline void deprecated_atomic_add(uint32_t volatile *addr,
-					 uint32_t value)
+static inline atomic_val_t atomic_sub(atomic_t *addr, atomic_val_t value)
 {
-	__sync_add_and_fetch(addr, value);
+	return __atomic_fetch_sub(addr, value, __ATOMIC_SEQ_CST);
 }
 
-static inline void deprecated_atomic_sub(uint32_t volatile *addr,
-					 uint32_t value)
+static inline atomic_val_t atomic_clear(atomic_t *addr)
 {
-	__sync_sub_and_fetch(addr, value);
+	return __atomic_exchange_n(addr, 0, __ATOMIC_SEQ_CST);
 }
 
-static inline uint32_t deprecated_atomic_read_clear(uint32_t volatile *addr)
+static inline atomic_val_t atomic_and(atomic_t *addr, atomic_val_t bits)
 {
-	return __sync_fetch_and_and(addr, 0);
+	return __atomic_fetch_and(addr, bits, __ATOMIC_SEQ_CST);
 }
-#endif  /* __CROS_EC_ATOMIC_H */
+#endif /* __CROS_EC_ATOMIC_H */
diff --git a/core/host/build.mk b/core/host/build.mk
index 503aa5538a..3995e7e4e4 100644
--- a/core/host/build.mk
+++ b/core/host/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
+# Copyright 2013 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/core/host/cpu.h b/core/host/cpu.h
index d990e06afa..f63e0b9d23 100644
--- a/core/host/cpu.h
+++ b/core/host/cpu.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,6 +8,8 @@
 #ifndef __CROS_EC_CPU_H
 #define __CROS_EC_CPU_H
 
-static inline void cpu_init(void) { }
+static inline void cpu_init(void)
+{
+}
 
 #endif /* __CROS_EC_CPU_H */
diff --git a/core/host/disabled.c b/core/host/disabled.c
index 759c215ebd..8f05e5e1d6 100644
--- a/core/host/disabled.c
+++ b/core/host/disabled.c
@@ -1,10 +1,13 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Disabled functions */
 
-#define DISABLED(proto) proto { }
+#define DISABLED(proto) \
+	proto           \
+	{               \
+	}
 
 DISABLED(void clock_init(void));
diff --git a/core/host/host_exe.lds b/core/host/host_exe.lds
index fbf7b56351..05943b408a 100644
--- a/core/host/host_exe.lds
+++ b/core/host/host_exe.lds
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -65,6 +65,10 @@ SECTIONS {
 		*(.rodata.HOOK_CHIPSET_SHUTDOWN_COMPLETE)
 		__hooks_chipset_shutdown_complete_end = .;
 
+		__hooks_chipset_hard_off = .;
+		KEEP(*(.rodata.HOOK_CHIPSET_HARD_OFF))
+		__hooks_chipset_hard_off_end = .;
+
 		__hooks_chipset_reset = .;
 		*(.rodata.HOOK_CHIPSET_RESET)
 		__hooks_chipset_reset_end = .;
@@ -81,6 +85,10 @@ SECTIONS {
 		KEEP(*(.rodata.HOOK_TABLET_MODE_CHANGE))
 		__hooks_tablet_mode_change_end = .;
 
+		__hooks_body_detect_change = .;
+		KEEP(*(.rodata.HOOK_BODY_DETECT_CHANGE))
+		__hooks_body_detect_change_end = .;
+
 		__hooks_base_attached_change = .;
 		KEEP(*(.rodata.HOOK_BASE_ATTACHED_CHANGE))
 		__hooks_base_attached_change_end = .;
@@ -109,6 +117,10 @@ SECTIONS {
 		KEEP(*(.rodata.HOOK_USB_PD_CONNECT))
 		__hooks_usb_pd_connect_end = .;
 
+		__hooks_power_supply_change = .;
+		KEEP(*(.rodata.HOOK_POWER_SUPPLY_CHANGE))
+		__hooks_power_supply_change_end = .;
+
 		__deferred_funcs = .;
 		*(.rodata.deferred)
 		__deferred_funcs_end = .;
diff --git a/core/host/host_task.h b/core/host/host_task.h
index 30cd2ff594..e79111f6f4 100644
--- a/core/host/host_task.h
+++ b/core/host/host_task.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,10 +8,10 @@
 #ifndef __CROS_EC_HOST_TASK_H
 #define __CROS_EC_HOST_TASK_H
 
-#include <pthread.h>
-
 #include "task.h"
 
+#include <pthread.h>
+
 /**
  * Returns the thread corresponding to the task.
  */
@@ -34,4 +34,4 @@ void task_register_interrupt(void);
  */
 pid_t getpid(void);
 
-#endif  /* __CROS_EC_HOST_TASK_H */
+#endif /* __CROS_EC_HOST_TASK_H */
diff --git a/core/host/irq_handler.h b/core/host/irq_handler.h
index 9ff5d9979c..8bbf596a57 100644
--- a/core/host/irq_handler.h
+++ b/core/host/irq_handler.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,15 +15,16 @@
  * Macro to connect the interrupt handler "routine" to the irq number "irq" and
  * ensure it is enabled in the interrupt controller with the right priority.
  */
-#define DECLARE_IRQ(irq, routine, priority)                     \
-	void IRQ_HANDLER(irq)(void)				\
-	{							\
-		void *ret = __builtin_return_address(0);	\
-		task_start_irq_handler(ret);			\
-		routine();					\
-		task_resched_if_needed(ret);			\
-	}							\
-	const struct irq_priority __keep IRQ_PRIORITY(irq)	\
-	__attribute__((section(".rodata.irqprio")))		\
-			= {irq, priority}
-#endif  /* __CROS_EC_IRQ_HANDLER_H */
+#define DECLARE_IRQ(irq, routine, priority)                          \
+	static void __keep routine(void);                            \
+	void IRQ_HANDLER(irq)(void)                                  \
+	{                                                            \
+		void *ret = __builtin_return_address(0);             \
+		task_start_irq_handler(ret);                         \
+		routine();                                           \
+		task_resched_if_needed(ret);                         \
+	}                                                            \
+	const struct irq_priority __keep IRQ_PRIORITY(irq)           \
+		__attribute__((section(".rodata.irqprio"))) = { irq, \
+								priority }
+#endif /* __CROS_EC_IRQ_HANDLER_H */
diff --git a/core/host/main.c b/core/host/main.c
index e773713b2a..1af5fa928c 100644
--- a/core/host/main.c
+++ b/core/host/main.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,7 +19,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 const char *__prog_name;
 
@@ -40,7 +40,7 @@ static int test_main(void)
 
 	register_test_end_hook();
 
-	flash_pre_init();
+	crec_flash_pre_init();
 	system_pre_init();
 	system_common_pre_init();
 
@@ -85,7 +85,7 @@ int LLVMFuzzerTestOneInput(const uint8_t *data, size_t size)
 	 * We lose the program name as LLVM fuzzer takes over main function:
 	 * make up one.
 	 */
-	static const char *name = STRINGIFY(PROJECT)".exe";
+	static const char *name = STRINGIFY(PROJECT) ".exe";
 
 	if (!initialized) {
 		__prog_name = name;
diff --git a/core/host/panic.c b/core/host/panic.c
index 7b0829989d..0dd00ac604 100644
--- a/core/host/panic.c
+++ b/core/host/panic.c
@@ -1,18 +1,23 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "config.h"
+#include "panic.h"
+#include "stack_trace.h"
+
+#include <assert.h>
+#include <stdint.h>
 #include <stdio.h>
 #include <stdlib.h>
-
-#include "stack_trace.h"
+#include <string.h>
 
 void panic_assert_fail(const char *msg, const char *func, const char *fname,
 		       int linenum)
 {
-	fprintf(stderr, "ASSERTION FAIL: %s:%d:%s - %s\n",
-		fname, linenum, func, msg);
+	fprintf(stderr, "ASSERTION FAIL: %s:%d:%s - %s\n", fname, linenum, func,
+		msg);
 	task_dump_trace();
 
 	puts("Fail!"); /* Inform test runner */
@@ -20,3 +25,34 @@ void panic_assert_fail(const char *msg, const char *func, const char *fname,
 
 	exit(1);
 }
+
+void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
+{
+	struct panic_data *const pdata = panic_get_data();
+
+	assert(pdata);
+	memset(pdata, 0, CONFIG_PANIC_DATA_SIZE);
+	pdata->magic = PANIC_DATA_MAGIC;
+	pdata->struct_size = CONFIG_PANIC_DATA_SIZE;
+	pdata->struct_version = 2;
+	pdata->arch = PANIC_ARCH_X86;
+
+	pdata->x86.vector = reason;
+	pdata->x86.error_code = info;
+	pdata->x86.eflags = exception;
+}
+
+void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception)
+{
+	struct panic_data *const pdata = panic_get_data();
+
+	assert(pdata);
+	assert(pdata->struct_version == 2);
+
+	if (reason)
+		*reason = pdata->x86.vector;
+	if (info)
+		*info = pdata->x86.error_code;
+	if (exception)
+		*exception = pdata->x86.eflags;
+}
diff --git a/core/host/stack_trace.c b/core/host/stack_trace.c
index adef66dd44..4f4ab380d9 100644
--- a/core/host/stack_trace.c
+++ b/core/host/stack_trace.c
@@ -1,16 +1,17 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <execinfo.h>
+#include "host_task.h"
+#include "host_test.h"
+#include "timer.h"
+
 #include <signal.h>
 #include <stdio.h>
 #include <stdlib.h>
 
-#include "host_task.h"
-#include "host_test.h"
-#include "timer.h"
+#include <execinfo.h>
 
 #define SIGNAL_TRACE_DUMP SIGTERM
 #define MAX_TRACE 30
@@ -40,13 +41,17 @@ static void __attribute__((noinline)) _task_dump_trace_impl(int offset)
 	int i, nb;
 
 	sz = backtrace(trace, MAX_TRACE);
+	if (sz < offset) {
+		fprintf(stderr, "Can't print backtrace: %ld < %d\n", sz,
+			offset);
+		return;
+	}
 	messages = backtrace_symbols(trace + offset, sz - offset);
 
 	for (i = 0; i < sz - offset; ++i) {
 		fprintf(stderr, "#%-2d %s\n", i, messages[i]);
-		/* %p is correct (as opposed to %pP) since this is the host */
-		sprintf(buf, "addr2line %p -e %s",
-			trace[i + offset], __get_prog_name());
+		sprintf(buf, "addr2line %p -e %s", trace[i + offset],
+			__get_prog_name());
 		file = popen(buf, "r");
 		if (file) {
 			nb = fread(buf, 1, sizeof(buf) - 1, file);
@@ -77,8 +82,8 @@ static void __attribute__((noinline)) _task_dump_trace_dispatch(int sig)
 	} else if (in_interrupt_context()) {
 		fprintf(stderr, "Stack trace of ISR:\n");
 	} else {
-		fprintf(stderr, "Stack trace of task %d (%s):\n",
-				running, task_get_name(running));
+		fprintf(stderr, "Stack trace of task %d (%s):\n", running,
+			task_get_name(running));
 	}
 
 	if (need_dispatch) {
diff --git a/core/host/task.c b/core/host/task.c
index ae5e525303..36996784af 100644
--- a/core/host/task.c
+++ b/core/host/task.c
@@ -1,19 +1,10 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Task scheduling / events module for Chrome EC operating system */
 
-#include <malloc.h>
-#include <pthread.h>
-#include <semaphore.h>
-#include <signal.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
 #include "atomic.h"
 #include "common.h"
 #include "console.h"
@@ -23,12 +14,22 @@
 #include "test_util.h"
 #include "timer.h"
 
+#include <signal.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <malloc.h>
+#include <pthread.h>
+#include <semaphore.h>
+
 #define SIGNAL_INTERRUPT SIGUSR1
 
 struct emu_task_t {
 	pthread_t thread;
 	pthread_cond_t resume;
-	uint32_t event;
+	atomic_t event;
 	timestamp_t wake_time;
 	uint8_t started;
 };
@@ -47,7 +48,7 @@ static int task_started;
 static sem_t interrupt_sem;
 static pthread_mutex_t interrupt_lock;
 static pthread_t interrupt_thread;
-static int in_interrupt;
+static bool in_interrupt;
 static int interrupt_disabled;
 static void (*pending_isr)(void);
 static int generator_sleeping;
@@ -66,6 +67,7 @@ CONFIG_CTS_TASK_LIST
 #undef TASK
 
 /* usleep that uses OS functions, instead of emulated timer. */
+/* LCOV_EXCL_START */
 void _usleep(int usec)
 {
 	struct timespec req;
@@ -75,6 +77,7 @@ void _usleep(int usec)
 
 	nanosleep(&req, NULL);
 }
+/* LCOV_EXCL_STOP */
 
 /* msleep that uses OS functions, instead of emulated timer. */
 void _msleep(int msec)
@@ -94,22 +97,18 @@ void _run_test(void *d)
 	run_test(0, NULL);
 }
 
-#define TASK(n, r, d, s) {r, d},
+#define TASK(n, r, d, s) { r, d },
 const struct task_args task_info[TASK_ID_COUNT] = {
-	{__idle, NULL},
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
-	CONFIG_CTS_TASK_LIST
-	{_run_test, NULL},
+	{ __idle, NULL },
+	CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST CONFIG_CTS_TASK_LIST{ _run_test,
+								     NULL },
 };
 #undef TASK
 
 #define TASK(n, r, d, s) #n,
-static const char * const task_names[] = {
+static const char *const task_names[] = {
 	"<< idle >>",
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
-	CONFIG_CTS_TASK_LIST
+	CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST CONFIG_CTS_TASK_LIST
 	"<< test runner >>",
 };
 #undef TASK
@@ -119,31 +118,36 @@ void task_pre_init(void)
 	/* Nothing */
 }
 
-int in_interrupt_context(void)
+bool in_interrupt_context(void)
 {
-	return !!in_interrupt;
+	return in_interrupt;
 }
 
-void interrupt_disable(void)
+test_mockable void interrupt_disable(void)
 {
 	pthread_mutex_lock(&interrupt_lock);
 	interrupt_disabled = 1;
 	pthread_mutex_unlock(&interrupt_lock);
 }
 
-void interrupt_enable(void)
+test_mockable void interrupt_enable(void)
 {
 	pthread_mutex_lock(&interrupt_lock);
 	interrupt_disabled = 0;
 	pthread_mutex_unlock(&interrupt_lock);
 }
 
+inline bool is_interrupt_enabled(void)
+{
+	return !interrupt_disabled;
+}
+
 static void _task_execute_isr(int sig)
 {
-	in_interrupt = 1;
+	in_interrupt = true;
 	pending_isr();
 	sem_post(&interrupt_sem);
-	in_interrupt = 0;
+	in_interrupt = false;
 }
 
 void task_register_interrupt(void)
@@ -161,7 +165,7 @@ void task_trigger_test_interrupt(void (*isr)(void))
 		return;
 	}
 
-	/* Suspend current task and excute ISR */
+	/* Suspend current task and execute ISR */
 	pending_isr = isr;
 	if (task_started) {
 		pthread_kill(tasks[running_task_id].thread, SIGNAL_INTERRUPT);
@@ -172,14 +176,16 @@ void task_trigger_test_interrupt(void (*isr)(void))
 
 	/* Wait for ISR to complete */
 	sem_wait(&interrupt_sem);
+	/* LCOV_EXCL_START */
 	while (in_interrupt)
 		_usleep(10);
+	/* LCOV_EXCL_STOP */
 	pending_isr = NULL;
 
 	pthread_mutex_unlock(&interrupt_lock);
 }
 
-void interrupt_generator_udelay(unsigned us)
+void interrupt_generator_udelay(unsigned int us)
 {
 	generator_sleep_deadline.val = get_time().val + us;
 	generator_sleeping = 1;
@@ -198,15 +204,12 @@ pthread_t task_get_thread(task_id_t tskid)
 	return tasks[tskid].thread;
 }
 
-uint32_t task_set_event(task_id_t tskid, uint32_t event, int wait)
+void task_set_event(task_id_t tskid, uint32_t event)
 {
-	deprecated_atomic_or(&tasks[tskid].event, event);
-	if (wait)
-		return task_wait_event(-1);
-	return 0;
+	atomic_or(&tasks[tskid].event, event);
 }
 
-uint32_t *task_get_event_bitmap(task_id_t tskid)
+atomic_t *task_get_event_bitmap(task_id_t tskid)
 {
 	return &tasks[tskid].event;
 }
@@ -224,7 +227,7 @@ uint32_t task_wait_event(int timeout_us)
 	pthread_cond_wait(&tasks[tid].resume, &run_lock);
 
 	/* Resume */
-	ret = deprecated_atomic_read_clear(&tasks[tid].event);
+	ret = atomic_clear(&tasks[tid].event);
 	pthread_mutex_unlock(&interrupt_lock);
 	return ret;
 }
@@ -252,8 +255,8 @@ uint32_t task_wait_event_mask(uint32_t event_mask, int timeout_us)
 
 	/* Re-post any other events collected */
 	if (events & ~event_mask)
-		deprecated_atomic_or(&tasks[task_get_current()].event,
-				     events & ~event_mask);
+		atomic_or(&tasks[task_get_current()].event,
+			  events & ~event_mask);
 
 	return events & event_mask;
 }
@@ -286,7 +289,7 @@ void mutex_unlock(struct mutex *mtx)
 	for (v = 31; v >= 0; --v)
 		if ((1ul << v) & mtx->waiters) {
 			mtx->waiters &= ~(1ul << v);
-			task_set_event(v, TASK_EVENT_MUTEX, 0);
+			task_set_event(v, TASK_EVENT_MUTEX);
 			break;
 		}
 }
@@ -313,14 +316,13 @@ void task_print_list(void)
 	}
 }
 
-int command_task_info(int argc, char **argv)
+static int command_task_info(int argc, const char **argv)
 {
 	task_print_list();
 
 	return EC_SUCCESS;
 }
-DECLARE_SAFE_CONSOLE_COMMAND(taskinfo, command_task_info,
-			     NULL,
+DECLARE_SAFE_CONSOLE_COMMAND(taskinfo, command_task_info, NULL,
 			     "Print task info");
 
 static void _wait_for_task_started(int can_sleep)
@@ -513,8 +515,8 @@ int task_start(void)
 	 */
 	pthread_mutex_lock(&interrupt_lock);
 
-	pthread_create(&interrupt_thread, NULL,
-		       _task_int_generator_start, NULL);
+	pthread_create(&interrupt_thread, NULL, _task_int_generator_start,
+		       NULL);
 
 	/*
 	 * Tell the hooks task to continue so that it can call back to enable
@@ -551,7 +553,6 @@ static void task_enable_all_tasks_callback(void)
 		pthread_mutex_unlock(&interrupt_lock);
 		pthread_cond_wait(&scheduler_cond, &run_lock);
 	}
-
 }
 
 void task_enable_all_tasks(void)
diff --git a/core/host/timer.c b/core/host/timer.c
index c99c002533..03c1f70018 100644
--- a/core/host/timer.c
+++ b/core/host/timer.c
@@ -1,22 +1,23 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Timer module */
 
-#include <stdint.h>
-#include <stdio.h>
-
+#include "builtin/assert.h"
 #include "task.h"
 #include "test_util.h"
 #include "timer.h"
 #include "util.h"
 
+#include <stdint.h>
+#include <stdio.h>
+
 static timestamp_t boot_time;
 static int time_set;
 
-void usleep(unsigned us)
+void usleep(unsigned int us)
 {
 	if (!task_start_called() || task_get_current() == TASK_ID_INVALID) {
 		udelay(us);
@@ -62,7 +63,7 @@ void force_time(timestamp_t ts)
 	time_set = 1;
 }
 
-void udelay(unsigned us)
+void udelay(unsigned int us)
 {
 	timestamp_t deadline;
 
@@ -90,6 +91,13 @@ int timestamp_expired(timestamp_t deadline, const timestamp_t *now)
 
 void timer_init(void)
 {
-	if (!time_set)
-		boot_time = _get_time();
+	if (!time_set) {
+		/*
+		 * Start the timer just before the 64-bit rollover to try
+		 * and catch 32-bit rollover/truncation bugs.
+		 */
+		timestamp_t ts = { .val = 0xFFFFFFF0 };
+
+		force_time(ts);
+	}
 }
diff --git a/core/host/toolchain.mk b/core/host/toolchain.mk
new file mode 100644
index 0000000000..9575559eb4
--- /dev/null
+++ b/core/host/toolchain.mk
@@ -0,0 +1,11 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CROSS_COMPILE_HOST_DEFAULT:=x86_64-pc-linux-gnu-
+CMAKE_SYSTEM_PROCESSOR ?= x86_64
+OPENSSL_NO_ASM ?= 0
+
+$(call set-option,CROSS_COMPILE,\
+	$(CROSS_COMPILE_host),\
+	$(CROSS_COMPILE_HOST_DEFAULT))
diff --git a/core/minute-ia/atomic.h b/core/minute-ia/atomic.h
index 598fc5b3ed..e722d799c8 100644
--- a/core/minute-ia/atomic.h
+++ b/core/minute-ia/atomic.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,87 +8,61 @@
 #ifndef __CROS_EC_ATOMIC_H
 #define __CROS_EC_ATOMIC_H
 
+#include "atomic_t.h"
 #include "common.h"
 #include "util.h"
 
-#define ATOMIC_OP(asm_op, a, v) do {		\
-	__asm__ __volatile__ (			\
-		ASM_LOCK_PREFIX #asm_op " %1, %0\n"	\
-		: "+m" (*a)			\
-		: "ir" (v)			\
-		: "memory");			\
-} while (0)
-
 static inline int bool_compare_and_swap_u32(uint32_t *var, uint32_t old_value,
-		uint32_t new_value)
+					    uint32_t new_value)
 {
 	uint32_t _old_value = old_value;
 
 	__asm__ __volatile__(ASM_LOCK_PREFIX "cmpxchgl %2, %1"
-			     : "=a" (old_value), "+m" (*var)
-			     : "r" (new_value), "0" (old_value)
+			     : "=a"(old_value), "+m"(*var)
+			     : "r"(new_value), "0"(old_value)
 			     : "memory");
 
 	return (_old_value == old_value);
 }
 
-/*
- * The atomic_* functions are marked as deprecated as a part of the process of
- * transaction to Zephyr compatible atomic functions. These prefixes will be
- * removed in the following patches. Please see b:169151160 for more details.
- */
-
-static inline void deprecated_atomic_or_u8(uint8_t *addr, uint8_t bits)
+static inline atomic_val_t atomic_or_u8(uint8_t *addr, uint8_t bits)
 {
-	ATOMIC_OP(or, addr, bits);
+	return __atomic_fetch_or(addr, bits, __ATOMIC_SEQ_CST);
 }
 
-static inline void deprecated_atomic_and_u8(uint8_t *addr, uint8_t bits)
+static inline atomic_val_t atomic_and_u8(uint8_t *addr, uint8_t bits)
 {
-	ATOMIC_OP(and, addr, bits);
+	return __atomic_fetch_and(addr, bits, __ATOMIC_SEQ_CST);
 }
 
-static inline void deprecated_atomic_clear_bits(uint32_t volatile *addr,
-						uint32_t bits)
+static inline atomic_val_t atomic_clear_bits(atomic_t *addr, atomic_val_t bits)
 {
-	ATOMIC_OP(andl, addr, ~bits);
+	return __atomic_fetch_and(addr, ~bits, __ATOMIC_SEQ_CST);
 }
 
-static inline void deprecated_atomic_or(uint32_t volatile *addr, uint32_t bits)
+static inline atomic_val_t atomic_or(atomic_t *addr, atomic_val_t bits)
 {
-	ATOMIC_OP(orl, addr, bits);
+	return __atomic_fetch_or(addr, bits, __ATOMIC_SEQ_CST);
 }
 
-static inline void deprecated_atomic_add(uint32_t volatile *addr,
-					 uint32_t value)
+static inline atomic_val_t atomic_add(atomic_t *addr, atomic_val_t value)
 {
-	ATOMIC_OP(addl, addr, value);
+	return __atomic_fetch_add(addr, value, __ATOMIC_SEQ_CST);
 }
 
-static inline void deprecated_atomic_and(uint32_t volatile *addr,
-					 uint32_t value)
+static inline atomic_val_t atomic_and(atomic_t *addr, atomic_val_t bits)
 {
-	ATOMIC_OP(andl, addr, value);
+	return __atomic_fetch_and(addr, bits, __ATOMIC_SEQ_CST);
 }
 
-static inline void deprecated_atomic_sub(uint32_t volatile *addr,
-					 uint32_t value)
+static inline atomic_val_t atomic_sub(atomic_t *addr, atomic_val_t value)
 {
-	ATOMIC_OP(subl, addr, value);
+	return __atomic_fetch_sub(addr, value, __ATOMIC_SEQ_CST);
 }
 
-static inline uint32_t deprecated_atomic_read_clear(uint32_t volatile *addr)
+static inline atomic_val_t atomic_clear(atomic_t *addr)
 {
-	int ret = 0;
-
-	if (*addr == 0)
-		return 0;
-
-	asm volatile(ASM_LOCK_PREFIX "xchgl %0, %1\n"
-		     : "+r" (ret), "+m" (*addr)
-		     : : "memory", "cc");
-
-	return ret;
+	return __atomic_exchange_n(addr, 0, __ATOMIC_SEQ_CST);
 }
 
-#endif  /* __CROS_EC_ATOMIC_H */
+#endif /* __CROS_EC_ATOMIC_H */
diff --git a/core/minute-ia/build.mk b/core/minute-ia/build.mk
index 099b9ea736..cd92c5618f 100644
--- a/core/minute-ia/build.mk
+++ b/core/minute-ia/build.mk
@@ -1,24 +1,23 @@
 # -*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
 # Minute-IA core build
 #
 
-# Select Minute-IA bare-metal toolchain
-$(call set-option,CROSS_COMPILE,$(CROSS_COMPILE_i386),\
-	/opt/coreboot-sdk/bin/i386-elf-)
-
 # FPU compilation flags
 CFLAGS_FPU-$(CONFIG_FPU)=
 
 # CPU specific compilation flags
-CFLAGS_CPU+=-O2 -fomit-frame-pointer -mno-accumulate-outgoing-args	\
+CFLAGS_CPU+=-O2 -fomit-frame-pointer					\
 	    -ffunction-sections -fdata-sections				\
 	    -fno-builtin-printf -fno-builtin-sprintf			\
 	    -fno-stack-protector -gdwarf-2  -fno-common -ffreestanding	\
 	    -minline-all-stringops -fno-strict-aliasing
+ifneq ($(cc-name),clang)
+CFLAGS_CPU+=-mno-accumulate-outgoing-args
+endif
 
 CFLAGS_CPU+=$(CFLAGS_FPU-y)
 
diff --git a/core/minute-ia/config_core.h b/core/minute-ia/config_core.h
index 47121642a4..d8a9b3adb1 100644
--- a/core/minute-ia/config_core.h
+++ b/core/minute-ia/config_core.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,8 +10,6 @@
 #define BFD_ARCH "i386"
 #define BFD_FORMAT "elf32-i386"
 
-#define CONFIG_SOFTWARE_PANIC
-
 /*
  * Since all implementations minute-ia are a single core, we do not need a
  * "lock;" prefix on any instructions. We use the below define in places where
@@ -29,6 +27,6 @@
 /*
  * Flag indicates the task uses FPU H/W
  */
-#define MIA_TASK_FLAG_USE_FPU                   0x00000001
+#define MIA_TASK_FLAG_USE_FPU 0x00000001
 
 #endif /* __CROS_EC_CONFIG_CORE_H */
diff --git a/core/minute-ia/cpu.c b/core/minute-ia/cpu.c
index cef39fe1ce..0157fec90b 100644
--- a/core/minute-ia/cpu.c
+++ b/core/minute-ia/cpu.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -7,7 +7,6 @@
 
 #include <cpu.h>
 
-
 void cpu_init(void)
 {
 	/* Nothing to do now */
diff --git a/core/minute-ia/cpu.h b/core/minute-ia/cpu.h
index 09eb50e4ca..bf5f3c5bbd 100644
--- a/core/minute-ia/cpu.h
+++ b/core/minute-ia/cpu.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,6 +8,5 @@
 #ifndef __CROS_EC_CPU_H
 #define __CROS_EC_CPU_H
 
-
 void cpu_init(void);
-#endif	/* __CROS_EC_CPU_H */
+#endif /* __CROS_EC_CPU_H */
diff --git a/core/minute-ia/ec.lds.S b/core/minute-ia/ec.lds.S
index 2463c6d397..e396b0e097 100644
--- a/core/minute-ia/ec.lds.S
+++ b/core/minute-ia/ec.lds.S
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -102,6 +102,10 @@ SECTIONS
 		KEEP(*(.rodata.HOOK_CHIPSET_SHUTDOWN_COMPLETE))
 		__hooks_chipset_shutdown_complete_end = .;
 
+		__hooks_chipset_hard_off = .;
+		KEEP(*(.rodata.HOOK_CHIPSET_HARD_OFF))
+		__hooks_chipset_hard_off_end = .;
+
 		__hooks_chipset_reset = .;
 		KEEP(*(.rodata.HOOK_CHIPSET_RESET))
 		__hooks_chipset_reset_end = .;
@@ -118,6 +122,12 @@ SECTIONS
 		KEEP(*(.rodata.HOOK_TABLET_MODE_CHANGE))
 		__hooks_tablet_mode_change_end = .;
 
+#ifdef CONFIG_BODY_DETECTION
+		__hooks_body_detect_change = .;
+		KEEP(*(.rodata.HOOK_BODY_DETECT_CHANGE))
+		__hooks_body_detect_change_end = .;
+#endif
+
 		__hooks_base_attached_change = .;
 		KEEP(*(.rodata.HOOK_BASE_ATTACHED_CHANGE))
 		__hooks_base_attached_change_end = .;
@@ -152,6 +162,10 @@ SECTIONS
 		KEEP(*(.rodata.HOOK_USB_PD_CONNECT))
 		__hooks_usb_pd_connect_end = .;
 
+		__hooks_power_supply_change = .;
+		KEEP(*(.rodata.HOOK_POWER_SUPPLY_CHANGE))
+		__hooks_power_supply_change_end = .;
+
 		__deferred_funcs = .;
 		KEEP(*(.rodata.deferred))
 		__deferred_funcs_end = .;
@@ -231,6 +245,12 @@ SECTIONS
 	/* TODO: Adjust __image_size to proper value for core minute-ia later */
 	__image_size = . - CONFIG_ISH_BOOT_START;
 
+#if defined(SECTION_IS_RW) && (CONFIG_FLASH_WRITE_SIZE > 0)
+	/* Alignment is needed by flash_command_write() for RW update. */
+	ASSERT(__image_size % CONFIG_FLASH_WRITE_SIZE == 0,
+	       "Error: RW image is not aligned to CONFIG_FLASH_WRITE_SIZE")
+#endif
+
 	def_irq_low  = ABSOLUTE(default_int_handler) & 0xFFFF;
 	def_irq_high = ABSOLUTE(default_int_handler) >> 16;
 
diff --git a/core/minute-ia/ia_structs.h b/core/minute-ia/ia_structs.h
index 29bbb6c005..83214e2c1b 100644
--- a/core/minute-ia/ia_structs.h
+++ b/core/minute-ia/ia_structs.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,7 +10,6 @@
 
 #include "common.h"
 
-
 /**
  * IA32/x86 architecture related data structure definitions.
  * including: Global Descriptor Table (GDT), Local Descriptor Table (LDT),
@@ -24,16 +23,16 @@
 struct gdt_entry {
 	union {
 		struct {
-			uint32_t dword_lo;	/* lower dword */
-			uint32_t dword_up;	/* upper dword */
+			uint32_t dword_lo; /* lower dword */
+			uint32_t dword_up; /* upper dword */
 		};
 		struct {
-			uint16_t limit_lw;	/* limit (0:15) */
-			uint16_t base_addr_lw;	/* base address (0:15) */
-			uint8_t base_addr_mb;	/* base address (16:23) */
-			uint8_t flags;		/* flags */
-			uint8_t limit_ub;	/* limit (16:19) */
-			uint8_t base_addr_ub;	/* base address (24:31) */
+			uint16_t limit_lw; /* limit (0:15) */
+			uint16_t base_addr_lw; /* base address (0:15) */
+			uint8_t base_addr_mb; /* base address (16:23) */
+			uint8_t flags; /* flags */
+			uint8_t limit_ub; /* limit (16:19) */
+			uint8_t base_addr_ub; /* base address (24:31) */
 		};
 	};
 
@@ -43,32 +42,32 @@ typedef struct gdt_entry ldt_entry;
 
 /* GDT header */
 struct gdt_header {
-	uint16_t limit;			/* GDT limit size */
-	struct gdt_entry *entries;	/* pointer to GDT entries */
+	uint16_t limit; /* GDT limit size */
+	struct gdt_entry *entries; /* pointer to GDT entries */
 } __packed;
 
 /* IDT entry descriptor */
 struct idt_entry {
 	union {
 		struct {
-			uint32_t dword_lo;	/* lower dword */
-			uint32_t dword_up;	/* upper dword */
+			uint32_t dword_lo; /* lower dword */
+			uint32_t dword_up; /* upper dword */
 		};
 
 		struct {
-			uint16_t offset_lw;	/* offset (0:15) */
-			uint16_t seg_selector;	/* segment selector */
-			uint8_t zero;		/* must be set to zero */
-			uint8_t flags;		/* flags */
-			uint16_t offset_uw;	/* offset (16:31) */
+			uint16_t offset_lw; /* offset (0:15) */
+			uint16_t seg_selector; /* segment selector */
+			uint8_t zero; /* must be set to zero */
+			uint8_t flags; /* flags */
+			uint16_t offset_uw; /* offset (16:31) */
 		};
 	};
 } __packed;
 
 /* IDT header */
 struct idt_header {
-	uint16_t limit;			/* IDT limit size */
-	struct idt_entry *entries;	/* pointer to IDT entries */
+	uint16_t limit; /* IDT limit size */
+	struct idt_entry *entries; /* pointer to IDT entries */
 } __packed;
 
 /* TSS entry descriptor */
@@ -117,22 +116,22 @@ struct tss_entry {
 #endif
 
 /* code segment flag,  E/R, Present = 1, DPL = 0, Acesssed = 1 */
-#define GDT_DESC_CODE_FLAGS	(0x9B)
+#define GDT_DESC_CODE_FLAGS (0x9B)
 
 /* data segment flag,  R/W, Present = 1, DPL = 0, Acesssed = 1 */
-#define GDT_DESC_DATA_FLAGS	(0x93)
+#define GDT_DESC_DATA_FLAGS (0x93)
 
 /* TSS segment limit size */
-#define GDT_DESC_TSS_LIMIT	(0x67)
+#define GDT_DESC_TSS_LIMIT (0x67)
 
 /* TSS segment flag, Present = 1, DPL = 0, Acesssed = 1 */
-#define GDT_DESC_TSS_FLAGS	(0x89)
+#define GDT_DESC_TSS_FLAGS (0x89)
 
 /* LDT segment flag, Present = 1, DPL = 0 */
-#define GDT_DESC_LDT_FLAGS	(0x82)
+#define GDT_DESC_LDT_FLAGS (0x82)
 
 /* IDT descriptor flag, Present = 1, DPL = 0, 32-bit interrupt gate */
-#define IDT_DESC_FLAGS		(0x8E)
+#define IDT_DESC_FLAGS (0x8E)
 
 /**
  * macros helper to create a GDT entry descriptor
@@ -141,21 +140,20 @@ struct tss_entry {
  * limit: 32bit limit size of bytes (will covert to unit of 4096-byte pages)
  * flags: 8bit flags
  */
-#define GEN_GDT_DESC_LO(base, limit, flags)                                    \
-	((((limit) >> 12) & 0xFFFF) | (((base) & 0xFFFF) << 16))
-
-#define GEN_GDT_DESC_UP(base, limit, flags)                                    \
-	((((base) >> 16) & 0xFF) | (((flags) << 8) & 0xFF00) |                 \
-	(((limit) >> 12) & 0xFF0000) | ((base) & 0xFF000000) | 0xc00000)
+#define GEN_GDT_DESC_LO(base, limit, flags) \
+	((((limit) >> 12) & 0xFFFF) | (((base)&0xFFFF) << 16))
 
+#define GEN_GDT_DESC_UP(base, limit, flags)                    \
+	((((base) >> 16) & 0xFF) | (((flags) << 8) & 0xFF00) | \
+	 (((limit) >> 12) & 0xFF0000) | ((base)&0xFF000000) | 0xc00000)
 
 /**
  * macro helper to create a IDT entry descriptor
  */
-#define GEN_IDT_DESC_LO(offset, selector, flags)                               \
-	(((uint32_t)(offset) & 0xFFFF) | (((selector) & 0xFFFF) << 16))
+#define GEN_IDT_DESC_LO(offset, selector, flags) \
+	(((uint32_t)(offset)&0xFFFF) | (((selector)&0xFFFF) << 16))
 
-#define GEN_IDT_DESC_UP(offset, selector, flags)                               \
-	(((uint32_t)(offset) & 0xFFFF0000) | (((flags) & 0xFF) << 8))
+#define GEN_IDT_DESC_UP(offset, selector, flags) \
+	(((uint32_t)(offset)&0xFFFF0000) | (((flags)&0xFF) << 8))
 
 #endif /* __CROS_EC_IA_STRUCTS_H */
diff --git a/core/minute-ia/include/fpu.h b/core/minute-ia/include/fpu.h
new file mode 100644
index 0000000000..9c0e818099
--- /dev/null
+++ b/core/minute-ia/include/fpu.h
@@ -0,0 +1,180 @@
+/* Copyright 2016 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Math utility functions for minute-IA */
+
+#ifndef __CROS_EC_FPU_H
+#define __CROS_EC_FPU_H
+
+#include "config.h"
+
+#ifdef CONFIG_FPU
+
+#define M_PI 3.14159265358979323846
+#define M_PI_2 1.57079632679489661923
+
+static inline float sqrtf(float v)
+{
+	float root;
+
+	/* root = fsqart (v); */
+	asm volatile("fsqrt" : "=t"(root) : "0"(v));
+	return root;
+}
+
+/* Absolute value of V. */
+static inline float fabsf(float v)
+{
+	float root;
+
+	/* root = fabs (v); */
+	asm volatile("fabs" : "=t"(root) : "0"(v));
+	return root;
+}
+
+/**
+ * Natural logarithm of V.
+ *
+ * @return ln(v)
+ */
+static inline float logf(float v)
+{
+	float res;
+
+	asm volatile("fldln2\n"
+		     "fxch\n"
+		     "fyl2x\n"
+		     : "=t"(res)
+		     : "0"(v));
+
+	return res;
+}
+
+/**
+ * Exponential function of V.
+ *
+ * @return e**v
+ */
+static inline float expf(float v)
+{
+	float res;
+
+	asm volatile("fldl2e\n"
+		     "fmulp\n"
+		     "fld %%st(0)\n"
+		     "frndint\n"
+		     "fsubr %%st(0),%%st(1)\n" /* bug-binutils/19054 */
+		     "fxch %%st(1)\n"
+		     "f2xm1\n"
+		     "fld1\n"
+		     "faddp\n"
+		     "fscale\n"
+		     "fstp %%st(1)\n"
+		     : "=t"(res)
+		     : "0"(v));
+
+	return res;
+}
+
+/**
+ * X to the Y power.
+ *
+ * @return x**y
+ */
+static inline float powf(float x, float y)
+{
+	float res;
+
+	asm volatile("fyl2x\n"
+		     "fld %%st(0)\n"
+		     "frndint\n"
+		     "fsub %%st,%%st(1)\n"
+		     "fxch\n"
+		     "fchs\n"
+		     "f2xm1\n"
+		     "fld1\n"
+		     "faddp\n"
+		     "fxch\n"
+		     "fld1\n"
+		     "fscale\n"
+		     "fstp %%st(1)\n"
+		     "fmulp\n"
+		     : "=t"(res)
+		     : "0"(x), "u"(y)
+		     : "st(1)");
+
+	return res;
+}
+
+/* Smallest integral value not less than V.  */
+static inline float ceilf(float v)
+{
+	float res;
+	unsigned short control_word, control_word_tmp;
+
+	asm volatile("fnstcw %0" : "=m"(control_word));
+	/* Set Rounding Mode to 10B, round up toward +infinity */
+	control_word_tmp = (control_word | 0x0800) & 0xfbff;
+	asm volatile("fld %3\n"
+		     "fldcw %1\n"
+		     "frndint\n"
+		     "fldcw %2"
+		     : "=t"(res)
+		     : "m"(control_word_tmp), "m"(control_word), "m"(v));
+
+	return res;
+}
+
+/* Arc tangent of Y/X.  */
+static inline float atan2f(float y, float x)
+{
+	float res;
+
+	asm volatile("fpatan" : "=t"(res) : "0"(x), "u"(y) : "st(1)");
+
+	return res;
+}
+
+/* Arc tangent of V. */
+static inline float atanf(float v)
+{
+	float res;
+
+	asm volatile("fld1\n"
+		     "fpatan\n"
+		     : "=t"(res)
+		     : "0"(v));
+
+	return res;
+}
+
+/* Sine of V. */
+static inline float sinf(float v)
+{
+	float res;
+
+	asm volatile("fsin" : "=t"(res) : "0"(v));
+
+	return res;
+}
+
+/* Cosine of V. */
+static inline float cosf(float v)
+{
+	float res;
+
+	asm volatile("fcos" : "=t"(res) : "0"(v));
+
+	return res;
+}
+
+/* Arc cosine of V. */
+static inline float acosf(float v)
+{
+	return atan2f(sqrtf(1.0 - v * v), v);
+}
+
+#endif /* CONFIG_FPU */
+#endif /* __CROS_EC_FPU_H */
diff --git a/core/minute-ia/include/math.h b/core/minute-ia/include/math.h
deleted file mode 100644
index 00f73ccaa1..0000000000
--- a/core/minute-ia/include/math.h
+++ /dev/null
@@ -1,241 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Math utility functions for minute-IA */
-
-#ifndef __CROS_EC_MATH_H
-#define __CROS_EC_MATH_H
-
-#include "config.h"
-
-#ifdef CONFIG_FPU
-
-#define M_PI            3.14159265358979323846
-#define M_PI_2          1.57079632679489661923
-
-static inline float sqrtf(float v)
-{
-	float root;
-
-	/* root = fsqart (v); */
-	asm volatile(
-		"fsqrt"
-		: "=t" (root)
-		: "0" (v)
-	);
-	return root;
-}
-
-/* Absolute value of V. */
-static inline float fabsf(float v)
-{
-	float root;
-
-	/* root = fabs (v); */
-	asm volatile(
-		"fabs"
-		: "=t" (root)
-		: "0" (v)
-	);
-	return root;
-}
-
-/**
- * Natural logarithm of V.
- *
- * @return ln(v)
- */
-static inline float logf(float v)
-{
-	float res;
-
-	asm volatile(
-		"fldln2\n"
-		"fxch\n"
-		"fyl2x\n"
-		: "=t" (res)
-		: "0" (v));
-
-	return res;
-}
-
-/**
- * Exponential function of V.
- *
- * @return e**v
- */
-static inline float expf(float v)
-{
-	float res;
-
-	asm volatile(
-		"fldl2e\n"
-		"fmulp\n"
-		"fld %%st(0)\n"
-		"frndint\n"
-		"fsubr %%st(0),%%st(1)\n" /* bug-binutils/19054 */
-		"fxch %%st(1)\n"
-		"f2xm1\n"
-		"fld1\n"
-		"faddp\n"
-		"fscale\n"
-		"fstp %%st(1)\n"
-		: "=t" (res)
-		: "0" (v));
-
-	return res;
-}
-
-/**
- * X to the Y power.
- *
- * @return x**y
- */
-static inline float powf(float x, float y)
-{
-	float res;
-
-	asm volatile(
-		"fyl2x\n"
-		"fld %%st(0)\n"
-		"frndint\n"
-		"fsub %%st,%%st(1)\n"
-		"fxch\n"
-		"fchs\n"
-		"f2xm1\n"
-		"fld1\n"
-		"faddp\n"
-		"fxch\n"
-		"fld1\n"
-		"fscale\n"
-		"fstp %%st(1)\n"
-		"fmulp\n"
-		: "=t" (res)
-		: "0" (x), "u" (y)
-		: "st(1)");
-
-	return res;
-}
-
-/* Smallest integral value not less than V.  */
-static inline float ceilf(float v)
-{
-	float res;
-	unsigned short control_word, control_word_tmp;
-
-	asm volatile("fnstcw %0" : "=m" (control_word));
-	/* Set Rounding Mode to 10B, round up toward +infinity */
-	control_word_tmp = (control_word | 0x0800) & 0xfbff;
-	asm volatile(
-		"fld %3\n"
-		"fldcw %1\n"
-		"frndint\n"
-		"fldcw %2"
-		: "=t" (res)
-		: "m" (control_word_tmp), "m"(control_word), "m" (v));
-
-	return res;
-}
-
-/* Arc tangent of Y/X.  */
-static inline float atan2f(float y, float x)
-{
-	float res;
-
-	asm volatile("fpatan" : "=t" (res) : "0" (x), "u" (y) : "st(1)");
-
-	return res;
-}
-
-/* Arc tangent of V. */
-static inline float atanf(float v)
-{
-	float res;
-
-	asm volatile(
-		"fld1\n"
-		"fpatan\n"
-		: "=t" (res)
-		: "0" (v));
-
-	return res;
-}
-
-/* Sine of V. */
-static inline float sinf(float v)
-{
-	float res;
-
-	asm volatile("fsin" : "=t" (res) : "0" (v));
-
-	return res;
-}
-
-/* Cosine of V. */
-static inline float cosf(float v)
-{
-	float res;
-
-	asm volatile("fcos" : "=t" (res) : "0" (v));
-
-	return res;
-}
-
-/* Arc cosine of V. */
-static inline float acosf(float v)
-{
-	return atan2f(sqrtf(1.0 - v * v), v);
-}
-
-#define COND_FP_NAN      0x0100
-#define COND_FP_SIGNBIT  0x0200
-#define COND_FP_NORMAL   0x0400
-#define COND_FP_ZERO     0x4000
-#define COND_FP_INFINITE (COND_FP_NAN | COND_FP_NORMAL)
-
-/* Check if V is NaN (not-a-number).  */
-static inline int __isnanf(float v)
-{
-	uint16_t stat;
-
-	asm volatile(
-		"fxam\n"
-		"fnstsw %0\n"
-		: "=r" (stat)
-		: "0" (v));
-
-	return (stat & (COND_FP_NAN | COND_FP_NORMAL | COND_FP_ZERO))
-	       == COND_FP_NAN;
-}
-
-/**
- * Check if V is infinite.
- *
- * @return 0 if V is finite or NaN.
- * @return +1 if V is +infinite.
- * @return -1 if V is -infinite.
- */
-static inline int __isinff(float v)
-{
-	uint16_t stat;
-
-	asm volatile(
-		"fxam\n"
-		"fnstsw %0\n"
-		: "=r" (stat)
-		: "v" (v));
-
-	if ((stat & (COND_FP_NAN | COND_FP_NORMAL | COND_FP_ZERO)) ==
-	    COND_FP_INFINITE) {
-		/* Infinite number, check sign */
-		return stat & COND_FP_SIGNBIT ? -1 : 1;
-	}
-
-	/* Finite or NaN */
-	return 0;
-}
-
-#endif  /* CONFIG_FPU */
-#endif  /* __CROS_EC_MATH_H */
diff --git a/core/minute-ia/init.S b/core/minute-ia/init.S
index b8e51ccc91..4d3ac47da6 100644
--- a/core/minute-ia/init.S
+++ b/core/minute-ia/init.S
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/minute-ia/interrupts.c b/core/minute-ia/interrupts.c
index 2d55d3129e..b99bb6e49a 100644
--- a/core/minute-ia/interrupts.c
+++ b/core/minute-ia/interrupts.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -20,8 +20,8 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 /* The IDT  - initialized in init.S */
 extern struct idt_entry __idt[NUM_VECTORS];
@@ -54,7 +54,7 @@ static void set_ioapic_redtbl_raw(const uint32_t irq, const uint32_t val)
  * bitmap for current IRQ's mask status
  * ISH support max 64 IRQs, 64 bit bitmap value is ok
  */
-#define ISH_MAX_IOAPIC_IRQS	(64)
+#define ISH_MAX_IOAPIC_IRQS (64)
 uint64_t ioapic_irq_mask_bitmap;
 
 /**
@@ -70,7 +70,7 @@ uint64_t disable_all_interrupts(void)
 	uint64_t saved_map;
 	int i;
 
-	saved_map =  ioapic_irq_mask_bitmap;
+	saved_map = ioapic_irq_mask_bitmap;
 
 	for (i = 0; i < ISH_MAX_IOAPIC_IRQS; i++) {
 		if (((uint64_t)0x1 << i) & saved_map)
@@ -179,27 +179,27 @@ static const irq_desc_t system_irqs[] = {
  * and go directly to the CPU core, so get_current_interrupt_vector
  * cannot be used.
  */
-#define DEFINE_EXN_HANDLER(vector)			\
+#define DEFINE_EXN_HANDLER(vector) \
 	_DEFINE_EXN_HANDLER(vector, exception_panic_##vector)
-#define _DEFINE_EXN_HANDLER(vector, name)		\
-	void __keep name(void);				\
-	noreturn void name(void)	\
-	{						\
-		__asm__ ("push $0\n"			\
-			 "push $" #vector "\n"		\
-			 "call exception_panic\n");	\
-		__builtin_unreachable();		\
+#define _DEFINE_EXN_HANDLER(vector, name)          \
+	void __keep name(void);                    \
+	noreturn void name(void)                   \
+	{                                          \
+		__asm__("push $0\n"                \
+			"push $" #vector "\n"      \
+			"call exception_panic\n"); \
+		__builtin_unreachable();           \
 	}
 
-#define DEFINE_EXN_HANDLER_W_ERRORCODE(vector)		\
+#define DEFINE_EXN_HANDLER_W_ERRORCODE(vector) \
 	_DEFINE_EXN_HANDLER_W_ERRORCODE(vector, exception_panic_##vector)
-#define _DEFINE_EXN_HANDLER_W_ERRORCODE(vector, name)	\
-	void __keep name(void);				\
-	noreturn void name(void)	\
-	{						\
-		__asm__ ("push $" #vector "\n"		\
-			 "call exception_panic\n");	\
-		__builtin_unreachable();		\
+#define _DEFINE_EXN_HANDLER_W_ERRORCODE(vector, name) \
+	void __keep name(void);                       \
+	noreturn void name(void)                      \
+	{                                             \
+		__asm__("push $" #vector "\n"         \
+			"call exception_panic\n");    \
+		__builtin_unreachable();              \
 	}
 
 DEFINE_EXN_HANDLER(0);
@@ -228,15 +228,10 @@ DEFINE_EXN_HANDLER(20);
  * watchdog timer expiration. However, this time, hardware does not
  * push errorcode, and we must account for that by pushing zero.
  */
-noreturn __keep
-void exception_panic_wdt(uint32_t cs)
+noreturn __keep void exception_panic_wdt(uint32_t cs)
 {
-	exception_panic(
-		CONFIG_MIA_WDT_VEC,
-		0,
-		(uint32_t)__builtin_return_address(0),
-		cs,
-		0);
+	exception_panic(CONFIG_MIA_WDT_VEC, 0,
+			(uint32_t)__builtin_return_address(0), cs, 0);
 }
 
 void set_interrupt_gate(uint8_t num, isr_handler_t func, uint8_t flags)
@@ -244,7 +239,7 @@ void set_interrupt_gate(uint8_t num, isr_handler_t func, uint8_t flags)
 	uint16_t code_segment;
 
 	/* When the flat model is used the CS will never change. */
-	__asm volatile ("mov %%cs, %0":"=r" (code_segment));
+	__asm volatile("mov %%cs, %0" : "=r"(code_segment));
 
 	__idt[num].dword_lo = GEN_IDT_DESC_LO(func, code_segment, flags);
 	__idt[num].dword_up = GEN_IDT_DESC_UP(func, code_segment, flags);
@@ -384,26 +379,28 @@ void handle_lapic_lvt_error(void)
 
 /* LAPIC LVT error is not an IRQ and can not use DECLARE_IRQ() to call. */
 void _lapic_error_handler(void);
-__asm__ (
-	".section .text._lapic_error_handler\n"
+__asm__(".section .text._lapic_error_handler\n"
 	"_lapic_error_handler:\n"
-		"pusha\n"
-		ASM_LOCK_PREFIX "addl $1, __in_isr\n"
-		"movl %esp, %eax\n"
-		"movl $stack_end, %esp\n"
-		"push %eax\n"
+	"pusha\n" ASM_LOCK_PREFIX "addl $1, __in_isr\n"
+	"movl %esp, %eax\n"
+	"movl $stack_end, %esp\n"
+	"push %eax\n"
 #ifdef CONFIG_TASK_PROFILING
-		"push $" STRINGIFY(CONFIG_IRQ_COUNT) "\n"
-		"call task_start_irq_handler\n"
-		"addl $0x04, %esp\n"
+	"push $" STRINGIFY(
+		CONFIG_IRQ_COUNT) "\n"
+				  "call task_start_irq_handler\n"
+				  "addl $0x04, %esp\n"
 #endif
-		"call handle_lapic_lvt_error\n"
-		"pop %esp\n"
-		"movl $0x00, (0xFEE000B0)\n"	/* Set EOI for LAPIC */
-		ASM_LOCK_PREFIX "subl $1, __in_isr\n"
-		"popa\n"
-		"iret\n"
-	);
+				  "call handle_lapic_lvt_error\n"
+				  "pop %esp\n"
+				  "movl $0x00, (0xFEE000B0)\n" /* Set
+								  EOI
+								  for
+								  LAPIC
+								*/
+	ASM_LOCK_PREFIX "subl $1, __in_isr\n"
+				  "popa\n"
+				  "iret\n");
 
 /* Should only be called in interrupt context */
 void unhandled_vector(void)
@@ -411,7 +408,7 @@ void unhandled_vector(void)
 	uint32_t vec = get_current_interrupt_vector();
 	CPRINTF("Ignoring vector 0x%0x!\n", vec);
 	/* Put the vector number in eax so default_int_handler can use it */
-	asm("" : : "a" (vec));
+	asm("" : : "a"(vec));
 }
 
 /**
@@ -447,15 +444,15 @@ void lapic_restore(void)
 
 void init_interrupts(void)
 {
-	unsigned entry;
+	unsigned int entry;
 	const struct irq_def *p;
-	unsigned num_system_irqs = ARRAY_SIZE(system_irqs);
-	unsigned max_entries = (read_ioapic_reg(IOAPIC_VERSION) >> 16) & 0xff;
+	unsigned int num_system_irqs = ARRAY_SIZE(system_irqs);
+	unsigned int max_entries = (read_ioapic_reg(IOAPIC_VERSION) >> 16) &
+				   0xff;
 
 	/* Setup gates for IRQs declared by drivers using DECLARE_IRQ */
 	for (p = __irq_data; p < __irq_data_end; p++)
-		set_interrupt_gate(IRQ_TO_VEC(p->irq),
-				   p->handler,
+		set_interrupt_gate(IRQ_TO_VEC(p->irq), p->handler,
 				   IDT_DESC_FLAGS);
 
 	/* Software generated IRQ */
@@ -474,11 +471,11 @@ void init_interrupts(void)
 	for (entry = 0; entry < num_system_irqs; entry++)
 		set_ioapic_redtbl_raw(system_irqs[entry].irq,
 				      system_irqs[entry].vector |
-				      IOAPIC_REDTBL_DELMOD_FIXED |
-				      IOAPIC_REDTBL_DESTMOD_PHYS |
-				      IOAPIC_REDTBL_MASK |
-				      system_irqs[entry].polarity |
-				      system_irqs[entry].trigger);
+					      IOAPIC_REDTBL_DELMOD_FIXED |
+					      IOAPIC_REDTBL_DESTMOD_PHYS |
+					      IOAPIC_REDTBL_MASK |
+					      system_irqs[entry].polarity |
+					      system_irqs[entry].trigger);
 
 	set_interrupt_gate(ISH_TS_VECTOR, __switchto, IDT_DESC_FLAGS);
 
diff --git a/core/minute-ia/interrupts.h b/core/minute-ia/interrupts.h
index 3a951a5ddb..34abd587d3 100644
--- a/core/minute-ia/interrupts.h
+++ b/core/minute-ia/interrupts.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,21 +11,19 @@
 #ifndef __ASSEMBLER__
 #include <stdint.h>
 
-#define USHRT_MAX		0xFFFF
+#define USHRT_MAX 0xFFFF
 typedef struct {
-	unsigned irq;
-	unsigned trigger;
-	unsigned polarity;
-	unsigned vector;
+	unsigned int irq;
+	unsigned int trigger;
+	unsigned int polarity;
+	unsigned int vector;
 } irq_desc_t;
 
-#define INTR_DESC(__irq,__vector,__trig)                    \
-    {                                                       \
-        .irq            = __irq,                            \
-        .trigger        = __trig,                           \
-        .polarity       = IOAPIC_REDTBL_INTPOL_HIGH,        \
-        .vector         = __vector	                    \
-    }
+#define INTR_DESC(__irq, __vector, __trig)                                \
+	{                                                                 \
+		.irq = __irq, .trigger = __trig,                          \
+		.polarity = IOAPIC_REDTBL_INTPOL_HIGH, .vector = __vector \
+	}
 
 #define LEVEL_INTR(__irq, __vector) \
 	INTR_DESC(__irq, __vector, IOAPIC_REDTBL_TRIGGER_LEVEL)
@@ -34,18 +32,18 @@ typedef struct {
 #endif
 
 /* ISH has a single core processor */
-#define DEST_APIC_ID			0
-#define NUM_VECTORS			256
+#define DEST_APIC_ID 0
+#define NUM_VECTORS 256
 
 /* APIC bit definitions. */
-#define APIC_DIV_16			0x03
-#define APIC_ENABLE_BIT			(1UL << 8UL)
-#define APIC_SPURIOUS_INT		REG32(ISH_LAPIC_BASE + 0xF0UL )
-#define APIC_LVT_ERROR			REG32(ISH_LAPIC_BASE + 0x370UL)
+#define APIC_DIV_16 0x03
+#define APIC_ENABLE_BIT (1UL << 8UL)
+#define APIC_SPURIOUS_INT REG32(ISH_LAPIC_BASE + 0xF0UL)
+#define APIC_LVT_ERROR REG32(ISH_LAPIC_BASE + 0x370UL)
 
 #ifndef __ASSEMBLER__
 
-typedef void (*isr_handler_t) (void);
+typedef void (*isr_handler_t)(void);
 
 void init_interrupts(void);
 void mask_interrupt(unsigned int irq);
@@ -66,4 +64,4 @@ void restore_interrupts(uint64_t irq_map);
 uint32_t get_current_interrupt_vector(void);
 #endif
 
-#endif	/* __CROS_EC_IA32_INTERRUPTS_H */
+#endif /* __CROS_EC_IA32_INTERRUPTS_H */
diff --git a/core/minute-ia/irq_handler.h b/core/minute-ia/irq_handler.h
index eec0ffddb4..deb8048e12 100644
--- a/core/minute-ia/irq_handler.h
+++ b/core/minute-ia/irq_handler.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,7 +12,7 @@
 #include "task.h"
 #include "task_defs.h"
 
-asm (".include \"core/minute-ia/irq_handler_common.S\"");
+asm(".include \"core/minute-ia/irq_handler_common.S\"");
 
 /* Helper macros to build the IRQ handler and priority struct names */
 #define IRQ_HANDLER(irqname) CONCAT3(_irq_, irqname, _handler)
@@ -30,26 +30,24 @@ asm (".include \"core/minute-ia/irq_handler_common.S\"");
  * Each irq has a irq_data structure placed in .rodata.irqs section,
  * to be used for dynamically setting up interrupt gates
  */
-#define DECLARE_IRQ_(irq_, routine_, vector)				\
-	void __keep routine_(void);					\
-	void IRQ_HANDLER(irq_)(void);					\
-	__asm__ (".section .rodata.irqs\n");				\
-	const struct irq_def __keep CONCAT4(__irq_, irq_, _, routine_)	\
-	__attribute__((section(".rodata.irqs"))) = {			\
-		.irq = irq_,						\
-		.routine = routine_,					\
-		.handler = IRQ_HANDLER(irq_)				\
-	};								\
-	__asm__ (							\
-		".section .text._irq_" #irq_ "_handler\n"		\
-		"_irq_" #irq_ "_handler:\n"				\
-		"pusha\n"						\
-		ASM_LOCK_PREFIX "addl  $1, __in_isr\n"			\
-		"irq_handler_common $0 $0 $" #irq_ "\n"			\
-		"movl $"#vector ", " STRINGIFY(IOAPIC_EOI_REG_ADDR) "\n" \
-		"movl $0x00, " STRINGIFY(LAPIC_EOI_REG_ADDR) "\n"	\
-		ASM_LOCK_PREFIX "subl  $1, __in_isr\n"			\
-		"popa\n"						\
-		"iret\n"						\
-	)
-#endif  /* __CROS_EC_IRQ_HANDLER_H */
+#define DECLARE_IRQ_(irq_, routine_, vector)                                                    \
+	static void __keep routine_(void);                                                      \
+	void IRQ_HANDLER(irq_)(void);                                                           \
+	__asm__(".section .rodata.irqs\n");                                                     \
+	const struct irq_def __keep CONCAT4(__irq_, irq_, _, routine_)                          \
+		__attribute__((section(                                                         \
+			".rodata.irqs"))) = { .irq = irq_,                                      \
+					      .routine = routine_,                              \
+					      .handler = IRQ_HANDLER(irq_) };                   \
+	__asm__(".section .text._irq_" #irq_ "_handler\n"                                       \
+		"_irq_" #irq_ "_handler:\n"                                                     \
+		"pusha\n" ASM_LOCK_PREFIX "addl  $1, __in_isr\n"                                \
+		"irq_handler_common $0 $0 $" #irq_ "\n"                                         \
+		"movl $" #vector ", " STRINGIFY(                                                \
+			IOAPIC_EOI_REG_ADDR) "\n"                                               \
+					     "movl $0x00, " STRINGIFY(                          \
+						     LAPIC_EOI_REG_ADDR) "\n" ASM_LOCK_PREFIX   \
+									 "subl  $1, __in_isr\n" \
+									 "popa\n"               \
+									 "iret\n")
+#endif /* __CROS_EC_IRQ_HANDLER_H */
diff --git a/core/minute-ia/irq_handler_common.S b/core/minute-ia/irq_handler_common.S
index e07cf26ce1..2445f83730 100644
--- a/core/minute-ia/irq_handler_common.S
+++ b/core/minute-ia/irq_handler_common.S
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/minute-ia/mia_panic_internal.h b/core/minute-ia/mia_panic_internal.h
index 748ccbf2dd..d9d213ca85 100644
--- a/core/minute-ia/mia_panic_internal.h
+++ b/core/minute-ia/mia_panic_internal.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,10 +8,5 @@
  * convenientely in the same order as pushed by hardwared during a
  * processor exception.
  */
-noreturn
-void exception_panic(
-	uint32_t vector,
-	uint32_t errorcode,
-	uint32_t eip,
-	uint32_t cs,
-	uint32_t eflags);
+noreturn void exception_panic(uint32_t vector, uint32_t errorcode, uint32_t eip,
+			      uint32_t cs, uint32_t eflags);
diff --git a/core/minute-ia/mpu.c b/core/minute-ia/mpu.c
index 389668ea6f..6cbf4c634f 100644
--- a/core/minute-ia/mpu.c
+++ b/core/minute-ia/mpu.c
@@ -1,12 +1,12 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* MPU module for ISH */
 
-#include "mpu.h"
 #include "console.h"
+#include "mpu.h"
 #include "registers.h"
 #include "task.h"
 #include "util.h"
diff --git a/core/minute-ia/panic.c b/core/minute-ia/panic.c
index acaee72496..d02778891d 100644
--- a/core/minute-ia/panic.c
+++ b/core/minute-ia/panic.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -57,13 +57,12 @@ void panic_data_print(const struct panic_data *pdata)
 	else if (pdata->x86.vector <= 20)
 		panic_printf("Reason: %s\n", panic_reason[pdata->x86.vector]);
 	else if (panic_sw_reason_is_valid(pdata->x86.vector)) {
-		panic_printf("Software panic reason %s\n",
-			     panic_sw_reasons[pdata->x86.vector -
-					      PANIC_SW_BASE]);
+		panic_printf(
+			"Software panic reason %s\n",
+			panic_sw_reasons[pdata->x86.vector - PANIC_SW_BASE]);
 		panic_printf("Software panic info 0x%x\n",
 			     pdata->x86.error_code);
-	}
-	else
+	} else
 		panic_printf("Interrupt vector number: 0x%08X (unknown)\n",
 			     pdata->x86.vector);
 	panic_printf("\n");
@@ -91,12 +90,8 @@ void panic_data_print(const struct panic_data *pdata)
  * order pushed to the stack by hardware: see "Intel 64 and IA-32
  * Architectures Software Developer's Manual", Volume 3A, Figure 6-4.
  */
-void exception_panic(
-	uint32_t vector,
-	uint32_t error_code,
-	uint32_t eip,
-	uint32_t cs,
-	uint32_t eflags)
+void exception_panic(uint32_t vector, uint32_t error_code, uint32_t eip,
+		     uint32_t cs, uint32_t eflags)
 {
 	/*
 	 * If a panic were to occur during the reset procedure, we want
@@ -105,6 +100,7 @@ void exception_panic(
 	 * already.
 	 */
 	static int panic_once;
+	struct panic_data *pdata;
 
 	register uint32_t eax asm("eax");
 	register uint32_t ebx asm("ebx");
@@ -112,8 +108,10 @@ void exception_panic(
 	register uint32_t edx asm("edx");
 	register uint32_t esi asm("esi");
 	register uint32_t edi asm("edi");
+	asm(""
+	    : "=r"(eax), "=r"(ebx), "=r"(ecx), "=r"(edx), "=r"(esi), "=r"(edi));
 
-	struct panic_data * const pdata = get_panic_data_write();
+	pdata = get_panic_data_write();
 
 	/* Save registers to global panic structure */
 	pdata->x86.eax = eax;
@@ -173,26 +171,22 @@ void exception_panic(
 	__builtin_unreachable();
 }
 
-noreturn
-void software_panic(uint32_t reason, uint32_t info)
+noreturn void software_panic(uint32_t reason, uint32_t info)
 {
 	uint16_t code_segment;
 
 	/* Get the current code segment */
-	__asm__ volatile ("movw  %%cs, %0":"=m" (code_segment));
+	__asm__ volatile("movw  %%cs, %0" : "=m"(code_segment));
 
-	exception_panic(reason,
-			info,
-			(uint32_t)__builtin_return_address(0),
-			code_segment,
-			0);
+	exception_panic(reason, info, (uint32_t)__builtin_return_address(0),
+			code_segment, 0);
 
 	__builtin_unreachable();
 }
 
 void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
 {
-	struct panic_data * const pdata = get_panic_data_write();
+	struct panic_data *const pdata = get_panic_data_write();
 
 	/* Setup panic data structure */
 	memset(pdata, 0, CONFIG_PANIC_DATA_SIZE);
@@ -209,7 +203,7 @@ void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
 
 void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception)
 {
-	struct panic_data * const pdata = panic_get_data();
+	struct panic_data *const pdata = panic_get_data();
 
 	if (pdata && pdata->struct_version == 2) {
 		*reason = pdata->x86.vector;
diff --git a/core/minute-ia/switch.S b/core/minute-ia/switch.S
index f8d0be3874..b014bb4c29 100644
--- a/core/minute-ia/switch.S
+++ b/core/minute-ia/switch.S
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -24,7 +24,6 @@
 # Start the task scheduling. Start current_task (hook_task)
 # This function is not an ISR but imitates the sequence.
 .align 4
-.func __task_start
 __task_start:
 	movl 0x4(%esp), %ecx
 	movl current_task, %eax
@@ -39,12 +38,10 @@ __task_start:
 	movl $0x1, (%ecx)       # first task is ready. set start_called = 1
 	popa
 	iret
-.endfunc
 
 # Default interrupt handler - to handle exceptions
 # and prints error
 .align 4
-.func default_int_handler
 default_int_handler:
 
 	pusha
@@ -70,10 +67,8 @@ default_int_handler:
 	ASM_LOCK_PREFIX subl $1, __in_isr
 	popa
 	iret
-.endfunc
 
 .align 4
-.func sw_irq_handler
 sw_irq_handler:
 	pusha
 	ASM_LOCK_PREFIX addl $1, __in_isr
@@ -91,14 +86,12 @@ sw_irq_handler:
 	ASM_LOCK_PREFIX subl $1, __in_isr
 	popa
 	iret
-.endfunc
 
 
 # Switches from one task to another if ready.
 # __schedule triggers software interrupt ISH_TS_VECTOR, which is handled by
 # __switchto
 .align 4
-.func __switchto
 __switchto:
 	pusha
 	ASM_LOCK_PREFIX addl $1, __in_isr
@@ -116,4 +109,3 @@ __switchto:
 	ASM_LOCK_PREFIX subl $1, __in_isr
 	popa
 	iret
-.endfunc
diff --git a/core/minute-ia/task.c b/core/minute-ia/task.c
index 431bd62e54..6322125247 100644
--- a/core/minute-ia/task.c
+++ b/core/minute-ia/task.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,21 +13,22 @@
 #define TEST_TASK_EXTRA_ARGS 0
 
 #include "atomic.h"
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
+#include "hpet.h"
+#include "interrupts.h"
 #include "link_defs.h"
 #include "panic.h"
 #include "task.h"
+#include "task_defs.h"
 #include "timer.h"
 #include "util.h"
-#include "task_defs.h"
-#include "interrupts.h"
-#include "hpet.h"
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 /* Value to store in unused stack */
 #define STACK_UNUSED_VALUE 0xdeadd00d
@@ -43,11 +44,9 @@ CONFIG_TEST_TASK_LIST
 extern volatile uint32_t __in_isr;
 
 /* Task names for easier debugging */
-#define TASK(n, r, d, s, f)  #n,
-static const char * const task_names[] = {
-	"<< idle >>",
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
+#define TASK(n, r, d, s, f) #n,
+static const char *const task_names[] = {
+	"<< idle >>", CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST
 };
 #undef TASK
 
@@ -57,12 +56,12 @@ static uint64_t task_start_time; /* Time task scheduling started */
  * We only keep 32-bit values for exception start/end time, to avoid
  * accounting errors when we service interrupt when the timer wraps around.
  */
-static uint32_t exc_start_time;  /* Time of task->exception transition */
-static uint32_t exc_end_time;    /* Time of exception->task transition */
-static uint64_t exc_total_time;  /* Total time in exceptions */
-static uint32_t svc_calls;	 /* Number of service calls */
-static uint32_t task_switches;	/* Number of times active task changed */
-static uint32_t irq_dist[CONFIG_IRQ_COUNT];	/* Distribution of IRQ calls */
+static uint32_t exc_start_time; /* Time of task->exception transition */
+static uint32_t exc_end_time; /* Time of exception->task transition */
+static uint64_t exc_total_time; /* Total time in exceptions */
+static atomic_t svc_calls; /* Number of service calls */
+static uint32_t task_switches; /* Number of times active task changed */
+static uint32_t irq_dist[CONFIG_IRQ_COUNT]; /* Distribution of IRQ calls */
 #endif
 
 void __schedule(int desched, int resched);
@@ -97,43 +96,36 @@ static void task_exit_trap(void)
 }
 
 /* Startup parameters for all tasks. */
-#define TASK(n, r, d, s, f)  {	\
-	.r0 = (uint32_t)d,	\
-	.pc = (uint32_t)r,	\
-	.stack_size = s,	\
-	.flags = f,		\
-},
+#define TASK(n, r, d, s, f)        \
+	{                          \
+		.r0 = (uint32_t)d, \
+		.pc = (uint32_t)r, \
+		.stack_size = s,   \
+		.flags = f,        \
+	},
 static const struct {
 	uint32_t r0;
 	uint32_t pc;
 	uint16_t stack_size;
 	uint32_t flags;
-} tasks_init[] = {
-	TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE, 0)
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
-};
+} tasks_init[] = { TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE, 0)
+			   CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST };
 
 #undef TASK
 
 /* Contexts for all tasks */
 static task_ tasks[TASK_ID_COUNT];
 /* Validity checks about static task invariants */
-BUILD_ASSERT(TASK_ID_COUNT <= sizeof(unsigned) * 8);
+BUILD_ASSERT(TASK_ID_COUNT <= sizeof(unsigned int) * 8);
 BUILD_ASSERT(TASK_ID_COUNT < (1 << (sizeof(task_id_t) * 8)));
 
-
 /* Stacks for all tasks */
-#define TASK(n, r, d, s, f)  + s
-uint8_t task_stacks[0
-		    TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE, 0)
-		    CONFIG_TASK_LIST
-		    CONFIG_TEST_TASK_LIST
-] __aligned(8);
+#define TASK(n, r, d, s, f) +s
+uint8_t task_stacks[0 TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE, 0)
+			    CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST] __aligned(8);
 
 #undef TASK
 
-
 task_ *current_task, *next_task;
 
 /*
@@ -143,15 +135,15 @@ task_ *current_task, *next_task;
  * can do their init within a task switching context.  The hooks task will then
  * make a call to enable all tasks.
  */
-static uint32_t tasks_ready = BIT(TASK_ID_HOOKS);
+static atomic_t tasks_ready = BIT(TASK_ID_HOOKS);
 /*
  * Initially allow only the HOOKS and IDLE task to run, regardless of ready
  * status, in order for HOOK_INIT to complete before other tasks.
  * task_enable_all_tasks() will open the flood gates.
  */
-static uint32_t tasks_enabled = BIT(TASK_ID_HOOKS) | BIT(TASK_ID_IDLE);
+static atomic_t tasks_enabled = BIT(TASK_ID_HOOKS) | BIT(TASK_ID_IDLE);
 
-static int start_called;  /* Has task swapping started */
+static int start_called; /* Has task swapping started */
 
 static inline task_ *__task_id_to_ptr(task_id_t id)
 {
@@ -160,7 +152,7 @@ static inline task_ *__task_id_to_ptr(task_id_t id)
 
 void interrupt_disable(void)
 {
-	__asm__ __volatile__ ("cli");
+	__asm__ __volatile__("cli");
 }
 
 void interrupt_enable(void)
@@ -170,12 +162,24 @@ void interrupt_enable(void)
 	 */
 	ASSERT(task_start_called() != 1);
 
-	__asm__ __volatile__ ("sti");
+	__asm__ __volatile__("sti");
 }
 
-inline int in_interrupt_context(void)
+inline bool is_interrupt_enabled(void)
 {
-	return !!__in_isr;
+	uint32_t eflags = 0;
+
+	__asm__ __volatile__("pushfl\n"
+			     "popl %0\n"
+			     : "=r"(eflags));
+
+	/* Check Interrupt Enable flag */
+	return eflags & 0x200;
+}
+
+inline bool in_interrupt_context(void)
+{
+	return __in_isr;
 }
 
 task_id_t task_get_current(void)
@@ -195,7 +199,7 @@ const char *task_get_name(task_id_t tskid)
 	return "<< unknown >>";
 }
 
-uint32_t *task_get_event_bitmap(task_id_t tskid)
+atomic_t *task_get_event_bitmap(task_id_t tskid)
 {
 	task_ *tsk = __task_id_to_ptr(tskid);
 
@@ -217,13 +221,12 @@ uint32_t switch_handler(int desched, task_id_t resched)
 	current = current_task;
 
 	if (IS_ENABLED(CONFIG_DEBUG_STACK_OVERFLOW) &&
-	    *current->stack != STACK_UNUSED_VALUE) {
+	    *current->stack != STACK_UNUSED_VALUE &&
+	    task_enabled(current - tasks)) {
 		panic_printf("\n\nStack overflow in %s task!\n",
 			     task_get_name(current - tasks));
 
-		if (IS_ENABLED(CONFIG_SOFTWARE_PANIC))
-			software_panic(PANIC_SW_STACK_OVERFLOW,
-				       current - tasks);
+		software_panic(PANIC_SW_STACK_OVERFLOW, current - tasks);
 	}
 
 	if (desched && !current->events) {
@@ -239,8 +242,7 @@ uint32_t switch_handler(int desched, task_id_t resched)
 	next = __task_id_to_ptr(__fls(tasks_ready & tasks_enabled));
 
 	/* Only the first ISR on the (nested IRQ) stack calculates time */
-	if (IS_ENABLED(CONFIG_TASK_PROFILING) &&
-	    __in_isr == 1) {
+	if (IS_ENABLED(CONFIG_TASK_PROFILING) && __in_isr == 1) {
 		/* Track time in interrupts */
 		uint32_t t = get_time().le.lo;
 
@@ -287,7 +289,7 @@ void __keep task_start_irq_handler(void *data)
 		irq_dist[irq]++;
 	else
 		/* Track total number of service calls */
-		deprecated_atomic_add(&svc_calls, 1);
+		atomic_add(&svc_calls, 1);
 
 	/* Only the outer ISR should keep track of the ISR start time */
 	if (__in_isr == 1) {
@@ -318,7 +320,7 @@ static uint32_t __wait_evt(int timeout_us, task_id_t resched)
 		ret = timer_arm(deadline, me);
 		ASSERT(ret == EC_SUCCESS);
 	}
-	while (!(evt = deprecated_atomic_read_clear(&tsk->events))) {
+	while (!(evt = atomic_clear(&tsk->events))) {
 		/* Remove ourself and get the next task in the scheduler */
 		__schedule(1, resched);
 		resched = TASK_ID_IDLE;
@@ -326,12 +328,12 @@ static uint32_t __wait_evt(int timeout_us, task_id_t resched)
 	if (timeout_us > 0) {
 		timer_cancel(me);
 		/* Ensure timer event is clear, we no longer care about it */
-		deprecated_atomic_clear_bits(&tsk->events, TASK_EVENT_TIMER);
+		atomic_clear_bits(&tsk->events, TASK_EVENT_TIMER);
 	}
 	return evt;
 }
 
-uint32_t task_set_event(task_id_t tskid, uint32_t event, int wait)
+void task_set_event(task_id_t tskid, uint32_t event)
 {
 	task_ *receiver = __task_id_to_ptr(tskid);
 
@@ -345,20 +347,15 @@ uint32_t task_set_event(task_id_t tskid, uint32_t event, int wait)
 	ASSERT(receiver);
 
 	/* Set the event bit in the receiver message bitmap */
-	deprecated_atomic_or(&receiver->events, event);
+	atomic_or(&receiver->events, event);
 
 	/* Re-schedule if priorities have changed */
 	if (in_interrupt_context()) {
 		/* The receiver might run again */
-		deprecated_atomic_or(&tasks_ready, 1 << tskid);
+		atomic_or(&tasks_ready, 1 << tskid);
 	} else {
-		if (wait)
-			return __wait_evt(-1, tskid);
-		else
-			__schedule(0, tskid);
+		__schedule(0, tskid);
 	}
-
-	return 0;
 }
 
 uint32_t task_wait_event(int timeout_us)
@@ -389,8 +386,7 @@ uint32_t task_wait_event_mask(uint32_t event_mask, int timeout_us)
 
 	/* Re-post any other events collected */
 	if (events & ~event_mask)
-		deprecated_atomic_or(&current_task->events,
-				     events & ~event_mask);
+		atomic_or(&current_task->events, events & ~event_mask);
 
 	return events & event_mask;
 }
@@ -406,12 +402,17 @@ void task_enable_all_tasks(void)
 
 void task_enable_task(task_id_t tskid)
 {
-	deprecated_atomic_or(&tasks_enabled, BIT(tskid));
+	atomic_or(&tasks_enabled, BIT(tskid));
+}
+
+bool task_enabled(task_id_t tskid)
+{
+	return tasks_enabled & BIT(tskid);
 }
 
 void task_disable_task(task_id_t tskid)
 {
-	deprecated_atomic_clear_bits(&tasks_enabled, BIT(tskid));
+	atomic_clear_bits(&tasks_enabled, BIT(tskid));
 
 	if (!in_interrupt_context() && tskid == task_get_current())
 		__schedule(0, 0);
@@ -455,15 +456,14 @@ void mutex_lock(struct mutex *mtx)
 	uint32_t id = 1 << task_get_current();
 
 	ASSERT(id != TASK_ID_INVALID);
-	deprecated_atomic_or(&mtx->waiters, id);
+	atomic_or(&mtx->waiters, id);
 
 	do {
 		old_val = 0;
-		__asm__ __volatile__(
-				ASM_LOCK_PREFIX "cmpxchg %1, %2\n"
-				: "=a" (old_val)
-				: "r" (value), "m" (mtx->lock), "a" (old_val)
-				: "memory");
+		__asm__ __volatile__(ASM_LOCK_PREFIX "cmpxchg %1, %2\n"
+				     : "=a"(old_val)
+				     : "r"(value), "m"(mtx->lock), "a"(old_val)
+				     : "memory");
 
 		if (old_val != 0) {
 			/* Contention on the mutex */
@@ -471,7 +471,7 @@ void mutex_lock(struct mutex *mtx)
 		}
 	} while (old_val);
 
-	deprecated_atomic_clear_bits(&mtx->waiters, id);
+	atomic_clear_bits(&mtx->waiters, id);
 }
 
 void mutex_unlock(struct mutex *mtx)
@@ -480,11 +480,10 @@ void mutex_unlock(struct mutex *mtx)
 	uint32_t old_val = 1, val = 0;
 	task_ *tsk = current_task;
 
-	__asm__ __volatile__(
-			ASM_LOCK_PREFIX "cmpxchg %1, %2\n"
-			: "=a" (old_val)
-			: "r" (val), "m" (mtx->lock), "a" (old_val)
-			: "memory");
+	__asm__ __volatile__(ASM_LOCK_PREFIX "cmpxchg %1, %2\n"
+			     : "=a"(old_val)
+			     : "r"(val), "m"(mtx->lock), "a"(old_val)
+			     : "memory");
 	if (old_val == 1)
 		waiters = mtx->waiters;
 	/* else? Does unlock fail - what to do then ? */
@@ -494,11 +493,11 @@ void mutex_unlock(struct mutex *mtx)
 		waiters &= ~BIT(id);
 
 		/* Somebody is waiting on the mutex */
-		task_set_event(id, TASK_EVENT_MUTEX, 0);
+		task_set_event(id, TASK_EVENT_MUTEX);
 	}
 
 	/* Ensure no event is remaining from mutex wake-up */
-	deprecated_atomic_clear_bits(&tsk->events, TASK_EVENT_MUTEX);
+	atomic_clear_bits(&tsk->events, TASK_EVENT_MUTEX);
 }
 
 void task_print_list(void)
@@ -513,7 +512,7 @@ void task_print_list(void)
 		       "StkUsed\n");
 
 	for (i = 0; i < TASK_ID_COUNT; i++) {
-		char is_ready = (tasks_ready & (1<<i)) ? 'R' : ' ';
+		char is_ready = ((uint32_t)tasks_ready & BIT(i)) ? 'R' : ' ';
 		uint32_t *sp;
 
 		int stackused = tasks_init[i].stack_size;
@@ -526,22 +525,22 @@ void task_print_list(void)
 		if (IS_ENABLED(CONFIG_FPU)) {
 			char use_fpu = tasks[i].use_fpu ? 'Y' : 'N';
 
-			ccprintf("%4d %c %-16s %08x %11.6lld  %3d/%3d %c\n",
-				 i, is_ready, task_get_name(i), tasks[i].events,
-				 tasks[i].runtime, stackused,
-				 tasks_init[i].stack_size, use_fpu);
+			ccprintf("%4d %c %-16s %08x %11.6lld  %3d/%3d %c\n", i,
+				 is_ready, task_get_name(i),
+				 (int)tasks[i].events, tasks[i].runtime,
+				 stackused, tasks_init[i].stack_size, use_fpu);
 		} else {
-			ccprintf("%4d %c %-16s %08x %11.6lld  %3d/%3d\n",
-				 i, is_ready, task_get_name(i), tasks[i].events,
-				 tasks[i].runtime, stackused,
-				 tasks_init[i].stack_size);
+			ccprintf("%4d %c %-16s %08x %11.6lld  %3d/%3d\n", i,
+				 is_ready, task_get_name(i),
+				 (int)tasks[i].events, tasks[i].runtime,
+				 stackused, tasks_init[i].stack_size);
 		}
 
 		cflush();
 	}
 }
 
-int command_task_info(int argc, char **argv)
+static int command_task_info(int argc, const char **argv)
 {
 	task_print_list();
 
@@ -557,8 +556,9 @@ int command_task_info(int argc, char **argv)
 				total += irq_dist[i];
 			}
 		}
-		ccprintf("Service calls:          %11d\n", svc_calls);
-		ccprintf("Total exceptions:       %11d\n", total + svc_calls);
+		ccprintf("Service calls:          %11d\n", (int)svc_calls);
+		ccprintf("Total exceptions:       %11d\n",
+			 total + (int)svc_calls);
 		ccprintf("Task switches:          %11d\n", task_switches);
 		ccprintf("Task switching started: %11.6lld s\n",
 			 task_start_time);
@@ -570,18 +570,15 @@ int command_task_info(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(taskinfo, command_task_info,
-			NULL,
-			"Print task info");
+DECLARE_CONSOLE_COMMAND(taskinfo, command_task_info, NULL, "Print task info");
 
-__maybe_unused
-static int command_task_ready(int argc, char **argv)
+__maybe_unused static int command_task_ready(int argc, const char **argv)
 {
 	if (argc < 2) {
-		ccprintf("tasks_ready: 0x%08x\n", tasks_ready);
+		ccprintf("tasks_ready: 0x%08x\n", (int)tasks_ready);
 	} else {
 		tasks_ready = strtoi(argv[1], NULL, 16);
-		ccprintf("Setting tasks_ready to 0x%08x\n", tasks_ready);
+		ccprintf("Setting tasks_ready to 0x%08x\n", (int)tasks_ready);
 		__schedule(0, 0);
 	}
 
@@ -589,8 +586,7 @@ static int command_task_ready(int argc, char **argv)
 }
 
 #ifdef CONFIG_CMD_TASKREADY
-DECLARE_CONSOLE_COMMAND(taskready, command_task_ready,
-			"[setmask]",
+DECLARE_CONSOLE_COMMAND(taskready, command_task_ready, "[setmask]",
 			"Print/set ready tasks");
 #endif
 
@@ -599,7 +595,7 @@ void task_pre_init(void)
 	int i, cs;
 	uint32_t *stack_next = (uint32_t *)task_stacks;
 
-	__asm__ __volatile__ ("movl %%cs, %0":"=r" (cs));
+	__asm__ __volatile__("movl %%cs, %0" : "=r"(cs));
 
 	/* Fill the task memory with initial values */
 	for (i = 0; i < TASK_ID_COUNT; i++) {
@@ -631,12 +627,12 @@ void task_pre_init(void)
 		sp[7] = 0xea;	/* EAX */
 #endif
 		/* For IRET */
-		sp[8] = tasks_init[i].pc;	/* pc */
+		sp[8] = tasks_init[i].pc; /* pc */
 		sp[9] = cs;
 		sp[10] = INITIAL_EFLAGS;
 
-		sp[11] = (uint32_t) task_exit_trap;
-		sp[12] = tasks_init[i].r0;	/* task argument */
+		sp[11] = (uint32_t)task_exit_trap;
+		sp[12] = tasks_init[i].r0; /* task argument */
 		sp[13] = 0x00;
 		sp[14] = 0x00;
 		sp[15] = 0x00;
@@ -649,7 +645,8 @@ void task_pre_init(void)
 				0x00, 0x00, /* Status[0-15] */
 				0xff, 0xff, /* unused */
 				0xff, 0xff, /* Tag[0-15] */
-				0xff, 0xff};/* unused */
+				0xff, 0xff
+			}; /* unused */
 
 			/* Copy default x86 FPU state for each task */
 			memcpy(tasks[i].fp_ctx, default_fp_ctx,
diff --git a/core/minute-ia/task_defs.h b/core/minute-ia/task_defs.h
index 01632392cb..dac80e0eb9 100644
--- a/core/minute-ia/task_defs.h
+++ b/core/minute-ia/task_defs.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,21 +7,22 @@
 #define __CROS_EC_TASK_DEFS_H
 
 #ifdef CONFIG_FPU
-#define FPU_CTX_SZ		108  /* 28 bytes header + 80 bytes registers */
-#define USE_FPU_OFFSET		20   /* offsetof(task_, use_fpu */
-#define FPU_CTX_OFFSET		24   /* offsetof(task_, fp_ctx) */
+#define FPU_CTX_SZ 108 /* 28 bytes header + 80 bytes registers */
+#define USE_FPU_OFFSET 20 /* offsetof(task_, use_fpu */
+#define FPU_CTX_OFFSET 24 /* offsetof(task_, fp_ctx) */
 
 /*
  * defines for inline asm
  */
 #ifndef __ASSEMBLER__
+#include "atomic.h"
 #include "common.h"
 
-#define USE_FPU_OFFSET_STR	STRINGIFY(USE_FPU_OFFSET)	/* "20" */
-#define FPU_CTX_OFFSET_STR	STRINGIFY(FPU_CTX_OFFSET)	/* "24" */
+#define USE_FPU_OFFSET_STR STRINGIFY(USE_FPU_OFFSET) /* "20" */
+#define FPU_CTX_OFFSET_STR STRINGIFY(FPU_CTX_OFFSET) /* "24" */
 
-asm (".equ USE_FPU_OFFSET, "USE_FPU_OFFSET_STR);
-asm (".equ FPU_CTX_OFFSET, "FPU_CTX_OFFSET_STR);
+asm(".equ USE_FPU_OFFSET, " USE_FPU_OFFSET_STR);
+asm(".equ FPU_CTX_OFFSET, " FPU_CTX_OFFSET_STR);
 
 #endif
 #endif /* CONFIG_FPU */
@@ -33,12 +34,12 @@ typedef union {
 		 * Note that sp must be the first element in the task struct
 		 * for __switchto() to work.
 		 */
-		uint32_t sp;	/* Saved stack pointer for context switch */
-		uint32_t events;	/* Bitmaps of received events */
-		uint64_t runtime;	/* Time spent in task */
-		uint32_t *stack;	/* Start of stack */
+		uint32_t sp; /* Saved stack pointer for context switch */
+		atomic_t events; /* Bitmaps of received events */
+		uint64_t runtime; /* Time spent in task */
+		uint32_t *stack; /* Start of stack */
 #ifdef CONFIG_FPU
-		uint32_t use_fpu;	/* set if task uses FPU */
+		uint32_t use_fpu; /* set if task uses FPU */
 		uint8_t fp_ctx[FPU_CTX_SZ]; /* x87 FPU context */
 #endif
 	};
@@ -49,7 +50,7 @@ void __switchto(void);
 void sw_irq_handler(void);
 
 /* Only the IF bit is set so tasks start with interrupts enabled. */
-#define INITIAL_EFLAGS		(0x200UL)
+#define INITIAL_EFLAGS (0x200UL)
 
 /* LAPIC ICR bit fields
  *	7:0	- vector
@@ -60,7 +61,7 @@ void sw_irq_handler(void);
  *	15	- Trigger mode (0 = edge)
  *	20:18	- Destination (1 = self)
  */
-#define LAPIC_ICR_BITS		0x44000
+#define LAPIC_ICR_BITS 0x44000
 
 #endif /* __ASSEMBLER__ */
 #endif /* __CROS_EC_TASK_DEFS_H */
diff --git a/core/minute-ia/toolchain.mk b/core/minute-ia/toolchain.mk
new file mode 100644
index 0000000000..0ddbf3d4ec
--- /dev/null
+++ b/core/minute-ia/toolchain.mk
@@ -0,0 +1,15 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+ifeq ($(cc-name),gcc)
+# coreboot sdk
+CROSS_COMPILE_X86_DEFAULT:=/opt/coreboot-sdk/bin/i386-elf-
+else
+# llvm sdk
+CROSS_COMPILE_X86_DEFAULT:=
+endif
+
+$(call set-option,CROSS_COMPILE,\
+	$(CROSS_COMPILE_x86),\
+	$(CROSS_COMPILE_X86_DEFAULT))
diff --git a/core/nds32/__builtin.c b/core/nds32/__builtin.c
index 7b1d5eea62..ae8aa4b053 100644
--- a/core/nds32/__builtin.c
+++ b/core/nds32/__builtin.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/core/nds32/__divdi3.S b/core/nds32/__divdi3.S
index d86e8f6273..36fe00a917 100644
--- a/core/nds32/__divdi3.S
+++ b/core/nds32/__divdi3.S
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/nds32/__libsoftfpu.S b/core/nds32/__libsoftfpu.S
index 672e6bbb3d..3f2e60767f 100644
--- a/core/nds32/__libsoftfpu.S
+++ b/core/nds32/__libsoftfpu.S
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/core/nds32/__muldi3.S b/core/nds32/__muldi3.S
index ef4a491183..0e766de3cb 100644
--- a/core/nds32/__muldi3.S
+++ b/core/nds32/__muldi3.S
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/nds32/__udivdi3.S b/core/nds32/__udivdi3.S
index 4cb3b058fe..624faff2c5 100644
--- a/core/nds32/__udivdi3.S
+++ b/core/nds32/__udivdi3.S
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/nds32/atomic.h b/core/nds32/atomic.h
index d93d1e7b06..746093c919 100644
--- a/core/nds32/atomic.h
+++ b/core/nds32/atomic.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,59 +8,81 @@
 #ifndef __CROS_EC_ATOMIC_H
 #define __CROS_EC_ATOMIC_H
 
+#include "atomic_t.h"
 #include "common.h"
 #include "cpu.h"
 #include "task.h"
 
-/*
- * The atomic_* functions are marked as deprecated as a part of the process of
- * transaction to Zephyr compatible atomic functions. These prefixes will be
- * removed in the following patches. Please see b:169151160 for more details.
- */
+static inline atomic_val_t atomic_clear_bits(atomic_t *addr, atomic_val_t bits)
+{
+	atomic_val_t ret;
+	atomic_t volatile *ptr = addr;
+	uint32_t int_mask = read_clear_int_mask();
 
-static inline void deprecated_atomic_clear_bits(uint32_t volatile *addr,
-						uint32_t bits)
+	ret = *ptr;
+	*ptr &= ~bits;
+	set_int_mask(int_mask);
+	return ret;
+}
+
+static inline atomic_val_t atomic_or(atomic_t *addr, atomic_val_t bits)
 {
+	atomic_val_t ret;
+	atomic_t volatile *ptr = addr;
 	uint32_t int_mask = read_clear_int_mask();
 
-	*addr &= ~bits;
+	ret = *ptr;
+	*ptr |= bits;
 	set_int_mask(int_mask);
+	return ret;
 }
 
-static inline void deprecated_atomic_or(uint32_t volatile *addr, uint32_t bits)
+static inline atomic_val_t atomic_add(atomic_t *addr, atomic_val_t value)
 {
+	atomic_val_t ret;
+	atomic_t volatile *ptr = addr;
 	uint32_t int_mask = read_clear_int_mask();
 
-	*addr |= bits;
+	ret = *ptr;
+	*ptr += value;
 	set_int_mask(int_mask);
+	return ret;
 }
 
-static inline void deprecated_atomic_add(uint32_t volatile *addr,
-					 uint32_t value)
+static inline atomic_val_t atomic_sub(atomic_t *addr, atomic_val_t value)
 {
+	atomic_val_t ret;
+	atomic_t volatile *ptr = addr;
 	uint32_t int_mask = read_clear_int_mask();
 
-	*addr += value;
+	ret = *ptr;
+	*ptr -= value;
 	set_int_mask(int_mask);
+	return ret;
 }
 
-static inline void deprecated_atomic_sub(uint32_t volatile *addr,
-					 uint32_t value)
+static inline atomic_val_t atomic_clear(atomic_t *addr)
 {
+	atomic_val_t ret;
+	atomic_t volatile *ptr = addr;
 	uint32_t int_mask = read_clear_int_mask();
 
-	*addr -= value;
+	ret = *ptr;
+	*ptr = 0;
 	set_int_mask(int_mask);
+	return ret;
 }
 
-static inline uint32_t deprecated_atomic_read_clear(uint32_t volatile *addr)
+static inline atomic_val_t atomic_and(atomic_t *addr, atomic_val_t bits)
 {
-	uint32_t val;
+	atomic_val_t ret;
+	atomic_t volatile *ptr = addr;
 	uint32_t int_mask = read_clear_int_mask();
 
-	val = *addr;
-	*addr = 0;
+	ret = *ptr;
+	*ptr &= bits;
 	set_int_mask(int_mask);
-	return val;
+	return ret;
 }
-#endif  /* __CROS_EC_ATOMIC_H */
+
+#endif /* __CROS_EC_ATOMIC_H */
diff --git a/core/nds32/build.mk b/core/nds32/build.mk
index ddd65c680b..7790b96009 100644
--- a/core/nds32/build.mk
+++ b/core/nds32/build.mk
@@ -1,17 +1,11 @@
 # -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
+# Copyright 2013 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
 # Andestar v3m architecture core OS files build
 #
 
-# Set coreboot-sdk as the default toolchain for nds32
-NDS32_DEFAULT_COMPILE=/opt/coreboot-sdk/bin/nds32le-elf-
-
-# Select Andes bare-metal toolchain
-$(call set-option,CROSS_COMPILE,$(CROSS_COMPILE_nds32),$(NDS32_DEFAULT_COMPILE))
-
 # CPU specific compilation flags
 CFLAGS_CPU+=-march=v3m -Os
 LDFLAGS_EXTRA+=-mrelax
diff --git a/core/nds32/config_core.h b/core/nds32/config_core.h
index 7670e5cfad..094a86f76a 100644
--- a/core/nds32/config_core.h
+++ b/core/nds32/config_core.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,8 +10,6 @@
 #define BFD_ARCH nds32
 #define BFD_FORMAT "elf32-nds32le"
 
-#define CONFIG_SOFTWARE_PANIC
-
 /*
  * The Andestar v3m architecture has no CLZ/CTZ instructions (contrary to v3),
  * so let's use the software implementation.
diff --git a/core/nds32/cpu.c b/core/nds32/cpu.c
index 6a3f3b5bc4..cfdddb334e 100644
--- a/core/nds32/cpu.c
+++ b/core/nds32/cpu.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -12,5 +12,5 @@ void cpu_init(void)
 {
 	/* DLM initialization is done in init.S */
 	/* Global interrupt enable */
-	asm volatile ("setgie.e");
+	asm volatile("setgie.e");
 }
diff --git a/core/nds32/cpu.h b/core/nds32/cpu.h
index 3bd5a93efc..54d1a243ba 100644
--- a/core/nds32/cpu.h
+++ b/core/nds32/cpu.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -15,9 +15,9 @@
 #define TASK_SCRATCHPAD_SIZE (18)
 
 /* Process Status Word bits */
-#define PSW_GIE		BIT(0) /* Global Interrupt Enable */
-#define PSW_INTL_SHIFT	1        /* Interrupt Stack Level */
-#define PSW_INTL_MASK	(0x3 << PSW_INTL_SHIFT)
+#define PSW_GIE BIT(0) /* Global Interrupt Enable */
+#define PSW_INTL_SHIFT 1 /* Interrupt Stack Level */
+#define PSW_INTL_MASK (0x3 << PSW_INTL_SHIFT)
 
 #ifndef __ASSEMBLER__
 
@@ -26,28 +26,28 @@
 /* write Process Status Word privileged register */
 static inline void set_psw(uint32_t val)
 {
-	asm volatile ("mtsr %0, $PSW" : : "r"(val));
+	asm volatile("mtsr %0, $PSW" : : "r"(val));
 }
 
 /* read Process Status Word privileged register */
 static inline uint32_t get_psw(void)
 {
 	uint32_t ret;
-	asm volatile ("mfsr %0, $PSW" : "=r"(ret));
+	asm volatile("mfsr %0, $PSW" : "=r"(ret));
 	return ret;
 }
 
 /* write Interruption Program Counter privileged register */
 static inline void set_ipc(uint32_t val)
 {
-	asm volatile ("mtsr %0, $IPC" : : "r"(val));
+	asm volatile("mtsr %0, $IPC" : : "r"(val));
 }
 
 /* read Interruption Program Counter privileged register */
 static inline uint32_t get_ipc(void)
 {
 	uint32_t ret;
-	asm volatile ("mfsr %0, $IPC" : "=r"(ret));
+	asm volatile("mfsr %0, $IPC" : "=r"(ret));
 	return ret;
 }
 
@@ -55,7 +55,7 @@ static inline uint32_t get_ipc(void)
 static inline uint32_t get_itype(void)
 {
 	uint32_t ret;
-	asm volatile ("mfsr %0, $ITYPE" : "=r"(ret));
+	asm volatile("mfsr %0, $ITYPE" : "=r"(ret));
 	return ret;
 }
 
diff --git a/core/nds32/ec.lds.S b/core/nds32/ec.lds.S
index 98edb36c3f..7d77afbc36 100644
--- a/core/nds32/ec.lds.S
+++ b/core/nds32/ec.lds.S
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,7 +22,7 @@ MEMORY
 {
 	FLASH (rx) : ORIGIN = FW_OFF(SECTION), LENGTH = FW_SIZE(SECTION)
 	IRAM (rw)  : ORIGIN = CONFIG_RAM_BASE, LENGTH = CONFIG_RAM_SIZE
-#if defined(CONFIG_HOSTCMD_X86) || defined(CONFIG_I2C_SLAVE)
+#if defined(CONFIG_HOSTCMD_X86) || defined(CONFIG_I2C_PERIPHERAL)
 	H2RAM (rw) : ORIGIN = CONFIG_H2RAM_BASE, LENGTH = CONFIG_H2RAM_SIZE
 #endif
 }
@@ -131,6 +131,10 @@ SECTIONS
 		KEEP(*(.rodata.HOOK_CHIPSET_SHUTDOWN_COMPLETE))
 		__hooks_chipset_shutdown_complete_end = .;
 
+		__hooks_chipset_hard_off = .;
+		KEEP(*(.rodata.HOOK_CHIPSET_HARD_OFF))
+		__hooks_chipset_hard_off_end = .;
+
 		__hooks_chipset_reset = .;
 		KEEP(*(.rodata.HOOK_CHIPSET_RESET))
 		__hooks_chipset_reset_end = .;
@@ -147,6 +151,12 @@ SECTIONS
 		KEEP(*(.rodata.HOOK_TABLET_MODE_CHANGE))
 		__hooks_tablet_mode_change_end = .;
 
+#ifdef CONFIG_BODY_DETECTION
+		__hooks_body_detect_change = .;
+		KEEP(*(.rodata.HOOK_BODY_DETECT_CHANGE))
+		__hooks_body_detect_change_end = .;
+#endif
+
 		__hooks_base_attached_change = .;
 		KEEP(*(.rodata.HOOK_BASE_ATTACHED_CHANGE))
 		__hooks_base_attached_change_end = .;
@@ -181,6 +191,10 @@ SECTIONS
 		KEEP(*(.rodata.HOOK_USB_PD_CONNECT))
 		__hooks_usb_pd_connect_end = .;
 
+		__hooks_power_supply_change = .;
+		KEEP(*(.rodata.HOOK_POWER_SUPPLY_CHANGE))
+		__hooks_power_supply_change_end = .;
+
 		__deferred_funcs = .;
 		KEEP(*(.rodata.deferred))
 		__deferred_funcs_end = .;
@@ -201,7 +215,7 @@ SECTIONS
 		*(.init.rom)
 		__init_rom_end = .;
 
-#if defined(SECTION_IS_RO) && defined(CONFIG_FLASH)
+#if defined(SECTION_IS_RO) && defined(CONFIG_FLASH_CROS)
 		. = ALIGN(64);
 		KEEP(*(.google))
 #endif
@@ -244,7 +258,6 @@ SECTIONS
 		*(.bss.task_scratchpad)
 		/* Rest of .bss takes care of its own alignment */
 		*(.bss)
-		*(.bss.slow)
 
 		/*
 		 * Reserve space for deferred function firing times.
@@ -274,31 +287,42 @@ SECTIONS
 		     (__shared_mem_buf + CONFIG_SHAREDMEM_MINIMUM_SIZE);
 
 	/*
-	 * __flash_used is used in flash free calculations by the makefile.
+	 * __flash_used and __flash_size is used in flash free calculations by
+	 * the makefile. Note the difference between __flash_size and
+	 * __config_flash_size. __flash_size is the flash size for the given
+	 * image (RW, RO, etc.), while __config_flash_size is the *total*
+	 * flash size.
 	 * __image_size is stored in the struct image_data header and used
-	 * in hash calcuations.
+	 * in hash calculations.
 	 */
 	__flash_used = LOADADDR(.data) + SIZEOF(.data) - FW_OFF(SECTION);
+	__flash_size = LENGTH(FLASH);
 	__image_size = __flash_used;
 
-#ifdef CONFIG_FLASH
+#if defined(SECTION_IS_RW) && (CONFIG_FLASH_WRITE_SIZE > 0)
+	/* Alignment is needed by flash_command_write() for RW update. */
+	ASSERT(__image_size % CONFIG_FLASH_WRITE_SIZE == 0,
+	       "Error: RW image is not aligned to CONFIG_FLASH_WRITE_SIZE")
+#endif
+
+#ifdef CONFIG_FLASH_CROS
         /*
          * These linker labels are just for analysis and not used in the code.
          */
-	__config_flash_size = CONFIG_FLASH_SIZE;
+	__config_flash_size = CONFIG_FLASH_SIZE_BYTES;
 	__config_ro_size = CONFIG_RO_SIZE;
 	__config_ec_protected_storage_size = CONFIG_EC_PROTECTED_STORAGE_SIZE;
 	__config_rw_size = CONFIG_RW_SIZE;
 	__config_ec_writable_storage_size = CONFIG_EC_WRITABLE_STORAGE_SIZE;
 #endif
 
-#if defined(CONFIG_HOSTCMD_X86) || defined(CONFIG_I2C_SLAVE)
+#if defined(CONFIG_HOSTCMD_X86) || defined(CONFIG_I2C_PERIPHERAL)
 	.h2ram (NOLOAD) : {
 		. += CONFIG_H2RAM_HOST_LPC_IO_BASE;
 		*(.h2ram.pool.hostcmd)
 		. = ALIGN(256);
 		*(.h2ram.pool.acpiec)
-#ifdef CONFIG_I2C_SLAVE
+#ifdef CONFIG_I2C_PERIPHERAL
 		. = ALIGN(256);
 		*(.h2ram.pool.i2cslv)
 #endif
@@ -309,7 +333,7 @@ SECTIONS
 	       "Not enough space for h2ram section.")
 #endif
 
-#if !(defined(SECTION_IS_RO) && defined(CONFIG_FLASH))
+#if !(defined(SECTION_IS_RO) && defined(CONFIG_FLASH_CROS))
 	/DISCARD/ : { *(.google) }
 #endif
 
diff --git a/core/nds32/include/fpu.h b/core/nds32/include/fpu.h
new file mode 100644
index 0000000000..80c3395d14
--- /dev/null
+++ b/core/nds32/include/fpu.h
@@ -0,0 +1,14 @@
+/* Copyright 2017 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Math utility functions for N8 */
+
+#ifndef __CROS_EC_FPU_H
+#define __CROS_EC_FPU_H
+
+float sqrtf(float x);
+float fabsf(float x);
+
+#endif /* __CROS_EC_FPU_H */
diff --git a/core/nds32/include/math.h b/core/nds32/include/math.h
deleted file mode 100644
index 49d5585657..0000000000
--- a/core/nds32/include/math.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Math utility functions for N8 */
-
-#ifndef __CROS_EC_MATH_H
-#define __CROS_EC_MATH_H
-
-float sqrtf(float x);
-float fabsf(float x);
-
-#endif  /* __CROS_EC_MATH_H */
diff --git a/core/nds32/init.S b/core/nds32/init.S
index b8e109c434..648e3d8183 100644
--- a/core/nds32/init.S
+++ b/core/nds32/init.S
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -87,7 +87,7 @@ vector irq_15,   15	/* HW 15 */
 .global eflash_sig
 eflash_sig:
 .byte 0xA5, 0xA5, 0xA5, 0xA5, 0xA5, 0xA5
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 .byte 0xA4 /* eSPI */
 #else
 .byte 0xA5 /* LPC */
diff --git a/core/nds32/irq_chip.h b/core/nds32/irq_chip.h
index ca517558b3..a339bb516c 100644
--- a/core/nds32/irq_chip.h
+++ b/core/nds32/irq_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/nds32/irq_handler.h b/core/nds32/irq_handler.h
index b37b7927ef..b1feaa44c3 100644
--- a/core/nds32/irq_handler.h
+++ b/core/nds32/irq_handler.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,11 +15,12 @@
  * Macro to connect the interrupt handler "routine" to the irq number "irq" and
  * ensure it is enabled in the interrupt controller with the right priority.
  */
-#define DECLARE_IRQ(irq, routine, priority)				\
-	void IRQ_HANDLER(CPU_INT(irq))(void)				\
-		__attribute__ ((alias(STRINGIFY(routine))));		\
-	const struct irq_priority __keep IRQ_PRIORITY(CPU_INT(irq))	\
-	__attribute__((section(".rodata.irqprio")))			\
-			= {CPU_INT(irq), priority}
+#define DECLARE_IRQ(irq, routine, priority)                                   \
+	static void __keep routine(void);                                     \
+	void IRQ_HANDLER(CPU_INT(irq))(void)                                  \
+		__attribute__((alias(STRINGIFY(routine))));                   \
+	const struct irq_priority __keep IRQ_PRIORITY(CPU_INT(irq))           \
+		__attribute__((section(".rodata.irqprio"))) = { CPU_INT(irq), \
+								priority }
 
-#endif  /* __CROS_EC_IRQ_HANDLER_H */
+#endif /* __CROS_EC_IRQ_HANDLER_H */
diff --git a/core/nds32/math.c b/core/nds32/math.c
index 496fcc0e5d..d0c8fc5c33 100644
--- a/core/nds32/math.c
+++ b/core/nds32/math.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,19 +12,19 @@ union ieee_float_shape_type {
 };
 
 /* Get a 32 bit int from a float.  */
-#define GET_FLOAT_WORD(i, d) \
-	do { \
+#define GET_FLOAT_WORD(i, d)                      \
+	do {                                      \
 		union ieee_float_shape_type gf_u; \
-		gf_u.value = (d); \
-		(i) = gf_u.word; \
+		gf_u.value = (d);                 \
+		(i) = gf_u.word;                  \
 	} while (0)
 
 /* Set a float from a 32 bit int. */
-#define SET_FLOAT_WORD(d, i) \
-	do { \
+#define SET_FLOAT_WORD(d, i)                      \
+	do {                                      \
 		union ieee_float_shape_type sf_u; \
-		sf_u.word = (i); \
-		(d) = sf_u.value; \
+		sf_u.word = (i);                  \
+		(d) = sf_u.value;                 \
 	} while (0)
 
 float fabsf(float x)
diff --git a/core/nds32/panic.c b/core/nds32/panic.c
index 70e2cae3e0..b50da13e2c 100644
--- a/core/nds32/panic.c
+++ b/core/nds32/panic.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,6 +10,7 @@
 #include "printf.h"
 #include "software_panic.h"
 #include "system.h"
+#include "system_safe_mode.h"
 #include "task.h"
 #include "timer.h"
 #include "util.h"
@@ -17,7 +18,7 @@
 /* General purpose register (r6) for saving software panic reason */
 #define SOFT_PANIC_GPR_REASON 6
 /* General purpose register (r7) for saving software panic information */
-#define SOFT_PANIC_GPR_INFO   7
+#define SOFT_PANIC_GPR_INFO 7
 
 #ifdef CONFIG_DEBUG_EXCEPTIONS
 /**
@@ -46,7 +47,7 @@
  * All other exceptions not in the abovetable should have the INST field of
  * the ITYPE register set to 0.
  */
-static const char * const itype_inst[2] = {
+static const char *const itype_inst[2] = {
 	"a data memory access",
 	"an instruction fetch access",
 };
@@ -54,7 +55,7 @@ static const char * const itype_inst[2] = {
 /**
  * bit[3-0] @ ITYPE, general exception type information.
  */
-static const char * const itype_exc_type[16] = {
+static const char *const itype_exc_type[16] = {
 	"Alignment check",
 	"Reserved instruction",
 	"Trap",
@@ -75,11 +76,10 @@ static const char * const itype_exc_type[16] = {
 };
 #endif /* CONFIG_DEBUG_EXCEPTIONS */
 
-#ifdef CONFIG_SOFTWARE_PANIC
 void software_panic(uint32_t reason, uint32_t info)
 {
-	asm volatile ("mov55  $r6, %0" : : "r"(reason));
-	asm volatile ("mov55  $r7, %0" : : "r"(info));
+	asm volatile("mov55  $r6, %0" : : "r"(reason));
+	asm volatile("mov55  $r7, %0" : : "r"(info));
 	if (in_interrupt_context())
 		asm("j excep_handler");
 	else
@@ -94,7 +94,7 @@ void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
 	 * If it was called earlier (eg. when saving nds_n8.ipc) calling it
 	 * once again won't remove any data
 	 */
-	struct panic_data * const pdata = get_panic_data_write();
+	struct panic_data *const pdata = get_panic_data_write();
 	uint32_t warning_ipc;
 	uint32_t *regs;
 
@@ -121,7 +121,7 @@ void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
 
 void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception)
 {
-	struct panic_data * const pdata = panic_get_data();
+	struct panic_data *const pdata = panic_get_data();
 	uint32_t *regs;
 
 	if (pdata && pdata->struct_version == 2) {
@@ -133,20 +133,27 @@ void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception)
 		*exception = *reason = *info = 0;
 	}
 }
-#endif /* CONFIG_SOFTWARE_PANIC */
+
+/**
+ * Returns the SP register
+ */
+uint32_t get_panic_stack_pointer(const struct panic_data *pdata)
+{
+	return pdata->nds_n8.regs[15];
+}
 
 static void print_panic_information(uint32_t *regs, uint32_t itype,
-					uint32_t ipc, uint32_t ipsw)
+				    uint32_t ipc, uint32_t ipsw)
 {
 	panic_printf("=== EXCEP: ITYPE=%x ===\n", itype);
-	panic_printf("R0  %08x R1  %08x R2  %08x R3  %08x\n",
-		     regs[0], regs[1], regs[2], regs[3]);
-	panic_printf("R4  %08x R5  %08x R6  %08x R7  %08x\n",
-		     regs[4], regs[5], regs[6], regs[7]);
-	panic_printf("R8  %08x R9  %08x R10 %08x R15 %08x\n",
-		     regs[8], regs[9], regs[10], regs[11]);
-	panic_printf("FP  %08x GP  %08x LP  %08x SP  %08x\n",
-		     regs[12], regs[13], regs[14], regs[15]);
+	panic_printf("R0  %08x R1  %08x R2  %08x R3  %08x\n", regs[0], regs[1],
+		     regs[2], regs[3]);
+	panic_printf("R4  %08x R5  %08x R6  %08x R7  %08x\n", regs[4], regs[5],
+		     regs[6], regs[7]);
+	panic_printf("R8  %08x R9  %08x R10 %08x R15 %08x\n", regs[8], regs[9],
+		     regs[10], regs[11]);
+	panic_printf("FP  %08x GP  %08x LP  %08x SP  %08x\n", regs[12],
+		     regs[13], regs[14], regs[15]);
 	panic_printf("IPC %08x IPSW   %05x\n", ipc, ipsw);
 	if ((ipsw & PSW_INTL_MASK) == (2 << PSW_INTL_SHIFT)) {
 		/* 2nd level exception */
@@ -159,18 +166,16 @@ static void print_panic_information(uint32_t *regs, uint32_t itype,
 #ifdef CONFIG_DEBUG_EXCEPTIONS
 	panic_printf("SWID of ITYPE: %x\n", ((itype >> 16) & 0x7fff));
 	if (panic_sw_reason_is_valid(regs[SOFT_PANIC_GPR_REASON])) {
-#ifdef CONFIG_SOFTWARE_PANIC
 		panic_printf("Software panic reason %s\n",
-			panic_sw_reasons[(regs[SOFT_PANIC_GPR_REASON] -
-					  PANIC_SW_BASE)]);
+			     panic_sw_reasons[(regs[SOFT_PANIC_GPR_REASON] -
+					       PANIC_SW_BASE)]);
 		panic_printf("Software panic info 0x%x\n",
-			regs[SOFT_PANIC_GPR_INFO]);
-#endif
+			     regs[SOFT_PANIC_GPR_INFO]);
 	} else {
 		panic_printf("Exception type: General exception [%s]\n",
-			itype_exc_type[(itype & 0xf)]);
+			     itype_exc_type[(itype & 0xf)]);
 		panic_printf("Exception is caused by %s\n",
-			itype_inst[(itype & BIT(4))]);
+			     itype_inst[(itype & BIT(4))]);
 	}
 #endif
 }
@@ -178,7 +183,7 @@ static void print_panic_information(uint32_t *regs, uint32_t itype,
 void report_panic(uint32_t *regs, uint32_t itype)
 {
 	int i;
-	struct panic_data * const pdata = get_panic_data_write();
+	struct panic_data *const pdata = get_panic_data_write();
 
 	pdata->magic = PANIC_DATA_MAGIC;
 	pdata->struct_size = CONFIG_PANIC_DATA_SIZE;
@@ -194,6 +199,26 @@ void report_panic(uint32_t *regs, uint32_t itype)
 	pdata->nds_n8.ipsw = regs[17];
 
 	print_panic_information(regs, itype, regs[16], regs[17]);
+
+	if (IS_ENABLED(CONFIG_SYSTEM_SAFE_MODE)) {
+		if (start_system_safe_mode() == EC_SUCCESS) {
+			pdata->flags |= PANIC_DATA_FLAG_SAFE_MODE_STARTED;
+			/* If not in an interrupt context (e.g. software_panic),
+			 * the next highest priority task will immediately
+			 * execute when the current task is disabled on the
+			 * following line.
+			 */
+			task_disable_task(task_get_current());
+			/* Current task has been disabled.
+			 * Returning from the exception here should cause the
+			 * highest priority task that wasn't disabled to run.
+			 */
+			asm("iret");
+			__builtin_unreachable();
+		}
+		pdata->flags |= PANIC_DATA_FLAG_SAFE_MODE_FAIL_PRECONDITIONS;
+	}
+
 	panic_reboot();
 }
 
diff --git a/core/nds32/switch.S b/core/nds32/switch.S
index 8696ef5f00..e7a8584ce5 100644
--- a/core/nds32/switch.S
+++ b/core/nds32/switch.S
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,7 +8,7 @@
 #include "config.h"
 #include "cpu.h"
 
-.text
+.section .ram_code
 
 /**
  * Task context switching
@@ -73,6 +73,7 @@ __switch_task:
 	/* restore PC and PSW */
 	iret
 
+.text
 /**
  * Start the task scheduling.
  *
@@ -81,6 +82,11 @@ __switch_task:
  */
 .global __task_start
 __task_start:
+	/*
+	 * Disable global interrupt here to ensure below sequence won't be
+	 * broken. The "iret" instruction of ISR will enable GIE again.
+	 */
+	setgie.d
 	/* area used as thread stack for the first switch */
 	la $r3, scratchpad
 
@@ -100,4 +106,3 @@ __task_start:
 	/* we should never return here: set code to EC_ERROR_UNKNOWN */
 	movi55 $r0, 0x1
 	ret5   $lp
-
diff --git a/core/nds32/task.c b/core/nds32/task.c
index 9c3d6357ac..bbfc5f79c7 100644
--- a/core/nds32/task.c
+++ b/core/nds32/task.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,6 +6,7 @@
 /* Task scheduling / events module for Chrome EC operating system */
 
 #include "atomic.h"
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
 #include "cpu.h"
@@ -13,6 +14,7 @@
 #include "intc.h"
 #include "irq_chip.h"
 #include "link_defs.h"
+#include "panic.h"
 #include "registers.h"
 #include "task.h"
 #include "timer.h"
@@ -24,10 +26,10 @@ typedef union {
 		 * Note that sp must be the first element in the task struct
 		 * for __switchto() to work.
 		 */
-		uint32_t sp;       /* Saved stack pointer for context switch */
-		uint32_t events;   /* Bitmaps of received events */
-		uint64_t runtime;  /* Time spent in task */
-		uint32_t *stack;   /* Start of stack */
+		uint32_t sp; /* Saved stack pointer for context switch */
+		atomic_t events; /* Bitmaps of received events */
+		uint64_t runtime; /* Time spent in task */
+		uint32_t *stack; /* Start of stack */
 	};
 } task_;
 
@@ -42,11 +44,9 @@ CONFIG_TEST_TASK_LIST
 #undef TASK
 
 /* Task names for easier debugging */
-#define TASK(n, r, d, s)  #n,
-static const char * const task_names[] = {
-	"<< idle >>",
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
+#define TASK(n, r, d, s) #n,
+static const char *const task_names[] = {
+	"<< idle >>", CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST
 };
 #undef TASK
 
@@ -54,12 +54,12 @@ static const char * const task_names[] = {
 static int task_will_switch;
 static uint32_t exc_sub_time;
 static uint64_t task_start_time; /* Time task scheduling started */
-static uint32_t exc_start_time;  /* Time of task->exception transition */
-static uint32_t exc_end_time;    /* Time of exception->task transition */
-static uint64_t exc_total_time;  /* Total time in exceptions */
-static uint32_t svc_calls;       /* Number of service calls */
-static uint32_t task_switches;   /* Number of times active task changed */
-static uint32_t irq_dist[CONFIG_IRQ_COUNT];  /* Distribution of IRQ calls */
+static uint32_t exc_start_time; /* Time of task->exception transition */
+static uint32_t exc_end_time; /* Time of exception->task transition */
+static uint64_t exc_total_time; /* Total time in exceptions */
+static uint32_t svc_calls; /* Number of service calls */
+static uint32_t task_switches; /* Number of times active task changed */
+static uint32_t irq_dist[CONFIG_IRQ_COUNT]; /* Distribution of IRQ calls */
 #endif
 
 extern int __task_start(void);
@@ -80,7 +80,7 @@ void __idle(void)
 		/* doze mode */
 		IT83XX_ECPM_PLLCTRL = EC_PLL_DOZE;
 #endif
-		asm volatile ("dsb");
+		asm volatile("dsb");
 		/*
 		 * Wait for the next irq event.  This stops the CPU clock
 		 * (sleep / deep sleep, depending on chip config).
@@ -100,42 +100,36 @@ static void task_exit_trap(void)
 }
 
 /* Startup parameters for all tasks. */
-#define TASK(n, r, d, s)  {	\
-	.r0 = (uint32_t)d,	\
-	.pc = (uint32_t)r,	\
-	.stack_size = s,	\
-},
+#define TASK(n, r, d, s)           \
+	{                          \
+		.r0 = (uint32_t)d, \
+		.pc = (uint32_t)r, \
+		.stack_size = s,   \
+	},
 static const struct {
 	uint32_t r0;
 	uint32_t pc;
 	uint16_t stack_size;
-} tasks_init[] = {
-	TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
-};
+} tasks_init[] = { TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
+			   CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST };
 #undef TASK
 
 /* Contexts for all tasks */
 static task_ tasks[TASK_ID_COUNT];
 /* Validity checks about static task invariants */
-BUILD_ASSERT(TASK_ID_COUNT <= sizeof(unsigned) * 8);
+BUILD_ASSERT(TASK_ID_COUNT <= sizeof(unsigned int) * 8);
 BUILD_ASSERT(TASK_ID_COUNT < (1 << (sizeof(task_id_t) * 8)));
 
-
 /* Stacks for all tasks */
-#define TASK(n, r, d, s)  + s
-uint8_t task_stacks[0
-		    TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
-		    CONFIG_TASK_LIST
-		    CONFIG_TEST_TASK_LIST
-] __aligned(8);
+#define TASK(n, r, d, s) +s
+uint8_t task_stacks[0 TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
+			    CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST] __aligned(8);
 
 #undef TASK
 
 /* Reserve space to discard context on first context switch. */
-uint32_t scratchpad[TASK_SCRATCHPAD_SIZE] __attribute__
-					((section(".bss.task_scratchpad")));
+uint32_t scratchpad[TASK_SCRATCHPAD_SIZE]
+	__attribute__((section(".bss.task_scratchpad")));
 
 task_ *current_task = (task_ *)scratchpad;
 
@@ -159,15 +153,15 @@ int need_resched;
  * can do their init within a task switching context.  The hooks task will then
  * make a call to enable all tasks.
  */
-static uint32_t tasks_ready = BIT(TASK_ID_HOOKS);
+static atomic_t tasks_ready = BIT(TASK_ID_HOOKS);
 /*
  * Initially allow only the HOOKS and IDLE task to run, regardless of ready
  * status, in order for HOOK_INIT to complete before other tasks.
  * task_enable_all_tasks() will open the flood gates.
  */
-static uint32_t tasks_enabled = BIT(TASK_ID_HOOKS) | BIT(TASK_ID_IDLE);
+static atomic_t tasks_enabled = BIT(TASK_ID_HOOKS) | BIT(TASK_ID_IDLE);
 
-int start_called;  /* Has task swapping started */
+int start_called; /* Has task swapping started */
 
 /* interrupt number of sw interrupt */
 static int sw_int_num;
@@ -213,18 +207,28 @@ void __ram_code interrupt_disable(void)
 {
 	/* Mask all interrupts, only keep division by zero exception */
 	uint32_t val = BIT(30);
-	asm volatile ("mtsr %0, $INT_MASK" : : "r"(val));
-	asm volatile ("dsb");
+	asm volatile("mtsr %0, $INT_MASK" : : "r"(val));
+	asm volatile("dsb");
 }
 
 void __ram_code interrupt_enable(void)
 {
 	/* Enable HW2 ~ HW15 and division by zero exception interrupts */
 	uint32_t val = (BIT(30) | 0xFFFC);
-	asm volatile ("mtsr %0, $INT_MASK" : : "r"(val));
+	asm volatile("mtsr %0, $INT_MASK" : : "r"(val));
 }
 
-inline int in_interrupt_context(void)
+inline bool is_interrupt_enabled(void)
+{
+	uint32_t val = 0;
+
+	asm volatile("mfsr %0, $INT_MASK" : "=r"(val));
+
+	/* Interrupts are enabled if any of HW2 ~ HW15 is enabled */
+	return val & 0xFFFC;
+}
+
+inline bool in_interrupt_context(void)
 {
 	/* check INTL (Interrupt Stack Level) bits */
 	return get_psw() & PSW_INTL_MASK;
@@ -236,10 +240,11 @@ task_id_t task_get_current(void)
 	/* If we haven't done a context switch then our task ID isn't valid */
 	ASSERT(current_task != (task_ *)scratchpad);
 #endif
-	return current_task - tasks;
+	/* return invalid task id if task scheduling is not yet start */
+	return start_called ? (current_task - tasks) : TASK_ID_INVALID;
 }
 
-uint32_t *task_get_event_bitmap(task_id_t tskid)
+atomic_t *task_get_event_bitmap(task_id_t tskid)
 {
 	task_ *tsk = __task_id_to_ptr(tskid);
 	return &tsk->events;
@@ -256,7 +261,7 @@ int task_start_called(void)
  * Also includes emulation of software triggering interrupt vector
  */
 void __ram_code __keep syscall_handler(int desched, task_id_t resched,
-								int swirq)
+				       int swirq)
 {
 	/* are we emulating an interrupt ? */
 	if (swirq) {
@@ -296,7 +301,7 @@ task_ *next_sched_task(void)
 #ifdef CONFIG_TASK_PROFILING
 	if (current_task != new_task) {
 		current_task->runtime +=
-				(exc_start_time - exc_end_time - exc_sub_time);
+			(exc_start_time - exc_end_time - exc_sub_time);
 		task_will_switch = 1;
 	}
 #endif
@@ -304,11 +309,11 @@ task_ *next_sched_task(void)
 #ifdef CONFIG_DEBUG_STACK_OVERFLOW
 	if (*current_task->stack != STACK_UNUSED_VALUE) {
 		int i = task_get_current();
-
-		panic_printf("\n\nStack overflow in %s task!\n", task_names[i]);
-#ifdef CONFIG_SOFTWARE_PANIC
-		software_panic(PANIC_SW_STACK_OVERFLOW, i);
-#endif
+		if (task_enabled(i)) {
+			panic_printf("\n\nStack overflow in %s task!\n",
+				     task_names[i]);
+			software_panic(PANIC_SW_STACK_OVERFLOW, i);
+		}
 	}
 #endif
 
@@ -337,7 +342,7 @@ volatile int ec_int;
 void __ram_code start_irq_handler(void)
 {
 	/* save r0, r1, and r2 for syscall */
-	asm volatile ("smw.adm $r0, [$sp], $r2, 0");
+	asm volatile("smw.adm $r0, [$sp], $r2, 0");
 	/* If this is a SW interrupt */
 	if (get_itype() & 8)
 		ec_int = sw_int_num;
@@ -358,7 +363,7 @@ void __ram_code start_irq_handler(void)
 		irq_dist[ec_int]++;
 #endif
 	/* restore r0, r1, and r2 */
-	asm volatile ("lmw.bim $r0, [$sp], $r2, 0");
+	asm volatile("lmw.bim $r0, [$sp], $r2, 0");
 }
 
 void end_irq_handler(void)
@@ -369,7 +374,7 @@ void end_irq_handler(void)
 	 * save r0 and fp (fp for restore r0-r5, r15, fp, lp and sp
 	 * while interrupt exit.
 	 */
-	asm volatile ("smw.adm $r0, [$sp], $r0, 8");
+	asm volatile("smw.adm $r0, [$sp], $r0, 8");
 
 	t = get_time().le.lo;
 	p = t - exc_start_time;
@@ -384,7 +389,7 @@ void end_irq_handler(void)
 	}
 
 	/* restore r0 and fp */
-	asm volatile ("lmw.bim $r0, [$sp], $r0, 8");
+	asm volatile("lmw.bim $r0, [$sp], $r0, 8");
 #endif
 }
 
@@ -403,7 +408,7 @@ static uint32_t __ram_code __wait_evt(int timeout_us, task_id_t resched)
 		ret = timer_arm(deadline, me);
 		ASSERT(ret == EC_SUCCESS);
 	}
-	while (!(evt = deprecated_atomic_read_clear(&tsk->events))) {
+	while (!(evt = atomic_clear(&tsk->events))) {
 		/* Remove ourself and get the next task in the scheduler */
 		__schedule(1, resched, 0);
 		resched = TASK_ID_IDLE;
@@ -411,33 +416,28 @@ static uint32_t __ram_code __wait_evt(int timeout_us, task_id_t resched)
 	if (timeout_us > 0) {
 		timer_cancel(me);
 		/* Ensure timer event is clear, we no longer care about it */
-		deprecated_atomic_clear_bits(&tsk->events, TASK_EVENT_TIMER);
+		atomic_clear_bits(&tsk->events, TASK_EVENT_TIMER);
 	}
 	return evt;
 }
 
-uint32_t __ram_code task_set_event(task_id_t tskid, uint32_t event, int wait)
+void __ram_code task_set_event(task_id_t tskid, uint32_t event)
 {
 	task_ *receiver = __task_id_to_ptr(tskid);
 	ASSERT(receiver);
 
 	/* Set the event bit in the receiver message bitmap */
-	deprecated_atomic_or(&receiver->events, event);
+	atomic_or(&receiver->events, event);
 
 	/* Re-schedule if priorities have changed */
 	if (in_interrupt_context()) {
 		/* The receiver might run again */
-		deprecated_atomic_or(&tasks_ready, 1 << tskid);
+		atomic_or(&tasks_ready, 1 << tskid);
 		if (start_called)
 			need_resched = 1;
 	} else {
-		if (wait)
-			return __wait_evt(-1, tskid);
-		else
-			__schedule(0, tskid, 0);
+		__schedule(0, tskid, 0);
 	}
-
-	return 0;
 }
 
 uint32_t __ram_code task_wait_event(int timeout_us)
@@ -468,8 +468,7 @@ uint32_t __ram_code task_wait_event_mask(uint32_t event_mask, int timeout_us)
 
 	/* Re-post any other events collected */
 	if (events & ~event_mask)
-		deprecated_atomic_or(&current_task->events,
-				     events & ~event_mask);
+		atomic_or(&current_task->events, events & ~event_mask);
 
 	return events & event_mask;
 }
@@ -478,37 +477,36 @@ uint32_t __ram_code read_clear_int_mask(void)
 {
 	uint32_t int_mask, int_dis = BIT(30);
 
-	asm volatile(
-		"mfsr %0, $INT_MASK\n\t"
-		"mtsr %1, $INT_MASK\n\t"
-		"dsb\n\t"
-		: "=&r"(int_mask)
-		: "r"(int_dis));
+	asm volatile("mfsr %0, $INT_MASK\n\t"
+		     "mtsr %1, $INT_MASK\n\t"
+		     "dsb\n\t"
+		     : "=&r"(int_mask)
+		     : "r"(int_dis));
 
 	return int_mask;
 }
 
 void __ram_code set_int_mask(uint32_t val)
 {
-	asm volatile ("mtsr %0, $INT_MASK" : : "r"(val));
+	asm volatile("mtsr %0, $INT_MASK" : : "r"(val));
 }
 
 static void set_int_priority(uint32_t val)
 {
-	asm volatile ("mtsr %0, $INT_PRI" : : "r"(val));
+	asm volatile("mtsr %0, $INT_PRI" : : "r"(val));
 }
 
 uint32_t get_int_ctrl(void)
 {
 	uint32_t ret;
 
-	asm volatile ("mfsr %0, $INT_CTRL" : "=r"(ret));
+	asm volatile("mfsr %0, $INT_CTRL" : "=r"(ret));
 	return ret;
 }
 
 void set_int_ctrl(uint32_t val)
 {
-	asm volatile ("mtsr %0, $INT_CTRL" : : "r"(val));
+	asm volatile("mtsr %0, $INT_CTRL" : : "r"(val));
 }
 
 void task_enable_all_tasks(void)
@@ -521,12 +519,17 @@ void task_enable_all_tasks(void)
 
 void task_enable_task(task_id_t tskid)
 {
-	deprecated_atomic_or(&tasks_enabled, BIT(tskid));
+	atomic_or(&tasks_enabled, BIT(tskid));
+}
+
+bool task_enabled(task_id_t tskid)
+{
+	return tasks_enabled & BIT(tskid);
 }
 
 void task_disable_task(task_id_t tskid)
 {
-	deprecated_atomic_clear_bits(&tasks_enabled, BIT(tskid));
+	atomic_clear_bits(&tasks_enabled, BIT(tskid));
 
 	if (!in_interrupt_context() && tskid == task_get_current())
 		__schedule(0, 0, 0);
@@ -594,7 +597,7 @@ static void ivic_init_irqs(void)
 	for (i = 0; i < exc_calls; i++) {
 		uint8_t irq = __irqprio[i].irq;
 		uint8_t prio = __irqprio[i].priority;
-		all_priorities |= (prio & 0x3)  << (irq * 2);
+		all_priorities |= (prio & 0x3) << (irq * 2);
 	}
 	set_int_priority(all_priorities);
 }
@@ -631,20 +634,29 @@ void __ram_code mutex_unlock(struct mutex *mtx)
 	uint32_t waiters;
 	task_ *tsk = current_task;
 
-	waiters = mtx->waiters;
-	/* give back the lock */
-	mtx->lock = 0;
+	/*
+	 * we need to read to waiters after giving the lock back
+	 * otherwise we might miss a waiter between the two calls.
+	 *
+	 * prevent compiler reordering
+	 */
+	asm volatile(
+		/* give back the lock */
+		"movi %0, #0\n\t"
+		"lwi %1, [%2]\n\t"
+		: "=&r"(mtx->lock), "=&r"(waiters)
+		: "r"(&mtx->waiters));
 
 	while (waiters) {
 		task_id_t id = __fls(waiters);
 		waiters &= ~BIT(id);
 
 		/* Somebody is waiting on the mutex */
-		task_set_event(id, TASK_EVENT_MUTEX, 0);
+		task_set_event(id, TASK_EVENT_MUTEX);
 	}
 
 	/* Ensure no event is remaining from mutex wake-up */
-	deprecated_atomic_clear_bits(&tsk->events, TASK_EVENT_MUTEX);
+	atomic_clear_bits(&tsk->events, TASK_EVENT_MUTEX);
 }
 
 void task_print_list(void)
@@ -654,7 +666,7 @@ void task_print_list(void)
 	ccputs("Task Ready Name         Events      Time (s)  StkUsed\n");
 
 	for (i = 0; i < TASK_ID_COUNT; i++) {
-		char is_ready = (tasks_ready & (1<<i)) ? 'R' : ' ';
+		char is_ready = ((uint32_t)tasks_ready & BIT(i)) ? 'R' : ' ';
 		uint32_t *sp;
 
 		int stackused = tasks_init[i].stack_size;
@@ -665,13 +677,13 @@ void task_print_list(void)
 			stackused -= sizeof(uint32_t);
 
 		ccprintf("%4d %c %-16s %08x %11.6lld  %3d/%3d\n", i, is_ready,
-			 task_names[i], tasks[i].events, tasks[i].runtime,
+			 task_names[i], (int)tasks[i].events, tasks[i].runtime,
 			 stackused, tasks_init[i].stack_size);
 		cflush();
 	}
 }
 
-int command_task_info(int argc, char **argv)
+static int command_task_info(int argc, const char **argv)
 {
 #ifdef CONFIG_TASK_PROFILING
 	int total = 0;
@@ -701,24 +713,21 @@ int command_task_info(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(taskinfo, command_task_info,
-			NULL,
-			"Print task info");
+DECLARE_CONSOLE_COMMAND(taskinfo, command_task_info, NULL, "Print task info");
 
-static int command_task_ready(int argc, char **argv)
+static int command_task_ready(int argc, const char **argv)
 {
 	if (argc < 2) {
-		ccprintf("tasks_ready: 0x%08x\n", tasks_ready);
+		ccprintf("tasks_ready: 0x%08x\n", (int)tasks_ready);
 	} else {
 		tasks_ready = strtoi(argv[1], NULL, 16);
-		ccprintf("Setting tasks_ready to 0x%08x\n", tasks_ready);
+		ccprintf("Setting tasks_ready to 0x%08x\n", (int)tasks_ready);
 		__schedule(0, 0, 0);
 	}
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(taskready, command_task_ready,
-			"[setmask]",
+DECLARE_CONSOLE_COMMAND(taskready, command_task_ready, "[setmask]",
 			"Print/set ready tasks");
 
 void task_pre_init(void)
@@ -741,11 +750,11 @@ void task_pre_init(void)
 		tasks[i].sp = (uint32_t)sp;
 
 		/* Initial context on stack (see __switchto()) */
-		sp[7] = tasks_init[i].r0;           /* r0 */
-		sp[15] = (uint32_t)task_exit_trap;  /* lr */
-		sp[1] = tasks_init[i].pc;           /* pc */
-		sp[0] = 0x70009;                    /* psw */
-		sp[16] = (uint32_t)(sp + 17);       /* sp */
+		sp[7] = tasks_init[i].r0; /* r0 */
+		sp[15] = (uint32_t)task_exit_trap; /* lr */
+		sp[1] = tasks_init[i].pc; /* pc */
+		sp[0] = 0x70009; /* psw */
+		sp[16] = (uint32_t)(sp + 17); /* sp */
 
 		/* Fill unused stack; also used to detect stack overflow. */
 		for (sp = stack_next; sp < (uint32_t *)tasks[i].sp; sp++)
diff --git a/core/nds32/toolchain.mk b/core/nds32/toolchain.mk
new file mode 100644
index 0000000000..e2405d3054
--- /dev/null
+++ b/core/nds32/toolchain.mk
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Set coreboot-sdk as the default toolchain for nds32
+NDS32_DEFAULT_COMPILE=/opt/coreboot-sdk/bin/nds32le-elf-
+
+# Select Andes bare-metal toolchain
+$(call set-option,CROSS_COMPILE,$(CROSS_COMPILE_nds32),$(NDS32_DEFAULT_COMPILE))
diff --git a/core/riscv-rv32i/__builtin.c b/core/riscv-rv32i/__builtin.c
index 4bf495a011..8e2bf984ff 100644
--- a/core/riscv-rv32i/__builtin.c
+++ b/core/riscv-rv32i/__builtin.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/core/riscv-rv32i/__it8xxx2_arithmetic.S b/core/riscv-rv32i/__it8xxx2_arithmetic.S
new file mode 100644
index 0000000000..de6dd220ad
--- /dev/null
+++ b/core/riscv-rv32i/__it8xxx2_arithmetic.S
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * When the 'M' extension is disabled, compiler can not recognize div/mul
+ * instructions. So mul/div instructions in the below integer arithmetic
+ * routines are hard coded by opcodes.
+ *
+ * IMPORTANT:
+ * The workaround requires the nop instruction, please don't optimize it.
+ */
+
+.macro __int_arithmetic func opcode
+.section .ram_code_ilm0
+.align 2
+.globl \func
+.type \func, @function
+\func:
+.word \opcode
+nop
+ret
+.size \func, .-\func
+.endm
+
+/* signed 32 bit multiplication. opcode of mul a0,a0,a1 is 0x02b50533 */
+__int_arithmetic __mulsi3 0x02b50533
+
+/* signed 32 bit division. opcode of div a0,a0,a1 is 0x02b54533 */
+__int_arithmetic __divsi3 0x02b54533
+
+/* unsigned 32 bit division. opcode of divu a0,a0,a1 is 0x02b55533 */
+__int_arithmetic __udivsi3 0x02b55533
+
+/*
+ * This function return the remainder of the signed division.
+ * opcode of rem a0,a0,a1 is 0x02b56533
+ */
+__int_arithmetic __modsi3 0x02b56533
+
+/*
+ * This function return the remainder of the unsigned division.
+ * opcode of remu a0,a0,a1 is 0x02b57533
+ */
+__int_arithmetic __umodsi3 0x02b57533
diff --git a/core/riscv-rv32i/atomic.h b/core/riscv-rv32i/atomic.h
index 7a7431b740..edd27f20e8 100644
--- a/core/riscv-rv32i/atomic.h
+++ b/core/riscv-rv32i/atomic.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,64 +8,49 @@
 #ifndef __CROS_EC_ATOMIC_H
 #define __CROS_EC_ATOMIC_H
 
+#include "atomic_t.h"
 #include "common.h"
 #include "cpu.h"
 #include "task.h"
 
-#define ATOMIC_OP(op, value, addr)             \
-({                                             \
-	uint32_t tmp;                          \
-	asm volatile (                         \
-		"amo" #op ".w.aqrl %0, %2, %1" \
-		: "=r" (tmp), "+A" (*addr)     \
-		: "r" (value));                \
-	tmp;                                   \
-})
-
-/*
- * The atomic_* functions are marked as deprecated as a part of the process of
- * transaction to Zephyr compatible atomic functions. These prefixes will be
- * removed in the following patches. Please see b:169151160 for more details.
- */
+static inline atomic_val_t atomic_clear_bits(atomic_t *addr, atomic_val_t bits)
+{
+	return __atomic_fetch_and(addr, ~bits, __ATOMIC_SEQ_CST);
+}
 
-static inline void deprecated_atomic_clear_bits(volatile uint32_t *addr,
-						uint32_t bits)
+static inline atomic_val_t atomic_or(atomic_t *addr, atomic_val_t bits)
 {
-	ATOMIC_OP(and, ~bits, addr);
+	return __atomic_fetch_or(addr, bits, __ATOMIC_SEQ_CST);
 }
 
-static inline void deprecated_atomic_or(volatile uint32_t *addr, uint32_t bits)
+static inline atomic_val_t atomic_add(atomic_t *addr, atomic_val_t value)
 {
-	ATOMIC_OP(or, bits, addr);
+	return __atomic_fetch_add(addr, value, __ATOMIC_SEQ_CST);
 }
 
-static inline void deprecated_atomic_add(volatile uint32_t *addr,
-					 uint32_t value)
+static inline atomic_val_t atomic_sub(atomic_t *addr, atomic_val_t value)
 {
-	ATOMIC_OP(add, value, addr);
+	return __atomic_fetch_sub(addr, value, __ATOMIC_SEQ_CST);
 }
 
-static inline void deprecated_atomic_sub(volatile uint32_t *addr,
-					 uint32_t value)
+static inline atomic_val_t atomic_clear(atomic_t *addr)
 {
-	ATOMIC_OP(add, -value, addr);
+	return __atomic_exchange_n(addr, 0, __ATOMIC_SEQ_CST);
 }
 
-static inline uint32_t deprecated_atomic_read_clear(volatile uint32_t *addr)
+static inline atomic_val_t atomic_read_add(atomic_t *addr, atomic_val_t value)
 {
-	return ATOMIC_OP(and, 0, addr);
+	return __atomic_fetch_add(addr, value, __ATOMIC_SEQ_CST);
 }
 
-static inline uint32_t deprecated_atomic_read_add(volatile uint32_t *addr,
-						  uint32_t value)
+static inline atomic_val_t atomic_read_sub(atomic_t *addr, atomic_val_t value)
 {
-	return ATOMIC_OP(add, value, addr);
+	return __atomic_fetch_sub(addr, value, __ATOMIC_SEQ_CST);
 }
 
-static inline uint32_t deprecated_atomic_read_sub(volatile uint32_t *addr,
-						  uint32_t value)
+static inline atomic_val_t atomic_and(atomic_t *addr, atomic_val_t bits)
 {
-	return ATOMIC_OP(add, -value, addr);
+	return __atomic_fetch_and(addr, bits, __ATOMIC_SEQ_CST);
 }
 
-#endif  /* __CROS_EC_ATOMIC_H */
+#endif /* __CROS_EC_ATOMIC_H */
diff --git a/core/riscv-rv32i/build.mk b/core/riscv-rv32i/build.mk
index a69e2ecafc..99171a422d 100644
--- a/core/riscv-rv32i/build.mk
+++ b/core/riscv-rv32i/build.mk
@@ -1,20 +1,29 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
 # RISC-V core OS files build
 #
 
-# Select RISC-V bare-metal toolchain
-$(call set-option,CROSS_COMPILE,$(CROSS_COMPILE_riscv),\
-	/opt/coreboot-sdk/bin/riscv64-elf-)
-
 # Enable FPU extension if config option of FPU is enabled.
 _FPU_EXTENSION=$(if $(CONFIG_FPU),f,)
+# Enable the 'M' extension if config option of RISCV_EXTENSION_M is enabled.
+_M_EXTENSION=$(if $(CONFIG_RISCV_EXTENSION_M),m,)
 # CPU specific compilation flags
-CFLAGS_CPU+=-march=rv32ima$(_FPU_EXTENSION)c -mabi=ilp32$(_FPU_EXTENSION) -Os
+CFLAGS_CPU+=-march=rv32i$(_M_EXTENSION)a$(_FPU_EXTENSION)c
+CFLAGS_CPU+=-mabi=ilp32$(_FPU_EXTENSION) -Os
+# RISC-V does not trap division by zero, enable the sanitizer to check those.
+# With `-fsanitize-undefined-trap-on-error`, we lose a bit of specificity on the
+# exact issue, but the added code is as small as it gets.
+CFLAGS_CPU+=-fsanitize=integer-divide-by-zero -fsanitize-undefined-trap-on-error
 LDFLAGS_EXTRA+=-mrelax
 LDFLAGS_EXTRA+=-static-libgcc -lgcc
 
+ifneq ($(CONFIG_LTO),)
+CFLAGS_CPU+=-flto
+LDFLAGS_EXTRA+=-flto
+endif
+
 core-y=cpu.o init.o panic.o task.o switch.o __builtin.o math.o
+core-$(CONFIG_IT8XXX2_MUL_WORKAROUND)+=__it8xxx2_arithmetic.o
diff --git a/core/riscv-rv32i/config_core.h b/core/riscv-rv32i/config_core.h
index fe6135683d..c5863efb25 100644
--- a/core/riscv-rv32i/config_core.h
+++ b/core/riscv-rv32i/config_core.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,6 +16,5 @@
  */
 #define CONFIG_SOFTWARE_CLZ
 #define CONFIG_SOFTWARE_CTZ
-#define CONFIG_SOFTWARE_PANIC
 
 #endif /* __CROS_EC_CONFIG_CORE_H */
diff --git a/core/riscv-rv32i/cpu.c b/core/riscv-rv32i/cpu.c
index fd18896846..911d170801 100644
--- a/core/riscv-rv32i/cpu.c
+++ b/core/riscv-rv32i/cpu.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,5 +10,5 @@
 void cpu_init(void)
 {
 	/* bit3: Global interrupt enable (M-mode) */
-	asm volatile ("csrsi mstatus, 0x8");
+	asm volatile("csrsi mstatus, 0x8");
 }
diff --git a/core/riscv-rv32i/cpu.h b/core/riscv-rv32i/cpu.h
index e46b893ad6..39ee3fe126 100644
--- a/core/riscv-rv32i/cpu.h
+++ b/core/riscv-rv32i/cpu.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -25,7 +25,7 @@
 /* write Exception Program Counter register */
 static inline void set_mepc(uint32_t val)
 {
-	asm volatile ("csrw mepc, %0" : : "r"(val));
+	asm volatile("csrw mepc, %0" : : "r"(val));
 }
 
 /* read Exception Program Counter register */
@@ -33,7 +33,7 @@ static inline uint32_t get_mepc(void)
 {
 	uint32_t ret;
 
-	asm volatile ("csrr %0, mepc" : "=r"(ret));
+	asm volatile("csrr %0, mepc" : "=r"(ret));
 	return ret;
 }
 
@@ -42,7 +42,7 @@ static inline uint32_t get_mcause(void)
 {
 	uint32_t ret;
 
-	asm volatile ("csrr %0, mcause" : "=r"(ret));
+	asm volatile("csrr %0, mcause" : "=r"(ret));
 	return ret;
 }
 
diff --git a/core/riscv-rv32i/ec.lds.S b/core/riscv-rv32i/ec.lds.S
index 15a26e5eff..5617f9786f 100644
--- a/core/riscv-rv32i/ec.lds.S
+++ b/core/riscv-rv32i/ec.lds.S
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -41,12 +41,16 @@ MEMORY
 	 */
 	ILM (rx) : ORIGIN = FW_OFF(SECTION), LENGTH = FW_SIZE(SECTION)
 
-#if defined(CONFIG_HOSTCMD_X86) || defined(CONFIG_I2C_SLAVE)
+#if defined(CONFIG_HOSTCMD_X86) || defined(CONFIG_I2C_PERIPHERAL)
 	H2RAM (rw) : ORIGIN = CONFIG_H2RAM_BASE, LENGTH = CONFIG_H2RAM_SIZE
 #endif
 #else
 	IRAM (rw) : ORIGIN = CONFIG_RAM_BASE, LENGTH = CONFIG_RAM_SIZE
 #endif /* CHIP_FAMILY_IT8XXX2 */
+
+#ifdef CONFIG_DRAM_BASE
+	DRAM (rwx) : ORIGIN = CONFIG_DRAM_BASE, LENGTH = CONFIG_DRAM_SIZE
+#endif
 }
 
 SECTIONS
@@ -78,8 +82,13 @@ SECTIONS
 		ASSERT((__flash_dma_size < IT83XX_ILM_BLOCK_SIZE),
 		       "__flash_dma_size < IT83XX_ILM_BLOCK_SIZE");
 		. = ALIGN(IT83XX_ILM_BLOCK_SIZE);
-
-		__flash_text_start = .;
+		__ilm0_ram_code = .;
+		KEEP(*(.ram_code_ilm0))
+		OUTDIR/chip/it83xx/i2c.o (.text*)
+		OUTDIR/chip/it83xx/i2c.o (.rodata)
+		OUTDIR/chip/it83xx/hwtimer.o (.text*)
+		OUTDIR/chip/it83xx/hwtimer.o (.rodata)
+		. = ALIGN(16);
 #endif
 		*(.text*)
 		. = ALIGN(4);
@@ -170,6 +179,10 @@ SECTIONS
 		KEEP(*(.rodata.HOOK_CHIPSET_SHUTDOWN_COMPLETE))
 		__hooks_chipset_shutdown_complete_end = .;
 
+		__hooks_chipset_hard_off = .;
+		KEEP(*(.rodata.HOOK_CHIPSET_HARD_OFF))
+		__hooks_chipset_hard_off_end = .;
+
 		__hooks_chipset_reset = .;
 		KEEP(*(.rodata.HOOK_CHIPSET_RESET))
 		__hooks_chipset_reset_end = .;
@@ -186,6 +199,12 @@ SECTIONS
 		KEEP(*(.rodata.HOOK_TABLET_MODE_CHANGE))
 		__hooks_tablet_mode_change_end = .;
 
+#ifdef CONFIG_BODY_DETECTION
+		__hooks_body_detect_change = .;
+		KEEP(*(.rodata.HOOK_BODY_DETECT_CHANGE))
+		__hooks_body_detect_change_end = .;
+#endif
+
 		__hooks_base_attached_change = .;
 		KEEP(*(.rodata.HOOK_BASE_ATTACHED_CHANGE))
 		__hooks_base_attached_change_end = .;
@@ -220,6 +239,10 @@ SECTIONS
 		KEEP(*(.rodata.HOOK_USB_PD_CONNECT))
 		__hooks_usb_pd_connect_end = .;
 
+		__hooks_power_supply_change = .;
+		KEEP(*(.rodata.HOOK_POWER_SUPPLY_CHANGE))
+		__hooks_power_supply_change_end = .;
+
 		__deferred_funcs = .;
 		KEEP(*(.rodata.deferred))
 		__deferred_funcs_end = .;
@@ -242,7 +265,7 @@ SECTIONS
 
 		. = ALIGN(4);
 		*(.srodata*)
-#if defined(SECTION_IS_RO) && defined(CONFIG_FLASH)
+#if defined(SECTION_IS_RO) && defined(CONFIG_FLASH_CROS)
 		. = ALIGN(64);
 		KEEP(*(.google))
 #endif
@@ -259,6 +282,25 @@ SECTIONS
 
 	__data_lma_start = .;
 
+#ifdef CONFIG_PRESERVE_LOGS
+	.preserve_logs(NOLOAD) : {
+		/*
+		 * The address of the preserved logs is fixed at the beginning
+		 * of memory.
+		 */
+		. = ALIGN(8);
+		__preserved_logs_start = .;
+		*(SORT(.preserved_logs.*))
+		. = ALIGN(8);
+		__preserved_logs_end = .;
+	} > IRAM
+	__preserved_logs_size = __preserved_logs_end - __preserved_logs_start;
+#ifdef CONFIG_IT83XX_HARD_RESET_BY_GPG1
+	ASSERT(__preserved_logs_size <= CHIP_FLASH_PRESERVE_LOGS_SIZE,
+	       "Not enough flash space to save EC logs.")
+#endif
+#endif /* CONFIG_PRESERVE_LOGS */
+
 	.data : {
 		. = ALIGN(4);
 		__data_start = .;
@@ -287,7 +329,6 @@ SECTIONS
 		. = ALIGN(4);
 		/* Rest of .bss takes care of its own alignment */
 		*(.bss)
-		*(.bss.slow)
 
 		/*
 		 * Reserve space for deferred function firing times.
@@ -317,23 +358,38 @@ SECTIONS
 		     (__shared_mem_buf + CONFIG_SHAREDMEM_MINIMUM_SIZE);
 
 	/*
-	 * __flash_used is used in flash free calculations by the makefile.
+	 * __flash_used and __flash_size is used in flash free calculations by
+	 * the makefile. Note the difference between __flash_size and
+	 * __config_flash_size. __flash_size is the flash size for the given
+	 * image (RW, RO, etc.), while __config_flash_size is the *total*
+	 * flash size.
 	 * __image_size is stored in the struct image_data header and used
-	 * in hash calcuations.
+	 * in hash calculations.
 	 */
 #if defined(CHIP_FAMILY_IT8XXX2)
 	__flash_used = LOADADDR(.data) + SIZEOF(.data) + \
 		       CHIP_ILM_BASE - FW_OFF(SECTION);
 #else
 	__flash_used = LOADADDR(.data) + SIZEOF(.data) - FW_OFF(SECTION);
+#endif
+#if defined(CONFIG_FLASH_PHYSICAL)
+	__flash_size = LENGTH(FLASH);
+#else
+	__flash_size = LENGTH(IROM);
 #endif
 	__image_size = __flash_used;
 
-#ifdef CONFIG_FLASH
+#if defined(SECTION_IS_RW) && (CONFIG_FLASH_WRITE_SIZE > 0)
+	/* Alignment is needed by flash_command_write() for RW update. */
+	ASSERT(__image_size % CONFIG_FLASH_WRITE_SIZE == 0,
+	       "Error: RW image is not aligned to CONFIG_FLASH_WRITE_SIZE")
+#endif
+
+#ifdef CONFIG_FLASH_CROS
         /*
          * These linker labels are just for analysis and not used in the code.
          */
-	__config_flash_size = CONFIG_FLASH_SIZE;
+	__config_flash_size = CONFIG_FLASH_SIZE_BYTES;
 	__config_ro_size = CONFIG_RO_SIZE;
 	__config_ec_protected_storage_size = CONFIG_EC_PROTECTED_STORAGE_SIZE;
 	__config_rw_size = CONFIG_RW_SIZE;
@@ -341,13 +397,13 @@ SECTIONS
 #endif
 
 #if defined(CHIP_FAMILY_IT8XXX2)
-#if defined(CONFIG_HOSTCMD_X86) || defined(CONFIG_I2C_SLAVE)
+#if defined(CONFIG_HOSTCMD_X86) || defined(CONFIG_I2C_PERIPHERAL)
 	.h2ram (NOLOAD) : {
 		. += CONFIG_H2RAM_HOST_LPC_IO_BASE;
 		*(.h2ram.pool.hostcmd)
 		. = ALIGN(256);
 		*(.h2ram.pool.acpiec)
-#ifdef CONFIG_I2C_SLAVE
+#ifdef CONFIG_I2C_PERIPHERAL
 		. = ALIGN(256);
 		*(.h2ram.pool.i2cslv)
 #endif
@@ -359,7 +415,67 @@ SECTIONS
 #endif
 #endif /* CHIP_FAMILY_IT8XXX2 */
 
-#if !(defined(SECTION_IS_RO) && defined(CONFIG_FLASH))
+#ifdef CONFIG_DRAM_BASE
+	/*
+	 * Sections in DRAM region are constructed as like in non-DRAM regions:
+	 * .dram.data LMA is for preserving initialized data across resets.
+	 * The only difference is that they are all in the DRAM region:
+	 * .dram.text     | LOAD
+	 * .dram.rodata   | LOAD
+	 * .dram.data LMA | LOAD
+	 * .dram.data VMA |
+	 * .dram.bss      | NOLOAD
+	 */
+
+	.dram.text : {
+		. = ALIGN(4);
+		KEEP(*(SORT(.dram.text.keep.*)))
+		*(SORT(.dram.text.*))
+		. = ALIGN(4);
+	} > DRAM
+
+	.dram.rodata : {
+		. = ALIGN(4);
+		KEEP(*(SORT(.dram.rodata.keep.*)))
+		*(SORT(.dram.rodata.*))
+		. = ALIGN(4);
+	} > DRAM
+
+	__dram_data_lma_start = ADDR(.dram.rodata) + SIZEOF(.dram.rodata);
+
+	/* Place .dram.data LMA in between .dram.rodata and .dram.data VMA. */
+	.dram.data __dram_data_lma_start +
+		(__dram_data_end - __dram_data_start) : {
+		. = ALIGN(4);
+		__dram_data_start = .;
+		*(.dram.data*)
+		. = ALIGN(4);
+		__dram_data_end = .;
+
+	/*
+	 * Normally, '> DRAM AT > DRAM' should be the same as '> DRAM',
+	 * and they  will be at the same address. However, if the address
+	 * of VMA specified, LMA and VMA might have different addresses:
+	 * '> DRAM' places VMA at the address where section declaration
+	 * specified.
+	 * 'AT > DRAM' places LMA at the location counter's address.
+	 */
+	} > DRAM AT > DRAM
+
+	/*
+	 * ld assigns correct attribute for .bss, but not for other .*.bss,
+	 * we need an explicltly NOLOAD.
+	 */
+	.dram.bss(NOLOAD) : {
+		. = ALIGN(4);
+		__dram_bss_start = .;
+		*(SORT(.dram.bss*))
+		. = ALIGN(4);
+		__dram_bss_end = .;
+	} > DRAM
+#endif /* CONFIG_DRAM_BASE */
+
+#if !(defined(SECTION_IS_RO) && defined(CONFIG_FLASH_CROS))
 	/DISCARD/ : { *(.google) }
 #endif
 
diff --git a/core/riscv-rv32i/include/fpu.h b/core/riscv-rv32i/include/fpu.h
new file mode 100644
index 0000000000..da48139d1c
--- /dev/null
+++ b/core/riscv-rv32i/include/fpu.h
@@ -0,0 +1,13 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Math utility functions for RISC-V */
+
+#ifndef __CROS_EC_FPU_H
+#define __CROS_EC_FPU_H
+
+float sqrtf(float x);
+
+#endif /* __CROS_EC_FPU_H */
diff --git a/core/riscv-rv32i/include/math.h b/core/riscv-rv32i/include/math.h
deleted file mode 100644
index f17144762a..0000000000
--- a/core/riscv-rv32i/include/math.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Math utility functions for RISC-V */
-
-#ifndef __CROS_EC_MATH_H
-#define __CROS_EC_MATH_H
-
-float sqrtf(float x);
-
-#endif  /* __CROS_EC_MATH_H */
diff --git a/core/riscv-rv32i/init.S b/core/riscv-rv32i/init.S
index 0bc99052da..6231ad94c0 100644
--- a/core/riscv-rv32i/init.S
+++ b/core/riscv-rv32i/init.S
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -29,6 +29,26 @@ __startup:
 __irq:
         j __irq_isr     /* interrupts / exceptions */
 
+.align 2
+__ec_intc:
+        vector irq_0    /* INT GROUP  0 */
+        vector irq_1    /* INT GROUP  1 */
+        vector irq_2    /* INT GROUP  2 */
+        vector irq_3    /* INT GROUP  3 */
+        vector irq_4    /* INT GROUP  4 */
+        vector irq_5    /* INT GROUP  5 */
+        vector irq_6    /* INT GROUP  6 */
+        vector irq_7    /* INT GROUP  7 */
+        vector irq_8    /* INT GROUP  8 */
+        vector irq_9    /* INT GROUP  9 */
+        vector irq_10   /* INT GROUP 10 */
+        vector irq_11   /* INT GROUP 11 */
+        vector irq_12   /* INT GROUP 12 */
+        vector irq_13   /* INT GROUP 13 */
+        vector irq_14   /* INT GROUP 14 */
+        vector irq_15   /* INT GROUP 15 */
+        vector syscall  /* system call (emulate INT GROUP 16) */
+
 #ifdef CHIP_FAMILY_IT8XXX2
 /*
  * E-flash signature used to enable specific function after power-on reset.
@@ -55,7 +75,7 @@ __irq:
 .global eflash_sig
 eflash_sig:
 .byte 0xA5, 0xA5, 0xA5, 0xA5, 0xA5, 0xA5
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 .byte 0xA4 /* eSPI */
 #else
 .byte 0xA5 /* LPC */
@@ -65,27 +85,9 @@ eflash_sig:
 /* flags: internal oscillator + implicit location */
 #endif /* CHIP_FAMILY_IT8XXX2 */
 
-.align 2
-__ec_intc:
-        vector irq_0    /* INT GROUP  0 */
-        vector irq_1    /* INT GROUP  1 */
-        vector irq_2    /* INT GROUP  2 */
-        vector irq_3    /* INT GROUP  3 */
-        vector irq_4    /* INT GROUP  4 */
-        vector irq_5    /* INT GROUP  5 */
-        vector irq_6    /* INT GROUP  6 */
-        vector irq_7    /* INT GROUP  7 */
-        vector irq_8    /* INT GROUP  8 */
-        vector irq_9    /* INT GROUP  9 */
-        vector irq_10   /* INT GROUP 10 */
-        vector irq_11   /* INT GROUP 11 */
-        vector irq_12   /* INT GROUP 12 */
-        vector irq_13   /* INT GROUP 13 */
-        vector irq_14   /* INT GROUP 14 */
-        vector irq_15   /* INT GROUP 15 */
-        vector syscall  /* system call (emulate INT GROUP 16) */
 
 .align 2
+.section .text.vectirq
 __irq_isr:
         /* save t2 to scratch register */
         csrw mscratch, t2
@@ -165,6 +167,10 @@ __irq_isr:
         bltu sp, t0, __sp_16byte_aligned
         mv sp, t0
 __sp_16byte_aligned:
+	/* in_interrupt = 1 */
+	li t0, 1
+	la t1, in_interrupt
+        sb t0, 0(t1)
         /*
          * This ensures sp is 16-byte aligned. This only applies to when there
          * is an interrupt before tasks start. Otherwise stack_end is already
@@ -183,9 +189,19 @@ __sp_16byte_aligned:
         /* This interrupt is unhandled */
         j unhandled_interrupt
 __irq_handler:
+        /* save a0, a1, and a2 for syscall */
+        addi sp, sp, -4*3
+        sw a0, 0(sp)
+        sw a1, 1*4(sp)
+        sw a2, 2*4(sp)
         jal start_irq_handler
-        /* t0 = -1 if it cannot find the corresponding interrupt source */
-        bltz t0, unhandled_interrupt
+        /* a0 = -1 if it cannot find the corresponding interrupt source */
+        bltz a0, unhandled_interrupt
+        /* restore a0, a1, and a2 */
+        lw a0, 0(sp)
+        lw a1, 1*4(sp)
+        lw a2, 2*4(sp)
+        addi sp, sp, 4*3
         /* get EC interrupt group 0-15 or 16:ecall */
         la t0, ec_int_group
         /* get corresponding isr */
@@ -202,6 +218,9 @@ __irq_handler:
 .global __irq_exit
 __irq_exit:
         jal end_irq_handler
+	/* in_interrupt = 0 */
+	la t0, in_interrupt
+	sb zero, 0(t0)
         /* restore sp from scratch register */
         csrr sp, mscratch
 #ifdef CONFIG_FPU
@@ -332,10 +351,11 @@ unhandled_ec_irq:
 unhandled_interrupt:
         li tp, 0xBAD0
 __unhandled_irq:
-        slli tp, tp, 8
-        csrr t0, mcause
+        slli tp, tp, 16
+        la t0, ec_int
+        lw t0, 0(t0)
         add tp, tp, t0
-        j excep_handler /* display exception with TP 80bad[0|1]<irq> */
+        j excep_handler /* display exception with TP bad[0|1]<ec_int> */
 
 .global excep_handler
 excep_handler:
diff --git a/core/riscv-rv32i/irq_chip.h b/core/riscv-rv32i/irq_chip.h
index 45cabf346e..b45a754f45 100644
--- a/core/riscv-rv32i/irq_chip.h
+++ b/core/riscv-rv32i/irq_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/riscv-rv32i/irq_handler.h b/core/riscv-rv32i/irq_handler.h
index 8d26ae6474..b980e8e0bc 100644
--- a/core/riscv-rv32i/irq_handler.h
+++ b/core/riscv-rv32i/irq_handler.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,11 +20,12 @@
  * Macro to connect the interrupt handler "routine" to the irq number "irq" and
  * ensure it is enabled in the interrupt controller with the right priority.
  */
-#define DECLARE_IRQ(irq, routine, priority)				\
-	void IRQ_HANDLER(CPU_INT(irq))(void)				\
-		__attribute__ ((alias(STRINGIFY(routine))));		\
-	const struct irq_priority __keep IRQ_PRIORITY(CPU_INT(irq))	\
-	__attribute__((section(".rodata.irqprio")))			\
-			= {CPU_INT(irq), priority}
+#define DECLARE_IRQ(irq, routine, priority)                                   \
+	static void __keep routine(void);                                     \
+	void IRQ_HANDLER(CPU_INT(irq))(void)                                  \
+		__attribute__((alias(STRINGIFY(routine))));                   \
+	const struct irq_priority __keep IRQ_PRIORITY(CPU_INT(irq))           \
+		__attribute__((section(".rodata.irqprio"))) = { CPU_INT(irq), \
+								priority }
 
-#endif  /* __CROS_EC_IRQ_HANDLER_H */
+#endif /* __CROS_EC_IRQ_HANDLER_H */
diff --git a/core/riscv-rv32i/math.c b/core/riscv-rv32i/math.c
index 591a67eb8f..425814f185 100644
--- a/core/riscv-rv32i/math.c
+++ b/core/riscv-rv32i/math.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,10 +9,7 @@
 /* Single precision floating point square root. */
 float sqrtf(float x)
 {
-	asm volatile (
-		"fsqrt.s %0, %1"
-		: "=f" (x)
-		: "f" (x));
+	asm volatile("fsqrt.s %0, %1" : "=f"(x) : "f"(x));
 
 	return x;
 }
diff --git a/core/riscv-rv32i/panic.c b/core/riscv-rv32i/panic.c
index 3d8cec1b06..0ea86840f9 100644
--- a/core/riscv-rv32i/panic.c
+++ b/core/riscv-rv32i/panic.c
@@ -1,8 +1,9 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "console.h"
 #include "cpu.h"
 #include "panic.h"
 #include "task.h"
@@ -12,7 +13,7 @@
 /**
  * bit[3-0] @ mcause, general exception type information.
  */
-static const char * const exc_type[16] = {
+static const char *const exc_type[16] = {
 	"Instruction address misaligned",
 	"Instruction access fault",
 	"Illegal instruction",
@@ -33,16 +34,15 @@ static const char * const exc_type[16] = {
 };
 #endif /* CONFIG_DEBUG_EXCEPTIONS */
 
-#ifdef CONFIG_SOFTWARE_PANIC
 /* General purpose register (s0) for saving software panic reason */
 #define SOFT_PANIC_GPR_REASON 11
 /* General purpose register (s1) for saving software panic information */
-#define SOFT_PANIC_GPR_INFO   10
+#define SOFT_PANIC_GPR_INFO 10
 
 void software_panic(uint32_t reason, uint32_t info)
 {
-	asm volatile ("mv s0, %0" : : "r"(reason));
-	asm volatile ("mv s1, %0" : : "r"(info));
+	asm volatile("mv s0, %0" : : "r"(reason) : "s0");
+	asm volatile("mv s1, %0" : : "r"(info) : "s1");
 	if (in_interrupt_context())
 		asm("j excep_handler");
 	else
@@ -57,7 +57,7 @@ void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
 	 * If it was called earlier (eg. when saving riscv.mepc) calling it
 	 * once again won't remove any data
 	 */
-	struct panic_data * const pdata = get_panic_data_write();
+	struct panic_data *const pdata = get_panic_data_write();
 	uint32_t warning_mepc;
 	uint32_t *regs;
 
@@ -84,7 +84,7 @@ void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
 
 void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception)
 {
-	struct panic_data * const pdata = panic_get_data();
+	struct panic_data *const pdata = panic_get_data();
 	uint32_t *regs;
 
 	if (pdata && pdata->struct_version == 2) {
@@ -96,38 +96,35 @@ void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception)
 		*exception = *reason = *info = 0;
 	}
 }
-#endif /* CONFIG_SOFTWARE_PANIC */
 
 static void print_panic_information(uint32_t *regs, uint32_t mcause,
-					uint32_t mepc)
+				    uint32_t mepc)
 {
 	panic_printf("=== EXCEPTION: MCAUSE=%x ===\n", mcause);
-	panic_printf("S11 %08x S10 %08x  S9 %08x  S8   %08x\n",
-		     regs[0], regs[1], regs[2], regs[3]);
-	panic_printf("S7  %08x S6  %08x  S5 %08x  S4   %08x\n",
-		     regs[4], regs[5], regs[6], regs[7]);
-	panic_printf("S3  %08x S2  %08x  S1 %08x  S0   %08x\n",
-		     regs[8], regs[9], regs[10], regs[11]);
-	panic_printf("T6  %08x T5  %08x  T4 %08x  T3   %08x\n",
-		     regs[12], regs[13], regs[14], regs[15]);
-	panic_printf("T2  %08x T1  %08x  T0 %08x  A7   %08x\n",
-		     regs[16], regs[17], regs[18], regs[19]);
-	panic_printf("A6  %08x A5  %08x  A4 %08x  A3   %08x\n",
-		     regs[20], regs[21], regs[22], regs[23]);
-	panic_printf("A2  %08x A1  %08x  A0 %08x  TP   %08x\n",
-		     regs[24], regs[25], regs[26], regs[27]);
-	panic_printf("GP  %08x RA  %08x  SP %08x  MEPC %08x\n",
-		     regs[28], regs[29], regs[30], mepc);
+	panic_printf("S11 %08x S10 %08x  S9 %08x  S8   %08x\n", regs[0],
+		     regs[1], regs[2], regs[3]);
+	panic_printf("S7  %08x S6  %08x  S5 %08x  S4   %08x\n", regs[4],
+		     regs[5], regs[6], regs[7]);
+	panic_printf("S3  %08x S2  %08x  S1 %08x  S0   %08x\n", regs[8],
+		     regs[9], regs[10], regs[11]);
+	panic_printf("T6  %08x T5  %08x  T4 %08x  T3   %08x\n", regs[12],
+		     regs[13], regs[14], regs[15]);
+	panic_printf("T2  %08x T1  %08x  T0 %08x  A7   %08x\n", regs[16],
+		     regs[17], regs[18], regs[19]);
+	panic_printf("A6  %08x A5  %08x  A4 %08x  A3   %08x\n", regs[20],
+		     regs[21], regs[22], regs[23]);
+	panic_printf("A2  %08x A1  %08x  A0 %08x  TP   %08x\n", regs[24],
+		     regs[25], regs[26], regs[27]);
+	panic_printf("GP  %08x RA  %08x  SP %08x  MEPC %08x\n", regs[28],
+		     regs[29], regs[30], mepc);
 
 #ifdef CONFIG_DEBUG_EXCEPTIONS
 	if ((regs[SOFT_PANIC_GPR_REASON] & 0xfffffff0) == PANIC_SW_BASE) {
-#ifdef CONFIG_SOFTWARE_PANIC
 		panic_printf("Software panic reason: %s\n",
-			panic_sw_reasons[(regs[SOFT_PANIC_GPR_REASON] -
-						PANIC_SW_BASE)]);
+			     panic_sw_reasons[(regs[SOFT_PANIC_GPR_REASON] -
+					       PANIC_SW_BASE)]);
 		panic_printf("Software panic info:   %d\n",
-			regs[SOFT_PANIC_GPR_INFO]);
-#endif
+			     regs[SOFT_PANIC_GPR_INFO]);
 	} else {
 		panic_printf("Exception type: %s\n", exc_type[(mcause & 0xf)]);
 	}
@@ -137,7 +134,7 @@ static void print_panic_information(uint32_t *regs, uint32_t mcause,
 void report_panic(uint32_t *regs)
 {
 	uint32_t i, mcause, mepc;
-	struct panic_data * const pdata = get_panic_data_write();
+	struct panic_data *const pdata = get_panic_data_write();
 
 	mepc = get_mepc();
 	mcause = get_mcause();
@@ -167,3 +164,51 @@ void panic_data_print(const struct panic_data *pdata)
 	mepc = pdata->riscv.mepc;
 	print_panic_information(regs, mcause, mepc);
 }
+
+#ifdef CONFIG_PANIC_CONSOLE_OUTPUT
+static void ccprint_panic_information(uint32_t *regs, uint32_t mcause,
+				      uint32_t mepc)
+{
+	ccprintf("=== EXCEPTION: MCAUSE=%x ===\n", mcause);
+	ccprintf("S11 %08x S10 %08x  S9 %08x  S8   %08x\n", regs[0], regs[1],
+		 regs[2], regs[3]);
+	ccprintf("S7  %08x S6  %08x  S5 %08x  S4   %08x\n", regs[4], regs[5],
+		 regs[6], regs[7]);
+	ccprintf("S3  %08x S2  %08x  S1 %08x  S0   %08x\n", regs[8], regs[9],
+		 regs[10], regs[11]);
+	ccprintf("T6  %08x T5  %08x  T4 %08x  T3   %08x\n", regs[12], regs[13],
+		 regs[14], regs[15]);
+	ccprintf("T2  %08x T1  %08x  T0 %08x  A7   %08x\n", regs[16], regs[17],
+		 regs[18], regs[19]);
+	cflush();
+
+	ccprintf("A6  %08x A5  %08x  A4 %08x  A3   %08x\n", regs[20], regs[21],
+		 regs[22], regs[23]);
+	ccprintf("A2  %08x A1  %08x  A0 %08x  TP   %08x\n", regs[24], regs[25],
+		 regs[26], regs[27]);
+	ccprintf("GP  %08x RA  %08x  SP %08x  MEPC %08x\n", regs[28], regs[29],
+		 regs[30], mepc);
+
+#ifdef CONFIG_DEBUG_EXCEPTIONS
+	if ((regs[SOFT_PANIC_GPR_REASON] & 0xfffffff0) == PANIC_SW_BASE) {
+		ccprintf("Software panic reason: %s\n",
+			 panic_sw_reasons[(regs[SOFT_PANIC_GPR_REASON] -
+					   PANIC_SW_BASE)]);
+		ccprintf("Software panic info:   %d\n",
+			 regs[SOFT_PANIC_GPR_INFO]);
+	} else {
+		ccprintf("Exception type: %s\n", exc_type[(mcause & 0xf)]);
+	}
+#endif /* CONFIG_DEBUG_EXCEPTIONS */
+	cflush();
+}
+void panic_data_ccprint(const struct panic_data *pdata)
+{
+	uint32_t *regs, mcause, mepc;
+
+	regs = (uint32_t *)pdata->riscv.regs;
+	mcause = pdata->riscv.mcause;
+	mepc = pdata->riscv.mepc;
+	ccprint_panic_information(regs, mcause, mepc);
+}
+#endif /* CONFIG_PANIC_CONSOLE_OUTPUT */
diff --git a/core/riscv-rv32i/switch.S b/core/riscv-rv32i/switch.S
index d6c00b8591..f8b88f9235 100644
--- a/core/riscv-rv32i/switch.S
+++ b/core/riscv-rv32i/switch.S
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,7 +8,9 @@
 #include "config.h"
 #include "cpu.h"
 
-.text
+#ifdef __RAM_CODE_ILM0_SECTION_NAME
+.section __RAM_CODE_ILM0_SECTION_NAME
+#endif
 
 /**
  * Task context switching
@@ -142,6 +144,7 @@ __switch_task:
         add sp, t3, zero
         j __irq_exit
 
+.text
 /**
  * Start the task scheduling.
  */
diff --git a/core/riscv-rv32i/task.c b/core/riscv-rv32i/task.c
index ecd8d72382..48244bc1b2 100644
--- a/core/riscv-rv32i/task.c
+++ b/core/riscv-rv32i/task.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,10 +6,12 @@
 /* Task scheduling / events module for Chrome EC operating system */
 
 #include "atomic.h"
+#include "builtin/assert.h"
 #include "console.h"
 #include "cpu.h"
 #include "irq_chip.h"
 #include "link_defs.h"
+#include "panic.h"
 #include "task.h"
 #include "timer.h"
 #include "util.h"
@@ -19,10 +21,10 @@ typedef struct {
 	 * Note that sp must be the first element in the task struct
 	 * for __switchto() to work.
 	 */
-	uint32_t sp;       /* Saved stack pointer for context switch */
-	uint32_t events;   /* Bitmaps of received events */
-	uint64_t runtime;  /* Time spent in task */
-	uint32_t *stack;   /* Start of stack */
+	uint32_t sp; /* Saved stack pointer for context switch */
+	atomic_t events; /* Bitmaps of received events */
+	uint64_t runtime; /* Time spent in task */
+	uint32_t *stack; /* Start of stack */
 } task_;
 
 /* Value to store in unused stack */
@@ -36,11 +38,9 @@ CONFIG_TEST_TASK_LIST
 #undef TASK
 
 /* Task names for easier debugging */
-#define TASK(n, r, d, s)  #n,
-static const char * const task_names[] = {
-	"<< idle >>",
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
+#define TASK(n, r, d, s) #n,
+static const char *const task_names[] = {
+	"<< idle >>", CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST
 };
 #undef TASK
 
@@ -48,12 +48,12 @@ static const char * const task_names[] = {
 static int task_will_switch;
 static uint32_t exc_sub_time;
 static uint64_t task_start_time; /* Time task scheduling started */
-static uint32_t exc_start_time;  /* Time of task->exception transition */
-static uint32_t exc_end_time;    /* Time of exception->task transition */
-static uint64_t exc_total_time;  /* Total time in exceptions */
-static uint32_t svc_calls;       /* Number of service calls */
-static uint32_t task_switches;   /* Number of times active task changed */
-static uint32_t irq_dist[CONFIG_IRQ_COUNT];  /* Distribution of IRQ calls */
+static uint32_t exc_start_time; /* Time of task->exception transition */
+static uint32_t exc_end_time; /* Time of exception->task transition */
+static uint64_t exc_total_time; /* Total time in exceptions */
+static uint32_t svc_calls; /* Number of service calls */
+static uint32_t task_switches; /* Number of times active task changed */
+static uint32_t irq_dist[CONFIG_IRQ_COUNT]; /* Distribution of IRQ calls */
 #endif
 
 extern int __task_start(void);
@@ -96,41 +96,36 @@ static void task_exit_trap(void)
 }
 
 /* Startup parameters for all tasks. */
-#define TASK(n, r, d, s)  {	\
-	.a0 = (uint32_t)d,	\
-	.pc = (uint32_t)r,	\
-	.stack_size = s,	\
-},
+#define TASK(n, r, d, s)           \
+	{                          \
+		.a0 = (uint32_t)d, \
+		.pc = (uint32_t)r, \
+		.stack_size = s,   \
+	},
 static const struct {
 	uint32_t a0;
 	uint32_t pc;
 	uint16_t stack_size;
-} tasks_init[] = {
-	TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
-};
+} tasks_init[] = { TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
+			   CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST };
 #undef TASK
 
 /* Contexts for all tasks */
-static task_ tasks[TASK_ID_COUNT] __attribute__ ((section(".bss.tasks")));
+static task_ tasks[TASK_ID_COUNT] __attribute__((section(".bss.tasks")));
 /* Validity checks about static task invariants */
-BUILD_ASSERT(TASK_ID_COUNT <= (sizeof(unsigned) * 8));
+BUILD_ASSERT(TASK_ID_COUNT <= (sizeof(unsigned int) * 8));
 BUILD_ASSERT(TASK_ID_COUNT < (1 << (sizeof(task_id_t) * 8)));
 
 /* Stacks for all tasks */
-#define TASK(n, r, d, s)  + s
-uint8_t task_stacks[0
-		    TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
-		    CONFIG_TASK_LIST
-		    CONFIG_TEST_TASK_LIST
-] __aligned(8);
+#define TASK(n, r, d, s) +s
+uint8_t task_stacks[0 TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
+			    CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST] __aligned(8);
 
 #undef TASK
 
 /* Reserve space to discard context on first context switch. */
-uint32_t scratchpad[TASK_SCRATCHPAD_SIZE] __attribute__
-					((section(".bss.task_scratchpad")));
+uint32_t scratchpad[TASK_SCRATCHPAD_SIZE]
+	__attribute__((section(".bss.task_scratchpad")));
 
 task_ *current_task = (task_ *)scratchpad;
 
@@ -154,18 +149,18 @@ int need_resched;
  * can do their init within a task switching context.  The hooks task will then
  * make a call to enable all tasks.
  */
-static uint32_t tasks_ready = BIT(TASK_ID_HOOKS);
+static atomic_t tasks_ready = BIT(TASK_ID_HOOKS);
 /*
  * Initially allow only the HOOKS and IDLE task to run, regardless of ready
  * status, in order for HOOK_INIT to complete before other tasks.
  * task_enable_all_tasks() will open the flood gates.
  */
-static uint32_t tasks_enabled = BIT(TASK_ID_HOOKS) | BIT(TASK_ID_IDLE);
+static atomic_t tasks_enabled = BIT(TASK_ID_HOOKS) | BIT(TASK_ID_IDLE);
 
-int start_called;  /* Has task swapping started */
+int start_called; /* Has task swapping started */
 
 /* in interrupt context */
-static volatile int in_interrupt;
+volatile bool in_interrupt;
 /* Interrupt number of EC modules */
 volatile int ec_int;
 /* Interrupt group of EC INTC modules */
@@ -188,23 +183,33 @@ static inline task_ *__task_id_to_ptr(task_id_t id)
 void __ram_code interrupt_disable(void)
 {
 	/* bit11: disable MEIE */
-	asm volatile ("li t0, 0x800");
-	asm volatile ("csrc mie, t0");
+	asm volatile("li t0, 0x800");
+	asm volatile("csrc mie, t0");
 }
 
 void __ram_code interrupt_enable(void)
 {
 	/* bit11: enable MEIE */
-	asm volatile ("li t0, 0x800");
-	asm volatile ("csrs  mie, t0");
+	asm volatile("li t0, 0x800");
+	asm volatile("csrs  mie, t0");
+}
+
+inline bool is_interrupt_enabled(void)
+{
+	int mie = 0;
+
+	asm volatile("csrr %0, mie" : "=r"(mie));
+
+	/* Check if MEIE bit is set in MIE register */
+	return mie & 0x800;
 }
 
-inline int in_interrupt_context(void)
+inline bool in_interrupt_context(void)
 {
 	return in_interrupt;
 }
 
-int in_soft_interrupt_context(void)
+bool in_soft_interrupt_context(void)
 {
 	/* group 16 is reserved for soft-irq */
 	return in_interrupt_context() && ec_int_group == 16;
@@ -219,7 +224,7 @@ task_id_t __ram_code task_get_current(void)
 	return current_task - tasks;
 }
 
-uint32_t * __ram_code task_get_event_bitmap(task_id_t tskid)
+atomic_t *__ram_code task_get_event_bitmap(task_id_t tskid)
 {
 	task_ *tsk = __task_id_to_ptr(tskid);
 
@@ -237,7 +242,7 @@ int task_start_called(void)
  * Also includes emulation of software triggering interrupt vector
  */
 void __ram_code __keep syscall_handler(int desched, task_id_t resched,
-								int swirq)
+				       int swirq)
 {
 	/* are we emulating an interrupt ? */
 	if (swirq) {
@@ -269,14 +274,14 @@ void __ram_code __keep syscall_handler(int desched, task_id_t resched,
 	set_mepc(get_mepc() + 4);
 }
 
-task_ * __ram_code next_sched_task(void)
+task_ *__ram_code next_sched_task(void)
 {
 	task_ *new_task = __task_id_to_ptr(__fls(tasks_ready & tasks_enabled));
 
 #ifdef CONFIG_TASK_PROFILING
 	if (current_task != new_task) {
 		current_task->runtime +=
-				(exc_start_time - exc_end_time - exc_sub_time);
+			(exc_start_time - exc_end_time - exc_sub_time);
 		task_will_switch = 1;
 	}
 #endif
@@ -284,11 +289,11 @@ task_ * __ram_code next_sched_task(void)
 #ifdef CONFIG_DEBUG_STACK_OVERFLOW
 	if (*current_task->stack != STACK_UNUSED_VALUE) {
 		int i = task_get_current();
-
-		panic_printf("\n\nStack overflow in %s task!\n", task_names[i]);
-#ifdef CONFIG_SOFTWARE_PANIC
-		software_panic(PANIC_SW_STACK_OVERFLOW, i);
-#endif
+		if (task_enabled(i)) {
+			panic_printf("\n\nStack overflow in %s task!\n",
+				     task_names[i]);
+			software_panic(PANIC_SW_STACK_OVERFLOW, i);
+		}
 	}
 #endif
 
@@ -311,16 +316,14 @@ void __ram_code update_exc_start_time(void)
 #endif
 }
 
-void __ram_code start_irq_handler(void)
+/**
+ * The beginning of interrupt handler of c language code.
+ *
+ * @param  none
+ * @return -1 if it cannot find the corresponding interrupt source.
+ */
+int __ram_code start_irq_handler(void)
 {
-	/* save a0, a1, and a2 for syscall */
-	asm volatile ("addi sp, sp, -4*3");
-	asm volatile ("sw a0, 0(sp)");
-	asm volatile ("sw a1, 1*4(sp)");
-	asm volatile ("sw a2, 2*4(sp)");
-
-	in_interrupt = 1;
-
 	/* If this is a SW interrupt */
 	if (get_mcause() == 11) {
 		ec_int = sw_int_num;
@@ -330,9 +333,8 @@ void __ram_code start_irq_handler(void)
 		 * Determine interrupt number.
 		 * -1 if it cannot find the corresponding interrupt source.
 		 */
-		ec_int = chip_get_ec_int();
-		if (ec_int == -1)
-			goto error;
+		if (chip_get_ec_int() == -1)
+			return -1;
 		ec_int_group = chip_get_intc_group(ec_int);
 	}
 
@@ -350,15 +352,7 @@ void __ram_code start_irq_handler(void)
 		irq_dist[ec_int]++;
 #endif
 
-error:
-	/* cannot use return statement because a0 has been used */
-	asm volatile ("add t0, zero, %0" :: "r"(ec_int));
-
-	/* restore a0, a1, and a2 */
-	asm volatile ("lw a0, 0(sp)");
-	asm volatile ("lw a1, 1*4(sp)");
-	asm volatile ("lw a2, 2*4(sp)");
-	asm volatile ("addi sp, sp, 4*3");
+	return EC_SUCCESS;
 }
 
 void __ram_code end_irq_handler(void)
@@ -378,7 +372,6 @@ void __ram_code end_irq_handler(void)
 		task_switches++;
 	}
 #endif
-	in_interrupt = 0;
 }
 
 static uint32_t __ram_code __wait_evt(int timeout_us, task_id_t resched)
@@ -397,7 +390,7 @@ static uint32_t __ram_code __wait_evt(int timeout_us, task_id_t resched)
 		ret = timer_arm(deadline, me);
 		ASSERT(ret == EC_SUCCESS);
 	}
-	while (!(evt = deprecated_atomic_read_clear(&tsk->events))) {
+	while (!(evt = atomic_clear(&tsk->events))) {
 		/* Remove ourself and get the next task in the scheduler */
 		__schedule(1, resched, 0);
 		resched = TASK_ID_IDLE;
@@ -405,34 +398,29 @@ static uint32_t __ram_code __wait_evt(int timeout_us, task_id_t resched)
 	if (timeout_us > 0) {
 		timer_cancel(me);
 		/* Ensure timer event is clear, we no longer care about it */
-		deprecated_atomic_clear_bits(&tsk->events, TASK_EVENT_TIMER);
+		atomic_clear_bits(&tsk->events, TASK_EVENT_TIMER);
 	}
 	return evt;
 }
 
-uint32_t __ram_code task_set_event(task_id_t tskid, uint32_t event, int wait)
+void __ram_code task_set_event(task_id_t tskid, uint32_t event)
 {
 	task_ *receiver = __task_id_to_ptr(tskid);
 
 	ASSERT(receiver);
 
 	/* Set the event bit in the receiver message bitmap */
-	deprecated_atomic_or(&receiver->events, event);
+	atomic_or(&receiver->events, event);
 
 	/* Re-schedule if priorities have changed */
 	if (in_interrupt_context()) {
 		/* The receiver might run again */
-		deprecated_atomic_or(&tasks_ready, 1 << tskid);
+		atomic_or(&tasks_ready, 1 << tskid);
 		if (start_called)
 			need_resched = 1;
 	} else {
-		if (wait)
-			return __wait_evt(-1, tskid);
-		else
-			__schedule(0, tskid, 0);
+		__schedule(0, tskid, 0);
 	}
-
-	return 0;
 }
 
 uint32_t __ram_code task_wait_event(int timeout_us)
@@ -463,8 +451,7 @@ uint32_t __ram_code task_wait_event_mask(uint32_t event_mask, int timeout_us)
 
 	/* Re-post any other events collected */
 	if (events & ~event_mask)
-		deprecated_atomic_or(&current_task->events,
-				     events & ~event_mask);
+		atomic_or(&current_task->events, events & ~event_mask);
 
 	return events & event_mask;
 }
@@ -474,14 +461,14 @@ uint32_t __ram_code read_clear_int_mask(void)
 	uint32_t mie, meie = BIT(11);
 
 	/* Read and clear MEIE bit of MIE register. */
-	asm volatile ("csrrc %0, mie, %1" : "=r"(mie) : "r"(meie));
+	asm volatile("csrrc %0, mie, %1" : "=r"(mie) : "r"(meie));
 
 	return mie;
 }
 
 void __ram_code set_int_mask(uint32_t val)
 {
-	asm volatile ("csrw mie, %0" : : "r"(val));
+	asm volatile("csrw mie, %0" : : "r"(val));
 }
 
 void task_enable_all_tasks(void)
@@ -494,12 +481,17 @@ void task_enable_all_tasks(void)
 
 void task_enable_task(task_id_t tskid)
 {
-	deprecated_atomic_or(&tasks_enabled, BIT(tskid));
+	atomic_or(&tasks_enabled, BIT(tskid));
+}
+
+bool task_enabled(task_id_t tskid)
+{
+	return tasks_enabled & BIT(tskid);
 }
 
 void task_disable_task(task_id_t tskid)
 {
-	deprecated_atomic_clear_bits(&tasks_enabled, BIT(tskid));
+	atomic_clear_bits(&tasks_enabled, BIT(tskid));
 
 	if (!in_interrupt_context() && tskid == task_get_current())
 		__schedule(0, 0, 0);
@@ -558,15 +550,15 @@ void __ram_code mutex_lock(struct mutex *mtx)
 	uint32_t id = 1 << task_get_current();
 
 	ASSERT(id != TASK_ID_INVALID);
-	deprecated_atomic_or(&mtx->waiters, id);
+	atomic_or(&mtx->waiters, id);
 
 	while (1) {
-		asm volatile (
+		asm volatile(
 			/* set lock value */
 			"li %0, 2\n\t"
 			/* attempt to acquire lock */
 			"amoswap.w.aq %0, %0, %1\n\t"
-			: "=r" (locked), "+A" (mtx->lock));
+			: "=&r"(locked), "+A"(mtx->lock));
 		/* we got it ! */
 		if (!locked)
 			break;
@@ -575,7 +567,7 @@ void __ram_code mutex_lock(struct mutex *mtx)
 		task_wait_event_mask(TASK_EVENT_MUTEX, 0);
 	}
 
-	deprecated_atomic_clear_bits(&mtx->waiters, id);
+	atomic_clear_bits(&mtx->waiters, id);
 }
 
 void __ram_code mutex_unlock(struct mutex *mtx)
@@ -584,9 +576,7 @@ void __ram_code mutex_unlock(struct mutex *mtx)
 	task_ *tsk = current_task;
 
 	/* give back the lock */
-	asm volatile (
-		"amoswap.w.aqrl zero, zero, %0\n\t"
-		: "+A" (mtx->lock));
+	asm volatile("amoswap.w.aqrl zero, zero, %0\n\t" : "+A"(mtx->lock));
 	waiters = mtx->waiters;
 
 	while (waiters) {
@@ -595,11 +585,11 @@ void __ram_code mutex_unlock(struct mutex *mtx)
 		waiters &= ~BIT(id);
 
 		/* Somebody is waiting on the mutex */
-		task_set_event(id, TASK_EVENT_MUTEX, 0);
+		task_set_event(id, TASK_EVENT_MUTEX);
 	}
 
 	/* Ensure no event is remaining from mutex wake-up */
-	deprecated_atomic_clear_bits(&tsk->events, TASK_EVENT_MUTEX);
+	atomic_clear_bits(&tsk->events, TASK_EVENT_MUTEX);
 }
 
 void task_print_list(void)
@@ -609,7 +599,7 @@ void task_print_list(void)
 	ccputs("Task Ready Name         Events      Time (s)  StkUsed\n");
 
 	for (i = 0; i < TASK_ID_COUNT; i++) {
-		char is_ready = (tasks_ready & (1<<i)) ? 'R' : ' ';
+		char is_ready = ((uint32_t)tasks_ready & BIT(i)) ? 'R' : ' ';
 		uint32_t *sp;
 
 		int stackused = tasks_init[i].stack_size;
@@ -620,13 +610,13 @@ void task_print_list(void)
 			stackused -= sizeof(uint32_t);
 
 		ccprintf("%4d %c %-16s %08x %11.6lld  %3d/%3d\n", i, is_ready,
-			 task_names[i], tasks[i].events, tasks[i].runtime,
+			 task_names[i], (int)tasks[i].events, tasks[i].runtime,
 			 stackused, tasks_init[i].stack_size);
 		cflush();
 	}
 }
 
-int command_task_info(int argc, char **argv)
+static int command_task_info(int argc, const char **argv)
 {
 #ifdef CONFIG_TASK_PROFILING
 	unsigned int total = 0;
@@ -656,24 +646,21 @@ int command_task_info(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(taskinfo, command_task_info,
-			NULL,
-			"Print task info");
+DECLARE_CONSOLE_COMMAND(taskinfo, command_task_info, NULL, "Print task info");
 
-static int command_task_ready(int argc, char **argv)
+static int command_task_ready(int argc, const char **argv)
 {
 	if (argc < 2) {
-		ccprintf("tasks_ready: 0x%08x\n", tasks_ready);
+		ccprintf("tasks_ready: 0x%08x\n", (int)tasks_ready);
 	} else {
 		tasks_ready = strtoi(argv[1], NULL, 16);
-		ccprintf("Setting tasks_ready to 0x%08x\n", tasks_ready);
+		ccprintf("Setting tasks_ready to 0x%08x\n", (int)tasks_ready);
 		__schedule(0, 0, 0);
 	}
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(taskready, command_task_ready,
-			"[setmask]",
+DECLARE_CONSOLE_COMMAND(taskready, command_task_ready, "[setmask]",
 			"Print/set ready tasks");
 
 void task_pre_init(void)
@@ -696,9 +683,10 @@ void task_pre_init(void)
 		tasks[i].sp = (uint32_t)sp;
 
 		/* Initial context on stack (see __switchto()) */
-		sp[TASK_SCRATCHPAD_SIZE-2] = tasks_init[i].a0;         /* a0 */
-		sp[TASK_SCRATCHPAD_SIZE-1] = (uint32_t)task_exit_trap; /* ra */
-		sp[0] = tasks_init[i].pc;  /* pc/mepc */
+		sp[TASK_SCRATCHPAD_SIZE - 2] = tasks_init[i].a0; /* a0 */
+		sp[TASK_SCRATCHPAD_SIZE - 1] = (uint32_t)task_exit_trap; /* ra
+									  */
+		sp[0] = tasks_init[i].pc; /* pc/mepc */
 
 		/* Fill unused stack; also used to detect stack overflow. */
 		for (sp = stack_next; sp < (uint32_t *)tasks[i].sp; sp++)
diff --git a/core/riscv-rv32i/toolchain.mk b/core/riscv-rv32i/toolchain.mk
new file mode 100644
index 0000000000..aa833d1ca3
--- /dev/null
+++ b/core/riscv-rv32i/toolchain.mk
@@ -0,0 +1,7 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Select RISC-V bare-metal toolchain
+$(call set-option,CROSS_COMPILE,$(CROSS_COMPILE_riscv),\
+	/opt/coreboot-sdk/bin/riscv64-elf-)
diff --git a/crypto/build.mk b/crypto/build.mk
new file mode 100644
index 0000000000..fbbfed1ac9
--- /dev/null
+++ b/crypto/build.mk
@@ -0,0 +1,8 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Crypto related Files
+#
+
+crypto-y+=elliptic_curve_key.o
diff --git a/crypto/elliptic_curve_key.cc b/crypto/elliptic_curve_key.cc
new file mode 100644
index 0000000000..53741d0944
--- /dev/null
+++ b/crypto/elliptic_curve_key.cc
@@ -0,0 +1,24 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "crypto/elliptic_curve_key.h"
+#include "openssl/ec_key.h"
+#include "openssl/mem.h"
+#include "openssl/obj_mac.h"
+
+bssl::UniquePtr<EC_KEY> generate_elliptic_curve_key()
+{
+	bssl::UniquePtr<EC_KEY> key(
+		EC_KEY_new_by_curve_name(NID_X9_62_prime256v1));
+	if (key == nullptr) {
+		return nullptr;
+	}
+
+	if (EC_KEY_generate_key(key.get()) != 1) {
+		return nullptr;
+	}
+
+	return key;
+}
diff --git a/cts/build.mk b/cts/build.mk
index 3f0cd750db..44db306f40 100644
--- a/cts/build.mk
+++ b/cts/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -13,7 +13,7 @@ ifeq "$(CTS_MODULE)" "i2c"
 CFLAGS_CTS+=-DCTS_MODULE_I2C=$(EMPTY)
 CONFIG_I2C=y
 ifneq ($(BOARD),stm32l476g-eval)
-CONFIG_I2C_MASTER=y
+CONFIG_I2C_CONTROLLER=y
 endif
 endif
 
diff --git a/cts/common/board.py b/cts/common/board.py
index 478da1479c..d04f73fe5f 100644
--- a/cts/common/board.py
+++ b/cts/common/board.py
@@ -1,4 +1,4 @@
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -6,379 +6,417 @@
 
 from __future__ import print_function
 
-from abc import ABCMeta
-from abc import abstractmethod
+from abc import ABCMeta, abstractmethod
 import os
 import shutil
 import subprocess as sp
-import serial
 
+import serial  # pylint:disable=import-error
 import six
 
 
-OCD_SCRIPT_DIR = '/usr/share/openocd/scripts'
+OCD_SCRIPT_DIR = "/usr/share/openocd/scripts"
 OPENOCD_CONFIGS = {
-    'stm32l476g-eval': 'board/stm32l4discovery.cfg',
-    'nucleo-f072rb': 'board/st_nucleo_f0.cfg',
-    'nucleo-f411re': 'board/st_nucleo_f4.cfg',
+    "stm32l476g-eval": "board/stm32l4discovery.cfg",
+    "nucleo-f072rb": "board/st_nucleo_f0.cfg",
+    "nucleo-f411re": "board/st_nucleo_f4.cfg",
 }
 FLASH_OFFSETS = {
-    'stm32l476g-eval': '0x08000000',
-    'nucleo-f072rb': '0x08000000',
-    'nucleo-f411re': '0x08000000',
+    "stm32l476g-eval": "0x08000000",
+    "nucleo-f072rb": "0x08000000",
+    "nucleo-f411re": "0x08000000",
 }
-REBOOT_MARKER = 'UART initialized after reboot'
+REBOOT_MARKER = "UART initialized after reboot"
 
 
 def get_subprocess_args():
-  if six.PY3:
-    return {'encoding': 'utf-8'}
-  return {}
+    if six.PY3:
+        return {"encoding": "utf-8"}
+    return {}
 
 
 class Board(six.with_metaclass(ABCMeta, object)):
-  """Class representing a single board connected to a host machine.
-
-  Attributes:
-    board: String containing actual type of board, i.e. nucleo-f072rb
-    config: Directory of board config file relative to openocd's
-        scripts directory
-    hla_serial: String containing board's hla_serial number (if board
-    is an stm32 board)
-    tty_port: String that is the path to the tty port which board's
-        UART outputs to
-    tty: String of file descriptor for tty_port
-  """
-
-  def __init__(self, board, module, hla_serial=None):
-    """Initializes a board object with given attributes.
-
-    Args:
-      board: String containing board name
-      module: String of the test module you are building,
-        i.e. gpio, timer, etc.
-      hla_serial: Serial number if board's adaptor is an HLA
-
-    Raises:
-      RuntimeError: Board is not supported
+    """Class representing a single board connected to a host machine.
+
+    Attributes:
+      board: String containing actual type of board, i.e. nucleo-f072rb
+      config: Directory of board config file relative to openocd's
+          scripts directory
+      hla_serial: String containing board's hla_serial number (if board
+      is an stm32 board)
+      tty_port: String that is the path to the tty port which board's
+          UART outputs to
+      tty: String of file descriptor for tty_port
     """
-    if board not in OPENOCD_CONFIGS:
-      msg = 'OpenOcd configuration not found for ' + board
-      raise RuntimeError(msg)
-    if board not in FLASH_OFFSETS:
-      msg = 'Flash offset not found for ' + board
-      raise RuntimeError(msg)
-    self.board = board
-    self.flash_offset = FLASH_OFFSETS[self.board]
-    self.openocd_config = OPENOCD_CONFIGS[self.board]
-    self.module = module
-    self.hla_serial = hla_serial
-    self.tty_port = None
-    self.tty = None
-
-  def reset_log_dir(self):
-    """Reset log directory."""
-    if os.path.isdir(self.log_dir):
-      shutil.rmtree(self.log_dir)
-    os.makedirs(self.log_dir)
-
-  @staticmethod
-  def get_stlink_serials():
-    """Gets serial numbers of all st-link v2.1 board attached to host.
-
-    Returns:
-      List of serials
-    """
-    usb_args = ['sudo', 'lsusb', '-v', '-d', '0x0483:0x374b']
-    st_link_info = sp.check_output(usb_args, **get_subprocess_args())
-    st_serials = []
-    for line in st_link_info.split('\n'):
-      if 'iSerial' not in line:
-        continue
-      words = line.split()
-      if len(words) <= 2:
-        continue
-      st_serials.append(words[2].strip())
-    return st_serials
-
-  @abstractmethod
-  def get_serial(self):
-    """Subclass should implement this."""
-    pass
-
-  def send_openocd_commands(self, commands):
-    """Send a command to the board via openocd.
-
-    Args:
-      commands: A list of commands to send
-
-    Returns:
-      True if execution is successful or False otherwise.
-    """
-    args = ['sudo', 'openocd', '-s', OCD_SCRIPT_DIR,
-            '-f', self.openocd_config, '-c', 'hla_serial ' + self.hla_serial]
-
-    for cmd in commands:
-      args += ['-c', cmd]
-    args += ['-c', 'shutdown']
-
-    rv = 1
-    with open(self.openocd_log, 'a') as output:
-      rv = sp.call(args, stdout=output, stderr=sp.STDOUT)
-
-    if rv != 0:
-      self.dump_openocd_log()
-
-    return rv == 0
-
-  def dump_openocd_log(self):
-    with open(self.openocd_log) as log:
-      print(log.read())
 
-  def build(self, ec_dir):
-    """Builds test suite module for board.
-
-    Args:
-      ec_dir: String of the ec directory path
-
-    Returns:
-      True if build is successful or False otherwise.
-    """
-    cmds = ['make',
-            '--directory=' + ec_dir,
-            'BOARD=' + self.board,
-            'CTS_MODULE=' + self.module,
-            '-j']
-
-    rv = 1
-    with open(self.build_log, 'a') as output:
-      rv = sp.call(cmds, stdout=output, stderr=sp.STDOUT)
-
-    if rv != 0:
-      self.dump_build_log()
-
-    return rv == 0
-
-  def dump_build_log(self):
-    with open(self.build_log) as log:
-      print(log.read())
-
-  def flash(self, image_path):
-    """Flashes board with most recent build ec.bin."""
-    cmd = ['reset_config connect_assert_srst',
-           'init',
-           'reset init',
-           'flash write_image erase %s %s' % (image_path, self.flash_offset)]
-    return self.send_openocd_commands(cmd)
-
-  def to_string(self):
-    s = ('Type: Board\n'
-         'board: ' + self.board + '\n'
-         'hla_serial: ' + self.hla_serial + '\n'
-         'openocd_config: ' + self.openocd_config + '\n'
-         'tty_port: ' + self.tty_port + '\n'
-         'tty: ' + str(self.tty) + '\n')
-    return s
-
-  def reset_halt(self):
-    """Reset then halt board."""
-    return self.send_openocd_commands(['init', 'reset halt'])
-
-  def resume(self):
-    """Resume halting board."""
-    return self.send_openocd_commands(['init', 'resume'])
-
-  def setup_tty(self):
-    """Call this before calling read_tty for the first time.
-
-    This is not in the initialization because caller only should call
-    this function after serial numbers are setup
-    """
-    self.get_serial()
-    self.reset_halt()
-    self.identify_tty_port()
-
-    tty = None
-    try:
-      tty = serial.Serial(self.tty_port, 115200, timeout=1)
-    except serial.SerialException:
-      raise ValueError('Failed to open ' + self.tty_port + ' of ' + self.board +
-                       '. Please make sure the port is available and you have' +
-                       ' permission to read it. Create dialout group and run:' +
-                       ' sudo usermod -a -G dialout <username>.')
-    self.tty = tty
-
-  def read_tty(self, max_boot_count=1):
-    """Read info from a serial port described by a file descriptor.
-
-    Args:
-      max_boot_count: Stop reading if boot count exceeds this number
-
-    Returns:
-      result: characters read from tty
-      boot: boot counts
-    """
-    buf = []
-    line = []
-    boot = 0
-    while True:
-      c = self.tty.read().decode('utf-8')
-      if not c:
-        break
-      line.append(c)
-      if c == '\n':
-        l = ''.join(line)
-        buf.append(l)
-        if REBOOT_MARKER in l:
-          boot += 1
+    def __init__(self, board, module, hla_serial=None):
+        """Initializes a board object with given attributes.
+
+        Args:
+          board: String containing board name
+          module: String of the test module you are building,
+            i.e. gpio, timer, etc.
+          hla_serial: Serial number if board's adaptor is an HLA
+
+        Raises:
+          RuntimeError: Board is not supported
+        """
+        if board not in OPENOCD_CONFIGS:
+            msg = "OpenOcd configuration not found for " + board
+            raise RuntimeError(msg)
+        if board not in FLASH_OFFSETS:
+            msg = "Flash offset not found for " + board
+            raise RuntimeError(msg)
+        self.board = board
+        self.flash_offset = FLASH_OFFSETS[self.board]
+        self.openocd_config = OPENOCD_CONFIGS[self.board]
+        self.module = module
+        self.hla_serial = hla_serial
+        self.tty_port = None
+        self.tty = None
+        self.log_dir = None
+        self.openocd_log = os.devnull
+        self.build_log = os.devnull
+
+    def reset_log_dir(self):
+        """Reset log directory."""
+        if self.log_dir:
+            if os.path.isdir(self.log_dir):
+                shutil.rmtree(self.log_dir)
+            os.makedirs(self.log_dir)
+
+    @staticmethod
+    def get_stlink_serials():
+        """Gets serial numbers of all st-link v2.1 board attached to host.
+
+        Returns:
+          List of serials
+        """
+        usb_args = ["sudo", "lsusb", "-v", "-d", "0x0483:0x374b"]
+        st_link_info = sp.check_output(usb_args, **get_subprocess_args())
+        st_serials = []
+        for line in st_link_info.split("\n"):
+            if "iSerial" not in line:
+                continue
+            words = line.split()
+            if len(words) <= 2:
+                continue
+            st_serials.append(words[2].strip())
+        return st_serials
+
+    @abstractmethod
+    def get_serial(self):
+        """Subclass should implement this."""
+        pass
+
+    def send_openocd_commands(self, commands):
+        """Send a command to the board via openocd.
+
+        Args:
+          commands: A list of commands to send
+
+        Returns:
+          True if execution is successful or False otherwise.
+        """
+        args = [
+            "sudo",
+            "openocd",
+            "-s",
+            OCD_SCRIPT_DIR,
+            "-f",
+            self.openocd_config,
+            "-c",
+            "hla_serial " + self.hla_serial,
+        ]
+
+        for cmd in commands:
+            args += ["-c", cmd]
+        args += ["-c", "shutdown"]
+
+        rv = 1
+        with open(self.openocd_log, "a") as output:
+            rv = sp.call(args, stdout=output, stderr=sp.STDOUT)
+
+        if rv != 0:
+            self.dump_openocd_log()
+
+        return rv == 0
+
+    def dump_openocd_log(self):
+        with open(self.openocd_log) as log:
+            print(log.read())
+
+    def build(self, ec_dir):
+        """Builds test suite module for board.
+
+        Args:
+          ec_dir: String of the ec directory path
+
+        Returns:
+          True if build is successful or False otherwise.
+        """
+        cmds = [
+            "make",
+            "--directory=" + ec_dir,
+            "BOARD=" + self.board,
+            "CTS_MODULE=" + self.module,
+            "-j",
+        ]
+
+        rv = 1
+        with open(self.build_log, "a") as output:
+            rv = sp.call(cmds, stdout=output, stderr=sp.STDOUT)
+
+        if rv != 0:
+            self.dump_build_log()
+
+        return rv == 0
+
+    def dump_build_log(self):
+        with open(self.build_log) as log:
+            print(log.read())
+
+    def flash(self, image_path):
+        """Flashes board with most recent build ec.bin."""
+        cmd = [
+            "reset_config connect_assert_srst",
+            "init",
+            "reset init",
+            "flash write_image erase %s %s" % (image_path, self.flash_offset),
+        ]
+        return self.send_openocd_commands(cmd)
+
+    def to_string(self):
+        s = (
+            "Type: Board\n"
+            "board: " + self.board + "\n"
+            "hla_serial: " + self.hla_serial + "\n"
+            "openocd_config: " + self.openocd_config + "\n"
+            "tty_port: " + self.tty_port + "\n"
+            "tty: " + str(self.tty) + "\n"
+        )
+        return s
+
+    def reset_halt(self):
+        """Reset then halt board."""
+        return self.send_openocd_commands(["init", "reset halt"])
+
+    def resume(self):
+        """Resume halting board."""
+        return self.send_openocd_commands(["init", "resume"])
+
+    def setup_tty(self):
+        """Call this before calling read_tty for the first time.
+
+        This is not in the initialization because caller only should call
+        this function after serial numbers are setup
+        """
+        self.get_serial()
+        self.reset_halt()
+        self.identify_tty_port()
+
+        tty = None
+        try:
+            tty = serial.Serial(self.tty_port, 115200, timeout=1)
+        except serial.SerialException:
+            raise ValueError(
+                "Failed to open "
+                + self.tty_port
+                + " of "
+                + self.board
+                + ". Please make sure the port is available and you have"
+                + " permission to read it. Create dialout group and run:"
+                + " sudo usermod -a -G dialout <username>."
+            )
+        self.tty = tty
+
+    def read_tty(self, max_boot_count=1):
+        """Read info from a serial port described by a file descriptor.
+
+        Args:
+          max_boot_count: Stop reading if boot count exceeds this number
+
+        Returns:
+          result: characters read from tty
+          boot: boot counts
+        """
+        buf = []
         line = []
-        if boot > max_boot_count:
-          break
-
-    l = ''.join(line)
-    buf.append(l)
-    result = ''.join(buf)
-
-    return result, boot
-
-  def identify_tty_port(self):
-    """Saves this board's serial port."""
-    dev_dir = '/dev'
-    id_prefix = 'ID_SERIAL_SHORT='
-    com_devices = [f for f in os.listdir(dev_dir) if f.startswith('ttyACM')]
-
-    for device in com_devices:
-      self.tty_port = os.path.join(dev_dir, device)
-      properties = sp.check_output(
-          ['udevadm', 'info', '-a', '-n', self.tty_port, '--query=property'],
-          **get_subprocess_args())
-      for line in [l.strip() for l in properties.split('\n')]:
-        if line.startswith(id_prefix):
-          if self.hla_serial == line[len(id_prefix):]:
-            return
-
-    # If we get here without returning, something is wrong
-    raise RuntimeError('The device dev path could not be found')
-
-  def close_tty(self):
-    """Close tty."""
-    self.tty.close()
+        boot = 0
+        while True:
+            c = self.tty.read().decode("utf-8")
+            if not c:
+                break
+            line.append(c)
+            if c == "\n":
+                l = "".join(line)
+                buf.append(l)
+                if REBOOT_MARKER in l:
+                    boot += 1
+                line = []
+                if boot > max_boot_count:
+                    break
+
+        l = "".join(line)
+        buf.append(l)
+        result = "".join(buf)
+
+        return result, boot
+
+    def identify_tty_port(self):
+        """Saves this board's serial port."""
+        dev_dir = "/dev"
+        id_prefix = "ID_SERIAL_SHORT="
+        com_devices = [f for f in os.listdir(dev_dir) if f.startswith("ttyACM")]
+
+        for device in com_devices:
+            self.tty_port = os.path.join(dev_dir, device)
+            properties = sp.check_output(
+                [
+                    "udevadm",
+                    "info",
+                    "-a",
+                    "-n",
+                    self.tty_port,
+                    "--query=property",
+                ],
+                **get_subprocess_args()
+            )
+            for line in [l.strip() for l in properties.split("\n")]:
+                if line.startswith(id_prefix):
+                    if self.hla_serial == line[len(id_prefix) :]:
+                        return
+
+        # If we get here without returning, something is wrong
+        raise RuntimeError("The device dev path could not be found")
+
+    def close_tty(self):
+        """Close tty."""
+        self.tty.close()
 
 
 class TestHarness(Board):
-  """Subclass of Board representing a Test Harness.
+    """Subclass of Board representing a Test Harness.
 
-  Attributes:
-    serial_path: Path to file containing serial number
-  """
-
-  def __init__(self, board, module, log_dir, serial_path):
-    """Initializes a board object with given attributes.
-
-    Args:
-      board: board name
-      module: module name
-      log_dir: Directory where log file is stored
+    Attributes:
       serial_path: Path to file containing serial number
     """
-    Board.__init__(self, board, module)
-    self.log_dir = log_dir
-    self.openocd_log = os.path.join(log_dir, 'openocd_th.log')
-    self.build_log = os.path.join(log_dir, 'build_th.log')
-    self.serial_path = serial_path
-    self.reset_log_dir()
-
-  def get_serial(self):
-    """Loads serial number from saved location."""
-    if self.hla_serial:
-      return  # serial was already loaded
-    try:
-      with open(self.serial_path, mode='r') as f:
-        s = f.read()
-        self.hla_serial = s.strip()
+
+    def __init__(self, board, module, log_dir, serial_path):
+        """Initializes a board object with given attributes.
+
+        Args:
+          board: board name
+          module: module name
+          log_dir: Directory where log file is stored
+          serial_path: Path to file containing serial number
+        """
+        Board.__init__(self, board, module)
+        self.log_dir = log_dir
+        self.openocd_log = os.path.join(log_dir, "openocd_th.log")
+        self.build_log = os.path.join(log_dir, "build_th.log")
+        self.serial_path = serial_path
+        self.reset_log_dir()
+
+    def get_serial(self):
+        """Loads serial number from saved location."""
+        if self.hla_serial:
+            return  # serial was already loaded
+        try:
+            with open(self.serial_path, mode="r") as f:
+                s = f.read()
+                self.hla_serial = s.strip()
+                return
+        except IOError:
+            msg = (
+                "Your TH board has not been identified.\n"
+                "Connect only TH and run the script --setup, then try again."
+            )
+            raise RuntimeError(msg)
+
+    def save_serial(self):
+        """Saves the TH serial number to a file."""
+        serials = Board.get_stlink_serials()
+        if len(serials) > 1:
+            msg = (
+                "There are more than one test board connected to the host."
+                "\nConnect only the test harness and remove other boards."
+            )
+            raise RuntimeError(msg)
+        if len(serials) < 1:
+            msg = "No test boards were found.\n" "Check boards are connected."
+            raise RuntimeError(msg)
+
+        s = serials[0]
+        serial_dir = os.path.dirname(self.serial_path)
+        if not os.path.exists(serial_dir):
+            os.makedirs(serial_dir)
+        with open(self.serial_path, mode="w") as f:
+            f.write(s)
+            self.hla_serial = s
+
+        print("Your TH serial", s, "has been saved as", self.serial_path)
         return
-    except IOError:
-      msg = ('Your TH board has not been identified.\n'
-             'Connect only TH and run the script --setup, then try again.')
-      raise RuntimeError(msg)
-
-  def save_serial(self):
-    """Saves the TH serial number to a file."""
-    serials = Board.get_stlink_serials()
-    if len(serials) > 1:
-      msg = ('There are more than one test board connected to the host.'
-             '\nConnect only the test harness and remove other boards.')
-      raise RuntimeError(msg)
-    if len(serials) < 1:
-      msg = ('No test boards were found.\n'
-             'Check boards are connected.')
-      raise RuntimeError(msg)
-
-    s = serials[0]
-    serial_dir = os.path.dirname(self.serial_path)
-    if not os.path.exists(serial_dir):
-      os.makedirs(serial_dir)
-    with open(self.serial_path, mode='w') as f:
-      f.write(s)
-      self.hla_serial = s
-
-    print('Your TH serial', s, 'has been saved as', self.serial_path)
-    return
 
 
 class DeviceUnderTest(Board):
-  """Subclass of Board representing a DUT board.
+    """Subclass of Board representing a DUT board.
 
-  Attributes:
-    th: Reference to test harness board to which this DUT is attached
-  """
-
-  def __init__(self, board, th, module, log_dir, hla_ser=None):
-    """Initializes a DUT object.
-
-    Args:
-      board: String containing board name
+    Attributes:
       th: Reference to test harness board to which this DUT is attached
-      module: module name
-      log_dir: Directory where log file is stored
-      hla_ser: Serial number if board uses an HLA adaptor
     """
-    Board.__init__(self, board, module, hla_serial=hla_ser)
-    self.th = th
-    self.log_dir = log_dir
-    self.openocd_log = os.path.join(log_dir, 'openocd_dut.log')
-    self.build_log = os.path.join(log_dir, 'build_dut.log')
-    self.reset_log_dir()
-
-  def get_serial(self):
-    """Get serial number.
 
-    Precondition: The DUT and TH must both be connected, and th.hla_serial
-    must hold the correct value (the th's serial #)
+    def __init__(self, board, th, module, log_dir, hla_ser=None):
+        """Initializes a DUT object.
+
+        Args:
+          board: String containing board name
+          th: Reference to test harness board to which this DUT is attached
+          module: module name
+          log_dir: Directory where log file is stored
+          hla_ser: Serial number if board uses an HLA adaptor
+        """
+        Board.__init__(self, board, module, hla_serial=hla_ser)
+        self.th = th
+        self.log_dir = log_dir
+        self.openocd_log = os.path.join(log_dir, "openocd_dut.log")
+        self.build_log = os.path.join(log_dir, "build_dut.log")
+        self.reset_log_dir()
+
+    def get_serial(self):
+        """Get serial number.
+
+        Precondition: The DUT and TH must both be connected, and th.hla_serial
+        must hold the correct value (the th's serial #)
+
+        Raises:
+          RuntimeError: DUT isn't found or multiple DUTs are found.
+        """
+        if self.hla_serial is not None:
+            # serial was already set ('' is a valid serial)
+            return
 
-    Raises:
-      RuntimeError: DUT isn't found or multiple DUTs are found.
-    """
-    if self.hla_serial is not None:
-      # serial was already set ('' is a valid serial)
-      return
-
-    serials = Board.get_stlink_serials()
-    dut = [s for s in serials if self.th.hla_serial != s]
-
-    # If len(dut) is 0 then your dut doesn't use an st-link device, so we
-    # don't have to worry about its serial number
-    if not dut:
-      msg = ('Failed to find serial for DUT.\n'
-             'Is ' + self.board + ' connected?')
-      raise RuntimeError(msg)
-    if len(dut) > 1:
-      msg = ('Found multiple DUTs.\n'
-             'You can connect only one DUT at a time. This may be caused by\n'
-             'an incorrect TH serial. Check if ' + self.th.serial_path + '\n'
-             'contains a correct serial.')
-      raise RuntimeError(msg)
-
-    # Found your other st-link device serial!
-    self.hla_serial = dut[0]
-    return
+        serials = Board.get_stlink_serials()
+        dut = [s for s in serials if self.th.hla_serial != s]
+
+        # If len(dut) is 0 then your dut doesn't use an st-link device, so we
+        # don't have to worry about its serial number
+        if not dut:
+            msg = (
+                "Failed to find serial for DUT.\nIs "
+                + self.board
+                + " connected?"
+            )
+            raise RuntimeError(msg)
+        if len(dut) > 1:
+            msg = (
+                "Found multiple DUTs.\n"
+                "You can connect only one DUT at a time. This may be caused by\n"
+                "an incorrect TH serial. Check if " + self.th.serial_path + "\n"
+                "contains a correct serial."
+            )
+            raise RuntimeError(msg)
+
+        # Found your other st-link device serial!
+        self.hla_serial = dut[0]
+        return
diff --git a/cts/common/cts.rc b/cts/common/cts.rc
index 264b982655..fe27b2c308 100644
--- a/cts/common/cts.rc
+++ b/cts/common/cts.rc
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/cts/common/cts_common.c b/cts/common/cts_common.c
index 8975636655..4b56456a3c 100644
--- a/cts/common/cts_common.c
+++ b/cts/common/cts_common.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,7 +11,7 @@ __attribute__((weak)) void clean_state(void)
 	/* Each test overrides as needed */
 }
 
-void cts_main_loop(const struct cts_test* tests, const char *name)
+void cts_main_loop(const struct cts_test *tests, const char *name)
 {
 	enum cts_rc rc;
 	int i;
diff --git a/cts/common/cts_common.h b/cts/common/cts_common.h
index 13a435e655..8fd9073c62 100644
--- a/cts/common/cts_common.h
+++ b/cts/common/cts_common.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,16 +10,16 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTL(format, args...) CPRINTS("%s:%d: "format, \
-					 __func__, __LINE__, ## args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTL(format, args...) \
+	CPRINTS("%s:%d: " format, __func__, __LINE__, ##args)
 
-#define READ_WAIT_TIME_MS		100
-#define CTS_INTERRUPT_TRIGGER_DELAY_US	(250 * MSEC)
+#define READ_WAIT_TIME_MS 100
+#define CTS_INTERRUPT_TRIGGER_DELAY_US (250 * MSEC)
 
 enum cts_rc {
-	#include "cts.rc"
+#include "cts.rc"
 };
 
 struct cts_test {
@@ -38,7 +38,7 @@ extern const int cts_test_count;
  * @test: List of tests to run
  * @name: Name of the test to be printed on EC console
  */
-void cts_main_loop(const struct cts_test* tests, const char *name);
+void cts_main_loop(const struct cts_test *tests, const char *name);
 
 /**
  * Callback function called at the beginning of the main loop
diff --git a/cts/common/cts_testlist.h b/cts/common/cts_testlist.h
index 1586c1348e..ee3ea58d39 100644
--- a/cts/common/cts_testlist.h
+++ b/cts/common/cts_testlist.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,7 +22,7 @@
 
 #undef CTS_TEST
 #define CTS_TEST(test, th_rc, th_string, dut_rc, dut_string) \
-	{test, STRINGIFY(test)},
+	{ test, STRINGIFY(test) },
 struct cts_test tests[] = {
 #include "cts.testlist"
 };
diff --git a/cts/common/dut_common.c b/cts/common/dut_common.c
index 6e62a280e2..aa68436d41 100644
--- a/cts/common/dut_common.c
+++ b/cts/common/dut_common.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,4 +25,3 @@ enum cts_rc sync(void)
 
 	return CTS_RC_SUCCESS;
 }
-
diff --git a/cts/common/th_common.c b/cts/common/th_common.c
index 1d692b7843..cc9c6be75f 100644
--- a/cts/common/th_common.c
+++ b/cts/common/th_common.c
@@ -1,12 +1,12 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "cts_common.h"
 #include "gpio.h"
 #include "timer.h"
 #include "watchdog.h"
-#include "cts_common.h"
 
 /* Return SUCCESS if and only if we reach end of function
  * Returning success here means sync was successful
diff --git a/cts/cts.py b/cts/cts.py
index 95a3b1c5f3..619c8858c2 100755
--- a/cts/cts.py
+++ b/cts/cts.py
@@ -1,6 +1,6 @@
 #!/usr/bin/env python
 #
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -24,416 +24,444 @@
 import os
 import shutil
 import time
+
 import common.board as board
 
 
-CTS_RC_PREFIX = 'CTS_RC_'
-DEFAULT_TH = 'stm32l476g-eval'
-DEFAULT_DUT = 'nucleo-f072rb'
+CTS_RC_PREFIX = "CTS_RC_"
+DEFAULT_TH = "stm32l476g-eval"
+DEFAULT_DUT = "nucleo-f072rb"
 MAX_SUITE_TIME_SEC = 5
-CTS_TEST_RESULT_DIR = '/tmp/ects'
+CTS_TEST_RESULT_DIR = "/tmp/ects"
 
 # Host only return codes. Make sure they match values in cts.rc
-CTS_RC_DID_NOT_START = -1          # test did not run.
-CTS_RC_DID_NOT_END = -2            # test did not run.
-CTS_RC_DUPLICATE_RUN = -3          # test was run multiple times.
-CTS_RC_INVALID_RETURN_CODE = -4    # failed to parse return code
+CTS_RC_DID_NOT_START = -1  # test did not run.
+CTS_RC_DID_NOT_END = -2  # test did not run.
+CTS_RC_DUPLICATE_RUN = -3  # test was run multiple times.
+CTS_RC_INVALID_RETURN_CODE = -4  # failed to parse return code
 
 
 class Cts(object):
-  """Class that represents a eCTS run.
-
-  Attributes:
-    dut: DeviceUnderTest object representing DUT
-    th: TestHarness object representing a test harness
-    module: Name of module to build/run tests for
-    testlist: List of strings of test names contained in given module
-    return_codes: Dict of strings of return codes, with a code's integer
-      value being the index for the corresponding string representation
-  """
-
-  def __init__(self, ec_dir, th, dut, module):
-    """Initializes cts class object with given arguments.
-
-    Args:
-      ec_dir: Path to ec directory
-      th: Name of the test harness board
-      dut: Name of the device under test board
-      module: Name of module to build/run tests for (e.g. gpio, interrupt)
-    """
-    self.results_dir = os.path.join(CTS_TEST_RESULT_DIR, dut, module)
-    if os.path.isdir(self.results_dir):
-      shutil.rmtree(self.results_dir)
-    else:
-      os.makedirs(self.results_dir)
-    self.ec_dir = ec_dir
-    self.module = module
-    serial_path = os.path.join(CTS_TEST_RESULT_DIR, 'th_serial')
-    self.th = board.TestHarness(th, module, self.results_dir, serial_path)
-    self.dut = board.DeviceUnderTest(dut, self.th, module, self.results_dir)
-    cts_dir = os.path.join(self.ec_dir, 'cts')
-    testlist_path = os.path.join(cts_dir, self.module, 'cts.testlist')
-    return_codes_path = os.path.join(cts_dir, 'common', 'cts.rc')
-    self.get_return_codes(return_codes_path)
-    self.testlist = self.get_macro_args(testlist_path, 'CTS_TEST')
-
-  def build(self):
-    """Build images for DUT and TH."""
-    print('Building DUT image...')
-    if not self.dut.build(self.ec_dir):
-      raise RuntimeError('Building module %s for DUT failed' % (self.module))
-    print('Building TH image...')
-    if not self.th.build(self.ec_dir):
-      raise RuntimeError('Building module %s for TH failed' % (self.module))
-
-  def flash_boards(self):
-    """Flashes TH and DUT with their most recently built ec.bin."""
-    cts_module = 'cts_' + self.module
-    image_path = os.path.join('build', self.th.board, cts_module, 'ec.bin')
-    self.identify_boards()
-    print('Flashing TH with', image_path)
-    if not self.th.flash(image_path):
-      raise RuntimeError('Flashing TH failed')
-    image_path = os.path.join('build', self.dut.board, cts_module, 'ec.bin')
-    print('Flashing DUT with', image_path)
-    if not self.dut.flash(image_path):
-      raise RuntimeError('Flashing DUT failed')
-
-  def setup(self):
-    """Setup boards."""
-    self.th.save_serial()
-
-  def identify_boards(self):
-    """Updates serials of TH and DUT in that order (order matters)."""
-    self.th.get_serial()
-    self.dut.get_serial()
-
-  def get_macro_args(self, filepath, macro):
-    """Get list of args of a macro in a file when macro.
-
-    Args:
-      filepath: String containing absolute path to the file
-      macro: String containing text of macro to get args of
-
-    Returns:
-      List of dictionaries where each entry is:
-        'name': Test name,
-        'th_string': Expected string from TH,
-        'dut_string': Expected string from DUT,
+    """Class that represents a eCTS run.
+
+    Attributes:
+      dut: DeviceUnderTest object representing DUT
+      th: TestHarness object representing a test harness
+      module: Name of module to build/run tests for
+      testlist: List of strings of test names contained in given module
+      return_codes: Dict of strings of return codes, with a code's integer
+        value being the index for the corresponding string representation
     """
-    tests = []
-    with open(filepath, 'r') as f:
-      lines = f.readlines()
-      joined = ''.join(lines).replace('\\\n', '').splitlines()
-      for l in joined:
-        if not l.strip().startswith(macro):
-          continue
-        d = {}
-        l = l.strip()[len(macro):]
-        l = l.strip('()').split(',')
-        d['name'] = l[0].strip()
-        d['th_rc'] = self.get_return_code_value(l[1].strip().strip('"'))
-        d['th_string'] = l[2].strip().strip('"')
-        d['dut_rc'] = self.get_return_code_value(l[3].strip().strip('"'))
-        d['dut_string'] = l[4].strip().strip('"')
-        tests.append(d)
-    return tests
-
-  def get_return_codes(self, filepath):
-    """Read return code names from the return code definition file."""
-    self.return_codes = {}
-    val = 0
-    with open(filepath, 'r') as f:
-      for line in f:
-        line = line.strip()
-        if not line.startswith(CTS_RC_PREFIX):
-          continue
-        line = line.split(',')[0]
-        if '=' in line:
-          tokens = line.split('=')
-          line = tokens[0].strip()
-          val = int(tokens[1].strip())
-        self.return_codes[line] = val
-        val += 1
-
-  def parse_output(self, output):
-    """Parse console output from DUT or TH.
-
-    Args:
-      output: String containing consoule output
-
-    Returns:
-      List of dictionaries where each key and value are:
-        name = 'ects_test_x',
-        started = True/False,
-        ended = True/False,
-        rc = CTS_RC_*,
-        output = All text between 'ects_test_x start' and 'ects_test_x end'
-    """
-    results = []
-    i = 0
-    for test in self.testlist:
-      results.append({})
-      results[i]['name'] = test['name']
-      results[i]['started'] = False
-      results[i]['rc'] = CTS_RC_DID_NOT_START
-      results[i]['string'] = False
-      results[i]['output'] = []
-      i += 1
-
-    i = 0
-    for ln in [ln.strip() for ln in output.split('\n')]:
-      if i + 1 > len(results):
-        break
-      tokens = ln.split()
-      if len(tokens) >= 2:
-        if tokens[0].strip() == results[i]['name']:
-          if tokens[1].strip() == 'start':
-            # start line found
-            if results[i]['started']:   # Already started
-              results[i]['rc'] = CTS_RC_DUPLICATE_RUN
-            else:
-              results[i]['rc'] = CTS_RC_DID_NOT_END
-              results[i]['started'] = True
-            continue
-          elif results[i]['started'] and tokens[1].strip() == 'end':
-            # end line found
-            results[i]['rc'] = CTS_RC_INVALID_RETURN_CODE
-            if len(tokens) == 3:
-              try:
-                results[i]['rc'] = int(tokens[2].strip())
-              except ValueError:
-                pass
-            # Since index is incremented when 'end' is encountered, we don't
-            # need to check duplicate 'end'.
-            i += 1
-            continue
-      if results[i]['started']:
-        results[i]['output'].append(ln)
-
-    return results
-
-  def get_return_code_name(self, code, strip_prefix=False):
-    name = ''
-    for k, v in self.return_codes.items():
-      if v == code:
-        if strip_prefix:
-          name = k[len(CTS_RC_PREFIX):]
-        else:
-          name = k
-    return name
-
-  def get_return_code_value(self, name):
-    if name:
-      return self.return_codes[name]
-    return  0
-
-  def evaluate_run(self, dut_output, th_output):
-    """Parse outputs to derive test results.
-
-    Args:
-      dut_output: String output of DUT
-      th_output: String output of TH
 
-    Returns:
-      th_results: list of test results for TH
-      dut_results: list of test results for DUT
-    """
-    th_results = self.parse_output(th_output)
-    dut_results = self.parse_output(dut_output)
-
-    # Search for expected string in each output
-    for i, v in enumerate(self.testlist):
-      if v['th_string'] in th_results[i]['output'] or not v['th_string']:
-        th_results[i]['string'] = True
-      if v['dut_string'] in dut_results[i]['output'] or not v['dut_string']:
-        dut_results[i]['string'] = True
+    def __init__(self, ec_dir, th, dut, module):
+        """Initializes cts class object with given arguments.
+
+        Args:
+          ec_dir: Path to ec directory
+          th: Name of the test harness board
+          dut: Name of the device under test board
+          module: Name of module to build/run tests for (e.g. gpio, interrupt)
+        """
+        self.results_dir = os.path.join(CTS_TEST_RESULT_DIR, dut, module)
+        if os.path.isdir(self.results_dir):
+            shutil.rmtree(self.results_dir)
+        else:
+            os.makedirs(self.results_dir)
+        self.ec_dir = ec_dir
+        self.module = module
+        serial_path = os.path.join(CTS_TEST_RESULT_DIR, "th_serial")
+        self.th = board.TestHarness(th, module, self.results_dir, serial_path)
+        self.dut = board.DeviceUnderTest(dut, self.th, module, self.results_dir)
+        cts_dir = os.path.join(self.ec_dir, "cts")
+        testlist_path = os.path.join(cts_dir, self.module, "cts.testlist")
+        return_codes_path = os.path.join(cts_dir, "common", "cts.rc")
+        self.get_return_codes(return_codes_path)
+        self.testlist = self.get_macro_args(testlist_path, "CTS_TEST")
+
+    def build(self):
+        """Build images for DUT and TH."""
+        print("Building DUT image...")
+        if not self.dut.build(self.ec_dir):
+            raise RuntimeError(
+                "Building module %s for DUT failed" % (self.module)
+            )
+        print("Building TH image...")
+        if not self.th.build(self.ec_dir):
+            raise RuntimeError(
+                "Building module %s for TH failed" % (self.module)
+            )
+
+    def flash_boards(self):
+        """Flashes TH and DUT with their most recently built ec.bin."""
+        cts_module = "cts_" + self.module
+        image_path = os.path.join("build", self.th.board, cts_module, "ec.bin")
+        self.identify_boards()
+        print("Flashing TH with", image_path)
+        if not self.th.flash(image_path):
+            raise RuntimeError("Flashing TH failed")
+        image_path = os.path.join("build", self.dut.board, cts_module, "ec.bin")
+        print("Flashing DUT with", image_path)
+        if not self.dut.flash(image_path):
+            raise RuntimeError("Flashing DUT failed")
+
+    def setup(self):
+        """Setup boards."""
+        self.th.save_serial()
+
+    def identify_boards(self):
+        """Updates serials of TH and DUT in that order (order matters)."""
+        self.th.get_serial()
+        self.dut.get_serial()
+
+    def get_macro_args(self, filepath, macro):
+        """Get list of args of a macro in a file when macro.
+
+        Args:
+          filepath: String containing absolute path to the file
+          macro: String containing text of macro to get args of
+
+        Returns:
+          List of dictionaries where each entry is:
+            'name': Test name,
+            'th_string': Expected string from TH,
+            'dut_string': Expected string from DUT,
+        """
+        tests = []
+        with open(filepath, "r") as f:
+            lines = f.readlines()
+            joined = "".join(lines).replace("\\\n", "").splitlines()
+            for l in joined:
+                if not l.strip().startswith(macro):
+                    continue
+                d = {}
+                l = l.strip()[len(macro) :]
+                l = l.strip("()").split(",")
+                d["name"] = l[0].strip()
+                d["th_rc"] = self.get_return_code_value(l[1].strip().strip('"'))
+                d["th_string"] = l[2].strip().strip('"')
+                d["dut_rc"] = self.get_return_code_value(
+                    l[3].strip().strip('"')
+                )
+                d["dut_string"] = l[4].strip().strip('"')
+                tests.append(d)
+        return tests
+
+    def get_return_codes(self, filepath):
+        """Read return code names from the return code definition file."""
+        self.return_codes = {}
+        val = 0
+        with open(filepath, "r") as f:
+            for line in f:
+                line = line.strip()
+                if not line.startswith(CTS_RC_PREFIX):
+                    continue
+                line = line.split(",")[0]
+                if "=" in line:
+                    tokens = line.split("=")
+                    line = tokens[0].strip()
+                    val = int(tokens[1].strip())
+                self.return_codes[line] = val
+                val += 1
+
+    def parse_output(self, output):
+        """Parse console output from DUT or TH.
+
+        Args:
+          output: String containing consoule output
+
+        Returns:
+          List of dictionaries where each key and value are:
+            name = 'ects_test_x',
+            started = True/False,
+            ended = True/False,
+            rc = CTS_RC_*,
+            output = All text between 'ects_test_x start' and 'ects_test_x end'
+        """
+        results = []
+        i = 0
+        for test in self.testlist:
+            results.append({})
+            results[i]["name"] = test["name"]
+            results[i]["started"] = False
+            results[i]["rc"] = CTS_RC_DID_NOT_START
+            results[i]["string"] = False
+            results[i]["output"] = []
+            i += 1
 
-    return th_results, dut_results
+        i = 0
+        for ln in [ln.strip() for ln in output.split("\n")]:
+            if i + 1 > len(results):
+                break
+            tokens = ln.split()
+            if len(tokens) >= 2:
+                if tokens[0].strip() == results[i]["name"]:
+                    if tokens[1].strip() == "start":
+                        # start line found
+                        if results[i]["started"]:  # Already started
+                            results[i]["rc"] = CTS_RC_DUPLICATE_RUN
+                        else:
+                            results[i]["rc"] = CTS_RC_DID_NOT_END
+                            results[i]["started"] = True
+                        continue
+                    elif results[i]["started"] and tokens[1].strip() == "end":
+                        # end line found
+                        results[i]["rc"] = CTS_RC_INVALID_RETURN_CODE
+                        if len(tokens) == 3:
+                            try:
+                                results[i]["rc"] = int(tokens[2].strip())
+                            except ValueError:
+                                pass
+                        # Since index is incremented when 'end' is encountered, we don't
+                        # need to check duplicate 'end'.
+                        i += 1
+                        continue
+            if results[i]["started"]:
+                results[i]["output"].append(ln)
+
+        return results
+
+    def get_return_code_name(self, code, strip_prefix=False):
+        name = ""
+        for k, v in self.return_codes.items():
+            if v == code:
+                if strip_prefix:
+                    name = k[len(CTS_RC_PREFIX) :]
+                else:
+                    name = k
+        return name
+
+    def get_return_code_value(self, name):
+        if name:
+            return self.return_codes[name]
+        return 0
+
+    def evaluate_run(self, dut_output, th_output):
+        """Parse outputs to derive test results.
+
+        Args:
+          dut_output: String output of DUT
+          th_output: String output of TH
+
+        Returns:
+          th_results: list of test results for TH
+          dut_results: list of test results for DUT
+        """
+        th_results = self.parse_output(th_output)
+        dut_results = self.parse_output(dut_output)
+
+        # Search for expected string in each output
+        for i, v in enumerate(self.testlist):
+            if v["th_string"] in th_results[i]["output"] or not v["th_string"]:
+                th_results[i]["string"] = True
+            if (
+                v["dut_string"] in dut_results[i]["output"]
+                or not v["dut_string"]
+            ):
+                dut_results[i]["string"] = True
+
+        return th_results, dut_results
+
+    def print_result(self, th_results, dut_results):
+        """Print results to the screen.
+
+        Args:
+          th_results: list of test results for TH
+          dut_results: list of test results for DUT
+        """
+        len_test_name = max(len(s["name"]) for s in self.testlist)
+        len_code_name = max(
+            len(self.get_return_code_name(v, True))
+            for v in self.return_codes.values()
+        )
+
+        head = "{:^" + str(len_test_name) + "} "
+        head += "{:^" + str(len_code_name) + "} "
+        head += "{:^" + str(len_code_name) + "}"
+        head += "{:^" + str(len(" TH_STR")) + "}"
+        head += "{:^" + str(len(" DUT_STR")) + "}"
+        head += "{:^" + str(len(" RESULT")) + "}\n"
+        fmt = "{:" + str(len_test_name) + "} "
+        fmt += "{:>" + str(len_code_name) + "} "
+        fmt += "{:>" + str(len_code_name) + "}"
+        fmt += "{:>" + str(len(" TH_STR")) + "}"
+        fmt += "{:>" + str(len(" DUT_STR")) + "}"
+        fmt += "{:>" + str(len(" RESULT")) + "}\n"
+
+        self.formatted_results = head.format(
+            "TEST NAME", "TH_RC", "DUT_RC", " TH_STR", " DUT_STR", " RESULT"
+        )
+        for i, d in enumerate(dut_results):
+            th_cn = self.get_return_code_name(th_results[i]["rc"], True)
+            dut_cn = self.get_return_code_name(dut_results[i]["rc"], True)
+            th_res = self.evaluate_result(
+                th_results[i],
+                self.testlist[i]["th_rc"],
+                self.testlist[i]["th_string"],
+            )
+            dut_res = self.evaluate_result(
+                dut_results[i],
+                self.testlist[i]["dut_rc"],
+                self.testlist[i]["dut_string"],
+            )
+            self.formatted_results += fmt.format(
+                d["name"],
+                th_cn,
+                dut_cn,
+                "YES" if th_results[i]["string"] else "NO",
+                "YES" if dut_results[i]["string"] else "NO",
+                "PASS" if th_res and dut_res else "FAIL",
+            )
+
+    def evaluate_result(self, result, expected_rc, expected_string):
+        if result["rc"] != expected_rc:
+            return False
+        if expected_string and expected_string not in result["output"]:
+            return False
+        return True
+
+    def run(self):
+        """Resets boards, records test results in results dir."""
+        print("Reading serials...")
+        self.identify_boards()
+        print("Opening DUT tty...")
+        self.dut.setup_tty()
+        print("Opening TH tty...")
+        self.th.setup_tty()
+
+        # Boards might be still writing to tty. Wait a few seconds before flashing.
+        time.sleep(3)
+
+        # clear buffers
+        print("Clearing DUT tty...")
+        self.dut.read_tty()
+        print("Clearing TH tty...")
+        self.th.read_tty()
+
+        # Resets the boards and allows them to run tests
+        # Due to current (7/27/16) version of sync function,
+        # both boards must be rest and halted, with the th
+        # resuming first, in order for the test suite to run in sync
+        print("Halting TH...")
+        if not self.th.reset_halt():
+            raise RuntimeError("Failed to halt TH")
+        print("Halting DUT...")
+        if not self.dut.reset_halt():
+            raise RuntimeError("Failed to halt DUT")
+        print("Resuming TH...")
+        if not self.th.resume():
+            raise RuntimeError("Failed to resume TH")
+        print("Resuming DUT...")
+        if not self.dut.resume():
+            raise RuntimeError("Failed to resume DUT")
+
+        time.sleep(MAX_SUITE_TIME_SEC)
+
+        print("Reading DUT tty...")
+        dut_output, _ = self.dut.read_tty()
+        self.dut.close_tty()
+        print("Reading TH tty...")
+        th_output, _ = self.th.read_tty()
+        self.th.close_tty()
+
+        print("Halting TH...")
+        if not self.th.reset_halt():
+            raise RuntimeError("Failed to halt TH")
+        print("Halting DUT...")
+        if not self.dut.reset_halt():
+            raise RuntimeError("Failed to halt DUT")
+
+        if not dut_output or not th_output:
+            raise ValueError(
+                "Output missing from boards. If you have a process "
+                "reading ttyACMx, please kill that process and try "
+                "again."
+            )
+
+            print("Pursing results...")
+        th_results, dut_results = self.evaluate_run(dut_output, th_output)
+
+        # Print out results
+        self.print_result(th_results, dut_results)
+
+        # Write results
+        dest = os.path.join(self.results_dir, "results.log")
+        with open(dest, "w") as fl:
+            fl.write(self.formatted_results)
+
+        # Write UART outputs
+        dest = os.path.join(self.results_dir, "uart_th.log")
+        with open(dest, "w") as fl:
+            fl.write(th_output)
+        dest = os.path.join(self.results_dir, "uart_dut.log")
+        with open(dest, "w") as fl:
+            fl.write(dut_output)
+
+        print(self.formatted_results)
+
+        # TODO(chromium:735652): Should set exit code for the shell
 
-  def print_result(self, th_results, dut_results):
-    """Print results to the screen.
 
-    Args:
-      th_results: list of test results for TH
-      dut_results: list of test results for DUT
-    """
-    len_test_name = max(len(s['name']) for s in self.testlist)
-    len_code_name = max(len(self.get_return_code_name(v, True))
-                        for v in self.return_codes.values())
-
-    head = '{:^' + str(len_test_name) + '} '
-    head += '{:^' + str(len_code_name) + '} '
-    head += '{:^' + str(len_code_name) + '}'
-    head += '{:^' + str(len(' TH_STR')) + '}'
-    head += '{:^' + str(len(' DUT_STR')) + '}'
-    head += '{:^' + str(len(' RESULT')) + '}\n'
-    fmt = '{:' + str(len_test_name) + '} '
-    fmt += '{:>' + str(len_code_name) + '} '
-    fmt += '{:>' + str(len_code_name) + '}'
-    fmt += '{:>' + str(len(' TH_STR')) + '}'
-    fmt += '{:>' + str(len(' DUT_STR')) + '}'
-    fmt += '{:>' + str(len(' RESULT')) + '}\n'
-
-    self.formatted_results = head.format(
-        'TEST NAME', 'TH_RC', 'DUT_RC',
-        ' TH_STR', ' DUT_STR', ' RESULT')
-    for i, d in enumerate(dut_results):
-      th_cn = self.get_return_code_name(th_results[i]['rc'], True)
-      dut_cn = self.get_return_code_name(dut_results[i]['rc'], True)
-      th_res = self.evaluate_result(th_results[i],
-                                    self.testlist[i]['th_rc'],
-                                    self.testlist[i]['th_string'])
-      dut_res = self.evaluate_result(dut_results[i],
-                                     self.testlist[i]['dut_rc'],
-                                     self.testlist[i]['dut_string'])
-      self.formatted_results += fmt.format(
-          d['name'], th_cn, dut_cn,
-          'YES' if th_results[i]['string'] else 'NO',
-          'YES' if dut_results[i]['string'] else 'NO',
-          'PASS' if th_res and dut_res else 'FAIL')
-
-  def evaluate_result(self, result, expected_rc, expected_string):
-    if result['rc'] != expected_rc:
-      return False
-    if expected_string and expected_string not in result['output']:
-      return False
-    return True
-
-  def run(self):
-    """Resets boards, records test results in results dir."""
-    print('Reading serials...')
-    self.identify_boards()
-    print('Opening DUT tty...')
-    self.dut.setup_tty()
-    print('Opening TH tty...')
-    self.th.setup_tty()
-
-    # Boards might be still writing to tty. Wait a few seconds before flashing.
-    time.sleep(3)
-
-    # clear buffers
-    print('Clearing DUT tty...')
-    self.dut.read_tty()
-    print('Clearing TH tty...')
-    self.th.read_tty()
-
-    # Resets the boards and allows them to run tests
-    # Due to current (7/27/16) version of sync function,
-    # both boards must be rest and halted, with the th
-    # resuming first, in order for the test suite to run in sync
-    print('Halting TH...')
-    if not self.th.reset_halt():
-      raise RuntimeError('Failed to halt TH')
-    print('Halting DUT...')
-    if not self.dut.reset_halt():
-      raise RuntimeError('Failed to halt DUT')
-    print('Resuming TH...')
-    if not self.th.resume():
-      raise RuntimeError('Failed to resume TH')
-    print('Resuming DUT...')
-    if not self.dut.resume():
-      raise RuntimeError('Failed to resume DUT')
-
-    time.sleep(MAX_SUITE_TIME_SEC)
-
-    print('Reading DUT tty...')
-    dut_output, _ = self.dut.read_tty()
-    self.dut.close_tty()
-    print('Reading TH tty...')
-    th_output, _ = self.th.read_tty()
-    self.th.close_tty()
-
-    print('Halting TH...')
-    if not self.th.reset_halt():
-      raise RuntimeError('Failed to halt TH')
-    print('Halting DUT...')
-    if not self.dut.reset_halt():
-      raise RuntimeError('Failed to halt DUT')
-
-    if not dut_output or not th_output:
-      raise ValueError('Output missing from boards. If you have a process '
-                       'reading ttyACMx, please kill that process and try '
-                       'again.')
-
-      print('Pursing results...')
-    th_results, dut_results = self.evaluate_run(dut_output, th_output)
-
-    # Print out results
-    self.print_result(th_results, dut_results)
-
-    # Write results
-    dest = os.path.join(self.results_dir, 'results.log')
-    with open(dest, 'w') as fl:
-      fl.write(self.formatted_results)
-
-    # Write UART outputs
-    dest = os.path.join(self.results_dir, 'uart_th.log')
-    with open(dest, 'w') as fl:
-      fl.write(th_output)
-    dest = os.path.join(self.results_dir, 'uart_dut.log')
-    with open(dest, 'w') as fl:
-      fl.write(dut_output)
-
-    print(self.formatted_results)
-
-    # TODO(chromium:735652): Should set exit code for the shell
+def main():
+    ec_dir = os.path.realpath(
+        os.path.join(os.path.dirname(os.path.abspath(__file__)), "..")
+    )
+    os.chdir(ec_dir)
+
+    dut = DEFAULT_DUT
+    module = "meta"
+
+    parser = argparse.ArgumentParser(description="Used to build/flash boards")
+    parser.add_argument(
+        "-d", "--dut", help="Specify DUT you want to build/flash"
+    )
+    parser.add_argument(
+        "-m", "--module", help="Specify module you want to build/flash"
+    )
+    parser.add_argument(
+        "-s",
+        "--setup",
+        action="store_true",
+        help="Connect only the TH to save its serial",
+    )
+    parser.add_argument(
+        "-b",
+        "--build",
+        action="store_true",
+        help="Build test suite (no flashing)",
+    )
+    parser.add_argument(
+        "-f",
+        "--flash",
+        action="store_true",
+        help="Flash boards with most recent images",
+    )
+    parser.add_argument(
+        "-r", "--run", action="store_true", help="Run tests without flashing"
+    )
+
+    args = parser.parse_args()
+
+    if args.module:
+        module = args.module
+
+    if args.dut:
+        dut = args.dut
+
+    cts = Cts(ec_dir, DEFAULT_TH, dut=dut, module=module)
+
+    if args.setup:
+        cts.setup()
+    elif args.build:
+        cts.build()
+    elif args.flash:
+        cts.flash_boards()
+    elif args.run:
+        cts.run()
+    else:
+        cts.build()
+        cts.flash_boards()
+        cts.run()
 
 
-def main():
-  ec_dir = os.path.realpath(os.path.join(
-      os.path.dirname(os.path.abspath(__file__)), '..'))
-  os.chdir(ec_dir)
-
-  dut = DEFAULT_DUT
-  module = 'meta'
-
-  parser = argparse.ArgumentParser(description='Used to build/flash boards')
-  parser.add_argument('-d',
-                      '--dut',
-                      help='Specify DUT you want to build/flash')
-  parser.add_argument('-m',
-                      '--module',
-                      help='Specify module you want to build/flash')
-  parser.add_argument('-s',
-                      '--setup',
-                      action='store_true',
-                      help='Connect only the TH to save its serial')
-  parser.add_argument('-b',
-                      '--build',
-                      action='store_true',
-                      help='Build test suite (no flashing)')
-  parser.add_argument('-f',
-                      '--flash',
-                      action='store_true',
-                      help='Flash boards with most recent images')
-  parser.add_argument('-r',
-                      '--run',
-                      action='store_true',
-                      help='Run tests without flashing')
-
-  args = parser.parse_args()
-
-  if args.module:
-    module = args.module
-
-  if args.dut:
-    dut = args.dut
-
-  cts = Cts(ec_dir, DEFAULT_TH, dut=dut, module=module)
-
-  if args.setup:
-    cts.setup()
-  elif args.build:
-    cts.build()
-  elif args.flash:
-    cts.flash_boards()
-  elif args.run:
-    cts.run()
-  else:
-    cts.build()
-    cts.flash_boards()
-    cts.run()
-
-if __name__ == '__main__':
-  main()
+if __name__ == "__main__":
+    main()
diff --git a/cts/cts.tasklist b/cts/cts.tasklist
index 152b0d02b2..40dfb21e10 100644
--- a/cts/cts.tasklist
+++ b/cts/cts.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/cts/gpio/cts.testlist b/cts/gpio/cts.testlist
index 113d2b405f..a5b7482675 100644
--- a/cts/gpio/cts.testlist
+++ b/cts/gpio/cts.testlist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/cts/gpio/dut.c b/cts/gpio/dut.c
index 828996db8e..ef609cf4a8 100644
--- a/cts/gpio/dut.c
+++ b/cts/gpio/dut.c
@@ -1,15 +1,15 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "common.h"
-#include "watchdog.h"
-#include "uart.h"
+#include "cts_common.h"
+#include "gpio.h"
 #include "task.h"
 #include "timer.h"
+#include "uart.h"
 #include "watchdog.h"
-#include "cts_common.h"
 
 enum cts_rc sync_test(void)
 {
@@ -20,7 +20,7 @@ enum cts_rc set_high_test(void)
 {
 	gpio_set_flags(GPIO_OUTPUT_TEST, GPIO_ODR_LOW);
 	gpio_set_level(GPIO_OUTPUT_TEST, 1);
-	msleep(READ_WAIT_TIME_MS*2);
+	msleep(READ_WAIT_TIME_MS * 2);
 	return CTS_RC_SUCCESS;
 }
 
@@ -28,7 +28,7 @@ enum cts_rc set_low_test(void)
 {
 	gpio_set_flags(GPIO_OUTPUT_TEST, GPIO_ODR_LOW);
 	gpio_set_level(GPIO_OUTPUT_TEST, 0);
-	msleep(READ_WAIT_TIME_MS*2);
+	msleep(READ_WAIT_TIME_MS * 2);
 	return CTS_RC_SUCCESS;
 }
 
diff --git a/cts/gpio/th.c b/cts/gpio/th.c
index 6c628b0ad5..54a083cef9 100644
--- a/cts/gpio/th.c
+++ b/cts/gpio/th.c
@@ -1,15 +1,15 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "common.h"
-#include "watchdog.h"
-#include "uart.h"
+#include "cts_common.h"
+#include "gpio.h"
 #include "task.h"
 #include "timer.h"
+#include "uart.h"
 #include "watchdog.h"
-#include "cts_common.h"
 
 enum cts_rc sync_test(void)
 {
@@ -46,7 +46,7 @@ enum cts_rc read_high_test(void)
 {
 	gpio_set_flags(GPIO_OUTPUT_TEST, GPIO_ODR_LOW);
 	gpio_set_level(GPIO_OUTPUT_TEST, 1);
-	msleep(READ_WAIT_TIME_MS*2);
+	msleep(READ_WAIT_TIME_MS * 2);
 	return CTS_RC_SUCCESS;
 }
 
@@ -54,14 +54,14 @@ enum cts_rc read_low_test(void)
 {
 	gpio_set_flags(GPIO_OUTPUT_TEST, GPIO_ODR_LOW);
 	gpio_set_level(GPIO_OUTPUT_TEST, 0);
-	msleep(READ_WAIT_TIME_MS*2);
+	msleep(READ_WAIT_TIME_MS * 2);
 	return CTS_RC_SUCCESS;
 }
 
 enum cts_rc od_read_high_test(void)
 {
 	gpio_set_flags(GPIO_INPUT_TEST, GPIO_OUTPUT | GPIO_ODR_LOW);
-	msleep(READ_WAIT_TIME_MS*2);
+	msleep(READ_WAIT_TIME_MS * 2);
 	return CTS_RC_SUCCESS;
 }
 
diff --git a/cts/hook/cts.testlist b/cts/hook/cts.testlist
index 97b25575d4..75e1a11324 100644
--- a/cts/hook/cts.testlist
+++ b/cts/hook/cts.testlist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/cts/hook/dut.c b/cts/hook/dut.c
index f3a52ddaf4..fc6187cade 100644
--- a/cts/hook/dut.c
+++ b/cts/hook/dut.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -88,8 +88,7 @@ static enum cts_rc test_ticks(void)
 	msleep(1300);
 
 	interval = tick_time[1].val - tick_time[0].val;
-	error_pct = (interval - HOOK_TICK_INTERVAL) * 100 /
-		    HOOK_TICK_INTERVAL;
+	error_pct = (interval - HOOK_TICK_INTERVAL) * 100 / HOOK_TICK_INTERVAL;
 	if (error_pct < -10 || 10 < error_pct) {
 		CPRINTS("tick error=%d%% interval=%lld", error_pct, interval);
 		return CTS_RC_FAILURE;
@@ -142,8 +141,8 @@ static enum cts_rc test_deferred(void)
 
 	/* Invalid deferred function */
 	deferred_call_count = 0;
-	if (hook_call_deferred(&invalid_deferred_func_data, 50 * MSEC)
-			== EC_SUCCESS) {
+	if (hook_call_deferred(&invalid_deferred_func_data, 50 * MSEC) ==
+	    EC_SUCCESS) {
 		CPRINTL("non_deferred_func_data");
 		return CTS_RC_FAILURE;
 	}
diff --git a/cts/hook/th.c b/cts/hook/th.c
deleted file mode 120000
index 41eab28462..0000000000
--- a/cts/hook/th.c
+++ /dev/null
@@ -1 +0,0 @@
-dut.c
\ No newline at end of file
diff --git a/cts/hook/th.c b/cts/hook/th.c
new file mode 100644
index 0000000000..fc6187cade
--- /dev/null
+++ b/cts/hook/th.c
@@ -0,0 +1,164 @@
+/* Copyright 2013 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Test hooks.
+ */
+
+#include "common.h"
+#include "console.h"
+#include "cts_common.h"
+#include "hooks.h"
+#include "task.h"
+#include "timer.h"
+#include "util.h"
+#include "watchdog.h"
+
+static int init_hook_count;
+static int tick_hook_count;
+static int tick2_hook_count;
+static int tick_count_seen_by_tick2;
+static timestamp_t tick_time[2];
+static int second_hook_count;
+static timestamp_t second_time[2];
+static int deferred_call_count;
+
+static void init_hook(void)
+{
+	init_hook_count++;
+}
+DECLARE_HOOK(HOOK_INIT, init_hook, HOOK_PRIO_DEFAULT);
+
+static void tick_hook(void)
+{
+	tick_hook_count++;
+	tick_time[0] = tick_time[1];
+	tick_time[1] = get_time();
+}
+DECLARE_HOOK(HOOK_TICK, tick_hook, HOOK_PRIO_DEFAULT);
+
+static void tick2_hook(void)
+{
+	tick2_hook_count++;
+	tick_count_seen_by_tick2 = tick_hook_count;
+}
+/* tick2_hook() prio means it should be called after tick_hook() */
+DECLARE_HOOK(HOOK_TICK, tick2_hook, HOOK_PRIO_DEFAULT + 1);
+
+static void second_hook(void)
+{
+	second_hook_count++;
+	second_time[0] = second_time[1];
+	second_time[1] = get_time();
+}
+DECLARE_HOOK(HOOK_SECOND, second_hook, HOOK_PRIO_DEFAULT);
+
+static void deferred_func(void)
+{
+	deferred_call_count++;
+}
+DECLARE_DEFERRED(deferred_func);
+
+static void invalid_deferred_func(void)
+{
+	deferred_call_count++;
+}
+
+static const struct deferred_data invalid_deferred_func_data = {
+	invalid_deferred_func
+};
+
+static enum cts_rc test_init_hook(void)
+{
+	if (init_hook_count != 1)
+		return CTS_RC_FAILURE;
+	return CTS_RC_SUCCESS;
+}
+
+static enum cts_rc test_ticks(void)
+{
+	int64_t interval;
+	int error_pct;
+
+	/*
+	 * HOOK_SECOND must have been fired at least once when HOOK
+	 * task starts. We only need to wait for just more than a second
+	 * to allow it fires for the second time.
+	 */
+	msleep(1300);
+
+	interval = tick_time[1].val - tick_time[0].val;
+	error_pct = (interval - HOOK_TICK_INTERVAL) * 100 / HOOK_TICK_INTERVAL;
+	if (error_pct < -10 || 10 < error_pct) {
+		CPRINTS("tick error=%d%% interval=%lld", error_pct, interval);
+		return CTS_RC_FAILURE;
+	}
+
+	interval = second_time[1].val - second_time[0].val;
+	error_pct = (interval - SECOND) * 100 / SECOND;
+	if (error_pct < -10 || 10 < error_pct) {
+		CPRINTS("second error=%d%% interval=%lld", error_pct, interval);
+		return CTS_RC_FAILURE;
+	}
+
+	return CTS_RC_SUCCESS;
+}
+
+static enum cts_rc test_priority(void)
+{
+	usleep(HOOK_TICK_INTERVAL);
+	if (tick_hook_count != tick2_hook_count)
+		return CTS_RC_FAILURE;
+	if (tick_hook_count != tick_count_seen_by_tick2)
+		return CTS_RC_FAILURE;
+	return CTS_RC_SUCCESS;
+}
+
+static enum cts_rc test_deferred(void)
+{
+	deferred_call_count = 0;
+	hook_call_deferred(&deferred_func_data, 50 * MSEC);
+	if (deferred_call_count != 0) {
+		CPRINTL("deferred_call_count=%d", deferred_call_count);
+		return CTS_RC_FAILURE;
+	}
+	msleep(100);
+	if (deferred_call_count != 1) {
+		CPRINTL("deferred_call_count=%d", deferred_call_count);
+		return CTS_RC_FAILURE;
+	}
+
+	/* Test cancellation */
+	deferred_call_count = 0;
+	hook_call_deferred(&deferred_func_data, 50 * MSEC);
+	msleep(25);
+	hook_call_deferred(&deferred_func_data, -1);
+	msleep(75);
+	if (deferred_call_count != 0) {
+		CPRINTL("deferred_call_count=%d", deferred_call_count);
+		return CTS_RC_FAILURE;
+	}
+
+	/* Invalid deferred function */
+	deferred_call_count = 0;
+	if (hook_call_deferred(&invalid_deferred_func_data, 50 * MSEC) ==
+	    EC_SUCCESS) {
+		CPRINTL("non_deferred_func_data");
+		return CTS_RC_FAILURE;
+	}
+	msleep(100);
+	if (deferred_call_count != 0) {
+		CPRINTL("deferred_call_count=%d", deferred_call_count);
+		return CTS_RC_FAILURE;
+	}
+
+	return CTS_RC_SUCCESS;
+}
+
+#include "cts_testlist.h"
+
+void cts_task(void)
+{
+	cts_main_loop(tests, "Hook");
+	task_wait_event(-1);
+}
diff --git a/cts/i2c/cts.testlist b/cts/i2c/cts.testlist
index 7b6461e84d..b52e247680 100644
--- a/cts/i2c/cts.testlist
+++ b/cts/i2c/cts.testlist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/cts/i2c/cts_i2c.h b/cts/i2c/cts_i2c.h
index 2914d92a99..ae4aab9878 100644
--- a/cts/i2c/cts_i2c.h
+++ b/cts/i2c/cts_i2c.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,9 +12,9 @@ enum cts_i2c_packets {
 	READ32_OFF,
 };
 
-#define WRITE8_DATA	0x42
-#define WRITE16_DATA	0x1234
-#define WRITE32_DATA	0xDEADBEEF
-#define READ8_DATA	0x23
-#define READ16_DATA	0xACED
-#define READ32_DATA	0x01ABCDEF
+#define WRITE8_DATA 0x42
+#define WRITE16_DATA 0x1234
+#define WRITE32_DATA 0xDEADBEEF
+#define READ8_DATA 0x23
+#define READ16_DATA 0xACED
+#define READ32_DATA 0x01ABCDEF
diff --git a/cts/i2c/dut.c b/cts/i2c/dut.c
index c7a3f9fccf..d2d721fdd6 100644
--- a/cts/i2c/dut.c
+++ b/cts/i2c/dut.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,24 +17,24 @@
 
 enum cts_rc write8_test(void)
 {
-	if (i2c_write8(i2c_ports[0].port, TH_ADDR_FLAGS,
-		       WRITE8_OFF, WRITE8_DATA))
+	if (i2c_write8(i2c_ports[0].port, TH_ADDR_FLAGS, WRITE8_OFF,
+		       WRITE8_DATA))
 		return CTS_RC_FAILURE;
 	return CTS_RC_SUCCESS;
 }
 
 enum cts_rc write16_test(void)
 {
-	if (i2c_write16(i2c_ports[0].port, TH_ADDR_FLAGS,
-			WRITE16_OFF, WRITE16_DATA))
+	if (i2c_write16(i2c_ports[0].port, TH_ADDR_FLAGS, WRITE16_OFF,
+			WRITE16_DATA))
 		return CTS_RC_FAILURE;
 	return CTS_RC_SUCCESS;
 }
 
 enum cts_rc write32_test(void)
 {
-	if (i2c_write32(i2c_ports[0].port, TH_ADDR_FLAGS,
-			WRITE32_OFF, WRITE32_DATA))
+	if (i2c_write32(i2c_ports[0].port, TH_ADDR_FLAGS, WRITE32_OFF,
+			WRITE32_DATA))
 		return CTS_RC_FAILURE;
 	return CTS_RC_SUCCESS;
 }
@@ -43,8 +43,7 @@ enum cts_rc read8_test(void)
 {
 	int data;
 
-	if (i2c_read8(i2c_ports[0].port, TH_ADDR_FLAGS,
-		      READ8_OFF, &data))
+	if (i2c_read8(i2c_ports[0].port, TH_ADDR_FLAGS, READ8_OFF, &data))
 		return CTS_RC_FAILURE;
 	if (data != READ8_DATA) {
 		CPRINTL("Expecting 0x%x but read 0x%x", READ8_DATA, data);
@@ -58,8 +57,7 @@ enum cts_rc read16_test(void)
 {
 	int data;
 
-	if (i2c_read16(i2c_ports[0].port, TH_ADDR_FLAGS,
-		       READ16_OFF, &data))
+	if (i2c_read16(i2c_ports[0].port, TH_ADDR_FLAGS, READ16_OFF, &data))
 		return CTS_RC_FAILURE;
 	if (data != READ16_DATA) {
 		CPRINTL("Expecting 0x%x but read 0x%x", READ16_DATA, data);
@@ -73,8 +71,7 @@ enum cts_rc read32_test(void)
 {
 	int data;
 
-	if (i2c_read32(i2c_ports[0].port, TH_ADDR_FLAGS,
-		       READ32_OFF, &data))
+	if (i2c_read32(i2c_ports[0].port, TH_ADDR_FLAGS, READ32_OFF, &data))
 		return CTS_RC_FAILURE;
 	if (data != READ32_DATA) {
 		CPRINTL("Read 0x%x expecting 0x%x", data, READ32_DATA);
@@ -84,7 +81,6 @@ enum cts_rc read32_test(void)
 	return CTS_RC_SUCCESS;
 }
 
-
 #include "cts_testlist.h"
 
 void cts_task(void)
diff --git a/cts/i2c/th.c b/cts/i2c/th.c
index 78035cb1b2..b613f2d25d 100644
--- a/cts/i2c/th.c
+++ b/cts/i2c/th.c
@@ -1,9 +1,8 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <string.h>
 #include "common.h"
 #include "cts_common.h"
 #include "cts_i2c.h"
@@ -14,6 +13,8 @@
 #include "uart.h"
 #include "watchdog.h"
 
+#include <string.h>
+
 static uint8_t inbox[I2C_MAX_HOST_PACKET_SIZE + 2];
 static char data_received;
 
diff --git a/cts/interrupt/cts.testlist b/cts/interrupt/cts.testlist
index 0fdaf6fca2..e48208d900 100644
--- a/cts/interrupt/cts.testlist
+++ b/cts/interrupt/cts.testlist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/cts/interrupt/dut.c b/cts/interrupt/dut.c
index 3c83e5701f..15bba740f0 100644
--- a/cts/interrupt/dut.c
+++ b/cts/interrupt/dut.c
@@ -1,9 +1,8 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <string.h>
 #include "common.h"
 #include "cts_common.h"
 #include "gpio.h"
@@ -12,6 +11,8 @@
 #include "timer.h"
 #include "watchdog.h"
 
+#include <string.h>
+
 static int got_interrupt;
 static int wake_me_up;
 static int state_index;
@@ -66,7 +67,7 @@ void cts_irq2(enum gpio_signal signal)
 
 void clean_state(void)
 {
-	uint32_t *event;
+	atomic_t *event;
 
 	interrupt_enable();
 	got_interrupt = 0;
diff --git a/cts/interrupt/th.c b/cts/interrupt/th.c
index 1639a1868c..ff9a3b303b 100644
--- a/cts/interrupt/th.c
+++ b/cts/interrupt/th.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/cts/meta/cts.testlist b/cts/meta/cts.testlist
index 28ac7e325f..2d41848737 100644
--- a/cts/meta/cts.testlist
+++ b/cts/meta/cts.testlist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/cts/meta/dut.c b/cts/meta/dut.c
index c321676aec..8880c7ba13 100644
--- a/cts/meta/dut.c
+++ b/cts/meta/dut.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/cts/meta/th.c b/cts/meta/th.c
index 57b2f492bd..ec7f061793 100644
--- a/cts/meta/th.c
+++ b/cts/meta/th.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/cts/mutex/cts.tasklist b/cts/mutex/cts.tasklist
index 3387e1de09..ad0c75c601 100644
--- a/cts/mutex/cts.tasklist
+++ b/cts/mutex/cts.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/cts/mutex/cts.testlist b/cts/mutex/cts.testlist
index 5b1cdb1dae..5cea62c079 100644
--- a/cts/mutex/cts.testlist
+++ b/cts/mutex/cts.testlist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/cts/mutex/dut.c b/cts/mutex/dut.c
index 4fcea73fdf..c4778de957 100644
--- a/cts/mutex/dut.c
+++ b/cts/mutex/dut.c
@@ -1,13 +1,13 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
- * Copyright 2011 Google Inc.
+ * Copyright 2011 Google LLC
  *
  * Tasks for mutexes basic tests.
  */
 
-#include "console.h"
 #include "common.h"
+#include "console.h"
 #include "cts_common.h"
 #include "task.h"
 #include "test_util.h"
@@ -23,7 +23,7 @@ static struct mutex mtx;
 
 int mutex_random_task(void *unused)
 {
-	char letter = 'A'+(TASK_ID_MTX3A - task_get_current());
+	char letter = 'A' + (TASK_ID_MTX3A - task_get_current());
 	/* wait to be activated */
 
 	while (1) {
@@ -82,7 +82,8 @@ static enum cts_rc lock_unlock_test(void)
 	/* --- Serialization to test simple contention --- */
 	ccprintf("Simple contention :\n");
 	/* lock the mutex from the other task */
-	task_set_event(TASK_ID_MTX2, TASK_EVENT_WAKE, 1);
+	task_set_event(TASK_ID_MTX2, TASK_EVENT_WAKE);
+	task_wait_event(0);
 	/* block on the mutex */
 	ccprintf("MTX1: blocking...\n");
 	mutex_lock(&mtx);
diff --git a/cts/mutex/th.c b/cts/mutex/th.c
index 4fcea73fdf..c4778de957 100644
--- a/cts/mutex/th.c
+++ b/cts/mutex/th.c
@@ -1,13 +1,13 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
- * Copyright 2011 Google Inc.
+ * Copyright 2011 Google LLC
  *
  * Tasks for mutexes basic tests.
  */
 
-#include "console.h"
 #include "common.h"
+#include "console.h"
 #include "cts_common.h"
 #include "task.h"
 #include "test_util.h"
@@ -23,7 +23,7 @@ static struct mutex mtx;
 
 int mutex_random_task(void *unused)
 {
-	char letter = 'A'+(TASK_ID_MTX3A - task_get_current());
+	char letter = 'A' + (TASK_ID_MTX3A - task_get_current());
 	/* wait to be activated */
 
 	while (1) {
@@ -82,7 +82,8 @@ static enum cts_rc lock_unlock_test(void)
 	/* --- Serialization to test simple contention --- */
 	ccprintf("Simple contention :\n");
 	/* lock the mutex from the other task */
-	task_set_event(TASK_ID_MTX2, TASK_EVENT_WAKE, 1);
+	task_set_event(TASK_ID_MTX2, TASK_EVENT_WAKE);
+	task_wait_event(0);
 	/* block on the mutex */
 	ccprintf("MTX1: blocking...\n");
 	mutex_lock(&mtx);
diff --git a/cts/task/cts.tasklist b/cts/task/cts.tasklist
index 6477d74c2c..1adbf211ec 100644
--- a/cts/task/cts.tasklist
+++ b/cts/task/cts.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/cts/task/cts.testlist b/cts/task/cts.testlist
index c4b7bc3231..3ad8e33928 100644
--- a/cts/task/cts.testlist
+++ b/cts/task/cts.testlist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/cts/task/dut.c b/cts/task/dut.c
index 7297b7de96..257809b4b8 100644
--- a/cts/task/dut.c
+++ b/cts/task/dut.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -34,10 +34,13 @@ void task_abc(void *data)
 
 	while (1) {
 		wake_count[id]++;
-		if (id == 2 && wake_count[id] == repeat_count)
-			task_set_event(TASK_ID_CTS, TASK_EVENT_WAKE, 1);
-		else
-			task_set_event(next, TASK_EVENT_WAKE, 1);
+		if (id == 2 && wake_count[id] == repeat_count) {
+			task_set_event(TASK_ID_CTS, TASK_EVENT_WAKE);
+			task_wait_event(0);
+		} else {
+			task_set_event(next, TASK_EVENT_WAKE);
+			task_wait_event(0);
+		}
 	}
 }
 
@@ -67,15 +70,15 @@ enum cts_rc test_task_switch(void)
 	}
 
 	if (wake_count[0] != repeat_count || wake_count[1] != repeat_count) {
-		CPRINTS("Unexpected counter values: %d %d %d",
-			wake_count[0], wake_count[1], wake_count[2]);
+		CPRINTS("Unexpected counter values: %d %d %d", wake_count[0],
+			wake_count[1], wake_count[2]);
 		return CTS_RC_FAILURE;
 	}
 
 	/* TODO: Verify no tasks are ready, no events are pending. */
-	if (*task_get_event_bitmap(TASK_ID_A)
-			|| *task_get_event_bitmap(TASK_ID_B)
-			|| *task_get_event_bitmap(TASK_ID_C)) {
+	if (*task_get_event_bitmap(TASK_ID_A) ||
+	    *task_get_event_bitmap(TASK_ID_B) ||
+	    *task_get_event_bitmap(TASK_ID_C)) {
 		CPRINTS("Events are pending");
 		return CTS_RC_FAILURE;
 	}
@@ -99,17 +102,17 @@ enum cts_rc test_task_priority(void)
 		return CTS_RC_FAILURE;
 	}
 
-	if (wake_count[0] != repeat_count - 1
-			|| wake_count[1] != repeat_count - 1) {
-		CPRINTS("Unexpected counter values: %d %d %d",
-			wake_count[0], wake_count[1], wake_count[2]);
+	if (wake_count[0] != repeat_count - 1 ||
+	    wake_count[1] != repeat_count - 1) {
+		CPRINTS("Unexpected counter values: %d %d %d", wake_count[0],
+			wake_count[1], wake_count[2]);
 		return CTS_RC_FAILURE;
 	}
 
 	/* TODO: Verify no tasks are ready, no events are pending. */
-	if (*task_get_event_bitmap(TASK_ID_A)
-			|| *task_get_event_bitmap(TASK_ID_B)
-			|| *task_get_event_bitmap(TASK_ID_C)) {
+	if (*task_get_event_bitmap(TASK_ID_A) ||
+	    *task_get_event_bitmap(TASK_ID_B) ||
+	    *task_get_event_bitmap(TASK_ID_C)) {
 		CPRINTS("Events are pending");
 		return CTS_RC_FAILURE;
 	}
diff --git a/cts/task/th.c b/cts/task/th.c
deleted file mode 120000
index 41eab28462..0000000000
--- a/cts/task/th.c
+++ /dev/null
@@ -1 +0,0 @@
-dut.c
\ No newline at end of file
diff --git a/cts/task/th.c b/cts/task/th.c
new file mode 100644
index 0000000000..257809b4b8
--- /dev/null
+++ b/cts/task/th.c
@@ -0,0 +1,144 @@
+/* Copyright 2013 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Tasks for scheduling test.
+ */
+
+#include "common.h"
+#include "cts_common.h"
+#include "task.h"
+#include "timer.h"
+
+static int repeat_count;
+static int wake_count[3];
+
+void clean_state(void)
+{
+	wake_count[0] = wake_count[1] = wake_count[2] = 0;
+}
+
+void task_abc(void *data)
+{
+	int task_id = task_get_current();
+	int id = task_id - TASK_ID_A;
+	task_id_t next = task_id + 1;
+
+	if (next > TASK_ID_C)
+		next = TASK_ID_A;
+
+	task_wait_event(-1);
+
+	CPRINTS("%c Starting", 'A' + id);
+	cflush();
+
+	while (1) {
+		wake_count[id]++;
+		if (id == 2 && wake_count[id] == repeat_count) {
+			task_set_event(TASK_ID_CTS, TASK_EVENT_WAKE);
+			task_wait_event(0);
+		} else {
+			task_set_event(next, TASK_EVENT_WAKE);
+			task_wait_event(0);
+		}
+	}
+}
+
+void task_tick(void *data)
+{
+	task_wait_event(-1);
+	ccprintf("\n[starting Task T]\n");
+
+	/* Wake up every tick */
+	while (1)
+		/* Wait for timer interrupt message */
+		usleep(3000);
+}
+
+enum cts_rc test_task_switch(void)
+{
+	uint32_t event;
+
+	repeat_count = 3000;
+
+	task_wake(TASK_ID_A);
+	event = task_wait_event(5 * SECOND);
+
+	if (event != TASK_EVENT_WAKE) {
+		CPRINTS("Woken up by unexpected event: 0x%08x", event);
+		return CTS_RC_FAILURE;
+	}
+
+	if (wake_count[0] != repeat_count || wake_count[1] != repeat_count) {
+		CPRINTS("Unexpected counter values: %d %d %d", wake_count[0],
+			wake_count[1], wake_count[2]);
+		return CTS_RC_FAILURE;
+	}
+
+	/* TODO: Verify no tasks are ready, no events are pending. */
+	if (*task_get_event_bitmap(TASK_ID_A) ||
+	    *task_get_event_bitmap(TASK_ID_B) ||
+	    *task_get_event_bitmap(TASK_ID_C)) {
+		CPRINTS("Events are pending");
+		return CTS_RC_FAILURE;
+	}
+
+	return CTS_RC_SUCCESS;
+}
+
+enum cts_rc test_task_priority(void)
+{
+	uint32_t event;
+
+	repeat_count = 2;
+
+	task_wake(TASK_ID_A);
+	task_wake(TASK_ID_C);
+
+	event = task_wait_event(5 * SECOND);
+
+	if (event != TASK_EVENT_WAKE) {
+		CPRINTS("Woken up by unexpected event: 0x%08x", event);
+		return CTS_RC_FAILURE;
+	}
+
+	if (wake_count[0] != repeat_count - 1 ||
+	    wake_count[1] != repeat_count - 1) {
+		CPRINTS("Unexpected counter values: %d %d %d", wake_count[0],
+			wake_count[1], wake_count[2]);
+		return CTS_RC_FAILURE;
+	}
+
+	/* TODO: Verify no tasks are ready, no events are pending. */
+	if (*task_get_event_bitmap(TASK_ID_A) ||
+	    *task_get_event_bitmap(TASK_ID_B) ||
+	    *task_get_event_bitmap(TASK_ID_C)) {
+		CPRINTS("Events are pending");
+		return CTS_RC_FAILURE;
+	}
+
+	return CTS_RC_SUCCESS;
+}
+
+static void recurse(int x)
+{
+	CPRINTS("+%d", x);
+	msleep(1);
+	recurse(x + 1);
+	CPRINTS("-%d", x);
+}
+
+enum cts_rc test_stack_overflow(void)
+{
+	recurse(0);
+	return CTS_RC_FAILURE;
+}
+
+#include "cts_testlist.h"
+
+void cts_task(void)
+{
+	task_wake(TASK_ID_TICK);
+	cts_main_loop(tests, "Task");
+	task_wait_event(-1);
+}
diff --git a/cts/timer/cts.testlist b/cts/timer/cts.testlist
index 9b5da0d6c9..6567757ced 100644
--- a/cts/timer/cts.testlist
+++ b/cts/timer/cts.testlist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/cts/timer/dut.c b/cts/timer/dut.c
index 96d7c5a3cf..9f94b9a398 100644
--- a/cts/timer/dut.c
+++ b/cts/timer/dut.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/cts/timer/th.c b/cts/timer/th.c
index e82cac71ab..e301ce0e38 100644
--- a/cts/timer/th.c
+++ b/cts/timer/th.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/docs/ap-ec-comm.md b/docs/ap-ec-comm.md
index a65c419171..6f1292bcaf 100644
--- a/docs/ap-ec-comm.md
+++ b/docs/ap-ec-comm.md
@@ -9,11 +9,12 @@ by issuing *host commands*, which are identified by a command ID and version
 number, and then reading a response. When a host command is issued through
 `ectool`, two or three software components are involved:
 
-* `ectool`, the user-space binary,
-* normally the `cros-ec` Kernel driver, and
-* the code on the EC itself. This can be thought of as two parts:
-  * a chip-specific driver for the appropriate transport, and
-  * the generic host command handling code (mostly in the [host command task]).
+*   `ectool`, the user-space binary,
+*   normally the `cros-ec` Kernel driver, and
+*   the code on the EC itself. This can be thought of as two parts:
+    *   a chip-specific driver for the appropriate transport, and
+    *   the generic host command handling code (mostly in the
+        [host command task]).
 
 We'll go into detail of each of these, as well as the traffic on the wire, in
 the following sections.
@@ -24,6 +25,21 @@ the following sections.
 providing a CLI. They call one of the transport-specific `ec_command`
 implementations in the `util/comm-*.c` files to send and receive from the EC.
 
+#### Stress test
+
+The `ectool stress` command sends a large amount of host commands continuously
+to the EC. This verifies that the EC can respond to all commands received
+without timeouts or communication errors.
+
+It will log the time elapsed for every iteration of sending 10000 host commands
+with the time that it took to send them.
+
+Example output of stress test is:
+`Update: attempt 10000 round 1 | took 205 seconds`
+
+Killing the process will result in displaying the total runtime and failures
+that happened during it.
+
 ### EC kernel driver
 
 In most cases, `ectool` communicates via the [`cros-ec` Kernel driver], rather
@@ -39,25 +55,25 @@ to the Linux [Industrial I/O] system.
 
 Now we come to the protocol itself. All transactions take this general form:
 
-* Host writes the request packet, consisting of:
-  * a transport-specific header;
-  * a `struct ec_host_request` containing the command ID, data length, and a
-    checksum; and
-  * zero or more bytes of parameters for the command, the format of which
-    depends on the command.
-* Host reads the response to its request, consisting of:
-  * a transport-specific header;
-  * a `struct ec_host_response` containing the result code, data length, and a
-    checksum; and
-  * zero or more bytes of response from the command, again with a
-    command-specific format.
+*   Host writes the request packet, consisting of:
+    *   a transport-specific header;
+    *   a `struct ec_host_request` containing the command ID, data length, and a
+        checksum; and
+    *   zero or more bytes of parameters for the command, the format of which
+        depends on the command.
+*   Host reads the response to its request, consisting of:
+    *   a transport-specific header;
+    *   a `struct ec_host_response` containing the result code, data length, and
+        a checksum; and
+    *   zero or more bytes of response from the command, again with a
+        command-specific format.
 
 ### On the EC
 
 The host packet is received on the EC by some chip-specific code which checks
-its transport-specific header, then passes it on to the common host command code,
-starting at `host_packet_receive`. The common code validates the packet and
-then sends it on to the handler function (annotated with the
+its transport-specific header, then passes it on to the common host command
+code, starting at `host_packet_receive`. The common code validates the packet
+and then sends it on to the handler function (annotated with the
 `DECLARE_HOST_COMMAND` macro), which runs in the `HOSTCMD` task. The handler can
 set a response by modifying its arguments struct, which is sent back to the host
 via the chip-specific code.
@@ -74,8 +90,8 @@ of the overarching protocol, and versions of individual commands.
 ### Protocol versions
 
 There have been three protocol versions so far, and this document describes
-version 3. Version 1 was superseded by 2 before it shipped, so no devices use
-it anymore. Version 2 is generally deprecated, but you might still encounter it
+version 3. Version 1 was superseded by 2 before it shipped, so no devices use it
+anymore. Version 2 is generally deprecated, but you might still encounter it
 occasionally.
 
 Which version is in use can be determined using the `EC_CMD_GET_PROTOCOL_INFO`
@@ -90,6 +106,41 @@ they're being called with. Different versions of a command may have different
 parameter or response formats. `EC_CMD_GET_CMD_VERSIONS` returns the versions of
 the given command supported by the EC. These version numbers start at 0.
 
+## Tracing
+
+Command tracing can be done on the EC console (`hc debug` command) and/or in
+the kernel:
+```
+echo 1 > /sys/kernel/debug/tracing/events/cros_ec/enable
+cat /sys/kernel/debug/tracing/trace
+
+369.416372: cros_ec_request_start: version: 0, command: EC_CMD_USB_PD_POWER_INFO
+369.420528: cros_ec_request_done: version: 0, command: EC_CMD_USB_PD_POWER_INFO, ec result: EC_RES_SUCCESS, retval: 16
+369.420529: cros_ec_request_start: version: 0, command: EC_CMD_USB_PD_DISCOVERY
+369.421383: cros_ec_request_done: version: 0, command: EC_CMD_USB_PD_DISCOVERY, ec result: EC_RES_SUCCESS, retval: 5
+```
+
+## API synchronization
+
+EC, coreboot, user space (`platform2)` and kernel needs to access the same
+information contained in `ec_commands.h`.
+
+*   Coreboot regularly update [ec_commands.h].
+*   User space/depthcharge use `ec_commands.h` installed by
+  `chromeos-base/chromeos-ec-headers` package.
+*   Kernel `ec_commands.h` - named
+  `./include/linux/platform_data/cros_ec_commands.h` - is not a direct
+copy. New commands and options are added on a need-to-know basis
+alongside the kernel code that uses these commands.
+
+A copy of `ec_commands.h`, matching kernel standard is auto-generated at
+`/build/kernel/include/linux/mfd/cros_ec_commands.h` when
+`make build_cros_ec_commands` or `make buildall` is run. (It is far from
+perfect, since the kernel include file has not been updated with `clang-format` as
+`ec_commands.h` has been). Copy the necessary changes from that file to
+`include/linux/platform_data/cros_ec_commands.h` and push the changes upstream
+first following the [upstream instructions].
+
 ## Transport-specific details
 
 Although the command and response formats are the same across all transports,
@@ -128,15 +179,14 @@ embedded controllers either aren't fast enough or don't have any support for
 hardware flow-control.
 
 It works like this: When the AP sends a byte to the EC, if the EC doesn't have a
-response queued up in advance, a default byte is returned. The EC
-preconfigures that default response byte to indicate its status (ready, busy,
-waiting for more input, etc.). Once the AP has sent a complete command message,
-it continues clocking bytes to the EC (which the EC ignores) and just looks at
-the response byte that comes back. Once the EC has parsed the AP's command and
-is ready to reply, it sends a "start of frame" byte, followed by the actual
-response. The AP continues to read and ignore bytes from the EC until it sees
-the start of frame byte, and then it knows that the EC's response is starting
-with the next byte.
+response queued up in advance, a default byte is returned. The EC preconfigures
+that default response byte to indicate its status (ready, busy, waiting for more
+input, etc.). Once the AP has sent a complete command message, it continues
+clocking bytes to the EC (which the EC ignores) and just looks at the response
+byte that comes back. Once the EC has parsed the AP's command and is ready to
+reply, it sends a "start of frame" byte, followed by the actual response. The AP
+continues to read and ignore bytes from the EC until it sees the start of frame
+byte, and then it knows that the EC's response is starting with the next byte.
 
 Once the response packet has been read, any additional reads should return
 `EC_SPI_PAST_END`.
@@ -146,8 +196,9 @@ Once the response packet has been read, any additional reads should return
 The EC should set `EC_LPC_STATUS_PROCESSING` in its command status register
 after receiving a host packet and before it has a response ready.
 
-
 [`cros-ec` Kernel driver]: https://chromium.googlesource.com/chromiumos/third_party/kernel/+/refs/heads/chromeos-4.19/drivers/mfd/cros_ec_dev.c
 [Industrial I/O]: https://www.kernel.org/doc/html/v4.14/driver-api/iio/index.html
-[host command task]: https://chromium.googlesource.com/chromiumos/platform/ec/+/refs/heads/master/common/host_command.c
+[host command task]: https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/common/host_command.c
 [Transport-specific details]: #Transport_specific-details
+[ec_commands.h]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/coreboot/src/ec/google/chromeec/ec_commands.h
+[upstream instructions]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/kernel_development.md#Upstream-development.
diff --git a/docs/case_closed_debugging.md b/docs/case_closed_debugging.md
index 05373f1de9..8310970652 100644
--- a/docs/case_closed_debugging.md
+++ b/docs/case_closed_debugging.md
@@ -1,2 +1,2 @@
-The has been moved into a [different
-branch](https://chromium.googlesource.com/chromiumos/platform/ec/+/cr50_stab/docs/case_closed_debugging.md)
+The has been moved into a
+[different branch](https://chromium.googlesource.com/chromiumos/platform/ec/+/cr50_stab/docs/case_closed_debugging.md)
diff --git a/docs/case_closed_debugging_cr50.md b/docs/case_closed_debugging_cr50.md
index 6eb622cc37..ac518c0153 100644
--- a/docs/case_closed_debugging_cr50.md
+++ b/docs/case_closed_debugging_cr50.md
@@ -1,2 +1,2 @@
-The has been moved into a [different
-branch](https://chromium.googlesource.com/chromiumos/platform/ec/+/cr50_stab/docs/case_closed_debugging_cr50.md)
+The has been moved into a
+[different branch](https://chromium.googlesource.com/chromiumos/platform/ec/+/cr50_stab/docs/case_closed_debugging_cr50.md)
diff --git a/docs/ccd_howtos.md b/docs/ccd_howtos.md
index 624253d22c..44deecd16d 100644
--- a/docs/ccd_howtos.md
+++ b/docs/ccd_howtos.md
@@ -1,2 +1,2 @@
-The has been moved into a [different
-branch](https://chromium.googlesource.com/chromiumos/platform/ec/+/cr50_stab/docs/ccd_howtos.md)
+The has been moved into a
+[different branch](https://chromium.googlesource.com/chromiumos/platform/ec/+/cr50_stab/docs/ccd_howtos.md)
diff --git a/docs/chromeos-ec-firmware-test-requirements.md b/docs/chromeos-ec-firmware-test-requirements.md
new file mode 100644
index 0000000000..721021275a
--- /dev/null
+++ b/docs/chromeos-ec-firmware-test-requirements.md
@@ -0,0 +1,121 @@
+# ChromeOS EC Firmware Code Test Requirements
+
+[TOC]
+
+## Overview
+
+The ChromeOS EC firmware requires that all C source and header file code changes
+include tests covering at least 90% of any new or changed lines of code. A
+non-blocking warning comment is posted on CLs that do not exceed 95% coverage
+This change is in effect as of 2023-01-19.
+
+The Gerrit commit-queue enforces the coverage requirement with the
+`firmware-zephyr-cov-cq` builder.
+
+## Rationale
+
+Starting 2H’22, all new Chromebook projects use the Zephyr RTOS as the
+foundation for the ChromeOS EC firmware.  As part of the switch to Zephyr RTOS,
+Google wrote unit and integration tests to verify functionality of the EC
+firmware.  These tests run directly on your development system using the
+native_posix environment and do not require any Chromebook hardware.
+
+These tests improve the quality of the EC firmware, reducing the number of EC
+crashes and bugs found on shipping Chromebooks.
+
+The ChromeOS EC firmware requires that all projects based on the Zephyr RTOS
+achieve code coverage of 90% or better.
+
+A Gitlab project creates and publishes the code coverage reports for the
+Zephyr EC projects. The latest results are available on the Gitlab [Jobs page].
+Refer to the [Gitlab CI] documentation for implementation details.
+
+## Resources for writing tests
+
+* The [Zephyr Testing] documentation in the ChromeOS EC firmware provides the
+  most up-to-date information for writing tests specifically for the ChromeOS EC
+  firmware.
+
+* [Zephyr Test Framework] documentation in the Zephyr Project provides general
+  information about the test framework used by Zephyr RTOS.
+
+### Testing project specific code
+
+* The board
+
+### Generating coverage reports
+
+* [Zephyr ztest code coverage] provides instructions for generating code coverage
+reports locally on your machine.
+
+* [Code Coverage in CQ] provides details for viewing the coverage information
+  directly from Gerrit or by using Google's code search tool.
+
+### Bypassing the code coverage requirement
+
+In limited cases, you may amend your commit message to include the
+`LOW_COVERAGE_REASON` tag. This tag bypasses the code coverage requirement
+enforced by Gerrit. Simply add the tag followed by a description to justify
+bypassing code coverage. You must include a reference to a bug (in the form
+`b:1234567` or `b/1234567`) that tracks whatever issue is impeding coverage.
+
+```
+LOW_COVERAGE_REASON=no emulator for the ANX7483 exists b/248086547
+```
+
+Permissible reasons for bypassing the code coverage requirements include:
+
+* Fixing a high-priority bug that blocks a release or some other milestone.
+
+* Fixing a bug in an existing driver that is currently untested.
+
+* Modifying on-chip EC peripheral drivers. See the [Known Issues](#known_issues)
+  section below for details.
+
+When bypassing code coverage, please open a bug to track the work required to
+create tests.
+
+Reviewers may reject your low coverage reason and request that you update or add
+tests for your change.
+
+## Exceptions to code coverage
+
+### Legacy EC code
+
+Zephyr EC projects share large portions of the legacy code found under the
+[`platform/ec`] repository. The code coverage requirements apply to the shared
+code, with exceptions for the following directories:
+
+* [`platform/ec/baseboard`]
+* [`platform/ec/board`]
+* [`platform/ec/chip`]
+
+### Known issues
+
+There are no tests for the chip specific code found under the
+[`platform/ec/zephyr/drivers`] directory. Due to include file conflicts, it is
+not currently known how to test these drivers.
+
+### False positives
+
+The coverage tool may falsely mark a line of code as executable but the line of
+code is not reachable. An example could be a switch statement, but the default
+label is not reachable. In these cases add a comment using exclusion markers,
+`LCOV_EXCL_*`,  to the file.  See the [geninfo manpage] for more information.
+
+Do not use exclusion markers to bypass executable code or to avoid writing tests
+for difficult to reach code.
+
+
+[`platform/ec/baseboard`]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/baseboard
+[`platform/ec/board`]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/board
+[`platform/ec/chip`]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/chip
+[`platform/ec/zephyr/drivers`]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/drivers
+[Jobs page]: https://gitlab.com/zephyr-ec/ec/-/jobs/
+[Gitlab CI]: ./gitlab.md
+[Zephyr Testing]: ./zephyr/ztest.md
+[Zephyr Test Framework]: https://docs.zephyrproject.org/latest/develop/test/ztest.html
+[Zephyr ztest code coverage]: ./code_coverage.md#Zephyr-ztest-code-coverage
+[Code Coverage in CQ]: ./code_coverage.md#code-coverage-in-cq
+[`platform/ec`]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/
+[geninfo manpage]: https://manpages.debian.org/unstable/lcov/geninfo.1.en.html
diff --git a/docs/code_coverage.md b/docs/code_coverage.md
index 458d87b7c5..0683dbe401 100644
--- a/docs/code_coverage.md
+++ b/docs/code_coverage.md
@@ -5,10 +5,16 @@ tests in the EC codebase.
 
 [TOC]
 
+## Test Coverage Requirements
+
+All changes to the EC code base require you include tests covering at least 80%
+of any new or changed lines of code. Refer to the [ChromeOS EC Firmware Test
+Requirements] for details.
+
 ## Availability
 
-Code coverage is only available for host-based unit tests, as opposed to
-manual tests that run on target hardware.
+Code coverage is only available for host-based unit tests, as opposed to manual
+tests that run on target hardware.
 
 ## Building for code coverage
 
@@ -23,12 +29,131 @@ data into a code coverage report using the `lcov` and `genhtml` tools.
 
 The coverage report top-level page is `build/coverage/coverage_rpt/index.html`.
 
+To get a report for one specific board's coverage run these commands:
+
+```
+BOARD=eldrid
+make -j$(nproc) build/coverage/initial-${BOARD}.info test-coverage
+# Merge board coverage and test coverage
+lcov -o build/coverage/${BOARD}_merged.info --rc lcov_branch_coverage=1 \
+  -a build/coverage/initial-${BOARD}.info -a build/coverage/lcov.info
+# Filter out some unhelpful paths
+lcov -o build/coverage/${BOARD}_filtered.info --rc lcov_branch_coverage=1 \
+  -r build/coverage/${BOARD}_merged.info ${PWD}'/third_party/**' \
+  ${PWD}'/build/**' '/usr/include/**' '/usr/lib/**' '${PWD}/test/**' \
+  ${PWD}'/private/fingerprint/*/mcutest/**'
+# Restrict to only files used by the board
+grep "SF:" "build/coverage/initial-${BOARD}.info" | sort -u | \
+      sed -e 's|^SF:||' | xargs lcov --rc lcov_branch_coverage=1 \
+      -o build/coverage/${BOARD}_final.info \
+      -e build/coverage/${BOARD}_filtered.info
+# Generate HTML
+genhtml --branch-coverage -q -o build/coverage/${BOARD}_rpt \
+  -t "${BOARD} coverage" -s build/coverage/${BOARD}_final.info
+```
+
 ### Noise in the build output
 
 When building for code coverage, you may see multiple warnings of the form
-`geninfo: WARNING: no data found for /mnt/host/source/src/platform/ec/core/host/cpu.h`
-and
-`genhtml: WARNING: function data mismatch at /mnt/host/source/src/platform/ec/common/math_util.c:134`
+`geninfo: WARNING: no data found for
+/mnt/host/source/src/platform/ec/core/host/cpu.h` and `genhtml: WARNING:
+function data mismatch at
+/mnt/host/source/src/platform/ec/common/math_util.c:134`
 
 These warnings can be ignored. (FYI, the "function data mismatch" warnings
 appear to be caused in part by using relative paths instead of absolute paths.)
+
+## Zephyr ztest code coverage
+
+To build the Zephyr unit tests for code coverage run:
+
+`./twister -v -i --coverage -p native_posix -p unit_testing`
+
+The coverage report top-level page is
+`twister-out/coverage/index.html`.
+
+However you probably want to merge that with a single board's coverage report
+also, so that you can include code that is not part of any test as well.
+
+```
+zmake build --coverage herobrine
+./twister -v -i --coverage -p native_posix -p unit_testing
+genhtml -q -s --branch-coverage -o build/zephyr/coverage_rpt/ \
+  twister-out/coverage.info build/zephyr/herobrine/output/zephyr.info
+```
+
+The coverage report top-level page is
+`build/zephyr/coverage_rpt/index.html`.
+
+For coverage report for a single test you can run: `./twister -v -i --coverage
+-p native_posix -p unit_testing -s <testDir>/<testName>`
+
+Example of running test `tasks.default` from `zephyr/test/tasks/testcase.yaml`:
+`./twister -v -i --coverage -p native_posix -p unit_testing -s
+tasks/tasks.default`
+
+## Code Coverage in CQ
+
+There are several ways to see the code coverage without running the tests
+locally, depending on what information you want to see. Many of the links
+below are only available to Googlers or TVCs with google.com accounts.
+
+### Code search
+
+To see the coverage of each directory, visit
+http://cs/chromeos_public/src/platform/ec/ and turn on the "Directory Coverage"
+layer.  The denominator for the percentage covered is not clear, so these
+numbers are really only useful if you are looking in very general terms. I.e.
+zephyr is covered better than common. Don't get too fixated on the specific
+percent shown. The results are also the last 7 days of builds combined, so there
+may be some odd results if the code has changed greatly in the last week.
+
+![Directory coverage screenshot](images/dir_coverage.png)
+
+The coverage of files is much more useful. If you are about to write a test
+and not sure what to focus on, you can look at the uncovered lines in code
+search. Visit [a file](http://cs/chromeos_public/src/platform/ec/common/mkbp_event.c)
+in code search and make sure the "File Coverage" layer is enabled. Lines that
+are not covered by any test are in red, tested lines are in green, and uncolored
+lines were not built at all in any board or test.
+
+![File coverage screenshot](images/file_coverage.png)
+
+### Presubmit
+
+Every gerrit cl, if you did a dry-run or full run of the CQ will have coverage
+results. They are slightly difficult to get to, but are very useful.
+
+On the "Checks" tab, find the build "firmware-zephyr-cov-cq" and open it.
+
+![Gerrit screenshot](images/gerrit_coverage_links.png)
+
+On the LUCI page, expand the "test firmware" step and click on "response". That
+will show you a very basic summary of the coverage.
+
+![LUCI screenshot test firmware](images/test_firmware.png)
+
+For a detailed report, you can download the coverage report. Expand "try to
+upload artifacts", then "upload artifacts", and click on "gs upload dir".
+
+![LUCI screenshot artifacts](images/artifacts.png)
+
+From there, click on the download icon for the html.tbz2 file, and untar it
+locally. Open lcov_rpt/index.html to view your results.
+
+![GCS screenshot](images/download_html.png)
+
+### Post-submit
+
+If you are interested in the state of the world, not a specific CL, and the
+coverage info in Code Search is not sufficient, you can download the coverage
+report from the post-submit CQ build.
+
+Visit https://ci.chromium.org/p/chromeos/builders/postsubmit/firmware-zephyr-cov-postsubmit
+and click on the latest successful build.
+
+![LUCI post-submit screenshot](images/postsubmit.png)
+
+From there, it is exactly the same steps as above to get to the artifacts.
+
+[ChromeOS EC Firmware Test Requirements]: ./chromeos-ec-firmware-test-requirements.md
diff --git a/docs/code_reviews.md b/docs/code_reviews.md
index 8bda5fe31a..a8e77c3fd8 100644
--- a/docs/code_reviews.md
+++ b/docs/code_reviews.md
@@ -44,11 +44,11 @@ Add your name to the [list of reviewers][1].
 
 ## Reference
 
-* [Chrome OS firmware review guidelines][2]
-* [Coreboot Gerrit Guidelines][3]
-* [Google small CL guidelines][5]
+*   [Chrome OS firmware review guidelines][2]
+*   [Coreboot Gerrit Guidelines][3]
+*   [Google small CL guidelines][5]
 
 [1]: http://google3/chrome/crosinfra/gwsq/ec_reviewers
-[2]: http://chromium.googlesource.com/chromiumos/docs/+/master/firmware_code_reviews.md
+[2]: http://chromium.googlesource.com/chromiumos/docs/+/HEAD/firmware_code_reviews.md
 [3]: https://doc.coreboot.org/getting_started/gerrit_guidelines.html
 [5]: https://google.github.io/eng-practices/review/developer/small-cls.html
diff --git a/docs/configuration/ap_power_sequencing.md b/docs/configuration/ap_power_sequencing.md
index 2b78592e57..ba9fc89f29 100644
--- a/docs/configuration/ap_power_sequencing.md
+++ b/docs/configuration/ap_power_sequencing.md
@@ -3,19 +3,19 @@
 This section details the configuration related to managing the system power
 states (G3, S5, S3, S0, S0iX, etc). This includes the following tasks:
 
-- Selecting the AP chipset type.
-- Configure output GPIOs that enable voltage rails.
-- Configure input GPIOs that monitor the voltage rail status (power good
-  signals).
-- Configure input GPIOs that monitor the AP sleep states.
-- Pass through power sequencing signals from the board to the AP, often with
-  delays or other sequencing control.
+-   Selecting the AP chipset type.
+-   Configure output GPIOs that enable voltage rails.
+-   Configure input GPIOs that monitor the voltage rail status (power good
+    signals).
+-   Configure input GPIOs that monitor the AP sleep states.
+-   Pass through power sequencing signals from the board to the AP, often with
+    delays or other sequencing control.
 
 ## Config options
 
 The AP chipset options are grouped together in [config.h]. Select exactly one of
 the available AP chipset options (e.g. `CONFIG_CHIPSET_APOLLOLAKE`,
-`CONFIG_CHIPSET_BRASWELL`, etc). If the AP chipset support is not available,
+`CONFIG_CHIPSET_COMETLAKE`, etc). If the AP chipset support is not available,
 select `CONFIG_CHIPSET_ECDRIVEN` to enable basic support for handling S3 and S0
 power states.
 
@@ -28,8 +28,8 @@ particular, the `CONFIG_POWER_BUTTON`, and `CONFIG_POWER_COMMON` should be
 defined.
 
 The `CONFIG_BRINGUP` option is especially useful option during the initial power
-up of a new board. This option is discussed in more detail in the [Testing and
-Debugging](#Testing-and-Debugging) section.
+up of a new board. This option is discussed in more detail in the
+[Testing and Debugging](#Testing-and-Debugging) section.
 
 ## Feature Parameters
 
@@ -54,15 +54,16 @@ GPIO(EN_PP5000,   PIN(A, 4), GPIO_OUT_LOW)
 For boards with an x86 AP, the following signals can be connected between the EC
 and AP/PCH. Create `GPIO()` entries for any signals used on your board.
 
-- `GPIO_PCH_PWRBTN_L` - Output from the EC that proxies the status of the EC
-  input `GPIO_POWER_BUTTON_L` (driven by the H1). Only used when
-  `CONFIG_POWER_BUTTON_X86` is defined.
-- `GPIO_PCH_RSMRST_L` - Output from the EC that proxies the status of the EC
-  input `GPIO_RSMRST_L_PGOOD` (driven by the PMIC or voltage regulators on the
-  board).
-- `GPIO_PCH_SYS_PWROK` - Output from the EC that indicates when the system power
-  is good and the AP can power up.
-- `GPIO_PCH_WAKE_L` - Output from the EC, driven low when there is a wake event.
+-   `GPIO_PCH_PWRBTN_L` - Output from the EC that proxies the status of the EC
+    input `GPIO_POWER_BUTTON_L` (driven by the H1). Only used when
+    `CONFIG_POWER_BUTTON_X86` is defined.
+-   `GPIO_PCH_RSMRST_L` - Output from the EC that proxies the status of the EC
+    input `GPIO_RSMRST_L_PGOOD` (driven by the PMIC or voltage regulators on the
+    board).
+-   `GPIO_PCH_SYS_PWROK` - Output from the EC that indicates when the system
+    power is good and the AP can power up.
+-   `GPIO_PCH_WAKE_L` - Output from the EC, driven low when there is a wake
+    event.
 
 ### Power Signal Interrupts
 
@@ -85,15 +86,15 @@ macros.
 
 ## Data structures
 
-- `const struct power_signal_info power_signal_list[]` - This array defines the
-  signals from the AP and from the power subsystem on the board that control the
-  power state. For some Intel chipsets, including Apollo Lake and Ice Lake, this
-  power signal list is already defined by the corresponding chipset file under
-  the `./power` directory.
+-   `const struct power_signal_info power_signal_list[]` - This array defines
+    the signals from the AP and from the power subsystem on the board that
+    control the power state. For some Intel chipsets, including Apollo Lake and
+    Ice Lake, this power signal list is already defined by the corresponding
+    chipset file under the `./power` directory.
 
 ## Tasks
 
-The `CHIPSET` task monitors and handles the power state changes.  This task
+The `CHIPSET` task monitors and handles the power state changes. This task
 should always be enabled with a priority higher than the `CHARGER` task, but
 lower than the `HOSTCMD` and `CONSOLE` tasks.
 
@@ -178,8 +179,8 @@ RTC: 0x000067bf (26559.00 s)
 [9.128640 power state 7 = S3->S0, in 0x003f]
 ```
 
-This example shows successful power on of the AP as the AP transitions from the G3
-state all the way to the S0 state.
+This example shows successful power on of the AP as the AP transitions from the
+G3 state all the way to the S0 state.
 
 The console messages shown in brackets `[]` include a timestamp. This timestamp
 records when the corresponding console message was printed.
@@ -192,7 +193,7 @@ signal changes shown on the console to be out of order with respect to the other
 EC messages.
 
 The power signal changes include a timestamp to help you correlate when the
-actual power signal changed compared to other messages.  From the example above,
+actual power signal changed compared to other messages. From the example above,
 the first power signal change recorded is the `DSW_PWROK` signal transitioning
 from 0 to 1, and this is recorded at timestamp `6.807298`. Using the regular EC
 console timestamp, you can reconstruct the real power sequence to look like the
@@ -246,7 +247,6 @@ RTC: 0x000067bf (26559.00 s)
 [9.128640 power state 7 = S3->S0, in 0x003f]
 ```
 
-
 *TODO ([b/147808790](http://issuetracker.google.com/147808790)) Add
 documentation specific to each x86 processor type.*
 
diff --git a/docs/configuration/cbi.md b/docs/configuration/cbi.md
index f285e8a8c2..f89ee78454 100644
--- a/docs/configuration/cbi.md
+++ b/docs/configuration/cbi.md
@@ -8,13 +8,13 @@ before enabling CBI.
 
 Add the following config options to `baseboard.h` or `board.h`.
 
-- `CONFIG_BOARD_VERSION_CBI`
-- `CONFIG_CROS_BOARD_INFO`
+-   `CONFIG_BOARD_VERSION_CBI`
+-   `CONFIG_CBI_EEPROM`
 
 ## Feature Parameters
 
-- `I2C_ADDR_EEPROM_FLAGS <7-bit addr>` - Defines the 7-bit slave address for the
-  EEPROM containing CBI.
+-   `I2C_ADDR_EEPROM_FLAGS <7-bit addr>` - Defines the 7-bit slave address for
+    the EEPROM containing CBI.
 
 ## GPIOs and Alternate Pins
 
@@ -31,8 +31,9 @@ None required by this feature.
 
 ## Testing and Debugging
 
-Refer to the [I2C debugging information] to verify communication with the CBI EEPROM.
+Refer to the [I2C debugging information] to verify communication with the CBI
+EEPROM.
 
-[CBI]: https://chromium.googlesource.com/chromiumos/docs/+/master/design_docs/cros_board_info.md
+[CBI]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/design_docs/cros_board_info.md
 [I2C buses]: ./i2c.md
-[I2C debugging information]: ./i2c.md#
\ No newline at end of file
+[I2C debugging information]: ./i2c.md#
diff --git a/docs/configuration/config_ap_to_ec_comm.md b/docs/configuration/config_ap_to_ec_comm.md
index 2fdcc5a147..0a517401be 100644
--- a/docs/configuration/config_ap_to_ec_comm.md
+++ b/docs/configuration/config_ap_to_ec_comm.md
@@ -1,7 +1,7 @@
 # Configure AP to EC Communication
 
 This document provides details on how to configure the AP to EC communication
-channel used on your board.  The [AP to EC Communication] document provides
+channel used on your board. The [AP to EC Communication] document provides
 details a system level of the operation of this feature.
 
 ## Config options
@@ -9,13 +9,13 @@ details a system level of the operation of this feature.
 Configure the AP to EC communication channel, picking exactly one of the
 following options.
 
-- `CONFIG_HOSTCMD_SPS` - [SPI slave](./ec_terms.md#spi) (SPS) interface
-- `CONFIG_HOSTCMD_HECI` - HECI interface
-- `CONFIG_HOSTCMD_LPC` - [LPC](./ec_terms.md#lpc) bus
-- `CONFIG_HOSTCMD_ESPI` - [eSPI](./ec_terms.md#espi) bus
+-   `CONFIG_HOST_INTERFACE_SHI` - [SPI Host Interface](../ec_terms.md#shi) (SHI)
+-   `CONFIG_HOST_INTERFACE_HECI` - HECI interface
+-   `CONFIG_HOST_INTERFACE_LPC` - [LPC](../ec_terms.md#lpc) bus
+-   `CONFIG_HOST_INTERFACE_ESPI` - [eSPI](../ec_terms.md#espi) bus
 
 In [config.h], search for options that start with the same name as your selected
-communication interface.  Override defaults as needed.
+communication interface. Override defaults as needed.
 
 ## Feature Parameters
 
@@ -26,26 +26,26 @@ None needed in this section.
 The EC code requires the following signals between the AP and the EC to be
 defined by each board variant.
 
-- `GPIO_ENTERING_RW` - Output from the EC, active high signal indicates when the
-  EC code transitions from RO to RW code.
+-   `GPIO_ENTERING_RW` - Output from the EC, active high signal indicates when
+    the EC code transitions from RO to RW code.
 
-  ```c
-  GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
-  ```
+    ```c
+    GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
+    ```
 
-- `GPIO_SYS_RESET_L` - Output from the EC, active low signal used to put the AP
-  into reset.
+-   `GPIO_SYS_RESET_L` - Output from the EC, active low signal used to put the
+    AP into reset.
 
-  ```c
-  GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
-  ```
+    ```c
+    GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
+    ```
 
 Create `ALTERNATE()` entries for all EC signals used for AP communication. This
 step can be skipped for any pins that default to communication channel
 functionality.
 
-See the [GPIO](./gpio.md) documentation for additional details on
-the GPIO macros.
+See the [GPIO](./gpio.md) documentation for additional details on the GPIO
+macros.
 
 ## Data structures
 
@@ -58,15 +58,15 @@ always required. The typical priority is higher than the `CHIPSET` task, but
 lower than the `CONSOLE` task.
 
 ```c
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE, 0) \
+    TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE, 0) \
 ```
 
 ## Testing and Debugging
 
 For Nuvoton EC chipsets, the file [./chip/npcx/registers.h] provides a
 collection of `DEBUG_*` macros that can be used to enable extra console messages
-related to a specific interface.  For AP to EC communication, the `DEBUG_LPC`
-and `DEBUG_ESPI` macros can help troubleshoot communication issues.
+related to a specific interface. For AP to EC communication, the `DEBUG_LPC` and
+`DEBUG_ESPI` macros can help troubleshoot communication issues.
 
 [./chip/npcx/registers.h]: ../../chip/npcx/registers.h
 [AP to EC Communication]: ../ap-ec-comm.md
diff --git a/docs/configuration/ec_chipset.md b/docs/configuration/ec_chipset.md
index 5f04c4d81e..defc27eec8 100644
--- a/docs/configuration/ec_chipset.md
+++ b/docs/configuration/ec_chipset.md
@@ -6,20 +6,20 @@ The EC chipset is selected using board specific make file [build.mk]. The
 following configuration options specify the type and size of flash memory used
 by the EC.
 
-  - `CONFIG_SPI_FLASH_REGS` - Should always be defined when using internal or
+-   `CONFIG_SPI_FLASH_REGS` - Should always be defined when using internal or
     external SPI flash.
-  - `CONFIG_SPI_FLASH` - Define only if your board uses an external flash.
-  - `CONFIG_SPI_FLASH_<device_type>` - Select exactly one the supported flash
+-   `CONFIG_SPI_FLASH` - Define only if your board uses an external flash.
+-   `CONFIG_SPI_FLASH_<device_type>` - Select exactly one the supported flash
     devices to compile in the required driver. This is needed even when using
     the internal SPI flash of the EC chipset.
-  - Additional EC Chipset options are prefixed with `CONFIG_HIBERNATE*` and
+-   Additional EC Chipset options are prefixed with `CONFIG_HIBERNATE*` and
     should be evaluated for relevance on your board.
 
 ## Feature Parameters
 
-  - `CONFIG_FLASH_SIZE <bytes>` - Set to the size of the internal flash of the
-    EC. Must be defined to link the final image.
-  - `CONFIG_SPI_FLASH_PORT <port>` - Only used if your board as an external
+-   `CONFIG_FLASH_SIZE_BYTES <bytes>` - Set to the size of the internal flash of
+    the EC. Must be defined to link the final image.
+-   `CONFIG_SPI_FLASH_PORT <port>` - Only used if your board as an external
     flash.
 
 ## GPIOs and Alternate Pins
@@ -27,38 +27,39 @@ by the EC.
 Configure the signals which will wakeup the EC from hibernate or deep sleep.
 Typical wakeup sources include:
 
-- `GPIO_LID_OPEN` - An active high signal that indicates the lid has been
-  opened. The source of the signal is typically from a [GMR](../ec_terms.md#gmr)
-  or Hall-Effect sensor. The `GPIO_INT()` entry for this signal should be
-  connected to the `lid_interrupt()` routine.
-- `GPIO_AC_PRESENT` - A signal from the battery charger that indicates the
-  device is connected to AC power. This signal is connected to the
-  `power_interrupt()` routine.
-- `GPIO_POWER_BUTTON_L` - An active low signal from the power switch. This signal is connected to the `power_button_interrupt()` routine.
-- `GPIO_EC_RST_ODL` - On some Nuvoton EC chipsets, the reset signal is
-  dual-routed to both a dedicated reset pin and a GPIO. In this case, no
-  interrupt handler needs to be registered to the GPIO signal, but the GPIO pin
-  must still be configured to wake on both edge types. The GPIO pin should also
-  be locked prevent the pin configuration from changing after the EC read-only
-  code runs.
+-   `GPIO_LID_OPEN` - An active high signal that indicates the lid has been
+    opened. The source of the signal is typically from a
+    [GMR](../ec_terms.md#gmr) or Hall-Effect sensor. The `GPIO_INT()` entry for
+    this signal should be connected to the `lid_interrupt()` routine.
+-   `GPIO_AC_PRESENT` - A signal from the battery charger that indicates the
+    device is connected to AC power. This signal is connected to the
+    `power_interrupt()` routine.
+-   `GPIO_POWER_BUTTON_L` - An active low signal from the power switch. This
+    signal is connected to the `power_button_interrupt()` routine.
+-   `GPIO_EC_RST_ODL` - On some Nuvoton EC chipsets, the reset signal is
+    dual-routed to both a dedicated reset pin and a GPIO. In this case, no
+    interrupt handler needs to be registered to the GPIO signal, but the GPIO
+    pin must still be configured to wake on both edge types. The GPIO pin should
+    also be locked prevent the pin configuration from changing after the EC
+    read-only code runs.
 
 See the [GPIO](./gpio.md) documentation for additional details on the GPIO
 macros.
 
 ## Data structures
 
-- `const enum gpio_signal hibernate_wake_pins[]` - add all GPIO signals that
-  should trigger a wakeup of the EC.
-- `const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);` -
-  configures the number of wake signals used on the board.
+-   `const enum gpio_signal hibernate_wake_pins[]` - add all GPIO signals that
+    should trigger a wakeup of the EC.
+-   `const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);` -
+    configures the number of wake signals used on the board.
 
 All ChromeOS wake sources are documented on the ChromeOS partner site in the
-[Wake Sources and Battery Life] section.  The EC specific wake sources are found
+[Wake Sources and Battery Life] section. The EC specific wake sources are found
 under the Deep Sleep and Shipping states and include:
 
-- Power button
-- AC insert
-- Lid open
+-   Power button
+-   AC insert
+-   Lid open
 
 ## Tasks
 
@@ -95,19 +96,21 @@ ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)
 ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)
 ```
 
-The final step is to add the hibernate signals array to Volteer [baseboard.c] file:
+The final step is to add the hibernate signals array to Volteer [baseboard.c]
+file:
 
 ```c
 /* Wake up pins */
 const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_LID_OPEN,
-	GPIO_ACOK_OD,
-	GPIO_POWER_BUTTON_L,
-	GPIO_EC_RST_ODL,
+    GPIO_LID_OPEN,
+    GPIO_ACOK_OD,
+    GPIO_POWER_BUTTON_L,
+    GPIO_EC_RST_ODL,
 };
 const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 ```
+
 [gpio.inc]: ../../board/volteer/gpio.inc
 [baseboard.c]: ../../baseboard/volteer/baseboard.c
 [build.mk]: ../new_board_checklist.md#board_build_mk
-[Wake Sources and Battery Life]: https://chromeos.google.com/partner/dlm/docs/latest-requirements/chromebook.html#wake-sources-and-battery-life
\ No newline at end of file
+[Wake Sources and Battery Life]: https://chromeos.google.com/partner/dlm/docs/latest-requirements/chromebook.html#wake-sources-and-battery-life
diff --git a/docs/configuration/gpio.md b/docs/configuration/gpio.md
index 4e13a7cb59..f4a5c4719a 100644
--- a/docs/configuration/gpio.md
+++ b/docs/configuration/gpio.md
@@ -4,18 +4,18 @@ GPIO setup is done for every board variant, but never for the baseboard, by
 configuring the file `./board/<board>/gpio.inc`. This file configures all the
 the pins on the EC chipset through the following macros.
 
-- `GPIO(<name>, ...)` - Configures simple GPIO input and outputs
-- `GPIO_INT(<name>, ...)` - Configures GPIO inputs that connect to an interrupt
-  service routine.  Historically these entries are defined first, but this no
-  longer required.
-- `ALTERNATE(...)` - Configures a pin for an alternate function (e.g I2C, ADC,
-  SPI, etc)
-- `UNIMPLEMENTED(<name>, ...)` - Creates a fake GPIO entry
+-   `GPIO(<name>, ...)` - Configures simple GPIO input and outputs
+-   `GPIO_INT(<name>, ...)` - Configures GPIO inputs that connect to an
+    interrupt service routine. Historically these entries are defined first, but
+    this no longer required.
+-   `ALTERNATE(...)` - Configures a pin for an alternate function (e.g I2C, ADC,
+    SPI, etc)
+-   `UNIMPLEMENTED(<name>, ...)` - Creates a fake GPIO entry
 
 The `GPIO()`, `GPIO_INT()`, and `UNIMPLEMENTED()` macros create a C enumeration
-of the form `GPIO_<name>` that can be used in the code. As noted in [GPIO
-Naming](../new_board_checklist.md#GPIO-Naming), the `<name>` parameter should
-always match the schematic net name.
+of the form `GPIO_<name>` that can be used in the code. As noted in
+[GPIO Naming](../new_board_checklist.md#GPIO-Naming), the `<name>` parameter
+should always match the schematic net name.
 
 ## `GPIO()` macro
 
@@ -23,13 +23,13 @@ always match the schematic net name.
 
 `GPIO(name, pin, flags)`
 
-- `name` - Defines the schematic net name, which is expanded to the enumeration
-  `GPIO_name` by the macro.
-- `pin` - Use the `PIN(group,pin)` macro to define the GPIO group and pin
-  number. Note that on a few EC chipsets, the PIN macro is just `PIN(pin)`.
-- `flags` - Define attributes of the pin (direction, pullup/pulldown, open
-  drain, voltage level, etc).  All supported flags are found following the
-  `GPIO_FLAG_NONE` definition in [./include/gpio.h](../../include/gpio.h).
+-   `name` - Defines the schematic net name, which is expanded to the
+    enumeration `GPIO_name` by the macro.
+-   `pin` - Use the `PIN(group,pin)` macro to define the GPIO group and pin
+    number. Note that on a few EC chipsets, the PIN macro is just `PIN(pin)`.
+-   `flags` - Define attributes of the pin (direction, pullup/pulldown, open
+    drain, voltage level, etc). All supported flags are found following the
+    `GPIO_FLAG_NONE` definition in [./include/gpio.h](../../include/gpio.h).
 
 ### Example
 
@@ -49,15 +49,16 @@ should also map the net name to the EC name in the `board.h` file.
 ## `GPIO_INT()` macro
 
 ### Prototype
+
 `GPIO_INT(name, pin, flags, signal)`
 
-- `name` - Defines the schematic net name, which is expanded to the enumeration
-  `GPIO_name` by the macro.
-- `pin` - Same definition as `GPIO()` macro.
-- `flags` - Same definition as `GPIO()` macro. Should always have one of the
-  `GPIO_INT_*` flags set.
-- `signal` - Interrupt service routine called when the pin asserts according to
-  the flags set.
+-   `name` - Defines the schematic net name, which is expanded to the
+    enumeration `GPIO_name` by the macro.
+-   `pin` - Same definition as `GPIO()` macro.
+-   `flags` - Same definition as `GPIO()` macro. Should always have one of the
+    `GPIO_INT_*` flags set.
+-   `signal` - Interrupt service routine called when the pin asserts according
+    to the flags set.
 
 ### Example
 
@@ -77,42 +78,43 @@ need to map the net name to the EC name in the `board.h` file.
 ## `ALTERNATE()` macro
 
 ### Prototype
+
 `ALTERNATE(pinmask, function, module, flags)`
 
-- `pinmask` - Defines a set of pins in the same GPIO group to assign to a
-  different function.
-- `function` - A chip-specific function number. Only used if the EC chipset
-  provides multiple alternate functions in addition to GPIO (e.g. pin can be
-  UART, I2C, SPI, or GPIO). The permitted values for this parameter vary based
-  on the EC chipset type.
-  - STM32 - 0 to 7
-  - Maxim - 1 to 3
-  - Microchip - 0 to 3
-  - MediaTek - 0 to 7
-  - All others (Nuvton, ITE, TI Stellaris, ) only support one alternate
-    function per pin, so this parameter should be set to 0.
-- `module` - One of the enum module_id values defined in
-  [./include/module_id.h](../../include/module_id.h).
-- `flags` - Same definition as `GPIO()` macro.
+-   `pinmask` - Defines a set of pins in the same GPIO group to assign to a
+    different function.
+-   `function` - A chip-specific function number. Only used if the EC chipset
+    provides multiple alternate functions in addition to GPIO (e.g. pin can be
+    UART, I2C, SPI, or GPIO). The permitted values for this parameter vary based
+    on the EC chipset type.
+    -   STM32 - 0 to 7
+    -   Maxim - 1 to 3
+    -   Microchip - 0 to 3
+    -   MediaTek - 0 to 7
+    -   All others (Nuvton, ITE, TI Stellaris, ) only support one alternate
+        function per pin, so this parameter should be set to 0.
+-   `module` - One of the enum module_id values defined in
+    [./include/module_id.h](../../include/module_id.h).
+-   `flags` - Same definition as `GPIO()` macro.
 
 ### Notes
 
 At runtime there are two mechanisms for switching a pin between GPIO mode and
 alternate function mode.
 
-- `gpio_config_module(enum module_id id, int enable)` - Configures all pins
-  matching the module enumeration `id`.
-- `gpio_config_pin(enum module_id id, enum gpio_signal signal, int enable)` -
-  Configures a single pin matching the GPIO enumeration `signal`.
+-   `gpio_config_module(enum module_id id, int enable)` - Configures all pins
+    matching the module enumeration `id`.
+-   `gpio_config_pin(enum module_id id, enum gpio_signal signal, int enable)` -
+    Configures a single pin matching the GPIO enumeration `signal`.
 
 For both routines, if `enable` is 1, then the corresponding pins are configured
-for alternate mode operation.  If `enable` is 0, then the corresponding pins are
+for alternate mode operation. If `enable` is 0, then the corresponding pins are
 configure for GPIO mode.
 
 `gpio_config_module()` is automatically called at runtime for all enabled
 interfaces (I2C, SPI, UART, etc). You can use `gpio_config_pin()` to temporarily
 configure a pin for GPIO operation, and to restore the original alternate
-function.  The I2C bus error recovery employs this mechanism to temporarily
+function. The I2C bus error recovery employs this mechanism to temporarily
 driver the I2C SCL and SDA signals to known states, without interference by the
 I2C controller in the EC chipset.
 
@@ -132,8 +134,6 @@ The general recipe for overriding alternate functions is shown below.
     gpio_config_pin(MODULE_I2C, GPIO_I2C1_SDA, 1);
 ```
 
-
-
 ### Example
 
 ![ALTERNATE Example]
@@ -148,8 +148,13 @@ ALTERNATE(PIN_MASK(B, BIT(4) | BIT(5)), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P
      appending "export/png" to the Google Drive link. -->
 
 <!-- https://docs.google.com/drawings/d/18cWTYQRRCpypYDOLlvKQJTObwcj6wOjUga02B0oZXBg -->
+
 [GPIO Example]: ../images/gpio_example.png
+
 <!-- https://docs.google.com/drawings/d/1X6p5XfB6BBmUUKCrwOg56Bz6LZj9P_WPQXsOdk-OIiI -->
+
 [GPIO_INT Example]: ../images/gpio_int_example.png
+
 <!-- https://docs.google.com/drawings/d/1-kroVezQuA_KdQLzqYPs8u94EBg37z3k6lKzkSLRv-0 -->
+
 [ALTERNATE Example]: ../images/alternate_example.png
diff --git a/docs/configuration/i2c.md b/docs/configuration/i2c.md
index 92bfe7ad0a..36464bb371 100644
--- a/docs/configuration/i2c.md
+++ b/docs/configuration/i2c.md
@@ -6,7 +6,7 @@ The I2C options are prefixed with `CONFIG_I2C*`. Evaluate whether each option is
 appropriate to add to your board.
 
 A typical EC and board should at a minimum set `CONFIG_I2C` and
-`CONFIG_I2C_MASTER`.
+`CONFIG_I2C_CONTROLLER`.
 
 ## Feature Parameters
 
@@ -14,10 +14,10 @@ The following parameters control the behavior of the I2C library. [config.h]
 defines a reasonable default value, but you may need to change the default value
 for your board.
 
-- `CONFIG_I2C_CHIP_MAX_READ_SIZE <bytes>`
-- `CONFIG_I2C_NACK_RETRY_COUNT <count>`
-- `CONFIG_I2C_EXTRA_PACKET_SIZE <bytes>` - Only used on STM32 EC's if
-  `CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS` is defined.
+-   `CONFIG_I2C_CHIP_MAX_TRANSFER_SIZE <bytes>`
+-   `CONFIG_I2C_NACK_RETRY_COUNT <count>`
+-   `CONFIG_I2C_EXTRA_PACKET_SIZE <bytes>` - Only used on STM32 EC's if
+    `CONFIG_HOSTCMD_I2C_ADDR_FLAGS` is defined.
 
 ## GPIOs and Alternate Pins
 
@@ -28,7 +28,7 @@ recovery actions using bit-banging without involvement by the EC-specific I2C
 device driver.
 
 You also need to define the alternate function assignment for all I2C pins using
-the `ALTERNATE()` macro.  This step can be skipped for any pins that default to
+the `ALTERNATE()` macro. This step can be skipped for any pins that default to
 I2C functionality.
 
 Note that many I2C buses only support 1.8V operation. This is determined by I2C
@@ -42,12 +42,12 @@ macros.
 
 ## Data Structures
 
-- `const struct i2c_port_t i2c_ports[]` - This array should be defined in your
-  baseboard.c or board.c file.  This array defines the mapping of internal I2C
-  port numbers used by the I2C library to the physical I2C ports connected to
-  the EC.
-- `const unsigned int i2c_port_used = ARRAY_SIZE(i2c_ports)` - Defines the
-  number of internal I2C ports accessible by the I2C library.
+-   `const struct i2c_port_t i2c_ports[]` - This array should be defined in your
+    baseboard.c or board.c file. This array defines the mapping of internal I2C
+    port numbers used by the I2C library to the physical I2C ports connected to
+    the EC.
+-   `const unsigned int i2c_port_used = ARRAY_SIZE(i2c_ports)` - Defines the
+    number of internal I2C ports accessible by the I2C library.
 
 ## Tasks
 
@@ -57,14 +57,14 @@ None required by this feature.
 
 ### Console Commands
 
-- `i2cscan` - Provides a quick look of all I2C devices found on all configured
-  buses.
-- `i2cxfer` - Allows you to read and write individual registers on an I2C
-  device.
+-   `i2cscan` - Provides a quick look of all I2C devices found on all configured
+    buses.
+-   `i2cxfer` - Allows you to read and write individual registers on an I2C
+    device.
 
-For runtime troubleshooting of an I2C device, enable and the [I2C
-tracing](../i2c-debugging.md) module to log all I2C transactions initiated by
-the EC code.
+For runtime troubleshooting of an I2C device, enable and the
+[I2C tracing](../i2c-debugging.md) module to log all I2C transactions initiated
+by the EC code.
 
 ## Example
 
@@ -72,8 +72,8 @@ The image below shows the I2C bus assignment for the Volteer reference board.
 
 ![I2C Example]
 
-The `gpio.inc` file for Volteer defines both `GPIO()` and `ALTERNATE()` entries for
-all I2C buses used in the design.
+The `gpio.inc` file for Volteer defines both `GPIO()` and `ALTERNATE()` entries
+for all I2C buses used in the design.
 
 ```c
 /* I2C pins - Alternate function below configures I2C module on these pins */
@@ -101,17 +101,17 @@ ALTERNATE(PIN_MASK(B, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)
 
 The `i2c_ports[]` array requires the `.port` field to be assigned to an EC
 chipset specific enumeration. For the NPCx7 I2C bus names are defined in
-[./chip/npcx/registers.h]. The Volteer `baseboard.h` file creates a mapping
-from the schematic net name to the NPCx7 I2C bus enumeration.
+[./chip/npcx/registers.h]. The Volteer `baseboard.h` file creates a mapping from
+the schematic net name to the NPCx7 I2C bus enumeration.
 
 ```c
 #define CONFIG_I2C
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_1_MIX	NPCX_I2C_PORT3_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
+#define I2C_PORT_SENSOR     NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0     NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1     NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_1_MIX  NPCX_I2C_PORT3_0
+#define I2C_PORT_POWER      NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM     NPCX_I2C_PORT7_0
 ```
 
 The last piece for I2C configuration is to create the `i2c_ports[]` array using
@@ -120,56 +120,56 @@ the macros and enumerations added to `baseboard.h` and `gpio.inc`.
 ```c
 /* I2C port map configuration */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C0_SENSOR_SCL,
-		.sda = GPIO_EC_I2C0_SENSOR_SDA,
-		.flags = 0,
-	},
-	{
-		.name = "usb_c0",
-		.port = I2C_PORT_USB_C0,
-		/*
-		 * I2C buses used for PD communication must be set for 400 kbps
-		 * or greater. Set to the maximum speed supported by all devices.
-		 */
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C1_USB_C0_SCL,
-		.sda = GPIO_EC_I2C1_USB_C0_SDA,
-	},
-	{
-		.name = "usb_c1",
-		.port = I2C_PORT_USB_C1,
-		/*
-		 * I2C buses used for PD communication must be set for 400 kbps
-		 * or greater. Set to the maximum speed supported by all devices.
-		 */
-		.scl = GPIO_EC_I2C2_USB_C1_SCL,
-		.sda = GPIO_EC_I2C2_USB_C1_SDA,
-	},
-	{
-		.name = "usb_1_mix",
-		.port = I2C_PORT_USB_1_MIX,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C3_USB_1_MIX_SCL,
-		.sda = GPIO_EC_I2C3_USB_1_MIX_SDA,
-	},
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C5_POWER_SCL,
-		.sda = GPIO_EC_I2C5_POWER_SDA,
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C7_EEPROM_SCL,
-		.sda = GPIO_EC_I2C7_EEPROM_SDA,
-	},
+    {
+        .name = "sensor",
+        .port = I2C_PORT_SENSOR,
+        .kbps = 400,
+        .scl = GPIO_EC_I2C0_SENSOR_SCL,
+        .sda = GPIO_EC_I2C0_SENSOR_SDA,
+        .flags = 0,
+    },
+    {
+        .name = "usb_c0",
+        .port = I2C_PORT_USB_C0,
+        /*
+         * I2C buses used for PD communication must be set for 400 kbps
+         * or greater. Set to the maximum speed supported by all devices.
+         */
+        .kbps = 1000,
+        .scl = GPIO_EC_I2C1_USB_C0_SCL,
+        .sda = GPIO_EC_I2C1_USB_C0_SDA,
+    },
+    {
+        .name = "usb_c1",
+        .port = I2C_PORT_USB_C1,
+        /*
+         * I2C buses used for PD communication must be set for 400 kbps
+         * or greater. Set to the maximum speed supported by all devices.
+         */
+        .scl = GPIO_EC_I2C2_USB_C1_SCL,
+        .sda = GPIO_EC_I2C2_USB_C1_SDA,
+    },
+    {
+        .name = "usb_1_mix",
+        .port = I2C_PORT_USB_1_MIX,
+        .kbps = 100,
+        .scl = GPIO_EC_I2C3_USB_1_MIX_SCL,
+        .sda = GPIO_EC_I2C3_USB_1_MIX_SDA,
+    },
+    {
+        .name = "power",
+        .port = I2C_PORT_POWER,
+        .kbps = 100,
+        .scl = GPIO_EC_I2C5_POWER_SCL,
+        .sda = GPIO_EC_I2C5_POWER_SDA,
+    },
+    {
+        .name = "eeprom",
+        .port = I2C_PORT_EEPROM,
+        .kbps = 400,
+        .scl = GPIO_EC_I2C7_EEPROM_SCL,
+        .sda = GPIO_EC_I2C7_EEPROM_SDA,
+    },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 ```
@@ -184,21 +184,20 @@ different speeds based on the BOARD_VERSION in [CBI]. For example board version
 operation. `I2C_PORT_FLAG_DYNAMIC_SPEED` is not used to change the I2C bus
 frequency on the fly depending on the addressed slave device.
 
-An example of changing the I2C bus frequency from the [Kodama
-board](../../board/kodama/board.c) is shown below.
+An example of changing the I2C bus frequency from the
+[Kodama board](../../board/kodama/board.c) is shown below.
 
 ```c
 static void board_i2c_init(void)
 {
-	if (board_get_version() < 2)
-		i2c_set_freq(1,  I2C_FREQ_100KHZ);
+    if (board_get_version() < 2)
+        i2c_set_freq(1,  I2C_FREQ_100KHZ);
 }
 DECLARE_HOOK(HOOK_INIT, board_i2c_init, HOOK_PRIO_INIT_I2C);
 ```
 
-
 [config.h]: ../new_board_checklist.md#config_h
 [./chip/npcx/registers.h]: ../../chip/npcx/registers.h
 [./include/i2c.h]: ../../include/i2c.h
 [I2C Example]: ../images/i2c_example.png
-[CBI]: https://chromium.googlesource.com/chromiumos/docs/+/master/design_docs/cros_board_info.md
+[CBI]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/design_docs/cros_board_info.md
diff --git a/docs/configuration/keyboard.md b/docs/configuration/keyboard.md
index f2dc585e1b..8398fefbde 100644
--- a/docs/configuration/keyboard.md
+++ b/docs/configuration/keyboard.md
@@ -8,23 +8,23 @@ appropriate to add to `baseboard.h` or `board.h`.
 Your board should select only one of these options to configure the protocol
 used to send keyboard events to the AP.
 
-- `CONFIG_KEYBOARD_PROTOCOL_8042` - Systems with an x86 AP use the 8042
-  protocol.
-- `CONFIG_KEYBOARD_PROTOCOL_MKBP` - Systems without an x86 AP (e.g. ARM)
-  typically use the MKBP protocol.
+-   `CONFIG_KEYBOARD_PROTOCOL_8042` - Systems with an x86 AP use the 8042
+    protocol.
+-   `CONFIG_KEYBOARD_PROTOCOL_MKBP` - Systems without an x86 AP (e.g. ARM)
+    typically use the MKBP protocol.
 
 ## Feature Parameters
 
-- `CONFIG_KEYBOARD_KSO_BASE <pin>` - Evaluate whether this parameter is required
-  by your board.
+-   `CONFIG_KEYBOARD_KSO_BASE <pin>` - Evaluate whether this parameter is
+    required by your board.
 
 ## GPIOs and Alternate Pins
 
 Define `ALTERNATE()` pin entries for all keyboard matrix signals, to connect the
 signals to the keyboard controller of the EC chipset.
 
-Note that KSO_02 is purposely not configured for for alternate mode. See the [H1
-Special Requirements](#H1-Special-Requirements) below for details.
+Note that KSO_02 is purposely not configured for for alternate mode. See the
+[H1 Special Requirements](#H1-Special-Requirements) below for details.
 
 ```c
 /* Example Keyboard pin setup */
@@ -42,8 +42,8 @@ macros.
 
 ## Data structures
 
-- `struct keyboard_scan_config keyscan_config` - This must be defined if the
-  `CONFIG_KEYBOARD_BOARD_CONFIG` option is defined.
+-   `struct keyboard_scan_config keyscan_config` - This can be used to customize
+    the keyboard scanner (e.g. scan frequency, debounce duration, etc.).
 
 ## Tasks
 
@@ -65,27 +65,23 @@ priority is lower than the `HOSTCMD` task.
 
 ## Additional Notes
 
-- If you're including keyboard support, you should also define
-  `CONFIG_CMD_KEYBOARD` to enable keyboard debug commands from the EC console.
-- `CONFIG_KEYBOARD_PROTOCOL_MKBP` automatically enables `CONFIG_MKBP_EVENT`.
-- Boards that enable `CONFIG_KEYBOARD_PROTOCOL_8042` will often also define
-  `CONFIG_MKBP_EVENT` for sensor events. In this case only motion sensor data is
-  reported using the MKBP protocol, keyboard events are provided using the 8042
-  protocol. Refer to [Configuring Sensors](./motion_sensors.md) for more
-  information.
+-   If you're including keyboard support, you should also define
+    `CONFIG_CMD_KEYBOARD` to enable keyboard debug commands from the EC console.
+-   `CONFIG_KEYBOARD_PROTOCOL_MKBP` automatically enables `CONFIG_MKBP_EVENT`.
+-   Boards that enable `CONFIG_KEYBOARD_PROTOCOL_8042` will often also define
+    `CONFIG_MKBP_EVENT` for sensor events. In this case only motion sensor data
+    is reported using the MKBP protocol, keyboard events are provided using the
+    8042 protocol. Refer to [Configuring Sensors](./motion_sensors.md) for more
+    information.
 
 ### H1 Special Requirements
+
 On Boards that use the H1 secure microcontroller, one KSI (keyboard scan input)
 signal and one KSO (keyboard scan output) signal are routed through the H1
 microcontroller. There are additional GPIO and configuration options that must
-be enabled in this case.
-- The KSO_02/COL2 signal is always inverted. Explicitly configure the GPIO to
-  default low.
-  ```c
-  GPIO(KBD_KSO2, PIN(1, 7), GPIO_OUT_LOW) /* KSO_02 inverted */
-  ```
-- Add the define `CONFIG_KEYBOARD_COL2_INVERTED` to `baseboard.h` or `board.h`.
-- If required by the board, define one of the following options to configure the
-  KSI pin routed to the H1 microcontroller.
-    - `CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2`
-    - `CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI3`
+be enabled in this case. - The KSO_02/COL2 signal is always inverted. Explicitly
+configure the GPIO to default low. `c GPIO(KBD_KSO2, PIN(1, 7), GPIO_OUT_LOW) /*
+KSO_02 inverted */` - Add the define `CONFIG_KEYBOARD_COL2_INVERTED` to
+`baseboard.h` or `board.h`. - If required by the board, define one of the
+following options to configure the KSI pin routed to the H1 microcontroller. -
+`CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2` - `CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI3`
diff --git a/docs/configuration/leds.md b/docs/configuration/leds.md
index 72a548a306..c4fe7894af 100644
--- a/docs/configuration/leds.md
+++ b/docs/configuration/leds.md
@@ -2,13 +2,13 @@
 
 LEDs provide status about the following:
 
-- Dedicated battery state/charging state
-- Chromebook power
-- Adapter power
-- Left side USB-C port (battery state/charging state)
-- Right side USB-C port (battery state/charging state)
-- Recovery mode
-- Debug mode
+-   Dedicated battery state/charging state
+-   Chromebook power
+-   Adapter power
+-   Left side USB-C port (battery state/charging state)
+-   Right side USB-C port (battery state/charging state)
+-   Recovery mode
+-   Debug mode
 
 LEDs can be configured as simple GPIOs, with on/off control only, or as PWM with
 adjustment brightness and color.
@@ -18,23 +18,21 @@ adjustment brightness and color.
 In [config.h], search for options that start with `CONFIG_LED*` and evaluate
 whether each option is appropriate to add to `baseboard.h` or `board.h`.
 
-- `CONFIG_LED_COMMON` - Should be defined for both GPIO and PWM style LEDs.
-- `CONFIG_LED_ONOFF_STATES` - used for GPIO controlled LEDs
-- `CONFIG_LED_PWM` - used for PWM controlled LEDs.  You must also define
-  `CONFIG_PWM` when using PWM controlled LEDs.
+-   `CONFIG_LED_COMMON` - Should be defined for both GPIO and PWM style LEDs.
+-   `CONFIG_LED_ONOFF_STATES` - used for GPIO controlled LEDs
+-   `CONFIG_LED_PWM` - used for PWM controlled LEDs. You must also define
+    `CONFIG_PWM` when using PWM controlled LEDs.
 
 ## Feature Parameters
 
-- `CONFIG_LED_PWM_COUNT <count>` - Must be defined when using PWM LEDs
+-   `CONFIG_LED_PWM_COUNT <count>` - Must be defined when using PWM LEDs
 
 Override the following parameters when using PWM LEDs if you don't want to use
-the recommended LED color settings.
-- `CONFIG_LED_PWM_CHARGE_COLOR <ec_led_color>`
-- `CONFIG_LED_PWM_NEAR_FULL_COLOR <ec_led_color>`
-- `CONFIG_LED_PWM_CHARGE_ERROR_COLOR <ec_led_color>`
-- `CONFIG_LED_PWM_SOC_ON_COLOR <ec_led_color>`
-- `CONFIG_LED_PWM_SOC_SUSPEND_COLOR <ec_led_color>`
-- `CONFIG_LED_PWM_LOW_BATT_COLOR <ec_led_color>`
+the recommended LED color settings. - `CONFIG_LED_PWM_CHARGE_COLOR
+<ec_led_color>` - `CONFIG_LED_PWM_NEAR_FULL_COLOR <ec_led_color>` -
+`CONFIG_LED_PWM_CHARGE_ERROR_COLOR <ec_led_color>` -
+`CONFIG_LED_PWM_SOC_ON_COLOR <ec_led_color>` - `CONFIG_LED_PWM_SOC_SUSPEND_COLOR
+<ec_led_color>` - `CONFIG_LED_PWM_LOW_BATT_COLOR <ec_led_color>`
 
 ## GPIOs and Alternate Pins
 
@@ -47,20 +45,18 @@ For PWM LEDs, configure the `ALTERNATE()` macro, setting the module type to
 
 ## Data structures
 
-For GPIO based LEDs:
-- `struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES]` -
-  Must be defined when `CONFIG_LED_ONOFF_STATES` is used. Defines the LED states
-  for the platform for various charging states.
-
-For PWM based LEDs:
-- `const enum ec_led_id supported_led_ids[]` - Defines the LED type for all PWM
-  LEDs in the system.  See [./include/ec_commands.h] for a description of the
-  supported LED types.
-- `struct pwm_led led_color_map[]` - Defines the PWM intensity of the individual
-  LEDs to generate the corresponding color. This table allows for custom tuning
-  of the LED brightness and color.
-- `const struct pwm_channels[]` - Configures the PWM module, refer to the
-  [Configuring PWM](./pwm.md) section for details.
+For GPIO based LEDs: - `struct led_descriptor
+led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES]` - Must be defined when
+`CONFIG_LED_ONOFF_STATES` is used. Defines the LED states for the platform for
+various charging states.
+
+For PWM based LEDs: - `const enum ec_led_id supported_led_ids[]` - Defines the
+LED type for all PWM LEDs in the system. See [./include/ec_commands.h] for a
+description of the supported LED types. - `struct pwm_led led_color_map[]` -
+Defines the PWM intensity of the individual LEDs to generate the corresponding
+color. This table allows for custom tuning of the LED brightness and color. -
+`const struct pwm_channels[]` - Configures the PWM module, refer to the
+[Configuring PWM](./pwm.md) section for details.
 
 See the [GPIO](./gpio.md) documentation for additional details on the GPIO
 macros.
@@ -73,12 +69,12 @@ None required by this feature.
 
 ### Console Commands
 
-- `pwmduty` - *TODO* add description.
-- `gpioset` - For GPIO based LEDs, this command lets you directly change the
-  state of the LED.
-- `gpioget` - For GPIO based LEDs, this reads current state of the pin. If the
-  current state does not track changes made with `gpioset`, check your board for
-  stuck at high or stuck at low condition.
+-   `pwmduty` - *TODO* add description.
+-   `gpioset` - For GPIO based LEDs, this command lets you directly change the
+    state of the LED.
+-   `gpioget` - For GPIO based LEDs, this reads current state of the pin. If the
+    current state does not track changes made with `gpioset`, check your board
+    for stuck at high or stuck at low condition.
 
 If you're having problems with a PWM LED, try reconfiguring the pin as a GPIO to
 verify the board operation independent of the PWM module.
@@ -89,4 +85,4 @@ LED driver chips are used to control the LCD panel backlight. The backlight
 control is separate from the platform LEDs.
 
 [config.h]: ../new_board_checklist.md#config_h
-[./include/ec_commands.h]: ../../include/ec_commands.h
\ No newline at end of file
+[./include/ec_commands.h]: ../../include/ec_commands.h
diff --git a/docs/configuration/motion_sensors.md b/docs/configuration/motion_sensors.md
index 4dac939b10..6e84fc3307 100644
--- a/docs/configuration/motion_sensors.md
+++ b/docs/configuration/motion_sensors.md
@@ -2,12 +2,12 @@
 
 EC sensors are used for the following capabilities:
 
-- Accelerometers in base and lid measure lid angle to toggle between laptop and
-  tablet modes.
-- Ambient light sensors control display backlight level.
-- All sensor types, including gyroscope, e-compass, and pressure, are used by
-  Android apps.
-- Special sync sensor type, synchronizes sensor events with AP.
+-   Accelerometers in base and lid measure lid angle to toggle between laptop
+    and tablet modes.
+-   Ambient light sensors control display backlight level.
+-   All sensor types, including gyroscope, e-compass, and pressure, are used by
+    Android apps.
+-   Special sync sensor type, synchronizes sensor events with AP.
 
 *TODO* - there is good content available in the most recent [Chrome EC] overview
 presentation that can be added here.
@@ -20,13 +20,12 @@ presentation that can be added here.
 
 *TODO*
 
-
 ## GPIOs and Alternate Pins
 
 *TODO*
 
-- `GPIO_EC_INT_L` - Output from the EC, driven low to indicate an event on the
-  EC is ready for servicing by the AP.
+-   `GPIO_EC_INT_L` - Output from the EC, driven low to indicate an event on the
+    EC is ready for servicing by the AP.
 
 ## Data Structures
 
@@ -49,4 +48,3 @@ presentation that can be added here.
 *TODO*
 
 [Chrome EC]: https://docs.google.com/presentation/d/1Y3PwNSnCQoCqDfL5rYqfaBP_ZqbMOTw_x83_ry4cro8/view#slide=id.g63bdbcea4b_0_27
-
diff --git a/docs/core_runtime.md b/docs/core_runtime.md
index 9d81b807be..9599521a6f 100644
--- a/docs/core_runtime.md
+++ b/docs/core_runtime.md
@@ -1,43 +1,38 @@
-Chromium OS Embedded Controller runtime
-=======================================
+# Chromium OS Embedded Controller Runtime
 
-Design principles
------------------
+## Design Principles
 
-  1. Never do at runtime what you can do at compile time
-The goal is saving flash space and computations.
-Compile-time configuration until you really need to switch at runtime.
+1.  Never do at runtime what you can do at compile time The goal is saving flash
+    space and computations. Compile-time configuration until you really need to
+    switch at runtime.
 
-  2. Real-time: guarantee low latency (eg < 20 us)
-no interrupt disabling ...
-bounded code in interrupt handlers.
+2.  Real-time: guarantee low latency (eg < 20 us) no interrupt disabling ...
+    bounded code in interrupt handlers.
 
-  3. Keep it simple: design for the subset of microcontroller we use
-targeted at 32-bit single core CPU
-for small systems : 4kB to 64kB data RAM, possibly execute-in-place from flash.
+3.  Keep it simple: design for the subset of microcontroller we use targeted at
+    32-bit single core CPU for small systems : 4kB to 64kB data RAM, possibly
+    execute-in-place from flash.
 
-Execution contexts
-------------------
+## Execution Contexts
 
-This is a pre-emptible runtime with static tasks.
-It has only 2 possible execution contexts:
+This is a pre-emptible runtime with static tasks. It has only 2 possible
+execution contexts:
 
-- the regular [tasks](#tasks)
-- the [interrupt handlers](#interrupts)
+-   the regular [tasks](#tasks)
+-   the [interrupt handlers](#interrupts)
 
 The initial startup is an exception as described in the
-[dedicated paragraph](#Startup).
+[dedicated paragraph](#startup).
 
-### tasks
+### Tasks
 
-The tasks are statically defined at compile-time.
-They are described for each *board* in the
-[board/$board/ec.tasklist](../board/host/ec.tasklist) file.
+The tasks are statically defined at compile-time. They are described for each
+*board* in the [board/$board/ec.tasklist](../board/host/ec.tasklist) file.
 
 They also have a static fixed priority implicitly defined at compile-time by
 their order in the [ec.tasklist](../board/host/ec.tasklist) file (the top-most
-one being the lowest priority aka *task* *1*).
-As a consequence, two different tasks cannot have the same priority.
+one being the lowest priority aka *task* *1*). As a consequence, two different
+tasks cannot have the same priority.
 
 In order to store its context, each task has its own stack whose (*small*) size
 is defined at compile-time in the [ec.tasklist](../board/host/ec.tasklist) file.
@@ -47,91 +42,90 @@ priority tasks, see the [preemption section](#scheduling-and-preemption) for
 details and the [locking section](#locking-and-atomicity) for the few cases
 where you need to avoid it.
 
-### interrupts
+### Interrupts
 
-The hardware interrupt requests are connected to the interruption handling
-*C* routines declared by the `DECLARE_IRQ` macros, through some chip/core
-specific mechanisms (e.g. depending whether we have a vectored interrupt
-controller, slave interrupt controllers...)
+The hardware interrupt requests are connected to the interruption handling *C*
+routines declared by the `DECLARE_IRQ` macros, through some chip/core specific
+mechanisms (e.g. depending on whether we have a vectored interrupt controller,
+slave interrupt controllers...)
 
 The interrupts can be nested (ie interrupted by a higher priority interrupt).
 All the interrupt vectors are assigned a priority as defined in their
 `DECLARE_IRQ` macro. The number of available priority level is
 architecture-specific (e.g. 4 on Cortex-M0, 8 on Cortex-M3/M4) and several
 interrupt handlers can have the same priority. An interrupt handler can only be
-interrupted by an handler having a priority **strictly** **greater** than
-its own.
+interrupted by a handler having a priority **strictly** **greater** than its
+own.
 
-In most cases, the exceptions (e.g data/prefetch aborts, software interrupt) can
-be seen as interrupts with a priority strictly greater than all IRQ vectors.
-So they can interrupt any IRQ handler using the same nesting mechanism.
-All fatal exceptions should ultimately lead to a reboot.
+In most cases, the exceptions (e.g., data/prefetch aborts, software interrupt)
+can be seen as interrupts with a priority strictly greater than all IRQ vectors.
+So they can interrupt any IRQ handler using the same nesting mechanism. All
+fatal exceptions should ultimately lead to a reboot.
 
 ### Events
 
-Each task has a *pending* events bitmap[1] implemented as a 32-bit word.
-Several events are pre-defined for all tasks, the most significant bits on the
-32-bit bitmap are reserved for them : the timer pending event on bit 31
-([see the corresponding section](#Timers)), the requested task wake (bit 29),
-the event to kick the waiters on a mutex (bit 30), along with a few hardware
-specific events.
-The 19 least significant bits are available for task-specific meanings.
+Each task has a *pending* events bitmap[1] implemented as a 32-bit word. Several
+events are pre-defined for all tasks, the most significant bits on the 32-bit
+bitmap are reserved for them : the timer pending event on bit 31
+([see the corresponding section](#time)), the requested task wake (bit 29), the
+event to kick the waiters on a mutex (bit 30), along with a few hardware
+specific events. The 19 least significant bits are available for task-specific
+meanings.
 
 Those event bits are used in inter-task communication and scheduling mechanism,
 other tasks **and** interrupt handlers can atomically set them to request
 specific actions from the task. Therefore, the presence of pending events in a
-task bitmap has an impact on its scheduling as described in the [scheduling
-section](#scheduling-and-preemption).
-These requests are done using the `task_set_event()` and `task_wake()`
-primitives.
+task bitmap has an impact on its scheduling as described in the
+[scheduling section](#scheduling-and-preemption). These requests are done using
+the `task_set_event()` and `task_wake()` primitives.
 
 The two typical use-cases are:
 
-- a task sends a message to another task (simply use some common memory
-  structures [see explanation](#single-address-space) and want it to process
-  it now.
-- an hardware IRQ occurred and we need to do some long processing to respond to
-  it (e.g. an I2C transaction). The associated interrupt handler cannot do it
-  (for latency reason), so it will raise an event to ask a task to do it.
+-   a task sends a message to another task (simply use some common memory
+    structures [see explanation](#single-address-space)) and want it to process
+    it now.
+-   a hardware IRQ occurred, and we need to do some long processing to respond
+    to it (e.g. an I2C transaction). The associated interrupt handler cannot do
+    it (for latency reason), so it will raise an event to ask a task to do it.
 
 The task code chooses to consume them (or a subset of them) when it's running
 through the `task_wait_event()` and `task_wait_event_mask()` primitives.
 
-### Scheduling and preemption
+### Scheduling and Preemption
 
-The system has a global bitmap[1] called `tasks_ready` containing one bit
-per task and indicating whether or not it is *ready* *to* *run*
-(ie want/need to be scheduled).
-The task ready bit can only be cleared when it's calling itself one of the
-functions explicitly triggering a re-scheduling (e.g. `task_wait_event()`
-or `task_set_event()`) **and** it has no pending event.
-The task ready bit is set by any task or interrupt handler setting an event
-bit for the task (ie `task_set_event()`).
+The system has a global bitmap[1] called `tasks_ready` containing one bit per
+task and indicating whether it is *ready* *to* *run* (ie want/need to be
+scheduled). The task ready bit can only be cleared when it's calling itself one
+of the functions explicitly triggering a re-scheduling (e.g. `task_wait_event()`
+or `task_set_event()`) **and** it has no pending event. The task ready bit is
+set by any task or interrupt handler setting an event bit for the task (ie
+`task_set_event()`).
 
-The scheduling is based on (and *only* on) the `tasks_ready` bitmap
-(which is derived from all the events bitmap of the tasks as explained above).
+The scheduling is based on (and *only* on) the `tasks_ready` bitmap (which is
+derived from all the events bitmap of the tasks as explained above).
 
 Then, the scheduling policy to find which task should run is just finding the
-most significant bit set in the tasks_ready bitmap and schedule the corresponding task.
-
-Important note: the re-scheduling happens **only** when we are exiting the interrupt context.
-It is done in a non-preemptible context (likely with the highest priority).
-Indeed, a re-scheduling is actually needed only when the highest priority task ready has changed.
-There are 3 distinct cases where this can happen:
-
-- an interrupt handler sets a new event for a task.
-  In this case, `task_set_event` will detect that it is executed in interrupt
-  context and record in the `need_resched_or_profiling` variable that it might
-  need to re-schedule at interrupt return. When the current interrupt is going
-  to return, it will see this bit and decide to take the slow path making a new
-  scheduling decision and eventually a context switch instead of the fast path
-  returning to the interrupt task.
-- a task sets an event on another task.
-  The runtime will trigger a software interrupt to force a re-scheduling at its
-  exit.
-- the running task voluntarily relinguish its current execution rights by
-  calling `task_wait_event()` or a similar function.
-  This will call the software interrupt similarly to the previous case.
+most significant bit set in the tasks_ready bitmap and schedule the
+corresponding task.
+
+Important note: the re-scheduling happens **only** when we are exiting the
+interrupt context. It is done in a non-preemptible context (likely with the
+highest priority). Indeed, a re-scheduling is actually needed only when the
+highest priority task ready has changed. There are 3 distinct cases where this
+can happen:
+
+-   an interrupt handler sets a new event for a task. In this case,
+    `task_set_event` will detect that it is executed in interrupt context and
+    record in the `need_resched_or_profiling` variable that it might need to
+    re-schedule at interrupt return. When the current interrupt is going to
+    return, it will see this bit and decide to take the slow path making a new
+    scheduling decision and eventually a context switch instead of the fast path
+    returning to the interrupt task.
+-   a task sets an event on another task. The runtime will trigger a software
+    interrupt to force a re-scheduling at its exit.
+-   the running task voluntarily relinquish its current execution rights by
+    calling `task_wait_event()` or a similar function. This will call the
+    software interrupt similarly to the previous case.
 
 On the re-scheduling path, if the highest-priority ready task is not matching
 the currently running one, it will perform a context-switch by saving all the
@@ -139,207 +133,201 @@ processor registers on the current task stack, switch the stack pointer to the
 newly scheduled task, and restore the registers from the previously saved
 context from there.
 
-### hooks and deferred function
+### Hooks and Deferred Functions
 
 The lowest priority task (ie Task 1, aka TASK_ID_HOOKS) is reserved to execute
 repetitive actions and future actions deferred in time without blocking the
 current task or creating a dedicated task (whose stack memory allocation would
 be wasting precious RAM).
 
-The HOOKS task has a list of deferred functions and their next deadline.
-Every time it is waken up, it runs through the list and calls the ones whose
-deadline is expired. Before going back to sleep, it arms a timer to the closest
-deadline.
+The HOOKS task has a list of deferred functions and their next deadline. Every
+time it is woken up, it runs through the list and calls the ones whose deadline
+is expired. Before going back to sleep, it arms a timer to the closest deadline.
 The deferred functions can be created using the `DECLARED_DEFERRED()` macro.
-Similarly the HOOK_SECOND and HOOK_TICK hooks are called periodically by the
-HOOKS task loop (the *tick* duration is platform-defined and shorter than
-the second).
+Similarly, the HOOK_SECOND and HOOK_TICK hooks are called periodically by the
+HOOKS task loop (the *tick* duration is platform-defined and shorter than the
+second).
+
+For examples, of hooks and deferred functions, see the [`hooks` testcases].
 
 Note: be specially careful about priority inversions when accessing resources
 protected by a mutex (e.g. a shared I2C controller) in a deferred function.
-Indeed being the lowest priority task, it might be de-scheduled for long time
-and starve higher priority tasks trying to access the resource given there is
-no priority boosting implemented for this case.
-Also be careful about long delays (> x 100us) in hook or deferred function
-handlers, since those will starve other hooks of execution time. It is better
-to implement a state machine where you set up a subsequent call to a deferred
-function than have a long delay in your handler.
+Indeed, being the lowest priority task, it might be de-scheduled for long time
+and starve higher priority tasks trying to access the resource given there is no
+priority boosting implemented for this case. Also, be careful about long delays
+(> x 100us) in hook or deferred function handlers, since those will starve other
+hooks of execution time. It is better to implement a state machine where you set
+up a subsequent call to a deferred function than have a long delay in your
+handler.
 
-### watchdog
+### Watchdog
 
 The system is always protected against misbehaving tasks and interrupt handlers
 by a hardware watchdog rebooting the CPU when it is not attended.
 
 The watchdog is petted in the HOOKS task, typically by declaring a HOOK_TICK
-doing it as regular intervals. Given this is the lowest priority task,
-this guarantees that all tasks are getting some run time during the watchdog
-period.
+doing it as regular intervals. Given this is the lowest priority task, this
+guarantees that all tasks are getting some run time during the watchdog period.
 
 Note: that's also why one should not sprinkle its code with `watchdog_reload()`
 to paper over long-running routine issues.
 
-To help debugging bad sequences triggering watchdog reboots, most platforms
-implement a warning mechanism defined under `CONFIG_WATCHDOG_HELP`.
-It's a timer firing at the middle of the watchdog period if it hasn't been
-petted by then, and dumping on the console the current state of the execution
-mainly to help finding a stuck task or handler. The normal execution is resumed
-though after this alert.
+To help debug bad sequences triggering watchdog reboots, most platforms
+implement a warning mechanism defined under `CONFIG_WATCHDOG_HELP`. It's a timer
+firing at the middle of the watchdog period if it hasn't been petted by then,
+and dumping on the console the current state of the execution mainly to help
+find a stuck task or handler. The normal execution is resumed though after this
+alert.
 
 ### Startup
 
 The startup sequence goes through the following steps:
 
-- the assembly entry routine clears the .bss (uninitialized data),
-  copies the initialized data (and optionally the code if we are not executing
-  from flash), sets a stack pointer.
-- we can jump to the `main()` C routine at this point.
-- then we go through the hardware pre-init (before we have all the clocks to
- run the peripherals normal) and init routines, in this rough order:
-   memory protection if any, gpios in their default state,
-   prepare the interrupt controller, set the clocks, then timers,
-   enable interrupts, init the debug UART and the watchdog.
-- finally start tasks.
-
-For the tasks startup, initially only the HOOKS task is marked as ready,
-so it is the first to start and can call all the HOOK_INIT handlers performing
-initializations before actually executing any real task code.
-Then all tasks are marked as ready, and the highest priority one is given
-the control.
-
-During all the startup sequence until the control is given the first task,
-we are using a speciak stack called 'system stack' which will be later re-used
-as the interrupts and exception stack.
+-   the assembly entry routine clears the .bss (uninitialized data), copies the
+    initialized data (and optionally the code if we are not executing from
+    flash), sets a stack pointer.
+-   we can jump to the `main()` C routine at this point.
+-   then we go through the hardware pre-init (before we have all the clocks to
+    run the peripherals normal) and init routines, in this rough order: memory
+    protection if any, gpios in their default state, prepare the interrupt
+    controller, set the clocks, then timers, enable interrupts, init the debug
+    UART and the watchdog.
+-   finally, start tasks.
+
+For the tasks startup, initially only the HOOKS task is marked as ready, so it
+is the first to start and can call all the HOOK_INIT handlers performing
+initializations before actually executing any real task code. Then all tasks are
+marked as ready, and the highest priority one is given the control.
+
+During all the startup sequence until the control is given the first task, we
+are using a special stack called 'system stack' which will be later re-used as
+the interrupts and exception stack.
 
 To prepare the first context switch, the code in `task_pre_init()` is stuffing
-all the tasks stacks with a *fake* saved context whose program counter is
-containing the task start address and the stack pointer is pointing to its
-reserved stack space.
+all the tasks stacks with a *fake* saved context whose program counter contains
+the task start address, and the stack pointer is pointing to its reserved stack
+space.
 
-### locking and atomicity
+### Locking and Atomicity
 
-The two main concurrency primitives are lightweight atomic variables and
-heavier mutexes.
+The two main concurrency primitives are lightweight atomic variables and heavier
+mutexes.
 
 The atomic variables are 32-bit integers (which can usually be loaded/stored
 atomically on the architecture we are supporting). The `atomic.h` headers
-include primitives to do atomically various bit and arithmetic operations
-using either load-linked/load-exclusive, store-conditional/store-exclusive
-or simple depending what is available.
+include primitives to do atomically various bit and arithmetic operations using
+either load-linked/load-exclusive, store-conditional/store-exclusive or simple
+depending on what is available.
 
-The mutexes are actually statically allocated binary semaphores.
-In case of contention, they will make the waiting task sleep
-(removing its ready bit) and use the [event mechanism](#Events) to wake-up
-the other waiters on unlocking.
+The mutexes are actually statically allocated binary semaphores. In case of
+contention, they will make the waiting task sleep (removing its ready bit) and
+use the [event mechanism](#events) to wake up the other waiters on unlocking.
 
-Note: the mutexes are NOT triggering any priority boosting to avoid the
-priority inversion phenomenon.
+Note: the mutexes are NOT triggering any priority boosting to avoid the priority
+inversion phenomenon.
 
 Given the runtime is running on single core CPU, spinlocks would be equivalent
-to masking interrupts with `interrupt_disable()` spinlocks, but it's
-strongly discouraged to avoid harming the real-time characterics of the runtime.
+to masking interrupts with `interrupt_disable()` spinlocks, but it's strongly
+discouraged to avoid harming the real-time characteristics of the runtime.
 
-Time
-----
+## Time
 
-### time keeping
+### Time Keeping
 
-In the runtime, the time is accounted everywhere using a
-**64-bit** **microsecond** count since the microcontroller **cold** **boot**.
+In the runtime, the time is accounted everywhere using a **64-bit**
+**microsecond** count since the microcontroller **cold** **boot**.
 
-Note: The runtime has no notion of wall-time/date, even though a few platform have
-an RTC inside the microcontroller.
+Note: The runtime has no notion of wall-time/date, even though a few platforms
+have an RTC inside the microcontroller.
 
 These microsecond timestamps are implemented in the code using the `timestamp_t`
-type and the current timestamp is returned by the `get_time()` function.
+type, and the current timestamp is returned by the `get_time()` function.
 
-The time-keeping is preferably implemented using a 32-bit hardware
-free running counter at 1Mhz plus a 32-bit word in memory keeping track of
-the high word of the 64-bit absolute time. This word is incremented by the
-32-bit timer rollback interrupt.
+The time-keeping is preferably implemented using a 32-bit hardware free running
+counter at 1Mhz plus a 32-bit word in memory keeping track of the high word of
+the 64-bit absolute time. This word is incremented by the 32-bit timer rollback
+interrupt.
 
 Note: as a consequence of this implementation, when the 64-bit timestamp is read
-in interrupt context in an handler having a higher priority than the timer IRQ
+in interrupt context in a handler having a higher priority than the timer IRQ
 (which is somewhat rare), the high 32-bit word might be incoherent (off by one).
 
-### timer event
+### Timer Event
 
-The runtime offers *one* (and only one) timer per task.
-All the task timers are multiplexed on a single hardware timer.
-(can be just a *match* *interrupt* on the free running counter mentioned in the
-[previous paragraph](#time-keeping))
+The runtime offers *one* (and only one) timer per task. All the task timers are
+multiplexed on a single hardware timer. (can be just a *match* *interrupt* on
+the free running counter mentioned in the [previous paragraph](#time-keeping))
 Every time a timer is armed or expired, the runtime finds the task timer having
-the closest deadline and programs it in the hardware to get an interrupt.
-At the same time, it sets the TASK_EVENT_TIMER event in all tasks whose timer
-deadline has expired.
-The next deadline is computed in interrupt context.
+the closest deadline and programs it in the hardware to get an interrupt. At the
+same time, it sets the TASK_EVENT_TIMER event in all tasks whose timer deadline
+has expired. The next deadline is computed in interrupt context.
 
-Note: given each task has a **single** timer which is also used to wake-up the
+Note: given each task has a **single** timer which is also used to wake up the
 task when `task_wait_event()` is called with a timeout, one needs to be careful
 when using directly the `timer_arm()` function because there is an eventuality
 that this timer is still running on the next `task_wait_event()` call, the call
 will fail due to the lack of available timer.
 
-Memory
-------
+## Memory
 
-### Single address space
+### Single Address Space
 
 There is no memory isolation between tasks (ie they all live in the same address
 space). Some architectures implement memory protection mechanism albeit only to
-differentiate executable area (eg `.code`) from writable area (eg `.bss` or
-`.data`) as there is a **single** **privilege** level for all execution contexts.
+differentiate executable area (eg `.code`) from writable area (e.g., `.bss` or
+`.data`) as there is a **single** **privilege** level for all execution
+contexts.
 
-As all the memory is implicitely shared between the task, the inter-task
-communication can be done by simply writing the data structures in memory
-and using events to wake the other task (given we properly thought the concurrent
-accesses on thoses structures).
+As all the memory is implicitly shared between the task, the inter-task
+communication can be done by simply writing the data structures in memory and
+using events to wake the other task (given we properly thought the concurrent
+accesses on those structures).
 
-### heap
+### Heap
 
 The data structure should be statically allocated at compile time.
 
 Note: there is no dynamic allocator available (e.g. `malloc()`), not due to
-impossibility to create one but to avoid the negative side effects of
-having one: ie poor/unpredictable real-time behavior and possible leaks
-leading to a long-tail of failures.
+impossibility to create one but to avoid the negative side effects of having
+one: ie poor/unpredictable real-time behavior and possible leaks leading to a
+long-tail of failures.
 
-- TODO: talk about shared memory
-- TODO: where/how we store *panic* *memory* and *sysjump* *parameters*.
+-   TODO: talk about shared memory
+-   TODO: where/how we store *panic* *memory* and *sysjump* *parameters*.
 
-### stacks
+### Stacks
 
 Each task has its own stack, in addition there is a system stack used for
 startup and interrupts/exceptions.
 
-Note 1: Each task stack is relatively small (e.g. 512 bytes), so one needs to
-be careful about stack usage when implementing features.
+Note 1: Each task stack is relatively small (e.g. 512 bytes), so one needs to be
+careful about stack usage when implementing features.
 
-Note 2: At the same time, the total size of RAM used by stacks is a big chunk
-of the total RAM consumption, so their sizes need to be carefully tuned.
-(please refer to the [debugging paragraph](#debugging) for additional input on
-this topic.
+Note 2: At the same time, the total size of RAM used by stacks is a big chunk of
+the total RAM consumption, so their sizes need to be carefully tuned. (Please
+refer to the [debugging paragraph](#debugging) for additional input on this
+topic.)
 
-## Firmware code organization and multiple copies
+## Firmware Code Organization and Multiple Copies
 
-- TODO: Details the classical RO / RW partitions and how we sysjump.
+-   TODO: Details the classical RO / RW partitions and how we sysjump.
 
-power management
-----------------
+## Power Management
 
-- TODO: talk about the idle task + WFI (note: interrupts are disabled!)
-- TODO: more about low power idle and the sleep-disable bitmap
-- TODO: adjusting the microsecond timer at wake-up
+-   TODO: talk about the idle task + WFI (note: interrupts are disabled!)
+-   TODO: more about low power idle and the sleep-disable bitmap
+-   TODO: adjusting the microsecond timer at wake-up
 
-debugging
----------
+## Debugging
 
-- TODO: our main tool: serial console ...
-(but non-blocking / discard overflow, cflush DO/DONT)
-- TODO: else JTAG stop and go: careful with watchdog and timer
-- TODO: panics and software panics
-- TODO: stack size tuning and canarying
+-   TODO: our main tool: serial console ... (but non-blocking / discard
+    overflow, cflush DO/DONT)
+-   TODO: else JTAG stop and go: careful with watchdog and timer
+-   TODO: panics and software panics
+-   TODO: stack size tuning and canarying
 
+-   TODO: Address the rest of the comments from https://crrev.com/c/445941
 
-- TODO: Address the rest of the comments from https://crrev.com/c/445941
+\[1]: bitmap: array of bits.
 
-[1]: bitmap: array of bits.
+[`hooks` testcases]: ../test/hooks.c
diff --git a/docs/ec-3po-design.md b/docs/ec-3po-design.md
index 56a217849b..79ec3ecf0f 100644
--- a/docs/ec-3po-design.md
+++ b/docs/ec-3po-design.md
@@ -32,21 +32,22 @@ while trying to parse strings from the EC console. This method can be fairly
 fragile as debug output can be interleaved with the console input. A lot of
 items could be improved by switching to this host command packet interface.
 
-* Communicating in packets makes testing easier and more robust.
-  * When FAFT is running, the EC could be in a binary mode where it only
-    communicates in host command packets. These packets are easier to parse,
-    create, and filter on.
-  * With filtering, you get the added bonus of not having unwanted debug output.
-  * It allows us to really test the host command interface which is how the EC
-    talks to the AP anyways.
-* Better testing of existing host command handlers.
-  * By speaking in host command packets, we can reuse the existing host command
-    handlers which is nice since we'll be using the same handlers that are used
-    to respond to the AP.
-* FAFT would no longer have to worry about the console dropping characters.
-  * We can add error checking to the interpreter which would automatically retry
-    errors. This alleviates FAFT from trying to check if the EC had properly
-    received a line of input. (Ctrl+L)
+*   Communicating in packets makes testing easier and more robust.
+    *   When FAFT is running, the EC could be in a binary mode where it only
+        communicates in host command packets. These packets are easier to parse,
+        create, and filter on.
+    *   With filtering, you get the added bonus of not having unwanted debug
+        output.
+    *   It allows us to really test the host command interface which is how the
+        EC talks to the AP anyways.
+*   Better testing of existing host command handlers.
+    *   By speaking in host command packets, we can reuse the existing host
+        command handlers which is nice since we'll be using the same handlers
+        that are used to respond to the AP.
+*   FAFT would no longer have to worry about the console dropping characters.
+    *   We can add error checking to the interpreter which would automatically
+        retry errors. This alleviates FAFT from trying to check if the EC had
+        properly received a line of input. (Ctrl+L)
 
 With better and more reliable tests, we can improve the quality of our EC
 codebase.
@@ -63,15 +64,15 @@ be restricted by the type of chip.
 
 ### A richer EC console
 
-* We could do things like on-the-fly console channel filtering.
-* Coloring specific channels such as "mark all USB PD messages in green".
-* Adding colors in general.
-* Adding temporary console commands.
-* Longer command history which survives EC reboot
-* Searching command history
-* Redirecting debug output to log files (which causes no interleaving of command
-  and debug output)
-* Bang commands (`!foo`)
+*   We could do things like on-the-fly console channel filtering.
+*   Coloring specific channels such as "mark all USB PD messages in green".
+*   Adding colors in general.
+*   Adding temporary console commands.
+*   Longer command history which survives EC reboot
+*   Searching command history
+*   Redirecting debug output to log files (which causes no interleaving of
+    command and debug output)
+*   Bang commands (`!foo`)
 
 ### Better debuggability
 
@@ -80,9 +81,9 @@ such as the keyboard locking up on certain keys or rows. At times like that, it
 would be nice to have an EC console to see what's going on. Other times maybe
 having a servo connected might make the issue not present itself.
 
-* We could do cool things like having an EC console without having to hook up
-  servo.
-* Run `ectool` from the chroot using a PTY interface.
+*   We could do cool things like having an EC console without having to hook up
+    servo.
+*   Run `ectool` from the chroot using a PTY interface.
 
 ## Deployment Strategy
 
@@ -99,28 +100,28 @@ Phase 1 will most likely consist of getting EC-3PO in place in between servo and
 the EC while not modifying the behavior of the console too much. In this phase,
 we can replicate the console interface and achieve the following things.
 
-* Replicate command editing.
-* Save command history.
-* Add error checking to the console commands.
+*   Replicate command editing.
+*   Save command history.
+*   Add error checking to the console commands.
 
 ### Phase 2: Assimilation
 
 Phase 2 will start to introduce the host command packet communication.
 
-* Printing will be done via packets and assembled in EC-3PO.
-* Console commands now are sent using the host command packets.
-  * This will be incremental as console commands are converted.
-* Add debug output filtering and redirection/logging.
+*   Printing will be done via packets and assembled in EC-3PO.
+*   Console commands now are sent using the host command packets.
+    *   This will be incremental as console commands are converted.
+*   Add debug output filtering and redirection/logging.
 
 ### Phase 3: Expansion
 
 Phase 3 will expand the feature set of EC-3PO.
 
-* Add PTY interface to `ectool`.
-* Add on-device console without `servod`.
-* Colored output.
-* Command history search.
-* Bang commands (`!foo`)
+*   Add PTY interface to `ectool`.
+*   Add on-device console without `servod`.
+*   Colored output.
+*   Command history search.
+*   Bang commands (`!foo`)
 
 ## High Level Design & Highlights
 
@@ -132,7 +133,7 @@ UART.](./images/ec-3po-high-level-design.png)
 
 Each host command is a 16-bit command value. Commands which take parameters or
 return response data specify `struct`s for that data. See
-[`include/ec_commands.h`](https://chromium.googlesource.com/chromiumos/platform/ec/+/refs/heads/master/include/ec_commands.h)
+[`include/ec_commands.h`](https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/include/ec_commands.h)
 for the current format of request and replies. Currently, there are no changes
 made to the format of the host request and response structures.
 
@@ -170,12 +171,12 @@ EC-3PO and the EC can perform error checking when sending the commands to the
 EC. This feature would be implemented prior to switching to the binary format.
 The interpreter can package the command in the following manner.
 
-* 2 Ampersands
-* 2 hex digits representing the length of the command
-* 2 hex digits representing the CRC-8 of the command
-* 1 Ampersand
-* The command itself
-* 2 newline characters.
+*   2 Ampersands
+*   2 hex digits representing the length of the command
+*   2 hex digits representing the CRC-8 of the command
+*   1 Ampersand
+*   The command itself
+*   2 newline characters.
 
 This is robust because no commands currently start with `&`. If the EC does not
 see ‘`&&`', then one of the ampersands has been dropped. If the EC doesn't see
@@ -295,10 +296,10 @@ prompt by pressing ‘%' . These were originally added for debug purposes.
 
 ##### Supported Commands
 
-* `loglevel <integer>`
-  * Allows setting the effective loglevel of the console and interpreter.
-* `interrogate <never | always | auto> [enhanced]`
-  * Allows control of when and how often interrogation occurs.
+*   `loglevel <integer>`
+    *   Allows setting the effective loglevel of the console and interpreter.
+*   `interrogate <never | always | auto> [enhanced]`
+    *   Allows control of when and how often interrogation occurs.
 
 ### Interpreter module
 
@@ -323,4 +324,3 @@ Since the interpreter communicates using pipes, it's not necessary that the user
 use the console module. For example, FAFT could directly connect to the
 interpreter and send down commands and receive command responses instead of
 having to deal with the PTY and instead just deal with python objects.
-
diff --git a/docs/ec-3po.md b/docs/ec-3po.md
index 83877374aa..dae7b9babb 100644
--- a/docs/ec-3po.md
+++ b/docs/ec-3po.md
@@ -5,9 +5,9 @@
 ## What is EC-3PO?
 
 EC-3PO is the console interpreter that will one day replace the EC console that
-we have today.  EC-3PO aims to migrate our rich debug console from the EC itself
-to the host.  This allows us to maintain our rich debug console without
-impacting our EC image sizes while also allowing us to add new features.
+we have today. EC-3PO aims to migrate our rich debug console from the EC itself
+to the host. This allows us to maintain our rich debug console without impacting
+our EC image sizes while also allowing us to add new features.
 
 For more information, see [the design doc](./ec-3po-design.md).
 
@@ -42,9 +42,9 @@ apparently, `cu` wants group write permissions. On Ubuntu at least, the PTY is
 created with the `tty` group. If on your machine it's not, then just replace
 `tty` with whatever group it's created with.
 
-1. Create a `tty` group if you don't have one already.
-1. Add root to the `tty` group.
-1. Rerun `cu` with `sudo` and it should work now.
+1.  Create a `tty` group if you don't have one already.
+1.  Add root to the `tty` group.
+1.  Rerun `cu` with `sudo` and it should work now.
 
 ## Why does the console seem "laggier" than before?
 
@@ -57,10 +57,10 @@ delay is unbearable.
 
 To disable the delay:
 
-1. Open the EC console.
-1. Press `%`
-1. Enter `interrogate never`
-1. Then press enter.
+1.  Open the EC console.
+1.  Press `%`
+1.  Enter `interrogate never`
+1.  Then press enter.
 
 \**For `socat` users, due to the line buffered nature, you'll have to just enter
 `%interrogate never`. Notice the lack of the space character between `%` and the
diff --git a/docs/ec-host-command-api.md b/docs/ec-host-command-api.md
new file mode 100644
index 0000000000..007df04e0b
--- /dev/null
+++ b/docs/ec-host-command-api.md
@@ -0,0 +1,69 @@
+# EC Host Command API
+
+## Overview
+
+The EC provices a control channel on an external interface using SPI,
+LPC, or I2C bus. The low level details of the protocol used on this
+interface is captured in [AP-EC-COMM](ap-ec-comm.md).
+
+The entity connected to the other side of this control channel is
+typically the "AP" (application processor) - the main processor of a
+system running a full-blown operating system.
+
+## `ec_commands.h`
+
+The EC implements hundreds of "host commands" (operations) to support
+the AP. These are organized as an opcode and data structures defining
+the input and output data for each opcode. `include/ec_commands.h`
+defines all of the available opcodes and associated data structures.
+
+For example, the `HELLO` host command is defined as:
+
+`#define EC_CMD_HELLO 0x0001`
+
+It takes a `struct ec_params_hello` as input and returns a
+`struct ec_response_hello`.
+
+The vast majority of host commands follow this simple naming pattern,
+but exceptions have crept in over time, generally unintentionally, as
+there is no mechanism to validate that this pattern has been followed.
+Also, implementers must be careful to use the intended combination of
+host commands and data types as there is no mechanism to validate the
+correct combination has been used.
+
+## `ec_cmd_api.h`
+
+`ec_cmd_api.h` extends `ec_commands.h` by providing a function based
+host command API. The `HELLO` host command from the previous example can
+be invoked using a function provided by `ec_cmd_api.h`:
+
+```
+int ec_cmd_hello(CROS_EC_COMMAND_INFO *h,
+                 const struct ec_params_hello *p,
+                 struct ec_response_hello *r)
+```
+
+where `CROS_EC_COMMAND_INFO` is defined by the application for its house-keeping.
+It is intended to be a connection handle or other state information needed by
+the caller to communicate with the EC.
+
+The application also needs to provide an implementation of
+`cros_ec_command` that performs the actual communication with the EC.
+
+```
+int CROS_EC_COMMAND(CROS_EC_COMMAND_INFO *h,
+                    int command, int version,
+                    const void *outdata, int outsize,
+                    void *indata, int insize)
+```
+
+## Maintaining `ec_cmd_api.h`
+
+`ec_cmd_api.h` consists of 2 sections corresponding to the different
+methods used to determine the host command API function signature:
+
+1. This section consists of functions that do not follow a simple
+   pattern and need to be specified explicitly.
+
+2. This section consists of functions that can be generated with the
+   help of template macros.
diff --git a/docs/ec_terms.md b/docs/ec_terms.md
index 4f1b590b1a..0349218e98 100644
--- a/docs/ec_terms.md
+++ b/docs/ec_terms.md
@@ -1,12 +1,13 @@
 # EC Acronyms and Technologies
 
 ## Glossary
-*   **8042 Interface**{#8042}
+
+*   **8042 Interface** {#8042}
 
     Interface for sending keyboard events to the [AP](#ap) and for receiving
     commands from the AP. Only supported by x86 based APs.
 
-*   **ACCEL - Accelerometer**{#accel}
+*   **ACCEL - Accelerometer** {#accel}
 
     A sensor that measures acceleration, typically over 3-axis. Nominally
     provides information about the orientation of a device. On Chromebook 2-in-1
@@ -14,57 +15,62 @@
     the measurements from both accelerometers allows for a precise calculation
     of the lid angle, used to switch between tablet and laptop mode.
 
-*   **ACCELGYRO - Accelerometer/Gyroscope**{#accelgyro}
+*   **ACCELGYRO - Accelerometer/Gyroscope** {#accelgyro}
 
     A combination [accelerometer](#accel) and [gyroscope](#gyro) sensor that
     provides more precise orientation information by measuring both linear and
     rotational motion.
 
-*   **ADC - Analog to Digital Converter**{#adc}
+*   **ADC - Analog to Digital Converter** {#adc}
 
     A sensor that converts an analog voltage to a digital reading.
 
-*   **ALS - Ambient Light Sensor**{#als}
+*   **ALS - Ambient Light Sensor** {#als}
 
     A sensor that measures the ambient light present. Used to automatically
     control the screen and keyboard backlight level.
 
-*   **AP - Application Processor**{#ap}
+*   **AP - Application Processor** {#ap}
 
     The processor on the board that boots and runs ChromeOS.
 
-*   **BAR - Barometer**{#bar}
+*   **BAR - Barometer** {#bar}
 
     A sensor that measures atmospheric pressure.
 
-*   **BC12 - Battery Charging**{#bc12}
+*   **BC12 - Battery Charging** {#bc12}
 
     A device that implements the USB Battery Charging specification, version
     1.2. The complete [BC 1.2 Specification] is available from the USB
     Implementers Forum.
 
-*   **CBI - CROS Board Information**{#cbi}
+*   **CBI - CROS Board Information** {#cbi}
 
     A collection of properties describing the board. This includes board
     version, SKU, model name, and other fields. More details are found in the
     [CrOS Board Info] documentation.
 
-*   **CEC - Consumer Electronics Control**{#cec}
+*   **CEC - Consumer Electronics Control** {#cec}
 
-    A one-wire bidirectional bus.  More details are on the [CEC Wikipedia page].
+    A one-wire bidirectional bus. More details are on the [CEC Wikipedia page].
 
-*   **DPTF - Dynamic Power and Thermal Framework (Intel)**{#dptf}
+*   **DPTF - Dynamic Power and Thermal Framework (Intel)** {#dptf}
 
     Intel's platform based power and thermal management. See the [DPTF Readme]
     for details on the implementation used in ChromeOS.
 
-*   **EC - Embedded Controller**{#ec}
+*   **EC - Embedded Controller** {#ec}
 
     The [MCU](#mcu) used to control the keyboard, battery charging, USB port
     switching, sensor management, and other functions, offloading these tasks
     from the [AP](#ap).
 
-*   **EC-3PO**{#ec-3po}
+*   **ectool** {#ectool}
+
+    The [ectool] is the [AP](#ap) console's CLI for sending commands to the
+    [EC](#ec).
+
+*   **EC-3PO** {#ec-3po}
 
     A replacement of the current UART-based console which moves much of the code
     off the EC into a host tool, reducing the amount of flash space required.
@@ -73,47 +79,47 @@
 
     See the [USB-C documentation](./usb-c.md#emark) for more details.
 
-*   **eSPI - Enhanced Serial Peripheral Interface (Intel)**{#espi}
+*   **eSPI - Enhanced Serial Peripheral Interface (Intel)** {#espi}
 
     Intel's synchronous communication interface between the [AP](#ap) and the
     [EC](#ec). Supports quad I/O mode and clock speeds up to 66 Mhz, providing
     bandwidth up to 264 Mbps. The full [eSPI Specification] is available from
     Intel.
 
-*   **FAFT - Fully Automated Firmware Tests**{#faft}
+*   **FAFT - Fully Automated Firmware Tests** {#faft}
 
     A collection of tests and related infrastructure that exercise and verify
-    capabilities of Chrome OS. See the [FAFT design doc] and [chromium.org
-    documentation](https://www.chromium.org/for-testers/faft) for more details.
-    Replaced [SAFT](#saft).
+    capabilities of Chrome OS. See the [FAFT design doc] and
+    [chromium.org documentation](https://www.chromium.org/for-testers/faft) for
+    more details. Replaced [SAFT](#saft).
 
 *   **GMR - Giant Magnetoresistance Sensor** {#gmr}
 
     A sensor device that detects a magnetic field. These sensors differ from
     [MAG](#mag) sensors, in that they only detect magnetic fields in close
     proximity to the sensor. On Chromebooks, GMR sensors are used to detect when
-    the lid is opened.  On convertible Chromebooks, the GMR sensor also detects
+    the lid is opened. On convertible Chromebooks, the GMR sensor also detects
     tablet mode when lid the is opened a full 360 degrees.
 
-*   **GPIO - General Purpose Input/Output**{#gpio}
+*   **GPIO - General Purpose Input/Output** {#gpio}
 
-    An individual signal that can independently controlled and read.  GPIOs are
+    An individual signal that can independently controlled and read. GPIOs are
     used to enable/disable power rails, drive reset signals, and receive
-    interrupts from devices connected to the EC.  GPIOs may also be connected
-    to [I/O expanders](#ioexpander).
+    interrupts from devices connected to the EC. GPIOs may also be connected to
+    [I/O expanders](#ioexpander).
 
-*   **GYRO - Gyroscope**{#gyro}
+*   **GYRO - Gyroscope** {#gyro}
 
     A sensor that measures angular momentum, providing information about
     rotational motion of the device.
 
-*   **I/O Expander**{#ioexpander}
+*   **I/O Expander** {#ioexpander}
 
     An [I2C](#i2c) peripheral device that provides additional GPIO signals
-    (anywhere from 8 - 32 signals).  GPIOs behind an I/O expander are written
-    and read using I2C register accesses from the I2C controller in the EC.
+    (anywhere from 8 - 32 signals). GPIOs behind an I/O expander are written and
+    read using I2C register accesses from the I2C controller in the EC.
 
-*   **I2C - Inter-Integrated Circuit**{#i2c}
+*   **I2C - Inter-Integrated Circuit** {#i2c}
 
     A 2-wire synchronous communication bus, consisting of a clock signal and a
     bidirectional data signal. An I2C bus typically contains one controller
@@ -121,119 +127,142 @@
     supported clock speeds of 100 KHz and 400 KHz. The full [I2C Specification]
     is available from NXP (formerly Phillips).
 
-*   **LED - Light Emitting Diode**{#led}
+*   **LED - Light Emitting Diode** {#led}
 
     A Light Emitting Diode is a semiconductor that emits light when current
     flows through it.
 
-*   **LPC - [Low Pin Count bus]**{#lpc}
+*   **LPC - [Low Pin Count bus]** {#lpc}
 
     Legacy communication bus between the [AP](#ap) and [EC](#ec). Runs at 33
-    MHz, providing a 133 Mbps bandwidth connection.  Replaced by the
+    MHz, providing a 133 Mbps bandwidth connection. Replaced by the
     [eSPI](#espi) interface.
 
-*   **MAG - Magnetometer**{#mag}
+*   **MAG - Magnetometer** {#mag}
 
     A digital compass sensor, providing orientation for navigation.
 
-*   **MCU - Microcontroller Unit**{#mcu}
+*   **MCU - Microcontroller Unit** {#mcu}
 
     A small integrated chip containing a CPU core, on-chip ROM, on-chip RAM.
     Also contains multiple peripheral interfaces, including GPIO, I2C buses, SPI
     buses, ADC, PWM, etc.
 
-*   **MKBP - Matrix Keyboard Protocol**{#mkbp}
+*   **MKBP - Matrix Keyboard Protocol** {#mkbp}
 
     Message based protocol for communicating asynchronous events from the
     [EC](#ec) to the [AP](#ap). Events are not limited to keyboard events with
     the sensor subsystem as one of the main users. An EC board implementation
-    can be configured to send keyboard events through MKBP or using the [8042
-    interface](#8042). This is the [EC MKBP driver] implementation.
+    can be configured to send keyboard events through MKBP or using the
+    [8042 interface](#8042). This is the [EC MKBP driver] implementation.
 
-*   **MST - Multi Stream Transport**{#mst}
+*   **MST - Multi Stream Transport** {#mst}
 
     Part of the Display Port 1.2 standard, used to drive multiple independent
     video streams from a single display port. The EC code is typically
     responsible for enabling and disabling the MST hub chipset.
 
-*   **OOBM - Out of Band Management**{#oobm}
+*   **OOBM - Out of Band Management** {#oobm}
 
     A command in the [EC-3PO protocol](#ec-3po) that allows commands to be
     entered to alter the behaviour of the console and interpreter during
     runtime.
 
-*   **PD - USB Power Delivery**{#pd}
+*   **PD - USB Power Delivery** {#pd}
 
     See the [USB-C documentation](./usb-c.md#pd) for more details.
 
-*   **PMIC - Power Management IC**{#pmic}
+*   **PMIC - Power Management IC** {#pmic}
 
     An integrated circuit used to turn power rails on and off.
 
-*   **PPC - USB Power Path Controller**{#ppc}
+*   **PPC - USB Power Path Controller** {#ppc}
 
     See the [USB-C documentation](./usb-c.md#ppc) for more details.
 
-*   **PWM - Pulse Width Modulation**{#pwm}
+*   **PWM - Pulse Width Modulation** {#pwm}
 
     Method of varying the duty cycle of a signal to control another device. A
     typical application is to control fan speeds or the brightness of a
     backlight.
 
-*   **SAFT - Semi-Automated Firmware Tests**{#saft}
+*   **Retimer** {#retimer}
+
+    A device that can extract the embedded clock signal from a high-speed
+    protocol, fully recover the data, and retransmit a fresh copy of the data
+    using a clean clock.
+
+*   **SAFT - Semi-Automated Firmware Tests** {#saft}
 
     A suite of tests for firmware, succeeded by [FAFT](#faft). See the
     [chromium.org documentation](https://www.chromium.org/for-testers/saft) for
     more details.
 
-*   **SPI - Serial Peripheral Interconnect**{#spi}
+*   **SHI - SPI Host Interface** {#shi}
+
+    [SPI](#spi) host interface used for communication between the AP and the EC.
+    In this configuration, the AP provides the SPI controller and the EC
+    provides the SPI peripheral. This interface is only used for non-x86 base
+    APs.
+
+    x86-based APs use either the [eSPI](#espi) or [LPC](#lpc) interface.
+
+*   **SPI - Serial Peripheral Interconnect** {#spi}
 
     A 4-wire synchronous communication bus consisting of the signals CLK
     (clock), SDO (Serial Data Out), SDI (Serial Data In), and CS (chip-select,
-    one per SPI peripheral).  The SDO and SDI pins are defined from the
+    one per SPI peripheral). The SDO and SDI pins are defined from the
     perspective of the device: the SPI controller's SDO pin connects to the SPI
     peripheral's SDI pin and vice-versa. Clock speeds over 100 MHz are
     supported. SPI communication involves the following sequence:
 
-    * SPI controller asserts CS.
-    * SPI controller transmits one or bytes on its SDO signal, received by the
-      SPI peripheral on its SDI signal.
-    * SPI peripheral transmits zero or more bytes on its SDO signal, received
-      by the SPI controller on its SDI signal.
-    * SPI controller de-asserts CS.
+    *   SPI controller asserts CS.
+    *   SPI controller transmits one or bytes on its SDO signal, received by the
+        SPI peripheral on its SDI signal.
+    *   SPI peripheral transmits zero or more bytes on its SDO signal, received
+        by the SPI controller on its SDI signal.
+    *   SPI controller de-asserts CS.
 
     The specific contents of a SPI frame varies based on the SPI peripheral
     type.
 
-*   **SVDM - Structured Vendor Defined Messages**{#svdm}
+*   **SSMUX - Super Speed Multiplexer** {#ssmux}
+
+    See the [USB-C documentation](./usb-c.md#ssmux) for more details.
+
+*   **SVDM - Structured Vendor Defined Messages** {#svdm}
 
     See the [USB-C documentation](./usb-c.md#svdm) for more details.
 
-*   **TCPC - USB Type-C Port Controller**{#tcpc}
+*   **TCPC - USB Type-C Port Controller** {#tcpc}
 
     See the [USB-C documentation](./usb-c.md#tcpc) for more details.
 
-*   **UART - Universal Asynchronous Receiver Transceiver**{#uart}
+*   **UART - Universal Asynchronous Receiver Transceiver** {#uart}
 
-    Also known as a serial port.  An asynchronous communication channel between
+    Also known as a serial port. An asynchronous communication channel between
     two devices with a dedicated receive pin, transmit pin, and ground. Optional
     hardware flow control signals require additional connections between the
     devices. Standard transmission rates are slow (up to 115200 bits per
     second). Typical use is to provide a debug console to the EC. [RS-232] is
     the protocol standard used by UARTs.
 
+*   **USBA - USB Type-A** {#usba}
+
+    Traditional USB Host port.
+
 *   **VCONN - Connector Voltage** {#vconn}
 
     See the [USB-C documentation](./usb-c.md#vconn) for more details.
 
-
 [BC 1.2 Specification]: <https://www.usb.org/document-library/battery-charging-v12-spec-and-adopters-agreement>
-[CrOS Board Info]: <https://chromium.googlesource.com/chromiumos/docs/+/master/design_docs/cros_board_info.md>
 [CEC Wikipedia page]: <https://en.wikipedia.org/wiki/Consumer_Electronics_Control>
-[DPTF Readme]: <https://github.com/intel/dptf/blob/master/README.txt>
-[eSPI Specification]: <https://www.intel.com/content/dam/support/us/en/documents/software/chipset-software/327432-004_espi_base_specification_rev1.0.pdf>
-[FAFT design doc]: <https://chromium.googlesource.com/chromiumos/third_party/autotest/+/refs/heads/master/docs/faft-design-doc.md>
+[CrOS Board Info]: <https://chromium.googlesource.com/chromiumos/docs/+/HEAD/design_docs/cros_board_info.md>
+[DPTF Readme]: <https://github.com/intel/dptf/blob/HEAD/README.txt>
+[EC MKBP driver]: <https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/common/keyboard_mkbp.c>
+[FAFT design doc]: <https://chromium.googlesource.com/chromiumos/third_party/autotest/+/HEAD/docs/faft-design-doc.md>
 [I2C Specification]: <https://www.nxp.com/docs/en/user-guide/UM10204.pdf>
-[RS-232]: <https://en.wikipedia.org/wiki/RS-232>
-[EC MKBP driver]: <https://chromium.googlesource.com/chromiumos/platform/ec/+/refs/heads/master/common/keyboard_mkbp.c>
 [Low Pin Count bus]: https://en.wikipedia.org/wiki/Low_Pin_Count
+[RS-232]: <https://en.wikipedia.org/wiki/RS-232>
+[eSPI Specification]: <https://www.intel.com/content/dam/support/us/en/documents/software/chipset-software/327432-004_espi_base_specification_rev1.0.pdf>
+[ectool]: ../docs/ap-ec-comm.md
diff --git a/docs/fingerprint/fingerprint-authentication-design-doc.md b/docs/fingerprint/fingerprint-authentication-design-doc.md
index 396fbfe8d0..9f73bd18bc 100644
--- a/docs/fingerprint/fingerprint-authentication-design-doc.md
+++ b/docs/fingerprint/fingerprint-authentication-design-doc.md
@@ -1,4 +1,4 @@
-# Fingerprint Authentication on Chrome OS
+# Fingerprint Authentication on ChromeOS
 
 Authors: norvez@google.com, vpalatin@google.com
 
@@ -31,17 +31,17 @@ Last Updated: 2019-01-14
 
 To unlock their Chromebook users have to enter their password or a PIN.
 [Windows] and [macOS] let the user authenticate with their fingerprint for
-faster unlocking, we want to bring that capability to Chrome OS.
+faster unlocking, we want to bring that capability to ChromeOS.
 
 ### Fingerprint matching basics
 
 #### Fingerprint enrollment
 
 When a user wants to register their finger for fingerprint authentication, they
-go through the _enrollment_ operation. They are asked to touch the sensor
+go through the *enrollment* operation. They are asked to touch the sensor
 multiple times with different parts of their fingerprint. The
 [matching algorithm] uses the images captured during enrollment to build a model
-of that fingerprint (known as a _template_).
+of that fingerprint (known as a *template*).
 
 #### Fingerprint matching
 
@@ -78,7 +78,7 @@ There are two main objectives for potential attackers:
 ### Privacy and security
 
 *   Biometric data is particularly sensitive, so all operations on fingerprint
-    data must happen in a _Secure Biometric Processor_ (**SBP**). Attackers must
+    data must happen in a *Secure Biometric Processor* (**SBP**). Attackers must
     not gain access to the user’s fingerprints even if they have exploited the
     software running on the AP.
 *   To protect the user’s privacy, fingerprint data must not be accessible
@@ -101,7 +101,7 @@ attack surface again.
 ## Overview {#overview}
 
 Devices have a dedicated microcontroller (MCU) running a firmware based on the
-[Chromium OS EC] codebase that is used as the _Secure Biometric Processor_
+[Chromium OS EC] codebase that is used as the *Secure Biometric Processor*
 (**SBP**), where all enrollment and matching operations take place. Even if
 attackers gained control of the AP, they still would not be able to access the
 fingerprint (FP) data since it never leaves the SBP unencrypted.
@@ -184,7 +184,7 @@ replace this post-launch with a mechanism similar to
 FP templates are AES-encrypted with `HW_Key`. `HW_Key` is bound to this specific
 SBP so encrypted templates can only be deciphered by this specific SBP. To
 ensure that a powerwash/recovery/WP toggle/.../ makes the encryption key
-impossible to recover, `HW_Key` also depends on a secret held by the TPM.
+impossible to recover, `HW_Key` also depends on a secret held by the [TPM].
 
 We use an AEAD cipher (AES-GCM) to detect if the encrypted templates have been
 tampered with by an attacker controlling the AP.
@@ -208,7 +208,7 @@ every time the TPM is cleared, for example if someone attempts to do a
 "[ccd open]" to disable the hardware WP.
 
 The following is a summary of the mechanism, see the specific design doc
-[“TPM-seed for Fingerprint MCU”] for details.
+[TPM Seed for Fingerprint MCU] for details.
 
 The TPM already holds a "[system key]" `Cros_Sys_Key` in NVRAM space that is
 used to derive the encryption key of the stateful partition. That "system key"
@@ -322,7 +322,7 @@ Encrypted templates are stored in a “[cryptohome daemon store folder]” that
 only mounted/decrypted when the user has logged in. The templates are stored as
 JSON files with the following fields:
 
-```JSON
+```json
 {
   "biomanager": “CrosFpBiometricsManager” string
   "version": integer describing the version of the file format. Set to 1 at launch
@@ -379,7 +379,7 @@ used to protect the EC in detachable keyboards as described in
 
 The SBP has a minimalistic RO firmware that contains the public part of an
 RSA-3072 exponent 3 key pair. The corresponding private key is only accessible
-by the Chrome OS signers and is used to sign SBP firmwares. On boot the RO
+by the ChromeOS signers and is used to sign SBP firmwares. On boot the RO
 firmware verifies the signature of the RW firmware. If the RW signature is
 valid, the RO firmware protects itself by setting the WP bit of the Flash then
 jumps to RW.
@@ -573,7 +573,7 @@ could start sending D-Bus commands to biod.
 
 The enrollment/matching and image capture libraries are provided by a 3rd-party
 vendor in binary form. That proprietary blob went through a security audit by a
-3rd party auditor (see the auditor’s [report][Security Audit Report].
+3rd party auditor (see the auditor’s [report][Security Audit Report]).
 
 On top of the security audit of the 3rd-party proprietary code, we limit the
 attack surface of those libraries by not directly exposing them to user input.
@@ -714,45 +714,46 @@ The log file is `/var/log/cros_fp.log`.
 [Arm TrustZone]: https://www.arm.com/products/security-on-arm/trustzone
 [Authentication-Time User Secrets]: http://go/authentication-time-user-secrets
 [AuthSession]: https://chromium.googlesource.com/chromiumos/platform2/+/eae39a9ad1239f8fbfa8164255578b306ff6ba5c/biod/biometrics_manager.h#96
-[biod D-Bus API]: https://chromium.googlesource.com/chromiumos/platform2/+/refs/heads/master/system_api/dbus/biod/
-[biod upstart script]: https://chromium.googlesource.com/chromiumos/platform2/+/master/biod/init/biod.conf
+[biod D-Bus API]: https://chromium.googlesource.com/chromiumos/platform2/+/HEAD/system_api/dbus/biod/
+[biod upstart script]: https://chromium.googlesource.com/chromiumos/platform2/+/HEAD/biod/init/biod.conf
 [ccd open]: https://chromium.googlesource.com/chromiumos/platform/ec/+/cr50_stab/docs/case_closed_debugging_cr50.md#Open-CCD
 [CDD]: https://source.android.com/compatibility/android-cdd#7_3_10_fingerprint_sensor
-[Chromium OS EC]: https://chromium.googlesource.com/chromiumos/platform/ec/+/master/README.md
+[Chromium OS EC]: https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/README.md
 [clobber-state]: https://chromium.googlesource.com/chromiumos/platform2/+/962ab1bc481db0cf504b5449eb3a3d5008ea7601/init/clobber_state.cc#475
-[cryptohome daemon store folder]: https://chromium.googlesource.com/chromiumos/docs/+/master/sandboxing.md#securely-mounting-cryptohome-daemon-store-folders
+[cryptohome daemon store folder]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/sandboxing.md#securely-mounting-cryptohome-daemon-store-folders
 [cryptohome]: https://www.chromium.org/chromium-os/chromiumos-design-docs/protecting-cached-user-data
 [Detachable Base Swap Detection]: https://docs.google.com/document/d/1WYdkkSAL_RHVc5mUXnAvBBfAeM7Wj3ABa1dbeTdvm74/edit#heading=h.g74ijelumqop
 [Detachable Base Verified Boot Anti-Rollback]: http://go/detachable-base-vboot#heading=h.fimcm174ok3
 [Detachable Base Verified Boot]: http://go/detachable-base-vboot#heading=h.dolfbdpggye6
-[EC primitives]: https://chromium.googlesource.com/chromiumos/platform/ec/+/master/README.md#Software-Features
+[EC primitives]: https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/README.md#Software-Features
 [EnrollSession]: https://chromium.googlesource.com/chromiumos/platform2/+/eae39a9ad1239f8fbfa8164255578b306ff6ba5c/biod/biometrics_manager.h#92
 [fingerprint authentication framework]: https://developer.android.com/about/versions/marshmallow/android-6.0.html#fingerprint-authentication
-[fuzzed]: https://chromium.googlesource.com/chromiumos/platform2/+/master/biod/biod_storage_fuzzer.cc
+[fuzzed]: https://chromium.googlesource.com/chromiumos/platform2/+/HEAD/biod/biod_storage_fuzzer.cc
 [Global Read-out Protection (RDP) mode Level 1]: https://www.st.com/content/ccc/resource/technical/document/application_note/b4/14/62/81/18/57/48/05/DM00075930.pdf/files/DM00075930.pdf/jcr:content/translations/en.DM00075930.pdf
 [HKDF]: https://tools.ietf.org/html/rfc5869
 [Input Key Material (IKM)]: https://en.wikipedia.org/wiki/HKDF
 [Intel SGX]: https://software.intel.com/en-us/sgx
 [macOS]: https://support.apple.com/en-us/HT207054
-[malloc/free memory module for Chrome EC]: https://chromium.googlesource.com/chromiumos/platform/ec/+/master/common/shmalloc.c
+[malloc/free memory module for Chrome EC]: https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/common/shmalloc.c
 [matching algorithm]: https://en.wikipedia.org/wiki/Fingerprint#Algorithms
-[mount_encrypted]: https://chromium.googlesource.com/chromiumos/platform2/+/master/cryptohome/mount_encrypted
+[mount_encrypted]: https://chromium.googlesource.com/chromiumos/platform2/+/HEAD/cryptohome/mount_encrypted
 [New UKM collection review - CrOS FP Unlock]: https://docs.google.com/document/d/1qjDCMcBcrhSeg_uwyEIRsXHKmzUTJahcg6a4YVhkuLo
 [Old Design Doc]: https://docs.google.com/document/d/1MdPRmCDkVg1HO9DdbvPT5fDZS2ICg5ys9_ok_K95EEU
 [PDD is here]: http://go/cros-fingerprint-pdd
 [Privacy fields for Fingerprints]: https://docs.google.com/spreadsheets/d/1jLfnuhfbrImpoxuj92OkAxS_GGrm7QkpQhsUQCkO9ec
 [Privacy fields for Fingerprints]: https://docs.google.com/spreadsheets/d/1jLfnuhfbrImpoxuj92OkAxS_GGrm7QkpQhsUQCkO9ec/
 [RM0433]: https://www.st.com/content/ccc/resource/technical/document/reference_manual/group0/c9/a3/76/fa/55/46/45/fa/DM00314099/files/DM00314099.pdf/jcr:content/translations/en.DM00314099.pdf
-[sandboxing]: https://chromium.googlesource.com/chromiumos/docs/+/master/sandboxing.md
-[seccomp filter]: https://chromium.googlesource.com/chromiumos/platform2/+/master/biod/init/seccomp/biod-seccomp-amd64.policy
-[Security Audit Report]: https://drive.google.com/a/google.com/file/d/0B1HHKpeDpzYnMDdocGxwWUhpckpWM0hMU0tPa2ZjdEFnLU53/
+[sandboxing]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/sandboxing.md
+[seccomp filter]: https://chromium.googlesource.com/chromiumos/platform2/+/HEAD/biod/init/seccomp/biod-seccomp-amd64.policy
+[Security Audit Report]: https://drive.google.com/file/d/0B1HHKpeDpzYnMDdocGxwWUhpckpWM0hMU0tPa2ZjdEFnLU53/view?usp=sharing&resourcekey=0-utAJosm8Lwvx9TOz7F4i7w
 [state machine]: https://chromium.googlesource.com/chromiumos/platform/ec/+/90d177e3f0ae729bea7e24934a3c6ef9f2520d45/common/fpsensor.c#252
 [statically allocated]: https://chromium.googlesource.com/chromiumos/platform/ec/+/90d177e3f0ae729bea7e24934a3c6ef9f2520d45/common/fpsensor.c#57
 [system key]: https://chromium.googlesource.com/chromiumos/platform2/+/23b79133514ac2cd986bce21c398fb6658bda248/cryptohome/mount_encrypted/encryption_key.h#125
 [UMA]: http://go/uma
 [Windows]: https://www.microsoft.com/en-us/windows/windows-hello
 [wrappers functions]: https://chrome-internal.googlesource.com/chromeos/platform/ec-private/+/9ebb3f10c611afff695f679aaeed1a35551a116b/fpc_sensor_pal.c#52
-[“TPM-seed for Fingerprint MCU”]: http://go/bio_tpm_seed
+[TPM Seed for Fingerprint MCU]: ../fingerprint/fingerprint-tpm-seed.md
+[TPM]: https://www.chromium.org/developers/design-documents/tpm-usage/
 
 <!-- Images -->
 
@@ -760,10 +761,13 @@ The log file is `/var/log/cros_fp.log`.
      appending "export/png" to the Google Drive link. -->
 
 <!-- https://docs.google.com/drawings/d/1-JUWTF7sUTND29BfhDvIudzX_S6g-iwoxG1InPedmVw -->
+
 [Decryption Flowchart]: ../images/cros_fingerprint_decryption_flowchart.png
 
 <!-- https://drive.google.com/open?id=1uUprgLsTUZZ2G2QWRYcRn6zBAh6ejvJagVRD7eZQv-k -->
+
 [Encryption Flowchart]: ../images/cros_fingerprint_encryption_flowchart.png
 
 <!-- https://docs.google.com/drawings/d/1DFEdxfDXEtYY3LNOOJFAxVw2A7rKouH98tnb1yiXLAA -->
+
 [Fingerprint Architecture]: ../images/cros_fingerprint_architecture_diagram.png
diff --git a/docs/fingerprint/fingerprint-debugging.md b/docs/fingerprint/fingerprint-debugging.md
index 7316ad3434..b015eb1199 100644
--- a/docs/fingerprint/fingerprint-debugging.md
+++ b/docs/fingerprint/fingerprint-debugging.md
@@ -1,7 +1,7 @@
 # Fingerprint Debugging
 
 This document describes how to attach a debugger with SWD in order to debug the
-FPMCU.
+FPMCU with [`gdb`](#gdb) or to [flash the FPMCU](#flash).
 
 [TOC]
 
@@ -22,39 +22,72 @@ used for JTAG and SWD for ARM devices.
 *   JTAG/SWD Debugger Probe: Any debug probe that supports SWD will work, but
     this document assumes that you're using a
     [Segger J-Trace PRO for Cortex-M][J-Trace].
-*   [Dragonclaw v0.2 Development board][FPMCU dev board].
+*   [Dragonclaw v0.3 Development board][FPMCU dev board] or
+    [Icetower v0.1 Development board][FPMCU dev board].
 *   [Servo Micro].
 
 ## Software Required
 
-*   [JLink Software] \(when using [J-Trace] or other Segger debug probes).
-*   Any tool that supports connecting `gdbserver`. This document will assume
-    [CLion] and was tested with `JLink_Linux_V684a_x86_64`.
-*   Alternatively, you can use [Ozone] a standalone debugger from Segger.
+*   [JLink Software] \(when using [J-Trace] or other Segger debug probes). This
+    is the only software required for flashing.
+*   In order to perform breakpoint debugging, you will need a tool that supports
+    connecting `gdbserver`. This document will assume [CLion] \(Googlers see
+    [CLion for ChromeOS]) and was tested with `JLink v6.94a`. Alternatively, you
+    can use [Ozone], a standalone debugger from Segger.
 
-## Connecting SWD
+## JLink Software {#software}
 
-The connector for SWD is `J4` on Dragonclaw v0.2.
+Install the JLink software in the chroot with the following command:
 
+```bash
+(chroot) $ sudo emerge jlink
+```
+
+<!-- mdformat off(b/139308852) -->
+*** note
+**NOTE**: The above command will print out a message directing you to manually
+download a tarball. You must follow these instructions for the installation to
+be complete.
+***
+<!-- mdformat on -->
+
+## Connecting SWD {#connect-swd}
+
+### Dragonclaw v0.3
+
+The connector for SWD is `J4` on Dragonclaw v0.3.
+
+<!-- mdformat off(b/139308852) -->
 *** note
 **NOTE**: Pay attention to the location of pin 1 (red wire) in the
 photos below so that you connect with the correct orientation.
 
-`SW2` on the bottom of Dragonclaw must be set to `CORESIGHT`.
+`SW2` on the edge of Dragonclaw must be set to `CORESIGHT`.
 
 If you want to connect a 20-Pin ARM Standard JTAG Connector (0.10" / 2.54 mm),
 you can use the following [adapter][JTAG to SWD Adapter] and [cable][SWD Cable].
 ***
+<!-- mdformat on -->
 
-Dragonclaw v0.2 with 20-pin SWD (0.05" / 1.27mm) on J4. Only half the pins are connected. |
+Dragonclaw v0.3 with 20-pin SWD (0.05" / 1.27mm) on J4. Only half the pins are connected. |
 ----------------------------------------------------------------------------------------- |
 ![Dragonclaw with 20-pin SWD]                                                             |
 
-Dragonclaw v0.2 with 10-pin SWD (0.05" / 1.27mm) on J4. |
+Dragonclaw v0.3 with 10-pin SWD (0.05" / 1.27mm) on J4. |
 ------------------------------------------------------- |
 ![Dragonclaw with 10-pin SWD]                           |
 
-## Powering the Board
+### Icetower v3
+
+The connector for SWD is labeled with `CORESIGHT20 DB CONN` on Icetower v3.
+
+`JTAG` on Icetower must be set to `CORESIGHT` (not `SERVO`).
+
+Icetower v3 with 20-pin SWD (0.05" / 1.27mm) on `CORESIGHT20 DB CONN`. |
+---------------------------------------------------------------------- |
+![Icetower with 20-pin SWD]                                            |
+
+## Powering the Board {#power}
 
 [Servo Micro] can provide both the 3.3V for the MCU and 1.8V for the sensor.
 
@@ -62,29 +95,83 @@ Run the following to start `servod`, which will enable power to these rails by
 default:
 
 ```bash
-(chroot) $ sudo servod --board=dragonclaw
+(chroot) $ sudo servod --board=<BOARD>
+```
+
+where `<BOARD>` is the board you are working with
+([`dartmonkey` or `bloonchipper`][fingerprint hardware]).
+
+Theoretically, it's also possible to power through J-Trace, though the
+[power pin] on J-Trace only outputs 5V, whereas the MCU runs at 3.3V and the
+sensor runs at 1.8V. The pin is also not connected on the current designs.
+
+## Flashing the FPMCU with JLink {#flash}
+
+*   Install the [JLink Software](#software).
+*   [Connect SWD](#connect-swd).
+*   [Power the board with servo](#power).
+*   Start the JLink server:
+
+```bash
+(chroot) $ cd ~/trunk/src/platform/ec
+```
+
+```bash
+# JLinkRemoteServerCLExe will listen on port 19020 (among others) by default.
+# This can be overridden with the -Port argument.
+(chroot) $ sudo JLinkRemoteServerCLExe -select USB
+```
+
+You should see the following:
+
+```bash
+SEGGER J-Link Remote Server V6.94a
+Compiled Jan 14 2021 11:52:48
+
+'q' to quit '?' for help
+
+Connected to J-Link with S/N 123456
+
+Waiting for client connections...
+```
+
+*   Build the FPMCU image:
+
+```bash
+(chroot) $ cd ~/trunk/src/platform/ec
+```
+
+```bash
+(chroot) $ make BOARD=<BOARD> -j
+```
+
+replacing `<BOARD>` with [`bloonchipper` or `dartmonkey`][fingerprint hardware].
+
+*   Run the [`flash_jlink.py`] script:
+
+```bash
+(chroot) $ ~/trunk/src/platform/ec/util/flash_jlink.py --board <BOARD> --image ./build/<BOARD>/ec.bin
 ```
 
-It's also possible to power through J-Trace, though this can only supply the MCU
-with power (3.3V), not a sensor using 1.8V.
+replacing `<BOARD>` with [`bloonchipper` or `dartmonkey`][fingerprint hardware].
 
-## Using JLink gdbserver
+## Using JLink gdbserver {#gdb}
 
 Start the JLink gdbserver for the appropriate MCU type:
 
 *   Dragonclaw / [Nucleo STM32F412ZG]: `STM32F412CG`
-*   Dragontalon / [Nucleo STM32H743ZI]: `STM32H743ZI`
+*   Icetower / [Nucleo STM32H743ZI]: `STM32H743ZI`
 
 ```bash
-(outside) $ ./JLink_Linux_V684a_x86_64/JLinkGDBServerCLExe -select USB -device STM32F412CG -endian little -if SWD -speed auto -noir -noLocalhostOnly
+(chroot) $ JLinkGDBServerCLExe -select USB -device STM32F412CG -endian little -if SWD -speed auto -noir -noLocalhostOnly
 ```
 
-You should see the port that gdbserver is running on in the output:
+You should see the port that `gdbserver` is running on in the output:
 
 ```bash
 Connecting to J-Link...
 J-Link is connected.
-Firmware: J-Trace PRO V2 Cortex-M compiled Dec 13 2019 11:19:22
+Firmware: J-Trace PRO V2 Cortex-M compiled Feb  5 2021 14:50:19
 Hardware: V2.00
 S/N: XXXXX
 Feature(s): RDI, FlashBP, FlashDL, JFlash, GDB
@@ -110,7 +197,7 @@ In your editor, specify the IP address and port for `gdbserver`:
 You will also want to provide the symbol files:
 
 *   RW image: `build/<board>/RW/ec.RW.elf`
-*   RO image: `build/<board>/RO.ec.RO.elf`
+*   RO image: `build/<board>/RO/ec.RO.elf`
 
 Also, since we're compiling the firmware in the chroot, but your editor is
 running outside of the chroot, you'll want to remap the source code path to
@@ -143,7 +230,7 @@ Ozone is a free standalone debugger provided by Segger that works with the
 gdbserver can provide. For example, Ozone has a register mapping for the MCUs we
 use, so you can easily inspect CPU registers. It can also be automated with a
 scripting language and show code coverage when used with a [J-Trace] that is
-connected to the trace pins on a board. Note that the Dragonclaw v0.2 uses an
+connected to the trace pins on a board. Note that the Dragonclaw v0.3 uses an
 STM32F412 package that does not have the synchronous trace pins, but the
 [Nucleo STM32F412ZG] does have the trace pins.
 
@@ -156,14 +243,19 @@ STM32F412 package that does not have the synchronous trace pins, but the
 [SWD Cable]: https://www.adafruit.com/product/1675
 [Ozone]: https://www.segger.com/products/development-tools/ozone-j-link-debugger/
 [CLion]: https://www.jetbrains.com/clion/
+[CLion for ChromeOS]: http://go/clion-for-chromeos
 [GDB Remote Debug Configuration]: https://www.jetbrains.com/help/clion/remote-debug.html#remote-config
 [CLion Start Remote Debug]: https://www.jetbrains.com/help/clion/remote-debug.html#start-remote-debug
 [Nucleo STM32F412ZG]: https://www.st.com/en/evaluation-tools/nucleo-f412zg.html
 [Nucleo STM32H743ZI]: https://www.st.com/en/evaluation-tools/nucleo-h743zi.html
 [`.gdbinit`]: /util/gdbinit
 [configure `~/.gdbinit`]: https://www.jetbrains.com/help/clion/configuring-debugger-options.html#gdbinit-lldbinit
+[power pin]: https://www.segger.com/products/debug-probes/j-link/technology/interface-description/
+[fingerprint hardware]: ./fingerprint.md#hardware
+[`flash_jlink.py`]: https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/util/flash_jlink.py
 
 <!-- Images -->
 
 [Dragonclaw with 20-pin SWD]: ../images/dragonclaw_with_20_pin_swd.jpg
 [Dragonclaw with 10-pin SWD]: ../images/dragonclaw_with_10_pin_swd.jpg
+[Icetower with 20-pin SWD]: ../images/icetower_with_20_pin_swd.jpg
diff --git a/docs/fingerprint/fingerprint-dev-for-partners.md b/docs/fingerprint/fingerprint-dev-for-partners.md
index 1aef3735fb..f2fe8fd34b 100644
--- a/docs/fingerprint/fingerprint-dev-for-partners.md
+++ b/docs/fingerprint/fingerprint-dev-for-partners.md
@@ -27,126 +27,80 @@ The Fingerprint MCU (FPMCU) board has the MCU that handles all
 fingerprint-related functionality (matching, encryption, etc). The fingerprint
 sensor itself connects to the FPMCU board.
 
-This FPMCU board is the Dragonclaw Rev 0.2. |
+<!-- mdformat off(b/139308852) -->
+*** note
+Older revisions of these boards are not supported. If you have an older version
+of the board, please request a replacement.
+***
+<!-- mdformat on -->
+
+This FPMCU board is the Dragonclaw Rev 0.3. |
 ------------------------------------------- |
 ![Dragonclaw board]                         |
 
 Download the [Dragonclaw schematics, layout, and BOM][dragonclaw schematics].
 
+<!-- mdformat off(b/139308852) -->
 *** note
-**Googlers**: You can pick up the Dragonclaw development board at Chromestop.
+**Googlers**: You can pick up a Dragonclaw development board at Chromestop.
+
 **Partners**: You can request a Dragonclaw development board from Google.
 ***
+<!-- mdformat on -->
 
+This FPMCU board is Icetower Rev 3. |
+----------------------------------- |
+![Icetower board]                   |
+
+<!-- mdformat off(b/139308852) -->
 *** note
-Dragonclaw Rev 0.2 needs a [rework](#dragonclaw-rev-0.2-rework) for the FPC
-sensor to work while being powered through Servo. All of the boards at Chromestop
-have already been reworked.
-***
+**Googlers**: You can pick up an Icetower development board at Chromestop.
 
-This FPMCU board is the Dartmonkey Rev 0.1. |
-------------------------------------------- |
-![Dartmonkey board]                         |
+**Partners**: You can request an Icetower development board from Google.
+***
+<!-- mdformat on -->
 
 ### Servo
 
 Servo is a general purpose debug board that connects to a header on the FPMCU
 board. Among other things, the servo supplies power to the FPMCU and can be used
 to program the FPMCU, interact with the EC console, take power measurements, and
-debug a running program. It supports SPI, UART, I2C, as well as JTAG/SWD.
+debug a running program.
 
-There are two different servo debugger setups supported, the
-[Servo Micro](#servo-micro) and the [Servo V2 + Yoshi](#servo-v2-yoshi). The
-servo micro is recommended for its simplicity. It lacks builtin JTAG/SWD support
-for single step debugging, but Dragonclaw v0.2 has an
+There are several variants of Servo and the fingerprint team uses the
+[Servo Micro](#servo-micro) for its simplicity. It lacks builtin JTAG/SWD
+support for single step debugging, but Dragonclaw v0.3 and Icetower v3 have an
 [SWD connector](#servo-micro-swd) that can be used.
 
-[Servo Micro](#servo-micro) | [ServoV2 + Yoshi](#servo-v2-yoshi)
---------------------------- | ----------------------------------
-![Servo Micro]              | ServoV2 ![Servo v2] Yoshi Flex ![Standard Yoshi Flex]
+[Servo Micro](#servo-micro) |
+--------------------------- |
+![Servo Micro]              |
 
+<!-- mdformat off(b/139308852) -->
 *** note
-For more information about both servos, see [servo].
+For more information about Servo, see [servo].
 ***
+<!-- mdformat on -->
 
 ### Servo Micro
 
-Unlike the Servo V2, the newer servo micro does not require any adapters to
-interface with the FPMCU board.
+Servo Micro does not require any adapters to interface with the FPMCU board.
 
 As you can see below, one end connects to the FPMCU board and the other connect
 to the developer's computer over micro USB.
 
 ![Servo Micro with Dragonclaw]
 
+<!-- mdformat off(b/139308852) -->
 *** note
 For more information about Servo Micro, see [Servo Micro Info].
 ***
+<!-- mdformat on -->
 
 #### Using SWD (Optional) {#servo-micro-swd}
 
 Instructions for setup are described in [Fingerprint Debugging].
 
-### Servo V2 + Yoshi
-
-Servo V2 is the original full featured debugger. It requires a
-[Yoshi Flex Cable](#yoshi-flex-cable) to interface with the FPMCU.
-
-![Servo v2]
-
-*** note
-NOTE: More information on servo can be found in the [servo] documentation.
-***
-
-#### Yoshi Flex Cable
-
-The Yoshi Flex cable is used to connect Servo v2 to the FPMCU board. The
-standard cable does not work with SWD, but a simple rework can be performed to
-support SWD.
-
-Standard Yoshi Flex    | Yoshi Flex Reworked to Support SWD
----------------------- | -------------------------------------
-![Standard Yoshi Flex] | ![Yoshi Flex Reworked to Support SWD]
-
-Rework steps:
-
-*   Remove R18 and R19
-*   Wire from Pin 6 of U21 to right side of R18
-*   Wire from Pin 6 of U21 to right side of R19
-
-#### Micro USB Cable
-
-A micro USB cable is needed to connect the the servo v2 board to your host Linux
-development machine.
-
-*   [Micro USB Cable]
-
-#### Servo V2 Hardware Setup
-
-1.  Connect the Yoshi Flex cable to servo, paying attention to the pin
-    numbering.
-
-    ![Connect Yoshi Flex] ![Another Yoshi Flex image]
-
-2.  Connect the other end of the Yoshi Flex cable to the servo header on the
-    FPMCU board.
-
-    ![Connect Yoshi Flex to FPMCU board] ![Another image]
-
-3.  Connect the fingerprint sensor to the header on the FPMCU board.
-
-4.  Connect the micro USB cable to servo's `HOST_IN` port. The other end of the
-    USB cable should be plugged into your host development machine.
-
-    ![Connect USB to Servo]
-
-5.  Optional: Connect SWD Debugger
-
-    If you want to use SWD for debugging, connect your debugger to the `JTAG`
-    header on servo v2.
-
-    ![Connect SWD Debugger]
-
 ## Software Setup
 
 ### Get the Chromium OS source code
@@ -164,13 +118,15 @@ Open **two** terminals and enter the chroot in each:
 # from a terminal on your machine
 (outside chroot) $ cd ~/chromiumos/src
 
-# enter the chroot (the flag is important)
-(outside chroot) $ cros_sdk --no-ns-pid
+# enter the chroot
+(outside chroot) $ cros_sdk
 ```
 
+<!-- mdformat off(b/139308852) -->
 *** note
 NOTE: More information on servo can be found in the [servo] documentation.
 ***
+<!-- mdformat on -->
 
 In one of the terminals, build and start `servod`
 
@@ -180,10 +136,12 @@ Build and install `servod` in the chroot:
 (chroot) $ sudo emerge hdctools
 ```
 
+<!-- mdformat off(b/139308852) -->
 *** note
 In all of the following commands, replace `<BOARD>` in the command with
 `bloonchipper` or `dartmonkey` depending on the development board you are using.
 ***
+<!-- mdformat on -->
 
 Run `servod`:
 
@@ -194,75 +152,114 @@ Run `servod`:
 You should see something like this. Leave it running:
 
 ```bash
-2019-04-11 15:21:53,715 - servod - INFO - Start
-2019-04-11 15:21:53,765 - servod - INFO - Found servo, vid: 0x18d1 pid: 0x5002 sid: 911416-00789
-2019-04-11 15:21:53,766 - servod - INFO - Found XML overlay for board zerblebarn
-2019-04-11 15:21:53,766 - SystemConfig - INFO - Loading XML config (/usr/lib64/python2.7/site-packages/servo/data/servo_v2_r1.xml, None, 0)
-2019-04-11 15:21:53,767 - SystemConfig - INFO - Loading XML config (/usr/lib64/python2.7/site-packages/servo/data/servo_v2_r0.xml, None, 0)
-2019-04-11 15:21:53,771 - SystemConfig - INFO - Loading XML config (/usr/lib64/python2.7/site-packages/servo/data/common.xml, None, 0)
-2019-04-11 15:21:53,772 - SystemConfig - INFO - Loading XML config (/usr/lib64/python2.7/site-packages/servo/data/power_tools.xml, None, 0)
-2019-04-11 15:21:53,774 - SystemConfig - INFO - Loading XML config (/usr/lib64/python2.7/site-packages/servo/data/keyboard.xml, None, 0)
-2019-04-11 15:21:53,775 - SystemConfig - INFO - Loading XML config (/usr/lib64/python2.7/site-packages/servo/data/uart_common.xml, None, 0)
-2019-04-11 15:21:53,777 - SystemConfig - INFO - Loading XML config (/usr/lib64/python2.7/site-packages/servo/data/ftdii2c_cmd.xml, None, 0)
-2019-04-11 15:21:53,777 - SystemConfig - INFO - Loading XML config (/usr/lib64/python2.7/site-packages/servo/data/usb_image_management.xml, None, 0)
-2019-04-11 15:21:53,784 - SystemConfig - INFO - Loading XML config (/usr/lib64/python2.7/site-packages/servo/data/servo_zerblebarn_overlay.xml, None, 0)
-2019-04-11 15:21:53,785 - SystemConfig - INFO - Loading XML config (/usr/lib64/python2.7/site-packages/servo/data/servoflex_v2_r0_p50.xml, None, 0)
-2019-04-11 15:21:53,792 - Servod - INFO - Initializing interface 1 to ftdi_empty
-2019-04-11 15:21:53,792 - Servod - INFO - Initializing interface 2 to ftdi_i2c
-2019-04-11 15:21:53,795 - Servod - INFO - Initializing interface 3 to ftdi_uart
-2019-04-11 15:21:53,799 - Servod - INFO - /dev/pts/8
-2019-04-11 15:21:53,799 - Servod - INFO - Initializing interface 4 to ftdi_uart
-2019-04-11 15:21:53,802 - Servod - INFO - /dev/pts/9
-2019-04-11 15:21:53,802 - Servod - INFO - Use the next FTDI part @ pid = 0x5003
-2019-04-11 15:21:53,802 - Servod - INFO - Initializing interface 5 to ftdi_empty
-2019-04-11 15:21:53,802 - Servod - INFO - Use the next FTDI part @ pid = 0x5003
-2019-04-11 15:21:53,802 - Servod - INFO - Initializing interface 6 to ftdi_empty
-2019-04-11 15:21:53,802 - Servod - INFO - Use the next FTDI part @ pid = 0x5003
-2019-04-11 15:21:53,802 - Servod - INFO - Initializing interface 7 to ftdi_uart
-2019-04-11 15:21:53,805 - Servod - INFO - /dev/pts/10
-2019-04-11 15:21:53,805 - Servod - INFO - Use the next FTDI part @ pid = 0x5003
-2019-04-11 15:21:53,805 - Servod - INFO - Initializing interface 8 to ftdi_uart
-2019-04-11 15:21:53,808 - Servod - INFO - /dev/pts/11
-2019-04-11 15:21:53,808 - Servod - INFO - Initializing interface 9 to ec3po_uart
-2019-04-11 15:21:53,811 - PD/Cr50 - EC3PO Interface - INFO - -------------------- PD/Cr50 console on: /dev/pts/12
-2019-04-11 15:21:53,811 - Servod - INFO - Initializing interface 10 to ec3po_uart
-2019-04-11 15:21:53,812 - EC - EC3PO Interface - INFO - -------------------- EC console on: /dev/pts/14
-2019-04-11 15:21:54,316 - Servod - INFO - Initialized i2c_mux to rem
-2019-04-11 15:21:54,317 - Servod - INFO - Initialized i2c_mux_en to on
-2019-04-11 15:21:54,319 - Servod - INFO - Initialized pch_disable to off
-2019-04-11 15:21:54,320 - Servod - INFO - Initialized jtag_buf_on_flex_en to off
-2019-04-11 15:21:54,321 - Servod - INFO - Initialized cold_reset to off
-2019-04-11 15:21:54,322 - Servod - INFO - Initialized warm_reset to off
-2019-04-11 15:21:54,323 - Servod - INFO - Initialized spi1_buf_on_flex_en to off
-2019-04-11 15:21:54,324 - Servod - INFO - Initialized spi_hold to off
-2019-04-11 15:21:54,326 - Servod - INFO - Initialized pwr_button to release
-2019-04-11 15:21:54,327 - Servod - INFO - Initialized lid_open to yes
-2019-04-11 15:21:54,328 - Servod - INFO - Initialized spi2_buf_on_flex_en to off
-2019-04-11 15:21:54,330 - Servod - INFO - Initialized rec_mode to off
-2019-04-11 15:21:54,331 - Servod - INFO - Initialized fw_up to off
-2019-04-11 15:21:54,332 - Servod - INFO - Initialized usb_mux_sel1 to dut_sees_usbkey
-2019-04-11 15:21:54,333 - Servod - INFO - Initialized prtctl4_pwren to on
-2019-04-11 15:21:54,334 - Servod - INFO - Initialized uart3_en to on
-2019-04-11 15:21:54,334 - Servod - INFO - Initialized dut_hub_pwren to on
-2019-04-11 15:21:54,335 - Servod - INFO - Initialized kbd_en to off
-2019-04-11 15:21:54,337 - Servod - INFO - Initialized spi1_vref to pp3300
-2019-04-11 15:21:54,338 - Servod - INFO - Initialized spi2_vref to pp1800
-2019-04-11 15:21:54,339 - Servod - INFO - Initialized uart2_en to on
-2019-04-11 15:21:54,340 - Servod - INFO - Initialized uart1_en to on
-2019-04-11 15:21:54,341 - Servod - INFO - Initialized jtag_buf_en to off
-2019-04-11 15:21:54,342 - Servod - INFO - Initialized fw_wp_en to off
-2019-04-11 15:21:54,343 - Servod - INFO - Initialized sd_vref_sel to off
-2019-04-11 15:21:54,343 - Servod - INFO - Initialized ec_ec3po_interp_connect to on
-2019-04-11 15:21:54,344 - Servod - INFO - Initialized uart3_vref to off
-2019-04-11 15:21:54,345 - Servod - INFO - Initialized jtag_vref_sel0 to pp3300
-2019-04-11 15:21:54,346 - Servod - INFO - Initialized jtag_vref_sel1 to pp3300
-2019-04-11 15:21:54,346 - Servod - INFO - Initialized fpmcu_ec3po_interp_connect to on
-2019-04-11 15:21:54,349 - ServoDeviceWatchdog - INFO - Watchdog setup for devices: set([(6353, 20482, '911416-00789')])
-2019-04-11 15:21:54,351 - servod - INFO - Listening on localhost port 9999
+2023-02-03 15:05:30,632 - servod - INFO - Start
+2023-02-03 15:05:30,639 - servod - INFO - Found XML overlay for board icetower
+2023-02-03 15:05:30,639 - SystemConfig - INFO - Loading XML config (/usr/lib64/python3.6/site-packages/servo/data/servo_micro.xml, None, 0)
+2023-02-03 15:05:30,640 - SystemConfig - INFO - Loading XML config (/usr/lib64/python3.6/site-packages/servo/data/common.xml, None, 0)
+2023-02-03 15:05:30,640 - SystemConfig - INFO - Loading XML config (/usr/lib64/python3.6/site-packages/servo/data/power_tools.xml, None, 0)
+2023-02-03 15:05:30,642 - SystemConfig - INFO - Loading XML config (/usr/lib64/python3.6/site-packages/servo/data/keyboard.xml, None, 0)
+2023-02-03 15:05:30,644 - SystemConfig - INFO - Loading XML config (/usr/lib64/python3.6/site-packages/servo/data/uart_common.xml, None, 0)
+2023-02-03 15:05:30,644 - SystemConfig - INFO - Loading XML config (/usr/lib64/python3.6/site-packages/servo/data/ec_info.xml, None, 0)
+2023-02-03 15:05:30,645 - SystemConfig - INFO - Loading XML config (/usr/lib64/python3.6/site-packages/servo/data/cpu_fw_spi.xml, None, 0)
+2023-02-03 15:05:30,645 - SystemConfig - INFO - Loading XML config (/usr/lib64/python3.6/site-packages/servo/data/servo_adc_enabled_noop.xml, None, 0)
+2023-02-03 15:05:30,648 - SystemConfig - INFO - Loading XML config (/usr/lib64/python3.6/site-packages/servo/data/servo_icetower_overlay.xml, None, 0)
+2023-02-03 15:05:30,648 - SystemConfig - INFO - Loading XML config (/usr/lib64/python3.6/site-packages/servo/data/servo_fpmcu_dev_board_common_overlay.xml, None, 0)
+2023-02-03 15:05:30,649 - SystemConfig - INFO - Loading XML config (/usr/lib64/python3.6/site-packages/servo/data/servoflex_v2_r0_p50.xml, None, 0)
+2023-02-03 15:05:30,649 - SystemConfig - INFO - Loading XML config (/usr/lib64/python3.6/site-packages/servo/data/fpmcu_dev_board_common_inas.xml, None, 0)
+2023-02-03 15:05:30,649 - SystemConfig - INFO - Loading XML config (/usr/lib64/python3.6/site-packages/servo/data/ina2xx.xml, None, 0)
+2023-02-03 15:05:30,650 - SystemConfig - INFO - Loading XML config (/usr/lib64/python3.6/site-packages/servo/data/servo_fpmcu_dev_board_uart_common_overlay.xml, None, 0)
+2023-02-03 15:05:30,655 - Servod - INFO - Initializing interface 1 to stm32_uart
+2023-02-03 15:05:30,655 - Interface.Build - INFO - Suart: interface: {'name': 'stm32_uart', 'interface': 0, 'index': 1}
+2023-02-03 15:05:30,661 - Interface.Build - INFO - /dev/pts/2
+2023-02-03 15:05:30,661 - Servod - INFO - Initializing interface 2 to stm32_i2c
+2023-02-03 15:05:30,661 - Interface.Build - INFO - Si2cBus: interface: {'name': 'stm32_i2c', 'interface': 4, 'index': 2}
+2023-02-03 15:05:30,661 - root - INFO - Skipping modprobe of i2c-dev: it is already loaded per existence of: /sys/module/i2c_dev/
+2023-02-03 15:05:30,661 - root - INFO - Executing command: ['modprobe', '--quiet', '--', 'i2c-pseudo']
+2023-02-03 15:05:30,664 - i2c_base - INFO - path b'/dev/i2c-pseudo-controller' not found, cannot start I2C pseudo adapter
+2023-02-03 15:05:30,665 - Servod - INFO - Initializing interface 3 to stm32_uart
+2023-02-03 15:05:30,666 - Interface.Build - INFO - Suart: interface: {'name': 'stm32_uart', 'interface': 3, 'index': 3}
+2023-02-03 15:05:30,670 - Interface.Build - INFO - /dev/pts/3
+2023-02-03 15:05:30,670 - Servod - INFO - Initializing interface 6 to ec3po_uart
+2023-02-03 15:05:30,673 - servo_micro - EC3PO Interface - INFO - -------------------- servo_micro console on: /dev/pts/4
+2023-02-03 15:05:30,673 - Servod - INFO - Initializing interface 7 to stm32_uart
+2023-02-03 15:05:30,673 - Interface.Build - INFO - Suart: interface: {'name': 'stm32_uart', 'interface': 6, 'index': 7}
+2023-02-03 15:05:30,678 - Interface.Build - INFO - /dev/pts/6
+2023-02-03 15:05:30,678 - Servod - INFO - Initializing interface 8 to stm32_uart
+2023-02-03 15:05:30,679 - Interface.Build - INFO - Suart: interface: {'name': 'stm32_uart', 'interface': 5, 'index': 8}
+2023-02-03 15:05:30,684 - Interface.Build - INFO - /dev/pts/7
+2023-02-03 15:05:30,684 - Servod - INFO - Initializing interface 9 to ec3po_uart
+2023-02-03 15:05:30,685 - PD/Cr50 - EC3PO Interface - INFO - -------------------- PD/Cr50 console on: /dev/pts/8
+2023-02-03 15:05:30,685 - Servod - INFO - Initializing interface 10 to ec3po_uart
+2023-02-03 15:05:30,687 - EC - EC3PO Interface - INFO - -------------------- EC console on: /dev/pts/10
+2023-02-03 15:05:30,687 - Servod - INFO - Initializing interface 11 to ec3po_uart
+2023-02-03 15:05:30,688 - CPU - EC3PO Interface - INFO - -------------------- CPU console on: /dev/pts/12
+2023-02-03 15:05:31,193 - Servod - INFO - Initialized init_keyboard to on
+2023-02-03 15:05:31,194 - root - WARNING - cpu_ec3po_interp_connect: '1' not found in the param values
+2023-02-03 15:05:31,195 - root - WARNING - cpu_ec3po_interp_connect: update drv to get and set values from the param map {'off': '0'}
+2023-02-03 15:05:31,195 - Servod - INFO - Initialized cpu_ec3po_interp_connect to off
+2023-02-03 15:05:31,200 - Servod - INFO - Initialized cpu_uart_raw_debug to off
+2023-02-03 15:05:31,202 - Servod - INFO - Initialized cpu_uart_timestamp to off
+2023-02-03 15:05:31,204 - Servod - INFO - Initialized ec_ec3po_interp_connect to on
+2023-02-03 15:05:31,205 - Servod - INFO - Initialized ec_uart_raw_debug to off
+2023-02-03 15:05:31,206 - Servod - INFO - Initialized ec_uart_timestamp to on
+2023-02-03 15:05:31,207 - Servod - INFO - Initialized ec_uart_flush to on
+2023-02-03 15:05:31,290 - CPU - EC3PO.Console - INFO - /dev/pts/12 - Disabling uart timestamps.
+2023-02-03 15:05:31,308 - Servod - INFO - Initialized uart1_en to on
+2023-02-03 15:05:31,335 - Servod - INFO - Initialized servo_micro_ec_boot_mode_uut to off
+2023-02-03 15:05:31,462 - Servod - INFO - Initialized servo_jtag_trst to off
+2023-02-03 15:05:31,564 - Servod - INFO - Initialized spi1_buf_en to off
+2023-02-03 15:05:31,664 - Servod - INFO - Initialized spi2_buf_en to off
+2023-02-03 15:05:31,767 - Servod - INFO - Initialized uart2_en to on
+2023-02-03 15:05:32,020 - Servod - INFO - Initialized spi1_vref to pp3300
+2023-02-03 15:05:32,268 - Servod - INFO - Initialized spi2_vref to pp1800
+2023-02-03 15:05:32,396 - Servod - INFO - Initialized servo_jtag_trst_dir to off
+2023-02-03 15:05:32,521 - Servod - INFO - Initialized servo_jtag_tdi_dir to off
+2023-02-03 15:05:32,620 - Servod - INFO - Initialized gpio_expander_reset to off
+2023-02-03 15:05:32,721 - Servod - INFO - Initialized uart3_on_spi1 to off
+2023-02-03 15:05:32,824 - Servod - INFO - Initialized SERVO_JTAG_TMS_DIR to off
+2023-02-03 15:05:32,952 - Servod - INFO - Initialized SERVO_JTAG_TDO_SEL to off
+2023-02-03 15:05:33,078 - Servod - INFO - Initialized SERVO_JTAG_TMS to off
+2023-02-03 15:05:33,206 - Servod - INFO - Initialized UART3_TX_SERVO_JTAG_TCK to off
+2023-02-03 15:05:33,334 - Servod - INFO - Initialized UART3_RX_JTAG_BUFFER_TO_SERVO_TDO to off
+2023-02-03 15:05:33,459 - Servod - INFO - Initialized SERVO_JTAG_TDO_BUFFER_EN to off
+2023-02-03 15:05:33,585 - Servod - INFO - Initialized SERVO_JTAG_TDI to off
+2023-02-03 15:05:33,711 - Servod - INFO - Initialized SERVO_JTAG_RTCK to off
+2023-02-03 15:05:33,808 - Servod - INFO - Initialized JTAG_BUFOUT_EN_L to off
+2023-02-03 15:05:33,936 - Servod - INFO - Initialized JTAG_BUFIN_EN_L to off
+2023-02-03 15:05:33,936 - Servod - INFO - Initialized usbpd_uart_routing to off
+2023-02-03 15:05:33,940 - Servod - INFO - Initialized fw_wp_en to off
+2023-02-03 15:05:33,943 - Servod - INFO - Initialized tp1 to off
+2023-02-03 15:05:33,948 - Servod - INFO - Initialized cold_reset to off
+2023-02-03 15:05:33,952 - Servod - INFO - Initialized pwr_button to release
+2023-02-03 15:05:33,958 - Servod - INFO - Initialized warm_reset to on
+2023-02-03 15:05:33,962 - Servod - INFO - Initialized rec_mode to on
+2023-02-03 15:05:33,968 - Servod - INFO - Initialized fw_up to off
+2023-02-03 15:05:33,972 - Servod - INFO - Initialized lid_open to yes
+2023-02-03 15:05:33,976 - Servod - INFO - Initialized pch_disable to off
+2023-02-03 15:05:33,978 - Servod - INFO - Initialized tp2 to off
+2023-02-03 15:05:34,380 - servoFirmwareChecker - INFO - servo_micro firmware up to date.
+2023-02-03 15:05:34,381 - Servod - INFO - Initialized servo_micro_firmware_uptodate to check
+2023-02-03 15:05:34,382 - Servod - INFO - Initialized servo_ec3po_interp_connect to on
+2023-02-03 15:05:34,384 - Servod - INFO - Initialized servo_micro_uart_raw_debug to off
+2023-02-03 15:05:34,385 - Servod - INFO - Initialized servo_micro_uart_timestamp to on
+2023-02-03 15:05:34,387 - Servod - INFO - Initialized usbpd_ec3po_interp_connect to on
+2023-02-03 15:05:34,389 - Servod - INFO - Initialized jtag_vref_sel0 to pp3300
+2023-02-03 15:05:34,391 - Servod - INFO - Initialized jtag_vref_sel1 to pp3300
+2023-02-03 15:05:34,398 - Servod - INFO - Initialized hpd to off
+2023-02-03 15:05:34,399 - Servod - INFO - Initialized fpmcu_ec3po_interp_connect to off
+2023-02-03 15:05:34,401 - Servod - INFO - Initialized fpmcu_ec3po_interp_connect_1 to off
+2023-02-03 15:05:34,401 - DeviceWatchdog - INFO - Watchdog setup for devices: [18d1:501a MICRO-S-2201160335]
+2023-02-03 15:05:34,402 - servod - INFO - Listening on localhost port 9999
 ```
 
 In the other terminal, build and flash the firmware:
 
+Make sure the toolchain is installed:
+
+```bash
+(chroot) $ sudo cros_setup_toolchains
+```
+
 Navigate to the EC source:
 
 ```bash
@@ -292,7 +289,7 @@ Prepare a serial terminal in your chroot:
 Connect to the UART pty:
 
 ```bash
-(chroot) $ sudo screen $(dut-control raw_fpmcu_uart_pty | cut -d: -f2)
+(chroot) $ sudo screen $(dut-control raw_fpmcu_console_uart_pty | cut -d: -f2)
 ```
 
 Press enter key several times (may need to wait up to 20 seconds). Then you will
@@ -348,6 +345,12 @@ You can get a summary of the power over `N` seconds with:
 (chroot) $ dut-control -t N pp3300_dx_mcu_mv pp3300_dx_fp_mv pp1800_dx_fp_mv pp3300_dx_mcu_mw pp3300_dx_fp_mw pp1800_dx_fp_mw
 ```
 
+When measuring the power, make sure that any debuggers are disconnected. The
+most reliable way to make sure it is disconnected is to physically disconnect
+the debugger and servo_micro from the board. Then re-attach servo_micro and
+restart `servod`.
+
+<!-- mdformat off(b/139308852) -->
 *** note
 The `_mv` suffix denotes millivolt and `_mw` suffix denotes milliwatt.
 ***
@@ -355,6 +358,7 @@ The `_mv` suffix denotes millivolt and `_mw` suffix denotes milliwatt.
 *** note
 See [Power Measurement Documentation] for more information.
 ***
+<!-- mdformat on -->
 
 ### Toggling Hardware Write Protect
 
@@ -397,7 +401,7 @@ some docs to help you get started:
 *   [Git: Concepts and Workflow]: Good overview of how `git` actually works.
 *   [Gerrit: Concepts and Workflow]: Good overview of how Gerrit works; assumes
     you understand `git` basics.
-*   [Life of a patch]: Android workflow, but similar to Chrome OS.
+*   [Life of a patch]: Android workflow, but similar to ChromeOS.
 
 The Gerrit dashboard that will show your pending reviews (and ones we have for
 you):
@@ -413,6 +417,7 @@ register for an account on the [Internal Gerrit]. Refer to the
 account, your contact at Google can make sure you have the necessary permissions
 to access the private repository.
 
+<!-- mdformat off(b/139308852) -->
 *** note
 **NOTE**: In order to use a private repository you will have to manually add it
 to the repo manifest file before running `repo sync`. Check with your contact
@@ -435,6 +440,7 @@ at Google for the exact values to use below:
         review="https://chrome-internal-review.googlesource.com" />
 ```
 ***
+<!-- mdformat on -->
 
 ### Tracking Issues and Communication
 
@@ -462,7 +468,7 @@ from the UI.
 
 ### Developer Mode and Write Protection
 
-Make sure that your fingerprint-equipped Chrome OS device is in [developer mode]
+Make sure that your fingerprint-equipped ChromeOS device is in [developer mode]
 with a *test* image flashed and [hardware write protection] disabled. Using the
 test image will allow you to SSH into the device and disabling hardware write
 protection allows you to have full access to flashing the FPMCU firmware.
@@ -509,37 +515,14 @@ From the DUT, flash the firmware you copied:
 ```bash
 (device) $ flash_fp_mcu /tmp/ec.bin
 ```
-## Commit-queue Prototype Environment
-
-![Dragonclaw in CQ Prototype Environment]
-
-## Troubleshooting
-
-### Dragonclaw Rev 0.2 Rework {#dragonclaw-rev-0.2-rework}
-
-*** note
-**NOTE**: All Dragonclaw v0.2 boards have been reworked, so it is not necessary
-to perform the rework yourself.
-***
-
-Dragonclaw **Rev 0.2** has two load switches (`U4` and `U6`) that enable the
-1.8V power rail from the servo connector or motherboard connector. However, this
-switch is not compatible with 1.8V, so will always output 0V.
-
-The [rework document][Dragonclaw Rev 0.2 1.8V Rework] describes replacing these
-two switches with ones compatible with 1.8V.
 
-### Dragonclaw Rev 0.1 Servo Fix
-
-Dragonclaw **Rev 0.1** has a known issue with UART and JTAG. Most notably, this
-issue causes servo micro to fail to program the FPMCU over UART.
+## Commit-queue Prototype Environment
 
-This issue can be fixed with the following rework steps:
+![CQ Prototype Environment]
 
-*   Connect servo header pin 13 to pin 18
-*   Connect servo header pin 13 to pin 29
+![FPMCU devboard environment v2 with satlab]
 
-![Dragonclaw servo fix diagram]
+## Troubleshooting
 
 ### Verify that servo and debugger are connected to USB {#servo-connected}
 
@@ -552,7 +535,7 @@ supply.
 (chroot) $ lsusb
 
 Bus 002 Device 003: ID 0897:0004 Lauterbach  # ← This is my Lauterbach (debugger)
-Bus 001 Device 013: ID 18d1:5002 Google Inc. # ← This is servo
+Bus 001 Device 013: ID 18d1:5002 Google LLC # ← This is servo
 ```
 
 ### "No servos found" when running servod
@@ -584,27 +567,27 @@ Make sure that this interface is disabled:
 <!-- Links -->
 
 [EC]: https://chromium.googlesource.com/chromiumos/platform/ec
-[ectool_servo_spi]: https://chromium.googlesource.com/chromiumos/platform/ec/+/refs/heads/master/util/comm-servo-spi.c#15
-[servo]: https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/master/README.md
-[developer mode]: https://chromium.googlesource.com/chromiumos/docs/+/master/debug_buttons.md#firmware-keyboard-interface
-[hardware write protection]: https://chromium.googlesource.com/chromiumos/platform/ec/+/refs/heads/master/docs/write_protection.md
-[have the prerequisites]: https://chromium.googlesource.com/chromiumos/docs/+/master/developer_guide.md#Prerequisites
-[get the source]: https://chromium.googlesource.com/chromiumos/docs/+/master/developer_guide.md#get-the-source
-[enter the `chroot`]: https://chromium.googlesource.com/chromiumos/docs/+/master/developer_guide.md#building-chromium-os
-[Chromium OS Contributing Guide]: https://chromium.googlesource.com/chromiumos/docs/+/master/contributing.md
-[Servo Micro Info]: https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/master/docs/servo_micro.md
-[Set your editor]: https://chromium.googlesource.com/chromiumos/docs/+/master/developer_guide.md#Set-your-editor
+[ectool_servo_spi]: https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/util/comm-servo-spi.c#15
+[servo]: https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/HEAD/README.md
+[developer mode]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/debug_buttons.md#firmware-keyboard-interface
+[hardware write protection]: https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/docs/write_protection.md
+[have the prerequisites]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/developer_guide.md#Prerequisites
+[get the source]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/developer_guide.md#get-the-source
+[enter the `chroot`]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/developer_guide.md#building-chromium-os
+[Chromium OS Contributing Guide]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/contributing.md
+[Servo Micro Info]: https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/HEAD/docs/servo_micro.md
+[Set your editor]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/developer_guide.md#Set-your-editor
 [Life of a patch]: https://source.android.com/setup/contribute/life-of-a-patch
 [Git: Concepts and Workflow]: https://docs.google.com/presentation/d/1IQCRPHEIX-qKo7QFxsD3V62yhyGA9_5YsYXFOiBpgkk/
 [Gerrit: Concepts and Workflow]: https://docs.google.com/presentation/d/1C73UgQdzZDw0gzpaEqIC6SPujZJhqamyqO1XOHjH-uk/
 [Public Gerrit]: https://chromium-review.googlesource.com
-[Power Measurement Documentation]: https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/master/docs/power_measurement.md
+[Power Measurement Documentation]: https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/HEAD/docs/power_measurement.md
 [Internal Gerrit]: https://chrome-internal-review.googlesource.com
 [Gerrit Credentials Setup]: https://www.chromium.org/chromium-os/developer-guide/gerrit-guide
 [Micro USB Cable]: https://www.monoprice.com/product?p_id=9762
 [PNM]: https://en.wikipedia.org/wiki/Netpbm_format
-[Git and Gerrit Intro for Chromium OS]: https://chromium.googlesource.com/chromiumos/docs/+/master/git_and_gerrit_intro.md
-[Installing Chromium]: https://chromium.googlesource.com/chromiumos/docs/+/master/developer_guide.md#installing-chromium-os-on-your-device
+[Git and Gerrit Intro for Chromium OS]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/git_and_gerrit_intro.md
+[Installing Chromium]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/developer_guide.md#installing-chromium-os-on-your-device
 [FPMCU documentation]: ./fingerprint.md
 [Fingerprint Debugging]: ./fingerprint-debugging.md
 [dragonclaw schematics]: ../schematics/dragonclaw
@@ -613,24 +596,21 @@ Make sure that this interface is disabled:
 
 [Servo Micro]: ../images/servo_micro.jpg
 [Servo Micro with Dragonclaw]: ../images/servomicro_dragonclaw.jpg
-[Servo v2]: ../images/servo_v2.jpg
-[Standard Yoshi Flex]: ../images/yoshi_flex.jpg
-[Yoshi Flex Reworked to Support SWD]: ../images/yoshi_flex_swd_rework.jpg
-[Dragonclaw board]: ../images/dragonclaw_rev_0.2.jpg
+[Dragonclaw board]: ../images/dragonclaw_v0.3.jpg
 [Dragonclaw servo fix diagram]: ../images/dragonclaw_servo_fix.jpg
-[Connect USB to Servo]: ../images/servo_v2_with_micro_usb.jpg
-[Connect Yoshi Flex]: ../images/servo_v2_with_yoshi_flex.jpg
-[Another Yoshi Flex image]: ../images/servo_v2_with_yoshi_flex2.jpg
-[Connect Yoshi Flex to FPMCU board]: ../images/dragonclaw_yoshi_flex_header.jpg
-[Another image]: ../images/dragonclaw_yoshi_flex_header2.jpg
-[Connect SWD Debugger]: ../images/servo_v2_jtag_header.jpg
-[Dartmonkey board]: ../images/dartmonkey.jpg
+[Icetower board]: ../images/icetower_v3.jpg
 
 <!-- If you make changes to the docs below make sure to regenerate the JPEGs by
      appending "export/pdf" to the Google Drive link. -->
 
 <!-- https://docs.google.com/drawings/d/1YhOUD-Qf69NUdugT6n0cX7o7CWvb5begcdmJwv7ch6I -->
-[Dragonclaw Rev 0.2 1.8V Rework]: https://github.com/coreboot/chrome-ec/blob/master/docs/images/dragonclaw_rev_0.2_1.8v_load_switch_rework.pdf
+
+[Dragonclaw Rev 0.2 1.8V Rework]: https://github.com/coreboot/chrome-ec/blob/HEAD/docs/images/dragonclaw_rev_0.2_1.8v_load_switch_rework.pdf
 
 <!-- https://docs.google.com/drawings/d/1w2qbb4AsSxY-KTK2vXZ6TKeWHveWvS3Dkgh61ocu0wc -->
-[Dragonclaw in CQ Prototype Environment]: ../images/Dragonclaw_in_CQ_Prototype_Environment.jpg
+
+[CQ Prototype Environment]: ../images/CQ_Prototype_Environment.jpg
+
+<!-- https://docs.google.com/drawings/d/13hsnPBa1aeMVU7CjrK1nz-aeYSQcdLxrylOEJNOiEA0 -->
+
+[FPMCU devboard environment v2 with satlab]: ../images/FPMCU_devboard_environment_v2_with_Satlab.jpg
diff --git a/docs/fingerprint/fingerprint-factory-quick-guide.md b/docs/fingerprint/fingerprint-factory-quick-guide.md
index aeb84f157b..0e095bf9fe 100644
--- a/docs/fingerprint/fingerprint-factory-quick-guide.md
+++ b/docs/fingerprint/fingerprint-factory-quick-guide.md
@@ -1,7 +1,7 @@
-# Chrome OS Fingerprint Sensor: Quick Factory Guide
+# ChromeOS Fingerprint Sensor: Quick Factory Guide
 
 The goal of this document is to outline how ODM partners can make use of the
-existing Chrome OS factory scripts to meet Chrome OS FPS factory requirements.
+existing ChromeOS factory scripts to meet ChromeOS FPS factory requirements.
 
 [TOC]
 
@@ -13,48 +13,44 @@ FPMCU firmware must be flashed before fingerprint functional test is run. ODM
 partners may work with the module house to preflash FPMCU firmware before
 factory SMT. However, this way ODM partners have to coordinate with the module
 house to make sure the preflash FPMCU firmware blob is extracted from the FSI
-release image (from /opt/google/biod/fw/). If the FPMCU firmware doesn’t match
+release image (from `/opt/google/biod/fw/`). If the FPMCU firmware doesn’t match
 the FPMCU firmware blob checked into the release image, the end users will see
 the ‘critical update’ screen in their out-of-box experience, because
-bio\_fw\_updater tries to update FPMCU firmware at boot time. This is a bad user
+`bio_fw_updater` tries to update FPMCU firmware at boot time. This is a bad user
 experience we want to avoid. Most importantly, in PVT/MP build, only the FPMCU
 firmware in the release image would be signed by MP key. So you **MUST** ensure
 FPMCU is flashed with the MP-signed firmware blob extracted from FSI, before
 shipping the devices.
 
 As opposed to pre-flashing FPMCU in the module house, ODM partners are
-encouraged to make use of
-[update\_fpmcu\_firmware.py](https://chromium.googlesource.com/chromiumos/platform/factory/+/e5e903d0a0d8327dd8b9e47d2c808fd845ed73a4/py/test/pytests/update_fpmcu_firmware.py)
-to update FPMCU firmware in the factory flow. This script can detect fingerprint
-MCU board name, find the right FPMCU firmware blob for the DUT from the release
-partition, and then flash FPMCU by flash\_fp\_mcu tool. Please note that this
-script may take more than 30 secs to complete, which is slow.
-
-Since bio\_fw\_update has been disabled in factory test image via
+encouraged to make use of [`update_fpmcu_firmware.py`] to update FPMCU firmware
+in the factory flow. This script can detect fingerprint MCU board name, find the
+right FPMCU firmware blob for the DUT from the release partition, and then flash
+FPMCU by [`flash_fp_mcu`] tool. Please note that this script may take more than
+30 secs to complete, which is slow.
+
+Since `bio_fw_updater` has been disabled in factory test image via
 [crrev/c/1913645](https://chromium-review.googlesource.com/c/chromiumos/platform2/+/1913645),
 in the factory flow, the FPMCU firmware should not be overwritten by
-boot-update-firmware service during reboot.
+`boot-update-firmware` service during reboot.
 
 ### Run fingerprint sensor functional test
 
-Please add
-[fingerprint\_mcu.py](https://chromium.git.corp.google.com/chromiumos/platform/factory/+/a283609cd8446ba4a4b75c2e1d84c9ba24ea8422/py/test/pytests/fingerprint_mcu.py)
-to your device test list. A more detailed description about this test can be
-found
-[here](https://chromium.googlesource.com/chromiumos/platform/ec/+/refs/heads/master/docs/fingerprint/fingerprint-factory-requirements.md).
+Please add [`fingerprint_mcu.py`] to your device test list. A more detailed
+description about this test can be found [here][factory requirements].
 
 ### Initialize FPMCU entropy in factory finalization
 
 The support for FPMCU entropy initialization has been integrated into the
 factory finalization script. So FPMCU entropy should be automatically
 initialized in factory finalization, if a FPMCU is found on DUT. Note that FPMCU
-entropy initialization would fail if rollback\_block\_id is not equal to zero,
+entropy initialization would fail if `rollback_block_id` is not equal to zero,
 which means the entropy has been initialized before. It is usually caused by
-biod trying to initialize FPMCU entropy and increment rollback\_block\_id at
-boot time. Since we have disabled biod and bio\_crypto\_init in factory test
+biod trying to initialize FPMCU entropy and increment `rollback_block_id` at
+boot time. Since we have disabled biod and `bio_crypto_init` in factory test
 image via
 [crrev/c/1910290](https://chromium-review.googlesource.com/c/chromiumos/platform/factory/+/1910290),
-we expect rollback\_block\_id would stay zero during the factory flow, and FPMCU
+we expect `rollback_block_id` would stay zero during the factory flow, and FPMCU
 entropy initialization should succeed in factory finalization. So just run
 factory finalization as any other CrOS boards.
 
@@ -62,8 +58,8 @@ factory finalization as any other CrOS boards.
 
 The support for FPMCU SWWP has been integrated into factory finalization script.
 So FPMCU SWWP should be automatically enabled in factory finalization together
-with AP/EC SWWP when write\_protection arg is set to true and a FPMCU is found
-on DUT. Just run factory finalization as any other CrOS boards.
+with AP/EC SWWP when `write_protection` arg is set to `true` and a FPMCU is
+found on DUT. Just run factory finalization as any other CrOS boards.
 
 ### Reset entropy for factory re-finalization (in case of RMA or OQC)
 
@@ -71,14 +67,12 @@ For the boards that have been finalized, FPMCU entropy has been initialized. So
 running re-finalization for those boards are expected to fail at FPMCU entropy
 initialization. Before running re-finalization for those boards, ODM partners
 have to remove hardware write protection (HWWP) and then run
-[update\_fpmcu\_firmware.py](https://chromium.googlesource.com/chromiumos/platform/factory/+/d399a0a1bdeb7249de2721b269e7365e4486e23c/py/test/pytests/update_fpmcu_firmware.py)
-to reset rollback\_block\_id and entropy. So the follow-up re-finalization
-(which re-initialize entropy) can succeed.
+[`update_fpmcu_firmware.py`] to reset `rollback_block_id` and entropy. So the
+follow-up re-finalization (which re-initialize entropy) can succeed.
 
 ## References
 
-*   CrOS fingerprint factory requirements:
-    [doc link](https://chromium.googlesource.com/chromiumos/platform/ec/+/refs/heads/master/docs/fingerprint/fingerprint-factory-requirements.md)
+*   CrOS fingerprint factory requirements: [doc link][factory requirements]
 *   The summary of CLs:
     *   Add a factory script to update FPMCU firmware:
         [crrev/c/1918679](https://chromium-review.googlesource.com/c/chromiumos/platform/factory/+/1918679),
@@ -95,3 +89,8 @@ to reset rollback\_block\_id and entropy. So the follow-up re-finalization
         [crrev/c/1900503](https://chromium-review.googlesource.com/c/chromiumos/platform/factory/+/1900503),
         [crrev/c/1925927](https://chromium-review.googlesource.com/c/chromiumos/platform/factory/+/1925927),
         [crrev/c/1948163](https://chromium-review.googlesource.com/c/chromiumos/platform/factory/+/1948163)
+
+[`update_fpmcu_firmware.py`]: https://crsrc.org/o/src/platform/factory/py/test/pytests/update_fpmcu_firmware.py;drc=672e24bb3e2dd0dec7578dcd4c52805d022662d1
+[factory requirements]: ./fingerprint-factory-requirements.md
+[`fingerprint_mcu.py`]: https://crsrc.org/o/src/platform/factory/py/test/pytests/fingerprint_mcu.py;drc=672e24bb3e2dd0dec7578dcd4c52805d022662d1
+[`flash_fp_mcu`]: https://crsrc.org/o/src/platform/ec/util/flash_fp_mcu;drc=12c473337e3bdcce6d180d266c9e9f8127448f33
diff --git a/docs/fingerprint/fingerprint-factory-requirements.md b/docs/fingerprint/fingerprint-factory-requirements.md
index 4aaf564570..5116b2c77a 100644
--- a/docs/fingerprint/fingerprint-factory-requirements.md
+++ b/docs/fingerprint/fingerprint-factory-requirements.md
@@ -1,4 +1,4 @@
-# Chrome OS Fingerprint Factory Requirements
+# ChromeOS Fingerprint Factory Requirements
 
 This document provides an overview of factory requirements and testing for the
 fingerprint sensor.
@@ -8,7 +8,7 @@ fingerprint sensor.
 ## Contact
 
 For questions regarding this document, please contact the
-[Chrome OS Fingerprint Team].
+[ChromeOS Fingerprint Team].
 
 ## Terminology
 
@@ -39,12 +39,12 @@ For questions regarding this document, please contact the
 ## FPMCU Firmware Location
 
 The binaries for the FPMCU firmware are located in `/opt/google/biod/fw`. Now
-that Chrome OS supports unibuild, there may be multiple firmware binaries in the
+that ChromeOS supports unibuild, there may be multiple firmware binaries in the
 directory since multiple sensors may be used across a single "board" (e.g., the
 `hatch` board can use either `bloonchipper` or `dartmonkey`).
 
 The correct firmware type to use for a given board can be discovered with the
-[Chrome OS Config] tool:
+[ChromeOS Config] tool:
 
 ```bash
 (dut) $ cros_config /fingerprint board
@@ -61,11 +61,13 @@ dartmonkey
 The corresponding firmware for the above command would be
 `/opt/google/biod/fw/dartmonkey_*.bin`.
 
+<!-- mdformat off(b/139308852) -->
 *** note
 **NOTE**: If you get an empty response when running the above commands, the
-Chrome OS Config settings may not have been updated for the Chrome OS board.
-See the instructions on [updating Chrome OS Config] for fingerprint.
+ChromeOS Config settings may not have been updated for the ChromeOS board.
+See the instructions on [updating ChromeOS Config] for fingerprint.
 ***
+<!-- mdformat on -->
 
 Note that the fingerprint team continuously releases updates to the firmware, so
 SIEs should watch for version changes in ToT if they are maintaining a separate
@@ -75,10 +77,7 @@ factory branch.
 
 When the FPMCU is completely blank a low-level flashing tool must be used to
 program an initial version of the FPMCU firmware. It’s possible to use the
-[`flash_fp_mcu`] script as this low-level flashing tool, though since it
-requires the AP and is not necessarily robust against failures, it is not
-recommended for mass-production. More details about [`flash_fp_mcu`] are in the
-[Fingerprint flashing documentation].
+factory script [`update_fpmcu_firmware.py`] as this low-level flashing tool.
 
 The initial version of the FPMCU firmware should be flashed either by the module
 house or by the factory. Once an initial version of the FPMCU firmware has been
@@ -88,12 +87,14 @@ the rootfs. Note that this update process can take around 30 seconds; if that
 length of time is an issue then the factory or module house should pre-flash the
 latest firmware beforehand.
 
+<!-- mdformat off(b/139308852) -->
 *** note
 **NOTE**: If the FPMCU is not flashed in the factory as part of development
 builds (EVT, etc.), it's possible for developers (or Chromestop) to manually
 run [`flash_fp_mcu`], as long as they can disable [hardware write protect].
 Obviously this only applies during development, not mass production.
 ***
+<!-- mdformat on -->
 
 ## biod and timberslide
 
@@ -127,7 +128,7 @@ Card). FPC also provides design drawings for the rubber stamp. The stamp,
 test-fixture and test station need to be implemented by the OEM/ODM/Module House
 (often only module house).
 
-The `MTS` _must_ be followed by the module manufacturer, but Google does not
+The `MTS` *must* be followed by the module manufacturer, but Google does not
 provide direct support for this testing. FPC is the main point of contact.
 
 The module testing procedure is documented in the following:
@@ -142,7 +143,7 @@ In-device tests are run during the `FATP` process once the device has been fully
 assembled. Google provides source code for these tests in
 [`fingerprint_mcu.py`].
 
-Hardware Required: Chrome OS DUT before finalization.
+Hardware Required: ChromeOS DUT before finalization.
 
 Documentation: [FPC In-Device Test Specification]
 
@@ -187,10 +188,12 @@ Perform median analysis on the resulting image as described in the `MTS`
 document. The factory toolkit does this in
 [`fingerprint_mcu.py`][Checkerboard Test].
 
+<!-- mdformat off(b/139308852) -->
 *** note
 **TIP**: You can view the `.pnm` files generated by the commands below on your
 Linux desktop with ImageMagick: `display /path/to/file.pnm`.
 ***
+<!-- mdformat on -->
 
 ##### Success/Failure
 
@@ -461,34 +464,36 @@ To convert the images from FPC’s proprietary format to PNG, you will need to
 have `cros deploy`’d `libfputils-nocturne`, which will install the required
 utilities in `/opt/fpc`.
 
+<!-- mdformat off(b/139308852) -->
 *** note
 **NOTE**: As of 2019-05-21, the `libfputils` library only works for the FPC 1145
 sensor (in nocturne), not the FPC 1025 sensor (hatch).
 ***
+<!-- mdformat on -->
 
 Convert the buffer in proprietary format into png:
 
 ```bash
-(dut) $ /opt/fpc/fputils.py /tmp/fp.raw --png
+(dut) $ /usr/local/opt/fpc/fputils.py /tmp/fp.raw --png
 Extraction found 2 images
 Wrote /tmp/fp.0.png (14085 bytes)
 Wrote /tmp/fp.1.png (14025 bytes)
 ```
 
-[Software Write Protect]: https://chromium.googlesource.com/chromiumos/platform/ec/+/refs/heads/master/docs/write_protection.md#Software-Write-Protect
-[hardware write protect]: https://chromium.googlesource.com/chromiumos/platform/ec/+/master/docs/write_protection.md#hw_wp
+[Software Write Protect]: https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/docs/write_protection.md#Software-Write-Protect
+[hardware write protect]: https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/docs/write_protection.md#hw_wp
 [FPC1025: Module Test Specification]: http://go/cros-fingerprint-fpc1025-module-test-spec
 [FPC1145: Module Test Specification]: http://go/cros-fingerprint-fpc1145-module-test-spec
 [FPC In-Device Test Specification]: http://go/cros-fingerprint-fpc-indevice-test-spec
-[`fingerprint_mcu.py`]: https://chromium.googlesource.com/chromiumos/platform/factory/+/master/py/test/pytests/fingerprint_mcu.py
+[`fingerprint_mcu.py`]: https://chromium.googlesource.com/chromiumos/platform/factory/+/HEAD/py/test/pytests/fingerprint_mcu.py
 [Checkerboard Test]: https://chromium.googlesource.com/chromiumos/platform/factory/+/d23ebc7eeb074760e8a720e3acac4cfe4073b2ae/py/test/pytests/fingerprint_mcu.py#166
 [GetSensorIdErrors]: https://chromium.googlesource.com/chromiumos/platform/factory/+/d23ebc7eeb074760e8a720e3acac4cfe4073b2ae/py/test/utils/fpmcu_utils.py#73
 [GetSensorId]: https://chromium.googlesource.com/chromiumos/platform/factory/+/d23ebc7eeb074760e8a720e3acac4cfe4073b2ae/py/test/utils/fpmcu_utils.py#65
 [ProcessResetPixelImage]: https://chromium.googlesource.com/chromiumos/platform/factory/+/d23ebc7eeb074760e8a720e3acac4cfe4073b2ae/py/test/pytests/fingerprint_mcu.py#268
 [rubber_finger_present]: https://chromium.googlesource.com/chromiumos/platform/factory/+/d23ebc7eeb074760e8a720e3acac4cfe4073b2ae/py/test/pytests/fingerprint_mcu.py#330
-[Chrome OS Fingerprint Team]: http://go/cros-fingerprint-docs
+[ChromeOS Fingerprint Team]: http://go/cros-fingerprint-docs
 [Factory Fingerprint Sensor Testing for `nocturne`]: http://go/fingerprint-factory-testing-nocturne
-[`flash_fp_mcu`]: https://chromium.googlesource.com/chromiumos/platform/ec/+/master/util/flash_fp_mcu
-[Fingerprint flashing documentation]: ./fingerprint.md#factory-rma-dev-updates
-[Chrome OS Config]: https://chromium.googlesource.com/chromiumos/platform2/+/master/chromeos-config/README.md
-[updating Chrome OS Config]: ./fingerprint.md#update-chromeos-config
+[`flash_fp_mcu`]: https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/util/flash_fp_mcu
+[ChromeOS Config]: https://chromium.googlesource.com/chromiumos/platform2/+/HEAD/chromeos-config/README.md
+[updating ChromeOS Config]: ./fingerprint.md#update-chromeos-config
+[`update_fpmcu_firmware.py`]: https://crsrc.org/o/src/platform/factory/py/test/pytests/update_fpmcu_firmware.py;drc=672e24bb3e2dd0dec7578dcd4c52805d022662d1
diff --git a/docs/fingerprint/fingerprint-firmware-testing-for-partners.md b/docs/fingerprint/fingerprint-firmware-testing-for-partners.md
new file mode 100644
index 0000000000..b9de1e92f4
--- /dev/null
+++ b/docs/fingerprint/fingerprint-firmware-testing-for-partners.md
@@ -0,0 +1,112 @@
+# Fingerprint Firmware Testing Instructions for Partners
+
+This document is intended to help partners (sensor vendors, MCU vendors, etc)
+run the ChromeOS fingerprint team's firmware tests, as part of the AVL process.
+The document assumes that you‘re using Linux to do the development; preferably a
+recent version of Ubuntu or Debian. It may be possible to use a virtual machine,
+but that is not a configuration we test.
+
+[TOC]
+
+## Hardware Requirements
+
+You will need a Chromebook with the fingerprint sensor and fingerprint MCU
+(FPMCU), and a [servo debugger].
+
+### Chromebook with fingerprint sensor
+
+The Chromebook needs to be in [developer mode] and running a test image so that
+the test can ssh into it. The fingerprint firmware tests will run a series of
+bash commands, including flashing the FPMCU firmware and rebooting the
+Chromebook. You do not need [CCD] because servo will handle the firmware write
+protection for you.
+
+### Servo
+
+Servo is a general purpose debug board used in many automated tests in Chromium
+OS. Among other things, servo enables the tests to toggle hardware write
+protect.
+
+While there are multiple versions of servo, for firmware tests we strongly
+recommend [Servo V4] as that's the simplest and most often used in autotests.
+This document will assume you are using Servo V4.
+
+### Hardware Setup
+
+*   Connect the "HOST" side of Servo V4 to your host machine (which should have
+    a Chromium OS chroot).
+*   Connect the other side of Servo V4 to a USB port on the Chromebook with
+    fingerprint sensor.
+*   Connect the "DUT POWER" side of Servo V4 to power supply.
+*   Make sure the USB cable from the host machine to Servo V4 is in data
+    transfer mode (i.e. if there's an LED, it should be yellow instead of
+    green).
+*   Make sure the you can ssh into the Chromebook from the chroot on the host
+    machine.
+
+## Software Setup
+
+### Get the Chromium OS source code.
+
+*   First, make sure you [have the prerequisites].
+*   Then [get the source].
+
+### Build the autotest codebase
+
+```bash
+# from a terminal on your machine
+(outside chroot) $ cd ~/chromiumos/src
+
+# enter the chroot
+(outside chroot) $ cros_sdk
+
+# build autotest for the board to be tested
+(chroot) $ emerge-<BOARD> autotest
+```
+
+### Start servod
+
+```bash
+(chroot) $ sudo servod --board=<BOARD>
+```
+
+At this point the servod daemon should be running and listening to port 9999 by
+default. If it isn't, check the hardware connection.
+
+## Run a Single Fingerprint Firmware Test
+
+Use another terminal and enter the chroot like before:
+
+```bash
+(outside chroot) $ cd ~/chromiumos/src
+(outside chroot) $ cros_sdk
+```
+
+To run a single test, use this command in your chroot:
+
+```bash
+test_that --board=<BOARD> <IP> <test name>
+```
+
+For example:
+
+```bash
+test_that --board=nocturne <IP> firmware_Fingerprint.ReadFlash
+```
+
+## Run the Entire Fingerprint Firmware Test Suite
+
+To run the entire suite, use this command in your chroot:
+
+```bash
+test_that --board=<BOARD> <IP> suite:fingerprint
+```
+
+<!-- Links -->
+
+[servo debugger]: https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/HEAD/docs/servo.md
+[developer mode]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/developer_mode.md
+[CCD]: https://chromium.googlesource.com/chromiumos/platform/ec/+/refs/heads/cr50_stab/docs/case_closed_debugging.md
+[Servo V4]: https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/HEAD/docs/servo_v4.md
+[have the prerequisites]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/developer_guide.md#Prerequisites
+[get the source]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/developer_guide.md#get-the-source
diff --git a/docs/fingerprint/fingerprint-ram-and-flash.md b/docs/fingerprint/fingerprint-ram-and-flash.md
new file mode 100644
index 0000000000..1972c25a38
--- /dev/null
+++ b/docs/fingerprint/fingerprint-ram-and-flash.md
@@ -0,0 +1,109 @@
+# Fingerprint MCU RAM and Flash
+
+[TOC]
+
+## Overview
+
+The fingerprint firmware divides flash into three sections: RO, Rollback, and
+RW. The RO (Read-only) section contains a minimal set of code to check the
+signature of the code in RW; it’s essentially a bootloader and once a device
+enters production it never changes. The RW section is the portion of flash that
+runs the matching algorithm and is the portion that we update over time. The
+Rollback section consists of two separate flash sectors that store the minimum
+RW version that is allowed to run; this prevents attacks where an older version
+of RW firmware has a security vulnerability, and we want to prevent it from ever
+being loaded again (even though it’s valid and will pass the signature check).
+The fingerprint firmware also uses the rollback section to store the entropy
+used for the encryption key that protects the fingerprint templates.
+
+<!-- mdformat off(b/139308852) -->
+*** note
+The amount of RAM and flash used is specific to the sensor and matching
+algorithm used. After building the FPMCU firmware (e.g.,
+[`make BOARD=bloonchipper`]), the amount of flash and RAM *remaining* will be
+printed out.
+***
+<!-- mdformat on -->
+
+## STM32H743 (Dartmonkey)
+
+Total Flash: [2 MB]
+
+Total SRAM: [1 MB], but [864 KB is "user SRAM"]. See [Section 2.4 Embedded SRAM]
+for more details.
+
+### Flash
+
+Flash section   | Size                                        | Amount Used
+--------------- | ------------------------------------------- | -----------
+Read-only (RO)  | [768 KB]                                    | See [`make BOARD=dartmonkey`] output.
+Rollback        | [256 KB total][256 KB] (two 128 KB sectors) | [44 bytes in each of the two sections]
+Read-write (RW) | [1024 KB]                                   | See [`make BOARD=dartmonkey`] output.
+
+#### Layout
+
+Flash sector | Flash sector size | Offset             | Firmware Region
+------------ | ----------------- | ------------------ | -------------------
+1            | 128 KB            | 0                  | RO ([768 KB])
+2            | 128 KB            | 0x20000 (131072)   | ...
+3            | 128 KB            | 0x40000 (262144)   | ...
+4            | 128 KB            | 0x60000 (393216)   | ...
+5            | 128 KB            | 0x80000 (524288)   | ...
+6            | 128 KB            | 0xA0000 (655360)   | ...
+7            | 128 KB            | 0xC0000 (786432)   | Rollback ([256 KB])
+8            | 128 KB            | 0xE0000 (917504)   | ...
+9            | 128 KB            | 0x100000 (1048576) | RW ([1024 KB])
+10           | 128 KB            | 0x120000 (1179648) | ...
+11           | 128 KB            | 0x140000 (1310720) | ...
+12           | 128 KB            | 0x160000 (1441792) | ...
+13           | 128 KB            | 0x180000 (1572864) | ...
+14           | 128 KB            | 0x1A0000 (1703936) | ...
+15           | 128 KB            | 0x1C0000 (1835008) | ...
+16           | 128 KB            | 0x1E0000 (1966080) | ...
+
+[2 MB]: https://www.st.com/resource/en/datasheet/stm32h743vi.pdf
+[1 MB]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/chip/stm32/memory_regions.inc;l=10-16;drc=eee7778fcfc5e555d119cff65caa7c045343e356
+[864 KB is "user SRAM"]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/chip/stm32/memory_regions.inc;l=13;drc=eee7778fcfc5e555d119cff65caa7c045343e356
+[Section 2.4 Embedded SRAM]: https://www.st.com/resource/en/reference_manual/dm00314099-stm32h742-stm32h743-753-and-stm32h750-value-line-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf#page=135
+[`make BOARD=dartmonkey`]: ./fingerprint.md
+[`make BOARD=bloonchipper`]: ./fingerprint.md
+[256 KB]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/board/nocturne_fp/board.h;l=62;drc=ed42e86fd3c444982aa7c313c4530ad89c310191
+[768 KB]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/board/nocturne_fp/board.h;l=58;drc=ed42e86fd3c444982aa7c313c4530ad89c310191
+[1024 KB]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/board/nocturne_fp/board.h;l=66-67;drc=ed42e86fd3c444982aa7c313c4530ad89c310191
+[44 bytes in each of the two sections]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/common/rollback_private.h;l=21-29;drc=675f3a1a481aae3247e2d2af3e603b149cdaf4aa
+
+## STM32F412CG (Bloonchipper)
+
+Total Flash: [1 MB][1 MB STM32F412]
+
+Total SRAM: [256 KB]
+
+### Flash
+
+Flash section   | Size                                              | Amount Used
+--------------- | ------------------------------------------------- | -----------
+Read-only (RO)  | [128 KB]                                          | See [`make BOARD=bloonchipper`] output.
+Rollback        | [256 KB (two 128 KB sectors)][STM32F412 Rollback] | [44 bytes in each of the two sections]
+Read-write (RW) | 640 KB                                            | See [`make BOARD=bloonchipper`] output.
+
+#### Layout
+
+Flash sector | Flash sector size | Offset           | Firmware Region
+------------ | ----------------- | ---------------- | ---------------
+1            | 16 KB             | 0                | RO ([128 KB])
+2            | 16 KB             | 0x4000 (16384)   | ...
+3            | 16 KB             | 0x8000 (32768)   | ...
+4            | 16 KB             | 0xC000 (49152)   | ...
+5            | 64 KB             | 0x10000 (65536)  | ...
+6            | 128 KB            | 0x20000 (131072) | Rollback ([256 KB][STM32F412 Rollback])
+7            | 128 KB            | 0x40000 (262144) | ...
+8            | 128 KB            | 0x60000 (393216) | RW (640KB)
+9            | 128 KB            | 0x80000 (524288) | ...
+10           | 128 KB            | 0xA0000 (655360) | ...
+11           | 128 KB            | 0xC0000 (786432) | ...
+12           | 128 KB            | 0xE0000 (917504) | ...
+
+[1 MB STM32F412]: https://www.st.com/resource/en/datasheet/stm32f412cg.pdf
+[256 KB]: https://www.st.com/resource/en/datasheet/stm32f412cg.pdf
+[128 KB]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/board/hatch_fp/board.h;l=66;drc=643635b91ee40def104188cf9623a9a28f25bd4f
+[STM32F412 Rollback]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/board/hatch_fp/board.h;l=70;drc=643635b91ee40def104188cf9623a9a28f25bd4f
diff --git a/docs/fingerprint/fingerprint-tpm-seed.md b/docs/fingerprint/fingerprint-tpm-seed.md
new file mode 100644
index 0000000000..0ee7c83df5
--- /dev/null
+++ b/docs/fingerprint/fingerprint-tpm-seed.md
@@ -0,0 +1,325 @@
+# TPM Seed for Fingerprint MCU
+
+Authors: pmalani@google.com, norvez@google.com
+
+Reviewers: semenzato@google.com, apronin@google.com, mnissler@google.com and
+others
+
+Last Updated: 2018-11-01
+
+[TOC]
+
+## Objective
+
+Increase security for Fingerprint (FP) templates by using a [TPM]-sourced seed
+in addition to internal FPMCU entropy while encrypting FP templates. The
+TPM-sourced seed will be derived from the system key which is loaded from the
+TPM during boot in mount-encrypted.
+
+## Background
+
+Fingerprint authorization in ChromeOS, relies on encrypted FP templates which
+are stored in each user’s mount directory. These templates are created and
+encrypted by the FPMCU during FP enrollment, before being sent back to the AP
+(Application Processor). When the user logs in, these templates are sent to the
+FPMCU where they get decrypted and loaded.
+
+The encryption is performed in the FPMCU using entropy which is internal to the
+MCU and never leaves the MCU. That way, even if the templates are somehow
+obtained by and attacker from the user mount directory, they cannot be
+decrypted, since the attacker will not have access to the MCU entropy. This
+entropy gets reset on every powerwash/recovery.
+
+The complete design doc is [Fingerprint Authentication on ChromeOS].
+
+## Requirements and Scale
+
+The solution proposed should exhibit the following attributes:
+
+*   Strengthens security of FP templates.
+*   Does not compromise the security of other sub-systems.
+*   Works fast and doesn’t affect time to boot, or reduce boot-time stability.
+
+## Design Ideas
+
+In addition to FPMCU entropy, we include a TPM-sourced seed (derived from the
+system key) while performing template encryption. The TPM system key gets
+regenerated during powerwash/recovery, so in the event that the FP templates are
+accessed due to a runtime exploit, a power-wash / recovery from the user will
+ensure:
+
+*   The raw templates cannot be decrypted, since the TPM-seed would have been
+    lost irrevocably.
+*   Since a new TPM-seed is generated (since a new system key is created), old
+    templates can’t be re-used, even if the attacker could somehow gain access
+    to the FP MCU entropy.
+
+The overall design consists of two components:
+
+*   Generating a TPM-seed and sending it to the Biometric sensor managers.
+*   The Bio sensor managers sending the seed to the FPMCU and programming it
+    into the encryption / decryption operations of FP templates.
+
+### TPM seed generation {#seed-generation}
+
+![TPM Seed Diagram]
+
+The TPM seed generation would proceed as follows:
+
+1.  During mount-encrypted execution, after the `System_key` is loaded, the
+    TPM-backed system key will be HMAC-ed with a simple salt (the string
+    `biod`):
+
+    ```
+    TPM_Seed = HMAC_SHA256(System_key, "biod")
+    ```
+
+2.  The resulting 256-bit seed (called `TPM_Seed`) will be maintained in a
+    `brillo::SecureBlob`.
+
+3.  The `TPM_seed` will be saved into a tmpfs file
+    (`/run/biod_crypto_init/seed`) for consumption by `bio_crypto_init`. This
+    file's ownership will be set up such that only user/group `biod` can access
+    it.
+
+4.  `bio_crypto_init` (the binary which sends the seed to the FPMCU) will be
+    spawned after mount-encrypted completes. This is ensured by setting the
+    `bio_crypto_init` upstart rules to depend on `starting boot-services`
+
+5.  On the `bio_crypto_init` side, the `TPM_seed` will be retrieved from the
+    tmpfs file and forwarded to the FP MCU via the various BiometricManagers.
+    Immediately after reading from the tmpfs file, `bio_crypto_init` will nuke
+    (write all 0’s and then delete) the tmpfs file.
+
+6.  The upstart rules of biod will be modified such that it will start after
+    `bio_crypto_init` stops (this modification can be made in the `.conf` file
+    of biod)
+
+#### IPC Mechanism {#ipc}
+
+(For a discussion of various alternatives, please see the
+[Alternatives Considered] section)
+
+The IPC mechanism selected should have the following features:
+
+*   Allow to quickly pass the `TPM_seed` between mount-encrypted and
+    `bio_crypto_init`.
+*   Minimize the presence of extra/asynchronously deleted copies of the
+    `TPM_seed` buffer in kernel and memory. This is crucial to minimize the risk
+    of access to this seed.
+
+The currently proposed method of passing the `TPM_seed` is to use a **file in
+tmpfs**. The sequence would be as follows:
+
+*   mount-encrypted will write the `TPM_Seed` to a file in `/run`
+    (`/run/bio_crypto_init/seed`). `/run` is a tmpfs created by the OS for use
+    by various system services.
+*   `bio_crypto_init` will read the `TPM_Seed` from the known tmpfs file.
+*   As soon as `bio_crypto_init` reads the `TPM_Seed`, it will first overwrite
+    (`/run/biod_crypto_init/seed`) with all 0s, and immediately after will
+    delete `/run/biod_crypto_init/seed`.
+*   `bio_crypto_init` can then instantiate its BiometricManager classes and send
+    the data to the FP MCU. This way, even if the sending of data fails, there
+    will not be any stray copy of the `TPM_seed` in a process’s memory, or in
+    tmpfs.
+
+##### Advantages
+
+*   No/minimal buffering of copies of `TPM_Seed` in kernel.
+*   No need to create and pass FDs between mount-encrypted and
+    `bio_crypto_init`.
+
+##### Disadvantages
+
+*   If `bio_crypto_init` crashes / fails to start, the tmpfs file remains in the
+    system, i.e cleanup of tmpfs is reliant on `bio_crypto_init`.
+
+### Programming TPM_Seed into MCU
+
+#### Entropy addition v/s programming TPM Seed
+
+When a device boots up for the first time after going through
+recovery/powerwash, biod will force an "Add Entropy" step. This involves:
+
+*   rebooting the FP MCU to RO
+*   Performing an entropy addition step
+*   Rebooting the FP MCU to RW
+*   Verifying that the entropy addition has taken place (by checking the block
+    ID of the rollback info on the MCU).
+
+Unfortunately, since the `TPM_Seed` will be stored in MCU RAM, the reboot of the
+FPMCU will lead to the `TPM_Seed` being lost until the next boot. In the absence
+of a `TPM_Seed`, all FPMCU operations will fail (until the next boot). There is
+no opportunity to reprogram the `TPM_Seed`, because that must take place during
+mount-encrypted, which must necessarily run before `biod` starts.
+
+There are two proposals to work around this issue. The one eventually selected
+has been included here, and the other alternative has been placed in the
+[Alternatives Considered] section.
+
+##### Make bio_crypto_init solely set the TPM_Seed (don't perform entropy_add)
+
+In this method, `bio_crypto_init` will not perform any reboot on the MCU, and
+solely program the `TPM_Seed`. This would mean that if a device was to boot for
+a first time without having done any previous powerwash/recovery, the first boot
+would not have FP functionality. FP functionality would be regained on all
+subsequent boot (since the entropy would have been added/initialized by then).
+
+The downside of this approach is a poor user experience.
+
+The benefit is a simple implementation of the `bio_crypto_init` tool, which will
+consequently also take less time to execute (booting to RO/RW are time consuming
+operations).
+
+In practice all devices leaving the factory floor would have `bio_wash
+--factory_init` done on them during finalisation to initialise the entropy, and
+so this shouldn't affect a large majority of end users.
+
+### Signaling biod to start
+
+In order to avoid races which might occur because both `bio_crypto_init` and
+`biod` will try to access the `BiometricManagers`' hardware. We need to ensure
+that `biod` only starts after `bio_crypto_init` ends.
+
+To accomplish this, `biod.conf` will be modified to include a dependency on
+`bio_crypto_init` to start the daemon. So, the relevant portion of `biod.conf`
+will now be:
+
+```
+start on started system-services and started uinput and stopped bio_crypto_init
+```
+
+### Formula to calculate IKM used for encryption in MCU
+
+In the FPMCU we will use the concatenation of `TPM_Seed` and [`SBP_Src_Key`] as
+Input Key Material (IKM) to derive an encryption key. Combined with a random
+salt, the pseudo random key (PRK) would be derived as:
+
+```
+PRK = HMAC_SHA256(Random_Salt, SBP_Src_Key || TPM_Seed)
+```
+
+## Alternatives Considered {#alt-considered}
+
+A few alternatives are being considered for the IPC Mechanism
+
+#### pipe/socketpair
+
+##### Disadvantages
+
+*   The data written to pipes is buffered in internal kernel buffers till it is
+    read out from the other end of the pipe/socketpair. In the case of a
+    `bio_crypto_init` crashing, this will leave a copy in the internal kernel
+    buffers. Question: How long before those internal buffers get cleared in the
+    case of the pipe not being read from?
+
+#### Anonymous file (memfd_create) / Anonymous mmap
+
+##### Disadvantages
+
+*   Question: When all references to the anonymous file are dropped, are the
+    contents of the anonymous file re-allocated, overwritten, or is the
+    corresponding inode simply destroyed (and the data blocks still stick around
+    and are reallocated lazily ?)
+
+There was also another alternative considered for the sequence of programming
+the TPM seed and initializing the FPMCU: make `bio_crypto_init` add entropy and
+then set TPM.
+
+## Security Considerations
+
+### Security boundaries
+
+*   A new minijailed process (`bio_crypto_init`) is run when `starting
+    boot-services` is signaled.
+*   An IPC takes place between mount-encrypted and `bio_crypto_init` via a tmpfs
+    file. The reading and deletion of the tmpfs file is detailed in the
+    [IPC Mechanism] section.
+
+### Privileges
+
+*   `bio_crypto_init` runs minijail-ed and runs with user/group `biod`. Only the
+    files required for its functioning (i.e., the tmpfs file `/run/`, the
+    devnode to access the FPMCU, log directory inside
+    `/var/log/bio_crypto_init`) are mounted and visible inside the sandbox. See
+    the [minijail0 arguments] for a full explanation.
+
+### Untrusted input
+
+*   The only input is the `System_key` which is retrieved from the TPM anyway
+    during mount-encrypted execution. Thus, no additional or new input is being
+    fed to the feature.
+*   Additionally, the derived TPM-seed is saved in a tmpfs file which has a
+    user/group ownership as `biod` so only users `root` or `biod` can access the
+    file. Since `bio_crypto_init` runs only during `starting boot-services` and
+    the process along with the conf file ensures that the file is deleted after
+    execution, there is no additional threat of the `/tmp` file being corrupted.
+
+### Sensitive data
+
+*   The feature involves the storage of a `TPM_Seed` derived from the
+    `System_key` from TPM, in a file on tmpfs (the file is zeroed and deleted
+    once read by `bio_crypto_init`).
+
+### Attack surface
+
+*   In the event of the contents of the tmp file being read, the `TPM_Seed`
+    would not be of much use to the attacker, since the use of `HMAC_SHA256`
+    means the attacker would still not have access to the system key (brute
+    force trial of HMAC 256 would be required to guess the system salt required
+    to produce the TPM-seed).
+*   In the unlikely event of the contents of the tmp file being modified before
+    they are programmed into the FPMCU, FP unlock would fail (since the
+    encrypted templates would no longer be decrypted correctly, since the FPMCU
+    encryption key would have changed). The FP templates encryption key is a
+    combination of both the `TPM_seed` as well as the internal `SBP_Src_Key`
+    combined with a random salt, and since only the encrypted templates are
+    stored on the rootfs, the templates would simply be rendered useless. A
+    powerwash/recovery can help restore functionality of FP unlock, but new
+    templates would have to be registered.
+*   This code should not be accessible to remote attackers.
+
+### Implementation robustness
+
+*   `bio_crypto_init` uses two processes. A child process is spawned by
+    `bio_crypto_init` and the FPMCU programming is done on the child process.
+    The parent process waits for the child process to complete, or kills the
+    process if it exceeds a timeout limit. This ensures that the process doesn't
+    hang indefinitely.
+*   The feature uses tmpfs (`/run/bio_crypto_init/seed`) as an IPC mechanism to
+    transfer the `TPM_Seed` between mount-encrypted and `bio_crypto_init`.
+    Please see the [Alternatives Considered] and [Design Ideas] section
+    regarding rationale behind choosing tmpfs vis a vis socketpair/pipe.
+
+### Cryptography
+
+*   `HMAC_SHA256` is used to derived `TPM_Seed` from the `System_key` as
+    described in section [TPM seed generation].
+
+*   `HMAC_SHA256` is also used to derive the FPMCU’s encryption key. This is the
+    same as it was earlier; the only change is that source key has been updated
+    to also include the `TPM_Seed`.
+
+## Privacy Considerations
+
+This implementation should not have any adverse implications on Privacy (over
+and above existing functionality on ChromeOS). This provides security hardening
+for the fingerprint templates to prevent their retrieval and mis-use.
+
+[Fingerprint Authentication on ChromeOS]: ../fingerprint/fingerprint-authentication-design-doc.md
+[`SBP_Src_Key`]: ../fingerprint/fingerprint-authentication-design-doc.md#sbp-secret-generation
+[IPC Mechanism]: #ipc
+[minijail0 arguments]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform2/biod/init/bio_crypto_init.conf;l=36;drc=1fcefaa166e868069ad1b81091333ff75e0657f6
+[Design Ideas]: #design-ideas
+[TPM seed generation]: #seed-generation
+[Alternatives Considered]: #alt-considered
+[TPM]: https://www.chromium.org/developers/design-documents/tpm-usage/
+
+<!-- Images -->
+
+<!-- If you make changes to the docs below make sure to regenerate the PNGs by
+     appending "export/png" to the Google Drive link. -->
+
+<!-- https://docs.google.com/drawings/d/1d0ocdnEjsO26c3usP1FwgTZ7VwEr-4ydnC0WMhOnbLY -->
+
+[TPM Seed Diagram]: ../images/cros_fingerprint_tpm_seed.png
diff --git a/docs/fingerprint/fingerprint.md b/docs/fingerprint/fingerprint.md
index 67f7b4bf1f..0edd7a35cd 100644
--- a/docs/fingerprint/fingerprint.md
+++ b/docs/fingerprint/fingerprint.md
@@ -2,16 +2,20 @@
 
 [TOC]
 
+<!-- mdformat off(b/139308852) -->
 *** note
 NOTE: The build commands assume you are in the `~/trunk/src/platform/ec`
 directory inside the chroot.
 ***
+<!-- mdformat on -->
 
+<!-- mdformat off(b/139308852) -->
 *** note
 WARNING: When switching branches in the EC codebase, you probably want to nuke
 the `build` directory or at least the board you're working on: `rm -rf
 build/<board>` or `make clobber` to prevent compilation errors.
 ***
+<!-- mdformat on -->
 
 ## Software
 
@@ -24,32 +28,44 @@ The main source code for fingerprint sensor functionality lives in the
 The following "boards" (specified by the `BOARD` environment variable when
 building the EC code) are for fingerprint:
 
-MCU                   | Firmware (EC "board")                          | Dev Board
---------------------- | ---------------------------------------------- | ---------
-[STM32H743] (Cortex-M7) | `dartmonkey`<br>(aka `nocturne_fp`, `nami_fp`) | Icetower v0.2 <br>(Previously Dragontalon)
-[STM32F412] (Cortex-M4) | `bloonchipper`<br>(aka `hatch_fp`)             | Dragonclaw v0.2
+MCU                      | Sensor     | Firmware (EC "board")                          | Dev Board                                  | Nucleo Board
+------------------------ | ---------- | ---------------------------------------------- | ------------------------------------------ | ------------
+[STM32H743] \(Cortex-M7) | [FPC 1145] | `dartmonkey`<br>(aka `nocturne_fp`, `nami_fp`) | [Icetower v3] <br>(Previously Dragontalon) | [Nucleo H743ZI2]
+[STM32F412] \(Cortex-M4) | [FPC 1025] | `bloonchipper`<br>(aka `hatch_fp`)             | [Dragonclaw v0.3]                          | [Nucleo F412ZG]
+
+RAM and Flash details for each board are in the [Fingerprint MCU RAM and Flash]
+document.
+
+### Sensor Template Sizes
+
+Sensor     | Fingerprint Template Size
+---------- | --------------------------------
+[FPC 1145] | [~48 KB][FPC 1145 Template Size]
+[FPC 1025] | [~5 KB][FPC 1025 Template Size]
 
 ### Determining Hardware {#chromeos-config-fingerprint}
 
-If you have access to a shell on your Chromebook, you can use [Chrome OS Config]
+If you have access to a shell on your Chromebook, you can use [ChromeOS Config]
 to determine the FPMCU that it contains:
 
 ```bash
 (dut) $ cros_config /fingerprint board
 ```
 
-Alternatively, if you have a Chromium OS build, you can use [Chrome OS Config]
-in the chroot to determine the FPMCU:
+Alternatively, if you have a Chromium OS build, you can use [ChromeOS Config] in
+the chroot to determine the FPMCU:
 
 ```bash
 (chroot) $  cros_config_host -c /build/<BOARD>/usr/share/chromeos-config/yaml/config.yaml -m <MODEL> get /fingerprint board
 ```
 
+<!-- mdformat off(b/139308852) -->
 *** note
 **NOTE**: If you get an empty response when running these commands, the
-[Chrome OS Config] properties for fingerprint may not have been set up yet. See
-the [section on updating Chrome OS Config](#update-chromeos-config).
+[ChromeOS Config] properties for fingerprint may not have been set up yet. See
+the [section on updating ChromeOS Config](#update-chromeos-config).
 ***
+<!-- mdformat on -->
 
 ## Building FPMCU Firmware Locally
 
@@ -82,10 +98,12 @@ Before uploading a change to Gerrit via `repo upload`, you'll need to build
 *all* the boards in the EC codebase to make sure your changes do not break any
 others.
 
+<!-- mdformat off(b/139308852) -->
 *** note
 NOTE: If you forget to do this, do not worry. `repo upload` will warn you and
 prevent you from uploading.
 ***
+<!-- mdformat on -->
 
 ```bash
 (chroot) ~/trunk/src/platform/ec $ make buildall -j
@@ -103,6 +121,12 @@ See the [Unit Tests] documentation for details on how to [run the unit tests].
 
 ## Build and run the `host_command` fuzz test
 
+<!-- mdformat off(b/139308852) -->
+*** note
+NOTE: For more details on fuzzing, see [Fuzz Testing in ChromeOS].
+***
+<!-- mdformat on -->
+
 ```bash
 (chroot) ~/trunk/src/platform/ec $ make run-host_command_fuzz
 ```
@@ -146,11 +170,13 @@ kernel:
 
 ### `fp_updater.sh` and `bio_fw_updater`
 
+<!-- mdformat off(b/139308852) -->
 *** note
 **NOTE**: The auto-update process requires a working version of the firmware
 running on the FPMCU. See [Fingerprint Factory Requirements] for details on
 flashing in the factory.
 ***
+<!-- mdformat on -->
 
 [`fp_updater.sh`] and [`bio_fw_updater`] are wrappers around [`flashrom`] and
 require already-functioning RO firmware running on the FPMCU. It’s meant to be
@@ -168,12 +194,14 @@ user disables [hardware write protection]).
 
 ### `flash_fp_mcu`
 
+<!-- mdformat off(b/139308852) -->
 *** note
 **NOTE**: This tool is really just for us to use during development or during
 the RMA flow (must go through finalization again in that case). We never update
 RO in the field (can’t by design). See [Fingerprint Factory Requirements] for
 details on flashing in the factory.
 ***
+<!-- mdformat on -->
 
 [`flash_fp_mcu`] enables spidev and toggles some GPIOs to put the FPMCU (STM32)
 into bootloader mode. At that point it uses [`stm32mon`] to rewrite the entire
@@ -224,9 +252,8 @@ openssl genrsa -3 -out board/$BOARD/dev_key.pem 3072
 
 ### Resources
 
-*   https://sites.google.com/a/google.com/chromeos/resources/engineering/releng/signer-documentation
-*   https://sites.google.com/a/google.com/chromeos/paygen---payload
-*   https://b.corp.google.com/issues/77882970
+*   http://go/cros-signer-docs
+*   https://issuetracker.google.com/issues/77882970
 
 ## Signing
 
@@ -295,68 +322,121 @@ a lot easier during both development and testing.
 ## Power
 
 See [Measuring Power] for instructions on how to measure power with the
-fingerprint development boards.
+fingerprint development boards. *Make sure that any debuggers are completely
+disconnected.*
 
-### Dragonclaw v0.2
+### Dragonclaw v0.3
 
 ```bash
-(chroot) $  dut-control -t 60 pp3300_dx_mcu_mv pp3300_dx_fp_mv pp1800_dx_fp_mv pp3300_dx_mcu_mw pp3300_dx_fp_mw pp1800_dx_fp_mw
+(chroot) $ dut-control -t 60 pp3300_dx_mcu_mv pp3300_dx_fp_mv pp1800_dx_fp_mv pp3300_dx_mcu_mw pp3300_dx_fp_mw pp1800_dx_fp_mw
+```
+
+**Firmware Version**:
+`bloonchipper_v2.0.4277-9f652bb3-RO_v2.0.14348-e5fb0b9-RW.bin`
+
+#### MCU is idle
+
+```
+(chroot) $ dut-control fpmcu_slp_alt:off
+```
+
+```
+@@               NAME  COUNT  AVERAGE  STDDEV      MAX      MIN
+@@       sample_msecs    478   125.49   26.02   431.96    92.23
+@@    pp1800_dx_fp_mv    478  1800.00    0.00  1800.00  1800.00
+@@    pp1800_dx_fp_mw    478     0.00    0.00     0.00     0.00
+@@    pp3300_dx_fp_mv    478  3280.00    0.00  3280.00  3280.00
+@@    pp3300_dx_fp_mw    478     0.00    0.03     0.26     0.00
+@@   pp3300_dx_mcu_mv    478  3280.00    0.00  3280.00  3280.00
+@@   pp3300_dx_mcu_mw    478    21.78    0.06    23.09    21.78
 ```
 
-**Firmware Version**: `bloonchipper_v2.0.4277-9f652bb3`
+#### MCU in low power mode (suspend)
+
+```
+(chroot) $ dut-control fpmcu_slp_alt:on
+```
 
 ```
 @@               NAME  COUNT  AVERAGE  STDDEV      MAX      MIN
-@@       sample_msecs    128   469.05   33.79   641.75   399.90
-@@    pp1800_dx_fp_mv    128  1802.06    3.50  1808.00  1800.00
-@@    pp1800_dx_fp_mw    128     0.00    0.00     0.00     0.00
-@@    pp3300_dx_fp_mv    128  3296.00    0.00  3296.00  3296.00
-@@    pp3300_dx_fp_mw    128     0.00    0.03     0.26     0.00
-@@   pp3300_dx_mcu_mv    128  3288.00    0.00  3288.00  3288.00
-@@   pp3300_dx_mcu_mw    128    24.20    0.00    24.20    24.20
+@@       sample_msecs    488   122.99   26.37   458.47    92.69
+@@    pp1800_dx_fp_mv    488  1800.00    0.00  1800.00  1800.00
+@@    pp1800_dx_fp_mw    488     0.00    0.00     0.00     0.00
+@@    pp3300_dx_fp_mv    488  3287.79    1.29  3288.00  3280.00
+@@    pp3300_dx_fp_mw    488     0.01    0.04     0.26     0.00
+@@   pp3300_dx_mcu_mv    488  3283.38    3.95  3288.00  3280.00
+@@   pp3300_dx_mcu_mw    488     1.57    0.59     9.73     1.31
 ```
 
-### Dragontalon
+### Icetower v3
 
+<!-- mdformat off(b/139308852) -->
 *** note
-**NOTE**: The sensor doesn't work on Dragontalon, so the measurements below show
-zero for the sensor.
+**NOTE**: Icetower v0.1 has a hardware bug in the INA connections, so you cannot
+measure the 1.8V fingerprint sensor rail. See http://b/178098140.
+
+Additionally, before https://crrev.com/c/2689101, the sleep GPIOs were not
+configured correctly, so the change needs to be cherry-picked in order to
+measure releases before that point.
 ***
+<!-- mdformat on -->
 
 ```bash
-(chroot) $  dut-control -t 60 pp3300_h7_mv pp3300_h7_mw pp1800_fpc_mv pp1800_fpc_mw
+(chroot) $ dut-control -t 60 pp3300_dx_mcu_mv pp3300_dx_fp_mv pp3300_dx_mcu_mw pp3300_dx_fp_mw
+```
+
+**Firmware Version**:
+`dartmonkey_v2.0.2887-311310808-RO_v2.0.14340-6c1587ca7-RW.bin`
+
+#### MCU is idle
+
+```
+(chroot) $ dut-control fpmcu_slp_alt:off
 ```
 
-**Firmware Version**: `dartmonkey_v2.0.4017-9c45fb4b3`
+```
+@@               NAME  COUNT  AVERAGE  STDDEV      MAX      MIN
+@@       sample_msecs    523   114.85   18.33   386.55    88.95
+@@    pp3300_dx_fp_mv    523  3256.00    0.00  3256.00  3256.00
+@@    pp3300_dx_fp_mw    523     0.00    0.00     0.00     0.00
+@@   pp3300_dx_mcu_mv    523  3248.00    0.00  3248.00  3248.00
+@@   pp3300_dx_mcu_mw    523    43.86    0.10    43.91    43.65
+```
+
+#### MCU in low power mode (suspend)
 
 ```
-@@            NAME  COUNT  AVERAGE  STDDEV      MAX      MIN
-@@    sample_msecs   1502    39.96   13.14   379.43    22.31
-@@   pp1800_fpc_mv   1502     0.00    0.00     0.00     0.00
-@@   pp1800_fpc_mw   1502     0.00    0.00     0.00     0.00
-@@    pp3300_h7_mv   1502  3288.00    0.00  3288.00  3288.00
-@@    pp3300_h7_mw   1502     8.20    0.51    18.08     7.67
+(chroot) $ dut-control fpmcu_slp_alt:on
+```
+
+```
+@@               NAME  COUNT  AVERAGE  STDDEV      MAX      MIN
+@@       sample_msecs    501   119.79   14.72   381.92    89.22
+@@    pp3300_dx_fp_mv    501  3256.00    0.00  3256.00  3256.00
+@@    pp3300_dx_fp_mw    501     0.00    0.00     0.00     0.00
+@@   pp3300_dx_mcu_mv    501  3256.00    0.00  3256.00  3256.00
+@@   pp3300_dx_mcu_mw    501     5.74    0.28    11.98     5.73
 ```
 
-## Chrome OS Build (portage / ebuild)
+## ChromeOS Build (portage / ebuild)
 
-In order to use the fingerprint sensor with a given [Chrome OS board], a few
-things need to be configured for the [Chrome OS board].
+In order to use the fingerprint sensor with a given [ChromeOS board], a few
+things need to be configured for the [ChromeOS board].
 
 ### Enable biod USE flag
 
-The biod [`USE` flag] needs to be enabled for the [Chrome OS board]. This `USE`
+The biod [`USE` flag] needs to be enabled for the [ChromeOS board]. This `USE`
 flag
 [determines whether the `biod` daemon is built and installed][biod chromium-os].
 
-To enable the `USE` flag, update the `make.defaults` for the [Chrome OS board].
+To enable the `USE` flag, update the `make.defaults` for the [ChromeOS board].
 See the [`make.defaults` for the Hatch board][hatch make.defaults] as an
 example.
 
 #### Verifying biod is installed in the rootfs
 
 After enabling the `biod` [`USE` flag] and building the `biod` package for your
-target [Chrome OS board], the `biod` binary should be in the build directory:
+target [ChromeOS board], the `biod` binary should be in the build directory:
 
 ```bash
 (chroot) $ emerge-<BOARD> biod
@@ -370,7 +450,7 @@ target [Chrome OS board], the `biod` binary should be in the build directory:
 ### Update FPMCU_FIRMWARE
 
 `FPMCU_FIRMWARE` should be set to the set of fingerprint firmware that should be
-built and installed for the [Chrome OS board].
+built and installed for the [ChromeOS board].
 
 `FPMCU_FIRMWARE` is a [`USE_EXPAND` variable][`USE` flag],
 [defined in the base `make.defaults`][FPMCU_FIRMWARE make.defaults].
@@ -392,9 +472,11 @@ See the [Hatch baseboard `make.defaults`] for an example.
 Once you have added the `FPMCU_FIRMWARE` flag and rebuilt the
 [`chromeos-firmware-fpmcu` ebuild], the firmware will show up in the the chroot:
 
+<!-- mdformat off(b/139308852) -->
 *** note
 **NOTE**: This requires access to the [internal manifest].
 ***
+<!-- mdformat on -->
 
 ```bash
 (chroot) $ emerge-<BOARD> chromeos-firmware-fpmcu
@@ -410,18 +492,18 @@ firmware by setting `FPMCU_FIRMWARE="bloonchipper dartmonkey"`. The actual
 version numbers displayed will not necessarily match since the firmware is
 constantly updated.
 
-### Update Chrome OS Config {#update-chromeos-config}
+### Update ChromeOS Config {#update-chromeos-config}
 
-With "unibuild", the same OS image (build) for a given [Chrome OS board] is used
+With "unibuild", the same OS image (build) for a given [ChromeOS board] is used
 across multiple devices. Often there will be some devices that have a
 fingerprint sensor, some that do not, and even different sensors for the same
 board.
 
-Determining what fingerprint hardware is on a given [Chrome OS board] is thus
-done at runtime, using [Chrome OS Config].
+Determining what fingerprint hardware is on a given [ChromeOS board] is thus
+done at runtime, using [ChromeOS Config].
 
 The `fingerprint` config needs to be in the `model.yaml` for the given
-[Chrome OS board]. The [Chrome OS Config fingerprint] section describes the
+[ChromeOS board]. The [ChromeOS Config fingerprint] section describes the
 attributes for the `fingerprint` config in more detail.
 
 The [`ec_extras` attribute] needs to be set to the list of fingerprint firmware
@@ -429,54 +511,102 @@ that should be built as part of the build.
 
 See the [`model.yaml` for the Hatch board][hatch model.yaml] as an example.
 
-You can test your changes by
-[running `cros_config`](#chromeos-config-fingerprint). The Chrome OS Config
+Instead of crafting the `model.yaml` by hand, newer boards are moving to the
+[ChromeOS Project Configuration] model, where the config is generated using
+[Starlark]. The common [`create_fingerprint`] function can be used across models
+to configure the fingerprint settings. See the [Morphius `config.star`] for an
+example of how to call `create_fingerprint`. After you modify a `config.star`
+file you will need to [regenerate the config]. If you need to change many
+projects (e.g., modifying [`create_fingerprint`]), you can use the [`CLFactory`]
+tool.
+
+Once you have updated the config, you can test your changes by
+[running `cros_config`](#chromeos-config-fingerprint). The ChromeOS Config
 documentation has a [section on testing properties] that describes this in more
 detail.
 
-[`common/fpsensor`]: https://chromium.googlesource.com/chromiumos/platform/ec/+/master/common/fpsensor/
-[`driver/fingerprint`]: https://chromium.googlesource.com/chromiumos/platform/ec/+/master/driver/fingerprint
-[`nocturne_fp`]: https://chromium.googlesource.com/chromiumos/platform/ec/+/refs/heads/master/board/nocturne_fp/
-[`nami_fp`]: https://chromium.googlesource.com/chromiumos/platform/ec/+/refs/heads/master/board/nami_fp/
-[`hatch_fp`]: https://chromium.googlesource.com/chromiumos/platform/ec/+/refs/heads/master/board/hatch_fp/
-[`bloonchipper`]: https://chromium.googlesource.com/chromiumos/platform/ec/+/refs/heads/master/board/bloonchipper/
-[`dartmonkey`]: https://chromium.googlesource.com/chromiumos/platform/ec/+/refs/heads/master/board/dartmonkey/
+### SKUs
+
+The fingerprint sensor may only be included on certain SKUs for a given device.
+The fingerprint code uses [ChromeOS Config] to determine whether a device has a
+fingerprint sensor or not. For each SKU, there is an associated
+[fingerprint config][ChromeOS Config fingerprint]. [ChromeOS Config] determines
+the [SKU information][ChromeOS Config SKU] (and thus the
+[fingerprint config][ChromeOS Config fingerprint]) from [CBI Info]. The SKU for
+a given device can be found by viewing `chrome://system/#platform_identity_sku`.
+
+## Kernel Driver
+
+The kernel driver responsible for handling communication between the AP and
+FPMCU is called [`cros_ec`] and is enabled with [`CONFIG_CROS_EC`] in the Linux
+kernel. FPMCUs that are connected via SPI use [`cros_ec_spi.c`], while FPMCUs
+that are connected via UART use [`cros_ec_uart.c`].
+
+[`common/fpsensor`]: https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/common/fpsensor/
+[`driver/fingerprint`]: https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/driver/fingerprint
+[`nocturne_fp`]: https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/board/nocturne_fp/
+[`nami_fp`]: https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/board/nami_fp/
+[`hatch_fp`]: https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/board/hatch_fp/
+[`bloonchipper`]: https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/board/bloonchipper/
+[`dartmonkey`]: https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/board/dartmonkey/
 [hardware write protection]: ../write_protection.md
-[`flash_fp_mcu`]: https://chromium.googlesource.com/chromiumos/platform/ec/+/master/util/flash_fp_mcu
+[`flash_fp_mcu`]: https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/util/flash_fp_mcu
 [`stm32mon`]: https://chromium.googlesource.com/chromiumos/platform/ec/+/e1f3f89e7ea7945adddd0c2e6838f5e59856cff2/util/stm32mon.c#14
-[`futility`]: https://chromium.googlesource.com/chromiumos/platform/vboot_reference/+/master/futility/
-[`sign_official_build.sh`]: https://chromium.googlesource.com/chromiumos/platform/vboot_reference/+/master/scripts/image_signing/sign_official_build.sh
+[`futility`]: https://chromium.googlesource.com/chromiumos/platform/vboot_reference/+/HEAD/futility/
+[`sign_official_build.sh`]: https://chromium.googlesource.com/chromiumos/platform/vboot_reference/+/HEAD/scripts/image_signing/sign_official_build.sh
 [vboot_key_id]: https://chromium.googlesource.com/chromiumos/platform/vboot_reference/+/e7db36856ce418552637d1981c173d22dfe5bf39/firmware/2lib/include/2id.h#5
 [vb2_public_key]: https://chromium.googlesource.com/chromiumos/platform/vboot_reference/+/e7db36856ce418552637d1981c173d22dfe5bf39/firmware/2lib/include/2rsa.h#14
 [chatty-firmware-q]: https://groups.google.com/a/google.com/d/msg/chromeos-chatty-firmware/ZSg423wsFPg/26UbdGwjFQAJ
 [`fp_updater.sh`]: http://go/cros-fp-updater-nocturne-source
-[`bio_fw_updater`]: https://chromium.googlesource.com/chromiumos/platform2/+/refs/heads/master/biod/tools
+[`bio_fw_updater`]: https://chromium.googlesource.com/chromiumos/platform2/+/HEAD/biod/tools
 [`flashrom`]: https://chromium.googlesource.com/chromiumos/third_party/flashrom/
 [STM32F412]: https://www.st.com/resource/en/reference_manual/dm00180369.pdf
 [STM32H743]: https://www.st.com/resource/en/reference_manual/dm00314099.pdf
-[`board/nocturne_fp/dev_key.pem`]: https://chromium.googlesource.com/chromiumos/platform/ec/+/master/board/nocturne_fp/dev_key.pem
-[`timberslide`]: https://chromium.googlesource.com/chromiumos/platform2/+/master/timberslide
+[`board/nocturne_fp/dev_key.pem`]: https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/board/nocturne_fp/dev_key.pem
+[`timberslide`]: https://chromium.googlesource.com/chromiumos/platform2/+/HEAD/timberslide
 [cros_ec_debugfs]: https://chromium.googlesource.com/chromiumos/third_party/kernel/+/9db44685934a2e4bc9180ea2de87a6c429672395/drivers/platform/chrome/cros_ec_debugfs.c
 [Fingerprint Factory Requirements]: ./fingerprint-factory-requirements.md
-[Chromium OS test image]: https://chromium.googlesource.com/chromiumos/platform/factory/+/master/README.md#building-test-image
-[Chrome OS Config]: https://chromium.googlesource.com/chromiumos/platform2/+/master/chromeos-config/README.md
-[Chrome OS Config fingerprint]: https://chromium.googlesource.com/chromiumos/platform2/+/refs/heads/master/chromeos-config/README.md#fingerprint
-[section on testing properties]: https://chromium.googlesource.com/chromiumos/platform2/+/refs/heads/master/chromeos-config/README.md#adding-and-testing-new-properties
-[Chrome OS board]: https://chromium.googlesource.com/chromiumos/docs/+/master/developer_guide.md#Select-a-board
+[Chromium OS test image]: https://chromium.googlesource.com/chromiumos/platform/factory/+/HEAD/README.md#building-test-image
+[ChromeOS Config]: https://chromium.googlesource.com/chromiumos/platform2/+/HEAD/chromeos-config/README.md
+[ChromeOS Config fingerprint]: https://chromium.googlesource.com/chromiumos/platform2/+/HEAD/chromeos-config/README.md#fingerprint
+[section on testing properties]: https://chromium.googlesource.com/chromiumos/platform2/+/HEAD/chromeos-config/README.md#adding-and-testing-new-properties
+[ChromeOS board]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/developer_guide.md#Select-a-board
 [biod chromium-os]: https://chromium.googlesource.com/chromiumos/overlays/chromiumos-overlay/+/4ea72b588af3394cb9fd1c330dcf726472183dfd/virtual/target-chromium-os/target-chromium-os-1.ebuild#154
 [hatch make.defaults]: https://chromium.googlesource.com/chromiumos/overlays/board-overlays/+/2f075f0e7ce09d3eb460f3c529da463a6201276c/overlay-hatch/profiles/base/make.defaults#22
-[Hatch baseboard `make.defaults`]: https://chrome-internal.googlesource.com/chromeos/overlays/baseboard-hatch-private/+/refs/heads/master/profiles/base/make.defaults#17
-[hatch model.yaml]: https://chrome-internal.googlesource.com/chromeos/overlays/overlay-hatch-private/+/master/chromeos-base/chromeos-config-bsp-hatch-private/files/model.yaml
-[`ec_extras` attribute]: https://chromium.googlesource.com/chromiumos/platform2/+/refs/heads/master/chromeos-config/README.md#build_targets
+[Hatch baseboard `make.defaults`]: https://chrome-internal.googlesource.com/chromeos/overlays/baseboard-hatch-private/+/HEAD/profiles/base/make.defaults#17
+[hatch model.yaml]: https://chrome-internal.googlesource.com/chromeos/overlays/overlay-hatch-private/+/HEAD/chromeos-base/chromeos-config-bsp-hatch-private/files/model.yaml
+[`ec_extras` attribute]: https://chromium.googlesource.com/chromiumos/platform2/+/HEAD/chromeos-config/README.md#build_targets
 [FPMCU_FIRMWARE make.defaults]: https://chromium.googlesource.com/chromiumos/overlays/chromiumos-overlay/+/4ea72b588af3394cb9fd1c330dcf726472183dfd/profiles/base/make.defaults#157
 [`USE` flag]: https://devmanual.gentoo.org/general-concepts/use-flags/index.html
 [`USE` flags]: https://devmanual.gentoo.org/general-concepts/use-flags/index.html
 [biod release firmware]: https://chromium.googlesource.com/chromiumos/overlays/chromiumos-overlay/+/4ea72b588af3394cb9fd1c330dcf726472183dfd/chromeos-base/biod/biod-9999.ebuild#49
-[`chromeos-firmware-fpmcu` ebuild]: https://chrome-internal.googlesource.com/chromeos/overlays/chromeos-overlay/+/refs/heads/master/chromeos-base/chromeos-firmware-fpmcu/chromeos-firmware-fpmcu-9999.ebuild
-[firmware ebuild]: https://chrome-internal.googlesource.com/chromeos/overlays/chromeos-overlay/+/refs/heads/master/chromeos-base/chromeos-firmware-fpmcu/chromeos-firmware-fpmcu-9999.ebuild#40
-[`chromeos-fpmcu-release*` ebuilds]: https://chromium.googlesource.com/chromiumos/overlays/chromiumos-overlay/+/master/sys-firmware
-[internal manifest]: https://chromium.googlesource.com/chromiumos/docs/+/master/developer_guide.md#get-the-source-code
+[`chromeos-firmware-fpmcu` ebuild]: https://chrome-internal.googlesource.com/chromeos/overlays/chromeos-overlay/+/HEAD/chromeos-base/chromeos-firmware-fpmcu/chromeos-firmware-fpmcu-9999.ebuild
+[firmware ebuild]: https://chrome-internal.googlesource.com/chromeos/overlays/chromeos-overlay/+/HEAD/chromeos-base/chromeos-firmware-fpmcu/chromeos-firmware-fpmcu-9999.ebuild#40
+[`chromeos-fpmcu-release*` ebuilds]: https://chromium.googlesource.com/chromiumos/overlays/chromiumos-overlay/+/HEAD/sys-firmware
+[internal manifest]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/developer_guide.md#get-the-source-code
 [Unit Tests]: ../unit_tests.md
 [run the unit tests]: ../unit_tests.md#running
 [Measuring Power]: ./fingerprint-dev-for-partners.md#measure-power
 [dragonclaw]: ./fingerprint-dev-for-partners.md#fpmcu-dev-board
+[FPC 1145]: ../../driver/fingerprint/fpc/libfp/fpc1145_private.h
+[FPC 1025]: ../../driver/fingerprint/fpc/bep/fpc1025_private.h
+[FPC 1145 Template Size]: https://chromium.googlesource.com/chromiumos/platform/ec/+/127521b109be8aac352e80e319e46ed123360408/driver/fingerprint/fpc/libfp/fpc1145_private.h#46
+[FPC 1025 Template Size]: https://chromium.googlesource.com/chromiumos/platform/ec/+/127521b109be8aac352e80e319e46ed123360408/driver/fingerprint/fpc/bep/fpc1025_private.h#44
+[Dragonclaw v0.3]: ./fingerprint-dev-for-partners.md#fpmcu-dev-board
+[Icetower v3]: ./fingerprint-dev-for-partners.md#fpmcu-dev-board
+[Nucleo F412ZG]: https://www.digikey.com/en/products/detail/stmicroelectronics/NUCLEO-F412ZG/6137573
+[Nucleo H743ZI2]: https://www.digikey.com/en/products/detail/stmicroelectronics/NUCLEO-H743ZI2/10130892
+[CBI Info]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/design_docs/cros_board_info.md
+[ChromeOS Config SKU]: https://chromium.googlesource.com/chromiumos/platform2/+/HEAD/chromeos-config/README.md#identity
+[ChromeOS Project Configuration]: https://chromium.googlesource.com/chromiumos/config/+/HEAD/README.md
+[Starlark]: https://docs.bazel.build/versions/main/skylark/language.html
+[`create_fingerprint`]: https://chromium.googlesource.com/chromiumos/config/+/e1fa0d7f56eb3dd6e9378e4326de086ada46b7d3/util/hw_topology.star#444
+[Morphius `config.star`]: https://chrome-internal.googlesource.com/chromeos/project/zork/morphius/+/593b657a776ed6b320c826916adc9cd845faf709/config.star#85
+[regenerate the config]: https://chromium.googlesource.com/chromiumos/config/+/HEAD/README.md#making-configuration-changes-for-your-project
+[`CLFactory`]: https://chromium.googlesource.com/chromiumos/config/+/HEAD/README.md#making-bulk-changes-across-repos
+[Fingerprint MCU RAM and Flash]: ./fingerprint-ram-and-flash.md
+[`CONFIG_CROS_EC`]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/kernel/upstream/drivers/platform/chrome/Makefile;l=11;drc=a4e493ca59115fc0692151c1818e5aadf0e79ad0
+[`cros_ec`]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/kernel/upstream/drivers/platform/chrome/cros_ec.c
+[`cros_ec_spi.c`]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/kernel/upstream/drivers/platform/chrome/cros_ec_spi.c
+[`cros_ec_uart.c`]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/kernel/upstream/drivers/platform/chrome/cros_ec_uart.c
+[Fuzz Testing in ChromeOS]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/testing/fuzzing.md
diff --git a/docs/getting_started_quickly.md b/docs/getting_started_quickly.md
index 9b22dc64c7..52dc774300 100644
--- a/docs/getting_started_quickly.md
+++ b/docs/getting_started_quickly.md
@@ -3,127 +3,64 @@
 [TOC]
 
 The
-[Chromium OS Developer Guide](https://chromium.googlesource.com/chromiumos/docs/+/master/developer_guide.md)
+[Chromium OS Developer Guide](https://chromium.googlesource.com/chromiumos/docs/+/HEAD/developer_guide.md)
 and [README](../README.md) walk through the steps needed to fetch and build
 Chromium OS source. These steps can be followed to retrieve and build EC source
 as well. On the other hand, if your sole interest is building an EC image, the
 general developer guide contains some extra unneeded steps.
 
-The fastest possible way to build an EC image is to skip the Chromium OS chroot
-install entirely. The following steps have been tested on an Ubuntu 15.10 (Wily
-Werewolf) 64-bit host machine. Other distros / versions may be used, but
-toolchain incompatibilities may require extra debug.
-
 ## Building
 
-1.  Install build / dev tools:
+Here is a set of steps to set up a development environment to build EC images
+inside the Chromium OS chroot:
 
-    ```bash
-    sudo apt-get install git libftdi-dev libusb-dev libncurses5-dev gcc-arm-none-eabi
-    ```
 
-1.  Sync the cros-ec git repo:
+1.  Create a folder for your chroot:
 
     ```bash
-    git clone https://chromium.googlesource.com/chromiumos/platform/ec
+    mkdir chromiumos; cd chromiumos
     ```
 
-1.  Build your EC image:
+1.  Initialize the checkout in the current directory:
 
     ```bash
-    HOSTCC=x86_64-linux-gnu-gcc make BOARD=$board
+    repo init -u https://chromium.googlesource.com/chromiumos/manifest
     ```
 
-## External Dependencies
-
-Most boards are buildable, but some will fail due to dependencies on external
-binaries (such as [`futility`](#building-futility)). Also, some related tools
-(such as `flash_ec` and `servod`) must be run from the Chromium OS chroot. Here
-is a set of steps to setup a minimal development environment to build EC images
-from the Chromium OS chroot:
-
-1.  Create a folder for your chroot:
+1.  Update the working tree to the latest version:
 
     ```bash
-    mkdir cros-src; cd cros-src
+    repo sync -j <number of cores on your workstatsion>
     ```
 
-1.  Run
+1.  Enter the chroot (type your password for `sudo` if prompted):
 
     ```bash
-    repo init -u https://chromium.googlesource.com/chromiumos/manifest.git --repo-url https://chromium.googlesource.com/external/repo.git -g minilayout
-    ```
-
-1.  Edit `.repo/manifest.xml`, and add `groups="minilayout"` to the platform/ec
-    project, so the line becomes:
-
-    ```
-    <project path="src/platform/ec" name="chromiumos/platform/ec" groups="minilayout" />
+    cros_sdk
     ```
 
-1.  Run `repo sync`:
+1.  Select a target board
 
     ```bash
-    repo sync -j <number of cores on your workstatsion>
+    export BOARD=<target board>
     ```
 
-1.  Enter the chroot and enter your password for `sudo` if prompted:
-
-    ```bash
-    ./chromite/bin/cros_sdk
-    ```
+    See previous section for recommendations.
 
 1.  Set up your board:
 
     ```bash
-    ./setup_board --board=$BOARD
+    setup_board --board=${BOARD}
     ```
 
-    (ex. `./setup_board --board=glados`)
-
 1.  Build EC:
 
     ```bash
-    ./build_packages --board=$BOARD chromeos-ec
+    build_packages --board=${BOARD} chromeos-ec
     ```
 
 1.  Now, EC images for any board can be built with:
 
     ```bash
-    cd ~/trunk/src/platform/ec; make BOARD=$board -j
-    ```
-
-## Building `futility` outside the chroot {#building-futility}
-
-If you want to build the `futility` host tool outside the normal Chrome OS
-chroot self-contained environment, you can try the following
-
-1.  Install futility build dependencies:
-
-    ```bash
-    sudo apt-get install uuid-dev liblzma-dev libyaml-dev libssl-dev
-    ```
-
-1.  Get the vboot reference sources:
-
-    ```bash
-    git clone https://chromium.googlesource.com/chromiumos/platform/vboot_reference
-    ```
-
-1.  Build it:
-
-    ```bash
-    cd vboot_reference ; make
-    ```
-
-1.  Install it in `/usr/local/bin`:
-
-    ```bash
-    sudo make install
-    ```
-
-1.  Add `/usr/local/bin` to your default `PATH`:
-
-    ```bash
-    export PATH="${PATH}:/usr/local/bin"
+    cd ~/chromiumos/src/platform/ec; make BOARD=${BOARD} -j
     ```
diff --git a/docs/gitlab.md b/docs/gitlab.md
new file mode 100644
index 0000000000..2ebc5c60f7
--- /dev/null
+++ b/docs/gitlab.md
@@ -0,0 +1,153 @@
+# Gitlab CI
+
+The Zephyr EC Test Team uses external Gitlab CI jobs to generate code coverage
+reports. These CI jobs are defined in the `.gitlab-ci.yml` file in
+`platform/ec`.
+
+[TOC]
+
+## Running CI jobs locally
+
+For development purposes, it is possible to run the CI jobs on a local machine
+using Docker and `gitlab-runner`.
+
+Note: not all features of Gitlab CI are available when running builds locally.
+For example, the local runner cannot build dependencies specified in the
+`needs:` sections. (But you can run jobs individually). More details can be
+found in the [`gitlab-runner` docs]
+(https://docs.gitlab.com/runner/commands/#limitations-of-gitlab-runner-exec).
+
+### Installation
+
+First, you must [install Docker](https://docs.docker.com/get-docker/) on your
+system. This is out of the scope of this guide, but there are many resources
+on the Internet describing how to do this. Docker allows the CI jobs to run in a
+controlled environment using containers, ensuring that the jobs run consistently
+and without needing to pollute your own system with the many dependencies.
+
+Next, install the Gitlab Runner. This application is able interpret the
+`.gitlab-ci.yml` file, spawn Docker containers to run jobs, and report back
+results and artifacts. Usually, runners are deployed in fleets and configured to
+register with a Gitlab server, which can push CI jobs to individual runners to
+execute. However, it is also possible to use the runner in a purely local mode
+using `gitlab-runner exec`.
+
+Full instructions are available on the
+[Gitlab website](https://docs.gitlab.com/runner/install/), but the fastest way
+to get it for Debian-based systems is to download and install the package
+directly:
+
+```
+wget https://gitlab-runner-downloads.s3.amazonaws.com/latest/deb/gitlab-runner_amd64.deb
+sudo dpkg -i gitlab-runner_amd64.deb
+```
+
+### Running a Job
+
+Once Docker and the Gitlab Runner are installed, invoke it as follows. This
+takes place outside of the chroot environment.
+
+```
+(outside)
+mkdir ~/gitlab-runner-output  # Do once
+
+cd ~/chromiumos/src/platform/ec
+sudo gitlab-runner exec docker \
+    --docker-volumes "$HOME/chromiumos/:$HOME/chromiumos/" \
+    --docker-volumes "$HOME/gitlab-runner-output:/builds" \
+    <name of job>
+```
+
+Please note:
+  * `$HOME/chromiumos` should be adjusted to wherever your tree is checked out
+    to. The reason it is necessary to mount the entire source tree to the
+    Docker container (as opposed to just `platform/ec`, which is done
+    automatically) is because the runner needs access to the Git database in
+    order to clone the source code. Because the `platform/ec` repository is
+    governed by the `repo` tool, the Git database is actually located at
+    `$HOME/chromiumos/.repo/projects/src/platform/ec.git`. (The `.git` directory
+    in `platform/ec` is merely a symlink)
+  * The second mount causes the runner's work directory to be backed by a
+    directory on your own system so that you can examine the artifacts after the
+    job finishes and the container is stopped.
+  * `<name of job>` is one of the jobs defined in `.gitlab-ci.yml`, such as
+    `twister_coverage`.
+  * You may see error messages like `ERROR: Could not create cache adapter`.
+    These appear to be benign, although getting the cache to work might improve
+    subsequent build times. This may be investigated at a later date.
+
+### Accessing Artifacts
+
+If you used the command as shown above, all of the build artifacts and source,
+as checked out by the Gitlab runner, should be under `~/gitlab-runner-output`.
+This will persist after the container exits but also get overwritten again on
+the next run.
+
+## Gitlab runners
+
+The gitlab builds run on a number of [virtual and real machines](https://gitlab.com/groups/zephyr-ec/-/runners)
+which are currently at Simon's house, and cloud virtual machines.
+
+### Create a new VM
+
+* Visit https://pantheon.corp.google.com/compute/instances?onCreate=true&project=chromeos-ec-gitlab
+  * Click on instance-1
+  * Click create similar
+* Wait for new instance to be created
+* Click on SSH
+* Install docker
+```
+sudo apt-get remove docker docker-engine docker.io containerd runc
+sudo apt-get update
+sudo apt-get install \
+    ca-certificates \
+    curl \
+    gnupg \
+    lsb-release
+sudo mkdir -p /etc/apt/keyrings
+curl -fsSL https://download.docker.com/linux/debian/gpg | sudo gpg --dearmor -o /etc/apt/keyrings/docker.gpg
+echo \
+  "deb [arch=$(dpkg --print-architecture) signed-by=/etc/apt/keyrings/docker.gpg] https://download.docker.com/linux/debian \
+  $(lsb_release -cs) stable" | sudo tee /etc/apt/sources.list.d/docker.list > /dev/null
+sudo apt-get update
+sudo apt-get install docker-ce docker-ce-cli containerd.io docker-compose-plugin
+sudo docker run hello-world
+```
+* Install gitlab runner
+```
+sudo curl -L --output /usr/local/bin/gitlab-runner https://gitlab-runner-downloads.s3.amazonaws.com/latest/binaries/gitlab-runner-linux-amd64
+sudo chmod +x /usr/local/bin/gitlab-runner
+sudo useradd --comment 'GitLab Runner' --create-home gitlab-runner --shell /bin/bash
+sudo gitlab-runner install --user=gitlab-runner --working-directory=/home/gitlab-runner
+sudo gitlab-runner start
+```
+* Register new runner using command from https://gitlab.com/groups/zephyr-ec/-/runners (click on Register a group runner, click on show instructions, click on Linux)
+```
+sudo gitlab-runner register --url https://gitlab.com/ --registration-token TOKENGOESHERE
+Runtime platform                                    arch=amd64 os=linux pid=56156 revision=bbcb5aba version=15.3.0
+Running in system-mode.
+
+Enter the GitLab instance URL (for example, https://gitlab.com/):
+[https://gitlab.com/]:
+Enter the registration token:
+[TOKENGOESHERE]:
+Enter a description for the runner:
+[instance-2]: Cloud runner instance-2
+Enter tags for the runner (comma-separated):
+
+Enter optional maintenance note for the runner:
+
+Registering runner... succeeded                     runner=TOKENGOESHERE
+Enter an executor: docker, parallels, shell, docker-ssh+machine, custom, docker-ssh, ssh, virtualbox, docker+machine, kubernetes:
+docker
+Enter the default Docker image (for example, ruby:2.7):
+ruby:2.7
+Runner registered successfully. Feel free to start it, but if it's running already the config should be automatically reloaded!
+
+Configuration (with the authentication token) was saved in "/etc/gitlab-runner/config.toml"
+```
+
+* Install cleanup docker cleanup daily cron
+```
+( echo "0 3 * * * /usr/bin/docker system prune -f -a --volumes" ; sudo crontab -l -u root ) | sudo crontab -u root -
+```
diff --git a/docs/goma.md b/docs/goma.md
new file mode 100644
index 0000000000..843cf18e1e
--- /dev/null
+++ b/docs/goma.md
@@ -0,0 +1,52 @@
+# Ludicrous Speed Compilation with Goma
+
+[TOC]
+
+*** note
+At the moment, Goma is only available for Googlers.
+***
+
+All commands should be performed in the chroot.
+
+## Login to Goma
+
+First, login to Goma:
+
+``` shellsession
+$ goma_auth login
+```
+
+You'll be prompted to accept an agreement, and copy a URL into your
+browser for login.  Be sure to use your @google.com account.
+
+The login info should persist across reboots, so you'll only need to
+do this step once (or rarely, if you get logged out).
+
+## Start Goma
+
+Start Goma's `compiler_proxy` daemon.  It will run in the background.
+
+``` shellsession
+$ goma_ctl ensure_start
+```
+
+You'll need to do this each time you start your machine.
+
+## Compiling (Zephyr EC)
+
+Run `zmake` as you normally do, and just add the `--goma` flag.  For
+example:
+
+``` shellsession
+$ zmake --goma testall
+```
+
+jrosenth@ observed on a ThinkStation P920 that a clean `testall` with
+`--goma` takes only 1 minute 55 seconds, versus 8 minutes and 20
+seconds without, so it's worth setting up!
+
+## Compiling (Legacy EC)
+
+The `Makefile` doesn't yet support Goma, but this is planned for the
+future.  [b/214323409](https://issuetracker.google.com/214323409)
+tracks the progress.
diff --git a/docs/hammer.md b/docs/hammer.md
new file mode 100644
index 0000000000..6048f1c441
--- /dev/null
+++ b/docs/hammer.md
@@ -0,0 +1,199 @@
+# Hammer care and feeding
+
+Original: [go/hammercare](http://go/hammercare)
+
+Last updated: 2021-03-18
+
+[TOC]
+
+## Servo
+
+### Start servod
+
+```
+cros_sdk --no-ns-pid
+sudo servod --port=9000 -b hammer -c hammer.xml
+```
+
+### UART console
+
+The simplest solution for most people is to use the `dut-console` script.
+
+First, add this line into your .bashrc (or other shell init script; needed once
+only):
+``` bash
+alias dut-console="~/chromiumos/src/platform/dev/contrib/dut-console"
+```
+
+Then simply run `dut-console -c ec`. `dut-console` uses `cu` under the hood, and
+works like ssh - to leave, press `<ENTER> <~> <.> <ENTER>`.
+
+
+``` bash
+src/platform/dev/contrib/dut-console -p 9000 -c ec
+```
+
+## Build EC
+
+(Inside chroot)
+``` bash
+cd ~/trunk/src/platform/ec
+make BOARD=<BOARD> -j
+```
+
+## Flash EC
+
+### Prerequisites
+
+#### Find the USB VID:PID of the device
+
+USB VID:PID is listed in [hammer/variants.h](../board/hammer/variants.h).
+Many scripts below requires correct PID to work.
+
+#### Stop hammerd
+
+Remove rootfs verification:
+``` bash
+/usr/share/vboot/bin/make_dev_ssd.sh --remove_rootfs_verification --force
+```
+
+Reboot the DUT then rename hammerd
+``` bash
+mv /usr/bin/hammerd /usr/bin/hammerd.bak
+```
+
+### Hammer connected to Chromebook, flash via USB
+
+(Inside chroot) Copy-paste the script below to a file named
+"flash_hammer.usbremote", run
+``` bash
+bash flash_hammer.usbremote <BOARD> <VID:PID> <IP> [ro]
+```
+
+``` bash
+#!/bin/bash
+# flash_hammer.usbremote
+set -x -e
+
+BOARD=$1
+ID=$2
+IP=$3
+EXTRA="-d $ID"
+
+ssh $IP sh -c "'rm -f /usr/local/ec.bin'"
+scp ~/trunk/src/platform/ec/build/${BOARD}/ec.bin $IP:/usr/local/ec.bin
+
+if [ "$4" = 'ro' ]; then
+   ssh $IP sh -x -c "'usb_updater2 $EXTRA -j;
+   sleep 1.0;
+   usb_updater2 $EXTRA /usr/local/ec.bin;
+   sleep 0.5;
+   usb_updater2 $EXTRA -s;
+   usb_updater2 $EXTRA /usr/local/ec.bin'"
+else
+   ssh $IP sh -x -c "'usb_updater2 $EXTRA -w;
+   usb_updater2 $EXTRA -r; sleep 0.5;
+   usb_updater2 $EXTRA -s;
+   usb_updater2 $EXTRA /usr/local/ec.bin'"
+fi
+```
+
+### Hammer connected to Chromebook, flash via servo
+
+(Inside chroot) Copy-paste the script below to a file named "flash_hammer",
+run `bash flash_hammer <IP> </path/to/ec.bin>`
+
+``` bash
+#!/bin/bash
+# Recommended to use a USB 3.0 Ethernet adapter for this to work, otherwise the
+# network on the DUT will temporarily go down when the root USB hub is taken
+# down.
+
+set -e
+IP=$1
+shift
+
+# USB 2.0 root hub
+USBID="usb1"
+
+set -x
+
+# unbind, then rebind, the root hub (in the mean time, we'll start programming)
+ssh $IP sh -c "'echo $USBID > /sys/bus/usb/drivers/usb/unbind; sleep 3; echo $USBID > /sys/bus/usb/drivers/usb/bind'" &
+
+util/flash_ec --board=hammer --port 9000 --image "$@"
+```
+
+### Hammer connected via servo only
+
+Do not connect hammer to Chromebook in this case, or at least make sure
+Chromebook is either suspended (S3) or off (when put into programming mode,
+STM32 always prefers USB interface when available)
+
+For Servo V2:
+
+``` bash
+dut-control -p 9000 spi1_vref:pp3300 spi1_buf_en:on spi1_buf_on_flex_en:on
+util/flash_ec --board=hammer --port=9000 [--image=/path/to/ec.bin]
+
+# To disable power from servo to Hammer
+dut-control -p 9000 spi1_vref:off spi1_buf_en:off spi1_buf_on_flex_en:off
+```
+
+For Servo Micro (there is only one buffer in the power delivery path,
+so don't include the spi1_buf_on_flex_en control):
+
+``` bash
+dut-control -p 9000 spi1_vref:pp3300 spi1_buf_en:on
+util/flash_ec --board=hammer --port=9000 [--image=/path/to/ec.bin]
+
+# To disable power from servo to Hammer
+dut-control -p 9000 spi1_vref:off spi1_buf_en:off
+```
+
+### Hammer connected via POGO-PIN-USB to Linux
+
+So this is very similar to Hammer connected to poppy, flash via USB, but you
+are directly running commands on the machine connected to Hammer, so you don’t
+need to SSH to it.
+
+``` bash
+#!/bin/bash
+# flash_hammer.usblocal
+
+EXTRA=
+EC=build/${BOARD:-hammer}/ec.bin
+UPDATER=usb_updater2
+
+if [ -n "$ID" ]; then
+   EXTRA="-d $ID"
+fi
+
+if [ "$1" = 'ro' ]; then
+   "${UPDATER}" $EXTRA -j;
+   sleep 1.0;
+   "${UPDATER}" $EXTRA "${EC}";
+   sleep 1.0;
+   "${UPDATER}" $EXTRA -s;
+   "${UPDATER}" $EXTRA "${EC}";
+else
+   "${UPDATER}" $EXTRA -w;
+   "${UPDATER}" $EXTRA -r;
+   sleep 1.0;
+   "${UPDATER}" $EXTRA -s;
+   "${UPDATER}" $EXTRA "${EC}";
+fi
+
+# To use this script: BOARD=<BOARD> ID=<VID:PID> ./flash_hammer.usblocal [ro]
+```
+
+## Update touchpad firmware
+
+(Inside DUT)
+``` bash
+usb_updater2 --tp_update <FILE> --device=<VID:PID>
+```
+or
+``` bash
+ec_touchpad_updater -p <PID> <FILE>
+```
diff --git a/docs/i2c-debugging.md b/docs/i2c-debugging.md
index 7ab84f9d8d..4b6afc9a54 100644
--- a/docs/i2c-debugging.md
+++ b/docs/i2c-debugging.md
@@ -1,13 +1,13 @@
-I²C Debugging Tips
-==================
+# I²C Debugging Tips
 
-The EC codebase has functionality to help you debug I²C errors without
-pulling out the scope. Some of the debug functionality is disabled by
-default to save space, but can be enabled with the `CONFIG_I2C_DEBUG`
-option.
+The EC codebase has functionality to help you debug I²C errors without pulling
+out the scope. Some of the debug functionality is disabled by default to save
+space, but can be enabled with the `CONFIG_I2C_DEBUG` option.
 
-Tracing
--------
+For Zephyr EC builds, enable I²C  by adding `CONFIG_PLATFORM_EC_I2C_DEBUG=y` to
+one of your project's Kconfig files.
+
+## Tracing
 
 You can use the `i2ctrace` command to monitor (ranges of) addresses:
 
@@ -51,4 +51,4 @@ Note that `i2ctrace enable` will merge debug entries when possible:
 id port address
 -- ---- -------
 0     0 0x10 to 0x50
-```
\ No newline at end of file
+```
diff --git a/docs/ide-support.md b/docs/ide-support.md
index e8ab342073..1a8abda422 100644
--- a/docs/ide-support.md
+++ b/docs/ide-support.md
@@ -1,5 +1,7 @@
 # IDE Support
 
+This document explains how to configure IDEs to better support the EC codebase.
+
 [TOC]
 
 ## Odd File Types
@@ -12,16 +14,17 @@ Patterns                                              | Vague Type
 ----------------------------------------------------- | ----------
 `README.*`                                            | Text
 `Makefile.rules`, `Makefile.toolchain`                | Makefile
+`Makefile.ide`                                        | Makefile
 `gpio.wrap`                                           | C Header
 `gpio.inc`                                            | C Header
 `*.tasklist`, `*.irqlist`, `*.mocklist`, `*.testlist` | C Header
 
 ## IDE Configuration Primitives
 
-Due to the way most EC code has been structured, you can typically only safely
-inspect a configuration for a single image (RO or RW) for a single board. Thus,
-you need to specify the specific board/image pair when requesting defines and
-includes.
+EC firmware presents some unique challenges because it is designed to support a
+number of different MCUs and board configurations, each of which is split across
+separate RO (Read-Only) and RW (Read-Write) applications. For this reason, you
+must specify the specific board/image pair when requesting defines and includes.
 
 Command                                      | Description
 -------------------------------------------- | ------------------------------
@@ -34,49 +37,85 @@ You can use the `ide-config.sh` tool to generate a VSCode configuration that
 includes selectable sub-configurations for every board/image pair.
 
 1.  From the root `ec` directory, do the following:
+
+    ```bash
+    (outside) $ mkdir -p .vscode
+    ```
+
     ```bash
-    mkdir -p .vscode
-    ./util/ide-config.sh vscode all:RW all:RO | tee .vscode/c_cpp_properties.json
+    (chroot) $ ./util/ide-config.sh vscode all:RW all:RO | tee .vscode/c_cpp_properties.json
     ```
+
 2.  Open VSCode and navigate to some C source file.
+
 3.  Run `C/C++ Reset IntelliSense Database` from the `Ctrl-Shift-P` menu
+
 4.  Select the config in the bottom right, next to the `Select Language Mode`.
     You will only see this option when a C/C++ file is open. Additionally, you
     can select a configuration by pressing `Ctrl-Shift-P` and selecting the
     `C/C++ Select a Configuration...` option.
-5. Add the EC specific file associations and style settings.
-   Modify `.vscode/settings.json` to have the following elements:
-   ```json
-   {
-       "editor.rulers": [80],
-       /* C, Makefiles, ASM, Linkerfiles, Properties */
-       "editor.insertSpaces": false,
-       "editor.tabSize": 8,
-       /* Some exceptions based on current trends */
-       "[markdown]": {
-           "editor.insertSpaces": true,
-           "editor.tabSize": 2
-       },
-       "[python]": {
-           "editor.insertSpaces": true,
-           "editor.tabSize": 2
-       },
-       "[shellscript]": {
-           "editor.insertSpaces": true,
-           "editor.tabSize": 2
-       },
-       "[yaml]": {
-           "editor.insertSpaces": true,
-           "editor.tabSize": 2
-       },
-       "files.associations": {
-           "Makefile.*": "makefile",
-           "*.inc": "c",
-           "*.wrap": "c",
-           "*.tasklist": "c",
-           "*.irqlist": "c",
-           "*.mocklist": "c",
-           "*.testlist": "c"
-       }
-   }
-   ```
+
+5.  Add the EC specific file associations and style settings. Do the following
+    to copy the default settings to `.vscode/settings.json`:
+
+    ```bash
+    (outside) $ cp .vscode/settings.json.default .vscode/settings.json
+    ```
+
+## VSCode CrOS IDE
+
+CrOS IDE is a VSCode extension to enable code completion and navigation for
+ChromeOS source files.
+
+Support for `platform/ec` is not available out of the box (yet), but can be
+manually enabled following these steps.
+
+### Prerequisites
+
+Install CrOS IDE following the [quickstart guide]
+
+<!-- mdformat off(b/139308852) -->
+*** note
+NOTE: CrOS IDE uses the VSCode extension `clangd` for code completion and
+navigation. The installation of CrOS IDE disables the built-in
+`C/C++ IntelliSense` because it is not compatible with `clangd`.
+***
+<!-- mdformat on -->
+
+### Configure EC Board
+
+1.  Enter the EC repository:
+
+    ```bash
+    (chroot) $ cd ~/chromiumos/src/platform/ec
+    ```
+
+1.  Create a `compile_commands.json` for the all EC boards:
+
+    ```bash
+    (chroot) $ make all-ide-compile-cmds -j
+    ```
+
+1.  Select a particular board:
+
+    ```bash
+    (chroot) $ export BOARD=bloonchipper
+    ```
+
+1.  Copy the new `compile_commands.json` in the root of the EC repository:
+
+    ```bash
+    cp build/${BOARD}/RW/compile_commands.json .
+    ```
+
+Note: a single `compile_commands.json` can only cover one specific build
+configuration. Only the `compile_commands.json`placed in the root of the EC
+repository is considered active. When the build configuration changes (e.g. user
+wants to use a different board), repeat steps 3 and 4 to replace the active
+`compile_commands.json` file.
+
+To create a `compile_commands.json` for a specific EC board:
+
+```bash
+(chroot) $ make BOARD=${BOARD} ide-compile-cmds
+```
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new file mode 100644
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+++ b/docs/ite-ec-reflashing.md
@@ -0,0 +1,194 @@
+# ITE EC firmware reflashing via Servo: How it works
+
+This doc: [http://go/cros-ite-reflash-design](https://goto.google.com/cros-ite-ec-reflash-design)
+<br>
+First written: 2022-08-15
+<br>
+Last updated: 2022-08-24
+
+Familiarity with [Chromium OS](https://www.chromium.org/chromium-os) and
+[Embedded Controller (EC)](../README.md) development is assumed.
+
+[TOC]
+
+## Background
+
+### Other documents
+* [Reflashing an ITE EC](../util/iteflash.md)
+* Googlers, and Partners involved in ITE EC projects only:
+  [The State of ITE CrOS EC Reflashing](https://goto.google.com/cros-ite-ec-reflash-state)
+  * That document is not public, do not request access if you lack it.
+* `i2c-pseudo` [README](../extra/i2c_pseudo/README)
+* `i2c-pseudo` [Documentation.txt](../extra/i2c_pseudo/Documentation.txt)
+
+### Terminology
+
+**EC** refers to an
+[Embedded Controller](https://en.wikipedia.org/wiki/Embedded_controller)
+(microcontroller).
+
+**ITE EC** refers to the [ITE](http://www.ite.com.tw/)
+[IT8320](http://www.ite.com.tw/en/product/view?mid=96)
+[Embedded Controller (EC)](https://en.wikipedia.org/wiki/Embedded_controller)
+microcontroller when used as a Chromium OS / Chrome OS EC.
+
+**CrOS** refers to Chromium OS, Chrome OS, or both, depending on the context.
+The distinction between Chromium OS and Chrome OS is largely immaterial to this
+document.
+
+**DUT Controller Servo** refers to a device that provides direct access
+to various circuits on a Chrome OS device motherboard. As of this writing, the
+most common DUT controller [servos](https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/refs/heads/main/docs/servo.md) used by
+CrOS developers are
+[CR50 (CCD)](https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/refs/heads/main/docs/ccd.md),
+`C2D2`,
+[Servo Micro](https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/refs/heads/main/docs/servo_micro.md), and
+[Servo v2](https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/refs/heads/main/docs/servo_v2.md). (Note that
+[Servo v4](https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/refs/heads/main/docs/servo_v4.md) and
+[Servo v4.1](https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/refs/heads/main/docs/servo_v4p1.md) are **not**
+DUT Controller Servos. They are Hub Servos, and are typically used in conjection with a DUT Controller Servo. Hub Servos are not directly involved in EC reflashing.)  See also
+[Case-Closed Debug in Chromebooks and Servo Micro](https://chromium.googlesource.com/chromiumos/platform/ec/+/refs/heads/main/board/servo_micro/ccd.md).
+
+**Servod** refers to a piece of software that runs on a USB host and provides
+interfaces for controlling a Servo connected to the host as a USB device. See [servod](https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/refs/heads/main/docs/servod.md).
+
+## Core steps
+
+Two things need to happen:
+
+1.  Send special non-I2C waveforms over I2C clock and data lines to the ITE EC,
+    to enable a debug mode in the EC where it will respond at a predefined
+    I2C address as an I2C peripheral.
+    * This debug mode is implemented by ITE in silicon and/or immutable
+      firmware, it is not part of Chrome OS EC firmware. It is available even
+      if Chrome OS RO+RW firmware on the EC is corrupted.
+
+1.  Communicate with and control the ITE EC using its I2C-based debug mode. All
+    signals on the I2C bus in question are now actual I2C, with the ITE EC
+    acting as an I2C peripheral device. The EC firmware gets sent as I2C
+    payload.
+    * If the previous step is not successful, then the EC will not respond to
+      I2C messages.
+
+The DUT Controller Servo performs these steps.
+
+## Control flow
+
+[flash_ec](https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/util/flash_ec)
+is the user interface for all Chrome OS device EC reflashing via Servos.
+`servod` must be running to use `flash_ec`.
+
+### Original control flow, for Servo v2 only
+
+The original implementation of ITE EC reflashing via Servo is only compatible
+with Servo v2, due to interfacing directly with its FTDI USB to MPSSE IC
+(FTDI FT4232HL).
+
+1.  `flash_ec` tells `servod` to close its interface for controlling the
+    `Servo v2` FTDI USB device.
+    * This breaks the layering of `servod` as the interface through which
+      servos are controlled, and is a maintenance + complexity burden to
+      support in `servod`. No other servo I2C interfaces in `servod` support or
+      need this functionality of relinquishing control.
+1.  `flash_ec` invokes [iteflash](https://chromium.googlesource.com/chromiumos/platform/ec/+/refs/heads/main/util/iteflash.c).
+1.  `iteflash` takes control of the `Servo v2` FTDI USB device.
+1.  `iteflash` [bit-bangs](https://en.wikipedia.org/wiki/Bit_banging) the
+    special waveforms using the `Servo v2` FTDI USB device.
+1.  `iteflash` uses FTDI I2C functionality (not bit-banging) to talk I2C with
+    the ITE EC, including sending the EC firmware as payload in I2C messages.
+1.  `flash_ec` tells `servod` to reopen its `Servo v2` FTDI USB interface.
+
+### New control flow through servod, for all other DUT controller servo types
+
+1.  When `servod` starts, it creates a pseudo I2C adapter in Linux for every
+    servo I2C bus it controls, if the `i2c-pseudo` module is loaded.
+    * This pseudo I2C adapter can be used on the host system as if it were a
+      native I2C bus, including from userspace if the `i2c-dev` module is
+      loaded.
+    * For more information on the `i2c-pseudo` module see
+      [Reflashing an ITE EC](../util/iteflash.md), as well as `i2c-pseudo`'s
+      [README](../extra/i2c_pseudo/README) and
+      [Documentation.txt](../extra/i2c_pseudo/Documentation.txt).
+1.  `flash_ec` issues a `servod` command for the DUT controller servo to send
+    the special waveforms.
+    * For `Servo Micro` and `C2D2` all `servod` needs to do is issue a
+      servo console command, `enable_ite_dfu`, which triggers a
+      servo firmware function to perform the special waveforms.
+      * The servo does not know what kind of DUT it is connected to, thus the
+        `enable_ite_dfu` console commands are always available. The
+        special waveforms will not do anything useful unless the DUT has
+        an ITE EC.
+    * `CR50` (CCD) is mostly the same, except:
+      1.  CCD must be unlocked and the `ccd_i2c_en` CCD capability must be set
+          to `Always`.
+      1.  The `CR50` firmware function for sending the special waveforms is
+          invoked by a special I2C message, not a console command.
+      1.  `CR50` must reboot itself to perform the special waveforms. During
+          normal operation `CR50` has deliberate clock jitter which would
+          prevent accurately preforming the waveforms. This jitter cannot
+          safely be disabled, except on reset, and only while the `AP` is held
+          in reset.
+    * [Future] If we were to support this control flow with `Servo v2`, the
+      cleanest way would be to move the FTDI-based bit-banging of the
+      special waveforms from `iteflash` into `servod` itself, as a C/C++
+      extension, so that `flash_ec` can trigger it with a `servod` command the
+      same as for other servo types. This would allow removing the hack in
+      `servod` to relinquish control of the `Servo v2` FTDI USB interface.
+      * Proof-of-concept [CL:1522847](https://crrev.com/c/1522847) adds support
+        for using Servo v2 via `servod`. However as of this writing that CL
+        ([patchset 14](https://crrev.com/c/1522847/14)) only changes the I2C
+        communication path, it does NOT move the special waveforms into
+        `servod`, which is needed to remove the `servod` I2C interface
+        close + reopen hack and fully merge the Servo v2 ITE EC reflashing into
+        this new control flow.
+1.  `flash_ec` asks `servod` for the local Linux i2c-dev path of the
+    DUT Controller Servo's DUT-connected I2C interface (which is backed by
+    `servod` itself via the `i2c-pseudo` module).
+1.  `flash_ec` invokes `iteflash`, passing it the i2c-dev path given by
+    `servod`.
+1.  `iteflash` performs the EC firmware update via the i2c-dev interface.
+
+## Why `i2c-pseudo` and alternative implementations considered
+
+Instead of using `i2c-dev` Linux I2C interfaces, `iteflash` could communicate
+directly with `servod` using a custom protocol. This would make `iteflash`
+dependent on `servod` and whatever custom protocol we come up with, as there is
+no standard userspace<->userspace I2C interface to implement.
+
+In the future we may choose to implement Servo I2C interfaces as actual
+host-side Linux drivers, which `servod` would use via `i2c-dev`
+(which it supports already!). Since the `flash_ec` and `iteflash` portions of
+this process are built around `i2c-dev` now, they should continue working with
+no changes needed for this scenario.
+
+Why bother with i2c-pseudo at all then? Why not go straight to reimplementing
+the Servo I2C interfaces as new Linux I2C adapter drivers, instead of
+implementing the new `i2c-pseudo` driver?
+
+Rearchitecting the Servo I2C interfaces is not something to be considered
+lightly, and not worthwhile just for ITE EC reflashing. By staying with the
+existing `servod` Servo I2C implementations we have not introduced any
+dependency on new kernel modules for *existing* `servod` functionality. Only
+the new ITE EC reflashing functionality depends on `i2c-pseudo`. As with
+`i2c-pseudo` we would need to rely on out-of-tree kernel module distribution
+for these new Servo I2C modules until eventual upstream acceptance +
+percolation down to distribution Linux kernels, with no guarantee of acceptance
+for our obscure Servo hardware. Depending on a new kernel module for this one
+new function of ITE EC reflashing is one thing. Requiring new modules for all
+`servod` use would be quite another. Realistically we would need to maintain
+fallback code in `servod` to use its existing internal Servo I2C interface
+implementations when the kernel ones aren't available, but that has a
+maintenance cost too. These same issues would be faced with every new
+generation of Servo, so this broad Servo + `servod` architectural change is not
+something to be considered lightly or just for ITE EC reflashing.
+
+`i2c-pseudo` has potential uses in the CrOS ecosystem beyond ITE EC reflashing.
+A big one is mocking I2C interfaces for driver and system tests. There is the
+longstanding `i2c-stub` module for this purpose, but its functionality is
+limited compared to `i2c-pseudo`, not all I2C device behavior can be modeled
+with `i2c-stub`. Also by having the `servod` I2C pseudo interfaces, one can
+conveniently use the standard Linux I2C command line tools
+(i2cget(8), i2cset(8), i2ctransfer(8), etc) for interfacing with Servo and DUT
+I2C devices. While it is unlikely that i2c-pseudo will have any use in CrOS
+itself, it is expected to have further uses in both developer tooling and
+code tests.
diff --git a/docs/low_battery_startup.md b/docs/low_battery_startup.md
index de346546c8..c82268a308 100644
--- a/docs/low_battery_startup.md
+++ b/docs/low_battery_startup.md
@@ -1,8 +1,8 @@
 # Configuring the EC for Low-Battery Startup
 
 Near the bottom of charge, starting up a ChromeOS device can be a tricky
-proposition.  Several features interact to make it difficult to reliably turn on
-the machine without browning out.  Over the years, a variety of configuration
+proposition. Several features interact to make it difficult to reliably turn on
+the machine without browning out. Over the years, a variety of configuration
 options have been written to maximize ChromeOS's compatibility with the basic
 user expectation,
 
@@ -26,23 +26,23 @@ which are available.
 ### Battery and Charging Circuit
 
 For the most part, ChromeOS device power systems are much like other laptop
-battery power systems.  A variable-voltage rail is connected to the battery via
-a series of cutoff MOSFETs.  Several system power rails derive their power from
-the system's variable-voltage rail.  Mains power is delivered to the
-variable-voltage system rail by a buck/boost charging circuit.  Mains power is
-itself rectified, isolated, and stepped down by an external power supply.
+battery power systems. A variable-voltage rail is connected to the battery via a
+series of cutoff MOSFETs. Several system power rails derive their power from the
+system's variable-voltage rail. Mains power is delivered to the variable-voltage
+system rail by a buck/boost charging circuit. Mains power is itself rectified,
+isolated, and stepped down by an external power supply.
 
 During most of the battery charge, the charger operates in current mode, acting
 as a constant current source that delivers current to the variable-voltage rail.
-Load transients are served by the capacitance on the rail and the battery.  By
+Load transients are served by the capacitance on the rail and the battery. By
 superposition, load transients during the charge don't necessarily draw current
 from the battery, they may just reduce the current flow into the battery.
 
 References to AC power in the EC codebase are actually references to an external
-power supply's DC source.  External supplies that are actually USB-PD-speaking
+power supply's DC source. External supplies that are actually USB-PD-speaking
 battery packs are indistinguishable from AC/DC adapters as far as the EC is
-concerned.  Variables and functions which refer to external supplies all refer
-to them as 'AC', though.
+concerned. Variables and functions which refer to external supplies all refer to
+them as 'AC', though.
 
 ### Source Current Negotiation
 
@@ -50,13 +50,13 @@ A device may draw power from an AC adapter via a few methods.
 
 #### USB BC1.2 Current Sources
 
-BC1.2 negotiation is usually managed entirely by an external IC.  Once it is
-complete, the EC limits itself to 2.4A max.  Additionally, the charger may be
+BC1.2 negotiation is usually managed entirely by an external IC. Once it is
+complete, the EC limits itself to 2.4A max. Additionally, the charger may be
 configured to switch to an input voltage regulation mode if the input voltage
 begins to sag too low.
 
 Ideally, the input source provides a voltage droop, such that it is not quite
-overloaded at the input voltage regulation setpoint of about 4.5V.  Thus, 4.5V
+overloaded at the input voltage regulation setpoint of about 4.5V. Thus, 4.5V
 serves as a reasonable reference voltage for the charger to use when it is in an
 input voltage-regulation mode.
 
@@ -68,45 +68,44 @@ See also `driver/bc12/max14637.c:bc12_detect()`.
 #### USB-PD Sources
 
 High-current power supplies are negotiated via the USB Type C Current Source and
-USB Power Delivery specifications (PD).  PD sources must support Type-C Current
-Source, but the reverse is not true.  Both types of current sources are managed
+USB Power Delivery specifications (PD). PD sources must support Type-C Current
+Source, but the reverse is not true. Both types of current sources are managed
 via the PD protocol module in the EC codebase.
 
 Type-C Current Source capabilities of up to 15W (3A, 5V) are advertised via
-analog signaling alone.  Via digital communication in the PD protocol, much
-higher power states may be negotiated.  However, higher power states also
-usually run at a higher voltage state as well.  Any time the voltage level is
-changing, the power sink (the ChromeOS device) must lower its power consumption
-during the transient.  The standby current level is governed by
-`CONFIG_CHARGER_INPUT_CURRENT`.
-
-PD port partners are capable of both soft and hard resets.  Hard resets will
+analog signaling alone. Via digital communication in the PD protocol, much
+higher power states may be negotiated. However, higher power states also usually
+run at a higher voltage state as well. Any time the voltage level is changing,
+the power sink (the ChromeOS device) must lower its power consumption during the
+transient.
+
+PD port partners are capable of both soft and hard resets. Hard resets will
 cause a dead-bus state for a brief interval before PD can renegotiate, from
-scratch, because it is intended to emulate a cable disconnect.  Therefore, a
-hard reset without a connected battery will brownout the Chromebook.
+scratch, because it is intended to emulate a cable disconnect. Therefore, a hard
+reset without a connected battery will brownout the Chromebook.
 
 ### Locked and Unlocked Firmware
 
 The Verified Boot implementation normally limits the complexity of the code
-which executes in the locked Read-Only firmware package.  The consequences for
+which executes in the locked Read-Only firmware package. The consequences for
 the EC are:
 
-- Locked RO EC firmware does not process any digital PD messages at all, it only
-  recognizes the analog advertisement of USB Current Source (15W max).
-- Installation of user-provided firmware is supported, but the write-protect pin
-  must be cleared to enable it.
-- On recent systems, write-protect is cleared by removing the system battery.
+-   Locked RO EC firmware does not process any digital PD messages at all, it
+    only recognizes the analog advertisement of USB Current Source (15W max).
+-   Installation of user-provided firmware is supported, but the write-protect
+    pin must be cleared to enable it.
+-   On recent systems, write-protect is cleared by removing the system battery.
 
 ### ChromeOS `powerd`
 
 The power management daemon provided by ChromeOS displays a "low-power charger"
 warning message via the system tray whenever the charger is limited to less than
-20W.  Therefore, if a USB-PD source is restricted to analog signaling, or a
-BC1.2 source is connected, the user gets alerted to the situation.
+20W. Therefore, if a USB-PD source is restricted to analog signaling, or a BC1.2
+source is connected, the user gets alerted to the situation.
 
 Systems that can run on very little power may be rapidly charged with a 15W
 charger, while a high power system may require a 40W state or more for a decent
-battery charging user experience.  Therefore, a board's overlay may override the
+battery charging user experience. Therefore, a board's overlay may override the
 warning threshold by replacing `/usr/share/power_manager/usb_min_ac_watts` in
 the board's filesystem.
 
@@ -116,7 +115,7 @@ See also `platform2/power_manager/` source code.
 
 Under normal conditions, the battery pack is equipped with a management IC which
 is solely responsible for the safety of the battery, measurement of the state of
-charge, and the balance of its cells.  Examples include (but are not limited to)
+charge, and the balance of its cells. Examples include (but are not limited to)
 the TI BQ40Z50 and Renesas RAJ240.
 
 However, after very long periods of rest without a battery charging cycle, the
@@ -124,7 +123,7 @@ natural self-discharge rate of each cell will cause them to diverge somewhat
 from each other.
 
 Some IC's can be configured to report a pack total state of charge of zero if
-any one cell's voltage is below a certain threshold.  However, many do not.
+any one cell's voltage is below a certain threshold. However, many do not.
 Therefore, after an extended rest period, one cell can be very close to the cell
 undervoltage cutoff threshold, even though the pack as a whole is considered to
 be at 3% charge or more.
@@ -132,14 +131,14 @@ be at 3% charge or more.
 ### Power Profile During Boot
 
 The power profile during the boot sequence is substantially different than that
-seen during typical use.  Dynamic voltage and frequency scaling of the AP is
-partially governed by the temperature of the processor core.  As the processor
+seen during typical use. Dynamic voltage and frequency scaling of the AP is
+partially governed by the temperature of the processor core. As the processor
 gets hotter, it will reduce its maximum core voltage and frequency to settle out
-at some maximum design junction temperature for the core.  For passively cooled
+at some maximum design junction temperature for the core. For passively cooled
 devices, the profile may also be chosen to limit the external case temperature.
 
-At startup, the case and core are cold.  The bootloaders and kernel are also
-optimized to boot as fast as possible for a responsive user experience.  So, the
+At startup, the case and core are cold. The bootloaders and kernel are also
+optimized to boot as fast as possible for a responsive user experience. So, the
 power drawn during the boot is much higher than that seen during typical
 productivity and entertainment tasks.
 
@@ -148,17 +147,15 @@ productivity and entertainment tasks.
 After verification and optional update of the EC's RW firwmare, Depthcharge will
 poll the EC to verify that it is allowed to proceed to boot to the kernel.
 
-It does this by polling via the:
-- `EC_CMD_CHARGE_STATE` host command.
-- `CHARGE_STATE_CMD_GET_PARAM` subcommand.
-- `CS_PARAM_LIMIT_POWER` parameter.
+It does this by polling via the: - `EC_CMD_CHARGE_STATE` host command. -
+`CHARGE_STATE_CMD_GET_PARAM` subcommand. - `CS_PARAM_LIMIT_POWER` parameter.
 
 When the EC returns 0, power draw by the AP is unlimited and depthcharge resumes
-the boot.  If the EC fails to return 0 in three seconds, depthcharge shuts down.
+the boot. If the EC fails to return 0 in three seconds, depthcharge shuts down.
 
 See also vb2ex_ec_vboot_done() in Depthcharge, and option
-`CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW` in the EC.  By default, this option
-is not set, and the EC immediately allows the boot to proceed.
+`CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW` in the EC. By default, this option is
+not set, and the EC immediately allows the boot to proceed.
 
 ## Example Low-Battery Boot Sequences and Configurations
 
@@ -166,49 +163,49 @@ Most ChromeOS devices power needs will be met by one of the following templates.
 
 ### Low-Power Device
 
-Low-power devices require 15W or less of power to boot the AP.  The battery pack
+Low-power devices require 15W or less of power to boot the AP. The battery pack
 is robust enough to support the device during brief intervals of PD negotiation
 without browning out.
 
 ```
-#define CONFIG_CHARGER_INPUT_CURRENT 512
+#define CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT 512
 #define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 1
 ```
 
 A detailed boot sequence under this configuration, with a low battery and
 available AC power via a USB-PD charger:
 
-1. EC ROM bootloader loads and jumps to the EC's read-only firmware image.
-1. RO firmware negotiates a 15W state via Current Source analog signaling and
-   begins charging the battery with it.
-1. RO firmware verifies conditions to begin booting the AP:
-     - Battery state of charge > 1%
-     - OR charger power greater or equal to 15W (met by Current Source analog
-       signaling).
-1. AP firmware performs verification of the EC's RW image, upgrades it if
-   necessary, and sysjumps the EC to it.
-1. AP firmware queries the charge state limit power flag via EC-host command,
-   and the EC immediately responds that it is clear.
-1. Depthcharge continues the boot.
-     1. In parallel with kernel loading and Linux's boot, the EC performs PD
-        negotiation.  Charger power lowers to 2.5W for up to 500ms as the source
+1.  EC ROM bootloader loads and jumps to the EC's read-only firmware image.
+1.  RO firmware negotiates a 15W state via Current Source analog signaling and
+    begins charging the battery with it.
+1.  RO firmware verifies conditions to begin booting the AP:
+    -   Battery state of charge > 1%
+    -   OR charger power greater or equal to 15W (met by Current Source analog
+        signaling).
+1.  AP firmware performs verification of the EC's RW image, upgrades it if
+    necessary, and sysjumps the EC to it.
+1.  AP firmware queries the charge state limit power flag via EC-host command,
+    and the EC immediately responds that it is clear.
+1.  Depthcharge continues the boot.
+    1.  In parallel with kernel loading and Linux's boot, the EC performs PD
+        negotiation. Charger power lowers to 2.5W for up to 500ms as the source
         transitions from vSafe5V to its highest supported voltage (15V or 20V
-        are typical).  During this transition time some power is drawn from the
+        are typical). During this transition time some power is drawn from the
         battery.
-     1. After PD negotiation is complete, the EC raises the charger current
+    1.  After PD negotiation is complete, the EC raises the charger current
         limit to the negotiated limit (45W is typical).
 
 ### Low-Power Device Startup With Marginal Battery Compatibility
 
 Similar in configuration to the low-power device startup, this system enables
 additional options to maximize its compatibility with marginal batteries near
-the bottom of charge.  The Grunt family is an exemplar.  This system will
-complete software sync with less than 15W of power, but may require more power
-to boot the kernel and get to the login screen.
+the bottom of charge. The Grunt family is an exemplar. This system will complete
+software sync with less than 15W of power, but may require more power to boot
+the kernel and get to the login screen.
 
 ```
 /* Limit battery impact during PD voltage changes. */
-#define CONFIG_CHARGER_INPUT_CURRENT 512
+#define CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT 512
 
 /* Distrust the battery SOC measurement a bit. */
 #define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 3
@@ -229,85 +226,81 @@ battery must support per-cell voltage measurement.
 A detailed boot sequence under this configuration, with a low battery and
 available AC power:
 
-1. EC ROM bootloader loads and jumps to the EC's read-only firmware image.
-1. RO firmware negotiates a 15W state via Current Source analog signaling and
-   begins charging the battery with it.
-1. RO firmware verifies conditions to begin booting the AP:
-     - battery state of charge >= 3% AND cell imbalance < 200 mV
-     - OR battery state of charge >= 5%
-     - OR charger power greater or equal to 15W (met by Current Source analog
-       signaling).
-1. AP firmware performs verification of the EC's RW image, upgrades it if
-   necessary, and sysjumps the EC to it.
-1. AP firmware polls the charge state limit power flag via EC-host command for
-   up to 3 seconds, in 50ms intervals.  The EC will return `1` (power limited)
-   so long as the charger power is < 15.001W and the battery is less than 3%.
-     1. Meanwhile, the EC performs PD negotiation.  Charger power lowers to 2.5W
+1.  EC ROM bootloader loads and jumps to the EC's read-only firmware image.
+1.  RO firmware negotiates a 15W state via Current Source analog signaling and
+    begins charging the battery with it.
+1.  RO firmware verifies conditions to begin booting the AP:
+    -   battery state of charge >= 3% AND cell imbalance < 200 mV
+    -   OR battery state of charge >= 5%
+    -   OR charger power greater or equal to 15W (met by Current Source analog
+        signaling).
+1.  AP firmware performs verification of the EC's RW image, upgrades it if
+    necessary, and sysjumps the EC to it.
+1.  AP firmware polls the charge state limit power flag via EC-host command for
+    up to 3 seconds, in 50ms intervals. The EC will return `1` (power limited)
+    so long as the charger power is < 15.001W and the battery is less than 3%.
+    1.  Meanwhile, the EC performs PD negotiation. Charger power lowers to 2.5W
         for up to 500ms as the source transitions from vSafe5V to its highest
         supported voltage (15V or 20V are typical).
-     1. After negotiation is complete, the EC raises the charger current limit
+    1.  After negotiation is complete, the EC raises the charger current limit
         to the negotiated limit (45W is typical).
-     1. The EC returns 0 (unlimited) on the next `LIMIT_POWER` request.
-1. Depthcharge continues to boot Linux.
-
+    1.  The EC returns 0 (unlimited) on the next `LIMIT_POWER` request.
+1.  Depthcharge continues to boot Linux.
 
 ### High-Power Boot Device Startup
 
 A "high-power device" in this case is one that requires significantly more than
-15W of power to boot the AP.  These devices may complete software sync at 15W or
-less.  Very briefly drawing current out of the battery does not cause a
-brownout.
+15W of power to boot the AP. These devices may complete software sync at 15W or
+less. Very briefly drawing current out of the battery does not cause a brownout.
 
 Example configuration:
 
 ```
-#define CONFIG_CHARGER_INPUT_CURRENT 512
+#define CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT 512
 #define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 3
 #define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 15000
 #define CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW 27000
 ```
 
-Where the low-power device specified a threshold that just barely
-requires PD negotiation to happen before booting, this device has a definite
-minimum power to boot Linux (27W).  A detailed boot sequence under this
-configuration, with a low battery and available AC power:
-
-1. EC ROM bootloader loads and jumps to the EC's read-only firmware image.
-1. RO firmware negotiates a 15W state via Current Source analog signaling and
-   begins charging the battery with it.
-1. RO firmware verifies conditions to begin booting the AP:
-    - battery state of charge >= 3%
-    - OR charger power greater or equal to 15W (met by Current Source analog
-      signaling).
-1. AP firmware performs verification of the EC's RW image, upgrades it if
-  necessary, and sysjumps the EC to it.
-1. AP firmware polls the charge state limit power flag via EC-host command for
-   up to 3 seconds, in 50ms intervals.  The EC will return `1` (power limited)
-   so long as the charger power is < 27W and the battery is less than 3%.
-     1. Meanwhile, the EC performs PD negotiation.  Charger power lowers to 2.5W
+Where the low-power device specified a threshold that just barely requires PD
+negotiation to happen before booting, this device has a definite minimum power
+to boot Linux (27W). A detailed boot sequence under this configuration, with a
+low battery and available AC power:
+
+1.  EC ROM bootloader loads and jumps to the EC's read-only firmware image.
+1.  RO firmware negotiates a 15W state via Current Source analog signaling and
+    begins charging the battery with it.
+1.  RO firmware verifies conditions to begin booting the AP:
+    -   battery state of charge >= 3%
+    -   OR charger power greater or equal to 15W (met by Current Source analog
+        signaling).
+1.  AP firmware performs verification of the EC's RW image, upgrades it if
+    necessary, and sysjumps the EC to it.
+1.  AP firmware polls the charge state limit power flag via EC-host command for
+    up to 3 seconds, in 50ms intervals. The EC will return `1` (power limited)
+    so long as the charger power is < 27W and the battery is less than 3%.
+    1.  Meanwhile, the EC performs PD negotiation. Charger power lowers to 2.5W
         for up to 500ms as the source transitions from vSafe5V to its highest
         supported voltage (15V or 20V are typical).
-     1. After negotiation is complete, the EC raises the charger current limit
+    1.  After negotiation is complete, the EC raises the charger current limit
         to the negotiated limit (45W is typical).
-     1. The EC returns 0 (unlimited) on the next `LIMIT_POWER` request.
-1. Depthcharge continues to boot Linux.
-
+    1.  The EC returns 0 (unlimited) on the next `LIMIT_POWER` request.
+1.  Depthcharge continues to boot Linux.
 
 ### High-Power SwSync Device Startup
 
 Like the high-power boot device startup, these devices draw less than 15W during
 most of the software sync process, but may briefly exceed 15W during short
-intervals of software sync.  However, there is substantial risk of brownout
-during those intervals unless the battery is charged up a bit first.  Therefore,
+intervals of software sync. However, there is substantial risk of brownout
+during those intervals unless the battery is charged up a bit first. Therefore,
 they strictly require 1% battery capacity to perform software sync.
 Additionally, this configuration requires PD negotiation to be complete prior to
-performing a no-battery boot.  Nami is an exemplar.
-
+performing a no-battery boot. Nami is an exemplar.
 
 Example configuration:
 
 ```
-#define CONFIG_CHARGER_INPUT_CURRENT 512
+#define CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT 512
 
 #define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC 1
 #define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT 15000
@@ -319,42 +312,51 @@ Example configuration:
 #define CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW 27000
 ```
 
-1. EC ROM bootloader loads and jumps to the EC's read-only firmware image.
-1. RO firmware negotiates a 15W state via Current Source analog signaling and
-   begins charging the battery with it.
-1. RO firmware verifies conditions to begin booting the AP:
-     - Battery state of charge is greater than 1% AND charger power is greater
-       than 15W  (met after a minute or so of charging on analog signaling)
-     - OR Battery state of charge is greater than 3%
-     - OR Charger power is greater than 27W (met after PD negotiation in
-       unlocked RO firmware).
-1. AP firmware performs verification of the EC's RW image, upgrades it if
-   necessary, and sysjumps the EC to it.
-1. AP firmware polls the charge state limit power flag via EC-host command for
-   up to 3 seconds, in 50ms intervals.  The EC will return `1` (power limited)
-   so long as the charger power is < 27W and the battery is less than 3%.
-     1. Meanwhile, the EC performs PD negotiation.  Charger power lowers to 2.5W
+1.  EC ROM bootloader loads and jumps to the EC's read-only firmware image.
+1.  RO firmware negotiates a 15W state via Current Source analog signaling and
+    begins charging the battery with it.
+1.  RO firmware verifies conditions to begin booting the AP:
+    -   Battery state of charge is greater than 1% AND charger power is greater
+        than 15W (met after a minute or so of charging on analog signaling)
+    -   OR Battery state of charge is greater than 3%
+    -   OR Charger power is greater than 27W (met after PD negotiation in
+        unlocked RO firmware).
+1.  AP firmware performs verification of the EC's RW image, upgrades it if
+    necessary, and sysjumps the EC to it.
+1.  AP firmware polls the charge state limit power flag via EC-host command for
+    up to 3 seconds, in 50ms intervals. The EC will return `1` (power limited)
+    so long as the charger power is < 27W and the battery is less than 3%.
+    1.  Meanwhile, the EC performs PD negotiation. Charger power lowers to 2.5W
         for up to 500ms as the source transitions from vSafe5V to its highest
         supported voltage (15V or 20V are typical).
-     1. After negotiation is complete, the EC raises the charger current limit
+    1.  After negotiation is complete, the EC raises the charger current limit
         to the negotiated limit (45W is typical).
-     1. The EC returns 0 (unlimited) on the next `LIMIT_POWER` request.
-1. Depthcharge continues to boot Linux.
-
+    1.  The EC returns 0 (unlimited) on the next `LIMIT_POWER` request.
+1.  Depthcharge continues to boot Linux.
 
 ## Configuration Option Details
 
-### `CONFIG_CHARGER_INPUT_CURRENT`
+### `CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT`
 
 Required.
 
-The lowest current limit programmed into the charger.  This determines both the
-default level used on startup, and the value used during the voltage transients
-in PD negotiation.
+The default charger current limit used on startup and for inactive ports. It
+should not be higher than 512 mA unless the device ships with a discrete power
+supply. Raising this term above 512 mA is contrary to USB-PD. It may be lowered
+in order to improve compatibility with marginal BC1.2 chargers.
 
-It should not be higher than 512 mA unless the device ships with a discrete
-power supply.  Raising this term above 512 mA is contrary to USB-PD.  It may be
-lowered in order to improve compatibility with marginal BC1.2 chargers.
+### `CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT`
+
+Optional.
+
+If set, charger input current limits will never be set lower than this value.
+Historically most boards used the same value
+as `CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT`, but doing so violates USB-PD standby
+power requirements when voltages greater than 5V are used with the default 512
+mA value. Configuring this option to a nonzero value may be useful if a board
+needs extra headroom (possibly at the cost of drawing excess standby power), but
+boards should prefer to override `board_set_charge_limit()` instead to limit
+situations with excess power draw to only occur when that extra power is needed.
 
 ### `CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON`
 
@@ -372,7 +374,7 @@ than `CHARGER_MIN_BAT_PCT_FOR_POWER_ON`, in milliwatts.
 
 ### `CONFIG_BATTERY_MEASURE_IMBALANCE`
 
-Optional.  Only set this option if one or more batteries shipped with this board
+Optional. Only set this option if one or more batteries shipped with this board
 support per-cell battery voltage measurement.
 
 When enabled, the EC will query the attached battery for its per-cell voltages.
@@ -381,15 +383,15 @@ is inhibited.
 
 #### `CONFIG_CHARGER_MIN_BAT_PCT_IMBALANCED_POWER_ON`
 
-Default: 5%.  Above this battery state of charge, cell voltage balance is
+Default: 5%. Above this battery state of charge, cell voltage balance is
 ignored.
 
 #### `CONFIG_BATTERY_MAX_IMBALANCE_MV`
 
-Default: 200 mV.  If the difference between the highest and lowest cell exceeds
+Default: 200 mV. If the difference between the highest and lowest cell exceeds
 this value, then the pack is considered to be imbalanced.
 
-Note that lithium chemistry cells will almost always read similar voltages.  It
+Note that lithium chemistry cells will almost always read similar voltages. It
 is only near the top and bottom of charge that the slope of dV/dQ increases
 enough for small cell imbalances to be visible as a voltage difference.
 
@@ -426,3 +428,12 @@ Similar to `CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON`, this is the minimum
 charger power needed to boot even when the battery is less than
 `CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC`
 
+### `CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT`
+
+Optional, default 5%.
+
+This option reduces the charger's programmed current limit below the detected
+current limit for a given charger in an attempt to ensure that load transients
+won't overcurrent the source. Devices that require a lot of power to boot may
+need to either decrease the derating factor (if behavior remains acceptable when
+decreased) or increase `MIN_POWER_MW` settings to compensate.
\ No newline at end of file
diff --git a/docs/new_board_checklist.md b/docs/new_board_checklist.md
index 22e8d25988..7fe89d4121 100644
--- a/docs/new_board_checklist.md
+++ b/docs/new_board_checklist.md
@@ -6,38 +6,47 @@
 
 This document describes the high-level steps needed to create a new EC board. If
 you're creating a new board based on existing baseboard, you can jump straight
-to the relevant link found under [Configuring EC
-Features](#Configure-EC-Features) and focus on known board changes.
+to the relevant link found under
+[Configuring EC Features](#Configure-EC-Features) and focus on known board
+changes.
 
 ## Conventions
+
 ### Key Files
+
 Before you get started, it's important to understand the role of a few key files
 in the EC codebase.
 
-- [`include/config.h`](../include/config.h) {#config_h} - Contains the list of
-  top-level configuration options for the Chrome EC codebase. Each configuration
-  option is documented inline and is considered the authoritative definition.
-
-- `baseboard/<name>/` - This directory contains header files and source files
-  shared by all boards in a baseboard family.
-    - `baseboard.h` - Contains the EC configuration options shared by all
-      devices in the baseboard family.
-    - `baseboard.c` - Contains code shared by all devices in the baseboard
-      family.
-    - `build.mk` - The board family makefile specifies C source files compiled
-      into all boards in the baseboard family.
-
-- `board/<board>` - Files in this directory are only built for a single board.
-    - `board.h` - EC configuration options specific to a single board.
-    - `board.c` - Code built only on this board.
-    - `build.mk` {#board_build_mk} - The board makefile defines the EC chipset family, defines the
-      baseboard name, and specifies the C source files that are compiled.
-    - `gpio.inc` - This C header file defines the interrupts, GPIOs, and
-      alternate function selection for all pins on the EC chipset.
-    - `ec.tasklist` - This C header defines the lists of tasks that are enabled
-      on the board.  See the main EC documentation more details on [EC tasks].
+-   [`include/config.h`](../include/config.h) {#config_h} - Contains the list of
+    top-level configuration options for the Chrome EC codebase. Each
+    configuration option is documented inline and is considered the
+    authoritative definition.
+
+-   `baseboard/<name>/` - This directory contains header files and source files
+    shared by all boards in a baseboard family.
+
+    -   `baseboard.h` - Contains the EC configuration options shared by all
+        devices in the baseboard family.
+    -   `baseboard.c` - Contains code shared by all devices in the baseboard
+        family.
+    -   `build.mk` - The board family makefile specifies C source files compiled
+        into all boards in the baseboard family.
+
+-   `board/<board>` - Files in this directory are only built for a single board.
+
+    -   `board.h` - EC configuration options specific to a single board.
+    -   `board.c` - Code built only on this board.
+    -   `build.mk` {#board_build_mk} - The board makefile defines the EC chipset
+        family, defines the baseboard name, and specifies the C source files
+        that are compiled.
+    -   `gpio.inc` - This C header file defines the interrupts, GPIOs, and
+        alternate function selection for all pins on the EC chipset.
+    -   `ec.tasklist` - This C header defines the lists of tasks that are
+        enabled on the board. See the main EC documentation more details on
+        [EC tasks].
 
 ### GPIO Naming
+
 Many drivers and libraries in the common EC code rely on board variants defining
 an exact GPIO signal name. Examples include the `GPIO_LID_OPEN`,
 `GPIO_ENTERING_RW`, and `GPIO_SYS_RESET_L` signals. The net names in schematics
@@ -46,7 +55,7 @@ all the `GPIO_INT()`, `GPIO()`, `ALTERNATE()`, and `UNIMPLEMENTED()` definitions
 in `gpio.inc` use the schematic net name. You then create `#define` macros in
 `board.h` to map the net names to the EC common names.
 
-Below is an example configuration for the SYS_RESET_L signal.  The schematic net
+Below is an example configuration for the SYS_RESET_L signal. The schematic net
 name of this signal is EC_RST_ODL and the signal connects to the EC chipset pin
 GPIO02.
 
@@ -63,6 +72,7 @@ Please see the [GPIO](./configuration/gpio.md) documentation for additional
 details on the GPIO macros.
 
 ## How to use this document
+
 Each of the following sections details a single feature set that may need to be
 modified or configured for your new board. The feature sets are organized so
 they can be implemented with a reasonably sized change list, and can be worked
@@ -70,34 +80,31 @@ on independently.
 
 Each configuration feature document includes the following sub-tasks:
 
-- **Config Options** - This section details the `CONFIG_*` options relevant to
-  the feature. Use the documentation found in [config.h] to determine whether
-  each option should be enabled (using #define) or disabled (using #undef) in
-  the relevant `baseboard.h` or `board.h` file.
-- **Feature Parameters** - This section details parameters that control the
-  operation of the feature. Similar to the config options, feature parameters
-  are defined in [config.h] and prefixed with `CONFIG_*`.  However, feature
-  parameters are assigned a default value, which can be overridden in by
-  `baseboard.h` or `board.h` using an `#undef/#define` pair.
-  ```c
-  #undef CONFIG_UART_TX_BUF_SIZE
-  #define CONFIG_UART_TX_BUF_SIZE 4096
-  ```
-- **GPIOs and Alternate Pins** - This section details signals and pins relevant
-  to the feature. Add the required `GPIO_INT()`, `GPIO()`, `ALTERNATE()`, and
-  `UNIMPLEMENTED()` definitions to `gpio.inc`, making sure to follow the [GPIO
-  naming conventions].
-- **Data Structures** - This section details the data structures required to
-  configure the feature for correct operation. Add the data structures to
-  `baseboard.c` or `board.c`. Note that most data structures required by the
-  common EC code should be declared `const` to save on RAM usage.
-- **Tasks** - This section details the tasks that the EC feature requires for
-  operation.
-- **Testing and Debugging** - This section details strategies for testing the EC
-  feature set and for debugging issues. This section also documents EC console
-  commands related to the feature set.
-- **Example** - When present, this section walks through a complete example for
-  configuring an EC feature based on an existing board implementation.
+-   **Config Options** - This section details the `CONFIG_*` options relevant to
+    the feature. Use the documentation found in [config.h] to determine whether
+    each option should be enabled (using #define) or disabled (using #undef) in
+    the relevant `baseboard.h` or `board.h` file.
+-   **Feature Parameters** - This section details parameters that control the
+    operation of the feature. Similar to the config options, feature parameters
+    are defined in [config.h] and prefixed with `CONFIG_*`. However, feature
+    parameters are assigned a default value, which can be overridden in by
+    `baseboard.h` or `board.h` using an `#undef/#define` pair. `c #undef
+    CONFIG_UART_TX_BUF_SIZE #define CONFIG_UART_TX_BUF_SIZE 4096`
+-   **GPIOs and Alternate Pins** - This section details signals and pins
+    relevant to the feature. Add the required `GPIO_INT()`, `GPIO()`,
+    `ALTERNATE()`, and `UNIMPLEMENTED()` definitions to `gpio.inc`, making sure
+    to follow the [GPIO naming conventions].
+-   **Data Structures** - This section details the data structures required to
+    configure the feature for correct operation. Add the data structures to
+    `baseboard.c` or `board.c`. Note that most data structures required by the
+    common EC code should be declared `const` to save on RAM usage.
+-   **Tasks** - This section details the tasks that the EC feature requires for
+    operation.
+-   **Testing and Debugging** - This section details strategies for testing the
+    EC feature set and for debugging issues. This section also documents EC
+    console commands related to the feature set.
+-   **Example** - When present, this section walks through a complete example
+    for configuring an EC feature based on an existing board implementation.
 
 ## Create the new EC board
 
@@ -113,8 +120,8 @@ are found in the corresponding [README.md] documentation.
 
 The [new_variant.py] script also verifies the new EC board compiles and prepares
 a changelist to upload to Gerrit. You should upload this changelist unmodified
-for review and submission (you may need to run `make buildall -k` to satisfy
-the EC pre-submit tests).
+for review and submission (you may need to run `make buildall -k` to satisfy the
+EC pre-submit tests).
 
 The next step is to review the following sections to make any needed
 modifications to your new board files, test the changes, and upload the changes
@@ -128,8 +135,8 @@ populate these directories with the minimum set of files required compile the EC
 board. The initial changelists for the Hatch and Volteer reference boards
 provide good examples for how to start.
 
-  * [Volteer EC skeleton build]
-  * [Hatch EC skeleton build]
+*   [Volteer EC skeleton build]
+*   [Hatch EC skeleton build]
 
 After submitting the skeleton builds, review the following sections and add each
 feature set as required by your design.
@@ -143,30 +150,30 @@ priority and should be ready before the first prototypes arrive. Use the
 documentation link for details about the code changes required to implement each
 feature.
 
-| EC Feature | Needed for Power On |
-| :--------- | ------------------: |
-| [Configure EC Chipset](./configuration/ec_chipset.md) | yes |
-| [Configure AP to EC Communication](./configuration/config_ap_to_ec_comm.md) | yes |
-| [Configure AP Power Sequencing](./configuration/ap_power_sequencing.md) | yes |
-| [Configure USB-C](./usb-c.md) | yes |
-| [Configure Charger (TODO)](./configuration/template.md) | yes |
-| [Configure I2C Buses](./configuration/i2c.md) | no |
-| [Configure CrOS Board Information (CBI)](./configuration/cbi.md) | no |
-| [Configure Keyboard](./configuration/keyboard.md) | no |
-| [Configure LEDs](./configuration/leds.md) | no |
-| [Configure Motion Sensors (TODO)](./configuration/motion_sensors.md) | no |
-| [Configure BC1.2 Charger Detector (TODO)](./configuration/template.md) | no |
-| [Configure Battery (TODO)](./configuration/template.md) | no |
+EC Feature                                                                  | Needed for Power On
+:-------------------------------------------------------------------------- | ------------------:
+[Configure EC Chipset](./configuration/ec_chipset.md)                       | yes
+[Configure AP to EC Communication](./configuration/config_ap_to_ec_comm.md) | yes
+[Configure AP Power Sequencing](./configuration/ap_power_sequencing.md)     | yes
+[Configure USB-C](./usb-c.md)                                               | yes
+[Configure Charger (TODO)](./configuration/template.md)                     | yes
+[Configure I2C Buses](./configuration/i2c.md)                               | no
+[Configure CrOS Board Information (CBI)](./configuration/cbi.md)            | no
+[Configure Keyboard](./configuration/keyboard.md)                           | no
+[Configure LEDs](./configuration/leds.md)                                   | no
+[Configure Motion Sensors (TODO)](./configuration/motion_sensors.md)        | no
+[Configure BC1.2 Charger Detector (TODO)](./configuration/template.md)      | no
+[Configure Battery (TODO)](./configuration/template.md)                     | no
 
 After finishing the changes required for all EC features, it is recommended that
 you make one final pass over all the GPIOs and pin assignments used on your
 board. Refer to the [GPIO](./configuration/gpio.md) documentation for details.
 
-[README.md]:https://chromium.googlesource.com/chromiumos/platform/dev-util/+/master/contrib/variant/README.md
-[new_variant.py]:https://chromium.googlesource.com/chromiumos/platform/dev-util/+/master/contrib/variant/new_variant.py
-[create_initial_ec_image.sh]:https://chromium.googlesource.com/chromiumos/platform/dev-util/+/master/contrib/variant/create_initial_ec_image.sh
+[README.md]:https://chromium.googlesource.com/chromiumos/platform/dev-util/+/HEAD/contrib/variant/README.md
+[new_variant.py]:https://chromium.googlesource.com/chromiumos/platform/dev-util/+/HEAD/contrib/variant/new_variant.py
+[create_initial_ec_image.sh]:https://chromium.googlesource.com/chromiumos/platform/dev-util/+/HEAD/contrib/variant/create_initial_ec_image.sh
 [Volteer EC skeleton build]:https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1758532
 [Hatch EC skeleton build]:https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1377569/
 [config.h]: ./new_board_checklist.md#config_h
 [EC tasks]: ../README.md#Tasks
-[GPIO naming conventions]: ./new_board_checklist.md#GPIO-Naming
\ No newline at end of file
+[GPIO naming conventions]: ./new_board_checklist.md#GPIO-Naming
diff --git a/docs/pupr.md b/docs/pupr.md
new file mode 100644
index 0000000000..cf97f4e381
--- /dev/null
+++ b/docs/pupr.md
@@ -0,0 +1,24 @@
+# Parallel Uprevs for platform/ec
+
+## Overview
+
+Since the platform/ec repo doesn't use the normal ebuild based CQ some of the
+ebuild files don't use the normal automatic uprev. Instead the go/pupr tool
+creates new CLs to uprev the chromeos-base/ec-utils and send them through the
+slow CQ running all the ebuilds that depend on it.
+
+## Reviewer responsibilities
+
+For the most part you can ignore these CLs. You don't need to add CR+2 nor CQ+2.
+However if you see that the CL has failed the CQ several times, you should
+check and see if there is a real bug that is preventing the CL from submitting.
+
+If there is a pupr cl that is known bad, i.e. there is a breakage in the code
+and pupr needs to pick a different cl, then please Abandon that cl, don't
+CR-2 it.  Pupr will keep adding CQ+2 to the cl over and over again until it
+submits, even if it never will.
+
+## Failure implications
+
+If the CL fails to merge, then the ectool binary will not be built with the
+latest code.
diff --git a/docs/reducing_ec_image_size.md b/docs/reducing_ec_image_size.md
new file mode 100644
index 0000000000..96c1a9eac9
--- /dev/null
+++ b/docs/reducing_ec_image_size.md
@@ -0,0 +1,467 @@
+# Reducing the EC image size
+
+The EC ToT codebase continues grows as new features are added and for bug fixes.
+This puts pressure on older boards that have limited flash space remaining. This
+document provides some tips for reducing the EC image size.
+
+[TOC]
+
+## Checking the EC image footprint
+
+The EC codebase supports two build types:
+
+1.  `cros-ec` builds are the legacy EC images built using Make (e.g. `make
+    BOARD=volteer`)
+1.  `zephyr-ec` builds are the EC images built using the Zephyr RTOS kernel
+    using zmake/Cmake (e.g. `zmake build herobrine`)
+
+### Checking a single cros-ec build
+
+Building a single cros-ec board using `make BOARD=<board> -j` reports the the
+number of bytes free in flash and RAM for both the RO and RW images. An example
+from building the juniper board is shown below.
+
+```
+$ make BOARD=juniper -j
+    ...
+  *** 668 bytes in flash and 10308 bytes in RAM still available on juniper RO ****
+  *** 3224 bytes in flash and 7460 bytes in RAM still available on juniper RW ****
+```
+
+### Checking all cros-ec builds
+
+Running `make buildall -j` shows a summary of the three boards with the smallest
+RO flash footprint, FW flash footprint, and RW RAM footprint.
+
+```
+$ make buildall -j
+    ...
+buildall completed successfully!
+Smallest free spaces in RO flash (bytes):
+servo_v4  :    104
+scarlet   :    108
+mushu     :    160
+Smallest free spaces in RW flash (bytes):
+mushu     :     96
+bobba     :    232
+trondo    :    376
+Tightest boards' RW RAM images, bytes free:
+whiskers  :    244
+minimuffin:    284
+zinger    :    284
+```
+
+### Comparing cros-ec image sizes
+
+The cros-ec makefile provides two make targets for helping track the impact of
+code changes.
+
+`make savesizes` saves the EC footprint information for all boards, providing
+the baseline for comparison. `make newsizes` compares the sizes of the current
+build against the EC footprint information saved by most recent invocation of
+`make savesizes`.
+
+General workflow:
+
+1.  Checkout branch you need to compare against. For example `repo start
+    check-ec-size -r cros/main` or `repo start check-ec-size -r <hash>`.
+1.  Run `make buildall -j`.
+1.  Run `make savesizes`.
+1.  Apply your code change (e.g. change the local branch, cherry-pick your
+    changes, or directly edit source files).
+1.  Run `make buildall -j` again.
+1.  Run `make newsizes` to generate report of size changes.
+
+Example report from `make newsizes` shown below:
+
+```
+$ make newsizes
+build/burnet/RO/space_free_flash grew by 576 bytes: (488 to 1064)
+build/burnet/RW/space_free_flash grew by 552 bytes: (1324 to 1876)
+build/cerise/RO/space_free_flash grew by 512 bytes: (276 to 788)
+build/cerise/RW/space_free_flash grew by 548 bytes: (7076 to 7624)
+    ...
+```
+
+### Checking a single zephyr-ec build
+
+By default, `zmake` will display the flash and SRAM usage of the board.
+
+```
+$ zmake build herobrine
+    ...
+Building herobrine:ro: /usr/bin/ninja -C /mnt/host/source/src/platform/ec/build/zephyr/herobrine/build-ro
+-- git describe warned: warning: tag 'upstream/v2.7.99' is externally known as 'v2.7.99'
+-- Zephyr version: 3.0.99 (/mnt/host/source/src/third_party/zephyr/main), build: v2.7.99-5035-ga17c05c7228e
+Memory region         Used Size  Region Size  %age Used
+           FLASH:      219920 B       256 KB     83.89%
+            SRAM:       49688 B        64 KB     75.82%
+        IDT_LIST:          0 GB         2 KB      0.00%
+Building herobrine:rw: /usr/bin/ninja -C /mnt/host/source/src/platform/ec/build/zephyr/herobrine/build-rw
+-- git describe warned: warning: tag 'upstream/v2.7.99' is externally known as 'v2.7.99'
+-- Zephyr version: 3.0.99 (/mnt/host/source/src/third_party/zephyr/main), build: v2.7.99-5035-ga17c05c7228e
+Memory region         Used Size  Region Size  %age Used
+           FLASH:      219920 B       256 KB     83.89%
+            SRAM:       49688 B        64 KB     75.82%
+        IDT_LIST:          0 GB         2 KB      0.00%
+```
+
+Note, that the flash region size listed above represents the total flash
+available on the EC. The actual available region size is only half the reported
+value in order to store two images (RO+RW).
+
+#### Other Zephyr utilities
+
+The Cmake system utilized by Zephyr provides two build targets `rom_report` and
+`ram_report` which generate a list of all the compiled objects in tabular form.
+This can be useful for identifying particular modules that contribute to the
+image size.
+
+The `rom_report` and `ram_report` targets are currently only supported when
+working outside the chroot. Follow the [instructions][1] for building zephyr-ec
+images outside chroot before running the commands below.
+
+```
+# Configure the Herobrine zephyr project, storing the build files in /tmp/zephyr-herobrine
+$ zmake configure -B /tmp/zephyr-herobrine herobrine
+
+# Build the RO image
+$ ninja -C /tmp/zephyr-herobrine/herobrine/build-ro
+
+# Generate the ROM report, report sent to stdout
+$ ninja -C /tmp/zephyr-herobrine/herobrine/build-ro rom_report
+```
+
+Please refer to the [Zephyr Optimization Tools][3] documentation for details on
+the `rom_report` and `ram_report` targets.
+
+## Checking a board's config
+
+If you want to see what configs are enabled for a given board, use the
+`print-configs` `Makefile` target:
+
+```shell
+$ make BOARD=<BOARD> print-configs
+```
+
+You can also open the `./build/<BOARD>/.config` file that is generated after
+building the board with `make BOARD=<BOARD>`.
+
+## Disable console commands
+
+The lowest hanging fruit for reducing the EC image size is by disabling console
+commands that provide debug information only and don't impact the user or the
+automated testing. Any console command that is not used by the FAFT tests and
+suites is safe to disable in the EC images.
+
+For cros-ec builds, add `#undef CONFIG_CMD_<name>` to the board.h or baseboard.h
+file to disable the console command.
+
+For zephyr-ec builds, add `CONFIG_PLATFORM_EC_CONSOLE_CMD_<name>=n` to the board
+prj.conf file to disable the console command.
+
+*   TODO: Create new CONFIG/Kconfig option that disables all console commands
+    not required by FAFT.
+
+<!-- mdformat off(Don't format table) -->
+
+| Used by FAFT | config.h option | Console commands | Notes |
+|:---|:---|:---|:---|
+|  | CONFIG_CMD_ACCELS | `accelrange`<br>`accelres`<br>`accelrate`<br>`accelread`<br>`accelinit`<br>`accelinfo` | |
+|  | CONFIG_CMD_ACCELSPOOF | `accelspoof` | |
+| | CONFIG_CMD_ACCEL_FIFO | `fiforead` | |
+| | CONFIG_CMD_ACCEL_INFO | `accelinfo` | |
+| | CONFIG_CMD_ADC | `adc` | Note firmware_ECAdc uses the `temps` command. |
+| | CONFIG_CMD_ALS | `als` | |
+| | CONFIG_CMD_APTHROTTLE | `apthrottle` | |
+| | CONFIG_CMD_AP_RESET_LOG |??? | |
+| | CONFIG_CMD_BATDEBUG | `fgunseal`<br>`fgseal`<br>`fginit`<br>`fgprobe`<br>`fgrd`<br>`fgcmd`<br>`fcmdrd` | |
+| | CONFIG_CMD_BATTFAKE | `battfake` | |
+| | CONFIG_CMD_BATT_MFG_ACCESS | `battmfgacc` | |
+| | CONFIG_CMD_CBI | `cbi` | firmwareECCbiEeprom uses `ectool` on AP to test CBI |
+| x | CONFIG_CMD_CHARGEN | `chargen` | Used by firmware_Cr50CCDUartStress, included in faft_ccd, faft_cr50_prepvt, and faft_cr50_pvt suites |
+| | CONFIG_CMD_CHARGER | `bd9995x`<br>`sy21612` | |
+| | CONFIG_CMD_CHARGER_ADC_AMON_BMON | `amonbmon` | |
+| | CONFIG_CMD_CHARGER_DUMP | `charger_dump` | |
+| | CONFIG_CMD_CHARGER_PROFILE_OVERRIDE | `fastcharge` | |
+| | CONFIG_CMD_CHARGER_PROFILE_OVERRIDE_TEST | `fastchgtest` | |
+| | CONFIG_CMD_CHARGE_SUPPLIER_INFO | `chgsup` | |
+| | CONFIG_CMD_CHGRAMP | `chgramp` | |
+| | CONFIG_CMD_CLOCKGATES | `clockgates` | |
+| | CONFIG_CMD_COMXTEST | `comxtest` | |
+| x | CONFIG_CMD_CRASH | `crash` | Used by TAST `crash.ECCrash`, FAFT `firmware_ECSharedMem` |
+| | CONFIG_CMD_DEVICE_EVENT | `deviceevent` | |
+| | CONFIG_CMD_DLOG | `dlog` | |
+| | CONFIG_CMD_ECTEMP | `ectemp` | |
+| | CONFIG_CMD_FASTCHARGE | `fastcharge` | Obsolete? use CONFIG_CMD_CHARGER_PROFILE_OVERRIDE? |
+| | CONFIG_CMD_FLASH | `flasherase`<br>`flashwrite`<br>`flashread` | |
+| x | CONFIG_CMD_FLASHINFO | `flashinfo` | Used by TAST `firmware.ECSize` |
+| | CONFIG_CMD_FLASH_TRISTATE | `fpcapture`<br>`flash_tristate` | |
+| | CONFIG_CMD_FLASH_WP | `flashwp` | |
+| | CONFIG_CMD_FORCETIME | `forcetime` | |
+| | CONFIG_CMD_FPSENSOR_DEBUG | `fpcapture`<br>`fpenroll`<br>`fpmatch`<br>`fpclear`<br>`fpmaintenance` | |
+| | CONFIG_CMD_GETTIME | `gettime` | Used by Cr50 tests, not by FAFT EC |
+| | CONFIG_CMD_GL3590 | `gl3590` | |
+| | CONFIG_CMD_GPIO_EXTENDED | Adds options to `gpioget` and `gpioset`. | Should be renamed to CONFIG_GPOI_EXTENDED |
+| | CONFIG_CMD_GPIO_POWER_DOWN | Not a valid config. | Should be CONFIG_GPIO_POWER_DOWN |
+| | CONFIG_CMD_GT7288 | `gt7288_desc`<br>`gt7288_repdesc`<br>`gt7288_ver`<br>`gt7288_report` | |
+| | CONFIG_CMD_HASH | `hash` | firmware_ECHash uses `ectool echash` |
+| x | CONFIG_CMD_HCDEBUG | `hcdebug` | firmware_ECBootTime.py |
+| x | CONFIG_CMD_HOSTCMD | `hostcmd` | |
+| | CONFIG_CMD_I2CWEDGE | `i2cwedge`<br>`i2cunwedge` | |
+| | CONFIG_CMD_I2C_PROTECT | `i2cprotect` | |
+| | CONFIG_CMD_I2C_SCAN | `i2cscan` | |
+| | CONFIG_CMD_I2C_STRESS_TEST | `i2ctest` | |
+| | CONFIG_CMD_I2C_STRESS_TEST_ACCEL | Not a console command | |
+| | CONFIG_CMD_I2C_STRESS_TEST_ALS | Not a console command | |
+| | CONFIG_CMD_I2C_STRESS_TEST_BATTERY | Not a console command | |
+| | CONFIG_CMD_I2C_STRESS_TEST_CHARGER | Not a console command | |
+| | CONFIG_CMD_I2C_STRESS_TEST_TCPC | `Not a console command | |
+| | CONFIG_CMD_I2C_XFER | `i2cxfer` | firmware_ECCbiEeprom uses `ectool i2cxfer` which is not guarded by CONFIG_CMD_I2C_XFER |
+| | CONFIG_CMD_I2C_XFER_RAW |  | Adds options to `i2cxfer` |
+| | CONFIG_CMD_IDLE_STATS | `idlestats` | |
+| | CONFIG_CMD_INA | `ina` | |
+| | CONFIG_CMD_JUMPTAGS | `jumptags` | |
+| x | CONFIG_CMD_KEYBOARD | `8042`<br>`ksstate`<br>`kbpress` | Used by `firmware_ECKeyboard` |
+| | CONFIG_CMD_LEDTEST | `ledtest` | |
+| | CONFIG_CMD_MCDP | `mcdp` | |
+| | CONFIG_CMD_MD | `md` | |
+| | CONFIG_CMD_MEM | | Not a console command - gates `md` and `rw` |
+| | CONFIG_CMD_MFALLOW | `mfallow` | |
+| | CONFIG_CMD_MMAPINFO | `mmapinfo` | |
+| x | CONFIG_CMD_PD | `pd` | Used by FAFT PD, TAST `firmware.ECSystemLocked` |
+| | CONFIG_CMD_PD_DEV_DUMP_INFO | | Not supported by TCPMv2 |
+| | CONFIG_CMD_PD_FLASH | `pd flash` | Not supported by TCPMv2 |
+| | CONFIG_CMD_PD_SRCCAPS_REDUCED_SIZE | `pd <port> srccaps` | Defining this reduces the verbosity of this command, saving bytes |
+| | CONFIG_CMD_PECI | `peci` | firmware_ECThermal uses `ectool tempsinfo` |
+| | CONFIG_CMD_PLL | `pll` | only used by lm4 chip |
+| | CONFIG_CMD_POWERINDEBUG | `powerindebug` | |
+| | CONFIG_CMD_POWERLED | `powerled` | |
+| x | CONFIG_CMD_POWER_AP | `apreset`<br>`apshutdown` | Used by power_Monitoring.py |
+| | CONFIG_CMD_PPC_DUMP | `ppc_dump` | |
+| | CONFIG_CMD_PS2 | `ps2ench`<br>`ps2write` | Used only on NPCX |
+| | CONFIG_CMD_PWR_AVG | `pwr_avg` | |
+| | CONFIG_CMD_RAND | `rand` | Used only on STM32 |
+| | CONFIG_CMD_REGULATOR | `ir357x` | |
+| | CONFIG_CMD_RESET_FLAGS | `rflags` | |
+| | CONFIG_CMD_RETIMER | `retimer` | |
+| | CONFIG_CMD_RTC | `rtc` | |
+| | CONFIG_CMD_RTC_ALARM | `rtc_alarm` | |
+| | CONFIG_CMD_RW | `rw` | |
+| | CONFIG_CMD_SCRATCHPAD | `scratchpad` | |
+| | CONFIG_CMD_SEVEN_SEG_DISPLAY | `seg` | |
+| | CONFIG_CMD_SHA256_TEST | `???` | |
+| x | CONFIG_CMD_SHMEM | `shmem` | Used by firmware_ECSharedMem |
+| | CONFIG_CMD_SLEEP | `sleep` | used only lm4 |
+| | CONFIG_CMD_SLEEPMASK | `sleepmask` | Only used for Cr50 tests |
+| | CONFIG_CMD_SLEEPMASK_SET | | Adds options to `sleepmask` |
+| | CONFIG_CMD_SPI_FLASH | `spi_flasherase`<br>`spi_flashwrite`<br>`spi_flashread`<br>`spi_flash_rsr`<br>`spi_flash_wsr`<br>`spi_flash_wsr` | |
+| | CONFIG_CMD_SPI_NOR | `spinorinfo`<br>`spinorerase`<br>`spinorwrite`<br>`spinorread` | |
+| | CONFIG_CMD_SPI_XFER | `spixfer` | |
+| x | CONFIG_CMD_SYSINFO | `sysinfo` | Used by firmware_ECSystemLocked |
+| x | CONFIG_CMD_SYSJUMP | `sysjump` | Used by firmware_ECSharedMem |
+| | CONFIG_CMD_SYSLOCK | `syslock` | |
+| | CONFIG_CMD_TASKREADY | `taskready` | |
+| | CONFIG_CMD_TASK_RESET | `taskreset` | |
+| | CONFIG_CMD_TCPC_DUMP | `tcpci_dump` | |
+| x | CONFIG_CMD_TEMP_SENSOR | `temps` | |
+| | CONFIG_CMD_TIMERINFO | `timerinfo` | |
+| | CONFIG_CMD_TYPEC | `typec` | |
+| | CONFIG_CMD_USART_INFO | `usart_info` | |
+| | CONFIG_CMD_USB_PD_CABLE | `pdcable` | |
+| x | CONFIG_CMD_USB_PD_PE | `pe` | Doesn't appear to be used but might be by FAFT PD |
+| x | CONFIG_CMD_WAITMS | `waitms` | firmware_ECWatchdog | |
+
+<!-- mdformat on -->
+
+## Reduce or eliminate USB-C debugging
+
+The TCPM (Type-C Port manager) implementation is one of the more complex modules
+implemented by the EC code. This module includes extensive debugging and is
+enabled by default due to the value provided during both board bringup and on
+production systems.
+
+The TCPM provides the following debug levels:
+
+*   `DEBUG_DISABLE` (0) - Debugging disabled, no runtime messages displayed
+*   `DEBUG_LEVEL_1` (1) - Displays all the state transitions for the TC (Type-C)
+    and PE (Policy Engine) state machines
+*   `DEBUG_LEVEL_2` (2) - Displays the raw contents of received PD (Power
+    Delivery) packets, excluding PING packets
+*   `DEBUG_LEVEL_3` (3) - Enables debug messages in the PRL Also displays
+    received PING packets.
+
+When `CONFIG_USB_PD_DEBUG_LEVEL` is undefined, the EC allows runtime
+configuration of the USB-C debug level using the `pd dump <level>` EC console
+command. In this configuration, the strings from all debug levels are included
+in the image.
+
+Enabling a fixed debug level removes runtime control of the debug level and also
+removes the strings for the higher debug levels.
+
+For cros-ec builds, add the following to your board.h/baseboard.h file:
+
+```c
+    #define CONFIG_USB_PD_DEBUG_LEVEL <level>
+```
+
+For zephyr-ec builds, add the following to your prj.conf file:
+
+```
+    CONFIG_PLATFORM_EC_USB_PD_DEBUG_FIXED_LEVEL=y
+    CONFIG_PLATFORM_EC_USB_PD_DEBUG_LEVEL=<level>
+```
+
+Approximate flash space savings from each fixed level setting:
+
+Fixed Debug Level | Relative Saving | Cumulative Saving
+----------------- | --------------- | -----------------
+Disabled          | 0               | 0
+3                 | 100 bytes       | 100 bytes
+2                 | 500-600 bytes   | 600-700 bytes
+1                 | 100 bytes       | 700-800 bytes
+0                 | 2000 bytes      | 2700-2800 bytes
+
+The recommended setting is setting the fixed debug level to `DEBUG_LEVEL_2` (2).
+This adds details about received PD packets in the EC log stored by the kernel
+and can help troubleshoot PD issues when a PD analyzer isn't available.
+
+It is not recommended to set the fixed debug level to `DEBUG_DISABLE` (0) on any
+shipping firmware.
+
+### TCPMv1 Configuration
+
+Many older platforms still use the legacy TCPMv1 (`CONFIG_USB_PD_TCPMV1`)
+implementation. Specific to TCPMv1, the PD protocol state names can be removed
+from the debug output by adding the following to the board.h/baseboard.h file.
+
+```c
+#undef CONFIG_USB_PD_TCPMV1_DEBUG
+```
+
+This saves around 900 bytes of flash space. TCPMv2 does not currently provide an
+equivalent configuration option, so there is also no Kconfig equivalent.
+
+## Other optional features
+
+### ASSERT() Calls
+
+By default, `ASSERT()` calls generate a console message of the following form:
+
+```
+    ASSERTION FAILURE '<expr>' in function() at file:line
+```
+
+There are two options available that reduce the size of strings stored with the
+`ASSERT()` calls.
+
+<!-- mdformat off(Don't format table) -->
+
+Description | cros-ec setting | zephyr-ec setting | Total Savings
+:--- | :--- | :--- | :---
+Display only file and line number | `#define CONFIG_DEBUG_ASSERT_BRIEF` | `CONFIG_PLATFORM_EC_DEBUG_ASSERT_BRIEF=y` | 2000-2500 bytes
+Disable all debug from ASSERT() calls.<br> EC is reset using a software breakpoint. | `#undef CONFIG_DEBUG_ASSERT_REBOOTS` | `CONFIG_PLATFORM_EC_DEBUG_ASSERT_REBOOTS=n`<br>`CONFIG_PLATFORM_EC_DEBUG_ASSERT_BREAKPOINT=y` | 3000-4000 bytes
+
+<!-- mdformat on -->
+
+It is not recommended to disable `CONFIG_PLATFORM_EC_DEBUG_ASSERT_REBOOTS` on
+shipping firmware.
+
+### Disable console help and history
+
+The help strings can be removed from the final build, saving about 5000 bytes of
+flash space. The history command can also be disabled to save another 200 bytes
+of flash space.
+
+For cros-ec builds, add `#undef CONFIG_CONSOLE_CMDHELP` and `#undef
+CONFIG_CONSOLE_HISTORY` to the board.h/baseboard.h file.
+
+zephyr-ec builds use Zephyr's shell subsystem and by default enable the
+`CONFIG_SHELL_MINIMAL` option. This option already disables shell help along
+with many other non-critical features. Refer to the shell subsystem [Kconfig][2]
+source file for the complete list of shell features than can be configured.
+
+### Link time optimizaiton
+
+Link time optimization (LTO) is a feature of the linker to identify and remove
+unused code.
+
+For cros-ec builds, LTO is enabled by adding this to the board.h/baseboard.h
+file.
+
+```c
+#define CONFIG_LTO
+```
+
+For zephyr-ec builds, LTO is enabled by default and is controlled with Kconfig.
+
+```
+CONFIG_LTO=y
+```
+
+Note that for zephyr-ec builds, LTO is only turned on for the source files found
+under `platform/ec`. The upstream Zephyr code does not currently support LTO due
+to some auto-generated code that breaks the assumptions made by the linker. This
+[Github issue][4] tracks the effort to support LTO in the Zephyr kernel.
+
+### CONFIG_CHIP_INIT_ROM_REGION
+
+The config option `CONFIG_CHIP_INIT_ROM_REGION` creates a new linker section to
+store data that remains resident in ROM/flash at runtime. This reduces the
+effective cros-ec image size by identifying data structures that do not need to
+be copied into the code RAM section at startup.
+
+This option has the following requirements:
+
+1.  EC executes code from RAM
+2.  The ROM/flash size is larger than 2 times the code RAM size.
+3.  The RO code released for the board includes this
+    [change](https://crrev.com/c/2428566).
+
+The only EC chip that matches these prerequisites is the Nuvoton NPCX7.
+
+Due to the RO code requirement, take care before enabling this option for boards
+released prior to 2021.
+
+If the above requirements are meant, add the following to the
+board.h/baseboard.h file:
+
+```c
+#define CONFIG_CHIP_INIT_ROM_REGION
+#define CONFIG_CHIP_DATA_IN_INIT_ROM
+```
+
+These options are not supported for zephyr-ec builds.
+
+### Enable short GPIO names
+
+The [GPIO macros](./configuration/gpio.md) defined by the board get stored as
+descriptive strings for use with the `gpioget` and `gpioset` console commands.
+
+The names of the GPIOs can be shorted by enabling the
+`CONFIG_COMMON_GPIO_SHORTNAMES` option.
+
+For example, the Kukui board defines this GPIO:
+
+```c
+GPIO(PMIC_FORCE_RESET_ODL, PIN(A, 2),  GPIO_ODR_HIGH)
+```
+
+Normally, the GPIO name is stored exactly as specified by the macro:
+`PMIC_FORCE_RESET_ODL`. However, when `CONFIG_COMMON_GPIO_SHORTNAMES` is
+defined, then the GPIO name is shortened to only include port and pin number:
+`A2`.
+
+This option is currently only supported by the STM32 chip and it is not
+supported by zephyr-ec builds.
+
+Note that there are some [FAFT tests][5] that rely on the GPIO name. If you
+enable this option, you may also need to change firmware testing configuration
+[file][6].
+
+[1]:./zephyr/zephyr_build.md#Working-outside-the-chroot
+[2]:https://github.com/zephyrproject-rtos/zephyr/blob/main/subsys/shell/Kconfig
+[3]:https://docs.zephyrproject.org/latest/guides/optimizations/tools.html
+[4]:https://github.com/zephyrproject-rtos/zephyr/issues/2112
+[5]:https://chromium.googlesource.com/chromiumos/third_party/autotest/+/069cb4b0/server/site_tests/firmware_ECUsbPorts/firmware_ECUsbPorts.py#81
+[6]:https://chromium.googlesource.com/chromiumos/platform/fw-testing-configs/+/e2e9547e/volteer.json#26
diff --git a/docs/schematics/dragonclaw/README.md b/docs/schematics/dragonclaw/README.md
index 66fde41df8..82a2fa2681 100644
--- a/docs/schematics/dragonclaw/README.md
+++ b/docs/schematics/dragonclaw/README.md
@@ -6,5 +6,5 @@ Note that you'll need to download and save the HTML file from
 
 The layout file is in the [`.brd`] file.
 
-[`.brd`]: https://raw.githubusercontent.com/coreboot/chrome-ec/master/docs/schematics/dragonclaw/dragonclaw_v0.2.brd
-[schematic]: https://raw.githubusercontent.com/coreboot/chrome-ec/master/docs/schematics/dragonclaw/dragonclaw_v0.2.html
+[`.brd`]: https://raw.githubusercontent.com/coreboot/chrome-ec/HEAD/docs/schematics/dragonclaw/dragonclaw_v0.2.brd
+[schematic]: https://raw.githubusercontent.com/coreboot/chrome-ec/HEAD/docs/schematics/dragonclaw/dragonclaw_v0.2.html
diff --git a/docs/sitemap.md b/docs/sitemap.md
index 38049c1b7d..1d9b2b3cb4 100644
--- a/docs/sitemap.md
+++ b/docs/sitemap.md
@@ -25,16 +25,20 @@
 
 *   [Fingerprint MCU (FPMCU)](./fingerprint/fingerprint.md)
 *   [FPMCU Development for Partners](./fingerprint/fingerprint-dev-for-partners.md)
+*   [FPMCU Firmware Testing for Partners](./fingerprint/fingerprint-firmware-testing-for-partners.md)
 *   [FPMCU Debugging](./fingerprint/fingerprint-debugging.md)
 *   [Fingerprint Authentication Design Doc](./fingerprint/fingerprint-authentication-design-doc.md)
 *   [Fingerprint Factory Requirements](./fingerprint/fingerprint-factory-requirements.md)
 *   [Fingerprint Quick Factory Guide](./fingerprint/fingerprint-factory-quick-guide.md)
 *   [Dragonclaw Schematics and Layout](./schematics/dragonclaw)
+*   [Fingerprint MCU RAM and Flash](./fingerprint/fingerprint-ram-and-flash.md)
 
 ## Testing
 
 *   [Unit Tests](./unit_tests.md)
+    *   [Zephyr Testing](./zephyr/ztest.md)
 *   [Code Coverage](./code_coverage.md)
+*   [ChromeOS EC Firmware Test Requirements](./chromeos-ec-firmware-test-requirements.md)
 
 ## Updaters
 
@@ -55,13 +59,25 @@
 *   [EC-3PO overview](./ec-3po.md)
 *   [EC-3PO design doc](./ec-3po-design.md)
 
+## Zephyr
+
+*   [Zephyr New Board Checklist](./zephyr/zephyr_new_board_checklist.md)
+*   [Building Zephyr OS](./zephyr/zephyr_build.md)
+*   [Initialization Order](./zephyr/zephyr_init.md)
+*   [Proof-of-Concept-Device Bringup](./zephyr/zephyr_poc_device_bringup.md)
+*   [Shimming](./zephyr/zephyr_shim.md)
+*   [Zephyr Testing](./zephyr/ztest.md)
+
 ## Miscellaneous
 
 *   [Low Battery Startup](./low_battery_startup.md)
 *   [I2C tracing via console commands](./i2c-debugging.md)
 *   [Application Processor to EC communication](./ap-ec-comm.md)
+*   [Reducing EC Image Size](./reducing_ec_image_size.md)
 *   [Code Reviews](./code_reviews.md)
 *   [IDE Support](./ide-support.md)
+*   [Building with Goma (Googlers only)](./goma.md)
+*   [Parallel Uprevs for ebuilds](./pupr.md)
 
 [1]:https://chromium.googlesource.com/chromiumos/platform/ec/+/cr50_stab/docs/case_closed_debugging.md
 [2]:https://chromium.googlesource.com/chromiumos/platform/ec/+/cr50_stab/docs/case_closed_debugging_cr50.md
diff --git a/docs/unit_tests.md b/docs/unit_tests.md
index 952d16b733..29311ac346 100644
--- a/docs/unit_tests.md
+++ b/docs/unit_tests.md
@@ -26,12 +26,41 @@ Build and run all unit tests:
 (chroot) ~/trunk/src/platform/ec $ make runhosttests -j
 ```
 
+## Debugging Unit Tests
+
+You need the host version of gdb:
+
+```bash
+(chroot) sudo emerge -j sys-devel/gdb
+```
+
+Then run gdb on the specific test you want to debug (the `host_command` test in this example):
+
+```
+(chroot) gdb build/host/host_command/host_command.exe
+handle SIGUSR1 noprint nostop
+break test_hostcmd_ok
+run
+```
+
 ## Writing Unit Tests
 
 Unit tests live in the [`test`] subdirectory of the CrOS EC codebase.
 
-Test-related macros (e.g., `TEST_EQ`, `TEST_NE`) and functions are defined in
-[`test_util.h`].
+All new unit tests should be written to use the Zephyr Ztest
+[API](https://docs.zephyrproject.org/latest/guides/test/ztest.html). If you are
+making significant changes to an existing test, you should also look at porting
+the test from the EC test API to the Ztest API.
+
+Using the Ztest API makes the unit tests suitable for submitting upstream to the
+Zephyr project, and reduces the porting work when the EC transitions to the
+Zephyr RTOS.
+
+### File headers
+
+Include [`test_util.h`] and any other required includes. In this example, the
+function being tested is defined in the test, but a real unit test would include
+the header file for the module that defines `some_function`.
 
 `test/my_test.c`:
 
@@ -43,9 +72,35 @@ static bool some_function(void)
 {
     return true;
 }
+```
+
+[`test_util.h`] includes `ztest.h` if `CONFIG_ZEPHYR` is defined, or defines a
+mapping from the `zassert` macros to the EC `TEST_ASSERT` macros if
+`CONFIG_ZEPHYR` is not defined.
+
+### Test cases
 
+Define the test cases. Use the `EC_TEST_RETURN` return type on these functions.
+
+```c
 /* Write a function with the following signature: */
-test_static int test_my_function(void)
+test_static EC_TEST_RETURN test_my_function(void)
+{
+    /* Run some code */
+    bool condition = some_function();
+
+    /* Check that the expected condition is correct. */
+    zassert_true(condition);
+
+    return EC_SUCCESS;
+}
+```
+
+`test/my_test.c`:
+
+```c
+/* Write a function with the following signature: */
+test_static EC_TEST_RETURN test_my_function(void)
 {
     /* Run some code */
     bool condition = some_function();
@@ -57,9 +112,27 @@ test_static int test_my_function(void)
 }
 ```
 
+The only difference between those two versions of `test/my_test.c` is the
+assertion: `c zassert_true(condition);` versus `c TEST_EQ(condition, true,
+"%d");`
+
+### Specify the test cases to run
+
+The EC test API enumerates the test cases using `RUN_TEST` in the `run_test`
+function, while the Ztest API enumerates the test cases using `ztest_unit_test`
+inside another macro for the test suite, inside of `test_main`.
+
 `test/my_test.c`:
 
 ```c
+#ifdef CONFIG_ZEPHYR
+void test_main(void)
+{
+    ztest_test_suite(test_my_unit,
+             ztest_unit_test(test_my_function));
+    ztest_run_test_suite(test_my_unit);
+}
+#else
 /* The test framework will call the function named "run_test" */
 void run_test(int argc, char **argv)
 {
@@ -69,8 +142,15 @@ void run_test(int argc, char **argv)
     /* Report the results of all the tests at the end. */
     test_print_result();
 }
+#endif /* CONFIG_ZEPHYR */
 ```
 
+### Task List
+
+EC unit tests can run additional tasks besides the main test thread. The EC unit
+test implementation provides a phtreads-based implementation of the EC task API.
+We do not yet support running additional tasks in Ztest-based tests.
+
 In the [`test`] subdirectory, create a `tasklist` file for your test that lists
 the tasks that should run as part of the test:
 
@@ -83,7 +163,9 @@ the tasks that should run as part of the test:
 #define CONFIG_TEST_TASK_LIST
 ```
 
-Add the test to the `Makefile`:
+### Makefile
+
+Add the test to the `Makefile` so that it can build as an EC unit test:
 
 `test/build.mk`:
 
@@ -104,25 +186,45 @@ Make sure you test shows up in the "host" tests:
 host-my_test
 run-my_test
 ```
+### Test Config File
 
-Build and run the test:
+Add any test-specific configurations to the [test_config.h](https://source.chromium.org/chromiumos/chromiumos/codesearch/+/HEAD:src/platform/ec/test/test_config.h) file:
+
+```c
+#ifdef TEST_<my_test>
+/*
+ * Add test-specific configurations here.
+ */
+#endif
+```
+
+### Build and Run
+
+Build and run the test as an EC unit test:
 
 ```bash
 (chroot) $ make run-my_test
 ```
 
+For building the test as a Zephyr Ztest unit test, follow the instructions in
+[Porting EC unit tests to Ztest](./zephyr/ztest.md) to build the unit test for Zephyr's
+"native_posix" host-based target.
+
+<!-- mdformat off(b/139308852) -->
 *** note
 **TIP**: Unit tests should be independent from each other as much as possible.
 This keeps the test (and any system state) simple to reason about and also
 allows running unit tests in parallel. You can use the
 [`before_test` hook][`test_util.h`] to reset the state before each test is run.
 ***
+<!-- mdformat on -->
 
 ## Mocks
 
-[Mocks][`mock`] enable you to simulate behavior for parts of the system that
-you're not directly testing. They can also be useful for testing specific edge
-cases that are hard to exercise during normal use (e.g., error conditions).
+We do not yet support mocks for Zephyr Ztest-based tests. [Mocks][`mock`] enable
+you to simulate behavior for parts of the system that you're not directly
+testing. They can also be useful for testing specific edge cases that are hard
+to exercise during normal use (e.g., error conditions).
 
 See the [Mock README] for details.
 
diff --git a/docs/usb-c.md b/docs/usb-c.md
index 1549b2abcc..5fa2c9953c 100644
--- a/docs/usb-c.md
+++ b/docs/usb-c.md
@@ -1,7 +1,24 @@
 # EC Implementation of USB-C Power Delivery and Alternate Modes
 
-USB-C PD requires a complex state machine as USB-C PD can operate in many
-different modes. This includes but isn't limited to:
+USB-C is intended to be a flexible connector supporting multiple data rates,
+protocols, and power in either direction. For one connector to support varying
+states of power delivery, the system and what it is connected to
+must decide who will act as the source (drives power) and sink (consumes power).
+Additionally, they need to decide the correct voltage and current for the source
+to drive by taking into account not only the source's and sink's capabilities,
+but also what the cable can support. Resistance of pull-up and pull-down resistors
+on the configuration channel (CC) ports of the USB-C connector are used to
+negotiate who is source and who is sink when a new USB-C connection is established.
+This allows for setting power characteristics to default USB2 (500mA) default
+USB3 (900mA) 1.5A and 3.0A at 5V. Additional power requirements using USB-PD must
+then be negotiated by the source and sink over the CC pins of the USB-C connectors.
+Beyond power contract negotiations, USB PD messages can be used to enable alternate
+modes (Example: DisplayPort) and send a class of messages called Structured Vendor
+Defined Message (SVDMs), which are not related to power delivery. The additional
+flexiblity and functionality in USB-C requires support from the OS.
+
+From the system, USB PD requires a complex state machine as USB PD can
+operate in many different modes. This includes but isn't limited to:
 
 *   Negotiated power contracts. Either side of the cable can source or sink
     power up to 100W (if supported by device).
@@ -12,7 +29,9 @@ different modes. This includes but isn't limited to:
     *   USB SuperSpeed mode (up to 4 lanes for USB data)
     *   DisplayPort Alternate Mode (up to 4 lanes for DisplayPort data)
     *   Dock Mode (2 lanes for USB data, and 2 lanes for DisplayPort)
+    *   Thunderbolt 3 (TBT3) Alternate Mode (4 lanes for TBT3 data)
     *   Audio Accessory mode. (1 lane is used for L and R analog audio signal)
+    *   USB4 (4 lanes for USB data, but using different signaling than USB 3.2)
 
 For a more complete list of USB-C Power Delivery features, see the
 [USB-C PD spec][USB PD Spec Id].
@@ -71,18 +90,26 @@ Modes in the EC codebase.
     *   Upstream Facing Port. The USB data role that is typical for a peripheral
         (e.g. HID keyboard).
 *   DFP {#dfp}
+
     *   Downstream Facing Port. The USB Data role that is typical for a host
         machine (e.g. device running ChromeOS).
 
 *   E-Mark {#emark}
+
     *   Electronically marked cable. A USB-C cable that contains an embedded
         chip in the cable, used to identify the capabilities of the cable.
 
 *   VCONN {#vconn}
+
     *   Connector Voltage. A dedicated power supply rail for [E-Mark](#emark)
         cables and other accessory functions (such as display dongles, and
         docks). VCONN re-uses one of the CC1/CC2 signals to provide 5 volt, 1
         watt, of power.
+*   VDM
+    * Vendor-Defined Message: A type of PD data message whose contents can be
+      specific to a particular vendor or subordinate specification. The TCPM
+      primarily uses VDMs to discover support for alternate modes and enter
+      them.
 
 ## Different PD stacks
 
@@ -93,6 +120,8 @@ Right now platform/ec has two different implementations of USB-C PD stack.
     [`usb_pd_policy.c`](../common/usb_pd_policy.c)
 2.  The newer implementation is found under [`common/usbc`](../common/usbc) and
     is broken up into multiple different files and state machines
+    *   Device policy manager files, `usb_pd_dpm.c`, `usb_mode.c`,
+        `*_alt_mode.c`.
     *   Policy engine state machine files, `usb_pe_*_sm.c`.
     *   Protocol engine state machine file, `usb_prl_*_sm.c`.
     *   State machine framework file, `usb_sm.c`.
@@ -205,8 +234,8 @@ TODO(https://crbug.com/974302): mention `USB_CHG_P#` and `CHARGER`
 
 ## Upgrading FW for TCPCs
 
-TODO(https://crbug.com/974302): Mention how this works even though it is in depthcharge.
-Probing now. Need new driver in depthcharge
+TODO(https://crbug.com/974302): Mention how this works even though it is in
+depthcharge. Probing now. Need new driver in depthcharge
 
 [Case Closed Debugging (CCD)]: https://chromium.googlesource.com/chromiumos/platform/ec/+/cr50_stab/docs/case_closed_debugging_cr50.md
 [Introduction to USB Power Delivery]: https://www.microchip.com/wwwAppNotes/AppNotes.aspx?appnote=en575003
diff --git a/docs/usb-tcpmv2.md b/docs/usb-tcpmv2.md
index 0afd07c3e6..b09805177f 100644
--- a/docs/usb-tcpmv2.md
+++ b/docs/usb-tcpmv2.md
@@ -1,6 +1,11 @@
 # EC USB-C Power Delivery TCPMv2 Overview
 
-As the original USB-C Power Delivery (PD) solution for the ChromeOS Embedded Controller has aged, it has grown to the point where it is difficult to add new features and address bugs.  A new PD stack (generally referred to as TCPMv2) has been introduced to the codebase for use moving forward.  It implements a layered, state-based design which tracks more closely with the USB Type-C and USB PD specifications.
+As the original USB-C Power Delivery (PD) solution for the ChromeOS Embedded
+Controller has aged, it has grown to the point where it is difficult to add new
+features and address bugs. A new PD stack (generally referred to as TCPMv2) has
+been introduced to the codebase for use moving forward. It implements a layered,
+state-based design which tracks more closely with the USB Type-C and USB PD
+specifications.
 
 [TOC]
 
@@ -8,38 +13,51 @@ As the original USB-C Power Delivery (PD) solution for the ChromeOS Embedded Con
 
 Boards may enable TCPMv2 by adding the following defines:
 
-
-
 *   `CONFIG_USB_PD_TCPMV2`Configures the board to use the new stack.
-*   `CONFIG_USB_DRP_ACC_TRYSRC`: Configures the type of state machine to run (in this case, a DRP which performs Try.SRC behavior).  Currently available are DRP and charge-through Vconn-powered device options
-*   `CONFIG_USB_PD_DECODE_SOP`: Sets up messaging for SOP’ and SOP’’, which is strongly encouraged in the TCPMv2 code moving forward
-*   `CONFIG_USB_PID 0x1234`: Sets the USB Product Identifier.  This will be shared for all boards within one reference design, and new PIDs may be requested by sending an email to the ChromeOS FW Team.
-*   `CONFIG_USB_PD_REV30`: The TCPMv2 stack defaults to PD2.0 operation but defining this macro enables PD3.0 functionality.
-
-Other configurations to specify behaviors within the task still apply (ex. `CONFIG_USB_PD_ALT_MODE_DFP` and `CONFIG_USB_PD_TCPC_LOW_POWER`).
-
+*   `CONFIG_USB_DRP_ACC_TRYSRC`: Configures the type of state machine to run (in
+    this case, a DRP which performs Try.SRC behavior). Currently available are
+    DRP and charge-through Vconn-powered device options
+*   `CONFIG_USB_PD_DECODE_SOP`: Sets up messaging for SOP’ and SOP’’, which is
+    strongly encouraged in the TCPMv2 code moving forward
+*   `CONFIG_USB_PID 0x1234`: Sets the USB Product Identifier. This will be
+    shared for all boards within one reference design, and new PIDs may be
+    requested by sending an email to the ChromeOS FW Team.
+*   `CONFIG_USB_PD_REV30`: The TCPMv2 stack defaults to PD2.0 operation but
+    defining this macro enables PD3.0 functionality.
+
+Other configurations to specify behaviors within the task still apply (ex.
+`CONFIG_USB_PD_ALT_MODE_DFP` and `CONFIG_USB_PD_TCPC_LOW_POWER`).
 
 ## State Machine Framework
 
-The basis of the TCPMv2 state machines is a generic state machine framework.  This framework can be found in common/usbc/usb\_sm.c.  For each state, there may be defined:
-
-
+The basis of the TCPMv2 state machines is a generic state machine framework.
+This framework can be found in common/usbc/usb\_sm.c. For each state, there may
+be defined:
 
 *   Entry: Called upon entering a state
 *   Run: Called while steady in a state
 *   Exit: Called upon leaving a state
-*   Parent: Superstate.  Enters, exits, and runs alongside the child state.  Only enters and exits when transitioning between states which do not share the parent.
-
-All fields are optional and may be set to NULL.  A new state is transitioned to with a call into set\_state(), which exits the old state and parents and enters the new parents and state.  States may be changed with set\_state() in any entry or run function, but any call from an exit function is ignored since exit is only called when a change is already in progress.  While in a state, run\_state() executes the run function for the current state and parents.  If set\_state() is called from either an entry function or a run function, the remaining run or entry functions are stopped.
-
-Below is a graphical example of what some states may look like.  States 1 and 2 share Parent State 1, while State 3 has Parent State of 2.
-
+*   Parent: Superstate. Enters, exits, and runs alongside the child state. Only
+    enters and exits when transitioning between states which do not share the
+    parent.
+
+All fields are optional and may be set to NULL. A new state is transitioned to
+with a call into set\_state(), which exits the old state and parents and enters
+the new parents and state. States may be changed with set\_state() in any entry
+or run function, but any call from an exit function is ignored since exit is
+only called when a change is already in progress. While in a state, run\_state()
+executes the run function for the current state and parents. If set\_state() is
+called from either an entry function or a run function, the remaining run or
+entry functions are stopped.
+
+Below is a graphical example of what some states may look like. States 1 and 2
+share Parent State 1, while State 3 has Parent State of 2.
 
 ![Example States](images/TCPMv2-ExampleStates.png "Example States")
 
-
-Translated into code, this would be something like below (note it is not necessary that the states be a part of an array, but the TCPMv2 code generally organizes the states in this way):
-
+Translated into code, this would be something like below (note it is not
+necessary that the states be a part of an array, but the TCPMv2 code generally
+organizes the states in this way):
 
 ```
 static const struct usb_state test_states[] = {
@@ -74,23 +92,18 @@ static const struct usb_state test_states[] = {
 };
 ```
 
-
-For this example, each test state is written simply to produce a print of its function name.  The two exceptions are:
-
-
+For this example, each test state is written simply to produce a print of its
+function name. The two exceptions are:
 
 *   parent\_1\_run() calls set\_state() into STATE\_2 when called a second time
 *   state\_2\_entry() calls set\_state() into STATE\_3
 
 Graphically, this is represented below:
 
-
 ![Example Transitions](images/TCPMv2-ExampleTransitions.png "Example state transitions and resulting called functions")
 
-
 And the following code output is produced:
 
-
 ```
 Calling run_state()
 state_1_run
@@ -112,74 +125,186 @@ state_3_run
 parent_2_run
 ```
 
+## TCPMv2 PD Task
 
+The TCPMv2 PD task is built upon state machines using the above framework and is
+located in common/usbc/usbc\_task.c. It is separated into three layers which
+track with the USB Type-C and USB PD specification states and run in a loop with
+5 ms periods between executions. A graphical representation of these layers is
+below.
 
-## TCPMv2 PD Task
+![PD Task Loop](images/TCPMv2-TaskLoop.png "PD task loop state machine calls")
 
-The TCPMv2 PD task is built upon state machines using the above framework and is located in common/usbc/usbc\_task.c.  It is separated into three layers which track with the USB Type-C and USB PD specification states and run in a loop with 5 ms periods between executions.  A graphical representation of these layers is below.
+The task is designed such that the Type-C (TC) layer could run independently for
+any application which doesn’t wish to enable PD messaging. Boards define their
+appropriate Policy Engine (PE) and TC state machines through their selection of
+a CONFIG\_USB\_\* define, with current options supporting both Dual-Role Ports
+(DRPs) and Charge-Through Vconn-Powered Device (CTVPD). All boards use the same
+Protocol Layer (PRL) code.
 
+## TCPMv2 Layers
 
+### Overview
 
-![PD Task Loop](images/TCPMv2-TaskLoop.png "PD task loop state machine calls")
+The three state machines mentioned above interact with each other and the EC
+drivers in order to orchestrate all Type-C connection behavior. Graphically,
+they are represented below.
 
+![PD Task Layers](images/TCPMv2-TaskLayers.png "PD task layer interactions")
 
-The task is designed such that the Type-C (TC) layer could run independently for any application which doesn’t wish to enable PD messaging.  Boards define their appropriate Policy Engine (PE) and TC state machines through their selection of a CONFIG\_USB\_\* define, with current options supporting both Dual-Role Ports (DRPs) and Charge-Through Vconn-Powered Device (CTVPD).  All boards use the same Protocol Layer (PRL) code.
+Layers communicate with each other using atomic operations on flags and shared
+buffers. Functions calling into each layer are clearly named to indicate the
+layer they are acting on, and anything calling into the PD task should be doing
+so through pd\_\* named functions.
+
+Some specific examples of how this communication works between layers is below.
+If a port partner sends in a Vconn\_swap request, then:
+
+*   PRL will communicate that a message was received to the PE layer through
+    pe\_message\_received(), which sets PE\_FLAGS\_MSG\_RECEIVED and indicates
+    the receive buffer has a message
+*   PE asks with the TC whether the board is sourcing Vconn with
+    tc\_is\_vconn\_src() which checks TC\_FLAGS\_VCONN\_ON
+*   PE tells the PRL to send an ACCEPT message to the port partner through
+    prl\_send\_ctrl\_msg() which fills in shared message information and sets
+    PRL\_FLAGS\_MSG\_XMIT
+*   PRL lets the PE know that the message transmit was successful through
+    pe\_message\_sent() which sets PE\_FLAGS\_TX\_COMPLETE
+*   TC tells the PE layer that the Vconn swap completed with
+    pe\_vconn\_swap\_complete() which sets PE\_FLAGS\_VCONN\_SWAP\_COMPLETE
 
+### Type-C Layer
 
-## TCPMv2 Layers
+Defined in the USB Type-C specification, this layer is responsible for basic
+connection. It takes care of setting the CC lines, detecting and debouncing the
+partner CC lines, and performs most of the interactions needed with the PPC and
+USB mux. Once the TC layer has gotten the connection to the point of being
+Attached.SNK or Attached.SRC, it will enable the PRL and PE layers accordingly.
 
+### Protocol Layer
 
-### Overview
+A part of the USB PD specification, the protocol layer is responsible for the
+actual sending and receiving of PD messages with the TCPCs. The layer is
+actually composed of 4 separate state machines running one after the other.
+These state machines are:
 
-The three state machines mentioned above interact with each other and the EC drivers in order to orchestrate all Type-C connection behavior.  Graphically, they are represented below.
+*   Chunked receive (RCH): passes messages up to the PE and requests chunks when
+    chunking
+*   Chunked transmit (TCH): receives messages from the PE and waits for chunk
+    requests when chunking
+*   Protocol transmit (PRL\_TX): passes messages to the TCPCs and handles PD 3.0
+    collision avoidance
+*   Protocol hard reset (PRL\_HR): responds to or transmits hard resets, resets
+    PRL layer variables, notifies PE of hard reset receipt or sent
 
+### Policy Engine Layer
 
+The PE layer states are defined as a part of the USB PD specification. State
+names are meant to track very closely with the specification so they can be
+easily searchable and understood. The PE’s primary responsibility is to send and
+process PD messages in order to implement the port’s policy.
 
-![PD Task Layers](images/TCPMv2-TaskLayers.png "PD task layer interactions")
+### Device Policy Manager Layer
 
+The USB PD specification defines some responsibilities of the DPM, e.g.
+selecting _Source Capabilities_ to offer and alternate modes to enter. Broadly,
+the DPM is supposed to make discretionary decisions about the behavior of the
+PE, i.e. policy decisions. However, the spec is relatively silent on the
+structure and scope of the DPM.
 
-Layers communicate with each other using atomic operations on flags and shared buffers.  Functions calling into each layer are clearly named to indicate the layer they are acting on, and anything calling into the PD task should be doing so through pd\_\* named functions.
+In TCPMv2, the DPM consists of a central code module in `usb_pd_dpm.c` and
+several code modules for supported alternate or USB modes. The mode entry and
+exit logic in the DPM takes the form of a state machine, and each mode has its
+own state machine to control the specific mode entry and exit steps. The DPM
+also contains logic to choose which Source PDO to offer in _Source
+Capabilities_.
 
-Some specific examples of how this communication works between layers is below.  If a port partner sends in a Vconn\_swap request, then:
+The DPM state machines do not currently use the USB state machine framework.
+Additionally, there are policy decisions encoded in the lower layers and in
+board code that ought to be made by the DPM. An effort to centralize policy
+decisions and improve DPM code organization is ongoing.
 
+## Alternate modes and USB4
 
+TCPMv2 supports several modes of operation besides USB 3.2. To determine which
+modes the port partner and cable support, the TCPM sends _SOP_ and _SOP'_
+Vendor-Defined Messages, specifically _Discover Identity_, _Discover SVIDs_,
+and _Discover Modes_. The responses to these messages list supported modes. The
+AP may query this information via `EC_CMD_TYPEC_DISCOVERY`.
 
-*   PRL will communicate that a message was received to the PE layer through pe\_message\_received(), which sets PE\_FLAGS\_MSG\_RECEIVED and indicates the receive buffer has a message
-*   PE asks with the TC whether the board is sourcing Vconn with tc\_is\_vconn\_src() which checks TC\_FLAGS\_VCONN\_ON
-*   PE tells the PRL to send an ACCEPT message to the port partner through prl\_send\_ctrl\_msg() which fills in shared message information and sets PRL\_FLAGS\_MSG\_XMIT
-*   PRL lets the PE know that the message transmit was successful through pe\_message\_sent() which sets PE\_FLAGS\_TX\_COMPLETE
-*   TC tells the PE layer that the Vconn swap completed with pe\_vconn\_swap\_complete() which sets PE\_FLAGS\_VCONN\_SWAP\_COMPLETE
+Based on the discovery responses, the DPM decides which mode to enter (if any)
+and drives mode entry. If `CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY` is enabled, the
+AP directs the DPM to enter and exit modes via `EC_CMD_TYPEC_CONTROL`.
 
+### DisplayPort
 
-### Type-C Layer
+DisplayPort alternate mode repurposes the SuperSpeed lanes as video data lanes,
+all flowing from the host to the monitor. DP mode can use 2 lanes, allowing
+simultaneous USB traffic on the cable, or it can use all 4 lanes, supporting
+greater display bandwidth at the expense of USB.
 
-Defined in the USB Type-C specification, this layer is responsible for basic connection.  It takes care of setting the CC lines, detecting and debouncing the partner CC lines, and performs most of the interactions needed with the PPC and USB mux.  Once the TC layer has gotten the connection to the point of being Attached.SNK or Attached.SRC, it will enable the PRL and PE layers accordingly.
+The sequence to enter DP alternate mode (v. 1.4) is
+*   The TCPM sends an SOP VDM _Enter Mode_ REQ with the DP VID.
+*   The TCPM sends an SOP _DP Status_ VDM REQ.
+*   The TCPM sends an SOP _DP Configure_ VDM REQ.
+*   Display sends an SOP _Attention_ VDM REQ.
 
+To exit DP alternate mode, the TCPM sends an SOP VDM _Exit Mode_ REQ.
 
-### Protocol Layer
+`dp_alt_mode.c` and `usb_pd_alt_mode_dfp.c` contain the majority of the DP entry
+and exit logic.
 
-A part of the USB PD specification, the protocol layer is responsible for the actual sending and receiving of PD messages with the TCPCs.  The layer is actually composed of 4 separate state machines running one after the other.  These state machines are:
+### Thunderbolt 3
 
+TBT3 alternate mode repurposes all 4 SuperSpeed lanes for Thunderbolt 3, which
+is itself a bidirectional tunneling protocol supporting various types of
+hardware, most commonly docks.
 
+The sequence to enter TBT3 alternate mode depends on the cable used:
+*   If the cable supports TBT3, the TCPM sends an SOP' VDM _Enter Mode_ REQ with
+    the Intel VID.
+*   If the cable is also an active cable with SOP'' support, the TCPM sends an
+    SOP'' VDM _Enter Mode_ REQ. (The TBT3 mode VDO may identify the cable as
+    active for this purpose when the ID Header VDO does not.)
+*   The TCPM sends an SOP VDM _Enter Mode_ REQ.
 
-*   Chunked receive (RCH):  passes messages up to the PE and requests chunks when chunking
-*   Chunked transmit (TCH): receives messages from the PE and waits for chunk requests when chunking
-*   Protocol transmit (PRL\_TX): passes messages to the TCPCs and handles PD 3.0 collision avoidance
-*   Protocol hard reset (PRL\_HR): responds to or transmits hard resets, resets PRL layer variables, notifies PE of hard reset receipt or sent
+To exit TBT3 alternate mode, the TCPM sends VDM _Exit Mode_ REQs to SOP, SOP'',
+and SOP', as appropriate.
 
+`tbt_alt_mode.c` and `usb_pd_alt_mode_dfp.c` contain the TBT entry and exit
+logic.
 
-### Policy Engine Layer
+### USB4
 
-The PE layer states are defined as a part of the USB PD specification.  State names are meant to track very closely with the specification so they can be easily searchable and understood.  The PE’s primary responsibility is to send and process PD messages in order to implement the port’s policy.
+USB4 is not an alternate mode, but it does repurpose the SuperSpeed lines (using
+different signaling and routing than USB 3.2), so the TCPM must explicitly enter
+USB4.
 
+The sequence to enter USB4 is conceptually similar to that for TBT3:
+*   If the cable supports USB4, the TCPM sends an SOP' _Enter USB_ message.
+*   If the cable is also an active cable, the TCPM sends an SOP'' _Enter USB_.
+*   The TCPM sends an SOP _Enter USB_.
+Complicating matters, if the cable does not support USB4 but does support TBT3,
+the TCPM may enter TBT3 for the cable as above, then enter USB4 for the port
+partner.
 
-## Best Practices
+To exit USB4 (returning to a USB 3.2 mux configuration), the TCPM performs a
+_Data Reset_ sequence.
 
+`usb_mode.c` and `usb_pd_alt_mode_dfp.c` contain the USB4 entry and exit logic.
 
+## Best Practices
 
-*   Always call return after set\_state().  Once the state has been changed, nothing further should be done in the current state.
-*   Never call set\_state() from an exit function.  The call will be ignored as there is already a state transition taking place.
-*   Never call set\_state() from outside the PD task.  The task may be waiting in any number of locations and the context should not change around it while it does so.
-*   Always use flags to communicate between layers, and to communicate with the PD task from other tasks.  Flags should be accessed through atomic operations.
+*   Always call return after set\_state(). Once the state has been changed,
+    nothing further should be done in the current state.
+*   Never call set\_state() from an exit function. The call will be ignored as
+    there is already a state transition taking place.
+*   Never call set\_state() from outside the PD task. The task may be waiting in
+    any number of locations and the context should not change around it while it
+    does so.
+*   Always use flags to communicate between layers, and to communicate with the
+    PD task from other tasks. Flags should be accessed through atomic
+    operations.
 *   Always use pd\_\* functions to access the PD task from other tasks.
-*   Always write unit tests as code is added, to verify new code works and protect against regressions as development continues.
+*   Always write unit tests as code is added, to verify new code works and
+    protect against regressions as development continues.
diff --git a/docs/usb_power.md b/docs/usb_power.md
index e066a7bba6..95177dc150 100644
--- a/docs/usb_power.md
+++ b/docs/usb_power.md
@@ -135,43 +135,59 @@ in-depth information can be found in the [USB Type-C Specification] \(section
 
 ### ChromeOS as Source - Policy for Type-C
 
+**Note:** Behavior outlined here is only implemented in the TCPMv2 Device
+Policy Manager (DPM) when a board defines a non-zero maximum number of 3A
+ports supported through `CONFIG_USB_PD_3A_PORTS`.
+
 ChromeOS devices currently source power to external USB devices at 5V with a
-typical current of 1.5A for each Type-C port. In certain scenarios, a single
-Type-C port can source up to 3A @ 5V.
-
-ChromeOS prefers that the first PD-capable Type-C device **that claims 3A**
-should get 3A guaranteed at 5V. Once a PD-capable Type-C device has claimed 3A,
-then other PD-capable Type-C devices will only be offered a maximum of 1.5A.
-
-If there are no PD-capable Type-C devices claiming 3A, then the first non-PD
-device will be given 3A until a PD-capable device **that claims 3A** is
-inserted.
-
-The 3A is only offered after a minimum delay of 200 ms following the initial
-connection. One main reason for this delay is to protect against non-PD capabale
-devices that only sample the CC resistors once at initial connection from
-continuing to consume 3A after we downgrade the CC resistors to 1.5A at a later
-point in the future. The motivation for this is that any non-PD device that
-notices that it can draw more current from a CC resistor change that happens 200
-ms after the initial connection will also notice a CC resistor change if we
-downgrade the CC resistors to a lower current advertisement. We want consistent
-behavior across non-PD capable devices and PD-capable devices, so we will only
-offer the additional 1.5A to PD ports after the same delay.
-
-When a device that is currently claiming 3A is removed or proactively reduces
-its power contract to 1.5A or less, then the next oldest PD-capable device is
-offered 3A in order. If no PD-capable devices claims 3A, then the oldest non-PD
-capable device is given 3A through a CC resistor change.
+typical current of 1.5A for each Type-C port. In certain scenarios, a Type-C
+port can source up to 3A @ 5V.
+
+ChromeOS prefers that the first PD-capable Type-C device **that requires 3A**
+should get 3A guaranteed at 5V. Once the maximum supported number of PD-capable
+Type-C device has claimed 3A, then other PD-capable Type-C devices will only be
+offered a maximum of 1.5A.
+
+If Fast Role Swap (FRS) is supported and a sourcing port partner reports
+requiring 3A after a fast role swap, then this port should be allocated 3A if
+no more PD-capable sinks require 3A, and FRS detection may be enabled.  Once a
+PD-capable device **that requires 3A** is inserted, the FRS port may have FRS
+detection disabled if the maximum number of 3A ports has been reached.
+
+If there are no PD-capable Type-C devices requiring 3A and no FRS ports
+requiring 3A, then the first non-PD device will be given 3A until a PD-capable
+device **that requires 3A** is inserted, or until an FRS source that requires
+3A is inserted.
+
+Devices will indicate they require 3A operating current in their sink
+capabilities, and this will be used as the trigger to let the EC know to
+offer that port a 3A source contract.  FRS source partners will also
+indicate the need for 3A in their sink capabilities, under their Fast Role
+Swap required current.
+
+This policy is laid out in the following flow chart.  Current policy for the
+"next" port allocation is to select the lowest port number any time more than
+one port meets criteria to receive 3A.
+
+Port balancing will occur when:
+* Sink Capabilities are received for a device
+* Source capabilities are not replied to after nCapsCount, indicating a non-PD
+  sink
+* Power roles are swapped
+* Detach occurs
+
+![Source Port Balancing](images/usb_source_port_balancing.png "Source Port Balancing")
 
 Inserting a Type-A device does not affect the power assignment for Type-C ports;
 only Type-C devices affect the power of Type-C ports.
 
-For example, the below sequence of events illustrates the above Type-C policy:
+For example, the below sequence of events illustrates the above Type-C policy
+with a board with a maximum number of 1 3A-ports supported:
 
 1.  A non-PD capable Type-C keyboard is inserted first
     *   Keyboard will be offered 1.5A initially
     *   Current state: `keyboard @ 1.5A`.
-2.  More than 200ms pass.
+2.  Partner is established to be non-PD through reaching PE\_SRC\_Disabled.
     *   Since there are no other PD-capable devices and this is the first
         device, offer this device 3A via CC resistor change.
     *   Current state: `keyboard @ 3A`.
@@ -179,53 +195,64 @@ For example, the below sequence of events illustrates the above Type-C policy:
     *   It will be offered 1.5A since there is already another non-PD device
         claiming 3A.
     *   Current state: `keyboard @ 3A` and `mouse @ 1.5A`.
-4.  A PD-capable Type-C dock is inserted third
-    *   Initially negotiate for 1.5A, then wait 200ms after negotiating.
-    *   Since this is the first PD device, we offer it 3A after 200ms from
-        initial power negotiation.
-    *   Dock does not want high power from Chromebook; dock continues to selects
+4.  A PD-capable Type-C hub is inserted third
+    *   Initially negotiate for 1.5A.
+    *   Since this is a PD device, query its operational current through
+        requesting Sink Capabilities.
+    *   Hub does not want high power from Chromebook; hub continues to receive
         1.5A.
     *   Keyboard gets to maintain higher 3A current supply.
-    *   Current state: `keyboard @ 3A` and `mouse @ 1.5A` and `dock @ 1.5A`.
+    *   Current state: `keyboard @ 3A` and `mouse @ 1.5A` and `hub @ 1.5A`.
 5.  A PD-capable Type-C phone is inserted fourth
     *   Phone is initially offered 1.5A.
-    *   Since there isn't an existing PD-capable device claiming 3A, the phone
-        is offered 3A after waiting the 200ms delay from initial negotiation.
-    *   The phone wants high power; phone selects 3A.
+    *   Since this is a PD device, query its operational current through
+        requesting Sink Capabilities.
+    *   The phone reports it wants 3A.
     *   Since PD devices are preferred for 3A, the non-PD keyboard will be
         downgraded from 3A to 1.5A via a CC resistor change.
-    *   Current state: `keyboard @ 1.5A` and `mouse @ 1.5A` and `dock @ 1.5A`
+    *   After tSinkAdj (60 ms), phone is offered 3A through new Source
+        Capabilities.
+    *   Current state: `keyboard @ 1.5A` and `mouse @ 1.5A` and `hub @ 1.5A`
         and `phone @ 3A`.
 6.  A PD-capable Type-C tablet is inserted fifth
-    *   Since there is already a PD-capable device claiming 3A, the tablet is
-        only offered 1.5A.
-    *   Current state: `keyboard @ 1.5A` and `mouse @ 1.5A` and `dock @ 1.5A`
+    *   Tablet is initially offered 1.5A.
+    *   Since this is a PD device, query its operational current through
+        requesting Sink Capabilities.
+    *   Tablet would like 3A, but the board has reached its maximum number of
+        supported 3A ports.  Note this port's desired current for later.
+    *   Current state: `keyboard @ 1.5A` and `mouse @ 1.5A` and `hub @ 1.5A`
         and `phone @ 3A` and `tablet @ 1.5A`.
-7.  The PD-capable phone is done charging so it downgrades its power contract to
-    1.5A without any user interaction
-    *   The next oldest PD-capable device is offered 3A in order: dock then
-        phone then tablet.
-    *   The dock and phone continue to select 1.5A, then the tablet takes 3A.
-    *   Current state: `keyboard @ 1.5A` and `mouse @ 1.5A` and `dock @ 1.5A`
-        and `phone @ 1.5A` and `tablet @ 3A`.
-8.  The PD-capable tablet is removed
-    *   The next oldest PD-capable device is offered 3A. If there are no
-        PD-capable devices claiming 3A, then the oldest non-PD capable device is
-        given 3A.
-    *   The dock and phone continue to select 1.5A, so keyboard is given 3A via
-        CC resistor change.
-    *   Current state: `keyboard @ 3A` and `mouse @ 1.5A` and `dock @ 1.5A` and
-        `phone @ 1.5A`.
-9.  The non-PD capable keyboard is removed
-    *   The next oldest PD-capable device is offered 3A. If there are no
-        PD-capable devices claiming 3A, then the next oldest non-PD capable
-        device is given 3A.
-    *   The dock and phone continue to select 1.5A, so mouse is given 3A via CC
+7.  The PD-capable phone is removed
+    *   The next PD-capable sink device is offered 3A: the tablet
+    *   Current state: `keyboard @ 1.5A` and `mouse @ 1.5A` and `hub @ 1.5A`
+        and `tablet @ 3A`.
+8.  A FRS-capable dock is inserted
+    *   The dock is sourcing us
+    *   Since this is a PD capable device, query its FRS current through
+        requesting Sink Capabilities.
+    *   Dock reports requiring 3A current after FRS.
+    *   Tablet is currently occupying the 3A port, so note this port's desired
+        FRS current for later.
+    *   Current state: `keyboard @ 1.5A` and `mouse @ 1.5A` and `hub @ 1.5A`
+        and `tablet @ 3A`; dock `FRS detection disabled`
+9.  The PD-capable tablet is removed
+    *   The next PD-capable device requiring 3A is offered 3A. If there are
+        no PD-capable devices requiring 3A, then the next FRS device is
+        allocated 3A.
+    *   The hub only requires 1.5A, so FRS is enabled for the dock.
+    *   Current state: `keyboard @ 1.5A` and `mouse @ 1.5A` and `hub @ 1.5A`;
+        dock `FRS detection enabled`
+10.  The FRS dock is removed
+    *   The next PD-capable  device requiring 3A is offered 3A. If there are
+        no PD-capable devices requiring 3A, then the next FRS device is
+        allocated 3A.  If there are no FRS devices, then the next non-PD
+        capable device is given 3A.
+    *   The hub only requires 1.5A, so mouse is given 3A via CC
         resistor change.
-    *   Current state: `mouse @ 3A` and `dock @ 1.5A` and `phone @ 1.5A`.
-10. The non-PD capable mouse is removed
-    *   The dock and phone continue to select 1.5A.
-    *   Current state: `dock @ 1.5A` and `phone @ 1.5A`.
+    *   Current state: `keyboard @ 1.5A` and `mouse @ 3A` and `hub @ 1.5A`.
+11. The non-PD capable mouse is removed
+    *   The hub does not require 3A.
+    *   Current state: `keyboard @ 3A` and `hub @ 1.5A`.
 
 Note: Not all released Chromebooks implement the above policy due to
 pre-existing hardware design constraints.
diff --git a/docs/usb_updater.md b/docs/usb_updater.md
index 476b50f316..f1505550d1 100644
--- a/docs/usb_updater.md
+++ b/docs/usb_updater.md
@@ -1,48 +1,44 @@
-EC update over USB
-==================
+# EC update over USB
 
 chip/g (Cr50) and common code (hammer, servo_micro/v4) update over USB protocols
 share a lot in terms of protocol and ideas, but use different code bases.
 
-chip/g EC-side implementation is found in `chip/g/*upgrade*`, and the
-userspace tool which provides updates over USB among with supporting other
-features and interfaces is found in `extra/usb_updater/gsctool.c`.
+chip/g EC-side implementation is found in `chip/g/*upgrade*`, and the userspace
+tool which provides updates over USB among with supporting other features and
+interfaces is found in `extra/usb_updater/gsctool.c`.
 
 Common code uses implementations in `common/*update*.c` and
 `include/*update*.h`, and `extra/usb_updater/usb_updater2.c` for the userspace
 updater.
 
-Cr50-specific notes
--------------------
+## Cr50-specific notes
 
-The Cr50 firmware image consists of multiple sections, of interest to the
-USB updater are the RO and RW code sections, two of each. When firmware update
+The Cr50 firmware image consists of multiple sections, of interest to the USB
+updater are the RO and RW code sections, two of each. When firmware update
 session is established, the Cr50 device reports locations of backup RW and RO
 sections (those not currently used by the device).
 
 Based on this information the updater carves out the appropriate sections from
-the full Cr50 firmware binary image and sends them to the device for
-programming into flash. Once the new sections are programmed and the device
-is restarted, the new RO and RW are used if they pass verification and are
-logically newer than the existing sections.
+the full Cr50 firmware binary image and sends them to the device for programming
+into flash. Once the new sections are programmed and the device is restarted,
+the new RO and RW are used if they pass verification and are logically newer
+than the existing sections.
 
 There are two ways to communicate with the Cr50 device: USB and `/dev/tpm0`
 (when `gsctool` is running on a chromebook with the Cr50 device). Originally
-different protocols were used to communicate over different channels,
-starting with version 3 the same protocol is used.
+different protocols were used to communicate over different channels, starting
+with version 3 the same protocol is used.
 
-Common-code notes
------------------
+## Common-code notes
 
-For non-Cr50 or chip/g devices (common code), the layout is a bit different,
-as devices usually have a single RO and a single RW, where RO is truly read-only
-in production, and verifies RW before jumping to it.
+For non-Cr50 or chip/g devices (common code), the layout is a bit different, as
+devices usually have a single RO and a single RW, where RO is truly read-only in
+production, and verifies RW before jumping to it.
 
 For testing and development, `usb_updater2` is provided, while production code
 will use `hammerd` (in `src/platform/hammerd`) to update the device.
 
-Update protocol
----------------
+## Update protocol
 
 The host (either a local AP or a workstation) is the master of the firmware
 update protocol, it sends data to the Cr50 device, which processes it and
@@ -50,75 +46,76 @@ responds.
 
 The encapsulation format is different between the `/dev/tpm0` and USB cases:
 
-      4 bytes      4 bytes         4 bytes               variable size
-    +-----------+--------------+---------------+----------~~--------------+
-    + total size| block digest |  dest address |           data           |
-    +-----------+--------------+---------------+----------~~--------------+
-     \           \                                                       /
-      \           \                                                     /
-       \           +----- FW update PDU sent over /dev/tpm0 -----------+
-        \                                                             /
-         +--------- USB frame, requires total size field ------------+
+```
+  4 bytes      4 bytes         4 bytes               variable size
++-----------+--------------+---------------+----------~~--------------+
++ total size| block digest |  dest address |           data           |
++-----------+--------------+---------------+----------~~--------------+
+ \           \                                                       /
+  \           \                                                     /
+   \           +----- FW update PDU sent over /dev/tpm0 -----------+
+    \                                                             /
+     +--------- USB frame, requires total size field ------------+
+```
 
 The update protocol data units (PDUs) are passed over `/dev/tpm0`, the
-encapsulation includes integrity verification and destination address of
-the data (more of this later). `/dev/tpm0` transactions pretty much do not
-have size limits, whereas the USB data is sent in chunks of the size
-determined when the USB connection is set up. This is why USB requires an
-additional encapsulation into frames to communicate the PDU size to the
-client side so that the PDU can be reassembled before passing to the
-programming function.
-
-In general, the protocol consists of two phases: connection establishment
-and actual image transfer.
-
-The very first PDU of the transfer session is used to establish the
-connection. The first PDU does not have any data, and the `dest address`
-field is set to zero. Receiving such a PDU signals the programming function
-that the host intends to transfer a new image.
+encapsulation includes integrity verification and destination address of the
+data (more of this later). `/dev/tpm0` transactions pretty much do not have size
+limits, whereas the USB data is sent in chunks of the size determined when the
+USB connection is set up. This is why USB requires an additional encapsulation
+into frames to communicate the PDU size to the client side so that the PDU can
+be reassembled before passing to the programming function.
+
+In general, the protocol consists of two phases: connection establishment and
+actual image transfer.
+
+The very first PDU of the transfer session is used to establish the connection.
+The first PDU does not have any data, and the `dest address` field is set to
+zero. Receiving such a PDU signals the programming function that the host
+intends to transfer a new image.
 
 The response to the first PDU varies depending on the protocol version.
 
-Note that protocol versions before 5 are described here for completeness,
-but are not supported any more.
+Note that protocol versions before 5 are described here for completeness, but
+are not supported any more.
 
-Version 1 is used over `/dev/tpm0`. The response is either 4 or 1 bytes in
-size. The 4 byte response is the *base address* of the backup RW section,
-and there is no support for RO updates. The one byte response is an error
-indication, possibly reporting flash erase failure, command format error, etc.
+Version 1 is used over `/dev/tpm0`. The response is either 4 or 1 bytes in size.
+The 4 byte response is the *base address* of the backup RW section, and there is
+no support for RO updates. The one byte response is an error indication,
+possibly reporting flash erase failure, command format error, etc.
 
 Version 2 is used over USB. The response is 8 bytes in size. The first four
 bytes are either the *base address* of the backup RW section (still no RO
-updates), or an error code, the same as in Version 1. The second 4 bytes
-are the protocol version number (set to 2).
+updates), or an error code, the same as in Version 1. The second 4 bytes are the
+protocol version number (set to 2).
 
 All versions above 2 behave the same over `/dev/tpm0` and USB.
 
-Version 3 response is 16 bytes in size. The first 4 bytes are the error code
-the second 4 bytes are the protocol version (set to 3) and then 4 byte
-*offset* of the RO section followed by the 4 byte *offset* of the RW section.
+Version 3 response is 16 bytes in size. The first 4 bytes are the error code the
+second 4 bytes are the protocol version (set to 3) and then 4 byte *offset* of
+the RO section followed by the 4 byte *offset* of the RW section.
 
-Version 4 response in addition to version 3 provides header revision fields
-for active RO and RW images running on the target.
+Version 4 response in addition to version 3 provides header revision fields for
+active RO and RW images running on the target.
 
-Once the connection is established, the image to be programmed into flash
-is transferred to the Cr50 in 1K PDUs. In versions 1 and 2 the address in
-the header is the absolute address to place the block to, in version 3 and
-later it is the offset into the flash.
+Once the connection is established, the image to be programmed into flash is
+transferred to the Cr50 in 1K PDUs. In versions 1 and 2 the address in the
+header is the absolute address to place the block to, in version 3 and later it
+is the offset into the flash.
 
 Protocol version 5 includes RO and RW key ID information into the first PDU
-response. The key ID could be used to tell between prod and dev signing
-modes, among other things.
+response. The key ID could be used to tell between prod and dev signing modes,
+among other things.
 
-Protocol version 6 does not change the format of the first PDU response,
-but it indicates the target's ability to channel TPM vendor commands
-through USB connection.
+Protocol version 6 does not change the format of the first PDU response, but it
+indicates the target's ability to channel TPM vendor commands through USB
+connection.
 
 Common-code updater also uses protocol version 6, but has a fairly different
 `first_response_pdu` header, indicated by setting `1` in the higher 16-bit for
-the protocol version field (`header_type`). The response includes fields
-such as maximum PDU size (which is not fixed to 1KB like for Cr50), flash
-protection status, version string, and a minimum rollback version.
+the protocol version field (`header_type`). The response includes fields such as
+maximum PDU size (which is not fixed to 1KB like for Cr50), flash protection
+status, version string, and a minimum rollback version.
 
 Details can be found in `include/update_fw.h`.
 
@@ -128,54 +125,55 @@ This describes the EC-side state machine for update over USB.
 
 IDLE state:
 
-* If host sends update start PDU (a command without any payload, digest = 0
-  and base = 0):
+*   If host sends update start PDU (a command without any payload, digest = 0
+    and base = 0):
 
-  * Reply with `first_update_pdu` block. Go to OUTSIDE_BLOCK state.
+    *   Reply with `first_update_pdu` block. Go to OUTSIDE_BLOCK state.
 
-* If host sends a vendor command (see below), execute that, reply, and stay
-  in IDLE state. Note that vendor commands are only accepted in IDLE state.
+*   If host sends a vendor command (see below), execute that, reply, and stay in
+    IDLE state. Note that vendor commands are only accepted in IDLE state.
 
 OUTSIDE_BLOCK (preparing to receive start of PDU):
 
-* If no data is received in 5 seconds, go back to IDLE state.
-* If host sends `UPDATE_DONE` command (by setting `dest address` to
-  `0xb007ab1e`), go back to IDLE state.
-* If host sends a valid block start with a valid address, copy the rest
-  of the payload and go to INSIDE_BLOCK state.
+*   If no data is received in 5 seconds, go back to IDLE state.
+*   If host sends `UPDATE_DONE` command (by setting `dest address` to
+    `0xb007ab1e`), go back to IDLE state.
+*   If host sends a valid block start with a valid address, copy the rest of the
+    payload and go to INSIDE_BLOCK state.
 
 INSIDE_BLOCK (in a middle of a PDU):
 
-* If no data is received in 5 seconds, go back to IDLE state.
-* Copy data to a buffer.
+*   If no data is received in 5 seconds, go back to IDLE state.
+*   Copy data to a buffer.
 
-  * If buffer is full (i.e. matches the total expected PDU size), write the
-    data and go to OUTSIDE_BLOCK.
-  * Else, stay in INSIDE_BLOCK.
+    *   If buffer is full (i.e. matches the total expected PDU size), write the
+        data and go to OUTSIDE_BLOCK.
+    *   Else, stay in INSIDE_BLOCK.
 
 ### Vendor commands (channeled TPM command, Cr50)
 
 When channeling TPM vendor commands the USB frame looks as follows:
 
-      4 bytes      4 bytes         4 bytes       2 bytes      variable size
-    +-----------+--------------+---------------+-----------+------~~~-------+
-    + total size| block digest |    EXT_CMD    | vend. sub.|      data      |
-    +-----------+--------------+---------------+-----------+------~~~-------+
+```
+  4 bytes      4 bytes         4 bytes       2 bytes      variable size
++-----------+--------------+---------------+-----------+------~~~-------+
++ total size| block digest |    EXT_CMD    | vend. sub.|      data      |
++-----------+--------------+---------------+-----------+------~~~-------+
+```
 
 Where `Vend. sub` is the vendor subcommand, and data field is subcommand
 dependent. The target tells between update PDUs and encapsulated vendor
-subcommands by looking at the `EXT_CMD` value - it is set to `0xbaccd00a` and
-as such is guaranteed not to be a valid update PDU destination address.
+subcommands by looking at the `EXT_CMD` value - it is set to `0xbaccd00a` and as
+such is guaranteed not to be a valid update PDU destination address.
 
-These commands cannot exceed the USB packet size (typically 64 bytes), as
-no reassembly is performed for such frames.
+These commands cannot exceed the USB packet size (typically 64 bytes), as no
+reassembly is performed for such frames.
 
 The vendor command response size is not fixed, it is subcommand dependent.
 
-The Cr50 device responds to each update PDU with a confirmation which is 4
-bytes in size in protocol version 2, and 1 byte in size in all other
-versions. Zero value means success, non-zero value is the error code
-reported by Cr50.
+The Cr50 device responds to each update PDU with a confirmation which is 4 bytes
+in size in protocol version 2, and 1 byte in size in all other versions. Zero
+value means success, non-zero value is the error code reported by Cr50.
 
 Again, vendor command responses are subcommand specific.
 
@@ -186,17 +184,18 @@ above, except that we use `UPDATE_EXTRA_CMD` (`b007ab1f`) instead of `EXT_CMD`,
 and `Vend. sub.` have a limit set of values (unless otherwise noted, commands
 take no parameter, and reply with a single 1-byte status code):
 
-* UPDATE_EXTRA_CMD_IMMEDIATE_RESET (0): Tell EC to reboot immediately.
-* UPDATE_EXTRA_CMD_JUMP_TO_RW (1): Tell EC (in RO) to jump to RW, if the
-  signature verifies.
-* UPDATE_EXTRA_CMD_STAY_IN_RO (2): Tell EC (in RO), to stay in RO, and not
-  jump to RW automatically. After this command is sent, a reset is necessary
-  for the EC to accept to jump to RW again.
-* UPDATE_EXTRA_CMD_UNLOCK_RW (3): Tell EC to unlock RW on next reset.
-* UPDATE_EXTRA_CMD_UNLOCK_ROLLBACK (4): Tell EC to unlock ROLLBACK on next reset.
-* UPDATE_EXTRA_CMD_INJECT_ENTROPY (5): Inject entropy into the device-specific
-  unique identifier (takes at least CONFIG_ROLLBACK_SECRET_SIZE=32 bytes of
-  data).
-* UPDATE_EXTRA_CMD_PAIR_CHALLENGE (6): Tell EC to answer a X25519 challenge
-  for pairing. Takes in a `struct pair_challenge` as data, answers with a
-  `struct pair_challenge_response`.
+*   UPDATE_EXTRA_CMD_IMMEDIATE_RESET (0): Tell EC to reboot immediately.
+*   UPDATE_EXTRA_CMD_JUMP_TO_RW (1): Tell EC (in RO) to jump to RW, if the
+    signature verifies.
+*   UPDATE_EXTRA_CMD_STAY_IN_RO (2): Tell EC (in RO), to stay in RO, and not
+    jump to RW automatically. After this command is sent, a reset is necessary
+    for the EC to accept to jump to RW again.
+*   UPDATE_EXTRA_CMD_UNLOCK_RW (3): Tell EC to unlock RW on next reset.
+*   UPDATE_EXTRA_CMD_UNLOCK_ROLLBACK (4): Tell EC to unlock ROLLBACK on next
+    reset.
+*   UPDATE_EXTRA_CMD_INJECT_ENTROPY (5): Inject entropy into the device-specific
+    unique identifier (takes at least CONFIG_ROLLBACK_SECRET_SIZE=32 bytes of
+    data).
+*   UPDATE_EXTRA_CMD_PAIR_CHALLENGE (6): Tell EC to answer a X25519 challenge
+    for pairing. Takes in a `struct pair_challenge` as data, answers with a
+    `struct pair_challenge_response`.
diff --git a/docs/write_protection.md b/docs/write_protection.md
index 00e384ee16..65f04f2fa5 100644
--- a/docs/write_protection.md
+++ b/docs/write_protection.md
@@ -3,7 +3,7 @@
 [TOC]
 
 This is a somewhat tricky topic since write protection implementations can
-differ between chips and the hardware write protection has changed over time,
+differ between chips, and the hardware write protection has changed over time,
 so please edit or open a bug if something is not clear.
 
 ## Terminology
@@ -13,13 +13,13 @@ so please edit or open a bug if something is not clear.
 MCUs running the EC code have read-only (RO) and read-write (RW) firmware.
 Coming out of reset, the MCU boots into its RO firmware.
 
-In the case of the EC, the RO firmware boots the host and asks it verify a hash
-of the RW firmware (software sync). If the RW firmware is invalid, it is
+In the case of the EC, the RO firmware boots the host and asks it to verify a
+hash of the RW firmware (software sync). If the RW firmware is invalid, it is
 updated from a copy in the host's RW firmware.
 
 In the case of the FPMCU, the RO firmware uses the public key embedded in it to
-validate the signature of the RW firmware. If the RW firmware is invalid it
-does not jump to the RW firmware.
+validate the signature of the RW firmware. If the RW firmware is invalid it does
+not jump to the RW firmware.
 
 Once the RW firmware is validated, the MCU jumps to it (without rebooting). The
 RO firmware is locked in the factory and is never changed. The RW firmware can
@@ -30,44 +30,46 @@ Note that both the RO and RW firmware regions are normally protected once write
 protect has been turned on.
 
 In the case of the EC, the RW region is unprotected at MCU boot until it has
-been verified by the host. The RW region is protected before the Linux kernel
-is loaded.
+been verified by the host. The RW region is protected before the Linux kernel is
+loaded.
 
 In the case of the FPMCU, the RW region is protected before jumping the RO
 firmware jumps to it.
 
 ## Hardware Write Protect {#hw_wp}
 
-On modern Chrome OS devices, the Cr50 (aka GSC / TPM) provides a "hardware
-write protect" GPIO that is connected to the AP SPI flash, EC SPI flash,
-EEPROM, and FPMCU via a [GPIO][write_protect_gpio].  This "hardware write
-protect" can only be disabled with servo or suzyq (["CCD open"]) and
-corresponds to [`OverrideWP`] in ccd. Disabling this write protect disables it
-for everything connected to this signal.
+On modern Chrome OS devices, the Cr50 (aka GSC / TPM) provides a "hardware write
+protect" GPIO that is connected to the AP SPI flash, EC SPI flash, EEPROM, and
+FPMCU via a [GPIO][write_protect_gpio]. This "hardware write protect" can only
+be disabled with [Servo] or [SuzyQ](["CCD open"]) and corresponds to
+[`OverrideWP`] in ccd. Disabling this write protect disables it for everything
+connected to this signal.
 
 In the case of the FPMCU, the hardware write protect GPIO is tied to the STM32
 `BOOT0` pin, which is what tells the MCU to enter the STM32 bootloader mode.
 
-You may see various references to a [write protect screw in
-documentation][wp_screw]. Older Chrome OS devices had a write protect screw
-that had to be physically removed. More details on this history can be found
-here: http://go/cros-wp-status.
+You may see various references to a
+[write protect screw in documentation][wp_screw]. Older Chrome OS devices had a
+write protect screw that had to be physically removed. More details on this
+history can be found here: http://go/cros-wp-status.
 
 Another way of disabling hardware write protection is to remove the battery;
 this method is mainly used during bringup.
 
 Additional reference:
-https://www.google.com/chromeos/partner/fe/docs/cpfe/firmwaretestmanual.html#hardware-write-protect
+https://chromium.googlesource.com/chromiumos/docs/+/HEAD/write_protection.md
 
 ## Changing Hardware Write Protection
 
-Modifying the state of hardware write protection (via Cr50 GPIO) can be done
-if the ["CCD open"] process has been completed.
+Modifying the state of hardware write protection (via Cr50 GPIO) can be done if
+the ["CCD open"] process has been completed.
 
+<!-- mdformat off(b/139308852) -->
 *** note
 `servod` *must* be running for `dut-control` to work. See the [Servo] page for
 details.
 ***
+<!-- mdformat on -->
 
 ### Enable Hardware Write Protection
 
@@ -106,7 +108,7 @@ enabled or disabled (note that some implementations require an EC reset to
 disable software write protect).
 
 The underlying mechanism implementing software write protect may differ between
-EC chips. However the common requirements are that software write protect can
+EC chips. However, the common requirements are that software write protect can
 only be disabled when hardware write protect is off and that the RO firmware
 must be protected before jumping to RW firmware if protection is enabled.
 
@@ -115,18 +117,21 @@ https://www.google.com/chromeos/partner/fe/docs/cpfe/firmwaretestmanual.html#sof
 
 ## Changing Software Write Protection
 
+<!-- mdformat off(b/139308852) -->
 *** note
 *NOTE*: You cannot disable software write protect if hardware write protect is
 enabled.
 ***
+<!-- mdformat on -->
 
-Software write protection can be toggled with `ectool --name=cros_fp flashprotect
-enable/disable`, which sends the `EC_CMD_FLASH_PROTECT` command toggling
-`EC_FLASH_PROTECT_RO_AT_BOOT` (changing `--name` to target different ECs).
+Software write protection can be toggled with `ectool --name=cros_fp
+flashprotect enable/disable`, which sends the `EC_CMD_FLASH_PROTECT` command
+toggling `EC_FLASH_PROTECT_RO_AT_BOOT` (changing `--name` to target different
+ECs).
 
-### Changing Software Write Protection with `ectool`
+### Changing Software Write Protection with ectool
 
-#### `ectool flashprotect`
+#### ectool flashprotect
 
 Print out current flash protection state.
 
@@ -163,103 +168,30 @@ Flags:
 *   `INCONSISTENT` - One or more banks of flash is not protected when it should
     be (should not happen during normal operation. Read only.).
 
-#### `ectool flashprotect enable`
+#### ectool flashprotect enable
 
 Set `ro_at_boot` flag. The next time the EC is reset it will protect the flash.
 Note that this requires a cold reset.
 
-#### `ectool flashprotect enable now`
+#### ectool flashprotect enable now
 
 Set `ro_at_boot` `ro_now all_now` flags and immediately protect the flash. Note
 that this will fail if hardware write protect is disabled.
 
-#### `ectool flashprotect disable`
+#### ectool flashprotect disable
 
 Clear `ro_at_boot` flag. This can only be cleared if the EC booted without
 hardware write protect enabled.
 
 Note that you must reset the EC to clear write protect after removing the screw.
-If the `ro_at_boot` flag set and the EC resets with the HW gpio disabled, the EC
-will leave the flash unprotected (`ro_now` and `all_now` flags are not set) but
-leave `ro_at_boot` flag set.
+If the `ro_at_boot` flag set, and the EC resets with the HW gpio disabled, the
+EC will leave the flash unprotected (`ro_now` and `all_now` flags are not set)
+but leave `ro_at_boot` flag set.
 
-### Changing Software Write Protection with `flashrom`
+## system_is_locked()
 
-#### View the current state of software write protection
-
-```bash
-(chroot) $ flashrom -p ec --wp-status
-```
-
-```
-WP: status: 0x00
-WP: status.srp0: 0
-WP: write protect is disabled.
-WP: write protect range: start=0x00000000, len=0x00000000
-```
-
-#### Enable software write protection
-
-This is immediate. The protection range indicates the RO region of the firmware.
-
-```bash
-(chroot) $ flashrom -p ec --wp-enable
-```
-
-```
-SUCCESS
-```
-
-```bash
-(chroot) $ flashrom -p ec --wp-status
-```
-
-```
-WP: status: 0x80
-WP: status.srp0: 1
-WP: write protect is enabled.
-WP: write protect range: start=0x00000000, len=0x0001f800
-```
-
-#### Disable software write protection
-
-Disable can only be done with hardware write protect disabled.
-
-```bash
-(chroot) $ flashrom -p ec --wp-disable
-```
-
-```
-FAILED: RO_AT_BOOT is not clear.
-FAILED
-```
-
-Reboot with [hardware write protection](#hw_wp) disabled. Note that protection
-is still enabled but the protection range is zero.
-
-```bash
-(chroot) $ flashrom -p ec --wp-status
-```
-
-```
-WP: status: 0x80
-WP: status.srp0: 1
-WP: write protect is enabled.
-WP: write protect range: start=0x00000000, len=0x00000000
-```
-
-```bash
-(chroot) $ flashrom -p ec --wp-disable
-```
-
-```
-SUCCESS
-```
-
-## `system_is_locked()`
-
-The [`system_is_locked()`] function in the EC code returns false if the HW
-write protect GPIO is disabled or the read-only firmware is not protected.
+The [`system_is_locked()`] function in the EC code returns false if the HW write
+protect GPIO is disabled, or the read-only firmware is not protected.
 
 One way this is used in the FPMCU source is to compile test or debug
 functionality into the firmware. Guarding the test functionality with
@@ -292,10 +224,11 @@ https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1222094
 The EC code command handlers (`command_flash_erase`, `command_flash_write`,
 etc.) return an error if `EC_FLASH_PROTECT_ALL_NOW` is set.
 
-["CCD open"]: https://chromium.googlesource.com/chromiumos/platform/ec/+/cr50_stab/docs/case_closed_debugging_cr50.md#Open-CCD
-[Cr50 console]: https://chromium.googlesource.com/chromiumos/platform/ec/+/cr50_stab/docs/case_closed_debugging_cr50.md#Consoles
-[Servo]: https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/refs/heads/master/README.md
-[`OverrideWP`]: https://chromium.googlesource.com/chromiumos/platform/ec/+/cr50_stab/docs/case_closed_debugging_cr50.md
+["CCD open"]: https://chromium.googlesource.com/chromiumos/platform/ec/+/cr50_stab/docs/case_closed_debugging_gsc.md#ccd-open
+[Cr50 console]: https://chromium.googlesource.com/chromiumos/platform/ec/+/cr50_stab/docs/case_closed_debugging_gsc.md#consoles
+[Servo]: https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/HEAD/README.md
+[`OverrideWP`]: https://chromium.googlesource.com/chromiumos/platform/ec/+/cr50_stab/docs/case_closed_debugging_gsc.md
 [`system_is_locked()`]: https://chromium.googlesource.com/chromiumos/platform/ec/+/aaba1d5efd51082d143ce2ac64e6caf9cb14d5e5/common/system.c#195
 [wp_screw]: https://www.chromium.org/chromium-os/firmware-porting-guide/firmware-ec-write-protection
 [write_protect_gpio]: https://chromium.googlesource.com/chromiumos/platform/ec/+/aaba1d5efd51082d143ce2ac64e6caf9cb14d5e5/include/ec_commands.h#1599
+[SuzyQ]: https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/HEAD/docs/ccd.md#SuzyQ-SuzyQable
diff --git a/docs/zephyr/README.md b/docs/zephyr/README.md
new file mode 100644
index 0000000000..84239d3b05
--- /dev/null
+++ b/docs/zephyr/README.md
@@ -0,0 +1,125 @@
+# Zephyr Embedded Controller (Zephyr EC)
+
+[TOC]
+
+## Introduction
+
+Starting roughly in July of 2021, Chromebooks switched from the original [Google
+Chrome EC](../../README.md) to an application based on the [Zephyr Project
+RTOS](https://zephyrproject.org/).
+
+The following terms are used to to describe these two implementations:
+
+* Original Chrome EC: ECOS, cros-ec, and legacy EC
+* Zephyr-based EC: Zephyr EC
+
+## Getting Started
+
+The [Zephyr build](zephyr_build.md) documentation details the usage of Google's
+meta build tool `zmake`, used to configure and build Zephyr EC binaries. Start
+here if you only need to build a Zephyr EC binary for an existing board.
+
+The [project configuration](project_config.md) documentation details the steps
+required to create a new Chromebook program (reference board) and for creating a
+new project variant.
+
+The [Zephyr New Board Checklist](zephyr_new_board_checklist.md) links to the
+documentation needed to configure individual EC features.
+
+The [Zephyr Troubleshooting](zephyr_troubleshooting.md) page lists few common
+errors and troubleshooting techniques used when working with Zephyr.
+
+## Source Code Organization
+
+Zephyr EC images rely on multiple Chromium repositories to build Zephyr EC images.
+
+* [`third_party/zephyr/main`] - Google's local mirror of the main Zephyr RTOS
+  source located on [Github](https://github.com/zephyrproject-rtos/zephyr).
+* [`third_party/zephyr/cmsis`] - Google's local mirror of the CMSIS module source
+  from [Github](https://github.com/zephyrproject-rtos/cmsis)
+* [`platform/ec`] - local repository containing code shared by the legacy EC and
+  the Zephyr EC
+
+The current Zephyr EC builds only the CMSIS module from the upstream Zephyr
+source, but may use other modules in the future.
+
+The diagram below shows the relationship of the upstream Zephyr repositories and
+the Chromium repositories.
+
+![Zephyr EC Structure](../images/zephyr_ec_structure.png)
+
+Google merges upstream Zephyr changes into the corresponding Chromium
+repository daily.
+
+### Shared Code
+
+The two EC implementations currently share a significant amount code found in
+the following directories (all paths relative to the Chrome EC base directory
+[`platform/ec`].)
+
+* `common/` - Upper-level code shared across boards and the EC implementations.
+  This includes the following features:
+  * Battery charging
+  * USB Power Delivery
+  * AP chipset power sequencing
+  * Motionsense (EC sensor support)
+  * Keyboard handling
+  * Verified boot support
+
+* `driver/` - Low-level drivers for on-board peripherals controlled by the EC.
+  This does not include any drivers for modules integrated directly into the EC
+  chipset (such as GPIO controllers, I2C, controllers, keyboard controller).
+  On-board peripheral drivers include:
+  * Charge controllers
+  * USB Power Delivery chips (TCPCs, PPCs, muxes, etc)
+  * Temperature sensors
+  * Motionsense sensors (accelerometers, gyrscopes, light sensors, etc)
+
+* `include/` - Header files for the `common/` and `driver/` code
+
+The following legacy EC directories are not used by the Zephyr EC application:
+* `baseboard/`
+* `board/`
+* `chip/`
+* `core/`
+
+### Zephyr Subdirectory
+
+Only the Zephyr EC application uses the following directory under the
+[`platform/ec`] repository:
+* `zephyr/`
+
+The following provides an overview of the sub-directories found under
+`zephyr/`.
+
+* `zephyr/app/` - The Zephyr EC application entry point. The Zephyr kernel
+  calls [`ec_app_main()`] routine after initializing all kernel services and
+  chip-level drivers,
+* `zephyr/boards/` - Contains the EC chip-level support. This directory and the
+  organization is required by the Zephyr build system.  This should not be
+  confused with the legacy EC `boards/` directory, as it does not contain any
+  Chromebook specific board code.
+* `zephyr/cmake/` - Configuration files for the CMake build system.
+* `zephyr/drivers/` - Drivers conforming to the Zephyr device model to
+  implement Chrome EC specific features. Google plans to eventually move these
+  drivers upstream.
+* `zephyr/dts/` - Devicetree description files for Google's Zephyr drivers that
+  are not yet available upstream.
+* `zephyr/emul/` - Emulator source code that has not yet been moved upstream.
+* `zephyr/include/` - Header files for files found in the `zephyr/`
+  sub-directory.
+* `zephyr/linker/` - Linker directive files used to construct the Zephyr EC
+  binaries.
+* `zephyr/program/` - Program-specific configurations for each program
+  supported by Zephyr.
+* `zephyr/shim/` - Source code that adapts the legacy EC APIs to the equivalent
+  Zephyr OS API.
+* `zephyr/subsys/` - Staging area for subsystem code that will be moved
+  upstream.
+* `zephyr/tests/` - Host based emulation tests.
+* `zephyr/zmake/` - Source code for the `zmake/` meta tool.
+
+[`third_party/zephyr/main`]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/zephyr/main
+[`third_party/zephyr/cmsis`]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/zephyr/cmsis
+[`platform/ec`]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec
+[`ec_app_main()`]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/app/ec/ec_app_main.c
diff --git a/docs/zephyr/out_of_chroot.md b/docs/zephyr/out_of_chroot.md
new file mode 100644
index 0000000000..22e1e2c342
--- /dev/null
+++ b/docs/zephyr/out_of_chroot.md
@@ -0,0 +1,76 @@
+# Building Zephyr Out-of-Chroot
+
+It is possible to build Zephyr outside of the Chromium OS chroot,
+albeit with additional steps.
+
+*** note
+**Note:** These steps are maintained on a best-effort basis, and may
+not be accurate depending on your Linux distribution and your system's
+specific environment.
+***
+
+[TOC]
+
+## Remove west, if installed [b/184654974](http://b/184654974)
+
+Zephyr's Cmake system will try to attach itself to the west tool if it finds it
+installed, conflicting with manual cmake invocations. If you installed west,
+you'll need to remove it:
+
+```bash
+python3 -m pip uninstall west
+```
+
+## Install zmake
+
+You can install zmake with pip:
+
+```bash
+cd ~/chromiumos/src/platform/ec
+python3 -m pip install -e zephyr/zmake --user
+```
+
+Ensure that `~/.local/bin` is in your `PATH`.
+
+You may also need to install these items:
+
+```bash
+sudo apt-get install cmake ninja-build python3-pyelftools gcc-multilib \
+    python3-pykwalify python3-colorama python3-testfixtures
+```
+
+## Install binman
+
+First build pylibfdt:
+
+```bash
+cd somewhere
+sudo apt-get install flex bison swig
+git clone git://git.kernel.org/pub/scm/utils/dtc/dtc.git
+cd dtc
+make
+make install PREFIX=~/.local         # You can install this where it suits
+```
+
+If you have a Chromium OS checkout then you should do:
+
+```bash
+cd ~/.local/bin
+ln -s ~/chromiumos/src/third_party/u-boot/files/tools/binman/binman
+```
+
+otherwise:
+
+```bash
+cd somewhere
+git clone https://source.denx.de/u-boot/u-boot.git
+cd ~/.local/bin
+ln -s somewhere/u-boot/tools/binman/binman
+```
+
+## Install Zephyr toolchain
+
+If using the Zephyr toolchain (`-t zephyr`), follow the [upstream
+documentation] to install the Zephyr build tools.
+
+[upstream documentation]: https://docs.zephyrproject.org/getting_started/index.html#install-a-toolchain
diff --git a/docs/zephyr/project_config.md b/docs/zephyr/project_config.md
new file mode 100644
index 0000000000..27b5a7414d
--- /dev/null
+++ b/docs/zephyr/project_config.md
@@ -0,0 +1,558 @@
+Project Configuration
+=====================
+
+[TOC]
+
+## Overview
+
+This document defines the organization of the program and project specific files
+needed by Zephyr EC projects.
+
+The goals of the project organization include:
+
+* Minimize code duplication, allowing multiple projects to share common
+  configuration options and devicetree nodes.
+* Define the set of files required by each project.
+* Define the best practices for devicetrees.
+
+
+### Glossary
+
+- **program**: The name of a Chromebook reference design. The **program**
+  includes all Chromebooks based on a single AP SoC, such as Intel MeteorLake,
+  Qualcomm 7c G3, or AMD Mendocino. The **program** corresponds to a single
+  board overlay in the ChromeOS SDK.  The term *baseboard* is often used as a
+  synonym for **program**.
+
+- **project**: The name of a specific Chromebook model or variant.  All
+  Chromebook **programs** contain at least one **project** which serves as the
+  reference design(s) for the **program**. The reference **project** may or may
+  not use the same name as the **program**. For example, the reference
+  **project** for the skyrim **program** is also called skyrim. The corsola
+  **program** included two reference **projects**, kingler and krabby. For the
+  legacy ECOS builds, *board* was used as a synonym for **project**.
+
+This document uses bold to highlight the terms **program** and **project** to
+reference the definitions above.
+
+## Directory Structure
+
+The [`zephyr/program`](../../zephyr/program) contains the **program** and
+**project** configuration files for all Zephyr based EC builds.
+
+### `zephyr/program` directory
+
+Each **program** has it's own subdirectory under `zephyr/program`.
+
+```
+zephyr/program/
+├── brya/
+├── corsola/
+├── herobrine/
+├── intelrvp/
+├── it8xxx2_evb/
+├── minimal/
+├── nissa/
+├── npcx_evb/
+├── rex/
+├── skyrim/
+└── trogdor/
+```
+
+> The [`zephyr/program/minimal`](../../zephyr/program/minimal/) **program**
+contains example EC projects that demonstrate how to build a Zephyr EC with the
+minimum feature set enabled. These projects require only a working UART on the
+target board.
+
+### `zephyr/program/`**`<program>`**`/` Directory Overview
+
+Each **program** subdirectory contains a subdirectory foreach each **project**,
+including a subdirectory for the reference **project**.
+
+The minimum configuration for a **program** named *skyrim* with just a single
+reference **project**, also named *skyrim*, is shown below.
+
+```
+zephyr/program/skyrim/
+├── include/
+│   └── <program headers>.h
+├── skyrim/
+│   ├── include/
+│   │   └── <project headers>.h
+│   ├── src/
+│   │   └── <project sources>.c
+│   ├── CMakeLists.txt
+│   ├── project.conf
+│   └── project.overlay
+├── src/
+│   └── <program sources>.c
+├── BUILD.py
+├── CMakeLists.txt
+├── Kconfig
+├── program.conf
+└── <devicetrees>.dtsi
+```
+
+#### `zephyr/program/`**`<program>`**`/` Directory Details
+
+Description of the files and directories found directly in the **<program>**
+level directory. Note that all paths are relative to the `zephyr/program/`
+directory.
+
+- **`<program>`**`/`: Top level directory for the **program**. [skyrim] is the
+  *program* name in the example above.
+- **`<program>`**`/include/`: Directory containing the header files common to
+  all **projects** in the **program**. Use of **program** level includes is
+  discouraged.  Instead, consider creating a generic driver that can be shared
+  across all **programs**.
+- **`<program>`**`/src/`: Directory containing the C source files common to all
+  **projects** in the **program**.
+- [**`<program>`**`/BUILD.py`](#build_py): Defines which **projects** can be
+  made from this directory.
+- [**`<program>`**`/CMakeLists.txt`](#cmakelists_txt): CMake file for the
+  **program**.
+- [**`<program>`**`/Kconfig`](#kconfig) - Defines new Kconfig options, used by
+  all **projects** in the **program**.
+- [**`<program>`**`/program.conf`](#program_conf) - Sets the default Kconfig
+  settings for all **projects**.
+- **`<program>`**`/<devictrees>.dtsi` - One or more devicetree files, organized
+  by the hardware module or EC feature.  See the [Devicetree Best
+  Practices](#devicetree-best-practices) section for additional information.
+- **`<program>`**`/`**`<project>`**`/`: Top level directory for the
+  **<project**>. Create a separate directory for each **project** defined by the
+  **program**.
+
+### `zephyr/program/`**`<program>`**`/`**`<project>`**`/` Directory Details
+
+Each **project** provides the following files. Note that all paths are relative
+to the `zephyr/program/`**`<program>`**`/` directory.
+
+- **`<project>`**`/include/`: The **project** may optionally provide a public
+  include directory, but this is discouraged. There are some exceptions where
+  the legacy EC code expects the project to define a public header, such as the
+  keyboard_customization.h file.
+- **`<project>`**`/src/`: Directory containing the C source files specific to
+  the **project**.
+- [**`<project>`**`/CMakeLists.txt`](#cmakelists_txt): CMake file for the
+  **project**.
+- [**`<project>`**`/project.conf`](#project_conf): Kconfig settings for the
+  **project**.
+- [**`<project>`**`/project.overlay`](#project_overlay): Main devicetree overlay
+  for the **project**.
+
+Creation of custom C source files specific to the **program** or **project** is
+discouaraged. You can usually project manage project specific settings with
+Kconfig and devicetree changes only.
+
+Note that **program** and **project** custom C files are still subject to the
+same unit test requirements. So all custom C files also require that you write
+tests.
+
+## Setting up a new **program**
+
+To set up a new EC **program**, create a new directory under
+[`zephyr/program`] with the organization shown below.
+Note that for this example, the new **program** is called "my_program", and the
+reference **project** is called "my_reference_project".
+
+> Tip - Copy one the **projects** defined by the [*minimal*] **program** to
+> start with the bare miminimum of features required to boot the Zephyr EC
+> appliation. Then follow the steps in the detailed in [Creating a New Zephyr EC
+> Project].
+
+```
+zephyr/program/my_program/
+├── my_reference_project/
+│   ├── CMakeLists.txt
+│   ├── project.conf
+│   └── project.overlay
+├── BUILD.py
+├── CMakeLists.txt
+├── Kconfig
+└── program.conf
+```
+
+An in-depth example of each file is given below:
+
+### BUILD.py
+
+`BUILD.py` is a Python-based config file for setting up your reference
+board and the associated variants.  The name `BUILD.py` is important
+and case-sensitive: `zmake` searches for files by this
+name.
+
+When `BUILD.py` is sourced, the following two globals are defined:
+
+- `here`: A `pathlib.Path` object containing the path to the directory
+  `BUILD.py` is located in.
+- `register_project`: A function which informs `zmake` of a new
+  project to be built.  Your `BUILD.py` file needs to call this
+  function one or more times.
+
+`register_project` takes the following keyword arguments:
+
+- `project_name` (required): The name of the project (typically the
+  Google codename).  This name must be unique amongst all projects
+  known to `zmake`, and `zmake` will error if you choose a conflicting
+  name.
+- `zephyr_board` (required): The name of the EC chip used. **Note:** the concept
+  of a Zephyr board does not align with the ChromeOS concept of a board. The
+  Zephyr build system requires a set of devicetree and Kconfig files under under
+  `boards/${ARCH}/${ZEPHYR_BOARD_NAME}`. For the Zephyr EC application, the EC
+  chip is mapped onto the Zephyr board organization. Supported `zephyr_boards`
+  include:
+   - `mec1727`: Microchip MEC1727, 416 KiB RAM, 512 KiB flash
+   - `npcx7`: Nuvoton NPCX7m7FC, 384 KiB, 512 KiB flash
+   - `npcx9m3f`: Nuvoton NPCX9m3F, 320 KiB RAM, 512 KiB flash
+   - `npcx9m7f`: Nuvoton NPCX9m7F, 384 KiB RAM, 1 MiB flash
+   - `it81202bx`: ITE IT81202, 60 KiB RAM, 1 MiB flash
+   - `it81302bx`: ITE IT81302, 60 KiB RAM, 1 MiB flash
+- `supported_toolchains` (required): A list of the toolchain names
+  supported by the build.  Valid values are:
+  - `coreboot-sdk`: only supported in the chroot
+  - `host`: used for unit and integration tests
+  - `llvm`: only supported in the chroot
+  - `zephyr`: only supported outside the chroot
+- `output_packer` (required): An output packer type which defines
+  which builds get generated, and how they get assembled together into
+  a binary.
+- `modules` (optional): A list of module names required by the
+  project.  The default, if left unspecified, is to use all modules
+  known by `zmake`.  Generally speaking, there is no harm to including
+  unnecessary modules as modules are typically guarded by Kconfig
+  options, so the only reason to set this is if your project needs to
+  build in a limited environment where not all modules are available.
+- `dts_overlays` (optional): A list of files which should be concatenated
+  together and applied as a Zephyr device-tree overlay. The recommended setting
+  is to select the **project** specific devicetree overlay file.
+
+    ``` python
+    dts_overlays=[here / project_name / "project.overlay"]
+    ```
+
+- `kconfig_files` (optional): A list of files that contain the Kconfig settings
+  for the **project**. The recommended setting is select the **program**
+  configuration file followed by the **project** configuration file.
+
+    ``` python
+    kconfig_files=[here / "program.conf", here / <project> / "project.conf",]
+    ```
+
+- `project_dir` (optional): The path to where `CMakeLists.txt` and
+  `Kconfig` can be found for the project, defaulting to `here`.
+
+Note that most projects will not want to call `register_project`
+directly, but instead one of the helper functions, which sets even
+more defaults for you:
+
+- `register_host_project`: Define a project which runs in the chroot
+  (not on hardware).
+- `register_raw_project`: Register a project which builds a single
+  `.bin` file, no RO+RW packing, no FMAP.
+- `register_binman_project`: Register a project which builds RO and RW
+  sections, packed together, and including FMAP.
+- `register_npcx_project`: Just like `register_binman_project`, but
+  expects a file generated named `zephyr.npcx.bin` for the RO section
+  with Nuvoton's header.
+
+You can find the implementation of these functions in
+[`zephyr/zmake/zmake/configlib.py`](../../zephyr/zmake/zmake/configlib.py).
+
+`BUILD.py` files are auto-formatted with `black`.  After editing a
+`BUILD.py` file, please run `black BUILD.py` on it.
+
+### CMakeLists.txt
+
+This file, should at minimum contain the following:
+
+``` cmake
+cmake_minimum_required(VERSION 3.20.1)
+
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(**project**)
+```
+
+If your **program** provides any C files, add them to your program CMake file
+using `zephyr_library_sources()`.
+
+``` cmake
+zephyr_library_sources("src/my_program_source.c")
+```
+
+For your **project** C files, create **`<project>/`**`CMakeLists.txt` and use
+`add_subdirectory()` to include the **project** CMake file.
+
+``` cmake
+add_subdirectory("my_reference_project")
+```
+
+Add the requires `zephyr_library_souces()` calls to the
+**`<project>/`**`CMakeLists.txt` file.
+
+If your **program** or **project** provides a public header, make the include
+directory visible to rest of the code using
+`cros_ec_library_include_directories()`.
+
+``` cmake
+cros_ec_library_include_directories("include")
+```
+
+### Kconfig
+
+If certain projects need project-specific C files or ifdefs, the only
+way to do so is to create a `Kconfig` file with the options schema you
+want, and use it to toggle the inclusion of certain files.
+
+The file must end with a single line that reads
+`source "Kconfig.zephyr"`.  Note that this file is optional, so it's
+recommended to only include it if you really need it.
+
+### program.conf
+
+`program.conf` has default Kconfig settings for all **projects** defined for the
+**program**. The format is `KEY=VALUE`, as typical for Kconfig.
+
+### project.conf
+
+`project.conf` has the Kconfig settings for a single **project**. The format is
+`KEY=VALUE`, as typical for Kconfig.
+
+Kconfig settings in `project.conf` take precedence over the Kconfig settings
+from `program.conf`.
+
+### project.overlay
+
+`project.overlay` is the main devicetree overlay for the **project**. The
+`project.overlay` contains the following components:
+- One or more `#include` statements to add devicetrees defined by the
+  **program** into project.
+- `/delete-node/` statements to remove specific devicetree nodes defined by the
+  **program** devicetrees.
+- New devicetree nodes for **project** specific settings that are not provided
+  by any **program** devicetrees.
+
+> Tip: After building your **project**, you can view the final devicetree in the
+file `build/zephyr/`**`<project>`**`/build-ro/zephyr/zephyr.dts`.
+
+## Setting up a new variant of an EC program
+
+**Unlike our legacy EC, there are no files or directories to copy and
+paste to setup a new variant in Zephyr code.**
+
+Simply add a `register_project`-based call to the existing `BUILD.py`
+for your reference board.
+
+Below is an example of how programs may wish to structure this in
+`BUILD.py`:
+
+``` python
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+def register_variant(project_name, chip="it8xx2", extra_dts_overlays=()):
+    return register_binman_project(
+        project_name=project_name,
+        zephyr_board=chip,
+        dts_overlays=[
+            here / "base_power_sequence.dts",
+            here / "i2c.dts",
+            **extra_dts_overlays,
+        ],
+    )
+
+
+# Reference board
+register_variant(
+    project_name="asurada",
+    extra_dts_overlays=[here / "reference_gpios.dts"],
+)
+
+# Variants
+register_variant(
+    project_name="hayato",
+    extra_dts_overlays=[here / "hayato_gpios.dts"],
+)
+```
+
+If a project is going to be a simple variant of another project (e.g.,
+project `bar` is exactly identical to project `foo` but has just a few
+device-tree/Kconfig changes), you can spin a new variant using the
+return value of the register functions:
+
+``` python
+foo = register_variant(project_name="foo")
+bar = foo.variant(
+    project_name="bar",
+    dts_overlays=[here / "bar_extras.dts"],
+)
+```
+
+With this simple variant syntax, lists (like Kconfig files and DTS
+overlays) are concatenated.  This means it's not possible to remove
+files during variant registration for this syntax, so it's only
+recommended for the simple case.
+
+## Devicetree Best Practices
+
+Below are the best practices for devicetree organization:
+
+* Split the devicetree across multiple files, organized by the functional block.
+  This organization applies to the shared **program** devicetrees only.
+  * FW_CONFIG
+  * GPIOs
+  * I2C
+  * Interrupts
+  * Keyboard
+  * LEDs
+  * Sensors
+  * Thermal (fans and temperature sensors)
+  * USB-C
+* When creating **program**, usually with a single reference project, add the
+  shared devicetree files in the program directory, separated by the functional
+  area noted above.
+* Each project creates a `project.overlay` file, and uses `#include` statements
+  to add shared devicetree files from the program directory. An example
+  project.overlay for the skyrim project is shown below.
+
+  ``` c
+  /* Copyright 2021 The ChromiumOS Authors
+   * Use of this source code is governed by a BSD-style license that can be
+   * found in the LICENSE file.
+   */
+
+  /* Skyrim program common DTS includes */
+  #include "../adc.dtsi"
+  #include "../fan.dtsi"
+  #include "../gpio.dtsi"
+  #include "../i2c.dtsi"
+  #include "../interrupts.dtsi"
+  #include "../keyboard.dtsi"
+  #include "../motionsense.dtsi"
+  #include "../usbc.dtsi"
+
+  /* Skyrim project node overrides */
+  /* ... */
+  ```
+
+### Managing **project** specific settings
+
+When the **project** needs to make changes to the shared devicetree files, there
+are two strategies:
+
+* For small changes, add the `/delete-node/` attribute to the `project.overlay`
+  file to remove the specific devices and devicetree nodes from the **project**
+  final devicetree.
+* For larger changes, remove the corresponding `#include` statements from the
+  `project.overlay` file. Then,dDirectly add any required nodes to the
+  `project.overlay` file.
+
+In both cases, the shared devicetree file in the **program** directory is not
+changed.
+
+### Small Devicetree Changes
+
+Examples of small devicetree changes include:
+* Change the I2C peripheral address of a device.
+* Changing USB-C related chips.
+* Changing motionsense properties, such as the odr and ec-rate properties.
+* Overriding a specific property of a node - for instance modifying the
+  `pinctrl-0` property to adjust the EC pins connected to a device driver.
+
+The example below demonstrates how to define a device in a **program**
+devicetree file and then override the setting in the `project.overlay` file.
+
+* The herobrine program defines the TCPC at I2C address `0xb` in the file
+`zephyr/program/herobrine/i2c.dtsi`. This I2C address is valid for the
+herobrine, evoker, and villager projects while the hoglin project needs to
+change the I2C address to `0x1b`.
+
+  ``` c
+  /* zephyr/program/herobrine/i2c.dtsi */
+
+  &i2c1_0 {
+    status = "okay";
+    /* ... */
+    tcpc_port0: ps8xxx@b {
+      compatible = "parade,ps8xxx";
+      reg = <0xb>;
+    };
+  };
+  ````
+* The hoglin `project.overlay` file deletes the TCPC node at address `0xb` and
+creates a new node at address `0x1b`.  The node name “tcpc_port0” is kept the
+same, so any references to this node name do not change, such as the USB-C port
+configuration.
+
+  ``` c
+  /* zephyr/program/herobrine/hoglin/project.overlay */
+
+  #include “../i2c.dtsi”
+
+  &i2c1_0 {
+    /delete-node/ ps8xxx@b;
+    tcpc_port0: ps8xxx@1b {
+      compatible = "parade,ps8xxx";
+      reg = <0x1b>;
+    };
+  };
+  ```
+
+While it is also possible to change a device’s I2C address by directly
+overriding the `reg` property, this should not be done. Changing only the `reg`
+property causes a mismatch between the node name, `ps8xxx@b`, and the actual
+device address, `0x1b`.
+
+Your `project.overlay` file can also directly override properties defined by the
+**program** devicetree files.
+
+* The skyrim **program** sets the I2C clock frequency for first I2C bus to fast
+  (400 KHz).
+  ``` c
+  /* zephyr/program/skyrim/i2c.dtsi */
+  &i2c0_0 {
+    status = "okay";
+    label = "I2C_TCPC0";
+    clock-frequency = <I2C_BITRATE_FAST>;
+    pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>;
+    pinctrl-names = "default";
+  };
+  ```
+* Override the I2C clock frequency to fast-plus (1 MHz) in the winterhold
+  `project.overlay`.
+  ``` c
+  /* zephyr/program/skyrim/winterhold/project.overlay */
+  #include "../i2c.dtsi"
+  &i2c0_0 {
+    clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+  };
+  ```
+### Large Devicetree Changes
+
+For large devicetree changes, the preference is to copy the relevant devicetree
+fragment into the `project.overlay` file and edit the fragment directly.
+
+Examples of large devicetree changes (or changes that don’t benefit from using
+the /delete-node/ attribute) include:
+* GPIOs - specifically the “named-gpios” node.  This integrates better with the
+  arbitrage and the pinmap utility, which auto-generates the EC GPIO settings
+  based on schematic data.
+* Changes to the motionsense sensor types.  Currently x86 architectures impose a
+  fixed ordering for the accelerometers and gryoscopes when accessed through the
+  LPC memory map (see the [`EC_MEMMAP_ACC_DATA`]). Deleting nodes changes the
+  order of the children under the motionsense-sense node and causes the test
+  [`hardware.SensorAccel`] to fail. Copy the motionsense nodes into the
+  project.overlay file and modify as required.
+* LED policies - generally each OEM/ODM defines unique LED policies for their
+  designs to establish differentiation for their brand. There is little value to
+  creating common LED policies for all **projects** in the **program**.
+* Batteries - batteries also are generally specific to the OEM/ODM. Define the
+  **project** batteries directly in the `project.overlay` file.
+
+
+[skyrim]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/HEAD:src/platform/ec/zephyr/program/skyrim
+[`zephyr/program`]: ../../zephyr/program/
+[*minimal*]: ../../zephyr/program/minimal/
+[Creating a New Zephyr EC Project]: ./zephyr_new_board_checklist.md
+[`EC_MEMMAP_ACC_DATA`]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/HEAD:src/platform/ec/include/ec_commands.h;l=181
+[`hardware.SensorAccel`]: https://crsrc.org/o/src/platform/tast-tests/src/chromiumos/tast/local/bundles/cros/hardware/sensor_accel.go;drc=8fbf2c53960bc8917a6a01fda5405cad7c17201e;l=30
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+++ b/docs/zephyr/zephyr_adc.md
@@ -0,0 +1,178 @@
+# Zephyr ADC Configuration
+
+[TOC]
+
+## Overview
+
+[ADC] is used to measure VBUS, temperature and other values depending on a board.
+
+## Kconfig Options
+
+The [`CONFIG_ADC`] option enables ADC support in the Zephyr EC application.
+Use the [`CONFIG_ADC_SHELL`] option to enable ADC related shell commands.
+
+Refer to [Kconfig.adc] for all sub-options related to ADC support that are
+specific to the Zephyr EC application.
+
+## Devicetree Nodes
+
+The EC chip disables all Analog-to-Digital Converters by default.  Enable ADC
+used on your design by changing the chip-specific ADC `status` property to
+`"okay"`.
+
+ADC properties:
+
+Property | Description | Settings
+:------- | :---------- | :-------
+`status` | Enables or disables the ADC module | `"okay"` <br> `"disabled"`
+`label` | Override the EC chip specific label. |`"ADC_<number>"`
+
+Either Nuvoton NPCX and ITE IT8xxx2 ECs use single a devicetree node `adc0` to
+describe ADC, but it supports multiple ADC channels.
+
+To enable the ADC set the `status` property to `"okay"`:
+```
+&adc0 {
+	status = "okay";
+};
+```
+
+### Mapping legacy ADC enums to ADC channels
+
+The legacy ADC API for the Chromium EC application uses an enumeration (e.g.
+`ADC_VBUS`, `ADC_AMON_BMON`) to specify the ADC channel to measure voltage.
+
+The `named-adc-channels` node creates the mapping between the legacy ADC channels
+enumeration and the Zephyr ADC driver's channel_id.
+```
+named-adc-channels {
+	compatible = "named-adc-channels";
+	vbus {
+		enum-name = "ADC_VBUS";
+		io-channels = <&adc0 1>;
+		/* Measure VBUS through a 1/10 voltage divider */
+		mul = <10>;
+	};
+};
+```
+
+Refer to the [named-adc.yaml] child-binding file for details about each property.
+
+## Board Specific Code
+
+None required.
+
+## Threads
+
+ADC support does not enable any threads.
+
+## Testing and Debugging
+
+Unfortunately, the are two `adc` console commands: a [Zephyr](#zephyr-cc) command
+and the one implemented in [CrosEC](#crosec-cc).
+Only one of them can be enabled with `CONFIG_ADC_SHELL` or
+`CONFIG_PLATFORM_EC_ADC_CMD` respectively.
+
+### Zephyr command {#zephyr-cc}
+
+The Zephyr `adc` includes the following subcommands:
+
+Subcommand | Description | Usage
+:--------- | :---------- | :----
+`acq_time` | Configure acquisition time | `adc <adc_label> acq_time <time> <unit>`
+`channel` | Configure ADC channel | `adc <adc_label> channel id <channel_id>`
+`gain` | Configure gain | `adc <adc_label> gain <gain>`
+`print` | Print current configuration | `adc <adc_label> print`
+`read` | Read adc value | `adc <adc_label> read <channel>`
+`reference` | Configure reference | `adc <adc_label> reference <reference>`
+`resolution` |Configure resolution for the `read` subcommand | `adc <adc_label> resolution <resolution>`
+
+Parameters summary:
+
+Parameter | Description
+:-------- | :----------
+`<adc_label>` | The ADC label property. By default, this is specified by the EC vendor in the respective devicetree include file unless you override the label in your devicetree.
+`<time>` | For the `acq_time` subcommand, specifies the time of acquisition.
+`<unit>` | For the `acq_time` subcommand, specifies the unit of the time of acquisition: `us`, `ns`, `ticks`.
+`<channel_id>` | For the `channel` subcommand, specifies the channel ID.
+`<gain>` | For the `gain` subcommand, specifies the gain of the ADC measurement, e.g. `GAIN_1_6`, `GAIN_2`, `GAIN_64`.
+`<channel>` | ADC channel.
+`<reference>` | For the `reference` subcommand, specifies the reference for the ADC measurement, e.g. `VDD_1`, `INTERNAL`.
+`<resolution>` | For the `resolution` subcommand, specifies the resolution for the ADC conversion for the `read` subcommand.
+
+E.g.
+```
+21-12-22 13:51:11.380 uart:~$ adc ADC_0 read 5
+adc ADC_0 read 5
+21-12-22 13:51:26.031 read: 1023
+```
+
+### CrosEC command {#crosec-cc}
+
+The CrosEC shell command `adc` displays current ADC measurements, e.g.
+```
+21-12-21 09:58:03.746 uart:~$ adc
+adc
+21-12-21 09:58:05.322   ADC_VBUS = 14850 mV
+21-12-21 09:58:05.325   ADC_AMON_BMON = 37111 mV
+21-12-21 09:58:05.325   ADC_PSYS = 8432000 mV
+```
+
+## Example
+
+The image below shows the ADC wiring for the Volteer reference board.
+
+![ADC Example]
+
+The Volteer board uses Nuvoton NPCX EC that has one Analog-to-Digital Converter
+`adc0`, so enable it:
+```
+&adc0 {
+	status = "okay";
+};
+```
+
+The board has four temperature sensors handled with ADC. Map legacy cros-ec enums
+to ADC channels with the following values:
+
+ADC Enumeration Name               | Volteer ADC channel
+:--------------------------------- | :------------------
+`ADC_TEMP_SENSOR_CHARGER`          | ADC0
+`ADC_TEMP_SENSOR_PP3300_REGULATOR` | ADC1
+`ADC_TEMP_SENSOR_DDR_SOC`          | ADC8
+`ADC_TEMP_SENSOR_FAN`              | ADC3
+
+The Volteer project establishes this map using the `named-adc-channels` as shown
+below:
+```
+named-adc-channels {
+	compatible = "named-adc-channels";
+
+	adc_charger: charger {
+		enum-name = "ADC_TEMP_SENSOR_CHARGER";
+		io-channels = <&adc0 0>;
+	};
+	adc_pp3300_regulator: pp3300_regulator {
+		enum-name = "ADC_TEMP_SENSOR_PP3300_REGULATOR";
+		io-channels = <&adc0 1>;
+	};
+	adc_ddr_soc: ddr_soc {
+		enum-name = "ADC_TEMP_SENSOR_DDR_SOC";
+		io-channels = <&adc0 8>;
+	};
+	adc_fan: fan {
+		enum-name = "ADC_TEMP_SENSOR_FAN";
+		io-channels = <&adc0 3>;
+	};
+};
+```
+
+[ADC]: ../ec_terms.md#adc
+[ADC Example]: ../images/volteer_adc.png
+[Kconfig.adc]: ../../zephyr/Kconfig.adc
+[`CONFIG_ADC`]:
+https://docs.zephyrproject.org/latest/kconfig.html#CONFIG_ADC
+[`CONFIG_ADC_SHELL`]:
+https://docs.zephyrproject.org/latest/kconfig.html#CONFIG_ADC_SHELL
+[named-adc.yaml]:
+../../zephyr/dts/bindings/adc/named-adc.yaml
diff --git a/docs/zephyr/zephyr_ap_ec_comm.md b/docs/zephyr/zephyr_ap_ec_comm.md
new file mode 100644
index 0000000000..77ec2330d0
--- /dev/null
+++ b/docs/zephyr/zephyr_ap_ec_comm.md
@@ -0,0 +1,215 @@
+# Application Processor to EC communication
+
+[TOC]
+
+## Overview
+
+Host commands allow communication between AP and EC.
+
+This communication is used to inform the ChromeOS running on AP about events
+like opening or closing lid, connecting or disconnecting charger,
+thermal status, keyboard events.
+
+## Kconfig options
+
+Kconfig Option                           | Default     | Documentation
+:--------------------------------------- | :---------: | :------------
+`CONFIG_PLATFORM_EC_HOSTCMD`             | y if AP     | [EC host commands]
+
+### Transport layer
+
+The `CONFIG_PLATFORM_EC_HOST_INTERFACE_TYPE` choice selects the interface type
+used to transport the AP/EC messages.
+
+Kconfig to select interface              | Default     | Documentation
+:--------------------------------------- | :---------: | :------------
+`CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI` | y if AP_X86 | [eSPI interface]
+`CONFIG_PLATFORM_EC_HOST_INTERFACE_HECI` | n           | [HECI interface]
+`CONFIG_PLATFORM_EC_HOST_INTERFACE_LPC`  | n           | [LPC interface]
+`CONFIG_PLATFORM_EC_HOST_INTERFACE_SHI`  | y if AP_ARM | [SHI interface]
+
+#### SHI
+
+[SHI] is acronym for SPI Host Interface. It's default interface for computers
+with ARM AP.
+It doesn't have any special Kconfigs.
+
+#### eSPI - Virtual wires
+
+[eSPI] is acronym for Enhanced Serial Peripheral Interface.
+It allows to define signals as virtual ones instead of using normal GPIOs.
+
+See the [Kconfig.espi] file for all sub-options related to the eSPI interface.
+
+#### HECI
+
+HECI is acronym for Host Embedded Controller Interface.
+It doesn't have any special Kconfigs.
+
+#### LPC
+
+[LPC] is acronym for Low Pin Count bus.
+It doesn't have any special Kconfigs.
+
+### Generic configuration
+
+The following options are generic and defines features available through
+host interface.
+
+Kconfig sub-options                          | Default     | Documentation
+:------------------------------------------- | :---------: | :------------
+`CONFIG_PLATFORM_EC_HOSTCMD_CONSOLE`         | y           | [Host command console]
+`CONFIG_PLATFORM_EC_HOSTCMD_CONSOLE_BUF_SIZE`| 4096        | [Host command console buffer size]
+`CONFIG_PLATFORM_EC_HOST_COMMAND_STATUS`     | y if PLATFORM_EC_HOST_INTERFACE_SHI | [Host command - status]
+
+### MKBP - Matrix Keyboard Protocol
+
+See the [MKBP documentation] for information about configuration of MKBP
+protocol.
+
+### Debug
+
+The `CONFIG_PLATFORM_EC_HOSTCMD_DEBUG_MODE_CHOICE` choice selects the verbosity
+level of messages on the EC console.
+
+Kconfig debug verbosity | Default | Documentation
+:---------------------- | :-----: | :------------
+`CONFIG_HCDEBUG_OFF`    | n       | [Debug off]
+`CONFIG_HCDEBUG_NORMAL` | y       | [Debug normal]
+`CONFIG_HCDEBUG_EVERY`  | n       | [Debug every]
+`CONFIG_HCDEBUG_PARAMS` | n       | [Debug params]
+
+## Device Tree nodes
+
+### eSPI
+
+Zephyr has built-in support for eSPI and EC takes advantage of this.
+Boards supported by Zephyr should have definitions of eSPI interfaces in their
+device trees.
+To select the eSPI interface to be used for sending the host commands it must
+be set as chosen node with name `cros-ec,espi`.
+The referenced node has to be enabled, which means that its `status` must
+be set as `okay`.
+
+```
+/ {
+	chosen {
+		cros-ec,espi = &espi0;
+	}
+}
+
+&espi0 {
+	status = "okay";
+};
+```
+
+### SHI
+
+The SoC specific Kconfig for SHI driver is automatically enabled based on
+selected host interface and SoC family. Each SoC driver has specific
+compatibility string which is used to get node with configuration from the
+device tree.
+For example, the nuvoton npcx chip uses compatibility string
+`nuvoton,npcx-shi`.
+
+The node's required properties are defined in yaml files: [SHI bindings]
+
+```
+/ {
+	shi0: shi@4000f000 {
+		compatible = "nuvoton,npcx-shi";
+		reg = <0x4000f000 0x120>;
+		interrupts = <18 1>;
+		clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 1>;
+		pinctrl-0 = <&altc_shi_sl>;
+		shi-cs-wui =<&wui_io53>;
+	};
+}
+```
+
+## Board Specific Code
+
+No board specific code is required.
+
+## Threads
+
+The host_command_task() thread processes all requests from the AP, regardless
+of the host interface type enabled.
+
+Enabling the `CONFIG_PLATFORM_EC_HOSTCMD` automatically selects
+`CONFIG_HAS_TASK_HOSTCMD` which is responsible for creating the thread.
+
+## Testing and Debugging
+
+Testing and debugging the host commands on DUT are described in
+[CrOS EC documentation]. It is recommended to run the stress test to check
+if communication is working properly with a huge amount of data sent.
+Running the stress test is described in the previously mentioned documentation,
+in the chapter [stress test].
+
+### From EC console
+
+If debug level is higher than `CONFIG_HCDEBUG_OFF`, then HC messages can
+be seen on EC console.
+
+If there's no output lines starting from HC, that may be due to hostcmd channel
+being masked.
+To check what channels are masked, execute `chan` command in EC console.
+```
+uart:~$ chan
+ # Mask     E Channel
+...
+ 7 00000080 * hostcmd
+```
+The asterisk next to channel name means that it is enabled. Otherwise, execute
+command `chan 128` to enable hostcmd channel while disabling others.
+
+If the hostcmd channel is disabled by default, it may be enabled by removing
+its name from `ec-console` node.
+
+```
+ec-console {
+	compatible = "ec-console";
+
+	disabled = "hostcmd";
+};
+```
+
+Removing the `hostcmd` and leaving the empty quotes will result in hostcmd
+messages visible on EC console since boot-up.
+
+## Examples
+
+[NPCX eSPI selection](https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/include/cros/nuvoton/npcx.dtsi?q=cros-ec,espi)
+
+[NPCX SHI definition](https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/include/cros/nuvoton/npcx.dtsi?q=shi)
+
+<!--
+Links to the documentation
+-->
+[SHI]:../ec_terms.md#shi
+[eSPI]:../ec_terms.md#espi
+[LPC]:../ec_terms.md#lpc
+[EC host commands]:https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig?q=%22menuconfig%20PLATFORM_EC_HOSTCMD%22
+[eSPI interface]:https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.host_interface?q=%22config%20PLATFORM_EC_HOST_INTERFACE_ESPI%22
+[HECI interface]:https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.host_interface?q=%22config%20PLATFORM_EC_HOST_INTERFACE_HECI%22
+[LPC interface]:https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.host_interface?q=%22config%20PLATFORM_EC_HOST_INTERFACE_LPC%22
+[SHI interface]:https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.host_interface?q=%22config%20PLATFORM_EC_HOST_INTERFACE_SHI%22
+
+[Kconfig.espi]:https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.espi
+
+[Host command console]:https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.console?q=%22menuconfig%20PLATFORM_EC_HOSTCMD_CONSOLE%22
+[Host command console buffer size]:https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.console?q=%22config%20PLATFORM_EC_HOSTCMD_CONSOLE_BUF_SIZE%22
+[Host command - status]:https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig?q=%22config%20PLATFORM_EC_HOST_COMMAND_STATUS%22
+
+[MKBP documentation]:zephyr_mkbp.md
+
+[Debug off]:https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig?q=%22config%20HCDEBUG_OFF%22
+[Debug normal]:https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig?q=%22config%20HCDEBUG_NORMAL%22
+[Debug every]:https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig?q=%22config%20HCDEBUG_EVERY%22
+[Debug params]:https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig?q=%22config%20HCDEBUG_PARAMS%22
+
+[SHI bindings]:https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/dts/bindings/cros_shi/
+
+[CrOS EC documentation]:../ap-ec-comm.md#ectool
+[stress test]:../ap-ec-comm.md#stress-test
diff --git a/docs/zephyr/zephyr_ap_power.md b/docs/zephyr/zephyr_ap_power.md
new file mode 100644
index 0000000000..0b95e375d6
--- /dev/null
+++ b/docs/zephyr/zephyr_ap_power.md
@@ -0,0 +1,58 @@
+# Zephyr EC AP Power Requirements
+
+[TOC]
+
+## Overview
+
+[AP] power configures the minimum amount of power needed to boot the Application
+Processor.
+
+## Kconfig Options
+
+The Kconfig option `CONFIG_PLATFORM_EC_BOOT_AP_POWER_REQUIREMENTS` enables checking power
+thresholds before booting the AP.  See the file [Kconfig.ap_power] for all Kconfig
+options related to this feature.
+
+## Devicetree Nodes
+
+None required.
+
+## Board Specific Code
+
+None required.
+
+## Threads
+
+AP_POWER support does not enable any threads.
+
+## Testing and Debugging
+
+Use the battfake  command to force the battery level, independent of the actual battery charge.
+To verify the AP power thresholds, force the battery level below the
+`CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON` setting and reboot the EC.
+The EC should prevent the AP from powering up.
+
+`battfake` usage: battfake <percent> (-1 = use real level)
+
+```
+battfake 2
+reboot
+/* Verify that AP does ot boot */
+battfak3 3
+/* Verify that AP boots */
+/* Restore normal operation */
+battfake -1
+```
+## Example
+
+For Herobrine, the minimum battery level to boot the AP without AC is 2 percent
+of the battery capacity and the minimum AC power to boot the AP with a battery
+is set to 10000 milliwats.
+
+```
+CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON=2
+CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON=10000
+```
+
+[AP]: ../ec_terms.md#ap
+[Kconfig.ap_power]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.ap_power
diff --git a/docs/zephyr/zephyr_battery.md b/docs/zephyr/zephyr_battery.md
new file mode 100644
index 0000000000..02ed5d424b
--- /dev/null
+++ b/docs/zephyr/zephyr_battery.md
@@ -0,0 +1,276 @@
+# Zephyr EC Battery
+
+[TOC]
+
+## Overview
+
+The battery is the rechargeable internal power source for the device.
+
+## Kconfig Options
+
+`CONFIG_PLATFORM_EC_BATTERY` enables battery support in the EC application.
+Refer to [Kconfig.battery] for all sub-options controlling battery behavior.
+
+## Devicetree Nodes
+
+### How to enable batteries on a board
+
+#### Enable battery feature configs
+
+Add battery configs to either the [`program.conf`] or [`project.conf`] file for
+your project.
+
+Example:
+
+```
+# Battery
+CONFIG_PLATFORM_EC_BATTERY=y
+CONFIG_PLATFORM_EC_BATTERY_SMART=y
+CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y
+CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y
+CONFIG_PLATFORM_EC_BATTERY_HW_PRESENT_CUSTOM=y
+CONFIG_PLATFORM_EC_BATTERY_REVIVE_DISCONNECT=y
+
+```
+
+#### Add devicetree nodes
+
+##### Add batteries devicetree node to the board overlay's root node
+
+Example:
+
+```
+  batteries {
+		default_battery: vendor_part {
+			compatible = "vendor,part";
+		};
+		vendor2_part2 {
+			compatible = "vendor2,part2";
+		};
+   };
+
+```
+
+Here `vendor_part` will be the default battery type. If this [*node label*] is
+present in the overlay, the [DEFAULT_BATTERY_TYPE] is set in the battery shim
+code with the labeled battery type. The `vendor` and `part` references must
+match an existing battery defined in [battery bindings directory].
+
+##### Add the battery present GPIO node as a child of `named-gpios`
+
+Example:
+
+```
+named-gpios {
+	compatible = "named-gpios";
+	...
+	...
+	ec_batt_pres_odl {
+		gpios = <{SOME GPIO} GPIO_INPUT>;
+	};
+	...
+	...
+};
+```
+
+See the [Zephyr gpios] doc for more information on the `named-gpios` node.
+
+##### Add a battery node as a child of `named-i2c-ports`
+
+Example:
+
+```
+named-i2c-ports {
+	compatible = "named-i2c-ports";
+	...
+	...
+	battery {
+		i2c-port = <{i2c_phandle}>;
+		remote-port = <{I2C_PASSTHRU-PORT-NUMBER}>;
+		enum-names = "I2C_PORT_BATTERY";
+	};
+	...
+	...
+}
+```
+
+Most battery fuel gauges support operation of only 100 KHz on the I2C bus, so
+ensure the clock-frequency for the bus is set appropriately.  See the
+[Zephyr I2C] doc for more information on the `named-i2c-ports` node.
+
+Refer to the [cros-ec-i2c-port-base.yaml] child-binding file for details about
+each property.
+
+[Example CL enabling batteries on a board]
+
+### How to create a new battery
+
++ Add `vendor,part` to [battery-smart enum]
++ Add `vendor,part.yaml` to the [battery bindings directory] beginning with:
+
+```
+description: "VENDOR PART"
+compatible: "vendor,part"
+
+include: battery-smart.yaml
+
+properties:
+   enum-name:
+      type: string
+      default: "vendor,part"
+
+```
+
+Refer to the vendor's datasheet to set all the fuel gauge and battery properties
+required in the `vendor,part.yaml` file.
+
+[Example CL adding a new battery]
+
+## Board Specific Code
+
+Enabling [CONFIG_PLATFORM_EC_BATTERY_PRESENT_CUSTOM] requires the board to provide a
+custom `battery_is_present()` function.
+
+## Threads
+
+Battery support alone does not enable any threads. However, the charger [task]
+requires the battery module for correct operation.
+
+## Testing and Debugging
+
+### EC Console Commands
+
+#### battery
+
+The `battery` [EC console command] may be invoked to check battery information
+on a flashed board.
+
+Example output of `uart:~$ battery`:
+
+```
+Status:    0x00e0 FULL DCHG INIT
+Param flags:00000002
+Temp:      0x0b69 = 292.1 K (19.0 C)
+V:         0x2ffc = 12284 mV
+V-desired: 0x0000 = 0 mV
+I:         0x0000 = 0 mA
+I-desired: 0x0000 = 0 mA
+Charging:  Not Allowed
+Charge:    96 %
+  Display: 98.7 %
+Manuf:     LGC
+Device:    AC17A8M
+Chem:      LION
+Serial:    0xd3b3
+V-design:  0x2d1e = 11550 mV
+Mode:      0x6001
+Abs charge:73 %
+Remaining: 3901 mAh
+Cap-full:  4074 mAh
+  Design:  5360 mAh
+Time-full: 0h:0
+  Empty:   0h:0
+full_factor:0.97
+shutdown_soc:4 %
+```
+
+#### pwr_avg
+
+The `pwr_avg` [EC console command] logs the battery charging rate by querying
+the battery fuel gauge driver.
+
+Example output of `uart:~$ pwr_avg`:
+
+Charging
+
+```
+mv = 13073
+ma = 439
+mw = 573
+```
+
+Discharging
+
+```
+mv = 12824
+ma = -146
+mw = -1872
+```
+
+Note: A fully charged board may report `ma = 0` and `mw = 0` average rates.
+
+#### chgstate
+
+The `chgstate` [EC console command] may be invoked to debug and manipulate machine
+charging state.
+
+Example output of `uart:~$ chgstate`:
+
+```
+state = charge
+ac = 1
+batt_is_charging = 1
+chg.*:
+	voltage = 13200mV
+	current = 0mA
+	input_current = 3000mA
+	status = 0xc010
+	option = 0x2830004
+	flags = 0x0
+batt.*:
+	temperature = 26C
+	state_of_charge = 100%
+	voltage = 13037mV
+	current = 0mA
+	desired_voltage = 0mV
+	desired_current = 0mA
+	flags = 0x2
+	remaining_capacity = 4436mAh
+	full_capacity = 4436mAh
+	is_present = YES
+requested_voltage = 0mV
+requested_current = 0mA
+chg_ctl_mode = 0
+manual_voltage = -1
+manual_current = -1
+user_current_limit = -1mA
+battery_seems_to_be_dead = 0
+battery_seems_to_be_disconnected = 0
+battery_was_removed = 0
+debug output = off
+```
+
+### AP Console Commands (ectool)
+
+#### chargestate
+
+The `chargestate` [ectool] command may be invoked to debug and manipulate
+machine charging state.
+
+Usage output of `uart: # ectool chargestate`:
+
+```
+Usage:
+  chargestate show                  - show current state
+  chargestate param NUM [VALUE]     - get/set param NUM
+  chargestate param help            - show known param NUMs
+```
+
+<!-- Reference Links -->
+
+[CONFIG_PLATFORM_EC_BATTERY_PRESENT_CUSTOM]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.battery?q=%22PLATFORM_EC_BATTERY_PRESENT_CUSTOM%22&ss=chromiumos
+[DEFAULT_BATTERY_TYPE]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/shim/src/battery.c?q=%22DEFAULT_BATTERY_TYPE%22&ss=chromiumos
+[EC console command]: https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/README.md#useful-ec-console-commands
+[Example CL adding a new battery]: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3312506/
+[Example CL enabling batteries on a board]: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3200068/
+[Kconfig.battery]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.battery
+[Zephyr I2C]: zephyr_i2c.md#Mapping-legacy-I2C-port-numbers-to-Zephyr-devicetree-nodes
+[Zephyr gpios]: zephyr_gpio.md#Devicetree-Nodes
+[battery bindings directory]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/dts/bindings/battery/
+[battery-smart enum]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/dts/bindings/battery/battery-smart.yaml?q=%22enum:%22&ss=chromiumos
+[cros-ec-i2c-port-base.yaml]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/dts/bindings/i2c/cros-ec-i2c-port-base.yaml
+[ectool]: ../ap-ec-comm.md
+[task]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/shim/include/shimmed_task_id.h
+[*node label*]: https://docs.zephyrproject.org/latest/build/dts/intro.html#dt-node-labels
+[`program.conf`]: ./project_config.md#program_conf
+[`project.conf`]: ./project_config.md#project_conf
diff --git a/docs/zephyr/zephyr_bc12.md b/docs/zephyr/zephyr_bc12.md
new file mode 100644
index 0000000000..a7f3431829
--- /dev/null
+++ b/docs/zephyr/zephyr_bc12.md
@@ -0,0 +1,103 @@
+# Zephyr BC12 Configuration
+
+[TOC]
+
+## Overview
+
+The Battery Charging Specification 1.2 describes mechanisms which allow drawing
+current in excess of the USB 2.0 specification. In the Zephyr EC, BC1.2 refers
+to devices known as USB Charger Detectors, which allow detecting when a BC1.2
+compliant charger is connected.
+
+## Kconfig Options
+
+The Kconfig option [`CONFIG_PLATFORM_EC_USB_CHARGER`] enables BC1.2 support in
+the EC application. This option is enabled by default when
+[`CONFIG_PLATFORM_EC_USBC`] is enabled. Refer to [Kconfig.usb_charger] for all
+sub-options related to BC1.2 support.
+
+## Devicetree Nodes
+
+The BC1.2 device node is added to the I2C bus node, and the  bc12  property on
+the USBC port node refers to the BC1.2 device.
+
+### Richtek RT1718S
+
+There are two nodes describing the Richtek RT1718, one for BC1.2
+[richtek,rt1718-bc12.yaml] and one for TCPC[richtek,rt1718s-tcpc.yaml]. The node
+for the TCPC contains information about I2C bus and address.
+
+### Richtek RT1739
+
+There are two nodes describing the Richtek RT1739, one for BC1.2
+[richtek,rt1739-bc12.yaml] and one for PPC [richtek,rt1739-ppc.yaml]. The node
+for the PCC contains information about I2C bus and address.
+
+### Richtek RT9490
+
+The Richtek RT9490 is described by [richtek,rt9490-bc12.yaml]. It allows
+defining which GPIO receives interrupts from the RT9490.
+
+### Pericom PI3USB9201
+
+The Pericom PI3USB9201 is described by [pericom,pi3usb9201.yaml]. It allows
+defining which GPIO receives interrupts from the PI3USB9201. The DTS node
+contains information about I2C bus and address.
+
+## Board Specific Code
+
+Enabling [CONFIG_PLATFORM_EC_USB_PD_5V_EN_CUSTOM] requires the board to provide
+a custom `battery_is_sourcing_vbus()` function.
+
+Some boards may implement the [board_vbus_sink_enable()] function.
+
+## Threads
+
+When enabled, a `usb_charger_task` will be created for each USBC port.
+The task's stack size can be set using CONFIG_TASK_USB_CHG_STACK_SIZE, but
+the priority is fixed. Additional information about the task priority can be
+found in [shimmed_task_id.h].
+
+## Example
+
+Example of defining a BC1.2 chip in DTS:
+
+```
+gpio-interrupts {
+    compatible = "cros-ec,gpio-interrupts"
+    int_usb_c0_bc12: usb_c0_bc12 {
+        irq-pin = <&gpio_usb_c0_bc12_int_odl>;
+        flags = <GPIO_INT_EDGE_FALLING>;
+        handler = "bc12_interrupt";
+    };
+};
+
+&i2c2_0 {
+	bc12_port0: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+		irq = <&int_usb_c0_bc12>;
+	};
+};
+
+port0@0 {
+    compatible = "named-usbc-port";
+    reg = <0>;
+    bc12 = <&bc12_port0>;
+};
+```
+
+`bc12_port0` is a BC1.2 device node ("pericom,pi3usb9201" is a compatible that
+is used by one of the BC1.2 devices). The `bc12_port0` is child of the `i2c2_0`
+which is an I2C controller device. Each "named-usbc-port" node can point one
+BC1.2 device node.
+
+[Kconfig.usb_charger]: https://source.chromium.org/chromium/chromiumos/platform/ec/+/HEAD:zephyr/Kconfig.usb_charger
+[richtek,rt1739-bc12.yaml]: https://source.chromium.org/chromium/chromiumos/platform/ec/+/HEAD:zephyr/dts/bindings/usbc/richtek,rt1739-bc12.yaml
+[richtek,rt1739-ppc.yaml]: https://source.chromium.org/chromium/chromiumos/platform/ec/+/HEAD:zephyr/dts/bindings/usbc/richtek,rt1739-ppc.yaml
+[richtek,rt9490-bc12.yaml]: https://source.chromium.org/chromium/chromiumos/platform/ec/+/HEAD:zephyr/dts/bindings/usbc/richtek,rt9490-bc12.yaml
+[pericom,pi3usb9201.yaml]: https://source.chromium.org/chromium/chromiumos/platform/ec/+/HEAD:zephyr/dts/bindings/usbc/pericom,pi3usb9201.yaml
+[shimmed_task_id.h]: https://source.chromium.org/chromium/chromiumos/platform/ec/+/HEAD:zephyr/shim/include/shimmed_task_id.h
+[CONFIG_PLATFORM_EC_USB_PD_5V_EN_CUSTOM]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.pd?q=%22PLATFORM_EC_USB_PD_5V_EN_CUSTOM%22
+[board_vbus_sink_enable()]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/include/usb_charge.h?q=%22board_vbus_sink_enable%22
diff --git a/docs/zephyr/zephyr_build.md b/docs/zephyr/zephyr_build.md
new file mode 100644
index 0000000000..a80fe06d98
--- /dev/null
+++ b/docs/zephyr/zephyr_build.md
@@ -0,0 +1,87 @@
+# Building Zephyr OS
+
+[TOC]
+
+Chromium OS EC uses the `zmake` tool to build Zephyr.
+
+This section describes how to build and use zmake.
+
+## Environment Setup
+
+Follow the [Chromium OS Developer Guide] to sync the source and get
+the chroot setup.
+
+It is also possible to build without a Chromium OS chroot, albeit with
+additional setup steps.  See [out-of-chroot building] if this
+interests you.
+
+### A Note on Syncing the Source
+
+The Legacy EC required only a single repository, and thus, it was common
+for developers to sync just the EC repository using `repo sync .`.
+
+Since the Zephyr build relies on multiple repositories, doing so will
+likely end you up in a broken state.  Please be sure to do a complete
+sync when updating the source.
+
+## Building
+
+To build the EC for a single project, run:
+
+``` shellsession
+(chroot) $ zmake build "${PROJECT}"
+```
+
+For example, to build the EC for `skyrim`, run:
+
+``` shellsession
+(chroot) $ zmake build skyrim
+```
+
+The output binary will then be located at `build/zephyr/skyrim/output/ec.bin`.
+
+Additional output files you may find useful:
+
+*   `build/zephyr/skyrim/output/zephyr.ro.elf` - read-only ELF for debugging
+*   `build/zephyr/skyrim/output/zephyr.rw.elf` - read-write ELF for debugging
+
+You might also find these files useful (using read-only as an example):
+
+*   `build/zephyr/skyrim/build-ro/zephyr/.config` - Kconfig options selected
+*   `build/zephyr/skyrim/build-ro/zephyr/include/generated/devicetree_unfixed.h` - the (large)
+    header file that zephyr uses to provide devicetree information to the C code
+*   `build/zephyr/skyrim/build-ro/zephyr/zephyr.dts` - devicetree that is used
+*   `build/zephyr/skyrim/build-ro/zephyr/zephyr.dts` - map of image
+
+For a complete list of `zmake` commands and options, see the
+[Zmake Documentation].
+
+Googlers may be interested in setting up [building with Goma](../goma.md)
+as well.
+
+### Building from Portage
+
+There is also a [an ebuild] for integration into the larger Chromium
+OS build system.
+
+To build using this flow, run:
+
+``` shellsession
+(chroot) $ emerge-${BOARD} chromeos-base/chromeos-zephyr
+```
+
+### Looking at the Kconfig
+
+It should be possible to do this with:
+
+```bash
+ninja -C /tmp/z/volteer/build-ro menuconfig
+```
+
+However at present this does not work [b/184662866](http://b/184662866).
+
+
+[Chromium OS Developer Guide]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/developer_guide.md
+[Zmake Documentation]: ../../zephyr/zmake/README.md
+[an ebuild]: https://chromium.googlesource.com/chromiumos/overlays/chromiumos-overlay/+/HEAD/chromeos-base/chromeos-zephyr/chromeos-zephyr-9999.ebuild
+[out-of-chroot building]: ./out_of_chroot.md
diff --git a/docs/zephyr/zephyr_cbi.md b/docs/zephyr/zephyr_cbi.md
new file mode 100644
index 0000000000..7d2f454865
--- /dev/null
+++ b/docs/zephyr/zephyr_cbi.md
@@ -0,0 +1,60 @@
+# Zephyr CrOS Board Information (CBI) Configuration
+
+[TOC]
+
+## Overview
+
+CrOS Board Info [`CBI`] is used to store static board information,
+such as BOARD_VERSION, SKU_ID and configuration information. With [`CBI`],
+the information is either hard coded as GPIO values or is stored in a
+writable [`EEPROM`] chip, so we can provision the correct SKU at RMA time.
+
+Kconfig has a CONFIG_PLATFORM_EC_CBI_STORAGE_TYPE choice that lets the
+user select GPIOs or an EEPROM as the source of [`CBI`] data.
+
+If your board uses GPIOs to hard code [`CBI`], then
+`CONFIG_PLATFORM_EC_CBI_GPIO` must be selected and the [`CBI`] data will be
+emulated and only the BOARD_VERSION and SKU_ID [`CBI`] fields are available.
+
+If your board includes an [`EEPROM`] to store [`CBI`], then
+`CONFIG_PLATFORM_EC_CBI_EEPROM` must be selected and configured.
+
+[`EEPROM`] [`CBI`] includes two additional pieces of firmware relevant
+configuration information that are programmed during manufacturing.
+
+1) The Firmware Configuration [`FW_CONFIG`] stores information
+specifically for the firmware, such as whether the device has a backlit
+keyboard.  One can view [`FW_CONFIG`] as the firmware characteristic of a
+SKU, so a SKU only maps to a single [`FW_CONFIG`], but different SKUs can
+map to the same [`FW_CONFIG`].
+2) The Second Source Factory Cache [`SSFC`] also stores information about
+the device for the firmware to read. The [`SSFC`] describes later decisions
+for a board to indicate alternate second sourced hardware stuffing which
+can be used by the EC to know which drivers to load.
+
+The difference between [`SSFC`] and [`FW_CONFIG`] is that [`SSFC`] doesn’t
+affect SKU. This prevents SKU explosion when a device has many second
+source components.
+
+If a Second Source Component is probeable, this should be stored in
+[`SSFC`], which avoids creating a new SKU.  If it is not probeable,
+it must be added to [`FW_CONFIG`].
+
+## Kconfig Options
+
+Refer to [`Kconfig.cbi`] for all the Kconfig options that control [`CBI`]
+behavior.
+
+## Testing and Debugging
+
+The [`ectool cbi`] command can be run from the kernel to get/set [`FW_CONFIG`]
+and [`SSFC`] values.  The console has a "cbi" command that can be used to do
+the same thing from the EC console.
+
+
+[`CBI`]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/design_docs/cros_board_info.md
+[`ectool cbi`]: ./zephyr_cbi.md#testing-and-debugging
+[`EEPROM`]: ./zephyr_eeprom.md
+[`FW_CONFIG`]: ./zephyr_fw_config.md
+[`SSFC`]: ./zephyr_ssfc.md
+[`Kconfig.cbi`]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.cbi
diff --git a/docs/zephyr/zephyr_charger.md b/docs/zephyr/zephyr_charger.md
new file mode 100644
index 0000000000..fa8dbdb178
--- /dev/null
+++ b/docs/zephyr/zephyr_charger.md
@@ -0,0 +1,295 @@
+# Zephyr EC Charger
+
+[TOC]
+
+## Overview
+
+The charger chip enables an external power supply to provide power to the
+board's components.
+
+## Kconfig Options
+
+`CONFIG_PLATFORM_EC_CHARGER` enables charging support in the EC
+application. Refer to [Kconfig.charger] for all sub-options controlling charging
+behavior.
+
+Note: At least one charger IC must be enabled.
+
+Note: The charger chip configuration serves a different role than the USB
+charging configuration found in [Kconfig.usb_charger].
+
+### Example of enabled configs
+
+Enable and disable charger configs in either the [`program.conf`] or
+[`project.conf`] file for your project.
+
+
+```
+# Charger
+CONFIG_PLATFORM_EC_CHARGER=y
+CONFIG_EC_CHARGER_ISL9237=y
+# Charger sub-options
+CONFIG_PLATFORM_EC_CHARGE_RAMP_HW=y
+CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y
+CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC_CHARGER=y
+CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON=2
+CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON=10000
+CONFIG_PLATFORM_EC_CHARGER_PROFILE_OVERRIDE=y
+CONFIG_PLATFORM_EC_CHARGER_PSYS=y
+CONFIG_PLATFORM_EC_CHARGER_PSYS_READ=y
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=20
+CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_ADC_AMON_BMON=y
+```
+
+## Devicetree Nodes
+### How to add a charger devicetree node
+
+#### Add charger node as child of `named-i2c-port`
+
+Example:
+
+```
+named-i2c-ports {
+   	compatible = "named-i2c-ports";
+   	charger {
+   		i2c-port = {ASSOCIATED PHANDLE};
+		/* Could be any name, but must correlate to "Board Specific Code" */
+		/* TODO(b/228237412): Update this comment once charger chg_chips[] is
+		 * created by a shim driver.
+		 */
+   		enum-names = "I2C_PORT_CHARGER";
+   	};
+};
+```
+
+See the I2C doc on [mapping legacy I2C port numbers to Zephyr devicetree nodes]
+for more information on configuring the `named-i2c-port` node.
+
+### How to create a new charger
+
+Add `vendor,part.yaml` to the [charger bindings directory]:
+
+Example Template:
+
+```
+description: Vendor Part Charger IC
+
+compatible: "vendor,part"
+
+include: i2c-device.yaml
+
+```
+See the [I2C doc](./zephyr_i2c.md) for more information on configuring I2C
+device bindings.
+
+## Board Specific Code
+
+### Define or append to the charger\_config\_t global array
+
+Example configuring an ISL923x charger chip:
+
+```c
+const struct charger_config_t chg_chips[] = {
+	{
+		/* .i2c_port must match corresponding named-i2c-port child */
+		.i2c_port = I2C_PORT_CHARGER,
+
+		/* these may vary by vendor and part */
+		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+		.drv = &isl923x_drv,
+	},
+};
+```
+
+<!-- TODO(b/228237412) - charger chips should be defined in code via DT
+macros. -->
+
+## Threads
+
+Enabling `CONFIG_PLATFORM_EC_CHARGER` also enables the [charger thread]
+described by [Kconfig.tasks].
+
+## Testing and Debugging a Flashed Board
+
+### EC Console Commands
+
+Use the `charger` [EC console command] to inspect the the chip's details and
+status.
+
+Example output of `uart:~$ charger`:
+
+```
+charger
+  Name:   ISL9241
+  Option: 10100000110000000000000100 (0x2830004)
+  Man id: 0x0049
+  Dev id: 0x000e
+  V_batt: 13152 (  64 - 18304,   8)
+  I_batt:  2364 (   4 -  6140,   4)
+  I_in:    3000 (   4 -  6140,   4)
+  I_dptf: disabled
+```
+
+#### taskinfo
+
+Use the `taskinfo` [EC console command] to inspect if the charging task was
+enabled.
+
+Example output of `uart:~$ taskinfo`:
+
+```
+ Task Ready Name         Events      Time (s)  StkUsed
+ 0 R << idle >>       00000000 2055.869084   80/672
+ 1   HOOKS            00000000    5.215864  560/800
+ 2   CHG_RAMP         00000000    0.108705  424/672
+ 3   USB_CHG_P0       00000000    0.002139  368/672
+ 4   USB_CHG_P1       00000000    0.002132  368/672
+ 5   CHARGER          00000000   17.692626  488/928
+ 6 R MOTIONSENSE      80000002   50.203370  632/928
+ 7   KEYPROTO         00000000    0.008531  312/672
+ 8   CHIPSET          00000000    0.026394  528/800
+ 9   HOSTCMD          00000000    1.483327  600/800
+10 R CONSOLE          00000000    0.101999  448/928
+11   POWERBTN         00000000    0.001535  464/800
+12   KEYSCAN          00000000    1.144058  328/672
+13   PD_C0            00000000  176.510938  632/928
+14   PD_C1            00000000   73.909944  624/928
+15   PD_INT_C0        00000000    0.003969  472/672
+16   PD_INT_C1        00000000    0.025180  512/672
+```
+
+#### pwr_avg
+
+Use the [pwr_avg] [EC console command] to see battery charging rates.
+
+#### chgstate
+
+Use the [chgstate] [EC console command] to debug and manipulate machine charging
+state.
+
+#### chgoverride
+
+Use the `chgoverride` [EC console command] to disable or force charging from a
+specific charging enabled port.
+See [Kconfig.charger] for configuring multiple charging ports.
+
+Use the [chgsup] command to view changes.
+
+#### chglim
+
+Use the `chglim` [EC console command] to set a max charger IC current and
+voltage charging limit.
+
+Use the [chgstate] command to view changes.
+
+#### chgsup
+
+Use the `chgsup` [EC console command] to get the status of the port that is the
+chosen charge supplier.
+
+Example output of `uart:~$ chgsup`:
+
+```
+port=1, type=0, cur=3000mA, vtg=15000mV, lsm=1
+```
+
+### AP Console Commands (ectool)
+
+#### chargecurrentlimit
+
+Use the `chargecurrentlimit` [ectool] command to set the charge limit in
+milliamps.
+
+Usage output of `uart: # ectool chargecurrentlimit`:
+
+```
+Usage: chargecurrentlimit <max_current_mA>
+```
+
+Use the [chargestate] [ectool] command to view changes.
+
+#### chargecontrol
+
+Use the `chargecontrol` [ectool] command to set whether the board is idle,
+discharging, or resume normal operation.
+
+Usage output of `uart: # ectool chargecontrol`:
+
+```
+Usage: chargecontrol <normal | idle | discharge>
+```
+
+Use the [chargestate] [ectool] command to view changes.
+
+#### chargeoverride
+
+Use the `chargeoverride` [ectool] command to disable or force charging from a
+specific charging enabled port.
+See [Kconfig.charger] for configuring multiple charging ports.
+
+Usage output of `uart: # ectool chargeoverride`:
+
+```
+Usage: chargeoverride <port# | dontcharge | off>
+```
+
+Use the `power_supply_info` [developer console] command to view which port is
+acting as the charge supplier.
+
+Example:
+
+Usage output of `uart: # power_supply_info`:
+
+```
+power_supply_info
+Device: Line Power
+  path:                    /sys/class/power_supply/CROS_USBPD_CHARGER1
+  online:                  yes
+  type:                    USB
+  enum type:               USB
+  voltage (V):             4.512
+  current (A):             Not available
+  max voltage (V):         5
+  max current (A):         3
+  active source:           CROS_USBPD_CHARGER1 /* Port 1 is the charge supplier*/
+  available sources:       CROS_USBPD_CHARGER0* [0/0], CROS_USBPD_CHARGER1* [0/0]
+  supports dual-role:      yes
+Device: Battery
+  path:                    /sys/class/power_supply/BAT0
+  vendor:                  AS3GXAE
+  model name:              C536-49
+  state:                   Fully charged
+  voltage (V):             13
+  energy (Wh):             52.771
+  energy rate (W):         0
+  current (A):             0
+  charge (Ah):             4.442
+  full charge (Ah):        4.442
+  full charge design (Ah): 4.8
+  percentage:              100
+  display percentage:      100
+  technology:              Li-ion
+
+```
+
+#### chargestate
+
+The [chargestate] command may also be invoked.
+
+<!-- Reference Links -->
+[EC console command]: https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/README.md#useful-ec-console-commands
+[Kconfig.charger]: https://crsrc.org/o/src/platform/ec/zephyr/Kconfig.charger
+[Kconfig.tasks]: https://crsrc.org/o/src/platform/ec/zephyr/Kconfig.tasks?q=%22config%20HAS_TASK_CHARGER%22&ss=chromiumos
+[Kconfig.usb_charger]: https://crsrc.org/o/src/platform/ec/zephyr/Kconfig.usb_charger?q=%22config%20PLATFORM_EC_USB_CHARGER%22&ss=chromiumos
+[charger bindings directory]: https://crsrc.org/o/src/platform/ec/zephyr/dts/bindings/charger/
+[charger thread]: https://crsrc.org/o/src/platform/ec/common/charge_state.c?q=%22void%20charger_task%22&ss=chromiumos
+[chargestate]: ./zephyr_battery.md#chargestate
+[chgstate]: ./zephyr_battery.md#chgstate
+[chgsup]: #chgsup
+[developer console]: https://chromium.googlesource.com/chromiumos/platform2/+/HEAD/crosh#crosh-the-chromium-os-shell
+[ectool]: ../docs/ap-ec-comm.md
+[mapping legacy I2C port numbers to Zephyr devicetree nodes]: ./zephyr_i2c.md#mapping-legacy-i2c-port-numbers-to-zephyr-devicetree-nodes
+[pwr_avg]: ./zephyr_battery.md#pwr_avg
+[`program.conf`]: ./project_config.md#program_conf
+[`project.conf`]: ./project_config.md#project_conf
diff --git a/docs/zephyr/zephyr_eeprom.md b/docs/zephyr/zephyr_eeprom.md
new file mode 100644
index 0000000000..9bc2f8b092
--- /dev/null
+++ b/docs/zephyr/zephyr_eeprom.md
@@ -0,0 +1,89 @@
+# Zephyr CBI EEPROM Configuration.
+
+[TOC]
+
+## Overview
+
+Zephyr `EEPROM` [`CBI Configuration`]
+
+Note: Since the `EEPROM` uses an [`I2C`] interface that must be
+configured and working before enabling [`CBI`].
+
+## Kconfig Options
+
+The CrOS Board Information [`CBI`] feature is enabled with the
+CONFIG_PLATFORM_EC_CBI_EEPROM Kconfig, as defined in the [`CBI Configuration`].
+
+The specific `EEPROM` also needs to be enabled. For example, the Atmel AT24
+would need the following enabled.
+
+Kconfig Option                  | Enabled state | Documentation
+:------------------------------ | :-----------: | :------------
+`CONFIG_EEPROM`                 | y             | Enabled EEPROM
+`CONFIG_EEPROM_AT24`            | y             | Enable Atmel AT24
+
+Device tree is used to define and specify the `EEPROM` device.
+
+## Devicetree Nodes
+
+The `EEPROM` device tree nodes are defined for each type of device
+YAML bindings that are specific to that particular `EEPROM`.  The standard
+fashion of defining that `EEPROM` is used with one exception, the `EEPROM`
+node must have the nodelabel `cbi_eeprom`.  Including the `cbi_eeprom`
+nodelabel in the Device Tree will include the cbi_eeprom driver.
+
+An example definition of the Atmel AT24 is:
+```
+    &i2c0_0 {
+        label = "I2C_EEPROM";
+        clock-frequency = <I2C_BITRATE_FAST>;
+
+        cbi_eeprom: eeprom@50 {
+            compatible = "atmel,at24";
+            reg = <0x50>;
+            size = <2048>;
+            pagesize = <16>;
+            address-width = <8>;
+            timeout = <5>;
+        };
+    };
+```
+
+Configuring the [`CBI`] Write Protect Signal is also necessary.
+The current requirement is that you define an alias node called
+"gpio-cbi-wp" that points to the GPIO used as the write protect.
+
+Note that the "wp-gpios" property should not be used.
+"wp-gpios" - Specifies the GPIO output signal from the SoC connected
+to the `EEPROM` write protect pin.  Zephyr uses this to automatically
+control write protection during write and erase operations.
+On Chromebooks, the write protect signal is controlled by the Google
+Security Chip.  gpio-cbi-wb specifies the GPIO input signal to the SoC,
+used by the EC application to monitor the write protect state.
+
+An example of configuring this is:
+```
+/ {
+    aliases {
+        gpio-cbi-wp = &gpio_cbi_wp;
+    };
+    named-gpios {
+        gpio_cbi_wp: ec_cbi_wp {
+            gpios = <&gpio8 1 GPIO_OUT_LOW>;
+        };
+    };
+};
+```
+
+## Threads
+
+No threads used in this feature.
+
+## Testing and Debugging
+
+Also the [`I2C bus scan`] can be used to verify the EEPROM device can be accessed.
+
+
+[`CBI`]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/design_docs/cros_board_info.md
+[`CBI Configuration`]: ./zephyr_cbi.md
+[`I2C bus scan`]: ./zephyr_i2c.md#Shell-Command_i2c
diff --git a/docs/zephyr/zephyr_fw_config.md b/docs/zephyr/zephyr_fw_config.md
new file mode 100644
index 0000000000..94c22a031b
--- /dev/null
+++ b/docs/zephyr/zephyr_fw_config.md
@@ -0,0 +1,117 @@
+# Zephyr CBI FW_CONFIG Configuration and Use.
+
+[TOC]
+
+## Overview
+
+Zephyr [`FW_CONFIG`] [`CBI Configuration`]
+
+## Kconfig Options
+
+The CrOS Board Information [`CBI`] feature is enabled with the
+CONFIG_PLATFORM_EC_CBI_EEPROM Kconfig, as defined in the [`CBI Configuration`].
+
+One of the [`CBI`] elements is the [`FW_CONFIG`] field.
+This config is used at run time to select different hardware options or behaviours, and
+is defined generally on a board by board basis.
+
+The [`FW_CONFIG`] block is limited to 32 bits. The 32 bits are divided into individual
+fields of varying sizes. Each field has defined values that may be set to control
+the behaviour according to the definition for that board.
+
+Device tree is used to define and specify the field sizes and values.
+
+## Devicetree Nodes
+
+The [`FW_CONFIG`] device tree nodes are defined via the [`cros-ec-cbi-fw-config`] and
+[`cros-ec-cbi-fw-config-value`]
+YAML bindings.
+
+The [`cros-ec-cbi-fw-config`] bindings define the name, starting bit and size of each field.
+The [`cros-ec-cbi-fw-config-value`] bindings allow names/values to be defined for each
+value that may be stored in the field.
+One of the values may be designated as the default, which is used if
+the [`CBI`] data cannot be accessed.
+
+Spare [`CBI`] [`FW_CONFIG`] fields are always initialised as zeros, so that
+future fields will have a guaranteed value, so typically a zero
+value is used as a default, indicating the default field.
+
+An example definition is:
+```
+puff-fw-config {
+   compatible = "cbi-fw-config";
+   bj-power {
+       enum-name = "FW_BJ_POWER";
+       start = <0>;
+       size = <4>;
+       p65w {
+           enum-name = "BJ_POWER_P65";
+           compatible = "cbi-fw-config-value";
+           value = <0>;
+       };
+       p90w {
+           enum-name = "BJ_POWER_P90";
+           compatible = "cbi-fw-config-value";
+           value = <1>;
+           default;
+       };
+    };
+    no-usb-port-4 {
+        enum-name = "FW_USB_PORT_4";
+        start = <4>;
+        size = <1>;
+        port-4-present {
+            enum-name = "USB_PORT_4_PRESENT";
+            compatible = "cbi-fw-config-value";
+            value = <1>;
+        };
+    };
+};
+```
+
+The device tree will generate a series of
+enum values and field names that can used
+to read the values (via the [`CBI`] driver).
+
+## Board Specific Code
+
+To access the generated enums and names, the [`CBI`] driver
+should be used to access the [`CBI`] API to retrieve selected fields,
+and then the defined enums used e.g:
+
+```
+#include "cros_cbi.h"
+
+    int get_power_watts()
+    {
+        int ret;
+        uint32_t val;
+
+        ret = cros_cbi_get_fw_config(FW_BJ_POWER, &val);
+        if (ret < 0)
+            return -1;
+
+        if (val == BJ_POWER_P65)
+            return 65;
+        if (val == BJ_POWER_P90)
+            return 90;
+        return -1;
+    }
+```
+
+## Threads
+
+No threads used in this feature.
+
+## Testing and Debugging
+
+The [`ectool cbi`] command can be used to read and set the [`FW_CONFIG`].
+
+
+[`CBI`]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/design_docs/cros_board_info.md
+[`CBI Configuration`]: ./zephyr_cbi.md
+[`cros-ec-cbi-fw-config`]: ../../zephyr/dts/bindings/cbi/cros-ec-cbi-fw-config.yaml
+[`cros-ec-cbi-fw-config-value`]: ../../zephyr/dts/bindings/cbi/cros-ec-cbi-fw-config-value.yaml
+[`ectool cbi`]: ./zephyr_cbi.md#testing-and-debugging
+[`FW_CONFIG`]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/design_docs/firmware_config.md
diff --git a/docs/zephyr/zephyr_gpio.md b/docs/zephyr/zephyr_gpio.md
new file mode 100644
index 0000000000..5204e6107f
--- /dev/null
+++ b/docs/zephyr/zephyr_gpio.md
@@ -0,0 +1,469 @@
+# Zephyr EC GPIO Configuration
+
+[TOC]
+
+## Overview
+
+[GPIO] provide support for general purpose I/Os on the platform, including
+initialization, setting and interrupt management.
+
+## Kconfig Options
+
+Kconfig Option                          | Default | Documentation
+:-------------------------------------- | :-----: | :------------
+`CONFIG_GPIO`                           | n       | [Include GPIO drivers in system config]
+`CONFIG_PLATFORM_EC_GPIO_INIT_PRIORITY` | 51      | [GPIO Init Priority]
+
+*No sub-options available.*
+
+## Devicetree Nodes
+
+Configure the GPIO module by declaring all GPIOs as child nodes in
+the devicetree node with
+`compatible` property `named-gpios`. The GPIO module automatically initializes
+all GPIOs from this node (unless the `no-auto-init` property is present).
+Legacy C source code accesses GPIOs using the specified
+`enum-name` property as an enum name of the GPIO.
+Zephyr based code uses the [*node label*], an alias, or other node reference
+to identify the GPIO.
+
+Named GPIO properties:
+
+Property | Description | Settings
+:------- | :---------- | :-------
+`gpios` | GPIO `phandle-array`, identifies the port (X), pin number (Y) and flags. | `<&gpioX Y flags>`
+`enum-name` | An optional name used to define an enum to refer to the GPIO in legacy code. | `GPIO_<NAME>`
+`no-auto-init` | If present, the GPIO **will not** be initialized at start-up. | boolean, default false
+
+The use of `no-auto-init` allows GPIOs to be skipped at start-up
+initialization time, and selectively enabled by code at some later time.
+
+The file [gpio-enum-name.yaml] defines the list of valid `enum-name` values.
+
+In the GPIO declaration use the lowercase net name from the schematic as the
+*node name*, and the same net name prefixed with `gpio_` as [*node label*].
+For example:
+
+```
+named-gpios {
+        compatible = "named-gpios";
+...
+        gpio_en_pp5000_fan: en_pp5000_fan {
+                gpios = <&gpio6 1 GPIO_OUT_LOW>;
+                enum-name = "GPIO_EN_PP5000_FAN";
+        };
+        gpio_power_on_odl: power_on {
+                gpios = <&gpio4 4 GPIO_INPUT_PULL_UP>;
+        };
+};
+...
+aliases {
+	gpio-power = &gpio_power_on_odl;
+};
+
+```
+
+The `flags` cell of the `gpios` property defines the GPIO signal properties,
+valid options are listed in [dt-bindings/gpio_defines.h], which is normally
+included from the main board DTS file.
+
+For platform specific features, other flags may be available in the Zephyr
+[dt-bindings/gpio/gpio.h] file, such as `GPIO_VOLTAGE_1P8`.
+
+### Alternate functions
+
+All pins are configured as GPIO by default, so normally pinctrl configuration
+for GPIO pins is not required. Note that on NPCX ECs some pins default to a
+non-GPIO function after reset. These are explicitly set to GPIO during
+initialization, based on the `def-io-conf-list` node in [npcx9.dtsi], so they
+do not need to be set to GPIO usage, but they need an explicit `pinctrl-x`
+entry to be set back to the specific function.
+
+### Legacy enum-name usage
+
+Only GPIOs that require referencing from legacy common code should have
+an `enum-name` property.
+The legacy API (e.g `gpio_get_level(enum gpio_signal)`) requires a known
+name for the enum, which is set using the `enum-name` property.
+
+Do *not* use `enum gpio_signal` or the enum signal names in any Zephyr
+based code - instead, use the standard Zephyr GPIO API.
+
+### Zephyr GPIO API usage
+
+GPIOs references that are not in legacy common code should use the
+[standard Zephyr API](https://docs.zephyrproject.org/latest/reference/peripherals/gpio.html)
+to access the GPIO.
+
+GPIOs are referenced in the `named-gpios` child nodes using the
+[*node label*] (if one exists), an alias to a [*node label*], or
+indirectly as a node reference via as a `phandle` in another node.
+
+To facilitate this, all GPIO child nodes in `named-gpios`
+have preinitialised `const struct gpio_dt_spec *` pointers
+created that may be used directly in the Zephyr GPIO API calls.
+These pointers are accessible via the following macros:
+
+Macro | Argument | Description
+:------- | :---------- | :-------
+`GPIO_DT_FROM_NODELABEL` | nodelabel | Uses a [*node label*] to reference the GPIO node.
+`GPIO_DT_FROM_NODE` | node | Uses a node id (referenced as a `phandle` in another node).
+`GPIO_DT_FROM_ALIAS` | alias | Uses an alias to a label on the GPIO node.
+
+The legacy enum can also be used to retrieve the `gpio_dt_spec` for
+a GPIO via the function `gpio_get_dt_spec()` (though this is a
+runtime lookup). E.g:
+
+```
+    fan_status = gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pp5000_fan));
+    power_status = gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_power));
+...
+    /*
+     * Legacy code gave us an enum gpio_signal, get a Zephyr reference
+     * for that GPIO.
+     */
+    const struct gpio_dt_spec *my_gpio = gpio_get_dt_spec(my_signal);
+    my_status = gpio_pin_get_dt(my_gpio);
+```
+
+The `GPIO_DT_FROM_NODE` macro is used when a `named-gpio` is referenced
+from another node via a `phandle` property.
+
+```
+    gpio-interrupts {
+	compatible = "cros-ec,gpio-interrupts";
+
+	int_power_button: power_button {
+	    irq-pin = <&gpio_gsc_ec_pwr_btn_odl>;
+	    ...
+	};
+...
+    /*
+     * Get the GPIO associated with interrupt.
+     */
+    const struct gpio_dt_spec *pwr_btn =
+	GPIO_DT_FROM_NODE(DT_PHANDLE(DT_NODELABEL(int_power_button), irq_pin));
+    pwr_on = gpio_pin_get_dt(pwr_btn);
+
+```
+
+When referencing a named-gpio child node from another DTS node,
+it is important not to use `gpio` or `gpios` as the trailing suffix
+of the name property. Any referencing property with a name
+ending in `gpio` or `gpios` is
+[treated specially in devicetree](https://docs.zephyrproject.org/latest/guides/dts/bindings.html#specifier-cell-names-cells),
+and assumes the target node is a GPIO node (i.e a node
+with cell specifiers of `pin` and `flags`).
+
+The goal is to migrate away from using the legacy API
+(using the Zephyr API instead), and deprecate the use of the `enum-name`
+property to generate the GPIO signal enum.
+
+### Run-time configuration of GPIOs
+
+It is common to have different hardware configurations supported
+within the same EC image by using `FW_CONFIG` configuration bits
+to selectively choose or enable/disable hardware options.
+Previously, GPIOs were aliased via a #define in `gpio_map.h` to a common
+GPIO in `named-gpios`, allowing different names to be used for the same GPIO.
+At run-time the GPIO would be configured according to the usage required.
+
+However this scheme relies on the use of the legacy
+`enum gpio_signal` to identify the GPIO.
+Given that code is being migrated to the Zephyr API, it is preferred that
+a separate `named-gpio` node be allocated to each use of the GPIO in question,
+and use the `no-auto-init` property to allow the initialisation only
+when code requires it.
+
+So if a board had 2 GPIOs with different use depending on a board type, the
+configuration would appear:
+
+```
+	gpio_hdmi_enable: hdmi_enable{
+                 gpios = <&gpio0 2 0>;
+                 no-auto-init;
+        };
+	gpio_udb_c1_int: udb_c1_int {
+                 gpios = <&gpio0 2 GPIO_PULL_UP>;
+                 no-auto-init;
+        };
+```
+
+The board config handling may have:
+
+```
+...
+    if (board_type() == 1) {
+	gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_hdmi_enable), GPIO_OUTPUT);
+    } else {
+	gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_int), GPIO_INPUT);
+    }
+```
+
+Alternatively, a DTS alias may be used:
+
+```
+    gpio_alt_pin: alt_pin {
+	gpios = <&gpio0 2 GPIO_PULL_UP>;
+	no-auto-init;
+    };
+...
+aliases {
+    gpio-usb-c1-int = &gpio_alt_pin;
+    gpio-hdmi-enable = &gpio_alt_pin;
+};
+...
+    if (board_type() == 1) {
+    	/* Use as output to enable the HDMI port */
+	gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_hdmi_enable), GPIO_OUTPUT);
+    } else {
+	/* Use as type C port 1 interrupt */
+	gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int), GPIO_INPUT);
+	/* enable interrupt */
+	...
+    }
+
+```
+
+Note that the alias names have a dash instead of an underscore
+(because the alias name is a *property*, not a node name), but the
+name is converted to lower case with underscores for code access.
+
+### Unused GPIOs
+
+Unused GPIOs should be listed separately in an `unused-gpio` node.  EC chip
+specific code initializes all the unused GPIOs for optimum power consumption.
+
+For example on the Volteer reference board:
+
+```
+    unused-pins {
+        compatible = "unused-gpios";
+        unused-gpios =
+            <&gpio3 4 0>, /* Unused, default platform initialization. */
+	    ...
+            <&gpiob 6 GPIO_OUTPUT_LOW>; /* Explicit initialization flags. */
+};
+```
+
+### Low Voltage Pins
+
+Low voltage pins configuration depends on the specific chip family.
+
+For Nuvoton, this is done using the `GPIO_VOLTAGE_1P8` flag in the `named-gpios`
+child node. For example
+
+```
+named-gpios {
+        compatible = "named-gpios";
+        ...
+        ec-i2c-sensor-scl {
+                gpios = <&gpiob 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+        };
+        ...
+}
+```
+
+For ITE, this is done using the `GPIO_VOLTAGE_1P8` flag in the `named-gpios`
+child node. For example
+
+```
+named-gpios {
+        compatible = "named-gpios";
+	...
+        spi0_cs {
+                gpios = <&gpiom 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+                enum-name = "GPIO_SPI0_CS";
+        };
+	...
+}
+```
+
+## GPIO Interrupts
+
+GPIO interrupts are specified in a device tree node with
+a `compatible` property of `cros-ec,gpio-interrupts`.
+
+Child nodes of this single node contain the following properties:
+
+Property | Description | Settings
+:------- | :---------- | :-------
+`irq-pin` | A reference via a [*node label*] to the named-gpio that is associated with this interrupt. | `<&gpio_label>`
+`flags` | The GPIO [interrupt flags](https://docs.zephyrproject.org/latest/reference/peripherals/gpio.html) that define how the interrupt is generated. | `GPIO_INT_<flags>`
+`handler` | The C name of the interrupt handler that handles the interrupt. | C function name.
+
+For example:
+
+```
+gpio-interrupts {
+        compatible = "cros-ec,gpio-interrupts";
+...
+        int_power_button: power_button {
+                irq-pin = <&gpio_ec_pwr_btn_l>;
+		flags = <GPIO_INT_EDGE_BOTH>;
+                handler = "power_button_interrupt";
+        };
+...
+}
+```
+
+There must only be one named node containing all of the device tree interrupt
+configuration, but of course overlays may be used to add child nodes or
+modify the single node.
+
+The C handler takes one argument, the `enum signal` of the GPIO, such as:
+
+```
+void power_button_interrupt(enum gpio_signal signal)
+{
+	/* Process power button event */
+...
+}
+```
+
+This matches the function signature of the existing legacy interrupt
+handlers, so no shims are required.
+
+Interrupt handlers in Zephyr based code may need to compare
+the `signal` against known GPIOs, if (for instance) there is a
+common handler for events from multiple GPIOs.
+Rather than using the predefined enums (which require that the GPIO
+has an `enum-name` property), the macro `GPIO_SIGNAL(node_id)` may be
+used to uniquely identify the signal regardless of whether
+an `enum-name` property is on the GPIO e.g:
+
+```
+void button_input(enum gpio_signal signal)
+{
+	switch(signal) {
+	case GPIO_SIGNAL(DT_NODELABEL(gpio_volume_up)):
+		...
+		break;
+	case GPIO_SIGNAL(DT_NODELABEL(gpio_volume_down)):
+		...
+		break;
+	case GPIO_SIGNAL(DT_NODELABEL(gpio_power_button)):
+		...
+		break;
+	}
+}
+```
+
+Before any interrupt can be received, it must be enabled.
+Legacy code uses the functions `gpio_enable_interrupt(enum signal)` and
+`gpio_disable_interrupt(enum signal)` functions. Do not use these in
+any Zephyr based code.
+
+Whilst it is possible to use the Zephyr GPIO interrupt API directly,
+for convenience (until the deprecation of the legacy GPIO enum signal names)
+interrupts can be identified via a macro and the label on the interrupt nodes,
+and these can be used to enable or disable the interrupts:
+
+```
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_power_button));
+```
+
+This avoid having to create boiler-plate callbacks as part of the interrupt setup.
+
+For nodes that require a reference to an GPIO interrupt (such as sensor
+configuration node etc.), the node can be referenced directly
+using `GPIO_INT_FROM_NODE` e.g:
+
+```
+[DTS]
+	sensor-irqs = <
+		&int_imu
+		&int_accel
+		>;
+[code]
+
+#define ENABLE_SENSOR_INTS(i, id) \
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODE(DT_PHANDLE_BY_IDX(id, sensor_irqs, i)))
+
+```
+
+## Threads
+
+GPIO support does not enable any threads.
+
+## Testing and Debugging
+
+### Shell Commands
+
+The EC application defines two different shell commands to read and
+change the state of a GPIO:
+
+Command | Description | Usage
+:------ | :---------- | :----
+`gpioget` | Read the current state of a GPIO | `gpioget [name]`
+`gpioset` | Change the state of a GPIO | `gpioset name <value>`
+
+GPIO parameter summary:
+
+Parameter | Description
+:-------- | :----------
+`name` | The GPIO node name as defined in the devicetree.
+`value` | The requested state, `0` or `1`.
+
+## Example
+
+The image below shows a GPIO assignment on the Volteer reference board.
+
+![GPIO Example]
+
+In this example, the `EC_ENTERING_RW` line could be configured as:
+
+Net Name | Port | Pin  | Flags
+:------- | :--- | :--- | :----
+EC_ENTERING_RW | GPIOE | 3 | Output, initialize low
+
+
+Which translate in the devicetree node:
+
+```
+named-gpios {
+        compatible = "named-gpios";
+	...
+        gpio_ec_entering_rw: ec_entering_rw {
+                gpios = <&gpioe 3 GPIO_OUT_LOW>;
+                enum-name = "GPIO_ENTERING_RW";
+        };
+	...
+}
+```
+
+Set or get the GPIO value in the C source code directly using the `enum-name`
+property `GPIO_ENTERING_RW`.
+
+```
+    gpio_set_level(GPIO_ENTERING_RW, 0);
+    val = gpio_get_level(GPIO_ENTERING_RW);
+```
+
+Use the [*node label*] to reference the GPIO in other devicetree nodes:
+
+```
+my_node: my-node {
+        compatible = "cros-ec,my-feature"
+        signal-pin = <&gpio_ec_entering_rw>;
+};
+```
+
+The `named-gpios` node and subnodes are normally declared in a separate
+[gpio.dts] file, which is added as an overlay in the [BUILD.py] file for the
+project.
+
+[GPIO]: ../ec_terms.md#gpio
+[GPIO Example]: ../images/gpio_example.png
+[Include GPIO drivers in system config]: https://docs.zephyrproject.org/latest/kconfig.html#CONFIG_GPIO
+[GPIO Init Priority]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.init_priority?q=%22config%20PLATFORM_EC_GPIO_INIT_PRIORITY%22&ss=chromiumos
+[nuvoton,npcx-lvolctrl-def]: https://github.com/zephyrproject-rtos/zephyr/blob/main/dts/bindings/pinctrl/nuvoton,npcx-lvolctrl-def.yaml
+[gpio-enum-name.yaml]: ../../zephyr/dts/bindings/gpio/gpio-enum-name.yaml
+[dt-bindings/gpio/gpio.h]: https://github.com/zephyrproject-rtos/zephyr/blob/main/include/dt-bindings/gpio/gpio.h
+[dt-bindings/gpio_defines.h]: ../../zephyr/include/dt-bindings/gpio_defines.h
+[include/drivers/gpio.h]: https://docs.zephyrproject.org/latest/reference/peripherals/gpio.html?highlight=gpio_int_disable#api-reference
+[gpio.dts]: ../../zephyr/projects/volteer/volteer/gpio.dts
+[interrupts.dts]: ../../zephyr/projects/volteer/volteer/interrupts.dts
+[BUILD.py]: ../../zephyr/projects/volteer/volteer/BUILD.py
+[*node label*]: https://docs.zephyrproject.org/latest/build/dts/intro.html#dt-node-labels
+[npcx9.dtsi]: https://github.com/zephyrproject-rtos/zephyr/blob/main/dts/arm/nuvoton/npcx9.dtsi
diff --git a/docs/zephyr/zephyr_i2c.md b/docs/zephyr/zephyr_i2c.md
new file mode 100644
index 0000000000..f8d17381d7
--- /dev/null
+++ b/docs/zephyr/zephyr_i2c.md
@@ -0,0 +1,342 @@
+# Zephyr I2C Bus Configuration
+
+[TOC]
+
+## Overview
+
+The [I2C] buses provide access and control to on-board peripherals, including
+USB-C chips, battery, charging IC, and sensors.
+
+## Kconfig Options
+
+The Kconfig option [`CONFIG_I2C`] enables I2C support in the EC
+application.  Refer to [Kconfig.i2c] for all sub-options related to I2C support.
+
+The upstream Zephyr I2C driver also provides I2C shell commands with the
+[`CONFIG_I2C_SHELL`] option.
+
+## Devicetree Nodes
+
+The EC chip disables all I2C buses by default.  Enable the I2C buses used on
+your design by changing the chip-specific I2C bus `status` property to `"okay"`.
+
+I2C bus properties:
+
+Property | Description | Settings
+:------- | :---------- | :-------
+`status` | Enables or disables the I2C controller | `"okay"` <br> `"disabled"`
+`label` | Override the EC chip specific label. We recommend changing the label to match the net name of the I2C bus. The label must begin with `"I2C_"`. |`"I2C_<net_name>"`
+`clock-frequency` | Sets the initial I2C bus frequency in Hz. | `I2C_BITRATE_STANDARD` - 100 KHz <br> `I2C_BITRATE_FAST` - 400 KHz <br> `I2C_BITRATE_FAST_PLUS` - 1 MHz
+
+Example enabling I2C0 and I2C3 at 100 KHz and 1 MHz, respectively.
+```
+&i2c0 {
+        status = "okay";
+        label = "I2C_BATTERY";
+        clock-frequency = <I2C_BITRATE_STANDARD>;
+};
+&i2c3 {
+        status = "okay";
+        label = "I2C_USB_C0_PD";
+        clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+};
+```
+
+### Nuvoton NPCX ECs
+
+Nuvoton ECs use two devicetree nodes to describe the I2C buses used, an I2C
+controller and an I2C port.
+
+Nuvoton I2C [*node labels*] use the following pattern:
+- I2C controller: `&i2c_ctrl<controller>`
+- I2C port: `&i2c<controller>_<port>`
+
+Where `<controller>` specifies the I2C controller number (0-7), and `<port>`
+specifies the port number (0-1). You can only enable one I2C port per
+controller, and not all I2C controllers support both ports.
+
+The Nuvoton I2C port contains the standard Zephyr I2C bus properties. The
+Nuvoton I2C controller contains only the `status` property.
+
+To enable a Nuvoton I2C bus, set both the I2C controller and I2C port `status`
+property to `"okay"`.Set the `clock-frequency` and `label` properties in the I2C
+port as shown below:
+
+```
+&i2c_ctrl4 {
+        status = "okay";
+};
+&i2c4_1 {
+        status = "okay";
+        label = "I2C_EEPROM";
+        clock-frequency = <I2C_BITRATE_FAST>;
+};
+```
+
+### ITE IT8xxx2 ECs
+
+ITE ECs use a single devicetree node, `&i2c<channel>` to enable an I2C bus.
+`<channel>` specifies the I2C/SMBus channel number (0-5).
+
+```
+&i2c3 {
+        status = "okay";
+        label = "I2C_USB_C0_PD";
+        clock-frequency = <I2C_BITRATE_STANDARD>;
+};
+```
+
+### Mapping legacy I2C port numbers to Zephyr devicetree nodes
+
+The legacy I2C API for the Chromium EC application uses an enumeration (e.g.
+`I2C_PORT_ACCEL`, `I2C_PORT_EEPROM`) to specify the I2C bus during transfer
+operations.
+
+The `named-i2c-ports` node creates the mapping between the legacy I2C bus
+enumeration and the Zephyr I2C bus device instance.
+
+```
+named-i2c-ports {
+        compatible = "named-i2c-ports";
+        battery {
+                i2c-port = <&i2c0_0>;
+                remote-port = <0>;
+                enum-names = "I2C_PORT_BATTERY";
+        }
+};
+```
+
+You can map multiple enumeration values to the same Zephyr I2C bus device
+instance.
+
+```
+named-i2c-ports {
+        compatible = "named-i2c-ports";
+        battery {
+                i2c-port = <&i2c0_0>;
+                remote-port = <0>;
+                enum-names = "I2C_PORT_BATTERY",
+                	"I2C_PORT_CHARGER";
+        }
+};
+```
+
+Refer to the [cros-ec-i2c-port-base.yaml] child-binding file for details about
+each property.
+
+## Board Specific Code
+
+None required.
+
+## Threads
+
+I2C support does not enable any threads.
+
+## Testing and Debugging
+
+### Shell Command: i2c
+The EC application enables the the Zephyr shell command, `i2c`, when
+`CONFIG_I2C_SHELL=y`. The `i2c` command includes the following [subcommands]:
+
+Subcommand | Description | Usage
+:--------- | :---------- | :----
+`scan` | Scan I2C devices | `i2c scan <i2c_bus_label>`
+`recover` | Recover I2C bus | `i2c recover <i2c_bus_label>`
+`read` | Read bytes from an I2C device | `i2c read <i2c_bus_label> <dev_addr> <reg_addr> [<num_bytes>]`
+`read_byte` | Read a byte from an I2C device | `i2c read_byte <i2c_bus_label> <dev_addr> <reg_addr>`
+`write` | Write bytes to an I2C device | `i2c write <i2c_bus_label> <dev_addr> <reg_addr> <out_byte0> .. <out_byteN>`
+`write_byte` | Write a byte to an I2C device | `i2c write_byte <i2c_bus_label> <dev_addr> <reg_addr> <out_byte>`
+
+I2C parameter summary:
+
+Parameter | Description
+:-------- | :----------
+`<i2c_bus_label>` | The I2C bus label property. By default this is specified by the EC vendor in the respective devicetree include file unless you override the label in your devicetree.
+`<dev_addr>` | The I2C device address, specified using 7-bit notation. Valid device addresses are 0 - 0x7F.
+`<reg_addr>` | The register address with the I2C device to read or write.
+`<num_bytes>` | For the `read` subcommand, specifies the number of bytes to read from the I2C device. Default is 16 bytes if not specified.
+`<out_byte>` | For the `write_byte` subcommand, specifies the single data byte to write to the I2C device.
+`<out_byte0>..<out_byteN>` | For the `write` subcommand, specifies the data bytes to write to the I2C device.
+
+### Shell Command: i2c_portmap
+The shell command `i2c_portmap` displays the mapping of I2C bus enumeration to
+the physical bus and to the remote port index.
+
+Example `i2c_portmap` output from a Volteer board:
+```
+uart:~$ i2c_portmap
+Zephyr physical I2C ports (9):
+  0 : 0
+  1 : 0
+  2 : 1
+  3 : 2
+  4 : 3
+  5 : 4
+  6 : 4
+  7 : 5
+  8 : 5
+Zephyr remote I2C ports (9):
+  0 : -1
+  1 : -1
+  2 : -1
+  3 : -1
+  4 : -1
+  5 : -1
+  6 : -1
+  7 : 7
+  8 : -1
+```
+
+### I2C Tracing
+
+For runtime troubleshooting of an I2C device, enable the [I2C
+tracing](../i2c-debugging.md) module to log all I2C transactions initiated by
+the EC code.
+
+## Example
+
+The image below shows the I2C bus assignment for the Volteer reference board.
+
+![I2C Example]
+
+The Volteer reference design uses the Nuvoton NPCX EC, and needs the following
+I2C buses enabled:
+
+Net Name           | NPCX I2C Designator | Bus speed
+:----------------- | :------------------ | :--------
+EC_I2C7_EEPROM_PWR | I2C7_PORT0          | 400 kHz
+EC_I2C5_BATTERY    | I2C5_PORT0          | 100 kHz
+EC_I2C0_SENSOR     | I2C0_PORT0          | 400 kHz
+EC_I2C1_USB_C0     | I2C1_PORT0          | 1000 kHz
+EC_I2C2_USB_C1     | I2C2_PORT0          | 1000 kHz
+EC_I2C3_USB_1_MIX  | I2C3_PORT0          | 100 kHz
+
+
+### Enable Nuvoton I2C buses
+The Volteer project enables the Nuvoton I2C buses in [volteer.dts].
+
+```c
+&i2c0_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	label = "I2C_SENSOR";
+};
+&i2c_ctrl0 {
+	status = "okay";
+};
+
+&i2c1_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+	label = "I2C_USB_C0";
+};
+&i2c_ctrl1 {
+	status = "okay";
+};
+
+&i2c2_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+	label = "I2C_USB_C1";
+};
+&i2c_ctrl2 {
+	status = "okay";
+};
+
+&i2c3_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	label = "I2C_USB_1_MIX";
+};
+&i2c_ctrl3 {
+	status = "okay";
+};
+
+&i2c5_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	label = "I2C_BATTERY";
+};
+&i2c_ctrl5 {
+	status = "okay";
+};
+
+&i2c7_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	label = "I2C_EEPROM_PWR";
+
+	isl9241: isl9241@9 {
+		compatible = "intersil,isl9241";
+		reg = <0x09>;
+		label = "ISL9241_CHARGER";
+		switching-frequency = <SWITCHING_FREQ_724KHZ>;
+	};
+};
+&i2c_ctrl7 {
+	status = "okay";
+};
+```
+
+### Map I2C Enumerations
+The legacy cros-ec drivers require the board to define the following enumeration
+values:
+
+I2C Enumeration Name | Volteer I2C Bus Mapping
+:------------------- | :----------------------
+`I2C_PORT_SENSOR`    | EC_I2C0_SENSOR
+`I2C_PORT_ACCEL`     | EC_I2C0_SENSOR
+`I2C_PORT_USB_C0`    | EC_I2C1_USB_C0
+`I2C_PORT_USB_C1`    | EC_I2C2_USB_C1
+`I2C_PORT_USB_1_MIX` | EC_I2C3_USB_1_MIX
+`I2C_PORT_POWER`     | EC_I2C5_BATTERY
+`I2C_PORT_BATTERY`   | EC_I2C5_BATTERY
+`I2C_PORT_EEPROM`    | EC_I2C7_EEPROM_PWR
+`I2C_PORT_CHARGER`   | EC_I2C7_EEPROM_PWR
+
+The Volteer project establishes this map using the `named-i2c-ports` as shown
+below:
+
+```c
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		i2c_sensor: sensor {
+			i2c-port = <&i2c0_0>;
+			enum-names = "I2C_PORT_SENSOR",
+				"I2C_PORT_ACCEL";
+		};
+		i2c_usb_c0: usb-c0 {
+			i2c-port = <&i2c1_0>;
+			enum-names = "I2C_PORT_USB_C0";
+		};
+		i2c_usb_c1: usb-c1 {
+			i2c-port = <&i2c2_0>;
+			enum-names = "I2C_PORT_USB_C1";
+		};
+		usb1-mix {
+			i2c-port = <&i2c3_0>;
+			enum-names = "I2C_PORT_USB_1_MIX";
+		};
+		power {
+			i2c-port = <&i2c5_0>;
+			enum-names = "I2C_PORT_POWER",
+				"I2C_PORT_BATTERY";
+		};
+		eeprom {
+			i2c-port = <&i2c7_0>;
+			enum-names = "I2C_PORT_EEPROM",
+				"I2C_PORT_CHARGER";
+		};
+	};
+```
+
+[I2C]: ../ec_terms.md#i2c
+[subcommands]: https://github.com/zephyrproject-rtos/zephyr/blob/f4a0ea7b43eee4d2ee735ab6beccc68c9d40a7d0/drivers/i2c/i2c_shell.c#L245
+[I2C Example]: ../images/i2c_example.png
+[Kconfig.i2c]: ../../zephyr/Kconfig.i2c
+[`CONFIG_I2C`]: https://docs.zephyrproject.org/latest/kconfig.html#CONFIG_I2C
+[`CONFIG_I2C_SHELL`]: https://docs.zephyrproject.org/latest/kconfig.html#CONFIG_I2C_SHELL
+[cros-ec-i2c-port-base.yaml]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/dts/bindings/i2c/cros-ec-i2c-port-base.yaml
+[volteer.dts]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/boards/arm/volteer/volteer.dts;
+[*node labels*]: https://docs.zephyrproject.org/latest/build/dts/intro.html#dt-node-labels
\ No newline at end of file
diff --git a/docs/zephyr/zephyr_init.md b/docs/zephyr/zephyr_init.md
new file mode 100644
index 0000000000..8822736efb
--- /dev/null
+++ b/docs/zephyr/zephyr_init.md
@@ -0,0 +1,53 @@
+# Zephyr OS-based EC Initialization Order
+
+Zephyr provides Z_INIT_ENTRY_DEFINE() & the extend macro to install the initial
+function. The initialize flow for different levels would be like the following
+(not very detailed):
+*   architecture-specific initialization
+*   `PRE_KERNEL_1` level
+*   `PRE_KERNEL_2` level
+*   `POST_KERNEL` level
+*   `APPLICATION` level
+*   main()
+
+The kernel and driver initial functions separate into specific initialize
+levels. It couldn't put all initial functions in main() for the Zephyr OS-based
+EC. It is also hard to maintain those initial priority which separates into
+different files.
+
+This file defines some Zephyr OS-based EC initial priorities which have critical
+sequence requirement for initializing:
+
+## PRE_KERNEL_1
+*   Priority (0-9) - Reserved for system testability:
+
+    The highest priority could be used in zephyr. Don't use it when system
+    development. Buffer it for the following system development & testing.
+
+*   Priority (10-19) - Chip level system pre-initialization:
+
+    These priorities in this range are used for critical chip initialization,
+    including determining the reset cause and initializing the battery-backed
+    RAM driver. Most chip drivers should only be initialized after
+    `PLATFORM_EC_SYSTEM_PRE_INIT`.
+
+*   Priority (20) - PLATFORM_EC_SYSTEM_PRE_INIT:
+
+    At this initialization priority, the CROS system checks the reset cause and
+    initializing the system reset flags. Any chip level drivers related to
+    determining the reset type must be at a higher priority.
+
+*   TODO
+
+## PRE_KERNEL_2
+*   TODO
+
+## POST_KERNEL
+*   TODO
+
+## APPLICATION
+*   TODO
+
+## main()
+*   TODO
+*   Start the tasks.
diff --git a/docs/zephyr/zephyr_leds.md b/docs/zephyr/zephyr_leds.md
new file mode 100644
index 0000000000..5601d913c7
--- /dev/null
+++ b/docs/zephyr/zephyr_leds.md
@@ -0,0 +1,238 @@
+# Zephyr EC LEDs
+
+[TOC]
+
+## Overview
+
+[LEDs](../ec_terms.md#led) provide status about the following:
+
+-   Dedicated battery state/charging state
+-   Chromebook power
+-   Adapter power
+-   Left side USB-C port (battery state/charging state)
+-   Right side USB-C port (battery state/charging state)
+-   Recovery mode
+-   Debug mode
+
+LEDs can be configured as simple GPIOs, with on/off control only, or as [PWM](../ec_terms.md#pwm) with
+adjustment brightness and color.
+
+## Kconfig Options
+
+The `CONFIG_PLATFORM_EC_LED_DT` option, found in the [Kconfig.led_dt](../../zephyr/Kconfig.led_dt) file, enables devicetree based configuration of LED
+policies and colors.
+
+Enabling the devicetree LED implementation requires that you disable the legacy EC implementation.
+
+Example:
+```
+# LED
+CONFIG_PLATFORM_EC_LED_COMMON=n
+```
+
+Enable other [config options](../configuration/leds.md) supported in the legacy code.
+
+## Devicetree Nodes
+
+LEDs are configured in two steps.
+
+### Configure LED colors
+The LED colors are configured using either GPIO based LEDs or PWM based LEDs.
+
+#### GPIO based LEDs
+Configure GPIO based LEDs using `cros-ec,gpio-led-pins` compatible node
+described by [cros-ec,gpio_led_pins.yaml].
+
+Example:
+
+For this example, the board contains dual-channel LED, one channel turns on the
+blue color, and one channel turns on the amber color.
+To set the LED color to amber, the yellow channel is enabled and the blue
+channel is disabled.
+
+```
+gpio-led-pins {
+	compatible = "cros-ec,gpio-led-pins";
+        /* Amber - turn on yellow LED */
+	color_amber: color-amber {
+		led-pins = <&gpio_ec_chg_led_y_c1 &gpio_ec_chg_led_b_c1>;
+		led-values = <1 0>;
+	};
+	/* Blue - turn on blue LED */
+	color_blue: color-blue {
+		led-pins = <&gpio_ec_chg_led_y_c1 &gpio_ec_chg_led_b_c1>;
+		led-values = <0 1>;
+	};
+	/* White - turn on both LEDs */
+	color_white: color-white {
+		led-pins = <&gpio_ec_chg_led_y_c1 &gpio_ec_chg_led_b_c1>;
+		led-values = <1 1>;
+	};
+	/* Off - turn off both LEDs */
+	color_off: color-off {
+		led-pins = <&gpio_ec_chg_led_y_c1 &gpio_ec_chg_led_b_c1>;
+		led-values = <0 0>;
+	};
+};
+```
+GPIO LED Pins dts file example: [led_pins_herobrine.dts]
+
+#### PWM based LEDs
+Configure PWM based LEDs with two separate nodes.
+The `pwm-leds` node, described in [pwm-leds.yaml], configures the PWM channel
+and frequency. The `cros-ec,pwm-led-pins` node, described in
+[cros-ec,pwm_led_pins.yaml], configures the LED colors. PWM LEDs can vary
+duty-cycle percentage, providing finer color control over GPIO LEDs.
+
+Example:
+
+For this example, the board contains dual-channel LED, one channel controls
+white color intensity, and one channel controls the amber color intensity. To
+set the LED color to amber, the yellow channel duty-cycle is set to 100
+percentage and white channel duty-cycle is set to 0.
+```
+pwmleds {
+	compatible = "pwm-leds";
+
+	pwm_y: pwm_y {
+		pwms = <&pwm2 0 PWM_HZ(100) PWM_POLARITY_INVERTED>;
+	};
+
+	pwm_w: pwm_w {
+		pwms = <&pwm3 0 PWM_HZ(100) PWM_POLARITY_INVERTED>;
+	};
+};
+
+pwm-led-pins {
+	compatible = "cros-ec,pwm-led-pins";
+	pwm-frequency = <100>;
+	/* Amber - turn on yellow LED */
+	color_amber: color-amber {
+		led-pwms = <&pwm_y &pwm_w>;
+		pwm-values = <100 0>;
+	};
+	/* White - turn on white LED */
+	color_white: color-white {
+		led-pwms = <&pwm_y &pwm_w>;
+		pwm-values = <0 100>;
+	};
+	/* Off - turn off both LEDs */
+	color_off: color-off {
+		led-pwms = <&pwm_y &pwm_w>;
+		pwm-values = <0 0>;
+	};
+};
+```
+
+PWM LED Pins dts file example: [led_pins_skyrim.dts]
+
+### Configure LED Policies
+`cros-ec,led-policy` nodes describe the LED policy and set the LED behavior by
+referencing `cros-ec,gpio-led-pins` or `cros-ec,pwm-led-pins` nodes.
+These are described in [cros-ec,led_policy.yaml]
+
+
+Example:
+
+Color policies to configure physical behavior of an LED
+
+e.g. If you want an LED to blink, create 2 color policies, one to turn on the
+LED and one to turn off the LED.
+
+```
+color-0 {
+	led-color = <&color_amber>;
+        period-ms = <1000>;
+        };
+color-1 {
+	led-color = <&color-off>;
+        period-ms = <1000>;
+        };
+```
+
+To tie this behavior with a system state, properties defining system state and
+color policies are added to `cros-ec,led-policy` node.
+
+e.g. To add a blinking behavior for a system state where charge-state is
+"LED_PWR_STATE_DISCHARGE" and chipset-state is "POWER_S3", a policy node
+is defined as below.
+
+```
+led-policy {
+	compatible = "cros-ec,led-policy";
+	...
+	...
+	power-state-discharge-s3 {
+		charge-state = "LED_PWR_STATE_DISCHARGE";
+		chipset-state = "POWER_S3";
+
+		/* Amber 1 sec, off 3 sec */
+		color-0 {
+			led-color = <&color_amber>;
+			period-ms = <1000>;
+		};
+		color-1 {
+			led-color = <&color_off>;
+			period-ms = <3000>;
+		};
+	};
+	...
+	...
+}
+```
+
+Note: It is recommended to split the policy specification and the pins
+specification into two devicetree files. e.g. [led_policy_skyrim.dts],
+[led_pins_skyrim.dts]
+
+LED policy dts file examples
+[led_policy_skyrim.dts], [led_policy_herobrine.dts]
+
+## Board Specific Code
+
+None
+
+## Threads
+
+The LEDs are controlled by hook task in the file
+[led_driver/led.c](https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/shim/src/led_driver/led.c).
+
+## Testing and Debugging
+TODO: Enable support for ledtest
+
+## Examples
+
+### How to setup LEDs and add nodes
+
+![Alt text](https://screenshot.googleplex.com/4eqXmo2jLcSD6eL.png)
+
+-   Look for the gpio/pwm pins in the schematic with which the LEDs are
+attached to.
+-   In the above snippet, LEDs are configured to use PWM pins and attached to
+PWM2 and PWM3.
+-   Add PWM config nodes as shown in [pwm-leds.yaml] and [led_pins_skyrim.dts].
+-   Add pin nodes based on the color of the LEDs attached as shown in
+[cros-ec,pwm_led_pins.yaml] and [led_pins_skyrim.dts]. Name the nodes according
+to the LED color for readability. e.g. `color-amber`
+-   Based on the device LED policy, create led_policy nodes as shown in
+[cros-ec,led_policy.yaml] and [led_policy_skyrim.dts].
+
+### PWM
+
+[Example CL enabling single port pwm based LEDs]
+
+### GPIO
+
+[Example CL enabling dual port gpio based LEDs]
+
+<!-- Reference Links -->
+[cros-ec,led_policy.yaml]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/dts/bindings/leds/cros-ec,led-colors.yaml
+[cros-ec,gpio_led_pins.yaml]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/dts/bindings/leds/cros-ec,gpio-led-pins.yaml
+[cros-ec,pwm_led_pins.yaml]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/dts/bindings/leds/cros-ec,pwm-led-pins.yaml
+[pwm-leds.yaml]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/zephyr/main/dts/bindings/led/pwm-leds.yaml
+[led_policy_skyrim.dts]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/program/skyrim/led_policy_skyrim.dts
+[led_pins_skyrim.dts]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/program/skyrim/led_pins_skyrim.dts
+[led_policy_herobrine.dts]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/program/herobrine/led_policy_herobrine.dts
+[led_pins_herobrine.dts]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/program/herobrine/led_pins_herobrine.dts
+[Example CL enabling single port pwm based LEDs]: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3651490
+[Example CL enabling dual port gpio based LEDs]: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3635067
diff --git a/docs/zephyr/zephyr_mkbp.md b/docs/zephyr/zephyr_mkbp.md
new file mode 100644
index 0000000000..9fa8cac71b
--- /dev/null
+++ b/docs/zephyr/zephyr_mkbp.md
@@ -0,0 +1,99 @@
+# MKBP - Matrix Keyboard Protocol
+
+[TOC]
+
+## Overview
+
+[MKBP] was originally used to send keyboard events to AP OS.
+Later, more functionalities were added and more types of events can be sent
+using this protocol. It can transfer information about keystrokes, sensors,
+switches, fingerprints and more.
+
+Kconfig sub-options                          | Default     | Documentation
+:------------------------------------------- | :---------: | :------------
+`CONFIG_PLATFORM_EC_MKBP_INPUT_DEVICES`      | n           | [MKBP input devices]
+`CONFIG_PLATFORM_EC_MKBP_EVENT`              | n           | [MKBP event]
+
+## Delivery method
+
+The following options select the delivery method of MKBP messages.
+
+Kconfig sub-options                              | Default     | Documentation
+:----------------------------------------------- | :---------: | :------------
+`CONFIG_PLATFORM_EC_MKBP_USE_GPIO`               | y           | [MKBP gpio]
+`CONFIG_PLATFORM_EC_MKBP_USE_HOST_EVENT`         | n           | [MKBP host event]
+`CONFIG_PLATFORM_EC_MKBP_USE_GPIO_AND_HOST_EVENT`| n           | [MKBP gpio and host event]
+`CONFIG_PLATFORM_EC_MKBP_USE_CUSTOM`             | n           | [MKBP custom]
+
+## Wake-up masks
+
+The EC can wake up the AP from sleep modes based on multiple event types.
+A wake-up mask specifies which specific event types are able to wake the AP.
+
+For x86 based Chromebooks, the wake-up mask is controlled by the AP firmware
+directly using host commands `EC_CMD_HOST_EVENT_SET_SMI_MASK`,
+`EC_CMD_HOST_EVENT_SET_SCI_MASK` and `EC_CMD_HOST_EVENT_SET_WAKE_MASK`.
+
+For ARM based Chromebooks, the wake-up mask is defined as device tree nodes,
+one for MKBP events and one for generic host events.
+They have respective Kconfig options, which must be enabled to take the masks
+into account.
+
+### Kconfigs
+
+The Kconfigs responsible for enabling the wake-up masks are automatically
+selected if the device tree nodes are specified.
+See [Device Tree nodes](#device-tree-nodes) paragraph for details.
+
+### Device Tree nodes
+
+Both masks have to be compatible with binding file: [MKBP event mask yaml]
+
+Possible enums to use in these nodes are specified in file: [MKBP event mask enums]
+
+```
+/ {
+	ec-mkbp-host-event-wakeup-mask {
+		compatible = "cros-ec,mkbp-host-event-wakeup-mask";
+		wakeup-mask = <(HOST_EVENT_LID_OPEN |
+				HOST_EVENT_POWER_BUTTON |
+				HOST_EVENT_AC_CONNECTED |
+				HOST_EVENT_AC_DISCONNECTED |
+				HOST_EVENT_HANG_DETECT |
+				HOST_EVENT_RTC |
+				HOST_EVENT_MODE_CHANGE |
+				HOST_EVENT_DEVICE)>;
+	};
+
+	ec-mkbp-event-wakeup-mask {
+		compatible = "cros-ec,mkbp-event-wakeup-mask";
+		wakeup-mask = <(MKBP_EVENT_KEY_MATRIX |
+				MKBP_EVENT_HOST_EVENT |
+				MKBP_EVENT_SENSOR_FIFO)>;
+	};
+}
+```
+
+## Examples
+
+[Lazor wake-up masks](https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/program/trogdor/lazor/gpio.dts?q=ec-mkbp-host-event-wakeup-mask)
+
+For detailed descriptions of the MKBP and host event types, please see
+[ec_commands.h](/include/ec_commands.h) header file.
+
+<!--
+Links to the documentation
+-->
+
+[MKBP]:../ec_terms.md#mkbp
+
+[MKBP input devices]:https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig?q=%22config%20PLATFORM_EC_MKBP_INPUT_DEVICES%22
+[MKBP event]:https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig?q=%22config%20PLATFORM_EC_MKBP_EVENT%22
+
+[MKBP gpio]:https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.mkbp_event?q=%22config%20PLATFORM_EC_MKBP_USE_GPIO%22
+[MKBP host event]:https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.mkbp_event?q=%22config%20PLATFORM_EC_MKBP_USE_HOST_EVENT%22
+[MKBP gpio and host event]:https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.mkbp_event?q=%22config%20PLATFORM_EC_MKBP_USE_GPIO_AND_HOST_EVENT%22
+[MKBP custom]:https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.mkbp_event?q=%22config%20PLATFORM_EC_MKBP_USE_CUSTOM%22
+
+[MKBP event mask yaml]:https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/dts/bindings/cros_mkbp_event/ec-mkbp-event.yaml
+[MKBP event mask enums]:https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/include/dt-bindings/wake_mask_event_defines.h
diff --git a/docs/zephyr/zephyr_motionsense.md b/docs/zephyr/zephyr_motionsense.md
new file mode 100644
index 0000000000..4e6d0102ca
--- /dev/null
+++ b/docs/zephyr/zephyr_motionsense.md
@@ -0,0 +1,287 @@
+# Zephyr EC MotionSense
+
+[TOC]
+
+## Overview
+
+Zephyr's wrapping of the EC motionsense provides a quick configuration of the
+sensor framework via Zephyr's device tree.
+
+## Kconfig Options
+
+The following are the various Kconfig options for the motionsense logic. Every
+config option depends on having `CONFIG_PLATFORM_EC_MOTIONSENSE=y`.
+
+Kconfig Option                                   | Default | Documentation
+:----------------------------------------------- | :-----: | :------------
+`CONFIG_PLATFORM_EC_MOTIONSENSE`                 | n       | [MOTIONSENSE]
+`CONFIG_PLATFORM_EC_ACCEL_FIFO`                  | n       | [ACCEL FIFO]
+`CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS`     | n       | [TIGHT TIMESTAMPS]
+`CONFIG_PLATFORM_EC_ALS`                         | n       | [ALS]
+`CONFIG_PLATFORM_EC_DYNAMIC_MOTION_SENSOR_COUNT` | n       | [DYNAMIC SENSOR COUNT]
+`CONFIG_PLATFORM_EC_LID_ANGLE`                   | n       | [LID ANGLE]
+`CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS`          | n       | [ACCELS CMD]
+`CONFIG_PLATFORM_EC_ACCEL_SPOOF_MODE`            | n       | [ACCEL SPOOF MODE]
+`CONFIG_PLATFORM_EC_MAX_SENSOR_FREQ_MILLIHZ`     | n       | [MAX SENSOR FREQUENCY]
+
+Additional Kconfig options are available at
+[Kconfig.sensor_devices](./zephyr_sensor_devices.md).
+
+### CONFIG_PLATFORM_EC_ACCEL_FIFO sub configs
+
+The following options are available only when `CONFIG_PLATFORM_EC_ACCEL_FIFO=y`.
+
+Kconfig sub-option                     | Default | Documentation
+:------------------------------------- | :-----: | :------------
+`CONFIG_PLATFORM_EC_ACCEL_FIFO_SIZE`   | 256     | [ACCEL FIFO SIZE]
+`CONFIG_PLATFORM_EC_ACCEL_FIFO_THRES`  | 85      | [ACCEL FIFO THRES]
+
+### CONFIG_PLATFORM_EC_LID_ANGLE sub configs
+
+The following options are available only when `CONFIG_PLATFORM_EC_LID_ANGLE=y`.
+
+Kconfig sub-option                     | Default | Documentation
+:------------------------------------- | :-----: | :------------
+`CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE`  | n       | [LID ANGLE UPDATE]
+`CONFIG_PLATFORM_EC_TABLET_MODE`       | n       | [TABLET MODE]
+
+### CONFIG_PLATFORM_EC_TABLET_MODE sub configs
+
+The following options are available only when `CONFIG_PLATFORM_EC_TABLET_MODE=y`.
+
+Kconfig sub-option                       | Default | Documentation
+:--------------------------------------- | :-----: | :------------
+`CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH`  | n       | [TABLET MODE SWITCH]
+`CONFIG_PLATFORM_EC_GMR_TABLET_MODE`     | n       | [GMR TABLET MODE]
+
+### CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS sub configs
+
+The following options are available only when `CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=y`.
+
+Kconfig sub-option                           | Default | Documentation
+:------------------------------------------- | :-----: | :------------
+`CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO`  | n       | [ACCEL INFO CMD]
+
+### CONFIG_PLATFORM_EC_ACCEL_SPOOF_MODE sub configs
+
+The following options are available only when `CONFIG_PLATFORM_EC_ACCEL_SPOOF_MODE=y`.
+
+Kconfig sub-option                           | Default | Documentation
+:------------------------------------------- | :-----: | :------------
+`CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_SPOOF` | n       | [ACCEL SPOOF CMD]
+
+## Devicetree Nodes
+
+Initiating the devicetree nodes for motionsense requires a bit of internal
+knowledge of the drivers'
+[bindings](https://source.chromium.org/chromium/chromiumos/platform/ec/+/HEAD:zephyr/dts/bindings/motionsense/).
+
+### Sensor mutex
+
+Some drivers, such as the BMI260, which combine 2 sensors (accelerometer and
+gyroscope) will require a mutex to be defined. The individual nodes in the
+devicetree will accept a `phandle` pointing to the mutex
+[here](https://source.chromium.org/chromium/chromiumos/platform/ec/+/HEAD:zephyr/dts/bindings/motionsense/motionsense-sensor-base.yaml;l=37;drc=67e0b58c17177858595001baa1aa607b54b18d11).
+It is important for both nodes of these sensors to point to the same mutex (
+see example below).
+
+### Location and orientation
+
+The location of the sensor is dictated in an enum property
+[location](https://source.chromium.org/chromium/chromiumos/platform/ec/+/HEAD:zephyr/dts/bindings/motionsense/motionsense-sensor-base.yaml;l=29;drc=67e0b58c17177858595001baa1aa607b54b18d11).
+It is important to note that sensors which are combined in a single chip (such
+as the BMI260) should have the same value for both nodes.
+This property allows the distinction between sensors location at the following:
+
+* "base" - the base of the laptop (where the keyboard is).
+* "lid" - the screen surface of the laptop.
+* "camera" - an explicit location for the camera.
+
+In addition to the location, each sensor node should also include a reference
+to a [rotation matrix](https://source.chromium.org/chromium/chromiumos/platform/ec/+/HEAD:zephyr/dts/bindings/motionsense/motionsense-sensor-base.yaml;l=45;drc=67e0b58c17177858595001baa1aa607b54b18d11).
+This will be used to orient the sensor data according to the standardised screen
+coordinates.
+
+### Internal sensor data
+
+Internal sensor data nodes can be found [here](https://source.chromium.org/chromium/chromiumos/platform/ec/+/HEAD:zephyr/dts/bindings/motionsense/drvdata/).
+These are required, one per physical sensor, in order to instantiate the
+internal data structures. It is important to check the required properties of
+each binding to ensure proper instantiation.
+
+### Motion sensor nodes
+
+All motion sensor nodes (accel, gyro, and mag) should be declared inside the
+`motionsense-sensor` node. This will in-turn create the `motion_sensors` array
+required for the sensor logic.
+
+### Additional sensor meta-data
+
+Additional information about sensors can be provided by the
+[motionsense-sensor-info](https://source.chromium.org/chromium/chromiumos/platform/ec/+/HEAD:zephyr/dts/bindings/motionsense/cros-ec,motionsense-sensor-info.yaml).
+This node provides information about the ALS (ambient light sensor) list, the
+various interrupts, and sensors which are placed in force mode (motionsense will
+directly query these sensors instead of waiting for an interrupt).
+
+## Board Specific Code
+
+Motionsense requires no board specific code.
+
+## Threads
+
+When enabled, the `motion_sense_task` will be created. The task's stack size can
+be set using `CONFIG_TASK_MOTIONSENSE_STACK_SIZE`, but the priority is fixed.
+Additional information about the task priority can be found in
+[shimmed_task_id.h](https://source.chromium.org/chromium/chromiumos/platform/ec/+/HEAD:zephyr/shim/include/shimmed_task_id.h).
+
+## Testing and Debugging
+
+Properly debugging the sensor framework generally involves one of the following:
+
+* If the device is a convertible (laptop/tablet) flip the screen over and make
+  sure that screen rotations work.
+* In the EC console test the following commands:
+  * `accelrange id [data [roundup]]` where the `id` is the sensor number. If
+    `data` is not provided, then this command will perform a read and print the
+    range of the motion sensor. Otherwise, it will set the range to the nearest
+    `data` value depending on `roundup` being either `0` or `1`.
+  * `accelres id [data [roundup]]` where the `id` is the sensor number. If
+    `data` is not provided, then this command will perform a read and print the
+    resolution of the motion sensor. Otherwise, it will set the resolution to
+    the nearest `data` value depending on `roundup` being either `0` or `1`.
+  * `accelrate id [data [roundup]]` where the `id` is the sensor number. If
+    `data` is not provided, then this command will perform a read and print the
+    ODR of the motion sensor. Otherwise, it will set the ODR to the nearest
+    `data` value depending on `roundup` being either `0` or `1`.
+  * `accelread id [n]` where the `id` is the sensor number. If `n` is provided,
+    the sensor will be read `n` times. Otherwise, only a single read operation
+    will take place.
+* From the kernel root shell, test the following commands:
+  * `ectool motionsense` to print all the motion data.
+  * `ectool lid_angle` to verify that the rotation matrices are set correctly
+    for the lid and base accelerometers.
+  * See [ectool] for additional commands or run `ectool help motionsense`.
+
+## Example
+
+### Create the mutex
+
+The mutexes are created as child nodes of the `cros-ec,motionsense-mutex`
+compatible string.
+
+```
+motionsense-mutex {
+  compatible = "cros-ec,motionsense-mutex";
+  lid_mutex: lid-mutex {
+    label = "LID_MUTEX";
+  };
+};
+```
+
+### Create the rotation reference
+
+The rotation references are created as child nodes of the
+`cros-ec,motionsense-rotation-ref` compatible string.
+
+```
+motionsense-rotation-ref {
+  compatible = "cros-ec,motionsense-rotation-ref";
+  lid_rot_ref: lid-rotation-ref {
+    mat33 = <1 0 0
+             0 1 0
+             0 0 1>;
+  };
+};
+```
+
+### Create the sensor data
+
+Data structures are iterated by their compatible string and do not need to be
+clustered under a parent node (though they usually are).
+
+```
+bmi260_data: bmi260-drv-data {
+  compatible = "cros-ec,drvdata-bmi260";
+  status = "okay";
+};
+```
+
+### Create the sensor list
+
+The sensor list is created from the child nodes of the `motionsense-sensor`
+node.
+
+```
+motionsense-sensor {
+  lid_accel: lid-accel {
+    compatible = "cros-ec,bmi260-accel";
+    status = "okay";
+    label = "Lid Accel";
+    /* Set the active mask so this sensor will be on in both S0 and S3 */
+    active-mask = "SENSOR_ACTIVE_S0_S3";
+    /* Set the location of the sensor */
+    location = "MOTIONSENSE_LOC_LID";
+    /* Set the mutex (must be the same as the gyro) */
+    mutex = <&lid_mutex>;
+    /* Set the rotation reference */
+    rot-standard-ref = <&lid_rot_ref>;
+    /* Set the data for the driver (must be the same as the gyro) */
+    drv-data = <&bmi260_data>;
+  };
+  lid_gyro: lid-gyro {
+    compatible = "cros-ec,bmi260-gyro";
+    status = "okay";
+    label = "Lid Gyro";
+    active-mask = "SENSOR_ACTIVE_S0_S3";
+    location = "MOTIONSENSE_LOC_LID";
+    mutex = <&lid_mutex>;
+    rot-standard-ref = <&lid_rot_ref>;
+    drv-data = <&bmi260_data>;
+  };
+};
+```
+
+### Configuring the sensor
+
+Some additional configurations can be provided to the first node of a sensor.
+For example, in the above, the `lid_accel` can include a `configs` section which
+will allow the EC to automatically re-configure the sensor on various power
+levels. For example, the following will enable the lid accelerometer in both
+`S0` and `S3` and set the `ODR` to 10,000mHz or the nearest higher sample rate.
+
+```
+lid_accel: lid-accel {
+  ...
+  configs {
+    compatible = "cros-ec,motionsense-sensor-config";
+    ec-s0 {
+      label = "SENSOR_CONFIG_EC_S0";
+      odr = <(10000 | ROUND_UP_FLAG)>;
+    };
+    ec-s3 {
+      label = "SENSOR_CONFIG_EC_S3";
+      odr = <(10000 | ROUND_UP_FLAG)>;
+    };
+  };
+};
+```
+
+[MOTIONSENSE]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.motionsense;?q="config%20PLATFORM_EC_MOTIONSENSE"&ss=chromiumos
+[ACCEL FIFO]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.motionsense;?q="config%20PLATFORM_EC_ACCEL_FIFO"&ss=chromiumos
+[TIGHT TIMESTAMPS]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.motionsense;?q="config%20PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS"&ss=chromiumos
+[ALS]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.motionsense;?q="config%20PLATFORM_EC_ALS"&ss=chromiumos
+[DYNAMIC SENSOR COUNT]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.motionsense;?q="config%20PLATFORM_EC_DYNAMIC_MOTION_SENSOR_COUNT"&ss=chromiumos
+[LID ANGLE]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.motionsense;?q="config%20PLATFORM_EC_LID_ANGLE"&ss=chromiumos
+[ACCELS CMD]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.motionsense;?q="config%20PLATFORM_EC_CONSOLE_CMD_ACCELS"&ss=chromiumos
+[ACCEL SPOOF MODE]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.motionsense;?q="config%20PLATFORM_EC_ACCEL_SPOOF_MODE"&ss=chromiumos
+[ACCEL FIFO SIZE]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.motionsense;?q="config%20PLATFORM_EC_ACCEL_FIFO_SIZE"&ss=chromiumos
+[ACCEL FIFO THRES]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.motionsense;?q="config%20PLATFORM_EC_ACCEL_FIFO_THRES"&ss=chromiumos
+[ALS COUNT]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.motionsense;?q="config%20PLATFORM_EC_ALS_COUNT"&ss=chromiumos
+[LID ANGLE UPDATE]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.motionsense;?q="config%20PLATFORM_EC_LID_ANGLE_UPDATE"&ss=chromiumos
+[TABLET MODE]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.motionsense;?q="config%20PLATFORM_EC_TABLET_MODE"&ss=chromiumos
+[TABLET MODE SWITCH]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.motionsense;?q="config%20PLATFORM_EC_TABLET_MODE_SWITCH"&ss=chromiumos
+[GMR TABLET MODE]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.motionsense;?q="config%20PLATFORM_EC_GMR_TABLET_MODE"&ss=chromiumos
+[ACCEL INFO CMD]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.motionsense;?q="config%20PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO"&ss=chromiumos
+[ACCEL SPOOF CMD]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.motionsense;?q="config%20PLATFORM_EC_CONSOLE_CMD_ACCEL_SPOOF"&ss=chromiumos
+[MAX SENSOR FREQUENCY ]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.motionsense;?q="config%20PLATFORM_EC_MAX_SENSOR_FREQ_MILLIHZ"&ss=chromiumos
+[ectool]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/util/ectool.c;?q=function:ms_help&ss=chromiumos
diff --git a/docs/zephyr/zephyr_new_board_checklist.md b/docs/zephyr/zephyr_new_board_checklist.md
new file mode 100644
index 0000000000..4b3917581b
--- /dev/null
+++ b/docs/zephyr/zephyr_new_board_checklist.md
@@ -0,0 +1,73 @@
+# Creating a New Zephyr EC Project
+
+[TOC]
+
+## Overview
+
+This document describes the high-level steps needed to create a new Zephyr EC
+project for a Chromebook design.
+
+## Intended Audience
+
+This document is for use by software engineers working in the EC codebase. This
+document and the linked documents provide a guide for creating new Zephyr EC
+projects and for modifying/maintaining existing Zephyr EC projects.
+
+## How to use this document
+
+The following sections detail a single feature set that needs modification for
+your board design. Each feature set can be implemented with a reasonably sized
+change list, and can be worked on independently.
+
+Each feature includes the following sub-tasks:
+
+- **Kconfig Options** - This section details the `Kconfig` options relevant to
+  the feature. `Kconfig` options are enabled in one of the [project
+  configuration files].
+- **Devicetree Nodes** - This section details the devicetree nodes and
+  properties required by the feature. The [Zephyr Introduction to Devicetree]
+  provides a conceptual overview of devicetree and how Zephyr uses it.
+- **Board Specific Code** - When present, this section details any C code that
+  your project must implement.
+- **Threads** - This section details the threads created by the feature and
+  provides an overview of each thread.
+- **Testing and Debugging** - This section details strategies for testing the EC
+  feature set and for debugging issues. This section also documents EC console
+  commands related to the feature set.
+- **Example** - This section walks through a complete example for configuring an
+  EC feature based on existing board implementation.
+
+## Adding a new project to zmake
+
+Refer the [project configuration](project_config.md) documentation to add a new
+board project to zmake.
+
+## Configure EC Features
+
+The checklist below provides an overview of EC features that you must configure
+for correct operation of a Chromebook. The “Needed for Power On” column
+indicates the critical features needed during board bringup. Use the
+documentation link for details about the code changes required to implement each
+feature.
+
+EC Feature                                                                  | Needed for Power On
+:-------------------------------------------------------------------------- | :-----------------:
+[Configure EC Chipset (TODO)](./zephyr_template.md)                         | yes
+[Configure AP to EC Communication](./zephyr_ap_ec_comm.md)                  | yes
+[Configure AP Power Thresholds](./zephyr_ap_power.md)                       | yes
+[Configure AP Power Sequencing (TODO)](./zephyr_template.md)                | yes
+[Configure USB-A](./zephyr_usba.md)                                         | no
+[Configure USB-C (TODO)](./zephyr_template.md)                              | yes
+[Configure Charger (TODO)](./zephyr_template.md)                            | yes
+[Configure I2C Buses](./zephyr_i2c.md)                                      | yes
+[Configure GPIO](./zephyr_gpio.md)                                          | yes
+[Configure Batteries](./zephyr_battery.md)                                  | no
+[Configure CrOS Board Information (CBI)](./zephyr_cbi.md)                   | no
+[Configure Keyboard (TODO)](./zephyr_template.md)                           | no
+[Configure LEDs](./zephyr_leds.md)                                          | no
+[Configure Motion Sensors](./zephyr_motionsense.md)                         | no
+[Configure BC1.2 Charger Detector (TODO)](./zephyr_template.md)             | no
+[Configure ADC](./zephyr_adc.md)                                            | no
+[Configure Temperature Sensors](./zephyr_temperature_sensor.md)             | no
+
+[Zephyr Introduction to Devicetree]: https://docs.zephyrproject.org/latest/build/dts/intro.html
diff --git a/docs/zephyr/zephyr_pd.md b/docs/zephyr/zephyr_pd.md
new file mode 100644
index 0000000000..8b88d8c598
--- /dev/null
+++ b/docs/zephyr/zephyr_pd.md
@@ -0,0 +1,131 @@
+# Zephyr EC PD Configuration
+
+[TOC]
+
+## Overview
+
+Configure [USB-C] [PD] features that enables a port to provide power
+greater than the basic 5V @ 900mA. Power can be negotiated up to
+20V @ 5A.
+
+## Kconfig Options
+
+The `CONFIG_PLATFORM_EC_USB_POWER_DELIVERY` option enables USB-C power delivery
+support on the Chromebook. See [Kconfig.pd] for sub-options related to this feature.
+
+### Additional USB-C PD Configuration
+
+The behavior of the USB-C PD implementation is further controlled through the
+following options:
+
+1. VBUS Measurement - See [Kconfig.pd_meas_vbus]
+2. VBUS Detection - See [Kconfig.pd_vbus_detection]
+3. VBUS Discharge - [Kconfig.pd_discharge]
+4. Shared PD Interrupts - See [Kconfig.pd_int_shared]
+5. Fast Role Swap - See [Kconfig.pd_frs]
+6. Console Commands - See [Kconfig.pd_console_cmd]
+7. USBC Device Type - See [Kconfig.pd_usbc_device_type]
+
+## Devicetree
+
+Devicetree nodes that have their compatible property set to `named-usbc-port` are used to
+represent [USB-C] [PD] ports. For example, the follow two nodes represent the two [PD]
+ports on Herobrine, aptly named port0 and port1.
+
+```
+port0@0 {
+	compatible = "named-usbc-port";
+	reg = <0>;
+	bc12 = <&bc12_port0>;
+	ppc = <&ppc_port0>;
+	ppc_alt = <&ppc_port0_alt>;
+	tcpc = <&tcpc_port0>;
+	chg = <&charger>;
+	usb-mux-chain-0 {
+		compatible = "cros-ec,usb-mux-chain";
+		usb-muxes = <&usb_mux_0>;
+	};
+};
+usb_mux_0: usb-mux-0 {
+	compatible = "parade,usbc-mux-ps8xxx";
+};
+
+port1@1 {
+	compatible = "named-usbc-port";
+	reg = <1>;
+	bc12 = <&bc12_port1>;
+	ppc = <&ppc_port1>;
+	tcpc = <&tcpc_port1>;
+	usb-mux-chain-1 {
+		compatible = "cros-ec,usb-mux-chain";
+		usb-muxes = <&usb_mux_1>;
+	};
+};
+usb_mux_1: usb-mux-1 {
+	compatible = "parade,usbc-mux-ps8xxx";
+};
+
+&i2c1_0 {
+	ppc_port0: sn5s330@40 {
+		compatible = "ti,sn5s330";
+		status = "okay";
+		reg = <0x40>;
+	};
+
+	ppc_port0_alt: syv682x@41 {
+		compatible = "silergy,syv682x";
+		status = "okay";
+		reg = <0x41>;
+		frs_en_gpio = <&gpio_usb_c0_frs_en>;
+	};
+
+	tcpc_port0: ps8xxx@b {
+		compatible = "parade,ps8xxx";
+		reg = <0xb>;
+	};
+};
+
+&i2c2_0 {
+	ppc_port1: sn5s330@40 {
+		compatible = "ti,sn5s330";
+		status = "okay";
+		reg = <0x40>;
+	};
+
+	tcpc_port1: ps8xxx@b {
+		compatible = "parade,ps8xxx";
+		reg = <0xb>;
+	};
+};
+```
+
+Each port gets a `reg` property that is used to represent the port in the system. For example,
+`reg = <0>` for port0 and `reg = <1>` for port1. Also note that the `reg` value matches the
+value after the @ in the node name.
+
+The primary use of the port node is to describe what devices are connected to each port.
+For example, the `named-usbc-port` can include the following devices:
+* [BC12]
+* [PPC]
+* [TCPC]
+* [USB muxes and USB retimers]
+
+The two ports shown above both have the same four devices, but this is not required. Board
+designs may use different USB-C devices on each USB-C port.
+
+[USB-C]:../usb-c.md
+[PD]:../usb-c.md#pd
+[VBUS]:../ec_terms.md#vbus
+[FRS]:../ec_terms.md#frs
+[BC12]:../ec_terms.md#bc12
+[PPC]:../usb-c.md#ppc
+[TCPC]:../usb-c.md#tcpc
+[USB muxes and USB retimers]:../usb-c.md#ssmux
+[Kconfig.pd]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.pd
+[Kconfig.pd_int_shared]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.pd_int_shared
+[Kconfig.pd_meas_vbus]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.pd_meas_vbus
+[Kconfig.pd_frs]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.pd_frs
+[Kconfig.pd_discharge]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.pd_discharge
+[Kconfig.pd_vbus_detection]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.pd_vbus_detection
+[Kconfig.pd_console_cmd]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.pd_console_cmd
+[Kconfig.pd_usbc_device_type]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.pd_usbc_device_type
diff --git a/docs/zephyr/zephyr_poc_device_bringup.md b/docs/zephyr/zephyr_poc_device_bringup.md
new file mode 100644
index 0000000000..d28457ee36
--- /dev/null
+++ b/docs/zephyr/zephyr_poc_device_bringup.md
@@ -0,0 +1,54 @@
+# Zephyr Proof-of-Concept-Device Bringup
+
+It may be useful to build a Zephyr OS-based EC for a device which
+already has a CrOS EC device build, for the purposes of demonstrating
+the feasibility of Zephyr OS.
+
+This document is a work-in-progress list of tricks & tools that may be
+useful to you.
+
+## Initial Bringup
+
+Initially, you'll want to get a basic UART functioning with nothing
+but a shell and some basic console commands.
+
+An example CL to do this for Lazor can be found
+[here](https://crrev.com/c/2749765).
+
+## Bringing up GPIOs
+
+After you have UART functioning, GPIOs can be an easy target to start
+unblocking further features.
+
+We have a very ugly program to auto-generate the GPIO DTS based on
+gpio.inc for the existing board.  You can find it at
+`util/gpios_to_zephyr_dts.c`, and instructions are in the file on how
+to compile and use it.  You may have to hand-modify the output.
+
+The resultant CL for Lazor can be found [here](https://crrev.com/c/2749768).
+
+## Bring up Host Commands
+
+Set `CONFIG_PLATFORM_EC_HOSTCMD=y` and enable the appropriate
+host-command interface for your platform (e.g., eSPI).
+
+An example CL for Lazor can be found [here](https://crrev.com/c/2749428).
+
+As long as you get this compiling that should be enough to move to the
+next step.  Further testing of the host command layer will require
+power sequencing up and going.
+
+For further explanation, check [AP-EC communication](zephyr_ap_ec_comm.md) document.
+
+## Enabling some simple GPIO-based buttons and switches
+
+Next, you can:
+
+* [Add the lid switch](https://crrev.com/c/2749768)
+* [Add the power button](https://crrev.com/c/2749426)
+* [Add AC presence detection](https://crrev.com/c/2749428)
+
+## Power Sequencing
+
+TODO(jrosenth): add steps on enabling power sequencing and expand this
+document.
diff --git a/docs/zephyr/zephyr_ppc.md b/docs/zephyr/zephyr_ppc.md
new file mode 100644
index 0000000000..243a90780e
--- /dev/null
+++ b/docs/zephyr/zephyr_ppc.md
@@ -0,0 +1,69 @@
+# Zephyr EC PPC Configuration
+
+[TOC]
+
+## Overview
+
+Enable support for a [USB-C] [PPC].
+
+## Kconfig Options
+
+The Kconfig option `CONFIG_PLATFORM_EC_USBC_PPC` enables the selection of a [PPC].
+See the file [Kconfig.ppc] for all Kconfig options related to this feature.
+
+## Devicetree Nodes
+
+The `PPC` device tree nodes are defined in the [`DTS Bindings`] file for
+each type of `PPC` that extends [ppc-chip.yaml]. The `PPC` device is added
+to the corresponding I2C bus node and the "named-usbc-port" contains a
+phandle to the `PPC` device.
+
+## Board Specific Code
+
+None required.
+
+## Threads
+
+PPC support does not enable any threads.
+
+## Testing and Debugging
+
+The [`I2C bus scan`] can be used to verify the PPC device can be accessed and
+the `ppc_dump` console command can be used to dump the PPC register.
+
+```
+Usage: ppc_dump <USB-C port>
+```
+
+## Example
+
+The Hoglin system uses the Silergy SYV682X PPC on USBC port 0.
+
+```
+CONFIG_PLATFORM_EC_USBC_PPC=y
+CONFIG_PLATFORM_EC_USBC_PPC_SYV682X=y
+```
+
+```
+port0@0 {
+	compatible = "named-usbc-port";
+	reg = <0>;
+	ppc = <&ppc_port1>;
+};
+
+&i2c2_0 {
+	ppc_port1: syv682x@41 {
+		compatible = "silergy,syv682x";
+		status = "okay";
+		reg = <0x41>;
+		frs_en_gpio = <&gpio_usb_c1_frs_en>;
+	};
+};
+```
+
+[USB-C]: ../usb-c.md
+[PPC]: ../ec_terms.md#ppc
+[`I2C bus scan`]: ./zephyr_i2c.md#Shell-Command_i2c
+[Kconfig.ppc]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.ppc
+[`DTS Bindings`]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/dts/bindings/usbc/ppc
+[ppc-chip.yaml]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/dts/bindings/usbc/ppc-chip.yaml
diff --git a/docs/zephyr/zephyr_pwm.md b/docs/zephyr/zephyr_pwm.md
new file mode 100644
index 0000000000..89be759d4a
--- /dev/null
+++ b/docs/zephyr/zephyr_pwm.md
@@ -0,0 +1,131 @@
+# Zephyr EC PWM Configuration
+
+[TOC]
+
+## Overview
+
+[PWM] provides support for PWM setup and control on the platform.
+
+## Kconfig Options
+
+Kconfig Option | Default | Documentation
+:------------- | :------ | :------------
+`CONFIG_PWM` | n | [PWM (Pulse Width Modulation) Drivers]
+`CONFIG_PWM_<platform>` | n | Platform specific PWM driver
+
+Kconfig sub-option | Default | Documentation
+:----------------- | :------ | :------------
+`CONFIG_PLATFORM_EC_PWM_INIT_PRIORITY` | 51 | [Init priority of the PWM module]
+
+## Devicetree Nodes
+
+PWM channels are configured by enabling the PWM subsystem in the project
+`prj.conf`, setting a phandle reference to higher level driver `pwms` property,
+and enabling and configuring the corresponding PWM controller device node.
+
+For example for a keyboard backlight device:
+
+```
+kblight {
+        compatible = "cros-ec,kblight-pwm";
+        pwms = <&pwm3 0 PWM_HZ(2400) PWM_POLARITY_NORMAL>;
+};
+```
+
+Property | Description | Settings
+:------- | :---------- | :-------
+`pwms` | PWM phandle, identifies the controller (X), channel (Y) and flags. | `<&pwmX Y flags>`
+`frequency` | PWM frequency, in Hz | `integer (32 bit unsigned)`
+
+The `flags` cell of `pwms` defines the PWM signal properties, valid options are
+listed in the [dt-bindings/pwm/pwm.h], commonly used ones are
+`PWM_POLARITY_NORMAL` and `PWM_POLARITY_INVERTED`.
+
+Any used platform PWM device has to be explicitly enabled and configured, for example:
+
+```
+&pwm3 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK"; /* Keep active during low power mode. */
+};
+```
+
+The device node may include any platform specific property, see the
+corresponding bindings files for more details ([nuvoton,npcx-pwm],
+[ite,it8xxx2-pwm]).
+
+## Board Specific Code
+
+None required.
+
+## Threads
+
+PWM support does not enable any thread.
+
+## Testing and Debugging
+
+### Shell Command
+
+Zephyr defines a `pwm` shell command that can be used to change the current PWM
+duty cycle and period.
+
+The command is enabled by setting `CONFIG_PWM_SHELL=y` ([CONFIG_PWM_SHELL]) in the project `prj.conf` file.
+
+Command | Description | Usage
+:------ | :---------- | :----
+`pwm` | PWM shell commands | `pwm <cycles or usec or nsec> <device> <pwm> <period> <pulse> [flags]`
+
+Parameter | Description
+:-------- | :----------
+`cycles/usec/nsec` | The unit of period and pulse (cycles, microseconds or nanoseconds).
+`device` | The PWM device label (for example `PWM_1`).
+`pwm` | The PWM channel number.
+`period` | Requested period of the PWM signal.
+`pulse` | Requested active cycle duration of the PWM signal.
+`flags` | PWM flags (for example `1` for inverted polarity).
+
+For example to set the keyboard backlight (connected to PWM3) to 90%  at 250Hz on Volteer:
+
+`$ pwm usec PWM_3 0 250 225`
+
+## Features using PWM directly
+
+### Keyboard backlight
+
+Kconfig Option | Default | Documentation
+:------------- | :------ | :------------
+`PLATFORM_EC_PWM_KBLIGHT` | n | [PWM keyboard backlight]
+
+This requires defining a node with `compatible = "cros-ec,kblight-pwm"`,
+normally in a separate overlay `keyboard.dts` file, for example on the Volteer
+reference board:
+
+![PWM Example]
+
+The keyboard backlight line is connected to `PWM3` channel 0 (there's only one
+channel per PWM on NPCX), normal polarity:
+
+```
+/ {
+        kblight {
+                compatible = "cros-ec,kblight-pwm";
+                pwms = <&pwm3 0 PWM_HZ(2400) PWM_POLARITY_NORMAL>;
+        };
+};
+
+&pwm3 {
+        status = "okay";
+};
+```
+
+[PWM]: ../ec_terms.md#pwm
+[PWM (Pulse Width Modulation) Drivers]: https://docs.zephyrproject.org/latest/kconfig.html#CONFIG_PWM
+[PWM (Pulse Width Modulation) module]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig?q=%22config%20PLATFORM_EC_PWM%22
+[Init priority of the PWM module]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.init_priority?q=%22config%20PLATFORM_EC_PWM_INIT_PRIORITY%22
+[CONFIG_PWM_SHELL]: https://docs.zephyrproject.org/latest/kconfig.html#CONFIG_PWM_SHELL
+[PWM display backlight]:https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig?q=%22config%20PLATFORM_EC_PWM_DISPLIGHT%22
+[PWM keyboard backlight]:https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig?q=%22config%20PLATFORM_EC_PWM_KBLIGHT%22
+[dt-bindings/pwm/pwm.h]: https://github.com/zephyrproject-rtos/zephyr/blob/main/include/dt-bindings/pwm/pwm.h
+[PWM Example]: pwm_schematic.png
+[nuvoton,npcx-pwm]: https://github.com/zephyrproject-rtos/zephyr/blob/main/dts/bindings/pwm/nuvoton%2Cnpcx-pwm.yaml
+[ite,it8xxx2-pwm]: https://github.com/zephyrproject-rtos/zephyr/blob/main/dts/bindings/pwm/ite%2Cit8xxx2-pwm.yaml
diff --git a/docs/zephyr/zephyr_sensor_devices.md b/docs/zephyr/zephyr_sensor_devices.md
new file mode 100644
index 0000000000..3aa9e30b38
--- /dev/null
+++ b/docs/zephyr/zephyr_sensor_devices.md
@@ -0,0 +1,91 @@
+# Zephyr Sensor Devices
+
+[TOC]
+
+## Overview
+
+Zephyr provides a way to enable the legacy cros-ec sensor drivers. This is done
+through both enabling Kconfig options and adding nodes to the devicetree.
+
+## Kconfig Options
+
+Kconfig Option                          | Default | Documentation
+:-------------------------------------- | :-----: | :------------
+`CONFIG_PLATFORM_EC_ACCELGYRO_BMI160`   | n       | [BMI160]
+`CONFIG_PLATFORM_EC_ACCELGYRO_BMI260`   | n       | [BMI260]
+`CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX`   | n       | [BMI3XX]
+`CONFIG_PLATFORM_EC_ACCELGYRO_ICM426XX` | n       | [ICM426XX]
+`CONFIG_PLATFORM_EC_ACCELGYRO_ICM42607` | n       | [ICM42607]
+`CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSO`  | n       | [LSM6DSO]
+`CONFIG_PLATFORM_EC_ACCEL_BMA255`       | n       | [BMA255]
+`CONFIG_PLATFORM_EC_ACCEL_BMA4XX`       | n       | [BMA4XX]
+`CONFIG_PLATFORM_EC_ACCEL_KX022`        | n       | [KX022]
+`CONFIG_PLATFORM_EC_ACCEL_LIS2DW12`     | n       | [LIS2DW12]
+`CONFIG_PLATFORM_EC_ALS_TCS3400`        | n       | [TCS3400]
+
+### CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM choice
+
+The following choice is available only when one of the
+`CONFIG_PLATFORM_EC_ACCELGYRO_BMI*` configs are selected.
+
+Kconfig choice                              | Documentation
+:------------------------------------------ | :------------
+`CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_SPI` | [BMI COMM SPI]
+`CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C` | [BMI COMM I2C]
+
+### CONFIG_PLATFORM_EC_ACCELGYRO_ICM_COMM choice
+
+The following choice is available only when one of the
+`CONFIG_PLATFORM_EC_ACCELGYRO_ICM*` configs are selected.
+
+Kconfig choice                              | Documentation
+:------------------------------------------ | :------------
+`CONFIG_PLATFORM_EC_ACCELGYRO_ICM_COMM_SPI` | [ICM COMM SPI]
+`CONFIG_PLATFORM_EC_ACCELGYRO_ICM_COMM_I2C` | [ICM COMM I2C]
+
+## Devicetree Nodes
+
+*Detail the devicetree nodes that configure the feature.*
+
+*Note - avoid documenting node properties here.  Point to the relevant `.yaml`
+file instead, which contains the authoritative definition.*
+
+## Board Specific Code
+
+*Document any board specific routines that a user must create to successfully
+compile and run. For many features, this can section can be empty.*
+
+## Threads
+
+*Document any threads enabled by this feature.*
+
+## Testing and Debugging
+
+*Provide any tips for testing and debugging the EC feature.*
+
+## Example
+
+*Provide code snippets from a working board to walk the user through
+all code that must be created to enable this feature.*
+
+[BMI160]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.sensor_devices?q=%22config%20PLATFORM_EC_ACCELGYRO_BMI160%22&ss=chromiumos
+[BMI260]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.sensor_devices?q=%22config%20PLATFORM_EC_ACCELGYRO_BMI260%22&ss=chromiumos
+[BMI3XX]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.sensor_devices?q=%22config%20PLATFORM_EC_ACCELGYRO_BMI3XX%22&ss=chromiumos
+[BMI COMM SPI]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.accelgyro_bmi?q=%22config%20PLATFORM_EC_ACCELGYRO_BMI_COMM_SPI%22&ss=chromiumos
+[BMI COMM I2C]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.accelgyro_bmi?q=%22config%20PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C%22&ss=chromiumos
+
+[ICM426XX]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.sensor_devices?q=%22config%20PLATFORM_EC_ACCELGYRO_ICM426XX%22&ss=chromiumos
+[ICM42607]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.sensor_devices?q=%22config%20PLATFORM_EC_ACCELGYRO_ICM42607%22&ss=chromiumos
+[ICM COMM SPI]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.accelgyro_bmi?q=%22config%20PLATFORM_EC_ACCELGYRO_ICM_COMM_SPI%22&ss=chromiumos
+[ICM COMM I2C]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.accelgyro_bmi?q=%22config%20PLATFORM_EC_ACCELGYRO_ICM_COMM_I2C%22&ss=chromiumos
+
+[LSM6DSO]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.sensor_devices?q=%22config%20PLATFORM_EC_ACCELGYRO_LSM6DSO%22&ss=chromiumos
+
+[BMA255]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.sensor_devices?q=%22config%20PLATFORM_EC_ACCEL_BMA255%22&ss=chromiumos
+[BMA4XX]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.sensor_devices?q=%22config%20PLATFORM_EC_ACCEL_BMA4XX%22&ss=chromiumos
+
+[KX022]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.sensor_devices?q=%22config%20PLATFORM_EC_ACCEL_KX022%22&ss=chromiumos
+
+[LIS2DW12]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.sensor_devices?q=%22config%20PLATFORM_EC_ACCEL_LIS2DW12%22&ss=chromiumos
+
+[TCS3400]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.sensor_devices?q=%22config%20PLATFORM_EC_ALS_TCS3400%22&ss=chromiumos
diff --git a/docs/zephyr/zephyr_shim.md b/docs/zephyr/zephyr_shim.md
new file mode 100644
index 0000000000..3c6b48f209
--- /dev/null
+++ b/docs/zephyr/zephyr_shim.md
@@ -0,0 +1,381 @@
+[TOC]
+
+# Zephyr Shimming How-To
+
+## Objective
+
+Allow a subset of the platform/ec code to be built as part of the Zephyr-based
+EC without needing to land code into upstream zephyr, or our zephyr-chrome
+repository.
+
+## Background
+
+Now that Google has joined [Zephyr OS](https://www.zephyrproject.org/), the EC
+team is moving toward it instead of platform/ec code on embedded controllers for
+future Chrome OS devices. See the
+[originally proposed idea](https://goto.google.com/cros-ec-rtos) and a more
+specific [Zephyr process doc](https://goto.google.com/zephyr-structure) of what
+future development on Zephyr will look like.
+
+Simply put, we want to move to Zephyr OS to use an open-source embedded OS that
+has a vibrant community. The embedded OS scene for the industry is very
+fragmented, with various parties using their own custom solution. We see the
+strong open-source community at Zephyr as potentially helping to consolidate
+efforts in the embedded controller space. It will also benefit our partners
+(both chip vendors and OEMs) since they should only have to support one embedded
+OS (i.e., Zephyr) for both their Chrome OS and Windows based devices.
+
+Migrating to use Zephyr fully is going to take a few years. We do not want to
+diverge from the active development happening on platform/ec code. We
+potentially want to ship a product using Zephyr before the migration is
+complete.
+
+## Design ideas
+
+In order to reuse `platform/ec` development , we shim "active" `platform/ec`
+code as a
+[Zephyr Module](https://docs.zephyrproject.org/latest/guides/modules.html). This
+requires us to add some Zephyr specific code in a `zephyr` directory in the
+`platform/ec` codebase. Once we release a Zephyr-based EC, then we can turn down
+platform/ec for future development and work on migrating the platform/ec-module
+code out of the module directory and into a first-class Zephyr code format -- in
+the local
+[Chrome Zephyr repo](https://chromium.googlesource.com/chromiumos/platform/zephyr-chrome/+/HEAD)
+and ultimately [upstream](https://github.com/zephyrproject-rtos/zephyr).
+
+For platform/ec code that is stable and not under active development, the Zephyr
+team may port that code to Zephyr, thus skipping the shimming process.
+
+### Subsystems of interest
+
+#### With Shim
+
+We shim the following subsystems (non-exhaustive).
+
+*   USB-C: TCPC, PPC, MUX, TCPMv2
+*   Charge Manager
+*   SoC Power Sequencing
+*   Sensors, if Intel’s HID-based solution is delayed in getting to Zephyr
+    upstream
+
+#### Little-to-No Shim
+
+We adopt upstream Zephyr or skip the shimming process (non-exhaustive).
+
+*   CBI and dependent EEPROM code
+    *   The format is stable. We pull in the list of CBI tags from platform/ec
+        though
+*   EFS2, Vboot, RO/RW split
+    *   Adjusting flash layout would be difficult to shim, and the concept is
+        very stable.
+    *   We may shim some core EFS2 logic
+*   Host command framework
+*   Sensors, if Intel’s HID-based solution getts to Zephyr upstream and passes
+    CTS
+*   Keyboard and keycode scanning support
+    *   We may shim the newer Vivaldi feature.
+*   Console support
+    *   We allow individual console commands via DECLARE\_CONSOLE\_COMMAND to be
+        shimmed to Zephyr. These convert commands to work with Zephyr's shell
+        subsystem.
+*   I2C
+
+### New content in platform/ec
+
+Add the `src/platform/ec/zephyr` folder with:
+
+*   [Module integration files](https://docs.zephyrproject.org/latest/guides/modules.html#build-system-integration),
+    e.g., module.yml, CMakeLists.txt, and KConfig.
+    *   **module.yml** is the required entry point (must be located at
+        _zephyr/module.yml_ in the repository) for Zephyr modules, and declares
+        the location of Kconfig and CMakeLists.txt files used by the Zephyr
+        build system.
+    *   **CMakeLists.txt** replicates build logic for the files being shimmed,
+        outside of the platform/ec Makefile.
+    *   **Kconfig** will declare any CONFIG\_\* options which are important to
+        expose from platform/ec code to the Zephyr build.
+*   Shim code to translate platform/ec code into Zephyr code
+    *   For example, redefine platform/ec’s
+        [`DECLARE_HOST_COMMAND`](https://source.chromium.org/chromiumos/chromiumos/codesearch/+/HEAD:src/platform/ec/include/host_command.h;l=256;drc=514923bc59f5a3435dbb7cbf348735ed41889ffe)
+        to map to Zephyr's upstream
+        [`EC_HOST_CMD_HANDLER`](https://github.com/zephyrproject-rtos/zephyr/blob/d7468bf836b75c29980441f294a61eae6bf4bc75/include/ec_host_cmd.h#L73)
+        macro. This allows us to compile select platform/ec files in the Zephyr
+        build.
+
+### Namespace Collisions
+
+One significant issue of mixing Zephyr headers with our existing EC code is that
+we currently have many names colliding with the Zephyr code. For example,
+Zephyr's atomic functions also are named `atomic_add`, `atomic_or`, ...,
+however, have a different API from our EC's atomic functions. This is critical,
+since atomic operations are often used in `static inline` functions placed in
+header files.
+
+In some cases, we are able to hack around these collisions by creating macros
+and functions which are compatible with both Zephyr and our EC's usages. For
+example, we can create a modified `IS_ENABLED` which accepts both defined to
+nothing usages (CrOS EC `config.h` style), and defined to `1` usages (Zephyr
+Kconfig style).
+
+However, long term, we may find this to be a continual cause of issues, and
+creating hacks for every colliding macro or function may be unsustainable. We
+propose _gradually_ introducing a namespace prefix to the `platform/ec`
+codebase, for example `crec_`. We can begin at the critical areas of namespace
+collision (e.g., atomics) and continue to improve the naming convention with
+time.
+
+### New CQ check
+
+As long as code from platform/ec is part of the zephyr
+[ebuild](http://cs/chromeos_public/src/third_party/chromiumos-overlay/chromeos-base/chromeos-zephyr-2_3/chromeos-zephyr-2_3-9999.ebuild),
+then we need to run the Zephyr CQ checks on any platform/ec CLs in addition to
+the normal platform/ec CQ checks. This ensures that platform/ec changes aren’t
+breaking the Zephyr builds and requiring the Zephyr team to debug recent
+changes.
+
+For local builds, we can run `emerge-betty chromeos-zephyr-2_3` or `zmake`
+utility to check that an EC CL has not broken anything on the Zephyr side.
+
+We will work with the CI team to enable this.
+
+## How to shim features
+
+Before you get started shimming a feature, it's important to
+understand the general philosophies behind Zephyr OS and shimming:
+
+* Our current EC's OS isn't going away any time soon. Even after we
+  ship our first device with a Zephyr-based EC, we may still be working on
+  other projects using the old OS.  It's important to consider how
+  your feature will apply to both the Zephyr world and CrOS EC OS
+  world.
+
+* We won't be converting old devices to use Zephyr-based firmware.
+  This means that our existing OS and its code will need maintained
+  for bug and security fixes for years to come.  **Do not allow the
+  code you write for the CrOS EC OS to lack in quality or be "throw
+  away code" as it will need to be maintained for a long time.**
+
+* Shimming, by the very nature of the design, will lead to some ugly
+  hacks.  We try and avoid this when we can, but some of them may be
+  completely unavoidable.  This means we need to actively work against
+  nature to keep the code clean.  If we do things right, there's even
+  a possibility that we leave things cleaner than we found them.
+
+* Shimming occasionally digs up landmines.  Be prepared to step on
+  them. 💣
+
+### What code can be shimmed?
+
+Code in the `common/` directory (and other common code directories,
+like `power/`) is the ideal target for shimming, with the exception of
+core OS features which have Zephyr OS equivalents.
+
+Code in the following directories should **never be shimmed**:
+
+- `core/`: this directory contains architecture-specific code which
+  should have a Zephyr OS equivalent feature.
+
+- `chip/`: this directory contains chip-specific code, and similarly
+  should have a Zephyr OS equivalent feature.
+
+In both cases, you should instead determine (or, in rare cases,
+implement upstream) the equivalent Zephyr OS feature, and *implement
+an architecture and chip agnostic* "shim layer" in the `zephyr/shim/`
+directory which translates the APIs as necessary.
+
+As of the time of this document, the shim layer is nearing 100%
+complete, and it should be rare that you encounter an API which needs
+translation.
+
+Finally, code in the following directories should **avoid being
+shimmed, if possible**:
+
+- `board/`: this directory contains variant-specific code.
+
+- `baseboard/`: this directory contains baseboard-specific code.
+
+In both cases, the only value in shimming in code from one of those
+directories would be to enable a Zephyr OS build for a device which
+already has CrOS EC OS support, as *Zephyr-only projects will not have
+these directories*.  You should be thinking about how this would be
+implemented for a Zephyr-only project, and filing bugs to create the
+appropriate device-tree and Kconfig equivalents before shimming this
+code.
+
+See [Zephyr PoC device bringup](zephyr_poc_device_bringup.md) for more
+information about bringing up proof-of-concept devices.
+
+### Configuration
+
+CrOS EC OS uses a special header `config.h`, which sets configuration
+defaults, and includes board and chip specific configurations by
+expecting the headers `board.h` and `config_chip.h` to be present.
+Most of these configuration options start with `CONFIG_`, however the
+rules were loosely defined over the years.
+
+Zephyr OS, on the other hand, uses two different configuration
+systems:
+
+* Kconfig, the configuration system from the Linux Kernel, which
+  fits well within the domain of preprocessor definitions in C.  The
+  schema for our Kconfig files can be found under `zephyr/Kconfig`,
+  and project-specific configurations are made in `prj.conf` files.
+
+  Kconfig is generally used to select which EC software features are
+  enabled, and should be avoided for hardware configurations, such as
+  chip configuration registers and their default settings.
+
+* Open Firmware Device Tree, which you may also be familiar with from
+  the Linux kernel.  This configuration can be found in `*.dts` files.
+
+  Device-tree is generally used for hardware configurations, and
+  should be avoided for EC software feature configuration.
+
+For code which is shimmed, we need to play nicely with both the CrOS
+EC OS configuration system, and Zephyr's configuration systems.  Thus,
+we follow the following pattern:
+
+* EC software features are configured using `Kconfig` and
+  `zephyr/shim/include/config_chip.h` translates them into the
+  appropriate CrOS EC OS configurations using patterns such as below:
+
+  ```c
+  #undef CONFIG_CMD_GETTIME
+  #ifdef CONFIG_PLATFORM_EC_TIMER_CMD_GETTIME
+  #define CONFIG_CMD_GETTIME
+  #endif
+  ```
+
+  The preprocessor code should follow that template exactly, and not
+  use any nesting (Kconfig handles dependencies, there is no reason to
+  do it again in the preprocessor code).
+
+* **The domain of Kconfig options and CrOS EC configuration names
+  should be completely distinct.**  This is because the Kconfig options
+  are included automatically, and including `config.h` may undefine
+  them.  To mitigate this, we follow a convention of using
+  `CONFIG_PLATFORM_EC_` as the prefix for EC software features in
+  Kconfig.
+
+One special configuration option exists, `CONFIG_ZEPHYR`, which you
+can use to detect whether the OS is Zephyr OS.  This is the
+conventional way to add Zephyr-specific (or excluded) code in CrOS EC
+code.
+
+The typical EC macros for reducing `#ifdef` messes (e.g.,
+`IS_ENABLED`, `STATIC_IF`, etc.) work with both CrOS EC OS and Kconfig
+options, and should be used when possible.
+
+### Header Files
+
+Besides the include paths provided by Zephyr OS, the following paths
+are additionally added for shimmed code:
+
+* `include/`
+* `zephyr/include/`
+* `zephyr/shim/include/`
+
+The names of headers in these directories should be completely
+distinct.  C compilers have no mechanism for "include ordering", and
+there is no way to "override a header".
+
+If you feel the need to "override" a header, say `foo.h` in
+`include/`, the best way to do this is to give it a different name
+under `zephyr/shim/include` (e.g., `zephyr_foo_shim.h`), and include
+that in the `foo.h` header with a `#ifdef CONFIG_ZEPHYR` guard.
+
+The typical styling convention for includes (following existing
+conventions in `platform/ec` and other C codebases we have) is:
+
+* Zephyr OS headers in pointy brackets, in alphabetical order.
+
+* One blank line
+
+* CrOS EC OS headers (either from `include/`, `zephyr/shim/include/`,
+  or the current directory), in quotes (not pointy brackets).
+
+### Adding files to Cmake
+
+Zephyr's build system (including shimmed code) uses CMake instead of
+`Makefiles`, and your code will not be compiled for Zephyr unless you
+list the files in `zephyr/CMakeLists.txt`.
+
+### Step-by-step guide to adding a Kconfig
+
+Follow these steps:
+
+1. Make sure you have read the above Configuration section
+
+2. Add your config to one of zephyr/Kconfig* files. Note the PLATFORM_EC_ prefix
+   and try to put it near related things:
+
+  ```kconfig
+   config PLATFORM_EC_CHARGER_BQ25720
+     bool "TI BQ25720 charger"
+     help
+       The TI BQ25720 is a blah blah (describe summary from datasheet,
+       at least 3 lines so take 10 minutes to write something truly useful)
+  ```
+
+   Consider a `depends on PLATFORM_EC_...` line if it depends on an existing
+   feature.
+
+3. Add to zephyr/shim/include/config_chip.h (put it at the bottom):
+
+  ```kconfig
+   #undef CONFIG_CHARGER_BQ25720
+   #ifdef CONFIG_PLATFORM_EC_CHARGER_BQ25720
+   #define CONFIG_CHARGER_BQ25720
+   #endif
+  ```
+
+4. Add the source file to zephyr/CMakeLists.txt if it is not already there. For
+   ordering check the comments in that file:
+
+   `zephyr_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER_BQ25720
+                                     "${PLATFORM_EC}/driver/charger/bq25720.c")`
+
+5. Run a build on a board that enables the new CONFIG (in config.h) to make sure
+   there are no problems.
+
+6. If it doesn't work, please email zephyr-task-force@ or file a bug and assign
+   it to sjg@, cc zephyr-task-force@ (please include CL link and the error
+   output).
+
+### Unit Tests
+
+Unit tests, implemented using the Ztest framework, can be found in
+`zephyr/test`.
+
+To build all projects and run all unit tests, you use `zmake test --all`.
+
+## Alternatives Considered
+
+### Translate code and mirror into the zephyr-chrome repository
+
+We could potentially write a script which, via a series of find/replace
+operations, translates a platform/ec module to use Zephyr functions, macros, and
+paradigms. On a frequent basis, we would translate all modules of interest in
+the platform/ec repository and land an "uprev" change in the zephyr-chrome
+repository.
+
+The main disadvantage of this technique is that we can't get any CQ coverage
+when platform/ec CLs land that the modules will continue to work in Zephyr.
+Additionally, the translator script would be delicate and probably require
+frequent maintenance.
+
+However, this technique does have some benefits. With modules directly
+translated to code in the Zephyr paradigm, the process of upstreaming a shimmed
+module to ZephyrOS would be significantly easier. Additionally, it would require
+no shim code in platform/ec.
+
+### Don't do any code sharing
+
+One option is to avoid shimming in any platform/ec code and allow the Zephyr
+team to re-implement features in upstream zephyr, or our local zephyr-chrome
+repository.
+
+Disregarding the infeasible amount of work required to complete this option, the
+platform/ec repository has a far faster development pace as there are many more
+contributors, and the Zephyr features would quickly lose parity during the time
+frame that we are launching both Zephyr-based and platform/ec-based devices.
diff --git a/docs/zephyr/zephyr_ssfc.md b/docs/zephyr/zephyr_ssfc.md
new file mode 100644
index 0000000000..6a3fe079d3
--- /dev/null
+++ b/docs/zephyr/zephyr_ssfc.md
@@ -0,0 +1,104 @@
+# Zephyr CBI SSFC Configuration and Use.
+
+[TOC]
+
+## Overview
+
+Zephyr [`SSFC`] [`CBI Configuration`]
+
+## Kconfig Options
+
+The CrOS Board Information [`CBI`] feature is enabled with the
+CONFIG_PLATFORM_EC_CBI_EEPROM Kconfig, as defined in the [`CBI Configuration`].
+
+One of the [`CBI`] elements is the Second Source Factory Cache [`SSFC`] field.
+This config is used at run time to select different hardware options or behaviours, and
+is defined generally on a board by board basis.  The [`SSFC`] describes later decisions
+for a board to indicate alternate second sourced hardware stuffing
+which can be used by the EC to know which drivers to load.
+
+The [`SSFC`] block is limited to 32 bits. The 32 bits are divided into individual
+fields of varying sizes. Each field has defined values that may be set to control
+the behaviour according to the definition for that board.
+
+Device tree is used to define and specify the field sizes and values.
+
+## Devicetree Nodes
+
+The [`SSFC`] device tree nodes are defined via the [`cros-ec,cbi-ssfc`] and
+[`cros-ec,cbi-ssfc-value`] YAML bindings.
+
+The [`cros-ec,cbi-ssfc`] bindings define the name and size of each field.
+The [`cros-ec,cbi-ssfc-value`] bindings allow names/values to be defined for each
+value that may be stored in the field.
+One of the values may be designated as the default, which is used if
+the [`CBI`] data cannot be accessed.
+
+Spare [`CBI`] [`SSFC`] fields are always initialised as zeros, so that
+future fields will have a guaranteed value, so typically a zero
+value is used as a default, indicating the default field.
+
+An example definition is:
+```
+cbi-ssfc {
+    compatible = "cros-ec,cbi-ssfc";
+    base_sensor {
+        enum-name = "BASE_SENSOR";
+        size = <3>;
+        base_sensor_0: bmi160 {
+            compatible = "cros-ec,cbi-ssfc-value";
+            status = "okay";
+            value = <1>;
+        };
+    };
+    lid_sensor {
+        enum-name = "LID_SENSOR";
+        size = <3>;
+        lid_sensor_0: bma255 {
+            compatible = "cros-ec,cbi-ssfc-value";
+            status = "okay";
+            value = <1>;
+        };
+    };
+    lightbar {
+        enum-name = "LIGHTBAR";
+        size = <2>;
+        lightbar_0: 10_led {
+            compatible = "cros-ec,cbi-ssfc-value";
+            status = "okay";
+            value = <1>;
+        };
+    };
+};
+```
+
+## Board Specific Code
+
+To access the presence of an [`SSFC`] component, the [`CBI`] driver
+should be used to access the [`CBI`] API to check for an [`SSFC`] match e.g:
+
+```
+#include "cros_cbi.h"
+
+    bool is_base_sensor_bmi160(void)
+    {
+        return cros_cbi_ssfc_check_match(
+            CBI_SSFC_VALUE_ID(DT_NODELABEL(base_sensor_0)));
+    }
+```
+
+## Threads
+
+No threads used in this feature.
+
+## Testing and Debugging
+
+The [`ectool cbi`] command can be used to read and set the [`SSFC`].
+
+
+[`CBI`]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/design_docs/cros_board_info.md
+[`CBI Configuration`]: ./zephyr_cbi.md
+[`ectool cbi`]: ./zephyr_cbi.md#testing-and-debugging
+[`cros-ec,cbi-ssfc`]: ../../zephyr/dts/bindings/cbi/cros-ec,cbi-fw-config.yaml
+[`cros-ec,cbi-ssfc-value`]: ../../zephyr/dts/bindings/cbi/cros-ec,cbi-fw-config-value.yaml
+[`SSFC`]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/design_docs/firmware_config.md
diff --git a/docs/zephyr/zephyr_tcpc.md b/docs/zephyr/zephyr_tcpc.md
new file mode 100644
index 0000000000..d25ad26b34
--- /dev/null
+++ b/docs/zephyr/zephyr_tcpc.md
@@ -0,0 +1,65 @@
+# Zephyr EC TCPC Configuration
+
+[TOC]
+
+## Overview
+
+Enable support for a [USB-C] [TCPC].
+
+## Kconfig Options
+
+See the file [Kconfig.tcpm] for all Kconfig options related to [TCPC].
+You must enable the specific Kconfig option matching the TCPC chips
+used on your design.
+
+## Devicetree Nodes
+
+The `TCPC` device tree nodes are defined in the [`DTS Bindings TCPC`] directory.
+The `TCPC` device is added to the corresponding I2C bus node and the
+"named-usbc-port" contains a phandle to the `TCPC` device
+
+## Board Specific Code
+
+None required.
+
+## Threads
+
+TCPC support does not enable any threads.
+
+## Testing and Debugging
+
+The [`I2C bus scan`] can be used to verify the TCPC device can be accessed and
+the `tcpc_dump` console command can be used to dump the TCPC register.
+
+```
+Usage: tcpc_dump <USB-C port>
+```
+
+## Example
+
+The Herobrine system uses the Parade PS8805 TCPC on USBC port 0.
+
+```
+CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8805=y
+```
+
+```
+port0@0 {
+	compatible = "named-usbc-port";
+	reg = <0>;
+	tcpc = <&tcpc_port0>;
+};
+
+&i2c1_0 {
+	tcpc_port0: ps8xxx@b {
+		compatible = "parade,ps8xxx";
+		reg = <0xb>;
+	};
+};
+```
+
+[USB-C]: ../usb-c.md
+[TCPC]: ../ec_terms.md#tcpc
+[`I2C bus scan`]: ./zephyr_i2c.md#Shell-Command_i2c
+[Kconfig.tcpm]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.tcpm
+[`DTS Bindings TCPC`]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/dts/bindings/usbc/tcpc
diff --git a/docs/zephyr/zephyr_temperature_sensor.md b/docs/zephyr/zephyr_temperature_sensor.md
new file mode 100644
index 0000000000..7be5f5ccaf
--- /dev/null
+++ b/docs/zephyr/zephyr_temperature_sensor.md
@@ -0,0 +1,212 @@
+# Zephyr EC Temperature Sensors
+
+- [Zephyr EC Temperature Sensors](#zephyr-ec-temperature-sensors)
+	- [Overview](#overview)
+		- [Zephyr-supported Temperature Sensors](#zephyr-supported-temperature-sensors)
+			- [Supported Thermistor Configurations](#supported-thermistor-configurations)
+		- [Legacy EC Temperature Sensors](#legacy-ec-temperature-sensors)
+	- [Kconfig Options](#kconfig-options)
+	- [Device Tree Nodes](#device-tree-nodes)
+		- [Thermistors](#thermistors)
+			- [Thermistor Circuit](#thermistor-circuit)
+	- [Board-specific code](#board-specific-code)
+	- [Threads](#threads)
+		- [Thermistors](#thermistors-1)
+		- [I2C-based Sensors](#i2c-based-sensors)
+- [Testing and Debugging](#testing-and-debugging)
+
+## Overview
+Temperature sensors are critical for monitoring the operating temperature of
+the device and taking action if temperatures rise beyond safe levels by
+throttling or shutting down the AP.
+
+### Zephyr-supported Temperature Sensors
+
+| Part | File | Description |
+|---|---|---|
+| TMP112 | [driver/temp_sensor/tmp112.h](../../driver/temp_sensor/tmp112.h) | SMBus / I2C temperature sensor |
+| Thermistors | [driver/temp_sensor/thermistor.c](../../driver/temp_sensor/thermistor.c) | Various analog thermistor configurations |
+
+#### Supported Thermistor Configurations
+
+   * `thermistor_3V3_30K9_47K_4050B`
+   * `thermistor_3V0_22K6_47K_4050B`
+   * `thermistor_3V3_13K7_47K_4050B`
+   * `thermistor_3V3_51K1_47K_4050B`
+
+See [zephyr/include/cros/thermistor/thermistor.dtsi](../../zephyr/include/cros/thermistor/thermistor.dtsi)
+and [zephyr/test/drivers/overlay.dts](../../zephyr/test/drivers/overlay.dts)
+to see where these are defined.
+
+### Legacy EC Temperature Sensors
+These models have drivers written for the legacy EC code, but would need
+further work to adapt to Zephyr.
+
+| Part # | File | Description |
+|---|---|---|
+| ADT7481 | [driver/temp_sensor/adt7481.h](../../driver/temp_sensor/adt7481.h) | SMBus / I2C 3-channel temperature sensor (local + 2x remote) |
+| R19ME4070 | [driver/temp_sensor/amd_r19me4070.h](../../driver/temp_sensor/amd_r19me4070.h) | AMD GPU, but has an onboard temperature sensor. |
+| BD99992GW | [driver/temp_sensor/bd99992gw.h](../../driver/temp_sensor/bd99992gw.h) | This is a PMIC, but has an onboard temp sensor. |
+| F75303 | [driver/temp_sensor/f75303.h](../../driver/temp_sensor/f75303.h) | SMBus / I2C 3-channel temperature sensor (local + 2x remote) |
+| G781/G782 | [driver/temp_sensor/g78x.h](../../driver/temp_sensor/g78x.h) | SMBus / I2C 2-channel temperature sensor (local + remote) |
+| G753 | [driver/temp_sensor/g753.h](../../driver/temp_sensor/g753.h) | SMBus / I2C single-channel temperature sensor |
+| OTI502 | [driver/temp_sensor/oti502.h](../../driver/temp_sensor/oti502.h) | I2C ambient plus infrared temperature sensor |
+| PCT2075 | [driver/temp_sensor/pct2075.h](../../driver/temp_sensor/pct2075.h) | I2C temperature sensor |
+| SB-TSI | [driver/temp_sensor/sb_tsi.h](../../driver/temp_sensor/sb_tsi.h) | I2C temp sensor on the AMD Stony Ridge FT4 SOC |
+| NCP15WB | [driver/temp_sensor/thermistor_ncp15wb.c](../../driver/temp_sensor/thermistor_ncp15wb.c) | NTC thermistor (used with ADC) |
+| TMP006 | [driver/temp_sensor/tmp006.h](../../driver/temp_sensor/tmp006.h) | SMBus / I2C infrared temperature sensor |
+| TMP112 | [driver/temp_sensor/tmp112.h](../../driver/temp_sensor/tmp112.h) | SMBus / I2C temperature sensor |
+| TMP411 | [driver/temp_sensor/tmp411.h](../../driver/temp_sensor/tmp411.h) | SMBus / I2C 2-channel temperature sensor (local + remote) |
+| TMP432 | [driver/temp_sensor/tmp432.h](../../driver/temp_sensor/tmp432.h) | SMBus / I2C 2-channel temperature sensor (local + remote) |
+| TMP468 | [driver/temp_sensor/tmp468.h](../../driver/temp_sensor/tmp468.h) | SMBus / I2C 9-channel temperature sensor (local + 8x remote) |
+
+## Kconfig Options
+
+Overall support for temperature sensors is enabled using the config flag
+`PLATFORM_EC_TEMP_SENSOR`. See [zephyr/Kconfig.temperature](../../zephyr/Kconfig.temperature)
+for more information. A separate config flag, `PLATFORM_EC_THERMISTOR`, is needed
+if analog thermistor sensors are being used. This option is dependent on ADCs
+being supported. These flags are configured in each board’s `prj.conf` file.
+
+There are no sensor-specific Kconfig options for specifying sensor types,
+drivers, or configuration. This is handled by the device tree (see below)
+on Zephyr-based boards.
+
+## Device Tree Nodes
+
+Temperature sensors are declared as separate nodes and additional properties are
+defined by the `cros-ec,temp-sensors` node in the device tree. This example is
+from [zephyr/program/brya/temp_sensors.dts](../../zephyr/program/brya/temp_sensors.dts):
+
+```
+	temp_ddr_soc: ddr_soc {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_30K9_47K_4050B>;
+		adc = <&adc_ddr_soc>;
+	};
+
+	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
+		ddr_soc {
+			temp_fan_off = <35>;
+			temp_fan_max = <60>;
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			sensor = <&temp_ddr_soc>;
+		};
+```
+
+More information about temperature sensor device tree settings can be found in the
+following locations:
+
+ * [cros_ec_temp_sensor.yaml](../../zephyr/dts/bindings/temp/cros_ec_temp_sensor.yaml) - Common properties
+ * [cors_ec_temp_sensor_thermistor.yaml](../../zephyr/dts/bindings/temp/cors_ec_temp_sensor_thermistor.yaml) - Special properties for analog thermistors
+ * [cros_ec_temp_sensor_tmp112.yaml](../../zephyr/dts/bindings/temp/cros_ec_temp_sensor_tmp112.yaml) - Properties for the TMP112 I2C-based sensor
+
+### Thermistors
+
+In addition to setting up the sensors, each type of supported thermistor needs to
+have calibration data saved in the device tree that is used to compute temperature
+values from the ADC counts / measured voltages. Example from
+[zephyr/include/cros/thermistor/thermistor.dtsi](../../zephyr/include/cros/thermistor/thermistor.dtsi).
+
+This must only be done once for each type of thermistor. Most boards should be
+covered by one of the existing types and can simply reference them in the device
+tree named-temp-sensors nodes.
+
+```
+	thermistor_3V3_30K9_47K_4050B: thermistor-3V3-30K9-47K-4050B {
+		status = "disabled";
+		compatible = "cros-ec,thermistor";
+		scaling-factor = <11>;
+		num-pairs = <10>;
+		steinhart-reference-mv = <3300>;
+		steinhart-reference-res = <30900>;
+		/*
+		 * Data derived from Steinhart-Hart equation in a resistor
+		 * divider circuit with Vdd=3300mV, R = 30.9Kohm, and thermistor
+		 * (B = 4050, T0 = 298.15 K, nominal resistance (R0) = 47Kohm).
+		 */
+		sample-datum-0 {
+			milivolt = <(2753 / 11)>;
+			temp = <0>;
+			sample-index = <0>;
+		};
+		sample-datum-1 {
+			milivolt = <(2487 / 11)>;
+			temp = <10>;
+			sample-index = <1>;
+		};
+		/* . . . */
+```
+
+#### Thermistor Circuit
+
+Type `thermistor_3V3_30K9_47K_4050B` corresponds to this circuit:
+
+![Schematic of a thermistor voltage divider](thermistor_schematic.png)
+
+The thermistor naming scheme is as follows:
+ * `3V3` - The voltage divider is supplied from a 3.3V rail.
+ * `30K9` - The high side of the voltage divider is a 30.9K ohm resistor.
+ * `47K` - The nominal thermistor resistance (R_0) is 47K ohm.
+ * `4050B` - Coefficient B in the Steinhart–Hart thermistor equation is 4050.
+
+## Board-specific code
+
+No board-specific code is required. Temperature sensors are automatically configured
+based on information in the device tree.
+
+## Threads
+
+There is no dedicated thread for monitoring temperature sensors. The sensor data is
+ultimately consumed by the thermal engine’s `thermal_control()` function in
+[common/thermal.c](../../common/thermal.c), which runs every second in the TICK
+thread by registering it as a callback with the Hook API.
+
+The mechanism for pulling in temperature data depends on the type of sensor:
+
+### Thermistors
+
+Thermistor-based temperature sensor readings are measured and processed on-the-fly
+whenever requested, so the TICK thread reads from the ADC directly during the
+`thermal_control()` routine.
+
+### I2C-based Sensors
+
+Most I2C-based sensors involve an extra step. Their drivers separately set up an
+internal function to run on a one second interval (also on the TICK task using the
+Hook API). For example, the TMP006 does this in [tmp006.c](../../driver/temp_sensor/tmp006.c):
+
+```c
+static void tmp006_poll(void)
+{
+	int i;
+
+	for (i = 0; i < TMP006_COUNT; ++i)
+		tmp006_poll_sensor(i);
+}
+DECLARE_HOOK(HOOK_SECOND, tmp006_poll, HOOK_PRIO_TEMP_SENSOR);
+```
+
+The poll function only updates an internal struct within the driver with the latest
+reading(s). These values then get read by the thermal engine through the same,
+standard API as the thermistors. This spares the thermal routine from having to
+wait on I2C accesses.
+
+However, not all temperature sensor drivers follow this approach. For instance,
+the [SB-TSI driver](../../driver/temp_sensor/sb_tsi.c) simply performs the I2C
+transaction to read the temperature directly in the public `sb_tsi_get_val()`
+function.
+
+# Testing and Debugging
+
+Temperature sensors can be queried with the `temps` console command:
+
+```
+> temps
+  Charger             : 303 K = 30 C
+  SOC                 : 303 K = 30 C
+  CPU                 : 301 K = 28 C
+```
diff --git a/docs/zephyr/zephyr_template.md b/docs/zephyr/zephyr_template.md
new file mode 100644
index 0000000000..f36c9f90da
--- /dev/null
+++ b/docs/zephyr/zephyr_template.md
@@ -0,0 +1,57 @@
+# Zephyr EC Feature Configuration Template
+
+[TOC]
+
+## Overview
+
+*Description of the Zephyr EC feature and the capabilities provided*
+
+## Kconfig Options
+
+*Link to the file providing all the Kconfig options related to the feature.  If
+the Kconfig options are not currently in a standalone file, consider moving the
+related Kconfigs into their own file.*
+
+*Example CL moving I2C related configs into a new file: https://crrev.com/c/3575081*
+
+*Note - Avoid documenting `CONFIG_` options in the markdown as the relevant
+`Kconfig*` contains the authoritative definition. If there is one main Kconfig
+that must be enabled for the feature, mention it in this section. See the [I2C
+documentation](zephyr_i2c.md#kconfig-options) for an example.*
+
+*If the `Kconfig` file does not provide sufficient help descriptions, please fix
+them.*
+
+## Devicetree Nodes
+
+*Detail the devicetree nodes that configure the feature.*
+
+*Note - avoid documenting node properties here.  Point to the relevant `.yaml`
+file instead, which contains the authoritative definition.*
+
+## Board Specific Code
+
+*Document any board specific routines that a user must create to successfully
+compile and run. For many features, this can section can be empty.*
+
+## Threads
+
+*Document any threads enabled by this feature.*
+
+## Testing and Debugging
+
+*Provide any tips for testing and debugging the EC feature.*
+
+*It's especially helpful to document EC console commands and `ectool` commands
+from the AP in this section.  Please provide example output.*
+
+## Example
+
+*Provide code snippets from a working board to walk the user through
+all code that must be created to enable this feature.*
+
+<!--
+The following demonstrates linking to a code search result for a Kconfig option.
+Reference this link in your text by matching the text in brackets exactly.
+-->
+[I2C Passthru Restricted]:https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig?q=%22config%20PLATFORM_EC_I2C_PASSTHRU_RESTRICTED%22&ss=chromiumos
diff --git a/docs/zephyr/zephyr_troubleshooting.md b/docs/zephyr/zephyr_troubleshooting.md
new file mode 100644
index 0000000000..3f3cc508cc
--- /dev/null
+++ b/docs/zephyr/zephyr_troubleshooting.md
@@ -0,0 +1,237 @@
+# Zephyr Troubleshooting
+
+[TOC]
+
+## Devicetree
+
+The devicetree is made out of different dts and dtsi files, gets aggregated
+into a single `zephyr.dts` file and generates a `devicetree_generated.h` header
+with all the definitions used by the `DT_` macros.
+
+The build system lists the various overlay files specified by `BUILD.py`, for
+example:
+
+```
+-- Found devicetree overlay: /mnt/host/source/src/platform/ec/zephyr/program/brya/adc.dts
+-- Found devicetree overlay: /mnt/host/source/src/platform/ec/zephyr/program/brya/battery.dts
+-- Found devicetree overlay: /mnt/host/source/src/platform/ec/zephyr/program/brya/cbi_eeprom.dts
+-- Found devicetree overlay: /mnt/host/source/src/platform/ec/zephyr/program/brya/fan.dts
+...
+```
+
+Useful artifacts (always present):
+
+Aggregated devicetree file, after all the overlays, preprocessor and
+`gen_defines.py`:
+
+```
+build/zephyr/$PROJECT/build-ro/zephyr/zephyr.dts
+```
+
+Main devicetree output, flat representation of the tree and various node
+references, including ordinals of `dts_ord_...` structs:
+
+```
+./build/zephyr/$PROJECT/build-ro/zephyr/include/generated/devicetree_generated.h
+```
+
+For more details see: [CMake configuration phase](https://docs.zephyrproject.org/latest/build/cmake/index.html?highlight=gen_defines%20py#configuration-phase)
+
+## Node nomenclature
+
+```
+/ {
+        a-node {
+                subnode_nodelabel: a-sub-node {
+                        foo = <3>;
+                        label = "SUBNODE";
+                };
+        };
+};
+```
+
+- `/` is the root node
+- `a-node` and `a-sub-node` are node names
+- `subnode_nodelabel` is a nodelabel
+- `foo` is a property, `3` is the value
+- `label` is a property, `SUBNODE` is the value
+
+NOTE: `subnode_nodelabel` is a nodelabel, `label` is a label property.
+
+## Adding multiple nodelabels
+
+Code can have hardcoded nodelables, so sometimes it's useful to add extra
+nodelabels to an existing node (referenced by another nodelabel). To do that
+add an overlay with something similar to:
+
+```
+another_node_label: &subnode_nodelabel {
+};
+```
+
+## Undefined reference to \_\_device\_dts\_ord\_...
+
+This happens when some code refer to a device using `DT_DEVICE_GET`, but the
+corresponding `struct device` is not instantiated, either because the driver
+has not been enabled or because of a devicetree misconfiguration (missing
+`status = "okay"`).
+
+Quick fix: find what device is causing the issue (look into
+`devicetree_generated.h`) enable the corresponding driver (CONFIG_...=y) or fix
+the devicetree.
+
+Proper fix: find the code referencing to the undefined node, make sure that the
+corresponding Kconfig option depends on the subsystem being enabled (ADC,
+I2C...), make sure that the specific platform driver is enabled based on the
+devicetree (`default y` and `depends on DT_HAS_...`).
+
+## error: 'CONFIG_..._LOG_LEVEL' undeclared
+
+The `CONFIG_..._LOG_LEVEL` symbols are not defined directly (i.e. there's no
+Kconfig `config ..._LOG_LEVEL`), they are generated using the
+`subsys/logging/Kconfig.template.log_config` template.
+
+Quick fix: enable the logging subsystem (normally `CONFIG_LOG=y`
+`CONFIG_LOG_MODE_MINIMAL=y` in the project `prj.conf`), or change the code so
+that the driver builds without this config.
+
+Fix: make the driver depends on the logging subsystem being enabled (`depends
+on LOG`) or change the code to compile with `CONFIG_LOG=n`.
+
+## Menuconfig
+
+Sometimes it's useful to run the `menuconfig` target on a specific project,
+this can be done with:
+
+```
+ninja -C build/zephyr/$PROJECT/build-ro menuconfig
+```
+
+This exposes all the available options from the various Kconfig fragments and
+can be useful to validate that config constraints are working correctly.
+
+For example, searching for `^SSHELL$` (using the `/` key) shows:
+
+```
+Name: SHELL
+Prompt: Shell
+Type: bool
+Value: y
+
+Symbols currently n-selecting this symbol (no effect):
+...
+
+Symbols currently y-implying this symbol:
+  - CROS_EC
+  - PLATFORM_EC
+```
+
+## LTO
+
+Many compiler and linker error are very uninformative if LTO is enabled, for
+example a missing `struct device` can show as
+
+```
+/tmp/ccCiGy7c.ltrans0.ltrans.o:(.rodata+0x6a0): undefined reference to `__device_dts_ord_75'
+```
+
+Adding `CONFIG_LTO=n` to the corresponding `prj.conf` or building with `zmake
+build <project> -DCONFIG_LTO=n` usually results in more useful error messages,
+for example:
+
+```
+modules/ec/libec_shim.a(adc.c.obj):(.rodata.adc_channels+0x58): undefined reference to `__device_dts_ord_75'
+```
+
+## Macro Error Expansion
+
+GCC errors on macros include macro expansion by default. This usually results
+in a wall of errors that makes it very hard to identify the actual problem. For
+these situations it's useful to disable macro expansion entirely by setting
+`CONFIG_COMPILER_TRACK_MACRO_EXPANSION=n`, for example by building with:
+
+`zmake build <project> -DCONFIG_COMPILER_TRACK_MACRO_EXPANSION=n`
+
+## Build artifacts
+
+The buildsystem can be configured to leave the build artifact next to the
+object files, this is useful to inspect the macro output. To do that use the
+`zmake` flag:
+
+```
+zmake build --save-temps $PROJECT
+```
+
+or for unit tests:
+
+```
+./twister -x=CONFIG_COMPILER_SAVE_TEMPS=y
+```
+
+This leaves a bunch of `.i` files in the build/ directory.
+
+For more information see: [Look at the preprocessor output](https://docs.zephyrproject.org/latest/build/dts/troubleshooting.html?highlight=save%20temps#look-at-the-preprocessor-output).
+
+This is also useful to analyze assembly errors, for example
+
+```
+/tmp/cctFuB4N.s: Assembler messages:
+/tmp/cctFuB4N.s:1869: Error: missing expression
+```
+
+becomes
+
+```
+zephyr/CMakeFiles/zephyr.dir/misc/generated/configs.c.s: Assembler messages:
+zephyr/CMakeFiles/zephyr.dir/misc/generated/configs.c.s:1869: Error: missing expression
+```
+
+## Statically initialized objects
+
+The `zephyr.elf` output file can be used with gdb to analyze all the statically
+allocated structures, for example:
+
+```
+$ arm-none-eabi-gdb build/zephyr/$PROJECT/output/zephyr-ro.elf
+(gdb) p fan_config
+$1 = {{pwm = {dev = 0x100ad244 <__device_dts_ord_169>, channel = 0, period = 1000000, flags = 0}, tach = 0x100ad43c <__device_dts_ord_172>}}
+(gdb) p __device_dts_ord_172.name
+$3 = 0x100ba480 "tach@400e1000"
+```
+
+If the symbol has been optimized, try rebuilding with `CONFIG_LTO=n`.
+
+
+## Using GDB for debugging unit tests
+
+Unit tests running on `native_posix` produce an executable file that can be
+rebuilt directly with ninja to save time, and run with GDB to help out
+debugging. This can be found after a twister run in the `twister-out`
+directory. For example:
+
+```
+$ ./twister -v -T zephyr/test/hooks
+...
+INFO - 1/1 native_posix hooks.default PASSED (native 0.042s)
+...
+
+# Modify the test code
+
+$ ninja -C twister-out/native_posix/hooks.default
+...
+[7/7] Linking C executable zephyr/zephyr.elf
+
+$ ./twister-out/native_posix/hooks.default/zephyr/zephyr.elf
+...
+PROJECT EXECUTION SUCCESSFUL
+
+$ gdb ./twister-out/native_posix/hooks.default/zephyr/zephyr.elf
+Reading symbols from ./twister-out/native_posix/hooks.default/zephyr/zephyr.elf...
+(gdb) b main
+Breakpoint 1 at 0x80568a9: file boards/posix/native_posix/main.c, line 112.
+(gdb) run
+Starting program: /mnt/host/source/src/platform/ec/twister-out/native_posix/hooks.default/zephyr/zephyr.elf
+Breakpoint 1, main (argc=-17520, argv=0xffffbc24) at boards/posix/native_posix/main.c:112
+112             posix_init(argc, argv);
+...
+```
diff --git a/docs/zephyr/zephyr_usba.md b/docs/zephyr/zephyr_usba.md
new file mode 100644
index 0000000000..ce66125905
--- /dev/null
+++ b/docs/zephyr/zephyr_usba.md
@@ -0,0 +1,78 @@
+# Zephyr USBA Configuration
+
+[TOC]
+
+## Overview
+
+[USBA] is used to configure the number of USB Type-A ports in the system and
+optional control of the power supplied by said ports.
+
+## Kconfig Options
+
+`CONFIG_PLATFORM_EC_USBA` enables support for USB-A ports in the EC application.
+Refer to [Kconfig.usba] for all sub-options controlling USB-A ports.
+
+## Devicetree Nodes
+
+By default, for each USB Type-A port, a GPIO pin is required to control when power
+is supplied to the port. The GPIO pins are described in Device Tree nodes.
+
+Refer to the [named-gpios.yaml] and [cros-ec,usba-port-enable-pins.yaml] child-binding
+files for details about gpio properties.
+
+## Board Specific Code
+
+none
+
+## Threads
+
+When `CONFIG_PLATFORM_EC_USB_PORT_POWER_DUMB=y`, then the EC application automatically
+powers up USB-A ports when the AP chipset starts up and powers off the USB-A ports
+when the AP chipset shuts down.
+
+## Testing and Debugging
+
+Use the  gpioset  console command to manually enable and disable the USB Type-A port power.
+
+`gpioset` usage: gpioset <pin_name> <0 | 1>
+
+The `usbchargemode` console command is used to enable and disable charging
+from the USB Type-A port.
+
+* For dumb power ports: `usbchargemode` <port>  <on | off>
+* For smart power ports: `usbchargemode` <port> <0 | 1 | 2 | 3> <0 | 1>
+
+Charging from USB Type-A ports can be controlled from the AP using  ectool `usbchargemode`.
+
+`ectool usbchargemode` <port> <disabled | SDP | CDP | DCP> [inhibit_charge]
+
+Refer to the Application Processor to EC communication for more information about using[ ectool].
+
+## Example
+
+The Herobrine board has one USB Type-A port:
+
+The following configures the project for one port.
+
+```
+`CONFIG_PLATFORM_EC_USB_PORT_POWER_DUMB=y`
+```
+
+The following device tree node configures the gpio pin.
+
+```
+gpio_en_usb_a_5v: en_usb_a_5v {
+	gpios = <&gpiof 0 GPIO_OUT_LOW>;
+};
+
+usba-port-enable-list {
+	compatible = "cros-ec,usba-port-enable-pins";
+	enable-pins = <&gpio_en_usb_a_5v>;
+};
+```
+
+[USBA]: ../ec_terms.md#usba
+[Kconfig.usba]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.usba
+[named-gpios.yaml]: ../../zephyr/dts/bindings/gpio/named-gpios.yaml
+[cros-ec,usba-port-enable-pins.yaml]: ../../zephyr/dts/bindings/gpio/cros-ec,usba-port-enable-pins.yaml
+[ectool]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/util/ectool.c;?q=function:ms_help&ss=chromiumos
diff --git a/docs/zephyr/zephyr_usbc.md b/docs/zephyr/zephyr_usbc.md
new file mode 100644
index 0000000000..2d1f337261
--- /dev/null
+++ b/docs/zephyr/zephyr_usbc.md
@@ -0,0 +1,67 @@
+# Zephyr EC USBC Configuration
+
+[TOC]
+
+## Overview
+
+[USB-C] is a flexible connector supporting multiple data rates, protocols, and
+power in either direction.
+
+From the system, USB PD requires a complex state machine as USB PD can
+operate in many different modes. This includes but isn't limited to:
+
+*   Negotiated power contracts. Either side of the cable can source or sink
+    power up to 240W (if supported by device).
+*   Reversed cable mode. This requires a mux to switch the signals before
+    getting to the SoC (or AP).
+*   Debug accessory mode, e.g. [Case Closed Debugging (CCD)]
+*   Multiple uses for the 4 differential pair signals including
+    *   USB SuperSpeed mode (up to 4 lanes for USB data)
+    *   DisplayPort Alternate Mode (up to 4 lanes for DisplayPort data)
+    *   Dock Mode (2 lanes for USB data, and 2 lanes for DisplayPort)
+    *   USB4/Thunderbolt mode. (4 lanes for USB data)
+
+For a more complete list of USB-C Power Delivery features, see the
+[USB-C PD spec][USB PD Spec Id].
+
+The image below shows a block diagram of a typical [USB-C] setup.
+
+![USBC Block Diagram]
+# Legend
+## See the [EC Acronyms and Technologies]
+*   [AP]
+*   [EC]
+*   [PPC]
+*   [TCPC]
+*   [USB-C Mux]
+*   [Retimer]
+
+## Kconfig Options
+
+The `CONFIG_PLATFORM_EC_USBC` option enables USB-C support on the Chromebook.
+See [Kconfig.usbc] for sub-options related to this feature.
+
+The following sub-components must be configured for correct operation of USB-C:
+*   [Zephyr EC Type-C Port Controller]
+*   [Zephyr EC PPC Configuration]
+*   [Zephyr EC SS Mux and Retimer Configuration]
+*   [Zephyr EC Charger Configuration]
+*   [Zephyr EC Power Delivery Configuration]
+
+[USB-C]:../usb-c.md
+[EC Acronyms and Technologies]:../ec_terms.md
+[AP]:../ec_terms.md#ap
+[EC]:../ec_terms.md#ec
+[PPC]:../ec_terms.md#ppc
+[TCPC]:../ec_terms.md#tcpc
+[USB-C Mux]:../ec_terms.md#ssmux
+[Retimer]:../ec_terms.md#retimer
+[USBC Block Diagram]:../images/usbc_block_diagram.png
+[USB PD Spec Id]: https://www.usb.org/document-library/usb-power-delivery
+[Kconfig.usbc]:
+https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.usbc
+[Zephyr EC Power Delivery Configuration]:zephyr_pd.md
+[Zephyr EC PPC Configuration]:zephyr_ppc.md
+[Zephyr EC SS Mux and Retimer Configuration]:zephyr_usbc_ss_mux_and_retimer.md
+[Zephyr EC Charger Configuration]:zephyr_charger.md
+[Zephyr EC Type-C Port Controller]:zephyr_tcpc.md
diff --git a/docs/zephyr/zephyr_usbc_ss_mux_and_retimer.md b/docs/zephyr/zephyr_usbc_ss_mux_and_retimer.md
new file mode 100644
index 0000000000..d6333e2c26
--- /dev/null
+++ b/docs/zephyr/zephyr_usbc_ss_mux_and_retimer.md
@@ -0,0 +1,93 @@
+# Zephyr EC USB-C SS MUX and Retimer Configuration
+
+[TOC]
+
+## Overview
+
+Enable support for a [USB-C] [SuperSpeed Mux] and [Retimer]. See
+[cros-ec,usb-mux-chain] for a description of how "mux-chains" work.
+
+## Kconfig Options
+
+The Kconfig option `CONFIG_PLATFORM_EC_USBC_SS_MUX` enables the selection of
+a [USB-C] [SuperSpeed Mux]. See the file [Kconfig.usbc_ss_mux] for all
+Kconfig options related to this feature.
+
+You must also enable the Kconfig option for the specific muxex and retimers
+used in your design. These Kconfig options are found in the [Kconfig.usb_mux]
+and [Kconfig.retimer], respectively.
+
+## Devicetree Nodes
+
+The `USB-C SuperSpeed Mux` device tree nodes are defined in the [`DTS Bindings`]
+file for each type of `USB-C SuperSpeed Mux` that extends [cros-ec,usbc-mux-tcpci].
+
+The `Retimer` device tree nodes are defined in the [`DTS Bindings`] file for
+each type of `Retimer`.
+
+The `USB-C SuperSpeed Mux` device is added to the corresponding I2C
+bus node and the "named-usbc-port" contains a phandle to the device.
+
+## Board Specific Code
+
+None required.
+
+## Threads
+
+USB-C SuperSpeed Mux and Retimer does not enable any threads.
+
+## Testing and Debugging
+
+The [`I2C bus scan`] can be used to verify the Retimer device can be accessed.
+
+## Example
+```
+port0@0 {
+	compatible = "named-usbc-port";
+	reg = <0>;
+	usb-mux-chain-0 {
+		compatible = "cros-ec,usb-mux-chain";
+		usb-muxes = <&usb_c0_bb_retimer
+			     &virtual_mux_c0>;
+	};
+};
+port0-muxes {
+	virtual_mux_c0: virtual-mux-c0 {
+		compatible = "cros-ec,usbc-mux-virtual";
+	};
+};
+
+&i2c3_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+	pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>;
+	pinctrl-names = "default";
+
+	usb_c0_bb_retimer: jhl8040r-c0@56 {
+		compatible = "intel,jhl8040r";
+		reg = <0x56>;
+		int-pin = <&usb_c0_rt_int_odl>;
+		reset-pin = <&usb_c0_rt_rst_odl>;
+	};
+
+	usb_c2_bb_retimer: jhl8040r-c2@57 {
+		compatible = "intel,jhl8040r";
+		reg = <0x57>;
+		int-pin = <&usb_c2_rt_int_odl>;
+		reset-pin = <&usb_c2_rt_rst_odl>;
+	};
+};
+
+```
+[USB-C]: ../usb-c.md
+[SuperSpeed Mux]:../usb-c.md#ssmux
+[Retimer]: ../ec_terms.md#retimer
+[Kconfig.usbc_ss_mux]:
+https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.usbc_ss_mux
+[Kconfig.retimer]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.retimer
+[`I2C bus scan`]: ./zephyr_i2c.md#Shell-Command_i2c
+[cros-ec,usbc-mux-tcpci]:
+https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/dts/bindings/usbc/mux/cros-ec,usbc-mux-tcpci.yaml
+[cros-ec,usb-mux-chain]:
+https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/dts/bindings/usbc/cros-ec,usb-mux-chain.yaml
+[`DTS Bindings`]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/dts/bindings/usbc/mux
diff --git a/docs/zephyr/ztest.md b/docs/zephyr/ztest.md
new file mode 100644
index 0000000000..c498b0b958
--- /dev/null
+++ b/docs/zephyr/ztest.md
@@ -0,0 +1,207 @@
+# Zephyr Testing
+
+[TOC]
+
+Before starting, developers should read the following:
+- [Zephyr Test Framework](https://docs.zephyrproject.org/latest/develop/test/ztest.html)
+- [Zephyr Test Runner (Twister)](https://docs.zephyrproject.org/latest/develop/test/twister.html)
+
+## Getting help
+
+Get your tests reviewed by adding [zephyr-test-eng@google.com](mailto:zephyr-test-eng@google.com)
+as a reviewer on your CL.
+
+Ask a question:
+- If you're a googler, please post using our YAQS label [zephyr-rtos-test](http://yaqs/eng/t/zephyr-rtos-test)
+- External contributors should:
+    - email to [zephyr-test-eng@google.com](mailto:zephyr-test-eng@google.com)
+    - or [sign up to the Public Zephyr discord](https://discord.com/invite/Ck7jw53nU2), and then visit the [#testing](https://discord.com/channels/720317445772017664/733037944922964069)
+  channel for questions.
+
+## Where to add tests?
+
+Tests currently reside in [zephyr/test](https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/test/).
+When adding a new test it's possible to either create a new directory which
+includes a `testcase.yaml` or add a new entry to an existing `testcase.yaml` if
+the test is a slight variation of an existing test.
+
+### How to decide where your tests should go?
+
+If you're adding a new compilational unit, check your dependencies. Is this unit
+tied to an existing Kconfig? If so, it's possible that another test is already
+enabling it and linking your `.c` file. It's probably worth your time to simply
+add a new test suite to that existing test binary, or at the very least,
+creating a variant of the binary by adding a new entry in the `testcase.yaml`
+file.
+
+If this doesn't work, it's possible that you might need to create a new test
+from scratch. First, decide if this will be an integration test or a unit test.
+Integration tests will build the full system (see below) and thus are sometimes
+easier to set up (since they look and feel like an application). For the same
+reason that makes them easier to set up, the lack of mocks can make things more
+difficult when trying to force execution down a specific code path.
+
+In the case of integration tests, any test under `zephyr/test` will serve as a
+good example. Alternatively, an example of a unit test can be found under
+[common/spi/flash_reg](https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/common/spi/flash_reg/).
+
+## The structure of the `testcase.yaml`
+
+The top level `testcase.yaml` uses the `test:` block to define the attributes
+for each test case. The optional `common:` block uses the same attributes as the
+test cases, but the attributes are applied to all test cases in the file. See
+[here](https://docs.zephyrproject.org/latest/develop/test/twister.html#test-cases)
+for more details.
+
+Some common attributes include:
+- `extra_configs` - a list of Kconfigs to add to the test.
+- `extra_conf_files` - specifies a YAML list of additional Kconfig files to
+  to apply to the build. Replaces the `CONF_FILE` field in extra_args.
+- `extra_overlay_confs` - specifies a list of overlay Kconfig files. Replaces
+  the `OVERLAY_CONFIG` field in extra_args.
+- `extra_dtc_overlay_files` - specifies a list of additional device tree files
+  to apply to the build. Replaces the `DTC_OVERLAY_FILE` field in extra_args.
+
+`extra_args` is a string field that allows injecting free-form CMake variables
+into the build. It is rarely needed and the practice of specifying `CONF_FILE`,
+`OVERLAY_CONFIG`, or `DTC_OVERLAY_FILE` here is deprecated. Please use the
+above fields for these functions, as they are much more readable.
+## Integration tests
+
+Integration tests build the full EC. They require devicetree and all Kconfigs to
+be set appropriately. To build an integration test, simply use the following
+CMakeLists.txt template:
+
+```cmake
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(<your_test_project_name>)
+target_sources(app
+  PRIVATE
+    src/...
+)
+
+# Add global FFF declaration
+add_subdirectory(${PLATFORM_EC}/zephyr/test/test_utils test_utils)
+```
+
+Then, you'll need a default `prj.conf` file to set the default configs. Keep in
+mind that this file will be automatically included in all the tests unless it is
+overridden by the test's `extra_args` so you only want to put things that will
+apply to all tests here. It will look like:
+
+```
+CONFIG_ZTEST=y
+CONFIG_ZTEST_NEW_API=y
+
+# Enable the shim of the legacy CrosEC (You’ll need both)
+CONFIG_CROS_EC=y
+CONFIG_PLATFORM_EC=y
+```
+
+## Mocking
+
+We're using [FFF](http://github.com/meekrosoft/fff) for our mocking framework.
+For most use cases these are the things to remember:
+1. Reset your fakes in your test suite's `before` function using `RESET_FAKE()`.
+   If multiple suites need to reset fakes, consider using a
+   [test rule](https://docs.zephyrproject.org/latest/develop/test/ztest.html#test-rules).
+2. You'll need *1* instance of `DEFINE_FFF_GLOBALS;` in your binary. This is
+   done in the sample above via including `test_utils` into your binary as a
+   subdirectory.
+3. Use C++ for better `custom_fake` handling by setting the following before
+    including `fff.h`:
+    ```c
+    #define CUSTOM_FFF_FUNCTION_TEMPLATE(RETURN, FUNCNAME, ...) \
+        std::function<RETURN(__VA_ARGS__)> FUNCNAME
+    ```
+    This will enable the following:
+    ```c
+    ZTEST_F(suite, test_x)
+    {
+      my_function_fake.custom_fake = [fixture]() {
+        /* Capturing lambda has access to 'fixture' */
+      };
+      ...
+    }
+    ```
+
+
+## Running twister
+
+### Run all tests under a specific directory
+
+```shell
+platform/ec$ ./twister -T path/to/my/tests
+```
+
+### Run a specific test
+```shell
+platform/ec$ ./twister -s <test dir>/<my.test.scenario>
+```
+
+For example:
+```shell
+platform/ec$ ./twister -s drivers/drivers.default
+```
+
+Explanation of this string: `drivers/` is the directory under `zephyr/test/`
+that contains the requested test, and `drivers.default` is the specific test
+scenario specified in that directory's `testcase.yaml` file.
+
+### Run all tests with coverage
+
+You can find more info on code coverage at
+[Zephyr ztest code coverage](../code_coverage.md#Zephyr_ztest_code_coverage).
+
+```shell
+platform/ec$ ./twister -p native_posix -p unit_testing --coverage
+```
+
+### Get more info on twister
+```shell
+platform/ec$ ./twister --help
+```
+
+Other useful flags:
+- `-i` Print inline logs to STDOUT on error (as well as log file)
+- `-n` No clean (incremental builds)
+- `-c` Clobber, don't create a new `twister-out/` directory
+- `-v` Verbose logging (can use `-vv` or `-vvv` for more logging)
+- `-b` Build only
+
+## Using assumptions
+
+The `zassume*` API is used to skip tests when certain preconditions are not
+met. Please don't use it. In our tests we shouldn't ever need to skip tests
+since we control all dependencies. If for some reason you actually need to skip
+a test use `ztest_test_skip()` since that will indicate that you intended to
+skip and didn't use assume by mistake when you meant to use assert.
+
+## Debugging
+
+If the test targets `native_posix` or `unit_testins` platforms, you can run it
+through your choice of debugger (lldb is provided in the chroot). Additionally,
+it's possible to run only a subset of the tests via:
+
+```shell
+$ ./twister-out/native_posix/zephyr/test/.../zephyr/zephyr.exe -list
+# List of all tests in the binary in the format of <suite_name:test_name>
+$ ./twister-out/native_posix/zephyr/test/.../zephyr/zephyr.exe -test=suite0:*,suite1:test0
+# Runs all tests under suite0 and test0 from suite1
+$ lldb ./twister-out/unit_testing/.../testbinary
+# Starts lldb for the test binary
+```
+
+## Deflaking
+
+zTest allows deflaking tests via shuffling. To enable this feature, simply turn
+on `CONFIG_ZTEST_SHUFFLE=y`. Your test binary's test suites and test order will
+be random as well as run multiple times. To fine-tune the execution:
+- Set `CONFIG_ZTEST_SHUFFLE_SUITE_REPEAT_COUNT` to an `int` controlling how many
+  times the test suites will be shuffled and run.
+- Set `CONFIG_ZTEST_SHUFFLE_TEST_REPEAT_COUNT` to an `int` controlling how many
+  times the individual tests will be shuffled and run (per suite run).
+
+Note that the total number of times that tests will run is the result of
+multiplying those two Kconfig values.
diff --git a/docs/zephyr_shim.md b/docs/zephyr_shim.md
deleted file mode 100644
index 900bc1775d..0000000000
--- a/docs/zephyr_shim.md
+++ /dev/null
@@ -1,168 +0,0 @@
-[TOC]
-
-# Objective
-
-Allow a subset of the platform/ec code to be built as part of the Zephyr-based
-EC without needing to land code into upstream zephyr, or our zephyr-chrome
-repository.
-
-# Background
-
-Now that Google has joined [Zephyr OS](https://www.zephyrproject.org/), the EC
-team is moving toward it instead of platform/ec code on embedded controllers for
-future Chrome OS devices. See the
-[originally proposed idea](https://goto.google.com/cros-ec-rtos) and a more
-specific [Zephyr process doc](https://goto.google.com/zephyr-structure) of what
-future development on Zephyr will look like.
-
-Simply put, we want to move to Zephyr OS to use an open-source embedded OS that
-has a vibrant community. The embedded OS scene for the industry is very
-fragmented, with various parties using their own custom solution. We see the
-strong open-source community at Zephyr as potentially helping to consolidate
-efforts in the embedded controller space. It will also benefit our partners
-(both chip vendors and OEMs) since they should only have to support one embedded
-OS (i.e., Zephyr) for both their Chrome OS and Windows based devices.
-
-Migrating to use Zephyr fully is going to take a few years. We do not want to
-diverge from the active development happening on platform/ec code. We
-potentially want to ship a product using Zephyr before the migration is
-complete.
-
-# Design ideas
-
-In order to reuse `platform/ec` development , we shim "active" `platform/ec`
-code as a
-[Zephyr Module](https://docs.zephyrproject.org/latest/guides/modules.html). This
-requires us to add some Zephyr specific code in a `zephyr` directory in the
-`platform/ec` codebase. Once we release a Zephyr-based EC, then we can turn down
-platform/ec for future development and work on migrating the platform/ec-module
-code out of the module directory and into a first-class Zephyr code format -- in
-the local
-[Chrome Zephyr repo](https://chromium.googlesource.com/chromiumos/platform/zephyr-chrome/+/refs/heads/master)
-and ultimately [upstream](https://github.com/zephyrproject-rtos/zephyr).
-
-For platform/ec code that is stable and not under active development, the Zephyr
-team may port that code to Zephyr, thus skipping the shimming process.
-
-## Subsystems of interest
-
-### With Shim
-
-We shim the following subsystems (non-exhaustive).
-
-*   USB-C: TCPC, PPC, MUX, TCPMv2
-*   Charge Manager
-*   SoC Power Sequencing
-*   Sensors, if Intel’s HID-based solution is delayed in getting to Zephyr
-    upstream
-
-### Little-to-No Shim
-
-We adopt upstream Zephyr or skip the shimming process (non-exhaustive).
-
-*   CBI and dependent EEPROM code
-    *   The format is stable. We pull in the list of CBI tags from platform/ec
-        though
-*   EFS2, Vboot, RO/RW split
-    *   Adjusting flash layout would be difficult to shim, and the concept is
-        very stable.
-    *   We may shim some core EFS2 logic
-*   Host command framework
-*   Sensors, if Intel’s HID-based solution getts to Zephyr upstream and passes
-    CTS
-*   Keyboard and keycode scanning support
-    *   We may shim the newer Vivaldi feature.
-*   Console support
-    *   We allow individual console commands via DECLARE\_CONSOLE\_COMMAND to be
-        shimmed to Zephyr. These convert commands to work with Zephyr's shell
-        subsystem.
-*   I2C
-
-## New content in platform/ec
-
-Add the `src/platform/ec/zephyr` folder with:
-
-*   [Module integration files](https://docs.zephyrproject.org/latest/guides/modules.html#build-system-integration),
-    e.g., module.yml, CMakeLists.txt, and KConfig.
-    *   **module.yml** is the required entry point (must be located at
-        _zephyr/module.yml_ in the repository) for Zephyr modules, and declares
-        the location of Kconfig and CMakeLists.txt files used by the Zephyr
-        build system.
-    *   **CMakeLists.txt** replicates build logic for the files being shimmed,
-        outside of the platform/ec Makefile.
-    *   **Kconfig** will declare any CONFIG\_\* options which are important to
-        expose from platform/ec code to the Zephyr build.
-*   Shim code to translate platform/ec code into Zephyr code
-    *   For example, redefine platform/ec’s
-        [`DECLARE_HOST_COMMAND`](https://source.chromium.org/chromiumos/chromiumos/codesearch/+/master:src/platform/ec/include/host_command.h;l=256;drc=514923bc59f5a3435dbb7cbf348735ed41889ffe)
-        to map to Zephyr's upstream
-        [`EC_HOST_CMD_HANDLER`](https://github.com/zephyrproject-rtos/zephyr/blob/d7468bf836b75c29980441f294a61eae6bf4bc75/include/ec_host_cmd.h#L73)
-        macro. This allows us to compile select platform/ec files in the Zephyr
-        build.
-
-## Namespace Collisions
-
-One significant issue of mixing Zephyr headers with our existing EC code is that
-we currently have many names colliding with the Zephyr code. For example,
-Zephyr's atomic functions also are named `atomic_add`, `atomic_or`, ...,
-however, have a different API from our EC's atomic functions. This is critical,
-since atomic operations are often used in `static inline` functions placed in
-header files.
-
-In some cases, we are able to hack around these collisions by creating macros
-and functions which are compatible with both Zephyr and our EC's usages. For
-example, we can create a modified `IS_ENABLED` which accepts both defined to
-nothing usages (CrOS EC `config.h` style), and defined to `1` usages (Zephyr
-Kconfig style).
-
-However, long term, we may find this to be a continual cause of issues, and
-creating hacks for every colliding macro or function may be unsustainable. We
-propose _gradually_ introducing a namespace prefix to the `platform/ec`
-codebase, for example `crec_`. We can begin at the critical areas of namespace
-collision (e.g., atomics) and continue to improve the naming convention with
-time.
-
-## New CQ check
-
-As long as code from platform/ec is part of the zephyr
-[ebuild](http://cs/chromeos_public/src/third_party/chromiumos-overlay/chromeos-base/chromeos-zephyr-2_3/chromeos-zephyr-2_3-9999.ebuild),
-then we need to run the Zephyr CQ checks on any platform/ec CLs in addition to
-the normal platform/ec CQ checks. This ensures that platform/ec changes aren’t
-breaking the Zephyr builds and requiring the Zephyr team to debug recent
-changes.
-
-For local builds, we can run `emerge-betty chromeos-zephyr-2_3` or `zmake`
-utility to check that an EC CL has not broken anything on the Zephyr side.
-
-We will work with the CI team to enable this.
-
-# Alternatives Considered
-
-## Translate code and mirror into the zephyr-chrome repository
-
-We could potentially write a script which, via a series of find/replace
-operations, translates a platform/ec module to use Zephyr functions, macros, and
-paradigms. On a frequent basis, we would translate all modules of interest in
-the platform/ec repository and land an "uprev" change in the zephyr-chrome
-repository.
-
-The main disadvantage of this technique is that we can't get any CQ coverage
-when platform/ec CLs land that the modules will continue to work in Zephyr.
-Additionally, the translator script would be delicate and probably require
-frequent maintenance.
-
-However, this technique does have some benefits. With modules directly
-translated to code in the Zephyr paradigm, the process of upstreaming a shimmed
-module to ZephyrOS would be significantly easier. Additionally, it would require
-no shim code in platform/ec.
-
-## Don't do any code sharing
-
-One option is to avoid shimming in any platform/ec code and allow the Zephyr
-team to re-implement features in upstream zephyr, or our local zephyr-chrome
-repository.
-
-Disregarding the infeasible amount of work required to complete this option, the
-platform/ec repository has a far faster development pace as there are many more
-contributors, and the Zephyr features would quickly lose parity during the time
-frame that we are launching both Zephyr-based and platform/ec-based devices.
diff --git a/driver/accel_bma2x2.c b/driver/accel_bma2x2.c
index 92e273cf9a..772ae64696 100644
--- a/driver/accel_bma2x2.c
+++ b/driver/accel_bma2x2.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,10 +9,11 @@
  * Supported: BMA255
  */
 
+#include "accel_bma2x2.h"
 #include "accelgyro.h"
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
-#include "driver/accel_bma2x2.h"
 #include "i2c.h"
 #include "math_util.h"
 #include "spi.h"
@@ -20,7 +21,7 @@
 #include "util.h"
 
 #define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
 
 /* Number of times to attempt to enable sensor before giving up. */
 #define SENSOR_ENABLE_ATTEMPTS 5
@@ -43,13 +44,18 @@ static inline int raw_write8(const int port, const uint16_t i2c_addr_flags,
 	return i2c_write8(port, i2c_addr_flags, reg, data);
 }
 
-static int set_range(const struct motion_sensor_t *s, int range, int rnd)
+static int set_range(struct motion_sensor_t *s, int range, int rnd)
 {
-	int ret,  range_val, reg_val, range_reg_val;
-	struct accelgyro_saved_data_t *data = s->drv_data;
+	int ret, range_val, reg_val, range_reg_val;
+
+	/* Range has to be between 2G-16G */
+	if (range < 2)
+		range = 2;
+	else if (range > 16)
+		range = 16;
 
 	range_val = BMA2x2_RANGE_TO_REG(range);
-	if ((BMA2x2_RANGE_TO_REG(range_val) < range) && rnd)
+	if ((BMA2x2_REG_TO_RANGE(range_val) < range) && rnd)
 		range_val = BMA2x2_RANGE_TO_REG(range * 2);
 
 	mutex_lock(s->mutex);
@@ -67,20 +73,13 @@ static int set_range(const struct motion_sensor_t *s, int range, int rnd)
 
 	/* If successfully written, then save the range. */
 	if (ret == EC_SUCCESS)
-		data->range = BMA2x2_REG_TO_RANGE(range_val);
+		s->current_range = BMA2x2_REG_TO_RANGE(range_val);
 
 	mutex_unlock(s->mutex);
 
 	return ret;
 }
 
-static int get_range(const struct motion_sensor_t *s)
-{
-	struct accelgyro_saved_data_t *data = s->drv_data;
-
-	return data->range;
-}
-
 static int get_resolution(const struct motion_sensor_t *s)
 {
 	return BMA2x2_RESOLUTION;
@@ -91,23 +90,32 @@ static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
 	int ret, odr_val, odr_reg_val, reg_val;
 	struct accelgyro_saved_data_t *data = s->drv_data;
 
-	odr_val = BMA2x2_BW_TO_REG(rate);
-	if ((BMA2x2_REG_TO_BW(odr_val) < rate) && rnd)
-		odr_val = BMA2x2_BW_TO_REG(rate * 2);
+	/* Rate has to be between 7.8125Hz - 1000Hz */
+	if (rate < 7813) {
+		rate = 7812;
+		odr_val = BMA2x2_BW_7_81HZ;
+	} else if (rate > 1000000) {
+		rate = 1000000;
+		odr_val = BMA2x2_BW_1000HZ;
+	} else {
+		odr_val = BMA2x2_BW_TO_REG(rate);
+		if ((BMA2x2_REG_TO_BW(odr_val) < rate) && rnd)
+			odr_val = BMA2x2_BW_TO_REG(rate * 2);
+	}
 
 	mutex_lock(s->mutex);
 
 	/* Determine the new value of control reg and attempt to write it. */
-	ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-			BMA2x2_BW_SELECT_ADDR, &odr_reg_val);
+	ret = raw_read8(s->port, s->i2c_spi_addr_flags, BMA2x2_BW_SELECT_ADDR,
+			&odr_reg_val);
 	if (ret != EC_SUCCESS) {
 		mutex_unlock(s->mutex);
 		return ret;
 	}
 	reg_val = (odr_reg_val & ~BMA2x2_BW_MSK) | odr_val;
 	/* Set output data rate. */
-	ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-			 BMA2x2_BW_SELECT_ADDR, reg_val);
+	ret = raw_write8(s->port, s->i2c_spi_addr_flags, BMA2x2_BW_SELECT_ADDR,
+			 reg_val);
 
 	/* If successfully written, then save the new data rate. */
 	if (ret == EC_SUCCESS)
@@ -197,7 +205,7 @@ static int read(const struct motion_sensor_t *s, intv3_t v)
 	return EC_SUCCESS;
 }
 
-static int perform_calib(const struct motion_sensor_t *s, int enable)
+static int perform_calib(struct motion_sensor_t *s, int enable)
 {
 	int ret, val, status, rate, range, i;
 	timestamp_t deadline;
@@ -205,15 +213,15 @@ static int perform_calib(const struct motion_sensor_t *s, int enable)
 	if (!enable)
 		return EC_SUCCESS;
 
-	ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-			BMA2x2_OFFSET_CTRL_ADDR, &val);
+	ret = raw_read8(s->port, s->i2c_spi_addr_flags, BMA2x2_OFFSET_CTRL_ADDR,
+			&val);
 	if (ret)
 		return ret;
 	if (!(val & BMA2x2_OFFSET_CAL_READY))
 		return EC_ERROR_ACCESS_DENIED;
 
 	rate = get_data_rate(s);
-	range = get_range(s);
+	range = s->current_range;
 	/*
 	 * Temporary set frequency to 100Hz to get enough data in a short
 	 * period of time.
@@ -230,8 +238,8 @@ static int perform_calib(const struct motion_sensor_t *s, int enable)
 	val = ((BMA2x2_OFC_TARGET_0G << BMA2x2_OFC_TARGET_AXIS(X)) |
 	       (BMA2x2_OFC_TARGET_0G << BMA2x2_OFC_TARGET_AXIS(Y)) |
 	       (val << BMA2x2_OFC_TARGET_AXIS(Z)));
-	raw_write8(s->port, s->i2c_spi_addr_flags,
-		   BMA2x2_OFC_SETTING_ADDR, val);
+	raw_write8(s->port, s->i2c_spi_addr_flags, BMA2x2_OFC_SETTING_ADDR,
+		   val);
 
 	for (i = X; i <= Z; i++) {
 		val = (i + 1) << BMA2x2_OFFSET_TRIGGER_OFF;
@@ -261,15 +269,15 @@ static int perform_calib(const struct motion_sensor_t *s, int enable)
 	return ret;
 }
 
-static int init(const struct motion_sensor_t *s)
+static int init(struct motion_sensor_t *s)
 {
 	int ret = 0, tries = 0, val, reg, reset_field;
 
 	/* This driver requires a mutex */
 	ASSERT(s->mutex);
 
-	ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-			BMA2x2_CHIP_ID_ADDR, &val);
+	ret = raw_read8(s->port, s->i2c_spi_addr_flags, BMA2x2_CHIP_ID_ADDR,
+			&val);
 	if (ret)
 		return EC_ERROR_UNKNOWN;
 
@@ -319,7 +327,6 @@ const struct accelgyro_drv bma2x2_accel_drv = {
 	.init = init,
 	.read = read,
 	.set_range = set_range,
-	.get_range = get_range,
 	.get_resolution = get_resolution,
 	.set_data_rate = set_data_rate,
 	.get_data_rate = get_data_rate,
diff --git a/driver/accel_bma2x2.h b/driver/accel_bma2x2.h
deleted file mode 100644
index 67228ab35d..0000000000
--- a/driver/accel_bma2x2.h
+++ /dev/null
@@ -1,174 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* BMA2x2 gsensor module for Chrome EC */
-
-#ifndef __CROS_EC_ACCEL_BMA2x2_H
-#define __CROS_EC_ACCEL_BMA2x2_H
-
-extern const struct accelgyro_drv bma2x2_accel_drv;
-
-/* I2C ADDRESS DEFINITIONS    */
-/* The following definition of I2C address is used for the following sensors
-* BMA253
-* BMA255
-* BMA355
-* BMA280
-* BMA282
-* BMA223
-* BMA254
-* BMA284
-* BMA250E
-* BMA222E
-*/
-#define BMA2x2_I2C_ADDR1_FLAGS              0x18
-#define BMA2x2_I2C_ADDR2_FLAGS              0x19
-
-/* The following definition of I2C address is used for the following sensors
-* BMC150
-* BMC056
-* BMC156
-*/
-#define BMA2x2_I2C_ADDR3_FLAGS              0x10
-#define BMA2x2_I2C_ADDR4_FLAGS              0x11
-
-/*** Chip-specific registers ***/
-/* REGISTER ADDRESS DEFINITIONS */
-#define BMA2x2_EEP_OFFSET                   0x16
-#define BMA2x2_IMAGE_BASE                   0x38
-#define BMA2x2_IMAGE_LEN                22
-#define BMA2x2_CHIP_ID_ADDR                 0x00
-#define BMA255_CHIP_ID_MAJOR                0xfa
-
-/* DATA ADDRESS DEFINITIONS */
-#define BMA2x2_X_AXIS_LSB_ADDR              0x02
-#define BMA2x2_X_AXIS_MSB_ADDR              0x03
-#define BMA2x2_Y_AXIS_LSB_ADDR              0x04
-#define BMA2x2_Y_AXIS_MSB_ADDR              0x05
-#define BMA2x2_Z_AXIS_LSB_ADDR              0x06
-#define BMA2x2_Z_AXIS_MSB_ADDR              0x07
-#define BMA2x2_TEMP_ADDR                    0x08
-
-/* STATUS ADDRESS DEFINITIONS */
-#define BMA2x2_STAT1_ADDR                   0x09
-#define BMA2x2_STAT2_ADDR                   0x0A
-#define BMA2x2_STAT_TAP_SLOPE_ADDR          0x0B
-#define BMA2x2_STAT_ORIENT_HIGH_ADDR        0x0C
-#define BMA2x2_STAT_FIFO_ADDR               0x0E
-#define BMA2x2_RANGE_SELECT_ADDR            0x0F
-#define BMA2x2_RANGE_SELECT_MSK         0x0F
-#define BMA2x2_RANGE_2G                 3
-#define BMA2x2_RANGE_4G                 5
-#define BMA2x2_RANGE_8G                 8
-#define BMA2x2_RANGE_16G                12
-
-#define BMA2x2_RANGE_TO_REG(_range) \
-	((_range) < 8 ? BMA2x2_RANGE_2G + ((_range) / 4) * 2 : \
-			BMA2x2_RANGE_8G + ((_range) / 16) * 4)
-
-#define BMA2x2_REG_TO_RANGE(_reg) \
-	((_reg) < BMA2x2_RANGE_8G ? 2 + (_reg) - BMA2x2_RANGE_2G : \
-				    8 + ((_reg) - BMA2x2_RANGE_8G) * 2)
-
-#define BMA2x2_BW_SELECT_ADDR               0x10
-#define BMA2x2_BW_MSK                   0x1F
-#define BMA2x2_BW_7_81HZ                0x08 /* LowPass   7.8125HZ */
-#define BMA2x2_BW_15_63HZ               0x09 /* LowPass  15.625HZ */
-#define BMA2x2_BW_31_25HZ               0x0A /* LowPass  31.25HZ */
-#define BMA2x2_BW_62_50HZ               0x0B /* LowPass  62.50HZ */
-#define BMA2x2_BW_125HZ                 0x0C /* LowPass 125HZ */
-#define BMA2x2_BW_250HZ                 0x0D /* LowPass 250HZ */
-#define BMA2x2_BW_500HZ                 0x0E /* LowPass 500HZ */
-#define BMA2x2_BW_1000HZ                0x0F /* LowPass 1000HZ */
-
-#define BMA2x2_BW_TO_REG(_bw) \
-	((_bw) < 125000 ? \
-	 BMA2x2_BW_7_81HZ + __fls(((_bw) * 10) / 78125) : \
-	 BMA2x2_BW_125HZ + __fls((_bw) / 125000))
-
-#define  BMA2x2_REG_TO_BW(_reg) \
-	((_reg) < BMA2x2_BW_125HZ ? \
-	 (78125 << ((_reg) - BMA2x2_BW_7_81HZ)) / 10 : \
-	 125000 << ((_reg) - BMA2x2_BW_125HZ))
-
-#define BMA2x2_MODE_CTRL_ADDR               0x11
-#define BMA2x2_LOW_NOISE_CTRL_ADDR          0x12
-#define BMA2x2_DATA_CTRL_ADDR               0x13
-#define BMA2x2_RST_ADDR                     0x14
-#define BMA2x2_CMD_SOFT_RESET               0xb6
-
-/* INTERRUPT ADDRESS DEFINITIONS */
-#define BMA2x2_INTR_ENABLE1_ADDR            0x16
-#define BMA2x2_INTR_ENABLE2_ADDR            0x17
-#define BMA2x2_INTR_SLOW_NO_MOTION_ADDR     0x18
-#define BMA2x2_INTR1_PAD_SELECT_ADDR        0x19
-#define BMA2x2_INTR_DATA_SELECT_ADDR        0x1A
-#define BMA2x2_INTR2_PAD_SELECT_ADDR        0x1B
-#define BMA2x2_INTR_SOURCE_ADDR             0x1E
-#define BMA2x2_INTR_SET_ADDR                0x20
-#define BMA2x2_INTR_CTRL_ADDR               0x21
-
-/* FEATURE ADDRESS DEFINITIONS */
-#define BMA2x2_LOW_DURN_ADDR                0x22
-#define BMA2x2_LOW_THRES_ADDR               0x23
-#define BMA2x2_LOW_HIGH_HYST_ADDR           0x24
-#define BMA2x2_HIGH_DURN_ADDR               0x25
-#define BMA2x2_HIGH_THRES_ADDR              0x26
-#define BMA2x2_SLOPE_DURN_ADDR              0x27
-#define BMA2x2_SLOPE_THRES_ADDR             0x28
-#define BMA2x2_SLOW_NO_MOTION_THRES_ADDR    0x29
-#define BMA2x2_TAP_PARAM_ADDR               0x2A
-#define BMA2x2_TAP_THRES_ADDR               0x2B
-#define BMA2x2_ORIENT_PARAM_ADDR            0x2C
-#define BMA2x2_THETA_BLOCK_ADDR             0x2D
-#define BMA2x2_THETA_FLAT_ADDR              0x2E
-#define BMA2x2_FLAT_HOLD_TIME_ADDR          0x2F
-#define BMA2x2_SELFTEST_ADDR                0x32
-#define BMA2x2_EEPROM_CTRL_ADDR             0x33
-#define BMA2x2_SERIAL_CTRL_ADDR             0x34
-
-/* OFFSET ADDRESS DEFINITIONS */
-#define BMA2x2_OFFSET_CTRL_ADDR             0x36
-#define BMA2x2_OFFSET_RESET          0x80
-#define BMA2x2_OFFSET_TRIGGER_OFF    5
-#define BMA2x2_OFFSET_TRIGGER_MASK   (0x3 << BMA2x2_OFFSET_TRIGGER_OFF)
-#define BMA2x2_OFFSET_CAL_READY      0x10
-
-#define BMA2x2_OFC_SETTING_ADDR           0x37
-#define BMA2x2_OFC_TARGET_AXIS_OFF   1
-#define BMA2x2_OFC_TARGET_AXIS_LEN   2
-#define BMA2x2_OFC_TARGET_AXIS(_axis) \
-	(BMA2x2_OFC_TARGET_AXIS_LEN * (_axis) + BMA2x2_OFC_TARGET_AXIS_OFF)
-#define BMA2x2_OFC_TARGET_0G         0
-#define BMA2x2_OFC_TARGET_PLUS_1G    1
-#define BMA2x2_OFC_TARGET_MINUS_1G   2
-
-#define BMA2x2_OFFSET_X_AXIS_ADDR           0x38
-#define BMA2x2_OFFSET_Y_AXIS_ADDR           0x39
-#define BMA2x2_OFFSET_Z_AXIS_ADDR           0x3A
-
-/* GP ADDRESS DEFINITIONS */
-#define BMA2x2_GP0_ADDR                     0x3B
-#define BMA2x2_GP1_ADDR                     0x3C
-
-/* FIFO ADDRESS DEFINITIONS */
-#define BMA2x2_FIFO_MODE_ADDR               0x3E
-#define BMA2x2_FIFO_DATA_OUTPUT_ADDR        0x3F
-#define BMA2x2_FIFO_WML_TRIG                0x30
-
-/* Sensor resolution in number of bits. This sensor has fixed resolution. */
-#define BMA2x2_RESOLUTION               12
-
-/*
- * Min and Max sampling frequency in mHz.
- * Given BMA255 is polled, we limit max frequency to 125Hz.
- * If set to 250Hz, given we can read up to 3ms before the due time
- * (see CONFIG_MOTION_MIN_SENSE_WAIT_TIME), we may read too early when
- * other sensors are active.
- */
-#define BMA255_ACCEL_MIN_FREQ           7810
-#define BMA255_ACCEL_MAX_FREQ \
-	MOTION_MAX_SENSOR_FREQUENCY(125000, 15625)
-#endif /* __CROS_EC_ACCEL_BMA2x2_H */
diff --git a/driver/accel_bma422.h b/driver/accel_bma422.h
new file mode 100644
index 0000000000..0b4f644101
--- /dev/null
+++ b/driver/accel_bma422.h
@@ -0,0 +1,16 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* BMA422 gsensor module for Chrome EC */
+
+#ifndef __CROS_EC_ACCEL_BMA422_H
+#define __CROS_EC_ACCEL_BMA422_H
+
+#include "accel_bma4xx.h"
+
+/* Chip ID of BMA422 */
+#define BMA422_CHIP_ID 0x12
+
+#endif /* __CROS_EC_ACCEL_BMA422_H */
diff --git a/driver/accel_bma4xx.c b/driver/accel_bma4xx.c
new file mode 100644
index 0000000000..3d6c7caa12
--- /dev/null
+++ b/driver/accel_bma4xx.c
@@ -0,0 +1,685 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Bosch Accelerometer driver for Chrome EC
+ *
+ * Supported: BMA422
+ */
+
+#include "accel_bma422.h"
+#include "accelgyro.h"
+#include "builtin/assert.h"
+#include "common.h"
+#include "console.h"
+#include "hwtimer.h"
+#include "i2c.h"
+#include "math_util.h"
+#include "spi.h"
+#include "task.h"
+#include "util.h"
+
+#include <motion_sense_fifo.h>
+
+#ifdef CONFIG_ACCEL_BMA4XX_INT_EVENT
+#define BMA4XX_USE_INTERRUPTS
+#endif
+
+#define CPUTS(outstr) cputs(CC_ACCEL, outstr)
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
+
+#define GOTO_ON_ERROR(label, expr)  \
+	do {                        \
+		ret = expr;         \
+		if (ret)            \
+			goto label; \
+	} while (0)
+/**
+ * Read 8bit register from accelerometer.
+ */
+static inline int bma4_read8(const struct motion_sensor_t *s, const int reg,
+			     int *data_ptr)
+{
+	return i2c_read8(s->port, s->i2c_spi_addr_flags, reg, data_ptr);
+}
+
+__maybe_unused static inline int bma4_read16(const struct motion_sensor_t *s,
+					     const int reg, int *data_ptr)
+{
+	return i2c_read16(s->port, s->i2c_spi_addr_flags, reg, data_ptr);
+}
+
+/**
+ * Write 8bit register to accelerometer.
+ */
+static inline int bma4_write8(const struct motion_sensor_t *s, const int reg,
+			      int data)
+{
+	int ret;
+
+	ret = i2c_write8(s->port, s->i2c_spi_addr_flags, reg, data);
+
+	/*
+	 * From Bosch: BMA needs a delay of 450us after each write if it
+	 * is in suspend mode, otherwise the operation may be ignored by
+	 * the sensor. Given we are only doing write during init, add
+	 * the delay unconditionally.
+	 */
+	usleep(450);
+
+	return ret;
+}
+
+/*
+ * Set specific bit set to certain value of a 8-bit reg.
+ */
+static inline int bma4_set_reg8(const struct motion_sensor_t *s, int reg,
+				uint8_t bits, int mask)
+{
+	int val;
+
+	RETURN_ERROR(bma4_read8(s, reg, &val));
+
+	val = (val & ~mask) | bits;
+
+	return bma4_write8(s, reg, val);
+}
+
+static int write_accel_offset(const struct motion_sensor_t *s, intv3_t v)
+{
+	int i, val;
+
+	rotate_inv(v, *s->rot_standard_ref, v);
+
+	for (i = X; i <= Z; i++) {
+		val = round_divide((int64_t)v[i] * BMA4_OFFSET_ACC_DIV_MG,
+				   BMA4_OFFSET_ACC_MULTI_MG);
+		if (val > 127)
+			val = 127;
+		if (val < -128)
+			val = -128;
+		if (val < 0)
+			val += 256;
+
+		RETURN_ERROR(bma4_write8(s, BMA4_OFFSET_0_ADDR + i, val));
+	}
+
+	return EC_SUCCESS;
+}
+
+static int set_foc_config(struct motion_sensor_t *s)
+{
+	/* Disabling offset compensation */
+	RETURN_ERROR(bma4_set_reg8(s, BMA4_NV_CONFIG_ADDR,
+				   (BMA4_DISABLE << BMA4_NV_ACCEL_OFFSET_POS),
+				   BMA4_NV_ACCEL_OFFSET_MSK));
+
+	/* Disable FIFO */
+	RETURN_ERROR(bma4_write8(s, BMA4_FIFO_CONFIG_1_ADDR, 0));
+
+	/* Set accelerometer configurations to 50Hz,CIC, continuous mode */
+	RETURN_ERROR(
+		bma4_write8(s, BMA4_ACCEL_CONFIG_ADDR, BMA4_FOC_ACC_CONF_VAL));
+
+	/* Set accelerometer to normal mode by enabling it */
+	RETURN_ERROR(bma4_set_reg8(s, BMA4_POWER_CTRL_ADDR,
+				   (BMA4_ENABLE << BMA4_ACCEL_ENABLE_POS),
+				   BMA4_ACCEL_ENABLE_MSK));
+
+	/* Disable advance power save mode */
+	RETURN_ERROR(
+		bma4_set_reg8(s, BMA4_POWER_CONF_ADDR,
+			      (BMA4_DISABLE << BMA4_ADVANCE_POWER_SAVE_POS),
+			      BMA4_ADVANCE_POWER_SAVE_MSK));
+
+	return EC_SUCCESS;
+}
+
+static int wait_and_read_data(struct motion_sensor_t *s, intv3_t v)
+{
+	int i;
+
+	/* Retry 5 times */
+	uint8_t reg_data[6] = { 0 }, try_cnt = 5;
+
+	/* Check if data is ready */
+	while (try_cnt && (!(reg_data[0] & BMA4_STAT_DATA_RDY_ACCEL_MSK))) {
+		/* 20ms delay for 50Hz ODR */
+		msleep(20);
+
+		/* Read the status register */
+		RETURN_ERROR(i2c_read_block(s->port, s->i2c_spi_addr_flags,
+					    BMA4_STATUS_ADDR, reg_data, 1));
+
+		try_cnt--;
+	}
+
+	if (!(reg_data[0] & 0x80))
+		return EC_ERROR_TIMEOUT;
+
+	/* Read the sensor data */
+	RETURN_ERROR(i2c_read_block(s->port, s->i2c_spi_addr_flags,
+				    BMA4_DATA_8_ADDR, reg_data, 6));
+
+	for (i = X; i <= Z; i++) {
+		v[i] = (((int8_t)reg_data[i * 2 + 1]) << 8) |
+		       (reg_data[i * 2] & 0xf0);
+
+		/* Since the resolution is only 12 bits*/
+		v[i] = (v[i] / 0x10);
+	}
+
+	rotate(v, *s->rot_standard_ref, v);
+
+	return EC_SUCCESS;
+}
+
+static int8_t perform_accel_foc(struct motion_sensor_t *s, int *target,
+				int sens_range)
+{
+	intv3_t accel_data, offset;
+
+	/* Structure to store accelerometer data temporarily */
+	int32_t delta_value[3] = { 0, 0, 0 };
+
+	/* Variable to define count */
+	uint8_t i, loop, sample_count = 0;
+
+	for (loop = 0; loop < BMA4_FOC_SAMPLE_LIMIT; loop++) {
+		RETURN_ERROR(wait_and_read_data(s, accel_data));
+
+		sample_count++;
+
+		/* Store the data in a temporary structure */
+		delta_value[0] += accel_data[0] - target[X];
+		delta_value[1] += accel_data[1] - target[Y];
+		delta_value[2] += accel_data[2] - target[Z];
+	}
+
+	/*
+	 * The data is in LSB so -> [(LSB)*1000*range/2^11*-1]
+	 * (unit of offset:mg)
+	 */
+	for (i = X; i <= Z; ++i) {
+		offset[i] = ((((delta_value[i] * 1000 * sens_range) /
+			       sample_count) /
+			      2048) *
+			     -1);
+	}
+
+	RETURN_ERROR(write_accel_offset(s, offset));
+
+	/* Enable the offsets and backup to NVM */
+	RETURN_ERROR(bma4_set_reg8(s, BMA4_NV_CONFIG_ADDR,
+				   (BMA4_ENABLE << BMA4_NV_ACCEL_OFFSET_POS),
+				   BMA4_NV_ACCEL_OFFSET_MSK));
+
+	return EC_SUCCESS;
+}
+
+static int perform_calib(struct motion_sensor_t *s, int enable)
+{
+	uint8_t config[2];
+	int pwr_ctrl, pwr_conf, fifo_conf;
+	intv3_t target = { 0, 0, 0 };
+	int sens_range = s->current_range;
+
+	if (!enable)
+		return EC_SUCCESS;
+
+	/* Read accelerometer configurations */
+	RETURN_ERROR(i2c_read_block(s->port, s->i2c_spi_addr_flags,
+				    BMA4_ACCEL_CONFIG_ADDR, config, 2));
+
+	RETURN_ERROR(bma4_read8(s, BMA4_FIFO_CONFIG_1_ADDR, &fifo_conf));
+
+	/* Get accelerometer enable status to be saved */
+	RETURN_ERROR(bma4_read8(s, BMA4_POWER_CTRL_ADDR, &pwr_ctrl));
+
+	/* Get advance power save mode to be saved */
+	RETURN_ERROR(bma4_read8(s, BMA4_POWER_CONF_ADDR, &pwr_conf));
+
+	/* Perform calibration */
+	RETURN_ERROR(set_foc_config(s));
+
+	/* We calibrate considering Z axis is laid flat on the surface */
+	target[Z] = BMA4_ACC_DATA_PLUS_1G(sens_range);
+
+	RETURN_ERROR(perform_accel_foc(s, target, sens_range));
+
+	/* Set the saved sensor configuration */
+	RETURN_ERROR(i2c_write_block(s->port, s->i2c_spi_addr_flags,
+				     BMA4_ACCEL_CONFIG_ADDR, config, 2));
+
+	RETURN_ERROR(bma4_write8(s, BMA4_FIFO_CONFIG_1_ADDR, fifo_conf));
+
+	RETURN_ERROR(bma4_write8(s, BMA4_POWER_CTRL_ADDR, pwr_ctrl));
+
+	RETURN_ERROR(bma4_write8(s, BMA4_POWER_CONF_ADDR, pwr_conf));
+
+	return EC_SUCCESS;
+}
+
+static int set_range(struct motion_sensor_t *s, int range, int round)
+{
+	int ret, range_reg_val;
+
+	range_reg_val = BMA4_RANGE_TO_REG(range);
+
+	/*
+	 * If rounding flag is set then set the range_val to nearest
+	 * valid value.
+	 */
+	if ((BMA4_REG_TO_RANGE(range_reg_val) < range) && round)
+		range_reg_val = BMA4_RANGE_TO_REG(range * 2);
+
+	mutex_lock(s->mutex);
+
+	/* Determine the new value of control reg and attempt to write it. */
+	ret = bma4_set_reg8(s, BMA4_ACCEL_RANGE_ADDR,
+			    range_reg_val << BMA4_ACCEL_RANGE_POS,
+			    BMA4_ACCEL_RANGE_MSK);
+
+	/* If successfully written, then save the range. */
+	if (ret == EC_SUCCESS)
+		s->current_range = BMA4_REG_TO_RANGE(range_reg_val);
+
+	mutex_unlock(s->mutex);
+
+	return ret;
+}
+
+static int get_resolution(const struct motion_sensor_t *s)
+{
+	return BMA4_12_BIT_RESOLUTION;
+}
+
+/**
+ * Return the data rate in millihz corresponding to an acc_odr register value.
+ *
+ * The input value is assumed to be in the range 1 to 15 inclusive, which is the
+ * entire range of documented values for acc_odr.
+ */
+static int bma4_reg_to_odr(uint8_t reg)
+{
+	/*
+	 * Maximum data rate is 12.8 kHz (12800000 mHz) at register value 0xf.
+	 * Reducing the register value by 1 halves data rate down to a minimum
+	 * of 0.78125 Hz at reg=1. Right-shifting the maximum value according
+	 * to the difference of the register value and maximum rate yields the
+	 * actual ODR, easily proven exhaustively:
+	 *
+	 * >>> [12800000 >> (0xf - reg) for reg in range(1, 16)]
+	 * [781, 1562, ... 6400000, 12800000]
+	 *
+	 * The register is documented to be valid only for values 1..=15, and
+	 * we can only cause undefined behavior if the register value is too
+	 * large; it's only wrong if reg = 0, not undefined.
+	 */
+	ASSERT(reg >= 1 && reg <= 15);
+	return 12800000 >> (0xf - reg);
+}
+
+/**
+ * Return a ACCEL_CONFIG register value for the given data rate in millihz.
+ *
+ * This always returns a valid acc_odr setting in the range of 1
+ * (DATA_RATE_0_78HZ) to 12 (DATA_RATE_1600HZ) inclusive. Rounds down if the
+ * requested rate cannot be exactly programmed.
+ */
+static uint8_t bma4_odr_to_reg(uint32_t odr)
+{
+	/*
+	 * Clamp ODR to supported sample rates, because any value outside that
+	 * range yields illegal register values. The lower bound is rounded up
+	 * to the nearest millihertz, since rounding down puts it out of range,
+	 * and the upper bound is limited to the highest non-reserved sample
+	 * rate (higher rates are documented but marked as reserved).
+	 */
+	odr = MIN(MAX(782 /* 25/32 Hz */, odr), 1600000);
+
+	/*
+	 * reg_to_odr (above) is fairly easy to understand, but this operation
+	 * is not as obvious to derive. It is derived algebraically, starting
+	 * with the reg_to_odr expression:
+	 *
+	 * 1. odr = 12800000 >> (15 - reg)
+	 * 2. Convert bitshift to division by an exponent so it can be
+	 *    manipulated more clearly: odr = 12800000 / (2**(15 - reg))
+	 * 3. Negate the exponent and replace division with multiplication:
+	 *    odr = 12800000 * 2**(reg - 15)
+	 * 4. Simplify by factoring out 2**12 (4096): odr = 3125 * 2**(reg - 3)
+	 * 5. Solve for reg: reg = log2(8 * odr / 3125)
+	 *
+	 * To avoid integer truncation issues, the multiplication is scaled by a
+	 * factor of 512 to yield log2(4096 * odr / 3125) - log2(512). For
+	 * high ODRs (greater than 800 Hz) the intermediate 4096 * odr exceeds
+	 * the range of a 32-bit integer, but losing bits in the division isn't
+	 * a problem for sufficiently large values so if the intermediate would
+	 * overflow 32 bits we instead skip the scaling by 512.
+	 */
+	uint32_t fp_shift = odr >= 800000 ? 0 : __fls(512);
+	uint32_t intermediate = (8 << fp_shift) * odr / 3125;
+
+	return __fls(intermediate) - fp_shift;
+}
+
+static int set_data_rate(const struct motion_sensor_t *s, int rate, int round)
+{
+	int ret = 0;
+	struct accelgyro_saved_data_t *data = s->drv_data;
+
+	mutex_lock(s->mutex);
+
+	if (rate == 0) {
+		/* Disable accel */
+		GOTO_ON_ERROR(out, bma4_set_reg8(s, BMA4_POWER_CTRL_ADDR, 0,
+						 BMA4_ACCEL_ENABLE_MSK));
+		data->odr = 0;
+	} else {
+		uint8_t odr_reg_val = bma4_odr_to_reg(rate);
+
+		ASSERT((odr_reg_val & BMA4_ACCEL_ODR_MSK) == odr_reg_val &&
+		       odr_reg_val != 0);
+
+		if (data->odr == 0) {
+			/* Accel was disabled; enable it */
+			GOTO_ON_ERROR(
+				out,
+				bma4_set_reg8(s, BMA4_POWER_CTRL_ADDR,
+					      BMA4_ENABLE
+						      << BMA4_ACCEL_ENABLE_POS,
+					      BMA4_ACCEL_ENABLE_MSK));
+		}
+
+		if ((bma4_reg_to_odr(odr_reg_val) < rate) && round)
+			/*
+			 * Go up to the next highest data rate, but don't exceed
+			 * the highest supported rate (odr_3k2 and higher are
+			 * documented but marked as reserved).
+			 */
+			odr_reg_val = MIN(BMA4_OUTPUT_DATA_RATE_1600HZ,
+					  odr_reg_val + 1);
+
+		/* Determine the new value of control reg and write it. */
+		GOTO_ON_ERROR(out,
+			      bma4_set_reg8(s, BMA4_ACCEL_CONFIG_ADDR,
+					    odr_reg_val << BMA4_ACCEL_ODR_POS,
+					    BMA4_ACCEL_ODR_MSK));
+
+		/* If successfully written, then save the new data rate. */
+		data->odr = bma4_reg_to_odr(odr_reg_val);
+	}
+
+out:
+	mutex_unlock(s->mutex);
+
+	return ret;
+}
+
+static int get_data_rate(const struct motion_sensor_t *s)
+{
+	struct accelgyro_saved_data_t *data = s->drv_data;
+
+	return data->odr;
+}
+
+static int set_offset(const struct motion_sensor_t *s, const int16_t *offset,
+		      int16_t temp)
+{
+	int ret;
+	intv3_t v = { offset[X], offset[Y], offset[Z] };
+
+	mutex_lock(s->mutex);
+
+	ret = write_accel_offset(s, v);
+
+	if (ret == EC_SUCCESS) {
+		/* Enable the offsets and backup to NVM */
+		ret = bma4_set_reg8(s, BMA4_NV_CONFIG_ADDR,
+				    (BMA4_ENABLE << BMA4_NV_ACCEL_OFFSET_POS),
+				    BMA4_NV_ACCEL_OFFSET_MSK);
+	}
+
+	mutex_unlock(s->mutex);
+
+	return ret;
+}
+
+static int get_offset(const struct motion_sensor_t *s, int16_t *offset,
+		      int16_t *temp)
+{
+	int i, val, ret;
+	intv3_t v;
+
+	mutex_lock(s->mutex);
+
+	for (i = X; i <= Z; i++) {
+		ret = bma4_read8(s, BMA4_OFFSET_0_ADDR + i, &val);
+		if (ret) {
+			mutex_unlock(s->mutex);
+			return ret;
+		}
+
+		if (val > 0x7f)
+			val -= 256;
+
+		v[i] = round_divide((int64_t)val * BMA4_OFFSET_ACC_MULTI_MG,
+				    BMA4_OFFSET_ACC_DIV_MG);
+	}
+
+	mutex_unlock(s->mutex);
+
+	/* Offset is in milli-g */
+	rotate(v, *s->rot_standard_ref, v);
+	offset[X] = v[X];
+	offset[Y] = v[Y];
+	offset[Z] = v[Z];
+
+	*temp = (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP;
+
+	return EC_SUCCESS;
+}
+
+/*
+ * Convert raw sensor register values in acc to 3d vector v, applying the
+ * sensor's standard rotation to the result.
+ */
+static void swizzle_sample_data(const struct motion_sensor_t *s,
+				const uint8_t acc[6], intv3_t v)
+{
+	/*
+	 * Convert acceleration to a signed 16-bit number. Note, based on
+	 * the order of the registers:
+	 *
+	 * acc[0] = X_AXIS_LSB -> bit 7~4 for value, bit 0 for new data bit
+	 * acc[1] = X_AXIS_MSB
+	 * acc[2] = Y_AXIS_LSB -> bit 7~4 for value, bit 0 for new data bit
+	 * acc[3] = Y_AXIS_MSB
+	 * acc[4] = Z_AXIS_LSB -> bit 7~4 for value, bit 0 for new data bit
+	 * acc[5] = Z_AXIS_MSB
+	 */
+	for (int i = X; i <= Z; i++)
+		v[i] = (((int8_t)acc[i * 2 + 1]) << 8) | (acc[i * 2] & 0xf0);
+
+	rotate(v, *s->rot_standard_ref, v);
+}
+
+static int read(const struct motion_sensor_t *s, intv3_t v)
+{
+	uint8_t acc[6];
+	int ret;
+
+	mutex_lock(s->mutex);
+
+	/* Read 6 bytes starting at X_AXIS_LSB. */
+	ret = i2c_read_block(s->port, s->i2c_spi_addr_flags, BMA4_DATA_8_ADDR,
+			     acc, 6);
+
+	mutex_unlock(s->mutex);
+
+	if (ret)
+		return ret;
+
+	swizzle_sample_data(s, acc, v);
+
+	return EC_SUCCESS;
+}
+
+static int init(struct motion_sensor_t *s)
+{
+	int ret = 0, reg_val;
+	struct accelgyro_saved_data_t *data = s->drv_data;
+
+	/* This driver requires a mutex. Assert if mutex is not supplied. */
+	ASSERT(s->mutex);
+
+	/* Read accelerometer's CHID ID */
+	RETURN_ERROR(bma4_read8(s, BMA4_CHIP_ID_ADDR, &reg_val));
+
+	if (s->chip != MOTIONSENSE_CHIP_BMA422 || reg_val != BMA422_CHIP_ID)
+		return EC_ERROR_HW_INTERNAL;
+
+	mutex_lock(s->mutex);
+
+	/*
+	 * Disable accelerometer by default, set ODR to match. This avoids
+	 * generating FIFO interrupts until we actually care about the data.
+	 */
+	GOTO_ON_ERROR(out, bma4_set_reg8(s, BMA4_POWER_CTRL_ADDR, 0,
+					 BMA4_ACCEL_ENABLE_MSK));
+	data->odr = 0;
+
+	/* Configure interrupt-driven acquisition if desired */
+	if (IS_ENABLED(BMA4XX_USE_INTERRUPTS)) {
+		GOTO_ON_ERROR(out,
+			      bma4_write8(s, BMA4_CMD_ADDR, BMA4_FIFO_FLUSH));
+		/*
+		 * Enable all interrupts on INT1 pin, active-low push-pull
+		 * output, latched until status register read.
+		 */
+		GOTO_ON_ERROR(out, bma4_write8(s, BMA4_INT_LATCH_ADDR,
+					       BMA4_INT_LATCH));
+		GOTO_ON_ERROR(out, bma4_write8(s, BMA4_INT1_IO_CTRL_ADDR,
+					       BMA4_INT1_OUTPUT_EN));
+		GOTO_ON_ERROR(out, bma4_write8(s, BMA4_INT_MAP_DATA_ADDR,
+					       BMA4_INT1_DRDY | BMA4_INT1_FWM |
+						       BMA4_INT1_FFULL));
+		/* Enable FIFO in headerless mode, accel data only */
+		GOTO_ON_ERROR(out, bma4_write8(s, BMA4_FIFO_CONFIG_1_ADDR,
+					       BMA4_FIFO_ACC_EN));
+	}
+
+out:
+	mutex_unlock(s->mutex);
+
+	if (ret)
+		return ret;
+
+	return sensor_init_done(s);
+}
+
+#ifdef BMA4XX_USE_INTERRUPTS
+static uint32_t last_irq_timestamp;
+
+/* Handle IRQ from sensor: schedule read from task context */
+void bma4xx_interrupt(enum gpio_signal signal)
+{
+	__atomic_store_n(&last_irq_timestamp, __hw_clock_source_read(),
+			 __ATOMIC_RELAXED);
+	task_set_event(TASK_ID_MOTIONSENSE, CONFIG_ACCEL_BMA4XX_INT_EVENT);
+}
+
+/* Process FIFO data read from accel and push data to host */
+static void process_fifo_data(struct motion_sensor_t *s, uint8_t *data,
+			      size_t data_bytes, uint32_t timestamp)
+{
+	ASSERT(data_bytes % 6 == 0);
+
+	for (int i = 0; i < data_bytes; i += 6) {
+		int *v = s->raw_xyz;
+
+		if (data[i + 1] == 0x80 && data[i] == 0) {
+			/* 0x8000 means read overrun; out of data */
+			break;
+		}
+		swizzle_sample_data(s, &data[i], v);
+
+		if (IS_ENABLED(CONFIG_ACCEL_SPOOF_MODE) &&
+		    s->flags & MOTIONSENSE_FLAG_IN_SPOOF_MODE)
+			v = s->spoof_xyz;
+		if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
+			struct ec_response_motion_sensor_data response = {
+				.sensor_num = s - motion_sensors,
+				.data = {
+					[X] = v[X],
+					[Y] = v[Y],
+					[Z] = v[Z],
+				},
+			};
+			motion_sense_fifo_stage_data(&response, s, 3,
+						     timestamp);
+		} else {
+			motion_sense_push_raw_xyz(s);
+		}
+	}
+}
+
+/* Handle interrupt in task context */
+static int irq_handler(struct motion_sensor_t *s, uint32_t *event)
+{
+	uint32_t irq_timestamp =
+		__atomic_load_n(&last_irq_timestamp, __ATOMIC_RELAXED);
+	bool read_any_data = false;
+	int interrupt_status_reg, fifo_depth;
+
+	/* Read interrupt status, also clears pending IRQs */
+	RETURN_ERROR(bma4_read8(s, BMA4_INT_STATUS_1, &interrupt_status_reg));
+	if ((interrupt_status_reg &
+	     (BMA4_FFULL_INT | BMA4_FWM_INT | BMA4_ACC_DRDY_INT)) == 0) {
+		return EC_ERROR_NOT_HANDLED;
+	}
+
+	RETURN_ERROR(bma4_read16(s, BMA4_FIFO_LENGTH_0_ADDR, &fifo_depth));
+	while (fifo_depth > 0) {
+		/* large enough buffer for 4 samples */
+		uint8_t fifo_data[24];
+		int fifo_read = MIN(ARRAY_SIZE(fifo_data), fifo_depth);
+		int ret;
+
+		mutex_lock(s->mutex);
+		ret = i2c_read_block(s->port, s->i2c_spi_addr_flags,
+				     BMA4_FIFO_DATA_ADDR, fifo_data, fifo_read);
+		fifo_depth -= fifo_read;
+		mutex_unlock(s->mutex);
+		if (ret)
+			return ret;
+
+		process_fifo_data(s, fifo_data, fifo_read, irq_timestamp);
+		read_any_data = true;
+	}
+
+	if (IS_ENABLED(CONFIG_ACCEL_FIFO) && read_any_data) {
+		motion_sense_fifo_commit_data();
+	}
+
+	return EC_SUCCESS;
+}
+#endif /* BMA4XX_USE_INTERRUPTS */
+
+const struct accelgyro_drv bma4_accel_drv = {
+	.init = init,
+	.read = read,
+	.set_range = set_range,
+	.get_resolution = get_resolution,
+	.set_data_rate = set_data_rate,
+	.get_data_rate = get_data_rate,
+	.set_offset = set_offset,
+	.get_offset = get_offset,
+	.perform_calib = perform_calib,
+#ifdef BMA4XX_USE_INTERRUPTS
+	.irq_handler = irq_handler,
+#endif
+};
diff --git a/driver/accel_bma4xx.h b/driver/accel_bma4xx.h
new file mode 100644
index 0000000000..bb89fd3971
--- /dev/null
+++ b/driver/accel_bma4xx.h
@@ -0,0 +1,212 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* BMA4XX gsensor module for Chrome EC */
+
+#ifndef __CROS_EC_ACCEL_BMA4XX_H
+#define __CROS_EC_ACCEL_BMA4XX_H
+
+#include "config.h"
+
+#define BMA4_I2C_ADDR_PRIMARY 0x18
+#define BMA4_I2C_ADDR_SECONDARY 0x19
+#define BMA4_I2C_BMM150_ADDR 0x10
+
+/* Chip-specific registers */
+#define BMA4_CHIP_ID_ADDR 0x00
+#define BMA4_CHIP_ID_MIN 0x10
+#define BMA4_CHIP_ID_MAX 0x15
+
+#define BMA4_ERROR_ADDR 0x02
+#define BMA4_FATAL_ERR_MSK 0x01
+#define BMA4_CMD_ERR_POS 1
+#define BMA4_CMD_ERR_MSK 0x02
+#define BMA4_ERR_CODE_POS 2
+#define BMA4_ERR_CODE_MSK 0x1C
+#define BMA4_FIFO_ERR_POS 6
+#define BMA4_FIFO_ERR_MSK 0x40
+#define BMA4_AUX_ERR_POS 7
+#define BMA4_AUX_ERR_MSK 0x80
+
+#define BMA4_STATUS_ADDR 0x03
+#define BMA4_STAT_DATA_RDY_ACCEL_POS 7
+#define BMA4_STAT_DATA_RDY_ACCEL_MSK 0x80
+
+#define BMA4_DATA_0_ADDR 0x0A
+#define BMA4_DATA_8_ADDR 0x12
+
+#define BMA4_SENSORTIME_0_ADDR 0x18
+#define BMA4_INT_STAT_0_ADDR 0x1C
+#define BMA4_INT_STAT_1_ADDR 0x1D
+#define BMA4_STEP_CNT_OUT_0_ADDR 0x1E
+#define BMA4_HIGH_G_OUT_ADDR 0x1F
+#define BMA4_TEMPERATURE_ADDR 0x22
+
+#define BMA4_INT_STATUS_1 0x1D
+#define BMA4_FFULL_INT BIT(0)
+#define BMA4_FWM_INT BIT(1)
+#define BMA4_ACC_DRDY_INT BIT(7)
+
+#define BMA4_FIFO_LENGTH_0_ADDR 0x24
+#define BMA4_FIFO_DATA_ADDR 0x26
+#define BMA4_ACTIVITY_OUT_ADDR 0x27
+#define BMA4_ORIENTATION_OUT_ADDR 0x28
+
+#define BMA4_INTERNAL_STAT 0x2A
+#define BMA4_ASIC_INITIALIZED 0x01
+
+#define BMA4_ACCEL_CONFIG_ADDR 0x40
+#define BMA4_ACCEL_ODR_POS 0
+#define BMA4_ACCEL_ODR_MSK 0x0F
+#define BMA4_ACCEL_BW_POS 4
+#define BMA4_ACCEL_BW_MSK 0x70
+#define BMA4_ACCEL_PERFMODE_POS 7
+#define BMA4_ACCEL_PERFMODE_MSK 0x80
+#define BMA4_OUTPUT_DATA_RATE_0_78HZ 0x01
+#define BMA4_OUTPUT_DATA_RATE_1_56HZ 0x02
+#define BMA4_OUTPUT_DATA_RATE_3_12HZ 0x03
+#define BMA4_OUTPUT_DATA_RATE_6_25HZ 0x04
+#define BMA4_OUTPUT_DATA_RATE_12_5HZ 0x05
+#define BMA4_OUTPUT_DATA_RATE_25HZ 0x06
+#define BMA4_OUTPUT_DATA_RATE_50HZ 0x07
+#define BMA4_OUTPUT_DATA_RATE_100HZ 0x08
+#define BMA4_OUTPUT_DATA_RATE_200HZ 0x09
+#define BMA4_OUTPUT_DATA_RATE_400HZ 0x0A
+#define BMA4_OUTPUT_DATA_RATE_800HZ 0x0B
+#define BMA4_OUTPUT_DATA_RATE_1600HZ 0x0C
+#define BMA4_ACCEL_OSR4_AVG1 0
+#define BMA4_ACCEL_OSR2_AVG2 1
+#define BMA4_ACCEL_NORMAL_AVG4 2
+#define BMA4_ACCEL_CIC_AVG8 3
+#define BMA4_ACCEL_RES_AVG16 4
+#define BMA4_ACCEL_RES_AVG32 5
+#define BMA4_ACCEL_RES_AVG64 6
+#define BMA4_ACCEL_RES_AVG128 7
+#define BMA4_CIC_AVG_MODE 0
+#define BMA4_CONTINUOUS_MODE 1
+
+#define BMA4_ACCEL_RANGE_ADDR 0x41
+#define BMA4_ACCEL_RANGE_POS 0
+#define BMA4_ACCEL_RANGE_MSK 0x03
+#define BMA4_ACCEL_RANGE_2G 0
+#define BMA4_ACCEL_RANGE_4G 1
+#define BMA4_ACCEL_RANGE_8G 2
+#define BMA4_ACCEL_RANGE_16G 3
+
+#define BMA4_FIFO_CONFIG_0_ADDR 0x48
+#define BMA4_FIFO_STOP_ON_FULL BIT(0)
+#define BMA4_FIFO_TIME_EN BIT(1)
+
+#define BMA4_FIFO_CONFIG_1_ADDR 0x49
+#define BMA4_FIFO_TAG_INT2_EN BIT(2)
+#define BMA4_FIFO_TAG_INT1_EN BIT(3)
+#define BMA4_FIFO_HEADER_EN BIT(4)
+#define BMA4_FIFO_AUX_EN BIT(5)
+#define BMA4_FIFO_ACC_EN BIT(6)
+
+#define BMA4_INT1_IO_CTRL_ADDR 0x53
+#define BMA4_INT1_OUTPUT_EN BIT(3)
+
+#define BMA4_INT_LATCH_ADDR 0x55
+#define BMA4_INT_LATCH BIT(0)
+
+#define BMA4_INT_MAP_DATA_ADDR 0x58
+#define BMA4_INT2_DRDY BIT(6)
+#define BMA4_INT2_FWM BIT(5)
+#define BMA4_INT2_FFULL BIT(4)
+#define BMA4_INT1_DRDY BIT(2)
+#define BMA4_INT1_FWM BIT(1)
+#define BMA4_INT1_FFULL BIT(0)
+
+#define BMA4_RESERVED_REG_5B_ADDR 0x5B
+#define BMA4_RESERVED_REG_5C_ADDR 0x5C
+#define BMA4_FEATURE_CONFIG_ADDR 0x5E
+#define BMA4_INTERNAL_ERROR 0x5F
+#define BMA4_IF_CONFIG_ADDR 0x6B
+#define BMA4_FOC_ACC_CONF_VAL 0xB7
+
+#define BMA4_NV_CONFIG_ADDR 0x70
+#define BMA4_NV_ACCEL_OFFSET_POS 3
+#define BMA4_NV_ACCEL_OFFSET_MSK 0x08
+
+#define BMA4_OFFSET_0_ADDR 0x71
+#define BMA4_OFFSET_1_ADDR 0x72
+#define BMA4_OFFSET_2_ADDR 0x73
+
+#define BMA4_POWER_CONF_ADDR 0x7C
+#define BMA4_ADVANCE_POWER_SAVE_POS 0
+#define BMA4_ADVANCE_POWER_SAVE_MSK 0x01
+
+#define BMA4_POWER_CTRL_ADDR 0x7D
+#define BMA4_ACCEL_ENABLE_POS 2
+#define BMA4_ACCEL_ENABLE_MSK 0x04
+#define BMA4_ENABLE 0x01
+#define BMA4_DISABLE 0x00
+
+#define BMA4_CMD_ADDR 0x7E
+#define BMA4_NVM_PROG 0xA0
+#define BMA4_FIFO_FLUSH 0xB0
+#define BMA4_SOFT_RESET 0xB6
+
+/* Other definitions */
+#define BMA4_X_AXIS 0
+#define BMA4_Y_AXIS 1
+#define BMA4_Z_AXIS 2
+
+#define BMA4_12_BIT_RESOLUTION 12
+#define BMA4_14_BIT_RESOLUTION 14
+#define BMA4_16_BIT_RESOLUTION 16
+
+/*
+ * The max positive value of accel data is 0x07FF, equal to range(g)
+ * So, in order to get +1g, divide the 0x07FF by range
+ */
+#define BMA4_ACC_DATA_PLUS_1G(range) (0x07FF / (range))
+
+/* For offset registers 1LSB - 3.9mg */
+#define BMA4_OFFSET_ACC_MULTI_MG (3900 * 1000)
+#define BMA4_OFFSET_ACC_DIV_MG 1000000
+
+#define BMA4_FOC_SAMPLE_LIMIT 32
+
+/* Min and Max sampling frequency in mHz */
+#define BMA4_ACCEL_MIN_FREQ 12500
+#define BMA4_ACCEL_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(1600000, 6250)
+
+#define BMA4_RANGE_TO_REG(_range)                              \
+	((_range) < 8 ? BMA4_ACCEL_RANGE_2G + ((_range) / 4) : \
+			BMA4_ACCEL_RANGE_8G + ((_range) / 16))
+
+#define BMA4_REG_TO_RANGE(_reg)                        \
+	((_reg) < BMA4_ACCEL_RANGE_8G ? 2 + (_reg)*2 : \
+					8 + ((_reg)-BMA4_ACCEL_RANGE_8G) * 8)
+
+extern const struct accelgyro_drv bma4_accel_drv;
+
+#if defined(CONFIG_ZEPHYR)
+#include <zephyr/devicetree.h>
+
+#if DT_NODE_EXISTS(DT_ALIAS(bma4xx_int))
+/*
+ * Get the motion sensor ID of the BMA4xx sensor that generates the interrupt.
+ * The interrupt is converted to the event and transferred to motion
+ * sense task that actually handles the interrupt.
+ *
+ * Here, we use alias to get the motion sensor ID
+ *
+ * e.g) base_accel is the label of a child node in /motionsense-sensors
+ * aliases {
+ *     bma4xx-int = &base_accel;
+ * };
+ */
+#define CONFIG_ACCEL_BMA4XX_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(SENSOR_ID(DT_ALIAS(bma4xx_int)))
+
+#include "gpio_signal.h"
+void bma4xx_interrupt(enum gpio_signal signal);
+#endif /* DT_NODE_EXISTS */
+#endif /* CONFIG_ZEPHYR */
+
+#endif /* __CROS_EC_ACCEL_BMA4XX_H */
diff --git a/driver/accel_kionix.c b/driver/accel_kionix.c
index ec7953551f..c04855c89d 100644
--- a/driver/accel_kionix.c
+++ b/driver/accel_kionix.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,24 +9,29 @@
  * Supported: KX022, KXCJ9
  */
 
+#include "accel_kionix.h"
+#include "accel_kx022.h"
+#include "accel_kxcj9.h"
 #include "accelgyro.h"
 #include "common.h"
 #include "console.h"
-#include "driver/accel_kionix.h"
-#include "driver/accel_kx022.h"
-#include "driver/accel_kxcj9.h"
 #include "i2c.h"
 #include "math_util.h"
+#include "motion_orientation.h"
 #include "spi.h"
 #include "task.h"
 #include "util.h"
 
 #define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
 
 /* Number of times to attempt to enable sensor before giving up. */
 #define SENSOR_ENABLE_ATTEMPTS 3
 
+#if !defined(CONFIG_ACCEL_KXCJ9) && !defined(CONFIG_ACCEL_KX022)
+#error "Must use either KXCJ9 or KX022"
+#endif
+
 #if defined(CONFIG_ACCEL_KXCJ9) && !defined(CONFIG_ACCEL_KX022)
 #define V(s_) 1
 #elif defined(CONFIG_ACCEL_KX022) && !defined(CONFIG_ACCEL_KXCJ9)
@@ -41,29 +46,28 @@
 #define T(s_) V(s_)
 #endif /* !defined(CONFIG_ACCEL_KXCJ9) || !defined(CONFIG_ACCEL_KX022) */
 
+STATIC_IF(CONFIG_KX022_ORIENTATION_SENSOR)
+int check_orientation_locked(const struct motion_sensor_t *s);
+
 /* List of range values in +/-G's and their associated register values. */
 static const struct accel_param_pair ranges[][3] = {
 #ifdef CONFIG_ACCEL_KX022
-	{ {2, KX022_GSEL_2G},
-	  {4, KX022_GSEL_4G},
-	  {8, KX022_GSEL_8G} },
+	{ { 2, KX022_GSEL_2G }, { 4, KX022_GSEL_4G }, { 8, KX022_GSEL_8G } },
 #endif /* defined(CONFIG_ACCEL_KX022) */
 #ifdef CONFIG_ACCEL_KXCJ9
-	{ {2, KXCJ9_GSEL_2G},
-	  {4, KXCJ9_GSEL_4G},
-	  {8, KXCJ9_GSEL_8G_14BIT} },
+	{ { 2, KXCJ9_GSEL_2G },
+	  { 4, KXCJ9_GSEL_4G },
+	  { 8, KXCJ9_GSEL_8G_14BIT } },
 #endif /* defined(CONFIG_ACCEL_KXCJ9) */
 };
 
 /* List of resolution values in bits and their associated register values. */
 static const struct accel_param_pair resolutions[][2] = {
 #ifdef CONFIG_ACCEL_KX022
-	{ {8,  KX022_RES_8BIT},
-	  {16, KX022_RES_16BIT} },
+	{ { 8, KX022_RES_8BIT }, { 16, KX022_RES_16BIT } },
 #endif /* defined(CONFIG_ACCEL_KX022) */
 #ifdef CONFIG_ACCEL_KXCJ9
-	{ {8,  KXCJ9_RES_8BIT},
-	  {12, KXCJ9_RES_12BIT} },
+	{ { 8, KXCJ9_RES_8BIT }, { 12, KXCJ9_RES_12BIT } },
 #endif /* defined(CONFIG_ACCEL_KXCJ9) */
 };
 
@@ -71,34 +75,34 @@ static const struct accel_param_pair resolutions[][2] = {
 static const struct accel_param_pair datarates[][13] = {
 #ifdef CONFIG_ACCEL_KX022
 	/* One duplicate because table sizes must match. */
-	{ {781,     KX022_OSA_0_781HZ},
-	  {781,     KX022_OSA_0_781HZ},
-	  {1563,    KX022_OSA_1_563HZ},
-	  {3125,    KX022_OSA_3_125HZ},
-	  {6250,    KX022_OSA_6_250HZ},
-	  {12500,   KX022_OSA_12_50HZ},
-	  {25000,   KX022_OSA_25_00HZ},
-	  {50000,   KX022_OSA_50_00HZ},
-	  {100000,  KX022_OSA_100_0HZ},
-	  {200000,  KX022_OSA_200_0HZ},
-	  {400000,  KX022_OSA_400_0HZ},
-	  {800000,  KX022_OSA_800_0HZ},
-	  {1600000, KX022_OSA_1600HZ} },
+	{ { 781, KX022_OSA_0_781HZ },
+	  { 781, KX022_OSA_0_781HZ },
+	  { 1563, KX022_OSA_1_563HZ },
+	  { 3125, KX022_OSA_3_125HZ },
+	  { 6250, KX022_OSA_6_250HZ },
+	  { 12500, KX022_OSA_12_50HZ },
+	  { 25000, KX022_OSA_25_00HZ },
+	  { 50000, KX022_OSA_50_00HZ },
+	  { 100000, KX022_OSA_100_0HZ },
+	  { 200000, KX022_OSA_200_0HZ },
+	  { 400000, KX022_OSA_400_0HZ },
+	  { 800000, KX022_OSA_800_0HZ },
+	  { 1600000, KX022_OSA_1600HZ } },
 #endif /* defined(CONFIG_ACCEL_KX022) */
 #ifdef CONFIG_ACCEL_KXCJ9
-	{ {0,       KXCJ9_OSA_0_000HZ},
-	  {781,     KXCJ9_OSA_0_781HZ},
-	  {1563,    KXCJ9_OSA_1_563HZ},
-	  {3125,    KXCJ9_OSA_3_125HZ},
-	  {6250,    KXCJ9_OSA_6_250HZ},
-	  {12500,   KXCJ9_OSA_12_50HZ},
-	  {25000,   KXCJ9_OSA_25_00HZ},
-	  {50000,   KXCJ9_OSA_50_00HZ},
-	  {100000,  KXCJ9_OSA_100_0HZ},
-	  {200000,  KXCJ9_OSA_200_0HZ},
-	  {400000,  KXCJ9_OSA_400_0HZ},
-	  {800000,  KXCJ9_OSA_800_0HZ},
-	  {1600000, KXCJ9_OSA_1600_HZ} },
+	{ { 0, KXCJ9_OSA_0_000HZ },
+	  { 781, KXCJ9_OSA_0_781HZ },
+	  { 1563, KXCJ9_OSA_1_563HZ },
+	  { 3125, KXCJ9_OSA_3_125HZ },
+	  { 6250, KXCJ9_OSA_6_250HZ },
+	  { 12500, KXCJ9_OSA_12_50HZ },
+	  { 25000, KXCJ9_OSA_25_00HZ },
+	  { 50000, KXCJ9_OSA_50_00HZ },
+	  { 100000, KXCJ9_OSA_100_0HZ },
+	  { 200000, KXCJ9_OSA_200_0HZ },
+	  { 400000, KXCJ9_OSA_400_0HZ },
+	  { 800000, KXCJ9_OSA_800_0HZ },
+	  { 1600000, KXCJ9_OSA_1600_HZ } },
 #endif /* defined(CONFIG_ACCEL_KXCJ9) */
 };
 
@@ -119,7 +123,7 @@ static int find_param_index(const int eng_val, const int round_up,
 		if (eng_val <= pairs[i].val)
 			return i;
 
-		if (eng_val < pairs[i+1].val) {
+		if (eng_val < pairs[i + 1].val) {
 			if (round_up)
 				return i + 1;
 			else
@@ -133,27 +137,25 @@ static int find_param_index(const int eng_val, const int round_up,
 /**
  * Read register from accelerometer.
  */
-static int raw_read8(const int port,
-		     const uint16_t i2c_spi_addr_flags,
+static int raw_read8(const int port, const uint16_t i2c_spi_addr_flags,
 		     const int reg, int *data_ptr)
 {
 	int rv = EC_ERROR_INVAL;
 
-	if (SLAVE_IS_SPI(i2c_spi_addr_flags)) {
+	if (ACCEL_ADDR_IS_SPI(i2c_spi_addr_flags)) {
 #ifdef CONFIG_SPI_ACCEL_PORT
 		uint8_t val;
 		uint8_t cmd = 0x80 | reg;
 
 		rv = spi_transaction(
-			&spi_devices[SLAVE_GET_SPI_ADDR(i2c_spi_addr_flags)],
+			&spi_devices[ACCEL_GET_SPI_ADDR(i2c_spi_addr_flags)],
 			&cmd, 1, &val, 1);
 		if (rv == EC_SUCCESS)
 			*data_ptr = val;
 
 #endif
 	} else {
-		rv = i2c_read8(port, i2c_spi_addr_flags,
-			       reg, data_ptr);
+		rv = i2c_read8(port, i2c_spi_addr_flags, reg, data_ptr);
 	}
 	return rv;
 }
@@ -161,43 +163,40 @@ static int raw_read8(const int port,
 /**
  * Write register from accelerometer.
  */
-static int raw_write8(const int port,
-		      const uint16_t i2c_spi_addr_flags,
+static int raw_write8(const int port, const uint16_t i2c_spi_addr_flags,
 		      const int reg, int data)
 {
 	int rv = EC_ERROR_INVAL;
 
-	if (SLAVE_IS_SPI(i2c_spi_addr_flags)) {
+	if (ACCEL_ADDR_IS_SPI(i2c_spi_addr_flags)) {
 #ifdef CONFIG_SPI_ACCEL_PORT
 		uint8_t cmd[2] = { reg, data };
 
 		rv = spi_transaction(
-			&spi_devices[SLAVE_GET_SPI_ADDR(i2c_spi_addr_flags)],
+			&spi_devices[ACCEL_GET_SPI_ADDR(i2c_spi_addr_flags)],
 			cmd, 2, NULL, 0);
 #endif
 	} else {
-		rv = i2c_write8(port, i2c_spi_addr_flags,
-				reg, data);
+		rv = i2c_write8(port, i2c_spi_addr_flags, reg, data);
 	}
 	return rv;
 }
 
-static int raw_read_multi(const int port,
-			  const uint16_t i2c_spi_addr_flags,
+static int raw_read_multi(const int port, const uint16_t i2c_spi_addr_flags,
 			  uint8_t reg, uint8_t *rxdata, int rxlen)
 {
 	int rv = EC_ERROR_INVAL;
 
-	if (SLAVE_IS_SPI(i2c_spi_addr_flags)) {
+	if (ACCEL_ADDR_IS_SPI(i2c_spi_addr_flags)) {
 #ifdef CONFIG_SPI_ACCEL_PORT
 		reg |= 0x80;
 		rv = spi_transaction(
-			&spi_devices[SLAVE_GET_SPI_ADDR(i2c_spi_addr_flags)],
+			&spi_devices[ACCEL_GET_SPI_ADDR(i2c_spi_addr_flags)],
 			&reg, 1, rxdata, rxlen);
 #endif
 	} else {
-		rv = i2c_read_block(port, i2c_spi_addr_flags,
-				    reg, rxdata, rxlen);
+		rv = i2c_read_block(port, i2c_spi_addr_flags, reg, rxdata,
+				    rxlen);
 	}
 	return rv;
 }
@@ -225,15 +224,13 @@ static int disable_sensor(const struct motion_sensor_t *s, int *reg_val)
 	 * so that we can restore it later.
 	 */
 	for (i = 0; i < SENSOR_ENABLE_ATTEMPTS; i++) {
-		ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-				reg, reg_val);
+		ret = raw_read8(s->port, s->i2c_spi_addr_flags, reg, reg_val);
 		if (ret != EC_SUCCESS)
 			continue;
 
 		*reg_val &= ~pc1_field;
 
-		ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-				 reg, *reg_val);
+		ret = raw_write8(s->port, s->i2c_spi_addr_flags, reg, *reg_val);
 		if (ret == EC_SUCCESS)
 			return EC_SUCCESS;
 	}
@@ -258,20 +255,18 @@ static int enable_sensor(const struct motion_sensor_t *s, int reg_val)
 	pc1_field = KIONIX_PC1_FIELD(V(s));
 
 	for (i = 0; i < SENSOR_ENABLE_ATTEMPTS; i++) {
-		ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-				reg, &reg_val);
+		ret = raw_read8(s->port, s->i2c_spi_addr_flags, reg, &reg_val);
 		if (ret != EC_SUCCESS)
 			continue;
 
-#ifdef CONFIG_KX022_ORIENTATION_SENSOR
 		/* Enable tilt orientation mode  if lid sensor */
-		if ((s->location == MOTIONSENSE_LOC_LID) && (V(s) == 0))
+		if (IS_ENABLED(CONFIG_KX022_ORIENTATION_SENSOR) &&
+		    (s->location == MOTIONSENSE_LOC_LID) && (V(s) == 0))
 			reg_val |= KX022_CNTL1_TPE;
-#endif
 
 		/* Enable accelerometer based on reg_val value. */
-		ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-				 reg, reg_val | pc1_field);
+		ret = raw_write8(s->port, s->i2c_spi_addr_flags, reg,
+				 reg_val | pc1_field);
 
 		/* On first success, we are done. */
 		if (ret == EC_SUCCESS)
@@ -305,8 +300,7 @@ static int set_value(const struct motion_sensor_t *s, int reg, int val,
 
 	/* Determine new value of control reg and attempt to write it. */
 	reg_val_new = (reg_val & ~field) | val;
-	ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-			 reg, reg_val_new);
+	ret = raw_write8(s->port, s->i2c_spi_addr_flags, reg, reg_val_new);
 
 	/* If successfully written, then save the range. */
 	if (ret == EC_SUCCESS)
@@ -317,10 +311,9 @@ static int set_value(const struct motion_sensor_t *s, int reg, int val,
 	return ret;
 }
 
-static int set_range(const struct motion_sensor_t *s, int range, int rnd)
+static int set_range(struct motion_sensor_t *s, int range, int rnd)
 {
 	int ret, index, reg, range_field, range_val;
-	struct kionix_accel_data *data = s->drv_data;
 
 	/* Find index for interface pair matching the specified range. */
 	index = find_param_index(range, rnd, ranges[T(s)],
@@ -331,17 +324,10 @@ static int set_range(const struct motion_sensor_t *s, int range, int rnd)
 
 	ret = set_value(s, reg, range_val, range_field);
 	if (ret == EC_SUCCESS)
-		data->base.range = ranges[T(s)][index].val;
+		s->current_range = ranges[T(s)][index].val;
 	return ret;
 }
 
-static int get_range(const struct motion_sensor_t *s)
-{
-	struct kionix_accel_data *data = s->drv_data;
-
-	return data->base.range;
-}
-
 static int set_resolution(const struct motion_sensor_t *s, int res, int rnd)
 {
 	int ret, index, reg, res_field, res_val;
@@ -381,7 +367,7 @@ static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
 
 	ret = set_value(s, reg, odr_val, odr_field);
 	if (ret == EC_SUCCESS)
-		data->base.odr =  datarates[T(s)][index].val;
+		data->base.odr = datarates[T(s)][index].val;
 	return ret;
 }
 
@@ -414,10 +400,8 @@ static int get_offset(const struct motion_sensor_t *s, int16_t *offset,
 	return EC_SUCCESS;
 }
 
-#ifdef CONFIG_KX022_ORIENTATION_SENSOR
-static enum motionsensor_orientation kx022_convert_orientation(
-		const struct motion_sensor_t *s,
-		int orientation)
+static __maybe_unused enum motionsensor_orientation
+kx022_convert_orientation(const struct motion_sensor_t *s, int orientation)
 {
 	enum motionsensor_orientation res = MOTIONSENSE_ORIENTATION_UNKNOWN;
 
@@ -437,18 +421,19 @@ static enum motionsensor_orientation kx022_convert_orientation(
 	default:
 		break;
 	}
-	res = motion_sense_remap_orientation(s, res);
+	res = motion_orientation_remap(s, res);
 	return res;
 }
 
+#ifdef CONFIG_KX022_ORIENTATION_SENSOR
 static int check_orientation_locked(const struct motion_sensor_t *s)
 {
 	struct kionix_accel_data *data = s->drv_data;
 	int orientation, raw_orientation;
 	int ret;
 
-	ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-			KX022_TSCP, &raw_orientation);
+	ret = raw_read8(s->port, s->i2c_spi_addr_flags, KX022_TSCP,
+			&raw_orientation);
 	if (ret != EC_SUCCESS)
 		return ret;
 
@@ -457,28 +442,46 @@ static int check_orientation_locked(const struct motion_sensor_t *s)
 	if (raw_orientation && (raw_orientation != data->raw_orientation)) {
 		data->raw_orientation = raw_orientation;
 		orientation = kx022_convert_orientation(s, raw_orientation);
-		SET_ORIENTATION(s, orientation);
+		*motion_orientation_ptr(s) = orientation;
 	}
 	return ret;
 }
+
+bool motion_orientation_changed(const struct motion_sensor_t *s)
+{
+	return ((struct kionix_accel_data *)s->drv_data)->orientation !=
+	       ((struct kionix_accel_data *)s->drv_data)->last_orientation;
+}
+
+enum motionsensor_orientation *
+motion_orientation_ptr(const struct motion_sensor_t *s)
+{
+	return &((struct kionix_accel_data *)s->drv_data)->orientation;
+}
+
+void motion_orientation_update(const struct motion_sensor_t *s)
+{
+	((struct kionix_accel_data *)s->drv_data)->last_orientation =
+		((struct kionix_accel_data *)s->drv_data)->orientation;
+}
+
 #endif
 
 static int read(const struct motion_sensor_t *s, intv3_t v)
 {
 	uint8_t acc[6];
 	uint8_t reg;
-	int ret, i, range, resolution;
+	int ret, i, resolution;
 	struct kionix_accel_data *data = s->drv_data;
 
 	/* Read 6 bytes starting at XOUT_L. */
 	reg = KIONIX_XOUT_L(V(s));
 	mutex_lock(s->mutex);
 	ret = raw_read_multi(s->port, s->i2c_spi_addr_flags, reg, acc, 6);
-#ifdef CONFIG_KX022_ORIENTATION_SENSOR
-	if ((s->location == MOTIONSENSE_LOC_LID) && (V(s) == 0) &&
-			(ret == EC_SUCCESS))
+	if (IS_ENABLED(CONFIG_KX022_ORIENTATION_SENSOR) &&
+	    (s->location == MOTIONSENSE_LOC_LID) && (V(s) == 0) &&
+	    (ret == EC_SUCCESS))
 		ret = check_orientation_locked(s);
-#endif
 	mutex_unlock(s->mutex);
 
 	if (ret != EC_SUCCESS)
@@ -501,7 +504,7 @@ static int read(const struct motion_sensor_t *s, intv3_t v)
 	for (i = X; i <= Z; i++) {
 		if (V(s)) {
 			v[i] = (((int8_t)acc[i * 2 + 1]) << 4) |
-				(acc[i * 2] >> 4);
+			       (acc[i * 2] >> 4);
 			v[i] <<= 16 - resolution;
 		} else {
 			if (resolution == 8)
@@ -512,14 +515,13 @@ static int read(const struct motion_sensor_t *s, intv3_t v)
 	rotate(v, *s->rot_standard_ref, v);
 
 	/* apply offset in the device coordinates */
-	range = get_range(s);
 	for (i = X; i <= Z; i++)
-		v[i] += (data->offset[i] << 5) / range;
+		v[i] += (data->offset[i] << 5) / s->current_range;
 
 	return EC_SUCCESS;
 }
 
-static int init(const struct motion_sensor_t *s)
+static int init(struct motion_sensor_t *s)
 {
 	int ret, val, reg, reset_field;
 	uint8_t timeout;
@@ -532,8 +534,8 @@ static int init(const struct motion_sensor_t *s)
 		do {
 			msleep(1);
 			/* Read WHO_AM_I to be sure the device has booted */
-			ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-					reg, &val);
+			ret = raw_read8(s->port, s->i2c_spi_addr_flags, reg,
+					&val);
 			if (ret == EC_SUCCESS)
 				break;
 
@@ -546,21 +548,18 @@ static int init(const struct motion_sensor_t *s)
 	} else {
 		/* Write 0x00 to the internal register for KX022 */
 		reg = KX022_INTERNAL;
-		ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-				 reg, 0x0);
+		ret = raw_write8(s->port, s->i2c_spi_addr_flags, reg, 0x0);
 		if (ret != EC_SUCCESS) {
 			/*
 			 * For I2C communication, if ACK was not received
 			 * from the first address, resend the command using
 			 * the second address.
 			 */
-			if (!SLAVE_IS_SPI(s->i2c_spi_addr_flags)) {
+			if (!ACCEL_ADDR_IS_SPI(s->i2c_spi_addr_flags)) {
 				const uint16_t i2c_alt_addr_flags =
-					I2C_GET_ADDR(
-						s->i2c_spi_addr_flags)
-					& ~2;
-				ret = raw_write8(s->port,
-						 i2c_alt_addr_flags,
+					I2C_STRIP_FLAGS(s->i2c_spi_addr_flags) &
+					~2;
+				ret = raw_write8(s->port, i2c_alt_addr_flags,
 						 reg, 0x0);
 			}
 		}
@@ -602,8 +601,8 @@ static int init(const struct motion_sensor_t *s)
 		do {
 			msleep(1);
 
-			ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-					reg, &val);
+			ret = raw_read8(s->port, s->i2c_spi_addr_flags, reg,
+					&val);
 			/* Reset complete. */
 			if ((ret == EC_SUCCESS) && !(val & reset_field))
 				break;
@@ -650,17 +649,31 @@ static int init(const struct motion_sensor_t *s)
 	return ret;
 }
 
+static int probe(const struct motion_sensor_t *s)
+{
+	int val;
+
+	if (i2c_read8(s->port, s->i2c_spi_addr_flags, KIONIX_WHO_AM_I(V(s)),
+		      &val) != EC_SUCCESS)
+		return EC_ERROR_HW_INTERNAL;
+
+	if (val != KIONIX_WHO_AM_I_VAL(V(s)))
+		return EC_ERROR_HW_INTERNAL;
+
+	return EC_SUCCESS;
+}
+
 const struct accelgyro_drv kionix_accel_drv = {
 	.init = init,
 	.read = read,
 	.set_range = set_range,
-	.get_range = get_range,
 	.set_resolution = set_resolution,
 	.get_resolution = get_resolution,
 	.set_data_rate = set_data_rate,
 	.get_data_rate = get_data_rate,
 	.set_offset = set_offset,
 	.get_offset = get_offset,
+	.probe = probe,
 };
 
 #ifdef CONFIG_CMD_I2C_STRESS_TEST_ACCEL
diff --git a/driver/accel_kionix.h b/driver/accel_kionix.h
index 2491c5d39d..4f5d02ee55 100644
--- a/driver/accel_kionix.h
+++ b/driver/accel_kionix.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,8 +8,8 @@
 #ifndef __CROS_EC_ACCEL_KIONIX_H
 #define __CROS_EC_ACCEL_KIONIX_H
 
-#include "common.h"
 #include "accelgyro.h"
+#include "common.h"
 #include "driver/accel_kx022.h"
 #include "driver/accel_kxcj9.h"
 
@@ -47,49 +47,29 @@ extern const struct accelgyro_drv kionix_accel_drv;
  * |    SPI device ID              | 1 |
  * +-------------------------------+---+
  */
-#define KIONIX_CTRL1_REG(v) (KX022_CNTL1 +	\
-			     (v) * (KXCJ9_CTRL1 - KX022_CNTL1))
-#define KIONIX_CTRL2_REG(v) (KX022_CNTL2 +	\
-			     (v) * (KXCJ9_CTRL2 - KX022_CNTL2))
-#define KIONIX_ODR_REG(v) (KX022_ODCNTL +	\
-			   (v) * (KXCJ9_DATA_CTRL - KX022_ODCNTL))
-#define KIONIX_ODR_FIELD(v) (KX022_OSA_FIELD +		\
-			     (v) * (KXCJ9_OSA_FIELD - KX022_OSA_FIELD))
-#define KIONIX_PC1_FIELD(v) (KX022_CNTL1_PC1 +		\
-			     (v) * (KXCJ9_CTRL1_PC1 - KX022_CNTL1_PC1))
-#define KIONIX_RANGE_FIELD(v) (KX022_GSEL_FIELD +	\
-			       (v) * (KXCJ9_GSEL_ALL - KX022_GSEL_FIELD))
-#define KIONIX_RES_FIELD(v) (KX022_RES_16BIT +		\
-			     (v) * (KXCJ9_RES_12BIT - KX022_RES_16BIT))
-#define KIONIX_RESET_FIELD(v) (KX022_CNTL2_SRST +	\
-			       (v) * (KXCJ9_CTRL2_SRST - KX022_CNTL2_SRST))
-#define KIONIX_XOUT_L(v) (KX022_XOUT_L +	\
-			  (v) * (KXCJ9_XOUT_L - KX022_XOUT_L))
+#define KIONIX_CTRL1_REG(v) (KX022_CNTL1 + (v) * (KXCJ9_CTRL1 - KX022_CNTL1))
+#define KIONIX_CTRL2_REG(v) (KX022_CNTL2 + (v) * (KXCJ9_CTRL2 - KX022_CNTL2))
+#define KIONIX_ODR_REG(v) \
+	(KX022_ODCNTL + (v) * (KXCJ9_DATA_CTRL - KX022_ODCNTL))
+#define KIONIX_ODR_FIELD(v) \
+	(KX022_OSA_FIELD + (v) * (KXCJ9_OSA_FIELD - KX022_OSA_FIELD))
+#define KIONIX_PC1_FIELD(v) \
+	(KX022_CNTL1_PC1 + (v) * (KXCJ9_CTRL1_PC1 - KX022_CNTL1_PC1))
+#define KIONIX_RANGE_FIELD(v) \
+	(KX022_GSEL_FIELD + (v) * (KXCJ9_GSEL_ALL - KX022_GSEL_FIELD))
+#define KIONIX_RES_FIELD(v) \
+	(KX022_RES_16BIT + (v) * (KXCJ9_RES_12BIT - KX022_RES_16BIT))
+#define KIONIX_RESET_FIELD(v) \
+	(KX022_CNTL2_SRST + (v) * (KXCJ9_CTRL2_SRST - KX022_CNTL2_SRST))
+#define KIONIX_XOUT_L(v) (KX022_XOUT_L + (v) * (KXCJ9_XOUT_L - KX022_XOUT_L))
 
-#define KIONIX_WHO_AM_I(v) (KX022_WHOAMI + \
-			    (v) * (KXCJ9_WHOAMI - KX022_WHOAMI))
+#define KIONIX_WHO_AM_I(v) (KX022_WHOAMI + (v) * (KXCJ9_WHOAMI - KX022_WHOAMI))
 
-#define KIONIX_WHO_AM_I_VAL(v) (KX022_WHO_AM_I_VAL + \
-			(v) * (KXCJ9_WHO_AM_I_VAL - KX022_WHO_AM_I_VAL))
+#define KIONIX_WHO_AM_I_VAL(v) \
+	(KX022_WHO_AM_I_VAL + (v) * (KXCJ9_WHO_AM_I_VAL - KX022_WHO_AM_I_VAL))
 
 #ifdef CONFIG_CMD_I2C_STRESS_TEST_ACCEL
 extern struct i2c_stress_test_dev kionix_i2c_stress_test_dev;
 #endif
 
-#ifdef CONFIG_KX022_ORIENTATION_SENSOR
-#define ORIENTATION_CHANGED(_sensor) \
-	(((struct kionix_accel_data *)(_sensor->drv_data))->orientation != \
-	((struct kionix_accel_data *)(_sensor->drv_data))->last_orientation)
-
-#define GET_ORIENTATION(_sensor) \
-	(((struct kionix_accel_data *)(_sensor->drv_data))->orientation)
-
-#define SET_ORIENTATION(_sensor, _val) \
-	(((struct kionix_accel_data *)(_sensor->drv_data))->orientation = _val)
-
-#define SET_ORIENTATION_UPDATED(_sensor) \
-	(((struct kionix_accel_data *)(_sensor->drv_data))->last_orientation = \
-	((struct kionix_accel_data *)(_sensor->drv_data))->orientation)
-#endif
-
 #endif /* __CROS_EC_ACCEL_KIONIX_H */
diff --git a/driver/accel_kx022.h b/driver/accel_kx022.h
index a806568c59..089270aca4 100644
--- a/driver/accel_kx022.h
+++ b/driver/accel_kx022.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,130 +12,128 @@
  * 7-bit address is 001111Xb. Where 'X' is determined
  * by the voltage on the ADDR pin.
  */
-#define KX022_ADDR0_FLAGS	0x1e
-#define KX022_ADDR1_FLAGS	0x1f
-#define KX022_WHO_AM_I_VAL	0x14
+#define KX022_ADDR0_FLAGS 0x1e
+#define KX022_ADDR1_FLAGS 0x1f
+#define KX022_WHO_AM_I_VAL 0x14
 
 /* Chip-specific registers */
-#define KX022_XHP_L		0x00
-#define KX022_XHP_H		0x01
-#define KX022_YHP_L		0x02
-#define KX022_YHP_H		0x03
-#define KX022_ZHP_L		0x04
-#define KX022_ZHP_H		0x05
-#define KX022_XOUT_L		0x06
-#define KX022_XOUT_H		0x07
-#define KX022_YOUT_L		0x08
-#define KX022_YOUT_H		0x09
-#define KX022_ZOUT_L		0x0a
-#define KX022_ZOUT_H		0x0b
-#define KX022_COTR		0x0c
-#define KX022_COTR_VAL_COTC	0xAA
-#define KX022_COTR_VAL_DEFAULT	0x55
-#define KX022_WHOAMI		0x0f
-#define KX022_TSCP		0x10
-#define KX022_TSPP		0x11
-#define KX022_INS1		0x12
-#define KX022_INS2		0x13
-#define KX022_INS3		0x14
-#define KX022_STATUS_REG	0x15
-#define KX022_INT_REL		0x17
-#define KX022_CNTL1		0x18
-#define KX022_CNTL2		0x19
-#define KX022_CNTL3		0x1a
-#define KX022_ODCNTL		0x1b
-#define KX022_INC1		0x1c
-#define KX022_INC2		0x1d
-#define KX022_INC3		0x1e
-#define KX022_INC4		0x1f
-#define KX022_INC5		0x20
-#define KX022_INC6		0x21
-#define KX022_TILT_TIMER	0x22
-#define KX022_WUFC		0x23
-#define KX022_TDTRC		0x24
-#define KX022_TDTC		0x25
-#define KX022_TTH		0x26
-#define KX022_TTL		0x27
-#define KX022_FTD		0x28
-#define KX022_STD		0x29
-#define KX022_TLT		0x2a
-#define KX022_TWS		0x2b
-#define KX022_ATH		0x30
-#define KX022_TILT_ANGLE_LL	0x32
-#define KX022_TILT_ANGLE_HL	0x33
-#define KX022_HYST_SET		0x34
-#define KX022_LP_CNTL		0x35
-#define KX022_BUF_CNTL1	0x3a
-#define KX022_BUF_CNTL2	0x3b
-#define KX022_BUF_STATUS_1	0x3c
-#define KX022_BUF_STATUS_2	0x3d
-#define KX022_BUF_CLEAR	0x3e
-#define KX022_BUF_READ		0x3f
-#define KX022_SELF_TEST	0x60
-#define KX022_INTERNAL		0x7f
-
-
-#define KX022_CNTL1_PC1		BIT(7)
-#define KX022_CNTL1_WUFE	BIT(1)
-#define KX022_CNTL1_TPE		BIT(0)
+#define KX022_XHP_L 0x00
+#define KX022_XHP_H 0x01
+#define KX022_YHP_L 0x02
+#define KX022_YHP_H 0x03
+#define KX022_ZHP_L 0x04
+#define KX022_ZHP_H 0x05
+#define KX022_XOUT_L 0x06
+#define KX022_XOUT_H 0x07
+#define KX022_YOUT_L 0x08
+#define KX022_YOUT_H 0x09
+#define KX022_ZOUT_L 0x0a
+#define KX022_ZOUT_H 0x0b
+#define KX022_COTR 0x0c
+#define KX022_COTR_VAL_COTC 0xAA
+#define KX022_COTR_VAL_DEFAULT 0x55
+#define KX022_WHOAMI 0x0f
+#define KX022_TSCP 0x10
+#define KX022_TSPP 0x11
+#define KX022_INS1 0x12
+#define KX022_INS2 0x13
+#define KX022_INS3 0x14
+#define KX022_STATUS_REG 0x15
+#define KX022_INT_REL 0x17
+#define KX022_CNTL1 0x18
+#define KX022_CNTL2 0x19
+#define KX022_CNTL3 0x1a
+#define KX022_ODCNTL 0x1b
+#define KX022_INC1 0x1c
+#define KX022_INC2 0x1d
+#define KX022_INC3 0x1e
+#define KX022_INC4 0x1f
+#define KX022_INC5 0x20
+#define KX022_INC6 0x21
+#define KX022_TILT_TIMER 0x22
+#define KX022_WUFC 0x23
+#define KX022_TDTRC 0x24
+#define KX022_TDTC 0x25
+#define KX022_TTH 0x26
+#define KX022_TTL 0x27
+#define KX022_FTD 0x28
+#define KX022_STD 0x29
+#define KX022_TLT 0x2a
+#define KX022_TWS 0x2b
+#define KX022_ATH 0x30
+#define KX022_TILT_ANGLE_LL 0x32
+#define KX022_TILT_ANGLE_HL 0x33
+#define KX022_HYST_SET 0x34
+#define KX022_LP_CNTL 0x35
+#define KX022_BUF_CNTL1 0x3a
+#define KX022_BUF_CNTL2 0x3b
+#define KX022_BUF_STATUS_1 0x3c
+#define KX022_BUF_STATUS_2 0x3d
+#define KX022_BUF_CLEAR 0x3e
+#define KX022_BUF_READ 0x3f
+#define KX022_SELF_TEST 0x60
+#define KX022_INTERNAL 0x7f
+
+#define KX022_CNTL1_PC1 BIT(7)
+#define KX022_CNTL1_WUFE BIT(1)
+#define KX022_CNTL1_TPE BIT(0)
 
 /* TSCP orientations */
-#define KX022_ORIENT_PORTRAIT		BIT(2)
-#define KX022_ORIENT_INVERT_PORTRAIT	BIT(3)
-#define KX022_ORIENT_LANDSCAPE		BIT(4)
-#define KX022_ORIENT_INVERT_LANDSCAPE	BIT(5)
-#define KX022_ORIENT_MASK		(KX022_ORIENT_PORTRAIT | \
-					 KX022_ORIENT_INVERT_PORTRAIT | \
-					 KX022_ORIENT_LANDSCAPE | \
-					 KX022_ORIENT_INVERT_LANDSCAPE)
-
-#define KX022_CNTL2_SRST	BIT(7)
-
-#define KX022_CNTL3_OWUF_FIELD	7
-
-#define KX022_INC1_IEA		BIT(4)
-#define KX022_INC1_IEN		BIT(5)
-
-#define KX022_GSEL_2G		(0 << 3)
-#define KX022_GSEL_4G		BIT(3)
-#define KX022_GSEL_8G		(2 << 3)
-#define KX022_GSEL_FIELD	(3 << 3)
-
-#define KX022_RES_8BIT		(0 << 6)
-#define KX022_RES_16BIT		BIT(6)
-
-#define KX022_OSA_0_781HZ	8
-#define KX022_OSA_1_563HZ	9
-#define KX022_OSA_3_125HZ	0xa
-#define KX022_OSA_6_250HZ	0xb
-#define KX022_OSA_12_50HZ	0
-#define KX022_OSA_25_00HZ	1
-#define KX022_OSA_50_00HZ	2
-#define KX022_OSA_100_0HZ	3
-#define KX022_OSA_200_0HZ	4
-#define KX022_OSA_400_0HZ	5
-#define KX022_OSA_800_0HZ	6
-#define KX022_OSA_1600HZ	7
-#define KX022_OSA_FIELD		0xf
-
-#define KX022_OWUF_0_781HZ	0
-#define KX022_OWUF_1_563HZ	1
-#define KX022_OWUF_3_125HZ	2
-#define KX022_OWUF_6_250HZ	3
-#define KX022_OWUF_12_50HZ	4
-#define KX022_OWUF_25_00HZ	5
-#define KX022_OWUF_50_00HZ	6
-#define KX022_OWUF_100_0HZ	7
-
-#define KX022_INC2_ZPWUE	BIT(0)
-#define KX022_INC2_ZNWUE	BIT(1)
-#define KX022_INC2_YPWUE	BIT(2)
-#define KX022_INC2_YNWUE	BIT(3)
-#define KX022_INC2_XPWUE	BIT(4)
-#define KX022_INC2_XNWUE	BIT(5)
+#define KX022_ORIENT_PORTRAIT BIT(2)
+#define KX022_ORIENT_INVERT_PORTRAIT BIT(3)
+#define KX022_ORIENT_LANDSCAPE BIT(4)
+#define KX022_ORIENT_INVERT_LANDSCAPE BIT(5)
+#define KX022_ORIENT_MASK                                       \
+	(KX022_ORIENT_PORTRAIT | KX022_ORIENT_INVERT_PORTRAIT | \
+	 KX022_ORIENT_LANDSCAPE | KX022_ORIENT_INVERT_LANDSCAPE)
+
+#define KX022_CNTL2_SRST BIT(7)
+
+#define KX022_CNTL3_OWUF_FIELD 7
+
+#define KX022_INC1_IEA BIT(4)
+#define KX022_INC1_IEN BIT(5)
+
+#define KX022_GSEL_2G (0 << 3)
+#define KX022_GSEL_4G BIT(3)
+#define KX022_GSEL_8G (2 << 3)
+#define KX022_GSEL_FIELD (3 << 3)
+
+#define KX022_RES_8BIT (0 << 6)
+#define KX022_RES_16BIT BIT(6)
+
+#define KX022_OSA_0_781HZ 8
+#define KX022_OSA_1_563HZ 9
+#define KX022_OSA_3_125HZ 0xa
+#define KX022_OSA_6_250HZ 0xb
+#define KX022_OSA_12_50HZ 0
+#define KX022_OSA_25_00HZ 1
+#define KX022_OSA_50_00HZ 2
+#define KX022_OSA_100_0HZ 3
+#define KX022_OSA_200_0HZ 4
+#define KX022_OSA_400_0HZ 5
+#define KX022_OSA_800_0HZ 6
+#define KX022_OSA_1600HZ 7
+#define KX022_OSA_FIELD 0xf
+
+#define KX022_OWUF_0_781HZ 0
+#define KX022_OWUF_1_563HZ 1
+#define KX022_OWUF_3_125HZ 2
+#define KX022_OWUF_6_250HZ 3
+#define KX022_OWUF_12_50HZ 4
+#define KX022_OWUF_25_00HZ 5
+#define KX022_OWUF_50_00HZ 6
+#define KX022_OWUF_100_0HZ 7
+
+#define KX022_INC2_ZPWUE BIT(0)
+#define KX022_INC2_ZNWUE BIT(1)
+#define KX022_INC2_YPWUE BIT(2)
+#define KX022_INC2_YNWUE BIT(3)
+#define KX022_INC2_XPWUE BIT(4)
+#define KX022_INC2_XNWUE BIT(5)
 
 /* Min and Max sampling frequency in mHz */
-#define KX022_ACCEL_MIN_FREQ    12500
-#define KX022_ACCEL_MAX_FREQ    MOTION_MAX_SENSOR_FREQUENCY(1600000, 6250)
+#define KX022_ACCEL_MIN_FREQ 12500
+#define KX022_ACCEL_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(1600000, 6250)
 
 #endif /* __CROS_EC_ACCEL_KX022_H */
diff --git a/driver/accel_kxcj9.h b/driver/accel_kxcj9.h
index f7488317f0..e8d3c71929 100644
--- a/driver/accel_kxcj9.h
+++ b/driver/accel_kxcj9.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,98 +14,98 @@
  * 7-bit address is 000111Xb. Where 'X' is determined
  * by the voltage on the ADDR pin.
  */
-#define KXCJ9_ADDR0_FLAGS	0x0E
-#define KXCJ9_ADDR1_FLAGS	0x0D
-#define KXCJ9_WHO_AM_I_VAL	0x0A
+#define KXCJ9_ADDR0_FLAGS 0x0E
+#define KXCJ9_ADDR1_FLAGS 0x0D
+#define KXCJ9_WHO_AM_I_VAL 0x0A
 
 /* Chip-specific registers */
-#define KXCJ9_XOUT_L		0x06
-#define KXCJ9_XOUT_H		0x07
-#define KXCJ9_YOUT_L		0x08
-#define KXCJ9_YOUT_H		0x09
-#define KXCJ9_ZOUT_L		0x0a
-#define KXCJ9_ZOUT_H		0x0b
-#define KXCJ9_DCST_RESP		0x0c
-#define KXCJ9_WHOAMI		0x0f
-#define KXCJ9_INT_SRC1		0x16
-#define KXCJ9_INT_SRC2		0x17
-#define KXCJ9_STATUS		0x18
-#define KXCJ9_INT_REL		0x1a
-#define KXCJ9_CTRL1		0x1b
-#define KXCJ9_CTRL2		0x1d
-#define KXCJ9_INT_CTRL1		0x1e
-#define KXCJ9_INT_CTRL2		0x1f
-#define KXCJ9_DATA_CTRL		0x21
-#define KXCJ9_WAKEUP_TIMER	0x29
-#define KXCJ9_SELF_TEST		0x3a
-#define KXCJ9_WAKEUP_THRESHOLD	0x6a
-
-#define KXCJ9_INT_SRC1_WUFS	BIT(1)
-#define KXCJ9_INT_SRC1_DRDY	BIT(4)
-
-#define KXCJ9_INT_SRC2_ZPWU	BIT(0)
-#define KXCJ9_INT_SRC2_ZNWU	BIT(1)
-#define KXCJ9_INT_SRC2_YPWU	BIT(2)
-#define KXCJ9_INT_SRC2_YNWU	BIT(3)
-#define KXCJ9_INT_SRC2_XPWU	BIT(4)
-#define KXCJ9_INT_SRC2_XNWU	BIT(5)
-
-#define KXCJ9_STATUS_INT	BIT(4)
-
-#define KXCJ9_CTRL1_WUFE	BIT(1)
-#define KXCJ9_CTRL1_DRDYE	BIT(5)
-#define KXCJ9_CTRL1_PC1		BIT(7)
-
-#define KXCJ9_GSEL_2G		(0 << 3)
-#define KXCJ9_GSEL_4G		BIT(3)
-#define KXCJ9_GSEL_8G		(2 << 3)
-#define KXCJ9_GSEL_8G_14BIT	(3 << 3)
-#define KXCJ9_GSEL_ALL          (3 << 3)
-
-#define KXCJ9_RES_8BIT		(0 << 6)
-#define KXCJ9_RES_12BIT		BIT(6)
-
-#define KXCJ9_CTRL2_OWUF	(7 << 0)
-#define KXCJ9_CTRL2_DCST	BIT(4)
-#define KXCJ9_CTRL2_SRST	BIT(7)
-
-#define KXCJ9_OWUF_0_781HZ	0
-#define KXCJ9_OWUF_1_563HZ	1
-#define KXCJ9_OWUF_3_125HZ	2
-#define KXCJ9_OWUF_6_250HZ	3
-#define KXCJ9_OWUF_12_50HZ	4
-#define KXCJ9_OWUF_25_00HZ	5
-#define KXCJ9_OWUF_50_00HZ	6
-#define KXCJ9_OWUF_100_0HZ	7
-
-#define KXCJ9_INT_CTRL1_IEL		BIT(3)
-#define KXCJ9_INT_CTRL1_IEA		BIT(4)
-#define KXCJ9_INT_CTRL1_IEN		BIT(5)
-
-#define KXCJ9_INT_CTRL2_ZPWUE		BIT(0)
-#define KXCJ9_INT_CTRL2_ZNWUE		BIT(1)
-#define KXCJ9_INT_CTRL2_YPWUE		BIT(2)
-#define KXCJ9_INT_CTRL2_YNWUE		BIT(3)
-#define KXCJ9_INT_CTRL2_XPWUE		BIT(4)
-#define KXCJ9_INT_CTRL2_XNWUE		BIT(5)
-
-#define KXCJ9_OSA_0_000HZ	0
-#define KXCJ9_OSA_0_781HZ	8
-#define KXCJ9_OSA_1_563HZ	9
-#define KXCJ9_OSA_3_125HZ	0xa
-#define KXCJ9_OSA_6_250HZ	0xb
-#define KXCJ9_OSA_12_50HZ	0
-#define KXCJ9_OSA_25_00HZ	1
-#define KXCJ9_OSA_50_00HZ	2
-#define KXCJ9_OSA_100_0HZ	3
-#define KXCJ9_OSA_200_0HZ	4
-#define KXCJ9_OSA_400_0HZ	5
-#define KXCJ9_OSA_800_0HZ	6
-#define KXCJ9_OSA_1600_HZ	7
-#define KXCJ9_OSA_FIELD		0xf
+#define KXCJ9_XOUT_L 0x06
+#define KXCJ9_XOUT_H 0x07
+#define KXCJ9_YOUT_L 0x08
+#define KXCJ9_YOUT_H 0x09
+#define KXCJ9_ZOUT_L 0x0a
+#define KXCJ9_ZOUT_H 0x0b
+#define KXCJ9_DCST_RESP 0x0c
+#define KXCJ9_WHOAMI 0x0f
+#define KXCJ9_INT_SRC1 0x16
+#define KXCJ9_INT_SRC2 0x17
+#define KXCJ9_STATUS 0x18
+#define KXCJ9_INT_REL 0x1a
+#define KXCJ9_CTRL1 0x1b
+#define KXCJ9_CTRL2 0x1d
+#define KXCJ9_INT_CTRL1 0x1e
+#define KXCJ9_INT_CTRL2 0x1f
+#define KXCJ9_DATA_CTRL 0x21
+#define KXCJ9_WAKEUP_TIMER 0x29
+#define KXCJ9_SELF_TEST 0x3a
+#define KXCJ9_WAKEUP_THRESHOLD 0x6a
+
+#define KXCJ9_INT_SRC1_WUFS BIT(1)
+#define KXCJ9_INT_SRC1_DRDY BIT(4)
+
+#define KXCJ9_INT_SRC2_ZPWU BIT(0)
+#define KXCJ9_INT_SRC2_ZNWU BIT(1)
+#define KXCJ9_INT_SRC2_YPWU BIT(2)
+#define KXCJ9_INT_SRC2_YNWU BIT(3)
+#define KXCJ9_INT_SRC2_XPWU BIT(4)
+#define KXCJ9_INT_SRC2_XNWU BIT(5)
+
+#define KXCJ9_STATUS_INT BIT(4)
+
+#define KXCJ9_CTRL1_WUFE BIT(1)
+#define KXCJ9_CTRL1_DRDYE BIT(5)
+#define KXCJ9_CTRL1_PC1 BIT(7)
+
+#define KXCJ9_GSEL_2G (0 << 3)
+#define KXCJ9_GSEL_4G BIT(3)
+#define KXCJ9_GSEL_8G (2 << 3)
+#define KXCJ9_GSEL_8G_14BIT (3 << 3)
+#define KXCJ9_GSEL_ALL (3 << 3)
+
+#define KXCJ9_RES_8BIT (0 << 6)
+#define KXCJ9_RES_12BIT BIT(6)
+
+#define KXCJ9_CTRL2_OWUF (7 << 0)
+#define KXCJ9_CTRL2_DCST BIT(4)
+#define KXCJ9_CTRL2_SRST BIT(7)
+
+#define KXCJ9_OWUF_0_781HZ 0
+#define KXCJ9_OWUF_1_563HZ 1
+#define KXCJ9_OWUF_3_125HZ 2
+#define KXCJ9_OWUF_6_250HZ 3
+#define KXCJ9_OWUF_12_50HZ 4
+#define KXCJ9_OWUF_25_00HZ 5
+#define KXCJ9_OWUF_50_00HZ 6
+#define KXCJ9_OWUF_100_0HZ 7
+
+#define KXCJ9_INT_CTRL1_IEL BIT(3)
+#define KXCJ9_INT_CTRL1_IEA BIT(4)
+#define KXCJ9_INT_CTRL1_IEN BIT(5)
+
+#define KXCJ9_INT_CTRL2_ZPWUE BIT(0)
+#define KXCJ9_INT_CTRL2_ZNWUE BIT(1)
+#define KXCJ9_INT_CTRL2_YPWUE BIT(2)
+#define KXCJ9_INT_CTRL2_YNWUE BIT(3)
+#define KXCJ9_INT_CTRL2_XPWUE BIT(4)
+#define KXCJ9_INT_CTRL2_XNWUE BIT(5)
+
+#define KXCJ9_OSA_0_000HZ 0
+#define KXCJ9_OSA_0_781HZ 8
+#define KXCJ9_OSA_1_563HZ 9
+#define KXCJ9_OSA_3_125HZ 0xa
+#define KXCJ9_OSA_6_250HZ 0xb
+#define KXCJ9_OSA_12_50HZ 0
+#define KXCJ9_OSA_25_00HZ 1
+#define KXCJ9_OSA_50_00HZ 2
+#define KXCJ9_OSA_100_0HZ 3
+#define KXCJ9_OSA_200_0HZ 4
+#define KXCJ9_OSA_400_0HZ 5
+#define KXCJ9_OSA_800_0HZ 6
+#define KXCJ9_OSA_1600_HZ 7
+#define KXCJ9_OSA_FIELD 0xf
 
 /* Min and Max sampling frequency in mHz */
-#define KXCJ9_ACCEL_MIN_FREQ    12500
-#define KXCJ9_ACCEL_MAX_FREQ    MOTION_MAX_SENSOR_FREQUENCY(1600000, 6250)
+#define KXCJ9_ACCEL_MIN_FREQ 12500
+#define KXCJ9_ACCEL_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(1600000, 6250)
 
 #endif /* __CROS_EC_ACCEL_KXCJ9_H */
diff --git a/driver/accel_lis2dh.c b/driver/accel_lis2dh.c
index d7307d46e3..26954f3c4b 100644
--- a/driver/accel_lis2dh.c
+++ b/driver/accel_lis2dh.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,18 +11,18 @@
 #include "accelgyro.h"
 #include "common.h"
 #include "console.h"
+#include "driver/accel_lis2dh.h"
+#include "driver/stm_mems_common.h"
 #include "hooks.h"
 #include "hwtimer.h"
 #include "i2c.h"
 #include "math_util.h"
 #include "task.h"
 #include "util.h"
-#include "driver/accel_lis2dh.h"
-#include "driver/stm_mems_common.h"
 
 #define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
 
 /**
  * set_range - set full scale range
@@ -30,10 +30,9 @@
  * @range: Range
  * @rnd: Round up/down flag
  */
-static int set_range(const struct motion_sensor_t *s, int range, int rnd)
+static int set_range(struct motion_sensor_t *s, int range, int rnd)
 {
 	int err, normalized_range;
-	struct stprivate_data *data = s->drv_data;
 	int val;
 
 	val = LIS2DH_FS_TO_REG(range);
@@ -63,19 +62,12 @@ static int set_range(const struct motion_sensor_t *s, int range, int rnd)
 
 	/* Save Gain in range for speed up data path */
 	if (err == EC_SUCCESS)
-		data->base.range = normalized_range;
+		s->current_range = normalized_range;
 
 	mutex_unlock(s->mutex);
 	return EC_SUCCESS;
 }
 
-static int get_range(const struct motion_sensor_t *s)
-{
-	struct stprivate_data *data = s->drv_data;
-
-	return data->base.range;
-}
-
 static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
 {
 	int ret, normalized_rate;
@@ -86,9 +78,9 @@ static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
 
 	if (rate == 0) {
 		/* Power Off device */
-		ret = st_write_data_with_mask(
-				s, LIS2DH_CTRL1_ADDR,
-				LIS2DH_ACC_ODR_MASK, LIS2DH_ODR_0HZ_VAL);
+		ret = st_write_data_with_mask(s, LIS2DH_CTRL1_ADDR,
+					      LIS2DH_ACC_ODR_MASK,
+					      LIS2DH_ODR_0HZ_VAL);
 		goto unlock_rate;
 	}
 
@@ -109,7 +101,7 @@ static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
 	 * to write accel parameters until we are done
 	 */
 	ret = st_write_data_with_mask(s, LIS2DH_CTRL1_ADDR, LIS2DH_ACC_ODR_MASK,
-			reg_val);
+				      reg_val);
 	if (ret == EC_SUCCESS)
 		data->base.odr = normalized_rate;
 
@@ -122,8 +114,8 @@ static int is_data_ready(const struct motion_sensor_t *s, int *ready)
 {
 	int ret, tmp;
 
-	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags,
-			   LIS2DH_STATUS_REG, &tmp);
+	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, LIS2DH_STATUS_REG,
+			   &tmp);
 	if (ret != EC_SUCCESS) {
 		CPRINTS("%s type:0x%X RS Error", s->name, s->type);
 		return ret;
@@ -155,8 +147,8 @@ static int read(const struct motion_sensor_t *s, intv3_t v)
 	}
 
 	/* Read output data bytes starting at LIS2DH_OUT_X_L_ADDR */
-	ret = st_raw_read_n(s->port, s->i2c_spi_addr_flags,
-			    LIS2DH_OUT_X_L_ADDR, raw, OUT_XYZ_SIZE);
+	ret = st_raw_read_n(s->port, s->i2c_spi_addr_flags, LIS2DH_OUT_X_L_ADDR,
+			    raw, OUT_XYZ_SIZE);
 	if (ret != EC_SUCCESS) {
 		CPRINTS("%s type:0x%X RD XYZ Error", s->name, s->type);
 		return ret;
@@ -168,7 +160,7 @@ static int read(const struct motion_sensor_t *s, intv3_t v)
 	return EC_SUCCESS;
 }
 
-static int init(const struct motion_sensor_t *s)
+static int init(struct motion_sensor_t *s)
 {
 	int ret = 0, tmp;
 	struct stprivate_data *data = s->drv_data;
@@ -203,34 +195,34 @@ static int init(const struct motion_sensor_t *s)
 	 * register must be restored to it's default.
 	 */
 	/* Enable all accel axes data and clear old settings */
-	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-			    LIS2DH_CTRL1_ADDR, LIS2DH_ENABLE_ALL_AXES);
+	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags, LIS2DH_CTRL1_ADDR,
+			    LIS2DH_ENABLE_ALL_AXES);
 	if (ret != EC_SUCCESS)
 		goto err_unlock;
 
-	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-			    LIS2DH_CTRL2_ADDR, LIS2DH_CTRL2_RESET_VAL);
+	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags, LIS2DH_CTRL2_ADDR,
+			    LIS2DH_CTRL2_RESET_VAL);
 	if (ret != EC_SUCCESS)
 		goto err_unlock;
 
-	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-			    LIS2DH_CTRL3_ADDR, LIS2DH_CTRL3_RESET_VAL);
+	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags, LIS2DH_CTRL3_ADDR,
+			    LIS2DH_CTRL3_RESET_VAL);
 	if (ret != EC_SUCCESS)
 		goto err_unlock;
 
 	/* Enable BDU */
-	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-			    LIS2DH_CTRL4_ADDR, LIS2DH_BDU_MASK);
+	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags, LIS2DH_CTRL4_ADDR,
+			    LIS2DH_BDU_MASK);
 	if (ret != EC_SUCCESS)
 		goto err_unlock;
 
-	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-			    LIS2DH_CTRL5_ADDR, LIS2DH_CTRL5_RESET_VAL);
+	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags, LIS2DH_CTRL5_ADDR,
+			    LIS2DH_CTRL5_RESET_VAL);
 	if (ret != EC_SUCCESS)
 		goto err_unlock;
 
-	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-			    LIS2DH_CTRL6_ADDR, LIS2DH_CTRL6_RESET_VAL);
+	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags, LIS2DH_CTRL6_ADDR,
+			    LIS2DH_CTRL6_RESET_VAL);
 	if (ret != EC_SUCCESS)
 		goto err_unlock;
 
@@ -252,7 +244,6 @@ const struct accelgyro_drv lis2dh_drv = {
 	.init = init,
 	.read = read,
 	.set_range = set_range,
-	.get_range = get_range,
 	.get_resolution = st_get_resolution,
 	.set_data_rate = set_data_rate,
 	.get_data_rate = st_get_data_rate,
diff --git a/driver/accel_lis2dh.h b/driver/accel_lis2dh.h
index 2a3108aab8..a645c3403c 100644
--- a/driver/accel_lis2dh.h
+++ b/driver/accel_lis2dh.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,8 +16,8 @@
  * 7-bit address is 0011 00X b. Where 'X' is determined
  * by the voltage on the ADDR pin
  */
-#define LIS2DH_ADDR0_FLAGS	0x18
-#define LIS2DH_ADDR1_FLAGS	0x19
+#define LIS2DH_ADDR0_FLAGS 0x18
+#define LIS2DH_ADDR1_FLAGS 0x19
 
 /*
  * LNG2DM:
@@ -25,54 +25,54 @@
  * 8-bit address is 0101 00XW b. Where 'X' is determined
  * by the voltage on the ADDR pin, and 'W' is read write bit
  */
-#define LNG2DM_ADDR0_FLAGS	0x28
-#define LNG2DM_ADDR1_FLAGS	0x29
+#define LNG2DM_ADDR0_FLAGS 0x28
+#define LNG2DM_ADDR1_FLAGS 0x29
 
 /* Who Am I  */
-#define LIS2DH_WHO_AM_I_REG	0x0f
-#define LIS2DH_WHO_AM_I		0x33
+#define LIS2DH_WHO_AM_I_REG 0x0f
+#define LIS2DH_WHO_AM_I 0x33
 
 /* COMMON DEFINE FOR ACCEL SENSOR */
-#define LIS2DH_EN_BIT		0x01
-#define LIS2DH_DIS_BIT		0x00
+#define LIS2DH_EN_BIT 0x01
+#define LIS2DH_DIS_BIT 0x00
 
-#define LIS2DH_INT2_ON_INT1_ADDR	0x13
-#define LIS2DH_INT2_ON_INT1_MASK	0x20
+#define LIS2DH_INT2_ON_INT1_ADDR 0x13
+#define LIS2DH_INT2_ON_INT1_MASK 0x20
 
-#define LIS2DH_OUT_X_L_ADDR	0x28
+#define LIS2DH_OUT_X_L_ADDR 0x28
 
-#define LIS2DH_CTRL1_ADDR	0x20
-#define LIS2DH_INT2_ON_INT1_MASK	0x20
-#define LIS2DH_ENABLE_ALL_AXES	0x07
+#define LIS2DH_CTRL1_ADDR 0x20
+#define LIS2DH_INT2_ON_INT1_MASK 0x20
+#define LIS2DH_ENABLE_ALL_AXES 0x07
 
-#define LIS2DH_CTRL2_ADDR	0x21
-#define LIS2DH_CTRL2_RESET_VAL	0x00
+#define LIS2DH_CTRL2_ADDR 0x21
+#define LIS2DH_CTRL2_RESET_VAL 0x00
 
-#define LIS2DH_CTRL3_ADDR	0x22
-#define LIS2DH_CTRL3_RESET_VAL	0x00
+#define LIS2DH_CTRL3_ADDR 0x22
+#define LIS2DH_CTRL3_RESET_VAL 0x00
 
-#define LIS2DH_CTRL4_ADDR	0x23
-#define LIS2DH_BDU_MASK		0x80
+#define LIS2DH_CTRL4_ADDR 0x23
+#define LIS2DH_BDU_MASK 0x80
 
-#define LIS2DH_CTRL5_ADDR	0x24
-#define LIS2DH_CTRL5_RESET_VAL	0x00
+#define LIS2DH_CTRL5_ADDR 0x24
+#define LIS2DH_CTRL5_RESET_VAL 0x00
 
-#define LIS2DH_CTRL6_ADDR	0x25
-#define LIS2DH_CTRL6_RESET_VAL	0x00
+#define LIS2DH_CTRL6_ADDR 0x25
+#define LIS2DH_CTRL6_RESET_VAL 0x00
 
-#define LIS2DH_STATUS_REG	0x27
-#define LIS2DH_STS_XLDA_UP	0x80
+#define LIS2DH_STATUS_REG 0x27
+#define LIS2DH_STS_XLDA_UP 0x80
 
-#define LIS2DH_FS_2G_VAL         0x00
-#define LIS2DH_FS_4G_VAL         0x01
-#define LIS2DH_FS_8G_VAL         0x02
-#define LIS2DH_FS_16G_VAL        0x03
+#define LIS2DH_FS_2G_VAL 0x00
+#define LIS2DH_FS_4G_VAL 0x01
+#define LIS2DH_FS_8G_VAL 0x02
+#define LIS2DH_FS_16G_VAL 0x03
 
 /* Interrupt source status register */
-#define LIS2DH_INT1_SRC_REG	0x31
+#define LIS2DH_INT1_SRC_REG 0x31
 
 /* Output data rate Mask register */
-#define LIS2DH_ACC_ODR_MASK	0xf0
+#define LIS2DH_ACC_ODR_MASK 0xf0
 
 /* Acc data rate */
 enum lis2dh_odr {
@@ -88,28 +88,29 @@ enum lis2dh_odr {
 };
 
 /* Absolute maximum rate for sensor */
-#define LIS2DH_ODR_MIN_VAL		1000
-#define LIS2DH_ODR_MAX_VAL \
-	MOTION_MAX_SENSOR_FREQUENCY(400000, 25000)
+#define LIS2DH_ODR_MIN_VAL 1000
+#define LIS2DH_ODR_MAX_VAL MOTION_MAX_SENSOR_FREQUENCY(400000, 25000)
 
 /* Return ODR reg value based on data rate set */
-#define LIS2DH_ODR_TO_REG(_odr) \
-	(_odr <= 1000) ? LIS2DH_ODR_1HZ_VAL : \
+#define LIS2DH_ODR_TO_REG(_odr)                 \
+	(_odr <= 1000)	? LIS2DH_ODR_1HZ_VAL :  \
 	(_odr <= 10000) ? LIS2DH_ODR_10HZ_VAL : \
-	((31 - __builtin_clz(_odr / 25000))) + 3
+			  ((31 - __builtin_clz(_odr / 25000))) + 3
 
 /* Return ODR real value normalized to sensor capabilities */
 #define LIS2DH_ODR_TO_NORMALIZE(_odr) \
-	(_odr <= 1000) ? 1000 : (_odr <= 10000) ? 10000 : \
-	(25000 * (1 << (31 - __builtin_clz(_odr / 25000))))
+	(_odr <= 1000)	? 1000 :      \
+	(_odr <= 10000) ? 10000 :     \
+			  (25000 * (1 << (31 - __builtin_clz(_odr / 25000))))
 
 /* Return ODR real value normalized to sensor capabilities from reg value */
-#define LIS2DH_REG_TO_NORMALIZE(_reg) \
-	(_reg == LIS2DH_ODR_1HZ_VAL) ? 1000 : \
-	(_reg == LIS2DH_ODR_10HZ_VAL) ? 10000 : (25000 * (1 << (_reg - 3)))
+#define LIS2DH_REG_TO_NORMALIZE(_reg)           \
+	(_reg == LIS2DH_ODR_1HZ_VAL)  ? 1000 :  \
+	(_reg == LIS2DH_ODR_10HZ_VAL) ? 10000 : \
+					(25000 * (1 << (_reg - 3)))
 
 /* Full scale range Mask register */
-#define LIS2DH_FS_MASK		0x30
+#define LIS2DH_FS_MASK 0x30
 
 /* FS reg value from Full Scale */
 #define LIS2DH_FS_TO_REG(_fs) (__fls(_fs) - 1)
@@ -123,9 +124,9 @@ enum lis2dh_odr {
  * lis2de/lng2dm only support 8bit resolution.
  */
 #if defined(CONFIG_ACCEL_LIS2DE) || defined(CONFIG_ACCEL_LNG2DM)
-#define LIS2DH_RESOLUTION       8
+#define LIS2DH_RESOLUTION 8
 #elif defined(CONFIG_ACCEL_LIS2DH)
-#define LIS2DH_RESOLUTION      	10
+#define LIS2DH_RESOLUTION 10
 #endif
 
 extern const struct accelgyro_drv lis2dh_drv;
diff --git a/driver/accel_lis2ds.c b/driver/accel_lis2ds.c
index a055d533b9..db27d870e5 100644
--- a/driver/accel_lis2ds.c
+++ b/driver/accel_lis2ds.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,9 +24,14 @@
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
+#ifdef CONFIG_ACCEL_LIS2DS_INT_EVENT
+#define ACCEL_LIS2DS_INT_ENABLE
+#endif
 
-STATIC_IF(CONFIG_ACCEL_FIFO) volatile uint32_t last_interrupt_timestamp;
+#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args)
+
+STATIC_IF(ACCEL_LIS2DS_INT_ENABLE)
+volatile uint32_t last_interrupt_timestamp;
 
 /**
  * lis2ds_enable_fifo - Enable/Disable FIFO in LIS2DS12
@@ -39,6 +44,34 @@ static int lis2ds_enable_fifo(const struct motion_sensor_t *s, int mode)
 				       LIS2DS_FIFO_MODE_MASK, mode);
 }
 
+static int lis2ds_config_interrupt(const struct motion_sensor_t *s)
+{
+	int ret = EC_SUCCESS;
+
+	/* Interrupt trigger level of power-on-reset is HIGH */
+	RETURN_ERROR(st_write_data_with_mask(
+		s, LIS2DS_H_ACTIVE_ADDR, LIS2DS_H_ACTIVE_MASK, LIS2DS_EN_BIT));
+
+	/*
+	 * Configure FIFO threshold to 1 sample: interrupt on watermark
+	 * will be generated every time a new data sample will be stored
+	 * in FIFO. The interrupr on watermark is cleared only when the
+	 * number or samples still present in FIFO exceeds the
+	 * configured threshold.
+	 */
+	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
+			    LIS2DS_FIFO_THS_ADDR, 1);
+	if (ret != EC_SUCCESS)
+		return ret;
+
+	/* Enable interrupt on FIFO watermark and route to int1. */
+	ret = st_write_data_with_mask(s, LIS2DS_CTRL4_ADDR, LIS2DS_INT1_FTH,
+				      LIS2DS_EN_BIT);
+
+	return ret;
+}
+
+#ifdef ACCEL_LIS2DS_INT_ENABLE
 /**
  * Load data from internal sensor FIFO
  * DIFF8 bits set means FIFO Full because 256 samples -> 0x100
@@ -47,7 +80,6 @@ static int lis2ds_load_fifo(struct motion_sensor_t *s, uint16_t nsamples,
 			    uint32_t saved_ts)
 {
 	int ret, read_len, fifo_len, chunk_len, i;
-	struct ec_response_motion_sensor_data vect;
 	int *axis = s->raw_xyz;
 	uint8_t fifo[FIFO_READ_LEN];
 
@@ -66,13 +98,23 @@ static int lis2ds_load_fifo(struct motion_sensor_t *s, uint16_t nsamples,
 			/* Apply precision, sensitivity and rotation vector */
 			st_normalize(s, axis, &fifo[i]);
 
-			/* Fill vector array */
-			vect.data[0] = axis[0];
-			vect.data[1] = axis[1];
-			vect.data[2] = axis[2];
-			vect.flags = 0;
-			vect.sensor_num = s - motion_sensors;
-			motion_sense_fifo_stage_data(&vect, s, 3, saved_ts);
+			if (IS_ENABLED(CONFIG_ACCEL_SPOOF_MODE) &&
+			    s->flags & MOTIONSENSE_FLAG_IN_SPOOF_MODE)
+				axis = s->spoof_xyz;
+			if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
+				struct ec_response_motion_sensor_data vect;
+
+				/* Fill vector array */
+				vect.data[0] = axis[0];
+				vect.data[1] = axis[1];
+				vect.data[2] = axis[2];
+				vect.flags = 0;
+				vect.sensor_num = s - motion_sensors;
+				motion_sense_fifo_stage_data(&vect, s, 3,
+							     saved_ts);
+			} else {
+				motion_sense_push_raw_xyz(s);
+			}
 		}
 
 		read_len += chunk_len;
@@ -84,104 +126,61 @@ static int lis2ds_load_fifo(struct motion_sensor_t *s, uint16_t nsamples,
 	return EC_SUCCESS;
 }
 
-__maybe_unused static int lis2ds_config_interrupt(const struct motion_sensor_t *s)
-{
-	int ret = EC_SUCCESS;
-
-	/* Interrupt trigger level of power-on-reset is HIGH */
-	if (!(s->flags & MOTIONSENSE_FLAG_INT_ACTIVE_HIGH)) {
-		ret = st_write_data_with_mask(s, LIS2DS_H_ACTIVE_ADDR,
-					      LIS2DS_H_ACTIVE_MASK, LIS2DS_EN_BIT);
-		if (ret != EC_SUCCESS)
-			return ret;
-	}
-
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
-		/*
-		 * Configure FIFO threshold to 1 sample: interrupt on watermark
-		 * will be generated every time a new data sample will be stored
-		 * in FIFO. The interrupr on watermark is cleared only when the
-		 * number or samples still present in FIFO exceeds the
-		 * configured threshold.
-		 */
-		ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-				    LIS2DS_FIFO_THS_ADDR, 1);
-		if (ret != EC_SUCCESS)
-			return ret;
-
-		/* Enable interrupt on FIFO watermark and route to int1. */
-		ret = st_write_data_with_mask(s, LIS2DS_CTRL4_ADDR,
-					      LIS2DS_INT1_FTH, LIS2DS_EN_BIT);
-		if (ret != EC_SUCCESS)
-			return ret;
-	}
-
-	return ret;
-}
-
 /**
  * lis2ds_interrupt - interrupt from int1 pin of sensor
  * Schedule Motion Sense Task to manage Interrupts
  */
 void lis2ds_interrupt(enum gpio_signal signal)
 {
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO))
-		last_interrupt_timestamp = __hw_clock_source_read();
+	last_interrupt_timestamp = __hw_clock_source_read();
 
-	task_set_event(TASK_ID_MOTIONSENSE,
-		       CONFIG_ACCEL_LIS2DS_INT_EVENT, 0);
+	task_set_event(TASK_ID_MOTIONSENSE, CONFIG_ACCEL_LIS2DS_INT_EVENT);
 }
 
 /**
  * lis2ds_irq_handler - bottom half of the interrupt stack.
  */
-__maybe_unused static int lis2ds_irq_handler(struct motion_sensor_t *s,
-					     uint32_t *event)
+static int lis2ds_irq_handler(struct motion_sensor_t *s, uint32_t *event)
 {
 	int ret = EC_SUCCESS;
+	uint16_t nsamples = 0;
+	uint8_t fifo_src_samples[2];
 
 	if ((s->type != MOTIONSENSE_TYPE_ACCEL) ||
 	    (!(*event & CONFIG_ACCEL_LIS2DS_INT_EVENT)))
 		return EC_ERROR_NOT_HANDLED;
 
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
-		uint16_t nsamples = 0;
-		uint8_t fifo_src_samples[2];
-
-		ret = st_raw_read_n_noinc(s->port,
-					  s->i2c_spi_addr_flags,
-					  LIS2DS_FIFO_SRC_ADDR,
-					  (uint8_t *)fifo_src_samples,
-					  sizeof(fifo_src_samples));
-		if (ret != EC_SUCCESS)
-			return ret;
-
-		/* Check if FIFO is full. */
-		if (fifo_src_samples[0] & LIS2DS_FIFO_OVR_MASK)
-			CPRINTS("%s FIFO Overrun", s->name);
+	ret = st_raw_read_n_noinc(s->port, s->i2c_spi_addr_flags,
+				  LIS2DS_FIFO_SRC_ADDR,
+				  (uint8_t *)fifo_src_samples,
+				  sizeof(fifo_src_samples));
+	if (ret != EC_SUCCESS)
+		return ret;
 
-		/* DIFF8 = 1 FIFO FULL, 256 unread samples. */
-		nsamples = fifo_src_samples[1] & LIS2DS_FIFO_DIFF_MASK;
-		if (fifo_src_samples[0] & LIS2DS_FIFO_DIFF8_MASK)
-			nsamples = 256;
+	/* Check if FIFO is full. */
+	if (fifo_src_samples[0] & LIS2DS_FIFO_OVR_MASK)
+		CPRINTS("%s FIFO Overrun", s->name);
 
-		ret = lis2ds_load_fifo(s, nsamples, last_interrupt_timestamp);
-	}
+	/* DIFF8 = 1 FIFO FULL, 256 unread samples. */
+	nsamples = fifo_src_samples[1] & LIS2DS_FIFO_DIFF_MASK;
+	if (fifo_src_samples[0] & LIS2DS_FIFO_DIFF8_MASK)
+		nsamples = 256;
 
-	return ret;
+	return lis2ds_load_fifo(s, nsamples, last_interrupt_timestamp);
 }
 
+#endif /* ACCEL_LIS2DS_INT_ENABLE */
+
 /**
  * set_range - set full scale range
  * @s: Motion sensor pointer
  * @range: Range
  * @rnd: Round up/down flag
  */
-static int set_range(const struct motion_sensor_t *s, int range, int rnd)
+static int set_range(struct motion_sensor_t *s, int range, int rnd)
 {
 	int err;
 	uint8_t reg_val;
-	struct stprivate_data *data = s->drv_data;
 	int newrange = ST_NORMALIZE_RATE(range);
 
 	/* Adjust and check rounded value */
@@ -190,6 +189,8 @@ static int set_range(const struct motion_sensor_t *s, int range, int rnd)
 
 	if (newrange > LIS2DS_ACCEL_FS_MAX_VAL)
 		newrange = LIS2DS_ACCEL_FS_MAX_VAL;
+	else if (newrange < LIS2DS_ACCEL_FS_MIN_VAL)
+		newrange = LIS2DS_ACCEL_FS_MIN_VAL;
 
 	reg_val = LIS2DS_FS_REG(newrange);
 
@@ -198,19 +199,12 @@ static int set_range(const struct motion_sensor_t *s, int range, int rnd)
 				      reg_val);
 	if (err == EC_SUCCESS)
 		/* Save internally gain for speed optimization. */
-		data->base.range = newrange;
+		s->current_range = newrange;
 	mutex_unlock(s->mutex);
 
 	return EC_SUCCESS;
 }
 
-static int get_range(const struct motion_sensor_t *s)
-{
-	struct stprivate_data *data = s->drv_data;
-
-	return data->base.range;
-}
-
 static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
 {
 	int ret, normalized_rate = 0;
@@ -218,13 +212,11 @@ static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
 	uint8_t reg_val = 0;
 
 	mutex_lock(s->mutex);
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
+	if (IS_ENABLED(ACCEL_LIS2DS_INT_ENABLE)) {
 		/* FIFO stop collecting events. Restart FIFO in Bypass mode */
 		ret = lis2ds_enable_fifo(s, LIS2DS_FIFO_BYPASS_MODE);
-		if (ret != EC_SUCCESS) {
-			CPRINTS("Failed to disable FIFO. Error: %d", ret);
+		if (ret != EC_SUCCESS)
 			goto unlock_rate;
-		}
 	}
 
 	/* Avoid LIS2DS_ODR_TO_REG to manage 0 mHz rate */
@@ -249,12 +241,9 @@ static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
 	if (ret == EC_SUCCESS) {
 		data->base.odr = normalized_rate;
 
-		if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
+		if (IS_ENABLED(ACCEL_LIS2DS_INT_ENABLE)) {
 			/* FIFO restart collecting events in Cont. mode. */
 			ret = lis2ds_enable_fifo(s, LIS2DS_FIFO_CONT_MODE);
-			if (ret != EC_SUCCESS)
-				CPRINTS("Failed to enable FIFO. Error: %d",
-					ret);
 		}
 	}
 
@@ -268,8 +257,8 @@ static int is_data_ready(const struct motion_sensor_t *s, int *ready)
 {
 	int ret, tmp;
 
-	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags,
-			   LIS2DS_STATUS_REG, &tmp);
+	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, LIS2DS_STATUS_REG,
+			   &tmp);
 	if (ret != EC_SUCCESS) {
 		CPRINTS("%s: type:0x%X RD XYZ Error %d", s->name, s->type, ret);
 		return ret;
@@ -315,13 +304,13 @@ static int read(const struct motion_sensor_t *s, intv3_t v)
 	return EC_SUCCESS;
 }
 
-static int init(const struct motion_sensor_t *s)
+static int init(struct motion_sensor_t *s)
 {
 	int ret = 0, tmp;
 	struct stprivate_data *data = s->drv_data;
 
-	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags,
-			   LIS2DS_WHO_AM_I_REG, &tmp);
+	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, LIS2DS_WHO_AM_I_REG,
+			   &tmp);
 	if (ret != EC_SUCCESS)
 		return EC_ERROR_UNKNOWN;
 
@@ -358,11 +347,10 @@ static int init(const struct motion_sensor_t *s)
 	if (ret != EC_SUCCESS)
 		goto err_unlock;
 
-#ifdef CONFIG_ACCEL_INTERRUPTS
-	ret = lis2ds_config_interrupt(s);
+	if (IS_ENABLED(ACCEL_LIS2DS_INT_ENABLE))
+		ret = lis2ds_config_interrupt(s);
 	if (ret != EC_SUCCESS)
 		goto err_unlock;
-#endif /* CONFIG_ACCEL_INTERRUPTS */
 
 	mutex_unlock(s->mutex);
 
@@ -382,14 +370,12 @@ const struct accelgyro_drv lis2ds_drv = {
 	.init = init,
 	.read = read,
 	.set_range = set_range,
-	.get_range = get_range,
 	.get_resolution = st_get_resolution,
 	.set_data_rate = set_data_rate,
 	.get_data_rate = st_get_data_rate,
 	.set_offset = st_set_offset,
 	.get_offset = st_get_offset,
-	.perform_calib = NULL,
-#ifdef CONFIG_ACCEL_INTERRUPTS
+#ifdef ACCEL_LIS2DS_INT_ENABLE
 	.irq_handler = lis2ds_irq_handler,
 #endif /* CONFIG_ACCEL_INTERRUPTS */
 };
diff --git a/driver/accel_lis2ds.h b/driver/accel_lis2ds.h
index b8e7f544f4..3f821b3514 100644
--- a/driver/accel_lis2ds.h
+++ b/driver/accel_lis2ds.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,95 +14,93 @@
  * 7-bit address is 110101Xb. Where 'X' is determined
  * by the voltage on the ADDR pin.
  */
-#define LIS2DS_ADDR0_FLAGS		0x1a
-#define LIS2DS_ADDR1_FLAGS		0x1e
+#define LIS2DS_ADDR0_FLAGS 0x1a
+#define LIS2DS_ADDR1_FLAGS 0x1e
 
 /* who am I  */
-#define LIS2DS_WHO_AM_I_REG		0x0f
-#define LIS2DS_WHO_AM_I			0x43
+#define LIS2DS_WHO_AM_I_REG 0x0f
+#define LIS2DS_WHO_AM_I 0x43
 
 /* X, Y, Z axis data len */
-#define LIS2DS_OUT_XYZ_SIZE		6
+#define LIS2DS_OUT_XYZ_SIZE 6
 
 /* COMMON DEFINE FOR ACCEL SENSOR */
-#define LIS2DS_EN_BIT			0x01
-#define LIS2DS_DIS_BIT			0x00
-
-#define LIS2DS_CTRL1_ADDR		0x20
-#define LIS2DS_CTRL2_ADDR		0x21
-#define LIS2DS_CTRL3_ADDR		0x22
-#define LIS2DS_TAP_X_EN			0x20
-#define LIS2DS_TAP_Y_EN			0x10
-#define LIS2DS_TAP_Z_EN			0x08
-#define LIS2DS_TAP_EN_MASK		(LIS2DS_TAP_X_EN | \
-					 LIS2DS_TAP_Y_EN | \
-					 LIS2DS_TAP_Z_EN)
-#define LIS2DS_TAP_EN_ALL		0x07
-
-#define LIS2DS_CTRL4_ADDR		0x23
-#define LIS2DS_INT1_FTH			0x02
-#define LIS2DS_INT1_D_TAP		0x08
-#define LIS2DS_INT1_S_TAP		0x40
-
-#define LIS2DS_CTRL5_ADDR		0x24
-#define LIS2DS_FIFO_CTRL_ADDR		0x25
-#define LIS2DS_FIFO_MODE_MASK		0xe0
-#define LIS2DS_FIFO_BYPASS_MODE		0
-#define LIS2DS_FIFO_MODE		1
-#define LIS2DS_FIFO_CONT_MODE		6
-
-#define LIS2DS_STATUS_REG		0x27
-#define LIS2DS_STS_XLDA_UP		0x01
-#define LIS2DS_SINGLE_TAP_UP		0x08
-#define LIS2DS_DOUBLE_TAP_UP		0x10
-#define LIS2DS_FIFO_THS_UP		0x80
-
-#define LIS2DS_OUT_X_L_ADDR		0x28
-#define LIS2DS_FIFO_THS_ADDR		0x2e
-
-#define LIS2DS_FIFO_SRC_ADDR		0x2f
-#define LIS2DS_FIFO_DIFF_MASK		0xff
-#define LIS2DS_FIFO_DIFF8_MASK		0x20
-#define LIS2DS_FIFO_OVR_MASK		0x40
-#define LIS2DS_FIFO_FTH_MASK		0x80
+#define LIS2DS_EN_BIT 0x01
+#define LIS2DS_DIS_BIT 0x00
+
+#define LIS2DS_CTRL1_ADDR 0x20
+#define LIS2DS_CTRL2_ADDR 0x21
+#define LIS2DS_CTRL3_ADDR 0x22
+#define LIS2DS_TAP_X_EN 0x20
+#define LIS2DS_TAP_Y_EN 0x10
+#define LIS2DS_TAP_Z_EN 0x08
+#define LIS2DS_TAP_EN_MASK (LIS2DS_TAP_X_EN | LIS2DS_TAP_Y_EN | LIS2DS_TAP_Z_EN)
+#define LIS2DS_TAP_EN_ALL 0x07
+
+#define LIS2DS_CTRL4_ADDR 0x23
+#define LIS2DS_INT1_FTH 0x02
+#define LIS2DS_INT1_D_TAP 0x08
+#define LIS2DS_INT1_S_TAP 0x40
+
+#define LIS2DS_CTRL5_ADDR 0x24
+#define LIS2DS_FIFO_CTRL_ADDR 0x25
+#define LIS2DS_FIFO_MODE_MASK 0xe0
+#define LIS2DS_FIFO_BYPASS_MODE 0
+#define LIS2DS_FIFO_MODE 1
+#define LIS2DS_FIFO_CONT_MODE 6
+
+#define LIS2DS_STATUS_REG 0x27
+#define LIS2DS_STS_XLDA_UP 0x01
+#define LIS2DS_SINGLE_TAP_UP 0x08
+#define LIS2DS_DOUBLE_TAP_UP 0x10
+#define LIS2DS_FIFO_THS_UP 0x80
+
+#define LIS2DS_OUT_X_L_ADDR 0x28
+#define LIS2DS_FIFO_THS_ADDR 0x2e
+
+#define LIS2DS_FIFO_SRC_ADDR 0x2f
+#define LIS2DS_FIFO_DIFF_MASK 0xff
+#define LIS2DS_FIFO_DIFF8_MASK 0x20
+#define LIS2DS_FIFO_OVR_MASK 0x40
+#define LIS2DS_FIFO_FTH_MASK 0x80
 
 /*
  * Concatenated with DIFF8 bit in FIFO_SRC (2Fh) register, it represents the
  * number of unread samples stored in FIFO. (000000000 = FIFO empty;
  * 100000000 = FIFO full, 256 unread samples).
  */
-#define LIS2DS_FIFO_SAMPLES_ADDR	0x30
-#define LIS2DS_TAP_6D_THS_ADDR		0x31
-#define LIS2DS_INT_DUR_ADDR		0x32
-#define LIS2DS_WAKE_UP_THS_ADDR		0x33
+#define LIS2DS_FIFO_SAMPLES_ADDR 0x30
+#define LIS2DS_TAP_6D_THS_ADDR 0x31
+#define LIS2DS_INT_DUR_ADDR 0x32
+#define LIS2DS_WAKE_UP_THS_ADDR 0x33
 
-#define LIS2DS_TAP_SRC_ADDR		0x38
-#define LIS2DS_TAP_EVENT_DETECT		0x40
+#define LIS2DS_TAP_SRC_ADDR 0x38
+#define LIS2DS_TAP_EVENT_DETECT 0x40
 
 /* Alias Register/Mask */
-#define LIS2DS_ACC_ODR_ADDR		LIS2DS_CTRL1_ADDR
-#define LIS2DS_ACC_ODR_MASK		0xf0
+#define LIS2DS_ACC_ODR_ADDR LIS2DS_CTRL1_ADDR
+#define LIS2DS_ACC_ODR_MASK 0xf0
 
-#define LIS2DS_BDU_ADDR			LIS2DS_CTRL1_ADDR
-#define LIS2DS_BDU_MASK			0x01
+#define LIS2DS_BDU_ADDR LIS2DS_CTRL1_ADDR
+#define LIS2DS_BDU_MASK 0x01
 
-#define LIS2DS_SOFT_RESET_ADDR		LIS2DS_CTRL2_ADDR
-#define LIS2DS_SOFT_RESET_MASK		0x40
+#define LIS2DS_SOFT_RESET_ADDR LIS2DS_CTRL2_ADDR
+#define LIS2DS_SOFT_RESET_MASK 0x40
 
-#define LIS2DS_LIR_ADDR			LIS2DS_CTRL3_ADDR
-#define LIS2DS_LIR_MASK			0x04
+#define LIS2DS_LIR_ADDR LIS2DS_CTRL3_ADDR
+#define LIS2DS_LIR_MASK 0x04
 
-#define LIS2DS_H_ACTIVE_ADDR		LIS2DS_CTRL3_ADDR
-#define LIS2DS_H_ACTIVE_MASK		0x02
+#define LIS2DS_H_ACTIVE_ADDR LIS2DS_CTRL3_ADDR
+#define LIS2DS_H_ACTIVE_MASK 0x02
 
-#define LIS2DS_INT1_FTH_ADDR		LIS2DS_CTRL4_ADDR
-#define LIS2DS_INT1_FTH_MASK		0x02
+#define LIS2DS_INT1_FTH_ADDR LIS2DS_CTRL4_ADDR
+#define LIS2DS_INT1_FTH_MASK 0x02
 
-#define LIS2DS_INT2_ON_INT1_ADDR	LIS2DS_CTRL5_ADDR
-#define LIS2DS_INT2_ON_INT1_MASK	0x20
+#define LIS2DS_INT2_ON_INT1_ADDR LIS2DS_CTRL5_ADDR
+#define LIS2DS_INT2_ON_INT1_MASK 0x20
 
-#define LIS2DS_DRDY_PULSED_ADDR		LIS2DS_CTRL5_ADDR
-#define LIS2DS_DRDY_PULSED_MASK		0x80
+#define LIS2DS_DRDY_PULSED_ADDR LIS2DS_CTRL5_ADDR
+#define LIS2DS_DRDY_PULSED_MASK 0x80
 
 /* Acc data rate for HR mode */
 enum lis2ds_odr {
@@ -118,7 +116,7 @@ enum lis2ds_odr {
 };
 
 /* Absolute Acc rate */
-#define LIS2DS_ODR_MIN_VAL		12500
+#define LIS2DS_ODR_MIN_VAL 12500
 #define LIS2DS_ODR_MAX_VAL \
 	MOTION_MAX_SENSOR_FREQUENCY(800000, LIS2DS_ODR_MIN_VAL)
 
@@ -130,8 +128,8 @@ enum lis2ds_odr {
 	(LIS2DS_ODR_MIN_VAL << (_reg - LIS2DS_ODR_12HZ_VAL))
 
 /* Full scale range registers */
-#define LIS2DS_FS_ADDR			LIS2DS_CTRL1_ADDR
-#define LIS2DS_FS_MASK			0x0c
+#define LIS2DS_FS_ADDR LIS2DS_CTRL1_ADDR
+#define LIS2DS_FS_MASK 0x0c
 
 /* Acc FS value */
 enum lis2ds_fs {
@@ -142,19 +140,20 @@ enum lis2ds_fs {
 	LIS2DS_FS_LIST_NUM
 };
 
-#define LIS2DS_ACCEL_FS_MAX_VAL		16
+#define LIS2DS_ACCEL_FS_MAX_VAL 16
+#define LIS2DS_ACCEL_FS_MIN_VAL 2
 
 /* Reg value from Full Scale */
-#define LIS2DS_FS_REG(_fs) \
-	(_fs == 2 ? LIS2DS_FS_2G_VAL : \
-	_fs == 16 ? LIS2DS_FS_16G_VAL : \
-	__fls(_fs))
+#define LIS2DS_FS_REG(_fs)               \
+	(_fs == 2  ? LIS2DS_FS_2G_VAL :  \
+	 _fs == 16 ? LIS2DS_FS_16G_VAL : \
+		     __fls(_fs))
 
 /*
  * Sensor resolution in number of bits. Sensor has two resolution:
  * 10 and 14 bit for LP and HR mode resp.
  */
-#define LIS2DS_RESOLUTION		16
+#define LIS2DS_RESOLUTION 16
 
 extern const struct accelgyro_drv lis2ds_drv;
 
diff --git a/driver/accel_lis2dw12.c b/driver/accel_lis2dw12.c
index 1f791a8364..bdd3f2120d 100644
--- a/driver/accel_lis2dw12.c
+++ b/driver/accel_lis2dw12.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,10 +7,10 @@
  * LIS2DW12 accelerometer module for Chrome EC 3D digital accelerometer.
  * For more details on LIS2DW12 device please refers to www.st.com.
  */
+#include "accel_lis2dw12.h"
 #include "accelgyro.h"
 #include "common.h"
 #include "console.h"
-#include "driver/accel_lis2dw12.h"
 #include "hooks.h"
 #include "hwtimer.h"
 #include "math_util.h"
@@ -18,38 +18,84 @@
 #include "task.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
+#ifdef CONFIG_ACCEL_LIS2DW12_INT_EVENT
+#define ACCEL_LIS2DW12_INT_ENABLE
+#endif
 
-/* Only when configured as base accel sensor, fifo and interrupt
- * are supported.
- */
-#ifdef CONFIG_ACCEL_LIS2DW_AS_BASE
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args)
 
-#ifdef CONFIG_ACCEL_FIFO
-static volatile uint32_t last_interrupt_timestamp;
+STATIC_IF(ACCEL_LIS2DW12_INT_ENABLE)
+volatile uint32_t last_interrupt_timestamp;
 
 /**
  * lis2dw12_enable_fifo - Enable/Disable FIFO in LIS2DW12
  * @s: Motion sensor pointer
  * @mode: fifo_modes
  */
-static int lis2dw12_enable_fifo(const struct motion_sensor_t *s,
-				enum lis2dw12_fmode mode)
+static __maybe_unused int lis2dw12_enable_fifo(const struct motion_sensor_t *s,
+					       enum lis2dw12_fmode mode)
 {
 	return st_write_data_with_mask(s, LIS2DW12_FIFO_CTRL_ADDR,
 				       LIS2DW12_FIFO_MODE_MASK, mode);
 }
 
+/**
+ * lis2dw12_config_interrupt- Configure interrupt for supported features.
+ * @s: Motion sensor pointer
+ *
+ * Must works with interface mutex locked
+ */
+static __maybe_unused int
+lis2dw12_config_interrupt(const struct motion_sensor_t *s)
+{
+	/* Configure FIFO watermark level. */
+	RETURN_ERROR(st_write_data_with_mask(s, LIS2DW12_FIFO_CTRL_ADDR,
+					     LIS2DW12_FIFO_THRESHOLD_MASK, 1));
+
+	/* Enable interrupt on FIFO watermark and route to int1. */
+	RETURN_ERROR(st_write_data_with_mask(s, LIS2DW12_INT1_FTH_ADDR,
+					     LIS2DW12_INT1_FTH_MASK,
+					     LIS2DW12_EN_BIT));
+
+	if (IS_ENABLED(CONFIG_GESTURE_SENSOR_DOUBLE_TAP)) {
+		/*
+		 * Configure D-TAP event detection on 3 axis.
+		 * For more details please refer to AN5038.
+		 */
+		RETURN_ERROR(st_raw_write8(s->port, s->i2c_spi_addr_flags,
+					   LIS2DW12_TAP_THS_X_ADDR, 0x09));
+		RETURN_ERROR(st_raw_write8(s->port, s->i2c_spi_addr_flags,
+					   LIS2DW12_TAP_THS_Y_ADDR, 0x09));
+		RETURN_ERROR(st_raw_write8(s->port, s->i2c_spi_addr_flags,
+					   LIS2DW12_TAP_THS_Z_ADDR, 0xE9));
+		RETURN_ERROR(st_raw_write8(s->port, s->i2c_spi_addr_flags,
+					   LIS2DW12_INT_DUR_ADDR, 0x7F));
+
+		/* Enable D-TAP event detection. */
+		RETURN_ERROR(st_write_data_with_mask(
+			s, LIS2DW12_WAKE_UP_THS_ADDR,
+			LIS2DW12_SINGLE_DOUBLE_TAP, LIS2DW12_EN_BIT));
+
+		/*
+		 * Enable D-TAP detection on int_1 pad. In any case D-TAP event
+		 * can be detected only if ODR is over 200 Hz.
+		 */
+		RETURN_ERROR(st_write_data_with_mask(s, LIS2DW12_INT1_TAP_ADDR,
+						     LIS2DW12_INT1_DTAP_MASK,
+						     LIS2DW12_EN_BIT));
+	}
+	return EC_SUCCESS;
+}
+
+#ifdef ACCEL_LIS2DW12_INT_ENABLE
 /**
  * Load data from internal sensor FIFO.
  * @s: Motion sensor pointer
  */
-static int lis2dw12_load_fifo(struct motion_sensor_t *s, int nsamples,
-			      uint32_t *last_fifo_read_ts)
+static int lis2dw12_load_fifo(struct motion_sensor_t *s, int nsamples)
 {
 	int ret, left, length, i;
-	struct ec_response_motion_sensor_data vect;
 	uint32_t interrupt_timestamp = last_interrupt_timestamp;
 	int *axis = s->raw_xyz;
 	uint8_t fifo[FIFO_READ_LEN];
@@ -69,7 +115,6 @@ static int lis2dw12_load_fifo(struct motion_sensor_t *s, int nsamples,
 
 		ret = st_raw_read_n(s->port, s->i2c_spi_addr_flags,
 				    LIS2DW12_OUT_X_L_ADDR, fifo, length);
-		*last_fifo_read_ts = __hw_clock_source_read();
 		if (ret != EC_SUCCESS)
 			return ret;
 
@@ -77,20 +122,26 @@ static int lis2dw12_load_fifo(struct motion_sensor_t *s, int nsamples,
 			/* Apply precision, sensitivity and rotation vector. */
 			st_normalize(s, axis, &fifo[i]);
 
-			/* Fill vector array. */
-			vect.data[X] = axis[X];
-			vect.data[Y] = axis[Y];
-			vect.data[Z] = axis[Z];
-			vect.flags = 0;
-			vect.sensor_num = 0;
-			motion_sense_fifo_stage_data(&vect, s, 3,
-						     interrupt_timestamp);
+			if (IS_ENABLED(CONFIG_ACCEL_SPOOF_MODE) &&
+			    s->flags & MOTIONSENSE_FLAG_IN_SPOOF_MODE)
+				axis = s->spoof_xyz;
+			if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
+				struct ec_response_motion_sensor_data vect;
+				/* Fill vector array. */
+				vect.data[X] = axis[X];
+				vect.data[Y] = axis[Y];
+				vect.data[Z] = axis[Z];
+				vect.flags = 0;
+				vect.sensor_num = s - motion_sensors;
+				motion_sense_fifo_stage_data(
+					&vect, s, 3, interrupt_timestamp);
+			} else {
+				motion_sense_push_raw_xyz(s);
+			}
+			left -= length;
 		}
-		left -= length;
 	} while (left > 0);
 
-	motion_sense_fifo_commit_data();
-
 	return EC_SUCCESS;
 }
 
@@ -111,103 +162,15 @@ static int lis2dw12_get_fifo_samples(struct motion_sensor_t *s, int *nsamples)
 	return EC_SUCCESS;
 }
 
-static int fifo_data_avail(struct motion_sensor_t *s)
-{
-	int ret, nsamples;
-
-	if (s->flags & MOTIONSENSE_FLAG_INT_SIGNAL)
-		return gpio_get_level(s->int_signal) ==
-			!!(MOTIONSENSE_FLAG_INT_ACTIVE_HIGH & s->flags);
-
-	ret = lis2dw12_get_fifo_samples(s, &nsamples);
-	/* If we failed to read the FIFO size assume empty. */
-	if (ret != EC_SUCCESS)
-		return 0;
-	return nsamples;
-}
-#endif  /* CONFIG_ACCEL_FIFO */
-
-/**
- * lis2dw12_config_interrupt- Configure interrupt for supported features.
- * @s: Motion sensor pointer
- *
- * Must works with interface mutex locked
- */
-static int lis2dw12_config_interrupt(const struct motion_sensor_t *s)
-{
-	int ret = EC_SUCCESS;
-
-#ifdef CONFIG_ACCEL_FIFO_THRES
-	/* Configure FIFO watermark level. */
-	ret = st_write_data_with_mask(s, LIS2DW12_FIFO_CTRL_ADDR,
-				      LIS2DW12_FIFO_THRESHOLD_MASK, 1);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	/* Enable interrupt on FIFO watermask and route to int1. */
-	ret = st_write_data_with_mask(s, LIS2DW12_INT1_FTH_ADDR,
-				      LIS2DW12_INT1_FTH_MASK, LIS2DW12_EN_BIT);
-	if (ret != EC_SUCCESS)
-		return ret;
-#endif /* CONFIG_ACCEL_FIFO */
-
-#ifdef CONFIG_GESTURE_SENSOR_DOUBLE_TAP
-	/*
-	 * Configure D-TAP event detection on 3 axis.
-	 * For more details please refer to AN5038.
-	 */
-	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-			    LIS2DW12_TAP_THS_X_ADDR, 0x09);
-	if (ret != EC_SUCCESS)
-		return ret;
-	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-			    LIS2DW12_TAP_THS_Y_ADDR, 0x09);
-	if (ret != EC_SUCCESS)
-		return ret;
-	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-			    LIS2DW12_TAP_THS_Z_ADDR, 0xE9);
-	if (ret != EC_SUCCESS)
-		return ret;
-	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-			    LIS2DW12_INT_DUR_ADDR, 0x7F);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	/* Enable D-TAP event detection. */
-	ret = st_write_data_with_mask(s, LIS2DW12_WAKE_UP_THS_ADDR,
-				      LIS2DW12_SINGLE_DOUBLE_TAP,
-				      LIS2DW12_EN_BIT);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	/*
-	 * Enable D-TAP detection on int_1 pad. In any case D-TAP event
-	 * can be detected only if ODR is over 200 Hz.
-	 */
-	ret = st_write_data_with_mask(s, LIS2DW12_INT1_TAP_ADDR,
-				      LIS2DW12_INT1_DTAP_MASK,
-				      LIS2DW12_EN_BIT);
-#endif /* CONFIG_GESTURE_SENSOR_DOUBLE_TAP */
-	return ret;
-}
-
-static void lis2dw12_handle_interrupt_for_fifo(uint32_t ts)
-{
-#ifdef CONFIG_ACCEL_FIFO
-	if (time_after(ts, last_interrupt_timestamp))
-		last_interrupt_timestamp = ts;
-#endif
-	task_set_event(TASK_ID_MOTIONSENSE,
-		       CONFIG_ACCEL_LIS2DW12_INT_EVENT, 0);
-}
-
 /**
  * lis2dw12_interrupt - interrupt from int pin of sensor
  * Schedule Motion Sense Task to manage Interrupts.
  */
 void lis2dw12_interrupt(enum gpio_signal signal)
 {
-	lis2dw12_handle_interrupt_for_fifo(__hw_clock_source_read());
+	last_interrupt_timestamp = __hw_clock_source_read();
+
+	task_set_event(TASK_ID_MOTIONSENSE, CONFIG_ACCEL_LIS2DW12_INT_EVENT);
 }
 
 /**
@@ -215,62 +178,43 @@ void lis2dw12_interrupt(enum gpio_signal signal)
  */
 static int lis2dw12_irq_handler(struct motion_sensor_t *s, uint32_t *event)
 {
-	int ret = EC_SUCCESS;
+	bool commit_needed = false;
+	int nsamples;
 
 	if ((s->type != MOTIONSENSE_TYPE_ACCEL) ||
 	    (!(*event & CONFIG_ACCEL_LIS2DW12_INT_EVENT))) {
 		return EC_ERROR_NOT_HANDLED;
 	}
 
-#ifdef CONFIG_GESTURE_SENSOR_DOUBLE_TAP
-	{
+	if (IS_ENABLED(CONFIG_GESTURE_SENSOR_DOUBLE_TAP)) {
 		int status = 0;
 
 		/* Read Status register to check TAP events. */
 		st_raw_read8(s->port, s->i2c_spi_addr_flags,
 			     LIS2DW12_STATUS_TAP, &status);
 		if (status & LIS2DW12_DOUBLE_TAP)
-			*event |= CONFIG_GESTURE_TAP_EVENT;
+			*event |= TASK_EVENT_MOTION_ACTIVITY_INTERRUPT(
+				MOTIONSENSE_ACTIVITY_DOUBLE_TAP);
 	}
-#endif /* CONFIG_GESTURE_SENSOR_DOUBLE_TAP */
 
-#ifdef CONFIG_ACCEL_FIFO
-	{
-		int nsamples;
-		uint32_t last_fifo_read_ts;
-		uint32_t triggering_interrupt_timestamp =
-			last_interrupt_timestamp;
-
-		ret = lis2dw12_get_fifo_samples(s, &nsamples);
-		if (ret != EC_SUCCESS)
-			return ret;
+	do {
+		RETURN_ERROR(lis2dw12_get_fifo_samples(s, &nsamples));
 
-		last_fifo_read_ts = __hw_clock_source_read();
-		if (nsamples == 0)
-			return EC_SUCCESS;
+		if (nsamples != 0) {
+			commit_needed = true;
+			RETURN_ERROR(lis2dw12_load_fifo(s, nsamples));
+		}
+	} while (nsamples != 0);
 
-		ret = lis2dw12_load_fifo(s, nsamples, &last_fifo_read_ts);
+	if (IS_ENABLED(CONFIG_ACCEL_FIFO) && commit_needed)
+		motion_sense_fifo_commit_data();
 
-		/*
-		 * Check if FIFO isn't empty and we never got an interrupt.
-		 * This can happen if new entries were added to the FIFO after
-		 * the count was read, but before the FIFO was cleared out.
-		 * In the long term it might be better to use the last
-		 * spread timestamp instead.
-		 */
-		if (fifo_data_avail(s) &&
-		    triggering_interrupt_timestamp == last_interrupt_timestamp)
-			lis2dw12_handle_interrupt_for_fifo(last_fifo_read_ts);
-	}
-#endif /* CONFIG_ACCEL_FIFO */
-
-	return ret;
+	return EC_SUCCESS;
 }
-
-#endif /* CONFIG_ACCEL_LIS2DW_AS_BASE */
+#endif
 
 /**
- * set_power_mode - set sensor power mode
+ * lis2dw12_set_power_mode - set sensor power mode
  * @s: Motion sensor pointer
  * @mode: LIS2DW12_LOW_POWER, LIS2DW12_HIGH_PERF
  * @lpmode: LIS2DW12_LOW_POWER_MODE_2,
@@ -280,14 +224,14 @@ static int lis2dw12_irq_handler(struct motion_sensor_t *s, uint32_t *event)
  * TODO: LIS2DW12_LOW_POWER_MODE_1 not implemented because output differ
  *       in resolution
  */
-static int set_power_mode(const struct motion_sensor_t *s,
-			  enum lis2sw12_mode mode,
-			  enum lis2sw12_lpmode lpmode)
+STATIC_IF_NOT(CONFIG_ZTEST)
+int lis2dw12_set_power_mode(const struct motion_sensor_t *s,
+			    enum lis2sw12_mode mode,
+			    enum lis2sw12_lpmode lpmode)
 {
 	int ret = EC_SUCCESS;
 
-	if (mode == LIS2DW12_LOW_POWER &&
-	    lpmode == LIS2DW12_LOW_POWER_MODE_1)
+	if (mode == LIS2DW12_LOW_POWER && lpmode == LIS2DW12_LOW_POWER_MODE_1)
 		return EC_ERROR_UNIMPLEMENTED;
 
 	/* Set Mode and Low Power Mode. */
@@ -307,11 +251,10 @@ static int set_power_mode(const struct motion_sensor_t *s,
  * @range: Range
  * @rnd: Round up/down flag
  */
-static int set_range(const struct motion_sensor_t *s, int range, int rnd)
+static int set_range(struct motion_sensor_t *s, int range, int rnd)
 {
 	int err = EC_SUCCESS;
 	uint8_t reg_val;
-	struct stprivate_data *data = s->drv_data;
 	int newrange = range;
 
 	/* Adjust and check rounded value. */
@@ -324,39 +267,34 @@ static int set_range(const struct motion_sensor_t *s, int range, int rnd)
 	reg_val = LIS2DW12_FS_REG(newrange);
 
 	mutex_lock(s->mutex);
-#if defined(CONFIG_ACCEL_FIFO) && defined(CONFIG_ACCEL_LIS2DW_AS_BASE)
 	/*
 	 * FIFO stop collecting events. Restart FIFO in Bypass mode.
 	 * If Range is changed all samples in FIFO must be discharged because
 	 * with a different sensitivity.
 	 */
-	err = lis2dw12_enable_fifo(s, LIS2DW12_FIFO_BYPASS_MODE);
-	if (err != EC_SUCCESS)
-		goto unlock_rate;
-#endif /* CONFIG_ACCEL_FIFO && CONFIG_ACCEL_LIS2DW_AS_BASE */
+	if (IS_ENABLED(ACCEL_LIS2DW12_INT_ENABLE)) {
+		err = lis2dw12_enable_fifo(s, LIS2DW12_FIFO_BYPASS_MODE);
+		if (err != EC_SUCCESS)
+			goto unlock_rate;
+	}
 
 	err = st_write_data_with_mask(s, LIS2DW12_FS_ADDR, LIS2DW12_FS_MASK,
 				      reg_val);
 	if (err == EC_SUCCESS)
-		data->base.range = newrange;
-#if defined(CONFIG_ACCEL_FIFO) && defined(CONFIG_ACCEL_LIS2DW_AS_BASE)
+		s->current_range = newrange;
+	else
+		goto unlock_rate;
+
 	/* FIFO restart collecting events in Cont. mode. */
-	err = lis2dw12_enable_fifo(s, LIS2DW12_FIFO_CONT_MODE);
+	if (IS_ENABLED(ACCEL_LIS2DW12_INT_ENABLE))
+		err = lis2dw12_enable_fifo(s, LIS2DW12_FIFO_CONT_MODE);
 
 unlock_rate:
-#endif /* CONFIG_ACCEL_FIFO && CONFIG_ACCEL_LIS2DW_AS_BASE */
 	mutex_unlock(s->mutex);
 
 	return err;
 }
 
-static int get_range(const struct motion_sensor_t *s)
-{
-	struct stprivate_data *data = s->drv_data;
-
-	return data->base.range;
-}
-
 /**
  * ODR reg value from selected data rate in mHz.
  */
@@ -387,12 +325,12 @@ static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
 
 	mutex_lock(s->mutex);
 
-#if defined(CONFIG_ACCEL_FIFO) && defined(CONFIG_ACCEL_LIS2DW_AS_BASE)
 	/* FIFO stop collecting events. Restart FIFO in Bypass mode. */
-	ret = lis2dw12_enable_fifo(s, LIS2DW12_FIFO_BYPASS_MODE);
-	if (ret != EC_SUCCESS)
-		goto unlock_rate;
-#endif /* CONFIG_ACCEL_FIFO && CONFIG_ACCEL_LIS2DW_AS_BASE */
+	if (IS_ENABLED(ACCEL_LIS2DW12_INT_ENABLE)) {
+		ret = lis2dw12_enable_fifo(s, LIS2DW12_FIFO_BYPASS_MODE);
+		if (ret != EC_SUCCESS)
+			goto unlock_rate;
+	}
 
 	if (rate == 0) {
 		ret = st_write_data_with_mask(s, LIS2DW12_ACC_ODR_ADDR,
@@ -415,32 +353,29 @@ static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
 	if (reg_val > LIS2DW12_ODR_1_6kHZ_VAL) {
 		reg_val = LIS2DW12_ODR_1_6kHZ_VAL;
 		normalized_rate = LIS2DW12_ODR_MAX_VAL;
-	} else if (reg_val < LIS2DW12_ODR_12HZ_VAL) {
-		reg_val = LIS2DW12_ODR_12HZ_VAL;
-		normalized_rate = LIS2DW12_ODR_MIN_VAL;
 	}
 
 	/* lis2dwl supports 14 bit resolution only at high performance mode,
 	 * and it will always stay at high performance mode from initialization.
 	 * But lis2dw12 needs switch low power mode according to odr value.
 	 */
-#ifndef CONFIG_ACCEL_LIS2DWL
-	if (reg_val > LIS2DW12_ODR_200HZ_VAL)
-		ret = set_power_mode(s, LIS2DW12_HIGH_PERF, 0);
-	else
-		ret = set_power_mode(s, LIS2DW12_LOW_POWER,
-				     LIS2DW12_LOW_POWER_MODE_2);
-#endif
+	if (!IS_ENABLED(CONFIG_ACCEL_LIS2DWL)) {
+		if (reg_val >= LIS2DW12_ODR_50HZ_VAL)
+			ret = lis2dw12_set_power_mode(s, LIS2DW12_HIGH_PERF, 0);
+		else
+			ret = lis2dw12_set_power_mode(
+				s, LIS2DW12_LOW_POWER,
+				LIS2DW12_LOW_POWER_MODE_2);
+	}
 
 	ret = st_write_data_with_mask(s, LIS2DW12_ACC_ODR_ADDR,
 				      LIS2DW12_ACC_ODR_MASK, reg_val);
 	if (ret == EC_SUCCESS)
 		data->base.odr = normalized_rate;
 
-#if defined(CONFIG_ACCEL_FIFO) && defined(CONFIG_ACCEL_LIS2DW_AS_BASE)
 	/* FIFO restart collecting events in continuous mode. */
-	ret = lis2dw12_enable_fifo(s, LIS2DW12_FIFO_CONT_MODE);
-#endif /* CONFIG_ACCEL_FIFO && CONFIG_ACCEL_LIS2DW_AS_BASE */
+	if (IS_ENABLED(ACCEL_LIS2DW12_INT_ENABLE))
+		ret = lis2dw12_enable_fifo(s, LIS2DW12_FIFO_CONT_MODE);
 
 unlock_rate:
 	mutex_unlock(s->mutex);
@@ -448,12 +383,41 @@ static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
 	return ret;
 }
 
+#ifdef CONFIG_BODY_DETECTION
+static int get_rms_noise(const struct motion_sensor_t *s)
+{
+	fp_t rate, noise_density_ug;
+
+	/* change unit of ODR to Hz to prevent INT_TO_FP() overflow */
+	rate = INT_TO_FP(st_get_data_rate(s) / 1000);
+
+	/*
+	 * LIS2DW12: 90ug/sqrt(Hz) when ODR is over 50Hz
+	 * When lower, we are in power mode 2, so the noise density does not
+	 * depend on frequency and the RMS at +/-2g is 2.4mg.
+	 *
+	 * LIS12DWL: 110uq/sqr(Hz) for all frequencies, since low power mode
+	 * is not used.
+	 */
+
+	if (!IS_ENABLED(CONFIG_ACCEL_LIS2DWL)) {
+		if (rate < INT_TO_FP(50))
+			return 2400;
+		noise_density_ug = INT_TO_FP(90);
+	} else {
+		noise_density_ug = INT_TO_FP(110);
+	}
+
+	return FP_TO_INT(fp_mul(fp_sqrtf(rate), noise_density_ug));
+}
+#endif
+
 static int is_data_ready(const struct motion_sensor_t *s, int *ready)
 {
 	int ret, tmp;
 
-	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags,
-			   LIS2DW12_STATUS_REG, &tmp);
+	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, LIS2DW12_STATUS_REG,
+			   &tmp);
 	if (ret != EC_SUCCESS)
 		return ret;
 
@@ -484,8 +448,7 @@ static int read(const struct motion_sensor_t *s, intv3_t v)
 
 	/* Read 6 bytes starting at xyz_reg. */
 	ret = st_raw_read_n_noinc(s->port, s->i2c_spi_addr_flags,
-				  LIS2DW12_OUT_X_L_ADDR, raw,
-				  OUT_XYZ_SIZE);
+				  LIS2DW12_OUT_X_L_ADDR, raw, OUT_XYZ_SIZE);
 	if (ret != EC_SUCCESS) {
 		CPRINTS("%s type:0x%X RD XYZ Error", s->name, s->type);
 		return ret;
@@ -497,7 +460,7 @@ static int read(const struct motion_sensor_t *s, intv3_t v)
 	return EC_SUCCESS;
 }
 
-static int init(const struct motion_sensor_t *s)
+static int init(struct motion_sensor_t *s)
 {
 	int ret = 0, tmp, timeout = 0, status;
 	struct stprivate_data *data = s->drv_data;
@@ -505,7 +468,7 @@ static int init(const struct motion_sensor_t *s)
 	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags,
 			   LIS2DW12_WHO_AM_I_REG, &tmp);
 	if (ret != EC_SUCCESS)
-		return EC_ERROR_UNKNOWN;
+		return ret;
 
 	if (tmp != LIS2DW12_WHO_AM_I)
 		return EC_ERROR_ACCESS_DENIED;
@@ -524,17 +487,15 @@ static int init(const struct motion_sensor_t *s)
 	/* Wait End of Reset. */
 	do {
 		if (timeout > 10) {
-			ret = EC_RES_TIMEOUT;
+			ret = EC_ERROR_TIMEOUT;
 			goto err_unlock;
 		}
 
 		msleep(1);
 		timeout += 1;
 		ret = st_raw_read8(s->port, s->i2c_spi_addr_flags,
-				  LIS2DW12_SOFT_RESET_ADDR, &status);
-		if (ret != EC_SUCCESS)
-			continue;
-	} while ((status & LIS2DW12_SOFT_RESET_MASK) != 0);
+				   LIS2DW12_SOFT_RESET_ADDR, &status);
+	} while (ret != EC_SUCCESS || (status & LIS2DW12_SOFT_RESET_MASK) != 0);
 
 	/* Enable BDU. */
 	ret = st_write_data_with_mask(s, LIS2DW12_BDU_ADDR, LIS2DW12_BDU_MASK,
@@ -547,34 +508,38 @@ static int init(const struct motion_sensor_t *s)
 	if (ret != EC_SUCCESS)
 		goto err_unlock;
 
-#if defined(CONFIG_ACCEL_INTERRUPTS) && defined(CONFIG_ACCEL_LIS2DW_AS_BASE)
+	ret = st_write_data_with_mask(s, LIS2DW12_LOW_NOISE_ADDR,
+				      LIS2DW12_LOW_NOISE_MASK, LIS2DW12_EN_BIT);
+	if (ret != EC_SUCCESS)
+		goto err_unlock;
+
 	/* Interrupt trigger level of power-on-reset is HIGH */
-	if (!(MOTIONSENSE_FLAG_INT_ACTIVE_HIGH & s->flags)) {
+	if (IS_ENABLED(ACCEL_LIS2DW12_INT_ENABLE)) {
 		ret = st_write_data_with_mask(s, LIS2DW12_H_ACTIVE_ADDR,
-						LIS2DW12_H_ACTIVE_MASK,
-						LIS2DW12_EN_BIT);
+					      LIS2DW12_H_ACTIVE_MASK,
+					      LIS2DW12_EN_BIT);
 		if (ret != EC_SUCCESS)
 			goto err_unlock;
 	}
-#endif
 
-#ifdef CONFIG_ACCEL_LIS2DWL
-	/* lis2dwl supports 14 bit resolution only at high perfomance mode */
-	ret = set_power_mode(s, LIS2DW12_HIGH_PERF, 0);
-#else
-	/* Set default Mode and Low Power Mode. */
-	ret = set_power_mode(s, LIS2DW12_LOW_POWER, LIS2DW12_LOW_POWER_MODE_2);
-#endif
+	if (IS_ENABLED(CONFIG_ACCEL_LIS2DWL))
+		/*
+		 * lis2dwl supports 14 bit resolution only
+		 * at high performance mode
+		 */
+		ret = lis2dw12_set_power_mode(s, LIS2DW12_HIGH_PERF, 0);
+	else
+		/* Set default Mode and Low Power Mode. */
+		ret = lis2dw12_set_power_mode(s, LIS2DW12_LOW_POWER,
+					      LIS2DW12_LOW_POWER_MODE_2);
 	if (ret != EC_SUCCESS)
 		goto err_unlock;
 
-#ifdef CONFIG_ACCEL_LIS2DW_AS_BASE
-	if (IS_ENABLED(CONFIG_ACCEL_INTERRUPTS)) {
+	if (IS_ENABLED(ACCEL_LIS2DW12_INT_ENABLE)) {
 		ret = lis2dw12_config_interrupt(s);
 		if (ret != EC_SUCCESS)
 			goto err_unlock;
 	}
-#endif
 	mutex_unlock(s->mutex);
 
 	/* Set default resolution. */
@@ -583,21 +548,23 @@ static int init(const struct motion_sensor_t *s)
 
 err_unlock:
 	mutex_unlock(s->mutex);
-	CPRINTS("%s: MS Init type:0x%X Error", s->name, s->type);
-	return EC_ERROR_UNKNOWN;
+	CPRINTS("%s: MS Init type:0x%X Error(%d)", s->name, s->type, ret);
+	return ret;
 }
 
 const struct accelgyro_drv lis2dw12_drv = {
 	.init = init,
 	.read = read,
 	.set_range = set_range,
-	.get_range = get_range,
 	.get_resolution = st_get_resolution,
 	.set_data_rate = set_data_rate,
 	.get_data_rate = st_get_data_rate,
 	.set_offset = st_set_offset,
 	.get_offset = st_get_offset,
-#if defined(CONFIG_ACCEL_INTERRUPTS) && defined(CONFIG_ACCEL_LIS2DW_AS_BASE)
+#ifdef ACCEL_LIS2DW12_INT_ENABLE
 	.irq_handler = lis2dw12_irq_handler,
-#endif /* CONFIG_ACCEL_INTERRUPTS && CONFIG_ACCEL_LIS2DW_AS_BASE */
+#endif /* ACCEL_LIS2DW12_INT_ENABLE */
+#ifdef CONFIG_BODY_DETECTION
+	.get_rms_noise = get_rms_noise,
+#endif
 };
diff --git a/driver/accel_lis2dw12.h b/driver/accel_lis2dw12.h
index c1f70bc513..3b014d26a5 100644
--- a/driver/accel_lis2dw12.h
+++ b/driver/accel_lis2dw12.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,57 +11,50 @@
 #ifndef __CROS_EC_ACCEL_LIS2DW12_H
 #define __CROS_EC_ACCEL_LIS2DW12_H
 
-#include "driver/stm_mems_common.h"
-
-/*
- * 7-bit address is 011000Xb. Where 'X' is determined
- * by the voltage on the ADDR pin.
- */
-#define LIS2DW12_ADDR0			0x18
-#define LIS2DW12_ADDR1			0x19
-
-#define LIS2DWL_ADDR0_FLAGS		0x18
-#define LIS2DWL_ADDR1_FLAGS		0x19
-
-#define LIS2DW12_EN_BIT			0x01
-#define LIS2DW12_DIS_BIT		0x00
+#include "driver/accel_lis2dw12_public.h"
+#include "stm_mems_common.h"
 
 /* Who am I. */
-#define LIS2DW12_WHO_AM_I_REG		0x0f
-#define LIS2DW12_WHO_AM_I		0x44
+#define LIS2DW12_WHO_AM_I_REG 0x0f
+#define LIS2DW12_WHO_AM_I 0x44
 
 /* Registers sensor. */
-#define LIS2DW12_CTRL1_ADDR		0x20
-#define LIS2DW12_CTRL2_ADDR		0x21
-#define LIS2DW12_CTRL3_ADDR		0x22
+#define LIS2DW12_CTRL1_ADDR 0x20
+#define LIS2DW12_CTRL2_ADDR 0x21
+#define LIS2DW12_CTRL3_ADDR 0x22
 
-#define LIS2DW12_CTRL4_ADDR		0x23
+#define LIS2DW12_CTRL4_ADDR 0x23
 
 /* CTRL4 bits. */
-#define LIS2DW12_INT1_FTH		0x02
-#define LIS2DW12_INT1_D_TAP		0x08
-#define LIS2DW12_INT1_S_TAP		0x40
+#define LIS2DW12_INT1_FTH 0x02
+#define LIS2DW12_INT1_D_TAP 0x08
+#define LIS2DW12_INT1_S_TAP 0x40
 
-#define LIS2DW12_CTRL5_ADDR		0x24
+#define LIS2DW12_CTRL5_ADDR 0x24
 
 /* CTRL5 bits. */
-#define LIS2DW12_INT2_FTH		0x02
+#define LIS2DW12_INT2_FTH 0x02
 
-#define LIS2DW12_CTRL6_ADDR		0x25
-#define LIS2DW12_STATUS_REG		0x27
+#define LIS2DW12_CTRL6_ADDR 0x25
+#define LIS2DW12_STATUS_REG 0x27
 
 /* STATUS bits. */
-#define LIS2DW12_STS_DRDY_UP		0x01
-#define LIS2DW12_SINGLE_TAP_UP		0x08
-#define LIS2DW12_DOUBLE_TAP_UP		0x10
-#define LIS2DW12_FIFO_THS_UP		0x80
+#define LIS2DW12_STS_DRDY_UP 0x01
+#define LIS2DW12_SINGLE_TAP_UP 0x08
+#define LIS2DW12_DOUBLE_TAP_UP 0x10
+#define LIS2DW12_FIFO_THS_UP 0x80
 
-#define LIS2DW12_OUT_X_L_ADDR		0x28
+#define LIS2DW12_OUT_X_L_ADDR 0x28
+#define LIS2DW12_OUT_X_H_ADDR 0x29
+#define LIS2DW12_OUT_Y_L_ADDR 0x2a
+#define LIS2DW12_OUT_Y_H_ADDR 0x2b
+#define LIS2DW12_OUT_Z_L_ADDR 0x2c
+#define LIS2DW12_OUT_Z_H_ADDR 0x2d
 
-#define LIS2DW12_FIFO_CTRL_ADDR		0x2e
+#define LIS2DW12_FIFO_CTRL_ADDR 0x2e
 
 /* FIFO_CTRL bits. */
-#define LIS2DW12_FIFO_MODE_MASK		0xe0
+#define LIS2DW12_FIFO_MODE_MASK 0xe0
 
 /* List of supported FIFO mode. */
 enum lis2dw12_fmode {
@@ -70,37 +63,37 @@ enum lis2dw12_fmode {
 	LIS2DW12_FIFO_CONT_MODE = 6
 };
 
-#define LIS2DW12_FIFO_THRESHOLD_MASK	0x1f
+#define LIS2DW12_FIFO_THRESHOLD_MASK 0x1f
 
-#define LIS2DW12_FIFO_SAMPLES_ADDR	0x2f
-#define LIS2DW12_TAP_THS_X_ADDR		0x30
-#define LIS2DW12_TAP_THS_Y_ADDR		0x31
-#define LIS2DW12_TAP_THS_Z_ADDR		0x32
-#define LIS2DW12_INT_DUR_ADDR		0x33
+#define LIS2DW12_FIFO_SAMPLES_ADDR 0x2f
+#define LIS2DW12_TAP_THS_X_ADDR 0x30
+#define LIS2DW12_TAP_THS_Y_ADDR 0x31
+#define LIS2DW12_TAP_THS_Z_ADDR 0x32
+#define LIS2DW12_INT_DUR_ADDR 0x33
 
-#define LIS2DW12_WAKE_UP_THS_ADDR	0x34
+#define LIS2DW12_WAKE_UP_THS_ADDR 0x34
 
 /* TAP bits. */
-#define LIS2DW12_SINGLE_DOUBLE_TAP	0x80
+#define LIS2DW12_SINGLE_DOUBLE_TAP 0x80
 
 /* FIFO_SAMPLES bits. */
-#define LIS2DW12_FIFO_DIFF_MASK		0x3f
-#define LIS2DW12_FIFO_OVR_MASK		0x40
-#define LIS2DW12_FIFO_FTH_MASK		0x80
+#define LIS2DW12_FIFO_DIFF_MASK 0x3f
+#define LIS2DW12_FIFO_OVR_MASK 0x40
+#define LIS2DW12_FIFO_FTH_MASK 0x80
 
-#define LIS2DW12_ABS_INT_CFG_ADDR	0x3f
+#define LIS2DW12_ABS_INT_CFG_ADDR 0x3f
 
 /* INT Configuration bits. */
-#define LIS2DW12_DRDY_PULSED		0x80
-#define LIS2DW12_INT2_ON_INT1		0x40
-#define LIS2DW12_INT_ENABLE		0x20
+#define LIS2DW12_DRDY_PULSED 0x80
+#define LIS2DW12_INT2_ON_INT1 0x40
+#define LIS2DW12_INT_ENABLE 0x20
 
 /* Alias Registers/Masks. */
-#define LIS2DW12_ACC_ODR_ADDR		LIS2DW12_CTRL1_ADDR
-#define LIS2DW12_ACC_ODR_MASK		0xf0
+#define LIS2DW12_ACC_ODR_ADDR LIS2DW12_CTRL1_ADDR
+#define LIS2DW12_ACC_ODR_MASK 0xf0
 
-#define LIS2DW12_ACC_MODE_ADDR		LIS2DW12_CTRL1_ADDR
-#define LIS2DW12_ACC_MODE_MASK		0x0c
+#define LIS2DW12_ACC_MODE_ADDR LIS2DW12_CTRL1_ADDR
+#define LIS2DW12_ACC_MODE_MASK 0x0c
 
 /* Power mode selection. */
 enum lis2sw12_mode {
@@ -110,8 +103,8 @@ enum lis2sw12_mode {
 	LIS2DW12_LOW_POWER_LIST_NUM
 };
 
-#define LIS2DW12_ACC_LPMODE_ADDR	LIS2DW12_CTRL1_ADDR
-#define LIS2DW12_ACC_LPMODE_MASK	0x03
+#define LIS2DW12_ACC_LPMODE_ADDR LIS2DW12_CTRL1_ADDR
+#define LIS2DW12_ACC_LPMODE_MASK 0x03
 
 /*
  * Low power mode selection.
@@ -126,39 +119,39 @@ enum lis2sw12_lpmode {
 	LIS2DW12_LOW_POWER_MODE_LIST_NUM
 };
 
-#define LIS2DW12_BDU_ADDR		LIS2DW12_CTRL2_ADDR
-#define LIS2DW12_BDU_MASK		0x08
+#define LIS2DW12_BDU_ADDR LIS2DW12_CTRL2_ADDR
+#define LIS2DW12_BDU_MASK 0x08
 
-#define LIS2DW12_SOFT_RESET_ADDR	LIS2DW12_CTRL2_ADDR
-#define LIS2DW12_SOFT_RESET_MASK	0x40
+#define LIS2DW12_SOFT_RESET_ADDR LIS2DW12_CTRL2_ADDR
+#define LIS2DW12_SOFT_RESET_MASK 0x40
 
-#define LIS2DW12_BOOT_ADDR		LIS2DW12_CTRL2_ADDR
-#define LIS2DW12_BOOT_MASK		0x80
+#define LIS2DW12_BOOT_ADDR LIS2DW12_CTRL2_ADDR
+#define LIS2DW12_BOOT_MASK 0x80
 
-#define LIS2DW12_LIR_ADDR		LIS2DW12_CTRL3_ADDR
-#define LIS2DW12_LIR_MASK		0x10
+#define LIS2DW12_LIR_ADDR LIS2DW12_CTRL3_ADDR
+#define LIS2DW12_LIR_MASK 0x10
 
-#define LIS2DW12_H_ACTIVE_ADDR		LIS2DW12_CTRL3_ADDR
-#define LIS2DW12_H_ACTIVE_MASK		0x08
+#define LIS2DW12_H_ACTIVE_ADDR LIS2DW12_CTRL3_ADDR
+#define LIS2DW12_H_ACTIVE_MASK 0x08
 
-#define LIS2DW12_INT1_FTH_ADDR		LIS2DW12_CTRL4_ADDR
-#define LIS2DW12_INT1_FTH_MASK		LIS2DW12_INT1_FTH
+#define LIS2DW12_INT1_FTH_ADDR LIS2DW12_CTRL4_ADDR
+#define LIS2DW12_INT1_FTH_MASK LIS2DW12_INT1_FTH
 
-#define LIS2DW12_INT1_TAP_ADDR		LIS2DW12_CTRL4_ADDR
-#define LIS2DW12_INT1_DTAP_MASK		0x08
-#define LIS2DW12_INT1_STAP_MASK		0x40
+#define LIS2DW12_INT1_TAP_ADDR LIS2DW12_CTRL4_ADDR
+#define LIS2DW12_INT1_DTAP_MASK 0x08
+#define LIS2DW12_INT1_STAP_MASK 0x40
 
-#define LIS2DW12_INT1_D_TAP_EN		LIS2DW12_INT1_DTAP_MASK
+#define LIS2DW12_INT1_D_TAP_EN LIS2DW12_INT1_DTAP_MASK
 
-#define LIS2DW12_STATUS_TAP		LIS2DW12_STS_DRDY_UP
-#define LIS2DW12_SINGLE_TAP		LIS2DW12_SINGLE_TAP_UP
-#define LIS2DW12_DOUBLE_TAP		LIS2DW12_DOUBLE_TAP_UP
+#define LIS2DW12_STATUS_TAP LIS2DW12_STS_DRDY_UP
+#define LIS2DW12_SINGLE_TAP LIS2DW12_SINGLE_TAP_UP
+#define LIS2DW12_DOUBLE_TAP LIS2DW12_DOUBLE_TAP_UP
 
-#define LIS2DW12_INT2_ON_INT1_ADDR	LIS2DW12_ABS_INT_CFG_ADDR
-#define LIS2DW12_INT2_ON_INT1_MASK	LIS2DW12_INT2_ON_INT1
+#define LIS2DW12_INT2_ON_INT1_ADDR LIS2DW12_ABS_INT_CFG_ADDR
+#define LIS2DW12_INT2_ON_INT1_MASK LIS2DW12_INT2_ON_INT1
 
-#define LIS2DW12_DRDY_PULSED_ADDR	LIS2DW12_ABS_INT_CFG_ADDR
-#define LIS2DW12_DRDY_PULSED_MASK	LIS2DW12_DRDY_PULSED
+#define LIS2DW12_DRDY_PULSED_ADDR LIS2DW12_ABS_INT_CFG_ADDR
+#define LIS2DW12_DRDY_PULSED_MASK LIS2DW12_DRDY_PULSED
 
 /* Acc data rate for HR mode. */
 enum lis2dw12_odr {
@@ -174,15 +167,9 @@ enum lis2dw12_odr {
 	LIS2DW12_ODR_LIST_NUM
 };
 
-/* Absolute Acc rate. */
-#define LIS2DW12_ODR_MIN_VAL		12500
-#define LIS2DW12_ODR_MAX_VAL		\
-	MOTION_MAX_SENSOR_FREQUENCY(1600000, LIS2DW12_ODR_MIN_VAL)
-
-
 /* Full scale range registers. */
-#define LIS2DW12_FS_ADDR		LIS2DW12_CTRL6_ADDR
-#define LIS2DW12_FS_MASK		0x30
+#define LIS2DW12_FS_ADDR LIS2DW12_CTRL6_ADDR
+#define LIS2DW12_FS_MASK 0x30
 
 /* Acc FS value. */
 enum lis2dw12_fs {
@@ -193,39 +180,64 @@ enum lis2dw12_fs {
 	LIS2DW12_FS_LIST_NUM
 };
 
-#define LIS2DW12_ACCEL_FS_MAX_VAL	16
+#define LIS2DW12_ACCEL_FS_MAX_VAL 16
+
+#define LIS2DW12_LOW_NOISE_ADDR LIS2DW12_CTRL6_ADDR
+#define LIS2DW12_LOW_NOISE_MASK 0x04
 
 /* Acc Gain value. */
-#define LIS2DW12_FS_2G_GAIN		3904
-#define LIS2DW12_FS_4G_GAIN		(LIS2DW12_FS_2G_GAIN << 1)
-#define LIS2DW12_FS_8G_GAIN		(LIS2DW12_FS_2G_GAIN << 2)
-#define LIS2DW12_FS_16G_GAIN		(LIS2DW12_FS_2G_GAIN << 3)
+#define LIS2DW12_FS_2G_GAIN 3904
+#define LIS2DW12_FS_4G_GAIN (LIS2DW12_FS_2G_GAIN << 1)
+#define LIS2DW12_FS_8G_GAIN (LIS2DW12_FS_2G_GAIN << 2)
+#define LIS2DW12_FS_16G_GAIN (LIS2DW12_FS_2G_GAIN << 3)
 
 /* FS Full Scale value from Gain. */
 #define LIS2DW12_GAIN_FS(_gain) \
 	(2 << (31 - __builtin_clz(_gain / LIS2DW12_FS_2G_GAIN)))
 
 /* Gain value from selected Full Scale. */
-#define LIS2DW12_FS_GAIN(_fs) \
-	(LIS2DW12_FS_2G_GAIN << (30 - __builtin_clz(_fs)))
+#define LIS2DW12_FS_GAIN(_fs) (LIS2DW12_FS_2G_GAIN << (30 - __builtin_clz(_fs)))
 
 /* Reg value from Full Scale. */
-#define LIS2DW12_FS_REG(_fs) \
-	(30 - __builtin_clz(_fs))
+#define LIS2DW12_FS_REG(_fs) (30 - __builtin_clz(_fs))
 
 /* Normalized FS value from Full Scale. */
-#define LIS2DW12_NORMALIZE_FS(_fs) \
-	(1 << (30 - __builtin_clz(_fs)))
+#define LIS2DW12_NORMALIZE_FS(_fs) (1 << (30 - __builtin_clz(_fs)))
 
 /*
  * Sensor resolution in number of bits.
  * Sensor driver support 14 bits resolution.
  * TODO: Support all "LP Power Mode" (res. 12/14 bits).
  */
-#define LIS2DW12_RESOLUTION		14
-
-extern const struct accelgyro_drv lis2dw12_drv;
-
-void lis2dw12_interrupt(enum gpio_signal signal);
+#define LIS2DW12_RESOLUTION 14
+
+/** Maximum possible sample */
+#define LIS2DW12_SAMPLE_MAX ((1 << (LIS2DW12_RESOLUTION - 1)) - 1)
+
+/** Smallest possible sample */
+#define LIS2DW12_SAMPLE_MIN (-(1 << (LIS2DW12_RESOLUTION - 1)))
+
+#ifdef CONFIG_ZTEST
+int lis2dw12_set_power_mode(const struct motion_sensor_t *s,
+			    enum lis2sw12_mode mode,
+			    enum lis2sw12_lpmode lpmode);
+#endif
+
+#if defined(CONFIG_ZEPHYR)
+#if DT_NODE_EXISTS(DT_ALIAS(lis2dw12_int))
+/* Get the motion sensor ID of the LIS2DW12 sensor that generates the
+ * interrupt. The interrupt is converted to the event and transferred to
+ * motion sense task that actually handles the interrupt.
+ *
+ * Here we use an alias (lis2dw12_int) to get the motion sensor ID. This alias
+ * MUST be defined for this driver to work.
+ * aliases {
+ *   lis2dw12-int = &lid_accel;
+ * };
+ */
+#define CONFIG_ACCEL_LIS2DW12_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(SENSOR_ID(DT_ALIAS(lis2dw12_int)))
+#endif
+#endif
 
 #endif /* __CROS_EC_ACCEL_LIS2DW12_H */
diff --git a/driver/accelgyro_bmi160.c b/driver/accelgyro_bmi160.c
index 803e705f42..7a398e5f4b 100644
--- a/driver/accelgyro_bmi160.c
+++ b/driver/accelgyro_bmi160.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,14 +9,16 @@
  */
 
 #include "accelgyro.h"
+#include "accelgyro_bmi160.h"
+#include "accelgyro_bmi_common.h"
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_bmi160.h"
-#include "driver/mag_bmm150.h"
 #include "hwtimer.h"
 #include "i2c.h"
+#include "mag_bmm150.h"
 #include "math_util.h"
+#include "motion_orientation.h"
 #include "motion_sense_fifo.h"
 #include "spi.h"
 #include "task.h"
@@ -24,31 +26,35 @@
 #include "util.h"
 
 #define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args)
 
-STATIC_IF(CONFIG_ACCEL_FIFO) volatile uint32_t last_interrupt_timestamp;
+#ifdef CONFIG_ACCELGYRO_BMI160_INT_EVENT
+#define ACCELGYRO_BMI160_INT_ENABLE
+#endif
 
-static int wakeup_time[] = {
-	[MOTIONSENSE_TYPE_ACCEL] = 4,
-	[MOTIONSENSE_TYPE_GYRO] = 80,
-	[MOTIONSENSE_TYPE_MAG] = 1
-};
+STATIC_IF(CONFIG_BMI_ORIENTATION_SENSOR)
+void irq_set_orientation(struct motion_sensor_t *s, int interrupt);
+
+STATIC_IF(ACCELGYRO_BMI160_INT_ENABLE)
+volatile uint32_t last_interrupt_timestamp;
+
+static int wakeup_time[] = { [MOTIONSENSE_TYPE_ACCEL] = 4,
+			     [MOTIONSENSE_TYPE_GYRO] = 80,
+			     [MOTIONSENSE_TYPE_MAG] = 1 };
 
-#ifdef CONFIG_BMI_SEC_I2C
 /**
  * Control access to the compass on the secondary i2c interface:
  * enable values are:
  * 1: manual access, we can issue i2c to the compass
  * 0: data access: BMI160 gather data periodically from the compass.
  */
-static int bmi160_sec_access_ctrl(const int port,
-				  const uint16_t i2c_spi_addr_flags,
-				  const int enable)
+static __maybe_unused int
+bmi160_sec_access_ctrl(const int port, const uint16_t i2c_spi_addr_flags,
+		       const int enable)
 {
 	int mag_if_ctrl;
-	bmi_read8(port, i2c_spi_addr_flags,
-		  BMI160_MAG_IF_1, &mag_if_ctrl);
+	bmi_read8(port, i2c_spi_addr_flags, BMI160_MAG_IF_1, &mag_if_ctrl);
 	if (enable) {
 		mag_if_ctrl |= BMI160_MAG_MANUAL_EN;
 		mag_if_ctrl &= ~BMI160_MAG_READ_BURST_MASK;
@@ -58,71 +64,62 @@ static int bmi160_sec_access_ctrl(const int port,
 		mag_if_ctrl &= ~BMI160_MAG_READ_BURST_MASK;
 		mag_if_ctrl |= BMI160_MAG_READ_BURST_8;
 	}
-	return bmi_write8(port, i2c_spi_addr_flags,
-			  BMI160_MAG_IF_1, mag_if_ctrl);
+	return bmi_write8(port, i2c_spi_addr_flags, BMI160_MAG_IF_1,
+			  mag_if_ctrl);
 }
 
 /**
  * Read register from compass.
  * Assuming we are in manual access mode, read compass i2c register.
  */
-int bmi160_sec_raw_read8(const int port,
-			 const uint16_t i2c_spi_addr_flags,
+int bmi160_sec_raw_read8(const int port, const uint16_t i2c_spi_addr_flags,
 			 const uint8_t reg, int *data_ptr)
 {
 	/* Only read 1 bytes */
-	bmi_write8(port, i2c_spi_addr_flags,
-		   BMI160_MAG_I2C_READ_ADDR, reg);
-	return bmi_read8(port, i2c_spi_addr_flags,
-			 BMI160_MAG_I2C_READ_DATA, data_ptr);
+	bmi_write8(port, i2c_spi_addr_flags, BMI160_MAG_I2C_READ_ADDR, reg);
+	return bmi_read8(port, i2c_spi_addr_flags, BMI160_MAG_I2C_READ_DATA,
+			 data_ptr);
 }
 
 /**
  * Write register from compass.
  * Assuming we are in manual access mode, write to compass i2c register.
  */
-int bmi160_sec_raw_write8(const int port,
-			  const uint16_t i2c_spi_addr_flags,
+int bmi160_sec_raw_write8(const int port, const uint16_t i2c_spi_addr_flags,
 			  const uint8_t reg, int data)
 {
-	bmi_write8(port, i2c_spi_addr_flags,
-		   BMI160_MAG_I2C_WRITE_DATA, data);
-	return bmi_write8(port, i2c_spi_addr_flags,
-			  BMI160_MAG_I2C_WRITE_ADDR, reg);
+	bmi_write8(port, i2c_spi_addr_flags, BMI160_MAG_I2C_WRITE_DATA, data);
+	return bmi_write8(port, i2c_spi_addr_flags, BMI160_MAG_I2C_WRITE_ADDR,
+			  reg);
 }
-#endif
 
-static int set_data_rate(const struct motion_sensor_t *s,
-				int rate,
-				int rnd)
+static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
 {
 	int ret, normalized_rate;
 	uint8_t reg_val;
 	struct accelgyro_saved_data_t *data = BMI_GET_SAVED_DATA(s);
-#ifdef CONFIG_MAG_BMI_BMM150
-	struct mag_cal_t              *moc = BMM150_CAL(s);
-#endif
 
 	if (rate == 0) {
 		/* FIFO stop collecting events */
-		if (IS_ENABLED(CONFIG_ACCEL_FIFO))
+		if (IS_ENABLED(ACCELGYRO_BMI160_INT_ENABLE))
 			bmi_enable_fifo(s, 0);
 
 		/* go to suspend mode */
-		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-				 BMI160_CMD_REG,
+		ret = bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_CMD_REG,
 				 BMI160_CMD_MODE_SUSPEND(s->type));
 		msleep(3);
 		data->odr = 0;
-#ifdef CONFIG_MAG_BMI_BMM150
-		if (s->type == MOTIONSENSE_TYPE_MAG)
+		if (IS_ENABLED(CONFIG_MAG_BMI_BMM150) &&
+		    (s->type == MOTIONSENSE_TYPE_MAG)) {
+			struct mag_cal_t *moc = BMM150_CAL(s);
+
 			moc->batch_size = 0;
-#endif
+		}
+
 		return ret;
 	} else if (data->odr == 0) {
 		/* back from suspend mode. */
-		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-				 BMI160_CMD_REG,
+		ret = bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_CMD_REG,
 				 BMI160_CMD_MODE_NORMAL(s->type));
 		msleep(wakeup_time[s->type]);
 	}
@@ -137,16 +134,17 @@ static int set_data_rate(const struct motion_sensor_t *s,
 	 */
 	mutex_lock(s->mutex);
 
-	ret = bmi_set_reg8(s, BMI_CONF_REG(s->type),
-			   reg_val, BMI_ODR_MASK);
+	ret = bmi_set_reg8(s, BMI_CONF_REG(s->type), reg_val, BMI_ODR_MASK);
 	if (ret != EC_SUCCESS)
 		goto accel_cleanup;
 
 	/* Now that we have set the odr, update the driver's value. */
 	data->odr = normalized_rate;
 
-#ifdef CONFIG_MAG_BMI_BMM150
-	if (s->type == MOTIONSENSE_TYPE_MAG) {
+	if (IS_ENABLED(CONFIG_MAG_BMI_BMM150) &&
+	    (s->type == MOTIONSENSE_TYPE_MAG)) {
+		struct mag_cal_t *moc = BMM150_CAL(s);
+
 		/* Reset the calibration */
 		init_mag_cal(moc);
 		/*
@@ -154,18 +152,17 @@ static int set_data_rate(const struct motion_sensor_t *s,
 		 * for at least MIN_BATCH_WINDOW_US.
 		 * Given odr is in mHz, multiply by 1000x
 		 */
-		moc->batch_size = MAX(
-			MAG_CAL_MIN_BATCH_SIZE,
-			(data->odr * 1000) / (MAG_CAL_MIN_BATCH_WINDOW_US));
+		moc->batch_size =
+			MAX(MAG_CAL_MIN_BATCH_SIZE,
+			    (data->odr * 1000) / (MAG_CAL_MIN_BATCH_WINDOW_US));
 		CPRINTS("Batch size: %d", moc->batch_size);
 	}
-#endif
 
 	/*
 	 * FIFO start collecting events.
 	 * They will be discarded if AP does not want them.
 	 */
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO))
+	if (IS_ENABLED(ACCELGYRO_BMI160_INT_ENABLE))
 		bmi_enable_fifo(s, 1);
 
 accel_cleanup:
@@ -173,29 +170,34 @@ static int set_data_rate(const struct motion_sensor_t *s,
 	return ret;
 }
 
-static int set_offset(const struct motion_sensor_t *s,
-			const int16_t *offset,
-			int16_t    temp)
+static int set_offset(const struct motion_sensor_t *s, const int16_t *offset,
+		      int16_t temp)
 {
 	int ret, val98;
 	intv3_t v = { offset[X], offset[Y], offset[Z] };
 
 	rotate_inv(v, *s->rot_standard_ref, v);
 
-	ret = bmi_read8(s->port, s->i2c_spi_addr_flags,
-			BMI160_OFFSET_EN_GYR98, &val98);
+	ret = bmi_read8(s->port, s->i2c_spi_addr_flags, BMI160_OFFSET_EN_GYR98,
+			&val98);
 	if (ret != 0)
 		return ret;
 
 	switch (s->type) {
 	case MOTIONSENSE_TYPE_ACCEL:
-		bmi_set_accel_offset(s, v);
+		ret = bmi_set_accel_offset(s, v);
+		if (ret != EC_SUCCESS)
+			return ret;
+
 		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
 				 BMI160_OFFSET_EN_GYR98,
 				 val98 | BMI160_OFFSET_ACC_EN);
 		break;
 	case MOTIONSENSE_TYPE_GYRO:
-		bmi_set_gyro_offset(s, v, &val98);
+		ret = bmi_set_gyro_offset(s, v, &val98);
+		if (ret != EC_SUCCESS)
+			return ret;
+
 		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
 				 BMI160_OFFSET_EN_GYR98,
 				 val98 | BMI160_OFFSET_GYRO_EN);
@@ -211,21 +213,27 @@ static int set_offset(const struct motion_sensor_t *s,
 	return ret;
 }
 
-static int perform_calib(const struct motion_sensor_t *s, int enable)
+static int perform_calib(struct motion_sensor_t *s, int enable)
 {
-	int ret, val, en_flag, status, rate, range;
+	int ret, val, en_flag, status, rate, range = s->current_range;
 	timestamp_t deadline, timeout;
 
 	if (!enable)
 		return EC_SUCCESS;
 
+	/* We only support accelerometers and gyroscopes */
+	if (s->type != MOTIONSENSE_TYPE_ACCEL &&
+	    s->type != MOTIONSENSE_TYPE_GYRO)
+		return EC_RES_INVALID_PARAM;
+
 	rate = bmi_get_data_rate(s);
-	range = bmi_get_range(s);
 	/*
 	 * Temporary set frequency to 100Hz to get enough data in a short
 	 * period of time.
 	 */
-	set_data_rate(s, 100000, 0);
+	ret = set_data_rate(s, 100000, 0);
+	if (ret != EC_SUCCESS)
+		goto end_perform_calib;
 
 	switch (s->type) {
 	case MOTIONSENSE_TYPE_ACCEL:
@@ -236,8 +244,8 @@ static int perform_calib(const struct motion_sensor_t *s, int enable)
 		else
 			val = BMI160_FOC_ACC_MINUS_1G;
 		val = (BMI160_FOC_ACC_0G << BMI160_FOC_ACC_X_OFFSET) |
-			(BMI160_FOC_ACC_0G << BMI160_FOC_ACC_Y_OFFSET) |
-			(val << BMI160_FOC_ACC_Z_OFFSET);
+		      (BMI160_FOC_ACC_0G << BMI160_FOC_ACC_Y_OFFSET) |
+		      (val << BMI160_FOC_ACC_Z_OFFSET);
 		en_flag = BMI160_OFFSET_ACC_EN;
 		/*
 		 * Temporary set range to minimum to run calibration with
@@ -258,15 +266,16 @@ static int perform_calib(const struct motion_sensor_t *s, int enable)
 		/* Timeout for gyroscope calibration */
 		timeout.val = 800 * MSEC;
 		break;
+	/* LCOV_EXCL_START */
 	default:
-		/* Not supported on Magnetometer */
-		ret = EC_RES_INVALID_PARAM;
-		goto end_perform_calib;
+		/* Unreachable due to sensor type check above. */
+		ASSERT(false);
+		return EC_RES_INVALID_PARAM;
+		/* LCOV_EXCL_STOP */
 	}
-	ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-			 BMI160_FOC_CONF, val);
-	ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-			 BMI160_CMD_REG, BMI160_CMD_START_FOC);
+	ret = bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_FOC_CONF, val);
+	ret = bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_CMD_REG,
+			 BMI160_CMD_START_FOC);
 	deadline.val = get_time().val + timeout.val;
 	do {
 		if (timestamp_expired(deadline, NULL)) {
@@ -274,8 +283,8 @@ static int perform_calib(const struct motion_sensor_t *s, int enable)
 			goto end_perform_calib;
 		}
 		msleep(50);
-		ret = bmi_read8(s->port, s->i2c_spi_addr_flags,
-				BMI160_STATUS, &status);
+		ret = bmi_read8(s->port, s->i2c_spi_addr_flags, BMI160_STATUS,
+				&status);
 		if (ret != EC_SUCCESS)
 			goto end_perform_calib;
 	} while ((status & BMI160_FOC_RDY) == 0);
@@ -293,10 +302,10 @@ static int perform_calib(const struct motion_sensor_t *s, int enable)
  * Defined even if host interface is not defined, to enable double tap even
  * when the host does not deal with gesture.
  */
-int manage_activity(const struct motion_sensor_t *s,
-		    enum motionsensor_activity activity,
-		    int enable,
-		    const struct ec_motion_sense_activity *param)
+#ifdef CONFIG_GESTURE_HOST_DETECTION
+static int manage_activity(const struct motion_sensor_t *s,
+			   enum motionsensor_activity activity, int enable,
+			   const struct ec_motion_sense_activity *param)
 {
 	int ret;
 	struct bmi_drv_data_t *data = BMI_GET_DATA(s);
@@ -307,23 +316,23 @@ int manage_activity(const struct motion_sensor_t *s,
 		if (enable) {
 			/* We should use parameters from caller */
 			bmi_write8(s->port, s->i2c_spi_addr_flags,
-				BMI160_INT_MOTION_3,
-				BMI160_MOTION_PROOF_TIME(
-					CONFIG_GESTURE_SIGMO_PROOF_MS) <<
-				BMI160_MOTION_PROOF_OFF |
-				BMI160_MOTION_SKIP_TIME(
-					CONFIG_GESTURE_SIGMO_SKIP_MS) <<
-				BMI160_MOTION_SKIP_OFF |
-				BMI160_MOTION_SIG_MOT_SEL);
+				   BMI160_INT_MOTION_3,
+				   BMI160_MOTION_PROOF_TIME(
+					   CONFIG_GESTURE_SIGMO_PROOF_MS)
+						   << BMI160_MOTION_PROOF_OFF |
+					   BMI160_MOTION_SKIP_TIME(
+						   CONFIG_GESTURE_SIGMO_SKIP_MS)
+						   << BMI160_MOTION_SKIP_OFF |
+					   BMI160_MOTION_SIG_MOT_SEL);
 			bmi_write8(s->port, s->i2c_spi_addr_flags,
-				BMI160_INT_MOTION_1,
-				BMI160_MOTION_TH(s,
-					CONFIG_GESTURE_SIGMO_THRES_MG));
+				   BMI160_INT_MOTION_1,
+				   BMI160_MOTION_TH(
+					   s, CONFIG_GESTURE_SIGMO_THRES_MG));
 		}
 		ret = bmi_enable_reg8(s, BMI160_INT_EN_0,
 				      BMI160_INT_ANYMO_X_EN |
-				      BMI160_INT_ANYMO_Y_EN |
-				      BMI160_INT_ANYMO_Z_EN,
+					      BMI160_INT_ANYMO_Y_EN |
+					      BMI160_INT_ANYMO_Z_EN,
 				      enable);
 		if (ret)
 			ret = EC_RES_UNAVAILABLE;
@@ -333,8 +342,7 @@ int manage_activity(const struct motion_sensor_t *s,
 #ifdef CONFIG_GESTURE_SENSOR_DOUBLE_TAP
 	case MOTIONSENSE_ACTIVITY_DOUBLE_TAP: {
 		/* Set double tap interrupt */
-		ret = bmi_enable_reg8(s, BMI160_INT_EN_0,
-				      BMI160_INT_D_TAP_EN,
+		ret = bmi_enable_reg8(s, BMI160_INT_EN_0, BMI160_INT_D_TAP_EN,
 				      enable);
 		if (ret)
 			ret = EC_RES_UNAVAILABLE;
@@ -355,61 +363,38 @@ int manage_activity(const struct motion_sensor_t *s,
 	}
 	return ret;
 }
-
-#ifdef CONFIG_GESTURE_HOST_DETECTION
-int list_activities(const struct motion_sensor_t *s,
-		    uint32_t *enabled,
-		    uint32_t *disabled)
-{
-	struct bmi_drv_data_t *data = BMI_GET_DATA(s);
-	*enabled = data->enabled_activities;
-	*disabled = data->disabled_activities;
-	return EC_RES_SUCCESS;
-}
 #endif
 
-#ifdef CONFIG_ACCEL_INTERRUPTS
-
-/**
- * bmi160_interrupt - called when the sensor activates the interrupt line.
- *
- * This is a "top half" interrupt handler, it just asks motion sense ask
- * to schedule the "bottom half", ->irq_handler().
- */
-void bmi160_interrupt(enum gpio_signal signal)
+#ifdef CONFIG_BODY_DETECTION
+static int get_rms_noise(const struct motion_sensor_t *s)
 {
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO))
-		last_interrupt_timestamp = __hw_clock_source_read();
-
-	task_set_event(TASK_ID_MOTIONSENSE,
-		       CONFIG_ACCELGYRO_BMI160_INT_EVENT, 0);
+	return bmi_get_rms_noise(s, BMI160_ACCEL_RMS_NOISE_100HZ);
 }
+#endif
 
-
-static int config_interrupt(const struct motion_sensor_t *s)
+/** Requires that the passed sensor `*s` is an accelerometer */
+static __maybe_unused int
+config_accel_interrupt(const struct motion_sensor_t *s)
 {
 	int ret, tmp;
 
-	if (s->type != MOTIONSENSE_TYPE_ACCEL)
-		return EC_SUCCESS;
-
 	mutex_lock(s->mutex);
-	bmi_write8(s->port, s->i2c_spi_addr_flags,
-		   BMI160_CMD_REG, BMI160_CMD_FIFO_FLUSH);
-	bmi_write8(s->port, s->i2c_spi_addr_flags,
-		   BMI160_CMD_REG, BMI160_CMD_INT_RESET);
-
-#ifdef CONFIG_GESTURE_SENSOR_DOUBLE_TAP
-	bmi_write8(s->port, s->i2c_spi_addr_flags,
-		   BMI160_INT_TAP_0,
-		   BMI160_TAP_DUR(s, CONFIG_GESTURE_TAP_MAX_INTERSTICE_T));
-	ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-			 BMI160_INT_TAP_1,
-			 BMI160_TAP_TH(s, CONFIG_GESTURE_TAP_THRES_MG));
-#endif
-#ifdef CONFIG_BMI_ORIENTATION_SENSOR
+	bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_CMD_REG,
+		   BMI160_CMD_FIFO_FLUSH);
+	bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_CMD_REG,
+		   BMI160_CMD_INT_RESET);
+
+	if (IS_ENABLED(CONFIG_GESTURE_SENSOR_DOUBLE_TAP)) {
+		bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_INT_TAP_0,
+			   BMI160_TAP_DUR(s,
+					  CONFIG_GESTURE_TAP_MAX_INTERSTICE_T));
+		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
+				 BMI160_INT_TAP_1,
+				 BMI160_TAP_TH(s, CONFIG_GESTURE_TAP_THRES_MG));
+	}
 	/* only use orientation sensor on the lid sensor */
-	if (s->location == MOTIONSENSE_LOC_LID) {
+	if (IS_ENABLED(CONFIG_BMI_ORIENTATION_SENSOR) &&
+	    (s->location == MOTIONSENSE_LOC_LID)) {
 		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
 				 BMI160_INT_ORIENT_0,
 				 BMI160_INT_ORIENT_0_INIT_VAL);
@@ -417,45 +402,40 @@ static int config_interrupt(const struct motion_sensor_t *s)
 				 BMI160_INT_ORIENT_1,
 				 BMI160_INT_ORIENT_1_INIT_VAL);
 	}
-#endif
 
-#ifdef CONFIG_ACCELGYRO_BMI160_INT2_OUTPUT
-	ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-			 BMI160_INT_LATCH, BMI160_LATCH_5MS);
-#else
-	/* Also, configure int2 as an external input. */
-	ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-			 BMI160_INT_LATCH,
-			 BMI160_INT2_INPUT_EN | BMI160_LATCH_5MS);
-#endif
+	if (IS_ENABLED(CONFIG_ACCELGYRO_BMI160_INT2_OUTPUT)) {
+		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
+				 BMI160_INT_LATCH, BMI160_LATCH_5MS);
+	} else {
+		/* Also, configure int2 as an external input. */
+		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
+				 BMI160_INT_LATCH,
+				 BMI160_INT2_INPUT_EN | BMI160_LATCH_5MS);
+	}
 
 	/* configure int1 as an interrupt */
-	ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-			 BMI160_INT_OUT_CTRL,
+	ret = bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_INT_OUT_CTRL,
 			 BMI160_INT_CTRL(1, OUTPUT_EN));
 
 	/* Map activity interrupt to int 1 */
 	tmp = 0;
-#ifdef CONFIG_GESTURE_SIGMO
-	tmp |= BMI160_INT_ANYMOTION;
-#endif
-#ifdef CONFIG_GESTURE_SENSOR_DOUBLE_TAP
-	tmp |= BMI160_INT_D_TAP;
-#endif
-#ifdef CONFIG_BMI_ORIENTATION_SENSOR
-	/* enable orientation interrupt for lid sensor only */
-	if (s->location == MOTIONSENSE_LOC_LID)
+	if (IS_ENABLED(CONFIG_GESTURE_SIGMO)) {
+		tmp |= BMI160_INT_ANYMOTION;
+	} else if (IS_ENABLED(CONFIG_GESTURE_SENSOR_DOUBLE_TAP)) {
+		tmp |= BMI160_INT_D_TAP;
+	} else if (IS_ENABLED(CONFIG_BMI_ORIENTATION_SENSOR) &&
+		   (s->location == MOTIONSENSE_LOC_LID)) {
+		/* enable orientation interrupt for lid sensor only */
 		tmp |= BMI160_INT_ORIENT;
-#endif
-	ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-			 BMI160_INT_MAP_REG(1), tmp);
+	}
+	ret = bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_INT_MAP_REG(1),
+			 tmp);
 
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
+	if (IS_ENABLED(ACCELGYRO_BMI160_INT_ENABLE)) {
 		/* map fifo water mark to int 1 */
-		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-				 BMI160_INT_FIFO_MAP,
-				 BMI160_INT_MAP(1, FWM) |
-				 BMI160_INT_MAP(1, FFULL));
+		ret = bmi_write8(
+			s->port, s->i2c_spi_addr_flags, BMI160_INT_FIFO_MAP,
+			BMI160_INT_MAP(1, FWM) | BMI160_INT_MAP(1, FFULL));
 
 		/*
 		 * Configure fifo watermark to int whenever there's any data in
@@ -463,16 +443,15 @@ static int config_interrupt(const struct motion_sensor_t *s)
 		 */
 		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
 				 BMI160_FIFO_CONFIG_0, 1);
-#ifdef CONFIG_ACCELGYRO_BMI160_INT2_OUTPUT
-		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-				 BMI160_FIFO_CONFIG_1,
-				 BMI160_FIFO_HEADER_EN);
-#else
-		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-				 BMI160_FIFO_CONFIG_1,
-				 BMI160_FIFO_TAG_INT2_EN |
-				 BMI160_FIFO_HEADER_EN);
-#endif
+		if (IS_ENABLED(CONFIG_ACCELGYRO_BMI160_INT2_OUTPUT))
+			ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
+					 BMI160_FIFO_CONFIG_1,
+					 BMI160_FIFO_HEADER_EN);
+		else
+			ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
+					 BMI160_FIFO_CONFIG_1,
+					 BMI160_FIFO_TAG_INT2_EN |
+						 BMI160_FIFO_HEADER_EN);
 
 		/* Set fifo*/
 		bmi_enable_reg8(s, BMI160_INT_EN_1,
@@ -482,18 +461,17 @@ static int config_interrupt(const struct motion_sensor_t *s)
 	return ret;
 }
 
+#ifdef ACCELGYRO_BMI160_INT_ENABLE
 #ifdef CONFIG_BMI_ORIENTATION_SENSOR
-static void irq_set_orientation(struct motion_sensor_t *s,
-				int interrupt)
+static void irq_set_orientation(struct motion_sensor_t *s, int interrupt)
 {
-	int shifted_masked_orientation =
-		(interrupt >> 24) & BMI160_ORIENT_XY_MASK;
+	int shifted_masked_orientation = (interrupt >> 24) &
+					 BMI160_ORIENT_XY_MASK;
 	if (BMI_GET_DATA(s)->raw_orientation != shifted_masked_orientation) {
 		enum motionsensor_orientation orientation =
 			MOTIONSENSE_ORIENTATION_UNKNOWN;
 
-		BMI_GET_DATA(s)->raw_orientation =
-			shifted_masked_orientation;
+		BMI_GET_DATA(s)->raw_orientation = shifted_masked_orientation;
 
 		switch (shifted_masked_orientation) {
 		case BMI160_ORIENT_PORTRAIT:
@@ -513,11 +491,25 @@ static void irq_set_orientation(struct motion_sensor_t *s,
 		default:
 			break;
 		}
-		orientation = motion_sense_remap_orientation(s, orientation);
-		SET_ORIENTATION(s, orientation);
+		orientation = motion_orientation_remap(s, orientation);
+		*motion_orientation_ptr(s) = orientation;
 	}
 }
-#endif
+#endif /* CONFIG_BMI_ORIENTATION_SENSOR */
+
+/**
+ * bmi160_interrupt - called when the sensor activates the interrupt line.
+ *
+ * This is a "top half" interrupt handler, it just asks motion sense ask
+ * to schedule the "bottom half", ->irq_handler().
+ */
+void bmi160_interrupt(enum gpio_signal signal)
+{
+	last_interrupt_timestamp = __hw_clock_source_read();
+
+	task_set_event(TASK_ID_MOTIONSENSE, CONFIG_ACCELGYRO_BMI160_INT_EVENT);
+}
+
 /**
  * irq_handler - bottom half of the interrupt stack.
  * Ran from the motion_sense task, finds the events that raised the interrupt.
@@ -532,7 +524,7 @@ static int irq_handler(struct motion_sensor_t *s, uint32_t *event)
 	int rv;
 
 	if ((s->type != MOTIONSENSE_TYPE_ACCEL) ||
-			(!(*event & CONFIG_ACCELGYRO_BMI160_INT_EVENT)))
+	    (!(*event & CONFIG_ACCELGYRO_BMI160_INT_EVENT)))
 		return EC_ERROR_NOT_HANDLED;
 
 	do {
@@ -544,26 +536,20 @@ static int irq_handler(struct motion_sensor_t *s, uint32_t *event)
 		if (rv)
 			return rv;
 
-#ifdef CONFIG_GESTURE_SENSOR_DOUBLE_TAP
-		if (interrupt & BMI160_D_TAP_INT) {
+		if (IS_ENABLED(CONFIG_GESTURE_SENSOR_DOUBLE_TAP) &&
+		    (interrupt & BMI160_D_TAP_INT))
 			*event |= TASK_EVENT_MOTION_ACTIVITY_INTERRUPT(
-					MOTIONSENSE_ACTIVITY_DOUBLE_TAP);
-		}
-#endif
-#ifdef CONFIG_GESTURE_SIGMO
-		if (interrupt & BMI160_SIGMOT_INT) {
+				MOTIONSENSE_ACTIVITY_DOUBLE_TAP);
+		if (IS_ENABLED(CONFIG_GESTURE_SIGMO) &&
+		    (interrupt & BMI160_SIGMOT_INT))
 			*event |= TASK_EVENT_MOTION_ACTIVITY_INTERRUPT(
-					MOTIONSENSE_ACTIVITY_SIG_MOTION);
-		}
-#endif
-		if (IS_ENABLED(CONFIG_ACCEL_FIFO) &&
-		    interrupt & (BMI160_FWM_INT | BMI160_FFULL_INT)) {
+				MOTIONSENSE_ACTIVITY_SIG_MOTION);
+		if (interrupt & (BMI160_FWM_INT | BMI160_FFULL_INT)) {
 			bmi_load_fifo(s, last_interrupt_timestamp);
 			has_read_fifo = 1;
 		}
-#ifdef CONFIG_BMI_ORIENTATION_SENSOR
-		irq_set_orientation(s, interrupt);
-#endif
+		if (IS_ENABLED(CONFIG_BMI_ORIENTATION_SENSOR))
+			irq_set_orientation(s, interrupt);
 	} while (interrupt != 0);
 
 	if (IS_ENABLED(CONFIG_ACCEL_FIFO) && has_read_fifo)
@@ -571,26 +557,25 @@ static int irq_handler(struct motion_sensor_t *s, uint32_t *event)
 
 	return EC_SUCCESS;
 }
-#endif  /* CONFIG_ACCEL_INTERRUPTS */
+#endif /* ACCELGYRO_BMI160_INT_ENABLE */
 
-static int init(const struct motion_sensor_t *s)
+static int init(struct motion_sensor_t *s)
 {
 	int ret = 0, tmp, i;
 	struct accelgyro_saved_data_t *saved_data = BMI_GET_SAVED_DATA(s);
 
-	ret = bmi_read8(s->port, s->i2c_spi_addr_flags,
-			BMI160_CHIP_ID, &tmp);
+	ret = bmi_read8(s->port, s->i2c_spi_addr_flags, BMI160_CHIP_ID, &tmp);
 	if (ret)
 		return EC_ERROR_UNKNOWN;
 
 	if (tmp != BMI160_CHIP_ID_MAJOR && tmp != BMI168_CHIP_ID_MAJOR) {
 		/* The device may be lock on paging mode. Try to unlock it. */
-		bmi_write8(s->port, s->i2c_spi_addr_flags,
-			   BMI160_CMD_REG, BMI160_CMD_EXT_MODE_EN_B0);
-		bmi_write8(s->port, s->i2c_spi_addr_flags,
-			   BMI160_CMD_REG, BMI160_CMD_EXT_MODE_EN_B1);
-		bmi_write8(s->port, s->i2c_spi_addr_flags,
-			   BMI160_CMD_REG, BMI160_CMD_EXT_MODE_EN_B2);
+		bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_CMD_REG,
+			   BMI160_CMD_EXT_MODE_EN_B0);
+		bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_CMD_REG,
+			   BMI160_CMD_EXT_MODE_EN_B1);
+		bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_CMD_REG,
+			   BMI160_CMD_EXT_MODE_EN_B2);
 		bmi_write8(s->port, s->i2c_spi_addr_flags,
 			   BMI160_CMD_EXT_MODE_ADDR, BMI160_CMD_PAGING_EN);
 		bmi_write8(s->port, s->i2c_spi_addr_flags,
@@ -598,32 +583,28 @@ static int init(const struct motion_sensor_t *s)
 		return EC_ERROR_ACCESS_DENIED;
 	}
 
-
 	if (s->type == MOTIONSENSE_TYPE_ACCEL) {
 		struct bmi_drv_data_t *data = BMI_GET_DATA(s);
 
 		/* Reset the chip to be in a good state */
-		bmi_write8(s->port, s->i2c_spi_addr_flags,
-			   BMI160_CMD_REG, BMI160_CMD_SOFT_RESET);
+		bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_CMD_REG,
+			   BMI160_CMD_SOFT_RESET);
 		msleep(1);
 		data->flags &= ~(BMI_FLAG_SEC_I2C_ENABLED |
-				(BMI_FIFO_ALL_MASK <<
-				 BMI_FIFO_FLAG_OFFSET));
-#ifdef CONFIG_GESTURE_HOST_DETECTION
-		data->enabled_activities = 0;
-		data->disabled_activities = 0;
-#ifdef CONFIG_GESTURE_SIGMO
-		data->disabled_activities |=
-			1 << MOTIONSENSE_ACTIVITY_SIG_MOTION;
-#endif
-#ifdef CONFIG_GESTURE_SENSOR_DOUBLE_TAP
-		data->disabled_activities |=
-			1 << MOTIONSENSE_ACTIVITY_DOUBLE_TAP;
-#endif
-#endif
+				 (BMI_FIFO_ALL_MASK << BMI_FIFO_FLAG_OFFSET));
+		if (IS_ENABLED(CONFIG_GESTURE_HOST_DETECTION)) {
+			data->enabled_activities = 0;
+			data->disabled_activities = 0;
+			if (IS_ENABLED(CONFIG_GESTURE_SIGMO))
+				data->disabled_activities |=
+					BIT(MOTIONSENSE_ACTIVITY_SIG_MOTION);
+			if (IS_ENABLED(CONFIG_GESTURE_SENSOR_DOUBLE_TAP))
+				data->disabled_activities |=
+					BIT(MOTIONSENSE_ACTIVITY_DOUBLE_TAP);
+		}
 		/* To avoid gyro wakeup */
-		bmi_write8(s->port, s->i2c_spi_addr_flags,
-			   BMI160_PMU_TRIGGER, 0);
+		bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_PMU_TRIGGER,
+			   0);
 	}
 
 #ifdef CONFIG_BMI_SEC_I2C
@@ -634,8 +615,8 @@ static int init(const struct motion_sensor_t *s)
 		 * To be able to configure the real magnetometer, we must set
 		 * the BMI160 magnetometer part (a pass through) in normal mode.
 		 */
-		bmi_write8(s->port, s->i2c_spi_addr_flags,
-			   BMI160_CMD_REG, BMI160_CMD_MODE_NORMAL(s->type));
+		bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_CMD_REG,
+			   BMI160_CMD_MODE_NORMAL(s->type));
 		msleep(wakeup_time[s->type]);
 
 		if ((data->flags & BMI_FLAG_SEC_I2C_ENABLED) == 0) {
@@ -671,21 +652,18 @@ static int init(const struct motion_sensor_t *s)
 				  BMI160_CMD_EXT_MODE_ADDR, &ext_page_reg);
 
 			/* Set the i2c address of the compass */
-			ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-					 BMI160_MAG_IF_0,
-					 I2C_GET_ADDR(
-					     CONFIG_ACCELGYRO_SEC_ADDR_FLAGS)
-					 << 1);
+			ret = bmi_write8(
+				s->port, s->i2c_spi_addr_flags, BMI160_MAG_IF_0,
+				I2C_STRIP_FLAGS(CONFIG_ACCELGYRO_SEC_ADDR_FLAGS)
+					<< 1);
 
 			/* Enable the secondary interface as I2C */
-			ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-					 BMI160_IF_CONF,
-					 BMI160_IF_MODE_AUTO_I2C <<
-					     BMI160_IF_MODE_OFF);
+			ret = bmi_write8(
+				s->port, s->i2c_spi_addr_flags, BMI160_IF_CONF,
+				BMI160_IF_MODE_AUTO_I2C << BMI160_IF_MODE_OFF);
 			data->flags |= BMI_FLAG_SEC_I2C_ENABLED;
 		}
 
-
 		bmi160_sec_access_ctrl(s->port, s->i2c_spi_addr_flags, 1);
 
 		ret = bmm150_init(s);
@@ -707,7 +685,7 @@ static int init(const struct motion_sensor_t *s)
 		 * BMI160 was in management mode.
 		 */
 		task_set_event(TASK_ID_MOTIONSENSE,
-				CONFIG_ACCELGYRO_BMI160_INT_EVENT, 0);
+			       CONFIG_ACCELGYRO_BMI160_INT_EVENT);
 	}
 #endif
 
@@ -718,13 +696,10 @@ static int init(const struct motion_sensor_t *s)
 	 * so set data rate to 0.
 	 */
 	saved_data->odr = 0;
-	bmi_set_range(s, s->default_range, 0);
 
-	if (s->type == MOTIONSENSE_TYPE_ACCEL) {
-#ifdef CONFIG_ACCEL_INTERRUPTS
-		ret = config_interrupt(s);
-#endif
-	}
+	if (IS_ENABLED(ACCELGYRO_BMI160_INT_ENABLE) &&
+	    (s->type == MOTIONSENSE_TYPE_ACCEL))
+		ret = config_accel_interrupt(s);
 
 	return sensor_init_done(s);
 }
@@ -733,7 +708,6 @@ const struct accelgyro_drv bmi160_drv = {
 	.init = init,
 	.read = bmi_read,
 	.set_range = bmi_set_range,
-	.get_range = bmi_get_range,
 	.get_resolution = bmi_get_resolution,
 	.set_data_rate = set_data_rate,
 	.get_data_rate = bmi_get_data_rate,
@@ -743,15 +717,15 @@ const struct accelgyro_drv bmi160_drv = {
 	.get_offset = bmi_get_offset,
 	.perform_calib = perform_calib,
 	.read_temp = bmi_read_temp,
-#ifdef CONFIG_ACCEL_INTERRUPTS
+#ifdef ACCELGYRO_BMI160_INT_ENABLE
 	.irq_handler = irq_handler,
 #endif
 #ifdef CONFIG_GESTURE_HOST_DETECTION
 	.manage_activity = manage_activity,
-	.list_activities = list_activities,
+	.list_activities = bmi_list_activities,
 #endif
 #ifdef CONFIG_BODY_DETECTION
-	.get_rms_noise = bmi_get_rms_noise,
+	.get_rms_noise = get_rms_noise,
 #endif
 };
 
diff --git a/driver/accelgyro_bmi160.h b/driver/accelgyro_bmi160.h
deleted file mode 100644
index c0e8a7128b..0000000000
--- a/driver/accelgyro_bmi160.h
+++ /dev/null
@@ -1,402 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* BMI160 accelerometer and gyro and BMM150 compass module for Chrome EC */
-
-#ifndef __CROS_EC_ACCELGYRO_BMI160_H
-#define __CROS_EC_ACCELGYRO_BMI160_H
-
-#include "accelgyro.h"
-#include "mag_bmm150.h"
-
-/*
- * The addr field of motion_sensor support both SPI and I2C:
- * This is defined in include/i2c.h and is no longer an 8bit
- * address. The 7/10 bit address starts at bit 0 and leaves
- * room for a 10 bit address, although we don't currently
- * have any 10 bit slaves.  I2C or SPI is indicated by a
- * more significant bit
- */
-
-/* I2C addresses */
-#define BMI160_ADDR0_FLAGS	0x68
-
-#define BMI160_CHIP_ID           0x00
-#define BMI160_CHIP_ID_MAJOR     0xd1
-#define BMI168_CHIP_ID_MAJOR     0xd2
-
-#define BMI160_SPEC_ACC_STARTUP_TIME_MS     10
-#define BMI160_SPEC_GYR_STARTUP_TIME_MS     80
-#define BMI160_SPEC_MAG_STARTUP_TIME_MS     60
-
-
-#define BMI160_ERR_REG         0x02
-#define BMI160_PMU_STATUS      0x03
-#define BMI160_PMU_MAG_OFFSET               0
-#define BMI160_PMU_GYR_OFFSET               2
-#define BMI160_PMU_ACC_OFFSET               4
-#define BMI160_PMU_SENSOR_STATUS(_sensor_type, _val) \
-	(((_val) >> (4 - 2 * (_sensor_type))) & 0x3)
-#define BMI160_PMU_SUSPEND                  0
-#define BMI160_PMU_NORMAL                   1
-#define BMI160_PMU_LOW_POWER                2
-#define BMI160_PMU_FAST_STARTUP             3
-
-#define BMI160_MAG_X_L_G       0x04
-#define BMI160_MAG_X_H_G       0x05
-#define BMI160_MAG_Y_L_G       0x06
-#define BMI160_MAG_Y_H_G       0x07
-#define BMI160_MAG_Z_L_G       0x08
-#define BMI160_MAG_Z_H_G       0x09
-#define BMI160_RHALL_L_G       0x0a
-#define BMI160_RHALL_H_G       0x0b
-#define BMI160_GYR_X_L_G       0x0c
-#define BMI160_GYR_X_H_G       0x0d
-#define BMI160_GYR_Y_L_G       0x0e
-#define BMI160_GYR_Y_H_G       0x0f
-#define BMI160_GYR_Z_L_G       0x10
-#define BMI160_GYR_Z_H_G       0x11
-#define BMI160_ACC_X_L_G       0x12
-#define BMI160_ACC_X_H_G       0x13
-#define BMI160_ACC_Y_L_G       0x14
-#define BMI160_ACC_Y_H_G       0x15
-#define BMI160_ACC_Z_L_G       0x16
-#define BMI160_ACC_Z_H_G       0x17
-
-#define BMI160_SENSORTIME_0    0x18
-#define BMI160_SENSORTIME_1    0x19
-#define BMI160_SENSORTIME_2    0x1a
-
-#define BMI160_STATUS          0x1b
-#define BMI160_POR_DETECTED        BIT(0)
-#define BMI160_GYR_SLF_TST         BIT(1)
-#define BMI160_MAG_MAN_OP          BIT(2)
-#define BMI160_FOC_RDY             BIT(3)
-#define BMI160_NVM_RDY             BIT(4)
-#define BMI160_DRDY_MAG            BIT(5)
-#define BMI160_DRDY_GYR            BIT(6)
-#define BMI160_DRDY_ACC            BIT(7)
-#define BMI160_DRDY_OFF(_sensor)   (7 - (_sensor))
-#define BMI160_DRDY_MASK(_sensor)  (1 << BMI160_DRDY_OFF(_sensor))
-
-/* first 2 bytes are the interrupt reasons, next 2 some qualifier */
-#define BMI160_INT_STATUS_0    0x1c
-#define BMI160_STEP_INT            BIT(0)
-#define BMI160_SIGMOT_INT          BIT(1)
-#define BMI160_ANYM_INT            BIT(2)
-#define BMI160_PMU_TRIGGER_INT     BIT(3)
-#define BMI160_D_TAP_INT           BIT(4)
-#define BMI160_S_TAP_INT           BIT(5)
-#define BMI160_ORIENT_INT          BIT(6)
-#define BMI160_FLAT_INT            BIT(7)
-#define BMI160_ORIENT_XY_MASK	   0x30
-#define BMI160_ORIENT_PORTRAIT		(0 << 4)
-#define BMI160_ORIENT_PORTRAIT_INVERT	BIT(4)
-#define BMI160_ORIENT_LANDSCAPE		(2 << 4)
-#define BMI160_ORIENT_LANDSCAPE_INVERT	(3 << 4)
-
-
-#define BMI160_INT_STATUS_1    0x1d
-#define BMI160_HIGHG_INT           (1 << (2 + 8))
-#define BMI160_LOWG_INT            (1 << (3 + 8))
-#define BMI160_DRDY_INT            (1 << (4 + 8))
-#define BMI160_FFULL_INT           (1 << (5 + 8))
-#define BMI160_FWM_INT             (1 << (6 + 8))
-#define BMI160_NOMO_INT            (1 << (7 + 8))
-
-#define BMI160_INT_MASK            0xFFFF
-
-#define BMI160_INT_STATUS_2    0x1e
-#define BMI160_INT_STATUS_3    0x1f
-#define BMI160_FIRST_X             (1 << (0 + 16))
-#define BMI160_FIRST_Y             (1 << (1 + 16))
-#define BMI160_FIRST_Z             (1 << (2 + 16))
-#define BMI160_SIGN                (1 << (3 + 16))
-#define BMI160_ANYM_OFFSET         0
-#define BMI160_TAP_OFFSET          4
-#define BMI160_HIGH_OFFSET         8
-#define BMI160_INT_INFO(_type, _data) \
-(CONCAT2(BMI160_, _data) << CONCAT3(BMI160_, _type, _OFFSET))
-
-#define BMI160_ORIENT_Z            (1 << (6 + 24))
-#define BMI160_FLAT                (1 << (7 + 24))
-
-#define BMI160_TEMPERATURE_0   0x20
-#define BMI160_TEMPERATURE_1   0x21
-
-
-#define BMI160_FIFO_LENGTH_0   0x22
-#define BMI160_FIFO_LENGTH_1   0x23
-#define BMI160_FIFO_LENGTH_MASK    (BIT(11) - 1)
-#define BMI160_FIFO_DATA       0x24
-
-#define BMI160_ACC_CONF        0x40
-#define BMI160_ACC_BW_OFFSET            4
-#define BMI160_ACC_BW_MASK     (0x7 << BMI160_ACC_BW_OFFSET)
-
-#define BMI160_ACC_RANGE       0x41
-#define BMI160_GSEL_2G         0x03
-#define BMI160_GSEL_4G         0x05
-#define BMI160_GSEL_8G         0x08
-#define BMI160_GSEL_16G        0x0c
-
-#define BMI160_GYR_CONF        0x42
-#define BMI160_GYR_BW_OFFSET   4
-#define BMI160_GYR_BW_MASK     (0x3 << BMI160_GYR_BW_OFFSET)
-
-#define BMI160_GYR_RANGE       0x43
-#define BMI160_DPS_SEL_2000    0x00
-#define BMI160_DPS_SEL_1000    0x01
-#define BMI160_DPS_SEL_500     0x02
-#define BMI160_DPS_SEL_250     0x03
-#define BMI160_DPS_SEL_125     0x04
-
-#define BMI160_MAG_CONF        0x44
-
-#define BMI160_FIFO_DOWNS      0x45
-#define BMI160_FIFO_CONFIG_0   0x46
-#define BMI160_FIFO_CONFIG_1   0x47
-#define BMI160_FIFO_TAG_TIME_EN    BIT(1)
-#define BMI160_FIFO_TAG_INT2_EN    BIT(2)
-#define BMI160_FIFO_TAG_INT1_EN    BIT(3)
-#define BMI160_FIFO_HEADER_EN      BIT(4)
-#define BMI160_FIFO_MAG_EN         BIT(5)
-#define BMI160_FIFO_ACC_EN         BIT(6)
-#define BMI160_FIFO_GYR_EN         BIT(7)
-#define BMI160_FIFO_TARG_INT(_i)  CONCAT3(BMI160_FIFO_TAG_INT, _i, _EN)
-#define BMI160_FIFO_SENSOR_EN(_sensor) \
-	((_sensor) == MOTIONSENSE_TYPE_ACCEL ? BMI160_FIFO_ACC_EN : \
-	  ((_sensor) == MOTIONSENSE_TYPE_GYRO ? BMI160_FIFO_GYR_EN : \
-	   BMI160_FIFO_MAG_EN))
-
-#define BMI160_MAG_IF_0        0x4b
-#define BMI160_MAG_I2C_ADDRESS BMI160_MAG_IF_0
-#define BMI160_MAG_IF_1        0x4c
-#define BMI160_MAG_I2C_CONTROL BMI160_MAG_IF_1
-#define BMI160_MAG_READ_BURST_MASK 3
-#define BMI160_MAG_READ_BURST_1    0
-#define BMI160_MAG_READ_BURST_2    1
-#define BMI160_MAG_READ_BURST_6    2
-#define BMI160_MAG_READ_BURST_8    3
-#define BMI160_MAG_OFFSET_OFF      3
-#define BMI160_MAG_OFFSET_MASK     (0xf << BMI160_MAG_OFFSET_OFF)
-#define BMI160_MAG_MANUAL_EN       BIT(7)
-
-#define BMI160_MAG_IF_2        0x4d
-#define BMI160_MAG_I2C_READ_ADDR    BMI160_MAG_IF_2
-#define BMI160_MAG_IF_3        0x4e
-#define BMI160_MAG_I2C_WRITE_ADDR   BMI160_MAG_IF_3
-#define BMI160_MAG_IF_4        0x4f
-#define BMI160_MAG_I2C_WRITE_DATA   BMI160_MAG_IF_4
-#define BMI160_MAG_I2C_READ_DATA    BMI160_MAG_X_L_G
-
-#define BMI160_INT_EN_0        0x50
-#define BMI160_INT_ANYMO_X_EN      BIT(0)
-#define BMI160_INT_ANYMO_Y_EN      BIT(1)
-#define BMI160_INT_ANYMO_Z_EN      BIT(2)
-#define BMI160_INT_D_TAP_EN        BIT(4)
-#define BMI160_INT_S_TAP_EN        BIT(5)
-#define BMI160_INT_ORIENT_EN       BIT(6)
-#define BMI160_INT_FLAT_EN         BIT(7)
-#define BMI160_INT_EN_1        0x51
-#define BMI160_INT_HIGHG_X_EN      BIT(0)
-#define BMI160_INT_HIGHG_Y_EN      BIT(1)
-#define BMI160_INT_HIGHG_Z_EN      BIT(2)
-#define BMI160_INT_LOW_EN          BIT(3)
-#define BMI160_INT_DRDY_EN         BIT(4)
-#define BMI160_INT_FFUL_EN         BIT(5)
-#define BMI160_INT_FWM_EN          BIT(6)
-#define BMI160_INT_EN_2        0x52
-#define BMI160_INT_NOMOX_EN        BIT(0)
-#define BMI160_INT_NOMOY_EN        BIT(1)
-#define BMI160_INT_NOMOZ_EN        BIT(2)
-#define BMI160_INT_STEP_DET_EN     BIT(3)
-
-#define BMI160_INT_OUT_CTRL    0x53
-#define BMI160_INT_EDGE_CTRL       BIT(0)
-#define BMI160_INT_LVL_CTRL        BIT(1)
-#define BMI160_INT_OD              BIT(2)
-#define BMI160_INT_OUTPUT_EN       BIT(3)
-#define BMI160_INT1_CTRL_OFFSET     0
-#define BMI160_INT2_CTRL_OFFSET     4
-#define BMI160_INT_CTRL(_i, _bit) \
-(CONCAT2(BMI160_INT_, _bit) << CONCAT3(BMI160_INT, _i, _CTRL_OFFSET))
-
-#define BMI160_INT_LATCH       0x54
-#define BMI160_INT1_INPUT_EN       BIT(4)
-#define BMI160_INT2_INPUT_EN       BIT(5)
-#define BMI160_LATCH_MASK          0xf
-#define BMI160_LATCH_NONE          0
-#define BMI160_LATCH_5MS           5
-#define BMI160_LATCH_FOREVER       0xf
-
-#define BMI160_INT_MAP_0       0x55
-#define BMI160_INT_LOWG_STEP       BIT(0)
-#define BMI160_INT_HIGHG           BIT(1)
-#define BMI160_INT_ANYMOTION       BIT(2)
-#define BMI160_INT_NOMOTION        BIT(3)
-#define BMI160_INT_D_TAP           BIT(4)
-#define BMI160_INT_S_TAP           BIT(5)
-#define BMI160_INT_ORIENT          BIT(6)
-#define BMI160_INT_FLAT            BIT(7)
-
-#define BMI160_INT_MAP_1       0x56
-#define BMI160_INT_PMU_TRIG        BIT(0)
-#define BMI160_INT_FFULL           BIT(1)
-#define BMI160_INT_FWM             BIT(2)
-#define BMI160_INT_DRDY            BIT(3)
-#define BMI160_INT1_MAP_OFFSET      4
-#define BMI160_INT2_MAP_OFFSET      0
-#define BMI160_INT_MAP(_i, _bit) \
-(CONCAT2(BMI160_INT_, _bit) << CONCAT3(BMI160_INT, _i, _MAP_OFFSET))
-#define BMI160_INT_FIFO_MAP    BMI160_INT_MAP_1
-
-#define BMI160_INT_MAP_2       0x57
-
-#define BMI160_INT_MAP_INT_1   BMI160_INT_MAP_0
-#define BMI160_INT_MAP_INT_2   BMI160_INT_MAP_2
-#define BMI160_INT_MAP_REG(_i)  CONCAT2(BMI160_INT_MAP_INT_, _i)
-
-#define BMI160_INT_DATA_0      0x58
-#define BMI160_INT_DATA_1      0x59
-
-#define BMI160_INT_MOTION_0    0x5f
-#define BMI160_INT_MOTION_1    0x60
-/*
- * The formula is defined in 2.11.25 (any motion interrupt [1]).
- *
- * if we want threshold at a (in mg), the register should be x, where
- * x * 7.81mg = a, assuming a range of 4G, which is
- * x * 4 * 1.953 = a so
- * x = a * 1000 / range * 1953
- */
-#define BMI160_MOTION_TH(_s, _mg) \
-	 (MIN(((_mg) * 1000) / ((_s)->drv->get_range(_s) * 1953), 0xff))
-#define BMI160_INT_MOTION_2    0x61
-#define BMI160_INT_MOTION_3    0x62
-#define BMI160_MOTION_NO_MOT_SEL   BIT(0)
-#define BMI160_MOTION_SIG_MOT_SEL  BIT(1)
-#define BMI160_MOTION_SKIP_OFF 2
-#define BMI160_MOTION_SKIP_MASK 0x3
-#define BMI160_MOTION_SKIP_TIME(_ms) \
-	(MIN(__fls((_ms) / 1500), BMI160_MOTION_SKIP_MASK))
-#define BMI160_MOTION_PROOF_OFF 4
-#define BMI160_MOTION_PROOF_MASK 0x3
-#define BMI160_MOTION_PROOF_TIME(_ms) \
-	(MIN(__fls((_ms) / 250), BMI160_MOTION_PROOF_MASK))
-
-#define BMI160_INT_TAP_0       0x63
-#define BMI160_TAP_DUR(_s, _ms) \
-	((_ms) <= 250 ? MAX((_ms), 50) / 50 - 1 : \
-	 (_ms) <= 500 ? 4 + ((_ms) - 250) / 125 : \
-	 (_ms) < 700 ? 6 : 7)
-
-#define BMI160_INT_TAP_1       0x64
-#define BMI160_TAP_TH(_s, _mg) \
-	 (MIN(((_mg) * 1000) / ((_s)->drv->get_range(_s) * 31250), 0x1f))
-
-#define BMI160_INT_ORIENT_0				0x65
-
-/* No hysterisis, theta block, int on slope > 0.2 or axis > 1.5, symmetrical */
-#define BMI160_INT_ORIENT_0_INIT_VAL			0x48
-
-#define BMI160_INT_ORIENT_1				0x66
-
-/* no axes remap, no int on up/down, no blocking angle */
-#define BMI160_INT_ORIENT_1_INIT_VAL			0x00
-
-#define BMI160_INT_FLAT_0      0x67
-#define BMI160_INT_FLAT_1      0x68
-
-#define BMI160_FOC_CONF        0x69
-#define BMI160_FOC_GYRO_EN              BIT(6)
-#define BMI160_FOC_ACC_PLUS_1G          1
-#define BMI160_FOC_ACC_MINUS_1G         2
-#define BMI160_FOC_ACC_0G               3
-#define BMI160_FOC_ACC_Z_OFFSET         0
-#define BMI160_FOC_ACC_Y_OFFSET         2
-#define BMI160_FOC_ACC_X_OFFSET         4
-
-#define BMI160_CONF            0x6a
-#define BMI160_IF_CONF         0x6b
-#define BMI160_IF_MODE_OFF     4
-#define BMI160_IF_MODE_MASK    3
-#define BMI160_IF_MODE_AUTO_OFF 0
-#define BMI160_IF_MODE_I2C_IOS  1
-#define BMI160_IF_MODE_AUTO_I2C 2
-
-#define BMI160_PMU_TRIGGER     0x6c
-#define BMI160_SELF_TEST       0x6d
-
-#define BMI160_OFFSET_ACC70        0x71
-#define BMI160_OFFSET_GYR70        0x74
-#define BMI160_OFFSET_EN_GYR98     0x77
-#define BMI160_OFFSET_ACC_EN            BIT(6)
-#define BMI160_OFFSET_GYRO_EN           BIT(7)
-
-
-#define BMI160_CMD_REG             0x7e
-#define BMI160_CMD_SOFT_RESET      0xb6
-#define BMI160_CMD_NOOP            0x00
-#define BMI160_CMD_START_FOC       0x03
-#define BMI160_CMD_ACC_MODE_OFFSET 0x10
-#define BMI160_CMD_ACC_MODE_SUSP   0x10
-#define BMI160_CMD_ACC_MODE_NORMAL 0x11
-#define BMI160_CMD_ACC_MODE_LOWPOWER 0x12
-#define BMI160_CMD_GYR_MODE_SUSP   0x14
-#define BMI160_CMD_GYR_MODE_NORMAL 0x15
-#define BMI160_CMD_GYR_MODE_FAST_STARTUP 0x17
-#define BMI160_CMD_MAG_MODE_SUSP   0x18
-#define BMI160_CMD_MAG_MODE_NORMAL 0x19
-#define BMI160_CMD_MAG_MODE_LOWPOWER 0x1a
-#define BMI160_CMD_MODE_SUSPEND(_sensor_type) \
-	(BMI160_CMD_ACC_MODE_OFFSET | (_sensor_type) << 2 | BMI160_PMU_SUSPEND)
-#define BMI160_CMD_MODE_NORMAL(_sensor_type) \
-	(BMI160_CMD_ACC_MODE_OFFSET | (_sensor_type) << 2 | BMI160_PMU_NORMAL)
-
-#define BMI160_CMD_FIFO_FLUSH      0xb0
-#define BMI160_CMD_INT_RESET       0xb1
-#define BMI160_CMD_SOFT_RESET      0xb6
-#define BMI160_CMD_EXT_MODE_EN_B0  0x37
-#define BMI160_CMD_EXT_MODE_EN_B1  0x9a
-#define BMI160_CMD_EXT_MODE_EN_B2  0xc0
-
-#define BMI160_CMD_EXT_MODE_ADDR   0x7f
-#define BMI160_CMD_PAGING_EN           BIT(7)
-#define BMI160_CMD_TARGET_PAGE         BIT(4)
-#define BMI160_COM_C_TRIM_ADDR 0x85
-#define BMI160_COM_C_TRIM              (3 << 4)
-
-#define BMI160_CMD_TGT_PAGE    0
-#define BMI160_CMD_TGT_PAGE_COM    1
-#define BMI160_CMD_TGT_PAGE_ACC    2
-#define BMI160_CMD_TGT_PAGE_GYR    3
-
-#define BMI160_FF_FRAME_LEN_TS          4
-#define BMI160_FF_DATA_LEN_ACC          6
-#define BMI160_FF_DATA_LEN_GYR          6
-#define BMI160_FF_DATA_LEN_MAG          8
-
-/* Root mean square noise of 100 Hz accelerometer, units: ug */
-#define BMI160_ACCEL_RMS_NOISE_100HZ    1300
-
-extern const struct accelgyro_drv bmi160_drv;
-
-void bmi160_interrupt(enum gpio_signal signal);
-
-#ifdef CONFIG_BMI_SEC_I2C
-/* Functions to access the secondary device through the accel/gyro. */
-int bmi160_sec_raw_read8(const int port, const uint16_t addr_flags,
-			 const uint8_t reg, int *data_ptr);
-int bmi160_sec_raw_write8(const int port, const uint16_t addr_flags,
-			  const uint8_t reg, int data);
-#endif
-
-#ifdef CONFIG_CMD_I2C_STRESS_TEST_ACCEL
-extern struct i2c_stress_test_dev bmi160_i2c_stress_test_dev;
-#endif
-
-int bmi160_get_sensor_temp(int idx, int *temp_ptr);
-#endif /* __CROS_EC_ACCELGYRO_BMI160_H */
diff --git a/driver/accelgyro_bmi260.c b/driver/accelgyro_bmi260.c
index cd75de2d9d..1b47983b80 100644
--- a/driver/accelgyro_bmi260.c
+++ b/driver/accelgyro_bmi260.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,10 +9,10 @@
  */
 
 #include "accelgyro.h"
+#include "accelgyro_bmi260.h"
+#include "accelgyro_bmi_common.h"
+#include "builtin/assert.h"
 #include "console.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_bmi260.h"
-#include "endian.h"
 #include "hwtimer.h"
 #include "i2c.h"
 #include "init_rom.h"
@@ -20,55 +20,60 @@
 #include "motion_sense_fifo.h"
 #include "spi.h"
 #include "task.h"
-#include "third_party/bmi260/accelgyro_bmi260_config_tbin.h"
 #include "timer.h"
 #include "util.h"
 #include "watchdog.h"
 
+#ifdef CONFIG_ACCELGYRO_BMI260_INT_EVENT
+#define ACCELGYRO_BMI260_INT_ENABLE
+#endif
+
+/* BMI220/BMI260 firmware binary */
+#if defined(CONFIG_ACCELGYRO_BMI220)
+#include "bmi220/accelgyro_bmi220_config_tbin.h"
+#endif /* CONFIG_ACCELGYRO_BMI220 */
+
+#if defined(CONFIG_ACCELGYRO_BMI260)
+#include "bmi260/accelgyro_bmi260_config_tbin.h"
+#endif /* CONFIG_ACCELGYRO_BMI260 */
+
 #define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args)
 
-STATIC_IF(CONFIG_ACCEL_FIFO) volatile uint32_t last_interrupt_timestamp;
+STATIC_IF(ACCELGYRO_BMI260_INT_ENABLE)
+volatile uint32_t last_interrupt_timestamp;
 
 /*
  * The gyro start-up time is 45ms in normal mode
  *                            2ms in fast start-up mode
  */
-static int wakeup_time[] = {
-	[MOTIONSENSE_TYPE_ACCEL] = 2,
-	[MOTIONSENSE_TYPE_GYRO] = 45,
-	[MOTIONSENSE_TYPE_MAG] = 1
-};
+static int wakeup_time[] = { [MOTIONSENSE_TYPE_ACCEL] = 2,
+			     [MOTIONSENSE_TYPE_GYRO] = 45,
+			     [MOTIONSENSE_TYPE_MAG] = 1 };
 
 static int enable_sensor(const struct motion_sensor_t *s, int enable)
 {
 	int ret;
 
-	ret = bmi_enable_reg8(s, BMI260_PWR_CTRL,
-			      BMI260_PWR_EN(s->type),
+	ret = bmi_enable_reg8(s, BMI260_PWR_CTRL, BMI260_PWR_EN(s->type),
 			      enable);
 	if (ret)
 		return ret;
 
 	if (s->type == MOTIONSENSE_TYPE_GYRO) {
 		/* switch to performance mode */
-		ret = bmi_enable_reg8(s, BMI_CONF_REG(s->type),
-				      BMI260_FILTER_PERF |
-				      BMI260_GYR_NOISE_PERF,
-				      enable);
+		ret = bmi_enable_reg8(
+			s, BMI_CONF_REG(s->type),
+			BMI260_FILTER_PERF | BMI260_GYR_NOISE_PERF, enable);
 	} else {
 		ret = bmi_enable_reg8(s, BMI_CONF_REG(s->type),
-				      BMI260_FILTER_PERF,
-				      enable);
+				      BMI260_FILTER_PERF, enable);
 	}
 	return ret;
-
 }
 
-static int set_data_rate(const struct motion_sensor_t *s,
-			 int rate,
-			 int rnd)
+static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
 {
 	int ret, normalized_rate;
 	uint8_t reg_val;
@@ -76,7 +81,7 @@ static int set_data_rate(const struct motion_sensor_t *s,
 
 	if (rate == 0) {
 		/* FIFO stop collecting events */
-		if (IS_ENABLED(CONFIG_ACCEL_FIFO))
+		if (IS_ENABLED(ACCELGYRO_BMI260_INT_ENABLE))
 			bmi_enable_fifo(s, 0);
 		/* disable sensor */
 		ret = enable_sensor(s, 0);
@@ -92,8 +97,7 @@ static int set_data_rate(const struct motion_sensor_t *s,
 		msleep(wakeup_time[s->type]);
 	}
 
-	ret = bmi_get_normalized_rate(s, rate, rnd,
-				      &normalized_rate, &reg_val);
+	ret = bmi_get_normalized_rate(s, rate, rnd, &normalized_rate, &reg_val);
 	if (ret)
 		return ret;
 
@@ -103,14 +107,10 @@ static int set_data_rate(const struct motion_sensor_t *s,
 	 */
 	mutex_lock(s->mutex);
 
-	ret = bmi_set_reg8(s, BMI_CONF_REG(s->type),
-			   reg_val, BMI_ODR_MASK);
+	ret = bmi_set_reg8(s, BMI_CONF_REG(s->type), reg_val, BMI_ODR_MASK);
 	if (ret != EC_SUCCESS)
 		goto accel_cleanup;
 
-	/* Wait for the change to become effective */
-	if (data->odr != 0)
-		msleep(1000000 / MIN(data->odr, normalized_rate));
 	/* Now that we have set the odr, update the driver's value. */
 	data->odr = normalized_rate;
 
@@ -118,40 +118,44 @@ static int set_data_rate(const struct motion_sensor_t *s,
 	 * FIFO start collecting events.
 	 * They will be discarded if AP does not want them.
 	 */
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO))
+	if (IS_ENABLED(ACCELGYRO_BMI260_INT_ENABLE))
 		bmi_enable_fifo(s, 1);
 accel_cleanup:
 	mutex_unlock(s->mutex);
 	return ret;
 }
 
-static int set_offset(const struct motion_sensor_t *s,
-			const int16_t *offset,
-			int16_t    temp)
+static int set_offset(const struct motion_sensor_t *s, const int16_t *offset,
+		      int16_t temp)
 {
 	int ret, val98, val_nv_conf;
 	intv3_t v = { offset[X], offset[Y], offset[Z] };
 
 	rotate_inv(v, *s->rot_standard_ref, v);
 
-	ret = bmi_read8(s->port, s->i2c_spi_addr_flags,
-			BMI260_OFFSET_EN_GYR98, &val98);
+	ret = bmi_read8(s->port, s->i2c_spi_addr_flags, BMI260_OFFSET_EN_GYR98,
+			&val98);
 	if (ret)
 		return ret;
-	ret = bmi_read8(s->port, s->i2c_spi_addr_flags,
-			BMI260_NV_CONF, &val_nv_conf);
+	ret = bmi_read8(s->port, s->i2c_spi_addr_flags, BMI260_NV_CONF,
+			&val_nv_conf);
 	if (ret)
 		return ret;
 
 	switch (s->type) {
 	case MOTIONSENSE_TYPE_ACCEL:
-		bmi_set_accel_offset(s, v);
-		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-				 BMI260_NV_CONF,
+		ret = bmi_set_accel_offset(s, v);
+		if (ret != EC_SUCCESS)
+			return ret;
+
+		ret = bmi_write8(s->port, s->i2c_spi_addr_flags, BMI260_NV_CONF,
 				 val_nv_conf | BMI260_ACC_OFFSET_EN);
 		break;
 	case MOTIONSENSE_TYPE_GYRO:
-		bmi_set_gyro_offset(s, v, &val98);
+		ret = bmi_set_gyro_offset(s, v, &val98);
+		if (ret != EC_SUCCESS)
+			return ret;
+
 		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
 				 BMI260_OFFSET_EN_GYR98,
 				 val98 | BMI260_OFFSET_GYRO_EN);
@@ -162,8 +166,15 @@ static int set_offset(const struct motion_sensor_t *s,
 	return ret;
 }
 
-static int wait_and_read_data(const struct motion_sensor_t *s,
-			      intv3_t v, int try_cnt, int msec)
+#ifdef CONFIG_BODY_DETECTION
+static int get_rms_noise(const struct motion_sensor_t *s)
+{
+	return bmi_get_rms_noise(s, BMI260_ACCEL_RMS_NOISE_100HZ);
+}
+#endif
+
+static int wait_and_read_data(const struct motion_sensor_t *s, intv3_t v,
+			      int try_cnt, int msec)
 {
 	uint8_t data[6];
 	int ret, status = 0;
@@ -171,8 +182,8 @@ static int wait_and_read_data(const struct motion_sensor_t *s,
 	/* Check if data is ready */
 	while (try_cnt && !(status & BMI260_DRDY_ACC)) {
 		msleep(msec);
-		ret = bmi_read8(s->port, s->i2c_spi_addr_flags,
-				BMI260_STATUS, &status);
+		ret = bmi_read8(s->port, s->i2c_spi_addr_flags, BMI260_STATUS,
+				&status);
 		if (ret)
 			return ret;
 		try_cnt -= 1;
@@ -180,18 +191,18 @@ static int wait_and_read_data(const struct motion_sensor_t *s,
 	if (!(status & BMI260_DRDY_ACC))
 		return EC_ERROR_TIMEOUT;
 	/* Read 6 bytes starting at xyz_reg */
-	ret = bmi_read_n(s->port, s->i2c_spi_addr_flags,
-			 bmi_get_xyz_reg(s), data, 6);
+	ret = bmi_read_n(s->port, s->i2c_spi_addr_flags, bmi_get_xyz_reg(s),
+			 data, 6);
 	bmi_normalize(s, v, data);
 	return ret;
 }
 
-static int calibrate_offset(const struct motion_sensor_t *s,
-			    int range, intv3_t target, int16_t *offset)
+static int calibrate_offset(const struct motion_sensor_t *s, int range,
+			    intv3_t target, int16_t *offset)
 {
 	int ret = EC_ERROR_UNKNOWN;
 	int i, n_sample = 32;
-	int data_diff[3] = {0};
+	int data_diff[3] = { 0 };
 
 	/* Manually offset compensation */
 	for (i = 0; i < n_sample; ++i) {
@@ -207,22 +218,29 @@ static int calibrate_offset(const struct motion_sensor_t *s,
 
 	/* The data LSB: 1000 * range / 32768 (mdps | mg)*/
 	for (i = X; i <= Z; ++i)
-		offset[i] -= ((int64_t)(data_diff[i] / n_sample) *
-			     1000 * range) >> 15;
+		offset[i] -=
+			((int64_t)(data_diff[i] / n_sample) * 1000 * range) >>
+			15;
 	return ret;
 }
 
-static int perform_calib(const struct motion_sensor_t *s, int enable)
+static int perform_calib(struct motion_sensor_t *s, int enable)
 {
 	int ret, rate;
 	int16_t temp;
 	int16_t offset[3];
-	intv3_t target = {0, 0, 0};
+	intv3_t target = { 0, 0, 0 };
 	/* Get sensor range for calibration*/
-	int range = bmi_get_range(s);
+	int range = s->current_range;
 
 	if (!enable)
 		return EC_SUCCESS;
+
+	/* We only support accelerometers and gyroscopes */
+	if (s->type != MOTIONSENSE_TYPE_ACCEL &&
+	    s->type != MOTIONSENSE_TYPE_GYRO)
+		return EC_RES_INVALID_PARAM;
+
 	rate = bmi_get_data_rate(s);
 	ret = set_data_rate(s, 100000, 0);
 	if (ret)
@@ -238,10 +256,12 @@ static int perform_calib(const struct motion_sensor_t *s, int enable)
 		break;
 	case MOTIONSENSE_TYPE_GYRO:
 		break;
+	/* LCOV_EXCL_START */
 	default:
-		/* Not supported on Magnetometer */
-		ret = EC_RES_INVALID_PARAM;
-		goto end_perform_calib;
+		/* Unreachable due to sensor type check above. */
+		ASSERT(false);
+		break;
+		/* LCOV_EXCL_STOP */
 	}
 
 	/* Get the calibrated offset */
@@ -260,85 +280,74 @@ static int perform_calib(const struct motion_sensor_t *s, int enable)
 	return ret;
 }
 
-#ifdef CONFIG_ACCEL_INTERRUPTS
-
 /**
- * bmi260_interrupt - called when the sensor activates the interrupt line.
+ * config_interrupt - sets up the interrupt request output pin on the BMI260
  *
- * This is a "top half" interrupt handler, it just asks motion sense ask
- * to schedule the "bottom half", ->irq_handler().
+ * Note: this function only supports motion_sensor_t structs of type
+ * MOTIONSENSE_TYPE_ACCEL and expects the caller to verify this.
  */
-void bmi260_interrupt(enum gpio_signal signal)
-{
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO))
-		last_interrupt_timestamp = __hw_clock_source_read();
-
-	task_set_event(TASK_ID_MOTIONSENSE,
-		       CONFIG_ACCELGYRO_BMI260_INT_EVENT, 0);
-}
-
-static int config_interrupt(const struct motion_sensor_t *s)
+static __maybe_unused int config_interrupt(const struct motion_sensor_t *s)
 {
 	int ret;
 
-	if (s->type != MOTIONSENSE_TYPE_ACCEL)
-		return EC_SUCCESS;
-
 	mutex_lock(s->mutex);
-	bmi_write8(s->port, s->i2c_spi_addr_flags,
-		   BMI260_CMD_REG, BMI260_CMD_FIFO_FLUSH);
+	bmi_write8(s->port, s->i2c_spi_addr_flags, BMI260_CMD_REG,
+		   BMI260_CMD_FIFO_FLUSH);
 
 	/* configure int1 as an interrupt */
-	ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-			 BMI260_INT1_IO_CTRL,
+	ret = bmi_write8(s->port, s->i2c_spi_addr_flags, BMI260_INT1_IO_CTRL,
 			 BMI260_INT1_OUTPUT_EN);
-#ifdef CONFIG_ACCELGYRO_BMI260_INT2_OUTPUT
-	/* TODO(chingkang): Test it if we want int2 as an interrupt */
-	/* configure int2 as an interrupt */
-	ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-			 BMI260_INT2_IO_CTRL,
-			 BMI260_INT2_OUTPUT_EN);
-#else
-	/* configure int2 as an external input. */
-	ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-			 BMI260_INT2_IO_CTRL,
-			 BMI260_INT2_INPUT_EN);
-#endif
-
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
-		/* map fifo water mark to int 1 */
+	if (IS_ENABLED(CONFIG_ACCELGYRO_BMI260_INT2_OUTPUT))
+		/* TODO(chingkang): Test it if we want int2 as an interrupt */
+		/* configure int2 as an interrupt */
+		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
+				 BMI260_INT2_IO_CTRL, BMI260_INT2_OUTPUT_EN);
+	else
+		/* configure int2 as an external input. */
 		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-				 BMI260_INT_MAP_DATA,
-				 BMI260_INT_MAP_DATA_REG(1, FWM) |
+				 BMI260_INT2_IO_CTRL, BMI260_INT2_INPUT_EN);
+
+	/* map fifo water mark to int 1 */
+	ret = bmi_write8(s->port, s->i2c_spi_addr_flags, BMI260_INT_MAP_DATA,
+			 BMI260_INT_MAP_DATA_REG(1, FWM) |
 				 BMI260_INT_MAP_DATA_REG(1, FFULL));
 
-		/*
-		 * Configure fifo watermark to int whenever there's any data in
-		 * there
-		 */
-		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-				 BMI260_FIFO_WTM_0, 1);
-		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-				 BMI260_FIFO_WTM_1, 0);
-#ifdef CONFIG_ACCELGYRO_BMI260_INT2_OUTPUT
+	/*
+	 * Configure fifo watermark to int whenever there's any data in
+	 * there
+	 */
+	ret = bmi_write8(s->port, s->i2c_spi_addr_flags, BMI260_FIFO_WTM_0, 1);
+	ret = bmi_write8(s->port, s->i2c_spi_addr_flags, BMI260_FIFO_WTM_1, 0);
+	if (IS_ENABLED(CONFIG_ACCELGYRO_BMI260_INT2_OUTPUT))
 		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-				 BMI260_FIFO_CONFIG_1,
-				 BMI260_FIFO_HEADER_EN);
-#else
+				 BMI260_FIFO_CONFIG_1, BMI260_FIFO_HEADER_EN);
+	else
 		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
 				 BMI260_FIFO_CONFIG_1,
-				 (BMI260_FIFO_TAG_INT_LEVEL <<
-				 BMI260_FIFO_TAG_INT2_EN_OFFSET) |
-				 BMI260_FIFO_HEADER_EN);
-#endif
-		/* disable FIFO sensortime frame */
-		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-				 BMI260_FIFO_CONFIG_0, 0);
-	}
+				 (BMI260_FIFO_TAG_INT_LEVEL
+				  << BMI260_FIFO_TAG_INT2_EN_OFFSET) |
+					 BMI260_FIFO_HEADER_EN);
+	/* disable FIFO sensortime frame */
+	ret = bmi_write8(s->port, s->i2c_spi_addr_flags, BMI260_FIFO_CONFIG_0,
+			 0);
 	mutex_unlock(s->mutex);
 	return ret;
 }
 
+#ifdef ACCELGYRO_BMI260_INT_ENABLE
+/**
+ * bmi260_interrupt - called when the sensor activates the interrupt line.
+ *
+ * This is a "top half" interrupt handler, it just asks motion sense ask
+ * to schedule the "bottom half", ->irq_handler().
+ */
+void bmi260_interrupt(enum gpio_signal signal)
+{
+	last_interrupt_timestamp = __hw_clock_source_read();
+
+	task_set_event(TASK_ID_MOTIONSENSE, CONFIG_ACCELGYRO_BMI260_INT_EVENT);
+}
+
 /**
  * irq_handler - bottom half of the interrupt stack.
  * Ran from the motion_sense task, finds the events that raised the interrupt.
@@ -354,7 +363,7 @@ static int irq_handler(struct motion_sensor_t *s, uint32_t *event)
 	int rv;
 
 	if ((s->type != MOTIONSENSE_TYPE_ACCEL) ||
-			(!(*event & CONFIG_ACCELGYRO_BMI260_INT_EVENT)))
+	    (!(*event & CONFIG_ACCELGYRO_BMI260_INT_EVENT)))
 		return EC_ERROR_NOT_HANDLED;
 
 	do {
@@ -366,8 +375,7 @@ static int irq_handler(struct motion_sensor_t *s, uint32_t *event)
 		if (rv)
 			return rv;
 
-		if (IS_ENABLED(CONFIG_ACCEL_FIFO) &&
-			interrupt & (BMI260_FWM_INT | BMI260_FFULL_INT)) {
+		if (interrupt & (BMI260_FWM_INT | BMI260_FFULL_INT)) {
 			bmi_load_fifo(s, last_interrupt_timestamp);
 			has_read_fifo = 1;
 		}
@@ -378,17 +386,17 @@ static int irq_handler(struct motion_sensor_t *s, uint32_t *event)
 
 	return EC_SUCCESS;
 }
-#endif  /* CONFIG_ACCEL_INTERRUPTS */
+#endif /* ACCELGYRO_BMI260_INT_ENABLE */
 
 /*
  * If the .init_rom section is not memory mapped, we need a static
  * buffer in RAM to access the BMI configuration data.
  */
 #ifdef CONFIG_CHIP_INIT_ROM_REGION
-#define BMI_RAM_BUFFER_SIZE		256
+#define BMI_RAM_BUFFER_SIZE 256
 static uint8_t bmi_ram_buffer[BMI_RAM_BUFFER_SIZE];
 #else
-#define BMI_RAM_BUFFER_SIZE		0
+#define BMI_RAM_BUFFER_SIZE 0
 static uint8_t *bmi_ram_buffer;
 #endif
 
@@ -397,6 +405,8 @@ static int bmi_config_load(const struct motion_sensor_t *s)
 	int ret = EC_SUCCESS;
 	uint16_t i;
 	const uint8_t *bmi_config = NULL;
+	const unsigned char *bmi_config_tbin;
+	int bmi_config_tbin_len;
 	/*
 	 * Due to i2c transaction timeout limit,
 	 * burst_write_len should not be above 2048 to prevent timeout.
@@ -407,8 +417,26 @@ static int bmi_config_load(const struct motion_sensor_t *s)
 	 * The BMI config data may be linked into .rodata or the .init_rom
 	 * section. Get the actual memory mapped address.
 	 */
-	bmi_config = init_rom_map(g_bmi260_config_tbin,
-				  g_bmi260_config_tbin_len);
+	switch (s->chip) {
+#ifdef CONFIG_ACCELGYRO_BMI220
+	case MOTIONSENSE_CHIP_BMI220:
+		bmi_config_tbin = g_bmi220_config_tbin;
+		bmi_config_tbin_len = g_bmi220_config_tbin_len;
+		break;
+#endif /* CONFIG_ACCELGYRO_BMI220 */
+
+#ifdef CONFIG_ACCELGYRO_BMI260
+	case MOTIONSENSE_CHIP_BMI260:
+		bmi_config_tbin = g_bmi260_config_tbin;
+		bmi_config_tbin_len = g_bmi260_config_tbin_len;
+		break;
+#endif /* CONFIG_ACCELGYRO_BMI260 */
+
+	default:
+		return EC_ERROR_INVALID_CONFIG;
+	}
+
+	bmi_config = init_rom_map(bmi_config_tbin, bmi_config_tbin_len);
 
 	/*
 	 * init_rom_map() only returns NULL when the CONFIG_CHIP_INIT_ROM_REGION
@@ -422,10 +450,9 @@ static int bmi_config_load(const struct motion_sensor_t *s)
 	/* We have to write the config even bytes of data every time */
 	ASSERT(((burst_write_len & 1) == 0) && (burst_write_len != 0));
 
-	for (i = 0; i < g_bmi260_config_tbin_len; i += burst_write_len) {
+	for (i = 0; i < bmi_config_tbin_len; i += burst_write_len) {
 		uint8_t addr[2];
-		const int len = MIN(burst_write_len,
-				    g_bmi260_config_tbin_len - i);
+		const int len = MIN(burst_write_len, bmi_config_tbin_len - i);
 
 		addr[0] = (i / 2) & 0xF;
 		addr[1] = (i / 2) >> 4;
@@ -439,18 +466,18 @@ static int bmi_config_load(const struct motion_sensor_t *s)
 			 * init_rom region isn't memory mapped. Copy the
 			 * data through a RAM buffer.
 			 */
-			ret = init_rom_copy((int)&g_bmi260_config_tbin[i], len,
-				bmi_ram_buffer);
+			ret = init_rom_copy((int)&bmi_config_tbin[i], len,
+					    bmi_ram_buffer);
 			if (ret)
 				break;
 
 			ret = bmi_write_n(s->port, s->i2c_spi_addr_flags,
-					  BMI260_INIT_DATA,
-					  bmi_ram_buffer, len);
+					  BMI260_INIT_DATA, bmi_ram_buffer,
+					  len);
 		} else {
 			ret = bmi_write_n(s->port, s->i2c_spi_addr_flags,
-					  BMI260_INIT_DATA,
-					  &bmi_config[i], len);
+					  BMI260_INIT_DATA, &bmi_config[i],
+					  len);
 		}
 
 		if (ret)
@@ -462,7 +489,7 @@ static int bmi_config_load(const struct motion_sensor_t *s)
 	 * a non NULL value.
 	 */
 	if (bmi_config)
-		init_rom_unmap(g_bmi260_config_tbin, g_bmi260_config_tbin_len);
+		init_rom_unmap(bmi_config_tbin, bmi_config_tbin_len);
 
 	return ret;
 }
@@ -490,7 +517,7 @@ static int init_config(const struct motion_sensor_t *s)
 	for (i = 0; i < 15; ++i) {
 		msleep(10);
 		ret = bmi_read8(s->port, s->i2c_spi_addr_flags,
-			BMI260_INTERNAL_STATUS, &init_status);
+				BMI260_INTERNAL_STATUS, &init_status);
 		if (ret)
 			break;
 		init_status &= BMI260_MESSAGE_MASK;
@@ -502,32 +529,42 @@ static int init_config(const struct motion_sensor_t *s)
 	return EC_SUCCESS;
 }
 
-static int init(const struct motion_sensor_t *s)
+static int init(struct motion_sensor_t *s)
 {
 	int ret = 0, tmp, i;
 	struct accelgyro_saved_data_t *saved_data = BMI_GET_SAVED_DATA(s);
 
-	ret = bmi_read8(s->port, s->i2c_spi_addr_flags,
-			BMI260_CHIP_ID, &tmp);
+	ret = bmi_read8(s->port, s->i2c_spi_addr_flags, BMI260_CHIP_ID, &tmp);
 	if (ret)
 		return EC_ERROR_UNKNOWN;
 
-	if (tmp != BMI260_CHIP_ID_MAJOR)
+	switch (s->chip) {
+	case MOTIONSENSE_CHIP_BMI220:
+		if (tmp != BMI220_CHIP_ID_MAJOR)
+			return EC_ERROR_ACCESS_DENIED;
+		break;
+
+	case MOTIONSENSE_CHIP_BMI260:
+		if (tmp != BMI260_CHIP_ID_MAJOR)
+			return EC_ERROR_ACCESS_DENIED;
+		break;
+
+	default:
 		return EC_ERROR_ACCESS_DENIED;
+	}
 
 	if (s->type == MOTIONSENSE_TYPE_ACCEL) {
 		struct bmi_drv_data_t *data = BMI_GET_DATA(s);
 
 		/* Reset the chip to be in a good state */
-		bmi_write8(s->port, s->i2c_spi_addr_flags,
-				 BMI260_CMD_REG, BMI260_CMD_SOFT_RESET);
+		bmi_write8(s->port, s->i2c_spi_addr_flags, BMI260_CMD_REG,
+			   BMI260_CMD_SOFT_RESET);
 		msleep(2);
 		if (init_config(s))
 			return EC_ERROR_INVALID_CONFIG;
 
 		data->flags &= ~(BMI_FLAG_SEC_I2C_ENABLED |
-				(BMI_FIFO_ALL_MASK <<
-				 BMI_FIFO_FLAG_OFFSET));
+				 (BMI_FIFO_ALL_MASK << BMI_FIFO_FLAG_OFFSET));
 	}
 
 	for (i = X; i <= Z; i++)
@@ -537,13 +574,10 @@ static int init(const struct motion_sensor_t *s)
 	 * so set data rate to 0.
 	 */
 	saved_data->odr = 0;
-	bmi_set_range(s, s->default_range, 0);
 
-	if (s->type == MOTIONSENSE_TYPE_ACCEL) {
-#ifdef CONFIG_ACCEL_INTERRUPTS
+	if (IS_ENABLED(ACCELGYRO_BMI260_INT_ENABLE) &&
+	    (s->type == MOTIONSENSE_TYPE_ACCEL))
 		ret = config_interrupt(s);
-#endif
-	}
 
 	return sensor_init_done(s);
 }
@@ -552,7 +586,6 @@ const struct accelgyro_drv bmi260_drv = {
 	.init = init,
 	.read = bmi_read,
 	.set_range = bmi_set_range,
-	.get_range = bmi_get_range,
 	.get_resolution = bmi_get_resolution,
 	.set_data_rate = set_data_rate,
 	.get_data_rate = bmi_get_data_rate,
@@ -562,11 +595,14 @@ const struct accelgyro_drv bmi260_drv = {
 	.get_offset = bmi_get_offset,
 	.perform_calib = perform_calib,
 	.read_temp = bmi_read_temp,
-#ifdef CONFIG_ACCEL_INTERRUPTS
+#ifdef ACCELGYRO_BMI260_INT_ENABLE
 	.irq_handler = irq_handler,
 #endif
+#ifdef CONFIG_GESTURE_HOST_DETECTION
+	.list_activities = bmi_list_activities,
+#endif
 #ifdef CONFIG_BODY_DETECTION
-	.get_rms_noise = bmi_get_rms_noise,
+	.get_rms_noise = get_rms_noise,
 #endif
 };
 
diff --git a/driver/accelgyro_bmi260.h b/driver/accelgyro_bmi260.h
deleted file mode 100644
index 9c7edc0766..0000000000
--- a/driver/accelgyro_bmi260.h
+++ /dev/null
@@ -1,343 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* BMI260 accelerometer and gyro for Chrome EC */
-
-#ifndef __CROS_EC_ACCELGYRO_BMI260_H
-#define __CROS_EC_ACCELGYRO_BMI260_H
-
-#include "accelgyro.h"
-#include "common.h"
-#include "driver/mag_bmm150.h"
-
-/*
- * The addr field of motion_sensor support both SPI and I2C:
- * This is defined in include/i2c.h and is no longer an 8bit
- * address. The 7/10 bit address starts at bit 0 and leaves
- * room for a 10 bit address, although we don't currently
- * have any 10 bit slaves.  I2C or SPI is indicated by a
- * more significant bit
- */
-
-/* I2C addresses */
-#define BMI260_ADDR0_FLAGS	0x68
-
-#define BMI260_CHIP_ID      0x00
-#define BMI260_CHIP_ID_MAJOR    0x27
-
-#define BMI260_ERR_REG          0x02
-
-#define BMI260_STATUS           0x03
-#define BMI260_AUX_BUSY             BIT(2)
-#define BMI260_CMD_RDY              BIT(4)
-#define BMI260_DRDY_AUX             BIT(5)
-#define BMI260_DRDY_GYR             BIT(6)
-#define BMI260_DRDY_ACC             BIT(7)
-#define BMI260_DRDY_OFF(_sensor)    (7 - (_sensor))
-#define BMI260_DRDY_MASK(_sensor)   (1 << BMI260_DRDY_OFF(_sensor))
-
-#define BMI260_AUX_X_L_G           0x04
-#define BMI260_AUX_X_H_G           0x05
-#define BMI260_AUX_Y_L_G           0x06
-#define BMI260_AUX_Y_H_G           0x07
-#define BMI260_AUX_Z_L_G           0x08
-#define BMI260_AUX_Z_H_G           0x09
-#define BMI260_AUX_R_L_G           0x0a
-#define BMI260_AUX_R_H_G           0x0b
-#define BMI260_ACC_X_L_G           0x0c
-#define BMI260_ACC_X_H_G           0x0d
-#define BMI260_ACC_Y_L_G           0x0e
-#define BMI260_ACC_Y_H_G           0x0f
-#define BMI260_ACC_Z_L_G           0x10
-#define BMI260_ACC_Z_H_G           0x11
-#define BMI260_GYR_X_L_G           0x12
-#define BMI260_GYR_X_H_G           0x13
-#define BMI260_GYR_Y_L_G           0x14
-#define BMI260_GYR_Y_H_G           0x15
-#define BMI260_GYR_Z_L_G           0x16
-#define BMI260_GYR_Z_H_G           0x17
-
-#define BMI260_SENSORTIME_0     0x18
-#define BMI260_SENSORTIME_1     0x19
-#define BMI260_SENSORTIME_2     0x1a
-
-#define BMI260_EVENT            0x1b
-
-/* 2 bytes interrupt reasons*/
-#define BMI260_INT_STATUS_0     0x1c
-#define BMI260_SIG_MOTION_OUT       BIT(0)
-#define BMI260_STEP_COUNTER_OUT     BIT(1)
-#define BMI260_HIGH_LOW_G_OUT       BIT(2)
-#define BMI260_TAP_OUT              BIT(3)
-#define BMI260_FLAT_OUT             BIT(4)
-#define BMI260_NO_MOTION_OUT        BIT(5)
-#define BMI260_ANY_MOTION_OUT       BIT(6)
-#define BMI260_ORIENTATION_OUT      BIT(7)
-
-#define BMI260_INT_STATUS_1     0x1d
-#define BMI260_FFULL_INT            BIT(0 + 8)
-#define BMI260_FWM_INT              BIT(1 + 8)
-#define BMI260_ERR_INT              BIT(2 + 8)
-#define BMI260_AUX_DRDY_INT         BIT(5 + 8)
-#define BMI260_GYR_DRDY_INT         BIT(6 + 8)
-#define BMI260_ACC_DRDY_INT         BIT(7 + 8)
-
-#define BMI260_INT_MASK             0xFFFF
-
-#define BMI260_SC_OUT_0         0x1e
-#define BMI260_SC_OUT_1         0x1f
-
-#define BMI260_ORIENT_ACT       0x20
-
-#define BMI260_INTERNAL_STATUS  0X21
-#define BMI260_MESSAGE_MASK         0xf
-#define BMI260_NOT_INIT             0x00
-#define BMI260_INIT_OK              0x01
-#define BMI260_INIT_ERR             0x02
-#define BMI260_DRV_ERR              0x03
-#define BMI260_SNS_STOP             0x04
-#define BMI260_NVM_ERROR            0x05
-#define BMI260_START_UP_ERROR       0x06
-#define BMI260_COMPAT_ERROR         0x07
-
-#define BMI260_TEMPERATURE_0    0x22
-#define BMI260_TEMPERATURE_1    0x23
-
-#define BMI260_FIFO_LENGTH_0    0x24
-#define BMI260_FIFO_LENGTH_1    0x25
-#define BMI260_FIFO_LENGTH_MASK     (BIT(14) - 1)
-#define BMI260_FIFO_DATA        0x26
-
-#define BMI260_FEAT_PAGE        0x2f
-/*
- * The register of feature page should be read/write as 16-bit register
- * Otherwise, there can be invalid data
- */
-/* Features page 0 */
-#define BMI260_ORIENT_OUT       0x36
-#define BMI260_ORIENT_OUT_PORTRAIT_LANDSCAPE_MASK   3
-#define BMI260_ORIENT_PORTRAIT                      0x0
-#define BMI260_ORIENT_LANDSCAPE                     0x1
-#define BMI260_ORIENT_PORTRAIT_INVERT               0x2
-#define BMI260_ORIENT_LANDSCAPE_INVERT              0x3
-
-/* Features page 1 */
-#define BMI260_GEN_SET_1        0x34
-#define BMI260_GYR_SELF_OFF         BIT(9)
-
-#define BMI260_TAP_1            0x3e
-#define BMI260_TAP_1_EN                     BIT(0)
-#define BMI260_TAP_1_SENSITIVITY_OFFSET     1
-#define BMI260_TAP_1_SENSITIVITY_MASK       \
-	(0x7 << BMI260_TAP_1_SENSITIVITY_OFFSET)
-
-/* Features page 2 */
-#define BMI260_ORIENT_1         0x30
-#define BMI260_ORIENT_1_EN          BIT(0)
-#define BMI260_ORIENT_1_UD_EN       BIT(1)
-#define BMI260_ORIENT_1_MODE_OFFSET 2
-#define BMI260_ORIENT_1_MODE_MASK   (0x3 << BMI260_ORIENT_1_MODE_OFFSET)
-#define BMI260_ORIENT_1_BLOCK_OFFSET    4
-#define BMI260_ORIENT_1_BLOCK_MASK      (0x3 << BMI260_ORIENT_1_BLOCK_OFFSET)
-#define BMI260_ORIENT_1_THETA_OFFSET     6
-#define BMI260_ORIENT_1_THETA_MASK      \
-	((BIT(6) - 1) << BMI260_ORIENT_1_THETA_OFFSET)
-
-#define BMI260_ORIENT_2         0x32
-/* hysteresis(10...0) range is 0~1g, default is 128 (0.0625g) */
-#define BMI260_ORIENT_2_HYSTERESIS_MASK     (BIT(11) - 1)
-
-#define BMI260_ACC_CONF         0x40
-#define BMI260_ACC_BW_OFFSET        4
-#define BMI260_ACC_BW_MASK          (0x7 << BMI260_ACC_BW_OFFSET)
-#define BMI260_FILTER_PERF          BIT(7)
-#define BMI260_ULP                  0x0
-#define BMI260_HP                   0x1
-
-#define BMI260_ACC_RANGE        0x41
-#define BMI260_GSEL_2G              0x00
-#define BMI260_GSEL_4G              0x01
-#define BMI260_GSEL_8G              0x02
-#define BMI260_GSEL_16G             0x03
-
-/* The max positvie value of accel data is 0x7FFF, equal to range(g) */
-/* So, in order to get +1g, divide the 0x7FFF by range */
-#define BMI260_ACC_DATA_PLUS_1G(range) (0x7FFF / (range))
-#define BMI260_ACC_DATA_MINUS_1G(range) (-BMI260_ACC_DATA_PLUS_1G(range))
-
-#define BMI260_GYR_CONF         0x42
-#define BMI260_GYR_BW_OFFSET        4
-#define BMI260_GYR_BW_MASK          (0x3 << BMI260_GYR_BW_OFFSET)
-#define BMI260_GYR_NOISE_PERF       BIT(6)
-
-#define BMI260_GYR_RANGE        0x43
-#define BMI260_DPS_SEL_2000         0x00
-#define BMI260_DPS_SEL_1000         0x01
-#define BMI260_DPS_SEL_500          0x02
-#define BMI260_DPS_SEL_250          0x03
-#define BMI260_DPS_SEL_125          0x04
-
-#define BMI260_AUX_CONF         0x44
-
-#define BMI260_FIFO_DOWNS       0x45
-
-#define BMI260_FIFO_WTM_0       0x46
-#define BMI260_FIFO_WTM_1       0x47
-
-#define BMI260_FIFO_CONFIG_0    0x48
-#define BMI260_FIFO_STOP_ON_FULL    BIT(0)
-#define BMI260_FIFO_TIME_EN     BIT(1)
-
-#define BMI260_FIFO_CONFIG_1    0x49
-#define BMI260_FIFO_TAG_INT1_EN_OFFSET  0
-#define BMI260_FIFO_TAG_INT1_EN_MASK    (0x3 << BMI260_FIFO_TAG_INT1_EN_OFFSET)
-#define BMI260_FIFO_TAG_INT2_EN_OFFSET  2
-#define BMI260_FIFO_TAG_INT2_EN_MASK    (0x3 << BMI260_FIFO_TAG_INT2_EN_OFFSET)
-#define BMI260_FIFO_TAG_INT_EDGE        0x0
-#define BMI260_FIFO_TAG_INT_LEVEL       0x1
-#define BMI260_FIFO_TAG_ACC_SAT         0x2
-#define BMI260_FIFO_TAG_GYR_SAT         0x3
-#define BMI260_FIFO_HEADER_EN           BIT(4)
-#define BMI260_FIFO_AUX_EN              BIT(5)
-#define BMI260_FIFO_ACC_EN              BIT(6)
-#define BMI260_FIFO_GYR_EN              BIT(7)
-#define BMI260_FIFO_SENSOR_EN(_sensor) \
-	((_sensor) == MOTIONSENSE_TYPE_ACCEL ? BMI260_FIFO_ACC_EN : \
-	  ((_sensor) == MOTIONSENSE_TYPE_GYRO ? BMI260_FIFO_GYR_EN : \
-	   BMI260_FIFO_AUX_EN))
-
-#define BMI260_AUX_DEV_ID       0x4b
-#define BMI260_AUX_I2C_ADDRESS          BMI260_AUX_DEV_ID
-
-#define BMI260_AUX_IF_CONF      0x4c
-#define BMI260_AUX_I2C_CONTROL          BMI260_AUX_IF_CONF
-#define BMI260_AUX_READ_BURST_MASK      3
-#define BMI260_AUX_MAN_READ_BURST_OFF   2
-#define BMI260_AUX_MAN_READ_BURST_MASK  (0x3 << BMI280_AUX_MAN_READ_BURST_OFF)
-#define BMI260_AUX_READ_BURST_1         0
-#define BMI260_AUX_READ_BURST_2         1
-#define BMI260_AUX_READ_BURST_6         2
-#define BMI260_AUX_READ_BURST_8         3
-#define BMI260_AUX_FCU_WRITE_EN         BIT(6)
-#define BMI260_AUX_MANUAL_EN            BIT(7)
-
-#define BMI260_AUX_RD_ADDR      0x4d
-#define BMI260_AUX_I2C_READ_ADDR    BMI260_AUX_RD_ADDR
-#define BMI260_AUX_WR_ADDR      0x4e
-#define BMI260_AUX_I2C_WRITE_ADDR   BMI260_AUX_WR_ADDR
-#define BMI260_AUX_WR_DATA      0x4f
-#define BMI260_AUX_I2C_WRITE_DATA   BMI260_AUX_WR_DATA
-#define BMI260_AUX_I2C_READ_DATA    BMI260_AUX_X_L_G
-
-#define BMI260_ERR_REG_MSK      0x52
-#define BMI260_FATAL_ERR            BIT(0)
-#define BMI260_INTERNAL_ERR_OFF     1
-#define BMI260_INTERNAL_ERR_MASK    (0xf << BMI260_INTERNAL_ERR_OFF)
-#define BMI260_FIFO_ERR             BIT(6)
-#define BMI260_AUX_ERR              BIT(7)
-
-#define BMI260_INT1_IO_CTRL     0x53
-#define BMI260_INT1_LVL             BIT(1)
-#define BMI260_INT1_OD              BIT(2)
-#define BMI260_INT1_OUTPUT_EN       BIT(3)
-#define BMI260_INT1_INPUT_EN        BIT(4)
-
-#define BMI260_INT2_IO_CTRL     0x54
-#define BMI260_INT2_LVL             BIT(1)
-#define BMI260_INT2_OD              BIT(2)
-#define BMI260_INT2_OUTPUT_EN       BIT(3)
-#define BMI260_INT2_INPUT_EN        BIT(4)
-
-#define BMI260_INT_LATCH        0x55
-#define BMI260_INT_LATCH_EN         BIT(0)
-
-#define BMI260_INT1_MAP_FEAT    0x56
-#define BMI260_INT2_MAP_FEAT    0x57
-#define BMI260_MAP_SIG_MOTION_OUT   BIT(0)
-#define BMI260_MAP_STEP_COUNTER_OUT BIT(1)
-#define BMI260_MAP_HIGH_LOW_G_OUT   BIT(2)
-#define BMI260_MAP_TAP_OUT          BIT(3)
-#define BMI260_MAP_FLAT_OUT         BIT(4)
-#define BMI260_MAP_NO_MOTION_OUT    BIT(5)
-#define BMI260_MAP_ANY_MOTION_OUT   BIT(6)
-#define BMI260_MAP_ORIENTAION_OUT   BIT(7)
-
-#define BMI260_INT_MAP_DATA     0x58
-#define BMI260_MAP_FFULL_INT        BIT(0)
-#define BMI260_MAP_FWM_INT          BIT(1)
-#define BMI260_MAP_DRDY_INT         BIT(2)
-#define BMI260_MAP_ERR_INT          BIT(3)
-#define BMI260_INT_MAP_DATA_INT1_OFFSET     0
-#define BMI260_INT_MAP_DATA_INT2_OFFSET     4
-#define BMI260_INT_MAP_DATA_REG(_i, _bit) \
-	(CONCAT3(BMI260_MAP_, _bit, _INT) << \
-	CONCAT3(BMI260_INT_MAP_DATA_INT, _i, _OFFSET))
-
-#define BMI260_INIT_CTRL        0x59
-#define BMI260_INIT_ADDR_0      0x5b
-#define BMI260_INIT_ADDR_1      0x5c
-#define BMI260_INIT_DATA        0x5e
-#define BMI260_INTERNAL_ERROR   0x5f
-#define BMI260_INT_ERR_1            BIT(1)
-#define BMI260_INT_ERR_2            BIT(2)
-#define BMI260_FEAT_ENG_DISABLED    BIT(4)
-
-#define BMI260_AUX_IF_TRIM      0x68
-#define BMI260_GYR_CRT_CONF     0x69
-
-#define BMI260_NVM_CONF         0x6a
-#define BMI260_NVM_PROG_EN          BIT(1)
-
-#define BMI260_IF_CONF          0x6b
-#define BMI260_IF_SPI3              BIT(0)
-#define BMI260_IF_SPI3_OIS          BIT(1)
-#define BMI260_IF_OIS_EN            BIT(4)
-#define BMI260_IF_AUX_EN            BIT(5)
-
-#define BMI260_DRV              0x6c
-#define BMI260_ACC_SELF_TEST    0x6d
-
-#define BMI260_NV_CONF          0x70
-#define BMI260_ACC_OFFSET_EN        BIT(3)
-
-#define BMI260_OFFSET_ACC70     0x71
-#define BMI260_OFFSET_GYR70     0x74
-#define BMI260_OFFSET_EN_GYR98  0x77
-#define BMI260_OFFSET_GYRO_EN       BIT(6)
-#define BMI260_GYR_GAIN_EN          BIT(7)
-
-#define BMI260_PWR_CONF         0x7c
-#define BMI260_ADV_POWER_SAVE       BIT(0)
-#define BMI260_FIFO_SELF_WAKE_UP    BIT(1)
-#define BMI260_FUP_EN               BIT(2)
-
-#define BMI260_PWR_CTRL         0x7d
-#define BMI260_AUX_EN               BIT(0)
-#define BMI260_GYR_EN               BIT(1)
-#define BMI260_ACC_EN               BIT(2)
-#define BMI260_PWR_EN(_sensor_type) BIT(2 - _sensor_type)
-#define BMI260_TEMP_EN              BIT(3)
-
-#define BMI260_CMD_REG          0x7e
-#define BMI260_CMD_FIFO_FLUSH       0xb0
-#define BMI260_CMD_SOFT_RESET       0xb6
-
-#define BMI260_FF_FRAME_LEN_TS          4
-#define BMI260_FF_DATA_LEN_ACC          6
-#define BMI260_FF_DATA_LEN_GYR          6
-#define BMI260_FF_DATA_LEN_MAG          8
-
-/* Root mean square noise of 100Hz accelerometer, units: ug */
-#define BMI260_ACCEL_RMS_NOISE_100HZ    1060
-
-extern const struct accelgyro_drv bmi260_drv;
-
-void bmi260_interrupt(enum gpio_signal signal);
-
-#ifdef CONFIG_CMD_I2C_STRESS_TEST_ACCEL
-extern struct i2c_stress_test_dev bmi260_i2c_stress_test_dev;
-#endif
-
-#endif /* __CROS_EC_ACCELGYRO_BMI260_H */
diff --git a/driver/accelgyro_bmi323.h b/driver/accelgyro_bmi323.h
new file mode 100644
index 0000000000..9b014448bd
--- /dev/null
+++ b/driver/accelgyro_bmi323.h
@@ -0,0 +1,15 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* BMI323 gsensor module for Chrome EC */
+
+#ifndef __CROS_EC_ACCELGYRO_BMI323_H
+#define __CROS_EC_ACCELGYRO_BMI323_H
+
+#include "accelgyro_bmi3xx.h"
+
+#define BMI323_CHIP_ID 0x43
+
+#endif /* __CROS_EC_ACCELGYRO_BMI323_H */
diff --git a/driver/accelgyro_bmi3xx.c b/driver/accelgyro_bmi3xx.c
new file mode 100644
index 0000000000..f2326c9631
--- /dev/null
+++ b/driver/accelgyro_bmi3xx.c
@@ -0,0 +1,1069 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * BMI3XX accelerometer and gyroscope module for Chrome EC
+ * 3D digital accelerometer & 3D digital gyroscope
+ */
+
+#include "accelgyro.h"
+#include "accelgyro_bmi323.h"
+#include "accelgyro_bmi_common.h"
+#include "builtin/assert.h"
+#include "console.h"
+#include "hwtimer.h"
+#include "i2c.h"
+#include "init_rom.h"
+#include "math_util.h"
+#include "motion_sense_fifo.h"
+#include "spi.h"
+#include "task.h"
+#include "timer.h"
+#include "util.h"
+#include "watchdog.h"
+
+#ifdef CONFIG_ACCELGYRO_BMI3XX_INT_EVENT
+#define ACCELGYRO_BMI3XX_INT_ENABLE
+#endif
+
+#define CPUTS(outstr) cputs(CC_ACCEL, outstr)
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args)
+
+#define OFFSET_UPDATE_PER_TRY 10
+
+/* Sensor definition */
+STATIC_IF(CONFIG_BMI_ORIENTATION_SENSOR)
+void irq_set_orientation(struct motion_sensor_t *s);
+
+STATIC_IF(ACCELGYRO_BMI3XX_INT_ENABLE)
+volatile uint32_t last_interrupt_timestamp;
+
+static inline int bmi3_read_n(const struct motion_sensor_t *s, const int reg,
+			      uint8_t *data_ptr, const int len)
+{
+	return bmi_read_n(s->port, s->i2c_spi_addr_flags, reg, data_ptr, len);
+}
+
+static inline int bmi3_write_n(const struct motion_sensor_t *s, const int reg,
+			       uint8_t *data_ptr, const int len)
+{
+	return bmi_write_n(s->port, s->i2c_spi_addr_flags, reg, data_ptr, len);
+}
+
+#ifdef ACCELGYRO_BMI3XX_INT_ENABLE
+
+#ifdef CONFIG_BMI_ORIENTATION_SENSOR
+
+static void irq_set_orientation(struct motion_sensor_t *s)
+{
+	int ret;
+	uint8_t reg_data[4];
+	uint8_t orient_data;
+
+	enum motionsensor_orientation orientation =
+		MOTIONSENSE_ORIENTATION_UNKNOWN;
+
+	RETURN_ERROR(bmi3_read_n(s, BMI3_FEATURE_EVENT_EXT, reg_data, 4));
+
+	orient_data = reg_data[2] & BMI3_PORTRAIT_LANDSCAPE_MASK;
+
+	if (BMI_GET_DATA(s)->raw_orientation != orient_data) {
+		BMI_GET_DATA(s)->raw_orientation = orient_data;
+
+		switch (orient_data) {
+		case BMI3_ORIENT_PORTRAIT:
+			orientation = MOTIONSENSE_ORIENTATION_PORTRAIT;
+			break;
+		case BMI3_PORTRAIT_INVERT:
+			orientation =
+				MOTIONSENSE_ORIENTATION_UPSIDE_DOWN_PORTRAIT;
+			break;
+		case BMI3_LANDSCAPE:
+			orientation = MOTIONSENSE_ORIENTATION_LANDSCAPE;
+			break;
+		case BMI3_LANDSCAPE_INVERT:
+			orientation =
+				MOTIONSENSE_ORIENTATION_UPSIDE_DOWN_LANDSCAPE;
+			break;
+		default:
+			break;
+		}
+
+		orientation = motion_orientation_remap(s, orientation);
+		*motion_orientation_ptr(s) = orientation;
+	}
+}
+
+#endif /* CONFIG_BMI_ORIENTATION_SENSOR */
+
+/*
+ * bmi3xx_interrupt - called when the sensor activates the interrupt line.
+ *
+ * This is a "top half" interrupt handler, it just asks motion sense ask
+ * to schedule the "bottom half", ->irq_handler().
+ */
+void bmi3xx_interrupt(enum gpio_signal signal)
+{
+	last_interrupt_timestamp = __hw_clock_source_read();
+
+	task_set_event(TASK_ID_MOTIONSENSE, CONFIG_ACCELGYRO_BMI3XX_INT_EVENT);
+}
+
+static int enable_fifo(const struct motion_sensor_t *s, int enable)
+{
+	struct bmi_drv_data_t *data = BMI_GET_DATA(s);
+	/* Set FIFO config to enable accel gyro data */
+	uint8_t reg_data[4];
+
+	RETURN_ERROR(bmi3_read_n(s, BMI3_REG_FIFO_CONF, reg_data, 4));
+
+	if (enable) {
+		if (s->type == MOTIONSENSE_TYPE_ACCEL)
+			reg_data[3] |= BMI3_FIFO_ACC_EN;
+		else
+			reg_data[3] |= BMI3_FIFO_GYR_EN;
+
+		data->flags |= 1 << (s->type + BMI_FIFO_FLAG_OFFSET);
+	} else {
+		if (s->type == MOTIONSENSE_TYPE_ACCEL)
+			reg_data[3] &= ~BMI3_FIFO_ACC_EN;
+		else
+			reg_data[3] &= ~BMI3_FIFO_GYR_EN;
+
+		data->flags &= ~(1 << (s->type + BMI_FIFO_FLAG_OFFSET));
+	}
+
+	return bmi3_write_n(s, BMI3_REG_FIFO_CONF, &reg_data[2], 2);
+}
+
+static int config_interrupt(const struct motion_sensor_t *s)
+{
+	int ret;
+	uint8_t reg_data[6] = { 0 };
+
+	if (s->type != MOTIONSENSE_TYPE_ACCEL)
+		return EC_SUCCESS;
+
+	mutex_lock(s->mutex);
+
+	/* Clear the FIFO using Flush command */
+	reg_data[0] = BMI3_ENABLE;
+	reg_data[1] = 0;
+	ret = bmi3_write_n(s, BMI3_REG_FIFO_CTRL, reg_data, 2);
+	if (ret)
+		goto err_unlock;
+
+	/* Map FIFO water-mark and FIFO full to INT1 pin */
+	ret = bmi3_read_n(s, BMI3_REG_INT_MAP1, reg_data, 6);
+	if (ret)
+		goto err_unlock;
+
+	reg_data[5] = BMI3_SET_BITS(reg_data[5], BMI3_FWM_INT, BMI3_INT1);
+	reg_data[5] = BMI3_SET_BITS(reg_data[5], BMI3_FFULL_INT, BMI3_INT1);
+	if (IS_ENABLED(CONFIG_BMI_ORIENTATION_SENSOR)) {
+		/* Map orientation to INT1 pin */
+		reg_data[2] =
+			BMI3_SET_BITS(reg_data[2], BMI3_ORIENT_INT, BMI3_INT1);
+	}
+
+	ret = bmi3_write_n(s, BMI3_REG_INT_MAP1, &reg_data[2], 4);
+	if (ret)
+		goto err_unlock;
+
+	/* Set FIFO water-mark to read data whenever available */
+	reg_data[0] = BMI3_FIFO_ENTRY;
+	reg_data[1] = 0;
+
+	ret = bmi3_write_n(s, BMI3_REG_FIFO_WATERMARK, reg_data, 2);
+	if (ret)
+		goto err_unlock;
+
+	/* Get the previous configuration data */
+	ret = bmi3_read_n(s, BMI3_REG_IO_INT_CTRL, reg_data, 4);
+	if (ret)
+		goto err_unlock;
+
+	reg_data[2] = BMI3_SET_BIT_POS0(reg_data[2], BMI3_INT1_LVL,
+					BMI3_INT_ACTIVE_LOW);
+
+	reg_data[2] =
+		BMI3_SET_BITS(reg_data[2], BMI3_INT1_OD, BMI3_INT_PUSH_PULL);
+
+	reg_data[2] = BMI3_SET_BITS(reg_data[2], BMI3_INT1_OUTPUT_EN,
+				    BMI3_INT_OUTPUT_ENABLE);
+
+	/*
+	 * Set the interrupt pin configurations
+	 */
+	ret = bmi3_write_n(s, BMI3_REG_IO_INT_CTRL, &reg_data[2], 2);
+	if (ret)
+		goto err_unlock;
+
+	if (IS_ENABLED(CONFIG_BMI_ORIENTATION_SENSOR)) {
+		/* Enable the orientation feature in BMI3 */
+		ret = bmi3_read_n(s, BMI3_FEATURE_IO_0, reg_data, 4);
+		if (ret)
+			goto err_unlock;
+
+		reg_data[2] |= BMI3_ANY_MOTION_X_EN_MASK;
+		ret = bmi3_write_n(s, BMI3_FEATURE_IO_0, &reg_data[2], 2);
+		if (ret)
+			goto err_unlock;
+
+		/* Write to feature engine */
+		reg_data[0] = 1;
+		reg_data[1] = 0;
+		ret = bmi3_write_n(s, BMI3_FEATURE_IO_STATUS, reg_data, 2);
+	}
+
+err_unlock:
+	mutex_unlock(s->mutex);
+	return ret;
+}
+
+static void bmi3_parse_fifo_data(struct motion_sensor_t *s,
+				 struct bmi3_fifo_frame *fifo_frame,
+				 uint32_t last_ts)
+{
+	struct bmi_drv_data_t *data = BMI_GET_DATA(s);
+	uint16_t reg_data;
+	int i;
+
+	/* Start index for FIFO parsing after I2C sync word removal */
+	size_t fifo_index = 1;
+
+	/* Variable to store I2C sync data which will get in FIFO data */
+	uint16_t i2c_sync_data, fifo_size;
+
+	if (!(data->flags & (BMI_FIFO_ALL_MASK << BMI_FIFO_FLAG_OFFSET))) {
+		/*
+		 * The FIFO was disabled while we were processing it
+		 * Flush potential left over:
+		 * When sensor is resumed, we won't read old data.
+		 */
+
+		/* Clear the FIFO using Flush command */
+		reg_data = BMI3_ENABLE;
+		bmi3_write_n(s, BMI3_REG_FIFO_CTRL, (uint8_t *)&reg_data, 2);
+		return;
+	}
+
+	/* Parse the length of data read excluding I2C sync word */
+	fifo_size = fifo_frame->available_fifo_len - 1;
+
+	while (fifo_size > 0) {
+		for (i = 0; i < NUM_OF_PRIMARY_SENSOR; i++) {
+			struct motion_sensor_t *sens_output = s + i;
+			int *v = sens_output->raw_xyz;
+
+			if (data->flags & BIT(i + BMI_FIFO_FLAG_OFFSET)) {
+				/*
+				 * In-case of FIFO read fail it has only
+				 * 0x8000.
+				 */
+				if (fifo_frame->data[fifo_index] == 0x8000)
+					return;
+
+				/*
+				 * In case the frame has been cut, FIFO was
+				 * greater than our buffer.
+				 * When a frame is only partially read out, it
+				 * is retransmitted at the next readout.
+				 * No need to process it here.
+				 */
+				if (fifo_size < BMI3_FIFO_ENTRY)
+					return;
+
+				/* Frame is complete, but may have no data. */
+				fifo_size -= BMI3_FIFO_ENTRY;
+				i2c_sync_data = fifo_frame->data[fifo_index++];
+				if (i2c_sync_data ==
+				    BMI3_FIFO_ACCEL_I2C_SYNC_FRAME + i) {
+					fifo_index += 2;
+					continue;
+				}
+
+				v[X] = i2c_sync_data;
+				v[Y] = fifo_frame->data[fifo_index++];
+				v[Z] = fifo_frame->data[fifo_index++];
+
+				rotate(v, *sens_output->rot_standard_ref, v);
+
+				if (IS_ENABLED(CONFIG_ACCEL_SPOOF_MODE) &&
+				    s->flags & MOTIONSENSE_FLAG_IN_SPOOF_MODE)
+					v = sens_output->spoof_xyz;
+				if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
+					struct ec_response_motion_sensor_data
+						vect;
+
+					vect.data[X] = v[X];
+					vect.data[Y] = v[Y];
+					vect.data[Z] = v[Z];
+					vect.flags = 0;
+					vect.sensor_num =
+						sens_output - motion_sensors;
+					motion_sense_fifo_stage_data(
+						&vect, sens_output, 3, last_ts);
+				} else {
+					motion_sense_push_raw_xyz(sens_output);
+				}
+			}
+		}
+	}
+}
+
+/*
+ * irq_handler - bottom half of the interrupt stack.
+ * Ran from the motion_sense task, finds the events that raised the interrupt.
+ *
+ * For now, we just print out. We should set a bitmask motion sense code will
+ * act upon.
+ */
+static int irq_handler(struct motion_sensor_t *s, uint32_t *event)
+{
+	bool has_read_fifo = false;
+	uint16_t int_status[2];
+	uint16_t reg_data[2];
+	struct bmi3_fifo_frame fifo_frame;
+
+	if ((s->type != MOTIONSENSE_TYPE_ACCEL) ||
+	    (!(*event & CONFIG_ACCELGYRO_BMI3XX_INT_EVENT)))
+		return EC_ERROR_NOT_HANDLED;
+
+	/* Get the interrupt status */
+	do {
+		RETURN_ERROR(bmi3_read_n(s, BMI3_REG_INT_STATUS_INT1,
+					 (uint8_t *)int_status, 4));
+
+		if (IS_ENABLED(CONFIG_BMI_ORIENTATION_SENSOR) &&
+		    (BMI3_INT_STATUS_ORIENTATION & int_status[1]))
+			irq_set_orientation(s);
+
+		if ((int_status[1] &
+		     (BMI3_INT_STATUS_FWM | BMI3_INT_STATUS_FFULL)) == 0)
+			break;
+
+		/* Get the FIFO fill level in words */
+		RETURN_ERROR(bmi3_read_n(s, BMI3_REG_FIFO_FILL_LVL,
+					 (uint8_t *)reg_data, 4));
+
+		reg_data[1] =
+			BMI3_GET_BIT_POS0(reg_data[1], BMI3_FIFO_FILL_LVL);
+
+		/* Add space for the initial 16bit read. */
+		fifo_frame.available_fifo_len = reg_data[1] + 1;
+
+		/*
+		 * If fill level is greater than buffer size then wrap it to
+		 * buffer size.
+		 */
+		if (fifo_frame.available_fifo_len > ARRAY_SIZE(fifo_frame.data))
+			CPRINTS("unexpected large FIFO: %d",
+				fifo_frame.available_fifo_len);
+
+		fifo_frame.available_fifo_len =
+			MIN(fifo_frame.available_fifo_len,
+			    ARRAY_SIZE(fifo_frame.data));
+		/* Read FIFO data */
+		RETURN_ERROR(bmi3_read_n(
+			s, BMI3_REG_FIFO_DATA, (uint8_t *)fifo_frame.data,
+			fifo_frame.available_fifo_len * sizeof(uint16_t)));
+
+		bmi3_parse_fifo_data(s, &fifo_frame, last_interrupt_timestamp);
+		has_read_fifo = true;
+	} while (true);
+
+	if (IS_ENABLED(CONFIG_ACCEL_FIFO) && has_read_fifo)
+		motion_sense_fifo_commit_data();
+
+	return EC_SUCCESS;
+}
+#endif /* ACCELGYRO_BMI3XX_INT_ENABLE */
+
+static int read_temp(const struct motion_sensor_t *s, int *temp_ptr)
+{
+	return EC_ERROR_UNIMPLEMENTED;
+}
+
+int get_gyro_offset(const struct motion_sensor_t *s, intv3_t v)
+{
+	int i;
+	uint8_t reg_data[14] = { 0 };
+
+	/* Get the accel offset values */
+	RETURN_ERROR(bmi3_read_n(s, BMI3_GYR_DP_OFF_X, reg_data, 14));
+
+	v[0] = ((uint16_t)(reg_data[3] << 8) | reg_data[2]) & 0x03FF;
+	v[1] = ((uint16_t)(reg_data[7] << 8) | reg_data[6]) & 0x03FF;
+	v[2] = ((uint16_t)(reg_data[11] << 8) | reg_data[10]) & 0x03FF;
+
+	for (i = X; i <= Z; ++i) {
+		if (v[i] > 0x01FF)
+			v[i] = -1024 + v[i];
+
+		v[i] = round_divide((int64_t)v[i] * BMI_OFFSET_GYRO_MULTI_MDS,
+				    BMI_OFFSET_GYRO_DIV_MDS);
+	}
+
+	return EC_SUCCESS;
+}
+
+static int write_gyro_offset(const struct motion_sensor_t *s, int *val)
+{
+	uint8_t reg_data[6] = { 0 };
+
+	/* x-axis offset */
+	reg_data[0] = (uint8_t)(val[0] & BMI3_SET_LOW_BYTE);
+	reg_data[1] = (uint8_t)((val[0] & 0x0300) >> 8);
+	/* y-axis offset */
+	reg_data[2] = (uint8_t)(val[1] & BMI3_SET_LOW_BYTE);
+	reg_data[3] = (uint8_t)((val[1] & 0x0300) >> 8);
+	/* z-axis offset */
+	reg_data[4] = (uint8_t)(val[2] & BMI3_SET_LOW_BYTE);
+	reg_data[5] = (uint8_t)((val[2] & 0x0300) >> 8);
+
+	/* Update the gyro data path offset registers */
+	RETURN_ERROR(bmi3_write_n(s, BMI3_GYR_DP_OFF_X, &reg_data[0], 2));
+	RETURN_ERROR(bmi3_write_n(s, BMI3_GYR_DP_OFF_Y, &reg_data[2], 2));
+	RETURN_ERROR(bmi3_write_n(s, BMI3_GYR_DP_OFF_Z, &reg_data[4], 2));
+
+	return EC_SUCCESS;
+}
+
+int set_gyro_offset(const struct motion_sensor_t *s, intv3_t v)
+{
+	uint8_t reg_data[4] = { 0 };
+	uint8_t saved_conf[6] = { 0 };
+	int i, val[3];
+
+	for (i = X; i <= Z; ++i) {
+		val[i] = round_divide((int64_t)v[i] * BMI_OFFSET_GYRO_DIV_MDS,
+				      BMI3_OFFSET_GYR_MDPS);
+		if (val[i] > 511)
+			val[i] = 511;
+		if (val[i] < -512)
+			val[i] = -512;
+		if (val[i] < 0)
+			val[i] = 1024 + val[i];
+	}
+
+	/* Set the power mode as suspend */
+	RETURN_ERROR(bmi3_read_n(s, BMI3_REG_ACC_CONF, saved_conf, 6));
+
+	/* Disable accelerometer and gyroscope */
+	reg_data[0] = saved_conf[2];
+	reg_data[1] = 0x00;
+	reg_data[2] = saved_conf[4];
+	reg_data[3] = 0x00;
+	RETURN_ERROR(bmi3_write_n(s, BMI3_REG_ACC_CONF, reg_data, 4));
+
+	/* Set the gyro offset in the sensor registers */
+	RETURN_ERROR(write_gyro_offset(s, val));
+
+	/* Restore ACC_CONF by storing saved_conf data */
+	RETURN_ERROR(bmi3_write_n(s, BMI3_REG_ACC_CONF, &saved_conf[2], 4));
+
+	return EC_SUCCESS;
+}
+
+int get_accel_offset(const struct motion_sensor_t *s, intv3_t v)
+{
+	int i;
+	uint8_t reg_data[14] = { 0 };
+
+	/* Get the accel offset values from user registers */
+	RETURN_ERROR(bmi3_read_n(s, BMI3_ACC_DP_OFF_X, reg_data, 14));
+
+	v[0] = ((uint16_t)(reg_data[3] << 8) | reg_data[2]) & 0x3FFF;
+	v[1] = ((uint16_t)(reg_data[7] << 8) | reg_data[6]) & 0x3FFF;
+	v[2] = ((uint16_t)(reg_data[11] << 8) | reg_data[10]) & 0x3FFF;
+
+	for (i = X; i <= Z; ++i) {
+		if (v[i] > 0x1FFF)
+			v[i] = -16384 + v[i];
+
+		v[i] = round_divide((int64_t)v[i] * BMI3_OFFSET_ACC_MULTI_MG,
+				    BMI_OFFSET_ACC_DIV_MG);
+	}
+
+	return EC_SUCCESS;
+}
+
+static int write_accel_offsets(const struct motion_sensor_t *s, int *val)
+{
+	uint8_t reg_data[6] = { 0 };
+
+	/* x-axis offset */
+	reg_data[0] = (uint8_t)(val[0] & BMI3_SET_LOW_BYTE);
+	reg_data[1] = (uint8_t)((val[0] & 0x3F00) >> 8);
+	/* y-axis offset */
+	reg_data[2] = (uint8_t)(val[1] & BMI3_SET_LOW_BYTE);
+	reg_data[3] = (uint8_t)((val[1] & 0x3F00) >> 8);
+	/* z-axis offset */
+	reg_data[4] = (uint8_t)(val[2] & BMI3_SET_LOW_BYTE);
+	reg_data[5] = (uint8_t)((val[2] & 0x3F00) >> 8);
+
+	/* Update the acc data path offset registers */
+	RETURN_ERROR(bmi3_write_n(s, BMI3_ACC_DP_OFF_X, &reg_data[0], 2));
+	RETURN_ERROR(bmi3_write_n(s, BMI3_ACC_DP_OFF_Y, &reg_data[2], 2));
+	RETURN_ERROR(bmi3_write_n(s, BMI3_ACC_DP_OFF_Z, &reg_data[4], 2));
+
+	return EC_SUCCESS;
+}
+
+int set_accel_offset(const struct motion_sensor_t *s, intv3_t v)
+{
+	uint8_t reg_data[4] = { 0 };
+	uint8_t saved_conf[6] = { 0 };
+	int i, val[3];
+
+	for (i = X; i <= Z; ++i) {
+		val[i] = round_divide((int64_t)v[i] * BMI_OFFSET_ACC_DIV_MG,
+				      BMI3_OFFSET_ACC_MULTI_MG);
+		if (val[i] > 8191)
+			val[i] = 8191;
+		if (val[i] < -8192)
+			val[i] = -8192;
+		if (val[i] < 0)
+			val[i] += 16384;
+	}
+
+	/* Set the power mode as suspend */
+	RETURN_ERROR(bmi3_read_n(s, BMI3_REG_ACC_CONF, saved_conf, 6));
+
+	/* Disable accelerometer and gyroscope */
+	reg_data[0] = saved_conf[2];
+	reg_data[1] = 0x00;
+	reg_data[2] = saved_conf[4];
+	reg_data[3] = 0x00;
+	RETURN_ERROR(bmi3_write_n(s, BMI3_REG_ACC_CONF, reg_data, 4));
+
+	/* Set the accel offset in the sensor registers */
+	RETURN_ERROR(write_accel_offsets(s, val));
+
+	/* Restore ACC_CONF by storing saved_conf data */
+	RETURN_ERROR(bmi3_write_n(s, BMI3_REG_ACC_CONF, &saved_conf[2], 4));
+
+	return EC_SUCCESS;
+}
+
+static int set_gyro_foc_config(struct motion_sensor_t *s)
+{
+	uint8_t reg_data[4] = { 0 };
+	uint8_t base_addr[2] = { BMI3_BASE_ADDR_SC, 0 };
+
+	/*
+	 * Set the FOC base address to feature engine
+	 * transmission address to start DMA transaction
+	 */
+	RETURN_ERROR(bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX, base_addr, 2));
+
+	/* Read the configuration from the feature engine register */
+	RETURN_ERROR(
+		bmi3_read_n(s, BMI3_FEATURE_ENGINE_DMA_TX_DATA, reg_data, 4));
+	/* Enable self calibration */
+	reg_data[2] |= 0x07;
+
+	RETURN_ERROR(bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX, base_addr, 2));
+
+	/* Set the configuration to the feature engine register */
+	RETURN_ERROR(bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX_DATA,
+				  &reg_data[2], 2));
+
+	/* Trigger bmi3 gyro self calibration */
+	reg_data[0] = (uint8_t)(BMI3_CMD_SELF_CALIB & BMI3_SET_LOW_BYTE);
+	reg_data[1] =
+		(uint8_t)((BMI3_CMD_SELF_CALIB & BMI3_SET_HIGH_BYTE) >> 8);
+
+	RETURN_ERROR(bmi3_write_n(s, BMI3_REG_CMD, reg_data, 2));
+
+	return EC_SUCCESS;
+}
+
+static int get_calib_result(struct motion_sensor_t *s)
+{
+	uint8_t i, reg_data[4];
+
+	for (i = 0; i < 25; i++) {
+		/* A delay of 120ms is required to read this status register */
+		msleep(OFFSET_UPDATE_DELAY);
+
+		/* Read the configuration from the feature engine register */
+		RETURN_ERROR(bmi3_read_n(s, BMI3_FEATURE_IO_1, reg_data, 4));
+
+		switch (s->type) {
+		case MOTIONSENSE_TYPE_GYRO:
+			if (reg_data[2] & BMI3_SC_ST_STATUS_MASK) {
+				/* Check calibration result */
+				if (reg_data[2] & BMI3_SC_RESULT_MASK)
+					return EC_SUCCESS;
+			}
+			break;
+		default:
+			return EC_ERROR_UNIMPLEMENTED;
+		}
+	}
+
+	return EC_ERROR_NOT_CALIBRATED;
+}
+
+static int perform_calib(struct motion_sensor_t *s, int enable)
+{
+	int ret;
+	uint8_t saved_conf[6] = { 0 };
+
+	/* Variable to set the accelerometer configuration value 50Hz for FOC */
+	uint8_t acc_conf_data[2] = { BMI3_FOC_ACC_CONF_VAL_LSB,
+				     BMI3_FOC_ACC_CONF_VAL_MSB };
+
+	if (!enable)
+		return EC_SUCCESS;
+
+	/* Get default configurations for the type of feature selected. */
+	RETURN_ERROR(bmi3_read_n(s, BMI3_REG_ACC_CONF, saved_conf, 6));
+
+	ret = bmi3_write_n(s, BMI3_REG_ACC_CONF, acc_conf_data, 2);
+	if (ret)
+		goto end_calib;
+
+	msleep(FOC_DELAY);
+
+	switch (s->type) {
+	case MOTIONSENSE_TYPE_ACCEL:
+		ret = EC_RES_INVALID_COMMAND;
+		goto end_calib;
+	case MOTIONSENSE_TYPE_GYRO:
+		ret = set_gyro_foc_config(s);
+		if (ret)
+			goto end_calib;
+
+		ret = get_calib_result(s);
+		if (ret)
+			goto end_calib;
+
+		break;
+	default:
+		/* Not supported on Magnetometer */
+		ret = EC_RES_INVALID_PARAM;
+		goto end_calib;
+	}
+
+end_calib:
+	/* Restore ACC_CONF before exiting */
+	RETURN_ERROR(bmi3_write_n(s, BMI3_REG_ACC_CONF, &saved_conf[2], 4));
+
+	return ret;
+}
+
+static int get_offset(const struct motion_sensor_t *s, int16_t *offset,
+		      int16_t *temp)
+{
+	int i;
+	intv3_t v;
+
+	switch (s->type) {
+	case MOTIONSENSE_TYPE_ACCEL:
+		/*
+		 * The offset of the accelerometer is a 8 bit
+		 * two-complement number in units of 3.9 mg independent of the
+		 * range selected for the accelerometer.
+		 */
+		RETURN_ERROR(get_accel_offset(s, v));
+		break;
+	case MOTIONSENSE_TYPE_GYRO:
+		/* Gyro offset is in milli-dps */
+		RETURN_ERROR(get_gyro_offset(s, v));
+		break;
+	default:
+		for (i = X; i <= Z; i++)
+			v[i] = 0;
+	}
+
+	rotate(v, *s->rot_standard_ref, v);
+	offset[X] = v[X];
+	offset[Y] = v[Y];
+	offset[Z] = v[Z];
+	/* Saving temperature at calibration not supported yet */
+	*temp = (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP;
+
+	return EC_SUCCESS;
+}
+
+static int set_offset(const struct motion_sensor_t *s, const int16_t *offset,
+		      int16_t temp)
+{
+	intv3_t v = { offset[X], offset[Y], offset[Z] };
+	(void)temp;
+
+	rotate_inv(v, *s->rot_standard_ref, v);
+
+	switch (s->type) {
+	case MOTIONSENSE_TYPE_ACCEL:
+		/* Offset should be in units of mg */
+		RETURN_ERROR(set_accel_offset(s, v));
+		break;
+	case MOTIONSENSE_TYPE_GYRO:
+		/* Offset should be in units of mdps */
+		RETURN_ERROR(set_gyro_offset(s, v));
+		break;
+	default:
+		return EC_RES_INVALID_PARAM;
+	}
+
+	return EC_SUCCESS;
+}
+
+#ifdef CONFIG_BODY_DETECTION
+static int get_rms_noise(const struct motion_sensor_t *s)
+{
+	return bmi_get_rms_noise(s, BMI3_ACCEL_RMS_NOISE_100HZ);
+}
+#endif
+
+static int set_scale(const struct motion_sensor_t *s, const uint16_t *scale,
+		     int16_t temp)
+{
+	struct accelgyro_saved_data_t *saved_data = BMI_GET_SAVED_DATA(s);
+
+	saved_data->scale[X] = scale[X];
+	saved_data->scale[Y] = scale[Y];
+	saved_data->scale[Z] = scale[Z];
+
+	return EC_SUCCESS;
+}
+
+static int get_scale(const struct motion_sensor_t *s, uint16_t *scale,
+		     int16_t *temp)
+{
+	struct accelgyro_saved_data_t *saved_data = BMI_GET_SAVED_DATA(s);
+
+	scale[X] = saved_data->scale[X];
+	scale[Y] = saved_data->scale[Y];
+	scale[Z] = saved_data->scale[Z];
+
+	*temp = (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP;
+
+	return EC_SUCCESS;
+}
+
+static int get_data_rate(const struct motion_sensor_t *s)
+{
+	struct accelgyro_saved_data_t *saved_data = BMI_GET_SAVED_DATA(s);
+
+	return saved_data->odr;
+}
+
+static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
+{
+	int ret;
+	int normalized_rate = 0;
+	uint8_t reg_data[4];
+	uint8_t reg_val = 0;
+
+	struct accelgyro_saved_data_t *saved_data = BMI_GET_SAVED_DATA(s);
+
+	if (rate > 0)
+		RETURN_ERROR(bmi_get_normalized_rate(
+			s, rate, rnd, &normalized_rate, &reg_val));
+
+	/*
+	 * Lock accel resource to prevent another task from attempting
+	 * to write accel parameters until we are done.
+	 */
+	mutex_lock(s->mutex);
+
+	/*
+	 * Get default configurations for the type of feature selected.
+	 */
+	ret = bmi3_read_n(s, BMI3_REG_ACC_CONF + s->type, reg_data, 4);
+	if (ret) {
+		mutex_unlock(s->mutex);
+		return ret;
+	}
+
+	if (s->type == MOTIONSENSE_TYPE_ACCEL) {
+		if (rate == 0) {
+			/* FIFO stop collecting events */
+			if (IS_ENABLED(ACCELGYRO_BMI3XX_INT_ENABLE))
+				ret = enable_fifo(s, 0);
+
+			/*
+			 * Disable accel to set rate equal to zero.
+			 * Accel does not have suspend mode.
+			 */
+			reg_data[3] = BMI3_SET_BITS(reg_data[3],
+						    BMI3_POWER_MODE,
+						    BMI3_ACC_MODE_DISABLE);
+
+			saved_data->odr = 0;
+		} else if (saved_data->odr == 0) {
+			/*
+			 * Power mode changed from suspend to
+			 * normal
+			 */
+			reg_data[3] = BMI3_SET_BITS(reg_data[3],
+						    BMI3_POWER_MODE,
+						    BMI3_ACC_MODE_NORMAL);
+		}
+	} else if (s->type == MOTIONSENSE_TYPE_GYRO) {
+		if (rate == 0) {
+			/* FIFO stop collecting events */
+			if (IS_ENABLED(ACCELGYRO_BMI3XX_INT_ENABLE))
+				ret = enable_fifo(s, 0);
+
+			/*
+			 * Set gyro to suspend mode to disable gyro
+			 * however keep internal driver enabled
+			 */
+			reg_data[3] = BMI3_SET_BITS(reg_data[3],
+						    BMI3_POWER_MODE,
+						    BMI3_GYR_MODE_SUSPEND);
+
+			saved_data->odr = 0;
+		} else if (saved_data->odr == 0) {
+			/* Power mode changed from suspend to
+			 * normal
+			 */
+			reg_data[3] = BMI3_SET_BITS(reg_data[3],
+						    BMI3_POWER_MODE,
+						    BMI3_GYR_MODE_NORMAL);
+		}
+	}
+
+	/* Set accelerometer ODR */
+	reg_data[2] = BMI3_SET_BIT_POS0(reg_data[2], BMI3_SENS_ODR, reg_val);
+
+	/* Set the accel/gyro configurations. */
+	ret = bmi3_write_n(s, BMI3_REG_ACC_CONF + s->type, &reg_data[2], 2);
+	if (ret) {
+		mutex_unlock(s->mutex);
+		return ret;
+	}
+
+	saved_data->odr = normalized_rate;
+
+	/*
+	 * If rate is non zero, FIFO start collecting events.
+	 * They will be discarded if AP does not want them.
+	 */
+	if (IS_ENABLED(ACCELGYRO_BMI3XX_INT_ENABLE) && (rate > 0))
+		ret = enable_fifo(s, 1);
+
+	mutex_unlock(s->mutex);
+	return ret;
+}
+
+static int get_resolution(const struct motion_sensor_t *s)
+{
+	return BMI3_16_BIT_RESOLUTION;
+}
+
+static int set_range(struct motion_sensor_t *s, int range, int rnd)
+{
+	int ret;
+	uint8_t index, sens_size = 0;
+	uint8_t reg_data[4] = { 0 };
+	int(*sensor_range)[2];
+
+	int acc_sensor_range[4][2] = {
+		{ 2, BMI3_ACC_RANGE_2G },
+		{ 4, BMI3_ACC_RANGE_4G },
+		{ 8, BMI3_ACC_RANGE_8G },
+		{ 16, BMI3_ACC_RANGE_16G },
+	};
+
+	int gyr_sensor_range[5][2] = {
+		{ 125, BMI3_GYR_RANGE_125DPS },
+		{ 250, BMI3_GYR_RANGE_250DPS },
+		{ 500, BMI3_GYR_RANGE_500DPS },
+		{ 1000, BMI3_GYR_RANGE_1000DPS },
+		{ 2000, BMI3_GYR_RANGE_2000DPS },
+	};
+
+	if (s->type == MOTIONSENSE_TYPE_ACCEL) {
+		sens_size = ARRAY_SIZE(acc_sensor_range);
+		sensor_range = acc_sensor_range;
+	} else {
+		sens_size = ARRAY_SIZE(gyr_sensor_range);
+		sensor_range = gyr_sensor_range;
+	}
+
+	for (index = 0; index < sens_size - 1; index++) {
+		if (range <= sensor_range[index][0])
+			break;
+
+		if (range < sensor_range[index + 1][0] && rnd) {
+			index++;
+			break;
+		}
+	}
+
+	mutex_lock(s->mutex);
+
+	/*
+	 * Read the range register from sensor for accelerometer/gyroscope
+	 * s->type should have MOTIONSENSE_TYPE_ACCEL = 0 ;
+	 * MOTIONSENSE_TYPE_GYRO = 1
+	 */
+	ret = bmi3_read_n(s, BMI3_REG_ACC_CONF + s->type, reg_data, 4);
+
+	if (ret == EC_SUCCESS) {
+		/* Set accelerometer/Gyroscope range */
+		/* Gravity range of the sensor (+/- 2G, 4G, 8G, 16G). */
+		reg_data[2] = BMI3_SET_BITS(reg_data[2], BMI3_SENS_RANGE,
+					    sensor_range[index][1]);
+
+		/* Set the accel/gyro configurations. */
+		ret = bmi3_write_n(s, BMI3_REG_ACC_CONF + s->type, &reg_data[2],
+				   2);
+
+		/* Now that we have set the range, update the driver's value. */
+		if (ret == EC_SUCCESS)
+			s->current_range = sensor_range[index][0];
+	}
+
+	mutex_unlock(s->mutex);
+
+	return ret;
+}
+
+static int read(const struct motion_sensor_t *s, intv3_t v)
+{
+	int ret;
+	uint8_t reg_data[8] = { 0 };
+	uint16_t status_val = 0;
+
+	mutex_lock(s->mutex);
+
+	/* Read the status register */
+	ret = bmi3_read_n(s, BMI3_REG_STATUS, reg_data, 4);
+
+	if (ret == EC_SUCCESS) {
+		status_val = (reg_data[2] | ((uint16_t)reg_data[3] << 8));
+		/*
+		 * If sensor data is not ready, return the previous read data.
+		 * Note: return success so that motion sensor task can read
+		 * again to get the latest updated sensor data quickly.
+		 */
+		if (!(status_val & BMI3_DRDY_MASK(s->type))) {
+			if (v != s->raw_xyz)
+				memcpy(v, s->raw_xyz, sizeof(s->raw_xyz));
+
+			mutex_unlock(s->mutex);
+
+			return EC_SUCCESS;
+		}
+
+		if (s->type == MOTIONSENSE_TYPE_ACCEL) {
+			/* Read the sensor data */
+			ret = bmi3_read_n(s, BMI3_REG_ACC_DATA_X, reg_data, 8);
+		} else if (s->type == MOTIONSENSE_TYPE_GYRO) {
+			/* Read the sensor data */
+			ret = bmi3_read_n(s, BMI3_REG_GYR_DATA_X, reg_data, 8);
+		}
+
+		if (ret == EC_SUCCESS) {
+			v[0] = ((int16_t)((reg_data[3] << 8) | reg_data[2]));
+			v[1] = ((int16_t)((reg_data[5] << 8) | reg_data[4]));
+			v[2] = ((int16_t)((reg_data[7] << 8) | reg_data[6]));
+
+			rotate(v, *s->rot_standard_ref, v);
+		}
+	}
+
+	mutex_unlock(s->mutex);
+
+	return ret;
+}
+
+static int init(struct motion_sensor_t *s)
+{
+	/* Status of communication result */
+	uint8_t i;
+	uint8_t reg_data[4] = { 0 };
+
+	/* Store the sensor configurations */
+	struct accelgyro_saved_data_t *saved_data = BMI_GET_SAVED_DATA(s);
+	struct bmi_drv_data_t *data = BMI_GET_DATA(s);
+
+	/* This driver requires a mutex */
+	ASSERT(s->mutex);
+
+	/*
+	 * BMI3xx driver only supports MOTIONSENSE_TYPE_ACCEL and
+	 * MOTIONSENSE_TYPE_GYR0
+	 */
+	if (s->type != MOTIONSENSE_TYPE_ACCEL &&
+	    s->type != MOTIONSENSE_TYPE_GYRO)
+		return EC_ERROR_UNIMPLEMENTED;
+
+	/* Read chip id */
+	RETURN_ERROR(bmi3_read_n(s, BMI3_REG_CHIP_ID, reg_data, 4));
+
+	if (reg_data[2] != BMI323_CHIP_ID)
+		return EC_ERROR_HW_INTERNAL;
+
+	if (s->type == MOTIONSENSE_TYPE_ACCEL) {
+		/* Reset bmi3 device */
+		reg_data[0] =
+			(uint8_t)(BMI3_CMD_SOFT_RESET & BMI3_SET_LOW_BYTE);
+		reg_data[1] =
+			(uint8_t)((BMI3_CMD_SOFT_RESET & BMI3_SET_HIGH_BYTE) >>
+				  8);
+
+		RETURN_ERROR(bmi3_write_n(s, BMI3_REG_CMD, reg_data, 2));
+
+		/* Delay of 2ms after soft reset*/
+		msleep(2);
+
+		/* Enable feature engine bit */
+		reg_data[0] = BMI3_ENABLE;
+		reg_data[1] = 0;
+
+		RETURN_ERROR(bmi3_write_n(s, BMI3_REG_FEATURE_ENGINE_GLOB_CTRL,
+					  reg_data, 2));
+
+		if (IS_ENABLED(ACCELGYRO_BMI3XX_INT_ENABLE))
+			RETURN_ERROR(config_interrupt(s));
+	}
+
+	for (i = X; i <= Z; i++)
+		saved_data->scale[i] = MOTION_SENSE_DEFAULT_SCALE;
+
+	/* The sensor is in Suspend mode at init, so set data rate to 0*/
+	saved_data->odr = 0;
+
+	/* Flags used in FIFO parsing */
+	data->flags &= ~(BMI_FLAG_SEC_I2C_ENABLED |
+			 (BMI_FIFO_ALL_MASK << BMI_FIFO_FLAG_OFFSET));
+
+	return sensor_init_done(s);
+}
+
+/* Accelerometer/Gyroscope base driver structure */
+const struct accelgyro_drv bmi3xx_drv = {
+	.init = init,
+	.read = read,
+	.set_range = set_range,
+	.get_resolution = get_resolution,
+	.set_data_rate = set_data_rate,
+	.get_data_rate = get_data_rate,
+	.get_scale = get_scale,
+	.set_scale = set_scale,
+	.set_offset = set_offset,
+	.get_offset = get_offset,
+	.perform_calib = perform_calib,
+	.read_temp = read_temp,
+#ifdef ACCELGYRO_BMI3XX_INT_ENABLE
+	.irq_handler = irq_handler,
+#endif
+#ifdef CONFIG_GESTURE_HOST_DETECTION
+	.list_activities = bmi_list_activities,
+#endif
+#ifdef CONFIG_BODY_DETECTION
+	.get_rms_noise = get_rms_noise,
+#endif
+};
diff --git a/driver/accelgyro_bmi3xx.h b/driver/accelgyro_bmi3xx.h
new file mode 100644
index 0000000000..e128b8381c
--- /dev/null
+++ b/driver/accelgyro_bmi3xx.h
@@ -0,0 +1,284 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* BMI3XX gsensor module for Chrome EC */
+
+#ifndef __CROS_EC_ACCELGYRO_BMI3XX_H
+#define __CROS_EC_ACCELGYRO_BMI3XX_H
+
+/* Sensor Specific macros */
+#define BMI3_ADDR_I2C_PRIM 0x68
+#define BMI3_ADDR_I2C_SEC 0x69
+#define BMI3_16_BIT_RESOLUTION 16
+
+/* Chip-specific registers */
+#define BMI3_REG_CHIP_ID 0x00
+
+#define BMI3_REG_STATUS 0x02
+#define BMI3_STAT_DATA_RDY_ACCEL_POS 7
+#define BMI3_STAT_DATA_RDY_ACCEL_MSK 0x80
+
+#define BMI3_REG_ACC_DATA_X 0x03
+#define BMI3_ACC_RANGE_2G 0x00
+#define BMI3_ACC_RANGE_4G 0x01
+#define BMI3_ACC_RANGE_8G 0x02
+#define BMI3_ACC_RANGE_16G 0x03
+#define BMI3_ACC_MODE_DISABLE 0x00
+#define BMI3_ACC_MODE_LOW_PWR 0x03
+#define BMI3_ACC_MODE_NORMAL 0X04
+#define BMI3_ACC_MODE_HIGH_PERF 0x07
+
+#define BMI3_REG_GYR_DATA_X 0x06
+#define BMI3_GYR_RANGE_125DPS 0x00
+#define BMI3_GYR_RANGE_250DPS 0x01
+#define BMI3_GYR_RANGE_500DPS 0x02
+#define BMI3_GYR_RANGE_1000DPS 0x03
+#define BMI3_GYR_RANGE_2000DPS 0x04
+#define BMI3_GYR_MODE_DISABLE 0x00
+#define BMI3_GYR_MODE_SUSPEND 0X01
+#define BMI3_GYR_MODE_ULTRA_LOW_PWR 0X02
+#define BMI3_GYR_MODE_LOW_PWR 0x03
+#define BMI3_GYR_MODE_NORMAL 0X04
+#define BMI3_GYR_MODE_HIGH_PERF 0x07
+
+#define BMI3_REG_INT_STATUS_INT1 0x0D
+#define BMI3_REG_FIFO_FILL_LVL 0x15
+#define BMI3_REG_FIFO_DATA 0x16
+#define BMI3_REG_ACC_CONF 0x20
+#define BMI3_REG_GYR_CONF 0x21
+#define BMI3_REG_INT_MAP1 0x3A
+#define BMI3_REG_FIFO_WATERMARK 0x35
+#define BMI3_REG_UGAIN_OFF_SEL 0x3F
+#define BMI3_REG_FIFO_CONF 0x36
+#define BMI3_FIFO_STOP_ON_FULL 0x01
+#define BMI3_FIFO_TIME_EN 0x01
+#define BMI3_FIFO_ACC_EN 0x02
+#define BMI3_FIFO_GYR_EN 0x04
+#define BMI3_FIFO_TEMP_EN 0x08
+#define BMI3_FIFO_ALL_EN 0x0F
+
+#define BMI3_REG_FIFO_CTRL 0x37
+#define BMI3_REG_IO_INT_CTRL 0x38
+#define BMI3_INT1_LVL_MASK 0x01
+#define BMI3_INT1_OD_MASK 0x02
+#define BMI3_INT1_OD_POS 1
+#define BMI3_INT1_OUTPUT_EN_MASK 0x04
+#define BMI3_INT1_OUTPUT_EN_POS 2
+#define BMI3_INT_PUSH_PULL 0
+#define BMI3_INT_OPEN_DRAIN 1
+#define BMI3_INT_ACTIVE_LOW 0
+#define BMI3_INT_ACTIVE_HIGH 1
+
+#define BMI3_REG_IO_INT_CONF 0x39
+#define BMI3_INT_LATCH_EN 1
+#define BMI3_INT_LATCH_DISABLE 0
+
+#define BMI3_REG_FEATURE_ENGINE_GLOB_CTRL 0x40
+
+#define BMI3_FEATURE_EVENT_EXT 0x47
+#define BMI3_PORTRAIT_LANDSCAPE_MASK 0x03
+#define BMI3_PORTRAIT 0
+#define BMI3_LANDSCAPE 1
+#define BMI3_PORTRAIT_INVERT 2
+#define BMI3_LANDSCAPE_INVERT 3
+
+#define BMI3_ACC_DP_OFF_X 0x60
+#define BMI3_ACC_DP_OFF_Y 0x62
+#define BMI3_ACC_DP_OFF_Z 0x64
+
+#define BMI3_GYR_DP_OFF_X 0x66
+#define BMI3_GYR_DP_OFF_Y 0x68
+#define BMI3_GYR_DP_OFF_Z 0x6A
+
+#define BMI3_REG_CMD 0x7E
+#define BMI3_CMD_SOFT_RESET 0xDEAF
+
+/* BMI3 Interrupt Output Enable */
+#define BMI3_INT_OUTPUT_DISABLE 0
+#define BMI3_INT_OUTPUT_ENABLE 1
+
+/* FIFO sensor data length (in word), Accel or Gyro */
+#define BMI3_FIFO_ENTRY 0x3
+/* Macro to define accelerometer configuration value for FOC */
+#define BMI3_FOC_ACC_CONF_VAL_LSB 0xB7
+#define BMI3_FOC_ACC_CONF_VAL_MSB 0x40
+/* Macro to define the accel FOC range */
+#define BMI3_ACC_FOC_2G_REF 16384
+#define BMI3_ACC_FOC_4G_REF 8192
+#define BMI3_ACC_FOC_8G_REF 4096
+#define BMI3_ACC_FOC_16G_REF 2048
+#define BMI3_FOC_SAMPLE_LIMIT 32
+
+#define FOC_TRY_COUNT 5
+/* 20ms delay for 50Hz ODR */
+#define FOC_DELAY 20
+#define OFFSET_UPDATE_DELAY 120
+#define BMI3_INT_STATUS_FWM 0x4000
+#define BMI3_INT_STATUS_FFULL 0x8000
+#define BMI3_INT_STATUS_ORIENTATION 0x0008
+
+#define BMI3_FIFO_GYRO_I2C_SYNC_FRAME 0x7f02
+#define BMI3_FIFO_ACCEL_I2C_SYNC_FRAME 0x7f01
+
+/* Gyro self calibration address */
+#define BMI3_BASE_ADDR_SC 0x26
+#define BMI3_CMD_SELF_CALIB 0x0101
+
+/* Feature engine General purpose register 1. */
+#define BMI3_FEATURE_IO_0 0x10
+#define BMI3_ANY_MOTION_X_EN_MASK 0x08
+
+#define BMI3_FEATURE_IO_1 0x11
+#define BMI3_FEATURE_IO_1_ERROR_MASK 0x0F
+#define BMI3_FEATURE_IO_1_NO_ERROR 0x05
+#define BMI3_SC_ST_STATUS_MASK 0x10
+#define BMI3_SC_RESULT_MASK 0x20
+#define BMI3_UGAIN_OFFS_UPD_COMPLETE 0x01
+
+#define BMI3_FEATURE_IO_STATUS 0x14
+
+/*
+ * The max positive value of accel data is 0x7FFF, equal to range(g)
+ * So, in order to get +1g, divide the 0x7FFF by range
+ */
+#define BMI3_ACC_DATA_PLUS_1G(range) (0x7FFF / (range))
+#define BMI3_ACC_DATA_MINUS_1G(range) (-BMI3_ACC_DATA_PLUS_1G(range))
+
+/* Offset DMA registers */
+#define BMI3_ACC_OFFSET_ADDR 0x40
+#define BMI3_GYRO_OFFSET_ADDR 0x46
+
+/*
+ * Start address of the DMA transaction. Has to be written to initiate a
+ * transaction.
+ */
+#define BMI3_FEATURE_ENGINE_DMA_TX 0x41
+
+/* DMA read/write data. On read transaction expect first word to be zero. */
+#define BMI3_FEATURE_ENGINE_DMA_TX_DATA 0x42
+
+/* Command for offset update */
+#define BMI3_CMD_USR_GAIN_OFFS_UPDATE 0x301
+
+/* 1LSB - 31 Micro-G */
+#define BMI3_OFFSET_ACC_MULTI_MG (31 * 1000)
+
+/* 1LSB = 61 milli-dps*/
+#define BMI3_OFFSET_GYR_MDPS (61 * 1000)
+
+#define BMI3_FIFO_BUFFER 32
+
+/* General Macro Definitions */
+/* LSB and MSB mask definitions */
+#define BMI3_SET_LOW_BYTE 0x00FF
+#define BMI3_SET_HIGH_BYTE 0xFF00
+
+/* For enable and disable */
+#define BMI3_ENABLE 0x1
+#define BMI3_DISABLE 0x0
+
+/* Defines mode of operation for Accelerometer */
+#define BMI3_POWER_MODE_MASK 0x70
+#define BMI3_POWER_MODE_POS 4
+
+#define BMI3_SENS_ODR_MASK 0x0F
+
+/* Full scale, Resolution */
+#define BMI3_SENS_RANGE_MASK 0x70
+#define BMI3_SENS_RANGE_POS 4
+
+#define BMI3_CHIP_ID_MASK 0xFF
+
+/* Map FIFO water-mark interrupt to either INT1 or INT2 or IBI */
+#define BMI3_FWM_INT_MASK 0x30
+#define BMI3_FWM_INT_POS 4
+
+/* Map FIFO full interrupt to either INT1 or INT2 or IBI */
+#define BMI3_FFULL_INT_MASK 0xC0
+#define BMI3_FFULL_INT_POS 6
+
+#define BMI3_ORIENT_INT_MASK 0xC0
+#define BMI3_ORIENT_INT_POS 6
+
+/*  Mask definitions for interrupt pin configuration */
+#define BMI3_INT_LATCH_MASK 0x0001
+
+/**
+ * Current fill level of FIFO buffer
+ * An empty FIFO corresponds to 0x000. The word counter may be reset by reading
+ * out all frames from the FIFO buffer or when the FIFO is reset through
+ * fifo_flush. The word counter is updated each time a complete frame was read
+ * or written.
+ */
+#define BMI3_FIFO_FILL_LVL_MASK 0x07FF
+
+/* Root mean square noise of 100 Hz accelerometer, units: ug */
+#define BMI3_ACCEL_RMS_NOISE_100HZ 1200
+
+/* Enum to define interrupt lines */
+enum bmi3_hw_int_pin {
+	BMI3_INT_NONE,
+	BMI3_INT1,
+	BMI3_INT2,
+	BMI3_I3C_INT,
+	BMI3_INT_PIN_MAX
+};
+
+/* Structure to define FIFO frame configuration */
+struct bmi3_fifo_frame {
+	uint16_t data[BMI3_FIFO_BUFFER + 1];
+
+	/* Available fifo length */
+	uint16_t available_fifo_len;
+};
+
+enum sensor_index_t {
+	FIRST_CONT_SENSOR = 0,
+	SENSOR_ACCEL = FIRST_CONT_SENSOR,
+	SENSOR_GYRO,
+	NUM_OF_PRIMARY_SENSOR,
+};
+
+#define BMI3_DRDY_OFF(_sensor) (7 - (_sensor))
+#define BMI3_DRDY_MASK(_sensor) (1 << BMI3_DRDY_OFF(_sensor))
+
+/* Utility macros */
+#define BMI3_SET_BITS(reg_data, bitname, data) \
+	((reg_data & ~(bitname##_MASK)) |      \
+	 ((data << bitname##_POS) & bitname##_MASK))
+
+#define BMI3_GET_BITS(reg_data, bitname) \
+	((reg_data & (bitname##_MASK)) >> (bitname##_POS))
+
+#define BMI3_SET_BIT_POS0(reg_data, bitname, data) \
+	((reg_data & ~(bitname##_MASK)) | (data & bitname##_MASK))
+
+#define BMI3_GET_BIT_POS0(reg_data, bitname) (reg_data & (bitname##_MASK))
+
+extern const struct accelgyro_drv bmi3xx_drv;
+
+void bmi3xx_interrupt(enum gpio_signal signal);
+
+#if defined(CONFIG_ZEPHYR)
+#if DT_NODE_EXISTS(DT_ALIAS(bmi3xx_int))
+/*
+ * Get the motion sensor ID of the BMI3xx sensor that
+ * generates the interrupt.
+ * The interrupt is converted to the event and transferred to motion
+ * sense task that actually handles the interrupt.
+ *
+ * Here, we use alias to get the motion sensor ID
+ *
+ * e.g) base_accel is the label of a child node in /motionsense-sensors
+ * aliases {
+ *     bmi3xx-int = &base_accel;
+ * };
+ */
+#define CONFIG_ACCELGYRO_BMI3XX_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(SENSOR_ID(DT_ALIAS(bmi3xx_int)))
+#endif
+#endif /* CONFIG_ZEPHYR */
+
+#endif /* __CROS_EC_ACCELGYRO_BMI3XX_H */
diff --git a/driver/accelgyro_bmi_common.c b/driver/accelgyro_bmi_common.c
index 2d8cfa2c45..27aab34c3e 100644
--- a/driver/accelgyro_bmi_common.c
+++ b/driver/accelgyro_bmi_common.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,46 +8,58 @@
  * 3D digital accelerometer & 3D digital gyroscope
  */
 
-
 #include "accelgyro.h"
+#include "accelgyro_bmi_common.h"
 #include "console.h"
-#include "driver/accelgyro_bmi_common.h"
 #include "i2c.h"
+#include "mag_bmm150.h"
+#include "mag_lis2mdl.h"
 #include "math_util.h"
 #include "motion_sense_fifo.h"
 #include "spi.h"
 
 #define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args)
+
+#if !defined(CONFIG_ACCELGYRO_BMI160) && !defined(CONFIG_ACCELGYRO_BMI220) && \
+	!defined(CONFIG_ACCELGYRO_BMI260) && !defined(CONFIG_ACCELGYRO_BMI3XX)
+#error "Must use following sensors BMI160 BMI220 BMI260 BMI3XX"
+#endif
 
-#if defined(CONFIG_ACCELGYRO_BMI260) && !defined(CONFIG_ACCELGYRO_BMI160)
+#if (defined(CONFIG_ACCELGYRO_BMI260) || defined(CONFIG_ACCELGYRO_BMI220)) && \
+	!defined(CONFIG_ACCELGYRO_BMI160)
 #define V(s_) 1
-#elif defined(CONFIG_ACCELGYRO_BMI160) && !defined(CONFIG_ACCELGYRO_BMI260)
+#elif defined(CONFIG_ACCELGYRO_BMI160) &&     \
+	!(defined(CONFIG_ACCELGYRO_BMI260) || \
+	  defined(CONFIG_ACCELGYRO_BMI220))
 #define V(s_) 0
 #else
-#define V(s_) ((s_)->chip == MOTIONSENSE_CHIP_BMI260)
+#define V(s_)                                     \
+	((s_)->chip == MOTIONSENSE_CHIP_BMI260 || \
+	 (s_)->chip == MOTIONSENSE_CHIP_BMI220)
 #endif
 /* Index for which table to use. */
-#if !defined(CONFIG_ACCELGYRO_BMI160) || !defined(CONFIG_ACCELGYRO_BMI260)
-#define T(s_) 0
-#else
+#if defined(CONFIG_ACCELGYRO_BMI160) && \
+	(defined(CONFIG_ACCELGYRO_BMI220) || defined(CONFIG_ACCELGYRO_BMI260))
 #define T(s_) V(s_)
+#else
+#define T(s_) 0
 #endif
 
 /* List of range values in +/-G's and their associated register values. */
 const struct bmi_accel_param_pair g_ranges[][4] = {
 #ifdef CONFIG_ACCELGYRO_BMI160
-	{ {2,  BMI160_GSEL_2G},
-	  {4,  BMI160_GSEL_4G},
-	  {8,  BMI160_GSEL_8G},
-	  {16, BMI160_GSEL_16G} },
+	{ { 2, BMI160_GSEL_2G },
+	  { 4, BMI160_GSEL_4G },
+	  { 8, BMI160_GSEL_8G },
+	  { 16, BMI160_GSEL_16G } },
 #endif
-#ifdef CONFIG_ACCELGYRO_BMI260
-	{ {2,  BMI260_GSEL_2G},
-	  {4,  BMI260_GSEL_4G},
-	  {8,  BMI260_GSEL_8G},
-	  {16, BMI260_GSEL_16G} },
+#if defined(CONFIG_ACCELGYRO_BMI220) || defined(CONFIG_ACCELGYRO_BMI260)
+	{ { 2, BMI260_GSEL_2G },
+	  { 4, BMI260_GSEL_4G },
+	  { 8, BMI260_GSEL_8G },
+	  { 16, BMI260_GSEL_16G } },
 #endif
 };
 
@@ -57,18 +69,18 @@ const struct bmi_accel_param_pair g_ranges[][4] = {
  */
 const struct bmi_accel_param_pair dps_ranges[][5] = {
 #ifdef CONFIG_ACCELGYRO_BMI160
-	{ {125,  BMI160_DPS_SEL_125},
-	  {250,  BMI160_DPS_SEL_250},
-	  {500,  BMI160_DPS_SEL_500},
-	  {1000, BMI160_DPS_SEL_1000},
-	  {2000, BMI160_DPS_SEL_2000} },
+	{ { 125, BMI160_DPS_SEL_125 },
+	  { 250, BMI160_DPS_SEL_250 },
+	  { 500, BMI160_DPS_SEL_500 },
+	  { 1000, BMI160_DPS_SEL_1000 },
+	  { 2000, BMI160_DPS_SEL_2000 } },
 #endif
-#ifdef CONFIG_ACCELGYRO_BMI260
-	{ {125,  BMI260_DPS_SEL_125},
-	  {250,  BMI260_DPS_SEL_250},
-	  {500,  BMI260_DPS_SEL_500},
-	  {1000, BMI260_DPS_SEL_1000},
-	  {2000, BMI260_DPS_SEL_2000} },
+#if defined(CONFIG_ACCELGYRO_BMI220) || defined(CONFIG_ACCELGYRO_BMI260)
+	{ { 125, BMI260_DPS_SEL_125 },
+	  { 250, BMI260_DPS_SEL_250 },
+	  { 500, BMI260_DPS_SEL_500 },
+	  { 1000, BMI260_DPS_SEL_1000 },
+	  { 2000, BMI260_DPS_SEL_2000 } },
 #endif
 };
 
@@ -86,8 +98,8 @@ int bmi_get_xyz_reg(const struct motion_sensor_t *s)
 	}
 }
 
-const struct bmi_accel_param_pair *bmi_get_range_table(
-		const struct motion_sensor_t *s, int *psize)
+const struct bmi_accel_param_pair *
+bmi_get_range_table(const struct motion_sensor_t *s, int *psize)
 {
 	if (s->type == MOTIONSENSE_TYPE_ACCEL) {
 		if (psize)
@@ -106,8 +118,7 @@ const struct bmi_accel_param_pair *bmi_get_range_table(
  * outside the range of values, it returns the closest valid reg value.
  */
 int bmi_get_reg_val(const int eng_val, const int round_up,
-		    const struct bmi_accel_param_pair *pairs,
-		    const int size)
+		    const struct bmi_accel_param_pair *pairs, const int size)
 {
 	int i;
 
@@ -115,7 +126,7 @@ int bmi_get_reg_val(const int eng_val, const int round_up,
 		if (eng_val <= pairs[i].val)
 			break;
 
-		if (eng_val < pairs[i+1].val) {
+		if (eng_val < pairs[i + 1].val) {
 			if (round_up)
 				i += 1;
 			break;
@@ -140,9 +151,9 @@ int bmi_get_engineering_val(const int reg_val,
 	return pairs[i].val;
 }
 
-#ifdef CONFIG_SPI_ACCEL_PORT
-int bmi_spi_raw_read(const int addr, const uint8_t reg,
-		     uint8_t *data, const int len)
+#ifdef CONFIG_ACCELGYRO_BMI_COMM_SPI
+static int bmi_spi_raw_read(const int addr, const uint8_t reg, uint8_t *data,
+			    const int len)
 {
 	uint8_t cmd = 0x80 | reg;
 
@@ -153,51 +164,45 @@ int bmi_spi_raw_read(const int addr, const uint8_t reg,
 /**
  * Read 8bit register from accelerometer.
  */
-int bmi_read8(const int port, const uint16_t i2c_spi_addr_flags,
-	      const int reg, int *data_ptr)
+int bmi_read8(const int port, const uint16_t i2c_spi_addr_flags, const int reg,
+	      int *data_ptr)
 {
-	int rv = -EC_ERROR_PARAM1;
+	int rv;
 
-	if (SLAVE_IS_SPI(i2c_spi_addr_flags)) {
-#ifdef CONFIG_SPI_ACCEL_PORT
+#ifdef CONFIG_ACCELGYRO_BMI_COMM_SPI
+	{
 		uint8_t val;
 
-		rv = bmi_spi_raw_read(SLAVE_GET_SPI_ADDR(i2c_spi_addr_flags),
-				  reg, &val, 1);
+		rv = bmi_spi_raw_read(ACCEL_GET_SPI_ADDR(i2c_spi_addr_flags),
+				      reg, &val, 1);
 		if (rv == EC_SUCCESS)
 			*data_ptr = val;
-#endif
-	} else {
-#ifdef I2C_PORT_ACCEL
-		rv = i2c_read8(port, i2c_spi_addr_flags,
-			       reg, data_ptr);
-#endif
 	}
+#else
+	rv = i2c_read8(port, i2c_spi_addr_flags, reg, data_ptr);
+#endif
 	return rv;
 }
 
 /**
  * Write 8bit register from accelerometer.
  */
-int bmi_write8(const int port, const uint16_t i2c_spi_addr_flags,
-	       const int reg, int data)
+int bmi_write8(const int port, const uint16_t i2c_spi_addr_flags, const int reg,
+	       int data)
 {
-	int rv = -EC_ERROR_PARAM1;
+	int rv;
 
-	if (SLAVE_IS_SPI(i2c_spi_addr_flags)) {
-#ifdef CONFIG_SPI_ACCEL_PORT
+#ifdef CONFIG_ACCELGYRO_BMI_COMM_SPI
+	{
 		uint8_t cmd[2] = { reg, data };
 
 		rv = spi_transaction(
-			&spi_devices[SLAVE_GET_SPI_ADDR(i2c_spi_addr_flags)],
+			&spi_devices[ACCEL_GET_SPI_ADDR(i2c_spi_addr_flags)],
 			cmd, 2, NULL, 0);
-#endif
-	} else {
-#ifdef I2C_PORT_ACCEL
-		rv = i2c_write8(port, i2c_spi_addr_flags,
-				reg, data);
-#endif
 	}
+#else
+	rv = i2c_write8(port, i2c_spi_addr_flags, reg, data);
+#endif
 	/*
 	 * From Bosch:  BMI needs a delay of 450us after each write if it
 	 * is in suspend mode, otherwise the operation may be ignored by
@@ -205,6 +210,7 @@ int bmi_write8(const int port, const uint16_t i2c_spi_addr_flags,
 	 * the delay unconditionally.
 	 */
 	msleep(1);
+
 	return rv;
 }
 
@@ -214,20 +220,12 @@ int bmi_write8(const int port, const uint16_t i2c_spi_addr_flags,
 int bmi_read16(const int port, const uint16_t i2c_spi_addr_flags,
 	       const uint8_t reg, int *data_ptr)
 {
-	int rv = -EC_ERROR_PARAM1;
-
-	if (SLAVE_IS_SPI(i2c_spi_addr_flags)) {
-#ifdef CONFIG_SPI_ACCEL_PORT
-		rv = bmi_spi_raw_read(SLAVE_GET_SPI_ADDR(i2c_spi_addr_flags),
-				      reg, (uint8_t *)data_ptr, 2);
-#endif
-	} else {
-#ifdef I2C_PORT_ACCEL
-		rv = i2c_read16(port, i2c_spi_addr_flags,
-				reg, data_ptr);
+#ifdef CONFIG_ACCELGYRO_BMI_COMM_SPI
+	return bmi_spi_raw_read(ACCEL_GET_SPI_ADDR(i2c_spi_addr_flags), reg,
+				(uint8_t *)data_ptr, 2);
+#else
+	return i2c_read16(port, i2c_spi_addr_flags, reg, data_ptr);
 #endif
-	}
-	return rv;
 }
 
 /**
@@ -238,16 +236,11 @@ int bmi_write16(const int port, const uint16_t i2c_spi_addr_flags,
 {
 	int rv = -EC_ERROR_PARAM1;
 
-	if (SLAVE_IS_SPI(i2c_spi_addr_flags)) {
-#ifdef CONFIG_SPI_ACCEL_PORT
-		CPRINTS("%s() spi part is not implemented", __func__);
-#endif
-	} else {
-#ifdef I2C_PORT_ACCEL
-		rv = i2c_write16(port, i2c_spi_addr_flags,
-				 reg, data);
+#ifdef CONFIG_ACCELGYRO_BMI_COMM_SPI
+	CPRINTS("%s() spi part is not implemented", __func__);
+#else
+	rv = i2c_write16(port, i2c_spi_addr_flags, reg, data);
 #endif
-	}
 	/*
 	 * From Bosch:  BMI needs a delay of 450us after each write if it
 	 * is in suspend mode, otherwise the operation may be ignored by
@@ -264,20 +257,12 @@ int bmi_write16(const int port, const uint16_t i2c_spi_addr_flags,
 int bmi_read32(const int port, const uint16_t i2c_spi_addr_flags,
 	       const uint8_t reg, int *data_ptr)
 {
-	int rv = -EC_ERROR_PARAM1;
-
-	if (SLAVE_IS_SPI(i2c_spi_addr_flags)) {
-#ifdef CONFIG_SPI_ACCEL_PORT
-		rv = bmi_spi_raw_read(SLAVE_GET_SPI_ADDR(i2c_spi_addr_flags),
-				  reg, (uint8_t *)data_ptr, 4);
-#endif
-	} else {
-#ifdef I2C_PORT_ACCEL
-		rv = i2c_read32(port, i2c_spi_addr_flags,
-				reg, data_ptr);
+#ifdef CONFIG_ACCELGYRO_BMI_COMM_SPI
+	return bmi_spi_raw_read(ACCEL_GET_SPI_ADDR(i2c_spi_addr_flags), reg,
+				(uint8_t *)data_ptr, 4);
+#else
+	return i2c_read32(port, i2c_spi_addr_flags, reg, data_ptr);
 #endif
-	}
-	return rv;
 }
 
 /**
@@ -286,20 +271,12 @@ int bmi_read32(const int port, const uint16_t i2c_spi_addr_flags,
 int bmi_read_n(const int port, const uint16_t i2c_spi_addr_flags,
 	       const uint8_t reg, uint8_t *data_ptr, const int len)
 {
-	int rv = -EC_ERROR_PARAM1;
-
-	if (SLAVE_IS_SPI(i2c_spi_addr_flags)) {
-#ifdef CONFIG_SPI_ACCEL_PORT
-		rv = bmi_spi_raw_read(SLAVE_GET_SPI_ADDR(i2c_spi_addr_flags),
-				  reg, data_ptr, len);
-#endif
-	} else {
-#ifdef I2C_PORT_ACCEL
-		rv = i2c_read_block(port, i2c_spi_addr_flags,
-				    reg, data_ptr, len);
+#ifdef CONFIG_ACCELGYRO_BMI_COMM_SPI
+	return bmi_spi_raw_read(ACCEL_GET_SPI_ADDR(i2c_spi_addr_flags), reg,
+				data_ptr, len);
+#else
+	return i2c_read_block(port, i2c_spi_addr_flags, reg, data_ptr, len);
 #endif
-	}
-	return rv;
 }
 
 /**
@@ -310,16 +287,11 @@ int bmi_write_n(const int port, const uint16_t i2c_spi_addr_flags,
 {
 	int rv = -EC_ERROR_PARAM1;
 
-	if (SLAVE_IS_SPI(i2c_spi_addr_flags)) {
-#ifdef CONFIG_SPI_ACCEL_PORT
-		CPRINTS("%s() spi part is not implemented", __func__);
-#endif
-	} else {
-#ifdef I2C_PORT_ACCEL
-		rv = i2c_write_block(port, i2c_spi_addr_flags,
-				     reg, data_ptr, len);
+#ifdef CONFIG_ACCELGYRO_BMI_COMM_SPI
+	CPRINTS("%s() spi part is not implemented", __func__);
+#else
+	rv = i2c_write_block(port, i2c_spi_addr_flags, reg, data_ptr, len);
 #endif
-	}
 	/*
 	 * From Bosch:  BMI needs a delay of 450us after each write if it
 	 * is in suspend mode, otherwise the operation may be ignored by
@@ -327,13 +299,14 @@ int bmi_write_n(const int port, const uint16_t i2c_spi_addr_flags,
 	 * the delay unconditionally.
 	 */
 	msleep(1);
+
 	return rv;
 }
 /*
  * Enable/Disable specific bit set of a 8-bit reg.
  */
-int bmi_enable_reg8(const struct motion_sensor_t *s,
-		    int reg, uint8_t bits, int enable)
+int bmi_enable_reg8(const struct motion_sensor_t *s, int reg, uint8_t bits,
+		    int enable)
 {
 	if (enable)
 		return bmi_set_reg8(s, reg, bits, 0);
@@ -343,8 +316,8 @@ int bmi_enable_reg8(const struct motion_sensor_t *s,
 /*
  * Set specific bit set to certain value of a 8-bit reg.
  */
-int bmi_set_reg8(const struct motion_sensor_t *s,
-		 int reg, uint8_t bits, int mask)
+int bmi_set_reg8(const struct motion_sensor_t *s, int reg, uint8_t bits,
+		 int mask)
 {
 	int ret, val;
 
@@ -361,17 +334,13 @@ void bmi_normalize(const struct motion_sensor_t *s, intv3_t v, uint8_t *input)
 	int i;
 	struct accelgyro_saved_data_t *data = BMI_GET_SAVED_DATA(s);
 
-#ifdef CONFIG_MAG_BMI_BMM150
-	if (s->type == MOTIONSENSE_TYPE_MAG)
+	if (IS_ENABLED(CONFIG_MAG_BMI_BMM150) &&
+	    (s->type == MOTIONSENSE_TYPE_MAG)) {
 		bmm150_normalize(s, v, input);
-	else
-#endif
-#ifdef CONFIG_MAG_BMI_LIS2MDL
-	if (s->type == MOTIONSENSE_TYPE_MAG)
-		lis2mdl_normalize(s, v, data);
-	else
-#endif
-	{
+	} else if (IS_ENABLED(CONFIG_MAG_BMI_LIS2MDL) &&
+		   (s->type == MOTIONSENSE_TYPE_MAG)) {
+		lis2mdl_normalize(s, v, input);
+	} else {
 		v[0] = ((int16_t)((input[1] << 8) | input[0]));
 		v[1] = ((int16_t)((input[3] << 8) | input[2]));
 		v[2] = ((int16_t)((input[5] << 8) | input[4]));
@@ -381,12 +350,11 @@ void bmi_normalize(const struct motion_sensor_t *s, intv3_t v, uint8_t *input)
 		v[i] = SENSOR_APPLY_SCALE(v[i], data->scale[i]);
 }
 
-int bmi_decode_header(struct motion_sensor_t *accel,
-		enum fifo_header hdr, uint32_t last_ts,
-		uint8_t **bp, uint8_t *ep)
+int bmi_decode_header(struct motion_sensor_t *accel, enum fifo_header hdr,
+		      uint32_t last_ts, uint8_t **bp, uint8_t *ep)
 {
 	if ((hdr & BMI_FH_MODE_MASK) == BMI_FH_EMPTY &&
-			(hdr & BMI_FH_PARM_MASK) != 0) {
+	    (hdr & BMI_FH_PARM_MASK) != 0) {
 		int i, size = 0;
 		/* Check if there is enough space for the data frame */
 		for (i = MOTIONSENSE_TYPE_MAG; i >= MOTIONSENSE_TYPE_ACCEL;
@@ -404,21 +372,26 @@ int bmi_decode_header(struct motion_sensor_t *accel,
 			struct motion_sensor_t *s = accel + i;
 
 			if (hdr & (1 << (i + BMI_FH_PARM_OFFSET))) {
-				struct ec_response_motion_sensor_data vector;
 				int *v = s->raw_xyz;
 
-				vector.flags = 0;
 				bmi_normalize(s, v, *bp);
 				if (IS_ENABLED(CONFIG_ACCEL_SPOOF_MODE) &&
-					s->flags &
-					MOTIONSENSE_FLAG_IN_SPOOF_MODE)
+				    s->flags & MOTIONSENSE_FLAG_IN_SPOOF_MODE)
 					v = s->spoof_xyz;
-				vector.data[X] = v[X];
-				vector.data[Y] = v[Y];
-				vector.data[Z] = v[Z];
-				vector.sensor_num = s - motion_sensors;
-				motion_sense_fifo_stage_data(&vector, s, 3,
-						last_ts);
+				if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
+					struct ec_response_motion_sensor_data
+						vector;
+
+					vector.flags = 0;
+					vector.data[X] = v[X];
+					vector.data[Y] = v[Y];
+					vector.data[Z] = v[Z];
+					vector.sensor_num = s - motion_sensors;
+					motion_sense_fifo_stage_data(
+						&vector, s, 3, last_ts);
+				} else {
+					motion_sense_push_raw_xyz(s);
+				}
 				*bp += (i == MOTIONSENSE_TYPE_MAG ? 8 : 6);
 			}
 		}
@@ -448,25 +421,22 @@ int bmi_load_fifo(struct motion_sensor_t *s, uint32_t last_ts)
 	uint8_t *ep;
 	uint32_t beginning;
 
-
 	if (s->type != MOTIONSENSE_TYPE_ACCEL)
 		return EC_SUCCESS;
 
-	if (!(data->flags &
-	     (BMI_FIFO_ALL_MASK << BMI_FIFO_FLAG_OFFSET))) {
+	if (!(data->flags & (BMI_FIFO_ALL_MASK << BMI_FIFO_FLAG_OFFSET))) {
 		/*
 		 * The FIFO was disabled while we were processing it.
 		 *
 		 * Flush potential left over:
 		 * When sensor is resumed, we won't read old data.
 		 */
-		bmi_write8(s->port, s->i2c_spi_addr_flags,
-			   BMI_CMD_REG(V(s)), BMI_CMD_FIFO_FLUSH);
+		bmi_write8(s->port, s->i2c_spi_addr_flags, BMI_CMD_REG(V(s)),
+			   BMI_CMD_FIFO_FLUSH);
 		return EC_SUCCESS;
 	}
 
-	bmi_read_n(s->port, s->i2c_spi_addr_flags,
-		   BMI_FIFO_LENGTH_0(V(s)),
+	bmi_read_n(s->port, s->i2c_spi_addr_flags, BMI_FIFO_LENGTH_0(V(s)),
 		   (uint8_t *)&length, sizeof(length));
 	length &= BMI_FIFO_LENGTH_MASK(V(s));
 
@@ -492,8 +462,8 @@ int bmi_load_fifo(struct motion_sensor_t *s, uint32_t last_ts)
 		CPRINTS("unexpected large FIFO: %d", length);
 	length = MIN(length, sizeof(bmi_buffer));
 
-	bmi_read_n(s->port, s->i2c_spi_addr_flags,
-		   BMI_FIFO_DATA(V(s)), bmi_buffer, length);
+	bmi_read_n(s->port, s->i2c_spi_addr_flags, BMI_FIFO_DATA(V(s)),
+		   bmi_buffer, length);
 	beginning = *(uint32_t *)bmi_buffer;
 	ep = bmi_buffer + length;
 	/*
@@ -504,16 +474,13 @@ int bmi_load_fifo(struct motion_sensor_t *s, uint32_t last_ts)
 	 * If we see those, assume the sensors have been disabled
 	 * while this thread was running.
 	 */
-	if (beginning == 0x84848484 ||
-			(beginning & 0xdcdcdcdc) == 0x40404040) {
+	if (beginning == 0x84848484 || (beginning & 0xdcdcdcdc) == 0x40404040) {
 		CPRINTS("Suspended FIFO: accel ODR/rate: %d/%d: 0x%08x",
-				BASE_ODR(s->config[SENSOR_CONFIG_AP].odr),
-				BMI_GET_SAVED_DATA(s)->odr,
-				beginning);
+			BASE_ODR(s->config[SENSOR_CONFIG_AP].odr),
+			BMI_GET_SAVED_DATA(s)->odr, beginning);
 		return EC_SUCCESS;
 	}
 
-
 	while (bp < ep) {
 		switch (state) {
 		case FIFO_HEADER: {
@@ -536,24 +503,24 @@ int bmi_load_fifo(struct motion_sensor_t *s, uint32_t last_ts)
 				state = FIFO_DATA_CONFIG;
 				break;
 			default:
-				CPRINTS("Unknown header: 0x%02x @ %zd",
-						hdr, bp - bmi_buffer);
+				CPRINTS("Unknown header: 0x%02x @ %zd", hdr,
+					bp - bmi_buffer);
 				bmi_write8(s->port, s->i2c_spi_addr_flags,
-						BMI_CMD_REG(V(s)),
-						BMI_CMD_FIFO_FLUSH);
+					   BMI_CMD_REG(V(s)),
+					   BMI_CMD_FIFO_FLUSH);
 				return EC_ERROR_NOT_HANDLED;
 			}
 			break;
 		}
 		case FIFO_DATA_SKIP:
 			CPRINTS("@ %zd - %d, skipped %d frames",
-					bp - bmi_buffer, length, *bp);
+				bp - bmi_buffer, length, *bp);
 			bp++;
 			state = FIFO_HEADER;
 			break;
 		case FIFO_DATA_CONFIG:
 			CPRINTS("@ %zd - %d, config change: 0x%02x",
-					bp - bmi_buffer, length, *bp);
+				bp - bmi_buffer, length, *bp);
 			bp++;
 			if (V(s))
 				state = FIFO_DATA_TIME;
@@ -566,8 +533,8 @@ int bmi_load_fifo(struct motion_sensor_t *s, uint32_t last_ts)
 				continue;
 			}
 			/* We are not requesting timestamp */
-			CPRINTS("timestamp %d", (bp[2] << 16) |
-					(bp[1] << 8) | bp[0]);
+			CPRINTS("timestamp %d",
+				(bp[2] << 16) | (bp[1] << 8) | bp[0]);
 			state = FIFO_HEADER;
 			bp += 3;
 			break;
@@ -580,15 +547,14 @@ int bmi_load_fifo(struct motion_sensor_t *s, uint32_t last_ts)
 	return EC_SUCCESS;
 }
 
-int bmi_set_range(const struct motion_sensor_t *s, int range, int rnd)
+int bmi_set_range(struct motion_sensor_t *s, int range, int rnd)
 {
 	int ret, range_tbl_size;
 	uint8_t reg_val, ctrl_reg;
 	const struct bmi_accel_param_pair *ranges;
-	struct accelgyro_saved_data_t *data = BMI_GET_SAVED_DATA(s);
 
 	if (s->type == MOTIONSENSE_TYPE_MAG) {
-		data->range = range;
+		s->current_range = range;
 		return EC_SUCCESS;
 	}
 
@@ -596,22 +562,14 @@ int bmi_set_range(const struct motion_sensor_t *s, int range, int rnd)
 	ranges = bmi_get_range_table(s, &range_tbl_size);
 	reg_val = bmi_get_reg_val(range, rnd, ranges, range_tbl_size);
 
-	ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-			 ctrl_reg, reg_val);
+	ret = bmi_write8(s->port, s->i2c_spi_addr_flags, ctrl_reg, reg_val);
 	/* Now that we have set the range, update the driver's value. */
 	if (ret == EC_SUCCESS)
-		data->range = bmi_get_engineering_val(reg_val, ranges,
-				range_tbl_size);
+		s->current_range = bmi_get_engineering_val(reg_val, ranges,
+							   range_tbl_size);
 	return ret;
 }
 
-int bmi_get_range(const struct motion_sensor_t *s)
-{
-	struct accelgyro_saved_data_t *data = BMI_GET_SAVED_DATA(s);
-
-	return data->range;
-}
-
 int bmi_get_data_rate(const struct motion_sensor_t *s)
 {
 	struct accelgyro_saved_data_t *data = BMI_GET_SAVED_DATA(s);
@@ -619,10 +577,10 @@ int bmi_get_data_rate(const struct motion_sensor_t *s)
 	return data->odr;
 }
 
-int bmi_get_offset(const struct motion_sensor_t *s,
-		   int16_t *offset, int16_t *temp)
+int bmi_get_offset(const struct motion_sensor_t *s, int16_t *offset,
+		   int16_t *temp)
 {
-	int i;
+	int i, ret = EC_SUCCESS;
 	intv3_t v;
 
 	switch (s->type) {
@@ -632,7 +590,7 @@ int bmi_get_offset(const struct motion_sensor_t *s,
 		 * two-complement number in units of 3.9 mg independent of the
 		 * range selected for the accelerometer.
 		 */
-		bmi_accel_get_offset(s, v);
+		ret = bmi_accel_get_offset(s, v);
 		break;
 	case MOTIONSENSE_TYPE_GYRO:
 		/*
@@ -641,17 +599,21 @@ int bmi_get_offset(const struct motion_sensor_t *s,
 		 * Therefore a maximum range that can be compensated is
 		 * -31.25 °/s to +31.25 °/s
 		 */
-		bmi_gyro_get_offset(s, v);
+		ret = bmi_gyro_get_offset(s, v);
 		break;
 #ifdef CONFIG_MAG_BMI_BMM150
 	case MOTIONSENSE_TYPE_MAG:
-		bmm150_get_offset(s, v);
+		ret = bmm150_get_offset(s, v);
 		break;
 #endif /* defined(CONFIG_MAG_BMI_BMM150) */
 	default:
 		for (i = X; i <= Z; i++)
 			v[i] = 0;
 	}
+
+	if (ret != EC_SUCCESS)
+		return ret;
+
 	rotate(v, *s->rot_standard_ref, v);
 	offset[X] = v[X];
 	offset[Y] = v[Y];
@@ -662,30 +624,21 @@ int bmi_get_offset(const struct motion_sensor_t *s,
 }
 
 #ifdef CONFIG_BODY_DETECTION
-int bmi_get_rms_noise(const struct motion_sensor_t *s)
+int bmi_get_rms_noise(const struct motion_sensor_t *accel,
+		      int rms_noise_100hz_mg)
 {
-	int ret;
-	fp_t noise_100hz, rate, sqrt_rate_ratio;
+	fp_t rate, sqrt_rate_ratio;
 
-	switch (s->type) {
-	case MOTIONSENSE_TYPE_ACCEL:
-		/* change unit of ODR to Hz to prevent INT_TO_FP() overflow */
-		rate = INT_TO_FP(bmi_get_data_rate(s) / 1000);
-		/*
-		 * Since the noise is proportional to sqrt(ODR) in BMI, and we
-		 * have rms noise in 100 Hz, we multiply it with the sqrt(ratio
-		 * of ODR to 100Hz) to get current noise.
-		 */
-		noise_100hz = INT_TO_FP(BMI_ACCEL_RMS_NOISE_100HZ(V(s)));
-		sqrt_rate_ratio = fp_sqrtf(fp_div(rate,
-						  INT_TO_FP(BMI_ACCEL_100HZ)));
-		ret = FP_TO_INT(fp_mul(noise_100hz, sqrt_rate_ratio));
-		break;
-	default:
-		CPRINTS("%s with gyro/mag is not implemented", __func__);
-		return 0;
-	}
-	return ret;
+	/* change unit of ODR to Hz to prevent INT_TO_FP() overflow */
+	rate = INT_TO_FP(bmi_get_data_rate(accel) / 1000);
+	/*
+	 * Since the noise is proportional to sqrt(ODR) in BMI, and we
+	 * have rms noise in 100 Hz, we multiply it with the sqrt(ratio
+	 * of ODR to 100Hz) to get current noise.
+	 */
+	sqrt_rate_ratio = fp_sqrtf(fp_div(rate, INT_TO_FP(BMI_ACCEL_100HZ)));
+	return FP_TO_INT(
+		fp_mul(INT_TO_FP(rms_noise_100hz_mg), sqrt_rate_ratio));
 }
 #endif
 
@@ -694,8 +647,8 @@ int bmi_get_resolution(const struct motion_sensor_t *s)
 	return BMI_RESOLUTION;
 }
 
-int bmi_set_scale(const struct motion_sensor_t *s,
-	      const uint16_t *scale, int16_t temp)
+int bmi_set_scale(const struct motion_sensor_t *s, const uint16_t *scale,
+		  int16_t temp)
 {
 	struct accelgyro_saved_data_t *data = BMI_GET_SAVED_DATA(s);
 
@@ -705,8 +658,8 @@ int bmi_set_scale(const struct motion_sensor_t *s,
 	return EC_SUCCESS;
 }
 
-int bmi_get_scale(const struct motion_sensor_t *s,
-	      uint16_t *scale, int16_t *temp)
+int bmi_get_scale(const struct motion_sensor_t *s, uint16_t *scale,
+		  int16_t *temp)
 {
 	struct accelgyro_saved_data_t *data = BMI_GET_SAVED_DATA(s);
 
@@ -741,8 +694,8 @@ int bmi_read(const struct motion_sensor_t *s, intv3_t v)
 	uint8_t data[6];
 	int ret, status = 0;
 
-	ret = bmi_read8(s->port, s->i2c_spi_addr_flags,
-			BMI_STATUS(V(s)), &status);
+	ret = bmi_read8(s->port, s->i2c_spi_addr_flags, BMI_STATUS(V(s)),
+			&status);
 	if (ret != EC_SUCCESS)
 		return ret;
 
@@ -758,8 +711,8 @@ int bmi_read(const struct motion_sensor_t *s, intv3_t v)
 	}
 
 	/* Read 6 bytes starting at xyz_reg */
-	ret = bmi_read_n(s->port, s->i2c_spi_addr_flags,
-			 bmi_get_xyz_reg(s), data, 6);
+	ret = bmi_read_n(s->port, s->i2c_spi_addr_flags, bmi_get_xyz_reg(s),
+			 data, 6);
 
 	if (ret != EC_SUCCESS) {
 		CPRINTS("%s: type:0x%X RD XYZ Error %d", s->name, s->type, ret);
@@ -781,10 +734,10 @@ int bmi_get_sensor_temp(int idx, int *temp_ptr)
 	int ret;
 
 	ret = bmi_read_n(s->port, s->i2c_spi_addr_flags,
-			 BMI_TEMPERATURE_0(V(s)),
-			 (uint8_t *)&temp, sizeof(temp));
+			 BMI_TEMPERATURE_0(V(s)), (uint8_t *)&temp,
+			 sizeof(temp));
 
-	if (ret || temp == BMI_INVALID_TEMP)
+	if (ret || temp == (int16_t)BMI_INVALID_TEMP)
 		return EC_ERROR_NOT_POWERED;
 
 	*temp_ptr = C_TO_K(23 + ((temp + 256) >> 9));
@@ -827,79 +780,123 @@ int bmi_get_normalized_rate(const struct motion_sensor_t *s, int rate, int rnd,
 	return EC_SUCCESS;
 }
 
-void bmi_accel_get_offset(const struct motion_sensor_t *accel, intv3_t v)
+int bmi_accel_get_offset(const struct motion_sensor_t *accel, intv3_t v)
 {
-	int i, val;
+	int i, val, ret;
 
 	for (i = X; i <= Z; i++) {
-		bmi_read8(accel->port, accel->i2c_spi_addr_flags,
-			  BMI_OFFSET_ACC70(V(accel)) + i, &val);
+		ret = bmi_read8(accel->port, accel->i2c_spi_addr_flags,
+				BMI_OFFSET_ACC70(V(accel)) + i, &val);
+		if (ret != EC_SUCCESS)
+			return ret;
+
 		if (val > 0x7f)
 			val = -256 + val;
-		v[i] = round_divide(
-			(int64_t)val * BMI_OFFSET_ACC_MULTI_MG,
-			BMI_OFFSET_ACC_DIV_MG);
-
+		v[i] = round_divide((int64_t)val * BMI_OFFSET_ACC_MULTI_MG,
+				    BMI_OFFSET_ACC_DIV_MG);
 	}
+
+	return EC_SUCCESS;
 }
 
-void bmi_gyro_get_offset(const struct motion_sensor_t *gyro, intv3_t v)
+int bmi_gyro_get_offset(const struct motion_sensor_t *gyro, intv3_t v)
 {
-	int i, val, val98;
+	int i, val, val98, ret;
 
 	/* Read the MSB first */
-	bmi_read8(gyro->port, gyro->i2c_spi_addr_flags,
-		  BMI_OFFSET_EN_GYR98(V(gyro)), &val98);
+	ret = bmi_read8(gyro->port, gyro->i2c_spi_addr_flags,
+			BMI_OFFSET_EN_GYR98(V(gyro)), &val98);
+	if (ret != EC_SUCCESS)
+		return ret;
+
 	for (i = X; i <= Z; i++) {
-		bmi_read8(gyro->port, gyro->i2c_spi_addr_flags,
-			  BMI_OFFSET_GYR70(V(gyro)) + i, &val);
+		ret = bmi_read8(gyro->port, gyro->i2c_spi_addr_flags,
+				BMI_OFFSET_GYR70(V(gyro)) + i, &val);
+		if (ret != EC_SUCCESS)
+			return ret;
+
 		val |= ((val98 >> (2 * i)) & 0x3) << 8;
 		if (val > 0x1ff)
 			val = -1024 + val;
-		v[i] = round_divide(
-			(int64_t)val * BMI_OFFSET_GYRO_MULTI_MDS,
-			BMI_OFFSET_GYRO_DIV_MDS);
+		v[i] = round_divide((int64_t)val * BMI_OFFSET_GYRO_MULTI_MDS,
+				    BMI_OFFSET_GYRO_DIV_MDS);
 	}
+
+	return EC_SUCCESS;
 }
 
-void bmi_set_accel_offset(const struct motion_sensor_t *accel, intv3_t v)
+int bmi_set_accel_offset(const struct motion_sensor_t *accel, intv3_t v)
 {
-	int i, val;
+	int i, val, ret;
 
 	for (i = X; i <= Z; ++i) {
-		val = round_divide(
-			(int64_t)v[i] * BMI_OFFSET_ACC_DIV_MG,
-			BMI_OFFSET_ACC_MULTI_MG);
+		val = round_divide((int64_t)v[i] * BMI_OFFSET_ACC_DIV_MG,
+				   BMI_OFFSET_ACC_MULTI_MG);
 		if (val > 127)
 			val = 127;
 		if (val < -128)
 			val = -128;
 		if (val < 0)
 			val = 256 + val;
-		bmi_write8(accel->port, accel->i2c_spi_addr_flags,
-			   BMI_OFFSET_ACC70(V(accel)) + i, val);
+		ret = bmi_write8(accel->port, accel->i2c_spi_addr_flags,
+				 BMI_OFFSET_ACC70(V(accel)) + i, val);
+		if (ret != EC_SUCCESS)
+			return ret;
 	}
+
+	return EC_SUCCESS;
 }
 
-void bmi_set_gyro_offset(const struct motion_sensor_t *gyro, intv3_t v,
-			 int *val98_ptr)
+int bmi_set_gyro_offset(const struct motion_sensor_t *gyro, intv3_t v,
+			int *val98_ptr)
 {
-	int i, val;
+	int i, val, ret;
 
 	for (i = X; i <= Z; i++) {
-		val = round_divide(
-			(int64_t)v[i] * BMI_OFFSET_GYRO_DIV_MDS,
-			BMI_OFFSET_GYRO_MULTI_MDS);
+		val = round_divide((int64_t)v[i] * BMI_OFFSET_GYRO_DIV_MDS,
+				   BMI_OFFSET_GYRO_MULTI_MDS);
 		if (val > 511)
 			val = 511;
 		if (val < -512)
 			val = -512;
 		if (val < 0)
 			val = 1024 + val;
-		bmi_write8(gyro->port, gyro->i2c_spi_addr_flags,
-			   BMI_OFFSET_GYR70(V(gyro)) + i, val & 0xFF);
+		ret = bmi_write8(gyro->port, gyro->i2c_spi_addr_flags,
+				 BMI_OFFSET_GYR70(V(gyro)) + i, val & 0xFF);
+		if (ret != EC_SUCCESS)
+			return ret;
+
 		*val98_ptr &= ~(0x3 << (2 * i));
 		*val98_ptr |= (val >> 8) << (2 * i);
 	}
+
+	return EC_SUCCESS;
+}
+
+#ifdef CONFIG_BMI_ORIENTATION_SENSOR
+bool motion_orientation_changed(const struct motion_sensor_t *s)
+{
+	return BMI_GET_DATA(s)->orientation !=
+	       BMI_GET_DATA(s)->last_orientation;
+}
+
+enum motionsensor_orientation *
+motion_orientation_ptr(const struct motion_sensor_t *s)
+{
+	return &BMI_GET_DATA(s)->orientation;
 }
 
+void motion_orientation_update(const struct motion_sensor_t *s)
+{
+	BMI_GET_DATA(s)->last_orientation = BMI_GET_DATA(s)->orientation;
+}
+#endif
+
+int bmi_list_activities(const struct motion_sensor_t *s, uint32_t *enabled,
+			uint32_t *disabled)
+{
+	struct bmi_drv_data_t *data = BMI_GET_DATA(s);
+	*enabled = data->enabled_activities;
+	*disabled = data->disabled_activities;
+	return EC_RES_SUCCESS;
+}
diff --git a/driver/accelgyro_bmi_common.h b/driver/accelgyro_bmi_common.h
deleted file mode 100644
index 8073cb1674..0000000000
--- a/driver/accelgyro_bmi_common.h
+++ /dev/null
@@ -1,349 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* BMI accelerometer and gyro common definitions for Chrome EC */
-
-#ifndef __CROS_EC_ACCELGYRO_BMI_COMMON_H
-#define __CROS_EC_ACCELGYRO_BMI_COMMON_H
-
-#include "accelgyro.h"
-#include "driver/accelgyro_bmi160.h"
-#include "driver/accelgyro_bmi260.h"
-#include "mag_bmm150.h"
-
-#define BMI_CONF_REG(_sensor)      (0x40 + 2 * (_sensor))
-#define BMI_RANGE_REG(_sensor)     (0x41 + 2 * (_sensor))
-
-#define BMI_ODR_MASK         0x0F
-/* odr = 100 / (1 << (8 - reg)) , within limit */
-#define BMI_ODR_0_78HZ       0x01
-#define BMI_ODR_100HZ        0x08
-
-#define BMI_REG_TO_ODR(_regval) \
-	((_regval) < BMI_ODR_100HZ ? 100000 / (1 << (8 - (_regval))) : \
-					100000 * (1 << ((_regval) - 8)))
-#define BMI_ODR_TO_REG(_odr) \
-	((_odr) < 100000 ? (__builtin_clz(100000 / ((_odr) + 1)) - 24) : \
-			   (39 - __builtin_clz((_odr) / 100000)))
-
-enum fifo_header {
-	BMI_FH_EMPTY = 0x80,
-	BMI_FH_SKIP = 0x40,
-	BMI_FH_TIME = 0x44,
-	BMI_FH_CONFIG = 0x48
-};
-
-#define BMI_FH_MODE_MASK     0xc0
-#define BMI_FH_PARM_OFFSET       2
-#define BMI_FH_PARM_MASK         (0x7 << BMI_FH_PARM_OFFSET)
-#define BMI_FH_EXT_MASK      0x03
-
-/* Sensor resolution in number of bits. This sensor has fixed resolution. */
-#define BMI_RESOLUTION      16
-/* Min and Max sampling frequency in mHz */
-#define BMI_ACCEL_MIN_FREQ 12500
-#define BMI_ACCEL_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(1600000, 100000)
-#define BMI_GYRO_MIN_FREQ  25000
-#define BMI_GYRO_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(3200000, 100000)
-
-enum bmi_running_mode {
-	STANDARD_UI_9DOF_FIFO          = 0,
-	STANDARD_UI_IMU_FIFO           = 1,
-	STANDARD_UI_IMU                = 2,
-	STANDARD_UI_ADVANCEPOWERSAVE   = 3,
-	ACCEL_PEDOMETER                = 4,
-	APPLICATION_HEAD_TRACKING      = 5,
-	APPLICATION_NAVIGATION         = 6,
-	APPLICATION_REMOTE_CONTROL     = 7,
-	APPLICATION_INDOOR_NAVIGATION  = 8,
-};
-
-#define BMI_FLAG_SEC_I2C_ENABLED    BIT(0)
-#define BMI_FIFO_FLAG_OFFSET        4
-#define BMI_FIFO_ALL_MASK           7
-
-struct bmi_drv_data_t {
-	struct accelgyro_saved_data_t saved_data[3];
-	uint8_t              flags;
-	uint8_t              enabled_activities;
-	uint8_t              disabled_activities;
-#ifdef CONFIG_MAG_BMI_BMM150
-	struct bmm150_private_data compass;
-#endif
-#ifdef CONFIG_BMI_ORIENTATION_SENSOR
-	uint8_t raw_orientation;
-	enum motionsensor_orientation orientation;
-	enum motionsensor_orientation last_orientation;
-#endif
-
-};
-
-#define BMI_GET_DATA(_s) \
-	((struct bmi_drv_data_t *)(_s)->drv_data)
-#define BMI_GET_SAVED_DATA(_s) \
-	(&BMI_GET_DATA(_s)->saved_data[(_s)->type])
-
-#ifdef CONFIG_BMI_ORIENTATION_SENSOR
-#define ORIENTATION_CHANGED(_sensor) \
-	(BMI_GET_DATA(_sensor)->orientation != \
-	BMI_GET_DATA(_sensor)->last_orientation)
-
-#define GET_ORIENTATION(_sensor) \
-	(BMI_GET_DATA(_sensor)->orientation)
-
-#define SET_ORIENTATION(_sensor, _val) \
-	(BMI_GET_DATA(_sensor)->orientation = _val)
-
-#define SET_ORIENTATION_UPDATED(_sensor) \
-	(BMI_GET_DATA(_sensor)->last_orientation = \
-	BMI_GET_DATA(_sensor)->orientation)
-#endif
-
-#define BMI_ACC_DATA(v) (BMI160_ACC_X_L_G + \
-	(v) * (BMI260_ACC_X_L_G - BMI160_ACC_X_L_G))
-#define BMI_GYR_DATA(v) (BMI160_GYR_X_L_G + \
-	(v) * (BMI260_GYR_X_L_G - BMI160_GYR_X_L_G))
-#define BMI_AUX_DATA(v) (BMI160_MAG_X_L_G + \
-	(v) * (BMI260_AUX_X_L_G - BMI160_MAG_X_L_G))
-
-#define BMI_FIFO_CONFIG_0(v) (BMI160_FIFO_CONFIG_0 + \
-	(v) * (BMI260_FIFO_CONFIG_0 - BMI160_FIFO_CONFIG_0))
-#define BMI_FIFO_CONFIG_1(v) (BMI160_FIFO_CONFIG_1 + \
-	(v) * (BMI260_FIFO_CONFIG_1 - BMI160_FIFO_CONFIG_1))
-#define BMI_FIFO_SENSOR_EN(v, _sensor) (BMI160_FIFO_SENSOR_EN(_sensor) + \
-	(v) * (BMI260_FIFO_SENSOR_EN(_sensor) - BMI160_FIFO_SENSOR_EN(_sensor)))
-
-#define BMI_TEMPERATURE_0(v) (BMI160_TEMPERATURE_0 + \
-	(v) * (BMI260_TEMPERATURE_0 - BMI160_TEMPERATURE_0))
-#define BMI_INVALID_TEMP     0x8000
-
-#define BMI_STATUS(v) (BMI160_STATUS + \
-	(v) * (BMI260_STATUS - BMI160_STATUS))
-#define BMI_DRDY_OFF(_sensor)   (7 - (_sensor))
-#define BMI_DRDY_MASK(_sensor)  (1 << BMI160_DRDY_OFF(_sensor))
-
-#define BMI_OFFSET_ACC70(v) (BMI160_OFFSET_ACC70 + \
-	(v) * (BMI260_OFFSET_ACC70 - BMI160_OFFSET_ACC70))
-#define BMI_OFFSET_GYR70(v) (BMI160_OFFSET_GYR70 + \
-	(v) * (BMI260_OFFSET_GYR70 - BMI160_OFFSET_GYR70))
-/*
- * There is some bits in this register that differ between BMI160 and BMI260
- * Only use this macro for gyro offset 9:8 (BMI_OFFSET_EN_GYR98 5:0).
- */
-#define BMI_OFFSET_EN_GYR98(v) (BMI160_OFFSET_EN_GYR98 + \
-	(v) * (BMI260_OFFSET_EN_GYR98 - BMI160_OFFSET_EN_GYR98))
-#define BMI_OFFSET_GYR98_MASK     (BIT(6) - 1)
-#define BMI_OFFSET_ACC_MULTI_MG   (3900 * 1024)
-#define BMI_OFFSET_ACC_DIV_MG     1000000
-#define BMI_OFFSET_GYRO_MULTI_MDS (61 * 1024)
-#define BMI_OFFSET_GYRO_DIV_MDS   1000
-
-#define BMI_FIFO_LENGTH_0(v) (BMI160_FIFO_LENGTH_0 + \
-	(v) * (BMI260_FIFO_LENGTH_0 - BMI160_FIFO_LENGTH_0))
-#define BMI_FIFO_LENGTH_MASK(v) (BMI160_FIFO_LENGTH_MASK + \
-	(v) * (BMI260_FIFO_LENGTH_MASK - BMI160_FIFO_LENGTH_MASK))
-#define BMI_FIFO_DATA(v) (BMI160_FIFO_DATA + \
-	(v) * (BMI260_FIFO_DATA - BMI160_FIFO_DATA))
-
-#define BMI_CMD_REG(v) (BMI160_CMD_REG + \
-	(v) * (BMI260_CMD_REG - BMI160_CMD_REG))
-#define BMI_CMD_FIFO_FLUSH 0xb0
-
-#define BMI_ACCEL_RMS_NOISE_100HZ(v) (BMI160_ACCEL_RMS_NOISE_100HZ + \
-	(v) * (BMI260_ACCEL_RMS_NOISE_100HZ - BMI160_ACCEL_RMS_NOISE_100HZ))
-#define BMI_ACCEL_100HZ 100
-
-/*
- * Struct for pairing an engineering value with the register value for a
- * parameter.
- */
-struct bmi_accel_param_pair {
-	int val; /* Value in engineering units. */
-	int reg_val; /* Corresponding register value. */
-};
-
-int bmi_get_xyz_reg(const struct motion_sensor_t *s);
-
-/**
- * @param type   Accel/Gyro
- * @param psize  Size of the table
- *
- * @return       Range table of the type.
- */
-const struct bmi_accel_param_pair *bmi_get_range_table(
-		const struct motion_sensor_t *s, int *psize);
-
-/**
- * @return reg value that matches the given engineering value passed in.
- * The round_up flag is used to specify whether to round up or down.
- * Note, this function always returns a valid reg value. If the request is
- * outside the range of values, it returns the closest valid reg value.
- */
-int bmi_get_reg_val(const int eng_val, const int round_up,
-		    const struct bmi_accel_param_pair *pairs,
-		    const int size);
-
-/**
- * @return engineering value that matches the given reg val
- */
-int bmi_get_engineering_val(const int reg_val,
-			    const struct bmi_accel_param_pair *pairs,
-			    const int size);
-
-#ifdef CONFIG_SPI_ACCEL_PORT
-int bmi_spi_raw_read(const int addr, const uint8_t reg,
-		     uint8_t *data, const int len);
-#endif
-
-/**
- * Read 8bit register from accelerometer.
- */
-int bmi_read8(const int port, const uint16_t i2c_spi_addr_flags,
-	      const int reg, int *data_ptr);
-
-/**
- * Write 8bit register from accelerometer.
- */
-int bmi_write8(const int port, const uint16_t i2c_spi_addr_flags,
-	       const int reg, int data);
-
-/**
- * Read 16bit register from accelerometer.
- */
-int bmi_read16(const int port, const uint16_t i2c_spi_addr_flags,
-	       const uint8_t reg, int *data_ptr);
-
-/**
- * Write 16bit register from accelerometer.
- */
-int bmi_write16(const int port, const uint16_t i2c_spi_addr_flags,
-		const int reg, int data);
-
-/**
- * Read 32bit register from accelerometer.
- */
-int bmi_read32(const int port, const uint16_t i2c_spi_addr_flags,
-	       const uint8_t reg, int *data_ptr);
-
-/**
- * Read n bytes from accelerometer.
- */
-int bmi_read_n(const int port, const uint16_t i2c_spi_addr_flags,
-	       const uint8_t reg, uint8_t *data_ptr, const int len);
-
-/**
- * Write n bytes from accelerometer.
- */
-int bmi_write_n(const int port, const uint16_t i2c_spi_addr_flags,
-		const uint8_t reg, const uint8_t *data_ptr, const int len);
-
-/*
- * Enable/Disable specific bit set of a 8-bit reg.
- */
-int bmi_enable_reg8(const struct motion_sensor_t *s,
-		    int reg, uint8_t bits, int enable);
-
-/*
- * Set specific bit set to certain value of a 8-bit reg.
- */
-int bmi_set_reg8(const struct motion_sensor_t *s, int reg,
-		 uint8_t bits, int mask);
-
-/*
- * @s: base sensor.
- * @v: output vector.
- * @input: 6-bits array input.
- */
-void bmi_normalize(const struct motion_sensor_t *s, intv3_t v, uint8_t *input);
-
-/*
- * Decode the header from the fifo.
- * Return 0 if we need further processing.
- * Sensor mutex must be held during processing, to protect the fifos.
- *
- * @accel: base sensor
- * @hdr: the header to decode
- * @last_ts: the last timestamp of fifo interrupt.
- * @bp: current pointer in the buffer, updated when processing the header.
- * @ep: pointer to the end of the valid data in the buffer.
- */
-int bmi_decode_header(struct motion_sensor_t *accel,
-		      enum fifo_header hdr, uint32_t last_ts,
-		      uint8_t **bp, uint8_t *ep);
-/**
- * Retrieve hardware FIFO from sensor,
- * - put data in Sensor Hub fifo.
- * - update sensor raw_xyz vector with the last information.
- * We put raw data in hub fifo and process data from there.
- * @s: Pointer to sensor data.
- * @last_ts: The last timestamp of fifo interrupt.
- *
- * Read only up to  bmi_buffer. If more reads are needed, we will be called
- * again by the interrupt routine.
- *
- * NOTE: If a new driver supports this function, be sure to add a check
- * for spoof_mode in order to load the sensor stack with the spoofed
- * data.  See accelgyro_bmi260.c::load_fifo for an example.
- */
-int bmi_load_fifo(struct motion_sensor_t *s, uint32_t last_ts);
-
-int bmi_set_range(const struct motion_sensor_t *s, int range, int rnd);
-
-int bmi_get_range(const struct motion_sensor_t *s);
-
-int bmi_get_data_rate(const struct motion_sensor_t *s);
-
-
-int bmi_get_offset(const struct motion_sensor_t *s,
-		   int16_t *offset, int16_t *temp);
-
-int bmi_get_resolution(const struct motion_sensor_t *s);
-
-#ifdef CONFIG_BODY_DETECTION
-int bmi_get_rms_noise(const struct motion_sensor_t *s);
-#endif
-
-int bmi_set_scale(const struct motion_sensor_t *s,
-		  const uint16_t *scale, int16_t temp);
-
-int bmi_get_scale(const struct motion_sensor_t *s,
-		  uint16_t *scale, int16_t *temp);
-
-/* Start/Stop the FIFO collecting events */
-int bmi_enable_fifo(const struct motion_sensor_t *s, int enable);
-
-/* Read the xyz data of accel/gyro */
-int bmi_read(const struct motion_sensor_t *s, intv3_t v);
-
-/* Read temperature of sensor s */
-int bmi_read_temp(const struct motion_sensor_t *s, int *temp_ptr);
-
-/* Read temperature of sensor idx */
-int bmi_get_sensor_temp(int idx, int *temp_ptr);
-
-/*
- * Get the normalized rate according to input rate and input rnd
- * @rate: input rate
- * @rnd: round up
- * @normalized_rate_ptr: normalized rate pointer for output
- * @reg_val_ptr: pointer to the actual register value of normalized rate for
- *               output.
- */
-int bmi_get_normalized_rate(const struct motion_sensor_t *s, int rate, int rnd,
-			    int *normalized_rate_ptr, uint8_t *reg_val_ptr);
-
-/* Get the accelerometer offset */
-void bmi_accel_get_offset(const struct motion_sensor_t *accel, intv3_t v);
-
-/* Get the gyroscope offset */
-void bmi_gyro_get_offset(const struct motion_sensor_t *gyro, intv3_t v);
-
-/* Set the accelerometer offset */
-void bmi_set_accel_offset(const struct motion_sensor_t *accel, intv3_t v);
-
-/* Set the gyroscope offset */
-void bmi_set_gyro_offset(const struct motion_sensor_t *gyro, intv3_t v,
-			 int *val98_ptr);
-
-#endif /* __CROS_EC_ACCELGYRO_BMI_COMMON_H */
diff --git a/driver/accelgyro_icm42607.c b/driver/accelgyro_icm42607.c
new file mode 100644
index 0000000000..1904782797
--- /dev/null
+++ b/driver/accelgyro_icm42607.c
@@ -0,0 +1,1277 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * ICM-42607 accelerometer and gyroscope module for Chrome EC
+ * 3D digital accelerometer & 3D digital gyroscope
+ */
+
+#include "accelgyro.h"
+#include "builtin/endian.h"
+#include "console.h"
+#include "driver/accelgyro_icm42607.h"
+#include "driver/accelgyro_icm_common.h"
+#include "hwtimer.h"
+#include "i2c.h"
+#include "math_util.h"
+#include "motion_sense.h"
+#include "motion_sense_fifo.h"
+#include "spi.h"
+#include "task.h"
+#include "timer.h"
+#include "util.h"
+
+#ifdef CONFIG_ACCELGYRO_ICM42607_INT_EVENT
+#define ACCELGYRO_ICM42607_INT_ENABLE
+#endif
+
+#define CPUTS(outstr) cputs(CC_ACCEL, outstr)
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args)
+
+STATIC_IF(ACCELGYRO_ICM42607_INT_ENABLE)
+volatile uint32_t last_interrupt_timestamp;
+
+static int icm_switch_on_mclk(const struct motion_sensor_t *s)
+{
+	int val;
+	int i, ret;
+
+	ret = icm_field_update8(s, ICM42607_REG_PWR_MGMT0, ICM42607_IDLE,
+				ICM42607_IDLE);
+	if (ret)
+		return ret;
+
+	/* Check if MCLK is ready */
+	for (i = 0; i < 10; ++i) {
+		ret = icm_read8(s, ICM42607_REG_MCLK_RDY, &val);
+		if (ret)
+			return ret;
+
+		if (val & ICM42607_MCLK_RDY)
+			return EC_SUCCESS;
+	}
+
+	return EC_ERROR_HW_INTERNAL;
+}
+
+static int icm_switch_off_mclk(const struct motion_sensor_t *s)
+{
+	return icm_field_update8(s, ICM42607_REG_PWR_MGMT0, ICM42607_IDLE, 0);
+}
+
+static int icm_read_mclk_reg(const struct motion_sensor_t *s, const int reg,
+			     int *buf)
+{
+	const int blk_sel = (reg & 0xFF00) >> 8;
+	const int val = reg & 0x00FF;
+	int ret;
+
+	/* optimize by changing BLK_SEL only if not 0 */
+	if (blk_sel) {
+		ret = icm_write8(s, ICM42607_REG_BLK_SEL_R, blk_sel);
+		if (ret)
+			return ret;
+	}
+
+	ret = icm_write8(s, ICM42607_REG_MADDR_R, val);
+	if (ret)
+		return ret;
+
+	udelay(10);
+
+	ret = icm_read8(s, ICM42607_REG_M_R, buf);
+	if (ret)
+		return ret;
+
+	udelay(10);
+
+	if (blk_sel) {
+		ret = icm_write8(s, ICM42607_REG_BLK_SEL_R, 0);
+		if (ret)
+			return ret;
+	}
+
+	return EC_SUCCESS;
+}
+
+static int icm_write_mclk_reg(const struct motion_sensor_t *s, const int reg,
+			      const int buf)
+{
+	const int blk_sel = (reg & 0xFF00) >> 8;
+	const int val = reg & 0x00FF;
+	int ret;
+
+	/* optimize by changing BLK_SEL only if not 0 */
+	if (blk_sel) {
+		ret = icm_write8(s, ICM42607_REG_BLK_SEL_W, blk_sel);
+		if (ret)
+			return ret;
+	}
+
+	ret = icm_write8(s, ICM42607_REG_MADDR_W, val);
+	if (ret)
+		return ret;
+
+	ret = icm_write8(s, ICM42607_REG_M_W, buf);
+	if (ret)
+		return ret;
+
+	udelay(10);
+
+	if (blk_sel) {
+		ret = icm_write8(s, ICM42607_REG_BLK_SEL_W, 0);
+		if (ret)
+			return ret;
+	}
+
+	return EC_SUCCESS;
+}
+
+static int icm_field_update_mclk_reg(const struct motion_sensor_t *s,
+				     const int reg, const uint8_t field_mask,
+				     const uint8_t set_value)
+{
+	int val, ret;
+
+	ret = icm_read_mclk_reg(s, reg, &val);
+	if (ret)
+		return ret;
+
+	val = (val & ~field_mask) | set_value;
+
+	return icm_write_mclk_reg(s, reg, val);
+}
+
+static int icm42607_normalize(const struct motion_sensor_t *s, intv3_t v,
+			      const uint8_t *raw)
+{
+	struct accelgyro_saved_data_t *data = ICM_GET_SAVED_DATA(s);
+	int i;
+
+	/* sensor data is configured as little-endian */
+	v[X] = (int16_t)UINT16_FROM_BYTE_ARRAY_LE(raw, 0);
+	v[Y] = (int16_t)UINT16_FROM_BYTE_ARRAY_LE(raw, 2);
+	v[Z] = (int16_t)UINT16_FROM_BYTE_ARRAY_LE(raw, 4);
+
+	/* check if data is valid */
+	if (v[X] == ICM42607_INVALID_DATA && v[Y] == ICM42607_INVALID_DATA &&
+	    v[Z] == ICM42607_INVALID_DATA) {
+		return EC_ERROR_INVAL;
+	}
+
+	rotate(v, *s->rot_standard_ref, v);
+
+	for (i = X; i <= Z; i++)
+		v[i] = SENSOR_APPLY_SCALE(v[i], data->scale[i]);
+
+	return EC_SUCCESS;
+}
+
+static int icm42607_check_sensor_stabilized(const struct motion_sensor_t *s,
+					    uint32_t ts)
+{
+	int32_t rem;
+
+	rem = icm_get_sensor_stabilized(s, ts);
+	if (rem == 0)
+		return EC_SUCCESS;
+	if (rem > 0)
+		return EC_ERROR_BUSY;
+
+	/* rem < 0: reset check since ts has passed stabilize_ts */
+	icm_reset_stabilize_ts(s);
+	return EC_SUCCESS;
+}
+
+static int __maybe_unused icm42607_flush_fifo(const struct motion_sensor_t *s)
+{
+	int i, val, ret;
+
+	ret = icm_write8(s, ICM42607_REG_SIGNAL_PATH_RESET,
+			 ICM42607_FIFO_FLUSH);
+	if (ret)
+		return ret;
+
+	udelay(10);
+
+	for (i = 0; i < 10; ++i) {
+		ret = icm_read8(s, ICM42607_REG_SIGNAL_PATH_RESET, &val);
+		if (ret)
+			return ret;
+
+		if (!(val & ICM42607_FIFO_FLUSH))
+			return EC_SUCCESS;
+
+		udelay(1);
+	}
+
+	return EC_ERROR_HW_INTERNAL;
+}
+
+/* use FIFO threshold interrupt on INT1 */
+#define ICM42607_FIFO_INT_EN ICM42607_FIFO_THS_INT1_EN
+#define ICM42607_FIFO_INT_STATUS ICM42607_FIFO_THS_INT
+
+static int __maybe_unused icm42607_enable_fifo(const struct motion_sensor_t *s,
+					       int enable)
+{
+	int ret;
+
+	if (enable) {
+		/* enable FIFO interrupts */
+		ret = icm_field_update8(s, ICM42607_REG_INT_SOURCE0,
+					ICM42607_FIFO_INT_EN,
+					ICM42607_FIFO_INT_EN);
+		if (ret)
+			return ret;
+
+		/* enable FIFO in streaming mode */
+		ret = icm_write8(s, ICM42607_REG_FIFO_CONFIG1,
+				 ICM42607_FIFO_MODE_STREAM);
+		if (ret)
+			return ret;
+	} else {
+		/* disable FIFO interrupts */
+		ret = icm_field_update8(s, ICM42607_REG_INT_SOURCE0,
+					ICM42607_FIFO_INT_EN, 0);
+		if (ret)
+			return ret;
+
+		/* set FIFO in bypass mode */
+		ret = icm_write8(s, ICM42607_REG_FIFO_CONFIG1,
+				 ICM42607_FIFO_BYPASS);
+		if (ret)
+			return ret;
+
+		/* flush FIFO data */
+		ret = icm42607_flush_fifo(s);
+		if (ret)
+			return ret;
+	}
+
+	return EC_SUCCESS;
+}
+
+static int __maybe_unused icm42607_config_fifo(const struct motion_sensor_t *s,
+					       int enable)
+{
+	struct icm_drv_data_t *st = ICM_GET_DATA(s);
+	int val;
+	uint8_t old_fifo_en, fifo_en;
+	int ret;
+
+	mutex_lock(s->mutex);
+
+	/* compute new FIFO enable bits and update FIFO config */
+	fifo_en = st->fifo_en;
+	if (enable)
+		fifo_en |= BIT(s->type);
+	else
+		fifo_en &= ~BIT(s->type);
+
+	val = ICM42607_FIFO_WM_GT_TH;
+	if (fifo_en & BIT(MOTIONSENSE_TYPE_ACCEL))
+		val |= ICM42607_FIFO_ACCEL_EN;
+	if (fifo_en & BIT(MOTIONSENSE_TYPE_GYRO))
+		val |= ICM42607_FIFO_GYRO_EN;
+
+	ret = icm_switch_on_mclk(s);
+	if (ret)
+		goto out_unlock;
+
+	ret = icm_write_mclk_reg(s, ICM42607_MREG_FIFO_CONFIG5, val);
+	if (ret)
+		goto out_unlock;
+
+	ret = icm_switch_off_mclk(s);
+	if (ret)
+		goto out_unlock;
+
+	old_fifo_en = st->fifo_en;
+	st->fifo_en = fifo_en;
+
+	if (!old_fifo_en && st->fifo_en) {
+		/* 1st sensor enabled => turn FIFO on */
+		ret = icm42607_enable_fifo(s, 1);
+		if (ret != EC_SUCCESS)
+			goto out_unlock;
+	} else if (old_fifo_en && !st->fifo_en) {
+		/* last sensor disabled => turn FIFO off */
+		ret = icm42607_enable_fifo(s, 0);
+		if (ret != EC_SUCCESS)
+			goto out_unlock;
+	}
+
+out_unlock:
+	mutex_unlock(s->mutex);
+	return ret;
+}
+
+static void __maybe_unused icm42607_push_fifo_data(struct motion_sensor_t *s,
+						   const uint8_t *raw,
+						   uint32_t ts)
+{
+	struct ec_response_motion_sensor_data vect;
+	int *v = s->raw_xyz;
+
+	if (icm42607_normalize(s, v, raw) != EC_SUCCESS)
+		return;
+
+	if (IS_ENABLED(CONFIG_ACCEL_SPOOF_MODE) &&
+	    s->flags & MOTIONSENSE_FLAG_IN_SPOOF_MODE)
+		v = s->spoof_xyz;
+	if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
+		vect.data[X] = v[X];
+		vect.data[Y] = v[Y];
+		vect.data[Z] = v[Z];
+		vect.flags = 0;
+		vect.sensor_num = s - motion_sensors;
+		motion_sense_fifo_stage_data(&vect, s, 3, ts);
+	} else {
+		motion_sense_push_raw_xyz(s);
+	}
+}
+
+static int __maybe_unused icm42607_load_fifo(struct motion_sensor_t *s,
+					     uint32_t ts)
+{
+	struct icm_drv_data_t *st = ICM_GET_DATA(s);
+	int count, i, size;
+	const uint8_t *accel, *gyro;
+	int ret;
+
+	ret = icm_read16(s, ICM42607_REG_FIFO_COUNT, &count);
+	if (ret != EC_SUCCESS)
+		return ret;
+
+	if (count <= 0)
+		return EC_ERROR_INVAL;
+
+	/* flush FIFO if buffer is not large enough */
+	if (count > ICM_FIFO_BUFFER) {
+		CPRINTS("It should not happen, the EC is too slow for the ODR");
+		/* flush FIFO data */
+		ret = icm42607_flush_fifo(s);
+		if (ret)
+			return ret;
+
+		return EC_ERROR_OVERFLOW;
+	}
+
+	ret = icm_read_n(s, ICM42607_REG_FIFO_DATA, st->fifo_buffer, count);
+	if (ret != EC_SUCCESS)
+		return ret;
+
+	for (i = 0; i < count; i += size) {
+		size = icm_fifo_decode_packet(&st->fifo_buffer[i], &accel,
+					      &gyro);
+		/* exit if error or FIFO is empty */
+		if (size <= 0)
+			return -size;
+		if (accel != NULL) {
+			ret = icm42607_check_sensor_stabilized(s, ts);
+			if (ret == EC_SUCCESS)
+				icm42607_push_fifo_data(s, accel, ts);
+		}
+		if (gyro != NULL) {
+			ret = icm42607_check_sensor_stabilized(s + 1, ts);
+			if (ret == EC_SUCCESS)
+				icm42607_push_fifo_data(s + 1, gyro, ts);
+		}
+	}
+
+	return EC_SUCCESS;
+}
+
+#ifdef ACCELGYRO_ICM42607_INT_ENABLE
+
+/**
+ * icm42607_interrupt - called when the sensor activates the interrupt line.
+ *
+ * This is a "top half" interrupt handler, it just asks motion sense ask
+ * to schedule the "bottom half", ->icm42607_irq_handler().
+ */
+void icm42607_interrupt(enum gpio_signal signal)
+{
+	last_interrupt_timestamp = __hw_clock_source_read();
+
+	task_set_event(TASK_ID_MOTIONSENSE,
+		       CONFIG_ACCELGYRO_ICM42607_INT_EVENT);
+}
+
+/**
+ * icm42607_irq_handler - bottom half of the interrupt stack.
+ * Ran from the motion_sense task, finds the events that raised the interrupt.
+ */
+static int icm42607_irq_handler(struct motion_sensor_t *s, uint32_t *event)
+{
+	int status;
+	int ret;
+
+	if ((s->type != MOTIONSENSE_TYPE_ACCEL) ||
+	    (!(*event & CONFIG_ACCELGYRO_ICM42607_INT_EVENT)))
+		return EC_ERROR_NOT_HANDLED;
+
+	mutex_lock(s->mutex);
+
+	/* read and clear interrupt status */
+	ret = icm_read8(s, ICM42607_REG_INT_STATUS, &status);
+	if (ret != EC_SUCCESS)
+		goto out_unlock;
+
+	if (status & ICM42607_FIFO_INT_STATUS) {
+		ret = icm42607_load_fifo(s, last_interrupt_timestamp);
+		if (IS_ENABLED(CONFIG_ACCEL_FIFO) && (ret == EC_SUCCESS))
+			motion_sense_fifo_commit_data();
+	}
+
+out_unlock:
+	mutex_unlock(s->mutex);
+	return ret;
+}
+
+static int icm42607_config_interrupt(const struct motion_sensor_t *s)
+{
+	struct icm_drv_data_t *st = ICM_GET_DATA(s);
+	int val, mask;
+
+	/* configure INT1 pin: push-pull active low */
+	RETURN_ERROR(icm_write8(s, ICM42607_REG_INT_CONFIG,
+				ICM42607_INT1_PUSH_PULL));
+
+	/* configure FIFO in little endian */
+	mask = ICM42607_FIFO_COUNT_ENDIAN | ICM42607_SENSOR_DATA_ENDIAN;
+	RETURN_ERROR(icm_field_update8(s, ICM42607_REG_INTF_CONFIG0, mask, 0));
+
+	RETURN_ERROR(icm_switch_on_mclk(s));
+
+	/*
+	 * configure FIFO:
+	 * - enable continuous watermark interrupt
+	 * - disable all FIFO en bits
+	 */
+	val = ICM42607_FIFO_WM_GT_TH;
+	RETURN_ERROR(icm_write_mclk_reg(s, ICM42607_MREG_FIFO_CONFIG5, val));
+
+	RETURN_ERROR(icm_switch_off_mclk(s));
+
+	/* clear internal FIFO enable bits tracking */
+	st->fifo_en = 0;
+
+	/* set FIFO watermark to 1 data packet (8 bytes) */
+	RETURN_ERROR(icm_write16(s, ICM42607_REG_FIFO_WM, 8));
+
+	return EC_SUCCESS;
+}
+
+#endif /* ACCELGYRO_ICM42607_INT_ENABLE */
+
+static int icm42607_enable_sensor(const struct motion_sensor_t *s, int enable)
+{
+	uint32_t delay, stop_delay;
+	int32_t rem;
+	uint8_t mask;
+	int val;
+	int ret;
+
+	switch (s->type) {
+	case MOTIONSENSE_TYPE_ACCEL:
+		mask = ICM42607_ACCEL_MODE_MASK;
+		if (enable) {
+			delay = ICM42607_ACCEL_START_TIME;
+			stop_delay = ICM42607_ACCEL_STOP_TIME;
+			val = ICM42607_ACCEL_MODE(ICM42607_MODE_LOW_POWER);
+		} else {
+			delay = ICM42607_ACCEL_STOP_TIME;
+			val = ICM42607_ACCEL_MODE(ICM42607_MODE_OFF);
+		}
+		break;
+	case MOTIONSENSE_TYPE_GYRO:
+		mask = ICM42607_GYRO_MODE_MASK;
+		if (enable) {
+			delay = ICM42607_GYRO_START_TIME;
+			stop_delay = ICM42607_GYRO_STOP_TIME;
+			val = ICM42607_GYRO_MODE(ICM42607_MODE_LOW_NOISE);
+		} else {
+			delay = ICM42607_GYRO_STOP_TIME;
+			val = ICM42607_GYRO_MODE(ICM42607_MODE_OFF);
+		}
+		break;
+	default:
+		return EC_ERROR_INVAL;
+	}
+
+	/* check stop delay and sleep if required */
+	if (enable) {
+		rem = icm_get_sensor_stabilized(s, __hw_clock_source_read());
+		/* rem > stop_delay means counter rollover */
+		if (rem > 0 && rem <= stop_delay)
+			usleep(rem);
+	}
+
+	mutex_lock(s->mutex);
+
+	ret = icm_field_update8(s, ICM42607_REG_PWR_MGMT0, mask, val);
+	if (ret == EC_SUCCESS) {
+		icm_set_stabilize_ts(s, delay);
+		/* when turning sensor on block any register write for 200 us */
+		if (enable)
+			usleep(200);
+	}
+
+	mutex_unlock(s->mutex);
+
+	return ret;
+}
+
+static int icm42607_set_data_rate(const struct motion_sensor_t *s, int rate,
+				  int rnd)
+{
+	struct accelgyro_saved_data_t *data = ICM_GET_SAVED_DATA(s);
+	int reg, reg2, ret, reg_val, reg2_val;
+	int normalized_rate;
+	int max_rate, min_rate;
+
+	switch (s->type) {
+	case MOTIONSENSE_TYPE_ACCEL:
+		reg = ICM42607_REG_ACCEL_CONFIG0;
+		reg2 = ICM42607_REG_ACCEL_CONFIG1;
+		min_rate = ICM42607_ACCEL_MIN_FREQ;
+		max_rate = ICM42607_ACCEL_MAX_FREQ;
+		break;
+	case MOTIONSENSE_TYPE_GYRO:
+		reg = ICM42607_REG_GYRO_CONFIG0;
+		reg2 = ICM42607_REG_GYRO_CONFIG1;
+		min_rate = ICM42607_GYRO_MIN_FREQ;
+		max_rate = ICM42607_GYRO_MAX_FREQ;
+		break;
+	default:
+		return EC_RES_INVALID_PARAM;
+	}
+
+	if (rate == 0) {
+		/* disable data in FIFO */
+		if (IS_ENABLED(ACCELGYRO_ICM42607_INT_ENABLE))
+			icm42607_config_fifo(s, 0);
+		/* disable sensor */
+		ret = icm42607_enable_sensor(s, 0);
+		data->odr = 0;
+		return ret;
+	}
+
+	/* normalize the rate */
+	reg_val = ICM42607_ODR_TO_REG(rate);
+	normalized_rate = ICM42607_REG_TO_ODR(reg_val);
+
+	/* round up the rate */
+	if (rnd && (normalized_rate < rate)) {
+		reg_val = ICM42607_ODR_REG_UP(reg_val);
+		normalized_rate = ICM42607_REG_TO_ODR(reg_val);
+	}
+
+	if (rate > 0) {
+		if ((normalized_rate < min_rate) ||
+		    (normalized_rate > max_rate))
+			return EC_RES_INVALID_PARAM;
+	}
+
+	reg2_val = ICM42607_ODR_TO_FILT_BW(reg_val);
+
+	mutex_lock(s->mutex);
+
+	/* update filter bandwidth */
+	ret = icm_field_update8(s, reg2, ICM42607_UI_FILT_BW_MASK,
+				ICM42607_UI_FILT_BW_SET(reg2_val));
+	if (ret != EC_SUCCESS)
+		goto out_unlock;
+
+	/* update ODR */
+	ret = icm_field_update8(s, reg, ICM42607_ODR_MASK,
+				ICM42607_ODR(reg_val));
+	if (ret != EC_SUCCESS)
+		goto out_unlock;
+
+	mutex_unlock(s->mutex);
+
+	if (data->odr == 0) {
+		/* enable sensor */
+		ret = icm42607_enable_sensor(s, 1);
+		if (ret)
+			return ret;
+		/* enable data in FIFO */
+		if (IS_ENABLED(ACCELGYRO_ICM42607_INT_ENABLE))
+			icm42607_config_fifo(s, 1);
+	}
+
+	data->odr = normalized_rate;
+
+	return EC_SUCCESS;
+
+out_unlock:
+	mutex_unlock(s->mutex);
+	return ret;
+}
+
+static int icm42607_set_range(struct motion_sensor_t *s, int range, int rnd)
+{
+	int reg, ret, reg_val;
+	int newrange;
+
+	switch (s->type) {
+	case MOTIONSENSE_TYPE_ACCEL:
+		reg = ICM42607_REG_ACCEL_CONFIG0;
+		reg_val = ICM42607_ACCEL_FS_TO_REG(range);
+		newrange = ICM42607_ACCEL_REG_TO_FS(reg_val);
+
+		if (rnd && (newrange < range) && (reg_val > 0)) {
+			reg_val--;
+			newrange = ICM42607_ACCEL_REG_TO_FS(reg_val);
+		}
+
+		if (newrange > ICM42607_ACCEL_FS_MAX_VAL) {
+			newrange = ICM42607_ACCEL_FS_MAX_VAL;
+			reg_val = ICM42607_ACCEL_FS_TO_REG(range);
+		}
+
+		break;
+	case MOTIONSENSE_TYPE_GYRO:
+		reg = ICM42607_REG_GYRO_CONFIG0;
+		reg_val = ICM42607_GYRO_FS_TO_REG(range);
+		newrange = ICM42607_GYRO_REG_TO_FS(reg_val);
+
+		if (rnd && (newrange < range) && (reg_val > 0)) {
+			reg_val--;
+			newrange = ICM42607_GYRO_REG_TO_FS(reg_val);
+		}
+
+		if (newrange > ICM42607_GYRO_FS_MAX_VAL) {
+			newrange = ICM42607_GYRO_FS_MAX_VAL;
+			reg_val = ICM42607_GYRO_FS_TO_REG(newrange);
+		}
+
+		break;
+	default:
+		return EC_RES_INVALID_PARAM;
+	}
+
+	mutex_lock(s->mutex);
+
+	ret = icm_field_update8(s, reg, ICM42607_FS_MASK,
+				ICM42607_FS_SEL(reg_val));
+	if (ret == EC_SUCCESS)
+		s->current_range = newrange;
+
+	mutex_unlock(s->mutex);
+
+	return ret;
+}
+
+static int icm42607_get_hw_offset(const struct motion_sensor_t *s,
+				  intv3_t offset)
+{
+	uint8_t raw[5];
+	int i, reg, val, ret;
+
+	switch (s->type) {
+	case MOTIONSENSE_TYPE_ACCEL:
+		reg = ICM42607_MREG_OFFSET_USER4;
+		break;
+	case MOTIONSENSE_TYPE_GYRO:
+		reg = ICM42607_MREG_OFFSET_USER0;
+		break;
+	default:
+		return EC_ERROR_INVAL;
+	}
+
+	mutex_lock(s->mutex);
+
+	ret = icm_switch_on_mclk(s);
+	if (ret != EC_SUCCESS)
+		goto out_unlock;
+
+	for (i = 0; i < sizeof(raw); ++i) {
+		ret = icm_read_mclk_reg(s, reg + i, &val);
+		if (ret != EC_SUCCESS)
+			goto out_unlock;
+		raw[i] = val;
+	}
+
+	ret = icm_switch_off_mclk(s);
+	if (ret != EC_SUCCESS)
+		goto out_unlock;
+
+	mutex_unlock(s->mutex);
+
+	switch (s->type) {
+	case MOTIONSENSE_TYPE_ACCEL:
+		/*
+		 * raw[0]: Accel X[11:8] | gyro Z[11:8]
+		 * raw[1]: Accel X[7:0]
+		 * raw[2]: Accel Y[7:0]
+		 * raw[3]: Accel Z[11:8] | Accel Y[11:8]
+		 * raw[4]: Accel Z[7:0]
+		 */
+		offset[X] = (((int)raw[0] << 4) & ~GENMASK(7, 0)) | raw[1];
+		offset[Y] = (((int)raw[3] << 8) & ~GENMASK(7, 0)) | raw[2];
+		offset[Z] = (((int)raw[3] << 4) & ~GENMASK(7, 0)) | raw[4];
+		break;
+	case MOTIONSENSE_TYPE_GYRO:
+		/*
+		 * raw[0]: Gyro X[7:0]
+		 * raw[1]: Gyro Y[11:8] | Gyro X[11:8]
+		 * raw[2]: Gyro Y[7:0]
+		 * raw[3]: Gyro Z[7:0]
+		 * raw[4]: Accel X[11:8] | gyro Z[11:8]
+		 */
+		offset[X] = (((int)raw[1] << 8) & ~GENMASK(7, 0)) | raw[0];
+		offset[Y] = (((int)raw[1] << 4) & ~GENMASK(7, 0)) | raw[2];
+		offset[Z] = (((int)raw[4] << 8) & ~GENMASK(7, 0)) | raw[3];
+		break;
+	default:
+		return EC_ERROR_INVAL;
+	}
+
+	/* Extend sign-bit of 12 bits signed values */
+	for (i = X; i <= Z; ++i)
+		offset[i] = sign_extend(offset[i], 11);
+
+	return EC_SUCCESS;
+
+out_unlock:
+	mutex_unlock(s->mutex);
+	return ret;
+}
+
+static int icm42607_set_hw_offset(const struct motion_sensor_t *s,
+				  intv3_t offset)
+{
+	int i, val, ret;
+
+	/* value is 12 bits signed maximum */
+	for (i = X; i <= Z; ++i) {
+		if (offset[i] > 2047)
+			offset[i] = 2047;
+		else if (offset[i] < -2048)
+			offset[i] = -2048;
+	}
+
+	mutex_lock(s->mutex);
+
+	ret = icm_switch_on_mclk(s);
+	if (ret != EC_SUCCESS)
+		goto out_unlock;
+
+	switch (s->type) {
+	case MOTIONSENSE_TYPE_ACCEL:
+		/* Accel X[11:8] | gyro Z[11:8] */
+		val = (offset[X] >> 4) & GENMASK(7, 4);
+		ret = icm_field_update_mclk_reg(s, ICM42607_MREG_OFFSET_USER4,
+						GENMASK(7, 4), val);
+		if (ret != EC_SUCCESS)
+			goto out_unlock;
+
+		/* Accel X[7:0] */
+		val = offset[X] & GENMASK(7, 0);
+		ret = icm_write_mclk_reg(s, ICM42607_MREG_OFFSET_USER5, val);
+		if (ret != EC_SUCCESS)
+			goto out_unlock;
+
+		/* Accel Y[7:0] */
+		val = offset[Y] & GENMASK(7, 0);
+		ret = icm_write_mclk_reg(s, ICM42607_MREG_OFFSET_USER6, val);
+		if (ret != EC_SUCCESS)
+			goto out_unlock;
+
+		/* Accel Z[11:8] | Accel Y[11:8] */
+		val = ((offset[Z] >> 4) & GENMASK(7, 4)) |
+		      ((offset[Y] >> 8) & GENMASK(3, 0));
+		ret = icm_write_mclk_reg(s, ICM42607_MREG_OFFSET_USER7, val);
+		if (ret != EC_SUCCESS)
+			goto out_unlock;
+
+		/* Accel Z[7:0] */
+		val = offset[Z] & GENMASK(7, 0);
+		ret = icm_write_mclk_reg(s, ICM42607_MREG_OFFSET_USER8, val);
+		if (ret != EC_SUCCESS)
+			goto out_unlock;
+		break;
+
+	case MOTIONSENSE_TYPE_GYRO:
+		/* Gyro X[7:0] */
+		val = offset[X] & GENMASK(7, 0);
+		ret = icm_write_mclk_reg(s, ICM42607_MREG_OFFSET_USER0, val);
+		if (ret != EC_SUCCESS)
+			goto out_unlock;
+
+		/* Gyro Y[11:8] | Gyro X[11:8] */
+		val = ((offset[Y] >> 4) & GENMASK(7, 4)) |
+		      ((offset[X] >> 8) & GENMASK(3, 0));
+		ret = icm_write_mclk_reg(s, ICM42607_MREG_OFFSET_USER1, val);
+		if (ret != EC_SUCCESS)
+			goto out_unlock;
+
+		/* Gyro Y[7:0] */
+		val = offset[Y] & GENMASK(7, 0);
+		ret = icm_write_mclk_reg(s, ICM42607_MREG_OFFSET_USER2, val);
+		if (ret != EC_SUCCESS)
+			goto out_unlock;
+
+		/* Gyro Z[7:0] */
+		val = offset[Z] & GENMASK(7, 0);
+		ret = icm_write_mclk_reg(s, ICM42607_MREG_OFFSET_USER3, val);
+		if (ret != EC_SUCCESS)
+			goto out_unlock;
+
+		/* Accel X[11:8] | gyro Z[11:8] */
+		val = (offset[Z] >> 8) & GENMASK(3, 0);
+		ret = icm_field_update_mclk_reg(s, ICM42607_MREG_OFFSET_USER4,
+						GENMASK(3, 0), val);
+		if (ret != EC_SUCCESS)
+			goto out_unlock;
+		break;
+
+	default:
+		ret = EC_ERROR_INVAL;
+		goto out_unlock;
+	}
+
+	ret = icm_switch_off_mclk(s);
+
+out_unlock:
+	mutex_unlock(s->mutex);
+	return ret;
+}
+
+static int icm42607_set_offset(const struct motion_sensor_t *s,
+			       const int16_t *offset, int16_t temp)
+{
+	intv3_t v = { offset[X], offset[Y], offset[Z] };
+	int div1, div2;
+	int i;
+
+	/* rotate back to chip frame */
+	rotate_inv(v, *s->rot_standard_ref, v);
+
+	switch (s->type) {
+	case MOTIONSENSE_TYPE_ACCEL:
+		/* hardware offset is 1/2048g /LSB, EC offset 1/1024g /LSB. */
+		div1 = 2;
+		div2 = 1;
+		break;
+	case MOTIONSENSE_TYPE_GYRO:
+		/* hardware offset is 1/32dps /LSB, EC offset 1/1024dps /LSB. */
+		div1 = 1;
+		div2 = 32;
+		break;
+	default:
+		return EC_ERROR_INVAL;
+	}
+	for (i = X; i <= Z; ++i)
+		v[i] = round_divide(v[i] * div1, div2);
+
+	return icm42607_set_hw_offset(s, v);
+}
+
+static int icm42607_get_offset(const struct motion_sensor_t *s, int16_t *offset,
+			       int16_t *temp)
+{
+	intv3_t v;
+	int div1, div2;
+	int i, ret;
+
+	ret = icm42607_get_hw_offset(s, v);
+	if (ret != EC_SUCCESS)
+		return ret;
+
+	switch (s->type) {
+	case MOTIONSENSE_TYPE_ACCEL:
+		/* hardware offset is 1/2048g /LSB, EC offset 1/1024g /LSB. */
+		div1 = 1;
+		div2 = 2;
+		break;
+	case MOTIONSENSE_TYPE_GYRO:
+		/* hardware offset is 1/32dps /LSB, EC offset 1/1024dps /LSB. */
+		div1 = 32;
+		div2 = 1;
+		break;
+	default:
+		return EC_ERROR_INVAL;
+	}
+
+	for (i = X; i <= Z; ++i)
+		v[i] = round_divide(v[i] * div1, div2);
+
+	rotate(v, *s->rot_standard_ref, v);
+	offset[X] = v[X];
+	offset[Y] = v[Y];
+	offset[Z] = v[Z];
+	*temp = EC_MOTION_SENSE_INVALID_CALIB_TEMP;
+
+	return EC_SUCCESS;
+}
+
+static int icm42607_read(const struct motion_sensor_t *s, intv3_t v)
+{
+	uint8_t raw[6];
+	int reg, ret;
+
+	switch (s->type) {
+	case MOTIONSENSE_TYPE_ACCEL:
+		reg = ICM42607_REG_ACCEL_DATA_XYZ;
+		break;
+	case MOTIONSENSE_TYPE_GYRO:
+		reg = ICM42607_REG_GYRO_DATA_XYZ;
+		break;
+	default:
+		return EC_ERROR_INVAL;
+	}
+
+	/* read data registers if sensor is stabilized */
+	mutex_lock(s->mutex);
+
+	ret = icm42607_check_sensor_stabilized(s, __hw_clock_source_read());
+	if (ret == EC_SUCCESS)
+		ret = icm_read_n(s, reg, raw, sizeof(raw));
+
+	mutex_unlock(s->mutex);
+	if (ret != EC_SUCCESS)
+		return ret;
+
+	ret = icm42607_normalize(s, v, raw);
+	/* if data is invalid return the previous read data */
+	if (ret != EC_SUCCESS) {
+		if (v != s->raw_xyz)
+			memcpy(v, s->raw_xyz, sizeof(s->raw_xyz));
+	}
+
+	return EC_SUCCESS;
+}
+
+static int icm42607_read_temp(const struct motion_sensor_t *s, int *temp_ptr)
+{
+	int val, ret;
+
+	mutex_lock(s->mutex);
+	ret = icm_read16(s, ICM42607_REG_TEMP_DATA, &val);
+	mutex_unlock(s->mutex);
+
+	if (ret != EC_SUCCESS)
+		return ret;
+
+	/* This register is big-endian and not configurable */
+	val = be16toh(val);
+
+	/* ensure correct propagation of 16 bits sign bit */
+	val = sign_extend(val, 15);
+
+	if (val == ICM42607_INVALID_DATA)
+		return EC_ERROR_NOT_POWERED;
+
+	*temp_ptr = C_TO_K((val / 128) + 25);
+	return EC_SUCCESS;
+}
+
+static int icm42607_reset_revA(const struct motion_sensor_t *s)
+{
+	int ret, val;
+
+	/* clear status register */
+	ret = icm_read8(s, ICM42607_REG_INT_STATUS, &val);
+	if (ret)
+		return ret;
+
+	ret = icm_switch_on_mclk(s);
+	if (ret)
+		return ret;
+
+	/* Set otp_copy_mode register field */
+	ret = icm_field_update_mclk_reg(s, ICM42607_MREG_OTP_CONFIG,
+					ICM42607_OTP_COPY_MODE_MASK,
+					ICM42607_OTP_COPY_TRIM);
+	if (ret)
+		return ret;
+
+	/* Set otp_power_down register field to 0 */
+	ret = icm_field_update_mclk_reg(s, ICM42607_MREG_OTP_CTRL7,
+					ICM42607_OTP_PWR_DOWN, 0);
+	if (ret)
+		return ret;
+
+	/* Wait for 300us for the OTP to fully power up */
+	usleep(300);
+
+	/* Set otp_reload register field */
+	ret = icm_field_update_mclk_reg(s, ICM42607_MREG_OTP_CTRL7,
+					ICM42607_OTP_RELOAD,
+					ICM42607_OTP_RELOAD);
+	if (ret)
+		return ret;
+
+	/* Wait for 280 us for the OTP to load */
+	usleep(280);
+
+	/* Write POR value for all registers not loaded with OTP */
+	ret = icm_write8(s, ICM42607_REG_GYRO_CONFIG0, 0x06);
+	if (ret)
+		return ret;
+
+	ret = icm_write8(s, ICM42607_REG_ACCEL_CONFIG0, 0x06);
+	if (ret)
+		return ret;
+
+	ret = icm_write8(s, ICM42607_REG_APEX_CONFIG0, 0x08);
+	if (ret)
+		return ret;
+
+	ret = icm_write8(s, ICM42607_REG_APEX_CONFIG1, 0x02);
+	if (ret)
+		return ret;
+
+	ret = icm_write8(s, ICM42607_REG_FIFO_CONFIG1, 0x01);
+	if (ret)
+		return ret;
+
+	ret = icm_write8(s, ICM42607_REG_FIFO_CONFIG2, 0x00);
+	if (ret)
+		return ret;
+
+	ret = icm_write8(s, ICM42607_REG_FIFO_CONFIG3, 0x00);
+	if (ret)
+		return ret;
+
+	ret = icm_write_mclk_reg(s, ICM42607_MREG_FIFO_CONFIG5, 0x20);
+	if (ret)
+		return ret;
+
+	ret = icm_write_mclk_reg(s, ICM42607_MREG_INT_SOURCE7, 0x00);
+	if (ret)
+		return ret;
+
+	ret = icm_write_mclk_reg(s, ICM42607_MREG_INT_SOURCE8, 0x00);
+	if (ret)
+		return ret;
+
+	ret = icm_write_mclk_reg(s, ICM42607_MREG_INT_SOURCE9, 0x00);
+	if (ret)
+		return ret;
+
+	ret = icm_write_mclk_reg(s, ICM42607_MREG_INT_SOURCE10, 0x00);
+	if (ret)
+		return ret;
+
+	ret = icm_write_mclk_reg(s, ICM42607_MREG_APEX_CONFIG2, 0xA2);
+	if (ret)
+		return ret;
+
+	ret = icm_write_mclk_reg(s, ICM42607_MREG_APEX_CONFIG3, 0x85);
+	if (ret)
+		return ret;
+
+	ret = icm_write_mclk_reg(s, ICM42607_MREG_APEX_CONFIG4, 0x51);
+	if (ret)
+		return ret;
+
+	ret = icm_write_mclk_reg(s, ICM42607_MREG_APEX_CONFIG5, 0x80);
+	if (ret)
+		return ret;
+
+	ret = icm_write_mclk_reg(s, ICM42607_MREG_APEX_CONFIG9, 0x00);
+	if (ret)
+		return ret;
+
+	ret = icm_write_mclk_reg(s, ICM42607_MREG_APEX_CONFIG10, 0x00);
+	if (ret)
+		return ret;
+
+	ret = icm_write_mclk_reg(s, ICM42607_MREG_APEX_CONFIG11, 0x00);
+	if (ret)
+		return ret;
+
+	ret = icm_write_mclk_reg(s, ICM42607_MREG_OFFSET_USER0, 0x00);
+	if (ret)
+		return ret;
+
+	ret = icm_write_mclk_reg(s, ICM42607_MREG_OFFSET_USER1, 0x00);
+	if (ret)
+		return ret;
+
+	ret = icm_write_mclk_reg(s, ICM42607_MREG_OFFSET_USER2, 0x00);
+	if (ret)
+		return ret;
+
+	ret = icm_write_mclk_reg(s, ICM42607_MREG_OFFSET_USER3, 0x00);
+	if (ret)
+		return ret;
+
+	ret = icm_write_mclk_reg(s, ICM42607_MREG_OFFSET_USER4, 0x00);
+	if (ret)
+		return ret;
+
+	ret = icm_write_mclk_reg(s, ICM42607_MREG_OFFSET_USER5, 0x00);
+	if (ret)
+		return ret;
+
+	ret = icm_write_mclk_reg(s, ICM42607_MREG_OFFSET_USER6, 0x00);
+	if (ret)
+		return ret;
+
+	ret = icm_write_mclk_reg(s, ICM42607_MREG_OFFSET_USER7, 0x00);
+	if (ret)
+		return ret;
+
+	ret = icm_write_mclk_reg(s, ICM42607_MREG_OFFSET_USER8, 0x00);
+	if (ret)
+		return ret;
+
+	ret = icm_write_mclk_reg(s, ICM42607_MREG_APEX_CONFIG12, 0x00);
+	if (ret)
+		return ret;
+
+	ret = icm_switch_off_mclk(s);
+	if (ret)
+		return ret;
+
+#ifdef CONFIG_ACCELGYRO_ICM_COMM_SPI
+	/* Device operation in shared spi bus configuration */
+	ret = icm_field_update8(s, ICM42607_REG_INTF_CONFIG0, 0x03, 0x03);
+	if (ret)
+		return ret;
+#endif
+	return EC_SUCCESS;
+}
+
+static int icm42607_reset_revB(const struct motion_sensor_t *s)
+{
+	int val, ret, i;
+
+	ret = icm_write8(s, ICM42607_REG_SIGNAL_PATH_RESET,
+			 ICM42607_SOFT_RESET_DEV_CONFIG);
+	if (ret)
+		return ret;
+
+	/* Check reset is done, 1ms max */
+	for (i = 0; i < 5; i++) {
+		usleep(200);
+		ret = icm_read8(s, ICM42607_REG_INT_STATUS, &val);
+		if (ret)
+			return ret;
+		if (val == ICM42607_RESET_DONE_INT)
+			break;
+	}
+	if (val != ICM42607_RESET_DONE_INT)
+		return EC_ERROR_HW_INTERNAL;
+
+	return EC_SUCCESS;
+}
+
+static int icm42607_init_config(const struct motion_sensor_t *s,
+				const int who_am_i)
+{
+	int mask, val, ret;
+
+	switch (who_am_i) {
+	case ICM42607_CHIP_ICM42607P:
+		ret = icm42607_reset_revA(s);
+		break;
+	case ICM42607_CHIP_ICM42608P:
+		ret = icm42607_reset_revB(s);
+		break;
+	default:
+		ret = EC_ERROR_ACCESS_DENIED;
+		break;
+	}
+	if (ret)
+		return ret;
+
+	/* disable i3c support */
+	mask = ICM42607_I3C_SDR_EN | ICM42607_I3C_DDR_EN;
+	ret = icm_field_update8(s, ICM42607_REG_INTF_CONFIG1, mask, 0);
+	if (ret)
+		return ret;
+
+	/* set averaging filter for accel, 8x is max for 400Hz */
+	if (ICM42607_ACCEL_MAX_FREQ == 400000)
+		val = ICM42607_UI_AVG_SET(ICM42607_UI_AVG_8X);
+	else
+		val = ICM42607_UI_AVG_SET(ICM42607_UI_AVG_32X);
+	ret = icm_field_update8(s, ICM42607_REG_ACCEL_CONFIG1,
+				ICM42607_UI_AVG_MASK, val);
+	if (ret)
+		return ret;
+
+	/* disable all interrupts */
+	ret = icm_write8(s, ICM42607_REG_INT_SOURCE0, 0);
+	if (ret)
+		return ret;
+
+	/* disable FIFO */
+	return icm_write8(s, ICM42607_REG_FIFO_CONFIG1, ICM42607_FIFO_BYPASS);
+}
+
+static int icm42607_init(struct motion_sensor_t *s)
+{
+	struct accelgyro_saved_data_t *saved_data = ICM_GET_SAVED_DATA(s);
+	int who_am_i;
+	int ret, i;
+
+	mutex_lock(s->mutex);
+
+	/* detect chip using whoami */
+	ret = icm_read8(s, ICM42607_REG_WHO_AM_I, &who_am_i);
+	if (ret)
+		goto out_unlock;
+
+	if (who_am_i != ICM42607_CHIP_ICM42607P &&
+	    who_am_i != ICM42607_CHIP_ICM42608P) {
+		CPRINTS("Unknown WHO_AM_I: 0x%02x", who_am_i);
+		ret = EC_ERROR_ACCESS_DENIED;
+		goto out_unlock;
+	}
+
+	/* first time init done only for 1st sensor (accel) */
+	if (s->type == MOTIONSENSE_TYPE_ACCEL) {
+		/* configure sensor */
+		ret = icm42607_init_config(s, who_am_i);
+		if (ret)
+			goto out_unlock;
+
+		if (IS_ENABLED(ACCELGYRO_ICM42607_INT_ENABLE)) {
+			ret = icm42607_config_interrupt(s);
+			if (ret)
+				goto out_unlock;
+		}
+	}
+
+	for (i = X; i <= Z; i++)
+		saved_data->scale[i] = MOTION_SENSE_DEFAULT_SCALE;
+
+	saved_data->odr = 0;
+
+	mutex_unlock(s->mutex);
+
+	return sensor_init_done(s);
+
+out_unlock:
+	mutex_unlock(s->mutex);
+	return ret;
+}
+
+const struct accelgyro_drv icm42607_drv = {
+	.init = icm42607_init,
+	.read = icm42607_read,
+	.read_temp = icm42607_read_temp,
+	.set_range = icm42607_set_range,
+	.get_resolution = icm_get_resolution,
+	.set_data_rate = icm42607_set_data_rate,
+	.get_data_rate = icm_get_data_rate,
+	.set_offset = icm42607_set_offset,
+	.get_offset = icm42607_get_offset,
+	.set_scale = icm_set_scale,
+	.get_scale = icm_get_scale,
+#ifdef ACCELGYRO_ICM42607_INT_ENABLE
+	.irq_handler = icm42607_irq_handler,
+#endif
+};
diff --git a/driver/accelgyro_icm42607.h b/driver/accelgyro_icm42607.h
new file mode 100644
index 0000000000..2da5bf17a5
--- /dev/null
+++ b/driver/accelgyro_icm42607.h
@@ -0,0 +1,309 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* ICM-42607 accelerometer and gyroscope for Chrome EC */
+
+#ifndef __CROS_EC_ACCELGYRO_ICM42607_H
+#define __CROS_EC_ACCELGYRO_ICM42607_H
+
+#include "accelgyro.h"
+#include "common.h"
+
+/*
+ * 7-bit address is 110100Xb. Where 'X' is determined
+ * by the logic level on pin AP_AD0.
+ */
+#define ICM42607_ADDR0_FLAGS 0x68
+#define ICM42607_ADDR1_FLAGS 0x69
+
+/* Min and Max sampling frequency in mHz */
+#define ICM42607_ACCEL_MIN_FREQ 1562
+#define ICM42607_ACCEL_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(400000, 100000)
+#define ICM42607_GYRO_MIN_FREQ 12500
+#define ICM42607_GYRO_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(1600000, 100000)
+
+/* Min and Max Accel FS in g */
+#define ICM42607_ACCEL_FS_MIN_VAL 2
+#define ICM42607_ACCEL_FS_MAX_VAL 16
+
+/* Min and Max Gyro FS in dps */
+#define ICM42607_GYRO_FS_MIN_VAL 250
+#define ICM42607_GYRO_FS_MAX_VAL 2000
+
+/* accel stabilization time in us */
+#define ICM42607_ACCEL_START_TIME 20000
+#define ICM42607_ACCEL_STOP_TIME 0
+
+/* gyro stabilization time in us */
+#define ICM42607_GYRO_START_TIME 40000
+#define ICM42607_GYRO_STOP_TIME 20000
+
+/* Reg value from Accel FS in G */
+#define ICM42607_ACCEL_FS_TO_REG(_fs) \
+	((_fs) <= 2 ? 3 : (_fs) >= 16 ? 0 : 3 - __fls((_fs) / 2))
+
+/* Accel FSR in G from Reg value */
+#define ICM42607_ACCEL_REG_TO_FS(_reg) ((1 << (3 - (_reg))) * 2)
+
+/* Reg value from Gyro FS in dps */
+#define ICM42607_GYRO_FS_TO_REG(_fs) \
+	((_fs) <= 250 ? 3 : (_fs) >= 2000 ? 0 : 3 - __fls((_fs) / 250))
+
+/* Gyro FSR in dps from Reg value */
+#define ICM42607_GYRO_REG_TO_FS(_reg) ((1 << (3 - (_reg))) * 250)
+
+/* Reg value from ODR in mHz */
+#define ICM42607_ODR_TO_REG(_odr) \
+	((_odr) == 0 ? 0 : (__fls(1600000 / (_odr)) + 5))
+
+/* ODR in mHz from Reg value */
+#define ICM42607_REG_TO_ODR(_reg) \
+	((_reg) <= 5 ? 1600000 : (1600000 / (1 << ((_reg)-5))))
+
+/* Reg value for the next higher ODR */
+#define ICM42607_ODR_REG_UP(_reg) ((_reg)-1)
+
+/*
+ * Filter bandwidth values from ODR reg
+ *   >= 400Hz (7) -> 180Hz (1)
+ *   200Hz (8) -> 73Hz (3)
+ *   100Hz (9) -> 53Hz (4)
+ *   50Hz (10) -> 25Hz (6)
+ *   <= 25Hz (11) -> 16Hz (7)
+ */
+#define ICM42607_ODR_TO_FILT_BW(_odr) \
+	((_odr) <= 7 ? 1 : (_odr) <= 9 ? (_odr)-5 : (_odr) == 10 ? 6 : 7)
+
+/*
+ * Register addresses are virtual address on 16 bits.
+ * MSB is coding block selection value for MREG registers
+ * and LSB real register address.
+ * ex: MREG2 (block 0x28) register 03 => 0x2803
+ */
+#define ICM42607_REG_MCLK_RDY 0x0000
+#define ICM42607_MCLK_RDY BIT(3)
+
+#define ICM42607_REG_DEVICE_CONFIG 0x0001
+#define ICM42607_SPI_MODE_1_2 BIT(0)
+#define ICM42607_SPI_AP_4WIRE BIT(2)
+
+#define ICM42607_REG_SIGNAL_PATH_RESET 0x0002
+#define ICM42607_SOFT_RESET_DEV_CONFIG BIT(4)
+#define ICM42607_FIFO_FLUSH BIT(2)
+
+#define ICM42607_REG_DRIVE_CONFIG1 0x0003
+
+#define ICM42607_REG_DRIVE_CONFIG2 0x0004
+
+#define ICM42607_REG_DRIVE_CONFIG3 0x0005
+
+/* default int configuration is pulsed mode, open drain, and active low */
+#define ICM42607_REG_INT_CONFIG 0x0006
+#define ICM42607_INT2_MASK GENMASK(5, 3)
+#define ICM42607_INT2_LATCHED BIT(5)
+#define ICM42607_INT2_PUSH_PULL BIT(4)
+#define ICM42607_INT2_ACTIVE_HIGH BIT(3)
+#define ICM42607_INT1_MASK GENMASK(2, 0)
+#define ICM42607_INT1_LATCHED BIT(2)
+#define ICM42607_INT1_PUSH_PULL BIT(1)
+#define ICM42607_INT1_ACTIVE_HIGH BIT(0)
+
+/* data are 16 bits */
+#define ICM42607_REG_TEMP_DATA 0x0009
+
+/* X + Y + Z: 3 * 16 bits */
+#define ICM42607_REG_ACCEL_DATA_XYZ 0x000B
+#define ICM42607_REG_GYRO_DATA_XYZ 0x0011
+
+#define ICM42607_INVALID_DATA -32768
+
+/* data are 16 bits */
+#define ICM42607_REG_TMST_FSYNCH 0x0017
+
+#define ICM42607_REG_PWR_MGMT0 0x001F
+#define ICM42607_ACCEL_LP_CLK_SEL BIT(7)
+#define ICM42607_IDLE BIT(4)
+#define ICM42607_GYRO_MODE_MASK GENMASK(3, 2)
+#define ICM42607_GYRO_MODE(_m) (((_m)&0x03) << 2)
+#define ICM42607_ACCEL_MODE_MASK GENMASK(1, 0)
+#define ICM42607_ACCEL_MODE(_m) ((_m)&0x03)
+
+enum icm42607_sensor_mode {
+	ICM42607_MODE_OFF,
+	ICM42607_MODE_STANDBY,
+	ICM42607_MODE_LOW_POWER,
+	ICM42607_MODE_LOW_NOISE,
+};
+
+#define ICM42607_REG_GYRO_CONFIG0 0x0020
+#define ICM42607_REG_ACCEL_CONFIG0 0x0021
+#define ICM42607_FS_MASK GENMASK(6, 5)
+#define ICM42607_FS_SEL(_fs) (((_fs)&0x03) << 5)
+#define ICM42607_ODR_MASK GENMASK(3, 0)
+#define ICM42607_ODR(_odr) ((_odr)&0x0F)
+
+#define ICM42607_REG_TEMP_CONFIG0 0x0022
+
+enum icm42607_ui_avg {
+	ICM42607_UI_AVG_2X,
+	ICM42607_UI_AVG_4X,
+	ICM42607_UI_AVG_8X,
+	ICM42607_UI_AVG_16X,
+	ICM42607_UI_AVG_32X,
+	ICM42607_UI_AVG_64X,
+};
+
+enum icm42607_ui_filt_bw {
+	ICM42607_UI_FILT_BW_DISABLED,
+	ICM42607_UI_FILT_BW_180HZ,
+	ICM42607_UI_FILT_BW_121HZ,
+	ICM42607_UI_FILT_BW_73HZ,
+	ICM42607_UI_FILT_BW_53HZ,
+	ICM42607_UI_FILT_BW_34HZ,
+	ICM42607_UI_FILT_BW_25HZ,
+	ICM42607_UI_FILT_BW_16HZ,
+};
+
+#define ICM42607_REG_GYRO_CONFIG1 0x0023
+#define ICM42607_REG_ACCEL_CONFIG1 0x0024
+#define ICM42607_UI_AVG_MASK GENMASK(6, 4)
+#define ICM42607_UI_AVG_SET(_avg) (((_avg)&0x07) << 4)
+#define ICM42607_UI_FILT_BW_MASK GENMASK(2, 0)
+#define ICM42607_UI_FILT_BW_SET(_filt) ((_filt)&0x07)
+
+#define ICM42607_REG_FIFO_CONFIG1 0x0028
+#define ICM42607_REG_FIFO_CONFIG2 0x0029
+#define ICM42607_REG_FIFO_CONFIG3 0x002A
+#define ICM42607_FIFO_STOP_ON_FULL_MODE BIT(1)
+#define ICM42607_FIFO_BYPASS BIT(0)
+#define ICM42607_FIFO_MODE_STREAM 0x00
+
+/* FIFO watermark value is 16 bits little endian */
+#define ICM42607_REG_FIFO_WM 0x0029
+
+#define ICM42607_REG_INT_SOURCE0 0x002B
+#define ICM42607_ST_INT1_EN BIT(7)
+#define ICM42607_FSYNC_INT1_EN BIT(6)
+#define ICM42607_PLL_RDY_INT1_EN BIT(5)
+#define ICM42607_RESET_DONE_INT1_EN BIT(4)
+#define ICM42607_DRDY_INT1_EN BIT(3)
+#define ICM42607_FIFO_THS_INT1_EN BIT(2)
+#define ICM42607_FIFO_FULL_INT1_EN BIT(1)
+#define ICM42607_UI_AGC_RDY_INT1_EN BIT(0)
+
+#define ICM42607_REG_INTF_CONFIG0 0x0035
+#define ICM42607_FIFO_COUNT_FORMAT BIT(6)
+#define ICM42607_FIFO_COUNT_ENDIAN BIT(5)
+#define ICM42607_SENSOR_DATA_ENDIAN BIT(4)
+
+#define ICM42607_REG_INTF_CONFIG1 0x0036
+#define ICM42607_I3C_SDR_EN BIT(3)
+#define ICM42607_I3C_DDR_EN BIT(2)
+#define ICM42607_CLKSEL_MASK GENMASK(1, 0)
+#define ICM42607_CLKSEL_PLL_ENABLE 0x01
+
+#define ICM42607_REG_INT_STATUS_DRDY 0x0039
+#define ICM42607_DATA_RDY_INT BIT(0)
+
+#define ICM42607_REG_INT_STATUS 0x003A
+#define ICM42607_ST_INT BIT(7)
+#define ICM42607_FSYNC_INT BIT(6)
+#define ICM42607_PLL_RDY_INT BIT(5)
+#define ICM42607_RESET_DONE_INT BIT(4)
+#define ICM42607_FIFO_THS_INT BIT(2)
+#define ICM42607_FIFO_FULL_INT BIT(1)
+#define ICM42607_AGC_RDY_INT BIT(0)
+
+/* FIFO count is 16 bits */
+#define ICM42607_REG_FIFO_COUNT 0x003D
+
+#define ICM42607_REG_FIFO_DATA 0x003F
+
+#define ICM42607_REG_APEX_CONFIG0 0x0025
+#define ICM42607_DMP_SRAM_RESET_APEX BIT(0)
+
+#define ICM42607_REG_APEX_CONFIG1 0x0026
+#define ICM42607_DMP_ODR_50HZ BIT(1)
+
+#define ICM42607_REG_WHO_AM_I 0x0075
+#define ICM42607_CHIP_ICM42607P 0x60
+#define ICM42607_CHIP_ICM42608P 0x3F
+
+/* MREG read access registers */
+#define ICM42607_REG_BLK_SEL_W 0x0079
+#define ICM42607_REG_MADDR_W 0x007A
+#define ICM42607_REG_M_W 0x007B
+
+/* MREG write access registers */
+#define ICM42607_REG_BLK_SEL_R 0x007C
+#define ICM42607_REG_MADDR_R 0x007D
+#define ICM42607_REG_M_R 0x007E
+
+/* USER BANK MREG1 */
+#define ICM42607_MREG_FIFO_CONFIG5 0x0001
+#define ICM42607_FIFO_WM_GT_TH BIT(5)
+#define ICM42607_FIFO_RESUME_PARTIAL_RD BIT(4)
+#define ICM42607_FIFO_HIRES_EN BIT(3)
+#define ICM42607_FIFO_TMST_FSYNC_EN BIT(2)
+#define ICM42607_FIFO_GYRO_EN BIT(1)
+#define ICM42607_FIFO_ACCEL_EN BIT(0)
+
+#define ICM42607_MREG_OTP_CONFIG 0x002B
+#define ICM42607_OTP_COPY_MODE_MASK GENMASK(3, 2)
+#define ICM42607_OTP_COPY_TRIM (0x01 << 2)
+#define ICM42607_OTP_COPY_ST_DATA (0x03 << 2)
+
+#define ICM42607_MREG_INT_SOURCE7 0x0030
+#define ICM42607_MREG_INT_SOURCE8 0x0031
+#define ICM42607_MREG_INT_SOURCE9 0x0032
+#define ICM42607_MREG_INT_SOURCE10 0x0033
+
+#define ICM42607_MREG_APEX_CONFIG2 0x0044
+#define ICM42607_MREG_APEX_CONFIG3 0x0045
+#define ICM42607_MREG_APEX_CONFIG4 0x0046
+#define ICM42607_MREG_APEX_CONFIG5 0x0047
+#define ICM42607_MREG_APEX_CONFIG9 0x0048
+#define ICM42607_MREG_APEX_CONFIG10 0x0049
+#define ICM42607_MREG_APEX_CONFIG11 0x004A
+#define ICM42607_MREG_APEX_CONFIG12 0x0067
+
+#define ICM42607_MREG_OFFSET_USER0 0x004E
+#define ICM42607_MREG_OFFSET_USER1 0x004F
+#define ICM42607_MREG_OFFSET_USER2 0x0050
+#define ICM42607_MREG_OFFSET_USER3 0x0051
+#define ICM42607_MREG_OFFSET_USER4 0x0052
+#define ICM42607_MREG_OFFSET_USER5 0x0053
+#define ICM42607_MREG_OFFSET_USER6 0x0054
+#define ICM42607_MREG_OFFSET_USER7 0x0055
+#define ICM42607_MREG_OFFSET_USER8 0x0056
+
+/* USER BANK MREG2 */
+#define ICM42607_MREG_OTP_CTRL7 0x2806
+#define ICM42607_OTP_RELOAD BIT(3)
+#define ICM42607_OTP_PWR_DOWN BIT(1)
+
+extern const struct accelgyro_drv icm42607_drv;
+
+void icm42607_interrupt(enum gpio_signal signal);
+
+#if defined(CONFIG_ZEPHYR)
+#if DT_NODE_EXISTS(DT_ALIAS(icm42607_int))
+/*
+ * Get the motion sensor ID of the ICM42607 sensor that generates the interrupt.
+ * The interrupt is converted to the event and transferred to motion sense task
+ * that actually handles the interrupt.
+ *
+ * Here we use an alias (icm42607_int) to get the motion sensor ID. This alias
+ * MUST be defined for this driver to work.
+ * aliases {
+ *   icm42607-int = &base_accel;
+ * };
+ */
+#define CONFIG_ACCELGYRO_ICM42607_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(SENSOR_ID(DT_ALIAS(icm42607_int)))
+#endif
+#endif /* defined(CONFIG_ZEPHYR) */
+
+#endif /* __CROS_EC_ACCELGYRO_ICM42607_H */
diff --git a/driver/accelgyro_icm426xx.c b/driver/accelgyro_icm426xx.c
index 27d590b96e..f82cb2d718 100644
--- a/driver/accelgyro_icm426xx.c
+++ b/driver/accelgyro_icm426xx.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,8 +10,8 @@
 
 #include "accelgyro.h"
 #include "console.h"
-#include "driver/accelgyro_icm_common.h"
 #include "driver/accelgyro_icm426xx.h"
+#include "driver/accelgyro_icm_common.h"
 #include "hwtimer.h"
 #include "i2c.h"
 #include "math_util.h"
@@ -22,11 +22,16 @@
 #include "timer.h"
 #include "util.h"
 
+#ifdef CONFIG_ACCELGYRO_ICM426XX_INT_EVENT
+#define ACCELGYRO_ICM426XX_INT_ENABLE
+#endif
+
 #define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args)
 
-STATIC_IF(CONFIG_ACCEL_FIFO) volatile uint32_t last_interrupt_timestamp;
+STATIC_IF(ACCELGYRO_ICM426XX_INT_ENABLE)
+volatile uint32_t last_interrupt_timestamp;
 
 static int icm426xx_normalize(const struct motion_sensor_t *s, intv3_t v,
 			      const uint8_t *raw)
@@ -40,8 +45,7 @@ static int icm426xx_normalize(const struct motion_sensor_t *s, intv3_t v,
 	v[Z] = (int16_t)UINT16_FROM_BYTE_ARRAY_LE(raw, 4);
 
 	/* check if data is valid */
-	if (v[X] == ICM426XX_INVALID_DATA &&
-	    v[Y] == ICM426XX_INVALID_DATA &&
+	if (v[X] == ICM426XX_INVALID_DATA && v[Y] == ICM426XX_INVALID_DATA &&
 	    v[Z] == ICM426XX_INVALID_DATA) {
 		return EC_ERROR_INVAL;
 	}
@@ -54,9 +58,25 @@ static int icm426xx_normalize(const struct motion_sensor_t *s, intv3_t v,
 	return EC_SUCCESS;
 }
 
+static int icm426xx_check_sensor_stabilized(const struct motion_sensor_t *s,
+					    uint32_t ts)
+{
+	int32_t rem;
+
+	rem = icm_get_sensor_stabilized(s, ts);
+	if (rem == 0)
+		return EC_SUCCESS;
+	if (rem > 0)
+		return EC_ERROR_BUSY;
+
+	/* rem < 0: reset check since ts has passed stabilize_ts */
+	icm_reset_stabilize_ts(s);
+	return EC_SUCCESS;
+}
+
 /* use FIFO threshold interrupt on INT1 */
-#define ICM426XX_FIFO_INT_EN		ICM426XX_FIFO_THS_INT1_EN
-#define ICM426XX_FIFO_INT_STATUS	ICM426XX_FIFO_THS_INT
+#define ICM426XX_FIFO_INT_EN ICM426XX_FIFO_THS_INT1_EN
+#define ICM426XX_FIFO_INT_STATUS ICM426XX_FIFO_THS_INT
 
 static int __maybe_unused icm426xx_enable_fifo(const struct motion_sensor_t *s,
 					       int enable)
@@ -163,23 +183,27 @@ static int __maybe_unused icm426xx_config_fifo(const struct motion_sensor_t *s,
 }
 
 static void __maybe_unused icm426xx_push_fifo_data(struct motion_sensor_t *s,
-						const uint8_t *raw, uint32_t ts)
+						   const uint8_t *raw,
+						   uint32_t ts)
 {
-	intv3_t v;
 	struct ec_response_motion_sensor_data vect;
-	int ret;
+	int *v = s->raw_xyz;
 
-	if (s == NULL)
+	if (icm426xx_normalize(s, v, raw) != EC_SUCCESS)
 		return;
 
-	ret = icm426xx_normalize(s, v, raw);
-	if (ret == EC_SUCCESS) {
+	if (IS_ENABLED(CONFIG_ACCEL_SPOOF_MODE) &&
+	    s->flags & MOTIONSENSE_FLAG_IN_SPOOF_MODE)
+		v = s->spoof_xyz;
+	if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
 		vect.data[X] = v[X];
 		vect.data[Y] = v[Y];
 		vect.data[Z] = v[Z];
 		vect.flags = 0;
 		vect.sensor_num = s - motion_sensors;
 		motion_sense_fifo_stage_data(&vect, s, 3, ts);
+	} else {
+		motion_sense_push_raw_xyz(s);
 	}
 }
 
@@ -201,10 +225,8 @@ static int __maybe_unused icm426xx_load_fifo(struct motion_sensor_t *s,
 	/* flush FIFO if buffer is not large enough */
 	if (count > ICM_FIFO_BUFFER) {
 		CPRINTS("It should not happen, the EC is too slow for the ODR");
-		ret = icm_write8(s, ICM426XX_REG_SIGNAL_PATH_RESET,
-				 ICM426XX_FIFO_FLUSH);
-		if (ret != EC_SUCCESS)
-			return ret;
+		RETURN_ERROR(icm_write8(s, ICM426XX_REG_SIGNAL_PATH_RESET,
+					ICM426XX_FIFO_FLUSH));
 		return EC_ERROR_OVERFLOW;
 	}
 
@@ -213,21 +235,27 @@ static int __maybe_unused icm426xx_load_fifo(struct motion_sensor_t *s,
 		return ret;
 
 	for (i = 0; i < count; i += size) {
-		size = icm_fifo_decode_packet(&st->fifo_buffer[i],
-				&accel, &gyro);
+		size = icm_fifo_decode_packet(&st->fifo_buffer[i], &accel,
+					      &gyro);
 		/* exit if error or FIFO is empty */
 		if (size <= 0)
 			return -size;
-		if (accel != NULL)
-			icm426xx_push_fifo_data(st->accel, accel, ts);
-		if (gyro != NULL)
-			icm426xx_push_fifo_data(st->gyro, gyro, ts);
+		if (accel != NULL) {
+			ret = icm426xx_check_sensor_stabilized(st->accel, ts);
+			if (ret == EC_SUCCESS)
+				icm426xx_push_fifo_data(st->accel, accel, ts);
+		}
+		if (gyro != NULL) {
+			ret = icm426xx_check_sensor_stabilized(st->gyro, ts);
+			if (ret == EC_SUCCESS)
+				icm426xx_push_fifo_data(st->gyro, gyro, ts);
+		}
 	}
 
 	return EC_SUCCESS;
 }
 
-#ifdef CONFIG_ACCEL_INTERRUPTS
+#ifdef ACCELGYRO_ICM426XX_INT_ENABLE
 
 /**
  * icm426xx_interrupt - called when the sensor activates the interrupt line.
@@ -237,11 +265,10 @@ static int __maybe_unused icm426xx_load_fifo(struct motion_sensor_t *s,
  */
 void icm426xx_interrupt(enum gpio_signal signal)
 {
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO))
-		last_interrupt_timestamp = __hw_clock_source_read();
+	last_interrupt_timestamp = __hw_clock_source_read();
 
 	task_set_event(TASK_ID_MOTIONSENSE,
-		       CONFIG_ACCELGYRO_ICM426XX_INT_EVENT, 0);
+		       CONFIG_ACCELGYRO_ICM426XX_INT_EVENT);
 }
 
 /**
@@ -264,12 +291,10 @@ static int icm426xx_irq_handler(struct motion_sensor_t *s, uint32_t *event)
 	if (ret != EC_SUCCESS)
 		goto out_unlock;
 
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
-		if (status & ICM426XX_FIFO_INT_STATUS) {
-			ret = icm426xx_load_fifo(s, last_interrupt_timestamp);
-			if (ret == EC_SUCCESS)
-				motion_sense_fifo_commit_data();
-		}
+	if (status & ICM426XX_FIFO_INT_STATUS) {
+		ret = icm426xx_load_fifo(s, last_interrupt_timestamp);
+		if (IS_ENABLED(CONFIG_ACCEL_FIFO) && (ret == EC_SUCCESS))
+			motion_sense_fifo_commit_data();
 	}
 
 out_unlock:
@@ -283,13 +308,8 @@ static int icm426xx_config_interrupt(const struct motion_sensor_t *s)
 	int val, ret;
 
 	/* configure INT1 pin */
-	val = ICM426XX_INT1_PUSH_PULL;
-	if (s->flags & MOTIONSENSE_FLAG_INT_ACTIVE_HIGH)
-		val |= ICM426XX_INT1_ACTIVE_HIGH;
-
-	ret = icm_write8(s, ICM426XX_REG_INT_CONFIG, val);
-	if (ret != EC_SUCCESS)
-		return ret;
+	RETURN_ERROR(icm_write8(s, ICM426XX_REG_INT_CONFIG,
+				ICM426XX_INT1_PUSH_PULL));
 
 	/* deassert async reset for proper INT pin operation */
 	ret = icm_field_update8(s, ICM426XX_REG_INT_CONFIG1,
@@ -297,37 +317,34 @@ static int icm426xx_config_interrupt(const struct motion_sensor_t *s)
 	if (ret != EC_SUCCESS)
 		return ret;
 
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
-		/*
-		 * configure FIFO:
-		 * - enable FIFO partial read
-		 * - enable continuous watermark interrupt
-		 * - disable all FIFO en bits
-		 */
-		val = ICM426XX_FIFO_PARTIAL_READ | ICM426XX_FIFO_WM_GT_TH;
-		ret = icm_field_update8(s, ICM426XX_REG_FIFO_CONFIG1,
-					GENMASK(6, 5) | ICM426XX_FIFO_EN_MASK,
-					val);
-		if (ret != EC_SUCCESS)
-			return ret;
-
-		/* clear internal FIFO enable bits tracking */
-		st->fifo_en = 0;
+	/*
+	 * configure FIFO:
+	 * - enable FIFO partial read
+	 * - enable continuous watermark interrupt
+	 * - disable all FIFO en bits
+	 */
+	val = ICM426XX_FIFO_PARTIAL_READ | ICM426XX_FIFO_WM_GT_TH;
+	ret = icm_field_update8(s, ICM426XX_REG_FIFO_CONFIG1,
+				GENMASK(6, 5) | ICM426XX_FIFO_EN_MASK, val);
+	if (ret != EC_SUCCESS)
+		return ret;
 
-		/* set FIFO watermark to 1 data packet (8 bytes) */
-		ret = icm_write16(s, ICM426XX_REG_FIFO_WATERMARK, 8);
-		if (ret != EC_SUCCESS)
-			return ret;
-	}
+	/* clear internal FIFO enable bits tracking */
+	st->fifo_en = 0;
 
+	/* set FIFO watermark to 1 data packet (8 bytes) */
+	ret = icm_write16(s, ICM426XX_REG_FIFO_WATERMARK, 8);
+	if (ret != EC_SUCCESS)
+		return ret;
 	return ret;
 }
 
-#endif	/* CONFIG_ACCEL_INTERRUPTS */
+#endif /* ACCELGYRO_ICM426XX_INT_ENABLE */
 
 static int icm426xx_enable_sensor(const struct motion_sensor_t *s, int enable)
 {
-	unsigned int sleep;
+	uint32_t delay, stop_delay;
+	int32_t rem;
 	uint8_t mask, val;
 	int ret;
 
@@ -335,43 +352,50 @@ static int icm426xx_enable_sensor(const struct motion_sensor_t *s, int enable)
 	case MOTIONSENSE_TYPE_ACCEL:
 		mask = ICM426XX_ACCEL_MODE_MASK;
 		if (enable) {
-			sleep = 20;
+			delay = ICM426XX_ACCEL_START_TIME;
+			stop_delay = ICM426XX_ACCEL_STOP_TIME;
 			val = ICM426XX_ACCEL_MODE(ICM426XX_MODE_LOW_POWER);
 		} else {
-			sleep = 0;
+			delay = ICM426XX_ACCEL_STOP_TIME;
 			val = ICM426XX_ACCEL_MODE(ICM426XX_MODE_OFF);
 		}
 		break;
 	case MOTIONSENSE_TYPE_GYRO:
 		mask = ICM426XX_GYRO_MODE_MASK;
 		if (enable) {
-			sleep = 60;
+			delay = ICM426XX_GYRO_START_TIME;
+			stop_delay = ICM426XX_GYRO_STOP_TIME;
 			val = ICM426XX_GYRO_MODE(ICM426XX_MODE_LOW_NOISE);
 		} else {
-			sleep = 150;
+			delay = ICM426XX_GYRO_STOP_TIME;
 			val = ICM426XX_GYRO_MODE(ICM426XX_MODE_OFF);
 		}
 		break;
 	default:
-		return -EC_ERROR_INVAL;
+		return EC_ERROR_INVAL;
+	}
+
+	/* check stop delay and sleep if required */
+	if (enable) {
+		rem = icm_get_sensor_stabilized(s, __hw_clock_source_read());
+		/* rem > stop_delay means counter rollover */
+		if (rem > 0 && rem <= stop_delay)
+			usleep(rem);
 	}
 
 	mutex_lock(s->mutex);
 
 	ret = icm_field_update8(s, ICM426XX_REG_PWR_MGMT0, mask, val);
-	/* when turning sensor on block any register write for 200 us */
-	if (ret == EC_SUCCESS && enable)
-		usleep(200);
+	if (ret == EC_SUCCESS) {
+		icm_set_stabilize_ts(s, delay);
+		/* when turning sensor on block any register write for 200 us */
+		if (enable)
+			usleep(200);
+	}
 
 	mutex_unlock(s->mutex);
 
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	if (sleep)
-		msleep(sleep);
-
-	return EC_SUCCESS;
+	return ret;
 }
 
 static int icm426xx_set_data_rate(const struct motion_sensor_t *s, int rate,
@@ -409,23 +433,17 @@ static int icm426xx_set_data_rate(const struct motion_sensor_t *s, int rate,
 
 	if (rate > 0) {
 		if ((normalized_rate < min_rate) ||
-			(normalized_rate > max_rate))
+		    (normalized_rate > max_rate))
 			return EC_RES_INVALID_PARAM;
 	}
 
 	if (rate == 0) {
 		/* disable data in FIFO */
-		if (IS_ENABLED(CONFIG_ACCEL_FIFO))
-			icm426xx_config_fifo(s, 0);
+		icm426xx_config_fifo(s, 0);
 		/* disable sensor */
 		ret = icm426xx_enable_sensor(s, 0);
 		data->odr = 0;
 		return ret;
-	} else if (data->odr == 0) {
-		/* enable sensor */
-		ret = icm426xx_enable_sensor(s, 1);
-		if (ret)
-			return ret;
 	}
 
 	mutex_lock(s->mutex);
@@ -435,14 +453,18 @@ static int icm426xx_set_data_rate(const struct motion_sensor_t *s, int rate,
 	if (ret != EC_SUCCESS)
 		goto out_unlock;
 
-	data->odr = normalized_rate;
-
 	mutex_unlock(s->mutex);
 
-	/* enable data in FIFO */
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO))
+	if (data->odr == 0) {
+		/* enable sensor */
+		ret = icm426xx_enable_sensor(s, 1);
+		if (ret)
+			return ret;
+		/* enable data in FIFO */
 		icm426xx_config_fifo(s, 1);
+	}
 
+	data->odr = normalized_rate;
 	return EC_SUCCESS;
 
 out_unlock:
@@ -450,10 +472,8 @@ static int icm426xx_set_data_rate(const struct motion_sensor_t *s, int rate,
 	return ret;
 }
 
-static int icm426xx_set_range(const struct motion_sensor_t *s, int range,
-			      int rnd)
+static int icm426xx_set_range(struct motion_sensor_t *s, int range, int rnd)
 {
-	struct accelgyro_saved_data_t *data = ICM_GET_SAVED_DATA(s);
 	int reg, ret, reg_val;
 	int newrange;
 
@@ -501,7 +521,7 @@ static int icm426xx_set_range(const struct motion_sensor_t *s, int range,
 	ret = icm_field_update8(s, reg, ICM426XX_FS_MASK,
 				ICM426XX_FS_SEL(reg_val));
 	if (ret == EC_SUCCESS)
-		data->range = newrange;
+		s->current_range = newrange;
 
 	mutex_unlock(s->mutex);
 
@@ -517,8 +537,8 @@ static int icm426xx_get_hw_offset(const struct motion_sensor_t *s,
 	switch (s->type) {
 	case MOTIONSENSE_TYPE_ACCEL:
 		mutex_lock(s->mutex);
-		ret = icm_read_n(s, ICM426XX_REG_OFFSET_USER4,
-				raw, sizeof(raw));
+		ret = icm_read_n(s, ICM426XX_REG_OFFSET_USER4, raw,
+				 sizeof(raw));
 		mutex_unlock(s->mutex);
 		if (ret != EC_SUCCESS)
 			return ret;
@@ -535,8 +555,8 @@ static int icm426xx_get_hw_offset(const struct motion_sensor_t *s,
 		break;
 	case MOTIONSENSE_TYPE_GYRO:
 		mutex_lock(s->mutex);
-		ret = icm_read_n(s, ICM426XX_REG_OFFSET_USER0,
-				raw, sizeof(raw));
+		ret = icm_read_n(s, ICM426XX_REG_OFFSET_USER0, raw,
+				 sizeof(raw));
 		mutex_unlock(s->mutex);
 		if (ret != EC_SUCCESS)
 			return ret;
@@ -659,28 +679,24 @@ static int icm426xx_set_hw_offset(const struct motion_sensor_t *s,
 static int icm426xx_set_offset(const struct motion_sensor_t *s,
 			       const int16_t *offset, int16_t temp)
 {
-	struct accelgyro_saved_data_t *data = ICM_GET_SAVED_DATA(s);
 	intv3_t v = { offset[X], offset[Y], offset[Z] };
-	int range, div1, div2;
+	int div1, div2;
 	int i;
 
-	/* unscale values and rotate back to chip frame */
-	for (i = X; i <= Z; ++i)
-		v[i] = SENSOR_APPLY_DIV_SCALE(v[i], data->scale[i]);
+	/* rotate back to chip frame */
 	rotate_inv(v, *s->rot_standard_ref, v);
 
 	/* convert raw data to hardware offset units */
-	range = icm_get_range(s);
 	switch (s->type) {
 	case MOTIONSENSE_TYPE_ACCEL:
-		/* hardware offset is 1/2048g by LSB */
-		div1 = range * 2048;
-		div2 = 32768;
+		/* hardware offset is 1/2048g /LSB, EC offset 1/1024g /LSB. */
+		div1 = 2;
+		div2 = 1;
 		break;
 	case MOTIONSENSE_TYPE_GYRO:
-		/* hardware offset is 1/32dps by LSB */
-		div1 = range * 32;
-		div2 = 32768;
+		/* hardware offset is 1/32dps /LSB, EC offset 1/1024dps /LSB. */
+		div1 = 1;
+		div2 = 32;
 		break;
 	default:
 		return EC_ERROR_INVAL;
@@ -694,9 +710,8 @@ static int icm426xx_set_offset(const struct motion_sensor_t *s,
 static int icm426xx_get_offset(const struct motion_sensor_t *s, int16_t *offset,
 			       int16_t *temp)
 {
-	struct accelgyro_saved_data_t *data = ICM_GET_SAVED_DATA(s);
 	intv3_t v;
-	int range, div1, div2;
+	int div1, div2;
 	int i, ret;
 
 	ret = icm426xx_get_hw_offset(s, v);
@@ -704,17 +719,16 @@ static int icm426xx_get_offset(const struct motion_sensor_t *s, int16_t *offset,
 		return ret;
 
 	/* transform offset to raw data */
-	range = icm_get_range(s);
 	switch (s->type) {
 	case MOTIONSENSE_TYPE_ACCEL:
-		/* hardware offset is 1/2048g by LSB */
-		div1 = 32768;
-		div2 = 2048 * range;
+		/* hardware offset is 1/2048g /LSB, EC offset 1/1024g /LSB. */
+		div1 = 1;
+		div2 = 2;
 		break;
 	case MOTIONSENSE_TYPE_GYRO:
-		/* hardware offset is 1/32dps by LSB */
-		div1 = 32768;
-		div2 = 32 * range;
+		/* hardware offset is 1/32dps /LSB, EC offset 1/1024dps /LSB. */
+		div1 = 32;
+		div2 = 1;
 		break;
 	default:
 		return EC_ERROR_INVAL;
@@ -723,9 +737,6 @@ static int icm426xx_get_offset(const struct motion_sensor_t *s, int16_t *offset,
 		v[i] = round_divide(v[i] * div1, div2);
 
 	rotate(v, *s->rot_standard_ref, v);
-	for (i = X; i <= Z; i++)
-		v[i] = SENSOR_APPLY_SCALE(v[i], data->scale[i]);
-
 	offset[X] = v[X];
 	offset[Y] = v[Y];
 	offset[Z] = v[Z];
@@ -749,9 +760,13 @@ static int icm426xx_read(const struct motion_sensor_t *s, intv3_t v)
 		return EC_ERROR_INVAL;
 	}
 
-	/* read data registers */
+	/* read data registers if sensor is stabilized */
 	mutex_lock(s->mutex);
-	ret = icm_read_n(s, reg, raw, sizeof(raw));
+
+	ret = icm426xx_check_sensor_stabilized(s, __hw_clock_source_read());
+	if (ret == EC_SUCCESS)
+		ret = icm_read_n(s, reg, raw, sizeof(raw));
+
 	mutex_unlock(s->mutex);
 	if (ret != EC_SUCCESS)
 		return ret;
@@ -798,46 +813,32 @@ static int icm426xx_init_config(const struct motion_sensor_t *s)
 	 * interferences on the bus.
 	 */
 
-	ret = 0;
-	if (SLAVE_IS_SPI(s->i2c_spi_addr_flags)) {
-#ifdef CONFIG_SPI_ACCEL_PORT
-		icm_field_update8(s, ICM426XX_REG_INTF_CONFIG6,
-			ICM426XX_INTF_CONFIG6_MASK,
-			ICM426XX_I3C_EN | ICM426XX_I3C_SDR_EN |
-			ICM426XX_I3C_DDR_EN);
-		ret = icm_field_update8(s, ICM426XX_REG_INTF_CONFIG4,
-			ICM426XX_I3C_BUS_MODE,
-			ICM426XX_I3C_BUS_MODE);
-#endif
-	} else {
-#ifdef I2C_PORT_ACCEL
-		icm_field_update8(s, ICM426XX_REG_INTF_CONFIG6,
-			ICM426XX_INTF_CONFIG6_MASK,
-			ICM426XX_I3C_EN);
-		ret = icm_field_update8(s, ICM426XX_REG_INTF_CONFIG4,
-			ICM426XX_I3C_BUS_MODE,
-			0);
+#ifdef CONFIG_ACCELGYRO_ICM_COMM_SPI
+	icm_field_update8(
+		s, ICM426XX_REG_INTF_CONFIG6, ICM426XX_INTF_CONFIG6_MASK,
+		ICM426XX_I3C_EN | ICM426XX_I3C_SDR_EN | ICM426XX_I3C_DDR_EN);
+	ret = icm_field_update8(s, ICM426XX_REG_INTF_CONFIG4,
+				ICM426XX_I3C_BUS_MODE, ICM426XX_I3C_BUS_MODE);
+#else
+	icm_field_update8(s, ICM426XX_REG_INTF_CONFIG6,
+			  ICM426XX_INTF_CONFIG6_MASK, ICM426XX_I3C_EN);
+	ret = icm_field_update8(s, ICM426XX_REG_INTF_CONFIG4,
+				ICM426XX_I3C_BUS_MODE, 0);
 #endif
-	}
 	if (ret)
 		return ret;
 
-	ret = 0;
-	if (SLAVE_IS_SPI(s->i2c_spi_addr_flags)) {
-#ifdef CONFIG_SPI_ACCEL_PORT
-		ret = icm_field_update8(s, ICM426XX_REG_DRIVE_CONFIG,
-			ICM426XX_DRIVE_CONFIG_MASK,
-			ICM426XX_I2C_SLEW_RATE(ICM426XX_SLEW_RATE_20NS_60NS) |
+#ifdef CONFIG_ACCELGYRO_ICM_COMM_SPI
+	ret = icm_field_update8(
+		s, ICM426XX_REG_DRIVE_CONFIG, ICM426XX_DRIVE_CONFIG_MASK,
+		ICM426XX_I2C_SLEW_RATE(ICM426XX_SLEW_RATE_20NS_60NS) |
 			ICM426XX_SPI_SLEW_RATE(ICM426XX_SLEW_RATE_INF_2NS));
-#endif
-	} else {
-#ifdef I2C_PORT_ACCEL
-		ret = icm_field_update8(s, ICM426XX_REG_DRIVE_CONFIG,
-			ICM426XX_DRIVE_CONFIG_MASK,
-			ICM426XX_I2C_SLEW_RATE(ICM426XX_SLEW_RATE_12NS_36NS) |
+#else
+	ret = icm_field_update8(
+		s, ICM426XX_REG_DRIVE_CONFIG, ICM426XX_DRIVE_CONFIG_MASK,
+		ICM426XX_I2C_SLEW_RATE(ICM426XX_SLEW_RATE_12NS_36NS) |
 			ICM426XX_SPI_SLEW_RATE(ICM426XX_SLEW_RATE_12NS_36NS));
 #endif
-	}
 	if (ret)
 		return ret;
 
@@ -847,21 +848,23 @@ static int icm426xx_init_config(const struct motion_sensor_t *s)
 	 * Disable unused serial interface.
 	 */
 	mask = ICM426XX_DATA_CONF_MASK | ICM426XX_UI_SIFS_CFG_MASK;
-	val = 0;
-	if (SLAVE_IS_SPI(s->i2c_spi_addr_flags)) {
-#ifdef CONFIG_SPI_ACCEL_PORT
-		val |= ICM426XX_UI_SIFS_CFG_I2C_DIS;
-#endif
-	} else {
-#ifdef I2C_PORT_ACCEL
-		val |= ICM426XX_UI_SIFS_CFG_SPI_DIS;
+#ifdef CONFIG_ACCELGYRO_ICM_COMM_SPI
+	val = ICM426XX_UI_SIFS_CFG_I2C_DIS;
+#else
+	val = ICM426XX_UI_SIFS_CFG_SPI_DIS;
 #endif
-	}
 
-	return icm_field_update8(s, ICM426XX_REG_INTF_CONFIG0, mask, val);
+	ret = icm_field_update8(s, ICM426XX_REG_INTF_CONFIG0, mask, val);
+	if (ret)
+		return ret;
+
+	/* set accel oscillator to RC clock to avoid bad transition with PLL */
+	return icm_field_update8(s, ICM426XX_REG_INTF_CONFIG1,
+				 ICM426XX_ACCEL_LP_CLK_SEL,
+				 ICM426XX_ACCEL_LP_CLK_SEL);
 }
 
-static int icm426xx_init(const struct motion_sensor_t *s)
+static int icm426xx_init(struct motion_sensor_t *s)
 {
 	struct icm_drv_data_t *st = ICM_GET_DATA(s);
 	struct accelgyro_saved_data_t *saved_data = ICM_GET_SAVED_DATA(s);
@@ -909,29 +912,28 @@ static int icm426xx_init(const struct motion_sensor_t *s)
 		if (ret)
 			goto out_unlock;
 
-#ifdef CONFIG_ACCEL_INTERRUPTS
-		ret = icm426xx_config_interrupt(s);
+		if (IS_ENABLED(ACCELGYRO_ICM426XX_INT_ENABLE))
+			ret = icm426xx_config_interrupt(s);
 		if (ret)
 			goto out_unlock;
-#endif
 	}
 
 	for (i = X; i <= Z; i++)
 		saved_data->scale[i] = MOTION_SENSE_DEFAULT_SCALE;
 
+	saved_data->odr = 0;
+
 	/* set sensor filter */
 	switch (s->type) {
 	case MOTIONSENSE_TYPE_ACCEL:
 		mask = ICM426XX_ACCEL_UI_FILT_MASK;
 		val = ICM426XX_ACCEL_UI_FILT_BW(ICM426XX_FILTER_BW_AVG_16X);
-		if (IS_ENABLED(CONFIG_ACCEL_FIFO))
-			st->accel = (struct motion_sensor_t *)s;
+		st->accel = (struct motion_sensor_t *)s;
 		break;
 	case MOTIONSENSE_TYPE_GYRO:
 		mask = ICM426XX_GYRO_UI_FILT_MASK;
 		val = ICM426XX_GYRO_UI_FILT_BW(ICM426XX_FILTER_BW_ODR_DIV_2);
-		if (IS_ENABLED(CONFIG_ACCEL_FIFO))
-			st->gyro = (struct motion_sensor_t *)s;
+		st->gyro = (struct motion_sensor_t *)s;
 		break;
 	default:
 		ret = EC_ERROR_INVAL;
@@ -950,12 +952,24 @@ static int icm426xx_init(const struct motion_sensor_t *s)
 	return ret;
 }
 
+static int icm426xx_probe(const struct motion_sensor_t *s)
+{
+	int val;
+
+	if (icm_read8(s, ICM426XX_REG_WHO_AM_I, &val) != EC_SUCCESS)
+		return EC_ERROR_NOT_HANDLED;
+
+	if (val != ICM426XX_CHIP_ICM40608 && val != ICM426XX_CHIP_ICM42605)
+		return EC_ERROR_NOT_HANDLED;
+
+	return EC_SUCCESS;
+}
+
 const struct accelgyro_drv icm426xx_drv = {
 	.init = icm426xx_init,
 	.read = icm426xx_read,
 	.read_temp = icm426xx_read_temp,
 	.set_range = icm426xx_set_range,
-	.get_range = icm_get_range,
 	.get_resolution = icm_get_resolution,
 	.set_data_rate = icm426xx_set_data_rate,
 	.get_data_rate = icm_get_data_rate,
@@ -963,7 +977,9 @@ const struct accelgyro_drv icm426xx_drv = {
 	.get_offset = icm426xx_get_offset,
 	.set_scale = icm_set_scale,
 	.get_scale = icm_get_scale,
-#ifdef CONFIG_ACCEL_INTERRUPTS
+	.probe = icm426xx_probe,
+#ifdef ACCELGYRO_ICM426XX_INT_ENABLE
+	.interrupt = icm426xx_interrupt,
 	.irq_handler = icm426xx_irq_handler,
 #endif
 };
diff --git a/driver/accelgyro_icm426xx.h b/driver/accelgyro_icm426xx.h
index 0b4e3aa14a..704256cb68 100644
--- a/driver/accelgyro_icm426xx.h
+++ b/driver/accelgyro_icm426xx.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,64 +15,69 @@
  * 7-bit address is 110100Xb. Where 'X' is determined
  * by the logic level on pin AP_AD0.
  */
-#define ICM426XX_ADDR0_FLAGS		0x68
-#define ICM426XX_ADDR1_FLAGS		0x69
+#define ICM426XX_ADDR0_FLAGS 0x68
+#define ICM426XX_ADDR1_FLAGS 0x69
 
 /* Min and Max sampling frequency in mHz */
-#define ICM426XX_ACCEL_MIN_FREQ	3125
-#define ICM426XX_ACCEL_MAX_FREQ	MOTION_MAX_SENSOR_FREQUENCY(500000, 100000)
-#define ICM426XX_GYRO_MIN_FREQ	12500
-#define ICM426XX_GYRO_MAX_FREQ	MOTION_MAX_SENSOR_FREQUENCY(4000000, 100000)
+#define ICM426XX_ACCEL_MIN_FREQ 3125
+#define ICM426XX_ACCEL_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(500000, 100000)
+#define ICM426XX_GYRO_MIN_FREQ 12500
+#define ICM426XX_GYRO_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(4000000, 100000)
 
 /* Min and Max Accel FS in G */
-#define ICM426XX_ACCEL_FS_MIN_VAL	2
-#define ICM426XX_ACCEL_FS_MAX_VAL	16
+#define ICM426XX_ACCEL_FS_MIN_VAL 2
+#define ICM426XX_ACCEL_FS_MAX_VAL 16
 
 /* Min and Max Gyro FS in dps */
-#define ICM426XX_GYRO_FS_MIN_VAL	125
-#define ICM426XX_GYRO_FS_MAX_VAL	2000
+#define ICM426XX_GYRO_FS_MIN_VAL 125
+#define ICM426XX_GYRO_FS_MAX_VAL 2000
+
+/* accel stabilization time in us */
+#define ICM426XX_ACCEL_START_TIME 20000
+#define ICM426XX_ACCEL_STOP_TIME 0
+
+/* gyro stabilization time in us */
+#define ICM426XX_GYRO_START_TIME 60000
+#define ICM426XX_GYRO_STOP_TIME 150000
 
 /* Reg value from Accel FS in G */
-#define ICM426XX_ACCEL_FS_TO_REG(_fs)	((_fs) < 2 ? 3 : \
-					(_fs) > 16 ? 0 : \
-					3 - __fls((_fs) / 2))
+#define ICM426XX_ACCEL_FS_TO_REG(_fs) \
+	((_fs) < 2 ? 3 : (_fs) > 16 ? 0 : 3 - __fls((_fs) / 2))
 
 /* Accel FSR in G from Reg value */
-#define ICM426XX_ACCEL_REG_TO_FS(_reg)	((1 << (3 - (_reg))) * 2)
+#define ICM426XX_ACCEL_REG_TO_FS(_reg) ((1 << (3 - (_reg))) * 2)
 
 /* Reg value from Gyro FS in dps */
-#define ICM426XX_GYRO_FS_TO_REG(_fs)	((_fs) < 125 ? 4 : \
-					(_fs) > 2000 ? 0 : \
-					4 - __fls((_fs) / 125))
+#define ICM426XX_GYRO_FS_TO_REG(_fs) \
+	((_fs) < 125 ? 4 : (_fs) > 2000 ? 0 : 4 - __fls((_fs) / 125))
 
 /* Gyro FSR in dps from Reg value */
-#define ICM426XX_GYRO_REG_TO_FS(_reg)	((1 << (4 - (_reg))) * 125)
+#define ICM426XX_GYRO_REG_TO_FS(_reg) ((1 << (4 - (_reg))) * 125)
 
 /* Reg value from ODR in mHz */
-#define ICM426XX_ODR_TO_REG(_odr)	((_odr) <= 200000 ? \
-					13 - __fls((_odr) / 3125) : \
-					(_odr) < 500000 ? 7 : \
-					(_odr) < 1000000 ? 15 : \
-					6 - __fls((_odr) / 1000000))
+#define ICM426XX_ODR_TO_REG(_odr)                       \
+	((_odr) <= 200000 ? 13 - __fls((_odr) / 3125) : \
+	 (_odr) < 500000  ? 7 :                         \
+	 (_odr) < 1000000 ? 15 :                        \
+			    6 - __fls((_odr) / 1000000))
 
 /* ODR in mHz from Reg value */
-#define ICM426XX_REG_TO_ODR(_reg)	((_reg) == 15 ? 500000 : \
-					(_reg) >= 7 ? \
-					(1 << (13 - (_reg))) * 3125 : \
-					(1 << (6 - (_reg))) * 1000000)
+#define ICM426XX_REG_TO_ODR(_reg)                     \
+	((_reg) == 15 ? 500000 :                      \
+	 (_reg) >= 7  ? (1 << (13 - (_reg))) * 3125 : \
+			(1 << (6 - (_reg))) * 1000000)
 
 /* Reg value for the next higher ODR */
-#define ICM426XX_ODR_REG_UP(_reg)	((_reg) == 15 ? 6 : \
-					(_reg) == 7 ? 15 : \
-					(_reg) - 1)
+#define ICM426XX_ODR_REG_UP(_reg) \
+	((_reg) == 15 ? 6 : (_reg) == 7 ? 15 : (_reg)-1)
 
 /*
  * Register addresses are virtual address on 16 bits.
  * MSB is coding register bank and LSB real register address.
  * ex: bank 4, register 1F => 0x041F
  */
-#define ICM426XX_REG_DEVICE_CONFIG	0x0011
-#define ICM426XX_SOFT_RESET_CONFIG	BIT(0)
+#define ICM426XX_REG_DEVICE_CONFIG 0x0011
+#define ICM426XX_SOFT_RESET_CONFIG BIT(0)
 
 enum icm426xx_slew_rate {
 	ICM426XX_SLEW_RATE_20NS_60NS,
@@ -82,60 +87,63 @@ enum icm426xx_slew_rate {
 	ICM426XX_SLEW_RATE_2NS_6NS,
 	ICM426XX_SLEW_RATE_INF_2NS,
 };
-#define ICM426XX_REG_DRIVE_CONFIG	0x0013
-#define ICM426XX_DRIVE_CONFIG_MASK	GENMASK(5, 0)
-#define ICM426XX_I2C_SLEW_RATE(_s)	(((_s) & 0x07) << 3)
-#define ICM426XX_SPI_SLEW_RATE(_s)	((_s) & 0x07)
+#define ICM426XX_REG_DRIVE_CONFIG 0x0013
+#define ICM426XX_DRIVE_CONFIG_MASK GENMASK(5, 0)
+#define ICM426XX_I2C_SLEW_RATE(_s) (((_s)&0x07) << 3)
+#define ICM426XX_SPI_SLEW_RATE(_s) ((_s)&0x07)
 
 /* default int configuration is pulsed mode, open drain, and active low */
-#define ICM426XX_REG_INT_CONFIG		0x0014
-#define ICM426XX_INT2_LATCHED		BIT(5)
-#define ICM426XX_INT2_PUSH_PULL		BIT(4)
-#define ICM426XX_INT2_ACTIVE_HIGH	BIT(3)
-#define ICM426XX_INT1_LATCHED		BIT(2)
-#define ICM426XX_INT1_PUSH_PULL		BIT(1)
-#define ICM426XX_INT1_ACTIVE_HIGH	BIT(0)
-
-#define ICM426XX_REG_FIFO_CONFIG	0x0016
-#define ICM426XX_FIFO_MODE_BYPASS	(0x00 << 6)
-#define ICM426XX_FIFO_MODE_STREAM	(0x01 << 6)
-#define ICM426XX_FIFO_MODE_STOP_FULL	(0x02 << 6)
+#define ICM426XX_REG_INT_CONFIG 0x0014
+#define ICM426XX_INT2_LATCHED BIT(5)
+#define ICM426XX_INT2_PUSH_PULL BIT(4)
+#define ICM426XX_INT2_ACTIVE_HIGH BIT(3)
+#define ICM426XX_INT1_LATCHED BIT(2)
+#define ICM426XX_INT1_PUSH_PULL BIT(1)
+#define ICM426XX_INT1_ACTIVE_HIGH BIT(0)
+
+#define ICM426XX_REG_FIFO_CONFIG 0x0016
+#define ICM426XX_FIFO_MODE_BYPASS (0x00 << 6)
+#define ICM426XX_FIFO_MODE_STREAM (0x01 << 6)
+#define ICM426XX_FIFO_MODE_STOP_FULL (0x02 << 6)
 
 /* data are 16 bits */
-#define ICM426XX_REG_TEMP_DATA		0x001D
+#define ICM426XX_REG_TEMP_DATA 0x001D
 /* X + Y + Z: 3 * 16 bits */
-#define ICM426XX_REG_ACCEL_DATA_XYZ	0x001F
-#define ICM426XX_REG_GYRO_DATA_XYZ	0x0025
+#define ICM426XX_REG_ACCEL_DATA_XYZ 0x001F
+#define ICM426XX_REG_GYRO_DATA_XYZ 0x0025
 
-#define ICM426XX_INVALID_DATA		-32768
+#define ICM426XX_INVALID_DATA -32768
 
-#define ICM426XX_REG_INT_STATUS		0x002D
-#define ICM426XX_UI_FSYNC_INT		BIT(6)
-#define ICM426XX_PLL_RDY_INT		BIT(5)
-#define ICM426XX_RESET_DONE_INT		BIT(4)
-#define ICM426XX_DATA_RDY_INT		BIT(3)
-#define ICM426XX_FIFO_THS_INT		BIT(2)
-#define ICM426XX_FIFO_FULL_INT		BIT(1)
-#define ICM426XX_AGC_RDY_INT		BIT(0)
+#define ICM426XX_REG_INT_STATUS 0x002D
+#define ICM426XX_UI_FSYNC_INT BIT(6)
+#define ICM426XX_PLL_RDY_INT BIT(5)
+#define ICM426XX_RESET_DONE_INT BIT(4)
+#define ICM426XX_DATA_RDY_INT BIT(3)
+#define ICM426XX_FIFO_THS_INT BIT(2)
+#define ICM426XX_FIFO_FULL_INT BIT(1)
+#define ICM426XX_AGC_RDY_INT BIT(0)
 
 /* FIFO count is 16 bits */
-#define ICM426XX_REG_FIFO_COUNT		0x002E
-#define ICM426XX_REG_FIFO_DATA		0x0030
-
-#define ICM426XX_REG_SIGNAL_PATH_RESET	0x004B
-#define ICM426XX_ABORT_AND_RESET	BIT(3)
-#define ICM426XX_TMST_STROBE		BIT(2)
-#define ICM426XX_FIFO_FLUSH		BIT(1)
-
-#define ICM426XX_REG_INTF_CONFIG0	0x004C
-#define ICM426XX_DATA_CONF_MASK		GENMASK(7, 4)
-#define ICM426XX_FIFO_HOLD_LAST_DATA	BIT(7)
-#define ICM426XX_FIFO_COUNT_REC		BIT(6)
-#define ICM426XX_FIFO_COUNT_BE		BIT(5)
-#define ICM426XX_SENSOR_DATA_BE		BIT(4)
-#define ICM426XX_UI_SIFS_CFG_MASK	GENMASK(1, 0)
-#define ICM426XX_UI_SIFS_CFG_SPI_DIS	0x02
-#define ICM426XX_UI_SIFS_CFG_I2C_DIS	0x03
+#define ICM426XX_REG_FIFO_COUNT 0x002E
+#define ICM426XX_REG_FIFO_DATA 0x0030
+
+#define ICM426XX_REG_SIGNAL_PATH_RESET 0x004B
+#define ICM426XX_ABORT_AND_RESET BIT(3)
+#define ICM426XX_TMST_STROBE BIT(2)
+#define ICM426XX_FIFO_FLUSH BIT(1)
+
+#define ICM426XX_REG_INTF_CONFIG0 0x004C
+#define ICM426XX_DATA_CONF_MASK GENMASK(7, 4)
+#define ICM426XX_FIFO_HOLD_LAST_DATA BIT(7)
+#define ICM426XX_FIFO_COUNT_REC BIT(6)
+#define ICM426XX_FIFO_COUNT_BE BIT(5)
+#define ICM426XX_SENSOR_DATA_BE BIT(4)
+#define ICM426XX_UI_SIFS_CFG_MASK GENMASK(1, 0)
+#define ICM426XX_UI_SIFS_CFG_SPI_DIS 0x02
+#define ICM426XX_UI_SIFS_CFG_I2C_DIS 0x03
+
+#define ICM426XX_REG_INTF_CONFIG1 0x004D
+#define ICM426XX_ACCEL_LP_CLK_SEL BIT(3)
 
 enum icm426xx_sensor_mode {
 	ICM426XX_MODE_OFF,
@@ -143,20 +151,20 @@ enum icm426xx_sensor_mode {
 	ICM426XX_MODE_LOW_POWER,
 	ICM426XX_MODE_LOW_NOISE,
 };
-#define ICM426XX_REG_PWR_MGMT0		0x004E
-#define ICM426XX_TEMP_DIS		BIT(5)
-#define ICM426XX_IDLE			BIT(4)
-#define ICM426XX_GYRO_MODE_MASK		GENMASK(3, 2)
-#define ICM426XX_GYRO_MODE(_m)		(((_m) & 0x03) << 2)
-#define ICM426XX_ACCEL_MODE_MASK	GENMASK(1, 0)
-#define ICM426XX_ACCEL_MODE(_m)		((_m) & 0x03)
-
-#define ICM426XX_REG_GYRO_CONFIG0	0x004F
-#define ICM426XX_REG_ACCEL_CONFIG0	0x0050
-#define ICM426XX_FS_MASK		GENMASK(7, 5)
-#define ICM426XX_FS_SEL(_fs)		(((_fs) & 0x07) << 5)
-#define ICM426XX_ODR_MASK		GENMASK(3, 0)
-#define ICM426XX_ODR(_odr)		((_odr) & 0x0F)
+#define ICM426XX_REG_PWR_MGMT0 0x004E
+#define ICM426XX_TEMP_DIS BIT(5)
+#define ICM426XX_IDLE BIT(4)
+#define ICM426XX_GYRO_MODE_MASK GENMASK(3, 2)
+#define ICM426XX_GYRO_MODE(_m) (((_m)&0x03) << 2)
+#define ICM426XX_ACCEL_MODE_MASK GENMASK(1, 0)
+#define ICM426XX_ACCEL_MODE(_m) ((_m)&0x03)
+
+#define ICM426XX_REG_GYRO_CONFIG0 0x004F
+#define ICM426XX_REG_ACCEL_CONFIG0 0x0050
+#define ICM426XX_FS_MASK GENMASK(7, 5)
+#define ICM426XX_FS_SEL(_fs) (((_fs)&0x07) << 5)
+#define ICM426XX_ODR_MASK GENMASK(3, 0)
+#define ICM426XX_ODR(_odr) ((_odr)&0x0F)
 
 enum icm426xx_filter_bw {
 	/* low noise mode */
@@ -167,90 +175,108 @@ enum icm426xx_filter_bw {
 	ICM426XX_FILTER_BW_AVG_16X = 6,
 };
 
-#define ICM426XX_REG_GYRO_ACCEL_CONFIG0	0x0052
-#define ICM426XX_ACCEL_UI_FILT_MASK	GENMASK(7, 4)
-#define ICM426XX_ACCEL_UI_FILT_BW(_f)	(((_f) & 0x0F) << 4)
-#define ICM426XX_GYRO_UI_FILT_MASK	GENMASK(3, 0)
-#define ICM426XX_GYRO_UI_FILT_BW(_f)	((_f) & 0x0F)
-
-#define ICM426XX_REG_FIFO_CONFIG1	0x005F
-#define ICM426XX_FIFO_PARTIAL_READ	BIT(6)
-#define ICM426XX_FIFO_WM_GT_TH		BIT(5)
-#define ICM426XX_FIFO_EN_MASK		GENMASK(3, 0)
-#define ICM426XX_FIFO_TMST_FSYNC_EN	BIT(3)
-#define ICM426XX_FIFO_TEMP_EN		BIT(2)
-#define ICM426XX_FIFO_GYRO_EN		BIT(1)
-#define ICM426XX_FIFO_ACCEL_EN		BIT(0)
+#define ICM426XX_REG_GYRO_ACCEL_CONFIG0 0x0052
+#define ICM426XX_ACCEL_UI_FILT_MASK GENMASK(7, 4)
+#define ICM426XX_ACCEL_UI_FILT_BW(_f) (((_f)&0x0F) << 4)
+#define ICM426XX_GYRO_UI_FILT_MASK GENMASK(3, 0)
+#define ICM426XX_GYRO_UI_FILT_BW(_f) ((_f)&0x0F)
+
+#define ICM426XX_REG_FIFO_CONFIG1 0x005F
+#define ICM426XX_FIFO_PARTIAL_READ BIT(6)
+#define ICM426XX_FIFO_WM_GT_TH BIT(5)
+#define ICM426XX_FIFO_EN_MASK GENMASK(3, 0)
+#define ICM426XX_FIFO_TMST_FSYNC_EN BIT(3)
+#define ICM426XX_FIFO_TEMP_EN BIT(2)
+#define ICM426XX_FIFO_GYRO_EN BIT(1)
+#define ICM426XX_FIFO_ACCEL_EN BIT(0)
 
 /* FIFO watermark value is 16 bits little endian */
-#define ICM426XX_REG_FIFO_WATERMARK	0x0060
-
-#define ICM426XX_REG_INT_CONFIG1	0x0064
-#define ICM426XX_INT_PULSE_DURATION	BIT(6)
-#define ICM426XX_INT_TDEASSERT_DIS	BIT(5)
-#define ICM426XX_INT_ASYNC_RESET	BIT(4)
-
-#define ICM426XX_REG_INT_SOURCE0	0x0065
-#define ICM426XX_UI_FSYNC_INT1_EN	BIT(6)
-#define ICM426XX_PLL_RDY_INT1_EN	BIT(5)
-#define ICM426XX_RESET_DONE_INT1_EN	BIT(4)
-#define ICM426XX_UI_DRDY_INT1_EN	BIT(3)
-#define ICM426XX_FIFO_THS_INT1_EN	BIT(2)
-#define ICM426XX_FIFO_FULL_INT1_EN	BIT(1)
-#define ICM426XX_UI_AGC_RDY_INT1_EN	BIT(0)
-
-#define ICM426XX_REG_INT_SOURCE3	0x0068
-#define ICM426XX_UI_FSYNC_INT2_EN	BIT(6)
-#define ICM426XX_PLL_RDY_INT2_EN	BIT(5)
-#define ICM426XX_RESET_DONE_INT2_EN	BIT(4)
-#define ICM426XX_UI_DRDY_INT2_EN	BIT(3)
-#define ICM426XX_FIFO_THS_INT2_EN	BIT(2)
-#define ICM426XX_FIFO_FULL_INT2_EN	BIT(1)
-#define ICM426XX_UI_AGC_RDY_INT2_EN	BIT(0)
-
-#define ICM426XX_REG_WHO_AM_I		0x0075
-#define ICM426XX_CHIP_ICM40608		0x39
-#define ICM426XX_CHIP_ICM42605		0x42
-
-#define ICM426XX_REG_BANK_SEL		0x0076
-#define ICM426XX_BANK_SEL(_b)		((_b) & 0x07)
-
-#define ICM426XX_REG_INTF_CONFIG4	0x017A
-#define ICM426XX_I3C_BUS_MODE		BIT(6)
-#define ICM426XX_SPI_AP_4WIRE		BIT(1)
-
-#define ICM426XX_REG_INTF_CONFIG5	0x017B
-#define ICM426XX_PIN9_FUNC_INT2		(0x00 << 1)
-#define ICM426XX_PIN9_FUNC_FSYNC	(0x01 << 1)
-
-#define ICM426XX_REG_INTF_CONFIG6	0x017C
-#define ICM426XX_INTF_CONFIG6_MASK	GENMASK(4, 0)
-#define ICM426XX_I3C_EN			BIT(4)
-#define ICM426XX_I3C_IBI_BYTE_EN	BIT(3)
-#define ICM426XX_I3C_IBI_EN		BIT(2)
-#define ICM426XX_I3C_DDR_EN		BIT(1)
-#define ICM426XX_I3C_SDR_EN		BIT(0)
-
-#define ICM426XX_REG_INT_SOURCE8	0x044F
-#define ICM426XX_FSYNC_IBI_EN		BIT(5)
-#define ICM426XX_PLL_RDY_IBI_EN		BIT(4)
-#define ICM426XX_UI_DRDY_IBI_EN		BIT(3)
-#define ICM426XX_FIFO_THS_IBI_EN	BIT(2)
-#define ICM426XX_FIFO_FULL_IBI_EN	BIT(1)
-#define ICM426XX_AGC_RDY_IBI_EN		BIT(0)
-
-#define ICM426XX_REG_OFFSET_USER0	0x0477
-#define ICM426XX_REG_OFFSET_USER1	0x0478
-#define ICM426XX_REG_OFFSET_USER2	0x0479
-#define ICM426XX_REG_OFFSET_USER3	0x047A
-#define ICM426XX_REG_OFFSET_USER4	0x047B
-#define ICM426XX_REG_OFFSET_USER5	0x047C
-#define ICM426XX_REG_OFFSET_USER6	0x047D
-#define ICM426XX_REG_OFFSET_USER7	0x047E
-#define ICM426XX_REG_OFFSET_USER8	0x047F
+#define ICM426XX_REG_FIFO_WATERMARK 0x0060
+
+#define ICM426XX_REG_INT_CONFIG1 0x0064
+#define ICM426XX_INT_PULSE_DURATION BIT(6)
+#define ICM426XX_INT_TDEASSERT_DIS BIT(5)
+#define ICM426XX_INT_ASYNC_RESET BIT(4)
+
+#define ICM426XX_REG_INT_SOURCE0 0x0065
+#define ICM426XX_UI_FSYNC_INT1_EN BIT(6)
+#define ICM426XX_PLL_RDY_INT1_EN BIT(5)
+#define ICM426XX_RESET_DONE_INT1_EN BIT(4)
+#define ICM426XX_UI_DRDY_INT1_EN BIT(3)
+#define ICM426XX_FIFO_THS_INT1_EN BIT(2)
+#define ICM426XX_FIFO_FULL_INT1_EN BIT(1)
+#define ICM426XX_UI_AGC_RDY_INT1_EN BIT(0)
+
+#define ICM426XX_REG_INT_SOURCE3 0x0068
+#define ICM426XX_UI_FSYNC_INT2_EN BIT(6)
+#define ICM426XX_PLL_RDY_INT2_EN BIT(5)
+#define ICM426XX_RESET_DONE_INT2_EN BIT(4)
+#define ICM426XX_UI_DRDY_INT2_EN BIT(3)
+#define ICM426XX_FIFO_THS_INT2_EN BIT(2)
+#define ICM426XX_FIFO_FULL_INT2_EN BIT(1)
+#define ICM426XX_UI_AGC_RDY_INT2_EN BIT(0)
+
+#define ICM426XX_REG_WHO_AM_I 0x0075
+#define ICM426XX_CHIP_ICM40608 0x39
+#define ICM426XX_CHIP_ICM42605 0x42
+
+#define ICM426XX_REG_BANK_SEL 0x0076
+#define ICM426XX_BANK_SEL(_b) ((_b)&0x07)
+
+#define ICM426XX_REG_INTF_CONFIG4 0x017A
+#define ICM426XX_I3C_BUS_MODE BIT(6)
+#define ICM426XX_SPI_AP_4WIRE BIT(1)
+
+#define ICM426XX_REG_INTF_CONFIG5 0x017B
+#define ICM426XX_PIN9_FUNC_INT2 (0x00 << 1)
+#define ICM426XX_PIN9_FUNC_FSYNC (0x01 << 1)
+
+#define ICM426XX_REG_INTF_CONFIG6 0x017C
+#define ICM426XX_INTF_CONFIG6_MASK GENMASK(4, 0)
+#define ICM426XX_I3C_EN BIT(4)
+#define ICM426XX_I3C_IBI_BYTE_EN BIT(3)
+#define ICM426XX_I3C_IBI_EN BIT(2)
+#define ICM426XX_I3C_DDR_EN BIT(1)
+#define ICM426XX_I3C_SDR_EN BIT(0)
+
+#define ICM426XX_REG_INT_SOURCE8 0x044F
+#define ICM426XX_FSYNC_IBI_EN BIT(5)
+#define ICM426XX_PLL_RDY_IBI_EN BIT(4)
+#define ICM426XX_UI_DRDY_IBI_EN BIT(3)
+#define ICM426XX_FIFO_THS_IBI_EN BIT(2)
+#define ICM426XX_FIFO_FULL_IBI_EN BIT(1)
+#define ICM426XX_AGC_RDY_IBI_EN BIT(0)
+
+#define ICM426XX_REG_OFFSET_USER0 0x0477
+#define ICM426XX_REG_OFFSET_USER1 0x0478
+#define ICM426XX_REG_OFFSET_USER2 0x0479
+#define ICM426XX_REG_OFFSET_USER3 0x047A
+#define ICM426XX_REG_OFFSET_USER4 0x047B
+#define ICM426XX_REG_OFFSET_USER5 0x047C
+#define ICM426XX_REG_OFFSET_USER6 0x047D
+#define ICM426XX_REG_OFFSET_USER7 0x047E
+#define ICM426XX_REG_OFFSET_USER8 0x047F
 
 extern const struct accelgyro_drv icm426xx_drv;
 
 void icm426xx_interrupt(enum gpio_signal signal);
 
+#if defined(CONFIG_ZEPHYR)
+#if DT_NODE_EXISTS(DT_ALIAS(icm426xx_int))
+
+/* Get the motion sensor ID of the ICM426xx sensor that generates the interrupt.
+ * The interrupt is converted to the event and transferred to motion sense task
+ * that actually handles the interrupt.
+ *
+ * Here we use an alias (icm426xx_int) to get the motion sensor ID. This alias
+ * MUST be defined for this driver to work.
+ * aliases {
+ *   icm426xx-int = &base_accel;
+ * };
+ */
+#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(SENSOR_ID(DT_ALIAS(icm426xx_int)))
+#endif
+#endif /* defined(CONFIG_ZEPHYR) */
+
 #endif /* __CROS_EC_ACCELGYRO_ICM426XX_H */
diff --git a/driver/accelgyro_icm_common.c b/driver/accelgyro_icm_common.c
index 03a736e76b..44a3b61370 100644
--- a/driver/accelgyro_icm_common.c
+++ b/driver/accelgyro_icm_common.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,18 +10,18 @@
 
 #include "accelgyro.h"
 #include "console.h"
+#include "driver/accelgyro_icm426xx.h"
+#include "driver/accelgyro_icm_common.h"
 #include "i2c.h"
 #include "spi.h"
-#include "driver/accelgyro_icm_common.h"
-#include "driver/accelgyro_icm426xx.h"
 
 #define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args)
 
-#ifdef CONFIG_SPI_ACCEL_PORT
-static int icm_spi_raw_read(const int addr, const uint8_t reg,
-			    uint8_t *data, const int len)
+#ifdef CONFIG_ACCELGYRO_ICM_COMM_SPI
+static int icm_spi_raw_read(const int addr, const uint8_t reg, uint8_t *data,
+			    const int len)
 {
 	uint8_t cmd = 0x80 | reg;
 
@@ -54,19 +54,13 @@ static int icm_bank_sel(const struct motion_sensor_t *s, const int reg)
 	if (bank == st->bank)
 		return EC_SUCCESS;
 
-	ret = EC_ERROR_UNIMPLEMENTED;
-	if (SLAVE_IS_SPI(s->i2c_spi_addr_flags)) {
-#ifdef CONFIG_SPI_ACCEL_PORT
-		ret = icm_spi_raw_write(
-				SLAVE_GET_SPI_ADDR(s->i2c_spi_addr_flags),
+#ifdef CONFIG_ACCELGYRO_ICM_COMM_SPI
+	ret = icm_spi_raw_write(ACCEL_GET_SPI_ADDR(s->i2c_spi_addr_flags),
 				ICM426XX_REG_BANK_SEL, &bank, 1);
+#else
+	ret = i2c_write8(s->port, s->i2c_spi_addr_flags, ICM426XX_REG_BANK_SEL,
+			 bank);
 #endif
-	} else {
-#ifdef I2C_PORT_ACCEL
-		ret = i2c_write8(s->port, s->i2c_spi_addr_flags,
-				 ICM426XX_REG_BANK_SEL, bank);
-#endif
-	}
 
 	if (ret == EC_SUCCESS)
 		st->bank = bank;
@@ -86,22 +80,19 @@ int icm_read8(const struct motion_sensor_t *s, const int reg, int *data_ptr)
 	if (ret != EC_SUCCESS)
 		return ret;
 
-	ret = EC_ERROR_UNIMPLEMENTED;
-	if (SLAVE_IS_SPI(s->i2c_spi_addr_flags)) {
-#ifdef CONFIG_SPI_ACCEL_PORT
+#ifdef CONFIG_ACCELGYRO_ICM_COMM_SPI
+	{
 		uint8_t val;
 
 		ret = icm_spi_raw_read(
-				SLAVE_GET_SPI_ADDR(s->i2c_spi_addr_flags),
-				addr, &val, sizeof(val));
+			ACCEL_GET_SPI_ADDR(s->i2c_spi_addr_flags), addr, &val,
+			sizeof(val));
 		if (ret == EC_SUCCESS)
 			*data_ptr = val;
-#endif
-	} else {
-#ifdef I2C_PORT_ACCEL
-		ret = i2c_read8(s->port, s->i2c_spi_addr_flags, addr, data_ptr);
-#endif
 	}
+#else
+	ret = i2c_read8(s->port, s->i2c_spi_addr_flags, addr, data_ptr);
+#endif
 
 	return ret;
 }
@@ -118,20 +109,17 @@ int icm_write8(const struct motion_sensor_t *s, const int reg, int data)
 	if (ret != EC_SUCCESS)
 		return ret;
 
-	ret = EC_ERROR_UNIMPLEMENTED;
-	if (SLAVE_IS_SPI(s->i2c_spi_addr_flags)) {
-#ifdef CONFIG_SPI_ACCEL_PORT
+#ifdef CONFIG_ACCELGYRO_ICM_COMM_SPI
+	{
 		uint8_t val = data;
 
 		ret = icm_spi_raw_write(
-				LAVE_GET_SPI_ADDR(s->i2c_spi_addr_flags),
-				addr, &val, sizeof(val));
-#endif
-	} else {
-#ifdef I2C_PORT_ACCEL
-		ret = i2c_write8(s->port, s->i2c_spi_addr_flags, addr, data);
-#endif
+			ACCEL_GET_SPI_ADDR(s->i2c_spi_addr_flags), addr, &val,
+			sizeof(val));
 	}
+#else
+	ret = i2c_write8(s->port, s->i2c_spi_addr_flags, addr, data);
+#endif
 
 	return ret;
 }
@@ -148,27 +136,23 @@ int icm_read16(const struct motion_sensor_t *s, const int reg, int *data_ptr)
 	if (ret != EC_SUCCESS)
 		return ret;
 
-	ret = EC_ERROR_UNIMPLEMENTED;
-	if (SLAVE_IS_SPI(s->i2c_spi_addr_flags)) {
-#ifdef CONFIG_SPI_ACCEL_PORT
+#ifdef CONFIG_ACCELGYRO_ICM_COMM_SPI
+	{
 		uint8_t val[2];
 
 		ret = icm_spi_raw_read(
-				LAVE_GET_SPI_ADDR(s->i2c_spi_addr_flags),
-				addr, val, sizeof(val));
+			ACCEL_GET_SPI_ADDR(s->i2c_spi_addr_flags), addr, val,
+			sizeof(val));
 		if (ret == EC_SUCCESS) {
 			if (I2C_IS_BIG_ENDIAN(s->i2c_spi_addr_flags))
 				*data_ptr = ((int)val[0] << 8) | val[1];
 			else
 				*data_ptr = ((int)val[1] << 8) | val[0];
 		}
-#endif
-	} else {
-#ifdef I2C_PORT_ACCEL
-		ret = i2c_read16(s->port, s->i2c_spi_addr_flags,
-				addr, data_ptr);
-#endif
 	}
+#else
+	ret = i2c_read16(s->port, s->i2c_spi_addr_flags, addr, data_ptr);
+#endif
 
 	return ret;
 }
@@ -185,9 +169,8 @@ int icm_write16(const struct motion_sensor_t *s, const int reg, int data)
 	if (ret != EC_SUCCESS)
 		return ret;
 
-	ret = EC_ERROR_UNIMPLEMENTED;
-	if (SLAVE_IS_SPI(s->i2c_spi_addr_flags)) {
-#ifdef CONFIG_SPI_ACCEL_PORT
+#ifdef CONFIG_ACCELGYRO_ICM_COMM_SPI
+	{
 		uint8_t val[2];
 
 		if (I2C_IS_BIG_ENDIAN(s->i2c_spi_addr_flags)) {
@@ -198,14 +181,12 @@ int icm_write16(const struct motion_sensor_t *s, const int reg, int data)
 			val[1] = (data >> 8) & 0xFF;
 		}
 		ret = icm_spi_raw_write(
-				LAVE_GET_SPI_ADDR(s->i2c_spi_addr_flags),
-				addr, val, sizeof(val));
-#endif
-	} else {
-#ifdef I2C_PORT_ACCEL
-		ret = i2c_write16(s->port, s->i2c_spi_addr_flags, addr, data);
-#endif
+			ACCEL_GET_SPI_ADDR(s->i2c_spi_addr_flags), addr, val,
+			sizeof(val));
 	}
+#else
+	ret = i2c_write16(s->port, s->i2c_spi_addr_flags, addr, data);
+#endif
 
 	return ret;
 }
@@ -223,19 +204,13 @@ int icm_read_n(const struct motion_sensor_t *s, const int reg,
 	if (ret != EC_SUCCESS)
 		return ret;
 
-	ret = EC_ERROR_UNIMPLEMENTED;
-	if (SLAVE_IS_SPI(s->i2c_spi_addr_flags)) {
-#ifdef CONFIG_SPI_ACCEL_PORT
-		ret = icm_spi_raw_read(
-				SLAVE_GET_SPI_ADDR(s->i2c_spi_addr_flags),
-				addr, data_ptr, len);
-#endif
-	} else {
-#ifdef I2C_PORT_ACCEL
-		ret = i2c_read_block(s->port, s->i2c_spi_addr_flags, addr,
-				     data_ptr, len);
+#ifdef CONFIG_ACCELGYRO_ICM_COMM_SPI
+	ret = icm_spi_raw_read(ACCEL_GET_SPI_ADDR(s->i2c_spi_addr_flags), addr,
+			       data_ptr, len);
+#else
+	ret = i2c_read_block(s->port, s->i2c_spi_addr_flags, addr, data_ptr,
+			     len);
 #endif
-	}
 
 	return ret;
 }
@@ -251,28 +226,26 @@ int icm_field_update8(const struct motion_sensor_t *s, const int reg,
 		return ret;
 
 	ret = EC_ERROR_UNIMPLEMENTED;
-	if (SLAVE_IS_SPI(s->i2c_spi_addr_flags)) {
-#ifdef CONFIG_SPI_ACCEL_PORT
+#ifdef CONFIG_ACCELGYRO_ICM_COMM_SPI
+	{
 		uint8_t val;
 
 		ret = icm_spi_raw_read(
-				SLAVE_GET_SPI_ADDR(s->i2c_spi_addr_flags),
-				addr, &val, sizeof(val));
+			ACCEL_GET_SPI_ADDR(s->i2c_spi_addr_flags), addr, &val,
+			sizeof(val));
 		if (ret != EC_SUCCESS)
 			return ret;
 
 		val = (val & (~field_mask)) | set_value;
 
 		ret = icm_spi_raw_write(
-				SLAVE_GET_SPI_ADDR(s->i2c_spi_addr_flags),
-				addr, &val, sizeof(val));
-#endif
-	} else {
-#ifdef I2C_PORT_ACCEL
-		ret = i2c_field_update8(s->port, s->i2c_spi_addr_flags, addr,
-					field_mask, set_value);
-#endif
+			ACCEL_GET_SPI_ADDR(s->i2c_spi_addr_flags), addr, &val,
+			sizeof(val));
 	}
+#else
+	ret = i2c_field_update8(s->port, s->i2c_spi_addr_flags, addr,
+				field_mask, set_value);
+#endif
 
 	return ret;
 }
@@ -282,13 +255,6 @@ int icm_get_resolution(const struct motion_sensor_t *s)
 	return ICM_RESOLUTION;
 }
 
-int icm_get_range(const struct motion_sensor_t *s)
-{
-	struct accelgyro_saved_data_t *data = ICM_GET_SAVED_DATA(s);
-
-	return data->range;
-}
-
 int icm_get_data_rate(const struct motion_sensor_t *s)
 {
 	struct accelgyro_saved_data_t *data = ICM_GET_SAVED_DATA(s);
@@ -320,12 +286,12 @@ int icm_get_scale(const struct motion_sensor_t *s, uint16_t *scale,
 }
 
 /* FIFO header: 1 byte */
-#define ICM_FIFO_HEADER_MSG		BIT(7)
-#define ICM_FIFO_HEADER_ACCEL		BIT(6)
-#define ICM_FIFO_HEADER_GYRO		BIT(5)
-#define ICM_FIFO_HEADER_TMST_FSYNC	GENMASK(3, 2)
-#define ICM_FIFO_HEADER_ODR_ACCEL	BIT(1)
-#define ICM_FIFO_HEADER_ODR_GYRO	BIT(0)
+#define ICM_FIFO_HEADER_MSG BIT(7)
+#define ICM_FIFO_HEADER_ACCEL BIT(6)
+#define ICM_FIFO_HEADER_GYRO BIT(5)
+#define ICM_FIFO_HEADER_TMST_FSYNC GENMASK(3, 2)
+#define ICM_FIFO_HEADER_ODR_ACCEL BIT(1)
+#define ICM_FIFO_HEADER_ODR_GYRO BIT(0)
 
 /* FIFO data packet */
 struct icm_fifo_sensor_data {
@@ -339,7 +305,7 @@ struct icm_fifo_1sensor_packet {
 	struct icm_fifo_sensor_data data;
 	int8_t temp;
 } __packed;
-#define ICM_FIFO_1SENSOR_PACKET_SIZE	8
+#define ICM_FIFO_1SENSOR_PACKET_SIZE 8
 
 struct icm_fifo_2sensors_packet {
 	uint8_t header;
@@ -348,10 +314,10 @@ struct icm_fifo_2sensors_packet {
 	int8_t temp;
 	uint16_t timestamp;
 } __packed;
-#define ICM_FIFO_2SENSORS_PACKET_SIZE	16
+#define ICM_FIFO_2SENSORS_PACKET_SIZE 16
 
 ssize_t icm_fifo_decode_packet(const void *packet, const uint8_t **accel,
-		const uint8_t **gyro)
+			       const uint8_t **gyro)
 {
 	const struct icm_fifo_1sensor_packet *pack1 = packet;
 	const struct icm_fifo_2sensors_packet *pack2 = packet;
diff --git a/driver/accelgyro_icm_common.h b/driver/accelgyro_icm_common.h
index 4d991ce341..32adf6f5ff 100644
--- a/driver/accelgyro_icm_common.h
+++ b/driver/accelgyro_icm_common.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,38 +9,47 @@
 #define __CROS_EC_ACCELGYRO_ICM_COMMON_H
 
 #include "accelgyro.h"
+#include "builtin/stddef.h"
+#include "hwtimer.h"
+#include "timer.h"
+
+#include <sys/types.h>
+
+#if !defined(CONFIG_ACCELGYRO_ICM_COMM_SPI) && \
+	!defined(CONFIG_ACCELGYRO_ICM_COMM_I2C)
+#error "ICM must use either SPI or I2C communication"
+#endif
 
 #ifdef CONFIG_ACCEL_FIFO
 /* reserve maximum 4 samples of 16 bytes */
-#define ICM_FIFO_BUFFER	64
+#define ICM_FIFO_BUFFER 64
 #else
-#define ICM_FIFO_BUFFER	0
+#define ICM_FIFO_BUFFER 0
 #endif
 
 struct icm_drv_data_t {
 	struct accelgyro_saved_data_t saved_data[2];
 	struct motion_sensor_t *accel;
 	struct motion_sensor_t *gyro;
+	uint32_t stabilize_ts[2];
 	uint8_t bank;
 	uint8_t fifo_en;
 	uint8_t fifo_buffer[ICM_FIFO_BUFFER] __aligned(sizeof(long));
 };
 
-#define ICM_GET_DATA(_s) \
-	((struct icm_drv_data_t *)(_s)->drv_data)
-#define ICM_GET_SAVED_DATA(_s) \
-	(&ICM_GET_DATA(_s)->saved_data[(_s)->type])
+#define ICM_GET_DATA(_s) ((struct icm_drv_data_t *)(_s)->drv_data)
+#define ICM_GET_SAVED_DATA(_s) (&ICM_GET_DATA(_s)->saved_data[(_s)->type])
 
 /*
  * Virtual register address is 16 bits:
  * - 8 bits MSB coding bank number
  * - 8 bits LSB coding physical address
  */
-#define ICM426XX_REG_GET_BANK(_r)	(((_r) & 0xFF00) >> 8)
-#define ICM426XX_REG_GET_ADDR(_r)	((_r) & 0x00FF)
+#define ICM426XX_REG_GET_BANK(_r) (((_r)&0xFF00) >> 8)
+#define ICM426XX_REG_GET_ADDR(_r) ((_r)&0x00FF)
 
 /* Sensor resolution in number of bits */
-#define ICM_RESOLUTION		16
+#define ICM_RESOLUTION 16
 
 /**
  * sign_extend - sign extend a standard int value using the given sign-bit
@@ -96,6 +105,36 @@ int icm_get_scale(const struct motion_sensor_t *s, uint16_t *scale,
 		  int16_t *temp);
 
 ssize_t icm_fifo_decode_packet(const void *packet, const uint8_t **accel,
-		const uint8_t **gyro);
+			       const uint8_t **gyro);
+
+static inline void icm_set_stabilize_ts(const struct motion_sensor_t *s,
+					uint32_t delay)
+{
+	struct icm_drv_data_t *st = ICM_GET_DATA(s);
+	uint32_t stabilize_ts;
+
+	stabilize_ts = __hw_clock_source_read() + delay;
+	/* prevent 0 value used for disabling time checking */
+	st->stabilize_ts[s->type] = stabilize_ts | 1;
+}
+
+static inline void icm_reset_stabilize_ts(const struct motion_sensor_t *s)
+{
+	struct icm_drv_data_t *st = ICM_GET_DATA(s);
+
+	st->stabilize_ts[s->type] = 0;
+}
+
+static inline int32_t icm_get_sensor_stabilized(const struct motion_sensor_t *s,
+						uint32_t ts)
+{
+	struct icm_drv_data_t *st = ICM_GET_DATA(s);
+	uint32_t stabilize_ts = st->stabilize_ts[s->type];
+
+	if (stabilize_ts == 0)
+		return 0;
+
+	return time_until(ts, stabilize_ts);
+}
 
-#endif	/* __CROS_EC_ACCELGYRO_ICM_COMMON_H */
+#endif /* __CROS_EC_ACCELGYRO_ICM_COMMON_H */
diff --git a/driver/accelgyro_lsm6ds0.c b/driver/accelgyro_lsm6ds0.c
index 54ee1c77cc..265d89e18c 100644
--- a/driver/accelgyro_lsm6ds0.c
+++ b/driver/accelgyro_lsm6ds0.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,8 +19,8 @@
 #include "util.h"
 
 #define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
 
 /*
  * Struct for pairing an engineering value with the register value for a
@@ -32,25 +32,21 @@ struct accel_param_pair {
 };
 
 /* List of range values in +/-G's and their associated register values. */
-static const struct accel_param_pair g_ranges[] = {
-	{2, LSM6DS0_GSEL_2G},
-	{4, LSM6DS0_GSEL_4G},
-	{8, LSM6DS0_GSEL_8G}
-};
+static const struct accel_param_pair g_ranges[] = { { 2, LSM6DS0_GSEL_2G },
+						    { 4, LSM6DS0_GSEL_4G },
+						    { 8, LSM6DS0_GSEL_8G } };
 
 /*
  * List of angular rate range values in +/-dps's
  * and their associated register values.
  */
-const struct accel_param_pair dps_ranges[] = {
-	{245, LSM6DS0_DPS_SEL_245},
-	{500, LSM6DS0_DPS_SEL_500},
-	{1000, LSM6DS0_DPS_SEL_1000},
-	{2000, LSM6DS0_DPS_SEL_2000}
-};
+const struct accel_param_pair dps_ranges[] = { { 245, LSM6DS0_DPS_SEL_245 },
+					       { 500, LSM6DS0_DPS_SEL_500 },
+					       { 1000, LSM6DS0_DPS_SEL_1000 },
+					       { 2000, LSM6DS0_DPS_SEL_2000 } };
 
-static inline const struct accel_param_pair *get_range_table(
-		enum motionsensor_type type, int *psize)
+static inline const struct accel_param_pair *
+get_range_table(enum motionsensor_type type, int *psize)
 {
 	if (MOTIONSENSE_TYPE_ACCEL == type) {
 		if (psize)
@@ -65,28 +61,22 @@ static inline const struct accel_param_pair *get_range_table(
 
 /* List of ODR (gyro off) values in mHz and their associated register values.*/
 const struct accel_param_pair gyro_on_odr[] = {
-	{0,        LSM6DS0_ODR_PD},
-	{15000,    LSM6DS0_ODR_15HZ},
-	{59000,    LSM6DS0_ODR_59HZ},
-	{119000,   LSM6DS0_ODR_119HZ},
-	{238000,   LSM6DS0_ODR_238HZ},
-	{476000,   LSM6DS0_ODR_476HZ},
-	{952000,   LSM6DS0_ODR_952HZ}
+	{ 0, LSM6DS0_ODR_PD },	       { 15000, LSM6DS0_ODR_15HZ },
+	{ 59000, LSM6DS0_ODR_59HZ },   { 119000, LSM6DS0_ODR_119HZ },
+	{ 238000, LSM6DS0_ODR_238HZ }, { 476000, LSM6DS0_ODR_476HZ },
+	{ 952000, LSM6DS0_ODR_952HZ }
 };
 
 /* List of ODR (gyro on) values in mHz and their associated register values. */
 const struct accel_param_pair gyro_off_odr[] = {
-	{0,        LSM6DS0_ODR_PD},
-	{10000,    LSM6DS0_ODR_10HZ},
-	{50000,    LSM6DS0_ODR_50HZ},
-	{119000,   LSM6DS0_ODR_119HZ},
-	{238000,   LSM6DS0_ODR_238HZ},
-	{476000,   LSM6DS0_ODR_476HZ},
-	{952000,   LSM6DS0_ODR_952HZ}
+	{ 0, LSM6DS0_ODR_PD },	       { 10000, LSM6DS0_ODR_10HZ },
+	{ 50000, LSM6DS0_ODR_50HZ },   { 119000, LSM6DS0_ODR_119HZ },
+	{ 238000, LSM6DS0_ODR_238HZ }, { 476000, LSM6DS0_ODR_476HZ },
+	{ 952000, LSM6DS0_ODR_952HZ }
 };
 
-static inline const struct accel_param_pair *get_odr_table(
-		enum motionsensor_type type, int *psize)
+static inline const struct accel_param_pair *
+get_odr_table(enum motionsensor_type type, int *psize)
 {
 	if (MOTIONSENSE_TYPE_ACCEL == type) {
 		if (psize)
@@ -101,14 +91,14 @@ static inline const struct accel_param_pair *get_odr_table(
 
 static inline int get_ctrl_reg(enum motionsensor_type type)
 {
-	return (MOTIONSENSE_TYPE_ACCEL == type) ?
-		LSM6DS0_CTRL_REG6_XL : LSM6DS0_CTRL_REG1_G;
+	return (MOTIONSENSE_TYPE_ACCEL == type) ? LSM6DS0_CTRL_REG6_XL :
+						  LSM6DS0_CTRL_REG1_G;
 }
 
 static inline int get_xyz_reg(enum motionsensor_type type)
 {
-	return (MOTIONSENSE_TYPE_ACCEL == type) ?
-		LSM6DS0_OUT_X_L_XL : LSM6DS0_OUT_X_L_G;
+	return (MOTIONSENSE_TYPE_ACCEL == type) ? LSM6DS0_OUT_X_L_XL :
+						  LSM6DS0_OUT_X_L_G;
 }
 
 /**
@@ -118,14 +108,14 @@ static inline int get_xyz_reg(enum motionsensor_type type)
  * outside the range of values, it returns the closest valid reg value.
  */
 static int get_reg_val(const int eng_val, const int round_up,
-		const struct accel_param_pair *pairs, const int size)
+		       const struct accel_param_pair *pairs, const int size)
 {
 	int i;
 	for (i = 0; i < size - 1; i++) {
 		if (eng_val <= pairs[i].val)
 			break;
 
-		if (eng_val < pairs[i+1].val) {
+		if (eng_val < pairs[i + 1].val) {
 			if (round_up)
 				i += 1;
 			break;
@@ -138,7 +128,8 @@ static int get_reg_val(const int eng_val, const int round_up,
  * @return engineering value that matches the given reg val
  */
 static int get_engineering_val(const int reg_val,
-		const struct accel_param_pair *pairs, const int size)
+			       const struct accel_param_pair *pairs,
+			       const int size)
 {
 	int i;
 	for (i = 0; i < size; i++) {
@@ -166,14 +157,11 @@ static inline int raw_write8(const int port, const uint16_t i2c_addr_flags,
 	return i2c_write8(port, i2c_addr_flags, reg, data);
 }
 
-static int set_range(const struct motion_sensor_t *s,
-				int range,
-				int rnd)
+static int set_range(struct motion_sensor_t *s, int range, int rnd)
 {
 	int ret, ctrl_val, range_tbl_size;
 	uint8_t ctrl_reg, reg_val;
 	const struct accel_param_pair *ranges;
-	struct lsm6ds0_data *data = s->drv_data;
 
 	ctrl_reg = get_ctrl_reg(s->type);
 	ranges = get_range_table(s->type, &range_tbl_size);
@@ -186,40 +174,29 @@ static int set_range(const struct motion_sensor_t *s,
 	 */
 	mutex_lock(s->mutex);
 
-	ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-			ctrl_reg, &ctrl_val);
+	ret = raw_read8(s->port, s->i2c_spi_addr_flags, ctrl_reg, &ctrl_val);
 	if (ret != EC_SUCCESS)
 		goto accel_cleanup;
 
 	ctrl_val = (ctrl_val & ~LSM6DS0_RANGE_MASK) | reg_val;
-	ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-			 ctrl_reg, ctrl_val);
+	ret = raw_write8(s->port, s->i2c_spi_addr_flags, ctrl_reg, ctrl_val);
 
 	/* Now that we have set the range, update the driver's value. */
 	if (ret == EC_SUCCESS)
-		data->base.range = get_engineering_val(reg_val, ranges,
-				range_tbl_size);
+		s->current_range =
+			get_engineering_val(reg_val, ranges, range_tbl_size);
 
 accel_cleanup:
 	mutex_unlock(s->mutex);
 	return ret;
 }
 
-static int get_range(const struct motion_sensor_t *s)
-{
-	struct lsm6ds0_data *data = s->drv_data;
-
-	return data->base.range;
-}
-
 static int get_resolution(const struct motion_sensor_t *s)
 {
 	return LSM6DS0_RESOLUTION;
 }
 
-static int set_data_rate(const struct motion_sensor_t *s,
-				int rate,
-				int rnd)
+static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
 {
 	int ret, val, odr_tbl_size;
 	uint8_t ctrl_reg, reg_val;
@@ -245,8 +222,8 @@ static int set_data_rate(const struct motion_sensor_t *s,
 
 	/* Now that we have set the odr, update the driver's value. */
 	if (ret == EC_SUCCESS)
-		data->base.odr = get_engineering_val(reg_val, data_rates,
-						       odr_tbl_size);
+		data->base.odr =
+			get_engineering_val(reg_val, data_rates, odr_tbl_size);
 
 	/* CTRL_REG3_G 12h
 	 * [7] low-power mode = 0;
@@ -262,8 +239,8 @@ static int set_data_rate(const struct motion_sensor_t *s,
 			goto accel_cleanup;
 		val &= ~(0x3 << 4); /* clear bit [5:4] */
 		val = (rate > 119000) ?
-			(val | (1<<7))   /* set high-power mode */ :
-			(val & ~(1<<7)); /* set low-power mode */
+			      (val | (1 << 7)) /* set high-power mode */ :
+			      (val & ~(1 << 7)); /* set low-power mode */
 		ret = raw_write8(s->port, s->i2c_spi_addr_flags,
 				 LSM6DS0_CTRL_REG3_G, val);
 	}
@@ -280,9 +257,8 @@ static int get_data_rate(const struct motion_sensor_t *s)
 	return data->base.odr;
 }
 
-static int set_offset(const struct motion_sensor_t *s,
-			const int16_t *offset,
-			int16_t    temp)
+static int set_offset(const struct motion_sensor_t *s, const int16_t *offset,
+		      int16_t temp)
 {
 	/* temperature is ignored */
 	struct lsm6ds0_data *data = s->drv_data;
@@ -292,9 +268,8 @@ static int set_offset(const struct motion_sensor_t *s,
 	return EC_SUCCESS;
 }
 
-static int get_offset(const struct motion_sensor_t *s,
-			int16_t    *offset,
-			int16_t    *temp)
+static int get_offset(const struct motion_sensor_t *s, int16_t *offset,
+		      int16_t *temp)
 {
 	struct lsm6ds0_data *data = s->drv_data;
 	offset[X] = data->offset[X];
@@ -308,8 +283,8 @@ static int is_data_ready(const struct motion_sensor_t *s, int *ready)
 {
 	int ret, tmp;
 
-	ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-			LSM6DS0_STATUS_REG, &tmp);
+	ret = raw_read8(s->port, s->i2c_spi_addr_flags, LSM6DS0_STATUS_REG,
+			&tmp);
 
 	if (ret != EC_SUCCESS) {
 		CPRINTS("%s type:0x%X RS Error", s->name, s->type);
@@ -328,7 +303,7 @@ static int read(const struct motion_sensor_t *s, intv3_t v)
 {
 	uint8_t raw[6];
 	uint8_t xyz_reg;
-	int ret, range, i, tmp = 0;
+	int ret, i, tmp = 0;
 	struct lsm6ds0_data *data = s->drv_data;
 
 	ret = is_data_ready(s, &tmp);
@@ -349,12 +324,10 @@ static int read(const struct motion_sensor_t *s, intv3_t v)
 	xyz_reg = get_xyz_reg(s->type);
 
 	/* Read 6 bytes starting at xyz_reg */
-	ret = i2c_read_block(s->port, s->i2c_spi_addr_flags,
-			     xyz_reg, raw, 6);
+	ret = i2c_read_block(s->port, s->i2c_spi_addr_flags, xyz_reg, raw, 6);
 
 	if (ret != EC_SUCCESS) {
-		CPRINTS("%s type:0x%X RD XYZ Error",
-			s->name, s->type);
+		CPRINTS("%s type:0x%X RD XYZ Error", s->name, s->type);
 		return ret;
 	}
 
@@ -364,19 +337,18 @@ static int read(const struct motion_sensor_t *s, intv3_t v)
 	rotate(v, *s->rot_standard_ref, v);
 
 	/* apply offset in the device coordinates */
-	range = get_range(s);
 	for (i = X; i <= Z; i++)
-		v[i] += (data->offset[i] << 5) / range;
+		v[i] += (data->offset[i] << 5) / s->current_range;
 
 	return EC_SUCCESS;
 }
 
-static int init(const struct motion_sensor_t *s)
+static int init(struct motion_sensor_t *s)
 {
 	int ret = 0, tmp;
 
-	ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-			LSM6DS0_WHO_AM_I_REG, &tmp);
+	ret = raw_read8(s->port, s->i2c_spi_addr_flags, LSM6DS0_WHO_AM_I_REG,
+			&tmp);
 	if (ret)
 		return EC_ERROR_UNKNOWN;
 
@@ -396,7 +368,6 @@ static int init(const struct motion_sensor_t *s)
 	 * SW_RESET is down for accel only!
 	 */
 	if (MOTIONSENSE_TYPE_ACCEL == s->type) {
-
 		mutex_lock(s->mutex);
 		ret = raw_read8(s->port, s->i2c_spi_addr_flags,
 				LSM6DS0_CTRL_REG8, &tmp);
@@ -425,11 +396,9 @@ const struct accelgyro_drv lsm6ds0_drv = {
 	.init = init,
 	.read = read,
 	.set_range = set_range,
-	.get_range = get_range,
 	.get_resolution = get_resolution,
 	.set_data_rate = set_data_rate,
 	.get_data_rate = get_data_rate,
 	.set_offset = set_offset,
 	.get_offset = get_offset,
-	.perform_calib = NULL,
 };
diff --git a/driver/accelgyro_lsm6ds0.h b/driver/accelgyro_lsm6ds0.h
index c6b0789c08..149a32ea7a 100644
--- a/driver/accelgyro_lsm6ds0.h
+++ b/driver/accelgyro_lsm6ds0.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,95 +15,95 @@
  * 7-bit address is 110101Xb. Where 'X' is determined
  * by the voltage on the ADDR pin.
  */
-#define LSM6DS0_ADDR0_FLAGS       0x6a
-#define LSM6DS0_ADDR1_FLAGS       0x6b
+#define LSM6DS0_ADDR0_FLAGS 0x6a
+#define LSM6DS0_ADDR1_FLAGS 0x6b
 
 /* who am I  */
-#define LSM6DS0_WHO_AM_I          0x68
+#define LSM6DS0_WHO_AM_I 0x68
 
 /* Chip specific registers. */
-#define LSM6DS0_ACT_THS           0x04
-#define LSM6DS0_ACT_DUR           0x05
-#define LSM6DS0_INT_GEN_CFG_XL    0x06
-#define LSM6DS0_INT_GEN_THS_X_XL  0x07
-#define LSM6DS0_INT_GEN_THS_Y_XL  0x08
-#define LSM6DS0_INT_GEN_THS_Z_XL  0x09
-#define LSM6DS0_INT_GEN_DUR_XL    0x0a
-#define LSM6DS0_REFERENCE_G       0x0b
-#define LSM6DS0_INT_CTRL          0x0c
-#define LSM6DS0_WHO_AM_I_REG      0x0f
-#define LSM6DS0_CTRL_REG1_G       0x10
-#define LSM6DS0_CTRL_REG2_G       0x11
-#define LSM6DS0_CTRL_REG3_G       0x12
-#define LSM6DS0_ORIENT_CFG_G      0x13
-#define LSM6DS0_INT_GEN_SRC_G     0x14
-#define LSM6DS0_OUT_TEMP_L        0x15
-#define LSM6DS0_OUT_TEMP_H        0x16
-#define LSM6DS0_OUT_X_L_G         0x18
-#define LSM6DS0_OUT_X_H_G         0x19
-#define LSM6DS0_OUT_Y_L_G         0x1a
-#define LSM6DS0_OUT_Y_H_G         0x1b
-#define LSM6DS0_OUT_Z_L_G         0x1c
-#define LSM6DS0_OUT_Z_H_G         0x1d
-#define LSM6DS0_CTRL_REG4         0x1e
-#define LSM6DS0_CTRL_REG5_XL      0x1f
-#define LSM6DS0_CTRL_REG6_XL      0x20
-#define LSM6DS0_CTRL_REG7_XL      0x21
-#define LSM6DS0_CTRL_REG8         0x22
-#define LSM6DS0_CTRL_REG9         0x23
-#define LSM6DS0_CTRL_REG10        0x24
-#define LSM6DS0_INT_GEN_SRC_XL    0x26
-#define LSM6DS0_STATUS_REG        0x27
-#define LSM6DS0_OUT_X_L_XL        0x28
-#define LSM6DS0_OUT_X_H_XL        0x29
-#define LSM6DS0_OUT_Y_L_XL        0x2a
-#define LSM6DS0_OUT_Y_H_XL        0x2b
-#define LSM6DS0_OUT_Z_L_XL        0x2c
-#define LSM6DS0_OUT_Z_H_XL        0x2d
-#define LSM6DS0_FIFO_CTRL         0x2e
-#define LSM6DS0_FIFO_SRC          0x2f
-#define LSM6DS0_INT_GEN_CFG_G     0x30
-#define LSM6DS0_INT_GEN_THS_XH_G  0x31
-#define LSM6DS0_INT_GEN_THS_XL_G  0x32
-#define LSM6DS0_INT_GEN_THS_YH_G  0x33
-#define LSM6DS0_INT_GEN_THS_YL_G  0x34
-#define LSM6DS0_INT_GEN_THS_ZH_G  0x35
-#define LSM6DS0_INT_GEN_THS_ZL_G  0x36
-#define LSM6DS0_INT_GEN_DUR_G     0x37
-
-#define LSM6DS0_DPS_SEL_245     (0 << 3)
-#define LSM6DS0_DPS_SEL_500     BIT(3)
-#define LSM6DS0_DPS_SEL_1000    (2 << 3)
-#define LSM6DS0_DPS_SEL_2000    (3 << 3)
-#define LSM6DS0_GSEL_2G         (0 << 3)
-#define LSM6DS0_GSEL_4G         (2 << 3)
-#define LSM6DS0_GSEL_8G         (3 << 3)
-
-#define LSM6DS0_RANGE_MASK      (3 << 3)
-
-#define LSM6DS0_ODR_PD          (0 << 5)
-#define LSM6DS0_ODR_10HZ        BIT(5)
-#define LSM6DS0_ODR_15HZ        BIT(5)
-#define LSM6DS0_ODR_50HZ        (2 << 5)
-#define LSM6DS0_ODR_59HZ        (2 << 5)
-#define LSM6DS0_ODR_119HZ       (3 << 5)
-#define LSM6DS0_ODR_238HZ       (4 << 5)
-#define LSM6DS0_ODR_476HZ       (5 << 5)
-#define LSM6DS0_ODR_952HZ       (6 << 5)
-
-#define LSM6DS0_ODR_MASK        (7 << 5)
+#define LSM6DS0_ACT_THS 0x04
+#define LSM6DS0_ACT_DUR 0x05
+#define LSM6DS0_INT_GEN_CFG_XL 0x06
+#define LSM6DS0_INT_GEN_THS_X_XL 0x07
+#define LSM6DS0_INT_GEN_THS_Y_XL 0x08
+#define LSM6DS0_INT_GEN_THS_Z_XL 0x09
+#define LSM6DS0_INT_GEN_DUR_XL 0x0a
+#define LSM6DS0_REFERENCE_G 0x0b
+#define LSM6DS0_INT_CTRL 0x0c
+#define LSM6DS0_WHO_AM_I_REG 0x0f
+#define LSM6DS0_CTRL_REG1_G 0x10
+#define LSM6DS0_CTRL_REG2_G 0x11
+#define LSM6DS0_CTRL_REG3_G 0x12
+#define LSM6DS0_ORIENT_CFG_G 0x13
+#define LSM6DS0_INT_GEN_SRC_G 0x14
+#define LSM6DS0_OUT_TEMP_L 0x15
+#define LSM6DS0_OUT_TEMP_H 0x16
+#define LSM6DS0_OUT_X_L_G 0x18
+#define LSM6DS0_OUT_X_H_G 0x19
+#define LSM6DS0_OUT_Y_L_G 0x1a
+#define LSM6DS0_OUT_Y_H_G 0x1b
+#define LSM6DS0_OUT_Z_L_G 0x1c
+#define LSM6DS0_OUT_Z_H_G 0x1d
+#define LSM6DS0_CTRL_REG4 0x1e
+#define LSM6DS0_CTRL_REG5_XL 0x1f
+#define LSM6DS0_CTRL_REG6_XL 0x20
+#define LSM6DS0_CTRL_REG7_XL 0x21
+#define LSM6DS0_CTRL_REG8 0x22
+#define LSM6DS0_CTRL_REG9 0x23
+#define LSM6DS0_CTRL_REG10 0x24
+#define LSM6DS0_INT_GEN_SRC_XL 0x26
+#define LSM6DS0_STATUS_REG 0x27
+#define LSM6DS0_OUT_X_L_XL 0x28
+#define LSM6DS0_OUT_X_H_XL 0x29
+#define LSM6DS0_OUT_Y_L_XL 0x2a
+#define LSM6DS0_OUT_Y_H_XL 0x2b
+#define LSM6DS0_OUT_Z_L_XL 0x2c
+#define LSM6DS0_OUT_Z_H_XL 0x2d
+#define LSM6DS0_FIFO_CTRL 0x2e
+#define LSM6DS0_FIFO_SRC 0x2f
+#define LSM6DS0_INT_GEN_CFG_G 0x30
+#define LSM6DS0_INT_GEN_THS_XH_G 0x31
+#define LSM6DS0_INT_GEN_THS_XL_G 0x32
+#define LSM6DS0_INT_GEN_THS_YH_G 0x33
+#define LSM6DS0_INT_GEN_THS_YL_G 0x34
+#define LSM6DS0_INT_GEN_THS_ZH_G 0x35
+#define LSM6DS0_INT_GEN_THS_ZL_G 0x36
+#define LSM6DS0_INT_GEN_DUR_G 0x37
+
+#define LSM6DS0_DPS_SEL_245 (0 << 3)
+#define LSM6DS0_DPS_SEL_500 BIT(3)
+#define LSM6DS0_DPS_SEL_1000 (2 << 3)
+#define LSM6DS0_DPS_SEL_2000 (3 << 3)
+#define LSM6DS0_GSEL_2G (0 << 3)
+#define LSM6DS0_GSEL_4G (2 << 3)
+#define LSM6DS0_GSEL_8G (3 << 3)
+
+#define LSM6DS0_RANGE_MASK (3 << 3)
+
+#define LSM6DS0_ODR_PD (0 << 5)
+#define LSM6DS0_ODR_10HZ BIT(5)
+#define LSM6DS0_ODR_15HZ BIT(5)
+#define LSM6DS0_ODR_50HZ (2 << 5)
+#define LSM6DS0_ODR_59HZ (2 << 5)
+#define LSM6DS0_ODR_119HZ (3 << 5)
+#define LSM6DS0_ODR_238HZ (4 << 5)
+#define LSM6DS0_ODR_476HZ (5 << 5)
+#define LSM6DS0_ODR_952HZ (6 << 5)
+
+#define LSM6DS0_ODR_MASK (7 << 5)
 
 /*
  * Register      : STATUS_REG
  * Address       : 0X27
  */
 enum lsm6ds0_status {
-	LSM6DS0_STS_DOWN                = 0x00,
-	LSM6DS0_STS_XLDA_UP             = 0x01,
-	LSM6DS0_STS_GDA_UP              = 0x02,
+	LSM6DS0_STS_DOWN = 0x00,
+	LSM6DS0_STS_XLDA_UP = 0x01,
+	LSM6DS0_STS_GDA_UP = 0x02,
 };
-#define         LSM6DS0_STS_XLDA_MASK       0x01
-#define         LSM6DS0_STS_GDA_MASK        0x02
+#define LSM6DS0_STS_XLDA_MASK 0x01
+#define LSM6DS0_STS_GDA_MASK 0x02
 
 /*
  * Register      : CTRL_REG8
@@ -111,18 +111,18 @@ enum lsm6ds0_status {
  * Bit Group Name: BDU
  */
 enum lsm6ds0_bdu {
-	LSM6DS0_BDU_DISABLE              = 0x00,
-	LSM6DS0_BDU_ENABLE               = 0x40,
+	LSM6DS0_BDU_DISABLE = 0x00,
+	LSM6DS0_BDU_ENABLE = 0x40,
 };
 /* Sensor resolution in number of bits. This sensor has fixed resolution. */
-#define LSM6DS0_RESOLUTION      16
+#define LSM6DS0_RESOLUTION 16
 
 /* Min and Max sampling frequency in mHz */
-#define LSM6DS0_ACCEL_MIN_FREQ  14900
-#define LSM6DS0_ACCEL_MAX_FREQ  MOTION_MAX_SENSOR_FREQUENCY(952000, 119000)
+#define LSM6DS0_ACCEL_MIN_FREQ 14900
+#define LSM6DS0_ACCEL_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(952000, 119000)
 
-#define LSM6DS0_GYRO_MIN_FREQ   14900
-#define LSM6DS0_GYRO_MAX_FREQ  MOTION_MAX_SENSOR_FREQUENCY(952000, 119000)
+#define LSM6DS0_GYRO_MIN_FREQ 14900
+#define LSM6DS0_GYRO_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(952000, 119000)
 
 extern const struct accelgyro_drv lsm6ds0_drv;
 struct lsm6ds0_data {
diff --git a/driver/accelgyro_lsm6dsm.c b/driver/accelgyro_lsm6dsm.c
index 64a1d22517..52966ddd2d 100644
--- a/driver/accelgyro_lsm6dsm.c
+++ b/driver/accelgyro_lsm6dsm.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,6 +9,7 @@
  * This driver supports both devices LSM6DSM and LSM6DSL
  */
 
+#include "builtin/assert.h"
 #include "driver/accelgyro_lsm6dsm.h"
 #include "driver/mag_lis2mdl.h"
 #include "hooks.h"
@@ -20,59 +21,16 @@
 #include "task.h"
 #include "timer.h"
 
-#define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
-
-#define IS_FSTS_EMPTY(s) ((s).len & LSM6DSM_FIFO_EMPTY)
-
-#ifndef FIFO_READ_LEN
-#define FIFO_READ_LEN 0
-#endif
-
-#ifndef CONFIG_ACCEL_LSM6DSM_INT_EVENT
-#define CONFIG_ACCEL_LSM6DSM_INT_EVENT 0
+#ifdef CONFIG_ACCEL_LSM6DSM_INT_EVENT
+#define ACCEL_LSM6DSM_INT_ENABLE
 #endif
 
-static volatile uint32_t last_interrupt_timestamp;
-
-/**
- * Resets the lsm6dsm load fifo sensor states to the given timestamp. This
- * should be called at the start of the fifo read sequence.
- *
- * @param s Pointer to the first sensor in the lsm6dsm (accelerometer).
- * @param ts The timestamp to use for the interrupt timestamp.
- */
-__maybe_unused static void reset_load_fifo_sensor_state(
-	struct motion_sensor_t *s, uint32_t ts)
-{
-	int i;
-	struct lsm6dsm_accel_fifo_state *fifo_state =
-		LSM6DSM_GET_DATA(s)->accel_fifo_state;
+#define CPUTS(outstr) cputs(CC_ACCEL, outstr)
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args)
 
-	for (i = 0; i < FIFO_DEV_NUM; i++) {
-		fifo_state->load_fifo_sensor_state[i].int_timestamp = ts;
-		fifo_state->load_fifo_sensor_state[i].sample_count = 0;
-	}
-}
-
-/**
- * Gets the dev_fifo enum value for a given sensor.
- *
- * @param s Pointer to the sensor in question.
- * @return the dev_fifo enum value corresponding to the sensor.
- */
-static inline enum dev_fifo get_fifo_type(const struct motion_sensor_t *s)
-{
-	static enum dev_fifo map[] = {
-		FIFO_DEV_ACCEL,
-		FIFO_DEV_GYRO,
-#ifdef CONFIG_LSM6DSM_SEC_I2C
-		FIFO_DEV_MAG
-#endif /* CONFIG_LSM6DSM_SEC_I2C */
-	};
-	return map[s->type];
-}
+STATIC_IF(ACCEL_LSM6DSM_INT_ENABLE)
+volatile uint32_t last_interrupt_timestamp;
 
 /**
  * Gets the sensor type associated with the dev_fifo enum. This type can be used
@@ -98,7 +56,7 @@ static inline uint8_t get_sensor_type(enum dev_fifo fifo_type)
 static inline int get_xyz_reg(enum motionsensor_type type)
 {
 	return LSM6DSM_ACCEL_OUT_X_L_ADDR -
-		(LSM6DSM_ACCEL_OUT_X_L_ADDR - LSM6DSM_GYRO_OUT_X_L_ADDR) * type;
+	       (LSM6DSM_ACCEL_OUT_X_L_ADDR - LSM6DSM_GYRO_OUT_X_L_ADDR) * type;
 }
 
 /**
@@ -110,30 +68,22 @@ static inline int get_xyz_reg(enum motionsensor_type type)
  */
 __maybe_unused static int config_interrupt(const struct motion_sensor_t *accel)
 {
-	int ret = EC_SUCCESS;
 	int int1_ctrl_val;
 
-	ret = st_raw_read8(accel->port, accel->i2c_spi_addr_flags,
-			   LSM6DSM_INT1_CTRL, &int1_ctrl_val);
-	if (ret != EC_SUCCESS)
-		return ret;
+	RETURN_ERROR(st_raw_read8(accel->port, accel->i2c_spi_addr_flags,
+				  LSM6DSM_INT1_CTRL, &int1_ctrl_val));
 
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
-		/* As soon as one sample is ready, trigger an interrupt. */
-		ret = st_raw_write8(accel->port, accel->i2c_spi_addr_flags,
-				    LSM6DSM_FIFO_CTRL1_ADDR,
-				    OUT_XYZ_SIZE / sizeof(uint16_t));
-		if (ret != EC_SUCCESS)
-			return ret;
-		int1_ctrl_val |= LSM6DSM_INT_FIFO_TH | LSM6DSM_INT_FIFO_OVR |
-			LSM6DSM_INT_FIFO_FULL;
-	}
+	/* As soon as one sample is ready, trigger an interrupt. */
+	RETURN_ERROR(st_raw_write8(accel->port, accel->i2c_spi_addr_flags,
+				   LSM6DSM_FIFO_CTRL1_ADDR,
+				   OUT_XYZ_SIZE / sizeof(uint16_t)));
+	int1_ctrl_val |= LSM6DSM_INT_FIFO_TH | LSM6DSM_INT_FIFO_OVR |
+			 LSM6DSM_INT_FIFO_FULL;
 
 	return st_raw_write8(accel->port, accel->i2c_spi_addr_flags,
 			     LSM6DSM_INT1_CTRL, int1_ctrl_val);
 }
 
-
 /**
  * fifo_disable - set fifo mode
  * @accel: Motion sensor pointer: must be MOTIONSENSE_TYPE_ACCEL.
@@ -182,7 +132,6 @@ static int fifo_enable(const struct motion_sensor_t *accel)
 		MOTIONSENSE_TYPE_MAG,
 	};
 
-
 	/* Search for min and max odr values for acc, gyro. */
 	for (i = FIFO_DEV_GYRO; i < FIFO_DEV_NUM; i++) {
 		/* Check if sensor enabled with ODR. */
@@ -201,8 +150,7 @@ static int fifo_enable(const struct motion_sensor_t *accel)
 	}
 
 	/* FIFO ODR must be set before the decimation factors */
-	odr_reg_val = LSM6DSM_ODR_TO_REG(max_odr) <<
-					LSM6DSM_FIFO_CTRL5_ODR_OFF;
+	odr_reg_val = LSM6DSM_ODR_TO_REG(max_odr) << LSM6DSM_FIFO_CTRL5_ODR_OFF;
 	err = st_raw_write8(accel->port, accel->i2c_spi_addr_flags,
 			    LSM6DSM_FIFO_CTRL5_ADDR, odr_reg_val);
 
@@ -224,18 +172,21 @@ static int fifo_enable(const struct motion_sensor_t *accel)
 	st_raw_write8(accel->port, accel->i2c_spi_addr_flags,
 		      LSM6DSM_FIFO_CTRL3_ADDR,
 		      (decimators[FIFO_DEV_GYRO] << LSM6DSM_FIFO_DEC_G_OFF) |
-		      (decimators[FIFO_DEV_ACCEL] << LSM6DSM_FIFO_DEC_XL_OFF));
+			      (decimators[FIFO_DEV_ACCEL]
+			       << LSM6DSM_FIFO_DEC_XL_OFF));
+	/* b/255967867: Cannot use IS_ENABLED here with clang. */
 #ifdef CONFIG_LSM6DSM_SEC_I2C
+	ASSERT(ARRAY_SIZE(decimators) > FIFO_DEV_MAG);
 	st_raw_write8(accel->port, accel->i2c_spi_addr_flags,
-		      LSM6DSM_FIFO_CTRL4_ADDR,
-		      decimators[FIFO_DEV_MAG]);
+		      LSM6DSM_FIFO_CTRL4_ADDR, decimators[FIFO_DEV_MAG]);
 
 	/*
 	 * FIFO ODR is limited by odr of gyro or accel.
 	 * If we are sampling magnetometer faster than gyro or accel,
-	 * bump up ODR of accel. Thanks to decimation we will still measure at
-	 * the specified ODR.
-	 * Contrary to gyroscope, sampling faster will not affect measurements.
+	 * bump up ODR of accel. Thanks to decimation we will still
+	 * measure at the specified ODR.
+	 * Contrary to gyroscope, sampling faster will not affect
+	 * measurements.
 	 * Set the ODR behind the back of set/get_data_rate.
 	 *
 	 * First samples after ODR changes must be thrown out [See
@@ -244,21 +195,22 @@ static int fifo_enable(const struct motion_sensor_t *accel)
 	 * - except the first one after ODR change.
 	 * When decreasing accel ODR, we don't need to drop sample if
 	 * frequency is less than 52Hz.
-	 * At most, we need to drop one sample, but Android requirement specify
-	 * that chaning one sensor ODR should not affect other sensors.
+	 * At most, we need to drop one sample, but Android requirement
+	 * specify that changing one sensor ODR should not affect other
+	 * sensors.
 	 * Leave the bad sample alone, it will be a single glitch in the
 	 * accelerometer data stream.
 	 */
 	if (max_odr > MAX(odrs[FIFO_DEV_ACCEL], odrs[FIFO_DEV_GYRO])) {
 		st_write_data_with_mask(accel, LSM6DSM_ODR_REG(accel->type),
-				LSM6DSM_ODR_MASK,
-				LSM6DSM_ODR_TO_REG(max_odr));
+					LSM6DSM_ODR_MASK,
+					LSM6DSM_ODR_TO_REG(max_odr));
 	} else {
-		st_write_data_with_mask(accel, LSM6DSM_ODR_REG(accel->type),
-				LSM6DSM_ODR_MASK,
-				LSM6DSM_ODR_TO_REG(odrs[FIFO_DEV_ACCEL]));
+		st_write_data_with_mask(
+			accel, LSM6DSM_ODR_REG(accel->type), LSM6DSM_ODR_MASK,
+			LSM6DSM_ODR_TO_REG(odrs[FIFO_DEV_ACCEL]));
 	}
-#endif /* CONFIG_MAG_LSM6DSM_LIS2MDL */
+#endif
 	/*
 	 * After ODR and decimation values are set, continuous mode can be
 	 * enabled
@@ -272,6 +224,7 @@ static int fifo_enable(const struct motion_sensor_t *accel)
 	return EC_SUCCESS;
 }
 
+#ifdef ACCEL_LSM6DSM_INT_ENABLE
 /*
  * Must order FIFO read based on ODR:
  * For example Acc @ 52 Hz, Gyro @ 26 Hz Mag @ 13 Hz in FIFO we have
@@ -319,14 +272,12 @@ static int fifo_next(struct lsm6dsm_data *private)
  * push_fifo_data - Scan data pattern and push upside
  */
 static void push_fifo_data(struct motion_sensor_t *accel, uint8_t *fifo,
-			   uint16_t flen,
-			   uint32_t timestamp)
+			   uint16_t flen, uint32_t timestamp)
 {
 	struct motion_sensor_t *s;
 	struct lsm6dsm_data *private = LSM6DSM_GET_DATA(accel);
 
 	while (flen > 0) {
-		struct ec_response_motion_sensor_data vect;
 		int id;
 		int *axis;
 		int next_fifo = fifo_next(private);
@@ -347,24 +298,31 @@ static void push_fifo_data(struct motion_sensor_t *accel, uint8_t *fifo,
 			axis = s->raw_xyz;
 
 			/* Apply precision, sensitivity and rotation. */
-#ifdef CONFIG_MAG_LSM6DSM_LIS2MDL
-			if (s->type == MOTIONSENSE_TYPE_MAG) {
+			if (IS_ENABLED(CONFIG_MAG_LSM6DSM_LIS2MDL) &&
+			    (s->type == MOTIONSENSE_TYPE_MAG)) {
 				lis2mdl_normalize(s, axis, fifo);
 				rotate(axis, *s->rot_standard_ref, axis);
-			} else
-#endif
-			{
+			} else {
 				st_normalize(s, axis, fifo);
 			}
 
-
-			vect.data[X] = axis[X];
-			vect.data[Y] = axis[Y];
-			vect.data[Z] = axis[Z];
-
-			vect.flags = 0;
-			vect.sensor_num = s - motion_sensors;
-			motion_sense_fifo_stage_data(&vect, s, 3, timestamp);
+			if (IS_ENABLED(CONFIG_ACCEL_SPOOF_MODE) &&
+			    s->flags & MOTIONSENSE_FLAG_IN_SPOOF_MODE)
+				axis = s->spoof_xyz;
+			if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
+				struct ec_response_motion_sensor_data vect;
+
+				vect.data[X] = axis[X];
+				vect.data[Y] = axis[Y];
+				vect.data[Z] = axis[Z];
+
+				vect.flags = 0;
+				vect.sensor_num = s - motion_sensors;
+				motion_sense_fifo_stage_data(&vect, s, 3,
+							     timestamp);
+			} else {
+				motion_sense_push_raw_xyz(s);
+			}
 		}
 
 		fifo += OUT_XYZ_SIZE;
@@ -372,16 +330,12 @@ static void push_fifo_data(struct motion_sensor_t *accel, uint8_t *fifo,
 	}
 }
 
-static int load_fifo(struct motion_sensor_t *s, const struct fstatus *fsts,
-		     uint32_t *last_fifo_read_ts)
+static int load_fifo(struct motion_sensor_t *s, const struct fstatus *fsts)
 {
 	uint32_t interrupt_timestamp = last_interrupt_timestamp;
 	int err, left, length;
 	uint8_t fifo[FIFO_READ_LEN];
 
-	/* Reset the load_fifo_sensor_state so we can start a new read. */
-	reset_load_fifo_sensor_state(s, interrupt_timestamp);
-
 	/*
 	 * DIFF[11:0] are number of unread uint16 in FIFO
 	 * mask DIFF and compute total byte len to read from FIFO.
@@ -390,12 +344,6 @@ static int load_fifo(struct motion_sensor_t *s, const struct fstatus *fsts,
 	left *= sizeof(uint16_t);
 	left = (left / OUT_XYZ_SIZE) * OUT_XYZ_SIZE;
 
-	/*
-	 * TODO(b/122912601): phaser360: Investigate Standard Deviation error
-	 *				 during CtsSensorTests
-	 * - check "pattern" register versus where code thinks it is parsing
-	 */
-
 	/* Push all data on upper side. */
 	do {
 		/* Fit len to pre-allocated static buffer. */
@@ -406,9 +354,7 @@ static int load_fifo(struct motion_sensor_t *s, const struct fstatus *fsts,
 
 		/* Read data and copy in buffer. */
 		err = st_raw_read_n_noinc(s->port, s->i2c_spi_addr_flags,
-					  LSM6DSM_FIFO_DATA_ADDR,
-					  fifo, length);
-		*last_fifo_read_ts = __hw_clock_source_read();
+					  LSM6DSM_FIFO_DATA_ADDR, fifo, length);
 		if (err != EC_SUCCESS)
 			return err;
 
@@ -419,93 +365,55 @@ static int load_fifo(struct motion_sensor_t *s, const struct fstatus *fsts,
 		 * where we empty the FIFO, and a new IRQ comes in between
 		 * reading the last sample and pushing it into the FIFO.
 		 */
-
 		push_fifo_data(s, fifo, length, interrupt_timestamp);
 		left -= length;
 	} while (left > 0);
 
-	motion_sense_fifo_commit_data();
-
 	return EC_SUCCESS;
 }
 
-static int is_fifo_empty(struct motion_sensor_t *s, struct fstatus *fsts)
-{
-	int res;
-
-	if (s->flags & MOTIONSENSE_FLAG_INT_SIGNAL)
-		return gpio_get_level(s->int_signal);
-	CPRINTS("Interrupt signal not set for %s", s->name);
-	res = st_raw_read_n_noinc(s->port, s->i2c_spi_addr_flags,
-				  LSM6DSM_FIFO_STS1_ADDR,
-				  (int8_t *)fsts, sizeof(*fsts));
-	/* If we failed to read the FIFO size assume empty. */
-	if (res != EC_SUCCESS)
-		return 1;
-	return IS_FSTS_EMPTY(*fsts);
-}
-
-static void handle_interrupt_for_fifo(uint32_t ts)
-{
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO) &&
-	    time_after(ts, last_interrupt_timestamp))
-		last_interrupt_timestamp = ts;
-	task_set_event(TASK_ID_MOTIONSENSE,
-		       CONFIG_ACCEL_LSM6DSM_INT_EVENT, 0);
-}
-
 /**
  * lsm6dsm_interrupt - interrupt from int1/2 pin of sensor
  */
 void lsm6dsm_interrupt(enum gpio_signal signal)
 {
-	handle_interrupt_for_fifo(__hw_clock_source_read());
+	last_interrupt_timestamp = __hw_clock_source_read();
+
+	task_set_event(TASK_ID_MOTIONSENSE, CONFIG_ACCEL_LSM6DSM_INT_EVENT);
 }
 
 /**
  * irq_handler - bottom half of the interrupt stack
  */
-__maybe_unused static int irq_handler(
-	struct motion_sensor_t *s, uint32_t *event)
+static int irq_handler(struct motion_sensor_t *s, uint32_t *event)
 {
-	int ret = EC_SUCCESS;
+	struct fstatus fsts;
+	int fifo_empty = false;
+	bool commit_needed = false;
 
 	if ((s->type != MOTIONSENSE_TYPE_ACCEL) ||
 	    (!(*event & CONFIG_ACCEL_LSM6DSM_INT_EVENT)))
 		return EC_ERROR_NOT_HANDLED;
 
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
-		struct fstatus fsts;
-		uint32_t last_fifo_read_ts;
-		uint32_t triggering_interrupt_timestamp =
-			last_interrupt_timestamp;
-
-		/* Read how many data pattern on FIFO to read and pattern. */
-		ret = st_raw_read_n_noinc(s->port, s->i2c_spi_addr_flags,
-					  LSM6DSM_FIFO_STS1_ADDR,
-					  (uint8_t *)&fsts, sizeof(fsts));
-		if (ret != EC_SUCCESS)
-			return ret;
-		last_fifo_read_ts = __hw_clock_source_read();
+	while (!fifo_empty) {
+		/* Read how many data pattern on FIFO to read. */
+		RETURN_ERROR(st_raw_read_n_noinc(
+			s->port, s->i2c_spi_addr_flags, LSM6DSM_FIFO_STS1_ADDR,
+			(uint8_t *)&fsts, sizeof(fsts)));
 		if (fsts.len & (LSM6DSM_FIFO_DATA_OVR | LSM6DSM_FIFO_FULL))
 			CPRINTS("%s FIFO Overrun: %04x", s->name, fsts.len);
-		if (!IS_FSTS_EMPTY(fsts))
-			ret = load_fifo(s, &fsts, &last_fifo_read_ts);
-
-		/*
-		 * Check if FIFO isn't empty and we never got an interrupt.
-		 * This can happen if new entries were added to the FIFO after
-		 * the count was read, but before the FIFO was cleared out.
-		 * In the long term it might be better to use the last
-		 * spread timestamp instead.
-		 */
-		if (!is_fifo_empty(s, &fsts) &&
-		    triggering_interrupt_timestamp == last_interrupt_timestamp)
-			handle_interrupt_for_fifo(last_fifo_read_ts);
+		fifo_empty = fsts.len & LSM6DSM_FIFO_EMPTY;
+		if (!fifo_empty) {
+			commit_needed = true;
+			RETURN_ERROR(load_fifo(s, &fsts));
+		}
 	}
+	if (IS_ENABLED(CONFIG_ACCEL_FIFO) && commit_needed)
+		motion_sense_fifo_commit_data();
 
-	return ret;
+	return EC_SUCCESS;
 }
+#endif /* ACCEL_LSM6DSM_INT_ENABLE */
 
 /**
  * set_range - set full scale range
@@ -514,11 +422,10 @@ __maybe_unused static int irq_handler(
  * @rnd: Round up/down flag
  * Note: Range is sensitivity/gain for speed purpose
  */
-static int set_range(const struct motion_sensor_t *s, int range, int rnd)
+static int set_range(struct motion_sensor_t *s, int range, int rnd)
 {
 	int err;
 	uint8_t ctrl_reg, reg_val;
-	struct stprivate_data *data = s->drv_data;
 	int newrange = range;
 
 	switch (s->type) {
@@ -551,24 +458,11 @@ static int set_range(const struct motion_sensor_t *s, int range, int rnd)
 	err = st_write_data_with_mask(s, ctrl_reg, LSM6DSM_RANGE_MASK, reg_val);
 	if (err == EC_SUCCESS)
 		/* Save internally gain for speed optimization. */
-		data->base.range = newrange;
+		s->current_range = newrange;
 	mutex_unlock(s->mutex);
 	return err;
 }
 
-/**
- * get_range - get full scale range
- * @s: Motion sensor pointer
- *
- * For mag range is fixed to LIS2MDL_RANGE by hardware
- */
-static int get_range(const struct motion_sensor_t *s)
-{
-	struct stprivate_data *data = s->drv_data;
-
-	return data->base.range;
-}
-
 /**
  * lsm6dsm_set_data_rate
  * @s: Motion sensor pointer
@@ -580,20 +474,16 @@ static int get_range(const struct motion_sensor_t *s)
 int lsm6dsm_set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
 {
 	struct stprivate_data *data = s->drv_data;
-	const struct motion_sensor_t *accel = IS_ENABLED(CONFIG_ACCEL_FIFO) ?
-		LSM6DSM_MAIN_SENSOR(s) : NULL;
-	struct lsm6dsm_data *private = IS_ENABLED(CONFIG_ACCEL_FIFO) ?
-		LSM6DSM_GET_DATA(accel) : NULL;
+	const struct motion_sensor_t *accel = LSM6DSM_MAIN_SENSOR(s);
+	struct lsm6dsm_data *private = LSM6DSM_GET_DATA(accel);
 	int ret = EC_SUCCESS, normalized_rate = 0;
 	uint8_t ctrl_reg, reg_val = 0;
 
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
-		/* FIFO must be disabled before setting any ODR values */
-		ret = fifo_disable(accel);
-		if (ret != EC_SUCCESS) {
-			CPRINTS("Failed to disable FIFO. Error: %d", ret);
-			return ret;
-		}
+	/* FIFO must be disabled before setting any ODR values */
+	ret = fifo_disable(accel);
+	if (ret != EC_SUCCESS) {
+		CPRINTS("Failed to disable FIFO. Error: %d", ret);
+		return ret;
 	}
 
 	if (rate > 0) {
@@ -609,12 +499,12 @@ int lsm6dsm_set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
 			return EC_RES_INVALID_PARAM;
 	}
 
-#ifdef CONFIG_MAG_LSM6DSM_LIS2MDL
 	/*
 	 * TODO(b:110143516) Improve data rate selection:
 	 * Sensor is always running at 100Hz, even when not used.
 	 */
-	if (s->type == MOTIONSENSE_TYPE_MAG) {
+	if (IS_ENABLED(CONFIG_MAG_LSM6DSM_LIS2MDL) &&
+	    (s->type == MOTIONSENSE_TYPE_MAG)) {
 		struct mag_cal_t *cal = LIS2MDL_CAL(s);
 
 		init_mag_cal(cal);
@@ -623,37 +513,30 @@ int lsm6dsm_set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
 		 * less often.
 		 */
 		if (normalized_rate > 0)
-			cal->batch_size = MAX(
-				MAG_CAL_MIN_BATCH_SIZE,
-				(normalized_rate * 1000) /
-					MAG_CAL_MIN_BATCH_WINDOW_US);
+			cal->batch_size =
+				MAX(MAG_CAL_MIN_BATCH_SIZE,
+				    (normalized_rate * 1000) /
+					    MAG_CAL_MIN_BATCH_WINDOW_US);
 		else
 			cal->batch_size = 0;
 		CPRINTS("Batch size: %d", cal->batch_size);
 		mutex_lock(s->mutex);
-	} else
-#endif
-	{
+	} else {
 		mutex_lock(s->mutex);
 		ctrl_reg = LSM6DSM_ODR_REG(s->type);
 		ret = st_write_data_with_mask(s, ctrl_reg, LSM6DSM_ODR_MASK,
 					      reg_val);
 	}
 	if (ret == EC_SUCCESS) {
+		struct lsm6dsm_accel_fifo_state *fifo_state =
+			private->accel_fifo_state;
+
 		data->base.odr = normalized_rate;
-		if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
-			struct lsm6dsm_accel_fifo_state *fifo_state =
-				private->accel_fifo_state;
-			fifo_state->samples_to_discard[s->type] =
-				LSM6DSM_DISCARD_SAMPLES;
-			fifo_state->load_fifo_sensor_state[get_fifo_type(s)]
-				.sample_rate = normalized_rate == 0
-					? 0 : SECOND * 1000 / normalized_rate;
-			ret = fifo_enable(accel);
-			if (ret != EC_SUCCESS)
-				CPRINTS("Failed to enable FIFO. Error: %d",
-					ret);
-		}
+		fifo_state->samples_to_discard[s->type] =
+			LSM6DSM_DISCARD_SAMPLES;
+		ret = fifo_enable(accel);
+		if (ret != EC_SUCCESS)
+			CPRINTS("Failed to enable FIFO. Error: %d", ret);
 	}
 
 	mutex_unlock(s->mutex);
@@ -664,8 +547,8 @@ static int is_data_ready(const struct motion_sensor_t *s, int *ready)
 {
 	int ret, tmp;
 
-	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags,
-			   LSM6DSM_STATUS_REG, &tmp);
+	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, LSM6DSM_STATUS_REG,
+			   &tmp);
 	if (ret != EC_SUCCESS) {
 		CPRINTS("%s type:0x%X RS Error", s->name, s->type);
 		return ret;
@@ -688,11 +571,9 @@ static int read(const struct motion_sensor_t *s, intv3_t v)
 {
 	uint8_t raw[OUT_XYZ_SIZE];
 	uint8_t xyz_reg;
-	int ret, tmp = 0;
+	int tmp = 0;
 
-	ret = is_data_ready(s, &tmp);
-	if (ret != EC_SUCCESS)
-		return ret;
+	RETURN_ERROR(is_data_ready(s, &tmp));
 
 	/*
 	 * If sensor data is not ready, return the previous read data.
@@ -708,24 +589,22 @@ static int read(const struct motion_sensor_t *s, intv3_t v)
 	xyz_reg = get_xyz_reg(s->type);
 
 	/* Read data bytes starting at xyz_reg. */
-	ret = st_raw_read_n_noinc(s->port, s->i2c_spi_addr_flags,
-				  xyz_reg, raw, OUT_XYZ_SIZE);
-	if (ret != EC_SUCCESS)
-		return ret;
+	RETURN_ERROR(st_raw_read_n_noinc(s->port, s->i2c_spi_addr_flags,
+					 xyz_reg, raw, OUT_XYZ_SIZE));
 
 	/* Apply precision, sensitivity and rotation vector. */
 	st_normalize(s, v, raw);
 	return EC_SUCCESS;
 }
 
-static int init(const struct motion_sensor_t *s)
+static int init(struct motion_sensor_t *s)
 {
 	int ret = 0, tmp;
 	struct stprivate_data *data = s->drv_data;
 	uint8_t ctrl_reg, reg_val = 0;
 
-	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags,
-			   LSM6DSM_WHO_AM_I_REG, &tmp);
+	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, LSM6DSM_WHO_AM_I_REG,
+			   &tmp);
 	if (ret != EC_SUCCESS)
 		return EC_ERROR_UNKNOWN;
 
@@ -733,6 +612,12 @@ static int init(const struct motion_sensor_t *s)
 		/* Unrecognized sensor */
 		CPRINTS("Unknown WHO_AM_I value: 0x%x", tmp);
 		return EC_ERROR_ACCESS_DENIED;
+	} else {
+		/*
+		 * Recognized sensor
+		 * Log print for factory check chip ID (b:196781249)
+		 */
+		CPRINTS("SENSOR accelgyro_lsm6dsm WHO_AM_I value: 0x%x", tmp);
 	}
 
 	/*
@@ -756,8 +641,8 @@ static int init(const struct motion_sensor_t *s)
 			goto err_unlock;
 
 		/* Power ON Accel. */
-		ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-				    ctrl_reg, reg_val);
+		ret = st_raw_write8(s->port, s->i2c_spi_addr_flags, ctrl_reg,
+				    reg_val);
 		if (ret != EC_SUCCESS)
 			goto err_unlock;
 
@@ -767,61 +652,56 @@ static int init(const struct motion_sensor_t *s)
 		if (ret != EC_SUCCESS)
 			goto err_unlock;
 
-#ifdef CONFIG_LSM6DSM_SEC_I2C
-		/*
-		 * Reboot to reload memory content as pass-through mode can get
-		 * stuck.
-		 * Direct to the AN: See "AN4987 - LSM6DSM: always-on 3D
-		 * accelerometer and 3D gyroscope".
-		 */
-
-		/* Power ON Accel. */
-		ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-				    ctrl_reg, reg_val);
-		if (ret != EC_SUCCESS)
-			goto err_unlock;
+		if (IS_ENABLED(CONFIG_LSM6DSM_SEC_I2C)) {
+			/*
+			 * Reboot to reload memory content as pass-through mode
+			 * can get stuck.
+			 * Direct to the AN: See "AN4987 - LSM6DSM: always-on 3D
+			 * accelerometer and 3D gyroscope".
+			 */
+
+			/* Power ON Accel. */
+			ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
+					    ctrl_reg, reg_val);
+			if (ret != EC_SUCCESS)
+				goto err_unlock;
 
-		ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-				    LSM6DSM_CTRL3_ADDR, LSM6DSM_BOOT);
-		if (ret != EC_SUCCESS)
-			goto err_unlock;
+			ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
+					    LSM6DSM_CTRL3_ADDR, LSM6DSM_BOOT);
+			if (ret != EC_SUCCESS)
+				goto err_unlock;
 
-		/*
-		 * Refer to AN4987, wait 15ms for accelerometer to doing full
-		 * reboot.
-		 */
-		msleep(15);
+			/*
+			 * Refer to AN4987, wait 15ms for accelerometer to doing
+			 * full reboot.
+			 */
+			msleep(15);
 
-		/* Power OFF Accel. */
-		ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-				    ctrl_reg, 0);
-		if (ret != EC_SUCCESS)
-			goto err_unlock;
-#endif
+			/* Power OFF Accel. */
+			ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
+					    ctrl_reg, 0);
+			if (ret != EC_SUCCESS)
+				goto err_unlock;
+		}
 
 		/*
 		 * Output data not updated until have been read.
 		 * Prefer interrupt to be active low.
 		 */
-		ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-				    LSM6DSM_CTRL3_ADDR,
-				    LSM6DSM_BDU
-				    | LSM6DSM_H_L_ACTIVE
-				    | LSM6DSM_IF_INC);
+		ret = st_raw_write8(
+			s->port, s->i2c_spi_addr_flags, LSM6DSM_CTRL3_ADDR,
+			LSM6DSM_BDU | LSM6DSM_H_L_ACTIVE | LSM6DSM_IF_INC);
 		if (ret != EC_SUCCESS)
 			goto err_unlock;
 
-		if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
-			ret = fifo_disable(s);
-			if (ret != EC_SUCCESS)
-				goto err_unlock;
-		}
+		ret = fifo_disable(s);
+		if (ret != EC_SUCCESS)
+			goto err_unlock;
 
-#ifdef CONFIG_ACCEL_INTERRUPTS
-		ret = config_interrupt(s);
+		if (IS_ENABLED(ACCEL_LSM6DSM_INT_ENABLE))
+			ret = config_interrupt(s);
 		if (ret != EC_SUCCESS)
 			goto err_unlock;
-#endif /* CONFIG_ACCEL_INTERRUPTS */
 
 		mutex_unlock(s->mutex);
 	}
@@ -838,31 +718,43 @@ static int init(const struct motion_sensor_t *s)
 
 static int read_temp(const struct motion_sensor_t *s, int *temp)
 {
-	int ret;
 	uint8_t raw[2];
 
-	ret = st_raw_read_n_noinc(s->port, s->i2c_spi_addr_flags,
-				  LSM6DSM_OUT_TEMP_L_ADDR, raw, 2);
-	if (ret != EC_SUCCESS)
-		return ret;
-
+	RETURN_ERROR(st_raw_read_n_noinc(s->port, s->i2c_spi_addr_flags,
+					 LSM6DSM_OUT_TEMP_L_ADDR, raw, 2));
 	*temp = C_TO_K(25 + (int)raw[1]);
 
 	return EC_SUCCESS;
 }
 
+#ifdef CONFIG_BODY_DETECTION
+static int get_rms_noise(const struct motion_sensor_t *s)
+{
+	/*
+	 * RMS | Acceleration RMS noise in normal/low-power mode
+	 * FS = ±4 g | 2.0 mg(RMS)
+	 */
+	return 2000;
+}
+#endif
+
 const struct accelgyro_drv lsm6dsm_drv = {
 	.init = init,
 	.read = read,
 	.set_range = set_range,
-	.get_range = get_range,
 	.get_resolution = st_get_resolution,
 	.set_data_rate = lsm6dsm_set_data_rate,
 	.get_data_rate = st_get_data_rate,
 	.read_temp = read_temp,
 	.set_offset = st_set_offset,
 	.get_offset = st_get_offset,
-#ifdef CONFIG_ACCEL_INTERRUPTS
+#ifdef ACCEL_LSM6DSM_INT_ENABLE
 	.irq_handler = irq_handler,
-#endif /* CONFIG_ACCEL_INTERRUPTS */
+#endif /* ACCEL_LSM6DSM_INT_ENABLE */
+#ifdef CONFIG_BODY_DETECTION
+	.get_rms_noise = get_rms_noise,
+#endif
+#ifdef CONFIG_GESTURE_HOST_DETECTION
+	.list_activities = st_list_activities,
+#endif
 };
diff --git a/driver/accelgyro_lsm6dsm.h b/driver/accelgyro_lsm6dsm.h
index 7be2219be0..8fa53c6a6d 100644
--- a/driver/accelgyro_lsm6dsm.h
+++ b/driver/accelgyro_lsm6dsm.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,174 +8,172 @@
 #ifndef __CROS_EC_ACCELGYRO_LSM6DSM_H
 #define __CROS_EC_ACCELGYRO_LSM6DSM_H
 
-#include "stm_mems_common.h"
-#include "mag_cal.h"
 #include "mag_bmm150.h"
+#include "mag_cal.h"
 #include "mag_lis2mdl.h"
+#include "stm_mems_common.h"
 
 /*
  * 7-bit address is 110101xb. Where 'x' is determined
  * by the voltage on the ADDR pin
  */
-#define LSM6DSM_ADDR0_FLAGS		0x6a
-#define LSM6DSM_ADDR1_FLAGS		0x6b
+#define LSM6DSM_ADDR0_FLAGS 0x6a
+#define LSM6DSM_ADDR1_FLAGS 0x6b
 
 /* COMMON DEFINE FOR ACCEL-GYRO SENSORS */
-#define LSM6DSM_EN_BIT			0x01
-#define LSM6DSM_DIS_BIT			0x00
+#define LSM6DSM_EN_BIT 0x01
+#define LSM6DSM_DIS_BIT 0x00
 
 /* Access to embedded sensor hub register bank */
-#define LSM6DSM_FUNC_CFG_ACC_ADDR	0x01
-#define LSM6DSM_FUNC_CFG_EN			0x80
-#define LSM6DSM_FUNC_CFG_EN_B			0x20
+#define LSM6DSM_FUNC_CFG_ACC_ADDR 0x01
+#define LSM6DSM_FUNC_CFG_EN 0x80
+#define LSM6DSM_FUNC_CFG_EN_B 0x20
 
 /* FIFO decimator registers and bitmask */
-#define LSM6DSM_FIFO_CTRL1_ADDR		0x06
+#define LSM6DSM_FIFO_CTRL1_ADDR 0x06
 
 /* Output data rate registers and masks */
-#define LSM6DSM_ODR_REG(_sensor) \
-	(LSM6DSM_CTRL1_ADDR + _sensor)
-#define LSM6DSM_ODR_MASK		0xf0
+#define LSM6DSM_ODR_REG(_sensor) (LSM6DSM_CTRL1_ADDR + _sensor)
+#define LSM6DSM_ODR_MASK 0xf0
 
-#define LSM6DSM_FIFO_CTRL2_ADDR		0x07
+#define LSM6DSM_FIFO_CTRL2_ADDR 0x07
 
-#define LSM6DSM_FIFO_CTRL3_ADDR		0x08
-#define LSM6DSM_FIFO_DEC_XL_OFF			0
-#define LSM6DSM_FIFO_DEC_G_OFF			3
+#define LSM6DSM_FIFO_CTRL3_ADDR 0x08
+#define LSM6DSM_FIFO_DEC_XL_OFF 0
+#define LSM6DSM_FIFO_DEC_G_OFF 3
 
-#define LSM6DSM_FIFO_CTRL4_ADDR		0x09
+#define LSM6DSM_FIFO_CTRL4_ADDR 0x09
 
 #define LSM6DSM_FIFO_DECIMATOR(_dec) \
 	(_dec < 8 ? _dec : (2 + __builtin_ctz(_dec)))
 
 /* Hardware FIFO size in byte */
-#define LSM6DSM_MAX_FIFO_SIZE		4096
-#define LSM6DSM_MAX_FIFO_LENGTH	(LSM6DSM_MAX_FIFO_SIZE / OUT_XYZ_SIZE)
+#define LSM6DSM_MAX_FIFO_SIZE 4096
+#define LSM6DSM_MAX_FIFO_LENGTH (LSM6DSM_MAX_FIFO_SIZE / OUT_XYZ_SIZE)
 
-#define LSM6DSM_FIFO_CTRL5_ADDR		0x0a
-#define LSM6DSM_FIFO_CTRL5_ODR_OFF		3
-#define LSM6DSM_FIFO_CTRL5_ODR_MASK \
-	(0xf << LSM6DSM_FIFO_CTRL5_ODR_OFF)
-#define LSM6DSM_FIFO_CTRL5_MODE_MASK		0x07
+#define LSM6DSM_FIFO_CTRL5_ADDR 0x0a
+#define LSM6DSM_FIFO_CTRL5_ODR_OFF 3
+#define LSM6DSM_FIFO_CTRL5_ODR_MASK (0xf << LSM6DSM_FIFO_CTRL5_ODR_OFF)
+#define LSM6DSM_FIFO_CTRL5_MODE_MASK 0x07
 
-#define LSM6DSM_INT1_CTRL		0x0d
-#define LSM6DSM_INT_FIFO_TH			0x08
-#define LSM6DSM_INT_FIFO_OVR			0x10
-#define LSM6DSM_INT_FIFO_FULL			0x20
-#define LSM6DSM_INT_SIGMO			0x40
+#define LSM6DSM_INT1_CTRL 0x0d
+#define LSM6DSM_INT_FIFO_TH 0x08
+#define LSM6DSM_INT_FIFO_OVR 0x10
+#define LSM6DSM_INT_FIFO_FULL 0x20
+#define LSM6DSM_INT_SIGMO 0x40
 
 /* Who Am I */
-#define LSM6DSM_WHO_AM_I_REG		0x0f
+#define LSM6DSM_WHO_AM_I_REG 0x0f
 /* LSM6DSM/LSM6DSL/LSM6DS3TR-C */
-#define LSM6DSM_WHO_AM_I			0x6a
+#define LSM6DSM_WHO_AM_I 0x6a
 /* LSM6DS3 */
-#define LSM6DS3_WHO_AM_I			0x69
-
-#define LSM6DSM_CTRL1_ADDR		0x10
-#define LSM6DSM_XL_ODR_MASK			0xf0
-
-#define LSM6DSM_CTRL2_ADDR		0x11
-#define LSM6DSM_CTRL3_ADDR		0x12
-#define LSM6DSM_SW_RESET			0x01
-#define LSM6DSM_IF_INC				0x04
-#define LSM6DSM_PP_OD				0x10
-#define LSM6DSM_H_L_ACTIVE			0x20
-#define LSM6DSM_BDU				0x40
-#define LSM6DSM_BOOT				0x80
-
-#define LSM6DSM_CTRL4_ADDR		0x13
-#define LSM6DSM_INT2_ON_INT1_MASK		0x20
-
-#define LSM6DSM_CTRL6_ADDR		0x15
-#define LSM6DSM_CTRL7_ADDR		0x16
-
-#define LSM6DSM_CTRL10_ADDR		0x19
-#define LSM6DSM_FUNC_EN_MASK			0x04
-#define LSM6DSM_SIG_MOT_MASK			0x01
-#define LSM6DSM_EMBED_FUNC_EN			0x04
-#define LSM6DSM_SIG_MOT_EN			0x01
-
-/* Master mode configuration register */
-#define LSM6DSM_MASTER_CFG_ADDR		0x1a
-#define LSM6DSM_PASSTROUGH_MASK			0x1f
-#define LSM6DSM_EXT_TRIGGER_EN			0x10
-#define LSM6DSM_PULLUP_EN			0x08
-#define LSM6DSM_I2C_PASS_THRU_MODE		0x04
-#define LSM6DSM_I2C_MASTER_ON			0x01
-
-#define LSM6DSM_TAP_SRC_ADDR		0x1c
-#define LSM6DSM_STAP_DETECT			0x20
-#define LSM6DSM_DTAP_DETECT			0x10
-
-#define LSM6DSM_STATUS_REG		0x1e
-
-#define LSM6DSM_OUT_TEMP_L_ADDR		0x20
-
-#define LSM6DSM_GYRO_OUT_X_L_ADDR	0x22
-#define LSM6DSM_ACCEL_OUT_X_L_ADDR	0x28
-
-#define LSM6DSM_SENSORHUB1_REG		0x2e
-
-#define LSM6DSM_FIFO_STS1_ADDR		0x3a
-#define LSM6DSM_FIFO_STS2_ADDR		0x3b
-#define LSM6DSM_FIFO_DIFF_MASK			0x0fff
-#define LSM6DSM_FIFO_EMPTY			0x1000
-#define LSM6DSM_FIFO_FULL			0x2000
-#define LSM6DSM_FIFO_DATA_OVR			0x4000
-#define LSM6DSM_FIFO_WATERMARK			0x8000
-#define LSM6DSM_FIFO_NODECIM			0x01
+#define LSM6DS3_WHO_AM_I 0x69
+
+#define LSM6DSM_CTRL1_ADDR 0x10
+#define LSM6DSM_XL_ODR_MASK 0xf0
+
+#define LSM6DSM_CTRL2_ADDR 0x11
+#define LSM6DSM_CTRL3_ADDR 0x12
+#define LSM6DSM_SW_RESET 0x01
+#define LSM6DSM_IF_INC 0x04
+#define LSM6DSM_PP_OD 0x10
+#define LSM6DSM_H_L_ACTIVE 0x20
+#define LSM6DSM_BDU 0x40
+#define LSM6DSM_BOOT 0x80
+
+#define LSM6DSM_CTRL4_ADDR 0x13
+#define LSM6DSM_INT2_ON_INT1_MASK 0x20
+
+#define LSM6DSM_CTRL6_ADDR 0x15
+#define LSM6DSM_CTRL7_ADDR 0x16
+
+#define LSM6DSM_CTRL10_ADDR 0x19
+#define LSM6DSM_FUNC_EN_MASK 0x04
+#define LSM6DSM_SIG_MOT_MASK 0x01
+#define LSM6DSM_EMBED_FUNC_EN 0x04
+#define LSM6DSM_SIG_MOT_EN 0x01
+
+/* Controller mode configuration register */
+#define LSM6DSM_CONTROLLER_CFG_ADDR 0x1a
+#define LSM6DSM_PASSTROUGH_MASK 0x1f
+#define LSM6DSM_EXT_TRIGGER_EN 0x10
+#define LSM6DSM_PULLUP_EN 0x08
+#define LSM6DSM_I2C_PASS_THRU_MODE 0x04
+#define LSM6DSM_I2C_CONTROLLER_ON 0x01
+
+#define LSM6DSM_TAP_SRC_ADDR 0x1c
+#define LSM6DSM_STAP_DETECT 0x20
+#define LSM6DSM_DTAP_DETECT 0x10
+
+#define LSM6DSM_STATUS_REG 0x1e
+
+#define LSM6DSM_OUT_TEMP_L_ADDR 0x20
+
+#define LSM6DSM_GYRO_OUT_X_L_ADDR 0x22
+#define LSM6DSM_ACCEL_OUT_X_L_ADDR 0x28
+
+#define LSM6DSM_SENSORHUB1_REG 0x2e
+
+#define LSM6DSM_FIFO_STS1_ADDR 0x3a
+#define LSM6DSM_FIFO_STS2_ADDR 0x3b
+#define LSM6DSM_FIFO_DIFF_MASK 0x0fff
+#define LSM6DSM_FIFO_EMPTY 0x1000
+#define LSM6DSM_FIFO_FULL 0x2000
+#define LSM6DSM_FIFO_DATA_OVR 0x4000
+#define LSM6DSM_FIFO_WATERMARK 0x8000
+#define LSM6DSM_FIFO_NODECIM 0x01
 
 /* Out data register */
-#define LSM6DSM_FIFO_DATA_ADDR		0x3e
+#define LSM6DSM_FIFO_DATA_ADDR 0x3e
 
 /* Registers value for supported FIFO mode */
-#define LSM6DSM_FIFO_MODE_BYPASS_VAL		0x00
-#define LSM6DSM_FIFO_MODE_CONTINUOUS_VAL	0x06
+#define LSM6DSM_FIFO_MODE_BYPASS_VAL 0x00
+#define LSM6DSM_FIFO_MODE_CONTINUOUS_VAL 0x06
 
-#define LSM6DSM_FUNC_SRC1_ADDR		0x53
-#define LSM6DSM_SENSORHUB_END_OP		0x01
-#define LSM6DSM_SIGN_MOTION_IA			0x40
+#define LSM6DSM_FUNC_SRC1_ADDR 0x53
+#define LSM6DSM_SENSORHUB_END_OP 0x01
+#define LSM6DSM_SIGN_MOTION_IA 0x40
 
-#define LSM6DSM_LIR_ADDR		0x58
-#define LSM6DSM_LIR_MASK			0x01
-#define LSM6DSM_EN_INT				0x80
-#define LSM6DSM_EN_TAP				0x0e
-#define LSM6DSM_TAP_MASK			0x8e
+#define LSM6DSM_LIR_ADDR 0x58
+#define LSM6DSM_LIR_MASK 0x01
+#define LSM6DSM_EN_INT 0x80
+#define LSM6DSM_EN_TAP 0x0e
+#define LSM6DSM_TAP_MASK 0x8e
 
-#define LSM6DSM_TAP_THS_6D		0x59
-#define LSM6DSM_D4D_EN_MASK			0x80
-#define LSM6DSM_TAP_TH_MASK			0x1f
+#define LSM6DSM_TAP_THS_6D 0x59
+#define LSM6DSM_D4D_EN_MASK 0x80
+#define LSM6DSM_TAP_TH_MASK 0x1f
 
-#define LSM6DSM_INT_DUR2_ADDR		0x5a
-#define LSM6DSM_TAP_DUR_MASK			0xf0
-#define LSM6DSM_TAP_QUIET_MASK			0x0c
+#define LSM6DSM_INT_DUR2_ADDR 0x5a
+#define LSM6DSM_TAP_DUR_MASK 0xf0
+#define LSM6DSM_TAP_QUIET_MASK 0x0c
 
-#define LSM6DSM_WUP_THS_ADDR		0x5b
-#define LSM6DSM_S_D_TAP_MASK			0x80
-#define LSM6DSM_STAP_EN				0
-#define LSM6DSM_DTAP_EN				1
+#define LSM6DSM_WUP_THS_ADDR 0x5b
+#define LSM6DSM_S_D_TAP_MASK 0x80
+#define LSM6DSM_STAP_EN 0
+#define LSM6DSM_DTAP_EN 1
 
-#define LSM6DSM_MD1_CFG_ADDR		0x5e
-#define LSM6DSM_INT1_STAP			0x40
-#define LSM6DSM_INT1_DTAP			0x08
+#define LSM6DSM_MD1_CFG_ADDR 0x5e
+#define LSM6DSM_INT1_STAP 0x40
+#define LSM6DSM_INT1_DTAP 0x08
 
 /* Register values for Sensor Hub Slave 0 / Bank A */
-#define LSM6DSM_SLV0_ADD_ADDR		0x02
-#define LSM6DSM_SLV0_ADDR_SHFT			1
-#define LSM6DSM_SLV0_ADDR_MASK			0xfe
-#define LSM6DSM_SLV0_RD_BIT			0x01
+#define LSM6DSM_SLV0_ADD_ADDR 0x02
+#define LSM6DSM_SLV0_ADDR_SHFT 1
+#define LSM6DSM_SLV0_ADDR_MASK 0xfe
+#define LSM6DSM_SLV0_RD_BIT 0x01
 
-#define LSM6DSM_SLV0_SUBADD_ADDR	0x03
+#define LSM6DSM_SLV0_SUBADD_ADDR 0x03
 
-#define LSM6DSM_SLV0_CONFIG_ADDR	0x04
-#define LSM6DSM_SLV0_SLV_RATE_SHFT		6
-#define LSM6DSM_SLV0_SLV_RATE_MASK		0xc0
-#define LSM6DSM_SLV0_AUX_SENS_SHFT		4
-#define LSM6DSM_SLV0_AUX_SENS_MASK		0x30
-#define LSM6DSM_SLV0_NUM_OPS_MASK		0x07
+#define LSM6DSM_SLV0_CONFIG_ADDR 0x04
+#define LSM6DSM_SLV0_SLV_RATE_SHFT 6
+#define LSM6DSM_SLV0_SLV_RATE_MASK 0xc0
+#define LSM6DSM_SLV0_AUX_SENS_SHFT 4
+#define LSM6DSM_SLV0_AUX_SENS_MASK 0x30
+#define LSM6DSM_SLV0_NUM_OPS_MASK 0x07
 
-#define LSM6DSM_SLV1_CONFIG_ADDR	0x07
-#define LSM6DSM_SLV0_WR_ONCE_MASK		0x20
+#define LSM6DSM_SLV1_CONFIG_ADDR 0x07
+#define LSM6DSM_SLV0_WR_ONCE_MASK 0x20
 
 #define LSM6DSM_DATA_WRITE_SUB_SLV0_ADDR 0x0e
 
@@ -184,19 +182,22 @@ enum dev_fifo {
 	FIFO_DEV_INVALID = -1,
 	FIFO_DEV_GYRO = 0,
 	FIFO_DEV_ACCEL,
-#ifdef CONFIG_LSM6DSM_SEC_I2C
 	FIFO_DEV_MAG,
-#endif
-	FIFO_DEV_NUM,
 };
 
+#ifdef CONFIG_LSM6DSM_SEC_I2C
+#define FIFO_DEV_NUM (FIFO_DEV_MAG + 1)
+#else
+#define FIFO_DEV_NUM (FIFO_DEV_ACCEL + 1)
+#endif
+
 struct fstatus {
 	uint16_t len;
 	uint16_t pattern;
 };
 
 /* Absolute maximum rate for acc and gyro sensors */
-#define LSM6DSM_ODR_MIN_VAL		13000
+#define LSM6DSM_ODR_MIN_VAL 13000
 #define LSM6DSM_ODR_MAX_VAL \
 	MOTION_MAX_SENSOR_FREQUENCY(416000, LSM6DSM_ODR_MIN_VAL)
 
@@ -207,31 +208,30 @@ struct fstatus {
 #define LSM6DSM_REG_TO_ODR(_reg) (LSM6DSM_ODR_MIN_VAL << (_reg - 1))
 
 /* Full Scale range value and gain for Acc */
-#define LSM6DSM_FS_LIST_NUM		4
+#define LSM6DSM_FS_LIST_NUM 4
 
-#define LSM6DSM_ACCEL_FS_ADDR		0x10
-#define LSM6DSM_ACCEL_FS_MASK		0x0c
+#define LSM6DSM_ACCEL_FS_ADDR 0x10
+#define LSM6DSM_ACCEL_FS_MASK 0x0c
 
-#define LSM6DSM_ACCEL_FS_2G_VAL		0x00
-#define LSM6DSM_ACCEL_FS_4G_VAL		0x02
-#define LSM6DSM_ACCEL_FS_8G_VAL		0x03
-#define LSM6DSM_ACCEL_FS_16G_VAL	0x01
+#define LSM6DSM_ACCEL_FS_2G_VAL 0x00
+#define LSM6DSM_ACCEL_FS_4G_VAL 0x02
+#define LSM6DSM_ACCEL_FS_8G_VAL 0x03
+#define LSM6DSM_ACCEL_FS_16G_VAL 0x01
 
-#define LSM6DSM_ACCEL_FS_MAX_VAL	16
+#define LSM6DSM_ACCEL_FS_MAX_VAL 16
 
 /* Accel Reg value from Full Scale */
-#define LSM6DSM_ACCEL_FS_REG(_fs) \
-	(_fs == 2 ? LSM6DSM_ACCEL_FS_2G_VAL : \
-	_fs == 16 ? LSM6DSM_ACCEL_FS_16G_VAL : \
-	__fls(_fs))
+#define LSM6DSM_ACCEL_FS_REG(_fs)               \
+	(_fs == 2  ? LSM6DSM_ACCEL_FS_2G_VAL :  \
+	 _fs == 16 ? LSM6DSM_ACCEL_FS_16G_VAL : \
+		     __fls(_fs))
 
 /* Accel normalized FS value from Full Scale */
 #define LSM6DSM_ACCEL_NORMALIZE_FS(_fs) (1 << __fls(_fs))
 
 /* Full Scale range value and gain for Gyro */
-#define LSM6DSM_GYRO_FS_ADDR		0x11
-#define LSM6DSM_GYRO_FS_MASK		0x0c
-
+#define LSM6DSM_GYRO_FS_ADDR 0x11
+#define LSM6DSM_GYRO_FS_MASK 0x0c
 
 /* Supported gyroscope ranges:
  * name(dps) | register | gain(udps/LSB) | actual value(dps)
@@ -252,8 +252,8 @@ struct fstatus {
 	((LSM6DSM_GYRO_FS_MIN_VAL_MDPS << (_reg)) / 1000)
 
 /* FS register address/mask for Acc/Gyro sensors */
-#define LSM6DSM_RANGE_REG(_sensor)  (LSM6DSM_ACCEL_FS_ADDR + (_sensor))
-#define LSM6DSM_RANGE_MASK		0x0c
+#define LSM6DSM_RANGE_REG(_sensor) (LSM6DSM_ACCEL_FS_ADDR + (_sensor))
+#define LSM6DSM_RANGE_MASK 0x0c
 
 /* Status register bitmask for Acc/Gyro data ready */
 enum lsm6dsm_status {
@@ -262,11 +262,11 @@ enum lsm6dsm_status {
 	LSM6DSM_STS_GDA_UP = 0x02
 };
 
-#define LSM6DSM_STS_XLDA_MASK		0x01
-#define LSM6DSM_STS_GDA_MASK		0x02
+#define LSM6DSM_STS_XLDA_MASK 0x01
+#define LSM6DSM_STS_GDA_MASK 0x02
 
 /* Sensor resolution in number of bits: fixed 16 bit */
-#define LSM6DSM_RESOLUTION		16
+#define LSM6DSM_RESOLUTION 16
 
 extern const struct accelgyro_drv lsm6dsm_drv;
 
@@ -290,17 +290,6 @@ struct lsm6dsm_fifo_data {
 	int total_samples_in_pattern;
 };
 
-/*
- * Structure used to maintain the load state per sensor. This will be used to
- * properly spread values in case we have more than one reading for a given
- * sensor in a single fifo read pass.
- */
-struct load_fifo_sensor_state_t {
-	uint32_t int_timestamp;
-	uint8_t sample_count;
-	int sample_rate;
-};
-
 /**
  * Structure used to hold fifo state. This struct should only be used if
  * CONFIG_ACCEL_FIFO is defined.
@@ -314,7 +303,6 @@ struct lsm6dsm_accel_fifo_state {
 	 * initial samples with incorrect values
 	 */
 	unsigned int samples_to_discard[FIFO_DEV_NUM];
-	struct load_fifo_sensor_state_t load_fifo_sensor_state[FIFO_DEV_NUM];
 };
 
 /*
@@ -356,24 +344,24 @@ struct lsm6dsm_data {
 #if defined(CONFIG_LSM6DSM_SEC_I2C) && defined(CONFIG_MAG_CALIBRATE)
 	union {
 #ifdef CONFIG_MAG_LSM6DSM_BMM150
-		struct bmm150_private_data   compass;
+		struct bmm150_private_data compass;
 #endif
 #ifdef CONFIG_MAG_LSM6DSM_LIS2MDL
-		struct lis2mdl_private_data  compass;
+		struct lis2mdl_private_data compass;
 #endif
-		struct mag_cal_t             cal;
+		struct mag_cal_t cal;
 	};
-#endif  /* CONFIG_MAG_CALIBRATE */
+#endif /* CONFIG_MAG_CALIBRATE */
 };
 
 #ifdef CONFIG_ACCEL_FIFO
-#define LSM6DSM_ACCEL_FIFO_STATE (&((struct lsm6dsm_accel_fifo_state) {}))
+#define LSM6DSM_ACCEL_FIFO_STATE (&((struct lsm6dsm_accel_fifo_state){}))
 #else
 #define LSM6DSM_ACCEL_FIFO_STATE NULL
 #endif
 
-#define LSM6DSM_DATA \
-	((struct lsm6dsm_data) { \
+#define LSM6DSM_DATA                                          \
+	((struct lsm6dsm_data){                               \
 		.accel_fifo_state = LSM6DSM_ACCEL_FIFO_STATE, \
 	})
 
@@ -398,5 +386,21 @@ struct lsm6dsm_data {
 
 int lsm6dsm_set_data_rate(const struct motion_sensor_t *s, int rate, int rnd);
 
+#if defined(CONFIG_ZEPHYR)
+/* Get the motion sensor ID of the LSM6DSM sensor that generates the
+ * interrupt. The interrupt is converted to the event and transferred to
+ * motion sense task that actually handles the interrupt.
+ *
+ * Here we use an alias (lsm6dsm_int) to get the motion sensor ID. This alias
+ * MUST be defined for this driver to work.
+ * aliases {
+ *   lsm6dsm-int = &lid_accel;
+ * };
+ */
+#if DT_NODE_EXISTS(DT_ALIAS(lsm6dsm_int))
+#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(SENSOR_ID(DT_ALIAS(lsm6dsm_int)))
+#endif
+#endif
 
 #endif /* __CROS_EC_ACCELGYRO_LSM6DSM_H */
diff --git a/driver/accelgyro_lsm6dso.c b/driver/accelgyro_lsm6dso.c
index e8ea0794d7..58679dbed9 100644
--- a/driver/accelgyro_lsm6dso.c
+++ b/driver/accelgyro_lsm6dso.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,9 +19,14 @@
 #include "task.h"
 #include "timer.h"
 
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
+#ifdef CONFIG_ACCEL_LSM6DSO_INT_EVENT
+#define ACCEL_LSM6DSO_INT_ENABLE
+#endif
 
-STATIC_IF(CONFIG_ACCEL_FIFO) volatile uint32_t last_interrupt_timestamp;
+#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args)
+
+STATIC_IF(ACCEL_LSM6DSO_INT_ENABLE)
+volatile uint32_t last_interrupt_timestamp;
 
 /*
  * When ODR change, the sensor filters need settling time;
@@ -39,7 +44,7 @@ static inline int get_xyz_reg(enum motionsensor_type type)
 	       (LSM6DSO_ACCEL_OUT_X_L_ADDR - LSM6DSO_GYRO_OUT_X_L_ADDR) * type;
 }
 
-#ifdef CONFIG_ACCEL_INTERRUPTS
+#ifdef ACCEL_LSM6DSO_INT_ENABLE
 /**
  * Configure interrupt int 1 to fire handler for:
  *
@@ -52,9 +57,6 @@ static int config_interrupt(const struct motion_sensor_t *s)
 	int ret = EC_SUCCESS;
 	int int1_ctrl_val;
 
-	if (!IS_ENABLED(CONFIG_ACCEL_FIFO))
-		return ret;
-
 	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, LSM6DSO_INT1_CTRL,
 			   &int1_ctrl_val);
 	if (ret != EC_SUCCESS)
@@ -73,7 +75,7 @@ static int config_interrupt(const struct motion_sensor_t *s)
 		return ret;
 
 	int1_ctrl_val |= LSM6DSO_INT_FIFO_TH | LSM6DSO_INT_FIFO_OVR |
-		LSM6DSO_INT_FIFO_FULL;
+			 LSM6DSO_INT_FIFO_FULL;
 
 	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags, LSM6DSO_INT1_CTRL,
 			    int1_ctrl_val);
@@ -111,7 +113,6 @@ static int fifo_enable(const struct motion_sensor_t *s)
 static void push_fifo_data(struct motion_sensor_t *main_s, uint8_t *fifo,
 			   uint32_t saved_ts)
 {
-	struct ec_response_motion_sensor_data vect;
 	struct motion_sensor_t *sensor;
 	uint8_t tag;
 	int id;
@@ -148,41 +149,39 @@ static void push_fifo_data(struct motion_sensor_t *main_s, uint8_t *fifo,
 
 	/* Apply precision, sensitivity and rotation. */
 	st_normalize(sensor, axis, ptr);
-	vect.data[X] = axis[X];
-	vect.data[Y] = axis[Y];
-	vect.data[Z] = axis[Z];
+	if (IS_ENABLED(CONFIG_ACCEL_SPOOF_MODE) &&
+	    sensor->flags & MOTIONSENSE_FLAG_IN_SPOOF_MODE)
+		axis = sensor->spoof_xyz;
+	if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
+		struct ec_response_motion_sensor_data vect;
+
+		vect.data[X] = axis[X];
+		vect.data[Y] = axis[Y];
+		vect.data[Z] = axis[Z];
 
-	vect.flags = 0;
-	vect.sensor_num = sensor - motion_sensors;
-	motion_sense_fifo_stage_data(&vect, sensor, 3, saved_ts);
+		vect.flags = 0;
+		vect.sensor_num = sensor - motion_sensors;
+		motion_sense_fifo_stage_data(&vect, sensor, 3, saved_ts);
+	} else {
+		motion_sense_push_raw_xyz(sensor);
+	}
 }
 
-static inline int load_fifo(struct motion_sensor_t *s,
-			    const struct lsm6dso_fstatus *fsts,
-			    uint32_t saved_ts)
+static inline int load_fifo(struct motion_sensor_t *main_s,
+			    const uint16_t fifo_len)
 {
-	uint8_t fifo[FIFO_READ_LEN], *ptr;
-	int i, err, read_len = 0, word_len, fifo_len;
-	uint16_t fifo_depth;
-
-	fifo_depth = fsts->len & LSM6DSO_FIFO_DIFF_MASK;
-	fifo_len = fifo_depth * LSM6DSO_FIFO_SAMPLE_SIZE;
-	while (read_len < fifo_len) {
-		word_len = GENERIC_MIN(fifo_len - read_len, sizeof(fifo));
-		err = st_raw_read_n_noinc(s->port, s->i2c_spi_addr_flags,
-					  LSM6DSO_FIFO_DATA_ADDR_TAG,
-					  fifo, word_len);
-		if (err != EC_SUCCESS)
-			return err;
-
-		for (i = 0; i < word_len; i += LSM6DSO_FIFO_SAMPLE_SIZE) {
-			ptr = &fifo[i];
-			push_fifo_data(LSM6DSO_MAIN_SENSOR(s), ptr, saved_ts);
-		}
-		read_len += word_len;
+	uint8_t fifo[LSM6DSO_FIFO_SAMPLE_SIZE];
+	int i;
+
+	for (i = 0; i < fifo_len; i++) {
+		RETURN_ERROR(st_raw_read_n_noinc(
+			main_s->port, main_s->i2c_spi_addr_flags,
+			LSM6DSO_FIFO_DATA_ADDR_TAG, fifo, sizeof(fifo)));
+
+		push_fifo_data(main_s, fifo, last_interrupt_timestamp);
 	}
 
-	return read_len;
+	return EC_SUCCESS;
 }
 
 /**
@@ -191,7 +190,7 @@ static inline int load_fifo(struct motion_sensor_t *s,
 static int accelgyro_config_fifo(const struct motion_sensor_t *s)
 {
 	int err;
-	struct stprivate_data *data = LSM6DSO_GET_DATA(s);
+	struct stprivate_data *data = s->drv_data;
 	uint8_t reg_val;
 	uint8_t fifo_odr_mask;
 
@@ -206,10 +205,10 @@ static int accelgyro_config_fifo(const struct motion_sensor_t *s)
 	 */
 	samples_to_discard[s->type] = LSM6DSO_DISCARD_SAMPLES;
 
-	fifo_odr_mask = LSM6DSO_FIFO_ODR_TO_REG(s);
+	fifo_odr_mask = LSM6DSO_FIFO_ODR_MASK(s);
 	reg_val = LSM6DSO_ODR_TO_REG(data->base.odr);
-	err = st_write_data_with_mask(s, LSM6DSO_FIFO_CTRL3_ADDR,
-				      fifo_odr_mask, reg_val);
+	err = st_write_data_with_mask(s, LSM6DSO_FIFO_CTRL3_ADDR, fifo_odr_mask,
+				      reg_val);
 	if (err != EC_SUCCESS)
 		return err;
 
@@ -221,11 +220,9 @@ static int accelgyro_config_fifo(const struct motion_sensor_t *s)
  */
 void lsm6dso_interrupt(enum gpio_signal signal)
 {
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO))
-		last_interrupt_timestamp = __hw_clock_source_read();
+	last_interrupt_timestamp = __hw_clock_source_read();
 
-	task_set_event(TASK_ID_MOTIONSENSE,
-		       CONFIG_ACCEL_LSM6DSO_INT_EVENT, 0);
+	task_set_event(TASK_ID_MOTIONSENSE, CONFIG_ACCEL_LSM6DSO_INT_EVENT);
 }
 
 /**
@@ -233,35 +230,35 @@ void lsm6dso_interrupt(enum gpio_signal signal)
  */
 static int irq_handler(struct motion_sensor_t *s, uint32_t *event)
 {
-	int ret = EC_SUCCESS;
+	int fifo_len = 0;
 	struct lsm6dso_fstatus fsts;
+	bool has_read_fifo = false;
 
-	if (((s->type != MOTIONSENSE_TYPE_ACCEL) &&
-	     (s->type != MOTIONSENSE_TYPE_GYRO)) ||
+	if ((s->type != MOTIONSENSE_TYPE_ACCEL) ||
 	    (!(*event & CONFIG_ACCEL_LSM6DSO_INT_EVENT)))
 		return EC_ERROR_NOT_HANDLED;
 
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
+	do {
 		/* Read how many data patterns on FIFO to read. */
-		ret = st_raw_read_n_noinc(s->port, s->i2c_spi_addr_flags,
-					  LSM6DSO_FIFO_STS1_ADDR,
-					  (uint8_t *)&fsts, sizeof(fsts));
-		if (ret != EC_SUCCESS)
-			return ret;
-
+		RETURN_ERROR(st_raw_read_n_noinc(
+			s->port, s->i2c_spi_addr_flags, LSM6DSO_FIFO_STS1_ADDR,
+			(uint8_t *)&fsts, sizeof(fsts)));
 		if (fsts.len & (LSM6DSO_FIFO_DATA_OVR | LSM6DSO_FIFO_FULL))
 			CPRINTS("%s FIFO Overrun: %04x", s->name, fsts.len);
 
-		if (fsts.len & LSM6DSO_FIFO_DIFF_MASK)
-			ret = load_fifo(s, &fsts, last_interrupt_timestamp);
+		fifo_len = fsts.len & LSM6DSO_FIFO_DIFF_MASK;
+		if (fifo_len) {
+			RETURN_ERROR(load_fifo(s, fifo_len));
+			has_read_fifo = true;
+		}
+	} while (fifo_len != 0);
 
-		if (IS_ENABLED(CONFIG_ACCEL_FIFO) && ret > 0)
-			motion_sense_fifo_commit_data();
-	}
+	if (IS_ENABLED(CONFIG_ACCEL_FIFO) && has_read_fifo)
+		motion_sense_fifo_commit_data();
 
-	return ret;
+	return EC_SUCCESS;
 }
-#endif /* CONFIG_ACCEL_INTERRUPTS */
+#endif /* ACCEL_LSM6DSO_INT_ENABLE */
 
 /**
  * set_range - set full scale range
@@ -270,11 +267,10 @@ static int irq_handler(struct motion_sensor_t *s, uint32_t *event)
  * @rnd: Round up/down flag
  * Note: Range is sensitivity/gain for speed purpose
  */
-static int set_range(const struct motion_sensor_t *s, int range, int rnd)
+static int set_range(struct motion_sensor_t *s, int range, int rnd)
 {
 	int err;
 	uint8_t ctrl_reg, reg_val;
-	struct stprivate_data *data = LSM6DSO_GET_DATA(s);
 	int newrange = range;
 
 	ctrl_reg = LSM6DSO_RANGE_REG(s->type);
@@ -300,27 +296,15 @@ static int set_range(const struct motion_sensor_t *s, int range, int rnd)
 	}
 
 	mutex_lock(s->mutex);
-	err = st_write_data_with_mask(s, ctrl_reg, LSM6DSO_RANGE_MASK,
-				      reg_val);
+	err = st_write_data_with_mask(s, ctrl_reg, LSM6DSO_RANGE_MASK, reg_val);
 	if (err == EC_SUCCESS)
-		data->base.range = newrange;
+		s->current_range = newrange;
 
 	mutex_unlock(s->mutex);
 
 	return EC_SUCCESS;
 }
 
-/**
- * get_range - get full scale range
- * @s: Motion sensor pointer
- */
-static int get_range(const struct motion_sensor_t *s)
-{
-	struct stprivate_data *data = LSM6DSO_GET_DATA(s);
-
-	return data->base.range;
-}
-
 /**
  * set_data_rate set sensor data rate
  * @s: Motion sensor pointer
@@ -330,7 +314,7 @@ static int get_range(const struct motion_sensor_t *s)
 static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
 {
 	int ret, normalized_rate = 0;
-	struct stprivate_data *data = LSM6DSO_GET_DATA(s);
+	struct stprivate_data *data = s->drv_data;
 	uint8_t ctrl_reg, reg_val = 0;
 
 	ctrl_reg = LSM6DSO_ODR_REG(s->type);
@@ -344,8 +328,7 @@ static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
 		}
 
 		if (normalized_rate < LSM6DSO_ODR_MIN_VAL ||
-		    normalized_rate > MIN(LSM6DSO_ODR_MAX_VAL,
-					  CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ))
+		    normalized_rate > LSM6DSO_ODR_MAX_VAL)
 			return EC_RES_INVALID_PARAM;
 	}
 
@@ -353,7 +336,7 @@ static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
 	ret = st_write_data_with_mask(s, ctrl_reg, LSM6DSO_ODR_MASK, reg_val);
 	if (ret == EC_SUCCESS) {
 		data->base.odr = normalized_rate;
-		if (IS_ENABLED(CONFIG_ACCEL_FIFO))
+		if (IS_ENABLED(ACCEL_LSM6DSO_INT_ENABLE))
 			accelgyro_config_fifo(s);
 	}
 
@@ -366,8 +349,8 @@ static int is_data_ready(const struct motion_sensor_t *s, int *ready)
 {
 	int ret, tmp;
 
-	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags,
-			   LSM6DSO_STATUS_REG, &tmp);
+	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, LSM6DSO_STATUS_REG,
+			   &tmp);
 	if (ret != EC_SUCCESS) {
 		CPRINTS("%s type:0x%X RS Error", s->name, s->type);
 
@@ -412,8 +395,8 @@ static int read(const struct motion_sensor_t *s, intv3_t v)
 	xyz_reg = get_xyz_reg(s->type);
 
 	/* Read data bytes starting at xyz_reg. */
-	ret = st_raw_read_n_noinc(s->port, s->i2c_spi_addr_flags,
-				  xyz_reg, raw, OUT_XYZ_SIZE);
+	ret = st_raw_read_n_noinc(s->port, s->i2c_spi_addr_flags, xyz_reg, raw,
+				  OUT_XYZ_SIZE);
 	if (ret != EC_SUCCESS)
 		return ret;
 
@@ -423,13 +406,13 @@ static int read(const struct motion_sensor_t *s, intv3_t v)
 	return EC_SUCCESS;
 }
 
-static int init(const struct motion_sensor_t *s)
+static int init(struct motion_sensor_t *s)
 {
 	int ret = 0, tmp;
-	struct stprivate_data *data = LSM6DSO_GET_DATA(s);
+	struct stprivate_data *data = s->drv_data;
 
-	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags,
-			   LSM6DSO_WHO_AM_I_REG, &tmp);
+	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, LSM6DSO_WHO_AM_I_REG,
+			   &tmp);
 	if (ret != EC_SUCCESS)
 		return EC_ERROR_UNKNOWN;
 
@@ -454,25 +437,24 @@ static int init(const struct motion_sensor_t *s)
 
 		/*
 		 * Output data not updated until have been read.
-		 * Prefer interrupt to be active low.
+		 * Require interrupt to be active low.
 		 */
-		ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-				    LSM6DSO_CTRL3_ADDR,
-				    LSM6DSO_BDU | LSM6DSO_IF_INC);
+		ret = st_raw_write8(
+			s->port, s->i2c_spi_addr_flags, LSM6DSO_CTRL3_ADDR,
+			LSM6DSO_BDU | LSM6DSO_IF_INC | LSM6DSO_H_L_ACTIVE);
 		if (ret != EC_SUCCESS)
 			goto err_unlock;
 
-		if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
+		if (IS_ENABLED(ACCEL_LSM6DSO_INT_ENABLE)) {
 			ret = fifo_disable(s);
 			if (ret != EC_SUCCESS)
 				goto err_unlock;
 		}
 
-#ifdef CONFIG_ACCEL_INTERRUPTS
-		ret = config_interrupt(s);
+		if (IS_ENABLED(ACCEL_LSM6DSO_INT_ENABLE))
+			ret = config_interrupt(s);
 		if (ret != EC_SUCCESS)
 			goto err_unlock;
-#endif /* CONFIG_ACCEL_INTERRUPTS */
 
 		mutex_unlock(s->mutex);
 	}
@@ -488,17 +470,33 @@ static int init(const struct motion_sensor_t *s)
 	return ret;
 }
 
+#ifdef CONFIG_BODY_DETECTION
+static int get_rms_noise(const struct motion_sensor_t *s)
+{
+	/*
+	 * RMS | Acceleration RMS noise in normal/low-power mode
+	 * FS = ±4 g | 2.0 mg(RMS)
+	 */
+	return 2000;
+}
+#endif
+
 const struct accelgyro_drv lsm6dso_drv = {
 	.init = init,
 	.read = read,
 	.set_range = set_range,
-	.get_range = get_range,
 	.get_resolution = st_get_resolution,
 	.set_data_rate = set_data_rate,
 	.get_data_rate = st_get_data_rate,
 	.set_offset = st_set_offset,
 	.get_offset = st_get_offset,
-#ifdef CONFIG_ACCEL_INTERRUPTS
+#ifdef ACCEL_LSM6DSO_INT_ENABLE
 	.irq_handler = irq_handler,
-#endif /* CONFIG_ACCEL_INTERRUPTS */
+#ifdef CONFIG_BODY_DETECTION
+	.get_rms_noise = get_rms_noise,
+#endif
+#ifdef CONFIG_GESTURE_HOST_DETECTION
+	.list_activities = st_list_activities,
+#endif
+#endif /* ACCEL_LSM6DSO_INT_ENABLE */
 };
diff --git a/driver/accelgyro_lsm6dso.h b/driver/accelgyro_lsm6dso.h
index a823fe7e61..ccc1fa0e84 100644
--- a/driver/accelgyro_lsm6dso.h
+++ b/driver/accelgyro_lsm6dso.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,92 +8,81 @@
 #ifndef __CROS_EC_ACCELGYRO_LSM6DSO_H
 #define __CROS_EC_ACCELGYRO_LSM6DSO_H
 
+#include "driver/accelgyro_lsm6dso_public.h"
 #include "stm_mems_common.h"
 
-/*
- * 7-bit address is 110101xb. Where 'x' is determined
- * by the voltage on the ADDR pin
- */
-#define LSM6DSO_ADDR0_FLAGS		0x6a
-#define LSM6DSO_ADDR1_FLAGS		0x6b
-
 /* Access to embedded sensor hub register bank */
-#define LSM6DSO_FUNC_CFG_ACC_ADDR	0x01
-#define LSM6DSO_FUNC_CFG_EN			0x80
+#define LSM6DSO_FUNC_CFG_ACC_ADDR 0x01
+#define LSM6DSO_FUNC_CFG_EN 0x80
 
 /* Who Am I */
-#define LSM6DSO_WHO_AM_I_REG		0x0f
-#define LSM6DSO_WHO_AM_I		0x6c
+#define LSM6DSO_WHO_AM_I_REG 0x0f
+#define LSM6DSO_WHO_AM_I 0x6c
 
 /* Common defines for Acc and Gyro sensors */
-#define LSM6DSO_EN_BIT				0x01
-#define LSM6DSO_DIS_BIT				0x00
+#define LSM6DSO_EN_BIT 0x01
+#define LSM6DSO_DIS_BIT 0x00
 
-#define LSM6DSO_GYRO_OUT_X_L_ADDR	0x22
-#define LSM6DSO_ACCEL_OUT_X_L_ADDR	0x28
+#define LSM6DSO_GYRO_OUT_X_L_ADDR 0x22
+#define LSM6DSO_ACCEL_OUT_X_L_ADDR 0x28
 
-#define LSM6DSO_CTRL1_ADDR		0x10
-#define LSM6DSO_CTRL2_ADDR		0x11
-#define LSM6DSO_CTRL3_ADDR		0x12
-#define LSM6DSO_SW_RESET			0x01
-#define LSM6DSO_IF_INC				0x04
-#define LSM6DSO_PP_OD				0x10
-#define LSM6DSO_H_L_ACTIVE			0x20
-#define LSM6DSO_BDU				0x40
+#define LSM6DSO_CTRL1_ADDR 0x10
+#define LSM6DSO_CTRL2_ADDR 0x11
+#define LSM6DSO_CTRL3_ADDR 0x12
+#define LSM6DSO_SW_RESET 0x01
+#define LSM6DSO_IF_INC 0x04
+#define LSM6DSO_PP_OD 0x10
+#define LSM6DSO_H_L_ACTIVE 0x20
+#define LSM6DSO_BDU 0x40
 
-#define LSM6DSO_CTRL4_ADDR		0x13
-#define LSM6DSO_INT2_ON_INT1_MASK		0x20
+#define LSM6DSO_CTRL4_ADDR 0x13
+#define LSM6DSO_INT2_ON_INT1_MASK 0x20
 
-#define LSM6DSO_CTRL5_ADDR		0x14
-#define LSM6DSO_CTRL6_ADDR		0x15
-#define LSM6DSO_CTRL7_ADDR		0x16
-#define LSM6DSO_CTRL8_ADDR		0x17
-#define LSM6DSO_CTRL9_ADDR		0x18
+#define LSM6DSO_CTRL5_ADDR 0x14
+#define LSM6DSO_CTRL6_ADDR 0x15
+#define LSM6DSO_CTRL7_ADDR 0x16
+#define LSM6DSO_CTRL8_ADDR 0x17
+#define LSM6DSO_CTRL9_ADDR 0x18
 
-#define LSM6DSO_CTRL10_ADDR		0x19
-#define LSM6DSO_TIMESTAMP_EN    		0x20
+#define LSM6DSO_CTRL10_ADDR 0x19
+#define LSM6DSO_TIMESTAMP_EN 0x20
 
-#define LSM6DSO_STATUS_REG		0x1e
+#define LSM6DSO_STATUS_REG 0x1e
 
 /* Output data rate registers and masks */
-#define LSM6DSO_ODR_REG(_sensor) \
-	(LSM6DSO_CTRL1_ADDR + (_sensor))
-#define LSM6DSO_ODR_MASK			0xf0
-
-/* Hardware FIFO size in byte */
-#define LSM6DSO_MAX_FIFO_SIZE		4096
-#define LSM6DSO_MAX_FIFO_LENGTH	(LSM6DSO_MAX_FIFO_SIZE / OUT_XYZ_SIZE)
+#define LSM6DSO_ODR_REG(_sensor) (LSM6DSO_CTRL1_ADDR + (_sensor))
+#define LSM6DSO_ODR_MASK 0xf0
 
 /* FIFO decimator registers and bitmask */
-#define LSM6DSO_FIFO_CTRL1_ADDR		0x07
-#define LSM6DSO_FIFO_CTRL2_ADDR		0x08
+#define LSM6DSO_FIFO_CTRL1_ADDR 0x07
+#define LSM6DSO_FIFO_CTRL2_ADDR 0x08
 
-#define LSM6DSO_FIFO_CTRL3_ADDR		0x09
-#define LSM6DSO_FIFO_ODR_XL_MASK		0x0f
-#define LSM6DSO_FIFO_ODR_G_MASK			0xf0
+#define LSM6DSO_FIFO_CTRL3_ADDR 0x09
+#define LSM6DSO_FIFO_ODR_XL_MASK 0x0f
+#define LSM6DSO_FIFO_ODR_G_MASK 0xf0
 
-#define LSM6DSO_FIFO_CTRL4_ADDR		0x0a
-#define LSM6DSO_FIFO_MODE_MASK			0x07
+#define LSM6DSO_FIFO_CTRL4_ADDR 0x0a
+#define LSM6DSO_FIFO_MODE_MASK 0x07
 
-#define LSM6DSO_INT1_CTRL		0x0d
-#define LSM6DSO_INT2_CTRL		0x0e
-#define LSM6DSO_INT_FIFO_TH			0x08
-#define LSM6DSO_INT_FIFO_OVR			0x10
-#define LSM6DSO_INT_FIFO_FULL			0x20
+#define LSM6DSO_INT1_CTRL 0x0d
+#define LSM6DSO_INT2_CTRL 0x0e
+#define LSM6DSO_INT_FIFO_TH 0x08
+#define LSM6DSO_INT_FIFO_OVR 0x10
+#define LSM6DSO_INT_FIFO_FULL 0x20
 
-#define LSM6DSO_FIFO_STS1_ADDR		0x3a
-#define LSM6DSO_FIFO_STS2_ADDR		0x3b
-#define LSM6DSO_FIFO_DIFF_MASK			0x07ff
-#define LSM6DSO_FIFO_FULL			0x2000
-#define LSM6DSO_FIFO_DATA_OVR			0x4000
-#define LSM6DSO_FIFO_WATERMARK			0x8000
+#define LSM6DSO_FIFO_STS1_ADDR 0x3a
+#define LSM6DSO_FIFO_STS2_ADDR 0x3b
+#define LSM6DSO_FIFO_DIFF_MASK 0x07ff
+#define LSM6DSO_FIFO_FULL 0x2000
+#define LSM6DSO_FIFO_DATA_OVR 0x4000
+#define LSM6DSO_FIFO_WATERMARK 0x8000
 
 /* Out FIFO data register */
-#define LSM6DSO_FIFO_DATA_ADDR_TAG	0x78
+#define LSM6DSO_FIFO_DATA_ADDR_TAG 0x78
 
 /* Registers value for supported FIFO mode */
-#define LSM6DSO_FIFO_MODE_BYPASS_VAL	0x00
-#define LSM6DSO_FIFO_MODE_CONTINUOUS_VAL	0x06
+#define LSM6DSO_FIFO_MODE_BYPASS_VAL 0x00
+#define LSM6DSO_FIFO_MODE_CONTINUOUS_VAL 0x06
 
 /* Define device available in FIFO pattern */
 enum lsm6dso_dev_fifo {
@@ -104,11 +93,8 @@ enum lsm6dso_dev_fifo {
 };
 
 /* Define FIFO data pattern, tag and len */
-#define LSM6DSO_SAMPLE_SIZE		6
-#define LSM6DSO_TS_SAMPLE_SIZE		4
-#define LSM6DSO_TAG_SIZE		1
-#define LSM6DSO_FIFO_SAMPLE_SIZE	LSM6DSO_SAMPLE_SIZE + LSM6DSO_TAG_SIZE
-#define LSM6DSO_MAX_FIFO_DEPTH		416
+#define LSM6DSO_TAG_SIZE 1
+#define LSM6DSO_FIFO_SAMPLE_SIZE (OUT_XYZ_SIZE + LSM6DSO_TAG_SIZE)
 
 enum lsm6dso_tag_fifo {
 	LSM6DSO_GYRO_TAG = 0x01,
@@ -120,40 +106,35 @@ struct lsm6dso_fstatus {
 	uint16_t pattern;
 };
 
-/* Absolute maximum rate for Acc and Gyro sensors */
-#define LSM6DSO_ODR_MIN_VAL		13000
-#define LSM6DSO_ODR_MAX_VAL \
-	MOTION_MAX_SENSOR_FREQUENCY(416000, 13000)
-
 /* ODR reg value from selected data rate in mHz */
 #define LSM6DSO_ODR_TO_REG(_odr) (__fls(_odr / LSM6DSO_ODR_MIN_VAL) + 1)
 
-#define LSM6DSO_FIFO_ODR_TO_REG(_s) \
+#define LSM6DSO_FIFO_ODR_MASK(_s)                                        \
 	(_s->type == MOTIONSENSE_TYPE_ACCEL ? LSM6DSO_FIFO_ODR_XL_MASK : \
-	 LSM6DSO_FIFO_ODR_G_MASK)
+					      LSM6DSO_FIFO_ODR_G_MASK)
 
 /* Normalized ODR values from selected data rate in mHz */
 #define LSM6DSO_REG_TO_ODR(_reg) (LSM6DSO_ODR_MIN_VAL << (_reg - 1))
 
 /* Full Scale ranges value and gain for Acc */
-#define LSM6DSO_FS_LIST_NUM		4
+#define LSM6DSO_FS_LIST_NUM 4
 
-#define LSM6DSO_ACCEL_FS_ADDR		0x10
-#define LSM6DSO_ACCEL_FS_MASK			0x0c
+#define LSM6DSO_ACCEL_FS_ADDR 0x10
+#define LSM6DSO_ACCEL_FS_MASK 0x0c
 
-#define LSM6DSO_ACCEL_FS_2G_VAL		0x00
-#define LSM6DSO_ACCEL_FS_4G_VAL		0x02
-#define LSM6DSO_ACCEL_FS_8G_VAL		0x03
-#define LSM6DSO_ACCEL_FS_16G_VAL	0x01
+#define LSM6DSO_ACCEL_FS_2G_VAL 0x00
+#define LSM6DSO_ACCEL_FS_4G_VAL 0x02
+#define LSM6DSO_ACCEL_FS_8G_VAL 0x03
+#define LSM6DSO_ACCEL_FS_16G_VAL 0x01
 
-#define LSM6DSO_ACCEL_FS_MAX_VAL	16
+#define LSM6DSO_ACCEL_FS_MAX_VAL 16
 
 /* Accel reg value from Full Scale range */
 static inline uint8_t lsm6dso_accel_fs_reg(int fs)
 {
 	uint8_t ret;
 
-	switch(fs) {
+	switch (fs) {
 	case 2:
 		ret = LSM6DSO_ACCEL_FS_2G_VAL;
 		break;
@@ -172,8 +153,8 @@ static inline uint8_t lsm6dso_accel_fs_reg(int fs)
 #define LSM6DSO_ACCEL_NORMALIZE_FS(_fs) (1 << __fls(_fs))
 
 /* Full Scale range value and gain for Gyro */
-#define LSM6DSO_GYRO_FS_ADDR		0x11
-#define LSM6DSO_GYRO_FS_MASK			0x0c
+#define LSM6DSO_GYRO_FS_ADDR 0x11
+#define LSM6DSO_GYRO_FS_MASK 0x0c
 
 /* Minimal Gyro range in mDPS */
 #define LSM6DSO_GYRO_FS_MIN_VAL_MDPS ((8750 << 15) / 1000)
@@ -188,8 +169,8 @@ static inline uint8_t lsm6dso_accel_fs_reg(int fs)
 	((LSM6DSO_GYRO_FS_MIN_VAL_MDPS << (_reg)) / 1000)
 
 /* FS register address/mask for Acc/Gyro sensors */
-#define LSM6DSO_RANGE_REG(_sensor)  	(LSM6DSO_ACCEL_FS_ADDR + (_sensor))
-#define LSM6DSO_RANGE_MASK  			0x0c
+#define LSM6DSO_RANGE_REG(_sensor) (LSM6DSO_ACCEL_FS_ADDR + (_sensor))
+#define LSM6DSO_RANGE_MASK 0x0c
 
 /* Status register bit for Acc/Gyro data ready */
 enum lsm6dso_status {
@@ -199,11 +180,11 @@ enum lsm6dso_status {
 };
 
 /* Status register bitmask for Acc/Gyro data ready */
-#define LSM6DSO_STS_XLDA_MASK			0x01
-#define LSM6DSO_STS_GDA_MASK			0x02
+#define LSM6DSO_STS_XLDA_MASK 0x01
+#define LSM6DSO_STS_GDA_MASK 0x02
 
 /* Sensor resolution in number of bits: fixed 16 bit */
-#define LSM6DSO_RESOLUTION      	16
+#define LSM6DSO_RESOLUTION 16
 
 /* Aggregate private data for all supported sensor (Acc, Gyro) */
 struct lsm6dso_data {
@@ -218,14 +199,28 @@ struct lsm6dso_data {
  */
 #define LSM6DSO_DISCARD_SAMPLES 3
 
-#define LSM6DSO_GET_DATA(_s) ((struct stprivate_data *)((_s)->drv_data))
-
 /* Macro to initialize motion_sensors structure */
-#define LSM6DSO_ST_DATA(g, type) (&(&(g))->st_data[(type)])
-#define LSM6DSO_MAIN_SENSOR(_s) ((_s) - (_s)->type)
+#define LSM6DSO_ST_DATA(g, type) (&((g).st_data[type]))
 
 extern const struct accelgyro_drv lsm6dso_drv;
 
 void lsm6dso_interrupt(enum gpio_signal signal);
 
+#if defined(CONFIG_ZEPHYR)
+#if DT_NODE_EXISTS(DT_ALIAS(lsm6dso_int))
+/* Get the motion sensor ID of the LSM6DSO sensor that generates the
+ * interrupt. The interrupt is converted to the event and transferred to
+ * motion sense task that actually handles the interrupt.
+ *
+ * Here we use an alias (lsm6dso_int) to get the motion sensor ID. This alias
+ * MUST be defined for this driver to work.
+ * aliases {
+ *   lsm6dso-int = &lid_accel;
+ * };
+ */
+#define CONFIG_ACCEL_LSM6DSO_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(SENSOR_ID(DT_ALIAS(lsm6dso_int)))
+#endif
+#endif /* CONFIG_ZEPHYR */
+
 #endif /* __CROS_EC_ACCELGYRO_LSM6DSO_H */
diff --git a/driver/als_al3010.c b/driver/als_al3010.c
index b129dc2f57..b3afe31790 100644
--- a/driver/als_al3010.c
+++ b/driver/als_al3010.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -15,13 +15,13 @@ int al3010_init(void)
 {
 	int ret;
 
-	ret = i2c_write8(I2C_PORT_ALS, AL3010_I2C_ADDR,
-			 AL3010_REG_CONFIG, AL3010_GAIN << 4);
+	ret = i2c_write8(I2C_PORT_ALS, AL3010_I2C_ADDR, AL3010_REG_CONFIG,
+			 AL3010_GAIN << 4);
 	if (ret)
 		return ret;
 
-	return i2c_write8(I2C_PORT_ALS, AL3010_I2C_ADDR,
-			  AL3010_REG_SYSTEM, AL3010_ENABLE);
+	return i2c_write8(I2C_PORT_ALS, AL3010_I2C_ADDR, AL3010_REG_SYSTEM,
+			  AL3010_ENABLE);
 }
 
 /**
@@ -33,8 +33,8 @@ int al3010_read_lux(int *lux, int af)
 	int val;
 	long long val64;
 
-	ret = i2c_read16(I2C_PORT_ALS, AL3010_I2C_ADDR,
-			 AL3010_REG_DATA_LOW, &val);
+	ret = i2c_read16(I2C_PORT_ALS, AL3010_I2C_ADDR, AL3010_REG_DATA_LOW,
+			 &val);
 
 	if (ret)
 		return ret;
diff --git a/driver/als_al3010.h b/driver/als_al3010.h
index 288e255990..6d8db9e7d9 100644
--- a/driver/als_al3010.h
+++ b/driver/als_al3010.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -9,32 +9,32 @@
 #define __CROS_EC_ALS_AL3010_H
 
 /* I2C interface */
-#define AL3010_I2C_ADDR1_FLAGS		0x1C
-#define AL3010_I2C_ADDR2_FLAGS		0x1D
-#define AL3010_I2C_ADDR3_FLAGS		0x1E
+#define AL3010_I2C_ADDR1_FLAGS 0x1C
+#define AL3010_I2C_ADDR2_FLAGS 0x1D
+#define AL3010_I2C_ADDR3_FLAGS 0x1E
 
 /* AL3010 registers */
-#define AL3010_REG_SYSTEM		0x00
-#define AL3010_REG_INT_STATUS		0x01
-#define AL3010_REG_CONFIG		0x10
-#define AL3010_REG_DATA_LOW		0x0C
+#define AL3010_REG_SYSTEM 0x00
+#define AL3010_REG_INT_STATUS 0x01
+#define AL3010_REG_CONFIG 0x10
+#define AL3010_REG_DATA_LOW 0x0C
 
-#define AL3010_ENABLE	0x01
+#define AL3010_ENABLE 0x01
 #define AL3010_GAIN_SELECT 3
 
-#define	AL3010_GAIN_1 0 /* 77806 lx */
-#define	AL3010_GAIN_2 1 /* 19452 lx  */
-#define	AL3010_GAIN_3 2 /* 4863  lx  */
-#define	AL3010_GAIN_4 3 /* 1216  lx  */
-#define AL3010_GAIN	CONCAT2(AL3010_GAIN_, AL3010_GAIN_SELECT)
+#define AL3010_GAIN_1 0 /* 77806 lx */
+#define AL3010_GAIN_2 1 /* 19452 lx  */
+#define AL3010_GAIN_3 2 /* 4863  lx  */
+#define AL3010_GAIN_4 3 /* 1216  lx  */
+#define AL3010_GAIN CONCAT2(AL3010_GAIN_, AL3010_GAIN_SELECT)
 
-#define AL3010_GAIN_SCALE_1 11872	/* 1.1872 lux/count */
-#define AL3010_GAIN_SCALE_2 2968	/* 0.2968 lux/count */
-#define AL3010_GAIN_SCALE_3 742		/* 0.0742 lux/count */
-#define AL3010_GAIN_SCALE_4 186		/* 0.0186 lux/count */
+#define AL3010_GAIN_SCALE_1 11872 /* 1.1872 lux/count */
+#define AL3010_GAIN_SCALE_2 2968 /* 0.2968 lux/count */
+#define AL3010_GAIN_SCALE_3 742 /* 0.0742 lux/count */
+#define AL3010_GAIN_SCALE_4 186 /* 0.0186 lux/count */
 #define AL3010_GAIN_SCALE CONCAT2(AL3010_GAIN_SCALE_, AL3010_GAIN_SELECT)
 
 int al3010_init(void);
 int al3010_read_lux(int *lux, int af);
 
-#endif	/* __CROS_EC_ALS_AL3010_H */
+#endif /* __CROS_EC_ALS_AL3010_H */
diff --git a/driver/als_bh1730.c b/driver/als_bh1730.c
index 872fdaa012..3e0684dbdb 100644
--- a/driver/als_bh1730.c
+++ b/driver/als_bh1730.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,8 +11,8 @@
 #include "driver/als_bh1730.h"
 #include "i2c.h"
 
-#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_MOTION_SENSE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_MOTION_SENSE, format, ##args)
 
 /**
  * Convert BH1730 data0, data1 to lux
@@ -32,16 +32,16 @@ static int bh1730_convert_to_lux(uint32_t data0_1)
 	else
 		d_temp = d1_1k / data0;
 
-	if(d_temp < BH1730_LUXTH1_1K) {
+	if (d_temp < BH1730_LUXTH1_1K) {
 		d0_1k = BH1730_LUXTH1_D0_1K * data0;
 		d1_1k = BH1730_LUXTH1_D1_1K * data1;
-	} else if(d_temp < BH1730_LUXTH2_1K) {
+	} else if (d_temp < BH1730_LUXTH2_1K) {
 		d0_1k = BH1730_LUXTH2_D0_1K * data0;
 		d1_1k = BH1730_LUXTH2_D1_1K * data1;
-	} else if(d_temp < BH1730_LUXTH3_1K) {
+	} else if (d_temp < BH1730_LUXTH3_1K) {
 		d0_1k = BH1730_LUXTH3_D0_1K * data0;
 		d1_1k = BH1730_LUXTH3_D1_1K * data1;
-	} else if(d_temp < BH1730_LUXTH4_1K) {
+	} else if (d_temp < BH1730_LUXTH4_1K) {
 		d0_1k = BH1730_LUXTH4_D0_1K * data0;
 		d1_1k = BH1730_LUXTH4_D1_1K * data1;
 	} else
@@ -64,8 +64,8 @@ static int bh1730_read_lux(const struct motion_sensor_t *s, intv3_t v)
 	int data0_1;
 
 	/* read data0 and data1 from sensor */
-	ret = i2c_read32(s->port, s->i2c_spi_addr_flags,
-			 BH1730_DATA0LOW, &data0_1);
+	ret = i2c_read32(s->port, s->i2c_spi_addr_flags, BH1730_DATA0LOW,
+			 &data0_1);
 	if (ret != EC_SUCCESS) {
 		CPRINTF("bh1730_read_lux - fail %d\n", ret);
 		return ret;
@@ -80,25 +80,26 @@ static int bh1730_read_lux(const struct motion_sensor_t *s, intv3_t v)
 	 * Return an error when nothing change to prevent filling the
 	 * fifo with useless data.
 	 */
-	if (v[0] == drv_data->last_value)
+	if (v[0] == drv_data->last_value) {
 		return EC_ERROR_UNCHANGED;
-	else
+	} else {
+		drv_data->last_value = v[0];
 		return EC_SUCCESS;
+	}
 }
 
-static int bh1730_set_range(const struct motion_sensor_t *s, int range,
-			     int rnd)
+static int bh1730_set_range(struct motion_sensor_t *s, int range, int rnd)
 {
-	return EC_SUCCESS;
-}
+	/* Range is fixed by hardware */
+	if (range != s->default_range)
+		return EC_ERROR_INVAL;
 
-static int bh1730_get_range(const struct motion_sensor_t *s)
-{
-	return 1;
+	s->current_range = range;
+	return EC_SUCCESS;
 }
 
-static int bh1730_set_data_rate(const struct motion_sensor_t *s,
-				int rate, int roundup)
+static int bh1730_set_data_rate(const struct motion_sensor_t *s, int rate,
+				int roundup)
 {
 	struct bh1730_drv_data_t *drv_data = BH1730_GET_DATA(s);
 
@@ -116,15 +117,13 @@ static int bh1730_get_data_rate(const struct motion_sensor_t *s)
 }
 
 static int bh1730_set_offset(const struct motion_sensor_t *s,
-			const int16_t *offset,
-			int16_t    temp)
+			     const int16_t *offset, int16_t temp)
 {
 	return EC_SUCCESS;
 }
 
-static int bh1730_get_offset(const struct motion_sensor_t *s,
-			int16_t   *offset,
-			int16_t    *temp)
+static int bh1730_get_offset(const struct motion_sensor_t *s, int16_t *offset,
+			     int16_t *temp)
 {
 	*offset = 0;
 
@@ -134,15 +133,14 @@ static int bh1730_get_offset(const struct motion_sensor_t *s,
 /**
  * Initialise BH1730 Ambient light sensor.
  */
-static int bh1730_init(const struct motion_sensor_t *s)
+static int bh1730_init(struct motion_sensor_t *s)
 {
 	int ret;
 
 	/* power and measurement bit high */
-	ret = i2c_write8(s->port, s->i2c_spi_addr_flags,
-			BH1730_CONTROL,
-			BH1730_CONTROL_POWER_ENABLE
-			      | BH1730_CONTROL_ADC_EN_ENABLE);
+	ret = i2c_write8(s->port, s->i2c_spi_addr_flags, BH1730_CONTROL,
+			 BH1730_CONTROL_POWER_ENABLE |
+				 BH1730_CONTROL_ADC_EN_ENABLE);
 
 	if (ret != EC_SUCCESS) {
 		CPRINTF("bh1730_init_sensor - enable fail %d\n", ret);
@@ -150,15 +148,15 @@ static int bh1730_init(const struct motion_sensor_t *s)
 	}
 
 	/* set timing */
-	ret = i2c_write8(s->port, s->i2c_spi_addr_flags,
-			 BH1730_TIMING, BH1730_CONF_ITIME);
+	ret = i2c_write8(s->port, s->i2c_spi_addr_flags, BH1730_TIMING,
+			 BH1730_CONF_ITIME);
 	if (ret != EC_SUCCESS) {
 		CPRINTF("bh1730_init_sensor - time fail %d\n", ret);
 		return ret;
 	}
 	/* set ADC gain */
-	ret = i2c_write8(s->port, s->i2c_spi_addr_flags,
-			 BH1730_GAIN, BH1730_CONF_GAIN);
+	ret = i2c_write8(s->port, s->i2c_spi_addr_flags, BH1730_GAIN,
+			 BH1730_CONF_GAIN);
 
 	if (ret != EC_SUCCESS) {
 		CPRINTF("bh1730_init_sensor - gain fail %d\n", ret);
@@ -172,10 +170,8 @@ const struct accelgyro_drv bh1730_drv = {
 	.init = bh1730_init,
 	.read = bh1730_read_lux,
 	.set_range = bh1730_set_range,
-	.get_range = bh1730_get_range,
 	.set_offset = bh1730_set_offset,
 	.get_offset = bh1730_get_offset,
 	.set_data_rate = bh1730_set_data_rate,
 	.get_data_rate = bh1730_get_data_rate,
 };
-
diff --git a/driver/als_bh1730.h b/driver/als_bh1730.h
index d0205033e4..ab5a34b92b 100644
--- a/driver/als_bh1730.h
+++ b/driver/als_bh1730.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -9,42 +9,42 @@
 #define __CROS_EC_ALS_BH1730_H
 
 /* I2C interface */
-#define BH1730_I2C_ADDR_FLAGS	0x29
+#define BH1730_I2C_ADDR_FLAGS 0x29
 
 /* BH1730 registers */
-#define BH1730_CONTROL		0x80
-#define BH1730_TIMING		0x81
-#define BH1730_INTERRUPT	0x82
-#define BH1730_THLLOW		0x83
-#define BH1730_THLHIGH		0x84
-#define BH1730_THHLOW		0x85
-#define BH1730_THHHIGH		0x86
-#define BH1730_GAIN		0x87
-#define BH1730_OPART_ID		0x92
-#define BH1730_DATA0LOW		0x94
-#define BH1730_DATA0HIGH	0x95
-#define BH1730_DATA1LOW		0x96
-#define BH1730_DATA1HIGH	0x97
+#define BH1730_CONTROL 0x80
+#define BH1730_TIMING 0x81
+#define BH1730_INTERRUPT 0x82
+#define BH1730_THLLOW 0x83
+#define BH1730_THLHIGH 0x84
+#define BH1730_THHLOW 0x85
+#define BH1730_THHHIGH 0x86
+#define BH1730_GAIN 0x87
+#define BH1730_OPART_ID 0x92
+#define BH1730_DATA0LOW 0x94
+#define BH1730_DATA0HIGH 0x95
+#define BH1730_DATA1LOW 0x96
+#define BH1730_DATA1HIGH 0x97
 /* Software reset */
-#define BH1730_RESET		0xE4
+#define BH1730_RESET 0xE4
 
 /* Registers bits */
-#define BH1730_CONTROL_ADC_INTR_INACTIVE	(0x00 << 5)
-#define BH1730_CONTROL_ADC_INTR_ACTIVE		(0x01 << 5)
-#define BH1730_CONTROL_ADC_VALID		(0x01 << 4)
-#define BH1730_CONTROL_ONE_TIME_CONTINOUS	(0x00 << 3)
-#define BH1730_CONTROL_ONE_TIME_ONETIME		(0x01 << 3)
-#define BH1730_CONTROL_DATA_SEL_TYPE0_AND_1	(0x00 << 2)
-#define BH1730_CONTROL_DATA_SEL_TYPE0		(0x01 << 2)
-#define BH1730_CONTROL_ADC_EN_DISABLE		(0x00 << 1)
-#define BH1730_CONTROL_ADC_EN_ENABLE		(0x01 << 1)
-#define BH1730_CONTROL_POWER_DISABLE		(0x00 << 0)
-#define BH1730_CONTROL_POWER_ENABLE		(0x01 << 0)
+#define BH1730_CONTROL_ADC_INTR_INACTIVE (0x00 << 5)
+#define BH1730_CONTROL_ADC_INTR_ACTIVE (0x01 << 5)
+#define BH1730_CONTROL_ADC_VALID (0x01 << 4)
+#define BH1730_CONTROL_ONE_TIME_CONTINOUS (0x00 << 3)
+#define BH1730_CONTROL_ONE_TIME_ONETIME (0x01 << 3)
+#define BH1730_CONTROL_DATA_SEL_TYPE0_AND_1 (0x00 << 2)
+#define BH1730_CONTROL_DATA_SEL_TYPE0 (0x01 << 2)
+#define BH1730_CONTROL_ADC_EN_DISABLE (0x00 << 1)
+#define BH1730_CONTROL_ADC_EN_ENABLE (0x01 << 1)
+#define BH1730_CONTROL_POWER_DISABLE (0x00 << 0)
+#define BH1730_CONTROL_POWER_ENABLE (0x01 << 0)
 
-#define BH1730_GAIN_GAIN_X1_GAIN		(0x00 << 0)
-#define BH1730_GAIN_GAIN_X2_GAIN		(0x01 << 0)
-#define BH1730_GAIN_GAIN_X64_GAIN		(0x02 << 0)
-#define BH1730_GAIN_GAIN_X128_GAIN		(0x03 << 0)
+#define BH1730_GAIN_GAIN_X1_GAIN (0x00 << 0)
+#define BH1730_GAIN_GAIN_X2_GAIN (0x01 << 0)
+#define BH1730_GAIN_GAIN_X64_GAIN (0x02 << 0)
+#define BH1730_GAIN_GAIN_X128_GAIN (0x03 << 0)
 
 /* Sensor configuration */
 /* Select Gain */
@@ -54,31 +54,37 @@
 /* Select Itime, 0xDA is 102.6ms = 38*2.7ms */
 #define BH1730_CONF_ITIME 0xDA
 #define ITIME_MS_X_10 ((256 - BH1730_CONF_ITIME) * 27)
-#define ITIME_MS_X_1K (ITIME_MS_X_10*100)
+#define ITIME_MS_X_1K (ITIME_MS_X_10 * 100)
 
 /* default Itime is about 10Hz */
-#define BH1730_10000_MHZ (10*1000)
+#define BH1730_10000_MHZ (10 * 1000)
+#define BH1730_MAX_FREQ BH1730_10000_MHZ
+/*
+ * 10Hz is too fast for the AP: allow the AP query data less often, the EC will
+ * downsample.
+ */
+#define BH1730_MIN_FREQ (BH1730_MAX_FREQ / 100)
 
 /*
  * Use default lux calculation formula parameters if board specific
  * parameters are not defined.
  */
 #ifndef CONFIG_ALS_BH1730_LUXTH_PARAMS
-#define BH1730_LUXTH1_1K                260
-#define BH1730_LUXTH1_D0_1K             1290
-#define BH1730_LUXTH1_D1_1K             2733
-#define BH1730_LUXTH2_1K                550
-#define BH1730_LUXTH2_D0_1K             797
-#define BH1730_LUXTH2_D1_1K             859
-#define BH1730_LUXTH3_1K                1090
-#define BH1730_LUXTH3_D0_1K             510
-#define BH1730_LUXTH3_D1_1K             345
-#define BH1730_LUXTH4_1K                2130
-#define BH1730_LUXTH4_D0_1K             276
-#define BH1730_LUXTH4_D1_1K             130
+#define BH1730_LUXTH1_1K 260
+#define BH1730_LUXTH1_D0_1K 1290
+#define BH1730_LUXTH1_D1_1K 2733
+#define BH1730_LUXTH2_1K 550
+#define BH1730_LUXTH2_D0_1K 797
+#define BH1730_LUXTH2_D1_1K 859
+#define BH1730_LUXTH3_1K 1090
+#define BH1730_LUXTH3_D0_1K 510
+#define BH1730_LUXTH3_D1_1K 345
+#define BH1730_LUXTH4_1K 2130
+#define BH1730_LUXTH4_D0_1K 276
+#define BH1730_LUXTH4_D1_1K 130
 #endif
 
-#define BH1730_GET_DATA(_s)    ((struct bh1730_drv_data_t *)(_s)->drv_data)
+#define BH1730_GET_DATA(_s) ((struct bh1730_drv_data_t *)(_s)->drv_data)
 
 struct bh1730_drv_data_t {
 	int rate;
@@ -87,5 +93,4 @@ struct bh1730_drv_data_t {
 
 extern const struct accelgyro_drv bh1730_drv;
 
-#endif	/* __CROS_EC_ALS_BH1730_H */
-
+#endif /* __CROS_EC_ALS_BH1730_H */
diff --git a/driver/als_cm32183.c b/driver/als_cm32183.c
new file mode 100644
index 0000000000..a2ee9f365e
--- /dev/null
+++ b/driver/als_cm32183.c
@@ -0,0 +1,142 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * CAPELLA CM32183 light sensor driver
+ */
+
+#include "accelgyro.h"
+#include "common.h"
+#include "driver/als_cm32183.h"
+#include "i2c.h"
+#include "math_util.h"
+
+struct cm32183_drv_data {
+	int rate;
+	int last_value;
+	/* the coefficient is scale.uscale */
+	int16_t scale;
+	uint16_t uscale;
+	int16_t offset;
+};
+
+#define CM32183_GET_DATA(_s) ((struct cm32183_drv_data *)(_s)->drv_data)
+
+/*
+ * Read CM32183 light sensor data.
+ */
+static int cm32183_read_lux(int *lux)
+{
+	int ret;
+	int data;
+
+	ret = i2c_read16(I2C_PORT_SENSOR, CM32183_I2C_ADDR,
+			 CM32183_REG_ALS_RESULT, &data);
+
+	if (ret)
+		return ret;
+
+	/*
+	 * lux = data * 0.016
+	 */
+	*lux = (data * 16) / 1000;
+
+	return EC_SUCCESS;
+}
+
+/*
+ * Read data from CM32183 light sensor, and transfer unit into lux.
+ */
+static int cm32183_read(const struct motion_sensor_t *s, intv3_t v)
+{
+	struct cm32183_drv_data *drv_data = CM32183_GET_DATA(s);
+	int ret;
+	int lux_data;
+
+	ret = cm32183_read_lux(&lux_data);
+
+	if (ret)
+		return ret;
+
+	lux_data += drv_data->offset;
+	lux_data = lux_data * drv_data->scale +
+		   lux_data * drv_data->uscale / 10000;
+
+	v[0] = lux_data;
+	v[1] = 0;
+	v[2] = 0;
+
+	/*
+	 * Return an error when nothing change to prevent filling the
+	 * fifo with useless data.
+	 */
+	if (v[0] == drv_data->last_value)
+		return EC_ERROR_UNCHANGED;
+
+	drv_data->last_value = v[0];
+	return EC_SUCCESS;
+}
+
+static int cm32183_set_range(struct motion_sensor_t *s, int range, int rnd)
+{
+	return EC_SUCCESS;
+}
+
+static int cm32183_set_data_rate(const struct motion_sensor_t *s, int rate,
+				 int roundup)
+{
+	CM32183_GET_DATA(s)->rate = rate;
+	return EC_SUCCESS;
+}
+
+static int cm32183_get_data_rate(const struct motion_sensor_t *s)
+{
+	return CM32183_GET_DATA(s)->rate;
+}
+
+static int cm32183_set_offset(const struct motion_sensor_t *s,
+			      const int16_t *offset, int16_t temp)
+{
+	/* TODO: check calibration method */
+	return EC_SUCCESS;
+}
+
+static int cm32183_get_offset(const struct motion_sensor_t *s, int16_t *offset,
+			      int16_t *temp)
+{
+	*offset = CM32183_GET_DATA(s)->offset;
+	return EC_SUCCESS;
+}
+
+/**
+ * Initialise CM32183 light sensor.
+ */
+static int cm32183_init(struct motion_sensor_t *s)
+{
+	int ret;
+	int data;
+
+	ret = i2c_write16(s->port, s->i2c_spi_addr_flags, CM32183_REG_CONFIGURE,
+			  CM32183_REG_CONFIGURE_CH_EN);
+
+	if (ret)
+		return ret;
+
+	ret = i2c_read16(s->port, s->i2c_spi_addr_flags, CM32183_REG_ALS_RESULT,
+			 &data);
+
+	if (ret)
+		return ret;
+
+	return sensor_init_done(s);
+}
+
+const struct accelgyro_drv cm32183_drv = {
+	.init = cm32183_init,
+	.read = cm32183_read,
+	.set_range = cm32183_set_range,
+	.set_offset = cm32183_set_offset,
+	.get_offset = cm32183_get_offset,
+	.set_data_rate = cm32183_set_data_rate,
+	.get_data_rate = cm32183_get_data_rate,
+};
diff --git a/driver/als_cm32183.h b/driver/als_cm32183.h
new file mode 100644
index 0000000000..f0dbaf3c03
--- /dev/null
+++ b/driver/als_cm32183.h
@@ -0,0 +1,103 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * CAPELLA CM32183 light sensor driver
+ */
+
+#ifndef __CROS_EC_ALS_CM32183_H
+#define __CROS_EC_ALS_CM32183_H
+
+/* I2C interface */
+#define CM32183_I2C_ADDR 0x29
+
+/* CM32183 registers */
+#define CM32183_REG_CONFIGURE 0x00
+
+#define CM32183_REG_CONFIGURE_CH_EN 0x0004
+
+/* ALS Sensitivity_mode (BIT 12:11) */
+#define CM32183_REG_CONFIGURE_ALS_SENSITIVITY_MASK GENMASK(12, 11)
+#define CM32183_REG_CONFIGURE_ALS_SENSITIVITY_SHIFT 11
+#define CM32183_REG_CONFIGURE_ALS_SENSITIVITY_1 0
+#define CM32183_REG_CONFIGURE_ALS_SENSITIVITY_2 1
+#define CM32183_REG_CONFIGURE_ALS_SENSITIVITY_1_DIV_8 2
+#define CM32183_REG_CONFIGURE_ALS_SENSITIVITY_1_DIV_4 3
+
+/*
+ * Gain mode
+ * 0 Gain*1
+ * 1 Gain*2  (bit 10)
+ */
+#define CM32183_REG_CONFIGURE_GAIN BIT(10)
+
+/*
+ * ALS integration time setting which represents how long
+ * ALS can update the readout value (BIT 9:6)
+ * BIT 9:6     function
+ *  0000         100ms
+ *  0001         200ms
+ *  0010         400ms
+ *  0011         800ms
+ */
+#define CM32183_REG_CONFIGURE_ALS_INTEGRATION_MASK GENMASK(9, 6)
+#define CM32183_REG_CONFIGURE_ALS_INTEGRATION_SHIFT 6
+#define CM32183_REG_CONFIGURE_ALS_INTEGRATION_SET100MS 0
+#define CM32183_REG_CONFIGURE_ALS_INTEGRATION_SET200MS 1
+#define CM32183_REG_CONFIGURE_ALS_INTEGRATION_SET400MS 2
+#define CM32183_REG_CONFIGURE_ALS_INTEGRATION_SET800MS 3
+
+/*
+ * ALS interrupt persistence setting.The interrupt pin is
+ * triggered while sensor reading is out of threshold windows
+ * after consecutive number of measurement cycle. (BIT 5:4)
+ *  BIT 5:4      measurement cycle
+ *    00                 1
+ *    01                 2
+ *    10                 4
+ *    11                 8
+ */
+#define CM32183_REG_CONFIGURE_MEASUREMENT_MASK GENMASK(5, 4)
+#define CM32183_REG_CONFIGURE_MEASUREMENT_SHIFT 4
+#define CM32183_REG_CONFIGURE_MEASUREMENT_CYCLE_1 0
+#define CM32183_REG_CONFIGURE_MEASUREMENT_CYCLE_2 1
+#define CM32183_REG_CONFIGURE_MEASUREMENT_CYCLE_4 2
+#define CM32183_REG_CONFIGURE_MEASUREMENT_CYCLE_8 3
+
+/*
+ * channel selection of interrupt (BIT 3)
+ * 0   ALS CH interrupt
+ * 1   White CH interrupt
+ */
+#define CM32183_REG_CONFIGURE_CHANNEL_SELECTION BIT(3)
+
+/*
+ * Channel enable (BIT 2)
+ *  0   ALS CH enable only
+ *  1   ALS & White CH enable
+ */
+#define CM32183_REG_CONFIGURE_CHANNEL_ENABLE BIT(2)
+
+/* enable/disable interrupt function (BIT 1) */
+#define CM32183_REG_CONFIGURE_INTERRUPT_ENABLE BIT(1)
+
+/*
+ * how to power on and shutdown sensor (BIT 0)
+ * 0   power on
+ * 1   shutdown
+ */
+#define CM32183_REG_CONFIGURE_POWER BIT(0)
+
+#define CM32183_REG_INT_HSB 0x01
+#define CM32183_REG_INT_LSB 0x02
+#define CM32183_REG_ALS_RESULT 0x04
+#define CM32183_REG_WHITE_RESULT 0x05
+
+#define CM32183_REG_TRIGGER 0x06
+
+#define CM32183_REG_TRIGGER_LOW_THRESHOLD BIT(15)
+#define CM32183_REG_TRIGGER_HIGH_THRESHOLD BIT(14)
+
+extern const struct accelgyro_drv cm32183_drv;
+
+#endif /* __CROS_EC_ALS_CM32183_H */
diff --git a/driver/als_isl29035.c b/driver/als_isl29035.c
index db77a19f09..3391a25e01 100644
--- a/driver/als_isl29035.c
+++ b/driver/als_isl29035.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -9,16 +9,16 @@
 #include "i2c.h"
 
 /* I2C interface */
-#define ILS29035_I2C_ADDR_FLAGS	0x44
-#define ILS29035_REG_COMMAND_I  0
+#define ILS29035_I2C_ADDR_FLAGS 0x44
+#define ILS29035_REG_COMMAND_I 0
 #define ILS29035_REG_COMMAND_II 1
-#define ILS29035_REG_DATA_LSB   2
-#define ILS29035_REG_DATA_MSB   3
+#define ILS29035_REG_DATA_LSB 2
+#define ILS29035_REG_DATA_MSB 3
 #define ILS29035_REG_INT_LT_LSB 4
 #define ILS29035_REG_INT_LT_MSB 5
 #define ILS29035_REG_INT_HT_LSB 6
 #define ILS29035_REG_INT_HT_MSB 7
-#define ILS29035_REG_ID         15
+#define ILS29035_REG_ID 15
 
 int isl29035_init(void)
 {
diff --git a/driver/als_isl29035.h b/driver/als_isl29035.h
index 153ba148f9..db67837375 100644
--- a/driver/als_isl29035.h
+++ b/driver/als_isl29035.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,4 +11,4 @@
 int isl29035_init(void);
 int isl29035_read_lux(int *lux, int af);
 
-#endif	/* __CROS_EC_ALS_ISL29035_H */
+#endif /* __CROS_EC_ALS_ISL29035_H */
diff --git a/driver/als_opt3001.c b/driver/als_opt3001.c
index 8f1e2bc775..6939e330dd 100644
--- a/driver/als_opt3001.c
+++ b/driver/als_opt3001.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -17,11 +17,10 @@ static int opt3001_i2c_read(const int reg, int *data_ptr)
 {
 	int ret;
 
-	ret = i2c_read16(I2C_PORT_ALS, OPT3001_I2C_ADDR_FLAGS,
-			 reg, data_ptr);
+	ret = i2c_read16(I2C_PORT_ALS, OPT3001_I2C_ADDR_FLAGS, reg, data_ptr);
 	if (!ret)
 		*data_ptr = ((*data_ptr << 8) & 0xFF00) |
-				((*data_ptr >> 8) & 0x00FF);
+			    ((*data_ptr >> 8) & 0x00FF);
 
 	return ret;
 }
@@ -32,8 +31,7 @@ static int opt3001_i2c_read(const int reg, int *data_ptr)
 static int opt3001_i2c_write(const int reg, int data)
 {
 	data = ((data << 8) & 0xFF00) | ((data >> 8) & 0x00FF);
-	return i2c_write16(I2C_PORT_ALS, OPT3001_I2C_ADDR_FLAGS,
-			   reg, data);
+	return i2c_write16(I2C_PORT_ALS, OPT3001_I2C_ADDR_FLAGS, reg, data);
 }
 
 /**
@@ -102,25 +100,23 @@ struct i2c_stress_test_dev opt3001_i2c_stress_test_dev = {
 	.i2c_read_dev = &opt3001_i2c_read,
 	.i2c_write_dev = &opt3001_i2c_write,
 };
-#endif  /* CONFIG_CMD_I2C_STRESS_TEST_ALS */
-#else  /* HAS_TASK_ALS */
+#endif /* CONFIG_CMD_I2C_STRESS_TEST_ALS */
+#else /* HAS_TASK_ALS */
 #include "accelgyro.h"
 #include "math_util.h"
 
 /**
  *  Read register from OPT3001 light sensor.
  */
-static int opt3001_i2c_read(const int port,
-			    const uint16_t i2c_addr_flags,
+static int opt3001_i2c_read(const int port, const uint16_t i2c_addr_flags,
 			    const int reg, int *data_ptr)
 {
 	int ret;
 
-	ret = i2c_read16(port, i2c_addr_flags,
-			 reg, data_ptr);
+	ret = i2c_read16(port, i2c_addr_flags, reg, data_ptr);
 	if (!ret)
 		*data_ptr = ((*data_ptr << 8) & 0xFF00) |
-				((*data_ptr >> 8) & 0x00FF);
+			    ((*data_ptr >> 8) & 0x00FF);
 
 	return ret;
 }
@@ -128,8 +124,7 @@ static int opt3001_i2c_read(const int port,
 /**
  *  Write register to OPT3001 light sensor.
  */
-static int opt3001_i2c_write(const int port,
-			     const uint16_t i2c_addr_flags,
+static int opt3001_i2c_write(const int port, const uint16_t i2c_addr_flags,
 			     const int reg, int data)
 {
 	data = ((data << 8) & 0xFF00) | ((data >> 8) & 0x00FF);
@@ -177,25 +172,18 @@ int opt3001_read_lux(const struct motion_sensor_t *s, intv3_t v)
 	}
 }
 
-static int opt3001_set_range(const struct motion_sensor_t *s, int range,
-			     int rnd)
+static int opt3001_set_range(struct motion_sensor_t *s, int range, int rnd)
 {
 	struct opt3001_drv_data_t *drv_data = OPT3001_GET_DATA(s);
 
 	drv_data->scale = range >> 16;
 	drv_data->uscale = range & 0xffff;
+	s->current_range = range;
 	return EC_SUCCESS;
 }
 
-static int opt3001_get_range(const struct motion_sensor_t *s)
-{
-	struct opt3001_drv_data_t *drv_data = OPT3001_GET_DATA(s);
-
-	return (drv_data->scale << 16) | (drv_data->uscale);
-}
-
-static int opt3001_set_data_rate(const struct motion_sensor_t *s,
-				int rate, int roundup)
+static int opt3001_set_data_rate(const struct motion_sensor_t *s, int rate,
+				 int roundup)
 {
 	struct opt3001_drv_data_t *drv_data = OPT3001_GET_DATA(s);
 	int rv;
@@ -222,10 +210,9 @@ static int opt3001_set_data_rate(const struct motion_sensor_t *s,
 	if (rv)
 		return rv;
 
-	rv = opt3001_i2c_write(s->port, s->i2c_spi_addr_flags,
-			       OPT3001_REG_CONFIGURE,
-			       (reg & OPT3001_MODE_MASK) |
-				   (mode << OPT3001_MODE_OFFSET));
+	rv = opt3001_i2c_write(
+		s->port, s->i2c_spi_addr_flags, OPT3001_REG_CONFIGURE,
+		(reg & OPT3001_MODE_MASK) | (mode << OPT3001_MODE_OFFSET));
 	if (rv)
 		return rv;
 
@@ -241,8 +228,7 @@ static int opt3001_get_data_rate(const struct motion_sensor_t *s)
 }
 
 static int opt3001_set_offset(const struct motion_sensor_t *s,
-			const int16_t *offset,
-			int16_t    temp)
+			      const int16_t *offset, int16_t temp)
 {
 	struct opt3001_drv_data_t *drv_data = OPT3001_GET_DATA(s);
 
@@ -250,9 +236,8 @@ static int opt3001_set_offset(const struct motion_sensor_t *s,
 	return EC_SUCCESS;
 }
 
-static int opt3001_get_offset(const struct motion_sensor_t *s,
-			int16_t   *offset,
-			int16_t    *temp)
+static int opt3001_get_offset(const struct motion_sensor_t *s, int16_t *offset,
+			      int16_t *temp)
 {
 	struct opt3001_drv_data_t *drv_data = OPT3001_GET_DATA(s);
 
@@ -265,7 +250,7 @@ static int opt3001_get_offset(const struct motion_sensor_t *s,
 /**
  * Initialise OPT3001 light sensor.
  */
-static int opt3001_init(const struct motion_sensor_t *s)
+static int opt3001_init(struct motion_sensor_t *s)
 {
 	int data;
 	int ret;
@@ -289,8 +274,8 @@ static int opt3001_init(const struct motion_sensor_t *s)
 	 * [11]   : 1b    Conversion time 800ms
 	 * [4]    : 1b    Latched window-style comparison operation
 	 */
-	opt3001_i2c_write(s->port, s->i2c_spi_addr_flags,
-			  OPT3001_REG_CONFIGURE, 0xC810);
+	opt3001_i2c_write(s->port, s->i2c_spi_addr_flags, OPT3001_REG_CONFIGURE,
+			  0xC810);
 
 	opt3001_set_range(s, s->default_range, 0);
 
@@ -301,7 +286,6 @@ const struct accelgyro_drv opt3001_drv = {
 	.init = opt3001_init,
 	.read = opt3001_read_lux,
 	.set_range = opt3001_set_range,
-	.get_range = opt3001_get_range,
 	.set_offset = opt3001_set_offset,
 	.get_offset = opt3001_get_offset,
 	.set_data_rate = opt3001_set_data_rate,
@@ -318,5 +302,5 @@ struct i2c_stress_test_dev opt3001_i2c_stress_test_dev = {
 	.i2c_read = &opt3001_i2c_read,
 	.i2c_write = &opt3001_i2c_write,
 };
-#endif  /* CONFIG_CMD_I2C_STRESS_TEST_ALS */
-#endif  /* HAS_TASK_ALS */
+#endif /* CONFIG_CMD_I2C_STRESS_TEST_ALS */
+#endif /* HAS_TASK_ALS */
diff --git a/driver/als_opt3001.h b/driver/als_opt3001.h
index 96b47232d1..54885c74ae 100644
--- a/driver/als_opt3001.h
+++ b/driver/als_opt3001.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -9,39 +9,39 @@
 #define __CROS_EC_ALS_OPT3001_H
 
 /* I2C interface */
-#define OPT3001_I2C_ADDR1_FLAGS		0x44
-#define OPT3001_I2C_ADDR2_FLAGS		0x45
-#define OPT3001_I2C_ADDR3_FLAGS		0x46
-#define OPT3001_I2C_ADDR4_FLAGS		0x47
+#define OPT3001_I2C_ADDR1_FLAGS 0x44
+#define OPT3001_I2C_ADDR2_FLAGS 0x45
+#define OPT3001_I2C_ADDR3_FLAGS 0x46
+#define OPT3001_I2C_ADDR4_FLAGS 0x47
 
 /* OPT3001 registers */
-#define OPT3001_REG_RESULT		0x00
-#define OPT3001_REG_CONFIGURE		0x01
-#define OPT3001_RANGE_OFFSET			12
-#define OPT3001_RANGE_MASK			0x0fff
-#define OPT3001_MODE_OFFSET			9
-#define OPT3001_MODE_MASK			0xf9ff
+#define OPT3001_REG_RESULT 0x00
+#define OPT3001_REG_CONFIGURE 0x01
+#define OPT3001_RANGE_OFFSET 12
+#define OPT3001_RANGE_MASK 0x0fff
+#define OPT3001_MODE_OFFSET 9
+#define OPT3001_MODE_MASK 0xf9ff
 enum opt3001_mode {
 	OPT3001_MODE_SUSPEND,
 	OPT3001_MODE_FORCED,
 	OPT3001_MODE_CONTINUOUS,
 };
 
-#define OPT3001_REG_INT_LIMIT_LSB	0x02
-#define OPT3001_REG_INT_LIMIT_MSB	0x03
-#define OPT3001_REG_MAN_ID		0x7e
-#define OPT3001_REG_DEV_ID		0x7f
+#define OPT3001_REG_INT_LIMIT_LSB 0x02
+#define OPT3001_REG_INT_LIMIT_MSB 0x03
+#define OPT3001_REG_MAN_ID 0x7e
+#define OPT3001_REG_DEV_ID 0x7f
 
 /* OPT3001 register values */
-#define OPT3001_MANUFACTURER_ID		0x5449
-#define OPT3001_DEVICE_ID		0x3001
+#define OPT3001_MANUFACTURER_ID 0x5449
+#define OPT3001_DEVICE_ID 0x3001
 
 /*
  * Min and Max sampling frequency in mHz.
  * Due to integration set at 800ms, we limit max frequency to 1Hz.
  */
-#define OPT3001_LIGHT_MIN_FREQ          100
-#define OPT3001_LIGHT_MAX_FREQ          1000
+#define OPT3001_LIGHT_MIN_FREQ 100
+#define OPT3001_LIGHT_MAX_FREQ 1000
 #if (CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ <= OPT3001_LIGHT_MAX_FREQ)
 #error "EC too slow for light sensor"
 #endif
@@ -50,7 +50,7 @@ enum opt3001_mode {
 int opt3001_init(void);
 int opt3001_read_lux(int *lux, int af);
 #else
-#define OPT3001_GET_DATA(_s)	((struct opt3001_drv_data_t *)(_s)->drv_data)
+#define OPT3001_GET_DATA(_s) ((struct opt3001_drv_data_t *)(_s)->drv_data)
 
 struct opt3001_drv_data_t {
 	int rate;
@@ -68,4 +68,4 @@ extern const struct accelgyro_drv opt3001_drv;
 extern struct i2c_stress_test_dev opt3001_i2c_stress_test_dev;
 #endif
 
-#endif	/* __CROS_EC_ALS_OPT3001_H */
+#endif /* __CROS_EC_ALS_OPT3001_H */
diff --git a/driver/als_si114x.c b/driver/als_si114x.c
index 35405bbea7..eba613be8b 100644
--- a/driver/als_si114x.c
+++ b/driver/als_si114x.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,11 +19,15 @@
 #include "timer.h"
 #include "util.h"
 
+#ifdef CONFIG_ALS_SI114X_INT_EVENT
+#define ALS_SI114X_INT_ENABLE
+#endif
+
 #define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args)
 
-static int init(const struct motion_sensor_t *s);
+static int init(struct motion_sensor_t *s);
 
 /**
  * Read 8bit register from device.
@@ -53,29 +57,26 @@ static inline int raw_read16(const int port, const uint16_t i2c_addr_flags,
 }
 
 /* helper function to operate on parameter values: op can be query/set/or/and */
-static int si114x_param_op(const struct motion_sensor_t *s,
-			   uint8_t op,
-			   uint8_t param,
-			   int *value)
+static int si114x_param_op(const struct motion_sensor_t *s, uint8_t op,
+			   uint8_t param, int *value)
 {
 	int ret;
 
 	mutex_lock(s->mutex);
 
-	if (op != SI114X_CMD_PARAM_QUERY) {
+	if (op != SI114X_COMMAND_PARAM_QUERY) {
 		ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-				 SI114X_REG_PARAM_WR, *value);
+				 SI114X_PARAM_WR, *value);
 		if (ret != EC_SUCCESS)
 			goto error;
 	}
 
-	ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-			 SI114X_REG_COMMAND, op | (param & 0x1F));
+	ret = raw_write8(s->port, s->i2c_spi_addr_flags, SI114X_COMMAND,
+			 op | (param & 0x1F));
 	if (ret != EC_SUCCESS)
 		goto error;
 
-	ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-			SI114X_REG_PARAM_RD, value);
+	ret = raw_read8(s->port, s->i2c_spi_addr_flags, SI114X_PARAM_RD, value);
 	if (ret != EC_SUCCESS)
 		goto error;
 
@@ -97,8 +98,7 @@ static int si114x_read_results(struct motion_sensor_t *s, int nb)
 	/* Read ALX result */
 	for (i = 0; i < nb; i++) {
 		ret = raw_read16(s->port, s->i2c_spi_addr_flags,
-				 type_data->base_data_reg + i * 2,
-				 &val);
+				 type_data->base_data_reg + i * 2, &val);
 		if (ret)
 			break;
 		if (val == SI114X_OVERFLOW) {
@@ -117,9 +117,8 @@ static int si114x_read_results(struct motion_sensor_t *s, int nb)
 		 * we correct later with the scale parameter.
 		 */
 		if (s->type == MOTIONSENSE_TYPE_PROX)
-			val = SI114X_PS_INVERSION(val);
-		val = val * type_data->scale +
-			val * type_data->uscale / 10000;
+			val = BIT(16) / val;
+		val = val * type_data->scale + val * type_data->uscale / 10000;
 		s->raw_xyz[i] = val;
 	}
 
@@ -144,39 +143,22 @@ static int si114x_read_results(struct motion_sensor_t *s, int nb)
 	if (i == nb)
 		return EC_ERROR_UNCHANGED;
 
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
-		struct ec_response_motion_sensor_data vector;
-
-		vector.flags = 0;
-		for (i = 0; i < nb; i++)
-			vector.data[i] = s->raw_xyz[i];
-		for (i = nb; i < 3; i++)
-			vector.data[i] = 0;
-		vector.sensor_num = s - motion_sensors;
-		motion_sense_fifo_stage_data(&vector, s, nb,
-					     __hw_clock_source_read());
-		motion_sense_fifo_commit_data();
-		/*
-		 * TODO: get time at a more accurate spot.
-		 * Like in si114x_interrupt
-		 */
-	}
-	/* Otherwise, we need to copy raw_xyz into xyz with mutex */
+	for (i = nb; i < 3; i++)
+		s->raw_xyz[i] = 0;
+
+	motion_sense_push_raw_xyz(s);
 	return EC_SUCCESS;
 }
 
 void si114x_interrupt(enum gpio_signal signal)
 {
-	task_set_event(TASK_ID_MOTIONSENSE,
-		       CONFIG_ALS_SI114X_INT_EVENT, 0);
+	task_set_event(TASK_ID_MOTIONSENSE, CONFIG_ALS_SI114X_INT_EVENT);
 }
 
 #ifdef CONFIG_ALS_SI114X_POLLING
 static void si114x_read_deferred(void)
 {
-	task_set_event(TASK_ID_MOTIONSENSE,
-		       CONFIG_ALS_SI114X_INT_EVENT, 0);
-
+	task_set_event(TASK_ID_MOTIONSENSE, CONFIG_ALS_SI114X_INT_EVENT);
 }
 DECLARE_DEFERRED(si114x_read_deferred);
 #endif
@@ -197,8 +179,8 @@ static int irq_handler(struct motion_sensor_t *s, uint32_t *event)
 	if (!(*event & CONFIG_ALS_SI114X_INT_EVENT))
 		return EC_ERROR_NOT_HANDLED;
 
-	ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-			SI114X_REG_IRQ_STATUS, &val);
+	ret = raw_read8(s->port, s->i2c_spi_addr_flags, SI114X_IRQ_STATUS,
+			&val);
 	if (ret)
 		return ret;
 
@@ -206,8 +188,7 @@ static int irq_handler(struct motion_sensor_t *s, uint32_t *event)
 		return EC_ERROR_INVAL;
 
 	/* clearing IRQ */
-	ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-			 SI114X_REG_IRQ_STATUS,
+	ret = raw_write8(s->port, s->i2c_spi_addr_flags, SI114X_IRQ_STATUS,
 			 val & type_data->irq_flags);
 	if (ret != EC_SUCCESS)
 		CPRINTS("clearing irq failed");
@@ -220,8 +201,8 @@ static int irq_handler(struct motion_sensor_t *s, uint32_t *event)
 		/* Fire pending requests */
 		if (data->state == SI114X_ALS_IN_PROGRESS_PS_PENDING) {
 			ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-					 SI114X_REG_COMMAND,
-					 SI114X_CMD_PS_FORCE);
+					 SI114X_COMMAND,
+					 SI114X_COMMAND_PS_FORCE);
 			data->state = SI114X_PS_IN_PROGRESS;
 		} else {
 			data->state = SI114X_IDLE;
@@ -233,8 +214,8 @@ static int irq_handler(struct motion_sensor_t *s, uint32_t *event)
 		ret = si114x_read_results(s, SI114X_NUM_LEDS);
 		if (data->state == SI114X_PS_IN_PROGRESS_ALS_PENDING) {
 			ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-					 SI114X_REG_COMMAND,
-					 SI114X_CMD_ALS_FORCE);
+					 SI114X_COMMAND,
+					 SI114X_COMMAND_ALS_FORCE);
 			data->state = SI114X_ALS_IN_PROGRESS;
 		} else {
 			data->state = SI114X_IDLE;
@@ -276,19 +257,19 @@ static int read(const struct motion_sensor_t *s, intv3_t v)
 	case SI114X_IDLE:
 		switch (s->type) {
 		case MOTIONSENSE_TYPE_LIGHT:
-			cmd = SI114X_CMD_ALS_FORCE;
+			cmd = SI114X_COMMAND_ALS_FORCE;
 			data->state = SI114X_ALS_IN_PROGRESS;
 			break;
 		case MOTIONSENSE_TYPE_PROX:
-			cmd = SI114X_CMD_PS_FORCE;
+			cmd = SI114X_COMMAND_PS_FORCE;
 			data->state = SI114X_PS_IN_PROGRESS;
 			break;
 		default:
 			CPRINTS("Invalid sensor type");
 			return EC_ERROR_INVAL;
 		}
-		ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-				 SI114X_REG_COMMAND, cmd);
+		ret = raw_write8(s->port, s->i2c_spi_addr_flags, SI114X_COMMAND,
+				 cmd);
 #ifdef CONFIG_ALS_SI114X_POLLING
 		hook_call_deferred(&si114x_read_deferred_data,
 				   SI114x_POLLING_DELAY);
@@ -317,7 +298,7 @@ static int read(const struct motion_sensor_t *s, intv3_t v)
 			int ret, val;
 
 			ret = raw_read8(s->port, s->addr,
-					SI114X_REG_IRQ_STATUS, &val);
+					SI114X_IRQ_STATUS, &val);
 			CPRINTS("%d stuck IRQ_STATUS 0x%02x - ret %d",
 				s->name, val, ret);
 			init(s);
@@ -332,26 +313,30 @@ static int si114x_set_chlist(const struct motion_sensor_t *s)
 	int reg = 0;
 
 	/* Not interested in temperature (AUX nor IR) */
-	reg = SI114X_CHLIST_EN_ALSVIS;
+	reg = SI114X_PARAM_CHLIST_EN_ALS_VIS;
 	switch (SI114X_NUM_LEDS) {
 	case 3:
-		reg |= SI114X_CHLIST_EN_PS3;
+		reg |= SI114X_PARAM_CHLIST_EN_PS3;
+		__fallthrough;
 	case 2:
-		reg |= SI114X_CHLIST_EN_PS2;
+		reg |= SI114X_PARAM_CHLIST_EN_PS2;
+		__fallthrough;
 	case 1:
-		reg |= SI114X_CHLIST_EN_PS1;
+		reg |= SI114X_PARAM_CHLIST_EN_PS1;
+		__fallthrough;
+	case 0:
 		break;
 	}
 
-	return si114x_param_op(s, SI114X_CMD_PARAM_SET,
-			SI114X_PARAM_CHLIST, &reg);
+	return si114x_param_op(s, SI114X_COMMAND_PARAM_SET, SI114X_PARAM_CHLIST,
+			       &reg);
 }
 
 #ifdef CONFIG_ALS_SI114X_CHECK_REVISION
 static int si114x_revisions(const struct motion_sensor_t *s)
 {
 	int val;
-	int ret = raw_read8(s->port, s->addr, SI114X_REG_PART_ID, &val);
+	int ret = raw_read8(s->port, s->addr, SI114X_PART_ID, &val);
 	if (ret != EC_SUCCESS)
 		return ret;
 
@@ -360,7 +345,7 @@ static int si114x_revisions(const struct motion_sensor_t *s)
 		return EC_ERROR_ACCESS_DENIED;
 	}
 
-	ret = raw_read8(s->port, s->port, s->addr, SI114X_REG_SEQ_ID, &val);
+	ret = raw_read8(s->port, s->port, s->addr, SI114X_SEQ_ID, &val);
 	if (ret != EC_SUCCESS)
 		return ret;
 
@@ -376,68 +361,67 @@ static int si114x_initialize(const struct motion_sensor_t *s)
 	int ret, val;
 
 	/* send reset command */
-	ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-			 SI114X_REG_COMMAND, SI114X_CMD_RESET);
+	ret = raw_write8(s->port, s->i2c_spi_addr_flags, SI114X_COMMAND,
+			 SI114X_COMMAND_RESET);
 	if (ret != EC_SUCCESS)
 		return ret;
 	msleep(20);
 
 	/* hardware key, magic value */
-	ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-			 SI114X_REG_HW_KEY, 0x17);
+	ret = raw_write8(s->port, s->i2c_spi_addr_flags, SI114X_HW_KEY,
+			 SI114X_HW_KEY_VALUE);
 	if (ret != EC_SUCCESS)
 		return ret;
 	msleep(20);
 
 	/* interrupt configuration, interrupt output enable */
-	ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-			 SI114X_REG_INT_CFG, SI114X_INT_CFG_OE);
+	ret = raw_write8(s->port, s->i2c_spi_addr_flags, SI114X_INT_CFG,
+			 SI114X_INT_CFG_INT_OE);
 	if (ret != EC_SUCCESS)
 		return ret;
 
 	/* enable interrupt for certain activities */
-	ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-			 SI114X_REG_IRQ_ENABLE,
-			 SI114X_PS3_IE | SI114X_PS2_IE | SI114X_PS1_IE |
-			 SI114X_ALS_INT0_IE);
+	ret = raw_write8(s->port, s->i2c_spi_addr_flags, SI114X_IRQ_ENABLE,
+			 SI114X_IRQ_ENABLE_PS3_IE | SI114X_IRQ_ENABLE_PS2_IE |
+				 SI114X_IRQ_ENABLE_PS1_IE |
+				 SI114X_IRQ_ENABLE_ALS_IE_INT0);
 	if (ret != EC_SUCCESS)
 		return ret;
 
 	/* Only forced mode */
-	ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-			 SI114X_REG_MEAS_RATE, 0);
+	ret = raw_write8(s->port, s->i2c_spi_addr_flags, SI114X_MEAS_RATE, 0);
 	if (ret != EC_SUCCESS)
 		return ret;
 
 	/* measure ALS every time device wakes up */
-	ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-			 SI114X_REG_ALS_RATE, 0);
+	ret = raw_write8(s->port, s->i2c_spi_addr_flags, SI114X_ALS_RATE, 0);
 	if (ret != EC_SUCCESS)
 		return ret;
 
 	/* measure proximity every time device wakes up */
-	ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-			 SI114X_REG_PS_RATE, 0);
+	ret = raw_write8(s->port, s->i2c_spi_addr_flags, SI114X_PS_RATE, 0);
 	if (ret != EC_SUCCESS)
 		return ret;
 
 	/* set LED currents to maximum */
 	switch (SI114X_NUM_LEDS) {
 	case 3:
-		ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-				 SI114X_REG_PS_LED3, 0x0f);
+		ret = raw_write8(s->port, s->i2c_spi_addr_flags, SI114X_PS_LED3,
+				 0x0f);
 		if (ret != EC_SUCCESS)
 			return ret;
 		ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-				 SI114X_REG_PS_LED21, 0xff);
+				 SI114X_PS_LED21, 0xff);
 		break;
 	case 2:
 		ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-				 SI114X_REG_PS_LED21, 0xff);
+				 SI114X_PS_LED21, 0xff);
 		break;
 	case 1:
 		ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-				 SI114X_REG_PS_LED21, 0x0f);
+				 SI114X_PS_LED21, 0x0f);
+		break;
+	case 0:
 		break;
 	}
 	if (ret != EC_SUCCESS)
@@ -449,15 +433,13 @@ static int si114x_initialize(const struct motion_sensor_t *s)
 
 	/* set normal proximity measurement mode, set high signal range
 	 * PS measurement */
-	val = SI114X_PARAM_PS_ADC_MISC_NORMAL_MODE;
-	ret = si114x_param_op(s, SI114X_CMD_PARAM_SET,
+	val = SI114X_PARAM_PS_ADC_MISC_MODE_NORMAL_PROXIMITY;
+	ret = si114x_param_op(s, SI114X_COMMAND_PARAM_SET,
 			      SI114X_PARAM_PS_ADC_MISC, &val);
 	return ret;
 }
 
-static int set_resolution(const struct motion_sensor_t *s,
-				int res,
-				int rnd)
+static int set_resolution(const struct motion_sensor_t *s, int res, int rnd)
 {
 	int ret, reg1, reg2, val;
 	/* override on resolution: set the gain. between 0 to 7 */
@@ -469,17 +451,17 @@ static int set_resolution(const struct motion_sensor_t *s,
 	} else {
 		if (res < 0 || res > 7)
 			return EC_ERROR_PARAM2;
-		reg1 = SI114X_PARAM_ALSVIS_ADC_GAIN;
-		reg2 = SI114X_PARAM_ALSVIS_ADC_COUNTER;
+		reg1 = SI114X_PARAM_ALS_VIS_ADC_GAIN;
+		reg2 = SI114X_PARAM_ALS_VIS_ADC_COUNTER;
 	}
 
 	val = res;
-	ret = si114x_param_op(s, SI114X_CMD_PARAM_SET, reg1, &val);
+	ret = si114x_param_op(s, SI114X_COMMAND_PARAM_SET, reg1, &val);
 	if (ret != EC_SUCCESS)
 		return ret;
 	/* set recovery period to one's complement of gain */
 	val = (~res & 0x07) << 4;
-	ret = si114x_param_op(s, SI114X_CMD_PARAM_SET, reg2, &val);
+	ret = si114x_param_op(s, SI114X_COMMAND_PARAM_SET, reg2, &val);
 	return ret;
 }
 
@@ -490,32 +472,25 @@ static int get_resolution(const struct motion_sensor_t *s)
 		reg = SI114X_PARAM_PS_ADC_GAIN;
 	else
 		/* ignore IR led */
-		reg = SI114X_PARAM_ALSVIS_ADC_GAIN;
+		reg = SI114X_PARAM_ALS_VIS_ADC_GAIN;
 
 	val = 0;
-	ret = si114x_param_op(s, SI114X_CMD_PARAM_QUERY, reg, &val);
+	ret = si114x_param_op(s, SI114X_COMMAND_PARAM_QUERY, reg, &val);
 	if (ret != EC_SUCCESS)
 		return -1;
 
 	return val & 0x07;
 }
 
-static int set_range(const struct motion_sensor_t *s,
-				int range,
-				int rnd)
+static int set_range(struct motion_sensor_t *s, int range, int rnd)
 {
 	struct si114x_typed_data_t *data = SI114X_GET_TYPED_DATA(s);
 	data->scale = range >> 16;
 	data->uscale = range & 0xffff;
+	s->current_range = range;
 	return EC_SUCCESS;
 }
 
-static int get_range(const struct motion_sensor_t *s)
-{
-	struct si114x_typed_data_t *data = SI114X_GET_TYPED_DATA(s);
-	return (data->scale << 16) | (data->uscale);
-}
-
 static int get_data_rate(const struct motion_sensor_t *s)
 {
 	/* Sensor in forced mode, rate is used by motion_sense */
@@ -523,27 +498,23 @@ static int get_data_rate(const struct motion_sensor_t *s)
 	return data->rate;
 }
 
-static int set_data_rate(const struct motion_sensor_t *s,
-				int rate,
-				int rnd)
+static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
 {
 	struct si114x_typed_data_t *data = SI114X_GET_TYPED_DATA(s);
 	data->rate = rate;
 	return EC_SUCCESS;
 }
 
-static int set_offset(const struct motion_sensor_t *s,
-			const int16_t *offset,
-			int16_t    temp)
+static int set_offset(const struct motion_sensor_t *s, const int16_t *offset,
+		      int16_t temp)
 {
 	struct si114x_typed_data_t *data = SI114X_GET_TYPED_DATA(s);
 	data->offset = offset[X];
 	return EC_SUCCESS;
 }
 
-static int get_offset(const struct motion_sensor_t *s,
-			int16_t   *offset,
-			int16_t    *temp)
+static int get_offset(const struct motion_sensor_t *s, int16_t *offset,
+		      int16_t *temp)
 {
 	struct si114x_typed_data_t *data = SI114X_GET_TYPED_DATA(s);
 	offset[X] = data->offset;
@@ -553,7 +524,7 @@ static int get_offset(const struct motion_sensor_t *s,
 	return EC_SUCCESS;
 }
 
-static int init(const struct motion_sensor_t *s)
+static int init(struct motion_sensor_t *s)
 {
 	int ret, resol;
 	struct si114x_drv_data_t *data = SI114X_GET_DATA(s);
@@ -590,14 +561,13 @@ const struct accelgyro_drv si114x_drv = {
 	.init = init,
 	.read = read,
 	.set_range = set_range,
-	.get_range = get_range,
 	.set_resolution = set_resolution,
 	.get_resolution = get_resolution,
 	.set_data_rate = set_data_rate,
 	.get_data_rate = get_data_rate,
 	.set_offset = set_offset,
 	.get_offset = get_offset,
-#ifdef CONFIG_ACCEL_INTERRUPTS
+#ifdef ALS_SI114X_INT_ENABLE
 	.irq_handler = irq_handler,
 #endif
 };
diff --git a/driver/als_si114x.h b/driver/als_si114x.h
index dc5459e8db..57ef6f8021 100644
--- a/driver/als_si114x.h
+++ b/driver/als_si114x.h
@@ -1,224 +1,82 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Silicon Image SI1141/SI1142 light sensor driver
  */
 
-/*
- * si114x.c - Support for Silabs si114x combined ambient light and
- * proximity sensor
- *
- * Copyright 2012 Peter Meerwald <pmeerw@pmeerw.net>
- *
- * This file is subject to the terms and conditions of version 2 of
- * the GNU General Public License.  See the file COPYING in the main
- * directory of this archive for more details.
- *
- * IIO driver for si114x (7-bit I2C slave address 0x5a) with sequencer
- * version >= A03
- */
-
 #ifndef __CROS_EC_ALS_SI114X_H
 #define __CROS_EC_ALS_SI114X_H
 
-#define SI114X_ADDR_FLAGS               0x5a
-
-#define SI114X_REG_PART_ID		0x00
-#define SI114X_SI1141_ID                     0x41
-#define SI114X_SI1142_ID                     0x42
-#define SI114X_SI1143_ID                     0x43
-
-#define SI114X_NUM_LEDS  (CONFIG_ALS_SI114X - 0x40)
-
-#define SI114X_REG_REV_ID		0x01
-#define SI114X_REG_SEQ_ID		0x02
-#define SI114X_REG_INT_CFG		0x03
-#define SI114X_REG_IRQ_ENABLE		0x04
-#define SI114X_REG_IRQ_MODE1		0x05
-#define SI114X_REG_IRQ_MODE2		0x06
-#define SI114X_REG_HW_KEY		0x07
-/* RATE stores a 16 bit value compressed to 8 bit */
-/* Not used, the sensor is in force mode */
-#define SI114X_REG_MEAS_RATE		0x08
-
-
-#define SI114X_REG_ALS_RATE		0x09
-#define SI114X_REG_PS_RATE		0x0a
-#define SI114X_REG_ALS_LOW_TH0		0x0b
-#define SI114X_REG_ALS_LOW_TH1		0x0c
-#define SI114X_REG_ALS_HI_TH0		0x0d
-#define SI114X_REG_ALS_HI_TH1		0x0e
-#define SI114X_REG_PS_LED21		0x0f
-#define SI114X_REG_PS_LED3		0x10
-/*
- * for rev A10 and below TH0 stores a 16 bit value compressed to 8 bit and
- * TH1 is not used; newer revision have the LSB in TH0 and the MSB in TH1
- */
-#define SI114X_REG_PS1_TH0		0x11
-#define SI114X_REG_PS1_TH1		0x12
-#define SI114X_REG_PS2_TH0		0x13
-#define SI114X_REG_PS2_TH1		0x11
-#define SI114X_REG_PS3_TH0		0x15
-#define SI114X_REG_PS3_TH1		0x16
-#define SI114X_REG_PARAM_WR		0x17
-#define SI114X_REG_COMMAND		0x18
-#define SI114X_REG_RESPONSE		0x20
-#define SI114X_REG_IRQ_STATUS		0x21
-#define SI114X_REG_ALSVIS_DATA0		0x22
-#define SI114X_REG_ALSVIS_DATA1		0x23
-#define SI114X_REG_ALSIR_DATA0		0x24
-#define SI114X_REG_ALSIR_DATA1		0x25
-#define SI114X_REG_PS1_DATA0		0x26
-#define SI114X_REG_PS1_DATA1		0x27
-#define SI114X_REG_PS2_DATA0		0x28
-#define SI114X_REG_PS2_DATA1		0x29
-#define SI114X_REG_PS3_DATA0		0x2a
-#define SI114X_REG_PS3_DATA1		0x2b
-#define SI114X_PS_INVERSION(_data) (BIT(16) / (_data))
-#define SI114X_REG_AUX_DATA0		0x2c
-#define SI114X_REG_AUX_DATA1		0x2d
-#define SI114X_REG_PARAM_RD		0x2e
-#define SI114X_REG_CHIP_STAT		0x30
-
-/* helper to figure out PS_LED register / shift per channel */
-#define SI114X_PS_LED_REG(ch) \
-	(((ch) == 2) ? SI114X_REG_PS_LED3 : SI114X_REG_PS_LED21)
-#define SI114X_PS_LED_SHIFT(ch) \
-	(((ch) == 1) ? 4 : 0)
-
-/* Parameter offsets */
-#define SI114X_PARAM_I2C_ADDR		0x00
-#define SI114X_PARAM_CHLIST		0x01
-#define SI114X_PARAM_PSLED12_SELECT	0x02
-#define SI114X_PARAM_PSLED3_SELECT	0x03
-#define SI114X_PARAM_FILTER_EN		0x04
-#define SI114X_PARAM_PS_ENCODING	0x05
-#define SI114X_PARAM_ALS_ENCODING	0x06
-#define SI114X_PARAM_PS1_ADC_MUX	0x07
-#define SI114X_PARAM_PS2_ADC_MUX	0x08
-#define SI114X_PARAM_PS3_ADC_MUX	0x09
-#define SI114X_PARAM_PS_ADC_COUNTER	0x0a
-#define SI114X_PARAM_PS_ADC_GAIN	0x0b
-#define SI114X_PARAM_PS_ADC_MISC	0x0c
-#define SI114X_PARAM_PS_ADC_MISC_HIGH_RANGE       0x20
-#define SI114X_PARAM_PS_ADC_MISC_NORMAL_MODE      0x04
-#define SI114X_PARAM_ALS_ADC_MUX	0x0d
-#define SI114X_PARAM_ALSIR_ADC_MUX	0x0e
-#define SI114X_PARAM_AUX_ADC_MUX	0x0f
-#define SI114X_PARAM_ALSVIS_ADC_COUNTER	0x10
-#define SI114X_PARAM_ALSVIS_ADC_GAIN	0x11
-#define SI114X_PARAM_ALSVIS_ADC_MISC	0x12
-#define SI114X_PARAM_ALS_HYST		0x16
-#define SI114X_PARAM_PS_HYST		0x17
-#define SI114X_PARAM_PS_HISTORY		0x18
-#define SI114X_PARAM_ALS_HISTORY	0x19
-#define SI114X_PARAM_ADC_OFFSET		0x1a
-#define SI114X_PARAM_SLEEP_CTRL		0x1b
-#define SI114X_PARAM_LED_RECOVERY	0x1c
-#define SI114X_PARAM_ALSIR_ADC_COUNTER	0x1d
-#define SI114X_PARAM_ALSIR_ADC_GAIN	0x1e
-#define SI114X_PARAM_ALSIR_ADC_MISC	0x1f
-
-/* Channel enable masks for CHLIST parameter */
-#define SI114X_CHLIST_EN_PS1		0x01
-#define SI114X_CHLIST_EN_PS2		0x02
-#define SI114X_CHLIST_EN_PS3		0x04
-#define SI114X_CHLIST_EN_ALSVIS		0x10
-#define SI114X_CHLIST_EN_ALSIR		0x20
-#define SI114X_CHLIST_EN_AUX		0x40
+#define SI114X_ADDR_FLAGS 0x5a
 
-/* Signal range mask for ADC_MISC parameter */
-#define SI114X_MISC_RANGE		0x20
+#define SI114X_PART_ID 0x00
+#define SI114X_SEQ_ID 0x02
 
-/* Commands for REG_COMMAND */
-#define SI114X_CMD_NOP			0x00
-#define SI114X_CMD_RESET		0x01
-#define SI114X_CMD_BUSADDR		0x02
-#define SI114X_CMD_PS_FORCE		0x05
-#define SI114X_CMD_ALS_FORCE		0x06
-#define SI114X_CMD_PSALS_FORCE		0x07
-#define SI114X_CMD_PS_PAUSE		0x09
-#define SI114X_CMD_ALS_PAUSE		0x0a
-#define SI114X_CMD_PSALS_PAUSE		0x0b
-#define SI114X_CMD_PS_AUTO		0x0d
-#define SI114X_CMD_ALS_AUTO		0x0e
-#define SI114X_CMD_PSALS_AUTO		0x0f
-#define SI114X_CMD_PARAM_QUERY		0x80
-#define SI114X_CMD_PARAM_SET		0xa0
-#define SI114X_CMD_PARAM_AND		0xc0
-#define SI114X_CMD_PARAM_OR		0xe0
+#define SI114X_INT_CFG 0x03
+#define SI114X_INT_CFG_INT_OE BIT(0)
 
-/* Interrupt configuration masks for INT_CFG register */
-#define SI114X_INT_CFG_OE		0x01 /* enable interrupt */
-#define SI114X_INT_CFG_MODE		0x02 /* auto reset interrupt pin */
+#define SI114X_IRQ_ENABLE 0x04
+#define SI114X_IRQ_ENABLE_PS3_IE BIT(4)
+#define SI114X_IRQ_ENABLE_PS2_IE BIT(3)
+#define SI114X_IRQ_ENABLE_PS1_IE BIT(2)
+#define SI114X_IRQ_ENABLE_ALS_IE_INT1 BIT(1)
+#define SI114X_IRQ_ENABLE_ALS_IE_INT0 BIT(0)
 
-/* Interrupt enable masks for IRQ_ENABLE register */
-#define SI114X_CMD_IE			0x20
-#define SI114X_PS3_IE			0x10
-#define SI114X_PS2_IE			0x08
-#define SI114X_PS1_IE			0x04
-#define SI114X_ALS_INT1_IE		0x02
-#define SI114X_ALS_INT0_IE		0x01
-#define SI114X_ALS_INT_FLAG \
-	(SI114X_ALS_INT1_IE | SI114X_ALS_INT0_IE)
-#define SI114X_PS_INT_FLAG \
-	(SI114X_PS3_IE | SI114X_PS2_IE | SI114X_PS1_IE)
+#define SI114X_HW_KEY 0x07
+#define SI114X_HW_KEY_VALUE 0x17
 
+#define SI114X_MEAS_RATE 0x08
+#define SI114X_ALS_RATE 0x09
+#define SI114X_PS_RATE 0x0A
 
-/* Interrupt mode masks for IRQ_MODE1 register */
-#define SI114X_PS2_IM_GREATER		0xc0
-#define SI114X_PS2_IM_CROSS		0x40
-#define SI114X_PS1_IM_GREATER		0x30
-#define SI114X_PS1_IM_CROSS		0x10
+#define SI114X_PS_LED21 0x0F
+#define SI114X_PS_LED3 0x10
+#define SI114X_NUM_LEDS (CONFIG_ALS_SI114X - 0x40)
 
-/* Interrupt mode masks for IRQ_MODE2 register */
-#define SI114X_CMD_IM_ERROR		0x04
-#define SI114X_PS3_IM_GREATER		0x03
-#define SI114X_PS3_IM_CROSS		0x01
+#define SI114X_PARAM_WR 0x17
+#define SI114X_COMMAND 0x18
 
-/* Measurement rate settings */
-#define SI114X_MEAS_RATE_FORCED		0x00
-#define SI114X_MEAS_RATE_10MS		0x84
-#define SI114X_MEAS_RATE_20MS		0x94
-#define SI114X_MEAS_RATE_100MS		0xb9
-#define SI114X_MEAS_RATE_496MS		0xdf
-#define SI114X_MEAS_RATE_1984MS		0xff
+#define SI114X_COMMAND_PARAM_QUERY 0x80
+#define SI114X_COMMAND_PARAM_SET 0xA0
+#define SI114X_PARAM_CHLIST 0x01
+#define SI114X_PARAM_CHLIST_EN_ALS_VIS BIT(4)
+#define SI114X_PARAM_CHLIST_EN_PS3 BIT(2)
+#define SI114X_PARAM_CHLIST_EN_PS2 BIT(1)
+#define SI114X_PARAM_CHLIST_EN_PS1 BIT(0)
+#define SI114X_PARAM_PS_ADC_COUNTER 0x0A
+#define SI114X_PARAM_PS_ADC_GAIN 0x0B
+#define SI114X_PARAM_PS_ADC_MISC 0x0C
+#define SI114X_PARAM_PS_ADC_MISC_MODE BIT(2)
+#define SI114X_PARAM_PS_ADC_MISC_MODE_NORMAL_PROXIMITY BIT(2)
+#define SI114X_PARAM_ALS_VIS_ADC_COUNTER 0x10
+#define SI114X_PARAM_ALS_VIS_ADC_GAIN 0x11
+#define SI114X_PARAM_ALS_VIS_ADC_MISC 0x12
 
-/* ALS rate settings relative to measurement rate */
-#define SI114X_ALS_RATE_OFF		0x00
-#define SI114X_ALS_RATE_1X		0x08
-#define SI114X_ALS_RATE_10X		0x32
-#define SI114X_ALS_RATE_100X		0x69
+#define SI114X_COMMAND_RESET 0x01
+#define SI114X_COMMAND_PS_FORCE 0x05
+#define SI114X_COMMAND_ALS_FORCE 0x06
 
-/* PS rate settings relative to measurement rate */
-#define SI114X_PS_RATE_OFF		0x00
-#define SI114X_PS_RATE_1X		0x08
-#define SI114X_PS_RATE_10X		0x32
-#define SI114X_PS_RATE_100X		0x69
+#define SI114X_IRQ_STATUS 0x21
+#define SI114X_ALS_VIS_DATA0 0x22
 
-/* Sequencer revision from SEQ_ID */
-#define SI114X_SEQ_REV_A01		0x01
-#define SI114X_SEQ_REV_A02		0x02
-#define SI114X_SEQ_REV_A03		0x03
-#define SI114X_SEQ_REV_A10		0x08
-#define SI114X_SEQ_REV_A11		0x09
+#define SI114X_PARAM_RD 0x2E
 
 /* Proximity sensor finds an object within 5 cm, disable light sensor */
-#define SI114X_COVERED_THRESHOLD        5
-#define SI114X_OVERFLOW                 0xffff
+#define SI114X_COVERED_THRESHOLD 5
+#define SI114X_OVERFLOW 0xffff
 
 /* Time to wait before re-initializing the device if access is denied */
-#define SI114X_DENIED_THRESHOLD		(10 * SECOND)
+#define SI114X_DENIED_THRESHOLD (10 * SECOND)
 
 /* Delay used for deferred callback when polling is enabled */
 #define SI114x_POLLING_DELAY (8 * MSEC)
 
 /* Min and Max sampling frequency in mHz */
-#define SI114X_PROX_MIN_FREQ            504
-#define SI114X_PROX_MAX_FREQ            50000
-#define SI114X_LIGHT_MIN_FREQ           504
-#define SI114X_LIGHT_MAX_FREQ           50000
+#define SI114X_PROX_MIN_FREQ 504
+#define SI114X_PROX_MAX_FREQ 50000
+#define SI114X_LIGHT_MIN_FREQ 504
+#define SI114X_LIGHT_MAX_FREQ 50000
 #if (CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ <= SI114X_PROX_MAX_FREQ)
 #error "EC too slow for light sensor"
 #endif
@@ -234,10 +92,6 @@ enum si114x_state {
 	SI114X_PS_IN_PROGRESS_ALS_PENDING,
 };
 
-/**
- * struct si114x_data - si114x chip state data
- * @client:	I2C client
- **/
 struct si114x_typed_data_t {
 	uint8_t base_data_reg;
 	uint8_t irq_flags;
@@ -255,12 +109,11 @@ struct si114x_drv_data_t {
 	struct si114x_typed_data_t type_data[2];
 };
 
-#define SI114X_GET_DATA(_s) \
-	((struct si114x_drv_data_t *)(_s)->drv_data)
+#define SI114X_GET_DATA(_s) ((struct si114x_drv_data_t *)(_s)->drv_data)
 
 #define SI114X_GET_TYPED_DATA(_s) \
 	(&SI114X_GET_DATA(_s)->type_data[(_s)->type - MOTIONSENSE_TYPE_PROX])
 
 void si114x_interrupt(enum gpio_signal signal);
 
-#endif	/* __CROS_EC_ALS_SI114X_H */
+#endif /* __CROS_EC_ALS_SI114X_H */
diff --git a/driver/als_tcs3400.c b/driver/als_tcs3400.c
index 9ffe3cfab1..384e477904 100644
--- a/driver/als_tcs3400.c
+++ b/driver/als_tcs3400.c
@@ -1,13 +1,13 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * AMS TCS3400 light sensor driver
  */
 #include "accelgyro.h"
+#include "als_tcs3400.h"
 #include "common.h"
 #include "console.h"
-#include "driver/als_tcs3400.h"
 #include "hooks.h"
 #include "hwtimer.h"
 #include "i2c.h"
@@ -16,77 +16,56 @@
 #include "task.h"
 #include "util.h"
 
-#define CPRINTS(fmt, args...) cprints(CC_ACCEL, "%s "fmt, __func__, ## args)
-
-STATIC_IF(CONFIG_ACCEL_FIFO) volatile uint32_t last_interrupt_timestamp;
-
-#ifdef CONFIG_TCS_USE_LUX_TABLE
-/*
- * Stores the number of atime increments/decrements needed to change light value
- * by 1% of saturation for each gain setting for each predefined LUX range.
- *
- * Values in array are TCS_ATIME_GAIN_FACTOR (100x) times actual value to allow
- * for fractions using integers.
- */
-static const uint16_t
-range_atime[TCS_MAX_AGAIN - TCS_MIN_AGAIN + 1][TCS_MAX_ATIME_RANGES] = {
-{11200, 5600, 5600, 7200, 5500, 4500, 3800, 3800, 3300, 2900, 2575, 2275, 2075},
-{11200, 5100, 2700, 1840, 1400, 1133, 981, 963, 833, 728, 650, 577, 525},
-{250, 1225, 643, 441, 337, 276, 253, 235, 203, 176, 150, 0, 0},
-{790, 261, 163, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} };
+#ifdef CONFIG_ALS_TCS3400_INT_EVENT
+#define ALS_TCS3400_INT_ENABLE
+#endif
 
-static void
-decrement_atime(struct tcs_saturation_t *sat_p, uint16_t cur_lux, int percent)
-{
-	int atime;
-	uint16_t steps;
-	int lux = MIN(cur_lux, TCS_GAIN_TABLE_MAX_LUX);
+#define CPRINTS(fmt, args...) cprints(CC_ACCEL, "%s " fmt, __func__, ##args)
 
-	steps = percent * range_atime[sat_p->again][lux / 1000] /
-			TCS_ATIME_GAIN_FACTOR;
-	atime = MAX(sat_p->atime - steps, TCS_MIN_ATIME);
-	sat_p->atime = MIN(atime, TCS_MAX_ATIME);
-}
-
-#else
+volatile uint32_t last_interrupt_timestamp;
 
-static void
-decrement_atime(struct tcs_saturation_t *sat_p,
-		uint16_t __attribute__((unused)) cur_lux,
-		int __attribute__((unused)) percent)
+static void decrement_atime(struct tcs_saturation_t *sat_p,
+			    uint16_t __attribute__((unused)) cur_lux,
+			    int __attribute__((unused)) percent)
 {
 	sat_p->atime = MAX(sat_p->atime - TCS_ATIME_DEC_STEP, TCS_MIN_ATIME);
 }
 
-#endif /* CONFIG_TCS_USE_LUX_TABLE */
-
 static void increment_atime(struct tcs_saturation_t *sat_p)
 {
 	sat_p->atime = MIN(sat_p->atime + TCS_ATIME_INC_STEP, TCS_MAX_ATIME);
 }
 
-static inline int tcs3400_i2c_read8(const struct motion_sensor_t *s,
-				    int reg, int *data)
+static inline int tcs3400_i2c_read8(const struct motion_sensor_t *s, int reg,
+				    int *data)
 {
 	return i2c_read8(s->port, s->i2c_spi_addr_flags, reg, data);
 }
 
-static inline int tcs3400_i2c_write8(const struct motion_sensor_t *s,
-				     int reg, int data)
+static inline int tcs3400_i2c_write8(const struct motion_sensor_t *s, int reg,
+				     int data)
 {
 	return i2c_write8(s->port, s->i2c_spi_addr_flags, reg, data);
 }
 
+#ifdef CONFIG_ALS_TCS3400_EMULATED_IRQ_EVENT
 static void tcs3400_read_deferred(void)
+#else
+void tcs3400_interrupt(enum gpio_signal signal)
+#endif
 {
-	task_set_event(TASK_ID_MOTIONSENSE, CONFIG_ALS_TCS3400_INT_EVENT, 0);
+	last_interrupt_timestamp = __hw_clock_source_read();
+
+	task_set_event(TASK_ID_MOTIONSENSE, CONFIG_ALS_TCS3400_INT_EVENT);
 }
+#ifdef CONFIG_ALS_TCS3400_EMULATED_IRQ_EVENT
 DECLARE_DEFERRED(tcs3400_read_deferred);
+#endif
 
 /* convert ATIME register to integration time, in microseconds */
-static int tcs3400_get_integration_time(int atime)
+int tcs3400_get_integration_time(int atime)
 {
-	return 2780 * (256 - atime);
+	return TCS_MAX_INTEGRATION_TIME * (TCS_ATIME_GRANULARITY - atime);
 }
 
 static int tcs3400_read(const struct motion_sensor_t *s, intv3_t v)
@@ -95,12 +74,12 @@ static int tcs3400_read(const struct motion_sensor_t *s, intv3_t v)
 	int ret;
 
 	/* Chip may have been off, make sure to setup important registers */
-	if (TCS3400_RGB_DRV_DATA(s+1)->calibration_mode) {
+	if (TCS3400_RGB_DRV_DATA(s + 1)->calibration_mode) {
 		atime = TCS_CALIBRATION_ATIME;
 		again = TCS_CALIBRATION_AGAIN;
 	} else {
-		atime = TCS3400_RGB_DRV_DATA(s+1)->saturation.atime;
-		again = TCS3400_RGB_DRV_DATA(s+1)->saturation.again;
+		atime = TCS3400_RGB_DRV_DATA(s + 1)->saturation.atime;
+		again = TCS3400_RGB_DRV_DATA(s + 1)->saturation.again;
 	}
 	ret = tcs3400_i2c_write8(s, TCS_I2C_ATIME, atime);
 	if (ret)
@@ -114,16 +93,10 @@ static int tcs3400_read(const struct motion_sensor_t *s, intv3_t v)
 	if (ret)
 		return ret;
 
-	if (IS_ENABLED(CONFIG_ALS_TCS3400_EMULATED_IRQ_EVENT)) {
-		int atime;
-
-		ret = tcs3400_i2c_read8(s, TCS_I2C_ATIME, &atime);
-		if (ret)
-			return ret;
-
-		hook_call_deferred(&tcs3400_read_deferred_data,
-				tcs3400_get_integration_time(atime));
-	}
+#ifdef CONFIG_ALS_TCS3400_EMULATED_IRQ_EVENT
+	hook_call_deferred(&tcs3400_read_deferred_data,
+			   tcs3400_get_integration_time(atime));
+#endif
 
 	/*
 	 * If write succeeded, we've started the read process, but can't
@@ -153,25 +126,20 @@ static int tcs3400_rgb_read(const struct motion_sensor_t *s, intv3_t v)
  * AGAIN if it is not already at its maximum, or if it is, decrease
  * ATIME if it is not at it's minimum already.
  */
-static int
-tcs3400_adjust_sensor_for_saturation(struct motion_sensor_t *s,
-				     uint16_t cur_lux,
-				     uint16_t *crgb_data)
+static int tcs3400_adjust_sensor_for_saturation(struct motion_sensor_t *s,
+						uint16_t cur_lux,
+						uint16_t *crgb_data,
+						uint32_t status)
 {
 	struct tcs_saturation_t *sat_p =
-			&TCS3400_RGB_DRV_DATA(s+1)->saturation;
+		&TCS3400_RGB_DRV_DATA(s + 1)->saturation;
 	const uint8_t save_again = sat_p->again;
 	const uint8_t save_atime = sat_p->atime;
-	uint16_t max_val =  0;
+	uint16_t max_val = 0;
 	int ret;
-	int status = 0;
 	int percent_left = 0;
 
 	/* Adjust for saturation if needed */
-	ret = tcs3400_i2c_read8(s, TCS_I2C_STATUS, &status);
-	if (ret)
-		return ret;
-
 	if (!(status & TCS_I2C_STATUS_RGBC_VALID))
 		return EC_SUCCESS;
 
@@ -180,7 +148,7 @@ tcs3400_adjust_sensor_for_saturation(struct motion_sensor_t *s,
 
 	/* Don't process if status isn't valid yet */
 	if ((status & TCS_I2C_STATUS_ALS_SATURATED) ||
-			(max_val >= TCS_SATURATION_LEVEL)) {
+	    (max_val >= TCS_SATURATION_LEVEL)) {
 		/* Saturation occurred, decrease AGAIN if we can */
 		if (sat_p->again > TCS_MIN_AGAIN)
 			sat_p->again--;
@@ -197,14 +165,15 @@ tcs3400_adjust_sensor_for_saturation(struct motion_sensor_t *s,
 				 * increase accumulation time by decrementing
 				 * ATIME register
 				 */
-				percent_left = TSC_SATURATION_LOW_BAND_PERCENT -
+				percent_left =
+					TSC_SATURATION_LOW_BAND_PERCENT -
 					(max_val * 100 / TCS_SATURATION_LEVEL);
 				decrement_atime(sat_p, cur_lux, percent_left);
 			}
 		} else if (sat_p->atime > TCS_MIN_ATIME) {
 			/* calculate percentage between current and desired */
 			percent_left = TSC_SATURATION_LOW_BAND_PERCENT -
-				(max_val * 100 / TCS_SATURATION_LEVEL);
+				       (max_val * 100 / TCS_SATURATION_LEVEL);
 
 			/* increase accumulation time by decrementing ATIME */
 			decrement_atime(sat_p, cur_lux, percent_left);
@@ -231,7 +200,7 @@ tcs3400_adjust_sensor_for_saturation(struct motion_sensor_t *s,
 	/* If atime or gain setting changed, update atime and gain registers */
 	if (save_again != sat_p->again) {
 		ret = tcs3400_i2c_write8(s, TCS_I2C_CONTROL,
-				(sat_p->again & TCS_I2C_CONTROL_MASK));
+					 (sat_p->again & TCS_I2C_CONTROL_MASK));
 		if (ret)
 			return ret;
 	}
@@ -242,7 +211,7 @@ tcs3400_adjust_sensor_for_saturation(struct motion_sensor_t *s,
 			return ret;
 	}
 
-	return ret;
+	return EC_SUCCESS;
 }
 
 /**
@@ -250,32 +219,38 @@ tcs3400_adjust_sensor_for_saturation(struct motion_sensor_t *s,
  * different atime and again settings from the sample.
  */
 static uint32_t normalize_channel_data(struct motion_sensor_t *s,
-					uint32_t  sample)
+				       uint32_t sample)
 {
 	struct tcs_saturation_t *sat_p =
-				&(TCS3400_RGB_DRV_DATA(s+1)->saturation);
+		&(TCS3400_RGB_DRV_DATA(s + 1)->saturation);
 	const uint16_t cur_gain = (1 << (2 * sat_p->again));
 	const uint16_t cal_again = (1 << (2 * TCS_CALIBRATION_AGAIN));
 
-	return DIV_ROUND_NEAREST(sample * (TCS_ATIME_GRANULARITY -
-				TCS_CALIBRATION_ATIME) * cal_again,
-				(TCS_ATIME_GRANULARITY - sat_p->atime) *
-				cur_gain);
+	return DIV_ROUND_NEAREST(
+		sample * (TCS_ATIME_GRANULARITY - TCS_CALIBRATION_ATIME) *
+			cal_again,
+		(TCS_ATIME_GRANULARITY - sat_p->atime) * cur_gain);
 }
 
-
-static void tcs3400_translate_to_xyz(struct motion_sensor_t *s,
-				     int32_t *crgb_data, int32_t *xyz_data)
+__overridable void tcs3400_translate_to_xyz(struct motion_sensor_t *s,
+					    int32_t *crgb_data,
+					    int32_t *xyz_data)
 {
-	struct tcs3400_rgb_drv_data_t *rgb_drv_data = TCS3400_RGB_DRV_DATA(s+1);
+	struct tcs3400_rgb_drv_data_t *rgb_drv_data =
+		TCS3400_RGB_DRV_DATA(s + 1);
 	int32_t crgb_prime[CRGB_COUNT];
 	int32_t ir;
 	int i;
 
+	/* normalize the data for atime and again changes */
+	for (i = 0; i < CRGB_COUNT; i++)
+		crgb_data[i] = normalize_channel_data(s, crgb_data[i]);
+
 	/* IR removal */
 	ir = FP_TO_INT(fp_mul(INT_TO_FP(crgb_data[1] + crgb_data[2] +
-			      crgb_data[3] - crgb_data[0]),
-			      rgb_drv_data->calibration.irt) / 2);
+					crgb_data[3] - crgb_data[0]),
+			      rgb_drv_data->calibration.irt) /
+		       2);
 
 	for (i = 0; i < ARRAY_SIZE(crgb_prime); i++) {
 		if (crgb_data[i] < ir)
@@ -291,17 +266,17 @@ static void tcs3400_translate_to_xyz(struct motion_sensor_t *s,
 	/* regression fit to XYZ space */
 	for (i = 0; i < 3; i++) {
 		const struct rgb_channel_calibration_t *p =
-				&rgb_drv_data->calibration.rgb_cal[i];
-
-		xyz_data[i] = p->offset + FP_TO_INT(
-			(fp_inter_t)p->coeff[RED_CRGB_IDX] *
-					crgb_prime[RED_CRGB_IDX] +
-			(fp_inter_t)p->coeff[GREEN_CRGB_IDX] *
-					crgb_prime[GREEN_CRGB_IDX] +
-			(fp_inter_t)p->coeff[BLUE_CRGB_IDX] *
-					crgb_prime[BLUE_CRGB_IDX] +
-			(fp_inter_t)p->coeff[CLEAR_CRGB_IDX] *
-					crgb_prime[CLEAR_CRGB_IDX]);
+			&rgb_drv_data->calibration.rgb_cal[i];
+
+		xyz_data[i] = p->offset +
+			      FP_TO_INT((fp_inter_t)p->coeff[RED_CRGB_IDX] *
+						crgb_prime[RED_CRGB_IDX] +
+					(fp_inter_t)p->coeff[GREEN_CRGB_IDX] *
+						crgb_prime[GREEN_CRGB_IDX] +
+					(fp_inter_t)p->coeff[BLUE_CRGB_IDX] *
+						crgb_prime[BLUE_CRGB_IDX] +
+					(fp_inter_t)p->coeff[CLEAR_CRGB_IDX] *
+						crgb_prime[CLEAR_CRGB_IDX]);
 
 		if (xyz_data[i] < 0)
 			xyz_data[i] = 0;
@@ -309,14 +284,16 @@ static void tcs3400_translate_to_xyz(struct motion_sensor_t *s,
 }
 
 static void tcs3400_process_raw_data(struct motion_sensor_t *s,
-				    uint8_t *raw_data_buf,
-				    uint16_t *raw_light_data, int32_t *xyz_data)
+				     uint8_t *raw_data_buf,
+				     uint16_t *raw_light_data,
+				     int32_t *xyz_data)
 {
 	struct als_drv_data_t *als_drv_data = TCS3400_DRV_DATA(s);
-	struct tcs3400_rgb_drv_data_t *rgb_drv_data = TCS3400_RGB_DRV_DATA(s+1);
+	struct tcs3400_rgb_drv_data_t *rgb_drv_data =
+		TCS3400_RGB_DRV_DATA(s + 1);
 	const uint8_t calibration_mode = rgb_drv_data->calibration_mode;
-	uint16_t  k_channel_scale =
-			als_drv_data->als_cal.channel_scale.k_channel_scale;
+	uint16_t k_channel_scale =
+		als_drv_data->als_cal.channel_scale.k_channel_scale;
 	uint16_t cover_scale = als_drv_data->als_cal.channel_scale.cover_scale;
 	int32_t crgb_data[CRGB_COUNT];
 	int i;
@@ -327,7 +304,7 @@ static void tcs3400_process_raw_data(struct motion_sensor_t *s,
 
 		/* assemble the light value for this channel */
 		crgb_data[i] = raw_light_data[i] =
-			((raw_data_buf[index+1] << 8) | raw_data_buf[index]);
+			((raw_data_buf[index + 1] << 8) | raw_data_buf[index]);
 
 		/* in calibration mode, we only assemble the raw data */
 		if (calibration_mode)
@@ -336,29 +313,30 @@ static void tcs3400_process_raw_data(struct motion_sensor_t *s,
 		/* rgb data at index 1, 2, and 3 owned by rgb driver, not ALS */
 		if (i > 0) {
 			struct als_channel_scale_t *csp =
-				&rgb_drv_data->calibration.rgb_cal[i-1].scale;
+				&rgb_drv_data->calibration.rgb_cal[i - 1].scale;
 			k_channel_scale = csp->k_channel_scale;
 			cover_scale = csp->cover_scale;
 		}
 
 		/* Step 1: divide by individual channel scale value */
-		crgb_data[i] = SENSOR_APPLY_DIV_SCALE(crgb_data[i],
-							k_channel_scale);
+		crgb_data[i] =
+			SENSOR_APPLY_DIV_SCALE(crgb_data[i], k_channel_scale);
 
 		/* compensate for the light cover */
 		crgb_data[i] = SENSOR_APPLY_SCALE(crgb_data[i], cover_scale);
-
-		/* normalize the data for atime and again changes */
-		crgb_data[i] = normalize_channel_data(s, crgb_data[i]);
 	}
 
 	if (!calibration_mode) {
 		/* we're not in calibration mode & we want xyz translation */
 		tcs3400_translate_to_xyz(s, crgb_data, xyz_data);
 	} else {
+		/* normalize the data for atime and again changes */
+		for (i = 0; i < CRGB_COUNT; i++)
+			crgb_data[i] = normalize_channel_data(s, crgb_data[i]);
+
 		/* calibration mode returns raw data */
 		for (i = 0; i < 3; i++)
-			xyz_data[i] = crgb_data[i+1];
+			xyz_data[i] = crgb_data[i + 1];
 	}
 }
 
@@ -366,7 +344,7 @@ static int32_t get_lux_from_xyz(struct motion_sensor_t *s, int32_t *xyz_data)
 {
 	int32_t lux = xyz_data[Y];
 	const int32_t offset =
-		TCS3400_RGB_DRV_DATA(s+1)->calibration.rgb_cal[Y].offset;
+		TCS3400_RGB_DRV_DATA(s + 1)->calibration.rgb_cal[Y].offset;
 
 	/*
 	 * Do not include the offset when determining LUX from XYZ.
@@ -382,7 +360,8 @@ static bool is_spoof(struct motion_sensor_t *s)
 	       (s->flags & MOTIONSENSE_FLAG_IN_SPOOF_MODE);
 }
 
-static int tcs3400_post_events(struct motion_sensor_t *s, uint32_t last_ts)
+static int tcs3400_post_events(struct motion_sensor_t *s, uint32_t last_ts,
+			       uint32_t status)
 {
 	/*
 	 * Rule says RGB sensor is right after ALS sensor.
@@ -390,34 +369,39 @@ static int tcs3400_post_events(struct motion_sensor_t *s, uint32_t last_ts)
 	 */
 	struct motion_sensor_t *rgb_s = s + 1;
 	const uint8_t is_calibration =
-			TCS3400_RGB_DRV_DATA(rgb_s)->calibration_mode;
-	struct ec_response_motion_sensor_data vector = { .flags = 0, };
+		TCS3400_RGB_DRV_DATA(rgb_s)->calibration_mode;
 	uint8_t buf[TCS_RGBC_DATA_SIZE]; /* holds raw data read from chip */
 	int32_t xyz_data[3] = { 0, 0, 0 };
 	uint16_t raw_data[CRGB_COUNT]; /* holds raw CRGB assembled from buf[] */
 	int *last_v;
-	int32_t lux, data = 0;
-	int i, ret;
+	int32_t lux = 0;
+	int ret;
 
-	i = 20;	/* 400ms max */
-	while (i--) {
-		/* Make sure data is valid */
-		ret = tcs3400_i2c_read8(s, TCS_I2C_STATUS, &data);
-		if (ret)
-			return ret;
-		if (data & TCS_I2C_STATUS_RGBC_VALID)
-			break;
-		msleep(20);
-	}
-	if (i < 0) {
-		CPRINTS("RGBC invalid (0x%x)", data);
-		return EC_ERROR_UNCHANGED;
+	if (IS_ENABLED(CONFIG_ALS_TCS3400_EMULATED_IRQ_EVENT)) {
+		int i = 5; /* 100ms max */
+
+		while (i--) {
+			/* Make sure data is valid */
+			if (status & TCS_I2C_STATUS_RGBC_VALID)
+				break;
+			msleep(20);
+			/*
+			 * When not in interrupt mode, we could have scheduled
+			 * the handler too early.
+			 */
+			ret = tcs3400_i2c_read8(s, TCS_I2C_STATUS, &status);
+			if (ret)
+				return ret;
+		}
+		if (i < 0) {
+			CPRINTS("RGBC invalid (0x%x)", status);
+			return EC_ERROR_UNCHANGED;
+		}
 	}
 
 	/* Read the light registers */
 	ret = i2c_read_block(s->port, s->i2c_spi_addr_flags,
-			TCS_DATA_START_LOCATION,
-			buf, sizeof(buf));
+			     TCS_DATA_START_LOCATION, buf, sizeof(buf));
 	if (ret)
 		return ret;
 
@@ -429,20 +413,28 @@ static int tcs3400_post_events(struct motion_sensor_t *s, uint32_t last_ts)
 
 	/* if clear channel data changed, send illuminance upstream */
 	last_v = s->raw_xyz;
-	if ((raw_data[CLEAR_CRGB_IDX] != TCS_SATURATION_LEVEL) &&
-	    (last_v[X] != lux)) {
+	if (is_calibration ||
+	    ((raw_data[CLEAR_CRGB_IDX] != TCS_SATURATION_LEVEL) &&
+	     (last_v[X] != lux))) {
 		if (is_spoof(s))
 			last_v[X] = s->spoof_xyz[X];
 		else
-			last_v[X] = is_calibration ? raw_data[CLEAR_CRGB_IDX] : lux;
-
-		vector.udata[X] = ec_motion_sensor_clamp_u16(last_v[X]);
-		vector.udata[Y] = 0;
-		vector.udata[Z] = 0;
+			last_v[X] = is_calibration ? raw_data[CLEAR_CRGB_IDX] :
+						     lux;
 
 		if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
+			struct ec_response_motion_sensor_data vector = {
+				.flags = 0,
+			};
+
+			vector.udata[X] = ec_motion_sensor_clamp_u16(last_v[X]);
+			vector.udata[Y] = 0;
+			vector.udata[Z] = 0;
+
 			vector.sensor_num = s - motion_sensors;
 			motion_sense_fifo_stage_data(&vector, s, 3, last_ts);
+		} else {
+			motion_sense_push_raw_xyz(s);
 		}
 	}
 
@@ -451,14 +443,15 @@ static int tcs3400_post_events(struct motion_sensor_t *s, uint32_t last_ts)
 	 * send it upstream
 	 */
 	last_v = rgb_s->raw_xyz;
-	if (((last_v[X] != xyz_data[X]) || (last_v[Y] != xyz_data[Y]) ||
-		(last_v[Z] != xyz_data[Z])) &&
-		((raw_data[RED_CRGB_IDX] != TCS_SATURATION_LEVEL) &&
-		(raw_data[BLUE_CRGB_IDX] != TCS_SATURATION_LEVEL) &&
-		(raw_data[GREEN_CRGB_IDX] != TCS_SATURATION_LEVEL))) {
-
+	if (is_calibration ||
+	    (((last_v[X] != xyz_data[X]) || (last_v[Y] != xyz_data[Y]) ||
+	      (last_v[Z] != xyz_data[Z])) &&
+	     ((raw_data[RED_CRGB_IDX] != TCS_SATURATION_LEVEL) &&
+	      (raw_data[BLUE_CRGB_IDX] != TCS_SATURATION_LEVEL) &&
+	      (raw_data[GREEN_CRGB_IDX] != TCS_SATURATION_LEVEL)))) {
 		if (is_spoof(rgb_s)) {
-			memcpy(last_v, rgb_s->spoof_xyz, sizeof(rgb_s->spoof_xyz));
+			memcpy(last_v, rgb_s->spoof_xyz,
+			       sizeof(rgb_s->spoof_xyz));
 		} else if (is_calibration) {
 			last_v[0] = raw_data[RED_CRGB_IDX];
 			last_v[1] = raw_data[GREEN_CRGB_IDX];
@@ -467,11 +460,19 @@ static int tcs3400_post_events(struct motion_sensor_t *s, uint32_t last_ts)
 			memcpy(last_v, xyz_data, sizeof(xyz_data));
 		}
 
-		ec_motion_sensor_clamp_u16s(vector.udata, last_v);
-
 		if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
+			struct ec_response_motion_sensor_data vector = {
+				.flags = 0,
+			};
+			void *udata = vector.udata;
+
+			ec_motion_sensor_clamp_u16s(udata, last_v);
+
 			vector.sensor_num = rgb_s - motion_sensors;
-			motion_sense_fifo_stage_data(&vector, rgb_s, 3, last_ts);
+			motion_sense_fifo_stage_data(&vector, rgb_s, 3,
+						     last_ts);
+		} else {
+			motion_sense_push_raw_xyz(rgb_s);
 		}
 	}
 	if (IS_ENABLED(CONFIG_ACCEL_FIFO))
@@ -479,20 +480,11 @@ static int tcs3400_post_events(struct motion_sensor_t *s, uint32_t last_ts)
 
 	if (!is_calibration)
 		ret = tcs3400_adjust_sensor_for_saturation(s, xyz_data[Y],
-							   raw_data);
+							   raw_data, status);
 
 	return ret;
 }
 
-void tcs3400_interrupt(enum gpio_signal signal)
-{
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO))
-		last_interrupt_timestamp = __hw_clock_source_read();
-
-	task_set_event(TASK_ID_MOTIONSENSE,
-		       CONFIG_ALS_TCS3400_INT_EVENT, 0);
-}
-
 /*
  * tcs3400_irq_handler - bottom half of the interrupt stack.
  * Ran from the motion_sense task, finds the events that raised the interrupt,
@@ -505,8 +497,8 @@ void tcs3400_interrupt(enum gpio_signal signal)
  */
 static int tcs3400_irq_handler(struct motion_sensor_t *s, uint32_t *event)
 {
-	int status = 0;
-	int ret = EC_SUCCESS;
+	uint32_t status = 0;
+	int ret;
 
 	if (!(*event & CONFIG_ALS_TCS3400_INT_EVENT))
 		return EC_ERROR_NOT_HANDLED;
@@ -521,10 +513,8 @@ static int tcs3400_irq_handler(struct motion_sensor_t *s, uint32_t *event)
 		return ret;
 
 	if ((status & TCS_I2C_STATUS_RGBC_VALID) ||
-			((status & TCS_I2C_STATUS_ALS_IRQ) &&
-			(status & TCS_I2C_STATUS_ALS_SATURATED)) ||
-			IS_ENABLED(CONFIG_ALS_TCS3400_EMULATED_IRQ_EVENT)) {
-		ret = tcs3400_post_events(s, last_interrupt_timestamp);
+	    IS_ENABLED(CONFIG_ALS_TCS3400_EMULATED_IRQ_EVENT)) {
+		ret = tcs3400_post_events(s, last_interrupt_timestamp, status);
 		if (ret)
 			return ret;
 	}
@@ -536,15 +526,14 @@ static int tcs3400_irq_handler(struct motion_sensor_t *s, uint32_t *event)
 	if (ret)
 		return ret;
 
-	return ret;
+	return EC_SUCCESS;
 }
 
 static int tcs3400_rgb_get_scale(const struct motion_sensor_t *s,
-				 uint16_t *scale,
-				 int16_t *temp)
+				 uint16_t *scale, int16_t *temp)
 {
 	struct rgb_channel_calibration_t *rgb_cal =
-			TCS3400_RGB_DRV_DATA(s)->calibration.rgb_cal;
+		TCS3400_RGB_DRV_DATA(s)->calibration.rgb_cal;
 
 	scale[X] = rgb_cal[RED_RGB_IDX].scale.k_channel_scale;
 	scale[Y] = rgb_cal[GREEN_RGB_IDX].scale.k_channel_scale;
@@ -554,11 +543,10 @@ static int tcs3400_rgb_get_scale(const struct motion_sensor_t *s,
 }
 
 static int tcs3400_rgb_set_scale(const struct motion_sensor_t *s,
-				 const uint16_t *scale,
-				 int16_t temp)
+				 const uint16_t *scale, int16_t temp)
 {
 	struct rgb_channel_calibration_t *rgb_cal =
-			TCS3400_RGB_DRV_DATA(s)->calibration.rgb_cal;
+		TCS3400_RGB_DRV_DATA(s)->calibration.rgb_cal;
 
 	if (scale[X] == 0 || scale[Y] == 0 || scale[Z] == 0)
 		return EC_ERROR_INVAL;
@@ -569,8 +557,7 @@ static int tcs3400_rgb_set_scale(const struct motion_sensor_t *s,
 }
 
 static int tcs3400_rgb_get_offset(const struct motion_sensor_t *s,
-				  int16_t *offset,
-				  int16_t *temp)
+				  int16_t *offset, int16_t *temp)
 {
 	offset[X] = TCS3400_RGB_DRV_DATA(s)->calibration.rgb_cal[X].offset;
 	offset[Y] = TCS3400_RGB_DRV_DATA(s)->calibration.rgb_cal[Y].offset;
@@ -580,51 +567,40 @@ static int tcs3400_rgb_get_offset(const struct motion_sensor_t *s,
 }
 
 static int tcs3400_rgb_set_offset(const struct motion_sensor_t *s,
-				  const int16_t *offset,
-				  int16_t temp)
+				  const int16_t *offset, int16_t temp)
 {
 	/* do not allow offset to be changed, it's predetermined */
 	return EC_SUCCESS;
 }
 
-static int tcs3400_rgb_get_data_rate(const struct motion_sensor_t *s)
-{
-	return 0;
-}
-
-static int tcs3400_rgb_set_data_rate(const struct motion_sensor_t *s,
-				     int rate,
+static int tcs3400_rgb_set_data_rate(const struct motion_sensor_t *s, int rate,
 				     int rnd)
 {
 	return EC_SUCCESS;
 }
 
 /* Enable/disable special factory calibration mode */
-static int tcs3400_perform_calib(const struct motion_sensor_t *s,
-				     int enable)
+static int tcs3400_perform_calib(struct motion_sensor_t *s, int enable)
 {
-	TCS3400_RGB_DRV_DATA(s+1)->calibration_mode = enable;
+	TCS3400_RGB_DRV_DATA(s + 1)->calibration_mode = enable;
 	return EC_SUCCESS;
 }
 
-static int tcs3400_get_range(const struct motion_sensor_t *s)
+static int tcs3400_rgb_set_range(struct motion_sensor_t *s, int range, int rnd)
 {
-	return (TCS3400_DRV_DATA(s)->als_cal.scale << 16) |
-			(TCS3400_DRV_DATA(s)->als_cal.uscale);
+	return EC_SUCCESS;
 }
 
-static int tcs3400_set_range(const struct motion_sensor_t *s,
-			     int range,
-			     int rnd)
+static int tcs3400_set_range(struct motion_sensor_t *s, int range, int rnd)
 {
 	TCS3400_DRV_DATA(s)->als_cal.scale = range >> 16;
 	TCS3400_DRV_DATA(s)->als_cal.uscale = range & 0xffff;
+	s->current_range = range;
 	return EC_SUCCESS;
 }
 
-static int tcs3400_get_scale(const struct motion_sensor_t *s,
-				 uint16_t *scale,
-				 int16_t *temp)
+static int tcs3400_get_scale(const struct motion_sensor_t *s, uint16_t *scale,
+			     int16_t *temp)
 {
 	scale[X] = TCS3400_DRV_DATA(s)->als_cal.channel_scale.k_channel_scale;
 	scale[Y] = 0;
@@ -634,8 +610,7 @@ static int tcs3400_get_scale(const struct motion_sensor_t *s,
 }
 
 static int tcs3400_set_scale(const struct motion_sensor_t *s,
-				 const uint16_t *scale,
-				 int16_t temp)
+			     const uint16_t *scale, int16_t temp)
 {
 	if (scale[X] == 0)
 		return EC_ERROR_INVAL;
@@ -643,8 +618,7 @@ static int tcs3400_set_scale(const struct motion_sensor_t *s,
 	return EC_SUCCESS;
 }
 
-static int tcs3400_get_offset(const struct motion_sensor_t *s,
-			      int16_t *offset,
+static int tcs3400_get_offset(const struct motion_sensor_t *s, int16_t *offset,
 			      int16_t *temp)
 {
 	offset[X] = TCS3400_DRV_DATA(s)->als_cal.offset;
@@ -655,8 +629,7 @@ static int tcs3400_get_offset(const struct motion_sensor_t *s,
 }
 
 static int tcs3400_set_offset(const struct motion_sensor_t *s,
-			      const int16_t *offset,
-			      int16_t temp)
+			      const int16_t *offset, int16_t temp)
 {
 	/* do not allow offset to be changed, it's predetermined */
 	return EC_SUCCESS;
@@ -667,8 +640,12 @@ static int tcs3400_get_data_rate(const struct motion_sensor_t *s)
 	return TCS3400_DRV_DATA(s)->rate;
 }
 
-static int tcs3400_set_data_rate(const struct motion_sensor_t *s,
-				 int rate,
+static int tcs3400_rgb_get_data_rate(const struct motion_sensor_t *s)
+{
+	return tcs3400_get_data_rate(s - 1);
+}
+
+static int tcs3400_set_data_rate(const struct motion_sensor_t *s, int rate,
 				 int rnd)
 {
 	enum tcs3400_mode mode;
@@ -703,12 +680,12 @@ static int tcs3400_set_data_rate(const struct motion_sensor_t *s,
 /**
  * Initialise TCS3400 light sensor.
  */
-static int tcs3400_rgb_init(const struct motion_sensor_t *s)
+static int tcs3400_rgb_init(struct motion_sensor_t *s)
 {
 	return EC_SUCCESS;
 }
 
-static int tcs3400_init(const struct motion_sensor_t *s)
+static int tcs3400_init(struct motion_sensor_t *s)
 {
 	/*
 	 * These are default power-on register values with two exceptions:
@@ -718,22 +695,21 @@ static int tcs3400_init(const struct motion_sensor_t *s)
 	const struct reg_data {
 		uint8_t reg;
 		uint8_t data;
-	} defaults[] = {
-		{ TCS_I2C_ENABLE, 0 },
-		{ TCS_I2C_ATIME, TCS_DEFAULT_ATIME },
-		{ TCS_I2C_WTIME, 0xFF },
-		{ TCS_I2C_AILTL, 0 },
-		{ TCS_I2C_AILTH, 0 },
-		{ TCS_I2C_AIHTL, 0 },
-		{ TCS_I2C_AIHTH, 0 },
-		{ TCS_I2C_PERS, 0 },
-		{ TCS_I2C_CONFIG, 0x40 },
-		{ TCS_I2C_CONTROL, (TCS_DEFAULT_AGAIN & TCS_I2C_CONTROL_MASK) },
-		{ TCS_I2C_AUX, 0 },
-		{ TCS_I2C_IR, 0 },
-		{ TCS_I2C_CICLEAR, 0 },
-		{ TCS_I2C_AICLEAR, 0 }
-	};
+	} defaults[] = { { TCS_I2C_ENABLE, 0 },
+			 { TCS_I2C_ATIME, TCS_DEFAULT_ATIME },
+			 { TCS_I2C_WTIME, 0xFF },
+			 { TCS_I2C_AILTL, 0 },
+			 { TCS_I2C_AILTH, 0 },
+			 { TCS_I2C_AIHTL, 0 },
+			 { TCS_I2C_AIHTH, 0 },
+			 { TCS_I2C_PERS, 0 },
+			 { TCS_I2C_CONFIG, 0x40 },
+			 { TCS_I2C_CONTROL,
+			   (TCS_DEFAULT_AGAIN & TCS_I2C_CONTROL_MASK) },
+			 { TCS_I2C_AUX, 0 },
+			 { TCS_I2C_IR, 0 },
+			 { TCS_I2C_CICLEAR, 0 },
+			 { TCS_I2C_AICLEAR, 0 } };
 	int data = 0;
 	int ret;
 
@@ -761,7 +737,6 @@ const struct accelgyro_drv tcs3400_drv = {
 	.init = tcs3400_init,
 	.read = tcs3400_read,
 	.set_range = tcs3400_set_range,
-	.get_range = tcs3400_get_range,
 	.set_offset = tcs3400_set_offset,
 	.get_offset = tcs3400_get_offset,
 	.set_scale = tcs3400_set_scale,
@@ -769,7 +744,7 @@ const struct accelgyro_drv tcs3400_drv = {
 	.set_data_rate = tcs3400_set_data_rate,
 	.get_data_rate = tcs3400_get_data_rate,
 	.perform_calib = tcs3400_perform_calib,
-#ifdef CONFIG_ACCEL_INTERRUPTS
+#ifdef ALS_TCS3400_INT_ENABLE
 	.irq_handler = tcs3400_irq_handler,
 #endif
 };
@@ -777,6 +752,7 @@ const struct accelgyro_drv tcs3400_drv = {
 const struct accelgyro_drv tcs3400_rgb_drv = {
 	.init = tcs3400_rgb_init,
 	.read = tcs3400_rgb_read,
+	.set_range = tcs3400_rgb_set_range,
 	.set_offset = tcs3400_rgb_set_offset,
 	.get_offset = tcs3400_rgb_get_offset,
 	.set_scale = tcs3400_rgb_set_scale,
diff --git a/driver/als_tcs3400.h b/driver/als_tcs3400.h
deleted file mode 100644
index 892b4881fd..0000000000
--- a/driver/als_tcs3400.h
+++ /dev/null
@@ -1,179 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * AMS TCS3400 light sensor driver
- */
-
-#ifndef __CROS_EC_ALS_TCS3400_H
-#define __CROS_EC_ALS_TCS3400_H
-
-/* I2C Interface */
-#define TCS3400_I2C_ADDR_FLAGS	0x39
-
-/* ID for TCS34001 and TCS34005 */
-#define TCS340015_DEVICE_ID	0x90
-
-/* ID for TCS34003 and TCS34007 */
-#define TCS340037_DEVICE_ID	0x93
-
-/* Register Map */
-#define TCS_I2C_ENABLE    0x80    /* R/W Enables states and interrupts */
-#define TCS_I2C_ATIME     0x81    /* R/W RGBC integration time */
-#define TCS_I2C_WTIME     0x83    /* R/W Wait time */
-#define TCS_I2C_AILTL     0x84    /* R/W Clear irq low threshold low byte */
-#define TCS_I2C_AILTH     0x85    /* R/W Clear irq low threshold high byte */
-#define TCS_I2C_AIHTL     0x86    /* R/W Clear irq high threshold low byte */
-#define TCS_I2C_AIHTH     0x87    /* R/W Clear irq high threshold high byte */
-#define TCS_I2C_PERS      0x8C    /* R/W Interrupt persistence filter */
-#define TCS_I2C_CONFIG    0x8D    /* R/W Configuration */
-#define TCS_I2C_CONTROL   0x8F    /* R/W Gain control register */
-#define TCS_I2C_AUX       0x90    /* R/W Auxiliary control register */
-#define TCS_I2C_REVID     0x91    /* R Revision ID */
-#define TCS_I2C_ID        0x92    /* R Device ID */
-#define TCS_I2C_STATUS    0x93    /* R Device status */
-#define TCS_I2C_CDATAL    0x94    /* R Clear / IR channel low data register */
-#define TCS_I2C_CDATAH    0x95    /* R Clear / IR channel high data register */
-#define TCS_I2C_RDATAL    0x96    /* R Red ADC low data register */
-#define TCS_I2C_RDATAH    0x97    /* R Red ADC high data register */
-#define TCS_I2C_GDATAL    0x98    /* R Green ADC low data register */
-#define TCS_I2C_GDATAH    0x99    /* R Green ADC high data register */
-#define TCS_I2C_BDATAL    0x9A    /* R Blue ADC low data register */
-#define TCS_I2C_BDATAH    0x9B    /* R Blue ADC high data register */
-#define TCS_I2C_IR        0xC0    /* R/W Access IR Channel */
-#define TCS_I2C_IFORCE    0xE4    /* W Force Interrupt */
-#define TCS_I2C_CICLEAR   0xE6    /* W Clear channel interrupt clear */
-#define TCS_I2C_AICLEAR   0xE7    /* W Clear all interrupts */
-
-#define TCS_I2C_ENABLE_POWER_ON             BIT(0)
-#define TCS_I2C_ENABLE_ADC_ENABLE           BIT(1)
-#define TCS_I2C_ENABLE_WAIT_ENABLE          BIT(3)
-#define TCS_I2C_ENABLE_INT_ENABLE           BIT(4)
-#define TCS_I2C_ENABLE_SLEEP_AFTER_INT      BIT(6)
-#define TCS_I2C_ENABLE_MASK                 (TCS_I2C_ENABLE_POWER_ON |    \
-					     TCS_I2C_ENABLE_ADC_ENABLE |  \
-					     TCS_I2C_ENABLE_WAIT_ENABLE | \
-					     TCS_I2C_ENABLE_INT_ENABLE |  \
-					     TCS_I2C_ENABLE_SLEEP_AFTER_INT)
-
-enum tcs3400_mode {
-	TCS3400_MODE_SUSPEND = 0,
-	TCS3400_MODE_IDLE =       (TCS_I2C_ENABLE_POWER_ON |
-				   TCS_I2C_ENABLE_ADC_ENABLE),
-	TCS3400_MODE_COLLECTING = (TCS_I2C_ENABLE_POWER_ON |
-				   TCS_I2C_ENABLE_ADC_ENABLE |
-				   TCS_I2C_ENABLE_INT_ENABLE),
-};
-
-#define TCS_I2C_CONTROL_MASK                0x03
-#define TCS_I2C_STATUS_RGBC_VALID           BIT(0)
-#define TCS_I2C_STATUS_ALS_IRQ              BIT(4)
-#define TCS_I2C_STATUS_ALS_SATURATED        BIT(7)
-
-#define TCS_I2C_AUX_ASL_INT_ENABLE          BIT(5)
-
-/* Light data resides at 0x94 thru 0x98 */
-#define TCS_DATA_START_LOCATION             TCS_I2C_CDATAL
-#define TCS_CLEAR_DATA_SIZE                 2
-#define TCS_RGBC_DATA_SIZE                  8
-
-/* Min and Max sampling frequency in mHz */
-#define TCS3400_LIGHT_MIN_FREQ              149
-#define TCS3400_LIGHT_MAX_FREQ              1000
-#if (CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ <= TCS3400_LIGHT_MAX_FREQ)
-#error "EC too slow for light sensor"
-#endif
-
-#define TCS3400_DRV_DATA(_s) ((struct als_drv_data_t *)(_s)->drv_data)
-#define TCS3400_RGB_DRV_DATA(_s) \
-	((struct tcs3400_rgb_drv_data_t *)(_s)->drv_data)
-
-/* NOTE: The higher the ATIME value in reg, the shorter the accumulation time */
-#define TCS_MIN_ATIME           0x00            /* 712 ms */
-#define TCS_MAX_ATIME           0x70            /* 400 ms */
-#define TCS_ATIME_GRANULARITY   256             /* 256 atime settings */
-#define TCS_SATURATION_LEVEL    0xffff          /* for 0 < atime < 0x70 */
-#define TCS_DEFAULT_ATIME       TCS_MIN_ATIME   /* 712 ms */
-#define TCS_CALIBRATION_ATIME   TCS_MIN_ATIME
-#define TCS_GAIN_UPSHIFT_ATIME  TCS_MAX_ATIME
-
-/* Number of different ranges supported for atime adjustment support */
-#define TCS_MAX_ATIME_RANGES    13
-#define TCS_GAIN_TABLE_MAX_LUX  12999
-#define TCS_ATIME_GAIN_FACTOR   100     /* table values are 100x actual value */
-
-#define TCS_MIN_AGAIN           0x00            /* 1x gain */
-#define TCS_MAX_AGAIN           0x03            /* 64x gain */
-#define TCS_CALIBRATION_AGAIN   0x02            /* 16x gain */
-#define TCS_DEFAULT_AGAIN       TCS_CALIBRATION_AGAIN
-
-#define TCS_ATIME_DEC_STEP      5
-#define TCS_ATIME_INC_STEP      TCS_GAIN_UPSHIFT_ATIME
-
-/*
- * Factor to multiply light value by to determine if an increase in gain
- * would cause the next value to saturate.
- *
- * On the TCS3400, gain increases 4x each time again register setting is
- * incremented.  However, I see cases where values that are 24% of saturation
- * go into saturation after increasing gain, causing a back-and-forth cycle to
- * occur :
- *
- * [134.654994 tcs3400_adjust_sensor_for_saturation value=65535 100% Gain=2 ]
- * [135.655064 tcs3400_adjust_sensor_for_saturation value=15750 24% Gain=1 ]
- * [136.655107 tcs3400_adjust_sensor_for_saturation value=65535 100% Gain=2 ]
- *
- * To avoid this, we require value to be <= 20% of saturation level
- * (TCS_GAIN_SAT_LEVEL) before allowing gain to be increased.
- */
-#define TCS_GAIN_ADJUST_FACTOR   5
-#define TCS_GAIN_SAT_LEVEL       (TCS_SATURATION_LEVEL / TCS_GAIN_ADJUST_FACTOR)
-#define TCS_UPSHIFT_FACTOR_N     25 /* upshift factor = 2.5 */
-#define TCS_UPSHIFT_FACTOR_D     10
-#define TCS_GAIN_UPSHIFT_LEVEL   (TCS_SATURATION_LEVEL * TCS_UPSHIFT_FACTOR_D \
-							/ TCS_UPSHIFT_FACTOR_N)
-
-/*
- * Percentage of saturation level that the auto-adjusting anti-saturation
- * method will drive towards.
- */
-#define TSC_SATURATION_LOW_BAND_PERCENT 90
-#define TSC_SATURATION_LOW_BAND_LEVEL   (TCS_SATURATION_LEVEL * \
-					 TSC_SATURATION_LOW_BAND_PERCENT / 100)
-
-enum crbg_index {
-	CLEAR_CRGB_IDX = 0,
-	RED_CRGB_IDX,
-	GREEN_CRGB_IDX,
-	BLUE_CRGB_IDX,
-	CRGB_COUNT,
-};
-
-/* saturation auto-adjustment */
-struct tcs_saturation_t {
-	/*
-	 * Gain Scaling; must be value between 0 and 3
-	 *      0 - 1x scaling
-	 *      1 - 4x scaling
-	 *      2 - 16x scaling
-	 *      3 - 64x scaling
-	 */
-	uint8_t again;
-
-	/* Acquisition Time, controlled by the ATIME register */
-	uint8_t atime;             /* ATIME register setting */
-};
-
-/* tcs3400 rgb als driver data */
-struct tcs3400_rgb_drv_data_t {
-	uint8_t calibration_mode;/* 0 = normal run mode, 1 = calibration mode */
-
-	struct rgb_calibration_t calibration;
-	struct tcs_saturation_t saturation;  /* saturation adjustment */
-};
-
-extern const struct accelgyro_drv tcs3400_drv;
-extern const struct accelgyro_drv tcs3400_rgb_drv;
-
-void tcs3400_interrupt(enum gpio_signal signal);
-#endif /* __CROS_EC_ALS_TCS3400_H */
diff --git a/driver/amd_stb.c b/driver/amd_stb.c
new file mode 100644
index 0000000000..9d847bb524
--- /dev/null
+++ b/driver/amd_stb.c
@@ -0,0 +1,77 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Driver for AMD STB dump functionality */
+#include "chipset.h"
+#include "driver/amd_stb.h"
+#include "hooks.h"
+
+#ifndef CONFIG_ZTEST
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
+#else
+#define CPRINTS(format, args...) printk(format, ##args)
+#endif
+
+static bool stb_dump_in_progress;
+static struct {
+	/* Interrupt from EC to AP. */
+	const struct gpio_dt_spec *int_out;
+	/* Interrupt from AP to EC. */
+	const struct gpio_dt_spec *int_in;
+} stb_dump_config;
+
+void amd_stb_dump_finish(void)
+{
+	gpio_pin_set_dt(stb_dump_config.int_out, 0);
+	stb_dump_in_progress = false;
+}
+
+void amd_stb_dump_trigger(void)
+{
+	if (stb_dump_in_progress || !stb_dump_config.int_out)
+		return;
+
+	CPRINTS("Triggering STB dump");
+	stb_dump_in_progress = true;
+	gpio_pin_set_dt(stb_dump_config.int_out, 1);
+}
+
+void amd_stb_dump_init(const struct gpio_dt_spec *int_out,
+		       const struct gpio_dt_spec *int_in)
+{
+	stb_dump_config.int_out = int_out;
+	stb_dump_config.int_in = int_in;
+}
+
+static void stb_dump_interrupt_deferred(void)
+{
+	/* AP has indicated that it has finished the dump. */
+	if (!stb_dump_in_progress)
+		return;
+
+	amd_stb_dump_finish();
+	CPRINTS("STB dump finished");
+}
+DECLARE_DEFERRED(stb_dump_interrupt_deferred);
+
+bool amd_stb_dump_in_progress(void)
+{
+	return stb_dump_in_progress;
+}
+
+void amd_stb_dump_interrupt(enum gpio_signal signal)
+{
+	hook_call_deferred(&stb_dump_interrupt_deferred_data, 0);
+}
+
+#ifdef CONFIG_PLATFORM_EC_AMD_STB_DUMP_CMD
+static int command_amdstbdump(int argc, const char **argv)
+{
+	amd_stb_dump_trigger();
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(amdstbdump, command_amdstbdump, NULL,
+			"Trigger an STB dump");
+#endif
diff --git a/driver/amd_stb.h b/driver/amd_stb.h
new file mode 100644
index 0000000000..5c339c66e5
--- /dev/null
+++ b/driver/amd_stb.h
@@ -0,0 +1,15 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include <stddef.h>
+
+#include <gpio_signal.h>
+
+struct gpio_dt_spec;
+void amd_stb_dump_finish(void);
+void amd_stb_dump_init(const struct gpio_dt_spec *int_out,
+		       const struct gpio_dt_spec *int_in);
+bool amd_stb_dump_in_progress(void);
+void amd_stb_dump_interrupt(enum gpio_signal signal);
+void amd_stb_dump_trigger(void);
diff --git a/driver/amd_stt.c b/driver/amd_stt.c
new file mode 100644
index 0000000000..a3e8378715
--- /dev/null
+++ b/driver/amd_stt.c
@@ -0,0 +1,179 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "amd_stt.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "driver/sb_rmi.h"
+#include "hooks.h"
+#include "math_util.h"
+#include "temp_sensor.h"
+#include "util.h"
+
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+#include "common_cpu_power.h"
+#endif
+
+/* Debug flag can be toggled with console command: stt debug */
+static bool amd_stt_debug;
+
+/* Console output macros */
+#define CPUTS(outstr) cputs(CC_THERMAL, outstr)
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
+
+static const char *const amd_stt_sensor_name[] = {
+	[AMD_STT_PCB_SENSOR_APU] = "APU",
+	[AMD_STT_PCB_SENSOR_REMOTE] = "Ambient",
+	[AMD_STT_PCB_SENSOR_GPU] = "GPU",
+};
+
+/**
+ * Write temperature sensor value to AP via SB-RMI
+ *
+ * sensor:
+ *	AMD_STT_PCB_SENSOR_APU
+ *	AMD_STT_PCB_SENSOR_REMOTE
+ *	AMD_STT_PCB_SENSOR_GPU
+ *
+ * temp_mk:
+ *	Temperature in degrees milli kelvin
+ */
+static int write_stt_sensor_val(enum amd_stt_pcb_sensor sensor, int temp_mk)
+{
+	uint32_t msgIn = 0;
+	uint32_t msgOut;
+	int temp_mc;
+	int temp_c_fp_msb;
+	int temp_c_fp_lsb;
+
+	temp_mc = MILLI_KELVIN_TO_MILLI_CELSIUS(temp_mk);
+
+	if (amd_stt_debug)
+		CPRINTS("STT: %s = %d.%d °C", amd_stt_sensor_name[sensor],
+			temp_mc / 1000, temp_mc % 1000);
+
+	/* Divide by 1000 to get MSB of fixed point temp */
+	temp_c_fp_msb = temp_mc / 1000;
+	/* Modulus 1000 and multiply by 256/1000 to get LSB of fixed point*/
+	temp_c_fp_lsb = ((temp_mc % 1000) << 8) / 1000;
+
+	/*
+	 * [15:0]: temperature as signed integer with 8 fractional bits.
+	 * [23:16]: sensor index
+	 * [31:24]: unused
+	 */
+	msgIn |= (temp_c_fp_lsb & 0xff);
+	msgIn |= (temp_c_fp_msb & 0xff) << 8;
+	msgIn |= (sensor & 0xff) << 16;
+	return sb_rmi_mailbox_xfer(SB_RMI_WRITE_STT_SENSOR_CMD, msgIn, &msgOut);
+}
+
+static void amd_stt_handler(void)
+{
+	int rv;
+	int soc_temp_mk;
+	int ambient_temp_mk;
+#ifdef CONFIG_GPU
+	int gpu_temp_mk;
+#endif
+
+	/* STT interface is only active in S0 */
+	if (!chipset_in_state(CHIPSET_STATE_ON)
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+	|| !get_apu_ready()
+#endif
+	)
+		return;
+
+	/*
+	 * TODO(b/192391025): Replace with temp_sensor_read_mk(TEMP_SENSOR_SOC)
+	 */
+	rv = board_get_soc_temp_mk(&soc_temp_mk);
+	if (rv) {
+		CPRINTS("STT: Failed to read SOC temp rv:%d", rv);
+		return;
+	}
+
+	rv = write_stt_sensor_val(AMD_STT_PCB_SENSOR_APU, soc_temp_mk);
+	if (rv) {
+		/* Failure reason will be logged by write_stt_sensor_val(), so
+		 * no need to log it here too.
+		 */
+		return;
+	}
+
+	/*
+	 * TODO(b/192391025): Replace with
+	 *	temp_sensor_read_mk(TEMP_SENSOR_AMBIENT)
+	 */
+	rv = board_get_ambient_temp_mk(&ambient_temp_mk);
+	if (rv) {
+		CPRINTS("STT: Failed to read AMBIENT temp rv:%d", rv);
+		return;
+	}
+
+	rv = write_stt_sensor_val(AMD_STT_PCB_SENSOR_REMOTE, ambient_temp_mk);
+	if (rv) {
+		/* Failure reason will be logged by write_stt_sensor_val(), so
+		 * no need to log it here too.
+		 */
+		return;
+	}
+
+#ifdef CONFIG_GPU
+
+	/*
+	 * TODO(b/192391025): Replace with
+	 *	temp_sensor_read_mk(TEMP_SENSOR_GPU)
+	 */
+	rv = board_get_gpu_temp_mk(&gpu_temp_mk);
+	if (rv) {
+		CPRINTS("STT: Failed to read GPU temp rv:%d", rv);
+		return;
+	}
+
+	rv = write_stt_sensor_val(AMD_STT_PCB_SENSOR_GPU, gpu_temp_mk);
+	if (rv) {
+		/* Failure reason will be logged by write_stt_sensor_val(), so
+		 * no need to log it here too.
+		 */
+		return;
+	}
+#endif
+}
+DECLARE_HOOK(HOOK_SECOND, amd_stt_handler, HOOK_PRIO_TEMP_SENSOR + 1);
+
+static int command_stt(int argc, const char **argv)
+{
+	int sensor_id;
+	int temp;
+
+	if (argc < 2)
+		return EC_ERROR_PARAM1;
+	else if (!strcasecmp(argv[1], "debug")) {
+		amd_stt_debug = !amd_stt_debug;
+		return EC_SUCCESS;
+	} else if (argc != 3)
+		return EC_ERROR_PARAM2;
+	else if (!strcasecmp(argv[1],
+			     amd_stt_sensor_name[AMD_STT_PCB_SENSOR_APU]))
+		sensor_id = AMD_STT_PCB_SENSOR_APU;
+	else if (!strcasecmp(argv[1],
+			     amd_stt_sensor_name[AMD_STT_PCB_SENSOR_REMOTE]))
+		sensor_id = AMD_STT_PCB_SENSOR_REMOTE;
+	else if (!strcasecmp(argv[1],
+			     amd_stt_sensor_name[AMD_STT_PCB_SENSOR_GPU]))
+		sensor_id = AMD_STT_PCB_SENSOR_GPU;
+	else
+		return EC_ERROR_PARAM2;
+
+	temp = atoi(argv[2]);
+
+	return write_stt_sensor_val(sensor_id, temp);
+}
+DECLARE_CONSOLE_COMMAND(stt, command_stt,
+			"<apu|ambient|gpu|debug> <temp in mK>",
+			"Write an STT mK temperature to AP");
diff --git a/driver/baro_bmp280.c b/driver/baro_bmp280.c
index 56376c8aa1..0175dc7e4a 100644
--- a/driver/baro_bmp280.c
+++ b/driver/baro_bmp280.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -63,10 +63,12 @@
 #include "i2c.h"
 #include "timer.h"
 
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args)
 
-static const uint16_t standby_durn[] = {1, 63, 125, 250, 500, 1000, 2000, 4000};
+static const uint16_t standby_durn[] = {
+	1, 63, 125, 250, 500, 1000, 2000, 4000
+};
 
 /*
  * This function is used to get calibration parameters used for
@@ -95,19 +97,19 @@ static int bmp280_get_calib_param(const struct motion_sensor_t *s)
 {
 	int ret;
 
-	uint8_t a_data_u8[BMP280_CALIB_DATA_SIZE] = {0};
+	uint8_t a_data_u8[BMP280_CALIB_DATA_SIZE] = { 0 };
 	struct bmp280_drv_data_t *data = BMP280_GET_DATA(s);
 
 	ret = i2c_read_block(s->port, s->i2c_spi_addr_flags,
-			BMP280_TEMPERATURE_CALIB_DIG_T1_LSB_REG,
-			a_data_u8, BMP280_CALIB_DATA_SIZE);
+			     BMP280_TEMPERATURE_CALIB_DIG_T1_LSB_REG, a_data_u8,
+			     BMP280_CALIB_DATA_SIZE);
 
 	if (ret)
 		return ret;
 
 	/* read calibration values*/
 	data->calib_param.dig_T1 = (a_data_u8[1] << 8) | a_data_u8[0];
-	data->calib_param.dig_T2 = (a_data_u8[3] << 8  | a_data_u8[2]);
+	data->calib_param.dig_T2 = (a_data_u8[3] << 8 | a_data_u8[2]);
 	data->calib_param.dig_T3 = (a_data_u8[5] << 8) | a_data_u8[4];
 
 	data->calib_param.dig_P1 = (a_data_u8[7] << 8) | a_data_u8[6];
@@ -124,21 +126,20 @@ static int bmp280_get_calib_param(const struct motion_sensor_t *s)
 }
 
 static int bmp280_read_uncomp_pressure(const struct motion_sensor_t *s,
-					int *uncomp_pres)
+				       int *uncomp_pres)
 {
 	int ret;
-	uint8_t a_data_u8[BMP280_PRESSURE_DATA_SIZE] = {0};
+	uint8_t a_data_u8[BMP280_PRESSURE_DATA_SIZE] = { 0 };
 
 	ret = i2c_read_block(s->port, s->i2c_spi_addr_flags,
-			BMP280_PRESSURE_MSB_REG,
-			a_data_u8, BMP280_PRESSURE_DATA_SIZE);
+			     BMP280_PRESSURE_MSB_REG, a_data_u8,
+			     BMP280_PRESSURE_DATA_SIZE);
 
 	if (ret)
 		return ret;
 
-	*uncomp_pres = (int32_t)((a_data_u8[0] << 12) |
-		     (a_data_u8[1] << 4) |
-		     (a_data_u8[2] >> 4));
+	*uncomp_pres = (int32_t)((a_data_u8[0] << 12) | (a_data_u8[1] << 4) |
+				 (a_data_u8[2] >> 4));
 
 	return EC_SUCCESS;
 }
@@ -153,34 +154,33 @@ static int bmp280_read_uncomp_pressure(const struct motion_sensor_t *s,
  *
  */
 static int bmp280_compensate_pressure(const struct motion_sensor_t *s,
-					int uncomp_pressure)
+				      int uncomp_pressure)
 {
 	int var1, var2;
 	uint32_t p;
 	struct bmp280_drv_data_t *data = BMP280_GET_DATA(s);
 
 	/* calculate x1 */
-	var1 = (((int32_t)data->calib_param.t_fine)
-		>> 1) - 64000;
+	var1 = (((int32_t)data->calib_param.t_fine) >> 1) - 64000;
 	/* calculate x2 */
-	var2 = (((var1 >> 2) * (var1 >> 2)) >> 11)
-		* ((int32_t)data->calib_param.dig_P6);
+	var2 = (((var1 >> 2) * (var1 >> 2)) >> 11) *
+	       ((int32_t)data->calib_param.dig_P6);
 	var2 = var2 + ((var1 * ((int32_t)data->calib_param.dig_P5)) << 1);
 	var2 = (var2 >> 2) + (((int32_t)data->calib_param.dig_P4) << 16);
 	/* calculate x1 */
 	var1 = (((data->calib_param.dig_P3 *
-		(((var1 >> 2) * (var1 >> 2)) >> 13)) >> 3) +
-		((((int32_t)data->calib_param.dig_P2) * var1) >> 1)) >> 18;
-	var1 = ((((32768 + var1)) *
-		((int32_t)data->calib_param.dig_P1)) >> 15);
+		  (((var1 >> 2) * (var1 >> 2)) >> 13)) >>
+		 3) +
+		((((int32_t)data->calib_param.dig_P2) * var1) >> 1)) >>
+	       18;
+	var1 = ((((32768 + var1)) * ((int32_t)data->calib_param.dig_P1)) >> 15);
 
 	/* Avoid exception caused by division by zero */
 	if (!var1)
 		return 0;
 
 	/* calculate pressure */
-	p = (((uint32_t)((1048576) - uncomp_pressure) -
-		(var2 >> 12))) * 3125;
+	p = (((uint32_t)((1048576) - uncomp_pressure) - (var2 >> 12))) * 3125;
 
 	/* check overflow */
 	if (p < 0x80000000)
@@ -190,13 +190,14 @@ static int bmp280_compensate_pressure(const struct motion_sensor_t *s,
 
 	/* calculate x1 */
 	var1 = (((int32_t)data->calib_param.dig_P9) *
-		((int32_t)(((p >> 3) * (p >> 3)) >> 13))) >> 12;
+		((int32_t)(((p >> 3) * (p >> 3)) >> 13))) >>
+	       12;
 	/* calculate x2 */
-	var2 = (((int32_t)(p >> 2)) *
-		((int32_t)data->calib_param.dig_P8)) >> 13;
+	var2 = (((int32_t)(p >> 2)) * ((int32_t)data->calib_param.dig_P8)) >>
+	       13;
 	/* calculate true pressure */
-	return (uint32_t)((int32_t)p + ((var1 + var2 +
-		data->calib_param.dig_P7) >> 4));
+	return (uint32_t)((int32_t)p +
+			  ((var1 + var2 + data->calib_param.dig_P7) >> 4));
 }
 
 /*
@@ -214,38 +215,36 @@ static int bmp280_compensate_pressure(const struct motion_sensor_t *s,
  *    0x07    | 4000_MS
  */
 static int bmp280_set_standby_durn(const struct motion_sensor_t *s,
-				uint8_t durn)
+				   uint8_t durn)
 {
 	int ret, val;
 
-	ret = i2c_read8(s->port, s->i2c_spi_addr_flags,
-			BMP280_CONFIG_REG, &val);
+	ret = i2c_read8(s->port, s->i2c_spi_addr_flags, BMP280_CONFIG_REG,
+			&val);
 
 	if (ret == EC_SUCCESS) {
 		val = (val & 0xE0) | ((durn << 5) & 0xE0);
 		/* write the standby duration*/
 		ret = i2c_write8(s->port, s->i2c_spi_addr_flags,
-			   BMP280_CONFIG_REG, val);
+				 BMP280_CONFIG_REG, val);
 	}
 
 	return ret;
 }
 
 static int bmp280_set_power_mode(const struct motion_sensor_t *s,
-				uint8_t power_mode)
+				 uint8_t power_mode)
 {
 	int val;
 
-	val = (BMP280_OVERSAMP_TEMP << 5) +
-		(BMP280_OVERSAMP_PRES << 2) + power_mode;
+	val = (BMP280_OVERSAMP_TEMP << 5) + (BMP280_OVERSAMP_PRES << 2) +
+	      power_mode;
 
-	return i2c_write8(s->port, s->i2c_spi_addr_flags,
-			  BMP280_CTRL_MEAS_REG, val);
+	return i2c_write8(s->port, s->i2c_spi_addr_flags, BMP280_CTRL_MEAS_REG,
+			  val);
 }
 
-static int bmp280_set_range(const struct motion_sensor_t *s,
-				int range,
-				int rnd)
+static int bmp280_set_range(struct motion_sensor_t *s, int range, int rnd)
 {
 	struct bmp280_drv_data_t *data = BMP280_GET_DATA(s);
 	/*
@@ -253,16 +252,10 @@ static int bmp280_set_range(const struct motion_sensor_t *s,
 	 * measurment to fit into 16 bits (or less if the AP wants to).
 	 */
 	data->range = 15 - __builtin_clz(range);
+	s->current_range = 1 << (16 + data->range);
 	return EC_SUCCESS;
 }
 
-static int bmp280_get_range(const struct motion_sensor_t *s)
-{
-	struct bmp280_drv_data_t *data = BMP280_GET_DATA(s);
-
-	return 1 << (16 + data->range);
-}
-
 /*
  * bmp280_init() - Used to initialize barometer with default config
  *
@@ -270,7 +263,7 @@ static int bmp280_get_range(const struct motion_sensor_t *s)
  * @retval 0 -> Success
  */
 
-static int bmp280_init(const struct motion_sensor_t *s)
+static int bmp280_init(struct motion_sensor_t *s)
 {
 	int val, ret;
 
@@ -278,8 +271,8 @@ static int bmp280_init(const struct motion_sensor_t *s)
 		return EC_ERROR_INVAL;
 
 	/* Read chip id */
-	ret = i2c_read8(s->port, s->i2c_spi_addr_flags,
-			BMP280_CHIP_ID_REG, &val);
+	ret = i2c_read8(s->port, s->i2c_spi_addr_flags, BMP280_CHIP_ID_REG,
+			&val);
 	if (ret)
 		return ret;
 
@@ -320,7 +313,7 @@ static int bmp280_read(const struct motion_sensor_t *s, intv3_t v)
  * Calculate the delay (in ms) to apply.
  */
 static int bmp280_set_data_rate(const struct motion_sensor_t *s, int rate,
-							int roundup)
+				int roundup)
 {
 	struct bmp280_drv_data_t *data = BMP280_GET_DATA(s);
 	int durn, i, ret;
@@ -341,12 +334,12 @@ static int bmp280_set_data_rate(const struct motion_sensor_t *s, int rate,
 	}
 
 	durn = 0;
-	for (i = BMP280_STANDBY_CNT-1;  i > 0; i--) {
+	for (i = BMP280_STANDBY_CNT - 1; i > 0; i--) {
 		if (period >= standby_durn[i] + BMP280_COMPUTE_TIME) {
 			durn = i;
 			break;
-		} else if (period > standby_durn[i-1] + BMP280_COMPUTE_TIME) {
-			durn = roundup ? i-1 : i;
+		} else if (period > standby_durn[i - 1] + BMP280_COMPUTE_TIME) {
+			durn = roundup ? i - 1 : i;
 			break;
 		}
 	}
@@ -372,7 +365,6 @@ const struct accelgyro_drv bmp280_drv = {
 	.init = bmp280_init,
 	.read = bmp280_read,
 	.set_range = bmp280_set_range,
-	.get_range = bmp280_get_range,
 	.set_data_rate = bmp280_set_data_rate,
 	.get_data_rate = bmp280_get_data_rate,
 };
diff --git a/driver/baro_bmp280.h b/driver/baro_bmp280.h
index ee95bd886f..605f3db4fa 100644
--- a/driver/baro_bmp280.h
+++ b/driver/baro_bmp280.h
@@ -1,62 +1,62 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 /** \mainpage
-*
-****************************************************************************
-* Copyright (C) 2012 - 2015 Bosch Sensortec GmbH
-*
-* File : bmp280.h
-*
-* Date : 2015/03/27
-*
-* Revision : 2.0.4(Pressure and Temperature compensation code revision is 1.1)
-*
-* Usage: Sensor Driver for BMP280 sensor
-*
-****************************************************************************
-*
-* \section License
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions are met:
-*
-*   Redistributions of source code must retain the above copyright
-*   notice, this list of conditions and the following disclaimer.
-*
-*   Redistributions in binary form must reproduce the above copyright
-*   notice, this list of conditions and the following disclaimer in the
-*   documentation and/or other materials provided with the distribution.
-*
-*   Neither the name of the copyright holder nor the names of the
-*   contributors may be used to endorse or promote products derived from
-*   this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
-* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDER
-* OR CONTRIBUTORS BE LIABLE FOR ANY
-* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-* OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT NOT LIMITED TO,
-* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
-*
-* The information provided is believed to be accurate and reliable.
-* The copyright holder assumes no responsibility
-* for the consequences of use
-* of such information nor for any infringement of patents or
-* other rights of third parties which may result from its use.
-* No license is granted by implication or otherwise under any patent or
-* patent rights of the copyright holder.
-**************************************************************************/
+ *
+ ****************************************************************************
+ * Copyright (C) 2012 - 2015 Bosch Sensortec GmbH
+ *
+ * File : bmp280.h
+ *
+ * Date : 2015/03/27
+ *
+ * Revision : 2.0.4(Pressure and Temperature compensation code revision is 1.1)
+ *
+ * Usage: Sensor Driver for BMP280 sensor
+ *
+ ****************************************************************************
+ *
+ * \section License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *   Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ *   Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ *
+ *   Neither the name of the copyright holder nor the names of the
+ *   contributors may be used to endorse or promote products derived from
+ *   this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ * The information provided is believed to be accurate and reliable.
+ * The copyright holder assumes no responsibility
+ * for the consequences of use
+ * of such information nor for any infringement of patents or
+ * other rights of third parties which may result from its use.
+ * No license is granted by implication or otherwise under any patent or
+ * patent rights of the copyright holder.
+ **************************************************************************/
 /* BMP280 pressure and temperature module for Chrome EC */
 
 #ifndef __CROS_EC_BARO_BMP280_H
@@ -74,80 +74,81 @@
  * Bit 1 of 7-bit address: 0 - If SDO is connected to GND
  * Bit 1 of 7-bit address: 1 - If SDO is connected to Vddio
  */
-#define BMP280_I2C_ADDRESS1_FLAGS	0x76
-#define BMP280_I2C_ADDRESS2_FLAGS	0x77
+#define BMP280_I2C_ADDRESS1_FLAGS 0x76
+#define BMP280_I2C_ADDRESS2_FLAGS 0x77
 
 /*
  *     CHIP ID
  */
-#define BMP280_CHIP_ID			0x58
+#define BMP280_CHIP_ID 0x58
 /************************************************/
 /*	CALIBRATION PARAMETERS DEFINITION       */
 /************************************************/
 
-#define BMP280_TEMPERATURE_CALIB_DIG_T1_LSB_REG	0x88
+#define BMP280_TEMPERATURE_CALIB_DIG_T1_LSB_REG 0x88
 
 /************************************************/
 /*	REGISTER ADDRESS DEFINITION             */
 /************************************************/
-#define BMP280_CHIP_ID_REG		     0xD0
-#define BMP280_RST_REG                       0xE0  /*Softreset Register */
-#define BMP280_STAT_REG                      0xF3  /*Status Register */
-#define BMP280_CTRL_MEAS_REG                 0xF4  /*Ctrl Measure Register */
-#define BMP280_CONFIG_REG                    0xF5  /*Configuration Register */
-#define BMP280_PRESSURE_MSB_REG              0xF7  /*Pressure MSB Register */
-#define BMP280_PRESSURE_LSB_REG              0xF8  /*Pressure LSB Register */
-#define BMP280_PRESSURE_XLSB_REG             0xF9  /*Pressure XLSB Register */
+#define BMP280_CHIP_ID_REG 0xD0
+#define BMP280_RST_REG 0xE0 /*Softreset Register */
+#define BMP280_STAT_REG 0xF3 /*Status Register */
+#define BMP280_CTRL_MEAS_REG 0xF4 /*Ctrl Measure Register */
+#define BMP280_CONFIG_REG 0xF5 /*Configuration Register */
+#define BMP280_PRESSURE_MSB_REG 0xF7 /*Pressure MSB Register */
+#define BMP280_PRESSURE_LSB_REG 0xF8 /*Pressure LSB Register */
+#define BMP280_PRESSURE_XLSB_REG 0xF9 /*Pressure XLSB Register */
 /************************************************/
 /*	POWER MODE DEFINITION                   */
 /************************************************/
 /* Sensor Specific constants */
-#define BMP280_SLEEP_MODE                    0x00
-#define BMP280_FORCED_MODE                   0x01
-#define BMP280_NORMAL_MODE                   0x03
-#define BMP280_SOFT_RESET_CODE               0xB6
+#define BMP280_SLEEP_MODE 0x00
+#define BMP280_FORCED_MODE 0x01
+#define BMP280_NORMAL_MODE 0x03
+#define BMP280_SOFT_RESET_CODE 0xB6
 /************************************************/
 /*	STANDBY TIME DEFINITION                 */
 /************************************************/
-#define BMP280_STANDBY_TIME_1_MS              0x00
-#define BMP280_STANDBY_TIME_63_MS             0x01
-#define BMP280_STANDBY_TIME_125_MS            0x02
-#define BMP280_STANDBY_TIME_250_MS            0x03
-#define BMP280_STANDBY_TIME_500_MS            0x04
-#define BMP280_STANDBY_TIME_1000_MS           0x05
-#define BMP280_STANDBY_TIME_2000_MS           0x06
-#define BMP280_STANDBY_TIME_4000_MS           0x07
+#define BMP280_STANDBY_TIME_1_MS 0x00
+#define BMP280_STANDBY_TIME_63_MS 0x01
+#define BMP280_STANDBY_TIME_125_MS 0x02
+#define BMP280_STANDBY_TIME_250_MS 0x03
+#define BMP280_STANDBY_TIME_500_MS 0x04
+#define BMP280_STANDBY_TIME_1000_MS 0x05
+#define BMP280_STANDBY_TIME_2000_MS 0x06
+#define BMP280_STANDBY_TIME_4000_MS 0x07
 /************************************************/
 /*	OVERSAMPLING DEFINITION                 */
 /************************************************/
-#define BMP280_OVERSAMP_SKIPPED          0x00
-#define BMP280_OVERSAMP_1X               0x01
-#define BMP280_OVERSAMP_2X               0x02
-#define BMP280_OVERSAMP_4X               0x03
-#define BMP280_OVERSAMP_8X               0x04
-#define BMP280_OVERSAMP_16X              0x05
+#define BMP280_OVERSAMP_SKIPPED 0x00
+#define BMP280_OVERSAMP_1X 0x01
+#define BMP280_OVERSAMP_2X 0x02
+#define BMP280_OVERSAMP_4X 0x03
+#define BMP280_OVERSAMP_8X 0x04
+#define BMP280_OVERSAMP_16X 0x05
 /************************************************/
 /*	DEFINITIONS FOR ARRAY SIZE OF DATA      */
 /************************************************/
-#define	BMP280_PRESSURE_DATA_SIZE	3
-#define	BMP280_DATA_FRAME_SIZE		6
-#define	BMP280_CALIB_DATA_SIZE		24
+#define BMP280_PRESSURE_DATA_SIZE 3
+#define BMP280_DATA_FRAME_SIZE 6
+#define BMP280_CALIB_DATA_SIZE 24
 /*******************************************************/
 /*         SAMPLING PERIOD COMPUTATION CONSTANT	       */
 /*******************************************************/
-#define BMP280_STANDBY_CNT		8
-#define T_INIT_MAX			(20) /* (20/16 = 1.25ms) */
-#define T_MEASURE_PER_OSRS_MAX		(37) /* (37/16 = 2.31ms) */
-#define T_SETUP_PRESSURE_MAX		(10) /* (10/16 = 0.62ms) */
+#define BMP280_STANDBY_CNT 8
+#define T_INIT_MAX (20) /* (20/16 = 1.25ms) */
+#define T_MEASURE_PER_OSRS_MAX (37) /* (37/16 = 2.31ms) */
+#define T_SETUP_PRESSURE_MAX (10) /* (10/16 = 0.62ms) */
 
 /*
  * This is the measurement time required for pressure and temp
  */
-#define BMP280_COMPUTE_TIME \
-	((T_INIT_MAX + T_MEASURE_PER_OSRS_MAX * \
-	  ((BIT(BMP280_OVERSAMP_TEMP) >> 1) + \
-	   (BIT(BMP280_OVERSAMP_PRES) >> 1)) + \
-	  (BMP280_OVERSAMP_PRES ? T_SETUP_PRESSURE_MAX : 0) + 15) / 16)
+#define BMP280_COMPUTE_TIME                                             \
+	((T_INIT_MAX +                                                  \
+	  T_MEASURE_PER_OSRS_MAX * ((BIT(BMP280_OVERSAMP_TEMP) >> 1) +  \
+				    (BIT(BMP280_OVERSAMP_PRES) >> 1)) + \
+	  (BMP280_OVERSAMP_PRES ? T_SETUP_PRESSURE_MAX : 0) + 15) /     \
+	 16)
 
 /*
  * These values are selected as per Bosch recommendation for
@@ -158,15 +159,14 @@
 /*******************************************************/
 /*             GET DRIVER DATA			       */
 /*******************************************************/
-#define BMP280_GET_DATA(_s) \
-	((struct bmp280_drv_data_t *)(_s)->drv_data)
+#define BMP280_GET_DATA(_s) ((struct bmp280_drv_data_t *)(_s)->drv_data)
 
 /* Min and Max sampling frequency in mHz based on x4 oversampling used */
 /* FIXME - verify how chip is setup to make sure MAX is correct, manual says
  * "Typical", not Max.
  */
-#define BMP280_BARO_MIN_FREQ  75000
-#define BMP280_BARO_MAX_FREQ  87000
+#define BMP280_BARO_MIN_FREQ 75000
+#define BMP280_BARO_MAX_FREQ 87000
 #if (CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ <= BMP280_BARO_MAX_FREQ)
 #error "EC too slow for accelerometer"
 #endif
@@ -208,8 +208,7 @@ struct bmp280_calib_param_t {
  * @range:		bit offset to fit data in 16 bit or less.
  */
 struct bmp280_drv_data_t {
-
-	struct   bmp280_calib_param_t calib_param;
+	struct bmp280_calib_param_t calib_param;
 	uint16_t rate;
 	uint16_t range;
 };
diff --git a/driver/battery/bq20z453.c b/driver/battery/bq20z453.c
index 3cd16e8b8f..943dfe41b2 100644
--- a/driver/battery/bq20z453.c
+++ b/driver/battery/bq20z453.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -18,7 +18,8 @@ static void cutoff(void)
 }
 DECLARE_DEFERRED(cutoff);
 
-enum ec_status battery_command_cut_off(struct host_cmd_handler_args *args)
+static enum ec_status
+battery_command_cut_off(struct host_cmd_handler_args *args)
 {
 	/*
 	 * Queue battery cutoff.  This must be deferred so we can send the
diff --git a/driver/battery/bq27541.c b/driver/battery/bq27541.c
index 868b0215e8..f190c942ac 100644
--- a/driver/battery/bq27541.c
+++ b/driver/battery/bq27541.c
@@ -1,49 +1,64 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
- * Battery driver for BQ27541/BQ27741/BQ27742.
+ * Battery driver for BQ27541/BQ27542/BQ27741/BQ27742.
  */
 
 #include "battery.h"
+#include "battery_smart.h"
 #include "console.h"
 #include "extpower.h"
 #include "hooks.h"
 #include "i2c.h"
 #include "util.h"
 
-#define BQ27541_ADDR_FLAGS          0x55
-#define BQ27541_TYPE_ID             0x0541
-#define BQ27741_TYPE_ID             0x0741
-#define BQ27742_TYPE_ID             0x0742
-
-#define REG_CTRL                    0x00
-#define REG_AT_RATE                 0x02
-#define REG_AT_RATE_TIME_TO_EMPTY   0x04
-#define REG_TEMPERATURE             0x06
-#define REG_VOLTAGE                 0x08
-#define REG_FLAGS                   0x0a
-#define REG_NOMINAL_CAPACITY        0x0c
+#define BQ27541_ADDR_FLAGS 0x55
+#define BQ27541_TYPE_ID 0x0541
+#define BQ27542_TYPE_ID 0x0542
+#define BQ27741_TYPE_ID 0x0741
+#define BQ27742_TYPE_ID 0x0742
+
+#define REG_CTRL 0x00
+#define REG_AT_RATE 0x02
+#define REG_AT_RATE_TIME_TO_EMPTY 0x04
+#define REG_TEMPERATURE 0x06
+#define REG_VOLTAGE 0x08
+#define REG_FLAGS 0x0a
+#define REG_NOMINAL_CAPACITY 0x0c
 #define REG_FULL_AVAILABLE_CAPACITY 0x0e
-#define REG_REMAINING_CAPACITY      0x10
-#define REG_FULL_CHARGE_CAPACITY    0x12
-#define REG_AVERAGE_CURRENT         0x14
-#define REG_TIME_TO_EMPTY           0x16
-#define REG_TIME_TO_FULL            0x18
-#define REG_STANDBY_CURRENT         0x1a
-#define REG_STANDBY_TIME_TO_EMPTY   0x1c
-#define REG_MAX_LOAD_CURRENT        0x1e
-#define REG_MAX_LOAD_TIME_TO_EMPTY  0x20
-#define REG_AVAILABLE_ENERGY        0x22
-#define REG_AVERAGE_POEWR           0x24
-#define REG_TT_EAT_CONSTANT_POWER   0x26
-#define REG_CYCLE_COUNT             0x2a
-#define REG_STATE_OF_CHARGE         0x2c
-#define REG_DESIGN_CAPACITY         0x3c
-#define REG_DEVICE_NAME_LENGTH      0x62
-#define MAX_DEVICE_NAME_LENGTH      7
-#define REG_DEVICE_NAME             0x63
-#define REG_PROTECTOR               0x6d
+#define REG_REMAINING_CAPACITY 0x10
+#define REG_FULL_CHARGE_CAPACITY 0x12
+#define REG_AVERAGE_CURRENT 0x14
+#define REG_TIME_TO_EMPTY 0x16
+#define REG_TIME_TO_FULL 0x18
+#define REG_STANDBY_CURRENT 0x1a
+#define REG_STANDBY_TIME_TO_EMPTY 0x1c
+#define REG_MAX_LOAD_CURRENT 0x1e
+#define REG_MAX_LOAD_TIME_TO_EMPTY 0x20
+#define REG_AVAILABLE_ENERGY 0x22
+#define REG_AVERAGE_POEWR 0x24
+#define REG_TT_EAT_CONSTANT_POWER 0x26
+#define REG_CYCLE_COUNT 0x2a
+#define REG_STATE_OF_CHARGE 0x2c
+#define REG_DATA_FLASH_BLOCK 0x3f
+#define REG_DESIGN_CAPACITY 0x3c
+#define REG_MANUFACTURER_INFO 0x52
+#define REG_DEVICE_NAME_LENGTH 0x62
+#define MAX_DEVICE_NAME_LENGTH 7
+#define REG_DEVICE_NAME 0x63
+#define REG_PROTECTOR 0x6d
+
+/* Over-charge */
+#define BQ27542_FLAG_BATHI BIT(13)
+/* Over Temperature in discharge */
+#define BQ27542_FLAG_OTD BIT(11)
+/* Over Temperature in charge */
+#define BQ27542_FLAG_OTC BIT(7)
+/* Charge allowed */
+#define BQ27542_FLAG_CHG BIT(3)
+/* Discharge */
+#define BQ27542_FLAG_DSG BIT(0)
 
 static int battery_type_id;
 static int fake_state_of_charge = -1;
@@ -69,10 +84,12 @@ int bq27541_probe(void)
 
 	rv = bq27541_write(REG_CTRL, 0x1);
 	rv |= bq27541_read(REG_CTRL, &battery_type_id);
-
+	/* Read twice to get the right value */
+	rv |= bq27541_read(REG_CTRL, &battery_type_id);
 	if (rv)
 		return rv;
 	if (battery_type_id == BQ27541_TYPE_ID ||
+	    battery_type_id == BQ27542_TYPE_ID ||
 	    battery_type_id == BQ27741_TYPE_ID ||
 	    battery_type_id == BQ27742_TYPE_ID)
 		return EC_SUCCESS;
@@ -95,6 +112,16 @@ int battery_device_name(char *device_name, int buf_size)
 		strzcpy(device_name, "<BATT>", len);
 		return 0;
 	}
+	/* Battery pack vendor specific */
+	if (battery_type_id == BQ27542_TYPE_ID) {
+		rv = bq27541_write(REG_DATA_FLASH_BLOCK, 0x1);
+		for (i = 0; i < len; ++i) {
+			rv |= bq27541_read8(REG_MANUFACTURER_INFO + i, &val);
+			device_name[i] = val;
+		}
+		device_name[i] = '\0';
+		return rv;
+	}
 
 	rv = bq27541_read8(REG_DEVICE_NAME_LENGTH, &val);
 	if (rv)
@@ -112,7 +139,7 @@ int battery_device_name(char *device_name, int buf_size)
 
 int battery_state_of_charge_abs(int *percent)
 {
-	return EC_ERROR_UNIMPLEMENTED;
+	return bq27541_read(REG_STATE_OF_CHARGE, percent);
 }
 
 int battery_remaining_capacity(int *capacity)
@@ -149,6 +176,9 @@ int battery_time_at_rate(int rate, int *minutes)
 {
 	int rv;
 
+	if (battery_type_id == BQ27542_TYPE_ID)
+		return EC_ERROR_UNIMPLEMENTED;
+
 	rv = bq27541_write(REG_AT_RATE, rate);
 	if (rv)
 		return rv;
@@ -197,7 +227,7 @@ static int battery_charging_allowed(int *allowed)
 	if (battery_type_id == BQ27541_TYPE_ID ||
 	    battery_type_id == BQ27741_TYPE_ID)
 		*allowed = (val & 0x100);
-	else /* BQ27742_TYPE_ID */
+	else /* BQ27742_TYPE_ID, BQ27542_TYPE_ID */
 		*allowed = (val & 0x8);
 
 	return EC_SUCCESS;
@@ -210,6 +240,25 @@ int battery_get_mode(int *mode)
 
 int battery_status(int *status)
 {
+	int rv;
+	int flag = 0;
+
+	*status = 0;
+	if (battery_type_id == BQ27542_TYPE_ID) {
+		rv = bq27541_read(REG_FLAGS, &flag);
+		if (rv)
+			return rv;
+
+		if (flag & (BQ27542_FLAG_OTC | BQ27542_FLAG_OTD))
+			*status |= STATUS_OVERTEMP_ALARM;
+		if (flag & BQ27542_FLAG_DSG)
+			*status |= STATUS_DISCHARGING;
+		if (flag & BQ27542_FLAG_BATHI)
+			*status |= STATUS_OVERCHARGED_ALARM;
+
+		return EC_SUCCESS;
+	}
+
 	return EC_ERROR_UNIMPLEMENTED;
 }
 
@@ -217,17 +266,16 @@ enum battery_present battery_is_present(void)
 {
 	int v;
 	if (bq27541_read(REG_TEMPERATURE, &v))
-		return BP_NOT_SURE;
+		return BP_NO;
 	return BP_YES;
 }
 
 void battery_get_params(struct batt_params *batt)
 {
 	int v;
-	const uint32_t flags_to_check = BATT_FLAG_BAD_TEMPERATURE |
-					BATT_FLAG_BAD_STATE_OF_CHARGE |
-					BATT_FLAG_BAD_VOLTAGE |
-					BATT_FLAG_BAD_CURRENT;
+	const uint32_t flags_to_check =
+		BATT_FLAG_BAD_TEMPERATURE | BATT_FLAG_BAD_STATE_OF_CHARGE |
+		BATT_FLAG_BAD_VOLTAGE | BATT_FLAG_BAD_CURRENT;
 
 	/* Reset flags */
 	batt->flags = 0;
@@ -238,8 +286,8 @@ void battery_get_params(struct batt_params *batt)
 	if (bq27541_read8(REG_STATE_OF_CHARGE, &v) && fake_state_of_charge < 0)
 		batt->flags |= BATT_FLAG_BAD_STATE_OF_CHARGE;
 
-	batt->state_of_charge = fake_state_of_charge >= 0 ?
-					fake_state_of_charge : v;
+	batt->state_of_charge =
+		fake_state_of_charge >= 0 ? fake_state_of_charge : v;
 
 	if (bq27541_read(REG_VOLTAGE, &batt->voltage))
 		batt->flags |= BATT_FLAG_BAD_VOLTAGE;
@@ -249,6 +297,12 @@ void battery_get_params(struct batt_params *batt)
 		batt->flags |= BATT_FLAG_BAD_CURRENT;
 	batt->current = (int16_t)v;
 
+	if (battery_remaining_capacity(&batt->remaining_capacity))
+		batt->flags |= BATT_FLAG_BAD_REMAINING_CAPACITY;
+
+	if (battery_full_charge_capacity(&batt->full_capacity))
+		batt->flags |= BATT_FLAG_BAD_FULL_CAPACITY;
+
 	/* Default to not desiring voltage and current */
 	batt->desired_voltage = batt->desired_current = 0;
 
@@ -257,9 +311,14 @@ void battery_get_params(struct batt_params *batt)
 		batt->flags |= BATT_FLAG_RESPONSIVE;
 		batt->is_present = BP_YES;
 	} else {
-		batt->is_present = BP_NOT_SURE;
+		/* If all of those reads error, the battery is not present */
+		batt->is_present = BP_NO;
 	}
 
+	/* update the battery status */
+	if (battery_status(&batt->status))
+		batt->flags |= BATT_FLAG_BAD_STATUS;
+
 	v = 0;
 	if (battery_charging_allowed(&v)) {
 		batt->flags |= BATT_FLAG_BAD_ANY;
@@ -330,7 +389,7 @@ enum battery_disconnect_state battery_get_disconnect_state(void)
 }
 #endif /* CONFIG_BATTERY_REVIVE_DISCONNECT */
 
-static int command_battfake(int argc, char **argv)
+static int command_battfake(int argc, const char **argv)
 {
 	char *e;
 	int v;
@@ -344,8 +403,7 @@ static int command_battfake(int argc, char **argv)
 	}
 
 	if (fake_state_of_charge >= 0)
-		ccprintf("Fake batt %d%%\n",
-			 fake_state_of_charge);
+		ccprintf("Fake batt %d%%\n", fake_state_of_charge);
 
 	return EC_SUCCESS;
 }
@@ -353,3 +411,18 @@ DECLARE_CONSOLE_COMMAND(battfake, command_battfake,
 			"percent (-1 = use real level)",
 			"Set fake battery level");
 
+#ifdef CONFIG_CMD_PWR_AVG
+int battery_get_avg_current(void)
+{
+	int current = -EC_ERROR_UNKNOWN;
+
+	bq27541_read(REG_AVERAGE_CURRENT, &current);
+	return current;
+}
+
+int battery_get_avg_voltage(void)
+{
+	/* BQ27541 does not have this parameter */
+	return -EC_ERROR_UNIMPLEMENTED;
+}
+#endif /* CONFIG_CMD_PWR_AVG */
diff --git a/driver/battery/bq27621_g1.c b/driver/battery/bq27621_g1.c
index dbda6f9c65..73ca8476b3 100644
--- a/driver/battery/bq27621_g1.c
+++ b/driver/battery/bq27621_g1.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -6,102 +6,103 @@
  */
 
 #include "battery.h"
+#include "builtin/assert.h"
 #include "console.h"
 #include "extpower.h"
 #include "hooks.h"
 #include "i2c.h"
-#include "util.h"
 #include "timer.h"
+#include "util.h"
 
-#define BQ27621_ADDR_FLAGS                  0x55
-#define BQ27621_TYPE_ID                     0x0621
-
-#define REG_CTRL                            0x00
-#define REG_TEMPERATURE                     0x02
-#define REG_VOLTAGE                         0x04
-#define REG_FLAGS                           0x06
-#define REG_NOMINAL_CAPACITY                0x08
-#define REG_FULL_AVAILABLE_CAPACITY         0x0a
-#define REG_REMAINING_CAPACITY              0x0c
-#define REG_FULL_CHARGE_CAPACITY            0x0e
-#define REG_EFFECTIVE_CURRENT               0x10
-#define REG_AVERAGE_POWER                   0x18
-#define REG_STATE_OF_CHARGE                 0x1c
-#define REG_INTERNAL_TEMPERATURE            0x1e
-#define REG_REMAINING_CAPACITY_UNFILTERED   0x28
-#define REG_REMAINING_CAPACITY_FILTERED     0x2a
+#define BQ27621_ADDR_FLAGS 0x55
+#define BQ27621_TYPE_ID 0x0621
+
+#define REG_CTRL 0x00
+#define REG_TEMPERATURE 0x02
+#define REG_VOLTAGE 0x04
+#define REG_FLAGS 0x06
+#define REG_NOMINAL_CAPACITY 0x08
+#define REG_FULL_AVAILABLE_CAPACITY 0x0a
+#define REG_REMAINING_CAPACITY 0x0c
+#define REG_FULL_CHARGE_CAPACITY 0x0e
+#define REG_EFFECTIVE_CURRENT 0x10
+#define REG_AVERAGE_POWER 0x18
+#define REG_STATE_OF_CHARGE 0x1c
+#define REG_INTERNAL_TEMPERATURE 0x1e
+#define REG_REMAINING_CAPACITY_UNFILTERED 0x28
+#define REG_REMAINING_CAPACITY_FILTERED 0x2a
 #define REG_FULL_CHARGE_CAPACITY_UNFILTERED 0x28
-#define REG_FULL_CHARGE_CAPACITY_FILTERED   0x2a
-#define REG_STATE_OF_CHARGE_UNFILTERED      0x30
-#define REG_OP_CONFIG                       0x3a
-#define REG_DESIGN_CAPACITY                 0x3c
-#define REG_DATA_CLASS                      0x3e
-#define REG_DATA_BLOCK                      0x3f
-#define REG_BLOCK_DATA_CHECKSUM             0x60
-#define REG_BLOCK_DATA_CONTROL              0x61
-
-#define REGISTERS_BLOCK_OFFSET                64
-#define REGISTERS_BLOCK_OP_CONFIG           0x40
-#define REGISTERS_BLOCK_OP_CONFIG_B         0x42
-#define REGISTERS_BLOCK_DF_VERSION          0x43
+#define REG_FULL_CHARGE_CAPACITY_FILTERED 0x2a
+#define REG_STATE_OF_CHARGE_UNFILTERED 0x30
+#define REG_OP_CONFIG 0x3a
+#define REG_DESIGN_CAPACITY 0x3c
+#define REG_DATA_CLASS 0x3e
+#define REG_DATA_BLOCK 0x3f
+#define REG_BLOCK_DATA_CHECKSUM 0x60
+#define REG_BLOCK_DATA_CONTROL 0x61
+
+#define REGISTERS_BLOCK_OFFSET 64
+#define REGISTERS_BLOCK_OP_CONFIG 0x40
+#define REGISTERS_BLOCK_OP_CONFIG_B 0x42
+#define REGISTERS_BLOCK_DF_VERSION 0x43
 
 /* State block */
-#define STATE_BLOCK_OFFSET                    82
-#define STATE_BLOCK_DESIGN_CAPACITY         0x43
-#define STATE_BLOCK_DESIGN_ENERGY           0x45
-#define STATE_BLOCK_TERMINATE_VOLTAGE       0x49
-#define STATE_BLOCK_TAPER_RATE              0x54
+#define STATE_BLOCK_OFFSET 82
+#define STATE_BLOCK_DESIGN_CAPACITY 0x43
+#define STATE_BLOCK_DESIGN_ENERGY 0x45
+#define STATE_BLOCK_TERMINATE_VOLTAGE 0x49
+#define STATE_BLOCK_TAPER_RATE 0x54
 
 /* BQ27621 Control subcommands */
-#define CONTROL_CONTROL_STATUS   0x00
-#define CONTROL_DEVICE_TYPE      0x01
-#define CONTROL_FW_VERSION       0x02
-#define CONTROL_PREV_MACWRITE    0x07
-#define CONTROL_CHEM_ID          0x08
-#define CONTROL_BAT_INSERT       0x0C
-#define CONTROL_BAT_REMOVE       0x0D
-#define CONTROL_TOGGLE_POWERMIN  0x10
-#define CONTROL_SET_HIBERNATE    0x11
-#define CONTROL_CLEAR_HIBERNATE  0x12
-#define CONTROL_SET_CFGUPDATE    0x13
-#define CONTROL_SHUTDOWN_ENABLE  0x1B
-#define CONTROL_SHUTDOWN         0x1C
-#define CONTROL_SEALED           0x20
-#define CONTROL_TOGGLE_GPOUT     0x23
-#define CONTROL_ALT_CHEM1        0x31
-#define CONTROL_ALT_CHEM2        0x32
-#define CONTROL_RESET            0x41
-#define CONTROL_SOFT_RESET       0x42
-#define CONTROL_EXIT_CFGUPDATE   0x43
-#define CONTROL_EXIT_RESIM       0x44
-#define CONTROL_UNSEAL           0x8000
+#define CONTROL_CONTROL_STATUS 0x00
+#define CONTROL_DEVICE_TYPE 0x01
+#define CONTROL_FW_VERSION 0x02
+#define CONTROL_PREV_MACWRITE 0x07
+#define CONTROL_CHEM_ID 0x08
+#define CONTROL_BAT_INSERT 0x0C
+#define CONTROL_BAT_REMOVE 0x0D
+#define CONTROL_TOGGLE_POWERMIN 0x10
+#define CONTROL_SET_HIBERNATE 0x11
+#define CONTROL_CLEAR_HIBERNATE 0x12
+#define CONTROL_SET_CFGUPDATE 0x13
+#define CONTROL_SHUTDOWN_ENABLE 0x1B
+#define CONTROL_SHUTDOWN 0x1C
+#define CONTROL_SEALED 0x20
+#define CONTROL_TOGGLE_GPOUT 0x23
+#define CONTROL_ALT_CHEM1 0x31
+#define CONTROL_ALT_CHEM2 0x32
+#define CONTROL_RESET 0x41
+#define CONTROL_SOFT_RESET 0x42
+#define CONTROL_EXIT_CFGUPDATE 0x43
+#define CONTROL_EXIT_RESIM 0x44
+#define CONTROL_UNSEAL 0x8000
 
 /* BQ27621 Status bits */
-#define STATUS_SHUTDOWNEN        0x8000
-#define STATUS_WDRESET           0x4000
-#define STATUS_SS                0x2000
-#define STATUS_CALMODE           0x1000
-#define STATUS_OCVCMDCOMP        0x0200
-#define STATUS_OCVFAIL           0x0100
-#define STATUS_INITCOMP          0x0080
-#define STATUS_HIBERNATE         0x0040
-#define STATUS_POWERMIN          0x0020
-#define STATUS_SLEEP             0x0010
-#define STATUS_LDMD              0x0008
-#define STATUS_CHEMCHNG          0x0001
+#define STATUS_SHUTDOWNEN 0x8000
+#define STATUS_WDRESET 0x4000
+#define STATUS_SS 0x2000
+#define STATUS_CALMODE 0x1000
+#define STATUS_OCVCMDCOMP 0x0200
+#define STATUS_OCVFAIL 0x0100
+#define STATUS_INITCOMP 0x0080
+#define STATUS_HIBERNATE 0x0040
+#define STATUS_POWERMIN 0x0020
+#define STATUS_SLEEP 0x0010
+#define STATUS_LDMD 0x0008
+#define STATUS_CHEMCHNG 0x0001
 
 /* BQ27621 Flags bits */
-#define FLAGS_OT                 0x8000
-#define FLAGS_UT                 0x4000
-#define FLAGS_FC                 0x0200
-#define FLAGS_CHG                0x0100
-#define FLAGS_OCVTAKEN           0x0080
-#define FLAGS_ITPOR              0x0020
-#define FLAGS_CFGUPD             0x0010
-#define FLAGS_BAT_DET            0x0008
-#define FLAGS_SOC1               0x0004
-#define FLAGS_SOCF               0x0002
-#define FLAGS_DSG                0x0001
+#define FLAGS_OT 0x8000
+#define FLAGS_UT 0x4000
+#define FLAGS_FC 0x0200
+#define FLAGS_CHG 0x0100
+#define FLAGS_OCVTAKEN 0x0080
+#define FLAGS_ITPOR 0x0020
+#define FLAGS_CFGUPD 0x0010
+#define FLAGS_BAT_DET 0x0008
+#define FLAGS_SOC1 0x0004
+#define FLAGS_SOCF 0x0002
+#define FLAGS_DSG 0x0001
 
 /*
  * There are some parameters that need to be defined in the board file:
@@ -119,19 +120,23 @@
  *
  */
 
-#define BQ27621_SCALE_FACTOR (BQ27621_DESIGN_CAPACITY < 150 ? 10.0 : \
-				(BQ27621_DESIGN_CAPACITY > 6000 ? 0.1 : 1))
+#define BQ27621_SCALE_FACTOR             \
+	(BQ27621_DESIGN_CAPACITY < 150 ? \
+		 10.0 :                  \
+		 (BQ27621_DESIGN_CAPACITY > 6000 ? 0.1 : 1))
 
-#define BQ27621_UNSCALE(x)   (BQ27621_SCALE_FACTOR == 10 ? (x) / 10 : \
-				(BQ27621_SCALE_FACTOR == 0.1 ? (x) * 10 : (x)))
+#define BQ27621_UNSCALE(x)            \
+	(BQ27621_SCALE_FACTOR == 10 ? \
+		 (x) / 10 :           \
+		 (BQ27621_SCALE_FACTOR == 0.1 ? (x)*10 : (x)))
 
-#define BQ27621_TAPER_RATE  ((int)(BQ27621_DESIGN_CAPACITY/    \
-				(0.1 * BQ27621_TAPER_CURRENT)))
+#define BQ27621_TAPER_RATE \
+	((int)(BQ27621_DESIGN_CAPACITY / (0.1 * BQ27621_TAPER_CURRENT)))
 
-#define BQ27621_SCALED_DESIGN_CAPACITY ((int)(BQ27621_DESIGN_CAPACITY *   \
-					BQ27621_SCALE_FACTOR))
-#define BQ27621_SCALED_DESIGN_ENERGY   ((int)(BQ27621_DESIGN_CAPACITY *   \
-					BQ27621_SCALE_FACTOR))
+#define BQ27621_SCALED_DESIGN_CAPACITY \
+	((int)(BQ27621_DESIGN_CAPACITY * BQ27621_SCALE_FACTOR))
+#define BQ27621_SCALED_DESIGN_ENERGY \
+	((int)(BQ27621_DESIGN_CAPACITY * BQ27621_SCALE_FACTOR))
 
 /*
  *Everything is LSB first.  Parameters need to be converted.
@@ -139,11 +144,11 @@
  * The values from the data sheet are already LSB-first.
  */
 
-#define ENDIAN_SWAP_2B(x)     ((((x) & 0xff) << 8) | (((x) & 0xff00) >> 8))
-#define DESIGN_CAPACITY       ENDIAN_SWAP_2B(BQ27621_SCALED_DESIGN_CAPACITY)
-#define DESIGN_ENERGY         ENDIAN_SWAP_2B(BQ27621_SCALED_DESIGN_ENERGY)
-#define TAPER_RATE            ENDIAN_SWAP_2B(BQ27621_TAPER_RATE)
-#define TERMINATE_VOLTAGE     ENDIAN_SWAP_2B(BQ27621_TERMINATE_VOLTAGE)
+#define ENDIAN_SWAP_2B(x) ((((x)&0xff) << 8) | (((x)&0xff00) >> 8))
+#define DESIGN_CAPACITY ENDIAN_SWAP_2B(BQ27621_SCALED_DESIGN_CAPACITY)
+#define DESIGN_ENERGY ENDIAN_SWAP_2B(BQ27621_SCALED_DESIGN_ENERGY)
+#define TAPER_RATE ENDIAN_SWAP_2B(BQ27621_TAPER_RATE)
+#define TERMINATE_VOLTAGE ENDIAN_SWAP_2B(BQ27621_TERMINATE_VOLTAGE)
 
 struct battery_info battery_params;
 
@@ -192,7 +197,7 @@ static int bq27621_probe(void)
 static inline int bq27621_unseal(void)
 {
 	return bq27621_write(REG_CTRL, CONTROL_UNSEAL) |
-				bq27621_write(REG_CTRL, CONTROL_UNSEAL);
+	       bq27621_write(REG_CTRL, CONTROL_UNSEAL);
 }
 
 static int bq27621_enter_config_update(void)
@@ -200,8 +205,9 @@ static int bq27621_enter_config_update(void)
 	int tries, flags = 0, rv = EC_SUCCESS;
 
 	/* Enter Config Update Mode (Can take up to a second) */
-	for (tries = 2000; tries > 0 && !(flags & FLAGS_CFGUPD) &&
-					(rv == EC_SUCCESS); tries--) {
+	for (tries = 2000;
+	     tries > 0 && !(flags & FLAGS_CFGUPD) && (rv == EC_SUCCESS);
+	     tries--) {
 		rv |= bq27621_write(REG_CTRL, CONTROL_SET_CFGUPDATE);
 		rv |= bq27621_read(REG_FLAGS, &flags);
 	}
@@ -255,7 +261,7 @@ static int bq27621_seal(void)
 	rv = bq27621_read8(REGISTERS_BLOCK_OP_CONFIG_B, &param);
 	checksum -= param; /* 1B */
 
-	param |= 1<<5; /* Set DEF_SEAL */
+	param |= 1 << 5; /* Set DEF_SEAL */
 
 	rv = bq27621_write8(REGISTERS_BLOCK_OP_CONFIG_B, param);
 	checksum += param; /* 1B */
@@ -273,7 +279,7 @@ static int bq27621_seal(void)
 	return rv;
 }
 
-#define CHECKSUM_2B(x) ((x & 0xff) + ((x>>8) & 0xff))
+#define CHECKSUM_2B(x) ((x & 0xff) + ((x >> 8) & 0xff))
 
 static int bq27621_init(void)
 {
@@ -308,18 +314,18 @@ static int bq27621_init(void)
 
 			if (BQ27621_CHEM_ID == 0x1210)
 				rv |= bq27621_write(REG_CTRL,
-					CONTROL_ALT_CHEM1);
+						    CONTROL_ALT_CHEM1);
 			if (BQ27621_CHEM_ID == 0x0354)
 				rv |= bq27621_write(REG_CTRL,
-					CONTROL_ALT_CHEM2);
+						    CONTROL_ALT_CHEM2);
 
-		/*
-		 * The datasheet recommends checking the status here.
-		 *
-		 * If the CHEMCHG is active, it wasn't successful.
-		 *
-		 * There's no recommendation for what to do if it isn't.
-		 */
+			/*
+			 * The datasheet recommends checking the status here.
+			 *
+			 * If the CHEMCHG is active, it wasn't successful.
+			 *
+			 * There's no recommendation for what to do if it isn't.
+			 */
 
 			rv |= bq27621_write(REG_CTRL, CONTROL_EXIT_CFGUPDATE);
 		}
@@ -374,7 +380,6 @@ static int bq27621_init(void)
 
 	checksum = 0xff - (0xff & checksum);
 
-
 	if (rv)
 		return rv;
 
@@ -403,7 +408,7 @@ static void probe_type_id_init(void)
 
 	if (rv) { /* Try it once more */
 		rv = bq27621_write(REG_CTRL, CONTROL_RESET);
-	  rv |= bq27621_init();
+		rv |= bq27621_init();
 	}
 }
 
@@ -555,14 +560,14 @@ int battery_wait_for_stable(void)
 }
 
 #ifdef CONFIG_CMD_BATDEBUG
-	#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args)
 #else
-	#define CPRINTF(format, args...)
+#define CPRINTF(format, args...)
 #endif
 
 #ifdef CONFIG_CMD_BATDEBUG
 
-static int command_fgunseal(int argc, char **argv)
+static int command_fgunseal(int argc, const char **argv)
 {
 	int rv = EC_SUCCESS;
 
@@ -574,11 +579,9 @@ static int command_fgunseal(int argc, char **argv)
 	return rv;
 }
 
-DECLARE_CONSOLE_COMMAND(fgunseal, command_fgunseal,
-			"",
-			"Unseal the fg");
+DECLARE_CONSOLE_COMMAND(fgunseal, command_fgunseal, "", "Unseal the fg");
 
-static int command_fgseal(int argc, char **argv)
+static int command_fgseal(int argc, const char **argv)
 {
 	int rv = EC_SUCCESS;
 
@@ -590,11 +593,9 @@ static int command_fgseal(int argc, char **argv)
 	return rv;
 }
 
-DECLARE_CONSOLE_COMMAND(fgseal, command_fgseal,
-			"",
-			"Seal the fg");
+DECLARE_CONSOLE_COMMAND(fgseal, command_fgseal, "", "Seal the fg");
 
-static int command_fginit(int argc, char **argv)
+static int command_fginit(int argc, const char **argv)
 {
 	int rv = EC_SUCCESS;
 	int force = 0;
@@ -625,11 +626,9 @@ static int command_fginit(int argc, char **argv)
 	return rv;
 }
 
-DECLARE_CONSOLE_COMMAND(fginit, command_fginit,
-			"[force]",
-			"Initialize the fg");
+DECLARE_CONSOLE_COMMAND(fginit, command_fginit, "[force]", "Initialize the fg");
 
-static int command_fgprobe(int argc, char **argv)
+static int command_fgprobe(int argc, const char **argv)
 {
 	int rv = EC_SUCCESS;
 
@@ -641,11 +640,9 @@ static int command_fgprobe(int argc, char **argv)
 	return rv;
 }
 
-DECLARE_CONSOLE_COMMAND(fgprobe, command_fgprobe,
-			"",
-			"Probe the fg");
+DECLARE_CONSOLE_COMMAND(fgprobe, command_fgprobe, "", "Probe the fg");
 
-static int command_fgrd(int argc, char **argv)
+static int command_fgrd(int argc, const char **argv)
 {
 	int cmd, len;
 	int rv = EC_SUCCESS;
@@ -675,11 +672,10 @@ static int command_fgrd(int argc, char **argv)
 	return rv;
 }
 
-DECLARE_CONSOLE_COMMAND(fgrd, command_fgrd,
-			"cmd len",
+DECLARE_CONSOLE_COMMAND(fgrd, command_fgrd, "cmd len",
 			"Read _len_ words from the fg");
 
-static int command_fgcmd(int argc, char **argv)
+static int command_fgcmd(int argc, const char **argv)
 {
 	int cmd, data, byte = 0;
 	char *e;
@@ -708,14 +704,12 @@ static int command_fgcmd(int argc, char **argv)
 		CPRINTF("Write 2 bytes @0xaa %0x: 0x%0x\n", cmd, data);
 		return bq27621_write(cmd, data);
 	}
-
 }
 
-DECLARE_CONSOLE_COMMAND(fgcmd, command_fgcmd,
-			"cmd data [byte]",
+DECLARE_CONSOLE_COMMAND(fgcmd, command_fgcmd, "cmd data [byte]",
 			"Send a cmd to the fg");
 
-static int command_fgcmdrd(int argc, char **argv)
+static int command_fgcmdrd(int argc, const char **argv)
 {
 	int cmd, data, val;
 	int rv = EC_SUCCESS;
@@ -739,9 +733,8 @@ static int command_fgcmdrd(int argc, char **argv)
 	return rv;
 }
 
-DECLARE_CONSOLE_COMMAND(fgcmdrd, command_fgcmdrd,
-			"cmd data",
-			"Send a 2-byte cmd to the fg, read back the 2-byte result");
+DECLARE_CONSOLE_COMMAND(
+	fgcmdrd, command_fgcmdrd, "cmd data",
+	"Send a 2-byte cmd to the fg, read back the 2-byte result");
 
 #endif /* CONFIG_CMD_BATDEBUG */
-
diff --git a/driver/battery/bq4050.c b/driver/battery/bq4050.c
index 684ade47e6..9ba9a7304c 100644
--- a/driver/battery/bq4050.c
+++ b/driver/battery/bq4050.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -18,9 +18,8 @@ int battery_bq4050_imbalance_mv(void)
 	 * returns a voltage for each cell, regardless of the number of cells
 	 * actually installed in the pack.  Unpopulated cells read exactly zero.
 	 */
-	static const uint8_t cell_voltage_address[4] = {
-		0x3c, 0x3d, 0x3e, 0x3f
-	};
+	static const uint8_t cell_voltage_address[4] = { 0x3c, 0x3d, 0x3e,
+							 0x3f };
 	int i, res, cell_voltage;
 	int n_cells = 0;
 	int max_voltage = 0;
@@ -36,4 +35,3 @@ int battery_bq4050_imbalance_mv(void)
 	}
 	return (n_cells == 0) ? 0 : max_voltage - min_voltage;
 }
-
diff --git a/driver/battery/max17055.c b/driver/battery/max17055.c
index bb0b941937..4610be64b6 100644
--- a/driver/battery/max17055.c
+++ b/driver/battery/max17055.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -6,6 +6,7 @@
  */
 
 #include "battery.h"
+#include "builtin/assert.h"
 #include "console.h"
 #include "extpower.h"
 #include "hooks.h"
@@ -16,13 +17,13 @@
 #include "util.h"
 
 /* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 /*
  * For max17055 to finish battery presence detection, this is the minimal time
  * we have to wait since the last POR. LSB = 175ms.
  */
-#define RELIABLE_BATT_DETECT_TIME	0x10
+#define RELIABLE_BATT_DETECT_TIME 0x10
 
 /*
  * Convert the register values to the units that match
@@ -30,50 +31,48 @@
  */
 
 /* Voltage reg value to mV */
-#define VOLTAGE_CONV(REG)       ((REG * 5) >> 6)
+#define VOLTAGE_CONV(REG) ((REG * 5) >> 6)
 /* Current reg value to mA */
-#define CURRENT_CONV(REG)       (((REG * 25) >> 4) / BATTERY_MAX17055_RSENSE)
+#define CURRENT_CONV(REG) (((REG * 25) >> 4) / BATTERY_MAX17055_RSENSE)
 /* Capacity reg value to mAh */
-#define CAPACITY_CONV(REG)      (REG * 5 / BATTERY_MAX17055_RSENSE)
+#define CAPACITY_CONV(REG) (REG * 5 / BATTERY_MAX17055_RSENSE)
 /* Time reg value to minute */
-#define TIME_CONV(REG)          ((REG * 3) >> 5)
+#define TIME_CONV(REG) ((REG * 3) >> 5)
 /* Temperature reg value to 0.1K */
-#define TEMPERATURE_CONV(REG)   (((REG * 10) >> 8) + 2731)
+#define TEMPERATURE_CONV(REG) (((REG * 10) >> 8) + 2731)
 /* Percentage reg value to 1% */
-#define PERCENTAGE_CONV(REG)    (REG >> 8)
+#define PERCENTAGE_CONV(REG) (REG >> 8)
 /* Cycle count reg value (LSB = 1%) to absolute count (100%) */
-#define CYCLE_COUNT_CONV(REG)	((REG * 5) >> 9)
+#define CYCLE_COUNT_CONV(REG) ((REG * 5) >> 9)
 
 /* Useful macros */
-#define MAX17055_READ_DEBUG(offset, ptr_reg) \
-	do { \
-		if (max17055_read(offset, ptr_reg)) { \
-			CPRINTS("%s: failed to read reg %02x", \
-				__func__, offset); \
-			return; \
-		} \
+#define MAX17055_READ_DEBUG(offset, ptr_reg)                             \
+	do {                                                             \
+		if (max17055_read(offset, ptr_reg)) {                    \
+			CPRINTS("%s: failed to read reg %02x", __func__, \
+				offset);                                 \
+			return;                                          \
+		}                                                        \
 	} while (0)
-#define MAX17055_WRITE_DEBUG(offset, reg) \
-	do { \
-		if (max17055_write(offset, reg)) { \
-			CPRINTS("%s: failed to read reg %02x", \
-				__func__, offset); \
-			return; \
-		} \
+#define MAX17055_WRITE_DEBUG(offset, reg)                                \
+	do {                                                             \
+		if (max17055_write(offset, reg)) {                       \
+			CPRINTS("%s: failed to read reg %02x", __func__, \
+				offset);                                 \
+			return;                                          \
+		}                                                        \
 	} while (0)
 
 static int fake_state_of_charge = -1;
 
 static int max17055_read(int offset, int *data)
 {
-	return i2c_read16(I2C_PORT_BATTERY, MAX17055_ADDR_FLAGS,
-			  offset, data);
+	return i2c_read16(I2C_PORT_BATTERY, MAX17055_ADDR_FLAGS, offset, data);
 }
 
 static int max17055_write(int offset, int data)
 {
-	return i2c_write16(I2C_PORT_BATTERY, MAX17055_ADDR_FLAGS,
-			   offset, data);
+	return i2c_write16(I2C_PORT_BATTERY, MAX17055_ADDR_FLAGS, offset, data);
 }
 
 /* Return 1 if the device id is correct. */
@@ -94,10 +93,13 @@ int battery_device_name(char *device_name, int buf_size)
 	int rv;
 
 	rv = max17055_read(REG_DEVICE_NAME, &dev_id);
-	if (!rv)
-		snprintf(device_name, buf_size, "0x%04x", dev_id);
+	if (rv != EC_SUCCESS)
+		return rv;
 
-	return rv;
+	if (snprintf(device_name, buf_size, "0x%04x", dev_id) <= 0)
+		return EC_ERROR_UNKNOWN;
+
+	return EC_SUCCESS;
 }
 
 int battery_state_of_charge_abs(int *percent)
@@ -269,7 +271,7 @@ enum battery_present battery_is_present(void)
 void battery_get_params(struct batt_params *batt)
 {
 	int reg = 0;
-	struct batt_params batt_new = {0};
+	struct batt_params batt_new = { 0 };
 
 	/*
 	 * Assuming the battery is responsive as long as
@@ -293,7 +295,8 @@ void battery_get_params(struct batt_params *batt)
 		batt_new.flags |= BATT_FLAG_BAD_STATE_OF_CHARGE;
 
 	batt_new.state_of_charge = fake_state_of_charge >= 0 ?
-				fake_state_of_charge : PERCENTAGE_CONV(reg);
+					   fake_state_of_charge :
+					   PERCENTAGE_CONV(reg);
 
 	if (max17055_read(REG_VOLTAGE, &reg))
 		batt_new.flags |= BATT_FLAG_BAD_VOLTAGE;
@@ -319,8 +322,7 @@ void battery_get_params(struct batt_params *batt)
 	 * and battery isn't full (and we read them all correctly).
 	 */
 	if (!(batt_new.flags & BATT_FLAG_BAD_STATE_OF_CHARGE) &&
-	    batt_new.desired_voltage &&
-	    batt_new.desired_current &&
+	    batt_new.desired_voltage && batt_new.desired_current &&
 	    batt_new.state_of_charge < BATTERY_LEVEL_FULL)
 		batt_new.flags |= BATT_FLAG_WANT_CHARGE;
 
diff --git a/driver/battery/max17055.h b/driver/battery/max17055.h
index 0f97fb90f0..6828ed6502 100644
--- a/driver/battery/max17055.h
+++ b/driver/battery/max17055.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,105 +8,105 @@
 #ifndef __CROS_EC_MAX17055_H
 #define __CROS_EC_MAX17055_H
 
-#define MAX17055_ADDR_FLAGS         0x36
-#define MAX17055_DEVICE_ID          0x4010
-#define MAX17055_OCV_TABLE_SIZE     48
-
-#define REG_STATUS                  0x00
-#define REG_VALRTTH                 0x01
-#define REG_TALRTTH                 0x02
-#define REG_SALRTTH                 0x03
-#define REG_AT_RATE                 0x04
-#define REG_REMAINING_CAPACITY      0x05
-#define REG_STATE_OF_CHARGE         0x06
-#define REG_TEMPERATURE             0x08
-#define REG_VOLTAGE                 0x09
-#define REG_CURRENT                 0x0a
-#define REG_AVERAGE_CURRENT         0x0b
-#define REG_MIXCAP                  0x0f
-#define REG_FULL_CHARGE_CAPACITY    0x10
-#define REG_TIME_TO_EMPTY           0x11
-#define REG_QR_TABLE00              0x12
-#define REG_CONFIG                  0x1D
-#define REG_AVERAGE_TEMPERATURE     0x16
-#define REG_CYCLE_COUNT             0x17
-#define REG_DESIGN_CAPACITY         0x18
-#define REG_AVERAGE_VOLTAGE         0x19
-#define REG_MAX_MIN_TEMP            0x1a
-#define REG_MAX_MIN_VOLT            0x1b
-#define REG_MAX_MIN_CURR            0x1c
-#define REG_CHARGE_TERM_CURRENT     0x1e
-#define REG_TIME_TO_FULL            0x20
-#define REG_DEVICE_NAME             0x21
-#define REG_QR_TABLE10              0x22
-#define REG_FULLCAPNOM              0x23
-#define REG_LEARNCFG                0x28
-#define REG_QR_TABLE20              0x32
-#define REG_RCOMP0                  0x38
-#define REG_TEMPCO                  0x39
-#define REG_EMPTY_VOLTAGE           0x3a
-#define REG_FSTAT                   0x3d
-#define REG_TIMER                   0x3e
-#define REG_QR_TABLE30              0x42
-#define REG_DQACC                   0x45
-#define REG_DPACC                   0x46
-#define REG_VFSOC0                  0x48
-#define REG_COMMAND                 0x60
-#define REG_LOCK1                   0x62
-#define REG_LOCK2                   0x63
-#define REG_OCV_TABLE_START         0x80
-#define REG_STATUS2                 0xb0
-#define REG_IALRTTH                 0xb4
-#define REG_HIBCFG                  0xba
-#define REG_CONFIG2                 0xbb
-#define REG_TIMERH                  0xbe
-#define REG_MODELCFG                0xdb
-#define REG_VFSOC                   0xff
+#define MAX17055_ADDR_FLAGS 0x36
+#define MAX17055_DEVICE_ID 0x4010
+#define MAX17055_OCV_TABLE_SIZE 48
+
+#define REG_STATUS 0x00
+#define REG_VALRTTH 0x01
+#define REG_TALRTTH 0x02
+#define REG_SALRTTH 0x03
+#define REG_AT_RATE 0x04
+#define REG_REMAINING_CAPACITY 0x05
+#define REG_STATE_OF_CHARGE 0x06
+#define REG_TEMPERATURE 0x08
+#define REG_VOLTAGE 0x09
+#define REG_CURRENT 0x0a
+#define REG_AVERAGE_CURRENT 0x0b
+#define REG_MIXCAP 0x0f
+#define REG_FULL_CHARGE_CAPACITY 0x10
+#define REG_TIME_TO_EMPTY 0x11
+#define REG_QR_TABLE00 0x12
+#define REG_CONFIG 0x1D
+#define REG_AVERAGE_TEMPERATURE 0x16
+#define REG_CYCLE_COUNT 0x17
+#define REG_DESIGN_CAPACITY 0x18
+#define REG_AVERAGE_VOLTAGE 0x19
+#define REG_MAX_MIN_TEMP 0x1a
+#define REG_MAX_MIN_VOLT 0x1b
+#define REG_MAX_MIN_CURR 0x1c
+#define REG_CHARGE_TERM_CURRENT 0x1e
+#define REG_TIME_TO_FULL 0x20
+#define REG_DEVICE_NAME 0x21
+#define REG_QR_TABLE10 0x22
+#define REG_FULLCAPNOM 0x23
+#define REG_LEARNCFG 0x28
+#define REG_QR_TABLE20 0x32
+#define REG_RCOMP0 0x38
+#define REG_TEMPCO 0x39
+#define REG_EMPTY_VOLTAGE 0x3a
+#define REG_FSTAT 0x3d
+#define REG_TIMER 0x3e
+#define REG_QR_TABLE30 0x42
+#define REG_DQACC 0x45
+#define REG_DPACC 0x46
+#define REG_VFSOC0 0x48
+#define REG_COMMAND 0x60
+#define REG_LOCK1 0x62
+#define REG_LOCK2 0x63
+#define REG_OCV_TABLE_START 0x80
+#define REG_STATUS2 0xb0
+#define REG_IALRTTH 0xb4
+#define REG_HIBCFG 0xba
+#define REG_CONFIG2 0xbb
+#define REG_TIMERH 0xbe
+#define REG_MODELCFG 0xdb
+#define REG_VFSOC 0xff
 
 /* Status reg (0x00) flags */
-#define STATUS_POR                  BIT(1)
-#define STATUS_IMN                  BIT(2)
-#define STATUS_BST                  BIT(3)
-#define STATUS_IMX                  BIT(6)
-#define STATUS_VMN                  BIT(8)
-#define STATUS_TMN                  BIT(9)
-#define STATUS_SMN                  BIT(10)
-#define STATUS_VMX                  BIT(12)
-#define STATUS_TMX                  BIT(13)
-#define STATUS_SMX                  BIT(14)
-#define STATUS_ALL_ALRT                                                        \
-	(STATUS_IMN | STATUS_IMX | STATUS_VMN | STATUS_VMX | STATUS_TMN |      \
+#define STATUS_POR BIT(1)
+#define STATUS_IMN BIT(2)
+#define STATUS_BST BIT(3)
+#define STATUS_IMX BIT(6)
+#define STATUS_VMN BIT(8)
+#define STATUS_TMN BIT(9)
+#define STATUS_SMN BIT(10)
+#define STATUS_VMX BIT(12)
+#define STATUS_TMX BIT(13)
+#define STATUS_SMX BIT(14)
+#define STATUS_ALL_ALRT                                                   \
+	(STATUS_IMN | STATUS_IMX | STATUS_VMN | STATUS_VMX | STATUS_TMN | \
 	 STATUS_TMX | STATUS_SMN | STATUS_SMX)
 
 /* Alert disable values (0x01, 0x02, 0x03, 0xb4) */
-#define VALRT_DISABLE               0xff00
-#define TALRT_DISABLE               0x7f80
-#define SALRT_DISABLE               0xff00
-#define IALRT_DISABLE               0x7f80
+#define VALRT_DISABLE 0xff00
+#define TALRT_DISABLE 0x7f80
+#define SALRT_DISABLE 0xff00
+#define IALRT_DISABLE 0x7f80
 
 /* Config reg (0x1d) flags */
-#define CONF_AEN                    BIT(2)
-#define CONF_IS                     BIT(11)
-#define CONF_VS                     BIT(12)
-#define CONF_TS                     BIT(13)
-#define CONF_SS                     BIT(14)
-#define CONF_TSEL                   BIT(15)
-#define CONF_ALL_STICKY             (CONF_IS | CONF_VS | CONF_TS | CONF_SS)
+#define CONF_AEN BIT(2)
+#define CONF_IS BIT(11)
+#define CONF_VS BIT(12)
+#define CONF_TS BIT(13)
+#define CONF_SS BIT(14)
+#define CONF_TSEL BIT(15)
+#define CONF_ALL_STICKY (CONF_IS | CONF_VS | CONF_TS | CONF_SS)
 
 /* FStat reg (0x3d) flags */
-#define FSTAT_DNR                   0x0001
-#define FSTAT_FQ                    0x0080
+#define FSTAT_DNR 0x0001
+#define FSTAT_FQ 0x0080
 
 /* Config2 reg (0xbb) flags */
-#define CONFIG2_LDMDL               BIT(5)
+#define CONFIG2_LDMDL BIT(5)
 
 /* ModelCfg reg (0xdb) flags */
-#define MODELCFG_REFRESH            BIT(15)
-#define MODELCFG_VCHG               BIT(10)
+#define MODELCFG_REFRESH BIT(15)
+#define MODELCFG_VCHG BIT(10)
 
 /* Smart battery status bits (sbs reg 0x16) */
-#define BATTERY_DISCHARGING         0x40
-#define BATTERY_FULLY_CHARGED       0x20
+#define BATTERY_DISCHARGING 0x40
+#define BATTERY_FULLY_CHARGED 0x20
 
 /*
  * Before we have the battery fully characterized, we use these macros to
@@ -125,28 +125,27 @@
  * VE. max17055 reenables empty detection when the cell voltage rises above VR.
  * VE ranges from 0 to 5110mV, and VR ranges from 0 to 5080mV.
  */
-#define MAX17055_VEMPTY_REG(ve_mv, vr_mv) \
-	(((ve_mv / 10) << 7) | (vr_mv / 40))
+#define MAX17055_VEMPTY_REG(ve_mv, vr_mv) (((ve_mv / 10) << 7) | (vr_mv / 40))
 
 #define MAX17055_MAX_MIN_REG(mx, mn) ((((int16_t)(mx)) << 8) | ((mn)))
 /* Converts voltages alert range for VALRTTH_REG */
 #define MAX17055_VALRTTH_RESOLUTION 20
-#define MAX17055_VALRTTH_REG(mx, mn)                                           \
-	MAX17055_MAX_MIN_REG((uint8_t)(mx / MAX17055_VALRTTH_RESOLUTION),      \
+#define MAX17055_VALRTTH_REG(mx, mn)                                      \
+	MAX17055_MAX_MIN_REG((uint8_t)(mx / MAX17055_VALRTTH_RESOLUTION), \
 			     (uint8_t)(mn / MAX17055_VALRTTH_RESOLUTION))
 /* Converts temperature alert range for TALRTTH_REG */
-#define MAX17055_TALRTTH_REG(mx, mn)                                           \
+#define MAX17055_TALRTTH_REG(mx, mn) \
 	MAX17055_MAX_MIN_REG((int8_t)(mx), (int8_t)(mn))
 /* Converts state-of-charge alert range for SALRTTH_REG */
-#define MAX17055_SALRTTH_REG(mx, mn)                                           \
+#define MAX17055_SALRTTH_REG(mx, mn) \
 	MAX17055_MAX_MIN_REG((uint8_t)(mx), (uint8_t)(mn))
 /* Converts current alert range for IALRTTH_REG */
 /* Current resolution: 0.4mV/RSENSE */
 #define MAX17055_IALRTTH_MUL (10 * BATTERY_MAX17055_RSENSE)
 #define MAX17055_IALRTTH_DIV 4
-#define MAX17055_IALRTTH_REG(mx, mn)                                           \
-	MAX17055_MAX_MIN_REG(                                                  \
-		(int8_t)(mx * MAX17055_IALRTTH_MUL / MAX17055_IALRTTH_DIV),    \
+#define MAX17055_IALRTTH_REG(mx, mn)                                        \
+	MAX17055_MAX_MIN_REG(                                               \
+		(int8_t)(mx * MAX17055_IALRTTH_MUL / MAX17055_IALRTTH_DIV), \
 		(int8_t)(mn * MAX17055_IALRTTH_MUL / MAX17055_IALRTTH_DIV))
 
 /*
diff --git a/driver/battery/mm8013.c b/driver/battery/mm8013.c
index 04503da2f5..5d9f6e7a8d 100644
--- a/driver/battery/mm8013.c
+++ b/driver/battery/mm8013.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -34,8 +34,8 @@ static int mm8013_read_block(int offset, uint8_t *data, int len)
 {
 	int rv;
 
-	rv = i2c_read_block(I2C_PORT_BATTERY, MM8013_ADDR_FLAGS,
-			    offset, data, len);
+	rv = i2c_read_block(I2C_PORT_BATTERY, MM8013_ADDR_FLAGS, offset, data,
+			    len);
 	usleep(I2C_WAIT_TIME);
 	if (rv)
 		return rv;
@@ -52,8 +52,8 @@ static int battery_current(int *current)
 	int16_t tmp;
 	int rv;
 
-	rv = mm8013_read_block(REG_AVERAGE_CURRENT,
-			(uint8_t *)&tmp, sizeof(int16_t));
+	rv = mm8013_read_block(REG_AVERAGE_CURRENT, (uint8_t *)&tmp,
+			       sizeof(int16_t));
 	if (rv)
 		return rv;
 	*current = tmp;
@@ -66,8 +66,8 @@ int battery_device_name(char *device_name, int buf_size)
 	int rv;
 	char out_buf[BATTERY_PACK_INFO_LENGTH + 1];
 
-	rv = mm8013_read_block(REG_PRODUCT_INFORMATION,
-			(uint8_t *)out_buf, BATTERY_PACK_INFO_LENGTH);
+	rv = mm8013_read_block(REG_PRODUCT_INFORMATION, (uint8_t *)out_buf,
+			       BATTERY_PACK_INFO_LENGTH);
 	if (rv)
 		return rv;
 
@@ -181,7 +181,7 @@ enum battery_present battery_is_present(void)
 
 void battery_get_params(struct batt_params *batt)
 {
-	struct batt_params batt_new = {0};
+	struct batt_params batt_new = { 0 };
 	int flag = 0;
 
 	/*
diff --git a/driver/battery/mm8013.h b/driver/battery/mm8013.h
index 2ffaca7b5d..40cb31a355 100644
--- a/driver/battery/mm8013.h
+++ b/driver/battery/mm8013.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,33 +8,32 @@
 #ifndef __CROS_EC_MM8013_H
 #define __CROS_EC_MM8013_H
 
-#define MM8013_ADDR_FLAGS           0x55
+#define MM8013_ADDR_FLAGS 0x55
 
-#define REG_TEMPERATURE             0x06
-#define REG_VOLTAGE                 0x08
-#define REG_FLAGS                   0x0a
-#define REG_FULL_CHARGE_CAPACITY    0x0e
-#define REG_REMAINING_CAPACITY      0x10
-#define REG_AVERAGE_CURRENT         0x14
-#define REG_AVERAGE_TIME_TO_EMPTY   0x16
-#define REG_AVERAGE_TIME_TO_FULL    0x18
-#define REG_STATE_OF_CHARGE         0x2c
-#define REG_CYCLE_COUNT             0x2a
-#define REG_DESIGN_CAPACITY         0x3c
-#define REG_PRODUCT_INFORMATION     0x64
+#define REG_TEMPERATURE 0x06
+#define REG_VOLTAGE 0x08
+#define REG_FLAGS 0x0a
+#define REG_FULL_CHARGE_CAPACITY 0x0e
+#define REG_REMAINING_CAPACITY 0x10
+#define REG_AVERAGE_CURRENT 0x14
+#define REG_AVERAGE_TIME_TO_EMPTY 0x16
+#define REG_AVERAGE_TIME_TO_FULL 0x18
+#define REG_STATE_OF_CHARGE 0x2c
+#define REG_CYCLE_COUNT 0x2a
+#define REG_DESIGN_CAPACITY 0x3c
+#define REG_PRODUCT_INFORMATION 0x64
 
 /* Over Temperature in charge */
-#define MM8013_FLAG_OTC             BIT(15)
+#define MM8013_FLAG_OTC BIT(15)
 /* Over Temperature in discharge */
-#define MM8013_FLAG_OTD             BIT(14)
+#define MM8013_FLAG_OTD BIT(14)
 /* Over-charge */
-#define MM8013_FLAG_BATHI           BIT(13)
+#define MM8013_FLAG_BATHI BIT(13)
 /* Full Charge */
-#define MM8013_FLAG_FC              BIT(9)
+#define MM8013_FLAG_FC BIT(9)
 /* Charge allowed */
-#define MM8013_FLAG_CHG             BIT(8)
+#define MM8013_FLAG_CHG BIT(8)
 /* Discharge */
-#define MM8013_FLAG_DSG             BIT(0)
-
+#define MM8013_FLAG_DSG BIT(0)
 
 #endif /* __CROS_EC_MM8013_H */
diff --git a/driver/battery/smart.c b/driver/battery/smart.c
index b0ccec8de9..4d64c29efa 100644
--- a/driver/battery/smart.c
+++ b/driver/battery/smart.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -15,49 +15,67 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CHARGER, outstr);
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
-#define BATTERY_NO_RESPONSE_TIMEOUT	(1000*MSEC)
+#define BATTERY_NO_RESPONSE_TIMEOUT (1000 * MSEC)
 
 static int fake_state_of_charge = -1;
 static int fake_temperature = -1;
 
-static int battery_supports_pec(void)
+#ifdef CONFIG_SMBUS_PEC
+static void addr_flags_for_pec(uint16_t *addr_flags)
 {
 	static int supports_pec = -1;
 
-	if (!IS_ENABLED(CONFIG_SMBUS_PEC))
-		return 0;
-
 	if (supports_pec < 0) {
 		int spec_info;
 		int rv = i2c_read16(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS,
 				    SB_SPECIFICATION_INFO, &spec_info);
-		/* failed, assuming not support and try again later */
+		/* failed, assuming not supported and try again later */
 		if (rv)
-			return 0;
+			return;
 
 		supports_pec = (BATTERY_SPEC_VERSION(spec_info) ==
 				BATTERY_SPEC_VER_1_1_WITH_PEC);
 		CPRINTS("battery supports pec: %d", supports_pec);
 	}
-	return supports_pec;
+
+	if (supports_pec) {
+		*addr_flags |= I2C_FLAG_PEC;
+	}
 }
+/* macro to avoid calling a routine when config is disabled */
+#define ADDR_FLAGS_FOR_PEC(ADDR_FLAGS) addr_flags_for_pec(ADDR_FLAGS)
+
+#else
+/*
+ * don't call it at all - this allows compiler optimization to prune
+ * PEC address code
+ */
+#define ADDR_FLAGS_FOR_PEC(ADDR_FLAGS)
+
+#endif
 
 test_mockable int sb_read(int cmd, int *param)
 {
 	uint16_t addr_flags = BATTERY_ADDR_FLAGS;
 
 #ifdef CONFIG_BATTERY_CUT_OFF
+	/*
+	 * Ship mode command need to set continuously, can't be interfered
+	 * by another command.
+	 */
+	if (battery_cutoff_in_progress())
+		return EC_ERROR_ACCESS_DENIED;
+
 	/*
 	 * Some batteries would wake up after cut-off if we talk to it.
 	 */
 	if (battery_is_cut_off())
 		return EC_RES_ACCESS_DENIED;
 #endif
-	if (battery_supports_pec())
-		addr_flags |= I2C_FLAG_PEC;
 
+	ADDR_FLAGS_FOR_PEC(&addr_flags);
 	return i2c_read16(I2C_PORT_BATTERY, addr_flags, cmd, param);
 }
 
@@ -72,8 +90,8 @@ test_mockable int sb_write(int cmd, int param)
 	if (battery_is_cut_off())
 		return EC_RES_ACCESS_DENIED;
 #endif
-	if (battery_supports_pec())
-		addr_flags |= I2C_FLAG_PEC;
+
+	ADDR_FLAGS_FOR_PEC(&addr_flags);
 
 	return i2c_write16(I2C_PORT_BATTERY, addr_flags, cmd, param);
 }
@@ -83,18 +101,51 @@ int sb_read_string(int offset, uint8_t *data, int len)
 	uint16_t addr_flags = BATTERY_ADDR_FLAGS;
 
 #ifdef CONFIG_BATTERY_CUT_OFF
+	/*
+	 * Ship mode command need to set continuously, can't be interfered
+	 * by another command.
+	 */
+	if (battery_cutoff_in_progress())
+		return EC_ERROR_ACCESS_DENIED;
+
 	/*
 	 * Some batteries would wake up after cut-off if we talk to it.
 	 */
 	if (battery_is_cut_off())
 		return EC_RES_ACCESS_DENIED;
 #endif
-	if (battery_supports_pec())
-		addr_flags |= I2C_FLAG_PEC;
+
+	ADDR_FLAGS_FOR_PEC(&addr_flags);
 
 	return i2c_read_string(I2C_PORT_BATTERY, addr_flags, offset, data, len);
 }
 
+int sb_read_sized_block(int offset, uint8_t *data, int len)
+{
+	uint16_t addr_flags = BATTERY_ADDR_FLAGS;
+	int read_len = 0;
+
+	if (IS_ENABLED(CONFIG_BATTERY_CUT_OFF)) {
+		/*
+		 * Ship mode command need to set continuously, can't be
+		 * interfered by another command.
+		 */
+		if (battery_cutoff_in_progress())
+			return EC_ERROR_ACCESS_DENIED;
+
+		/*
+		 * Some batteries would wake up after cut-off if we talk to it.
+		 */
+		if (battery_is_cut_off())
+			return EC_RES_ACCESS_DENIED;
+	}
+
+	ADDR_FLAGS_FOR_PEC(&addr_flags);
+
+	return i2c_read_sized_block(I2C_PORT_BATTERY, addr_flags, offset, data,
+				    len, &read_len);
+}
+
 int sb_read_mfgacc(int cmd, int block, uint8_t *data, int len)
 {
 	int rv;
@@ -116,7 +167,43 @@ int sb_read_mfgacc(int cmd, int block, uint8_t *data, int len)
 	 * First two bytes returned are command sent,
 	 * rest are actual data LSB to MSB.
 	 */
-	rv = sb_read_string(block, data, len);
+	rv = sb_read_sized_block(block, data, len);
+	if (rv)
+		return rv;
+	if ((data[0] | data[1] << 8) != cmd)
+		return EC_ERROR_UNKNOWN;
+
+	return EC_SUCCESS;
+}
+
+int sb_read_mfgacc_block(int cmd, int block, uint8_t *data, int len)
+{
+	int rv;
+
+	uint8_t operation_status[3] = {
+		0x02,
+		cmd & 0xFF,
+		cmd >> 8,
+	};
+
+	/*
+	 * First two bytes returned from read are command sent hence read
+	 * doesn't yield anything if the length is less than 3 bytes.
+	 */
+	if (len < 3)
+		return EC_ERROR_INVAL;
+
+	/* Send manufacturer access command by the SMB block protocol */
+	rv = sb_write_block(block, operation_status, sizeof(operation_status));
+	if (rv)
+		return rv;
+
+	/*
+	 * Read data on the register block.
+	 * First two bytes returned are command sent,
+	 * rest are actual data LSB to MSB.
+	 */
+	rv = sb_read_sized_block(block, data, len);
 	if (rv)
 		return rv;
 	if ((data[0] | data[1] << 8) != cmd)
@@ -137,8 +224,7 @@ int sb_write_block(int reg, const uint8_t *val, int len)
 		return EC_RES_ACCESS_DENIED;
 #endif
 
-	if (battery_supports_pec())
-		addr_flags |= I2C_FLAG_PEC;
+	ADDR_FLAGS_FOR_PEC(&addr_flags);
 
 	/* TODO: implement smbus_write_block. */
 	return i2c_write_block(I2C_PORT_BATTERY, addr_flags, reg, val, len);
@@ -294,9 +380,12 @@ test_mockable int battery_manufacture_date(int *year, int *month, int *day)
 	/* battery date format:
 	 * ymd = day + month * 32 + (year - 1980) * 512
 	 */
-	*year  = (ymd >> 9) + 1980;
-	*month = (ymd >> 5) & 0xf;
-	*day   = ymd & 0x1f;
+	*year = ((ymd & MANUFACTURE_DATE_YEAR_MASK) >>
+		 MANUFACTURE_DATE_YEAR_SHIFT) +
+		MANUFACTURE_DATE_YEAR_OFFSET;
+	*month = (ymd & MANUFACTURE_DATE_MONTH_MASK) >>
+		 MANUFACTURE_DATE_MONTH_SHIFT;
+	*day = (ymd & MANUFACTURE_DATE_DAY_MASK) >> MANUFACTURE_DATE_DAY_SHIFT;
 
 	return EC_SUCCESS;
 }
@@ -318,7 +407,16 @@ test_mockable int battery_device_chemistry(char *dest, int size)
 	return sb_read_string(SB_DEVICE_CHEMISTRY, dest, size);
 }
 
-#ifdef CONFIG_CMD_PWR_AVG
+int battery_manufacturer_data(char *data, int size)
+{
+	return sb_read_string(SB_MANUFACTURER_DATA, data, size);
+}
+
+int battery_manufacturer_access(int cmd)
+{
+	return sb_write(SB_MANUFACTURER_ACCESS, cmd);
+}
+
 int battery_get_avg_current(void)
 {
 	int current;
@@ -328,6 +426,7 @@ int battery_get_avg_current(void)
 	return (int16_t)current;
 }
 
+#ifdef CONFIG_CMD_PWR_AVG
 /*
  * Technically returns only the instantaneous reading, but tests showed that
  * for the majority of charge states above 3% this varies by less than 40mV
@@ -356,25 +455,62 @@ static void apply_fake_state_of_charge(struct batt_params *batt)
 
 	batt->state_of_charge = fake_state_of_charge;
 	batt->remaining_capacity = full * fake_state_of_charge / 100;
+	battery_compensate_params(batt);
 	batt->flags &= ~BATT_FLAG_BAD_STATE_OF_CHARGE;
 	batt->flags &= ~BATT_FLAG_BAD_REMAINING_CAPACITY;
 }
 
+static bool battery_want_charge(struct batt_params *batt)
+{
+	if (batt->flags &
+	    (BATT_FLAG_BAD_DESIRED_VOLTAGE | BATT_FLAG_BAD_DESIRED_CURRENT |
+	     BATT_FLAG_BAD_STATE_OF_CHARGE))
+		return false;
+
+	/*
+	 * Charging allowed if both desired voltage and current are nonzero
+	 * and battery isn't full (and we read them all correctly).
+	 */
+	if (batt->desired_voltage && batt->desired_current &&
+	    batt->state_of_charge < BATTERY_LEVEL_FULL)
+		return true;
+
+	/*
+	 * TODO (crosbug.com/p/29467): remove this workaround for dead battery
+	 * that requests no voltage/current
+	 */
+	if (IS_ENABLED(CONFIG_BATTERY_REQUESTS_NIL_WHEN_DEAD)) {
+		if (batt->desired_voltage == 0 && batt->desired_current == 0 &&
+		    batt->state_of_charge == 0)
+			return true;
+	}
+
+	return false;
+}
+
 void battery_get_params(struct batt_params *batt)
 {
-	struct batt_params batt_new = {0};
+	struct batt_params batt_new;
 	int v;
 
-	if (sb_read(SB_TEMPERATURE, &batt_new.temperature)
-			&& fake_temperature < 0)
+	/*
+	 * Start with a copy so that only valid fields will be updated. Note
+	 * sb_read doesn't change the value if I2C fails. So, the current value
+	 * will be preserved.
+	 */
+	memcpy(&batt_new, batt, sizeof(*batt));
+	batt_new.flags &= ~BATT_FLAG_VOLATILE;
+
+	if (sb_read(SB_TEMPERATURE, &batt_new.temperature) &&
+	    fake_temperature < 0)
 		batt_new.flags |= BATT_FLAG_BAD_TEMPERATURE;
 
 	/* If temperature is faked, override with faked data */
 	if (fake_temperature >= 0)
 		batt_new.temperature = fake_temperature;
 
-	if (sb_read(SB_RELATIVE_STATE_OF_CHARGE, &batt_new.state_of_charge)
-	    && fake_state_of_charge < 0)
+	if (sb_read(SB_RELATIVE_STATE_OF_CHARGE, &batt_new.state_of_charge) &&
+	    fake_state_of_charge < 0)
 		batt_new.flags |= BATT_FLAG_BAD_STATE_OF_CHARGE;
 
 	if (sb_read(SB_VOLTAGE, &batt_new.voltage))
@@ -386,6 +522,9 @@ void battery_get_params(struct batt_params *batt)
 	else
 		batt_new.current = (int16_t)v;
 
+	if (sb_read(SB_AVERAGE_CURRENT, &v))
+		batt_new.flags |= BATT_FLAG_BAD_AVERAGE_CURRENT;
+
 	if (sb_read(SB_CHARGING_VOLTAGE, &batt_new.desired_voltage))
 		batt_new.flags |= BATT_FLAG_BAD_DESIRED_VOLTAGE;
 
@@ -410,7 +549,7 @@ void battery_get_params(struct batt_params *batt)
 		batt_new.flags |= BATT_FLAG_IMBALANCED_CELL;
 #endif
 
-#if defined(CONFIG_BATTERY_PRESENT_CUSTOM) ||	\
+#if defined(CONFIG_BATTERY_PRESENT_CUSTOM) || \
 	defined(CONFIG_BATTERY_PRESENT_GPIO)
 	/* Hardware can tell us for certain */
 	batt_new.is_present = battery_is_present();
@@ -422,33 +561,7 @@ void battery_get_params(struct batt_params *batt)
 		batt_new.is_present = BP_NOT_SURE;
 #endif
 
-	/*
-	 * Charging allowed if both desired voltage and current are nonzero
-	 * and battery isn't full (and we read them all correctly).
-	 */
-	if (!(batt_new.flags & (BATT_FLAG_BAD_DESIRED_VOLTAGE |
-				BATT_FLAG_BAD_DESIRED_CURRENT |
-				BATT_FLAG_BAD_STATE_OF_CHARGE)) &&
-#ifdef CONFIG_BATTERY_REQUESTS_NIL_WHEN_DEAD
-		/*
-		 * TODO (crosbug.com/p/29467): remove this workaround
-		 * for dead battery that requests no voltage/current
-		 */
-		((batt_new.desired_voltage &&
-			batt_new.desired_current &&
-			batt_new.state_of_charge < BATTERY_LEVEL_FULL) ||
-		(batt_new.desired_voltage == 0 &&
-			batt_new.desired_current == 0 &&
-#ifdef CONFIG_BATTERY_DEAD_UNTIL_VALUE
-			batt_new.state_of_charge < CONFIG_BATTERY_DEAD_UNTIL_VALUE)))
-#else
-			batt_new.state_of_charge == 0)))
-#endif
-#else
-	    batt_new.desired_voltage &&
-	    batt_new.desired_current &&
-	    batt_new.state_of_charge < BATTERY_LEVEL_FULL)
-#endif
+	if (battery_want_charge(&batt_new))
 		batt_new.flags |= BATT_FLAG_WANT_CHARGE;
 	else
 		/* Force both to zero */
@@ -474,22 +587,33 @@ int battery_wait_for_stable(void)
 	uint64_t wait_timeout = get_time().val + BATTERY_NO_RESPONSE_TIMEOUT;
 
 	CPRINTS("Wait for battery stabilized during %d",
-			 BATTERY_NO_RESPONSE_TIMEOUT);
+		BATTERY_NO_RESPONSE_TIMEOUT);
 	while (get_time().val < wait_timeout) {
 		/* Starting pinging battery */
-		if (battery_status(&status) == EC_SUCCESS) {
-			/* Battery is stable */
-			CPRINTS("battery responded with status %x", status);
-			return EC_SUCCESS;
+		if (battery_status(&status) != EC_SUCCESS) {
+			msleep(25); /* clock stretching could hold 25ms */
+			continue;
+		}
+
+#ifdef CONFIG_BATTERY_STBL_STAT
+		if (((status & CONFIG_BATT_ALARM_MASK1) ==
+		     CONFIG_BATT_ALARM_MASK1) ||
+		    ((status & CONFIG_BATT_ALARM_MASK2) ==
+		     CONFIG_BATT_ALARM_MASK2)) {
+			msleep(25);
+			continue;
 		}
-		msleep(25); /* clock stretching could hold 25ms */
+#endif
+		/* Battery is stable */
+		CPRINTS("battery responded with status %x", status);
+		return EC_SUCCESS;
 	}
-	CPRINTS("battery not responding");
+	CPRINTS("battery not responding with status %x", status);
 	return EC_ERROR_NOT_POWERED;
 }
 
 #if defined(CONFIG_CMD_BATTFAKE)
-static int command_battfake(int argc, char **argv)
+static int command_battfake(int argc, const char **argv)
 {
 	char *e;
 	int v;
@@ -511,7 +635,7 @@ DECLARE_CONSOLE_COMMAND(battfake, command_battfake,
 			"percent (-1 = use real level)",
 			"Set fake battery level");
 
-static int command_batttempfake(int argc, char **argv)
+static int command_batttempfake(int argc, const char **argv)
 {
 	char *e;
 	int t;
@@ -530,13 +654,14 @@ static int command_batttempfake(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(batttempfake, command_batttempfake,
-			"temperature (-1 = use real temperature)",
-			"Set fake battery temperature in deciKelvin (2731 = 273.1 K = 0 deg C)");
+DECLARE_CONSOLE_COMMAND(
+	batttempfake, command_batttempfake,
+	"temperature (-1 = use real temperature)",
+	"Set fake battery temperature in deciKelvin (2731 = 273.1 K = 0 deg C)");
 #endif
 
 #ifdef CONFIG_CMD_BATT_MFG_ACCESS
-static int command_batt_mfg_access_read(int argc, char **argv)
+static int command_batt_mfg_access_read(int argc, const char **argv)
 {
 	char *e;
 	uint8_t data[32];
@@ -579,86 +704,6 @@ DECLARE_CONSOLE_COMMAND(battmfgacc, command_batt_mfg_access_read,
 			"Read battery manufacture access data");
 #endif /* CONFIG_CMD_BATT_MFG_ACCESS */
 
-/*****************************************************************************/
-/* Smart battery pass-through
- */
-#ifdef CONFIG_SB_PASSTHROUGH
-static enum ec_status
-host_command_sb_read_word(struct host_cmd_handler_args *args)
-{
-	int rv;
-	int val;
-	const struct ec_params_sb_rd *p = args->params;
-	struct ec_response_sb_rd_word *r = args->response;
-
-	if (p->reg > 0x1c)
-		return EC_RES_INVALID_PARAM;
-	rv = sb_read(p->reg, &val);
-	if (rv)
-		return EC_RES_ERROR;
-
-	r->value = val;
-	args->response_size = sizeof(struct ec_response_sb_rd_word);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_SB_READ_WORD,
-		     host_command_sb_read_word,
-		     EC_VER_MASK(0));
-
-static enum ec_status
-host_command_sb_write_word(struct host_cmd_handler_args *args)
-{
-	int rv;
-	const struct ec_params_sb_wr_word *p = args->params;
-
-	if (p->reg > 0x1c)
-		return EC_RES_INVALID_PARAM;
-	rv = sb_write(p->reg, p->value);
-	if (rv)
-		return EC_RES_ERROR;
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_SB_WRITE_WORD,
-		     host_command_sb_write_word,
-		     EC_VER_MASK(0));
-
-static enum ec_status
-host_command_sb_read_block(struct host_cmd_handler_args *args)
-{
-	int rv;
-	const struct ec_params_sb_rd *p = args->params;
-	struct ec_response_sb_rd_block *r = args->response;
-
-	if ((p->reg != SB_MANUFACTURER_NAME) &&
-	    (p->reg != SB_DEVICE_NAME) &&
-	    (p->reg != SB_DEVICE_CHEMISTRY) &&
-	    (p->reg != SB_MANUFACTURER_DATA))
-		return EC_RES_INVALID_PARAM;
-	rv = sb_read_string(p->reg, r->data, 32);
-	if (rv)
-		return EC_RES_ERROR;
-
-	args->response_size = sizeof(struct ec_response_sb_rd_block);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_SB_READ_BLOCK,
-		     host_command_sb_read_block,
-		     EC_VER_MASK(0));
-
-static enum ec_status
-host_command_sb_write_block(struct host_cmd_handler_args *args)
-{
-	/* Not implemented */
-	return EC_RES_INVALID_COMMAND;
-}
-DECLARE_HOST_COMMAND(EC_CMD_SB_WRITE_BLOCK,
-		     host_command_sb_write_block,
-		     EC_VER_MASK(0));
-#endif
-
 #ifdef CONFIG_CMD_I2C_STRESS_TEST_BATTERY
 test_mockable int sb_i2c_test_read(int cmd, int *param)
 {
@@ -666,8 +711,8 @@ test_mockable int sb_i2c_test_read(int cmd, int *param)
 	int rv;
 
 	if (cmd == SB_DEVICE_CHEMISTRY) {
-		rv = battery_device_chemistry(chemistry,
-			sizeof(CONFIG_BATTERY_DEVICE_CHEMISTRY));
+		rv = battery_device_chemistry(
+			chemistry, sizeof(CONFIG_BATTERY_DEVICE_CHEMISTRY));
 		if (rv)
 			return rv;
 		if (strcasecmp(chemistry, CONFIG_BATTERY_DEVICE_CHEMISTRY))
@@ -677,7 +722,6 @@ test_mockable int sb_i2c_test_read(int cmd, int *param)
 		return EC_SUCCESS;
 	}
 
-
 	return sb_read(cmd, param);
 }
 
diff --git a/driver/bc12/max14637.c b/driver/bc12/max14637.c
index 91b5441a68..a2603c7973 100644
--- a/driver/bc12/max14637.c
+++ b/driver/bc12/max14637.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,23 +12,24 @@
  * the system will have to charge ramp.
  */
 
-#include "max14637.h"
-#include "cannonlake.h"
+#include "builtin/assert.h"
 #include "charge_manager.h"
 #include "chipset.h"
 #include "common.h"
 #include "console.h"
 #include "gpio.h"
 #include "hooks.h"
+#include "max14637.h"
 #include "power.h"
+#include "power/cannonlake.h"
 #include "task.h"
-#include "tcpm.h"
+#include "tcpm/tcpm.h"
 #include "timer.h"
 #include "usb_charge.h"
 #include "usb_pd.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 #if defined(CONFIG_CHARGE_RAMP_SW) || defined(CONFIG_CHARGE_RAMP_HW)
 /**
@@ -38,10 +39,10 @@
  * @return 1 if charger detect is activated (high when active high or
  *	low with active low), otherwise 0.
  */
-static int is_chg_det_activated(const struct max14637_config_t * const cfg)
+static int is_chg_det_activated(const struct max14637_config_t *const cfg)
 {
 	return !!gpio_get_level(cfg->chg_det_pin) ^
-		!!(cfg->flags & MAX14637_FLAGS_CHG_DET_ACTIVE_LOW);
+	       !!(cfg->flags & MAX14637_FLAGS_CHG_DET_ACTIVE_LOW);
 }
 #endif
 
@@ -52,24 +53,56 @@ static int is_chg_det_activated(const struct max14637_config_t * const cfg)
  * @param enable 1 to activate gpio (high for active high and low for active
  *	low).
  */
-static void activate_chip_enable(
-	const struct max14637_config_t * const cfg, const int enable)
+static void activate_chip_enable(const struct max14637_config_t *const cfg,
+				 const int enable)
 {
-	gpio_set_level(
-		cfg->chip_enable_pin,
-		!!enable ^ !!(cfg->flags & MAX14637_FLAGS_ENABLE_ACTIVE_LOW));
+	gpio_set_level(cfg->chip_enable_pin,
+		       !!enable ^ !!(cfg->flags &
+				     MAX14637_FLAGS_ENABLE_ACTIVE_LOW));
 }
 
 /**
- * Perform BC1.2 detection and update charge manager.
+ * Update BC1.2 detected status to charge manager.
  *
  * @param port: The Type-C port where VBUS is present.
  */
-static void bc12_detect(const int port)
+static void update_bc12_status_to_charger_manager(const int port)
 {
-	const struct max14637_config_t * const cfg = &max14637_config[port];
+	const struct max14637_config_t *const cfg = &max14637_config[port];
 	struct charge_port_info new_chg;
 
+	new_chg.voltage = USB_CHARGER_VOLTAGE_MV;
+#if defined(CONFIG_CHARGE_RAMP_SW) || defined(CONFIG_CHARGE_RAMP_HW)
+	/*
+	 * The driver assumes that CHG_AL_N and SW_OPEN are not connected,
+	 * therefore an activated CHG_DET indicates whether the source is NOT a
+	 * low-power standard downstream port (SDP). The system will have to
+	 * ramp the current to determine the limit.  The Type-C spec prohibits
+	 * proprietary methods now, therefore 1500mA is the max.
+	 */
+	new_chg.current = is_chg_det_activated(cfg) ? USB_CHARGER_MAX_CURR_MA :
+						      500;
+#else
+	/*
+	 * If the board doesn't support charge ramping, then assume the lowest
+	 * denominator; that is assume the charger detected is a weak dedicated
+	 * charging port (DCP) which can only supply 500mA.
+	 */
+	new_chg.current = 500;
+#endif /* !defined(CONFIG_CHARGE_RAMP_SW && CONFIG_CHARGE_RAMP_HW) */
+
+	charge_manager_update_charge(CHARGE_SUPPLIER_OTHER, port, &new_chg);
+}
+
+/**
+ * Perform BC1.2 detection.
+ *
+ * @param port: The Type-C port where VBUS is present.
+ */
+static void bc12_detect(const int port)
+{
+	const struct max14637_config_t *const cfg = &max14637_config[port];
+
 	/*
 	 * Enable the IC to begin detection and connect switches if
 	 * necessary. This is only necessary if the port power role is a
@@ -83,36 +116,16 @@ static void bc12_detect(const int port)
 	 */
 	msleep(100);
 	activate_chip_enable(cfg, 0);
-	msleep(1);
+	msleep(CONFIG_BC12_MAX14637_DELAY_FROM_OFF_TO_ON_MS);
 	activate_chip_enable(cfg, 1);
 
-	new_chg.voltage = USB_CHARGER_VOLTAGE_MV;
 #if defined(CONFIG_CHARGE_RAMP_SW) || defined(CONFIG_CHARGE_RAMP_HW)
 	/*
 	 * Apple or TomTom charger detection can take as long as 600ms.  Wait a
 	 * little bit longer for margin.
 	 */
 	msleep(630);
-
-	/*
-	 * The driver assumes that CHG_AL_N and SW_OPEN are not connected,
-	 * therefore an activated CHG_DET indicates whether the source is NOT a
-	 * low-power standard downstream port (SDP). The system will have to
-	 * ramp the current to determine the limit.  The Type-C spec prohibits
-	 * proprietary methods now, therefore 1500mA is the max.
-	 */
-	new_chg.current = is_chg_det_activated(cfg) ? USB_CHARGER_MAX_CURR_MA :
-						      500;
-#else
-	/*
-	 * If the board doesn't support charge ramping, then assume the lowest
-	 * denominator; that is assume the charger detected is a weak dedicated
-	 * charging port (DCP) which can only supply 500mA.
-	 */
-	new_chg.current = 500;
 #endif /* !defined(CONFIG_CHARGE_RAMP_SW && CONFIG_CHARGE_RAMP_HW) */
-
-	charge_manager_update_charge(CHARGE_SUPPLIER_OTHER, port, &new_chg);
 }
 
 /**
@@ -135,26 +148,36 @@ static void detect_or_power_down_ic(const int port)
 #endif /* !defined(CONFIG_USB_PD_VBUS_DETECT_TCPC) */
 
 	if (vbus_present) {
-#if defined(CONFIG_POWER_PP5000_CONTROL) && defined(HAS_TASK_CHIPSET)
+#if defined(CONFIG_POWER_PP5000_CONTROL) && defined(CONFIG_AP_POWER_CONTROL)
 		/* Turn on the 5V rail to allow the chip to be powered. */
 		power_5v_enable(task_get_current(), 1);
 #endif
-		if (pd_get_power_role(port) == PD_ROLE_SINK)
+		if (pd_get_power_role(port) == PD_ROLE_SINK) {
 			bc12_detect(port);
+			update_bc12_status_to_charger_manager(port);
+		}
 	} else {
 		/* Let charge manager know there's no more charge available. */
 		charge_manager_update_charge(CHARGE_SUPPLIER_OTHER, port, NULL);
-#if defined(CONFIG_POWER_PP5000_CONTROL) && defined(HAS_TASK_CHIPSET)
+		/*
+		 * If latest attached charger is PD Adapter then it would be
+		 * detected as DCP and data switch of USB2.0 would be open which
+		 * prevents USB 2.0 data path from working later. As a result,
+		 * bc12_detect() is called again here and SCP would be detected
+		 * due to D+/D- are NC (open) if nothing is attached then data
+		 * switch of USB2.0 can be kept close from now on.
+		 */
+		bc12_detect(port);
+#if defined(CONFIG_POWER_PP5000_CONTROL) && defined(CONFIG_AP_POWER_CONTROL)
 		/* Issue a request to turn off the rail. */
 		power_5v_enable(task_get_current(), 0);
 #endif
 	}
 }
 
-static void max14637_usb_charger_task(const int port)
+static void max14637_usb_charger_task_init(const int port)
 {
-	uint32_t evt;
-	const struct max14637_config_t * const cfg = &max14637_config[port];
+	const struct max14637_config_t *const cfg = &max14637_config[port];
 
 	ASSERT(port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	/*
@@ -165,13 +188,12 @@ static void max14637_usb_charger_task(const int port)
 	activate_chip_enable(cfg, 1);
 	/* Check whether bc1.2 client mode detection needs to be triggered */
 	detect_or_power_down_ic(port);
+}
 
-	while (1) {
-		evt = task_wait_event(-1);
-
-		if (evt & USB_CHG_EVENT_VBUS)
-			detect_or_power_down_ic(port);
-	}
+static void max14637_usb_charger_task_event(const int port, uint32_t evt)
+{
+	if (evt & USB_CHG_EVENT_VBUS)
+		detect_or_power_down_ic(port);
 }
 
 #if defined(CONFIG_CHARGE_RAMP_SW) || defined(CONFIG_CHARGE_RAMP_HW)
@@ -207,14 +229,14 @@ static void bc12_chipset_startup(void)
 	 * not drop even during the USB PD hard reset.
 	 */
 	for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++)
-		task_set_event(USB_CHG_PORT_TO_TASK_ID(port),
-			       USB_CHG_EVENT_VBUS, 0);
+		usb_charger_task_set_event(port, USB_CHG_EVENT_VBUS);
 }
 DECLARE_HOOK(HOOK_CHIPSET_STARTUP, bc12_chipset_startup, HOOK_PRIO_DEFAULT);
 DECLARE_HOOK(HOOK_CHIPSET_RESUME, bc12_chipset_startup, HOOK_PRIO_DEFAULT);
 
 const struct bc12_drv max14637_drv = {
-	.usb_charger_task = max14637_usb_charger_task,
+	.usb_charger_task_init = max14637_usb_charger_task_init,
+	.usb_charger_task_event = max14637_usb_charger_task_event,
 #if defined(CONFIG_CHARGE_RAMP_SW) || defined(CONFIG_CHARGE_RAMP_HW)
 	.ramp_allowed = max14637_ramp_allowed,
 	.ramp_max = max14637_ramp_max,
diff --git a/driver/bc12/max14637.h b/driver/bc12/max14637.h
index 2b18bc222b..119437d9da 100644
--- a/driver/bc12/max14637.h
+++ b/driver/bc12/max14637.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,8 +7,8 @@
 
 #include "gpio.h"
 
-#define MAX14637_FLAGS_ENABLE_ACTIVE_LOW		BIT(0)
-#define MAX14637_FLAGS_CHG_DET_ACTIVE_LOW		BIT(1)
+#define MAX14637_FLAGS_ENABLE_ACTIVE_LOW BIT(0)
+#define MAX14637_FLAGS_CHG_DET_ACTIVE_LOW BIT(1)
 
 struct max14637_config_t {
 	/*
@@ -29,5 +29,5 @@ struct max14637_config_t {
  * Array that contains boards-specific configuration for BC 1.2 charging chips.
  */
 extern const struct max14637_config_t
-				max14637_config[CONFIG_USB_PD_PORT_MAX_COUNT];
+	max14637_config[CONFIG_USB_PD_PORT_MAX_COUNT];
 extern const struct bc12_drv max14637_drv;
diff --git a/driver/bc12/mt6360.c b/driver/bc12/mt6360.c
index c634be8e33..ca4bf11794 100644
--- a/driver/bc12/mt6360.c
+++ b/driver/bc12/mt6360.c
@@ -1,16 +1,17 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include "charger.h"
 #include "charge_manager.h"
+#include "charger.h"
 #include "console.h"
 #include "crc8.h"
-#include "driver/bc12/mt6360.h"
 #include "ec_commands.h"
+#include "gpio.h"
 #include "hooks.h"
 #include "i2c.h"
+#include "mt6360.h"
 #include "task.h"
 #include "timer.h"
 #include "usb_charge.h"
@@ -18,20 +19,20 @@
 #include "util.h"
 
 /* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
 #define CPRINTS(format, args...) \
-	cprints(CC_USBCHARGE, "%s " format, "MT6360", ## args)
+	cprints(CC_USBCHARGE, "%s " format, "MT6360", ##args)
 
 static enum ec_error_list mt6360_read8(int reg, int *val)
 {
 	return i2c_read8(mt6360_config.i2c_port, mt6360_config.i2c_addr_flags,
-			reg, val);
+			 reg, val);
 }
 
 static enum ec_error_list mt6360_write8(int reg, int val)
 {
 	return i2c_write8(mt6360_config.i2c_port, mt6360_config.i2c_addr_flags,
-			reg, val);
+			  reg, val);
 }
 
 static int mt6360_update_bits(int reg, int mask, int val)
@@ -118,7 +119,9 @@ static void mt6360_update_charge_manager(int port,
 	static enum charge_supplier current_bc12_type = CHARGE_SUPPLIER_NONE;
 
 	if (new_bc12_type != current_bc12_type) {
-		charge_manager_update_charge(current_bc12_type, port, NULL);
+		if (current_bc12_type >= 0)
+			charge_manager_update_charge(current_bc12_type, port,
+						     NULL);
 
 		if (new_bc12_type != CHARGE_SUPPLIER_NONE) {
 			struct charge_port_info chg = {
@@ -143,39 +146,45 @@ static void mt6360_handle_bc12_irq(int port)
 		/* Check vbus again to avoid timing issue */
 		if (pd_snk_is_vbus_provided(port))
 			mt6360_update_charge_manager(
-					port, mt6360_get_bc12_device_type());
+				port, mt6360_get_bc12_device_type());
 		else
-			mt6360_update_charge_manager(
-					0, CHARGE_SUPPLIER_NONE);
+			mt6360_update_charge_manager(0, CHARGE_SUPPLIER_NONE);
 	}
 
 	/* write clear */
 	mt6360_write8(MT6360_REG_DPDMIRQ, reg);
 }
 
-static void mt6360_usb_charger_task(const int port)
+static void mt6360_usb_charger_task_init(const int port)
 {
 	mt6360_clr_bit(MT6360_REG_DPDM_MASK1,
 		       MT6360_REG_DPDM_MASK1_CHGDET_DONEI_M);
 	mt6360_enable_bc12_detection(0);
+}
 
-	while (1) {
-		uint32_t evt = task_wait_event(-1);
+static void mt6360_usb_charger_task_event(const int port, uint32_t evt)
+{
+	/* vbus change, start bc12 detection */
+	if (evt & USB_CHG_EVENT_VBUS) {
+		bool is_sink = pd_get_power_role(port) == PD_ROLE_SINK;
+		bool is_non_pd_sink = !pd_capable(port) && is_sink &&
+				      pd_snk_is_vbus_provided(port);
+
+		if (is_sink)
+			mt6360_clr_bit(MT6360_REG_CHG_CTRL1, MT6360_MASK_HZ);
+		else
+			mt6360_set_bit(MT6360_REG_CHG_CTRL1, MT6360_MASK_HZ);
 
-		/* vbus change, start bc12 detection */
-		if (evt & USB_CHG_EVENT_VBUS) {
-			if (pd_snk_is_vbus_provided(port))
-				mt6360_enable_bc12_detection(1);
-			else
-				mt6360_update_charge_manager(
-						0, CHARGE_SUPPLIER_NONE);
-		}
+		if (is_non_pd_sink)
+			mt6360_enable_bc12_detection(1);
+		else
+			mt6360_update_charge_manager(0, CHARGE_SUPPLIER_NONE);
+	}
 
-		/* detection done, update charge_manager and stop detection */
-		if (evt & USB_CHG_EVENT_BC12) {
-			mt6360_handle_bc12_irq(port);
-			mt6360_enable_bc12_detection(0);
-		}
+	/* detection done, update charge_manager and stop detection */
+	if (evt & USB_CHG_EVENT_BC12) {
+		mt6360_handle_bc12_irq(port);
+		mt6360_enable_bc12_detection(0);
 	}
 }
 
@@ -186,15 +195,15 @@ static int mt6360_regulator_write8(uint8_t addr, int reg, int val)
 	 * Note: The checksum from I2C_FLAG_PEC happens to be correct because
 	 * length == 1 -> the high 3 bits of the offset byte is 0.
 	 */
-	return i2c_write8(mt6360_config.i2c_port,
-			  addr | I2C_FLAG_PEC, reg, val);
+	return i2c_write8(mt6360_config.i2c_port, addr | I2C_FLAG_PEC, reg,
+			  val);
 }
 
 static int mt6360_regulator_read8(int addr, int reg, int *val)
 {
 	int rv;
 	uint8_t crc = 0, real_crc;
-	uint8_t out[3] = {(addr << 1) | 1, reg};
+	uint8_t out[3] = { (addr << 1) | 1, reg };
 
 	rv = i2c_read16(mt6360_config.i2c_port, addr, reg, val);
 	if (rv)
@@ -203,7 +212,7 @@ static int mt6360_regulator_read8(int addr, int reg, int *val)
 	real_crc = (*val >> 8) & 0xFF;
 	*val &= 0xFF;
 	out[2] = *val;
-	crc = crc8(out, ARRAY_SIZE(out));
+	crc = cros_crc8(out, ARRAY_SIZE(out));
 
 	if (crc != real_crc)
 		return EC_ERROR_CRC;
@@ -251,22 +260,10 @@ static const uint16_t MT6360_LDO5_VOSEL_TABLE[8] = {
 };
 
 static const uint16_t MT6360_LDO6_VOSEL_TABLE[16] = {
-	[0x0] = 500,
-	[0x1] = 600,
-	[0x2] = 700,
-	[0x3] = 800,
-	[0x4] = 900,
-	[0x5] = 1000,
-	[0x6] = 1100,
-	[0x7] = 1200,
-	[0x8] = 1300,
-	[0x9] = 1400,
-	[0xA] = 1500,
-	[0xB] = 1600,
-	[0xC] = 1700,
-	[0xD] = 1800,
-	[0xE] = 1900,
-	[0xF] = 2000,
+	[0x0] = 500,  [0x1] = 600,  [0x2] = 700,  [0x3] = 800,
+	[0x4] = 900,  [0x5] = 1000, [0x6] = 1100, [0x7] = 1200,
+	[0x8] = 1300, [0x9] = 1400, [0xA] = 1500, [0xB] = 1600,
+	[0xC] = 1700, [0xD] = 1800, [0xE] = 1900, [0xF] = 2000,
 };
 
 /* LDO7 VOSEL table is the same as LDO6's. */
@@ -280,7 +277,7 @@ struct mt6360_regulator_data regulator_data[MT6360_REGULATOR_COUNT] = {
 		.name = "mt6360_ldo3",
 		.ldo_vosel_table = MT6360_LDO3_VOSEL_TABLE,
 		.ldo_vosel_table_len = ARRAY_SIZE(MT6360_LDO3_VOSEL_TABLE),
-		.addr = MT6360_LDO_SLAVE_ADDR_FLAGS,
+		.addr = MT6360_LDO_I2C_ADDR_FLAGS,
 		.reg_en_ctrl2 = MT6360_REG_LDO3_EN_CTRL2,
 		.reg_ctrl3 = MT6360_REG_LDO3_CTRL3,
 		.mask_vosel = MT6360_MASK_LDO3_VOSEL,
@@ -291,7 +288,7 @@ struct mt6360_regulator_data regulator_data[MT6360_REGULATOR_COUNT] = {
 		.name = "mt6360_ldo5",
 		.ldo_vosel_table = MT6360_LDO5_VOSEL_TABLE,
 		.ldo_vosel_table_len = ARRAY_SIZE(MT6360_LDO5_VOSEL_TABLE),
-		.addr = MT6360_LDO_SLAVE_ADDR_FLAGS,
+		.addr = MT6360_LDO_I2C_ADDR_FLAGS,
 		.reg_en_ctrl2 = MT6360_REG_LDO5_EN_CTRL2,
 		.reg_ctrl3 = MT6360_REG_LDO5_CTRL3,
 		.mask_vosel = MT6360_MASK_LDO5_VOSEL,
@@ -302,7 +299,7 @@ struct mt6360_regulator_data regulator_data[MT6360_REGULATOR_COUNT] = {
 		.name = "mt6360_ldo6",
 		.ldo_vosel_table = MT6360_LDO6_VOSEL_TABLE,
 		.ldo_vosel_table_len = ARRAY_SIZE(MT6360_LDO6_VOSEL_TABLE),
-		.addr = MT6360_PMIC_SLAVE_ADDR_FLAGS,
+		.addr = MT6360_PMIC_I2C_ADDR_FLAGS,
 		.reg_en_ctrl2 = MT6360_REG_LDO6_EN_CTRL2,
 		.reg_ctrl3 = MT6360_REG_LDO6_CTRL3,
 		.mask_vosel = MT6360_MASK_LDO6_VOSEL,
@@ -313,7 +310,7 @@ struct mt6360_regulator_data regulator_data[MT6360_REGULATOR_COUNT] = {
 		.name = "mt6360_ldo7",
 		.ldo_vosel_table = MT6360_LDO7_VOSEL_TABLE,
 		.ldo_vosel_table_len = MT6360_LDO7_VOSEL_TABLE_SIZE,
-		.addr = MT6360_PMIC_SLAVE_ADDR_FLAGS,
+		.addr = MT6360_PMIC_I2C_ADDR_FLAGS,
 		.reg_en_ctrl2 = MT6360_REG_LDO7_EN_CTRL2,
 		.reg_ctrl3 = MT6360_REG_LDO7_CTRL3,
 		.mask_vosel = MT6360_MASK_LDO7_VOSEL,
@@ -322,7 +319,7 @@ struct mt6360_regulator_data regulator_data[MT6360_REGULATOR_COUNT] = {
 	},
 	[MT6360_BUCK1] = {
 		.name = "mt6360_buck1",
-		.addr = MT6360_PMIC_SLAVE_ADDR_FLAGS,
+		.addr = MT6360_PMIC_I2C_ADDR_FLAGS,
 		.reg_en_ctrl2 = MT6360_REG_BUCK1_EN_CTRL2,
 		.reg_ctrl3 = MT6360_REG_BUCK1_VOSEL,
 		.mask_vosel = MT6360_MASK_BUCK1_VOSEL,
@@ -331,7 +328,7 @@ struct mt6360_regulator_data regulator_data[MT6360_REGULATOR_COUNT] = {
 	},
 	[MT6360_BUCK2] = {
 		.name = "mt6360_buck2",
-		.addr = MT6360_PMIC_SLAVE_ADDR_FLAGS,
+		.addr = MT6360_PMIC_I2C_ADDR_FLAGS,
 		.reg_en_ctrl2 = MT6360_REG_BUCK2_EN_CTRL2,
 		.reg_ctrl3 = MT6360_REG_BUCK2_VOSEL,
 		.mask_vosel = MT6360_MASK_BUCK2_VOSEL,
@@ -399,14 +396,12 @@ int mt6360_regulator_enable(enum mt6360_regulator_id id, uint8_t enable)
 
 	if (enable)
 		return mt6360_regulator_update_bits(
-			data->addr,
-			data->reg_en_ctrl2,
+			data->addr, data->reg_en_ctrl2,
 			MT6360_MASK_RGL_SW_OP_EN | MT6360_MASK_RGL_SW_EN,
 			MT6360_MASK_RGL_SW_OP_EN | MT6360_MASK_RGL_SW_EN);
 	else
 		return mt6360_regulator_update_bits(
-			data->addr,
-			data->reg_en_ctrl2,
+			data->addr, data->reg_en_ctrl2,
 			MT6360_MASK_RGL_SW_OP_EN | MT6360_MASK_RGL_SW_EN,
 			MT6360_MASK_RGL_SW_OP_EN);
 }
@@ -457,8 +452,7 @@ int mt6360_regulator_set_voltage(enum mt6360_regulator_id id, int min_mv,
 
 		step = (mv - MT6360_BUCK_VOSEL_MIN) / MT6360_BUCK_VOSEL_STEP_MV;
 
-		return mt6360_regulator_update_bits(data->addr,
-						    data->reg_ctrl3,
+		return mt6360_regulator_update_bits(data->addr, data->reg_ctrl3,
 						    data->mask_vosel, step);
 	}
 
@@ -478,8 +472,7 @@ int mt6360_regulator_set_voltage(enum mt6360_regulator_id id, int min_mv,
 		if (mv + step * MT6360_LDO_VOCAL_STEP_MV > max_mv)
 			continue;
 		return mt6360_regulator_update_bits(
-			data->addr,
-			data->reg_ctrl3,
+			data->addr, data->reg_ctrl3,
 			data->mask_vosel | data->mask_vocal,
 			(i << data->shift_vosel) | step);
 	}
@@ -535,7 +528,7 @@ DECLARE_HOOK(HOOK_INIT, mt6360_led_init, HOOK_PRIO_DEFAULT);
 
 int mt6360_led_enable(enum mt6360_led_id led_id, int enable)
 {
-	if (!IN_RANGE(led_id, 0, MT6360_LED_COUNT))
+	if (!IN_RANGE(led_id, 0, MT6360_LED_COUNT - 1))
 		return EC_ERROR_INVAL;
 
 	if (enable)
@@ -548,9 +541,9 @@ int mt6360_led_set_brightness(enum mt6360_led_id led_id, int brightness)
 {
 	int val;
 
-	if (!IN_RANGE(led_id, 0, MT6360_LED_COUNT))
+	if (!IN_RANGE(led_id, 0, MT6360_LED_COUNT - 1))
 		return EC_ERROR_INVAL;
-	if (!IN_RANGE(brightness, 0, 16))
+	if (!IN_RANGE(brightness, 0, 15))
 		return EC_ERROR_INVAL;
 
 	RETURN_ERROR(mt6360_read8(MT6360_REG_RGB_ISINK(led_id), &val));
@@ -561,7 +554,8 @@ int mt6360_led_set_brightness(enum mt6360_led_id led_id, int brightness)
 }
 
 const struct bc12_drv mt6360_drv = {
-	.usb_charger_task = mt6360_usb_charger_task,
+	.usb_charger_task_init = mt6360_usb_charger_task_init,
+	.usb_charger_task_event = mt6360_usb_charger_task_event,
 };
 
 #ifdef CONFIG_BC12_SINGLE_DRIVER
diff --git a/driver/bc12/mt6360.h b/driver/bc12/mt6360.h
index e5fb47384c..85dab2b6ad 100644
--- a/driver/bc12/mt6360.h
+++ b/driver/bc12/mt6360.h
@@ -1,17 +1,17 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #ifndef __CROS_EC_MT6360_H
 
-#define MT6360_PMU_SLAVE_ADDR_FLAGS 0x34
-#define MT6360_PMIC_SLAVE_ADDR_FLAGS 0x1A
-#define MT6360_LDO_SLAVE_ADDR_FLAGS 0x64
-#define MT6360_PD_SLAVE_ADDR_FLAGS 0x4E
+#include "bc12/mt6360_public.h"
 
 #define MT6360_IRQ_MASK 0x0C
 
+#define MT6360_REG_CHG_CTRL1 0x11
+#define MT6360_MASK_HZ BIT(2)
+
 #define MT6360_REG_DEVICE_TYPE 0x22
 #define MT6360_MASK_USBCHGEN BIT(7)
 
@@ -91,51 +91,4 @@
 	(MT6360_BUCK_VOSEL_MIN + \
 	 MT6360_BUCK_VOSEL_STEP_MV * MT6360_BUCK_VOSEL_MAX_STEP)
 
-enum mt6360_regulator_id {
-	MT6360_LDO3,
-	MT6360_LDO5,
-	MT6360_LDO6,
-	MT6360_LDO7,
-	MT6360_BUCK1,
-	MT6360_BUCK2,
-
-	MT6360_REGULATOR_COUNT,
-};
-
-int mt6360_regulator_get_info(enum mt6360_regulator_id id, char *name,
-			      uint16_t *voltage_count, uint16_t *voltages_mv);
-
-int mt6360_regulator_enable(enum mt6360_regulator_id id, uint8_t enable);
-
-int mt6360_regulator_is_enabled(enum mt6360_regulator_id id, uint8_t *enabled);
-
-int mt6360_regulator_set_voltage(enum mt6360_regulator_id id, int min_mv,
-				 int max_mv);
-
-int mt6360_regulator_get_voltage(enum mt6360_regulator_id id, int *voltage_mv);
-
-enum mt6360_led_id {
-	MT6360_LED_RGB1,
-	MT6360_LED_RGB2,
-	MT6360_LED_RGB3,
-	MT6360_LED_RGB_ML,
-
-	MT6360_LED_COUNT,
-};
-
-#define MT6360_LED_BRIGHTNESS_MAX 15
-
-struct mt6360_config_t {
-	int i2c_port;
-	int i2c_addr_flags;
-};
-
-int mt6360_led_enable(enum mt6360_led_id led_id, int enable);
-
-int mt6360_led_set_brightness(enum mt6360_led_id led_id, int brightness);
-
-extern const struct mt6360_config_t mt6360_config;
-
-extern const struct bc12_drv mt6360_drv;
-
 #endif /* __CROS_EC_MT6360_H */
diff --git a/driver/bc12/pi3usb9201.c b/driver/bc12/pi3usb9201.c
index d53668933f..4e39933657 100644
--- a/driver/bc12/pi3usb9201.c
+++ b/driver/bc12/pi3usb9201.c
@@ -1,25 +1,24 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* PI3USB9201 USB BC 1.2 Charger Detector driver. */
 
-#include "pi3usb9201.h"
 #include "charge_manager.h"
 #include "chipset.h"
 #include "common.h"
 #include "console.h"
 #include "gpio.h"
+#include "pi3usb9201.h"
 #include "power.h"
 #include "task.h"
-#include "tcpm.h"
 #include "timer.h"
 #include "usb_charge.h"
 #include "usb_pd.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
 
 enum pi3usb9201_client_sts {
 	CHG_OTHER = 0,
@@ -46,32 +45,21 @@ static enum charge_supplier bc12_supplier[CONFIG_USB_PD_PORT_MAX_COUNT];
  * will continue to allow those.
  */
 static const struct bc12_status bc12_chg_limits[] = {
-	[CHG_OTHER] = {CHARGE_SUPPLIER_OTHER, 500},
-	[CHG_2_4A] = {CHARGE_SUPPLIER_PROPRIETARY, USB_CHARGER_MAX_CURR_MA},
-	[CHG_2_0A] = {CHARGE_SUPPLIER_PROPRIETARY, USB_CHARGER_MAX_CURR_MA},
-	[CHG_1_0A] = {CHARGE_SUPPLIER_PROPRIETARY, 1000},
-	[CHG_RESERVED] = {CHARGE_SUPPLIER_NONE, 0},
-	[CHG_CDP] = {CHARGE_SUPPLIER_BC12_CDP, USB_CHARGER_MAX_CURR_MA},
-	[CHG_SDP] = {CHARGE_SUPPLIER_BC12_SDP, 500},
-#if defined(CONFIG_CHARGE_RAMP_SW) || defined(CONFIG_CHARGE_RAMP_HW)
-	/*
-	 * If ramping is supported, then for DCP set the current limit to be the
-	 * max supported for the port by the board or 1.5A (whichever is lower).
-	 * Although, the BC 1.2 specification allows DCP suppliers to ramp to
-	 * much higher currents, the USB Type-C specification limits the
-	 * maximum current allowed for BC 1.2 suppliers to 1.5A.
-	 */
-	[CHG_DCP] = {CHARGE_SUPPLIER_BC12_DCP, USB_CHARGER_MAX_CURR_MA},
-#else
-	[CHG_DCP] = {CHARGE_SUPPLIER_BC12_DCP, 500},
-#endif
+	[CHG_OTHER] = { CHARGE_SUPPLIER_OTHER, 500 },
+	[CHG_2_4A] = { CHARGE_SUPPLIER_PROPRIETARY, USB_CHARGER_MAX_CURR_MA },
+	[CHG_2_0A] = { CHARGE_SUPPLIER_PROPRIETARY, USB_CHARGER_MAX_CURR_MA },
+	[CHG_1_0A] = { CHARGE_SUPPLIER_PROPRIETARY, 1000 },
+	[CHG_RESERVED] = { CHARGE_SUPPLIER_NONE, 0 },
+	[CHG_CDP] = { CHARGE_SUPPLIER_BC12_CDP, USB_CHARGER_MAX_CURR_MA },
+	[CHG_SDP] = { CHARGE_SUPPLIER_BC12_SDP, 500 },
+	[CHG_DCP] = { CHARGE_SUPPLIER_BC12_DCP, USB_CHARGER_MAX_CURR_MA },
 };
 
 static inline int raw_read8(int port, int offset, int *value)
 {
 	return i2c_read8(pi3usb9201_bc12_chips[port].i2c_port,
-			 pi3usb9201_bc12_chips[port].i2c_addr_flags,
-			 offset, value);
+			 pi3usb9201_bc12_chips[port].i2c_addr_flags, offset,
+			 value);
 }
 
 static int pi3usb9201_raw(int port, int reg, int mask, int val)
@@ -85,8 +73,7 @@ static int pi3usb9201_raw(int port, int reg, int mask, int val)
 static int pi3usb9201_interrupt_mask(int port, int enable)
 {
 	return pi3usb9201_raw(port, PI3USB9201_REG_CTRL_1,
-			  PI3USB9201_REG_CTRL_1_INT_MASK,
-			  enable);
+			      PI3USB9201_REG_CTRL_1_INT_MASK, enable);
 }
 
 static int pi3usb9201_bc12_detect_ctrl(int port, int enable)
@@ -103,7 +90,7 @@ static int pi3usb9201_set_mode(int port, int desired_mode)
 			      desired_mode << PI3USB9201_REG_CTRL_1_MODE_SHIFT);
 }
 
-static int pi3usb9201_get_mode(int port, int *mode)
+static __maybe_unused int pi3usb9201_get_mode(int port, int *mode)
 {
 	int rv;
 
@@ -133,7 +120,7 @@ static int pi3usb9201_get_status(int port, int *client, int *host)
 }
 
 static void bc12_update_supplier(enum charge_supplier supplier, int port,
-			  struct charge_port_info *new_chg)
+				 struct charge_port_info *new_chg)
 {
 	/*
 	 * If most recent supplier type is not CHARGE_SUPPLIER_NONE, then the
@@ -167,8 +154,8 @@ static void bc12_update_charge_manager(int port, int client_status)
 	new_chg.current = bc12_chg_limits[bit_pos].current_limit;
 	supplier = bc12_chg_limits[bit_pos].supplier;
 
-	CPRINTS("pi3usb9201[p%d]: sts = 0x%x, lim = %d mA, supplier = %d",
-		port, client_status, new_chg.current, supplier);
+	CPRINTS("pi3usb9201[p%d]: sts = 0x%x, lim = %d mA, supplier = %d", port,
+		client_status, new_chg.current, supplier);
 	/* bc1.2 is complete and start bit does not auto clear */
 	pi3usb9201_bc12_detect_ctrl(port, 0);
 	/* Inform charge manager of new supplier type and current limit */
@@ -215,7 +202,7 @@ static void bc12_power_down(int port)
 	if (pi3usb9201_bc12_chips[port].flags & PI3USB9201_ALWAYS_POWERED)
 		return;
 
-#if defined(CONFIG_POWER_PP5000_CONTROL) && defined(HAS_TASK_CHIPSET)
+#if defined(CONFIG_POWER_PP5000_CONTROL) && defined(CONFIG_AP_POWER_CONTROL)
 	/* Indicate PP5000_A rail is not required by USB_CHG task. */
 	power_5v_enable(task_get_current(), 0);
 #endif
@@ -224,7 +211,7 @@ static void bc12_power_down(int port)
 static void bc12_power_up(int port)
 {
 	if (IS_ENABLED(CONFIG_POWER_PP5000_CONTROL) &&
-	    IS_ENABLED(HAS_TASK_CHIPSET) &&
+	    IS_ENABLED(CONFIG_AP_POWER_CONTROL) &&
 	    !(pi3usb9201_bc12_chips[port].flags & PI3USB9201_ALWAYS_POWERED)) {
 		/* Turn on the 5V rail to allow the chip to be powered. */
 		power_5v_enable(task_get_current(), 1);
@@ -238,129 +225,126 @@ static void bc12_power_up(int port)
 	pi3usb9201_interrupt_mask(port, 1);
 }
 
-static void pi3usb9201_usb_charger_task(const int port)
+static void pi3usb9201_usb_charger_task_init(const int port)
 {
-	uint32_t evt;
-	int i;
-
 	/*
 	 * Set most recent bc1.2 detection supplier result to
-	 * CHARGE_SUPPLIER_NONE for all ports.
+	 * CHARGE_SUPPLIER_NONE for the port.
 	 */
-	for (i = 0; i < board_get_usb_pd_port_count(); i++)
-		bc12_supplier[port] = CHARGE_SUPPLIER_NONE;
+	bc12_supplier[port] = CHARGE_SUPPLIER_NONE;
 
 	/*
 	 * The is no specific initialization required for the pi3usb9201 other
 	 * than enabling the interrupt mask.
 	 */
 	pi3usb9201_interrupt_mask(port, 1);
+}
 
-	while (1) {
-		/* Wait for interrupt */
-		evt = task_wait_event(-1);
-
-		/* Interrupt from the Pericom chip, determine charger type */
-		if (evt & USB_CHG_EVENT_BC12) {
-			int client;
-			int host;
-			int rv;
-
-			rv = pi3usb9201_get_status(port, &client, &host);
-			if (!rv && client)
-				/*
-				 * Any bit set in client status register
-				 * indicates that BC1.2 detection has
-				 * completed.
-				 */
-				bc12_update_charge_manager(port, client);
-			if (!rv && host) {
-				/*
-				 * Switch to SDP after device is plugged in to
-				 * avoid noise (pulse on D-) causing USB
-				 * disconnect (b/156014140).
-				 */
-				if (host & PI3USB9201_REG_HOST_STS_DEV_PLUG)
-					pi3usb9201_set_mode(port,
-						PI3USB9201_SDP_HOST_MODE);
-				/*
-				 * Switch to CDP after device is unplugged so
-				 * we advertise higher power available for next
-				 * device.
-				 */
-				if (host & PI3USB9201_REG_HOST_STS_DEV_UNPLUG)
-					pi3usb9201_set_mode(port,
-						PI3USB9201_CDP_HOST_MODE);
-			}
+static void pi3usb9201_usb_charger_task_event(const int port, uint32_t evt)
+{
+	/* Interrupt from the Pericom chip, determine charger type */
+	if (evt & USB_CHG_EVENT_BC12) {
+		int client;
+		int host;
+		int rv;
+
+		rv = pi3usb9201_get_status(port, &client, &host);
+		if (!rv && client)
 			/*
-			 * TODO(b/124061702): Use host status to allocate power
-			 * more intelligently.
+			 * Any bit set in client status register indicates that
+			 * BC1.2 detection has completed.
 			 */
+			bc12_update_charge_manager(port, client);
+		if (!rv && host) {
+#ifdef CONFIG_BC12_CLIENT_MODE_ONLY_PI3USB9201
+			pi3usb9201_set_mode(port, PI3USB9201_USB_PATH_ON);
+#else
+			/*
+			 * Switch to SDP after device is plugged in to avoid
+			 * noise (pulse on D-) causing USB disconnect
+			 * (b/156014140).
+			 */
+			if (host & PI3USB9201_REG_HOST_STS_DEV_PLUG)
+				pi3usb9201_set_mode(port,
+						    PI3USB9201_SDP_HOST_MODE);
+			/*
+			 * Switch to CDP after device is unplugged so we
+			 * advertise higher power available for next device.
+			 */
+			if (host & PI3USB9201_REG_HOST_STS_DEV_UNPLUG)
+				pi3usb9201_set_mode(port,
+						    PI3USB9201_CDP_HOST_MODE);
+#endif
 		}
+		/*
+		 * TODO(b/124061702): Use host status to allocate power more
+		 * intelligently.
+		 */
+	}
 
-#ifndef CONFIG_USB_PD_VBUS_DETECT_TCPC
-		if (evt & USB_CHG_EVENT_VBUS)
-			CPRINTS("VBUS p%d %d", port,
-				pd_snk_is_vbus_provided(port));
-#endif
+	if (!IS_ENABLED(CONFIG_USB_PD_VBUS_DETECT_TCPC) &&
+	    (evt & USB_CHG_EVENT_VBUS))
+		CPRINTS("VBUS p%d %d", port, pd_snk_is_vbus_provided(port));
+
+	if (evt & USB_CHG_EVENT_DR_UFP) {
+		bc12_power_up(port);
+		if (bc12_detect_start(port)) {
+			struct charge_port_info new_chg;
+
+			/*
+			 * VBUS is present, but starting bc1.2 detection failed
+			 * for some reason. So limit charge current to default
+			 * 500 mA for this case.
+			 */
 
-		if (evt & USB_CHG_EVENT_DR_UFP) {
-			bc12_power_up(port);
-			if (bc12_detect_start(port)) {
-				struct charge_port_info new_chg;
-
-				/*
-				 * VBUS is present, but starting bc1.2 detection
-				 * failed for some reason. So limit charge
-				 * current to default 500 mA for this case.
-				 */
-
-				new_chg.voltage = USB_CHARGER_VOLTAGE_MV;
-				new_chg.current = USB_CHARGER_MIN_CURR_MA;
-				/* Save supplier type and notify chg manager */
-				bc12_update_supplier(CHARGE_SUPPLIER_OTHER,
-						     port, &new_chg);
-				CPRINTS("pi3usb9201[p%d]: bc1.2 failed use "
-					"defaults", port);
-			}
+			new_chg.voltage = USB_CHARGER_VOLTAGE_MV;
+			new_chg.current = USB_CHARGER_MIN_CURR_MA;
+			/* Save supplier type and notify chg manager */
+			bc12_update_supplier(CHARGE_SUPPLIER_OTHER, port,
+					     &new_chg);
+			CPRINTS("pi3usb9201[p%d]: bc1.2 failed use defaults",
+				port);
 		}
+	}
 
-		if (evt & USB_CHG_EVENT_DR_DFP) {
-			int mode;
-			int rv;
+	if (evt & USB_CHG_EVENT_DR_DFP) {
+#ifdef CONFIG_BC12_CLIENT_MODE_ONLY_PI3USB9201
+		pi3usb9201_set_mode(port, PI3USB9201_USB_PATH_ON);
+#else
+		int mode;
+		int rv;
 
+		/*
+		 * Update the charge manager if bc1.2 client mode is currently
+		 * active.
+		 */
+		bc12_update_supplier(CHARGE_SUPPLIER_NONE, port, NULL);
+		/*
+		 * If the port is in DFP mode, then need to set mode to
+		 * CDP_HOST which will auto close D+/D- switches.
+		 */
+		bc12_power_up(port);
+		rv = pi3usb9201_get_mode(port, &mode);
+		if (!rv && (mode != PI3USB9201_CDP_HOST_MODE)) {
+			CPRINTS("pi3usb9201[p%d]: CDP_HOST mode", port);
 			/*
-			 * Update the charge manager if bc1.2 client mode is
-			 * currently active.
+			 * Read both status registers to ensure that all
+			 * interrupt indications are cleared prior to starting
+			 * DFP CDP host mode.
 			 */
-			bc12_update_supplier(CHARGE_SUPPLIER_NONE, port, NULL);
+			pi3usb9201_get_status(port, NULL, NULL);
+			pi3usb9201_set_mode(port, PI3USB9201_CDP_HOST_MODE);
 			/*
-			 * If the port is in DFP mode, then need to set mode to
-			 * CDP_HOST which will auto close D+/D- switches.
+			 * Unmask interrupt to wake task when host status
+			 * changes.
 			 */
-			bc12_power_up(port);
-			rv = pi3usb9201_get_mode(port, &mode);
-			if (!rv && (mode != PI3USB9201_CDP_HOST_MODE)) {
-				CPRINTS("pi3usb9201[p%d]: CDP_HOST mode", port);
-				/*
-				 * Read both status registers to ensure that all
-				 * interrupt indications are cleared prior to
-				 * starting DFP CDP host mode.
-				 */
-				pi3usb9201_get_status(port, NULL, NULL);
-				pi3usb9201_set_mode(port,
-						    PI3USB9201_CDP_HOST_MODE);
-				/*
-				 * Unmask interrupt to wake task when host
-				 * status changes.
-				 */
-				pi3usb9201_interrupt_mask(port, 0);
-			}
+			pi3usb9201_interrupt_mask(port, 0);
 		}
-
-		if (evt & USB_CHG_EVENT_CC_OPEN)
-			bc12_power_down(port);
+#endif
 	}
+
+	if (evt & USB_CHG_EVENT_CC_OPEN)
+		bc12_power_down(port);
 }
 
 #if defined(CONFIG_CHARGE_RAMP_SW) || defined(CONFIG_CHARGE_RAMP_HW)
@@ -369,6 +353,7 @@ static int pi3usb9201_ramp_allowed(int supplier)
 	/* Don't allow ramp if charge supplier is OTHER, SDP, or NONE */
 	return !(supplier == CHARGE_SUPPLIER_OTHER ||
 		 supplier == CHARGE_SUPPLIER_BC12_SDP ||
+		 supplier == CHARGE_SUPPLIER_BC12_DCP ||
 		 supplier == CHARGE_SUPPLIER_NONE);
 }
 
@@ -394,7 +379,8 @@ static int pi3usb9201_ramp_max(int supplier, int sup_curr)
 #endif /* CONFIG_CHARGE_RAMP_SW || CONFIG_CHARGE_RAMP_HW */
 
 const struct bc12_drv pi3usb9201_drv = {
-	.usb_charger_task = pi3usb9201_usb_charger_task,
+	.usb_charger_task_init = pi3usb9201_usb_charger_task_init,
+	.usb_charger_task_event = pi3usb9201_usb_charger_task_event,
 #if defined(CONFIG_CHARGE_RAMP_SW) || defined(CONFIG_CHARGE_RAMP_HW)
 	.ramp_allowed = pi3usb9201_ramp_allowed,
 	.ramp_max = pi3usb9201_ramp_max,
@@ -403,9 +389,8 @@ const struct bc12_drv pi3usb9201_drv = {
 
 #ifdef CONFIG_BC12_SINGLE_DRIVER
 /* provide a default bc12_ports[] for backward compatibility */
-struct bc12_config bc12_ports[CHARGE_PORT_COUNT] = {
-	[0 ... (CHARGE_PORT_COUNT - 1)] = {
-		.drv = &pi3usb9201_drv,
-	}
-};
+struct bc12_config
+	bc12_ports[CHARGE_PORT_COUNT] = { [0 ...(CHARGE_PORT_COUNT - 1)] = {
+						  .drv = &pi3usb9201_drv,
+					  } };
 #endif /* CONFIG_BC12_SINGLE_DRIVER */
diff --git a/driver/bc12/pi3usb9201.h b/driver/bc12/pi3usb9201.h
index 6326ee1d49..61728cce2a 100644
--- a/driver/bc12/pi3usb9201.h
+++ b/driver/bc12/pi3usb9201.h
@@ -1,15 +1,14 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* PI3USB9201 USB BC 1.2 Charger Detector driver definitions */
 
-/* I2C address */
-#define PI3USB9201_I2C_ADDR_0_FLAGS 0x5C
-#define PI3USB9201_I2C_ADDR_1_FLAGS 0x5D
-#define PI3USB9201_I2C_ADDR_2_FLAGS 0x5E
-#define PI3USB9201_I2C_ADDR_3_FLAGS 0x5F
+#ifndef __CROS_EC_DRIVER_BC12_PI3USB9201_H
+#define __CROS_EC_DRIVER_BC12_PI3USB9201_H
+
+#include "driver/bc12/pi3usb9201_public.h"
 
 #define PI3USB9201_REG_CTRL_1 0x0
 #define PI3USB9201_REG_CTRL_2 0x1
@@ -22,8 +21,8 @@
 /* Control_1 regiter bit definitions */
 #define PI3USB9201_REG_CTRL_1_INT_MASK BIT(0)
 #define PI3USB9201_REG_CTRL_1_MODE_SHIFT 1
-#define PI3USB9201_REG_CTRL_1_MODE_MASK (0x7 << \
-					 PI3USB9201_REG_CTRL_1_MODE_SHIFT)
+#define PI3USB9201_REG_CTRL_1_MODE_MASK \
+	(0x7 << PI3USB9201_REG_CTRL_1_MODE_SHIFT)
 
 /* Control_2 regiter bit definitions */
 #define PI3USB9201_REG_CTRL_2_AUTO_SW BIT(1)
@@ -34,12 +33,6 @@
 #define PI3USB9201_REG_HOST_STS_DEV_PLUG BIT(1)
 #define PI3USB9201_REG_HOST_STS_DEV_UNPLUG BIT(2)
 
-struct pi3usb9201_config_t {
-	const int i2c_port;
-	const int i2c_addr_flags;
-	const int flags;
-};
-
 enum pi3usb9201_mode {
 	PI3USB9201_POWER_DOWN,
 	PI3USB9201_SDP_HOST_MODE,
@@ -51,7 +44,4 @@ enum pi3usb9201_mode {
 	PI3USB9201_USB_PATH_ON,
 };
 
-/* Configuration struct defined at board level */
-extern const struct pi3usb9201_config_t pi3usb9201_bc12_chips[];
-
-extern const struct bc12_drv pi3usb9201_drv;
+#endif /* __CROS_EC_DRIVER_BC12_PI3USB9201_H */
diff --git a/driver/bc12/pi3usb9281.c b/driver/bc12/pi3usb9281.c
index 56ad5bf602..9e92d0f273 100644
--- a/driver/bc12/pi3usb9281.c
+++ b/driver/bc12/pi3usb9281.c
@@ -1,10 +1,11 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Pericom PI3USB3281 USB port switch driver.
  */
 
+#include "builtin/assert.h"
 #include "charge_manager.h"
 #include "common.h"
 #include "console.h"
@@ -19,9 +20,9 @@
 #include "usb_pd.h"
 #include "util.h"
 
- /* Console output macros */
+/* Console output macros */
 #define CPUTS(outstr) cputs(CC_USBCHARGE, outstr)
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
 
 /* I2C address */
 #define PI3USB9281_I2C_ADDR_FLAGS 0x25
@@ -30,10 +31,10 @@
 #define PI3USB9281_SW_RESET_DELAY 20
 
 /* Wait after a charger is detected to debounce pin contact order */
-#define PI3USB9281_DETECT_DEBOUNCE_MS			1000
-#define PI3USB9281_RESET_DEBOUNCE_MS			100
-#define PI3USB9281_RESET_STARTUP_DELAY			(200 * MSEC)
-#define PI3USB9281_RESET_STARTUP_DELAY_INTERVAL_MS	40
+#define PI3USB9281_DETECT_DEBOUNCE_MS 1000
+#define PI3USB9281_RESET_DEBOUNCE_MS 100
+#define PI3USB9281_RESET_STARTUP_DELAY (200 * MSEC)
+#define PI3USB9281_RESET_STARTUP_DELAY_INTERVAL_MS 40
 
 /* Store the state of our USB data switches so that they can be restored. */
 static int usb_switch_state[CONFIG_USB_PD_PORT_MAX_COUNT];
@@ -69,8 +70,7 @@ static uint8_t pi3usb9281_do_read(int port, uint8_t reg, int with_lock)
 	if (with_lock)
 		select_chip(port);
 
-	res = i2c_read8(chip->i2c_port, PI3USB9281_I2C_ADDR_FLAGS,
-			reg, &val);
+	res = i2c_read8(chip->i2c_port, PI3USB9281_I2C_ADDR_FLAGS, reg, &val);
 
 	if (with_lock)
 		unselect_chip(port);
@@ -91,8 +91,8 @@ static uint8_t pi3usb9281_read(int port, uint8_t reg)
 	return pi3usb9281_do_read(port, reg, 1);
 }
 
-static int pi3usb9281_do_write(
-	int port, uint8_t reg, uint8_t val, int with_lock)
+static int pi3usb9281_do_write(int port, uint8_t reg, uint8_t val,
+			       int with_lock)
 {
 	struct pi3usb9281_config *chip = &pi3usb9281_chips[port];
 	int res;
@@ -100,8 +100,7 @@ static int pi3usb9281_do_write(
 	if (with_lock)
 		select_chip(port);
 
-	res = i2c_write8(chip->i2c_port, PI3USB9281_I2C_ADDR_FLAGS,
-			 reg, val);
+	res = i2c_write8(chip->i2c_port, PI3USB9281_I2C_ADDR_FLAGS, reg, val);
 
 	if (with_lock)
 		unselect_chip(port);
@@ -120,8 +119,9 @@ static int pi3usb9281_write(int port, uint8_t reg, uint8_t val)
 static int pi3usb9281_do_write_ctrl(int port, uint8_t ctrl, int with_lock)
 {
 	return pi3usb9281_do_write(port, PI3USB9281_REG_CONTROL,
-				(ctrl & PI3USB9281_CTRL_MASK) |
-				PI3USB9281_CTRL_RSVD_1, with_lock);
+				   (ctrl & PI3USB9281_CTRL_MASK) |
+					   PI3USB9281_CTRL_RSVD_1,
+				   with_lock);
 }
 
 static int pi3usb9281_write_ctrl(int port, uint8_t ctrl)
@@ -156,7 +156,6 @@ static void pi3usb9281_init(int port)
 	pi3usb9281_enable_interrupts(port);
 }
 
-
 int pi3usb9281_enable_interrupts(int port)
 {
 	uint8_t ctrl;
@@ -287,7 +286,7 @@ static void pi3usb9281_set_switches(int port, enum usb_switch setting)
 	if (setting != USB_SWITCH_RESTORE)
 		usb_switch_state[port] = setting;
 	CPRINTS("USB MUX %d", usb_switch_state[port]);
-	task_set_event(TASK_ID_USB_CHG_P0 + port, USB_CHG_EVENT_MUX, 0);
+	usb_charger_task_set_event(port, USB_CHG_EVENT_MUX);
 }
 
 static int pc3usb9281_read_interrupt(int port)
@@ -297,7 +296,7 @@ static int pc3usb9281_read_interrupt(int port)
 	do {
 		/* Read (& clear) possible attach & detach interrupt */
 		if (pi3usb9281_get_interrupts(port) &
-				PI3USB9281_INT_ATTACH_DETACH)
+		    PI3USB9281_INT_ATTACH_DETACH)
 			return EC_SUCCESS;
 		msleep(PI3USB9281_RESET_STARTUP_DELAY_INTERVAL_MS);
 	} while (get_time().val < timeout.val);
@@ -416,51 +415,49 @@ static uint32_t bc12_detect(int port)
 	return evt;
 }
 
-static void pi3usb9281_usb_charger_task(const int port)
+static void pi3usb9281_usb_charger_task_event(const int port, uint32_t evt)
 {
-	uint32_t evt;
-
-	/* Initialize chip and enable interrupts */
-	pi3usb9281_init(port);
-
-	evt = bc12_detect(port);
-
-	while (1) {
-		/* Interrupt from the Pericom chip, determine charger type */
-		if (evt & USB_CHG_EVENT_BC12) {
-			/* Read interrupt register to clear on chip */
-			pi3usb9281_get_interrupts(port);
+	/* Interrupt from the Pericom chip, determine charger type */
+	if (evt & USB_CHG_EVENT_BC12) {
+		/* Read interrupt register to clear on chip */
+		pi3usb9281_get_interrupts(port);
+		evt = bc12_detect(port);
+	} else if (evt & USB_CHG_EVENT_INTR) {
+		/* USB_CHG_EVENT_INTR & _BC12 are mutually exclusive */
+		/* Check the interrupt register, and clear on chip */
+		if (pi3usb9281_get_interrupts(port) &
+		    PI3USB9281_INT_ATTACH_DETACH)
 			evt = bc12_detect(port);
-		} else if (evt & USB_CHG_EVENT_INTR) {
-			/* USB_CHG_EVENT_INTR & _BC12 are mutually exclusive */
-			/* Check the interrupt register, and clear on chip */
-			if (pi3usb9281_get_interrupts(port) &
-					PI3USB9281_INT_ATTACH_DETACH)
-				evt = bc12_detect(port);
-		}
+	}
 
-		if (evt & USB_CHG_EVENT_MUX)
-			pi3usb9281_set_switches_impl(
-					port, usb_switch_state[port]);
+	if (evt & USB_CHG_EVENT_MUX)
+		pi3usb9281_set_switches_impl(port, usb_switch_state[port]);
 
-		/*
-		 * Re-enable interrupts on pericom charger detector since the
-		 * chip may periodically reset itself, and come back up with
-		 * registers in default state. TODO(crosbug.com/p/33823): Fix
-		 * these unwanted resets.
-		 */
-		if (evt & USB_CHG_EVENT_VBUS) {
-			pi3usb9281_enable_interrupts(port);
-#ifndef CONFIG_USB_PD_VBUS_DETECT_TCPC
+	/*
+	 * Re-enable interrupts on pericom charger detector since the chip may
+	 * periodically reset itself, and come back up with registers in
+	 * default state. TODO(crosbug.com/p/33823): Fix these unwanted resets.
+	 */
+	if (evt & USB_CHG_EVENT_VBUS) {
+		pi3usb9281_enable_interrupts(port);
+		if (!IS_ENABLED(CONFIG_USB_PD_VBUS_DETECT_TCPC))
 			CPRINTS("VBUS p%d %d", port,
 				pd_snk_is_vbus_provided(port));
-#endif
-		}
-
-		evt = task_wait_event(-1);
 	}
 }
 
+static void pi3usb9281_usb_charger_task_init(const int port)
+{
+	uint32_t evt;
+
+	/* Initialize chip and enable interrupts */
+	pi3usb9281_init(port);
+
+	/* Set the initial state */
+	evt = bc12_detect(port);
+	pi3usb9281_usb_charger_task_event(port, evt);
+}
+
 #if defined(CONFIG_CHARGE_RAMP_SW) || defined(CONFIG_CHARGE_RAMP_HW)
 static int pi3usb9281_ramp_allowed(int supplier)
 {
@@ -487,7 +484,8 @@ static int pi3usb9281_ramp_max(int supplier, int sup_curr)
 #endif /* CONFIG_CHARGE_RAMP_SW || CONFIG_CHARGE_RAMP_HW */
 
 const struct bc12_drv pi3usb9281_drv = {
-	.usb_charger_task = pi3usb9281_usb_charger_task,
+	.usb_charger_task_init = pi3usb9281_usb_charger_task_init,
+	.usb_charger_task_event = pi3usb9281_usb_charger_task_event,
 	.set_switches = pi3usb9281_set_switches,
 #if defined(CONFIG_CHARGE_RAMP_SW) || defined(CONFIG_CHARGE_RAMP_HW)
 	.ramp_allowed = pi3usb9281_ramp_allowed,
diff --git a/driver/bc12/pi3usb9281.h b/driver/bc12/pi3usb9281.h
index ca1828f49c..7910502df8 100644
--- a/driver/bc12/pi3usb9281.h
+++ b/driver/bc12/pi3usb9281.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,55 +8,55 @@
 #ifndef __CROS_EC_PI3USB9281_H
 #define __CROS_EC_PI3USB9281_H
 
-#define PI3USB9281_REG_DEV_ID       0x01
-#define PI3USB9281_REG_CONTROL      0x02
-#define PI3USB9281_REG_INT          0x03
-#define PI3USB9281_REG_INT_MASK     0x05
-#define PI3USB9281_REG_DEV_TYPE     0x0a
-#define PI3USB9281_REG_CHG_STATUS   0x0e
-#define PI3USB9281_REG_MANUAL       0x13
-#define PI3USB9281_REG_RESET        0x1b
-#define PI3USB9281_REG_VBUS         0x1d
+#define PI3USB9281_REG_DEV_ID 0x01
+#define PI3USB9281_REG_CONTROL 0x02
+#define PI3USB9281_REG_INT 0x03
+#define PI3USB9281_REG_INT_MASK 0x05
+#define PI3USB9281_REG_DEV_TYPE 0x0a
+#define PI3USB9281_REG_CHG_STATUS 0x0e
+#define PI3USB9281_REG_MANUAL 0x13
+#define PI3USB9281_REG_RESET 0x1b
+#define PI3USB9281_REG_VBUS 0x1d
 
-#define PI3USB9281_DEV_ID           0x10
-#define PI3USB9281_DEV_ID_A         0x18
+#define PI3USB9281_DEV_ID 0x10
+#define PI3USB9281_DEV_ID_A 0x18
 
-#define PI3USB9281_CTRL_INT_DIS     BIT(0)
-#define PI3USB9281_CTRL_AUTO        BIT(2)
+#define PI3USB9281_CTRL_INT_DIS BIT(0)
+#define PI3USB9281_CTRL_AUTO BIT(2)
 #define PI3USB9281_CTRL_SWITCH_AUTO BIT(4)
 /* Bits 5 thru 7 are read X, write 0 */
-#define PI3USB9281_CTRL_MASK        0x1f
+#define PI3USB9281_CTRL_MASK 0x1f
 /* Bits 1 and 3 are read 1, write 1 */
-#define PI3USB9281_CTRL_RSVD_1      0x0a
+#define PI3USB9281_CTRL_RSVD_1 0x0a
 
-#define PI3USB9281_PIN_MANUAL_VBUS  (3 << 0)
-#define PI3USB9281_PIN_MANUAL_DP    BIT(2)
-#define PI3USB9281_PIN_MANUAL_DM    BIT(5)
+#define PI3USB9281_PIN_MANUAL_VBUS (3 << 0)
+#define PI3USB9281_PIN_MANUAL_DP BIT(2)
+#define PI3USB9281_PIN_MANUAL_DM BIT(5)
 
-#define PI3USB9281_INT_ATTACH       BIT(0)
-#define PI3USB9281_INT_DETACH       BIT(1)
-#define PI3USB9281_INT_OVP          BIT(5)
-#define PI3USB9281_INT_OCP          BIT(6)
-#define PI3USB9281_INT_OVP_OC       BIT(7)
-#define PI3USB9281_INT_ATTACH_DETACH (PI3USB9281_INT_ATTACH | \
-				      PI3USB9281_INT_DETACH)
+#define PI3USB9281_INT_ATTACH BIT(0)
+#define PI3USB9281_INT_DETACH BIT(1)
+#define PI3USB9281_INT_OVP BIT(5)
+#define PI3USB9281_INT_OCP BIT(6)
+#define PI3USB9281_INT_OVP_OC BIT(7)
+#define PI3USB9281_INT_ATTACH_DETACH \
+	(PI3USB9281_INT_ATTACH | PI3USB9281_INT_DETACH)
 
-#define PI3USB9281_TYPE_NONE        0
-#define PI3USB9281_TYPE_MHL         BIT(0)
-#define PI3USB9281_TYPE_OTG         BIT(1)
-#define PI3USB9281_TYPE_SDP         BIT(2)
-#define PI3USB9281_TYPE_CAR         BIT(4)
-#define PI3USB9281_TYPE_CDP         BIT(5)
-#define PI3USB9281_TYPE_DCP         BIT(6)
+#define PI3USB9281_TYPE_NONE 0
+#define PI3USB9281_TYPE_MHL BIT(0)
+#define PI3USB9281_TYPE_OTG BIT(1)
+#define PI3USB9281_TYPE_SDP BIT(2)
+#define PI3USB9281_TYPE_CAR BIT(4)
+#define PI3USB9281_TYPE_CDP BIT(5)
+#define PI3USB9281_TYPE_DCP BIT(6)
 
-#define PI3USB9281_CHG_NONE         0
-#define PI3USB9281_CHG_CAR_TYPE1    BIT(1)
-#define PI3USB9281_CHG_CAR_TYPE2    (3 << 0)
-#define PI3USB9281_CHG_APPLE_1A     BIT(2)
-#define PI3USB9281_CHG_APPLE_2A     BIT(3)
-#define PI3USB9281_CHG_APPLE_2_4A   BIT(4)
+#define PI3USB9281_CHG_NONE 0
+#define PI3USB9281_CHG_CAR_TYPE1 BIT(1)
+#define PI3USB9281_CHG_CAR_TYPE2 (3 << 0)
+#define PI3USB9281_CHG_APPLE_1A BIT(2)
+#define PI3USB9281_CHG_APPLE_2A BIT(3)
+#define PI3USB9281_CHG_APPLE_2_4A BIT(4)
 /* Check if charge status has any connection */
-#define PI3USB9281_CHG_STATUS_ANY(x) (((x) & 0x1f) > 1)
+#define PI3USB9281_CHG_STATUS_ANY(x) (((x)&0x1f) > 1)
 
 /* Define configuration of one pi3usb9281 part */
 struct pi3usb9281_config {
diff --git a/driver/bc12/rt1718s.c b/driver/bc12/rt1718s.c
new file mode 100644
index 0000000000..16c543d9d3
--- /dev/null
+++ b/driver/bc12/rt1718s.c
@@ -0,0 +1,197 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * RT1718S BC 1.2 Driver
+ */
+
+#include "battery.h"
+#include "console.h"
+#include "driver/tcpm/rt1718s.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "stdint.h"
+#include "system.h"
+#include "task.h"
+#include "timer.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pe_sm.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/* enable bc 1.2 sink function  */
+static int rt1718s_enable_bc12_sink(int port, bool en)
+{
+	return rt1718s_update_bits8(port, RT1718S_RT2_BC12_SNK_FUNC,
+				    RT1718S_RT2_BC12_SNK_FUNC_BC12_SNK_EN,
+				    en ? 0xFF : 0);
+}
+
+static int rt1718s_set_bc12_sink_spec_ta(int port, bool en)
+{
+	return rt1718s_update_bits8(port, RT1718S_RT2_BC12_SNK_FUNC,
+				    RT1718S_RT2_BC12_SNK_FUNC_SPEC_TA_EN,
+				    en ? 0xFF : 0);
+}
+
+static int rt1718s_set_bc12_sink_dcdt_sel(int port, uint8_t dcdt_sel)
+{
+	return rt1718s_update_bits8(port, RT1718S_RT2_BC12_SNK_FUNC,
+				    RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_MASK,
+				    dcdt_sel);
+}
+
+static int rt1718s_set_bc12_sink_vlgc_option(int port, bool en)
+{
+	return rt1718s_update_bits8(port, RT1718S_RT2_BC12_SNK_FUNC,
+				    RT1718S_RT2_BC12_SNK_FUNC_VLGC_OPT,
+				    en ? 0xFF : 0);
+}
+
+static int rt1718s_set_bc12_sink_vport_sel(int port, uint8_t sel)
+{
+	return rt1718s_update_bits8(
+		port, RT1718S_RT2_DPDM_CTR1_DPDM_SET,
+		RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_MASK, sel);
+}
+
+static int rt1718s_set_bc12_sink_wait_vbus(int port, bool en)
+{
+	return rt1718s_update_bits8(port, RT1718S_RT2_BC12_SNK_FUNC,
+				    RT1718S_RT2_BC12_SNK_FUNC_BC12_WAIT_VBUS,
+				    en ? 0xFF : 0);
+}
+
+/*
+ * rt1718s BC12 function initial
+ */
+int rt1718s_bc12_init(int port)
+{
+	/* Enable vendor defined BC12 function */
+	RETURN_ERROR(rt1718s_write8(port, RT1718S_RT_MASK6,
+				    RT1718S_RT_MASK6_M_BC12_SNK_DONE |
+					    RT1718S_RT_MASK6_M_BC12_TA_CHG));
+
+	RETURN_ERROR(rt1718s_write8(port, RT1718S_RT2_SBU_CTRL_01,
+				    RT1718S_RT2_SBU_CTRL_01_DPDM_VIEN |
+					    RT1718S_RT2_SBU_CTRL_01_DM_SWEN |
+					    RT1718S_RT2_SBU_CTRL_01_DP_SWEN));
+
+	/* Disable 2.7v mode */
+	RETURN_ERROR(rt1718s_set_bc12_sink_spec_ta(port, false));
+
+	/* DCDT select 600ms timeout */
+	RETURN_ERROR(rt1718s_set_bc12_sink_dcdt_sel(
+		port, RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_600MS));
+
+	/* Disable vlgc option */
+	RETURN_ERROR(rt1718s_set_bc12_sink_vlgc_option(port, false));
+
+	/* DPDM voltage selection */
+	RETURN_ERROR(rt1718s_set_bc12_sink_vport_sel(
+		port, RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_0_65V));
+
+	/* Disable sink wait vbus */
+	RETURN_ERROR(rt1718s_set_bc12_sink_wait_vbus(port, false));
+
+	return EC_SUCCESS;
+}
+
+static enum charge_supplier rt1718s_get_bc12_type(int port)
+{
+	int data;
+
+	if (rt1718s_read8(port, RT1718S_RT2_BC12_STAT, &data))
+		return CHARGE_SUPPLIER_OTHER;
+
+	switch (data & RT1718S_RT2_BC12_STAT_PORT_STATUS_MASK) {
+	case RT1718S_RT2_BC12_STAT_PORT_STATUS_NONE:
+		return CHARGE_SUPPLIER_NONE;
+	case RT1718S_RT2_BC12_STAT_PORT_STATUS_SDP:
+		return CHARGE_SUPPLIER_BC12_SDP;
+	case RT1718S_RT2_BC12_STAT_PORT_STATUS_CDP:
+		return CHARGE_SUPPLIER_BC12_CDP;
+	case RT1718S_RT2_BC12_STAT_PORT_STATUS_DCP:
+		return CHARGE_SUPPLIER_BC12_DCP;
+	}
+
+	return CHARGE_SUPPLIER_OTHER;
+}
+
+static int rt1718s_get_bc12_ilim(enum charge_supplier supplier)
+{
+	switch (supplier) {
+	case CHARGE_SUPPLIER_BC12_DCP:
+	case CHARGE_SUPPLIER_BC12_CDP:
+		return USB_CHARGER_MAX_CURR_MA;
+	case CHARGE_SUPPLIER_BC12_SDP:
+	default:
+		return USB_CHARGER_MIN_CURR_MA;
+	}
+}
+
+static void rt1718s_update_charge_manager(int port,
+					  enum charge_supplier new_bc12_type)
+{
+	static enum charge_supplier current_bc12_type = CHARGE_SUPPLIER_NONE;
+
+	if (new_bc12_type != current_bc12_type) {
+		if (current_bc12_type != CHARGE_SUPPLIER_NONE)
+			charge_manager_update_charge(current_bc12_type, port,
+						     NULL);
+
+		if (new_bc12_type != CHARGE_SUPPLIER_NONE) {
+			struct charge_port_info chg = {
+				.current = rt1718s_get_bc12_ilim(new_bc12_type),
+				.voltage = USB_CHARGER_VOLTAGE_MV,
+			};
+
+			charge_manager_update_charge(new_bc12_type, port, &chg);
+		}
+
+		current_bc12_type = new_bc12_type;
+	}
+}
+
+static void rt1718s_bc12_usb_charger_task_init(const int port)
+{
+	rt1718s_enable_bc12_sink(port, false);
+}
+
+static void rt1718s_bc12_usb_charger_task_event(const int port, uint32_t evt)
+{
+	bool is_non_pd_sink = !pd_capable(port) &&
+			      !usb_charger_port_is_sourcing_vbus(port) &&
+			      pd_check_vbus_level(port, VBUS_PRESENT);
+
+	if (evt & USB_CHG_EVENT_VBUS) {
+		if (is_non_pd_sink)
+			rt1718s_enable_bc12_sink(port, true);
+		else
+			rt1718s_update_charge_manager(port,
+						      CHARGE_SUPPLIER_NONE);
+	}
+
+	/* detection done, update charge_manager and stop detection */
+	if (evt & USB_CHG_EVENT_BC12) {
+		int type;
+
+		if (is_non_pd_sink)
+			type = rt1718s_get_bc12_type(port);
+		else
+			type = CHARGE_SUPPLIER_NONE;
+
+		rt1718s_update_charge_manager(port, type);
+		rt1718s_enable_bc12_sink(port, false);
+	}
+}
+
+const struct bc12_drv rt1718s_bc12_drv = {
+	.usb_charger_task_init = rt1718s_bc12_usb_charger_task_init,
+	.usb_charger_task_event = rt1718s_bc12_usb_charger_task_event,
+};
diff --git a/driver/bc12/rt1718s.h b/driver/bc12/rt1718s.h
new file mode 100644
index 0000000000..03ca63f329
--- /dev/null
+++ b/driver/bc12/rt1718s.h
@@ -0,0 +1,12 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Richtek BC 1.2 Detection */
+
+#ifndef __CROS_EC_DRIVER_BC12_RT1718S_H
+#define __CROS_EC_DRIVER_BC12_RT1718S_H
+
+int rt1718s_bc12_init(int port);
+#endif /* __CROS_EC_DRIVER_BC12_RT1718S_H */
diff --git a/driver/build.mk b/driver/build.mk
index 5d4f92e6be..64ccb3ec4e 100644
--- a/driver/build.mk
+++ b/driver/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
+# Copyright 2014 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -15,7 +15,10 @@ driver-$(CONFIG_ACCEL_KXCJ9)+=accel_kionix.o
 driver-$(CONFIG_ACCEL_KX022)+=accel_kionix.o
 driver-$(CONFIG_ACCELGYRO_LSM6DS0)+=accelgyro_lsm6ds0.o
 driver-$(CONFIG_ACCELGYRO_BMI160)+=accelgyro_bmi160.o accelgyro_bmi_common.o
+driver-$(CONFIG_ACCELGYRO_BMI220)+=accelgyro_bmi260.o accelgyro_bmi_common.o
 driver-$(CONFIG_ACCELGYRO_BMI260)+=accelgyro_bmi260.o accelgyro_bmi_common.o
+driver-$(CONFIG_ACCELGYRO_BMI3XX)+=accelgyro_bmi3xx.o accelgyro_bmi_common.o
+driver-$(CONFIG_ACCEL_BMA4XX)+=accel_bma4xx.o
 driver-$(CONFIG_MAG_BMI_BMM150)+=mag_bmm150.o
 driver-$(CONFIG_ACCELGYRO_LSM6DSM)+=accelgyro_lsm6dsm.o stm_mems_common.o
 driver-$(CONFIG_ACCELGYRO_LSM6DSO)+=accelgyro_lsm6dso.o stm_mems_common.o
@@ -26,12 +29,14 @@ driver-$(CONFIG_SYNC)+=sync.o
 driver-$(CONFIG_ACCEL_LIS2DW_COMMON)+=accel_lis2dw12.o stm_mems_common.o
 driver-$(CONFIG_ACCEL_LIS2DS)+=accel_lis2ds.o stm_mems_common.o
 driver-$(CONFIG_ACCELGYRO_ICM426XX)+=accelgyro_icm426xx.o accelgyro_icm_common.o
+driver-$(CONFIG_ACCELGYRO_ICM42607)+=accelgyro_icm42607.o accelgyro_icm_common.o
 
 # BC1.2 Charger Detection Devices
 driver-$(CONFIG_BC12_DETECT_MAX14637)+=bc12/max14637.o
 driver-$(CONFIG_BC12_DETECT_MT6360)+=bc12/mt6360.o
 driver-$(CONFIG_BC12_DETECT_PI3USB9201)+=bc12/pi3usb9201.o
 driver-$(CONFIG_BC12_DETECT_PI3USB9281)+=bc12/pi3usb9281.o
+driver-$(CONFIG_BC12_DETECT_RT1718S)+=bc12/rt1718s.o
 
 # Gyrometers
 driver-$(CONFIG_GYRO_L3GD20H)+=gyro_l3gd20h.o
@@ -43,6 +48,7 @@ driver-$(CONFIG_ALS_OPT3001)+=als_opt3001.o
 driver-$(CONFIG_ALS_SI114X)+=als_si114x.o
 driver-$(CONFIG_ALS_BH1730)+=als_bh1730.o
 driver-$(CONFIG_ALS_TCS3400)+=als_tcs3400.o
+driver-$(CONFIG_ALS_CM32183)+=als_cm32183.o
 
 # Barometers
 driver-$(CONFIG_BARO_BMP280)+=baro_bmp280.o
@@ -52,7 +58,9 @@ driver-$(CONFIG_BATTERY_BQ20Z453)+=battery/bq20z453.o
 driver-$(CONFIG_BATTERY_BQ27541)+=battery/bq27541.o
 driver-$(CONFIG_BATTERY_BQ27621)+=battery/bq27621_g1.o
 driver-$(CONFIG_BATTERY_MAX17055)+=battery/max17055.o
+ifeq ($(HAS_MOCK_BATTERY),)
 driver-$(CONFIG_BATTERY_SMART)+=battery/smart.o
+endif
 driver-$(CONFIG_BATTERY_BQ4050)+=battery/bq4050.o
 driver-$(CONFIG_BATTERY_MM8013)+=battery/mm8013.o
 
@@ -62,29 +70,42 @@ driver-$(CONFIG_CHARGER_BQ24715)+=charger/bq24715.o
 driver-$(CONFIG_CHARGER_BQ24770)+=charger/bq24773.o
 driver-$(CONFIG_CHARGER_BQ24773)+=charger/bq24773.o
 driver-$(CONFIG_CHARGER_BQ25710)+=charger/bq25710.o
+driver-$(CONFIG_CHARGER_BQ25720)+=charger/bq25710.o
 driver-$(CONFIG_CHARGER_ISL9237)+=charger/isl923x.o
 driver-$(CONFIG_CHARGER_ISL9238)+=charger/isl923x.o
 driver-$(CONFIG_CHARGER_ISL9238C)+=charger/isl923x.o
 driver-$(CONFIG_CHARGER_ISL9241)+=charger/isl9241.o
 driver-$(CONFIG_CHARGER_MT6370)+=charger/rt946x.o
 driver-$(CONFIG_CHARGER_RAA489000)+=charger/isl923x.o
+driver-$(CONFIG_CHARGER_RAA489110)+=charger/isl9241.o
 driver-$(CONFIG_CHARGER_RT9466)+=charger/rt946x.o
 driver-$(CONFIG_CHARGER_RT9467)+=charger/rt946x.o
+driver-$(CONFIG_CHARGER_RT9490)+=charger/rt9490.o
 driver-$(CONFIG_CHARGER_SY21612)+=charger/sy21612.o
 driver-$(CONFIG_CHARGER_SM5803)+=charger/sm5803.o
 
+# CEC drivers
+driver-$(CONFIG_CEC_BITBANG)+=cec/bitbang.o
+
+# DP Redrivers
+driver-$(CONFIG_DP_REDRIVER_TDP142)+=retimer/tdp142.o
+
 # Fingerprint Sensors
 include $(_driver_cur_dir)fingerprint/build.mk
 
 # I/O expander
+driver-$(CONFIG_IO_EXPANDER_CCGXXF)+=ioexpander/ccgxxf.o
 driver-$(CONFIG_IO_EXPANDER_IT8801)+=ioexpander/it8801.o
-driver-$(CONFIG_IO_EXPANDER_PCA9534)+=ioexpander/pca9534.o
 driver-$(CONFIG_IO_EXPANDER_NCT38XX)+=ioexpander/ioexpander_nct38xx.o
+driver-$(CONFIG_IO_EXPANDER_PCA9534)+=ioexpander/pca9534.o
+driver-$(CONFIG_IO_EXPANDER_PCA9675)+=ioexpander/pca9675.o
 driver-$(CONFIG_IO_EXPANDER_PCAL6408)+=ioexpander/pcal6408.o
+driver-$(CONFIG_IO_EXPANDER_TCA64XXA)+=ioexpander/tca64xxa.o
 
+driver-$(CONFIG_CTN730)+=nfc/ctn730.o
 
 # Current/Power monitor
-driver-$(CONFIG_INA219)$(CONFIG_INA231)+=ina2xx.o
+driver-$(CONFIG_INA219)$(CONFIG_INA231)$(CONFIG_INA236)+=ina2xx.o
 driver-$(CONFIG_INA3221)+=ina3221.o
 
 # LED drivers
@@ -92,14 +113,25 @@ driver-$(CONFIG_LED_DRIVER_DS2413)+=led/ds2413.o
 driver-$(CONFIG_LED_DRIVER_LM3509)+=led/lm3509.o
 driver-$(CONFIG_LED_DRIVER_LM3630A)+=led/lm3630a.o
 driver-$(CONFIG_LED_DRIVER_LP5562)+=led/lp5562.o
+driver-$(CONFIG_LED_DRIVER_MP3385)+=led/mp3385.o
 driver-$(CONFIG_LED_DRIVER_OZ554)+=led/oz554.o
+driver-$(CONFIG_LED_DRIVER_IS31FL3733B)+=led/is31fl3733b.o
+driver-$(CONFIG_LED_DRIVER_IS31FL3743B)+=led/is31fl3743b.o
+driver-$(CONFIG_LED_DRIVER_AW20198)+=led/aw20198.o
+driver-$(CONFIG_LED_DRIVER_TLC59116F)+=led/tlc59116f.o
 
 # 7-segment display
 driver-$(CONFIG_MAX695X_SEVEN_SEGMENT_DISPLAY)+=led/max695x.o
 
+# Nvidia GPU D-Notify driver
+driver-$(CONFIG_GPU_NVIDIA)+=nvidia_gpu.o
+
 # Voltage regulators
 driver-$(CONFIG_REGULATOR_IR357X)+=regulator_ir357x.o
 
+# Power Sourcing Equipment
+driver-$(CONFIG_PSE_LTC4291)+=pse_ltc4291.o
+
 # Temperature sensors
 driver-$(CONFIG_TEMP_SENSOR_ADT7481)+=temp_sensor/adt7481.o
 driver-$(CONFIG_TEMP_SENSOR_BD99992GW)+=temp_sensor/bd99992gw.o
@@ -109,6 +141,7 @@ driver-$(CONFIG_TEMP_SENSOR_G753)+=temp_sensor/g753.o
 driver-$(CONFIG_TEMP_SENSOR_G781)+=temp_sensor/g78x.o
 driver-$(CONFIG_TEMP_SENSOR_G782)+=temp_sensor/g78x.o
 driver-$(CONFIG_TEMP_SENSOR_OTI502)+=temp_sensor/oti502.o
+driver-$(CONFIG_TEMP_SENSOR_PCT2075)+=temp_sensor/pct2075.o
 driver-$(CONFIG_TEMP_SENSOR_SB_TSI)+=temp_sensor/sb_tsi.o
 driver-$(CONFIG_TEMP_SENSOR_TMP006)+=temp_sensor/tmp006.o
 driver-$(CONFIG_TEMP_SENSOR_TMP112)+=temp_sensor/tmp112.o
@@ -127,17 +160,21 @@ driver-$(CONFIG_THERMISTOR)+=temp_sensor/thermistor.o
 driver-$(CONFIG_THERMISTOR_NCP15WB)+=temp_sensor/thermistor_ncp15wb.o
 
 # Type-C port controller (TCPC) drivers
+driver-$(CONFIG_USB_PD_TCPM_CCGXXF)+=tcpm/ccgxxf.o
 driver-$(CONFIG_USB_PD_TCPM_STUB)+=tcpm/stub.o
 driver-$(CONFIG_USB_PD_TCPM_TCPCI)+=tcpm/tcpci.o
 driver-$(CONFIG_USB_PD_TCPM_FUSB302)+=tcpm/fusb302.o
 driver-$(CONFIG_USB_PD_TCPM_MT6370)+=tcpm/mt6370.o
 ifdef CONFIG_USB_PD_TCPM_ITE_ON_CHIP
+driver-y +=tcpm/ite_pd_intc.o
 driver-$(CONFIG_USB_PD_TCPM_DRIVER_IT83XX)+=tcpm/it83xx.o
 driver-$(CONFIG_USB_PD_TCPM_DRIVER_IT8XXX2)+=tcpm/it8xxx2.o
 endif
+driver-$(CONFIG_USB_PD_TCPM_ANX7406)+=tcpm/anx7406.o
 driver-$(CONFIG_USB_PD_TCPM_ANX74XX)+=tcpm/anx74xx.o
 driver-$(CONFIG_USB_PD_TCPM_ANX7688)+=tcpm/anx7688.o
 driver-$(CONFIG_USB_PD_TCPM_ANX7447)+=tcpm/anx7447.o
+driver-$(CONFIG_USB_PD_TCPM_PS8745)+=tcpm/ps8xxx.o
 driver-$(CONFIG_USB_PD_TCPM_PS8751)+=tcpm/ps8xxx.o
 driver-$(CONFIG_USB_PD_TCPM_PS8755)+=tcpm/ps8xxx.o
 driver-$(CONFIG_USB_PD_TCPM_PS8705)+=tcpm/ps8xxx.o
@@ -145,17 +182,23 @@ driver-$(CONFIG_USB_PD_TCPM_PS8805)+=tcpm/ps8xxx.o
 driver-$(CONFIG_USB_PD_TCPM_PS8815)+=tcpm/ps8xxx.o
 driver-$(CONFIG_USB_PD_TCPM_TUSB422)+=tcpm/tusb422.o
 driver-$(CONFIG_USB_PD_TCPM_RT1715)+=tcpm/rt1715.o
+driver-$(CONFIG_USB_PD_TCPM_RT1718S)+=tcpm/rt1718s.o
 driver-$(CONFIG_USB_PD_TCPM_NCT38XX)+=tcpm/nct38xx.o
 driver-$(CONFIG_USB_PD_TCPM_RAA489000)+=tcpm/raa489000.o
 driver-$(CONFIG_USB_PD_TCPM_FUSB307)+=tcpm/fusb307.o
 driver-$(CONFIG_USB_PD_TCPM_STM32GX)+=tcpm/stm32gx.o
 
 # Type-C Retimer drivers
+driver-$(CONFIG_USBC_RETIMER_ANX7483)+=retimer/anx7483.o
+driver-$(CONFIG_USBC_RETIMER_ANX7452)+=retimer/anx7452.o
 driver-$(CONFIG_USBC_RETIMER_INTEL_BB)+=retimer/bb_retimer.o
+driver-$(CONFIG_USBC_RETIMER_KB800X)+=retimer/kb800x.o
+driver-$(CONFIG_USBC_RETIMER_KB8010)+=retimer/kb8010.o
 driver-$(CONFIG_USBC_RETIMER_NB7V904M)+=retimer/nb7v904m.o
 driver-$(CONFIG_USBC_RETIMER_PI3DPX1207)+=retimer/pi3dpx1207.o
 driver-$(CONFIG_USBC_RETIMER_PI3HDX1204)+=retimer/pi3hdx1204.o
 driver-$(CONFIG_USBC_RETIMER_PS8802)+=retimer/ps8802.o
+driver-$(CONFIG_USBC_RETIMER_PS8811)+=retimer/ps8811.o
 driver-$(CONFIG_USBC_RETIMER_PS8818)+=retimer/ps8818.o
 driver-$(CONFIG_USBC_RETIMER_TUSB544)+=retimer/tusb544.o
 
@@ -164,23 +207,37 @@ driver-$(CONFIG_USBC_SS_MUX)+=usb_mux/usb_mux.o
 
 # USB muxes
 driver-$(CONFIG_USB_MUX_AMD_FP5)+=usb_mux/amd_fp5.o
+driver-$(CONFIG_USB_MUX_AMD_FP6)+=usb_mux/amd_fp6.o
+driver-$(CONFIG_USB_MUX_ANX3443)+=usb_mux/anx3443.o
 driver-$(CONFIG_USB_MUX_ANX7440)+=usb_mux/anx7440.o
+driver-$(CONFIG_USB_MUX_ANX7451)+=usb_mux/anx7451.o
 driver-$(CONFIG_USB_MUX_IT5205)+=usb_mux/it5205.o
 driver-$(CONFIG_USB_MUX_PI3USB30532)+=usb_mux/pi3usb3x532.o
 driver-$(CONFIG_USB_MUX_PI3USB31532)+=usb_mux/pi3usb3x532.o
 driver-$(CONFIG_USB_MUX_PS8740)+=usb_mux/ps8740.o
 driver-$(CONFIG_USB_MUX_PS8742)+=usb_mux/ps8740.o
 driver-$(CONFIG_USB_MUX_PS8743)+=usb_mux/ps8743.o
+driver-$(CONFIG_USB_MUX_PS8822)+=usb_mux/ps8822.o
+driver-$(CONFIG_USB_MUX_TUSB1044)+=usb_mux/tusb1064.o
+driver-$(CONFIG_USB_MUX_TUSB1064)+=usb_mux/tusb1064.o
+driver-$(CONFIG_USB_MUX_TUSB546)+=usb_mux/tusb1064.o
 driver-$(CONFIG_USB_MUX_VIRTUAL)+=usb_mux/virtual.o
 
+# USB Hub with I2C interface
+driver-$(CONFIG_USB_HUB_GL3590)+=gl3590.o
+
 # Type-C Power Path Controllers (PPC)
 driver-$(CONFIG_USBC_PPC_AOZ1380)+=ppc/aoz1380.o
+driver-$(CONFIG_USBC_PPC_RT1718S)+=ppc/rt1718s.o
+driver-$(CONFIG_USBC_PPC_RT1739)+=ppc/rt1739.o
 driver-$(CONFIG_USBC_PPC_SN5S330)+=ppc/sn5s330.o
 ifeq ($(CONFIG_USBC_PPC_NX20P3481)$(CONFIG_USBC_PPC_NX20P3483),y)
 driver-y += ppc/nx20p348x.o
 endif
 driver-$(CONFIG_USBC_PPC_SYV682X)+=ppc/syv682x.o
 driver-$(CONFIG_USBC_PPC_NX20P3483)+=ppc/nx20p348x.o
+driver-$(CONFIG_USBC_PPC_KTU1125)+=ppc/ktu1125.o
+driver-$(CONFIG_USBC_PPC_TCPCI)+=ppc/tcpci_ppc.o
 
 # Switchcap
 driver-$(CONFIG_LN9310)+=ln9310.o
@@ -189,4 +246,15 @@ driver-$(CONFIG_LN9310)+=ln9310.o
 driver-$(CONFIG_MCDP28X0)+=mcdp28x0.o
 
 # Wireless Power Chargers
+driver-$(CONFIG_CPS8100)+=wpc/cps8100.o
 driver-$(HAS_TASK_WPC) += wpc/p9221.o
+
+# Buck-Boost converters
+driver-$(CONFIG_MP4245)+=mp4245.o
+
+# Power Management ICs
+driver-$(CONFIG_MP2964)+=mp2964.o
+
+# SOC Interface
+driver-$(CONFIG_AMD_SB_RMI)+=sb_rmi.o
+driver-$(CONFIG_AMD_STT)+=amd_stt.o
diff --git a/driver/cec/bitbang.c b/driver/cec/bitbang.c
new file mode 100644
index 0000000000..b91a9d1e87
--- /dev/null
+++ b/driver/cec/bitbang.c
@@ -0,0 +1,760 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cec.h"
+#include "cec_bitbang_chip.h"
+#include "console.h"
+#include "driver/cec/bitbang.h"
+#include "gpio.h"
+#include "task.h"
+#include "util.h"
+
+#ifdef CONFIG_CEC_DEBUG
+#define CPRINTF(format, args...) cprintf(CC_CEC, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CEC, format, ##args)
+#else
+#define CPRINTF(...)
+#define CPRINTS(...)
+#endif
+
+/*
+ * Free time timing (us). Our free-time is calculated from the end of
+ * the last bit (not from the start). We compensate by having one
+ * free-time period less than in the spec.
+ */
+#define NOMINAL_BIT_TICKS CEC_US_TO_TICKS(2400)
+/* Resend */
+#define FREE_TIME_RS_TICKS (2 * (NOMINAL_BIT_TICKS))
+/* New initiator */
+#define FREE_TIME_NI_TICKS (4 * (NOMINAL_BIT_TICKS))
+/* Present initiator */
+#define FREE_TIME_PI_TICKS (6 * (NOMINAL_BIT_TICKS))
+
+/* Start bit timing */
+#define START_BIT_LOW_TICKS CEC_US_TO_TICKS(3700)
+#define START_BIT_MIN_LOW_TICKS CEC_US_TO_TICKS(3500)
+#define START_BIT_MAX_LOW_TICKS CEC_US_TO_TICKS(3900)
+#define START_BIT_HIGH_TICKS CEC_US_TO_TICKS(800)
+#define START_BIT_MIN_DURATION_TICKS CEC_US_TO_TICKS(4300)
+#define START_BIT_MAX_DURATION_TICKS CEC_US_TO_TICKS(5700)
+
+/* Data bit timing */
+#define DATA_ZERO_LOW_TICKS CEC_US_TO_TICKS(1500)
+#define DATA_ZERO_MIN_LOW_TICKS CEC_US_TO_TICKS(1300)
+#define DATA_ZERO_MAX_LOW_TICKS CEC_US_TO_TICKS(1700)
+#define DATA_ZERO_HIGH_TICKS CEC_US_TO_TICKS(900)
+#define DATA_ZERO_MIN_DURATION_TICKS CEC_US_TO_TICKS(2050)
+#define DATA_ZERO_MAX_DURATION_TICKS CEC_US_TO_TICKS(2750)
+
+#define DATA_ONE_LOW_TICKS CEC_US_TO_TICKS(600)
+#define DATA_ONE_MIN_LOW_TICKS CEC_US_TO_TICKS(400)
+#define DATA_ONE_MAX_LOW_TICKS CEC_US_TO_TICKS(800)
+#define DATA_ONE_HIGH_TICKS CEC_US_TO_TICKS(1800)
+#define DATA_ONE_MIN_DURATION_TICKS CEC_US_TO_TICKS(2050)
+#define DATA_ONE_MAX_DURATION_TICKS CEC_US_TO_TICKS(2750)
+
+/* Time from low that it should be safe to sample an ACK */
+#define NOMINAL_SAMPLE_TIME_TICKS CEC_US_TO_TICKS(1050)
+
+#define DATA_TIME(type, data) \
+	((data) ? (DATA_ONE_##type##_TICKS) : (DATA_ZERO_##type##_TICKS))
+#define DATA_HIGH(data) DATA_TIME(HIGH, data)
+#define DATA_LOW(data) DATA_TIME(LOW, data)
+
+/*
+ * Number of short pulses seen before the debounce logic goes into ignoring
+ * the bus for DEBOUNCE_WAIT_LONG instead of DEBOUNCE_WAIT_SHORT
+ */
+#define DEBOUNCE_CUTOFF 3
+
+/* The limit how short a start-bit can be to trigger debounce logic */
+#define DEBOUNCE_LIMIT_TICKS CEC_US_TO_TICKS(200)
+/* The time we ignore the bus for the first three debounce cases */
+#define DEBOUNCE_WAIT_SHORT_TICKS CEC_US_TO_TICKS(100)
+/* The time we ignore the bus after the three initial debounce cases */
+#define DEBOUNCE_WAIT_LONG_TICKS CEC_US_TO_TICKS(500)
+
+/*
+ * The variance in timing we allow outside of the CEC specification for
+ * incoming signals. Our measurements aren't 100% accurate either, so this
+ * gives some robustness.
+ */
+#define VALID_TOLERANCE_TICKS CEC_US_TO_TICKS(100)
+
+/*
+ * Defines used for setting capture timers to a point where we are
+ * sure that if we get a timeout, something is wrong.
+ */
+#define CAP_START_LOW_TICKS (START_BIT_MAX_LOW_TICKS + VALID_TOLERANCE_TICKS)
+#define CAP_START_HIGH_TICKS                                      \
+	(START_BIT_MAX_DURATION_TICKS - START_BIT_MIN_LOW_TICKS + \
+	 VALID_TOLERANCE_TICKS)
+#define CAP_DATA_LOW_TICKS (DATA_ZERO_MAX_LOW_TICKS + VALID_TOLERANCE_TICKS)
+#define CAP_DATA_HIGH_TICKS                                     \
+	(DATA_ONE_MAX_DURATION_TICKS - DATA_ONE_MIN_LOW_TICKS + \
+	 VALID_TOLERANCE_TICKS)
+
+#define VALID_TIME(type, bit, t)                                          \
+	((t) >= ((bit##_MIN_##type##_TICKS) - (VALID_TOLERANCE_TICKS)) && \
+	 (t) <= (bit##_MAX_##type##_TICKS) + (VALID_TOLERANCE_TICKS))
+#define VALID_LOW(bit, t) VALID_TIME(LOW, bit, t)
+#define VALID_HIGH(bit, low_time, high_time)                   \
+	(((low_time) + (high_time) <=                          \
+	  bit##_MAX_DURATION_TICKS + VALID_TOLERANCE_TICKS) && \
+	 ((low_time) + (high_time) >=                          \
+	  bit##_MIN_DURATION_TICKS - VALID_TOLERANCE_TICKS))
+#define VALID_DATA_HIGH(data, low_time, high_time)            \
+	((data) ? VALID_HIGH(DATA_ONE, low_time, high_time) : \
+		  VALID_HIGH(DATA_ZERO, low_time, high_time))
+
+/*
+ * CEC state machine states. Each state typically takes action on entry and
+ * timeouts. INITIATIOR states are used for sending, FOLLOWER states are used
+ *  for receiving.
+ */
+enum cec_state {
+	CEC_STATE_DISABLED = 0,
+	CEC_STATE_IDLE,
+	CEC_STATE_INITIATOR_FREE_TIME,
+	CEC_STATE_INITIATOR_START_LOW,
+	CEC_STATE_INITIATOR_START_HIGH,
+	CEC_STATE_INITIATOR_HEADER_INIT_LOW,
+	CEC_STATE_INITIATOR_HEADER_INIT_HIGH,
+	CEC_STATE_INITIATOR_HEADER_DEST_LOW,
+	CEC_STATE_INITIATOR_HEADER_DEST_HIGH,
+	CEC_STATE_INITIATOR_DATA_LOW,
+	CEC_STATE_INITIATOR_DATA_HIGH,
+	CEC_STATE_INITIATOR_EOM_LOW,
+	CEC_STATE_INITIATOR_EOM_HIGH,
+	CEC_STATE_INITIATOR_ACK_LOW,
+	CEC_STATE_INITIATOR_ACK_HIGH,
+	CEC_STATE_INITIATOR_ACK_VERIFY,
+	CEC_STATE_FOLLOWER_START_LOW,
+	CEC_STATE_FOLLOWER_START_HIGH,
+	CEC_STATE_FOLLOWER_DEBOUNCE,
+	CEC_STATE_FOLLOWER_HEADER_INIT_LOW,
+	CEC_STATE_FOLLOWER_HEADER_INIT_HIGH,
+	CEC_STATE_FOLLOWER_HEADER_DEST_LOW,
+	CEC_STATE_FOLLOWER_HEADER_DEST_HIGH,
+	CEC_STATE_FOLLOWER_EOM_LOW,
+	CEC_STATE_FOLLOWER_EOM_HIGH,
+	CEC_STATE_FOLLOWER_ACK_LOW,
+	CEC_STATE_FOLLOWER_ACK_VERIFY,
+	CEC_STATE_FOLLOWER_ACK_FINISH,
+	CEC_STATE_FOLLOWER_DATA_LOW,
+	CEC_STATE_FOLLOWER_DATA_HIGH,
+};
+
+/* Receive buffer and states */
+struct cec_rx {
+	/*
+	 * The current incoming message being parsed. Copied to
+	 * receive queue upon completion
+	 */
+	struct cec_msg_transfer transfer;
+	/* End of Message received from source? */
+	uint8_t eom;
+	/* A follower NAK:ed a broadcast transfer */
+	uint8_t broadcast_nak;
+	/*
+	 * Keep track of pulse low time to be able to verify
+	 * pulse duration
+	 */
+	int low_ticks;
+	/* Number of too short pulses seen in a row */
+	int debounce_count;
+};
+
+/* Transfer buffer and states */
+struct cec_tx {
+	/* Outgoing message */
+	struct cec_msg_transfer transfer;
+	/* Message length */
+	uint8_t len;
+	/* Number of resends attempted in current send */
+	uint8_t resends;
+	/* Acknowledge received from sink? */
+	uint8_t ack;
+	/*
+	 * When sending multiple concurrent frames,
+	 * the free-time is slightly higher
+	 */
+	int present_initiator;
+};
+
+/* Single state for CEC. We are INITIATOR, FOLLOWER or IDLE */
+static enum cec_state cec_state;
+
+/* Parameters and buffers for follower (receiver) state */
+static struct cec_rx cec_rx;
+
+/* Parameters and buffer for initiator (sender) state */
+static struct cec_tx cec_tx;
+
+/*
+ * CEC address of ourself. We ack incoming packages on this address.
+ * However, the AP is responsible for writing the initiator address
+ * on writes. UINT32_MAX means means that the address hasn't been
+ * set by the AP yet.
+ */
+static uint8_t cec_addr = UINT8_MAX;
+
+static void enter_state(enum cec_state new_state)
+{
+	int gpio = -1, timeout = -1;
+	enum cec_cap_edge cap_edge = CEC_CAP_EDGE_NONE;
+	uint8_t addr;
+
+	cec_state = new_state;
+	switch (new_state) {
+	case CEC_STATE_DISABLED:
+		gpio = 1;
+		memset(&cec_rx, 0, sizeof(struct cec_rx));
+		memset(&cec_tx, 0, sizeof(struct cec_tx));
+		break;
+	case CEC_STATE_IDLE:
+		cec_tx.transfer.bit = 0;
+		cec_tx.transfer.byte = 0;
+		cec_rx.transfer.bit = 0;
+		cec_rx.transfer.byte = 0;
+		if (cec_tx.len > 0) {
+			/* Execute a postponed send */
+			enter_state(CEC_STATE_INITIATOR_FREE_TIME);
+		} else {
+			/* Wait for incoming command */
+			gpio = 1;
+			cap_edge = CEC_CAP_EDGE_FALLING;
+			timeout = 0;
+		}
+		break;
+	case CEC_STATE_INITIATOR_FREE_TIME:
+		gpio = 1;
+		cap_edge = CEC_CAP_EDGE_FALLING;
+		if (cec_tx.resends)
+			timeout = FREE_TIME_RS_TICKS;
+		else if (cec_tx.present_initiator)
+			timeout = FREE_TIME_PI_TICKS;
+		else
+			timeout = FREE_TIME_NI_TICKS;
+		break;
+	case CEC_STATE_INITIATOR_START_LOW:
+		cec_tx.present_initiator = 1;
+		cec_tx.transfer.bit = 0;
+		cec_tx.transfer.byte = 0;
+		gpio = 0;
+		timeout = START_BIT_LOW_TICKS;
+		break;
+	case CEC_STATE_INITIATOR_START_HIGH:
+		gpio = 1;
+		cap_edge = CEC_CAP_EDGE_FALLING;
+		timeout = START_BIT_HIGH_TICKS;
+		break;
+	case CEC_STATE_INITIATOR_HEADER_INIT_LOW:
+	case CEC_STATE_INITIATOR_HEADER_DEST_LOW:
+	case CEC_STATE_INITIATOR_DATA_LOW:
+		gpio = 0;
+		timeout = DATA_LOW(cec_transfer_get_bit(&cec_tx.transfer));
+		break;
+	case CEC_STATE_INITIATOR_HEADER_INIT_HIGH:
+		gpio = 1;
+		cap_edge = CEC_CAP_EDGE_FALLING;
+		timeout = DATA_HIGH(cec_transfer_get_bit(&cec_tx.transfer));
+		break;
+	case CEC_STATE_INITIATOR_HEADER_DEST_HIGH:
+	case CEC_STATE_INITIATOR_DATA_HIGH:
+		gpio = 1;
+		timeout = DATA_HIGH(cec_transfer_get_bit(&cec_tx.transfer));
+		break;
+	case CEC_STATE_INITIATOR_EOM_LOW:
+		gpio = 0;
+		timeout = DATA_LOW(
+			cec_transfer_is_eom(&cec_tx.transfer, cec_tx.len));
+		break;
+	case CEC_STATE_INITIATOR_EOM_HIGH:
+		gpio = 1;
+		timeout = DATA_HIGH(
+			cec_transfer_is_eom(&cec_tx.transfer, cec_tx.len));
+		break;
+	case CEC_STATE_INITIATOR_ACK_LOW:
+		gpio = 0;
+		timeout = DATA_LOW(1);
+		break;
+	case CEC_STATE_INITIATOR_ACK_HIGH:
+		gpio = 1;
+		/* Aim for the middle of the safe sample time */
+		timeout = (DATA_ONE_LOW_TICKS + DATA_ZERO_LOW_TICKS) / 2 -
+			  DATA_ONE_LOW_TICKS;
+		break;
+	case CEC_STATE_INITIATOR_ACK_VERIFY:
+		cec_tx.ack = !gpio_get_level(CEC_GPIO_OUT);
+		if ((cec_tx.transfer.buf[0] & 0x0f) == CEC_BROADCAST_ADDR) {
+			/*
+			 * We are sending a broadcast. Any follower can
+			 * can NAK a broadcast message the same way they
+			 * would ACK a direct message
+			 */
+			cec_tx.ack = !cec_tx.ack;
+		}
+		/*
+		 * We are at the safe sample time. Wait
+		 * until the end of this bit
+		 */
+		timeout = NOMINAL_BIT_TICKS - NOMINAL_SAMPLE_TIME_TICKS;
+		break;
+	case CEC_STATE_FOLLOWER_START_LOW:
+		cec_tx.present_initiator = 0;
+		cap_edge = CEC_CAP_EDGE_RISING;
+		timeout = CAP_START_LOW_TICKS;
+		break;
+	case CEC_STATE_FOLLOWER_START_HIGH:
+		cec_rx.debounce_count = 0;
+		cap_edge = CEC_CAP_EDGE_FALLING;
+		timeout = CAP_START_HIGH_TICKS;
+		break;
+	case CEC_STATE_FOLLOWER_DEBOUNCE:
+		if (cec_rx.debounce_count >= DEBOUNCE_CUTOFF) {
+			timeout = DEBOUNCE_WAIT_LONG_TICKS;
+		} else {
+			timeout = DEBOUNCE_WAIT_SHORT_TICKS;
+			cec_rx.debounce_count++;
+		}
+		break;
+	case CEC_STATE_FOLLOWER_HEADER_INIT_LOW:
+	case CEC_STATE_FOLLOWER_HEADER_DEST_LOW:
+	case CEC_STATE_FOLLOWER_EOM_LOW:
+		cap_edge = CEC_CAP_EDGE_RISING;
+		timeout = CAP_DATA_LOW_TICKS;
+		break;
+	case CEC_STATE_FOLLOWER_HEADER_INIT_HIGH:
+	case CEC_STATE_FOLLOWER_HEADER_DEST_HIGH:
+	case CEC_STATE_FOLLOWER_EOM_HIGH:
+		cap_edge = CEC_CAP_EDGE_FALLING;
+		timeout = CAP_DATA_HIGH_TICKS;
+		break;
+	case CEC_STATE_FOLLOWER_ACK_LOW:
+		addr = cec_rx.transfer.buf[0] & 0x0f;
+		if (addr == cec_addr) {
+			/* Destination is our address, so ACK the packet */
+			gpio = 0;
+		}
+		/* Don't ack broadcast or packets whose destinations aren't us,
+		 * but continue reading.
+		 */
+		timeout = NOMINAL_SAMPLE_TIME_TICKS;
+		break;
+	case CEC_STATE_FOLLOWER_ACK_VERIFY:
+		/*
+		 * We are at safe sample time. A broadcast frame is considered
+		 * lost if any follower pulls the line low
+		 */
+		if ((cec_rx.transfer.buf[0] & 0x0f) == CEC_BROADCAST_ADDR)
+			cec_rx.broadcast_nak = !gpio_get_level(CEC_GPIO_OUT);
+		else
+			cec_rx.broadcast_nak = 0;
+
+		/*
+		 * We release the ACK at the end of data zero low
+		 * period (ACK is technically a zero).
+		 */
+		timeout = DATA_ZERO_LOW_TICKS - NOMINAL_SAMPLE_TIME_TICKS;
+		break;
+	case CEC_STATE_FOLLOWER_ACK_FINISH:
+		gpio = 1;
+		if (cec_rx.eom || cec_rx.transfer.byte >= MAX_CEC_MSG_LEN) {
+			addr = cec_rx.transfer.buf[0] & 0x0f;
+			if (addr == cec_addr || addr == CEC_BROADCAST_ADDR) {
+				task_set_event(TASK_ID_CEC,
+					       CEC_TASK_EVENT_RECEIVED_DATA);
+			}
+			timeout = DATA_ZERO_HIGH_TICKS;
+		} else {
+			cap_edge = CEC_CAP_EDGE_FALLING;
+			timeout = CAP_DATA_HIGH_TICKS;
+		}
+		break;
+	case CEC_STATE_FOLLOWER_DATA_LOW:
+		cap_edge = CEC_CAP_EDGE_RISING;
+		timeout = CAP_DATA_LOW_TICKS;
+		break;
+	case CEC_STATE_FOLLOWER_DATA_HIGH:
+		cap_edge = CEC_CAP_EDGE_FALLING;
+		timeout = CAP_DATA_HIGH_TICKS;
+		break;
+		/* No default case, since all states must be handled explicitly
+		 */
+	}
+
+	if (gpio >= 0)
+		gpio_set_level(CEC_GPIO_OUT, gpio);
+	if (timeout >= 0) {
+		cec_tmr_cap_start(cap_edge, timeout);
+	}
+}
+
+void cec_event_timeout(void)
+{
+	switch (cec_state) {
+	case CEC_STATE_DISABLED:
+	case CEC_STATE_IDLE:
+		break;
+	case CEC_STATE_INITIATOR_FREE_TIME:
+		enter_state(CEC_STATE_INITIATOR_START_LOW);
+		break;
+	case CEC_STATE_INITIATOR_START_LOW:
+		enter_state(CEC_STATE_INITIATOR_START_HIGH);
+		break;
+	case CEC_STATE_INITIATOR_START_HIGH:
+		enter_state(CEC_STATE_INITIATOR_HEADER_INIT_LOW);
+		break;
+	case CEC_STATE_INITIATOR_HEADER_INIT_LOW:
+		enter_state(CEC_STATE_INITIATOR_HEADER_INIT_HIGH);
+		break;
+	case CEC_STATE_INITIATOR_HEADER_INIT_HIGH:
+		cec_transfer_inc_bit(&cec_tx.transfer);
+		if (cec_tx.transfer.bit == 4)
+			enter_state(CEC_STATE_INITIATOR_HEADER_DEST_LOW);
+		else
+			enter_state(CEC_STATE_INITIATOR_HEADER_INIT_LOW);
+		break;
+	case CEC_STATE_INITIATOR_HEADER_DEST_LOW:
+		enter_state(CEC_STATE_INITIATOR_HEADER_DEST_HIGH);
+		break;
+	case CEC_STATE_INITIATOR_HEADER_DEST_HIGH:
+		cec_transfer_inc_bit(&cec_tx.transfer);
+		if (cec_tx.transfer.byte == 1)
+			enter_state(CEC_STATE_INITIATOR_EOM_LOW);
+		else
+			enter_state(CEC_STATE_INITIATOR_HEADER_DEST_LOW);
+		break;
+	case CEC_STATE_INITIATOR_EOM_LOW:
+		enter_state(CEC_STATE_INITIATOR_EOM_HIGH);
+		break;
+	case CEC_STATE_INITIATOR_EOM_HIGH:
+		enter_state(CEC_STATE_INITIATOR_ACK_LOW);
+		break;
+	case CEC_STATE_INITIATOR_ACK_LOW:
+		enter_state(CEC_STATE_INITIATOR_ACK_HIGH);
+		break;
+	case CEC_STATE_INITIATOR_ACK_HIGH:
+		enter_state(CEC_STATE_INITIATOR_ACK_VERIFY);
+		break;
+	case CEC_STATE_INITIATOR_ACK_VERIFY:
+		if (cec_tx.ack) {
+			if (!cec_transfer_is_eom(&cec_tx.transfer,
+						 cec_tx.len)) {
+				/* More data in this frame */
+				enter_state(CEC_STATE_INITIATOR_DATA_LOW);
+			} else {
+				/* Transfer completed successfully */
+				cec_tx.len = 0;
+				cec_tx.resends = 0;
+				enter_state(CEC_STATE_IDLE);
+				task_set_event(TASK_ID_CEC,
+					       CEC_TASK_EVENT_OKAY);
+			}
+		} else {
+			if (cec_tx.resends < CEC_MAX_RESENDS) {
+				/* Resend */
+				cec_tx.resends++;
+				enter_state(CEC_STATE_INITIATOR_FREE_TIME);
+			} else {
+				/* Transfer failed */
+				cec_tx.len = 0;
+				cec_tx.resends = 0;
+				enter_state(CEC_STATE_IDLE);
+				task_set_event(TASK_ID_CEC,
+					       CEC_TASK_EVENT_FAILED);
+			}
+		}
+		break;
+	case CEC_STATE_INITIATOR_DATA_LOW:
+		enter_state(CEC_STATE_INITIATOR_DATA_HIGH);
+		break;
+	case CEC_STATE_INITIATOR_DATA_HIGH:
+		cec_transfer_inc_bit(&cec_tx.transfer);
+		if (cec_tx.transfer.bit == 0)
+			enter_state(CEC_STATE_INITIATOR_EOM_LOW);
+		else
+			enter_state(CEC_STATE_INITIATOR_DATA_LOW);
+		break;
+	case CEC_STATE_FOLLOWER_ACK_LOW:
+		enter_state(CEC_STATE_FOLLOWER_ACK_VERIFY);
+		break;
+	case CEC_STATE_FOLLOWER_ACK_VERIFY:
+		if (cec_rx.broadcast_nak)
+			enter_state(CEC_STATE_IDLE);
+		else
+			enter_state(CEC_STATE_FOLLOWER_ACK_FINISH);
+		break;
+	case CEC_STATE_FOLLOWER_START_LOW:
+	case CEC_STATE_FOLLOWER_START_HIGH:
+	case CEC_STATE_FOLLOWER_DEBOUNCE:
+	case CEC_STATE_FOLLOWER_HEADER_INIT_LOW:
+	case CEC_STATE_FOLLOWER_HEADER_INIT_HIGH:
+	case CEC_STATE_FOLLOWER_HEADER_DEST_LOW:
+	case CEC_STATE_FOLLOWER_HEADER_DEST_HIGH:
+	case CEC_STATE_FOLLOWER_EOM_LOW:
+	case CEC_STATE_FOLLOWER_EOM_HIGH:
+	case CEC_STATE_FOLLOWER_ACK_FINISH:
+	case CEC_STATE_FOLLOWER_DATA_LOW:
+	case CEC_STATE_FOLLOWER_DATA_HIGH:
+		enter_state(CEC_STATE_IDLE);
+		break;
+	}
+}
+
+void cec_event_cap(void)
+{
+	int t;
+	int data;
+
+	switch (cec_state) {
+	case CEC_STATE_IDLE:
+		/* A falling edge during idle, likely a start bit */
+		enter_state(CEC_STATE_FOLLOWER_START_LOW);
+		break;
+	case CEC_STATE_INITIATOR_FREE_TIME:
+	case CEC_STATE_INITIATOR_START_HIGH:
+	case CEC_STATE_INITIATOR_HEADER_INIT_HIGH:
+		/*
+		 * A falling edge during free-time, postpone
+		 * this send and listen
+		 */
+		cec_tx.transfer.bit = 0;
+		cec_tx.transfer.byte = 0;
+		enter_state(CEC_STATE_FOLLOWER_START_LOW);
+		break;
+	case CEC_STATE_FOLLOWER_START_LOW:
+		/* Rising edge of start bit, validate low time */
+		t = cec_tmr_cap_get();
+		if (VALID_LOW(START_BIT, t)) {
+			cec_rx.low_ticks = t;
+			enter_state(CEC_STATE_FOLLOWER_START_HIGH);
+		} else if (t < DEBOUNCE_LIMIT_TICKS) {
+			/* Wait a bit if start-pulses are really short */
+			enter_state(CEC_STATE_FOLLOWER_DEBOUNCE);
+		} else {
+			enter_state(CEC_STATE_IDLE);
+		}
+		break;
+	case CEC_STATE_FOLLOWER_START_HIGH:
+		if (VALID_HIGH(START_BIT, cec_rx.low_ticks, cec_tmr_cap_get()))
+			enter_state(CEC_STATE_FOLLOWER_HEADER_INIT_LOW);
+		else
+			enter_state(CEC_STATE_IDLE);
+		break;
+	case CEC_STATE_FOLLOWER_HEADER_INIT_LOW:
+	case CEC_STATE_FOLLOWER_HEADER_DEST_LOW:
+	case CEC_STATE_FOLLOWER_DATA_LOW:
+		t = cec_tmr_cap_get();
+		if (VALID_LOW(DATA_ZERO, t)) {
+			cec_rx.low_ticks = t;
+			cec_transfer_set_bit(&cec_rx.transfer, 0);
+			enter_state(cec_state + 1);
+		} else if (VALID_LOW(DATA_ONE, t)) {
+			cec_rx.low_ticks = t;
+			cec_transfer_set_bit(&cec_rx.transfer, 1);
+			enter_state(cec_state + 1);
+		} else {
+			enter_state(CEC_STATE_IDLE);
+		}
+		break;
+	case CEC_STATE_FOLLOWER_HEADER_INIT_HIGH:
+		t = cec_tmr_cap_get();
+		data = cec_transfer_get_bit(&cec_rx.transfer);
+		if (VALID_DATA_HIGH(data, cec_rx.low_ticks, t)) {
+			cec_transfer_inc_bit(&cec_rx.transfer);
+			if (cec_rx.transfer.bit == 4)
+				enter_state(CEC_STATE_FOLLOWER_HEADER_DEST_LOW);
+			else
+				enter_state(CEC_STATE_FOLLOWER_HEADER_INIT_LOW);
+		} else {
+			enter_state(CEC_STATE_IDLE);
+		}
+		break;
+	case CEC_STATE_FOLLOWER_HEADER_DEST_HIGH:
+		t = cec_tmr_cap_get();
+		data = cec_transfer_get_bit(&cec_rx.transfer);
+		if (VALID_DATA_HIGH(data, cec_rx.low_ticks, t)) {
+			cec_transfer_inc_bit(&cec_rx.transfer);
+			if (cec_rx.transfer.bit == 0)
+				enter_state(CEC_STATE_FOLLOWER_EOM_LOW);
+			else
+				enter_state(CEC_STATE_FOLLOWER_HEADER_DEST_LOW);
+		} else {
+			enter_state(CEC_STATE_IDLE);
+		}
+		break;
+	case CEC_STATE_FOLLOWER_EOM_LOW:
+		t = cec_tmr_cap_get();
+		if (VALID_LOW(DATA_ZERO, t)) {
+			cec_rx.low_ticks = t;
+			cec_rx.eom = 0;
+			enter_state(CEC_STATE_FOLLOWER_EOM_HIGH);
+		} else if (VALID_LOW(DATA_ONE, t)) {
+			cec_rx.low_ticks = t;
+			cec_rx.eom = 1;
+			enter_state(CEC_STATE_FOLLOWER_EOM_HIGH);
+		} else {
+			enter_state(CEC_STATE_IDLE);
+		}
+		break;
+	case CEC_STATE_FOLLOWER_EOM_HIGH:
+		t = cec_tmr_cap_get();
+		data = cec_rx.eom;
+		if (VALID_DATA_HIGH(data, cec_rx.low_ticks, t))
+			enter_state(CEC_STATE_FOLLOWER_ACK_LOW);
+		else
+			enter_state(CEC_STATE_IDLE);
+		break;
+	case CEC_STATE_FOLLOWER_ACK_LOW:
+		enter_state(CEC_STATE_FOLLOWER_ACK_FINISH);
+		break;
+	case CEC_STATE_FOLLOWER_ACK_FINISH:
+		enter_state(CEC_STATE_FOLLOWER_DATA_LOW);
+		break;
+	case CEC_STATE_FOLLOWER_DATA_HIGH:
+		t = cec_tmr_cap_get();
+		data = cec_transfer_get_bit(&cec_rx.transfer);
+		if (VALID_DATA_HIGH(data, cec_rx.low_ticks, t)) {
+			cec_transfer_inc_bit(&cec_rx.transfer);
+			if (cec_rx.transfer.bit == 0)
+				enter_state(CEC_STATE_FOLLOWER_EOM_LOW);
+			else
+				enter_state(CEC_STATE_FOLLOWER_DATA_LOW);
+		} else {
+			enter_state(CEC_STATE_IDLE);
+		}
+		break;
+	default:
+		break;
+	}
+}
+
+void cec_event_tx(void)
+{
+	/*
+	 * If we have an ongoing receive, this transfer
+	 * will start when transitioning to IDLE
+	 */
+	if (cec_state == CEC_STATE_IDLE) {
+		/*
+		 * Only update the interrupt time if it's idle, otherwise it
+		 * will interfere with the timing of the current transfer.
+		 */
+		cec_update_interrupt_time();
+		enter_state(CEC_STATE_INITIATOR_FREE_TIME);
+	}
+}
+
+__overridable void cec_update_interrupt_time(void)
+{
+}
+
+static int bitbang_cec_init(int port)
+{
+	cec_init_timer();
+
+	/* If RO doesn't set it, RW needs to set it explicitly. */
+#ifdef CEC_GPIO_PULL_UP
+	gpio_set_level(CEC_GPIO_PULL_UP, 1);
+#endif
+
+	/* Ensure the CEC bus is not pulled low by default on startup. */
+	gpio_set_level(CEC_GPIO_OUT, 1);
+
+	return EC_SUCCESS;
+}
+
+static int bitbang_cec_get_enable(int port, uint8_t *enable)
+{
+	*enable = cec_state == CEC_STATE_DISABLED ? 0 : 1;
+
+	return EC_SUCCESS;
+}
+
+static int bitbang_cec_set_enable(int port, uint8_t enable)
+{
+	/* Enabling when already enabled? */
+	if (enable && cec_state != CEC_STATE_DISABLED)
+		return EC_SUCCESS;
+
+	/* Disabling when already disabled? */
+	if (!enable && cec_state == CEC_STATE_DISABLED)
+		return EC_SUCCESS;
+
+	if (enable) {
+		enter_state(CEC_STATE_IDLE);
+
+		cec_enable_timer();
+
+		CPRINTF("CEC enabled\n");
+	} else {
+		cec_disable_timer();
+
+		enter_state(CEC_STATE_DISABLED);
+
+		CPRINTF("CEC disabled\n");
+	}
+
+	return EC_SUCCESS;
+}
+
+static int bitbang_cec_get_logical_addr(int port, uint8_t *logical_addr)
+{
+	*logical_addr = cec_addr;
+
+	return EC_SUCCESS;
+}
+
+static int bitbang_cec_set_logical_addr(int port, uint8_t logical_addr)
+{
+	cec_addr = logical_addr;
+	CPRINTF("CEC address set to: %u\n", cec_addr);
+
+	return EC_SUCCESS;
+}
+
+static int bitbang_cec_send(int port, const uint8_t *msg, uint8_t len)
+{
+	int i;
+
+	if (cec_state == CEC_STATE_DISABLED)
+		return EC_ERROR_BUSY;
+
+	if (cec_tx.len != 0)
+		return EC_ERROR_BUSY;
+
+	cec_tx.len = len;
+
+	CPRINTS("Send CEC:");
+	for (i = 0; i < len && i < MAX_CEC_MSG_LEN; i++)
+		CPRINTS(" 0x%02x", msg[i]);
+
+	memcpy(cec_tx.transfer.buf, msg, len);
+
+	cec_trigger_send();
+
+	return EC_SUCCESS;
+}
+
+static int bitbang_cec_get_received_message(int port, uint8_t **msg,
+					    uint8_t *len)
+{
+	*msg = cec_rx.transfer.buf;
+	*len = cec_rx.transfer.byte;
+
+	return EC_SUCCESS;
+}
+
+const struct cec_drv bitbang_cec_drv = {
+	.init = &bitbang_cec_init,
+	.get_enable = &bitbang_cec_get_enable,
+	.set_enable = &bitbang_cec_set_enable,
+	.get_logical_addr = &bitbang_cec_get_logical_addr,
+	.set_logical_addr = &bitbang_cec_set_logical_addr,
+	.send = &bitbang_cec_send,
+	.get_received_message = &bitbang_cec_get_received_message,
+};
diff --git a/driver/cec/bitbang.h b/driver/cec/bitbang.h
new file mode 100644
index 0000000000..7f3fb93820
--- /dev/null
+++ b/driver/cec/bitbang.h
@@ -0,0 +1,87 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#ifndef __CROS_EC_DRIVER_CEC_BITBANG_H
+#define __CROS_EC_DRIVER_CEC_BITBANG_H
+
+/* Edge to trigger capture timer interrupt on */
+enum cec_cap_edge {
+	CEC_CAP_EDGE_NONE,
+	CEC_CAP_EDGE_FALLING,
+	CEC_CAP_EDGE_RISING
+};
+
+extern const struct cec_drv bitbang_cec_drv;
+
+/**
+ * Start the capture timer. An interrupt will be triggered when either a capture
+ * edge or a timeout occurs.
+ * If edge is NONE, disable the capture interrupt and wait for a timeout only.
+ * If timeout is 0, disable the timeout interrupt and wait for a capture event
+ * only.
+ *
+ * @param edge		Edge to trigger on
+ * @param timeout	Timeout to program into the capture timer
+ */
+void cec_tmr_cap_start(enum cec_cap_edge edge, int timeout);
+
+/**
+ * Stop the capture timer.
+ */
+void cec_tmr_cap_stop(void);
+
+/**
+ * Return the time measured by the capture timer.
+ */
+int cec_tmr_cap_get(void);
+
+/**
+ * ITE-specific callback to record the interrupt time.
+ */
+__override_proto void cec_update_interrupt_time(void);
+
+/**
+ * Called when a transfer is initiated from the host. Should trigger an
+ * interrupt which then calls cec_event_tx(). It must be called from interrupt
+ * context since the CEC state machine relies on the fact that the state is only
+ * modified from interrupt context for synchronisation.
+ */
+void cec_trigger_send(void);
+
+/**
+ * Enable timers used for CEC.
+ */
+void cec_enable_timer(void);
+
+/**
+ * Disable timers used for CEC.
+ */
+void cec_disable_timer(void);
+
+/**
+ * Initialise timers used for CEC.
+ */
+void cec_init_timer(void);
+
+/**
+ * Event for timeout.
+ */
+void cec_event_timeout(void);
+
+/**
+ * Event for capture edge.
+ */
+void cec_event_cap(void);
+
+/**
+ * Event for transfer from host.
+ */
+void cec_event_tx(void);
+
+/**
+ * Interrupt handler for rising and falling edges on the CEC line.
+ */
+void cec_gpio_interrupt(enum gpio_signal signal);
+
+#endif /* __CROS_EC_DRIVER_CEC_BITBANG_H */
diff --git a/driver/charger/bd9995x.c b/driver/charger/bd9995x.c
index 2531d4225d..f8e426fdc3 100644
--- a/driver/charger/bd9995x.c
+++ b/driver/charger/bd9995x.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -15,13 +15,14 @@
 #include "ec_commands.h"
 #include "hooks.h"
 #include "i2c.h"
+#include "panic.h"
 #include "task.h"
 #include "time.h"
-#include "util.h"
 #include "usb_charge.h"
 #include "usb_pd.h"
+#include "util.h"
 
-#define OTPROM_LOAD_WAIT_RETRY	3
+#define OTPROM_LOAD_WAIT_RETRY 3
 
 #define BD9995X_CHARGE_PORT_COUNT 2
 
@@ -29,11 +30,11 @@
  * BC1.2 detection starts 100ms after VBUS/VCC attach and typically
  * completes 312ms after VBUS/VCC attach.
  */
-#define BC12_DETECT_US (312*MSEC)
+#define BC12_DETECT_US (312 * MSEC)
 #define BD9995X_VSYS_PRECHARGE_OFFSET_MV 200
 
 /* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 #ifdef CONFIG_BD9995X_DELAY_INPUT_PORT_SELECT
 /*
@@ -44,18 +45,18 @@
 #define VBUS_DELTA 1000
 
 /* VBUS is debounced if it's stable for this length of time */
-#define VBUS_MSEC (100*MSEC)
+#define VBUS_MSEC (100 * MSEC)
 
 /* VBUS debouncing sample interval */
-#define VBUS_CHECK_MSEC (10*MSEC)
+#define VBUS_CHECK_MSEC (10 * MSEC)
 
 /* Time to wait before VBUS debouncing begins */
-#define STABLE_TIMEOUT (500*MSEC)
+#define STABLE_TIMEOUT (500 * MSEC)
 
 /* Maximum time to wait until VBUS is debounced */
-#define DEBOUNCE_TIMEOUT (500*MSEC)
+#define DEBOUNCE_TIMEOUT (500 * MSEC)
 
-enum vstate {START, STABLE, DEBOUNCE};
+enum vstate { START, STABLE, DEBOUNCE };
 static enum vstate vbus_state;
 
 static int vbus_voltage;
@@ -66,17 +67,30 @@ static int select_update;
 static int select_input_port_update;
 #endif
 
+/* Charger parameters */
+#define CHARGER_NAME BD9995X_CHARGER_NAME
+#define CHARGE_V_MAX 19200
+#define CHARGE_V_MIN 3072
+#define CHARGE_V_STEP 16
+#define CHARGE_I_MAX 16320
+#define CHARGE_I_MIN 128
+#define CHARGE_I_OFF 0
+#define CHARGE_I_STEP 64
+#define INPUT_I_MAX 16352
+#define INPUT_I_MIN 512
+#define INPUT_I_STEP 32
+
 /* Charger parameters */
 static const struct charger_info bd9995x_charger_info = {
-	.name         = CHARGER_NAME,
-	.voltage_max  = CHARGE_V_MAX,
-	.voltage_min  = CHARGE_V_MIN,
+	.name = CHARGER_NAME,
+	.voltage_max = CHARGE_V_MAX,
+	.voltage_min = CHARGE_V_MIN,
 	.voltage_step = CHARGE_V_STEP,
-	.current_max  = CHARGE_I_MAX,
-	.current_min  = CHARGE_I_MIN,
+	.current_max = CHARGE_I_MAX,
+	.current_min = CHARGE_I_MIN,
 	.current_step = CHARGE_I_STEP,
-	.input_current_max  = INPUT_I_MAX,
-	.input_current_min  = INPUT_I_MIN,
+	.input_current_max = INPUT_I_MAX,
+	.input_current_min = INPUT_I_MIN,
 	.input_current_step = INPUT_I_STEP,
 };
 
@@ -151,8 +165,7 @@ static inline enum ec_error_list ch_raw_read16(int chgnum, int cmd, int *param,
 	}
 
 	rv = i2c_read16(chg_chips[chgnum].i2c_port,
-			chg_chips[chgnum].i2c_addr_flags,
-			cmd, param);
+			chg_chips[chgnum].i2c_addr_flags, cmd, param);
 
 bd9995x_read_cleanup:
 	mutex_unlock(&bd9995x_map_mutex);
@@ -180,8 +193,7 @@ static inline enum ec_error_list ch_raw_write16(int chgnum, int cmd, int param,
 	}
 
 	rv = i2c_write16(chg_chips[chgnum].i2c_port,
-			 chg_chips[chgnum].i2c_addr_flags,
-			 cmd, param);
+			 chg_chips[chgnum].i2c_addr_flags, cmd, param);
 
 bd9995x_write_cleanup:
 	mutex_unlock(&bd9995x_map_mutex);
@@ -193,12 +205,11 @@ static inline enum ec_error_list ch_raw_write16(int chgnum, int cmd, int param,
 
 static int bd9995x_set_vfastchg(int chgnum, int voltage)
 {
-
 	int rv;
 
 	/* Fast Charge Voltage Regulation Settings for fast charging. */
 	rv = ch_raw_write16(chgnum, BD9995X_CMD_VFASTCHG_REG_SET1,
-			voltage & 0x7FF0, BD9995X_EXTENDED_COMMAND);
+			    voltage & 0x7FF0, BD9995X_EXTENDED_COMMAND);
 	if (rv)
 		return rv;
 
@@ -208,12 +219,12 @@ static int bd9995x_set_vfastchg(int chgnum, int voltage)
 	 * to same voltage.
 	 */
 	rv = ch_raw_write16(chgnum, BD9995X_CMD_VFASTCHG_REG_SET2,
-			voltage & 0x7FF0, BD9995X_EXTENDED_COMMAND);
+			    voltage & 0x7FF0, BD9995X_EXTENDED_COMMAND);
 	if (rv)
 		return rv;
 
 	rv = ch_raw_write16(chgnum, BD9995X_CMD_VFASTCHG_REG_SET3,
-			voltage & 0x7FF0, BD9995X_EXTENDED_COMMAND);
+			    voltage & 0x7FF0, BD9995X_EXTENDED_COMMAND);
 #endif
 
 	return rv;
@@ -233,7 +244,7 @@ static int bd9995x_is_discharging_on_ac(int chgnum)
 	int reg;
 
 	if (ch_raw_read16(chgnum, BD9995X_CMD_CHGOP_SET2, &reg,
-				BD9995X_EXTENDED_COMMAND))
+			  BD9995X_EXTENDED_COMMAND))
 		return 0;
 
 	return !!(reg & BD9995X_CMD_CHGOP_SET2_BATT_LEARN);
@@ -279,8 +290,9 @@ static int bd9995x_charger_enable(int chgnum, int enable)
 		 * Set VSYSREG_SET > VBAT so that the charger is in Pre-Charge
 		 * state when not charging or discharging.
 		 */
-		rv = bd9995x_set_vsysreg(chgnum, bi->voltage_max +
-					 BD9995X_VSYS_PRECHARGE_OFFSET_MV);
+		rv = bd9995x_set_vsysreg(
+			chgnum,
+			bi->voltage_max + BD9995X_VSYS_PRECHARGE_OFFSET_MV);
 
 		/*
 		 * Allow charger in pre-charge state for 50ms before disabling
@@ -293,7 +305,7 @@ static int bd9995x_charger_enable(int chgnum, int enable)
 		return rv;
 
 	rv = ch_raw_read16(chgnum, BD9995X_CMD_CHGOP_SET2, &reg,
-				BD9995X_EXTENDED_COMMAND);
+			   BD9995X_EXTENDED_COMMAND);
 	if (rv)
 		return rv;
 
@@ -303,7 +315,7 @@ static int bd9995x_charger_enable(int chgnum, int enable)
 		reg &= ~BD9995X_CMD_CHGOP_SET2_CHG_EN;
 
 	return ch_raw_write16(chgnum, BD9995X_CMD_CHGOP_SET2, reg,
-				BD9995X_EXTENDED_COMMAND);
+			      BD9995X_EXTENDED_COMMAND);
 }
 
 static int bd9995x_por_reset(int chgnum)
@@ -313,9 +325,9 @@ static int bd9995x_por_reset(int chgnum)
 	int i;
 
 	rv = ch_raw_write16(chgnum, BD9995X_CMD_SYSTEM_CTRL_SET,
-			BD9995X_CMD_SYSTEM_CTRL_SET_OTPLD |
-			BD9995X_CMD_SYSTEM_CTRL_SET_ALLRST,
-			BD9995X_EXTENDED_COMMAND);
+			    BD9995X_CMD_SYSTEM_CTRL_SET_OTPLD |
+				    BD9995X_CMD_SYSTEM_CTRL_SET_ALLRST,
+			    BD9995X_EXTENDED_COMMAND);
 	if (rv)
 		return rv;
 
@@ -323,10 +335,10 @@ static int bd9995x_por_reset(int chgnum)
 	for (i = 0; i < OTPROM_LOAD_WAIT_RETRY; i++) {
 		msleep(10);
 		rv = ch_raw_read16(chgnum, BD9995X_CMD_SYSTEM_STATUS, &reg,
-				BD9995X_EXTENDED_COMMAND);
+				   BD9995X_EXTENDED_COMMAND);
 
 		if (!rv && (reg & BD9995X_CMD_SYSTEM_STATUS_OTPLD_STATE) &&
-			(reg & BD9995X_CMD_SYSTEM_STATUS_ALLRST_STATE))
+		    (reg & BD9995X_CMD_SYSTEM_STATUS_ALLRST_STATE))
 			break;
 	}
 
@@ -336,7 +348,7 @@ static int bd9995x_por_reset(int chgnum)
 		return EC_ERROR_TIMEOUT;
 
 	return ch_raw_write16(chgnum, BD9995X_CMD_SYSTEM_CTRL_SET, 0,
-				BD9995X_EXTENDED_COMMAND);
+			      BD9995X_EXTENDED_COMMAND);
 }
 
 static int bd9995x_reset_to_zero(int chgnum)
@@ -353,7 +365,7 @@ static int bd9995x_reset_to_zero(int chgnum)
 static int bd9995x_get_charger_op_status(int chgnum, int *status)
 {
 	return ch_raw_read16(chgnum, BD9995X_CMD_CHGOP_STATUS, status,
-				BD9995X_EXTENDED_COMMAND);
+			     BD9995X_EXTENDED_COMMAND);
 }
 
 #ifdef HAS_TASK_USB_CHG
@@ -366,10 +378,11 @@ static int bd9995x_get_bc12_device_type(int chgnum, int port)
 	int rv;
 	int reg;
 
-	rv = ch_raw_read16(chgnum, (port == BD9995X_CHARGE_PORT_VBUS) ?
-				BD9995X_CMD_VBUS_UCD_STATUS :
-				BD9995X_CMD_VCC_UCD_STATUS,
-				&reg, BD9995X_EXTENDED_COMMAND);
+	rv = ch_raw_read16(chgnum,
+			   (port == BD9995X_CHARGE_PORT_VBUS) ?
+				   BD9995X_CMD_VBUS_UCD_STATUS :
+				   BD9995X_CMD_VCC_UCD_STATUS,
+			   &reg, BD9995X_EXTENDED_COMMAND);
 	if (rv)
 		return CHARGE_SUPPLIER_NONE;
 
@@ -402,7 +415,8 @@ static int bd9995x_update_ucd_set_reg(int chgnum, int port, uint16_t mask,
 	int rv;
 	int reg;
 	int port_reg = (port == BD9995X_CHARGE_PORT_VBUS) ?
-		BD9995X_CMD_VBUS_UCD_SET : BD9995X_CMD_VCC_UCD_SET;
+			       BD9995X_CMD_VBUS_UCD_SET :
+			       BD9995X_CMD_VCC_UCD_SET;
 
 	mutex_lock(&ucd_set_mutex[port]);
 	rv = ch_raw_read16(chgnum, port_reg, &reg, BD9995X_EXTENDED_COMMAND);
@@ -471,32 +485,33 @@ static int bd9995x_enable_vbus_detect_interrupts(int chgnum, int port,
 
 	/* 1st Level Interrupt Setting */
 	rv = ch_raw_read16(chgnum, BD9995X_CMD_INT0_SET, &reg,
-			BD9995X_EXTENDED_COMMAND);
+			   BD9995X_EXTENDED_COMMAND);
 	if (rv)
 		return rv;
 
 	mask_val = ((port == BD9995X_CHARGE_PORT_VBUS) ?
-			BD9995X_CMD_INT0_SET_INT1_EN :
-			BD9995X_CMD_INT0_SET_INT2_EN) |
-			BD9995X_CMD_INT0_SET_INT0_EN;
+			    BD9995X_CMD_INT0_SET_INT1_EN :
+			    BD9995X_CMD_INT0_SET_INT2_EN) |
+		   BD9995X_CMD_INT0_SET_INT0_EN;
 	if (enable)
 		reg |= mask_val;
 	else
 		reg &= ~mask_val;
 
 	rv = ch_raw_write16(chgnum, BD9995X_CMD_INT0_SET, reg,
-			BD9995X_EXTENDED_COMMAND);
+			    BD9995X_EXTENDED_COMMAND);
 	if (rv)
 		return rv;
 
 	/* 2nd Level Interrupt Setting */
-	port_reg = (port == BD9995X_CHARGE_PORT_VBUS) ?
-			BD9995X_CMD_INT1_SET : BD9995X_CMD_INT2_SET;
+	port_reg = (port == BD9995X_CHARGE_PORT_VBUS) ? BD9995X_CMD_INT1_SET :
+							BD9995X_CMD_INT2_SET;
 	rv = ch_raw_read16(chgnum, port_reg, &reg, BD9995X_EXTENDED_COMMAND);
 	if (rv)
 		return rv;
 
-	/* Enable threshold interrupts if we need to control discharge */
+		/* Enable threshold interrupts if we need to control discharge
+		 */
 #ifdef CONFIG_USB_PD_DISCHARGE
 	mask_val = BD9995X_CMD_INT_VBUS_DET | BD9995X_CMD_INT_VBUS_TH;
 #else
@@ -518,7 +533,8 @@ static int bd9995x_get_interrupts(int chgnum, int port)
 	int port_reg;
 
 	port_reg = (port == BD9995X_CHARGE_PORT_VBUS) ?
-			BD9995X_CMD_INT1_STATUS : BD9995X_CMD_INT2_STATUS;
+			   BD9995X_CMD_INT1_STATUS :
+			   BD9995X_CMD_INT2_STATUS;
 
 	rv = ch_raw_read16(chgnum, port_reg, &reg, BD9995X_EXTENDED_COMMAND);
 
@@ -540,8 +556,8 @@ static int bd9995x_bc12_detect(int chgnum, int port, int enable)
 {
 	return bd9995x_update_ucd_set_reg(chgnum, port,
 					  BD9995X_CMD_UCD_SET_BCSRETRY |
-					  BD9995X_CMD_UCD_SET_USBDETEN |
-					  BD9995X_CMD_UCD_SET_USB_SW_EN,
+						  BD9995X_CMD_UCD_SET_USBDETEN |
+						  BD9995X_CMD_UCD_SET_USB_SW_EN,
 					  enable);
 }
 
@@ -601,8 +617,8 @@ static int bd9995x_ramp_max(int supplier, int sup_curr)
 
 /* chip specific interfaces */
 
-static enum ec_error_list bd9995x_set_input_current(int chgnum,
-						    int input_current)
+static enum ec_error_list bd9995x_set_input_current_limit(int chgnum,
+							  int input_current)
 {
 	int rv;
 
@@ -613,16 +629,16 @@ static enum ec_error_list bd9995x_set_input_current(int chgnum,
 		input_current = bd9995x_charger_info.input_current_min;
 
 	rv = ch_raw_write16(chgnum, BD9995X_CMD_IBUS_LIM_SET, input_current,
-				BD9995X_BAT_CHG_COMMAND);
+			    BD9995X_BAT_CHG_COMMAND);
 	if (rv)
 		return rv;
 
 	return ch_raw_write16(chgnum, BD9995X_CMD_ICC_LIM_SET, input_current,
-				BD9995X_BAT_CHG_COMMAND);
+			      BD9995X_BAT_CHG_COMMAND);
 }
 
-static enum ec_error_list bd9995x_get_input_current(int chgnum,
-						    int *input_current)
+static enum ec_error_list bd9995x_get_input_current_limit(int chgnum,
+							  int *input_current)
 {
 	return ch_raw_read16(chgnum, BD9995X_CMD_CUR_ILIM_VAL, input_current,
 			     BD9995X_EXTENDED_COMMAND);
@@ -645,12 +661,12 @@ static enum ec_error_list bd9995x_get_option(int chgnum, int *option)
 	int reg;
 
 	rv = ch_raw_read16(chgnum, BD9995X_CMD_CHGOP_SET1, option,
-				BD9995X_EXTENDED_COMMAND);
+			   BD9995X_EXTENDED_COMMAND);
 	if (rv)
 		return rv;
 
 	rv = ch_raw_read16(chgnum, BD9995X_CMD_CHGOP_SET2, &reg,
-				BD9995X_EXTENDED_COMMAND);
+			   BD9995X_EXTENDED_COMMAND);
 	if (rv)
 		return rv;
 
@@ -664,7 +680,7 @@ static enum ec_error_list bd9995x_set_option(int chgnum, int option)
 	int rv;
 
 	rv = ch_raw_write16(chgnum, BD9995X_CMD_CHGOP_SET1, option & 0xFFFF,
-				BD9995X_EXTENDED_COMMAND);
+			    BD9995X_EXTENDED_COMMAND);
 	if (rv)
 		return rv;
 
@@ -691,7 +707,7 @@ static enum ec_error_list bd9995x_get_status(int chgnum, int *status)
 
 	/* charger enable/inhibit */
 	rv = ch_raw_read16(chgnum, BD9995X_CMD_CHGOP_SET2, &reg,
-				BD9995X_EXTENDED_COMMAND);
+			   BD9995X_EXTENDED_COMMAND);
 	if (rv)
 		return rv;
 
@@ -700,15 +716,15 @@ static enum ec_error_list bd9995x_get_status(int chgnum, int *status)
 
 	/* charger alarm enable/inhibit */
 	rv = ch_raw_read16(chgnum, BD9995X_CMD_PROCHOT_CTRL_SET, &reg,
-				BD9995X_EXTENDED_COMMAND);
+			   BD9995X_EXTENDED_COMMAND);
 	if (rv)
 		return rv;
 
 	if (!(reg & (BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN4 |
-			BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN3 |
-			BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN2 |
-			BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN1 |
-			BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN0)))
+		     BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN3 |
+		     BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN2 |
+		     BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN1 |
+		     BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN0)))
 		*status |= CHARGER_ALARM_INHIBITED;
 
 	rv = bd9995x_get_charger_op_status(chgnum, &reg);
@@ -742,6 +758,7 @@ static enum ec_error_list bd9995x_get_status(int chgnum, int *status)
 		break;
 	case BD9995X_CMD_CHGOP_STATUS_BATTEMP_BATOPEN:
 		*status &= ~CHARGER_BATTERY_PRESENT;
+		break;
 	default:
 		break;
 	}
@@ -775,7 +792,7 @@ static enum ec_error_list bd9995x_set_mode(int chgnum, int mode)
 static enum ec_error_list bd9995x_get_current(int chgnum, int *current)
 {
 	return ch_raw_read16(chgnum, BD9995X_CMD_CHG_CURRENT, current,
-				BD9995X_BAT_CHG_COMMAND);
+			     BD9995X_BAT_CHG_COMMAND);
 }
 
 static enum ec_error_list bd9995x_set_current(int chgnum, int current)
@@ -811,7 +828,7 @@ static enum ec_error_list bd9995x_set_current(int chgnum, int current)
 		return rv;
 
 	rv = ch_raw_write16(chgnum, BD9995X_CMD_CHG_CURRENT, current,
-			      BD9995X_BAT_CHG_COMMAND);
+			    BD9995X_BAT_CHG_COMMAND);
 	if (rv)
 		return rv;
 
@@ -856,7 +873,7 @@ static enum ec_error_list bd9995x_get_voltage(int chgnum, int *voltage)
 	}
 
 	return ch_raw_read16(chgnum, BD9995X_CMD_CHG_VOLTAGE, voltage,
-				BD9995X_BAT_CHG_COMMAND);
+			     BD9995X_BAT_CHG_COMMAND);
 }
 
 static enum ec_error_list bd9995x_set_voltage(int chgnum, int voltage)
@@ -867,11 +884,9 @@ static enum ec_error_list bd9995x_set_voltage(int chgnum, int voltage)
 	 * Regulate the system voltage to battery max if the battery
 	 * is not present or the battery is discharging on AC.
 	 */
-	if (voltage == 0 ||
-		bd9995x_is_discharging_on_ac(chgnum) ||
-		battery_is_present() != BP_YES ||
-		battery_is_cut_off() ||
-		voltage > battery_voltage_max)
+	if (voltage == 0 || bd9995x_is_discharging_on_ac(chgnum) ||
+	    battery_is_present() != BP_YES || battery_is_cut_off() ||
+	    voltage > battery_voltage_max)
 		voltage = battery_voltage_max;
 
 	/* Charge voltage step 16 mV */
@@ -889,7 +904,8 @@ static void bd9995x_battery_charging_profile_settings(int chgnum)
 	const struct battery_info *bi = battery_get_info();
 
 	/* Input Current Limit Setting */
-	bd9995x_set_input_current(chgnum, CONFIG_CHARGER_INPUT_CURRENT);
+	bd9995x_set_input_current_limit(chgnum,
+					CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT);
 
 	/* Charge Termination Current Setting */
 	ch_raw_write16(chgnum, BD9995X_CMD_ITERM_SET, 0,
@@ -908,8 +924,7 @@ static void bd9995x_battery_charging_profile_settings(int chgnum)
 		       BD9995X_EXTENDED_COMMAND);
 
 	/* Re-charge Battery Voltage Setting */
-	ch_raw_write16(chgnum, BD9995X_CMD_VRECHG_SET,
-		       bi->voltage_max & 0x7FF0,
+	ch_raw_write16(chgnum, BD9995X_CMD_VRECHG_SET, bi->voltage_max & 0x7FF0,
 		       BD9995X_EXTENDED_COMMAND);
 
 	/* Set battery OVP to 500 + maximum battery voltage */
@@ -959,8 +974,9 @@ static void bd9995x_init(void)
 	 * that the charger is in Pre-Charge state and that the input current
 	 * disable setting below will be active.
 	 */
-	bd9995x_set_vsysreg(CHARGER_SOLO, battery_get_info()->voltage_max +
-			    BD9995X_VSYS_PRECHARGE_OFFSET_MV);
+	bd9995x_set_vsysreg(CHARGER_SOLO,
+			    battery_get_info()->voltage_max +
+				    BD9995X_VSYS_PRECHARGE_OFFSET_MV);
 
 	/* Enable BC1.2 USB charging and DC/DC converter @ 1200KHz */
 	if (ch_raw_read16(CHARGER_SOLO, BD9995X_CMD_CHGOP_SET2, &reg,
@@ -989,10 +1005,10 @@ static void bd9995x_init(void)
 	 * Disable the input current limit when VBAT is < VSYSREG_SET. This
 	 * needs to be done before calling
 	 * bd9995x_battery_charging_profile_settings() as in that function the
-	 * input current limit is set to CONFIG_CHARGER_INPUT_CURRENT which is
-	 * 512 mA. In deeply discharged battery cases, setting the input current
-	 * limit this low can cause VSYS to collapse, which in turn can cause
-	 * the EC's brownout detector to reset the EC.
+	 * input current limit is set to CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT
+	 * which is 512 mA. In deeply discharged battery cases, setting the
+	 * input current limit this low can cause VSYS to collapse, which in
+	 * turn can cause the EC's brownout detector to reset the EC.
 	 */
 	if (ch_raw_read16(CHARGER_SOLO, BD9995X_CMD_VIN_CTRL_SET, &reg,
 			  BD9995X_EXTENDED_COMMAND))
@@ -1047,7 +1063,7 @@ static enum ec_error_list bd9995x_discharge_on_ac(int chgnum, int enable)
 	int reg;
 
 	rv = ch_raw_read16(chgnum, BD9995X_CMD_CHGOP_SET2, &reg,
-				BD9995X_EXTENDED_COMMAND);
+			   BD9995X_EXTENDED_COMMAND);
 	if (rv)
 		return rv;
 
@@ -1059,13 +1075,13 @@ static enum ec_error_list bd9995x_discharge_on_ac(int chgnum, int enable)
 	 */
 	if (enable)
 		reg |= BD9995X_CMD_CHGOP_SET2_BATT_LEARN |
-			BD9995X_CMD_CHGOP_SET2_USB_SUS;
+		       BD9995X_CMD_CHGOP_SET2_USB_SUS;
 	else
 		reg &= ~(BD9995X_CMD_CHGOP_SET2_BATT_LEARN |
-			BD9995X_CMD_CHGOP_SET2_USB_SUS);
+			 BD9995X_CMD_CHGOP_SET2_USB_SUS);
 
 	return ch_raw_write16(chgnum, BD9995X_CMD_CHGOP_SET2, reg,
-				BD9995X_EXTENDED_COMMAND);
+			      BD9995X_EXTENDED_COMMAND);
 }
 
 static enum ec_error_list bd9995x_get_vbus_voltage(int chgnum, int port,
@@ -1130,7 +1146,7 @@ int bd9995x_select_input_port(enum bd9995x_charge_port port, int select)
 		} else if (port == BD9995X_CHARGE_PORT_BOTH) {
 			/* Enable both the ports for PG3 */
 			reg |= BD9995X_CMD_VIN_CTRL_SET_VBUS_EN |
-				BD9995X_CMD_VIN_CTRL_SET_VCC_EN;
+			       BD9995X_CMD_VIN_CTRL_SET_VCC_EN;
 		} else {
 			/* Invalid charge port */
 			panic("Invalid charge port");
@@ -1148,7 +1164,7 @@ int bd9995x_select_input_port(enum bd9995x_charge_port port, int select)
 	}
 
 	rv = ch_raw_write16(CHARGER_SOLO, BD9995X_CMD_VIN_CTRL_SET, reg,
-			      BD9995X_EXTENDED_COMMAND);
+			    BD9995X_EXTENDED_COMMAND);
 select_input_port_exit:
 	mutex_unlock(&bd9995x_vin_mutex);
 	return rv;
@@ -1179,8 +1195,8 @@ static int bd9995x_vbus_debounce(int chgnum, enum bd9995x_charge_port port)
 	int vbus_reg;
 	int voltage;
 
-	vbus_reg = (port == BD9995X_CHARGE_PORT_VBUS) ?
-		BD9995X_CMD_VBUS_VAL : BD9995X_CMD_VCC_VAL;
+	vbus_reg = (port == BD9995X_CHARGE_PORT_VBUS) ? BD9995X_CMD_VBUS_VAL :
+							BD9995X_CMD_VCC_VAL;
 	if (ch_raw_read16(chgnum, vbus_reg, &voltage, BD9995X_EXTENDED_COMMAND))
 		voltage = 0;
 
@@ -1196,14 +1212,13 @@ static int bd9995x_vbus_debounce(int chgnum, enum bd9995x_charge_port port)
 }
 #endif
 
-
 #ifdef CONFIG_CHARGER_BATTERY_TSENSE
 int bd9995x_get_battery_temp(int *temp_ptr)
 {
 	int rv;
 
 	rv = ch_raw_read16(CHARGER_SOLO, BD9995X_CMD_THERM_VAL, temp_ptr,
-			BD9995X_EXTENDED_COMMAND);
+			   BD9995X_EXTENDED_COMMAND);
 	if (rv)
 		return rv;
 
@@ -1224,7 +1239,7 @@ int bd9995x_get_battery_voltage(void)
 	int vbat_val, rv;
 
 	rv = ch_raw_read16(CHARGER_SOLO, BD9995X_CMD_VBAT_VAL, &vbat_val,
-			BD9995X_EXTENDED_COMMAND);
+			   BD9995X_EXTENDED_COMMAND);
 
 	return rv ? 0 : vbat_val;
 }
@@ -1242,15 +1257,15 @@ int bd9995x_bc12_enable_charging(int port, int enable)
 	 * for USB-C.
 	 */
 	rv = ch_raw_read16(CHARGER_SOLO, BD9995X_CMD_CHGOP_SET1, &reg,
-			BD9995X_EXTENDED_COMMAND);
+			   BD9995X_EXTENDED_COMMAND);
 	if (rv)
 		return rv;
 
 	mask_val = (BD9995X_CMD_CHGOP_SET1_SDP_CHG_TRIG_EN |
-		BD9995X_CMD_CHGOP_SET1_SDP_CHG_TRIG |
-		((port == BD9995X_CHARGE_PORT_VBUS) ?
-		BD9995X_CMD_CHGOP_SET1_VBUS_BC_DISEN :
-		BD9995X_CMD_CHGOP_SET1_VCC_BC_DISEN));
+		    BD9995X_CMD_CHGOP_SET1_SDP_CHG_TRIG |
+		    ((port == BD9995X_CHARGE_PORT_VBUS) ?
+			     BD9995X_CMD_CHGOP_SET1_VBUS_BC_DISEN :
+			     BD9995X_CMD_CHGOP_SET1_VCC_BC_DISEN));
 
 	if (enable)
 		reg &= ~mask_val;
@@ -1258,7 +1273,7 @@ int bd9995x_bc12_enable_charging(int port, int enable)
 		reg |= mask_val;
 
 	return ch_raw_write16(CHARGER_SOLO, BD9995X_CMD_CHGOP_SET1, reg,
-			BD9995X_EXTENDED_COMMAND);
+			      BD9995X_EXTENDED_COMMAND);
 }
 
 static void bd9995x_set_switches(int port, enum usb_switch setting)
@@ -1270,17 +1285,18 @@ static void bd9995x_set_switches(int port, enum usb_switch setting)
 	if (setting != USB_SWITCH_RESTORE)
 		usb_switch_state[port] = setting;
 
-	/* ensure we disable power saving when we are using DP/DN */
+		/* ensure we disable power saving when we are using DP/DN */
 #ifdef CONFIG_BD9995X_POWER_SAVE_MODE
 	bd9995x_set_power_save_mode(
 		(usb_switch_state[0] == USB_SWITCH_DISCONNECT &&
-		usb_switch_state[1] == USB_SWITCH_DISCONNECT)
-		? CONFIG_BD9995X_POWER_SAVE_MODE : BD9995X_PWR_SAVE_OFF);
+		 usb_switch_state[1] == USB_SWITCH_DISCONNECT) ?
+			CONFIG_BD9995X_POWER_SAVE_MODE :
+			BD9995X_PWR_SAVE_OFF);
 #endif
 
-	bd9995x_update_ucd_set_reg(CHARGER_SOLO, port,
-				   BD9995X_CMD_UCD_SET_USB_SW,
-				usb_switch_state[port] == USB_SWITCH_CONNECT);
+	bd9995x_update_ucd_set_reg(
+		CHARGER_SOLO, port, BD9995X_CMD_UCD_SET_USB_SW,
+		usb_switch_state[port] == USB_SWITCH_CONNECT);
 }
 
 void bd9995x_vbus_interrupt(enum gpio_signal signal)
@@ -1288,7 +1304,7 @@ void bd9995x_vbus_interrupt(enum gpio_signal signal)
 	task_wake(TASK_ID_USB_CHG);
 }
 
-static void bd9995x_usb_charger_task(const int unused)
+static void bd9995x_usb_charger_task_init(const int unused)
 {
 	static int initialized;
 	int changed, port, interrupts;
@@ -1324,8 +1340,11 @@ static void bd9995x_usb_charger_task(const int unused)
 				 * provided, then disable wait for this port.
 				 */
 				bc12_det_mark[port] =
-					usb_charger_process(CHARGER_SOLO, port)
-					? get_time().val + BC12_DETECT_US : 0;
+					usb_charger_process(CHARGER_SOLO,
+							    port) ?
+						get_time().val +
+							BC12_DETECT_US :
+						0;
 				changed = 1;
 			}
 #ifdef CONFIG_USB_PD_DISCHARGE
@@ -1333,21 +1352,22 @@ static void bd9995x_usb_charger_task(const int unused)
 			    !initialized) {
 				/* Get VBUS voltage */
 				vbus_reg = (port == BD9995X_CHARGE_PORT_VBUS) ?
-					   BD9995X_CMD_VBUS_VAL :
-					   BD9995X_CMD_VCC_VAL;
+						   BD9995X_CMD_VBUS_VAL :
+						   BD9995X_CMD_VCC_VAL;
 				if (ch_raw_read16(CHARGER_SOLO, vbus_reg,
 						  &voltage,
 						  BD9995X_EXTENDED_COMMAND))
 					voltage = 0;
 
 				/* Set discharge accordingly */
-				pd_set_vbus_discharge(port,
+				pd_set_vbus_discharge(
+					port,
 					voltage < BD9995X_VBUS_DISCHARGE_TH);
 				changed = 1;
 			}
 #endif
-			if (bc12_det_mark[port] && (get_time().val >
-						    bc12_det_mark[port])) {
+			if (bc12_det_mark[port] &&
+			    (get_time().val > bc12_det_mark[port])) {
 				/*
 				 * bc12_type result should be available. If not
 				 * available still, then function will return
@@ -1358,7 +1378,8 @@ static void bd9995x_usb_charger_task(const int unused)
 				bc12_det_mark[port] =
 					bd9995x_bc12_check_type(CHARGER_SOLO,
 								port) ?
-					get_time().val + 100 * MSEC : 0;
+						get_time().val + 100 * MSEC :
+						0;
 				/* Reset BC1.2 regs to skip auto-detection. */
 				bd9995x_bc12_detect(CHARGER_SOLO, port, 0);
 			}
@@ -1373,8 +1394,8 @@ static void bd9995x_usb_charger_task(const int unused)
 			if (bc12_det_mark[port]) {
 				int bc12_wait_usec;
 
-				bc12_wait_usec = bc12_det_mark[port]
-					- get_time().val;
+				bc12_wait_usec =
+					bc12_det_mark[port] - get_time().val;
 				if ((sleep_usec < 0) ||
 				    (sleep_usec > bc12_wait_usec))
 					sleep_usec = bc12_wait_usec;
@@ -1383,40 +1404,43 @@ static void bd9995x_usb_charger_task(const int unused)
 
 		initialized = 1;
 #ifdef CONFIG_BD9995X_DELAY_INPUT_PORT_SELECT
-/*
- * When a charge port is selected and VBUS is 5V, the inrush current on some
- * devices causes VBUS to droop, which could signal a sink disconnection.
- *
- * To mitigate the problem, charge port selection is delayed until VBUS
- * is stable or one second has passed. Hopefully PD has negotiated a VBUS
- * voltage of at least 9V before the one second timeout.
- */
-	if (select_input_port_update) {
-		sleep_usec = VBUS_CHECK_MSEC;
-		changed = 0;
-
-		switch (vbus_state) {
-		case START:
-			vbus_timeout = get_time().val + STABLE_TIMEOUT;
-			vbus_state = STABLE;
-			break;
-		case STABLE:
-			if (get_time().val > vbus_timeout) {
-				vbus_state = DEBOUNCE;
-				vbus_timeout = get_time().val +
-							DEBOUNCE_TIMEOUT;
-			}
-			break;
-		case DEBOUNCE:
-			if (bd9995x_vbus_debounce(CHARGER_SOLO, port_update) ||
-					get_time().val > vbus_timeout) {
-				select_input_port_update = 0;
-				bd9995x_select_input_port_private(
+		/*
+		 * When a charge port is selected and VBUS is 5V, the inrush
+		 * current on some devices causes VBUS to droop, which could
+		 * signal a sink disconnection.
+		 *
+		 * To mitigate the problem, charge port selection is delayed
+		 * until VBUS is stable or one second has passed. Hopefully PD
+		 * has negotiated a VBUS voltage of at least 9V before the one
+		 * second timeout.
+		 */
+		if (select_input_port_update) {
+			sleep_usec = VBUS_CHECK_MSEC;
+			changed = 0;
+
+			switch (vbus_state) {
+			case START:
+				vbus_timeout = get_time().val + STABLE_TIMEOUT;
+				vbus_state = STABLE;
+				break;
+			case STABLE:
+				if (get_time().val > vbus_timeout) {
+					vbus_state = DEBOUNCE;
+					vbus_timeout = get_time().val +
+						       DEBOUNCE_TIMEOUT;
+				}
+				break;
+			case DEBOUNCE:
+				if (bd9995x_vbus_debounce(CHARGER_SOLO,
+							  port_update) ||
+				    get_time().val > vbus_timeout) {
+					select_input_port_update = 0;
+					bd9995x_select_input_port_private(
 						port_update, select_update);
+				}
+				break;
 			}
-			break;
 		}
-	}
 #endif
 
 		/*
@@ -1432,7 +1456,6 @@ static void bd9995x_usb_charger_task(const int unused)
 }
 #endif /* HAS_TASK_USB_CHG */
 
-
 /*** Console commands ***/
 #ifdef CONFIG_CMD_CHARGER_DUMP
 static int read_bat(int chgnum, uint8_t cmd)
@@ -1452,31 +1475,26 @@ static int read_ext(int chgnum, uint8_t cmd)
 }
 
 /* Dump all readable registers on bd9995x */
-static int console_bd9995x_dump_regs(int argc, char **argv)
+static void console_bd9995x_dump_regs(int chgnum)
 {
 	int i;
 	uint8_t regs[] = { 0x14, 0x15, 0x3c, 0x3d, 0x3e, 0x3f };
 
 	/* Battery group registers */
 	for (i = 0; i < ARRAY_SIZE(regs); ++i)
-		ccprintf("BAT REG %4x:  %4x\n", regs[i], read_bat(CHARGER_SOLO,
-								  regs[i]));
+		ccprintf("BAT REG %4x:  %4x\n", regs[i],
+			 read_bat(CHARGER_SOLO, regs[i]));
 
 	/* Extended group registers */
 	for (i = 0; i < 0x7f; ++i) {
 		ccprintf("EXT REG %4x:  %4x\n", i, read_ext(CHARGER_SOLO, i));
 		cflush();
 	}
-
-	return 0;
 }
-DECLARE_CONSOLE_COMMAND(charger_dump, console_bd9995x_dump_regs,
-			NULL,
-			"Dump all charger registers");
 #endif /* CONFIG_CMD_CHARGER_DUMP */
 
 #ifdef CONFIG_CMD_CHARGER
-static int console_command_bd9995x(int argc, char **argv)
+static int console_command_bd9995x(int argc, const char **argv)
 {
 	int rv, reg, data, val;
 	char rw, *e;
@@ -1530,7 +1548,7 @@ static int bd9995x_psys_charger_adc(int chgnum)
 
 	for (i = 0; i < BD9995X_PMON_IOUT_ADC_READ_COUNT; i++) {
 		if (ch_raw_read16(chgnum, BD9995X_CMD_PMON_DACIN_VAL, &reg,
-				BD9995X_EXTENDED_COMMAND))
+				  BD9995X_EXTENDED_COMMAND))
 			return 0;
 
 		/* Conversion Interval is 200us */
@@ -1542,8 +1560,8 @@ static int bd9995x_psys_charger_adc(int chgnum)
 	 * Calculate power in mW
 	 * PSYS = VACP×IACP+VBAT×IBAT = IPMON / GPMON
 	 */
-	return (int) ((ipmon * 1000) / (BIT(BD9995X_PSYS_GAIN_SELECT) *
-		BD9995X_PMON_IOUT_ADC_READ_COUNT));
+	return (int)((ipmon * 1000) / (BIT(BD9995X_PSYS_GAIN_SELECT) *
+				       BD9995X_PMON_IOUT_ADC_READ_COUNT));
 }
 
 static int bd9995x_enable_psys(int chgnum)
@@ -1552,7 +1570,7 @@ static int bd9995x_enable_psys(int chgnum)
 	int reg;
 
 	rv = ch_raw_read16(chgnum, BD9995X_CMD_PMON_IOUT_CTRL_SET, &reg,
-			BD9995X_EXTENDED_COMMAND);
+			   BD9995X_EXTENDED_COMMAND);
 	if (rv)
 		return rv;
 
@@ -1563,7 +1581,7 @@ static int bd9995x_enable_psys(int chgnum)
 		BD9995X_PSYS_GAIN_SELECT);
 
 	return ch_raw_write16(chgnum, BD9995X_CMD_PMON_IOUT_CTRL_SET, reg,
-			BD9995X_EXTENDED_COMMAND);
+			      BD9995X_EXTENDED_COMMAND);
 }
 
 /**
@@ -1574,7 +1592,7 @@ static int bd9995x_enable_psys(int chgnum)
  * update "psys" console command to use charger_get_system_power and move it
  * to some common code.
  */
-static int console_command_psys(int argc, char **argv)
+static int console_command_psys(int argc, const char **argv)
 {
 	int rv;
 
@@ -1583,12 +1601,11 @@ static int console_command_psys(int argc, char **argv)
 		return rv;
 
 	CPRINTS("PSYS from chg_adc: %d mW",
-			bd9995x_psys_charger_adc(CHARGER_SOLO));
+		bd9995x_psys_charger_adc(CHARGER_SOLO));
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(psys, console_command_psys,
-			NULL,
+DECLARE_CONSOLE_COMMAND(psys, console_command_psys, NULL,
 			"Get the system power in mW");
 #endif /* CONFIG_CHARGER_PSYS_READ */
 
@@ -1601,7 +1618,7 @@ static int bd9995x_amon_bmon_chg_adc(int chgnum)
 
 	for (i = 0; i < BD9995X_PMON_IOUT_ADC_READ_COUNT; i++) {
 		ch_raw_read16(chgnum, BD9995X_CMD_IOUT_DACIN_VAL, &reg,
-				BD9995X_EXTENDED_COMMAND);
+			      BD9995X_EXTENDED_COMMAND);
 		iout += reg;
 
 		/* Conversion Interval is 200us */
@@ -1617,7 +1634,7 @@ static int bd9995x_amon_bmon_chg_adc(int chgnum)
 	 * VIADP = GIADP * (VACP- VACN) = GIADP * IADP / IADP_RES
 	 */
 	return (iout * (5 << BD9995X_IOUT_GAIN_SELECT)) /
-		(10 * BD9995X_PMON_IOUT_ADC_READ_COUNT);
+	       (10 * BD9995X_PMON_IOUT_ADC_READ_COUNT);
 }
 
 static int bd9995x_amon_bmon(int chgnum, int amon_bmon)
@@ -1628,7 +1645,7 @@ static int bd9995x_amon_bmon(int chgnum, int amon_bmon)
 	int sns_res;
 
 	rv = ch_raw_read16(chgnum, BD9995X_CMD_PMON_IOUT_CTRL_SET, &reg,
-			BD9995X_EXTENDED_COMMAND);
+			   BD9995X_EXTENDED_COMMAND);
 	if (rv)
 		return rv;
 
@@ -1647,16 +1664,14 @@ static int bd9995x_amon_bmon(int chgnum, int amon_bmon)
 	}
 
 	rv = ch_raw_write16(chgnum, BD9995X_CMD_PMON_IOUT_CTRL_SET, reg,
-			BD9995X_EXTENDED_COMMAND);
+			    BD9995X_EXTENDED_COMMAND);
 	if (rv)
 		return rv;
 
 	imon = bd9995x_amon_bmon_chg_adc(chgnum);
 
-	CPRINTS("%cMON from chg_adc: %d uV, %d mA]",
-		amon_bmon ? 'A' : 'B',
-		imon * sns_res,
-		imon);
+	CPRINTS("%cMON from chg_adc: %d uV, %d mA]", amon_bmon ? 'A' : 'B',
+		imon * sns_res, imon);
 
 	return EC_SUCCESS;
 }
@@ -1664,7 +1679,7 @@ static int bd9995x_amon_bmon(int chgnum, int amon_bmon)
 /**
  * Get charger AMON and BMON current.
  */
-static int console_command_amon_bmon(int argc, char **argv)
+static int console_command_amon_bmon(int argc, const char **argv)
 {
 	int rv = EC_ERROR_PARAM1;
 
@@ -1678,8 +1693,7 @@ static int console_command_amon_bmon(int argc, char **argv)
 
 	return rv;
 }
-DECLARE_CONSOLE_COMMAND(amonbmon, console_command_amon_bmon,
-			"amonbmon [a|b]",
+DECLARE_CONSOLE_COMMAND(amonbmon, console_command_amon_bmon, "amonbmon [a|b]",
 			"Get charger AMON/BMON voltage diff, current");
 #endif /* CONFIG_CMD_CHARGER_ADC_AMON_BMON */
 
@@ -1718,37 +1732,47 @@ const struct charger_drv bd9995x_drv = {
 	.set_voltage = &bd9995x_set_voltage,
 	.discharge_on_ac = &bd9995x_discharge_on_ac,
 	.get_vbus_voltage = &bd9995x_get_vbus_voltage,
-	.set_input_current = &bd9995x_set_input_current,
-	.get_input_current = &bd9995x_get_input_current,
+	.set_input_current_limit = &bd9995x_set_input_current_limit,
+	.get_input_current_limit = &bd9995x_get_input_current_limit,
 	.manufacturer_id = &bd9995x_manufacturer_id,
 	.device_id = &bd9995x_device_id,
 	.get_option = &bd9995x_get_option,
 	.set_option = &bd9995x_set_option,
+#ifdef CONFIG_CMD_CHARGER_DUMP
+	.dump_registers = &console_bd9995x_dump_regs,
+#endif
 };
 
 #ifdef CONFIG_BC12_SINGLE_DRIVER
 /* provide a default bc12_ports[] for backward compatibility */
 struct bc12_config bc12_ports[BD9995X_CHARGE_PORT_COUNT] = {
 	{
-		.drv = &(const struct bc12_drv) {
-			.usb_charger_task = bd9995x_usb_charger_task,
-			.set_switches = bd9995x_set_switches,
+		.drv =
+			&(const struct bc12_drv){
+				.usb_charger_task_init =
+					bd9995x_usb_charger_task_init,
+				/* events handled in init */
+				.usb_charger_task_event = NULL,
+				.set_switches = bd9995x_set_switches,
 #if defined(CONFIG_CHARGE_RAMP_SW)
-			.ramp_allowed = bd9995x_ramp_allowed,
-			.ramp_max = bd9995x_ramp_max,
+				.ramp_allowed = bd9995x_ramp_allowed,
+				.ramp_max = bd9995x_ramp_max,
 #endif /* CONFIG_CHARGE_RAMP_SW */
-		},
+			},
 	},
 	{
-		.drv = &(const struct bc12_drv) {
-			/* bd9995x uses a single task thread for both ports */
-			.usb_charger_task = NULL,
-			.set_switches = bd9995x_set_switches,
+		.drv =
+			&(const struct bc12_drv){
+				/* bd9995x uses a single task thread for both
+				   ports */
+				.usb_charger_task_init = NULL,
+				.usb_charger_task_event = NULL,
+				.set_switches = bd9995x_set_switches,
 #if defined(CONFIG_CHARGE_RAMP_SW)
-			.ramp_allowed = bd9995x_ramp_allowed,
-			.ramp_max = bd9995x_ramp_max,
+				.ramp_allowed = bd9995x_ramp_allowed,
+				.ramp_max = bd9995x_ramp_max,
 #endif /* CONFIG_CHARGE_RAMP_SW */
-		},
+			},
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(bc12_ports) == CHARGE_PORT_COUNT);
diff --git a/driver/charger/bd9995x.h b/driver/charger/bd9995x.h
index 5d346eb969..f50712ead0 100644
--- a/driver/charger/bd9995x.h
+++ b/driver/charger/bd9995x.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,11 +8,11 @@
 #ifndef __CROS_EC_BD9995X_H
 #define __CROS_EC_BD9995X_H
 
-#define BD9995X_ADDR_FLAGS	0x09
+#define BD9995X_ADDR_FLAGS 0x09
 
-#define BD9995X_CHARGER_NAME	"bd9995x"
-#define BD99955_CHIP_ID		0x221
-#define BD99956_CHIP_ID		0x331
+#define BD9995X_CHARGER_NAME "bd9995x"
+#define BD99955_CHIP_ID 0x221
+#define BD99956_CHIP_ID 0x331
 
 /* BD9995X commands to change the command code map */
 enum bd9995x_command {
@@ -34,21 +34,8 @@ enum bd9995x_charge_port {
 	BD9995X_CHARGE_PORT_BOTH,
 };
 
-/* Charger parameters */
-#define CHARGER_NAME	BD9995X_CHARGER_NAME
-#define CHARGE_V_MAX	19200
-#define CHARGE_V_MIN	3072
-#define CHARGE_V_STEP	16
-#define CHARGE_I_MAX	16320
-#define CHARGE_I_MIN	128
-#define CHARGE_I_OFF	0
-#define CHARGE_I_STEP	64
-#define INPUT_I_MAX	16352
-#define INPUT_I_MIN	512
-#define INPUT_I_STEP	32
-
 /* Min. charge current w/ no battery to prevent collapse */
-#define BD9995X_NO_BATTERY_CHARGE_I_MIN	512
+#define BD9995X_NO_BATTERY_CHARGE_I_MIN 512
 
 /*
  * BC1.2 minimum voltage threshold.
@@ -56,285 +43,283 @@ enum bd9995x_charge_port {
  * BD9995X Anti-Collapse Threshold Voltage Accuracy is -100mV to +100mV,
  * and Delta of 50mV.
  */
-#define BD9995X_BC12_MIN_VOLTAGE	4600
+#define BD9995X_BC12_MIN_VOLTAGE 4600
 
 /* Battery Charger Commands */
-#define BD9995X_CMD_CHG_CURRENT		0x14
-#define BD9995X_CMD_CHG_VOLTAGE		0x15
-#define BD9995X_CMD_IBUS_LIM_SET	0x3C
-#define BD9995X_CMD_ICC_LIM_SET		0x3D
-#define BD9995X_CMD_PROTECT_SET		0x3E
-#define BD9995X_CMD_MAP_SET		0x3F
+#define BD9995X_CMD_CHG_CURRENT 0x14
+#define BD9995X_CMD_CHG_VOLTAGE 0x15
+#define BD9995X_CMD_IBUS_LIM_SET 0x3C
+#define BD9995X_CMD_ICC_LIM_SET 0x3D
+#define BD9995X_CMD_PROTECT_SET 0x3E
+#define BD9995X_CMD_MAP_SET 0x3F
 
 /* Extended commands */
-#define BD9995X_CMD_CHGSTM_STATUS	0x00
-#define BD9995X_CMD_VBAT_VSYS_STATUS	0x01
-#define BD9995X_CMD_VBUS_VCC_STATUS	0x02
-#define BD9995X_CMD_VBUS_VCC_STATUS_VCC_DETECT  BIT(8)
+#define BD9995X_CMD_CHGSTM_STATUS 0x00
+#define BD9995X_CMD_VBAT_VSYS_STATUS 0x01
+#define BD9995X_CMD_VBUS_VCC_STATUS 0x02
+#define BD9995X_CMD_VBUS_VCC_STATUS_VCC_DETECT BIT(8)
 #define BD9995X_CMD_VBUS_VCC_STATUS_VBUS_DETECT BIT(0)
 
-#define BD9995X_CMD_CHGOP_STATUS	0x03
-#define BD9995X_CMD_CHGOP_STATUS_BATTEMP2	BIT(10)
-#define BD9995X_CMD_CHGOP_STATUS_BATTEMP1	BIT(9)
-#define BD9995X_CMD_CHGOP_STATUS_BATTEMP0	BIT(8)
-#define BD9995X_BATTTEMP_MASK			0x700
-#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_ROOMTEMP	0
-#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_HOT1		1
-#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_HOT2		2
-#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_HOT3		3
-#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_COLD1		4
-#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_COLD2		5
-#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_DISABLE	6
-#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_BATOPEN	7
-#define BD9995X_CMD_CHGOP_STATUS_RBOOST_UV	BIT(1)
-
-#define BD9995X_CMD_WDT_STATUS		0x04
-#define BD9995X_CMD_CUR_ILIM_VAL	0x05
-#define BD9995X_CMD_SEL_ILIM_VAL	0x06
-#define BD9995X_CMD_EXT_IBUS_LIM_SET	0x07
-#define BD9995X_CMD_EXT_ICC_LIM_SET	0x08
-#define BD9995X_CMD_IOTG_LIM_SET	0x09
-#define BD9995X_CMD_VIN_CTRL_SET	0x0A
-#define BD9995X_CMD_VIN_CTRL_SET_VSYS_PRIORITY	BIT(4)
-
-#define BD9995X_CMD_VIN_CTRL_SET_PP_BOTH_THRU  BIT(11)
+#define BD9995X_CMD_CHGOP_STATUS 0x03
+#define BD9995X_CMD_CHGOP_STATUS_BATTEMP2 BIT(10)
+#define BD9995X_CMD_CHGOP_STATUS_BATTEMP1 BIT(9)
+#define BD9995X_CMD_CHGOP_STATUS_BATTEMP0 BIT(8)
+#define BD9995X_BATTTEMP_MASK 0x700
+#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_ROOMTEMP 0
+#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_HOT1 1
+#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_HOT2 2
+#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_HOT3 3
+#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_COLD1 4
+#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_COLD2 5
+#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_DISABLE 6
+#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_BATOPEN 7
+#define BD9995X_CMD_CHGOP_STATUS_RBOOST_UV BIT(1)
+
+#define BD9995X_CMD_WDT_STATUS 0x04
+#define BD9995X_CMD_CUR_ILIM_VAL 0x05
+#define BD9995X_CMD_SEL_ILIM_VAL 0x06
+#define BD9995X_CMD_EXT_IBUS_LIM_SET 0x07
+#define BD9995X_CMD_EXT_ICC_LIM_SET 0x08
+#define BD9995X_CMD_IOTG_LIM_SET 0x09
+#define BD9995X_CMD_VIN_CTRL_SET 0x0A
+#define BD9995X_CMD_VIN_CTRL_SET_VSYS_PRIORITY BIT(4)
+
+#define BD9995X_CMD_VIN_CTRL_SET_PP_BOTH_THRU BIT(11)
 #define BD9995X_CMD_VIN_CTRL_SET_VBUS_PRIORITY BIT(7)
-#define BD9995X_CMD_VIN_CTRL_SET_VBUS_EN       BIT(6)
-#define BD9995X_CMD_VIN_CTRL_SET_VCC_EN        BIT(5)
+#define BD9995X_CMD_VIN_CTRL_SET_VBUS_EN BIT(6)
+#define BD9995X_CMD_VIN_CTRL_SET_VCC_EN BIT(5)
 
-#define BD9995X_CMD_CHGOP_SET1		0x0B
-#define BD9995X_CMD_CHGOP_SET1_DCP_2500_SEL    BIT(15)
-#define BD9995X_CMD_CHGOP_SET1_SDP_500_SEL     BIT(14)
+#define BD9995X_CMD_CHGOP_SET1 0x0B
+#define BD9995X_CMD_CHGOP_SET1_DCP_2500_SEL BIT(15)
+#define BD9995X_CMD_CHGOP_SET1_SDP_500_SEL BIT(14)
 #define BD9995X_CMD_CHGOP_SET1_ILIM_AUTO_DISEN BIT(13)
-#define BD9995X_CMD_CHGOP_SET1_VCC_BC_DISEN    BIT(11)
-#define BD9995X_CMD_CHGOP_SET1_VBUS_BC_DISEN   BIT(10)
+#define BD9995X_CMD_CHGOP_SET1_VCC_BC_DISEN BIT(11)
+#define BD9995X_CMD_CHGOP_SET1_VBUS_BC_DISEN BIT(10)
 #define BD9995X_CMD_CHGOP_SET1_SDP_CHG_TRIG_EN BIT(9)
-#define BD9995X_CMD_CHGOP_SET1_SDP_CHG_TRIG    BIT(8)
-
-#define BD9995X_CMD_CHGOP_SET2		0x0C
-#define BD9995X_CMD_CHGOP_SET2_BATT_LEARN	 BIT(8)
-#define BD9995X_CMD_CHGOP_SET2_CHG_EN		 BIT(7)
-#define BD9995X_CMD_CHGOP_SET2_USB_SUS		 BIT(6)
-#define BD9995X_CMD_CHGOP_SET2_DCDC_CLK_SEL      (3 << 2)
-#define BD9995X_CMD_CHGOP_SET2_DCDC_CLK_SEL_600  (0 << 2)
-#define BD9995X_CMD_CHGOP_SET2_DCDC_CLK_SEL_857  BIT(2)
+#define BD9995X_CMD_CHGOP_SET1_SDP_CHG_TRIG BIT(8)
+
+#define BD9995X_CMD_CHGOP_SET2 0x0C
+#define BD9995X_CMD_CHGOP_SET2_BATT_LEARN BIT(8)
+#define BD9995X_CMD_CHGOP_SET2_CHG_EN BIT(7)
+#define BD9995X_CMD_CHGOP_SET2_USB_SUS BIT(6)
+#define BD9995X_CMD_CHGOP_SET2_DCDC_CLK_SEL (3 << 2)
+#define BD9995X_CMD_CHGOP_SET2_DCDC_CLK_SEL_600 (0 << 2)
+#define BD9995X_CMD_CHGOP_SET2_DCDC_CLK_SEL_857 BIT(2)
 #define BD9995X_CMD_CHGOP_SET2_DCDC_CLK_SEL_1000 (2 << 2)
 #define BD9995X_CMD_CHGOP_SET2_DCDC_CLK_SEL_1200 (3 << 2)
 
-#define BD9995X_CMD_VBUSCLPS_TH_SET	0x0D
-#define BD9995X_CMD_VCCCLPS_TH_SET	0x0E
-#define BD9995X_CMD_CHGWDT_SET		0x0F
-#define BD9995X_CMD_BATTWDT_SET		0x10
-#define BD9995X_CMD_VSYSREG_SET		0x11
-#define BD9995X_CMD_VSYSVAL_THH_SET	0x12
-#define BD9995X_CMD_VSYSVAL_THL_SET	0x13
-#define BD9995X_CMD_ITRICH_SET		0x14
-
-#define BD9995X_CMD_IPRECH_SET		0x15
-#define BD9995X_IPRECH_MAX		1024
-
-#define BD9995X_CMD_ICHG_SET		0x16
-#define BD9995X_CMD_ITERM_SET		0x17
-#define BD9995X_CMD_VPRECHG_TH_SET	0x18
-#define BD9995X_CMD_VRBOOST_SET		0x19
-#define BD9995X_CMD_VFASTCHG_REG_SET1	0x1A
-#define BD9995X_CMD_VFASTCHG_REG_SET2	0x1B
-#define BD9995X_CMD_VFASTCHG_REG_SET3	0x1C
-#define BD9995X_CMD_VRECHG_SET		0x1D
-#define BD9995X_CMD_VBATOVP_SET		0x1E
-#define BD9995X_CMD_IBATSHORT_SET	0x1F
-#define BD9995X_CMD_PROCHOT_CTRL_SET	0x20
-#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN4	BIT(4)
-#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN3	BIT(3)
-#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN2	BIT(2)
-#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN1	BIT(1)
-#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN0	BIT(0)
-
-#define BD9995X_CMD_PROCHOT_ICRIT_SET	0x21
-#define BD9995X_CMD_PROCHOT_INORM_SET	0x22
-#define BD9995X_CMD_PROCHOT_IDCHG_SET	0x23
-#define BD9995X_CMD_PROCHOT_VSYS_SET	0x24
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET	0x25
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IMON_INSEL	BIT(9)
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_INSEL	BIT(8)
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_OUT_EN	BIT(7)
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_SOURCE_SEL	BIT(6)
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_MASK	0x30
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_40V	0x03
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V	0x02
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_10V	0x01
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_05V	0x00
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_OUT_EN	BIT(3)
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_MASK	0x07
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_64UAW	0x06
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_32UAW	0x05
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_16UAW	0x04
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_08UAW	0x03
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_04UAW	0x02
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_02UAW	0x01
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_01UAW	0x00
-#define BD9995X_PMON_IOUT_ADC_READ_COUNT	128
-
-#define BD9995X_CMD_PMON_DACIN_VAL	0x26
-#define BD9995X_CMD_IOUT_DACIN_VAL	0x27
-#define BD9995X_CMD_VCC_UCD_SET		0x28
+#define BD9995X_CMD_VBUSCLPS_TH_SET 0x0D
+#define BD9995X_CMD_VCCCLPS_TH_SET 0x0E
+#define BD9995X_CMD_CHGWDT_SET 0x0F
+#define BD9995X_CMD_BATTWDT_SET 0x10
+#define BD9995X_CMD_VSYSREG_SET 0x11
+#define BD9995X_CMD_VSYSVAL_THH_SET 0x12
+#define BD9995X_CMD_VSYSVAL_THL_SET 0x13
+#define BD9995X_CMD_ITRICH_SET 0x14
+
+#define BD9995X_CMD_IPRECH_SET 0x15
+#define BD9995X_IPRECH_MAX 1024
+
+#define BD9995X_CMD_ICHG_SET 0x16
+#define BD9995X_CMD_ITERM_SET 0x17
+#define BD9995X_CMD_VPRECHG_TH_SET 0x18
+#define BD9995X_CMD_VRBOOST_SET 0x19
+#define BD9995X_CMD_VFASTCHG_REG_SET1 0x1A
+#define BD9995X_CMD_VFASTCHG_REG_SET2 0x1B
+#define BD9995X_CMD_VFASTCHG_REG_SET3 0x1C
+#define BD9995X_CMD_VRECHG_SET 0x1D
+#define BD9995X_CMD_VBATOVP_SET 0x1E
+#define BD9995X_CMD_IBATSHORT_SET 0x1F
+#define BD9995X_CMD_PROCHOT_CTRL_SET 0x20
+#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN4 BIT(4)
+#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN3 BIT(3)
+#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN2 BIT(2)
+#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN1 BIT(1)
+#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN0 BIT(0)
+
+#define BD9995X_CMD_PROCHOT_ICRIT_SET 0x21
+#define BD9995X_CMD_PROCHOT_INORM_SET 0x22
+#define BD9995X_CMD_PROCHOT_IDCHG_SET 0x23
+#define BD9995X_CMD_PROCHOT_VSYS_SET 0x24
+#define BD9995X_CMD_PMON_IOUT_CTRL_SET 0x25
+#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IMON_INSEL BIT(9)
+#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_INSEL BIT(8)
+#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_OUT_EN BIT(7)
+#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_SOURCE_SEL BIT(6)
+#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_MASK 0x30
+#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_40V 0x03
+#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V 0x02
+#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_10V 0x01
+#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_05V 0x00
+#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_OUT_EN BIT(3)
+#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_MASK 0x07
+#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_64UAW 0x06
+#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_32UAW 0x05
+#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_16UAW 0x04
+#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_08UAW 0x03
+#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_04UAW 0x02
+#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_02UAW 0x01
+#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_01UAW 0x00
+#define BD9995X_PMON_IOUT_ADC_READ_COUNT 128
+
+#define BD9995X_CMD_PMON_DACIN_VAL 0x26
+#define BD9995X_CMD_IOUT_DACIN_VAL 0x27
+#define BD9995X_CMD_VCC_UCD_SET 0x28
 /* Bits for both VCC_UCD_SET and VBUS_UCD_SET regs */
 /*  Retry BC1.2 detection on set */
-#define BD9995X_CMD_UCD_SET_BCSRETRY	BIT(12)
+#define BD9995X_CMD_UCD_SET_BCSRETRY BIT(12)
 /* Enable BC1.2 detection, will automatically occur on VBUS detect */
-#define BD9995X_CMD_UCD_SET_USBDETEN	BIT(7)
+#define BD9995X_CMD_UCD_SET_USBDETEN BIT(7)
 /* USB switch state auto-control */
-#define BD9995X_CMD_UCD_SET_USB_SW_EN	BIT(1)
+#define BD9995X_CMD_UCD_SET_USB_SW_EN BIT(1)
 /* USB switch state, 1 = ON, only meaningful when USB_SW_EN = 0 */
-#define BD9995X_CMD_UCD_SET_USB_SW	BIT(0)
+#define BD9995X_CMD_UCD_SET_USB_SW BIT(0)
 
-#define BD9995X_CMD_VCC_UCD_STATUS	0x29
+#define BD9995X_CMD_VCC_UCD_STATUS 0x29
 /* Bits for both VCC_UCD_STATUS and VBUS_UCD_STATUS regs */
-#define BD9995X_CMD_UCD_STATUS_DCDFAIL	BIT(15)
-#define BD9995X_CMD_UCD_STATUS_CHGPORT1	BIT(13)
-#define BD9995X_CMD_UCD_STATUS_CHGPORT0	BIT(12)
-#define BD9995X_CMD_UCD_STATUS_PUPDET	BIT(11)
-#define BD9995X_CMD_UCD_STATUS_CHGDET	BIT(6)
-#define BD9995X_TYPE_MASK		(BD9995X_CMD_UCD_STATUS_DCDFAIL | \
-					 BD9995X_CMD_UCD_STATUS_CHGPORT1 | \
-					 BD9995X_CMD_UCD_STATUS_CHGPORT0 | \
-					 BD9995X_CMD_UCD_STATUS_PUPDET | \
-					 BD9995X_CMD_UCD_STATUS_CHGDET)
+#define BD9995X_CMD_UCD_STATUS_DCDFAIL BIT(15)
+#define BD9995X_CMD_UCD_STATUS_CHGPORT1 BIT(13)
+#define BD9995X_CMD_UCD_STATUS_CHGPORT0 BIT(12)
+#define BD9995X_CMD_UCD_STATUS_PUPDET BIT(11)
+#define BD9995X_CMD_UCD_STATUS_CHGDET BIT(6)
+#define BD9995X_TYPE_MASK                                                   \
+	(BD9995X_CMD_UCD_STATUS_DCDFAIL | BD9995X_CMD_UCD_STATUS_CHGPORT1 | \
+	 BD9995X_CMD_UCD_STATUS_CHGPORT0 | BD9995X_CMD_UCD_STATUS_PUPDET |  \
+	 BD9995X_CMD_UCD_STATUS_CHGDET)
 
 /* BC1.2 chargers */
-#define BD9995X_TYPE_CDP		(BD9995X_CMD_UCD_STATUS_CHGPORT1 | \
-					 BD9995X_CMD_UCD_STATUS_CHGDET)
-#define BD9995X_TYPE_DCP		(BD9995X_CMD_UCD_STATUS_CHGPORT1 | \
-					 BD9995X_CMD_UCD_STATUS_CHGPORT0 | \
-					 BD9995X_CMD_UCD_STATUS_CHGDET)
-#define BD9995X_TYPE_SDP		(BD9995X_CMD_UCD_STATUS_CHGPORT0)
+#define BD9995X_TYPE_CDP \
+	(BD9995X_CMD_UCD_STATUS_CHGPORT1 | BD9995X_CMD_UCD_STATUS_CHGDET)
+#define BD9995X_TYPE_DCP                                                     \
+	(BD9995X_CMD_UCD_STATUS_CHGPORT1 | BD9995X_CMD_UCD_STATUS_CHGPORT0 | \
+	 BD9995X_CMD_UCD_STATUS_CHGDET)
+#define BD9995X_TYPE_SDP (BD9995X_CMD_UCD_STATUS_CHGPORT0)
 /* non-standard BC1.2 chargers */
-#define BD9995X_TYPE_OTHER		(BD9995X_CMD_UCD_STATUS_DCDFAIL | \
-					 BD9995X_CMD_UCD_STATUS_CHGPORT1 | \
-					 BD9995X_CMD_UCD_STATUS_CHGPORT0 | \
-					 BD9995X_CMD_UCD_STATUS_CHGDET)
-#define BD9995X_TYPE_PUP_PORT		(BD9995X_CMD_UCD_STATUS_DCDFAIL | \
-					 BD9995X_CMD_UCD_STATUS_CHGPORT0 | \
-					 BD9995X_CMD_UCD_STATUS_PUPDET)
+#define BD9995X_TYPE_OTHER                                                  \
+	(BD9995X_CMD_UCD_STATUS_DCDFAIL | BD9995X_CMD_UCD_STATUS_CHGPORT1 | \
+	 BD9995X_CMD_UCD_STATUS_CHGPORT0 | BD9995X_CMD_UCD_STATUS_CHGDET)
+#define BD9995X_TYPE_PUP_PORT                                               \
+	(BD9995X_CMD_UCD_STATUS_DCDFAIL | BD9995X_CMD_UCD_STATUS_CHGPORT0 | \
+	 BD9995X_CMD_UCD_STATUS_PUPDET)
 /* Open ports */
-#define BD9995X_TYPE_OPEN_PORT		(BD9995X_CMD_UCD_STATUS_DCDFAIL | \
-					 BD9995X_CMD_UCD_STATUS_CHGPORT0)
-#define BD9995X_TYPE_VBUS_OPEN		0
-
-#define BD9995X_CMD_VCC_IDD_STATUS	0x2A
-#define BD9995X_CMD_VCC_UCD_FCTRL_SET	0x2B
-#define BD9995X_CMD_VCC_UCD_FCTRL_EN	0x2C
-#define BD9995X_CMD_VBUS_UCD_SET	0x30
-#define BD9995X_CMD_VBUS_UCD_STATUS	0x31
-#define BD9995X_CMD_VBUS_IDD_STATUS	0x32
-#define BD9995X_CMD_VBUS_UCD_FCTRL_SET	0x33
-#define BD9995X_CMD_VBUS_UCD_FCTRL_EN	0x34
-#define BD9995X_CMD_CHIP_ID		0x38
-#define BD9995X_CMD_CHIP_REV		0x39
-#define BD9995X_CMD_IC_SET1		0x3A
-#define BD9995X_CMD_IC_SET2		0x3B
-#define BD9995X_CMD_SYSTEM_STATUS	0x3C
-#define BD9995X_CMD_SYSTEM_STATUS_OTPLD_STATE	BIT(1)
-#define BD9995X_CMD_SYSTEM_STATUS_ALLRST_STATE	BIT(0)
-
-#define BD9995X_CMD_SYSTEM_CTRL_SET	0x3D
-#define BD9995X_CMD_SYSTEM_CTRL_SET_OTPLD	BIT(1)
-#define BD9995X_CMD_SYSTEM_CTRL_SET_ALLRST	BIT(0)
-
-#define BD9995X_CMD_EXT_PROTECT_SET	0x3E
-#define BD9995X_CMD_EXT_MAP_SET		0x3F
-#define BD9995X_CMD_VM_CTRL_SET		0x40
-#define BD9995X_CMD_VM_CTRL_SET_EXTIADPEN	BIT(9)
-#define BD9995X_CMD_THERM_WINDOW_SET1	0x41
-#define BD9995X_CMD_THERM_WINDOW_SET2	0x42
-#define BD9995X_CMD_THERM_WINDOW_SET3	0x43
-#define BD9995X_CMD_THERM_WINDOW_SET4	0x44
-#define BD9995X_CMD_THERM_WINDOW_SET5	0x45
-#define BD9995X_CMD_IBATP_TH_SET	0x46
-#define BD9995X_CMD_IBATM_TH_SET	0x47
-#define BD9995X_CMD_VBAT_TH_SET		0x48
-#define BD9995X_CMD_THERM_TH_SET	0x49
-#define BD9995X_CMD_IACP_TH_SET		0x4A
-#define BD9995X_CMD_VACP_TH_SET		0x4B
+#define BD9995X_TYPE_OPEN_PORT \
+	(BD9995X_CMD_UCD_STATUS_DCDFAIL | BD9995X_CMD_UCD_STATUS_CHGPORT0)
+#define BD9995X_TYPE_VBUS_OPEN 0
+
+#define BD9995X_CMD_VCC_IDD_STATUS 0x2A
+#define BD9995X_CMD_VCC_UCD_FCTRL_SET 0x2B
+#define BD9995X_CMD_VCC_UCD_FCTRL_EN 0x2C
+#define BD9995X_CMD_VBUS_UCD_SET 0x30
+#define BD9995X_CMD_VBUS_UCD_STATUS 0x31
+#define BD9995X_CMD_VBUS_IDD_STATUS 0x32
+#define BD9995X_CMD_VBUS_UCD_FCTRL_SET 0x33
+#define BD9995X_CMD_VBUS_UCD_FCTRL_EN 0x34
+#define BD9995X_CMD_CHIP_ID 0x38
+#define BD9995X_CMD_CHIP_REV 0x39
+#define BD9995X_CMD_IC_SET1 0x3A
+#define BD9995X_CMD_IC_SET2 0x3B
+#define BD9995X_CMD_SYSTEM_STATUS 0x3C
+#define BD9995X_CMD_SYSTEM_STATUS_OTPLD_STATE BIT(1)
+#define BD9995X_CMD_SYSTEM_STATUS_ALLRST_STATE BIT(0)
+
+#define BD9995X_CMD_SYSTEM_CTRL_SET 0x3D
+#define BD9995X_CMD_SYSTEM_CTRL_SET_OTPLD BIT(1)
+#define BD9995X_CMD_SYSTEM_CTRL_SET_ALLRST BIT(0)
+
+#define BD9995X_CMD_EXT_PROTECT_SET 0x3E
+#define BD9995X_CMD_EXT_MAP_SET 0x3F
+#define BD9995X_CMD_VM_CTRL_SET 0x40
+#define BD9995X_CMD_VM_CTRL_SET_EXTIADPEN BIT(9)
+#define BD9995X_CMD_THERM_WINDOW_SET1 0x41
+#define BD9995X_CMD_THERM_WINDOW_SET2 0x42
+#define BD9995X_CMD_THERM_WINDOW_SET3 0x43
+#define BD9995X_CMD_THERM_WINDOW_SET4 0x44
+#define BD9995X_CMD_THERM_WINDOW_SET5 0x45
+#define BD9995X_CMD_IBATP_TH_SET 0x46
+#define BD9995X_CMD_IBATM_TH_SET 0x47
+#define BD9995X_CMD_VBAT_TH_SET 0x48
+#define BD9995X_CMD_THERM_TH_SET 0x49
+#define BD9995X_CMD_IACP_TH_SET 0x4A
+#define BD9995X_CMD_VACP_TH_SET 0x4B
 
 /* Enable discharge when VBUS falls below BD9995X_VBUS_DISCHARGE_TH */
-#define BD9995X_VBUS_DISCHARGE_TH	3900
-#define BD9995X_CMD_VBUS_TH_SET		0x4C
-#define BD9995X_CMD_VCC_TH_SET		0x4D
-
-#define BD9995X_CMD_VSYS_TH_SET		0x4E
-#define BD9995X_CMD_EXTIADP_TH_SET	0x4F
-#define BD9995X_CMD_IBATP_VAL		0x50
-#define BD9995X_CMD_IBATP_AVE_VAL	0x51
-#define BD9995X_CMD_IBATM_VAL		0x52
-#define BD9995X_CMD_IBATM_AVE_VAL	0x53
-#define BD9995X_CMD_VBAT_VAL		0x54
-#define BD9995X_CMD_VBAT_AVE_VAL	0x55
-#define BD9995X_CMD_THERM_VAL		0x56
-#define BD9995X_CMD_VTH_VAL		0x57
-#define BD9995X_CMD_IACP_VAL		0x58
-#define BD9995X_CMD_IACP_AVE_VAL	0x59
-#define BD9995X_CMD_VACP_VAL		0x5A
-#define BD9995X_CMD_VACP_AVE_VAL	0x5B
-#define BD9995X_CMD_VBUS_VAL		0x5C
-#define BD9995X_CMD_VBUS_AVE_VAL	0x5D
-#define BD9995X_CMD_VCC_VAL		0x5E
-#define BD9995X_CMD_VCC_AVE_VAL		0x5F
-#define BD9995X_CMD_VSYS_VAL		0x60
-#define BD9995X_CMD_VSYS_AVE_VAL	0x61
-#define BD9995X_CMD_EXTIADP_VAL		0x62
-#define BD9995X_CMD_EXTIADP_AVE_VAL	0x63
-#define BD9995X_CMD_VACPCLPS_TH_SET	0x64
-#define BD9995X_CMD_INT0_SET		0x68
-#define BD9995X_CMD_INT0_SET_INT2_EN	BIT(2)
-#define BD9995X_CMD_INT0_SET_INT1_EN	BIT(1)
-#define BD9995X_CMD_INT0_SET_INT0_EN	BIT(0)
-
-#define BD9995X_CMD_INT1_SET		0x69
+#define BD9995X_VBUS_DISCHARGE_TH 3900
+#define BD9995X_CMD_VBUS_TH_SET 0x4C
+#define BD9995X_CMD_VCC_TH_SET 0x4D
+
+#define BD9995X_CMD_VSYS_TH_SET 0x4E
+#define BD9995X_CMD_EXTIADP_TH_SET 0x4F
+#define BD9995X_CMD_IBATP_VAL 0x50
+#define BD9995X_CMD_IBATP_AVE_VAL 0x51
+#define BD9995X_CMD_IBATM_VAL 0x52
+#define BD9995X_CMD_IBATM_AVE_VAL 0x53
+#define BD9995X_CMD_VBAT_VAL 0x54
+#define BD9995X_CMD_VBAT_AVE_VAL 0x55
+#define BD9995X_CMD_THERM_VAL 0x56
+#define BD9995X_CMD_VTH_VAL 0x57
+#define BD9995X_CMD_IACP_VAL 0x58
+#define BD9995X_CMD_IACP_AVE_VAL 0x59
+#define BD9995X_CMD_VACP_VAL 0x5A
+#define BD9995X_CMD_VACP_AVE_VAL 0x5B
+#define BD9995X_CMD_VBUS_VAL 0x5C
+#define BD9995X_CMD_VBUS_AVE_VAL 0x5D
+#define BD9995X_CMD_VCC_VAL 0x5E
+#define BD9995X_CMD_VCC_AVE_VAL 0x5F
+#define BD9995X_CMD_VSYS_VAL 0x60
+#define BD9995X_CMD_VSYS_AVE_VAL 0x61
+#define BD9995X_CMD_EXTIADP_VAL 0x62
+#define BD9995X_CMD_EXTIADP_AVE_VAL 0x63
+#define BD9995X_CMD_VACPCLPS_TH_SET 0x64
+#define BD9995X_CMD_INT0_SET 0x68
+#define BD9995X_CMD_INT0_SET_INT2_EN BIT(2)
+#define BD9995X_CMD_INT0_SET_INT1_EN BIT(1)
+#define BD9995X_CMD_INT0_SET_INT0_EN BIT(0)
+
+#define BD9995X_CMD_INT1_SET 0x69
 /* Bits for both INT1 & INT2 reg */
-#define BD9995X_CMD_INT_SET_TH_DET	BIT(9)
-#define BD9995X_CMD_INT_SET_TH_RES	BIT(8)
-#define BD9995X_CMD_INT_SET_DET		BIT(1)
-#define BD9995X_CMD_INT_SET_RES		BIT(0)
-#define BD9995X_CMD_INT_VBUS_DET	(BD9995X_CMD_INT_SET_RES | \
-					 BD9995X_CMD_INT_SET_DET)
-#define BD9995X_CMD_INT_VBUS_TH         (BD9995X_CMD_INT_SET_TH_RES | \
-					 BD9995X_CMD_INT_SET_TH_DET)
-
-#define BD9995X_CMD_INT2_SET		0x6A
-#define BD9995X_CMD_INT3_SET		0x6B
-#define BD9995X_CMD_INT4_SET		0x6C
-#define BD9995X_CMD_INT5_SET		0x6D
-#define BD9995X_CMD_INT6_SET		0x6E
-#define BD9995X_CMD_INT7_SET		0x6F
-#define BD9995X_CMD_INT0_STATUS		0x70
-#define BD9995X_CMD_INT1_STATUS		0x71
+#define BD9995X_CMD_INT_SET_TH_DET BIT(9)
+#define BD9995X_CMD_INT_SET_TH_RES BIT(8)
+#define BD9995X_CMD_INT_SET_DET BIT(1)
+#define BD9995X_CMD_INT_SET_RES BIT(0)
+#define BD9995X_CMD_INT_VBUS_DET \
+	(BD9995X_CMD_INT_SET_RES | BD9995X_CMD_INT_SET_DET)
+#define BD9995X_CMD_INT_VBUS_TH \
+	(BD9995X_CMD_INT_SET_TH_RES | BD9995X_CMD_INT_SET_TH_DET)
+
+#define BD9995X_CMD_INT2_SET 0x6A
+#define BD9995X_CMD_INT3_SET 0x6B
+#define BD9995X_CMD_INT4_SET 0x6C
+#define BD9995X_CMD_INT5_SET 0x6D
+#define BD9995X_CMD_INT6_SET 0x6E
+#define BD9995X_CMD_INT7_SET 0x6F
+#define BD9995X_CMD_INT0_STATUS 0x70
+#define BD9995X_CMD_INT1_STATUS 0x71
 /* Bits for both INT1_STATUS & INT2_STATUS reg */
-#define BD9995X_CMD_INT_STATUS_DET	BIT(1)
-#define BD9995X_CMD_INT_STATUS_RES	BIT(0)
-
-#define BD9995X_CMD_INT2_STATUS		0x72
-#define BD9995X_CMD_INT3_STATUS		0x73
-#define BD9995X_CMD_INT4_STATUS		0x74
-#define BD9995X_CMD_INT5_STATUS		0x75
-#define BD9995X_CMD_INT6_STATUS		0x76
-#define BD9995X_CMD_INT7_STATUS		0x77
-#define BD9995X_CMD_REG0		0x78
-#define BD9995X_CMD_REG1		0x79
-#define BD9995X_CMD_OTPREG0		0x7A
-#define BD9995X_CMD_OTPREG1		0x7B
-#define BD9995X_CMD_SMBREG		0x7C
+#define BD9995X_CMD_INT_STATUS_DET BIT(1)
+#define BD9995X_CMD_INT_STATUS_RES BIT(0)
+
+#define BD9995X_CMD_INT2_STATUS 0x72
+#define BD9995X_CMD_INT3_STATUS 0x73
+#define BD9995X_CMD_INT4_STATUS 0x74
+#define BD9995X_CMD_INT5_STATUS 0x75
+#define BD9995X_CMD_INT6_STATUS 0x76
+#define BD9995X_CMD_INT7_STATUS 0x77
+#define BD9995X_CMD_REG0 0x78
+#define BD9995X_CMD_REG1 0x79
+#define BD9995X_CMD_OTPREG0 0x7A
+#define BD9995X_CMD_OTPREG1 0x7B
+#define BD9995X_CMD_SMBREG 0x7C
 /* Normal functionality - power save mode disabled. */
-#define BD9995X_PWR_SAVE_OFF		0
+#define BD9995X_PWR_SAVE_OFF 0
 /* BGATE ON w/ PROCHOT# monitored only system voltage. */
-#define BD9995X_PWR_SAVE_LOW		0x1
+#define BD9995X_PWR_SAVE_LOW 0x1
 /* BGATE ON w/ PROCHOT# monitored only system voltage every 1ms. */
-#define BD9995X_PWR_SAVE_MED		0x2
+#define BD9995X_PWR_SAVE_MED 0x2
 /* BGATE ON w/o PROCHOT# monitoring. */
-#define BD9995X_PWR_SAVE_HIGH		0x5
+#define BD9995X_PWR_SAVE_HIGH 0x5
 /* BGATE OFF */
-#define BD9995X_PWR_SAVE_MAX		0x6
-#define BD9995X_CMD_DEBUG_MODE_SET	0x7F
+#define BD9995X_PWR_SAVE_MAX 0x6
+#define BD9995X_CMD_DEBUG_MODE_SET 0x7F
 
 /*
  * Non-standard interface functions - bd9995x integrates additional
diff --git a/driver/charger/bq24715.c b/driver/charger/bq24715.c
index 691d5f94fb..6855d6e334 100644
--- a/driver/charger/bq24715.c
+++ b/driver/charger/bq24715.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,56 +8,54 @@
 #include "battery_smart.h"
 #include "bq24715.h"
 #include "charger.h"
-#include "console.h"
 #include "common.h"
+#include "console.h"
 #include "i2c.h"
 #include "util.h"
 
 /* Sense resistor configurations and macros */
 #define DEFAULT_SENSE_RESISTOR 10
 #define R_SNS CONFIG_CHARGER_SENSE_RESISTOR
-#define R_AC  CONFIG_CHARGER_SENSE_RESISTOR_AC
-#define REG_TO_CURRENT(REG, RS) ((REG) * DEFAULT_SENSE_RESISTOR / (RS))
+#define R_AC CONFIG_CHARGER_SENSE_RESISTOR_AC
+#define REG_TO_CURRENT(REG, RS) ((REG)*DEFAULT_SENSE_RESISTOR / (RS))
 #define CURRENT_TO_REG(CUR, RS) ((CUR) * (RS) / DEFAULT_SENSE_RESISTOR)
 
 /* Note: it is assumed that the sense resistors are 10mOhm. */
 
 static const struct charger_info bq24715_charger_info = {
-	.name         = "bq24715",
-	.voltage_max  = CHARGE_V_MAX,
-	.voltage_min  = CHARGE_V_MIN,
+	.name = "bq24715",
+	.voltage_max = CHARGE_V_MAX,
+	.voltage_min = CHARGE_V_MIN,
 	.voltage_step = CHARGE_V_STEP,
-	.current_max  = REG_TO_CURRENT(CHARGE_I_MAX, R_SNS),
-	.current_min  = REG_TO_CURRENT(CHARGE_I_MIN, R_SNS),
+	.current_max = REG_TO_CURRENT(CHARGE_I_MAX, R_SNS),
+	.current_min = REG_TO_CURRENT(CHARGE_I_MIN, R_SNS),
 	.current_step = REG_TO_CURRENT(CHARGE_I_STEP, R_SNS),
-	.input_current_max  = REG_TO_CURRENT(INPUT_I_MAX, R_AC),
-	.input_current_min  = REG_TO_CURRENT(INPUT_I_MIN, R_AC),
+	.input_current_max = REG_TO_CURRENT(INPUT_I_MAX, R_AC),
+	.input_current_min = REG_TO_CURRENT(INPUT_I_MIN, R_AC),
 	.input_current_step = REG_TO_CURRENT(INPUT_I_STEP, R_AC),
 };
 
 static inline enum ec_error_list sbc_read(int chgnum, int cmd, int *param)
 {
 	return i2c_read16(chg_chips[chgnum].i2c_port,
-			  chg_chips[chgnum].i2c_addr_flags,
-			  cmd, param);
+			  chg_chips[chgnum].i2c_addr_flags, cmd, param);
 }
 
 static inline enum ec_error_list sbc_write(int chgnum, int cmd, int param)
 {
 	return i2c_write16(chg_chips[chgnum].i2c_port,
-			   chg_chips[chgnum].i2c_addr_flags,
-			   cmd, param);
+			   chg_chips[chgnum].i2c_addr_flags, cmd, param);
 }
 
-static enum ec_error_list bq24715_set_input_current(int chgnum,
-						    int input_current)
+static enum ec_error_list bq24715_set_input_current_limit(int chgnum,
+							  int input_current)
 {
 	return sbc_write(chgnum, BQ24715_INPUT_CURRENT,
 			 CURRENT_TO_REG(input_current, R_AC));
 }
 
-static enum ec_error_list bq24715_get_input_current(int chgnum,
-						    int *input_current)
+static enum ec_error_list bq24715_get_input_current_limit(int chgnum,
+							  int *input_current)
 {
 	int rv;
 	int reg;
@@ -209,7 +207,8 @@ static enum ec_error_list bq24715_post_init(int chgnum)
 	if (rv)
 		return rv;
 
-	rv = bq24715_set_input_current(chgnum, CONFIG_CHARGER_INPUT_CURRENT);
+	rv = bq24715_set_input_current_limit(
+		chgnum, CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT);
 	return rv;
 }
 
@@ -242,8 +241,8 @@ const struct charger_drv bq24715_drv = {
 	.get_voltage = &bq24715_get_voltage,
 	.set_voltage = &bq24715_set_voltage,
 	.discharge_on_ac = &bq24715_discharge_on_ac,
-	.set_input_current = &bq24715_set_input_current,
-	.get_input_current = &bq24715_get_input_current,
+	.set_input_current_limit = &bq24715_set_input_current_limit,
+	.get_input_current_limit = &bq24715_get_input_current_limit,
 	.manufacturer_id = &bq24715_manufacturer_id,
 	.device_id = &bq24715_device_id,
 	.get_option = &bq24715_get_option,
diff --git a/driver/charger/bq24715.h b/driver/charger/bq24715.h
index 644f995f2e..905cdf47be 100644
--- a/driver/charger/bq24715.h
+++ b/driver/charger/bq24715.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -14,118 +14,117 @@
  */
 
 /* Chip specific registers */
-#define BQ24715_CHARGE_OPTION           0x12
-#define BQ24715_CHARGE_CURRENT          0x14
-#define BQ24715_MAX_CHARGE_VOLTAGE      0x15
-#define BQ24715_MIN_SYSTEM_VOLTAGE      0x3e
-#define BQ24715_INPUT_CURRENT           0x3f
-#define BQ24715_MANUFACTURER_ID         0xfe
-#define BQ24715_DEVICE_ID               0xff
+#define BQ24715_CHARGE_OPTION 0x12
+#define BQ24715_CHARGE_CURRENT 0x14
+#define BQ24715_MAX_CHARGE_VOLTAGE 0x15
+#define BQ24715_MIN_SYSTEM_VOLTAGE 0x3e
+#define BQ24715_INPUT_CURRENT 0x3f
+#define BQ24715_MANUFACTURER_ID 0xfe
+#define BQ24715_DEVICE_ID 0xff
 
 /* ChargeOption Register - 0x12 */
-#define OPT_LOWPOWER_MASK               BIT(15)
-#define   OPT_LOWPOWER_DSCHRG_I_MON_ON    (0 << 15)
-#define   OPT_LOWPOWER_DSCHRG_I_MON_OFF   BIT(15)
-#define OPT_WATCHDOG_MASK               (3 << 13)
-#define   OPT_WATCHDOG_DISABLE            (0 << 13)
-#define   OPT_WATCHDOG_44SEC              BIT(13)
-#define   OPT_WATCHDOG_88SEC              (2 << 13)
-#define   OPT_WATCHDOG_175SEC             (3 << 13)
-#define OPT_SYSOVP_MASK                 BIT(12)
-#define   OPT_SYSOVP_15P1_3SEC_10P1_2SEC  (0 << 12)
-#define   OPT_SYSOVP_17P0_3SEC_11P3_2SEC  BIT(12)
-#define OPT_SYSOVP_STATUS_MASK          BIT(11)
-#define   OPT_SYSOVP_STATUS               BIT(11)
-#define OPT_AUDIO_FREQ_LIMIT_MASK       BIT(10)
-#define   OPT_AUDIO_FREQ_NO_LIMIT         (0 << 10)
-#define   OPT_AUDIO_FREQ_40KHZ_LIMIT      BIT(10)
-#define OPT_SWITCH_FREQ_MASK            (3 << 8)
-#define   OPT_SWITCH_FREQ_600KHZ          (0 << 8)
-#define   OPT_SWITCH_FREQ_800KHZ          BIT(8)
-#define   OPT_SWITCH_FREQ_1MHZ            (2 << 8)
-#define   OPT_SWITCH_FREQ_800KHZ_DUP      (3 << 8)
-#define OPT_ACOC_MASK                   BIT(7)
-#define   OPT_ACOC_DISABLED               (0 << 7)
-#define   OPT_ACOC_333PCT_IPDM            BIT(7)
-#define OPT_LSFET_OCP_MASK              BIT(6)
-#define   OPT_LSFET_OCP_250MV             (0 << 6)
-#define   OPT_LSFET_OCP_350MV             BIT(6)
-#define OPT_LEARN_MASK                  BIT(5)
-#define   OPT_LEARN_DISABLE               (0 << 5)
-#define   OPT_LEARN_ENABLE                BIT(5)
-#define OPT_IOUT_MASK                   BIT(4)
-#define   OPT_IOUT_40X                    (0 << 4)
-#define   OPT_IOUT_16X                    BIT(4)
-#define OPT_FIX_IOUT_MASK               BIT(3)
-#define   OPT_FIX_IOUT_IDPM_EN            (0 << 3)
-#define   OPT_FIX_IOUT_ALWAYS             BIT(3)
-#define OPT_LDO_MODE_MASK               BIT(2)
-#define   OPT_LDO_DISABLE                 (0 << 2)
-#define   OPT_LDO_ENABLE                  BIT(2)
-#define OPT_IDPM_MASK                   BIT(1)
-#define   OPT_IDPM_DISABLE                (0 << 1)
-#define   OPT_IDPM_ENABLE                 BIT(1)
-#define OPT_CHARGE_INHIBIT_MASK         BIT(0)
-#define   OPT_CHARGE_ENABLE               (0 << 0)
-#define   OPT_CHARGE_DISABLE              BIT(0)
-
+#define OPT_LOWPOWER_MASK BIT(15)
+#define OPT_LOWPOWER_DSCHRG_I_MON_ON (0 << 15)
+#define OPT_LOWPOWER_DSCHRG_I_MON_OFF BIT(15)
+#define OPT_WATCHDOG_MASK (3 << 13)
+#define OPT_WATCHDOG_DISABLE (0 << 13)
+#define OPT_WATCHDOG_44SEC BIT(13)
+#define OPT_WATCHDOG_88SEC (2 << 13)
+#define OPT_WATCHDOG_175SEC (3 << 13)
+#define OPT_SYSOVP_MASK BIT(12)
+#define OPT_SYSOVP_15P1_3SEC_10P1_2SEC (0 << 12)
+#define OPT_SYSOVP_17P0_3SEC_11P3_2SEC BIT(12)
+#define OPT_SYSOVP_STATUS_MASK BIT(11)
+#define OPT_SYSOVP_STATUS BIT(11)
+#define OPT_AUDIO_FREQ_LIMIT_MASK BIT(10)
+#define OPT_AUDIO_FREQ_NO_LIMIT (0 << 10)
+#define OPT_AUDIO_FREQ_40KHZ_LIMIT BIT(10)
+#define OPT_SWITCH_FREQ_MASK (3 << 8)
+#define OPT_SWITCH_FREQ_600KHZ (0 << 8)
+#define OPT_SWITCH_FREQ_800KHZ BIT(8)
+#define OPT_SWITCH_FREQ_1MHZ (2 << 8)
+#define OPT_SWITCH_FREQ_800KHZ_DUP (3 << 8)
+#define OPT_ACOC_MASK BIT(7)
+#define OPT_ACOC_DISABLED (0 << 7)
+#define OPT_ACOC_333PCT_IPDM BIT(7)
+#define OPT_LSFET_OCP_MASK BIT(6)
+#define OPT_LSFET_OCP_250MV (0 << 6)
+#define OPT_LSFET_OCP_350MV BIT(6)
+#define OPT_LEARN_MASK BIT(5)
+#define OPT_LEARN_DISABLE (0 << 5)
+#define OPT_LEARN_ENABLE BIT(5)
+#define OPT_IOUT_MASK BIT(4)
+#define OPT_IOUT_40X (0 << 4)
+#define OPT_IOUT_16X BIT(4)
+#define OPT_FIX_IOUT_MASK BIT(3)
+#define OPT_FIX_IOUT_IDPM_EN (0 << 3)
+#define OPT_FIX_IOUT_ALWAYS BIT(3)
+#define OPT_LDO_MODE_MASK BIT(2)
+#define OPT_LDO_DISABLE (0 << 2)
+#define OPT_LDO_ENABLE BIT(2)
+#define OPT_IDPM_MASK BIT(1)
+#define OPT_IDPM_DISABLE (0 << 1)
+#define OPT_IDPM_ENABLE BIT(1)
+#define OPT_CHARGE_INHIBIT_MASK BIT(0)
+#define OPT_CHARGE_ENABLE (0 << 0)
+#define OPT_CHARGE_DISABLE BIT(0)
 
 /* ChargeCurrent Register - 0x14
  * The ChargeCurrent register controls a DAC. Therefore
  * the below definitions are cummulative. */
-#define CHARGE_I_64MA                   BIT(6)
-#define CHARGE_I_128MA                  BIT(7)
-#define CHARGE_I_256MA                  BIT(8)
-#define CHARGE_I_512MA                  BIT(9)
-#define CHARGE_I_1024MA                 BIT(10)
-#define CHARGE_I_2048MA                 BIT(11)
-#define CHARGE_I_4096MA                 BIT(12)
-#define CHARGE_I_OFF                    (0)
-#define CHARGE_I_MIN                    (128)
-#define CHARGE_I_MAX                    (8128)
-#define CHARGE_I_STEP                   (64)
+#define CHARGE_I_64MA BIT(6)
+#define CHARGE_I_128MA BIT(7)
+#define CHARGE_I_256MA BIT(8)
+#define CHARGE_I_512MA BIT(9)
+#define CHARGE_I_1024MA BIT(10)
+#define CHARGE_I_2048MA BIT(11)
+#define CHARGE_I_4096MA BIT(12)
+#define CHARGE_I_OFF (0)
+#define CHARGE_I_MIN (128)
+#define CHARGE_I_MAX (8128)
+#define CHARGE_I_STEP (64)
 
 /* MaxChargeVoltage Register - 0x15
  * The MaxChargeVoltage register controls a DAC. Therefore
  * the below definitions are cummulative. */
-#define CHARGE_V_16MV                   BIT(4)
-#define CHARGE_V_32MV                   BIT(5)
-#define CHARGE_V_64MV                   BIT(6)
-#define CHARGE_V_128MV                  BIT(7)
-#define CHARGE_V_256MV                  BIT(8)
-#define CHARGE_V_512MV                  BIT(9)
-#define CHARGE_V_1024MV                 BIT(10)
-#define CHARGE_V_2048MV                 BIT(11)
-#define CHARGE_V_4096MV                 BIT(12)
-#define CHARGE_V_8192MV                 BIT(13)
-#define CHARGE_V_MIN                    (4096)
-#define CHARGE_V_MAX                    (0x3ff0)
-#define CHARGE_V_STEP                   (16)
+#define CHARGE_V_16MV BIT(4)
+#define CHARGE_V_32MV BIT(5)
+#define CHARGE_V_64MV BIT(6)
+#define CHARGE_V_128MV BIT(7)
+#define CHARGE_V_256MV BIT(8)
+#define CHARGE_V_512MV BIT(9)
+#define CHARGE_V_1024MV BIT(10)
+#define CHARGE_V_2048MV BIT(11)
+#define CHARGE_V_4096MV BIT(12)
+#define CHARGE_V_8192MV BIT(13)
+#define CHARGE_V_MIN (4096)
+#define CHARGE_V_MAX (0x3ff0)
+#define CHARGE_V_STEP (16)
 
 /* MinSystemVoltage Register - 0x3e
  * The MinSystemVoltage register controls a DAC. Therefore
  * the below definitions are cummulative. */
-#define MIN_SYS_V_256MV                 BIT(8)
-#define MIN_SYS_V_512MV                 BIT(9)
-#define MIN_SYS_V_1024MV                BIT(10)
-#define MIN_SYS_V_2048MV                BIT(11)
-#define MIN_SYS_V_4096MV                BIT(12)
-#define MIN_SYS_V_8192MV                BIT(13)
-#define MIN_SYS_V_MIN                   (4096)
+#define MIN_SYS_V_256MV BIT(8)
+#define MIN_SYS_V_512MV BIT(9)
+#define MIN_SYS_V_1024MV BIT(10)
+#define MIN_SYS_V_2048MV BIT(11)
+#define MIN_SYS_V_4096MV BIT(12)
+#define MIN_SYS_V_8192MV BIT(13)
+#define MIN_SYS_V_MIN (4096)
 
 /* InputCurrent Register - 0x3f
  * The InputCurrent register controls a DAC. Therefore
  * the below definitions are cummulative. */
-#define INPUT_I_64MA                   BIT(6)
-#define INPUT_I_128MA                  BIT(7)
-#define INPUT_I_256MA                  BIT(8)
-#define INPUT_I_512MA                  BIT(9)
-#define INPUT_I_1024MA                 BIT(10)
-#define INPUT_I_2048MA                 BIT(11)
-#define INPUT_I_4096MA                 BIT(12)
-#define INPUT_I_MIN                    (128)
-#define INPUT_I_MAX                    (8064)
-#define INPUT_I_STEP                   (64)
+#define INPUT_I_64MA BIT(6)
+#define INPUT_I_128MA BIT(7)
+#define INPUT_I_256MA BIT(8)
+#define INPUT_I_512MA BIT(9)
+#define INPUT_I_1024MA BIT(10)
+#define INPUT_I_2048MA BIT(11)
+#define INPUT_I_4096MA BIT(12)
+#define INPUT_I_MIN (128)
+#define INPUT_I_MAX (8064)
+#define INPUT_I_STEP (64)
 
 extern const struct charger_drv bq24715_drv;
 
diff --git a/driver/charger/bq24773.c b/driver/charger/bq24773.c
index 87ef187357..d678944ceb 100644
--- a/driver/charger/bq24773.c
+++ b/driver/charger/bq24773.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,8 +8,8 @@
 #include "battery_smart.h"
 #include "bq24773.h"
 #include "charger.h"
-#include "console.h"
 #include "common.h"
+#include "console.h"
 #include "util.h"
 
 /*
@@ -22,23 +22,39 @@
 /* Sense resistor configurations and macros */
 #define DEFAULT_SENSE_RESISTOR 10
 #define R_SNS CONFIG_CHARGER_SENSE_RESISTOR
-#define R_AC  (CONFIG_CHARGER_SENSE_RESISTOR_AC)
-#define REG_TO_CURRENT(REG, RS) ((REG) * DEFAULT_SENSE_RESISTOR / (RS))
+#define R_AC (CONFIG_CHARGER_SENSE_RESISTOR_AC)
+#define REG_TO_CURRENT(REG, RS) ((REG)*DEFAULT_SENSE_RESISTOR / (RS))
 #define CURRENT_TO_REG(CUR, RS) ((CUR) * (RS) / DEFAULT_SENSE_RESISTOR)
-#define REG8_TO_CURRENT(REG, RS) ((REG) * DEFAULT_SENSE_RESISTOR / (RS) * R8)
+#define REG8_TO_CURRENT(REG, RS) ((REG)*DEFAULT_SENSE_RESISTOR / (RS)*R8)
 #define CURRENT_TO_REG8(CUR, RS) ((CUR) * (RS) / DEFAULT_SENSE_RESISTOR / R8)
 
+/* ChargeCurrent Register - 0x14 (mA) */
+#define CHARGE_I_OFF 0
+#define CHARGE_I_MIN 128
+#define CHARGE_I_MAX 8128
+#define CHARGE_I_STEP 64
+
+/* MaxChargeVoltage Register - 0x15 (mV) */
+#define CHARGE_V_MIN 1024
+#define CHARGE_V_MAX 19200
+#define CHARGE_V_STEP 16
+
+/* InputCurrent Register - 0x3f (mA) */
+#define INPUT_I_MIN 128
+#define INPUT_I_MAX 8128
+#define INPUT_I_STEP 64
+
 /* Charger parameters */
 static const struct charger_info bq2477x_charger_info = {
-	.name         = CHARGER_NAME,
-	.voltage_max  = CHARGE_V_MAX,
-	.voltage_min  = CHARGE_V_MIN,
+	.name = CHARGER_NAME,
+	.voltage_max = CHARGE_V_MAX,
+	.voltage_min = CHARGE_V_MIN,
 	.voltage_step = CHARGE_V_STEP,
-	.current_max  = REG_TO_CURRENT(CHARGE_I_MAX, R_SNS),
-	.current_min  = REG_TO_CURRENT(CHARGE_I_MIN, R_SNS),
+	.current_max = REG_TO_CURRENT(CHARGE_I_MAX, R_SNS),
+	.current_min = REG_TO_CURRENT(CHARGE_I_MIN, R_SNS),
 	.current_step = REG_TO_CURRENT(CHARGE_I_STEP, R_SNS),
-	.input_current_max  = REG_TO_CURRENT(INPUT_I_MAX, R_AC),
-	.input_current_min  = REG_TO_CURRENT(INPUT_I_MIN, R_AC),
+	.input_current_max = REG_TO_CURRENT(INPUT_I_MAX, R_AC),
+	.input_current_min = REG_TO_CURRENT(INPUT_I_MIN, R_AC),
 	.input_current_step = REG_TO_CURRENT(INPUT_I_STEP, R_AC),
 };
 
@@ -46,37 +62,32 @@ static const struct charger_info bq2477x_charger_info = {
 static inline enum ec_error_list raw_read8(int chgnum, int offset, int *value)
 {
 	return i2c_read8(chg_chips[chgnum].i2c_port,
-			 chg_chips[chgnum].i2c_addr_flags,
-			 offset, value);
+			 chg_chips[chgnum].i2c_addr_flags, offset, value);
 }
 
 static inline enum ec_error_list raw_write8(int chgnum, int offset, int value)
 {
 	return i2c_write8(chg_chips[chgnum].i2c_port,
-			  chg_chips[chgnum].i2c_addr_flags,
-			  offset, value);
+			  chg_chips[chgnum].i2c_addr_flags, offset, value);
 }
 #endif
 
 static inline enum ec_error_list raw_read16(int chgnum, int offset, int *value)
 {
 	return i2c_read16(chg_chips[chgnum].i2c_port,
-			  chg_chips[chgnum].i2c_addr_flags,
-			  offset, value);
+			  chg_chips[chgnum].i2c_addr_flags, offset, value);
 }
 
 static inline enum ec_error_list raw_write16(int chgnum, int offset, int value)
 {
 	return i2c_write16(chg_chips[chgnum].i2c_port,
-			   chg_chips[chgnum].i2c_addr_flags,
-			   offset, value);
+			   chg_chips[chgnum].i2c_addr_flags, offset, value);
 }
 
-
 /* chip specific interfaces */
 
-static enum ec_error_list bq2477x_set_input_current(int chgnum,
-						    int input_current)
+static enum ec_error_list bq2477x_set_input_current_limit(int chgnum,
+							  int input_current)
 {
 #ifdef CONFIG_CHARGER_BQ24770
 	return raw_write16(chgnum, REG_INPUT_CURRENT,
@@ -87,8 +98,8 @@ static enum ec_error_list bq2477x_set_input_current(int chgnum,
 #endif
 }
 
-static enum ec_error_list bq2477x_get_input_current(int chgnum,
-						    int *input_current)
+static enum ec_error_list bq2477x_get_input_current_limit(int chgnum,
+							  int *input_current)
 {
 	int rv;
 	int reg;
@@ -228,22 +239,13 @@ static enum ec_error_list bq2477x_post_init(int chgnum)
 	if (rv)
 		return rv;
 
-#ifndef BOARD_SAMUS
 	/* Turn off PROCHOT warning */
 	rv = raw_read16(chgnum, REG_PROCHOT_OPTION1, &option);
 	if (rv)
 		return rv;
 
 	option &= ~PROCHOT_OPTION1_SELECTOR_MASK;
-
 	rv = raw_write16(chgnum, REG_PROCHOT_OPTION1, option);
-#else
-	/* On Samus, use PROCHOT warning to detect charging problems */
-	/* Turn on PROCHOT warning */
-	rv = raw_write16(chgnum, REG_PROCHOT_OPTION1, 0x8120);
-	/* Set PROCHOT ICRIT warning when IADP is >120% of IDPM */
-	rv |= raw_write16(chgnum, REG_PROCHOT_OPTION0, 0x1b54);
-#endif
 
 	if (rv)
 		return rv;
@@ -292,8 +294,8 @@ const struct charger_drv bq2477x_drv = {
 	.get_voltage = &bq2477x_get_voltage,
 	.set_voltage = &bq2477x_set_voltage,
 	.discharge_on_ac = &bq2477x_discharge_on_ac,
-	.set_input_current = &bq2477x_set_input_current,
-	.get_input_current = &bq2477x_get_input_current,
+	.set_input_current_limit = &bq2477x_set_input_current_limit,
+	.get_input_current_limit = &bq2477x_get_input_current_limit,
 	.manufacturer_id = &bq2477x_manufacturer_id,
 	.device_id = &bq2477x_device_id,
 	.get_option = &bq2477x_get_option,
diff --git a/driver/charger/bq24773.h b/driver/charger/bq24773.h
index c22bfa528a..ede480e9d0 100644
--- a/driver/charger/bq24773.h
+++ b/driver/charger/bq24773.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -12,94 +12,78 @@
 #include "i2c.h"
 
 /* I2C address */
-#define BQ24770_ADDR_FLAGS	0x09
-#define BQ24773_ADDR_FLAGS	0x6a
+#define BQ24770_ADDR_FLAGS 0x09
+#define BQ24773_ADDR_FLAGS 0x6a
 
 /* Chip specific commands */
-#define BQ24770_CHARGE_OPTION0          0x12
-#define BQ24770_CHARGE_OPTION1          0x3B
-#define BQ24770_CHARGE_OPTION2          0x38
-#define BQ24770_PROCHOT_OPTION0         0x3C
-#define BQ24770_PROCHOT_OPTION1         0x3D
-#define BQ24770_CHARGE_CURRENT          0x14
-#define BQ24770_MAX_CHARGE_VOLTAGE      0x15
-#define BQ24770_MIN_SYSTEM_VOLTAGE      0x3E
-#define BQ24770_INPUT_CURRENT           0x3F
-#define BQ24770_MANUFACTURE_ID          0xFE
-#define BQ24770_DEVICE_ADDRESS          0xFF
-
-#define BQ24773_CHARGE_OPTION0          0x00
-#define BQ24773_CHARGE_OPTION1          0x02
-#define BQ24773_PROCHOT_OPTION0         0x04
-#define BQ24773_PROCHOT_OPTION1         0x06
-#define BQ24773_PROCHOT_STATUS          0x08
-#define BQ24773_DEVICE_ADDRESS          0x09
-#define BQ24773_CHARGE_CURRENT          0x0A
-#define BQ24773_MAX_CHARGE_VOLTAGE      0x0C
-#define BQ24773_MIN_SYSTEM_VOLTAGE      0x0E
-#define BQ24773_INPUT_CURRENT           0x0F
-#define BQ24773_CHARGE_OPTION2          0x10
+#define BQ24770_CHARGE_OPTION0 0x12
+#define BQ24770_CHARGE_OPTION1 0x3B
+#define BQ24770_CHARGE_OPTION2 0x38
+#define BQ24770_PROCHOT_OPTION0 0x3C
+#define BQ24770_PROCHOT_OPTION1 0x3D
+#define BQ24770_CHARGE_CURRENT 0x14
+#define BQ24770_MAX_CHARGE_VOLTAGE 0x15
+#define BQ24770_MIN_SYSTEM_VOLTAGE 0x3E
+#define BQ24770_INPUT_CURRENT 0x3F
+#define BQ24770_MANUFACTURE_ID 0xFE
+#define BQ24770_DEVICE_ADDRESS 0xFF
+
+#define BQ24773_CHARGE_OPTION0 0x00
+#define BQ24773_CHARGE_OPTION1 0x02
+#define BQ24773_PROCHOT_OPTION0 0x04
+#define BQ24773_PROCHOT_OPTION1 0x06
+#define BQ24773_PROCHOT_STATUS 0x08
+#define BQ24773_DEVICE_ADDRESS 0x09
+#define BQ24773_CHARGE_CURRENT 0x0A
+#define BQ24773_MAX_CHARGE_VOLTAGE 0x0C
+#define BQ24773_MIN_SYSTEM_VOLTAGE 0x0E
+#define BQ24773_INPUT_CURRENT 0x0F
+#define BQ24773_CHARGE_OPTION2 0x10
 
 /* Option bits */
-#define OPTION0_CHARGE_INHIBIT          BIT(0)
-#define OPTION0_LEARN_ENABLE            BIT(5)
-#define OPTION0_SWITCHING_FREQ_MASK     (3 << 8)
-#define OPTION0_SWITCHING_FREQ_600KHZ   (0 << 8)
-#define OPTION0_SWITCHING_FREQ_800KHZ   BIT(8)
-#define OPTION0_SWITCHING_FREQ_1000KHZ  (2 << 8)
-#define OPTION0_SWITCHING_FREQ_1200KHZ  (3 << 8)
+#define OPTION0_CHARGE_INHIBIT BIT(0)
+#define OPTION0_LEARN_ENABLE BIT(5)
+#define OPTION0_SWITCHING_FREQ_MASK (3 << 8)
+#define OPTION0_SWITCHING_FREQ_600KHZ (0 << 8)
+#define OPTION0_SWITCHING_FREQ_800KHZ BIT(8)
+#define OPTION0_SWITCHING_FREQ_1000KHZ (2 << 8)
+#define OPTION0_SWITCHING_FREQ_1200KHZ (3 << 8)
 
-#define OPTION2_EN_EXTILIM              BIT(7)
+#define OPTION2_EN_EXTILIM BIT(7)
 
 /* Prochot Option bits */
-#define PROCHOT_OPTION1_SELECTOR_MASK   0x7f /* [6:0] PROCHOT SELECTOR */
-
-/* ChargeCurrent Register - 0x14 (mA) */
-#define CHARGE_I_OFF                    0
-#define CHARGE_I_MIN                    128
-#define CHARGE_I_MAX                    8128
-#define CHARGE_I_STEP                   64
-
-/* MaxChargeVoltage Register - 0x15 (mV) */
-#define CHARGE_V_MIN                    1024
-#define CHARGE_V_MAX                    19200
-#define CHARGE_V_STEP                   16
-
-/* InputCurrent Register - 0x3f (mA) */
-#define INPUT_I_MIN                    128
-#define INPUT_I_MAX                    8128
-#define INPUT_I_STEP                   64
+#define PROCHOT_OPTION1_SELECTOR_MASK 0x7f /* [6:0] PROCHOT SELECTOR */
 
 #ifdef CONFIG_CHARGER_BQ24770
-	#define CHARGER_NAME		"bq24770"
-	#define I2C_ADDR_CHARGER_FLAGS	BQ24770_ADDR_FLAGS
-
-	#define REG_CHARGE_OPTION0	BQ24770_CHARGE_OPTION0
-	#define REG_CHARGE_OPTION1	BQ24770_CHARGE_OPTION1
-	#define REG_CHARGE_OPTION2	BQ24770_CHARGE_OPTION2
-	#define REG_PROCHOT_OPTION0	BQ24770_PROCHOT_OPTION0
-	#define REG_PROCHOT_OPTION1	BQ24770_PROCHOT_OPTION1
-	#define REG_CHARGE_CURRENT	BQ24770_CHARGE_CURRENT
-	#define REG_MAX_CHARGE_VOLTAGE	BQ24770_MAX_CHARGE_VOLTAGE
-	#define REG_MIN_SYSTEM_VOLTAGE	BQ24770_MIN_SYSTEM_VOLTAGE
-	#define REG_INPUT_CURRENT	BQ24770_INPUT_CURRENT
-	#define REG_MANUFACTURE_ID	BQ24770_MANUFACTURE_ID
-	#define REG_DEVICE_ADDRESS	BQ24770_DEVICE_ADDRESS
+#define CHARGER_NAME "bq24770"
+#define I2C_ADDR_CHARGER_FLAGS BQ24770_ADDR_FLAGS
+
+#define REG_CHARGE_OPTION0 BQ24770_CHARGE_OPTION0
+#define REG_CHARGE_OPTION1 BQ24770_CHARGE_OPTION1
+#define REG_CHARGE_OPTION2 BQ24770_CHARGE_OPTION2
+#define REG_PROCHOT_OPTION0 BQ24770_PROCHOT_OPTION0
+#define REG_PROCHOT_OPTION1 BQ24770_PROCHOT_OPTION1
+#define REG_CHARGE_CURRENT BQ24770_CHARGE_CURRENT
+#define REG_MAX_CHARGE_VOLTAGE BQ24770_MAX_CHARGE_VOLTAGE
+#define REG_MIN_SYSTEM_VOLTAGE BQ24770_MIN_SYSTEM_VOLTAGE
+#define REG_INPUT_CURRENT BQ24770_INPUT_CURRENT
+#define REG_MANUFACTURE_ID BQ24770_MANUFACTURE_ID
+#define REG_DEVICE_ADDRESS BQ24770_DEVICE_ADDRESS
 
 #elif defined(CONFIG_CHARGER_BQ24773)
-	#define CHARGER_NAME		"bq24773"
-	#define I2C_ADDR_CHARGER_FLAGS	BQ24773_ADDR_FLAGS
-
-	#define REG_CHARGE_OPTION0	BQ24773_CHARGE_OPTION0
-	#define REG_CHARGE_OPTION1	BQ24773_CHARGE_OPTION1
-	#define REG_CHARGE_OPTION2	BQ24773_CHARGE_OPTION2
-	#define REG_PROCHOT_OPTION0	BQ24773_PROCHOT_OPTION0
-	#define REG_PROCHOT_OPTION1	BQ24773_PROCHOT_OPTION1
-	#define REG_CHARGE_CURRENT	BQ24773_CHARGE_CURRENT
-	#define REG_MAX_CHARGE_VOLTAGE	BQ24773_MAX_CHARGE_VOLTAGE
-	#define REG_MIN_SYSTEM_VOLTAGE	BQ24773_MIN_SYSTEM_VOLTAGE
-	#define REG_INPUT_CURRENT	BQ24773_INPUT_CURRENT
-	#define REG_DEVICE_ADDRESS	BQ24773_DEVICE_ADDRESS
+#define CHARGER_NAME "bq24773"
+#define I2C_ADDR_CHARGER_FLAGS BQ24773_ADDR_FLAGS
+
+#define REG_CHARGE_OPTION0 BQ24773_CHARGE_OPTION0
+#define REG_CHARGE_OPTION1 BQ24773_CHARGE_OPTION1
+#define REG_CHARGE_OPTION2 BQ24773_CHARGE_OPTION2
+#define REG_PROCHOT_OPTION0 BQ24773_PROCHOT_OPTION0
+#define REG_PROCHOT_OPTION1 BQ24773_PROCHOT_OPTION1
+#define REG_CHARGE_CURRENT BQ24773_CHARGE_CURRENT
+#define REG_MAX_CHARGE_VOLTAGE BQ24773_MAX_CHARGE_VOLTAGE
+#define REG_MIN_SYSTEM_VOLTAGE BQ24773_MIN_SYSTEM_VOLTAGE
+#define REG_INPUT_CURRENT BQ24773_INPUT_CURRENT
+#define REG_DEVICE_ADDRESS BQ24773_DEVICE_ADDRESS
 #endif
 
 extern const struct charger_drv bq2477x_drv;
diff --git a/driver/charger/bq25710.c b/driver/charger/bq25710.c
index e653588bca..a13770a02c 100644
--- a/driver/charger/bq25710.c
+++ b/driver/charger/bq25710.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -7,23 +7,98 @@
 
 #include "battery.h"
 #include "battery_smart.h"
-#include "bq25710.h"
+#include "bq257x0_regs.h"
 #include "charge_ramp.h"
-#include "charge_state_v2.h"
+#include "charge_state.h"
 #include "charger.h"
 #include "common.h"
 #include "console.h"
 #include "hooks.h"
 #include "i2c.h"
-#include "task.h"
 #include "system.h"
+#include "task.h"
 #include "timer.h"
 #include "util.h"
 
+#include <stdbool.h>
+
+#if !defined(CONFIG_CHARGER_BQ25710) && !defined(CONFIG_CHARGER_BQ25720)
+#error Only the BQ25720 and BQ25710 are supported by bq25710 driver.
+#endif
+
 #ifndef CONFIG_CHARGER_NARROW_VDC
 #error "BQ25710 is a NVDC charger, please enable CONFIG_CHARGER_NARROW_VDC."
 #endif
 
+#ifndef CONFIG_CHARGER_BQ25720_VSYS_TH2_CUSTOM
+#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV \
+	GET_BQ_FIELD(BQ25720, VMIN_AP, VSYS_TH2, UINT16_MAX)
+#endif
+
+#ifndef CONFIG_CHARGER_BQ25710_VSYS_MIN_VOLTAGE_CUSTOM
+#define CONFIG_CHARGER_BQ25710_VSYS_MIN_VOLTAGE_MV 0
+#endif
+
+#ifndef CONFIG_CHARGER_BQ25720_VSYS_UVP_CUSTOM
+#define CONFIG_CHARGER_BQ25720_VSYS_UVP 0
+#endif
+
+#ifndef CONFIG_CHARGER_BQ25720_IDCHG_DEG2_CUSTOM
+#define CONFIG_CHARGER_BQ25720_IDCHG_DEG2 1
+#endif
+
+#ifndef CONFIG_CHARGER_BQ25720_IDCHG_TH2_CUSTOM
+#define CONFIG_CHARGER_BQ25720_IDCHG_TH2 1
+#endif
+
+#if !defined(CONFIG_ZEPHYR) && \
+	!defined(CONFIG_CHARGER_BQ25710_PKPWR_TOVLD_DEG_CUSTOM)
+#define CONFIG_CHARGER_BQ25710_PKPWR_TOVLD_DEG 0
+#endif
+
+#ifndef CONFIG_CHARGER_BQ257X0_ILIM2_VTH_CUSTOM
+/* Reduce ILIM from default of 150% to 110% */
+#define CONFIG_CHARGER_BQ257X0_ILIM2_VTH \
+	BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH__1P10
+#endif
+
+/*
+ * Helper macros
+ */
+
+#define SET_CO1_BY_NAME(_field, _c, _x) \
+	SET_BQ_FIELD_BY_NAME(BQ257X0, CHARGE_OPTION_1, _field, _c, (_x))
+
+#define SET_CO2(_field, _v, _x) \
+	SET_BQ_FIELD(BQ257X0, CHARGE_OPTION_2, _field, _v, (_x))
+
+#define SET_CO2_BY_NAME(_field, _c, _x) \
+	SET_BQ_FIELD_BY_NAME(BQ257X0, CHARGE_OPTION_2, _field, _c, (_x))
+
+#define SET_CO3(_field, _v, _x) \
+	SET_BQ_FIELD(BQ257X0, CHARGE_OPTION_3, _field, _v, (_x))
+
+#define SET_CO3_BY_NAME(_field, _c, _x) \
+	SET_BQ_FIELD_BY_NAME(BQ257X0, CHARGE_OPTION_3, _field, _c, (_x))
+
+#define SET_CO4(_field, _v, _x) \
+	SET_BQ_FIELD(BQ25720, CHARGE_OPTION_4, _field, _v, (_x))
+
+#define SET_CO4_BY_NAME(_field, _c, _x) \
+	SET_BQ_FIELD_BY_NAME(BQ25720, CHARGE_OPTION_4, _field, _c, (_x))
+
+#define SET_PO0(_field, _v, _x) \
+	SET_BQ_FIELD(BQ257X0, PROCHOT_OPTION_0, _field, _v, (_x))
+
+#define SET_PO0_BY_NAME(_field, _c, _x) \
+	SET_BQ_FIELD_BY_NAME(BQ257X0, PROCHOT_OPTION_0, _field, _c, (_x))
+
+#define SET_PO1(_field, _v, _x) \
+	SET_BQ_FIELD(BQ257X0, PROCHOT_OPTION_1, _field, _v, (_x))
+
+#define SET_PO1_BY_NAME(_field, _c, _x) \
+	SET_BQ_FIELD_BY_NAME(BQ257X0, PROCHOT_OPTION_1, _field, _c, (_x))
+
 /*
  * Delay required from taking the bq25710 out of low power mode and having the
  * correct value in register 0x3E for VSYS_MIN voltage. The length of the delay
@@ -35,18 +110,17 @@
 /* Sense resistor configurations and macros */
 #define DEFAULT_SENSE_RESISTOR 10
 
-#define INPUT_RESISTOR_RATIO \
-	((CONFIG_CHARGER_SENSE_RESISTOR_AC) / DEFAULT_SENSE_RESISTOR)
-#define REG_TO_INPUT_CURRENT(REG) ((REG + 1) * 50 / INPUT_RESISTOR_RATIO)
-#define INPUT_CURRENT_TO_REG(CUR) (((CUR) * INPUT_RESISTOR_RATIO / 50) - 1)
-
-#define CHARGING_RESISTOR_RATIO \
-	((CONFIG_CHARGER_SENSE_RESISTOR) / DEFAULT_SENSE_RESISTOR)
-#define REG_TO_CHARGING_CURRENT(REG) ((REG) / CHARGING_RESISTOR_RATIO)
-#define CHARGING_CURRENT_TO_REG(CUR) ((CUR) * CHARGING_RESISTOR_RATIO)
+#define REG_TO_CHARGING_CURRENT(REG) \
+	((REG)*DEFAULT_SENSE_RESISTOR / CONFIG_CHARGER_BQ25710_SENSE_RESISTOR)
+#define REG_TO_CHARGING_CURRENT_AC(REG) \
+	((REG)*DEFAULT_SENSE_RESISTOR / \
+	 CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC)
+#define CHARGING_CURRENT_TO_REG(CUR) \
+	((CUR)*CONFIG_CHARGER_BQ25710_SENSE_RESISTOR / DEFAULT_SENSE_RESISTOR)
+#define VMIN_AP_VSYS_TH2_TO_REG(DV) ((DV)-32)
 
 /* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
 
 #ifdef CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA
 /*
@@ -58,35 +132,76 @@ static uint32_t bq25710_perf_mode_req;
 static struct mutex bq25710_perf_mode_mutex;
 #endif
 
+/*
+ * 10mOhm sense resistor, there is 50mA offset at code 0.
+ * 5mOhm sense resistor, there is 100mA offset at code 0.
+ */
+#define BQ25710_IIN_DPM_CODE0_OFFSET REG_TO_CHARGING_CURRENT(50)
+
 /* Charger parameters */
 static const struct charger_info bq25710_charger_info = {
-	.name         = "bq25710",
-	.voltage_max  = 19200,
-	.voltage_min  = 1024,
+	.name = "bq25710",
+	.voltage_max = 19200,
+	.voltage_min = 1024,
 	.voltage_step = 8,
-	.current_max  = 8128 / CHARGING_RESISTOR_RATIO,
-	.current_min  = 64 / CHARGING_RESISTOR_RATIO,
-	.current_step = 64 / CHARGING_RESISTOR_RATIO,
-	.input_current_max  = 6400 / INPUT_RESISTOR_RATIO,
-	.input_current_min  = 50 / INPUT_RESISTOR_RATIO,
-	.input_current_step = 50 / INPUT_RESISTOR_RATIO,
+	.current_max = REG_TO_CHARGING_CURRENT(8128),
+	.current_min = REG_TO_CHARGING_CURRENT(64),
+	.current_step = REG_TO_CHARGING_CURRENT(64),
+	.input_current_max = REG_TO_CHARGING_CURRENT_AC(6400),
+	.input_current_min = REG_TO_CHARGING_CURRENT_AC(50),
+	.input_current_step = REG_TO_CHARGING_CURRENT_AC(50),
 };
 
 static enum ec_error_list bq25710_get_option(int chgnum, int *option);
 static enum ec_error_list bq25710_set_option(int chgnum, int option);
 
+static inline int iin_dpm_reg_to_current(int reg)
+{
+	/*
+	 * When set 00 at 3F register, read 22h back,
+	 * you will see 00, but actually it’s 50mA@10mOhm right now.
+	 * TI don’t have exactly 0A setting for input current limit,
+	 * it set the 50mA@10mOhm offset so that the converter can
+	 * work normally.
+	 */
+	if (reg == 0)
+		return BQ25710_IIN_DPM_CODE0_OFFSET;
+	else
+		return REG_TO_CHARGING_CURRENT_AC(
+			reg * BQ257X0_IIN_DPM_CURRENT_STEP_MA);
+}
+
+static inline int iin_host_current_to_reg(int current)
+{
+	return (REG_TO_CHARGING_CURRENT_AC(current) /
+		BQ257X0_IIN_HOST_CURRENT_STEP_MA);
+}
+
 static inline enum ec_error_list raw_read16(int chgnum, int offset, int *value)
 {
 	return i2c_read16(chg_chips[chgnum].i2c_port,
-			  chg_chips[chgnum].i2c_addr_flags,
-			  offset, value);
+			  chg_chips[chgnum].i2c_addr_flags, offset, value);
+}
+
+static inline int min_system_voltage_to_reg(int voltage_mv)
+{
+	int steps;
+	int reg;
+
+	if (IS_ENABLED(CONFIG_CHARGER_BQ25720)) {
+		steps = voltage_mv / BQ25720_VSYS_MIN_VOLTAGE_STEP_MV;
+		reg = SET_BQ_FIELD(BQ25720, VSYS_MIN, VOLTAGE, steps, 0);
+	} else {
+		steps = voltage_mv / BQ25710_MIN_SYSTEM_VOLTAGE_STEP_MV;
+		reg = SET_BQ_FIELD(BQ25710, MIN_SYSTEM, VOLTAGE, steps, 0);
+	}
+	return reg;
 }
 
 static inline enum ec_error_list raw_write16(int chgnum, int offset, int value)
 {
 	return i2c_write16(chg_chips[chgnum].i2c_port,
-			   chg_chips[chgnum].i2c_addr_flags,
-			   offset, value);
+			   chg_chips[chgnum].i2c_addr_flags, offset, value);
 }
 
 #if defined(CONFIG_CHARGE_RAMP_HW) || \
@@ -100,7 +215,7 @@ static int bq25710_get_low_power_mode(int chgnum, int *mode)
 	if (rv)
 		return rv;
 
-	*mode = !!(reg & BQ25710_CHARGE_OPTION_0_LOW_POWER_MODE);
+	*mode = !!(reg & BQ_FIELD_MASK(BQ257X0, CHARGE_OPTION_0, EN_LWPWR));
 
 	return EC_SUCCESS;
 }
@@ -130,9 +245,11 @@ static int bq25710_set_low_power_mode(int chgnum, int enable)
 #endif
 
 	if (enable)
-		reg |= BQ25710_CHARGE_OPTION_0_LOW_POWER_MODE;
+		reg = SET_BQ_FIELD(BQ257X0, CHARGE_OPTION_0, EN_LWPWR, true,
+				   reg);
 	else
-		reg &= ~BQ25710_CHARGE_OPTION_0_LOW_POWER_MODE;
+		reg = SET_BQ_FIELD(BQ257X0, CHARGE_OPTION_0, EN_LWPWR, false,
+				   reg);
 
 	rv = raw_write16(chgnum, BQ25710_REG_CHARGE_OPTION_0, reg);
 #ifdef CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA
@@ -144,11 +261,28 @@ static int bq25710_set_low_power_mode(int chgnum, int enable)
 	return EC_SUCCESS;
 }
 
+static int co1_set_psys_sensing(int reg, bool enable)
+{
+	if (IS_ENABLED(CONFIG_CHARGER_BQ25720)) {
+		if (enable)
+			reg = SET_BQ_FIELD_BY_NAME(BQ25720, CHARGE_OPTION_1,
+						   PSYS_CONFIG, PBUS_PBAT, reg);
+		else
+			reg = SET_BQ_FIELD_BY_NAME(BQ25720, CHARGE_OPTION_1,
+						   PSYS_CONFIG, OFF, reg);
+	} else if (IS_ENABLED(CONFIG_CHARGER_BQ25710)) {
+		reg = SET_BQ_FIELD(BQ25710, CHARGE_OPTION_1, EN_PSYS, enable,
+				   reg);
+	}
+
+	return reg;
+}
+
 static int bq25710_adc_start(int chgnum, int adc_en_mask)
 {
 	int reg;
 	int mode;
-	int tries_left = 8;
+	int tries_left = BQ25710_ADC_OPTION_ADC_CONV_MS;
 
 	/* Save current mode to restore same state after ADC read */
 	if (bq25710_get_low_power_mode(chgnum, &mode))
@@ -162,33 +296,242 @@ static int bq25710_adc_start(int chgnum, int adc_en_mask)
 	 * Turn on the ADC for one reading. Note that adc_en_mask
 	 * maps to bit[7:0] in ADCOption register.
 	 */
-	reg = (adc_en_mask & BQ25710_ADC_OPTION_EN_ADC_ALL) |
-	      BQ25710_ADC_OPTION_ADC_START;
+	reg = (adc_en_mask & BQ257X0_ADC_OPTION_EN_ADC_ALL) |
+	      BQ_FIELD_MASK(BQ257X0, ADC_OPTION, ADC_START);
 	if (raw_write16(chgnum, BQ25710_REG_ADC_OPTION, reg))
 		return EC_ERROR_UNKNOWN;
 
 	/*
 	 * Wait until the ADC operation completes. The spec says typical
-	 * conversion time is 10 msec. If low power mode isn't exited first,
-	 * then the conversion time jumps to ~60 msec.
+	 * conversion time is 10 msec (25 msec on bq25720). If low power
+	 * mode isn't exited first, then the conversion time jumps to
+	 * ~60 msec.
 	 */
 	do {
+		/* sleep 2 ms so we time out after 2x the expected time */
 		msleep(2);
 		raw_read16(chgnum, BQ25710_REG_ADC_OPTION, &reg);
-	} while (--tries_left && (reg & BQ25710_ADC_OPTION_ADC_START));
+	} while (--tries_left &&
+		 (reg & BQ_FIELD_MASK(BQ257X0, ADC_OPTION, ADC_START)));
 
 	/* ADC reading attempt complete, go back to low power mode */
 	if (bq25710_set_low_power_mode(chgnum, mode))
 		return EC_ERROR_UNKNOWN;
 
 	/* Could not complete read */
-	if (reg & BQ25710_ADC_OPTION_ADC_START)
+	if (reg & BQ_FIELD_MASK(BQ257X0, ADC_OPTION, ADC_START))
 		return EC_ERROR_TIMEOUT;
 
 	return EC_SUCCESS;
 }
 #endif
 
+static int bq257x0_init_charge_option_1(int chgnum)
+{
+	int rv;
+	int reg;
+
+	if (!IS_ENABLED(CONFIG_CHARGER_BQ25710_PSYS_SENSING) &&
+	    !IS_ENABLED(CONFIG_CHARGER_BQ25710_CMP_REF_1P2))
+		return EC_SUCCESS;
+
+	rv = raw_read16(chgnum, BQ25710_REG_CHARGE_OPTION_1, &reg);
+	if (rv)
+		return rv;
+
+	if (IS_ENABLED(CONFIG_CHARGER_BQ25710_PSYS_SENSING))
+		reg = co1_set_psys_sensing(reg, true);
+
+	if (IS_ENABLED(CONFIG_CHARGER_BQ25710_CMP_REF_1P2))
+		reg = SET_CO1_BY_NAME(CMP_REF, 1P2, reg);
+
+	if (IS_ENABLED(CONFIG_CHARGER_BQ25710_CMP_POL_EXTERNAL))
+		reg = SET_CO1_BY_NAME(CMP_POL, EXTERNAL, reg);
+
+	return raw_write16(chgnum, BQ25710_REG_CHARGE_OPTION_1, reg);
+}
+
+static int bq257x0_init_prochot_option_0(int chgnum)
+{
+	int rv;
+	int reg;
+
+	rv = raw_read16(chgnum, BQ25710_REG_PROCHOT_OPTION_0, &reg);
+	if (rv)
+		return rv;
+
+	reg = SET_PO0(ILIM2_VTH, CONFIG_CHARGER_BQ257X0_ILIM2_VTH, reg);
+
+	return raw_write16(chgnum, BQ25710_REG_PROCHOT_OPTION_0, reg);
+}
+
+static int bq257x0_init_prochot_option_1(int chgnum)
+{
+	int rv;
+	int reg;
+
+	rv = raw_read16(chgnum, BQ25710_REG_PROCHOT_OPTION_1, &reg);
+	if (rv)
+		return rv;
+
+	/* Disable VDPM prochot profile at initialization */
+	reg = SET_PO1_BY_NAME(PP_VDPM, DISABLE, reg);
+
+	/*
+	 * Enable PROCHOT to be asserted with VSYS min detection. Note
+	 * that when no battery is present, then VSYS will be set to the
+	 * value in register 0x3E (MinSysVoltage) which means that when
+	 * no battery is present prochot will continuosly be asserted.
+	 */
+	reg = SET_PO1_BY_NAME(PP_VSYS, ENABLE, reg);
+
+#ifdef CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA
+	/*
+	 * Set the IDCHG limit who's value is defined in the config
+	 * option in mA.
+	 *
+	 * IDCHG limit is in 512 mA steps. Note there is a 128 mA offset
+	 * so the actual IDCHG limit will be the value stored in
+	 * IDCHG_VTH + 128 mA.
+	 */
+	reg = SET_PO1(IDCHG_VTH, CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA >> 9,
+		      reg);
+
+	/*  Enable IDCHG trigger for prochot. */
+	reg = SET_PO1_BY_NAME(PP_IDCHG, ENABLE, reg);
+#endif
+	if (IS_ENABLED(CONFIG_CHARGER_BQ25710_PP_COMP))
+		reg = SET_PO1_BY_NAME(PP_COMP, ENABLE, reg);
+
+	if (IS_ENABLED(CONFIG_CHARGER_BQ25710_PP_INOM))
+		reg = SET_PO1_BY_NAME(PP_INOM, ENABLE, reg);
+
+	if (IS_ENABLED(CONFIG_CHARGER_BQ25710_PP_BATPRES))
+		reg = SET_PO1_BY_NAME(PP_BATPRES, ENABLE, reg);
+
+	if (IS_ENABLED(CONFIG_CHARGER_BQ25710_PP_ACOK))
+		reg = SET_PO1_BY_NAME(PP_ACOK, ENABLE, reg);
+
+	return raw_write16(chgnum, BQ25710_REG_PROCHOT_OPTION_1, reg);
+}
+
+static int bq257x0_init_charge_option_2(int chgnum)
+{
+	int reg;
+	int rv;
+
+	rv = raw_read16(chgnum, BQ25710_REG_CHARGE_OPTION_2, &reg);
+	if (rv)
+		return rv;
+
+	/*
+	 * Reduce peak power mode overload and relax cycle time from
+	 * default 20 msec to the minimum of 5 msec on the bq25710. The
+	 * minimum is 20 msec on the bq25720.
+	 */
+	reg = SET_BQ_FIELD(BQ257X0, CHARGE_OPTION_2, PKPWR_TMAX, 0, reg);
+
+	if (IS_ENABLED(CONFIG_CHARGER_BQ25710_PKPWR_TOVLD_DEG_CUSTOM)) {
+		/* Set input overload time in peak power mode. */
+		reg = SET_CO2(PKPWR_TOVLD_DEG,
+			      CONFIG_CHARGER_BQ25710_PKPWR_TOVLD_DEG, reg);
+	}
+
+	if (IS_ENABLED(CONFIG_CHARGER_BQ25710_EN_ACOC)) {
+		/* Enable AC input over-current protection. */
+		reg = SET_CO2_BY_NAME(EN_ACOC, ENABLE, reg);
+	}
+
+	if (IS_ENABLED(CONFIG_CHARGER_BQ25710_ACOC_VTH_1P33)) {
+		/* Set ACOC threshold to 133% of ILIM2 */
+		reg = SET_CO2_BY_NAME(ACOC_VTH, 1P33, reg);
+	}
+
+	if (IS_ENABLED(CONFIG_CHARGER_BQ25710_BATOC_VTH_MINIMUM)) {
+		/* Set battery over-current threshold to minimum. */
+		reg = SET_CO2_BY_NAME(BATOC_VTH, 1P33, reg);
+	}
+
+	return raw_write16(chgnum, BQ25710_REG_CHARGE_OPTION_2, reg);
+}
+
+static int bq257x0_init_charge_option_3(int chgnum)
+{
+	int reg;
+	int rv;
+
+	if (!IS_ENABLED(CONFIG_CHARGER_BQ25720))
+		return EC_SUCCESS;
+
+	rv = raw_read16(chgnum, BQ25710_REG_CHARGE_OPTION_3, &reg);
+	if (rv)
+		return rv;
+
+	reg = SET_CO3_BY_NAME(IL_AVG, 10A, reg);
+
+	return raw_write16(chgnum, BQ25710_REG_CHARGE_OPTION_3, reg);
+}
+
+static int bq257x0_init_charge_option_4(int chgnum)
+{
+	int reg;
+	int rv;
+
+	if (!IS_ENABLED(CONFIG_CHARGER_BQ25720))
+		return EC_SUCCESS;
+
+	if (!IS_ENABLED(CONFIG_CHARGER_BQ25720_VSYS_UVP_CUSTOM) &&
+	    !IS_ENABLED(CONFIG_CHARGER_BQ25720_IDCHG_DEG2_CUSTOM) &&
+	    !IS_ENABLED(CONFIG_CHARGER_BQ25720_IDCHG_TH2_CUSTOM))
+		return EC_SUCCESS;
+
+	rv = raw_read16(chgnum, BQ25720_REG_CHARGE_OPTION_4, &reg);
+	if (rv)
+		return rv;
+
+	if (IS_ENABLED(CONFIG_CHARGER_BQ25720_VSYS_UVP_CUSTOM))
+		reg = SET_CO4(VSYS_UVP, CONFIG_CHARGER_BQ25720_VSYS_UVP, reg);
+
+	if (IS_ENABLED(CONFIG_CHARGER_BQ25720_IDCHG_DEG2_CUSTOM))
+		reg = SET_CO4(IDCHG_DEG2, CONFIG_CHARGER_BQ25720_IDCHG_DEG2,
+			      reg);
+
+	if (IS_ENABLED(CONFIG_CHARGER_BQ25720_IDCHG_TH2_CUSTOM))
+		reg = SET_CO4(IDCHG_TH2, CONFIG_CHARGER_BQ25720_IDCHG_TH2, reg);
+
+	if (IS_ENABLED(CONFIG_CHARGER_BQ25720_PP_IDCHG2))
+		reg = SET_CO4_BY_NAME(PP_IDCHG2, ENABLE, reg);
+
+	return raw_write16(chgnum, BQ25720_REG_CHARGE_OPTION_4, reg);
+}
+
+static int bq25720_init_vmin_active_protection(int chgnum)
+{
+	int reg;
+	int rv;
+	int th2_dv;
+
+	if (!IS_ENABLED(CONFIG_CHARGER_BQ25720))
+		return EC_SUCCESS;
+
+	if (!IS_ENABLED(CONFIG_CHARGER_BQ25720_VSYS_TH2_CUSTOM))
+		return EC_SUCCESS;
+
+	rv = raw_read16(chgnum, BQ25720_REG_VMIN_ACTIVE_PROTECTION, &reg);
+	if (rv)
+		return rv;
+
+	/*
+	 * The default VSYS_TH2 is 5.9v for a 2S config. Boards may need
+	 * to increase this for stability. PROCHOT is asserted when the
+	 * threshold is reached.
+	 */
+	th2_dv = VMIN_AP_VSYS_TH2_TO_REG(CONFIG_CHARGER_BQ25720_VSYS_TH2_DV);
+	reg = SET_BQ_FIELD(BQ25720, VMIN_AP, VSYS_TH2, th2_dv, reg);
+
+	return raw_write16(chgnum, BQ25720_REG_VMIN_ACTIVE_PROTECTION, reg);
+}
+
 static void bq25710_init(int chgnum)
 {
 	int reg;
@@ -196,23 +539,35 @@ static void bq25710_init(int chgnum)
 	int rv;
 
 	/*
-	 * Reset registers to their default settings. There is no reset pin for
-	 * this chip so without a full power cycle, some registers may not be at
-	 * their default values. Note, need to save the POR value of
-	 * MIN_SYSTEM_VOLTAGE register prior to setting the reset so that the
-	 * correct value is preserved. In order to have the correct value read,
-	 * the bq25710 must not be in low power mode, otherwise the VDDA rail
-	 * may not be powered if AC is not connected. Note, this reset is only
-	 * required when running out of RO and not following sysjump to RW.
+	 * Reset registers to their default settings. There is no reset
+	 * pin for this chip so without a full power cycle, some
+	 * registers may not be at their default values. Note, need to
+	 * save the POR value of MIN_SYSTEM_VOLTAGE/VSYS_MIN register
+	 * prior to setting the reset so that the correct value is
+	 * preserved. In order to have the correct value read, the
+	 * bq25710 must not be in low power mode, otherwise the VDDA
+	 * rail may not be powered if AC is not connected. Note, this
+	 * reset is only required when running out of RO and not
+	 * following sysjump to RW.
 	 */
-	if (!system_is_in_rw()) {
+	if (!system_jumped_late()) {
 		rv = bq25710_set_low_power_mode(chgnum, 0);
 		/* Allow enough time for VDDA to be powered */
 		msleep(BQ25710_VDDA_STARTUP_DELAY_MSEC);
-		rv |= raw_read16(chgnum, BQ25710_REG_MIN_SYSTEM_VOLTAGE, &vsys);
+
+		if (IS_ENABLED(
+			    CONFIG_CHARGER_BQ25710_VSYS_MIN_VOLTAGE_CUSTOM)) {
+			vsys = min_system_voltage_to_reg(
+				CONFIG_CHARGER_BQ25710_VSYS_MIN_VOLTAGE_MV);
+		} else {
+			rv |= raw_read16(chgnum, BQ25710_REG_MIN_SYSTEM_VOLTAGE,
+					 &vsys);
+		}
+
 		rv |= raw_read16(chgnum, BQ25710_REG_CHARGE_OPTION_3, &reg);
 		if (!rv) {
-			reg |= BQ25710_CHARGE_OPTION_3_RESET_REG;
+			reg = SET_BQ_FIELD(BQ257X0, CHARGE_OPTION_3, RESET_REG,
+					   1, reg);
 			/* Set all registers to default values */
 			raw_write16(chgnum, BQ25710_REG_CHARGE_OPTION_3, reg);
 			/* Restore VSYS_MIN voltage to POR reset value */
@@ -223,48 +578,19 @@ static void bq25710_init(int chgnum)
 		bq25710_set_low_power_mode(chgnum, 1);
 	}
 
-	if (!raw_read16(chgnum, BQ25710_REG_PROCHOT_OPTION_1, &reg)) {
-		/* Disable VDPM prochot profile at initialization */
-		reg &= ~BQ25710_PROCHOT_PROFILE_VDPM;
-		/*
-		 * Enable PROCHOT to be asserted with VSYS min detection. Note
-		 * that when no battery is present, then VSYS will be set to the
-		 * value in register 0x3E (MinSysVoltage) which means that when
-		 * no battery is present prochot will continuosly be asserted.
-		 */
-		reg |= BQ25710_PROCHOT_PROFILE_VSYS;
-#ifdef CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA
-		/*
-		 * Set the IDCHG limit who's value is defined in the config
-		 * option in mA. Also, enable IDCHG trigger for prochot.
-		 */
-		reg &= ~BQ25710_PROCHOT_IDCHG_VTH_MASK;
-		/*
-		 * IDCHG limit is in 512 mA steps. Note there is a 128 mA offset
-		 * so the actual IDCHG limit will be the value stored in bits
-		 * 15:10 + 128 mA.
-		 */
-		reg |= ((CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA << 1) &
-			BQ25710_PROCHOT_IDCHG_VTH_MASK);
-		reg |= BQ25710_PROCHOT_PROFILE_IDCHG;
-#endif
-		raw_write16(chgnum, BQ25710_REG_PROCHOT_OPTION_1, reg);
-	}
+	bq257x0_init_charge_option_1(chgnum);
 
-	/* Reduce ILIM from default of 150% to 105% */
-	if (!raw_read16(chgnum, BQ25710_REG_PROCHOT_OPTION_0, &reg)) {
-		reg &= ~BQ25710_PROCHOT0_ILIM_VTH_MASK;
-		raw_write16(chgnum, BQ25710_REG_PROCHOT_OPTION_0, reg);
-	}
+	bq257x0_init_prochot_option_0(chgnum);
 
-	/*
-	 * Reduce peak power mode overload and relax cycle time from default 20
-	 * msec to the minimum of 5 msec.
-	 */
-	if (!raw_read16(chgnum, BQ25710_REG_CHARGE_OPTION_2, &reg)) {
-		reg &= ~BQ25710_CHARGE_OPTION_2_TMAX_MASK;
-		raw_write16(chgnum, BQ25710_REG_CHARGE_OPTION_2, reg);
-	}
+	bq257x0_init_prochot_option_1(chgnum);
+
+	bq257x0_init_charge_option_2(chgnum);
+
+	bq257x0_init_charge_option_3(chgnum);
+
+	bq257x0_init_charge_option_4(chgnum);
+
+	bq25720_init_vmin_active_protection(chgnum);
 }
 
 /* Charger interfaces */
@@ -299,7 +625,7 @@ static enum ec_error_list bq25710_get_status(int chgnum, int *status)
 	/* Default status */
 	*status = CHARGER_LEVEL_2;
 
-	if (option & BQ25710_CHARGE_OPTION_0_CHRG_INHIBIT)
+	if (option & BQ_FIELD_MASK(BQ257X0, CHARGE_OPTION_0, CHRG_INHIBIT))
 		*status |= CHARGER_CHARGE_INHIBITED;
 
 	return EC_SUCCESS;
@@ -315,9 +641,11 @@ static enum ec_error_list bq25710_set_mode(int chgnum, int mode)
 		return rv;
 
 	if (mode & CHARGER_CHARGE_INHIBITED)
-		option |= BQ25710_CHARGE_OPTION_0_CHRG_INHIBIT;
+		option = SET_BQ_FIELD(BQ257X0, CHARGE_OPTION_0, CHRG_INHIBIT, 1,
+				      option);
 	else
-		option &= ~BQ25710_CHARGE_OPTION_0_CHRG_INHIBIT;
+		option = SET_BQ_FIELD(BQ257X0, CHARGE_OPTION_0, CHRG_INHIBIT, 0,
+				      option);
 
 	return bq25710_set_option(chgnum, option);
 }
@@ -350,7 +678,7 @@ static enum ec_error_list bq25710_get_current(int chgnum, int *current)
 static enum ec_error_list bq25710_set_current(int chgnum, int current)
 {
 	return raw_write16(chgnum, BQ25710_REG_CHARGE_CURRENT,
-		CHARGING_CURRENT_TO_REG(current));
+			   CHARGING_CURRENT_TO_REG(current));
 }
 
 /* Get/set charge voltage limit in mV */
@@ -374,24 +702,26 @@ static enum ec_error_list bq25710_discharge_on_ac(int chgnum, int enable)
 		return rv;
 
 	if (enable)
-		option |= BQ25710_CHARGE_OPTION_0_EN_LEARN;
+		option = SET_BQ_FIELD(BQ257X0, CHARGE_OPTION_0, EN_LEARN, 1,
+				      option);
 	else
-		option &= ~BQ25710_CHARGE_OPTION_0_EN_LEARN;
+		option = SET_BQ_FIELD(BQ257X0, CHARGE_OPTION_0, EN_LEARN, 0,
+				      option);
 
 	return bq25710_set_option(chgnum, option);
 }
 
-static enum ec_error_list bq25710_set_input_current(int chgnum,
-						    int input_current)
+static enum ec_error_list bq25710_set_input_current_limit(int chgnum,
+							  int input_current)
 {
-	int num_steps = INPUT_CURRENT_TO_REG(input_current);
+	int num_steps = iin_host_current_to_reg(input_current);
 
-	return raw_write16(chgnum, BQ25710_REG_IIN_HOST, num_steps <<
-			  BQ25710_CHARGE_IIN_BIT_0FFSET);
+	return raw_write16(chgnum, BQ25710_REG_IIN_HOST,
+			   num_steps << BQ257X0_IIN_HOST_CURRENT_SHIFT);
 }
 
-static enum ec_error_list bq25710_get_input_current(int chgnum,
-						    int *input_current)
+static enum ec_error_list bq25710_get_input_current_limit(int chgnum,
+							  int *input_current)
 {
 	int rv, reg;
 
@@ -403,9 +733,8 @@ static enum ec_error_list bq25710_get_input_current(int chgnum,
 	 */
 	rv = raw_read16(chgnum, BQ25710_REG_IIN_DPM, &reg);
 	if (!rv)
-		*input_current =
-			REG_TO_INPUT_CURRENT((reg >>
-					      BQ25710_CHARGE_IIN_BIT_0FFSET));
+		*input_current = iin_dpm_reg_to_current(
+			reg >> BQ257X0_IIN_DPM_CURRENT_SHIFT);
 
 	return rv;
 }
@@ -421,12 +750,41 @@ static enum ec_error_list bq25710_device_id(int chgnum, int *id)
 }
 
 #ifdef CONFIG_USB_PD_VBUS_MEASURE_CHARGER
+
+#if defined(CONFIG_CHARGER_BQ25720)
+
+static int reg_adc_vbus_to_mv(int reg)
+{
+	/*
+	 * LSB => 96mV, no DC offset.
+	 */
+	return reg * BQ25720_ADC_VBUS_STEP_MV;
+}
+
+#elif defined(CONFIG_CHARGER_BQ25710)
+
+static int reg_adc_vbus_to_mv(int reg)
+{
+	/*
+	 * LSB => 64mV.
+	 * Return 0 when VBUS <= 3.2V as ADC can't measure it.
+	 */
+	return reg ? (reg * BQ25710_ADC_VBUS_STEP_MV +
+		      BQ25710_ADC_VBUS_BASE_MV) :
+		     0;
+}
+
+#else
+#error Only the BQ25720 and BQ25710 are supported by bq25710 driver.
+#endif
+
 static enum ec_error_list bq25710_get_vbus_voltage(int chgnum, int port,
 						   int *voltage)
 {
 	int reg, rv;
 
-	rv = bq25710_adc_start(chgnum, BQ25710_ADC_OPTION_EN_ADC_VBUS);
+	rv = bq25710_adc_start(chgnum,
+			       BQ_FIELD_MASK(BQ257X0, ADC_OPTION, EN_ADC_VBUS));
 	if (rv)
 		goto error;
 
@@ -435,13 +793,8 @@ static enum ec_error_list bq25710_get_vbus_voltage(int chgnum, int port,
 	if (rv)
 		goto error;
 
-	reg >>= BQ25710_ADC_VBUS_STEP_BIT_OFFSET;
-	/*
-	 * LSB => 64mV.
-	 * Return 0 when VBUS <= 3.2V as ADC can't measure it.
-	 */
-	*voltage = reg ?
-	       (reg * BQ25710_ADC_VBUS_STEP_MV + BQ25710_ADC_VBUS_BASE_MV) : 0;
+	reg >>= BQ257X0_ADC_VBUS_PSYS_VBUS_SHIFT;
+	*voltage = reg_adc_vbus_to_mv(reg);
 
 error:
 	if (rv)
@@ -462,6 +815,14 @@ static enum ec_error_list bq25710_set_option(int chgnum, int option)
 	return raw_write16(chgnum, BQ25710_REG_CHARGE_OPTION_0, option);
 }
 
+int bq25710_set_min_system_voltage(int chgnum, int mv)
+{
+	int reg;
+
+	reg = min_system_voltage_to_reg(mv);
+	return raw_write16(chgnum, BQ25710_REG_MIN_SYSTEM_VOLTAGE, reg);
+}
+
 #ifdef CONFIG_CHARGE_RAMP_HW
 
 static void bq25710_chg_ramp_handle(void)
@@ -478,7 +839,8 @@ static void bq25710_chg_ramp_handle(void)
 	 */
 	ramp_curr = chg_ramp_get_current_limit();
 	if (chg_ramp_is_stable()) {
-		if (ramp_curr && !charger_set_input_current(chgnum, ramp_curr))
+		if (ramp_curr &&
+		    !charger_set_input_current_limit(chgnum, ramp_curr))
 			CPRINTF("bq25710: stable ramp current=%d\n", ramp_curr);
 	} else {
 		CPRINTF("bq25710: ICO stall, ramp current=%d\n", ramp_curr);
@@ -517,27 +879,31 @@ static enum ec_error_list bq25710_set_hw_ramp(int chgnum, int enable)
 
 		/* Set InputVoltage register to BC1.2 minimum ramp voltage */
 		rv = raw_write16(chgnum, BQ25710_REG_INPUT_VOLTAGE,
-			BQ25710_BC12_MIN_VOLTAGE_MV);
+				 BQ25710_BC12_MIN_VOLTAGE_MV);
 		if (rv)
 			return rv;
 
 		/*  Enable ICO algorithm */
-		option3_reg |= BQ25710_CHARGE_OPTION_3_EN_ICO_MODE;
+		option3_reg = SET_BQ_FIELD(BQ257X0, CHARGE_OPTION_3,
+					   EN_ICO_MODE, 1, option3_reg);
 
 		/* 0b: Input current limit is set by BQ25710_REG_IIN_HOST */
-		option2_reg &= ~BQ25710_CHARGE_OPTION_2_EN_EXTILIM;
+		option2_reg = SET_BQ_FIELD(BQ257X0, CHARGE_OPTION_2, EN_EXTILIM,
+					   0, option2_reg);
 
 		/* Charge ramp may take up to 2s to settle down */
 		hook_call_deferred(&bq25710_chg_ramp_handle_data, (4 * SECOND));
 	} else {
 		/*  Disable ICO algorithm */
-		option3_reg &= ~BQ25710_CHARGE_OPTION_3_EN_ICO_MODE;
+		option3_reg = SET_BQ_FIELD(BQ257X0, CHARGE_OPTION_3,
+					   EN_ICO_MODE, 0, option3_reg);
 
 		/*
 		 * 1b: Input current limit is set by the lower value of
 		 * ILIM_HIZ pin and BQ25710_REG_IIN_HOST
 		 */
-		option2_reg |= BQ25710_CHARGE_OPTION_2_EN_EXTILIM;
+		option2_reg = SET_BQ_FIELD(BQ257X0, CHARGE_OPTION_2, EN_EXTILIM,
+					   1, option2_reg);
 	}
 
 	rv = raw_write16(chgnum, BQ25710_REG_CHARGE_OPTION_2, option2_reg);
@@ -553,7 +919,7 @@ static int bq25710_ramp_is_stable(int chgnum)
 	if (raw_read16(chgnum, BQ25710_REG_CHARGER_STATUS, &reg))
 		return 0;
 
-	return reg & BQ25710_CHARGE_STATUS_ICO_DONE;
+	return reg & BQ_FIELD_MASK(BQ257X0, CHARGER_STATUS, ICO_DONE);
 }
 
 static int bq25710_ramp_get_current_limit(int chgnum)
@@ -567,8 +933,7 @@ static int bq25710_ramp_get_current_limit(int chgnum)
 		return 0;
 	}
 
-	return ((reg >> BQ25710_IIN_DPM_BIT_SHIFT) * BQ25710_IIN_DPM_STEP_MA +
-		BQ25710_IIN_DPM_STEP_MA);
+	return iin_dpm_reg_to_current(reg >> BQ257X0_IIN_DPM_CURRENT_SHIFT);
 }
 #endif /* CONFIG_CHARGE_RAMP_HW */
 
@@ -581,7 +946,6 @@ static void bq25710_chipset_startup(void)
 DECLARE_HOOK(HOOK_CHIPSET_STARTUP, bq25710_chipset_startup, HOOK_PRIO_DEFAULT);
 DECLARE_HOOK(HOOK_CHIPSET_RESUME, bq25710_chipset_startup, HOOK_PRIO_DEFAULT);
 
-
 /* Called on AP S0 -> S0iX/S3 or S3 -> S5 transition */
 static void bq25710_chipset_suspend(void)
 {
@@ -592,24 +956,16 @@ DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, bq25710_chipset_suspend, HOOK_PRIO_DEFAULT);
 #endif
 
 #ifdef CONFIG_CMD_CHARGER_DUMP
-static int console_bq25710_dump_regs(int argc, char **argv)
+static void console_bq25710_dump_regs(int chgnum)
 {
 	int i;
 	int val;
-	int chgnum = 0;
-	char *e;
 
 	/* Dump all readable registers on bq25710. */
 	static const uint8_t regs[] = {
 		BQ25710_REG_CHARGE_OPTION_0,
 		BQ25710_REG_CHARGE_CURRENT,
 		BQ25710_REG_MAX_CHARGE_VOLTAGE,
-		BQ25710_REG_CHARGE_OPTION_1,
-		BQ25710_REG_CHARGE_OPTION_2,
-		BQ25710_REG_CHARGE_OPTION_3,
-		BQ25710_REG_PROCHOT_OPTION_0,
-		BQ25710_REG_PROCHOT_OPTION_1,
-		BQ25710_REG_ADC_OPTION,
 		BQ25710_REG_CHARGER_STATUS,
 		BQ25710_REG_PROCHOT_STATUS,
 		BQ25710_REG_IIN_DPM,
@@ -617,7 +973,16 @@ static int console_bq25710_dump_regs(int argc, char **argv)
 		BQ25710_REG_ADC_IBAT,
 		BQ25710_REG_ADC_CMPIN_IIN,
 		BQ25710_REG_ADC_VSYS_VBAT,
+		BQ25710_REG_CHARGE_OPTION_1,
+		BQ25710_REG_CHARGE_OPTION_2,
+		BQ25710_REG_CHARGE_OPTION_3,
+		BQ25710_REG_PROCHOT_OPTION_0,
 		BQ25710_REG_PROCHOT_OPTION_1,
+		BQ25710_REG_ADC_OPTION,
+#ifdef CONFIG_CHARGER_BQ25720
+		BQ25720_REG_CHARGE_OPTION_4,
+		BQ25720_REG_VMIN_ACTIVE_PROTECTION,
+#endif
 		BQ25710_REG_OTG_VOLTAGE,
 		BQ25710_REG_OTG_CURRENT,
 		BQ25710_REG_INPUT_VOLTAGE,
@@ -626,25 +991,13 @@ static int console_bq25710_dump_regs(int argc, char **argv)
 		BQ25710_REG_MANUFACTURER_ID,
 		BQ25710_REG_DEVICE_ADDRESS,
 	};
-	if (argc >= 2) {
-		chgnum = strtoi(argv[1], &e, 10);
-		if (*e)
-			return EC_ERROR_PARAM1;
-	}
 
 	for (i = 0; i < ARRAY_SIZE(regs); ++i) {
 		if (raw_read16(chgnum, regs[i], &val))
 			continue;
 		ccprintf("BQ25710 REG 0x%02x:  0x%04x\n", regs[i], val);
 	}
-
-
-	return 0;
 }
-DECLARE_CONSOLE_COMMAND(charger_dump, console_bq25710_dump_regs,
-			"charger_dump <chgnum>",
-			"Dump all charger registers");
-
 #endif /* CONFIG_CMD_CHARGER_DUMP */
 
 const struct charger_drv bq25710_drv = {
@@ -661,13 +1014,18 @@ const struct charger_drv bq25710_drv = {
 	.set_voltage = &bq25710_set_voltage,
 	.discharge_on_ac = &bq25710_discharge_on_ac,
 	.get_vbus_voltage = &bq25710_get_vbus_voltage,
-	.set_input_current = &bq25710_set_input_current,
-	.get_input_current = &bq25710_get_input_current,
+	.set_input_current_limit = &bq25710_set_input_current_limit,
+	.get_input_current_limit = &bq25710_get_input_current_limit,
 	.manufacturer_id = &bq25710_manufacturer_id,
 	.device_id = &bq25710_device_id,
 	.get_option = &bq25710_get_option,
 	.set_option = &bq25710_set_option,
+#ifdef CONFIG_CHARGE_RAMP_HW
 	.set_hw_ramp = &bq25710_set_hw_ramp,
 	.ramp_is_stable = &bq25710_ramp_is_stable,
 	.ramp_get_current_limit = &bq25710_ramp_get_current_limit,
+#endif /* CONFIG_CHARGE_RAMP_HW */
+#ifdef CONFIG_CMD_CHARGER_DUMP
+	.dump_registers = &console_bq25710_dump_regs,
+#endif
 };
diff --git a/driver/charger/bq25710.h b/driver/charger/bq25710.h
index 37facb7831..078160e66e 100644
--- a/driver/charger/bq25710.h
+++ b/driver/charger/bq25710.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,88 +11,67 @@
 /* SMBUS Interface */
 #define BQ25710_SMBUS_ADDR1_FLAGS 0x09
 
-#define BQ25710_BC12_MIN_VOLTAGE_MV	1408
+#define BQ25710_BC12_MIN_VOLTAGE_MV 1408
 
 /* Registers */
-#define BQ25710_REG_CHARGE_OPTION_0		0x12
-#define BQ25710_REG_CHARGE_CURRENT		0x14
-#define BQ25710_REG_MAX_CHARGE_VOLTAGE		0x15
-#define BQ25710_REG_CHARGE_OPTION_1		0x30
-#define BQ25710_REG_CHARGE_OPTION_2		0x31
-#define BQ25710_REG_CHARGE_OPTION_3		0x32
-#define BQ25710_REG_PROCHOT_OPTION_0		0x33
-#define BQ25710_REG_PROCHOT_OPTION_1		0x34
-#define BQ25710_REG_ADC_OPTION			0x35
-#define BQ25710_REG_CHARGER_STATUS		0x20
-#define BQ25710_REG_PROCHOT_STATUS		0x21
-#define BQ25710_REG_IIN_DPM			0x22
-#define BQ25710_REG_ADC_VBUS_PSYS		0x23
-#define BQ25710_REG_ADC_IBAT			0x24
-#define BQ25710_REG_ADC_CMPIN_IIN		0x25
-#define BQ25710_REG_ADC_VSYS_VBAT		0x2C
-#define BQ25710_REG_PROCHOT_OPTION_1		0x34
-#define BQ25710_REG_OTG_VOLTAGE			0x3B
-#define BQ25710_REG_OTG_CURRENT			0x3C
-#define BQ25710_REG_INPUT_VOLTAGE		0x3D
-#define BQ25710_REG_MIN_SYSTEM_VOLTAGE		0x3E
-#define BQ25710_REG_IIN_HOST			0x3F
-#define BQ25710_REG_MANUFACTURER_ID		0xFE
-#define BQ25710_REG_DEVICE_ADDRESS		0xFF
-
-/* ChargeOption0 Register */
-#define BQ25710_CHARGE_OPTION_0_LOW_POWER_MODE	BIT(15)
-#define BQ25710_CHARGE_OPTION_0_IDPM_AUTO_DIS	BIT(12)
-#define BQ25710_CHARGE_OPTION_0_EN_LEARN	BIT(5)
-#define BQ25710_CHARGE_OPTION_0_EN_IDPM		BIT(1)
-#define BQ25710_CHARGE_OPTION_0_CHRG_INHIBIT	BIT(0)
-
-/* ChargeOption2 Register */
-#define BQ25710_CHARGE_OPTION_2_EN_EXTILIM	BIT(7)
-#define BQ25710_CHARGE_OPTION_2_TMAX_SHIFT	8
-#define BQ25710_CHARGE_OPTION_2_TMAX_MASK (0x3 << \
-					   BQ25710_CHARGE_OPTION_2_TMAX_SHIFT)
-
-/* ChargeOption3 Register */
-#define BQ25710_CHARGE_OPTION_3_RESET_REG	BIT(14)
-#define BQ25710_CHARGE_OPTION_3_EN_ICO_MODE	BIT(11)
-
-/* ChargeStatus Register */
-#define BQ25710_CHARGE_STATUS_ICO_DONE		BIT(14)
-
-/* IIN_DPM Register */
-#define BQ25710_CHARGE_IIN_BIT_0FFSET		8
-#define BQ25710_CHARGE_MA_PER_STEP		50
-
-/* ADCOption Register */
-#define BQ25710_ADC_OPTION_ADC_START		BIT(14)
-#define BQ25710_ADC_OPTION_EN_ADC_VBUS		BIT(6)
-#define BQ25710_ADC_OPTION_EN_ADC_IIN		BIT(4)
-#define BQ25710_ADC_OPTION_EN_ADC_ALL		0xFF
+#define BQ25710_REG_CHARGE_OPTION_0 0x12
+#define BQ25710_REG_CHARGE_CURRENT 0x14
+#define BQ25710_REG_MAX_CHARGE_VOLTAGE 0x15
+#define BQ25710_REG_CHARGER_STATUS 0x20
+#define BQ25710_REG_PROCHOT_STATUS 0x21
+#define BQ25710_REG_IIN_DPM 0x22
+#define BQ25710_REG_ADC_VBUS_PSYS 0x23
+#define BQ25710_REG_ADC_IBAT 0x24
+#define BQ25710_REG_ADC_CMPIN_IIN 0x25
+#define BQ25710_REG_ADC_VSYS_VBAT 0x26
+#define BQ25710_REG_CHARGE_OPTION_1 0x30
+#define BQ25710_REG_CHARGE_OPTION_2 0x31
+#define BQ25710_REG_CHARGE_OPTION_3 0x32
+#define BQ25710_REG_PROCHOT_OPTION_0 0x33
+#define BQ25710_REG_PROCHOT_OPTION_1 0x34
+#define BQ25710_REG_ADC_OPTION 0x35
+#define BQ25720_REG_CHARGE_OPTION_4 0x36
+#define BQ25720_REG_VMIN_ACTIVE_PROTECTION 0x37
+#define BQ25710_REG_OTG_VOLTAGE 0x3B
+#define BQ25710_REG_OTG_CURRENT 0x3C
+#define BQ25710_REG_INPUT_VOLTAGE 0x3D
+#define BQ25710_REG_MIN_SYSTEM_VOLTAGE 0x3E
+#define BQ25710_REG_IIN_HOST 0x3F
+#define BQ25710_REG_MANUFACTURER_ID 0xFE
+#define BQ25710_REG_DEVICE_ADDRESS 0xFF
+
+/* ADC conversion time ins ms */
+#if defined(CONFIG_CHARGER_BQ25720)
+#define BQ25710_ADC_OPTION_ADC_CONV_MS 25
+#elif defined(CONFIG_CHARGER_BQ25710)
+#define BQ25710_ADC_OPTION_ADC_CONV_MS 10
+#else
+#error Only the BQ25720 and BQ25710 are supported by bq25710 driver.
+#endif
 
 /* ADCVBUS/PSYS Register */
-#define BQ25710_ADC_VBUS_STEP_MV		64
-#define BQ25710_ADC_VBUS_BASE_MV		3200
-#define BQ25710_ADC_VBUS_STEP_BIT_OFFSET	8
-
-/* ADCIIN Register */
-#define BQ25710_ADC_IIN_STEP_MA			50
-#define BQ25710_ADC_IIN_STEP_BIT_OFFSET		8
-
-/* ProchotOption0 Register */
-#define BQ25710_PROCHOT0_ILIM_VTH_SHIFT 11
-#define BQ25710_PROCHOT0_ILIM_VTH_MASK	(0x1f << \
-					 BQ25710_PROCHOT0_ILIM_VTH_SHIFT)
-
-/* ProchotOption1 Register */
-#define BQ25710_PROCHOT_PROFILE_VDPM		BIT(7)
-#define BQ25710_PROCHOT_PROFILE_IDCHG		BIT(3)
-#define BQ25710_PROCHOT_PROFILE_VSYS		BIT(2)
-#define BQ25710_PROCHOT_IDCHG_VTH_MASK		0xFC00
-
-/* IIN_DPM Register */
-#define BQ25710_IIN_DPM_BIT_SHIFT		8
-#define BQ25710_IIN_DPM_STEP_MA			50
+#if defined(CONFIG_CHARGER_BQ25720)
+#define BQ25720_ADC_VBUS_STEP_MV 96
+#elif defined(CONFIG_CHARGER_BQ25710)
+#define BQ25710_ADC_VBUS_STEP_MV 64
+#define BQ25710_ADC_VBUS_BASE_MV 3200
+#else
+#error Only the BQ25720 and BQ25710 are supported by bq25710 driver.
+#endif
+
+/* Min System Voltage Register */
+#define BQ25710_MIN_SYSTEM_VOLTAGE_STEP_MV 256
+#define BQ25720_VSYS_MIN_VOLTAGE_STEP_MV 100
 
 extern const struct charger_drv bq25710_drv;
 
+/**
+ * Set VSYS_MIN
+ *
+ * @param chgnum: Index into charger chips
+ * @param mv: min system voltage in mV
+ * @return EC_SUCCESS or error
+ */
+int bq25710_set_min_system_voltage(int chgnum, int mv);
+
 #endif /* __CROS_EC_BQ25710_H */
diff --git a/driver/charger/bq257x0_regs.h b/driver/charger/bq257x0_regs.h
new file mode 100644
index 0000000000..69b218436a
--- /dev/null
+++ b/driver/charger/bq257x0_regs.h
@@ -0,0 +1,301 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * TI bq257x0 battery charger driver.
+ */
+
+#ifndef __CROS_EC_BQ257X0_REGS_H
+#define __CROS_EC_BQ257X0_REGS_H
+
+#include "bq25710.h"
+
+/*
+ * BQ257x0 family register definitions.
+ *
+ * Common registers are prefixed with BQ257X0, chip specific registers
+ * and registers with incompatible definitions are prefixed with
+ * BQ25710, BQ25720, etc.
+ */
+
+/*
+ * ChargerStatus Register (0x20)
+ */
+#define BQ257X0_CHARGER_STATUS_ICO_DONE_SHIFT 14
+#define BQ257X0_CHARGER_STATUS_ICO_DONE_BITS 1
+
+/*
+ * ChargeOption0 Register (0x12)
+ */
+#define BQ257X0_CHARGE_OPTION_0_EN_LWPWR_SHIFT 15
+#define BQ257X0_CHARGE_OPTION_0_EN_LWPWR_BITS 1
+#define BQ257X0_CHARGE_OPTION_0_EN_LEARN_SHIFT 5
+#define BQ257X0_CHARGE_OPTION_0_EN_LEARN_BITS 1
+#define BQ257X0_CHARGE_OPTION_0_IADP_GAIN_SHIFT 4
+#define BQ257X0_CHARGE_OPTION_0_IADP_GAIN_BITS 1
+#define BQ257X0_CHARGE_OPTION_0_EN_IDPM_SHIFT 1
+#define BQ257X0_CHARGE_OPTION_0_EN_IDPM_BITS 1
+#define BQ257X0_CHARGE_OPTION_0_CHRG_INHIBIT_SHIFT 0
+#define BQ257X0_CHARGE_OPTION_0_CHRG_INHIBIT_BITS 1
+
+/*
+ * ChargeOption1 Register (0x30)
+ */
+#define BQ25710_CHARGE_OPTION_1_EN_PSYS_SHIFT 12
+#define BQ25710_CHARGE_OPTION_1_EN_PSYS_BITS 1
+
+#define BQ25720_CHARGE_OPTION_1_PSYS_CONFIG_SHIFT 12
+#define BQ25720_CHARGE_OPTION_1_PSYS_CONFIG_BITS 2
+#define BQ25720_CHARGE_OPTION_1_PSYS_CONFIG__PBUS_PBAT 0
+#define BQ25720_CHARGE_OPTION_1_PSYS_CONFIG__OFF 3
+
+#define BQ257X0_CHARGE_OPTION_1_CMP_REF_SHIFT 7
+#define BQ257X0_CHARGE_OPTION_1_CMP_REF_BITS 1
+#define BQ257X0_CHARGE_OPTION_1_CMP_REF__2P3 0
+#define BQ257X0_CHARGE_OPTION_1_CMP_REF__1P2 1
+
+#define BQ257X0_CHARGE_OPTION_1_CMP_POL_SHIFT 6
+#define BQ257X0_CHARGE_OPTION_1_CMP_POL_BITS 1
+#define BQ257X0_CHARGE_OPTION_1_CMP_POL__INTERNAL 0
+#define BQ257X0_CHARGE_OPTION_1_CMP_POL__EXTERNAL 1
+
+/*
+ * ChargeOption2 Register (0x31)
+ */
+#define BQ257X0_CHARGE_OPTION_2_PKPWR_TOVLD_DEG_SHIFT 14
+#define BQ257X0_CHARGE_OPTION_2_PKPWR_TOVLD_DEG_BITS 2
+#define BQ25720_CHARGE_OPTION_2_PKPWR_TOVLD_DEG__10MS 3
+
+#define BQ257X0_CHARGE_OPTION_2_PKPWR_TMAX_SHIFT 8
+#define BQ257X0_CHARGE_OPTION_2_PKPWR_TMAX_BITS 2
+
+#define BQ257X0_CHARGE_OPTION_2_EN_EXTILIM_SHIFT 7
+#define BQ257X0_CHARGE_OPTION_2_EN_EXTILIM_BITS 1
+
+#define BQ257X0_CHARGE_OPTION_2_EN_ACOC_SHIFT 3
+#define BQ257X0_CHARGE_OPTION_2_EN_ACOC_BITS 1
+#define BQ257X0_CHARGE_OPTION_2_EN_ACOC__DISABLE 0
+#define BQ257X0_CHARGE_OPTION_2_EN_ACOC__ENABLE 1
+
+#define BQ257X0_CHARGE_OPTION_2_ACOC_VTH_SHIFT 2
+#define BQ257X0_CHARGE_OPTION_2_ACOC_VTH_BITS 1
+#define BQ257X0_CHARGE_OPTION_2_ACOC_VTH__1P33 0
+#define BQ257X0_CHARGE_OPTION_2_ACOC_VTH__2P00 1
+
+#define BQ257X0_CHARGE_OPTION_2_BATOC_VTH_SHIFT 0
+#define BQ257X0_CHARGE_OPTION_2_BATOC_VTH_BITS 1
+#define BQ257X0_CHARGE_OPTION_2_BATOC_VTH__1P33 0
+#define BQ257X0_CHARGE_OPTION_2_BATOC_VTH__2P00 1
+
+/*
+ * ChargeOption3 Register (0x32)
+ */
+#define BQ257X0_CHARGE_OPTION_3_RESET_REG_SHIFT 14
+#define BQ257X0_CHARGE_OPTION_3_RESET_REG_BITS 1
+
+#define BQ257X0_CHARGE_OPTION_3_EN_ICO_MODE_SHIFT 11
+#define BQ257X0_CHARGE_OPTION_3_EN_ICO_MODE_BITS 1
+
+#define BQ257X0_CHARGE_OPTION_3_IL_AVG_SHIFT 3
+#define BQ257X0_CHARGE_OPTION_3_IL_AVG_BITS 2
+#define BQ257X0_CHARGE_OPTION_3_IL_AVG__10A 1
+
+/*
+ * ChargeOption4 Register (0x36)
+ */
+#define BQ25720_CHARGE_OPTION_4_VSYS_UVP_SHIFT 13
+#define BQ25720_CHARGE_OPTION_4_VSYS_UVP_BITS 3
+#define BQ25720_CHARGE_OPTION_4_VSYS_UVP__2P4 0
+#define BQ25720_CHARGE_OPTION_4_VSYS_UVP__3P2 1
+#define BQ25720_CHARGE_OPTION_4_VSYS_UVP__4P0 2
+#define BQ25720_CHARGE_OPTION_4_VSYS_UVP__4P8 3
+#define BQ25720_CHARGE_OPTION_4_VSYS_UVP__5P6 4
+#define BQ25720_CHARGE_OPTION_4_VSYS_UVP__6P4 5
+#define BQ25720_CHARGE_OPTION_4_VSYS_UVP__7P2 6
+#define BQ25720_CHARGE_OPTION_4_VSYS_UVP__8P0 7
+
+#define BQ25720_CHARGE_OPTION_4_IDCHG_DEG2_SHIFT 6
+#define BQ25720_CHARGE_OPTION_4_IDCHG_DEG2_BITS 2
+#define BQ25720_CHARGE_OPTION_4_IDCHG_DEG2__1P6MS 1
+#define BQ25720_CHARGE_OPTION_4_IDCHG_DEG2__12MS 3
+
+#define BQ25720_CHARGE_OPTION_4_IDCHG_TH2_SHIFT 3
+#define BQ25720_CHARGE_OPTION_4_IDCHG_TH2_BITS 3
+#define BQ25720_CHARGE_OPTION_4_IDCHG_TH2__1P25 0
+#define BQ25720_CHARGE_OPTION_4_IDCHG_TH2__1P5 1
+
+#define BQ25720_CHARGE_OPTION_4_PP_IDCHG2_SHIFT 2
+#define BQ25720_CHARGE_OPTION_4_PP_IDCHG2_BITS 1
+#define BQ25720_CHARGE_OPTION_4_PP_IDCHG2__DISABLE 0
+#define BQ25720_CHARGE_OPTION_4_PP_IDCHG2__ENABLE 1
+
+/*
+ * Vmin Active Protection Register (0x37)
+ */
+#define BQ25720_VMIN_AP_VSYS_TH2_SHIFT 2
+#define BQ25720_VMIN_AP_VSYS_TH2_BITS 6
+
+/*
+ * ProchotOption0 Register (0x33)
+ */
+#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH_SHIFT 11
+#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH_BITS 5
+#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH__1P10 1
+#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH__1P40 7
+#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH__1P50 9
+#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH__2P30 25
+#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH__2P50 26
+#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH__4P50 30
+#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH__NA 31
+
+/*
+ * ProchotOption1 Register (0x34)
+ */
+#define BQ257X0_PROCHOT_OPTION_1_IDCHG_VTH_SHIFT 10
+#define BQ257X0_PROCHOT_OPTION_1_IDCHG_VTH_BITS 6
+
+#define BQ257X0_PROCHOT_OPTION_1_PP_COMP_SHIFT 6
+#define BQ257X0_PROCHOT_OPTION_1_PP_COMP_BITS 1
+#define BQ257X0_PROCHOT_OPTION_1_PP_COMP__DISABLE 0
+#define BQ257X0_PROCHOT_OPTION_1_PP_COMP__ENABLE 1
+
+#define BQ257X0_PROCHOT_OPTION_1_PP_INOM_SHIFT 4
+#define BQ257X0_PROCHOT_OPTION_1_PP_INOM_BITS 1
+#define BQ257X0_PROCHOT_OPTION_1_PP_INOM__DISABLE 0
+#define BQ257X0_PROCHOT_OPTION_1_PP_INOM__ENABLE 1
+
+#define BQ257X0_PROCHOT_OPTION_1_PP_IDCHG_SHIFT 3
+#define BQ257X0_PROCHOT_OPTION_1_PP_IDCHG_BITS 1
+#define BQ257X0_PROCHOT_OPTION_1_PP_IDCHG__DISABLE 0
+#define BQ257X0_PROCHOT_OPTION_1_PP_IDCHG__ENABLE 1
+
+#define BQ257X0_PROCHOT_OPTION_1_PP_VDPM_SHIFT 7
+#define BQ257X0_PROCHOT_OPTION_1_PP_VDPM_BITS 1
+#define BQ257X0_PROCHOT_OPTION_1_PP_VDPM__DISABLE 0
+#define BQ257X0_PROCHOT_OPTION_1_PP_VDPM__ENABLE 1
+
+#define BQ257X0_PROCHOT_OPTION_1_PP_VSYS_SHIFT 2
+#define BQ257X0_PROCHOT_OPTION_1_PP_VSYS_BITS 1
+#define BQ257X0_PROCHOT_OPTION_1_PP_VSYS__DISABLE 0
+#define BQ257X0_PROCHOT_OPTION_1_PP_VSYS__ENABLE 1
+
+#define BQ257X0_PROCHOT_OPTION_1_PP_BATPRES_SHIFT 1
+#define BQ257X0_PROCHOT_OPTION_1_PP_BATPRES_BITS 1
+#define BQ257X0_PROCHOT_OPTION_1_PP_BATPRES__DISABLE 0
+#define BQ257X0_PROCHOT_OPTION_1_PP_BATPRES__ENABLE 1
+
+#define BQ257X0_PROCHOT_OPTION_1_PP_ACOK_SHIFT 0
+#define BQ257X0_PROCHOT_OPTION_1_PP_ACOK_BITS 1
+#define BQ257X0_PROCHOT_OPTION_1_PP_ACOK__DISABLE 0
+#define BQ257X0_PROCHOT_OPTION_1_PP_ACOK__ENABLE 1
+
+/*
+ * ChargeCurrent Register (0x14)
+ */
+#define BQ257X0_CHARGE_CURRENT_CHARGE_CURRENT_SHIFT 6
+#define BQ257X0_CHARGE_CURRENT_CHARGE_CURRENT_BITS 7
+
+/*
+ * IIN_DPM Register (0x22)
+ */
+#define BQ257X0_IIN_DPM_CURRENT_SHIFT 8
+#define BQ257X0_IIN_DPM_CURRENT_BITS 7
+#define BQ257X0_IIN_DPM_CURRENT_STEP_MA 50
+
+/*
+ * IIN_HOST Register (0x3f)
+ */
+#define BQ257X0_IIN_HOST_CURRENT_SHIFT 8
+#define BQ257X0_IIN_HOST_CURRENT_BITS 7
+#define BQ257X0_IIN_HOST_CURRENT_STEP_MA 50
+
+/*
+ * ADCOption Register (0x35)
+ */
+#define BQ257X0_ADC_OPTION_ADC_START_SHIFT 14
+#define BQ257X0_ADC_OPTION_ADC_START_BITS 1
+#define BQ257X0_ADC_OPTION_ADC_FULLSCALE_SHIFT 13
+#define BQ257X0_ADC_OPTION_ADC_FULLSCALE_BITS 1
+
+#define BQ257X0_ADC_OPTION_EN_ADC_VBUS_SHIFT 6
+#define BQ257X0_ADC_OPTION_EN_ADC_VBUS_BITS 1
+#define BQ257X0_ADC_OPTION_EN_ADC_ALL GENMASK(7, 0)
+
+/*
+ * ADCVBUS/PSYS Register (0x23)
+ */
+#define BQ257X0_ADC_VBUS_PSYS_VBUS_SHIFT 8
+#define BQ257X0_ADC_VBUS_PSYS_VBUS_BITS 8
+#define BQ257X0_ADC_VBUS_PSYS_PSYS_SHIFT 0
+#define BQ257X0_ADC_VBUS_PSYS_PSYS_BITS 8
+
+/*
+ * VSYS_MIN Register (0x3e)
+ */
+#define BQ25710_MIN_SYSTEM_VOLTAGE_SHIFT 8
+#define BQ25710_MIN_SYSTEM_VOLTAGE_BITS 6
+#define BQ25720_VSYS_MIN_VOLTAGE_SHIFT 8
+#define BQ25720_VSYS_MIN_VOLTAGE_BITS 8
+
+/*
+ * BQ257x0 register field accessor macros.
+ */
+
+/*
+ * Returns the bitmask of a register field.
+ *
+ *  _chip	chip name
+ *  _reg	chip register name
+ *  _field	register field name
+ */
+
+#define BQ_FIELD_MASK(_chip, _reg, _field)              \
+	GENMASK((_chip##_##_reg##_##_field##_SHIFT +    \
+		 _chip##_##_reg##_##_field##_BITS - 1), \
+		_chip##_##_reg##_##_field##_SHIFT)
+
+/*
+ * Given a register value, returns the value of the specified field.
+ *
+ *  _chip	chip name
+ *  _reg	chip register name
+ *  _field	register field name
+ *  _x		the value of the register to be examined
+ */
+
+#define GET_BQ_FIELD(_chip, _reg, _field, _x)          \
+	(((_x) >> _chip##_##_reg##_##_field##_SHIFT) & \
+	 GENMASK(_chip##_##_reg##_##_field##_BITS - 1, 0))
+
+/*
+ * Given a register value, sets the specified field to the given value,
+ * and returns the resulting register value.
+ *
+ *  _chip	chip name
+ *  _reg	chip register name
+ *  _field	register field name
+ *  _v		register field value
+ *  _x		the initial value of the register
+ */
+
+#define SET_BQ_FIELD(_chip, _reg, _field, _v, _x)                 \
+	(((_x) & ~BQ_FIELD_MASK(_chip, _reg, _field)) |           \
+	 (((_v)&GENMASK(_chip##_##_reg##_##_field##_BITS - 1, 0)) \
+	  << _chip##_##_reg##_##_field##_SHIFT))
+
+/*
+ * Given a register value, sets the specified field to the predefined
+ * constant, and returns the resulting register value.
+ *
+ *  _chip	chip name
+ *  _reg	chip register name
+ *  _field	register field name
+ *  _c		register field value constant name
+ *  _x		the initial value of the register
+ */
+
+#define SET_BQ_FIELD_BY_NAME(_chip, _reg, _field, _c, _x)                    \
+	SET_BQ_FIELD(_chip, _reg, _field, _chip##_##_reg##_##_field##__##_c, \
+		     (_x))
+
+#endif /* __CROS_EC_BQ257X0_REGS_H */
diff --git a/driver/charger/isl923x.c b/driver/charger/isl923x.c
index 714d73a93c..997838f53e 100644
--- a/driver/charger/isl923x.c
+++ b/driver/charger/isl923x.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,10 +8,12 @@
 #include "adc.h"
 #include "battery.h"
 #include "battery_smart.h"
+#include "builtin/assert.h"
+#include "charge_state.h"
 #include "charger.h"
+#include "common.h"
 #include "compile_time_macros.h"
 #include "console.h"
-#include "common.h"
 #include "hooks.h"
 #include "i2c.h"
 #include "isl923x.h"
@@ -30,67 +32,106 @@
 #define CHARGER_ISL9238X
 #endif
 
+#ifdef CONFIG_CHARGER_SENSE_RESISTOR_AC_ISL9238
+#undef CONFIG_CHARGER_SENSE_RESISTOR_AC
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC \
+	CONFIG_CHARGER_SENSE_RESISTOR_AC_ISL9238
+#endif
+
 #define DEFAULT_R_AC 20
 #define DEFAULT_R_SNS 10
 #define R_AC CONFIG_CHARGER_SENSE_RESISTOR_AC
 #define R_SNS CONFIG_CHARGER_SENSE_RESISTOR
-#define REG_TO_CURRENT(REG) ((REG) * DEFAULT_R_SNS / R_SNS)
-#define CURRENT_TO_REG(CUR) ((CUR) * R_SNS / DEFAULT_R_SNS)
-#define AC_REG_TO_CURRENT(REG) ((REG) * DEFAULT_R_AC / R_AC)
-#define AC_CURRENT_TO_REG(CUR) ((CUR) * R_AC / DEFAULT_R_AC)
+#define REG_TO_CURRENT(REG) ((REG)*DEFAULT_R_SNS / R_SNS)
+#define CURRENT_TO_REG(CUR) ((CUR)*R_SNS / DEFAULT_R_SNS)
+#define AC_REG_TO_CURRENT(REG) ((REG)*DEFAULT_R_AC / R_AC)
+#define AC_CURRENT_TO_REG(CUR) ((CUR)*R_AC / DEFAULT_R_AC)
+
+#if defined(CONFIG_CHARGER_ISL9237)
+#define CHARGER_NAME "isl9237"
+#define CHARGE_V_MAX ISL9237_SYS_VOLTAGE_REG_MAX
+#define CHARGE_V_MIN ISL923X_SYS_VOLTAGE_REG_MIN
+#define CHARGE_V_STEP 8
+#elif defined(CONFIG_CHARGER_ISL9238)
+#define CHARGER_NAME "isl9238"
+#define CHARGE_V_MAX ISL9238_SYS_VOLTAGE_REG_MAX
+#define CHARGE_V_MIN ISL923X_SYS_VOLTAGE_REG_MIN
+#define CHARGE_V_STEP 8
+#elif defined(CONFIG_CHARGER_ISL9238C)
+#define CHARGER_NAME "isl9238c"
+#define CHARGE_V_MAX ISL9238_SYS_VOLTAGE_REG_MAX
+#define CHARGE_V_MIN ISL923X_SYS_VOLTAGE_REG_MIN
+#define CHARGE_V_STEP 8
+#elif defined(CONFIG_CHARGER_RAA489000)
+#define CHARGER_NAME "raa489000"
+#define CHARGE_V_MAX RAA489000_SYS_VOLTAGE_REG_MAX
+#define CHARGE_V_MIN RAA489000_SYS_VOLTAGE_REG_MIN
+#define CHARGE_V_STEP 8
+#endif
+
+#ifdef CONFIG_CHARGER_RAA489000
+#define CHARGE_I_MAX RAA489000_CURRENT_REG_MAX
+#else
+#define CHARGE_I_MAX ISL923X_CURRENT_REG_MAX
+#endif /* CONFIG_CHARGER_RAA489000 */
+#define CHARGE_I_MIN 4
+#define CHARGE_I_OFF 0
+#define CHARGE_I_STEP 4
+#ifdef CONFIG_CHARGER_RAA489000
+#define INPUT_I_MAX RAA489000_CURRENT_REG_MAX
+#else
+#define INPUT_I_MAX ISL923X_CURRENT_REG_MAX
+#endif /* CONFIG_CHARGER_RAA489000 */
+#define INPUT_I_MIN 4
+#define INPUT_I_STEP 4
 
 /* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+
+enum isl923x_amon_bmon { AMON, BMON };
+enum isl923x_mon_dir { MON_CHARGE = 0, MON_DISCHARGE = 1 };
 
 static int learn_mode;
 
 /* Mutex for CONTROL1 register, that can be updated from multiple tasks. */
-static struct mutex control1_mutex;
+K_MUTEX_DEFINE(control1_mutex_isl923x);
 
 static enum ec_error_list isl923x_discharge_on_ac(int chgnum, int enable);
+static enum ec_error_list isl923x_discharge_on_ac_weak_disable(int chgnum);
 
 /* Charger parameters */
 static const struct charger_info isl9237_charger_info = {
-	.name         = CHARGER_NAME,
-	.voltage_max  = CHARGE_V_MAX,
-	.voltage_min  = CHARGE_V_MIN,
+	.name = CHARGER_NAME,
+	.voltage_max = CHARGE_V_MAX,
+	.voltage_min = CHARGE_V_MIN,
 	.voltage_step = CHARGE_V_STEP,
-	.current_max  = REG_TO_CURRENT(CHARGE_I_MAX),
-	.current_min  = REG_TO_CURRENT(CHARGE_I_MIN),
+	.current_max = REG_TO_CURRENT(CHARGE_I_MAX),
+	.current_min = REG_TO_CURRENT(CHARGE_I_MIN),
 	.current_step = REG_TO_CURRENT(CHARGE_I_STEP),
-	.input_current_max  = AC_REG_TO_CURRENT(INPUT_I_MAX),
-	.input_current_min  = AC_REG_TO_CURRENT(INPUT_I_MIN),
+	.input_current_max = AC_REG_TO_CURRENT(INPUT_I_MAX),
+	.input_current_min = AC_REG_TO_CURRENT(INPUT_I_MIN),
 	.input_current_step = AC_REG_TO_CURRENT(INPUT_I_STEP),
 };
 
-static inline enum ec_error_list raw_read8(int chgnum, int offset, int *value)
-{
-	return i2c_read8(chg_chips[chgnum].i2c_port,
-			 chg_chips[chgnum].i2c_addr_flags,
-			 offset, value);
-}
-
 static inline enum ec_error_list raw_read16(int chgnum, int offset, int *value)
 {
 	return i2c_read16(chg_chips[chgnum].i2c_port,
-			  chg_chips[chgnum].i2c_addr_flags,
-			  offset, value);
+			  chg_chips[chgnum].i2c_addr_flags, offset, value);
 }
 
 static inline enum ec_error_list raw_write16(int chgnum, int offset, int value)
 {
 	return i2c_write16(chg_chips[chgnum].i2c_port,
-			   chg_chips[chgnum].i2c_addr_flags,
-			   offset, value);
+			   chg_chips[chgnum].i2c_addr_flags, offset, value);
 }
 
 static inline enum ec_error_list raw_update16(int chgnum, int offset, int mask,
 					      enum mask_update_action action)
 {
 	return i2c_update16(chg_chips[chgnum].i2c_port,
-			    chg_chips[chgnum].i2c_addr_flags,
-			    offset, mask, action);
+			    chg_chips[chgnum].i2c_addr_flags, offset, mask,
+			    action);
 }
 
 static enum ec_error_list isl9237_set_current(int chgnum, uint16_t current)
@@ -106,50 +147,134 @@ static enum ec_error_list isl9237_set_voltage(int chgnum, uint16_t voltage)
 
 /* chip specific interfaces */
 
-static enum ec_error_list isl923x_set_input_current(int chgnum,
-						    int input_current)
+static enum ec_error_list isl923x_set_input_current_limit(int chgnum,
+							  int input_current)
 {
 	int rv;
 	uint16_t reg = AC_CURRENT_TO_REG(input_current);
 
-	rv = raw_write16(chgnum, ISL923X_REG_ADAPTER_CURRENT1, reg);
+	rv = raw_write16(chgnum, ISL923X_REG_ADAPTER_CURRENT_LIMIT1, reg);
 	if (rv)
 		return rv;
 
-	return raw_write16(chgnum, ISL923X_REG_ADAPTER_CURRENT2, reg);
+	return raw_write16(chgnum, ISL923X_REG_ADAPTER_CURRENT_LIMIT2, reg);
 }
 
-static enum ec_error_list isl923x_get_input_current(int chgnum,
-						    int *input_current)
+#ifdef CONFIG_CMD_CHARGER_ADC_AMON_BMON
+static int get_amon_bmon(int chgnum, enum isl923x_amon_bmon amon,
+			 enum isl923x_mon_dir direction, int *adc)
+{
+	int reg, ret;
+
+	if (IS_ENABLED(CHARGER_ISL9238X)) {
+		ret = raw_read16(chgnum, ISL9238_REG_CONTROL3, &reg);
+		if (ret)
+			return ret;
+
+		/* Switch direction */
+		if (direction)
+			reg |= ISL9238_C3_AMON_BMON_DIRECTION;
+		else
+			reg &= ~ISL9238_C3_AMON_BMON_DIRECTION;
+		ret = raw_write16(chgnum, ISL9238_REG_CONTROL3, reg);
+		if (ret)
+			return ret;
+	}
+
+	mutex_lock(&control1_mutex_isl923x);
+
+	ret = raw_read16(chgnum, ISL923X_REG_CONTROL1, &reg);
+	if (!ret) {
+		/* Switch between AMON/BMON */
+		if (amon == AMON)
+			reg &= ~ISL923X_C1_SELECT_BMON;
+		else
+			reg |= ISL923X_C1_SELECT_BMON;
+
+		/* Enable monitor */
+		reg &= ~ISL923X_C1_DISABLE_MON;
+		ret = raw_write16(chgnum, ISL923X_REG_CONTROL1, reg);
+	}
+
+	if (ret)
+		goto err;
+
+	*adc = adc_read_channel(ADC_AMON_BMON);
+
+	ret = raw_read16(chgnum, ISL923X_REG_CONTROL1, &reg);
+	if (ret)
+		goto err;
+
+	/* Disable monitor */
+	reg |= ISL923X_C1_DISABLE_MON;
+
+	ret = raw_write16(chgnum, ISL923X_REG_CONTROL1, reg);
+	if (ret)
+		goto err;
+
+err:
+	mutex_unlock(&control1_mutex_isl923x);
+	return ret;
+}
+#endif
+
+static enum ec_error_list isl923x_get_input_current_limit(int chgnum,
+							  int *input_current)
+{
+	int rv;
+	int regval;
+
+	rv = raw_read16(chgnum, ISL923X_REG_ADAPTER_CURRENT_LIMIT1, &regval);
+	if (rv)
+		return rv;
+
+	*input_current = AC_REG_TO_CURRENT(regval);
+	return EC_SUCCESS;
+}
+
+#ifdef CONFIG_CHARGER_RAA489000
+static enum ec_error_list raa489000_get_input_current(int chgnum,
+						      int *input_current)
 {
 	int rv;
 	int regval;
 	int reg;
 
-	if (IS_ENABLED(CONFIG_CHARGER_RAA489000))
-		reg = RAA489000_REG_ADC_INPUT_CURRENT;
-	else
-		reg = ISL923X_REG_ADAPTER_CURRENT1;
+	reg = RAA489000_REG_ADC_INPUT_CURRENT;
 
 	rv = raw_read16(chgnum, reg, &regval);
 	if (rv)
 		return rv;
 
-	if (IS_ENABLED(CONFIG_CHARGER_RAA489000)) {
-		/* LSB is 22.2mA */
-		regval *= 22;
-	}
+	/* The value is in 22.2mA increments. */
+	regval *= 222;
+	regval /= 10;
 
 	*input_current = AC_REG_TO_CURRENT(regval);
 	return EC_SUCCESS;
 }
+#elif defined(CONFIG_CMD_CHARGER_ADC_AMON_BMON)
+static enum ec_error_list isl923x_get_input_current(int chgnum,
+						    int *input_current)
+{
+	int rv, adc;
+
+	rv = get_amon_bmon(chgnum, AMON, MON_CHARGE, &adc);
+	if (rv)
+		return rv;
+
+	*input_current = adc / CONFIG_CHARGER_SENSE_RESISTOR_AC;
+
+	return EC_SUCCESS;
+}
+#endif /* CONFIG_CHARGER_RAA489000 */
 
 #if defined(CONFIG_CHARGER_OTG) && defined(CHARGER_ISL9238X)
 static enum ec_error_list isl923x_enable_otg_power(int chgnum, int enabled)
 {
 	int rv, control1;
 
-	mutex_lock(&control1_mutex);
+	mutex_lock(&control1_mutex_isl923x);
 
 	rv = raw_read16(chgnum, ISL923X_REG_CONTROL1, &control1);
 	if (rv)
@@ -163,7 +288,7 @@ static enum ec_error_list isl923x_enable_otg_power(int chgnum, int enabled)
 	rv = raw_write16(chgnum, ISL923X_REG_CONTROL1, control1);
 
 out:
-	mutex_unlock(&control1_mutex);
+	mutex_unlock(&control1_mutex_isl923x);
 
 	return rv;
 }
@@ -178,13 +303,13 @@ static enum ec_error_list isl923x_set_otg_current_voltage(int chgnum,
 {
 	int rv;
 	uint16_t volt_reg = (output_voltage / ISL9238_OTG_VOLTAGE_STEP)
-			<< ISL9238_OTG_VOLTAGE_SHIFT;
+			    << ISL9238_OTG_VOLTAGE_SHIFT;
 	uint16_t current_reg =
 		DIV_ROUND_UP(output_current, ISL923X_OTG_CURRENT_STEP)
-			<< ISL923X_OTG_CURRENT_SHIFT;
+		<< ISL923X_OTG_CURRENT_SHIFT;
 
 	if (output_current < 0 || output_current > ISL923X_OTG_CURRENT_MAX ||
-			output_voltage > ISL9238_OTG_VOLTAGE_MAX)
+	    output_voltage > ISL9238_OTG_VOLTAGE_MAX)
 		return EC_ERROR_INVAL;
 
 	/* Set voltage. */
@@ -280,26 +405,34 @@ static enum ec_error_list isl923x_set_mode(int chgnum, int mode)
 	 * See crosbug.com/p/51196.  Always disable learn mode unless it was set
 	 * explicitly.
 	 */
-	if (!learn_mode)
-		rv = isl923x_discharge_on_ac(chgnum, 0);
+	rv = isl923x_discharge_on_ac_weak_disable(chgnum);
 
 	/* ISL923X does not support inhibit mode setting. */
 	return rv;
 }
 
+#ifdef CONFIG_CHARGER_RAA489000
+static enum ec_error_list raa489000_get_actual_current(int chgnum, int *current)
+{
+	int rv;
+	int reg;
+
+	rv = raw_read16(chgnum, RAA489000_REG_ADC_CHARGE_CURRENT, &reg);
+	/* The value is in 22.2mA increments. */
+	reg *= 222;
+	reg /= 10;
+
+	*current = REG_TO_CURRENT(reg);
+	return rv;
+}
+#endif /* CONFIG_CHARGER_RAA489000 */
+
 static enum ec_error_list isl923x_get_current(int chgnum, int *current)
 {
 	int rv;
 	int reg;
 
-	if (IS_ENABLED(CONFIG_CHARGER_RAA489000)) {
-		rv = raw_read16(chgnum, RAA489000_REG_ADC_CHARGE_CURRENT, &reg);
-		/* The value is in 22.2mA increments. */
-		reg *= 222;
-		reg /= 10;
-	} else {
-		rv = raw_read16(chgnum, ISL923X_REG_CHG_CURRENT, &reg);
-	}
+	rv = raw_read16(chgnum, ISL923X_REG_CHG_CURRENT, &reg);
 	if (rv)
 		return rv;
 
@@ -312,24 +445,28 @@ static enum ec_error_list isl923x_set_current(int chgnum, int current)
 	return isl9237_set_current(chgnum, current);
 }
 
-static enum ec_error_list isl923x_get_voltage(int chgnum, int *voltage)
+#ifdef CONFIG_CHARGER_RAA489000
+static enum ec_error_list raa489000_get_actual_voltage(int chgnum, int *voltage)
 {
 	int rv;
 	int reg;
 
-	if (IS_ENABLED(CONFIG_CHARGER_RAA489000)) {
-		rv = raw_read16(chgnum, RAA489000_REG_ADC_VSYS, &reg);
-		if (rv)
-			return rv;
+	rv = raw_read16(chgnum, RAA489000_REG_ADC_VSYS, &reg);
+	if (rv)
+		return rv;
 
-		/* The voltage is returned in bits 13:6. LSB is 96mV. */
-		reg &= GENMASK(13, 6);
-		reg >>= 6;
-		reg *= 96;
+	/* The voltage is returned in bits 13:6. LSB is 96mV. */
+	reg &= GENMASK(13, 6);
+	reg >>= 6;
+	reg *= 96;
 
-		*voltage = reg;
-		return EC_SUCCESS;
-	}
+	*voltage = reg;
+	return EC_SUCCESS;
+}
+#endif /* CONFIG_CHARGER_RAA489000 */
+
+static enum ec_error_list isl923x_get_voltage(int chgnum, int *voltage)
+{
 	return raw_read16(chgnum, ISL923X_REG_SYS_VOLTAGE_MAX, voltage);
 }
 
@@ -362,6 +499,23 @@ static enum ec_error_list isl923x_post_init(int chgnum)
 	return EC_SUCCESS;
 }
 
+static enum ec_error_list isl923x_set_hw_ramp(int chgnum, int enable)
+{
+	int rv, reg;
+
+	rv = raw_read16(chgnum, ISL923X_REG_CONTROL0, &reg);
+	if (rv)
+		return rv;
+
+	/* HW ramp is controlled by input voltage regulation reference bits */
+	if (enable)
+		reg &= ~ISL923X_C0_DISABLE_VREG;
+	else
+		reg |= ISL923X_C0_DISABLE_VREG;
+
+	return raw_write16(chgnum, ISL923X_REG_CONTROL0, reg);
+}
+
 int isl923x_set_ac_prochot(int chgnum, uint16_t ma)
 {
 	int rv;
@@ -371,7 +525,7 @@ int isl923x_set_ac_prochot(int chgnum, uint16_t ma)
 		return EC_ERROR_INVAL;
 	}
 
-	rv = raw_write16(chgnum, ISL923X_REG_PROCHOT_AC, ma);
+	rv = raw_write16(chgnum, ISL923X_REG_PROCHOT_AC, AC_CURRENT_TO_REG(ma));
 	if (rv)
 		CPRINTS("%s set_ac_prochot failed (%d)", CHARGER_NAME, rv);
 	return rv;
@@ -386,7 +540,7 @@ int isl923x_set_dc_prochot(int chgnum, uint16_t ma)
 		return EC_ERROR_INVAL;
 	}
 
-	rv = raw_write16(chgnum, ISL923X_REG_PROCHOT_DC, ma);
+	rv = raw_write16(chgnum, ISL923X_REG_PROCHOT_DC, CURRENT_TO_REG(ma));
 	if (rv)
 		CPRINTS("%s set_dc_prochot failed (%d)", CHARGER_NAME, rv);
 	return rv;
@@ -398,8 +552,8 @@ int isl923x_set_comparator_inversion(int chgnum, int invert)
 	int regval;
 
 	rv = i2c_read16(chg_chips[chgnum].i2c_port,
-			chg_chips[chgnum].i2c_addr_flags,
-			ISL923X_REG_CONTROL2, &regval);
+			chg_chips[chgnum].i2c_addr_flags, ISL923X_REG_CONTROL2,
+			&regval);
 	if (invert)
 		regval |= ISL923X_C2_INVERT_CMOUT;
 	else
@@ -421,8 +575,8 @@ static void isl923x_init(int chgnum)
 {
 	int reg;
 	const struct battery_info *bi = battery_get_info();
-	int precharge_voltage = bi->precharge_voltage ?
-		bi->precharge_voltage : bi->voltage_min;
+	int precharge_voltage = bi->precharge_voltage ? bi->precharge_voltage :
+							bi->voltage_min;
 
 	if (IS_ENABLED(CONFIG_CHARGER_RAA489000)) {
 		if (CONFIG_CHARGER_SENSE_RESISTOR ==
@@ -434,13 +588,43 @@ static void isl923x_init(int chgnum)
 			if (raw_read16(chgnum, ISL9238_REG_CONTROL4, &reg))
 				goto init_fail;
 
-			if (raw_write16(chgnum, ISL9238_REG_CONTROL4,
-					reg |
-					RAA489000_C4_PSYS_RSNS_RATIO_1_TO_1))
+			if (raw_write16(
+				    chgnum, ISL9238_REG_CONTROL4,
+				    reg | RAA489000_C4_PSYS_RSNS_RATIO_1_TO_1))
 				goto init_fail;
 		}
+
+		/*
+		 * Enable hysteresis for CCM/DCM boundary to help with ripple.
+		 */
+		if (raw_read16(chgnum, ISL9238_REG_CONTROL3, &reg))
+			goto init_fail;
+
+		if (raw_write16(chgnum, ISL9238_REG_CONTROL3,
+				reg | RAA489000_C3_DCM_CCM_HYSTERESIS_ENABLE))
+			goto init_fail;
+
+		/* Set switching frequency to 600KHz to help with ripple. */
+		if (raw_read16(chgnum, ISL923X_REG_CONTROL1, &reg))
+			goto init_fail;
+
+		reg &= ~ISL923X_C1_SWITCH_FREQ_MASK;
+
+		if (raw_write16(chgnum, ISL923X_REG_CONTROL1,
+				reg | ISL9237_C1_SWITCH_FREQ_599K))
+			goto init_fail;
 	}
 
+	if (raw_read16(chgnum, ISL923X_REG_CONTROL1, &reg))
+		goto init_fail;
+	/*
+	 * Disable amon/bmon by default.
+	 */
+	reg |= ISL923X_C1_DISABLE_MON;
+
+	if (raw_write16(chgnum, ISL923X_REG_CONTROL1, reg))
+		goto init_fail;
+
 	if (IS_ENABLED(CONFIG_TRICKLE_CHARGING))
 		if (raw_write16(chgnum, ISL923X_REG_SYS_VOLTAGE_MIN,
 				precharge_voltage))
@@ -455,10 +639,22 @@ static void isl923x_init(int chgnum)
 
 	if (!IS_ENABLED(CONFIG_CHARGER_RAA489000))
 		reg |= ISL923X_C2_OTG_DEBOUNCE_150;
+
+	if (IS_ENABLED(CONFIG_CHARGER_RAA489000))
+		reg |= ISL923X_C2_PROCHOT_DEBOUNCE_500;
+	else
+		reg |= ISL923X_C2_PROCHOT_DEBOUNCE_1000;
+
 	if (raw_write16(chgnum, ISL923X_REG_CONTROL2,
-			reg |
-			ISL923X_C2_PROCHOT_DEBOUNCE_1000 |
-			ISL923X_C2_ADAPTER_DEBOUNCE_150))
+			reg | ISL923X_C2_ADAPTER_DEBOUNCE_150))
+		goto init_fail;
+
+	/*
+	 * Disable input regulation until other tasks such as USB-C,
+	 * charger_manager, etc. have had time to gather information
+	 * about the state of the connected charger
+	 */
+	if (isl923x_set_hw_ramp(chgnum, 0))
 		goto init_fail;
 
 	if (IS_ENABLED(CONFIG_CHARGE_RAMP_HW)) {
@@ -486,23 +682,14 @@ static void isl923x_init(int chgnum)
 			 */
 			if (IS_ENABLED(CONFIG_CHARGER_RAA489000))
 				reg = (4437 / RAA489000_INPUT_VOLTAGE_REF_STEP)
-					<< RAA489000_INPUT_VOLTAGE_REF_SHIFT;
+				      << RAA489000_INPUT_VOLTAGE_REF_SHIFT;
 			else
 				reg = (4439 / ISL9238_INPUT_VOLTAGE_REF_STEP)
-					<< ISL9238_INPUT_VOLTAGE_REF_SHIFT;
+				      << ISL9238_INPUT_VOLTAGE_REF_SHIFT;
 
 			if (raw_write16(chgnum, ISL9238_REG_INPUT_VOLTAGE, reg))
 				goto init_fail;
 		}
-	} else {
-		if (raw_read16(chgnum, ISL923X_REG_CONTROL0, &reg))
-			goto init_fail;
-
-		/* Disable voltage regulation loop to disable charge ramp */
-		reg |= ISL923X_C0_DISABLE_VREG;
-
-		if (raw_write16(chgnum, ISL923X_REG_CONTROL0, reg))
-			goto init_fail;
 	}
 
 	if (IS_ENABLED(CONFIG_CHARGER_ISL9238C)) {
@@ -512,8 +699,26 @@ static void isl923x_init(int chgnum)
 
 		reg |= ISL9238C_C6_SLEW_RATE_CONTROL;
 
+		if (IS_ENABLED(CONFIG_ISL9238C_DISABLE_CMOUT_LATCH)) {
+			reg |= ISL9238C_C6_CMOUT_LATCH;
+		}
+
 		if (raw_write16(chgnum, ISL9238C_REG_CONTROL6, reg))
 			goto init_fail;
+
+		if (IS_ENABLED(CONFIG_ISL9238C_ENABLE_BUCK_MODE)) {
+			if (raw_read16(chgnum, ISL923X_REG_CONTROL0, &reg))
+				goto init_fail;
+
+			reg |= ISL923X_C0_ENABLE_BUCK;
+			/* Adjusts phase comparator threshold offset */
+			reg &= ~ISL923X_C0_BUCK_PHASE_MASK;
+			reg |= CONFIG_ISL9238C_BUCK_PHASE_VOLTAGE
+			       << ISL923X_C0_BUCK_PHASE_SHIFT;
+
+			if (raw_write16(chgnum, ISL923X_REG_CONTROL0, reg))
+				goto init_fail;
+		}
 	}
 
 	if (IS_ENABLED(CONFIG_CHARGER_RAA489000)) {
@@ -528,6 +733,17 @@ static void isl923x_init(int chgnum)
 			goto init_fail;
 	}
 
+	if (IS_ENABLED(CONFIG_CHARGER_RAA489000)) {
+		if (raw_read16(chgnum, ISL923X_REG_CONTROL2, &reg))
+			goto init_fail;
+		/* Set trickle charge current bits. */
+		reg &= ~GENMASK(13, 15);
+		reg |= ((CONFIG_RAA489000_TRICKLE_CHARGE_CURRENT - 32) / 32)
+		       << 13;
+		if (raw_write16(chgnum, ISL923X_REG_CONTROL2, reg))
+			goto init_fail;
+	}
+
 	/* Revert all changes done by isl9238c_hibernate(). */
 	if (IS_ENABLED(CONFIG_CHARGER_ISL9238C) && isl9238c_resume(chgnum))
 		goto init_fail;
@@ -569,23 +785,54 @@ static void isl923x_init(int chgnum)
 		/*
 		 * Initialize the input current limit to the board's default.
 		 */
-		if (isl923x_set_input_current(chgnum,
-					      CONFIG_CHARGER_INPUT_CURRENT))
+		if (isl923x_set_input_current_limit(
+			    chgnum, CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT))
 			goto init_fail;
 	}
 
+#ifdef CONFIG_OCPC
+	if (IS_ENABLED(CONFIG_CHARGER_RAA489000)) {
+		/*
+		 * Ignore BATGONE on auxiliary charger ICs as it's not connected
+		 * there.
+		 * Clear DISABLE_GP_CMP & MCU_LDO_BAT_STATE_DISABLE to
+		 * enable ALERT_B with control the power of sub-board
+		 */
+		if (chgnum != CHARGER_PRIMARY) {
+			if (raw_read16(chgnum, ISL9238_REG_CONTROL4, &reg))
+				goto init_fail;
+
+			reg |= RAA489000_C4_BATGONE_DISABLE;
+			reg &= ~RAA489000_C4_DISABLE_GP_CMP;
+
+			if (raw_write16(chgnum, ISL9238_REG_CONTROL4, reg))
+				goto init_fail;
+
+			if (raw_read16(chgnum, RAA489000_REG_CONTROL8, &reg))
+				goto init_fail;
+
+			reg &= ~RAA489000_C8_MCU_LDO_BAT_STATE_DISABLE;
+
+			if (raw_write16(chgnum, RAA489000_REG_CONTROL8, reg))
+				goto init_fail;
+		}
+	}
+#endif /* CONFIG_OCPC */
+
 	return;
 init_fail:
 	CPRINTS("%s init failed!", CHARGER_NAME);
 }
 
-static enum ec_error_list isl923x_discharge_on_ac(int chgnum, int enable)
+/*
+ * Writes to ISL923X_REG_CONTROL1, unsafe as it does not lock
+ * control1_mutex_isl923x.
+ */
+static enum ec_error_list isl923x_discharge_on_ac_unsafe(int chgnum, int enable)
 {
 	int rv;
 	int control1;
 
-	mutex_lock(&control1_mutex);
-
 	rv = raw_read16(chgnum, ISL923X_REG_CONTROL1, &control1);
 	if (rv)
 		goto out;
@@ -598,19 +845,87 @@ static enum ec_error_list isl923x_discharge_on_ac(int chgnum, int enable)
 
 	rv = raw_write16(chgnum, ISL923X_REG_CONTROL1, control1);
 
-	learn_mode = !rv && enable;
+	if (!rv)
+		learn_mode = enable;
 
 out:
-	mutex_unlock(&control1_mutex);
 	return rv;
 }
 
-#ifdef CONFIG_CHARGER_RAA489000
-void raa489000_hibernate(int chgnum)
+static enum ec_error_list isl923x_discharge_on_ac(int chgnum, int enable)
+{
+	int rv;
+
+	mutex_lock(&control1_mutex_isl923x);
+	rv = isl923x_discharge_on_ac_unsafe(chgnum, enable);
+	mutex_unlock(&control1_mutex_isl923x);
+	return rv;
+}
+
+/* Disables discharge on ac only if it wasn't explicitly enabled. */
+static enum ec_error_list isl923x_discharge_on_ac_weak_disable(int chgnum)
+{
+	int rv = 0;
+
+	mutex_lock(&control1_mutex_isl923x);
+	if (!learn_mode)
+		rv = isl923x_discharge_on_ac_unsafe(chgnum, 0);
+
+	mutex_unlock(&control1_mutex_isl923x);
+	return rv;
+}
+
+enum ec_error_list raa489000_is_acok(int chgnum, bool *acok)
+{
+	int regval, rv;
+
+	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
+		CPRINTS("%s: Invalid chgnum! (%d)", __func__, chgnum);
+		return EC_ERROR_INVAL;
+	}
+
+	rv = raw_read16(chgnum, ISL9238_REG_INFO2, &regval);
+	if (rv != EC_SUCCESS)
+		return rv;
+
+	/*
+	 * ACOK can sometimes be asserted when RAA489000 is sourcing VBUS in OTG
+	 * mode, because that bit is derived from the VBUS comparator. If the
+	 * charger reports it's in OTG mode, always say ACOK is false because we
+	 * can't be running from a charger if we're also sourcing VBUS and the
+	 * ACOK bit may be untrustworthy.
+	 *
+	 * This may sometimes report incorrectly because the state bits of
+	 * the Information2 register take a small amount of time to update on
+	 * a state change. In most cases the event hooks used to trigger
+	 * raa489000_check_ac_present are good indications of a state change,
+	 * but during power role swaps there may be no hooks executed so it's
+	 * most consistent to use the charger's reported state only (otherwise
+	 * some situations could use the EC's view of the current state and
+	 * others would require asking the charger).
+	 */
+	if (((regval >> RAA489000_INFO2_STATE_SHIFT) &
+	     RAA489000_INFO2_STATE_MASK) == RAA489000_INFO2_STATE_OTG)
+		*acok = false;
+	else
+		*acok = (regval & RAA489000_INFO2_ACOK) != 0;
+
+	return EC_SUCCESS;
+}
+
+int raa489000_enable_asgate(int chgnum, bool enable)
+{
+	enum mask_update_action action = enable ? MASK_SET : MASK_CLR;
+
+	return raw_update16(chgnum, RAA489000_REG_CONTROL8,
+			    RAA489000_C8_ASGATE_ON_READY, action);
+}
+
+void raa489000_hibernate(int chgnum, bool disable_adc)
 {
 	int rv, regval;
 
-	if ((chgnum < 0) || (chgnum > board_get_charger_chip_count())) {
+	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
 		CPRINTS("%s: Invalid chgnum! (%d)", __func__, chgnum);
 		return;
 	}
@@ -639,7 +954,7 @@ void raa489000_hibernate(int chgnum)
 		 */
 		regval |= RAA489000_C1_BGATE_FORCE_OFF;
 
-		/* Disable AMON/BMON */
+		/* Disable AMON/BMON. MON is enabled at get_amon_bmon() */
 		regval |= ISL923X_C1_DISABLE_MON;
 
 		/* Disable PSYS */
@@ -652,8 +967,11 @@ void raa489000_hibernate(int chgnum)
 
 	rv = raw_read16(chgnum, ISL9238_REG_CONTROL3, &regval);
 	if (!rv) {
-		/* ADC is active only when adapter plugged in */
-		regval &= ~RAA489000_ENABLE_ADC;
+		if (disable_adc)
+			/* ADC is active only when adapter plugged in */
+			regval &= ~RAA489000_ENABLE_ADC;
+		else
+			regval |= RAA489000_ENABLE_ADC;
 
 		rv = raw_write16(chgnum, ISL9238_REG_CONTROL3, regval);
 	}
@@ -685,31 +1003,32 @@ void raa489000_hibernate(int chgnum)
 			CPRINTS("%s(%d):Failed to set Control8!", __func__,
 				chgnum);
 	}
+
+	/* Disable DVC on the main charger to reduce power consumption. */
+	if (chgnum == CHARGER_PRIMARY) {
+		rv = raw_write16(chgnum, RAA489000_REG_CONTROL10, 0);
+		if (rv)
+			CPRINTS("%s(%d):Failed to set Control10!", __func__,
+				chgnum);
+	}
 #endif
 
 	cflush();
 }
-#endif /* CONFIG_CHARGER_RAA489000 */
 
-#ifdef CONFIG_CHARGER_ISL9238C
 enum ec_error_list isl9238c_hibernate(int chgnum)
 {
-	/* Disable IMON */
-	RETURN_ERROR(raw_update16(chgnum, ISL923X_REG_CONTROL1,
-				ISL923X_C1_DISABLE_MON, MASK_SET));
-
 	/* Disable PSYS */
 	RETURN_ERROR(raw_update16(chgnum, ISL923X_REG_CONTROL1,
-				ISL923X_C1_ENABLE_PSYS, MASK_CLR));
+				  ISL923X_C1_ENABLE_PSYS, MASK_CLR));
 
 	/* Disable GP comparator */
 	RETURN_ERROR(raw_update16(chgnum, ISL923X_REG_CONTROL2,
-				ISL923X_C2_COMPARATOR, MASK_SET));
+				  ISL923X_C2_COMPARATOR, MASK_SET));
 
 	/* Force BGATE off */
 	RETURN_ERROR(raw_update16(chgnum, ISL9238_REG_CONTROL3,
-				ISL9238_C3_BGATE_OFF, MASK_SET));
-
+				  ISL9238_C3_BGATE_OFF, MASK_SET));
 
 	return EC_SUCCESS;
 }
@@ -718,44 +1037,22 @@ enum ec_error_list isl9238c_resume(int chgnum)
 {
 	/* Revert everything in isl9238c_hibernate() */
 	RETURN_ERROR(raw_update16(chgnum, ISL923X_REG_CONTROL1,
-				ISL923X_C1_DISABLE_MON, MASK_CLR));
-
-	RETURN_ERROR(raw_update16(chgnum, ISL923X_REG_CONTROL1,
-				ISL923X_C1_ENABLE_PSYS, MASK_SET));
+				  ISL923X_C1_ENABLE_PSYS, MASK_SET));
 
 	RETURN_ERROR(raw_update16(chgnum, ISL923X_REG_CONTROL2,
-				ISL923X_C2_COMPARATOR, MASK_CLR));
+				  ISL923X_C2_COMPARATOR, MASK_CLR));
 
 	RETURN_ERROR(raw_update16(chgnum, ISL9238_REG_CONTROL3,
-				ISL9238_C3_BGATE_OFF, MASK_CLR));
+				  ISL9238_C3_BGATE_OFF, MASK_CLR));
 
 	return EC_SUCCESS;
 }
-#endif /* CONFIG_CHARGER_ISL9238C */
-
 
 /*****************************************************************************/
 /* Hardware current ramping */
 
 #ifdef CONFIG_CHARGE_RAMP_HW
-static enum ec_error_list isl923x_set_hw_ramp(int chgnum, int enable)
-{
-	int rv, reg;
-
-	rv = raw_read16(chgnum, ISL923X_REG_CONTROL0, &reg);
-	if (rv)
-		return rv;
-
-	/* HW ramp is controlled by input voltage regulation reference bits */
-	if (enable)
-		reg &= ~ISL923X_C0_DISABLE_VREG;
-	else
-		reg |= ISL923X_C0_DISABLE_VREG;
-
-	return raw_write16(chgnum, ISL923X_REG_CONTROL0, reg);
-}
-
-static int isl923x_ramp_is_stable(int chgnum)
+test_mockable_static int isl923x_ramp_is_stable(int chgnum)
 {
 	/*
 	 * Since ISL cannot read the current limit that the ramp has settled
@@ -765,7 +1062,7 @@ static int isl923x_ramp_is_stable(int chgnum)
 	return 0;
 }
 
-static int isl923x_ramp_is_detected(int chgnum)
+test_mockable_static int isl923x_ramp_is_detected(int chgnum)
 {
 	return 1;
 }
@@ -778,13 +1075,12 @@ static int isl923x_ramp_get_current_limit(int chgnum)
 	 */
 	int input_current;
 
-	if (isl923x_get_input_current(chgnum, &input_current) != EC_SUCCESS)
+	if (isl923x_get_input_current_limit(chgnum, &input_current))
 		return 0;
 	return input_current;
 }
 #endif /* CONFIG_CHARGE_RAMP_HW */
 
-
 #ifdef CONFIG_CHARGER_PSYS
 static int psys_enabled;
 /*
@@ -795,7 +1091,7 @@ static void charger_enable_psys(void)
 {
 	int val;
 
-	mutex_lock(&control1_mutex);
+	mutex_lock(&control1_mutex_isl923x);
 
 	/*
 	 * enable system power monitor PSYS function
@@ -811,15 +1107,15 @@ static void charger_enable_psys(void)
 	psys_enabled = 1;
 
 out:
-	mutex_unlock(&control1_mutex);
+	mutex_unlock(&control1_mutex_isl923x);
 }
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, charger_enable_psys, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, charger_enable_psys, HOOK_PRIO_DEFAULT);
 
 static void charger_disable_psys(void)
 {
 	int val;
 
-	mutex_lock(&control1_mutex);
+	mutex_lock(&control1_mutex_isl923x);
 
 	/*
 	 * disable system power monitor PSYS function
@@ -835,9 +1131,9 @@ static void charger_disable_psys(void)
 	psys_enabled = 0;
 
 out:
-	mutex_unlock(&control1_mutex);
+	mutex_unlock(&control1_mutex_isl923x);
 }
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, charger_disable_psys, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, charger_disable_psys, HOOK_PRIO_DEFAULT);
 
 #ifdef CONFIG_CHARGER_PSYS_READ
 int charger_get_system_power(void)
@@ -861,64 +1157,29 @@ int charger_get_system_power(void)
 	return adc;
 }
 
-static int console_command_psys(int argc, char **argv)
+static int console_command_psys(int argc, const char **argv)
 {
 	ccprintf("PSYS = %d uW\n", charger_get_system_power());
 	return 0;
 }
-DECLARE_CONSOLE_COMMAND(psys, console_command_psys,
-			NULL,
+DECLARE_CONSOLE_COMMAND(psys, console_command_psys, NULL,
 			"Get the system power in mW");
 #endif /* CONFIG_CHARGER_PSYS_READ */
 #endif /* CONFIG_CHARGER_PSYS */
 
 #ifdef CONFIG_CMD_CHARGER_ADC_AMON_BMON
-enum amon_bmon { AMON, BMON };
-
-static int print_amon_bmon(int chgnum, enum amon_bmon amon,
-					  int direction, int resistor)
+static int print_amon_bmon(int chgnum, enum isl923x_amon_bmon amon,
+			   enum isl923x_mon_dir direction, int resistor)
 {
-	int adc, curr, reg, ret;
-
-	if (IS_ENABLED(CHARGER_ISL9238X)) {
-		ret = raw_read16(chgnum, ISL9238_REG_CONTROL3, &reg);
-		if (ret)
-			return ret;
-
-		/* Switch direction */
-		if (direction)
-			reg |= ISL9238_C3_AMON_BMON_DIRECTION;
-		else
-			reg &= ~ISL9238_C3_AMON_BMON_DIRECTION;
-		ret = raw_write16(chgnum, ISL9238_REG_CONTROL3, reg);
-		if (ret)
-			return ret;
-	}
-
-	mutex_lock(&control1_mutex);
-
-	ret = raw_read16(chgnum, ISL923X_REG_CONTROL1, &reg);
-	if (!ret) {
-		/* Switch between AMON/BMON */
-		if (amon == AMON)
-			reg &= ~ISL923X_C1_SELECT_BMON;
-		else
-			reg |= ISL923X_C1_SELECT_BMON;
-
-		/* Enable monitor */
-		reg &= ~ISL923X_C1_DISABLE_MON;
-		ret = raw_write16(chgnum, ISL923X_REG_CONTROL1, reg);
-	}
-
-	mutex_unlock(&control1_mutex);
+	int ret, adc, curr;
 
+	ret = get_amon_bmon(chgnum, amon, direction, &adc);
 	if (ret)
 		return ret;
 
-	adc = adc_read_channel(ADC_AMON_BMON);
 	curr = adc / resistor;
 	ccprintf("%cMON(%sharging): %d uV, %d mA\n", amon == AMON ? 'A' : 'B',
-		direction ? "Disc" : "C", adc, curr);
+		 direction == MON_DISCHARGE ? "Disc" : "C", adc, curr);
 
 	return ret;
 }
@@ -926,7 +1187,7 @@ static int print_amon_bmon(int chgnum, enum amon_bmon amon,
 /**
  * Get charger AMON and BMON current.
  */
-static int console_command_amon_bmon(int argc, char **argv)
+static int console_command_amon_bmon(int argc, const char **argv)
 {
 	int ret = EC_SUCCESS;
 	int print_ac = 1;
@@ -952,24 +1213,27 @@ static int console_command_amon_bmon(int argc, char **argv)
 
 	if (print_ac) {
 		if (print_charge)
-			ret |= print_amon_bmon(chgnum, AMON, 0,
-					CONFIG_CHARGER_SENSE_RESISTOR_AC);
+			ret |= print_amon_bmon(
+				chgnum, AMON, MON_CHARGE,
+				CONFIG_CHARGER_SENSE_RESISTOR_AC);
 		if (IS_ENABLED(CHARGER_ISL9238X) && print_discharge)
-			ret |= print_amon_bmon(chgnum, AMON, 1,
-					CONFIG_CHARGER_SENSE_RESISTOR_AC);
+			ret |= print_amon_bmon(
+				chgnum, AMON, MON_DISCHARGE,
+				CONFIG_CHARGER_SENSE_RESISTOR_AC);
 	}
 
 	if (print_battery) {
 		if (IS_ENABLED(CHARGER_ISL9238X) && print_charge)
-			ret |= print_amon_bmon(chgnum, BMON, 0,
-					/*
-					 * charging current monitor has
-					 * 2x amplification factor
-					 */
-					2 * CONFIG_CHARGER_SENSE_RESISTOR);
+			ret |= print_amon_bmon(
+				chgnum, BMON, MON_CHARGE,
+				/*
+				 * charging current monitor has
+				 * 2x amplification factor
+				 */
+				2 * CONFIG_CHARGER_SENSE_RESISTOR);
 		if (print_discharge)
-			ret |= print_amon_bmon(chgnum, BMON, 1,
-					CONFIG_CHARGER_SENSE_RESISTOR);
+			ret |= print_amon_bmon(chgnum, BMON, MON_DISCHARGE,
+					       CONFIG_CHARGER_SENSE_RESISTOR);
 	}
 
 	return ret;
@@ -993,8 +1257,7 @@ static void dump_reg_range(int chgnum, int low, int high)
 	for (reg = low; reg <= high; reg++) {
 		CPRINTF("[%Xh] = ", reg);
 		rv = i2c_read16(chg_chips[chgnum].i2c_port,
-				chg_chips[chgnum].i2c_addr_flags,
-				reg, &regval);
+				chg_chips[chgnum].i2c_addr_flags, reg, &regval);
 		if (!rv)
 			CPRINTF("0x%04x\n", regval);
 		else
@@ -1003,17 +1266,8 @@ static void dump_reg_range(int chgnum, int low, int high)
 	}
 }
 
-static int command_isl923x_dump(int argc, char **argv)
+static void command_isl923x_dump(int chgnum)
 {
-	int chgnum = 0;
-	char *e;
-
-	if (argc >= 2) {
-		chgnum = strtoi(argv[1], &e, 10);
-		if (*e)
-			return EC_ERROR_PARAM1;
-	}
-
 	dump_reg_range(chgnum, 0x14, 0x15);
 	if (IS_ENABLED(CONFIG_CHARGER_ISL9238C))
 		dump_reg_range(chgnum, 0x37, 0x37);
@@ -1023,11 +1277,7 @@ static int command_isl923x_dump(int argc, char **argv)
 	    IS_ENABLED(CONFIG_CHARGER_RAA489000))
 		dump_reg_range(chgnum, 0x4B, 0x4E);
 	dump_reg_range(chgnum, 0xFE, 0xFF);
-
-	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(charger_dump, command_isl923x_dump,
-			"charger_dump <chgnum>", "Dumps ISL923x registers");
 #endif /* CONFIG_CMD_CHARGER_DUMP */
 
 static enum ec_error_list isl923x_get_vbus_voltage(int chgnum, int port,
@@ -1050,6 +1300,75 @@ static enum ec_error_list isl923x_get_vbus_voltage(int chgnum, int port,
 }
 
 #if defined(CONFIG_CHARGER_RAA489000) && defined(CONFIG_OCPC)
+static enum ec_error_list raa489000_enable_linear_charge(int chgnum,
+							 bool enable)
+{
+	const struct battery_info *batt_info;
+	int trickle_regval;
+	int precharge_current;
+	int regval;
+	enum ec_error_list rv;
+	int act_chg = charge_get_active_chg_chip();
+
+	batt_info = battery_get_info();
+
+	if (enable) {
+		/* Set the auxiliary max VSYS to 300mV + min VSYS. */
+		rv = isl9237_set_voltage(act_chg, batt_info->voltage_min + 300);
+
+		/* Disable charge current loop for the aux charger. */
+		rv |= raw_update16(act_chg, RAA489000_REG_CONTROL10,
+				   RAA489000_C10_DISABLE_DVC_CC_LOOP, MASK_SET);
+
+		/*
+		 * Set primary charger charge current to the desired precharge
+		 * current.
+		 */
+		rv |= isl9237_set_current(CHARGER_PRIMARY,
+					  batt_info->precharge_current);
+
+		/*
+		 * Set primary charger max VSYS to the max of the battery.
+		 */
+		rv |= isl9237_set_voltage(CHARGER_PRIMARY,
+					  batt_info->voltage_max);
+
+		/*
+		 * Set trickle charging level.
+		 *
+		 * 64mA is the minimum current level we must set.
+		 */
+		precharge_current = MAX(64, batt_info->precharge_current);
+		trickle_regval = precharge_current / 32;
+		trickle_regval--; /* convert to 0-based field */
+		rv |= raw_read16(CHARGER_PRIMARY, ISL923X_REG_CONTROL2,
+				 &regval);
+		regval &= ~(GENMASK(15, 13));
+		regval |= trickle_regval << 13;
+		rv |= raw_write16(CHARGER_PRIMARY, ISL923X_REG_CONTROL2,
+				  regval);
+
+		/* Enable DVC trickle charge and DVC charge mode. */
+		rv |= raw_update16(
+			CHARGER_PRIMARY, RAA489000_REG_CONTROL10,
+			RAA489000_C10_ENABLE_DVC_MODE |
+				RAA489000_C10_ENABLE_DVC_TRICKLE_CHARGE,
+			MASK_SET);
+
+		if (rv)
+			return EC_ERROR_UNKNOWN;
+
+	} else {
+		/* Disable DVC trickle charge. */
+		rv = raw_update16(CHARGER_PRIMARY, RAA489000_REG_CONTROL10,
+				  RAA489000_C10_ENABLE_DVC_TRICKLE_CHARGE,
+				  MASK_CLR);
+		rv |= isl9237_set_current(CHARGER_PRIMARY, 0);
+	}
+
+	return rv;
+}
+
 static enum ec_error_list raa489000_set_vsys_compensation(int chgnum,
 							  struct ocpc_data *o,
 							  int current_ma,
@@ -1164,6 +1483,71 @@ static enum ec_error_list raa489000_set_vsys_compensation(int chgnum,
 }
 #endif /* CONFIG_CHARGER_RAA489000 && CONFIG_OCPC */
 
+#ifdef CONFIG_PLATFORM_EC_RAA489000_AC_PRESENT_CONTROL
+/*
+ * If the device is in OTG mode, flip the comparator output
+ * so that the AC_PRESENT signal does not get asserted incorrectly
+ * (the comparator still operates in OTG mode).
+ * The main use case for this is in the factory where battery cut-off
+ * is performed, and the expectation is that the power will be supplied
+ * on port 0 (the primary charger port).
+ * This does not fully support the case where power is supplied
+ * by port 1, and a device on port 0 undergoes a role swap.
+ */
+void raa489000_check_ac_delayed(void)
+{
+	static bool current_val;
+	bool new_val;
+	int rv, regval;
+	int chgnum =
+#ifdef CONFIG_OCPC
+		CHARGER_PRIMARY;
+#else
+		0;
+#endif
+
+	rv = raw_read16(chgnum, ISL9238_REG_INFO2, &regval);
+	if (rv == EC_SUCCESS) {
+		new_val = (((regval >> RAA489000_INFO2_STATE_SHIFT) &
+			    RAA489000_INFO2_STATE_MASK) ==
+			   RAA489000_INFO2_STATE_OTG);
+		if (new_val != current_val) {
+			/*
+			 * If the mode has changed to/from OTG mode,
+			 * set the comparator output to be inverted (OTG mode)
+			 * or non-inverted.
+			 * In OTG mode, ACOK is always on, and AC_PRESENT should
+			 * be low.
+			 */
+			current_val = new_val;
+			isl923x_set_comparator_inversion(chgnum, new_val);
+		}
+	}
+}
+DECLARE_DEFERRED(raa489000_check_ac_delayed);
+
+void raa489000_check_ac_present(void)
+{
+	/*
+	 * The check is deferred for a short time since
+	 * the chip state machine status does not
+	 * update immediately.
+	 */
+	hook_call_deferred(&raa489000_check_ac_delayed_data, 1 * SECOND);
+}
+
+/*
+ * Several hooks are required to ensure the check is done
+ * for the relevant cases.
+ */
+DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, raa489000_check_ac_present,
+	     HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_USB_PD_CONNECT, raa489000_check_ac_present,
+	     HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_POWER_SUPPLY_CHANGE, raa489000_check_ac_present,
+	     HOOK_PRIO_DEFAULT);
+#endif /* CONFIG_PLATFORM_EC_RAA489000_AC_PRESENT_CONTROL */
+
 const struct charger_drv isl923x_drv = {
 	.init = &isl923x_init,
 	.post_init = &isl923x_post_init,
@@ -1173,15 +1557,26 @@ const struct charger_drv isl923x_drv = {
 #if defined(CONFIG_CHARGER_OTG) && defined(CHARGER_ISL9238X)
 	.enable_otg_power = &isl923x_enable_otg_power,
 	.set_otg_current_voltage = &isl923x_set_otg_current_voltage,
+#endif
+#ifdef CONFIG_CHARGER_RAA489000
+	.get_actual_current = &raa489000_get_actual_current,
 #endif
 	.get_current = &isl923x_get_current,
 	.set_current = &isl923x_set_current,
+#ifdef CONFIG_CHARGER_RAA489000
+	.get_actual_voltage = &raa489000_get_actual_voltage,
+#endif
 	.get_voltage = &isl923x_get_voltage,
 	.set_voltage = &isl923x_set_voltage,
 	.discharge_on_ac = &isl923x_discharge_on_ac,
 	.get_vbus_voltage = &isl923x_get_vbus_voltage,
-	.set_input_current = &isl923x_set_input_current,
+	.set_input_current_limit = &isl923x_set_input_current_limit,
+	.get_input_current_limit = &isl923x_get_input_current_limit,
+#ifdef CONFIG_CHARGER_RAA489000
+	.get_input_current = &raa489000_get_input_current,
+#elif defined(CONFIG_CMD_CHARGER_ADC_AMON_BMON)
 	.get_input_current = &isl923x_get_input_current,
+#endif
 	.manufacturer_id = &isl923x_manufacturer_id,
 	.device_id = &isl923x_device_id,
 	.get_option = &isl923x_get_option,
@@ -1193,6 +1588,10 @@ const struct charger_drv isl923x_drv = {
 	.ramp_get_current_limit = &isl923x_ramp_get_current_limit,
 #endif
 #if defined(CONFIG_CHARGER_RAA489000) && defined(CONFIG_OCPC)
+	.enable_linear_charge = &raa489000_enable_linear_charge,
 	.set_vsys_compensation = &raa489000_set_vsys_compensation,
 #endif
+#ifdef CONFIG_CMD_CHARGER_DUMP
+	.dump_registers = &command_isl923x_dump,
+#endif
 };
diff --git a/driver/charger/isl923x.h b/driver/charger/isl923x.h
index a09354d811..251d62dc99 100644
--- a/driver/charger/isl923x.h
+++ b/driver/charger/isl923x.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -9,32 +9,32 @@
 #ifndef __CROS_EC_ISL923X_H
 #define __CROS_EC_ISL923X_H
 
-#define ISL923X_ADDR_FLAGS	(0x09)
+#include "driver/charger/isl923x_public.h"
 
 /* Registers */
-#define ISL923X_REG_CHG_CURRENT      0x14
-#define ISL923X_REG_ADAPTER_CURRENT1 0x3f
-#define ISL923X_REG_ADAPTER_CURRENT2 0x3b
-#define ISL923X_REG_SYS_VOLTAGE_MAX  0x15
-#define ISL923X_REG_SYS_VOLTAGE_MIN  0x3e
-#define ISL923X_REG_PROCHOT_AC       0x47
-#define ISL923X_REG_PROCHOT_DC       0x48
-#define ISL923X_REG_T1_T2            0x38
-#define ISL923X_REG_CONTROL0         0x39
-#define ISL923X_REG_CONTROL1         0x3c
-#define ISL923X_REG_CONTROL2         0x3d
-#define ISL9238_REG_CONTROL3         0x4c
-#define ISL9238_REG_CONTROL4         0x4e
-#define ISL9238C_REG_CONTROL6        0x37
-#define ISL923X_REG_INFO             0x3a
-#define ISL9238_REG_INFO2            0x4d
-#define ISL923X_REG_OTG_VOLTAGE      0x49
-#define ISL923X_REG_OTG_CURRENT      0x4a
-#define ISL9238_REG_INPUT_VOLTAGE    0x4b
-#define ISL923X_REG_MANUFACTURER_ID  0xfe
-#define ISL923X_REG_DEVICE_ID        0xff
-#define RAA489000_REG_CONTROL8       0x37
-#define RAA489000_REG_CONTROL10      0x35
+#define ISL923X_REG_CHG_CURRENT 0x14
+#define ISL923X_REG_ADAPTER_CURRENT_LIMIT1 0x3f
+#define ISL923X_REG_ADAPTER_CURRENT_LIMIT2 0x3b
+#define ISL923X_REG_SYS_VOLTAGE_MAX 0x15
+#define ISL923X_REG_SYS_VOLTAGE_MIN 0x3e
+#define ISL923X_REG_PROCHOT_AC 0x47
+#define ISL923X_REG_PROCHOT_DC 0x48
+#define ISL923X_REG_T1_T2 0x38
+#define ISL923X_REG_CONTROL0 0x39
+#define ISL923X_REG_CONTROL1 0x3c
+#define ISL923X_REG_CONTROL2 0x3d
+#define ISL9238_REG_CONTROL3 0x4c
+#define ISL9238_REG_CONTROL4 0x4e
+#define ISL9238C_REG_CONTROL6 0x37
+#define ISL923X_REG_INFO 0x3a
+#define ISL9238_REG_INFO2 0x4d
+#define ISL923X_REG_OTG_VOLTAGE 0x49
+#define ISL923X_REG_OTG_CURRENT 0x4a
+#define ISL9238_REG_INPUT_VOLTAGE 0x4b
+#define ISL923X_REG_MANUFACTURER_ID 0xfe
+#define ISL923X_REG_DEVICE_ID 0xff
+#define RAA489000_REG_CONTROL8 0x37
+#define RAA489000_REG_CONTROL10 0x35
 
 /* Sense resistor default values in mOhm */
 #define ISL923X_DEFAULT_SENSE_RESISTOR_AC 20
@@ -42,24 +42,24 @@
 
 /* Maximum charging current register value */
 #define ISL923X_CURRENT_REG_MAX 0x17c0 /* bit<12:2> 10111110000 */
-#define RAA489000_CURRENT_REG_MAX 0x1ffc
+#define RAA489000_CURRENT_REG_MAX 0x17fc
 
 /* 2-level adpater current limit duration T1 & T2 in micro seconds */
 #define ISL923X_T1_10000 0x00
 #define ISL923X_T1_20000 0x01
 #define ISL923X_T1_15000 0x02
-#define ISL923X_T1_5000  0x03
-#define ISL923X_T1_1000  0x04
-#define ISL923X_T1_500   0x05
-#define ISL923X_T1_100   0x06
-#define ISL923X_T1_0     0x07
-#define ISL923X_T2_10    (0x00 << 8)
-#define ISL923X_T2_100   (0x01 << 8)
-#define ISL923X_T2_500   (0x02 << 8)
-#define ISL923X_T2_1000  (0x03 << 8)
-#define ISL923X_T2_300   (0x04 << 8)
-#define ISL923X_T2_750   (0x05 << 8)
-#define ISL923X_T2_2000  (0x06 << 8)
+#define ISL923X_T1_5000 0x03
+#define ISL923X_T1_1000 0x04
+#define ISL923X_T1_500 0x05
+#define ISL923X_T1_100 0x06
+#define ISL923X_T1_0 0x07
+#define ISL923X_T2_10 (0x00 << 8)
+#define ISL923X_T2_100 (0x01 << 8)
+#define ISL923X_T2_500 (0x02 << 8)
+#define ISL923X_T2_1000 (0x03 << 8)
+#define ISL923X_T2_300 (0x04 << 8)
+#define ISL923X_T2_750 (0x05 << 8)
+#define ISL923X_T2_2000 (0x06 << 8)
 #define ISL923X_T2_10000 (0x07 << 8)
 
 #define ISL9237_SYS_VOLTAGE_REG_MAX 13824
@@ -69,19 +69,19 @@
 #define RAA489000_SYS_VOLTAGE_REG_MIN 64
 
 /* PROCHOT# debounce time and duration time in micro seconds */
-#define ISL923X_PROCHOT_DURATION_10000  (0 << 6)
-#define ISL923X_PROCHOT_DURATION_20000  BIT(6)
-#define ISL923X_PROCHOT_DURATION_15000  (2 << 6)
-#define ISL923X_PROCHOT_DURATION_5000   (3 << 6)
-#define ISL923X_PROCHOT_DURATION_1000   (4 << 6)
-#define ISL923X_PROCHOT_DURATION_500    (5 << 6)
+#define ISL923X_PROCHOT_DURATION_10000 (0 << 6)
+#define ISL923X_PROCHOT_DURATION_20000 BIT(6)
+#define ISL923X_PROCHOT_DURATION_15000 (2 << 6)
+#define ISL923X_PROCHOT_DURATION_5000 (3 << 6)
+#define ISL923X_PROCHOT_DURATION_1000 (4 << 6)
+#define ISL923X_PROCHOT_DURATION_500 (5 << 6)
 #define ISL923X_PROCHOT_DURATION_100000 (6 << 6)
-#define ISL923X_PROCHOT_DURATION_0      (7 << 6)
-#define ISL923X_PROCHOT_DURATION_MASK   (7 << 6)
+#define ISL923X_PROCHOT_DURATION_0 (7 << 6)
+#define ISL923X_PROCHOT_DURATION_MASK (7 << 6)
 
-#define ISL923X_PROCHOT_DEBOUNCE_10   (0 << 9)
-#define ISL923X_PROCHOT_DEBOUNCE_100  BIT(9)
-#define ISL923X_PROCHOT_DEBOUNCE_500  (2 << 9)
+#define ISL923X_PROCHOT_DEBOUNCE_10 (0 << 9)
+#define ISL923X_PROCHOT_DEBOUNCE_100 BIT(9)
+#define ISL923X_PROCHOT_DEBOUNCE_500 (2 << 9)
 #define ISL923X_PROCHOT_DEBOUNCE_1000 (3 << 9)
 #define ISL923X_PROCHOT_DEBOUNCE_MASK (3 << 9)
 
@@ -97,29 +97,34 @@
 #define ISL9237_C0_VREG_REF_MASK 0x03
 
 /* Control0: disable adapter voltaqe regulation */
+#define ISL923X_C0_ENABLE_BUCK BIT(1)
 #define ISL923X_C0_DISABLE_VREG BIT(2)
 
 /* Control0: battery DCHOT reference for RS2 == 20mOhm */
-#define ISL923X_C0_DCHOT_6A   (0 << 3)
-#define ISL923X_C0_DCHOT_5A   BIT(3)
-#define ISL923X_C0_DCHOT_4A   (2 << 3)
-#define ISL923X_C0_DCHOT_3A   (3 << 3)
+#define ISL923X_C0_DCHOT_6A (0 << 3)
+#define ISL923X_C0_DCHOT_5A BIT(3)
+#define ISL923X_C0_DCHOT_4A (2 << 3)
+#define ISL923X_C0_DCHOT_3A (3 << 3)
 #define ISL923X_C0_DCHOT_MASK (3 << 3)
 
+/* Control0: adjusts phase comparator threshold offset for forward buck */
+#define ISL923X_C0_BUCK_PHASE_MASK GENMASK(15, 13)
+#define ISL923X_C0_BUCK_PHASE_SHIFT 13
+
 /* Control0: BGATE force on */
 #define RAA489000_C0_BGATE_FORCE_ON BIT(10)
 #define RAA489000_C0_EN_CHG_PUMPS_TO_100PCT BIT(6)
 
 /* Control1: general purpose comparator debounce time in micro second */
-#define ISL923X_C1_GP_DEBOUNCE_2       (0 << 14)
-#define ISL923X_C1_GP_DEBOUNCE_12      BIT(14)
-#define ISL923X_C1_GP_DEBOUNCE_2000    (2 << 14)
+#define ISL923X_C1_GP_DEBOUNCE_2 (0 << 14)
+#define ISL923X_C1_GP_DEBOUNCE_12 BIT(14)
+#define ISL923X_C1_GP_DEBOUNCE_2000 (2 << 14)
 #define ISL923X_C1_GP_DEBOUNCE_5000000 (3 << 14)
-#define ISL923X_C1_GP_DEBOUNCE_MASK    (3 << 14)
+#define ISL923X_C1_GP_DEBOUNCE_MASK (3 << 14)
 
 /* Control1: learn mode */
 #define ISL923X_C1_LEARN_MODE_AUTOEXIT BIT(13)
-#define ISL923X_C1_LEARN_MODE_ENABLE   BIT(12)
+#define ISL923X_C1_LEARN_MODE_ENABLE BIT(12)
 
 /* Control1: OTG enable */
 #define ISL923X_C1_OTG BIT(11)
@@ -161,15 +166,15 @@
 #define RAA489000_C1_BGATE_FORCE_OFF BIT(6)
 
 /* Control2: trickle charging current in mA */
-#define ISL923X_C2_TRICKLE_256  (0 << 14)
-#define ISL923X_C2_TRICKLE_128  BIT(14)
-#define ISL923X_C2_TRICKLE_64   (2 << 14)
-#define ISL923X_C2_TRICKLE_512  (3 << 14)
+#define ISL923X_C2_TRICKLE_256 (0 << 14)
+#define ISL923X_C2_TRICKLE_128 BIT(14)
+#define ISL923X_C2_TRICKLE_64 (2 << 14)
+#define ISL923X_C2_TRICKLE_512 (3 << 14)
 #define ISL923X_C2_TRICKLE_MASK (3 << 14)
 
 /* Control2: OTGEN debounce time in ms */
 #define ISL923X_C2_OTG_DEBOUNCE_1300 (0 << 13)
-#define ISL923X_C2_OTG_DEBOUNCE_150  BIT(13)
+#define ISL923X_C2_OTG_DEBOUNCE_150 BIT(13)
 #define ISL923X_C2_OTG_DEBOUNCE_MASK BIT(13)
 
 /* Control2: 2-level adapter over current */
@@ -177,14 +182,14 @@
 
 /* Control2: adapter insertion debounce time in ms */
 #define ISL923X_C2_ADAPTER_DEBOUNCE_1300 (0 << 11)
-#define ISL923X_C2_ADAPTER_DEBOUNCE_150  BIT(11)
+#define ISL923X_C2_ADAPTER_DEBOUNCE_150 BIT(11)
 #define ISL923X_C2_ADAPTER_DEBOUNCE_MASK BIT(11)
 
 /* Control2: PROCHOT debounce time in uS */
-#define ISL9238_C2_PROCHOT_DEBOUNCE_7    (0 << 9)
-#define ISL9237_C2_PROCHOT_DEBOUNCE_10   (0 << 9)
-#define ISL923X_C2_PROCHOT_DEBOUNCE_100  BIT(9)
-#define ISL923X_C2_PROCHOT_DEBOUNCE_500  (2 << 9)
+#define ISL9238_C2_PROCHOT_DEBOUNCE_7 (0 << 9)
+#define ISL9237_C2_PROCHOT_DEBOUNCE_10 (0 << 9)
+#define ISL923X_C2_PROCHOT_DEBOUNCE_100 BIT(9)
+#define ISL923X_C2_PROCHOT_DEBOUNCE_500 (2 << 9)
 #define ISL923X_C2_PROCHOT_DEBOUNCE_1000 (3 << 9)
 #define ISL923X_C2_PROCHOT_DEBOUNCE_MASK (3 << 9)
 
@@ -192,12 +197,12 @@
 #define ISL923X_C2_PROCHOT_DURATION_10000 (0 << 6)
 #define ISL923X_C2_PROCHOT_DURATION_20000 BIT(6)
 #define ISL923X_C2_PROCHOT_DURATION_15000 (2 << 6)
-#define ISL923X_C2_PROCHOT_DURATION_5000  (3 << 6)
-#define ISL923X_C2_PROCHOT_DURATION_1000  (4 << 6)
-#define ISL923X_C2_PROCHOT_DURATION_500   (5 << 6)
-#define ISL923X_C2_PROCHOT_DURATION_100   (6 << 6)
-#define ISL923X_C2_PROCHOT_DURATION_0     (7 << 6)
-#define ISL923X_C2_PROCHOT_DURATION_MASK  (7 << 6)
+#define ISL923X_C2_PROCHOT_DURATION_5000 (3 << 6)
+#define ISL923X_C2_PROCHOT_DURATION_1000 (4 << 6)
+#define ISL923X_C2_PROCHOT_DURATION_500 (5 << 6)
+#define ISL923X_C2_PROCHOT_DURATION_100 (6 << 6)
+#define ISL923X_C2_PROCHOT_DURATION_0 (7 << 6)
+#define ISL923X_C2_PROCHOT_DURATION_MASK (7 << 6)
 
 /* Control2: turn off ASGATE in OTG mode */
 #define ISL923X_C2_ASGATE_OFF BIT(5)
@@ -247,6 +252,9 @@
 /* Control3: Enables or disables Battery Ship mode */
 #define ISL9238_C3_BGATE_OFF BIT(10)
 
+/* Control3: Enable or disable DCM/CCM Hysteresis */
+#define RAA489000_C3_DCM_CCM_HYSTERESIS_ENABLE BIT(10)
+
 /* Control3: Don't reload ACLIM on ACIN. */
 #define ISL9238_C3_NO_RELOAD_ACLIM_ON_ACIN BIT(14)
 
@@ -259,11 +267,18 @@
 /* Control4: GP comparator control bit */
 #define RAA489000_C4_DISABLE_GP_CMP BIT(12)
 
+/* Control4: Ignores BATGONE input */
+#define RAA489000_C4_BATGONE_DISABLE BIT(15)
+
+/* Control6: enables the CMOUT latch function. */
+#define ISL9238C_C6_CMOUT_LATCH BIT(3)
+
 /* Control6: charger current and maximum system voltage slew rate control. */
 #define ISL9238C_C6_SLEW_RATE_CONTROL BIT(6)
 
 /* Control8: MCU_LDO - BAT state disable */
 #define RAA489000_C8_MCU_LDO_BAT_STATE_DISABLE BIT(14)
+#define RAA489000_C8_ASGATE_ON_READY BIT(13)
 
 /* OTG voltage limit in mV, current limit in mA */
 #define ISL9237_OTG_VOLTAGE_MIN 4864
@@ -287,6 +302,10 @@
 #define ISL923X_INFO_TRICKLE_ACTIVE_MASK BIT(4)
 #define ISL9237_INFO_PSTATE_SHIFT 5
 #define ISL9237_INFO_PSTATE_MASK 3
+#define RAA489000_INFO2_STATE_SHIFT 8
+#define RAA489000_INFO2_STATE_MASK 0xF
+#define RAA489000_INFO2_STATE_OTG 0x9
+#define RAA489000_INFO2_ACOK BIT(14)
 
 /* ADC registers */
 #define RAA489000_REG_ADC_INPUT_CURRENT 0x83
@@ -336,83 +355,9 @@ enum isl9237_fsm_state {
 #define RAA489000_C10_RP1_SHIFT 10
 #define RAA489000_C10_ENABLE_DVC_MODE BIT(15)
 
-#if defined(CONFIG_CHARGER_ISL9237)
-#define CHARGER_NAME  "isl9237"
-#define CHARGE_V_MAX  ISL9237_SYS_VOLTAGE_REG_MAX
-#define CHARGE_V_MIN  ISL923X_SYS_VOLTAGE_REG_MIN
-#define CHARGE_V_STEP 8
-#elif defined(CONFIG_CHARGER_ISL9238)
-#define CHARGER_NAME  "isl9238"
-#define CHARGE_V_MAX  ISL9238_SYS_VOLTAGE_REG_MAX
-#define CHARGE_V_MIN  ISL923X_SYS_VOLTAGE_REG_MIN
-#define CHARGE_V_STEP 8
-#elif defined(CONFIG_CHARGER_ISL9238C)
-#define CHARGER_NAME  "isl9238c"
-#define CHARGE_V_MAX  ISL9238_SYS_VOLTAGE_REG_MAX
-#define CHARGE_V_MIN  ISL923X_SYS_VOLTAGE_REG_MIN
-#define CHARGE_V_STEP 8
-#elif defined(CONFIG_CHARGER_RAA489000)
-#define CHARGER_NAME  "raa489000"
-#define CHARGE_V_MAX  RAA489000_SYS_VOLTAGE_REG_MAX
-#define CHARGE_V_MIN  RAA489000_SYS_VOLTAGE_REG_MIN
-#define CHARGE_V_STEP 64
-#endif
-
-#ifdef CONFIG_CHARGER_RAA489000
-#define CHARGE_I_MAX  RAA489000_CURRENT_REG_MAX
-#else
-#define CHARGE_I_MAX  ISL923X_CURRENT_REG_MAX
-#endif /* CONFIG_CHARGER_RAA489000 */
-#define CHARGE_I_MIN  4
-#define CHARGE_I_OFF  0
-#define CHARGE_I_STEP 4
-#ifdef CONFIG_CHARGER_RAA489000
-#define INPUT_I_MAX   RAA489000_CURRENT_REG_MAX
-#else
-#define INPUT_I_MAX   ISL923X_CURRENT_REG_MAX
-#endif /* CONFIG_CHARGER_RAA489000 */
-#define INPUT_I_MIN   4
-#define INPUT_I_STEP  4
-
 #define I2C_ADDR_CHARGER_FLAGS ISL923X_ADDR_FLAGS
 
-extern const struct charger_drv isl923x_drv;
+#define ISL923X_AC_PROCHOT_CURRENT_MAX 6400 /* mA */
+#define ISL923X_DC_PROCHOT_CURRENT_MAX 12800 /* mA */
 
 #endif /* __CROS_EC_ISL923X_H */
-
-/**
- * Initialize AC & DC prochot threshold
- *
- * @param	chgnum: Index into charger chips
- * @param	AC Prochot threshold current in mA:
- *			multiple of 128 up to 6400 mA
- *			DC Prochot threshold current in mA:
- *			multiple of 128 up to 12800 mA
- * 		Bits below 128mA are truncated (ignored).
- * @return enum ec_error_list
- */
-int isl923x_set_ac_prochot(int chgnum, uint16_t ma);
-int isl923x_set_dc_prochot(int chgnum, uint16_t ma);
-
-/**
- * Set the general comparator output polarity when asserted.
- *
- * @param chgnum: Index into charger chips
- * @param invert: Non-zero to invert polarity, zero to non-invert.
- * @return EC_SUCCESS, error otherwise.
- */
-int isl923x_set_comparator_inversion(int chgnum, int invert);
-
-/**
- * Prepare the charger IC for battery ship mode.  Battery ship mode sets the
- * lowest power state for the IC. Battery ship mode can only be entered from
- * battery only mode.
- *
- * @param chgnum index into chg_chips table.
- */
-void raa489000_hibernate(int chgnum);
-enum ec_error_list isl9238c_hibernate(int chgnum);
-enum ec_error_list isl9238c_resume(int chgnum);
-
-#define ISL923X_AC_PROCHOT_CURRENT_MAX	6400	/* mA */
-#define ISL923X_DC_PROCHOT_CURRENT_MAX	12800	/* mA */
diff --git a/driver/charger/isl9241.c b/driver/charger/isl9241.c
index d6dbf395d8..ce928bb46b 100644
--- a/driver/charger/isl9241.c
+++ b/driver/charger/isl9241.c
@@ -1,16 +1,21 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
- * Renesas (Intersil) ISL-9241 battery charger driver.
+ * Renesas (Intersil) ISL-9241 (and RAA489110) battery charger driver.
  */
 
+/* TODO(b/175881324) */
+#ifndef CONFIG_ZEPHYR
 #include "adc.h"
+#endif
 #include "battery.h"
 #include "battery_smart.h"
+#include "charge_manager.h"
+#include "charge_state.h"
 #include "charger.h"
-#include "console.h"
 #include "common.h"
+#include "console.h"
 #include "hooks.h"
 #include "i2c.h"
 #include "isl9241.h"
@@ -23,74 +28,77 @@
 #error "ISL9241 is a NVDC charger, please enable CONFIG_CHARGER_NARROW_VDC."
 #endif
 
-/* Sense resistor default values in milli Ohm */
-#define ISL9241_DEFAULT_RS1 20	/* Input current sense resistor */
-#define ISL9241_DEFAULT_RS2 10	/* Battery charge current sense resistor */
-
-#define BOARD_RS1 CONFIG_CHARGER_SENSE_RESISTOR_AC
-#define BOARD_RS2 CONFIG_CHARGER_SENSE_RESISTOR
-
-#define BC_REG_TO_CURRENT(REG) (((REG) * ISL9241_DEFAULT_RS2) / BOARD_RS2)
-#define BC_CURRENT_TO_REG(CUR) (((CUR) * BOARD_RS2) / ISL9241_DEFAULT_RS2)
-
-#define AC_REG_TO_CURRENT(REG) (((REG) * ISL9241_DEFAULT_RS1) / BOARD_RS1)
-#define AC_CURRENT_TO_REG(CUR) (((CUR) * BOARD_RS1) / ISL9241_DEFAULT_RS1)
-
 /* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, "ISL9241 " format, ##args)
 
 static int learn_mode;
 
 /* Mutex for CONTROL1 register, that can be updated from multiple tasks. */
-static struct mutex control1_mutex;
+K_MUTEX_DEFINE(control1_mutex_isl9241);
+
+/* Mutex for CONTROL3 register, that can be updated from multiple tasks. */
+K_MUTEX_DEFINE(control3_mutex_isl9241);
 
 /* Charger parameters */
 static const struct charger_info isl9241_charger_info = {
-	.name         = CHARGER_NAME,
-	.voltage_max  = CHARGE_V_MAX,
-	.voltage_min  = CHARGE_V_MIN,
+	.name = CHARGER_NAME,
+	.voltage_max = CHARGE_V_MAX,
+	.voltage_min = CHARGE_V_MIN,
 	.voltage_step = CHARGE_V_STEP,
-	.current_max  = CHARGE_I_MAX,
-	.current_min  = CHARGE_I_MIN,
-	.current_step = CHARGE_I_STEP,
-	.input_current_max  = INPUT_I_MAX,
-	.input_current_min  = INPUT_I_MIN,
-	.input_current_step = INPUT_I_STEP,
+	.current_max = BC_REG_TO_CURRENT(CHARGE_I_MAX),
+	.current_min = BC_REG_TO_CURRENT(CHARGE_I_MIN),
+	.current_step = BC_REG_TO_CURRENT(CHARGE_I_STEP),
+	.input_current_max = AC_REG_TO_CURRENT(INPUT_I_MAX),
+	.input_current_min = AC_REG_TO_CURRENT(INPUT_I_MIN),
+	.input_current_step = AC_REG_TO_CURRENT(INPUT_I_STEP),
 };
 
 static enum ec_error_list isl9241_discharge_on_ac(int chgnum, int enable);
+static enum ec_error_list isl9241_discharge_on_ac_unsafe(int chgnum,
+							 int enable);
+static enum ec_error_list isl9241_discharge_on_ac_weak_disable(int chgnum);
 
 static inline enum ec_error_list isl9241_read(int chgnum, int offset,
 					      int *value)
 {
-	return i2c_read16(chg_chips[chgnum].i2c_port,
-			  chg_chips[chgnum].i2c_addr_flags,
-			  offset, value);
+	int rv = i2c_read16(chg_chips[chgnum].i2c_port,
+			    chg_chips[chgnum].i2c_addr_flags, offset, value);
+	if (rv)
+		CPRINTS("%s failed (%d)", __func__, rv);
+
+	return rv;
 }
 
 static inline enum ec_error_list isl9241_write(int chgnum, int offset,
 					       int value)
 {
-	return i2c_write16(chg_chips[chgnum].i2c_port,
-			   chg_chips[chgnum].i2c_addr_flags,
-			   offset, value);
+	int rv = i2c_write16(chg_chips[chgnum].i2c_port,
+			     chg_chips[chgnum].i2c_addr_flags, offset, value);
+	if (rv)
+		CPRINTS("%s failed (%d)", __func__, rv);
+
+	return rv;
 }
 
 static inline enum ec_error_list isl9241_update(int chgnum, int offset,
 						uint16_t mask,
 						enum mask_update_action action)
 {
-	return i2c_update16(chg_chips[chgnum].i2c_port,
-			    chg_chips[chgnum].i2c_addr_flags,
-			    offset, mask, action);
+	int rv = i2c_update16(chg_chips[chgnum].i2c_port,
+			      chg_chips[chgnum].i2c_addr_flags, offset, mask,
+			      action);
+	if (rv)
+		CPRINTS("%s failed (%d)", __func__, rv);
+
+	return rv;
 }
 
 /* chip specific interfaces */
 
 /*****************************************************************************/
 /* Charger interfaces */
-static enum ec_error_list isl9241_set_input_current(int chgnum,
-						    int input_current)
+static enum ec_error_list isl9241_set_input_current_limit(int chgnum,
+							  int input_current)
 {
 	int rv;
 	uint16_t reg = AC_CURRENT_TO_REG(input_current);
@@ -102,8 +110,8 @@ static enum ec_error_list isl9241_set_input_current(int chgnum,
 	return isl9241_write(chgnum, ISL9241_REG_ADAPTER_CUR_LIMIT2, reg);
 }
 
-static enum ec_error_list isl9241_get_input_current(int chgnum,
-						    int *input_current)
+static enum ec_error_list isl9241_get_input_current_limit(int chgnum,
+							  int *input_current)
 {
 	int rv;
 
@@ -126,6 +134,53 @@ static enum ec_error_list isl9241_device_id(int chgnum, int *id)
 	return isl9241_read(chgnum, ISL9241_REG_DEVICE_ID, id);
 }
 
+static enum ec_error_list isl9241_set_frequency(int chgnum, int freq_khz)
+{
+	int rv;
+	int reg;
+	int freq;
+
+	mutex_lock(&control1_mutex_isl9241);
+	rv = isl9241_read(chgnum, ISL9241_REG_CONTROL1, &reg);
+	if (rv) {
+		CPRINTS("Could not read CONTROL1. (rv=%d)", rv);
+		return rv;
+	}
+	/* 000 = 1420kHz */
+	/* 001 = 1180kHz */
+	/* 010 = 1020kHz */
+	/* 011 = 890kHz  */
+	/* 100 = 808kHz  */
+	/* 101 = 724kHz  */
+	/* 110 = 656kHz  */
+	/* 111 = 600kHz  */
+	if (freq_khz >= 1300)
+		freq = ISL9241_CONTROL1_SWITCHING_FREQ_1420KHZ;
+	else if (freq_khz >= 1100)
+		freq = ISL9241_CONTROL1_SWITCHING_FREQ_1180KHZ;
+	else if (freq_khz >= 955)
+		freq = ISL9241_CONTROL1_SWITCHING_FREQ_1020KHZ;
+	else if (freq_khz >= 849)
+		freq = ISL9241_CONTROL1_SWITCHING_FREQ_890KHZ;
+	else if (freq_khz >= 766)
+		freq = ISL9241_CONTROL1_SWITCHING_FREQ_808KHZ;
+	else if (freq_khz >= 690)
+		freq = ISL9241_CONTROL1_SWITCHING_FREQ_724KHZ;
+	else if (freq_khz >= 628)
+		freq = ISL9241_CONTROL1_SWITCHING_FREQ_656KHZ;
+	else
+		freq = ISL9241_CONTROL1_SWITCHING_FREQ_600KHZ;
+
+	reg &= ~ISL9241_CONTROL1_SWITCHING_FREQ_MASK;
+	reg |= (freq << 7);
+	rv = isl9241_write(chgnum, ISL9241_REG_CONTROL1, reg);
+	if (rv)
+		return rv;
+
+	mutex_unlock(&control1_mutex_isl9241);
+	return EC_SUCCESS;
+}
+
 static enum ec_error_list isl9241_get_option(int chgnum, int *option)
 {
 	int rv;
@@ -163,6 +218,19 @@ static const struct charger_info *isl9241_get_info(int chgnum)
 	return &isl9241_charger_info;
 }
 
+static enum ec_error_list isl9241_bypass_mode_enabled(int chgnum, int *enabled)
+{
+	int reg, rv;
+
+	rv = isl9241_read(chgnum, ISL9241_REG_CONTROL0, &reg);
+	if (rv)
+		return rv;
+
+	*enabled = !!(reg & ISL9241_CONTROL0_EN_BYPASS_GATE);
+
+	return EC_SUCCESS;
+}
+
 static enum ec_error_list isl9241_get_status(int chgnum, int *status)
 {
 	int rv;
@@ -187,6 +255,13 @@ static enum ec_error_list isl9241_get_status(int chgnum, int *status)
 	if (reg & ISL9241_INFORMATION2_ACOK_PIN)
 		*status |= CHARGER_AC_PRESENT;
 
+	/* Bypass mode status */
+	rv = isl9241_bypass_mode_enabled(chgnum, &reg);
+	if (rv)
+		return rv;
+	if (reg)
+		*status |= CHARGER_BYPASS_MODE;
+
 	return EC_SUCCESS;
 }
 
@@ -195,29 +270,30 @@ static enum ec_error_list isl9241_set_mode(int chgnum, int mode)
 	int rv;
 
 	/*
-	 * See crosbug.com/p/51196. Always disable learn mode unless it was set
-	 * explicitly.
+	 * See crosbug.com/p/51196.
+	 * Disable learn mode if it wasn't explicitly enabled.
 	 */
-	if (!learn_mode) {
-		rv = isl9241_discharge_on_ac(chgnum, 0);
-		if (rv)
-			return rv;
-	}
+	rv = isl9241_discharge_on_ac_weak_disable(chgnum);
+	if (rv)
+		return rv;
 
 	/*
 	 * Charger inhibit
 	 * MinSystemVoltage 0x00h = disables all battery charging
 	 */
 	rv = isl9241_write(chgnum, ISL9241_REG_MIN_SYSTEM_VOLTAGE,
-		mode & CHARGE_FLAG_INHIBIT_CHARGE ?
-		0 : battery_get_info()->voltage_min);
+			   mode & CHARGE_FLAG_INHIBIT_CHARGE ?
+				   0 :
+				   battery_get_info()->voltage_min);
 	if (rv)
 		return rv;
 
 	/* POR reset */
 	if (mode & CHARGE_FLAG_POR_RESET) {
+		mutex_lock(&control3_mutex_isl9241);
 		rv = isl9241_write(chgnum, ISL9241_REG_CONTROL3,
-			ISL9241_CONTROL3_DIGITAL_RESET);
+				   ISL9241_CONTROL3_DIGITAL_RESET);
+		mutex_unlock(&control3_mutex_isl9241);
 	}
 
 	return rv;
@@ -238,7 +314,7 @@ static enum ec_error_list isl9241_get_current(int chgnum, int *current)
 static enum ec_error_list isl9241_set_current(int chgnum, int current)
 {
 	return isl9241_write(chgnum, ISL9241_REG_CHG_CURRENT_LIMIT,
-				BC_CURRENT_TO_REG(current));
+			     BC_CURRENT_TO_REG(current));
 }
 
 static enum ec_error_list isl9241_get_voltage(int chgnum, int *voltage)
@@ -259,6 +335,7 @@ static enum ec_error_list isl9241_get_vbus_voltage(int chgnum, int port,
 	int rv;
 
 	/* Get current Control3 value */
+	mutex_lock(&control3_mutex_isl9241);
 	rv = isl9241_read(chgnum, ISL9241_REG_CONTROL3, &ctl3_val);
 	if (rv)
 		goto error;
@@ -293,51 +370,906 @@ static enum ec_error_list isl9241_get_vbus_voltage(int chgnum, int port,
 		(void)isl9241_write(chgnum, ISL9241_REG_CONTROL3, ctl3_val);
 
 error:
+	mutex_unlock(&control3_mutex_isl9241);
 	if (rv)
-		CPRINTF("Could not read VBUS ADC! Error: %d\n", rv);
+		CPRINTS("Could not read VBUS ADC! Error: %d", rv);
 
 	return rv;
 }
 
-static enum ec_error_list isl9241_post_init(int chgnum)
+/**
+ * Mutex less version of isl9241_get_vsys_voltage. This should be called only
+ * if control3_mutex_isl9241 is already locked.
+ */
+static enum ec_error_list _get_vsys_voltage(int chgnum, int port, int *voltage)
 {
-	return EC_SUCCESS;
+	int val = 0;
+	int rv = EC_SUCCESS;
+
+	rv = isl9241_update(chgnum, ISL9241_REG_CONTROL3,
+			    ISL9241_CONTROL3_ENABLE_ADC, MASK_SET);
+	if (rv) {
+		CPRINTS("Could not enable ADC for Vsys. (rv=%d)", rv);
+		return rv;
+	}
+
+	usleep(ISL9241_ADC_POLLING_TIME_US);
+
+	/* Read voltage ADC value */
+	rv = isl9241_read(chgnum, ISL9241_REG_VSYS_ADC_RESULTS, &val);
+	if (rv) {
+		CPRINTS("Could not read Vsys. (rv=%d)", rv);
+		isl9241_update(chgnum, ISL9241_REG_CONTROL3,
+			       ISL9241_CONTROL3_ENABLE_ADC, MASK_CLR);
+		return rv;
+	}
+
+	/* Adjust adc_val. Same as Vin. */
+	val >>= ISL9241_VIN_ADC_BIT_OFFSET;
+	val *= ISL9241_VIN_ADC_STEP_MV;
+	*voltage = val;
+
+	return rv;
 }
 
-static enum ec_error_list isl9241_discharge_on_ac(int chgnum, int enable)
+static enum ec_error_list isl9241_get_vsys_voltage(int chgnum, int port,
+						   int *voltage)
 {
 	int rv;
 
-	mutex_lock(&control1_mutex);
+	mutex_lock(&control3_mutex_isl9241);
+	rv = _get_vsys_voltage(chgnum, port, voltage);
+	mutex_unlock(&control3_mutex_isl9241);
 
-	rv = isl9241_update(chgnum, ISL9241_REG_CONTROL1,
-			    ISL9241_CONTROL1_LEARN_MODE,
-			    (enable) ? MASK_SET : MASK_CLR);
+	return rv;
+}
+
+static enum ec_error_list isl9241_post_init(int chgnum)
+{
+	return EC_SUCCESS;
+}
+
+/*
+ * Writes to ISL9241_REG_CONTROL1, unsafe as it does not lock
+ * control1_mutex_isl9241.
+ */
+static enum ec_error_list isl9241_discharge_on_ac_unsafe(int chgnum, int enable)
+{
+	int rv = isl9241_update(chgnum, ISL9241_REG_CONTROL1,
+				ISL9241_CONTROL1_LEARN_MODE,
+				(enable) ? MASK_SET : MASK_CLR);
 	if (!rv)
 		learn_mode = enable;
 
-	mutex_unlock(&control1_mutex);
+	return rv;
+}
+
+/* Disables discharge on ac only if it wasn't explicitly enabled. */
+static enum ec_error_list isl9241_discharge_on_ac_weak_disable(int chgnum)
+{
+	int rv = 0;
+
+	mutex_lock(&control1_mutex_isl9241);
+	if (!learn_mode) {
+		rv = isl9241_discharge_on_ac_unsafe(chgnum, 0);
+	}
+
+	mutex_unlock(&control1_mutex_isl9241);
+	return rv;
+}
+
+static enum ec_error_list isl9241_discharge_on_ac(int chgnum, int enable)
+{
+	int rv = 0;
+
+	mutex_lock(&control1_mutex_isl9241);
+	rv = isl9241_discharge_on_ac_unsafe(chgnum, enable);
+	mutex_unlock(&control1_mutex_isl9241);
 	return rv;
 }
 
 int isl9241_set_ac_prochot(int chgnum, int ma)
 {
 	int rv;
-	uint16_t reg = AC_CURRENT_TO_REG(ma);
+	uint16_t reg;
+
+	/*
+	 * The register reserves bits [6:0] ([4:0] for rsa489110) and bits
+	 * [15:13]. This routine should ensure these bits are not set before
+	 * writing the register.
+	 */
+
+	if (ma > AC_REG_TO_CURRENT(ISL9241_AC_PROCHOT_CURRENT_MAX))
+		reg = AC_CURRENT_TO_REG(ISL9241_AC_PROCHOT_CURRENT_MAX);
+	else if (ma < AC_REG_TO_CURRENT(ISL9241_AC_PROCHOT_CURRENT_MIN))
+		reg = AC_CURRENT_TO_REG(ISL9241_AC_PROCHOT_CURRENT_MIN);
+	else
+		reg = AC_CURRENT_TO_REG(ma);
 
 	rv = isl9241_write(chgnum, ISL9241_REG_AC_PROCHOT, reg);
 	if (rv)
-		CPRINTF("set_ac_prochot failed (%d)", rv);
+		CPRINTS("set_ac_prochot failed (%d)", rv);
+
+	return rv;
+}
+
+int isl9241_set_dc_prochot(int chgnum, int ma)
+{
+	int rv;
+
+	/*
+	 * The register reserves bits [7:0] ([5:0] for RAA489110) and bits
+	 * [15:14]. This routine should ensure these bits are not set before
+	 * writing the register.
+	 */
+	if (ma > ISL9241_DC_PROCHOT_CURRENT_MAX)
+		ma = ISL9241_DC_PROCHOT_CURRENT_MAX;
+	else if (ma < ISL9241_DC_PROCHOT_CURRENT_MIN)
+		ma = ISL9241_DC_PROCHOT_CURRENT_MIN;
+
+	rv = isl9241_write(chgnum, ISL9241_REG_DC_PROCHOT, ma);
+	if (rv)
+		CPRINTS("set_dc_prochot failed (%d)", rv);
+
+	return rv;
+}
+
+#ifdef CONFIG_CHARGER_DUMP_PROCHOT
+static int isl9241_get_ac_prochot(int chgnum, int *out_ma)
+{
+	return isl9241_read(chgnum, ISL9241_REG_AC_PROCHOT, out_ma);
+}
+
+static int isl9241_get_dc_prochot(int chgnum, int *out_ma)
+{
+	return isl9241_read(chgnum, ISL9241_REG_DC_PROCHOT, out_ma);
+}
+
+static int isl9241_get_prochot_status(int chgnum, bool *out_low_vsys,
+				      bool *out_dcprochot, bool *out_acprochot,
+				      int *out_input_current,
+				      int *out_charge_current,
+				      int *out_discharge_current, int *out_vsys,
+				      int *out_vbus)
+{
+	int rv;
+	int val;
+	bool restore_adc = false;
+
+	/* Get prochot statuses. */
+	rv = isl9241_read(chgnum, ISL9241_REG_INFORMATION1, &val);
+	if (rv) {
+		CPRINTS("%s: failed to read prochot status (%d)", __func__, rv);
+		return rv;
+	}
+
+	*out_low_vsys = val & ISL9241_REG_INFORMATION1_LOW_VSYS_PROCHOT;
+	*out_dcprochot = val & ISL9241_REG_INFORMATION1_DC_PROCHOT;
+	*out_acprochot = val & ISL9241_REG_INFORMATION1_AC_PROCHOT;
+
+	/* Get current Control3 value */
+	mutex_lock(&control3_mutex_isl9241);
+	rv = isl9241_read(chgnum, ISL9241_REG_CONTROL3, &val);
+	if (rv) {
+		CPRINTS("%s: failed to read control3 (%d)", __func__, rv);
+		goto restore_control3;
+	}
+
+	/* Enable ADC */
+	if (!(val & ISL9241_CONTROL3_ENABLE_ADC)) {
+		rv = isl9241_write(chgnum, ISL9241_REG_CONTROL3,
+				   val | ISL9241_CONTROL3_ENABLE_ADC);
+		if (rv) {
+			CPRINTS("%s: failed to enable ADC (%d)", __func__, rv);
+			goto restore_control3;
+		}
+
+		restore_adc = true;
+	}
+
+	usleep(ISL9241_ADC_POLLING_TIME_US);
+
+	/* Get input current */
+	rv = isl9241_read(chgnum, ISL9241_REG_IADP_ADC_RESULTS,
+			  out_input_current);
+	if (rv) {
+		CPRINTS("%s: failed to get input current (%d)", __func__, rv);
+		goto restore_control3;
+	}
+
+	/* Input current is in steps of 22.2 mA, occupies bits 0-7 */
+	*out_input_current &= 0xff;
+	*out_input_current = (*out_input_current * 222) / 10;
+
+	/* Get battery discharge current */
+	rv = isl9241_read(chgnum, ISL9241_REG_DC_ADC_RESULTS,
+			  out_discharge_current);
+	if (rv) {
+		CPRINTS("%s: failed to get battery discharge current (%d)",
+			__func__, rv);
+		goto restore_control3;
+	}
+
+	/* Discharge current is in steps of 44.4 mA, occupies bits 0-7 */
+	*out_discharge_current &= 0xff;
+	*out_discharge_current = (*out_discharge_current * 444) / 10;
+
+	/* Get battery charge current */
+	rv = isl9241_read(chgnum, ISL9241_REG_CC_ADC_RESULTS,
+			  out_charge_current);
+	if (rv) {
+		CPRINTS("%s: failed to get battery charge current (%d)",
+			__func__, rv);
+		goto restore_control3;
+	}
+
+	/* Discharge current is in steps of 22.2 mA, occupies bits 0-7 */
+	*out_charge_current &= 0xff;
+	*out_charge_current = (*out_charge_current * 222) / 10;
+
+	/* Get Vsys */
+	rv = isl9241_read(chgnum, ISL9241_REG_VSYS_ADC_RESULTS, out_vsys);
+	if (rv) {
+		CPRINTS("%s: failed to get vsys (%d)", __func__, rv);
+		goto restore_control3;
+	}
+
+	/* Bits [13:6] hold the value in steps of 96 mV, same as Vbus */
+	*out_vsys >>= ISL9241_VIN_ADC_BIT_OFFSET;
+	*out_vsys *= ISL9241_VIN_ADC_STEP_MV;
+
+	/* Get Vbus */
+	rv = isl9241_read(chgnum, ISL9241_REG_VIN_ADC_RESULTS, out_vbus);
+	if (rv) {
+		CPRINTS("%s: failed to get vbus (%d)", __func__, rv);
+		goto restore_control3;
+	}
+
+	/* Bits [13:6] hold the value in steps of 96 mV */
+	*out_vbus >>= ISL9241_VIN_ADC_BIT_OFFSET;
+	*out_vbus *= ISL9241_VIN_ADC_STEP_MV;
+
+restore_control3:
+	if (restore_adc) {
+		/* Disable ADC measurements */
+		rv = isl9241_update(chgnum, ISL9241_REG_CONTROL3,
+				    ISL9241_CONTROL3_ENABLE_ADC, MASK_CLR);
+		if (rv)
+			CPRINTS("%s: failed to disable ADC (%d)", __func__, rv);
+	}
+	mutex_unlock(&control3_mutex_isl9241);
+
+	return rv;
+}
+
+static void isl9241_dump_prochot_status(int chgnum)
+{
+	int input_current = 0;
+	int battery_charge = 0;
+	int battery_discharge = 0;
+	int vsys = 0;
+	int vin = 0;
+	int dc_prochot_limit = 0;
+	int ac_prochot_limit = 0;
+	bool low_vsys_prochot = false;
+	bool dc_prochot = false;
+	bool ac_prochot = false;
+	int rv = 0;
+
+	rv = isl9241_get_ac_prochot(chgnum, &ac_prochot_limit);
+	if (rv) {
+		CPRINTS("Failed to get prochot AC limit (%d)", rv);
+		return;
+	}
+
+	rv = isl9241_get_dc_prochot(chgnum, &dc_prochot_limit);
+	if (rv) {
+		CPRINTS("Failed to get prochot DC limit (%d)", rv);
+		return;
+	}
+
+	rv = isl9241_get_prochot_status(chgnum, &low_vsys_prochot, &dc_prochot,
+					&ac_prochot, &input_current,
+					&battery_charge, &battery_discharge,
+					&vsys, &vin);
+	if (rv) {
+		CPRINTS("Failed to get prochot status (%d)", rv);
+		return;
+	}
+
+	CPRINTS("prochot status for charger %d", chgnum);
+	CPRINTS("\tProchot status: %s %s %s", low_vsys_prochot ? "LOWVSYS" : "",
+		dc_prochot ? "DC" : "", ac_prochot ? "AC" : "");
+
+	CPRINTS("\tDC prochot limit: %d mA", dc_prochot_limit);
+	CPRINTS("\tAC prochot limit: %d mA", ac_prochot_limit);
+	CPRINTS("\tInput current: %d mA", input_current);
+	CPRINTS("\tBattery charge current: %d mA", battery_charge);
+	CPRINTS("\tBattery discharge current: %d mA", battery_discharge);
+	CPRINTS("\tVsys: %d mV", vsys);
+	CPRINTS("\tVin: %d mV", vin);
+}
+#endif
+
+#ifdef CONFIG_CHARGER_BYPASS_MODE
+static bool isl9241_is_ac_present(int chgnum)
+{
+	static bool ac_is_present;
+	int reg;
+	int rv;
+
+	rv = isl9241_read(chgnum, ISL9241_REG_INFORMATION2, &reg);
+	if (rv == EC_SUCCESS)
+		ac_is_present = !!(reg & ISL9241_INFORMATION2_ACOK_PIN);
+
+	return ac_is_present;
+}
+
+/*
+ * Check whether ISL9241 is in any CHRG state, including NVDC+CHRG, Bypass+CHRG,
+ * RTB+CHRG.
+ */
+static bool isl9241_is_in_chrg(int chgnum)
+{
+	static bool trickle_charge_enabled, fast_charge_enabled;
+	int reg;
+	int rv;
+
+	rv = isl9241_read(chgnum, ISL9241_REG_MIN_SYSTEM_VOLTAGE, &reg);
+	if (rv == EC_SUCCESS)
+		trickle_charge_enabled = reg > 0;
+
+	rv = isl9241_read(chgnum, ISL9241_REG_CHG_CURRENT_LIMIT, &reg);
+	if (rv == EC_SUCCESS)
+		fast_charge_enabled = reg > 0;
+
+	return trickle_charge_enabled || fast_charge_enabled;
+}
+
+static enum ec_error_list
+isl9241_update_force_buck_mode(int chgnum, enum mask_update_action action)
+{
+	if (IS_ENABLED(CONFIG_CHARGER_ISL9241))
+		return isl9241_update(chgnum, ISL9241_REG_CONTROL4,
+				      ISL9241_CONTROL4_FORCE_BUCK_MODE, action);
+	else
+		/* CONFIG_CHARGER_RAA489110 */
+		return isl9241_update(chgnum, ISL9241_REG_CONTROL0,
+				      RAA489110_CONTROL0_EN_FORCE_BUCK_MODE,
+				      action);
+}
+
+/*
+ * Transition from Bypass to BAT.
+ */
+static enum ec_error_list isl9241_bypass_to_bat(int chgnum)
+{
+	const struct battery_info *bi = battery_get_info();
+
+	CPRINTS("bypass -> bat");
+
+	mutex_lock(&control3_mutex_isl9241);
+	/* 1: Disable force forward buck/reverse boost. */
+	isl9241_update_force_buck_mode(chgnum, MASK_CLR);
+
+	/*
+	 * 2: Turn off BYPSG, turn on NGATE, disable charge pump 100%, disable
+	 *    Vin<Vout comparator.
+	 */
+	isl9241_write(chgnum, ISL9241_REG_CONTROL0, 0);
+
+	/* 3: Set MaxSysVoltage to full charge. */
+	isl9241_write(chgnum, ISL9241_REG_MAX_SYSTEM_VOLTAGE, bi->voltage_max);
+
+	/* 4: Disable ADC. */
+	isl9241_update(chgnum, ISL9241_REG_CONTROL3,
+		       ISL9241_CONTROL3_ENABLE_ADC, MASK_CLR);
+
+	/* 5: Set BGATE to normal operation. */
+	isl9241_update(chgnum, ISL9241_REG_CONTROL1, ISL9241_CONTROL1_BGATE_OFF,
+		       MASK_CLR);
+
+	/* 6: Set ACOK reference to normal value. TODO: Revisit. */
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+	isl9241_write(chgnum, ISL9241_REG_ACOK_REFERENCE,
+		      ISL9241_MV_TO_ACOK_REFERENCE(4000));
+#else
+	isl9241_write(chgnum, ISL9241_REG_ACOK_REFERENCE,
+		      ISL9241_MV_TO_ACOK_REFERENCE(
+			      ISL9241_ACOK_REF_LOW_VOLTAGE_ADAPTER_MV));
+#endif
+	mutex_unlock(&control3_mutex_isl9241);
+	return EC_SUCCESS;
+}
+
+/*
+ * Transition from Bypass+CHRG to BAT (M).
+ */
+static enum ec_error_list isl9241_bypass_chrg_to_bat(int chgnum)
+{
+	CPRINTS("bypass_chrg -> bat");
+
+	mutex_lock(&control3_mutex_isl9241);
+	/* 1: Disable force forward buck/reverse boost. */
+	isl9241_update_force_buck_mode(chgnum, MASK_CLR);
+	/* 2: Disable fast charge. */
+	isl9241_write(chgnum, ISL9241_REG_CHG_CURRENT_LIMIT, 0);
+	/* 3: Disable trickle charge. */
+	isl9241_write(chgnum, ISL9241_REG_MIN_SYSTEM_VOLTAGE, 0);
+	/*
+	 * 4: Turn off BYPSG, turn on NGATE, disable charge pump 100%, disable
+	 *     Vin<Vout comparator.
+	 */
+	isl9241_write(chgnum, ISL9241_REG_CONTROL0, 0);
+	/* 5: Disable ADC. */
+	isl9241_update(chgnum, ISL9241_REG_CONTROL3,
+		       ISL9241_CONTROL3_ENABLE_ADC, MASK_CLR);
+	/* 6: Set BGATE to normal operation. */
+	isl9241_update(chgnum, ISL9241_REG_CONTROL1, ISL9241_CONTROL1_BGATE_OFF,
+		       MASK_CLR);
+	/* 7: Set ACOK reference to normal value. TODO: Revisit. */
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+	isl9241_write(chgnum, ISL9241_REG_ACOK_REFERENCE,
+		      ISL9241_MV_TO_ACOK_REFERENCE(4000));
+#else
+	isl9241_write(chgnum, ISL9241_REG_ACOK_REFERENCE,
+		      ISL9241_MV_TO_ACOK_REFERENCE(3600));
+#endif
+	mutex_unlock(&control3_mutex_isl9241);
+	return EC_SUCCESS;
+}
+
+/*
+ * Transition from NVDC+CHRG to NVDC (L).
+ */
+static enum ec_error_list isl9241_nvdc_chrg_to_nvdc(int chgnum)
+{
+	enum ec_error_list rv;
+
+	CPRINTS("nvdc_chrg -> nvdc");
+
+	/* L: If we're in NVDC+Chg, first transition to NVDC. */
+	/* 1: Disable fast charge. */
+	rv = isl9241_set_current(chgnum, 0);
+	if (rv)
+		return rv;
+
+	/* 2: Disable trickle charge. */
+	rv = isl9241_write(chgnum, ISL9241_REG_MIN_SYSTEM_VOLTAGE, 0);
+	if (rv)
+		return rv;
+
+	return EC_SUCCESS;
+}
+
+static enum ec_error_list isl9241_enable_bypass_mode(int chgnum, bool enable);
+
+/*
+ * Transition from NVDC to Bypass (A).
+ */
+static enum ec_error_list isl9241_nvdc_to_bypass(int chgnum)
+{
+	const struct battery_info *bi = battery_get_info();
+	const int charge_current = charge_manager_get_charger_current();
+	const int charge_voltage = charge_manager_get_charger_voltage();
+	int vsys, vsys_target;
+	int rv = EC_SUCCESS;
+	timestamp_t deadline;
+
+	CPRINTS("nvdc -> bypass");
+
+	mutex_lock(&control3_mutex_isl9241);
+	/* 1: Set adapter current limit. */
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+	board_set_charge_limit(0, 0, charge_current, 0, charge_voltage);
+#else
+	isl9241_set_input_current_limit(chgnum, charge_current);
+#endif
+
+	/* 2: Set charge pumps to 100%. */
+	isl9241_update(chgnum, ISL9241_REG_CONTROL0,
+		       ISL9241_CONTROL0_EN_CHARGE_PUMPS, MASK_SET);
+
+	/* 3: Enable ADC. */
+	isl9241_update(chgnum, ISL9241_REG_CONTROL3,
+		       ISL9241_CONTROL3_ENABLE_ADC, MASK_SET);
+
+	/* 4: Turn on Vin/Vout comparator. */
+	isl9241_update(chgnum, ISL9241_REG_CONTROL0,
+		       ISL9241_CONTROL0_EN_VIN_VOUT_COMP, MASK_SET);
+
+	/* 5: Set ACOK reference higher than battery full voltage. */
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+	isl9241_write(chgnum, ISL9241_REG_ACOK_REFERENCE,
+		      ISL9241_MV_TO_ACOK_REFERENCE(bi->voltage_max + 1100));
+#else
+	isl9241_write(chgnum, ISL9241_REG_ACOK_REFERENCE,
+		      ISL9241_MV_TO_ACOK_REFERENCE(bi->voltage_max + 800));
+#endif
+
+	/* 6*: Reduce system load below ACLIM. */
+	/* 7: Turn off BGATE */
+	isl9241_update(chgnum, ISL9241_REG_CONTROL1, ISL9241_CONTROL1_BGATE_OFF,
+		       MASK_SET);
+
+	/* 8*: Set MaxSysVoltage to VADP. */
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+	vsys_target = bi->voltage_max;
+#else
+	vsys_target = MIN(charge_voltage - 256, CHARGE_V_MAX);
+#endif
+	isl9241_write(chgnum, ISL9241_REG_MAX_SYSTEM_VOLTAGE, vsys_target);
+
+	/* 9*: Wait until VSYS == MaxSysVoltage. */
+	deadline.val = get_time().val + ISL9241_BYPASS_VSYS_TIMEOUT_MS * MSEC;
+	do {
+		msleep(ISL9241_BYPASS_VSYS_TIMEOUT_MS / 10);
+		if (_get_vsys_voltage(chgnum, 0, &vsys)) {
+			CPRINTS("Aborting bypass mode. Vsys is unknown.");
+			rv = EC_ERROR_UNKNOWN;
+			goto unlock_control3;
+		}
+		if (timestamp_expired(deadline, NULL)) {
+			CPRINTS("Aborting bypass mode. Vsys too low (%d < %d)",
+				vsys, vsys_target);
+			rv = EC_ERROR_TIMEOUT;
+			goto unlock_control3;
+		}
+	} while (vsys < vsys_target - 256);
+
+	/* 10*: Turn on Bypass gate */
+	isl9241_update(chgnum, ISL9241_REG_CONTROL0,
+		       ISL9241_CONTROL0_EN_BYPASS_GATE, MASK_SET);
+
+	/* 11: Wait 1 ms. */
+	msleep(1);
+
+	/* 12*: Turn off NGATE. */
+	isl9241_update(chgnum, ISL9241_REG_CONTROL0, ISL9241_CONTROL0_NGATE_OFF,
+		       MASK_SET);
+
+	/* 14*: Stop switching. */
+	isl9241_write(chgnum, ISL9241_REG_MAX_SYSTEM_VOLTAGE, 0);
+
+	/* 15: Set BGATE to normal operation. */
+	isl9241_update(chgnum, ISL9241_REG_CONTROL1, ISL9241_CONTROL1_BGATE_OFF,
+		       MASK_CLR);
+
+	if (!isl9241_is_ac_present(chgnum)) {
+		/*
+		 * Suggestion: If ACOK goes low before step A16, stop
+		 * executing commands and complete steps for Bypass to BAT.
+		 */
+		rv = EC_ERROR_PARAM1;
+		goto unlock_control3;
+	}
+
+	/* 16: Enable 10 mA discharge on CSOP. */
+	/* 17: Read diode emulation active bit. */
+	/* 18: Disable 10mA discharge on CSOP. */
+	/* 19*: Force forward buck/reverse boost mode. */
+	isl9241_update_force_buck_mode(chgnum, MASK_SET);
+
+	if (!isl9241_is_ac_present(chgnum)) {
+		/*
+		 * Suggestion: If AC is removed on or after A16, complete all
+		 * 19 steps then execute Bypass to BAT.
+		 */
+		rv = EC_ERROR_PARAM2;
+	}
+
+unlock_control3:
+	mutex_unlock(&control3_mutex_isl9241);
+
+	return rv;
+}
+
+/*
+ * Transition from Bypass + CHRG to Bypass (J).
+ */
+static enum ec_error_list isl9241_bypass_chrg_to_bypass(int chgnum)
+{
+	int rv;
+
+	CPRINTS("bypass_chrg -> bypass");
+
+	/* 1: Stop switching. */
+	rv = isl9241_write(chgnum, ISL9241_REG_MAX_SYSTEM_VOLTAGE, 0);
+	if (rv)
+		return rv;
+
+	/* 2: Disable fast charge. */
+	rv = isl9241_write(chgnum, ISL9241_REG_CHG_CURRENT_LIMIT, 0);
+	if (rv)
+		return rv;
+
+	/* 3: Disable trickle charge. */
+	rv = isl9241_write(chgnum, ISL9241_REG_MIN_SYSTEM_VOLTAGE, 0);
+	if (rv)
+		return rv;
+
+	return EC_SUCCESS;
+}
+
+/*
+ * Transition from Bypass to NVDC (B).
+ */
+static enum ec_error_list isl9241_bypass_to_nvdc(int chgnum)
+{
+	const struct battery_info *bi = battery_get_info();
+	int voltage;
+	int rv;
+
+	CPRINTS("bypass -> nvdc");
+
+	/* 1*: Reduce system load below ACLIM. */
+	/* 3*: Disable force forward buck/reverse boost. */
+	rv = isl9241_update_force_buck_mode(chgnum, MASK_CLR);
+	if (rv)
+		return rv;
+
+	/* 6*: Set MaxSysVoltage to VADP. */
+	rv = isl9241_get_vbus_voltage(chgnum, 0, &voltage);
+	if (rv)
+		return rv;
+	rv = isl9241_write(chgnum, ISL9241_REG_MAX_SYSTEM_VOLTAGE,
+			   voltage - 256);
+	if (rv)
+		return rv;
+
+	/* 7*: Wait until VSYS == MaxSysVoltage. */
+	msleep(1);
+
+	/* 8*: Turn on NGATE. */
+	rv = isl9241_update(chgnum, ISL9241_REG_CONTROL0,
+			    ISL9241_CONTROL0_NGATE_OFF, MASK_CLR);
+	if (rv)
+		return rv;
+
+	/* 10*: Turn off Bypass gate */
+	rv = isl9241_update(chgnum, ISL9241_REG_CONTROL0,
+			    ISL9241_CONTROL0_EN_BYPASS_GATE, MASK_CLR);
+	if (rv)
+		return rv;
+
+	/* 12*: Set MaxSysVoltage to full charge. */
+	rv = isl9241_write(chgnum, ISL9241_REG_MAX_SYSTEM_VOLTAGE,
+			     bi->voltage_max);
+
+	if (rv)
+		return rv;
+
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+	rv = isl9241_write(chgnum, ISL9241_REG_ACOK_REFERENCE,
+		      ISL9241_MV_TO_ACOK_REFERENCE(4000));
+#else
+	rv = isl9241_write(chgnum, ISL9241_REG_ACOK_REFERENCE,
+		      ISL9241_MV_TO_ACOK_REFERENCE(
+			      ISL9241_ACOK_REF_LOW_VOLTAGE_ADAPTER_MV));
+#endif
 
 	return rv;
 }
 
+#ifdef CONFIG_CHARGER_BYPASS_REVERSE_TURBO
+/*
+ * Transition from Bypass to RTB (C).
+ */
+static enum ec_error_list isl9241_bypass_to_rtb(int chgnum)
+{
+	int rv;
+	const struct battery_info *bi = battery_get_info();
+
+	CPRINTS("Bypass -> RTB");
+	/* 1*: Enable Reverse Turbo Boost function. */
+	rv = isl9241_update(chgnum, ISL9241_REG_CONTROL0,
+	       ISL9241_CONTROL0_REVERSE_TURBO_BOOST, MASK_SET);
+
+	if (rv)
+		return rv;
+
+	/* 2*: Set MaxSysVoltage register to full battery charge voltage. */
+	rv = isl9241_write(chgnum, ISL9241_REG_MAX_SYSTEM_VOLTAGE,
+		bi->voltage_max);
+
+	if (rv)
+		return rv;
+
+	return EC_SUCCESS;
+}
+
+/*
+ * Transition from RTB to Bypass (F).
+ */
+static enum ec_error_list isl9241_rtb_to_bypass(int chgnum)
+{
+	int rv;
+
+	CPRINTS("RTB -> Bypass");
+	/* 1*: Disable switching. */
+	rv = isl9241_write(chgnum, ISL9241_REG_MAX_SYSTEM_VOLTAGE, 0);
+
+	if (rv)
+		return rv;
+
+	/* 2*: Disable reverse turbo boost function. */
+	rv = isl9241_update(chgnum, ISL9241_REG_CONTROL0,
+		ISL9241_CONTROL0_REVERSE_TURBO_BOOST, MASK_CLR);
+
+	if (rv)
+		return rv;
+
+	return EC_SUCCESS;
+}
+
+/*
+ * Transition from RTB to Bypass (E).
+ */
+static enum ec_error_list isl9241_rtb_chrg_to_rtb(int chgnum)
+{
+	int rv;
+
+	CPRINTS("RTB_chrg -> RTB");
+
+	/* 2: Disable fast charge. */
+	rv = isl9241_write(chgnum, ISL9241_REG_CHG_CURRENT_LIMIT, 0);
+	if (rv)
+		return rv;
+
+	/* 3: Disable trickle charge. */
+	rv = isl9241_write(chgnum, ISL9241_REG_MIN_SYSTEM_VOLTAGE, 0);
+	if (rv)
+		return rv;
+
+	return EC_SUCCESS;
+}
+#endif
+
+static bool isl9241_in_bypass_mode;
+
+bool isl9241_is_in_bypass_mode(int chgnum)
+{
+	return isl9241_in_bypass_mode;
+}
+
+static enum ec_error_list isl9241_enable_bypass_mode(int chgnum, bool enable)
+{
+	enum ec_error_list rv = EC_ERROR_UNKNOWN;
+
+	if (enable) {
+#ifdef CONFIG_CHARGER_BYPASS_REVERSE_TURBO
+		int reg;
+
+		rv = isl9241_read(chgnum, ISL9241_REG_CONTROL0, &reg);
+
+		if ((reg & ISL9241_CONTROL0_REVERSE_TURBO_BOOST) &&
+			battery_is_present() == BP_NO) {
+			/* Needs to exit RTB mode if battery is disconnects */
+			if (isl9241_is_in_chrg(chgnum)) {
+				/* E (then F) */
+				rv = isl9241_rtb_chrg_to_rtb(chgnum);
+				if (rv)
+					CPRINTS("RTB_chrg -> RTB failed(%d)", rv);
+			}
+			/* F */
+			rv = isl9241_rtb_to_bypass(chgnum);
+			if (rv)
+				CPRINTS("RTB -> bypass failed(%d)", rv);
+		}
+		/* If charger already in bypass mode, ignore it */
+		if (!(reg & ISL9241_CONTROL0_EN_BYPASS_GATE)) {
+#endif
+			/* We should be already in NVDC. */
+			if (isl9241_is_in_chrg(chgnum)) {
+				/* (Optional) L (then A) */
+				rv = isl9241_nvdc_chrg_to_nvdc(chgnum);
+				if (rv)
+					CPRINTS("nvdc_chrg -> nvdc failed(%d)", rv);
+			}
+			/* A */
+			rv = isl9241_nvdc_to_bypass(chgnum);
+			if (rv == EC_ERROR_PARAM1 || rv == EC_ERROR_PARAM2) {
+				CPRINTS("AC removed (%d) in nvdc -> bypass mode", rv);
+				return isl9241_bypass_to_bat(chgnum);
+			} else if (rv) {
+				CPRINTS("Failed to enable bypass mode(%d)", rv);
+				return isl9241_bypass_to_nvdc(chgnum);
+			}
+
+#ifdef CONFIG_CHARGER_BYPASS_REVERSE_TURBO
+		}
+
+		rv = isl9241_read(chgnum, ISL9241_REG_CONTROL0, &reg);
+		if ((reg & ISL9241_CONTROL0_EN_BYPASS_GATE) &&
+			battery_is_present() == BP_YES) {
+			rv = isl9241_bypass_to_rtb(chgnum);
+			if (rv)
+				CPRINTS("bypass -> RTB failed(%d)", rv);
+		}
+#endif
+		if (rv == EC_SUCCESS) {
+			isl9241_in_bypass_mode = true;
+		}
+		return rv;
+	}
+
+	/* Disable */
+	if (isl9241_is_ac_present(chgnum)) {
+#ifdef CONFIG_CHARGER_BYPASS_REVERSE_TURBO
+		int reg;
+
+		rv = isl9241_read(chgnum, ISL9241_REG_CONTROL0, &reg);
+		if ((reg & ISL9241_CONTROL0_EN_BYPASS_GATE) != ISL9241_CONTROL0_EN_BYPASS_GATE) {
+			CPRINTS("Not in bypass mode, ignore change");
+			return rv;
+		}
+
+#endif
+		/* Switch to another AC (e.g. BJ -> Type-C) */
+		if (isl9241_is_in_chrg(chgnum)) {
+			/* J (then B) */
+			rv = isl9241_bypass_chrg_to_bypass(chgnum);
+			if (rv)
+				CPRINTS("bypass_chrg -> bypass failed(%d)", rv);
+		}
+#ifdef CONFIG_CHARGER_BYPASS_REVERSE_TURBO
+		/* F */
+		rv = isl9241_rtb_to_bypass(chgnum);
+		if (rv)
+			CPRINTS("RTB -> bypass failed(%d)", rv);
+#endif
+		/* B */
+		rv = isl9241_bypass_to_nvdc(chgnum);
+		if (rv)
+			CPRINTS("bypass -> nvdc failed(%d)", rv);
+
+		if (rv == EC_SUCCESS) {
+			isl9241_in_bypass_mode = false;
+		}
+		return rv;
+	} else {
+		/* AC removal */
+		if (isl9241_is_in_chrg(chgnum)) {
+			/* M */
+			rv = isl9241_bypass_chrg_to_bat(chgnum);
+			if (rv)
+				CPRINTS("bypass_chrg -> bat failed(%d)", rv);
+		} else {
+			/* M' */
+			rv = isl9241_bypass_to_bat(chgnum);
+			if (rv)
+				CPRINTS("bypass -> bat failed(%d)", rv);
+		}
+
+		if (rv == EC_SUCCESS) {
+			isl9241_in_bypass_mode = false;
+		}
+
+		return rv;
+	}
+
+	return rv;
+}
+#else 
+
+bool isl9241_is_in_bypass_mode(int chgnum)
+{
+	return false;
+}
+
+#endif /* CONFIG_CHARGER_BYPASS_MODE */
+
 /*****************************************************************************/
 /* ISL-9241 initialization */
 static void isl9241_init(int chgnum)
 {
+#ifdef CONFIG_ISL9241_SWITCHING_FREQ
+	int ctl_val;
+#endif
+
 	const struct battery_info *bi = battery_get_info();
 
+	mutex_lock(&control3_mutex_isl9241);
 	/*
 	 * Set the MaxSystemVoltage to battery maximum,
 	 * 0x00=disables switching charger states
@@ -359,11 +1291,11 @@ static void isl9241_init(int chgnum)
 	 * [15:13]: Trickle Charging Current (battery pre-charge current)
 	 * [10:9] : Prochot# Debounce time (1000us)
 	 */
-	if (isl9241_update(chgnum, ISL9241_REG_CONTROL2,
-			   (ISL9241_CONTROL2_TRICKLE_CHG_CURR(
-				bi->precharge_current) |
-			    ISL9241_CONTROL2_PROCHOT_DEBOUNCE_1000),
-			   MASK_SET))
+	if (isl9241_update(
+		    chgnum, ISL9241_REG_CONTROL2,
+		    (ISL9241_CONTROL2_TRICKLE_CHG_CURR(bi->precharge_current) |
+		     ISL9241_CONTROL2_PROCHOT_DEBOUNCE_1000),
+		    MASK_SET))
 		goto init_fail;
 
 	/*
@@ -371,8 +1303,7 @@ static void isl9241_init(int chgnum)
 	 * [14]: ACLIM Reload (Do not reload)
 	 */
 	if (isl9241_update(chgnum, ISL9241_REG_CONTROL3,
-			   ISL9241_CONTROL3_ACLIM_RELOAD,
-			   MASK_SET))
+			   ISL9241_CONTROL3_ACLIM_RELOAD, MASK_SET))
 		goto init_fail;
 
 	/*
@@ -380,17 +1311,27 @@ static void isl9241_init(int chgnum)
 	 * [13]: Slew rate control enable (sets VSYS ramp to 8mV/us)
 	 */
 	if (isl9241_update(chgnum, ISL9241_REG_CONTROL4,
-			   ISL9241_CONTROL4_SLEW_RATE_CTRL,
-			   MASK_SET))
+			   ISL9241_CONTROL4_SLEW_RATE_CTRL, MASK_SET))
 		goto init_fail;
 
 #ifndef CONFIG_CHARGE_RAMP_HW
 	if (isl9241_update(chgnum, ISL9241_REG_CONTROL0,
-			   ISL9241_CONTROL0_INPUT_VTG_REGULATION,
-			   MASK_SET))
+			   ISL9241_CONTROL0_INPUT_VTG_REGULATION, MASK_SET))
+		goto init_fail;
+#endif
+
+#ifdef CONFIG_ISL9241_SWITCHING_FREQ
+	if (isl9241_read(chgnum, ISL9241_REG_CONTROL1, &ctl_val))
+		goto init_fail;
+	ctl_val &= ~ISL9241_CONTROL1_SWITCHING_FREQ_MASK;
+	ctl_val |= ((CONFIG_ISL9241_SWITCHING_FREQ << 7) &
+		    ISL9241_CONTROL1_SWITCHING_FREQ_MASK);
+	if (isl9241_write(chgnum, ISL9241_REG_CONTROL1, ctl_val))
 		goto init_fail;
 #endif
 
+	mutex_unlock(&control3_mutex_isl9241);
+
 	/*
 	 * No need to proceed with the rest of init if we sysjump'd to this
 	 * image as the input current limit has already been set.
@@ -399,13 +1340,15 @@ static void isl9241_init(int chgnum)
 		return;
 
 	/* Initialize the input current limit to the board's default. */
-	if (isl9241_set_input_current(chgnum, CONFIG_CHARGER_INPUT_CURRENT))
+	if (isl9241_set_input_current_limit(
+		    chgnum, CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT))
 		goto init_fail;
 
 	return;
 
 init_fail:
-	CPRINTF("ISL9241_init failed!");
+	mutex_unlock(&control3_mutex_isl9241);
+	CPRINTS("Init failed!");
 }
 
 /*****************************************************************************/
@@ -447,6 +1390,31 @@ static int isl9241_ramp_get_current_limit(int chgnum)
 }
 #endif /* CONFIG_CHARGE_RAMP_HW */
 
+/*
+ * When fully charged in a low-power state, the ISL9241 may get stuck
+ * in CCM. Toggle learning mode for 50 ms to enter DCM and save power.
+ * This is a workaround provided by Renesas. See b/183771327.
+ * Note: the charger_get_state() returns the last known charge value,
+ * so need to check the battery is not disconnected when the system
+ * comes from the battery cutoff.
+ */
+static void isl9241_restart_charge_voltage_when_full(void)
+{
+	if (!chipset_in_or_transitioning_to_state(CHIPSET_STATE_ON) &&
+	    led_pwr_get_state() == LED_PWRS_CHARGE_NEAR_FULL &&
+	    battery_get_disconnect_state() == BATTERY_NOT_DISCONNECTED) {
+		charger_discharge_on_ac(1);
+		msleep(50);
+		charger_discharge_on_ac(0);
+	}
+}
+DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, isl9241_restart_charge_voltage_when_full,
+	     HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, isl9241_restart_charge_voltage_when_full,
+	     HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, isl9241_restart_charge_voltage_when_full,
+	     HOOK_PRIO_DEFAULT);
+
 /*****************************************************************************/
 #ifdef CONFIG_CMD_CHARGER_DUMP
 static void dump_reg_range(int chgnum, int low, int high)
@@ -456,27 +1424,18 @@ static void dump_reg_range(int chgnum, int low, int high)
 	int rv;
 
 	for (reg = low; reg <= high; reg++) {
-		CPRINTF("[%Xh] = ", reg);
+		ccprintf("[%Xh] = ", reg);
 		rv = isl9241_read(chgnum, reg, &regval);
 		if (!rv)
-			CPRINTF("0x%04x\n", regval);
+			ccprintf("0x%04x\n", regval);
 		else
-			CPRINTF("ERR (%d)\n", rv);
+			ccprintf("ERR (%d)\n", rv);
 		cflush();
 	}
 }
 
-static int command_isl9241_dump(int argc, char **argv)
+static void command_isl9241_dump(int chgnum)
 {
-	char *e;
-	int chgnum = 0;
-
-	if (argc >= 2) {
-		chgnum = strtoi(argv[1], &e, 10);
-		if (*e)
-			return EC_ERROR_PARAM1;
-	}
-
 	dump_reg_range(chgnum, 0x14, 0x15);
 	dump_reg_range(chgnum, 0x38, 0x40);
 	dump_reg_range(chgnum, 0x43, 0x43);
@@ -484,12 +1443,7 @@ static int command_isl9241_dump(int argc, char **argv)
 	dump_reg_range(chgnum, 0x80, 0x87);
 	dump_reg_range(chgnum, 0x90, 0x91);
 	dump_reg_range(chgnum, 0xFE, 0xFF);
-
-	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(charger_dump, command_isl9241_dump,
-			"charger_dump <chgnum>",
-			"Dumps ISL9241 registers");
 #endif /* CONFIG_CMD_CHARGER_DUMP */
 
 const struct charger_drv isl9241_drv = {
@@ -504,10 +1458,12 @@ const struct charger_drv isl9241_drv = {
 	.set_voltage = &isl9241_set_voltage,
 	.discharge_on_ac = &isl9241_discharge_on_ac,
 	.get_vbus_voltage = &isl9241_get_vbus_voltage,
-	.set_input_current = &isl9241_set_input_current,
-	.get_input_current = &isl9241_get_input_current,
+	.get_vsys_voltage = &isl9241_get_vsys_voltage,
+	.set_input_current_limit = &isl9241_set_input_current_limit,
+	.get_input_current_limit = &isl9241_get_input_current_limit,
 	.manufacturer_id = &isl9241_manufacturer_id,
 	.device_id = &isl9241_device_id,
+	.set_frequency = &isl9241_set_frequency,
 	.get_option = &isl9241_get_option,
 	.set_option = &isl9241_set_option,
 #ifdef CONFIG_CHARGE_RAMP_HW
@@ -516,4 +1472,13 @@ const struct charger_drv isl9241_drv = {
 	.ramp_is_detected = &isl9241_ramp_is_detected,
 	.ramp_get_current_limit = &isl9241_ramp_get_current_limit,
 #endif
+#ifdef CONFIG_CHARGER_BYPASS_MODE
+	.enable_bypass_mode = isl9241_enable_bypass_mode,
+#endif
+#ifdef CONFIG_CMD_CHARGER_DUMP
+	.dump_registers = &command_isl9241_dump,
+#endif
+#ifdef CONFIG_CHARGER_DUMP_PROCHOT
+	.dump_prochot = &isl9241_dump_prochot_status,
+#endif
 };
diff --git a/driver/charger/isl9241.h b/driver/charger/isl9241.h
index b29a300fb2..d1a022ae49 100644
--- a/driver/charger/isl9241.h
+++ b/driver/charger/isl9241.h
@@ -1,28 +1,30 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
- * Renesas (Intersil) ISL-9241 battery charger driver header.
+ * Renesas (Intersil) ISL-9241 (and RAA489110) battery charger driver header.
  */
 
 #ifndef __CROS_EC_ISL9241_H
 #define __CROS_EC_ISL9241_H
 
-#define ISL9241_ADDR_FLAGS	0x09
+#include "driver/charger/isl9241_public.h"
 
-#define CHARGER_NAME	"ISL9241"
-#define CHARGE_V_MAX	18304
-#define CHARGE_V_MIN	64
-#define CHARGE_V_STEP	8
-#define CHARGE_I_MAX	6140
-#define CHARGE_I_MIN	4
-#define CHARGE_I_STEP	4
-#define INPUT_I_MAX	6140
-#define INPUT_I_MIN	4
-#define	INPUT_I_STEP	4
-
-/* Default minimum VIN voltage controlled by ISL9241_REG_VIN_VOLTAGE */
-#define ISL9241_BC12_MIN_VOLTAGE	4096
+#define CHARGER_NAME "ISL9241"
+#define CHARGE_V_MAX 18304
+#define CHARGE_V_MIN 64
+#define CHARGE_V_STEP 8
+/*
+ * When the default sense resistor value is used, register values
+ * represent mA. For other sense resistors values, register
+ * values must be scaled accordingly to convert to mA.
+ */
+#define CHARGE_I_MAX 6140
+#define CHARGE_I_MIN 4
+#define CHARGE_I_STEP 4
+#define INPUT_I_MAX 6140
+#define INPUT_I_MIN 4
+#define INPUT_I_STEP 4
 
 /* Registers */
 
@@ -30,28 +32,51 @@
  * ChargeCurrentLimit [12:2] 11-bit (0x0000h = disables fast charging,
  * trickle charging is allowed)
  */
-#define ISL9241_REG_CHG_CURRENT_LIMIT	0x14
+#define ISL9241_REG_CHG_CURRENT_LIMIT 0x14
 
 /* MaxSystemVoltage [14:3] 12-bit, (0x0000h = disables switching) */
-#define ISL9241_REG_MAX_SYSTEM_VOLTAGE	0x15
+#define ISL9241_REG_MAX_SYSTEM_VOLTAGE 0x15
 
-#define ISL9241_REG_CONTROL7		0x38
+#define ISL9241_REG_CONTROL7 0x38
 
 /* Configures various charger options */
-#define ISL9241_REG_CONTROL0		0x39
+#define ISL9241_REG_CONTROL0 0x39
 /* 2: Input Voltage Regulation (0 = Enable (default), 1 = Disable) */
-#define ISL9241_CONTROL0_INPUT_VTG_REGULATION	BIT(2)
+#define ISL9241_CONTROL0_REVERSE_TURBO_BOOST BIT(0)
+#define ISL9241_CONTROL0_INPUT_VTG_REGULATION BIT(2)
+#define ISL9241_CONTROL0_EN_VIN_VOUT_COMP BIT(5)
+#define ISL9241_CONTROL0_EN_CHARGE_PUMPS BIT(6)
+#define RAA489110_CONTROL0_EN_FORCE_BUCK_MODE BIT(10)
+#define ISL9241_CONTROL0_EN_BYPASS_GATE BIT(11)
+#define ISL9241_CONTROL0_NGATE_OFF BIT(12)
 
+#define ISL9241_REG_INFORMATION1 0x3A
+#define ISL9241_REG_INFORMATION1_LOW_VSYS_PROCHOT BIT(10)
+#define ISL9241_REG_INFORMATION1_DC_PROCHOT BIT(11)
+#define ISL9241_REG_INFORMATION1_AC_PROCHOT BIT(12)
 
-#define ISL9241_REG_INFORMATION1	0x3A
-#define ISL9241_REG_ADAPTER_CUR_LIMIT2	0x3B
+#define ISL9241_REG_ADAPTER_CUR_LIMIT2 0x3B
 
 /* Configures various charger options */
-#define ISL9241_REG_CONTROL1		0x3C
-#define ISL9241_CONTROL1_LEARN_MODE	BIT(12)
+#define ISL9241_REG_CONTROL1 0x3C
+#define ISL9241_CONTROL1_PSYS BIT(3)
+#define ISL9241_CONTROL1_BGATE_OFF BIT(6)
+#define ISL9241_CONTROL1_LEARN_MODE BIT(12)
+/*
+ * 9:7 - Switching Frequency
+ */
+#define ISL9241_CONTROL1_SWITCHING_FREQ_MASK 0x380
+#define ISL9241_CONTROL1_SWITCHING_FREQ_1420KHZ 0
+#define ISL9241_CONTROL1_SWITCHING_FREQ_1180KHZ 1
+#define ISL9241_CONTROL1_SWITCHING_FREQ_1020KHZ 2
+#define ISL9241_CONTROL1_SWITCHING_FREQ_890KHZ 3
+#define ISL9241_CONTROL1_SWITCHING_FREQ_808KHZ 4
+#define ISL9241_CONTROL1_SWITCHING_FREQ_724KHZ 5
+#define ISL9241_CONTROL1_SWITCHING_FREQ_656KHZ 6
+#define ISL9241_CONTROL1_SWITCHING_FREQ_600KHZ 7
 
 /* Configures various charger options */
-#define ISL9241_REG_CONTROL2		0x3D
+#define ISL9241_REG_CONTROL2 0x3D
 /*
  * 15:13 - Trickle Charging Current
  *         <000> 32mA (do not use)
@@ -63,75 +88,110 @@
  *         <110> 224mA
  *         <111> 256mA
  */
-#define ISL9241_CONTROL2_TRICKLE_CHG_CURR(curr)	((((curr) >> 5) - 1) << 13)
+#define ISL9241_CONTROL2_TRICKLE_CHG_CURR(curr) ((((curr) >> 5) - 1) << 13)
 /* 12 - Two-Level Adapter Current Limit */
-#define ISL9241_CONTROL2_TWO_LEVEL_ADP_CURR	BIT(12)
+#define ISL9241_CONTROL2_TWO_LEVEL_ADP_CURR BIT(12)
 /* 10:9 PROCHOT# debounce time in uS */
-#define ISL9241_CONTROL2_PROCHOT_DEBOUNCE_1000	(3 << 9)
+#define ISL9241_CONTROL2_PROCHOT_DEBOUNCE_MASK GENMASK(10, 9)
+#define ISL9241_CONTROL2_PROCHOT_DEBOUNCE_100 (1 << 9)
+#define ISL9241_CONTROL2_PROCHOT_DEBOUNCE_500 (2 << 9)
+#define ISL9241_CONTROL2_PROCHOT_DEBOUNCE_1000 (3 << 9)
 
 /* MinSystemVoltage [13:6] 8-bit (0x0000h = disables all battery charging) */
-#define ISL9241_REG_MIN_SYSTEM_VOLTAGE	0x3E
-
-#define ISL9241_REG_ADAPTER_CUR_LIMIT1	0x3F
-#define ISL9241_REG_ACOK_REFERENCE	0x40
-#define ISL9241_REG_CONTROL6		0x43
-#define ISL9241_REG_AC_PROCHOT		0x47
-#define ISL9241_REG_DC_PROCHOT		0x48
-#define ISL9241_REG_OTG_VOLTAGE		0x49
-#define ISL9241_REG_OTG_CURRENT		0x4A
+#define ISL9241_REG_MIN_SYSTEM_VOLTAGE 0x3E
+
+#define ISL9241_REG_ADAPTER_CUR_LIMIT1 0x3F
+#define ISL9241_REG_ACOK_REFERENCE 0x40
+#define ISL9241_REG_CONTROL6 0x43
+#define ISL9241_REG_AC_PROCHOT 0x47
+#define ISL9241_REG_DC_PROCHOT 0x48
+#define ISL9241_REG_OTG_VOLTAGE 0x49
+#define ISL9241_REG_OTG_CURRENT 0x4A
+
+#ifdef CONFIG_CHARGER_RAA489110
+#define ISL9241_MV_TO_ACOK_REFERENCE(mv) (((mv) / 144) << 6)
+#else /* CONFIG_CHARGER_ISL9241 */
+#define ISL9241_MV_TO_ACOK_REFERENCE(mv) (((mv) / 96) << 6)
+#endif
 
 /* VIN Voltage (ADP Min Voltage) (default 4.096V) */
-#define ISL9241_REG_VIN_VOLTAGE		0x4B
+#define ISL9241_REG_VIN_VOLTAGE 0x4B
 
 /* Configures various charger options */
-#define ISL9241_REG_CONTROL3		0x4C
+#define ISL9241_REG_CONTROL3 0x4C
 /* 14: ACLIM Reload (0 - reload, 1 - Do not reload */
-#define ISL9241_CONTROL3_ACLIM_RELOAD	BIT(14)
+#define ISL9241_CONTROL3_ACLIM_RELOAD BIT(14)
+/* 5: Input Current Limit Loop (0 - Enable, 1 - Disable */
+#define ISL9241_CONTROL3_INPUT_CURRENT_LIMIT BIT(5)
 /* 2: Digital Reset (0 - Idle, 1 - Reset */
-#define ISL9241_CONTROL3_DIGITAL_RESET	BIT(2)
+#define ISL9241_CONTROL3_DIGITAL_RESET BIT(2)
 /* 0: Enable ADC (0 - Active when charging, 1 - Active always) */
-#define ISL9241_CONTROL3_ENABLE_ADC	BIT(0)
+#define ISL9241_CONTROL3_ENABLE_ADC BIT(0)
 
 /* Indicates various charger status */
-#define ISL9241_REG_INFORMATION2	0x4D
+#define ISL9241_REG_INFORMATION2 0x4D
 /* 12: BATGONE pin status (0 = Battery is present, 1 = No battery) */
-#define ISL9241_INFORMATION2_BATGONE_PIN	BIT(12)
+#define ISL9241_INFORMATION2_BATGONE_PIN BIT(12)
 /* 14: ACOK pin status (0 = No adapter, 1 = Adapter is present) */
-#define ISL9241_INFORMATION2_ACOK_PIN		BIT(14)
+#define ISL9241_INFORMATION2_ACOK_PIN BIT(14)
 
-#define ISL9241_REG_CONTROL4		0x4E
+#define ISL9241_REG_CONTROL4 0x4E
+/* ISL9241 only */
+#define ISL9241_CONTROL4_FORCE_BUCK_MODE BIT(10)
+/* 11: Rsense (Rs1:Rs2) ratio for PSYS (0 - 2:1, 1 - 1:1) */
+#define ISL9241_CONTROL4_PSYS_RSENSE_RATIO BIT(11)
 /* 13: Enable VSYS slew rate control (0 - disable, 1 - enable) */
-#define ISL9241_CONTROL4_SLEW_RATE_CTRL     BIT(13)
+#define ISL9241_CONTROL4_SLEW_RATE_CTRL BIT(13)
 
-#define ISL9241_REG_CONTROL5		0x4F
-#define ISL9241_REG_NTC_ADC_RESULTS	0x80
-#define ISL9241_REG_VBAT_ADC_RESULTS	0x81
-#define ISL9241_REG_TJ_ADC_RESULTS	0x82
+#define ISL9241_REG_CONTROL5 0x4F
+#define ISL9241_REG_NTC_ADC_RESULTS 0x80
+#define ISL9241_REG_VBAT_ADC_RESULTS 0x81
+#define ISL9241_REG_TJ_ADC_RESULTS 0x82
 
 /* ADC result for adapter current measurements, LSB = 22.2mA */
-#define ISL9241_REG_IADP_ADC_RESULTS	0x83
+#define ISL9241_REG_IADP_ADC_RESULTS 0x83
+
+#define ISL9241_REG_DC_ADC_RESULTS 0x84
+#define ISL9241_REG_CC_ADC_RESULTS 0x85
+#define ISL9241_REG_VSYS_ADC_RESULTS 0x86
+#define ISL9241_REG_VIN_ADC_RESULTS 0x87
+#define ISL9241_REG_INFORMATION3 0x90
+#define ISL9241_REG_INFORMATION4 0x91
+#define ISL9241_REG_MANUFACTURER_ID 0xFE
+#define ISL9241_REG_DEVICE_ID 0xFF
+
+#define ISL9241_VIN_ADC_BIT_OFFSET 6
+#ifdef CONFIG_CHARGER_RAA489110
+#define ISL9241_VIN_ADC_STEP_MV 144
+#else /* CONFIG_CHARGER_ISL9241 */
+#define ISL9241_VIN_ADC_STEP_MV 96
+#endif
+
+#define ISL9241_ADC_POLLING_TIME_US 400
+
+/*
+ * Used to reset ACOKref register to normal value to detect low voltage (5V or
+ * 9V) adapter during next plug in event
+ */
+#define ISL9241_ACOK_REF_LOW_VOLTAGE_ADAPTER_MV 3600
 
-#define ISL9241_REG_DC_ADC_RESULTS	0x84
-#define ISL9241_REG_CC_ADC_RESULTS	0x85
-#define ISL9241_REG_VSYS_ADC_RESULTS	0x86
-#define ISL9241_REG_VIN_ADC_RESULTS	0x87
-#define ISL9241_REG_INFORMATION3	0x90
-#define ISL9241_REG_INFORMATION4	0x91
-#define ISL9241_REG_MANUFACTURER_ID	0xFE
-#define ISL9241_REG_DEVICE_ID		0xFF
+/*
+ * Max wait time for Vsys to be close to Vin (Vadp) before turning on the bypass
+ * gate. See 2.5.1 of application notes for details.
+ */
+#define ISL9241_BYPASS_VSYS_TIMEOUT_MS 500
 
-#define ISL9241_VIN_ADC_BIT_OFFSET	6
-#define ISL9241_VIN_ADC_STEP_MV		96
+/* Sense resistor default values in milli Ohm */
+#define ISL9241_DEFAULT_RS1 20 /* Input current sense resistor */
+#define ISL9241_DEFAULT_RS2 10 /* Battery charge current sense resistor */
 
-extern const struct charger_drv isl9241_drv;
+#define BOARD_RS1 CONFIG_CHARGER_SENSE_RESISTOR_AC
+#define BOARD_RS2 CONFIG_CHARGER_SENSE_RESISTOR
 
-/**
- * Set AC prochot threshold
- *
- * @param chgnum: Index into charger chips
- * @param ma: AC prochot threshold current in mA, multiple of 128mA
- * @return EC_SUCCESS or error
- */
-int isl9241_set_ac_prochot(int chgnum, int ma);
+#define BC_REG_TO_CURRENT(REG) (((REG)*ISL9241_DEFAULT_RS2) / BOARD_RS2)
+#define BC_CURRENT_TO_REG(CUR) (((CUR)*BOARD_RS2) / ISL9241_DEFAULT_RS2)
+
+#define AC_REG_TO_CURRENT(REG) (((REG)*ISL9241_DEFAULT_RS1) / BOARD_RS1)
+#define AC_CURRENT_TO_REG(CUR) (((CUR)*BOARD_RS1) / ISL9241_DEFAULT_RS1)
 
 #endif /* __CROS_EC_ISL9241_H */
diff --git a/driver/charger/rt946x.c b/driver/charger/rt946x.c
index d78089439c..0e52d8e3bb 100644
--- a/driver/charger/rt946x.c
+++ b/driver/charger/rt946x.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -7,41 +7,54 @@
 
 #include "battery.h"
 #include "battery_smart.h"
-#include "charger.h"
 #include "charge_manager.h"
+#include "charger.h"
 #include "common.h"
 #include "compile_time_macros.h"
 #include "config.h"
 #include "console.h"
+#include "driver/wpc/p9221.h"
 #include "extpower.h"
 #include "hooks.h"
 #include "i2c.h"
 #include "printf.h"
-#include "driver/wpc/p9221.h"
 #include "rt946x.h"
 #include "task.h"
-#include "tcpm.h"
+#include "tcpm/tcpm.h"
 #include "timer.h"
 #include "usb_charge.h"
 #include "usb_pd.h"
 #include "util.h"
 
 /* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
 #define CPRINTS(format, args...) \
-	cprints(CC_CHARGER, "%s " format, "RT946X", ## args)
+	cprints(CC_CHARGER, "%s " format, "RT946X", ##args)
+
+/* Charger parameters */
+#define CHARGER_NAME RT946X_CHARGER_NAME
+#define CHARGE_V_MAX 4710
+#define CHARGE_V_MIN 3900
+#define CHARGE_V_STEP 10
+#define CHARGE_I_MAX 5000
+#define CHARGE_I_MIN 100
+#define CHARGE_I_OFF 0
+#define CHARGE_I_STEP 100
+#define INPUT_I_MAX 3250
+#define INPUT_I_MIN 100
+#define INPUT_I_STEP 50
 
 /* Charger parameters */
 static const struct charger_info rt946x_charger_info = {
-	.name         = CHARGER_NAME,
-	.voltage_max  = CHARGE_V_MAX,
-	.voltage_min  = CHARGE_V_MIN,
+	.name = CHARGER_NAME,
+	.voltage_max = CHARGE_V_MAX,
+	.voltage_min = CHARGE_V_MIN,
 	.voltage_step = CHARGE_V_STEP,
-	.current_max  = CHARGE_I_MAX,
-	.current_min  = CHARGE_I_MIN,
+	.current_max = CHARGE_I_MAX,
+	.current_min = CHARGE_I_MIN,
 	.current_step = CHARGE_I_STEP,
-	.input_current_max  = INPUT_I_MAX,
-	.input_current_min  = INPUT_I_MIN,
+	.input_current_max = INPUT_I_MAX,
+	.input_current_min = INPUT_I_MIN,
 	.input_current_step = INPUT_I_STEP,
 };
 
@@ -54,8 +67,8 @@ static const struct rt946x_init_setting default_init_setting = {
 	.boost_current = 1500,
 };
 
-__attribute__((weak))
-const struct rt946x_init_setting *board_rt946x_init_setting(void)
+__attribute__((weak)) const struct rt946x_init_setting *
+board_rt946x_init_setting(void)
 {
 	return &default_init_setting;
 }
@@ -122,11 +135,17 @@ static const unsigned char mt6370_reg_en_hidden_mode[] = {
 };
 
 static const unsigned char mt6370_val_en_hidden_mode[] = {
-	0x96, 0x69, 0xC3, 0x3C,
+	0x96,
+	0x69,
+	0xC3,
+	0x3C,
 };
 
 static const unsigned char mt6370_val_en_test_mode[] = {
-	0x69, 0x96, 0x63, 0x70,
+	0x69,
+	0x96,
+	0x63,
+	0x70,
 };
 #endif /* CONFIG_CHARGER_MT6370 */
 
@@ -179,17 +198,13 @@ enum rt946x_irq {
 };
 
 static uint8_t rt946x_irqmask[RT946X_IRQ_COUNT] = {
-	0xBF, 0xFF, 0xFF, 0xFF, 0xFF,
-	0xFF, 0xFC, 0xFF, 0xFF, 0xFF,
-	0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-	0xFF,
+	0xBF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
 };
 
 static const uint8_t rt946x_irq_maskall[RT946X_IRQ_COUNT] = {
-	0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-	0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-	0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-	0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
 };
 #endif
 
@@ -220,8 +235,7 @@ static enum ec_error_list rt946x_block_write(int chgnum, int reg,
 					     const uint8_t *val, int len)
 {
 	return i2c_write_block(chg_chips[chgnum].i2c_port,
-			       chg_chips[chgnum].i2c_addr_flags,
-			       reg, val, len);
+			       chg_chips[chgnum].i2c_addr_flags, reg, val, len);
 }
 
 static int rt946x_update_bits(int chgnum, int reg, int mask, int val)
@@ -296,13 +310,13 @@ static int mt6370_enable_hidden_mode(int chgnum, int en)
 	if (in_interrupt_context()) {
 		CPRINTS("Err: use hidden mode in IRQ");
 		return EC_ERROR_INVAL;
-        }
+	}
 
 	mutex_lock(&hidden_mode_lock);
 	if (en) {
 		if (hidden_mode_cnt == 0) {
-			rv = rt946x_block_write(chgnum,
-				mt6370_reg_en_hidden_mode[0],
+			rv = rt946x_block_write(
+				chgnum, mt6370_reg_en_hidden_mode[0],
 				mt6370_val_en_hidden_mode,
 				ARRAY_SIZE(mt6370_val_en_hidden_mode));
 			if (rv)
@@ -373,15 +387,15 @@ static int mt6370_ichg_workaround(int chgnum, int new_ichg)
 
 static inline int rt946x_enable_wdt(int chgnum, int en)
 {
-	return (en ? rt946x_set_bit : rt946x_clr_bit)
-		(chgnum, RT946X_REG_CHGCTRL13, RT946X_MASK_WDT_EN);
+	return (en ? rt946x_set_bit : rt946x_clr_bit)(
+		chgnum, RT946X_REG_CHGCTRL13, RT946X_MASK_WDT_EN);
 }
 
 /* Enable high-impedance mode */
 static inline int rt946x_enable_hz(int chgnum, int en)
 {
-	return (en ? rt946x_set_bit : rt946x_clr_bit)
-		(chgnum, RT946X_REG_CHGCTRL1, RT946X_MASK_HZ_EN);
+	return (en ? rt946x_set_bit : rt946x_clr_bit)(
+		chgnum, RT946X_REG_CHGCTRL1, RT946X_MASK_HZ_EN);
 }
 
 int rt946x_por_reset(void)
@@ -457,7 +471,7 @@ static int rt946x_set_ieoc(int chgnum, unsigned int ieoc)
 	CPRINTS("ieoc=%d", ieoc);
 
 	return rt946x_update_bits(chgnum, RT946X_REG_CHGCTRL9, RT946X_MASK_IEOC,
-				reg_ieoc << RT946X_SHIFT_IEOC);
+				  reg_ieoc << RT946X_SHIFT_IEOC);
 }
 
 static int rt946x_set_mivr(int chgnum, unsigned int mivr)
@@ -465,12 +479,12 @@ static int rt946x_set_mivr(int chgnum, unsigned int mivr)
 	uint8_t reg_mivr = 0;
 
 	reg_mivr = rt946x_closest_reg(RT946X_MIVR_MIN, RT946X_MIVR_MAX,
-		RT946X_MIVR_STEP, mivr);
+				      RT946X_MIVR_STEP, mivr);
 
 	CPRINTS("mivr=%d", mivr);
 
 	return rt946x_update_bits(chgnum, RT946X_REG_CHGCTRL6, RT946X_MASK_MIVR,
-		reg_mivr << RT946X_SHIFT_MIVR);
+				  reg_mivr << RT946X_SHIFT_MIVR);
 }
 
 static int rt946x_set_boost_voltage(int chgnum, unsigned int voltage)
@@ -478,13 +492,14 @@ static int rt946x_set_boost_voltage(int chgnum, unsigned int voltage)
 	uint8_t reg_voltage = 0;
 
 	reg_voltage = rt946x_closest_reg(RT946X_BOOST_VOLTAGE_MIN,
-		RT946X_BOOST_VOLTAGE_MAX, RT946X_BOOST_VOLTAGE_STEP, voltage);
+					 RT946X_BOOST_VOLTAGE_MAX,
+					 RT946X_BOOST_VOLTAGE_STEP, voltage);
 
 	CPRINTS("voltage=%d", voltage);
 
 	return rt946x_update_bits(chgnum, RT946X_REG_CHGCTRL5,
-		RT946X_MASK_BOOST_VOLTAGE,
-		reg_voltage << RT946X_SHIFT_BOOST_VOLTAGE);
+				  RT946X_MASK_BOOST_VOLTAGE,
+				  reg_voltage << RT946X_SHIFT_BOOST_VOLTAGE);
 }
 
 static int rt946x_set_boost_current(int chgnum, unsigned int current)
@@ -504,8 +519,8 @@ static int rt946x_set_boost_current(int chgnum, unsigned int current)
 	CPRINTS("current=%d", current);
 
 	return rt946x_update_bits(chgnum, RT946X_REG_CHGCTRL10,
-		RT946X_MASK_BOOST_CURRENT,
-		i << RT946X_SHIFT_BOOST_CURRENT);
+				  RT946X_MASK_BOOST_CURRENT,
+				  i << RT946X_SHIFT_BOOST_CURRENT);
 }
 
 static int rt946x_set_ircmp_vclamp(int chgnum, unsigned int vclamp)
@@ -513,13 +528,14 @@ static int rt946x_set_ircmp_vclamp(int chgnum, unsigned int vclamp)
 	uint8_t reg_vclamp = 0;
 
 	reg_vclamp = rt946x_closest_reg(RT946X_IRCMP_VCLAMP_MIN,
-		RT946X_IRCMP_VCLAMP_MAX, RT946X_IRCMP_VCLAMP_STEP, vclamp);
+					RT946X_IRCMP_VCLAMP_MAX,
+					RT946X_IRCMP_VCLAMP_STEP, vclamp);
 
 	CPRINTS("vclamp=%d", vclamp);
 
 	return rt946x_update_bits(chgnum, RT946X_REG_CHGCTRL18,
-		RT946X_MASK_IRCMP_VCLAMP,
-		reg_vclamp << RT946X_SHIFT_IRCMP_VCLAMP);
+				  RT946X_MASK_IRCMP_VCLAMP,
+				  reg_vclamp << RT946X_SHIFT_IRCMP_VCLAMP);
 }
 
 static int rt946x_set_ircmp_res(int chgnum, unsigned int res)
@@ -527,7 +543,7 @@ static int rt946x_set_ircmp_res(int chgnum, unsigned int res)
 	uint8_t reg_res = 0;
 
 	reg_res = rt946x_closest_reg(RT946X_IRCMP_RES_MIN, RT946X_IRCMP_RES_MAX,
-		RT946X_IRCMP_RES_STEP, res);
+				     RT946X_IRCMP_RES_STEP, res);
 
 	CPRINTS("res=%d", res);
 
@@ -541,7 +557,7 @@ static int rt946x_set_vprec(int chgnum, unsigned int vprec)
 	uint8_t reg_vprec = 0;
 
 	reg_vprec = rt946x_closest_reg(RT946X_VPREC_MIN, RT946X_VPREC_MAX,
-		RT946X_VPREC_STEP, vprec);
+				       RT946X_VPREC_STEP, vprec);
 
 	CPRINTS("vprec=%d", vprec);
 
@@ -555,7 +571,7 @@ static int rt946x_set_iprec(int chgnum, unsigned int iprec)
 	uint8_t reg_iprec = 0;
 
 	reg_iprec = rt946x_closest_reg(RT946X_IPREC_MIN, RT946X_IPREC_MAX,
-		RT946X_IPREC_STEP, iprec);
+				       RT946X_IPREC_STEP, iprec);
 
 	CPRINTS("iprec=%d", iprec);
 
@@ -629,12 +645,10 @@ static int rt946x_init_setting(int chgnum)
 	rv = rt946x_set_ieoc(chgnum, setting->eoc_current);
 	if (rv)
 		return rv;
-	rv = rt946x_set_boost_voltage(chgnum,
-		setting->boost_voltage);
+	rv = rt946x_set_boost_voltage(chgnum, setting->boost_voltage);
 	if (rv)
 		return rv;
-	rv = rt946x_set_boost_current(chgnum,
-		setting->boost_current);
+	rv = rt946x_set_boost_current(chgnum, setting->boost_current);
 	if (rv)
 		return rv;
 	rv = rt946x_set_ircmp_vclamp(chgnum, setting->ircmp_vclamp);
@@ -644,7 +658,8 @@ static int rt946x_init_setting(int chgnum)
 	if (rv)
 		return rv;
 	rv = rt946x_set_vprec(chgnum, batt_info->precharge_voltage ?
-			batt_info->precharge_voltage : batt_info->voltage_min);
+					      batt_info->precharge_voltage :
+					      batt_info->voltage_min);
 	if (rv)
 		return rv;
 	rv = rt946x_set_iprec(chgnum, batt_info->precharge_current);
@@ -652,8 +667,9 @@ static int rt946x_init_setting(int chgnum)
 		return rv;
 
 #ifdef CONFIG_CHARGER_MT6370_BACKLIGHT
-	rt946x_write8(chgnum, MT6370_BACKLIGHT_BLEN,
-		      MT6370_MASK_BLED_EXT_EN | MT6370_MASK_BLED_EN |
+	rt946x_write8(
+		chgnum, MT6370_BACKLIGHT_BLEN,
+		MT6370_MASK_BLED_EXT_EN | MT6370_MASK_BLED_EN |
 			MT6370_MASK_BLED_1CH_EN | MT6370_MASK_BLED_2CH_EN |
 			MT6370_MASK_BLED_3CH_EN | MT6370_MASK_BLED_4CH_EN |
 			MT6370_BLED_CODE_LINEAR);
@@ -668,8 +684,8 @@ static int rt946x_init_setting(int chgnum)
 #ifdef CONFIG_CHARGER_OTG
 static enum ec_error_list rt946x_enable_otg_power(int chgnum, int enabled)
 {
-	return (enabled ? rt946x_set_bit : rt946x_clr_bit)
-		(chgnum, RT946X_REG_CHGCTRL1, RT946X_MASK_OPA_MODE);
+	return (enabled ? rt946x_set_bit : rt946x_clr_bit)(
+		chgnum, RT946X_REG_CHGCTRL1, RT946X_MASK_OPA_MODE);
 }
 
 static int rt946x_is_sourcing_otg_power(int chgnum, int port)
@@ -683,36 +699,36 @@ static int rt946x_is_sourcing_otg_power(int chgnum, int port)
 }
 #endif
 
-static enum ec_error_list rt946x_set_input_current(int chgnum,
-						   int input_current)
+static enum ec_error_list rt946x_set_input_current_limit(int chgnum,
+							 int input_current)
 {
 	uint8_t reg_iin = 0;
-	const struct charger_info * const info = rt946x_get_info(chgnum);
+	const struct charger_info *const info = rt946x_get_info(chgnum);
 
 	reg_iin = rt946x_closest_reg(info->input_current_min,
-		info->input_current_max, info->input_current_step,
-		input_current);
+				     info->input_current_max,
+				     info->input_current_step, input_current);
 
 	CPRINTS("iin=%d", input_current);
 
 	return rt946x_update_bits(chgnum, RT946X_REG_CHGCTRL3, RT946X_MASK_AICR,
-		reg_iin << RT946X_SHIFT_AICR);
+				  reg_iin << RT946X_SHIFT_AICR);
 }
 
-static enum ec_error_list rt946x_get_input_current(int chgnum,
-						   int *input_current)
+static enum ec_error_list rt946x_get_input_current_limit(int chgnum,
+							 int *input_current)
 {
 	int rv;
 	int val = 0;
-	const struct charger_info * const info = rt946x_get_info(chgnum);
+	const struct charger_info *const info = rt946x_get_info(chgnum);
 
 	rv = rt946x_read8(chgnum, RT946X_REG_CHGCTRL3, &val);
 	if (rv)
 		return rv;
 
 	val = (val & RT946X_MASK_AICR) >> RT946X_SHIFT_AICR;
-	*input_current = val * info->input_current_step
-		+ info->input_current_min;
+	*input_current =
+		val * info->input_current_step + info->input_current_min;
 
 	return EC_SUCCESS;
 }
@@ -768,7 +784,6 @@ static enum ec_error_list rt946x_get_status(int chgnum, int *status)
 	if (val & RT946X_MASK_CHG_VBATOV)
 		*status |= CHARGER_VOLTAGE_OR;
 
-
 	rv = rt946x_read8(chgnum, RT946X_REG_CHGNTC, &val);
 	if (rv)
 		return rv;
@@ -819,7 +834,7 @@ static enum ec_error_list rt946x_get_current(int chgnum, int *current)
 {
 	int rv;
 	int val = 0;
-	const struct charger_info * const info = rt946x_get_info(chgnum);
+	const struct charger_info *const info = rt946x_get_info(chgnum);
 
 	rv = rt946x_read8(chgnum, RT946X_REG_CHGCTRL7, &val);
 	if (rv)
@@ -892,7 +907,7 @@ static enum ec_error_list rt946x_get_voltage(int chgnum, int *voltage)
 {
 	int rv;
 	int val = 0;
-	const struct charger_info * const info = rt946x_get_info(chgnum);
+	const struct charger_info *const info = rt946x_get_info(chgnum);
 
 	rv = rt946x_read8(chgnum, RT946X_REG_CHGCTRL4, &val);
 	if (rv)
@@ -907,13 +922,13 @@ static enum ec_error_list rt946x_get_voltage(int chgnum, int *voltage)
 static enum ec_error_list rt946x_set_voltage(int chgnum, int voltage)
 {
 	uint8_t reg_cv = 0;
-	const struct charger_info * const info = rt946x_get_info(chgnum);
+	const struct charger_info *const info = rt946x_get_info(chgnum);
 
 	reg_cv = rt946x_closest_reg(info->voltage_min, info->voltage_max,
-		info->voltage_step, voltage);
+				    info->voltage_step, voltage);
 
 	return rt946x_update_bits(chgnum, RT946X_REG_CHGCTRL4, RT946X_MASK_CV,
-		reg_cv << RT946X_SHIFT_CV);
+				  reg_cv << RT946X_SHIFT_CV);
 }
 
 static enum ec_error_list rt946x_discharge_on_ac(int chgnum, int enable)
@@ -927,8 +942,8 @@ static int rt946x_enable_ilim_pin(int chgnum, int en)
 {
 	int ret;
 
-	ret = (en ? rt946x_set_bit : rt946x_clr_bit)
-		(chgnum, RT946X_REG_CHGCTRL3, RT946X_MASK_ILIMEN);
+	ret = (en ? rt946x_set_bit : rt946x_clr_bit)(
+		chgnum, RT946X_REG_CHGCTRL3, RT946X_MASK_ILIMEN);
 
 	return ret;
 }
@@ -988,7 +1003,8 @@ static int rt946x_set_aicl_vth(int chgnum, uint8_t aicl_vth)
 	uint8_t reg_aicl_vth = 0;
 
 	reg_aicl_vth = rt946x_closest_reg(RT946X_AICLVTH_MIN,
-		RT946X_AICLVTH_MAX, RT946X_AICLVTH_STEP, aicl_vth);
+					  RT946X_AICLVTH_MAX,
+					  RT946X_AICLVTH_STEP, aicl_vth);
 
 	return rt946x_update_bits(chgnum, RT946X_REG_CHGCTRL14,
 				  RT946X_MASK_AICLVTH,
@@ -1048,7 +1064,7 @@ static int rt946x_ramp_get_current_limit(int chgnum)
 	int rv;
 	int input_current = 0;
 
-	rv = rt946x_get_input_current(chgnum, &input_current);
+	rv = rt946x_get_input_current_limit(chgnum, &input_current);
 
 	return rv ? -1 : input_current;
 }
@@ -1066,14 +1082,13 @@ static void rt946x_init(int chgnum)
 static int mt6370_detect_apple_samsung_ta(int chgnum, int usb_stat)
 {
 	int ret, reg;
-	int chg_type =
-		(usb_stat & MT6370_MASK_USB_STATUS) >> MT6370_SHIFT_USB_STATUS;
+	int chg_type = (usb_stat & MT6370_MASK_USB_STATUS) >>
+		       MT6370_SHIFT_USB_STATUS;
 	int dp_2_3v, dm_2_3v;
 
 	/* Only SDP/CDP/DCP could possibly be Apple/Samsung TA */
 	if (chg_type != MT6370_CHG_TYPE_SDPNSTD &&
-	    chg_type != MT6370_CHG_TYPE_CDP &&
-	    chg_type != MT6370_CHG_TYPE_DCP)
+	    chg_type != MT6370_CHG_TYPE_CDP && chg_type != MT6370_CHG_TYPE_DCP)
 		return chg_type;
 
 	if (chg_type == MT6370_CHG_TYPE_SDPNSTD ||
@@ -1102,13 +1117,13 @@ static int mt6370_detect_apple_samsung_ta(int chgnum, int usb_stat)
 	ret = rt946x_update_bits(chgnum, MT6370_REG_QCSTATUS2,
 				 MT6360_MASK_CHECK_DPDM,
 				 MT6370_MASK_APP_REF | MT6370_MASK_APP_SS_PL |
-				 MT6370_MASK_APP_SS_EN);
+					 MT6370_MASK_APP_SS_EN);
 	ret |= rt946x_read8(chgnum, MT6370_REG_QCSTATUS2, &reg);
 	dp_2_3v = reg & MT6370_MASK_APP_OUT;
 
 	/* Check D- > 2.3 V */
-	ret |= rt946x_update_bits(chgnum,
-		MT6370_REG_QCSTATUS2, MT6360_MASK_CHECK_DPDM,
+	ret |= rt946x_update_bits(
+		chgnum, MT6370_REG_QCSTATUS2, MT6360_MASK_CHECK_DPDM,
 		MT6370_MASK_APP_REF | MT6370_MASK_APP_DPDM_IN |
 			MT6370_MASK_APP_SS_PL | MT6370_MASK_APP_SS_EN);
 	ret |= rt946x_read8(chgnum, MT6370_REG_QCSTATUS2, &reg);
@@ -1218,7 +1233,7 @@ static int rt946x_get_bc12_ilim(int charge_supplier)
 		    IS_ENABLED(CONFIG_CHARGE_RAMP_HW))
 			/* A conservative value to prevent a bad charger. */
 			return RT946X_AICR_TYP2MAX(USB_CHARGER_MAX_CURR_MA);
-		/* fallback */
+		__fallthrough;
 	case CHARGE_SUPPLIER_BC12_CDP:
 		return USB_CHARGER_MAX_CURR_MA;
 	case CHARGE_SUPPLIER_BC12_SDP:
@@ -1314,7 +1329,7 @@ int rt946x_get_adc(enum rt946x_adc_in_sel adc_sel, int *adc_val)
 	if (in_interrupt_context()) {
 		CPRINTS("Err: use ADC in IRQ");
 		return EC_ERROR_INVAL;
-        }
+	}
 	mutex_lock(&adc_access_lock);
 #ifdef CONFIG_CHARGER_MT6370
 	mt6370_enable_hidden_mode(CHARGER_SOLO, 1);
@@ -1328,7 +1343,7 @@ int rt946x_get_adc(enum rt946x_adc_in_sel adc_sel, int *adc_val)
 		goto out;
 
 	if (adc_sel == MT6370_ADC_IBUS) {
-		rv = charger_get_input_current(CHARGER_SOLO, &aicr);
+		rv = charger_get_input_current_limit(CHARGER_SOLO, &aicr);
 		if (rv)
 			goto out;
 	}
@@ -1342,8 +1357,8 @@ int rt946x_get_adc(enum rt946x_adc_in_sel adc_sel, int *adc_val)
 	for (i = 0; i < max_wait_times; i++) {
 		msleep(35);
 		rv = mt6370_pmu_reg_test_bit(CHARGER_SOLO, RT946X_REG_CHGADC,
-					      RT946X_SHIFT_ADC_START,
-					      &adc_start);
+					     RT946X_SHIFT_ADC_START,
+					     &adc_start);
 		if (!adc_start && rv == 0)
 			break;
 	}
@@ -1364,8 +1379,9 @@ int rt946x_get_adc(enum rt946x_adc_in_sel adc_sel, int *adc_val)
 	*adc_val = adc_result;
 #elif defined(CONFIG_CHARGER_MT6370)
 	/* Calculate ADC value */
-	adc_result = (adc_data_h * 256 + adc_data_l)
-			* mt6370_adc_unit[adc_sel] + mt6370_adc_offset[adc_sel];
+	adc_result =
+		(adc_data_h * 256 + adc_data_l) * mt6370_adc_unit[adc_sel] +
+		mt6370_adc_offset[adc_sel];
 
 	/* For TS_BAT/TS_BUS, the real unit is 0.25, here we use 25(unit) */
 	if (adc_sel == MT6370_ADC_TS_BAT)
@@ -1434,7 +1450,7 @@ static int mt6370_pmu_chg_mivr_irq_handler(int chgnum)
 	int rv, ibus = 0, mivr_stat;
 
 	rv = mt6370_pmu_reg_test_bit(chgnum, MT6370_REG_CHGSTAT1,
-				MT6370_SHIFT_MIVR_STAT, &mivr_stat);
+				     MT6370_SHIFT_MIVR_STAT, &mivr_stat);
 	if (rv)
 		return rv;
 
@@ -1515,7 +1531,7 @@ static void rt946x_bc12_workaround(void)
 }
 DECLARE_DEFERRED(rt946x_bc12_workaround);
 
-static void rt946x_usb_charger_task(const int unused)
+static void rt946x_usb_charger_task_init(const int unused_port)
 {
 	struct charge_port_info chg;
 	int bc12_type = CHARGE_SUPPLIER_NONE;
@@ -1544,33 +1560,26 @@ static void rt946x_usb_charger_task(const int unused)
 					mt6370_get_bc12_device_type(chg_type);
 				chg.current = mt6370_get_bc12_ilim(bc12_type);
 			} else {
-				bc12_type =
-				    rt946x_get_bc12_device_type(CHARGER_SOLO,
-								    chg_type);
+				bc12_type = rt946x_get_bc12_device_type(
+					CHARGER_SOLO, chg_type);
 				chg.current = rt946x_get_bc12_ilim(bc12_type);
 			}
 			CPRINTS("BC12 type %d", bc12_type);
 			if (bc12_type == CHARGE_SUPPLIER_NONE)
 				goto bc12_none;
-			if (IS_ENABLED(CONFIG_WIRELESS_CHARGER_P9221_R7) &&
-			    bc12_type == CHARGE_SUPPLIER_BC12_SDP &&
-			    wpc_chip_is_online()) {
-					p9221_notify_vbus_change(1);
-					CPRINTS("WPC ON");
-			}
 			if (bc12_type == CHARGE_SUPPLIER_BC12_SDP &&
 			    ++bc12_cnt < max_bc12_cnt) {
 				/*
 				 * defer the workaround and awaiting for
 				 * waken up by the interrupt.
 				 */
-				hook_call_deferred(
-					&rt946x_bc12_workaround_data, 5);
+				hook_call_deferred(&rt946x_bc12_workaround_data,
+						   5);
 				goto wait_event;
 			}
 
 			charge_manager_update_charge(bc12_type, 0, &chg);
-bc12_none:
+		bc12_none:
 			rt946x_enable_bc12_detection(CHARGER_SOLO, 0);
 		}
 
@@ -1579,13 +1588,10 @@ static void rt946x_usb_charger_task(const int unused)
 		    bc12_type != CHARGE_SUPPLIER_NONE) {
 			CPRINTS("VBUS detached");
 			bc12_cnt = 0;
-#ifdef CONFIG_WIRELESS_CHARGER_P9221_R7
-			p9221_notify_vbus_change(0);
-#endif
 			charge_manager_update_charge(bc12_type, 0, NULL);
 		}
 
-wait_event:
+	wait_event:
 		task_wait_event(-1);
 	}
 }
@@ -1605,8 +1611,8 @@ static int rt946x_ramp_max(int supplier, int sup_curr)
 
 int rt946x_enable_charger_boost(int en)
 {
-	return (en ? rt946x_set_bit : rt946x_clr_bit)
-		(CHARGER_SOLO, RT946X_REG_CHGCTRL2, RT946X_MASK_CHG_EN);
+	return (en ? rt946x_set_bit : rt946x_clr_bit)(
+		CHARGER_SOLO, RT946X_REG_CHGCTRL2, RT946X_MASK_CHG_EN);
 }
 
 /*
@@ -1618,7 +1624,8 @@ int rt946x_is_vbus_ready(void)
 	int val = 0;
 
 	return rt946x_read8(CHARGER_SOLO, RT946X_REG_CHGSTATC, &val) ?
-	       0 : !!(val & RT946X_MASK_PWR_RDY);
+		       0 :
+		       !!(val & RT946X_MASK_PWR_RDY);
 }
 
 int rt946x_is_charge_done(void)
@@ -1636,10 +1643,10 @@ int rt946x_is_charge_done(void)
 int rt946x_cutoff_battery(void)
 {
 #ifdef CONFIG_CHARGER_MT6370
-/*
- * We should lock ADC usage to prevent from using ADC while
- * cut-off. Or this might cause the ADC power not turning off.
- */
+	/*
+	 * We should lock ADC usage to prevent from using ADC while
+	 * cut-off. Or this might cause the ADC power not turning off.
+	 */
 
 	int rv;
 
@@ -1662,7 +1669,7 @@ int rt946x_cutoff_battery(void)
 	/* disable chg auto sensing */
 	mt6370_enable_hidden_mode(CHARGER_SOLO, 1);
 	rv = rt946x_clr_bit(CHARGER_SOLO, MT6370_REG_CHGHIDDENCTRL15,
-				MT6370_MASK_ADC_TS_AUTO);
+			    MT6370_MASK_ADC_TS_AUTO);
 	mt6370_enable_hidden_mode(CHARGER_SOLO, 0);
 	if (rv)
 		goto out;
@@ -1682,14 +1689,14 @@ int rt946x_cutoff_battery(void)
 
 int rt946x_enable_charge_termination(int en)
 {
-	return (en ? rt946x_set_bit : rt946x_clr_bit)
-		(CHARGER_SOLO, RT946X_REG_CHGCTRL2, RT946X_MASK_TE);
+	return (en ? rt946x_set_bit : rt946x_clr_bit)(
+		CHARGER_SOLO, RT946X_REG_CHGCTRL2, RT946X_MASK_TE);
 }
 
 int rt946x_enable_charge_eoc(int en)
 {
-	return (en ? rt946x_set_bit : rt946x_clr_bit)
-		(CHARGER_SOLO, RT946X_REG_CHGCTRL9, RT946X_MASK_EOC);
+	return (en ? rt946x_set_bit : rt946x_clr_bit)(
+		CHARGER_SOLO, RT946X_REG_CHGCTRL9, RT946X_MASK_EOC);
 }
 
 #ifdef CONFIG_CHARGER_MT6370
@@ -1732,29 +1739,26 @@ int mt6370_db_set_voltages(int vbst, int vpos, int vneg)
 	int rv;
 
 	/* set display bias VBST */
-	rv = rt946x_update_bits(CHARGER_SOLO, MT6370_REG_DBVBST,
-				MT6370_MASK_DB_VBST,
-				rt946x_closest_reg(MT6370_DB_VBST_MIN,
-						   MT6370_DB_VBST_MAX,
-						   MT6370_DB_VBST_STEP, vbst));
+	rv = rt946x_update_bits(
+		CHARGER_SOLO, MT6370_REG_DBVBST, MT6370_MASK_DB_VBST,
+		rt946x_closest_reg(MT6370_DB_VBST_MIN, MT6370_DB_VBST_MAX,
+				   MT6370_DB_VBST_STEP, vbst));
 
 	/* set display bias VPOS */
-	rv |= rt946x_update_bits(CHARGER_SOLO, MT6370_REG_DBVPOS,
-				 MT6370_MASK_DB_VPOS,
-				 rt946x_closest_reg(MT6370_DB_VPOS_MIN,
-						    MT6370_DB_VPOS_MAX,
-						    MT6370_DB_VPOS_STEP, vpos));
+	rv |= rt946x_update_bits(
+		CHARGER_SOLO, MT6370_REG_DBVPOS, MT6370_MASK_DB_VPOS,
+		rt946x_closest_reg(MT6370_DB_VPOS_MIN, MT6370_DB_VPOS_MAX,
+				   MT6370_DB_VPOS_STEP, vpos));
 
 	/* set display bias VNEG */
-	rv |= rt946x_update_bits(CHARGER_SOLO, MT6370_REG_DBVNEG,
-				 MT6370_MASK_DB_VNEG,
-				 rt946x_closest_reg(MT6370_DB_VNEG_MIN,
-						    MT6370_DB_VNEG_MAX,
-						    MT6370_DB_VNEG_STEP, vneg));
+	rv |= rt946x_update_bits(
+		CHARGER_SOLO, MT6370_REG_DBVNEG, MT6370_MASK_DB_VNEG,
+		rt946x_closest_reg(MT6370_DB_VNEG_MIN, MT6370_DB_VNEG_MAX,
+				   MT6370_DB_VNEG_STEP, vneg));
 
 	/* Enable VNEG/VPOS discharge when VNEG/VPOS rails disabled. */
-	rv |= rt946x_update_bits(CHARGER_SOLO,
-		MT6370_REG_DBCTRL2,
+	rv |= rt946x_update_bits(
+		CHARGER_SOLO, MT6370_REG_DBCTRL2,
 		MT6370_MASK_DB_VNEG_DISC | MT6370_MASK_DB_VPOS_DISC,
 		MT6370_MASK_DB_VNEG_DISC | MT6370_MASK_DB_VPOS_DISC);
 
@@ -1882,8 +1886,8 @@ const struct charger_drv rt946x_drv = {
 	.set_voltage = &rt946x_set_voltage,
 	.discharge_on_ac = &rt946x_discharge_on_ac,
 	.get_vbus_voltage = &rt946x_get_vbus_voltage,
-	.set_input_current = &rt946x_set_input_current,
-	.get_input_current = &rt946x_get_input_current,
+	.set_input_current_limit = &rt946x_set_input_current_limit,
+	.get_input_current_limit = &rt946x_get_input_current_limit,
 	.manufacturer_id = &rt946x_manufacturer_id,
 	.device_id = &rt946x_device_id,
 	.get_option = &rt946x_get_option,
@@ -1898,7 +1902,9 @@ const struct charger_drv rt946x_drv = {
 
 #ifdef HAS_TASK_USB_CHG
 const struct bc12_drv rt946x_bc12_drv = {
-	.usb_charger_task = rt946x_usb_charger_task,
+	.usb_charger_task_init = rt946x_usb_charger_task_init,
+	/* events handled in init */
+	.usb_charger_task_event = NULL,
 	.ramp_allowed = rt946x_ramp_allowed,
 	.ramp_max = rt946x_ramp_max,
 };
diff --git a/driver/charger/rt946x.h b/driver/charger/rt946x.h
index 38ec200c77..9d0247ac5d 100644
--- a/driver/charger/rt946x.h
+++ b/driver/charger/rt946x.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,707 +8,693 @@
 #ifndef __CROS_EC_RT946X_H
 #define __CROS_EC_RT946X_H
 
-/* Charger parameters */
-#define CHARGER_NAME	RT946X_CHARGER_NAME
-#define CHARGE_V_MAX	4710
-#define CHARGE_V_MIN	3900
-#define CHARGE_V_STEP	10
-#define CHARGE_I_MAX	5000
-#define CHARGE_I_MIN	100
-#define CHARGE_I_OFF	0
-#define CHARGE_I_STEP	100
-#define INPUT_I_MAX	3250
-#define INPUT_I_MIN	100
-#define INPUT_I_STEP	50
-
 /* Registers for rt9466, rt9467 */
 #if defined(CONFIG_CHARGER_RT9466) || defined(CONFIG_CHARGER_RT9467)
-#define RT946X_REG_CORECTRL0		0x00
-#define RT946X_REG_CORECTRL_RST		RT946X_REG_CORECTRL0
-#define RT946X_REG_CHGCTRL1		0x01
-#define RT946X_REG_CHGCTRL2		0x02
-#define RT946X_REG_CHGCTRL3		0x03
-#define RT946X_REG_CHGCTRL4		0x04
-#define RT946X_REG_CHGCTRL5		0x05
-#define RT946X_REG_CHGCTRL6		0x06
-#define RT946X_REG_CHGCTRL7		0x07
-#define RT946X_REG_CHGCTRL8		0x08
-#define RT946X_REG_CHGCTRL9		0x09
-#define RT946X_REG_CHGCTRL10		0x0A
-#define RT946X_REG_CHGCTRL11		0x0B
-#define RT946X_REG_CHGCTRL12		0x0C
-#define RT946X_REG_CHGCTRL13		0x0D
-#define RT946X_REG_CHGCTRL14		0x0E
-#define RT946X_REG_CHGCTRL15		0x0F
-#define RT946X_REG_CHGCTRL16		0x10
-#define RT946X_REG_CHGADC		0x11
+#define RT946X_REG_CORECTRL0 0x00
+#define RT946X_REG_CORECTRL_RST RT946X_REG_CORECTRL0
+#define RT946X_REG_CHGCTRL1 0x01
+#define RT946X_REG_CHGCTRL2 0x02
+#define RT946X_REG_CHGCTRL3 0x03
+#define RT946X_REG_CHGCTRL4 0x04
+#define RT946X_REG_CHGCTRL5 0x05
+#define RT946X_REG_CHGCTRL6 0x06
+#define RT946X_REG_CHGCTRL7 0x07
+#define RT946X_REG_CHGCTRL8 0x08
+#define RT946X_REG_CHGCTRL9 0x09
+#define RT946X_REG_CHGCTRL10 0x0A
+#define RT946X_REG_CHGCTRL11 0x0B
+#define RT946X_REG_CHGCTRL12 0x0C
+#define RT946X_REG_CHGCTRL13 0x0D
+#define RT946X_REG_CHGCTRL14 0x0E
+#define RT946X_REG_CHGCTRL15 0x0F
+#define RT946X_REG_CHGCTRL16 0x10
+#define RT946X_REG_CHGADC 0x11
 
 #ifdef CONFIG_CHARGER_RT9467
-#define RT946X_REG_DPDM1		0x12
-#define RT946X_REG_DPDM2		0x13
-#define RT946X_REG_DPDM3		0x14
+#define RT946X_REG_DPDM1 0x12
+#define RT946X_REG_DPDM2 0x13
+#define RT946X_REG_DPDM3 0x14
 #endif
 
-#define RT946X_REG_CHGCTRL19		0x18
-#define RT946X_REG_CHGCTRL17		0x19
-#define RT946X_REG_CHGCTRL18		0x1A
-#define RT946X_REG_CHGHIDDENCTRL2	0x21
-#define RT946X_REG_CHGHIDDENCTRL4	0x23
-#define RT946X_REG_CHGHIDDENCTRL6	0x25
-#define RT946X_REG_CHGHIDDENCTRL7	0x26
-#define RT946X_REG_CHGHIDDENCTRL8	0x27
-#define RT946X_REG_CHGHIDDENCTRL9	0x28
-#define RT946X_REG_CHGHIDDENCTRL15	0x2E
-#define RT946X_REG_DEVICEID		0x40
-#define RT946X_REG_CHGSTAT		0x42
-#define RT946X_REG_CHGNTC		0x43
-#define RT946X_REG_ADCDATAH		0x44
-#define RT946X_REG_ADCDATAL		0x45
-#define RT946X_REG_CHGSTATC		0x50
-#define RT946X_REG_CHGFAULT		0x51
-#define RT946X_REG_TSSTATC		0x52
-#define RT946X_REG_CHGIRQ1		0x53
-#define RT946X_REG_CHGIRQ2		0x54
-#define RT946X_REG_CHGIRQ3		0x55
+#define RT946X_REG_CHGCTRL19 0x18
+#define RT946X_REG_CHGCTRL17 0x19
+#define RT946X_REG_CHGCTRL18 0x1A
+#define RT946X_REG_CHGHIDDENCTRL2 0x21
+#define RT946X_REG_CHGHIDDENCTRL4 0x23
+#define RT946X_REG_CHGHIDDENCTRL6 0x25
+#define RT946X_REG_CHGHIDDENCTRL7 0x26
+#define RT946X_REG_CHGHIDDENCTRL8 0x27
+#define RT946X_REG_CHGHIDDENCTRL9 0x28
+#define RT946X_REG_CHGHIDDENCTRL15 0x2E
+#define RT946X_REG_DEVICEID 0x40
+#define RT946X_REG_CHGSTAT 0x42
+#define RT946X_REG_CHGNTC 0x43
+#define RT946X_REG_ADCDATAH 0x44
+#define RT946X_REG_ADCDATAL 0x45
+#define RT946X_REG_CHGSTATC 0x50
+#define RT946X_REG_CHGFAULT 0x51
+#define RT946X_REG_TSSTATC 0x52
+#define RT946X_REG_CHGIRQ1 0x53
+#define RT946X_REG_CHGIRQ2 0x54
+#define RT946X_REG_CHGIRQ3 0x55
 
 #ifdef CONFIG_CHARGER_RT9467
-#define RT946X_REG_DPDMIRQ		0x56
+#define RT946X_REG_DPDMIRQ 0x56
 #endif
 
-#define RT946X_REG_CHGSTATCCTRL		0x60
-#define RT946X_REG_CHGFAULTCTRL		0x61
-#define RT946X_REG_TSSTATCCTRL		0x62
-#define RT946X_REG_CHGIRQ1CTRL		0x63
-#define RT946X_REG_CHGIRQ2CTRL		0x64
-#define RT946X_REG_CHGIRQ3CTRL		0x65
+#define RT946X_REG_CHGSTATCCTRL 0x60
+#define RT946X_REG_CHGFAULTCTRL 0x61
+#define RT946X_REG_TSSTATCCTRL 0x62
+#define RT946X_REG_CHGIRQ1CTRL 0x63
+#define RT946X_REG_CHGIRQ2CTRL 0x64
+#define RT946X_REG_CHGIRQ3CTRL 0x65
 
 #ifdef CONFIG_CHARGER_RT9467
-#define RT946X_REG_DPDMIRQCTRL		0x66
+#define RT946X_REG_DPDMIRQCTRL 0x66
 #endif
 
 #elif defined(CONFIG_CHARGER_MT6370)
 /* Registers for mt6370 */
-#define RT946X_REG_DEVICEID		0x00
-#define RT946X_REG_CORECTRL1		0x01
-#define RT946X_REG_CORECTRL2		0x02
-#define RT946X_REG_CORECTRL_RST		RT946X_REG_CORECTRL2
-#define MT6370_REG_RSTPASCODE1		0x03
-#define MT6370_REG_RSTPASCODE2		0x04
-#define MT6370_REG_HIDDENPASCODE1	0x07
-#define MT6370_REG_HIDDENPASCODE2	0x08
-#define MT6370_REG_HIDDENPASCODE3	0x09
-#define MT6370_REG_HIDDENPASCODE4	0x0A
-#define MT6370_REG_IRQIND		0x0B
-#define MT6370_REG_IRQMASK		0x0C
-#define MT6370_REG_OSCCTRL		0x10
-#define RT946X_REG_CHGCTRL1		0x11
-#define RT946X_REG_CHGCTRL2		0x12
-#define RT946X_REG_CHGCTRL3		0x13
-#define RT946X_REG_CHGCTRL4		0x14
-#define RT946X_REG_CHGCTRL5		0x15
-#define RT946X_REG_CHGCTRL6		0x16
-#define RT946X_REG_CHGCTRL7		0x17
-#define RT946X_REG_CHGCTRL8		0x18
-#define RT946X_REG_CHGCTRL9		0x19
-#define RT946X_REG_CHGCTRL10		0x1A
-#define RT946X_REG_CHGCTRL11		0x1B
-#define RT946X_REG_CHGCTRL12		0x1C
-#define RT946X_REG_CHGCTRL13		0x1D
-#define RT946X_REG_CHGCTRL14		0x1E
-#define RT946X_REG_CHGCTRL15		0x1F
-#define RT946X_REG_CHGCTRL16		0x20
-#define RT946X_REG_CHGADC		0x21
-#define MT6370_REG_DEVICETYPE		0x22
-#define RT946X_REG_DPDM1		MT6370_REG_DEVICETYPE
-#define MT6370_REG_USBSTATUS1		0x27
-#define MT6370_REG_QCSTATUS2		0x29
-#define RT946X_REG_CHGCTRL17		0X2B
-#define RT946X_REG_CHGCTRL18		0X2C
-#define RT946X_REG_CHGHIDDENCTRL7	0x36
-#define MT6370_REG_CHGHIDDENCTRL15	0x3E
-#define RT946X_REG_CHGSTAT		0X4A
-#define RT946X_REG_CHGNTC		0X4B
-#define RT946X_REG_ADCDATAH		0X4C
-#define RT946X_REG_ADCDATAL		0X4D
+#define RT946X_REG_DEVICEID 0x00
+#define RT946X_REG_CORECTRL1 0x01
+#define RT946X_REG_CORECTRL2 0x02
+#define RT946X_REG_CORECTRL_RST RT946X_REG_CORECTRL2
+#define MT6370_REG_RSTPASCODE1 0x03
+#define MT6370_REG_RSTPASCODE2 0x04
+#define MT6370_REG_HIDDENPASCODE1 0x07
+#define MT6370_REG_HIDDENPASCODE2 0x08
+#define MT6370_REG_HIDDENPASCODE3 0x09
+#define MT6370_REG_HIDDENPASCODE4 0x0A
+#define MT6370_REG_IRQIND 0x0B
+#define MT6370_REG_IRQMASK 0x0C
+#define MT6370_REG_OSCCTRL 0x10
+#define RT946X_REG_CHGCTRL1 0x11
+#define RT946X_REG_CHGCTRL2 0x12
+#define RT946X_REG_CHGCTRL3 0x13
+#define RT946X_REG_CHGCTRL4 0x14
+#define RT946X_REG_CHGCTRL5 0x15
+#define RT946X_REG_CHGCTRL6 0x16
+#define RT946X_REG_CHGCTRL7 0x17
+#define RT946X_REG_CHGCTRL8 0x18
+#define RT946X_REG_CHGCTRL9 0x19
+#define RT946X_REG_CHGCTRL10 0x1A
+#define RT946X_REG_CHGCTRL11 0x1B
+#define RT946X_REG_CHGCTRL12 0x1C
+#define RT946X_REG_CHGCTRL13 0x1D
+#define RT946X_REG_CHGCTRL14 0x1E
+#define RT946X_REG_CHGCTRL15 0x1F
+#define RT946X_REG_CHGCTRL16 0x20
+#define RT946X_REG_CHGADC 0x21
+#define MT6370_REG_DEVICETYPE 0x22
+#define RT946X_REG_DPDM1 MT6370_REG_DEVICETYPE
+#define MT6370_REG_USBSTATUS1 0x27
+#define MT6370_REG_QCSTATUS2 0x29
+#define RT946X_REG_CHGCTRL17 0X2B
+#define RT946X_REG_CHGCTRL18 0X2C
+#define RT946X_REG_CHGHIDDENCTRL7 0x36
+#define MT6370_REG_CHGHIDDENCTRL15 0x3E
+#define RT946X_REG_CHGSTAT 0X4A
+#define RT946X_REG_CHGNTC 0X4B
+#define RT946X_REG_ADCDATAH 0X4C
+#define RT946X_REG_ADCDATAL 0X4D
 /* FLED */
-#define MT6370_REG_FLEDEN		0x7E
+#define MT6370_REG_FLEDEN 0x7E
 /* LDO */
-#define MT6370_REG_LDOCFG		0X80
-#define MT6370_REG_LDOVOUT		0X81
+#define MT6370_REG_LDOCFG 0X80
+#define MT6370_REG_LDOVOUT 0X81
 /* RGB led */
-#define MT6370_REG_RGBDIM_BASE		0x81
-#define MT6370_REG_RGB1DIM		0x82
-#define MT6370_REG_RGB2DIM		0x83
-#define MT6370_REG_RGB3DIM		0x84
-#define MT6370_REG_RGBEN		0x85
-#define MT6370_REG_RGBISNK_BASE		0x85
-#define MT6370_REG_RGB1ISNK		0x86
-#define MT6370_REG_RGB2ISNK		0x87
-#define MT6370_REG_RGB3ISNK		0x88
-#define MT6370_REG_RGBCHRINDDIM		0x92
-#define MT6370_REG_RGBCHRINDCTRL	0x93
+#define MT6370_REG_RGBDIM_BASE 0x81
+#define MT6370_REG_RGB1DIM 0x82
+#define MT6370_REG_RGB2DIM 0x83
+#define MT6370_REG_RGB3DIM 0x84
+#define MT6370_REG_RGBEN 0x85
+#define MT6370_REG_RGBISNK_BASE 0x85
+#define MT6370_REG_RGB1ISNK 0x86
+#define MT6370_REG_RGB2ISNK 0x87
+#define MT6370_REG_RGB3ISNK 0x88
+#define MT6370_REG_RGBCHRINDDIM 0x92
+#define MT6370_REG_RGBCHRINDCTRL 0x93
 
 /* backlight */
-#define MT6370_BACKLIGHT_BLEN		0xA0
-#define MT6370_BACKLIGHT_BLPWM		0xA2
-#define MT6370_BACKLIGHT_BLDIM2		0xA4
-#define MT6370_BACKLIGHT_BLDIM		0xA5
+#define MT6370_BACKLIGHT_BLEN 0xA0
+#define MT6370_BACKLIGHT_BLPWM 0xA2
+#define MT6370_BACKLIGHT_BLDIM2 0xA4
+#define MT6370_BACKLIGHT_BLDIM 0xA5
 
 /* Display bias */
-#define MT6370_REG_DBCTRL1		0XB0
-#define MT6370_REG_DBCTRL2		0XB1
-#define MT6370_REG_DBVBST		0XB2
-#define MT6370_REG_DBVPOS		0XB3
-#define MT6370_REG_DBVNEG		0XB4
-#define MT6370_REG_CHGIRQ1		0xC0
-#define RT946X_REG_DPDMIRQ		0xC6
+#define MT6370_REG_DBCTRL1 0XB0
+#define MT6370_REG_DBCTRL2 0XB1
+#define MT6370_REG_DBVBST 0XB2
+#define MT6370_REG_DBVPOS 0XB3
+#define MT6370_REG_DBVNEG 0XB4
+#define MT6370_REG_CHGIRQ1 0xC0
+#define RT946X_REG_DPDMIRQ 0xC6
 
 /* status event */
-#define MT6370_REG_CHGSTAT1		0xD0
-#define RT946X_REG_CHGSTATC		MT6370_REG_CHGSTAT1
-#define MT6370_REG_CHGSTAT2		0xD1
-#define RT946X_REG_CHGFAULT		MT6370_REG_CHGSTAT2
-#define MT6370_REG_CHGSTAT3		0xD2
-#define MT6370_REG_CHGSTAT4		0xD3
-#define MT6370_REG_CHGSTAT5		0xD4
-#define MT6370_REG_CHGSTAT6		0xD5
-#define MT6370_REG_DPDMSTAT		0xD6
-#define MT6370_REG_DICHGSTAT		0xD7
-#define MT6370_REG_OVPCTRLSTAT		0xD8
-#define MT6370_REG_FLEDSTAT1		0xD9
-#define MT6370_REG_FLEDSTAT2		0xDA
-#define MT6370_REG_BASESTAT		0xDB
-#define MT6370_REG_LDOSTAT		0xDC
-#define MT6370_REG_RGBSTAT		0xDD
-#define MT6370_REG_BLSTAT		0xDE
-#define MT6370_REG_DBSTAT		0xDF
+#define MT6370_REG_CHGSTAT1 0xD0
+#define RT946X_REG_CHGSTATC MT6370_REG_CHGSTAT1
+#define MT6370_REG_CHGSTAT2 0xD1
+#define RT946X_REG_CHGFAULT MT6370_REG_CHGSTAT2
+#define MT6370_REG_CHGSTAT3 0xD2
+#define MT6370_REG_CHGSTAT4 0xD3
+#define MT6370_REG_CHGSTAT5 0xD4
+#define MT6370_REG_CHGSTAT6 0xD5
+#define MT6370_REG_DPDMSTAT 0xD6
+#define MT6370_REG_DICHGSTAT 0xD7
+#define MT6370_REG_OVPCTRLSTAT 0xD8
+#define MT6370_REG_FLEDSTAT1 0xD9
+#define MT6370_REG_FLEDSTAT2 0xDA
+#define MT6370_REG_BASESTAT 0xDB
+#define MT6370_REG_LDOSTAT 0xDC
+#define MT6370_REG_RGBSTAT 0xDD
+#define MT6370_REG_BLSTAT 0xDE
+#define MT6370_REG_DBSTAT 0xDF
 /* irq mask */
-#define MT6370_REG_CHGMASK1		0xE0
-#define RT946X_REG_CHGSTATCCTRL		MT6370_REG_CHGMASK1
-#define MT6370_REG_CHGMASK2		0xE1
-#define MT6370_REG_CHGMASK3		0xE2
-#define MT6370_REG_CHGMASK4		0xE3
-#define MT6370_REG_CHGMASK5		0xE4
-#define MT6370_REG_CHGMASK6		0xE5
-#define MT6370_REG_DPDMMASK1		0xE6
-#define MT6370_REG_DICHGMASK		0xE7
-#define MT6370_REG_OVPCTRLMASK		0xE8
-#define MT6370_REG_FLEDMASK1		0xE9
-#define MT6370_REG_FLEDMASK2		0xEA
-#define MT6370_REG_BASEMASK		0xEB
-#define MT6370_REG_LDOMASK		0xEC
-#define MT6370_REG_RGBMASK		0xED
-#define MT6370_REG_BLMASK		0xEE
-#define MT6370_REG_DBMASK		0xEF
-#define MT6370_REG_TM_PAS_CODE1		0xF0
-#define MT6370_REG_BANK			0xFF
+#define MT6370_REG_CHGMASK1 0xE0
+#define RT946X_REG_CHGSTATCCTRL MT6370_REG_CHGMASK1
+#define MT6370_REG_CHGMASK2 0xE1
+#define MT6370_REG_CHGMASK3 0xE2
+#define MT6370_REG_CHGMASK4 0xE3
+#define MT6370_REG_CHGMASK5 0xE4
+#define MT6370_REG_CHGMASK6 0xE5
+#define MT6370_REG_DPDMMASK1 0xE6
+#define MT6370_REG_DICHGMASK 0xE7
+#define MT6370_REG_OVPCTRLMASK 0xE8
+#define MT6370_REG_FLEDMASK1 0xE9
+#define MT6370_REG_FLEDMASK2 0xEA
+#define MT6370_REG_BASEMASK 0xEB
+#define MT6370_REG_LDOMASK 0xEC
+#define MT6370_REG_RGBMASK 0xED
+#define MT6370_REG_BLMASK 0xEE
+#define MT6370_REG_DBMASK 0xEF
+#define MT6370_REG_TM_PAS_CODE1 0xF0
+#define MT6370_REG_BANK 0xFF
 /* TM REGISTER */
-#define MT6370_TM_REG_BL3		0x34
-#define MT6370_TM_REG_DSV1		0x37
+#define MT6370_TM_REG_BL3 0x34
+#define MT6370_TM_REG_DSV1 0x37
 #else
 #error "No suitable charger option defined"
 #endif
 
 /* EOC current */
-#define RT946X_IEOC_MIN		100
-#define RT946X_IEOC_MAX		850
-#define RT946X_IEOC_STEP	50
+#define RT946X_IEOC_MIN 100
+#define RT946X_IEOC_MAX 850
+#define RT946X_IEOC_STEP 50
 
 /* Minimum Input Voltage Regulator */
-#define RT946X_MIVR_MIN		3900
-#define RT946X_MIVR_MAX		13400
-#define RT946X_MIVR_STEP	100
+#define RT946X_MIVR_MIN 3900
+#define RT946X_MIVR_MAX 13400
+#define RT946X_MIVR_STEP 100
 
 /* Boost voltage */
-#define RT946X_BOOST_VOLTAGE_MIN	4425
-#define RT946X_BOOST_VOLTAGE_MAX	5825
-#define RT946X_BOOST_VOLTAGE_STEP	25
+#define RT946X_BOOST_VOLTAGE_MIN 4425
+#define RT946X_BOOST_VOLTAGE_MAX 5825
+#define RT946X_BOOST_VOLTAGE_STEP 25
 
 /* IR compensation resistor */
-#define RT946X_IRCMP_RES_MIN	0
-#define RT946X_IRCMP_RES_MAX	175
-#define RT946X_IRCMP_RES_STEP	25
+#define RT946X_IRCMP_RES_MIN 0
+#define RT946X_IRCMP_RES_MAX 175
+#define RT946X_IRCMP_RES_STEP 25
 
 /* IR compensation voltage clamp */
-#define RT946X_IRCMP_VCLAMP_MIN		0
-#define RT946X_IRCMP_VCLAMP_MAX		224
-#define RT946X_IRCMP_VCLAMP_STEP	32
+#define RT946X_IRCMP_VCLAMP_MIN 0
+#define RT946X_IRCMP_VCLAMP_MAX 224
+#define RT946X_IRCMP_VCLAMP_STEP 32
 
 /* Pre-charge mode threshold voltage */
-#define RT946X_VPREC_MIN		2000
-#define RT946X_VPREC_MAX		3500
-#define RT946X_VPREC_STEP		100
+#define RT946X_VPREC_MIN 2000
+#define RT946X_VPREC_MAX 3500
+#define RT946X_VPREC_STEP 100
 
 /* Pre-charge current */
-#define RT946X_IPREC_MIN		100
-#define RT946X_IPREC_MAX		850
-#define RT946X_IPREC_STEP		50
+#define RT946X_IPREC_MIN 100
+#define RT946X_IPREC_MAX 850
+#define RT946X_IPREC_STEP 50
 
 /* AICLVTH */
-#define RT946X_AICLVTH_MIN	4100
-#define RT946X_AICLVTH_MAX	4800
-#define RT946X_AICLVTH_STEP	100
+#define RT946X_AICLVTH_MIN 4100
+#define RT946X_AICLVTH_MAX 4800
+#define RT946X_AICLVTH_STEP 100
 
 /* NTC */
-#define RT946X_BATTEMP_NORMAL	0x00
-#define RT946X_BATTEMP_WARM	0x02
-#define RT946X_BATTEMP_COOL	0x03
-#define RT946X_BATTEMP_COLD	0x05
-#define RT946X_BATTEMP_HOT	0x06
+#define RT946X_BATTEMP_NORMAL 0x00
+#define RT946X_BATTEMP_WARM 0x02
+#define RT946X_BATTEMP_COOL 0x03
+#define RT946X_BATTEMP_COLD 0x05
+#define RT946X_BATTEMP_HOT 0x06
 
 /* LDO voltage */
-#define MT6370_LDO_MIN		1600
-#define MT6370_LDO_MAX		4000
-#define MT6370_LDO_STEP		200
+#define MT6370_LDO_MIN 1600
+#define MT6370_LDO_MAX 4000
+#define MT6370_LDO_STEP 200
 
 /* ========== CORECTRL0 0x00 ============ */
-#define RT946X_SHIFT_RST	7
-#define RT946X_SHIFT_CHG_RST	6
-#define RT946X_SHIFT_FLED_RST	5
-#define RT946X_SHIFT_LDO_RST	4
-#define RT946X_SHIFT_RGB_RST	3
-#define RT946X_SHIFT_BL_RST	2
-#define RT946X_SHIFT_DB_RST	1
-#define RT946X_SHIFT_REG_RST	0
-
-#define RT946X_MASK_RST		BIT(RT946X_SHIFT_RST)
-#define RT946X_MASK_CHG_RST	BIT(RT946X_SHIFT_CHG_RST)
-#define RT946X_MASK_FLED_RST	BIT(RT946X_SHIFT_FLED_RST)
-#define RT946X_MASK_LDO_RST	BIT(RT946X_SHIFT_LDO_RST)
-#define RT946X_MASK_RGB_RST	BIT(RT946X_SHIFT_RGB_RST)
-#define RT946X_MASK_BL_RST	BIT(RT946X_SHIFT_BL_RST)
-#define RT946X_MASK_DB_RST	BIT(RT946X_SHIFT_DB_RST)
-#define RT946X_MASK_REG_RST	BIT(RT946X_SHIFT_REG_RST)
-#define RT946X_MASK_SOFT_RST                                                   \
-	(RT946X_MASK_CHG_RST | RT946X_MASK_FLED_RST | RT946X_MASK_LDO_RST |    \
-	 RT946X_MASK_RGB_RST | RT946X_MASK_BL_RST | RT946X_MASK_DB_RST |       \
+#define RT946X_SHIFT_RST 7
+#define RT946X_SHIFT_CHG_RST 6
+#define RT946X_SHIFT_FLED_RST 5
+#define RT946X_SHIFT_LDO_RST 4
+#define RT946X_SHIFT_RGB_RST 3
+#define RT946X_SHIFT_BL_RST 2
+#define RT946X_SHIFT_DB_RST 1
+#define RT946X_SHIFT_REG_RST 0
+
+#define RT946X_MASK_RST BIT(RT946X_SHIFT_RST)
+#define RT946X_MASK_CHG_RST BIT(RT946X_SHIFT_CHG_RST)
+#define RT946X_MASK_FLED_RST BIT(RT946X_SHIFT_FLED_RST)
+#define RT946X_MASK_LDO_RST BIT(RT946X_SHIFT_LDO_RST)
+#define RT946X_MASK_RGB_RST BIT(RT946X_SHIFT_RGB_RST)
+#define RT946X_MASK_BL_RST BIT(RT946X_SHIFT_BL_RST)
+#define RT946X_MASK_DB_RST BIT(RT946X_SHIFT_DB_RST)
+#define RT946X_MASK_REG_RST BIT(RT946X_SHIFT_REG_RST)
+#define RT946X_MASK_SOFT_RST                                                \
+	(RT946X_MASK_CHG_RST | RT946X_MASK_FLED_RST | RT946X_MASK_LDO_RST | \
+	 RT946X_MASK_RGB_RST | RT946X_MASK_BL_RST | RT946X_MASK_DB_RST |    \
 	 RT946X_MASK_REG_RST)
 
 /* ========== CHGCTRL1 0x01 ============ */
-#define RT946X_SHIFT_OPA_MODE   0
-#define RT946X_SHIFT_HZ_EN      2
-#define RT946X_SHIFT_STAT_EN	4
+#define RT946X_SHIFT_OPA_MODE 0
+#define RT946X_SHIFT_HZ_EN 2
+#define RT946X_SHIFT_STAT_EN 4
 
-#define RT946X_MASK_OPA_MODE	BIT(RT946X_SHIFT_OPA_MODE)
-#define RT946X_MASK_HZ_EN	BIT(RT946X_SHIFT_HZ_EN)
-#define RT946X_MASK_STAT_EN	BIT(RT946X_SHIFT_STAT_EN)
+#define RT946X_MASK_OPA_MODE BIT(RT946X_SHIFT_OPA_MODE)
+#define RT946X_MASK_HZ_EN BIT(RT946X_SHIFT_HZ_EN)
+#define RT946X_MASK_STAT_EN BIT(RT946X_SHIFT_STAT_EN)
 
 /* ========== CHGCTRL2 0x02 ============ */
-#define RT946X_SHIFT_SHIP_MODE	7
-#define RT946X_SHIFT_TE		4
-#define RT946X_SHIFT_ILMTSEL	2
-#define RT946X_SHIFT_CFO_EN	1
-#define RT946X_SHIFT_CHG_EN	0
-
-#define RT946X_MASK_SHIP_MODE	BIT(RT946X_SHIFT_SHIP_MODE)
-#define RT946X_MASK_TE		BIT(RT946X_SHIFT_TE)
-#define RT946X_MASK_ILMTSEL	(0x3 << RT946X_SHIFT_ILMTSEL)
-#define RT946X_MASK_CFO_EN	BIT(RT946X_SHIFT_CFO_EN)
-#define RT946X_MASK_CHG_EN	BIT(RT946X_SHIFT_CHG_EN)
+#define RT946X_SHIFT_SHIP_MODE 7
+#define RT946X_SHIFT_BATDET_DIS_DLY 6
+#define RT946X_SHIFT_TE 4
+#define RT946X_SHIFT_ILMTSEL 2
+#define RT946X_SHIFT_CFO_EN 1
+#define RT946X_SHIFT_CHG_EN 0
+
+#define RT946X_MASK_SHIP_MODE BIT(RT946X_SHIFT_SHIP_MODE)
+#define RT946X_MASK_TE BIT(RT946X_SHIFT_TE)
+#define RT946X_MASK_ILMTSEL (0x3 << RT946X_SHIFT_ILMTSEL)
+#define RT946X_MASK_CFO_EN BIT(RT946X_SHIFT_CFO_EN)
+#define RT946X_MASK_CHG_EN BIT(RT946X_SHIFT_CHG_EN)
 
 /* ========== RSTPASCODE1 0x03 (mt6370) ============ */
-#define MT6370_MASK_RSTPASCODE1	0xA9
+#define MT6370_MASK_RSTPASCODE1 0xA9
 
 /* ========== CHGCTRL3 0x03 ============ */
-#define RT946X_SHIFT_AICR	2
-#define RT946X_SHIFT_ILIMEN	0
+#define RT946X_SHIFT_AICR 2
+#define RT946X_SHIFT_ILIMEN 0
 
-#define RT946X_MASK_AICR	(0x3F << RT946X_SHIFT_AICR)
-#define RT946X_MASK_ILIMEN	BIT(RT946X_SHIFT_ILIMEN)
+#define RT946X_MASK_AICR (0x3F << RT946X_SHIFT_AICR)
+#define RT946X_MASK_ILIMEN BIT(RT946X_SHIFT_ILIMEN)
 
 /*
  * The accuracy of AICR is 7%.  So if AICR = 2150,
  * then Max=2150, Typ=2000, Min=1860. And plus 25 since the AICR
  * is 50ma a step.
  */
-#define RT946X_AICR_TYP2MAX(x)	((x) * 107 / 100 + 25)
+#define RT946X_AICR_TYP2MAX(x) ((x)*107 / 100 + 25)
 
 /* ========== RSTPASCODE2 0x04 (mt6370) ============ */
-#define MT6370_MASK_RSTPASCODE2	0x96
+#define MT6370_MASK_RSTPASCODE2 0x96
 
 /* ========== CHGCTRL4 0x04 ============ */
-#define RT946X_SHIFT_CV	1
+#define RT946X_SHIFT_CV 1
 
-#define RT946X_MASK_CV	0xFE
+#define RT946X_MASK_CV 0xFE
 
 /* ========== CHGCTRL5 0x05 ============ */
-#define RT946X_SHIFT_BOOST_VOLTAGE	2
+#define RT946X_SHIFT_BOOST_VOLTAGE 2
 
-#define RT946X_MASK_BOOST_VOLTAGE	0xFC
+#define RT946X_MASK_BOOST_VOLTAGE 0xFC
 
 /* ========== CHGCTRL6 0x06 ============ */
-#define RT946X_SHIFT_MIVR	1
+#define RT946X_SHIFT_MIVR 1
 
-#define RT946X_MASK_MIVR	(0x7F << RT946X_SHIFT_MIVR)
+#define RT946X_MASK_MIVR (0x7F << RT946X_SHIFT_MIVR)
 
 /* ========== CHGCTRL7 0x07 ============ */
-#define RT946X_SHIFT_ICHG	2
+#define RT946X_SHIFT_ICHG 2
 
-#define RT946X_MASK_ICHG	(0x3F << RT946X_SHIFT_ICHG)
+#define RT946X_MASK_ICHG (0x3F << RT946X_SHIFT_ICHG)
 
 /* ========== CHGCTRL8 0x08 ============ */
-#define RT946X_SHIFT_VPREC	4
-#define RT946X_SHIFT_IPREC	0
+#define RT946X_SHIFT_VPREC 4
+#define RT946X_SHIFT_IPREC 0
 
-#define RT946X_MASK_VPREC	(0xF << RT946X_SHIFT_VPREC)
-#define RT946X_MASK_IPREC	(0xF << RT946X_SHIFT_IPREC)
+#define RT946X_MASK_VPREC (0xF << RT946X_SHIFT_VPREC)
+#define RT946X_MASK_IPREC (0xF << RT946X_SHIFT_IPREC)
 
 /* ========== CHGCTRL9 0x09 ============ */
-#define RT946X_SHIFT_EOC	3
-#define RT946X_SHIFT_IEOC	4
+#define RT946X_SHIFT_EOC 3
+#define RT946X_SHIFT_IEOC 4
 
-#define RT946X_MASK_EOC		BIT(RT946X_SHIFT_EOC)
-#define RT946X_MASK_IEOC	(0xF << RT946X_SHIFT_IEOC)
+#define RT946X_MASK_EOC BIT(RT946X_SHIFT_EOC)
+#define RT946X_MASK_IEOC (0xF << RT946X_SHIFT_IEOC)
 
 /* ========== CHGCTRL10 0x0A ============ */
-#define RT946X_SHIFT_BOOST_CURRENT	0
+#define RT946X_SHIFT_BOOST_CURRENT 0
 
-#define RT946X_MASK_BOOST_CURRENT	0x07
+#define RT946X_MASK_BOOST_CURRENT 0x07
 
 /* ========== CHGCTRL12 0x0C ============ */
-#define RT946X_SHIFT_TMR_EN	1
-#define MT6370_IRQ_MASK_ALL	0xFE
+#define RT946X_SHIFT_TMR_EN 1
+#define MT6370_IRQ_MASK_ALL 0xFE
 
-#define RT946X_MASK_TMR_EN	BIT(RT946X_SHIFT_TMR_EN)
+#define RT946X_MASK_TMR_EN BIT(RT946X_SHIFT_TMR_EN)
 
 /* ========== CHGCTRL13 0x0D ============ */
-#define RT946X_SHIFT_WDT_EN	7
+#define RT946X_SHIFT_WDT_EN 7
 
-#define RT946X_MASK_WDT_EN	BIT(RT946X_SHIFT_WDT_EN)
+#define RT946X_MASK_WDT_EN BIT(RT946X_SHIFT_WDT_EN)
 
 /* ========== CHGCTRL14 0x0E ============ */
-#define RT946X_SHIFT_AICLMEAS	7
-#define RT946X_SHIFT_AICLVTH	0
+#define RT946X_SHIFT_AICLMEAS 7
+#define RT946X_SHIFT_AICLVTH 0
 
-#define RT946X_MASK_AICLMEAS	BIT(RT946X_SHIFT_AICLMEAS)
-#define RT946X_MASK_AICLVTH	0x07
+#define RT946X_MASK_AICLMEAS BIT(RT946X_SHIFT_AICLMEAS)
+#define RT946X_MASK_AICLVTH 0x07
 
 /* ========== CHGCTRL16 0x10 ============ */
-#define RT946X_SHIFT_JEITA_EN	4
+#define RT946X_SHIFT_JEITA_EN 4
 
-#define RT946X_MASK_JEITA_EN	BIT(RT946X_SHIFT_JEITA_EN)
+#define RT946X_MASK_JEITA_EN BIT(RT946X_SHIFT_JEITA_EN)
 
 /* ========== CHGADC 0x11 ============ */
-#define RT946X_SHIFT_ADC_IN_SEL	4
-#define RT946X_SHIFT_ADC_START	0
+#define RT946X_SHIFT_ADC_IN_SEL 4
+#define RT946X_SHIFT_ADC_START 0
 
-#define RT946X_MASK_ADC_IN_SEL	(0xF << RT946X_SHIFT_ADC_IN_SEL)
-#define RT946X_MASK_ADC_START	BIT(RT946X_SHIFT_ADC_START)
+#define RT946X_MASK_ADC_IN_SEL (0xF << RT946X_SHIFT_ADC_IN_SEL)
+#define RT946X_MASK_ADC_START BIT(RT946X_SHIFT_ADC_START)
 
 /* ========== CHGDPDM1 0x12 (rt946x) DEVICETYPE 0x22 (mt6370) ============ */
-#define RT946X_SHIFT_USBCHGEN	7
-#define RT946X_SHIFT_DCDTIMEOUT	6
-#define RT946X_SHIFT_DCP	2
-#define RT946X_SHIFT_CDP	1
-#define RT946X_SHIFT_SDP	0
-
-#define RT946X_MASK_USBCHGEN	BIT(RT946X_SHIFT_USBCHGEN)
-#define RT946X_MASK_DCDTIMEOUT	BIT(RT946X_SHIFT_DCDTIMEOUT)
-#define RT946X_MASK_DCP		BIT(RT946X_SHIFT_DCP)
-#define RT946X_MASK_CDP		BIT(RT946X_SHIFT_CDP)
-#define RT946X_MASK_SDP		BIT(RT946X_SHIFT_SDP)
-
-#define RT946X_MASK_BC12_TYPE	(RT946X_MASK_DCP | \
-				 RT946X_MASK_CDP | \
-				 RT946X_MASK_SDP)
+#define RT946X_SHIFT_USBCHGEN 7
+#define RT946X_SHIFT_DCDTIMEOUT 6
+#define RT946X_SHIFT_DCP 2
+#define RT946X_SHIFT_CDP 1
+#define RT946X_SHIFT_SDP 0
+
+#define RT946X_MASK_USBCHGEN BIT(RT946X_SHIFT_USBCHGEN)
+#define RT946X_MASK_DCDTIMEOUT BIT(RT946X_SHIFT_DCDTIMEOUT)
+#define RT946X_MASK_DCP BIT(RT946X_SHIFT_DCP)
+#define RT946X_MASK_CDP BIT(RT946X_SHIFT_CDP)
+#define RT946X_MASK_SDP BIT(RT946X_SHIFT_SDP)
+
+#define RT946X_MASK_BC12_TYPE \
+	(RT946X_MASK_DCP | RT946X_MASK_CDP | RT946X_MASK_SDP)
 
 /* ========== USBSTATUS1 0x27 (mt6370) ============ */
-#define MT6370_SHIFT_DCD_TIMEOUT 	2
-#define MT6370_SHIFT_USB_STATUS		4
+#define MT6370_SHIFT_DCD_TIMEOUT 2
+#define MT6370_SHIFT_USB_STATUS 4
 
-#define MT6370_MASK_USB_STATUS	0x70
+#define MT6370_MASK_USB_STATUS 0x70
 
-#define MT6370_CHG_TYPE_NOVBUS			0
-#define MT6370_CHG_TYPE_BUSY			1
-#define MT6370_CHG_TYPE_SDP			2
-#define MT6370_CHG_TYPE_SDPNSTD			3
-#define MT6370_CHG_TYPE_DCP			4
-#define MT6370_CHG_TYPE_CDP			5
-#define MT6370_CHG_TYPE_SAMSUNG_CHARGER		6
-#define MT6370_CHG_TYPE_APPLE_0_5A_CHARGER	7
-#define MT6370_CHG_TYPE_APPLE_1_0A_CHARGER	8
-#define MT6370_CHG_TYPE_APPLE_2_1A_CHARGER	9
-#define MT6370_CHG_TYPE_APPLE_2_4A_CHARGER	10
+#define MT6370_CHG_TYPE_NOVBUS 0
+#define MT6370_CHG_TYPE_BUSY 1
+#define MT6370_CHG_TYPE_SDP 2
+#define MT6370_CHG_TYPE_SDPNSTD 3
+#define MT6370_CHG_TYPE_DCP 4
+#define MT6370_CHG_TYPE_CDP 5
+#define MT6370_CHG_TYPE_SAMSUNG_CHARGER 6
+#define MT6370_CHG_TYPE_APPLE_0_5A_CHARGER 7
+#define MT6370_CHG_TYPE_APPLE_1_0A_CHARGER 8
+#define MT6370_CHG_TYPE_APPLE_2_1A_CHARGER 9
+#define MT6370_CHG_TYPE_APPLE_2_4A_CHARGER 10
 
-#define MT6370_MASK_DCD_TIMEOUT		BIT(MT6370_SHIFT_DCD_TIMEOUT)
+#define MT6370_MASK_DCD_TIMEOUT BIT(MT6370_SHIFT_DCD_TIMEOUT)
 
 /* ========== QCSTATUS2 0x29 (mt6370) ============ */
-#define MT6370_SHIFT_APP_OUT		5
-#define MT6370_SHIFT_SS_OUT		4
-#define MT6370_SHIFT_APP_REF		3
-#define MT6370_SHIFT_APP_DPDM_IN	2
-#define MT6370_SHIFT_APP_SS_PL		1
-#define MT6370_SHIFT_APP_SS_EN		0
-
-#define MT6370_MASK_APP_OUT	BIT(MT6370_SHIFT_APP_OUT)
-#define MT6370_MASK_SS_OUT	BIT(MT6370_SHIFT_SS_OUT)
-#define MT6370_MASK_APP_REF	BIT(MT6370_SHIFT_APP_REF)
-#define MT6370_MASK_APP_DPDM_IN	BIT(MT6370_SHIFT_APP_DPDM_IN)
-#define MT6370_MASK_APP_SS_PL	BIT(MT6370_SHIFT_APP_SS_PL)
-#define MT6370_MASK_APP_SS_EN	BIT(MT6370_SHIFT_APP_SS_EN)
-
-#define MT6360_MASK_CHECK_DPDM	(MT6370_MASK_APP_SS_EN | \
-				MT6370_MASK_APP_SS_PL | \
-				MT6370_MASK_APP_DPDM_IN | \
-				MT6370_MASK_APP_REF)
+#define MT6370_SHIFT_APP_OUT 5
+#define MT6370_SHIFT_SS_OUT 4
+#define MT6370_SHIFT_APP_REF 3
+#define MT6370_SHIFT_APP_DPDM_IN 2
+#define MT6370_SHIFT_APP_SS_PL 1
+#define MT6370_SHIFT_APP_SS_EN 0
+
+#define MT6370_MASK_APP_OUT BIT(MT6370_SHIFT_APP_OUT)
+#define MT6370_MASK_SS_OUT BIT(MT6370_SHIFT_SS_OUT)
+#define MT6370_MASK_APP_REF BIT(MT6370_SHIFT_APP_REF)
+#define MT6370_MASK_APP_DPDM_IN BIT(MT6370_SHIFT_APP_DPDM_IN)
+#define MT6370_MASK_APP_SS_PL BIT(MT6370_SHIFT_APP_SS_PL)
+#define MT6370_MASK_APP_SS_EN BIT(MT6370_SHIFT_APP_SS_EN)
+
+#define MT6360_MASK_CHECK_DPDM                           \
+	(MT6370_MASK_APP_SS_EN | MT6370_MASK_APP_SS_PL | \
+	 MT6370_MASK_APP_DPDM_IN | MT6370_MASK_APP_REF)
 
 /* ========= CHGHIDDENCTRL7 0x36 (mt6370) ======== */
-#define RT946X_ENABLE_VSYS_PROTECT		0x40
+#define RT946X_ENABLE_VSYS_PROTECT 0x40
 
-#define RT946X_SHIFT_HIDDENCTRL7_VSYS_PROTECT	5
+#define RT946X_SHIFT_HIDDENCTRL7_VSYS_PROTECT 5
 #define RT946X_MASK_HIDDENCTRL7_VSYS_PROTECT \
 	(0x3 << RT946X_SHIFT_HIDDENCTRL7_VSYS_PROTECT)
 
 /* ========== CHGCTRL18 0x1A ============ */
-#define RT946X_SHIFT_IRCMP_RES		3
-#define RT946X_SHIFT_IRCMP_VCLAMP	0
+#define RT946X_SHIFT_IRCMP_RES 3
+#define RT946X_SHIFT_IRCMP_VCLAMP 0
 
-#define RT946X_MASK_IRCMP_RES		(0x7 << RT946X_SHIFT_IRCMP_RES)
-#define RT946X_MASK_IRCMP_VCLAMP	(0x7 << RT946X_SHIFT_IRCMP_VCLAMP)
+#define RT946X_MASK_IRCMP_RES (0x7 << RT946X_SHIFT_IRCMP_RES)
+#define RT946X_MASK_IRCMP_VCLAMP (0x7 << RT946X_SHIFT_IRCMP_VCLAMP)
 
 /* ========== HIDDEN CTRL15 0x3E ============ */
-#define MT6370_SHIFT_ADC_TS_AUTO	0
-#define MT6370_MASK_ADC_TS_AUTO		BIT(MT6370_SHIFT_ADC_TS_AUTO)
+#define MT6370_SHIFT_ADC_TS_AUTO 0
+#define MT6370_MASK_ADC_TS_AUTO BIT(MT6370_SHIFT_ADC_TS_AUTO)
 
 /* ========== DEVICE_ID 0x40 ============ */
-#define RT946X_MASK_VENDOR_ID	0xF0
-#define RT946X_MASK_CHIP_REV	0x0F
+#define RT946X_MASK_VENDOR_ID 0xF0
+#define RT946X_MASK_CHIP_REV 0x0F
 
 /* ========== CHGSTAT 0x42 ============ */
-#define RT946X_SHIFT_CHG_STAT	6
-#define RT946X_SHIFT_ADC_STAT	0
+#define RT946X_SHIFT_CHG_STAT 6
+#define RT946X_SHIFT_ADC_STAT 0
 
-#define RT946X_MASK_CHG_STAT	(0x3 << RT946X_SHIFT_CHG_STAT)
-#define RT946X_MASK_ADC_STAT	BIT(RT946X_SHIFT_ADC_STAT)
+#define RT946X_MASK_CHG_STAT (0x3 << RT946X_SHIFT_CHG_STAT)
+#define RT946X_MASK_ADC_STAT BIT(RT946X_SHIFT_ADC_STAT)
 
 /* ========== CHGNTC 0x43 ============ */
-#define RT946X_SHIFT_BATNTC_FAULT	4
+#define RT946X_SHIFT_BATNTC_FAULT 4
 
-#define RT946X_MASK_BATNTC_FAULT	0x70
+#define RT946X_MASK_BATNTC_FAULT 0x70
 
 /* ========== CHGSTATC 0x50 (rt946x) ============ */
-#define RT946X_SHIFT_PWR_RDY    7
+#define RT946X_SHIFT_PWR_RDY 7
 
-#define RT946X_MASK_PWR_RDY     BIT(RT946X_SHIFT_PWR_RDY)
+#define RT946X_MASK_PWR_RDY BIT(RT946X_SHIFT_PWR_RDY)
 
 /* ========== CHGFAULT 0x51 (rt946x) ============ */
 #if defined(CONFIG_CHARGER_RT9466) || defined(CONFIG_CHARGER_RT9467)
-#define RT946X_SHIFT_CHG_VSYSUV	4
-#define RT946X_SHIFT_CHG_VSYSOV	5
-#define RT946X_SHIFT_CHG_VBATOV	6
-#define RT946X_SHIFT_CHG_VBUSOV	7
-
-#define RT946X_MASK_CHG_VSYSUV	BIT(RT946X_SHIFT_CHG_VSYSUV)
-#define RT946X_MASK_CHG_VSYSOV	BIT(RT946X_SHIFT_CHG_VSYSOV)
-#define RT946X_MASK_CHG_VBATOV	BIT(RT946X_SHIFT_CHG_VBATOV)
-#define RT946X_MASK_CHG_VBUSOV	BIT(RT946X_SHIFT_CHG_VBUSOV)
+#define RT946X_SHIFT_CHG_VSYSUV 4
+#define RT946X_SHIFT_CHG_VSYSOV 5
+#define RT946X_SHIFT_CHG_VBATOV 6
+#define RT946X_SHIFT_CHG_VBUSOV 7
+
+#define RT946X_MASK_CHG_VSYSUV BIT(RT946X_SHIFT_CHG_VSYSUV)
+#define RT946X_MASK_CHG_VSYSOV BIT(RT946X_SHIFT_CHG_VSYSOV)
+#define RT946X_MASK_CHG_VBATOV BIT(RT946X_SHIFT_CHG_VBATOV)
+#define RT946X_MASK_CHG_VBUSOV BIT(RT946X_SHIFT_CHG_VBUSOV)
 #endif
 
 /* ========== DPDMIRQ 0x56 ============ */
 #if defined(CONFIG_CHARGER_RT9467) || defined(CONFIG_CHARGER_MT6370)
-#define RT946X_SHIFT_DPDMIRQ_DETACH	1
-#define RT946X_SHIFT_DPDMIRQ_ATTACH	0
+#define RT946X_SHIFT_DPDMIRQ_DETACH 1
+#define RT946X_SHIFT_DPDMIRQ_ATTACH 0
 
-#define RT946X_MASK_DPDMIRQ_DETACH	BIT(RT946X_SHIFT_DPDMIRQ_DETACH)
-#define RT946X_MASK_DPDMIRQ_ATTACH	BIT(RT946X_SHIFT_DPDMIRQ_ATTACH)
+#define RT946X_MASK_DPDMIRQ_DETACH BIT(RT946X_SHIFT_DPDMIRQ_DETACH)
+#define RT946X_MASK_DPDMIRQ_ATTACH BIT(RT946X_SHIFT_DPDMIRQ_ATTACH)
 #endif
 
 /* ========== FLED EN 0x7E (mt6370) ============ */
-#define MT6370_STROBE_EN_MASK		0x04
+#define MT6370_STROBE_EN_MASK 0x04
 
 /* ========== LDOCFG 0x80 (mt6370) ============ */
-#define MT6370_SHIFT_LDOCFG_OMS	6
+#define MT6370_SHIFT_LDOCFG_OMS 6
 
-#define MT6370_MASK_LDOCFG_OMS		BIT(MT6370_SHIFT_LDOCFG_OMS)
+#define MT6370_MASK_LDOCFG_OMS BIT(MT6370_SHIFT_LDOCFG_OMS)
 
 /* ========== LDOVOUT 0x81 (mt6370) ============ */
-#define MT6370_SHIFT_LDOVOUT_EN		7
-#define MT6370_SHIFT_LDOVOUT_VOUT	0
+#define MT6370_SHIFT_LDOVOUT_EN 7
+#define MT6370_SHIFT_LDOVOUT_VOUT 0
 
-#define MT6370_MASK_LDOVOUT_EN		BIT(MT6370_SHIFT_LDOVOUT_EN)
-#define MT6370_MASK_LDOVOUT_VOUT	(0xf << MT6370_SHIFT_LDOVOUT_VOUT)
+#define MT6370_MASK_LDOVOUT_EN BIT(MT6370_SHIFT_LDOVOUT_EN)
+#define MT6370_MASK_LDOVOUT_VOUT (0xf << MT6370_SHIFT_LDOVOUT_VOUT)
 
 /* ========== RGBDIM 0x82/0x83/0x84 (mt6370) ============ */
-#define MT6370_LED_PWM_DIMDUTY_MIN	0x00
-#define MT6370_LED_PWM_DIMDUTY_MAX	0x1f
+#define MT6370_LED_PWM_DIMDUTY_MIN 0x00
+#define MT6370_LED_PWM_DIMDUTY_MAX 0x1f
 
-#define MT6370_SHIFT_RGB_DIMMODE	5
-#define MT6370_SHIFT_RGB_DIMDUTY	0
+#define MT6370_SHIFT_RGB_DIMMODE 5
+#define MT6370_SHIFT_RGB_DIMDUTY 0
 
-#define MT6370_MASK_RGB_DIMMODE		(3 << MT6370_SHIFT_RGB_DIMMODE)
-#define MT6370_MASK_RGB_DIMDUTY		(0x1f << MT6370_SHIFT_RGB_DIMDUTY)
+#define MT6370_MASK_RGB_DIMMODE (3 << MT6370_SHIFT_RGB_DIMMODE)
+#define MT6370_MASK_RGB_DIMDUTY (0x1f << MT6370_SHIFT_RGB_DIMDUTY)
 
 /* ========== RGBEN 0x85 (mt6370) ============ */
-#define MT6370_SHIFT_RGB_ISNK1DIM	7
-#define MT6370_SHIFT_RGB_ISNK2DIM	6
-#define MT6370_SHIFT_RGB_ISNK3DIM	5
-#define MT6370_SHIFT_RGB_ISNKDIM_BASE	8
-
-#define MT6370_MASK_RGB_ISNK1DIM_EN	BIT(MT6370_SHIFT_RGB_ISNK1DIM)
-#define MT6370_MASK_RGB_ISNK2DIM_EN	BIT(MT6370_SHIFT_RGB_ISNK2DIM)
-#define MT6370_MASK_RGB_ISNK3DIM_EN	BIT(MT6370_SHIFT_RGB_ISNK3DIM)
-#define MT6370_MASK_RGB_ISNK_ALL_EN	(MT6370_MASK_RGB_ISNK1DIM_EN | \
-					 MT6370_MASK_RGB_ISNK2DIM_EN | \
-					 MT6370_MASK_RGB_ISNK3DIM_EN)
+#define MT6370_SHIFT_RGB_ISNK1DIM 7
+#define MT6370_SHIFT_RGB_ISNK2DIM 6
+#define MT6370_SHIFT_RGB_ISNK3DIM 5
+#define MT6370_SHIFT_RGB_ISNKDIM_BASE 8
+
+#define MT6370_MASK_RGB_ISNK1DIM_EN BIT(MT6370_SHIFT_RGB_ISNK1DIM)
+#define MT6370_MASK_RGB_ISNK2DIM_EN BIT(MT6370_SHIFT_RGB_ISNK2DIM)
+#define MT6370_MASK_RGB_ISNK3DIM_EN BIT(MT6370_SHIFT_RGB_ISNK3DIM)
+#define MT6370_MASK_RGB_ISNK_ALL_EN                                  \
+	(MT6370_MASK_RGB_ISNK1DIM_EN | MT6370_MASK_RGB_ISNK2DIM_EN | \
+	 MT6370_MASK_RGB_ISNK3DIM_EN)
 
 /* ========== RGB_ISNK 0x86/0x87/0x88 (mt6370) ============ */
 #define MT6370_LED_BRIGHTNESS_MIN 0
 #define MT6370_LED_BRIGHTNESS_MAX 7
 
-#define MT6370_SHIFT_RGBISNK_CURSEL	0
-#define MT6370_SHIFT_RGBISNK_DIMFSEL	3
-#define MT6370_MASK_RGBISNK_CURSEL	(0x7 << MT6370_SHIFT_RGBISNK_CURSEL)
-#define MT6370_MASK_RGBISNK_DIMFSEL	(0x7 << MT6370_SHIFT_RGBISNK_DIMFSEL)
+#define MT6370_SHIFT_RGBISNK_CURSEL 0
+#define MT6370_SHIFT_RGBISNK_DIMFSEL 3
+#define MT6370_MASK_RGBISNK_CURSEL (0x7 << MT6370_SHIFT_RGBISNK_CURSEL)
+#define MT6370_MASK_RGBISNK_DIMFSEL (0x7 << MT6370_SHIFT_RGBISNK_DIMFSEL)
 
 /* ========== DBCTRL1 (mt6370) ============ */
-#define MT6370_SHIFT_DB_EXT_EN		0
-#define MT6370_SHIFT_DB_PERIODIC_FIX	4
-#define MT6370_SHIFT_DB_SINGLE_PIN	5
-#define MT6370_SHIFT_DB_FREQ_PM		6
-#define MT6370_SHIFT_DB_PERIODIC_MODE	7
-
-#define MT6370_MASK_DB_EXT_EN		1
-#define MT6370_MASK_DB_PERIODIC_FIX	1
-#define MT6370_MASK_DB_SINGLE_PIN	1
-#define MT6370_MASK_DB_FREQ_PM		1
-#define MT6370_MASK_DB_PERIODIC_MODE	1
+#define MT6370_SHIFT_DB_EXT_EN 0
+#define MT6370_SHIFT_DB_PERIODIC_FIX 4
+#define MT6370_SHIFT_DB_SINGLE_PIN 5
+#define MT6370_SHIFT_DB_FREQ_PM 6
+#define MT6370_SHIFT_DB_PERIODIC_MODE 7
+
+#define MT6370_MASK_DB_EXT_EN 1
+#define MT6370_MASK_DB_PERIODIC_FIX 1
+#define MT6370_MASK_DB_SINGLE_PIN 1
+#define MT6370_MASK_DB_FREQ_PM 1
+#define MT6370_MASK_DB_PERIODIC_MODE 1
 
 /* ========== DBCTRL1 (mt6370) ============ */
-#define MT6370_MASK_DB_VNEG_DISC	BIT(2)
-#define MT6370_MASK_DB_VPOS_DISC	BIT(5)
+#define MT6370_MASK_DB_VNEG_DISC BIT(2)
+#define MT6370_MASK_DB_VPOS_DISC BIT(5)
 
 /* ========== DBVBST (mt6370) ============ */
-#define MT6370_SHIFT_DB_VBST		0
+#define MT6370_SHIFT_DB_VBST 0
 
-#define MT6370_MASK_DB_VBST		0x3f
+#define MT6370_MASK_DB_VBST 0x3f
 
-#define MT6370_DB_VBST_MAX		6200
-#define MT6370_DB_VBST_MIN		4000
-#define MT6370_DB_VBST_STEP		50
+#define MT6370_DB_VBST_MAX 6200
+#define MT6370_DB_VBST_MIN 4000
+#define MT6370_DB_VBST_STEP 50
 
 /* ========== DBVPOS (mt6370) ============ */
-#define MT6370_SHIFT_DB_VPOS		0
+#define MT6370_SHIFT_DB_VPOS 0
 
-#define MT6370_MASK_DB_VPOS		0x3f
+#define MT6370_MASK_DB_VPOS 0x3f
 
-#define MT6370_DB_VPOS_MAX		6000
-#define MT6370_DB_VPOS_MIN		4000
-#define MT6370_DB_VPOS_STEP		50
+#define MT6370_DB_VPOS_MAX 6000
+#define MT6370_DB_VPOS_MIN 4000
+#define MT6370_DB_VPOS_STEP 50
 
 /* ========== DBVNEG (mt6370) ============ */
-#define MT6370_SHIFT_DB_VNEG		0
+#define MT6370_SHIFT_DB_VNEG 0
 
-#define MT6370_MASK_DB_VNEG		0x3f
+#define MT6370_MASK_DB_VNEG 0x3f
 
-#define MT6370_DB_VNEG_MAX		6000
-#define MT6370_DB_VNEG_MIN		4000
-#define MT6370_DB_VNEG_STEP		50
+#define MT6370_DB_VNEG_MAX 6000
+#define MT6370_DB_VNEG_MIN 4000
+#define MT6370_DB_VNEG_STEP 50
 
 /* ========== BLEN 0xA0 (mt6370) ============ */
-#define MT6370_SHIFT_BLED_EXT_EN	7
-#define MT6370_SHIFT_BLED_EN		6
-#define MT6370_SHIFT_BLED_1CH_EN	5
-#define MT6370_SHIFT_BLED_2CH_EN	4
-#define MT6370_SHIFT_BLED_3CH_EN	3
-#define MT6370_SHIFT_BLED_4CH_EN	2
-#define MT6370_SHIFT_BLED_CODE		1
-#define MT6370_SHIFT_BLED_CONFIG	0
-
-#define MT6370_MASK_BLED_EXT_EN		BIT(MT6370_SHIFT_BLED_EXT_EN)
-#define MT6370_MASK_BLED_EN		BIT(MT6370_SHIFT_BLED_EN)
-#define MT6370_MASK_BLED_1CH_EN		BIT(MT6370_SHIFT_BLED_1CH_EN)
-#define MT6370_MASK_BLED_2CH_EN		BIT(MT6370_SHIFT_BLED_2CH_EN)
-#define MT6370_MASK_BLED_3CH_EN		BIT(MT6370_SHIFT_BLED_3CH_EN)
-#define MT6370_MASK_BLED_4CH_EN		BIT(MT6370_SHIFT_BLED_4CH_EN)
-
-#define MT6370_BLED_CODE_LINEAR		BIT(MT6370_SHIFT_BLED_CODE)
-#define MT6370_BLED_CODE_EXP		0
-
-#define MT6370_BLED_CONFIG_ACTIVE_HIGH	BIT(MT6370_SHIFT_BLED_CONFIG)
-#define MT6370_BLED_CONFIG_ACTIVE_LOW	0
+#define MT6370_SHIFT_BLED_EXT_EN 7
+#define MT6370_SHIFT_BLED_EN 6
+#define MT6370_SHIFT_BLED_1CH_EN 5
+#define MT6370_SHIFT_BLED_2CH_EN 4
+#define MT6370_SHIFT_BLED_3CH_EN 3
+#define MT6370_SHIFT_BLED_4CH_EN 2
+#define MT6370_SHIFT_BLED_CODE 1
+#define MT6370_SHIFT_BLED_CONFIG 0
+
+#define MT6370_MASK_BLED_EXT_EN BIT(MT6370_SHIFT_BLED_EXT_EN)
+#define MT6370_MASK_BLED_EN BIT(MT6370_SHIFT_BLED_EN)
+#define MT6370_MASK_BLED_1CH_EN BIT(MT6370_SHIFT_BLED_1CH_EN)
+#define MT6370_MASK_BLED_2CH_EN BIT(MT6370_SHIFT_BLED_2CH_EN)
+#define MT6370_MASK_BLED_3CH_EN BIT(MT6370_SHIFT_BLED_3CH_EN)
+#define MT6370_MASK_BLED_4CH_EN BIT(MT6370_SHIFT_BLED_4CH_EN)
+
+#define MT6370_BLED_CODE_LINEAR BIT(MT6370_SHIFT_BLED_CODE)
+#define MT6370_BLED_CODE_EXP 0
+
+#define MT6370_BLED_CONFIG_ACTIVE_HIGH BIT(MT6370_SHIFT_BLED_CONFIG)
+#define MT6370_BLED_CONFIG_ACTIVE_LOW 0
 
 /* ========== BLPWM 0xA2 (mt6370) ============ */
-#define MT6370_SHIFT_BLPWM_BLED_PWM	7
+#define MT6370_SHIFT_BLPWM_BLED_PWM 7
 
-#define MT6370_MASK_BLPWM_BLED_PWM	BIT(MT6370_SHIFT_BLPWM_BLED_PWM)
+#define MT6370_MASK_BLPWM_BLED_PWM BIT(MT6370_SHIFT_BLPWM_BLED_PWM)
 
 /* ========== BLDIM2 0xA4 (mt6370) ============ */
-#define MT6370_MASK_BLDIM2		0x7
+#define MT6370_MASK_BLDIM2 0x7
 
 /* ========== BLDIM 0xA5 (mt6370) ============ */
-#define MT6370_SHIFT_BLDIM_MSB		3
-#define MT6370_MASK_BLDIM		0xff
+#define MT6370_SHIFT_BLDIM_MSB 3
+#define MT6370_MASK_BLDIM 0xff
 
-#define MT6370_BLDIM_DEFAULT		0x7ff
+#define MT6370_BLDIM_DEFAULT 0x7ff
 
 /* ========== CHG_IRQ1 0xC0 (mt6370) ============ */
-#define MT6370_SHIFT_MIVR_EVT		6
-#define MT6370_MASK_MIVR_EVT		BIT(MT6370_SHIFT_MIVR_EVT)
+#define MT6370_SHIFT_MIVR_EVT 6
+#define MT6370_MASK_MIVR_EVT BIT(MT6370_SHIFT_MIVR_EVT)
 
 /* ========== CHGSTAT2 0xD0 (mt6370) ============ */
-#define MT6370_SHIFT_MIVR_STAT		6
+#define MT6370_SHIFT_MIVR_STAT 6
 
 /* ========== CHGSTAT2 0xD1 (mt6370) ============ */
 #ifdef CONFIG_CHARGER_MT6370
-#define MT6370_SHIFT_CHG_VBUSOV_STAT	7
-#define MT6370_SHIFT_CHG_VBATOV_STAT	6
+#define MT6370_SHIFT_CHG_VBUSOV_STAT 7
+#define MT6370_SHIFT_CHG_VBATOV_STAT 6
 
-#define RT946X_MASK_CHG_VBATOV		MT6370_SHIFT_CHG_VBATOV_STAT
+#define RT946X_MASK_CHG_VBATOV MT6370_SHIFT_CHG_VBATOV_STAT
 
-#define MT6370_MASK_CHG_VBUSOV_STAT	BIT(MT6370_SHIFT_CHG_VBUSOV_STAT)
-#define MT6370_MASK_CHG_VBATOV_STAT	BIT(MT6370_SHIFT_CHG_VBATOV_STAT)
+#define MT6370_MASK_CHG_VBUSOV_STAT BIT(MT6370_SHIFT_CHG_VBUSOV_STAT)
+#define MT6370_MASK_CHG_VBATOV_STAT BIT(MT6370_SHIFT_CHG_VBATOV_STAT)
 #endif
 
 /* ========== TM PAS CODE1 0xF0 (mt6370) ============ */
-#define MT6370_LEAVE_TM			0x00
+#define MT6370_LEAVE_TM 0x00
 
 /* ========== BANK REG 0xFF (mt6370) ============ */
-#define MT6370_MASK_REG_TM		0x69
+#define MT6370_MASK_REG_TM 0x69
 
 /* ========== TM REG 0x34 (mt6370) ============ */
-#define MT6370_TM_MASK_BL3_SL		0xC0
-#define MT6370_TM_REDUCE_BL3_SL		0xC0
+#define MT6370_TM_MASK_BL3_SL 0xC0
+#define MT6370_TM_REDUCE_BL3_SL 0xC0
 
 /* ========== TM REG 0x37 (mt6370) ============ */
-#define MT6370_TM_MASK_DSV1_SL		0xC0
-#define MT6370_TM_REDUCE_DSV1_SL	0x00
+#define MT6370_TM_MASK_DSV1_SL 0xC0
+#define MT6370_TM_REDUCE_DSV1_SL 0x00
 
 /* ADC unit/offset */
-#define MT6370_ADC_UNIT_VBUS_DIV5	25000	/* uV */
-#define MT6370_ADC_UNIT_VBUS_DIV2	10000	/* uV */
-#define MT6370_ADC_UNIT_VSYS		5000	/* uV */
-#define MT6370_ADC_UNIT_VBAT		5000	/* uV */
-#define MT6370_ADC_UNIT_TS_BAT		25	/* 0.01% */
-#define MT6370_ADC_UNIT_IBUS		50000	/* uA */
-#define MT6370_ADC_UNIT_IBAT		50000	/* uA */
-#define MT6370_ADC_UNIT_CHG_VDDP	5000	/* uV */
-#define MT6370_ADC_UNIT_TEMP_JC		2	/* degree */
-
-#define MT6370_ADC_OFFSET_VBUS_DIV5	0	/* mV */
-#define MT6370_ADC_OFFSET_VBUS_DIV2	0	/* mV */
-#define MT6370_ADC_OFFSET_VSYS		0	/* mV */
-#define MT6370_ADC_OFFSET_VBAT		0	/* mV */
-#define MT6370_ADC_OFFSET_TS_BAT	0	/* % */
-#define MT6370_ADC_OFFSET_IBUS		0	/* mA */
-#define MT6370_ADC_OFFSET_IBAT		0	/* mA */
-#define MT6370_ADC_OFFSET_CHG_VDDP	0	/* mV */
-#define MT6370_ADC_OFFSET_TEMP_JC	(-40)	/* degree */
+#define MT6370_ADC_UNIT_VBUS_DIV5 25000 /* uV */
+#define MT6370_ADC_UNIT_VBUS_DIV2 10000 /* uV */
+#define MT6370_ADC_UNIT_VSYS 5000 /* uV */
+#define MT6370_ADC_UNIT_VBAT 5000 /* uV */
+#define MT6370_ADC_UNIT_TS_BAT 25 /* 0.01% */
+#define MT6370_ADC_UNIT_IBUS 50000 /* uA */
+#define MT6370_ADC_UNIT_IBAT 50000 /* uA */
+#define MT6370_ADC_UNIT_CHG_VDDP 5000 /* uV */
+#define MT6370_ADC_UNIT_TEMP_JC 2 /* degree */
+
+#define MT6370_ADC_OFFSET_VBUS_DIV5 0 /* mV */
+#define MT6370_ADC_OFFSET_VBUS_DIV2 0 /* mV */
+#define MT6370_ADC_OFFSET_VSYS 0 /* mV */
+#define MT6370_ADC_OFFSET_VBAT 0 /* mV */
+#define MT6370_ADC_OFFSET_TS_BAT 0 /* % */
+#define MT6370_ADC_OFFSET_IBUS 0 /* mA */
+#define MT6370_ADC_OFFSET_IBAT 0 /* mA */
+#define MT6370_ADC_OFFSET_CHG_VDDP 0 /* mV */
+#define MT6370_ADC_OFFSET_TEMP_JC (-40) /* degree */
 
 /* ========== Variant-specific configuration ============ */
 #if defined(CONFIG_CHARGER_RT9466)
-	#define RT946X_CHARGER_NAME	"rt9466"
-	#define RT946X_VENDOR_ID	0x80
-	#define RT946X_ADDR_FLAGS	0x53
+#define RT946X_CHARGER_NAME "rt9466"
+#define RT946X_VENDOR_ID 0x80
+#define RT946X_ADDR_FLAGS 0x53
 #elif defined(CONFIG_CHARGER_RT9467)
-	#define RT946X_CHARGER_NAME	"rt9467"
-	#define RT946X_VENDOR_ID	0x90
-	#define RT946X_ADDR_FLAGS	0x5B
+#define RT946X_CHARGER_NAME "rt9467"
+#define RT946X_VENDOR_ID 0x90
+#define RT946X_ADDR_FLAGS 0x5B
 #elif defined(CONFIG_CHARGER_MT6370)
-	#define RT946X_CHARGER_NAME	"mt6370"
-	#define RT946X_VENDOR_ID	0xE0
-	#define RT946X_ADDR_FLAGS	0x34
+#define RT946X_CHARGER_NAME "mt6370"
+#define RT946X_VENDOR_ID 0xE0
+#define RT946X_ADDR_FLAGS 0x34
 #else
-	#error "No suitable charger option defined"
+#error "No suitable charger option defined"
 #endif
 
 /* RT946x specific interface functions */
diff --git a/driver/charger/rt9490.c b/driver/charger/rt9490.c
new file mode 100644
index 0000000000..54bd3f9594
--- /dev/null
+++ b/driver/charger/rt9490.c
@@ -0,0 +1,814 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Richtek 5A 1-4 cell buck-boost switching battery charger driver.
+ */
+
+#include "battery.h"
+#include "battery_smart.h"
+#include "builtin/assert.h"
+#include "builtin/endian.h"
+#include "charge_manager.h"
+#include "charger.h"
+#include "common.h"
+#include "config.h"
+#include "console.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "rt9490.h"
+#include "task.h"
+#include "temp_sensor/temp_sensor.h"
+#include "temp_sensor/thermistor.h"
+#include "usb_charge.h"
+#include "usb_pd.h"
+#include "util.h"
+
+/* Console output macros */
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) \
+	cprints(CC_CHARGER, "%s " format, "RT9490", ##args)
+
+/* Charger parameters */
+#define CHARGER_NAME "rt9490"
+#define CHARGE_V_MAX 18800
+#define CHARGE_V_MIN 3000
+#define CHARGE_V_STEP 10
+#define CHARGE_I_MAX 5000
+
+/* b/238980988
+ * RT9490 can't measure the 50mA charge current precisely due to insufficient
+ * ADC resolution, and faulty leads it into battery supply mode.
+ * the final number would be expected between 100mA ~ 200mA.
+ * Vendor has done the FT correlation and will revise the datasheet's
+ * CHARGE_I_MIN value from 50mA to 150mA as the final solution.
+ */
+#define CHARGE_I_MIN 150
+#define CHARGE_I_STEP 10
+#define INPUT_I_MAX 3300
+#define INPUT_I_MIN 100
+#define INPUT_I_STEP 10
+
+/* Charger parameters */
+static const struct charger_info rt9490_charger_info = {
+	.name = CHARGER_NAME,
+	.voltage_max = CHARGE_V_MAX,
+	.voltage_min = CHARGE_V_MIN,
+	.voltage_step = CHARGE_V_STEP,
+	.current_max = CHARGE_I_MAX,
+	.current_min = CHARGE_I_MIN,
+	.current_step = CHARGE_I_STEP,
+	.input_current_max = INPUT_I_MAX,
+	.input_current_min = INPUT_I_MIN,
+	.input_current_step = INPUT_I_STEP,
+};
+
+#ifndef CONFIG_ZEPHYR
+const struct rt9490_init_setting rt9490_setting = {
+	/* b/230442545#comment28
+	 * With EOC-Force-CCM disabled, the real IEOC would be
+	 * 30~50mA lower than expected, so move eoc_current one step up
+	 */
+	.eoc_current = 240,
+	.mivr = 4000,
+	.boost_voltage = 5050,
+	.boost_current = 1500,
+};
+#endif
+
+static enum ec_error_list rt9490_read8(int chgnum, int reg, int *val)
+{
+	return i2c_read8(chg_chips[chgnum].i2c_port,
+			 chg_chips[chgnum].i2c_addr_flags, reg, val);
+}
+
+static enum ec_error_list rt9490_write8(int chgnum, int reg, int val)
+{
+	return i2c_write8(chg_chips[chgnum].i2c_port,
+			  chg_chips[chgnum].i2c_addr_flags, reg, val);
+}
+
+static enum ec_error_list rt9490_read16(int chgnum, int reg, uint16_t *val)
+{
+	int reg_val;
+
+	RETURN_ERROR(i2c_read16(chg_chips[chgnum].i2c_port,
+				chg_chips[chgnum].i2c_addr_flags, reg,
+				&reg_val));
+
+	*val = be16toh(reg_val);
+
+	return EC_SUCCESS;
+}
+
+static enum ec_error_list rt9490_write16(int chgnum, int reg, uint16_t val)
+{
+	int reg_val = htobe16(val);
+
+	return i2c_write16(chg_chips[chgnum].i2c_port,
+			   chg_chips[chgnum].i2c_addr_flags, reg, reg_val);
+}
+
+static int rt9490_field_update8(int chgnum, int reg, int mask, int val)
+{
+	return i2c_field_update8(chg_chips[chgnum].i2c_port,
+				 chg_chips[chgnum].i2c_addr_flags, reg, mask,
+				 val);
+}
+
+static inline int rt9490_update8(int chgnum, int reg, int mask,
+				 enum mask_update_action action)
+{
+	return i2c_update8(chg_chips[chgnum].i2c_port,
+			   chg_chips[chgnum].i2c_addr_flags, reg, mask, action);
+}
+
+static inline int rt9490_set_bit(int chgnum, int reg, int mask)
+{
+	return rt9490_update8(chgnum, reg, mask, MASK_SET);
+}
+
+static inline int rt9490_clr_bit(int chgnum, int reg, int mask)
+{
+	return rt9490_update8(chgnum, reg, mask, MASK_CLR);
+}
+
+static inline int rt9490_enable_hz(int chgnum, bool en)
+{
+	return rt9490_update8(chgnum, RT9490_REG_CHG_CTRL0, RT9490_EN_HZ,
+			      en ? MASK_SET : MASK_CLR);
+}
+
+static const struct charger_info *rt9490_get_info(int chgnum)
+{
+	return &rt9490_charger_info;
+}
+
+static enum ec_error_list rt9490_get_current(int chgnum, int *current)
+{
+	uint16_t val = 0;
+	const struct charger_info *const info = rt9490_get_info(chgnum);
+
+	RETURN_ERROR(rt9490_read16(chgnum, RT9490_REG_ICHG_CTRL, &val));
+
+	val = (val & RT9490_ICHG_MASK) >> RT9490_ICHG_SHIFT;
+	val *= info->current_step;
+	*current = CLAMP(val, info->current_min, info->current_max);
+
+	return EC_SUCCESS;
+}
+
+static enum ec_error_list rt9490_set_current(int chgnum, int current)
+{
+	uint16_t reg_ichg;
+	const struct charger_info *const info = rt9490_get_info(chgnum);
+
+	if (current == 0)
+		current = info->current_min;
+
+	if (!IN_RANGE(current, info->current_min, info->current_max))
+		return EC_ERROR_PARAM2;
+	reg_ichg = current / info->current_step;
+
+	return rt9490_write16(chgnum, RT9490_REG_ICHG_CTRL, reg_ichg);
+}
+
+static enum ec_error_list rt9490_get_voltage(int chgnum, int *voltage)
+{
+	uint16_t val = 0;
+	const struct charger_info *const info = rt9490_get_info(chgnum);
+
+	RETURN_ERROR(rt9490_read16(chgnum, RT9490_REG_VCHG_CTRL, &val));
+
+	val = val & RT9490_CV_MASK;
+	val *= info->voltage_step;
+	*voltage = CLAMP(val, info->voltage_min, info->voltage_max);
+
+	return EC_SUCCESS;
+}
+
+static enum ec_error_list rt9490_set_voltage(int chgnum, int voltage)
+{
+	uint16_t reg_cv;
+	const struct charger_info *const info = rt9490_get_info(chgnum);
+
+	if (voltage == 0)
+		voltage = info->voltage_min;
+
+	if (!IN_RANGE(voltage, info->voltage_min, info->voltage_max))
+		return EC_ERROR_PARAM2;
+	reg_cv = voltage / info->voltage_step;
+
+	return rt9490_write16(chgnum, RT9490_REG_VCHG_CTRL, reg_cv);
+}
+
+#ifdef CONFIG_CHARGER_OTG
+static enum ec_error_list rt9490_enable_otg_power(int chgnum, int enabled)
+{
+	return rt9490_update8(chgnum, RT9490_REG_CHG_CTRL3, RT9490_EN_OTG,
+			      enabled ? MASK_SET : MASK_CLR);
+}
+
+enum ec_error_list rt9490_set_otg_current_voltage(int chgnum,
+						  int output_current,
+						  int output_voltage)
+{
+	uint16_t reg_cur, reg_vol;
+
+	if (!IN_RANGE(output_current, RT9490_IOTG_MIN, RT9490_IOTG_MAX))
+		return EC_ERROR_PARAM2;
+	if (!IN_RANGE(output_voltage, RT9490_VOTG_MIN, RT9490_VOTG_MAX))
+		return EC_ERROR_PARAM3;
+
+	reg_cur = (output_current - RT9490_IOTG_MIN) / RT9490_IOTG_STEP + 3;
+	reg_vol = (output_voltage - RT9490_VOTG_MIN) / RT9490_VOTG_STEP;
+	RETURN_ERROR(rt9490_write8(chgnum, RT9490_REG_IOTG_REGU, reg_cur));
+
+	return rt9490_write16(chgnum, RT9490_REG_VOTG_REGU, reg_vol);
+}
+
+static int rt9490_is_sourcing_otg_power(int chgnum, int port)
+{
+	int val;
+
+	if (rt9490_read8(chgnum, RT9490_REG_CHG_CTRL3, &val))
+		return 0;
+	return !!(val & RT9490_EN_OTG);
+}
+#endif
+
+/* Reset all registers' value to default */
+static int rt9490_reset_chip(int chgnum)
+{
+	/* disable hz before reset chip */
+	RETURN_ERROR(rt9490_enable_hz(chgnum, false));
+
+	return rt9490_set_bit(chgnum, RT9490_REG_EOC_CTRL, RT9490_RST_ALL_MASK);
+}
+
+static inline int rt9490_enable_chgdet_flow(int chgnum, bool en)
+{
+	return rt9490_update8(chgnum, RT9490_REG_CHG_CTRL2, RT9490_BC12_EN,
+			      en ? MASK_SET : MASK_CLR);
+}
+
+static inline int rt9490_enable_wdt(int chgnum, bool en)
+{
+	int val = en ? RT9490_WATCHDOG_40_SEC : RT9490_WATCHDOG_DISABLE;
+
+	return rt9490_field_update8(chgnum, RT9490_REG_CHG_CTRL1,
+				    RT9490_WATCHDOG_MASK, val);
+}
+
+static inline int rt9490_set_mivr(int chgnum, unsigned int mivr)
+{
+	uint8_t reg_mivr = mivr / RT9490_MIVR_STEP;
+
+	return rt9490_write8(chgnum, RT9490_REG_MIVR_CTRL, reg_mivr);
+}
+
+static inline int rt9490_set_ieoc(int chgnum, unsigned int ieoc)
+{
+	uint8_t reg_ieoc = ieoc / RT9490_IEOC_STEP;
+
+	return rt9490_field_update8(chgnum, RT9490_REG_EOC_CTRL,
+				    RT9490_IEOC_MASK, reg_ieoc);
+}
+
+static inline int rt9490_enable_jeita(int chgnum, bool en)
+{
+	return rt9490_update8(chgnum, RT9490_REG_JEITA_CTRL1, RT9490_JEITA_DIS,
+			      en ? MASK_CLR : MASK_SET);
+}
+
+int rt9490_enable_adc(int chgnum, bool en)
+{
+	return rt9490_update8(chgnum, RT9490_REG_ADC_CTRL, RT9490_ADC_EN,
+			      en ? MASK_SET : MASK_CLR);
+}
+
+static int rt9490_set_iprec(int chgnum, unsigned int iprec)
+{
+	uint8_t reg_iprec = iprec / RT9490_IPRE_CHG_STEP;
+
+	return rt9490_field_update8(chgnum, RT9490_REG_PRE_CHG,
+				    RT9490_IPRE_CHG_MASK,
+				    reg_iprec << RT9490_IPREC_SHIFT);
+}
+
+static int rt9490_init_setting(int chgnum)
+{
+	const struct battery_info *batt_info = battery_get_info();
+
+#ifdef CONFIG_CHARGER_OTG
+	/*  Disable boost-mode output voltage */
+	RETURN_ERROR(rt9490_enable_otg_power(chgnum, 0));
+	RETURN_ERROR(rt9490_set_otg_current_voltage(
+		chgnum, rt9490_setting.boost_current,
+		rt9490_setting.boost_voltage));
+#endif
+	/* Disable ILIM_HZ pin current limit */
+	RETURN_ERROR(rt9490_clr_bit(chgnum, RT9490_REG_CHG_CTRL5,
+				    RT9490_ILIM_HZ_EN));
+	/* Disable BC 1.2 detection by default. It will be enabled on demand */
+	RETURN_ERROR(rt9490_enable_chgdet_flow(chgnum, false));
+	/* Disable WDT */
+	RETURN_ERROR(rt9490_enable_wdt(chgnum, false));
+	/* Disable battery thermal protection */
+	RETURN_ERROR(rt9490_set_bit(chgnum, RT9490_REG_ADD_CTRL0,
+				    RT9490_JEITA_COLD_HOT));
+	/* Disable AUTO_AICR / AUTO_MIVR */
+	RETURN_ERROR(rt9490_clr_bit(chgnum, RT9490_REG_ADD_CTRL0,
+				    RT9490_AUTO_AICR | RT9490_AUTO_MIVR));
+	RETURN_ERROR(rt9490_set_mivr(chgnum, rt9490_setting.mivr));
+	RETURN_ERROR(rt9490_set_ieoc(chgnum, rt9490_setting.eoc_current));
+	RETURN_ERROR(rt9490_set_iprec(chgnum, batt_info->precharge_current));
+	RETURN_ERROR(rt9490_enable_adc(chgnum, true));
+	RETURN_ERROR(rt9490_enable_jeita(chgnum, false));
+	RETURN_ERROR(rt9490_field_update8(
+		chgnum, RT9490_REG_CHG_CTRL1, RT9490_VAC_OVP_MASK,
+		RT9490_VAC_OVP_26V << RT9490_VAC_OVP_SHIFT));
+
+	/* Mask all interrupts except BC12 done */
+	RETURN_ERROR(rt9490_set_bit(chgnum, RT9490_REG_CHG_IRQ_MASK0,
+				    RT9490_CHG_IRQ_MASK0_ALL));
+	RETURN_ERROR(rt9490_set_bit(chgnum, RT9490_REG_CHG_IRQ_MASK1,
+				    RT9490_CHG_IRQ_MASK1_ALL &
+					    ~RT9490_BC12_DONE_MASK));
+	RETURN_ERROR(rt9490_set_bit(chgnum, RT9490_REG_CHG_IRQ_MASK2,
+				    RT9490_CHG_IRQ_MASK2_ALL));
+	RETURN_ERROR(rt9490_set_bit(chgnum, RT9490_REG_CHG_IRQ_MASK3,
+				    RT9490_CHG_IRQ_MASK3_ALL));
+	RETURN_ERROR(rt9490_set_bit(chgnum, RT9490_REG_CHG_IRQ_MASK4,
+				    RT9490_CHG_IRQ_MASK4_ALL));
+	RETURN_ERROR(rt9490_set_bit(chgnum, RT9490_REG_CHG_IRQ_MASK5,
+				    RT9490_CHG_IRQ_MASK5_ALL));
+	/* Reduce SW freq from 1.5MHz to 1MHz
+	 * for 10% higher current rating b/215294785
+	 */
+	RETURN_ERROR(rt9490_enable_pwm_1mhz(CHARGER_SOLO, true));
+
+	/* b/230442545#comment28
+	 * Disable EOC-Force-CCM which would potentially
+	 * cause Vsys drop problem for all silicon version(ES1~ES4)
+	 */
+	RETURN_ERROR(rt9490_set_bit(chgnum, RT9490_REG_CHG_CTRL2,
+				    RT9490_DIS_EOC_FCCM));
+
+	/* b/253568743#comment14 vsys workaround */
+	RETURN_ERROR(rt9490_enable_hidden_mode(chgnum, true));
+	rt9490_clr_bit(chgnum, RT9490_REG_HD_ADD_CTRL2,
+		       RT9490_EN_FON_PP_BAT_TRACK);
+	RETURN_ERROR(rt9490_enable_hidden_mode(chgnum, false));
+
+	/* Disable non-standard TA detection */
+	RETURN_ERROR(rt9490_clr_bit(chgnum, RT9490_REG_ADD_CTRL2,
+				    RT9490_SPEC_TA_EN));
+
+	return EC_SUCCESS;
+}
+
+int rt9490_enable_hidden_mode(int chgnum, bool en)
+{
+	if (en) {
+		RETURN_ERROR(
+			rt9490_write8(chgnum, RT9490_REG_TM_PAS_CODE1, 0x69));
+		RETURN_ERROR(
+			rt9490_write8(chgnum, RT9490_REG_TM_PAS_CODE2, 0x96));
+	} else {
+		RETURN_ERROR(rt9490_write8(chgnum, RT9490_REG_TM_PAS_CODE1, 0));
+		RETURN_ERROR(rt9490_write8(chgnum, RT9490_REG_TM_PAS_CODE2, 0));
+	}
+
+	return EC_SUCCESS;
+}
+
+int rt9490_enable_pwm_1mhz(int chgnum, bool en)
+{
+	return rt9490_update8(chgnum, RT9490_REG_ADD_CTRL1, RT9490_PWM_1MHZ_EN,
+			      en ? MASK_SET : MASK_CLR);
+}
+
+static void rt9490_init(int chgnum)
+{
+	int ret = rt9490_init_setting(chgnum);
+
+	CPRINTS("init%d %s(%d)", chgnum, ret ? "fail" : "good", ret);
+}
+
+static enum ec_error_list rt9490_get_status(int chgnum, int *status)
+{
+	int val = 0;
+
+	*status = 0;
+
+	RETURN_ERROR(rt9490_read8(chgnum, RT9490_REG_CHG_CTRL0, &val));
+	if (!(val & RT9490_EN_CHG))
+		*status |= CHARGER_CHARGE_INHIBITED;
+
+	RETURN_ERROR(rt9490_read8(chgnum, RT9490_REG_FAULT_STATUS0, &val));
+	if (val & RT9490_VBAT_OVP_STAT)
+		*status |= CHARGER_VOLTAGE_OR;
+
+	RETURN_ERROR(rt9490_read8(chgnum, RT9490_REG_CHG_STATUS4, &val));
+	if (val & RT9490_JEITA_COLD_MASK) {
+		*status |= CHARGER_RES_COLD;
+		*status |= CHARGER_RES_UR;
+	}
+	if (val & RT9490_JEITA_COOL_MASK) {
+		*status |= CHARGER_RES_COLD;
+	}
+	if (val & RT9490_JEITA_WARM_MASK) {
+		*status |= CHARGER_RES_HOT;
+	}
+	if (val & RT9490_JEITA_HOT_MASK) {
+		*status |= CHARGER_RES_HOT;
+		*status |= CHARGER_RES_OR;
+	}
+	return EC_SUCCESS;
+}
+
+static int rt9490_reset_to_zero(int chgnum)
+{
+	RETURN_ERROR(rt9490_set_current(chgnum, 0));
+	RETURN_ERROR(rt9490_set_voltage(chgnum, 0));
+	RETURN_ERROR(rt9490_enable_hz(chgnum, true));
+
+	return EC_SUCCESS;
+}
+
+static enum ec_error_list rt9490_set_mode(int chgnum, int mode)
+{
+	if (mode & CHARGE_FLAG_POR_RESET)
+		RETURN_ERROR(rt9490_reset_chip(chgnum));
+	if (mode & CHARGE_FLAG_RESET_TO_ZERO)
+		RETURN_ERROR(rt9490_reset_to_zero(chgnum));
+	return EC_SUCCESS;
+}
+
+static enum ec_error_list rt9490_get_actual_current(int chgnum, int *current)
+{
+	uint16_t reg_val;
+
+	RETURN_ERROR(rt9490_read16(chgnum, RT9490_REG_IBAT_ADC, &reg_val));
+	*current = (int)reg_val;
+	return EC_SUCCESS;
+}
+
+static enum ec_error_list rt9490_get_actual_voltage(int chgnum, int *voltage)
+{
+	uint16_t reg_val;
+
+	RETURN_ERROR(rt9490_read16(chgnum, RT9490_REG_VBAT_ADC, &reg_val));
+	*voltage = (int)reg_val;
+	return EC_SUCCESS;
+}
+
+static enum ec_error_list rt9490_discharge_on_ac(int chgnum, int enable)
+{
+	return rt9490_enable_hz(chgnum, enable);
+}
+
+static enum ec_error_list rt9490_get_vbus_voltage(int chgnum, int port,
+						  int *voltage)
+{
+	uint16_t reg_val;
+
+	RETURN_ERROR(rt9490_read16(chgnum, RT9490_REG_VBUS_ADC, &reg_val));
+	*voltage = (int)reg_val;
+	return EC_SUCCESS;
+}
+
+static enum ec_error_list rt9490_set_input_current_limit(int chgnum,
+							 int input_current)
+{
+	uint16_t reg_val;
+
+	input_current = CLAMP(input_current, RT9490_AICR_MIN, RT9490_AICR_MAX);
+	reg_val = input_current / RT9490_AICR_STEP;
+	return rt9490_write16(chgnum, RT9490_REG_AICR_CTRL, reg_val);
+}
+
+static enum ec_error_list rt9490_get_input_current_limit(int chgnum,
+							 int *input_current)
+{
+	uint16_t val = 0;
+
+	RETURN_ERROR(rt9490_read16(chgnum, RT9490_REG_AICR_CTRL, &val));
+	val = (val & RT9490_AICR_MASK) >> RT9490_AICR_SHIFT;
+	val *= RT9490_AICR_STEP;
+	*input_current = CLAMP(val, RT9490_AICR_MIN, RT9490_AICR_MAX);
+	return EC_SUCCESS;
+}
+
+static enum ec_error_list rt9490_get_input_current(int chgnum,
+						   int *input_current)
+{
+	int16_t reg_val;
+
+	RETURN_ERROR(rt9490_read16(chgnum, RT9490_REG_IBUS_ADC,
+				   (uint16_t *)&reg_val));
+	*input_current = reg_val;
+	return EC_SUCCESS;
+}
+
+static enum ec_error_list rt9490_device_id(int chgnum, int *id)
+{
+	RETURN_ERROR(rt9490_read8(chgnum, RT9490_REG_DEVICE_INFO, id));
+	*id &= RT9490_DEVICE_INFO_MASK;
+	return EC_SUCCESS;
+}
+
+#ifdef CONFIG_CHARGE_RAMP_HW
+static enum ec_error_list rt9490_set_hw_ramp(int chgnum, int enable)
+{
+	if (enable) {
+		RETURN_ERROR(rt9490_set_bit(chgnum, RT9490_REG_CHG_CTRL0,
+					    RT9490_EN_AICC));
+		RETURN_ERROR(rt9490_set_bit(chgnum, RT9490_REG_CHG_CTRL0,
+					    RT9490_FORCE_AICC));
+	} else {
+		RETURN_ERROR(rt9490_clr_bit(chgnum, RT9490_REG_CHG_CTRL0,
+					    RT9490_EN_AICC));
+	}
+	return EC_SUCCESS;
+}
+
+static int rt9490_ramp_is_stable(int chgnum)
+{
+	int rv;
+	int val = 0;
+
+	rv = rt9490_read8(chgnum, RT9490_REG_CHG_CTRL0, &val);
+	return !rv && !(val & RT9490_FORCE_AICC);
+}
+
+static int rt9490_ramp_is_detected(int chgnum)
+{
+	return true;
+}
+
+static int rt9490_ramp_get_current_limit(int chgnum)
+{
+	int rv;
+	int input_current = 0;
+
+	rv = rt9490_get_input_current_limit(chgnum, &input_current);
+	return rv ? -1 : input_current;
+}
+#endif
+
+static enum ec_error_list rt9490_get_option(int chgnum, int *option)
+{
+	/* Ignored: does not exist */
+	*option = 0;
+	return EC_SUCCESS;
+}
+
+static enum ec_error_list rt9490_set_option(int chgnum, int option)
+{
+	/* Ignored: does not exist */
+	return EC_SUCCESS;
+}
+
+#ifdef CONFIG_CMD_CHARGER_DUMP
+static void dump_range(int chgnum, int from, int to)
+{
+	for (int reg = from; reg <= to; ++reg) {
+		int val = 0;
+
+		if (!rt9490_read8(chgnum, reg, &val))
+			CPRINTS("    0x%02x: 0x%02x", reg, val);
+		else
+			CPRINTS("    0x%02x: (error)", reg);
+	}
+}
+
+static void rt9490_dump_registers(int chgnum)
+{
+	uint16_t ts, tdie;
+
+	CPRINTS("CHG_STATUS:");
+	dump_range(chgnum, RT9490_REG_CHG_STATUS0, RT9490_REG_CHG_STATUS4);
+	CPRINTS("FAULT_STATUS:");
+	dump_range(chgnum, RT9490_REG_FAULT_STATUS0, RT9490_REG_FAULT_STATUS1);
+	CPRINTS("IRQ_FLAG:");
+	dump_range(chgnum, RT9490_REG_CHG_IRQ_FLAG0, RT9490_REG_CHG_IRQ_FLAG5);
+
+	rt9490_read16(chgnum, RT9490_REG_TS_ADC, &ts);
+	CPRINTS("TS_ADC: %d.%d%%", ts / 10, ts % 10);
+	rt9490_read16(chgnum, RT9490_REG_TDIE_ADC, &tdie);
+	CPRINTS("TDIE_ADC: %d deg C", tdie);
+}
+#endif
+
+const struct charger_drv rt9490_drv = {
+	.init = &rt9490_init,
+	.get_info = &rt9490_get_info,
+	.get_status = &rt9490_get_status,
+	.set_mode = &rt9490_set_mode,
+#ifdef CONFIG_CHARGER_OTG
+	.enable_otg_power = &rt9490_enable_otg_power,
+	.set_otg_current_voltage = &rt9490_set_otg_current_voltage,
+	.is_sourcing_otg_power = &rt9490_is_sourcing_otg_power,
+#endif
+	.get_current = &rt9490_get_current,
+	.set_current = &rt9490_set_current,
+	.get_voltage = &rt9490_get_voltage,
+	.set_voltage = &rt9490_set_voltage,
+	.get_actual_current = &rt9490_get_actual_current,
+	.get_actual_voltage = &rt9490_get_actual_voltage,
+	.discharge_on_ac = &rt9490_discharge_on_ac,
+	.get_vbus_voltage = &rt9490_get_vbus_voltage,
+	.set_input_current_limit = &rt9490_set_input_current_limit,
+	.get_input_current_limit = &rt9490_get_input_current_limit,
+	.get_input_current = &rt9490_get_input_current,
+	.get_option = &rt9490_get_option,
+	.set_option = &rt9490_set_option,
+	.device_id = &rt9490_device_id,
+#ifdef CONFIG_CHARGE_RAMP_HW
+	.set_hw_ramp = &rt9490_set_hw_ramp,
+	.ramp_is_stable = &rt9490_ramp_is_stable,
+	.ramp_is_detected = &rt9490_ramp_is_detected,
+	.ramp_get_current_limit = &rt9490_ramp_get_current_limit,
+#endif
+#ifdef CONFIG_CMD_CHARGER_DUMP
+	.dump_registers = &rt9490_dump_registers,
+#endif
+};
+
+#ifdef CONFIG_USB_CHARGER
+/* BC1.2 */
+static int rt9490_get_bc12_ilim(enum charge_supplier supplier)
+{
+	switch (supplier) {
+	case CHARGE_SUPPLIER_BC12_DCP:
+	case CHARGE_SUPPLIER_BC12_CDP:
+		return USB_CHARGER_MAX_CURR_MA;
+	case CHARGE_SUPPLIER_BC12_SDP:
+	default:
+		return USB_CHARGER_MIN_CURR_MA;
+	}
+}
+
+static enum charge_supplier rt9490_get_bc12_device_type(int chgnum)
+{
+	int reg, vbus_stat;
+
+	if (rt9490_read8(chgnum, RT9490_REG_CHG_STATUS1, &reg))
+		return CHARGE_SUPPLIER_NONE;
+
+	vbus_stat = (reg & RT9490_VBUS_STAT_MASK) >> RT9490_VBUS_STAT_SHIFT;
+
+	switch (vbus_stat) {
+	case RT9490_SDP:
+		CPRINTS("BC12 SDP");
+		return CHARGE_SUPPLIER_BC12_SDP;
+	case RT9490_CDP:
+		CPRINTS("BC12 CDP");
+		return CHARGE_SUPPLIER_BC12_CDP;
+	case RT9490_DCP:
+		CPRINTS("BC12 DCP");
+		return CHARGE_SUPPLIER_BC12_DCP;
+	default:
+		CPRINTS("BC12 UNKNOWN 0x%02X", vbus_stat);
+		return CHARGE_SUPPLIER_NONE;
+	}
+}
+
+static void rt9490_update_charge_manager(int port,
+					 enum charge_supplier new_bc12_type)
+{
+	static enum charge_supplier current_bc12_type = CHARGE_SUPPLIER_NONE;
+
+	if (new_bc12_type != current_bc12_type) {
+		if (current_bc12_type >= 0)
+			charge_manager_update_charge(current_bc12_type, port,
+						     NULL);
+
+		if (new_bc12_type != CHARGE_SUPPLIER_NONE) {
+			struct charge_port_info chg = {
+				.current = rt9490_get_bc12_ilim(new_bc12_type),
+				.voltage = USB_CHARGER_VOLTAGE_MV,
+			};
+
+			charge_manager_update_charge(new_bc12_type, port, &chg);
+		}
+
+		current_bc12_type = new_bc12_type;
+	}
+}
+
+/* TODO: chgnum is not passed into the task, assuming only one charger */
+#ifndef CONFIG_CHARGER_SINGLE_CHIP
+#error rt9490 bc1.2 driver only works in single charger mode.
+#endif
+
+static void rt9490_usb_charger_task_init(const int port)
+{
+	rt9490_enable_chgdet_flow(CHARGER_SOLO, false);
+}
+
+static void rt9490_usb_charger_task_event(const int port, uint32_t evt)
+{
+	/*
+	 * b/193753475#comment33: don't trigger bc1.2 detection after
+	 * PRSwap/FRSwap.
+	 *
+	 * Note that the only scenario we want to catch is power role swap. For
+	 * other cases, `is_non_pd_sink` may have false positive (e.g.
+	 * pd_capable() is false during initial PD negotiation). But it's okay
+	 * to always trigger bc1.2 detection for other cases.
+	 */
+	bool is_non_pd_sink = !pd_capable(port) &&
+			      !usb_charger_port_is_sourcing_vbus(port) &&
+			      pd_check_vbus_level(port, VBUS_PRESENT);
+
+	/* vbus change, start bc12 detection */
+	if (evt & USB_CHG_EVENT_VBUS) {
+		if (is_non_pd_sink)
+			rt9490_enable_chgdet_flow(CHARGER_SOLO, true);
+		else
+			rt9490_update_charge_manager(port,
+						     CHARGE_SUPPLIER_NONE);
+	}
+
+	/* detection done, update charge_manager and stop detection */
+	if (evt & USB_CHG_EVENT_BC12) {
+		enum charge_supplier supplier;
+
+		if (is_non_pd_sink)
+			supplier = rt9490_get_bc12_device_type(CHARGER_SOLO);
+		else
+			supplier = CHARGE_SUPPLIER_NONE;
+
+		rt9490_update_charge_manager(port, supplier);
+		rt9490_enable_chgdet_flow(CHARGER_SOLO, false);
+	}
+}
+
+static atomic_t pending_events;
+
+void rt9490_deferred_interrupt(void)
+{
+	atomic_t current = atomic_clear(&pending_events);
+
+	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) {
+		int ret, irq_flag;
+
+		if (!(current & BIT(port)))
+			continue;
+
+		if (bc12_ports[port].drv != &rt9490_bc12_drv)
+			continue;
+
+		/* IRQ flag is read clear, no need to write back */
+		ret = rt9490_read8(CHARGER_SOLO, RT9490_REG_CHG_IRQ_FLAG1,
+				   &irq_flag);
+		if (ret)
+			return;
+
+		if (irq_flag & RT9490_BC12_DONE_FLAG)
+			usb_charger_task_set_event(port, USB_CHG_EVENT_BC12);
+	}
+}
+DECLARE_DEFERRED(rt9490_deferred_interrupt);
+
+void rt9490_interrupt(int port)
+{
+	atomic_or(&pending_events, BIT(port));
+	hook_call_deferred(&rt9490_deferred_interrupt_data, 0);
+}
+
+const struct bc12_drv rt9490_bc12_drv = {
+	.usb_charger_task_init = rt9490_usb_charger_task_init,
+	.usb_charger_task_event = rt9490_usb_charger_task_event,
+};
+
+#ifdef CONFIG_BC12_SINGLE_DRIVER
+/* provide a default bc12_ports[] for backward compatibility */
+struct bc12_config bc12_ports[CHARGE_PORT_COUNT] = {
+	[0 ... (CHARGE_PORT_COUNT - 1)] = {
+		.drv = &rt9490_bc12_drv,
+	},
+};
+#endif /* CONFIG_BC12_SINGLE_DRIVER */
+#endif /* CONFIG_USB_CHARGER */
+
+int rt9490_get_thermistor_val(const struct temp_sensor_t *sensor, int *temp_ptr)
+{
+	uint16_t mv;
+	int idx = sensor->idx;
+#if IS_ENABLED(CONFIG_ZEPHYR) && IS_ENABLED(CONFIG_TEMP_SENSOR)
+	const struct thermistor_info *info = sensor->zephyr_info->thermistor;
+#else
+	const struct thermistor_info *info = &rt9490_thermistor_info;
+#endif
+
+	if (idx != 0)
+		return EC_ERROR_PARAM1;
+	RETURN_ERROR(rt9490_read16(idx, RT9490_REG_TS_ADC, &mv));
+	*temp_ptr = thermistor_linear_interpolate(mv, info);
+	*temp_ptr = C_TO_K(*temp_ptr);
+	return EC_SUCCESS;
+}
diff --git a/driver/charger/rt9490.h b/driver/charger/rt9490.h
new file mode 100644
index 0000000000..476be39784
--- /dev/null
+++ b/driver/charger/rt9490.h
@@ -0,0 +1,278 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Richtek 5A 1-4 cell buck-boost switching battery charger driver.
+ */
+#include "temp_sensor.h"
+
+#include <stdbool.h>
+
+#ifndef __CROS_EC_RT9490_H
+#define __CROS_EC_RT9490_H
+
+#define RT9490_ADDR_FLAGS 0x53
+
+/* Registers */
+#define RT9490_REG_SYS_MIN_REGU 0x00
+#define RT9490_REG_VCHG_CTRL 0x01
+#define RT9490_REG_ICHG_CTRL 0x03
+#define RT9490_REG_MIVR_CTRL 0x05
+#define RT9490_REG_AICR_CTRL 0x06
+#define RT9490_REG_PRE_CHG 0x08
+#define RT9490_REG_EOC_CTRL 0x09
+#define RT9490_REG_RECHG 0x0A
+#define RT9490_REG_VOTG_REGU 0x0B
+#define RT9490_REG_IOTG_REGU 0x0D
+#define RT9490_REG_SAFETY_TMR_CTRL 0x0E
+#define RT9490_REG_CHG_CTRL0 0x0F
+#define RT9490_REG_CHG_CTRL1 0x10
+#define RT9490_REG_CHG_CTRL2 0x11
+#define RT9490_REG_CHG_CTRL3 0x12
+#define RT9490_REG_CHG_CTRL4 0x13
+#define RT9490_REG_CHG_CTRL5 0x14
+#define RT9490_REG_THREG_CTRL 0x16
+#define RT9490_REG_JEITA_CTRL0 0x17
+#define RT9490_REG_JEITA_CTRL1 0x18
+#define RT9490_REG_AICC_CTRL 0x19
+#define RT9490_REG_CHG_STATUS0 0x1B
+#define RT9490_REG_CHG_STATUS1 0x1C
+#define RT9490_REG_CHG_STATUS2 0x1D
+#define RT9490_REG_CHG_STATUS3 0x1E
+#define RT9490_REG_CHG_STATUS4 0x1F
+#define RT9490_REG_FAULT_STATUS0 0x20
+#define RT9490_REG_FAULT_STATUS1 0x21
+#define RT9490_REG_CHG_IRQ_FLAG0 0x22
+#define RT9490_REG_CHG_IRQ_FLAG1 0x23
+#define RT9490_REG_CHG_IRQ_FLAG2 0x24
+#define RT9490_REG_CHG_IRQ_FLAG3 0x25
+#define RT9490_REG_CHG_IRQ_FLAG4 0x26
+#define RT9490_REG_CHG_IRQ_FLAG5 0x27
+#define RT9490_REG_CHG_IRQ_MASK0 0x28
+#define RT9490_REG_CHG_IRQ_MASK1 0x29
+#define RT9490_REG_CHG_IRQ_MASK2 0x2A
+#define RT9490_REG_CHG_IRQ_MASK3 0x2B
+#define RT9490_REG_CHG_IRQ_MASK4 0x2C
+#define RT9490_REG_CHG_IRQ_MASK5 0x2D
+#define RT9490_REG_ADC_CTRL 0x2E
+#define RT9490_REG_ADC_CHANNEL0 0x2F
+#define RT9490_REG_ADC_CHANNEL1 0x30
+#define RT9490_REG_IBUS_ADC 0x31
+#define RT9490_REG_IBAT_ADC 0x33
+#define RT9490_REG_VBUS_ADC 0x35
+#define RT9490_REG_VAC1_ADC 0x37
+#define RT9490_REG_VAC2_ADC 0x39
+#define RT9490_REG_VBAT_ADC 0x3B
+#define RT9490_REG_VSYS_ADC 0x3D
+#define RT9490_REG_TS_ADC 0x3F
+#define RT9490_REG_TDIE_ADC 0x41
+#define RT9490_REG_DP_ADC 0x43
+#define RT9490_REG_DM_ADC 0x45
+#define RT9490_REG_DPDM_MANU_CTRL 0x47
+#define RT9490_REG_DEVICE_INFO 0x48
+#define RT9490_REG_PUMP_EXP 0x49
+#define RT9490_REG_ADD_CTRL0 0x4A
+#define RT9490_REG_ADD_CTRL1 0x4B
+#define RT9490_REG_ADD_CTRL2 0x4C
+#define RT9490_REG_ADD_IRQ_FLAG 0x4D
+#define RT9490_REG_ADD_IRQ_MASK6 0x4E
+#define RT9490_REG_HD_ADD_CTRL2 0x6F
+#define RT9490_REG_TM_PAS_CODE1 0xF1
+#define RT9490_REG_TM_PAS_CODE2 0xF2
+
+struct rt9490_init_setting {
+	int eoc_current;
+	int mivr;
+	int boost_voltage;
+	int boost_current;
+};
+
+/* CV */
+#define RT9490_CV_MASK 0x7FF
+#define RT9490_CV_MIN 3000
+#define RT9490_CV_MAX 18800
+#define RT9490_CV_STEP 10
+
+/* ICGH */
+#define RT9490_ICHG_MASK 0x1FF
+#define RT9490_ICHG_SHIFT 0
+#define RT9490_ICHG_MIN 50
+#define RT9490_ICHG_MAX 5000
+#define RT9490_ICHG_STEP 10
+#define RT9490_ICHG_MIN_REG_VAL 0x0005
+
+/* PRE CHG */
+#define RT9490_IPRE_CHG_MASK 0x1F
+#define RT9490_IPRE_CHG_MIN 40
+#define RT9490_IPRE_CHG_MAX 2000
+#define RT9490_IPRE_CHG_STEP 40
+#define RT9490_IPREC_SHIFT 0
+
+/* MIVR */
+#define RT9490_MIVR_MIN 3600
+#define RT9490_MIVR_MAX 22000
+#define RT9490_MIVR_STEP 100
+#define RT9490_MIVR_MIN_REG_VAL 0x24
+
+/* AICR */
+#define RT9490_AICR_MASK 0x1FF
+#define RT9490_AICR_SHIFT 0
+#define RT9490_AICR_MIN 100
+#define RT9490_AICR_MAX 3300
+#define RT9490_AICR_STEP 10
+#define RT9490_AICR_MIN_REG_VAL 0x000A
+
+/* EOC */
+#define RT9490_IEOC_MIN 40
+#define RT9490_IEOC_MAX 1000
+#define RT9490_IEOC_STEP 40
+#define RT9490_IEOC_MIN_REG_VAL 0x01
+#define RT9490_IEOC_SHIFT 0
+#define RT9490_IEOC_MASK 0x1F
+
+/* DEVICE INFO */
+#define RT9490_DEVICE_ID 0x60
+#define RT9490_DEVICE_INFO_MASK 0x78
+
+/* EOC_CTRL */
+#define RT9490_RST_ALL_MASK BIT(7)
+
+/* CHG_CTRL0 */
+#define RT9490_EN_CHG BIT(5)
+#define RT9490_EN_AICC BIT(4)
+#define RT9490_FORCE_AICC BIT(3)
+#define RT9490_EN_HZ BIT(2)
+
+/* CHG_CTRL1 */
+#define RT9490_VAC_OVP_SHIFT 4
+#define RT9490_VAC_OVP_MASK (3 << RT9490_VAC_OVP_SHIFT)
+#define RT9490_VAC_OVP_26V 0
+#define RT9490_VAC_OVP_22V 1
+#define RT9490_VAC_OVP_12V 2
+#define RT9490_VAC_OVP_7V 3
+
+#define RT9490_WATCHDOG_MASK 0x07
+#define RT9490_WATCHDOG_DISABLE 0
+#define RT9490_WATCHDOG_0_5_SEC 1 /* 0.5 sec */
+#define RT9490_WATCHDOG_1_SEC 2
+#define RT9490_WATCHDOG_2_SEC 3
+#define RT9490_WATCHDOG_20_SEC 4
+#define RT9490_WATCHDOG_40_SEC 5
+#define RT9490_WATCHDOG_80_SEC 6
+#define RT9490_WATCHDOG_160_SEC 7
+
+/* CHG_CTRL2 */
+#define RT9490_BC12_EN BIT(6)
+#define RT9490_DIS_EOC_FCCM BIT(3)
+
+/* CHG_CTRL3 */
+#define RT9490_EN_OTG BIT(6)
+
+/* CHG_CTRL5 */
+#define RT9490_ILIM_HZ_EN BIT(1)
+
+/* CHG_STATUS4 */
+#define RT9490_JEITA_COLD_MASK BIT(3)
+#define RT9490_JEITA_COOL_MASK BIT(2)
+#define RT9490_JEITA_WARM_MASK BIT(1)
+#define RT9490_JEITA_HOT_MASK BIT(0)
+
+/* CHG_IRQ_FLAG1 */
+#define RT9490_BC12_DONE_FLAG BIT(0)
+
+/* CHG_IRQ_MASK0 */
+#define RT9490_CHG_IRQ_MASK0_ALL 0xFF
+
+/* CHG_IRQ_MASK1 */
+#define RT9490_BC12_DONE_MASK BIT(0)
+#define RT9490_CHG_IRQ_MASK1_ALL 0xD7
+
+/* CHG_IRQ_MASK2 */
+#define RT9490_CHG_IRQ_MASK2_ALL 0x7F
+
+/* CHG_IRQ_MASK3 */
+#define RT9490_CHG_IRQ_MASK3_ALL 0x1F
+
+/* CHG_IRQ_MASK4 */
+#define RT9490_CHG_IRQ_MASK4_ALL 0xFF
+
+/* CHG_IRQ_MASK5 */
+#define RT9490_CHG_IRQ_MASK5_ALL 0xF4
+
+/* SAFETY TMR CTRL */
+#define RT9490_EN_TRICHG_TMR BIT(5)
+#define RT9490_EN_PRECHG_TMR BIT(4)
+#define RT9490_EN_FASTCHG_TMR BIT(3)
+
+/* VOTG REGU */
+#define RT9490_VOTG_MASK 0x7FF
+#define RT9490_VOTG_MIN 2800
+#define RT9490_VOTG_MAX 22000
+#define RT9490_VOTG_STEP 10
+
+/* IOTG REGU */
+#define RT9490_IOTG_MASK 0x7F
+#define RT9490_IOTG_MIN 120
+#define RT9490_IOTG_MAX 3320
+#define RT9490_IOTG_STEP 40
+
+/* JEITA_CTRL1 */
+#define RT9490_JEITA_DIS BIT(0)
+
+/* CHG_STATUS1 */
+#define RT9490_CHG_STAT_MASK 0xE0
+#define RT9490_CHG_STAT_SHIFT 5
+#define RT9490_VBUS_STAT_MASK 0x1E
+#define RT9490_VBUS_STAT_SHIFT 1
+#define RT9490_BC12_DONE_STAT BIT(0)
+
+#define RT9490_SDP 0x1
+#define RT9490_CDP 0x2
+#define RT9490_DCP 0x3
+
+/* FAULT STATUS0 */
+#define RT9490_VBAT_OVP_STAT BIT(5)
+
+/* ADC CTRL */
+#define RT9490_ADC_EN BIT(7)
+
+/* ADC CHANNEL0 */
+#define RT9490_VSYS_ADC_DIS BIT(3)
+
+/* ADD CTRL0 */
+#define RT9490_AUTO_AICR BIT(5)
+#define RT9490_TD_EOC BIT(4)
+#define RT9490_AUTO_MIVR BIT(2)
+#define RT9490_JEITA_COLD_HOT BIT(0)
+
+/* ADD CTRL1 */
+#define RT9490_PWM_1MHZ_EN BIT(4)
+
+/* ADD CTRL2 */
+#define RT9490_SPEC_TA_EN BIT(2)
+
+/* HD_ADD_CTRL 2 */
+#define RT9490_EN_FON_PP_BAT_TRACK BIT(5)
+
+extern const struct charger_drv rt9490_drv;
+extern const struct bc12_drv rt9490_bc12_drv;
+
+void rt9490_interrupt(int port);
+
+int rt9490_enable_adc(int chgnum, bool en);
+/* enable pwm frequency 1MHz mode */
+int rt9490_enable_pwm_1mhz(int chgnum, bool en);
+
+int rt9490_enable_hidden_mode(int chgnum, bool en);
+
+#endif /* __CROS_EC_RT9490_H */
+
+/*
+ * Required for TS_ADC temperature calculation.
+ * Non-zephyr devices that using TS_ADC must define this in board layer.
+ */
+extern const struct thermistor_info rt9490_thermistor_info;
+
+int rt9490_get_thermistor_val(const struct temp_sensor_t *sensor,
+			      int *temp_ptr);
+extern const struct rt9490_init_setting rt9490_setting;
diff --git a/driver/charger/sm5803.c b/driver/charger/sm5803.c
index a7b7611d98..02235a7fa3 100644
--- a/driver/charger/sm5803.c
+++ b/driver/charger/sm5803.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -7,16 +7,20 @@
 #include "atomic.h"
 #include "battery.h"
 #include "battery_smart.h"
-#include "charge_state_v2.h"
+#include "charge_state.h"
 #include "charger.h"
+#include "extpower.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "i2c.h"
 #include "sm5803.h"
+#include "stdbool.h"
+#include "system.h"
 #include "throttle_ap.h"
 #include "timer.h"
 #include "usb_charge.h"
 #include "usb_pd.h"
+#include "usbc_ocp.h"
 #include "util.h"
 #include "watchdog.h"
 
@@ -24,129 +28,195 @@
 #error "SM5803 is a NVDC charger, please enable CONFIG_CHARGER_NARROW_VDC."
 #endif
 
+#ifdef PD_MAX_VOLTAGE_MV
+#if PD_MAX_VOLTAGE_MV > 15000
+/* See https://issuetracker.google.com/230712704 for details. */
+#error "VBUS >15V is forbidden for SM5803 because it can cause hardware damage"
+#endif
+#endif
+
+#ifdef CONFIG_CHARGER_SINGLE_CHIP
+#define CHARGER_PRIMARY CHARGER_SOLO
+#endif
+
 /* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 #define UNKNOWN_DEV_ID -1
-static int dev_id = UNKNOWN_DEV_ID;
+test_export_static int dev_id = UNKNOWN_DEV_ID;
 
 static const struct charger_info sm5803_charger_info = {
-	.name         = CHARGER_NAME,
-	.voltage_max  = CHARGE_V_MAX,
-	.voltage_min  = CHARGE_V_MIN,
+	.name = CHARGER_NAME,
+	.voltage_max = CHARGE_V_MAX,
+	.voltage_min = CHARGE_V_MIN,
 	.voltage_step = CHARGE_V_STEP,
-	.current_max  = CHARGE_I_MAX,
-	.current_min  = CHARGE_I_MIN,
+	.current_max = CHARGE_I_MAX,
+	.current_min = CHARGE_I_MIN,
 	.current_step = CHARGE_I_STEP,
-	.input_current_max  = INPUT_I_MAX,
-	.input_current_min  = INPUT_I_MIN,
+	.input_current_max = INPUT_I_MAX,
+	.input_current_min = INPUT_I_MIN,
 	.input_current_step = INPUT_I_STEP,
 };
 
-static uint32_t irq_pending; /* Bitmask of chips with interrupts pending */
+static atomic_t irq_pending; /* Bitmask of chips with interrupts pending */
 
-static struct mutex flow1_access_lock[CHARGER_NUM];
-static struct mutex flow2_access_lock[CHARGER_NUM];
+static mutex_t flow1_access_lock[CHARGER_NUM];
+static mutex_t flow2_access_lock[CHARGER_NUM];
 
 static int charger_vbus[CHARGER_NUM];
 
+/* Tracker for charging failures per port */
+struct {
+	int count;
+	timestamp_t time;
+} failure_tracker[CHARGER_NUM] = {};
+
+/* Port to restart charging on */
+static int active_restart_port = CHARGE_PORT_NONE;
+
+/*
+ * If powered from the sub board port, we need to attempt to enable the BFET
+ * before proceeding with charging.
+ */
+static int attempt_bfet_enable;
+
+/*
+ * Note if auto fast charge for the primary port is disabled due to a
+ * disconnected battery, at re-enable auto fast charge later when the battery
+ * has connected.
+ */
+static bool fast_charge_disabled;
+
+#ifdef TEST_BUILD
+void test_sm5803_set_fast_charge_disabled(bool value)
+{
+	fast_charge_disabled = value;
+}
+
+bool test_sm5803_get_fast_charge_disabled(void)
+{
+	return fast_charge_disabled;
+}
+#endif
+
+#define CHARGING_FAILURE_MAX_COUNT 5
+#define CHARGING_FAILURE_INTERVAL MINUTE
+
 static int sm5803_is_sourcing_otg_power(int chgnum, int port);
 static enum ec_error_list sm5803_get_dev_id(int chgnum, int *id);
+static enum ec_error_list sm5803_set_current(int chgnum, int current);
 
 static inline enum ec_error_list chg_read8(int chgnum, int offset, int *value)
 {
 	return i2c_read8(chg_chips[chgnum].i2c_port,
-			 chg_chips[chgnum].i2c_addr_flags,
-			 offset, value);
+			 chg_chips[chgnum].i2c_addr_flags, offset, value);
 }
 
 static inline enum ec_error_list chg_write8(int chgnum, int offset, int value)
 {
 	return i2c_write8(chg_chips[chgnum].i2c_port,
-			  chg_chips[chgnum].i2c_addr_flags,
-			  offset, value);
+			  chg_chips[chgnum].i2c_addr_flags, offset, value);
 }
 
 static inline enum ec_error_list meas_read8(int chgnum, int offset, int *value)
 {
-	return i2c_read8(chg_chips[chgnum].i2c_port,
-			 SM5803_ADDR_MEAS_FLAGS,
+	return i2c_read8(chg_chips[chgnum].i2c_port, SM5803_ADDR_MEAS_FLAGS,
 			 offset, value);
 }
 
 static inline enum ec_error_list meas_write8(int chgnum, int offset, int value)
 {
-	return i2c_write8(chg_chips[chgnum].i2c_port,
-			 SM5803_ADDR_MEAS_FLAGS,
-			 offset, value);
+	return i2c_write8(chg_chips[chgnum].i2c_port, SM5803_ADDR_MEAS_FLAGS,
+			  offset, value);
 }
 
 static inline enum ec_error_list main_read8(int chgnum, int offset, int *value)
 {
-	return i2c_read8(chg_chips[chgnum].i2c_port,
-			 SM5803_ADDR_MAIN_FLAGS,
+	return i2c_read8(chg_chips[chgnum].i2c_port, SM5803_ADDR_MAIN_FLAGS,
 			 offset, value);
 }
 
 static inline enum ec_error_list main_write8(int chgnum, int offset, int value)
 {
-	return i2c_write8(chg_chips[chgnum].i2c_port,
-			 SM5803_ADDR_MAIN_FLAGS,
-			 offset, value);
+	return i2c_write8(chg_chips[chgnum].i2c_port, SM5803_ADDR_MAIN_FLAGS,
+			  offset, value);
 }
 
 static inline enum ec_error_list test_write8(int chgnum, int offset, int value)
 {
-	return i2c_write8(chg_chips[chgnum].i2c_port,
-			 SM5803_ADDR_TEST_FLAGS,
-			 offset, value);
+	return i2c_write8(chg_chips[chgnum].i2c_port, SM5803_ADDR_TEST_FLAGS,
+			  offset, value);
 }
 
-static inline enum ec_error_list test_update8(int chgnum, const int offset,
-					      const uint8_t mask,
-					const enum mask_update_action action)
+static inline enum ec_error_list
+test_update8(int chgnum, const int offset, const uint8_t mask,
+	     const enum mask_update_action action)
 {
-	return i2c_update8(chg_chips[chgnum].i2c_port,
-			   SM5803_ADDR_TEST_FLAGS, offset, mask, action);
+	return i2c_update8(chg_chips[chgnum].i2c_port, SM5803_ADDR_TEST_FLAGS,
+			   offset, mask, action);
 }
 
-static enum ec_error_list sm5803_flow1_update(int chgnum, const uint8_t mask,
-					const enum mask_update_action action)
+/*
+ * Ensure the charger configuration is safe for operation, updating registers
+ * as necessary to become safe.
+ *
+ * The SM5803 runs multiple digital control loops that are important to correct
+ * operation. The CLOCK_SEL_LOW register reduces their speed by about 10x, which
+ * is dangerous when either sinking or sourcing is to be enabled because the
+ * control loops will respond much more slowly. Leaving clocks at low speed can
+ * cause incorrect operation or even hardware damage.
+ *
+ * The GPADCs are inputs to the control loops, and disabling them can also cause
+ * incorrect operation or hardware damage. They must be enabled for the charger
+ * to be safe to operate.
+ *
+ * This function is used by the functions that enable sinking or sourcing to
+ * ensure the current configuration is safe before enabling switching on the
+ * charger.
+ */
+static int sm5803_set_active_safe(int chgnum)
 {
-	int reg, rv, dev_id;
+	int rv, val;
 
 	/*
-	 * On Si rev 3, confirm that init value in 0x5C is intact before
-	 * enabling charging.
+	 * Set clocks to full speed.
+	 *
+	 * This should occur first because enabling GPADCs with clocks slowed
+	 * can cause spurious acquisition.
 	 */
-	rv = sm5803_get_dev_id(chgnum, &dev_id);
-	if (rv)
-		return rv;
-
-	if (dev_id == 0x03) {
-		rv = chg_read8(chgnum, 0x5C, &reg);
-		if (rv) {
-			CPRINTS("%s %d: Failed 0x5C read",
-				CHARGER_NAME, chgnum);
-			return rv;
-		}
+	rv = main_read8(chgnum, SM5803_REG_CLOCK_SEL, &val);
+	if (rv == 0 && val & SM5803_CLOCK_SEL_LOW) {
+		rv = main_write8(chgnum, SM5803_REG_CLOCK_SEL,
+				 val & ~SM5803_CLOCK_SEL_LOW);
+	}
+	if (rv) {
+		goto out;
+	}
 
-		if (reg != 0x7A) {
-			CPRINTS("%s %d: Unexpected 0x5C reg: 0x%02x. File bug",
-				CHARGER_NAME, chgnum, reg);
+	/* Enable default GPADCs */
+	rv = meas_write8(chgnum, SM5803_REG_GPADC_CONFIG1,
+			 SM5803_GPADCC1_DEFAULT_ENABLE);
 
-			/* Fix it before enabling charging */
-			rv = chg_write8(chgnum, 0x5C, 0x7A);
-		}
+out:
+	if (rv) {
+		CPRINTS("%s %d: failed to set clocks to full speed: %d",
+			CHARGER_NAME, chgnum, rv);
 	}
+	return rv;
+}
+
+static enum ec_error_list
+sm5803_flow1_update(int chgnum, const uint8_t mask,
+		    const enum mask_update_action action)
+{
+	int rv;
 
 	/* Safety checks done, onto the actual register update */
 	mutex_lock(&flow1_access_lock[chgnum]);
 
 	rv = i2c_update8(chg_chips[chgnum].i2c_port,
-			 chg_chips[chgnum].i2c_addr_flags,
-			 SM5803_REG_FLOW1,
+			 chg_chips[chgnum].i2c_addr_flags, SM5803_REG_FLOW1,
 			 mask, action);
 
 	mutex_unlock(&flow1_access_lock[chgnum]);
@@ -154,16 +224,16 @@ static enum ec_error_list sm5803_flow1_update(int chgnum, const uint8_t mask,
 	return rv;
 }
 
-static enum ec_error_list sm5803_flow2_update(int chgnum, const uint8_t mask,
-					const enum mask_update_action action)
+static enum ec_error_list
+sm5803_flow2_update(int chgnum, const uint8_t mask,
+		    const enum mask_update_action action)
 {
 	int rv;
 
 	mutex_lock(&flow2_access_lock[chgnum]);
 
 	rv = i2c_update8(chg_chips[chgnum].i2c_port,
-			 chg_chips[chgnum].i2c_addr_flags,
-			 SM5803_REG_FLOW2,
+			 chg_chips[chgnum].i2c_addr_flags, SM5803_REG_FLOW2,
 			 mask, action);
 
 	mutex_unlock(&flow2_access_lock[chgnum]);
@@ -171,6 +241,16 @@ static enum ec_error_list sm5803_flow2_update(int chgnum, const uint8_t mask,
 	return rv;
 }
 
+static bool is_platform_id_2s(uint32_t platform_id)
+{
+	return platform_id >= 0x06 && platform_id <= 0x0D;
+}
+
+static bool is_platform_id_3s(uint32_t platform_id)
+{
+	return platform_id >= 0x0E && platform_id <= 0x16;
+}
+
 int sm5803_is_vbus_present(int chgnum)
 {
 	return charger_vbus[chgnum];
@@ -276,6 +356,11 @@ enum ec_error_list sm5803_vbus_sink_enable(int chgnum, int enable)
 		return rv;
 
 	if (enable) {
+		rv = sm5803_set_active_safe(chgnum);
+		if (rv) {
+			return rv;
+		}
+
 		if (chgnum == CHARGER_PRIMARY) {
 			/* Magic for new silicon */
 			if (dev_id >= 3) {
@@ -283,9 +368,25 @@ enum ec_error_list sm5803_vbus_sink_enable(int chgnum, int enable)
 				rv |= test_write8(chgnum, 0x44, 0x2);
 				rv |= main_write8(chgnum, 0x1F, 0);
 			}
-			rv = sm5803_flow2_update(chgnum,
-						 SM5803_FLOW2_AUTO_ENABLED,
-						 MASK_SET);
+			/*
+			 * Only enable auto fast charge when a battery is
+			 * connected and out of cutoff.
+			 */
+			if (IS_ENABLED(CONFIG_BATTERY) &&
+			    battery_get_disconnect_state() ==
+				    BATTERY_NOT_DISCONNECTED) {
+				rv = sm5803_flow2_update(
+					chgnum, SM5803_FLOW2_AUTO_ENABLED,
+					MASK_SET);
+				fast_charge_disabled = false;
+			} else {
+				rv = sm5803_flow2_update(
+					chgnum,
+					SM5803_FLOW2_AUTO_TRKL_EN |
+						SM5803_FLOW2_AUTO_PRECHG_EN,
+					MASK_SET);
+				fast_charge_disabled = true;
+			}
 		} else {
 			if (dev_id >= 3) {
 				/* Touch of magic on the primary charger */
@@ -309,11 +410,22 @@ enum ec_error_list sm5803_vbus_sink_enable(int chgnum, int enable)
 		/* Last but not least, enable sinking */
 		rv |= sm5803_flow1_update(chgnum, CHARGER_MODE_SINK, MASK_SET);
 	} else {
-		if (chgnum == CHARGER_PRIMARY)
-			rv |= sm5803_flow2_update(chgnum,
-						  SM5803_FLOW2_AUTO_ENABLED,
+		/*
+		 * Disable sink mode, unless currently sourcing out.
+		 *
+		 * Writes to the FLOW2_AUTO_ENABLED bits below have no effect if
+		 * flow1 is set to an active state, so disable sink mode first
+		 * before making other config changes.
+		 */
+		if (!sm5803_is_sourcing_otg_power(chgnum, chgnum))
+			rv |= sm5803_flow1_update(chgnum, CHARGER_MODE_SINK,
 						  MASK_CLR);
 
+		if (chgnum == CHARGER_PRIMARY)
+			rv |= sm5803_flow2_update(
+				chgnum, SM5803_FLOW2_AUTO_ENABLED, MASK_CLR);
+
+#ifndef CONFIG_CHARGER_SINGLE_CHIP
 		if (chgnum == CHARGER_SECONDARY) {
 			rv |= sm5803_flow1_update(CHARGER_PRIMARY,
 						  SM5803_FLOW1_LINEAR_CHARGE_EN,
@@ -325,32 +437,67 @@ enum ec_error_list sm5803_vbus_sink_enable(int chgnum, int enable)
 			rv |= chg_write8(CHARGER_PRIMARY, SM5803_REG_FLOW3,
 					 regval);
 		}
-
-
-		/* Disable sink mode, unless currently sourcing out */
-		if (!sm5803_is_sourcing_otg_power(chgnum, chgnum))
-			rv |= sm5803_flow1_update(chgnum, CHARGER_MODE_SINK,
-						  MASK_CLR);
+#endif
 	}
 
 	return rv;
+}
+
+/*
+ * Track and store whether we've initialized the charger chips already on this
+ * boot.  This should prevent us from re-running inits after sysjumps.
+ */
+test_export_static bool chip_inited[CHARGER_NUM];
+#define SM5803_SYSJUMP_TAG 0x534D /* SM */
+#define SM5803_HOOK_VERSION 1
 
+static void init_status_preserve(void)
+{
+	system_add_jump_tag(SM5803_SYSJUMP_TAG, SM5803_HOOK_VERSION,
+			    sizeof(chip_inited), &chip_inited);
 }
+DECLARE_HOOK(HOOK_SYSJUMP, init_status_preserve, HOOK_PRIO_DEFAULT);
+
+static void init_status_retrieve(void)
+{
+	const uint8_t *tag_contents;
+	int version, size;
+
+	tag_contents = system_get_jump_tag(SM5803_SYSJUMP_TAG, &version, &size);
+	if (tag_contents && (version == SM5803_HOOK_VERSION) &&
+	    (size == sizeof(chip_inited)))
+		/* Valid init status found, restore before charger chip init */
+		memcpy(&chip_inited, tag_contents, size);
+}
+DECLARE_HOOK(HOOK_INIT, init_status_retrieve, HOOK_PRIO_FIRST);
+
+#ifdef CONFIG_ZEPHYR
+static void init_mutexes(void)
+{
+	int i;
+
+	for (i = 0; i < CHARGER_NUM; i++) {
+		k_mutex_init(&flow1_access_lock[i]);
+		k_mutex_init(&flow2_access_lock[i]);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, init_mutexes, HOOK_PRIO_FIRST);
+#endif
 
 static void sm5803_init(int chgnum)
 {
 	enum ec_error_list rv;
 	int reg;
 	int vbus_mv;
-	const struct battery_info *batt_info;
-	int pre_term;
-	int cells;
 
 	/*
 	 * If a charger is not currently present, disable switching per OCPC
 	 * requirements
 	 */
-	rv = charger_get_vbus_voltage(chgnum, &vbus_mv);
+	/* Reset clocks and enable GPADCs */
+	rv = sm5803_set_active_safe(chgnum);
+
+	rv |= charger_get_vbus_voltage(chgnum, &vbus_mv);
 	if (rv == EC_SUCCESS) {
 		if (vbus_mv < 4000) {
 			/*
@@ -367,6 +514,15 @@ static void sm5803_init(int chgnum)
 		return;
 	}
 
+	/*
+	 * A previous boot already ran inits, safe to return now that we've
+	 * checked i2c communication to the chip and cached Vbus presence
+	 */
+	if (chip_inited[chgnum]) {
+		CPRINTS("%s %d: Already initialized", CHARGER_NAME, chgnum);
+		return;
+	}
+
 	rv |= charger_device_id(&reg);
 	if (reg == 0x02) {
 		/* --- Special register init ---
@@ -427,13 +583,19 @@ static void sm5803_init(int chgnum)
 		rv = main_read8(chgnum, SM5803_REG_PLATFORM, &platform_id);
 		if (rv) {
 			CPRINTS("%s %d: Failed to read platform during init",
-							CHARGER_NAME, chgnum);
+				CHARGER_NAME, chgnum);
 			return;
 		}
 		platform_id &= SM5803_PLATFORM_ID;
 
-		if (platform_id >= 0x0E && platform_id <= 0x16) {
+		if (is_platform_id_3s(platform_id)) {
 			/* 3S Battery inits */
+			/* set 13.3V VBAT_SNSP TH GPADC THRESHOLD*/
+			rv |= meas_write8(chgnum, 0x26,
+					  SM5803_VBAT_SNSP_MAXTH_3S_LEVEL);
+			/* OV_VBAT HW second level (14.1V) */
+			rv |= chg_write8(chgnum, 0x21,
+					 SM5803_VBAT_PWR_MINTH_3S_LEVEL);
 			rv |= main_write8(chgnum, 0x30, 0xC0);
 			rv |= main_write8(chgnum, 0x80, 0x01);
 			rv |= main_write8(chgnum, 0x1A, 0x08);
@@ -471,8 +633,20 @@ static void sm5803_init(int chgnum)
 			rv |= chg_write8(chgnum, 0x33, 0x3C);
 
 			rv |= chg_write8(chgnum, 0x5C, 0x7A);
-		} else if (platform_id >= 0x06 && platform_id <= 0x0D) {
+		} else if (is_platform_id_2s(platform_id)) {
 			/* 2S Battery inits */
+
+			/*
+			 * Set 9V as higher threshold for VBATSNSP_MAX_TH GPADC
+			 * threshold for interrupt generation.
+			 */
+			rv |= meas_write8(chgnum, 0x26,
+					  SM5803_VBAT_SNSP_MAXTH_2S_LEVEL);
+
+			/* Set OV_VBAT HW second level threshold as 9.4V */
+			rv |= chg_write8(chgnum, 0x21,
+					 SM5803_VBAT_PWR_MINTH_2S_LEVEL);
+
 			rv |= main_write8(chgnum, 0x30, 0xC0);
 			rv |= main_write8(chgnum, 0x80, 0x01);
 			rv |= main_write8(chgnum, 0x1A, 0x08);
@@ -528,14 +702,6 @@ static void sm5803_init(int chgnum)
 	reg &= ~(BIT(0) | BIT(1));
 	rv |= main_write8(chgnum, SM5803_REG_REFERENCE, reg);
 
-	/* Set a higher clock speed in case it was lowered for z-state */
-	rv |= main_read8(chgnum, SM5803_REG_CLOCK_SEL, &reg);
-	reg &= ~SM5803_CLOCK_SEL_LOW;
-	rv |= main_write8(chgnum, SM5803_REG_CLOCK_SEL, reg);
-
-	/* Turn on GPADCs to default */
-	rv |= meas_write8(chgnum, SM5803_REG_GPADC_CONFIG1, 0xF3);
-
 	/* Enable Psys DAC */
 	rv |= meas_read8(chgnum, SM5803_REG_PSYS1, &reg);
 	reg |= SM5803_PSYS1_DAC_EN;
@@ -552,35 +718,40 @@ static void sm5803_init(int chgnum)
 	reg &= ~SM5803_PHOT1_IBUS_PHOT_COMP_EN;
 	rv |= chg_write8(chgnum, SM5803_REG_PHOT1, reg);
 
-	if (chgnum != CHARGER_PRIMARY) {
-		/*
-		 * Enable the IBAT_CHG adc in order to calculate
-		 * system resistance.
-		 */
-		rv |= meas_read8(chgnum, SM5803_REG_GPADC_CONFIG1, &reg);
-		reg |= SM5803_GPADCC1_IBAT_CHG_EN;
-		rv |= meas_write8(chgnum, SM5803_REG_GPADC_CONFIG1, reg);
-	}
+	/* Set DPM Voltage to 4200 mv, see b:172173517 */
+	reg = SM5803_VOLTAGE_TO_REG(4200);
+	rv = chg_write8(chgnum, SM5803_REG_DPM_VL_SET_MSB, (reg >> 3));
+	rv |= chg_write8(chgnum, SM5803_REG_DPM_VL_SET_LSB, (reg & 0x7));
 
 	/* Set default input current */
-	reg = SM5803_CURRENT_TO_REG(CONFIG_CHARGER_INPUT_CURRENT)
-		& SM5803_CHG_ILIM_RAW;
+	reg = SM5803_CURRENT_TO_REG(CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT) &
+	      SM5803_CHG_ILIM_RAW;
 	rv |= chg_write8(chgnum, SM5803_REG_CHG_ILIM, reg);
 
 	/* Configure charger insertion interrupts */
 	rv |= main_write8(chgnum, SM5803_REG_INT1_EN, SM5803_INT1_CHG);
 	/* Enable end of charge interrupts for logging */
-	rv |= main_write8(chgnum, SM5803_REG_INT4_EN, SM5803_INT4_CHG_FAIL |
-						      SM5803_INT4_CHG_DONE);
+	rv |= main_write8(chgnum, SM5803_REG_INT4_EN,
+			  SM5803_INT4_CHG_FAIL | SM5803_INT4_CHG_DONE |
+				  SM5803_INT4_OTG_FAIL);
 
-	/* Set TINT interrupts for 360 K and 330 K */
+	/* Set TINT interrupts for higher threshold 360 K */
 	rv |= meas_write8(chgnum, SM5803_REG_TINT_HIGH_TH,
-						SM5803_TINT_HIGH_LEVEL);
+			  SM5803_TINT_HIGH_LEVEL);
+	/*
+	 * Set TINT interrupts for lower threshold to 0 when not
+	 * throttled to prevent trigger interrupts continually
+	 */
 	rv |= meas_write8(chgnum, SM5803_REG_TINT_LOW_TH,
-						SM5803_TINT_LOW_LEVEL);
+			  SM5803_TINT_MIN_LEVEL);
 
-	/* Configure TINT interrupts to fire after thresholds are set */
-	rv |= main_write8(chgnum, SM5803_REG_INT2_EN, SM5803_INT2_TINT);
+	/*
+	 * Configure VBAT_SNSP high and TINT interrupts to fire after
+	 * thresholds are set.
+	 */
+	rv |= main_read8(chgnum, SM5803_REG_INT2_EN, &reg);
+	reg |= SM5803_INT2_VBATSNSP | SM5803_INT2_TINT;
+	rv |= main_write8(chgnum, SM5803_REG_INT2_EN, reg);
 
 	/*
 	 * Configure CHG_ENABLE to only be set through I2C by setting
@@ -589,40 +760,52 @@ static void sm5803_init(int chgnum)
 	rv |= chg_write8(chgnum, SM5803_REG_FLOW2, SM5803_FLOW2_HOST_MODE_EN);
 
 	if (chgnum == CHARGER_PRIMARY) {
-		int ibat_eoc_ma;
+		if (IS_ENABLED(CONFIG_BATTERY)) {
+			const struct battery_info *batt_info;
+			int ibat_eoc_ma;
+			int pre_term;
+			int cells;
+
+			/* Set end of fast charge threshold */
+			batt_info = battery_get_info();
+			ibat_eoc_ma = batt_info->precharge_current - 50;
+			ibat_eoc_ma /= 100;
+			ibat_eoc_ma =
+				CLAMP(ibat_eoc_ma, 0, SM5803_CONF5_IBAT_EOC_TH);
+			rv |= chg_read8(chgnum, SM5803_REG_FAST_CONF5, &reg);
+			reg &= ~SM5803_CONF5_IBAT_EOC_TH;
+			reg |= ibat_eoc_ma;
+			rv |= chg_write8(CHARGER_PRIMARY, SM5803_REG_FAST_CONF5,
+					 reg);
+
+			/* Setup the proper precharge thresholds. */
+			cells = batt_info->voltage_max / 4;
+			pre_term = batt_info->voltage_min / cells;
+			/* Convert to decivolts. */
+			pre_term /= 100;
+			pre_term = CLAMP(pre_term, SM5803_VBAT_PRE_TERM_MIN_DV,
+					 SM5803_VBAT_PRE_TERM_MAX_DV);
+			/* Convert to regval */
+			pre_term -= SM5803_VBAT_PRE_TERM_MIN_DV;
+
+			rv |= chg_read8(chgnum, SM5803_REG_PRE_FAST_CONF_REG1,
+					&reg);
+			reg &= ~SM5803_VBAT_PRE_TERM;
+			reg |= pre_term << SM5803_VBAT_PRE_TERM_SHIFT;
+			rv |= chg_write8(chgnum, SM5803_REG_PRE_FAST_CONF_REG1,
+					 reg);
 
-		/* Set end of fast charge threshold */
-		batt_info = battery_get_info();
-		ibat_eoc_ma = batt_info->precharge_current - 50;
-		ibat_eoc_ma /= 100;
-		ibat_eoc_ma = CLAMP(ibat_eoc_ma, 0, SM5803_CONF5_IBAT_EOC_TH);
-		rv |= chg_read8(chgnum, SM5803_REG_FAST_CONF5, &reg);
-		reg &= ~SM5803_CONF5_IBAT_EOC_TH;
-		reg |= ibat_eoc_ma;
-		rv |= chg_write8(CHARGER_PRIMARY, SM5803_REG_FAST_CONF5, reg);
-
-		/* Setup the proper precharge thresholds. */
-		cells = batt_info->voltage_max / 4;
-		pre_term = batt_info->voltage_min / cells;
-		pre_term /= 100; /* Convert to decivolts. */
-		pre_term = CLAMP(pre_term, SM5803_VBAT_PRE_TERM_MIN_DV,
-				 SM5803_VBAT_PRE_TERM_MAX_DV);
-		pre_term -= SM5803_VBAT_PRE_TERM_MIN_DV; /* Convert to regval */
-
-		rv |= chg_read8(chgnum, SM5803_REG_PRE_FAST_CONF_REG1, &reg);
-		reg &= ~SM5803_VBAT_PRE_TERM;
-		reg |= pre_term << SM5803_VBAT_PRE_TERM_SHIFT;
-		rv |= chg_write8(chgnum, SM5803_REG_PRE_FAST_CONF_REG1, reg);
-
-		/*
-		 * Set up precharge current
-		 * Note it is preferred to under-shoot the precharge current
-		 * requested. Upper bits of this register are read/write 1 to
-		 * clear
-		 */
-		reg = SM5803_CURRENT_TO_REG(batt_info->precharge_current);
-		reg = MIN(reg, SM5803_PRECHG_ICHG_PRE_SET);
-		rv |= chg_write8(chgnum, SM5803_REG_PRECHG, reg);
+			/*
+			 * Set up precharge current
+			 * Note it is preferred to under-shoot the precharge
+			 * current requested. Upper bits of this register are
+			 * read/write 1 to clear
+			 */
+			reg = SM5803_CURRENT_TO_REG(
+				batt_info->precharge_current);
+			reg = MIN(reg, SM5803_PRECHG_ICHG_PRE_SET);
+			rv |= chg_write8(chgnum, SM5803_REG_PRECHG, reg);
+		}
 
 		/*
 		 * Set up BFET alerts
@@ -635,7 +818,7 @@ static void sm5803_init(int chgnum)
 		rv |= meas_write8(chgnum, SM5803_REG_BFET_PWR_MAX_TH, reg);
 		reg = (6000 * 10) / 292;
 		rv |= meas_write8(chgnum, SM5803_REG_BFET_PWR_HWSAFE_MAX_TH,
-				 reg);
+				  reg);
 		rv |= main_read8(chgnum, SM5803_REG_INT3_EN, &reg);
 		reg |= SM5803_INT3_BFET_PWR_LIMIT |
 		       SM5803_INT3_BFET_PWR_HWSAFE_LIMIT;
@@ -652,6 +835,8 @@ static void sm5803_init(int chgnum)
 
 	if (rv)
 		CPRINTS("%s %d: Failed initialization", CHARGER_NAME, chgnum);
+	else
+		chip_inited[chgnum] = true;
 }
 
 static enum ec_error_list sm5803_post_init(int chgnum)
@@ -719,10 +904,9 @@ static void sm5803_disable_runtime_low_power_mode(void)
 			chgnum);
 		return;
 	}
-	/* Set a higher clock speed */
-	rv |= main_read8(chgnum, SM5803_REG_CLOCK_SEL, &reg);
-	reg &= ~SM5803_CLOCK_SEL_LOW;
-	rv |= main_write8(chgnum, SM5803_REG_CLOCK_SEL, reg);
+
+	/* Reset clocks and enable GPADCs */
+	rv = sm5803_set_active_safe(chgnum);
 
 	/* Enable ADC sigma delta */
 	rv |= chg_read8(chgnum, SM5803_REG_CC_CONFIG1, &reg);
@@ -733,9 +917,59 @@ static void sm5803_disable_runtime_low_power_mode(void)
 		CPRINTS("%s %d: Failed to set in disable runtime LPM",
 			CHARGER_NAME, chgnum);
 }
-DECLARE_HOOK(HOOK_USB_PD_CONNECT,
-		sm5803_disable_runtime_low_power_mode,
-		HOOK_PRIO_FIRST);
+DECLARE_HOOK(HOOK_USB_PD_CONNECT, sm5803_disable_runtime_low_power_mode,
+	     HOOK_PRIO_FIRST);
+
+#ifdef CONFIG_BATTERY
+static enum ec_error_list sm5803_enable_linear_charge(int chgnum, bool enable)
+{
+	int rv;
+	int regval;
+	const struct battery_info *batt_info;
+
+	if (enable) {
+		/*
+		 * We need to wait for the BFET enable attempt to complete,
+		 * otherwise we may end up disabling linear charge.
+		 */
+		if (!attempt_bfet_enable)
+			return EC_ERROR_TRY_AGAIN;
+		rv = main_write8(chgnum, 0x1F, 0x1);
+		rv |= test_write8(chgnum, 0x44, 0x20);
+		rv |= main_write8(chgnum, 0x1F, 0);
+
+		/*
+		 * Precharge thresholds have already been set up as a part of
+		 * init, however set fast charge current equal to the precharge
+		 * current in case the battery moves beyond that threshold.
+		 */
+		batt_info = battery_get_info();
+		rv |= sm5803_set_current(CHARGER_PRIMARY,
+					 batt_info->precharge_current);
+
+		/* Enable linear charge mode. */
+		rv |= sm5803_flow1_update(chgnum, SM5803_FLOW1_LINEAR_CHARGE_EN,
+					  MASK_SET);
+		rv |= chg_read8(chgnum, SM5803_REG_FLOW3, &regval);
+		regval |= BIT(6) | BIT(5) | BIT(4);
+		rv |= chg_write8(chgnum, SM5803_REG_FLOW3, regval);
+	} else {
+		rv = sm5803_flow1_update(chgnum, SM5803_FLOW1_LINEAR_CHARGE_EN,
+					 MASK_CLR);
+		rv |= sm5803_flow2_update(chgnum, SM5803_FLOW2_AUTO_ENABLED,
+					  MASK_CLR);
+		rv |= chg_read8(chgnum, SM5803_REG_FLOW3, &regval);
+		regval &= ~(BIT(6) | BIT(5) | BIT(4) |
+			    SM5803_FLOW3_SWITCH_BCK_BST);
+		rv |= chg_write8(chgnum, SM5803_REG_FLOW3, regval);
+		rv |= chg_read8(chgnum, SM5803_REG_SWITCHER_CONF, &regval);
+		regval |= SM5803_SW_BCK_BST_CONF_AUTO;
+		rv |= chg_write8(chgnum, SM5803_REG_SWITCHER_CONF, regval);
+	}
+
+	return rv;
+}
+#endif
 
 static void sm5803_enable_runtime_low_power_mode(void)
 {
@@ -750,10 +984,22 @@ static void sm5803_enable_runtime_low_power_mode(void)
 			chgnum);
 		return;
 	}
-	/* Slow the clock speed */
-	rv |= main_read8(chgnum, SM5803_REG_CLOCK_SEL, &reg);
-	reg |= SM5803_CLOCK_SEL_LOW;
-	rv |= main_write8(chgnum, SM5803_REG_CLOCK_SEL, reg);
+
+	/*
+	 * Turn off GPADCs.
+	 *
+	 * This is only safe to do if the charger is inactive. We ensure that
+	 * they are enabled again in sm5803_set_active_safe() before the charger
+	 * is enabled, and verify here that the charger is not currently active.
+	 */
+	rv |= chg_read8(chgnum, SM5803_REG_FLOW1, &reg);
+	if (rv == 0 && (reg & SM5803_FLOW1_MODE) == CHARGER_MODE_DISABLED) {
+		rv |= meas_write8(chgnum, SM5803_REG_GPADC_CONFIG1, 0);
+		rv |= meas_write8(chgnum, SM5803_REG_GPADC_CONFIG2, 0);
+	} else {
+		CPRINTS("%s %d: FLOW1 %x is active! Not disabling GPADCs",
+			CHARGER_NAME, chgnum, reg);
+	}
 
 	/* Disable ADC sigma delta */
 	rv |= chg_read8(chgnum, SM5803_REG_CC_CONFIG1, &reg);
@@ -768,13 +1014,17 @@ static void sm5803_enable_runtime_low_power_mode(void)
 		rv |= chg_write8(chgnum, SM5803_REG_PHOT1, reg);
 	}
 
+	/* Slow the clock speed */
+	rv |= main_read8(chgnum, SM5803_REG_CLOCK_SEL, &reg);
+	reg |= SM5803_CLOCK_SEL_LOW;
+	rv |= main_write8(chgnum, SM5803_REG_CLOCK_SEL, reg);
+
 	if (rv)
 		CPRINTS("%s %d: Failed to set in enable runtime LPM",
 			CHARGER_NAME, chgnum);
 }
-DECLARE_HOOK(HOOK_USB_PD_DISCONNECT,
-		sm5803_enable_runtime_low_power_mode,
-		HOOK_PRIO_LAST);
+DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, sm5803_enable_runtime_low_power_mode,
+	     HOOK_PRIO_LAST);
 
 void sm5803_disable_low_power_mode(int chgnum)
 {
@@ -789,19 +1039,27 @@ void sm5803_disable_low_power_mode(int chgnum)
 		return;
 	}
 	/* Enable Psys DAC */
-	rv |= meas_read8(chgnum, SM5803_REG_PSYS1, &reg);
+	rv = meas_read8(chgnum, SM5803_REG_PSYS1, &reg);
+	if (rv) {
+		goto err;
+	}
 	reg |= SM5803_PSYS1_DAC_EN;
-	rv |= meas_write8(chgnum, SM5803_REG_PSYS1, reg);
+	rv = meas_write8(chgnum, SM5803_REG_PSYS1, reg);
 
 	/* Enable PROCHOT comparators except Ibus */
 	rv |= chg_read8(chgnum, SM5803_REG_PHOT1, &reg);
+	if (rv) {
+		goto err;
+	}
 	reg |= SM5803_PHOT1_COMPARATOR_EN;
 	reg &= ~SM5803_PHOT1_IBUS_PHOT_COMP_EN;
 	rv |= chg_write8(chgnum, SM5803_REG_PHOT1, reg);
 
-	if (rv)
+err:
+	if (rv) {
 		CPRINTS("%s %d: Failed to set in disable low power mode",
 			CHARGER_NAME, chgnum);
+	}
 }
 
 void sm5803_enable_low_power_mode(int chgnum)
@@ -817,7 +1075,10 @@ void sm5803_enable_low_power_mode(int chgnum)
 		return;
 	}
 	/* Disable Psys DAC */
-	rv |= meas_read8(chgnum, SM5803_REG_PSYS1, &reg);
+	rv = meas_read8(chgnum, SM5803_REG_PSYS1, &reg);
+	if (rv) {
+		goto err;
+	}
 	reg &= ~SM5803_PSYS1_DAC_EN;
 	rv |= meas_write8(chgnum, SM5803_REG_PSYS1, reg);
 
@@ -828,17 +1089,54 @@ void sm5803_enable_low_power_mode(int chgnum)
 	 * called after Vbus has turned on.
 	 */
 	rv |= chg_read8(chgnum, SM5803_REG_PHOT1, &reg);
+	if (rv) {
+		goto err;
+	}
 	reg &= ~SM5803_PHOT1_COMPARATOR_EN;
 	if (pd_is_connected(chgnum))
 		reg |= SM5803_PHOT1_VBUS_MON_EN;
 	rv |= chg_write8(chgnum, SM5803_REG_PHOT1, reg);
 
-
-	if (rv)
+err:
+	if (rv) {
 		CPRINTS("%s %d: Failed to set in enable low power mode",
 			CHARGER_NAME, chgnum);
+	}
 }
 
+/*
+ * Restart charging on the active port, if it's still active and it hasn't
+ * exceeded our maximum number of restarts.
+ */
+void sm5803_restart_charging(void)
+{
+	int act_chg = charge_manager_get_active_charge_port();
+	timestamp_t now = get_time();
+
+	if (act_chg != CHARGE_PORT_NONE && act_chg == active_restart_port) {
+		if (timestamp_expired(failure_tracker[act_chg].time, &now)) {
+			/*
+			 * Enough time has passed since our last failure,
+			 * restart the timing and count from now.
+			 */
+			failure_tracker[act_chg].time.val =
+				now.val + CHARGING_FAILURE_INTERVAL;
+			failure_tracker[act_chg].count = 1;
+
+			sm5803_vbus_sink_enable(act_chg, 1);
+		} else if (++failure_tracker[act_chg].count >
+			   CHARGING_FAILURE_MAX_COUNT) {
+			CPRINTS("%s %d: Exceeded charging failure retries",
+				CHARGER_NAME, act_chg);
+		} else {
+			sm5803_vbus_sink_enable(act_chg, 1);
+		}
+	}
+
+	active_restart_port = CHARGE_PORT_NONE;
+}
+DECLARE_DEFERRED(sm5803_restart_charging);
+
 /*
  * Process interrupt registers and report any Vbus changes.  Alert the AP if the
  * charger has become too hot.
@@ -848,8 +1146,7 @@ void sm5803_handle_interrupt(int chgnum)
 	enum ec_error_list rv;
 	int int_reg, meas_reg;
 	static bool throttled;
-	struct batt_params bp;
-	int act_chg, val;
+	int act_chg;
 
 	/* Note: Interrupt registers are clear on read */
 	rv = main_read8(chgnum, SM5803_REG_INT1_REQ, &int_reg);
@@ -865,13 +1162,12 @@ void sm5803_handle_interrupt(int chgnum)
 			charger_vbus[chgnum] = 0;
 			if (IS_ENABLED(CONFIG_USB_CHARGER))
 				usb_charger_vbus_change(chgnum, 0);
-			board_vbus_present_change();
 		} else {
 			charger_vbus[chgnum] = 1;
 			if (IS_ENABLED(CONFIG_USB_CHARGER))
 				usb_charger_vbus_change(chgnum, 1);
-			board_vbus_present_change();
 		}
+		board_check_extpower();
 	}
 
 	rv = main_read8(chgnum, SM5803_REG_INT2_REQ, &int_reg);
@@ -882,20 +1178,31 @@ void sm5803_handle_interrupt(int chgnum)
 	}
 
 	if (int_reg & SM5803_INT2_TINT) {
-		/*
-		 * Ignore any interrupts from the low threshold when not
-		 * throttled in order to prevent console spam when the
-		 * temperature is holding near the threshold.
-		 */
 		rv = meas_read8(chgnum, SM5803_REG_TINT_MEAS_MSB, &meas_reg);
 		if ((meas_reg <= SM5803_TINT_LOW_LEVEL) && throttled) {
 			throttled = false;
 			throttle_ap(THROTTLE_OFF, THROTTLE_HARD,
-							THROTTLE_SRC_THERMAL);
+				    THROTTLE_SRC_THERMAL);
+			/*
+			 * Set back higher threshold to 360 K and set lower
+			 * threshold to 0.
+			 */
+			rv |= meas_write8(chgnum, SM5803_REG_TINT_LOW_TH,
+					  SM5803_TINT_MIN_LEVEL);
+			rv |= meas_write8(chgnum, SM5803_REG_TINT_HIGH_TH,
+					  SM5803_TINT_HIGH_LEVEL);
 		} else if (meas_reg >= SM5803_TINT_HIGH_LEVEL) {
 			throttled = true;
 			throttle_ap(THROTTLE_ON, THROTTLE_HARD,
-							THROTTLE_SRC_THERMAL);
+				    THROTTLE_SRC_THERMAL);
+			/*
+			 * Set back lower threshold to 330 K and set higher
+			 * threshold to maximum.
+			 */
+			rv |= meas_write8(chgnum, SM5803_REG_TINT_HIGH_TH,
+					  SM5803_TINT_MAX_LEVEL);
+			rv |= meas_write8(chgnum, SM5803_REG_TINT_LOW_TH,
+					  SM5803_TINT_LOW_LEVEL);
 		}
 		/*
 		 * If the interrupt came in and we're not currently throttling
@@ -904,6 +1211,72 @@ void sm5803_handle_interrupt(int chgnum)
 		 */
 	}
 
+	if (int_reg & SM5803_INT2_VBATSNSP) {
+		int meas_volt;
+		uint32_t platform_id;
+
+		rv = main_read8(chgnum, SM5803_REG_PLATFORM, &platform_id);
+		if (rv) {
+			CPRINTS("%s %d: Failed to read platform in interrupt",
+				CHARGER_NAME, chgnum);
+			return;
+		}
+		platform_id &= SM5803_PLATFORM_ID;
+		act_chg = charge_manager_get_active_charge_port();
+		rv = meas_read8(CHARGER_PRIMARY, SM5803_REG_VBATSNSP_MEAS_MSB,
+				&meas_reg);
+		if (rv)
+			return;
+		meas_volt = meas_reg << 2;
+		rv = meas_read8(CHARGER_PRIMARY, SM5803_REG_VBATSNSP_MEAS_LSB,
+				&meas_reg);
+		if (rv)
+			return;
+		meas_volt |= meas_reg & 0x03;
+		rv = meas_read8(CHARGER_PRIMARY, SM5803_REG_VBATSNSP_MAX_TH,
+				&meas_reg);
+		if (rv)
+			return;
+
+		if (is_platform_id_2s(platform_id)) {
+			/* 2S Battery */
+			CPRINTS("%s %d : VBAT_SNSP_HIGH_TH: %d mV ! - "
+				"VBAT %d mV",
+				CHARGER_NAME, CHARGER_PRIMARY,
+				meas_reg * 408 / 10, meas_volt * 102 / 10);
+		}
+
+		if (is_platform_id_3s(platform_id)) {
+			/* 3S Battery */
+			CPRINTS("%s %d : VBAT_SNSP_HIGH_TH: %d mV ! "
+				"- VBAT %d mV",
+				CHARGER_NAME, CHARGER_PRIMARY,
+				meas_reg * 616 / 10, meas_volt * 154 / 10);
+		}
+
+		/* Set Vbat Threshold to Max value to re-arm the interrupt */
+		rv = meas_write8(CHARGER_PRIMARY, SM5803_REG_VBATSNSP_MAX_TH,
+				 0xFF);
+
+		/* Disable battery charge */
+		rv |= sm5803_flow1_update(chgnum, SM5803_FLOW1_MODE, MASK_CLR);
+		if (is_platform_id_2s(platform_id)) {
+			/* 2S battery: set VBAT_SENSP TH 9V */
+			rv |= meas_write8(CHARGER_PRIMARY,
+					  SM5803_REG_VBATSNSP_MAX_TH,
+					  SM5803_VBAT_SNSP_MAXTH_2S_LEVEL);
+		}
+		if (is_platform_id_3s(platform_id)) {
+			/* 3S battery: set VBAT_SENSP TH 13.3V */
+			rv |= meas_write8(CHARGER_PRIMARY,
+					  SM5803_REG_VBATSNSP_MAX_TH,
+					  SM5803_VBAT_SNSP_MAXTH_3S_LEVEL);
+		}
+
+		active_restart_port = act_chg;
+		hook_call_deferred(&sm5803_restart_charging_data, 1 * SECOND);
+	}
+
 	/* TODO(b/159376384): Take action on fatal BFET power alert. */
 	rv = main_read8(chgnum, SM5803_REG_INT3_REQ, &int_reg);
 	if (rv) {
@@ -912,13 +1285,17 @@ void sm5803_handle_interrupt(int chgnum)
 		return;
 	}
 
-	if ((int_reg & SM5803_INT3_BFET_PWR_LIMIT) ||
-	    (int_reg & SM5803_INT3_BFET_PWR_HWSAFE_LIMIT)) {
+	if (IS_ENABLED(CONFIG_BATTERY) &&
+	    ((int_reg & SM5803_INT3_BFET_PWR_LIMIT) ||
+	     (int_reg & SM5803_INT3_BFET_PWR_HWSAFE_LIMIT))) {
+		struct batt_params bp;
+		int val;
+
 		battery_get_params(&bp);
 		act_chg = charge_manager_get_active_charge_port();
 		CPRINTS("%s BFET power limit reached! (%s)", CHARGER_NAME,
 			(int_reg & SM5803_INT3_BFET_PWR_LIMIT) ? "warn" :
-			"FATAL");
+								 "FATAL");
 		CPRINTS("\tVbat: %dmV", bp.voltage);
 		CPRINTS("\tIbat: %dmA", bp.current);
 		charger_get_voltage(act_chg, &val);
@@ -935,17 +1312,70 @@ void sm5803_handle_interrupt(int chgnum)
 		return;
 	}
 
-	if (int_reg & SM5803_INT4_CHG_FAIL)
-		CPRINTS("%s %d: CHG_FAIL_INT fired!!!", CHARGER_NAME, chgnum);
+	if (int_reg & SM5803_INT4_CHG_FAIL) {
+		int status_reg;
+
+		act_chg = charge_manager_get_active_charge_port();
+		chg_read8(chgnum, SM5803_REG_STATUS_CHG_REG, &status_reg);
+		CPRINTS("%s %d: CHG_FAIL_INT fired.  Status 0x%02x",
+			CHARGER_NAME, chgnum, status_reg);
+
+		/* Write 1 to clear status interrupts */
+		chg_write8(chgnum, SM5803_REG_STATUS_CHG_REG, status_reg);
+
+		/*
+		 * If a survivable fault happened, re-start sinking on the
+		 * active charger after an appropriate delay.
+		 */
+		if (status_reg & SM5803_STATUS_CHG_OV_ITEMP) {
+			active_restart_port = act_chg;
+			hook_call_deferred(&sm5803_restart_charging_data,
+					   30 * SECOND);
+		} else if ((status_reg & SM5803_STATUS_CHG_OV_VBAT) &&
+			   act_chg == CHARGER_PRIMARY) {
+			active_restart_port = act_chg;
+			hook_call_deferred(&sm5803_restart_charging_data,
+					   1 * SECOND);
+		}
+	}
 
 	if (int_reg & SM5803_INT4_CHG_DONE)
 		CPRINTS("%s %d: CHG_DONE_INT fired!!!", CHARGER_NAME, chgnum);
+
+	if (int_reg & SM5803_INT4_OTG_FAIL) {
+		int status_reg;
+
+		/*
+		 * Gather status to detect if this was overcurrent
+		 *
+		 * Note: a status of 0 with this interrupt also indicates an
+		 * overcurrent (see b/170517117)
+		 */
+		chg_read8(chgnum, SM5803_REG_STATUS_DISCHG, &status_reg);
+		CPRINTS("%s %d: OTG_FAIL_INT fired. Status 0x%02x",
+			CHARGER_NAME, chgnum, status_reg);
+		if ((status_reg == 0) ||
+		    (status_reg == SM5803_STATUS_DISCHG_VBUS_SHORT)) {
+			pd_handle_overcurrent(chgnum);
+		}
+
+		/*
+		 * Clear source mode here when status is 0, since OTG disable
+		 * will detect us as sinking in this failure case.
+		 */
+		if (status_reg == 0)
+			rv = sm5803_flow1_update(
+				chgnum,
+				CHARGER_MODE_SOURCE |
+					SM5803_FLOW1_DIRECTCHG_SRC_EN,
+				MASK_CLR);
+	}
 }
 
 static void sm5803_irq_deferred(void)
 {
 	int i;
-	uint32_t pending = deprecated_atomic_read_clear(&irq_pending);
+	uint32_t pending = atomic_clear(&irq_pending);
 
 	for (i = 0; i < CHARGER_NUM; i++)
 		if (BIT(i) & pending)
@@ -955,7 +1385,7 @@ DECLARE_DEFERRED(sm5803_irq_deferred);
 
 void sm5803_interrupt(int chgnum)
 {
-	deprecated_atomic_or(&irq_pending, BIT(chgnum));
+	atomic_or(&irq_pending, BIT(chgnum));
 	hook_call_deferred(&sm5803_irq_deferred_data, 0);
 }
 
@@ -970,7 +1400,6 @@ static enum ec_error_list sm5803_get_dev_id(int chgnum, int *id)
 		*id = dev_id;
 
 	return rv;
-
 }
 
 static const struct charger_info *sm5803_get_info(int chgnum)
@@ -990,7 +1419,6 @@ static enum ec_error_list sm5803_get_status(int chgnum, int *status)
 	if (rv)
 		return rv;
 
-
 	if ((reg & SM5803_FLOW1_MODE) == CHARGER_MODE_DISABLED &&
 	    !(reg & SM5803_FLOW1_LINEAR_CHARGE_EN))
 		*status |= CHARGER_CHARGE_INHIBITED;
@@ -1011,18 +1439,18 @@ static enum ec_error_list sm5803_set_mode(int chgnum, int mode)
 	return rv;
 }
 
-static enum ec_error_list sm5803_get_current(int chgnum, int *current)
+static enum ec_error_list sm5803_get_actual_current(int chgnum, int *current)
 {
 	enum ec_error_list rv;
 	int reg;
 	int curr;
 
-	rv = meas_read8(chgnum, SM5803_REG_IBAT_CHG_MEAS_MSB, &reg);
+	rv = meas_read8(chgnum, SM5803_REG_IBAT_CHG_AVG_MEAS_MSB, &reg);
 	if (rv)
 		return rv;
 	curr = reg << 2;
 
-	rv = meas_read8(chgnum, SM5803_REG_IBAT_CHG_MEAS_LSB, &reg);
+	rv = meas_read8(chgnum, SM5803_REG_IBAT_CHG_AVG_MEAS_LSB, &reg);
 	if (rv)
 		return rv;
 	curr |= reg & SM5803_IBAT_CHG_MEAS_LSB;
@@ -1032,11 +1460,38 @@ static enum ec_error_list sm5803_get_current(int chgnum, int *current)
 	return EC_SUCCESS;
 }
 
+static enum ec_error_list sm5803_get_current(int chgnum, int *current)
+{
+	enum ec_error_list rv;
+	int reg;
+
+	rv = chg_read8(chgnum, SM5803_REG_FAST_CONF4, &reg);
+	if (rv)
+		return rv;
+
+	reg &= SM5803_CONF4_ICHG_FAST;
+	*current = SM5803_REG_TO_CURRENT(reg);
+
+	return EC_SUCCESS;
+}
+
 static enum ec_error_list sm5803_set_current(int chgnum, int current)
 {
 	enum ec_error_list rv;
 	int reg;
 
+	if (current == 0) {
+		/*
+		 * Per Silicon Mitus, setting the fast charge current limit to 0
+		 * causes "much unstable". This normally happens when the
+		 * battery is fully charged (so we don't expect fast charge to
+		 * be in use): turn 0 into the minimum nonzero value so we
+		 * avoid setting this register to 0 but still make the requested
+		 * current as small as possible.
+		 */
+		current = SM5803_REG_TO_CURRENT(1);
+	}
+
 	rv = chg_read8(chgnum, SM5803_REG_FAST_CONF4, &reg);
 	if (rv)
 		return rv;
@@ -1048,18 +1503,18 @@ static enum ec_error_list sm5803_set_current(int chgnum, int current)
 	return rv;
 }
 
-static enum ec_error_list sm5803_get_voltage(int chgnum, int *voltage)
+static enum ec_error_list sm5803_get_actual_voltage(int chgnum, int *voltage)
 {
 	enum ec_error_list rv;
 	int reg;
 	int volt_bits;
 
-	rv = meas_read8(chgnum, SM5803_REG_VSYS_MEAS_MSB, &reg);
+	rv = meas_read8(chgnum, SM5803_REG_VSYS_AVG_MEAS_MSB, &reg);
 	if (rv)
 		return rv;
 	volt_bits = reg << 2;
 
-	rv = meas_read8(chgnum, SM5803_REG_VSYS_MEAS_LSB, &reg);
+	rv = meas_read8(chgnum, SM5803_REG_VSYS_AVG_MEAS_LSB, &reg);
 	if (rv)
 		return rv;
 	volt_bits |= reg & 0x3;
@@ -1070,11 +1525,29 @@ static enum ec_error_list sm5803_get_voltage(int chgnum, int *voltage)
 	return EC_SUCCESS;
 }
 
+static enum ec_error_list sm5803_get_voltage(int chgnum, int *voltage)
+{
+	enum ec_error_list rv;
+	int regval;
+	int v;
+
+	rv = chg_read8(chgnum, SM5803_REG_VBAT_FAST_MSB, &regval);
+	v = regval << 3;
+	rv |= chg_read8(chgnum, SM5803_REG_VBAT_FAST_LSB, &regval);
+	v |= (regval & 0x3);
+
+	*voltage = SM5803_REG_TO_VOLTAGE(v);
+
+	if (rv)
+		return EC_ERROR_UNKNOWN;
+
+	return EC_SUCCESS;
+}
+
 static enum ec_error_list sm5803_set_voltage(int chgnum, int voltage)
 {
 	enum ec_error_list rv;
 	int regval;
-	static int attempt_bfet_enable;
 
 	regval = SM5803_VOLTAGE_TO_REG(voltage);
 
@@ -1087,6 +1560,15 @@ static enum ec_error_list sm5803_set_voltage(int chgnum, int voltage)
 	rv |= chg_write8(chgnum, SM5803_REG_VBAT_FAST_MSB, (regval >> 3));
 	rv |= chg_write8(chgnum, SM5803_REG_VBAT_FAST_LSB, (regval & 0x7));
 
+	/* Once battery is connected, set up fast charge enable */
+	if (fast_charge_disabled && chgnum == CHARGER_PRIMARY &&
+	    IS_ENABLED(CONFIG_BATTERY) &&
+	    battery_get_disconnect_state() == BATTERY_NOT_DISCONNECTED) {
+		rv = sm5803_flow2_update(chgnum, SM5803_FLOW2_AUTO_ENABLED,
+					 MASK_SET);
+		fast_charge_disabled = false;
+	}
+
 	if (IS_ENABLED(CONFIG_OCPC) && chgnum != CHARGER_PRIMARY) {
 		/*
 		 * Check to see if the BFET is enabled.  If not, enable it by
@@ -1107,6 +1589,9 @@ static enum ec_error_list sm5803_set_voltage(int chgnum, int voltage)
 			attempt_bfet_enable = 1;
 			sm5803_vbus_sink_enable(chgnum, 1);
 		}
+		/* There's no need to attempt it if the BFET's already on. */
+		if (regval & SM5803_BATFET_ON)
+			attempt_bfet_enable = 1;
 	}
 
 	return rv;
@@ -1127,12 +1612,20 @@ static enum ec_error_list sm5803_discharge_on_ac(int chgnum, int enable)
 }
 
 static enum ec_error_list sm5803_get_vbus_voltage(int chgnum, int port,
-						   int *voltage)
+						  int *voltage)
 {
 	enum ec_error_list rv;
 	int reg;
 	int volt_bits;
 
+	rv = meas_read8(chgnum, SM5803_REG_GPADC_CONFIG1, &reg);
+	if (rv)
+		return rv;
+	if ((reg & SM5803_GPADCC1_VBUS_EN) == 0) {
+		/* VBUS ADC is currently disabled */
+		return EC_ERROR_NOT_POWERED;
+	}
+
 	rv = meas_read8(chgnum, SM5803_REG_VBUS_MEAS_MSB, &reg);
 	if (rv)
 		return rv;
@@ -1148,8 +1641,56 @@ static enum ec_error_list sm5803_get_vbus_voltage(int chgnum, int port,
 	return rv;
 }
 
-static enum ec_error_list sm5803_set_input_current(int chgnum,
-						   int input_current)
+bool sm5803_check_vbus_level(int chgnum, enum vbus_level level)
+{
+	int rv, vbus_voltage;
+
+	/*
+	 * Analog reading of VBUS is more accurate and helps reliability when
+	 * doing power role swaps, but if the charger is in LPM with the GPADCs
+	 * disabled then the reading won't update.
+	 *
+	 * Digital VBUS presence (with transitions flagged by STATUS1_CHG_DET
+	 * interrupt) still works when GPADCs are off, and shouldn't otherwise
+	 * impact performance because the GPADCs should be enabled in any
+	 * situation where we're doing a PRS.
+	 */
+	rv = sm5803_get_vbus_voltage(chgnum, chgnum, &vbus_voltage);
+	if (rv == EC_ERROR_NOT_POWERED) {
+		/* VBUS ADC is disabled, use digital presence */
+		switch (level) {
+		case VBUS_PRESENT:
+			return sm5803_is_vbus_present(chgnum);
+		case VBUS_SAFE0V:
+		case VBUS_REMOVED:
+			return !sm5803_is_vbus_present(chgnum);
+		default:
+			CPRINTS("%s: unrecognized vbus_level value: %d",
+				__func__, level);
+			return false;
+		}
+	}
+	if (rv != EC_SUCCESS) {
+		/* Unhandled communication error; assume unsatisfied */
+		return false;
+	}
+
+	switch (level) {
+	case VBUS_PRESENT:
+		return vbus_voltage > PD_V_SAFE5V_MIN;
+	case VBUS_SAFE0V:
+		return vbus_voltage < PD_V_SAFE0V_MAX;
+	case VBUS_REMOVED:
+		return vbus_voltage < PD_V_SINK_DISCONNECT_MAX;
+	default:
+		CPRINTS("%s: unrecognized vbus_level value: %d", __func__,
+			level);
+		return false;
+	}
+}
+
+static enum ec_error_list sm5803_set_input_current_limit(int chgnum,
+							 int input_current)
 {
 	int reg;
 
@@ -1158,6 +1699,20 @@ static enum ec_error_list sm5803_set_input_current(int chgnum,
 	return chg_write8(chgnum, SM5803_REG_CHG_ILIM, reg);
 }
 
+static enum ec_error_list sm5803_get_input_current_limit(int chgnum,
+							 int *input_current)
+{
+	int rv;
+	int val;
+
+	rv = chg_read8(chgnum, SM5803_REG_CHG_ILIM, &val);
+	if (rv)
+		return rv;
+
+	*input_current = SM5803_REG_TO_CURRENT(val & SM5803_CHG_ILIM_RAW);
+	return rv;
+}
+
 static enum ec_error_list sm5803_get_input_current(int chgnum,
 						   int *input_current)
 {
@@ -1198,6 +1753,52 @@ static enum ec_error_list sm5803_get_option(int chgnum, int *option)
 	return rv;
 }
 
+enum ec_error_list sm5803_is_acok(int chgnum, bool *acok)
+{
+	int rv;
+	int reg, vbus_mv;
+
+	rv = main_read8(chgnum, SM5803_REG_STATUS1, &reg);
+
+	if (rv)
+		return rv;
+
+	/* If we're not sinking, then AC can't be OK. */
+	if (!(reg & SM5803_STATUS1_CHG_DET)) {
+		*acok = false;
+		return EC_SUCCESS;
+	}
+
+	/*
+	 * Okay, we're sinking. Check that VBUS has some voltage. This
+	 * should indicate that the path is good.
+	 */
+	rv = charger_get_vbus_voltage(chgnum, &vbus_mv);
+
+	if (rv)
+		return rv;
+
+	/* Assume that ACOK would be asserted if VBUS is higher than ~4V. */
+	*acok = vbus_mv >= 4000;
+
+	return EC_SUCCESS;
+}
+
+static enum ec_error_list sm5803_is_input_current_limit_reached(int chgnum,
+								bool *reached)
+{
+	enum ec_error_list rv;
+	int reg;
+
+	rv = chg_read8(chgnum, SM5803_REG_LOG2, &reg);
+	if (rv)
+		return rv;
+
+	*reached = (reg & SM5803_ISOLOOP_ON) ? true : false;
+
+	return EC_SUCCESS;
+}
+
 static enum ec_error_list sm5803_set_option(int chgnum, int option)
 {
 	enum ec_error_list rv;
@@ -1236,13 +1837,13 @@ static enum ec_error_list sm5803_set_otg_current_voltage(int chgnum,
 
 	reg &= ~SM5803_DISCH_CONF5_CLS_LIMIT;
 	reg |= MIN((output_current / SM5803_CLS_CURRENT_STEP),
-						SM5803_DISCH_CONF5_CLS_LIMIT);
+		   SM5803_DISCH_CONF5_CLS_LIMIT);
 	rv |= chg_write8(chgnum, SM5803_REG_DISCH_CONF5, reg);
 
-	reg = SM5803_VOLTAGE_TO_REG(output_voltage);
+	reg = MAX(SM5803_VOLTAGE_TO_REG(output_voltage), 0);
 	rv = chg_write8(chgnum, SM5803_REG_VPWR_MSB, (reg >> 3));
 	rv |= chg_write8(chgnum, SM5803_REG_DISCH_CONF2,
-					reg & SM5803_DISCH_CONF5_VPWR_LSB);
+			 reg & SM5803_DISCH_CONF5_VPWR_LSB);
 
 	return rv;
 }
@@ -1250,11 +1851,16 @@ static enum ec_error_list sm5803_set_otg_current_voltage(int chgnum,
 static enum ec_error_list sm5803_enable_otg_power(int chgnum, int enabled)
 {
 	enum ec_error_list rv;
-	int reg;
+	int reg, status;
 
 	if (enabled) {
 		int selected_current;
 
+		rv = sm5803_set_active_safe(chgnum);
+		if (rv) {
+			return rv;
+		}
+
 		rv = chg_read8(chgnum, SM5803_REG_ANA_EN1, &reg);
 		if (rv)
 			return rv;
@@ -1263,6 +1869,11 @@ static enum ec_error_list sm5803_enable_otg_power(int chgnum, int enabled)
 		reg &= ~SM5803_ANA_EN1_CLS_DISABLE;
 		rv = chg_write8(chgnum, SM5803_REG_ANA_EN1, reg);
 
+		/* Disable ramps on current set in discharge */
+		rv |= chg_read8(chgnum, SM5803_REG_DISCH_CONF6, &reg);
+		reg |= SM5803_DISCH_CONF6_RAMPS_DIS;
+		rv |= chg_write8(chgnum, SM5803_REG_DISCH_CONF6, reg);
+
 		/*
 		 * In order to ensure the Vbus output doesn't overshoot too
 		 * much, turn the starting voltage down to 4.8 V and ramp up
@@ -1273,7 +1884,7 @@ static enum ec_error_list sm5803_enable_otg_power(int chgnum, int enabled)
 			return rv;
 
 		selected_current = (reg & SM5803_DISCH_CONF5_CLS_LIMIT) *
-			SM5803_CLS_CURRENT_STEP;
+				   SM5803_CLS_CURRENT_STEP;
 		sm5803_set_otg_current_voltage(chgnum, selected_current, 4800);
 
 		/*
@@ -1281,28 +1892,49 @@ static enum ec_error_list sm5803_enable_otg_power(int chgnum, int enabled)
 		 *	   DIRECTCHG_SOURCE_EN - enable current loop
 		 *	   (for designs with no external Vbus FET)
 		 */
-		rv = sm5803_flow1_update(chgnum, CHARGER_MODE_SOURCE |
-					 SM5803_FLOW1_DIRECTCHG_SRC_EN,
+		rv = sm5803_flow1_update(chgnum,
+					 CHARGER_MODE_SOURCE |
+						 SM5803_FLOW1_DIRECTCHG_SRC_EN,
 					 MASK_SET);
 		usleep(4000);
 
 		sm5803_set_otg_current_voltage(chgnum, selected_current, 5000);
 	} else {
+		/* Always clear out discharge status before clearing FLOW1 */
+		rv = chg_read8(chgnum, SM5803_REG_STATUS_DISCHG, &status);
+		if (rv)
+			return rv;
+
+		if (status)
+			CPRINTS("%s %d: Discharge failure 0x%02x", CHARGER_NAME,
+				chgnum, status);
+
+		rv |= chg_write8(chgnum, SM5803_REG_STATUS_DISCHG, status);
+
+		/* Re-enable ramps on current set in discharge */
+		rv |= chg_read8(chgnum, SM5803_REG_DISCH_CONF6, &reg);
+		reg &= ~SM5803_DISCH_CONF6_RAMPS_DIS;
+		rv |= chg_write8(chgnum, SM5803_REG_DISCH_CONF6, reg);
+
 		/*
 		 * PD tasks will always turn off previous sourcing on init.
 		 * Protect ourselves from brown out on init by checking if we're
 		 * sinking right now.  The init process should only leave sink
 		 * mode enabled if a charger is plugged in; otherwise it's
 		 * expected to be 0.
+		 *
+		 * Always clear out sourcing if the previous source-out failed.
 		 */
-		rv = chg_read8(chgnum, SM5803_REG_FLOW1, &reg);
+		rv |= chg_read8(chgnum, SM5803_REG_FLOW1, &reg);
 		if (rv)
 			return rv;
 
-		if ((reg & SM5803_FLOW1_MODE) != CHARGER_MODE_SINK)
-			rv = sm5803_flow1_update(chgnum, CHARGER_MODE_SOURCE |
-						 SM5803_FLOW1_DIRECTCHG_SRC_EN,
-						 MASK_CLR);
+		if ((reg & SM5803_FLOW1_MODE) != CHARGER_MODE_SINK || status)
+			rv = sm5803_flow1_update(
+				chgnum,
+				CHARGER_MODE_SOURCE |
+					SM5803_FLOW1_DIRECTCHG_SRC_EN,
+				MASK_CLR);
 	}
 
 	return rv;
@@ -1329,7 +1961,6 @@ static enum ec_error_list sm5803_set_vsys_compensation(int chgnum,
 						       int current_ma,
 						       int voltage_mv)
 {
-
 	int rv;
 	int regval;
 	int r;
@@ -1337,7 +1968,7 @@ static enum ec_error_list sm5803_set_vsys_compensation(int chgnum,
 	/* Set IR drop compensation */
 	r = ocpc->combined_rsys_rbatt_mo * 100 / 167; /* 1.67mOhm steps */
 	r = MAX(0, r);
-	rv = chg_write8(chgnum, SM5803_REG_IR_COMP2, r & 0x7F);
+	rv = chg_write8(chgnum, SM5803_REG_IR_COMP2, r & 0xFF);
 	rv |= chg_read8(chgnum, SM5803_REG_IR_COMP1, &regval);
 	regval &= ~SM5803_IR_COMP_RES_SET_MSB;
 	r = r >> 8; /* Bits 9:8 */
@@ -1351,15 +1982,57 @@ static enum ec_error_list sm5803_set_vsys_compensation(int chgnum,
 	return EC_ERROR_UNIMPLEMENTED;
 }
 
+/* Hardware current ramping (aka DPM: Dynamic Power Management) */
+
+#ifdef CONFIG_CHARGE_RAMP_HW
+static enum ec_error_list sm5803_set_hw_ramp(int chgnum, int enable)
+{
+	enum ec_error_list rv;
+	int reg;
+
+	rv = chg_read8(chgnum, SM5803_REG_CHG_MON_REG, &reg);
+
+	if (enable)
+		reg |= SM5803_DPM_LOOP_EN;
+	else
+		reg &= ~SM5803_DPM_LOOP_EN;
+
+	rv |= chg_write8(chgnum, SM5803_REG_CHG_MON_REG, reg);
+
+	return rv;
+}
+
+static int sm5803_ramp_is_stable(int chgnum)
+{
+	/*
+	 * There is no way to read current limit that the ramp has
+	 * settled on with sm5803, so we don't consider the ramp stable,
+	 * because we never know what the stable limit is.
+	 */
+	return 0;
+}
+
+static int sm5803_ramp_is_detected(int chgnum)
+{
+	return 1;
+}
+
+static int sm5803_ramp_get_current_limit(int chgnum)
+{
+	int rv;
+	int input_current = 0;
+
+	rv = sm5803_get_input_current_limit(chgnum, &input_current);
+
+	return rv ? -1 : input_current;
+}
+#endif /* CONFIG_CHARGE_RAMP_HW */
+
 #ifdef CONFIG_CMD_CHARGER_DUMP
-static int command_sm5803_dump(int argc, char **argv)
+static void command_sm5803_dump(int chgnum)
 {
 	int reg;
 	int regval;
-	int chgnum = 0;
-
-	if (argc > 1)
-		chgnum = atoi(argv[1]);
 
 	/* Dump base regs */
 	ccprintf("BASE regs\n");
@@ -1393,12 +2066,31 @@ static int command_sm5803_dump(int argc, char **argv)
 			watchdog_reload();
 		}
 	}
+}
+#endif /* CONFIG_CMD_CHARGER_DUMP */
+
+static enum ec_error_list sm5803_get_battery_cells(int chgnum, int *cells)
+{
+	enum ec_error_list rv;
+	uint32_t platform_id;
+
+	rv = main_read8(chgnum, SM5803_REG_PLATFORM, &platform_id);
+	if (rv)
+		return rv;
+
+	platform_id &= SM5803_PLATFORM_ID;
+	if (is_platform_id_2s(platform_id))
+		*cells = 2;
+	else if (is_platform_id_3s(platform_id))
+		*cells = 3;
+	else {
+		*cells = -1;
+
+		return EC_ERROR_UNKNOWN;
+	}
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(charger_dump, command_sm5803_dump,
-			"charger_dump [chgnum]", "Dumps SM5803 registers");
-#endif /* CONFIG_CMD_CHARGER_DUMP */
 
 const struct charger_drv sm5803_drv = {
 	.init = &sm5803_init,
@@ -1406,13 +2098,16 @@ const struct charger_drv sm5803_drv = {
 	.get_info = &sm5803_get_info,
 	.get_status = &sm5803_get_status,
 	.set_mode = &sm5803_set_mode,
+	.get_actual_current = &sm5803_get_actual_current,
 	.get_current = &sm5803_get_current,
 	.set_current = &sm5803_set_current,
+	.get_actual_voltage = &sm5803_get_actual_voltage,
 	.get_voltage = &sm5803_get_voltage,
 	.set_voltage = &sm5803_set_voltage,
 	.discharge_on_ac = &sm5803_discharge_on_ac,
 	.get_vbus_voltage = &sm5803_get_vbus_voltage,
-	.set_input_current = &sm5803_set_input_current,
+	.set_input_current_limit = &sm5803_set_input_current_limit,
+	.get_input_current_limit = &sm5803_get_input_current_limit,
 	.get_input_current = &sm5803_get_input_current,
 	.device_id = &sm5803_get_dev_id,
 	.get_option = &sm5803_get_option,
@@ -1421,4 +2116,18 @@ const struct charger_drv sm5803_drv = {
 	.enable_otg_power = &sm5803_enable_otg_power,
 	.is_sourcing_otg_power = &sm5803_is_sourcing_otg_power,
 	.set_vsys_compensation = &sm5803_set_vsys_compensation,
+	.is_icl_reached = &sm5803_is_input_current_limit_reached,
+#ifdef CONFIG_BATTERY
+	.enable_linear_charge = &sm5803_enable_linear_charge,
+#endif
+#ifdef CONFIG_CHARGE_RAMP_HW
+	.set_hw_ramp = &sm5803_set_hw_ramp,
+	.ramp_is_stable = &sm5803_ramp_is_stable,
+	.ramp_is_detected = &sm5803_ramp_is_detected,
+	.ramp_get_current_limit = &sm5803_ramp_get_current_limit,
+#endif
+#ifdef CONFIG_CMD_CHARGER_DUMP
+	.dump_registers = &command_sm5803_dump,
+#endif
+	.get_battery_cells = &sm5803_get_battery_cells,
 };
diff --git a/driver/charger/sm5803.h b/driver/charger/sm5803.h
index a6b3d6aaa7..5b6d7db662 100644
--- a/driver/charger/sm5803.h
+++ b/driver/charger/sm5803.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,90 +8,96 @@
 #ifndef __CROS_EC_SM5803_H
 #define __CROS_EC_SM5803_H
 
+#include "common.h"
+#include "usb_pd_tcpm.h"
+
 /* Note: configure charger struct with CHARGER_FLAGS */
-#define SM5803_ADDR_MAIN_FLAGS		0x30
-#define SM5803_ADDR_MEAS_FLAGS		0x31
-#define SM5803_ADDR_CHARGER_FLAGS	0x32
-#define SM5803_ADDR_TEST_FLAGS		0x37
+#define SM5803_ADDR_MAIN_FLAGS 0x30
+#define SM5803_ADDR_MEAS_FLAGS 0x31
+#define SM5803_ADDR_CHARGER_FLAGS 0x32
+#define SM5803_ADDR_TEST_FLAGS 0x37
 
 /* Main registers (address 0x30) */
 
-#define SM5803_REG_CHIP_ID		0x00
-
-#define SM5803_REG_STATUS1		0x01
-#define SM5803_STATUS1_VSYS_OK		BIT(0)
-#define SM5803_STATUS1_VPWR_OK		BIT(1)
-#define SM5803_STATUS1_VBUS_UVL		BIT(3)
-#define SM5803_STATUS1_VBUS_SHORT	BIT(4)
-#define SM5803_STATUS1_VBUS_OVH		BIT(5)
-#define SM5803_STATUS1_CHG_DET		BIT(6)
-#define SM5803_STATUS1_BAT_DET		BIT(7)
-
-#define SM5803_REG_STATUS2		0x02
-#define SM5803_STATUS2_BAT_DET_FG	BIT(1)
-#define SM5803_STATUS2_VBAT_SHORT	BIT(0)
-
-#define SM5803_REG_INT1_REQ			0x05
-#define SM5803_REG_INT1_EN			0x0A
-#define SM5803_INT1_VBUS_PWR_HWSAFE_LIMIT	BIT(0)
-#define SM5803_INT1_CHG				BIT(2)
-#define SM5803_INT1_BAT				BIT(3)
-#define SM5803_INT1_CLS_OC			BIT(4)
-#define SM5803_INT1_SLV_DET			BIT(5)
-#define SM5803_INT1_SWL_DISCH			BIT(6)
-#define SM5803_INT1_PREREG			BIT(7)
-
-#define SM5803_REG_INT2_REQ		0x06
-#define SM5803_REG_INT2_EN		0x0B
-#define SM5803_INT2_VBATSNSP		BIT(0)
-#define SM5803_INT2_IBAT_DISCHG		BIT(1)
-#define SM5803_INT2_IBAT_CHG		BIT(2)
-#define SM5803_INT2_IBUS		BIT(3)
-#define SM5803_INT2_VBUS		BIT(4)
-#define SM5803_INT2_VCHGPWR		BIT(5)
-#define SM5803_INT2_VSYS		BIT(6)
-#define SM5803_INT2_TINT		BIT(7)
-
-#define SM5803_REG_INT3_REQ			0x07
-#define SM5803_REG_INT3_EN			0x0C
-#define SM5803_INT3_GPADC0			BIT(0)
-#define SM5803_INT3_BFET_PWR_LIMIT		BIT(1)
-#define SM5803_INT3_BFET_PWR_HWSAFE_LIMIT	BIT(2)
-#define SM5803_INT3_SPARE			BIT(3)
-#define SM5803_INT3_VBUS_PWR_LIMIT		BIT(4)
-#define SM5803_INT3_IBAT			BIT(5)
-
-#define SM5803_REG_INT4_REQ		0x08
-#define SM5803_REG_INT4_EN		0x0D
-#define SM5803_INT4_CHG_FAIL		BIT(0)
-#define SM5803_INT4_CHG_DONE		BIT(1)
-#define SM5803_INT4_CHG_START		BIT(2)
-#define SM5803_INT4_SLP_EXIT		BIT(3)
-#define SM5803_INT4_OTG_FAIL		BIT(4)
-#define SM5803_INT4_CHG_ILIM		BIT(5)
-#define SM5803_INT4_IBAT_CC		BIT(6)
-#define SM5803_INT4_CC			BIT(7)
-
-#define SM5803_REG_MISC_CONFIG		0x15
-#define SM5803_MISC_INV_INT		BIT(0)
-#define SM5803_INT_CLEAR_MODE		BIT(1)
-#define SM5803_INT_MASK_MODE		BIT(2)
-
-#define SM5803_REG_PLATFORM		0x18
-#define SM5803_PLATFORM_ID		GENMASK(4, 0)
-
-#define SM5803_REG_REFERENCE		0x20
-#define SM5803_REFERENCE_LDO3P3_PGOOD	BIT(4)
-#define SM5803_REFERENCE_LDO5_PGOOD	BIT(5)
-
-#define SM5803_REG_CLOCK_SEL		0x2A
-#define SM5803_CLOCK_SEL_LOW		BIT(0)
-
-#define SM5803_REG_GPIO0_CTRL		0x30
-#define SM5803_GPIO0_VAL		BIT(0)
-#define SM5803_GPIO0_MODE_MASK		GENMASK(2, 1)
-#define SM5803_GPIO0_OPEN_DRAIN_EN	BIT(6)
-#define SM5803_CHG_DET_OPEN_DRAIN_EN	BIT(7)
+#define SM5803_REG_CHIP_ID 0x00
+
+#define SM5803_REG_STATUS1 0x01
+#define SM5803_STATUS1_VSYS_OK BIT(0)
+#define SM5803_STATUS1_VPWR_OK BIT(1)
+#define SM5803_STATUS1_VBUS_UVL BIT(3)
+#define SM5803_STATUS1_VBUS_SHORT BIT(4)
+#define SM5803_STATUS1_VBUS_OVH BIT(5)
+#define SM5803_STATUS1_CHG_DET BIT(6)
+#define SM5803_STATUS1_BAT_DET BIT(7)
+
+#define SM5803_REG_STATUS2 0x02
+#define SM5803_STATUS2_BAT_DET_FG BIT(1)
+#define SM5803_STATUS2_VBAT_SHORT BIT(0)
+
+#define SM5803_REG_INT1_REQ 0x05
+#define SM5803_REG_INT1_EN 0x0A
+#define SM5803_INT1_VBUS_PWR_HWSAFE_LIMIT BIT(0)
+#define SM5803_INT1_CHG BIT(2)
+#define SM5803_INT1_BAT BIT(3)
+#define SM5803_INT1_CLS_OC BIT(4)
+#define SM5803_INT1_SLV_DET BIT(5)
+#define SM5803_INT1_SWL_DISCH BIT(6)
+#define SM5803_INT1_PREREG BIT(7)
+
+#define SM5803_REG_INT2_REQ 0x06
+#define SM5803_REG_INT2_EN 0x0B
+#define SM5803_INT2_VBATSNSP BIT(0)
+#define SM5803_INT2_IBAT_DISCHG BIT(1)
+#define SM5803_INT2_IBAT_CHG BIT(2)
+#define SM5803_INT2_IBUS BIT(3)
+#define SM5803_INT2_VBUS BIT(4)
+#define SM5803_INT2_VCHGPWR BIT(5)
+#define SM5803_INT2_VSYS BIT(6)
+#define SM5803_INT2_TINT BIT(7)
+
+#define SM5803_REG_INT3_REQ 0x07
+#define SM5803_REG_INT3_EN 0x0C
+#define SM5803_INT3_GPADC0 BIT(0)
+#define SM5803_INT3_BFET_PWR_LIMIT BIT(1)
+#define SM5803_INT3_BFET_PWR_HWSAFE_LIMIT BIT(2)
+#define SM5803_INT3_SPARE BIT(3)
+#define SM5803_INT3_VBUS_PWR_LIMIT BIT(4)
+#define SM5803_INT3_IBAT BIT(5)
+
+#define SM5803_REG_INT4_REQ 0x08
+#define SM5803_REG_INT4_EN 0x0D
+#define SM5803_INT4_CHG_FAIL BIT(0)
+#define SM5803_INT4_CHG_DONE BIT(1)
+#define SM5803_INT4_CHG_START BIT(2)
+#define SM5803_INT4_SLP_EXIT BIT(3)
+#define SM5803_INT4_OTG_FAIL BIT(4)
+#define SM5803_INT4_CHG_ILIM BIT(5)
+#define SM5803_INT4_IBAT_CC BIT(6)
+#define SM5803_INT4_CC BIT(7)
+
+#define SM5803_REG_MISC_CONFIG 0x15
+#define SM5803_MISC_INV_INT BIT(0)
+#define SM5803_INT_CLEAR_MODE BIT(1)
+#define SM5803_INT_MASK_MODE BIT(2)
+
+#define SM5803_REG_PLATFORM 0x18
+#define SM5803_PLATFORM_ID GENMASK(4, 0)
+
+#define SM5803_REG_REFERENCE 0x20
+#define SM5803_REFERENCE_LDO3P3_PGOOD BIT(4)
+#define SM5803_REFERENCE_LDO5_PGOOD BIT(5)
+
+#define SM5803_REG_CLOCK_SEL 0x2A
+#define SM5803_CLOCK_SEL_LOW BIT(0)
+
+#define SM5803_REG_GPIO0_CTRL 0x30
+#define SM5803_GPIO0_VAL BIT(0)
+#define SM5803_GPIO0_MODE_MASK GENMASK(2, 1)
+#define SM5803_GPIO0_OPEN_DRAIN_EN BIT(6)
+#define SM5803_CHG_DET_OPEN_DRAIN_EN BIT(7)
+
+#define SM5803_REG_VBATSNSP_MEAS_MSB 0x40
+#define SM5803_REG_VBATSNSP_MEAS_LSB 0x41
 
 enum sm5803_gpio0_modes {
 	GPIO0_MODE_PROCHOT,
@@ -99,14 +105,14 @@ enum sm5803_gpio0_modes {
 	GPIO0_MODE_INPUT
 };
 
-#define SM5803_REG_BFET_PWR_MAX_TH		0x35
-#define SM5803_REG_BFET_PWR_HWSAFE_MAX_TH	0x36
+#define SM5803_REG_BFET_PWR_MAX_TH 0x35
+#define SM5803_REG_BFET_PWR_HWSAFE_MAX_TH 0x36
 
-#define SM5803_REG_PORTS_CTRL		0x40
-#define SM5803_PORTS_VBUS_DISCH		BIT(0)
-#define SM5803_PORTS_VBUS_PULLDOWN	BIT(1)
-#define SM5803_PORTS_VBUS_SNS_DISCH	BIT(2)
-#define SM5803_PORTS_VBUS_SNS_PULLDOWN	BIT(3)
+#define SM5803_REG_PORTS_CTRL 0x40
+#define SM5803_PORTS_VBUS_DISCH BIT(0)
+#define SM5803_PORTS_VBUS_PULLDOWN BIT(1)
+#define SM5803_PORTS_VBUS_SNS_DISCH BIT(2)
+#define SM5803_PORTS_VBUS_SNS_PULLDOWN BIT(3)
 
 /* ADC Registers (address 0x31) */
 
@@ -114,76 +120,117 @@ enum sm5803_gpio0_modes {
  * Note: Some register bits must be enabled for the DC-DC converter to properly
  * handle transitions.
  */
-#define SM5803_REG_GPADC_CONFIG1	0x01
-#define SM5803_GPADCC1_VBATSNSP_EN	BIT(0)
-#define SM5803_GPADCC1_IBAT_DIS_EN	BIT(1)
-#define SM5803_GPADCC1_IBAT_CHG_EN	BIT(2)
-#define SM5803_GPADCC1_IBUS_EN		BIT(3)
-#define SM5803_GPADCC1_VBUS_EN		BIT(4)
-#define SM5803_GPADCC1_VCHGPWR_EN	BIT(5)  /* NOTE: DO NOT CLEAR */
-#define SM5803_GPADCC1_VSYS_EN		BIT(6)  /* NOTE: DO NOT CLEAR */
-#define SM5803_GPADCC1_TINT_EN		BIT(7)
+#define SM5803_REG_GPADC_CONFIG1 0x01
+#define SM5803_GPADCC1_VBATSNSP_EN BIT(0)
+#define SM5803_GPADCC1_IBAT_DIS_EN BIT(1)
+#define SM5803_GPADCC1_IBAT_CHG_EN BIT(2)
+#define SM5803_GPADCC1_IBUS_EN BIT(3)
+#define SM5803_GPADCC1_VBUS_EN BIT(4)
+#define SM5803_GPADCC1_VCHGPWR_EN BIT(5) /* NOTE: DO NOT CLEAR */
+#define SM5803_GPADCC1_VSYS_EN BIT(6) /* NOTE: DO NOT CLEAR */
+#define SM5803_GPADCC1_TINT_EN BIT(7)
+
+/*
+ * Default value for GPADCC1, set at initialization: the normal operating state.
+ *
+ * IBAT_CHG is enabled in order to measure battery current and calculate system
+ * resistance.
+ */
+#define SM5803_GPADCC1_DEFAULT_ENABLE                              \
+	(SM5803_GPADCC1_TINT_EN | SM5803_GPADCC1_VSYS_EN |         \
+	 SM5803_GPADCC1_VCHGPWR_EN | SM5803_GPADCC1_VBUS_EN |      \
+	 SM5803_GPADCC1_IBAT_CHG_EN | SM5803_GPADCC1_IBAT_DIS_EN | \
+	 SM5803_GPADCC1_VBATSNSP_EN)
 
-#define SM5803_REG_GPADC_CONFIG2	0x02
+#define SM5803_REG_GPADC_CONFIG2 0x02
 
-#define SM5803_REG_PSYS1		0x04
-#define SM5803_PSYS1_DAC_EN		BIT(0)
+#define SM5803_REG_PSYS1 0x04
+#define SM5803_PSYS1_DAC_EN BIT(0)
 
 /* Note: Threshold registers all assume lower 2 bits are 0 */
-#define SM5803_REG_VBUS_LOW_TH		0x1A
-#define SM5803_REG_VBUS_HIGH_TH		0x2A
-#define SM5803_REG_TINT_LOW_TH		0x1D
-#define SM5803_REG_TINT_HIGH_TH		0x2D
+#define SM5803_REG_VBUS_LOW_TH 0x1A
+#define SM5803_REG_VBATSNSP_MAX_TH 0x26
+#define SM5803_REG_VBUS_HIGH_TH 0x2A
+#define SM5803_REG_VCHG_PWR_LOW_TH 0x1B
+#define SM5803_REG_VCHG_PWR_HIGH_TH 0x2B
+#define SM5803_REG_TINT_LOW_TH 0x1D
+#define SM5803_REG_TINT_HIGH_TH 0x2D
 
 /*
  * Vbus levels increment in 23.4 mV, set thresholds to below 3.5V and above 4.0V
  * to mirror what TCPCI uses for Vbus present indication
  */
-#define SM5803_VBUS_LOW_LEVEL		0x25
-#define SM5803_VBUS_HIGH_LEVEL		0x2C
+#define SM5803_VBUS_LOW_LEVEL 0x25
+#define SM5803_VBUS_HIGH_LEVEL 0x2C
 
 /*
  * TINT thresholds.  TINT steps are in 0.43 K with the upper threshold set to
  * 360 K and lower threshold to de-assert PROCHOT at 330 K.
  */
-#define SM5803_TINT_LOW_LEVEL		0xBF
-#define SM5803_TINT_HIGH_LEVEL		0xD1
+#define SM5803_TINT_LOW_LEVEL 0xBF
+#define SM5803_TINT_HIGH_LEVEL 0xD1
+
+#define SM5803_TINT_MAX_LEVEL 0xFF
+#define SM5803_TINT_MIN_LEVEL 0x00
+
+/*
+ * Set minimum thresholds for VBUS_PWR_LOW_TH interrupt generation
+ * 2S battery 9.4v
+ * 3S battery 14.1V VBUS_PWR MIN TH
+ */
+#define SM5803_VBAT_PWR_MINTH_3S_LEVEL 0x9B
+#define SM5803_VBAT_PWR_MINTH_2S_LEVEL 0x9B
+
+/*
+ * Set thresholds for VBATSNSP_MAX_TH GPADC interrupt generation
+ * 2S battery 9v
+ * 3S battery 13.3V
+ */
+#define SM5803_VBAT_SNSP_MAXTH_3S_LEVEL 0xD8
+#define SM5803_VBAT_SNSP_MAXTH_2S_LEVEL 0xDC
 
 /* IBAT levels - The IBAT levels increment in 7.32mA */
-#define SM5803_REG_IBAT_CHG_MEAS_MSB	0x44
-#define SM5803_REG_IBAT_CHG_MEAS_LSB	0x45
-#define SM5803_IBAT_CHG_MEAS_LSB	GENMASK(1, 0)
+#define SM5803_REG_IBAT_CHG_MEAS_MSB 0x44
+#define SM5803_REG_IBAT_CHG_MEAS_LSB 0x45
+#define SM5803_REG_IBAT_CHG_AVG_MEAS_MSB 0xC4
+#define SM5803_REG_IBAT_CHG_AVG_MEAS_LSB 0xC5
+#define SM5803_IBAT_CHG_MEAS_LSB GENMASK(1, 0)
 
 /* IBUS levels - The IBUS levels increment in 7.32mA */
-#define SM5803_REG_IBUS_CHG_MEAS_MSB	0x46
-#define SM5803_REG_IBUS_CHG_MEAS_LSB	0x47
-#define SM5803_IBUS_CHG_MEAS_LSB	GENMASK(1, 0)
+#define SM5803_REG_IBUS_CHG_MEAS_MSB 0x46
+#define SM5803_REG_IBUS_CHG_MEAS_LSB 0x47
+#define SM5803_IBUS_CHG_MEAS_LSB GENMASK(1, 0)
 
-#define SM5803_REG_VBUS_MEAS_MSB	0x48
-#define SM5803_REG_VBUS_MEAS_LSB	0x49
-#define SM5803_VBUS_MEAS_LSB		GENMASK(1, 0)
-#define SM5803_VBUS_MEAS_BAT_DET	BIT(2)
-#define SM5803_VBUS_MEAS_VBUS_SHORT	BIT(4)
-#define SM5803_VBUS_MEAS_OV_TEMP	BIT(5)
-#define SM5803_VBUS_MEAS_CHG_DET	BIT(6)
+#define SM5803_REG_VBUS_MEAS_MSB 0x48
+#define SM5803_REG_VBUS_MEAS_LSB 0x49
+#define SM5803_VBUS_MEAS_LSB GENMASK(1, 0)
+#define SM5803_VBUS_MEAS_BAT_DET BIT(2)
+#define SM5803_VBUS_MEAS_VBUS_SHORT BIT(4)
+#define SM5803_VBUS_MEAS_OV_TEMP BIT(5)
+#define SM5803_VBUS_MEAS_CHG_DET BIT(6)
 
-#define SM5803_REG_TINT_MEAS_MSB	0x4E
+/* VCHGPWR levels - The VCHGPWR levels increment in 23.4mV steps. */
+#define SM5803_REG_VCHG_PWR_MSB 0x4A
+
+#define SM5803_REG_TINT_MEAS_MSB 0x4E
 
 /* VSYS levels - The VSYS levels increment in  23.4mV steps. */
-#define SM5803_REG_VSYS_MEAS_MSB	0x4C
-#define SM5803_REG_VSYS_MEAS_LSB	0x4D
-#define SM5803_VSYS_MEAS_LSB		GENMASK(1, 0)
+#define SM5803_REG_VSYS_MEAS_MSB 0x4C
+#define SM5803_REG_VSYS_MEAS_LSB 0x4D
+#define SM5803_REG_VSYS_AVG_MEAS_MSB 0xCC
+#define SM5803_REG_VSYS_AVG_MEAS_LSB 0xCD
+#define SM5803_VSYS_MEAS_LSB GENMASK(1, 0)
 
 /* Charger registers (address 0x32) */
 
-#define SM5803_REG_CC_CONFIG1		0x01
-#define SM5803_CC_CONFIG1_SD_PWRUP	BIT(3)
+#define SM5803_REG_CC_CONFIG1 0x01
+#define SM5803_CC_CONFIG1_SD_PWRUP BIT(3)
 
-#define SM5803_REG_FLOW1		0x1C
-#define SM5803_FLOW1_MODE		GENMASK(1, 0)
-#define SM5803_FLOW1_DIRECTCHG_SRC_EN	BIT(2)
-#define SM5803_FLOW1_LINEAR_CHARGE_EN	BIT(3)
-#define SM5803_FLOW1_USB_SUSP		BIT(7)
+#define SM5803_REG_FLOW1 0x1C
+#define SM5803_FLOW1_MODE GENMASK(1, 0)
+#define SM5803_FLOW1_DIRECTCHG_SRC_EN BIT(2)
+#define SM5803_FLOW1_LINEAR_CHARGE_EN BIT(3)
+#define SM5803_FLOW1_USB_SUSP BIT(7)
 
 enum sm5803_charger_modes {
 	CHARGER_MODE_DISABLED,
@@ -192,120 +239,157 @@ enum sm5803_charger_modes {
 	CHARGER_MODE_SOURCE,
 };
 
-#define SM5803_REG_FLOW2		0x1D
-#define SM5803_FLOW2_AUTO_TRKL_EN	BIT(0)
-#define SM5803_FLOW2_AUTO_PRECHG_EN	BIT(1)
-#define SM5803_FLOW2_AUTO_FASTCHG_EN	BIT(2)
-#define SM5803_FLOW2_AUTO_ENABLED	GENMASK(2, 0)
-#define SM5803_FLOW2_FW_TRKL_CMD	BIT(3)
-#define SM5803_FLOW2_FW_PRECHG_CMD	BIT(4)
-#define SM5803_FLOW2_FW_FASTCHG_CMD	BIT(5)
-#define SM5803_FLOW2_HOST_MODE_EN	BIT(6)
-#define SM5803_FLOW2_AUTO_CHGEN_SET	BIT(7)
-
-#define SM5803_REG_FLOW3		0x1E
-#define SM5803_FLOW3_SWITCH_BCK_BST	BIT(0)
-#define SM5803_FLOW3_FW_SWITCH_RESUME	BIT(1)
-#define SM5803_FLOW3_FW_SWITCH_PAUSE	BIT(2)
-#define SM5803_FLOW3_SOFT_DISABLE_EN	BIT(3)
-
-#define SM5803_REG_SWITCHER_CONF	0x1F
-#define SM5803_SW_BCK_BST_CONF_AUTO	BIT(0)
-
-#define SM5803_REG_ANA_EN1		0x21
-#define SM5803_ANA_EN1_CLS_DISABLE	BIT(7)
+#define SM5803_REG_FLOW2 0x1D
+#define SM5803_FLOW2_AUTO_TRKL_EN BIT(0)
+#define SM5803_FLOW2_AUTO_PRECHG_EN BIT(1)
+#define SM5803_FLOW2_AUTO_FASTCHG_EN BIT(2)
+#define SM5803_FLOW2_AUTO_ENABLED GENMASK(2, 0)
+#define SM5803_FLOW2_FW_TRKL_CMD BIT(3)
+#define SM5803_FLOW2_FW_PRECHG_CMD BIT(4)
+#define SM5803_FLOW2_FW_FASTCHG_CMD BIT(5)
+#define SM5803_FLOW2_HOST_MODE_EN BIT(6)
+#define SM5803_FLOW2_AUTO_CHGEN_SET BIT(7)
+
+#define SM5803_REG_FLOW3 0x1E
+#define SM5803_FLOW3_SWITCH_BCK_BST BIT(0)
+#define SM5803_FLOW3_FW_SWITCH_RESUME BIT(1)
+#define SM5803_FLOW3_FW_SWITCH_PAUSE BIT(2)
+#define SM5803_FLOW3_SOFT_DISABLE_EN BIT(3)
+
+#define SM5803_REG_SWITCHER_CONF 0x1F
+#define SM5803_SW_BCK_BST_CONF_AUTO BIT(0)
+
+#define SM5803_REG_ANA_EN1 0x21
+#define SM5803_ANA_EN1_CLS_DISABLE BIT(7)
 
 /*
  * Input current limit is CHG_ILIM_RAW *100 mA
  */
-#define SM5803_REG_CHG_ILIM		0x24
-#define SM5803_CHG_ILIM_RAW		GENMASK(4, 0)
-#define SM5803_CURRENT_STEP		100
-#define SM5803_REG_TO_CURRENT(r)	(r * SM5803_CURRENT_STEP)
-#define SM5803_CURRENT_TO_REG(c)	(c / SM5803_CURRENT_STEP)
+#define SM5803_REG_CHG_ILIM 0x24
+#define SM5803_CHG_ILIM_RAW GENMASK(4, 0)
+#define SM5803_CURRENT_STEP 100
+#define SM5803_REG_TO_CURRENT(r) ((r)*SM5803_CURRENT_STEP)
+#define SM5803_CURRENT_TO_REG(c) ((c) / SM5803_CURRENT_STEP)
+
+/*
+ * DPM Voltage loop regulation contains the 8 bits with MSB register
+ * and the lower 3 bits with LSB register.
+ * The regulation value is 2.72 V + DPM_VL_SET * 10mV
+ */
+#define SM5803_REG_DPM_VL_SET_MSB 0x26
+#define SM5803_REG_DPM_VL_SET_LSB 0x27
 
 /*
  * Output voltage uses the same equation as Vsys
  * Lower saturation value is 3 V, upper 20.5 V
  */
-#define SM5803_REG_VPWR_MSB		0x30
-#define SM5803_REG_DISCH_CONF2		0x31
-#define SM5803_DISCH_CONF5_VPWR_LSB	GENMASK(2, 0)
+#define SM5803_REG_VPWR_MSB 0x30
+#define SM5803_REG_DISCH_CONF2 0x31
+#define SM5803_DISCH_CONF5_VPWR_LSB GENMASK(2, 0)
 
 /*
  * Output current limit is CLS_LIMIT * 50 mA and saturates to 3.2 A
  */
-#define SM5803_REG_DISCH_CONF5		0x34
-#define SM5803_DISCH_CONF5_CLS_LIMIT	GENMASK(6, 0)
-#define SM5803_CLS_CURRENT_STEP		50
+#define SM5803_REG_DISCH_CONF5 0x34
+#define SM5803_DISCH_CONF5_CLS_LIMIT GENMASK(6, 0)
+#define SM5803_CLS_CURRENT_STEP 50
+
+#define SM5803_REG_DISCH_CONF6 0x35
+#define SM5803_DISCH_CONF6_RAMPS_DIS BIT(0)
+#define SM5803_DISCH_CONF6_SMOOTH_DIS BIT(1)
 
 /*
  * Vsys is 11 bits, with the lower 3 bits in the LSB register.
  * The pre-regulation value is 2.72 V + Vsys_prereg * 10 mV
  * Lower saturation value is 3V, upper is 20V
  */
-#define SM5803_REG_VSYS_PREREG_MSB	0x36
-#define SM5803_REG_VSYS_PREREG_LSB	0x37
-#define SM5803_VOLTAGE_STEP		10
-#define SM5803_VOLTAGE_SHIFT		2720
-#define SM5803_REG_TO_VOLTAGE(r)	(SM5803_VOLTAGE_SHIFT + \
-					 r * SM5803_VOLTAGE_STEP)
-#define SM5803_VOLTAGE_TO_REG(v)	((v - SM5803_VOLTAGE_SHIFT) \
-					 / SM5803_VOLTAGE_STEP)
+#define SM5803_REG_VSYS_PREREG_MSB 0x36
+#define SM5803_REG_VSYS_PREREG_LSB 0x37
+#define SM5803_VOLTAGE_STEP 10
+#define SM5803_VOLTAGE_SHIFT 2720
+#define SM5803_REG_TO_VOLTAGE(r) \
+	(SM5803_VOLTAGE_SHIFT + (r)*SM5803_VOLTAGE_STEP)
+#define SM5803_VOLTAGE_TO_REG(v) \
+	(((v)-SM5803_VOLTAGE_SHIFT) / SM5803_VOLTAGE_STEP)
 
 /*
  * Precharge Termination threshold.
  */
-#define SM5803_REG_PRE_FAST_CONF_REG1	0x39
-#define SM5803_VBAT_PRE_TERM_MIN_DV	23
+#define SM5803_REG_PRE_FAST_CONF_REG1 0x39
+#define SM5803_VBAT_PRE_TERM_MIN_DV 23
 /* 3.8V+ gets rounded to 4V */
-#define SM5803_VBAT_PRE_TERM_MAX_DV	38
-#define SM5803_VBAT_PRE_TERM		GENMASK(7, 4)
-#define SM5803_VBAT_PRE_TERM_SHIFT	4
+#define SM5803_VBAT_PRE_TERM_MAX_DV 38
+#define SM5803_VBAT_PRE_TERM GENMASK(7, 4)
+#define SM5803_VBAT_PRE_TERM_SHIFT 4
 
 /*
  * Vbat for fast charge uses the same equation as Vsys
  * Lower saturation value is 3V, upper is dependent on number of cells
  */
-#define SM5803_REG_VBAT_FAST_MSB	0x3A
-#define SM5803_REG_VBAT_FAST_LSB	0x3B
+#define SM5803_REG_VBAT_FAST_MSB 0x3A
+#define SM5803_REG_VBAT_FAST_LSB 0x3B
 
 /*
  * Fast charge current limit is ICHG_FAST * 100 mA
  * Value read back may be adjusted if tempearture limits are exceeded
  */
-#define SM5803_REG_FAST_CONF4		0x3C
-#define SM5803_CONF4_ICHG_FAST		GENMASK(5, 0)
-
-/* Precharge current limit is also intervals of 100 mA */
-#define SM5803_REG_PRECHG		0x41
-#define SM5803_PRECHG_ICHG_PRE_SET	GENMASK(5, 0)
+#define SM5803_REG_FAST_CONF4 0x3C
+#define SM5803_CONF4_ICHG_FAST GENMASK(5, 0)
 
 /* Fast charge Termination */
-#define SM5803_REG_FAST_CONF5		0x3D
-#define SM5803_CONF5_IBAT_EOC_TH	GENMASK(3, 0)
+#define SM5803_REG_FAST_CONF5 0x3D
+#define SM5803_CONF5_IBAT_EOC_TH GENMASK(3, 0)
 
 /* IR drop compensation */
-#define SM5803_REG_IR_COMP1		0x3F
-#define SM5803_IR_COMP_RES_SET_MSB	GENMASK(7, 6)
+#define SM5803_REG_IR_COMP1 0x3F
+#define SM5803_IR_COMP_RES_SET_MSB GENMASK(7, 6)
 #define SM5803_IR_COMP_RES_SET_MSB_SHIFT 6
-#define SM5803_IR_COMP_EN		BIT(5)
+#define SM5803_IR_COMP_EN BIT(5)
 
 /* LSB is in 1.67mOhm steps. */
-#define SM5803_REG_IR_COMP2		0x40
-
-#define SM5803_REG_LOG1			0x42
-#define SM5803_BATFET_ON		BIT(2)
+#define SM5803_REG_IR_COMP2 0x40
 
-#define SM5803_REG_PHOT1		0x72
-#define SM5803_PHOT1_IBAT_PHOT_COMP_EN	BIT(0)
-#define SM5803_PHOT1_IBUS_PHOT_COMP_EN	BIT(1)
-#define SM5803_PHOT1_VSYS_MON_EN	BIT(2)
-#define SM5803_PHOT1_VBUS_MON_EN	BIT(3)
-#define SM5803_PHOT1_COMPARATOR_EN	GENMASK(3, 0)
-#define SM5803_PHOT1_DURATION		GENMASK(6, 4)
-#define SM5803_PHOT1_DURATION_SHIFT	4
-#define SM5803_PHOT1_IRQ_MODE		BIT(7)
+/* Precharge current limit is also intervals of 100 mA */
+#define SM5803_REG_PRECHG 0x41
+#define SM5803_PRECHG_ICHG_PRE_SET GENMASK(5, 0)
+
+#define SM5803_REG_LOG1 0x42
+#define SM5803_BATFET_ON BIT(2)
+
+#define SM5803_REG_LOG2 0x43
+#define SM5803_ISOLOOP_ON BIT(1)
+
+#define SM5803_REG_STATUS_CHG_REG 0x48
+#define SM5803_STATUS_CHG_BATT_REMOVAL BIT(0)
+#define SM5803_STATUS_CHG_CHG_REMOVAL BIT(1)
+#define SM5803_STATUS_CHG_BATTEMP_NOK BIT(2)
+#define SM5803_STATUS_CHG_CHGWDG_EXP BIT(3)
+#define SM5803_STATUS_CHG_VBUS_OC BIT(4)
+#define SM5803_STATUS_CHG_OV_VBAT BIT(5)
+#define SM5803_STATUS_CHG_TIMEOUT BIT(6)
+#define SM5803_STATUS_CHG_OV_ITEMP BIT(7)
+
+#define SM5803_REG_STATUS_DISCHG 0x49
+#define SM5803_STATUS_DISCHG_BATT_REM BIT(0)
+#define SM5803_STATUS_DISCHG_UV_VBAT BIT(1)
+#define SM5803_STATUS_DISCHG_VBUS_OC BIT(2)
+#define SM5803_STATUS_DISCHG_VBUS_PWR GENMASK(4, 3)
+#define SM5803_STATUS_DISCHG_ISO_CURR BIT(5)
+#define SM5803_STATUS_DISCHG_VBUS_SHORT BIT(6)
+#define SM5803_STATUS_DISCHG_OV_ITEMP BIT(7)
+
+#define SM5803_REG_CHG_MON_REG 0x5C
+#define SM5803_DPM_LOOP_EN BIT(0)
+
+#define SM5803_REG_PHOT1 0x72
+#define SM5803_PHOT1_IBAT_PHOT_COMP_EN BIT(0)
+#define SM5803_PHOT1_IBUS_PHOT_COMP_EN BIT(1)
+#define SM5803_PHOT1_VSYS_MON_EN BIT(2)
+#define SM5803_PHOT1_VBUS_MON_EN BIT(3)
+#define SM5803_PHOT1_COMPARATOR_EN GENMASK(3, 0)
+#define SM5803_PHOT1_DURATION GENMASK(6, 4)
+#define SM5803_PHOT1_DURATION_SHIFT 4
+#define SM5803_PHOT1_IRQ_MODE BIT(7)
 
 #define CHARGER_NAME "sm5803"
 
@@ -338,10 +422,42 @@ enum ec_error_list sm5803_vbus_sink_enable(int chgnum, int enable);
 void sm5803_hibernate(int chgnum);
 void sm5803_interrupt(int chgnum);
 
+/**
+ * Return whether ACOK is high or low.
+ *
+ * @param chgnum index into chg_chips table.
+ * @param acok will be set to true if ACOK is asserted, otherwise false.
+ * @return EC_SUCCESS, error otherwise.
+ */
+enum ec_error_list sm5803_is_acok(int chgnum, bool *acok);
+
+/**
+ * Test whether the current voltage on VBUS corresponds to the given range.
+ *
+ * Users should prefer this function to manually evaluating the result of
+ * charger_get_vbus_voltage because that function may behave incorrectly when
+ * the charger is in low power mode. This function will return correct results
+ * regardless of the charger state.
+ *
+ * @param chgnum charger index to test
+ * @param level VBUS range
+ * @return true if the current VBUS voltage is in the given range, false if it
+ *         is not or if there is a problem communicating with the charger.
+ */
+bool sm5803_check_vbus_level(int chgnum, enum vbus_level level);
+
 /* Expose low power mode functions */
 void sm5803_disable_low_power_mode(int chgnum);
 void sm5803_enable_low_power_mode(int chgnum);
 
 extern const struct charger_drv sm5803_drv;
 
+/* Expose interrupt handler for processing in PD_INT task when needed */
+void sm5803_handle_interrupt(int chgnum);
+
+#ifdef TEST_BUILD
+void test_sm5803_set_fast_charge_disabled(bool value);
+bool test_sm5803_get_fast_charge_disabled(void);
+#endif
+
 #endif
diff --git a/driver/charger/sy21612.c b/driver/charger/sy21612.c
index 0a1b122d28..bded1474b6 100644
--- a/driver/charger/sy21612.c
+++ b/driver/charger/sy21612.c
@@ -1,11 +1,10 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * SILERGY SY21612 buck-boost converter driver.
  */
 
-
 #include "console.h"
 #include "hooks.h"
 #include "i2c.h"
@@ -15,8 +14,8 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CHARGER, outstr)
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 static int sy21612_clear_set_reg(int reg, int clear, int set)
 {
@@ -31,8 +30,7 @@ static int sy21612_clear_set_reg(int reg, int clear, int set)
 	val |= set;
 
 	if (val != old_val || clear || set)
-		rv = i2c_write8(I2C_PORT_SY21612, SY21612_ADDR_FLAGS,
-				reg, val);
+		rv = i2c_write8(I2C_PORT_SY21612, SY21612_ADDR_FLAGS, reg, val);
 
 	return rv;
 }
@@ -44,64 +42,62 @@ static int sy21612_read(int reg, int *val)
 
 int sy21612_enable_regulator(int enable)
 {
-	return enable ?
-		sy21612_clear_set_reg(SY21612_CTRL1, 0, SY21612_CTRL1_REG_EN) :
-		sy21612_clear_set_reg(SY21612_CTRL1, SY21612_CTRL1_REG_EN, 0);
+	return enable ? sy21612_clear_set_reg(SY21612_CTRL1, 0,
+					      SY21612_CTRL1_REG_EN) :
+			sy21612_clear_set_reg(SY21612_CTRL1,
+					      SY21612_CTRL1_REG_EN, 0);
 }
 
 int sy21612_enable_adc(int enable)
 {
-	return enable ?
-		sy21612_clear_set_reg(SY21612_CTRL1, 0, SY21612_CTRL1_ADC_EN) :
-		sy21612_clear_set_reg(SY21612_CTRL1, SY21612_CTRL1_ADC_EN, 0);
+	return enable ? sy21612_clear_set_reg(SY21612_CTRL1, 0,
+					      SY21612_CTRL1_ADC_EN) :
+			sy21612_clear_set_reg(SY21612_CTRL1,
+					      SY21612_CTRL1_ADC_EN, 0);
 }
 
 int sy21612_set_adc_mode(int auto_mode)
 {
 	return auto_mode ?
-		sy21612_clear_set_reg(SY21612_CTRL1,
-				      0, SY21612_CTRL1_ADC_AUTO_MODE) :
-		sy21612_clear_set_reg(SY21612_CTRL1,
-				      SY21612_CTRL1_ADC_AUTO_MODE, 0);
+		       sy21612_clear_set_reg(SY21612_CTRL1, 0,
+					     SY21612_CTRL1_ADC_AUTO_MODE) :
+		       sy21612_clear_set_reg(SY21612_CTRL1,
+					     SY21612_CTRL1_ADC_AUTO_MODE, 0);
 }
 
 int sy21612_set_vbus_discharge(int auto_discharge)
 {
 	return auto_discharge ?
-		sy21612_clear_set_reg(SY21612_CTRL1,
-				      SY21612_CTRL1_VBUS_NDISCHG, 0) :
-		sy21612_clear_set_reg(SY21612_CTRL1,
-				      0, SY21612_CTRL1_VBUS_NDISCHG);
+		       sy21612_clear_set_reg(SY21612_CTRL1,
+					     SY21612_CTRL1_VBUS_NDISCHG, 0) :
+		       sy21612_clear_set_reg(SY21612_CTRL1, 0,
+					     SY21612_CTRL1_VBUS_NDISCHG);
 }
 
 int sy21612_set_switching_freq(enum sy21612_switching_freq freq)
 {
-	return sy21612_clear_set_reg(SY21612_CTRL2,
-				     SY21612_CTRL2_FREQ_MASK,
+	return sy21612_clear_set_reg(SY21612_CTRL2, SY21612_CTRL2_FREQ_MASK,
 				     freq << SY21612_CTRL2_FREQ_SHIFT);
 }
 
 int sy21612_set_vbus_volt(enum sy21612_vbus_volt volt)
 {
-	return sy21612_clear_set_reg(SY21612_CTRL2,
-				     SY21612_CTRL2_VBUS_MASK,
+	return sy21612_clear_set_reg(SY21612_CTRL2, SY21612_CTRL2_VBUS_MASK,
 				     volt << SY21612_CTRL2_VBUS_SHIFT);
 }
 
 int sy21612_set_vbus_adj(enum sy21612_vbus_adj adj)
 {
-	return sy21612_clear_set_reg(SY21612_CTRL2,
-				     SY21612_CTRL2_VBUS_ADJ_MASK,
+	return sy21612_clear_set_reg(SY21612_CTRL2, SY21612_CTRL2_VBUS_ADJ_MASK,
 				     adj << SY21612_CTRL2_VBUS_ADJ_SHIFT);
 }
 
 int sy21612_set_sink_mode(int sink_mode)
 {
-	return sink_mode ?
-		sy21612_clear_set_reg(SY21612_PROT2,
-				      0, SY21612_PROT2_SINK_MODE) :
-		sy21612_clear_set_reg(SY21612_PROT2,
-				      SY21612_PROT2_SINK_MODE, 0);
+	return sink_mode ? sy21612_clear_set_reg(SY21612_PROT2, 0,
+						 SY21612_PROT2_SINK_MODE) :
+			   sy21612_clear_set_reg(SY21612_PROT2,
+						 SY21612_PROT2_SINK_MODE, 0);
 }
 
 int sy21612_is_power_good(void)
@@ -166,7 +162,7 @@ void sy21612_int(enum gpio_signal signal)
 }
 
 #ifdef HAS_TASK_SY21612
-void sy21612_task(void)
+void sy21612_task(void *u)
 {
 	int flags;
 
@@ -188,7 +184,7 @@ void sy21612_task(void)
 #endif
 
 #ifdef CONFIG_CMD_CHARGER
-static int command_sy21612(int argc, char **argv)
+static int command_sy21612(int argc, const char **argv)
 {
 	int i, val, rv;
 
@@ -199,7 +195,7 @@ static int command_sy21612(int argc, char **argv)
 		if (rv)
 			ccprintf(" x (%d)\n", rv);
 		else
-			ccprintf("%02x - %pb\n", val, BINARY_VALUE(val, 8));
+			ccprintf("%02x\n", val);
 	}
 
 	ccprintf("vbat voltage: %d mV\n", sy21612_get_vbat_voltage());
@@ -208,7 +204,5 @@ static int command_sy21612(int argc, char **argv)
 
 	return 0;
 }
-DECLARE_CONSOLE_COMMAND(sy21612, command_sy21612,
-			NULL, NULL);
+DECLARE_CONSOLE_COMMAND(sy21612, command_sy21612, NULL, NULL);
 #endif
-
diff --git a/driver/charger/sy21612.h b/driver/charger/sy21612.h
index befb8e6a35..bc6d45797b 100644
--- a/driver/charger/sy21612.h
+++ b/driver/charger/sy21612.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,7 +11,7 @@
 #include "gpio.h"
 
 #ifndef SY21612_ADDR_FLAGS
-#define SY21612_ADDR_FLAGS		0x71
+#define SY21612_ADDR_FLAGS 0x71
 #endif
 
 enum sy21612_switching_freq {
@@ -40,94 +40,94 @@ enum sy21612_vbus_adj {
 	SY21612_VBUS_5,
 };
 
-#define SY21612_CTRL1        0x00
-#define SY21612_CTRL1_REG_EN         BIT(7)
-#define SY21612_CTRL1_LOW_BAT_MASK   (7 << 4)
-#define SY21612_CTRL1_LOW_BAT_10_2V  (0 << 4)
-#define SY21612_CTRL1_LOW_BAT_10_7V  BIT(4)
-#define SY21612_CTRL1_LOW_BAT_11_2V  (2 << 4)
-#define SY21612_CTRL1_LOW_BAT_11_7V  (3 << 4)
-#define SY21612_CTRL1_LOW_BAT_22_0V  (4 << 4)
-#define SY21612_CTRL1_LOW_BAT_22_5V  (5 << 4)
-#define SY21612_CTRL1_LOW_BAT_23_0V  (6 << 4)
-#define SY21612_CTRL1_LOW_BAT_23_5V  (7 << 4)
-#define SY21612_CTRL1_ADC_EN         BIT(3)
-#define SY21612_CTRL1_ADC_AUTO_MODE  BIT(2)
-#define SY21612_CTRL1_VBUS_NDISCHG   BIT(1)
-
-#define SY21612_CTRL2        0x01
-#define SY21612_CTRL2_FREQ_MASK      (3 << 6)
-#define SY21612_CTRL2_FREQ_SHIFT     6
-#define SY21612_CTRL2_FREQ_250K      (0 << 6)
-#define SY21612_CTRL2_FREQ_500K      BIT(6)
-#define SY21612_CTRL2_FREQ_750K      (2 << 6)
-#define SY21612_CTRL2_FREQ_1M        (3 << 6)
-#define SY21612_CTRL2_VBUS_MASK      (7 << 3)
-#define SY21612_CTRL2_VBUS_SHIFT     3
-#define SY21612_CTRL2_VBUS_5V        (2 << 3)
-#define SY21612_CTRL2_VBUS_7V        (3 << 3)
-#define SY21612_CTRL2_VBUS_9V        (4 << 3)
-#define SY21612_CTRL2_VBUS_12V       (5 << 3)
-#define SY21612_CTRL2_VBUS_15V       (6 << 3)
-#define SY21612_CTRL2_VBUS_20V       (7 << 3)
-#define SY21612_CTRL2_VBUS_ADJ_MASK  7
+#define SY21612_CTRL1 0x00
+#define SY21612_CTRL1_REG_EN BIT(7)
+#define SY21612_CTRL1_LOW_BAT_MASK (7 << 4)
+#define SY21612_CTRL1_LOW_BAT_10_2V (0 << 4)
+#define SY21612_CTRL1_LOW_BAT_10_7V BIT(4)
+#define SY21612_CTRL1_LOW_BAT_11_2V (2 << 4)
+#define SY21612_CTRL1_LOW_BAT_11_7V (3 << 4)
+#define SY21612_CTRL1_LOW_BAT_22_0V (4 << 4)
+#define SY21612_CTRL1_LOW_BAT_22_5V (5 << 4)
+#define SY21612_CTRL1_LOW_BAT_23_0V (6 << 4)
+#define SY21612_CTRL1_LOW_BAT_23_5V (7 << 4)
+#define SY21612_CTRL1_ADC_EN BIT(3)
+#define SY21612_CTRL1_ADC_AUTO_MODE BIT(2)
+#define SY21612_CTRL1_VBUS_NDISCHG BIT(1)
+
+#define SY21612_CTRL2 0x01
+#define SY21612_CTRL2_FREQ_MASK (3 << 6)
+#define SY21612_CTRL2_FREQ_SHIFT 6
+#define SY21612_CTRL2_FREQ_250K (0 << 6)
+#define SY21612_CTRL2_FREQ_500K BIT(6)
+#define SY21612_CTRL2_FREQ_750K (2 << 6)
+#define SY21612_CTRL2_FREQ_1M (3 << 6)
+#define SY21612_CTRL2_VBUS_MASK (7 << 3)
+#define SY21612_CTRL2_VBUS_SHIFT 3
+#define SY21612_CTRL2_VBUS_5V (2 << 3)
+#define SY21612_CTRL2_VBUS_7V (3 << 3)
+#define SY21612_CTRL2_VBUS_9V (4 << 3)
+#define SY21612_CTRL2_VBUS_12V (5 << 3)
+#define SY21612_CTRL2_VBUS_15V (6 << 3)
+#define SY21612_CTRL2_VBUS_20V (7 << 3)
+#define SY21612_CTRL2_VBUS_ADJ_MASK 7
 #define SY21612_CTRL2_VBUS_ADJ_SHIFT 0
-#define SY21612_CTRL2_VBUS_ADJ_M2_5  0
+#define SY21612_CTRL2_VBUS_ADJ_M2_5 0
 #define SY21612_CTRL2_VBUS_ADJ_M1_25 1
-#define SY21612_CTRL2_VBUS_ADJ_0     2
-#define SY21612_CTRL2_VBUS_ADJ_1_25  3
-#define SY21612_CTRL2_VBUS_ADJ_2_5   4
-#define SY21612_CTRL2_VBUS_ADJ_3_75  5
-#define SY21612_CTRL2_VBUS_ADJ_5     6
-
-#define SY21612_PROT1        0x02
-#define SY21612_PROT1_I_THRESH_MASK   (7 << 5)
-#define SY21612_PROT1_I_THRESH_18MV   (0 << 5)
-#define SY21612_PROT1_I_THRESH_22MV   BIT(5)
-#define SY21612_PROT1_I_THRESH_27MV   (2 << 5)
-#define SY21612_PROT1_I_THRESH_31MV   (3 << 5)
-#define SY21612_PROT1_I_THRESH_36MV   (4 << 5)
-#define SY21612_PROT1_I_THRESH_45MV   (5 << 5)
-#define SY21612_PROT1_I_THRESH_54MV   (6 << 5)
-#define SY21612_PROT1_I_THRESH_64MV   (7 << 5)
+#define SY21612_CTRL2_VBUS_ADJ_0 2
+#define SY21612_CTRL2_VBUS_ADJ_1_25 3
+#define SY21612_CTRL2_VBUS_ADJ_2_5 4
+#define SY21612_CTRL2_VBUS_ADJ_3_75 5
+#define SY21612_CTRL2_VBUS_ADJ_5 6
+
+#define SY21612_PROT1 0x02
+#define SY21612_PROT1_I_THRESH_MASK (7 << 5)
+#define SY21612_PROT1_I_THRESH_18MV (0 << 5)
+#define SY21612_PROT1_I_THRESH_22MV BIT(5)
+#define SY21612_PROT1_I_THRESH_27MV (2 << 5)
+#define SY21612_PROT1_I_THRESH_31MV (3 << 5)
+#define SY21612_PROT1_I_THRESH_36MV (4 << 5)
+#define SY21612_PROT1_I_THRESH_45MV (5 << 5)
+#define SY21612_PROT1_I_THRESH_54MV (6 << 5)
+#define SY21612_PROT1_I_THRESH_64MV (7 << 5)
 #define SY21612_PROT1_OVP_THRESH_MASK (3 << 3)
-#define SY21612_PROT1_OVP_THRESH_110  (0 << 3)
-#define SY21612_PROT1_OVP_THRESH_115  BIT(3)
-#define SY21612_PROT1_OVP_THRESH_120  (2 << 3)
-#define SY21612_PROT1_OVP_THRESH_125  (3 << 3)
+#define SY21612_PROT1_OVP_THRESH_110 (0 << 3)
+#define SY21612_PROT1_OVP_THRESH_115 BIT(3)
+#define SY21612_PROT1_OVP_THRESH_120 (2 << 3)
+#define SY21612_PROT1_OVP_THRESH_125 (3 << 3)
 #define SY21612_PROT1_UVP_THRESH_MASK (3 << 1)
-#define SY21612_PROT1_UVP_THRESH_50   (0 << 1)
-#define SY21612_PROT1_UVP_THRESH_60   BIT(1)
-#define SY21612_PROT1_UVP_THRESH_70   (2 << 1)
-#define SY21612_PROT1_UVP_THRESH_80   (3 << 1)
-
-#define SY21612_PROT2        0x03
-#define SY21612_PROT2_I_LIMIT_MASK    (3 << 6)
-#define SY21612_PROT2_I_LIMIT_6A      (0 << 6)
-#define SY21612_PROT2_I_LIMIT_8A      (2 << 6)
-#define SY21612_PROT2_I_LIMIT_10A     (3 << 6)
+#define SY21612_PROT1_UVP_THRESH_50 (0 << 1)
+#define SY21612_PROT1_UVP_THRESH_60 BIT(1)
+#define SY21612_PROT1_UVP_THRESH_70 (2 << 1)
+#define SY21612_PROT1_UVP_THRESH_80 (3 << 1)
+
+#define SY21612_PROT2 0x03
+#define SY21612_PROT2_I_LIMIT_MASK (3 << 6)
+#define SY21612_PROT2_I_LIMIT_6A (0 << 6)
+#define SY21612_PROT2_I_LIMIT_8A (2 << 6)
+#define SY21612_PROT2_I_LIMIT_10A (3 << 6)
 #define SY21612_PROT2_OCP_AUTORECOVER BIT(5)
 #define SY21612_PROT2_UVP_AUTORECOVER BIT(4)
 #define SY21612_PROT2_OTP_AUTORECOVER BIT(3)
-#define SY21612_PROT2_SINK_MODE       BIT(2)
+#define SY21612_PROT2_SINK_MODE BIT(2)
 
-#define SY21612_STATE        0x04
-#define SY21612_STATE_POWER_GOOD      BIT(7)
-#define SY21612_STATE_VBAT_LT_VBUS    BIT(6)
-#define SY21612_STATE_VBAT_LOW        BIT(5)
+#define SY21612_STATE 0x04
+#define SY21612_STATE_POWER_GOOD BIT(7)
+#define SY21612_STATE_VBAT_LT_VBUS BIT(6)
+#define SY21612_STATE_VBAT_LOW BIT(5)
 
-#define SY21612_INT          0x05
-#define SY21612_INT_ADC_READY         BIT(7)
-#define SY21612_INT_VBUS_OCP          BIT(6)
-#define SY21612_INT_INDUCTOR_OCP      BIT(5)
-#define SY21612_INT_UVP               BIT(4)
-#define SY21612_INT_OTP               BIT(3)
+#define SY21612_INT 0x05
+#define SY21612_INT_ADC_READY BIT(7)
+#define SY21612_INT_VBUS_OCP BIT(6)
+#define SY21612_INT_INDUCTOR_OCP BIT(5)
+#define SY21612_INT_UVP BIT(4)
+#define SY21612_INT_OTP BIT(3)
 
 /* Battery voltage range: 0 ~ 25V */
-#define SY21612_VBAT_VOLT    0x06
+#define SY21612_VBAT_VOLT 0x06
 
 /* VBUS voltage range: 0 ~ 25V */
-#define SY21612_VBUS_VOLT    0x07
+#define SY21612_VBUS_VOLT 0x07
 
 /* Output current sense voltage range 0 ~ 67mV */
 #define SY21612_VBUS_CURRENT 0x08
diff --git a/driver/fingerprint/build.mk b/driver/fingerprint/build.mk
index 862fa29914..d0d92cb011 100644
--- a/driver/fingerprint/build.mk
+++ b/driver/fingerprint/build.mk
@@ -1,4 +1,4 @@
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -7,4 +7,5 @@
 # Note that this variable includes the trailing "/"
 _fingerprint_cur_dir:=$(dir $(lastword $(MAKEFILE_LIST)))
 
+include $(_fingerprint_cur_dir)elan/build.mk
 include $(_fingerprint_cur_dir)fpc/build.mk
diff --git a/driver/fingerprint/elan/build.mk b/driver/fingerprint/elan/build.mk
new file mode 100644
index 0000000000..791cce9e73
--- /dev/null
+++ b/driver/fingerprint/elan/build.mk
@@ -0,0 +1,20 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Build for ELAN fingerprint drivers
+
+# Note that this variable includes the trailing "/"
+_elan_cur_dir:=$(dir $(lastword $(MAKEFILE_LIST)))
+
+ifneq (,$(filter rw,$(CONFIG_FP_SENSOR_ELAN80) $(CONFIG_FP_SENSOR_ELAN515)))
+
+# Make sure output directory is created (in build directory)
+dirs-y+="$(_elan_cur_dir)"
+
+include $(_elan_cur_dir)../../../private/fingerprint/elan/build.mk
+
+all-obj-rw+=$(_elan_cur_dir)elan_private.o
+all-obj-rw+=$(_elan_cur_dir)elan_sensor_pal.o
+
+endif
diff --git a/driver/fingerprint/elan/elan_private.c b/driver/fingerprint/elan/elan_private.c
new file mode 100644
index 0000000000..1b56a1c9f5
--- /dev/null
+++ b/driver/fingerprint/elan/elan_private.c
@@ -0,0 +1,264 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "console.h"
+#include "cryptoc/util.h"
+#include "elan_sensor.h"
+#include "elan_sensor_pal.h"
+#include "elan_setting.h"
+#include "fpsensor.h"
+#include "fpsensor_utils.h"
+#include "gpio.h"
+#include "link_defs.h"
+#include "math_util.h"
+#include "shared_mem.h"
+#include "spi.h"
+#include "system.h"
+#include "timer.h"
+#include "trng.h"
+#include "util.h"
+
+#include <stddef.h>
+
+static uint16_t errors;
+
+/* Sensor description */
+static struct ec_response_fp_info ec_fp_sensor_info = {
+	/* Sensor identification */
+	.vendor_id = VID,
+	.product_id = PID,
+	.model_id = MID,
+	.version = VERSION,
+	/* Image frame characteristics */
+	.frame_size = FP_SENSOR_RES_X_ELAN * FP_SENSOR_RES_Y_ELAN,
+	.pixel_format = V4L2_PIX_FMT_GREY,
+	.width = FP_SENSOR_RES_X_ELAN,
+	.height = FP_SENSOR_RES_Y_ELAN,
+	.bpp = FP_SENSOR_RES_BPP_ELAN,
+};
+
+/**
+ * set fingerprint sensor into power saving mode
+ */
+void fp_sensor_low_power(void)
+{
+	elan_woe_mode();
+}
+
+/**
+ * Reset and initialize the sensor IC
+ */
+int fp_sensor_init(void)
+{
+	CPRINTF("========%s=======\n", __func__);
+
+	errors = 0;
+	elan_execute_reset();
+	algorithm_parameter_setting();
+	if (elan_execute_calibration() < 0)
+		errors |= FP_ERROR_INIT_FAIL;
+	if (elan_woe_mode() != 0)
+		errors |= FP_ERROR_SPI_COMM;
+
+	return EC_SUCCESS;
+}
+
+/**
+ * Deinitialize the sensor IC
+ */
+int fp_sensor_deinit(void)
+{
+	CPRINTF("========%s=======\n", __func__);
+	return elan_fp_deinit();
+}
+
+/**
+ * Fill the 'ec_response_fp_info' buffer with the sensor information
+ *
+ * @param[out] resp      retrieve the version, sensor and template information
+ *
+ * @return EC_SUCCESS on success otherwise error.
+ */
+int fp_sensor_get_info(struct ec_response_fp_info *resp)
+{
+	int ret = 0;
+
+	CPRINTF("========%s=======\n", __func__);
+	memcpy(resp, &ec_fp_sensor_info, sizeof(struct ec_response_fp_info));
+	elan_sensor_get_alg_info(resp);
+	resp->errors |= errors;
+	CPRINTF("##%s## FrameSize=%d, errors=0x%04x\n", __func__,
+		resp->frame_size, resp->errors);
+
+	return ret;
+}
+
+/**
+ * Compares given finger image against enrolled templates.
+ *
+ * @param[in]  templ            a pointer to the array of template buffers.
+ * @param[in]  templ_count      the number of buffers in the array of templates.
+ * @param[in]  image            the buffer containing the finger image
+ * @param[out] match_index      index of the matched finger in the template
+ *                              array if any.
+ * @param[out] update_bitmap    contains one bit per template, the bit is set if
+ *                              the match has updated the given template.
+ *
+ * @return negative value on error, else one of the following code :
+ * - EC_MKBP_FP_ERR_MATCH_NO on non-match
+ * - EC_MKBP_FP_ERR_MATCH_YES for match when template was not updated with
+ *   new data
+ * - EC_MKBP_FP_ERR_MATCH_YES_UPDATED for match when template was updated
+ * - EC_MKBP_FP_ERR_MATCH_YES_UPDATE_FAILED match, but update failed (not saved)
+ * - EC_MKBP_FP_ERR_MATCH_LOW_QUALITY when matching could not be performed due
+ *   to low image quality
+ * - EC_MKBP_FP_ERR_MATCH_LOW_COVERAGE when matching could not be performed
+ *   due to finger covering too little area of the sensor
+ */
+int fp_finger_match(void *templ, uint32_t templ_count, uint8_t *image,
+		    int32_t *match_index, uint32_t *update_bitmap)
+{
+	CPRINTF("========%s=======\n", __func__);
+	return elan_match(templ, templ_count, image, match_index,
+			  update_bitmap);
+}
+
+/**
+ * start a finger enrollment session and initialize enrollment data
+ *
+ * @return 0 on success.
+ *
+ */
+int fp_enrollment_begin(void)
+{
+	CPRINTF("========%s=======\n", __func__);
+	return elan_enrollment_begin();
+}
+
+/**
+ * Generate a template from the finger whose enrollment has just being
+ * completed.
+ *
+ * @param templ the buffer which will receive the template.
+ *              templ can be set to NULL to abort the current enrollment
+ *              process.
+ *
+ * @return 0 on success or a negative error code.
+ */
+int fp_enrollment_finish(void *templ)
+{
+	CPRINTF("========%s=======\n", __func__);
+	return elan_enrollment_finish(templ);
+}
+
+/**
+ * Adds fingerprint image to the current enrollment session.
+ *
+ * @param[in]  image             fingerprint image data
+ * @param[out] completion        retrieve percentage of current enrollment
+ *
+ * @return a negative value on error or one of the following codes:
+ * - EC_MKBP_FP_ERR_ENROLL_OK when image was successfully enrolled
+ * - EC_MKBP_FP_ERR_ENROLL_IMMOBILE when image added, but user should be
+ *   advised to move finger
+ * - EC_MKBP_FP_ERR_ENROLL_LOW_QUALITY when image could not be used due to
+ *   low image quality
+ * - EC_MKBP_FP_ERR_ENROLL_LOW_COVERAGE when image could not be used due to
+ *   finger covering too little area of the sensor
+ */
+int fp_finger_enroll(uint8_t *image, int *completion)
+{
+	CPRINTF("========%s=======\n", __func__);
+	return elan_enroll(image, completion);
+}
+
+/**
+ * Put the sensor in its lowest power state.
+ *
+ * fp_sensor_configure_detect needs to be called to restore finger detection
+ * functionality.
+ */
+void fp_sensor_configure_detect(void)
+{
+	CPRINTF("========%s=======\n", __func__);
+	elan_woe_mode();
+}
+
+/**
+ * Acquires a fingerprint image with specific capture mode.
+ *
+ * @param[out] image_data    Memory buffer to retrieve fingerprint image data
+ *                          Image_data is allocated by the caller and the size
+ *                          is FP_SENSOR_IMAGE_SIZE.
+ * @param[in]  mode         one of the FP_CAPTURE_ constants to get a specific
+ *                          image type
+ * - FP_CAPTURE_VENDOR_FORMAT: Full blown vendor-defined capture
+ * - FP_CAPTURE_SIMPLE_IMAGE: Simple raw image capture
+ * - FP_CAPTURE_PATTERN0: Self test pattern
+ * - FP_CAPTURE_PATTERN1: Self test pattern
+ * - FP_CAPTURE_QUALITY_TEST
+ * - FP_CAPTURE_RESET_TEST
+ * - FP_CAPTURE_TYPE_MAX
+ *
+ * @return
+ * - 0 on success
+ * - negative value on error
+ * - FP_SENSOR_LOW_IMAGE_QUALITY on image captured but quality is too low
+ * - FP_SENSOR_TOO_FAST on finger removed before image was captured
+ * - FP_SENSOR_LOW_SENSOR_COVERAGE on sensor not fully covered by finger
+ */
+int fp_sensor_acquire_image_with_mode(uint8_t *image_data, int mode)
+{
+	CPRINTF("========%s=======\n", __func__);
+	return elan_sensor_acquire_image_with_mode(image_data, mode);
+}
+
+/**
+ * Returns the status of the finger on the sensor.
+ *
+ * @return one of the following codes:
+ * - FINGER_NONE
+ * - FINGER_PARTIAL
+ * - FINGER_PRESENT
+ */
+enum finger_state fp_sensor_finger_status(void)
+{
+	CPRINTF("========%s=======\n", __func__);
+	return elan_sensor_finger_status();
+}
+
+/**
+ * Runs a test for defective pixels.
+ *
+ * Should be triggered periodically by the client. The maintenance command can
+ * take several hundred milliseconds to run.
+ *
+ * @return EC_ERROR_HW_INTERNAL on error (such as finger on sensor)
+ * @return EC_SUCCESS on success
+ */
+int fp_maintenance(void)
+{
+	CPRINTF("========%s=======\n", __func__);
+	return elan_fp_maintenance(&errors);
+}
+
+/**
+ * Provides the init_trng function required by the elan library using the EC
+ * trng API
+ */
+void init_trng(void)
+{
+	trng_init();
+}
+
+/**
+ * Provides the exit_trng function required by the elan library using the EC
+ * trng API
+ */
+void exit_trng(void)
+{
+	trng_exit();
+}
diff --git a/driver/fingerprint/elan/elan_sensor.h b/driver/fingerprint/elan/elan_sensor.h
new file mode 100644
index 0000000000..010d36a14c
--- /dev/null
+++ b/driver/fingerprint/elan/elan_sensor.h
@@ -0,0 +1,183 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef CROS_EC_DRIVER_FINGERPRINT_ELAN_ELAN_SENSOR_H
+#define CROS_EC_DRIVER_FINGERPRINT_ELAN_ELAN_SENSOR_H
+#include "common.h"
+#include "ec_commands.h"
+#include "fpsensor_types.h"
+
+/* Sensor pixel resolution */
+#if defined(CONFIG_FP_SENSOR_ELAN80)
+#define FP_SENSOR_IMAGE_SIZE_ELAN (80 * 80)
+#define FP_SENSOR_RES_X_ELAN 80
+#define FP_SENSOR_RES_Y_ELAN 80
+#if defined(CHIP_FAMILY_STM32F4)
+#define FP_ALGORITHM_TEMPLATE_SIZE_ELAN 15000
+#elif defined(CHIP_FAMILY_STM32H7)
+#define FP_ALGORITHM_TEMPLATE_SIZE_ELAN 40960
+#endif
+#define FP_MAX_FINGER_COUNT_ELAN 3
+#elif defined(CONFIG_FP_SENSOR_ELAN515)
+#define FP_SENSOR_IMAGE_SIZE_ELAN (52 * 150)
+#define FP_SENSOR_RES_X_ELAN 52
+#define FP_SENSOR_RES_Y_ELAN 150
+#if defined(CHIP_FAMILY_STM32F4)
+#define FP_ALGORITHM_TEMPLATE_SIZE_ELAN 15000
+#elif defined(CHIP_FAMILY_STM32H7)
+#define FP_ALGORITHM_TEMPLATE_SIZE_ELAN 67000
+#endif
+#define FP_MAX_FINGER_COUNT_ELAN 3
+#endif
+
+#define FP_SENSOR_IMAGE_OFFSET_ELAN (0)
+#define FP_SENSOR_RES_BPP_ELAN (8)
+
+/**
+ * Set ELAN fingerprint sensor into finger touch detects and power saving mode
+ *
+ * @return 0 on success.
+ *         negative value on error.
+ */
+int elan_woe_mode(void);
+
+/**
+ * Set ELAN fingerprint sensor into the image sensing mode
+ *
+ * @return 0 on success.
+ *         negative value on error.
+ */
+int elan_sensing_mode(void);
+
+/**
+ * To initialize parameters of the ELAN matching algorithm
+ *
+ */
+void algorithm_parameter_setting(void);
+
+/**
+ * Compares given finger image against enrolled templates.
+ *
+ * @param[in]  templ            a pointer to the array of template buffers.
+ * @param[in]  templ_count      the number of buffers in the array of templates.
+ * @param[in]  image            the buffer containing the finger image
+ * @param[out] match_index      index of the matched finger in the template
+ *                              array if any.
+ * @param[out] update_bitmap    contains one bit per template, the bit is set if
+ *                              the match has updated the given template.
+ *
+ * @return negative value on error, else one of the following code :
+ * - EC_MKBP_FP_ERR_MATCH_NO on non-match
+ * - EC_MKBP_FP_ERR_MATCH_YES for match when template was not updated with
+ *   new data
+ * - EC_MKBP_FP_ERR_MATCH_YES_UPDATED for match when template was updated
+ * - EC_MKBP_FP_ERR_MATCH_YES_UPDATE_FAILED match, but update failed (not saved)
+ * - EC_MKBP_FP_ERR_MATCH_LOW_QUALITY when matching could not be performed due
+ *   to low image quality
+ * - EC_MKBP_FP_ERR_MATCH_LOW_COVERAGE when matching could not be performed
+ *   due to finger covering too little area of the sensor
+ */
+int elan_match(void *templ, uint32_t templ_count, uint8_t *image,
+	       int32_t *match_index, uint32_t *update_bitmap);
+
+/**
+ * start a finger enrollment session and initialize enrollment data
+ *
+ * @return 0 on success.
+ *
+ */
+int elan_enrollment_begin(void);
+
+/**
+ * Adds fingerprint image to the current enrollment session.
+ *
+ * @param[in]  image        fingerprint image data
+ * @param[out] completion   retrieve percentage of current enrollment
+ *
+ * @return a negative value on error or one of the following codes:
+ * - EC_MKBP_FP_ERR_ENROLL_OK when image was successfully enrolled
+ * - EC_MKBP_FP_ERR_ENROLL_IMMOBILE when image added, but user should be
+     advised to move finger
+ * - EC_MKBP_FP_ERR_ENROLL_LOW_QUALITY when image could not be used due to
+ *   low image quality
+ * - EC_MKBP_FP_ERR_ENROLL_LOW_COVERAGE when image could not be used due to
+ *   finger covering too little area of the sensor
+ */
+int elan_enroll(uint8_t *image, int *completion);
+
+/**
+ * Acquires a fingerprint image with specific capture mode.
+ *
+ * @param[out] image_data   Memory buffer to retrieve fingerprint image data
+ *                          Image_data is allocated by the caller and the size
+ *                          is FP_SENSOR_IMAGE_SIZE.
+ * @param[in]  mode         one of the FP_CAPTURE_ constants to get a
+ *                          specific image type
+ * - FP_CAPTURE_VENDOR_FORMAT: Full blown vendor-defined capture
+ * - FP_CAPTURE_SIMPLE_IMAGE: Simple raw image capture
+ * - FP_CAPTURE_PATTERN0: Self test pattern
+ * - FP_CAPTURE_PATTERN1: Self test pattern
+ * - FP_CAPTURE_QUALITY_TEST
+ * - FP_CAPTURE_RESET_TEST
+ * - FP_CAPTURE_TYPE_MAX
+ *
+ * @return
+ * - 0 on success
+ * - negative value on error
+ * - FP_SENSOR_LOW_IMAGE_QUALITY on image captured but quality is too low
+ * - FP_SENSOR_TOO_FAST on finger removed before image was captured
+ * - FP_SENSOR_LOW_SENSOR_COVERAGE on sensor not fully covered by finger
+ */
+int elan_sensor_acquire_image_with_mode(uint8_t *image_data, int mode);
+
+/**
+ * Returns the status of the finger on the sensor.
+ *
+ * @return one of the following codes:
+ * - FINGER_NONE
+ * - FINGER_PARTIAL
+ * - FINGER_PRESENT
+ */
+enum finger_state elan_sensor_finger_status(void);
+
+/**
+ * Generate a template from the finger whose enrollment has just being
+ * completed.
+ *
+ * @param templ the buffer which will receive the template.
+ *              templ can be set to NULL to abort the current enrollment
+ *              process.
+ *
+ * @return 0 on success or a negative error code.
+ */
+int elan_enrollment_finish(void *templ);
+
+/**
+ * Fill the 'ec_response_fp_alg_info' buffer with the sensor alg information
+ *
+ * @param[out] resp      retrieve the algorithm information
+ *
+ * @return EC_SUCCESS on success otherwise error.
+ */
+int elan_sensor_get_alg_info(struct ec_response_fp_info *resp);
+
+/**
+ * Runs a test for defective pixels.
+ *
+ * Should be triggered periodically by the client. The maintenance command can
+ * take several hundred milliseconds to run.
+ *
+ * @return EC_ERROR_HW_INTERNAL on error (such as finger on sensor)
+ * @return EC_SUCCESS on success
+ */
+int elan_fp_maintenance(uint16_t *error_state);
+
+/**
+ * Deinitialize the sensor IC.
+ *
+ * @return EC_SUCCESS on success otherwise error.
+ */
+int elan_fp_deinit(void);
+#endif
diff --git a/driver/fingerprint/elan/elan_sensor_pal.c b/driver/fingerprint/elan/elan_sensor_pal.c
new file mode 100644
index 0000000000..f9fbcbd6e5
--- /dev/null
+++ b/driver/fingerprint/elan/elan_sensor_pal.c
@@ -0,0 +1,252 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* ELAN Platform Abstraction Layer callbacks */
+
+#include "common.h"
+#include "console.h"
+#include "cryptoc/util.h"
+#include "elan_sensor.h"
+#include "elan_sensor_pal.h"
+#include "elan_setting.h"
+#include "fpsensor.h"
+#include "gpio.h"
+#include "link_defs.h"
+#include "math_util.h"
+#include "shared_mem.h"
+#include "spi.h"
+#include "system.h"
+#include "timer.h"
+#include "util.h"
+
+#include <stddef.h>
+
+static uint8_t tx_buf[CONFIG_SPI_TX_BUF_SIZE] __uncached;
+static uint8_t rx_buf[CONFIG_SPI_RX_BUF_SIZE] __uncached;
+
+int elan_write_cmd(uint8_t fp_cmd)
+{
+	int rc = 0;
+
+	memset(tx_buf, 0, CONFIG_SPI_TX_BUF_SIZE);
+	memset(rx_buf, 0, CONFIG_SPI_RX_BUF_SIZE);
+
+	tx_buf[0] = fp_cmd;
+	rc = spi_transaction(&spi_devices[0], tx_buf, 2, rx_buf,
+			     SPI_READBACK_ALL);
+	return rc;
+}
+
+int elan_read_cmd(uint8_t fp_cmd, uint8_t *regdata)
+{
+	int ret = 0;
+
+	memset(tx_buf, 0, CONFIG_SPI_TX_BUF_SIZE);
+	memset(rx_buf, 0, CONFIG_SPI_RX_BUF_SIZE);
+
+	tx_buf[0] = fp_cmd; /* one byte data read */
+	ret = spi_transaction(&spi_devices[0], tx_buf, 2, rx_buf,
+			      SPI_READBACK_ALL);
+	*regdata = rx_buf[1];
+
+	return ret;
+}
+
+int elan_spi_transaction(uint8_t *tx, int tx_len, uint8_t *rx, int rx_len)
+{
+	int ret = 0;
+
+	memset(tx_buf, 0, CONFIG_SPI_TX_BUF_SIZE);
+	memset(rx_buf, 0, CONFIG_SPI_RX_BUF_SIZE);
+
+	memcpy(tx_buf, tx, tx_len);
+	ret = spi_transaction(&spi_devices[0], tx_buf, tx_len, rx_buf, rx_len);
+	memcpy(rx, rx_buf, rx_len);
+
+	return ret;
+}
+
+int elan_write_register(uint8_t regaddr, uint8_t regdata)
+{
+	int ret = 0;
+
+	memset(tx_buf, 0, CONFIG_SPI_TX_BUF_SIZE);
+	memset(rx_buf, 0, CONFIG_SPI_RX_BUF_SIZE);
+
+	tx_buf[0] = WRITE_REG_HEAD + regaddr; /* one byte data write */
+	tx_buf[1] = regdata;
+	ret = spi_transaction(&spi_devices[0], tx_buf, 2, rx_buf,
+			      SPI_READBACK_ALL);
+	return ret;
+}
+
+int elan_write_page(uint8_t page)
+{
+	int ret = 0;
+
+	memset(tx_buf, 0, CONFIG_SPI_TX_BUF_SIZE);
+	memset(rx_buf, 0, CONFIG_SPI_RX_BUF_SIZE);
+
+	tx_buf[0] = PAGE_SEL;
+	tx_buf[1] = page;
+	ret = spi_transaction(&spi_devices[0], tx_buf, 2, rx_buf,
+			      SPI_READBACK_ALL);
+
+	return ret;
+}
+
+int elan_write_reg_vector(const uint8_t *reg_table, int length)
+{
+	int ret = 0;
+	int i = 0;
+	uint8_t write_regaddr;
+	uint8_t write_regdata;
+
+	for (i = 0; i < length; i = i + 2) {
+		write_regaddr = reg_table[i];
+		write_regdata = reg_table[i + 1];
+		ret = elan_write_register(write_regaddr, write_regdata);
+		if (ret < 0)
+			break;
+	}
+	return ret;
+}
+
+int raw_capture(uint16_t *short_raw)
+{
+	int ret = 0, i = 0, image_index = 0, index = 0;
+	int cnt_timer = 0;
+	int dma_loop = 0, dma_len = 0;
+	uint8_t regdata[4] = { 0 };
+	char *img_buf;
+
+	memset(short_raw, 0, sizeof(uint16_t) * IMAGE_TOTAL_PIXEL);
+
+	ret = shared_mem_acquire(sizeof(uint8_t) * IMG_BUF_SIZE, &img_buf);
+	if (ret) {
+		LOGE_SA("%s Can't get shared mem\n", __func__);
+		return ret;
+	}
+	memset(img_buf, 0, sizeof(uint8_t) * IMG_BUF_SIZE);
+
+	/* Write start scans command to fp sensor */
+	if (elan_write_cmd(START_SCAN) < 0) {
+		ret = ELAN_ERROR_SPI;
+		LOGE_SA("%s SPISendCommand( SSP2, START_SCAN ) fail ret = %d",
+			__func__, ret);
+		goto exit;
+	}
+
+	/* Polling scan status */
+	cnt_timer = 0;
+	while (1) {
+		usleep(1000);
+		cnt_timer++;
+		regdata[0] = SENSOR_STATUS;
+		elan_spi_transaction(regdata, 2, regdata, 2);
+		if (regdata[0] & 0x04)
+			break;
+
+		if (cnt_timer > POLLING_SCAN_TIMER) {
+			ret = ELAN_ERROR_SCAN;
+			LOGE_SA("%s regdata = 0x%x, fail ret = %d", __func__,
+				regdata[0], ret);
+			goto exit;
+		}
+	}
+
+	/* Read the image from fp sensor */
+	dma_loop = 4;
+	dma_len = IMG_BUF_SIZE / dma_loop;
+
+	for (i = 0; i < dma_loop; i++) {
+		memset(tx_buf, 0, CONFIG_SPI_TX_BUF_SIZE);
+		memset(rx_buf, 0, CONFIG_SPI_RX_BUF_SIZE);
+		tx_buf[0] = START_READ_IMAGE;
+		ret = spi_transaction(&spi_devices[0], tx_buf, 2, rx_buf,
+				      dma_len);
+		memcpy(&img_buf[dma_len * i], rx_buf, dma_len);
+	}
+
+	/* Remove dummy byte */
+	for (image_index = 1; image_index < IMAGE_WIDTH; image_index++)
+		memcpy(&img_buf[RAW_PIXEL_SIZE * image_index],
+		       &img_buf[RAW_DATA_SIZE * image_index], RAW_PIXEL_SIZE);
+
+	for (index = 0; index < IMAGE_TOTAL_PIXEL; index++)
+		short_raw[index] =
+			(img_buf[index * 2] << 8) + img_buf[index * 2 + 1];
+
+exit:
+	if (img_buf != NULL) {
+		always_memset(img_buf, 0, sizeof(uint8_t) * IMG_BUF_SIZE);
+		shared_mem_release(img_buf);
+	}
+
+	if (ret != 0)
+		LOGE_SA("%s error = %d", __func__, ret);
+
+	return ret;
+}
+
+int elan_execute_calibration(void)
+{
+	int retry_time = 0;
+	int ret = 0;
+
+	while (retry_time < REK_TIMES) {
+		elan_write_cmd(SRST);
+		elan_write_cmd(FUSE_LOAD);
+		register_initialization();
+		elan_sensing_mode();
+
+		ret = calibration();
+		if (ret == 0)
+			break;
+
+		retry_time++;
+	}
+
+	return ret;
+}
+
+int elan_fp_maintenance(uint16_t *error_state)
+{
+	int rv;
+	fp_sensor_info_t sensor_info;
+	timestamp_t start = get_time();
+
+	if (error_state == NULL)
+		return EC_ERROR_INVAL;
+
+	/* Initial status */
+	*error_state &= 0xFC00;
+	sensor_info.num_defective_pixels = 0;
+	sensor_info.sensor_error_code = 0;
+	rv = fp_sensor_maintenance(&sensor_info);
+	LOGE_SA("Maintenance took %d ms", time_since32(start) / MSEC);
+
+	if (rv != 0) {
+		/*
+		 * Failure can occur if any of the fingerprint detection zones
+		 * are covered (i.e., finger is on sensor).
+		 */
+		LOGE_SA("Failed to run maintenance: %d", rv);
+		return EC_ERROR_HW_INTERNAL;
+	}
+	if (sensor_info.num_defective_pixels >= FP_ERROR_DEAD_PIXELS_UNKNOWN)
+		*error_state = FP_ERROR_DEAD_PIXELS_UNKNOWN;
+	else
+		*error_state |=
+			FP_ERROR_DEAD_PIXELS(sensor_info.num_defective_pixels);
+	LOGE_SA("num_defective_pixels: %d", sensor_info.num_defective_pixels);
+	LOGE_SA("sensor_error_code: %d", sensor_info.sensor_error_code);
+
+	return EC_SUCCESS;
+}
+
+void __unused elan_sensor_set_rst(bool state)
+{
+	gpio_set_level(GPIO_FP_RST_ODL, state ? 0 : 1);
+}
diff --git a/driver/fingerprint/elan/elan_sensor_pal.h b/driver/fingerprint/elan/elan_sensor_pal.h
new file mode 100644
index 0000000000..235dcd5fa8
--- /dev/null
+++ b/driver/fingerprint/elan/elan_sensor_pal.h
@@ -0,0 +1,141 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* ELAN Platform Abstraction Layer callbacks */
+
+#ifndef ELAN_SENSOR_PAL_H_
+#define ELAN_SENSOR_PAL_H_
+
+/* ELAN error codes */
+enum elan_error_code {
+	ELAN_ERROR_NONE = 0,
+	ELAN_ERROR_SPI = 1,
+	ELAN_ERROR_SCAN = 2,
+	ELAN_ERROR_CAL = 3,
+	ELAN_ERROR_DEFECT_NUM = 4,
+	ELAN_ERROR_DEFECT_X = 5,
+	ELAN_ERROR_DEFECT_Y = 6
+};
+
+/* ELAN error info */
+typedef struct {
+	uint32_t num_defective_pixels;
+	uint16_t sensor_error_code;
+} fp_sensor_info_t;
+
+/**
+ * @brief Write fp command to the sensor
+ *
+ * @param[in] fp_cmd     One byte fp command to write
+ *
+ * @return 0 on success.
+ *         negative value on error.
+ */
+int elan_write_cmd(uint8_t fp_cmd);
+
+/**
+ * @brief Read fp register data from the sensor
+ *
+ * @param[in]   fp_cmd   One byte fp command to read
+ * @param[out]  regdata  One byte data where register's data will be stored
+ *
+ * @return 0 on success.
+ *         negative value on error.
+ */
+int elan_read_cmd(uint8_t fp_cmd, uint8_t *regdata);
+
+/**
+ * @brief Transfers and receives SPI data.
+ *
+ * @param[in]   tx              The buffer to transfer
+ * @param[in]   tx_len          The length to transfer
+ * @param[out]  rx              The buffer where read data will be stored
+ * @param[in]   rx_len          The length to receive
+ * @return 0 on success.
+ *         negative value on error.
+ */
+int elan_spi_transaction(uint8_t *tx, int tx_len, uint8_t *rx, int rx_len);
+
+/**
+ * @brief Write fp register data to sensor
+ *
+ * @param[in]    regaddr  One byte register address to write
+ * @param[in]    regdata  Data to write to register
+ *
+ * @return 0 on success.
+ *         negative value on error.
+ */
+int elan_write_register(uint8_t regaddr, uint8_t regdata);
+
+/**
+ * @brief Select sensor RAM page of register
+ *
+ * @param[in]   page    The number of RAM page control registers
+ *
+ * @return 0 on success.
+ *         negative value on error.
+ */
+int elan_write_page(uint8_t page);
+
+/**
+ * @brief Write register table to fp sensor
+ *
+ * Using a table to write data to sensor register.
+ * This table contains multiple pairs of address and data to
+ * be written.
+ *
+ * @param[in]    reg_table       The register address to write
+ * @param[in]    length          The data to write to register
+ *
+ * @return 0 on success.
+ *         negative value on error.
+ */
+int elan_write_reg_vector(const uint8_t *reg_table, int length);
+
+/**
+ * Get 14bits raw image data from ELAN fingerprint sensor
+ *
+ * @param[out] short_raw    The memory buffer to receive fingerprint image
+ *                          raw data, buffer length is:
+ *                          (IMAGE_WIDTH*IMAGE_HEIGHT)*sizeof(uint16_t)
+ *
+ * @return 0 on success.
+ *         negative value on error.
+ */
+int raw_capture(uint16_t *short_raw);
+
+/**
+ * Execute calibrate ELAN fingerprint sensor flow.
+ *
+ * @return 0 on success.
+ *         negative value on error.
+ */
+int elan_execute_calibration(void);
+
+/**
+ * Execute reset ELAN fingerprint sensor flow.
+ */
+void elan_execute_reset(void);
+
+/**
+ * Runs a test for defective pixels.
+ *
+ * @param[out] fp_sensor_info  Structure containing output data.
+ *
+ * @return 0 on success.
+ *         negative value on error.
+ */
+int fp_sensor_maintenance(fp_sensor_info_t *fp_sensor_info);
+
+/**
+ * @brief Set sensor reset state.
+ *
+ * Set sensor reset state.
+ *
+ * @param[in] state Reset state.
+ *                  true  => reset sensor, i.e. low GPIO state
+ *                  false => normal operation, i.e. high GPIO state
+ */
+void __unused elan_sensor_set_rst(bool state);
+#endif
diff --git a/driver/fingerprint/elan/elan_setting.h b/driver/fingerprint/elan/elan_setting.h
new file mode 100644
index 0000000000..7e62653b8f
--- /dev/null
+++ b/driver/fingerprint/elan/elan_setting.h
@@ -0,0 +1,101 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef ELAN_SETTING_H
+#define ELAN_SETTING_H
+
+#include <stdint.h>
+
+/* The hardware ID information and FW version */
+#define VID 0x04F3
+#define PID 0x0903
+#define MID 0x01
+#define VERSION 0x100B
+
+/* SPI tx and rx buffer size */
+#define CONFIG_SPI_TX_BUF_SIZE 1024
+#define CONFIG_SPI_RX_BUF_SIZE 5120
+
+/**
+ * Elan sensor operation is controlled by sending commands and receiving
+ * through the SPI interface. There are several SPI command codes for
+ * controlling FP sensor:
+ *
+ * - START_SCAN            Start scan
+ * - START_READ_IMAGE      Start read the image
+ * - SRST                  Software reset
+ * - FUSE_LOAD             Load OTP trims data to control registers
+ * - READ_REG_HEAD         Register single read
+ * - WRITE_REG_HEAD        Register burst write
+ * - READ_SERIER_REG_HEAD  Register burst read
+ * - PAGE_SEL              Register page selection
+ * - SENSOR_STATUS         Read sensor status
+ */
+#define START_SCAN 0x01
+#define START_READ_IMAGE 0x10
+#define SRST 0x31
+#define FUSE_LOAD 0x04
+#define READ_REG_HEAD 0x40
+#define WRITE_REG_HEAD 0x80
+#define READ_SERIER_REG_HEAD 0xC0
+#define PAGE_SEL 0x07
+#define SENSOR_STATUS 0x03
+
+/* Sensor type name */
+#define EFSA515 1
+#define EFSA80SC 2
+#if defined(CONFIG_FP_SENSOR_ELAN80)
+#define IC_SELECTION EFSA80SC
+#elif defined(CONFIG_FP_SENSOR_ELAN515)
+#define IC_SELECTION EFSA515
+#endif
+
+/* Sensor pixel resolution */
+#if (IC_SELECTION == EFSA80SC)
+#define IMAGE_WIDTH 80
+#define IMAGE_HEIGHT 80
+#elif (IC_SELECTION == EFSA515)
+#define IMAGE_WIDTH 150
+#define IMAGE_HEIGHT 52
+#endif
+
+/**
+ * Sensor real image size:
+ * ((IMAGE_HEIGHT * ONE_PIXEL_BYTE) + FP_DUMMY_BYTE) * IMAGE_WIDTH
+ */
+#define FP_DUMMY_BYTE 2
+#define ONE_PIXEL_BYTE 2
+#define IMAGE_TOTAL_PIXEL (IMAGE_WIDTH * IMAGE_HEIGHT)
+#define RAW_PIXEL_SIZE (IMAGE_HEIGHT * ONE_PIXEL_BYTE)
+#define RAW_DATA_SIZE (RAW_PIXEL_SIZE + FP_DUMMY_BYTE)
+#define IMG_BUF_SIZE (RAW_DATA_SIZE * IMAGE_WIDTH)
+
+/* Polling scan status counter */
+#define POLLING_SCAN_TIMER 10000
+
+/* Re-calibration timer */
+#define REK_TIMES 3
+
+/* Console output macros */
+#define LOGE_SA(format, args...) cprints(CC_FP, format, ##args)
+
+/**
+ * Set ELAN fingerprint sensor register initialization
+ *
+ * @return 0 on success.
+ *         negative value on error.
+ */
+int register_initialization(void);
+
+/**
+ * To calibrate ELAN fingerprint sensor and keep the calibration results
+ * for correcting fingerprint image data
+ *
+ * @return 0 on success.
+ *         negative value on error.
+ */
+int calibration(void);
+
+#endif /* _ELAN_SETTING_H */
diff --git a/driver/fingerprint/fpc/bep/build.mk b/driver/fingerprint/fpc/bep/build.mk
index ac7f05fb60..ac5879a913 100644
--- a/driver/fingerprint/fpc/bep/build.mk
+++ b/driver/fingerprint/fpc/bep/build.mk
@@ -1,4 +1,4 @@
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/driver/fingerprint/fpc/bep/fpc1025_private.h b/driver/fingerprint/fpc/bep/fpc1025_private.h
index 2da127741f..3024a5ac39 100644
--- a/driver/fingerprint/fpc/bep/fpc1025_private.h
+++ b/driver/fingerprint/fpc/bep/fpc1025_private.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,32 +7,33 @@
 #define __CROS_EC_FPC1025_PRIVATE_H
 
 /* The 16-bit hardware ID is 0x021y */
-#define FP_SENSOR_HWID 0x021
+#define FP_SENSOR_HWID_FPC 0x021
 
 /* Sensor type name */
-#define FP_SENSOR_NAME "FPC1025"
+#define FP_SENSOR_NAME_FPC "FPC1025"
 
 /* Sensor pixel resolution */
-#define FP_SENSOR_RES_X     (160) /**< Sensor width                          */
-#define FP_SENSOR_RES_Y     (160) /**< Sensor height                         */
-#define FP_SENSOR_RES_BPP   (8)   /**< Resolution bits per pixel             */
+#define FP_SENSOR_RES_X_FPC (160) /**< Sensor width */
+#define FP_SENSOR_RES_Y_FPC (160) /**< Sensor height */
+#define FP_SENSOR_RES_BPP_FPC (8) /**< Resolution bits per pixel */
 
 /*
  * Sensor image size
  *
  * Value from fpc_bep_image_get_buffer_size(): (160*160)+660
  */
-#define FP_SENSOR_IMAGE_SIZE        (26260)
-#define FP_SENSOR_REAL_IMAGE_SIZE   (FP_SENSOR_RES_X * FP_SENSOR_RES_Y)
+#define FP_SENSOR_IMAGE_SIZE_FPC (26260)
+#define FP_SENSOR_REAL_IMAGE_SIZE_FPC \
+	(FP_SENSOR_RES_X_FPC * FP_SENSOR_RES_Y_FPC)
 /* Offset of image data in fp_buffer */
-#define FP_SENSOR_IMAGE_OFFSET      (400)
+#define FP_SENSOR_IMAGE_OFFSET_FPC (400)
 
 /*
  * Constant value for the enrollment data size
  *
  * Size of private fp_bio_enrollment_t
  */
-#define FP_ALGORITHM_ENROLLMENT_SIZE (4)
+#define FP_ALGORITHM_ENROLLMENT_SIZE_FPC (4)
 
 /*
  * Constant value corresponding to the maximum template size
@@ -41,9 +42,11 @@
  *
  * Template size + alignment padding + size of template size variable
  */
-#define FP_ALGORITHM_TEMPLATE_SIZE      (5088 + 0 + 4)
+#define FP_ALGORITHM_TEMPLATE_SIZE_FPC (5088 + 0 + 4)
 
 /* Max number of templates stored / matched against */
-#define FP_MAX_FINGER_COUNT     (5)
+#ifndef FP_MAX_FINGER_COUNT_FPC
+#define FP_MAX_FINGER_COUNT_FPC (5)
+#endif
 
 #endif /* __CROS_EC_FPC1025_PRIVATE_H */
diff --git a/driver/fingerprint/fpc/bep/fpc1035_private.h b/driver/fingerprint/fpc/bep/fpc1035_private.h
index 695228898b..2bf14f9ca2 100644
--- a/driver/fingerprint/fpc/bep/fpc1035_private.h
+++ b/driver/fingerprint/fpc/bep/fpc1035_private.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,32 +7,33 @@
 #define __CROS_EC_FPC1035_PRIVATE_H
 
 /* The 16-bit hardware ID is 0x011y */
-#define FP_SENSOR_HWID 0x011
+#define FP_SENSOR_HWID_FPC 0x011
 
 /* Sensor type name */
-#define FP_SENSOR_NAME "FPC1035"
+#define FP_SENSOR_NAME_FPC "FPC1035"
 
 /* Sensor pixel resolution */
-#define FP_SENSOR_RES_X     (112) /**< Sensor width                          */
-#define FP_SENSOR_RES_Y     (88)  /**< Sensor height                         */
-#define FP_SENSOR_RES_BPP   (8)   /**< Resolution bits per pixel             */
+#define FP_SENSOR_RES_X_FPC (112) /**< Sensor width */
+#define FP_SENSOR_RES_Y_FPC (88) /**< Sensor height */
+#define FP_SENSOR_RES_BPP_FPC (8) /**< Resolution bits per pixel */
 
 /*
  * Sensor image size
  *
  * Value from fpc_bep_image_get_buffer_size(): (112*88)+660
  */
-#define FP_SENSOR_IMAGE_SIZE        (10516)
-#define FP_SENSOR_REAL_IMAGE_SIZE   (FP_SENSOR_RES_X * FP_SENSOR_RES_Y)
+#define FP_SENSOR_IMAGE_SIZE_FPC (10516)
+#define FP_SENSOR_REAL_IMAGE_SIZE_FPC \
+	(FP_SENSOR_RES_X_FPC * FP_SENSOR_RES_Y_FPC)
 /* Offset of image data in fp_buffer */
-#define FP_SENSOR_IMAGE_OFFSET      (400)
+#define FP_SENSOR_IMAGE_OFFSET_FPC (400)
 
 /*
  * Constant value for the enrollment data size
  *
  * Size of private fp_bio_enrollment_t
  */
-#define FP_ALGORITHM_ENROLLMENT_SIZE (4)
+#define FP_ALGORITHM_ENROLLMENT_SIZE_FPC (4)
 
 /*
  * Constant value corresponding to the maximum template size
@@ -41,9 +42,9 @@
  *
  * Template size + alignment padding + size of template size variable
  */
-#define FP_ALGORITHM_TEMPLATE_SIZE      (14373 + 3 + 4)
+#define FP_ALGORITHM_TEMPLATE_SIZE_FPC (14373 + 3 + 4)
 
 /* Max number of templates stored / matched against */
-#define FP_MAX_FINGER_COUNT     (5)
+#define FP_MAX_FINGER_COUNT_FPC (5)
 
 #endif /* __CROS_EC_FPC1035_PRIVATE_H */
diff --git a/driver/fingerprint/fpc/bep/fpc_bio_algorithm.h b/driver/fingerprint/fpc/bep/fpc_bio_algorithm.h
index 1bf598a3ee..1da01d0a08 100644
--- a/driver/fingerprint/fpc/bep/fpc_bio_algorithm.h
+++ b/driver/fingerprint/fpc/bep/fpc_bio_algorithm.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -66,12 +66,12 @@ int bio_algorithm_exit(void);
  * - BIO_TEMPLATE_LOW_COVERAGE when matching could not be performed due to
  *   finger covering too little area of the sensor
  */
-#define BIO_TEMPLATE_NO_MATCH            0
-#define BIO_TEMPLATE_MATCH               1
-#define BIO_TEMPLATE_MATCH_UPDATED       3
+#define BIO_TEMPLATE_NO_MATCH 0
+#define BIO_TEMPLATE_MATCH 1
+#define BIO_TEMPLATE_MATCH_UPDATED 3
 #define BIO_TEMPLATE_MATCH_UPDATE_FAILED 5
-#define BIO_TEMPLATE_LOW_QUALITY         2
-#define BIO_TEMPLATE_LOW_COVERAGE        4
+#define BIO_TEMPLATE_LOW_QUALITY 2
+#define BIO_TEMPLATE_LOW_COVERAGE 4
 
 int bio_template_image_match_list(bio_template_t templ, uint32_t num_templ,
 				  bio_image_t image, int32_t *match_index,
@@ -101,14 +101,14 @@ int bio_enrollment_begin(bio_enrollment_t *enrollment);
  *   finger covering too little area of the sensor
  * - BIO_ENROLLMENT_INTERNAL_ERROR when an internal error occurred
  */
-#define BIO_ENROLLMENT_OK               0
-#define BIO_ENROLLMENT_LOW_QUALITY      1
-#define BIO_ENROLLMENT_IMMOBILE         2
-#define BIO_ENROLLMENT_LOW_COVERAGE     3
-#define BIO_ENROLLMENT_INTERNAL_ERROR   5
+#define BIO_ENROLLMENT_OK 0
+#define BIO_ENROLLMENT_LOW_QUALITY 1
+#define BIO_ENROLLMENT_IMMOBILE 2
+#define BIO_ENROLLMENT_LOW_COVERAGE 3
+#define BIO_ENROLLMENT_INTERNAL_ERROR 5
 
 /* Can be used to detect if image was usable for enrollment or not. */
-#define BIO_ENROLLMENT_PROBLEM_MASK     1
+#define BIO_ENROLLMENT_PROBLEM_MASK 1
 int bio_enrollment_add_image(bio_enrollment_t enrollment, bio_image_t image);
 /*
  * Returns percent of coverage accumulated during enrollment process.
diff --git a/driver/fingerprint/fpc/bep/fpc_misc.c b/driver/fingerprint/fpc/bep/fpc_misc.c
index c4c779b702..6b716e0524 100644
--- a/driver/fingerprint/fpc/bep/fpc_misc.c
+++ b/driver/fingerprint/fpc/bep/fpc_misc.c
@@ -1,16 +1,16 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* FPC Platform Abstraction Layer */
 
-#include <stdint.h>
-#include <stddef.h>
-
 #include "shared_mem.h"
 #include "uart.h"
 
+#include <stddef.h>
+#include <stdint.h>
+
 void __unused *fpc_malloc(uint32_t size)
 {
 	char *data;
@@ -44,8 +44,3 @@ void __unused fpc_log_var(const char *source, uint8_t level, const char *format,
 	uart_vprintf(format, args);
 	va_end(args);
 }
-
-uint32_t abs(int32_t a)
-{
-	return (a < 0) ? (uint32_t)(-a) : (uint32_t)a;
-}
diff --git a/driver/fingerprint/fpc/bep/fpc_private.c b/driver/fingerprint/fpc/bep/fpc_private.c
index 36ca0fe1b9..007b7692b9 100644
--- a/driver/fingerprint/fpc/bep/fpc_private.c
+++ b/driver/fingerprint/fpc/bep/fpc_private.c
@@ -1,25 +1,22 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <stdint.h>
-#include <stddef.h>
-
+#include "driver/fingerprint/fpc/fpc_sensor.h"
 #include "fpc_bio_algorithm.h"
 #include "fpsensor.h"
+#include "fpsensor_utils.h"
 #include "gpio.h"
 #include "spi.h"
 #include "system.h"
 #include "util.h"
 
-#include "driver/fingerprint/fpc/fpc_sensor.h"
-
-/* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_FP, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_FP, format, ## args)
+#include <stddef.h>
+#include <stdint.h>
 
-static uint8_t enroll_ctx[FP_ALGORITHM_ENROLLMENT_SIZE] = {0};
+static uint8_t
+	enroll_ctx[FP_ALGORITHM_ENROLLMENT_SIZE_FPC] __aligned(4) = { 0 };
 
 /* Recorded error flags */
 static uint16_t errors;
@@ -42,11 +39,11 @@ static struct ec_response_fp_info ec_fp_sensor_info = {
 	.model_id = 1,
 	.version = 1,
 	/* Image frame characteristics */
-	.frame_size = FP_SENSOR_IMAGE_SIZE,
+	.frame_size = FP_SENSOR_IMAGE_SIZE_FPC,
 	.pixel_format = V4L2_PIX_FMT_GREY,
-	.width = FP_SENSOR_RES_X,
-	.height = FP_SENSOR_RES_Y,
-	.bpp = FP_SENSOR_RES_BPP,
+	.width = FP_SENSOR_RES_X_FPC,
+	.height = FP_SENSOR_RES_Y_FPC,
+	.bpp = FP_SENSOR_RES_BPP_FPC,
 };
 
 typedef struct fpc_bep_sensor fpc_bep_sensor_t;
@@ -63,12 +60,12 @@ extern const fpc_bep_algorithm_t fpc_bep_algorithm_pfe_1025;
 
 const fpc_sensor_info_t fpc_sensor_info = {
 	.sensor = &fpc_bep_sensor_1025,
-	.image_buffer_size = FP_SENSOR_IMAGE_SIZE,
+	.image_buffer_size = FP_SENSOR_IMAGE_SIZE_FPC,
 };
 
 const fpc_bio_info_t fpc_bio_info = {
 	.algorithm = &fpc_bep_algorithm_pfe_1025,
-	.template_size = FP_ALGORITHM_TEMPLATE_SIZE,
+	.template_size = FP_ALGORITHM_TEMPLATE_SIZE_FPC,
 };
 
 #elif defined(CONFIG_FP_SENSOR_FPC1035)
@@ -91,8 +88,8 @@ const fpc_bio_info_t fpc_bio_info = {
 
 /* Sensor IC commands */
 enum fpc_cmd {
-	FPC_CMD_DEEPSLEEP         = 0x2C,
-	FPC_CMD_HW_ID             = 0xFC,
+	FPC_CMD_DEEPSLEEP = 0x2C,
+	FPC_CMD_HW_ID = 0xFC,
 };
 
 /* Maximum size of a sensor command SPI transfer */
@@ -114,10 +111,13 @@ void fp_sensor_low_power(void)
 	fpc_send_cmd(FPC_CMD_DEEPSLEEP);
 }
 
-static int fpc_check_hwid(void)
+int fpc_get_hwid(uint16_t *id)
 {
-	uint16_t id;
 	int rc;
+	uint16_t sensor_id;
+
+	if (id == NULL)
+		return EC_ERROR_INVAL;
 
 	spi_buf[0] = FPC_CMD_HW_ID;
 
@@ -128,14 +128,26 @@ static int fpc_check_hwid(void)
 		return FP_ERROR_SPI_COMM;
 	}
 
-	id = (spi_buf[1] << 8) | spi_buf[2];
-	if ((id >> 4) != FP_SENSOR_HWID) {
+	sensor_id = ((spi_buf[1] << 8) | spi_buf[2]);
+	*id = sensor_id;
+
+	return EC_SUCCESS;
+}
+
+int fpc_check_hwid(void)
+{
+	uint16_t id = 0;
+	int status;
+
+	status = fpc_get_hwid(&id);
+	if ((id >> 4) != FP_SENSOR_HWID_FPC) {
 		CPRINTS("FPC unknown silicon 0x%04x", id);
 		return FP_ERROR_BAD_HWID;
 	}
-	CPRINTS(FP_SENSOR_NAME " id 0x%04x", id);
+	if (status == EC_SUCCESS)
+		CPRINTS(FP_SENSOR_NAME_FPC " id 0x%04x", id);
 
-	return EC_SUCCESS;
+	return status;
 }
 
 /* Reset and initialize the sensor IC */
@@ -143,12 +155,6 @@ int fp_sensor_init(void)
 {
 	int rc;
 
-	/* The dragonclaw development board needs this enabled to enable the
-	 * AND gate (U10) to CS. Production boards could disable this to save
-	 * power since it's only needed for initial detection on those boards.
-	 */
-	gpio_set_level(GPIO_DIVIDER_HIGHSIDE, 1);
-
 	/* Print the binary libfpbep.a library version */
 	CPRINTS("FPC libfpbep.a %s", fp_sensor_get_version());
 
diff --git a/driver/fingerprint/fpc/bep/fpc_private.h b/driver/fingerprint/fpc/bep/fpc_private.h
index 5334779672..8975b89916 100644
--- a/driver/fingerprint/fpc/bep/fpc_private.h
+++ b/driver/fingerprint/fpc/bep/fpc_private.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,8 +8,113 @@
 #ifndef __CROS_EC_FPC_PRIVATE_H
 #define __CROS_EC_FPC_PRIVATE_H
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 #include <stdint.h>
 
+/** @brief Common results returned by BEP functions.
+ *
+ * BEP config/usage errors:
+ * Examples: Incorrect arguments/parameters when calling BEP API
+ * functions; functions called in incorrect order.
+ * Action: Fix SW bug.
+ * FPC_BEP_RESULT_GENERAL_ERROR
+ * FPC_BEP_RESULT_NOT_IMPLEMENTED
+ * FPC_BEP_RESULT_NOT_SUPPORTED
+ * FPC_BEP_RESULT_NOT_INITIALIZED
+ * FPC_BEP_RESULT_CANCELLED
+ * FPC_BEP_RESULT_NO_RESOURCE
+ * FPC_BEP_RESULT_WRONG_STATE
+ * FPC_BEP_RESULT_ID_NOT_UNIQUE
+ * FPC_BEP_RESULT_ID_NOT_FOUND
+ * FPC_BEP_RESULT_INVALID_FORMAT
+ * FPC_BEP_RESULT_INVALID_ARGUMENT
+ * FPC_BEP_RESULT_INVALID_PARAMETER
+ * FPC_BEP_RESULT_INVALID_CALIBRATION
+ * FPC_BEP_RESULT_MISSING_TEMPLATE
+ * FPC_BEP_RESULT_STORAGE_NOT_FORMATTED
+ * FPC_BEP_RESULT_SENSOR_NOT_INITIALIZED
+ * FPC_BEP_RESULT_SENSOR_MISMATCH
+ * FPC_BEP_RESULT_CRYPTO_ERROR
+ *
+ * Dynamic memory/heap errors:
+ * Examples: Memory leak; heap is too small.
+ * Action: Fix SW bug.
+ * FPC_BEP_RESULT_NO_MEMORY
+ *
+ * Sensor and communication errors:
+ * Examples: Broken sensor communication lines; unstable power supply.
+ * Action: Fix HW bug.
+ * FPC_BEP_RESULT_BROKEN_SENSOR
+ * FPC_BEP_RESULT_INTERNAL_ERROR
+ * FPC_BEP_RESULT_TIMEOUT
+ * FPC_BEP_RESULT_IO_ERROR
+ *
+ * Image capture errors:
+ * Examples: Finger removed from sensor too quickly.
+ * Action: Call the function again.
+ * FPC_BEP_RESULT_IMAGE_CAPTURE_ERROR
+ */
+
+typedef enum {
+	/** No errors occurred. */
+	FPC_BEP_RESULT_OK = 0,
+	/** General error. */
+	FPC_BEP_RESULT_GENERAL_ERROR = -1,
+	/** Internal error. */
+	FPC_BEP_RESULT_INTERNAL_ERROR = -2,
+	/** Invalid argument. */
+	FPC_BEP_RESULT_INVALID_ARGUMENT = -3,
+	/** The functionality is not implemented. */
+	FPC_BEP_RESULT_NOT_IMPLEMENTED = -4,
+	/** The operation was cancelled. */
+	FPC_BEP_RESULT_CANCELLED = -5,
+	/** Out of memory. */
+	FPC_BEP_RESULT_NO_MEMORY = -6,
+	/** Resources are not available. */
+	FPC_BEP_RESULT_NO_RESOURCE = -7,
+	/** An I/O error occurred. */
+	FPC_BEP_RESULT_IO_ERROR = -8,
+	/** Sensor is broken. */
+	FPC_BEP_RESULT_BROKEN_SENSOR = -9,
+	/** The operation cannot be performed in the current state. */
+	FPC_BEP_RESULT_WRONG_STATE = -10,
+	/** The operation timed out. */
+	FPC_BEP_RESULT_TIMEOUT = -11,
+	/** The ID is not unique. */
+	FPC_BEP_RESULT_ID_NOT_UNIQUE = -12,
+	/** The ID is not found. */
+	FPC_BEP_RESULT_ID_NOT_FOUND = -13,
+	/** The format is invalid. */
+	FPC_BEP_RESULT_INVALID_FORMAT = -14,
+	/** An image capture error occurred. */
+	FPC_BEP_RESULT_IMAGE_CAPTURE_ERROR = -15,
+	/** Sensor hardware id or sensor configuration mismatch. */
+	FPC_BEP_RESULT_SENSOR_MISMATCH = -16,
+	/** Invalid parameter. */
+	FPC_BEP_RESULT_INVALID_PARAMETER = -17,
+	/** Missing Template. */
+	FPC_BEP_RESULT_MISSING_TEMPLATE = -18,
+	/** Invalid Calibration.*/
+	FPC_BEP_RESULT_INVALID_CALIBRATION = -19,
+	/** Calibration/template storage not formatted.*/
+	FPC_BEP_RESULT_STORAGE_NOT_FORMATTED = -20,
+	/** Sensor hasn't been initialized. */
+	FPC_BEP_RESULT_SENSOR_NOT_INITIALIZED = -21,
+	/** Enroll fail after too many bad images. */
+	FPC_BEP_RESULT_TOO_MANY_BAD_IMAGES = -22,
+	/** Cryptographic operation failed. */
+	FPC_BEP_RESULT_CRYPTO_ERROR = -23,
+	/** The functionality is not supported. */
+	FPC_BEP_RESULT_NOT_SUPPORTED = -24,
+	/** Finger not stable. */
+	FPC_BEP_RESULT_FINGER_NOT_STABLE = -25,
+	/** The functionality could not be used before it's initialized. */
+	FPC_BEP_RESULT_NOT_INITIALIZED = -26,
+} fpc_bep_result_t;
+
 typedef struct {
 	uint32_t num_defective_pixels;
 } fp_sensor_info_t;
@@ -24,7 +129,8 @@ typedef struct {
  * the finger detect zones are covered. A client can call
  * fp_sensor_finger_status to determine the current status.
  *
- * @param[in]  image_data      pointer to FP_SENSOR_IMAGE_SIZE bytes of memory
+ * @param[in]  image_data      pointer to a buffer containing at least
+ * FP_SENSOR_IMAGE_SIZE_FPC bytes of memory
  * @param[out] fp_sensor_info  Structure containing output data.
  *
  * @return
@@ -34,4 +140,20 @@ typedef struct {
 int fp_sensor_maintenance(uint8_t *image_data,
 			  fp_sensor_info_t *fp_sensor_info);
 
-#endif  /* __CROS_EC_FPC_PRIVATE_H */
+/**
+ * Get the HWID of the sensor.
+ *
+ * @param id Pointer to where to store the HWID value.  The HWID value here is
+ * the full 16 bits (contrast to FP_SENSOR_HWID_FPC where the lower four bits,
+ * which are a manufacturing id, are truncated).
+ * @return
+ * - EC_SUCCESS on success
+ * - EC_ERROR_INVAL or FP_ERROR_SPI_COMM on error
+ */
+int fpc_get_hwid(uint16_t *id);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CROS_EC_FPC_PRIVATE_H */
diff --git a/driver/fingerprint/fpc/bep/fpc_sensor_spi.c b/driver/fingerprint/fpc/bep/fpc_sensor_spi.c
index 225752bdb6..74bdff0bf6 100644
--- a/driver/fingerprint/fpc/bep/fpc_sensor_spi.c
+++ b/driver/fingerprint/fpc/bep/fpc_sensor_spi.c
@@ -1,31 +1,27 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* FPC Platform Abstraction Layer */
 
-#include <stdint.h>
-#include <stdbool.h>
-#include <stddef.h>
-
 #include "console.h"
-#include "fpsensor.h"
+#include "driver/fingerprint/fpc/fpc_sensor.h"
 #include "fpc_sensor_spi.h"
+#include "fpsensor.h"
+#include "fpsensor_utils.h"
 #include "gpio.h"
 #include "spi.h"
 #include "util.h"
 
-#include "driver/fingerprint/fpc/fpc_sensor.h"
-
-/* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_FP, format, ##args)
-#define CPRINTS(format, args...) cprints(CC_FP, format, ##args)
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
 
-#define SPI_BUF_SIZE              (1024)
+#define SPI_BUF_SIZE (1024)
 
-#define FPC_RESULT_OK                (0)
-#define FPC_RESULT_IO_ERROR         (-8)
+#define FPC_RESULT_OK (0)
+#define FPC_RESULT_IO_ERROR (-8)
 
 static uint8_t spi_buf[SPI_BUF_SIZE] FP_FRAME_SECTION __aligned(4);
 
@@ -34,7 +30,7 @@ int __unused fpc_sensor_spi_write_read(uint8_t *write, uint8_t *read,
 {
 	int rc = 0;
 
-	if (size == FP_SENSOR_REAL_IMAGE_SIZE) {
+	if (size == FP_SENSOR_REAL_IMAGE_SIZE_FPC) {
 		rc |= spi_transaction(SPI_FP_DEVICE, write, size, read,
 				      SPI_READBACK_ALL);
 		spi_transaction_flush(SPI_FP_DEVICE);
diff --git a/driver/fingerprint/fpc/bep/fpc_sensor_spi.h b/driver/fingerprint/fpc/bep/fpc_sensor_spi.h
index 4b9bcd63a8..015bc03dae 100644
--- a/driver/fingerprint/fpc/bep/fpc_sensor_spi.h
+++ b/driver/fingerprint/fpc/bep/fpc_sensor_spi.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,13 +8,15 @@
 
 /**
  * @file    fpc_sensor_spi.h
- * @brief   Driver for SPI master.
+ * @brief   Driver for SPI controller.
  *
- * Driver for SPI master. Intended for communication with fingerprint sensor.
+ * Driver for SPI controller. Intended for communication with
+ * fingerprint sensor.
  */
 
-#include <stdint.h>
 #include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
 
 typedef bool (*fpc_wfi_check_t)(void);
 
@@ -70,7 +72,7 @@ bool __unused fpc_sensor_spi_read_irq(void);
 void __unused fpc_sensor_spi_reset(bool state);
 
 /**
- * @brief Initializes SPI master.
+ * @brief Initializes SPI controller.
  *
  * @param[in] speed_hz  Maximum SPI clock speed according to sensor HW spec
  *                      (unit Hz).
diff --git a/driver/fingerprint/fpc/bep/fpc_timebase.c b/driver/fingerprint/fpc/bep/fpc_timebase.c
index 113e150ed9..c34b9e27db 100644
--- a/driver/fingerprint/fpc/bep/fpc_timebase.c
+++ b/driver/fingerprint/fpc/bep/fpc_timebase.c
@@ -1,15 +1,15 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* FPC Platform Abstraction Layer */
 
-#include <stdint.h>
-
 #include "fpc_timebase.h"
 #include "timer.h"
 
+#include <stdint.h>
+
 uint32_t __unused fpc_timebase_get_tick(void)
 {
 	clock_t time;
diff --git a/driver/fingerprint/fpc/bep/fpc_timebase.h b/driver/fingerprint/fpc/bep/fpc_timebase.h
index 388d13293e..35cf67fed2 100644
--- a/driver/fingerprint/fpc/bep/fpc_timebase.h
+++ b/driver/fingerprint/fpc/bep/fpc_timebase.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,10 +13,10 @@
  * Supplies tick counter and wait operation(s).
  */
 
-#include <stdint.h>
-
 #include "common.h"
 
+#include <stdint.h>
+
 /**
  * @brief Reads the system tick counter.
  *
diff --git a/driver/fingerprint/fpc/build.mk b/driver/fingerprint/fpc/build.mk
index d5e3ede14e..f17af5e496 100644
--- a/driver/fingerprint/fpc/build.mk
+++ b/driver/fingerprint/fpc/build.mk
@@ -1,4 +1,4 @@
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -7,6 +7,10 @@
 # Note that this variable includes the trailing "/"
 _fpc_cur_dir:=$(dir $(lastword $(MAKEFILE_LIST)))
 
+# Only build if FPC sensor is configured.
+ifneq (,$(filter rw,$(CONFIG_FP_SENSOR_FPC1145) $(CONFIG_FP_SENSOR_FPC1025) \
+	$(CONFIG_FP_SENSOR_FPC1035)))
+
 ifeq ($(CONFIG_FP_SENSOR_FPC1145),rw)
 include $(_fpc_cur_dir)libfp/build.mk
 else ifeq ($(CONFIG_FP_SENSOR_FPC1025),rw)
@@ -15,10 +19,12 @@ else ifeq ($(CONFIG_FP_SENSOR_FPC1035),rw)
 include $(_fpc_cur_dir)bep/build.mk
 endif
 
-ifeq ($(CONFIG_FP_SENSOR),rw)
+ifneq ($(CONFIG_FINGERPRINT_MCU),)
 # Make sure output directory is created (in build directory)
-dirs-y+="$(_fpc_cur_dir)"
+dirs-rw+="$(_fpc_cur_dir)"
 
 # Only build these objects for the RW image
 all-obj-rw+=$(_fpc_cur_dir)fpc_sensor.o
 endif
+
+endif
diff --git a/driver/fingerprint/fpc/fpc_sensor.c b/driver/fingerprint/fpc/fpc_sensor.c
index a15502521f..e2891e4d18 100644
--- a/driver/fingerprint/fpc/fpc_sensor.c
+++ b/driver/fingerprint/fpc/fpc_sensor.c
@@ -1,12 +1,13 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include <stddef.h>
+
 #include <include/fpsensor.h>
 #include <include/fpsensor_state.h>
-#include <common/fpsensor/fpsensor_private.h>
+#include <include/fpsensor_utils.h>
 #if defined(CONFIG_FP_SENSOR_FPC1025) || defined(CONFIG_FP_SENSOR_FPC1035)
 #include "bep/fpc_private.h"
 #elif defined(CONFIG_FP_SENSOR_FPC1145)
diff --git a/driver/fingerprint/fpc/fpc_sensor.h b/driver/fingerprint/fpc/fpc_sensor.h
index 2ab9248eeb..22e670afd0 100644
--- a/driver/fingerprint/fpc/fpc_sensor.h
+++ b/driver/fingerprint/fpc/fpc_sensor.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/driver/fingerprint/fpc/libfp/build.mk b/driver/fingerprint/fpc/libfp/build.mk
index 3fabab38e9..f22700f309 100644
--- a/driver/fingerprint/fpc/libfp/build.mk
+++ b/driver/fingerprint/fpc/libfp/build.mk
@@ -1,4 +1,4 @@
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/driver/fingerprint/fpc/libfp/fpc1145_private.h b/driver/fingerprint/fpc/libfp/fpc1145_private.h
index 399c75118b..392665607d 100644
--- a/driver/fingerprint/fpc/libfp/fpc1145_private.h
+++ b/driver/fingerprint/fpc/libfp/fpc1145_private.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,37 +15,37 @@
  * 1140 family with identical functionality.
  * See http://b/150407388 for additional details.
  */
-#define FP_SENSOR_HWID 0x140
+#define FP_SENSOR_HWID_FPC 0x140
 
 /* Sensor type name */
-#define FP_SENSOR_NAME "FPC1145"
+#define FP_SENSOR_NAME_FPC "FPC1145"
 
 /* Sensor pixel resolution */
-#define FP_SENSOR_RES_Y        192
-#define FP_SENSOR_RES_X        56
-#define FP_SENSOR_RES_BPP      8
+#define FP_SENSOR_RES_Y_FPC 192
+#define FP_SENSOR_RES_X_FPC 56
+#define FP_SENSOR_RES_BPP_FPC 8
 
 /* Acquired finger frame definitions */
-#define FP_SENSOR_IMAGE_SIZE_MODE_VENDOR (35460)
-#define FP_SENSOR_IMAGE_SIZE_MODE_SIMPLE (13356)
+#define FP_SENSOR_IMAGE_SIZE_MODE_VENDOR_FPC (35460)
+#define FP_SENSOR_IMAGE_SIZE_MODE_SIMPLE_FPC (13356)
 /*
  * Size of the captured image in MQT mode. If you this is modified the
  * corresponding value in the MQT tool fputils.py must be changed too.
  * See b/111443750 for context.
  */
-#define FP_SENSOR_IMAGE_SIZE_MODE_QUAL   (24408)
+#define FP_SENSOR_IMAGE_SIZE_MODE_QUAL_FPC (24408)
 
-#define FP_SENSOR_IMAGE_SIZE   FP_SENSOR_IMAGE_SIZE_MODE_VENDOR
-#define FP_SENSOR_IMAGE_OFFSET 2340
+#define FP_SENSOR_IMAGE_SIZE_FPC FP_SENSOR_IMAGE_SIZE_MODE_VENDOR_FPC
+#define FP_SENSOR_IMAGE_OFFSET_FPC 2340
 
 /* Opaque FPC context */
-#define FP_SENSOR_CONTEXT_SIZE 4944
+#define FP_SENSOR_CONTEXT_SIZE_FPC 4944
 
 /* Algorithm buffer sizes */
-#define FP_ALGORITHM_ENROLLMENT_SIZE    28
-#define FP_ALGORITHM_TEMPLATE_SIZE   47552
+#define FP_ALGORITHM_ENROLLMENT_SIZE_FPC 28
+#define FP_ALGORITHM_TEMPLATE_SIZE_FPC 47552
 
 /* Max number of templates stored / matched against */
-#define FP_MAX_FINGER_COUNT 5
+#define FP_MAX_FINGER_COUNT_FPC 5
 
 #endif /* __CROS_EC_FPC1145_PRIVATE_H */
diff --git a/driver/fingerprint/fpc/libfp/fpc_bio_algorithm.h b/driver/fingerprint/fpc/libfp/fpc_bio_algorithm.h
index 9c00b14640..834f7394e4 100644
--- a/driver/fingerprint/fpc/libfp/fpc_bio_algorithm.h
+++ b/driver/fingerprint/fpc/libfp/fpc_bio_algorithm.h
@@ -1,12 +1,15 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 #ifndef BIOD_BIO_ALGORITHM_H_
 #define BIOD_BIO_ALGORITHM_H_
 
+#include <stddef.h>
 #include <stdint.h>
 
+#include <sys/types.h>
+
 enum bio_algorithm_type {
 	BIO_ALGORITHM_FINGERPRINT,
 	BIO_ALGORITHM_IRIS,
@@ -196,12 +199,12 @@ int bio_enrollment_begin(bio_sensor_t sensor, bio_enrollment_t *enrollment);
  * - BIO_ENROLLMENT_LOW_COVERAGE when image could not be used  due to
  *   finger covering too little area of the sensor
  */
-#define BIO_ENROLLMENT_OK               0
-#define BIO_ENROLLMENT_IMMOBILE         2
-#define BIO_ENROLLMENT_LOW_QUALITY      1
-#define BIO_ENROLLMENT_LOW_COVERAGE     3
+#define BIO_ENROLLMENT_OK 0
+#define BIO_ENROLLMENT_IMMOBILE 2
+#define BIO_ENROLLMENT_LOW_QUALITY 1
+#define BIO_ENROLLMENT_LOW_COVERAGE 3
 /* Can be used to detect if image was usable for enrollment or not. */
-#define BIO_ENROLLMENT_PROBLEM_MASK     1
+#define BIO_ENROLLMENT_PROBLEM_MASK 1
 int bio_enrollment_add_image(bio_enrollment_t enrollment, bio_image_t image);
 /*
  * Indicates whether there is enough data in the enrollment for it to be
@@ -236,10 +239,10 @@ int bio_enrollment_get_percent_complete(bio_enrollment_t enrollment);
 int bio_enrollment_finish(bio_enrollment_t enrollment, bio_template_t *tmpl);
 
 typedef struct {
-	int32_t coverage;     /* Sensor coverage in range [0..100]        */
-	int32_t quality;      /* Image quality in range [0..100]          */
+	int32_t coverage; /* Sensor coverage in range [0..100]        */
+	int32_t quality; /* Image quality in range [0..100]          */
 	int32_t min_coverage; /* Minimum coverage accepted by enroll      */
-	int32_t min_quality;  /* Minimum image quality accepted by enroll */
+	int32_t min_quality; /* Minimum image quality accepted by enroll */
 } bio_image_status_t;
 
 /*
diff --git a/driver/fingerprint/fpc/libfp/fpc_private.c b/driver/fingerprint/fpc/libfp/fpc_private.c
index 8c11849c8f..3e40962631 100644
--- a/driver/fingerprint/fpc/libfp/fpc_private.c
+++ b/driver/fingerprint/fpc/libfp/fpc_private.c
@@ -1,15 +1,15 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <stddef.h>
 #include "common.h"
 #include "console.h"
-#include "endian.h"
+#include "driver/fingerprint/fpc/fpc_sensor.h"
 #include "fpc_bio_algorithm.h"
 #include "fpc_private.h"
 #include "fpsensor.h"
+#include "fpsensor_utils.h"
 #include "gpio.h"
 #include "link_defs.h"
 #include "spi.h"
@@ -17,10 +17,9 @@
 #include "timer.h"
 #include "util.h"
 
-#include "driver/fingerprint/fpc/fpc_sensor.h"
+#include <stddef.h>
 
-#define CPRINTF(format, args...) cprintf(CC_FP, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_FP, format, ## args)
+#include <sys/types.h>
 
 /* Minimum reset duration */
 #define FP_SENSOR_RESET_DURATION_US (10 * MSEC)
@@ -32,7 +31,7 @@
 #define FP_SENSOR_OPEN_DELAY_US (500 * MSEC)
 
 /* Decode internal error codes from FPC's sensor library */
-#define FPC_GET_INTERNAL_CODE(res) (((res) & 0x000fc000) >> 14)
+#define FPC_GET_INTERNAL_CODE(res) (((res)&0x000fc000) >> 14)
 /* There was a finger on the sensor when calibrating finger detect */
 #define FPC_INTERNAL_FINGER_DFD FPC_ERROR_INTERNAL_38
 
@@ -40,9 +39,9 @@
  * The sensor context is uncached as it contains the SPI buffers,
  * the binary library assumes that it is aligned.
  */
-static uint8_t ctx[FP_SENSOR_CONTEXT_SIZE] __uncached __aligned(4);
+static uint8_t ctx[FP_SENSOR_CONTEXT_SIZE_FPC] __uncached __aligned(4);
 static bio_sensor_t bio_sensor;
-static uint8_t enroll_ctx[FP_ALGORITHM_ENROLLMENT_SIZE];
+static uint8_t enroll_ctx[FP_ALGORITHM_ENROLLMENT_SIZE_FPC] __aligned(4);
 
 /* recorded error flags */
 static uint16_t errors;
@@ -55,23 +54,23 @@ static struct ec_response_fp_info fpc1145_info = {
 	.model_id = 1,
 	.version = 1,
 	/* Image frame characteristics */
-	.frame_size = FP_SENSOR_IMAGE_SIZE,
+	.frame_size = FP_SENSOR_IMAGE_SIZE_FPC,
 	.pixel_format = V4L2_PIX_FMT_GREY,
-	.width = FP_SENSOR_RES_X,
-	.height = FP_SENSOR_RES_Y,
-	.bpp = FP_SENSOR_RES_BPP,
+	.width = FP_SENSOR_RES_X_FPC,
+	.height = FP_SENSOR_RES_Y_FPC,
+	.bpp = FP_SENSOR_RES_BPP_FPC,
 };
 
 /* Sensor IC commands */
 enum fpc_cmd {
-	FPC_CMD_STATUS            = 0x14,
-	FPC_CMD_INT_STS           = 0x18,
-	FPC_CMD_INT_CLR           = 0x1C,
-	FPC_CMD_FINGER_QUERY      = 0x20,
-	FPC_CMD_SLEEP             = 0x28,
-	FPC_CMD_DEEPSLEEP         = 0x2C,
-	FPC_CMD_SOFT_RESET        = 0xF8,
-	FPC_CMD_HW_ID             = 0xFC,
+	FPC_CMD_STATUS = 0x14,
+	FPC_CMD_INT_STS = 0x18,
+	FPC_CMD_INT_CLR = 0x1C,
+	FPC_CMD_FINGER_QUERY = 0x20,
+	FPC_CMD_SLEEP = 0x28,
+	FPC_CMD_DEEPSLEEP = 0x2C,
+	FPC_CMD_SOFT_RESET = 0xF8,
+	FPC_CMD_HW_ID = 0xFC,
 };
 
 /* Maximum size of a sensor command SPI transfer */
@@ -97,10 +96,13 @@ void fp_sensor_low_power(void)
 		fpc_send_cmd(FPC_CMD_SLEEP);
 }
 
-static int fpc_check_hwid(void)
+int fpc_get_hwid(uint16_t *id)
 {
-	uint16_t id;
 	int rc;
+	uint16_t sensor_id;
+
+	if (id == NULL)
+		return EC_ERROR_INVAL;
 
 	/* Clear previous occurences of relevant |errors| flags. */
 	errors &= (~FP_ERROR_SPI_COMM & ~FP_ERROR_BAD_HWID);
@@ -109,19 +111,31 @@ static int fpc_check_hwid(void)
 	rc = spi_transaction(SPI_FP_DEVICE, spi_buf, 3, spi_buf,
 			     SPI_READBACK_ALL);
 	if (rc) {
-		CPRINTS("FPC ID read failed %d", rc);
+		CPRINTS("FPC HW ID read failed %d", rc);
 		errors |= FP_ERROR_SPI_COMM;
 		return EC_ERROR_HW_INTERNAL;
 	}
-	id = (spi_buf[1] << 8) | spi_buf[2];
-	if ((id >> 4) != FP_SENSOR_HWID) {
+
+	sensor_id = ((spi_buf[1] << 8) | spi_buf[2]);
+	*id = sensor_id;
+
+	return EC_SUCCESS;
+}
+
+int fpc_check_hwid(void)
+{
+	uint16_t id = 0;
+	int status;
+
+	status = fpc_get_hwid(&id);
+	if ((id >> 4) != FP_SENSOR_HWID_FPC) {
 		CPRINTS("FPC unknown silicon 0x%04x", id);
 		errors |= FP_ERROR_BAD_HWID;
 		return EC_ERROR_HW_INTERNAL;
 	}
-	CPRINTS(FP_SENSOR_NAME " id 0x%04x", id);
-
-	return EC_SUCCESS;
+	if (status == EC_SUCCESS)
+		CPRINTS(FP_SENSOR_NAME_FPC " id 0x%04x", id);
+	return status;
 }
 
 static uint8_t fpc_read_clear_int(void)
@@ -214,9 +228,9 @@ int fp_sensor_init(void)
 		 * Ensure that any previous context data is obliterated in case
 		 * of a sensor reset.
 		 */
-		memset(ctx, 0, FP_SENSOR_CONTEXT_SIZE);
+		memset(ctx, 0, FP_SENSOR_CONTEXT_SIZE_FPC);
 
-		res = fp_sensor_open(ctx, FP_SENSOR_CONTEXT_SIZE);
+		res = fp_sensor_open(ctx, FP_SENSOR_CONTEXT_SIZE_FPC);
 		/* Flush messages from the PAL if any */
 		cflush();
 		CPRINTS("Sensor init (attempt %d): 0x%x", attempt, res);
diff --git a/driver/fingerprint/fpc/libfp/fpc_private.h b/driver/fingerprint/fpc/libfp/fpc_private.h
index 18feff3a49..a1fe0e47a2 100644
--- a/driver/fingerprint/fpc/libfp/fpc_private.h
+++ b/driver/fingerprint/fpc/libfp/fpc_private.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,85 +8,109 @@
 #ifndef __CROS_EC_FPC_PRIVATE_H
 #define __CROS_EC_FPC_PRIVATE_H
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /* External error codes from FPC's sensor library */
 enum fpc_error_code_external {
-	FPC_ERROR_NONE                        = 0,
-	FPC_ERROR_NOT_FOUND                   = 1,
-	FPC_ERROR_CAN_BE_USED_2               = 2,
-	FPC_ERROR_CAN_BE_USED_3               = 3,
-	FPC_ERROR_CAN_BE_USED_4               = 4,
-	FPC_ERROR_PAL                         = 5,
-	FPC_ERROR_IO                          = 6,
-	FPC_ERROR_CANCELLED                   = 7,
-	FPC_ERROR_UNKNOWN                     = 8,
-	FPC_ERROR_MEMORY                      = 9,
-	FPC_ERROR_PARAMETER                   = 10,
-	FPC_ERROR_TEST_FAILED                 = 11,
-	FPC_ERROR_TIMEDOUT                    = 12,
-	FPC_ERROR_SENSOR                      = 13,
-	FPC_ERROR_SPI                         = 14,
-	FPC_ERROR_NOT_SUPPORTED               = 15,
-	FPC_ERROR_OTP                         = 16,
-	FPC_ERROR_STATE                       = 17,
-	FPC_ERROR_PN                          = 18,
-	FPC_ERROR_DEAD_PIXELS                 = 19,
-	FPC_ERROR_TEMPLATE_CORRUPTED          = 20,
-	FPC_ERROR_CRC                         = 21,
-	FPC_ERROR_STORAGE                     = 22, /**< Errors related to storage                  **/
-	FPC_ERROR_MAXIMUM_REACHED             = 23, /**< The allowed maximum has been reached       **/
-	FPC_ERROR_MINIMUM_NOT_REACHED         = 24, /**< The required minimum was not reached       **/
-	FPC_ERROR_SENSOR_LOW_COVERAGE         = 25, /**< Minimum sensor coverage was not reached    **/
-	FPC_ERROR_SENSOR_LOW_QUALITY          = 26, /**< Sensor image is considered low quality     **/
-	FPC_ERROR_SENSOR_FINGER_NOT_STABLE    = 27, /**< Finger was not stable during image capture **/
+	FPC_ERROR_NONE = 0,
+	FPC_ERROR_NOT_FOUND = 1,
+	FPC_ERROR_CAN_BE_USED_2 = 2,
+	FPC_ERROR_CAN_BE_USED_3 = 3,
+	FPC_ERROR_CAN_BE_USED_4 = 4,
+	FPC_ERROR_PAL = 5,
+	FPC_ERROR_IO = 6,
+	FPC_ERROR_CANCELLED = 7,
+	FPC_ERROR_UNKNOWN = 8,
+	FPC_ERROR_MEMORY = 9,
+	FPC_ERROR_PARAMETER = 10,
+	FPC_ERROR_TEST_FAILED = 11,
+	FPC_ERROR_TIMEDOUT = 12,
+	FPC_ERROR_SENSOR = 13,
+	FPC_ERROR_SPI = 14,
+	FPC_ERROR_NOT_SUPPORTED = 15,
+	FPC_ERROR_OTP = 16,
+	FPC_ERROR_STATE = 17,
+	FPC_ERROR_PN = 18,
+	FPC_ERROR_DEAD_PIXELS = 19,
+	FPC_ERROR_TEMPLATE_CORRUPTED = 20,
+	FPC_ERROR_CRC = 21,
+	FPC_ERROR_STORAGE = 22, /**< Errors related to storage **/
+	FPC_ERROR_MAXIMUM_REACHED = 23, /**< The allowed maximum has been
+					   reached       **/
+	FPC_ERROR_MINIMUM_NOT_REACHED = 24, /**< The required minimum was not
+					       reached       **/
+	FPC_ERROR_SENSOR_LOW_COVERAGE = 25, /**< Minimum sensor coverage was not
+					       reached    **/
+	FPC_ERROR_SENSOR_LOW_QUALITY = 26, /**< Sensor image is considered low
+					      quality     **/
+	FPC_ERROR_SENSOR_FINGER_NOT_STABLE = 27, /**< Finger was not stable
+						    during image capture **/
 };
 
 /* Internal error codes from FPC's sensor library */
 enum fpc_error_code_internal {
-	FPC_ERROR_INTERNAL_0  = 0,  /* Indicates that no internal code was set.                         */
-	FPC_ERROR_INTERNAL_1  = 1,  /* Not supported by sensor.                                         */
-	FPC_ERROR_INTERNAL_2  = 2,  /* Sensor got a NULL response (from other module).                  */
-	FPC_ERROR_INTERNAL_3  = 3,  /* Runtime config not supported by firmware.                        */
-	FPC_ERROR_INTERNAL_4  = 4,  /* CAC has not been created.                                        */
-	FPC_ERROR_INTERNAL_5  = 5,  /* CAC returned an error to the sensor.                             */
-	FPC_ERROR_INTERNAL_6  = 6,  /* CAC fasttap image capture failed.                                */
-	FPC_ERROR_INTERNAL_7  = 7,  /* CAC fasttap image capture failed.                                */
-	FPC_ERROR_INTERNAL_8  = 8,  /* CAC Simple image capture failed.                                 */
-	FPC_ERROR_INTERNAL_9  = 9,  /* CAC custom image capture failed.                                 */
-	FPC_ERROR_INTERNAL_10 = 10, /* CAC MQT image capture failed.                                    */
-	FPC_ERROR_INTERNAL_11 = 11, /* CAC PN image capture failed.                                     */
-	FPC_ERROR_INTERNAL_12 = 12, /* Reading CAC context size.                                        */
-	FPC_ERROR_INTERNAL_13 = 13, /* Reading CAC context size.                                        */
-	FPC_ERROR_INTERNAL_14 = 14, /* Sensor context invalid.                                          */
-	FPC_ERROR_INTERNAL_15 = 15, /* Buffer reference is invalid.                                     */
-	FPC_ERROR_INTERNAL_16 = 16, /* Buffer size reference is invalid.                                */
-	FPC_ERROR_INTERNAL_17 = 17, /* Image data reference is invalid.                                 */
-	FPC_ERROR_INTERNAL_18 = 18, /* Capture type specified is invalid.                               */
-	FPC_ERROR_INTERNAL_19 = 19, /* Capture config specified is invalid.                             */
-	FPC_ERROR_INTERNAL_20 = 20, /* Sensor type in hw desc could not be extracted.                   */
-	FPC_ERROR_INTERNAL_21 = 21, /* Failed to create BNC component.                                  */
-	FPC_ERROR_INTERNAL_22 = 22, /* BN calibration failed.                                           */
-	FPC_ERROR_INTERNAL_23 = 23, /* BN memory allocation failed.                                     */
-	FPC_ERROR_INTERNAL_24 = 24, /* Companion type in hw desc could not be extracted.                */
-	FPC_ERROR_INTERNAL_25 = 25, /* Coating type in hw desc could not be extracted.                  */
-	FPC_ERROR_INTERNAL_26 = 26, /* Sensor mode type is invalid.                                     */
-	FPC_ERROR_INTERNAL_27 = 27, /* Wrong Sensor state in OTP read.                                  */
-	FPC_ERROR_INTERNAL_28 = 28, /* Mismatch of register size in overlay vs rrs.                     */
-	FPC_ERROR_INTERNAL_29 = 29, /* Checkerboard capture failed.                                     */
-	FPC_ERROR_INTERNAL_30 = 30, /* Error converting to fpc_image in dp calibration.                 */
-	FPC_ERROR_INTERNAL_31 = 31, /* Failed to capture reset pixel image.                             */
-	FPC_ERROR_INTERNAL_32 = 32, /* API level not support in dp calibration.                         */
-	FPC_ERROR_INTERNAL_33 = 33, /* The image data in parameter is invalid.                          */
-	FPC_ERROR_INTERNAL_34 = 34, /* PAL delay function has failed.                                   */
-	FPC_ERROR_INTERNAL_35 = 35, /* AFD sensor commad did not complete.                              */
-	FPC_ERROR_INTERNAL_36 = 36, /* AFD wrong runlevel detected after calibration.                   */
-	FPC_ERROR_INTERNAL_37 = 37, /* Wrong rrs size.                                                  */
-	FPC_ERROR_INTERNAL_38 = 38, /* There was a finger on the sensor when calibrating finger detect. */
-	FPC_ERROR_INTERNAL_39 = 39, /* The calculated calibration value is larger than max.             */
-	FPC_ERROR_INTERNAL_40 = 40, /* The sensor fifo always underflows                                */
-	FPC_ERROR_INTERNAL_41 = 41, /* The oscillator calibration resulted in a too high or low value   */
-	FPC_ERROR_INTERNAL_42 = 42, /* Sensor driver was opened with NULL configuration                 */
-	FPC_ERROR_INTERNAL_43 = 43, /* Sensor driver as opened with NULL hw descriptor                  */
-	FPC_ERROR_INTERNAL_44 = 44, /* Error occured during image drive test                            */
+	FPC_ERROR_INTERNAL_0 = 0, /* Indicates that no internal code was set. */
+	FPC_ERROR_INTERNAL_1 = 1, /* Not supported by sensor. */
+	FPC_ERROR_INTERNAL_2 = 2, /* Sensor got a NULL response (from other
+				     module).                  */
+	FPC_ERROR_INTERNAL_3 = 3, /* Runtime config not supported by firmware.
+				   */
+	FPC_ERROR_INTERNAL_4 = 4, /* CAC has not been created. */
+	FPC_ERROR_INTERNAL_5 = 5, /* CAC returned an error to the sensor. */
+	FPC_ERROR_INTERNAL_6 = 6, /* CAC fasttap image capture failed. */
+	FPC_ERROR_INTERNAL_7 = 7, /* CAC fasttap image capture failed. */
+	FPC_ERROR_INTERNAL_8 = 8, /* CAC Simple image capture failed. */
+	FPC_ERROR_INTERNAL_9 = 9, /* CAC custom image capture failed. */
+	FPC_ERROR_INTERNAL_10 = 10, /* CAC MQT image capture failed. */
+	FPC_ERROR_INTERNAL_11 = 11, /* CAC PN image capture failed. */
+	FPC_ERROR_INTERNAL_12 = 12, /* Reading CAC context size. */
+	FPC_ERROR_INTERNAL_13 = 13, /* Reading CAC context size. */
+	FPC_ERROR_INTERNAL_14 = 14, /* Sensor context invalid. */
+	FPC_ERROR_INTERNAL_15 = 15, /* Buffer reference is invalid. */
+	FPC_ERROR_INTERNAL_16 = 16, /* Buffer size reference is invalid. */
+	FPC_ERROR_INTERNAL_17 = 17, /* Image data reference is invalid. */
+	FPC_ERROR_INTERNAL_18 = 18, /* Capture type specified is invalid. */
+	FPC_ERROR_INTERNAL_19 = 19, /* Capture config specified is invalid. */
+	FPC_ERROR_INTERNAL_20 = 20, /* Sensor type in hw desc could not be
+				       extracted.                   */
+	FPC_ERROR_INTERNAL_21 = 21, /* Failed to create BNC component. */
+	FPC_ERROR_INTERNAL_22 = 22, /* BN calibration failed. */
+	FPC_ERROR_INTERNAL_23 = 23, /* BN memory allocation failed. */
+	FPC_ERROR_INTERNAL_24 = 24, /* Companion type in hw desc could not be
+				       extracted.                */
+	FPC_ERROR_INTERNAL_25 = 25, /* Coating type in hw desc could not be
+				       extracted.                  */
+	FPC_ERROR_INTERNAL_26 = 26, /* Sensor mode type is invalid. */
+	FPC_ERROR_INTERNAL_27 = 27, /* Wrong Sensor state in OTP read. */
+	FPC_ERROR_INTERNAL_28 = 28, /* Mismatch of register size in overlay vs
+				       rrs.                     */
+	FPC_ERROR_INTERNAL_29 = 29, /* Checkerboard capture failed. */
+	FPC_ERROR_INTERNAL_30 = 30, /* Error converting to fpc_image in dp
+				       calibration.                 */
+	FPC_ERROR_INTERNAL_31 = 31, /* Failed to capture reset pixel image. */
+	FPC_ERROR_INTERNAL_32 = 32, /* API level not support in dp calibration.
+				     */
+	FPC_ERROR_INTERNAL_33 = 33, /* The image data in parameter is invalid.
+				     */
+	FPC_ERROR_INTERNAL_34 = 34, /* PAL delay function has failed. */
+	FPC_ERROR_INTERNAL_35 = 35, /* AFD sensor commad did not complete. */
+	FPC_ERROR_INTERNAL_36 = 36, /* AFD wrong runlevel detected after
+				       calibration.                   */
+	FPC_ERROR_INTERNAL_37 = 37, /* Wrong rrs size. */
+	FPC_ERROR_INTERNAL_38 = 38, /* There was a finger on the sensor when
+				       calibrating finger detect. */
+	FPC_ERROR_INTERNAL_39 = 39, /* The calculated calibration value is
+				       larger than max.             */
+	FPC_ERROR_INTERNAL_40 = 40, /* The sensor fifo always underflows */
+	FPC_ERROR_INTERNAL_41 = 41, /* The oscillator calibration resulted in a
+				       too high or low value   */
+	FPC_ERROR_INTERNAL_42 = 42, /* Sensor driver was opened with NULL
+				       configuration                 */
+	FPC_ERROR_INTERNAL_43 = 43, /* Sensor driver as opened with NULL hw
+				       descriptor                  */
+	FPC_ERROR_INTERNAL_44 = 44, /* Error occured during image drive test */
 };
 
 /* FPC specific initialization function to fill their context */
@@ -125,4 +149,20 @@ typedef struct {
 int fp_sensor_maintenance(uint8_t *image_data,
 			  fp_sensor_info_t *fp_sensor_info);
 
+/**
+ * Get the HWID of the sensor.
+ *
+ * @param id Pointer to where to store the HWID value.  The HWID value here is
+ * the full 16 bits (contrast to FP_SENSOR_HWID where the lower four bits, which
+ * are a manufacturing id, are truncated).
+ * @return
+ * - EC_SUCCESS on success
+ * - EC_ERROR_INVAL or EC_ERROR_HW_INTERNAL on error
+ */
+int fpc_get_hwid(uint16_t *id);
+
+#ifdef __cplusplus
+}
+#endif
+
 #endif /* __CROS_EC_FPC_PRIVATE_H */
diff --git a/driver/fingerprint/fpc/libfp/fpc_sensor_pal.c b/driver/fingerprint/fpc/libfp/fpc_sensor_pal.c
index 35c07b464a..57ac6258c1 100644
--- a/driver/fingerprint/fpc/libfp/fpc_sensor_pal.c
+++ b/driver/fingerprint/fpc/libfp/fpc_sensor_pal.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,17 +6,15 @@
 
 #include "common.h"
 #include "console.h"
-#include "fpsensor.h"
 #include "fpc_sensor_pal.h"
+#include "fpsensor.h"
+#include "fpsensor_utils.h"
 #include "shared_mem.h"
 #include "spi.h"
 #include "timer.h"
 #include "uart.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_FP, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_FP, format, ## args)
-
 void fpc_pal_log_entry(const char *tag, int log_level, const char *format, ...)
 {
 	va_list args;
@@ -57,4 +55,5 @@ int32_t FpcMalloc(void **data, size_t size)
 void FpcFree(void **data)
 {
 	shared_mem_release(*data);
+	*data = NULL;
 }
diff --git a/driver/fingerprint/fpc/libfp/fpc_sensor_pal.h b/driver/fingerprint/fpc/libfp/fpc_sensor_pal.h
index 78376863f1..844f1d7498 100644
--- a/driver/fingerprint/fpc/libfp/fpc_sensor_pal.h
+++ b/driver/fingerprint/fpc/libfp/fpc_sensor_pal.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,8 +14,10 @@ typedef void *fpc_device_t;
  * @brief Used to describe an interrupt
  */
 typedef enum {
-    IRQ_INT_TRIG = 0x01, /**< Internally triggered by sensor (fast interrupt)                   **/
-    IRQ_EXT_TRIG = 0x02  /**< Externally triggered by event outside sensor (may take long time) **/
+	IRQ_INT_TRIG = 0x01, /**< Internally triggered by sensor (fast
+				interrupt)                   **/
+	IRQ_EXT_TRIG = 0x02 /**< Externally triggered by event outside sensor
+			       (may take long time) **/
 } fpc_pal_irq_t;
 
 /**
@@ -109,9 +111,9 @@ int fpc_pal_spi_get_speed_hz(fpc_device_t device, uint32_t *speed_hz);
  * @param[in] ...        additional arguments.
  *
  */
-#define FPC_SENSOR_SDK_LOG_LEVEL_DEBUG    (1)
-#define FPC_SENSOR_SDK_LOG_LEVEL_INFO     (2)
-#define FPC_SENSOR_SDK_LOG_LEVEL_ERROR    (3)
+#define FPC_SENSOR_SDK_LOG_LEVEL_DEBUG (1)
+#define FPC_SENSOR_SDK_LOG_LEVEL_INFO (2)
+#define FPC_SENSOR_SDK_LOG_LEVEL_ERROR (3)
 #define FPC_SENSOR_SDK_LOG_LEVEL_DISABLED (4)
 void fpc_pal_log_entry(const char *tag, int log_level, const char *format, ...);
 
diff --git a/driver/fingerprint/fpsensor.h b/driver/fingerprint/fpsensor.h
deleted file mode 100644
index 44d989df13..0000000000
--- a/driver/fingerprint/fpsensor.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_DRIVER_FINGERPRINT_FPSENSOR_H_
-#define __CROS_EC_DRIVER_FINGERPRINT_FPSENSOR_H_
-
-#if defined(HAVE_PRIVATE) && !defined(EMU_BUILD)
-#define HAVE_FP_PRIVATE_DRIVER
-#include "fpc/fpc_sensor.h"
-#else
-/* These values are used by the host (emulator) tests. */
-#define FP_SENSOR_IMAGE_SIZE 0
-#define FP_SENSOR_RES_X 0
-#define FP_SENSOR_RES_Y 0
-#define FP_ALGORITHM_TEMPLATE_SIZE 0
-#define FP_MAX_FINGER_COUNT 5
-#endif
-
-#if defined(HAVE_PRIVATE) && defined(TEST_BUILD)
-/*
- * For unittest in a private build, enable driver-related code in
- * common/fpsensor/ so that they can be tested (with fp_sensor_mock).
- */
-#define HAVE_FP_PRIVATE_DRIVER
-#endif
-
-#endif /* __CROS_EC_DRIVER_FINGERPRINT_FPSENSOR_H_ */
diff --git a/driver/fingerprint/fpsensor_driver.h b/driver/fingerprint/fpsensor_driver.h
new file mode 100644
index 0000000000..e5cdc78d3d
--- /dev/null
+++ b/driver/fingerprint/fpsensor_driver.h
@@ -0,0 +1,50 @@
+/* Copyright 2019 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_DRIVER_FINGERPRINT_FPSENSOR_DRIVER_H_
+#define __CROS_EC_DRIVER_FINGERPRINT_FPSENSOR_DRIVER_H_
+
+#if defined(HAVE_PRIVATE) && !defined(EMU_BUILD)
+#define HAVE_FP_PRIVATE_DRIVER
+#if defined(CONFIG_FP_SENSOR_ELAN80) || defined(CONFIG_FP_SENSOR_ELAN515)
+#include "elan/elan_sensor.h"
+#define FP_SENSOR_IMAGE_OFFSET (FP_SENSOR_IMAGE_OFFSET_ELAN)
+#define FP_SENSOR_IMAGE_SIZE (FP_SENSOR_IMAGE_SIZE_ELAN)
+#define FP_SENSOR_RES_X (FP_SENSOR_RES_X_ELAN)
+#define FP_SENSOR_RES_Y (FP_SENSOR_RES_Y_ELAN)
+#define FP_ALGORITHM_TEMPLATE_SIZE (FP_ALGORITHM_TEMPLATE_SIZE_ELAN)
+#define FP_MAX_FINGER_COUNT (FP_MAX_FINGER_COUNT_ELAN)
+#else
+#include "fpc/fpc_sensor.h"
+#define FP_SENSOR_IMAGE_OFFSET (FP_SENSOR_IMAGE_OFFSET_FPC)
+#define FP_SENSOR_IMAGE_SIZE (FP_SENSOR_IMAGE_SIZE_FPC)
+#define FP_SENSOR_RES_X (FP_SENSOR_RES_X_FPC)
+#define FP_SENSOR_RES_Y (FP_SENSOR_RES_Y_FPC)
+#define FP_ALGORITHM_TEMPLATE_SIZE (FP_ALGORITHM_TEMPLATE_SIZE_FPC)
+#define FP_MAX_FINGER_COUNT (FP_MAX_FINGER_COUNT_FPC)
+#endif
+#else
+/* These values are used by the host (emulator) tests. */
+#define FP_SENSOR_IMAGE_OFFSET (0)
+#define FP_SENSOR_IMAGE_SIZE 0
+#define FP_SENSOR_RES_X 0
+#define FP_SENSOR_RES_Y 0
+#define FP_ALGORITHM_TEMPLATE_SIZE 0
+#define FP_MAX_FINGER_COUNT 5
+#endif
+
+#if defined(HAVE_PRIVATE) && defined(TEST_BUILD)
+/*
+ * For unittest in a private build, enable driver-related code in
+ * common/fpsensor/ so that they can be tested (with fpsensor_mock).
+ */
+#define HAVE_FP_PRIVATE_DRIVER
+#endif
+
+#if !defined(FP_SENSOR_IMAGE_OFFSET) && defined(TEST_BUILD)
+#define FP_SENSOR_IMAGE_OFFSET (0)
+#endif
+
+#endif /* __CROS_EC_DRIVER_FINGERPRINT_FPSENSOR_DRIVER_H_ */
diff --git a/driver/gl3590.c b/driver/gl3590.c
new file mode 100644
index 0000000000..03af496293
--- /dev/null
+++ b/driver/gl3590.c
@@ -0,0 +1,337 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "gl3590.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "pwr_defs.h"
+#include "system.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args)
+
+/* GL3590 is unique in terms of i2c_read, since it doesn't support repeated
+ * start sequence. One need to issue two separate transactions - first is write
+ * with a register offset, then after a delay second transaction is actual read.
+ */
+int gl3590_read(int hub, uint8_t reg, uint8_t *data, int count)
+{
+	int rv;
+	struct uhub_i2c_iface_t *uhub_p = &uhub_config[hub];
+
+	i2c_lock(uhub_p->i2c_host_port, 1);
+	rv = i2c_xfer_unlocked(uhub_p->i2c_host_port, uhub_p->i2c_addr, &reg, 1,
+			       NULL, 0, I2C_XFER_SINGLE);
+	i2c_lock(uhub_p->i2c_host_port, 0);
+
+	if (rv)
+		return rv;
+
+	/* GL3590 requires at least 1ms between consecutive i2c transactions */
+	udelay(MSEC);
+
+	i2c_lock(uhub_p->i2c_host_port, 1);
+	rv = i2c_xfer_unlocked(uhub_p->i2c_host_port, uhub_p->i2c_addr, NULL, 0,
+			       data, count, I2C_XFER_SINGLE);
+	i2c_lock(uhub_p->i2c_host_port, 0);
+
+	/*
+	 * GL3590 requires at least 1ms between consecutive i2c transactions.
+	 * Make sure that we are safe across API calls.
+	 */
+	udelay(MSEC);
+
+	return rv;
+};
+
+int gl3590_write(int hub, uint8_t reg, uint8_t *data, int count)
+{
+	int rv;
+	uint8_t buf[5];
+	struct uhub_i2c_iface_t *uhub_p = &uhub_config[hub];
+
+	/* GL3590 registers accept 4 bytes at max */
+	if (count > (sizeof(buf) - 1)) {
+		ccprintf("Too many bytes to write");
+		return EC_ERROR_INVAL;
+	}
+
+	buf[0] = reg;
+	memcpy(&buf[1], data, count);
+
+	i2c_lock(uhub_p->i2c_host_port, 1);
+	rv = i2c_xfer_unlocked(uhub_p->i2c_host_port, uhub_p->i2c_addr, buf,
+			       count + 1, NULL, 0, I2C_XFER_SINGLE);
+	i2c_lock(uhub_p->i2c_host_port, 0);
+
+	/*
+	 * GL3590 requires at least 1ms between consecutive i2c transactions.
+	 * Make sure that we are safe across API calls.
+	 */
+	udelay(MSEC);
+
+	return rv;
+}
+
+/*
+ * Basic initialization of GL3590 I2C interface.
+ *
+ * Please note, that I2C interface is online not earlier than ~50ms after
+ * RESETJ# is deasserted. Platform should check that PGREEN_A_SMD pin is
+ * asserted. This init function shouldn't be invoked until that time.
+ */
+void gl3590_init(int hub)
+{
+	uint8_t tmp;
+	struct uhub_i2c_iface_t *uhub_p = &uhub_config[hub];
+
+	if (uhub_p->initialized)
+		return;
+
+	if (gl3590_read(hub, GL3590_HUB_MODE_REG, &tmp, 1)) {
+		CPRINTF("GL3590: Cannot read HUB_MODE register");
+		return;
+	}
+	if ((tmp & GL3590_HUB_MODE_I2C_READY) == 0)
+		CPRINTF("GL3590 interface isn't ready, consider deferring "
+			"this init\n");
+
+	/* Deassert INTR# signal */
+	tmp = GL3590_INT_CLEAR;
+	if (gl3590_write(hub, GL3590_INT_REG, &tmp, 1)) {
+		CPRINTF("GL3590: Cannot write to INT register");
+		return;
+	};
+
+	uhub_p->initialized = 1;
+}
+
+/*
+ * GL3590 chip may drive I2C_SDA and I2C_SCL lines for 200ms (max) after it is
+ * released from reset (through gpio de-assertion in main()). In order to avoid
+ * broken I2C transactions, we need to add an extra delay before any activity on
+ * the I2C bus in the system.
+ */
+static void gl3590_delay_on_init(void)
+{
+	CPRINTS("Applying 200ms delay for GL3590 to release I2C lines");
+	udelay(200 * MSEC);
+}
+DECLARE_HOOK(HOOK_INIT, gl3590_delay_on_init, HOOK_PRIO_INIT_I2C - 1);
+
+void gl3590_irq_handler(int hub)
+{
+	uint8_t buf = 0;
+	uint8_t res_reg[2];
+	struct uhub_i2c_iface_t *uhub_p = &uhub_config[hub];
+
+	if (!uhub_p->initialized)
+		return;
+
+	/* Verify that irq is pending */
+	if (gl3590_read(hub, GL3590_INT_REG, &buf, sizeof(buf))) {
+		ccprintf("Cannot read from the host hub i2c\n");
+		goto exit;
+	}
+
+	if ((buf & GL3590_INT_PENDING) == 0) {
+		ccprintf("Invalid hub event\n");
+		goto exit;
+	}
+
+	/* Get the hub event reason */
+	if (gl3590_read(hub, GL3590_RESPONSE_REG, res_reg, sizeof(res_reg))) {
+		ccprintf("Cannot read from the host hub i2c\n");
+		goto exit;
+	}
+
+	if ((res_reg[0] & GL3590_RESPONSE_REG_SYNC_MASK) == 0)
+		ccprintf("Host hub response: ");
+	else
+		ccprintf("Host hub event! ");
+
+	switch (res_reg[0]) {
+	case 0x0:
+		ccprintf("No response");
+		break;
+	case 0x1:
+		ccprintf("Successful");
+		break;
+	case 0x2:
+		ccprintf("Invalid command");
+		break;
+	case 0x3:
+		ccprintf("Invalid arguments");
+		break;
+	case 0x4:
+		ccprintf("Invalid port: %d", res_reg[1]);
+		break;
+	case 0x5:
+		ccprintf("Command not completed");
+		break;
+	case 0x80:
+		ccprintf("Reset complete");
+		break;
+	case 0x81:
+		ccprintf("Power operation mode change");
+		break;
+	case 0x82:
+		ccprintf("Connect change");
+		break;
+	case 0x83:
+		ccprintf("Error on the specific port");
+		break;
+	case 0x84:
+		ccprintf("Hub state change");
+		break;
+	case 0x85:
+		ccprintf("SetFeature PORT_POWER failure");
+		break;
+	default:
+		ccprintf("Unknown value: 0x%0x", res_reg[0]);
+	}
+	ccprintf("\n");
+
+	if (res_reg[1])
+		ccprintf("Affected port %d\n", res_reg[1]);
+
+exit:
+	/* Try to clear interrupt */
+	buf = GL3590_INT_CLEAR;
+	gl3590_write(hub, GL3590_INT_REG, &buf, sizeof(buf));
+}
+
+enum ec_error_list gl3590_ufp_pwr(int hub, struct pwr_con_t *pwr)
+{
+	uint8_t hub_sts, hub_mode;
+	int rv = 0;
+	struct uhub_i2c_iface_t *uhub_p = &uhub_config[hub];
+
+	if (!uhub_p->initialized)
+		return EC_ERROR_HW_INTERNAL;
+
+	if (gl3590_read(hub, GL3590_HUB_STS_REG, &hub_sts, sizeof(hub_sts))) {
+		CPRINTF("Error reading HUB_STS %d\n", rv);
+		return EC_ERROR_BUSY;
+	}
+
+	pwr->volts = 5;
+
+	switch ((hub_sts & GL3590_HUB_STS_HOST_PWR_MASK) >>
+		GL3590_HUB_STS_HOST_PWR_SHIFT) {
+	case GL3590_DEFAULT_HOST_PWR_SRC:
+		if (gl3590_read(hub, GL3590_HUB_MODE_REG, &hub_mode,
+				sizeof(hub_mode))) {
+			CPRINTF("Error reading HUB_MODE %d\n", rv);
+			return EC_ERROR_BUSY;
+		}
+		if (hub_mode & GL3590_HUB_MODE_USB3_EN) {
+			pwr->milli_amps = 900;
+			return EC_SUCCESS;
+		} else if (hub_mode & GL3590_HUB_MODE_USB2_EN) {
+			pwr->milli_amps = 500;
+			return EC_SUCCESS;
+		} else {
+			CPRINTF("GL3590: Neither USB3 nor USB2 hubs "
+				"configured\n");
+			return EC_ERROR_HW_INTERNAL;
+		}
+	case GL3590_1_5_A_HOST_PWR_SRC:
+		pwr->milli_amps = 1500;
+		return EC_SUCCESS;
+	case GL3590_3_0_A_HOST_PWR_SRC:
+		pwr->milli_amps = 3000;
+		return EC_SUCCESS;
+	default:
+		CPRINTF("GL3590: Unkown host power source %d\n", hub_sts);
+		return EC_ERROR_UNKNOWN;
+	}
+}
+
+#define GL3590_EN_PORT_MAX_RETRY_COUNT 10
+
+int gl3590_enable_ports(int hub, uint8_t port_mask, bool enable)
+{
+	uint8_t buf[4] = { 0 };
+	uint8_t en_mask = 0;
+	uint8_t tmp;
+	int rv, i;
+	struct uhub_i2c_iface_t *uhub_p = &uhub_config[hub];
+
+	if (!uhub_p->initialized)
+		return EC_ERROR_HW_INTERNAL;
+
+	if (!enable)
+		en_mask = port_mask;
+
+	buf[0] = en_mask;
+	buf[2] = port_mask;
+
+	for (i = 1; i <= GL3590_EN_PORT_MAX_RETRY_COUNT; i++) {
+		rv = gl3590_write(hub, GL3590_PORT_DISABLED_REG, buf,
+				  sizeof(buf));
+		if (rv)
+			return rv;
+
+		usleep(200 * MSEC);
+
+		/* Verify whether port is enabled/disabled */
+		rv = gl3590_read(hub, GL3590_PORT_EN_STS_REG, &tmp, 1);
+		if (rv)
+			return rv;
+
+		if (enable && ((tmp & port_mask) == port_mask))
+			break;
+		if (!enable && ((tmp & port_mask) == 0))
+			break;
+
+		if (i > GL3590_EN_PORT_MAX_RETRY_COUNT) {
+			CPRINTF("GL3590: Failed to %s port 0x%x\n",
+				enable ? "enable" : "disable", port_mask);
+			return EC_ERROR_HW_INTERNAL;
+		}
+
+		CPRINTF("GL3590: Port %s retrying.. %d/%d\n"
+			"Port status is 0x%x\n",
+			enable ? "enable" : "disable", i,
+			GL3590_EN_PORT_MAX_RETRY_COUNT, tmp);
+	}
+
+	return EC_SUCCESS;
+}
+
+#ifdef CONFIG_CMD_GL3590
+static int command_gl3590(int argc, const char **argv)
+{
+	char *e;
+	int port;
+
+	if (argc < 2)
+		return EC_ERROR_PARAM_COUNT;
+
+	port = strtoi(argv[2], &e, 0);
+	if (*e)
+		return EC_ERROR_PARAM2;
+
+	if (strcasecmp(argv[1], "enable") == 0) {
+		if (!gl3590_enable_ports(0, port, 1))
+			return EC_SUCCESS;
+		else
+			return EC_ERROR_HW_INTERNAL;
+	} else if (strcasecmp(argv[1], "disable") == 0) {
+		if (!gl3590_enable_ports(0, port, 0))
+			return EC_SUCCESS;
+		else
+			return EC_ERROR_HW_INTERNAL;
+	}
+
+	return EC_ERROR_PARAM1;
+}
+DECLARE_CONSOLE_COMMAND(gl3590, command_gl3590,
+			"<enable | disable> <port_bitmask>",
+			"Manage GL3590 USB3.1 hub and its ports");
+#endif /* CONFIG_CMD_GL3590 */
diff --git a/driver/gl3590.h b/driver/gl3590.h
new file mode 100644
index 0000000000..ef429c04f1
--- /dev/null
+++ b/driver/gl3590.h
@@ -0,0 +1,63 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "pwr_defs.h"
+#include "stdbool.h"
+
+/* Registers definitions */
+#define GL3590_HUB_MODE_REG 0x0
+#define GL3590_HUB_MODE_I2C_READY 0x1
+#define GL3590_HUB_MODE_USB2_EN 0x2
+#define GL3590_HUB_MODE_USB3_EN 0x4
+#define GL3590_INT_REG 0x1
+#define GL3590_INT_PENDING 0x1
+#define GL3590_INT_CLEAR 0x1
+#define GL3590_RESPONSE_REG 0x2
+#define GL3590_RESPONSE_REG_SYNC_MASK 0x80
+#define GL3590_PORT_DISABLED_REG 0x4
+#define GL3590_PORT_EN_STS_REG 0x8
+#define GL3590_HUB_STS_REG 0xA
+#define GL3590_HUB_STS_HOST_PWR_MASK 0x30
+#define GL3590_HUB_STS_HOST_PWR_SHIFT 4
+#define GL3590_DEFAULT_HOST_PWR_SRC 0x0
+#define GL3590_1_5_A_HOST_PWR_SRC 0x1
+#define GL3590_3_0_A_HOST_PWR_SRC 0x2
+
+#define GL3590_I2C_ADDR0 0x50
+
+/* Read GL3590 I2C register */
+int gl3590_read(int hub, uint8_t reg, uint8_t *data, int count);
+
+/* Write to GL3590 I2C register */
+int gl3590_write(int hub, uint8_t reg, uint8_t *data, int count);
+
+/* Initialize GL3590 I2C interface */
+void gl3590_init(int hub);
+
+/* Generic handler for GL3590 IRQ, can be registered/invoked by platform */
+void gl3590_irq_handler(int hub);
+
+/* Get power capabilities of UFP host connection */
+enum ec_error_list gl3590_ufp_pwr(int hub, struct pwr_con_t *pwr);
+
+#define GL3590_DFP1 BIT(0)
+#define GL3590_DFP2 BIT(1)
+#define GL3590_DFP3 BIT(2)
+#define GL3590_DFP4 BIT(3)
+#define GL3590_DFP5 BIT(4)
+#define GL3590_DFP6 BIT(5)
+#define GL3590_DFP7 BIT(6)
+#define GL3590_DFP8 BIT(7)
+
+/* Enable/disable power to particular downstream facing ports */
+int gl3590_enable_ports(int hub, uint8_t port_mask, bool enable);
+
+/* Generic USB HUB I2C interface */
+struct uhub_i2c_iface_t {
+	int i2c_host_port;
+	int i2c_addr;
+	int initialized;
+};
+extern struct uhub_i2c_iface_t uhub_config[];
diff --git a/driver/gyro_l3gd20h.c b/driver/gyro_l3gd20h.c
index 4fcaf15ed0..9e47b86893 100644
--- a/driver/gyro_l3gd20h.c
+++ b/driver/gyro_l3gd20h.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,8 +17,8 @@
 #include "util.h"
 
 #define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
 
 /*
  * Struct for pairing an engineering value with the register value for a
@@ -33,15 +33,13 @@ struct gyro_param_pair {
  * List of angular rate range values in +/-dps's
  * and their associated register values.
  */
-const struct gyro_param_pair dps_ranges[] = {
-	{245, L3GD20_DPS_SEL_245},
-	{500, L3GD20_DPS_SEL_500},
-	{2000, L3GD20_DPS_SEL_2000_0},
-	{2000, L3GD20_DPS_SEL_2000_1}
-};
+const struct gyro_param_pair dps_ranges[] = { { 245, L3GD20_DPS_SEL_245 },
+					      { 500, L3GD20_DPS_SEL_500 },
+					      { 2000, L3GD20_DPS_SEL_2000_0 },
+					      { 2000, L3GD20_DPS_SEL_2000_1 } };
 
-static inline const struct gyro_param_pair *get_range_table(
-		enum motionsensor_type type, int *psize)
+static inline const struct gyro_param_pair *
+get_range_table(enum motionsensor_type type, int *psize)
 {
 	if (psize)
 		*psize = ARRAY_SIZE(dps_ranges);
@@ -50,19 +48,19 @@ static inline const struct gyro_param_pair *get_range_table(
 
 /* List of ODR values in mHz and their associated register values. */
 const struct gyro_param_pair gyro_odr[] = {
-	{0,      L3GD20_ODR_PD | L3GD20_LOW_ODR_MASK},
-	{12500,  L3GD20_ODR_12_5HZ | L3GD20_ODR_PD_MASK | L3GD20_LOW_ODR_MASK},
-	{25000,  L3GD20_ODR_25HZ | L3GD20_ODR_PD_MASK | L3GD20_LOW_ODR_MASK},
-	{50000,  L3GD20_ODR_50HZ_0 | L3GD20_ODR_PD_MASK | L3GD20_LOW_ODR_MASK},
-	{50000,  L3GD20_ODR_50HZ_1 | L3GD20_ODR_PD_MASK | L3GD20_LOW_ODR_MASK},
-	{100000, L3GD20_ODR_100HZ | L3GD20_ODR_PD_MASK},
-	{200000, L3GD20_ODR_200HZ | L3GD20_ODR_PD_MASK},
-	{400000, L3GD20_ODR_400HZ | L3GD20_ODR_PD_MASK},
-	{800000, L3GD20_ODR_800HZ | L3GD20_ODR_PD_MASK},
+	{ 0, L3GD20_ODR_PD | L3GD20_LOW_ODR_MASK },
+	{ 12500, L3GD20_ODR_12_5HZ | L3GD20_ODR_PD_MASK | L3GD20_LOW_ODR_MASK },
+	{ 25000, L3GD20_ODR_25HZ | L3GD20_ODR_PD_MASK | L3GD20_LOW_ODR_MASK },
+	{ 50000, L3GD20_ODR_50HZ_0 | L3GD20_ODR_PD_MASK | L3GD20_LOW_ODR_MASK },
+	{ 50000, L3GD20_ODR_50HZ_1 | L3GD20_ODR_PD_MASK | L3GD20_LOW_ODR_MASK },
+	{ 100000, L3GD20_ODR_100HZ | L3GD20_ODR_PD_MASK },
+	{ 200000, L3GD20_ODR_200HZ | L3GD20_ODR_PD_MASK },
+	{ 400000, L3GD20_ODR_400HZ | L3GD20_ODR_PD_MASK },
+	{ 800000, L3GD20_ODR_800HZ | L3GD20_ODR_PD_MASK },
 };
 
-static inline const struct gyro_param_pair *get_odr_table(
-		enum motionsensor_type type, int *psize)
+static inline const struct gyro_param_pair *
+get_odr_table(enum motionsensor_type type, int *psize)
 {
 	if (psize)
 		*psize = ARRAY_SIZE(gyro_odr);
@@ -86,14 +84,14 @@ static inline int get_xyz_reg(enum motionsensor_type type)
  * outside the range of values, it returns the closest valid reg value.
  */
 static int get_reg_val(const int eng_val, const int round_up,
-		const struct gyro_param_pair *pairs, const int size)
+		       const struct gyro_param_pair *pairs, const int size)
 {
 	int i;
 	for (i = 0; i < size - 1; i++) {
 		if (eng_val <= pairs[i].val)
 			break;
 
-		if (eng_val < pairs[i+1].val) {
+		if (eng_val < pairs[i + 1].val) {
 			if (round_up)
 				i += 1;
 			break;
@@ -106,7 +104,8 @@ static int get_reg_val(const int eng_val, const int round_up,
  * @return engineering value that matches the given reg val
  */
 static int get_engineering_val(const int reg_val,
-		const struct gyro_param_pair *pairs, const int size)
+			       const struct gyro_param_pair *pairs,
+			       const int size)
 {
 	int i;
 	for (i = 0; i < size; i++) {
@@ -120,7 +119,7 @@ static int get_engineering_val(const int reg_val,
  * Read register from Gyrometer.
  */
 static inline int raw_read8(const int port, const int addr, const int reg,
-							int *data_ptr)
+			    int *data_ptr)
 {
 	return i2c_read8(port, addr, reg, data_ptr);
 }
@@ -129,19 +128,16 @@ static inline int raw_read8(const int port, const int addr, const int reg,
  * Write register from Gyrometer.
  */
 static inline int raw_write8(const int port, const int addr, const int reg,
-							 int data)
+			     int data)
 {
 	return i2c_write8(port, addr, reg, data);
 }
 
-static int set_range(const struct motion_sensor_t *s,
-				int range,
-				int rnd)
+static int set_range(struct motion_sensor_t *s, int range, int rnd)
 {
 	int ret, ctrl_val, range_tbl_size;
 	uint8_t ctrl_reg, reg_val;
 	const struct gyro_param_pair *ranges;
-	struct l3gd20_data *data = (struct l3gd20_data *)s->drv_data;
 
 	ctrl_reg = L3GD20_CTRL_REG4;
 	ranges = get_range_table(s->type, &range_tbl_size);
@@ -163,29 +159,20 @@ static int set_range(const struct motion_sensor_t *s,
 
 	/* Now that we have set the range, update the driver's value. */
 	if (ret == EC_SUCCESS)
-		data->base.range = get_engineering_val(reg_val, ranges,
-							 range_tbl_size);
+		s->current_range =
+			get_engineering_val(reg_val, ranges, range_tbl_size);
 
 gyro_cleanup:
 	mutex_unlock(s->mutex);
 	return EC_SUCCESS;
 }
 
-static int get_range(const struct motion_sensor_t *s)
-{
-	struct l3gd20_data *data = (struct l3gd20_data *)s->drv_data;
-
-	return data->base.range;
-}
-
 static int get_resolution(const struct motion_sensor_t *s)
 {
 	return L3GD20_RESOLUTION;
 }
 
-static int set_data_rate(const struct motion_sensor_t *s,
-				int rate,
-				int rnd)
+static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
 {
 	int ret, val, odr_tbl_size;
 	uint8_t ctrl_reg, reg_val;
@@ -207,13 +194,13 @@ static int set_data_rate(const struct motion_sensor_t *s,
 		goto gyro_cleanup;
 
 	val = (val & ~(L3GD20_ODR_MASK | L3GD20_ODR_PD_MASK)) |
-		(reg_val & ~L3GD20_LOW_ODR_MASK);
+	      (reg_val & ~L3GD20_LOW_ODR_MASK);
 	ret = raw_write8(s->port, s->addr, ctrl_reg, val);
 
 	/* Now that we have set the odr, update the driver's value. */
 	if (ret == EC_SUCCESS)
-		data->base.odr = get_engineering_val(reg_val, data_rates,
-						       odr_tbl_size);
+		data->base.odr =
+			get_engineering_val(reg_val, data_rates, odr_tbl_size);
 
 	ret = raw_read8(s->port, s->addr, L3GD20_LOW_ODR, &val);
 	if (ret != EC_SUCCESS)
@@ -271,9 +258,8 @@ static int get_data_rate(const struct motion_sensor_t *s)
 	return data->base.odr;
 }
 
-static int set_offset(const struct motion_sensor_t *s,
-			const int16_t *offset,
-			int16_t    temp)
+static int set_offset(const struct motion_sensor_t *s, const int16_t *offset,
+		      int16_t temp)
 {
 	/* temperature is ignored */
 	struct l3gd20_data *data = s->drv_data;
@@ -283,9 +269,8 @@ static int set_offset(const struct motion_sensor_t *s,
 	return EC_SUCCESS;
 }
 
-static int get_offset(const struct motion_sensor_t *s,
-			int16_t    *offset,
-			int16_t    *temp)
+static int get_offset(const struct motion_sensor_t *s, int16_t *offset,
+		      int16_t *temp)
 {
 	struct l3gd20_data *data = s->drv_data;
 	offset[X] = data->offset[X];
@@ -349,14 +334,14 @@ static int read(const struct motion_sensor_t *s, intv3_t v)
 	rotate(v, *s->rot_standard_ref, v);
 
 	/* apply offset in the device coordinates */
-	range = get_range(s);
+	range = s->current_range;
 	for (i = X; i <= Z; i++)
 		v[i] += (data->offset[i] << 5) / range;
 
 	return EC_SUCCESS;
 }
 
-static int init(const struct motion_sensor_t *s)
+static int init(struct motion_sensor_t *s)
 {
 	int ret = 0, tmp;
 
@@ -392,7 +377,6 @@ const struct accelgyro_drv l3gd20h_drv = {
 	.init = init,
 	.read = read,
 	.set_range = set_range,
-	.get_range = get_range,
 	.get_resolution = get_resolution,
 	.set_data_rate = set_data_rate,
 	.get_data_rate = get_data_rate,
diff --git a/driver/gyro_l3gd20h.h b/driver/gyro_l3gd20h.h
index 7a7ed6b7da..26e4e55d10 100644
--- a/driver/gyro_l3gd20h.h
+++ b/driver/gyro_l3gd20h.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,65 +15,65 @@
  * 7-bit address is 110101Xb. Where 'X' is determined
  * by the voltage on the ADDR pin.
  */
-#define L3GD20_ADDR0_FLAGS       0x6a
-#define L3GD20_ADDR1_FLAGS       0x6b
+#define L3GD20_ADDR0_FLAGS 0x6a
+#define L3GD20_ADDR1_FLAGS 0x6b
 
 /* who am I  */
-#define L3GD20_WHO_AM_I          0xd7
+#define L3GD20_WHO_AM_I 0xd7
 
 /* Chip specific registers. */
-#define L3GD20_WHO_AM_I_REG      0x0f
-#define L3GD20_CTRL_REG1         0x20
-#define L3GD20_CTRL_REG2         0x21
-#define L3GD20_CTRL_REG3         0x22
-#define L3GD20_CTRL_REG4         0x23
-#define L3GD20_CTRL_REG5         0x24
-#define L3GD20_CTRL_REFERENCE    0x25
-#define L3GD20_OUT_TEMP          0x26
-#define L3GD20_STATUS_REG        0x27
-#define L3GD20_OUT_X_L           0x28
-#define L3GD20_OUT_X_H           0x29
-#define L3GD20_OUT_Y_L           0x2a
-#define L3GD20_OUT_Y_H           0x2b
-#define L3GD20_OUT_Z_L           0x2c
-#define L3GD20_OUT_Z_H           0x2d
-#define L3GD20_FIFO_CTRL_REG     0x2e
-#define L3GD20_FIFO_SRC_REG      0x2f
-#define L3GD20_INT1_CFG          0x30
-#define L3GD20_INT1_SRC          0x31
-#define L3GD20_INT1_TSH_XH       0x32
-#define L3GD20_INT1_TSH_XL       0x33
-#define L3GD20_INT1_TSH_YH       0x34
-#define L3GD20_INT1_TSH_YL       0x35
-#define L3GD20_INT1_TSH_ZH       0x36
-#define L3GD20_INT1_TSH_ZL       0x37
-#define L3GD20_INT1_DURATION     0x38
-#define L3GD20_LOW_ODR           0x39
+#define L3GD20_WHO_AM_I_REG 0x0f
+#define L3GD20_CTRL_REG1 0x20
+#define L3GD20_CTRL_REG2 0x21
+#define L3GD20_CTRL_REG3 0x22
+#define L3GD20_CTRL_REG4 0x23
+#define L3GD20_CTRL_REG5 0x24
+#define L3GD20_CTRL_REFERENCE 0x25
+#define L3GD20_OUT_TEMP 0x26
+#define L3GD20_STATUS_REG 0x27
+#define L3GD20_OUT_X_L 0x28
+#define L3GD20_OUT_X_H 0x29
+#define L3GD20_OUT_Y_L 0x2a
+#define L3GD20_OUT_Y_H 0x2b
+#define L3GD20_OUT_Z_L 0x2c
+#define L3GD20_OUT_Z_H 0x2d
+#define L3GD20_FIFO_CTRL_REG 0x2e
+#define L3GD20_FIFO_SRC_REG 0x2f
+#define L3GD20_INT1_CFG 0x30
+#define L3GD20_INT1_SRC 0x31
+#define L3GD20_INT1_TSH_XH 0x32
+#define L3GD20_INT1_TSH_XL 0x33
+#define L3GD20_INT1_TSH_YH 0x34
+#define L3GD20_INT1_TSH_YL 0x35
+#define L3GD20_INT1_TSH_ZH 0x36
+#define L3GD20_INT1_TSH_ZL 0x37
+#define L3GD20_INT1_DURATION 0x38
+#define L3GD20_LOW_ODR 0x39
 
-#define L3GD20_DPS_SEL_245       (0 << 4)
-#define L3GD20_DPS_SEL_500       BIT(4)
-#define L3GD20_DPS_SEL_2000_0    (2 << 4)
-#define L3GD20_DPS_SEL_2000_1    (3 << 4)
+#define L3GD20_DPS_SEL_245 (0 << 4)
+#define L3GD20_DPS_SEL_500 BIT(4)
+#define L3GD20_DPS_SEL_2000_0 (2 << 4)
+#define L3GD20_DPS_SEL_2000_1 (3 << 4)
 
-#define L3GD20_ODR_PD            (0 << 3)
-#define L3GD20_ODR_12_5HZ        (0 << 6)
-#define L3GD20_ODR_25HZ          BIT(6)
-#define L3GD20_ODR_50HZ_0        (2 << 6)
-#define L3GD20_ODR_50HZ_1        (3 << 6)
-#define L3GD20_ODR_100HZ         (0 << 6)
-#define L3GD20_ODR_200HZ         BIT(6)
-#define L3GD20_ODR_400HZ         (2 << 6)
-#define L3GD20_ODR_800HZ         (3 << 6)
+#define L3GD20_ODR_PD (0 << 3)
+#define L3GD20_ODR_12_5HZ (0 << 6)
+#define L3GD20_ODR_25HZ BIT(6)
+#define L3GD20_ODR_50HZ_0 (2 << 6)
+#define L3GD20_ODR_50HZ_1 (3 << 6)
+#define L3GD20_ODR_100HZ (0 << 6)
+#define L3GD20_ODR_200HZ BIT(6)
+#define L3GD20_ODR_400HZ (2 << 6)
+#define L3GD20_ODR_800HZ (3 << 6)
 
-#define L3GD20_ODR_MASK          (3 << 6)
-#define L3GD20_STS_ZYXDA_MASK    BIT(3)
-#define L3GD20_RANGE_MASK        (3 << 4)
-#define L3GD20_LOW_ODR_MASK      BIT(0)
-#define L3GD20_ODR_PD_MASK       BIT(3)
+#define L3GD20_ODR_MASK (3 << 6)
+#define L3GD20_STS_ZYXDA_MASK BIT(3)
+#define L3GD20_RANGE_MASK (3 << 4)
+#define L3GD20_LOW_ODR_MASK BIT(0)
+#define L3GD20_ODR_PD_MASK BIT(3)
 
 /* Min and Max sampling frequency in mHz */
-#define L3GD20_GYRO_MIN_FREQ     12500
-#define L3GD20_GYRO_MAX_FREQ     \
+#define L3GD20_GYRO_MIN_FREQ 12500
+#define L3GD20_GYRO_MAX_FREQ \
 	MOTION_MAX_SENSOR_FREQUENCY(800000, L3GD20_GYRO_MIN_FREQ)
 
 /*
@@ -81,8 +81,8 @@
  * Address       : 0X27
  */
 enum l3gd20_status {
-	L3GD20_STS_DOWN          = 0x00,
-	L3GD20_STS_ZYXDA_UP      = 0x08,
+	L3GD20_STS_DOWN = 0x00,
+	L3GD20_STS_ZYXDA_UP = 0x08,
 };
 
 /*
@@ -91,12 +91,12 @@ enum l3gd20_status {
  * Bit Group Name: BDU
  */
 enum l3gd20_bdu {
-	L3GD20_BDU_DISABLE       = 0x00,
-	L3GD20_BDU_ENABLE        = 0x80,
+	L3GD20_BDU_DISABLE = 0x00,
+	L3GD20_BDU_ENABLE = 0x80,
 };
 
 /* Sensor resolution in number of bits. This sensor has fixed resolution. */
-#define L3GD20_RESOLUTION        16
+#define L3GD20_RESOLUTION 16
 
 extern const struct accelgyro_drv l3gd20h_drv;
 struct l3gd20_data {
diff --git a/driver/ina2xx.c b/driver/ina2xx.c
index 2b0fca07e5..7e07480fa1 100644
--- a/driver/ina2xx.c
+++ b/driver/ina2xx.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,24 +8,28 @@
 #include "console.h"
 #include "hooks.h"
 #include "i2c.h"
+#include "ina2xx.h"
 #include "system.h"
 #include "timer.h"
-#include "ina2xx.h"
 #include "util.h"
 
 /* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
 
 /* I2C base address */
+#if defined(CONFIG_INA231) || defined(CONFIG_INA219)
 #define INA2XX_I2C_ADDR_FLAGS 0x40
+#else
+#define INA2XX_I2C_ADDR_FLAGS 0x41
+#endif
 
 uint16_t ina2xx_read(uint8_t idx, uint8_t reg)
 {
 	int res;
 	int val;
 
-	res = i2c_read16(I2C_PORT_MASTER, INA2XX_I2C_ADDR_FLAGS | idx,
-			 reg, &val);
+	res = i2c_read16(I2C_PORT_MASTER, INA2XX_I2C_ADDR_FLAGS | idx, reg,
+			 &val);
 	if (res) {
 		CPRINTS("INA2XX I2C read failed");
 		return 0x0bad;
@@ -38,8 +42,8 @@ int ina2xx_write(uint8_t idx, uint8_t reg, uint16_t val)
 	int res;
 	uint16_t be_val = (val >> 8) | ((val & 0xff) << 8);
 
-	res = i2c_write16(I2C_PORT_MASTER, INA2XX_I2C_ADDR_FLAGS | idx,
-			  reg, be_val);
+	res = i2c_write16(I2C_PORT_MASTER, INA2XX_I2C_ADDR_FLAGS | idx, reg,
+			  be_val);
 	if (res)
 		CPRINTS("INA2XX I2C write failed");
 	return res;
@@ -75,6 +79,26 @@ int ina2xx_get_power(uint8_t idx)
 	return INA2XX_POW_MW((int)pow);
 }
 
+int ina2xx_get_mask(uint8_t idx)
+{
+	return ina2xx_read(idx, INA2XX_REG_MASK);
+}
+
+int ina2xx_set_mask(uint8_t idx, uint16_t mask)
+{
+	return ina2xx_write(idx, INA2XX_REG_MASK, mask);
+}
+
+int ina2xx_get_alert(uint8_t idx)
+{
+	return ina2xx_read(idx, INA2XX_REG_ALERT);
+}
+
+int ina2xx_set_alert(uint8_t idx, uint16_t alert)
+{
+	return ina2xx_write(idx, INA2XX_REG_ALERT, alert);
+}
+
 #ifdef CONFIG_CMD_INA
 static void ina2xx_dump(uint8_t idx)
 {
@@ -89,11 +113,10 @@ static void ina2xx_dump(uint8_t idx)
 
 	ccprintf("Configuration: %04x\n", cfg);
 	ccprintf("Shunt voltage: %04x => %d uV\n", sv,
-						   INA2XX_SHUNT_UV((int)sv));
-	ccprintf("Bus voltage  : %04x => %d mV\n", bv,
-						   INA2XX_BUS_MV((int)bv));
+		 INA2XX_SHUNT_UV((int)sv));
+	ccprintf("Bus voltage  : %04x => %d mV\n", bv, INA2XX_BUS_MV((int)bv));
 	ccprintf("Power        : %04x => %d mW\n", pow,
-						   INA2XX_POW_MW((int)pow));
+		 INA2XX_POW_MW((int)pow));
 	ccprintf("Current      : %04x => %d mA\n", curr, curr);
 	ccprintf("Calibration  : %04x\n", calib);
 	ccprintf("Mask/Enable  : %04x\n", mask);
@@ -103,7 +126,7 @@ static void ina2xx_dump(uint8_t idx)
 /*****************************************************************************/
 /* Console commands */
 
-static int command_ina(int argc, char **argv)
+static int command_ina(int argc, const char **argv)
 {
 	char *e;
 	int idx;
diff --git a/driver/ina2xx.h b/driver/ina2xx.h
index 69d602abba..3c8e7cd45f 100644
--- a/driver/ina2xx.h
+++ b/driver/ina2xx.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,28 +8,28 @@
 #ifndef __CROS_EC_INA2XX_H
 #define __CROS_EC_INA2XX_H
 
-#define INA2XX_REG_CONFIG     0x00
+#define INA2XX_REG_CONFIG 0x00
 #define INA2XX_REG_SHUNT_VOLT 0x01
-#define INA2XX_REG_BUS_VOLT   0x02
-#define INA2XX_REG_POWER      0x03
-#define INA2XX_REG_CURRENT    0x04
-#define INA2XX_REG_CALIB      0x05
-#define INA2XX_REG_MASK       0x06
-#define INA2XX_REG_ALERT      0x07
-
-#define INA2XX_CONFIG_MODE_MASK     (7 << 0)
-#define INA2XX_CONFIG_MODE_PWRDWN   (0 << 0)
-#define INA2XX_CONFIG_MODE_SHUNT    BIT(0)
-#define INA2XX_CONFIG_MODE_BUS      BIT(1)
-#define INA2XX_CONFIG_MODE_TRG      (0 << 2)
-#define INA2XX_CONFIG_MODE_CONT     BIT(2)
+#define INA2XX_REG_BUS_VOLT 0x02
+#define INA2XX_REG_POWER 0x03
+#define INA2XX_REG_CURRENT 0x04
+#define INA2XX_REG_CALIB 0x05
+#define INA2XX_REG_MASK 0x06
+#define INA2XX_REG_ALERT 0x07
+
+#define INA2XX_CONFIG_MODE_MASK (7 << 0)
+#define INA2XX_CONFIG_MODE_PWRDWN (0 << 0)
+#define INA2XX_CONFIG_MODE_SHUNT BIT(0)
+#define INA2XX_CONFIG_MODE_BUS BIT(1)
+#define INA2XX_CONFIG_MODE_TRG (0 << 2)
+#define INA2XX_CONFIG_MODE_CONT BIT(2)
 
 /* Conversion time for bus and shunt in micro-seconds */
 enum ina2xx_conv_time {
-	INA2XX_CONV_TIME_140  = 0x00,
-	INA2XX_CONV_TIME_204  = 0x01,
-	INA2XX_CONV_TIME_332  = 0x02,
-	INA2XX_CONV_TIME_588  = 0x03,
+	INA2XX_CONV_TIME_140 = 0x00,
+	INA2XX_CONV_TIME_204 = 0x01,
+	INA2XX_CONV_TIME_332 = 0x02,
+	INA2XX_CONV_TIME_588 = 0x03,
 	INA2XX_CONV_TIME_1100 = 0x04,
 	INA2XX_CONV_TIME_2116 = 0x05,
 	INA2XX_CONV_TIME_4156 = 0x06,
@@ -37,29 +37,28 @@ enum ina2xx_conv_time {
 };
 #define INA2XX_CONV_TIME_MASK 0x7
 #define INA2XX_CONFIG_SHUNT_CONV_TIME(t) ((t) << 3)
-#define INA2XX_CONFIG_BUS_CONV_TIME(t)   ((t) << 6)
-
-#define INA2XX_CONFIG_AVG_1        (0 << 9)
-#define INA2XX_CONFIG_AVG_4        BIT(9)
-#define INA2XX_CONFIG_AVG_16       (2 << 9)
-#define INA2XX_CONFIG_AVG_64       (3 << 9)
-#define INA2XX_CONFIG_AVG_128      (4 << 9)
-#define INA2XX_CONFIG_AVG_256      (5 << 9)
-#define INA2XX_CONFIG_AVG_512      (6 << 9)
-#define INA2XX_CONFIG_AVG_1024     (7 << 9)
-
-#define INA2XX_MASK_EN_LEN         BIT(0)
-#define INA2XX_MASK_EN_APOL        BIT(1)
-#define INA2XX_MASK_EN_OVF         BIT(2)
-#define INA2XX_MASK_EN_CVRF        BIT(3)
-#define INA2XX_MASK_EN_AFF         BIT(4)
-#define INA2XX_MASK_EN_CNVR        BIT(10)
-#define INA2XX_MASK_EN_POL         BIT(11)
-#define INA2XX_MASK_EN_BUL         BIT(12)
-#define INA2XX_MASK_EN_BOL         BIT(13)
-#define INA2XX_MASK_EN_SUL         BIT(14)
-#define INA2XX_MASK_EN_SOL        BIT(15)
-
+#define INA2XX_CONFIG_BUS_CONV_TIME(t) ((t) << 6)
+
+#define INA2XX_CONFIG_AVG_1 (0 << 9)
+#define INA2XX_CONFIG_AVG_4 BIT(9)
+#define INA2XX_CONFIG_AVG_16 (2 << 9)
+#define INA2XX_CONFIG_AVG_64 (3 << 9)
+#define INA2XX_CONFIG_AVG_128 (4 << 9)
+#define INA2XX_CONFIG_AVG_256 (5 << 9)
+#define INA2XX_CONFIG_AVG_512 (6 << 9)
+#define INA2XX_CONFIG_AVG_1024 (7 << 9)
+
+#define INA2XX_MASK_EN_LEN BIT(0)
+#define INA2XX_MASK_EN_APOL BIT(1)
+#define INA2XX_MASK_EN_OVF BIT(2)
+#define INA2XX_MASK_EN_CVRF BIT(3)
+#define INA2XX_MASK_EN_AFF BIT(4)
+#define INA2XX_MASK_EN_CNVR BIT(10)
+#define INA2XX_MASK_EN_POL BIT(11)
+#define INA2XX_MASK_EN_BUL BIT(12)
+#define INA2XX_MASK_EN_BOL BIT(13)
+#define INA2XX_MASK_EN_SUL BIT(14)
+#define INA2XX_MASK_EN_SOL BIT(15)
 
 #if defined(CONFIG_INA231) && defined(CONFIG_INA219)
 #error CONFIG_INA231 and CONFIG_INA219 must not be both defined.
@@ -68,27 +67,37 @@ enum ina2xx_conv_time {
 #ifdef CONFIG_INA231
 
 /* Calibration value to get current LSB = 1mA */
-#define INA2XX_CALIB_1MA(rsense_mohm) (5120/(rsense_mohm))
+#define INA2XX_CALIB_1MA(rsense_mohm) (5120 / (rsense_mohm))
 /* Bus voltage: mV per LSB */
-#define INA2XX_BUS_MV(reg) ((reg) * 125 / 100)
+#define INA2XX_BUS_MV(reg) ((reg)*125 / 100)
 /* Shunt voltage: uV per LSB */
-#define INA2XX_SHUNT_UV(reg) ((reg) * 25 / 10)
+#define INA2XX_SHUNT_UV(reg) ((reg)*25 / 10)
 /* Power LSB: mW per current LSB */
-#define INA2XX_POW_MW(reg) ((reg) * 25 * 1/*Current mA/LSB*/)
+#define INA2XX_POW_MW(reg) ((reg)*25 * 1 /*Current mA/LSB*/)
 
-#else /* CONFIG_INA219 */
+#elif CONFIG_INA219
 
 /* Calibration value to get current LSB = 1mA */
-#define INA2XX_CALIB_1MA(rsense_mohm) (40960/(rsense_mohm))
+#define INA2XX_CALIB_1MA(rsense_mohm) (40960 / (rsense_mohm))
 /* Bus voltage: mV per LSB */
 #define INA2XX_BUS_MV(reg) ((reg) / 2)
 /* Shunt voltage: uV */
-#define INA2XX_SHUNT_UV(reg) ((reg) * 10)
+#define INA2XX_SHUNT_UV(reg) ((reg)*10)
 /* Power LSB: mW per current LSB */
-#define INA2XX_POW_MW(reg) ((reg) * 20 * 1/*Current mA/LSB*/)
+#define INA2XX_POW_MW(reg) ((reg)*20 * 1 /*Current mA/LSB*/)
 
-#endif
+#else
+
+/* Calibration value to get current LSB = 1mA */
+#define INA2XX_CALIB_1MA(rsense_mohm) (5120 / (rsense_mohm))
+/* Bus voltage: mV per LSB */
+#define INA2XX_BUS_MV(reg) ((reg)*160 / 100)
+/* Shunt voltage: uV per LSB */
+#define INA2XX_SHUNT_UV(reg) ((reg)*25 / 10)
+/* Power LSB: mW per current LSB */
+#define INA2XX_POW_MW(reg) ((reg)*25 * 1 /*Current mA/LSB*/)
 
+#endif
 
 /* Read INA2XX register. */
 uint16_t ina2xx_read(uint8_t idx, uint8_t reg);
@@ -108,4 +117,16 @@ int ina2xx_get_current(uint8_t idx);
 /* Return power in milliWatts */
 int ina2xx_get_power(uint8_t idx);
 
+/* Return content of mask register */
+int ina2xx_get_mask(uint8_t idx);
+
+/* Set mask register to desired value */
+int ina2xx_set_mask(uint8_t idx, uint16_t mask);
+
+/* Return alert register value */
+int ina2xx_get_alert(uint8_t idx);
+
+/* Set alert register to desired value */
+int ina2xx_set_alert(uint8_t idx, uint16_t alert);
+
 #endif /* __CROS_EC_INA2XX_H */
diff --git a/driver/ina3221.c b/driver/ina3221.c
index 5b89f9694e..ec28ec3f26 100644
--- a/driver/ina3221.c
+++ b/driver/ina3221.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,18 +8,18 @@
 #include "console.h"
 #include "hooks.h"
 #include "i2c.h"
+#include "ina3221.h"
 #include "system.h"
 #include "timer.h"
-#include "ina3221.h"
 #include "util.h"
 
 /* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
 
 const static uint8_t ina3221_reg_map[INA3221_CHAN_COUNT][INA3221_MAX_REG] = {
-{ 1, 2,  7,  8 }, /* Chan 1 */
-{ 3, 4,  9, 10 }, /* Chan 2 */
-{ 5, 6, 11, 12 }  /* Chan 3 */
+	{ 1, 2, 7, 8 }, /* Chan 1 */
+	{ 3, 4, 9, 10 }, /* Chan 2 */
+	{ 5, 6, 11, 12 } /* Chan 3 */
 };
 
 static uint16_t ina3221_read(unsigned int unit, uint8_t reg)
@@ -27,8 +27,7 @@ static uint16_t ina3221_read(unsigned int unit, uint8_t reg)
 	int res;
 	int val;
 
-	res = i2c_read16(ina3221[unit].port, ina3221[unit].address,
-			 reg, &val);
+	res = i2c_read16(ina3221[unit].port, ina3221[unit].address, reg, &val);
 	if (res) {
 		CPRINTS("INA3221 I2C read failed");
 		return 0x0bad;
@@ -37,7 +36,7 @@ static uint16_t ina3221_read(unsigned int unit, uint8_t reg)
 }
 
 static uint16_t ina3221_chan_read(unsigned int unit, enum ina3221_channel chan,
-			   enum ina3221_register reg)
+				  enum ina3221_register reg)
 {
 	if (chan >= INA3221_CHAN_COUNT || reg >= INA3221_MAX_REG) {
 		CPRINTS("INA3221 Bad channel or register value");
@@ -51,8 +50,8 @@ static int ina3221_write(unsigned int unit, uint8_t reg, uint16_t val)
 	int res;
 	uint16_t be_val = (val >> 8) | ((val & 0xff) << 8);
 
-	res = i2c_write16(ina3221[unit].port, ina3221[unit].address,
-			  reg, be_val);
+	res = i2c_write16(ina3221[unit].port, ina3221[unit].address, reg,
+			  be_val);
 	if (res)
 		CPRINTS("INA3221 I2C write failed");
 	return res;
@@ -93,12 +92,12 @@ static void ina3221_dump(unsigned int unit)
 		if (ina3221[unit].name[chan] != NULL) {
 			sv[chan] = ina3221_chan_read(unit, chan,
 						     INA3221_SHUNT_VOLT);
-			bv[chan] = ina3221_chan_read(unit, chan,
-						     INA3221_BUS_VOLT);
-			crit[chan] = ina3221_chan_read(unit, chan,
-						       INA3221_CRITICAL);
-			warn[chan] = ina3221_chan_read(unit, chan,
-						       INA3221_WARNING);
+			bv[chan] =
+				ina3221_chan_read(unit, chan, INA3221_BUS_VOLT);
+			crit[chan] =
+				ina3221_chan_read(unit, chan, INA3221_CRITICAL);
+			warn[chan] =
+				ina3221_chan_read(unit, chan, INA3221_WARNING);
 		}
 	}
 	mask = ina3221_read(unit, INA3221_REG_MASK);
@@ -109,9 +108,9 @@ static void ina3221_dump(unsigned int unit)
 		if (ina3221[unit].name[chan] != NULL) {
 			ccprintf("%d: %s:\n", chan, ina3221[unit].name[chan]);
 			ccprintf("      Shunt voltage: %04x => %d uV\n",
-				sv[chan], INA3221_SHUNT_UV((int)sv[chan]));
+				 sv[chan], INA3221_SHUNT_UV((int)sv[chan]));
 			ccprintf("      Bus voltage  : %04x => %d mV\n",
-				bv[chan], INA3221_BUS_MV((int)bv[chan]));
+				 bv[chan], INA3221_BUS_MV((int)bv[chan]));
 			ccprintf("      Warning      : %04x\n", warn[chan]);
 			ccprintf("      Critical     : %04x\n", crit[chan]);
 		}
@@ -122,7 +121,7 @@ static void ina3221_dump(unsigned int unit)
 /*****************************************************************************/
 /* Console commands */
 
-static int command_ina(int argc, char **argv)
+static int command_ina(int argc, const char **argv)
 {
 	char *e;
 	unsigned int unit;
@@ -156,7 +155,6 @@ static int command_ina(int argc, char **argv)
 
 	return EC_ERROR_INVAL;
 }
-DECLARE_CONSOLE_COMMAND(ina, command_ina,
-			"<index> [config|mask <val>]",
+DECLARE_CONSOLE_COMMAND(ina, command_ina, "<index> [config|mask <val>]",
 			"INA3221 voltage sensing");
 #endif
diff --git a/driver/ina3221.h b/driver/ina3221.h
index 4d8c8211b4..5d642bba3b 100644
--- a/driver/ina3221.h
+++ b/driver/ina3221.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,8 +8,8 @@
 #ifndef __CROS_EC_INA3221_H
 #define __CROS_EC_INA3221_H
 
-#define INA3221_REG_CONFIG	0x00
-#define INA3221_REG_MASK	0x0F
+#define INA3221_REG_CONFIG 0x00
+#define INA3221_REG_MASK 0x0F
 
 /*
  * Common bits are:
@@ -18,12 +18,12 @@
  * conversion time = 1.1 ms
  * mode = shunt and bus, continuous.
  */
-#define INA3221_CONFIG_BASE	0x8127
+#define INA3221_CONFIG_BASE 0x8127
 
 /* Bus voltage: lower 3 bits clear, LSB = 8 mV */
 #define INA3221_BUS_MV(reg) (reg)
 /* Shunt voltage: lower 3 bits clear, LSB = 40 uV */
-#define INA3221_SHUNT_UV(reg) ((reg) * (40/8))
+#define INA3221_SHUNT_UV(reg) ((reg) * (40 / 8))
 
 enum ina3221_channel {
 	INA3221_CHAN_1 = 0,
@@ -43,9 +43,9 @@ enum ina3221_register {
 
 /* Configuration table - defined in board file. */
 struct ina3221_t {
-	int port;             /* I2C port index */
-	uint8_t address;      /* I2C address */
-	const char *name[INA3221_CHAN_COUNT];  /* Channel names */
+	int port; /* I2C port index */
+	uint8_t address; /* I2C address */
+	const char *name[INA3221_CHAN_COUNT]; /* Channel names */
 };
 
 /* External config in board file */
diff --git a/driver/ioexpander/ccgxxf.c b/driver/ioexpander/ccgxxf.c
new file mode 100644
index 0000000000..a95d17ada3
--- /dev/null
+++ b/driver/ioexpander/ccgxxf.c
@@ -0,0 +1,157 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Cypress CCGXXF I/O Port expander (built inside PD chip) driver source
+ */
+
+#include "console.h"
+#include "i2c.h"
+#include "ioexpander.h"
+
+/* Add after all include files */
+#include "ccgxxf.h"
+
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
+
+static inline int ccgxxf_read8(int ioex, int reg, int *data)
+{
+	return i2c_read8(ioex_config[ioex].i2c_host_port,
+			 ioex_config[ioex].i2c_addr_flags, reg, data);
+}
+
+static inline int ccgxxf_update8(int ioex, int reg, uint8_t mask,
+				 enum mask_update_action action)
+{
+	return i2c_update8(ioex_config[ioex].i2c_host_port,
+			   ioex_config[ioex].i2c_addr_flags, reg, mask, action);
+}
+
+static inline int ccgxxf_write16(int ioex, uint16_t reg, uint16_t data)
+{
+	return i2c_write16(ioex_config[ioex].i2c_host_port,
+			   ioex_config[ioex].i2c_addr_flags, reg, data);
+}
+
+static int ccgxxf_get_level(int ioex, int port, int mask, int *val)
+{
+	int rv;
+
+	rv = ccgxxf_read8(ioex, CCGXXF_REG_GPIO_STATUS(port), val);
+	if (!rv)
+		*val = !!(*val & mask);
+
+	return rv;
+}
+
+static int ccgxxf_set_level(int ioex, int port, int mask, int val)
+{
+	return ccgxxf_update8(ioex, CCGXXF_REG_GPIO_CONTROL(port), mask, val);
+}
+
+/*
+ * Following type of pins are supported
+ * - Output pins are supported with open-drain & pull-up
+ * - Input pins are supported with pull-up & pull-down
+ * - Analog pins
+ * - 1.8V level GPIOs are supported per port and outputs can only be
+ *   open-drain pins
+ */
+static int ccgxxf_set_flags_by_mask(int ioex, int port, int mask, int flags)
+{
+	uint16_t pin_mode;
+	int rv;
+
+	/* Push-pull output can't be configured for 1.8V level */
+	if ((flags & GPIO_OUTPUT) && (flags & GPIO_SEL_1P8V) &&
+	    !(flags & GPIO_OPEN_DRAIN)) {
+		CPRINTS("Invalid flags: ioex=%d, port=%d, mask=%d, flags=0x%x",
+			ioex, port, mask, flags);
+
+		return EC_ERROR_INVAL;
+	}
+
+	if (flags & GPIO_OUTPUT) {
+		if (flags & GPIO_OPEN_DRAIN) {
+			if (flags & GPIO_PULL_UP)
+				pin_mode = CCGXXF_GPIO_MODE_RES_UP;
+			else
+				pin_mode = CCGXXF_GPIO_MODE_OD_LOW;
+		} else {
+			pin_mode = CCGXXF_GPIO_MODE_STRONG;
+		}
+	} else if (flags & GPIO_INPUT) {
+		if (flags & GPIO_PULL_UP) {
+			pin_mode = CCGXXF_GPIO_MODE_RES_UP;
+			flags |= GPIO_HIGH;
+		} else if (flags & GPIO_PULL_DOWN) {
+			pin_mode = CCGXXF_GPIO_MODE_RES_DWN;
+			flags |= GPIO_LOW;
+		} else {
+			pin_mode = CCGXXF_GPIO_MODE_HIZ_DIGITAL;
+		}
+#ifndef CONFIG_ZEPHYR
+	} else if (flags & GPIO_ANALOG) {
+		pin_mode = CCGXXF_GPIO_MODE_HIZ_ANALOG;
+#endif
+	} else {
+		return EC_ERROR_INVAL;
+	}
+
+	pin_mode = port | (pin_mode << CCGXXF_GPIO_PIN_MODE_SHIFT) |
+		   (mask << CCGXXF_GPIO_PIN_MASK_SHIFT);
+
+	/* Note: once set the 1.8V level affect whole GPIO port */
+	if (flags & GPIO_SEL_1P8V)
+		pin_mode |= CCGXXF_GPIO_1P8V_SEL;
+
+	/*
+	 * Before setting the GPIO mode, initilaize the pins to default value
+	 * to avoid spike on pins.
+	 */
+	if (flags & (GPIO_HIGH | GPIO_LOW)) {
+		rv = ccgxxf_set_level(ioex, port, mask,
+				      flags & GPIO_HIGH ? 1 : 0);
+		if (rv)
+			return rv;
+	}
+
+	return ccgxxf_write16(ioex, CCGXXF_REG_GPIO_MODE, pin_mode);
+}
+
+static int ccgxxf_get_flags_by_mask(int ioex, int port, int mask, int *flags)
+{
+	/* TODO: Add it after implementing in the CCGXXF firmware. */
+	return EC_SUCCESS;
+}
+
+static int ccgxxf_enable_interrupt(int ioex, int port, int mask, int enable)
+{
+	/* CCGXXF doesn't have interrupt capability on I/O expnader pins */
+	return EC_ERROR_UNIMPLEMENTED;
+}
+
+#ifdef CONFIG_IO_EXPANDER_SUPPORT_GET_PORT
+static int ccgxxf_get_port(int ioex, int port, int *val)
+{
+	return ccgxxf_read8(ioex, CCGXXF_REG_GPIO_STATUS(port), val);
+}
+#endif
+
+int ccgxxf_init(int ioex)
+{
+	/* TCPC init of CCGXXF should handle initialization */
+	return EC_SUCCESS;
+}
+
+const struct ioexpander_drv ccgxxf_ioexpander_drv = {
+	.init = &ccgxxf_init,
+	.get_level = &ccgxxf_get_level,
+	.set_level = &ccgxxf_set_level,
+	.get_flags_by_mask = &ccgxxf_get_flags_by_mask,
+	.set_flags_by_mask = &ccgxxf_set_flags_by_mask,
+	.enable_interrupt = &ccgxxf_enable_interrupt,
+#ifdef CONFIG_IO_EXPANDER_SUPPORT_GET_PORT
+	.get_port = &ccgxxf_get_port,
+#endif
+};
diff --git a/driver/ioexpander/ioexpander_nct38xx.c b/driver/ioexpander/ioexpander_nct38xx.c
index ae7957e013..a97bf06908 100644
--- a/driver/ioexpander/ioexpander_nct38xx.c
+++ b/driver/ioexpander/ioexpander_nct38xx.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,10 +11,14 @@
 #include "i2c.h"
 #include "ioexpander.h"
 #include "nct38xx.h"
-#include "tcpci.h"
+#include "tcpm/tcpci.h"
 
-#define CPRINTF(format, args...) cprintf(CC_GPIO, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_GPIO, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
+
+#ifdef CONFIG_IO_EXPANDER_SUPPORT_GET_PORT
+#error "This driver doesn't support get_port function"
+#endif
 
 /*
  * Store the GPIO_ALERT_MASK_0/1 and chip ID registers locally. In this way,
@@ -26,7 +30,7 @@ struct nct38xx_chip_data {
 };
 
 static struct nct38xx_chip_data chip_data[CONFIG_IO_EXPANDER_PORT_COUNT] = {
-	 [0 ... (CONFIG_IO_EXPANDER_PORT_COUNT - 1)] =  { {0, 0}, -1 }
+	[0 ...(CONFIG_IO_EXPANDER_PORT_COUNT - 1)] = { { 0, 0 }, -1 }
 };
 
 static int nct38xx_ioex_check_is_valid(int ioex, int port, int mask)
@@ -37,9 +41,8 @@ static int nct38xx_ioex_check_is_valid(int ioex, int port, int mask)
 			return EC_ERROR_INVAL;
 		}
 		if (mask & ~NCT38XXX_3808_VALID_GPIO_MASK) {
-
 			CPRINTF("GPIO%02d is not support in NCT3808\n",
-							__fls(mask));
+				__fls(mask));
 			return EC_ERROR_INVAL;
 		}
 	}
@@ -57,12 +60,12 @@ static int nct38xx_ioex_init(int ioex)
 	 *  000: NCT3807
 	 *  010: NCT3808
 	 */
-	rv = i2c_read8(ioex_p->i2c_host_port, ioex_p->i2c_slave_addr,
-			TCPC_REG_BCD_DEV, &val);
+	rv = i2c_read8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags,
+		       TCPC_REG_BCD_DEV, &val);
 
 	if (rv != EC_SUCCESS) {
 		CPRINTF("Failed to read NCT38XX DEV ID for IOexpander %d\n",
-					ioex);
+			ioex);
 		return rv;
 	}
 
@@ -77,9 +80,9 @@ static int nct38xx_ioex_init(int ioex)
 	 * function of IOEX when the NCT38XX TCPCI driver is not included.
 	 */
 	if (!IS_ENABLED(CONFIG_USB_PD_TCPM_NCT38XX)) {
-		rv = i2c_write16(ioex_p->i2c_host_port,
-				ioex_p->i2c_slave_addr, TCPC_REG_ALERT_MASK,
-				TCPC_REG_ALERT_VENDOR_DEF);
+		rv = i2c_write16(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags,
+				 TCPC_REG_ALERT_MASK,
+				 TCPC_REG_ALERT_VENDOR_DEF);
 		if (rv != EC_SUCCESS)
 			return rv;
 	}
@@ -96,7 +99,7 @@ static int nct38xx_ioex_get_level(int ioex, int port, int mask, int *val)
 
 	reg = NCT38XX_REG_GPIO_DATA_IN(port);
 	rv = i2c_read8(ioex_config[ioex].i2c_host_port,
-			ioex_config[ioex].i2c_slave_addr, reg, val);
+		       ioex_config[ioex].i2c_addr_flags, reg, val);
 	if (rv != EC_SUCCESS)
 		return rv;
 
@@ -116,7 +119,7 @@ static int nct38xx_ioex_set_level(int ioex, int port, int mask, int value)
 	reg = NCT38XX_REG_GPIO_DATA_OUT(port);
 
 	rv = i2c_read8(ioex_config[ioex].i2c_host_port,
-			ioex_config[ioex].i2c_slave_addr, reg, &val);
+		       ioex_config[ioex].i2c_addr_flags, reg, &val);
 	if (rv != EC_SUCCESS)
 		return rv;
 
@@ -126,7 +129,7 @@ static int nct38xx_ioex_set_level(int ioex, int port, int mask, int value)
 		val &= ~mask;
 
 	return i2c_write8(ioex_config[ioex].i2c_host_port,
-			ioex_config[ioex].i2c_slave_addr, reg, val);
+			  ioex_config[ioex].i2c_addr_flags, reg, val);
 }
 
 static int nct38xx_ioex_get_flags(int ioex, int port, int mask, int *flags)
@@ -135,7 +138,7 @@ static int nct38xx_ioex_get_flags(int ioex, int port, int mask, int *flags)
 	struct ioexpander_config_t *ioex_p = &ioex_config[ioex];
 
 	i2c_port = ioex_p->i2c_host_port;
-	i2c_addr = ioex_p->i2c_slave_addr;
+	i2c_addr = ioex_p->i2c_addr_flags;
 
 	rv = nct38xx_ioex_check_is_valid(ioex, port, mask);
 	if (rv != EC_SUCCESS)
@@ -173,7 +176,7 @@ static int nct38xx_ioex_get_flags(int ioex, int port, int mask, int *flags)
 }
 
 static int nct38xx_ioex_sel_int_type(int i2c_port, int i2c_addr, int port,
-					int mask, int flags)
+				     int mask, int flags)
 {
 	int rv;
 	int reg_rising, reg_falling;
@@ -218,7 +221,7 @@ static int nct38xx_ioex_sel_int_type(int i2c_port, int i2c_addr, int port,
 		if (rv != EC_SUCCESS)
 			return rv;
 	} else if ((flags & GPIO_INT_F_RISING) ||
-				(flags & GPIO_INT_F_FALLING)) {
+		   (flags & GPIO_INT_F_FALLING)) {
 		if (flags & GPIO_INT_F_RISING)
 			rising |= mask;
 		else
@@ -238,13 +241,13 @@ static int nct38xx_ioex_sel_int_type(int i2c_port, int i2c_addr, int port,
 }
 
 static int nct38xx_ioex_set_flags_by_mask(int ioex, int port, int mask,
-					int flags)
+					  int flags)
 {
 	int rv, reg, val, i2c_port, i2c_addr;
 	struct ioexpander_config_t *ioex_p = &ioex_config[ioex];
 
 	i2c_port = ioex_p->i2c_host_port;
-	i2c_addr = ioex_p->i2c_slave_addr;
+	i2c_addr = ioex_p->i2c_addr_flags;
 
 	rv = nct38xx_ioex_check_is_valid(ioex, port, mask);
 	if (rv != EC_SUCCESS)
@@ -256,8 +259,8 @@ static int nct38xx_ioex_set_flags_by_mask(int ioex, int port, int mask,
 	 */
 	if (port == 0) {
 		/* GPIO03 in NCT3807 is not muxed with other function. */
-		if (!(chip_data[ioex].chip_id ==
-					NCT38XX_VARIANT_3807 && mask & 0x08)) {
+		if (!(chip_data[ioex].chip_id == NCT38XX_VARIANT_3807 &&
+		      mask & 0x08)) {
 			reg = NCT38XX_REG_MUX_CONTROL;
 			rv = i2c_read8(i2c_port, i2c_addr, reg, &val);
 			if (rv != EC_SUCCESS)
@@ -316,7 +319,7 @@ static int nct38xx_ioex_set_flags_by_mask(int ioex, int port, int mask,
 	else
 		val &= ~mask;
 
-	return  i2c_write8(i2c_port, i2c_addr, reg, val);
+	return i2c_write8(i2c_port, i2c_addr, reg, val);
 }
 
 /*
@@ -337,7 +340,7 @@ static int nct38xx_ioex_set_flags_by_mask(int ioex, int port, int mask,
  *    TCPC.
  */
 static int nct38xx_ioex_enable_interrupt(int ioex, int port, int mask,
-					int enable)
+					 int enable)
 {
 	int rv, reg, val;
 	struct ioexpander_config_t *ioex_p = &ioex_config[ioex];
@@ -348,14 +351,14 @@ static int nct38xx_ioex_enable_interrupt(int ioex, int port, int mask,
 
 	/* Clear the pending bit */
 	reg = NCT38XX_REG_GPIO_ALERT_STAT(port);
-	rv = i2c_read8(ioex_p->i2c_host_port, ioex_p->i2c_slave_addr,
-					reg, &val);
+	rv = i2c_read8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, reg,
+		       &val);
 	if (rv != EC_SUCCESS)
 		return rv;
 
 	val |= mask;
-	rv = i2c_write8(ioex_p->i2c_host_port, ioex_p->i2c_slave_addr,
-					reg, val);
+	rv = i2c_write8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, reg,
+			val);
 	if (rv != EC_SUCCESS)
 		return rv;
 
@@ -370,8 +373,8 @@ static int nct38xx_ioex_enable_interrupt(int ioex, int port, int mask,
 		val = chip_data[ioex].int_mask[port];
 	}
 
-	return i2c_write8(ioex_p->i2c_host_port, ioex_p->i2c_slave_addr,
-					reg, val);
+	return i2c_write8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, reg,
+			  val);
 }
 
 int nct38xx_ioex_event_handler(int ioex)
@@ -382,15 +385,15 @@ int nct38xx_ioex_event_handler(int ioex)
 	struct ioexpander_config_t *ioex_p = &ioex_config[ioex];
 	int rv = 0;
 
-	int_mask = chip_data[ioex].int_mask[0] | (
-				chip_data[ioex].int_mask[1] << 8);
+	int_mask = chip_data[ioex].int_mask[0] |
+		   (chip_data[ioex].int_mask[1] << 8);
 	reg = NCT38XX_REG_GPIO_ALERT_STAT(0);
 	/*
 	 * Read ALERT_STAT_0 and ALERT_STAT_1 register in a single I2C
 	 * transaction to increase efficiency
 	 */
-	rv = i2c_read16(ioex_p->i2c_host_port, ioex_p->i2c_slave_addr,
-					reg, &int_status);
+	rv = i2c_read16(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, reg,
+			&int_status);
 	if (rv != EC_SUCCESS)
 		return rv;
 
@@ -399,15 +402,15 @@ int nct38xx_ioex_event_handler(int ioex)
 	 * Clear the changed status bits in ALERT_STAT_0 and ALERT_STAT_1
 	 * register in a single I2C transaction to increase efficiency
 	 */
-	rv = i2c_write16(ioex_p->i2c_host_port, ioex_p->i2c_slave_addr,
-					reg, int_status);
+	rv = i2c_write16(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, reg,
+			 int_status);
 	if (rv != EC_SUCCESS)
 		return rv;
 
 	/* For NCT3808, only check one port */
 	total_port = (chip_data[ioex].chip_id == NCT38XX_VARIANT_3808) ?
-		NCT38XX_NCT3808_MAX_IO_PORT :
-		NCT38XX_NCT3807_MAX_IO_PORT;
+			     NCT38XX_NCT3808_MAX_IO_PORT :
+			     NCT38XX_NCT3807_MAX_IO_PORT;
 	for (i = 0; i < total_port; i++) {
 		uint8_t pending;
 
@@ -417,15 +420,13 @@ int nct38xx_ioex_event_handler(int ioex)
 			continue;
 
 		for (j = 0, g = ioex_list; j < ioex_ih_count; j++, g++) {
-
 			if (ioex == g->ioex && i == g->port &&
-						(pending & g->mask)) {
-				ioex_irq_handlers[j](j);
+			    (pending & g->mask)) {
+				ioex_irq_handlers[j](j + IOEX_SIGNAL_START);
 				pending &= ~g->mask;
 				if (!pending)
 					break;
 			}
-
 		}
 	}
 
@@ -443,15 +444,14 @@ void nct38xx_ioex_handle_alert(int ioex)
 	int rv, status;
 	struct ioexpander_config_t *ioex_p = &ioex_config[ioex];
 
-	rv = i2c_read16(ioex_p->i2c_host_port, ioex_p->i2c_slave_addr,
+	rv = i2c_read16(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags,
 			TCPC_REG_ALERT, &status);
 	if (rv != EC_SUCCESS)
 		CPRINTF("fail to read ALERT register\n");
 
 	if (status & TCPC_REG_ALERT_VENDOR_DEF) {
-		rv = i2c_write16(ioex_p->i2c_host_port,
-				ioex_p->i2c_slave_addr, TCPC_REG_ALERT,
-				TCPC_REG_ALERT_VENDOR_DEF);
+		rv = i2c_write16(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags,
+				 TCPC_REG_ALERT, TCPC_REG_ALERT_VENDOR_DEF);
 		if (rv != EC_SUCCESS) {
 			CPRINTF("Fail to clear Vendor Define mask\n");
 			return;
@@ -461,10 +461,10 @@ void nct38xx_ioex_handle_alert(int ioex)
 }
 
 const struct ioexpander_drv nct38xx_ioexpander_drv = {
-	.init              = &nct38xx_ioex_init,
-	.get_level         = &nct38xx_ioex_get_level,
-	.set_level         = &nct38xx_ioex_set_level,
+	.init = &nct38xx_ioex_init,
+	.get_level = &nct38xx_ioex_get_level,
+	.set_level = &nct38xx_ioex_set_level,
 	.get_flags_by_mask = &nct38xx_ioex_get_flags,
 	.set_flags_by_mask = &nct38xx_ioex_set_flags_by_mask,
-	.enable_interrupt  = &nct38xx_ioex_enable_interrupt,
+	.enable_interrupt = &nct38xx_ioex_enable_interrupt,
 };
diff --git a/driver/ioexpander/it8300.h b/driver/ioexpander/it8300.h
index 2b47e7f3e1..ce1dfc91a8 100644
--- a/driver/ioexpander/it8300.h
+++ b/driver/ioexpander/it8300.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,96 +11,96 @@
 #include "i2c.h"
 
 /* Gather Interrupt Status Register */
-#define IT8300_GISR		0x0
+#define IT8300_GISR 0x0
 
 /* Interrupt Status Registers */
-#define IT8300_ISR_A		0x6
-#define IT8300_ISR_B		0x7
-#define IT8300_ISR_C		0x28
-#define IT8300_ISR_D		0x2E
-#define IT8300_ISR_E		0x2F
+#define IT8300_ISR_A 0x6
+#define IT8300_ISR_B 0x7
+#define IT8300_ISR_C 0x28
+#define IT8300_ISR_D 0x2E
+#define IT8300_ISR_E 0x2F
 
 /* Port Data Register Groups */
-#define IT8300_PDGR_A		0x1
-#define IT8300_PDGR_B		0x2
-#define IT8300_PDGR_C		0x3
-#define IT8300_PDGR_D		0x4
-#define IT8300_PDGR_E		0x5
+#define IT8300_PDGR_A 0x1
+#define IT8300_PDGR_B 0x2
+#define IT8300_PDGR_C 0x3
+#define IT8300_PDGR_D 0x4
+#define IT8300_PDGR_E 0x5
 
 /* GPIO Port Control n Registers */
-#define IT8300_GPCR_A0		0x10
-#define IT8300_GPCR_A1		0x11
-#define IT8300_GPCR_A2		0x12
-#define IT8300_GPCR_A3		0x13
-#define IT8300_GPCR_A4		0x14
-#define IT8300_GPCR_A5		0x15
-#define IT8300_GPCR_A6		0x16
-#define IT8300_GPCR_A7		0x17
-
-#define IT8300_GPCR_B0		0x18
-#define IT8300_GPCR_B1		0x19
-#define IT8300_GPCR_B2		0x1A
-#define IT8300_GPCR_B3		0x1B
-#define IT8300_GPCR_B4		0x1C
-#define IT8300_GPCR_B5		0x1D
-#define IT8300_GPCR_B6		0x1E
-
-#define IT8300_GPCR_C0		0x20
-#define IT8300_GPCR_C1		0x21
-#define IT8300_GPCR_C2		0x22
-#define IT8300_GPCR_C3		0x23
-#define IT8300_GPCR_C4		0x24
-#define IT8300_GPCR_C5		0x25
-#define IT8300_GPCR_C6		0x26
-
-#define IT8300_GPCR_D0		0x08
-#define IT8300_GPCR_D1		0x09
-#define IT8300_GPCR_D2		0x0A
-#define IT8300_GPCR_D3		0x0B
-#define IT8300_GPCR_D4		0x0C
-#define IT8300_GPCR_D5		0x0D
-
-#define IT8300_GPCR_E0		0x32
-
-#define IT8300_GPCR_E2		0x34
-#define IT8300_GPCR_E3		0x35
-#define IT8300_GPCR_E4		0x36
-#define IT8300_GPCR_E5		0x37
-#define IT8300_GPCR_E6		0x38
-
-#define IT8300_GPCR_GPI_MODE	BIT(7)
-#define IT8300_GPCR_GP0_MODE	BIT(6)
-#define IT8300_GPCR_PULL_UP_EN	BIT(2)
-#define IT8300_GPCR_PULL_DN_EN	BIT(1)
+#define IT8300_GPCR_A0 0x10
+#define IT8300_GPCR_A1 0x11
+#define IT8300_GPCR_A2 0x12
+#define IT8300_GPCR_A3 0x13
+#define IT8300_GPCR_A4 0x14
+#define IT8300_GPCR_A5 0x15
+#define IT8300_GPCR_A6 0x16
+#define IT8300_GPCR_A7 0x17
+
+#define IT8300_GPCR_B0 0x18
+#define IT8300_GPCR_B1 0x19
+#define IT8300_GPCR_B2 0x1A
+#define IT8300_GPCR_B3 0x1B
+#define IT8300_GPCR_B4 0x1C
+#define IT8300_GPCR_B5 0x1D
+#define IT8300_GPCR_B6 0x1E
+
+#define IT8300_GPCR_C0 0x20
+#define IT8300_GPCR_C1 0x21
+#define IT8300_GPCR_C2 0x22
+#define IT8300_GPCR_C3 0x23
+#define IT8300_GPCR_C4 0x24
+#define IT8300_GPCR_C5 0x25
+#define IT8300_GPCR_C6 0x26
+
+#define IT8300_GPCR_D0 0x08
+#define IT8300_GPCR_D1 0x09
+#define IT8300_GPCR_D2 0x0A
+#define IT8300_GPCR_D3 0x0B
+#define IT8300_GPCR_D4 0x0C
+#define IT8300_GPCR_D5 0x0D
+
+#define IT8300_GPCR_E0 0x32
+
+#define IT8300_GPCR_E2 0x34
+#define IT8300_GPCR_E3 0x35
+#define IT8300_GPCR_E4 0x36
+#define IT8300_GPCR_E5 0x37
+#define IT8300_GPCR_E6 0x38
+
+#define IT8300_GPCR_GPI_MODE BIT(7)
+#define IT8300_GPCR_GP0_MODE BIT(6)
+#define IT8300_GPCR_PULL_UP_EN BIT(2)
+#define IT8300_GPCR_PULL_DN_EN BIT(1)
 
 /* EXGPIO Clear Alert */
-#define IT8300_ECA		0x30
+#define IT8300_ECA 0x30
 
 /* EXGPIO Alert Enable */
-#define IT8300_EAE		0x31
+#define IT8300_EAE 0x31
 
 /* Port Data Mirror Registers */
-#define IT8300_PDMRA_A		0x29
-#define IT8300_PDMRA_B		0x2A
-#define IT8300_PDMRA_C		0x2B
-#define IT8300_PDMRA_D		0x2C
-#define IT8300_PDMRA_E		0x2D
+#define IT8300_PDMRA_A 0x29
+#define IT8300_PDMRA_B 0x2A
+#define IT8300_PDMRA_C 0x2B
+#define IT8300_PDMRA_D 0x2C
+#define IT8300_PDMRA_E 0x2D
 
 /* Output Open-Drain Enable Registers */
-#define IT8300_OODER_A		0x39
-#define IT8300_OODER_B		0x3A
-#define IT8300_OODER_C		0x3B
-#define IT8300_OODER_D		0x3C
-#define IT8300_OODER_E		0x3D
+#define IT8300_OODER_A 0x39
+#define IT8300_OODER_B 0x3A
+#define IT8300_OODER_C 0x3B
+#define IT8300_OODER_D 0x3C
+#define IT8300_OODER_E 0x3D
 
 /* IT83200 Port GPIOs */
-#define IT8300_GPX_0		BIT(0)
-#define IT8300_GPX_1		BIT(1)
-#define IT8300_GPX_2		BIT(2)
-#define IT8300_GPX_3		BIT(3)
-#define IT8300_GPX_4		BIT(4)
-#define IT8300_GPX_5		BIT(5)
-#define IT8300_GPX_6		BIT(6)
-#define IT8300_GPX_7		BIT(7)
+#define IT8300_GPX_0 BIT(0)
+#define IT8300_GPX_1 BIT(1)
+#define IT8300_GPX_2 BIT(2)
+#define IT8300_GPX_3 BIT(3)
+#define IT8300_GPX_4 BIT(4)
+#define IT8300_GPX_5 BIT(5)
+#define IT8300_GPX_6 BIT(6)
+#define IT8300_GPX_7 BIT(7)
 
 #endif /* __CROS_EC_IOEXPANDER_IT8300_H */
diff --git a/driver/ioexpander/it8801.c b/driver/ioexpander/it8801.c
index d59bee8e3f..932cbb2648 100644
--- a/driver/ioexpander/it8801.c
+++ b/driver/ioexpander/it8801.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,30 +6,33 @@
 #include "common.h"
 #include "console.h"
 #include "gpio.h"
+#include "hooks.h"
 #include "i2c.h"
 #include "ioexpander.h"
 #include "it8801.h"
+#include "keyboard_backlight.h"
 #include "keyboard_raw.h"
 #include "keyboard_scan.h"
 #include "registers.h"
 #include "task.h"
 #include "util.h"
-#include "keyboard_backlight.h"
 
-#define CPRINTS(format, args...) cprints(CC_KEYSCAN, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_KEYSCAN, format, ##args)
 
 static int it8801_ioex_set_level(int ioex, int port, int mask, int value);
+static void it8801_ioex_event_handler(void);
+DECLARE_DEFERRED(it8801_ioex_event_handler);
 
 static int it8801_read(int reg, int *data)
 {
-	return i2c_read8(I2C_PORT_IO_EXPANDER_IT8801, IT8801_I2C_ADDR,
-		reg, data);
+	return i2c_read8(I2C_PORT_KB_DISCRETE, KB_DISCRETE_I2C_ADDR_FLAGS, reg,
+			 data);
 }
 
-static int it8801_write(int reg, int data)
+__maybe_unused static int it8801_write(int reg, int data)
 {
-	return i2c_write8(I2C_PORT_IO_EXPANDER_IT8801, IT8801_I2C_ADDR,
-		reg, data);
+	return i2c_write8(I2C_PORT_KB_DISCRETE, KB_DISCRETE_I2C_ADDR_FLAGS, reg,
+			  data);
 }
 
 struct it8801_vendor_id_t {
@@ -38,8 +41,8 @@ struct it8801_vendor_id_t {
 };
 
 static const struct it8801_vendor_id_t it8801_vendor_id_verify[] = {
-	{ 0x12, IT8801_REG_HBVIDR},
-	{ 0x83, IT8801_REG_LBVIDR},
+	{ 0x12, IT8801_REG_HBVIDR },
+	{ 0x83, IT8801_REG_LBVIDR },
 };
 
 static int it8801_check_vendor_id(void)
@@ -60,6 +63,30 @@ static int it8801_check_vendor_id(void)
 	return EC_SUCCESS;
 }
 
+/*
+ * Keyboard and GPIO interrupts are muxed inside the IT8801 chip.
+ * Interrupt enable register controls the individual pins from
+ * triggering this global interrupt hence it is okay that this
+ * pin is enabled all the time.
+ */
+static void it8801_muxed_kbd_gpio_intr_enable(void)
+{
+	static bool intr_enabled;
+
+	/*
+	 * Allow enabling this pin either by Keyboard enable code or
+	 * IOEX init code whichever gets called first.
+	 */
+	if (!intr_enabled) {
+#ifndef CONFIG_ZEPHYR
+		gpio_clear_pending_interrupt(GPIO_KB_DISCRETE_INT);
+#endif
+		gpio_enable_interrupt(GPIO_KB_DISCRETE_INT);
+		intr_enabled = true;
+	}
+}
+
+#ifdef CONFIG_KEYBOARD_DISCRETE
 void keyboard_raw_init(void)
 {
 	int ret;
@@ -106,13 +133,13 @@ void keyboard_raw_task_start(void)
 	keyboard_raw_enable_interrupt(1);
 }
 
-static const uint8_t kso_mapping[] = {
-	0, 1, 20, 3, 4, 5, 6, 17, 18, 16, 15, 11, 12,
+__overridable const uint8_t it8801_kso_mapping[] = { 0,	 1,  20, 3,  4,	 5,  6,
+						     17, 18, 16, 15, 11, 12,
 #ifdef CONFIG_KEYBOARD_KEYPAD
-	13, 14
+						     13, 14
 #endif
 };
-BUILD_ASSERT(ARRAY_SIZE(kso_mapping) == KEYBOARD_COLS_MAX);
+BUILD_ASSERT(ARRAY_SIZE(it8801_kso_mapping) == KEYBOARD_COLS_MAX);
 
 test_mockable void keyboard_raw_drive_column(int col)
 {
@@ -145,18 +172,18 @@ test_mockable void keyboard_raw_drive_column(int col)
 		 * Selected KSO[20, 18:11, 6:3, 1:0] output low,
 		 * all others KSO output high.
 		 */
-		kso_val = kso_mapping[col];
+		kso_val = it8801_kso_mapping[col];
 
 		if (IS_ENABLED(CONFIG_KEYBOARD_COL2_INVERTED)) {
 			/* GPIO23 is inverted. */
 			if (col == IT8801_REG_MASK_SELKSO2) {
 				/* Output high(so selected). */
 				it8801_ioex_set_level(0, 2,
-						IT8801_REG_GPIO23SOV, 1);
+						      IT8801_REG_GPIO23SOV, 1);
 			} else {
 				/* Output low(so not selected). */
 				it8801_ioex_set_level(0, 2,
-						IT8801_REG_GPIO23SOV, 0);
+						      IT8801_REG_GPIO23SOV, 0);
 			}
 		}
 	}
@@ -182,34 +209,45 @@ test_mockable int keyboard_raw_read_rows(void)
 void keyboard_raw_enable_interrupt(int enable)
 {
 	if (enable) {
+		/* Clear pending iterrupts */
 		it8801_write(IT8801_REG_KSIEER, 0xff);
-		gpio_clear_pending_interrupt(GPIO_IT8801_SMB_INT);
-		gpio_enable_interrupt(GPIO_IT8801_SMB_INT);
-	} else {
-		gpio_disable_interrupt(GPIO_IT8801_SMB_INT);
+
+		/* Enable muxed Keyboard & GPIO interrupt */
+		it8801_muxed_kbd_gpio_intr_enable();
 	}
+
+	it8801_write(IT8801_REG_KSIIER, enable ? 0xff : 0x00);
 }
+#endif /* CONFIG_KEYBOARD_DISCRETE */
 
 void io_expander_it8801_interrupt(enum gpio_signal signal)
 {
-	/* Wake the scan task */
-	task_wake(TASK_ID_KEYSCAN);
+	hook_call_deferred(&it8801_ioex_event_handler_data, 0);
 }
 
 static int it8801_ioex_read(int ioex, int reg, int *data)
 {
 	struct ioexpander_config_t *ioex_p = &ioex_config[ioex];
 
-	return i2c_read8(ioex_p->i2c_host_port, ioex_p->i2c_slave_addr,
-			 reg, data);
+	return i2c_read8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, reg,
+			 data);
 }
 
 static int it8801_ioex_write(int ioex, int reg, int data)
 {
 	struct ioexpander_config_t *ioex_p = &ioex_config[ioex];
 
-	return i2c_write8(ioex_p->i2c_host_port, ioex_p->i2c_slave_addr,
-			  reg, data);
+	return i2c_write8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, reg,
+			  data);
+}
+
+static int it8801_ioex_update(int ioex, int reg, int data,
+			      enum mask_update_action action)
+{
+	struct ioexpander_config_t *ioex_p = &ioex_config[ioex];
+
+	return i2c_update8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, reg,
+			   data, action);
 }
 
 static const int it8801_valid_gpio_group[] = {
@@ -219,7 +257,7 @@ static const int it8801_valid_gpio_group[] = {
 };
 
 /* Mutexes */
-static struct mutex ioex_mutex;
+K_MUTEX_DEFINE(ioex_mutex);
 
 static uint8_t it8801_gpio_sov[ARRAY_SIZE(it8801_valid_gpio_group)];
 
@@ -247,6 +285,9 @@ static int it8801_ioex_init(int ioex)
 		it8801_gpio_sov[port] = val;
 	}
 
+	/* Enable muxed Keyboard & GPIO interrupt */
+	it8801_muxed_kbd_gpio_intr_enable();
+
 	return EC_SUCCESS;
 }
 
@@ -299,15 +340,15 @@ static int it8801_ioex_set_level(int ioex, int port, int mask, int value)
 			it8801_gpio_sov[port] &= ~mask;
 
 		rv = it8801_ioex_write(ioex, IT8801_REG_GPIO_SOVR(port),
-						it8801_gpio_sov[port]);
+				       it8801_gpio_sov[port]);
 	}
 	mutex_unlock(&ioex_mutex);
 
 	return rv;
 }
 
-static int it8801_ioex_get_flags_by_mask(int ioex, int port,
-		int mask, int *flags)
+static int it8801_ioex_get_flags_by_mask(int ioex, int port, int mask,
+					 int *flags)
 {
 	int rv, val;
 
@@ -337,8 +378,8 @@ static int it8801_ioex_get_flags_by_mask(int ioex, int port,
 	return EC_SUCCESS;
 }
 
-static int it8801_ioex_set_flags_by_mask(int ioex, int port,
-		int mask, int flags)
+static int it8801_ioex_set_flags_by_mask(int ioex, int port, int mask,
+					 int flags)
 {
 	int rv, val;
 
@@ -347,20 +388,21 @@ static int it8801_ioex_set_flags_by_mask(int ioex, int port,
 
 	if (flags & ~IT8801_SUPPORT_GPIO_FLAGS) {
 		CPRINTS("Flag 0x%08x is not supported at port %d, mask %d",
-					flags, port, mask);
+			flags, port, mask);
 		return EC_ERROR_INVAL;
 	}
 
 	/* GPIO alternate function switching(GPIO[00, 12:15, 20:23]). */
-	it8801_ioex_write(ioex, IT8801_REG_GPIO_CR(port, mask),
-					IT8801_REG_MASK_GPIOAFS_FUNC1);
+	rv = it8801_ioex_write(ioex, IT8801_REG_GPIO_CR(port, mask),
+			       IT8801_REG_MASK_GPIOAFS_FUNC1);
+	if (rv)
+		return rv;
 
 	mutex_lock(&ioex_mutex);
 	rv = it8801_ioex_read(ioex, IT8801_REG_GPIO_CR(port, mask), &val);
-	if (rv) {
-		mutex_unlock(&ioex_mutex);
-		return rv;
-	}
+	if (rv)
+		goto unlock_mutex;
+
 	/* Select open drain 0:push-pull 1:open-drain */
 	if (flags & GPIO_OPEN_DRAIN)
 		val |= IT8801_GPIOIOT;
@@ -376,27 +418,132 @@ static int it8801_ioex_set_flags_by_mask(int ioex, int port,
 			it8801_gpio_sov[port] &= ~mask;
 
 		rv = it8801_ioex_write(ioex, IT8801_REG_GPIO_SOVR(port),
-						it8801_gpio_sov[port]);
-		if (rv) {
-			mutex_unlock(&ioex_mutex);
-			return rv;
-		}
+				       it8801_gpio_sov[port]);
+		if (rv)
+			goto unlock_mutex;
+
 		val |= IT8801_GPIODIR;
-	} else
+	} else {
 		val &= ~IT8801_GPIODIR;
+	}
+
+	/* Set Interrupt Type */
+	if (flags & GPIO_INT_RISING)
+		val |= IT8801_GPIOIOT_INT_RISING;
+	if (flags & GPIO_INT_FALLING)
+		val |= IT8801_GPIOIOT_INT_FALLING;
 
 	rv = it8801_ioex_write(ioex, IT8801_REG_GPIO_CR(port, mask), val);
+
+unlock_mutex:
 	mutex_unlock(&ioex_mutex);
 
 	return rv;
 }
 
+/* Enable the individual GPIO interrupt pins based on the board requirement. */
+static int it8801_ioex_enable_interrupt(int ioex, int port, int mask,
+					int enable)
+{
+	int rv;
+
+	if (ioex_check_is_not_valid(port, mask))
+		return EC_ERROR_INVAL;
+
+	/* Clear pending interrupt */
+	rv = it8801_ioex_update(ioex, IT8801_REG_GPIO_ISR(port), mask,
+				MASK_SET);
+	if (rv)
+		return rv;
+
+	return it8801_ioex_update(ioex, IT8801_REG_GPIO_IER(port), mask,
+				  enable ? MASK_SET : MASK_CLR);
+}
+
+#ifdef CONFIG_ZEPHYR
+static void it8801_ioex_irq(int ioex, int port)
+{
+	/* TODO (b/230008245): Handle interrupts in Zephyr Shim */
+}
+#else
+static void it8801_ioex_irq(int ioex, int port)
+{
+	int rv, data, i;
+	const struct ioex_info *g;
+
+	rv = it8801_ioex_read(ioex, IT8801_REG_GPIO_ISR(port), &data);
+	if (rv || !data)
+		return;
+
+	/* Trigger the intended interrupt from the IOEX IRQ pins */
+	for (i = 0, g = ioex_list; i < ioex_ih_count; i++, g++) {
+		if (ioex == g->ioex && port == g->port && data & g->mask) {
+			ioex_irq_handlers[i](i + IOEX_SIGNAL_START);
+			data &= ~g->mask;
+
+			/* Clear pending interrupt */
+			it8801_ioex_update(ioex, IT8801_REG_GPIO_ISR(port),
+					   g->mask, MASK_SET);
+
+			if (!data)
+				break;
+		}
+	}
+}
+#endif /* CONFIG_ZEPHYR */
+
+static void it8801_ioex_event_handler(void)
+{
+	int data, i;
+
+	/* Gather KSI interrupt status register */
+	if (it8801_read(IT8801_REG_GISR, &data))
+		return;
+
+	/* Wake the keyboard scan task if KSI interrupts are triggered */
+	if (IS_ENABLED(CONFIG_KEYBOARD_DISCRETE) &&
+	    data & IT8801_REG_MASK_GISR_GKSIIS)
+		task_wake(TASK_ID_KEYSCAN);
+
+	/*
+	 * Trigger the GPIO callback functions if the GPIO interrupts are
+	 * triggered.
+	 */
+	if (data & (IT8801_REG_MASK_GISR_GGPIOGXIS)) {
+		for (i = 0; i < CONFIG_IO_EXPANDER_PORT_COUNT; i++) {
+			if (ioex_config[i].drv == &it8801_ioexpander_drv) {
+				/* Interrupt from GPIO port 0 is triggered */
+				if (data & IT8801_REG_MASK_GISR_GGPIOG0IS)
+					it8801_ioex_irq(i, 0);
+				/* Interrupt from GPIO port 1 is triggered */
+				if (data & IT8801_REG_MASK_GISR_GGPIOG1IS)
+					it8801_ioex_irq(i, 1);
+				/* Interrupt from GPIO port 2 is triggered */
+				if (data & IT8801_REG_MASK_GISR_GGPIOG2IS)
+					it8801_ioex_irq(i, 2);
+			}
+		}
+	}
+}
+
+#ifdef CONFIG_IO_EXPANDER_SUPPORT_GET_PORT
+/* Read levels for whole IO expander port */
+static int it8801_ioex_get_port(int ioex, int port, int *val)
+{
+	return it8801_ioex_read(ioex, IT8801_REG_GPIO_IPSR(port), val);
+}
+#endif
+
 const struct ioexpander_drv it8801_ioexpander_drv = {
-	.init              = &it8801_ioex_init,
-	.get_level         = &it8801_ioex_get_level,
-	.set_level         = &it8801_ioex_set_level,
+	.init = &it8801_ioex_init,
+	.get_level = &it8801_ioex_get_level,
+	.set_level = &it8801_ioex_set_level,
 	.get_flags_by_mask = &it8801_ioex_get_flags_by_mask,
 	.set_flags_by_mask = &it8801_ioex_set_flags_by_mask,
+	.enable_interrupt = &it8801_ioex_enable_interrupt,
+#ifdef CONFIG_IO_EXPANDER_SUPPORT_GET_PORT
+	.get_port = &it8801_ioex_get_port,
+#endif
 };
 
 static void dump_register(int reg)
@@ -414,7 +561,7 @@ static void dump_register(int reg)
 		ccprintf("ERR (%d)\n", rv);
 }
 
-static int it8801_dump(int argc, char **argv)
+static int it8801_dump(int argc, const char **argv)
 {
 	dump_register(IT8801_REG_KSIIER);
 	dump_register(IT8801_REG_KSIEER);
@@ -435,13 +582,13 @@ struct it8801_pwm_gpio_map {
 };
 
 const static struct it8801_pwm_gpio_map it8801_pwm_gpio_map[] = {
-	[1] = {.port = 1, .mask = BIT(2), .pushpull_en = BIT(0)},
-	[2] = {.port = 1, .mask = BIT(3), .pushpull_en = BIT(1)},
-	[3] = {.port = 1, .mask = BIT(4), .pushpull_en = BIT(2)},
-	[4] = {.port = 1, .mask = BIT(5), .pushpull_en = BIT(3)},
-	[7] = {.port = 2, .mask = BIT(0), .pushpull_en = BIT(4)},
-	[8] = {.port = 2, .mask = BIT(3), .pushpull_en = BIT(5)},
-	[9] = {.port = 2, .mask = BIT(2), .pushpull_en = BIT(6)},
+	[1] = { .port = 1, .mask = BIT(2), .pushpull_en = BIT(0) },
+	[2] = { .port = 1, .mask = BIT(3), .pushpull_en = BIT(1) },
+	[3] = { .port = 1, .mask = BIT(4), .pushpull_en = BIT(2) },
+	[4] = { .port = 1, .mask = BIT(5), .pushpull_en = BIT(3) },
+	[7] = { .port = 2, .mask = BIT(0), .pushpull_en = BIT(4) },
+	[8] = { .port = 2, .mask = BIT(3), .pushpull_en = BIT(5) },
+	[9] = { .port = 2, .mask = BIT(2), .pushpull_en = BIT(6) },
 };
 
 void it8801_pwm_enable(enum pwm_channel ch, int enabled)
@@ -462,10 +609,10 @@ void it8801_pwm_enable(enum pwm_channel ch, int enabled)
 	 */
 	if (it8801_pwm_channels[ch].index <= 7)
 		it8801_write(IT8801_REG_GPIO_CR(port, mask),
-				0x1 << IT8801_GPIOAFS_SHIFT);
+			     0x1 << IT8801_GPIOAFS_SHIFT);
 	else
 		it8801_write(IT8801_REG_GPIO_CR(port, mask),
-				0x2 << IT8801_GPIOAFS_SHIFT);
+			     0x2 << IT8801_GPIOAFS_SHIFT);
 
 	it8801_read(IT8801_REG_PWMMCR(it8801_pwm_channels[ch].index), &val);
 	val &= (~IT8801_PWMMCR_MCR_MASK);
@@ -481,7 +628,6 @@ void it8801_pwm_enable(enum pwm_channel ch, int enabled)
 	if (enabled)
 		val |= it8801_pwm_gpio_map[index].pushpull_en;
 	it8801_write(IT8801_REG_PWMODDSR, val);
-
 }
 
 int it8801_pwm_get_enabled(enum pwm_channel ch)
@@ -528,15 +674,15 @@ static int it8801_kblight_enable(int enable)
 	return EC_SUCCESS;
 }
 
-static int it8801_kblight_set_brightness(int percent)
+static int it8801_kblight_get_enabled(void)
 {
-	it8801_pwm_set_duty(it8801_kblight_pwm_ch, percent);
-	return EC_SUCCESS;
+	return it8801_pwm_get_enabled(it8801_kblight_pwm_ch);
 }
 
-static int it8801_kblight_get_brightness(void)
+static int it8801_kblight_set_brightness(int percent)
 {
-	return it8801_pwm_get_duty(it8801_kblight_pwm_ch);
+	it8801_pwm_set_duty(it8801_kblight_pwm_ch, percent);
+	return EC_SUCCESS;
 }
 
 static int it8801_kblight_init(void)
@@ -549,8 +695,8 @@ static int it8801_kblight_init(void)
 const struct kblight_drv kblight_it8801 = {
 	.init = it8801_kblight_init,
 	.set = it8801_kblight_set_brightness,
-	.get = it8801_kblight_get_brightness,
 	.enable = it8801_kblight_enable,
+	.get_enabled = it8801_kblight_get_enabled,
 };
 #endif
-#endif  /* CONFIG_IO_EXPANDER_IT8801_PWM */
+#endif /* CONFIG_IO_EXPANDER_IT8801_PWM */
diff --git a/driver/ioexpander/it8801.h b/driver/ioexpander/it8801.h
index 25a82fe617..605c88789b 100644
--- a/driver/ioexpander/it8801.h
+++ b/driver/ioexpander/it8801.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -9,80 +9,86 @@
 #ifndef __CROS_EC_IO_EXPANDER_IT8801_H
 #define __CROS_EC_IO_EXPANDER_IT8801_H
 
-/* I2C slave address(7-bit without R/W) */
-#define IT8801_I2C_ADDR 0x38
+/* I2C address flags (7-bit without R/W) */
+#define IT8801_I2C_ADDR1 0x38
+#define IT8801_I2C_ADDR2 0x39
 
 /* Keyboard Matrix Scan control (KBS) */
-#define IT8801_REG_KSOMCR               0x40
-#define IT8801_REG_MASK_KSOSDIC         BIT(7)
-#define IT8801_REG_MASK_KSE             BIT(6)
-#define IT8801_REG_MASK_AKSOSC          BIT(5)
-#define IT8801_REG_KSIDR                0x41
-#define IT8801_REG_KSIEER               0x42
-#define IT8801_REG_KSIIER               0x43
-#define IT8801_REG_SMBCR                0xfa
-#define IT8801_REG_MASK_ARE             BIT(4)
-#define IT8801_REG_GIECR                0xfb
-#define IT8801_REG_MASK_GKSIIE          BIT(3)
-#define IT8801_REG_GPIO10               0x12
-#define IT8801_REG_GPIO00_KSO19         0x0a
-#define IT8801_REG_GPIO01_KSO18         0x0b
-#define IT8801_REG_GPIO22_KSO21         0x1c
-#define IT8801_REG_GPIO23_KSO20         0x1d
-#define IT8801_REG_MASK_GPIOAFS_PULLUP  BIT(7)
-#define IT8801_REG_MASK_GPIOAFS_FUNC2   BIT(6)
-#define IT8801_REG_MASK_GPIODIR         BIT(5)
-#define IT8801_REG_MASK_GPIOPUE         BIT(0)
-#define IT8801_REG_GPIO23SOV            BIT(3)
-#define IT8801_REG_MASK_SELKSO2         0x02
-#define IT8801_REG_LBVIDR               0xFE
-#define IT8801_REG_HBVIDR               0xFF
-#define IT8801_KSO_COUNT                18
+#define IT8801_REG_KSOMCR 0x40
+#define IT8801_REG_MASK_KSOSDIC BIT(7)
+#define IT8801_REG_MASK_KSE BIT(6)
+#define IT8801_REG_MASK_AKSOSC BIT(5)
+#define IT8801_REG_KSIDR 0x41
+#define IT8801_REG_KSIEER 0x42
+#define IT8801_REG_KSIIER 0x43
+#define IT8801_REG_SMBCR 0xfa
+#define IT8801_REG_MASK_ARE BIT(4)
+#define IT8801_REG_GIECR 0xfb
+#define IT8801_REG_MASK_GKSIIE BIT(3)
+#define IT8801_REG_GPIO10 0x12
+#define IT8801_REG_GPIO00_KSO19 0x0a
+#define IT8801_REG_GPIO01_KSO18 0x0b
+#define IT8801_REG_GPIO22_KSO21 0x1c
+#define IT8801_REG_GPIO23_KSO20 0x1d
+#define IT8801_REG_MASK_GPIOAFS_PULLUP BIT(7)
+#define IT8801_REG_MASK_GPIOAFS_FUNC2 BIT(6)
+#define IT8801_REG_MASK_GPIODIR BIT(5)
+#define IT8801_REG_MASK_GPIOPUE BIT(0)
+#define IT8801_REG_GPIO23SOV BIT(3)
+#define IT8801_REG_MASK_SELKSO2 0x02
+#define IT8801_REG_GISR 0xF9
+#define IT8801_REG_MASK_GISR_GKSIIS BIT(6)
+#define IT8801_REG_MASK_GISR_GGPIOG2IS BIT(2)
+#define IT8801_REG_MASK_GISR_GGPIOG1IS BIT(1)
+#define IT8801_REG_MASK_GISR_GGPIOG0IS BIT(0)
+#define IT8801_REG_MASK_GISR_GGPIOGXIS                                     \
+	(IT8801_REG_MASK_GISR_GGPIOG2IS | IT8801_REG_MASK_GISR_GGPIOG1IS | \
+	 IT8801_REG_MASK_GISR_GGPIOG0IS)
+#define IT8801_REG_LBVIDR 0xFE
+#define IT8801_REG_HBVIDR 0xFF
+#define IT8801_KSO_COUNT 18
 
 /* General Purpose I/O Port (GPIO) */
-#define IT8801_SUPPORT_GPIO_FLAGS (GPIO_OPEN_DRAIN | GPIO_INPUT | \
-		GPIO_OUTPUT | GPIO_LOW | GPIO_HIGH)
+#define IT8801_SUPPORT_GPIO_FLAGS                                            \
+	(GPIO_OPEN_DRAIN | GPIO_INPUT | GPIO_OUTPUT | GPIO_LOW | GPIO_HIGH | \
+	 GPIO_INT_ANY)
 
-#define IT8801_REG_MASK_GPIOAFS_FUNC1   (0x00 << 7)
+#define IT8801_REG_MASK_GPIOAFS_FUNC1 (0x00 << 7)
 
 /* IT8801 only supports GPIO 0/1/2 */
-#define IT8801_VALID_GPIO_G0_MASK       0xD9
-#define IT8801_VALID_GPIO_G1_MASK       0x3F
-#define IT8801_VALID_GPIO_G2_MASK       0x0F
+#define IT8801_VALID_GPIO_G0_MASK 0xD9
+#define IT8801_VALID_GPIO_G1_MASK 0x3F
+#define IT8801_VALID_GPIO_G2_MASK 0x0F
 
+extern __override_proto const uint8_t it8801_kso_mapping[];
 extern const struct ioexpander_drv it8801_ioexpander_drv;
 
 /* GPIO Register map */
 /* Input pin status register */
-#define IT8801_REG_GPIO_IPSR(port)      (0x00 + (port))
+#define IT8801_REG_GPIO_IPSR(port) (0x00 + (port))
 /* Set output value register */
-#define IT8801_REG_GPIO_SOVR(port)      (0x05 + (port))
+#define IT8801_REG_GPIO_SOVR(port) (0x05 + (port))
 /* Control register */
-#define IT8801_REG_GPIO_CR(port, mask)  \
-	(0x0A + (port) * 8 + GPIO_MASK_TO_NUM(mask))
+#define IT8801_REG_GPIO_CR(port, mask) \
+	(0x0A + (port)*8 + GPIO_MASK_TO_NUM(mask))
 /* Interrupt status register */
-#define IT8801_REG_GPIO_ISR(port)       (0x32 + (port))
+#define IT8801_REG_GPIO_ISR(port) (0x32 + (port))
 /* Interrupt enable register */
-#define IT8801_REG_GPIO_IER(port)       (0x37 + (port))
+#define IT8801_REG_GPIO_IER(port) (0x37 + (port))
 
 /* Control register values */
-#define IT8801_GPIOAFS_SHIFT            6  /* bit 6~7 */
+#define IT8801_GPIOAFS_SHIFT 6 /* bit 6~7 */
 
-#define IT8801_GPIODIR                  BIT(5)  /* direction, output=1 */
+#define IT8801_GPIODIR BIT(5) /* direction, output=1 */
+/* input pin */
+#define IT8801_GPIOIOT_INT_RISING BIT(3)
+#define IT8801_GPIOIOT_INT_FALLING BIT(4)
 
-#define IT8801_GPIOIOT_SHIFT            3  /* bit 3~4 */
-#define IT8801_GPIOIOT_MASK             0x3
-#define IT8801_GPIOIOT_INT_LEVEL        0
-#define IT8801_GPIOIOT_INT_RISING       1
-#define IT8801_GPIOIOT_INT_FALLING      2
-#define IT8801_GPIOIOT_INT_EDGE         3  /* = RISING + FALLING */
-#define IT8801_GPIOIOT_OPEN_DRAIN       2
-
-#define IT8801_GPIODIR                  BIT(5)
-#define IT8801_GPIOIOT                  BIT(4)
-#define IT8801_GPIOPOL                  BIT(2)  /* polarity */
-#define IT8801_GPIOPDE                  BIT(1)  /* pull-down enable */
-#define IT8801_GPIOPUE                  BIT(0)  /* pull-up enable */
+#define IT8801_GPIODIR BIT(5)
+#define IT8801_GPIOIOT BIT(4)
+#define IT8801_GPIOPOL BIT(2) /* polarity */
+#define IT8801_GPIOPDE BIT(1) /* pull-down enable */
+#define IT8801_GPIOPUE BIT(0) /* pull-up enable */
 
 /* ISR for IT8801's SMB_INT# */
 void io_expander_it8801_interrupt(enum gpio_signal signal);
@@ -105,18 +111,18 @@ uint16_t it8801_pwm_get_raw_duty(enum pwm_channel ch);
 void it8801_pwm_set_duty(enum pwm_channel ch, int percent);
 int it8801_pwm_get_duty(enum pwm_channel ch);
 
-#define IT8801_REG_PWMODDSR                            0x5F
-#define IT8801_REG_PWMMCR(n)            (0x60 + ((n) - 1) * 8)
-#define IT8801_REG_PWMDCR(n)            (0x64 + ((n) - 1) * 8)
-#define IT8801_REG_PWMPRSL(n)           (0x66 + ((n) - 1) * 8)
-#define IT8801_REG_PWMPRSM(n)           (0x67 + ((n) - 1) * 8)
+#define IT8801_REG_PWMODDSR 0x5F
+#define IT8801_REG_PWMMCR(n) (0x60 + ((n)-1) * 8)
+#define IT8801_REG_PWMDCR(n) (0x64 + ((n)-1) * 8)
+#define IT8801_REG_PWMPRSL(n) (0x66 + ((n)-1) * 8)
+#define IT8801_REG_PWMPRSM(n) (0x67 + ((n)-1) * 8)
 
-#define IT8801_PWMMCR_MCR_MASK          0x3
-#define IT8801_PWMMCR_MCR_OFF           0
-#define IT8801_PWMMCR_MCR_BLINKING      1
-#define IT8801_PWMMCR_MCR_BREATHING     2
-#define IT8801_PWMMCR_MCR_ON            3
+#define IT8801_PWMMCR_MCR_MASK 0x3
+#define IT8801_PWMMCR_MCR_OFF 0
+#define IT8801_PWMMCR_MCR_BLINKING 1
+#define IT8801_PWMMCR_MCR_BREATHING 2
+#define IT8801_PWMMCR_MCR_ON 3
 
-#endif  /* CONFIG_IO_EXPANDER_IT8801_PWM */
+#endif /* CONFIG_IO_EXPANDER_IT8801_PWM */
 
 #endif /* __CROS_EC_KBEXPANDER_IT8801_H */
diff --git a/driver/ioexpander/pca9534.c b/driver/ioexpander/pca9534.c
index d56eb864cb..cd7fc0acf5 100644
--- a/driver/ioexpander/pca9534.c
+++ b/driver/ioexpander/pca9534.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,8 +8,8 @@
 #include "i2c.h"
 #include "pca9534.h"
 
-static int pca9534_pin_read(const int port, const uint16_t addr_flags,
-			    int reg, int pin, int *val)
+static int pca9534_pin_read(const int port, const uint16_t addr_flags, int reg,
+			    int pin, int *val)
 {
 	int ret;
 	ret = i2c_read8(port, addr_flags, reg, val);
@@ -17,8 +17,8 @@ static int pca9534_pin_read(const int port, const uint16_t addr_flags,
 	return ret;
 }
 
-static int pca9534_pin_write(const int port, const uint16_t addr_flags,
-			     int reg, int pin, int val)
+static int pca9534_pin_write(const int port, const uint16_t addr_flags, int reg,
+			     int pin, int val)
 {
 	int ret, v;
 	ret = i2c_read8(port, addr_flags, reg, &v);
@@ -30,23 +30,23 @@ static int pca9534_pin_write(const int port, const uint16_t addr_flags,
 	return i2c_write8(port, addr_flags, reg, v);
 }
 
-int pca9534_get_level(const int port, const uint16_t addr_flags,
-		      int pin, int *level)
+int pca9534_get_level(const int port, const uint16_t addr_flags, int pin,
+		      int *level)
 {
-	return pca9534_pin_read(port, addr_flags,
-				PCA9534_REG_INPUT, pin, level);
+	return pca9534_pin_read(port, addr_flags, PCA9534_REG_INPUT, pin,
+				level);
 }
 
-int pca9534_set_level(const int port, const uint16_t addr_flags,
-		      int pin, int level)
+int pca9534_set_level(const int port, const uint16_t addr_flags, int pin,
+		      int level)
 {
-	return pca9534_pin_write(port, addr_flags,
-				 PCA9534_REG_OUTPUT, pin, level);
+	return pca9534_pin_write(port, addr_flags, PCA9534_REG_OUTPUT, pin,
+				 level);
 }
 
-int pca9534_config_pin(const int port, const uint16_t addr_flags,
-		       int pin, int is_input)
+int pca9534_config_pin(const int port, const uint16_t addr_flags, int pin,
+		       int is_input)
 {
-	return pca9534_pin_write(port, addr_flags,
-				 PCA9534_REG_CONFIG, pin, is_input);
+	return pca9534_pin_write(port, addr_flags, PCA9534_REG_CONFIG, pin,
+				 is_input);
 }
diff --git a/driver/ioexpander/pca9534.h b/driver/ioexpander/pca9534.h
index 0fec577576..67e48191e1 100644
--- a/driver/ioexpander/pca9534.h
+++ b/driver/ioexpander/pca9534.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,12 +8,12 @@
 #ifndef __CROS_EC_IOEXPANDER_PCA9534_H
 #define __CROS_EC_IOEXPANDER_PCA9534_H
 
-#define PCA9534_REG_INPUT  0x0
+#define PCA9534_REG_INPUT 0x0
 #define PCA9534_REG_OUTPUT 0x1
 #define PCA9534_REG_CONFIG 0x3
 
 #define PCA9534_OUTPUT 0
-#define PCA9534_INPUT  1
+#define PCA9534_INPUT 1
 
 /*
  * Get input level. Note that this reflects the actual level on the
@@ -26,8 +26,8 @@
  *
  * @return EC_SUCCESS, or EC_ERROR_* on error.
  */
-int pca9534_get_level(const int port, const uint16_t addr_flags,
-		      int pin, int *level);
+int pca9534_get_level(const int port, const uint16_t addr_flags, int pin,
+		      int *level);
 
 /*
  * Set output level. This function has no effect if the pin is
@@ -40,8 +40,8 @@ int pca9534_get_level(const int port, const uint16_t addr_flags,
  *
  * @return EC_SUCCESS, or EC_ERROR_* on error.
  */
-int pca9534_set_level(const int port, const uint16_t addr_flags,
-		      int pin, int level);
+int pca9534_set_level(const int port, const uint16_t addr_flags, int pin,
+		      int level);
 
 /*
  * Config a pin as input or output.
@@ -53,7 +53,7 @@ int pca9534_set_level(const int port, const uint16_t addr_flags,
  *
  * @return EC_SUCCESS, or EC_ERROR_* on error.
  */
-int pca9534_config_pin(const int port, const uint16_t addr_flags,
-		       int pin, int is_input);
+int pca9534_config_pin(const int port, const uint16_t addr_flags, int pin,
+		       int is_input);
 
-#endif  /* __CROS_EC_IOEXPANDER_PCA9534_H */
+#endif /* __CROS_EC_IOEXPANDER_PCA9534_H */
diff --git a/driver/ioexpander/pca9555.h b/driver/ioexpander/pca9555.h
index 273f898821..ea29c91656 100644
--- a/driver/ioexpander/pca9555.h
+++ b/driver/ioexpander/pca9555.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,33 +10,31 @@
 
 #include "i2c.h"
 
-#define PCA9555_CMD_INPUT_PORT_0		0
-#define PCA9555_CMD_INPUT_PORT_1		1
-#define PCA9555_CMD_OUTPUT_PORT_0		2
-#define PCA9555_CMD_OUTPUT_PORT_1		3
-#define PCA9555_CMD_POLARITY_INVERSION_PORT_0	4
-#define PCA9555_CMD_POLARITY_INVERSION_PORT_1	5
-#define PCA9555_CMD_CONFIGURATION_PORT_0	6
-#define PCA9555_CMD_CONFIGURATION_PORT_1	7
+#define PCA9555_CMD_INPUT_PORT_0 0
+#define PCA9555_CMD_INPUT_PORT_1 1
+#define PCA9555_CMD_OUTPUT_PORT_0 2
+#define PCA9555_CMD_OUTPUT_PORT_1 3
+#define PCA9555_CMD_POLARITY_INVERSION_PORT_0 4
+#define PCA9555_CMD_POLARITY_INVERSION_PORT_1 5
+#define PCA9555_CMD_CONFIGURATION_PORT_0 6
+#define PCA9555_CMD_CONFIGURATION_PORT_1 7
 
-#define PCA9555_IO_0	BIT(0)
-#define PCA9555_IO_1	BIT(1)
-#define PCA9555_IO_2	BIT(2)
-#define PCA9555_IO_3	BIT(3)
-#define PCA9555_IO_4	BIT(4)
-#define PCA9555_IO_5	BIT(5)
-#define PCA9555_IO_6	BIT(6)
-#define PCA9555_IO_7	BIT(7)
+#define PCA9555_IO_0 BIT(0)
+#define PCA9555_IO_1 BIT(1)
+#define PCA9555_IO_2 BIT(2)
+#define PCA9555_IO_3 BIT(3)
+#define PCA9555_IO_4 BIT(4)
+#define PCA9555_IO_5 BIT(5)
+#define PCA9555_IO_6 BIT(6)
+#define PCA9555_IO_7 BIT(7)
 
-static inline int pca9555_read(const int port,
-			       const uint16_t i2c_addr_flags,
+static inline int pca9555_read(const int port, const uint16_t i2c_addr_flags,
 			       int reg, int *data_ptr)
 {
 	return i2c_read8(port, i2c_addr_flags, reg, data_ptr);
 }
 
-static inline int pca9555_write(const int port,
-				const uint16_t i2c_addr_flags,
+static inline int pca9555_write(const int port, const uint16_t i2c_addr_flags,
 				int reg, int data)
 {
 	return i2c_write8(port, i2c_addr_flags, reg, data);
diff --git a/driver/ioexpander/pca9675.c b/driver/ioexpander/pca9675.c
new file mode 100644
index 0000000000..74faab8722
--- /dev/null
+++ b/driver/ioexpander/pca9675.c
@@ -0,0 +1,140 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * NXP PCA9675PW I/O Port expander driver source
+ */
+
+#include "gpio.h"
+#include "i2c.h"
+#include "ioexpander.h"
+#include "pca9675.h"
+
+struct pca9675_ioexpander {
+	/* I/O port direction (1 = input, 0 = output) */
+	uint16_t io_direction;
+	uint16_t cache_out_pins;
+};
+
+static struct pca9675_ioexpander pca9675_iox[CONFIG_IO_EXPANDER_PORT_COUNT];
+
+static int pca9675_read16(int ioex, uint16_t *data)
+{
+	return i2c_xfer(ioex_config[ioex].i2c_host_port,
+			ioex_config[ioex].i2c_addr_flags, NULL, 0,
+			(uint8_t *)data, 2);
+}
+
+static int pca9675_write16(int ioex, uint16_t data)
+{
+	/*
+	 * PCA9675 is Quasi-bidirectional I/O architecture hence
+	 * append the direction (1 = input, 0 = output) to prevent
+	 * overwriting I/O pins inadvertently.
+	 */
+	data |= pca9675_iox[ioex].io_direction;
+
+	return i2c_xfer(ioex_config[ioex].i2c_host_port,
+			ioex_config[ioex].i2c_addr_flags, (uint8_t *)&data, 2,
+			NULL, 0);
+}
+
+static int pca9675_reset(int ioex)
+{
+	uint8_t reset = PCA9675_RESET_SEQ_DATA;
+
+	return i2c_xfer(ioex_config[ioex].i2c_host_port, 0, &reset, 1, NULL, 0);
+}
+
+static int pca9675_get_flags_by_mask(int ioex, int port, int mask, int *flags)
+{
+	*flags = mask & pca9675_iox[ioex].io_direction ? GPIO_INPUT :
+							 GPIO_OUTPUT;
+
+	return EC_SUCCESS;
+}
+
+static int pca9675_get_level(int ioex, int port, int mask, int *val)
+{
+	int rv = EC_SUCCESS;
+	uint16_t data_read;
+
+	/* Read from IO-expander only if the pin is input */
+	if (pca9675_iox[ioex].io_direction & mask) {
+		rv = pca9675_read16(ioex, &data_read);
+		if (!rv)
+			*val = !!(data_read & mask);
+	} else {
+		*val = !!(pca9675_iox[ioex].cache_out_pins & mask);
+	}
+
+	return rv;
+}
+
+static int pca9675_set_level(int ioex, int port, int mask, int val)
+{
+	/* Update the output pins */
+	if (val)
+		pca9675_iox[ioex].cache_out_pins |= mask;
+	else
+		pca9675_iox[ioex].cache_out_pins &= ~mask;
+
+	return pca9675_write16(ioex, pca9675_iox[ioex].cache_out_pins);
+}
+
+static int pca9675_set_flags_by_mask(int ioex, int port, int mask, int flags)
+{
+	int rv = EC_SUCCESS;
+
+	/* Initialize the I/O directions */
+	if (flags & GPIO_INPUT) {
+		pca9675_iox[ioex].io_direction |= mask;
+	} else {
+		pca9675_iox[ioex].io_direction &= ~mask;
+
+		/* Initialize the pin */
+		rv = pca9675_set_level(ioex, port, mask, flags & GPIO_HIGH);
+	}
+
+	return rv;
+}
+
+static int pca9675_enable_interrupt(int ioex, int port, int mask, int enable)
+{
+	/*
+	 * Nothing to do as an interrupt is generated by any rising or
+	 * falling edge of the port inputs.
+	 */
+	return EC_SUCCESS;
+}
+
+int pca9675_init(int ioex)
+{
+	pca9675_iox[ioex].io_direction = PCA9675_DEFAULT_IO_DIRECTION;
+	pca9675_iox[ioex].cache_out_pins = 0;
+
+	/* Set pca9675 to Power-on reset */
+	return pca9675_reset(ioex);
+}
+
+#ifdef CONFIG_IO_EXPANDER_SUPPORT_GET_PORT
+
+/* Read levels for whole IO expander port */
+static int pca9675_get_port(int ioex, int port, int *val)
+{
+	return pca9675_read16(ioex, (uint16_t *)val);
+}
+
+#endif
+
+const struct ioexpander_drv pca9675_ioexpander_drv = {
+	.init = &pca9675_init,
+	.get_level = &pca9675_get_level,
+	.set_level = &pca9675_set_level,
+	.get_flags_by_mask = &pca9675_get_flags_by_mask,
+	.set_flags_by_mask = &pca9675_set_flags_by_mask,
+	.enable_interrupt = &pca9675_enable_interrupt,
+#ifdef CONFIG_IO_EXPANDER_SUPPORT_GET_PORT
+	.get_port = &pca9675_get_port,
+#endif
+};
diff --git a/driver/ioexpander/pca9675.h b/driver/ioexpander/pca9675.h
new file mode 100644
index 0000000000..6b71ffa023
--- /dev/null
+++ b/driver/ioexpander/pca9675.h
@@ -0,0 +1,39 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * NXP PCA9675PW I/O Port expander driver header
+ */
+
+#ifndef __CROS_EC_IOEXPANDER_PCA9675_H
+#define __CROS_EC_IOEXPANDER_PCA9675_H
+
+/* PCA9675 IO pins that can be referenced in gpio.inc */
+enum pca9675_io_pins {
+	PCA9675_IO_P00,
+	PCA9675_IO_P01,
+	PCA9675_IO_P02,
+	PCA9675_IO_P03,
+	PCA9675_IO_P04,
+	PCA9675_IO_P05,
+	PCA9675_IO_P06,
+	PCA9675_IO_P07,
+	PCA9675_IO_P10,
+	PCA9675_IO_P11,
+	PCA9675_IO_P12,
+	PCA9675_IO_P13,
+	PCA9675_IO_P14,
+	PCA9675_IO_P15,
+	PCA9675_IO_P16,
+	PCA9675_IO_P17,
+};
+
+/* Write 06 to address 00 to reset the PCA9675 to back to power up state */
+#define PCA9675_RESET_SEQ_DATA 0x06
+
+/* Default I/O directons of PCA9675 is input */
+#define PCA9675_DEFAULT_IO_DIRECTION 0xffff
+
+extern const struct ioexpander_drv pca9675_ioexpander_drv;
+
+#endif /* __CROS_EC_IOEXPANDER_PCA9675_H */
diff --git a/driver/ioexpander/pcal6408.c b/driver/ioexpander/pcal6408.c
index 27fbacca70..cec5e5902e 100644
--- a/driver/ioexpander/pcal6408.c
+++ b/driver/ioexpander/pcal6408.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -6,31 +6,34 @@
  */
 #include "common.h"
 #include "console.h"
-#include "math_util.h"
 #include "gpio.h"
 #include "i2c.h"
 #include "ioexpander.h"
+#include "math_util.h"
 #include "pcal6408.h"
 
-#define CPRINTF(format, args...) cprintf(CC_GPIO, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_GPIO, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
+
+#ifdef CONFIG_IO_EXPANDER_SUPPORT_GET_PORT
+#error "This driver doesn't support get_port function"
+#endif
 
 /*
  * Store interrupt mask registers locally. In this way,
  * we don't have to read it via i2c transaction every time.
  * Default value of interrupt mask register is 0xff.
  */
-uint8_t pcal6408_int_mask[] = {
-	[0 ... (CONFIG_IO_EXPANDER_PORT_COUNT - 1)] =  0xff };
-
+uint8_t pcal6408_int_mask[] = { [0 ...(CONFIG_IO_EXPANDER_PORT_COUNT - 1)] =
+					0xff };
 
 static int pcal6408_read(int ioex, int reg, int *data)
 {
 	int rv;
 	struct ioexpander_config_t *ioex_p = &ioex_config[ioex];
 
-	rv = i2c_read8(ioex_p->i2c_host_port, ioex_p->i2c_slave_addr,
-			reg, data);
+	rv = i2c_read8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, reg,
+		       data);
 
 	return rv;
 }
@@ -40,8 +43,8 @@ static int pcal6408_write(int ioex, int reg, int data)
 	int rv;
 	struct ioexpander_config_t *ioex_p = &ioex_config[ioex];
 
-	rv = i2c_write8(ioex_p->i2c_host_port, ioex_p->i2c_slave_addr,
-			reg, data);
+	rv = i2c_write8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, reg,
+			data);
 
 	return rv;
 }
@@ -52,8 +55,7 @@ static int pcal6408_ioex_check_is_valid(int port, int mask)
 		return EC_ERROR_INVAL;
 
 	if (mask & ~PCAL6408_VALID_GPIO_MASK) {
-		CPRINTF("GPIO%02d is not support in PCAL6408\n",
-						__fls(mask));
+		CPRINTF("GPIO%02d is not support in PCAL6408\n", __fls(mask));
 		return EC_ERROR_INVAL;
 	}
 
@@ -106,7 +108,7 @@ static int pcal6408_ioex_set_level(int ioex, int port, int mask, int value)
 }
 
 static int pcal6408_ioex_get_flags_by_mask(int ioex, int port, int mask,
-					int *flags)
+					   int *flags)
 {
 	int rv, val;
 
@@ -167,7 +169,7 @@ static int pcal6408_ioex_get_flags_by_mask(int ioex, int port, int mask,
 }
 
 static int pcal6408_ioex_set_flags_by_mask(int ioex, int port, int mask,
-					int flags)
+					   int flags)
 {
 	int rv, val;
 
@@ -176,14 +178,13 @@ static int pcal6408_ioex_set_flags_by_mask(int ioex, int port, int mask,
 		return rv;
 
 	if (((flags & GPIO_INT_BOTH) == GPIO_INT_RISING) ||
-		((flags & GPIO_INT_BOTH) == GPIO_INT_FALLING)) {
+	    ((flags & GPIO_INT_BOTH) == GPIO_INT_FALLING)) {
 		CPRINTF("PCAL6408 only support GPIO_INT_BOTH.\n");
 		return EC_ERROR_INVAL;
 	}
 
-
 	if ((flags & (GPIO_INT_F_RISING | GPIO_INT_F_FALLING)) &&
-		!(flags & GPIO_INPUT)) {
+	    !(flags & GPIO_INPUT)) {
 		CPRINTF("Interrupt pin must be GPIO_INPUT.\n");
 		return EC_ERROR_INVAL;
 	}
@@ -265,7 +266,7 @@ static int pcal6408_ioex_set_flags_by_mask(int ioex, int port, int mask,
 }
 
 static int pcal6408_ioex_enable_interrupt(int ioex, int port, int mask,
-					int enable)
+					  int enable)
 {
 	int rv, val;
 
@@ -298,7 +299,7 @@ static int pcal6408_ioex_enable_interrupt(int ioex, int port, int mask,
 		pcal6408_int_mask[ioex] |= mask;
 
 	rv = pcal6408_write(ioex, PCAL6408_REG_INT_MASK,
-			pcal6408_int_mask[ioex]);
+			    pcal6408_int_mask[ioex]);
 
 	return rv;
 }
@@ -316,8 +317,8 @@ int pcal6408_ioex_event_handler(int ioex)
 	 * Read input port register will clear the interrupt,
 	 * read status register will not.
 	 */
-	rv = i2c_read8(ioex_p->i2c_host_port, ioex_p->i2c_slave_addr,
-				PCAL6408_REG_INT_STATUS, &int_status);
+	rv = i2c_read8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags,
+		       PCAL6408_REG_INT_STATUS, &int_status);
 	if (rv != EC_SUCCESS)
 		return rv;
 
@@ -331,10 +332,8 @@ int pcal6408_ioex_event_handler(int ioex)
 		return EC_SUCCESS;
 
 	for (i = 0, g = ioex_list; i < ioex_ih_count; i++, g++) {
-
-		if (ioex == g->ioex && 0 == g->port &&
-					(int_status & g->mask)) {
-			ioex_irq_handlers[i](i);
+		if (ioex == g->ioex && 0 == g->port && (int_status & g->mask)) {
+			ioex_irq_handlers[i](i + IOEX_SIGNAL_START);
 			int_status &= ~g->mask;
 			if (!int_status)
 				break;
@@ -345,10 +344,10 @@ int pcal6408_ioex_event_handler(int ioex)
 }
 
 const struct ioexpander_drv pcal6408_ioexpander_drv = {
-	.init			= &pcal6408_ioex_init,
-	.get_level		= &pcal6408_ioex_get_level,
-	.set_level		= &pcal6408_ioex_set_level,
-	.get_flags_by_mask	= &pcal6408_ioex_get_flags_by_mask,
-	.set_flags_by_mask	= &pcal6408_ioex_set_flags_by_mask,
-	.enable_interrupt	= &pcal6408_ioex_enable_interrupt,
+	.init = &pcal6408_ioex_init,
+	.get_level = &pcal6408_ioex_get_level,
+	.set_level = &pcal6408_ioex_set_level,
+	.get_flags_by_mask = &pcal6408_ioex_get_flags_by_mask,
+	.set_flags_by_mask = &pcal6408_ioex_set_flags_by_mask,
+	.enable_interrupt = &pcal6408_ioex_enable_interrupt,
 };
diff --git a/driver/ioexpander/pcal6408.h b/driver/ioexpander/pcal6408.h
index fc9969aab1..3bedf5bdc4 100644
--- a/driver/ioexpander/pcal6408.h
+++ b/driver/ioexpander/pcal6408.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,28 +8,28 @@
 #ifndef __CROS_EC_IOEXPANDER_PCAL6408_H
 #define __CROS_EC_IOEXPANDER_PCAL6408_H
 
-#define PCAL6408_I2C_ADDR0		0x20
-#define PCAL6408_I2C_ADDR1		0x21
+#define PCAL6408_I2C_ADDR0 0x20
+#define PCAL6408_I2C_ADDR1 0x21
 
-#define PCAL6408_REG_INPUT		0x00
-#define PCAL6408_REG_OUTPUT		0x01
-#define PCAL6408_REG_POLARITY_INVERSION	0x02
-#define PCAL6408_REG_CONFIG		0x03
-#define PCAL6408_REG_OUT_STRENGTH0	0x40
-#define PCAL6408_REG_OUT_STRENGTH1	0x41
-#define PCAL6408_REG_INPUT_LATCH	0x42
-#define PCAL6408_REG_PULL_ENABLE	0x43
-#define PCAL6408_REG_PULL_UP_DOWN	0x44
-#define PCAL6408_REG_INT_MASK		0x45
-#define PCAL6408_REG_INT_STATUS		0x46
-#define PCAL6408_REG_OUT_CONFIG		0x4f
+#define PCAL6408_REG_INPUT 0x00
+#define PCAL6408_REG_OUTPUT 0x01
+#define PCAL6408_REG_POLARITY_INVERSION 0x02
+#define PCAL6408_REG_CONFIG 0x03
+#define PCAL6408_REG_OUT_STRENGTH0 0x40
+#define PCAL6408_REG_OUT_STRENGTH1 0x41
+#define PCAL6408_REG_INPUT_LATCH 0x42
+#define PCAL6408_REG_PULL_ENABLE 0x43
+#define PCAL6408_REG_PULL_UP_DOWN 0x44
+#define PCAL6408_REG_INT_MASK 0x45
+#define PCAL6408_REG_INT_STATUS 0x46
+#define PCAL6408_REG_OUT_CONFIG 0x4f
 
-#define PCAL6408_VALID_GPIO_MASK	0xff
+#define PCAL6408_VALID_GPIO_MASK 0xff
 
-#define PCAL6408_OUTPUT			0
-#define PCAL6408_INPUT			1
+#define PCAL6408_OUTPUT 0
+#define PCAL6408_INPUT 1
 
-#define PCAL6408_OUT_CONFIG_OPEN_DRAIN	0x01
+#define PCAL6408_OUT_CONFIG_OPEN_DRAIN 0x01
 
 /*
  * Check which IO's interrupt event is triggered. If any, call its
@@ -39,4 +39,4 @@ int pcal6408_ioex_event_handler(int ioex);
 
 extern const struct ioexpander_drv pcal6408_ioexpander_drv;
 
-#endif  /* __CROS_EC_IOEXPANDER_PCAL6408_H */
+#endif /* __CROS_EC_IOEXPANDER_PCAL6408_H */
diff --git a/driver/ioexpander/tca64xxa.c b/driver/ioexpander/tca64xxa.c
new file mode 100644
index 0000000000..b1b0d2dd09
--- /dev/null
+++ b/driver/ioexpander/tca64xxa.c
@@ -0,0 +1,224 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "gpio.h"
+#include "i2c.h"
+#include "ioexpander.h"
+#include "system.h"
+#include "tca64xxa.h"
+
+/*
+ * This chip series contain registers in the same order.
+ * Difference between models is only amount of registers and
+ * value of which you must multiply to access specific register.
+ * For 16 bit series, registers are 2 byte away, so to access TCA64XXA_REG_CONF
+ * you must multiply it by 2. For 24 bit, they are away by 4 bytes so you
+ * must multiply them by 4. Flags value contains information which version
+ * of chip is used.
+ */
+#define TCA64XXA_PORT_ID(port, reg, flags)                                \
+	((((flags)&TCA64XXA_FLAG_VER_MASK) >> TCA64XXA_FLAG_VER_OFFSET) * \
+		 (reg) +                                                  \
+	 (port))
+
+static int tca64xxa_write_byte(int ioex, int port, int reg, uint8_t val)
+{
+	const struct ioexpander_config_t *ioex_p = &ioex_config[ioex];
+	const int reg_addr = TCA64XXA_PORT_ID(
+		port, reg,
+		(ioex_p->flags & IOEX_FLAGS_TCA64XXA_FLAG_VER_TCA6416A) ? 2 :
+									  4);
+
+	return i2c_write8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags,
+			  reg_addr, val);
+}
+
+static int tca64xxa_read_byte(int ioex, int port, int reg, int *val)
+{
+	const struct ioexpander_config_t *ioex_p = &ioex_config[ioex];
+	const int reg_addr = TCA64XXA_PORT_ID(
+		port, reg,
+		(ioex_p->flags & IOEX_FLAGS_TCA64XXA_FLAG_VER_TCA6416A) ? 2 :
+									  4);
+
+	return i2c_read8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags,
+			 reg_addr, val);
+}
+
+/* Restore default values in registers */
+static int tca64xxa_reset(int ioex, int portsCount)
+{
+	int port;
+	int ret;
+
+	/*
+	 * On servo_v4p1, reset pin is pulled up and it results in values
+	 * not being restored to default ones after software reboot.
+	 * This loop sets default values (from specification) to all registers.
+	 */
+	for (port = 0; port < portsCount; port++) {
+		ret = tca64xxa_write_byte(ioex, port, TCA64XXA_REG_OUTPUT,
+					  TCA64XXA_DEFAULT_OUTPUT);
+		if (ret)
+			return ret;
+
+		ret = tca64xxa_write_byte(ioex, port, TCA64XXA_REG_POLARITY_INV,
+					  TCA64XXA_DEFAULT_POLARITY_INV);
+		if (ret)
+			return ret;
+
+		ret = tca64xxa_write_byte(ioex, port, TCA64XXA_REG_CONF,
+					  TCA64XXA_DEFAULT_CONF);
+		if (ret)
+			return ret;
+	}
+
+	return EC_SUCCESS;
+}
+
+/* Initialize IO expander chip/driver */
+static int tca64xxa_init(int ioex)
+{
+	const struct ioexpander_config_t *ioex_p = &ioex_config[ioex];
+	int portsCount;
+
+	if (ioex_p->flags & IOEX_FLAGS_TCA64XXA_FLAG_VER_TCA6416A)
+		portsCount = 2;
+	else if (ioex_p->flags & IOEX_FLAGS_TCA64XXA_FLAG_VER_TCA6424A)
+		portsCount = 3;
+	else
+		return EC_ERROR_UNIMPLEMENTED;
+
+	if (!system_jumped_late())
+		return tca64xxa_reset(ioex, portsCount);
+
+	return EC_SUCCESS;
+}
+
+/* Get the current level of the IOEX pin */
+static int tca64xxa_get_level(int ioex, int port, int mask, int *val)
+{
+	int buf;
+	int ret;
+
+	ret = tca64xxa_read_byte(ioex, port, TCA64XXA_REG_INPUT, &buf);
+	*val = !!(buf & mask);
+
+	return ret;
+}
+
+/* Set the level of the IOEX pin */
+static int tca64xxa_set_level(int ioex, int port, int mask, int val)
+{
+	int ret;
+	int v;
+
+	ret = tca64xxa_read_byte(ioex, port, TCA64XXA_REG_OUTPUT, &v);
+	if (ret)
+		return ret;
+
+	if (val)
+		v |= mask;
+	else
+		v &= ~mask;
+
+	return tca64xxa_write_byte(ioex, port, TCA64XXA_REG_OUTPUT, v);
+}
+
+/* Get flags for the IOEX pin */
+static int tca64xxa_get_flags_by_mask(int ioex, int port, int mask, int *flags)
+{
+	int ret;
+	int v;
+
+	ret = tca64xxa_read_byte(ioex, port, TCA64XXA_REG_CONF, &v);
+	if (ret)
+		return ret;
+
+	*flags = 0;
+	if (v & mask) {
+		*flags |= GPIO_INPUT;
+	} else {
+		*flags |= GPIO_OUTPUT;
+
+		ret = tca64xxa_read_byte(ioex, port, TCA64XXA_REG_OUTPUT, &v);
+		if (ret)
+			return ret;
+
+		if (v & mask)
+			*flags |= GPIO_HIGH;
+		else
+			*flags |= GPIO_LOW;
+	}
+
+	return EC_SUCCESS;
+}
+
+/* Set flags for the IOEX pin */
+static int tca64xxa_set_flags_by_mask(int ioex, int port, int mask, int flags)
+{
+	int ret;
+	int v;
+
+	/* Output value */
+	if (flags & GPIO_OUTPUT) {
+		ret = tca64xxa_read_byte(ioex, port, TCA64XXA_REG_OUTPUT, &v);
+		if (ret)
+			return ret;
+
+		if (flags & GPIO_LOW)
+			v &= ~mask;
+		else if (flags & GPIO_HIGH)
+			v |= mask;
+		else
+			return EC_ERROR_INVAL;
+
+		ret = tca64xxa_write_byte(ioex, port, TCA64XXA_REG_OUTPUT, v);
+		if (ret)
+			return ret;
+	}
+
+	/* Configuration */
+	ret = tca64xxa_read_byte(ioex, port, TCA64XXA_REG_CONF, &v);
+	if (ret)
+		return ret;
+
+	if (flags & GPIO_INPUT)
+		v |= mask;
+	else if (flags & GPIO_OUTPUT)
+		v &= ~mask;
+	else
+		return EC_ERROR_INVAL;
+
+	ret = tca64xxa_write_byte(ioex, port, TCA64XXA_REG_CONF, v);
+	if (ret)
+		return ret;
+
+	return EC_SUCCESS;
+}
+
+#ifdef CONFIG_IO_EXPANDER_SUPPORT_GET_PORT
+
+/* Read levels for whole IO expander port */
+static int tca64xxa_get_port(int ioex, int port, int *val)
+{
+	return tca64xxa_read_byte(ioex, port, TCA64XXA_REG_INPUT, val);
+}
+
+#endif
+
+/* Driver structure */
+const struct ioexpander_drv tca64xxa_ioexpander_drv = {
+	.init = tca64xxa_init,
+	.get_level = tca64xxa_get_level,
+	.set_level = tca64xxa_set_level,
+	.get_flags_by_mask = tca64xxa_get_flags_by_mask,
+	.set_flags_by_mask = tca64xxa_set_flags_by_mask,
+	.enable_interrupt = NULL,
+#ifdef CONFIG_IO_EXPANDER_SUPPORT_GET_PORT
+	.get_port = tca64xxa_get_port,
+#endif
+};
diff --git a/driver/ioexpander/tca64xxa.h b/driver/ioexpander/tca64xxa.h
new file mode 100644
index 0000000000..af095d7ea9
--- /dev/null
+++ b/driver/ioexpander/tca64xxa.h
@@ -0,0 +1,28 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_DRIVER_IOEXPANDER_TCA64XXA_H_
+#define __CROS_EC_DRIVER_IOEXPANDER_TCA64XXA_H_
+
+/* io-expander driver specific flag bit for tca6416a */
+#define IOEX_FLAGS_TCA64XXA_FLAG_VER_TCA6416A IOEX_FLAGS_CUSTOM_BIT(24)
+/* io-expander driver specific flag bit for tca6424a */
+#define IOEX_FLAGS_TCA64XXA_FLAG_VER_TCA6424A IOEX_FLAGS_CUSTOM_BIT(25)
+
+#define TCA64XXA_FLAG_VER_MASK GENMASK(2, 1)
+#define TCA64XXA_FLAG_VER_OFFSET 0
+
+#define TCA64XXA_REG_INPUT 0
+#define TCA64XXA_REG_OUTPUT 1
+#define TCA64XXA_REG_POLARITY_INV 2
+#define TCA64XXA_REG_CONF 3
+
+#define TCA64XXA_DEFAULT_OUTPUT 0xFF
+#define TCA64XXA_DEFAULT_POLARITY_INV 0x00
+#define TCA64XXA_DEFAULT_CONF 0xFF
+
+extern const struct ioexpander_drv tca64xxa_ioexpander_drv;
+
+#endif /* __CROS_EC_DRIVER_IOEXPANDER_TCA64XXA_H_ */
diff --git a/driver/led/aw20198.c b/driver/led/aw20198.c
new file mode 100644
index 0000000000..eca596d62e
--- /dev/null
+++ b/driver/led/aw20198.c
@@ -0,0 +1,178 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "aw20198.h"
+#include "common.h"
+#include "console.h"
+#include "gpio.h"
+#include "i2c.h"
+#include "rgb_keyboard.h"
+#include "stddef.h"
+#include "timer.h"
+
+#include <string.h>
+
+#define CPRINTF(fmt, args...) cprintf(CC_RGBKBD, "AW20198: " fmt, ##args)
+#define CPRINTS(fmt, args...) cprints(CC_RGBKBD, "AW20198: " fmt, ##args)
+
+#define BUF_SIZE (SIZE_OF_RGB * AW20198_GRID_SIZE)
+
+static int aw20198_read(struct rgbkbd *ctx, uint8_t addr, uint8_t *value)
+{
+	return i2c_xfer(ctx->cfg->i2c, AW20198_I2C_ADDR_FLAG, &addr,
+			sizeof(addr), value, sizeof(*value));
+}
+
+static int aw20198_write(struct rgbkbd *ctx, uint8_t addr, uint8_t value)
+{
+	uint8_t buf[2] = {
+		[0] = addr,
+		[1] = value,
+	};
+
+	return i2c_xfer(ctx->cfg->i2c, AW20198_I2C_ADDR_FLAG, buf, sizeof(buf),
+			NULL, 0);
+}
+
+static int aw20198_set_page(struct rgbkbd *ctx, uint8_t page)
+{
+	return aw20198_write(ctx, AW20198_REG_PAGE, page);
+}
+
+static int aw20198_get_config(struct rgbkbd *ctx, uint8_t addr, uint8_t *value)
+{
+	int rv = aw20198_set_page(ctx, AW20198_PAGE_FUNC);
+	if (rv) {
+		return rv;
+	}
+
+	return aw20198_read(ctx, addr, value);
+}
+
+static int aw20198_set_config(struct rgbkbd *ctx, uint8_t addr, uint8_t value)
+{
+	int rv = aw20198_set_page(ctx, AW20198_PAGE_FUNC);
+	if (rv) {
+		return rv;
+	}
+
+	return aw20198_write(ctx, addr, value);
+}
+
+static int aw20198_reset(struct rgbkbd *ctx)
+{
+	return aw20198_set_config(ctx, AW20198_REG_RSTN, AW20198_RESET_MAGIC);
+}
+
+static int aw20198_enable(struct rgbkbd *ctx, bool enable)
+{
+	uint8_t cfg;
+	int rv;
+
+	rv = aw20198_get_config(ctx, AW20198_REG_GCR, &cfg);
+	if (rv) {
+		return rv;
+	}
+
+	WRITE_BIT(cfg, 0, enable);
+	return aw20198_write(ctx, AW20198_REG_GCR, cfg);
+}
+
+static int aw20198_set_color(struct rgbkbd *ctx, uint8_t offset,
+			     struct rgb_s *color, uint8_t len)
+{
+	uint8_t buf[sizeof(offset) + BUF_SIZE];
+	const int frame_len = len * SIZE_OF_RGB + sizeof(offset);
+	const int frame_offset = offset * SIZE_OF_RGB;
+	int i, rv;
+
+	if (frame_offset + frame_len > sizeof(buf)) {
+		return EC_ERROR_OVERFLOW;
+	}
+
+	rv = aw20198_set_page(ctx, AW20198_PAGE_PWM);
+	if (rv) {
+		return rv;
+	}
+
+	buf[0] = offset * SIZE_OF_RGB;
+	for (i = 0; i < len; i++) {
+		buf[i * SIZE_OF_RGB + 1] = color[i].r;
+		buf[i * SIZE_OF_RGB + 2] = color[i].g;
+		buf[i * SIZE_OF_RGB + 3] = color[i].b;
+	}
+
+	return i2c_xfer(ctx->cfg->i2c, AW20198_I2C_ADDR_FLAG, buf, frame_len,
+			NULL, 0);
+}
+
+static int aw20198_set_scale(struct rgbkbd *ctx, uint8_t offset,
+			     struct rgb_s scale, uint8_t len)
+{
+	uint8_t buf[sizeof(offset) + BUF_SIZE];
+	const int frame_len = len * SIZE_OF_RGB + sizeof(offset);
+	const int frame_offset = offset * SIZE_OF_RGB;
+	int i, rv;
+
+	if (frame_offset + frame_len > sizeof(buf)) {
+		return EC_ERROR_OVERFLOW;
+	}
+
+	rv = aw20198_set_page(ctx, AW20198_PAGE_SCALE);
+	if (rv) {
+		return rv;
+	}
+
+	buf[0] = frame_offset;
+	for (i = 0; i < len; i++) {
+		buf[i * SIZE_OF_RGB + 1] = scale.r;
+		buf[i * SIZE_OF_RGB + 2] = scale.g;
+		buf[i * SIZE_OF_RGB + 3] = scale.b;
+	}
+
+	return i2c_xfer(ctx->cfg->i2c, AW20198_I2C_ADDR_FLAG, buf, frame_len,
+			NULL, 0);
+}
+
+static int aw20198_set_gcc(struct rgbkbd *ctx, uint8_t level)
+{
+	return aw20198_set_config(ctx, AW20198_REG_GCC, level);
+}
+
+static int aw20198_init(struct rgbkbd *ctx)
+{
+	uint8_t u8;
+	int rv;
+
+	rv = aw20198_reset(ctx);
+	msleep(3);
+
+	/* Read chip ID, assuming page is still 0. */
+	rv = aw20198_read(ctx, AW20198_REG_RSTN, &u8);
+	if (rv) {
+		return rv;
+	}
+	CPRINTS("ID=0x%02x", u8);
+
+	/* Modify SWSEL bit4-7 to match the LED layout */
+	rv = aw20198_get_config(ctx, AW20198_REG_GCR, &u8);
+	if (rv) {
+		return rv;
+	}
+	u8 &= ~AW20198_REG_GCR_SWSEL_MASK;
+	u8 |= ((ctx->cfg->col_len - 1) << AW20198_REG_GCR_SWSEL_SHIFT);
+	rv = aw20198_write(ctx, AW20198_REG_GCR, u8);
+	CPRINTS("GCR=0x%02x", u8);
+
+	return rv;
+}
+
+const struct rgbkbd_drv aw20198_drv = {
+	.reset = aw20198_reset,
+	.init = aw20198_init,
+	.enable = aw20198_enable,
+	.set_color = aw20198_set_color,
+	.set_scale = aw20198_set_scale,
+	.set_gcc = aw20198_set_gcc,
+};
diff --git a/driver/led/aw20198.h b/driver/led/aw20198.h
new file mode 100644
index 0000000000..85ef8c4b9e
--- /dev/null
+++ b/driver/led/aw20198.h
@@ -0,0 +1,44 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_DRIVER_LED_AW20198_H
+#define __CROS_EC_DRIVER_LED_AW20198_H
+
+/* This depends on AD0 and AD1. (GRD, GRD) = 0x20. */
+#define AW20198_I2C_ADDR_FLAG 0x20
+
+#define AW20198_ROW_SIZE 6
+#define AW20198_COL_SIZE 11
+#define AW20198_GRID_SIZE (AW20198_COL_SIZE * AW20198_ROW_SIZE)
+
+#define AW20198_PAGE_FUNC 0xC0
+#define AW20198_PAGE_PWM 0xC1
+#define AW20198_PAGE_SCALE 0xC2
+
+#define AW20198_REG_GCR 0x00
+#define AW20198_REG_GCR_SWSEL_MASK 0xF0
+#define AW20198_REG_GCR_SWSEL_SHIFT 4
+#define AW20198_REG_GCR_SW1_ACTIVE 0
+#define AW20198_REG_GCR_SW1_TO_SW2_ACTIVE 1
+#define AW20198_REG_GCR_SW1_TO_SW3_ACTIVE 2
+#define AW20198_REG_GCR_SW1_TO_SW4_ACTIVE 3
+#define AW20198_REG_GCR_SW1_TO_SW5_ACTIVE 4
+#define AW20198_REG_GCR_SW1_TO_SW6_ACTIVE 5
+#define AW20198_REG_GCR_SW1_TO_SW7_ACTIVE 6
+#define AW20198_REG_GCR_SW1_TO_SW8_ACTIVE 7
+#define AW20198_REG_GCR_SW1_TO_SW9_ACTIVE 8
+#define AW20198_REG_GCR_SW1_TO_SW10_ACTIVE 9
+#define AW20198_REG_GCR_SW1_TO_SW11_ACTIVE 10
+
+#define AW20198_REG_GCC 0x01
+#define AW20198_REG_RSTN 0x2F
+#define AW20198_REG_MIXCR 0x46
+#define AW20198_REG_PAGE 0xF0
+
+#define AW20198_RESET_MAGIC 0xAE
+
+extern const struct rgbkbd_drv aw20198_drv;
+
+#endif /* __CROS_EC_DRIVER_LED_AW20198_H */
diff --git a/driver/led/ds2413.c b/driver/led/ds2413.c
index b856d85671..2692c89e30 100644
--- a/driver/led/ds2413.c
+++ b/driver/led/ds2413.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,12 +19,12 @@ enum led_color {
 	LED_RED,
 	LED_YELLOW,
 	LED_GREEN,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
-static const uint8_t led_masks[LED_COLOR_COUNT] = {0xff, 0xfe, 0xfc, 0xfd};
-static const char * const color_names[LED_COLOR_COUNT] = {
-	"off", "red", "yellow", "green"};
+static const uint8_t led_masks[LED_COLOR_COUNT] = { 0xff, 0xfe, 0xfc, 0xfd };
+static const char *const color_names[LED_COLOR_COUNT] = { "off", "red",
+							  "yellow", "green" };
 
 /**
  * Set the onewire LED GPIO controller outputs
@@ -48,9 +48,9 @@ static int led_set_mask(int mask)
 	/* Write and turn on the LEDs */
 	onewire_write(0x5a);
 	onewire_write(mask);
-	onewire_write(~mask);  /* Repeat inverted */
+	onewire_write(~mask); /* Repeat inverted */
 
-	rv = onewire_read();   /* Confirmation byte */
+	rv = onewire_read(); /* Confirmation byte */
 	if (rv != 0xaa)
 		return EC_ERROR_UNKNOWN;
 
@@ -107,20 +107,20 @@ static void onewire_led_tick(void)
 	}
 
 	/* Translate charge state to LED color */
-	switch (charge_get_state()) {
-	case PWR_STATE_IDLE:
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			new_color = (tick_count & 1) ? LED_GREEN : LED_OFF;
-		else
-			new_color = LED_GREEN;
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_IDLE:
+		new_color = LED_GREEN;
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		new_color = (tick_count & 1) ? LED_GREEN : LED_OFF;
 		break;
-	case PWR_STATE_CHARGE:
+	case LED_PWRS_CHARGE:
 		new_color = LED_YELLOW;
 		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
+	case LED_PWRS_CHARGE_NEAR_FULL:
 		new_color = LED_GREEN;
 		break;
-	case PWR_STATE_ERROR:
+	case LED_PWRS_ERROR:
 		new_color = LED_RED;
 		break;
 	default:
@@ -149,7 +149,7 @@ DECLARE_HOOK(HOOK_SECOND, onewire_led_tick, HOOK_PRIO_DEFAULT);
 /*****************************************************************************/
 /* Console commands */
 #define CONFIG_CMD_POWERLED
-static int command_powerled(int argc, char **argv)
+static int command_powerled(int argc, const char **argv)
 {
 	int i;
 
@@ -161,6 +161,5 @@ static int command_powerled(int argc, char **argv)
 	return EC_ERROR_PARAM1;
 }
 DECLARE_CONSOLE_COMMAND(powerled, command_powerled,
-			"<off | red | yellow | green>",
-			"Set power LED color");
+			"<off | red | yellow | green>", "Set power LED color");
 #endif
diff --git a/driver/led/is31fl3733b.c b/driver/led/is31fl3733b.c
new file mode 100644
index 0000000000..3ff0c19655
--- /dev/null
+++ b/driver/led/is31fl3733b.c
@@ -0,0 +1,232 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "common.h"
+#include "console.h"
+#include "gpio.h"
+#include "i2c.h"
+#include "rgb_keyboard.h"
+#include "stddef.h"
+#include "timer.h"
+
+#include <string.h>
+
+#define CPRINTF(fmt, args...) cprintf(CC_RGBKBD, "RGBKBD: " fmt, ##args)
+#define CPRINTS(fmt, args...) cprints(CC_RGBKBD, "RGBKBD: " fmt, ##args)
+
+/* This depends on ADDR1 and ADDR2. (GND, GND) = 0x50. */
+#define IS31FL3733B_ADDR_FLAGS 0x50
+
+#define IS31FL3733B_ROW_SIZE 16
+#define IS31FL3733B_COL_SIZE 4
+#define IS31FL3733B_GRID_SIZE (IS31FL3733B_COL_SIZE * IS31FL3733B_ROW_SIZE)
+#define IS31FL3733B_BUF_SIZE (SIZE_OF_RGB * IS31FL3733B_GRID_SIZE)
+
+/* IS31FL3733B registers */
+#define IS31FL3733B_REG_COMMAND 0xFD
+#define IS31FL3733B_REG_COMMAND_WRITE_LOCK 0xFE
+#define IS31FL3733B_REG_INT_MASK 0xF0
+#define IS31FL3733B_REG_INT_STATUS 0xF1
+
+#define IS31FL3733B_PAGE_CTRL 0x00
+#define IS31FL3733B_PAGE_PWM 0x01
+#define IS31FL3733B_PAGE_AUTO 0x02
+#define IS31FL3733B_PAGE_FUNC 0x03
+
+/* FEh Command Register Write Lock */
+#define IS31FL3733B_WRITE_DISABLE 0x00
+#define IS31FL3733B_WRITE_ENABLE 0xC5
+
+#define IS31FL3733B_INT_MASK_IAC BIT(3)
+#define IS31FL3733B_INT_MASK_IAB BIT(2)
+#define IS31FL3733B_INT_MASK_IS BIT(1)
+#define IS31FL3733B_INT_MASK_IO BIT(0)
+#define IS31FL3733B_INT_STATUS_ABM3 BIT(4)
+#define IS31FL3733B_INT_STATUS_ABM2 BIT(3)
+#define IS31FL3733B_INT_STATUS_ABM1 BIT(2)
+#define IS31FL3733B_INT_STATUS_SB BIT(1)
+#define IS31FL3733B_INT_STATUS_OB BIT(0)
+
+#define IS31FL3733B_FUNC_CFG 0x00
+#define IS31FL3733B_FUNC_GCC 0x01
+#define IS31FL3733B_FUNC_ABM1_1 0x02
+#define IS31FL3733B_FUNC_ABM1_2 0x03
+#define IS31FL3733B_FUNC_ABM1_3 0x04
+#define IS31FL3733B_FUNC_ABM1_4 0x05
+#define IS31FL3733B_FUNC_ABM2_1 0x06
+#define IS31FL3733B_FUNC_ABM2_2 0x07
+#define IS31FL3733B_FUNC_ABM2_3 0x08
+#define IS31FL3733B_FUNC_ABM2_4 0x09
+#define IS31FL3733B_FUNC_ABM3_1 0x0a
+#define IS31FL3733B_FUNC_ABM3_2 0x0b
+#define IS31FL3733B_FUNC_ABM3_3 0x0c
+#define IS31FL3733B_FUNC_ABM3_4 0x0d
+#define IS31FL3733B_FUNC_TUR 0x0e
+#define IS31FL3733B_FUNC_SW_PU 0x0f
+#define IS31FL3733B_FUNC_CS_PD 0x10
+#define IS31FL3733B_FUNC_RST 0x11
+
+static int is31fl3733b_read(struct rgbkbd *ctx, uint8_t addr, uint8_t *value)
+{
+	return i2c_xfer(ctx->cfg->i2c, IS31FL3733B_ADDR_FLAGS, &addr,
+			sizeof(addr), value, sizeof(*value));
+}
+
+static int is31fl3733b_write(struct rgbkbd *ctx, uint8_t addr, uint8_t value)
+{
+	uint8_t buf[2] = {
+		[0] = addr,
+		[1] = value,
+	};
+
+	return i2c_xfer(ctx->cfg->i2c, IS31FL3733B_ADDR_FLAGS, buf, sizeof(buf),
+			NULL, 0);
+}
+
+static int is31fl3733b_set_page(struct rgbkbd *ctx, uint8_t page)
+{
+	int rv;
+
+	/* unlock page select once */
+	rv = is31fl3733b_write(ctx, IS31FL3733B_REG_COMMAND_WRITE_LOCK,
+			       IS31FL3733B_WRITE_ENABLE);
+	if (rv) {
+		return rv;
+	}
+
+	return is31fl3733b_write(ctx, IS31FL3733B_REG_COMMAND, page);
+}
+
+static int is31fl3733b_get_config(struct rgbkbd *ctx, uint8_t addr,
+				  uint8_t *value)
+{
+	int rv;
+
+	rv = is31fl3733b_set_page(ctx, IS31FL3733B_PAGE_FUNC);
+	if (rv) {
+		return rv;
+	}
+
+	return is31fl3733b_read(ctx, addr, value);
+}
+
+static int is31fl3733b_set_config(struct rgbkbd *ctx, uint8_t addr,
+				  uint8_t value)
+{
+	int rv;
+
+	rv = is31fl3733b_set_page(ctx, IS31FL3733B_PAGE_FUNC);
+	if (rv) {
+		return rv;
+	}
+
+	return is31fl3733b_write(ctx, addr, value);
+}
+
+static int is31fl3733b_reset(struct rgbkbd *ctx)
+{
+	uint8_t value;
+
+	return is31fl3733b_get_config(ctx, IS31FL3733B_FUNC_RST, &value);
+}
+
+static int is31fl3733b_enable(struct rgbkbd *ctx, bool enable)
+{
+	uint8_t u8;
+	int rv;
+
+	rv = is31fl3733b_set_page(ctx, IS31FL3733B_PAGE_FUNC);
+	if (rv) {
+		return rv;
+	}
+
+	u8 = 0;
+
+	WRITE_BIT(u8, 4, 1);
+	WRITE_BIT(u8, 0, enable);
+
+	return is31fl3733b_write(ctx, IS31FL3733B_FUNC_CFG, u8);
+}
+
+static int is31fl3733b_set_color(struct rgbkbd *ctx, uint8_t offset,
+				 struct rgb_s *color, uint8_t len)
+{
+	int led_addr, led_addr_row, led_addr_col;
+	int i, rv;
+
+	rv = is31fl3733b_set_page(ctx, IS31FL3733B_PAGE_PWM);
+	if (rv) {
+		return rv;
+	}
+
+	for (i = 0; i < len; i++) {
+		led_addr_row = (offset + i) % ctx->cfg->row_len;
+		led_addr_col = (offset + i) / ctx->cfg->row_len;
+		led_addr = led_addr_row * 0x30 + led_addr_col;
+
+		rv = is31fl3733b_write(ctx, led_addr + 0x00, color[i].r);
+		rv |= is31fl3733b_write(ctx, led_addr + 0x10, color[i].g);
+		rv |= is31fl3733b_write(ctx, led_addr + 0x20, color[i].b);
+
+		if (rv) {
+			return rv;
+		}
+	}
+
+	return EC_SUCCESS;
+}
+
+static int is31fl3733b_set_scale(struct rgbkbd *ctx, uint8_t offset,
+				 struct rgb_s scale, uint8_t len)
+{
+	/* is31fl3733b not support scale function */
+	return EC_SUCCESS;
+}
+
+static int is31fl3733b_set_gcc(struct rgbkbd *ctx, uint8_t level)
+{
+	return is31fl3733b_set_config(ctx, IS31FL3733B_FUNC_GCC, level);
+}
+
+static int is31fl3733b_init(struct rgbkbd *ctx)
+{
+	int i, rv;
+
+	rv = is31fl3733b_reset(ctx);
+	msleep(3);
+
+	/* enable all led */
+	rv = is31fl3733b_set_page(ctx, IS31FL3733B_PAGE_CTRL);
+	if (rv) {
+		return rv;
+	}
+
+	for (i = 0; i < 0x18; i++) {
+		rv = is31fl3733b_write(ctx, i, 0xff);
+		if (rv)
+			CPRINTS("LED 0x%02x init fail (rv=%d)", i, rv);
+	}
+
+	if (IS_ENABLED(CONFIG_RGB_KEYBOARD_DEBUG)) {
+		uint8_t val;
+		int ret;
+
+		ret = is31fl3733b_get_config(ctx, IS31FL3733B_FUNC_SW_PU, &val);
+		CPRINTS("SW_PU: val=0x%02x (rv=%d)", val, ret);
+
+		ret = is31fl3733b_get_config(ctx, IS31FL3733B_FUNC_CS_PD, &val);
+		CPRINTS("CS_PD: val=0x%02x (rv=%d)", val, ret);
+	}
+
+	return rv;
+}
+
+const struct rgbkbd_drv is31fl3733b_drv = {
+	.reset = is31fl3733b_reset,
+	.init = is31fl3733b_init,
+	.enable = is31fl3733b_enable,
+	.set_color = is31fl3733b_set_color,
+	.set_scale = is31fl3733b_set_scale,
+	.set_gcc = is31fl3733b_set_gcc,
+};
diff --git a/driver/led/is31fl3743b.c b/driver/led/is31fl3743b.c
new file mode 100644
index 0000000000..6725c1d406
--- /dev/null
+++ b/driver/led/is31fl3743b.c
@@ -0,0 +1,178 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "common.h"
+#include "console.h"
+#include "gpio.h"
+#include "rgb_keyboard.h"
+#include "spi.h"
+#include "stddef.h"
+#include "timer.h"
+
+#include <string.h>
+
+#define CPRINTF(fmt, args...) cprintf(CC_RGBKBD, "RGBKBD: " fmt, ##args)
+#define CPRINTS(fmt, args...) cprints(CC_RGBKBD, "RGBKBD: " fmt, ##args)
+
+#define SPI(id) (&(spi_devices[id]))
+
+#define IS31FL3743B_ROW_SIZE 6
+#define IS31FL3743B_COL_SIZE 11
+#define IS31FL3743B_GRID_SIZE (IS31FL3743B_COL_SIZE * IS31FL3743B_ROW_SIZE)
+#define IS31FL3743B_BUF_SIZE (SIZE_OF_RGB * IS31FL3743B_GRID_SIZE)
+
+#define IS31FL3743B_CMD_ID 0b101
+#define IS31FL3743B_PAGE_PWM 0
+#define IS31FL3743B_PAGE_SCALE 1
+#define IS31FL3743B_PAGE_FUNC 2
+
+#define IS31FL3743B_REG_CONFIG 0x00
+#define IS31FL3743B_REG_GCC 0x01
+#define IS31FL3743B_REG_PD_PU 0x02
+#define IS31FL3743B_REG_SPREAD_SPECTRUM 0x25
+#define IS31FL3743B_REG_RSTN 0x2f
+
+#define IS31FL3743B_CFG_SWS_1_11 0b0000
+#define IS31FL3743B_CONFIG(sws, osde, ssd) \
+	((sws) << 4 | BIT(3) | (osde) << 1 | (ssd) << 0)
+
+struct is31fl3743b_cmd {
+	uint8_t page : 4;
+	uint8_t id : 3;
+	uint8_t read : 1;
+} __packed;
+
+struct is31fl3743b_msg {
+	struct is31fl3743b_cmd cmd;
+	uint8_t addr;
+	uint8_t payload[];
+} __packed;
+
+__maybe_unused static int is31fl3743b_read(struct rgbkbd *ctx, uint8_t addr,
+					   uint8_t *value)
+{
+	uint8_t buf[8];
+	struct is31fl3743b_msg *msg = (void *)buf;
+	const int frame_len = sizeof(*msg);
+
+	msg->cmd.read = 1;
+	msg->cmd.id = IS31FL3743B_CMD_ID;
+	msg->cmd.page = IS31FL3743B_PAGE_FUNC;
+	msg->addr = addr;
+
+	return spi_transaction(SPI(ctx->cfg->spi), buf, frame_len, value, 1);
+}
+
+static int is31fl3743b_write(struct rgbkbd *ctx, uint8_t addr, uint8_t value)
+{
+	uint8_t buf[8];
+	struct is31fl3743b_msg *msg = (void *)buf;
+	const int frame_len = sizeof(*msg) + 1;
+
+	msg->cmd.read = 0;
+	msg->cmd.id = IS31FL3743B_CMD_ID;
+	msg->cmd.page = IS31FL3743B_PAGE_FUNC;
+	msg->addr = addr;
+	msg->payload[0] = value;
+
+	return spi_transaction(SPI(ctx->cfg->spi), buf, frame_len, NULL, 0);
+}
+
+static int is31fl3743b_enable(struct rgbkbd *ctx, bool enable)
+{
+	uint8_t u8 =
+		IS31FL3743B_CONFIG(IS31FL3743B_CFG_SWS_1_11, 0, enable ? 1 : 0);
+	CPRINTS("Setting config register to 0x%x", u8);
+	return is31fl3743b_write(ctx, IS31FL3743B_REG_CONFIG, u8);
+}
+
+static int is31fl3743b_set_color(struct rgbkbd *ctx, uint8_t offset,
+				 struct rgb_s *color, uint8_t len)
+{
+	uint8_t buf[sizeof(struct is31fl3743b_msg) + IS31FL3743B_BUF_SIZE];
+	struct is31fl3743b_msg *msg = (void *)buf;
+	const int frame_len = len * SIZE_OF_RGB + sizeof(*msg);
+	const int frame_offset = offset * SIZE_OF_RGB;
+	int i;
+
+	msg->cmd.read = 0;
+	msg->cmd.id = IS31FL3743B_CMD_ID;
+	msg->cmd.page = IS31FL3743B_PAGE_PWM;
+
+	if (frame_offset + frame_len > sizeof(buf)) {
+		return EC_ERROR_OVERFLOW;
+	}
+
+	msg->addr = frame_offset + 1; /* Register addr base is 1. */
+	for (i = 0; i < len; i++) {
+		msg->payload[i * SIZE_OF_RGB + 0] = color[i].r;
+		msg->payload[i * SIZE_OF_RGB + 1] = color[i].g;
+		msg->payload[i * SIZE_OF_RGB + 2] = color[i].b;
+	}
+
+	return spi_transaction(SPI(ctx->cfg->spi), buf, frame_len, NULL, 0);
+}
+
+static int is31fl3743b_set_scale(struct rgbkbd *ctx, uint8_t offset,
+				 struct rgb_s scale, uint8_t len)
+{
+	uint8_t buf[sizeof(struct is31fl3743b_msg) + IS31FL3743B_BUF_SIZE];
+	struct is31fl3743b_msg *msg = (void *)buf;
+	const int frame_len = len * SIZE_OF_RGB + sizeof(*msg);
+	const int frame_offset = offset * SIZE_OF_RGB;
+	int i;
+
+	msg->cmd.read = 0;
+	msg->cmd.id = IS31FL3743B_CMD_ID;
+	msg->cmd.page = IS31FL3743B_PAGE_SCALE;
+
+	if (frame_offset + frame_len > sizeof(buf)) {
+		return EC_ERROR_OVERFLOW;
+	}
+
+	msg->addr = frame_offset + 1; /* Address base is 1. */
+	for (i = 0; i < len; i++) {
+		msg->payload[i * SIZE_OF_RGB + 0] = scale.r;
+		msg->payload[i * SIZE_OF_RGB + 1] = scale.g;
+		msg->payload[i * SIZE_OF_RGB + 2] = scale.b;
+	}
+
+	return spi_transaction(SPI(ctx->cfg->spi), buf, frame_len, NULL, 0);
+}
+
+static int is31fl3743b_set_gcc(struct rgbkbd *ctx, uint8_t level)
+{
+	uint8_t buf[8];
+	struct is31fl3743b_msg *msg = (void *)buf;
+	const int frame_len = sizeof(*msg) + 1;
+
+	msg->cmd.read = 0;
+	msg->cmd.id = IS31FL3743B_CMD_ID;
+	msg->cmd.page = IS31FL3743B_PAGE_FUNC;
+	msg->addr = IS31FL3743B_REG_GCC;
+	msg->payload[0] = level;
+
+	return spi_transaction(SPI(ctx->cfg->spi), buf, frame_len, NULL, 0);
+}
+
+static int is31fl3743b_init(struct rgbkbd *ctx)
+{
+	int rv;
+
+	/* Reset registers to the default values. */
+	rv = is31fl3743b_write(ctx, IS31FL3743B_REG_RSTN, 0xae);
+	if (rv)
+		return rv;
+	msleep(3);
+
+	return EC_SUCCESS;
+}
+
+const struct rgbkbd_drv is31fl3743b_drv = {
+	.init = is31fl3743b_init,
+	.enable = is31fl3743b_enable,
+	.set_color = is31fl3743b_set_color,
+	.set_scale = is31fl3743b_set_scale,
+	.set_gcc = is31fl3743b_set_gcc,
+};
diff --git a/driver/led/lm3509.c b/driver/led/lm3509.c
index 7c20c43ac2..81dd940c4f 100644
--- a/driver/led/lm3509.c
+++ b/driver/led/lm3509.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -12,22 +12,19 @@
 
 static inline int lm3509_write(uint8_t reg, uint8_t val)
 {
-	return i2c_write8(I2C_PORT_KBLIGHT, LM3509_I2C_ADDR_FLAGS,
-			  reg, val);
+	return i2c_write8(I2C_PORT_KBLIGHT, LM3509_I2C_ADDR_FLAGS, reg, val);
 }
 
 static inline int lm3509_read(uint8_t reg, int *val)
 {
-	return i2c_read8(I2C_PORT_KBLIGHT, LM3509_I2C_ADDR_FLAGS,
-			 reg, val);
+	return i2c_read8(I2C_PORT_KBLIGHT, LM3509_I2C_ADDR_FLAGS, reg, val);
 }
 
 /* Brightness level (0.0 to 100.0%) to brightness register conversion table */
 static const uint16_t lm3509_brightness[32] = {
-	  0,   1,   6,  10,  11,  13,  16,  20,
-	 24,  28,  31,  37,  43,  52,  62,  75,
-	 87, 100, 125, 150, 168, 187, 225, 262,
-	312, 375, 437, 525, 612, 700, 875, 1000
+	0,   1,	  6,   10,  11,	 13,  16,  20,	24,  28,  31,
+	37,  43,  52,  62,  75,	 87,  100, 125, 150, 168, 187,
+	225, 262, 312, 375, 437, 525, 612, 700, 875, 1000
 };
 
 static int brightness_to_bmain(int percent)
@@ -54,6 +51,17 @@ static int lm3509_power(int enable)
 	return lm3509_write(LM3509_REG_GP, enable ? 0x7 : 0);
 }
 
+static int lm3509_get_power(void)
+{
+	int rv, val;
+
+	rv = lm3509_read(LM3509_REG_GP, &val);
+	if (rv)
+		return -1;
+	/* Bit 0: Enable MAIN. Bit 1: Enable SUB/FB */
+	return (val & 0x3) == 0x3 ? 1 : 0;
+}
+
 static int lm3509_set_brightness(int percent)
 {
 	/* We don't need to read/mask/write BMAIN because bit6 and 7 are non
@@ -62,16 +70,6 @@ static int lm3509_set_brightness(int percent)
 	return lm3509_write(LM3509_REG_BMAIN, brightness_to_bmain(percent));
 }
 
-static int lm3509_get_brightness(void)
-{
-	int rv, val;
-	rv = lm3509_read(LM3509_REG_BMAIN, &val);
-	if (rv)
-		return -1;
-	val &= LM3509_BMAIN_MASK;
-	return lm3509_brightness[val] / 10;
-}
-
 static int lm3509_init(void)
 {
 	return EC_SUCCESS;
@@ -80,6 +78,6 @@ static int lm3509_init(void)
 const struct kblight_drv kblight_lm3509 = {
 	.init = lm3509_init,
 	.set = lm3509_set_brightness,
-	.get = lm3509_get_brightness,
 	.enable = lm3509_power,
+	.get_enabled = lm3509_get_power,
 };
diff --git a/driver/led/lm3509.h b/driver/led/lm3509.h
index a7defe1fb7..1f2ace46f0 100644
--- a/driver/led/lm3509.h
+++ b/driver/led/lm3509.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,7 +8,7 @@
 #ifndef __CROS_EC_LM3509_H
 #define __CROS_EC_LM3509_H
 
-#define LM3509_I2C_ADDR_FLAGS	0x36
+#define LM3509_I2C_ADDR_FLAGS 0x36
 
 /*
  * General purpose register
@@ -18,7 +18,7 @@
  * [1]= enable secondary current sink.
  * [0]= enable main current sink.
  */
-#define LM3509_REG_GP		0x10
+#define LM3509_REG_GP 0x10
 
 /*
  * Brightness register
@@ -27,10 +27,10 @@
  * 0x1F: 100%
  * Power-on-value: 0% (0xE0)
  */
-#define LM3509_REG_BMAIN	0xA0
-#define LM3509_REG_BSUB		0xB0
+#define LM3509_REG_BMAIN 0xA0
+#define LM3509_REG_BSUB 0xB0
 
-#define LM3509_BMAIN_MASK	0x1F
+#define LM3509_BMAIN_MASK 0x1F
 
 extern const struct kblight_drv kblight_lm3509;
 
diff --git a/driver/led/lm3630a.c b/driver/led/lm3630a.c
index a2c4aaa74c..e3194ede45 100644
--- a/driver/led/lm3630a.c
+++ b/driver/led/lm3630a.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,20 +10,12 @@
 #include "lm3630a.h"
 #include "timer.h"
 
-
 /* I2C address */
 #define LM3630A_I2C_ADDR_FLAGS 0x36
 
 static inline int lm3630a_write(uint8_t reg, uint8_t val)
 {
-	return i2c_write8(I2C_PORT_KBLIGHT, LM3630A_I2C_ADDR_FLAGS,
-			  reg, val);
-}
-
-static inline int lm3630a_read(uint8_t reg, int *val)
-{
-	return i2c_read8(I2C_PORT_KBLIGHT, LM3630A_I2C_ADDR_FLAGS,
-			 reg, val);
+	return i2c_write8(I2C_PORT_KBLIGHT, LM3630A_I2C_ADDR_FLAGS, reg, val);
 }
 
 static void deferred_lm3630a_poweron(void)
@@ -52,23 +44,22 @@ int lm3630a_poweron(void)
 
 	/* Enable feedback and PWM for banks A. */
 	ret |= lm3630a_write(LM3630A_REG_CONFIG,
-				LM3630A_CFG_BIT_FB_EN_A |
-				LM3630A_CFG_BIT_PWM_EN_A);
+			     LM3630A_CFG_BIT_FB_EN_A |
+				     LM3630A_CFG_BIT_PWM_EN_A);
 
 	/* 24V, 800mA overcurrent protection, 500kHz boost frequency. */
 	ret |= lm3630a_write(LM3630A_REG_BOOST_CONTROL,
-				LM3630A_BOOST_OVP_24V |
-				LM3630A_BOOST_OCP_800MA |
-				LM3630A_FMODE_500KHZ);
+			     LM3630A_BOOST_OVP_24V | LM3630A_BOOST_OCP_800MA |
+				     LM3630A_FMODE_500KHZ);
 
 	/* Limit current to 24.5mA */
 	ret |= lm3630a_write(LM3630A_REG_A_CURRENT, 0x1a);
 
 	/* Enable bank A, put in linear mode, and connect LED2 to bank A. */
 	ret |= lm3630a_write(LM3630A_REG_CONTROL,
-				LM3630A_CTRL_BIT_LINEAR_A |
-				LM3630A_CTRL_BIT_LED_EN_A |
-				LM3630A_CTRL_BIT_LED2_ON_A);
+			     LM3630A_CTRL_BIT_LINEAR_A |
+				     LM3630A_CTRL_BIT_LED_EN_A |
+				     LM3630A_CTRL_BIT_LED2_ON_A);
 
 	/*
 	 * Only set the brightness after ~100 ms. Without this, LED may blink
diff --git a/driver/led/lm3630a.h b/driver/led/lm3630a.h
index d43304b66e..34a268c370 100644
--- a/driver/led/lm3630a.h
+++ b/driver/led/lm3630a.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,56 +8,56 @@
 #ifndef __CROS_EC_LM3630A_H
 #define __CROS_EC_LM3630A_H
 
-#define LM3630A_REG_CONTROL		0x00
-#define LM3630A_REG_CONFIG		0x01
-#define LM3630A_REG_BOOST_CONTROL	0x02
-#define LM3630A_REG_A_BRIGHTNESS	0x03
-#define LM3630A_REG_B_BRIGHTNESS	0x04
-#define LM3630A_REG_A_CURRENT		0x05
-#define LM3630A_REG_B_CURRENT		0x06
-#define LM3630A_REG_ONOFF_RAMP		0x07
-#define LM3630A_REG_RUN_RAMP		0x08
-#define LM3630A_REG_INT_STATUS		0x09
-#define LM3630A_REG_INT_ENABLE		0x0a
-#define LM3630A_REG_FAULT_STATUS	0x0b
-#define LM3630A_REG_SW_RESET		0x0f
-#define LM3630A_REG_PWM_OUT_LOW		0x12
-#define LM3630A_REG_PWM_OUT_HIGH	0x13
-#define LM3630A_REG_REVISION		0x1f
-#define LM3630A_REG_FILTER_STRENGTH	0x50
+#define LM3630A_REG_CONTROL 0x00
+#define LM3630A_REG_CONFIG 0x01
+#define LM3630A_REG_BOOST_CONTROL 0x02
+#define LM3630A_REG_A_BRIGHTNESS 0x03
+#define LM3630A_REG_B_BRIGHTNESS 0x04
+#define LM3630A_REG_A_CURRENT 0x05
+#define LM3630A_REG_B_CURRENT 0x06
+#define LM3630A_REG_ONOFF_RAMP 0x07
+#define LM3630A_REG_RUN_RAMP 0x08
+#define LM3630A_REG_INT_STATUS 0x09
+#define LM3630A_REG_INT_ENABLE 0x0a
+#define LM3630A_REG_FAULT_STATUS 0x0b
+#define LM3630A_REG_SW_RESET 0x0f
+#define LM3630A_REG_PWM_OUT_LOW 0x12
+#define LM3630A_REG_PWM_OUT_HIGH 0x13
+#define LM3630A_REG_REVISION 0x1f
+#define LM3630A_REG_FILTER_STRENGTH 0x50
 
 /* Control register bits */
-#define LM3630A_CTRL_BIT_SLEEP_CMD	BIT(7)
-#define LM3630A_CTRL_BIT_SLEEP_STAT	BIT(6)
-#define LM3630A_CTRL_BIT_LINEAR_A	BIT(4)
-#define LM3630A_CTRL_BIT_LINEAR_B	BIT(3)
-#define LM3630A_CTRL_BIT_LED_EN_A	BIT(2)
-#define LM3630A_CTRL_BIT_LED_EN_B	BIT(1)
-#define LM3630A_CTRL_BIT_LED2_ON_A	BIT(0)
+#define LM3630A_CTRL_BIT_SLEEP_CMD BIT(7)
+#define LM3630A_CTRL_BIT_SLEEP_STAT BIT(6)
+#define LM3630A_CTRL_BIT_LINEAR_A BIT(4)
+#define LM3630A_CTRL_BIT_LINEAR_B BIT(3)
+#define LM3630A_CTRL_BIT_LED_EN_A BIT(2)
+#define LM3630A_CTRL_BIT_LED_EN_B BIT(1)
+#define LM3630A_CTRL_BIT_LED2_ON_A BIT(0)
 
 /* Config register bits */
-#define LM3630A_CFG_BIT_FB_EN_B		BIT(4)
-#define LM3630A_CFG_BIT_FB_EN_A		BIT(3)
-#define LM3630A_CFG_BIT_PWM_LOW		BIT(2)
-#define LM3630A_CFG_BIT_PWM_EN_B	BIT(1)
-#define LM3630A_CFG_BIT_PWM_EN_A	BIT(0)
+#define LM3630A_CFG_BIT_FB_EN_B BIT(4)
+#define LM3630A_CFG_BIT_FB_EN_A BIT(3)
+#define LM3630A_CFG_BIT_PWM_LOW BIT(2)
+#define LM3630A_CFG_BIT_PWM_EN_B BIT(1)
+#define LM3630A_CFG_BIT_PWM_EN_A BIT(0)
 
 /* Boost control register bits */
-#define LM3630A_BOOST_OVP_16V		(0 << 5)
-#define LM3630A_BOOST_OVP_24V		BIT(5)
-#define LM3630A_BOOST_OVP_32V		(2 << 5)
-#define LM3630A_BOOST_OVP_40V		(3 << 5)
-#define LM3630A_BOOST_OCP_600MA		(0 << 3)
-#define LM3630A_BOOST_OCP_800MA		BIT(3)
-#define LM3630A_BOOST_OCP_1000MA	(2 << 3)
-#define LM3630A_BOOST_OCP_1200MA	(3 << 3)
-#define LM3630A_BOOST_SLOW_START	BIT(2)
-#define LM3630A_SHIFT_500KHZ		(0 << 1)  /* FMODE=0 */
-#define LM3630A_SHIFT_560KHZ		BIT(1)  /* FMODE=0 */
-#define LM3630A_SHIFT_1000KHZ		(0 << 1)  /* FMODE=1 */
-#define LM3630A_SHIFT_1120KHZ		BIT(1)  /* FMODE=1 */
-#define LM3630A_FMODE_500KHZ		(0 << 0)
-#define LM3630A_FMODE_1000KHZ		BIT(0)
+#define LM3630A_BOOST_OVP_16V (0 << 5)
+#define LM3630A_BOOST_OVP_24V BIT(5)
+#define LM3630A_BOOST_OVP_32V (2 << 5)
+#define LM3630A_BOOST_OVP_40V (3 << 5)
+#define LM3630A_BOOST_OCP_600MA (0 << 3)
+#define LM3630A_BOOST_OCP_800MA BIT(3)
+#define LM3630A_BOOST_OCP_1000MA (2 << 3)
+#define LM3630A_BOOST_OCP_1200MA (3 << 3)
+#define LM3630A_BOOST_SLOW_START BIT(2)
+#define LM3630A_SHIFT_500KHZ (0 << 1) /* FMODE=0 */
+#define LM3630A_SHIFT_560KHZ BIT(1) /* FMODE=0 */
+#define LM3630A_SHIFT_1000KHZ (0 << 1) /* FMODE=1 */
+#define LM3630A_SHIFT_1120KHZ BIT(1) /* FMODE=1 */
+#define LM3630A_FMODE_500KHZ (0 << 0)
+#define LM3630A_FMODE_1000KHZ BIT(0)
 
 /* Power on and initialize LM3630A. */
 int lm3630a_poweron(void);
diff --git a/driver/led/lp5562.c b/driver/led/lp5562.c
index e0758a8b91..e1766fd776 100644
--- a/driver/led/lp5562.c
+++ b/driver/led/lp5562.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -123,7 +123,7 @@ int lp5562_set_pc(int engine, int val)
 /*****************************************************************************/
 /* Console commands */
 #ifdef CONFIG_CMD_POWERLED
-static int command_lp5562(int argc, char **argv)
+static int command_lp5562(int argc, const char **argv)
 {
 	if (argc == 4) {
 		char *e;
diff --git a/driver/led/lp5562.h b/driver/led/lp5562.h
index 75e820aab7..81031ee084 100644
--- a/driver/led/lp5562.h
+++ b/driver/led/lp5562.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,40 +8,40 @@
 #ifndef __CROS_EC_LP5562_H
 #define __CROS_EC_LP5562_H
 
-#define LP5562_REG_ENABLE	0x00
-#define LP5562_REG_OP_MODE	0x01
-#define LP5562_REG_B_PWM	0x02
-#define LP5562_REG_G_PWM	0x03
-#define LP5562_REG_R_PWM	0x04
-#define LP5562_REG_B_CURRENT	0x05
-#define LP5562_REG_G_CURRENT	0x06
-#define LP5562_REG_R_CURRENT	0x07
-#define LP5562_REG_CONFIG	0x08
-#define LP5562_REG_ENG1_PC	0x09
-#define LP5562_REG_ENG2_PC	0x0a
-#define LP5562_REG_ENG3_PC	0x0b
-#define LP5562_REG_STATUS	0x0c
-#define LP5562_REG_RESET	0x0d
-#define LP5562_REG_W_PWM	0x0e
-#define LP5562_REG_W_CURRENT	0x0f
-#define LP5562_REG_LED_MAP	0x70
-
-#define LP5562_REG_ENG_PROG(n)	(0x10 + ((n)-1) * 0x20)
+#define LP5562_REG_ENABLE 0x00
+#define LP5562_REG_OP_MODE 0x01
+#define LP5562_REG_B_PWM 0x02
+#define LP5562_REG_G_PWM 0x03
+#define LP5562_REG_R_PWM 0x04
+#define LP5562_REG_B_CURRENT 0x05
+#define LP5562_REG_G_CURRENT 0x06
+#define LP5562_REG_R_CURRENT 0x07
+#define LP5562_REG_CONFIG 0x08
+#define LP5562_REG_ENG1_PC 0x09
+#define LP5562_REG_ENG2_PC 0x0a
+#define LP5562_REG_ENG3_PC 0x0b
+#define LP5562_REG_STATUS 0x0c
+#define LP5562_REG_RESET 0x0d
+#define LP5562_REG_W_PWM 0x0e
+#define LP5562_REG_W_CURRENT 0x0f
+#define LP5562_REG_LED_MAP 0x70
+
+#define LP5562_REG_ENG_PROG(n) (0x10 + ((n)-1) * 0x20)
 
 /* Brightness range: 0x00 - 0xff */
-#define LP5562_COLOR_NONE	0x000000
-#define LP5562_COLOR_RED(b)	(0x010000 * (b))
-#define LP5562_COLOR_GREEN(b)	(0x000100 * (b))
-#define LP5562_COLOR_BLUE(b)	(0x000001 * (b))
-
-#define LP5562_ENG_SEL_NONE	0x0
-#define LP5562_ENG_SEL_1	0x1
-#define LP5562_ENG_SEL_2	0x2
-#define LP5562_ENG_SEL_3	0x3
-
-#define LP5562_ENG_HOLD		0x0
-#define LP5562_ENG_STEP		0x1
-#define LP5562_ENG_RUN		0x2
+#define LP5562_COLOR_NONE 0x000000
+#define LP5562_COLOR_RED(b) (0x010000 * (b))
+#define LP5562_COLOR_GREEN(b) (0x000100 * (b))
+#define LP5562_COLOR_BLUE(b) (0x000001 * (b))
+
+#define LP5562_ENG_SEL_NONE 0x0
+#define LP5562_ENG_SEL_1 0x1
+#define LP5562_ENG_SEL_2 0x2
+#define LP5562_ENG_SEL_3 0x3
+
+#define LP5562_ENG_HOLD 0x0
+#define LP5562_ENG_STEP 0x1
+#define LP5562_ENG_RUN 0x2
 
 /* Power on and initialize LP5562. */
 int lp5562_poweron(void);
diff --git a/driver/led/max695x.c b/driver/led/max695x.c
index 6f0e1b8e84..31e0799b11 100644
--- a/driver/led/max695x.c
+++ b/driver/led/max695x.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -13,12 +13,11 @@
 #include "max695x.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 static inline int max695x_i2c_write8(uint8_t offset, uint8_t data)
 {
-	return i2c_write8(I2C_PORT_PORT80, PORT80_I2C_ADDR,
-			   offset, (int)data);
+	return i2c_write8(I2C_PORT_PORT80, PORT80_I2C_ADDR, offset, (int)data);
 }
 
 static inline int max695x_i2c_write(uint8_t offset, uint8_t *data, int len)
@@ -27,8 +26,8 @@ static inline int max695x_i2c_write(uint8_t offset, uint8_t *data, int len)
 	 * The address pointer stored in the MAX695x increments after
 	 * each data byte is written unless the address equals 01111111
 	 */
-	return i2c_write_block(I2C_PORT_PORT80, PORT80_I2C_ADDR,
-			   offset, data, len);
+	return i2c_write_block(I2C_PORT_PORT80, PORT80_I2C_ADDR, offset, data,
+			       len);
 }
 
 int display_7seg_write(enum seven_seg_module_display module, uint16_t data)
@@ -84,20 +83,18 @@ int display_7seg_write(enum seven_seg_module_display module, uint16_t data)
  */
 static void max695x_init(void)
 {
-	uint8_t buf[4] = {
-		[0] = MAX695X_DECODE_MODE_HEX_DECODE,
-		[1] = MAX695X_INTENSITY_MEDIUM,
-		[2] = MAX695X_SCAN_LIMIT_4,
-		[3] = MAX695X_CONFIG_OPR_NORMAL
-	};
+	uint8_t buf[4] = { [0] = MAX695X_DECODE_MODE_HEX_DECODE,
+			   [1] = MAX695X_INTENSITY_MEDIUM,
+			   [2] = MAX695X_SCAN_LIMIT_4,
+			   [3] = MAX695X_CONFIG_OPR_NORMAL };
 	max695x_i2c_write(MAX695X_REG_DECODE_MODE, buf, ARRAY_SIZE(buf));
 }
 DECLARE_HOOK(HOOK_INIT, max695x_init, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, max695x_init, HOOK_PRIO_DEFAULT);
 
 static void max695x_shutdown(void)
 {
-	max695x_i2c_write8(MAX695X_REG_CONFIG,
-			   MAX695X_CONFIG_OPR_SHUTDOWN);
+	max695x_i2c_write8(MAX695X_REG_CONFIG, MAX695X_CONFIG_OPR_SHUTDOWN);
 }
 DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, max695x_shutdown, HOOK_PRIO_DEFAULT);
 
@@ -117,7 +114,6 @@ static int console_command_max695x_write(int argc, char **argv)
 
 	return display_7seg_write(SEVEN_SEG_CONSOLE_DISPLAY, val);
 }
-DECLARE_CONSOLE_COMMAND(seg, console_command_max695x_write,
-			"<val>",
+DECLARE_CONSOLE_COMMAND(seg, console_command_max695x_write, "<val>",
 			"Write to 7 segment display in hex");
 #endif
diff --git a/driver/led/max695x.h b/driver/led/max695x.h
index 5ed5d91e2f..b792237d57 100644
--- a/driver/led/max695x.h
+++ b/driver/led/max695x.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -9,36 +9,36 @@
 #define __CROS_EC_MAX656X_H
 
 /* I2C interface */
-#define MAX695X_I2C_ADDR1_FLAGS	0x38
-#define MAX695X_I2C_ADDR2_FLAGS	0x39
+#define MAX695X_I2C_ADDR1_FLAGS 0x38
+#define MAX695X_I2C_ADDR2_FLAGS 0x39
 
 /* Decode mode register */
-#define MAX695X_REG_DECODE_MODE		0x01
+#define MAX695X_REG_DECODE_MODE 0x01
 /* Hexadecimal decode for digits 3–0 */
-#define MAX695X_DECODE_MODE_HEX_DECODE	0x0f
+#define MAX695X_DECODE_MODE_HEX_DECODE 0x0f
 
 /* Intensity register */
-#define MAX695X_REG_INTENSITY		0x02
+#define MAX695X_REG_INTENSITY 0x02
 /* Setting meduim intensity */
-#define MAX695X_INTENSITY_MEDIUM	0x20
+#define MAX695X_INTENSITY_MEDIUM 0x20
 
 /* Scan limit register value */
-#define MAX695X_REG_SCAN_LIMIT		0x03
+#define MAX695X_REG_SCAN_LIMIT 0x03
 
 /* Scanning digits 0-3 */
-#define MAX695X_SCAN_LIMIT_4		0x03
+#define MAX695X_SCAN_LIMIT_4 0x03
 
 /* Configuration register */
-#define MAX695X_REG_CONFIG		0x04
+#define MAX695X_REG_CONFIG 0x04
 /* Shutdown seven segment display */
-#define MAX695X_CONFIG_OPR_SHUTDOWN	0x00
+#define MAX695X_CONFIG_OPR_SHUTDOWN 0x00
 /* Start seven segment display */
-#define MAX695X_CONFIG_OPR_NORMAL	0x01
+#define MAX695X_CONFIG_OPR_NORMAL 0x01
 
 /* Digit addresses */
-#define MAX695X_DIGIT0_ADDR	0x20
-#define MAX695X_DIGIT1_ADDR	0x21
-#define MAX695X_DIGIT2_ADDR	0x22
-#define MAX695X_DIGIT3_ADDR	0x23
+#define MAX695X_DIGIT0_ADDR 0x20
+#define MAX695X_DIGIT1_ADDR 0x21
+#define MAX695X_DIGIT2_ADDR 0x22
+#define MAX695X_DIGIT3_ADDR 0x23
 
 #endif /* __CROS_EC_MAX656X_H */
diff --git a/driver/led/mp3385.c b/driver/led/mp3385.c
new file mode 100644
index 0000000000..50ce31341a
--- /dev/null
+++ b/driver/led/mp3385.c
@@ -0,0 +1,132 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * MPS MP3385 LED driver.
+ */
+
+#include "console.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "mp3385.h"
+#include "task.h"
+#include "timer.h"
+
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args)
+
+#define I2C_ADDR_MP3385_FLAGS 0x31
+
+struct mp3385_value {
+	uint8_t offset;
+	uint8_t data;
+};
+
+/*
+ * MP3385 asserts the interrupt when it's ready for writing settings, which
+ * are cleared when it's turned off. We enable the interrupt on HOOK_INIT and
+ * keep it enabled in S0/S3/S5.
+ *
+ * It's assumed the device doesn't have a lid and MP3385 is powered only in
+ * S0. For clamshell devices, different interrupt & power control scheme may be
+ * needed.
+ */
+
+/* This ordering is suggested by vendor. */
+static struct mp3385_value mp3385_conf[] = {
+	/*
+	 * Register 0x01: Operation frequency control
+	 * Frequency selection: 300(KHz)
+	 * Short circuit protection: 8(V)
+	 */
+	{ .offset = 1, .data = 0x43 },
+	/*
+	 * Register 0x02: LED current Full-Scale Register
+	 * ISET Resistor: 127(Kohm)
+	 * Maximum LED current: 20196/127 = 159(mA)
+	 * Setting LED current: 62(mA)
+	 */
+	{ .offset = 2, .data = 0x65 },
+
+	/* Register 0x03: RO - ignored */
+
+	/*
+	 * Register 0x04: Internal LED Dimming Brightness Register
+	 * SMBus PWM function: None Use
+	 */
+	{ .offset = 4, .data = 0x00 },
+	/*
+	 * Register 0x05: OVP, OCP Threshold Register
+	 * Over Current Protection: 0.5(V)
+	 * Panel LED Voltage(Max): 47.8(V)
+	 * OVP setting: 54(V)
+	 */
+	{ .offset = 5, .data = 0x97 },
+	/*
+	 * Register 0x00: Dimming mode Register
+	 * String Selection: 4(Number)
+	 * Interface Selection: 1
+	 * Brightness mode: 3
+	 */
+	{ .offset = 0, .data = 0xF2 },
+};
+static const int mp3385_conf_size = ARRAY_SIZE(mp3385_conf);
+
+static void set_mp3385_reg(void)
+{
+	int i;
+
+	for (i = 0; i < mp3385_conf_size; ++i) {
+		int rv = i2c_write8(I2C_PORT_BACKLIGHT, I2C_ADDR_MP3385_FLAGS,
+				    mp3385_conf[i].offset, mp3385_conf[i].data);
+		if (rv) {
+			CPRINTS("Write MP3385 register %d "
+				"failed rv=%d",
+				i, rv);
+			return;
+		}
+	}
+	CPRINTS("Wrote MP3385 settings");
+}
+
+static void mp3385_backlight_enable_deferred(void)
+{
+	if (gpio_get_level(GPIO_PANEL_BACKLIGHT_EN))
+		set_mp3385_reg();
+}
+DECLARE_DEFERRED(mp3385_backlight_enable_deferred);
+
+void mp3385_interrupt(enum gpio_signal signal)
+{
+	/*
+	 * 1. Spec says backlight should be turned on after 500ms
+	 *    after eDP signals are ready.
+	 *
+	 * 2. There's no way to get exact eDP ready time, therefore,
+	 *    give one second delay.
+	 *
+	 * power up  __/----------------
+	 * eDP       ______/------------
+	 * backlight _____________/-----
+	 *                 |- t1 -| : >=500 ms
+	 *             |-   t2   -| : 1 second is enough
+	 */
+	hook_call_deferred(&mp3385_backlight_enable_deferred_data,
+			   MP3385_POWER_BACKLIGHT_DELAY);
+}
+
+int mp3385_set_config(int offset, int data)
+{
+	int i;
+
+	for (i = 0; i < mp3385_conf_size; i++) {
+		if (mp3385_conf[i].offset == offset) {
+			mp3385_conf[i].data = data;
+			return EC_SUCCESS;
+		}
+	}
+
+	CPRINTS("mp3385: offset %d not found", i);
+	return EC_ERROR_INVAL;
+}
diff --git a/driver/led/mp3385.h b/driver/led/mp3385.h
new file mode 100644
index 0000000000..2f179666d8
--- /dev/null
+++ b/driver/led/mp3385.h
@@ -0,0 +1,35 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * MPS MP3385 LED driver.
+ */
+
+#ifndef __CROS_EC_MP3385_H
+#define __CROS_EC_MP3385_H
+
+#include "common.h"
+#include "gpio.h"
+
+/*
+ * Overridable board initialization.  Should be overridden by a board
+ * specific function if the default is not appropriate
+ */
+void mp3385_board_init(void);
+
+/**
+ * Update mp3385 configuration array (mp3385_conf).
+ *
+ * @param offset: Offset of the register to be set.
+ * @param data:   Value to be set.
+ * @return EC_SUCCESS or EC_ERROR_* for errors.
+ */
+int mp3385_set_config(int offset, int data);
+
+#ifndef MP3385_POWER_BACKLIGHT_DELAY
+#define MP3385_POWER_BACKLIGHT_DELAY (15 * MSEC)
+#endif
+
+void mp3385_interrupt(enum gpio_signal signal);
+
+#endif
diff --git a/driver/led/oz554.c b/driver/led/oz554.c
index 504ac55e90..b2cbff08ba 100644
--- a/driver/led/oz554.c
+++ b/driver/led/oz554.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -13,10 +13,10 @@
 #include "task.h"
 #include "timer.h"
 
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args)
 
-#define I2C_ADDR_OZ554_FLAGS	0x31
+#define I2C_ADDR_OZ554_FLAGS 0x31
 
 struct oz554_value {
 	uint8_t offset;
@@ -40,38 +40,38 @@ static struct oz554_value oz554_conf[] = {
 	 * Frequency selection: 300(KHz)
 	 * Short circuit protection: 8(V)
 	 */
-	{.offset = 1, .data = 0x43},
+	{ .offset = 1, .data = 0x43 },
 	/*
 	 * Reigster 0x02: LED current amplitude control
 	 * ISET Resistor: 10.2(Kohm)
 	 * Maximum LED current: 1636/10.2 = 160.4(mA)
 	 * Setting LED current: 65(mA)
 	 */
-	{.offset = 2, .data = 0x65},
+	{ .offset = 2, .data = 0x65 },
 	/*
 	 * Reigster 0x03: LED backlight Status
 	 * Status function: Read only
 	 */
-	{.offset = 3, .data = 0x00},
+	{ .offset = 3, .data = 0x00 },
 	/*
 	 * Reigster 0x04: LED current control with SMBus
 	 * SMBus PWM function: None Use
 	 */
-	{.offset = 4, .data = 0x00},
+	{ .offset = 4, .data = 0x00 },
 	/*
 	 * Reigster 0x05: OVP, OCP control
 	 * Over Current Protection: 0.5(V)
 	 * Panel LED Voltage(Max): 47.8(V)
 	 * OVP setting: 54(V)
 	 */
-	{.offset = 5, .data = 0x97},
+	{ .offset = 5, .data = 0x97 },
 	/*
 	 * Reigster 0x00: Dimming mode and string ON/OFF control
 	 * String Selection: 4(Number)
 	 * Interface Selection: 1
 	 * Brightness mode: 3
 	 */
-	{.offset = 0, .data = 0xF2},
+	{ .offset = 0, .data = 0xF2 },
 };
 static const int oz554_conf_size = ARRAY_SIZE(oz554_conf);
 
@@ -80,11 +80,10 @@ static void set_oz554_reg(void)
 	int i;
 
 	for (i = 0; i < oz554_conf_size; ++i) {
-		int rv = i2c_write8(I2C_PORT_BACKLIGHT,
-				    I2C_ADDR_OZ554_FLAGS,
+		int rv = i2c_write8(I2C_PORT_BACKLIGHT, I2C_ADDR_OZ554_FLAGS,
 				    oz554_conf[i].offset, oz554_conf[i].data);
 		if (rv) {
-			CPRINTS("Write OZ554 register %d failed rv=%d" , i, rv);
+			CPRINTS("Write OZ554 register %d failed rv=%d", i, rv);
 			return;
 		}
 	}
@@ -98,7 +97,7 @@ static void backlight_enable_deferred(void)
 }
 DECLARE_DEFERRED(backlight_enable_deferred);
 
-void backlight_enable_interrupt(enum gpio_signal signal)
+void oz554_interrupt(enum gpio_signal signal)
 {
 	/*
 	 * 1. Spec says backlight should be turned on after 500ms
@@ -114,7 +113,7 @@ void backlight_enable_interrupt(enum gpio_signal signal)
 	 *             |-   t2   -| : 1 second is enough
 	 */
 	hook_call_deferred(&backlight_enable_deferred_data,
-                           OZ554_POWER_BACKLIGHT_DELAY);
+			   OZ554_POWER_BACKLIGHT_DELAY);
 }
 
 int oz554_set_config(int offset, int data)
@@ -132,16 +131,3 @@ int oz554_set_config(int offset, int data)
 	oz554_conf[i].data = data;
 	return EC_SUCCESS;
 }
-
-static void init_oz554(void)
-{
-	oz554_board_init();
-
-	gpio_enable_interrupt(GPIO_PANEL_BACKLIGHT_EN);
-}
-DECLARE_HOOK(HOOK_INIT, init_oz554, HOOK_PRIO_DEFAULT);
-
-
-__overridable void oz554_board_init(void)
-{
-}
diff --git a/driver/led/oz554.h b/driver/led/oz554.h
index d1d9d9656e..27b43a1300 100644
--- a/driver/led/oz554.h
+++ b/driver/led/oz554.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,14 +8,14 @@
 #ifndef __CROS_EC_OZ554_H
 #define __CROS_EC_OZ554_H
 
-#include "gpio.h"
 #include "common.h"
+#include "gpio.h"
 
 /*
  * Overridable board initialization.  Should be overridden by a board
  * specific function if the default is not appropriate
  */
-__override_proto void oz554_board_init(void);
+void oz554_board_init(void);
 
 /**
  * Update oz554 configuration array (oz554_conf).
@@ -30,6 +30,6 @@ int oz554_set_config(int offset, int data);
 #define OZ554_POWER_BACKLIGHT_DELAY SECOND
 #endif
 
-void backlight_enable_interrupt(enum gpio_signal signal);
+void oz554_interrupt(enum gpio_signal signal);
 
 #endif
diff --git a/driver/led/tlc59116f.c b/driver/led/tlc59116f.c
new file mode 100644
index 0000000000..72e51e3fb8
--- /dev/null
+++ b/driver/led/tlc59116f.c
@@ -0,0 +1,137 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "common.h"
+#include "console.h"
+#include "i2c.h"
+#include "rgb_keyboard.h"
+#include "stddef.h"
+#include "tlc59116f.h"
+
+#include <string.h>
+
+#define CPRINTF(fmt, args...) cprintf(CC_RGBKBD, "TLC59116F: " fmt, ##args)
+#define CPRINTS(fmt, args...) cprints(CC_RGBKBD, "TLC59116F: " fmt, ##args)
+
+#define TLC59116F_BUF_SIZE (SIZE_OF_RGB * TLC59116F_GRID_SIZE)
+#define TLC59116_MODE_BIT_SLEEP 4
+
+static int tlc59116f_read(struct rgbkbd *ctx, uint8_t addr, uint8_t *value)
+{
+	return i2c_xfer(ctx->cfg->i2c, TLC59116F_I2C_ADDR_FLAG, &addr,
+			sizeof(addr), value, sizeof(*value));
+}
+
+static int tlc59116f_write(struct rgbkbd *ctx, uint8_t addr, uint8_t value)
+{
+	uint8_t buf[2] = {
+		[0] = addr,
+		[1] = value,
+	};
+
+	return i2c_xfer(ctx->cfg->i2c, TLC59116F_I2C_ADDR_FLAG, buf,
+			sizeof(buf), NULL, 0);
+}
+
+static int tlc59116f_reset(struct rgbkbd *ctx)
+{
+	return i2c_write8(ctx->cfg->i2c, TLC59116F_RESET, 0xA5, 0x5A);
+}
+
+static int tlc59116f_init(struct rgbkbd *ctx)
+{
+	int i, rv;
+
+	for (i = TLC59116F_LEDOUT0; i <= TLC59116F_LEDOUT3; i++) {
+		rv = tlc59116f_write(ctx, i, TLC59116_LEDOUT_PWM);
+		if (rv) {
+			return rv;
+		}
+	}
+
+	rv = tlc59116f_write(ctx, TLC59116F_MODE1, 0x01);
+	if (rv) {
+		CPRINTS("Failed to set TLC59116F normal mode");
+		return rv;
+	}
+
+	return EC_SUCCESS;
+}
+
+static int tlc59116f_enable(struct rgbkbd *ctx, bool enable)
+{
+	uint8_t cfg;
+	int rv;
+
+	rv = tlc59116f_read(ctx, TLC59116F_MODE1, &cfg);
+	if (rv) {
+		CPRINTS("Failed to enable TLC59116F");
+		return rv;
+	}
+
+	if (!enable) {
+		for (int i = TLC59116F_LEDOUT0; i <= TLC59116F_LEDOUT3; i++) {
+			rv = tlc59116f_write(ctx, i, TLC59116_LEDOUT_OFF);
+			if (rv) {
+				return rv;
+			}
+		}
+	}
+
+	WRITE_BIT(cfg, TLC59116_MODE_BIT_SLEEP, !enable);
+	return tlc59116f_write(ctx, TLC59116F_MODE1, cfg);
+}
+
+static int tlc59116f_set_color(struct rgbkbd *ctx, uint8_t offset,
+			       struct rgb_s *color, uint8_t len)
+{
+	uint8_t buf[sizeof(offset) + TLC59116F_BUF_SIZE];
+	const int frame_len = len * SIZE_OF_RGB + sizeof(offset);
+	const int frame_offset = offset * SIZE_OF_RGB;
+	int i;
+
+	if (frame_offset + frame_len > sizeof(buf)) {
+		return EC_ERROR_OVERFLOW;
+	}
+
+	buf[0] = TLC59116_AI_BRIGHTNESS_ONLY | (frame_offset + TLC59116F_PWM0);
+	for (i = 0; i < len; i++) {
+		buf[i * SIZE_OF_RGB + 1] = color[i].r;
+		buf[i * SIZE_OF_RGB + 2] = color[i].g;
+		buf[i * SIZE_OF_RGB + 3] = color[i].b;
+	}
+
+	return i2c_xfer(ctx->cfg->i2c, TLC59116F_I2C_ADDR_FLAG, buf, frame_len,
+			NULL, 0);
+}
+
+static int tlc59116f_set_scale(struct rgbkbd *ctx, uint8_t offset,
+			       struct rgb_s scale, uint8_t len)
+{
+	/* tlc59116f not support scale function */
+	return EC_SUCCESS;
+}
+
+static int tlc59116f_set_gcc(struct rgbkbd *ctx, uint8_t level)
+{
+	int j, rv;
+
+	for (j = TLC59116F_LEDOUT0; j <= TLC59116F_LEDOUT3; j++) {
+		rv = tlc59116f_write(ctx, j, TLC59116_LEDOUT_GROUP);
+		if (rv) {
+			return rv;
+		}
+	}
+
+	return tlc59116f_write(ctx, TLC59116F_GRPPWM, level);
+}
+
+const struct rgbkbd_drv tlc59116f_drv = {
+	.reset = tlc59116f_reset,
+	.init = tlc59116f_init,
+	.enable = tlc59116f_enable,
+	.set_color = tlc59116f_set_color,
+	.set_scale = tlc59116f_set_scale,
+	.set_gcc = tlc59116f_set_gcc,
+};
diff --git a/driver/led/tlc59116f.h b/driver/led/tlc59116f.h
new file mode 100644
index 0000000000..2a0347f568
--- /dev/null
+++ b/driver/led/tlc59116f.h
@@ -0,0 +1,74 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_DRIVER_LED_TLC59116F_H
+#define __CROS_EC_DRIVER_LED_TLC59116F_H
+
+/* TLC59116F secondary address */
+#define TLC59116F_ADDR0_FLAG 0x60
+#define TLC59116F_ADDR1_FLAG 0x61
+#define TLC59116F_ADDR2_FLAG 0x62
+#define TLC59116F_ADDR3_FLAG 0x63
+#define TLC59116F_ADDR4_FLAG 0x64
+#define TLC59116F_ADDR5_FLAG 0x65
+#define TLC59116F_ADDR6_FLAG 0x66
+#define TLC59116F_ADDR7_FLAG 0x67
+#define TLC59116F_ADDR8_FLAG 0x68
+#define TLC59116F_ADDR9_FLAG 0x69
+#define TLC59116F_ADDR10_FLAG 0x6A
+#define TLC59116F_RESET 0x6B
+#define TLC59116F_ADDR12_FLAG 0x6C
+#define TLC59116F_ADDR13_FLAG 0x6D
+#define TLC59116F_ADDR14_FLAG 0x6E
+#define TLC59116F_ADDR15_FLAG 0x6F
+
+#define TLC59116F_ROW_SIZE 1
+#define TLC59116F_COL_SIZE 5
+#define TLC59116F_GRID_SIZE (TLC59116F_COL_SIZE * TLC59116F_ROW_SIZE)
+
+/* TLC59116F registers */
+#define TLC59116F_MODE1 0x00
+#define TLC59116F_MODE2 0x01
+#define TLC59116F_PWM0 0x02
+#define TLC59116F_PWM1 0x03
+#define TLC59116F_PWM2 0x04
+#define TLC59116F_PWM3 0x05
+#define TLC59116F_PWM4 0x06
+#define TLC59116F_PWM5 0x07
+#define TLC59116F_PWM6 0x08
+#define TLC59116F_PWM7 0x09
+#define TLC59116F_PWM8 0x0A
+#define TLC59116F_PWM9 0x0B
+#define TLC59116F_PWM10 0x0C
+#define TLC59116F_PWM11 0x0D
+#define TLC59116F_PWM12 0x0E
+#define TLC59116F_PWM13 0x0F
+#define TLC59116F_PWM14 0x10
+#define TLC59116F_PWM15 0x11
+#define TLC59116F_GRPPWM 0x12
+#define TLC59116F_GRPFREQ 0x13
+#define TLC59116F_LEDOUT0 0x14
+#define TLC59116F_LEDOUT1 0x15
+#define TLC59116F_LEDOUT2 0x16
+#define TLC59116F_LEDOUT3 0x17
+#define TLC59116F_SUBADR1 0x18
+#define TLC59116F_SUBADR2 0x19
+#define TLC59116F_SUBADR3 0x1A
+#define TLC59116F_ALLCALLADR 0x1B
+
+#define TLC59116_LEDOUT_OFF 0x00
+#define TLC59116_LEDOUT_ON 0x55
+#define TLC59116_LEDOUT_PWM 0xAA
+#define TLC59116_LEDOUT_GROUP 0xFF
+
+/* Auto Increment flag */
+#define TLC59116_AI_NONE 0
+#define TLC59116_AI_ALL BIT(7)
+#define TLC59116_AI_BRIGHTNESS_ONLY (BIT(7) | BIT(5))
+#define TLC59116_AI_GCR_ONLY (BIT(7) | BIT(6))
+
+extern const struct rgbkbd_drv tlc59116f_drv;
+
+#endif /* __CROS_EC_DRIVER_LED_TLC59116F_H */
diff --git a/driver/ln9310.c b/driver/ln9310.c
index b6e1c0f197..f9dfedfc54 100644
--- a/driver/ln9310.c
+++ b/driver/ln9310.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -7,17 +7,18 @@
 
 #include "common.h"
 #include "console.h"
-#include "ln9310.h"
+#include "driver/ln9310.h"
 #include "hooks.h"
 #include "i2c.h"
-#include "util.h"
 #include "timer.h"
+#include "util.h"
 
-#define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
-#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPUTS(outstr) cputs(CC_I2C, outstr)
+#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
 
 static int power_good;
+static int startup_workaround_required;
 
 int ln9310_power_good(void)
 {
@@ -26,19 +27,15 @@ int ln9310_power_good(void)
 
 static inline int raw_read8(int offset, int *value)
 {
-	return i2c_read8(ln9310_config.i2c_port,
-			 ln9310_config.i2c_addr_flags,
-			 offset,
-			 value);
+	return i2c_read8(ln9310_config.i2c_port, ln9310_config.i2c_addr_flags,
+			 offset, value);
 }
 
 static inline int field_update8(int offset, int mask, int value)
 {
 	/* Clear mask and then set value in i2c reg value */
 	return i2c_field_update8(ln9310_config.i2c_port,
-				 ln9310_config.i2c_addr_flags,
-				 offset,
-				 mask,
+				 ln9310_config.i2c_addr_flags, offset, mask,
 				 value);
 }
 
@@ -77,26 +74,29 @@ void ln9310_interrupt(enum gpio_signal signal)
 	hook_call_deferred(&ln9310_irq_deferred_data, 0);
 }
 
-static int is_battery_gt_10v(void)
+static int is_battery_gt_10v(bool *out)
 {
-	int status, val, gt_10v;
+	int status, val;
 
 	CPRINTS("LN9310 checking input voltage, threshold=10V");
 	/*
 	 * Turn on INFET_OUT_SWITCH_OK comparator;
 	 * configure INFET_OUT_SWITCH_OK to 10V.
 	 */
-	field_update8(LN9310_REG_TRACK_CTRL,
-		      LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_MASK |
-				LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG_MASK,
-		      LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_ON |
-				LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG_10V);
+	status =
+		field_update8(LN9310_REG_TRACK_CTRL,
+			      LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_MASK |
+				      LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG_MASK,
+			      LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_ON |
+				      LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG_10V);
+	if (status != EC_SUCCESS)
+		return status;
 
 	/* Read INFET_OUT_SWITCH_OK comparator */
 	status = raw_read8(LN9310_REG_BC_STS_B, &val);
-	if (status) {
+	if (status != EC_SUCCESS) {
 		CPRINTS("LN9310 reading BC_STS_B failed");
-		return -1;
+		return status;
 	}
 	CPRINTS("LN9310 BC_STS_B: 0x%x", val);
 
@@ -104,93 +104,290 @@ static int is_battery_gt_10v(void)
 	 * If INFET_OUT_SWITCH_OK=0, VIN < 10V
 	 * If INFET_OUT_SWITCH_OK=1, VIN > 10V
 	 */
-	gt_10v = !!(val & LN9310_BC_STS_B_INFET_OUT_SWITCH_OK);
-	CPRINTS("LN9310 battery %s 10V", gt_10v ? ">" : "<");
+	*out = !!(val & LN9310_BC_STS_B_INFET_OUT_SWITCH_OK);
+	CPRINTS("LN9310 battery %s 10V", (*out) ? ">" : "<");
 
 	/* Turn off INFET_OUT_SWITCH_OK comparator */
-	field_update8(LN9310_REG_TRACK_CTRL,
-		      LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_MASK,
-		      LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_OFF);
+	status = field_update8(LN9310_REG_TRACK_CTRL,
+			       LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_MASK,
+			       LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_OFF);
+
+	return status;
+}
+
+static int ln9310_reset_detected(void)
+{
+	/*
+	 * Check LN9310_REG_LION_CTRL to see if it has been reset to 0x0.
+	 * ln9310_init() and all other functions will set this register
+	 * to a non-zero value so it should only become 0 again if LN9310
+	 * is reset.
+	 */
+	int val, status, reset_detected;
 
-	return gt_10v;
+	status = raw_read8(LN9310_REG_LION_CTRL, &val);
+	if (status) {
+		CPRINTS("LN9310 reading LN9310_REG_LION_CTRL failed");
+		/* If read fails, safest to assume reset has occurred */
+		return 1;
+	}
+	reset_detected = (val == 0x0);
+	if (reset_detected) {
+		CPRINTS("LN9310 was reset (possibly in error)");
+	}
+	return reset_detected;
+}
+
+static int ln9310_update_startup_seq(void)
+{
+	int rc;
+
+	CPRINTS("LN9310 update startup sequence");
+
+	/*
+	 * Startup sequence instruction swap to hold Cfly
+	 * bottom plate low during startup
+	 */
+	rc = field_update8(LN9310_REG_LION_CTRL, LN9310_LION_CTRL_MASK,
+			   LN9310_LION_CTRL_UNLOCK_AND_EN_TM);
+
+	rc |= field_update8(LN9310_REG_SWAP_CTRL_0, 0xff, 0x52);
+
+	rc |= field_update8(LN9310_REG_SWAP_CTRL_1, 0xff, 0x54);
+
+	rc |= field_update8(LN9310_REG_SWAP_CTRL_2, 0xff, 0xCC);
+
+	rc |= field_update8(LN9310_REG_SWAP_CTRL_3, 0xff, 0x02);
+
+	/* Startup sequence settings */
+	rc |= field_update8(
+		LN9310_REG_CFG_4,
+		LN9310_CFG_4_SC_OUT_PRECHARGE_EN_TIME_CFG_MASK |
+			LN9310_CFG_4_SW1_VGS_SHORT_EN_MSK_MASK |
+			LN9310_CFG_4_BSTH_BSTL_HIGH_ROUT_CFG_MASK,
+		LN9310_CFG_4_SC_OUT_PRECHARGE_EN_TIME_CFG_ON |
+			LN9310_CFG_4_SW1_VGS_SHORT_EN_MSK_OFF |
+			LN9310_CFG_4_BSTH_BSTL_HIGH_ROUT_CFG_LOWEST);
+
+	/* SW4 before BSTH_BSTL */
+	rc |= field_update8(LN9310_REG_SPARE_0,
+			    LN9310_SPARE_0_SW4_BEFORE_BSTH_BSTL_EN_CFG_MASK,
+			    LN9310_SPARE_0_SW4_BEFORE_BSTH_BSTL_EN_CFG_ON);
+
+	rc |= field_update8(LN9310_REG_LION_CTRL, LN9310_LION_CTRL_MASK,
+			    LN9310_LION_CTRL_LOCK);
+
+	return rc == EC_SUCCESS ? EC_SUCCESS : EC_ERROR_UNKNOWN;
 }
 
 static int ln9310_init_3to1(void)
 {
+	int rc;
+
 	CPRINTS("LN9310 init (3:1 operation)");
 
 	/* Enable track protection and SC_OUT configs for 3:1 switching */
-	field_update8(LN9310_REG_MODE_CHANGE_CFG,
-		      LN9310_MODE_TM_TRACK_MASK |
-				LN9310_MODE_TM_SC_OUT_PRECHG_MASK |
-				LN9310_MODE_TM_VIN_OV_CFG_MASK,
-		      LN9310_MODE_TM_TRACK_SWITCH31 |
-				LN9310_MODE_TM_SC_OUT_PRECHG_SWITCH31 |
-				LN9310_MODE_TM_VIN_OV_CFG_3S);
+	rc = field_update8(LN9310_REG_MODE_CHANGE_CFG,
+			   LN9310_MODE_TM_TRACK_MASK |
+				   LN9310_MODE_TM_SC_OUT_PRECHG_MASK |
+				   LN9310_MODE_TM_VIN_OV_CFG_MASK,
+			   LN9310_MODE_TM_TRACK_SWITCH31 |
+				   LN9310_MODE_TM_SC_OUT_PRECHG_SWITCH31 |
+				   LN9310_MODE_TM_VIN_OV_CFG_3S);
 
 	/* Enable 3:1 operation mode */
-	field_update8(LN9310_REG_PWR_CTRL,
-		      LN9310_PWR_OP_MODE_MASK,
-		      LN9310_PWR_OP_MODE_SWITCH31);
+	rc |= field_update8(LN9310_REG_PWR_CTRL, LN9310_PWR_OP_MODE_MASK,
+			    LN9310_PWR_OP_MODE_SWITCH31);
 
-	/* 3S lower bounde delta configurations */
-	field_update8(LN9310_REG_LB_CTRL,
-		      LN9310_LB_DELTA_MASK,
-		      LN9310_LB_DELTA_3S);
+	/* 3S lower bound delta configurations */
+	rc |= field_update8(LN9310_REG_LB_CTRL, LN9310_LB_DELTA_MASK,
+			    LN9310_LB_DELTA_3S);
 
 	/*
 	 * TODO(waihong): The LN9310_REG_SYS_CTR was set to a wrong value
 	 * accidentally. Override it to 0. This may not need.
 	 */
-	field_update8(LN9310_REG_SYS_CTRL,
-		      0xff,
-		      0);
+	rc |= field_update8(LN9310_REG_SYS_CTRL, 0xff, 0);
 
-	return EC_SUCCESS;
+	return rc == EC_SUCCESS ? EC_SUCCESS : EC_ERROR_UNKNOWN;
 }
 
 static int ln9310_init_2to1(void)
 {
+	int rc;
+	bool battery_gt_10v;
+
 	CPRINTS("LN9310 init (2:1 operation)");
 
-	if (is_battery_gt_10v()) {
+	rc = is_battery_gt_10v(&battery_gt_10v);
+	if (rc != EC_SUCCESS || battery_gt_10v) {
 		CPRINTS("LN9310 init stop. Input voltage is too high.");
 		return EC_ERROR_UNKNOWN;
 	}
 
 	/* Enable track protection and SC_OUT configs for 2:1 switching */
-	field_update8(LN9310_REG_MODE_CHANGE_CFG,
-		      LN9310_MODE_TM_TRACK_MASK |
-				LN9310_MODE_TM_SC_OUT_PRECHG_MASK,
-		      LN9310_MODE_TM_TRACK_SWITCH21 |
-				LN9310_MODE_TM_SC_OUT_PRECHG_SWITCH21);
+	rc = field_update8(LN9310_REG_MODE_CHANGE_CFG,
+			   LN9310_MODE_TM_TRACK_MASK |
+				   LN9310_MODE_TM_SC_OUT_PRECHG_MASK,
+			   LN9310_MODE_TM_TRACK_SWITCH21 |
+				   LN9310_MODE_TM_SC_OUT_PRECHG_SWITCH21);
 
 	/* Enable 2:1 operation mode */
-	field_update8(LN9310_REG_PWR_CTRL,
-		      LN9310_PWR_OP_MODE_MASK,
-		      LN9310_PWR_OP_MODE_SWITCH21);
+	rc |= field_update8(LN9310_REG_PWR_CTRL, LN9310_PWR_OP_MODE_MASK,
+			    LN9310_PWR_OP_MODE_SWITCH21);
 
-	/* 2S lower bounde delta configurations */
-	field_update8(LN9310_REG_LB_CTRL,
-		      LN9310_LB_DELTA_MASK,
-		      LN9310_LB_DELTA_2S);
+	/* 2S lower bound delta configurations */
+	rc |= field_update8(LN9310_REG_LB_CTRL, LN9310_LB_DELTA_MASK,
+			    LN9310_LB_DELTA_2S);
 
 	/*
 	 * TODO(waihong): The LN9310_REG_SYS_CTR was set to a wrong value
 	 * accidentally. Override it to 0. This may not need.
 	 */
-	field_update8(LN9310_REG_SYS_CTRL,
-		      0xff,
-		      0);
+	rc |= field_update8(LN9310_REG_SYS_CTRL, 0xff, 0);
 
-	return EC_SUCCESS;
+	return rc == EC_SUCCESS ? EC_SUCCESS : EC_ERROR_UNKNOWN;
 }
 
-void ln9310_init(void)
+static int ln9310_update_infet(void)
 {
-	int status, val;
+	int rc;
+
+	CPRINTS("LN9310 update infet configuration");
+
+	rc = field_update8(LN9310_REG_LION_CTRL, LN9310_LION_CTRL_MASK,
+			   LN9310_LION_CTRL_UNLOCK_AND_EN_TM);
+
+	/* Update Infet register settings */
+	rc |= field_update8(LN9310_REG_CFG_5, LN9310_CFG_5_INGATE_PD_EN_MASK,
+			    LN9310_CFG_5_INGATE_PD_EN_OFF);
+
+	rc |= field_update8(LN9310_REG_CFG_5,
+			    LN9310_CFG_5_INFET_CP_PD_BIAS_CFG_MASK,
+			    LN9310_CFG_5_INFET_CP_PD_BIAS_CFG_LOWEST);
+
+	/* enable automatic infet control */
+	rc |= field_update8(LN9310_REG_PWR_CTRL,
+			    LN9310_PWR_INFET_AUTO_MODE_MASK,
+			    LN9310_PWR_INFET_AUTO_MODE_ON);
+
+	/* disable LS_HELPER during IDLE by setting MSK bit high  */
+	rc |= field_update8(LN9310_REG_CFG_0,
+			    LN9310_CFG_0_LS_HELPER_IDLE_MSK_MASK,
+			    LN9310_CFG_0_LS_HELPER_IDLE_MSK_ON);
+
+	rc |= field_update8(LN9310_REG_LION_CTRL, LN9310_LION_CTRL_MASK,
+			    LN9310_LION_CTRL_LOCK);
+
+	return rc == EC_SUCCESS ? EC_SUCCESS : EC_ERROR_UNKNOWN;
+}
+
+static int ln9310_precharge_cfly(uint64_t *precharge_timeout)
+{
+	int status = 0;
+	CPRINTS("LN9310 precharge cfly");
+
+	/* Unlock registers and enable test mode */
+	status |= field_update8(LN9310_REG_LION_CTRL, LN9310_LION_CTRL_MASK,
+				LN9310_LION_CTRL_UNLOCK_AND_EN_TM);
+
+	/* disable test mode overrides */
+	status |= field_update8(LN9310_REG_FORCE_SC21_CTRL_2,
+				LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_MASK,
+				LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_OFF);
+
+	/* Configure test mode target values for precharge ckts.  */
+	status |= field_update8(
+		LN9310_REG_FORCE_SC21_CTRL_1,
+		LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_MASK,
+		LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_ON);
+
+	/* Force SCOUT precharge/predischarge overrides */
+	status |= field_update8(
+		LN9310_REG_TEST_MODE_CTRL,
+		LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_MASK |
+			LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_MASK,
+		LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_ON |
+			LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_ON);
+
+	/* Force enable CFLY precharge overrides */
+	status |= field_update8(LN9310_REG_FORCE_SC21_CTRL_2,
+				LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_MASK,
+				LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_ON);
+
+	/* delay long enough to ensure CFLY has time to fully precharge */
+	usleep(LN9310_CFLY_PRECHARGE_DELAY);
+
+	/* locking and leaving test mode will stop CFLY precharge */
+	*precharge_timeout = get_time().val + LN9310_CFLY_PRECHARGE_TIMEOUT;
+	status |= field_update8(LN9310_REG_LION_CTRL, LN9310_LION_CTRL_MASK,
+				LN9310_LION_CTRL_LOCK);
+
+	return status;
+}
+
+static int ln9310_precharge_cfly_reset(void)
+{
+	int status = 0;
+	CPRINTS("LN9310 precharge cfly reset");
+
+	/* set known initial state for config bits related to cfly precharge */
+	status |= field_update8(LN9310_REG_LION_CTRL, LN9310_LION_CTRL_MASK,
+				LN9310_LION_CTRL_UNLOCK);
+
+	/* Force off SCOUT precharge/predischarge overrides */
+	status |= field_update8(
+		LN9310_REG_TEST_MODE_CTRL,
+		LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_MASK |
+			LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_MASK,
+		LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_OFF |
+			LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_OFF);
+
+	/* disable test mode overrides */
+	status |= field_update8(LN9310_REG_FORCE_SC21_CTRL_2,
+				LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_MASK,
+				LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_OFF);
+
+	/* disable CFLY and SC_OUT precharge control  */
+	status |= field_update8(
+		LN9310_REG_FORCE_SC21_CTRL_1,
+		LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_MASK,
+		LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_OFF);
+
+	status |= field_update8(LN9310_REG_LION_CTRL, LN9310_LION_CTRL_MASK,
+				LN9310_LION_CTRL_LOCK);
+
+	return status;
+}
+
+int ln9310_init(void)
+{
+	int status, val, chip_revision;
 	enum battery_cell_type batt;
 
+	/* Make sure initial state of LN9310 is STANDBY (i.e. output is off)  */
+	field_update8(LN9310_REG_STARTUP_CTRL, LN9310_STARTUP_STANDBY_EN, 1);
+
+	/*
+	 * LN9310 software startup is only required for earlier silicon revs.
+	 * LN9310 hardware revisions after LN9310_BC_STS_C_CHIP_REV_FIXED
+	 * should not use the software startup sequence.
+	 */
+	status = raw_read8(LN9310_REG_BC_STS_C, &val);
+	if (status != EC_SUCCESS) {
+		CPRINTS("LN9310 reading BC_STS_C failed: %d", status);
+		return status;
+	}
+	chip_revision = val & LN9310_BC_STS_C_CHIP_REV_MASK;
+	startup_workaround_required = chip_revision <
+				      LN9310_BC_STS_C_CHIP_REV_FIXED;
+
+	/* Update INFET configuration  */
+	status = ln9310_update_infet();
+
+	if (status != EC_SUCCESS)
+		return status;
+
 	/*
 	 * Set OPERATION_MODE update method
 	 *   - OP_MODE_MANUAL_UPDATE = 0
@@ -200,13 +397,33 @@ void ln9310_init(void)
 		      LN9310_PWR_OP_MODE_MANUAL_UPDATE_MASK,
 		      LN9310_PWR_OP_MODE_MANUAL_UPDATE_OFF);
 
-	field_update8(LN9310_REG_TIMER_CTRL,
-		      LN9310_TIMER_OP_SELF_SYNC_EN_MASK,
+	field_update8(LN9310_REG_TIMER_CTRL, LN9310_TIMER_OP_SELF_SYNC_EN_MASK,
 		      LN9310_TIMER_OP_SELF_SYNC_EN_ON);
 
+	/*
+	 * Use VIN for VDR, not EXT_5V. The following usleep will give
+	 * circuit time to settle.
+	 */
+	field_update8(LN9310_REG_STARTUP_CTRL,
+		      LN9310_STARTUP_SELECT_EXT_5V_FOR_VDR, 0);
+
+	field_update8(LN9310_REG_LB_CTRL, LN9310_LB_MIN_FREQ_EN,
+		      LN9310_LB_MIN_FREQ_EN);
+
+	/* Set minimum switching frequency to 25 kHz */
+	field_update8(LN9310_REG_SPARE_0, LN9310_SPARE_0_LB_MIN_FREQ_SEL_MASK,
+		      LN9310_SPARE_0_LB_MIN_FREQ_SEL_ON);
+
 	usleep(LN9310_CDC_DELAY);
 	CPRINTS("LN9310 OP_MODE Update method: Self-sync");
 
+	if (startup_workaround_required) {
+		/* Update Startup sequence */
+		status = ln9310_update_startup_seq();
+		if (status != EC_SUCCESS)
+			return status;
+	}
+
 	batt = board_get_battery_cell_type();
 	if (batt == BATTERY_CELL_TYPE_3S) {
 		status = ln9310_init_3to1();
@@ -214,16 +431,49 @@ void ln9310_init(void)
 		status = ln9310_init_2to1();
 	} else {
 		CPRINTS("LN9310 not supported battery type: %d", batt);
-		return;
+		return EC_ERROR_INVAL;
 	}
 
 	if (status != EC_SUCCESS)
-		return;
+		return status;
 
 	/* Unmask the MODE change interrupt */
-	field_update8(LN9310_REG_INT1_MSK,
-		      LN9310_INT1_MODE,
-		      0);
+	field_update8(LN9310_REG_INT1_MSK, LN9310_INT1_MODE, 0);
+	return EC_SUCCESS;
+}
+
+void ln9310_software_enable(int enable)
+{
+	int status, val, retry_count;
+	uint64_t precharge_timeout;
+	bool ln9310_init_completed = false;
+
+	/*
+	 * LN9310 startup requires (nEN=0 AND STANDBY_EN=0) where nEN is a pin
+	 * and STANDBY_EN is a register bit. Previous EC firmware set
+	 * STANDBY_EN=1 in ln9310_init and toggled nEN to startup/shutdown. In
+	 * addition to normal startup, this function also implements an
+	 * alternate software (i.e. controlled by EC through I2C commands)
+	 * startup sequence required by older chip versions, so one option is to
+	 * set nEN=1 and just used ln9310_software_enable to startup/shutdown.
+	 * ln9310_software_enable can also be used in conjunction w/ the nEN pin
+	 * (in case nEN pin is desired as visible signal ) as follows:
+	 *
+	 * Initial battery insertion:
+	 * nEN=1
+	 * ln9310_init() - initial condition is STANDBY_EN=1
+	 *
+	 * Power up LN9310:
+	 * nEN=0 - STANDBY_EN should be 1 so this doesn't trigger startup
+	 * ln9310_software_enable(1) - triggers alternate software-based startup
+	 *
+	 * Power down LN9310:
+	 * nEN=1 - shutdown LN9310 (shutdown seq. does not require modification)
+	 * ln9310_software_enable(0) - reset LN9310 register to state necessary
+	 *                             for subsequent startups
+	 */
+	if (ln9310_reset_detected())
+		ln9310_init();
 
 	/* Dummy clear all interrupts */
 	status = raw_read8(LN9310_REG_INT1, &val);
@@ -231,11 +481,99 @@ void ln9310_init(void)
 		CPRINTS("LN9310 reading INT1 failed");
 		return;
 	}
+	CPRINTS("LN9310 cleared interrupts: 0x%x", val);
 
-	/* Clear the STANDBY_EN bit */
-	field_update8(LN9310_REG_STARTUP_CTRL,
-		      LN9310_STANDBY_EN,
-		      0);
+	if (startup_workaround_required) {
+		if (enable) {
+			/*
+			 * Software modification of LN9310 startup sequence w/
+			 * retry loop.
+			 *
+			 * (1) Clear interrupts
+			 * (2) Precharge Cfly w/ overrides of internal LN9310
+			 * signals (3) disable overrides -> stop precharging
+			 * Cfly (4.1) if < 100 ms elapsed since (2) -> trigger
+			 * LN9310 internal startup seq. (4.2) else -> abort and
+			 * optionally retry from step 2
+			 */
+			retry_count = 0;
+			while (!ln9310_init_completed &&
+			       retry_count < LN9310_INIT_RETRY_COUNT) {
+				/* Precharge CFLY before starting up */
+				status = ln9310_precharge_cfly(
+					&precharge_timeout);
+				if (status != EC_SUCCESS) {
+					CPRINTS("LN9310 failed to run Cfly precharge sequence");
+					status = ln9310_precharge_cfly_reset();
+					retry_count++;
+					continue;
+				}
+
+				/*
+				 * Only start the SC if the cfly precharge
+				 * hasn't timed out (i.e. ended too long ago)
+				 */
+				if (get_time().val < precharge_timeout) {
+					/* Clear the STANDBY_EN bit to enable
+					 * the SC */
+					field_update8(LN9310_REG_STARTUP_CTRL,
+						      LN9310_STARTUP_STANDBY_EN,
+						      0);
+					if (get_time().val >
+					    precharge_timeout) {
+						/*
+						 * if timed out during previous
+						 * I2C command, abort startup
+						 * attempt
+						 */
+						field_update8(
+							LN9310_REG_STARTUP_CTRL,
+							LN9310_STARTUP_STANDBY_EN,
+							1);
+					} else {
+						/* all other paths should
+						 * reattempt startup  */
+						ln9310_init_completed = true;
+					}
+				}
+				/* Reset to known state for config bits related
+				 * to cfly precharge */
+				ln9310_precharge_cfly_reset();
+				retry_count++;
+			}
+
+			if (!ln9310_init_completed) {
+				CPRINTS("LN9310 failed to start after %d retry attempts",
+					retry_count);
+			}
+		} else {
+			/*
+			 * Internal LN9310 shutdown sequence is ok as is, so
+			 * just reset the state to prepare for subsequent
+			 * startup sequences.
+			 *
+			 * (1) set STANDBY_EN=1 to be sure the part turns off
+			 * even if nEN=0 (2) reset cfly precharge related
+			 * registers to known initial state
+			 */
+			field_update8(LN9310_REG_STARTUP_CTRL,
+				      LN9310_STARTUP_STANDBY_EN, 1);
+
+			ln9310_precharge_cfly_reset();
+		}
+	} else {
+		/*
+		 * for newer LN9310 revsisions, the startup workaround is not
+		 * required so the STANDBY_EN bit can just be set directly
+		 */
+		field_update8(LN9310_REG_STARTUP_CTRL,
+			      LN9310_STARTUP_STANDBY_EN, !enable);
+	}
+	return;
+}
 
-	CPRINTS("LN9310 cleared interrupts: 0x%x", val);
+__test_only void ln9310_reset_to_initial_state(void)
+{
+	power_good = 0;
+	startup_workaround_required = 0;
 }
diff --git a/driver/ln9310.h b/driver/ln9310.h
deleted file mode 100644
index 2208b0624f..0000000000
--- a/driver/ln9310.h
+++ /dev/null
@@ -1,154 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * LION Semiconductor LN-9310 switched capacitor converter.
- */
-
-#ifndef __CROS_EC_LN9310_H
-#define __CROS_EC_LN9310_H
-
-/* I2C address */
-#define LN9310_I2C_ADDR_0_FLAGS		0x72
-#define LN9310_I2C_ADDR_1_FLAGS		0x73
-#define LN9310_I2C_ADDR_2_FLAGS		0x53
-#define LN9310_I2C_ADDR_3_FLAGS		0x54
-
-/* Registers */
-#define LN9310_REG_CHIP_ID		0x00
-#define LN9310_CHIP_ID			0x44
-#define LN9310_REG_INT1			0x01
-#define LN9310_REG_INT1_MSK		0x02
-#define LN9310_INT1_TIMER		BIT(0)
-#define LN9310_INT1_INFET		BIT(1)
-#define LN9310_INT1_TEMP		BIT(2)
-#define LN9310_INT1_REV_CURR		BIT(3)
-#define LN9310_INT1_MODE		BIT(4)
-#define LN9310_INT1_ALARM		BIT(5)
-#define LN9310_INT1_OK			BIT(6)
-#define LN9310_INT1_FAULT		BIT(7)
-
-#define LN9310_REG_SYSGPIO_MSK		0x03
-
-#define LN9310_REG_SYS_STS		0x04
-#define LN9310_SYS_STANDBY		BIT(0)
-#define LN9310_SYS_SWITCHING21_ACTIVE	BIT(1)
-#define LN9310_SYS_SWITCHING31_ACTIVE	BIT(2)
-#define LN9310_SYS_BYPASS_ACTIVE	BIT(3)
-#define LN9310_SYS_INFET_OK		BIT(4)
-#define LN9310_SYS_SC_OUT_SWITCH_OK	BIT(5)
-#define LN9310_SYS_INFET_OUT_SWITCH_OK	BIT(6)
-
-#define LN9310_REG_SAFETY_STS		0x05
-#define LN9310_REG_FAULT1_STS		0x06
-#define LN9310_REG_FAULT2_STS		0x07
-
-#define LN9310_REG_PWR_CTRL		0x1d
-#define LN9310_PWR_OP_MODE0		BIT(0)
-#define LN9310_PWR_OP_MODE1		BIT(1)
-#define LN9310_PWR_INFET_EN		BIT(2)
-#define LN9310_PWR_INFET_AUTO_MODE	BIT(3)
-#define LN9310_PWR_REVERSE_MODE		BIT(4)
-#define LN9310_PWR_VIN_OV_IGNORE	BIT(5)
-#define LN9310_PWR_OP_MANUAL_UPDATE	BIT(6)
-#define LN9310_PWR_FORCE_INSNS_EN	BIT(7)
-#define LN9310_PWR_OP_MODE_MASK		0x03
-#define LN9310_PWR_OP_MODE_DISABLED	0x00
-#define LN9310_PWR_OP_MODE_BYPASS	0x01
-#define LN9310_PWR_OP_MODE_SWITCH21	0x02
-#define LN9310_PWR_OP_MODE_SWITCH31	0x03
-#define LN9310_PWR_OP_MODE_MANUAL_UPDATE_MASK	0x40
-#define LN9310_PWR_OP_MODE_MANUAL_UPDATE_OFF	0x00
-
-#define LN9310_REG_SYS_CTRL		0x1e
-
-#define LN9310_REG_STARTUP_CTRL		0x1f
-#define LN9310_STANDBY_EN		0x01
-
-#define LN9310_REG_IIN_CTRL		0x20
-#define LN9310_REG_VIN_CTRL		0x21
-
-#define LN9310_REG_TRACK_CTRL		0x22
-#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN		BIT(7)
-#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG2		BIT(6)
-#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG1		BIT(5)
-#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG0		BIT(4)
-#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_MASK	0x80
-#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_ON		0x80
-#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_OFF		0x00
-#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG_MASK	0x70
-#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG_10V	0x10
-
-#define LN9310_REG_OCP_CTRL		0x23
-
-#define LN9310_REG_TIMER_CTRL		0x24
-#define LN9310_TIMER_OP_SELF_SYNC_EN		BIT(3)
-#define LN9310_TIMER_OP_SELF_SYNC_EN_MASK	0x08
-#define LN9310_TIMER_OP_SELF_SYNC_EN_ON		0x08
-
-#define LN9310_REG_RECOVERY_CTRL	0x25
-
-#define LN9310_REG_LB_CTRL		0x26
-#define LN9310_LB_DELTA_MASK		0x38
-#define LN9310_LB_DELTA_2S		0x20
-#define LN9310_LB_DELTA_3S		0x20
-
-#define LN9310_REG_SC_OUT_OV_CTRL	0x29
-#define LN9310_REG_STS_CTRL		0x2d
-
-#define LN9310_REG_MODE_CHANGE_CFG	0x2e
-#define LN9310_MODE_TM_VIN_OV_CFG0		BIT(0)
-#define LN9310_MODE_TM_VIN_OV_CFG1		BIT(1)
-#define LN9310_MODE_TM_VIN_OV_CFG2		BIT(2)
-#define LN9310_MODE_TM_SC_OUT_PRECHG_CFG0	BIT(3)
-#define LN9310_MODE_TM_SC_OUT_PRECHG_CFG1	BIT(4)
-#define LN9310_MODE_TM_TRACK_CFG0		BIT(5)
-#define LN9310_MODE_TM_TRACK_CFG1		BIT(6)
-#define LN9310_MODE_FORCE_MODE_CFG		BIT(7)
-#define LN9310_MODE_TM_TRACK_MASK		0x60
-#define LN9310_MODE_TM_TRACK_BYPASS		0x00
-#define LN9310_MODE_TM_TRACK_SWITCH21		0x20
-#define LN9310_MODE_TM_TRACK_SWITCH31		0x60
-#define LN9310_MODE_TM_SC_OUT_PRECHG_MASK	0x18
-#define LN9310_MODE_TM_SC_OUT_PRECHG_BYPASS	0x0
-#define LN9310_MODE_TM_SC_OUT_PRECHG_SWITCH21	0x08
-#define LN9310_MODE_TM_SC_OUT_PRECHG_SWITCH31	0x18
-#define LN9310_MODE_TM_VIN_OV_CFG_MASK		0x07
-#define LN9310_MODE_TM_VIN_OV_CFG_2S		0x0  /* 14V */
-#define LN9310_MODE_TM_VIN_OV_CFG_3S		0x2  /* 20V */
-
-#define LN9310_REG_SC_DITHER_CTRL	0x2f
-
-#define LN9310_REG_BC_STS_B		0x51
-#define LN9310_BC_STS_B_INFET_OUT_SWITCH_OK		BIT(5)
-#define LN9310_BC_STS_B_INFET_OUT_SWITCH_OK_MASK	0x20
-
-/* LN9310 Timing definition */
-#define LN9310_CDC_DELAY 120	/* 120us */
-
-/* Battery cell type */
-enum battery_cell_type {
-	BATTERY_CELL_TYPE_UNKNOWN = 0,
-	BATTERY_CELL_TYPE_2S = 2,
-	BATTERY_CELL_TYPE_3S = 3
-};
-
-/* Define configuration of LN9310 part */
-struct ln9310_config_t {
-	const int i2c_port;
-	const int i2c_addr_flags;
-};
-
-/* Configuration struct defined at board level */
-extern const struct ln9310_config_t ln9310_config;
-
-/* Init the driver */
-void ln9310_init(void);
-
-/* Interrupt handler */
-void ln9310_interrupt(enum gpio_signal signal);
-
-/* Return the POWER_GOOD status */
-int ln9310_power_good(void);
-
-#endif /* __CROS_EC_LN9310_H */
diff --git a/driver/mag_bmm150.c b/driver/mag_bmm150.c
index 2289a730f9..5088e51c14 100644
--- a/driver/mag_bmm150.c
+++ b/driver/mag_bmm150.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,75 +25,74 @@
 #error "Not implemented"
 #endif
 
-
 #define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
-
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args)
 
 /****************************************************************************
-* Copyright (C) 2011 - 2014 Bosch Sensortec GmbH
-*
-****************************************************************************/
+ * Copyright (C) 2011 - 2014 Bosch Sensortec GmbH
+ *
+ ****************************************************************************/
 /***************************************************************************
-* License:
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions are met:
-*
-*   Redistributions of source code must retain the above copyright
-*   notice, this list of conditions and the following disclaimer.
-*
-*   Redistributions in binary form must reproduce the above copyright
-*   notice, this list of conditions and the following disclaimer in the
-*   documentation and/or other materials provided with the distribution.
-*
-*   Neither the name of the copyright holder nor the names of the
-*   contributors may be used to endorse or promote products derived from
-*   this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
-*
-* The information provided is believed to be accurate and reliable.
-* The copyright holder assumes no responsibility for the consequences of use
-* of such information nor for any infringement of patents or
-* other rights of third parties which may result from its use.
-* No license is granted by implication or otherwise under any patent or
-* patent rights of the copyright holder.
-*/
-
-#define BMI150_READ_16BIT_COM_REG(store_, addr_) do { \
-	int val; \
-	raw_mag_read8(s->port, s->i2c_spi_addr_flags, (addr_), &val); \
-	store_ = val; \
-	raw_mag_read8(s->port, s->i2c_spi_addr_flags, (addr_) + 1, &val); \
-	store_ |= (val << 8); \
-} while (0)
-
+ * License:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *   Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ *   Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ *
+ *   Neither the name of the copyright holder nor the names of the
+ *   contributors may be used to endorse or promote products derived from
+ *   this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ * The information provided is believed to be accurate and reliable.
+ * The copyright holder assumes no responsibility for the consequences of use
+ * of such information nor for any infringement of patents or
+ * other rights of third parties which may result from its use.
+ * No license is granted by implication or otherwise under any patent or
+ * patent rights of the copyright holder.
+ */
 
-int bmm150_init(const struct motion_sensor_t *s)
+#define BMI150_READ_16BIT_COM_REG(store_, addr_)                              \
+	do {                                                                  \
+		int val;                                                      \
+		raw_mag_read8(s->port, s->i2c_spi_addr_flags, (addr_), &val); \
+		store_ = val;                                                 \
+		raw_mag_read8(s->port, s->i2c_spi_addr_flags, (addr_) + 1,    \
+			      &val);                                          \
+		store_ |= (val << 8);                                         \
+	} while (0)
+
+int bmm150_init(struct motion_sensor_t *s)
 {
 	int ret;
 	int val;
 	struct bmm150_comp_registers *regs = BMM150_COMP_REG(s);
-	struct mag_cal_t             *moc = BMM150_CAL(s);
+	struct mag_cal_t *moc = BMM150_CAL(s);
 
 	/* Set the compass from Suspend to Sleep */
-	ret = raw_mag_write8(s->port, s->i2c_spi_addr_flags,
-			     BMM150_PWR_CTRL, BMM150_PWR_ON);
+	ret = raw_mag_write8(s->port, s->i2c_spi_addr_flags, BMM150_PWR_CTRL,
+			     BMM150_PWR_ON);
 	msleep(4);
 	/* Now we can read the device id */
-	ret = raw_mag_read8(s->port, s->i2c_spi_addr_flags,
-			    BMM150_CHIP_ID, &val);
+	ret = raw_mag_read8(s->port, s->i2c_spi_addr_flags, BMM150_CHIP_ID,
+			    &val);
 	if (ret)
 		return EC_ERROR_UNKNOWN;
 
@@ -101,27 +100,24 @@ int bmm150_init(const struct motion_sensor_t *s)
 		return EC_ERROR_ACCESS_DENIED;
 
 	/* Read the private registers for compensation */
-	ret = raw_mag_read8(s->port, s->i2c_spi_addr_flags,
-			    BMM150_REGA_DIG_X1, &val);
+	ret = raw_mag_read8(s->port, s->i2c_spi_addr_flags, BMM150_REGA_DIG_X1,
+			    &val);
 	if (ret)
 		return EC_ERROR_UNKNOWN;
 	regs->dig1[X] = val;
-	raw_mag_read8(s->port, s->i2c_spi_addr_flags,
-		      BMM150_REGA_DIG_Y1, &val);
+	raw_mag_read8(s->port, s->i2c_spi_addr_flags, BMM150_REGA_DIG_Y1, &val);
 	regs->dig1[Y] = val;
-	raw_mag_read8(s->port, s->i2c_spi_addr_flags,
-		      BMM150_REGA_DIG_X2, &val);
+	raw_mag_read8(s->port, s->i2c_spi_addr_flags, BMM150_REGA_DIG_X2, &val);
 	regs->dig2[X] = val;
-	raw_mag_read8(s->port, s->i2c_spi_addr_flags,
-		      BMM150_REGA_DIG_Y2, &val);
+	raw_mag_read8(s->port, s->i2c_spi_addr_flags, BMM150_REGA_DIG_Y2, &val);
 	regs->dig2[Y] = val;
 
-	raw_mag_read8(s->port, s->i2c_spi_addr_flags,
-		      BMM150_REGA_DIG_XY1, &val);
+	raw_mag_read8(s->port, s->i2c_spi_addr_flags, BMM150_REGA_DIG_XY1,
+		      &val);
 	regs->dig_xy1 = val;
 
-	raw_mag_read8(s->port, s->i2c_spi_addr_flags,
-		      BMM150_REGA_DIG_XY2, &val);
+	raw_mag_read8(s->port, s->i2c_spi_addr_flags, BMM150_REGA_DIG_XY2,
+		      &val);
 	regs->dig_xy2 = val;
 
 	BMI150_READ_16BIT_COM_REG(regs->dig_z1, BMM150_REGA_DIG_Z1_LSB);
@@ -130,21 +126,17 @@ int bmm150_init(const struct motion_sensor_t *s)
 	BMI150_READ_16BIT_COM_REG(regs->dig_z4, BMM150_REGA_DIG_Z4_LSB);
 	BMI150_READ_16BIT_COM_REG(regs->dig_xyz1, BMM150_REGA_DIG_XYZ1_LSB);
 
-
 	/* Set the repetition in "Regular Preset" */
-	raw_mag_write8(s->port, s->i2c_spi_addr_flags,
-		       BMM150_REPXY, BMM150_REP(SPECIAL, XY));
-	raw_mag_write8(s->port, s->i2c_spi_addr_flags,
-		       BMM150_REPZ, BMM150_REP(SPECIAL, Z));
-	ret = raw_mag_read8(s->port, s->i2c_spi_addr_flags,
-			    BMM150_REPXY, &val);
-	ret = raw_mag_read8(s->port, s->i2c_spi_addr_flags,
-			    BMM150_REPZ, &val);
+	raw_mag_write8(s->port, s->i2c_spi_addr_flags, BMM150_REPXY,
+		       BMM150_REP(SPECIAL, XY));
+	raw_mag_write8(s->port, s->i2c_spi_addr_flags, BMM150_REPZ,
+		       BMM150_REP(SPECIAL, Z));
+	ret = raw_mag_read8(s->port, s->i2c_spi_addr_flags, BMM150_REPXY, &val);
+	ret = raw_mag_read8(s->port, s->i2c_spi_addr_flags, BMM150_REPZ, &val);
 	/*
 	 * Set the compass forced mode, to sleep after each measure.
 	 */
-	ret = raw_mag_write8(s->port, s->i2c_spi_addr_flags,
-			     BMM150_OP_CTRL,
+	ret = raw_mag_write8(s->port, s->i2c_spi_addr_flags, BMM150_OP_CTRL,
 			     BMM150_OP_MODE_FORCED << BMM150_OP_MODE_OFFSET);
 
 	init_mag_cal(moc);
@@ -152,10 +144,8 @@ int bmm150_init(const struct motion_sensor_t *s)
 	return ret;
 }
 
-void bmm150_temp_compensate_xy(const struct motion_sensor_t *s,
-			       intv3_t raw,
-			       intv3_t comp,
-			       int r)
+void bmm150_temp_compensate_xy(const struct motion_sensor_t *s, intv3_t raw,
+			       intv3_t comp, int r)
 {
 	int inter, axis;
 	struct bmm150_comp_registers *regs = BMM150_COMP_REG(s);
@@ -191,10 +181,8 @@ void bmm150_temp_compensate_xy(const struct motion_sensor_t *s,
 	}
 }
 
-void bmm150_temp_compensate_z(const struct motion_sensor_t *s,
-			      intv3_t raw,
-			      intv3_t comp,
-			      int r)
+void bmm150_temp_compensate_z(const struct motion_sensor_t *s, intv3_t raw,
+			      intv3_t comp, int r)
 {
 	int dividend, divisor;
 	struct bmm150_comp_registers *regs = BMM150_COMP_REG(s);
@@ -221,9 +209,7 @@ void bmm150_temp_compensate_z(const struct motion_sensor_t *s,
 		comp[Z] = BMM150_OVERFLOW_OUTPUT;
 }
 
-void bmm150_normalize(const struct motion_sensor_t *s,
-		      intv3_t v,
-		      uint8_t *data)
+void bmm150_normalize(const struct motion_sensor_t *s, intv3_t v, uint8_t *data)
 {
 	uint16_t r;
 	intv3_t raw;
@@ -247,8 +233,7 @@ void bmm150_normalize(const struct motion_sensor_t *s,
 	v[Z] += cal->bias[Z];
 }
 
-int bmm150_set_offset(const struct motion_sensor_t *s,
-		      const intv3_t offset)
+int bmm150_set_offset(const struct motion_sensor_t *s, const intv3_t offset)
 {
 	struct mag_cal_t *cal = BMM150_CAL(s);
 	cal->bias[X] = offset[X];
@@ -257,8 +242,7 @@ int bmm150_set_offset(const struct motion_sensor_t *s,
 	return EC_SUCCESS;
 }
 
-int bmm150_get_offset(const struct motion_sensor_t *s,
-		      intv3_t offset)
+int bmm150_get_offset(const struct motion_sensor_t *s, intv3_t offset)
 {
 	struct mag_cal_t *cal = BMM150_CAL(s);
 	offset[X] = cal->bias[X];
diff --git a/driver/mag_bmm150.h b/driver/mag_bmm150.h
deleted file mode 100644
index f97d2a8882..0000000000
--- a/driver/mag_bmm150.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* BMM150 magnetometer definition */
-
-#ifndef __CROS_EC_MAG_BMM150_H
-#define __CROS_EC_MAG_BMM150_H
-
-#include "accelgyro.h"
-#include "mag_cal.h"
-
-#define BMM150_ADDR0_FLAGS       0x10
-#define BMM150_ADDR1_FLAGS       0x11
-#define BMM150_ADDR2_FLAGS       0x12
-#define BMM150_ADDR3_FLAGS       0x13
-
-#define BMM150_CHIP_ID           0x40
-#define BMM150_CHIP_ID_MAJOR     0x32
-
-#define BMM150_BASE_DATA         0x42
-
-#define BMM150_INT_STATUS        0x4a
-#define BMM150_PWR_CTRL          0x4b
-#define BMM150_SRST                  (BIT(7) | BIT(1))
-#define BMM150_PWR_ON                BIT(0)
-
-#define BMM150_OP_CTRL           0x4c
-#define BMM150_OP_MODE_OFFSET    1
-#define BMM150_OP_MODE_MASK      3
-#define BMM150_OP_MODE_NORMAL    0x00
-#define BMM150_OP_MODE_FORCED    0x01
-#define BMM150_OP_MODE_SLEEP     0x03
-
-#define BMM150_INT_CTRL          0x4d
-
-#define BMM150_REPXY             0x51
-#define BMM150_LOW_POWER_nXY         3
-#define BMM150_REGULAR_nXY           9
-#define BMM150_ENHANCED_nXY         15
-#define BMM150_HIGH_ACCURACY_nXY    47
-#define BMM150_SPECIAL_nXY          75
-#define BMM150_REPZ              0x52
-#define BMM150_LOW_POWER_nZ          3
-#define BMM150_REGULAR_nZ           15
-#define BMM150_ENHANCED_nZ          27
-#define BMM150_HIGH_ACCURACY_nZ     83
-#define BMM150_SPECIAL_nZ           27
-
-#define BMM150_REP(_preset, _axis) CONCAT4(BMM150_, _preset, _n, _axis)
-
-/* Hidden registers for RHALL calculation */
-#define BMM150_REGA_DIG_X1       0x5d
-#define BMM150_REGA_DIG_Y1       0x5e
-#define BMM150_REGA_DIG_Z4_LSB   0x62
-#define BMM150_REGA_DIG_Z4_MSB   0x63
-#define BMM150_REGA_DIG_X2       0x64
-#define BMM150_REGA_DIG_Y2       0x65
-#define BMM150_REGA_DIG_Z2_LSB   0x68
-#define BMM150_REGA_DIG_Z2_MSB   0x69
-#define BMM150_REGA_DIG_Z1_LSB   0x6a
-#define BMM150_REGA_DIG_Z1_MSB   0x6b
-#define BMM150_REGA_DIG_XYZ1_LSB 0x6c
-#define BMM150_REGA_DIG_XYZ1_MSB 0x6d
-#define BMM150_REGA_DIG_Z3_LSB   0x6e
-#define BMM150_REGA_DIG_Z3_MSB   0x6f
-#define BMM150_REGA_DIG_XY2      0x70
-#define BMM150_REGA_DIG_XY1      0x71
-
-/* Overflow */
-
-#define BMM150_FLIP_OVERFLOW_ADCVAL             (-4096)
-#define BMM150_HALL_OVERFLOW_ADCVAL             (-16384)
-#define BMM150_OVERFLOW_OUTPUT                  (0x8000)
-
-/* Min and Max sampling frequency in mHz */
-#define BMM150_MAG_MIN_FREQ 781
-
-/*
- * From Section 4.2.4, max frequency depends on the preset.
- *
- *  Fmax ~= 1 / (145us * nXY + 500us * nZ + 980us)
- *
- *  To be safe, declare only 75% of the value.
- */
-#define __BMM150_MAG_MAX_FREQ(_preset) (750000000 / \
-	(145 * BMM150_REP(_preset, XY) + 500 *  BMM150_REP(_preset, Z) + 980))
-
-#if (__BMM150_MAG_MAX_FREQ(SPECIAL) > CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ)
-#error "EC too slow for magnetometer"
-#endif
-
-struct bmm150_comp_registers {
-	/* Local copy of the compensation registers. */
-	int8_t       dig1[2];
-	int8_t       dig2[2];
-
-	uint16_t     dig_z1;
-	int16_t      dig_z2;
-	int16_t      dig_z3;
-	int16_t      dig_z4;
-
-	uint8_t      dig_xy1;
-	int8_t       dig_xy2;
-
-	uint16_t     dig_xyz1;
-};
-
-struct bmm150_private_data {
-	/* lsm6dsm_data union requires cal be first element */
-	struct mag_cal_t             cal;
-	struct bmm150_comp_registers comp;
-};
-
-#ifdef CONFIG_MAG_BMI_BMM150
-#include "accelgyro_bmi_common.h"
-
-#define BMM150_COMP_REG(_s) \
-	(&BMI_GET_DATA(_s)->compass.comp)
-
-#define BMM150_CAL(_s) \
-	(&BMI_GET_DATA(_s)->compass.cal)
-/*
- * Behind a BMI, the BMM150 is in forced mode. Be sure to choose a frequency
- * compatible with BMI.
- */
-#define BMM150_MAG_MAX_FREQ(_preset) \
-	BMI_REG_TO_ODR(BMI_ODR_TO_REG(__BMM150_MAG_MAX_FREQ(_preset)))
-#else
-#define BMM150_MAG_MAX_FREQ(_preset) __BMM150_MAG_MAX_FREQ(_preset)
-#endif
-
-/* Specific initialization of BMM150 when behing BMI160 */
-int bmm150_init(const struct motion_sensor_t *s);
-
-/* Command to normalize and apply temperature compensation */
-void bmm150_normalize(const struct motion_sensor_t *s,
-		      intv3_t v,
-		      uint8_t *data);
-
-int bmm150_set_offset(const struct motion_sensor_t *s,
-		      const intv3_t offset);
-
-int bmm150_get_offset(const struct motion_sensor_t *s,
-		      intv3_t   offset);
-
-#endif /* __CROS_EC_MAG_BMM150_H */
diff --git a/driver/mag_lis2mdl.c b/driver/mag_lis2mdl.c
index a9a00cc7c9..f6929ef79a 100644
--- a/driver/mag_lis2mdl.c
+++ b/driver/mag_lis2mdl.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,9 +10,9 @@
  */
 
 #include "common.h"
+#include "driver/accelgyro_lsm6dsm.h"
 #include "driver/mag_lis2mdl.h"
 #include "driver/sensorhub_lsm6dsm.h"
-#include "driver/accelgyro_lsm6dsm.h"
 #include "driver/stm_mems_common.h"
 #include "hwtimer.h"
 #include "mag_cal.h"
@@ -24,11 +24,9 @@
 #endif
 #endif
 
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
 
-void lis2mdl_normalize(const struct motion_sensor_t *s,
-		       intv3_t v,
-		       uint8_t *raw)
+void lis2mdl_normalize(const struct motion_sensor_t *s, intv3_t v, uint8_t *raw)
 {
 	struct mag_cal_t *cal = LIS2MDL_CAL(s);
 	int i;
@@ -66,33 +64,24 @@ void lis2mdl_normalize(const struct motion_sensor_t *s,
 	v[Z] += cal->bias[Z];
 }
 
-static int set_range(const struct motion_sensor_t *s, int range, int rnd)
+static int set_range(struct motion_sensor_t *s, int range, int rnd)
 {
-	struct stprivate_data *data = s->drv_data;
-
 	/* Range is fixed by hardware */
 	if (range != s->default_range)
 		return EC_ERROR_INVAL;
 
-	data->base.range = range;
+	s->current_range = range;
 	return EC_SUCCESS;
 }
 
-static int get_range(const struct motion_sensor_t *s)
-{
-	struct stprivate_data *data = s->drv_data;
-
-	return data->base.range;
-}
-
 /**
  * set_offset - Set data offset
  * @s: Motion sensor pointer
  * @offset: offset vector
  * @temp: Temp
  */
-static int set_offset(const struct motion_sensor_t *s,
-		      const int16_t *offset, int16_t temp)
+static int set_offset(const struct motion_sensor_t *s, const int16_t *offset,
+		      int16_t temp)
 {
 	struct mag_cal_t *cal = LIS2MDL_CAL(s);
 
@@ -109,8 +98,8 @@ static int set_offset(const struct motion_sensor_t *s,
  * @offset: offset vector
  * @temp: Temp
  */
-static int get_offset(const struct motion_sensor_t *s,
-		      int16_t *offset, int16_t *temp)
+static int get_offset(const struct motion_sensor_t *s, int16_t *offset,
+		      int16_t *temp)
 {
 	struct mag_cal_t *cal = LIS2MDL_CAL(s);
 	intv3_t offset_int;
@@ -140,7 +129,7 @@ int lis2mdl_thru_lsm6dsm_read(const struct motion_sensor_t *s, intv3_t v)
 	return ret;
 }
 
-int lis2mdl_thru_lsm6dsm_init(const struct motion_sensor_t *s)
+int lis2mdl_thru_lsm6dsm_init(struct motion_sensor_t *s)
 {
 	int ret = EC_ERROR_UNIMPLEMENTED;
 	struct mag_cal_t *cal = LIS2MDL_CAL(s);
@@ -148,26 +137,24 @@ int lis2mdl_thru_lsm6dsm_init(const struct motion_sensor_t *s)
 
 	mutex_lock(s->mutex);
 	/* Magnetometer in cascade mode */
-	ret = sensorhub_check_and_rst(
-			LSM6DSM_MAIN_SENSOR(s),
-			CONFIG_ACCELGYRO_SEC_ADDR_FLAGS,
-			LIS2MDL_WHO_AM_I_REG, LIS2MDL_WHO_AM_I,
-			LIS2MDL_CFG_REG_A_ADDR, LIS2MDL_FLAG_SW_RESET);
+	ret = sensorhub_check_and_rst(LSM6DSM_MAIN_SENSOR(s),
+				      CONFIG_ACCELGYRO_SEC_ADDR_FLAGS,
+				      LIS2MDL_WHO_AM_I_REG, LIS2MDL_WHO_AM_I,
+				      LIS2MDL_CFG_REG_A_ADDR,
+				      LIS2MDL_FLAG_SW_RESET);
 	if (ret != EC_SUCCESS)
 		goto err_unlock;
 
-	ret = sensorhub_config_ext_reg(
-			LSM6DSM_MAIN_SENSOR(s),
-			CONFIG_ACCELGYRO_SEC_ADDR_FLAGS,
-			LIS2MDL_CFG_REG_A_ADDR,
-			LIS2MDL_ODR_50HZ | LIS2MDL_MODE_CONT);
+	ret = sensorhub_config_ext_reg(LSM6DSM_MAIN_SENSOR(s),
+				       CONFIG_ACCELGYRO_SEC_ADDR_FLAGS,
+				       LIS2MDL_CFG_REG_A_ADDR,
+				       LIS2MDL_ODR_50HZ | LIS2MDL_MODE_CONT);
 	if (ret != EC_SUCCESS)
 		goto err_unlock;
 
-	ret = sensorhub_config_slv0_read(
-			LSM6DSM_MAIN_SENSOR(s),
-			CONFIG_ACCELGYRO_SEC_ADDR_FLAGS,
-			LIS2MDL_OUT_REG, OUT_XYZ_SIZE);
+	ret = sensorhub_config_slv0_read(LSM6DSM_MAIN_SENSOR(s),
+					 CONFIG_ACCELGYRO_SEC_ADDR_FLAGS,
+					 LIS2MDL_OUT_REG, OUT_XYZ_SIZE);
 	if (ret != EC_SUCCESS)
 		goto err_unlock;
 
@@ -206,8 +193,8 @@ static int lis2mdl_is_data_ready(const struct motion_sensor_t *s, int *ready)
 {
 	int ret, tmp;
 
-	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags,
-			   LIS2MDL_STATUS_REG, &tmp);
+	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, LIS2MDL_STATUS_REG,
+			   &tmp);
 	if (ret != EC_SUCCESS) {
 		*ready = 0;
 		return ret;
@@ -215,7 +202,6 @@ static int lis2mdl_is_data_ready(const struct motion_sensor_t *s, int *ready)
 
 	*ready = tmp & LIS2MDL_XYZ_DIRTY_MASK;
 	return EC_SUCCESS;
-
 }
 
 /**
@@ -248,8 +234,8 @@ int lis2mdl_read(const struct motion_sensor_t *s, intv3_t v)
 	}
 
 	mutex_lock(s->mutex);
-	ret = st_raw_read_n(s->port, s->i2c_spi_addr_flags,
-			    LIS2MDL_OUT_REG, raw, OUT_XYZ_SIZE);
+	ret = st_raw_read_n(s->port, s->i2c_spi_addr_flags, LIS2MDL_OUT_REG,
+			    raw, OUT_XYZ_SIZE);
 	mutex_unlock(s->mutex);
 	if (ret == EC_SUCCESS) {
 		lis2mdl_normalize(s, v, raw);
@@ -261,7 +247,7 @@ int lis2mdl_read(const struct motion_sensor_t *s, intv3_t v)
 /**
  * Initialize the sensor. This function will verify the who-am-I register
  */
-int lis2mdl_init(const struct motion_sensor_t *s)
+int lis2mdl_init(struct motion_sensor_t *s)
 {
 	int ret = EC_ERROR_UNKNOWN, who_am_i, count = LIS2MDL_STARTUP_MS;
 	struct stprivate_data *data = s->drv_data;
@@ -289,8 +275,7 @@ int lis2mdl_init(const struct motion_sensor_t *s)
 	mutex_lock(s->mutex);
 
 	/* Reset the sensor */
-	ret = st_raw_write8(s->port, LIS2MDL_ADDR_FLAGS,
-			    LIS2MDL_CFG_REG_A_ADDR,
+	ret = st_raw_write8(s->port, LIS2MDL_ADDR_FLAGS, LIS2MDL_CFG_REG_A_ADDR,
 			    LIS2MDL_FLAG_SW_RESET);
 	if (ret != EC_SUCCESS)
 		goto lis2mdl_init_error;
@@ -339,20 +324,20 @@ int lis2mdl_set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
 	if (rate > 0) {
 		if (rnd)
 			/* Round up */
-			reg_val = rate <= 10000 ? LIS2MDL_ODR_10HZ
-				: rate <= 20000 ? LIS2MDL_ODR_20HZ
-				: LIS2MDL_ODR_50HZ;
+			reg_val = rate <= 10000 ? LIS2MDL_ODR_10HZ :
+				  rate <= 20000 ? LIS2MDL_ODR_20HZ :
+						  LIS2MDL_ODR_50HZ;
 		else
 			/* Round down */
-			reg_val = rate < 20000 ? LIS2MDL_ODR_10HZ
-				: rate < 50000 ? LIS2MDL_ODR_20HZ
-				: LIS2MDL_ODR_50HZ;
+			reg_val = rate < 20000 ? LIS2MDL_ODR_10HZ :
+				  rate < 50000 ? LIS2MDL_ODR_20HZ :
+						 LIS2MDL_ODR_50HZ;
 	}
 
-	normalized_rate = rate <= 0 ? 0
-		: reg_val == LIS2MDL_ODR_10HZ ? 10000
-		: reg_val == LIS2MDL_ODR_20HZ ? 20000
-		: 50000;
+	normalized_rate = rate <= 0		      ? 0 :
+			  reg_val == LIS2MDL_ODR_10HZ ? 10000 :
+			  reg_val == LIS2MDL_ODR_20HZ ? 20000 :
+							50000;
 
 	/*
 	 * If no change is needed just bail. Not doing so will require a reset
@@ -365,10 +350,9 @@ int lis2mdl_set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
 		init_mag_cal(cal);
 
 	if (normalized_rate > 0)
-		cal->batch_size = MAX(
-				MAG_CAL_MIN_BATCH_SIZE,
-				(normalized_rate * 1000) /
-					MAG_CAL_MIN_BATCH_WINDOW_US);
+		cal->batch_size = MAX(MAG_CAL_MIN_BATCH_SIZE,
+				      (normalized_rate * 1000) /
+					      MAG_CAL_MIN_BATCH_WINDOW_US);
 	else
 		cal->batch_size = 0;
 
@@ -405,7 +389,6 @@ const struct accelgyro_drv lis2mdl_drv = {
 	.set_data_rate = lis2mdl_set_data_rate,
 #endif /* !CONFIG_MAG_LSM6DSM_LIS2MDL */
 	.set_range = set_range,
-	.get_range = get_range,
 	.get_data_rate = st_get_data_rate,
 	.get_resolution = st_get_resolution,
 	.set_offset = set_offset,
diff --git a/driver/mag_lis2mdl.h b/driver/mag_lis2mdl.h
index a7c47ec00e..ea28137beb 100644
--- a/driver/mag_lis2mdl.h
+++ b/driver/mag_lis2mdl.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,45 +16,45 @@
  * 8-bit address is 0011110Wb where the last bit represents whether the
  * operation is a read or a write.
  */
-#define LIS2MDL_ADDR_FLAGS		0x1e
+#define LIS2MDL_ADDR_FLAGS 0x1e
 
-#define LIS2MDL_STARTUP_MS		10
+#define LIS2MDL_STARTUP_MS 10
 
 /* Registers */
-#define LIS2MDL_WHO_AM_I_REG		0x4f
-#define LIS2MDL_CFG_REG_A_ADDR		0x60
-#define LIS2MDL_INT_CTRL_REG		0x63
-#define LIS2MDL_STATUS_REG		0x67
-#define LIS2MDL_OUT_REG			0x68
-
-#define LIS2MDL_WHO_AM_I		0x40
-
-#define LIS2MDL_FLAG_TEMP_COMPENSATION	0x80
-#define LIS2MDL_FLAG_REBOOT		0x40
-#define LIS2MDL_FLAG_SW_RESET		0x20
-#define LIS2MDL_FLAG_LOW_POWER		0x10
-#define LIS2MDL_ODR_50HZ		0x08
-#define LIS2MDL_ODR_20HZ		0x04
-#define LIS2MDL_ODR_10HZ		0x00
-#define LIS2MDL_MODE_IDLE		0x03
-#define LIS2MDL_MODE_SINGLE		0x01
-#define LIS2MDL_MODE_CONT		0x00
-#define LIS2MDL_ODR_MODE_MASK		0x8f
-
-#define LIS2MDL_X_DIRTY			0x01
-#define LIS2MDL_Y_DIRTY			0x02
-#define LIS2MDL_Z_DIRTY			0x04
-#define LIS2MDL_XYZ_DIRTY		0x08
-#define LIS2MDL_XYZ_DIRTY_MASK		0x0f
-
-#define	LIS2DSL_RESOLUTION		16
+#define LIS2MDL_WHO_AM_I_REG 0x4f
+#define LIS2MDL_CFG_REG_A_ADDR 0x60
+#define LIS2MDL_INT_CTRL_REG 0x63
+#define LIS2MDL_STATUS_REG 0x67
+#define LIS2MDL_OUT_REG 0x68
+
+#define LIS2MDL_WHO_AM_I 0x40
+
+#define LIS2MDL_FLAG_TEMP_COMPENSATION 0x80
+#define LIS2MDL_FLAG_REBOOT 0x40
+#define LIS2MDL_FLAG_SW_RESET 0x20
+#define LIS2MDL_FLAG_LOW_POWER 0x10
+#define LIS2MDL_ODR_50HZ 0x08
+#define LIS2MDL_ODR_20HZ 0x04
+#define LIS2MDL_ODR_10HZ 0x00
+#define LIS2MDL_MODE_IDLE 0x03
+#define LIS2MDL_MODE_SINGLE 0x01
+#define LIS2MDL_MODE_CONT 0x00
+#define LIS2MDL_ODR_MODE_MASK 0x8f
+
+#define LIS2MDL_X_DIRTY 0x01
+#define LIS2MDL_Y_DIRTY 0x02
+#define LIS2MDL_Z_DIRTY 0x04
+#define LIS2MDL_XYZ_DIRTY 0x08
+#define LIS2MDL_XYZ_DIRTY_MASK 0x0f
+
+#define LIS2DSL_RESOLUTION 16
 /*
  * Maximum sensor data range (milligauss):
  * Spec is 1.5 mguass / LSB, so 0.15 uT / LSB.
  * Calibration code is set to 16LSB/ut, [0.0625 uT/LSB]
  * Apply a multiplier to change the unit
  */
-#define LIS2MDL_RATIO(_in) (((_in) * 24) / 10)
+#define LIS2MDL_RATIO(_in) (((_in)*24) / 10)
 
 struct lis2mdl_private_data {
 	/* lsm6dsm_data union requires cal be first element */
@@ -63,8 +63,8 @@ struct lis2mdl_private_data {
 	struct stprivate_data data;
 #endif
 #ifdef CONFIG_MAG_BMI_LIS2MDL
-	intv3_t          hn;   /* last sample for offset compensation */
-	int              hn_valid;
+	intv3_t hn; /* last sample for offset compensation */
+	int hn_valid;
 #endif
 };
 
@@ -75,18 +75,15 @@ struct lis2mdl_private_data {
 	(&(DOWNCAST(s->drv_data, struct lis2mdl_private_data, data)->cal))
 #endif
 
-
-#define LIS2MDL_ODR_MIN_VAL	10000
-#define LIS2MDL_ODR_MAX_VAL	50000
+#define LIS2MDL_ODR_MIN_VAL 10000
+#define LIS2MDL_ODR_MAX_VAL 50000
 #if (CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ <= LIS2MDL_ODR_MAX_VAL)
 #error "EC too slow for magnetometer"
 #endif
 
-void lis2mdl_normalize(const struct motion_sensor_t *s,
-		       intv3_t v,
+void lis2mdl_normalize(const struct motion_sensor_t *s, intv3_t v,
 		       uint8_t *data);
 
 extern const struct accelgyro_drv lis2mdl_drv;
 
 #endif /* __CROS_EC_MAG_LIS2MDL_H */
-
diff --git a/driver/mcdp28x0.c b/driver/mcdp28x0.c
index bf44a6eaf8..791c3c519f 100644
--- a/driver/mcdp28x0.c
+++ b/driver/mcdp28x0.c
@@ -1,13 +1,13 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Megachips DisplayPort to HDMI protocol converter / level shifter driver.
  */
 
+#include "common.h"
 #include "config.h"
 #include "console.h"
-#include "common.h"
 #include "ec_commands.h"
 #include "mcdp28x0.h"
 #include "queue.h"
@@ -16,7 +16,7 @@
 #include "usart-stm32f0.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
 
 static uint8_t mcdp_inbuf[MCDP_INBUF_MAX];
 
@@ -35,27 +35,21 @@ static inline void print_buffer(uint8_t *buf, int cnt)
 	CPRINTF("\n");
 }
 #else
-static inline void print_buffer(uint8_t *buf, int cnt) {}
+static inline void print_buffer(uint8_t *buf, int cnt)
+{
+}
 #endif
 
 static struct usart_config const usart_mcdp;
 
-struct queue const usart_mcdp_rx_queue = QUEUE_DIRECT(MCDP_INBUF_MAX,
-						      uint8_t,
-						      usart_mcdp.producer,
-						      null_consumer);
-struct queue const usart_mcdp_tx_queue = QUEUE_DIRECT(MCDP_OUTBUF_MAX,
-						      uint8_t,
-						      null_producer,
-						      usart_mcdp.consumer);
-
-static struct usart_config const usart_mcdp = USART_CONFIG(CONFIG_MCDP28X0,
-							   usart_rx_interrupt,
-							   usart_tx_interrupt,
-							   115200,
-							   0,
-							   usart_mcdp_rx_queue,
-							   usart_mcdp_tx_queue);
+struct queue const usart_mcdp_rx_queue = QUEUE_DIRECT(
+	MCDP_INBUF_MAX, uint8_t, usart_mcdp.producer, null_consumer);
+struct queue const usart_mcdp_tx_queue = QUEUE_DIRECT(
+	MCDP_OUTBUF_MAX, uint8_t, null_producer, usart_mcdp.consumer);
+
+static struct usart_config const usart_mcdp =
+	USART_CONFIG(CONFIG_MCDP28X0, usart_rx_interrupt, usart_tx_interrupt,
+		     115200, 0, usart_mcdp_rx_queue, usart_mcdp_tx_queue);
 
 /**
  * Compute checksum.
@@ -131,7 +125,7 @@ static int rx_serial(uint8_t *msg, int cnt)
 
 	read = queue_remove_units(&usart_mcdp_rx_queue, msg, cnt);
 	while ((read < cnt) && retry) {
-		usleep(100*MSEC);
+		usleep(100 * MSEC);
 		read += queue_remove_units(&usart_mcdp_rx_queue, msg + read,
 					   cnt - read);
 		retry--;
@@ -143,7 +137,7 @@ static int rx_serial(uint8_t *msg, int cnt)
 	if (cnt > msg[0])
 		cnt = msg[0];
 
-	if (msg[cnt-1] != compute_checksum(0, msg, cnt-1))
+	if (msg[cnt - 1] != compute_checksum(0, msg, cnt - 1))
 		return MCDP_ERROR_CHKSUM;
 
 	if (read != cnt) {
@@ -176,9 +170,9 @@ void mcdp_disable(void)
 	usart_shutdown(&usart_mcdp);
 }
 
-int mcdp_get_info(struct mcdp_info  *info)
+int mcdp_get_info(struct mcdp_info *info)
 {
-	const uint8_t msg[2] = {MCDP_CMD_APPSTEST, 0x28};
+	const uint8_t msg[2] = { MCDP_CMD_APPSTEST, 0x28 };
 	int rv = tx_serial(msg, sizeof(msg));
 
 	if (rv)
@@ -233,8 +227,8 @@ static int mcdp_appstest(uint8_t cmd, int paramc, char **paramv)
 		msg[1] = i + 1;
 		msg[2] = (param >> 24) & 0xff;
 		msg[3] = (param >> 16) & 0xff;
-		msg[4] = (param >>  8) & 0xff;
-		msg[5] = (param >>  0) & 0xff;
+		msg[4] = (param >> 8) & 0xff;
+		msg[5] = (param >> 0) & 0xff;
 		rv = tx_serial(msg, sizeof(msg));
 		if (rv)
 			return rv;
@@ -261,7 +255,7 @@ static int mcdp_appstest(uint8_t cmd, int paramc, char **paramv)
 	return EC_SUCCESS;
 }
 
-int command_mcdp(int argc, char **argv)
+int command_mcdp(int argc, const char **argv)
 {
 	int rv = EC_SUCCESS;
 	char *e;
@@ -277,9 +271,8 @@ int command_mcdp(int argc, char **argv)
 			ccprintf("family:%04x chipid:%04x irom:%d.%d.%d "
 				 "fw:%d.%d.%d\n",
 				 MCDP_FAMILY(info.family),
-				 MCDP_CHIPID(info.chipid),
-				 info.irom.major, info.irom.minor,
-				 info.irom.build,
+				 MCDP_CHIPID(info.chipid), info.irom.major,
+				 info.irom.minor, info.irom.build,
 				 info.fw.major, info.fw.minor, info.fw.build);
 	} else if (!strncasecmp(argv[1], "devid", 4)) {
 		uint8_t dev_id = strtoi(argv[2], &e, 10);
@@ -309,6 +302,5 @@ int command_mcdp(int argc, char **argv)
 	return EC_SUCCESS;
 }
 DECLARE_CONSOLE_COMMAND(mcdp, command_mcdp,
-			"info|devid <id>|appstest <cmd> [<params>]",
-			"USB PD");
+			"info|devid <id>|appstest <cmd> [<params>]", "USB PD");
 #endif /* CONFIG_CMD_MCDP */
diff --git a/driver/mcdp28x0.h b/driver/mcdp28x0.h
index 4352a3899e..a35184600f 100644
--- a/driver/mcdp28x0.h
+++ b/driver/mcdp28x0.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,11 +11,11 @@
 #define MCDP_OUTBUF_MAX 16
 #define MCDP_INBUF_MAX 16
 
-#define MCDP_CMD_GETINFO       0x40
-#define MCDP_CMD_GETDEVID      0x30
-#define MCDP_CMD_APPSTEST      0x12
+#define MCDP_CMD_GETINFO 0x40
+#define MCDP_CMD_GETDEVID 0x30
+#define MCDP_CMD_APPSTEST 0x12
 #define MCDP_CMD_APPSTESTPARAM 0x11
-#define MCDP_CMD_ACK           0x0c
+#define MCDP_CMD_ACK 0x0c
 
 /* packet header (2 bytes: length + cmd) + data + footer (1byte: checksum) */
 #define MCDP_RSP_LEN(len) (len + 3)
@@ -48,6 +48,6 @@ void mcdp_disable(void);
  * @info pointer to mcdp_info structure
  * @return zero if success, error code otherwise.
  */
-int mcdp_get_info(struct mcdp_info  *info);
+int mcdp_get_info(struct mcdp_info *info);
 
 #endif
diff --git a/driver/mp2964.c b/driver/mp2964.c
new file mode 100644
index 0000000000..7e08d4f5ba
--- /dev/null
+++ b/driver/mp2964.c
@@ -0,0 +1,147 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Driver for tuning the MP2964 IMVP8 - IMVP9.1 parameters */
+
+#include "console.h"
+#include "i2c.h"
+#include "mp2964.h"
+#include "timer.h"
+#include "util.h"
+
+#define MP2964_STARTUP_WAIT_US (50 * MSEC)
+#define MP2964_STORE_WAIT_US (300 * MSEC)
+#define MP2964_RESTORE_WAIT_US (2 * MSEC)
+
+enum reg_page { REG_PAGE_0, REG_PAGE_1, REG_PAGE_COUNT };
+
+static int mp2964_write8(uint8_t reg, uint8_t value)
+{
+	const uint8_t tx[2] = { reg, value };
+
+	return i2c_xfer_unlocked(I2C_PORT_MP2964, I2C_ADDR_MP2964_FLAGS, tx,
+				 sizeof(tx), NULL, 0, I2C_XFER_SINGLE);
+}
+
+static void mp2964_read16(uint8_t reg, uint16_t *value)
+{
+	const uint8_t tx[1] = { reg };
+	uint8_t rx[2];
+
+	i2c_xfer_unlocked(I2C_PORT_MP2964, I2C_ADDR_MP2964_FLAGS, tx,
+			  sizeof(tx), rx, sizeof(rx), I2C_XFER_SINGLE);
+	*value = (rx[1] << 8) | rx[0];
+}
+
+static void mp2964_write16(uint8_t reg, uint16_t value)
+{
+	const uint8_t tx[3] = { reg, value & 0xff, value >> 8 };
+
+	i2c_xfer_unlocked(I2C_PORT_MP2964, I2C_ADDR_MP2964_FLAGS, tx,
+			  sizeof(tx), NULL, 0, I2C_XFER_SINGLE);
+}
+
+static int mp2964_select_page(enum reg_page page)
+{
+	int status;
+
+	if (page >= REG_PAGE_COUNT)
+		return EC_ERROR_INVAL;
+
+	status = mp2964_write8(MP2964_PAGE, page);
+	if (status != EC_SUCCESS) {
+		ccprintf("%s: could not select page 0x%02x, error %d\n",
+			 __func__, page, status);
+	}
+	return status;
+}
+
+static void mp2964_write_vec16(const struct mp2964_reg_val *init_list,
+			       int count, int *delta)
+{
+	const struct mp2964_reg_val *reg_val;
+	uint16_t outval;
+	int i;
+
+	reg_val = init_list;
+	for (i = 0; i < count; ++i, ++reg_val) {
+		mp2964_read16(reg_val->reg, &outval);
+		if (outval == reg_val->val) {
+			ccprintf("mp2964: reg 0x%02x already 0x%04x\n",
+				 reg_val->reg, outval);
+			continue;
+		}
+		ccprintf("mp2964: tuning reg 0x%02x from 0x%04x to 0x%04x\n",
+			 reg_val->reg, outval, reg_val->val);
+		mp2964_write16(reg_val->reg, reg_val->val);
+		*delta += 1;
+	}
+}
+
+static int mp2964_store_user_all(void)
+{
+	const uint8_t wr = MP2964_STORE_USER_ALL;
+	const uint8_t rd = MP2964_RESTORE_USER_ALL;
+	int status;
+
+	ccprintf("%s: updating persistent settings\n", __func__);
+
+	status = i2c_xfer_unlocked(I2C_PORT_MP2964, I2C_ADDR_MP2964_FLAGS, &wr,
+				   sizeof(wr), NULL, 0, I2C_XFER_SINGLE);
+	if (status != EC_SUCCESS)
+		return status;
+
+	usleep(MP2964_STORE_WAIT_US);
+
+	status = i2c_xfer_unlocked(I2C_PORT_MP2964, I2C_ADDR_MP2964_FLAGS, &rd,
+				   sizeof(rd), NULL, 0, I2C_XFER_SINGLE);
+	if (status != EC_SUCCESS)
+		return status;
+
+	usleep(MP2964_RESTORE_WAIT_US);
+
+	return EC_SUCCESS;
+}
+
+static void mp2964_patch_rail(enum reg_page page,
+			      const struct mp2964_reg_val *page_vals, int count,
+			      int *delta)
+{
+	if (mp2964_select_page(page) != EC_SUCCESS)
+		return;
+	mp2964_write_vec16(page_vals, count, delta);
+}
+
+int mp2964_tune(const struct mp2964_reg_val *rail_a, int count_a,
+		const struct mp2964_reg_val *rail_b, int count_b)
+{
+	int tries = 2;
+	int delta;
+
+	udelay(MP2964_STARTUP_WAIT_US);
+
+	i2c_lock(I2C_PORT_MP2964, 1);
+
+	do {
+		int status;
+
+		delta = 0;
+		mp2964_patch_rail(REG_PAGE_0, rail_a, count_a, &delta);
+		mp2964_patch_rail(REG_PAGE_1, rail_b, count_b, &delta);
+		if (delta == 0)
+			break;
+
+		status = mp2964_store_user_all();
+		if (status != EC_SUCCESS)
+			ccprintf("%s: STORE_USER_ALL failed\n", __func__);
+	} while (--tries > 0);
+
+	i2c_lock(I2C_PORT_MP2964, 0);
+
+	if (delta)
+		return EC_ERROR_UNKNOWN;
+	else
+		return EC_SUCCESS;
+}
diff --git a/driver/mp2964.h b/driver/mp2964.h
new file mode 100644
index 0000000000..228cae8d5b
--- /dev/null
+++ b/driver/mp2964.h
@@ -0,0 +1,45 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_PMIC_MP2964_H
+#define __CROS_EC_PMIC_MP2964_H
+
+#define MP2964_PAGE 0x00
+#define MP2964_STORE_USER_ALL 0x15
+#define MP2964_RESTORE_USER_ALL 0x16
+#define MP2964_MFR_VOUT_TRIM 0x22
+#define MP2964_MFR_PHASE_NUM 0x29
+#define MP2964_MFR_IMON_SNS_OFFS 0x2c
+#define MP2964_IOUT_CAL_GAIN_SET 0x38
+#define MP2964_MFR_TRANS_FAST 0x3d
+#define MP2964_MFR_ALT_SET 0x3f
+#define MP2964_MFR_CONFIG2 0x48
+#define MP2964_MFR_SLOPE_SR_DCM 0x4e
+#define MP2964_MFR_ICC_MAX_SET 0x53
+#define MP2964_MFR_OCP_OVP_DAC_LIMIT 0x60
+#define MP2964_MFR_OCP_SET 0x62
+#define MP2964_PRODUCT_DATA_CODE 0x93
+#define MP2964_LOT_CODE_VR 0x94
+#define MP2964_MFR_PSI_TRIM4 0xb0
+#define MP2964_MFR_PSI_TRIM1 0xb1
+#define MP2964_MFR_PSI_TRIM3 0xb3
+#define MP2964_MFR_SLOPE_CNT_2P 0xd4
+#define MP2964_MFR_SLOPE_CNT_5P 0xe0
+#define MP2964_MFR_IMON_SVID1 0xe8
+#define MP2964_MFR_IMON_SVID2 0xe9
+#define MP2964_MFR_IMON_SVID3 0xea
+#define MP2964_MFR_IMON_SVID4 0xeb
+#define MP2964_MFR_IMON_SVID5 0xef
+#define MP2964_MFR_IMON_SVID6 0xf0
+
+struct mp2964_reg_val {
+	uint8_t reg;
+	uint16_t val;
+};
+
+int mp2964_tune(const struct mp2964_reg_val *page0, int count0,
+		const struct mp2964_reg_val *page1, int count1);
+
+#endif /* __CROS_EC_PMIC_MP2964_H */
diff --git a/driver/mp4245.c b/driver/mp4245.c
new file mode 100644
index 0000000000..a78cfbd068
--- /dev/null
+++ b/driver/mp4245.c
@@ -0,0 +1,198 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* MPS MP4245 Buck-Boost converter driver. */
+
+#include "common.h"
+#include "console.h"
+#include "i2c.h"
+#include "mp4245.h"
+#include "util.h"
+
+static int mp4245_reg16_write(int offset, int data)
+{
+	return i2c_write16(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS, offset,
+			   data);
+}
+
+int mp4245_set_voltage_out(int desired_mv)
+{
+	int vout;
+
+	/*
+	 * For a desired voltage output Vdes, Vout = Vdes * 1024. This means
+	 * there are 10 fractional and 6 integer bits. Vdes is stored in in mV
+	 * so this scaling to mV must also be accounted for.
+	 *
+	 * VOUT_COMMAND = (Vdes (mV) * 1024 / 1000) / 1024
+	 */
+	vout = (desired_mv * MP4245_VOUT_FROM_MV + (MP4245_VOUT_1V >> 1)) /
+	       MP4245_VOUT_1V;
+
+	return mp4245_reg16_write(MP4245_CMD_VOUT_COMMAND, vout);
+}
+
+int mp4245_set_current_lim(int desired_ma)
+{
+	int limit;
+
+	/* Current limit is stored as number of 50 mA steps */
+	limit = (desired_ma + (MP4245_ILIM_STEP_MA / 2)) / MP4245_ILIM_STEP_MA;
+
+	return mp4245_reg16_write(MP4245_CMD_MFR_CURRENT_LIM, limit);
+}
+
+int mp4245_votlage_out_enable(int enable)
+{
+	int cmd_val = enable ? MP4245_CMD_OPERATION_ON : 0;
+
+	return i2c_write8(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS,
+			  MP4245_CMD_OPERATION, cmd_val);
+}
+
+int mp3245_get_vbus(int *mv, int *ma)
+{
+	int vbus = 0;
+	int ibus = 0;
+	int rv;
+
+	/* Get Vbus/Ibus raw measurements */
+	rv = i2c_read16(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS,
+			MP4245_CMD_READ_VOUT, &vbus);
+	rv |= i2c_read16(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS,
+			 MP4245_CMD_READ_IOUT, &ibus);
+
+	if (rv == EC_SUCCESS) {
+		/* Convert Vbus/Ibus to mV/mA */
+		vbus = MP4245_VOUT_TO_MV(vbus);
+		ibus = MP4245_IOUT_TO_MA(ibus);
+	}
+
+	*mv = vbus;
+	*ma = ibus;
+
+	return rv;
+}
+
+struct mp4245_info {
+	uint8_t cmd;
+	uint8_t len;
+};
+
+static struct mp4245_info mp4245_cmds[] = {
+	{ MP4245_CMD_OPERATION, 1 },	    { MP4245_CMD_CLEAR_FAULTS, 1 },
+	{ MP4245_CMD_WRITE_PROTECT, 1 },    { MP4245_CMD_STORE_USER_ALL, 1 },
+	{ MP4245_CMD_RESTORE_USER_ALL, 1 }, { MP4245_CMD_VOUT_MODE, 1 },
+	{ MP4245_CMD_VOUT_COMMAND, 2 },	    { MP4245_CMD_VOUT_SCALE_LOOP, 2 },
+	{ MP4245_CMD_STATUS_BYTE, 1 },	    { MP4245_CMD_STATUS_WORD, 2 },
+	{ MP4245_CMD_STATUS_VOUT, 1 },	    { MP4245_CMD_STATUS_INPUT, 1 },
+	{ MP4245_CMD_STATUS_TEMP, 1 },	    { MP4245_CMD_STATUS_CML, 1 },
+	{ MP4245_CMD_READ_VIN, 2 },	    { MP4245_CMD_READ_VOUT, 2 },
+	{ MP4245_CMD_READ_IOUT, 2 },	    { MP4245_CMD_READ_TEMP, 2 },
+	{ MP4245_CMD_MFR_MODE_CTRL, 1 },    { MP4245_CMD_MFR_CURRENT_LIM, 1 },
+	{ MP4245_CMD_MFR_LINE_DROP, 1 },    { MP4245_CMD_MFR_OT_FAULT_LIM, 1 },
+	{ MP4245_CMD_MFR_OT_WARN_LIM, 1 },  { MP4245_CMD_MFR_CRC_ERROR, 1 },
+	{ MP4245_CMD_MFF_MTP_CFG_CODE, 1 }, { MP4245_CMD_MFR_MTP_REV_NUM, 1 },
+	{ MP4245_CMD_MFR_STATUS_MASK, 1 },
+};
+
+static void mp4245_dump_reg(void)
+{
+	int i;
+	int val;
+	int rv;
+
+	for (i = 0; i < ARRAY_SIZE(mp4245_cmds); i++) {
+		if (mp4245_cmds[i].len == 1) {
+			rv = i2c_read8(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS,
+				       mp4245_cmds[i].cmd, &val);
+		} else {
+			rv = i2c_read16(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS,
+					mp4245_cmds[i].cmd, &val);
+		}
+
+		if (!rv)
+			ccprintf("[%02x]:\t%04x\n", mp4245_cmds[i].cmd, val);
+	}
+}
+
+void mp4245_get_status(void)
+{
+	int status;
+	int on;
+	int vbus;
+	int ibus;
+	int ilim;
+	int vout;
+
+	/* Get Operation register */
+	i2c_read8(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS, MP4245_CMD_OPERATION,
+		  &on);
+	/* Vbus on/off is bit 7 */
+	on >>= 7;
+
+	/* Get status word */
+	i2c_read16(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS,
+		   MP4245_CMD_STATUS_WORD, &status);
+
+	/* Get Vbus measurement */
+	i2c_read16(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS, MP4245_CMD_READ_VOUT,
+		   &vbus);
+	vbus = MP4245_VOUT_TO_MV(vbus);
+
+	/* Get Ibus measurement */
+	i2c_read16(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS, MP4245_CMD_READ_IOUT,
+		   &ibus);
+	ibus = MP4245_IOUT_TO_MA(ibus);
+
+	/* Get Vout command (sets Vbus level) */
+	i2c_read16(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS,
+		   MP4245_CMD_VOUT_COMMAND, &vout);
+	vout = MP4245_VOUT_TO_MV(vout);
+
+	/* Get Input current limit */
+	i2c_read8(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS,
+		  MP4245_CMD_MFR_CURRENT_LIM, &ilim);
+	ilim *= MP4245_ILIM_STEP_MA;
+
+	ccprintf("mp4245 Vbus %s:\n", on ? "On" : "Off");
+	ccprintf("\tstatus = 0x%04x\n", status);
+	ccprintf("\tVout   = %d mV, Vbus = %d mV\n", vout, vbus);
+	ccprintf("\tIlim   = %d mA, Ibus = %d mA\n", ilim, ibus);
+}
+
+static int command_mp4245(int argc, const char **argv)
+{
+	char *e;
+	int val;
+
+	if (argc < 2)
+		return EC_ERROR_PARAM_COUNT;
+
+	if (!strcasecmp(argv[1], "info")) {
+		mp4245_get_status();
+	} else if (!strcasecmp(argv[1], "dump")) {
+		mp4245_dump_reg();
+	} else if (!strcasecmp(argv[1], "vbus")) {
+		if (argc < 3)
+			return EC_ERROR_PARAM_COUNT;
+		val = strtoi(argv[2], &e, 10);
+		/* If value out of bounds, turn off */
+		if (val < 0 || val > 20) {
+			return EC_ERROR_PARAM2;
+		}
+		if (val == 0) {
+			mp4245_votlage_out_enable(0);
+		} else {
+			mp4245_set_voltage_out(val * 1000);
+			mp4245_votlage_out_enable(1);
+		}
+	} else {
+		return EC_ERROR_PARAM1;
+	}
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(mp4245, command_mp4245, "<info|dump|vbus|ilim>",
+			"Turn on/off|set vbus.");
diff --git a/driver/mp4245.h b/driver/mp4245.h
new file mode 100644
index 0000000000..64fc3e9bc1
--- /dev/null
+++ b/driver/mp4245.h
@@ -0,0 +1,94 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* MPS MP4245 Buck-Boost converter driver definitions */
+
+/* I2C addresses */
+#define MP4245_I2C_ADDR_0_FLAGS 0x61 /* R1 -> GND */
+#define MP4245_I2C_ADDR_1_FLAGS 0x62 /* R1 -> 15.0k */
+#define MP4245_I2C_ADDR_2_FLAGS 0x63 /* R1 -> 25.5k */
+#define MP4245_I2C_ADDR_3_FLAGS 0x64 /* R1 -> 35.7k */
+#define MP4245_I2C_ADDR_4_FLAGS 0x65 /* R1 -> 45.3k */
+#define MP4245_I2C_ADDR_5_FLAGS 0x66 /* R1 -> 56.0k */
+#define MP4245_I2C_ADDR_6_FLAGS 0x67 /* R1 -> VCC */
+
+/* MP4245 CMD Offsets */
+#define MP4245_CMD_OPERATION 0x01
+#define MP4245_CMD_CLEAR_FAULTS 0x03
+#define MP4245_CMD_WRITE_PROTECT 0x10
+#define MP4245_CMD_STORE_USER_ALL 0x15
+#define MP4245_CMD_RESTORE_USER_ALL 0x16
+#define MP4245_CMD_VOUT_MODE 0x20
+#define MP4245_CMD_VOUT_COMMAND 0x21
+#define MP4245_CMD_VOUT_SCALE_LOOP 0x29
+#define MP4245_CMD_STATUS_BYTE 0x78
+#define MP4245_CMD_STATUS_WORD 0x79
+#define MP4245_CMD_STATUS_VOUT 0x7A
+#define MP4245_CMD_STATUS_INPUT 0x7C
+#define MP4245_CMD_STATUS_TEMP 0x7D
+#define MP4245_CMD_STATUS_CML 0x7E
+#define MP4245_CMD_READ_VIN 0x88
+#define MP4245_CMD_READ_VOUT 0x8B
+#define MP4245_CMD_READ_IOUT 0x8C
+#define MP4245_CMD_READ_TEMP 0x8D
+#define MP4245_CMD_MFR_MODE_CTRL 0xD0
+#define MP4245_CMD_MFR_CURRENT_LIM 0xD1
+#define MP4245_CMD_MFR_LINE_DROP 0xD2
+#define MP4245_CMD_MFR_OT_FAULT_LIM 0xD3
+#define MP4245_CMD_MFR_OT_WARN_LIM 0xD4
+#define MP4245_CMD_MFR_CRC_ERROR 0xD5
+#define MP4245_CMD_MFF_MTP_CFG_CODE 0xD6
+#define MP4245_CMD_MFR_MTP_REV_NUM 0xD7
+#define MP4245_CMD_MFR_STATUS_MASK 0xD8
+
+#define MP4245_CMD_OPERATION_ON BIT(7)
+
+#define MP4245_VOUT_1V BIT(10)
+#define MP4245_VOUT_FROM_MV (MP4245_VOUT_1V * MP4245_VOUT_1V / 1000)
+#define MP4245_VOUT_TO_MV(v) ((v * 1000) / MP4245_VOUT_1V)
+#define MP4245_IOUT_TO_MA(i) (((i & 0x7ff) * 1000) / BIT(6))
+#define MP4245_ILIM_STEP_MA 50
+#define MP4245_VOUT_5V_DELAY_MS 10
+
+#define MP4245_MFR_STATUS_MASK_VOUT BIT(7)
+#define MP4245_MFR_STATUS_MASK_IOUT BIT(6)
+#define MP4245_MFR_STATUS_MASK_INPUT BIT(5)
+#define MP4245_MFR_STATUS_MASK_TEMP BIT(4)
+#define MP4245_MFR_STATUS_MASK_PG_STATUS BIT(3)
+#define MP4245_MFR_STATUS_MASK_PG_ALT_EDGE BIT(2)
+#define MP4245_MFR_STATUS_MASK_OTHER BIT(1)
+#define MP4245_MFR_STATUS_MASK_UNKNOWN BIT(0)
+
+/**
+ * MP4245 set output voltage level
+ *
+ * @param desired_mv -> voltage level in mV
+ * @return i2c write result
+ */
+int mp4245_set_voltage_out(int desired_mv);
+
+/**
+ * MP4245 set output current limit
+ *
+ * @param desired_ma -> current limit in mA
+ * @return i2c write result
+ */
+int mp4245_set_current_lim(int desired_ma);
+
+/**
+ * MP4245 set output current limit
+ *
+ * @param enable -> 0 = off, else on
+ * @return i2c write result
+ */
+int mp4245_votlage_out_enable(int enable);
+
+/**
+ * MP4245 get Vbus voltage/current values
+ *
+ * @param *mv -> vbus voltage in mV
+ * @param *ma -> vbus current in mA
+ * @return i2c read results
+ */
+int mp3245_get_vbus(int *mv, int *ma);
diff --git a/driver/nfc/ctn730.c b/driver/nfc/ctn730.c
new file mode 100644
index 0000000000..61f5281994
--- /dev/null
+++ b/driver/nfc/ctn730.c
@@ -0,0 +1,794 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "ctn730.h"
+#include "gpio.h"
+#include "i2c.h"
+#include "peripheral_charger.h"
+#include "printf.h"
+#include "timer.h"
+#include "util.h"
+#include "watchdog.h"
+
+/*
+ * Configuration
+ */
+
+/* Print additional data */
+#define CTN730_DEBUG
+
+/*
+ * When ctn730 is asleep, I2C is ignored but can wake it up. I2C will be resent
+ * after this delay.
+ */
+static const int _wake_up_delay_ms = 10;
+
+/* Device detection interval */
+static const int _detection_interval_ms = 500;
+
+/* Buffer size for i2c read & write */
+#define CTN730_MESSAGE_BUFFER_SIZE 0x20
+
+/* This driver isn't compatible with big endian. */
+BUILD_ASSERT(__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__);
+
+#define CPRINTS(fmt, args...) cprints(CC_PCHG, "CTN730: " fmt, ##args)
+
+static const char *_text_instruction(uint8_t instruction)
+{
+	switch (instruction) {
+	case WLC_HOST_CTRL_RESET:
+		return "RESET";
+	case WLC_HOST_CTRL_DL_OPEN_SESSION:
+		return "DL_OPEN";
+	case WLC_HOST_CTRL_DL_COMMIT_SESSION:
+		return "DL_COMMIT";
+	case WLC_HOST_CTRL_DL_WRITE_FLASH:
+		return "DL_WRITE";
+	case WLC_HOST_CTRL_DUMP_STATUS:
+		return "DUMP_STATUS";
+	case WLC_HOST_CTRL_GENERIC_ERROR:
+		return "GENERIC_ERROR";
+	case WLC_HOST_CTRL_BIST:
+		return "BIST";
+	case WLC_CHG_CTRL_ENABLE:
+		return "ENABLE";
+	case WLC_CHG_CTRL_DISABLE:
+		return "DISABLE";
+	case WLC_CHG_CTRL_DEVICE_STATE:
+		return "DEVICE_STATE";
+	case WLC_CHG_CTRL_CHARGING_STATE:
+		return "CHARGING_STATE";
+	case WLC_CHG_CTRL_CHARGING_INFO:
+		return "CHARGING_INFO";
+	case WLC_CHG_CTRL_OPTIONAL_NDEF:
+		return "OPTIONAL_NDEF";
+	default:
+		return "UNDEF";
+	}
+}
+
+static const char *_text_message_type(uint8_t type)
+{
+	switch (type) {
+	case CTN730_MESSAGE_TYPE_COMMAND:
+		return "CMD";
+	case CTN730_MESSAGE_TYPE_RESPONSE:
+		return "RSP";
+	case CTN730_MESSAGE_TYPE_EVENT:
+		return "EVT";
+	default:
+		return "BAD";
+	}
+}
+
+static const char *_text_status_code(uint8_t code)
+{
+	switch (code) {
+	case WLC_HOST_STATUS_OK:
+		return "OK";
+	case WLC_HOST_STATUS_PARAMETER_ERROR:
+		return "PARAMETER_ERR";
+	case WLC_HOST_STATUS_STATE_ERROR:
+		return "STATE_ERR";
+	case WLC_HOST_STATUS_VALUE_ERROR:
+		return "VALUE_ERR";
+	case WLC_HOST_STATUS_REJECTED:
+		return "REJECTED";
+	case WLC_HOST_STATUS_RESOURCE_ERROR:
+		return "RESOURCE_ERR";
+	case WLC_HOST_STATUS_TXLDO_ERROR:
+		return "TXLDO_ERR";
+	case WLC_HOST_STATUS_ANTENNA_SELECTION_ERROR:
+		return "ANTENNA_SELECTION_ERR";
+	case WLC_HOST_STATUS_BIST_FAILED:
+		return "BIST_FAILED";
+	case WLC_HOST_STATUS_BIST_NO_WLC_CAP:
+		return "BIST_NO_WLC_CAP";
+	case WLC_HOST_STATUS_BIST_TXLDO_CURRENT_OVERFLOW:
+		return "BIST_TXLDO_CURRENT_OVERFLOW";
+	case WLC_HOST_STATUS_BIST_TXLDO_CURRENT_UNDERFLOW:
+		return "BIST_TXLDO_CURRENT_UNDERFLOW";
+	case WLC_HOST_STATUS_FW_VERSION_ERROR:
+		return "FW_VERSION_ERR";
+	case WLC_HOST_STATUS_FW_VERIFICATION_ERROR:
+		return "FW_VERIFICATION_ERR";
+	case WLC_HOST_STATUS_NTAG_BLOCK_PARAMETER_ERROR:
+		return "NTAG_BLOCK_PARAMETER_ERR";
+	case WLC_HOST_STATUS_NTAG_READ_ERROR:
+		return "NTAG_READ_ERR";
+	default:
+		return "UNDEF";
+	}
+}
+
+static const char *_text_reset_reason(uint8_t code)
+{
+	switch (code) {
+	case WLC_HOST_CTRL_RESET_REASON_INTENDED:
+		return "intended";
+	case WLC_HOST_CTRL_RESET_REASON_CORRUPTED:
+		return "corrupted";
+	case WLC_HOST_CTRL_RESET_REASON_UNRECOVERABLE:
+		return "unrecoverable";
+	default:
+		return "unknown";
+	}
+}
+
+static int _i2c_read(int i2c_port, uint8_t *in, int in_len)
+{
+	int rv;
+
+	memset(in, 0, in_len);
+
+	rv = i2c_xfer(i2c_port, CTN730_I2C_ADDR, NULL, 0, in, in_len);
+	if (rv) {
+		msleep(_wake_up_delay_ms);
+		rv = i2c_xfer(i2c_port, CTN730_I2C_ADDR, NULL, 0, in, in_len);
+	}
+	if (rv)
+		CPRINTS("Failed to read: %d", rv);
+
+	return rv;
+}
+
+static void _print_header(const struct ctn730_msg *msg)
+{
+	CPRINTS("%s_%s", _text_instruction(msg->instruction),
+		_text_message_type(msg->message_type));
+}
+
+static int _send_command(struct pchg *ctx, const struct ctn730_msg *cmd)
+{
+	int i2c_port = ctx->cfg->i2c_port;
+	int rv;
+
+	_print_header(cmd);
+
+	rv = i2c_xfer(i2c_port, CTN730_I2C_ADDR, (void *)cmd,
+		      sizeof(*cmd) + cmd->length, NULL, 0);
+
+	if (rv) {
+		msleep(_wake_up_delay_ms);
+		rv = i2c_xfer(i2c_port, CTN730_I2C_ADDR, (void *)cmd,
+			      sizeof(*cmd) + cmd->length, NULL, 0);
+	}
+	if (rv)
+		CPRINTS("Failed to write: %d", rv);
+
+	return rv;
+}
+
+static int ctn730_reset(struct pchg *ctx)
+{
+	gpio_set_level(GPIO_WLC_NRST_CONN, 0);
+	/*
+	 * Datasheet says minimum is 10 us. This is better not to be a sleep
+	 * especially if it's long (e.g. ~1 ms) since the PCHG state machine
+	 * may try to access the I2C bus, which is held low by ctn730.
+	 */
+	udelay(15);
+	gpio_set_level(GPIO_WLC_NRST_CONN, 1);
+	return EC_SUCCESS_IN_PROGRESS;
+}
+
+static int ctn730_init(struct pchg *ctx)
+{
+	uint8_t buf[CTN730_MESSAGE_BUFFER_SIZE];
+	struct ctn730_msg *cmd = (void *)buf;
+	int rv;
+
+	cmd->message_type = CTN730_MESSAGE_TYPE_COMMAND;
+	cmd->instruction = WLC_HOST_CTRL_RESET;
+	cmd->length = WLC_HOST_CTRL_RESET_CMD_SIZE;
+	cmd->payload[0] = ctx->mode == PCHG_MODE_DOWNLOAD ?
+				  WLC_HOST_CTRL_RESET_CMD_MODE_DOWNLOAD :
+				  WLC_HOST_CTRL_RESET_CMD_MODE_NORMAL;
+
+	/* TODO: Run 1 sec timeout timer. */
+	rv = _send_command(ctx, cmd);
+	if (rv)
+		return rv;
+
+	/* WLC-host should send EVT_HOST_CTRL_RESET_EVT shortly. */
+	return EC_SUCCESS_IN_PROGRESS;
+}
+
+static int ctn730_enable(struct pchg *ctx, bool enable)
+{
+	uint8_t buf[CTN730_MESSAGE_BUFFER_SIZE];
+	struct ctn730_msg *cmd = (void *)buf;
+	uint16_t *interval = (void *)cmd->payload;
+	int rv;
+
+	cmd->message_type = CTN730_MESSAGE_TYPE_COMMAND;
+	if (enable) {
+		cmd->instruction = WLC_CHG_CTRL_ENABLE;
+		cmd->length = WLC_CHG_CTRL_ENABLE_CMD_SIZE;
+		/* Assume core is little endian. Use htole16 for portability. */
+		*interval = _detection_interval_ms;
+	} else {
+		cmd->instruction = WLC_CHG_CTRL_DISABLE;
+		cmd->length = WLC_CHG_CTRL_DISABLE_CMD_SIZE;
+	}
+
+	rv = _send_command(ctx, cmd);
+	if (rv)
+		return rv;
+
+	return EC_SUCCESS_IN_PROGRESS;
+}
+
+static int _process_payload_response(struct pchg *ctx, struct ctn730_msg *res)
+{
+	uint8_t len = res->length;
+	uint8_t buf[CTN730_MESSAGE_BUFFER_SIZE];
+
+	if (sizeof(buf) < len) {
+		CPRINTS("Response size (%d) exceeds buffer", len);
+		return EC_ERROR_OVERFLOW;
+	}
+
+	if (len > 0) {
+		int rv = _i2c_read(ctx->cfg->i2c_port, buf, len);
+		if (rv)
+			return rv;
+		if (IS_ENABLED(CTN730_DEBUG)) {
+			char str_buf[hex_str_buf_size(len)];
+
+			snprintf_hex_buffer(str_buf, sizeof(str_buf),
+					    HEX_BUF(buf, len));
+			CPRINTS("Payload: %s", str_buf);
+		}
+	}
+
+	ctx->event = PCHG_EVENT_NONE;
+
+	/*
+	 * Messages with no payload (<len> == 0) is allowed in the spec. So,
+	 * make sure <len> is checked before reading buf[0].
+	 */
+	switch (res->instruction) {
+	case WLC_HOST_CTRL_RESET:
+		if (len != WLC_HOST_CTRL_RESET_RSP_SIZE)
+			return EC_ERROR_UNKNOWN;
+		if (buf[0] != WLC_HOST_STATUS_OK) {
+			ctx->event = PCHG_EVENT_ERROR;
+			ctx->error |= PCHG_ERROR_MASK(PCHG_ERROR_RESPONSE);
+		}
+		break;
+	case WLC_HOST_CTRL_DL_OPEN_SESSION:
+		if (len != WLC_HOST_CTRL_DL_OPEN_SESSION_RSP_SIZE)
+			return EC_ERROR_UNKNOWN;
+		if (buf[0] != WLC_HOST_STATUS_OK) {
+			CPRINTS("FW open session failed for %s",
+				_text_status_code(buf[0]));
+			ctx->event = PCHG_EVENT_UPDATE_ERROR;
+			ctx->error |= PCHG_ERROR_MASK(PCHG_ERROR_FW_VERSION);
+		} else {
+			ctx->event = PCHG_EVENT_UPDATE_OPENED;
+		}
+		break;
+	case WLC_HOST_CTRL_DL_COMMIT_SESSION:
+		if (len != WLC_HOST_CTRL_DL_COMMIT_SESSION_RSP_SIZE)
+			return EC_ERROR_UNKNOWN;
+		if (buf[0] != WLC_HOST_STATUS_OK) {
+			CPRINTS("FW commit failed for %s",
+				_text_status_code(buf[0]));
+			ctx->event = PCHG_EVENT_UPDATE_ERROR;
+			ctx->error |= PCHG_ERROR_MASK(PCHG_ERROR_INVALID_FW);
+		} else {
+			ctx->event = PCHG_EVENT_UPDATE_CLOSED;
+		}
+		break;
+	case WLC_HOST_CTRL_DL_WRITE_FLASH:
+		if (len != WLC_HOST_CTRL_DL_WRITE_FLASH_RSP_SIZE)
+			return EC_ERROR_UNKNOWN;
+		if (buf[0] != WLC_HOST_STATUS_OK) {
+			CPRINTS("FW write failed for %s",
+				_text_status_code(buf[0]));
+			ctx->event = PCHG_EVENT_UPDATE_ERROR;
+			ctx->error |= PCHG_ERROR_MASK(PCHG_ERROR_WRITE_FLASH);
+		} else {
+			ctx->event = PCHG_EVENT_UPDATE_WRITTEN;
+		}
+		break;
+	case WLC_HOST_CTRL_BIST:
+		if (len != WLC_HOST_CTRL_BIST_CMD_SIZE)
+			return EC_ERROR_UNKNOWN;
+		if (buf[0] != WLC_HOST_STATUS_OK) {
+			CPRINTS("BIST command failed for %s",
+				_text_status_code(buf[0]));
+			ctx->event = PCHG_EVENT_ERROR;
+			ctx->error |= PCHG_ERROR_MASK(PCHG_ERROR_RESPONSE);
+		}
+		break;
+	case WLC_CHG_CTRL_ENABLE:
+		if (len != WLC_CHG_CTRL_ENABLE_RSP_SIZE)
+			return EC_ERROR_UNKNOWN;
+		if (buf[0] != WLC_HOST_STATUS_OK) {
+			ctx->event = PCHG_EVENT_ERROR;
+			ctx->error |= PCHG_ERROR_MASK(PCHG_ERROR_RESPONSE);
+		} else
+			ctx->event = PCHG_EVENT_ENABLED;
+		break;
+	case WLC_CHG_CTRL_DISABLE:
+		if (len != WLC_CHG_CTRL_DISABLE_RSP_SIZE)
+			return EC_ERROR_UNKNOWN;
+		if (buf[0] != WLC_HOST_STATUS_OK) {
+			ctx->event = PCHG_EVENT_ERROR;
+			ctx->error |= PCHG_ERROR_MASK(PCHG_ERROR_RESPONSE);
+		} else
+			ctx->event = PCHG_EVENT_DISABLED;
+		break;
+	case WLC_CHG_CTRL_CHARGING_INFO:
+		if (len != WLC_CHG_CTRL_CHARGING_INFO_RSP_SIZE)
+			return EC_ERROR_UNKNOWN;
+		if (buf[0] != WLC_HOST_STATUS_OK) {
+			ctx->event = PCHG_EVENT_ERROR;
+			ctx->error |= PCHG_ERROR_MASK(PCHG_ERROR_RESPONSE);
+		} else {
+			ctx->battery_percent = buf[1];
+			ctx->event = PCHG_EVENT_CHARGE_UPDATE;
+		}
+		break;
+	default:
+		CPRINTS("Received unknown response (%d)", res->instruction);
+		break;
+	}
+
+	return EC_SUCCESS;
+}
+
+static int _process_payload_event(struct pchg *ctx, struct ctn730_msg *res)
+{
+	uint8_t len = res->length;
+	uint8_t buf[CTN730_MESSAGE_BUFFER_SIZE];
+
+	if (sizeof(buf) < len) {
+		CPRINTS("Response size (%d) exceeds buffer", len);
+		return EC_ERROR_OVERFLOW;
+	}
+
+	if (len > 0) {
+		int rv = _i2c_read(ctx->cfg->i2c_port, buf, len);
+		if (rv)
+			return rv;
+		if (IS_ENABLED(CTN730_DEBUG)) {
+			char str_buf[hex_str_buf_size(len)];
+
+			snprintf_hex_buffer(str_buf, sizeof(str_buf),
+					    HEX_BUF(buf, len));
+			CPRINTS("Payload: %s", str_buf);
+		}
+	}
+
+	ctx->event = PCHG_EVENT_NONE;
+
+	/*
+	 * Messages with no payload (<len> == 0) is allowed in the spec. So,
+	 * make sure <len> is checked before reading buf[0].
+	 */
+	switch (res->instruction) {
+	case WLC_HOST_CTRL_RESET:
+		if (len < WLC_HOST_CTRL_RESET_EVT_MIN_SIZE)
+			return EC_ERROR_INVAL;
+		if (buf[0] == WLC_HOST_CTRL_RESET_EVT_NORMAL_MODE) {
+			if (len != WLC_HOST_CTRL_RESET_EVT_NORMAL_MODE_SIZE)
+				return EC_ERROR_INVAL;
+			ctx->event = PCHG_EVENT_IN_NORMAL;
+			ctx->fw_version = (uint16_t)buf[1] << 8 | buf[2];
+			CPRINTS("Normal Mode (FW=0x%02x.%02x)", buf[1], buf[2]);
+			/*
+			 * ctn730 isn't immediately ready for i2c write after
+			 * normal mode initialization (b:178096436).
+			 */
+			msleep(5);
+		} else if (buf[0] == WLC_HOST_CTRL_RESET_EVT_DOWNLOAD_MODE) {
+			if (len != WLC_HOST_CTRL_RESET_EVT_DOWNLOAD_MODE_SIZE)
+				return EC_ERROR_INVAL;
+			CPRINTS("Download Mode (%s)",
+				_text_reset_reason(buf[1]));
+			ctx->event = PCHG_EVENT_RESET;
+			/*
+			 * CTN730 sends a reset event to notify us it entered
+			 * download mode unintentionally (e.g. corrupted FW).
+			 * In such cases, we stay in download mode to avoid an
+			 * infinite loop.
+			 *
+			 * If it's intended, we leave alone the mode, respecting
+			 * the mode set by the PCHG task.
+			 */
+			if (buf[1] != WLC_HOST_CTRL_RESET_REASON_INTENDED)
+				ctx->mode = PCHG_MODE_DOWNLOAD;
+		} else {
+			return EC_ERROR_INVAL;
+		}
+		break;
+	case WLC_HOST_CTRL_GENERIC_ERROR:
+		break;
+	case WLC_CHG_CTRL_DISABLE:
+		if (len != WLC_CHG_CTRL_DISABLE_EVT_SIZE)
+			return EC_ERROR_INVAL;
+		ctx->event = PCHG_EVENT_DISABLED;
+		break;
+	case WLC_CHG_CTRL_DEVICE_STATE:
+		if (len < WLC_CHG_CTRL_DEVICE_STATE_EVT_SIZE)
+			return EC_ERROR_INVAL;
+		switch (buf[0]) {
+		case WLC_CHG_CTRL_DEVICE_STATE_DEVICE_DOCKED:
+			if (len != WLC_CHG_CTRL_DEVICE_STATE_EVT_SIZE)
+				return EC_ERROR_INVAL;
+			ctx->event = PCHG_EVENT_DEVICE_DETECTED;
+			break;
+		case WLC_CHG_CTRL_DEVICE_STATE_DEVICE_DETECTED:
+			if (len != WLC_CHG_CTRL_DEVICE_STATE_EVT_SIZE_DETECTED)
+				return EC_ERROR_INVAL;
+			ctx->event = PCHG_EVENT_DEVICE_CONNECTED;
+			break;
+		case WLC_CHG_CTRL_DEVICE_STATE_DEVICE_DEVICE_LOST:
+		case WLC_CHG_CTRL_DEVICE_STATE_DEVICE_UNDOCKED:
+			if (len != WLC_CHG_CTRL_DEVICE_STATE_EVT_SIZE)
+				return EC_ERROR_INVAL;
+			ctx->event = PCHG_EVENT_DEVICE_LOST;
+			break;
+		case WLC_CHG_CTRL_DEVICE_STATE_DEVICE_FO_PRESENT:
+			if (len != WLC_CHG_CTRL_DEVICE_STATE_EVT_SIZE)
+				return EC_ERROR_INVAL;
+			ctx->event = PCHG_EVENT_ERROR;
+			ctx->error |=
+				PCHG_ERROR_MASK(PCHG_ERROR_FOREIGN_OBJECT);
+			break;
+		default:
+			return EC_ERROR_INVAL;
+		}
+		break;
+	case WLC_CHG_CTRL_CHARGING_STATE:
+		if (len != WLC_CHG_CTRL_CHARGING_STATE_EVT_SIZE)
+			return EC_ERROR_INVAL;
+		switch (buf[0]) {
+		case WLC_CHG_CTRL_CHARGING_STATE_CHARGE_STARTED:
+			ctx->event = PCHG_EVENT_CHARGE_STARTED;
+			break;
+		case WLC_CHG_CTRL_CHARGING_STATE_CHARGE_ENDED:
+			ctx->event = PCHG_EVENT_CHARGE_ENDED;
+			break;
+		case WLC_CHG_CTRL_CHARGING_STATE_CHARGE_STOPPED:
+			/* Includes over temp., DISABLE_CMD, device removal. */
+			ctx->event = PCHG_EVENT_CHARGE_STOPPED;
+			break;
+		default:
+			return EC_ERROR_INVAL;
+		}
+		break;
+	case WLC_CHG_CTRL_CHARGING_INFO:
+		if (len != WLC_CHG_CTRL_CHARGING_INFO_EVT_SIZE || buf[0] > 100)
+			return EC_ERROR_INVAL;
+		ctx->event = PCHG_EVENT_CHARGE_UPDATE;
+		ctx->battery_percent = buf[0];
+		break;
+	case WLC_CHG_CTRL_OPTIONAL_NDEF:
+		if (len == 0)
+			return EC_ERROR_INVAL;
+		break;
+	default:
+		CPRINTS("Received unknown event (%d)", res->instruction);
+		break;
+	}
+
+	return EC_SUCCESS;
+}
+
+static int ctn730_get_event(struct pchg *ctx)
+{
+	struct ctn730_msg res;
+	int i2c_port = ctx->cfg->i2c_port;
+	int rv;
+
+	/* Read message header */
+	rv = _i2c_read(i2c_port, (uint8_t *)&res, sizeof(res));
+	if (rv)
+		return rv;
+
+	_print_header(&res);
+
+	if (res.message_type == CTN730_MESSAGE_TYPE_RESPONSE) {
+		/* TODO: Check 1 sec timeout. */
+		return _process_payload_response(ctx, &res);
+	} else if (res.message_type == CTN730_MESSAGE_TYPE_EVENT) {
+		return _process_payload_event(ctx, &res);
+	}
+
+	CPRINTS("Invalid message type (%d)", res.message_type);
+	return EC_ERROR_UNKNOWN;
+}
+
+static int ctn730_get_soc(struct pchg *ctx)
+{
+	struct ctn730_msg cmd;
+	int rv;
+
+	cmd.message_type = CTN730_MESSAGE_TYPE_COMMAND;
+	cmd.instruction = WLC_CHG_CTRL_CHARGING_INFO;
+	cmd.length = WLC_CHG_CTRL_CHARGING_INFO_CMD_SIZE;
+
+	rv = _send_command(ctx, &cmd);
+	if (rv)
+		return rv;
+
+	return EC_SUCCESS_IN_PROGRESS;
+}
+
+static int ctn730_update_open(struct pchg *ctx)
+{
+	uint8_t buf[sizeof(struct ctn730_msg) +
+		    WLC_HOST_CTRL_DL_OPEN_SESSION_CMD_SIZE];
+	struct ctn730_msg *cmd = (void *)buf;
+	uint32_t version = ctx->update.version;
+	int rv;
+
+	cmd->message_type = CTN730_MESSAGE_TYPE_COMMAND;
+	cmd->instruction = WLC_HOST_CTRL_DL_OPEN_SESSION;
+	cmd->length = WLC_HOST_CTRL_DL_OPEN_SESSION_CMD_SIZE;
+	cmd->payload[0] = (version >> 8) & 0xff;
+	cmd->payload[1] = version & 0xff;
+
+	rv = _send_command(ctx, cmd);
+	if (rv)
+		return rv;
+
+	return EC_SUCCESS_IN_PROGRESS;
+}
+
+static int ctn730_update_write(struct pchg *ctx)
+{
+	uint8_t buf[sizeof(struct ctn730_msg) +
+		    WLC_HOST_CTRL_DL_WRITE_FLASH_CMD_SIZE];
+	struct ctn730_msg *cmd = (void *)buf;
+	uint32_t *a = (void *)cmd->payload;
+	uint8_t *d = (void *)&cmd->payload[CTN730_FLASH_ADDR_SIZE];
+	int rv;
+
+	/* Address is 3 bytes. FW size must be a multiple of 128 bytes. */
+	if (ctx->update.addr & GENMASK(31, 24) ||
+	    ctx->update.size != WLC_HOST_CTRL_DL_WRITE_FLASH_BLOCK_SIZE)
+		return EC_ERROR_INVAL;
+
+	cmd->message_type = CTN730_MESSAGE_TYPE_COMMAND;
+	cmd->instruction = WLC_HOST_CTRL_DL_WRITE_FLASH;
+	cmd->length = WLC_HOST_CTRL_DL_WRITE_FLASH_CMD_SIZE;
+
+	/* 4th byte will be overwritten by memcpy below. */
+	*a = ctx->update.addr;
+
+	/* Store data in payload with 0-padding for short blocks. */
+	memset(d, 0, WLC_HOST_CTRL_DL_WRITE_FLASH_BLOCK_SIZE);
+	memcpy(d, ctx->update.data, ctx->update.size);
+
+	rv = _send_command(ctx, cmd);
+	if (rv)
+		return rv;
+
+	return EC_SUCCESS_IN_PROGRESS;
+}
+
+static int ctn730_update_close(struct pchg *ctx)
+{
+	uint8_t buf[sizeof(struct ctn730_msg) +
+		    WLC_HOST_CTRL_DL_COMMIT_SESSION_CMD_SIZE];
+	struct ctn730_msg *cmd = (void *)buf;
+	uint32_t *crc32 = (void *)cmd->payload;
+	int rv;
+
+	cmd->message_type = CTN730_MESSAGE_TYPE_COMMAND;
+	cmd->instruction = WLC_HOST_CTRL_DL_COMMIT_SESSION;
+	cmd->length = WLC_HOST_CTRL_DL_COMMIT_SESSION_CMD_SIZE;
+	*crc32 = ctx->update.crc32;
+
+	rv = _send_command(ctx, cmd);
+	if (rv)
+		return rv;
+
+	return EC_SUCCESS_IN_PROGRESS;
+}
+
+static int ctn730_passthru(struct pchg *ctx, bool enable)
+{
+	ctx->mode = enable ? PCHG_MODE_PASSTHRU : PCHG_MODE_NORMAL;
+
+	return EC_SUCCESS;
+}
+
+static int ctn730_bist(struct pchg *ctx, uint8_t test_id)
+{
+	uint8_t buf[sizeof(struct ctn730_msg) + WLC_HOST_CTRL_BIST_CMD_SIZE];
+	struct ctn730_msg *cmd = (void *)buf;
+	uint8_t *id = cmd->payload;
+	int rv;
+
+	cmd->message_type = CTN730_MESSAGE_TYPE_COMMAND;
+	cmd->instruction = WLC_HOST_CTRL_BIST;
+	*id = test_id;
+
+	switch (test_id) {
+	case PCHG_BIST_CMD_RF_CHARGE_ON:
+		cmd->length = 1;
+		break;
+	default:
+		return EC_ERROR_UNIMPLEMENTED;
+	}
+
+	rv = _send_command(ctx, cmd);
+	if (rv)
+		return rv;
+
+	return EC_SUCCESS_IN_PROGRESS;
+}
+
+/**
+ * Send command in blocking loop
+ *
+ * @param ctx     PCHG port context
+ * @param buf     [IN] Command header and payload to send.
+ *                [OUT] Response header and payload received.
+ * @param buf_len Size of <buf>
+ * @return        enum ec_error_list
+ */
+static int _send_command_blocking(struct pchg *ctx, uint8_t *buf, int buf_len)
+{
+	int i2c_port = ctx->cfg->i2c_port;
+	int irq_pin = ctx->cfg->irq_pin;
+	struct ctn730_msg *cmd = (void *)buf;
+	struct ctn730_msg *res = (void *)buf;
+	timestamp_t deadline;
+	int rv;
+
+	gpio_disable_interrupt(irq_pin);
+
+	rv = _send_command(ctx, cmd);
+	if (rv)
+		goto exit;
+
+	deadline.val = get_time().val + CTN730_COMMAND_TIME_OUT;
+
+	/* Busy loop */
+	while (gpio_get_level(irq_pin) == 0 && !rv) {
+		udelay(1 * MSEC);
+		rv = timestamp_expired(deadline, NULL);
+		watchdog_reload();
+	}
+
+	if (rv) {
+		ccprintf("Response timeout\n");
+		rv = EC_ERROR_TIMEOUT;
+		goto exit;
+	}
+
+	rv = _i2c_read(i2c_port, buf, sizeof(*res));
+	if (rv)
+		goto exit;
+
+	_print_header(res);
+
+	if (sizeof(*res) + res->length > buf_len) {
+		ccprintf("RSP size exceeds buffer\n");
+		rv = EC_ERROR_OVERFLOW;
+		goto exit;
+	}
+
+	rv = _i2c_read(i2c_port, res->payload, res->length);
+	if (rv)
+		goto exit;
+
+exit:
+	gpio_clear_pending_interrupt(irq_pin);
+	gpio_enable_interrupt(irq_pin);
+
+	return rv;
+}
+
+const struct pchg_drv ctn730_drv = {
+	.reset = ctn730_reset,
+	.init = ctn730_init,
+	.enable = ctn730_enable,
+	.get_event = ctn730_get_event,
+	.get_soc = ctn730_get_soc,
+	.update_open = ctn730_update_open,
+	.update_write = ctn730_update_write,
+	.update_close = ctn730_update_close,
+	.passthru = ctn730_passthru,
+	.bist = ctn730_bist,
+};
+
+static int cc_ctn730(int argc, const char **argv)
+{
+	int port;
+	char *end;
+	uint8_t buf[CTN730_MESSAGE_BUFFER_SIZE];
+	struct ctn730_msg *cmd = (void *)buf;
+	struct ctn730_msg *res = (void *)buf;
+	int rv;
+
+	if (argc < 4)
+		return EC_ERROR_PARAM_COUNT;
+
+	port = strtoi(argv[1], &end, 0);
+	if (*end || port < 0 || board_get_pchg_count() <= port)
+		return EC_ERROR_PARAM2;
+
+	cmd->message_type = CTN730_MESSAGE_TYPE_COMMAND;
+
+	if (!strcasecmp(argv[2], "dump")) {
+		int tag = strtoi(argv[3], &end, 0);
+
+		if (*end || tag < 0 || 0x07 < tag)
+			return EC_ERROR_PARAM3;
+
+		cmd->instruction = WLC_HOST_CTRL_DUMP_STATUS;
+		cmd->length = WLC_HOST_CTRL_DUMP_STATUS_CMD_SIZE;
+		cmd->payload[0] = tag;
+	} else if (!strcasecmp(argv[2], "bist")) {
+		int id = strtoi(argv[3], &end, 0);
+
+		if (*end || id < 0)
+			return EC_ERROR_PARAM3;
+
+		cmd->instruction = WLC_HOST_CTRL_BIST;
+		cmd->payload[0] = id;
+
+		switch (id) {
+		case WLC_BIST_CMD_RF_SWITCH_ON:
+		case WLC_BIST_CMD_RF_SWITCH_OFF:
+			/* Tx driver configuration is not implemented. */
+			cmd->length = 1;
+			break;
+		case WLC_BIST_CMD_DEVICE_ACTIVATION_TEST:
+			cmd->length = 1;
+			break;
+		default:
+			return EC_ERROR_PARAM3;
+		}
+	} else {
+		return EC_ERROR_PARAM2;
+	}
+
+	rv = _send_command_blocking(&pchgs[port], buf, sizeof(buf));
+	if (rv)
+		return rv;
+
+	ccprintf("STATUS_%s\n", _text_status_code(res->payload[0]));
+	hexdump(res->payload, res->length);
+
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(ctn730, cc_ctn730,
+			"<port> dump/bist <tag/id>"
+			"\n\t<port> dump <tag>"
+			"\n\t<port> bist <test_id>",
+			"Control ctn730");
diff --git a/driver/nfc/ctn730.h b/driver/nfc/ctn730.h
new file mode 100644
index 0000000000..80a7f134d8
--- /dev/null
+++ b/driver/nfc/ctn730.h
@@ -0,0 +1,136 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_CTN730_H
+#define __CROS_EC_CTN730_H
+
+#define CTN730_I2C_ADDR 0x28
+
+/* Size of flash address space in bytes */
+#define CTN730_FLASH_ADDR_SIZE 3
+
+/* All commands are guaranteed to finish within 1 second. */
+#define CTN730_COMMAND_TIME_OUT (1 * SECOND)
+
+/* Message Types */
+#define CTN730_MESSAGE_TYPE_COMMAND 0b00
+#define CTN730_MESSAGE_TYPE_RESPONSE 0b01
+#define CTN730_MESSAGE_TYPE_EVENT 0b10
+
+/* Instruction Codes */
+#define WLC_HOST_CTRL_RESET 0b000000
+#define WLC_HOST_CTRL_DL_OPEN_SESSION 0b000011
+#define WLC_HOST_CTRL_DL_COMMIT_SESSION 0b000100
+#define WLC_HOST_CTRL_DL_WRITE_FLASH 0b000101
+#define WLC_HOST_CTRL_DUMP_STATUS 0b001100
+#define WLC_HOST_CTRL_GENERIC_ERROR 0b001111
+#define WLC_HOST_CTRL_BIST 0b000110
+#define WLC_CHG_CTRL_ENABLE 0b010000
+#define WLC_CHG_CTRL_DISABLE 0b010001
+#define WLC_CHG_CTRL_DEVICE_STATE 0b010010
+#define WLC_CHG_CTRL_CHARGING_STATE 0b010100
+#define WLC_CHG_CTRL_CHARGING_INFO 0b010101
+#define WLC_CHG_CTRL_OPTIONAL_NDEF 0b011111
+
+/* WLC_HOST_CTRL_RESET constants */
+#define WLC_HOST_CTRL_RESET_CMD_SIZE 1
+#define WLC_HOST_CTRL_RESET_RSP_SIZE 1
+#define WLC_HOST_CTRL_RESET_EVT_NORMAL_MODE 0x00
+#define WLC_HOST_CTRL_RESET_EVT_NORMAL_MODE_SIZE 3
+#define WLC_HOST_CTRL_RESET_EVT_DOWNLOAD_MODE 0x01
+#define WLC_HOST_CTRL_RESET_EVT_DOWNLOAD_MODE_SIZE 2
+#define WLC_HOST_CTRL_RESET_REASON_INTENDED 0x00
+#define WLC_HOST_CTRL_RESET_REASON_CORRUPTED 0x01
+#define WLC_HOST_CTRL_RESET_REASON_UNRECOVERABLE 0x02
+#define WLC_HOST_CTRL_RESET_CMD_MODE_NORMAL 0x00
+#define WLC_HOST_CTRL_RESET_CMD_MODE_DOWNLOAD 0x01
+#define WLC_HOST_CTRL_RESET_EVT_MIN_SIZE \
+	WLC_HOST_CTRL_RESET_EVT_DOWNLOAD_MODE_SIZE
+
+/* WLC_HOST_CTRL_DL_* constants */
+#define WLC_HOST_CTRL_DL_OPEN_SESSION_CMD_SIZE 2
+#define WLC_HOST_CTRL_DL_OPEN_SESSION_RSP_SIZE 1
+#define WLC_HOST_CTRL_DL_WRITE_FLASH_BLOCK_SIZE 128
+#define WLC_HOST_CTRL_DL_WRITE_FLASH_CMD_SIZE \
+	(CTN730_FLASH_ADDR_SIZE + WLC_HOST_CTRL_DL_WRITE_FLASH_BLOCK_SIZE)
+#define WLC_HOST_CTRL_DL_WRITE_FLASH_RSP_SIZE 1
+#define WLC_HOST_CTRL_DL_COMMIT_SESSION_CMD_SIZE 4
+#define WLC_HOST_CTRL_DL_COMMIT_SESSION_RSP_SIZE 1
+
+/* WLC_HOST_CTRL_BIST constants */
+#define WLC_HOST_CTRL_BIST_CMD_SIZE 1
+
+/* WLC_CHG_CTRL_ENABLE constants */
+#define WLC_CHG_CTRL_ENABLE_CMD_SIZE 2
+#define WLC_CHG_CTRL_ENABLE_RSP_SIZE 1
+
+/* WLC_CHG_CTRL_DISABLE constants */
+#define WLC_CHG_CTRL_DISABLE_CMD_SIZE 0
+#define WLC_CHG_CTRL_DISABLE_RSP_SIZE 1
+#define WLC_CHG_CTRL_DISABLE_EVT_SIZE 1
+
+/* WLC_CHG_CTRL_DEVICE_STATE constants */
+#define WLC_CHG_CTRL_DEVICE_STATE_DEVICE_DETECTED 0x00
+#define WLC_CHG_CTRL_DEVICE_STATE_DEVICE_DEACTIVATED 0x01
+#define WLC_CHG_CTRL_DEVICE_STATE_DEVICE_DEVICE_LOST 0x02
+#define WLC_CHG_CTRL_DEVICE_STATE_DEVICE_DEVICE_BAD_VERSION 0x03
+#define WLC_CHG_CTRL_DEVICE_STATE_DEVICE_DOCKED 0x04
+#define WLC_CHG_CTRL_DEVICE_STATE_DEVICE_UNDOCKED 0x05
+#define WLC_CHG_CTRL_DEVICE_STATE_DEVICE_FO_PRESENT 0x06
+#define WLC_CHG_CTRL_DEVICE_STATE_DEVICE_BATTERY_FULL 0x07
+#define WLC_CHG_CTRL_DEVICE_STATE_DEVICE_CHARGE_FAILURE 0x08
+#define WLC_CHG_CTRL_DEVICE_STATE_DEVICE_NDEF_MODE 0x0A
+#define WLC_CHG_CTRL_DEVICE_STATE_DEVICE_LISTENER_OT 0xFA
+#define WLC_CHG_CTRL_DEVICE_STATE_EVT_SIZE_DETECTED 8
+#define WLC_CHG_CTRL_DEVICE_STATE_EVT_SIZE 1
+
+/* WLC_CHG_CTRL_CHARGING_STATE constants */
+#define WLC_CHG_CTRL_CHARGING_STATE_CHARGE_STARTED 0x00
+#define WLC_CHG_CTRL_CHARGING_STATE_CHARGE_ENDED 0x01
+#define WLC_CHG_CTRL_CHARGING_STATE_CHARGE_STOPPED 0x02
+#define WLC_CHG_CTRL_CHARGING_STATE_EVT_SIZE 1
+
+/* WLC_HOST_CTRL_DUMP_STATUS constants */
+#define WLC_HOST_CTRL_DUMP_STATUS_CMD_SIZE 1
+
+/* WLC_CHG_CTRL_CHARGING_INFO constants */
+#define WLC_CHG_CTRL_CHARGING_INFO_CMD_SIZE 0
+#define WLC_CHG_CTRL_CHARGING_INFO_RSP_SIZE 2
+#define WLC_CHG_CTRL_CHARGING_INFO_EVT_SIZE 5
+
+/* WLC_HOST_CTRL_BIST_CMD constants */
+#define WLC_BIST_RSP_SIZE 1
+#define WLC_BIST_CMD_RF_SWITCH_ON 0x01
+#define WLC_BIST_CMD_RF_SWITCH_OFF 0x02
+#define WLC_BIST_CMD_DEVICE_ACTIVATION_TEST 0x04
+
+/* Status Codes */
+enum wlc_host_status {
+	WLC_HOST_STATUS_OK = 0x00,
+	WLC_HOST_STATUS_PARAMETER_ERROR = 0x01,
+	WLC_HOST_STATUS_STATE_ERROR = 0x02,
+	WLC_HOST_STATUS_VALUE_ERROR = 0x03,
+	WLC_HOST_STATUS_REJECTED = 0x04,
+	WLC_HOST_STATUS_RESOURCE_ERROR = 0x10,
+	WLC_HOST_STATUS_TXLDO_ERROR = 0x11,
+	WLC_HOST_STATUS_ANTENNA_SELECTION_ERROR = 0x12,
+	WLC_HOST_STATUS_BIST_FAILED = 0x20,
+	WLC_HOST_STATUS_BIST_NO_WLC_CAP = 0x21,
+	WLC_HOST_STATUS_BIST_TXLDO_CURRENT_OVERFLOW = 0x22,
+	WLC_HOST_STATUS_BIST_TXLDO_CURRENT_UNDERFLOW = 0x23,
+	WLC_HOST_STATUS_FW_VERSION_ERROR = 0x30,
+	WLC_HOST_STATUS_FW_VERIFICATION_ERROR = 0x31,
+	WLC_HOST_STATUS_NTAG_BLOCK_PARAMETER_ERROR = 0x32,
+	WLC_HOST_STATUS_NTAG_READ_ERROR = 0x33,
+};
+
+struct ctn730_msg {
+	uint8_t instruction : 6;
+	uint8_t message_type : 2;
+	uint8_t length;
+	uint8_t payload[];
+} __packed;
+
+#endif /* __CROS_EC_CTN730_H */
diff --git a/driver/nvidia_gpu.c b/driver/nvidia_gpu.c
new file mode 100644
index 0000000000..ff6e5fe39b
--- /dev/null
+++ b/driver/nvidia_gpu.c
@@ -0,0 +1,161 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Nvidia GPU D-Notify driver
+ */
+
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "nvidia_gpu.h"
+#include "throttle_ap.h"
+#include "timer.h"
+
+#include <stddef.h>
+
+#define CPRINTS(fmt, args...) cprints(CC_GPU, "GPU: " fmt, ##args)
+#define CPRINTF(fmt, args...) cprintf(CC_GPU, "GPU: " fmt, ##args)
+
+test_export_static enum d_notify_level d_notify_level = D_NOTIFY_1;
+test_export_static bool policy_initialized = false;
+test_export_static const struct d_notify_policy *d_notify_policy = NULL;
+
+void nvidia_gpu_init_policy(const struct d_notify_policy *policy)
+{
+	if (policy) {
+		d_notify_policy = policy;
+		policy_initialized = true;
+	}
+}
+
+void nvidia_gpu_over_temp(int assert)
+{
+	uint8_t *memmap_gpu = (uint8_t *)host_get_memmap(EC_MEMMAP_GPU);
+
+	if (assert)
+		*memmap_gpu |= EC_MEMMAP_GPU_OVERT_BIT;
+	else
+		*memmap_gpu &= ~EC_MEMMAP_GPU_OVERT_BIT;
+
+	host_set_single_event(EC_HOST_EVENT_GPU);
+}
+
+static void set_d_notify_level(enum d_notify_level level)
+{
+	uint8_t *memmap_gpu = (uint8_t *)host_get_memmap(EC_MEMMAP_GPU);
+
+	if (level == d_notify_level)
+		return;
+
+	d_notify_level = level;
+	*memmap_gpu = (*memmap_gpu & ~EC_MEMMAP_GPU_D_NOTIFY_MASK) |
+		      d_notify_level;
+	host_set_single_event(EC_HOST_EVENT_GPU);
+	CPRINTS("Set D-notify level to D%c", ('1' + (int)d_notify_level));
+}
+
+static void evaluate_d_notify_level(void)
+{
+	enum d_notify_level lvl;
+	const struct d_notify_policy *policy = d_notify_policy;
+
+	/*
+	 * We don't need to care about 'transitioning to S0' because throttling
+	 * is unlikely required when the system is about to start.
+	 */
+	if (!chipset_in_state(CHIPSET_STATE_ON))
+		return;
+
+	if (!policy_initialized) {
+		CPRINTS("WARN: %s called before policies are set.", __func__);
+		return;
+	}
+
+	if (extpower_is_present()) {
+		const int watts = charge_manager_get_power_limit_uw() / 1000000;
+
+		for (lvl = D_NOTIFY_1; lvl <= D_NOTIFY_5; lvl++) {
+			if (policy[lvl].power_source != D_NOTIFY_AC &&
+			    policy[lvl].power_source != D_NOTIFY_AC_DC)
+				continue;
+
+			if (policy[lvl].power_source == D_NOTIFY_AC) {
+				if (watts >= policy[lvl].ac.min_charger_watts) {
+					set_d_notify_level(lvl);
+					break;
+				}
+			} else {
+				set_d_notify_level(lvl);
+				break;
+			}
+		}
+	} else {
+		const int soc = charge_get_percent();
+
+		for (lvl = D_NOTIFY_5; lvl >= D_NOTIFY_1; lvl--) {
+			if (policy[lvl].power_source == D_NOTIFY_DC) {
+				if (soc <= policy[lvl].dc.max_battery_soc) {
+					set_d_notify_level(lvl);
+					break;
+				}
+			} else if (policy[lvl].power_source == D_NOTIFY_AC_DC) {
+				set_d_notify_level(lvl);
+				break;
+			}
+		}
+	}
+}
+
+static void disable_gpu_acoff(void)
+{
+	gpio_set_level(GPIO_NVIDIA_GPU_ACOFF_ODL, 1);
+	evaluate_d_notify_level();
+}
+DECLARE_DEFERRED(disable_gpu_acoff);
+
+static void handle_battery_soc_change(void)
+{
+	evaluate_d_notify_level();
+}
+DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, handle_battery_soc_change,
+	     HOOK_PRIO_DEFAULT);
+
+/*
+ * This function enables and disables both hard and soft throttles. (Thus,
+ * <type> has no meaning.).
+ *
+ * When throttling, it hard-throttles the GPU and sets the D-level to D5. It
+ * also schedules a deferred call to disable the hard throttle. So, it's not
+ * necessary to call it for unthrottling.
+ *
+ * Currently, it's upto each board when this is called. For example, it can be
+ * called from board_set_active_charge_port since board_set_active_charge_port
+ * is called whenever (and prior to) active port or active supplier or both
+ * changes.
+ */
+void throttle_gpu(enum throttle_level level, enum throttle_type type, /* not
+									 used */
+		  enum throttle_sources source)
+{
+	if (level == THROTTLE_ON) {
+		/* Cancel pending deferred call. */
+		hook_call_deferred(&disable_gpu_acoff_data, -1);
+		/* Toggle hardware throttle immediately. */
+		gpio_set_level(GPIO_NVIDIA_GPU_ACOFF_ODL, 0);
+		/*
+		 * Switch to the lowest (D5) first then move up as the situation
+		 * improves.
+		 */
+		set_d_notify_level(D_NOTIFY_5);
+		hook_call_deferred(&disable_gpu_acoff_data,
+				   NVIDIA_GPU_ACOFF_DURATION);
+	} else {
+		disable_gpu_acoff();
+	}
+}
diff --git a/driver/nvidia_gpu.h b/driver/nvidia_gpu.h
new file mode 100644
index 0000000000..9d87914a91
--- /dev/null
+++ b/driver/nvidia_gpu.h
@@ -0,0 +1,67 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Nvidia GPU D-Notify driver header file
+ */
+
+#ifndef DRIVER_NVIDIA_GPU_H
+#define DRIVER_NVIDIA_GPU_H
+
+#define NVIDIA_GPU_ACOFF_DURATION (100 * MSEC)
+
+enum d_notify_level {
+	D_NOTIFY_1 = 0,
+	D_NOTIFY_2,
+	D_NOTIFY_3,
+	D_NOTIFY_4,
+	D_NOTIFY_5,
+	D_NOTIFY_COUNT,
+};
+
+enum d_notify_policy_type {
+	/* High- or low-power A/C */
+	D_NOTIFY_AC,
+	/* Too low of A/C to still charge or DC with high battery SOC */
+	D_NOTIFY_AC_DC,
+	/* DC with medium or low battery SOC */
+	D_NOTIFY_DC,
+};
+
+struct d_notify_policy {
+	enum d_notify_policy_type power_source;
+	union {
+		struct {
+			unsigned int min_charger_watts;
+		} ac;
+		struct {
+			unsigned int max_battery_soc;
+		} dc;
+	};
+};
+
+#define AC_ATLEAST_W(W)                                                   \
+	{                                                                 \
+		.power_source = D_NOTIFY_AC, .ac.min_charger_watts = (W), \
+	}
+
+#define AC_DC                                   \
+	{                                       \
+		.power_source = D_NOTIFY_AC_DC, \
+	}
+
+#define DC_ATMOST_SOC(S)                                                \
+	{                                                               \
+		.power_source = D_NOTIFY_DC, .dc.max_battery_soc = (S), \
+	}
+
+void nvidia_gpu_init_policy(const struct d_notify_policy *policies);
+
+/**
+ * Notify the host of assertion or deassertion of GPU over temperature.
+ *
+ * @param assert  True for assert. False for deassert.
+ */
+void nvidia_gpu_over_temp(int assert);
+
+#endif /* DRIVER_NVIDIA_GPU_H */
diff --git a/driver/pmic_bd99992gw.h b/driver/pmic_bd99992gw.h
index e00ea1d252..9229b62f48 100644
--- a/driver/pmic_bd99992gw.h
+++ b/driver/pmic_bd99992gw.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,22 +10,22 @@
 
 #include "temp_sensor/bd99992gw.h"
 
-#define BD99992GW_REG_PWRSRCINT		0x04
-#define BD99992GW_REG_RESETIRQ1		0x08
-#define BD99992GW_REG_PBCONFIG		0x14
-#define BD99992GW_REG_PWRSTAT1		0x16
-#define BD99992GW_REG_PWRSTAT2		0x17
-#define BD99992GW_REG_VCCIOCNT		0x30
-#define BD99992GW_REG_V5ADS3CNT		0x31
-#define BD99992GW_REG_V18ACNT		0x34
-#define BD99992GW_REG_V100ACNT		0x37
-#define BD99992GW_REG_V085ACNT		0x38
-#define BD99992GW_REG_VRMODECTRL	0x3b
-#define BD99992GW_REG_DISCHGCNT1	0x3c
-#define BD99992GW_REG_DISCHGCNT2	0x3d
-#define BD99992GW_REG_DISCHGCNT3	0x3e
-#define BD99992GW_REG_DISCHGCNT4	0x3f
-#define BD99992GW_REG_SDWNCTRL		0x49
-#define BD99992GW_SDWNCTRL_SWDN		BIT(0) /* SWDN mask */
+#define BD99992GW_REG_PWRSRCINT 0x04
+#define BD99992GW_REG_RESETIRQ1 0x08
+#define BD99992GW_REG_PBCONFIG 0x14
+#define BD99992GW_REG_PWRSTAT1 0x16
+#define BD99992GW_REG_PWRSTAT2 0x17
+#define BD99992GW_REG_VCCIOCNT 0x30
+#define BD99992GW_REG_V5ADS3CNT 0x31
+#define BD99992GW_REG_V18ACNT 0x34
+#define BD99992GW_REG_V100ACNT 0x37
+#define BD99992GW_REG_V085ACNT 0x38
+#define BD99992GW_REG_VRMODECTRL 0x3b
+#define BD99992GW_REG_DISCHGCNT1 0x3c
+#define BD99992GW_REG_DISCHGCNT2 0x3d
+#define BD99992GW_REG_DISCHGCNT3 0x3e
+#define BD99992GW_REG_DISCHGCNT4 0x3f
+#define BD99992GW_REG_SDWNCTRL 0x49
+#define BD99992GW_SDWNCTRL_SWDN BIT(0) /* SWDN mask */
 
-#endif  /* __CROS_EC_PMIC_BD99992GW_H */
+#endif /* __CROS_EC_PMIC_BD99992GW_H */
diff --git a/driver/pmic_tps650x30.h b/driver/pmic_tps650x30.h
index f03bef5f05..f346fba380 100644
--- a/driver/pmic_tps650x30.h
+++ b/driver/pmic_tps650x30.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -9,29 +9,29 @@
 #define __CROS_EC_PMIC_TPS650X30_H
 
 /* I2C interface */
-#define TPS650X30_I2C_ADDR1_FLAGS	0x30
-#define TPS650X30_I2C_ADDR2_FLAGS	0x32
-#define TPS650X30_I2C_ADDR3_FLAGS	0x34
+#define TPS650X30_I2C_ADDR1_FLAGS 0x30
+#define TPS650X30_I2C_ADDR2_FLAGS 0x32
+#define TPS650X30_I2C_ADDR3_FLAGS 0x34
 
 /* TPS650X30 registers */
-#define TPS650X30_REG_VENDORID		0x00
-#define TPS650X30_REG_PBCONFIG		0x14
-#define TPS650X30_REG_PGMASK1		0x18
-#define TPS650X30_REG_VCCIOCNT		0x30
-#define TPS650X30_REG_V5ADS3CNT		0x31
-#define TPS650X30_REG_V33ADSWCNT	0x32
-#define TPS650X30_REG_V18ACNT		0x34
-#define TPS650X30_REG_V1P2UCNT		0x36
-#define TPS650X30_REG_V100ACNT		0x37
-#define TPS650X30_REG_VRMODECTRL	0x3B
-#define TPS650X30_REG_DISCHCNT1		0x3C
-#define TPS650X30_REG_DISCHCNT2		0x3D
-#define TPS650X30_REG_DISCHCNT3		0x3E
-#define TPS650X30_REG_DISCHCNT4		0x3F
-#define TPS650X30_REG_PWFAULT_MASK1	0xE5
-#define TPS650X30_REG_PWFAULT_MASK2	0xE6
+#define TPS650X30_REG_VENDORID 0x00
+#define TPS650X30_REG_PBCONFIG 0x14
+#define TPS650X30_REG_PGMASK1 0x18
+#define TPS650X30_REG_VCCIOCNT 0x30
+#define TPS650X30_REG_V5ADS3CNT 0x31
+#define TPS650X30_REG_V33ADSWCNT 0x32
+#define TPS650X30_REG_V18ACNT 0x34
+#define TPS650X30_REG_V1P2UCNT 0x36
+#define TPS650X30_REG_V100ACNT 0x37
+#define TPS650X30_REG_VRMODECTRL 0x3B
+#define TPS650X30_REG_DISCHCNT1 0x3C
+#define TPS650X30_REG_DISCHCNT2 0x3D
+#define TPS650X30_REG_DISCHCNT3 0x3E
+#define TPS650X30_REG_DISCHCNT4 0x3F
+#define TPS650X30_REG_PWFAULT_MASK1 0xE5
+#define TPS650X30_REG_PWFAULT_MASK2 0xE6
 
 /* TPS650X30 register values */
-#define TPS650X30_VENDOR_ID		0x22
+#define TPS650X30_VENDOR_ID 0x22
 
-#endif	/* __CROS_EC_PMIC_TPS650X30_H */
+#endif /* __CROS_EC_PMIC_TPS650X30_H */
diff --git a/driver/ppc/aoz1380.c b/driver/ppc/aoz1380.c
index c4d3cc6056..27d55cab51 100644
--- a/driver/ppc/aoz1380.c
+++ b/driver/ppc/aoz1380.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,41 +14,35 @@
 #include "atomic.h"
 #include "common.h"
 #include "console.h"
-#include "driver/ppc/aoz1380.h"
 #include "hooks.h"
+#include "ppc/aoz1380_public.h"
 #include "system.h"
-#include "tcpm.h"
+#include "tcpm/tcpm.h"
 #include "usb_pd.h"
 #include "usb_pd_tcpc.h"
 #include "usbc_ppc.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
-static uint32_t irq_pending; /* Bitmask of ports signaling an interrupt. */
+static atomic_t irq_pending; /* Bitmask of ports signaling an interrupt. */
 
-#define AOZ1380_FLAGS_SOURCE_ENABLED    BIT(0)
-#define AOZ1380_FLAGS_SINK_ENABLED      BIT(1)
+#define AOZ1380_FLAGS_SOURCE_ENABLED BIT(0)
+#define AOZ1380_FLAGS_SINK_ENABLED BIT(1)
 #define AOZ1380_FLAGS_INT_ON_DISCONNECT BIT(2)
-static uint32_t flags[CONFIG_USB_PD_PORT_MAX_COUNT];
+static atomic_t flags[CONFIG_USB_PD_PORT_MAX_COUNT];
 
-#define AOZ1380_SET_FLAG(port, flag) deprecated_atomic_or(&flags[port], (flag))
-#define AOZ1380_CLR_FLAG(port, flag) \
-	deprecated_atomic_clear_bits(&flags[port], (flag))
+#define AOZ1380_SET_FLAG(port, flag) atomic_or(&flags[port], (flag))
+#define AOZ1380_CLR_FLAG(port, flag) atomic_clear_bits(&flags[port], (flag))
 
 static int aoz1380_init(int port)
 {
-	int rv;
-	bool is_sinking, is_sourcing;
-
 	flags[port] = 0;
 
-	rv = tcpm_get_snk_ctrl(port, &is_sinking);
-	if (rv == EC_SUCCESS && is_sinking)
+	if (tcpm_get_snk_ctrl(port))
 		AOZ1380_SET_FLAG(port, AOZ1380_FLAGS_SINK_ENABLED);
 
-	rv = tcpm_get_src_ctrl(port, &is_sourcing);
-	if (rv == EC_SUCCESS && is_sourcing)
+	if (tcpm_get_src_ctrl(port))
 		AOZ1380_SET_FLAG(port, AOZ1380_FLAGS_SOURCE_ENABLED);
 
 	return EC_SUCCESS;
@@ -144,7 +138,7 @@ static void aoz1380_handle_interrupt(int port)
 static void aoz1380_irq_deferred(void)
 {
 	int i;
-	uint32_t pending = deprecated_atomic_read_clear(&irq_pending);
+	uint32_t pending = atomic_clear(&irq_pending);
 
 	for (i = 0; i < board_get_usb_pd_port_count(); i++)
 		if (BIT(i) & pending)
@@ -154,7 +148,7 @@ DECLARE_DEFERRED(aoz1380_irq_deferred);
 
 void aoz1380_interrupt(int port)
 {
-	deprecated_atomic_or(&irq_pending, BIT(port));
+	atomic_or(&irq_pending, BIT(port));
 	hook_call_deferred(&aoz1380_irq_deferred_data, 0);
 }
 
@@ -163,6 +157,6 @@ const struct ppc_drv aoz1380_drv = {
 	.is_sourcing_vbus = &aoz1380_is_sourcing_vbus,
 	.vbus_sink_enable = &aoz1380_vbus_sink_enable,
 	.vbus_source_enable = &aoz1380_vbus_source_enable,
-	.set_vbus_source_current_limit =
-		&aoz1380_set_vbus_source_current_limit,
+	.set_vbus_source_current_limit = &aoz1380_set_vbus_source_current_limit,
+	.interrupt = &aoz1380_interrupt,
 };
diff --git a/driver/ppc/aoz1380.h b/driver/ppc/aoz1380.h
deleted file mode 100644
index 94f2b804b7..0000000000
--- a/driver/ppc/aoz1380.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * AOZ1380 USB-C Power Path Controller
- *
- * This is a basic TCPM controlled PPC driver.  It could easily be
- * renamed and repurposed to be generic, if there are other TCPM
- * controlled PPC chips that are similar to the AOZ1380
- */
-
-#ifndef __CROS_EC_AOZ1380_H
-#define __CROS_EC_AOZ1380_H
-
-#include "usb_pd_tcpm.h"
-
-struct ppc_drv;
-extern const struct ppc_drv aoz1380_drv;
-
-/**
- * AOZ1380 Set VBus Source Current Limit.
- *
- * Using this driver requires a board_aoz1380_set_vbus_source_limit
- * function due to the lack of programability of this device and
- * requirement for hardware specific code to handle setting this limit.
- *
- * @param port The Type-C port
- * @param rp The Type-C RP value
- * @return EC_SUCCESS for success, otherwise error
- */
-int board_aoz1380_set_vbus_source_current_limit(int port,
-						enum tcpc_rp_value rp);
-
-
-/**
- * Interrupt Handler for the AOZ1380.
- *
- * @param port: The Type-C port which triggered the interrupt.
- */
-void aoz1380_interrupt(int port);
-
-#endif /* defined(__CROS_EC_AOZ1380_H) */
diff --git a/driver/ppc/ktu1125.c b/driver/ppc/ktu1125.c
new file mode 100644
index 0000000000..80ad74d74d
--- /dev/null
+++ b/driver/ppc/ktu1125.c
@@ -0,0 +1,557 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Kinetic KTU1125 USB-C Power Path Controller */
+
+#include "common.h"
+#include "console.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "ktu1125.h"
+#include "system.h"
+#include "timer.h"
+#include "usb_charge.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+static atomic_t irq_pending; /* Bitmask of ports signaling an interrupt. */
+
+static void ktu1125_handle_interrupt(int port);
+
+static int read_reg(uint8_t port, int reg, int *regval)
+{
+	return i2c_read8(ppc_chips[port].i2c_port,
+			 ppc_chips[port].i2c_addr_flags, reg, regval);
+}
+
+static int write_reg(uint8_t port, int reg, int regval)
+{
+	return i2c_write8(ppc_chips[port].i2c_port,
+			  ppc_chips[port].i2c_addr_flags, reg, regval);
+}
+
+static int set_flags(const int port, const int addr, const int flags_to_set)
+{
+	int val, rv;
+
+	rv = read_reg(port, addr, &val);
+	if (rv)
+		return rv;
+
+	val |= flags_to_set;
+
+	return write_reg(port, addr, val);
+}
+
+static int clr_flags(const int port, const int addr, const int flags_to_clear)
+{
+	int val, rv;
+
+	rv = read_reg(port, addr, &val);
+	if (rv)
+		return rv;
+
+	val &= ~flags_to_clear;
+
+	return write_reg(port, addr, val);
+}
+
+static int set_field(const int port, const int addr, const int shift,
+		     const int field_length, const int field_to_set)
+{
+	int val, rv, mask;
+
+	mask = ((1 << field_length) - 1) << shift;
+	val = (field_to_set << shift) & mask;
+
+	rv = clr_flags(port, addr, mask);
+	if (rv)
+		return rv;
+
+	return set_flags(port, addr, val);
+}
+
+#ifdef CONFIG_CMD_PPC_DUMP
+static int ktu1125_dump(int port)
+{
+	int i;
+	int data;
+	CPRINTF("PPC%d: KTU1125. Registers:\n", port);
+
+	for (i = KTU1125_ID; i <= KTU1125_INT_DATA; i++) {
+		read_reg(port, i, &data);
+		CPRINTF("REG %02Xh = 0x%02x\n", i, data);
+	}
+
+	cflush();
+	return EC_SUCCESS;
+}
+#endif /* defined(CONFIG_CMD_PPC_DUMP) */
+
+/* helper */
+static int ktu1125_power_path_control(int port, int enable)
+{
+	int status =
+		enable ?
+			set_flags(port, KTU1125_CTRL_SW_CFG, KTU1125_SW_AB_EN) :
+			clr_flags(port, KTU1125_CTRL_SW_CFG, KTU1125_SW_AB_EN);
+
+	if (status) {
+		CPRINTS("ppc p%d: Failed to %s power path", port,
+			enable ? "enable" : "disable");
+	}
+
+	return status;
+}
+
+static int ktu1125_init(int port)
+{
+	int regval;
+	int ctrl_sw_cfg = 0;
+	int set_sw_cfg = 0;
+	int set_sw2_cfg = 0;
+	int sysb_clp;
+	int status;
+
+	/* Read and verify KTU1125 Vendor and Chip ID */
+	status = read_reg(port, KTU1125_ID, &regval);
+
+	if (status) {
+		ppc_prints("Failed to read device ID!", port);
+		return status;
+	}
+
+	if (regval != KTU1125_VENDOR_DIE_IDS) {
+		ppc_err_prints("KTU1125 ID mismatch!", port, regval);
+		return regval;
+	}
+
+	/*
+	 * Setting control register CTRL_SW_CFG
+	 */
+
+	/* Check if VBUS is present and set SW_AB_EN accordingly */
+	status = read_reg(port, KTU1125_MONITOR_SNK, &regval);
+	if (status) {
+		ppc_err_prints("VBUS present error", port, status);
+		return 0;
+	}
+
+	if (regval & KTU1125_SYSA_OK)
+		ctrl_sw_cfg = KTU1125_SW_AB_EN;
+
+	status = write_reg(port, KTU1125_CTRL_SW_CFG, ctrl_sw_cfg);
+	if (status) {
+		ppc_err_prints("Failed to write CTRL_SW_CFG!", port, status);
+		return status;
+	}
+
+	/*
+	 * Setting control register SET_SW_CFG
+	 */
+
+#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
+	/* Set the sourcing current limit value */
+	switch (CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) {
+	case TYPEC_RP_3A0:
+		/* Set current limit to ~3A */
+		sysb_clp = KTU1125_SYSB_ILIM_3_30;
+		break;
+
+	case TYPEC_RP_1A5:
+	default:
+		/* Set current limit to ~1.5A */
+		sysb_clp = KTU1125_SYSB_ILIM_1_70;
+		break;
+	}
+#else /* !defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
+	/* Default SRC current limit to ~1.5A */
+	sysb_clp = KTU1125_SYSB_ILIM_1_70;
+#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
+
+	/* Set SYSB Current Limit Protection */
+	set_sw_cfg |= sysb_clp << KTU1125_SYSB_CLP_SHIFT;
+	/* Set VCONN Current Limit Protection.
+	 * Note: might be changed to 600mA in future
+	 */
+	set_sw_cfg |= KTU1125_VCONN_ILIM_0_40 << KTU1125_VCONN_CLP_SHIFT;
+	/* Disable Dead Battery resistance, because CC FETs are ON */
+	set_sw_cfg |= KTU1125_RDB_DIS;
+
+	status = write_reg(port, KTU1125_SET_SW_CFG, set_sw_cfg);
+	if (status) {
+		ppc_err_prints("Failed to write SET_SW_CFG!", port, status);
+		return status;
+	}
+
+	/*
+	 * Setting control register SET_SW2_CFG
+	 */
+
+	/* Set T_HIC */
+	set_sw2_cfg |= (KTU_T_HIC_MS_17 << KTU1125_T_HIC_SHIFT);
+	/* Set vbus discharge resistance */
+	set_sw2_cfg |= (KTU1125_DIS_RES_1400 << KTU1125_DIS_RES_SHIFT);
+	/*
+	 * Set the over voltage protection to the maximum (25V) to support
+	 * sinking from a 20V PD charger. The common PPC code doesn't provide
+	 * any hooks for indicating what the currently negotiated voltage is
+	 */
+	set_sw2_cfg |= (KTU1125_SYSB_VLIM_25_00 << KTU1125_OVP_BUS_SHIFT);
+
+	status = write_reg(port, KTU1125_SET_SW2_CFG, set_sw2_cfg);
+	if (status) {
+		ppc_err_prints("Failed to write SET_SW2_CFG!", port, status);
+		return status;
+	}
+
+	/*
+	 * Don't proceed with the rest of initialization if we're sysjumping.
+	 * We would have already done this before
+	 */
+	if (system_jumped_late())
+		return EC_SUCCESS;
+
+	/*
+	 * Enable interrupts
+	 */
+
+	/* Leave SYSA_OK and FRS masked for SNK group of interrupts */
+	regval = KTU1125_SNK_MASK_ALL & (KTU1125_SYSA_OK | KTU1125_FR_SWAP);
+	status = write_reg(port, KTU1125_INTMASK_SNK, regval);
+	if (status) {
+		ppc_err_prints("Failed to write INTMASK_SNK!", port, status);
+		return status;
+	}
+
+	/* Only leave VBUS_OK masked for SRC group of interrupts */
+	regval = KTU1125_SRC_MASK_ALL & KTU1125_VBUS_OK;
+	status = write_reg(port, KTU1125_INTMASK_SRC, regval);
+	if (status) {
+		ppc_err_prints("Failed to write INTMASK_SRC!", port, status);
+		return status;
+	}
+
+	/* Unmask the entire DATA group of interrupts */
+	status = write_reg(port, KTU1125_INTMASK_DATA, ~KTU1125_DATA_MASK_ALL);
+	if (status) {
+		ppc_err_prints("Failed to write INTMASK_DATA!", port, status);
+		return status;
+	}
+
+	return EC_SUCCESS;
+}
+
+#ifdef CONFIG_USB_PD_VBUS_DETECT_PPC
+static int ktu1125_is_vbus_present(int port)
+{
+	int regval;
+	int rv;
+
+	rv = read_reg(port, KTU1125_MONITOR_SNK, &regval);
+	if (rv) {
+		ppc_err_prints("VBUS present error", port, rv);
+		return 0;
+	}
+
+	return !!(regval & KTU1125_SYSA_OK);
+}
+#endif /* defined(CONFIG_USB_PD_VBUS_DETECT_PPC) */
+
+static int ktu1125_is_sourcing_vbus(int port)
+{
+	int regval;
+	int rv;
+
+	rv = read_reg(port, KTU1125_MONITOR_SRC, &regval);
+	if (rv) {
+		ppc_err_prints("Sourcing VBUS error", port, rv);
+		return 0;
+	}
+
+	return !!(regval & KTU1125_VBUS_OK);
+}
+
+#ifdef CONFIG_USBC_PPC_POLARITY
+static int ktu1125_set_polarity(int port, int polarity)
+{
+	/*
+	 * KTU1125 doesn't need to be informed about polarity.
+	 * Polarity is queried via pd_get_polarity when applying VCONN.
+	 */
+	ppc_prints("KTU1125 sets polarity only when applying VCONN", port);
+	return EC_SUCCESS;
+}
+#endif
+
+static int ktu1125_set_vbus_src_current_limit(int port, enum tcpc_rp_value rp)
+{
+	int regval;
+	int status;
+
+	/*
+	 * Note that we chose the lowest current limit setting that is just
+	 * above indicated Rp value. This is because these are minimum values
+	 * and we must be able to provide the current that we advertise
+	 */
+	switch (rp) {
+	case TYPEC_RP_3A0:
+		regval = KTU1125_SYSB_ILIM_3_30;
+		break;
+
+	case TYPEC_RP_1A5:
+		regval = KTU1125_SYSB_ILIM_1_70;
+		break;
+
+	case TYPEC_RP_USB:
+	default:
+		regval = KTU1125_SYSB_ILIM_0_6;
+		break;
+	};
+
+	status = set_field(port, KTU1125_SET_SW_CFG, KTU1125_SYSB_CLP_SHIFT,
+			   KTU1125_SYSB_CLP_LEN, regval);
+	if (status)
+		ppc_prints("Failed to set KTU1125_SET_SW_CFG!", port);
+
+	return status;
+}
+
+static int ktu1125_discharge_vbus(int port, int enable)
+{
+	int status = enable ? set_flags(port, KTU1125_SET_SW2_CFG,
+					KTU1125_VBUS_DIS_EN) :
+			      clr_flags(port, KTU1125_SET_SW2_CFG,
+					KTU1125_VBUS_DIS_EN);
+
+	if (status) {
+		CPRINTS("ppc p%d: Failed to %s vbus discharge", port,
+			enable ? "enable" : "disable");
+		return status;
+	}
+
+	return EC_SUCCESS;
+}
+
+#ifdef CONFIG_USBC_PPC_VCONN
+static int ktu1125_set_vconn(int port, int enable)
+{
+	int polarity;
+	int status;
+	int flags = KTU1125_VCONN_EN;
+
+	polarity = polarity_rm_dts(pd_get_polarity(port));
+
+	if (enable) {
+		/*
+		 * If polarity is CC1, then apply VCONN on CC2.
+		 * else if polarity is CC2, then apply VCONN on CC1
+		 */
+		flags |= polarity ? KTU1125_CC1S_VCONN : KTU1125_CC2S_VCONN;
+		status = set_flags(port, KTU1125_CTRL_SW_CFG, flags);
+	} else {
+		flags |= KTU1125_CC1S_VCONN | KTU1125_CC2S_VCONN;
+		status = clr_flags(port, KTU1125_CTRL_SW_CFG, flags);
+	}
+
+	return status;
+}
+#endif
+
+#ifdef CONFIG_USB_PD_FRS_PPC
+static int ktu1125_set_frs_enable(int port, int enable)
+{
+	/* Enable/Disable FR_SWAP Interrupt */
+	int status =
+		enable ? clr_flags(port, KTU1125_INTMASK_SNK, KTU1125_FR_SWAP) :
+			 set_flags(port, KTU1125_INTMASK_SNK, KTU1125_FR_SWAP);
+
+	if (status) {
+		ppc_prints("Failed to write KTU1125_INTMASK_SNK!", port);
+		return status;
+	}
+
+	/* Set the FRS_EN bit */
+	status = enable ? set_flags(port, KTU1125_CTRL_SW_CFG, KTU1125_FRS_EN) :
+			  clr_flags(port, KTU1125_CTRL_SW_CFG, KTU1125_FRS_EN);
+
+	return status;
+}
+#endif
+
+static int ktu1125_vbus_sink_enable(int port, int enable)
+{
+#ifdef CONFIG_USB_PD_VBUS_DETECT_PPC
+	/* Skip if VBUS SNK is already enabled/disabled */
+	if (ktu1125_is_vbus_present(port) == enable)
+		return EC_SUCCESS;
+#endif
+
+	/* Select active sink */
+	int rv = clr_flags(port, KTU1125_CTRL_SW_CFG, KTU1125_POW_MODE);
+
+	if (rv) {
+		ppc_err_prints("Could not select SNK path", port, rv);
+		return rv;
+	}
+
+	return ktu1125_power_path_control(port, enable);
+}
+
+static int ktu1125_vbus_source_enable(int port, int enable)
+{
+	/* Skip if VBUS SRC is already enabled/disabled */
+	if (ktu1125_is_sourcing_vbus(port) == enable)
+		return EC_SUCCESS;
+
+	/* Select active source */
+	int rv = set_flags(port, KTU1125_CTRL_SW_CFG, KTU1125_POW_MODE);
+
+	if (rv) {
+		ppc_err_prints("Could not select SRC path", port, rv);
+		return rv;
+	}
+
+	return ktu1125_power_path_control(port, enable);
+}
+
+#ifdef CONFIG_USBC_PPC_SBU
+static int ktu1125_set_sbu(int port, int enable)
+{
+	int status =
+		enable ?
+			clr_flags(port, KTU1125_CTRL_SW_CFG, KTU1125_SBU_SHUT) :
+			set_flags(port, KTU1125_CTRL_SW_CFG, KTU1125_SBU_SHUT);
+
+	if (status) {
+		CPRINTS("ppc p%d: Failed to %s sbu", port,
+			enable ? "enable" : "disable");
+	}
+
+	return status;
+}
+#endif /* CONFIG_USBC_PPC_SBU */
+
+static void ktu1125_irq_deferred(void)
+{
+	int i;
+	uint32_t pending = atomic_clear(&irq_pending);
+
+	for (i = 0; i < board_get_usb_pd_port_count(); i++)
+		if (BIT(i) & pending)
+			ktu1125_handle_interrupt(i);
+}
+DECLARE_DEFERRED(ktu1125_irq_deferred);
+
+void ktu1125_interrupt(int port)
+{
+	atomic_or(&irq_pending, BIT(port));
+	hook_call_deferred(&ktu1125_irq_deferred_data, 0);
+}
+
+static void ktu1125_handle_interrupt(int port)
+{
+	int attempt = 0;
+
+	/*
+	 * KTU1125's /INT pin is level, so process interrupts until it
+	 * deasserts if the chip has a dedicated interrupt pin.
+	 */
+#ifdef CONFIG_USBC_PPC_DEDICATED_INT
+	while (ppc_get_alert_status(port))
+#endif
+	{
+		int ovp_int_count = 0;
+		int snk = 0;
+		int src = 0;
+		int data = 0;
+
+		attempt++;
+		if (attempt > 1)
+			ppc_prints("Could not clear interrupts on first "
+				   "try, retrying",
+				   port);
+
+		if (attempt > 10) {
+			ppc_prints("Rescheduling interrupt handler", port);
+			atomic_or(&irq_pending, BIT(port));
+			hook_call_deferred(&ktu1125_irq_deferred_data, MSEC);
+			return;
+		}
+
+		/* Clear the interrupt by reading all 3 registers */
+		read_reg(port, KTU1125_INT_SNK, &snk);
+		read_reg(port, KTU1125_INT_SRC, &src);
+		read_reg(port, KTU1125_INT_DATA, &data);
+
+		CPRINTS("ppc p%d: INTERRUPT snk=%02X src=%02X data=%02X", port,
+			snk, src, data);
+
+		if (snk & KTU1125_FR_SWAP)
+			pd_got_frs_signal(port);
+
+		if (snk &
+		    (KTU1125_SYSA_SCP | KTU1125_SYSA_OCP | KTU1125_VBUS_OVP)) {
+			/* Log and PD reset */
+			pd_handle_overcurrent(port);
+		}
+
+		if (src &
+		    (KTU1125_SYSB_CLP | KTU1125_SYSB_OCP | KTU1125_SYSB_SCP |
+		     KTU1125_VCONN_CLP | KTU1125_VCONN_SCP)) {
+			/* Log and PD reset */
+			pd_handle_overcurrent(port);
+		}
+
+		if (data & (KTU1125_SBU2_OVP | KTU1125_SBU1_OVP)) {
+			/* Log and PD reset */
+			pd_handle_overcurrent(port);
+		}
+
+		if (data & (KTU1125_CC1_OVP | KTU1125_CC2_OVP)) {
+			ppc_prints("CC Over Voltage!", port);
+			/*
+			 * Bug on ktu1125 Rev A:
+			 * OVP interrupts are falsely triggered
+			 * after IC reset (RST_L 0-> 1)
+			 */
+			if (ovp_int_count++)
+				pd_handle_cc_overvoltage(port);
+		}
+	}
+}
+
+const struct ppc_drv ktu1125_drv = {
+	.init = &ktu1125_init,
+	.is_sourcing_vbus = &ktu1125_is_sourcing_vbus,
+	.vbus_sink_enable = &ktu1125_vbus_sink_enable,
+	.vbus_source_enable = &ktu1125_vbus_source_enable,
+#ifdef CONFIG_USBC_PPC_POLARITY
+	.set_polarity = &ktu1125_set_polarity,
+#endif
+	.set_vbus_source_current_limit = &ktu1125_set_vbus_src_current_limit,
+	.discharge_vbus = &ktu1125_discharge_vbus,
+#ifdef CONFIG_USBC_PPC_SBU
+	.set_sbu = &ktu1125_set_sbu,
+#endif
+#ifdef CONFIG_USBC_PPC_VCONN
+	.set_vconn = &ktu1125_set_vconn,
+#endif
+#ifdef CONFIG_USB_PD_FRS_PPC
+	.set_frs_enable = &ktu1125_set_frs_enable,
+#endif
+#ifdef CONFIG_CMD_PPC_DUMP
+	.reg_dump = &ktu1125_dump,
+#endif
+#ifdef CONFIG_USB_PD_VBUS_DETECT_PPC
+	.is_vbus_present = &ktu1125_is_vbus_present,
+#endif
+	.interrupt = &ktu1125_interrupt,
+};
diff --git a/driver/ppc/ktu1125.h b/driver/ppc/ktu1125.h
new file mode 100644
index 0000000000..9957ed80ec
--- /dev/null
+++ b/driver/ppc/ktu1125.h
@@ -0,0 +1,124 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Kinetic KTU1125 Type-C Power Path Controller */
+
+#ifndef __CROS_EC_KTU1125_H
+#define __CROS_EC_KTU1125_H
+
+#include "common.h"
+#include "driver/ppc/ktu1125_public.h"
+
+#define KTU1125_ID 0x0
+#define KTU1125_CTRL_SW_CFG 0x1
+#define KTU1125_SET_SW_CFG 0x2
+#define KTU1125_SET_SW2_CFG 0x3
+#define KTU1125_MONITOR_SNK 0x4
+#define KTU1125_MONITOR_SRC 0x5
+#define KTU1125_MONITOR_DATA 0x6
+#define KTU1125_INTMASK_SNK 0x7
+#define KTU1125_INTMASK_SRC 0x8
+#define KTU1125_INTMASK_DATA 0x9
+#define KTU1125_INT_SNK 0xA
+#define KTU1125_INT_SRC 0xB
+#define KTU1125_INT_DATA 0xC
+
+/* KTU1125_ID default value */
+#define KTU1125_VENDOR_DIE_IDS 0xA5
+
+/* KTU1125_CTRL_SW_CFG bits */
+#define KTU1125_SBU_SHUT BIT(0)
+#define KTU1125_VCONN_EN BIT(1)
+#define KTU1125_CC2S_VCONN BIT(2)
+#define KTU1125_CC1S_VCONN BIT(3)
+#define KTU1125_POW_MODE BIT(4)
+#define KTU1125_SW_AB_EN BIT(5)
+#define KTU1125_FRS_EN BIT(6)
+#define KTU1125_EN_L BIT(7)
+
+/* KTU1125_SET_SW_CFG bits and fields */
+#define KTU1125_RDB_DIS BIT(0)
+#define KTU1125_SS_CLP_SNK BIT(1)
+#define KTU1125_TDON BIT(2)
+#define KTU1125_VCONN_CLP_SHIFT 3
+#define KTU1125_VCONN_CLP_LEN 2
+#define KTU1125_SYSB_CLP_SHIFT 5
+#define KTU1125_SYSB_CLP_LEN 3
+
+/* VBUS Switch Current Limit Settings - SYSB_CLP */
+#define KTU1125_SYSB_ILIM_0_6 0
+#define KTU1125_SYSB_ILIM_1_05 1
+#define KTU1125_SYSB_ILIM_1_70 2
+#define KTU1125_SYSB_ILIM_3_30 3
+#define KTU1125_SYSB_ILIM_3_60 4
+
+/* VCONN Current Limit Settings - VCONN_CLP */
+#define KTU1125_VCONN_ILIM_0_40 0
+#define KTU1125_VCONN_ILIM_0_60 1
+#define KTU1125_VCONN_ILIM_1_00 2
+#define KTU1125_VCONN_ILIM_1_40 3
+
+/* KTU1125_SET_SW2_CFG bits and fields */
+#define KTU1125_OVP_BUS_SHIFT 0
+#define KTU1125_OVP_BUS_LEN 3
+#define KTU1125_DIS_RES_SHIFT 3
+#define KTU1125_DIS_RES_LEN 2
+#define KTU1125_VBUS_DIS_EN BIT(5)
+#define KTU1125_T_HIC_SHIFT 6
+#define KTU1125_T_HIC_LEN 2
+
+/* VBUS Over Voltage Protection */
+#define KTU1125_SYSB_VLIM_25_00 0
+#define KTU1125_SYSB_VLIM_17_00 4
+#define KTU1125_SYSB_VLIM_13_75 5
+#define KTU1125_SYSB_VLIM_10_60 6
+#define KTU1125_SYSB_VLIM_6_00 7
+
+/* Discharge resistor [ohms] */
+#define KTU1125_DIS_RES_1400 0
+#define KTU1125_DIS_RES_730 1
+#define KTU1125_DIS_RES_570 2
+#define KTU1125_DIS_RES_205 3
+
+/* T _HIC values [ms] */
+#define KTU_T_HIC_MS_17 0
+#define KTU_T_HIC_MS_34 1
+#define KTU_T_HIC_MS_51 2
+#define KTU_T_HIC_MS_68 3
+
+/* Bits for MONITOR/INTMASK/INT SNK */
+#define KTU1125_SS_FAIL BIT(0)
+#define KTU1125_OTP BIT(1)
+#define KTU1125_FR_SWAP BIT(2)
+#define KTU1125_SYSA_SCP BIT(3)
+#define KTU1125_SYSA_OCP BIT(4)
+#define KTU1125_VBUS_OVP BIT(5)
+#define KTU1125_VBUS_UVLO BIT(6)
+#define KTU1125_SYSA_OK BIT(7)
+#define KTU1125_SNK_MASK_ALL 0xFF
+
+/* Bits for MONITOR/INTMASK/INT SRC */
+#define KTU1125_VCONN_SCP BIT(0)
+#define KTU1125_VCONN_CLP BIT(1)
+#define KTU1125_VCONN_UVLO BIT(2)
+#define KTU1125_SYSB_SCP BIT(3)
+#define KTU1125_SYSB_OCP BIT(4)
+#define KTU1125_SYSB_CLP BIT(5)
+#define KTU1125_SYSB_UVLO BIT(6)
+#define KTU1125_VBUS_OK BIT(7)
+#define KTU1125_SRC_MASK_ALL 0xFF
+
+/* Bits for MONITOR/INTMASK/INT DATA */
+#define KTU1125_SBUB BIT(0)
+#define KTU1125_SBUA BIT(1)
+#define KTU1125_SBU2_OVP BIT(2)
+#define KTU1125_SBU1_OVP BIT(3)
+#define KTU1125_CC2_OVP BIT(4)
+#define KTU1125_CC1_OVP BIT(5)
+#define KTU1125_CC2S_CLAMP BIT(6)
+#define KTU1125_CC1S_CLAMP BIT(7)
+#define KTU1125_DATA_MASK_ALL 0xFC
+
+#endif /* defined(__CROS_EC_KTU1125_H) */
diff --git a/driver/ppc/nx20p348x.c b/driver/ppc/nx20p348x.c
index c13087fa52..cb35e9ff23 100644
--- a/driver/ppc/nx20p348x.c
+++ b/driver/ppc/nx20p348x.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,22 +7,22 @@
 
 #include "common.h"
 #include "console.h"
-#include "driver/ppc/nx20p348x.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "i2c.h"
+#include "nx20p348x.h"
 #include "system.h"
-#include "tcpm.h"
+#include "tcpm/tcpm.h"
 #include "usb_charge.h"
-#include "usb_pd_tcpm.h"
 #include "usb_pd.h"
+#include "usb_pd_tcpm.h"
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
-static uint32_t irq_pending; /* Bitmask of ports signaling an interrupt. */
+static atomic_t irq_pending; /* Bitmask of ports signaling an interrupt. */
 
 #define NX20P348X_DB_EXIT_FAIL_THRESHOLD 10
 static int db_exit_fail_count[CONFIG_USB_PD_PORT_MAX_COUNT];
@@ -37,17 +37,13 @@ static uint8_t flags[CONFIG_USB_PD_PORT_MAX_COUNT];
 static int read_reg(uint8_t port, int reg, int *regval)
 {
 	return i2c_read8(ppc_chips[port].i2c_port,
-			 ppc_chips[port].i2c_addr_flags,
-			 reg,
-			 regval);
+			 ppc_chips[port].i2c_addr_flags, reg, regval);
 }
 
 static int write_reg(uint8_t port, int reg, int regval)
 {
 	return i2c_write8(ppc_chips[port].i2c_port,
-			  ppc_chips[port].i2c_addr_flags,
-			  reg,
-			  regval);
+			  ppc_chips[port].i2c_addr_flags, reg, regval);
 }
 
 static int nx20p348x_set_ovp_limit(int port)
@@ -76,7 +72,7 @@ static int nx20p348x_is_sourcing_vbus(int port)
 }
 
 static int nx20p348x_set_vbus_source_current_limit(int port,
-						 enum tcpc_rp_value rp)
+						   enum tcpc_rp_value rp)
 {
 	int regval;
 	int status;
@@ -103,13 +99,13 @@ static int nx20p348x_set_vbus_source_current_limit(int port,
 		break;
 	};
 
-
 	return write_reg(port, NX20P348X_5V_SRC_OCP_THRESHOLD_REG, regval);
 }
 
 static int nx20p348x_discharge_vbus(int port, int enable)
 {
 	int regval;
+	int newval;
 	int status;
 
 	status = read_reg(port, NX20P348X_DEVICE_CONTROL_REG, &regval);
@@ -117,13 +113,16 @@ static int nx20p348x_discharge_vbus(int port, int enable)
 		return status;
 
 	if (enable)
-		regval |= NX20P348X_CTRL_VBUSDIS_EN;
+		newval = regval | NX20P348X_CTRL_VBUSDIS_EN;
 	else
-		regval &= ~NX20P348X_CTRL_VBUSDIS_EN;
+		newval = regval & ~NX20P348X_CTRL_VBUSDIS_EN;
 
-	status = write_reg(port, NX20P348X_DEVICE_CONTROL_REG, regval);
+	if (newval == regval)
+		return EC_SUCCESS;
+
+	status = write_reg(port, NX20P348X_DEVICE_CONTROL_REG, newval);
 	if (status) {
-		CPRINTS("Failed to %s vbus discharge",
+		CPRINTS("Failed to %s VBUS discharge",
 			enable ? "enable" : "disable");
 		return status;
 	}
@@ -131,23 +130,22 @@ static int nx20p348x_discharge_vbus(int port, int enable)
 	return EC_SUCCESS;
 }
 
-static int nx20p348x_vbus_sink_enable(int port, int enable)
+__maybe_unused static int nx20p3481_vbus_sink_enable(int port, int enable)
 {
 	int status;
 	int rv;
-	int control = enable ? NX20P348X_SWITCH_CONTROL_HVSNK : 0;
-
-	enable = !!enable;
+	int control = enable ? NX20P3481_SWITCH_CONTROL_HVSNK : 0;
 
-	if (IS_ENABLED(CONFIG_USBC_PPC_NX20P3481))
-		rv = write_reg(port, NX20P348X_SWITCH_CONTROL_REG, control);
-	else if (IS_ENABLED(CONFIG_USBC_PPC_NX20P3483))
+	if (enable) {
 		/*
-		 * We cannot use an EC GPIO for EN_SNK since an EC reset
-		 * will float the GPIO thus browning out the board (without
-		 * a battery).
+		 * VBUS Discharge must be off in sink mode.
 		 */
-		rv = tcpm_set_snk_ctrl(port, enable);
+		rv = nx20p348x_discharge_vbus(port, 0);
+		if (rv)
+			return rv;
+	}
+
+	rv = write_reg(port, NX20P348X_SWITCH_CONTROL_REG, control);
 	if (rv)
 		return rv;
 
@@ -162,28 +160,19 @@ static int nx20p348x_vbus_sink_enable(int port, int enable)
 	if (rv)
 		return rv;
 
-	return (status & NX20P348X_SWITCH_STATUS_MASK) == control ?
-		EC_SUCCESS : EC_ERROR_UNKNOWN;
+	return (status & NX20P348X_SWITCH_STATUS_HVSNK) == control ?
+		       EC_SUCCESS :
+		       EC_ERROR_UNKNOWN;
 }
 
-static int nx20p348x_vbus_source_enable(int port, int enable)
+__maybe_unused static int nx20p3481_vbus_source_enable(int port, int enable)
 {
 	int status;
 	int rv;
 	uint8_t previous_flags = flags[port];
-	int control = enable ? NX20P348X_SWITCH_CONTROL_5VSRC : 0;
-
-	enable = !!enable;
+	int control = enable ? NX20P3481_SWITCH_CONTROL_5VSRC : 0;
 
-	if (IS_ENABLED(CONFIG_USBC_PPC_NX20P3481))
-		rv = write_reg(port, NX20P348X_SWITCH_CONTROL_REG, control);
-	else if (IS_ENABLED(CONFIG_USBC_PPC_NX20P3483))
-		/*
-		 * For parity's sake, we should not use an EC GPIO for
-		 * EN_SRC since we cannot use it for EN_SNK (for brown
-		 * out reason listed above).
-		 */
-		rv = tcpm_set_src_ctrl(port, enable);
+	rv = write_reg(port, NX20P348X_SWITCH_CONTROL_REG, control);
 	if (rv)
 		return rv;
 
@@ -216,6 +205,95 @@ static int nx20p348x_vbus_source_enable(int port, int enable)
 	return EC_SUCCESS;
 }
 
+__maybe_unused static int nx20p3483_vbus_sink_enable(int port, int enable)
+{
+	int rv;
+
+	enable = !!enable;
+
+	if (enable) {
+		/*
+		 * VBUS Discharge must be off in sink mode.
+		 */
+		rv = nx20p348x_discharge_vbus(port, 0);
+		if (rv)
+			return rv;
+	}
+
+	/*
+	 * We cannot use an EC GPIO for EN_SNK since an EC reset
+	 * will float the GPIO thus browning out the board (without
+	 * a battery).
+	 */
+	rv = tcpm_set_snk_ctrl(port, enable);
+	if (rv)
+		return rv;
+
+	for (int i = 0; i < NX20P348X_SWITCH_STATUS_DEBOUNCE_MSEC; ++i) {
+		int ds;
+		bool is_sink;
+
+		rv = read_reg(port, NX20P348X_DEVICE_STATUS_REG, &ds);
+		if (rv != EC_SUCCESS)
+			return rv;
+
+		is_sink = (ds & NX20P3483_DEVICE_MODE_MASK) ==
+			  NX20P3483_MODE_HV_SNK;
+		if (enable == is_sink)
+			return EC_SUCCESS;
+
+		msleep(1);
+	}
+
+	return EC_ERROR_TIMEOUT;
+}
+
+__maybe_unused static int nx20p3483_vbus_source_enable(int port, int enable)
+{
+	int rv;
+
+	enable = !!enable;
+
+	/*
+	 * For parity's sake, we should not use an EC GPIO for
+	 * EN_SRC since we cannot use it for EN_SNK (for brown
+	 * out reason listed above).
+	 */
+	rv = tcpm_set_src_ctrl(port, enable);
+	if (rv)
+		return rv;
+
+	/*
+	 * Wait up to NX20P348X_SWITCH_STATUS_DEBOUNCE_MSEC for the status
+	 * to reflect the control command.
+	 */
+
+	for (int i = 0; i < NX20P348X_SWITCH_STATUS_DEBOUNCE_MSEC; ++i) {
+		int s;
+
+		rv = read_reg(port, NX20P348X_SWITCH_STATUS_REG, &s);
+		if (rv != EC_SUCCESS)
+			return rv;
+
+		if (!!(s & (NX20P348X_SWITCH_STATUS_5VSRC |
+			    NX20P348X_SWITCH_STATUS_HVSRC)) == enable) {
+			if (enable)
+				flags[port] |= NX20P348X_FLAGS_SOURCE_ENABLED;
+			else
+				flags[port] &= ~NX20P348X_FLAGS_SOURCE_ENABLED;
+			return EC_SUCCESS;
+		}
+		msleep(1);
+	}
+
+	return EC_ERROR_TIMEOUT;
+}
+
+__overridable int board_nx20p348x_init(int port)
+{
+	return EC_SUCCESS;
+}
+
 static int nx20p348x_init(int port)
 {
 	int reg;
@@ -233,10 +311,15 @@ static int nx20p348x_init(int port)
 	/* Mask interrupts for interrupt 1 register */
 	mask = ~(NX20P348X_INT1_OC_5VSRC | NX20P348X_INT1_SC_5VSRC |
 		 NX20P348X_INT1_RCP_5VSRC | NX20P348X_INT1_DBEXIT_ERR);
-#if defined(CONFIG_USBC_PPC_NX20P3481) || defined(CONFIG_USBC_PPC_NX20P3483)
-	/* Unmask Fast Role Swap detect interrupt */
-	mask &= ~NX20P348X_INT1_FRS_DET;
-#endif
+	mask &= ~NX20P3481_INT1_RESERVED;
+	if (IS_ENABLED(CONFIG_USBC_PPC_NX20P3481)) {
+		/* Unmask Fast Role Swap detect interrupt */
+		mask &= ~NX20P3481_INT1_FRS_DET;
+	}
+	if (IS_ENABLED(CONFIG_USBC_NX20P348X_RCP_5VSRC_MASK_ENABLE)) {
+		/* Mask RCP 5V SRC */
+		mask |= NX20P348X_INT1_RCP_5VSRC;
+	}
 	rv = write_reg(port, NX20P348X_INTERRUPT1_MASK_REG, mask);
 	if (rv)
 		return rv;
@@ -249,7 +332,11 @@ static int nx20p348x_init(int port)
 	rv = read_reg(port, NX20P348X_DEVICE_STATUS_REG, &mode);
 	if (rv)
 		return rv;
-	mode &= NX20P348X_DEVICE_MODE_MASK;
+
+	if (IS_ENABLED(CONFIG_USBC_PPC_NX20P3481))
+		mode &= NX20P3481_DEVICE_MODE_MASK;
+	else if (IS_ENABLED(CONFIG_USBC_PPC_NX20P3483))
+		mode &= NX20P3483_DEVICE_MODE_MASK;
 
 	/* Check if dead battery mode is active. */
 	if (mode == NX20P348X_MODE_DEAD_BATTERY) {
@@ -260,7 +347,7 @@ static int nx20p348x_init(int port)
 		 * mode will not reflect the correct value and therefore the
 		 * return value isn't useful here.
 		 */
-		nx20p348x_vbus_sink_enable(port, 1);
+		nx20p348x_drv.vbus_sink_enable(port, 1);
 
 		/* Exit dead battery mode. */
 		rv = read_reg(port, NX20P348X_DEVICE_CONTROL_REG, &reg);
@@ -287,6 +374,15 @@ static int nx20p348x_init(int port)
 #endif
 	nx20p348x_set_vbus_source_current_limit(port, initial_current_limit);
 
+	/* Restore power-on reset value */
+	rv = write_reg(port, NX20P348X_DEVICE_CONTROL_REG, 0);
+	if (rv)
+		return rv;
+
+	rv = board_nx20p348x_init(port);
+	if (rv)
+		return rv;
+
 	return EC_SUCCESS;
 }
 
@@ -314,14 +410,14 @@ static void nx20p348x_handle_interrupt(int port)
 		    NX20P348X_DB_EXIT_FAIL_THRESHOLD) {
 			ppc_prints("failed to exit DB mode", port);
 			if (read_reg(port, NX20P348X_INTERRUPT1_MASK_REG,
-				    &mask_reg)) {
+				     &mask_reg) == 0) {
 				mask_reg |= NX20P348X_INT1_DBEXIT_ERR;
 				write_reg(port, NX20P348X_INTERRUPT1_MASK_REG,
 					  mask_reg);
 			}
 		}
 		read_reg(port, NX20P348X_DEVICE_CONTROL_REG, &control_reg);
-		reg |= NX20P348X_CTRL_DB_EXIT;
+		control_reg |= NX20P348X_CTRL_DB_EXIT;
 		write_reg(port, NX20P348X_DEVICE_CONTROL_REG, control_reg);
 		/*
 		 * If DB exit mode failed, then the OVP limit setting done in
@@ -338,16 +434,18 @@ static void nx20p348x_handle_interrupt(int port)
 	}
 
 	/* Check for Vbus reverse current protection */
-	if (reg & NX20P348X_INT1_RCP_5VSRC)
+	if (reg & NX20P348X_INT1_RCP_5VSRC) {
 		ppc_prints("detected Vbus reverse current!", port);
+		pd_handle_overcurrent(port);
+	}
 
 	/* Check for Vbus short protection */
 	if (reg & NX20P348X_INT1_SC_5VSRC)
 		ppc_prints("Vbus short detected!", port);
 
-#ifdef CONFIG_USBC_PPC_NX20P3481
 	/* Check for FRS detection */
-	if (reg & NX20P348X_INT1_FRS_DET) {
+	if (IS_ENABLED(CONFIG_USBC_PPC_NX20P3481) &&
+	    (reg & NX20P3481_INT1_FRS_DET)) {
 		/*
 		 * TODO(b/113069469): Need to check for CC status and verifiy
 		 * that a sink is attached to continue with FRS. If a sink is
@@ -363,9 +461,8 @@ static void nx20p348x_handle_interrupt(int port)
 		 * NX20P3481.
 		 */
 		ppc_prints("FRS false detect, disabling SRC mode!", port);
-		nx20p348x_vbus_source_enable(port, 0);
+		nx20p3481_vbus_source_enable(port, 0);
 	}
-#endif
 
 	/*
 	 * Read interrupt 2 status register. Note, interrupt register is
@@ -384,7 +481,7 @@ static void nx20p348x_handle_interrupt(int port)
 static void nx20p348x_irq_deferred(void)
 {
 	int i;
-	uint32_t pending = deprecated_atomic_read_clear(&irq_pending);
+	uint32_t pending = atomic_clear(&irq_pending);
 
 	for (i = 0; i < board_get_usb_pd_port_count(); i++)
 		if (BIT(i) & pending)
@@ -394,7 +491,7 @@ DECLARE_DEFERRED(nx20p348x_irq_deferred);
 
 void nx20p348x_interrupt(int port)
 {
-	deprecated_atomic_or(&irq_pending, BIT(port));
+	atomic_or(&irq_pending, BIT(port));
 	hook_call_deferred(&nx20p348x_irq_deferred_data, 0);
 }
 
@@ -405,9 +502,8 @@ static int nx20p348x_dump(int port)
 	int reg;
 	int rv;
 
-	ccprintf("Port %d NX20P348X registers\n", port);
-	for (reg_addr = NX20P348X_DEVICE_ID_REG; reg_addr <=
-		     NX20P348X_DEVICE_CONTROL_REG; reg_addr++) {
+	for (reg_addr = NX20P348X_DEVICE_ID_REG;
+	     reg_addr <= NX20P348X_DEVICE_CONTROL_REG; reg_addr++) {
 		rv = read_reg(port, reg_addr, &reg);
 		if (rv) {
 			ccprintf("nx20p: Failed to read register 0x%x\n",
@@ -455,8 +551,14 @@ static int nx20p348x_set_vconn(int port, int enable)
 const struct ppc_drv nx20p348x_drv = {
 	.init = &nx20p348x_init,
 	.is_sourcing_vbus = &nx20p348x_is_sourcing_vbus,
-	.vbus_sink_enable = &nx20p348x_vbus_sink_enable,
-	.vbus_source_enable = &nx20p348x_vbus_source_enable,
+#ifdef CONFIG_USBC_PPC_NX20P3481
+	.vbus_sink_enable = &nx20p3481_vbus_sink_enable,
+	.vbus_source_enable = &nx20p3481_vbus_source_enable,
+#endif /* CONFIG_USBC_PPC_NX20P3481 */
+#ifdef CONFIG_USBC_PPC_NX20P3483
+	.vbus_sink_enable = &nx20p3483_vbus_sink_enable,
+	.vbus_source_enable = &nx20p3483_vbus_source_enable,
+#endif /* CONFIG_USBC_PPC_NX20P3483 */
 #ifdef CONFIG_CMD_PPC_DUMP
 	.reg_dump = &nx20p348x_dump,
 #endif /* defined(CONFIG_CMD_PPC_DUMP) */
@@ -472,4 +574,5 @@ const struct ppc_drv nx20p348x_drv = {
 #ifdef CONFIG_USBC_PPC_VCONN
 	.set_vconn = &nx20p348x_set_vconn,
 #endif /* defined(CONFIG_USBC_PPC_VCONN) */
+	.interrupt = &nx20p348x_interrupt,
 };
diff --git a/driver/ppc/nx20p348x.h b/driver/ppc/nx20p348x.h
index 6aad5c9881..9bab7298be 100644
--- a/driver/ppc/nx20p348x.h
+++ b/driver/ppc/nx20p348x.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,15 +8,8 @@
 #ifndef __CROS_EC_NX20P348X_H
 #define __CROS_EC_NX20P348X_H
 
-#define NX20P3483_ADDR0_FLAGS 0x70
-#define NX20P3483_ADDR1_FLAGS 0x71
-#define NX20P3483_ADDR2_FLAGS 0x72
-#define NX20P3483_ADDR3_FLAGS 0x73
-
-#define NX20P3481_ADDR0_FLAGS 0x74
-#define NX20P3481_ADDR1_FLAGS 0x75
-#define NX20P3481_ADDR2_FLAGS 0x76
-#define NX20P3481_ADDR3_FLAGS 0x77
+#include "common.h"
+#include "ppc/nx20p348x_public.h"
 
 /*
  * This PPC hard-codes the over voltage protect of Vbus at 6.8V in dead-battery
@@ -26,62 +19,63 @@
 #define NX20P348X_SAFE_RESET_VBUS_MV 5000
 
 /* NX20P348x register addresses */
-#define NX20P348X_DEVICE_ID_REG		0x00
-#define NX20P348X_DEVICE_STATUS_REG		0x01
-#define NX20P348X_SWITCH_CONTROL_REG		0x02
-#define NX20P348X_SWITCH_STATUS_REG		0x03
-#define NX20P348X_INTERRUPT1_REG		0x04
-#define NX20P348X_INTERRUPT2_REG		0x05
-#define NX20P348X_INTERRUPT1_MASK_REG		0x06
-#define NX20P348X_INTERRUPT2_MASK_REG		0x07
-#define NX20P348X_OVLO_THRESHOLD_REG		0x08
-#define NX20P348X_HV_SRC_OCP_THRESHOLD_REG	0x09
-#define NX20P348X_5V_SRC_OCP_THRESHOLD_REG	0x0A
-#define NX20P348X_DEVICE_CONTROL_REG		0x0B
-
-/* Device Control Register */
-#define NX20P348X_CTRL_FRS_AT BIT(3)
+#define NX20P348X_DEVICE_ID_REG 0x00
+#define NX20P348X_DEVICE_STATUS_REG 0x01
+#define NX20P348X_SWITCH_CONTROL_REG 0x02
+#define NX20P348X_SWITCH_STATUS_REG 0x03
+#define NX20P348X_INTERRUPT1_REG 0x04
+#define NX20P348X_INTERRUPT2_REG 0x05
+#define NX20P348X_INTERRUPT1_MASK_REG 0x06
+#define NX20P348X_INTERRUPT2_MASK_REG 0x07
+#define NX20P348X_OVLO_THRESHOLD_REG 0x08
+#define NX20P348X_HV_SRC_OCP_THRESHOLD_REG 0x09
+#define NX20P348X_5V_SRC_OCP_THRESHOLD_REG 0x0A
+#define NX20P348X_DEVICE_CONTROL_REG 0x0B
+
+/* Device Control Register (0x0B) */
+#define NX20P3483_CTRL_FRS_AT BIT(3)
 #define NX20P348X_CTRL_DB_EXIT BIT(2)
 #define NX20P348X_CTRL_VBUSDIS_EN BIT(1)
 #define NX20P348X_CTRL_LDO_SD BIT(0)
 
-/* Device Status Modes */
-#define NX20P348X_DEVICE_MODE_MASK 0x7
+/* Device Status Modes (0x01) */
+#define NX20P3481_DEVICE_MODE_MASK 0x3
+#define NX20P3483_DEVICE_MODE_MASK 0x7
 #define NX20P348X_MODE_DEAD_BATTERY 0
 /* After dead battery, mode values are different between 3481 and 3483 */
-#define NX20P3481_MODE_NORMAL  1
-#define NX20P3481_MODE_FRS  2
+#define NX20P3481_MODE_NORMAL 1
+#define NX20P3481_MODE_FRS 2
 #define NX20P3481_MODE_STANDBY 3
 
-#define NX20P3483_MODE_HV_SNK  1
-#define NX20P3483_MODE_5V_SRC  2
-#define NX20P3483_MODE_HV_SRC  3
+#define NX20P3483_MODE_HV_SNK 1
+#define NX20P3483_MODE_5V_SRC 2
+#define NX20P3483_MODE_HV_SRC 3
 #define NX20P3483_MODE_STANDBY 4
 
-/* Switch Control Register */
-#define NX20P348X_SWITCH_CONTROL_HVSNK BIT(0)
-#define NX20P348X_SWITCH_CONTROL_HVSRC BIT(1)
-#define NX20P348X_SWITCH_CONTROL_5VSRC BIT(2)
+/* Switch Control Register (0x02) */
+#define NX20P3481_SWITCH_CONTROL_5VSRC BIT(2)
+#define NX20P3481_SWITCH_CONTROL_HVSRC BIT(1)
+#define NX20P3481_SWITCH_CONTROL_HVSNK BIT(0)
 
-/* Switch Status Register */
-#define NX20P348X_HVSNK_STS BIT(0)
-#define NX20P348X_HVSRC_STS BIT(1)
-#define NX20P348X_5VSRC_STS BIT(2)
+/* Switch Status Register (0x03) */
+#define NX20P348X_SWITCH_STATUS_5VSRC BIT(2)
+#define NX20P348X_SWITCH_STATUS_HVSRC BIT(1)
+#define NX20P348X_SWITCH_STATUS_HVSNK BIT(0)
 #define NX20P348X_SWITCH_STATUS_DEBOUNCE_MSEC 25
 #define NX20P348X_SWITCH_STATUS_MASK 0x7
 
 /* Internal 5V VBUS Switch Current Limit Settings (min) */
 #define NX20P348X_ILIM_MASK 0xF
-#define NX20P348X_ILIM_0_400  0
-#define NX20P348X_ILIM_0_600  1
-#define NX20P348X_ILIM_0_800  2
-#define NX20P348X_ILIM_1_000  3
-#define NX20P348X_ILIM_1_200  4
-#define NX20P348X_ILIM_1_400  5
-#define NX20P348X_ILIM_1_600  6
-#define NX20P348X_ILIM_1_800  7
-#define NX20P348X_ILIM_2_000  8
-#define NX20P348X_ILIM_2_200  9
+#define NX20P348X_ILIM_0_400 0
+#define NX20P348X_ILIM_0_600 1
+#define NX20P348X_ILIM_0_800 2
+#define NX20P348X_ILIM_1_000 3
+#define NX20P348X_ILIM_1_200 4
+#define NX20P348X_ILIM_1_400 5
+#define NX20P348X_ILIM_1_600 6
+#define NX20P348X_ILIM_1_800 7
+#define NX20P348X_ILIM_2_000 8
+#define NX20P348X_ILIM_2_200 9
 #define NX20P348X_ILIM_2_400 10
 #define NX20P348X_ILIM_2_600 11
 #define NX20P348X_ILIM_2_800 12
@@ -99,33 +93,31 @@
 #define NX20P348X_OVLO_17_0 5
 #define NX20P348X_OVLO_23_0 6
 
-/* Interrupt 1 Register Bits */
+/* Interrupt 1 Register Bits (0x04) */
 #define NX20P348X_INT1_DBEXIT_ERR BIT(7)
-#define NX20P348X_INT1_FRS_DET    BIT(6)
-#define NX20P348X_INT1_OV_5VSRC   BIT(4)
-#define NX20P348X_INT1_RCP_5VSRC  BIT(3)
-#define NX20P348X_INT1_SC_5VSRC   BIT(2)
-#define NX20P348X_INT1_OC_5VSRC   BIT(1)
-#define NX20P348X_INT1_OTP        BIT(0)
-
-/* Interrupt 2 Register Bits */
-#define NX20P348X_INT2_EN_ERR     BIT(7)
-#define NX20P348X_INT2_RCP_HVSNK  BIT(6)
-#define NX20P348X_INT2_SC_HVSNK   BIT(5)
-#define NX20P348X_INT2_OV_HVSNK   BIT(4)
-#define NX20P348X_INT2_RCP_HVSRC  BIT(3)
-#define NX20P348X_INT2_SC_HVSRC   BIT(2)
-#define NX20P348X_INT2_OC_HVSRC   BIT(1)
-#define NX20P348X_INT2_OV_HVSRC   BIT(0)
-
-struct ppc_drv;
-extern const struct ppc_drv nx20p348x_drv;
+#define NX20P3481_INT1_FRS_DET BIT(6)
+#define NX20P3481_INT1_RESERVED BIT(5)
+#define NX20P348X_INT1_OV_5VSRC BIT(4)
+#define NX20P348X_INT1_RCP_5VSRC BIT(3)
+#define NX20P348X_INT1_SC_5VSRC BIT(2)
+#define NX20P348X_INT1_OC_5VSRC BIT(1)
+#define NX20P348X_INT1_OTP BIT(0)
+
+/* Interrupt 2 Register Bits (0x05) */
+#define NX20P348X_INT2_EN_ERR BIT(7)
+#define NX20P348X_INT2_RCP_HVSNK BIT(6)
+#define NX20P348X_INT2_SC_HVSNK BIT(5)
+#define NX20P348X_INT2_OV_HVSNK BIT(4)
+#define NX20P348X_INT2_RCP_HVSRC BIT(3)
+#define NX20P348X_INT2_SC_HVSRC BIT(2)
+#define NX20P348X_INT2_OC_HVSRC BIT(1)
+#define NX20P348X_INT2_OV_HVSRC BIT(0)
 
 /**
- * Interrupt Handler for the NX20P348x.
+ * Board override for NX20P348X init.
  *
  * @param port: The Type-C port which triggered the interrupt.
  */
-void nx20p348x_interrupt(int port);
+__override_proto int board_nx20p348x_init(int port);
 
 #endif /* defined(__CROS_EC_NX20P348X_H) */
diff --git a/driver/ppc/rt1718s.c b/driver/ppc/rt1718s.c
new file mode 100644
index 0000000000..3accf5d0fa
--- /dev/null
+++ b/driver/ppc/rt1718s.c
@@ -0,0 +1,193 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Richtek RT1718S USB-C Power Path Controller */
+#include "atomic.h"
+#include "common.h"
+#include "config.h"
+#include "console.h"
+#include "driver/ppc/rt1718s.h"
+#include "driver/tcpm/tcpci.h"
+#include "usb_pe_sm.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#define RT1718S_FLAGS_SOURCE_ENABLED BIT(0)
+static atomic_t flags[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+static int read_reg(uint8_t port, int reg, int *val)
+{
+	if (reg > 0xFF) {
+		return i2c_read_offset16(ppc_chips[port].i2c_port,
+					 ppc_chips[port].i2c_addr_flags, reg,
+					 val, 1);
+	} else {
+		return i2c_read8(ppc_chips[port].i2c_port,
+				 ppc_chips[port].i2c_addr_flags, reg, val);
+	}
+}
+
+static int write_reg(uint8_t port, int reg, int val)
+{
+	if (reg > 0xFF) {
+		return i2c_write_offset16(ppc_chips[port].i2c_port,
+					  ppc_chips[port].i2c_addr_flags, reg,
+					  val, 1);
+	} else {
+		return i2c_write8(ppc_chips[port].i2c_port,
+				  ppc_chips[port].i2c_addr_flags, reg, val);
+	}
+}
+
+static int update_bits(int port, int reg, int mask, int val)
+{
+	int reg_val;
+
+	if (mask == 0xFF)
+		return write_reg(port, reg, val);
+
+	RETURN_ERROR(read_reg(port, reg, &reg_val));
+
+	reg_val &= (~mask);
+	reg_val |= (mask & val);
+	return write_reg(port, reg, reg_val);
+}
+
+static int rt1718s_is_sourcing_vbus(int port)
+{
+	return (flags[port] & RT1718S_FLAGS_SOURCE_ENABLED);
+}
+
+static int rt1718s_vbus_source_enable(int port, int enable)
+{
+	if (enable)
+		atomic_or(&flags[port], RT1718S_FLAGS_SOURCE_ENABLED);
+	else
+		atomic_clear_bits(&flags[port], RT1718S_FLAGS_SOURCE_ENABLED);
+
+	RETURN_ERROR(tcpm_set_src_ctrl(port, enable));
+
+#if defined(CONFIG_USB_CHARGER) && defined(CONFIG_USB_PD_VBUS_DETECT_PPC)
+	/*
+	 * Since the VBUS state could be changing here, need to wake the
+	 * USB_CHG_N task so that BC 1.2 detection will be triggered.
+	 */
+	usb_charger_vbus_change(port, enable);
+#endif
+
+	return EC_SUCCESS;
+}
+
+static int rt1718s_vbus_sink_enable(int port, int enable)
+{
+	return tcpm_set_snk_ctrl(port, enable);
+}
+
+static int rt1718s_discharge_vbus(int port, int enable)
+{
+	return update_bits(port, TCPC_REG_POWER_CTRL,
+			   TCPC_REG_POWER_CTRL_FORCE_DISCHARGE,
+			   enable ? 0xFF : 0x00);
+}
+
+#ifdef CONFIG_CMD_PPC_DUMP
+static int rt1718s_dump(int port)
+{
+	for (int i = 0; i <= 0xEF; i++) {
+		int val = 0;
+		int rt = read_reg(port, i, &val);
+
+		if (i % 16 == 0)
+			CPRINTF("%02X: ", i);
+		if (rt)
+			CPRINTF("-- ");
+		else
+			CPRINTF("%02X ", val);
+		if (i % 16 == 15)
+			CPRINTF("\n");
+	}
+	for (int i = 0xF200; i <= 0xF2CF; i++) {
+		int val = 0;
+		int rt = read_reg(port, i, &val);
+
+		if (i % 16 == 0)
+			CPRINTF("%04X: ", i);
+		if (rt)
+			CPRINTF("-- ");
+		else
+			CPRINTF("%02X ", val);
+		if (i % 16 == 15)
+			CPRINTF("\n");
+	}
+
+	return EC_SUCCESS;
+}
+#endif /* defined(CONFIG_CMD_PPC_DUMP) */
+
+#ifdef CONFIG_USB_PD_VBUS_DETECT_PPC
+static int rt1718s_is_vbus_present(int port)
+{
+	__maybe_unused static atomic_t vbus_prev[CONFIG_USB_PD_PORT_MAX_COUNT];
+	int status, vbus;
+
+	if (read_reg(port, TCPC_REG_POWER_STATUS, &status))
+		return 0;
+
+	vbus = !!(status & TCPC_REG_POWER_STATUS_VBUS_PRES);
+
+#ifdef CONFIG_USB_CHARGER
+	if (!!(vbus_prev[port] != vbus))
+		usb_charger_vbus_change(port, vbus);
+
+	if (vbus)
+		atomic_or(&vbus_prev[port], 1);
+	else
+		atomic_clear(&vbus_prev[port]);
+#endif
+
+	return vbus;
+}
+#endif
+
+static int rt1718s_init(int port)
+{
+	atomic_clear(&flags[port]);
+
+	return EC_SUCCESS;
+}
+
+#ifdef CONFIG_USBC_PPC_POLARITY
+static int rt1718s_set_polarity(int port, int polarity)
+{
+	return tcpci_tcpm_set_polarity(port, polarity);
+}
+#endif
+
+const struct ppc_drv rt1718s_ppc_drv = {
+	.init = &rt1718s_init,
+	.is_sourcing_vbus = &rt1718s_is_sourcing_vbus,
+	.vbus_sink_enable = &rt1718s_vbus_sink_enable,
+	.vbus_source_enable = &rt1718s_vbus_source_enable,
+#ifdef CONFIG_CMD_PPC_DUMP
+	.reg_dump = &rt1718s_dump,
+#endif /* defined(CONFIG_CMD_PPC_DUMP) */
+
+#ifdef CONFIG_USB_PD_VBUS_DETECT_PPC
+	.is_vbus_present = &rt1718s_is_vbus_present,
+#endif /* defined(CONFIG_USB_PD_VBUS_DETECT_PPC) */
+	.discharge_vbus = &rt1718s_discharge_vbus,
+#ifdef CONFIG_USBC_PPC_POLARITY
+	.set_polarity = &rt1718s_set_polarity,
+#endif
+#ifdef CONFIG_USBC_PPC_VCONN
+	.set_vconn = &tcpci_tcpm_set_vconn,
+#endif
+#ifdef CONFIG_USB_PD_FRS_PPC
+	.set_frs_enable = rt1718s_set_frs_enable,
+#endif
+};
diff --git a/driver/ppc/rt1718s.h b/driver/ppc/rt1718s.h
new file mode 100644
index 0000000000..e3fd8ac74e
--- /dev/null
+++ b/driver/ppc/rt1718s.h
@@ -0,0 +1,16 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Richtek RT1718S Type-C Power Path Controller */
+
+#ifndef __CROS_EC_PPC_RT1718S_H
+#define __CROS_EC_PPC_RT1718S_H
+
+#include "driver/tcpm/rt1718s.h"
+#include "usbc_ppc.h"
+
+extern const struct ppc_drv rt1718s_ppc_drv;
+
+#endif /* defined(__CROS_EC_PPC_RT1718S_H) */
diff --git a/driver/ppc/rt1739.c b/driver/ppc/rt1739.c
new file mode 100644
index 0000000000..69146c0052
--- /dev/null
+++ b/driver/ppc/rt1739.c
@@ -0,0 +1,561 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Richtek RT1739 USB-C Power Path Controller */
+#include "atomic.h"
+#include "battery.h"
+#include "common.h"
+#include "config.h"
+#include "console.h"
+#include "driver/ppc/rt1739.h"
+#include "driver/tcpm/tcpci.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#if defined(CONFIG_USBC_PPC_VCONN) && !defined(CONFIG_USBC_PPC_POLARITY)
+#error "Can't use set_vconn without set_polarity"
+#endif
+
+#define RT1739_FLAGS_SOURCE_ENABLED BIT(0)
+#define RT1739_FLAGS_FRS_ENABLED BIT(1)
+static atomic_t flags[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+
+static int read_reg(uint8_t port, int reg, int *val)
+{
+	return i2c_read8(ppc_chips[port].i2c_port,
+			 ppc_chips[port].i2c_addr_flags, reg, val);
+}
+
+static int write_reg(uint8_t port, int reg, int val)
+{
+	return i2c_write8(ppc_chips[port].i2c_port,
+			  ppc_chips[port].i2c_addr_flags, reg, val);
+}
+
+static int update_reg(int port, int reg, int mask,
+		      enum mask_update_action action)
+{
+	return i2c_update8(ppc_chips[port].i2c_port,
+			   ppc_chips[port].i2c_addr_flags, reg, mask, action);
+}
+
+static int rt1739_is_sourcing_vbus(int port)
+{
+	return flags[port] & RT1739_FLAGS_SOURCE_ENABLED;
+}
+
+static int rt1739_vbus_source_enable(int port, int enable)
+{
+	atomic_t prev_flag;
+
+	if (enable)
+		prev_flag =
+			atomic_or(&flags[port], RT1739_FLAGS_SOURCE_ENABLED);
+	else
+		prev_flag = atomic_clear_bits(&flags[port],
+					      RT1739_FLAGS_SOURCE_ENABLED);
+
+	/* Return if status doesn't change */
+	if (!!(prev_flag & RT1739_FLAGS_SOURCE_ENABLED) == !!enable)
+		return EC_SUCCESS;
+
+	RETURN_ERROR(update_reg(port, RT1739_REG_VBUS_SWITCH_CTRL,
+				RT1739_LV_SRC_EN,
+				enable ? MASK_SET : MASK_CLR));
+
+#if defined(CONFIG_USB_CHARGER) && defined(CONFIG_USB_PD_VBUS_DETECT_PPC)
+	/*
+	 * Since the VBUS state could be changing here, need to wake the
+	 * USB_CHG_N task so that BC 1.2 detection will be triggered.
+	 */
+	usb_charger_vbus_change(port, enable);
+#endif
+
+	return EC_SUCCESS;
+}
+
+static int rt1739_vbus_sink_enable(int port, int enable)
+{
+	return update_reg(port, RT1739_REG_VBUS_SWITCH_CTRL, RT1739_HV_SNK_EN,
+			  enable ? MASK_SET : MASK_CLR);
+}
+
+#ifdef CONFIG_CMD_PPC_DUMP
+static int rt1739_dump(int port)
+{
+	ccprintf("    ");
+	for (int i = 0; i < 16; i++) {
+		ccprintf("%2X ", i);
+	}
+	ccprintf("\n");
+
+	for (int i = 0; i <= 0x61; i++) {
+		int val = 0;
+		int rt = read_reg(port, i, &val);
+
+		if (i % 16 == 0)
+			ccprintf("%02X: ", i);
+		if (rt)
+			ccprintf("-- ");
+		else
+			ccprintf("%02X ", val);
+		if (i % 16 == 15)
+			ccprintf("\n");
+	}
+	ccprintf("\n");
+
+	return EC_SUCCESS;
+}
+#endif /* defined(CONFIG_CMD_PPC_DUMP) */
+
+#ifdef CONFIG_USB_PD_VBUS_DETECT_PPC
+static int rt1739_is_vbus_present(int port)
+{
+	__maybe_unused static atomic_t vbus_prev[CONFIG_USB_PD_PORT_MAX_COUNT];
+	int status, vbus;
+
+	if (read_reg(port, RT1739_REG_INT_STS4, &status))
+		return 0;
+
+	vbus = !!(status & RT1739_VBUS_PRESENT);
+
+#ifdef CONFIG_USB_CHARGER
+	if (!!(vbus_prev[port] != vbus))
+		usb_charger_vbus_change(port, vbus);
+
+	if (vbus)
+		atomic_or(&vbus_prev[port], 1);
+	else
+		atomic_clear(&vbus_prev[port]);
+#endif
+
+	return vbus;
+}
+#endif
+
+#ifdef CONFIG_USBC_PPC_POLARITY
+static int rt1739_set_polarity(int port, int polarity)
+{
+	return update_reg(port, RT1739_REG_VCONN_CTRL1, RT1739_VCONN_ORIENT,
+			  polarity ? RT1739_VCONN_ORIENT_CC1 :
+				     RT1739_VCONN_ORIENT_CC2);
+}
+#endif
+
+#ifdef CONFIG_USBC_PPC_VCONN
+static int rt1739_set_vconn(int port, int enable)
+{
+	return update_reg(port, RT1739_REG_VCONN_CTRL1, RT1739_VCONN_EN,
+			  enable ? MASK_SET : MASK_CLR);
+}
+#endif
+
+static int rt1739_get_device_id(int port, int *device_id)
+{
+	return read_reg(port, RT1739_REG_DEVICE_ID0, device_id);
+}
+
+static int rt1739_workaround(int port)
+{
+	int device_id, vconn_ctrl4;
+
+	RETURN_ERROR(rt1739_get_device_id(port, &device_id));
+
+	switch (device_id) {
+	case RT1739_DEVICE_ID_ES1:
+		CPRINTS("RT1739 ES1");
+		RETURN_ERROR(update_reg(port, RT1739_REG_SYS_CTRL1,
+					RT1739_OSC640K_FORCE_EN, MASK_SET));
+
+		RETURN_ERROR(write_reg(port, RT1739_VBUS_FAULT_DIS,
+				       RT1739_OVP_DISVBUS_EN |
+					       RT1739_UVLO_DISVBUS_EN |
+					       RT1739_SCP_DISVBUS_EN |
+					       RT1739_OCPS_DISVBUS_EN));
+		RETURN_ERROR(update_reg(port, RT1739_REG_VCONN_CTRL3,
+					RT1739_VCONN_CLIMIT_EN, MASK_SET));
+		break;
+
+	case RT1739_DEVICE_ID_ES2:
+		CPRINTS("RT1739 ES2");
+		/* Disable SWENB test output */
+		/* enter hidden mode */
+		RETURN_ERROR(write_reg(port, 0xF1, 0x62));
+		RETURN_ERROR(write_reg(port, 0xF0, 0x86));
+		/* turn off SWENB output */
+		RETURN_ERROR(write_reg(port, 0xE0, 0x07));
+		/* leave hidden mode */
+		RETURN_ERROR(write_reg(port, 0xF1, 0));
+		RETURN_ERROR(write_reg(port, 0xF0, 0));
+
+		/* Set VBUS to VIN_LV leakage remove setting */
+		RETURN_ERROR(write_reg(port, RT1739_VBUS_FAULT_DIS, 0));
+		RETURN_ERROR(write_reg(port, RT1739_REG_VBUS_CTRL1, 0));
+		RETURN_ERROR(write_reg(port, RT1739_REG_VBUS_SWITCH_CTRL, 0));
+		msleep(5);
+		RETURN_ERROR(write_reg(port, RT1739_REG_VBUS_SWITCH_CTRL,
+				       RT1739_LV_SRC_EN));
+		msleep(5);
+		RETURN_ERROR(write_reg(port, RT1739_REG_VBUS_SWITCH_CTRL, 0));
+		msleep(5);
+		RETURN_ERROR(write_reg(
+			port, RT1739_VBUS_FAULT_DIS,
+			RT1739_OVP_DISVBUS_EN | RT1739_UVLO_DISVBUS_EN |
+				RT1739_RCP_DISVBUS_EN | RT1739_SCP_DISVBUS_EN));
+		RETURN_ERROR(
+			write_reg(port, RT1739_REG_VBUS_CTRL1,
+				  RT1739_HVLV_SCP_EN | RT1739_HVLV_OCRC_EN));
+		RETURN_ERROR(update_reg(port, RT1739_REG_VCONN_CTRL3,
+					RT1739_VCONN_CLIMIT_EN, MASK_SET));
+		break;
+
+	case RT1739_DEVICE_ID_ES4:
+		CPRINTS("RT1739 ES4");
+		RETURN_ERROR(update_reg(port, RT1739_REG_LVHVSW_OV_CTRL,
+					RT1739_OT_SEL_LVL, MASK_CLR));
+		RETURN_ERROR(
+			read_reg(port, RT1739_REG_VCONN_CTRL4, &vconn_ctrl4));
+		vconn_ctrl4 &= ~RT1739_VCONN_OCP_SEL_MASK;
+		vconn_ctrl4 |= RT1739_VCONN_OCP_SEL_600MA;
+		RETURN_ERROR(
+			write_reg(port, RT1739_REG_VCONN_CTRL4, vconn_ctrl4));
+		RETURN_ERROR(update_reg(port, RT1739_REG_VCONN_CTRL3,
+					RT1739_VCONN_CLIMIT_EN, MASK_CLR));
+		break;
+
+	default:
+		CPRINTF("RT1739 unknown device id: %02X", device_id);
+		break;
+	}
+
+	return EC_SUCCESS;
+}
+
+static int rt1739_set_frs_enable(int port, int enable)
+{
+	/* Enable FRS RX detect */
+	RETURN_ERROR(update_reg(port, RT1739_REG_CC_FRS_CTRL1, RT1739_FRS_RX_EN,
+				enable ? MASK_SET : MASK_CLR));
+
+	/*
+	 * To enable FRS, turn on FRS_RX interrupt and disable
+	 * all other interrupts (currently bc1.2 only).
+	 *
+	 * When interrupt triggered, we can always assume it's a FRS
+	 * event without spending extra time to read the flags.
+	 */
+	RETURN_ERROR(update_reg(port, RT1739_REG_INT_MASK5,
+				RT1739_BC12_SNK_DONE_MASK,
+				enable ? MASK_CLR : MASK_SET));
+	RETURN_ERROR(update_reg(port, RT1739_REG_INT_MASK4, RT1739_FRS_RX_MASK,
+				enable ? MASK_SET : MASK_CLR));
+	if (enable)
+		atomic_or(&flags[port], RT1739_FLAGS_FRS_ENABLED);
+	else
+		atomic_clear_bits(&flags[port], RT1739_FLAGS_FRS_ENABLED);
+
+	return EC_SUCCESS;
+}
+
+static int rt1739_src_oc(enum tcpc_rp_value rp)
+{
+	switch (rp) {
+	case TYPEC_RP_3A0:
+		return RT1739_LV_SRC_OCP_SEL_3_3A;
+	case TYPEC_RP_1A5:
+		return RT1739_LV_SRC_OCP_SEL_1_75A;
+	default:
+		return RT1739_LV_SRC_OCP_SEL_1_25A;
+	}
+}
+
+static int rt1739_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	int reg;
+
+	RETURN_ERROR(read_reg(port, RT1739_REG_VBUS_OC_SETTING, &reg));
+	reg = (reg & ~RT1739_LV_SRC_OCP_MASK) | rt1739_src_oc(rp);
+	return write_reg(port, RT1739_REG_VBUS_OC_SETTING, reg);
+}
+
+int rt1739_init(int port)
+{
+	int device_id, oc_setting, sys_ctrl, vbus_switch_ctrl;
+	bool batt_connected = false;
+
+	atomic_clear(&flags[port]);
+
+	RETURN_ERROR(read_reg(port, RT1739_REG_SYS_CTRL, &sys_ctrl));
+	RETURN_ERROR(
+		read_reg(port, RT1739_REG_VBUS_SWITCH_CTRL, &vbus_switch_ctrl));
+
+	if (IS_ENABLED(CONFIG_BATTERY_FUEL_GAUGE)) {
+		batt_connected = (battery_get_disconnect_state() ==
+				  BATTERY_NOT_DISCONNECTED);
+	}
+
+	if (sys_ctrl & RT1739_DEAD_BATTERY) {
+		/*
+		 * Dead battery boot, see b/267412033#comment6 for the init
+		 * sequence.
+		 */
+		RETURN_ERROR(
+			write_reg(port, RT1739_REG_SYS_CTRL,
+				  RT1739_DEAD_BATTERY | RT1739_SHUTDOWN_OFF));
+		rt1739_vbus_sink_enable(port, true);
+		RETURN_ERROR(write_reg(port, RT1739_REG_SYS_CTRL,
+				       RT1739_OT_EN | RT1739_SHUTDOWN_OFF));
+	} else if (batt_connected || !(vbus_switch_ctrl & RT1739_HV_SNK_EN)) {
+		/* b/275294155: reset vbus switch only instead of doing a full
+		 * reset
+		 */
+		RETURN_ERROR(write_reg(port, RT1739_REG_VBUS_SWITCH_CTRL, 0));
+	}
+	RETURN_ERROR(write_reg(port, RT1739_REG_SYS_CTRL,
+			       RT1739_OT_EN | RT1739_SHUTDOWN_OFF));
+
+	RETURN_ERROR(rt1739_workaround(port));
+	RETURN_ERROR(rt1739_set_frs_enable(port, false));
+	RETURN_ERROR(rt1739_set_vconn(port, false));
+	RETURN_ERROR(update_reg(port, RT1739_REG_VBUS_DET_EN,
+				RT1739_VBUS_PRESENT_EN, MASK_SET));
+	RETURN_ERROR(update_reg(port, RT1739_REG_SBU_CTRL_01,
+				RT1739_DM_SWEN | RT1739_DP_SWEN, MASK_SET));
+	RETURN_ERROR(update_reg(port, RT1739_REG_SBU_CTRL_01,
+				RT1739_SBUSW_MUX_SEL, MASK_CLR));
+
+	/* VBUS OVP -> 23V */
+	RETURN_ERROR(write_reg(
+		port, RT1739_REG_VBUS_OV_SETTING,
+		(RT1739_OVP_SEL_23_0V << RT1739_VBUS_OVP_SEL_SHIFT) |
+			(RT1739_OVP_SEL_23_0V << RT1739_VIN_HV_OVP_SEL_SHIFT)));
+	/* VBUS OCP -> 3.3A (or 5.5A for ES2 HV Sink) */
+	RETURN_ERROR(rt1739_get_device_id(port, &device_id));
+	oc_setting = RT1739_OCP_TIMEOUT_SEL_16MS;
+	if (device_id == RT1739_DEVICE_ID_ES2)
+		oc_setting |= RT1739_HV_SINK_OCP_SEL_5_5A;
+	else
+		oc_setting |= RT1739_HV_SINK_OCP_SEL_3_3A;
+#if defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT)
+	oc_setting |= rt1739_src_oc(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT);
+#else
+	oc_setting |= rt1739_src_oc(CONFIG_USB_PD_PULLUP);
+#endif
+	RETURN_ERROR(write_reg(port, RT1739_REG_VBUS_OC_SETTING, oc_setting));
+
+	return EC_SUCCESS;
+}
+
+#ifdef CONFIG_USB_CHARGER
+static int rt1739_get_bc12_ilim(int charge_supplier)
+{
+	switch (charge_supplier) {
+	case CHARGE_SUPPLIER_BC12_DCP:
+	case CHARGE_SUPPLIER_BC12_CDP:
+		return USB_CHARGER_MAX_CURR_MA;
+	case CHARGE_SUPPLIER_BC12_SDP:
+	default:
+		return USB_CHARGER_MIN_CURR_MA;
+	}
+}
+
+static void rt1739_update_charge_manager(int port,
+					 enum charge_supplier new_bc12_type)
+{
+	static enum charge_supplier current_bc12_type = CHARGE_SUPPLIER_NONE;
+
+	if (new_bc12_type != current_bc12_type) {
+		if (current_bc12_type != CHARGE_SUPPLIER_NONE)
+			charge_manager_update_charge(current_bc12_type, port,
+						     NULL);
+
+		if (new_bc12_type != CHARGE_SUPPLIER_NONE) {
+			struct charge_port_info chg = {
+				.current = rt1739_get_bc12_ilim(new_bc12_type),
+				.voltage = USB_CHARGER_VOLTAGE_MV,
+			};
+
+			charge_manager_update_charge(new_bc12_type, port, &chg);
+		}
+
+		current_bc12_type = new_bc12_type;
+	}
+}
+
+static void rt1739_enable_bc12_detection(int port, bool enable)
+{
+	update_reg(port, RT1739_REG_BC12_SNK_FUNC, RT1739_BC12_SNK_EN,
+		   enable ? MASK_SET : MASK_CLR);
+}
+
+static enum charge_supplier rt1739_bc12_get_device_type(int port)
+{
+	int reg, bc12_type;
+
+	if (read_reg(port, RT1739_REG_BC12_STAT, &reg))
+		return CHARGE_SUPPLIER_NONE;
+
+	bc12_type = reg & RT1739_PORT_STAT_MASK;
+	switch (bc12_type) {
+	case RT1739_PORT_STAT_SDP:
+		CPRINTS("BC12 SDP");
+		return CHARGE_SUPPLIER_BC12_SDP;
+	case RT1739_PORT_STAT_CDP:
+		CPRINTS("BC12 CDP");
+		return CHARGE_SUPPLIER_BC12_CDP;
+	case RT1739_PORT_STAT_DCP:
+		CPRINTS("BC12 DCP");
+		return CHARGE_SUPPLIER_BC12_DCP;
+	default:
+		CPRINTS("BC12 UNKNOWN 0x%02X", bc12_type);
+		return CHARGE_SUPPLIER_NONE;
+	}
+}
+
+static void rt1739_usb_charger_task_init(const int port)
+{
+	rt1739_enable_bc12_detection(port, false);
+}
+
+static void rt1739_usb_charger_task_event(const int port, uint32_t evt)
+{
+	bool is_non_pd_sink = !pd_capable(port) &&
+			      !usb_charger_port_is_sourcing_vbus(port) &&
+			      pd_check_vbus_level(port, VBUS_PRESENT);
+
+	/* vbus change, start bc12 detection */
+	if (evt & USB_CHG_EVENT_VBUS) {
+		if (is_non_pd_sink)
+			rt1739_enable_bc12_detection(port, true);
+		else
+			rt1739_update_charge_manager(port,
+						     CHARGE_SUPPLIER_NONE);
+	}
+
+	/* detection done, update charge_manager and stop detection */
+	if (evt & USB_CHG_EVENT_BC12) {
+		enum charge_supplier supplier;
+
+		if (is_non_pd_sink)
+			supplier = rt1739_bc12_get_device_type(port);
+		else
+			supplier = CHARGE_SUPPLIER_NONE;
+		rt1739_update_charge_manager(port, supplier);
+		rt1739_enable_bc12_detection(port, false);
+	}
+}
+#endif /* CONFIG_USB_CHARGER */
+
+static atomic_t pending_events;
+
+void rt1739_deferred_interrupt(void)
+{
+	atomic_t current = atomic_clear(&pending_events);
+
+	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) {
+		int event4, event5;
+
+		if (!(current & BIT(port)))
+			continue;
+
+		if (ppc_chips[port].drv != &rt1739_ppc_drv)
+			continue;
+
+		if (read_reg(port, RT1739_REG_INT_EVENT4, &event4))
+			continue;
+		if (read_reg(port, RT1739_REG_INT_EVENT5, &event5))
+			continue;
+
+#ifdef CONFIG_USB_CHARGER
+		if (event5 & RT1739_BC12_SNK_DONE_INT)
+			usb_charger_task_set_event(port, USB_CHG_EVENT_BC12);
+#endif /* CONFIG_USB_CHARGER */
+
+		/* write to clear EVENT4 since FRS interrupt has been handled */
+		write_reg(port, RT1739_REG_INT_EVENT4, event4);
+		write_reg(port, RT1739_REG_INT_EVENT5, event5);
+	}
+}
+DECLARE_DEFERRED(rt1739_deferred_interrupt);
+
+void rt1739_interrupt(int port)
+{
+	if (flags[port] & RT1739_FLAGS_FRS_ENABLED)
+		pd_got_frs_signal(port);
+
+	atomic_or(&pending_events, BIT(port));
+	hook_call_deferred(&rt1739_deferred_interrupt_data, 0);
+}
+
+/* disconnect SBU, DP, DM when unused to save power */
+void rt1739_pd_connect(void)
+{
+	for (int i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; ++i) {
+		if (ppc_chips[i].drv == &rt1739_ppc_drv && pd_is_connected(i))
+			update_reg(i, RT1739_REG_SBU_CTRL_01,
+				   RT1739_DM_SWEN | RT1739_DP_SWEN |
+					   RT1739_SBU1_SWEN | RT1739_SBU2_SWEN,
+				   MASK_SET);
+	}
+}
+DECLARE_HOOK(HOOK_USB_PD_CONNECT, rt1739_pd_connect, HOOK_PRIO_DEFAULT);
+
+void rt1739_pd_disconnect(void)
+{
+	for (int i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; ++i) {
+		if (ppc_chips[i].drv == &rt1739_ppc_drv &&
+		    pd_is_disconnected(i))
+			update_reg(i, RT1739_REG_SBU_CTRL_01,
+				   RT1739_DM_SWEN | RT1739_DP_SWEN |
+					   RT1739_SBU1_SWEN | RT1739_SBU2_SWEN,
+				   MASK_CLR);
+	}
+}
+DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, rt1739_pd_disconnect, HOOK_PRIO_DEFAULT);
+
+const struct ppc_drv rt1739_ppc_drv = {
+	.init = &rt1739_init,
+	.is_sourcing_vbus = &rt1739_is_sourcing_vbus,
+	.vbus_sink_enable = &rt1739_vbus_sink_enable,
+	.vbus_source_enable = &rt1739_vbus_source_enable,
+#ifdef CONFIG_CMD_PPC_DUMP
+	.reg_dump = &rt1739_dump,
+#endif
+#ifdef CONFIG_USB_PD_VBUS_DETECT_PPC
+	.is_vbus_present = &rt1739_is_vbus_present,
+#endif
+	.set_vbus_source_current_limit = &rt1739_set_vbus_source_current_limit,
+#ifdef CONFIG_USBC_PPC_POLARITY
+	.set_polarity = &rt1739_set_polarity,
+#endif
+#ifdef CONFIG_USBC_PPC_VCONN
+	.set_vconn = &rt1739_set_vconn,
+#endif
+#ifdef CONFIG_USB_PD_FRS_PPC
+	.set_frs_enable = &rt1739_set_frs_enable,
+#endif
+	.interrupt = &rt1739_interrupt,
+};
+
+#ifdef CONFIG_USB_CHARGER
+const struct bc12_drv rt1739_bc12_drv = {
+	.usb_charger_task_init = rt1739_usb_charger_task_init,
+	.usb_charger_task_event = rt1739_usb_charger_task_event,
+};
+
+#ifdef CONFIG_BC12_SINGLE_DRIVER
+/* provide a default bc12_ports[] for backward compatibility */
+struct bc12_config bc12_ports[CHARGE_PORT_COUNT] = {
+	[0 ... (CHARGE_PORT_COUNT - 1)] = {
+		.drv = &rt1739_bc12_drv,
+	},
+};
+#endif /* CONFIG_BC12_SINGLE_DRIVER */
+#endif /* CONFIG_USB_CHARGER */
diff --git a/driver/ppc/rt1739.h b/driver/ppc/rt1739.h
new file mode 100644
index 0000000000..5edc35080c
--- /dev/null
+++ b/driver/ppc/rt1739.h
@@ -0,0 +1,156 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Richtek RT1739 Type-C Power Path Controller */
+
+#ifndef __CROS_EC_PPC_RT1739_H
+#define __CROS_EC_PPC_RT1739_H
+
+#include "usb_charge.h"
+#include "usbc_ppc.h"
+
+#define RT1739_ADDR1_FLAGS 0x70
+#define RT1739_ADDR2_FLAGS 0x71
+#define RT1739_ADDR3_FLAGS 0x72
+#define RT1739_ADDR4_FLAGS 0x73
+
+#define RT1739_REG_DEVICE_ID0 0x02
+#define RT1739_DEVICE_ID_ES1 0x11
+#define RT1739_DEVICE_ID_ES2 0x12
+#define RT1739_DEVICE_ID_ES4 0x14
+
+#define RT1739_REG_SW_RESET 0x04
+#define RT1739_SW_RESET BIT(0)
+
+#define RT1739_REG_INT_MASK4 0x0C
+#define RT1739_FRS_RX_MASK BIT(4)
+
+#define RT1739_REG_INT_MASK5 0x0D
+#define RT1739_BC12_SNK_DONE_MASK BIT(0)
+
+#define RT1739_REG_INT_EVENT4 0x14
+
+#define RT1739_REG_INT_EVENT5 0x15
+#define RT1739_BC12_SNK_DONE_INT BIT(0)
+
+#define RT1739_REG_INT_STS4 0x1C
+#define RT1739_VBUS_VALID BIT(2)
+#define RT1739_VBUS_PRESENT BIT(0)
+
+#define RT1739_REG_SYS_CTRL 0x20
+#define RT1739_OT_EN BIT(4)
+#define RT1739_DEAD_BATTERY BIT(1)
+#define RT1739_SHUTDOWN_OFF BIT(0)
+
+#define RT1739_REG_VBUS_SWITCH_CTRL 0x21
+#define RT1739_LV_SRC_EN BIT(2)
+#define RT1739_HV_SRC_EN BIT(1)
+#define RT1739_HV_SNK_EN BIT(0)
+
+#define RT1739_REG_VBUS_CTRL1 0x23
+#define RT1739_HVLV_SCP_EN BIT(1)
+#define RT1739_HVLV_OCRC_EN BIT(0)
+
+#define RT1739_REG_VBUS_OV_SETTING 0x24
+
+#define RT1739_VBUS_OVP_SEL_SHIFT 0
+#define RT1739_VIN_HV_OVP_SEL_SHIFT 4
+#define RT1739_OVP_SEL_6_0V 0
+#define RT1739_OVP_SEL_6_8V 1
+#define RT1739_OVP_SEL_10_0V 2
+#define RT1739_OVP_SEL_11_5V 3
+#define RT1739_OVP_SEL_14_0V 4
+#define RT1739_OVP_SEL_17_0V 5
+#define RT1739_OVP_SEL_23_0V 6
+
+#define RT1739_REG_VBUS_OC_SETTING 0x25
+
+#define RT1739_OCP_TIMEOUT_SEL_SHIFT 6
+#define RT1739_OCP_TIMEOUT_SEL_0_5MS (0 << RT1739_OCP_TIMEOUT_SEL_SHIFT)
+#define RT1739_OCP_TIMEOUT_SEL_1MS (1 << RT1739_OCP_TIMEOUT_SEL_SHIFT)
+#define RT1739_OCP_TIMEOUT_SEL_8MS (2 << RT1739_OCP_TIMEOUT_SEL_SHIFT)
+#define RT1739_OCP_TIMEOUT_SEL_16MS (3 << RT1739_OCP_TIMEOUT_SEL_SHIFT)
+
+#define RT1739_LV_SRC_OCP_SHIFT 4
+#define RT1739_LV_SRC_OCP_MASK (3 << RT1739_LV_SRC_OCP_SHIFT)
+#define RT1739_LV_SRC_OCP_SEL_1_25A (0 << RT1739_LV_SRC_OCP_SHIFT)
+#define RT1739_LV_SRC_OCP_SEL_1_75A (1 << RT1739_LV_SRC_OCP_SHIFT)
+#define RT1739_LV_SRC_OCP_SEL_2_25A (2 << RT1739_LV_SRC_OCP_SHIFT)
+#define RT1739_LV_SRC_OCP_SEL_3_3A (3 << RT1739_LV_SRC_OCP_SHIFT)
+
+#define RT1739_HV_SINK_OCP_SHIFT 0
+#define RT1739_HV_SINK_OCP_SEL_1_25A (0 << RT1739_HV_SINK_OCP_SHIFT)
+#define RT1739_HV_SINK_OCP_SEL_1_75A (1 << RT1739_HV_SINK_OCP_SHIFT)
+#define RT1739_HV_SINK_OCP_SEL_3_3A (2 << RT1739_HV_SINK_OCP_SHIFT)
+#define RT1739_HV_SINK_OCP_SEL_5_5A (3 << RT1739_HV_SINK_OCP_SHIFT)
+
+#define RT1739_VBUS_FAULT_DIS 0x26
+#define RT1739_OVP_DISVBUS_EN BIT(6)
+#define RT1739_UVLO_DISVBUS_EN BIT(5)
+#define RT1739_SRCP_DISVBUS_EN BIT(4)
+#define RT1739_RCP_DISVBUS_EN BIT(3)
+#define RT1739_SCP_DISVBUS_EN BIT(2)
+#define RT1739_OCPS_DISVBUS_EN BIT(1)
+#define RT1739_OCP_DISVBUS_EN BIT(0)
+
+#define RT1739_REG_VBUS_DET_EN 0x27
+#define RT1739_VBUS_SAFE5V_EN BIT(2)
+#define RT1739_VBUS_SAFE0V_EN BIT(1)
+#define RT1739_VBUS_PRESENT_EN BIT(0)
+
+#define RT1739_REG_CC_FRS_CTRL1 0x2D
+#define RT1739_FRS_RX_EN BIT(1)
+
+#define RT1739_REG_VCONN_CTRL1 0x31
+#define RT1739_VCONN_ORIENT BIT(1)
+#define RT1739_VCONN_EN BIT(0)
+
+#define RT1739_VCONN_ORIENT_CC1 MASK_SET
+#define RT1739_VCONN_ORIENT_CC2 MASK_CLR
+
+#define RT1739_REG_VCONN_CTRL3 0x33
+#define RT1739_VCONN_CLIMIT_EN BIT(0)
+
+#define RT1739_REG_VCONN_CTRL4 0x34
+#define RT1739_VCONN_OCP_SEL_SHIFT 2
+#define RT1739_VCONN_OCP_SEL_MASK (7 << RT1739_VCONN_OCP_SEL_SHIFT)
+#define RT1739_VCONN_OCP_SEL_200MA (1 << RT1739_VCONN_OCP_SEL_SHIFT)
+#define RT1739_VCONN_OCP_SEL_300MA (2 << RT1739_VCONN_OCP_SEL_SHIFT)
+#define RT1739_VCONN_OCP_SEL_400MA (3 << RT1739_VCONN_OCP_SEL_SHIFT)
+#define RT1739_VCONN_OCP_SEL_500MA (4 << RT1739_VCONN_OCP_SEL_SHIFT)
+#define RT1739_VCONN_OCP_SEL_600MA (5 << RT1739_VCONN_OCP_SEL_SHIFT)
+#define RT1739_VCONN_OCP_SEL_700MA (6 << RT1739_VCONN_OCP_SEL_SHIFT)
+#define RT1739_VCONN_OCP_SEL_800MA (7 << RT1739_VCONN_OCP_SEL_SHIFT)
+
+#define RT1739_REG_LVHVSW_OV_CTRL 0x36
+#define RT1739_OT_SEL_LVL BIT(1)
+
+#define RT1739_REG_SBU_CTRL_01 0x38
+#define RT1739_SBUSW_MUX_SEL BIT(4)
+#define RT1739_SBU2_SWEN BIT(3)
+#define RT1739_SBU1_SWEN BIT(2)
+#define RT1739_DM_SWEN BIT(1)
+#define RT1739_DP_SWEN BIT(0)
+
+#define RT1739_REG_BC12_SNK_FUNC 0x40
+#define RT1739_BC12_SNK_EN BIT(7)
+
+#define RT1739_REG_BC12_STAT 0x41
+#define RT1739_PORT_STAT_MASK 0x0F
+#define RT1739_PORT_STAT_SDP 0x0D
+#define RT1739_PORT_STAT_CDP 0x0E
+#define RT1739_PORT_STAT_DCP 0x0F
+
+#define RT1739_REG_SYS_CTRL1 0x60
+#define RT1739_OSC640K_FORCE_EN BIT(3)
+
+extern const struct ppc_drv rt1739_ppc_drv;
+extern const struct bc12_drv rt1739_bc12_drv;
+
+void rt1739_interrupt(int port);
+
+int rt1739_init(int port);
+
+#endif /* defined(__CROS_EC_PPC_RT1739_H) */
diff --git a/driver/ppc/sn5s330.c b/driver/ppc/sn5s330.c
index 0de09ca60d..9404c8df76 100644
--- a/driver/ppc/sn5s330.c
+++ b/driver/ppc/sn5s330.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,37 +12,33 @@
 
 #include "common.h"
 #include "console.h"
-#include "driver/ppc/sn5s330.h"
 #include "hooks.h"
 #include "i2c.h"
+#include "sn5s330.h"
 #include "system.h"
 #include "timer.h"
 #include "usb_charge.h"
-#include "usb_pd_tcpm.h"
 #include "usb_pd.h"
+#include "usb_pd_tcpm.h"
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
-static uint32_t irq_pending; /* Bitmask of ports signaling an interrupt. */
+static atomic_t irq_pending; /* Bitmask of ports signaling an interrupt. */
 static int source_enabled[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 static int read_reg(uint8_t port, int reg, int *regval)
 {
 	return i2c_read8(ppc_chips[port].i2c_port,
-			 ppc_chips[port].i2c_addr_flags,
-			 reg,
-			 regval);
+			 ppc_chips[port].i2c_addr_flags, reg, regval);
 }
 
 static int write_reg(uint8_t port, int reg, int regval)
 {
 	return i2c_write8(ppc_chips[port].i2c_port,
-			  ppc_chips[port].i2c_addr_flags,
-			  reg,
-			  regval);
+			  ppc_chips[port].i2c_addr_flags, reg, regval);
 }
 
 static int set_flags(const int port, const int addr, const int flags_to_set)
@@ -58,7 +54,6 @@ static int set_flags(const int port, const int addr, const int flags_to_set)
 	return write_reg(port, addr, val);
 }
 
-
 static int clr_flags(const int port, const int addr, const int flags_to_clear)
 {
 	int val, rv;
@@ -85,9 +80,7 @@ static int sn5s330_dump(int port)
 	for (i = SN5S330_FUNC_SET1; i <= SN5S330_FUNC_SET12; i++) {
 		i2c_read8(i2c_port, i2c_addr_flags, i, &data);
 		ccprintf("FUNC_SET%d [%02Xh] = 0x%02x\n",
-			 i - SN5S330_FUNC_SET1 + 1,
-			 i,
-			 data);
+			 i - SN5S330_FUNC_SET1 + 1, i, data);
 	}
 
 	cflush();
@@ -95,9 +88,7 @@ static int sn5s330_dump(int port)
 	for (i = SN5S330_INT_STATUS_REG1; i <= SN5S330_INT_STATUS_REG4; i++) {
 		i2c_read8(i2c_port, i2c_addr_flags, i, &data);
 		ccprintf("INT_STATUS_REG%d [%02Xh] = 0x%02x\n",
-			 i - SN5S330_INT_STATUS_REG1 + 1,
-			 i,
-			 data);
+			 i - SN5S330_INT_STATUS_REG1 + 1, i, data);
 	}
 
 	cflush();
@@ -106,9 +97,7 @@ static int sn5s330_dump(int port)
 	     i++) {
 		i2c_read8(i2c_port, i2c_addr_flags, i, &data);
 		ccprintf("INT_TRIP_RISE_REG%d [%02Xh] = 0x%02x\n",
-			 i - SN5S330_INT_TRIP_RISE_REG1 + 1,
-			 i,
-			 data);
+			 i - SN5S330_INT_TRIP_RISE_REG1 + 1, i, data);
 	}
 
 	cflush();
@@ -117,9 +106,7 @@ static int sn5s330_dump(int port)
 	     i++) {
 		i2c_read8(i2c_port, i2c_addr_flags, i, &data);
 		ccprintf("INT_TRIP_FALL_REG%d [%02Xh] = 0x%02x\n",
-			 i - SN5S330_INT_TRIP_FALL_REG1 + 1,
-			 i,
-			 data);
+			 i - SN5S330_INT_TRIP_FALL_REG1 + 1, i, data);
 	}
 
 	cflush();
@@ -128,9 +115,7 @@ static int sn5s330_dump(int port)
 	     i++) {
 		i2c_read8(i2c_port, i2c_addr_flags, i, &data);
 		ccprintf("INT_MASK_RISE_REG%d [%02Xh] = 0x%02x\n",
-			 i - SN5S330_INT_MASK_RISE_REG1 + 1,
-			 i,
-			 data);
+			 i - SN5S330_INT_MASK_RISE_REG1 + 1, i, data);
 	}
 
 	cflush();
@@ -139,9 +124,7 @@ static int sn5s330_dump(int port)
 	     i++) {
 		i2c_read8(i2c_port, i2c_addr_flags, i, &data);
 		ccprintf("INT_MASK_FALL_REG%d [%02Xh] = 0x%02x\n",
-			 i - SN5S330_INT_MASK_FALL_REG1 + 1,
-			 i,
-			 data);
+			 i - SN5S330_INT_MASK_FALL_REG1 + 1, i, data);
 	}
 
 	cflush();
@@ -160,11 +143,13 @@ static int sn5s330_pp_fet_enable(uint8_t port, enum sn5s330_pp_idx pp,
 		pp_bit = SN5S330_PP1_EN;
 	else if (pp == SN5S330_PP2)
 		pp_bit = SN5S330_PP2_EN;
+	/* LCOV_EXCL_START - this branch unreachable in unit tests. */
 	else
 		return EC_ERROR_INVAL;
+	/* LCOV_EXCL_STOP */
 
-	status = enable ? set_flags(port, SN5S330_FUNC_SET3, pp_bit)
-			: clr_flags(port, SN5S330_FUNC_SET3, pp_bit);
+	status = enable ? set_flags(port, SN5S330_FUNC_SET3, pp_bit) :
+			  clr_flags(port, SN5S330_FUNC_SET3, pp_bit);
 
 	if (status) {
 		ppc_prints("Failed to set FUNC_SET3!", port);
@@ -183,7 +168,7 @@ static int sn5s330_init(int port)
 	int status;
 	int retries;
 	int reg;
-	const int i2c_port  = ppc_chips[port].i2c_port;
+	const int i2c_port = ppc_chips[port].i2c_port;
 	const uint16_t i2c_addr_flags = ppc_chips[port].i2c_addr_flags;
 
 #ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
@@ -211,11 +196,10 @@ static int sn5s330_init(int port)
 	 */
 	retries = 0;
 	do {
-		status = i2c_write8(i2c_port, i2c_addr_flags,
-				    SN5S330_FUNC_SET1, regval);
+		status = i2c_write8(i2c_port, i2c_addr_flags, SN5S330_FUNC_SET1,
+				    regval);
 		if (status) {
-			ppc_prints("Failed to set FUNC_SET1! Retrying..",
-				port);
+			ppc_prints("Failed to set FUNC_SET1! Retrying..", port);
 			retries++;
 			msleep(1);
 		} else {
@@ -225,24 +209,24 @@ static int sn5s330_init(int port)
 
 	/* Set Vbus OVP threshold to ~22.325V. */
 	regval = 0x37;
-	status = i2c_write8(i2c_port, i2c_addr_flags,
-			    SN5S330_FUNC_SET5, regval);
+	status =
+		i2c_write8(i2c_port, i2c_addr_flags, SN5S330_FUNC_SET5, regval);
 	if (status) {
 		ppc_prints("Failed to set FUNC_SET5!", port);
 		return status;
 	}
 
 	/* Set Vbus UVP threshold to ~2.75V. */
-	status = i2c_read8(i2c_port, i2c_addr_flags,
-			   SN5S330_FUNC_SET6, &regval);
+	status =
+		i2c_read8(i2c_port, i2c_addr_flags, SN5S330_FUNC_SET6, &regval);
 	if (status) {
 		ppc_prints("Failed to read FUNC_SET6!", port);
 		return status;
 	}
 	regval &= ~0x3F;
 	regval |= 1;
-	status = i2c_write8(i2c_port, i2c_addr_flags,
-			    SN5S330_FUNC_SET6, regval);
+	status =
+		i2c_write8(i2c_port, i2c_addr_flags, SN5S330_FUNC_SET6, regval);
 	if (status) {
 		ppc_prints("Failed to write FUNC_SET6!", port);
 		return status;
@@ -250,8 +234,8 @@ static int sn5s330_init(int port)
 
 	/* Enable SBU Fets and set PP2 current limit to ~3A. */
 	regval = SN5S330_SBU_EN | 0x8;
-	status = i2c_write8(i2c_port, i2c_addr_flags,
-			    SN5S330_FUNC_SET2, regval);
+	status =
+		i2c_write8(i2c_port, i2c_addr_flags, SN5S330_FUNC_SET2, regval);
 	if (status) {
 		ppc_prints("Failed to set FUNC_SET2!", port);
 		return status;
@@ -270,8 +254,8 @@ static int sn5s330_init(int port)
 	 * low voltage protection).
 	 */
 	regval = SN5S330_OVP_EN_CC | SN5S330_PP2_CONFIG | SN5S330_CONFIG_UVP;
-	status = i2c_write8(i2c_port, i2c_addr_flags,
-			    SN5S330_FUNC_SET9, regval);
+	status =
+		i2c_write8(i2c_port, i2c_addr_flags, SN5S330_FUNC_SET9, regval);
 	if (status) {
 		ppc_prints("Failed to set FUNC_SET9!", port);
 		return status;
@@ -282,7 +266,7 @@ static int sn5s330_init(int port)
 	 * set 1000 us for PP2 for compatibility.
 	 */
 	regval = (PPX_ILIM_DEGLITCH_0_US_200 << 3) |
-		  PPX_ILIM_DEGLITCH_0_US_1000;
+		 PPX_ILIM_DEGLITCH_0_US_1000;
 	status = i2c_write8(i2c_port, i2c_addr_flags, SN5S330_FUNC_SET11,
 			    regval);
 	if (status) {
@@ -297,16 +281,16 @@ static int sn5s330_init(int port)
 	 * reset default (20 us).
 	 */
 	regval = 0;
-	status = i2c_read8(i2c_port, i2c_addr_flags,
-			   SN5S330_FUNC_SET8, &regval);
+	status =
+		i2c_read8(i2c_port, i2c_addr_flags, SN5S330_FUNC_SET8, &regval);
 	if (status) {
 		ppc_prints("Failed to read FUNC_SET8!", port);
 		return status;
 	}
 	regval &= ~SN5S330_VCONN_DEGLITCH_MASK;
 	regval |= SN5S330_VCONN_DEGLITCH_640_US;
-	status = i2c_write8(i2c_port, i2c_addr_flags,
-			    SN5S330_FUNC_SET8, regval);
+	status =
+		i2c_write8(i2c_port, i2c_addr_flags, SN5S330_FUNC_SET8, regval);
 	if (status) {
 		ppc_prints("Failed to set FUNC_SET8!", port);
 		return status;
@@ -333,10 +317,22 @@ static int sn5s330_init(int port)
 		return status;
 	}
 
+	/*
+	 * Set RCP voltage threshold to 3mV instead of 6mV default for the
+	 * source path. This modification helps prevent false RCP triggers
+	 * against certain port partners when VBUS is set to 20V.
+	 */
+	status = clr_flags(port, SN5S330_FUNC_SET10, SN5S330_PP1_RCP_OFFSET);
+	if (status) {
+		ppc_prints("Failed to set FUNC_SET10!", port);
+		return status;
+	}
+
 	/* Turn off PP1 FET. */
 	status = sn5s330_pp_fet_enable(port, SN5S330_PP1, 0);
 	if (status) {
 		ppc_prints("Failed to turn off PP1 FET!", port);
+		return status;
 	}
 
 	/*
@@ -352,8 +348,8 @@ static int sn5s330_init(int port)
 	 * is checked below.
 	 */
 	regval = SN5S330_DIG_RES | SN5S330_VSAFE0V_MASK;
-	status = i2c_write8(i2c_port, i2c_addr_flags,
-			    SN5S330_INT_STATUS_REG4, regval);
+	status = i2c_write8(i2c_port, i2c_addr_flags, SN5S330_INT_STATUS_REG4,
+			    regval);
 	if (status) {
 		ppc_prints("Failed to write INT_STATUS_REG4!", port);
 		return status;
@@ -404,7 +400,7 @@ static int sn5s330_init(int port)
 	regval = ~SN5S330_VBUS_GOOD_MASK;
 #else
 	regval = 0xFF;
-#endif  /* CONFIG_USB_PD_VBUS_DETECT_PPC && CONFIG_USB_CHARGER */
+#endif /* CONFIG_USB_PD_VBUS_DETECT_PPC && CONFIG_USB_CHARGER */
 
 	status = i2c_write8(i2c_port, i2c_addr_flags,
 			    SN5S330_INT_MASK_RISE_REG3, regval);
@@ -422,24 +418,21 @@ static int sn5s330_init(int port)
 
 	/* Now clear any pending interrupts. */
 	for (reg = SN5S330_INT_TRIP_RISE_REG1;
-	     reg <= SN5S330_INT_TRIP_FALL_REG3;
-	     reg++) {
-		status = i2c_write8(i2c_port, i2c_addr_flags,
-				    reg, 0xFF);
+	     reg <= SN5S330_INT_TRIP_FALL_REG3; reg++) {
+		status = i2c_write8(i2c_port, i2c_addr_flags, reg, 0xFF);
 		if (status) {
-			CPRINTS("ppc p%d: Failed to write reg 0x%2x!",
-				port, reg);
+			CPRINTS("ppc p%d: Failed to write reg 0x%2x!", port,
+				reg);
 			return status;
 		}
 	}
 
-
 	/*
 	 * For PP2, check to see if we booted in dead battery mode.  If we
 	 * booted in dead battery mode, the PP2 FET will already be enabled.
 	 */
-	status = i2c_read8(i2c_port, i2c_addr_flags,
-			   SN5S330_INT_STATUS_REG4, &regval);
+	status = i2c_read8(i2c_port, i2c_addr_flags, SN5S330_INT_STATUS_REG4,
+			   &regval);
 	if (status) {
 		ppc_prints("Failed to read INT_STATUS_REG4!", port);
 		return status;
@@ -450,10 +443,17 @@ static int sn5s330_init(int port)
 		 * Clear the bit by writing 1 and keep vSafe0V_MASK
 		 * unchanged.
 		 */
-		i2c_write8(i2c_port, i2c_addr_flags,
-			   SN5S330_INT_STATUS_REG4, regval);
+		i2c_write8(i2c_port, i2c_addr_flags, SN5S330_INT_STATUS_REG4,
+			   regval);
+
+		/*
+		 * Turn on PP2 FET.
+		 * Although PP2 FET is already enabled during dead batter boot
+		 * by the spec, we force that state here.
+		 *
+		 * TODO(207034759): Verify need or remove redundant PP2 set.
+		 */
 
-		/* Turn on PP2 FET. */
 		status = sn5s330_pp_fet_enable(port, SN5S330_PP2, 1);
 		if (status) {
 			ppc_prints("Failed to turn on PP2 FET!", port);
@@ -522,8 +522,10 @@ static int sn5s330_set_vbus_source_current_limit(int port,
 		regval |= SN5S330_ILIM_1_62;
 		break;
 
+	/* USB minimum source current is 0.5A */
 	case TYPEC_RP_USB:
 	default:
+		/* SN5S330 Defaults to USB associated limits */
 		regval |= SN5S330_ILIM_0_63;
 		break;
 	};
@@ -536,13 +538,13 @@ static int sn5s330_set_vbus_source_current_limit(int port,
 static int sn5s330_discharge_vbus(int port, int enable)
 {
 	int status = enable ? set_flags(port, SN5S330_FUNC_SET3,
-					SN5S330_VBUS_DISCH_EN)
-			    : clr_flags(port, SN5S330_FUNC_SET3,
+					SN5S330_VBUS_DISCH_EN) :
+			      clr_flags(port, SN5S330_FUNC_SET3,
 					SN5S330_VBUS_DISCH_EN);
 
 	if (status) {
-		CPRINTS("ppc p%d: Failed to %s vbus discharge",
-			port, enable ? "enable" : "disable");
+		CPRINTS("ppc p%d: Failed to %s vbus discharge", port,
+			enable ? "enable" : "disable");
 		return status;
 	}
 
@@ -658,7 +660,8 @@ static void sn5s330_handle_interrupt(int port)
 
 		if (attempt > 1)
 			ppc_prints("Could not clear interrupts on first "
-				"try, retrying", port);
+				   "try, retrying",
+				   port);
 
 		read_reg(port, SN5S330_INT_TRIP_RISE_REG1, &rise);
 		read_reg(port, SN5S330_INT_TRIP_FALL_REG1, &fall);
@@ -696,23 +699,22 @@ static void sn5s330_handle_interrupt(int port)
 		read_reg(port, SN5S330_INT_TRIP_FALL_REG3, &fall);
 
 		/* Inform other modules about VBUS level */
-		if (rise & SN5S330_VBUS_GOOD_MASK
-		    || fall & SN5S330_VBUS_GOOD_MASK)
+		if (rise & SN5S330_VBUS_GOOD_MASK ||
+		    fall & SN5S330_VBUS_GOOD_MASK)
 			usb_charger_vbus_change(port,
 						sn5s330_is_vbus_present(port));
 
 		/* Clear the interrupt sources. */
 		write_reg(port, SN5S330_INT_TRIP_RISE_REG3, rise);
 		write_reg(port, SN5S330_INT_TRIP_FALL_REG3, fall);
-#endif  /* CONFIG_USB_PD_VBUS_DETECT_PPC && CONFIG_USB_CHARGER */
-
+#endif /* CONFIG_USB_PD_VBUS_DETECT_PPC && CONFIG_USB_CHARGER */
 	}
 }
 
 static void sn5s330_irq_deferred(void)
 {
 	int i;
-	uint32_t pending = deprecated_atomic_read_clear(&irq_pending);
+	uint32_t pending = atomic_clear(&irq_pending);
 
 	for (i = 0; i < board_get_usb_pd_port_count(); i++)
 		if (BIT(i) & pending)
@@ -722,7 +724,7 @@ DECLARE_DEFERRED(sn5s330_irq_deferred);
 
 void sn5s330_interrupt(int port)
 {
-	deprecated_atomic_or(&irq_pending, BIT(port));
+	atomic_or(&irq_pending, BIT(port));
 	hook_call_deferred(&sn5s330_irq_deferred_data, 0);
 }
 
@@ -749,4 +751,5 @@ const struct ppc_drv sn5s330_drv = {
 #ifdef CONFIG_USBC_PPC_VCONN
 	.set_vconn = &sn5s330_set_vconn,
 #endif
+	.interrupt = &sn5s330_interrupt,
 };
diff --git a/driver/ppc/sn5s330.h b/driver/ppc/sn5s330.h
index 94d0ab0f1e..3748370007 100644
--- a/driver/ppc/sn5s330.h
+++ b/driver/ppc/sn5s330.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,6 +9,7 @@
 #define __CROS_EC_SN5S330_H
 
 #include "common.h"
+#include "driver/ppc/sn5s330_public.h"
 
 struct sn5s330_config {
 	uint8_t i2c_port;
@@ -25,20 +26,15 @@ enum sn5s330_pp_idx {
 	SN5S330_PP_COUNT,
 };
 
-#define SN5S330_ADDR0_FLAGS 0x40
-#define SN5S330_ADDR1_FLAGS 0x41
-#define SN5S330_ADDR2_FLAGS 0x42
-#define SN5S330_ADDR3_FLAGS 0x43
-
-#define SN5S330_FUNC_SET1  0x50
-#define SN5S330_FUNC_SET2  0x51
-#define SN5S330_FUNC_SET3  0x52
-#define SN5S330_FUNC_SET4  0x53
-#define SN5S330_FUNC_SET5  0x54
-#define SN5S330_FUNC_SET6  0x55
-#define SN5S330_FUNC_SET7  0x56
-#define SN5S330_FUNC_SET8  0x57
-#define SN5S330_FUNC_SET9  0x58
+#define SN5S330_FUNC_SET1 0x50
+#define SN5S330_FUNC_SET2 0x51
+#define SN5S330_FUNC_SET3 0x52
+#define SN5S330_FUNC_SET4 0x53
+#define SN5S330_FUNC_SET5 0x54
+#define SN5S330_FUNC_SET6 0x55
+#define SN5S330_FUNC_SET7 0x56
+#define SN5S330_FUNC_SET8 0x57
+#define SN5S330_FUNC_SET9 0x58
 #define SN5S330_FUNC_SET10 0x59
 #define SN5S330_FUNC_SET11 0x5A
 #define SN5S330_FUNC_SET12 0x5B
@@ -46,6 +42,9 @@ enum sn5s330_pp_idx {
 #define SN5S330_INT_STATUS_REG1 0x2F
 #define SN5S330_INT_STATUS_REG2 0x30
 #define SN5S330_INT_STATUS_REG3 0x31
+/*
+ * TODO(b:205754232): Register name discrepancy
+ */
 #define SN5S330_INT_STATUS_REG4 0x32
 
 #define SN5S330_INT_TRIP_RISE_REG1 0x20
@@ -62,68 +61,72 @@ enum sn5s330_pp_idx {
 #define SN5S330_INT_MASK_FALL_REG2 0x2A
 #define SN5S330_INT_MASK_FALL_REG3 0x2B
 
-#define PPX_ILIM_DEGLITCH_0_US_20     0x1
-#define PPX_ILIM_DEGLITCH_0_US_50     0x2
-#define PPX_ILIM_DEGLITCH_0_US_100    0x3
-#define PPX_ILIM_DEGLITCH_0_US_200    0x4
-#define PPX_ILIM_DEGLITCH_0_US_1000   0x5
-#define PPX_ILIM_DEGLITCH_0_US_2000   0x6
-#define PPX_ILIM_DEGLITCH_0_US_10000  0x7
+#define PPX_ILIM_DEGLITCH_0_US_20 0x1
+#define PPX_ILIM_DEGLITCH_0_US_50 0x2
+#define PPX_ILIM_DEGLITCH_0_US_100 0x3
+#define PPX_ILIM_DEGLITCH_0_US_200 0x4
+#define PPX_ILIM_DEGLITCH_0_US_1000 0x5
+#define PPX_ILIM_DEGLITCH_0_US_2000 0x6
+#define PPX_ILIM_DEGLITCH_0_US_10000 0x7
 
 /* Internal VBUS Switch Current Limit Settings (min) */
-#define SN5S330_ILIM_0_35  0
-#define SN5S330_ILIM_0_63  1
-#define SN5S330_ILIM_0_90  2
-#define SN5S330_ILIM_1_14  3
-#define SN5S330_ILIM_1_38  4
-#define SN5S330_ILIM_1_62  5
-#define SN5S330_ILIM_1_86  6
-#define SN5S330_ILIM_2_10  7
-#define SN5S330_ILIM_2_34  8
-#define SN5S330_ILIM_2_58  9
-#define SN5S330_ILIM_2_82  10
-#define SN5S330_ILIM_3_06  11
-#define SN5S330_ILIM_3_30  12
+#define SN5S330_ILIM_0_35 0
+#define SN5S330_ILIM_0_63 1
+#define SN5S330_ILIM_0_90 2
+#define SN5S330_ILIM_1_14 3
+#define SN5S330_ILIM_1_38 4
+#define SN5S330_ILIM_1_62 5
+#define SN5S330_ILIM_1_86 6
+#define SN5S330_ILIM_2_10 7
+#define SN5S330_ILIM_2_34 8
+#define SN5S330_ILIM_2_58 9
+#define SN5S330_ILIM_2_82 10
+#define SN5S330_ILIM_3_06 11
+#define SN5S330_ILIM_3_30 12
 
 /* FUNC_SET_2 */
-#define SN5S330_SBU_EN			BIT(4)
+#define SN5S330_SBU_EN BIT(4)
 
 /* FUNC_SET_3 */
-#define SN5S330_PP1_EN			BIT(0)
-#define SN5S330_PP2_EN			BIT(1)
-#define SN5S330_VBUS_DISCH_EN		BIT(2)
-#define SN5S330_SET_RCP_MODE_PP1	BIT(5)
-#define SN5S330_SET_RCP_MODE_PP2	BIT(6)
+#define SN5S330_PP1_EN BIT(0)
+#define SN5S330_PP2_EN BIT(1)
+#define SN5S330_VBUS_DISCH_EN BIT(2)
+#define SN5S330_SET_RCP_MODE_PP1 BIT(5)
+#define SN5S330_SET_RCP_MODE_PP2 BIT(6)
 
 /* FUNC_SET_4 */
-#define SN5S330_VCONN_EN		BIT(0)
-#define SN5S330_CC_POLARITY		BIT(1)
-#define SN5S330_CC_EN			BIT(4)
-#define SN5S330_VCONN_ILIM_SEL		BIT(5)
+#define SN5S330_VCONN_EN BIT(0)
+#define SN5S330_CC_POLARITY BIT(1)
+#define SN5S330_CC_EN BIT(4)
+#define SN5S330_VCONN_ILIM_SEL BIT(5)
 
 /* FUNC_SET_8 */
-#define SN5S330_VCONN_DEGLITCH_MASK	(3 << 6)
-#define SN5S330_VCONN_DEGLITCH_63_US	(0 << 6)
-#define SN5S330_VCONN_DEGLITCH_125_US	BIT(6)
-#define SN5S330_VCONN_DEGLITCH_640_US	(2 << 6)
-#define SN5S330_VCONN_DEGLITCH_1280_US	(3 << 6)
+#define SN5S330_VCONN_DEGLITCH_MASK (3 << 6)
+#define SN5S330_VCONN_DEGLITCH_63_US (0 << 6)
+#define SN5S330_VCONN_DEGLITCH_125_US BIT(6)
+#define SN5S330_VCONN_DEGLITCH_640_US (2 << 6)
+#define SN5S330_VCONN_DEGLITCH_1280_US (3 << 6)
 
 /* FUNC_SET_9 */
-#define SN5S330_FORCE_OVP_EN_SBU	BIT(1)
-#define SN5S330_PP2_CONFIG		BIT(2)
-#define SN5S330_OVP_EN_CC		BIT(4)
-#define SN5S330_CONFIG_UVP		BIT(5)
-#define SN5S330_FORCE_ON_VBUS_OVP	BIT(6)
-#define SN5S330_FORCE_ON_VBUS_UVP	BIT(7)
+#define SN5S330_FORCE_OVP_EN_SBU BIT(1)
+#define SN5S330_PP2_CONFIG BIT(2)
+#define SN5S330_PWR_OVR_VBUS BIT(3)
+#define SN5S330_OVP_EN_CC BIT(4)
+#define SN5S330_CONFIG_UVP BIT(5)
+#define SN5S330_FORCE_ON_VBUS_OVP BIT(6)
+#define SN5S330_FORCE_ON_VBUS_UVP BIT(7)
 
 /* INT_STATUS_REG3 */
-#define SN5S330_VBUS_GOOD		BIT(0)
+#define SN5S330_VBUS_GOOD BIT(0)
 
 /* INT_STATUS_REG4 */
-#define SN5S330_DIG_RES			BIT(0)
-#define SN5S330_DB_BOOT			BIT(1)
-#define SN5S330_VSAFE0V_STAT		BIT(2)
-#define SN5S330_VSAFE0V_MASK		BIT(3)
+#define SN5S330_DIG_RES BIT(0)
+#define SN5S330_DB_BOOT BIT(1)
+#define SN5S330_VSAFE0V_STAT BIT(2)
+#define SN5S330_VSAFE0V_MASK BIT(3)
+
+/* FUNC_SET_10 */
+#define SN5S330_PP1_RCP_OFFSET BIT(4)
 
 /*
  * INT_MASK_RISE/FALL_EDGE_1
@@ -161,17 +164,4 @@ enum sn5s330_pp_idx {
  */
 #define SN5S330_VBUS_GOOD_MASK BIT(0)
 
-extern const struct ppc_drv sn5s330_drv;
-
-/**
- * Interrupt Handler for the SN5S330.
- *
- * By default, the only interrupt sources that are unmasked are overcurrent
- * conditions for PP1, and VBUS_GOOD if PPC is being used to detect VBUS
- * (CONFIG_USB_PD_VBUS_DETECT_PPC).
- *
- * @param port: The Type-C port which triggered the interrupt.
- */
-void sn5s330_interrupt(int port);
-
 #endif /* defined(__CROS_EC_SN5S330_H) */
diff --git a/driver/ppc/syv682x.c b/driver/ppc/syv682x.c
index 81a2034577..68fc45cacf 100644
--- a/driver/ppc/syv682x.c
+++ b/driver/ppc/syv682x.c
@@ -1,44 +1,61 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Silergy SYV682x USB-C Power Path Controller */
+#include "atomic.h"
 #include "common.h"
 #include "config.h"
 #include "console.h"
-#include "driver/ppc/syv682x.h"
+#include "gpio.h"
 #include "hooks.h"
 #include "i2c.h"
 #include "system.h"
+#include "syv682x.h"
+#include "tcpm/tcpm.h"
 #include "timer.h"
 #include "usb_charge.h"
+#include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 #include "usbc_ppc.h"
-#include "usb_pd.h"
 #include "util.h"
 
-#define SYV682X_FLAGS_SOURCE_ENABLED	BIT(0)
+#define SYV682X_FLAGS_SOURCE_ENABLED BIT(0)
+#define SYV682X_FLAGS_SINK_ENABLED BIT(1)
 /* 0 -> CC1, 1 -> CC2 */
-#define SYV682X_FLAGS_CC_POLARITY	BIT(1)
-#define SYV682X_FLAGS_VBUS_PRESENT	BIT(2)
-#define SYV682X_FLAGS_OCP		BIT(3)
-#define SYV682X_FLAGS_OVP		BIT(4)
-#define SYV682X_FLAGS_5V_OC		BIT(5)
-#define SYV682X_FLAGS_RVS		BIT(6)
-#define SYV682X_FLAGS_VCONN_OCP		BIT(7)
-
-static uint32_t irq_pending; /* Bitmask of ports signaling an interrupt. */
-static uint8_t flags[CONFIG_USB_PD_PORT_MAX_COUNT];
-static timestamp_t oc_timer[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-#define SYV682X_VBUS_DET_THRESH_MV		4000
+#define SYV682X_FLAGS_CC_POLARITY BIT(2)
+#define SYV682X_FLAGS_VBUS_PRESENT BIT(3)
+#define SYV682X_FLAGS_TSD BIT(4)
+#define SYV682X_FLAGS_OVP BIT(5)
+#define SYV682X_FLAGS_5V_OC BIT(6)
+#define SYV682X_FLAGS_FRS BIT(7)
+#define SYV682X_FLAGS_VCONN_OCP BIT(8)
+
+static atomic_t irq_pending; /* Bitmask of ports signaling an interrupt. */
+static atomic_t flags[CONFIG_USB_PD_PORT_MAX_COUNT];
+/* Running count of sink ocp events */
+static atomic_t sink_ocp_count[CONFIG_USB_PD_PORT_MAX_COUNT];
+static timestamp_t vbus_oc_timer[CONFIG_USB_PD_PORT_MAX_COUNT];
+static timestamp_t vconn_oc_timer[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+#define SYV682X_VBUS_DET_THRESH_MV 4000
 /* Longest time that can be programmed in DSG_TIME field */
-#define SYV682X_MAX_VBUS_DISCHARGE_TIME_MS	400
-/* Delay between checks when polling the interrupt registers */
-#define INTERRUPT_DELAY_MS 10
+#define SYV682X_MAX_VBUS_DISCHARGE_TIME_MS 400
+/*
+ * Delay between checks when polling the interrupt registers. Must be longer
+ * than the HW deglitch on OC (10ms)
+ */
+#define INTERRUPT_DELAY_MS 15
 /* Deglitch in ms of sourcing overcurrent detection */
 #define SOURCE_OC_DEGLITCH_MS 100
+#define VCONN_OC_DEGLITCH_MS 100
+/* Max. number of OC events allowed before disabling port */
+#define OCP_COUNT_LIMIT 3
+
+#if INTERRUPT_DELAY_MS <= SYV682X_HW_OC_DEGLITCH_MS
+#error "INTERRUPT_DELAY_MS should be greater than SYV682X_HW_OC_DEGLITCH_MS"
+#endif
 
 #if SOURCE_OC_DEGLITCH_MS < INTERRUPT_DELAY_MS
 #error "SOURCE_OC_DEGLITCH_MS should be at least INTERRUPT_DELAY_MS"
@@ -51,28 +68,46 @@ static timestamp_t oc_timer[CONFIG_USB_PD_PORT_MAX_COUNT];
 "instead of the TCPC"
 #endif
 
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+	static int
+	syv682x_vbus_sink_enable(int port, int enable);
+
+static int syv682x_init(int port);
+
+static void syv682x_interrupt_delayed(int port, int delay);
 
 static int read_reg(uint8_t port, int reg, int *regval)
 {
 	return i2c_read8(ppc_chips[port].i2c_port,
-			 ppc_chips[port].i2c_addr_flags,
-			 reg,
-			 regval);
+			 ppc_chips[port].i2c_addr_flags, reg, regval);
 }
 
+#ifdef CONFIG_USBC_PPC_SYV682C
+__overridable int syv682x_board_is_syv682c(int port)
+{
+	return true;
+}
+#endif
+
 /*
- * During channel transition or discharge, the SYV682A silently ignores I2C
+ * During channel transition or discharge, the SYV682X silently ignores I2C
  * writes. Poll the BUSY bit until the SYV682A is ready.
  */
-static int syv682x_wait_for_ready(int port)
+static int syv682x_wait_for_ready(int port, int reg)
 {
 	int regval;
 	int rv;
 	timestamp_t deadline;
 
-	deadline.val = get_time().val
-			+ (SYV682X_MAX_VBUS_DISCHARGE_TIME_MS * MSEC);
+#ifdef CONFIG_USBC_PPC_SYV682C
+	/* On SYV682C, busy bit is not applied to CONTROL_4 */
+	if (syv682x_board_is_syv682c(port) && reg == SYV682X_CONTROL_4_REG)
+		return EC_SUCCESS;
+#endif
+
+	deadline.val =
+		get_time().val + (SYV682X_MAX_VBUS_DISCHARGE_TIME_MS * MSEC);
 
 	do {
 		rv = read_reg(port, SYV682X_CONTROL_3_REG, &regval);
@@ -97,14 +132,12 @@ static int write_reg(uint8_t port, int reg, int regval)
 {
 	int rv;
 
-	rv = syv682x_wait_for_ready(port);
+	rv = syv682x_wait_for_ready(port, reg);
 	if (rv)
 		return rv;
 
 	return i2c_write8(ppc_chips[port].i2c_port,
-			  ppc_chips[port].i2c_addr_flags,
-			  reg,
-			  regval);
+			  ppc_chips[port].i2c_addr_flags, reg, regval);
 }
 
 static int syv682x_is_sourcing_vbus(int port)
@@ -114,10 +147,40 @@ static int syv682x_is_sourcing_vbus(int port)
 
 static int syv682x_discharge_vbus(int port, int enable)
 {
+#ifndef CONFIG_USBC_PPC_SYV682X_SMART_DISCHARGE
+	int regval;
+	int rv;
+	/* cached force discharge flag to reduce the call to the discharge
+	 * function.
+	 */
+	static uint8_t sd_flags[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+		[0 ... CONFIG_USB_PD_PORT_MAX_COUNT - 1] = 0xFF
+	};
+
+	if ((!!enable) == sd_flags[port])
+		return EC_SUCCESS;
+
+	rv = read_reg(port, SYV682X_CONTROL_2_REG, &regval);
+	if (rv)
+		return rv;
+
+	if (enable)
+		regval |= SYV682X_CONTROL_2_FDSG;
+	else
+		regval &= ~SYV682X_CONTROL_2_FDSG;
+
+	rv = write_reg(port, SYV682X_CONTROL_2_REG, regval);
+
+	if (!rv)
+		sd_flags[port] = !!enable;
+
+	return rv;
+#else
 	/*
 	 * Smart discharge mode is enabled, nothing to do
 	 */
 	return EC_SUCCESS;
+#endif
 }
 
 static int syv682x_vbus_source_enable(int port, int enable)
@@ -134,8 +197,8 @@ static int syv682x_vbus_source_enable(int port, int enable)
 
 	if (enable) {
 		/* Select 5V path and turn on channel */
-		regval &= ~(SYV682X_CONTROL_1_CH_SEL |
-			    SYV682X_CONTROL_1_PWR_ENB);
+		regval &=
+			~(SYV682X_CONTROL_1_CH_SEL | SYV682X_CONTROL_1_PWR_ENB);
 		/* Disable HV Sink path */
 		regval |= SYV682X_CONTROL_1_HV_DR;
 	} else if (flags[port] & SYV682X_FLAGS_SOURCE_ENABLED) {
@@ -148,18 +211,25 @@ static int syv682x_vbus_source_enable(int port, int enable)
 		 *
 		 * No need to change the voltage path or channel direction. But,
 		 * turn both paths off.
+		 *
+		 * De-assert the FRS GPIO, which will be asserted if we got to
+		 * be a source via an FRS.
 		 */
 		regval |= SYV682X_CONTROL_1_PWR_ENB;
+		if (IS_ENABLED(CONFIG_USB_PD_FRS_PPC))
+			gpio_or_ioex_set_level(ppc_chips[port].frs_en, 0);
 	}
 
 	rv = write_reg(port, SYV682X_CONTROL_1_REG, regval);
 	if (rv)
 		return rv;
 
-	if (enable)
-		flags[port] |= SYV682X_FLAGS_SOURCE_ENABLED;
-	else
-		flags[port] &= ~SYV682X_FLAGS_SOURCE_ENABLED;
+	if (enable) {
+		atomic_or(&flags[port], SYV682X_FLAGS_SOURCE_ENABLED);
+		atomic_clear_bits(&flags[port], SYV682X_FLAGS_SINK_ENABLED);
+	} else {
+		atomic_clear_bits(&flags[port], SYV682X_FLAGS_SOURCE_ENABLED);
+	}
 
 #if defined(CONFIG_USB_CHARGER) && defined(CONFIG_USB_PD_VBUS_DETECT_PPC)
 	/*
@@ -178,11 +248,11 @@ static bool syv682x_interrupt_filter(int port, int regval, int regmask,
 {
 	if (regval & regmask) {
 		if (!(flags[port] & flagmask)) {
-			flags[port] |= flagmask;
+			atomic_or(&flags[port], flagmask);
 			return true;
 		}
 	} else {
-		flags[port] &= ~flagmask;
+		atomic_clear_bits(&flags[port], flagmask);
 	}
 	return false;
 }
@@ -196,30 +266,26 @@ static bool syv682x_interrupt_filter(int port, int regval, int regmask,
  */
 static void syv682x_handle_status_interrupt(int port, int regval)
 {
-	/* An FRS will automatically enable the source path */
-	if (IS_ENABLED(CONFIG_USB_PD_FRS_PPC) &&
-	    (regval & SYV682X_STATUS_FRS)) {
-		flags[port] |= SYV682X_FLAGS_SOURCE_ENABLED;
-		/*
-		 * Workaround for bug in SYV692.
-		 *
-		 * The SYV682X has an FRS trigger but it is broken in some
-		 * versions of the part. The old parts require VBUS to fall to
-		 * generate the interrupt, it needs to be generated on CC alone.
-		 *
-		 * The workaround is to use to the TCPC trigger if
-		 * available. When the part is fixed, the TCPC trigger is no
-		 * longer needed. If the TCPC doesn't have a trigger, FRS timing
-		 * may be violated for slow-vbus discharge cases.
-		 */
-		if (!IS_ENABLED(CONFIG_USB_PD_FRS_TCPC))
-			pd_got_frs_signal(port);
+	/*
+	 * An FRS will automatically disable sinking immediately, and enable the
+	 * source path if VBUS is <5V. The FRS GPIO must remain asserted until
+	 * VBUS falls below 5V. SYV682X_FLAGS_FRS signals that the SRC state was
+	 * entered via an FRS.
+	 *
+	 * Note the FRS Alert will remain asserted until VBUS has fallen below
+	 * 5V or the frs_en gpio is de-asserted. So use the rising edge trigger.
+	 */
+	if (IS_ENABLED(CONFIG_USB_PD_FRS_PPC)) {
+		if (syv682x_interrupt_filter(port, regval, SYV682X_STATUS_FRS,
+					     SYV682X_FLAGS_FRS)) {
+			atomic_or(&flags[port], SYV682X_FLAGS_SOURCE_ENABLED);
+			atomic_clear_bits(&flags[port],
+					  SYV682X_FLAGS_SINK_ENABLED);
+			if (!tcpm_tcpc_has_frs_control(port))
+				pd_got_frs_signal(port);
+		}
 	}
 
-	/* These conditions automatically turn off VBUS sourcing */
-	if (regval & (SYV682X_STATUS_OVP | SYV682X_STATUS_TSD))
-		flags[port] &= ~SYV682X_FLAGS_SOURCE_ENABLED;
-
 	/*
 	 * 5V OC is actually notifying that it is current limiting
 	 * to 3.3A. If this happens for a long time, we will trip TSD
@@ -231,44 +297,101 @@ static void syv682x_handle_status_interrupt(int port, int regval)
 	 */
 	if (syv682x_interrupt_filter(port, regval, SYV682X_STATUS_OC_5V,
 				     SYV682X_FLAGS_5V_OC)) {
-		oc_timer[port].val =
+		vbus_oc_timer[port].val =
 			get_time().val + SOURCE_OC_DEGLITCH_MS * MSEC;
 	} else if ((regval & SYV682X_STATUS_OC_5V) &&
-		   (get_time().val > oc_timer[port].val)) {
-		oc_timer[port].val = UINT64_MAX;
-		flags[port] &= ~SYV682X_FLAGS_5V_OC;
+		   (get_time().val > vbus_oc_timer[port].val)) {
+		vbus_oc_timer[port].val = UINT64_MAX;
+		atomic_clear_bits(&flags[port], SYV682X_FLAGS_5V_OC);
 		syv682x_vbus_source_enable(port, 0);
 		pd_handle_overcurrent(port);
 	}
 
-	if (syv682x_interrupt_filter(port, regval,
-				     SYV682X_STATUS_OC_HV | SYV682X_STATUS_TSD,
-				     SYV682X_FLAGS_OCP))
-		pd_handle_overcurrent(port);
-
-	/* No PD handler for VBUS OVP/RVS events */
-
+	/*
+	 * No PD handling for VBUS OVP or TSD events.
+	 * For TSD, this means we are in danger of burning the device so turn
+	 *   everything off and leave it off. The power paths will be
+	 *   automatically disabled.
+	 * In the case of OVP, the channels will be
+	 *   disabled but don't unset the sink flag, since a sink OCP can
+	 *   inadvertently cause an OVP, and we'd want to re-enable the sink
+	 *   path in that situation.
+	 */
+	if (syv682x_interrupt_filter(port, regval, SYV682X_STATUS_TSD,
+				     SYV682X_FLAGS_TSD)) {
+		ppc_prints("TSD!", port);
+		atomic_clear_bits(&flags[port],
+				  SYV682X_FLAGS_SOURCE_ENABLED |
+					  SYV682X_FLAGS_SINK_ENABLED);
+	}
 	if (syv682x_interrupt_filter(port, regval, SYV682X_STATUS_OVP,
 				     SYV682X_FLAGS_OVP)) {
 		ppc_prints("VBUS OVP!", port);
+		atomic_clear_bits(&flags[port], SYV682X_FLAGS_SOURCE_ENABLED);
 	}
-	if (syv682x_interrupt_filter(port, regval, SYV682X_STATUS_RVS,
-				     SYV682X_FLAGS_RVS)) {
-		ppc_prints("VBUS Reverse Voltage!", port);
+
+	/*
+	 * HV OC is a hard limit that will disable the sink path (automatically
+	 * removing this alert condition), so try re-enabling if we hit an OCP.
+	 * If we get multiple OCPs, don't re-enable. The OCP counter is reset on
+	 * the sink path being explicitly disabled or on a PPC init.
+	 */
+	if (regval & SYV682X_STATUS_OC_HV) {
+		ppc_prints("Sink OCP!", port);
+		atomic_add(&sink_ocp_count[port], 1);
+		if ((sink_ocp_count[port] < OCP_COUNT_LIMIT) &&
+		    (flags[port] & SYV682X_FLAGS_SINK_ENABLED)) {
+			syv682x_vbus_sink_enable(port, 1);
+		} else {
+			ppc_prints("Disable sink", port);
+			atomic_clear_bits(&flags[port],
+					  SYV682X_FLAGS_SINK_ENABLED);
+		}
 	}
 }
 
-static void syv682x_handle_control_4_interrupt(int port, int regval)
+static int syv682x_handle_control_4_interrupt(int port, int regval)
 {
+	/*
+	 * VCONN OC is actually notifying that it is current limiting
+	 * to 600mA. If this happens for a long time, we will trip TSD
+	 * which will disable the channel. We should disable the sourcing path
+	 * before that happens for safety reasons.
+	 *
+	 * On first check, set the flag and set the timer. This also clears the
+	 * flag if the OC is gone.
+	 */
 	if (syv682x_interrupt_filter(port, regval, SYV682X_CONTROL_4_VCONN_OCP,
 				     SYV682X_FLAGS_VCONN_OCP)) {
+		vconn_oc_timer[port].val =
+			get_time().val + VCONN_OC_DEGLITCH_MS * MSEC;
+	} else if ((regval & SYV682X_CONTROL_4_VCONN_OCP) &&
+		   (get_time().val > vconn_oc_timer[port].val)) {
+		vconn_oc_timer[port].val = UINT64_MAX;
+		atomic_clear_bits(&flags[port], SYV682X_FLAGS_VCONN_OCP);
+
+		/* Disable VCONN */
+		regval &=
+			~(SYV682X_CONTROL_4_VCONN2 | SYV682X_CONTROL_4_VCONN1);
+		write_reg(port, SYV682X_CONTROL_4_REG, regval);
+
 		ppc_prints("VCONN OC!", port);
 	}
 
-	/* This should never happen unless something really bad happened */
+	/*
+	 * On VBAT OVP, CC/VCONN are cut. Re-enable before sending the hard
+	 * reset using a PPC re-init. We could reconfigure CC based on flags,
+	 * but these will be updated anyway due to a hard reset so just re-init
+	 * for simplicity. If this happens return an error since this isn't
+	 * recoverable.
+	 */
 	if (regval & SYV682X_CONTROL_4_VBAT_OVP) {
-		ppc_prints("VBAT OVP!", port);
+		ppc_prints("VBAT or CC OVP!", port);
+		syv682x_init(port);
+		pd_handle_cc_overvoltage(port);
+		return EC_ERROR_UNKNOWN;
 	}
+	return EC_SUCCESS;
 }
 
 static int syv682x_vbus_sink_enable(int port, int enable)
@@ -276,11 +399,20 @@ static int syv682x_vbus_sink_enable(int port, int enable)
 	int regval;
 	int rv;
 
-	if (!enable && syv682x_is_sourcing_vbus(port)) {
+	if (!enable) {
+		atomic_clear(&sink_ocp_count[port]);
+		atomic_clear_bits(&flags[port], SYV682X_FLAGS_SINK_ENABLED);
 		/*
 		 * We're currently a source, so nothing more to do
 		 */
-		return EC_SUCCESS;
+		if (syv682x_is_sourcing_vbus(port))
+			return EC_SUCCESS;
+	} else if (sink_ocp_count[port] > OCP_COUNT_LIMIT) {
+		/*
+		 * Don't re-enable the channel until an explicit sink disable
+		 * resets the ocp counter.
+		 */
+		return EC_ERROR_UNKNOWN;
 	}
 
 	/*
@@ -295,11 +427,12 @@ static int syv682x_vbus_sink_enable(int port, int enable)
 		/* Select high voltage path */
 		regval |= SYV682X_CONTROL_1_CH_SEL;
 		/* Select Sink mode and turn on the channel */
-		regval &= ~(SYV682X_CONTROL_1_HV_DR |
-			    SYV682X_CONTROL_1_PWR_ENB);
+		regval &=
+			~(SYV682X_CONTROL_1_HV_DR | SYV682X_CONTROL_1_PWR_ENB);
 		/* Set sink current limit to the configured value */
 		regval |= CONFIG_SYV682X_HV_ILIM << SYV682X_HV_ILIM_BIT_SHIFT;
-		flags[port] &= ~SYV682X_FLAGS_SOURCE_ENABLED;
+		atomic_clear_bits(&flags[port], SYV682X_FLAGS_SOURCE_ENABLED);
+		atomic_or(&flags[port], SYV682X_FLAGS_SINK_ENABLED);
 	} else {
 		/*
 		 * No need to change the voltage path or channel direction. But,
@@ -338,9 +471,9 @@ static int syv682x_is_vbus_present(int port)
 		usb_charger_vbus_change(port, vbus);
 
 	if (vbus)
-		flags[port] |= SYV682X_FLAGS_VBUS_PRESENT;
+		atomic_or(&flags[port], SYV682X_FLAGS_VBUS_PRESENT);
 	else
-		flags[port] &= ~SYV682X_FLAGS_VBUS_PRESENT;
+		atomic_clear_bits(&flags[port], SYV682X_FLAGS_VBUS_PRESENT);
 #endif
 
 	return vbus;
@@ -392,9 +525,9 @@ static int syv682x_set_polarity(int port, int polarity)
 	 * polarity = CC1.
 	 */
 	if (polarity)
-		flags[port] |= SYV682X_FLAGS_CC_POLARITY;
+		atomic_or(&flags[port], SYV682X_FLAGS_CC_POLARITY);
 	else
-		flags[port] &= ~SYV682X_FLAGS_CC_POLARITY;
+		atomic_clear_bits(&flags[port], SYV682X_FLAGS_CC_POLARITY);
 
 	return EC_SUCCESS;
 }
@@ -414,7 +547,9 @@ static int syv682x_set_vconn(int port, int enable)
 	 * register value to see if there are interrupts to avoid race
 	 * conditions with the interrupt handler
 	 */
-	syv682x_handle_control_4_interrupt(port, regval);
+	rv = syv682x_handle_control_4_interrupt(port, regval);
+	if (rv)
+		return rv;
 
 	regval &= ~(SYV682X_CONTROL_4_VCONN2 | SYV682X_CONTROL_4_VCONN1);
 	if (enable) {
@@ -443,8 +578,8 @@ static int syv682x_dump(int port)
 			ccprintf("ppc_syv682[p%d]: Failed to read reg 0x%02x\n",
 				 port, reg_addr);
 		else
-			ccprintf("ppc_syv682[p%d]: reg 0x%02x = 0x%02x\n",
-				 port, reg_addr, data);
+			ccprintf("ppc_syv682[p%d]: reg 0x%02x = 0x%02x\n", port,
+				 reg_addr, data);
 	}
 
 	cflush();
@@ -453,8 +588,6 @@ static int syv682x_dump(int port)
 }
 #endif /* defined(CONFIG_CMD_PPC_DUMP) */
 
-static void syv682x_interrupt_delayed(int port, int delay);
-
 static void syv682x_handle_interrupt(int port)
 {
 	int control4;
@@ -469,27 +602,22 @@ static void syv682x_handle_interrupt(int port)
 
 	/*
 	 * Since ALERT_L is level-triggered, check the alert status and repeat
-	 * until all interrupts are cleared. This will not spam indefinitely on
-	 * OCP, but may on OVP, RVS, or TSD
+	 * until all interrupts are cleared. The SYV682B and later have a 10ms
+	 * deglitch on OC, so make sure not to check the status register again
+	 * for at least 10ms to give it time to re-trigger. This will not spam
+	 * indefinitely on OCP, but may on OVP, RVS, or TSD.
 	 */
 
-	if (IS_ENABLED(CONFIG_USBC_PPC_DEDICATED_INT) &&
-	    ppc_get_alert_status(port)) {
+	if (status & SYV682X_STATUS_INT_MASK ||
+	    control4 & SYV682X_CONTROL_4_INT_MASK) {
 		syv682x_interrupt_delayed(port, INTERRUPT_DELAY_MS);
-	} else {
-		read_reg(port, SYV682X_CONTROL_4_REG, &control4);
-		read_reg(port, SYV682X_STATUS_REG, &status);
-		if (status & SYV682X_STATUS_INT_MASK ||
-		    control4 & SYV682X_CONTROL_4_INT_MASK) {
-			syv682x_interrupt_delayed(port, INTERRUPT_DELAY_MS);
-		}
 	}
 }
 
 static void syv682x_irq_deferred(void)
 {
 	int i;
-	uint32_t pending = deprecated_atomic_read_clear(&irq_pending);
+	uint32_t pending = atomic_clear(&irq_pending);
 
 	for (i = 0; i < board_get_usb_pd_port_count(); i++)
 		if (BIT(i) & pending)
@@ -499,7 +627,7 @@ DECLARE_DEFERRED(syv682x_irq_deferred);
 
 static void syv682x_interrupt_delayed(int port, int delay)
 {
-	deprecated_atomic_or(&irq_pending, BIT(port));
+	atomic_or(&irq_pending, BIT(port));
 	hook_call_deferred(&syv682x_irq_deferred_data, delay * MSEC);
 }
 
@@ -516,64 +644,64 @@ void syv682x_interrupt(int port)
 #ifdef CONFIG_USB_PD_FRS_PPC
 static int syv682x_set_frs_enable(int port, int enable)
 {
-	int status;
 	int regval;
 
 	read_reg(port, SYV682X_CONTROL_4_REG, &regval);
 	syv682x_handle_control_4_interrupt(port, regval);
 
 	if (enable) {
-		read_reg(port, SYV682X_STATUS_REG, &status);
-		syv682x_handle_status_interrupt(port, status);
 		/*
-		 * Workaround for a bug in SYV682A
-		 *
-		 * The bug is that VBUS needs to be below VBAT when CC is pulled
-		 * low to trigger FRS. This is fine when charging at 5V usually,
-		 * but often not when charging at higher voltages. At higher
-		 * voltages, the CC trigger needs to be disabled for the broken
-		 * parts.
+		 * The CC line is the FRS trigger, and VCONN should
+		 * be ignored. The SYV682 uses the CCx_BPS fields to
+		 * determine if CC1 or CC2 is CC and should be used for
+		 * FRS. This CCx is also connected through to the TCPC.
+		 * The other CCx signal (VCONN) is isolated from the
+		 * TCPC with this write (VCONN must be provided by PPC).
 		 *
-		 * TODO (b/161372139): When this is fixed in SYV682B, always use
-		 * the CC trigger.
+		 * It is not a valid state to have both or neither
+		 * CC_BPS bits set and the CC_FRS enabled, exactly 1
+		 * should be set.
 		 */
-		if (status & SYV682X_STATUS_VSAFE_5V) {
-			/* Inverted register, clear to enable CC detection */
-			regval &= ~SYV682X_CONTROL_4_CC_FRS;
-			/*
-			 * The CC line is the FRS trigger, and VCONN should
-			 * be ignored. The SYV682 uses the CCx_BPS fields to
-			 * determine if CC1 or CC2 is CC and should be used for
-			 * FRS. This CCx is also connected through to the TCPC.
-			 * The other CCx signal (VCONN) is isolated from the
-			 * TCPC with this write (VCONN must be provided by PPC)
-			 *
-			 * It is not a valid state to have both or neither
-			 * CC_BPS bits set and the CC_FRS enabled, exactly 1
-			 * should be set.
-			 */
-			regval &= ~(SYV682X_CONTROL_4_CC1_BPS |
-				    SYV682X_CONTROL_4_CC2_BPS);
-			regval |= flags[port] & SYV682X_FLAGS_CC_POLARITY ?
-					  SYV682X_CONTROL_4_CC2_BPS :
-					  SYV682X_CONTROL_4_CC1_BPS;
-
-		} else {
-			regval |= SYV682X_CONTROL_4_CC_FRS;
-		}
+		regval &= ~(SYV682X_CONTROL_4_CC1_BPS |
+			    SYV682X_CONTROL_4_CC2_BPS);
+		regval |= flags[port] & SYV682X_FLAGS_CC_POLARITY ?
+				  SYV682X_CONTROL_4_CC2_BPS :
+				  SYV682X_CONTROL_4_CC1_BPS;
+		/* set GPIO after configuring */
+		write_reg(port, SYV682X_CONTROL_4_REG, regval);
+		gpio_or_ioex_set_level(ppc_chips[port].frs_en, 1);
 	} else {
 		/*
-		 * Disabling FRS is part of the disconnect sequence, reconnect
-		 * CC lines to TCPC.
+		 * Reconnect CC lines to TCPC. Since the FRS GPIO needs to be
+		 * asserted until VBUS falls below 5V during an FRS, if
+		 * SYV682X_FLAGS_FRS is set then don't deassert it, instead
+		 * disable when sourcing is disabled.
 		 */
 		regval |= SYV682X_CONTROL_4_CC1_BPS | SYV682X_CONTROL_4_CC2_BPS;
+		write_reg(port, SYV682X_CONTROL_4_REG, regval);
+		if (!(flags[port] & SYV682X_FLAGS_FRS))
+			gpio_or_ioex_set_level(ppc_chips[port].frs_en, 0);
 	}
-	write_reg(port, SYV682X_CONTROL_4_REG, regval);
-	gpio_set_level(ppc_chips[port].frs_en, enable);
 	return EC_SUCCESS;
 }
 #endif /*CONFIG_USB_PD_FRS_PPC*/
 
+#ifndef CONFIG_USBC_PPC_SYV682X_SMART_DISCHARGE
+static int syv682x_dev_is_connected(int port, enum ppc_device_role dev)
+{
+	/*
+	 * (b:160548079) We disable the smart discharge(SDSG), so we should
+	 * turn off the discharge FET if a source is connected.
+	 */
+	if (dev == PPC_DEV_SRC)
+		return syv682x_discharge_vbus(port, 0);
+	else if (dev == PPC_DEV_DISCONNECTED)
+		return syv682x_discharge_vbus(port, 1);
+
+	return EC_SUCCESS;
+}
+#endif
+
 static bool syv682x_is_sink(uint8_t control_1)
 {
 	/*
@@ -588,14 +716,19 @@ static bool syv682x_is_sink(uint8_t control_1)
 	 *
 	 * The SYV682 is only a sink when !HV_DR && CH_SEL
 	 */
-	if (!(control_1 & SYV682X_CONTROL_1_PWR_ENB)
-		&& !(control_1 & SYV682X_CONTROL_1_HV_DR)
-		&& (control_1 & SYV682X_CONTROL_1_CH_SEL))
+	if (!(control_1 & SYV682X_CONTROL_1_PWR_ENB) &&
+	    !(control_1 & SYV682X_CONTROL_1_HV_DR) &&
+	    (control_1 & SYV682X_CONTROL_1_CH_SEL))
 		return true;
 
 	return false;
 }
 
+static bool syv682x_is_vconn_controlled_by_tcpc(int port)
+{
+	return tcpc_config[port].flags & TCPC_FLAGS_CONTROL_VCONN;
+}
+
 static int syv682x_init(int port)
 {
 	int rv;
@@ -603,6 +736,15 @@ static int syv682x_init(int port)
 	int status, control_1;
 	enum tcpc_rp_value initial_current_limit;
 
+	/*
+	 * Vconn must be sourced by syv682x. The maximum voltage of HOST_CCx
+	 * pin is 3.6V. Vconn source by TCPC may exceed 3.6V and damage syv682x.
+	 */
+	if (syv682x_is_vconn_controlled_by_tcpc(port)) {
+		CPRINTS("ERROR! Vconn MUST NOT be controlled by TCPC");
+		return EC_ERROR_INVALID_CONFIG;
+	}
+
 	rv = read_reg(port, SYV682X_STATUS_REG, &status);
 	if (rv)
 		return rv;
@@ -610,9 +752,15 @@ static int syv682x_init(int port)
 	rv = read_reg(port, SYV682X_CONTROL_1_REG, &control_1);
 	if (rv)
 		return rv;
+	atomic_clear(&sink_ocp_count[port]);
 
-	if (!syv682x_is_sink(control_1)
-		|| (status & SYV682X_STATUS_VSAFE_0V)) {
+	/*
+	 * Disable FRS prior to configuring the power paths
+	 */
+	if (IS_ENABLED(CONFIG_USB_PD_FRS_PPC))
+		gpio_or_ioex_set_level(ppc_chips[port].frs_en, 0);
+
+	if (!syv682x_is_sink(control_1) || (status & SYV682X_STATUS_VSAFE_0V)) {
 		/*
 		 * Disable both power paths,
 		 * set HV_ILIM to 3.3A,
@@ -621,9 +769,9 @@ static int syv682x_init(int port)
 		 * select HV channel.
 		 */
 		regval = SYV682X_CONTROL_1_PWR_ENB |
-			(CONFIG_SYV682X_HV_ILIM << SYV682X_HV_ILIM_BIT_SHIFT) |
-			/* !SYV682X_CONTROL_1_HV_DR */
-			SYV682X_CONTROL_1_CH_SEL;
+			 (CONFIG_SYV682X_HV_ILIM << SYV682X_HV_ILIM_BIT_SHIFT) |
+			 /* !SYV682X_CONTROL_1_HV_DR */
+			 SYV682X_CONTROL_1_CH_SEL;
 		rv = write_reg(port, SYV682X_CONTROL_1_REG, regval);
 		if (rv)
 			return rv;
@@ -644,15 +792,20 @@ static int syv682x_init(int port)
 		return rv;
 
 	/*
-	 * Set Control Reg 2 to defaults, plus enable smart discharge mode.
-	 * The SYV682 automatically discharges under the following conditions:
-	 * UVLO (under voltage lockout), channel shutdown, over current, over
-	 * voltage, and thermal shutdown
+	 * Set Control Reg 2 to defaults except 50ms smart discharge time.
+	 * Note: On SYV682A/B, enable smart discharge would block i2c
+	 * transactions for 50ms (discharge time) and this
+	 * prevents us from disabling Vconn when stop sourcing Vbus and has
+	 * tVconnOff (35ms) timeout.
+	 * On SYV682C, we are allowed to access CONTROL4 while the i2c busy.
 	 */
-	regval = (SYV682X_OC_DELAY_10MS << SYV682X_OC_DELAY_SHIFT)
-		| (SYV682X_DSG_TIME_50MS << SYV682X_DSG_TIME_SHIFT)
-		| (SYV682X_DSG_RON_200_OHM << SYV682X_DSG_RON_SHIFT)
-		| SYV682X_CONTROL_2_SDSG;
+	regval = (SYV682X_OC_DELAY_10MS << SYV682X_OC_DELAY_SHIFT) |
+		 (SYV682X_DSG_RON_200_OHM << SYV682X_DSG_RON_SHIFT) |
+		 (SYV682X_DSG_TIME_50MS << SYV682X_DSG_TIME_SHIFT);
+
+	if (IS_ENABLED(CONFIG_USBC_PPC_SYV682X_SMART_DISCHARGE))
+		regval |= SYV682X_CONTROL_2_SDSG;
+
 	rv = write_reg(port, SYV682X_CONTROL_2_REG, regval);
 	if (rv)
 		return rv;
@@ -661,8 +814,10 @@ static int syv682x_init(int port)
 	 * Always set the over voltage setting to the maximum to support
 	 * sinking from a 20V PD charger. The common PPC code doesn't provide
 	 * any hooks for indicating what the currently negotiated voltage is.
+	 *
+	 * Mask Alerts due to Reverse Voltage.
 	 */
-	regval = (SYV682X_OVP_23_7 << SYV682X_OVP_BIT_SHIFT);
+	regval = (SYV682X_OVP_23_7 << SYV682X_OVP_BIT_SHIFT) | SYV682X_RVS_MASK;
 	rv = write_reg(port, SYV682X_CONTROL_3_REG, regval);
 	if (rv)
 		return rv;
@@ -670,10 +825,9 @@ static int syv682x_init(int port)
 	/*
 	 * Remove Rd and connect CC1/CC2 lines to TCPC
 	 * Disable Vconn
-	 * Disable CC detection of Fast Role Swap (FRS)
+	 * Enable CC detection of Fast Role Swap (FRS)
 	 */
-	regval = SYV682X_CONTROL_4_CC1_BPS | SYV682X_CONTROL_4_CC2_BPS |
-		 SYV682X_CONTROL_4_CC_FRS;
+	regval = SYV682X_CONTROL_4_CC1_BPS | SYV682X_CONTROL_4_CC2_BPS;
 	rv = write_reg(port, SYV682X_CONTROL_4_REG, regval);
 	if (rv)
 		return rv;
@@ -697,10 +851,14 @@ const struct ppc_drv syv682x_drv = {
 #endif /* defined(CONFIG_USB_PD_VBUS_DETECT_PPC) */
 	.set_vbus_source_current_limit = &syv682x_set_vbus_source_current_limit,
 	.discharge_vbus = &syv682x_discharge_vbus,
+#ifndef CONFIG_USBC_PPC_SYV682X_SMART_DISCHARGE
+	.dev_is_connected = &syv682x_dev_is_connected,
+#endif /* defined(CONFIG_USBC_PPC_SYV682X_SMART_DISCHARGE) */
 #ifdef CONFIG_USBC_PPC_POLARITY
 	.set_polarity = &syv682x_set_polarity,
 #endif
 #ifdef CONFIG_USBC_PPC_VCONN
 	.set_vconn = &syv682x_set_vconn,
 #endif
+	.interrupt = &syv682x_interrupt,
 };
diff --git a/driver/ppc/syv682x.h b/driver/ppc/syv682x.h
index 3f6d41b512..f4fa616725 100644
--- a/driver/ppc/syv682x.h
+++ b/driver/ppc/syv682x.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,98 +8,105 @@
 #ifndef __CROS_EC_SYV682X_H
 #define __CROS_EC_SYV682X_H
 
-/* I2C addresses */
-#define SYV682X_ADDR0_FLAGS		0x40
-#define SYV682X_ADDR1_FLAGS		0x41
-#define SYV682X_ADDR2_FLAGS		0x42
-#define SYV682x_ADDR3_FLAGS		0x43
+#include "common.h"
+#include "driver/ppc/syv682x_public.h"
+
+/* Source OC deglitch implemented in HW for SYV682B */
+#define SYV682X_HW_OC_DEGLITCH_MS 10
 
 /* SYV682x register addresses */
-#define SYV682X_STATUS_REG		0x00
-#define SYV682X_CONTROL_1_REG		0x01
-#define SYV682X_CONTROL_2_REG		0x02
-#define SYV682X_CONTROL_3_REG		0x03
-#define SYV682X_CONTROL_4_REG		0x04
+#define SYV682X_STATUS_REG 0x00
+#define SYV682X_CONTROL_1_REG 0x01
+#define SYV682X_CONTROL_2_REG 0x02
+#define SYV682X_CONTROL_3_REG 0x03
+#define SYV682X_CONTROL_4_REG 0x04
 
 /* Status Register */
-#define SYV682X_STATUS_OC_HV		BIT(7)
-#define SYV682X_STATUS_RVS		BIT(6)
-#define SYV682X_STATUS_OC_5V		BIT(5)
-#define SYV682X_STATUS_OVP		BIT(4)
-#define SYV682X_STATUS_FRS		BIT(3)
-#define SYV682X_STATUS_TSD		BIT(2)
-#define SYV682X_STATUS_VSAFE_5V		BIT(1)
-#define SYV682X_STATUS_VSAFE_0V		BIT(0)
-#define SYV682X_STATUS_INT_MASK		0xfc
+#define SYV682X_STATUS_OC_HV BIT(7)
+#define SYV682X_STATUS_RVS BIT(6)
+#define SYV682X_STATUS_OC_5V BIT(5)
+#define SYV682X_STATUS_OVP BIT(4)
+#define SYV682X_STATUS_FRS BIT(3)
+#define SYV682X_STATUS_TSD BIT(2)
+#define SYV682X_STATUS_VSAFE_5V BIT(1)
+#define SYV682X_STATUS_VSAFE_0V BIT(0)
+#define SYV682X_STATUS_INT_MASK 0xfc
 
 /* Control Register 1 */
-#define SYV682X_CONTROL_1_CH_SEL	BIT(1)
-#define SYV682X_CONTROL_1_HV_DR		BIT(2)
-#define SYV682X_CONTROL_1_PWR_ENB	BIT(7)
+#define SYV682X_CONTROL_1_CH_SEL BIT(1)
+#define SYV682X_CONTROL_1_HV_DR BIT(2)
+#define SYV682X_CONTROL_1_PWR_ENB BIT(7)
 
-#define SYV682X_5V_ILIM_MASK		0x18
-#define SYV682X_5V_ILIM_BIT_SHIFT	3
-#define SYV682X_5V_ILIM_1_25		0
-#define SYV682X_5V_ILIM_1_75		1
-#define SYV682X_5V_ILIM_2_25		2
-#define SYV682X_5V_ILIM_3_30		3
+#define SYV682X_5V_ILIM_MASK 0x18
+#define SYV682X_5V_ILIM_BIT_SHIFT 3
+#define SYV682X_5V_ILIM_1_25 0
+#define SYV682X_5V_ILIM_1_75 1
+#define SYV682X_5V_ILIM_2_25 2
+#define SYV682X_5V_ILIM_3_30 3
 
-#define SYV682X_HV_ILIM_MASK		0x60
-#define SYV682X_HV_ILIM_BIT_SHIFT	5
-#define SYV682X_HV_ILIM_1_25		0
-#define SYV682X_HV_ILIM_1_75		1
-#define SYV682X_HV_ILIM_3_30		2
-#define SYV682X_HV_ILIM_5_50		3
+#define SYV682X_HV_ILIM_MASK 0x60
+#define SYV682X_HV_ILIM_BIT_SHIFT 5
+#define SYV682X_HV_ILIM_1_25 0
+#define SYV682X_HV_ILIM_1_75 1
+#define SYV682X_HV_ILIM_3_30 2
+#define SYV682X_HV_ILIM_5_50 3
 
 /* Control Register 2 */
-#define SYV682X_OC_DELAY_MASK		GENMASK(7, 6)
-#define SYV682X_OC_DELAY_SHIFT		6
-#define SYV682X_OC_DELAY_1MS		0
-#define SYV682X_OC_DELAY_10MS		1
-#define SYV682X_OC_DELAY_50MS		2
-#define SYV682X_OC_DELAY_100MS		3
-#define SYV682X_DSG_TIME_MASK		GENMASK(5, 4)
-#define SYV682X_DSG_TIME_SHIFT		4
-#define SYV682X_DSG_TIME_50MS		0
-#define SYV682X_DSG_TIME_100MS		1
-#define SYV682X_DSG_TIME_200MS		2
-#define SYV682X_DSG_TIME_400MS		3
-#define SYV682X_DSG_RON_MASK		GENMASK(3, 2)
-#define SYV682X_DSG_RON_SHIFT		2
-#define SYV682X_DSG_RON_200_OHM		0
-#define SYV682X_DSG_RON_400_OHM		1
-#define SYV682X_DSG_RON_800_OHM		2
-#define SYV682X_DSG_RON_1600_OHM	3
-#define SYV682X_CONTROL_2_SDSG		BIT(1)
-#define SYV682X_CONTROL_2_FDSG		BIT(0)
+#define SYV682X_OC_DELAY_MASK GENMASK(7, 6)
+#define SYV682X_OC_DELAY_SHIFT 6
+#define SYV682X_OC_DELAY_1MS 0
+#define SYV682X_OC_DELAY_10MS 1
+#define SYV682X_OC_DELAY_50MS 2
+#define SYV682X_OC_DELAY_100MS 3
+#define SYV682X_DSG_TIME_MASK GENMASK(5, 4)
+#define SYV682X_DSG_TIME_SHIFT 4
+#define SYV682X_DSG_TIME_50MS 0
+#define SYV682X_DSG_TIME_100MS 1
+#define SYV682X_DSG_TIME_200MS 2
+#define SYV682X_DSG_TIME_400MS 3
+#define SYV682X_DSG_RON_MASK GENMASK(3, 2)
+#define SYV682X_DSG_RON_SHIFT 2
+#define SYV682X_DSG_RON_200_OHM 0
+#define SYV682X_DSG_RON_400_OHM 1
+#define SYV682X_DSG_RON_800_OHM 2
+#define SYV682X_DSG_RON_1600_OHM 3
+#define SYV682X_CONTROL_2_SDSG BIT(1)
+#define SYV682X_CONTROL_2_FDSG BIT(0)
 
 /* Control Register 3 */
-#define SYV682X_BUSY			BIT(7)
-#define SYV682X_RST_REG			BIT(0)
-#define SYV682X_OVP_MASK		0x70
-#define SYV682X_OVP_BIT_SHIFT		4
-#define SYV682X_OVP_06_0		0
-#define SYV682X_OVP_08_0		1
-#define SYV682X_OVP_11_1		2
-#define SYV682X_OVP_12_1		3
-#define SYV682X_OVP_14_2		4
-#define SYV682X_OVP_17_9		5
-#define SYV682X_OVP_21_6		6
-#define SYV682X_OVP_23_7		7
+#define SYV682X_BUSY BIT(7)
+#define SYV682X_RVS_MASK BIT(3)
+#define SYV682X_RST_REG BIT(0)
+#define SYV682X_OVP_MASK 0x70
+#define SYV682X_OVP_BIT_SHIFT 4
+#define SYV682X_OVP_06_0 0
+#define SYV682X_OVP_08_0 1
+#define SYV682X_OVP_11_1 2
+#define SYV682X_OVP_12_1 3
+#define SYV682X_OVP_14_2 4
+#define SYV682X_OVP_17_9 5
+#define SYV682X_OVP_21_6 6
+#define SYV682X_OVP_23_7 7
 
 /* Control Register 4 */
-#define SYV682X_CONTROL_4_CC1_BPS	BIT(7)
-#define SYV682X_CONTROL_4_CC2_BPS	BIT(6)
-#define SYV682X_CONTROL_4_VCONN1	BIT(5)
-#define SYV682X_CONTROL_4_VCONN2	BIT(4)
-#define SYV682X_CONTROL_4_VBAT_OVP	BIT(3)
-#define SYV682X_CONTROL_4_VCONN_OCP	BIT(2)
-#define SYV682X_CONTROL_4_CC_FRS	BIT(1)
-#define SYV682X_CONTROL_4_INT_MASK	0x0c
-
-struct ppc_drv;
-extern const struct ppc_drv syv682x_drv;
+#define SYV682X_CONTROL_4_CC1_BPS BIT(7)
+#define SYV682X_CONTROL_4_CC2_BPS BIT(6)
+#define SYV682X_CONTROL_4_VCONN1 BIT(5)
+#define SYV682X_CONTROL_4_VCONN2 BIT(4)
+#define SYV682X_CONTROL_4_VBAT_OVP BIT(3)
+#define SYV682X_CONTROL_4_VCONN_OCP BIT(2)
+#define SYV682X_CONTROL_4_CC_FRS BIT(1)
+#define SYV682X_CONTROL_4_INT_MASK 0x0c
 
-void syv682x_interrupt(int port);
+/*
+ * syv682x_board_is_syv682c
+ *
+ * b:160548079 This is a function to workaround that some board revisions
+ * might have different SYV682 sub-version.
+ *
+ * @param port the query port
+ * @return 1 if the PPC is SYV682C else 0
+ */
+__override_proto int syv682x_board_is_syv682c(int port);
 
 #endif /* defined(__CROS_EC_SYV682X_H) */
diff --git a/driver/ppc/tcpci_ppc.c b/driver/ppc/tcpci_ppc.c
new file mode 100644
index 0000000000..055c7f3048
--- /dev/null
+++ b/driver/ppc/tcpci_ppc.c
@@ -0,0 +1,91 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* USB-C Power Path Controller via TCPCI conformant TCPC */
+
+#include "atomic.h"
+#include "common.h"
+#include "console.h"
+#include "driver/tcpm/tcpci.h"
+#include "usbc_ppc.h"
+
+#define TCPCI_PPC_FLAGS_SOURCE_ENABLED BIT(0)
+
+static atomic_t flags[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+static int tcpci_ppc_is_sourcing_vbus(int port)
+{
+	return (flags[port] & TCPCI_PPC_FLAGS_SOURCE_ENABLED);
+}
+
+static int tcpci_ppc_vbus_source_enable(int port, int enable)
+{
+	RETURN_ERROR(tcpci_tcpm_set_src_ctrl(port, enable));
+
+	if (enable)
+		atomic_or(&flags[port], TCPCI_PPC_FLAGS_SOURCE_ENABLED);
+	else
+		atomic_clear_bits(&flags[port], TCPCI_PPC_FLAGS_SOURCE_ENABLED);
+
+	/*
+	 * Since the VBUS state could be changing here, need to wake the
+	 * USB_CHG_N task so that BC 1.2 detection will be triggered.
+	 */
+	if (IS_ENABLED(CONFIG_USB_CHARGER) &&
+	    IS_ENABLED(CONFIG_USB_PD_VBUS_DETECT_PPC))
+		usb_charger_vbus_change(port, enable);
+
+	return EC_SUCCESS;
+}
+
+#ifdef CONFIG_USB_PD_VBUS_DETECT_PPC
+static int tcpci_is_vbus_present(int port)
+{
+	int status;
+
+	if (tcpci_tcpm_get_power_status(port, &status))
+		return 0;
+
+	return !!(status & TCPC_REG_POWER_STATUS_VBUS_PRES);
+}
+#endif
+
+static int tcpci_ppc_discharge_vbus(int port, int enable)
+{
+	tcpci_tcpc_discharge_vbus(port, enable);
+
+	return EC_SUCCESS;
+}
+
+#ifdef CONFIG_USBC_PPC_POLARITY
+static int tcpci_ppc_set_polarity(int port, int polarity)
+{
+	return tcpci_tcpm_set_polarity(port, polarity);
+}
+#endif
+
+static int tcpci_ppc_init(int port)
+{
+	atomic_clear(&flags[port]);
+
+	return EC_SUCCESS;
+}
+
+const struct ppc_drv tcpci_ppc_drv = {
+	.init = &tcpci_ppc_init,
+	.is_sourcing_vbus = tcpci_ppc_is_sourcing_vbus,
+	.vbus_sink_enable = tcpci_tcpm_set_snk_ctrl,
+	.vbus_source_enable = tcpci_ppc_vbus_source_enable,
+
+#ifdef CONFIG_USB_PD_VBUS_DETECT_PPC
+	.is_vbus_present = tcpci_is_vbus_present,
+#endif
+
+	.discharge_vbus = tcpci_ppc_discharge_vbus,
+
+#ifdef CONFIG_USBC_PPC_POLARITY
+	.set_polarity = tcpci_ppc_set_polarity,
+#endif
+};
diff --git a/driver/ppc/tcpci_ppc.h b/driver/ppc/tcpci_ppc.h
new file mode 100644
index 0000000000..0afe2d245e
--- /dev/null
+++ b/driver/ppc/tcpci_ppc.h
@@ -0,0 +1,8 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* USB-C Power Path Controller via TCPCI conformant TCPC */
+
+extern const struct ppc_drv tcpci_ppc_drv;
diff --git a/driver/pse_ltc4291.c b/driver/pse_ltc4291.c
new file mode 100644
index 0000000000..80255eb501
--- /dev/null
+++ b/driver/pse_ltc4291.c
@@ -0,0 +1,209 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * The LTC4291 is a power over ethernet (PoE) power sourcing equipment (PSE)
+ * controller.
+ */
+
+#include "common.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "i2c.h"
+#include "pse_ltc4291.h"
+#include "string.h"
+#include "timer.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, "PSE: " format, ##args)
+
+static int pse_write_hpmd(int port, int val)
+{
+	switch (port) {
+	case 0:
+		return I2C_PSE_WRITE(HPMD1, val);
+	case 1:
+		return I2C_PSE_WRITE(HPMD2, val);
+	case 2:
+		return I2C_PSE_WRITE(HPMD3, val);
+	case 3:
+		return I2C_PSE_WRITE(HPMD4, val);
+	default:
+		return EC_ERROR_INVAL;
+	}
+}
+
+static int pse_port_enable(int port)
+{
+	/* Enable detection and classification */
+	return I2C_PSE_WRITE(DETPB, LTC4291_DETPB_EN_PORT(port));
+}
+
+static int pse_port_disable(int port)
+{
+	/* Request power off (this also disables detection/classification) */
+	return I2C_PSE_WRITE(PWRPB, LTC4291_PWRPB_OFF_PORT(port));
+}
+
+static int pse_init_worker(void)
+{
+	timestamp_t deadline;
+	int err, id, devid, statpin, port;
+
+	/* Ignore errors -- may already be resetting */
+	I2C_PSE_WRITE(RSTPB, LTC4291_FLD_RSTPB_RSTALL);
+
+	deadline.val = get_time().val + LTC4291_RESET_DELAY_US;
+	while ((err = I2C_PSE_READ(ID, &id)) != EC_SUCCESS) {
+		if (timestamp_expired(deadline, NULL))
+			return EC_ERROR_TIMEOUT;
+		msleep(1);
+	}
+
+	err = I2C_PSE_READ(DEVID, &devid);
+	if (err != EC_SUCCESS)
+		return err;
+
+	if (id != LTC4291_ID || devid != LTC4291_DEVID)
+		return EC_ERROR_INVAL;
+
+	err = I2C_PSE_READ(STATPIN, &statpin);
+	if (err != EC_SUCCESS)
+		return err;
+
+	/*
+	 * We don't want to supply power until we've had a chance to set the
+	 * limits.
+	 */
+	if (statpin & LTC4291_FLD_STATPIN_AUTO)
+		CPRINTS("WARN: PSE reset in AUTO mode");
+
+	err = I2C_PSE_WRITE(OPMD, LTC4291_OPMD_AUTO);
+	if (err != EC_SUCCESS)
+		return err;
+
+	/* Set maximum power each port is allowed to allocate. */
+	for (port = 0; port < LTC4291_PORT_MAX; port++) {
+		err = pse_write_hpmd(port, pse_port_hpmd[port]);
+		if (err != EC_SUCCESS)
+			return err;
+	}
+
+	err = I2C_PSE_WRITE(DISENA, LTC4291_DISENA_ALL);
+	if (err != EC_SUCCESS)
+		return err;
+
+	err = I2C_PSE_WRITE(DETENA, LTC4291_DETENA_ALL);
+	if (err != EC_SUCCESS)
+		return err;
+
+	return EC_SUCCESS;
+}
+
+static void pse_init(void)
+{
+	int err;
+
+	err = pse_init_worker();
+	if (err != EC_SUCCESS)
+		CPRINTS("PSE init failed: %d", err);
+	else
+		CPRINTS("PSE init done");
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, pse_init, HOOK_PRIO_DEFAULT);
+
+/* Also reset the PSE on a reboot to toggle the power. */
+DECLARE_HOOK(HOOK_CHIPSET_RESET, pse_init, HOOK_PRIO_DEFAULT);
+
+static int command_pse(int argc, const char **argv)
+{
+	int port;
+
+	/*
+	 *  Initialization does not reliably work after reset because the device
+	 *  is held in reset by the AP. Running this command after boot finishes
+	 *  always succeeds. Remove once the reset signal changes.
+	 */
+	if (!strncmp(argv[1], "init", 4))
+		return pse_init_worker();
+
+	if (argc != 3)
+		return EC_ERROR_PARAM_COUNT;
+
+	port = atoi(argv[1]);
+	if (port < 0 || port >= LTC4291_PORT_MAX)
+		return EC_ERROR_PARAM1;
+
+	if (!strncmp(argv[2], "off", 3))
+		return pse_port_disable(port);
+	else if (!strncmp(argv[2], "on", 2))
+		return pse_port_enable(port);
+	else if (!strncmp(argv[2], "min", 3))
+		return pse_write_hpmd(port, LTC4291_HPMD_MIN);
+	else if (!strncmp(argv[2], "max", 3))
+		return pse_write_hpmd(port, LTC4291_HPMD_MAX);
+	else
+		return EC_ERROR_PARAM2;
+}
+DECLARE_CONSOLE_COMMAND(pse, command_pse, "<port# 0-3> <off | on | min | max>",
+			"Set PSE port power");
+
+static int ec_command_pse_status(int port, uint8_t *status)
+{
+	int detena, statpwr;
+	int err;
+
+	err = I2C_PSE_READ(DETENA, &detena);
+	if (err != EC_SUCCESS)
+		return err;
+
+	err = I2C_PSE_READ(STATPWR, &statpwr);
+	if (err != EC_SUCCESS)
+		return err;
+
+	if ((detena & LTC4291_DETENA_EN_PORT(port)) == 0)
+		*status = EC_PSE_STATUS_DISABLED;
+	else if ((statpwr & LTC4291_STATPWR_ON_PORT(port)) == 0)
+		*status = EC_PSE_STATUS_ENABLED;
+	else
+		*status = EC_PSE_STATUS_POWERED;
+
+	return EC_SUCCESS;
+}
+
+static enum ec_status ec_command_pse(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_pse *p = args->params;
+	int err = 0;
+
+	if (p->port >= LTC4291_PORT_MAX)
+		return EC_RES_INVALID_PARAM;
+
+	switch (p->cmd) {
+	case EC_PSE_STATUS: {
+		struct ec_response_pse_status *r = args->response;
+
+		args->response_size = sizeof(*r);
+		err = ec_command_pse_status(p->port, &r->status);
+		break;
+	}
+	case EC_PSE_ENABLE:
+		err = pse_port_enable(p->port);
+		break;
+	case EC_PSE_DISABLE:
+		err = pse_port_disable(p->port);
+		break;
+	default:
+		return EC_RES_INVALID_PARAM;
+	}
+
+	if (err)
+		return EC_RES_ERROR;
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_PSE, ec_command_pse, EC_VER_MASK(0));
diff --git a/driver/regulator_ir357x.c b/driver/regulator_ir357x.c
index 4721146367..24e4e26bbe 100644
--- a/driver/regulator_ir357x.c
+++ b/driver/regulator_ir357x.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -14,7 +14,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
-#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ##args)
 
 /* I2C address */
 #define IR357x_I2C_ADDR_FLAGS 0x08
@@ -25,73 +25,72 @@ struct ir_setting {
 };
 
 static struct ir_setting ir3570_settings[] = {
-	{0x10, 0x22}, {0x11, 0x22}, {0x12, 0x88}, {0x13, 0x10},
-	{0x14, 0x0d}, {0x15, 0x21}, {0x16, 0x21}, {0x17, 0x00},
-	{0x18, 0x00}, {0x19, 0x00}, {0x1a, 0x00}, {0x1b, 0x00},
-	{0x1c, 0x00}, {0x1d, 0x00}, {0x1e, 0x00}, {0x1f, 0x00},
-	{0x20, 0x00}, {0x21, 0x00}, {0x22, 0x60}, {0x23, 0x60},
-	{0x24, 0x74}, {0x25, 0x4e}, {0x26, 0xff}, {0x27, 0x80},
-	{0x28, 0x00}, {0x29, 0x20}, {0x2a, 0x15}, {0x2b, 0x26},
-	{0x2c, 0xb6}, {0x2d, 0x21}, {0x2e, 0x11}, {0x2f, 0x20},
-	{0x30, 0xab}, {0x31, 0x14}, {0x32, 0x90}, {0x33, 0x4d},
-	{0x34, 0x75}, {0x35, 0x64}, {0x36, 0x64}, {0x37, 0x09},
-	{0x38, 0xc4}, {0x39, 0x20}, {0x3a, 0x80}, {0x3b, 0x00},
-	{0x3c, 0x00}, {0x3d, 0xaa}, {0x3e, 0x00}, {0x3f, 0x05},
-	{0x40, 0x50}, {0x41, 0x40}, {0x42, 0x00}, {0x43, 0x00},
-	{0x44, 0x00}, {0x45, 0x00}, {0x46, 0x00}, {0x47, 0x00},
-	{0x48, 0x1c}, {0x49, 0x0c}, {0x4a, 0x0f}, {0x4b, 0x40},
-	{0x4c, 0x80}, {0x4d, 0x40}, {0x4e, 0x80},
-	{0x51, 0x00}, {0x52, 0x45}, {0x53, 0x59},
-	{0x54, 0x23}, {0x55, 0xae}, {0x56, 0x68}, {0x57, 0x24},
-	{0x58, 0x62}, {0x59, 0x42}, {0x5a, 0x34}, {0x5b, 0x00},
-	{0x5c, 0x30}, {0x5d, 0x05}, {0x5e, 0x02}, {0x5f, 0x35},
-	{0x60, 0x30}, {0x61, 0x00}, {0x62, 0xd8}, {0x63, 0x00},
-	{0x64, 0x52}, {0x65, 0x28}, {0x66, 0x14}, {0x67, 0x87},
-	{0x68, 0x80}, {0x69, 0x00}, {0x6a, 0x00}, {0x6b, 0x00},
-	{0x6c, 0x00}, {0x6d, 0xff}, {0x6e, 0x06}, {0x6f, 0xff},
-	{0x70, 0xff}, {0x71, 0x20}, {0x72, 0x00}, {0x73, 0x01},
-	{0x74, 0x00}, {0x75, 0x00}, {0x76, 0x00}, {0x77, 0x00},
-	{0x78, 0x00}, {0x79, 0x00}, {0x7a, 0x00}, {0x7b, 0x00},
-	{0x7c, 0x15}, {0x7d, 0x15}, {0x7e, 0x00}, {0x7f, 0x00},
-	{0x80, 0x00}, {0x81, 0x00}, {0x82, 0x00}, {0x83, 0x00},
-	{0x84, 0x00}, {0x85, 0x00}, {0x86, 0x00}, {0x87, 0x00},
-	{0x88, 0x88}, {0x89, 0x88}, {0x8a, 0x01}, {0x8b, 0x42},
-	{0x8d, 0x00}, {0x8e, 0x00}, {0x8f, 0x1f},
-	{0, 0}
+	{ 0x10, 0x22 }, { 0x11, 0x22 }, { 0x12, 0x88 }, { 0x13, 0x10 },
+	{ 0x14, 0x0d }, { 0x15, 0x21 }, { 0x16, 0x21 }, { 0x17, 0x00 },
+	{ 0x18, 0x00 }, { 0x19, 0x00 }, { 0x1a, 0x00 }, { 0x1b, 0x00 },
+	{ 0x1c, 0x00 }, { 0x1d, 0x00 }, { 0x1e, 0x00 }, { 0x1f, 0x00 },
+	{ 0x20, 0x00 }, { 0x21, 0x00 }, { 0x22, 0x60 }, { 0x23, 0x60 },
+	{ 0x24, 0x74 }, { 0x25, 0x4e }, { 0x26, 0xff }, { 0x27, 0x80 },
+	{ 0x28, 0x00 }, { 0x29, 0x20 }, { 0x2a, 0x15 }, { 0x2b, 0x26 },
+	{ 0x2c, 0xb6 }, { 0x2d, 0x21 }, { 0x2e, 0x11 }, { 0x2f, 0x20 },
+	{ 0x30, 0xab }, { 0x31, 0x14 }, { 0x32, 0x90 }, { 0x33, 0x4d },
+	{ 0x34, 0x75 }, { 0x35, 0x64 }, { 0x36, 0x64 }, { 0x37, 0x09 },
+	{ 0x38, 0xc4 }, { 0x39, 0x20 }, { 0x3a, 0x80 }, { 0x3b, 0x00 },
+	{ 0x3c, 0x00 }, { 0x3d, 0xaa }, { 0x3e, 0x00 }, { 0x3f, 0x05 },
+	{ 0x40, 0x50 }, { 0x41, 0x40 }, { 0x42, 0x00 }, { 0x43, 0x00 },
+	{ 0x44, 0x00 }, { 0x45, 0x00 }, { 0x46, 0x00 }, { 0x47, 0x00 },
+	{ 0x48, 0x1c }, { 0x49, 0x0c }, { 0x4a, 0x0f }, { 0x4b, 0x40 },
+	{ 0x4c, 0x80 }, { 0x4d, 0x40 }, { 0x4e, 0x80 }, { 0x51, 0x00 },
+	{ 0x52, 0x45 }, { 0x53, 0x59 }, { 0x54, 0x23 }, { 0x55, 0xae },
+	{ 0x56, 0x68 }, { 0x57, 0x24 }, { 0x58, 0x62 }, { 0x59, 0x42 },
+	{ 0x5a, 0x34 }, { 0x5b, 0x00 }, { 0x5c, 0x30 }, { 0x5d, 0x05 },
+	{ 0x5e, 0x02 }, { 0x5f, 0x35 }, { 0x60, 0x30 }, { 0x61, 0x00 },
+	{ 0x62, 0xd8 }, { 0x63, 0x00 }, { 0x64, 0x52 }, { 0x65, 0x28 },
+	{ 0x66, 0x14 }, { 0x67, 0x87 }, { 0x68, 0x80 }, { 0x69, 0x00 },
+	{ 0x6a, 0x00 }, { 0x6b, 0x00 }, { 0x6c, 0x00 }, { 0x6d, 0xff },
+	{ 0x6e, 0x06 }, { 0x6f, 0xff }, { 0x70, 0xff }, { 0x71, 0x20 },
+	{ 0x72, 0x00 }, { 0x73, 0x01 }, { 0x74, 0x00 }, { 0x75, 0x00 },
+	{ 0x76, 0x00 }, { 0x77, 0x00 }, { 0x78, 0x00 }, { 0x79, 0x00 },
+	{ 0x7a, 0x00 }, { 0x7b, 0x00 }, { 0x7c, 0x15 }, { 0x7d, 0x15 },
+	{ 0x7e, 0x00 }, { 0x7f, 0x00 }, { 0x80, 0x00 }, { 0x81, 0x00 },
+	{ 0x82, 0x00 }, { 0x83, 0x00 }, { 0x84, 0x00 }, { 0x85, 0x00 },
+	{ 0x86, 0x00 }, { 0x87, 0x00 }, { 0x88, 0x88 }, { 0x89, 0x88 },
+	{ 0x8a, 0x01 }, { 0x8b, 0x42 }, { 0x8d, 0x00 }, { 0x8e, 0x00 },
+	{ 0x8f, 0x1f }, { 0, 0 }
 };
 
 static struct ir_setting ir3571_settings[] = {
-	{0x18, 0x22}, {0x19, 0x22}, {0x1a, 0x08}, {0x1b, 0x10},
-	{0x1c, 0x06}, {0x1d, 0x21}, {0x1e, 0x21}, {0x1f, 0x83},
-	{0x20, 0x83}, {0x21, 0x00}, {0x22, 0x00}, {0x23, 0x00},
-	{0x24, 0x00}, {0x25, 0x00}, {0x26, 0x00}, {0x27, 0x34},
-	{0x28, 0x34}, {0x29, 0x74}, {0x2a, 0x4e}, {0x2b, 0xff},
-	{0x2c, 0x00}, {0x2d, 0x1d}, {0x2e, 0x14}, {0x2f, 0x1f},
-	{0x30, 0x88}, {0x31, 0x9a}, {0x32, 0x1e}, {0x33, 0x19},
-	{0x34, 0xe9}, {0x35, 0x40}, {0x36, 0x90}, {0x37, 0x6d},
-	{0x38, 0x75}, {0x39, 0xa0}, {0x3a, 0x84}, {0x3b, 0x08},
-	{0x3c, 0xc5}, {0x3d, 0xa0}, {0x3e, 0x80}, {0x3f, 0xaa},
-	{0x40, 0x50}, {0x41, 0x4b}, {0x42, 0x02}, {0x43, 0x04},
-	{0x44, 0x00}, {0x45, 0x00}, {0x46, 0x00}, {0x47, 0x78},
-	{0x48, 0x56}, {0x49, 0x18}, {0x4a, 0x88}, {0x4b, 0x00},
-	{0x4c, 0x80}, {0x4d, 0x60}, {0x4e, 0x60}, {0x4f, 0xff},
-	{0x50, 0xff}, {0x51, 0x00}, {0x52, 0x9b}, {0x53, 0xaa},
-	{0x54, 0xd8}, {0x55, 0x56}, {0x56, 0x31}, {0x57, 0x1a},
-	{0x58, 0x12}, {0x59, 0x63}, {0x5a, 0x00}, {0x5b, 0x09},
-	{0x5c, 0x02}, {0x5d, 0x00}, {0x5e, 0xea}, {0x5f, 0x00},
-	{0x60, 0xb0}, {0x61, 0x1e}, {0x62, 0x00}, {0x63, 0x56},
-	{0x64, 0x00}, {0x65, 0x00}, {0x66, 0x00}, {0x67, 0x00},
-	{0x68, 0x28}, {0x69, 0x00}, {0x6a, 0x00}, {0x6b, 0x00},
-	{0x6c, 0x00}, {0x6d, 0x00}, {0x6e, 0x00}, {0x6f, 0x00},
-	{0x70, 0x80}, {0x71, 0x00}, {0x72, 0x00}, {0x73, 0x00},
-	{0x74, 0x00}, {0x75, 0xbf}, {0x76, 0x06}, {0x77, 0xff},
-	{0x78, 0xff}, {0x79, 0x04}, {0x7a, 0x00}, {0x7b, 0x1d},
-	{0x7c, 0xa0}, {0x7d, 0x10}, {0x7e, 0x00}, {0x7f, 0x8a},
-	{0x80, 0x1b}, {0x81, 0x11}, {0x82, 0x00}, {0x83, 0x00},
-	{0x84, 0x00}, {0x85, 0x00}, {0x86, 0x00}, {0x87, 0x00},
-	{0x88, 0x00}, {0x89, 0x00}, {0x8a, 0x00}, {0x8b, 0x00},
-	{0x8c, 0x00}, {0x8d, 0x00}, {0x8e, 0x00}, {0x8f, 0x00},
-	{0, 0}
+	{ 0x18, 0x22 }, { 0x19, 0x22 }, { 0x1a, 0x08 }, { 0x1b, 0x10 },
+	{ 0x1c, 0x06 }, { 0x1d, 0x21 }, { 0x1e, 0x21 }, { 0x1f, 0x83 },
+	{ 0x20, 0x83 }, { 0x21, 0x00 }, { 0x22, 0x00 }, { 0x23, 0x00 },
+	{ 0x24, 0x00 }, { 0x25, 0x00 }, { 0x26, 0x00 }, { 0x27, 0x34 },
+	{ 0x28, 0x34 }, { 0x29, 0x74 }, { 0x2a, 0x4e }, { 0x2b, 0xff },
+	{ 0x2c, 0x00 }, { 0x2d, 0x1d }, { 0x2e, 0x14 }, { 0x2f, 0x1f },
+	{ 0x30, 0x88 }, { 0x31, 0x9a }, { 0x32, 0x1e }, { 0x33, 0x19 },
+	{ 0x34, 0xe9 }, { 0x35, 0x40 }, { 0x36, 0x90 }, { 0x37, 0x6d },
+	{ 0x38, 0x75 }, { 0x39, 0xa0 }, { 0x3a, 0x84 }, { 0x3b, 0x08 },
+	{ 0x3c, 0xc5 }, { 0x3d, 0xa0 }, { 0x3e, 0x80 }, { 0x3f, 0xaa },
+	{ 0x40, 0x50 }, { 0x41, 0x4b }, { 0x42, 0x02 }, { 0x43, 0x04 },
+	{ 0x44, 0x00 }, { 0x45, 0x00 }, { 0x46, 0x00 }, { 0x47, 0x78 },
+	{ 0x48, 0x56 }, { 0x49, 0x18 }, { 0x4a, 0x88 }, { 0x4b, 0x00 },
+	{ 0x4c, 0x80 }, { 0x4d, 0x60 }, { 0x4e, 0x60 }, { 0x4f, 0xff },
+	{ 0x50, 0xff }, { 0x51, 0x00 }, { 0x52, 0x9b }, { 0x53, 0xaa },
+	{ 0x54, 0xd8 }, { 0x55, 0x56 }, { 0x56, 0x31 }, { 0x57, 0x1a },
+	{ 0x58, 0x12 }, { 0x59, 0x63 }, { 0x5a, 0x00 }, { 0x5b, 0x09 },
+	{ 0x5c, 0x02 }, { 0x5d, 0x00 }, { 0x5e, 0xea }, { 0x5f, 0x00 },
+	{ 0x60, 0xb0 }, { 0x61, 0x1e }, { 0x62, 0x00 }, { 0x63, 0x56 },
+	{ 0x64, 0x00 }, { 0x65, 0x00 }, { 0x66, 0x00 }, { 0x67, 0x00 },
+	{ 0x68, 0x28 }, { 0x69, 0x00 }, { 0x6a, 0x00 }, { 0x6b, 0x00 },
+	{ 0x6c, 0x00 }, { 0x6d, 0x00 }, { 0x6e, 0x00 }, { 0x6f, 0x00 },
+	{ 0x70, 0x80 }, { 0x71, 0x00 }, { 0x72, 0x00 }, { 0x73, 0x00 },
+	{ 0x74, 0x00 }, { 0x75, 0xbf }, { 0x76, 0x06 }, { 0x77, 0xff },
+	{ 0x78, 0xff }, { 0x79, 0x04 }, { 0x7a, 0x00 }, { 0x7b, 0x1d },
+	{ 0x7c, 0xa0 }, { 0x7d, 0x10 }, { 0x7e, 0x00 }, { 0x7f, 0x8a },
+	{ 0x80, 0x1b }, { 0x81, 0x11 }, { 0x82, 0x00 }, { 0x83, 0x00 },
+	{ 0x84, 0x00 }, { 0x85, 0x00 }, { 0x86, 0x00 }, { 0x87, 0x00 },
+	{ 0x88, 0x00 }, { 0x89, 0x00 }, { 0x8a, 0x00 }, { 0x8b, 0x00 },
+	{ 0x8c, 0x00 }, { 0x8d, 0x00 }, { 0x8e, 0x00 }, { 0x8f, 0x00 },
+	{ 0, 0 }
 };
 
 static uint8_t ir357x_read(uint8_t reg)
@@ -186,8 +185,8 @@ static int ir357x_check(void)
 	for (; settings->reg; settings++) {
 		val = ir357x_read(settings->reg);
 		if (val != settings->value) {
-			ccprintf("DIFF reg 0x%02x %02x->%02x\n",
-				 settings->reg, settings->value, val);
+			ccprintf("DIFF reg 0x%02x %02x->%02x\n", settings->reg,
+				 settings->value, val);
 			cflush();
 			diff++;
 		}
@@ -196,7 +195,7 @@ static int ir357x_check(void)
 }
 
 #ifdef CONFIG_CMD_REGULATOR
-static int command_ir357x(int argc, char **argv)
+static int command_ir357x(int argc, const char **argv)
 {
 	int reg, val;
 	char *rem;
@@ -234,8 +233,7 @@ static int command_ir357x(int argc, char **argv)
 
 	return EC_ERROR_INVAL;
 }
-DECLARE_CONSOLE_COMMAND(ir357x, command_ir357x,
-			"[check|write]",
+DECLARE_CONSOLE_COMMAND(ir357x, command_ir357x, "[check|write]",
 			"IR357x core regulator control");
 #endif
 
diff --git a/driver/retimer/anx7452.c b/driver/retimer/anx7452.c
new file mode 100644
index 0000000000..3a7a30b8ed
--- /dev/null
+++ b/driver/retimer/anx7452.c
@@ -0,0 +1,188 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * ANX7452: Active redriver with linear equalisation
+ */
+
+#include "anx7452.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "gpio.h"
+#include "i2c.h"
+#include "retimer/anx7452_public.h"
+#include "timer.h"
+#include "usb_mux.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+static int anx7452_top_read(const struct usb_mux *me, uint8_t reg, int *val)
+{
+	return i2c_read8(me->i2c_port, me->i2c_addr_flags, reg, val);
+}
+
+static int anx7452_top_update(const struct usb_mux *me, uint8_t reg,
+			      uint8_t mask, uint8_t val)
+{
+	return i2c_field_update8(me->i2c_port, me->i2c_addr_flags, reg, mask,
+				 val & mask);
+}
+
+static int anx7452_ctltop_update(const struct usb_mux *me, uint8_t reg,
+				 uint8_t mask, uint8_t val)
+{
+	return i2c_field_update8(me->i2c_port, ANX7452_I2C_ADDR_CTLTOP_FLAGS,
+				 reg, mask, val & mask);
+}
+
+static int anx7452_ctltop_update_all(const struct usb_mux *me, uint8_t cfg0_val,
+				     uint8_t cfg1_val, uint8_t cfg2_val)
+{
+	RETURN_ERROR(anx7452_ctltop_update(me, ANX7452_CTLTOP_CFG0_REG,
+					   ANX7452_CTLTOP_CFG0_REG_BIT_MASK,
+					   cfg0_val));
+	RETURN_ERROR(anx7452_ctltop_update(me, ANX7452_CTLTOP_CFG1_REG,
+					   ANX7452_CTLTOP_CFG1_REG_BIT_MASK,
+					   cfg1_val));
+	RETURN_ERROR(anx7452_ctltop_update(me, ANX7452_CTLTOP_CFG2_REG,
+					   ANX7452_CTLTOP_CFG2_REG_BIT_MASK,
+					   cfg2_val));
+	return EC_SUCCESS;
+}
+
+static int anx7452_power_enable(const struct usb_mux *me)
+{
+	int usb_enable;
+
+	usb_enable = anx7452_controls[me->usb_port].usb_enable_gpio;
+
+	if (chipset_in_state(CHIPSET_STATE_HARD_OFF)) {
+		return EC_ERROR_NOT_POWERED;
+	}
+
+	gpio_set_level(usb_enable, 1);
+	return EC_SUCCESS;
+}
+
+static int anx7452_i2c_awake(const struct usb_mux *me)
+{
+	int rv;
+	timestamp_t start;
+
+	/* Keep trying to update top register until mux wakes up or times
+	 * out
+	 */
+	start = get_time();
+	do {
+		/* Configure for i2c control */
+		rv = anx7452_top_update(
+			me, ANX7452_TOP_STATUS_REG,
+			ANX7452_TOP_STATUS_REG_I2C_CTRL_EN_BIT_MASK,
+			ANX7452_TOP_REG_EN);
+		if (rv == EC_SUCCESS) {
+			break;
+		}
+		usleep(ANX7452_I2C_WAKE_RETRY_DELAY_US);
+	} while (time_since32(start) < ANX7452_I2C_WAKE_TIMEOUT_MS * MSEC);
+	if (rv != EC_SUCCESS) {
+		CPRINTS("ANX7452: Failed to wake mux rv: %d", rv);
+		return EC_ERROR_TIMEOUT;
+	}
+
+	return EC_SUCCESS;
+}
+
+static int anx7452_init(const struct usb_mux *me)
+{
+	RETURN_ERROR(anx7452_power_enable(me));
+
+	msleep(ANX7452_I2C_PRE_WAKE_WAIT_MS);
+
+	RETURN_ERROR(anx7452_i2c_awake(me));
+
+	return EC_SUCCESS;
+}
+
+static int anx7452_set(const struct usb_mux *me, mux_state_t mux_state,
+		       bool *ack_required)
+{
+	int cfg0_val = 0;
+	int cfg1_val = 0;
+	int cfg2_val = 0;
+
+	if (chipset_in_state(CHIPSET_STATE_HARD_OFF)) {
+		return EC_ERROR_NOT_POWERED;
+	}
+
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
+	/* Apply CC polarity settings */
+	if (mux_state & USB_PD_MUX_POLARITY_INVERTED) {
+		cfg0_val |= ANX7452_CTLTOP_CFG0_FLIP_EN;
+	}
+
+	/* Apply DP enable settings */
+	if (mux_state & USB_PD_MUX_DP_ENABLED) {
+		cfg1_val |= ANX7452_CTLTOP_CFG1_DP_EN;
+	}
+
+	/* Apply USB3 enable settings */
+	if (mux_state & USB_PD_MUX_USB_ENABLED) {
+		cfg0_val |= ANX7452_CTLTOP_CFG0_USB3_EN;
+	}
+
+	/* Apply USB4 enable settings */
+	if (mux_state & USB_PD_MUX_USB4_ENABLED) {
+		cfg2_val |= ANX7452_CTLTOP_CFG2_USB4_EN;
+	}
+
+	/* Apply TBT compatible enable settings */
+	if (mux_state & USB_PD_MUX_TBT_COMPAT_ENABLED) {
+		cfg2_val |= ANX7452_CTLTOP_CFG2_TBT_EN;
+	}
+
+	RETURN_ERROR(
+		anx7452_ctltop_update_all(me, cfg0_val, cfg1_val, cfg2_val));
+	return EC_SUCCESS;
+}
+
+static int anx7452_get(const struct usb_mux *me, mux_state_t *mux_state)
+{
+	int reg_val = 0;
+
+	if (chipset_in_state(CHIPSET_STATE_HARD_OFF)) {
+		*mux_state = USB_PD_MUX_NONE;
+		return EC_ERROR_NOT_POWERED;
+	}
+
+	RETURN_ERROR(anx7452_top_read(me, ANX7452_TOP_STATUS_REG, &reg_val));
+
+	*mux_state = 0;
+	if (reg_val & ANX7452_TOP_FLIP_INFO) {
+		*mux_state |= USB_PD_MUX_POLARITY_INVERTED;
+	}
+	if (reg_val & ANX7452_TOP_DP_INFO) {
+		*mux_state |= USB_PD_MUX_DP_ENABLED;
+	}
+	if (reg_val & ANX7452_TOP_TBT_INFO) {
+		*mux_state |= USB_PD_MUX_TBT_COMPAT_ENABLED;
+	}
+	if (reg_val & ANX7452_TOP_USB3_INFO) {
+		*mux_state |= USB_PD_MUX_USB_ENABLED;
+	}
+	if (reg_val & ANX7452_TOP_USB4_INFO) {
+		*mux_state |= USB_PD_MUX_USB4_ENABLED;
+	}
+
+	return EC_SUCCESS;
+}
+
+const struct usb_mux_driver anx7452_usb_retimer_driver = {
+	.init = anx7452_init,
+	.set = anx7452_set,
+	.get = anx7452_get,
+};
diff --git a/driver/retimer/anx7452.h b/driver/retimer/anx7452.h
new file mode 100644
index 0000000000..b20e294e69
--- /dev/null
+++ b/driver/retimer/anx7452.h
@@ -0,0 +1,80 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * ANX7452: 2-Lane USB4 Retimer MUX driver
+ */
+
+#ifndef __CROS_EC_USB_RETIMER_ANX7452_H
+#define __CROS_EC_USB_RETIMER_ANX7452_H
+
+/*
+ * Programming guide specifies it may be as much as 30-50 ms after chip power on
+ * before it's ready for i2c
+ */
+#define ANX7452_I2C_PRE_WAKE_WAIT_MS 30
+#define ANX7452_I2C_WAKE_TIMEOUT_MS 50
+#define ANX7452_I2C_WAKE_RETRY_DELAY_US 3000
+
+/*
+ * CTLTOP I2C address (7 bit)
+ */
+#define ANX7452_I2C_ADDR_CTLTOP_FLAGS 0x20
+
+/*
+ * TOP Status register
+ *
+ * 7   EN (0: Config info from pins, 1: Config info from registers)
+ * 6   Reserved
+ * 5   SWAP (0: host side, 1: device side)
+ * 4   FLIP info (Read only use)
+ * 3   USB4 info (Read only use)
+ * 2   TBT info (Read only use)
+ * 1   DP info (Read only use)
+ * 0   USB3 info (Read only use)
+ */
+#define ANX7452_TOP_STATUS_REG 0xF8
+#define ANX7452_TOP_REG_EN BIT(7)
+#define ANX7452_TOP_RESERVED_BIT BIT(6)
+#define ANX7452_TOP_SWAP_EN BIT(5)
+#define ANX7452_TOP_FLIP_INFO BIT(4)
+#define ANX7452_TOP_USB4_INFO BIT(3)
+#define ANX7452_TOP_TBT_INFO BIT(2)
+#define ANX7452_TOP_DP_INFO BIT(1)
+#define ANX7452_TOP_USB3_INFO BIT(0)
+#define ANX7452_TOP_STATUS_REG_I2C_CTRL_EN_BIT_MASK ANX7452_TOP_REG_EN
+#define ANX7452_TOP_STATUS_REG_SWAP_EN_BIT_MASK ANX7452_TOP_SWAP_EN
+
+/*
+ * CTLTOP - 0 register
+ *
+ * 5   USB3 info (To set Bit 0 of TOP Status register indirectly)
+ * 1   FLIP info (To set BIT 4 of TOP Status register indirectly)
+ */
+#define ANX7452_CTLTOP_CFG0_REG 0x04
+#define ANX7452_CTLTOP_CFG0_USB3_EN BIT(5)
+#define ANX7452_CTLTOP_CFG0_FLIP_EN BIT(1)
+#define ANX7452_CTLTOP_CFG0_REG_BIT_MASK \
+	(ANX7452_CTLTOP_CFG0_USB3_EN | ANX7452_CTLTOP_CFG0_FLIP_EN)
+
+/*
+ * CTLTOP - 1 register
+ *
+ * 0   DP info (To set Bit 1 of TOP Status register indirectly)
+ */
+#define ANX7452_CTLTOP_CFG1_REG 0x05
+#define ANX7452_CTLTOP_CFG1_DP_EN BIT(0)
+#define ANX7452_CTLTOP_CFG1_REG_BIT_MASK ANX7452_CTLTOP_CFG1_DP_EN
+
+/*
+ * CTLTOP - 2 register
+ *
+ * 7   USB4 info (To set Bit 3 of TOP Status register indirectly)
+ * 0   TBT info (To set BIT 2 of TOP Status register indirectly)
+ */
+#define ANX7452_CTLTOP_CFG2_REG 0x06
+#define ANX7452_CTLTOP_CFG2_USB4_EN BIT(7)
+#define ANX7452_CTLTOP_CFG2_TBT_EN BIT(0)
+#define ANX7452_CTLTOP_CFG2_REG_BIT_MASK \
+	(ANX7452_CTLTOP_CFG2_USB4_EN | ANX7452_CTLTOP_CFG2_TBT_EN)
+#endif /* __CROS_EC_USB_RETIMER_ANX7452_H */
diff --git a/driver/retimer/anx7483.c b/driver/retimer/anx7483.c
new file mode 100644
index 0000000000..b4532ee12c
--- /dev/null
+++ b/driver/retimer/anx7483.c
@@ -0,0 +1,392 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * ANX7483: Active redriver with linear equilzation
+ */
+
+#include "anx7483.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "i2c.h"
+#include "retimer/anx7483_public.h"
+#include "timer.h"
+#include "usb_mux.h"
+#include "util.h"
+
+/*
+ * Programming guide specifies it may be as much as 30ms after chip power on
+ * before it's ready for i2c
+ */
+#define ANX7483_I2C_WAKE_TIMEOUT_MS 30
+#define ANX7483_I2C_WAKE_RETRY_DELAY_US 5000
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+const test_export_static struct anx7483_tuning_set anx7483_usb_enabled[] = {
+	{ ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+	{ ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+	{ ANX7483_DRX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+	{ ANX7483_DRX2_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+
+	{ ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+	{ ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+	{ ANX7483_DRX1_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+	{ ANX7483_DRX2_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+
+	{ ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE },
+	{ ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE },
+	{ ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE },
+	{ ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE },
+
+	{ ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+	{ ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+	{ ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+	{ ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+
+	{ ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+	{ ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+	{ ANX7483_DRX1_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+	{ ANX7483_DRX2_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+
+	{ ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT },
+	{ ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT },
+	{ ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT },
+	{ ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT },
+
+	{ ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+	{ ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+	{ ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+	{ ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+};
+
+const test_export_static struct anx7483_tuning_set anx7483_dp_enabled[] = {
+	{ ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF },
+
+	{ ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+	{ ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+	{ ANX7483_UTX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+	{ ANX7483_UTX2_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+
+	{ ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+	{ ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+	{ ANX7483_UTX1_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+	{ ANX7483_UTX2_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+
+	{ ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+	{ ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+	{ ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+	{ ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+	{ ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+	{ ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+	{ ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+	{ ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+
+	{ ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+	{ ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+	{ ANX7483_UTX1_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+	{ ANX7483_UTX2_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+
+	{ ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+	{ ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+	{ ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+	{ ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+	{ ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+	{ ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+	{ ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+	{ ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+};
+
+const test_export_static struct anx7483_tuning_set anx7483_dock_noflip[] = {
+	{ ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF },
+
+	{ ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+	{ ANX7483_DRX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+	{ ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+	{ ANX7483_UTX2_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+
+	{ ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+	{ ANX7483_DRX1_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+	{ ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+	{ ANX7483_UTX2_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+
+	{ ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE },
+	{ ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE },
+
+	{ ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+	{ ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+	{ ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+	{ ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+	{ ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+	{ ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+
+	{ ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+	{ ANX7483_DRX1_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+	{ ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+	{ ANX7483_UTX2_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+
+	{ ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+	{ ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+	{ ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+	{ ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+	{ ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+	{ ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+	{ ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+	{ ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+};
+
+const test_export_static struct anx7483_tuning_set anx7483_dock_flip[] = {
+	{ ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF },
+
+	{ ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+	{ ANX7483_DRX2_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+	{ ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+	{ ANX7483_UTX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+
+	{ ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+	{ ANX7483_DRX2_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+	{ ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+	{ ANX7483_UTX1_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+
+	{ ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE },
+	{ ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE },
+
+	{ ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+	{ ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+	{ ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+	{ ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+	{ ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+	{ ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+
+	{ ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+	{ ANX7483_UTX1_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+	{ ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+	{ ANX7483_DRX2_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+
+	{ ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+	{ ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+	{ ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+	{ ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+	{ ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+	{ ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+	{ ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+	{ ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+};
+
+const size_t anx7483_usb_enabled_count = ARRAY_SIZE(anx7483_usb_enabled);
+const size_t anx7483_dp_enabled_count = ARRAY_SIZE(anx7483_dp_enabled);
+const size_t anx7483_dock_noflip_count = ARRAY_SIZE(anx7483_dock_noflip);
+const size_t anx7483_dock_flip_count = ARRAY_SIZE(anx7483_dock_flip);
+
+test_export_static int anx7483_read(const struct usb_mux *me, uint8_t reg,
+				    int *val)
+{
+	return i2c_read8(me->i2c_port, me->i2c_addr_flags, reg, val);
+}
+
+test_export_static int anx7483_write(const struct usb_mux *me, uint8_t reg,
+				     uint8_t val)
+{
+	return i2c_write8(me->i2c_port, me->i2c_addr_flags, reg, val);
+}
+
+test_export_static int anx7483_init(const struct usb_mux *me)
+{
+	timestamp_t start;
+	int rv;
+	int val;
+
+	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	/* Keep reading control register until mux wakes up or times out */
+	start = get_time();
+	do {
+		rv = anx7483_read(me, ANX7483_ANALOG_STATUS_CTRL_REG, &val);
+		if (!rv)
+			break;
+		usleep(ANX7483_I2C_WAKE_RETRY_DELAY_US);
+	} while (time_since32(start) < ANX7483_I2C_WAKE_TIMEOUT_MS * MSEC);
+
+	if (rv) {
+		CPRINTS("ANX7483: Failed to wake mux rv:%d", rv);
+		return EC_ERROR_TIMEOUT;
+	}
+
+	/* Configure for i2c control */
+	val |= ANX7483_CTRL_REG_EN;
+	RETURN_ERROR(anx7483_write(me, ANX7483_ANALOG_STATUS_CTRL_REG, val));
+
+	return EC_SUCCESS;
+}
+
+test_export_static int anx7483_set(const struct usb_mux *me,
+				   mux_state_t mux_state, bool *ack_required)
+{
+	int reg;
+	int val;
+
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
+	/* This driver treats safe mode as none */
+	if (mux_state & USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
+
+	/*
+	 * Mux is not powered in Z1
+	 */
+	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	/*
+	 * Always ensure i2c control is set and state machine is enabled
+	 * (setting ANX7483_CTRL_REG_BYPASS_EN disables state machine)
+	 * Not recommend because it turns off whole low power function
+	 */
+	/*
+	 * Modify LFPS_TIMER to prevent going USB SLUMBER state too early
+	 */
+	RETURN_ERROR(anx7483_read(me, ANX7483_LFPS_TIMER_REG, &val));
+	val &= ~ANX7483_LFPS_TIMER_MASK;
+	val |= ANX7483_LFPS_TIMER_SLUMBER_TIME_H << ANX7483_LFPS_TIMER_SHIFT;
+	RETURN_ERROR(anx7483_write(me, ANX7483_LFPS_TIMER_REG, val));
+
+	reg = ANX7483_CTRL_REG_EN;
+	if (mux_state & USB_PD_MUX_USB_ENABLED)
+		reg |= ANX7483_CTRL_USB_EN;
+	if (mux_state & USB_PD_MUX_DP_ENABLED)
+		reg |= ANX7483_CTRL_DP_EN;
+	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
+		reg |= ANX7483_CTRL_FLIP_EN;
+
+	return anx7483_write(me, ANX7483_ANALOG_STATUS_CTRL_REG, reg);
+}
+
+test_export_static int anx7483_get(const struct usb_mux *me,
+				   mux_state_t *mux_state)
+{
+	int reg;
+
+	/* Mux is not powered in Z1 */
+	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
+		return USB_PD_MUX_NONE;
+
+	*mux_state = 0;
+	RETURN_ERROR(anx7483_read(me, ANX7483_ANALOG_STATUS_CTRL_REG, &reg));
+
+	if (reg & ANX7483_CTRL_USB_EN)
+		*mux_state |= USB_PD_MUX_USB_ENABLED;
+	if (reg & ANX7483_CTRL_DP_EN)
+		*mux_state |= USB_PD_MUX_DP_ENABLED;
+	if (reg & ANX7483_CTRL_FLIP_EN)
+		*mux_state |= USB_PD_MUX_POLARITY_INVERTED;
+
+	return EC_SUCCESS;
+}
+
+/* Helper to apply entire array of tuning registers, returning on first error */
+static enum ec_error_list
+anx7483_apply_tuning(const struct usb_mux *me,
+		     const struct anx7483_tuning_set *reg, int num)
+{
+	int i;
+
+	for (i = 0; i < num; i++) {
+		RETURN_ERROR(anx7483_write(me, reg[i].addr, reg[i].value));
+	}
+
+	return EC_SUCCESS;
+}
+
+int anx7483_set_default_tuning(const struct usb_mux *me, mux_state_t mux_state)
+{
+	bool flipped = mux_state & USB_PD_MUX_POLARITY_INVERTED;
+
+	/* Remove flipped from the state for easier compraisons */
+	mux_state = mux_state & ~USB_PD_MUX_POLARITY_INVERTED;
+
+	/* Enable i2c configuration of tuning registers */
+	RETURN_ERROR(anx7483_write(me, ANX7483_ENABLE_EQ_FLAT_SWING_REG,
+				   ANX7483_ENABLE_EQ_FLAT_SWING_EN));
+
+	if (mux_state == USB_PD_MUX_USB_ENABLED) {
+		return anx7483_apply_tuning(me, anx7483_usb_enabled,
+					    ARRAY_SIZE(anx7483_usb_enabled));
+	} else if (mux_state == USB_PD_MUX_DP_ENABLED) {
+		return anx7483_apply_tuning(me, anx7483_dp_enabled,
+					    ARRAY_SIZE(anx7483_dp_enabled));
+	} else if (mux_state == USB_PD_MUX_DOCK && !flipped) {
+		return anx7483_apply_tuning(me, anx7483_dock_noflip,
+					    ARRAY_SIZE(anx7483_dock_noflip));
+	} else if (mux_state == USB_PD_MUX_DOCK && flipped) {
+		return anx7483_apply_tuning(me, anx7483_dock_flip,
+					    ARRAY_SIZE(anx7483_dock_flip));
+	}
+
+	return EC_SUCCESS;
+}
+
+enum ec_error_list anx7483_set_eq(const struct usb_mux *me,
+				  enum anx7483_tune_pin pin,
+				  enum anx7483_eq_setting eq)
+{
+	int reg, value;
+
+	if (pin == ANX7483_PIN_UTX1)
+		reg = ANX7483_UTX1_PORT_CFG0_REG;
+	else if (pin == ANX7483_PIN_UTX2)
+		reg = ANX7483_UTX2_PORT_CFG0_REG;
+	else if (pin == ANX7483_PIN_URX1)
+		reg = ANX7483_URX1_PORT_CFG0_REG;
+	else if (pin == ANX7483_PIN_URX2)
+		reg = ANX7483_URX2_PORT_CFG0_REG;
+	else if (pin == ANX7483_PIN_DRX1)
+		reg = ANX7483_DRX1_PORT_CFG0_REG;
+	else if (pin == ANX7483_PIN_DRX2)
+		reg = ANX7483_DRX2_PORT_CFG0_REG;
+	else
+		return EC_ERROR_INVAL;
+
+	RETURN_ERROR(anx7483_read(me, reg, &value));
+	value &= ~ANX7483_CFG0_EQ_MASK;
+	value |= eq << ANX7483_CFG0_EQ_SHIFT;
+
+	return anx7483_write(me, reg, value);
+}
+
+enum ec_error_list anx7483_set_fg(const struct usb_mux *me,
+				  enum anx7483_tune_pin pin,
+				  enum anx7483_fg_setting fg)
+{
+	int reg, value;
+
+	if (pin == ANX7483_PIN_UTX1)
+		reg = ANX7483_UTX1_PORT_CFG2_REG;
+	else if (pin == ANX7483_PIN_UTX2)
+		reg = ANX7483_UTX2_PORT_CFG2_REG;
+	else if (pin == ANX7483_PIN_URX1)
+		reg = ANX7483_URX1_PORT_CFG2_REG;
+	else if (pin == ANX7483_PIN_URX2)
+		reg = ANX7483_URX2_PORT_CFG2_REG;
+	else if (pin == ANX7483_PIN_DRX1)
+		reg = ANX7483_DRX1_PORT_CFG2_REG;
+	else if (pin == ANX7483_PIN_DRX2)
+		reg = ANX7483_DRX2_PORT_CFG2_REG;
+	else
+		return EC_ERROR_INVAL;
+
+	RETURN_ERROR(anx7483_read(me, reg, &value));
+	value &= ~ANX7483_CFG2_FG_MASK;
+	value |= fg << ANX7483_CFG2_FG_SHIFT;
+
+	return anx7483_write(me, reg, value);
+}
+
+const struct usb_mux_driver anx7483_usb_retimer_driver = {
+	.init = anx7483_init,
+	.set = anx7483_set,
+	.get = anx7483_get,
+};
diff --git a/driver/retimer/anx7483.h b/driver/retimer/anx7483.h
new file mode 100644
index 0000000000..a478f5abf6
--- /dev/null
+++ b/driver/retimer/anx7483.h
@@ -0,0 +1,185 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * ANX7483: Active redriver with linear equilzation
+ */
+
+#ifndef __CROS_EC_USB_RETIMER_ANX7483_H
+#define __CROS_EC_USB_RETIMER_ANX7483_H
+
+#include "common.h"
+
+/* Tuning defaults */
+struct anx7483_tuning_set {
+	uint8_t addr;
+	uint8_t value;
+};
+
+/*
+ * LFPS_TIMER register
+ *
+ * 7:4 Reserved
+ * 3:0 SLUMBER_TIMER_H (usb when ss and lfps not received min 24ms max 300ms,
+ *                      enter SLUMBER state)
+ */
+#define ANX7483_LFPS_TIMER_REG 0x0F
+#define ANX7483_LFPS_TIMER_SLUMBER_TIME_H 0x04
+#define ANX7483_LFPS_TIMER_SHIFT 0
+#define ANX7483_LFPS_TIMER_MASK GENMASK(3, 0)
+
+/*
+ * Analog_Status_CTRL register
+ *
+ * 7:6 Reserved
+ * 5   Reg_bypass_EN (0: Enable state machine, 1: Disable state machine.)
+ * 4   Reg_EN (0: All configures are controlled by pin.
+ *             1: All configures are controlled by registers.)
+ * 3   Reserved
+ * 2   FLIP_EN (0: no flip; 1: enable flip.)
+ * 1   DP_EN (0: disable DP mode; 1: Enable DP mode.)
+ * 0   USB_EN (1: disable USB mode; 1: enable USB mode.)
+ */
+#define ANX7483_ANALOG_STATUS_CTRL_REG 0x07
+#define ANX7483_CTRL_REG_BYPASS_EN BIT(5)
+#define ANX7483_CTRL_REG_EN BIT(4)
+#define ANX7483_CTRL_FLIP_EN BIT(2)
+#define ANX7483_CTRL_DP_EN BIT(1)
+#define ANX7483_CTRL_USB_EN BIT(0)
+
+/*
+ * Register_EQ/FG/SW_EN register
+ * Enable equalizer/flat gain/output swing selection from pin or register
+ *
+ * 7:1 Reserved
+ * 0   Reg_EQ/FG/SW_EN (0: from pin control; 1: from register control)
+ */
+#define ANX7483_ENABLE_EQ_FLAT_SWING_REG 0x15
+#define ANX7483_ENABLE_EQ_FLAT_SWING_EN BIT(0)
+
+/*
+ * EQ Settings Registers
+ *
+ * 7:4 Equilation settings when pin is input
+ * 3:0 Fine tuning EQ step
+ */
+#define ANX7483_UTX1_PORT_CFG0_REG 0x52
+#define ANX7483_UTX2_PORT_CFG0_REG 0x16
+#define ANX7483_URX1_PORT_CFG0_REG 0x3E
+#define ANX7483_URX2_PORT_CFG0_REG 0x2A
+#define ANX7483_DRX1_PORT_CFG0_REG 0x5C
+#define ANX7483_DRX2_PORT_CFG0_REG 0x20
+
+#define ANX7483_CFG0_EQ_SHIFT 4
+#define ANX7483_CFG0_EQ_MASK GENMASK(7, 4)
+
+/*
+ * Default CFG0 value to apply: 9.2 dB with optimized tuning step
+ */
+#define ANX7483_CFG0_DEF 0x53
+
+/*
+ * Flat Gain Settings Registers
+ *
+ * 7:6 Fine tuning flat gain
+ * 5:4 Flat gain settings when pin is input
+ * 3:0 Fine tuning EQ
+ */
+#define ANX7483_UTX1_PORT_CFG2_REG 0x54
+#define ANX7483_UTX2_PORT_CFG2_REG 0x18
+#define ANX7483_URX1_PORT_CFG2_REG 0x40
+#define ANX7483_URX2_PORT_CFG2_REG 0x2C
+#define ANX7483_DRX1_PORT_CFG2_REG 0x5E
+#define ANX7483_DRX2_PORT_CFG2_REG 0x22
+
+#define ANX7483_CFG2_FG_SHIFT 4
+#define ANX7483_CFG2_FG_MASK GENMASK(5, 4)
+
+/*
+ * Default CFG2 value to apply: 0.3 dB with optimized fine tuning
+ */
+#define ANX7483_CFG2_DEF 0xEE
+
+/*
+ * Swing and 60K Input Termination Registers
+ *
+ * 7:6 Reserved
+ * 4   Enable 60k input termination during reset or RX termination not powered
+ * 3:2 Vendor internal use
+ * 1:0 Swing setting when configured as input port
+ */
+#define ANX7483_UTX1_PORT_CFG4_REG 0x56
+#define ANX7483_UTX2_PORT_CFG4_REG 0x1A
+#define ANX7483_URX1_PORT_CFG4_REG 0x42
+#define ANX7483_URX2_PORT_CFG4_REG 0x2E
+#define ANX7483_DRX1_PORT_CFG4_REG 0x60
+#define ANX7483_DRX2_PORT_CFG4_REG 0x24
+#define ANX7483_DTX1_PORT_CFG4_REG 0x4C
+#define ANX7483_DTX2_PORT_CFG4_REG 0x38
+
+/*
+ * Default values: 1300 mV gain with 60k termination either enabled or disabled
+ */
+#define ANX7483_CFG4_TERM_DISABLE 0x63
+#define ANX7483_CFG4_TERM_ENABLE 0x73
+
+/*
+ * Termination Resistance Registers
+ *
+ * 7:3 Termination resistance selection (00111:100 ohms; 01111:90 ohms.)
+ * 2   Termination resistance configuration for RX/TX mode (0: input, 1: output)
+ * 1   Enable termination res for UTX2 path. (0:disable 1: enable.)
+ * 0   Tune Flat Gain.
+ */
+#define ANX7483_UTX1_PORT_CFG3_REG 0x55
+#define ANX7483_UTX2_PORT_CFG3_REG 0x19
+#define ANX7483_URX1_PORT_CFG3_REG 0x41
+#define ANX7483_URX2_PORT_CFG3_REG 0x2D
+#define ANX7483_DTX1_PORT_CFG3_REG 0x4B
+#define ANX7483_DTX2_PORT_CFG3_REG 0x37
+#define ANX7483_DRX1_PORT_CFG3_REG 0x5F
+#define ANX7483_DRX2_PORT_CFG3_REG 0x23
+
+/*
+ * Default values: Either 100Ohm or 90Ohm, input or output
+ */
+#define ANX7483_CFG3_100Ohm_IN 0x3A
+#define ANX7483_CFG3_90Ohm_IN 0x7A
+#define ANX7483_CFG3_90Ohm_OUT 0x7E
+
+/*
+ * AUX_Snooping_CTRL register
+ *
+ * 7:3 Reserved
+ * 2:1 AUX_VTH (00:60mVppd, 01:90mVppd, 10:120mVppd, 11:140mVppd)
+ * 0   AUX_Snooping_EN (0: disable; 1: enable.)
+ */
+#define ANX7483_AUX_SNOOPING_CTRL_REG 0x13
+
+/*
+ * Default value: Enable snooping with 90mVppd
+ * (register ignored outside DP mode and does not need to be cleared)
+ */
+#define ANX7483_AUX_SNOOPING_DEF 0x13
+
+/*
+ * Middle Frequency Compensation
+ *
+ * 7:6 UTX1_EQ_CRT CTLE bias current when input
+ * 5:3 UTX1_EQ_MFR CTLE middle-freq resistance when input
+ * 2:0 UTX1_EQ_MFC CTLE middle-freq Capacitance
+ */
+#define ANX7483_UTX1_PORT_CFG1_REG 0x53
+#define ANX7483_UTX2_PORT_CFG1_REG 0x17
+#define ANX7483_URX1_PORT_CFG1_REG 0x3F
+#define ANX7483_URX2_PORT_CFG1_REG 0x2B
+#define ANX7483_DRX1_PORT_CFG1_REG 0x5D
+#define ANX7483_DRX2_PORT_CFG1_REG 0x21
+
+/*
+ * Default CFG1 setting: current bias max, Middle frequency resistance of 0x5,
+ * Middle frequency capacitance of 0x6
+ */
+#define ANX7483_CFG1_DEF 0xEE
+
+#endif /* __CROS_EC_USB_RETIMER_ANX7483_H */
diff --git a/driver/retimer/anx7491.h b/driver/retimer/anx7491.h
new file mode 100644
index 0000000000..9bf9594ea7
--- /dev/null
+++ b/driver/retimer/anx7491.h
@@ -0,0 +1,17 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * ANX7491:10G USB 3.2 Re-timer (1-Port)
+ */
+
+#ifndef __CROS_EC_USB_RETIMER_ANX7491_H
+#define __CROS_EC_USB_RETIMER_ANX7491_H
+
+/* I2C interface addresses */
+#define ANX7491_I2C_ADDR0_FLAGS 0x10
+#define ANX7491_I2C_ADDR1_FLAGS 0x14
+#define ANX7491_I2C_ADDR2_FLAGS 0x16
+#define ANX7491_I2C_ADDR3_FLAGS 0x11
+
+#endif /* __CROS_EC_USB_RETIMER_ANX7491_H */
diff --git a/driver/retimer/bb_retimer.c b/driver/retimer/bb_retimer.c
index 64ffa2b4dd..5571b666d4 100644
--- a/driver/retimer/bb_retimer.c
+++ b/driver/retimer/bb_retimer.c
@@ -1,64 +1,94 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Driver for Intel Burnside Bridge - Thunderbolt/USB/DisplayPort Retimer
  */
 
-#include "bb_retimer.h"
 #include "chipset.h"
 #include "common.h"
 #include "console.h"
+#include "driver/retimer/bb_retimer.h"
+#include "gpio.h"
+#include "hooks.h"
 #include "i2c.h"
 #include "task.h"
 #include "timer.h"
 #include "usb_pd.h"
 #include "util.h"
 
-#define BB_RETIMER_REG_SIZE	4
-#define BB_RETIMER_READ_SIZE	(BB_RETIMER_REG_SIZE + 1)
-#define BB_RETIMER_WRITE_SIZE	(BB_RETIMER_REG_SIZE + 2)
-#define BB_RETIMER_MUX_DATA_PRESENT (USB_PD_MUX_USB_ENABLED \
-				| USB_PD_MUX_DP_ENABLED \
-				| USB_PD_MUX_SAFE_MODE \
-				| USB_PD_MUX_TBT_COMPAT_ENABLED \
-				| USB_PD_MUX_USB4_ENABLED)
+#define BB_RETIMER_REG_SIZE 4
+#define BB_RETIMER_READ_SIZE (BB_RETIMER_REG_SIZE + 1)
+#define BB_RETIMER_WRITE_SIZE (BB_RETIMER_REG_SIZE + 2)
+#define BB_RETIMER_MUX_DATA_PRESENT                             \
+	(USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED |       \
+	 USB_PD_MUX_SAFE_MODE | USB_PD_MUX_TBT_COMPAT_ENABLED | \
+	 USB_PD_MUX_USB4_ENABLED)
 
-#define BB_RETIMER_MUX_USB_ALT_MODE (USB_PD_MUX_USB_ENABLED\
-				| USB_PD_MUX_DP_ENABLED \
-				| USB_PD_MUX_TBT_COMPAT_ENABLED \
-				| USB_PD_MUX_USB4_ENABLED)
+#define BB_RETIMER_MUX_USB_ALT_MODE                       \
+	(USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED | \
+	 USB_PD_MUX_TBT_COMPAT_ENABLED | USB_PD_MUX_USB4_ENABLED)
 
-#define BB_RETIMER_MUX_USB_DP_MODE (USB_PD_MUX_USB_ENABLED \
-				| USB_PD_MUX_DP_ENABLED \
-				| USB_PD_MUX_USB4_ENABLED)
+#define BB_RETIMER_MUX_USB_DP_MODE                        \
+	(USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED | \
+	 USB_PD_MUX_USB4_ENABLED)
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-/* Mutex for shared NVM access */
-static struct mutex bb_nvm_mutex;
+#define BB_RETIMER_I2C_RETRY 5
+#define BB_RETIMER_REG_OFFSET_MAX UINT8_MAX
+
+/*
+ * Mutex for BB_RETIMER_REG_CONNECTION_STATE register, which can be
+ * accessed from multiple tasks.
+ */
+static mutex_t bb_retimer_lock[CONFIG_USB_PD_PORT_MAX_COUNT];
+/*
+ * Requested BB mux state.
+ */
+static mux_state_t bb_mux_state[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 /**
  * Utility functions
  */
-static int bb_retimer_read(const struct usb_mux *me,
-			   const uint8_t offset, uint32_t *data)
+static int bb_retimer_read(const struct usb_mux *me, const uint32_t offset,
+			   uint32_t *data)
 {
-	int rv;
+	int rv, retry = 0;
 	uint8_t buf[BB_RETIMER_READ_SIZE];
 
+	/* Validate the register address */
+	if (offset > BB_RETIMER_REG_OFFSET_MAX)
+		return EC_ERROR_INVAL;
+
 	/*
-	 * Read sequence
-	 * Slave Addr(w) - Reg offset - repeated start - Slave Addr(r)
-	 * byte[0]   : Read size
-	 * byte[1:4] : Data [LSB -> MSB]
-	 * Stop
+	 * This I2C message will trigger retimer's internal read sequence
+	 * if its a NAK, sleep and resend same I2C
 	 */
-	rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags,
-		      &offset, 1, buf, BB_RETIMER_READ_SIZE);
-	if (rv)
-		return rv;
+	while (1) {
+		/*
+		 * Read sequence
+		 * Addr flags (w) - Reg offset - repeated start - Addr flags(r)
+		 * byte[0]   : Read size
+		 * byte[1:4] : Data [LSB -> MSB]
+		 * Stop
+		 */
+		rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags,
+			      (const uint8_t *)&offset, 1, buf,
+			      BB_RETIMER_READ_SIZE);
+
+		if (rv == EC_SUCCESS)
+			break;
+
+		if (++retry >= BB_RETIMER_I2C_RETRY) {
+			CPRINTS("C%d: Retimer I2C read err=%d", me->usb_port,
+				rv);
+			return rv;
+		}
+		msleep(10);
+	}
+
 	if (buf[0] != BB_RETIMER_REG_SIZE)
 		return EC_ERROR_UNKNOWN;
 
@@ -67,45 +97,59 @@ static int bb_retimer_read(const struct usb_mux *me,
 	return EC_SUCCESS;
 }
 
-static int bb_retimer_write(const struct usb_mux *me,
-			    const uint8_t offset, uint32_t data)
+static int bb_retimer_write(const struct usb_mux *me, const uint32_t offset,
+			    uint32_t data)
 {
+	int rv, retry = 0;
 	uint8_t buf[BB_RETIMER_WRITE_SIZE];
 
+	/* Validate the register address */
+	if (offset > BB_RETIMER_REG_OFFSET_MAX)
+		return EC_ERROR_INVAL;
+
 	/*
 	 * Write sequence
-	 * Slave Addr(w)
+	 * Addr flags(w)
 	 * byte[0]   : Reg offset
 	 * byte[1]   : Write Size
 	 * byte[2:5] : Data [LSB -> MSB]
 	 * stop
 	 */
-	buf[0] = offset;
+	buf[0] = (uint8_t)offset;
 	buf[1] = BB_RETIMER_REG_SIZE;
 	buf[2] = data & 0xFF;
 	buf[3] = (data >> 8) & 0xFF;
 	buf[4] = (data >> 16) & 0xFF;
 	buf[5] = (data >> 24) & 0xFF;
 
-	return i2c_xfer(me->i2c_port,
-			me->i2c_addr_flags,
-			buf, BB_RETIMER_WRITE_SIZE, NULL, 0);
+	/*
+	 * This I2C message will trigger retimer's internal write sequence
+	 * if its a NAK, sleep and resend same I2C
+	 */
+	while (1) {
+		rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags, buf,
+			      BB_RETIMER_WRITE_SIZE, NULL, 0);
+
+		if (rv == EC_SUCCESS)
+			break;
+
+		if (++retry >= BB_RETIMER_I2C_RETRY) {
+			CPRINTS("C%d: Retimer I2C write err=%d", me->usb_port,
+				rv);
+			break;
+		}
+		msleep(10);
+	}
+	return rv;
 }
 
-__overridable void bb_retimer_power_handle(const struct usb_mux *me, int on_off)
+__overridable int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
 {
 	const struct bb_usb_control *control = &bb_controls[me->usb_port];
 
 	/* handle retimer's power domain */
 
-	if (on_off) {
-		/*
-		 * BB retimer NVM can be shared between multiple ports, hence
-		 * lock enabling the retimer until the current retimer request
-		 * is complete.
-		 */
-		mutex_lock(&bb_nvm_mutex);
-
+	if (enable) {
 		gpio_set_level(control->usb_ls_en_gpio, 1);
 		/*
 		 * Tpw, minimum time from VCC to RESET_N de-assertion is 100us.
@@ -115,39 +159,28 @@ __overridable void bb_retimer_power_handle(const struct usb_mux *me, int on_off)
 		 */
 		msleep(1);
 		gpio_set_level(control->retimer_rst_gpio, 1);
-
-		/* Allow 20ms time for the retimer to be initialized. */
-		msleep(20);
-
-		mutex_unlock(&bb_nvm_mutex);
+		/*
+		 * Allow 1ms time for the retimer to power up lc_domain
+		 * which powers I2C controller within retimer
+		 */
+		msleep(1);
 	} else {
 		gpio_set_level(control->retimer_rst_gpio, 0);
 		msleep(1);
 		gpio_set_level(control->usb_ls_en_gpio, 0);
 	}
+	return EC_SUCCESS;
 }
 
 static void retimer_set_state_dfp(int port, mux_state_t mux_state,
 				  uint32_t *set_retimer_con)
 {
-	union tbt_mode_resp_cable cable_resp;
+	union tbt_mode_resp_cable cable_resp = {
+		.raw_value = pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME)
+	};
 	union tbt_mode_resp_device dev_resp;
 	enum idh_ptype cable_type = get_usb_pd_cable_type(port);
 
-	if (mux_state & USB_PD_MUX_USB_ENABLED) {
-		/*
-		 * Bit 4: USB2_CONNECTION (ignored if BIT5=0).
-		 * 0 - No USB2 Connection
-		 * 1 - USB2 connection
-		 *
-		 * For passive cable, USB2_CONNECTION = 1
-		 * For active cable, USB2_CONNECTION =
-		 * According to Active cable VDO2 Bit 5, USB 2.0 support.
-		 */
-		if (is_usb2_cable_support(port))
-			*set_retimer_con |= BB_RETIMER_USB_2_CONNECTION;
-	}
-
 	/*
 	 * Bit 2: RE_TIMER_DRIVER
 	 * 0 - Re-driver
@@ -158,7 +191,7 @@ static void retimer_set_state_dfp(int port, mux_state_t mux_state,
 	 *
 	 */
 	if (is_active_cable_element_retimer(port) &&
-	   (mux_state & BB_RETIMER_MUX_USB_DP_MODE))
+	    (mux_state & BB_RETIMER_MUX_USB_DP_MODE))
 		*set_retimer_con |= BB_RETIMER_RE_TIMER_DRIVER;
 
 	/*
@@ -170,13 +203,13 @@ static void retimer_set_state_dfp(int port, mux_state_t mux_state,
 	 * set according to Discover mode SOP' response.
 	 */
 	if ((mux_state & BB_RETIMER_MUX_USB_ALT_MODE) &&
-	    (cable_type == IDH_PTYPE_ACABLE))
+	    ((cable_type == IDH_PTYPE_ACABLE) ||
+	     cable_resp.tbt_active_passive == TBT_CABLE_ACTIVE))
 		*set_retimer_con |= BB_RETIMER_ACTIVE_PASSIVE;
 
-	if (mux_state & USB_PD_MUX_TBT_COMPAT_ENABLED) {
-		cable_resp.raw_value =
-			pd_get_tbt_mode_vdo(port, TCPC_TX_SOP_PRIME);
-		dev_resp.raw_value = pd_get_tbt_mode_vdo(port, TCPC_TX_SOP);
+	if (mux_state & USB_PD_MUX_TBT_COMPAT_ENABLED ||
+	    mux_state & USB_PD_MUX_USB4_ENABLED) {
+		dev_resp.raw_value = pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP);
 
 		/*
 		 * Bit 2: RE_TIMER_DRIVER
@@ -213,7 +246,8 @@ static void retimer_set_state_dfp(int port, mux_state_t mux_state,
 		 * 1 - vPro Dock or DP Overdrive
 		 *     detected
 		 */
-		if (dev_resp.intel_spec_b0 == VENDOR_SPECIFIC_SUPPORTED ||
+		if ((IS_ENABLED(CONFIG_USBC_RETIMER_INTEL_BB_VPRO_CAPABLE) &&
+		     dev_resp.intel_spec_b0 == VENDOR_SPECIFIC_SUPPORTED) ||
 		    dev_resp.vendor_spec_b1 == VENDOR_SPECIFIC_SUPPORTED)
 			*set_retimer_con |= BB_RETIMER_VPRO_DOCK_DP_OVERDRIVE;
 
@@ -223,12 +257,13 @@ static void retimer_set_state_dfp(int port, mux_state_t mux_state,
 		 * 1 - Active with uni-directional LSRX communication
 		 * Set to "0" when passive cable plug
 		 */
-		if (cable_type == IDH_PTYPE_ACABLE &&
+		if ((cable_type == IDH_PTYPE_ACABLE ||
+		     cable_resp.tbt_active_passive == TBT_CABLE_ACTIVE) &&
 		    cable_resp.lsrx_comm == UNIDIR_LSRX_COMM)
 			*set_retimer_con |= BB_RETIMER_TBT_ACTIVE_LINK_TRAINING;
 
 		/*
-		 * Bit 27-25: TBT Cable speed
+		 * Bit 27-25: USB4/TBT Cable speed
 		 * 000b - No functionality
 		 * 001b - USB3.1 Gen1 Cable
 		 * 010b - 10Gb/s
@@ -236,7 +271,10 @@ static void retimer_set_state_dfp(int port, mux_state_t mux_state,
 		 * 10..11b - Reserved
 		 */
 		*set_retimer_con |= BB_RETIMER_USB4_TBT_CABLE_SPEED_SUPPORT(
-						get_tbt_cable_speed(port));
+			mux_state & USB_PD_MUX_TBT_COMPAT_ENABLED ?
+				get_tbt_cable_speed(port) :
+				get_usb4_cable_speed(port));
+
 		/*
 		 * Bits 29-28: TBT_GEN_SUPPORT
 		 * 00b - 3rd generation TBT (10.3125 and 20.625Gb/s)
@@ -244,97 +282,129 @@ static void retimer_set_state_dfp(int port, mux_state_t mux_state,
 		 *                           20.0625Gb/s, 20.000Gb/s)
 		 * 10..11b - Reserved
 		 */
-		*set_retimer_con |= BB_RETIMER_TBT_CABLE_GENERATION(
-				       cable_resp.tbt_rounded);
-	} else if (mux_state & USB_PD_MUX_USB4_ENABLED) {
-		/*
-		 * Bit 27-25: USB4 Cable speed
-		 * 000b - No functionality
-		 * 001b - USB3.1 Gen1 Cable
-		 * 010b - 10Gb/s
-		 * 011b - 10Gb/s and 20Gb/s
-		 * 10..11b - Reserved
-		 */
-		*set_retimer_con |= BB_RETIMER_USB4_TBT_CABLE_SPEED_SUPPORT(
-					get_usb4_cable_speed(port));
+		*set_retimer_con |=
+			BB_RETIMER_TBT_CABLE_GENERATION(cable_resp.tbt_rounded);
 	}
 }
 
-static void retimer_set_state_ufp(mux_state_t mux_state,
+static void retimer_set_state_ufp(int port, mux_state_t mux_state,
 				  uint32_t *set_retimer_con)
 {
-	if (mux_state & USB_PD_MUX_USB_ENABLED) {
+	/*
+	 * Bit 7: USB_DATA_ROLE for the Burnside Bridge side of
+	 * connection.
+	 * 0 - DFP
+	 * 1 - UFP
+	 */
+	*set_retimer_con |= BB_RETIMER_USB_DATA_ROLE;
+
+	if (!IS_ENABLED(CONFIG_USB_PD_ALT_MODE_UFP))
+		return;
+
+	/* TODO:b/168890624: Set USB4 retimer config for UFP */
+	if (mux_state & USB_PD_MUX_TBT_COMPAT_ENABLED) {
+		union tbt_dev_mode_enter_cmd ufp_tbt_enter_mode = {
+			.raw_value = pd_ufp_get_enter_mode(port)
+		};
 		/*
-		 * Bit 4: USB2_CONNECTION (ignored if BIT5=0).
-		 * 0 - No USB2 Connection
-		 * 1 - USB2 connection
+		 * Bit 2: RE_TIMER_DRIVER
+		 * 0 - Re-driver
+		 * 1 - Re-timer
 		 *
-		 * Don't care
+		 * Set according to TBT3 Enter Mode bit 22.
 		 */
+		if (ufp_tbt_enter_mode.retimer_type == USB_RETIMER)
+			*set_retimer_con |= BB_RETIMER_RE_TIMER_DRIVER;
 
 		/*
-		 * Bit 7: USB_DATA_ROLE for the Burnside Bridge side of
-		 * connection (ignored if BIT5=0).
-		 * 0 - DFP
-		 * 1 - UFP
+		 * Bit 18: CABLE_TYPE
+		 * 0 - Electrical cable
+		 * 1 - Optical cable
+		 *
+		 * Set according to TBT3 Enter Mode bit 21.
 		 */
-		*set_retimer_con |= BB_RETIMER_USB_DATA_ROLE;
-	}
+		if (ufp_tbt_enter_mode.tbt_cable == TBT_CABLE_OPTICAL)
+			*set_retimer_con |= BB_RETIMER_TBT_CABLE_TYPE;
 
-	 /*
-	  * Bit 17: TBT_TYPE
-	  * 0 - Type-C to Type-C Cable
-	  * 1 - Type-C Legacy TBT Adapter
-	  * For UFP, TBT_TYPE = 0
-	  */
+		/*
+		 * Bit 19: VPO_DOCK_DETECTED_OR_DP_OVERDRIVE
+		 * 0 - No vPro Dock.No DP Overdrive
+		 *     detected
+		 * 1 - vPro Dock or DP Overdrive
+		 *     detected
+		 *
+		 * Set according to TBT3 Enter Mode bit 26 or bit 31
+		 */
+		if ((IS_ENABLED(CONFIG_USBC_RETIMER_INTEL_BB_VPRO_CAPABLE) &&
+		     ufp_tbt_enter_mode.intel_spec_b0 ==
+			     VENDOR_SPECIFIC_SUPPORTED) ||
+		    ufp_tbt_enter_mode.vendor_spec_b1 ==
+			    VENDOR_SPECIFIC_SUPPORTED)
+			*set_retimer_con |= BB_RETIMER_VPRO_DOCK_DP_OVERDRIVE;
 
-	/*
-	 * TODO: b/157163664: Add the following bits:
-	 *
-	 * Bit 2: RE_TIMER_DRIVER:
-	 * Set according to b20:19 of enter USB.
-	 *
-	 * Bit 18: CABLE_TYPE:
-	 * For Thunderbolt-compat mode, set according to bit 21 of enter mode.
-	 * For USB/DP/USB4, set according to bits 20:19 of enter mode.
-	 *
-	 * Bit 20: TBT_ACTIVE_LINK_TRAINING:
-	 * For Thunderbolt-compat mode, set according to bit 23 of enter mode.
-	 * For USB, set to 0.
-	 *
-	 * Bit 22: ACTIVE/PASSIVE
-	 * For USB4, set according to bits 20:19 of enter USB SOP.
-	 * For thubderbolt-compat mode, set according to bit 24 of enter mode.
-	 *
-	 * Bits 29-28: TBT_GEN_SUPPORT
-	 * For Thunderbolt-compat mode, set according to bits 20:19 of enter
-	 * mode.
-	 */
+		/*
+		 * Bit 20: TBT_ACTIVE_LINK_TRAINING
+		 * 0 - Active with bi-directional LSRX communication
+		 * 1 - Active with uni-directional LSRX communication
+		 *
+		 * Set according to TBT3 Enter Mode bit 23
+		 */
+		if (ufp_tbt_enter_mode.lsrx_comm == UNIDIR_LSRX_COMM)
+			*set_retimer_con |= BB_RETIMER_TBT_ACTIVE_LINK_TRAINING;
+
+		/*
+		 * Bit 22: ACTIVE/PASSIVE
+		 * 0 - Passive cable
+		 * 1 - Active cable
+		 *
+		 * Set according to TBT3 Enter Mode bit 24
+		 */
+		if (ufp_tbt_enter_mode.cable == TBT_ENTER_ACTIVE_CABLE)
+			*set_retimer_con |= BB_RETIMER_ACTIVE_PASSIVE;
+
+		/*
+		 * Bit 27-25: TBT Cable speed
+		 * 000b - No functionality
+		 * 001b - USB3.1 Gen1 Cable
+		 * 010b - 10Gb/s
+		 * 011b - 10Gb/s and 20Gb/s
+		 * 10..11b - Reserved
+		 *
+		 * Set according to TBT3 Enter Mode bit 18:16
+		 */
+		*set_retimer_con |= BB_RETIMER_USB4_TBT_CABLE_SPEED_SUPPORT(
+			ufp_tbt_enter_mode.tbt_cable_speed);
+		/*
+		 * Bits 29-28: TBT_GEN_SUPPORT
+		 * 00b - 3rd generation TBT (10.3125 and 20.625Gb/s)
+		 * 01b - 4th generation TBT (10.00005Gb/s, 10.3125Gb/s,
+		 *                           20.0625Gb/s, 20.000Gb/s)
+		 * 10..11b - Reserved
+		 *
+		 * Set according to TBT3 Enter Mode bit 20:19
+		 */
+		*set_retimer_con |= BB_RETIMER_TBT_CABLE_GENERATION(
+			ufp_tbt_enter_mode.tbt_rounded);
+	}
 }
 
 /**
  * Driver interface functions
  */
-static int retimer_set_state(const struct usb_mux *me, mux_state_t mux_state)
+static int retimer_set_state(const struct usb_mux *me, mux_state_t mux_state,
+			     bool *ack_required)
 {
 	uint32_t set_retimer_con = 0;
 	uint8_t dp_pin_mode;
 	int port = me->usb_port;
-	/*
-	 * TODO(b/161327513): Remove this once we have final fix for
-	 * the Type-C MFD degradation issue.
-	 * In alternate mode, mux changes states as USB->Safe->DP Alt Mode.
-	 * As EC programs retimer into safe mode independent of virtual mux,
-	 * the super speed lanes are terminated while IOM is in the process
-	 * of establishing the super speed link, which causes a fallback to
-	 * USB 2.0 enumeration through PCH. By removing the Safe mode in retimer
-	 * Super Speed lanes are available to virtual mux and would not
-	 * interrupt the enumeration process and then entering safe.
-	 * From the protocol analyser traces the safe mode is still achieved
-	 * with virtual mux Safe mode settings.
-	 */
-	if (mux_state & USB_PD_MUX_SAFE_MODE)
-		return 0;
+	int rv = 0;
+
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
+	mutex_lock(&bb_retimer_lock[port]);
+	bb_mux_state[port] = mux_state;
+
 	/*
 	 * Bit 0: DATA_CONNECTION_PRESENT
 	 * 0 - No connection present
@@ -372,6 +442,8 @@ static int retimer_set_state(const struct usb_mux *me, mux_state_t mux_state)
 	 * Bit 8: DP_CONNECTION
 	 * 0 – No DP connection
 	 * 1 – DP connected
+	 *
+	 * TODO: Refactor if CONFIG_USB_PD_VDM_AP_CONTROL is supported
 	 */
 	if (mux_state & USB_PD_MUX_DP_ENABLED) {
 		set_retimer_con |= BB_RETIMER_DP_CONNECTION;
@@ -384,7 +456,7 @@ static int retimer_set_state(const struct usb_mux *me, mux_state_t mux_state)
 		 */
 		dp_pin_mode = get_dp_pin_mode(port);
 		if (dp_pin_mode == MODE_DP_PIN_C ||
-			dp_pin_mode == MODE_DP_PIN_D)
+		    dp_pin_mode == MODE_DP_PIN_D)
 			set_retimer_con |= BB_RETIMER_DP_PIN_ASSIGNMENT;
 
 		/*
@@ -423,45 +495,181 @@ static int retimer_set_state(const struct usb_mux *me, mux_state_t mux_state)
 	if (pd_get_data_role(port) == PD_ROLE_DFP)
 		retimer_set_state_dfp(port, mux_state, &set_retimer_con);
 	else
-		retimer_set_state_ufp(mux_state, &set_retimer_con);
+		retimer_set_state_ufp(port, mux_state, &set_retimer_con);
+
+	/* Writing the register4 */
+	rv = bb_retimer_write(me, BB_RETIMER_REG_CONNECTION_STATE,
+			      set_retimer_con);
+	mutex_unlock(&bb_retimer_lock[port]);
+	return rv;
+}
+
+static int bb_set_idle_mode(const struct usb_mux *me, bool idle)
+{
+	bool usb3_enable;
+	int rv;
+	uint32_t reg_val;
+	int port = me->usb_port;
+
+	mutex_lock(&bb_retimer_lock[port]);
+
+	if (!(bb_mux_state[port] & USB_PD_MUX_USB_ENABLED)) {
+		mutex_unlock(&bb_retimer_lock[port]);
+		return EC_SUCCESS;
+	}
+
+	rv = bb_retimer_read(me, BB_RETIMER_REG_CONNECTION_STATE, &reg_val);
+	if (rv != EC_SUCCESS) {
+		mutex_unlock(&bb_retimer_lock[port]);
+		return rv;
+	}
+
+	usb3_enable = !idle;
+
+	/* Bit 5: BB_RETIMER_USB_3_CONNECTION */
+	WRITE_BIT(reg_val, 5, usb3_enable);
+	rv = bb_retimer_write(me, BB_RETIMER_REG_CONNECTION_STATE, reg_val);
+
+	mutex_unlock(&bb_retimer_lock[port]);
+
+	return rv;
+}
+
+int bb_retimer_set_dp_connection(const struct usb_mux *me, bool enable)
+{
+	int rv;
+	uint32_t reg_val;
+	int port = me->usb_port;
+
+	mutex_lock(&bb_retimer_lock[port]);
+
+	rv = bb_retimer_read(me, BB_RETIMER_REG_CONNECTION_STATE, &reg_val);
+	if (rv != EC_SUCCESS) {
+		mutex_unlock(&bb_retimer_lock[port]);
+		return rv;
+	}
+	/* Bit 8: BB_RETIMER_DP_CONNECTION */
+	WRITE_BIT(reg_val, 8, enable);
+	rv = bb_retimer_write(me, BB_RETIMER_REG_CONNECTION_STATE, reg_val);
+
+	mutex_unlock(&bb_retimer_lock[port]);
+
+	return rv;
+}
+
+void bb_retimer_hpd_update(const struct usb_mux *me, mux_state_t hpd_state,
+			   bool *ack_required)
+{
+	uint32_t retimer_con_reg = 0;
+	int port = me->usb_port;
+
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
+	mutex_lock(&bb_retimer_lock[port]);
+	bb_mux_state[port] = (bb_mux_state[port] & ~MUX_STATE_HPD_UPDATE_MASK) |
+			     (hpd_state & MUX_STATE_HPD_UPDATE_MASK);
+
+	if (bb_retimer_read(me, BB_RETIMER_REG_CONNECTION_STATE,
+			    &retimer_con_reg) != EC_SUCCESS) {
+		mutex_unlock(&bb_retimer_lock[port]);
+		return;
+	}
+	/*
+	 * Bit 14: IRQ_HPD (ignored if BIT8 = 0)
+	 * 0 - No IRQ_HPD
+	 * 1 - IRQ_HPD received
+	 */
+	if (hpd_state & USB_PD_MUX_HPD_IRQ)
+		retimer_con_reg |= BB_RETIMER_IRQ_HPD;
+	else
+		retimer_con_reg &= ~BB_RETIMER_IRQ_HPD;
+
+	/*
+	 * Bit 15: HPD_LVL (ignored if BIT8 = 0)
+	 * 0 - HPD_State Low
+	 * 1 - HPD_State High
+	 */
+
+	if (hpd_state & USB_PD_MUX_HPD_LVL)
+		retimer_con_reg |= BB_RETIMER_HPD_LVL;
+	else
+		retimer_con_reg &= ~BB_RETIMER_HPD_LVL;
 
 	/* Writing the register4 */
-	return bb_retimer_write(me, BB_RETIMER_REG_CONNECTION_STATE,
-			set_retimer_con);
+	bb_retimer_write(me, BB_RETIMER_REG_CONNECTION_STATE, retimer_con_reg);
+
+	mutex_unlock(&bb_retimer_lock[port]);
 }
 
+#ifdef CONFIG_ZEPHYR
+static void init_retimer_mutexes(void)
+{
+	int port;
+
+	for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++) {
+		k_mutex_init(&bb_retimer_lock[port]);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, init_retimer_mutexes, HOOK_PRIO_FIRST);
+#endif
+
 static int retimer_low_power_mode(const struct usb_mux *me)
 {
-	bb_retimer_power_handle(me, 0);
-	return EC_SUCCESS;
+	const int port = me->usb_port;
+
+	bb_mux_state[port] = USB_PD_MUX_NONE;
+	return bb_retimer_power_enable(me, false);
+}
+
+static bool is_retimer_fw_update_capable(void)
+{
+	return true;
 }
 
 static int retimer_init(const struct usb_mux *me)
 {
 	int rv;
 	uint32_t data;
+	const int port = me->usb_port;
+
+	bb_mux_state[port] = USB_PD_MUX_NONE;
 
 	/* Burnside Bridge is powered by main AP rail */
 	if (chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF)) {
 		/* Ensure reset is asserted while chip is not powered */
-		bb_retimer_power_handle(me, 0);
+		bb_retimer_power_enable(me, false);
 		return EC_ERROR_NOT_POWERED;
 	}
 
-	bb_retimer_power_handle(me, 1);
+	rv = bb_retimer_power_enable(me, true);
+	if (rv != EC_SUCCESS)
+		return rv;
 
 	rv = bb_retimer_read(me, BB_RETIMER_REG_VENDOR_ID, &data);
-	if (rv)
+	/*
+	 * After reset, i2c controller may not be ready, if this fails,
+	 * retry one more time.
+	 * TODO: revisit the delay time after retimer reset.
+	 */
+	if (rv != EC_SUCCESS)
+		rv = bb_retimer_read(me, BB_RETIMER_REG_VENDOR_ID, &data);
+	if (rv != EC_SUCCESS)
 		return rv;
-	if (data != BB_RETIMER_VENDOR_ID)
-		return EC_ERROR_UNKNOWN;
+	CPRINTS("C%d: retimer power enable success", me->usb_port);
+#ifdef CONFIG_USBC_RETIMER_INTEL_HB
+	if (data != BB_RETIMER_DEVICE_ID)
+		return EC_ERROR_INVAL;
+#else
+	if ((data != BB_RETIMER_VENDOR_ID_1) && data != BB_RETIMER_VENDOR_ID_2)
+		return EC_ERROR_INVAL;
 
 	rv = bb_retimer_read(me, BB_RETIMER_REG_DEVICE_ID, &data);
-	if (rv)
+	if (rv != EC_SUCCESS)
 		return rv;
-
 	if (data != BB_RETIMER_DEVICE_ID)
-		return EC_ERROR_UNKNOWN;
+		return EC_ERROR_INVAL;
+#endif
 
 	return EC_SUCCESS;
 }
@@ -469,66 +677,11 @@ static int retimer_init(const struct usb_mux *me)
 const struct usb_mux_driver bb_usb_retimer = {
 	.init = retimer_init,
 	.set = retimer_set_state,
+	.set_idle_mode = bb_set_idle_mode,
 	.enter_low_power_mode = retimer_low_power_mode,
-};
-
+	.is_retimer_fw_update_capable = is_retimer_fw_update_capable,
 #ifdef CONFIG_CMD_RETIMER
-static int console_command_bb_retimer(int argc, char **argv)
-{
-	char rw, *e;
-	int rv, port, reg, data, val;
-	const struct usb_mux *mux;
-
-	if (argc < 4)
-		return EC_ERROR_PARAM_COUNT;
-
-	/* Get port number */
-	port = strtoi(argv[1], &e, 0);
-	if (*e || port < 0 || port > board_get_usb_pd_port_count())
-		return EC_ERROR_PARAM1;
-
-	mux = &usb_muxes[port];
-	while (mux) {
-		if (mux->driver == &bb_usb_retimer)
-			break;
-		mux = mux->next_mux;
-	}
-
-	if (!mux)
-		return EC_ERROR_PARAM1;
-
-	/* Validate r/w selection */
-	rw = argv[2][0];
-	if (rw != 'w' && rw != 'r')
-		return EC_ERROR_PARAM2;
-
-	/* Get register address */
-	reg = strtoi(argv[3], &e, 0);
-	if (*e || reg < 0)
-		return EC_ERROR_PARAM3;
-
-	if (rw == 'r')
-		rv = bb_retimer_read(mux, reg, &data);
-	else {
-		/* Get value to be written */
-		val = strtoi(argv[4], &e, 0);
-		if (*e || val < 0)
-			return EC_ERROR_PARAM4;
-
-		rv = bb_retimer_write(mux, reg, val);
-		if (rv == EC_SUCCESS) {
-			rv = bb_retimer_read(mux, reg, &data);
-			if (rv == EC_SUCCESS && data != val)
-				rv = EC_ERROR_UNKNOWN;
-		}
-	}
-
-	if (rv == EC_SUCCESS)
-		CPRINTS("register 0x%x [%d] = 0x%x [%d]", reg, reg, data, data);
-
-	return rv;
-}
-DECLARE_CONSOLE_COMMAND(bb, console_command_bb_retimer,
-			"<port> <r/w> <reg> | <val>",
-			"Read or write to BB retimer register");
+	.retimer_read = bb_retimer_read,
+	.retimer_write = bb_retimer_write,
 #endif /* CONFIG_CMD_RETIMER */
+};
diff --git a/driver/retimer/bb_retimer.h b/driver/retimer/bb_retimer.h
deleted file mode 100644
index 26ad560aaf..0000000000
--- a/driver/retimer/bb_retimer.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Driver header for Intel Burnside Bridge - Thunderbolt/USB/DisplayPort Retimer
- */
-
-#ifndef __CROS_EC_BB_RETIMER_H
-#define __CROS_EC_BB_RETIMER_H
-
-#include "gpio.h"
-#include "usb_mux.h"
-
-/* Burnside Bridge I2C Configuration Space */
-#define BB_RETIMER_REG_VENDOR_ID	0
-#define BB_RETIMER_VENDOR_ID		0x8086
-
-#define BB_RETIMER_REG_DEVICE_ID	1
-#define BB_RETIMER_DEVICE_ID		0x15EE
-
-/* Connection State Register Attributes */
-#define BB_RETIMER_REG_CONNECTION_STATE		4
-#define BB_RETIMER_DATA_CONNECTION_PRESENT	BIT(0)
-#define BB_RETIMER_CONNECTION_ORIENTATION	BIT(1)
-#define BB_RETIMER_RE_TIMER_DRIVER		BIT(2)
-#define BB_RETIMER_USB_2_CONNECTION		BIT(4)
-#define BB_RETIMER_USB_3_CONNECTION		BIT(5)
-#define BB_RETIMER_USB_3_SPEED			BIT(6)
-#define BB_RETIMER_USB_DATA_ROLE		BIT(7)
-#define BB_RETIMER_DP_CONNECTION		BIT(8)
-#define BB_RETIMER_DP_PIN_ASSIGNMENT		BIT(10)
-#define BB_RETIMER_IRQ_HPD			BIT(14)
-#define BB_RETIMER_HPD_LVL			BIT(15)
-#define BB_RETIMER_TBT_CONNECTION		BIT(16)
-#define BB_RETIMER_TBT_TYPE			BIT(17)
-#define BB_RETIMER_TBT_CABLE_TYPE		BIT(18)
-#define BB_RETIMER_VPRO_DOCK_DP_OVERDRIVE	BIT(19)
-#define BB_RETIMER_TBT_ACTIVE_LINK_TRAINING	BIT(20)
-#define BB_RETIMER_ACTIVE_PASSIVE		BIT(22)
-#define BB_RETIMER_USB4_ENABLED			BIT(23)
-#define BB_RETIMER_USB4_TBT_CABLE_SPEED_SUPPORT(x)	(((x) & 0x7) << 25)
-#define BB_RETIMER_TBT_CABLE_GENERATION(x)		(((x) & 0x3) << 28)
-
-/* Supported USB retimer drivers */
-extern const struct usb_mux_driver bb_usb_retimer;
-
-/* Retimer driver hardware specific controls */
-struct bb_usb_control {
-	/* Load switch enable */
-	enum gpio_signal usb_ls_en_gpio;
-	/* Retimer reset */
-	enum gpio_signal retimer_rst_gpio;
-};
-
-#ifndef CONFIG_USBC_RETIMER_INTEL_BB_RUNTIME_CONFIG
-extern const struct bb_usb_control bb_controls[];
-#else
-extern struct bb_usb_control bb_controls[];
-#endif
-
-/**
- * Handle the power state of BB retimer
- *
- * Define override function at board level if the platform specific changes
- * are needed to handle the power state of BB retimer.
- *
- * @param me     Pointer to USB mux
- * @param on_off BB retimer state to be changed
- *
- */
-__override_proto void bb_retimer_power_handle(const struct usb_mux *me,
-						int on_off);
-
-#endif /* __CROS_EC_BB_RETIMER_H */
diff --git a/driver/retimer/kb800x.c b/driver/retimer/kb800x.c
new file mode 100644
index 0000000000..2ca4b062bb
--- /dev/null
+++ b/driver/retimer/kb800x.c
@@ -0,0 +1,497 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Driver for Kandou KB800x USB-C 40 Gb/s multiprotocol switch.
+ */
+
+#include "common.h"
+#include "console.h"
+#include "gpio.h"
+#include "i2c.h"
+#include "kb800x.h"
+#include "time.h"
+
+/* Time between load switch enable and the reset being de-asserted */
+#define KB800X_POWER_ON_DELAY_MS 20
+#define KB800X_REG_OFFSET_MAX UINT16_MAX
+#define KB800X_REG_DATA_MAX UINT8_MAX
+
+static mux_state_t cached_mux_state[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+static int kb800x_write(const struct usb_mux *me, uint32_t address,
+			uint32_t data)
+{
+	uint8_t kb800x_config[3] = { 0x00, 0x00, 0x00 };
+
+	/* Validate the register address */
+	if (address > KB800X_REG_OFFSET_MAX)
+		return EC_ERROR_INVAL;
+
+	/* Validate the writeable data */
+	if (data > KB800X_REG_DATA_MAX)
+		return EC_ERROR_INVAL;
+
+	kb800x_config[0] = (address >> 8) & 0xff;
+	kb800x_config[1] = address & 0xff;
+	kb800x_config[2] = (uint8_t)data;
+	return i2c_xfer(me->i2c_port, me->i2c_addr_flags, kb800x_config,
+			sizeof(kb800x_config), NULL, 0);
+}
+
+static int kb800x_read(const struct usb_mux *me, uint32_t address,
+		       uint32_t *data)
+{
+	uint8_t kb800x_config[2] = { 0x00, 0x00 };
+
+	/* Validate the register address */
+	if (address > KB800X_REG_OFFSET_MAX)
+		return EC_ERROR_INVAL;
+
+	kb800x_config[0] = (address >> 8) & 0xff;
+	kb800x_config[1] = address & 0xff;
+	return i2c_xfer(me->i2c_port, me->i2c_addr_flags, kb800x_config,
+			sizeof(kb800x_config), (uint8_t *)data, 1);
+}
+
+#ifdef CONFIG_KB800X_CUSTOM_XBAR
+
+/* These lookup tables are derived from the KB8001 EVB GUI register map */
+
+/* Map elastic buffer (EB) to register field for TX configuration. */
+static const uint8_t tx_eb_to_field_ab[] = {
+	[KB800X_EB1] = 4, [KB800X_EB2] = 0, [KB800X_EB3] = 0,
+	[KB800X_EB4] = 1, [KB800X_EB5] = 2, [KB800X_EB6] = 3
+};
+static const uint8_t tx_eb_to_field_cd[] = {
+	[KB800X_EB1] = 1, [KB800X_EB2] = 2, [KB800X_EB3] = 3,
+	[KB800X_EB4] = 4, [KB800X_EB5] = 0, [KB800X_EB6] = 0
+};
+/* Map phy lane to register field for RX configuration */
+static const uint8_t rx_phy_lane_to_field[] = {
+	[KB800X_A0] = 1, [KB800X_A1] = 2, [KB800X_B0] = 5, [KB800X_B1] = 6,
+	[KB800X_C0] = 1, [KB800X_C1] = 2, [KB800X_D0] = 5, [KB800X_D1] = 6
+};
+/* Map EB to address for RX configuration */
+static const uint16_t rx_eb_to_address[] = {
+	[KB800X_EB1] = KB800X_REG_XBAR_EB1SEL,
+	[KB800X_EB2] = KB800X_REG_XBAR_EB23SEL,
+	[KB800X_EB3] = KB800X_REG_XBAR_EB23SEL,
+	[KB800X_EB4] = KB800X_REG_XBAR_EB4SEL,
+	[KB800X_EB5] = KB800X_REG_XBAR_EB56SEL,
+	[KB800X_EB6] = KB800X_REG_XBAR_EB56SEL
+};
+/* Map SS lane to EB for DP or USB/CIO protocols */
+static const uint8_t dp_ss_lane_to_eb[] = { [KB800X_TX0] = KB800X_EB4,
+					    [KB800X_TX1] = KB800X_EB5,
+					    [KB800X_RX0] = KB800X_EB6,
+					    [KB800X_RX1] = KB800X_EB1 };
+static const uint8_t usb_ss_lane_to_eb[] = { [KB800X_TX0] = KB800X_EB4,
+					     [KB800X_TX1] = KB800X_EB5,
+					     [KB800X_RX0] = KB800X_EB1,
+					     [KB800X_RX1] = KB800X_EB2 };
+
+/* Assign a phy TX to an elastic buffer */
+static int kb800x_assign_tx_to_eb(const struct usb_mux *me,
+				  enum kb800x_phy_lane phy_lane,
+				  enum kb800x_eb eb)
+{
+	uint8_t field_value = 0;
+	uint32_t regval;
+	int rv;
+
+	field_value = KB800X_PHY_IS_AB(phy_lane) ? tx_eb_to_field_ab[eb] :
+						   tx_eb_to_field_cd[eb];
+
+	/* For lane1 of each PHY, shift by 3 bits */
+	field_value <<= 3 * KB800X_LANE_NUMBER_FROM_PHY(phy_lane);
+
+	rv = kb800x_read(me, KB800X_REG_TXSEL_FROM_PHY(phy_lane), &regval);
+	if (rv)
+		return rv;
+	return kb800x_write(me, KB800X_REG_TXSEL_FROM_PHY(phy_lane),
+			    regval | field_value);
+}
+
+/* Assign a phy RX to an elastic buffer */
+static int kb800x_assign_rx_to_eb(const struct usb_mux *me,
+				  enum kb800x_phy_lane phy_lane,
+				  enum kb800x_eb eb)
+{
+	uint16_t address = 0;
+	uint8_t field_value = 0;
+	uint32_t regval = 0;
+	int rv;
+
+	field_value = rx_phy_lane_to_field[phy_lane];
+	address = rx_eb_to_address[eb];
+
+	/*
+	 * need to shift by 4 for reverse EB or 3rd EB in set based on the
+	 * register definition from the KB8001 EVB register map
+	 */
+	switch (eb) {
+	case KB800X_EB1:
+		if (!KB800X_PHY_IS_AB(phy_lane))
+			field_value <<= 4;
+		break;
+	case KB800X_EB4:
+		if (KB800X_PHY_IS_AB(phy_lane))
+			field_value <<= 4;
+		break;
+	case KB800X_EB3:
+	case KB800X_EB6:
+		field_value <<= 4;
+		break;
+	default:
+		break;
+	}
+
+	rv = kb800x_read(me, address, &regval);
+	if (rv)
+		return rv;
+	return kb800x_write(me, address, regval | field_value);
+}
+
+static bool kb800x_in_dpmf(const struct usb_mux *me)
+{
+	if ((cached_mux_state[me->usb_port] & USB_PD_MUX_DP_ENABLED) &&
+	    (cached_mux_state[me->usb_port] & USB_PD_MUX_USB_ENABLED))
+		return true;
+	else
+		return false;
+}
+
+static bool kb800x_is_dp_lane(const struct usb_mux *me,
+			      enum kb800x_ss_lane ss_lane)
+{
+	if (cached_mux_state[me->usb_port] & USB_PD_MUX_DP_ENABLED) {
+		/* DP ALT mode */
+		if (kb800x_in_dpmf(me)) {
+			/* DPMF pin configuration */
+			if ((ss_lane == KB800X_TX1) ||
+			    (ss_lane == KB800X_RX1)) {
+				return true; /* ML0 or ML1 */
+			}
+		} else {
+			/* Pure, 4-lane DP mode */
+			return true;
+		}
+	}
+	/* Not a DP mode or ML2/3 while in DPMF */
+	return false;
+}
+
+/* Assigning this PHY to this SS lane means it should be RX */
+static bool kb800x_phy_ss_lane_is_rx(enum kb800x_phy_lane phy_lane,
+				     enum kb800x_ss_lane ss_lane)
+{
+	bool rx;
+
+	switch (ss_lane) {
+	case KB800X_TX0:
+	case KB800X_TX1:
+		rx = false;
+		break;
+	case KB800X_RX0:
+	case KB800X_RX1:
+		rx = true;
+		break;
+	}
+	/* invert for C/D (host side), since it is receiving the TX signal*/
+	if (!KB800X_PHY_IS_AB(phy_lane))
+		return !rx;
+	return rx;
+}
+
+/* Assign SS lane to PHY. Assumes A/B is connector-side, and C/D is host-side */
+static int kb800x_assign_lane(const struct usb_mux *me,
+			      enum kb800x_phy_lane phy_lane,
+			      enum kb800x_ss_lane ss_lane)
+{
+	enum kb800x_eb eb = 0;
+
+	/*
+	 * Easiest way to handle flipping is to just swap lane 1/0. This assumes
+	 * lanes are flipped in the AP. If they are not, they shouldn't be
+	 * flipped for the AP-side lanes, but should for connector-side
+	 */
+	if (cached_mux_state[me->usb_port] & USB_PD_MUX_POLARITY_INVERTED)
+		ss_lane = KB800X_FLIP_SS_LANE(ss_lane);
+
+	if (kb800x_is_dp_lane(me, ss_lane)) {
+		if (kb800x_in_dpmf(me)) {
+			/* Route USB3 RX/TX to EB1/4, and ML0/1 to EB5/6 */
+			switch (ss_lane) {
+			case KB800X_TX1: /* ML1 */
+				eb = KB800X_EB6;
+				break;
+			case KB800X_RX1: /* ML0 */
+				eb = KB800X_EB5;
+				break;
+			default:
+				break;
+			}
+		} else {
+			/* Route ML0/1/2/3 through EB1/5/4/6 */
+			eb = dp_ss_lane_to_eb[ss_lane];
+		}
+
+		/* For DP lanes, always DFP so A/B is TX, C/D is RX */
+		if (KB800X_PHY_IS_AB(phy_lane))
+			return kb800x_assign_tx_to_eb(me, phy_lane, eb);
+		else
+			return kb800x_assign_rx_to_eb(me, phy_lane, eb);
+	}
+
+	/* Lane is either USB3 or CIO */
+	if (kb800x_phy_ss_lane_is_rx(phy_lane, ss_lane))
+		return kb800x_assign_rx_to_eb(me, phy_lane,
+					      usb_ss_lane_to_eb[ss_lane]);
+	else
+		return kb800x_assign_tx_to_eb(me, phy_lane,
+					      usb_ss_lane_to_eb[ss_lane]);
+}
+
+static int kb800x_xbar_override(const struct usb_mux *me)
+{
+	int rv;
+	int i;
+
+	for (i = KB800X_A0; i < KB800X_PHY_LANE_COUNT; ++i) {
+		rv = kb800x_assign_lane(
+			me, i, kb800x_control[me->usb_port].ss_lanes[i]);
+		if (rv)
+			return rv;
+	}
+	return kb800x_write(me, KB800X_REG_XBAR_OVR, KB800X_XBAR_OVR_EN);
+}
+#endif /* CONFIG_KB800X_CUSTOM_XBAR */
+
+/*
+ * The initialization writes for each protocol can be found in the KB8001/KB8002
+ * Programming Guidelines
+ */
+static const uint16_t global_init_addresses[] = {
+	0x5058, 0x5059, 0xFF63, 0xF021, 0xF022, 0xF057, 0xF058,
+	0x8194, 0xF0C9, 0xF0CA, 0xF0CB, 0xF0CC, 0xF0CD, 0xF0CE,
+	0xF0DF, 0xF0E0, 0xF0E1, 0x8198, 0x8191
+};
+static const uint8_t global_init_values[] = { 0x12, 0x12, 0x3C, 0x02, 0x02,
+					      0x02, 0x02, 0x37, 0x0C, 0x0B,
+					      0x0A, 0x09, 0x08, 0x07, 0x57,
+					      0x66, 0x66, 0x33, 0x00 };
+static const uint16_t usb3_init_addresses[] = { 0xF020, 0xF056 };
+static const uint8_t usb3_init_values[] = { 0x2f, 0x2f };
+static const uint16_t dp_init_addresses[] = { 0xF2CB, 0x0011 };
+static const uint8_t dp_init_values[] = { 0x30, 0x00 };
+/*
+ * The first 2 CIO writes apply an SBRX pullup to the host side (C/D)
+ * This is required when the CPU doesn't apply a pullup.
+ */
+static const uint16_t cio_init_addresses[] = { 0x81fd, 0x81fe, 0xF26B, 0xF26E };
+static const uint8_t cio_init_values[] = { 0x08, 0x80, 0x01, 0x19 };
+
+static int kb800x_bulk_write(const struct usb_mux *me,
+			     const uint16_t *addresses, const uint8_t *values,
+			     const uint8_t size)
+{
+	int i;
+	int rv;
+
+	for (i = 0; i < size; ++i) {
+		rv = kb800x_write(me, addresses[i], values[i]);
+		if (rv != EC_SUCCESS)
+			return rv;
+	}
+
+	return EC_SUCCESS;
+}
+
+static int kb800x_global_init(const struct usb_mux *me)
+{
+	return kb800x_bulk_write(me, global_init_addresses, global_init_values,
+				 sizeof(global_init_values));
+}
+
+static int kb800x_dp_init(const struct usb_mux *me, mux_state_t mux_state)
+{
+	int rv;
+
+	rv = kb800x_bulk_write(me, dp_init_addresses, dp_init_values,
+			       sizeof(dp_init_values));
+	if (rv)
+		return rv;
+	return kb800x_write(
+		me, KB800X_REG_ORIENTATION,
+		KB800X_ORIENTATION_DP_DFP |
+			((mux_state & USB_PD_MUX_POLARITY_INVERTED) ?
+				 KB800X_ORIENTATION_POLARITY :
+				 0x0));
+}
+
+static int kb800x_usb3_init(const struct usb_mux *me, mux_state_t mux_state)
+{
+	int rv;
+
+	rv = kb800x_bulk_write(me, usb3_init_addresses, usb3_init_values,
+			       sizeof(usb3_init_values));
+	if (rv)
+		return rv;
+	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
+		/* This will be overwritten in the DPMF case */
+		return kb800x_write(me, KB800X_REG_ORIENTATION,
+				    KB800X_ORIENTATION_POLARITY);
+	return EC_SUCCESS;
+}
+
+static int kb800x_cio_init(const struct usb_mux *me, mux_state_t mux_state)
+{
+	uint8_t orientation = 0x0;
+	int rv;
+
+	enum idh_ptype cable_type = get_usb_pd_cable_type(me->usb_port);
+	union tbt_mode_resp_cable cable_resp = {
+		.raw_value =
+			pd_get_tbt_mode_vdo(me->usb_port, TCPCI_MSG_SOP_PRIME)
+	};
+
+	rv = kb800x_bulk_write(me, cio_init_addresses, cio_init_values,
+			       sizeof(cio_init_values));
+	if (rv)
+		return rv;
+
+	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
+		orientation = KB800X_ORIENTATION_CIO_LANE_SWAP |
+			      KB800X_ORIENTATION_POLARITY;
+
+	if (!(mux_state & USB_PD_MUX_USB4_ENABLED)) {
+		/* Special configuration only for legacy mode */
+		if (cable_type == IDH_PTYPE_ACABLE ||
+		    cable_resp.tbt_active_passive == TBT_CABLE_ACTIVE) {
+			/* Active cable */
+			if (cable_resp.lsrx_comm == UNIDIR_LSRX_COMM) {
+				orientation |=
+					KB800X_ORIENTATION_CIO_LEGACY_UNIDIR;
+			} else {
+				/* 'Pre-Coding on a TBT3-Compatible Link' ECN */
+				rv = kb800x_write(me, 0x8194, 0x31);
+				if (rv)
+					return rv;
+				orientation |=
+					KB800X_ORIENTATION_CIO_LEGACY_BIDIR;
+			}
+		} else {
+			/* Passive Cable */
+			orientation |= KB800X_ORIENTATION_CIO_LEGACY_PASSIVE;
+		}
+	}
+	return kb800x_write(me, KB800X_REG_ORIENTATION, orientation);
+}
+
+static int kb800x_set_state(const struct usb_mux *me, mux_state_t mux_state,
+			    bool *ack_required)
+{
+	int rv;
+
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
+	cached_mux_state[me->usb_port] = mux_state;
+	rv = kb800x_write(me, KB800X_REG_RESET, KB800X_RESET_MASK);
+	if (rv)
+		return rv;
+	/* Release memory map reset */
+	rv = kb800x_write(me, KB800X_REG_RESET,
+			  KB800X_RESET_MASK & ~KB800X_RESET_MM);
+	if (rv)
+		return rv;
+
+	/* Already in reset, nothing to do */
+	if ((mux_state == USB_PD_MUX_NONE) ||
+	    (mux_state & USB_PD_MUX_SAFE_MODE))
+		return EC_SUCCESS;
+
+	rv = kb800x_global_init(me);
+	if (rv)
+		return rv;
+
+	/* CIO mode (USB4/TBT) */
+	if (mux_state &
+	    (USB_PD_MUX_USB4_ENABLED | USB_PD_MUX_TBT_COMPAT_ENABLED)) {
+		rv = kb800x_cio_init(me, mux_state);
+		if (rv)
+			return rv;
+		rv = kb800x_write(me, KB800X_REG_PROTOCOL, KB800X_PROTOCOL_CIO);
+	} else {
+		/* USB3 enabled (USB3-only or DPMF) */
+		if (mux_state & USB_PD_MUX_USB_ENABLED) {
+			rv = kb800x_usb3_init(me, mux_state);
+			if (rv)
+				return rv;
+			/* USB3-only is the default KB800X_REG_PROTOCOL value */
+		}
+
+		/* DP alt modes (DP-only or DPMF) */
+		if (mux_state & USB_PD_MUX_DP_ENABLED) {
+			rv = kb800x_dp_init(me, mux_state);
+			if (rv)
+				return rv;
+			if (mux_state & USB_PD_MUX_USB_ENABLED)
+				rv = kb800x_write(me, KB800X_REG_PROTOCOL,
+						  KB800X_PROTOCOL_DPMF);
+			else
+				rv = kb800x_write(me, KB800X_REG_PROTOCOL,
+						  KB800X_PROTOCOL_DP);
+		}
+	}
+	if (rv)
+		return rv;
+
+#ifdef CONFIG_KB800X_CUSTOM_XBAR
+	rv = kb800x_xbar_override(me);
+	if (rv)
+		return rv;
+#endif /* CONFIG_KB800X_CUSTOM_XBAR */
+
+	return kb800x_write(me, KB800X_REG_RESET, 0x00);
+}
+
+static int kb800x_init(const struct usb_mux *me)
+{
+	bool unused;
+
+	gpio_set_level(kb800x_control[me->usb_port].usb_ls_en_gpio, 1);
+	gpio_set_level(kb800x_control[me->usb_port].retimer_rst_gpio, 1);
+
+	/*
+	 * Delay after enabling power and releasing the reset to allow the power
+	 * to come up and the reset to be released by the power sequencing
+	 * logic. If after the delay, the reset is still held low - return an
+	 * error.
+	 */
+	msleep(KB800X_POWER_ON_DELAY_MS);
+	if (!gpio_get_level(kb800x_control[me->usb_port].retimer_rst_gpio))
+		return EC_ERROR_NOT_POWERED;
+
+	return kb800x_set_state(me, USB_PD_MUX_NONE, &unused);
+}
+
+static int kb800x_enter_low_power_mode(const struct usb_mux *me)
+{
+	gpio_set_level(kb800x_control[me->usb_port].retimer_rst_gpio, 0);
+	/* Power-down sequencing must be handled in HW */
+	gpio_set_level(kb800x_control[me->usb_port].usb_ls_en_gpio, 0);
+
+	return EC_SUCCESS;
+}
+
+const struct usb_mux_driver kb800x_usb_mux_driver = {
+	.init = kb800x_init,
+	.set = kb800x_set_state,
+	.enter_low_power_mode = kb800x_enter_low_power_mode,
+#ifdef CONFIG_CMD_RETIMER
+	.retimer_read = kb800x_read,
+	.retimer_write = kb800x_write,
+#endif /* CONFIG_CMD_RETIMER */
+};
diff --git a/driver/retimer/kb800x.h b/driver/retimer/kb800x.h
new file mode 100644
index 0000000000..1d041f3e29
--- /dev/null
+++ b/driver/retimer/kb800x.h
@@ -0,0 +1,104 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Driver for Kandou KB8001 USB-C 40 Gb/s multiprotocol switch.
+ */
+
+#ifndef __CROS_EC_KB800X_H
+#define __CROS_EC_KB800X_H
+
+#include "compile_time_macros.h"
+#include "gpio_signal.h"
+#include "usb_mux.h"
+
+#define KB800X_I2C_ADDR0_FLAGS 0x08
+#define KB800X_I2C_ADDR1_FLAGS 0x0C
+
+extern const struct usb_mux_driver kb800x_usb_mux_driver;
+
+/* Set the protocol */
+#define KB800X_REG_PROTOCOL 0x0001
+#define KB800X_PROTOCOL_USB3 0x0
+#define KB800X_PROTOCOL_DPMF 0x1
+#define KB800X_PROTOCOL_DP 0x2
+#define KB800X_PROTOCOL_CIO 0x3
+
+/* Configure the lane orientaitons */
+#define KB800X_REG_ORIENTATION 0x0002
+#define KB800X_ORIENTATION_POLARITY 0x1
+#define KB800X_ORIENTATION_DP_UFP 0x4
+#define KB800X_ORIENTATION_DP_DFP 0x6
+#define KB800X_ORIENTATION_CIO_LANE_SWAP 0x8
+/* Select one, 0x0 for non-legacy */
+#define KB800X_ORIENTATION_CIO_LEGACY_PASSIVE (0x1 << 4)
+#define KB800X_ORIENTATION_CIO_LEGACY_UNIDIR (0x2 << 4)
+#define KB800X_ORIENTATION_CIO_LEGACY_BIDIR (0x3 << 4)
+
+#define KB800X_REG_RESET 0x0006
+#define KB800X_RESET_FSM BIT(0)
+#define KB800X_RESET_MM BIT(1)
+#define KB800X_RESET_SERDES BIT(2)
+#define KB800X_RESET_COM BIT(3)
+#define KB800X_RESET_MASK GENMASK(3, 0)
+
+#define KB800X_REG_XBAR_OVR 0x5040
+#define KB800X_XBAR_OVR_EN BIT(6)
+
+/* Registers to configure the elastic buffer input connection */
+#define KB800X_REG_XBAR_EB1SEL 0x5044
+#define KB800X_REG_XBAR_EB23SEL 0x5045
+#define KB800X_REG_XBAR_EB4SEL 0x5046
+#define KB800X_REG_XBAR_EB56SEL 0x5047
+
+/* Registers to configure the elastic buffer output connection (x=0-7) */
+#define KB800X_REG_TXSEL_FROM_PHY(x) (0x5048 + ((x) / 2))
+
+enum kb800x_ss_lane { KB800X_TX0 = 0, KB800X_TX1, KB800X_RX0, KB800X_RX1 };
+
+enum kb800x_phy_lane {
+	KB800X_A0 = 0,
+	KB800X_A1,
+	KB800X_B0,
+	KB800X_B1,
+	KB800X_C0,
+	KB800X_C1,
+	KB800X_D0,
+	KB800X_D1,
+	KB800X_PHY_LANE_COUNT
+};
+
+enum kb800x_eb {
+	KB800X_EB1 = 0,
+	KB800X_EB2,
+	KB800X_EB3,
+	KB800X_EB4,
+	KB800X_EB5,
+	KB800X_EB6
+};
+
+#define KB800X_FLIP_SS_LANE(x) ((x) + 1 - 2 * ((x)&0x1))
+#define KB800X_LANE_NUMBER_FROM_PHY(x) ((x)&0x1)
+#define KB800X_PHY_IS_AB(x) ((x) <= KB800X_B1)
+
+struct kb800x_control_t {
+	enum gpio_signal retimer_rst_gpio;
+	enum gpio_signal usb_ls_en_gpio;
+#ifdef CONFIG_KB800X_CUSTOM_XBAR
+	enum kb800x_ss_lane ss_lanes[KB800X_PHY_LANE_COUNT];
+#endif /* CONFIG_KB800X_CUSTOM_XBAR */
+};
+
+/*
+ * Default 'example' lane mapping. With this mapping, CONFIG_KB800X_CUSTOM_XBAR
+ * can be undefined, since a custom xbar mapping is not needed.
+ * ss_lanes = {
+ * [KB800X_A0] = KB800X_TX0, [KB800X_A1] = KB800X_RX0,
+ * [KB800X_B0] = KB800X_RX1, [KB800X_B1] = KB800X_TX1,
+ * [KB800X_C0] = KB800X_RX0, [KB800X_C1] = KB800X_TX0,
+ * [KB800X_D0] = KB800X_TX1, [KB800X_D1] = KB800X_RX1,}
+ */
+
+extern struct kb800x_control_t kb800x_control[];
+
+#endif /* __CROS_EC_KB800X_H  */
diff --git a/driver/retimer/kb8010.c b/driver/retimer/kb8010.c
new file mode 100644
index 0000000000..f3727e297f
--- /dev/null
+++ b/driver/retimer/kb8010.c
@@ -0,0 +1,280 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Driver for Kandou KB801x USB-C 40 Gb/s multiprotocol switch.
+ */
+
+#include "common.h"
+#include "console.h"
+#include "gpio.h"
+#include "i2c.h"
+#include "kb8010.h"
+#include "retimer/kb8010_public.h"
+#include "timer.h"
+
+/* Time between load switch enable and the reset being de-asserted */
+#define KB8010_POWER_ON_DELAY_MS 20
+
+static mux_state_t cached_mux_state[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+#define KB8010_LANE_CFG_LEN 8
+enum kb8010_modes {
+	KB8010_USB3 = KB8010_PROTOCOL_USB3,
+	KB8010_DPMF = KB8010_PROTOCOL_DPMF,
+	KB8010_DP = KB8010_PROTOCOL_DP,
+	KB8010_USB4_TBT = KB8010_PROTOCOL_USB4,
+	KB8010_NUM_MODES
+};
+
+struct kb80010_reg_desc {
+	uint16_t offset;
+	uint8_t val;
+};
+
+const static struct kb80010_reg_desc kb8010_init_cfg[] = {
+	{ KB8010_REG_SBBR_COMRX_CH_SHARED_LINK_CTRL_RUN_POST_CDR_OFFSET, 0x03 },
+	{ KB8010_REG_SBBR_COMRX_CH_SHARED_LINK_CTRL_RUN_OFFSET, 0x07 },
+	{ KB8010_REG_SBBR_BR_RX_CAL_VGA2_GXR, 0x04 },
+	{ KB8010_REG_SBBR_COMRX_AZC_CTRL_CTLE_OC_BW_STG1, 0x03 },
+	{ KB8010_REG_SBBR_COMRX_AZC_CTRL_CTLE_OC_BW_STG2, 0x06 },
+	{ KB8010_REG_SBBR_COMRX_AZC_CTRL_CTLE_OC_BW_STG3, 0x0A },
+	{ KB8010_REG_SBBR_COMRX_LFPS_LFPS_CTRL, 0x13 },
+	{ KB8010_REG_SBBR_BR_RX_CAL_OFFSET_EYE_BG_SAT_OVF, 0x01 },
+	{ KB8010_REG_SBBR_COMRX_CH_0_LINK_CTRL_RUN3, 0xFF },
+	{ KB8010_REG_SBBR_COMRX_CH_1_LINK_CTRL_RUN3, 0xFF },
+};
+
+const static struct kb80010_reg_desc kb8010_dp_cfg[] = {
+	{ KB8010_REG_ORIENTATION, 0x06 },
+	{ KB8010_REG_SBBR_COMTX_OUTPUT_DRIVER_MISC_OVR_EN, 0x02 },
+	{ KB8010_REG_DP_L_EQ_CFG, 0x09 },
+	{ KB8010_REG_DFP_REPLY_TIMEOUT, 0x60 },
+	{ KB8010_REG_DP_D_IEEE_OUI, 0xba },
+	{ KB8010_REG_DP_D_FUNC_1, 0x67 },
+	{ KB8010_REG_DP_D_FUNC_2, 0x91 },
+};
+
+const static uint8_t kb8010_flip_cfg[KB8010_NUM_MODES][KB8010_LANE_CFG_LEN] = {
+	{ 0x05, 0x02, 0x05, 0x02, 0x02, 0x08, 0x02, 0x08 },
+	{ 0x05, 0x20, 0x05, 0x01, 0x13, 0x08, 0x00, 0x08 },
+	{ 0x50, 0x20, 0x06, 0x01, 0x13, 0x21, 0x00, 0x00 },
+	{ 0x05, 0x02, 0x05, 0x02, 0x02, 0x08, 0x02, 0x08 },
+};
+
+static int kb8010_write(const struct usb_mux *me, uint16_t address,
+			uint8_t data)
+{
+	uint8_t kb8010_config[3];
+
+	kb8010_config[0] = (address >> 8) & 0xff;
+	kb8010_config[1] = address & 0xff;
+	kb8010_config[2] = data;
+	return i2c_xfer(me->i2c_port, me->i2c_addr_flags, kb8010_config,
+			sizeof(kb8010_config), NULL, 0);
+}
+
+static int kb8010_pair_write(const struct usb_mux *me,
+			     const struct kb80010_reg_desc *pair,
+			     const int num_pairs)
+{
+	int i;
+	int rv;
+
+	for (i = 0; i < num_pairs; ++i) {
+		rv = kb8010_write(me, pair[i].offset, pair[i].val);
+		if (rv != EC_SUCCESS) {
+			return rv;
+		}
+	}
+
+	return EC_SUCCESS;
+}
+
+static int kb8010_sequential_write(const struct usb_mux *me,
+				   const uint16_t start_addr,
+				   const uint8_t *values, const uint8_t size)
+{
+	int i;
+	int rv;
+
+	for (i = 0; i < size; ++i) {
+		rv = kb8010_write(me, start_addr + i, values[i]);
+		if (rv != EC_SUCCESS) {
+			return rv;
+		}
+	}
+
+	return EC_SUCCESS;
+}
+
+static int kb8010_global_init(const struct usb_mux *me)
+{
+	return kb8010_pair_write(me, kb8010_init_cfg,
+				 ARRAY_SIZE(kb8010_init_cfg));
+}
+
+static int kb8010_config_usb4_tbt(const struct usb_mux *me,
+				  mux_state_t mux_state)
+{
+	enum idh_ptype cable_type;
+	int rv;
+	union tbt_mode_resp_cable cable_resp = {
+		.raw_value =
+			pd_get_tbt_mode_vdo(me->usb_port, TCPCI_MSG_SOP_PRIME)
+	};
+
+	cable_type = get_usb_pd_cable_type(me->usb_port);
+
+	/* Special configuration only for legacy mode */
+	if (cable_type == IDH_PTYPE_ACABLE ||
+	    cable_resp.tbt_active_passive == TBT_CABLE_ACTIVE) {
+		/* Active cable */
+		if (cable_resp.lsrx_comm == UNIDIR_LSRX_COMM) {
+			/* uni-directional */
+			cable_type = KB8010_CABLE_TYPE_ACTIVE_UNIDIR;
+		} else {
+			/* bi-directional */
+			cable_type = KB8010_CABLE_TYPE_ACTIVE_BIDIR;
+		}
+	} else {
+		/* Passive Cable */
+		rv = kb8010_write(me, KB8010_REG_CIO_CFG_WAKEUP_IGN_LS_DET,
+				  0x1d);
+		if (rv) {
+			return rv;
+		}
+		cable_type = KB8010_CABLE_TYPE_PASSIVE;
+	}
+
+	return kb8010_write(me, KB8010_REG_ORIENTATION, cable_type);
+}
+
+static int kb8010_set_state(const struct usb_mux *me, mux_state_t mux_state,
+			    bool *ack_required)
+{
+	int rv;
+	enum kb8010_modes mode = KB8010_USB3;
+
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
+	cached_mux_state[me->usb_port] = mux_state;
+	rv = kb8010_write(me, KB8010_REG_RESET, KB8010_RESET_MASK);
+	if (rv) {
+		return rv;
+	}
+	/* Release memory map reset */
+	rv = kb8010_write(me, KB8010_REG_RESET,
+			  KB8010_RESET_MASK & ~KB8010_RESET_MM);
+	if (rv) {
+		return rv;
+	}
+
+	/* Already in reset, nothing to do */
+	if ((mux_state == USB_PD_MUX_NONE) ||
+	    (mux_state & USB_PD_MUX_SAFE_MODE)) {
+		return EC_SUCCESS;
+	}
+
+	/* Perform common initialization */
+	rv = kb8010_global_init(me);
+	if (rv) {
+		return rv;
+	}
+
+	/* USB4/TBT mode */
+	if (mux_state &
+	    (USB_PD_MUX_USB4_ENABLED | USB_PD_MUX_TBT_COMPAT_ENABLED)) {
+		mode = KB8010_USB4_TBT;
+		rv = kb8010_config_usb4_tbt(me, mux_state);
+		if (rv) {
+			return rv;
+		}
+	} else if (mux_state &
+		   (USB_PD_MUX_DP_ENABLED | USB_PD_MUX_USB_ENABLED)) {
+		/*
+		 * USB3, DP, or DPMF mode
+		 * DP and DPMF modes require the same set of register writes for
+		 * the DP function. USB3 does not require any additional
+		 * configuration other than selecting the mode.
+		 */
+		if (mux_state & USB_PD_MUX_DP_ENABLED) {
+			/* DP or DPMF mode utilizes the same DP configuration */
+			rv = kb8010_pair_write(me, kb8010_dp_cfg,
+					       ARRAY_SIZE(kb8010_dp_cfg));
+			if (rv) {
+				return rv;
+			}
+			mode = mux_state & USB_PD_MUX_USB_ENABLED ?
+				       KB8010_DPMF :
+				       KB8010_DP;
+		}
+	}
+
+	/* Flip configuration */
+	if (mux_state & USB_PD_MUX_POLARITY_INVERTED) {
+		rv = kb8010_write(me, KB8010_REG_XBAR_SBU_CFG, 0x0d);
+		if (rv) {
+			return rv;
+		}
+		rv = kb8010_write(me, KB8010_REG_XBAR_OVR, 0x40);
+		if (rv) {
+			return rv;
+		}
+		rv = kb8010_sequential_write(me, KB8010_REG_XBAR_EB1SEL,
+					     kb8010_flip_cfg[mode],
+					     ARRAY_SIZE(kb8010_flip_cfg[mode]));
+		if (rv) {
+			return rv;
+		}
+	} else {
+		rv = kb8010_write(me, KB8010_REG_XBAR_SBU_CFG, 0x02);
+		if (rv) {
+			return rv;
+		}
+	}
+
+	/* Write mode to protocol register */
+	rv = kb8010_write(me, KB8010_REG_PROTOCOL, (uint8_t)mode);
+	if (rv) {
+		return rv;
+	}
+
+	/* Enable KB8010 */
+	return kb8010_write(me, KB8010_REG_RESET, 0x00);
+}
+
+static int kb8010_init(const struct usb_mux *me)
+{
+	bool unused;
+
+	gpio_set_level(kb8010_controls[me->usb_port].retimer_rst_gpio, 1);
+
+	/*
+	 * Delay after enabling power and releasing the reset to allow the power
+	 * to come up and the reset to be released by the power sequencing
+	 * logic. If after the delay, the reset is still held low - return an
+	 * error.
+	 */
+	msleep(KB8010_POWER_ON_DELAY_MS);
+	if (!gpio_get_level(kb8010_controls[me->usb_port].retimer_rst_gpio)) {
+		return EC_ERROR_NOT_POWERED;
+	}
+
+	return kb8010_set_state(me, USB_PD_MUX_NONE, &unused);
+}
+
+static int kb8010_enter_low_power_mode(const struct usb_mux *me)
+{
+	/* To endter low power mode, put KB8010 in reset */
+	gpio_set_level(kb8010_controls[me->usb_port].retimer_rst_gpio, 0);
+
+	return EC_SUCCESS;
+}
+
+const struct usb_mux_driver kb8010_usb_retimer_driver = {
+	.init = kb8010_init,
+	.set = kb8010_set_state,
+	.enter_low_power_mode = kb8010_enter_low_power_mode,
+};
diff --git a/driver/retimer/kb8010.h b/driver/retimer/kb8010.h
new file mode 100644
index 0000000000..7e319ce81f
--- /dev/null
+++ b/driver/retimer/kb8010.h
@@ -0,0 +1,80 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Driver for Kandou KB8001 USB-C 40 Gb/s multiprotocol switch.
+ */
+
+#ifndef __CROS_EC_KB8010_H
+#define __CROS_EC_KB8010_H
+
+#include "compile_time_macros.h"
+
+#define KB8010_I2C_ADDR0_FLAGS 0x08
+#define KB8010_I2C_ADDR1_FLAGS 0x0C
+
+/* Set the protocol */
+#define KB8010_REG_PROTOCOL 0x0001
+#define KB8010_PROTOCOL_USB3 0x0
+#define KB8010_PROTOCOL_DPMF 0x1
+#define KB8010_PROTOCOL_DP 0x2
+#define KB8010_PROTOCOL_USB4 0x3
+
+/* Configure the lane orientaitons */
+#define KB8010_REG_ORIENTATION 0x0002
+#define KB8010_CABLE_TYPE_PASSIVE 0x10
+#define KB8010_CABLE_TYPE_ACTIVE_UNIDIR 0x20
+#define KB8010_CABLE_TYPE_ACTIVE_BIDIR 0x30
+
+#define KB8010_REG_RESET 0x0006
+#define KB8010_RESET_FSM BIT(0)
+#define KB8010_RESET_MM BIT(1)
+#define KB8010_RESET_SERDES BIT(2)
+#define KB8010_RESET_COM BIT(3)
+#define KB8010_RESET_MASK GENMASK(3, 0)
+
+/* XBAR */
+#define KB8010_REG_XBAR_OVR 0x5040
+
+/* Registers to configure the elastic buffer input connection */
+#define KB8010_REG_XBAR_EB1SEL 0x5044
+#define KB8010_REG_XBAR_EB2SEL 0x5045
+#define KB8010_REG_XBAR_EB4SEL 0x5046
+#define KB8010_REG_XBAR_EB5SEL 0x5047
+#define KB8010_REG_XBAR_TXASEL 0x5048
+#define KB8010_REG_XBAR_TXBSEL 0x5049
+#define KB8010_REG_XBAR_TXCSEL 0x504A
+#define KB8010_REG_XBAR_TXDSEL 0x504B
+
+/* Registers to configure SBU LSX/AUX flip */
+#define KB8010_REG_XBAR_SBU_CFG 0x504C
+
+/* DP */
+#define KB8010_REG_DP_D_IEEE_OUI 0x603D
+
+/* TODO: b:280629671
+ * Following two registers don't have names yet,
+ * need to work with Kandou to get names and update
+ */
+#define KB8010_REG_DP_D_FUNC_1 0x603E
+#define KB8010_REG_DP_D_FUNC_2 0x603F
+#define KB8010_REG_DP_L_EQ_CFG 0X6314
+#define KB8010_REG_DFP_REPLY_TIMEOUT 0X6393
+
+/* CIO */
+#define KB8010_REG_CIO_CFG_WAKEUP_IGN_LS_DET 0X811F
+
+/* SerDes broadcast */
+#define KB8010_REG_SBBR_COMRX_CH_0_LINK_CTRL_RUN3 0XF02D
+#define KB8010_REG_SBBR_COMRX_CH_1_LINK_CTRL_RUN3 0XF063
+#define KB8010_REG_SBBR_COMRX_CH_SHARED_LINK_CTRL_RUN_OFFSET 0XF0A0
+#define KB8010_REG_SBBR_COMRX_CH_SHARED_LINK_CTRL_RUN_POST_CDR_OFFSET 0XF0A9
+#define KB8010_REG_SBBR_COMRX_AZC_CTRL_CTLE_OC_BW_STG1 0xF172
+#define KB8010_REG_SBBR_COMRX_AZC_CTRL_CTLE_OC_BW_STG2 0xF173
+#define KB8010_REG_SBBR_COMRX_AZC_CTRL_CTLE_OC_BW_STG3 0xF174
+#define KB8010_REG_SBBR_COMRX_LFPS_LFPS_CTRL 0XF242
+#define KB8010_REG_SBBR_COMTX_OUTPUT_DRIVER_MISC_OVR_EN 0XF2CC
+#define KB8010_REG_SBBR_BR_RX_CAL_OFFSET_EYE_BG_SAT_OVF 0XFECA
+#define KB8010_REG_SBBR_BR_RX_CAL_VGA2_GXR 0XFFB9
+
+#endif /* __CROS_EC_KB8010_H  */
diff --git a/driver/retimer/nb7v904m.c b/driver/retimer/nb7v904m.c
index 2defda52a2..18fdf3b2ba 100644
--- a/driver/retimer/nb7v904m.c
+++ b/driver/retimer/nb7v904m.c
@@ -1,10 +1,9 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * ON Semiconductor NB7V904M USB Type-C DisplayPort Alt Mode Redriver
  */
-#include <stdbool.h>
 #include "common.h"
 #include "console.h"
 #include "ec_commands.h"
@@ -12,23 +11,23 @@
 #include "nb7v904m.h"
 #include "usb_mux.h"
 
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
+#include <stdbool.h>
+
+#define CPRINTS(format, args...) cprints(CC_USB, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args)
+
+#ifdef CONFIG_NB7V904M_LPM_OVERRIDE
+int nb7v904m_lpm_disable = 0;
+#endif
 
 static int nb7v904m_write(const struct usb_mux *me, int offset, int data)
 {
-	return i2c_write8(me->i2c_port,
-			  me->i2c_addr_flags,
-			  offset, data);
-
+	return i2c_write8(me->i2c_port, me->i2c_addr_flags, offset, data);
 }
 
 static int nb7v904m_read(const struct usb_mux *me, int offset, int *regval)
 {
-	return i2c_read8(me->i2c_port,
-			 me->i2c_addr_flags,
-			 offset, regval);
-
+	return i2c_read8(me->i2c_port, me->i2c_addr_flags, offset, regval);
 }
 
 static int set_low_power_mode(const struct usb_mux *me, bool enable)
@@ -39,6 +38,10 @@ static int set_low_power_mode(const struct usb_mux *me, bool enable)
 	rv = nb7v904m_read(me, NB7V904M_REG_GEN_DEV_SETTINGS, &regval);
 	if (rv)
 		return rv;
+#ifdef CONFIG_NB7V904M_LPM_OVERRIDE
+	if (nb7v904m_lpm_disable)
+		enable = 0;
+#endif
 
 	if (enable)
 		regval &= ~NB7V904M_CHIP_EN;
@@ -58,6 +61,79 @@ static int nb7v904m_enter_low_power_mode(const struct usb_mux *me)
 	return rv;
 }
 
+/* Tune USB Eq All: This must be called on board_init context */
+int nb7v904m_tune_usb_set_eq(const struct usb_mux *me, uint8_t eq_a,
+			     uint8_t eq_b, uint8_t eq_c, uint8_t eq_d)
+{
+	int rv = EC_SUCCESS;
+
+	if (eq_a != NB7V904M_CH_ALL_SKIP_EQ)
+		rv = nb7v904m_write(me, NB7V904M_REG_CH_A_EQ_SETTINGS, eq_a);
+
+	if (eq_b != NB7V904M_CH_ALL_SKIP_EQ)
+		rv |= nb7v904m_write(me, NB7V904M_REG_CH_B_EQ_SETTINGS, eq_b);
+
+	if (eq_c != NB7V904M_CH_ALL_SKIP_EQ)
+		rv |= nb7v904m_write(me, NB7V904M_REG_CH_C_EQ_SETTINGS, eq_c);
+
+	if (eq_d != NB7V904M_CH_ALL_SKIP_EQ)
+		rv |= nb7v904m_write(me, NB7V904M_REG_CH_D_EQ_SETTINGS, eq_d);
+
+	return rv;
+}
+
+/* Tune USB Flat Gain: This must be called on board_init context */
+int nb7v904m_tune_usb_flat_gain(const struct usb_mux *me, uint8_t gain_a,
+				uint8_t gain_b, uint8_t gain_c, uint8_t gain_d)
+{
+	int rv = EC_SUCCESS;
+
+	if (gain_a != NB7V904M_CH_ALL_SKIP_GAIN)
+		rv = nb7v904m_write(me, NB7V904M_REG_CH_A_FLAT_GAIN, gain_a);
+
+	if (gain_b != NB7V904M_CH_ALL_SKIP_GAIN)
+		rv |= nb7v904m_write(me, NB7V904M_REG_CH_B_FLAT_GAIN, gain_b);
+
+	if (gain_c != NB7V904M_CH_ALL_SKIP_GAIN)
+		rv |= nb7v904m_write(me, NB7V904M_REG_CH_C_FLAT_GAIN, gain_c);
+
+	if (gain_d != NB7V904M_CH_ALL_SKIP_GAIN)
+		rv |= nb7v904m_write(me, NB7V904M_REG_CH_D_FLAT_GAIN, gain_d);
+
+	return rv;
+}
+
+/* Set Loss Profile Matching : This must be called on board_init context */
+int nb7v904m_set_loss_profile_match(const struct usb_mux *me, uint8_t loss_a,
+				    uint8_t loss_b, uint8_t loss_c,
+				    uint8_t loss_d)
+{
+	int rv = EC_SUCCESS;
+
+	if (loss_a != NB7V904M_CH_ALL_SKIP_LOSS)
+		rv |= nb7v904m_write(me, NB7V904M_REG_CH_A_LOSS_CTRL, loss_a);
+
+	if (loss_b != NB7V904M_CH_ALL_SKIP_LOSS)
+		rv |= nb7v904m_write(me, NB7V904M_REG_CH_B_LOSS_CTRL, loss_b);
+
+	if (loss_c != NB7V904M_CH_ALL_SKIP_LOSS)
+		rv |= nb7v904m_write(me, NB7V904M_REG_CH_C_LOSS_CTRL, loss_c);
+
+	if (loss_d != NB7V904M_CH_ALL_SKIP_LOSS)
+		rv |= nb7v904m_write(me, NB7V904M_REG_CH_D_LOSS_CTRL, loss_d);
+
+	return rv;
+}
+
+/* Set AUX control switch */
+int nb7v904m_set_aux_ch_switch(const struct usb_mux *me, uint8_t aux_ch)
+{
+	int rv = EC_SUCCESS;
+
+	rv = nb7v904m_write(me, NB7V904M_REG_AUX_CH_CTRL, aux_ch);
+	return rv;
+}
+
 static int nb7v904m_init(const struct usb_mux *me)
 {
 	int rv = set_low_power_mode(me, 0);
@@ -67,12 +143,20 @@ static int nb7v904m_init(const struct usb_mux *me)
 	return rv;
 }
 
-static int nb7v904m_set_mux(const struct usb_mux *me, mux_state_t mux_state)
+static int nb7v904m_set_mux(const struct usb_mux *me, mux_state_t mux_state,
+			    bool *ack_required)
 {
 	int rv = EC_SUCCESS;
 	int regval;
 	int flipped = !!(mux_state & USB_PD_MUX_POLARITY_INVERTED);
 
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
+	/* This driver treats safe mode as none */
+	if (mux_state & USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
+
 	/* Turn off redriver if it's not needed at all. */
 	if (mux_state == USB_PD_MUX_NONE)
 		return nb7v904m_enter_low_power_mode(me);
@@ -84,8 +168,8 @@ static int nb7v904m_set_mux(const struct usb_mux *me, mux_state_t mux_state)
 	/* Clear operation mode field */
 	rv = nb7v904m_read(me, NB7V904M_REG_GEN_DEV_SETTINGS, &regval);
 	if (rv) {
-		CPRINTS("C%d %s: Failed to obtain dev settings!",
-			me->usb_port, __func__);
+		CPRINTS("C%d %s: Failed to obtain dev settings!", me->usb_port,
+			__func__);
 		return rv;
 	}
 	regval &= ~NB7V904M_OP_MODE_MASK;
@@ -109,9 +193,9 @@ static int nb7v904m_set_mux(const struct usb_mux *me, mux_state_t mux_state)
 
 	if (mux_state & USB_PD_MUX_DP_ENABLED) {
 		/* Connect AUX */
-		rv = nb7v904m_write(me, NB7V904M_REG_AUX_CH_CTRL, flipped ?
-				    NB7V904M_AUX_CH_FLIPPED :
-				    NB7V904M_AUX_CH_NORMAL);
+		rv = nb7v904m_write(me, NB7V904M_REG_AUX_CH_CTRL,
+				    flipped ? NB7V904M_AUX_CH_FLIPPED :
+					      NB7V904M_AUX_CH_NORMAL);
 		/* Enable all channels for DP */
 		regval |= NB7V904M_CH_EN_MASK;
 	} else {
diff --git a/driver/retimer/nb7v904m.h b/driver/retimer/nb7v904m.h
index 8bb43f79eb..07c3b4d51f 100644
--- a/driver/retimer/nb7v904m.h
+++ b/driver/retimer/nb7v904m.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -16,26 +16,119 @@
 #define NB7V904M_I2C_ADDR2 0x1C
 
 /* Registers */
-#define NB7V904M_REG_GEN_DEV_SETTINGS	0x00
-#define NB7V904M_REG_AUX_CH_CTRL        0x09
+#define NB7V904M_REG_GEN_DEV_SETTINGS 0x00
+#define NB7V904M_REG_CH_A_EQ_SETTINGS 0x01
+#define NB7V904M_REG_CH_B_EQ_SETTINGS 0x03
+#define NB7V904M_REG_CH_C_EQ_SETTINGS 0x05
+#define NB7V904M_REG_CH_D_EQ_SETTINGS 0x07
+#define NB7V904M_REG_AUX_CH_CTRL 0x09
+#define NB7V904M_REG_CH_A_FLAT_GAIN 0x18
+#define NB7V904M_REG_CH_A_LOSS_CTRL 0x19
+#define NB7V904M_REG_CH_B_FLAT_GAIN 0x1a
+#define NB7V904M_REG_CH_B_LOSS_CTRL 0x1b
+#define NB7V904M_REG_CH_C_FLAT_GAIN 0x1c
+#define NB7V904M_REG_CH_C_LOSS_CTRL 0x1d
+#define NB7V904M_REG_CH_D_FLAT_GAIN 0x1e
+#define NB7V904M_REG_CH_D_LOSS_CTRL 0x1f
 
 /* 0x00 - General Device Settings */
-#define NB7V904M_CHIP_EN        BIT(0)
-#define NB7V904M_USB_DP_NORMAL  BIT(1)
+#define NB7V904M_CHIP_EN BIT(0)
+#define NB7V904M_USB_DP_NORMAL BIT(1)
 #define NB7V904M_USB_DP_FLIPPED 0
-#define NB7V904M_DP_ONLY        BIT(2)
-#define NB7V904M_USB_ONLY       (BIT(3) | BIT(1))
-#define NB7V904M_OP_MODE_MASK   GENMASK(3, 1)
-#define NB7V904M_CH_A_EN        BIT(4)
-#define NB7V904M_CH_B_EN        BIT(5)
-#define NB7V904M_CH_C_EN        BIT(6)
-#define NB7V904M_CH_D_EN        BIT(7)
-#define NB7V904M_CH_EN_MASK     GENMASK(7, 4)
+#define NB7V904M_DP_ONLY BIT(2)
+#define NB7V904M_USB_ONLY (BIT(3) | BIT(1))
+#define NB7V904M_OP_MODE_MASK GENMASK(3, 1)
+#define NB7V904M_CH_A_EN BIT(4)
+#define NB7V904M_CH_B_EN BIT(5)
+#define NB7V904M_CH_C_EN BIT(6)
+#define NB7V904M_CH_D_EN BIT(7)
+#define NB7V904M_CH_EN_MASK GENMASK(7, 4)
+
+/* 0x01 - Channel A Equalization Settings */
+#define NB7V904M_CH_A_EQ_0_DB 0x0a
+#define NB7V904M_CH_A_EQ_2_DB 0x08
+#define NB7V904M_CH_A_EQ_4_DB 0x0e
+#define NB7V904M_CH_A_EQ_6_DB 0x0c
+#define NB7V904M_CH_A_EQ_8_DB 0x02
+#define NB7V904M_CH_A_EQ_10_DB 0x00
+
+/* 0x03 - Channel B Equalization Settings */
+#define NB7V904M_CH_B_EQ_0_DB 0x0e
+#define NB7V904M_CH_B_EQ_2_DB 0x0c
+#define NB7V904M_CH_B_EQ_4_DB 0x0a
+#define NB7V904M_CH_B_EQ_6_DB 0x08
+#define NB7V904M_CH_B_EQ_8_DB 0x06
+#define NB7V904M_CH_B_EQ_10_DB 0x00
+
+/* 0x05 - Channel C Equalization Settings */
+#define NB7V904M_CH_C_EQ_0_DB 0x0e
+#define NB7V904M_CH_C_EQ_2_DB 0x0c
+#define NB7V904M_CH_C_EQ_4_DB 0x0a
+#define NB7V904M_CH_C_EQ_6_DB 0x08
+#define NB7V904M_CH_C_EQ_8_DB 0x06
+#define NB7V904M_CH_C_EQ_10_DB 0x00
+
+/* 0x07 - Channel D Equalization Settings */
+#define NB7V904M_CH_D_EQ_0_DB 0x0a
+#define NB7V904M_CH_D_EQ_2_DB 0x08
+#define NB7V904M_CH_D_EQ_4_DB 0x0e
+#define NB7V904M_CH_D_EQ_6_DB 0x0c
+#define NB7V904M_CH_D_EQ_8_DB 0x02
+#define NB7V904M_CH_D_EQ_10_DB 0x00
 
 /* 0x09 - Auxiliary Channel Control */
-#define NB7V904M_AUX_CH_NORMAL   0
-#define NB7V904M_AUX_CH_FLIPPED  BIT(0)
-#define NB7V904M_AUX_CH_HI_Z     BIT(1)
+#define NB7V904M_AUX_CH_NORMAL 0
+#define NB7V904M_AUX_CH_FLIPPED BIT(0)
+#define NB7V904M_AUX_CH_HI_Z BIT(1)
+
+/* 0x18 - Channel A Flag Gain */
+#define NB7V904M_CH_A_GAIN_0_DB 0x00
+#define NB7V904M_CH_A_GAIN_1P5_DB 0x02
+#define NB7V904M_CH_A_GAIN_3P5_DB 0x03
+
+/* 0x1a - Channel B Flag Gain */
+#define NB7V904M_CH_B_GAIN_0_DB 0x03
+#define NB7V904M_CH_B_GAIN_1P5_DB 0x01
+#define NB7V904M_CH_B_GAIN_3P5_DB 0x00
+
+/* 0x1c - Channel C Flag Gain */
+#define NB7V904M_CH_C_GAIN_0_DB 0x03
+#define NB7V904M_CH_C_GAIN_1P5_DB 0x01
+#define NB7V904M_CH_C_GAIN_3P5_DB 0x00
+
+/* 0x1e - Channel D Flag Gain */
+#define NB7V904M_CH_D_GAIN_0_DB 0x00
+#define NB7V904M_CH_D_GAIN_1P5_DB 0x02
+#define NB7V904M_CH_D_GAIN_3P5_DB 0x03
+
+/* 0x19 - Channel A Loss Profile Matching Control */
+/* 0x1b - Channel B Loss Profile Matching Control */
+/* 0x1d - Channel C Loss Profile Matching Control */
+/* 0x1f - Channel D Loss Profile Matching Control */
+#define NB7V904M_LOSS_PROFILE_A 0x00
+#define NB7V904M_LOSS_PROFILE_B 0x01
+#define NB7V904M_LOSS_PROFILE_C 0x02
+#define NB7V904M_LOSS_PROFILE_D 0x03
 
 extern const struct usb_mux_driver nb7v904m_usb_redriver_drv;
+#ifdef CONFIG_NB7V904M_LPM_OVERRIDE
+extern int nb7v904m_lpm_disable;
+#endif
+
+/* Use this value if tuning eq wants to be skipped  */
+#define NB7V904M_CH_ALL_SKIP_EQ 0xff
+int nb7v904m_tune_usb_set_eq(const struct usb_mux *me, uint8_t eq_a,
+			     uint8_t eq_b, uint8_t eq_c, uint8_t eq_d);
+/* Use this value if tuning gain wants to be skipped  */
+#define NB7V904M_CH_ALL_SKIP_GAIN 0xff
+int nb7v904m_tune_usb_flat_gain(const struct usb_mux *me, uint8_t gain_a,
+				uint8_t gain_b, uint8_t gain_c, uint8_t gain_d);
+/* Use this value if loss profile control  wants to be skipped  */
+#define NB7V904M_CH_ALL_SKIP_LOSS 0xff
+/* Control channel Loss Profile Matching */
+int nb7v904m_set_loss_profile_match(const struct usb_mux *me, uint8_t loss_a,
+				    uint8_t loss_b, uint8_t loss_c,
+				    uint8_t loss_d);
+/* Control mapping between AUX and SBU */
+int nb7v904m_set_aux_ch_switch(const struct usb_mux *me, uint8_t aux_ch);
 #endif /* __CROS_EC_USB_REDRIVER_NB7V904M_H */
diff --git a/driver/retimer/pi3dpx1207.c b/driver/retimer/pi3dpx1207.c
index 9254c3d4bb..c7053564de 100644
--- a/driver/retimer/pi3dpx1207.c
+++ b/driver/retimer/pi3dpx1207.c
@@ -1,16 +1,16 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * PI3DPX1207 retimer.
  */
 
-#include "pi3dpx1207.h"
 #include "common.h"
 #include "console.h"
 #include "gpio.h"
 #include "i2c.h"
 #include "ioexpander.h"
+#include "pi3dpx1207.h"
 #include "usb_mux.h"
 
 #define I2C_MAX_RETRIES 2
@@ -21,8 +21,7 @@ static uint8_t buf[PI3DPX1207_NUM_REGISTERS];
 /**
  * Local utility functions
  */
-static int pi3dpx1207_i2c_write(const struct usb_mux *me,
-				uint8_t offset,
+static int pi3dpx1207_i2c_write(const struct usb_mux *me, uint8_t offset,
 				uint8_t val)
 {
 	int rv = EC_SUCCESS;
@@ -44,8 +43,8 @@ static int pi3dpx1207_i2c_write(const struct usb_mux *me,
 		attempt = 0;
 		do {
 			attempt++;
-			rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags,
-				      NULL, 0, buf, offset);
+			rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags, NULL, 0,
+				      buf, offset);
 		} while ((rv != EC_SUCCESS) && (attempt < I2C_MAX_RETRIES));
 	}
 
@@ -55,8 +54,8 @@ static int pi3dpx1207_i2c_write(const struct usb_mux *me,
 		attempt = 0;
 		do {
 			attempt++;
-			rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags,
-				      buf, offset + 1, NULL, 0);
+			rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags, buf,
+				      offset + 1, NULL, 0);
 		} while ((rv != EC_SUCCESS) && (attempt < I2C_MAX_RETRIES));
 	}
 	return rv;
@@ -68,6 +67,10 @@ static void pi3dpx1207_shutoff_power(const struct usb_mux *me)
 	const int gpio_enable = pi3dpx1207_controls[port].enable_gpio;
 	const int gpio_dp_enable = pi3dpx1207_controls[port].dp_enable_gpio;
 
+	/* The chip may be automatically turned on by PP3300_S5. */
+	if (gpio_enable == GPIO_SIGNAL_NONE)
+		return;
+
 	gpio_or_ioex_set_level(gpio_enable, 0);
 	gpio_or_ioex_set_level(gpio_dp_enable, 0);
 }
@@ -80,7 +83,9 @@ static int pi3dpx1207_init(const struct usb_mux *me)
 	const int port = me->usb_port;
 	const int gpio_enable = pi3dpx1207_controls[port].enable_gpio;
 
-	gpio_or_ioex_set_level(gpio_enable, 1);
+	if (gpio_enable != GPIO_SIGNAL_NONE)
+		gpio_or_ioex_set_level(gpio_enable, 1);
+
 	return EC_SUCCESS;
 }
 
@@ -90,7 +95,8 @@ static int pi3dpx1207_enter_low_power_mode(const struct usb_mux *me)
 	return EC_SUCCESS;
 }
 
-static int pi3dpx1207_set_mux(const struct usb_mux *me, mux_state_t mux_state)
+static int pi3dpx1207_set_mux(const struct usb_mux *me, mux_state_t mux_state,
+			      bool *ack_required)
 {
 	int rv = EC_SUCCESS;
 	uint8_t mode_val = PI3DPX1207_MODE_WATCHDOG_EN;
@@ -98,31 +104,40 @@ static int pi3dpx1207_set_mux(const struct usb_mux *me, mux_state_t mux_state)
 	const int gpio_enable = pi3dpx1207_controls[port].enable_gpio;
 	const int gpio_dp_enable = pi3dpx1207_controls[port].dp_enable_gpio;
 
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
+	/* This driver treats safe mode as none */
+	if (mux_state & USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
+
 	/* USB */
 	if (mux_state & USB_PD_MUX_USB_ENABLED) {
-		gpio_or_ioex_set_level(gpio_enable, 1);
+		if (gpio_enable != GPIO_SIGNAL_NONE)
+			gpio_or_ioex_set_level(gpio_enable, 1);
 		/* USB with DP */
 		if (mux_state & USB_PD_MUX_DP_ENABLED) {
 			gpio_or_ioex_set_level(gpio_dp_enable, 1);
-			mode_val |= (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-					? PI3DPX1207_MODE_CONF_USB_DP_FLIP
-					: PI3DPX1207_MODE_CONF_USB_DP;
+			mode_val |= (mux_state & USB_PD_MUX_POLARITY_INVERTED) ?
+					    PI3DPX1207_MODE_CONF_USB_DP_FLIP :
+					    PI3DPX1207_MODE_CONF_USB_DP;
 		}
 		/* USB without DP */
 		else {
 			gpio_or_ioex_set_level(gpio_dp_enable, 0);
-			mode_val |= (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-					? PI3DPX1207_MODE_CONF_USB_FLIP
-					: PI3DPX1207_MODE_CONF_USB;
+			mode_val |= (mux_state & USB_PD_MUX_POLARITY_INVERTED) ?
+					    PI3DPX1207_MODE_CONF_USB_FLIP :
+					    PI3DPX1207_MODE_CONF_USB;
 		}
 	}
 	/* DP without USB */
 	else if (mux_state & USB_PD_MUX_DP_ENABLED) {
-		gpio_or_ioex_set_level(gpio_enable, 1);
+		if (gpio_enable != GPIO_SIGNAL_NONE)
+			gpio_or_ioex_set_level(gpio_enable, 1);
 		gpio_or_ioex_set_level(gpio_dp_enable, 1);
-		mode_val |= (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-				? PI3DPX1207_MODE_CONF_DP_FLIP
-				: PI3DPX1207_MODE_CONF_DP;
+		mode_val |= (mux_state & USB_PD_MUX_POLARITY_INVERTED) ?
+				    PI3DPX1207_MODE_CONF_DP_FLIP :
+				    PI3DPX1207_MODE_CONF_DP;
 	}
 	/* Nothing enabled, power down the retimer */
 	else {
diff --git a/driver/retimer/pi3dpx1207.h b/driver/retimer/pi3dpx1207.h
index 2e3405d1aa..b246052f2c 100644
--- a/driver/retimer/pi3dpx1207.h
+++ b/driver/retimer/pi3dpx1207.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -9,35 +9,35 @@
 #ifndef __CROS_EC_USB_RETIMER_PI3PDX1207_H
 #define __CROS_EC_USB_RETIMER_PI3PDX1207_H
 
-#define PI3DPX1207_I2C_ADDR_FLAGS	0x57
-#define PI3DPX1207_NUM_REGISTERS	32
+#define PI3DPX1207_I2C_ADDR_FLAGS 0x57
+#define PI3DPX1207_NUM_REGISTERS 32
 
 /* Register Offset 0 - Revision and Vendor ID */
-#define PI3DPX1207_VID_OFFSET		0
+#define PI3DPX1207_VID_OFFSET 0
 
-#define PI3DPX1207B_VID				0x03
-#define PI3DPX1207C_VID				0x13
+#define PI3DPX1207B_VID 0x03
+#define PI3DPX1207C_VID 0x13
 
 /* Register Offset 1 - Device Type/ID */
-#define PI3DPX1207_DID_OFFSET		1
+#define PI3DPX1207_DID_OFFSET 1
 
-#define PI3DPX1207_DID_ACTIVE_MUX		0x11
+#define PI3DPX1207_DID_ACTIVE_MUX 0x11
 
 /* Register Offset 3 - Mode Control */
-#define PI3DPX1207_MODE_OFFSET		3
+#define PI3DPX1207_MODE_OFFSET 3
 
-#define PI3DPX1207_MODE_WATCHDOG_EN		0x02
+#define PI3DPX1207_MODE_WATCHDOG_EN 0x02
 
-#define PI3DPX1207B_MODE_GEN_APP_EN		0x08
+#define PI3DPX1207B_MODE_GEN_APP_EN 0x08
 
-#define PI3DPX1207_MODE_CONF_SAFE		0x00
-#define PI3DPX1207_MODE_CONF_DP			0x20
-#define PI3DPX1207_MODE_CONF_DP_FLIP		0x30
-#define PI3DPX1207_MODE_CONF_USB		0x40
-#define PI3DPX1207_MODE_CONF_USB_FLIP		0x50
-#define PI3DPX1207_MODE_CONF_USB_DP		0x60
-#define PI3DPX1207_MODE_CONF_USB_DP_FLIP	0x70
-#define PI3DPX1207_MODE_CONF_USB_SUPER		0xC0
+#define PI3DPX1207_MODE_CONF_SAFE 0x00
+#define PI3DPX1207_MODE_CONF_DP 0x20
+#define PI3DPX1207_MODE_CONF_DP_FLIP 0x30
+#define PI3DPX1207_MODE_CONF_USB 0x40
+#define PI3DPX1207_MODE_CONF_USB_FLIP 0x50
+#define PI3DPX1207_MODE_CONF_USB_DP 0x60
+#define PI3DPX1207_MODE_CONF_USB_DP_FLIP 0x70
+#define PI3DPX1207_MODE_CONF_USB_SUPER 0xC0
 
 /* Supported USB retimer drivers */
 extern const struct usb_mux_driver pi3dpx1207_usb_retimer;
@@ -45,7 +45,7 @@ extern const struct usb_mux_driver pi3dpx1207_usb_retimer;
 /* Retimer driver hardware specific controls */
 struct pi3dpx1207_usb_control {
 	/* Retimer enable */
-	const enum gpio_signal enable_gpio;
+	const enum ioex_signal enable_gpio;
 	/* DP Mode enable */
 	const enum gpio_signal dp_enable_gpio;
 };
diff --git a/driver/retimer/pi3hdx1204.c b/driver/retimer/pi3hdx1204.c
index 3b0d80609f..7cf963c7f9 100644
--- a/driver/retimer/pi3hdx1204.c
+++ b/driver/retimer/pi3hdx1204.c
@@ -1,15 +1,15 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * PI3HDX1204 retimer.
  */
 
+#include "console.h"
 #include "i2c.h"
 #include "pi3hdx1204.h"
 
-int pi3hdx1204_enable(const int i2c_port,
-		      const uint16_t i2c_addr_flags,
+int pi3hdx1204_enable(const int i2c_port, const uint16_t i2c_addr_flags,
 		      const int enable)
 {
 	const uint8_t buf[PI3HDX1204_DE_OFFSET + 1] = {
@@ -26,8 +26,7 @@ int pi3hdx1204_enable(const int i2c_port,
 	};
 	int rv;
 
-	rv = i2c_xfer(i2c_port, i2c_addr_flags,
-		      buf, PI3HDX1204_DE_OFFSET + 1,
+	rv = i2c_xfer(i2c_port, i2c_addr_flags, buf, PI3HDX1204_DE_OFFSET + 1,
 		      NULL, 0);
 
 	if (rv)
diff --git a/driver/retimer/pi3hdx1204.h b/driver/retimer/pi3hdx1204.h
index 391e00c73c..637accaf56 100644
--- a/driver/retimer/pi3hdx1204.h
+++ b/driver/retimer/pi3hdx1204.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,60 +8,61 @@
 #ifndef __CROS_EC_USB_RETIMER_PI3HDX1204_H
 #define __CROS_EC_USB_RETIMER_PI3HDX1204_H
 
-#define PI3HDX1204_I2C_ADDR_FLAGS	0x60
+#define PI3HDX1204_I2C_ADDR_FLAGS 0x60
 
 /* Register Offset 0 - Activity */
-#define PI3HDX1204_ACTIVITY_OFFSET	0
+#define PI3HDX1204_ACTIVITY_OFFSET 0
 
 /* Register Offset 1 - Not Used */
-#define PI3HDX1204_NOT_USED_OFFSET	1
+#define PI3HDX1204_NOT_USED_OFFSET 1
 
 /* Register Offset 2 - Enable */
-#define PI3HDX1204_ENABLE_OFFSET	2
-#define PI3HDX1204_ENABLE_ALL_CHANNELS	0xF0
+#define PI3HDX1204_ENABLE_OFFSET 2
+#define PI3HDX1204_ENABLE_ALL_CHANNELS 0xF0
 
 /* Register Offset 3 - EQ setting BIT7-4:CH1, BIT3-0:CH0 */
-#define PI3HDX1204_EQ_CH0_CH1_OFFSET	3
+#define PI3HDX1204_EQ_CH0_CH1_OFFSET 3
 
 /* Register Offset 4 - EQ setting BIT7-4:CH3, BIT3-0:CH2 */
-#define PI3HDX1204_EQ_CH2_CH3_OFFSET	4
+#define PI3HDX1204_EQ_CH2_CH3_OFFSET 4
 
 /* EQ setting for two channel */
-#define PI3HDX1204_EQ_DB25	0x00
-#define PI3HDX1204_EQ_DB80	0x11
-#define PI3HDX1204_EQ_DB110	0x22
-#define PI3HDX1204_EQ_DB220	0x33
-#define PI3HDX1204_EQ_DB410	0x44
-#define PI3HDX1204_EQ_DB710	0x55
-#define PI3HDX1204_EQ_DB900	0x66
-#define PI3HDX1204_EQ_DB1030	0x77
-#define PI3HDX1204_EQ_DB1180	0x88
-#define PI3HDX1204_EQ_DB1390	0x99
-#define PI3HDX1204_EQ_DB1530	0xAA
-#define PI3HDX1204_EQ_DB1690	0xBB
-#define PI3HDX1204_EQ_DB1790	0xCC
-#define PI3HDX1204_EQ_DB1920	0xDD
-#define PI3HDX1204_EQ_DB2050	0xEE
-#define PI3HDX1204_EQ_DB2220	0xFF
+#define PI3HDX1204_EQ_DB25 0x00
+#define PI3HDX1204_EQ_DB80 0x11
+#define PI3HDX1204_EQ_DB110 0x22
+#define PI3HDX1204_EQ_DB220 0x33
+#define PI3HDX1204_EQ_DB410 0x44
+#define PI3HDX1204_EQ_DB710 0x55
+#define PI3HDX1204_EQ_DB900 0x66
+#define PI3HDX1204_EQ_DB1030 0x77
+#define PI3HDX1204_EQ_DB1180 0x88
+#define PI3HDX1204_EQ_DB1390 0x99
+#define PI3HDX1204_EQ_DB1530 0xAA
+#define PI3HDX1204_EQ_DB1690 0xBB
+#define PI3HDX1204_EQ_DB1790 0xCC
+#define PI3HDX1204_EQ_DB1920 0xDD
+#define PI3HDX1204_EQ_DB2050 0xEE
+#define PI3HDX1204_EQ_DB2220 0xFF
 
 /* Register Offset 5 - Output Voltage Swing Setting */
-#define PI3HDX1204_VOD_OFFSET	5
-#define PI3HDX1204_VOD_85_ALL_CHANNELS	0x00
-#define PI3HDX1204_VOD_115_ALL_CHANNELS	0xFF
+#define PI3HDX1204_VOD_OFFSET 5
+#define PI3HDX1204_VOD_80_ALL_CHANNELS 0x00
+#define PI3HDX1204_VOD_95_ALL_CHANNELS 0x55
+#define PI3HDX1204_VOD_115_ALL_CHANNELS 0xAA
+#define PI3HDX1204_VOD_130_ALL_CHANNELS 0xFF
 
 /* Register Offset 6 - Output De-emphasis Setting */
-#define PI3HDX1204_DE_OFFSET	6
-#define PI3HDX1204_DE_DB_0		0x00
-#define PI3HDX1204_DE_DB_MINUS5		0x55
-#define PI3HDX1204_DE_DB_MINUS7		0xAA
-#define PI3HDX1204_DE_DB_MINUS10	0xFF
+#define PI3HDX1204_DE_OFFSET 6
+#define PI3HDX1204_DE_DB_0 0x00
+#define PI3HDX1204_DE_DB_MINUS5 0x55
+#define PI3HDX1204_DE_DB_MINUS7 0xAA
+#define PI3HDX1204_DE_DB_MINUS10 0xFF
 
 /* Delay for I2C to be ready after power on. */
-#define PI3HDX1204_POWER_ON_DELAY_MS 2
+#define PI3HDX1204_POWER_ON_DELAY_MS 13
 
 /* Enable or disable the PI3HDX1204. */
-int pi3hdx1204_enable(const int i2c_port,
-		      const uint16_t i2c_addr_flags,
+int pi3hdx1204_enable(const int i2c_port, const uint16_t i2c_addr_flags,
 		      const int enable);
 
 struct pi3hdx1204_tuning {
diff --git a/driver/retimer/ps8802.c b/driver/retimer/ps8802.c
index cb81b84f4e..24ad0f290f 100644
--- a/driver/retimer/ps8802.c
+++ b/driver/retimer/ps8802.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -16,19 +16,19 @@
 #define PS8802_DEBUG 0
 #define PS8802_I2C_WAKE_DELAY 500
 
+#define CPRINTS(format, args...) cprints(CC_USB, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args)
+
 int ps8802_i2c_read(const struct usb_mux *me, int page, int offset, int *data)
 {
 	int rv;
 
-	rv = i2c_read8(me->i2c_port,
-		       me->i2c_addr_flags + page,
-		       offset, data);
+	rv = i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset, data);
 
 	if (PS8802_DEBUG)
 		ccprintf("%s(%d:0x%02X, 0x%02X) =>0x%02X\n", __func__,
-			 me->i2c_port,
-			 me->i2c_addr_flags + page,
-			 offset, *data);
+			 me->i2c_port, me->i2c_addr_flags + page, offset,
+			 *data);
 
 	return rv;
 }
@@ -39,58 +39,43 @@ int ps8802_i2c_write(const struct usb_mux *me, int page, int offset, int data)
 	int pre_val, post_val;
 
 	if (PS8802_DEBUG)
-		i2c_read8(me->i2c_port,
-			me->i2c_addr_flags + page,
-			offset, &pre_val);
+		i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset,
+			  &pre_val);
 
-	rv = i2c_write8(me->i2c_port,
-			me->i2c_addr_flags + page,
-			offset, data);
+	rv = i2c_write8(me->i2c_port, me->i2c_addr_flags + page, offset, data);
 
 	if (PS8802_DEBUG) {
-		i2c_read8(me->i2c_port,
-			me->i2c_addr_flags + page,
-			offset, &post_val);
+		i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset,
+			  &post_val);
 
 		ccprintf("%s(%d:0x%02X, 0x%02X, 0x%02X) "
-			"0x%02X=>0x%02X\n",
-			 __func__,
-			 me->i2c_port,
-			 me->i2c_addr_flags + page,
-			 offset, data,
-			 pre_val, post_val);
+			 "0x%02X=>0x%02X\n",
+			 __func__, me->i2c_port, me->i2c_addr_flags + page,
+			 offset, data, pre_val, post_val);
 	}
 
 	return rv;
 }
 
-int ps8802_i2c_write16(const struct usb_mux *me, int page, int offset,
-		       int data)
+int ps8802_i2c_write16(const struct usb_mux *me, int page, int offset, int data)
 {
 	int rv;
 	int pre_val, post_val;
 
 	if (PS8802_DEBUG)
-		i2c_read16(me->i2c_port,
-			   me->i2c_addr_flags + page,
-			   offset, &pre_val);
+		i2c_read16(me->i2c_port, me->i2c_addr_flags + page, offset,
+			   &pre_val);
 
-	rv = i2c_write16(me->i2c_port,
-			 me->i2c_addr_flags + page,
-			 offset, data);
+	rv = i2c_write16(me->i2c_port, me->i2c_addr_flags + page, offset, data);
 
 	if (PS8802_DEBUG) {
-		i2c_read16(me->i2c_port,
-			   me->i2c_addr_flags + page,
-			   offset, &post_val);
+		i2c_read16(me->i2c_port, me->i2c_addr_flags + page, offset,
+			   &post_val);
 
 		ccprintf("%s(%d:0x%02X, 0x%02X, 0x%04X) "
 			 "0x%04X=>0x%04X\n",
-			 __func__,
-			 me->i2c_port,
-			 me->i2c_addr_flags + page,
-			 offset, data,
-			 pre_val, post_val);
+			 __func__, me->i2c_port, me->i2c_addr_flags + page,
+			 offset, data, pre_val, post_val);
 	}
 
 	return rv;
@@ -103,62 +88,46 @@ int ps8802_i2c_field_update8(const struct usb_mux *me, int page, int offset,
 	int pre_val, post_val;
 
 	if (PS8802_DEBUG)
-		i2c_read8(me->i2c_port,
-			  me->i2c_addr_flags + page,
-			  offset, &pre_val);
+		i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset,
+			  &pre_val);
 
-	rv = i2c_field_update8(me->i2c_port,
-			       me->i2c_addr_flags + page,
-			       offset,
-			       field_mask,
-			       set_value);
+	rv = i2c_field_update8(me->i2c_port, me->i2c_addr_flags + page, offset,
+			       field_mask, set_value);
 
 	if (PS8802_DEBUG) {
-		i2c_read8(me->i2c_port,
-			  me->i2c_addr_flags + page,
-			  offset, &post_val);
+		i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset,
+			  &post_val);
 
 		ccprintf("%s(%d:0x%02X, 0x%02X, 0x%02X, 0x%02X) "
 			 "0x%02X=>0x%02X\n",
-			 __func__,
-			 me->i2c_port,
-			 me->i2c_addr_flags + page,
-			 offset, field_mask, set_value,
-			 pre_val, post_val);
+			 __func__, me->i2c_port, me->i2c_addr_flags + page,
+			 offset, field_mask, set_value, pre_val, post_val);
 	}
 
 	return rv;
 }
 
 int ps8802_i2c_field_update16(const struct usb_mux *me, int page, int offset,
-			     uint16_t field_mask, uint16_t set_value)
+			      uint16_t field_mask, uint16_t set_value)
 {
 	int rv;
 	int pre_val, post_val;
 
 	if (PS8802_DEBUG)
-		i2c_read16(me->i2c_port,
-			   me->i2c_addr_flags + page,
-			   offset, &pre_val);
+		i2c_read16(me->i2c_port, me->i2c_addr_flags + page, offset,
+			   &pre_val);
 
-	rv = i2c_field_update16(me->i2c_port,
-				me->i2c_addr_flags + page,
-				offset,
-				field_mask,
-				set_value);
+	rv = i2c_field_update16(me->i2c_port, me->i2c_addr_flags + page, offset,
+				field_mask, set_value);
 
 	if (PS8802_DEBUG) {
-		i2c_read16(me->i2c_port,
-			   me->i2c_addr_flags + page,
-			   offset, &post_val);
+		i2c_read16(me->i2c_port, me->i2c_addr_flags + page, offset,
+			   &post_val);
 
 		ccprintf("%s(%d:0x%02X, 0x%02X, 0x%02X, 0x%04X) "
 			 "0x%04X=>0x%04X\n",
-			 __func__,
-			 me->i2c_port,
-			 me->i2c_addr_flags + page,
-			 offset, field_mask, set_value,
-			 pre_val, post_val);
+			 __func__, me->i2c_port, me->i2c_addr_flags + page,
+			 offset, field_mask, set_value, pre_val, post_val);
 	}
 
 	return rv;
@@ -176,9 +145,7 @@ int ps8802_i2c_wake(const struct usb_mux *me)
 
 	/* If in standby, first read will fail, second should succeed. */
 	for (int i = 0; i < 2; i++) {
-		rv = ps8802_i2c_read(me,
-				     PS8802_REG_PAGE2,
-				     PS8802_REG2_MODE,
+		rv = ps8802_i2c_read(me, PS8802_REG_PAGE2, PS8802_REG2_MODE,
 				     &data);
 		if (rv == EC_SUCCESS)
 			return rv;
@@ -189,19 +156,45 @@ int ps8802_i2c_wake(const struct usb_mux *me)
 	return rv;
 }
 
+/*
+ * Setting operation mode to standby mode
+ */
+static int ps8802_enter_low_power_mode(const struct usb_mux *me)
+{
+	int rv;
+
+	rv = ps8802_i2c_write(me, PS8802_REG_PAGE2, PS8802_REG2_MODE,
+			      PS8802_MODE_STANDBY_MODE);
+
+	if (rv)
+		CPRINTS("C%d: PS8802: Failed to enter low power mode!",
+			me->usb_port);
+
+	return rv;
+}
+
 static int ps8802_init(const struct usb_mux *me)
 {
+	ps8802_enter_low_power_mode(me);
 	return EC_SUCCESS;
 }
 
-static int ps8802_set_mux(const struct usb_mux *me, mux_state_t mux_state)
+static int ps8802_set_mux(const struct usb_mux *me, mux_state_t mux_state,
+			  bool *ack_required)
 {
 	int val;
 	int rv;
 
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
+	/* This driver treats safe mode as none */
+	if (mux_state & USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
+
 	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
-		return (mux_state == USB_PD_MUX_NONE) ? EC_SUCCESS
-						      : EC_ERROR_NOT_POWERED;
+		return (mux_state == USB_PD_MUX_NONE) ? EC_SUCCESS :
+							EC_ERROR_NOT_POWERED;
 
 	/* Make sure the PS8802 is awake */
 	rv = ps8802_i2c_wake(me);
@@ -209,18 +202,16 @@ static int ps8802_set_mux(const struct usb_mux *me, mux_state_t mux_state)
 		return rv;
 
 	if (PS8802_DEBUG)
-		ccprintf("%s(%d, 0x%02X) %s %s %s\n",
-			 __func__, me->usb_port, mux_state,
-			 (mux_state & USB_PD_MUX_USB_ENABLED)	? "USB" : "",
-			 (mux_state & USB_PD_MUX_DP_ENABLED)	? "DP" : "",
-			 (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-								? "FLIP" : "");
+		ccprintf("%s(%d, 0x%02X) %s %s %s\n", __func__, me->usb_port,
+			 mux_state,
+			 (mux_state & USB_PD_MUX_USB_ENABLED) ? "USB" : "",
+			 (mux_state & USB_PD_MUX_DP_ENABLED) ? "DP" : "",
+			 (mux_state & USB_PD_MUX_POLARITY_INVERTED) ? "FLIP" :
+								      "");
 
 	/* Set the mode and flip */
-	val = (PS8802_MODE_DP_REG_CONTROL |
-	       PS8802_MODE_USB_REG_CONTROL |
-	       PS8802_MODE_FLIP_REG_CONTROL |
-	       PS8802_MODE_IN_HPD_REG_CONTROL);
+	val = (PS8802_MODE_DP_REG_CONTROL | PS8802_MODE_USB_REG_CONTROL |
+	       PS8802_MODE_FLIP_REG_CONTROL | PS8802_MODE_IN_HPD_REG_CONTROL);
 
 	if (mux_state & USB_PD_MUX_USB_ENABLED)
 		val |= PS8802_MODE_USB_ENABLE;
@@ -229,10 +220,7 @@ static int ps8802_set_mux(const struct usb_mux *me, mux_state_t mux_state)
 	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
 		val |= PS8802_MODE_FLIP_ENABLE;
 
-	rv = ps8802_i2c_write(me,
-			      PS8802_REG_PAGE2,
-			      PS8802_REG2_MODE,
-			      val);
+	rv = ps8802_i2c_write(me, PS8802_REG_PAGE2, PS8802_REG2_MODE, val);
 
 	return rv;
 }
@@ -251,10 +239,7 @@ static int ps8802_get_mux(const struct usb_mux *me, mux_state_t *mux_state)
 	if (rv)
 		return rv;
 
-	rv = ps8802_i2c_read(me,
-			     PS8802_REG_PAGE2,
-			     PS8802_REG2_MODE,
-			     &val);
+	rv = ps8802_i2c_read(me, PS8802_REG_PAGE2, PS8802_REG2_MODE, &val);
 	if (rv)
 		return rv;
 
@@ -272,4 +257,20 @@ const struct usb_mux_driver ps8802_usb_mux_driver = {
 	.init = ps8802_init,
 	.set = ps8802_set_mux,
 	.get = ps8802_get_mux,
+	.enter_low_power_mode = &ps8802_enter_low_power_mode,
 };
+
+/*
+ * If PS8802 I2c address was conflicted, change
+ * the I2c address in page 0x0A, offset 0xB0
+ * switch to 0x50 8-bit address
+ */
+int ps8802_chg_i2c_addr(int i2c_port)
+{
+	int rv;
+
+	rv = i2c_write8(i2c_port, PS8802_P1_ADDR, PS8802_ADDR_CFG,
+			PS8802_I2C_ADDR_FLAGS_ALT);
+
+	return rv;
+}
diff --git a/driver/retimer/ps8802.h b/driver/retimer/ps8802.h
index bdcf44dea8..b8a51de62d 100644
--- a/driver/retimer/ps8802.h
+++ b/driver/retimer/ps8802.h
@@ -1,8 +1,8 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
- * PS8802 retimer.
+ * PS8802/PS8762 retimer.
  */
 #include "usb_mux.h"
 
@@ -13,57 +13,94 @@
  * PS8802 uses 7-bit I2C addresses 0x08 to 0x17 (ADDR=L).
  * Page 0 = 0x08, Page 1 = 0x09, Page 2 = 0x0A.
  */
-#define PS8802_I2C_ADDR_FLAGS	0x08
+#define PS8802_I2C_ADDR_FLAGS 0x08
+
+/*
+ * PS8802 uses 7-bit I2C addresses 0x28 to 0x37.
+ * Page 0 = 0x028, Page 1 = 0x29, Page 2 = 0x2A.
+ */
+#define PS8802_I2C_ADDR_FLAGS_CUSTOM 0x28
 
 /*
  * PAGE 0 Register Definitions
  */
-#define PS8802_REG_PAGE0	0x00
+#define PS8802_REG_PAGE0 0x00
+
+#define PS8802_REG0_TX_STATUS 0x72
+#define PS8802_REG0_RX_STATUS 0x76
+#define PS8802_STATUS_NORMAL_OPERATION BIT(7)
+#define PS8802_STATUS_10_GBPS BIT(5)
+
+/*
+ * PAGE 1 Register Definitions
+ */
+#define PS8802_REG_PAGE1 0x01
 
-#define PS8802_REG0_TX_STATUS		0x72
-#define PS8802_REG0_RX_STATUS		0x76
-#define PS8802_STATUS_NORMAL_OPERATION		BIT(7)
-#define PS8802_STATUS_10_GBPS			BIT(5)
+#define PS8802_800MV_LEVEL_TUNING 0x8A
+#define PS8802_EXTRA_SWING_LEVEL_P0_DEFAULT 0X00
+#define PS8802_EXTRA_SWING_LEVEL_P0_DOWN_1 0X01
+#define PS8802_EXTRA_SWING_LEVEL_P0_DOWN_2 0X02
+#define PS8802_EXTRA_SWING_LEVEL_P0_DOWN_3 0X03
+#define PS8802_EXTRA_SWING_LEVEL_P0_DOWN_4 0X04
+#define PS8802_EXTRA_SWING_LEVEL_P0_UP_1 0X05
+#define PS8802_EXTRA_SWING_LEVEL_P0_UP_2 0X06
+#define PS8802_EXTRA_SWING_LEVEL_P0_UP_3 0X07
+#define PS8802_EXTRA_SWING_LEVEL_P0_MASK 0X07
+
+#define PS8802_REG_DCIRX 0x4B
+#define PS8802_AUTO_DCI_MODE_DISABLE BIT(7)
+#define PS8802_FORCE_DCI_MODE BIT(6)
 
 /*
  * PAGE 2 Register Definitions
  */
-#define PS8802_REG_PAGE2	0x02
-
-#define PS8802_REG2_USB_SSEQ_LEVEL	0x02
-#define PS8802_REG2_USB_CEQ_LEVEL	0x04
-#define PS8802_USBEQ_LEVEL_UP_12DB		(0x0000 | 0x0003)
-#define PS8802_USBEQ_LEVEL_UP_13DB		(0x0400 | 0x0007)
-#define PS8802_USBEQ_LEVEL_UP_16DB		(0x0C00 | 0x000F)
-#define PS8802_USBEQ_LEVEL_UP_17DB		(0x1C00 | 0x001F)
-#define PS8802_USBEQ_LEVEL_UP_18DB		(0x3C00 | 0x003F)
-#define PS8802_USBEQ_LEVEL_UP_19DB		(0x7C00 | 0x007F)
-#define PS8802_USBEQ_LEVEL_UP_20DB		(0xFC00 | 0x00FF)
-#define PS8802_USBEQ_LEVEL_UP_23DB		(0xFD00 | 0x01FF)
-#define PS8802_USBEQ_LEVEL_UP_MASK		0xFDFF
-
-#define PS8802_REG2_MODE		0x06
-#define PS8802_MODE_DP_REG_CONTROL		BIT(7)
-#define PS8802_MODE_DP_ENABLE			BIT(6)
-#define PS8802_MODE_USB_REG_CONTROL		BIT(5)
-#define PS8802_MODE_USB_ENABLE			BIT(4)
-#define PS8802_MODE_FLIP_REG_CONTROL		BIT(3)
-#define PS8802_MODE_FLIP_ENABLE			BIT(2)
-#define PS8802_MODE_IN_HPD_REG_CONTROL		BIT(1)
-#define PS8802_MODE_IN_HPD_ENABLE		BIT(0)
-
-#define PS8802_REG2_DPEQ_LEVEL		0x07
-#define PS8802_DPEQ_LEVEL_UP_9DB		0x00
-#define PS8802_DPEQ_LEVEL_UP_11DB		0x01
-#define PS8802_DPEQ_LEVEL_UP_12DB		0x02
-#define PS8802_DPEQ_LEVEL_UP_14DB		0x03
-#define PS8802_DPEQ_LEVEL_UP_17DB		0x04
-#define PS8802_DPEQ_LEVEL_UP_18DB		0x05
-#define PS8802_DPEQ_LEVEL_UP_19DB		0x06
-#define PS8802_DPEQ_LEVEL_UP_20DB		0x07
-#define PS8802_DPEQ_LEVEL_UP_21DB		0x08
-#define PS8802_DPEQ_LEVEL_UP_MASK		0x0F
+#define PS8802_REG_PAGE2 0x02
+
+#define PS8802_REG2_USB_SSEQ_LEVEL 0x02
+#define PS8802_REG2_USB_CEQ_LEVEL 0x04
+#define PS8802_USBEQ_LEVEL_UP_12DB (0x0000 | 0x0003)
+#define PS8802_USBEQ_LEVEL_UP_13DB (0x0400 | 0x0007)
+#define PS8802_USBEQ_LEVEL_UP_16DB (0x0C00 | 0x000F)
+#define PS8802_USBEQ_LEVEL_UP_17DB (0x1C00 | 0x001F)
+#define PS8802_USBEQ_LEVEL_UP_18DB (0x3C00 | 0x003F)
+#define PS8802_USBEQ_LEVEL_UP_19DB (0x7C00 | 0x007F)
+#define PS8802_USBEQ_LEVEL_UP_20DB (0xFC00 | 0x00FF)
+#define PS8802_USBEQ_LEVEL_UP_23DB (0xFD00 | 0x01FF)
+#define PS8802_USBEQ_LEVEL_UP_MASK 0xFDFF
+
+#define PS8802_REG2_MODE 0x06
+#define PS8802_MODE_DP_REG_CONTROL BIT(7)
+#define PS8802_MODE_DP_ENABLE BIT(6)
+#define PS8802_MODE_USB_REG_CONTROL BIT(5)
+#define PS8802_MODE_USB_ENABLE BIT(4)
+#define PS8802_MODE_FLIP_REG_CONTROL BIT(3)
+#define PS8802_MODE_FLIP_ENABLE BIT(2)
+#define PS8802_MODE_IN_HPD_REG_CONTROL BIT(1)
+#define PS8802_MODE_IN_HPD_ENABLE BIT(0)
+
+/*
+ * Support power saving mode, Bit7 Disable
+ * CE_DP, Bit5 Disable CE_USB, Bit3 Disable
+ * FLIP pin, Bit1 Display IN_HPD pin, [Bit6 Bit4]
+ * 00: I2C standy by mode.
+ */
+#define PS8802_MODE_STANDBY_MODE 0xAA
+
+#define PS8802_REG2_DPEQ_LEVEL 0x07
+#define PS8802_DPEQ_LEVEL_UP_9DB 0x00
+#define PS8802_DPEQ_LEVEL_UP_11DB 0x01
+#define PS8802_DPEQ_LEVEL_UP_12DB 0x02
+#define PS8802_DPEQ_LEVEL_UP_14DB 0x03
+#define PS8802_DPEQ_LEVEL_UP_17DB 0x04
+#define PS8802_DPEQ_LEVEL_UP_18DB 0x05
+#define PS8802_DPEQ_LEVEL_UP_19DB 0x06
+#define PS8802_DPEQ_LEVEL_UP_20DB 0x07
+#define PS8802_DPEQ_LEVEL_UP_21DB 0x08
+#define PS8802_DPEQ_LEVEL_UP_MASK 0x0F
 
+#define PS8802_P1_ADDR 0x0A
+#define PS8802_ADDR_CFG 0xB0
+#define PS8802_I2C_ADDR_FLAGS_ALT 0x50
 
 extern const struct usb_mux_driver ps8802_usb_mux_driver;
 
@@ -71,10 +108,11 @@ int ps8802_i2c_wake(const struct usb_mux *me);
 int ps8802_i2c_read(const struct usb_mux *me, int page, int offset, int *data);
 int ps8802_i2c_write(const struct usb_mux *me, int page, int offset, int data);
 int ps8802_i2c_write16(const struct usb_mux *me, int page, int offset,
-			int data);
+		       int data);
 int ps8802_i2c_field_update8(const struct usb_mux *me, int page, int offset,
 			     uint8_t field_mask, uint8_t set_value);
 int ps8802_i2c_field_update16(const struct usb_mux *me, int page, int offset,
-			     uint16_t field_mask, uint16_t set_value);
+			      uint16_t field_mask, uint16_t set_value);
+int ps8802_chg_i2c_addr(int i2c_port);
 
 #endif /* __CROS_EC_USB_RETIMER_PS8802_H */
diff --git a/driver/retimer/ps8811.c b/driver/retimer/ps8811.c
new file mode 100644
index 0000000000..aadcbc9f6c
--- /dev/null
+++ b/driver/retimer/ps8811.c
@@ -0,0 +1,41 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * PS8811 retimer.
+ */
+
+#include "common.h"
+#include "console.h"
+#include "i2c.h"
+#include "ps8811.h"
+#include "usb_mux.h"
+
+int ps8811_i2c_read(const struct usb_mux *me, int page, int offset, int *data)
+{
+	int rv;
+
+	rv = i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset, data);
+
+	return rv;
+}
+
+int ps8811_i2c_write(const struct usb_mux *me, int page, int offset, int data)
+{
+	int rv;
+
+	rv = i2c_write8(me->i2c_port, me->i2c_addr_flags + page, offset, data);
+
+	return rv;
+}
+
+int ps8811_i2c_field_update(const struct usb_mux *me, int page, int offset,
+			    uint8_t field_mask, uint8_t set_value)
+{
+	int rv;
+
+	rv = i2c_field_update8(me->i2c_port, me->i2c_addr_flags + page, offset,
+			       field_mask, set_value);
+
+	return rv;
+}
diff --git a/driver/retimer/ps8811.h b/driver/retimer/ps8811.h
index 13a83c045d..5f196de870 100644
--- a/driver/retimer/ps8811.h
+++ b/driver/retimer/ps8811.h
@@ -1,50 +1,200 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * PS8811 retimer.
  */
 
+#include "usb_mux.h"
+
 #ifndef __CROS_EC_USB_RETIMER_PS8811_H
 #define __CROS_EC_USB_RETIMER_PS8811_H
 
 /*
+ * PS8811 uses 7-bit I2C addresses 0x28 to 0x29 (ADDR=LL).
+ * Page 0 = 0x28, Page 1 = 0x29.
+ * PS8811 uses 7-bit I2C addresses 0x2A to 0x2B (ADDR=LH).
+ * Page 0 = 0x2A, Page 1 = 0x2B.
+ * PS8811 uses 7-bit I2C addresses 0x70 to 0x71 (ADDR=HL).
+ * Page 0 = 0x70, Page 1 = 0x71.
  * PS8811 uses 7-bit I2C addresses 0x72 to 0x73 (ADDR=HH).
  * Page 0 = 0x72, Page 1 = 0x73.
  */
-#define PS8811_I2C_ADDR_FLAGS	0x72
+#define PS8811_I2C_ADDR_FLAGS0 0x28
+#define PS8811_I2C_ADDR_FLAGS1 0x2A
+#define PS8811_I2C_ADDR_FLAGS2 0x70
+#define PS8811_I2C_ADDR_FLAGS3 0x72
+
+/*
+ * PAGE 0 Register Definitions
+ */
+#define PS8811_REG_PAGE0 0x00
 
 /*
  * PAGE 1 Register Definitions
  */
-#define PS8811_REG_PAGE1	0x01
-
-#define PS8811_REG1_USB_BEQ_LEVEL	0x05
-#define PS8811_BEQ_PIN_LEVEL_UP_9DB		0x00
-#define PS8811_BEQ_PIN_LEVEL_UP_10_5DB		0x01
-#define PS8811_BEQ_PIN_LEVEL_UP_12DB		0x02
-#define PS8811_BEQ_PIN_LEVEL_UP_13DB		0x03
-#define PS8811_BEQ_PIN_LEVEL_UP_16DB		0x04
-#define PS8811_BEQ_PIN_LEVEL_UP_17DB		0x05
-#define PS8811_BEQ_PIN_LEVEL_UP_18DB		0x06
-#define PS8811_BEQ_PIN_LEVEL_UP_19DB		0x07
-#define PS8811_BEQ_PIN_LEVEL_UP_20DB		0x08
-#define PS8811_BEQ_PIN_LEVEL_UP_21DB		0x09
-#define PS8811_BEQ_PIN_LEVEL_UP_23DB		0x0A
-#define PS8811_BEQ_I2C_LEVEL_UP_9DB		0x00
-#define PS8811_BEQ_I2C_LEVEL_UP_10_5DB		0x10
-#define PS8811_BEQ_I2C_LEVEL_UP_12DB		0x20
-#define PS8811_BEQ_I2C_LEVEL_UP_13DB		0x30
-#define PS8811_BEQ_I2C_LEVEL_UP_16DB		0x40
-#define PS8811_BEQ_I2C_LEVEL_UP_17DB		0x50
-#define PS8811_BEQ_I2C_LEVEL_UP_18DB		0x60
-#define PS8811_BEQ_I2C_LEVEL_UP_19DB		0x70
-#define PS8811_BEQ_I2C_LEVEL_UP_20DB		0x80
-#define PS8811_BEQ_I2C_LEVEL_UP_21DB		0x90
-#define PS8811_BEQ_I2C_LEVEL_UP_23DB		0xA0
-
-#define PS8811_REG1_USB_BEQ_CONFIG	0x06
-#define PS8811_BEQ_CONFIG_REG_ENABLE		BIT(0)
+#define PS8811_REG_PAGE1 0x01
+
+#define PS8811_REG1_USB_AEQ_LEVEL 0x01
+#define PS8811_AEQ_PIN_LEVEL_UP_CONFIG_MASK GENMASK(3, 0)
+#define PS8811_AEQ_PIN_LEVEL_UP_SHIFT 0
+#define PS8811_AEQ_PIN_LEVEL_UP_9DB 0x00
+#define PS8811_AEQ_PIN_LEVEL_UP_10P5DB 0x01
+#define PS8811_AEQ_PIN_LEVEL_UP_12DB 0x02
+#define PS8811_AEQ_PIN_LEVEL_UP_13DB 0x03
+#define PS8811_AEQ_PIN_LEVEL_UP_16DB 0x04
+#define PS8811_AEQ_PIN_LEVEL_UP_17DB 0x05
+#define PS8811_AEQ_PIN_LEVEL_UP_18DB 0x06
+#define PS8811_AEQ_PIN_LEVEL_UP_19DB 0x07
+#define PS8811_AEQ_PIN_LEVEL_UP_20DB 0x08
+#define PS8811_AEQ_PIN_LEVEL_UP_21DB 0x09
+#define PS8811_AEQ_PIN_LEVEL_UP_23DB 0x0A
+#define PS8811_AEQ_I2C_LEVEL_UP_CONFIG_MASK GENMASK(7, 4)
+#define PS8811_AEQ_I2C_LEVEL_UP_SHIFT 4
+#define PS8811_AEQ_I2C_LEVEL_UP_9DB 0x00
+#define PS8811_AEQ_I2C_LEVEL_UP_10P5DB 0x01
+#define PS8811_AEQ_I2C_LEVEL_UP_12DB 0x02
+#define PS8811_AEQ_I2C_LEVEL_UP_13DB 0x03
+#define PS8811_AEQ_I2C_LEVEL_UP_16DB 0x04
+#define PS8811_AEQ_I2C_LEVEL_UP_17DB 0x05
+#define PS8811_AEQ_I2C_LEVEL_UP_18DB 0x06
+#define PS8811_AEQ_I2C_LEVEL_UP_19DB 0x07
+#define PS8811_AEQ_I2C_LEVEL_UP_20DB 0x08
+#define PS8811_AEQ_I2C_LEVEL_UP_21DB 0x09
+#define PS8811_AEQ_I2C_LEVEL_UP_23DB 0x0A
+
+#define PS8811_REG1_USB_ADE_CONFIG 0x02
+#define PS8811_AEQ_CONFIG_REG_ENABLE BIT(0)
+#define PS8811_AEQ_ADAPTIVE_REG_ENABLE BIT(1)
+#define PS8811_ADE_PIN_MID_LEVEL_CONFIG_MASK GENMASK(7, 5)
+#define PS8811_ADE_PIN_MID_LEVEL_SHIFT 5
+#define PS8811_ADE_PIN_MID_LEVEL_0P5DB 0x00
+#define PS8811_ADE_PIN_MID_LEVEL_1P5DB 0x01
+#define PS8811_ADE_PIN_MID_LEVEL_2DB 0x02
+#define PS8811_ADE_PIN_MID_LEVEL_3DB 0x03
+#define PS8811_ADE_PIN_MID_LEVEL_3P5DB 0x04
+#define PS8811_ADE_PIN_MID_LEVEL_4P5DB 0x05
+#define PS8811_ADE_PIN_MID_LEVEL_6DB 0x06
+#define PS8811_ADE_PIN_MID_LEVEL_7P5DB 0x07
+#define PS8811_ADE_PIN_LOW_LEVEL_CONFIG_MASK GENMASK(4, 2)
+#define PS8811_ADE_PIN_LOW_LEVEL_SHIFT 2
+#define PS8811_ADE_PIN_LOW_LEVEL_0P5DB 0x00
+#define PS8811_ADE_PIN_LOW_LEVEL_1P5DB 0x01
+#define PS8811_ADE_PIN_LOW_LEVEL_2DB 0x02
+#define PS8811_ADE_PIN_LOW_LEVEL_3DB 0x03
+#define PS8811_ADE_PIN_LOW_LEVEL_3P5DB 0x04
+#define PS8811_ADE_PIN_LOW_LEVEL_4P5DB 0x05
+#define PS8811_ADE_PIN_LOW_LEVEL_6DB 0x06
+#define PS8811_ADE_PIN_LOW_LEVEL_7P5DB 0x07
+
+#define PS8811_REG1_USB_BEQ_LEVEL 0x05
+#define PS8811_BEQ_PIN_LEVEL_UP_CONFIG_MASK GENMASK(3, 0)
+#define PS8811_BEQ_PIN_LEVEL_UP_SHIFT 0
+#define PS8811_BEQ_PIN_LEVEL_UP_9DB 0x00
+#define PS8811_BEQ_PIN_LEVEL_UP_10P5DB 0x01
+#define PS8811_BEQ_PIN_LEVEL_UP_12DB 0x02
+#define PS8811_BEQ_PIN_LEVEL_UP_13DB 0x03
+#define PS8811_BEQ_PIN_LEVEL_UP_16DB 0x04
+#define PS8811_BEQ_PIN_LEVEL_UP_17DB 0x05
+#define PS8811_BEQ_PIN_LEVEL_UP_18DB 0x06
+#define PS8811_BEQ_PIN_LEVEL_UP_19DB 0x07
+#define PS8811_BEQ_PIN_LEVEL_UP_20DB 0x08
+#define PS8811_BEQ_PIN_LEVEL_UP_21DB 0x09
+#define PS8811_BEQ_PIN_LEVEL_UP_23DB 0x0A
+#define PS8811_BEQ_I2C_LEVEL_UP_CONFIG_MASK GENMASK(7, 4)
+#define PS8811_BEQ_I2C_LEVEL_UP_SHIFT 4
+#define PS8811_BEQ_I2C_LEVEL_UP_9DB 0x00
+#define PS8811_BEQ_I2C_LEVEL_UP_10P5DB 0x01
+#define PS8811_BEQ_I2C_LEVEL_UP_12DB 0x02
+#define PS8811_BEQ_I2C_LEVEL_UP_13DB 0x03
+#define PS8811_BEQ_I2C_LEVEL_UP_16DB 0x04
+#define PS8811_BEQ_I2C_LEVEL_UP_17DB 0x05
+#define PS8811_BEQ_I2C_LEVEL_UP_18DB 0x06
+#define PS8811_BEQ_I2C_LEVEL_UP_19DB 0x07
+#define PS8811_BEQ_I2C_LEVEL_UP_20DB 0x08
+#define PS8811_BEQ_I2C_LEVEL_UP_21DB 0x09
+#define PS8811_BEQ_I2C_LEVEL_UP_23DB 0x0A
+
+#define PS8811_REG1_USB_BDE_CONFIG 0x06
+#define PS8811_BEQ_CONFIG_REG_ENABLE BIT(0)
+#define PS8811_BEQ_ADAPTIVE_REG_ENABLE BIT(1)
+#define PS8811_BDE_PIN_MID_LEVEL_CONFIG_MASK GENMASK(7, 5)
+#define PS8811_BDE_PIN_MID_LEVEL_SHIFT 5
+#define PS8811_BDE_PIN_MID_LEVEL_0P5DB 0x00
+#define PS8811_BDE_PIN_MID_LEVEL_1P5DB 0x01
+#define PS8811_BDE_PIN_MID_LEVEL_2DB 0x02
+#define PS8811_BDE_PIN_MID_LEVEL_3DB 0x03
+#define PS8811_BDE_PIN_MID_LEVEL_3P5DB 0x04
+#define PS8811_BDE_PIN_MID_LEVEL_4P5DB 0x05
+#define PS8811_BDE_PIN_MID_LEVEL_6DB 0x06
+#define PS8811_BDE_PIN_MID_LEVEL_7P5DB 0x07
+#define PS8811_BDE_PIN_LOW_LEVEL_CONFIG_MASK GENMASK(4, 2)
+#define PS8811_BDE_PIN_LOW_LEVEL_SHIFT 2
+#define PS8811_BDE_PIN_LOW_LEVEL_0P5DB 0x00
+#define PS8811_BDE_PIN_LOW_LEVEL_1P5DB 0x01
+#define PS8811_BDE_PIN_LOW_LEVEL_2DB 0x02
+#define PS8811_BDE_PIN_LOW_LEVEL_3DB 0x03
+#define PS8811_BDE_PIN_LOW_LEVEL_3P5DB 0x04
+#define PS8811_BDE_PIN_LOW_LEVEL_4P5DB 0x05
+#define PS8811_BDE_PIN_LOW_LEVEL_6DB 0x06
+#define PS8811_BDE_PIN_LOW_LEVEL_7P5DB 0x07
+
+#define PS8811_REG1_USB_CHAN_A_SWING 0x66
+#define PS8811_CHAN_A_SWING_MASK GENMASK(6, 4)
+#define PS8811_CHAN_A_SWING_SHIFT 4
+
+#define PS8811_REG1_50OHM_ADJUST_CHAN_B 0x73
+#define PS8811_50OHM_ADJUST_CHAN_B_CONFIG_MASK GENMASK(3, 1)
+#define PS8811_50OHM_ADJUST_CHAN_B_SHIFT 1
+#define PS8811_50OHM_ADJUST_CHAN_B_DEFAULT 0x00
+#define PS8811_50OHM_ADJUST_CHAN_B_MINUS_6PCT 0x01
+#define PS8811_50OHM_ADJUST_CHAN_B_MINUS_9PCT 0x02
+#define PS8811_50OHM_ADJUST_CHAN_B_MINUS_14PCT 0x03
+#define PS8811_50OHM_ADJUST_CHAN_B_PLUS_7PCT 0x04
+#define PS8811_50OHM_ADJUST_CHAN_B_PLUS_11PCT 0x05
+#define PS8811_50OHM_ADJUST_CHAN_B_PLUS_20PCT 0x06
+
+#define PS8811_BDE_PIN_MID_LEVEL_1P5DB 0x01
+#define PS8811_BDE_PIN_MID_LEVEL_2DB 0x02
+#define PS8811_BDE_PIN_MID_LEVEL_3DB 0x03
+#define PS8811_BDE_PIN_MID_LEVEL_3P5DB 0x04
+#define PS8811_BDE_PIN_MID_LEVEL_4P5DB 0x05
+#define PS8811_BDE_PIN_MID_LEVEL_6DB 0x06
+#define PS8811_BDE_PIN_MID_LEVEL_7P5DB 0x07
+
+#define PS8811_REG1_USB_CHAN_B_SWING 0xA4
+#define PS8811_CHAN_B_SWING_MASK GENMASK(2, 0)
+#define PS8811_CHAN_B_SWING_SHIFT 0
+
+/* De-emphasis -2.2 dB, Pre-shoot 1.2 dB */
+#define PS8811_CHAN_B_DE_2_2_PS_1_2_LSB 0x1
+#define PS8811_CHAN_B_DE_2_2_PS_1_2_MSB 0x13
+
+/* De-emphasis -3.5 dB, Pre-shoot 0 dB */
+#define PS8811_CHAN_B_DE_3_5_PS_0_LSB 0x0
+#define PS8811_CHAN_B_DE_3_5_PS_0_MSB 0x5
+
+/* De-emphasis -4.5 dB, Pre-shoot 0 dB */
+#define PS8811_CHAN_B_DE_4_5_PS_0_LSB 0x0
+#define PS8811_CHAN_B_DE_4_5_PS_0_MSB 0x6
+
+/* De-emphasis -6 dB, Pre-shoot 1.5 dB */
+#define PS8811_CHAN_B_DE_6_PS_1_5_LSB 0x2
+#define PS8811_CHAN_B_DE_6_PS_1_5_MSB 0x16
+
+/* De-emphasis -6 dB, Pre-shoot 3 dB */
+#define PS8811_CHAN_B_DE_6_PS_3_LSB 0x4
+#define PS8811_CHAN_B_DE_6_PS_3_MSB 0x16
+
+#define PS8811_REG1_USB_CHAN_B_DE_PS_LSB 0xA5
+#define PS8811_CHAN_B_DE_PS_LSB_MASK GENMASK(2, 0)
+
+#define PS8811_REG1_USB_CHAN_B_DE_PS_MSB 0xA6
+#define PS8811_CHAN_B_DE_PS_MSB_MASK GENMASK(5, 0)
 
+int ps8811_i2c_read(const struct usb_mux *me, int page, int offset, int *data);
+int ps8811_i2c_write(const struct usb_mux *me, int page, int offset, int data);
+int ps8811_i2c_field_update(const struct usb_mux *me, int page, int offset,
+			    uint8_t field_mask, uint8_t set_value);
 
 #endif /* __CROS_EC_USB_RETIMER_PS8802_H */
diff --git a/driver/retimer/ps8818.c b/driver/retimer/ps8818.c
index 65abcddd23..1f17146476 100644
--- a/driver/retimer/ps8818.c
+++ b/driver/retimer/ps8818.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,10 +8,10 @@
 #include "chipset.h"
 #include "common.h"
 #include "console.h"
+#include "driver/retimer/ps8818_public.h"
 #include "gpio.h"
 #include "i2c.h"
 #include "ioexpander.h"
-#include "ps8818.h"
 #include "usb_mux.h"
 
 #define PS8818_DEBUG 0
@@ -20,15 +20,12 @@ int ps8818_i2c_read(const struct usb_mux *me, int page, int offset, int *data)
 {
 	int rv;
 
-	rv = i2c_read8(me->i2c_port,
-		       me->i2c_addr_flags + page,
-		       offset, data);
+	rv = i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset, data);
 
 	if (PS8818_DEBUG)
 		ccprintf("%s(%d:0x%02X, 0x%02X) =>0x%02X\n", __func__,
-			 me->usb_port,
-			 me->i2c_addr_flags + page,
-			 offset, *data);
+			 me->usb_port, me->i2c_addr_flags + page, offset,
+			 *data);
 
 	return rv;
 }
@@ -39,26 +36,19 @@ int ps8818_i2c_write(const struct usb_mux *me, int page, int offset, int data)
 	int pre_val, post_val;
 
 	if (PS8818_DEBUG)
-		i2c_read8(me->i2c_port,
-			me->i2c_addr_flags + page,
-			offset, &pre_val);
+		i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset,
+			  &pre_val);
 
-	rv = i2c_write8(me->i2c_port,
-			me->i2c_addr_flags + page,
-			offset, data);
+	rv = i2c_write8(me->i2c_port, me->i2c_addr_flags + page, offset, data);
 
 	if (PS8818_DEBUG) {
-		i2c_read8(me->i2c_port,
-			me->i2c_addr_flags + page,
-			offset, &post_val);
+		i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset,
+			  &post_val);
 
 		ccprintf("%s(%d:0x%02X, 0x%02X, 0x%02X) "
-			"0x%02X=>0x%02X\n",
-			 __func__,
-			 me->usb_port,
-			 me->i2c_addr_flags + page,
-			 offset, data,
-			 pre_val, post_val);
+			 "0x%02X=>0x%02X\n",
+			 __func__, me->usb_port, me->i2c_addr_flags + page,
+			 offset, data, pre_val, post_val);
 	}
 
 	return rv;
@@ -71,49 +61,49 @@ int ps8818_i2c_field_update8(const struct usb_mux *me, int page, int offset,
 	int pre_val, post_val;
 
 	if (PS8818_DEBUG)
-		i2c_read8(me->i2c_port,
-			me->i2c_addr_flags + page,
-			offset, &pre_val);
+		i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset,
+			  &pre_val);
 
-	rv = i2c_field_update8(me->i2c_port,
-			       me->i2c_addr_flags + page,
-			       offset,
-			       field_mask,
-			       set_value);
+	rv = i2c_field_update8(me->i2c_port, me->i2c_addr_flags + page, offset,
+			       field_mask, set_value);
 
 	if (PS8818_DEBUG) {
-		i2c_read8(me->i2c_port,
-			me->i2c_addr_flags + page,
-			offset, &post_val);
+		i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset,
+			  &post_val);
 
 		ccprintf("%s(%d:0x%02X, 0x%02X, 0x%02X, 0x%02X) "
 			 "0x%02X=>0x%02X\n",
-			 __func__,
-			 me->usb_port,
-			 me->i2c_addr_flags + page,
-			 offset, field_mask, set_value,
-			 pre_val, post_val);
+			 __func__, me->usb_port, me->i2c_addr_flags + page,
+			 offset, field_mask, set_value, pre_val, post_val);
 	}
 
 	return rv;
 }
 
-static int ps8818_set_mux(const struct usb_mux *me, mux_state_t mux_state)
+static int ps8818_set_mux(const struct usb_mux *me, mux_state_t mux_state,
+			  bool *ack_required)
 {
 	int rv;
 	int val = 0;
 
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
+	/* This driver treats safe mode as none */
+	if (mux_state & USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
+
 	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
-		return (mux_state == USB_PD_MUX_NONE) ? EC_SUCCESS
-						      : EC_ERROR_NOT_POWERED;
+		return (mux_state == USB_PD_MUX_NONE) ? EC_SUCCESS :
+							EC_ERROR_NOT_POWERED;
 
 	if (PS8818_DEBUG)
-		ccprintf("%s(%d, 0x%02X) %s %s %s\n",
-			 __func__, me->usb_port, mux_state,
-			 (mux_state & USB_PD_MUX_USB_ENABLED)	? "USB" : "",
-			 (mux_state & USB_PD_MUX_DP_ENABLED)	? "DP" : "",
-			 (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-								? "FLIP" : "");
+		ccprintf("%s(%d, 0x%02X) %s %s %s\n", __func__, me->usb_port,
+			 mux_state,
+			 (mux_state & USB_PD_MUX_USB_ENABLED) ? "USB" : "",
+			 (mux_state & USB_PD_MUX_DP_ENABLED) ? "DP" : "",
+			 (mux_state & USB_PD_MUX_POLARITY_INVERTED) ? "FLIP" :
+								      "");
 
 	/* Set the mode */
 	if (mux_state & USB_PD_MUX_USB_ENABLED)
@@ -121,11 +111,8 @@ static int ps8818_set_mux(const struct usb_mux *me, mux_state_t mux_state)
 	if (mux_state & USB_PD_MUX_DP_ENABLED)
 		val |= PS8818_MODE_DP_ENABLE;
 
-	rv = ps8818_i2c_field_update8(me,
-				PS8818_REG_PAGE0,
-				PS8818_REG0_MODE,
-				PS8818_MODE_NON_RESERVED_MASK,
-				val);
+	rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE0, PS8818_REG0_MODE,
+				      PS8818_MODE_NON_RESERVED_MASK, val);
 	if (rv)
 		return rv;
 
@@ -134,11 +121,8 @@ static int ps8818_set_mux(const struct usb_mux *me, mux_state_t mux_state)
 	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
 		val |= PS8818_FLIP_CONFIG;
 
-	rv = ps8818_i2c_field_update8(me,
-				PS8818_REG_PAGE0,
-				PS8818_REG0_FLIP,
-				PS8818_FLIP_NON_RESERVED_MASK,
-				val);
+	rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE0, PS8818_REG0_FLIP,
+				      PS8818_FLIP_NON_RESERVED_MASK, val);
 	if (rv)
 		return rv;
 
@@ -147,11 +131,9 @@ static int ps8818_set_mux(const struct usb_mux *me, mux_state_t mux_state)
 	if (mux_state & USB_PD_MUX_DP_ENABLED)
 		val |= PS8818_DPHPD_PLUGGED;
 
-	rv = ps8818_i2c_field_update8(me,
-				PS8818_REG_PAGE0,
-				PS8818_REG0_DPHPD_CONFIG,
-				PS8818_DPHPD_NON_RESERVED_MASK,
-				val);
+	rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE0,
+				      PS8818_REG0_DPHPD_CONFIG,
+				      PS8818_DPHPD_NON_RESERVED_MASK, val);
 
 	return rv;
 }
diff --git a/driver/retimer/ps8818.h b/driver/retimer/ps8818.h
deleted file mode 100644
index ab7ba211ff..0000000000
--- a/driver/retimer/ps8818.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * PS8818 retimer.
- */
-#include "usb_mux.h"
-
-#ifndef __CROS_EC_USB_RETIMER_PS8818_H
-#define __CROS_EC_USB_RETIMER_PS8818_H
-
-#define PS8818_I2C_ADDR_FLAGS	0x28
-
-/*
- * PAGE 0 Register Definitions
- */
-#define PS8818_REG_PAGE0	0x00
-
-#define PS8818_REG0_FLIP		0x00
-#define PS8818_FLIP_CONFIG			BIT(7)
-#define PS8818_FLIP_NON_RESERVED_MASK		0xE0
-
-#define PS8818_REG0_MODE		0x01
-#define PS8818_MODE_DP_ENABLE			BIT(7)
-#define PS8818_MODE_USB_ENABLE			BIT(6)
-#define PS8818_MODE_NON_RESERVED_MASK		0xC0
-
-#define PS8818_REG0_DPHPD_CONFIG	0x02
-#define PS8818_DPHPD_CONFIG_INHPD_DISABLE	BIT(7)
-#define PS8818_DPHPD_PLUGGED			BIT(6)
-#define PS8818_DPHPD_NON_RESERVED_MASK		0xFC
-
-/*
- * PAGE 1 Register Definitions
- */
-#define PS8818_REG_PAGE1	0x01
-
-#define PS8818_REG1_APTX1EQ_10G_LEVEL	0x00
-#define PS8818_REG1_APTX2EQ_10G_LEVEL	0x02
-#define PS8818_REG1_CRX1EQ_10G_LEVEL	0x08
-#define PS8818_REG1_CRX2EQ_10G_LEVEL	0x0A
-#define PS8818_REG1_APTX1EQ_5G_LEVEL	0x70
-#define PS8818_REG1_APTX2EQ_5G_LEVEL	0x72
-#define PS8818_REG1_CRX1EQ_5G_LEVEL	0x78
-#define PS8818_REG1_CRX2EQ_5G_LEVEL	0x7A
-#define PS8818_EQ_LEVEL_UP_9DB			(0)
-#define PS8818_EQ_LEVEL_UP_10DB			(1)
-#define PS8818_EQ_LEVEL_UP_12DB			(2)
-#define PS8818_EQ_LEVEL_UP_13DB			(3)
-#define PS8818_EQ_LEVEL_UP_16DB			(4)
-#define PS8818_EQ_LEVEL_UP_17DB			(5)
-#define PS8818_EQ_LEVEL_UP_18DB			(6)
-#define PS8818_EQ_LEVEL_UP_19DB			(7)
-#define PS8818_EQ_LEVEL_UP_20DB			(8)
-#define PS8818_EQ_LEVEL_UP_21DB			(9)
-#define PS8818_EQ_LEVEL_UP_MASK			(0x0F)
-
-#define PS8818_REG1_DPEQ_LEVEL		0xB6
-#define PS8818_DPEQ_LEVEL_UP_9DB		(0 << 3)
-#define PS8818_DPEQ_LEVEL_UP_10DB		(1 << 3)
-#define PS8818_DPEQ_LEVEL_UP_12DB		(2 << 3)
-#define PS8818_DPEQ_LEVEL_UP_13DB		(3 << 3)
-#define PS8818_DPEQ_LEVEL_UP_16DB		(4 << 3)
-#define PS8818_DPEQ_LEVEL_UP_17DB		(5 << 3)
-#define PS8818_DPEQ_LEVEL_UP_18DB		(6 << 3)
-#define PS8818_DPEQ_LEVEL_UP_19DB		(7 << 3)
-#define PS8818_DPEQ_LEVEL_UP_20DB		(8 << 3)
-#define PS8818_DPEQ_LEVEL_UP_21DB		(9 << 3)
-#define PS8818_DPEQ_LEVEL_UP_MASK		(0x0F << 3)
-
-/*
- * PAGE 2 Register Definitions
- */
-#define PS8818_REG_PAGE2	0x02
-
-#define PS8818_REG2_TX_STATUS		0x42
-#define PS8818_REG2_RX_STATUS		0x46
-#define PS8818_STATUS_NORMAL_OPERATION		BIT(7)
-#define PS8818_STATUS_10_GBPS			BIT(5)
-
-extern const struct usb_mux_driver ps8818_usb_retimer_driver;
-
-int ps8818_i2c_read(const struct usb_mux *me,
-		    int page, int offset, int *data);
-int ps8818_i2c_write(const struct usb_mux *me,
-		     int page, int offset, int data);
-int ps8818_i2c_field_update8(const struct usb_mux *me,
-			     int page, int offset,
-			     uint8_t field_mask, uint8_t set_value);
-
-#endif /* __CROS_EC_USB_RETIMER_PS8818_H */
diff --git a/driver/retimer/tdp142.c b/driver/retimer/tdp142.c
new file mode 100644
index 0000000000..fb5149da63
--- /dev/null
+++ b/driver/retimer/tdp142.c
@@ -0,0 +1,36 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Texas Instruments TDP142 DisplayPort Linear Redriver
+ */
+
+#include "common.h"
+#include "ec_commands.h"
+#include "i2c.h"
+#include "tdp142.h"
+
+static enum ec_error_list tdp142_write(int offset, int data)
+{
+	return i2c_write8(TDP142_I2C_PORT, TDP142_I2C_ADDR, offset, data);
+}
+
+static enum ec_error_list tdp142_read(int offset, int *regval)
+{
+	return i2c_read8(TDP142_I2C_PORT, TDP142_I2C_ADDR, offset, regval);
+}
+
+enum ec_error_list tdp142_set_ctlsel(enum tdp142_ctlsel selection)
+{
+	int regval;
+	enum ec_error_list rv;
+
+	rv = tdp142_read(TDP142_REG_GENERAL, &regval);
+	if (rv)
+		return rv;
+
+	regval &= ~TDP142_GENERAL_CTLSEL;
+	regval |= selection;
+
+	return tdp142_write(TDP142_REG_GENERAL, regval);
+}
diff --git a/driver/retimer/tdp142.h b/driver/retimer/tdp142.h
new file mode 100644
index 0000000000..abf0e3588c
--- /dev/null
+++ b/driver/retimer/tdp142.h
@@ -0,0 +1,38 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Texas Instruments TDP142 DisplayPort Linear Redriver
+ */
+
+#ifndef __CROS_EC_REDRIVER_TDP142_H
+#define __CROS_EC_REDRIVER_TDP142_H
+
+#include "compile_time_macros.h"
+
+/*
+ * Note: Since DP redrivers do not have a standard EC structure, define a
+ * TDP142_I2C_PORT and TDP142_I2C_ADDR in board.h
+ */
+#define TDP142_I2C_ADDR0 0x44
+#define TDP142_I2C_ADDR1 0x47
+#define TDP142_I2C_ADDR2 0x0C
+#define TDP142_I2C_ADDR3 0x0F
+
+/* Registers */
+#define TDP142_REG_GENERAL 0x0A
+#define TDP142_GENERAL_CTLSEL GENMASK(1, 0)
+#define TDP142_GENERAL_HPDIN_OVRRIDE BIT(3)
+#define TDP142_GENERAL_EQ_OVERRIDE BIT(4)
+#define TDP142_GENERAL_SWAP_HPDIN BIT(5)
+
+enum tdp142_ctlsel {
+	TDP142_CTLSEL_SHUTDOWN,
+	TDP142_CTLSEL_DISABLED,
+	TDP142_CTLSEL_ENABLED,
+};
+
+/* Control redriver enable */
+enum ec_error_list tdp142_set_ctlsel(enum tdp142_ctlsel selection);
+
+#endif /* __CROS_EC_REDRIVER_TDP142_H */
diff --git a/driver/retimer/tusb544.c b/driver/retimer/tusb544.c
index c9e2642651..8bac6cedd6 100644
--- a/driver/retimer/tusb544.c
+++ b/driver/retimer/tusb544.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,16 +10,23 @@
 
 static int tusb544_write(const struct usb_mux *me, int offset, int data)
 {
-	return i2c_write8(me->i2c_port,
-			  me->i2c_addr_flags,
-			  offset, data);
+	return i2c_write8(me->i2c_port, me->i2c_addr_flags, offset, data);
 }
 
 static int tusb544_read(const struct usb_mux *me, int offset, int *data)
 {
-	return i2c_read8(me->i2c_port,
-			 me->i2c_addr_flags,
-			 offset, data);
+	return i2c_read8(me->i2c_port, me->i2c_addr_flags, offset, data);
+}
+
+int tusb544_i2c_field_update8(const struct usb_mux *me, int offset,
+			      uint8_t field_mask, uint8_t set_value)
+{
+	int rv;
+
+	rv = i2c_field_update8(me->i2c_port, me->i2c_addr_flags, offset,
+			       field_mask, set_value);
+
+	return rv;
 }
 
 static int tusb544_enter_low_power_mode(const struct usb_mux *me)
@@ -44,11 +51,19 @@ static int tusb544_init(const struct usb_mux *me)
 	return EC_SUCCESS;
 }
 
-static int tusb544_set_mux(const struct usb_mux *me, mux_state_t mux_state)
+static int tusb544_set_mux(const struct usb_mux *me, mux_state_t mux_state,
+			   bool *ack_required)
 {
 	int reg;
 	int rv;
 
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
+	/* This driver treats safe mode as none */
+	if (mux_state & USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
+
 	if (mux_state == USB_PD_MUX_NONE)
 		return tusb544_enter_low_power_mode(me);
 
@@ -63,6 +78,9 @@ static int tusb544_set_mux(const struct usb_mux *me, mux_state_t mux_state)
 
 	reg &= ~TUSB544_GEN4_CTL_SEL;
 
+	if (IS_ENABLED(CONFIG_TUSB544_EQ_BY_REGISTER))
+		reg |= TUSB544_GEN4_EQ_OVRD;
+
 	if ((mux_state & USB_PD_MUX_USB_ENABLED) &&
 	    (mux_state & USB_PD_MUX_DP_ENABLED)) {
 		reg |= TUSB544_CTL_SEL_DP_USB;
diff --git a/driver/retimer/tusb544.h b/driver/retimer/tusb544.h
index 2c63a159ca..9fe74c5299 100644
--- a/driver/retimer/tusb544.h
+++ b/driver/retimer/tusb544.h
@@ -1,21 +1,62 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * TI TUSB544 USB Type-C Multi-Protocol Linear Redriver
  */
+#include "usb_mux.h"
 
 #ifndef __CROS_EC_USB_REDRIVER_TUSB544_H
 #define __CROS_EC_USB_REDRIVER_TUSB544_H
 
 #define TUSB544_I2C_ADDR_FLAGS0 0x44
 
-#define TUSB544_REG_GENERAL4	0x0A
-#define TUSB544_GEN4_CTL_SEL	GENMASK(1, 0)
-#define TUSB544_GEN4_FLIP_SEL	BIT(2)
-#define TUSB544_GEN4_HPDIN	BIT(3)
-#define TUSB544_GEN4_EQ_OVRD	BIT(4)
-#define TUSB544_GEN4_SWAP_SEL	BIT(5)
+#define TUSB544_REG_GENERAL4 0x0A
+#define TUSB544_GEN4_CTL_SEL GENMASK(1, 0)
+#define TUSB544_GEN4_FLIP_SEL BIT(2)
+#define TUSB544_GEN4_HPDIN BIT(3)
+#define TUSB544_GEN4_EQ_OVRD BIT(4)
+#define TUSB544_GEN4_SWAP_SEL BIT(5)
+
+#define TUSB544_REG_DISPLAYPORT_1 0x10
+#define TUSB544_REG_DISPLAYPORT_2 0x11
+#define TUSB544_REG_USB3_1_1 0x20
+#define TUSB544_REG_USB3_1_2 0x21
+#define TUSB544_EQ_RX_DFP_MINUS14_UFP_MINUS33 (0)
+#define TUSB544_EQ_RX_DFP_04_UFP_MINUS15 (1)
+#define TUSB544_EQ_RX_DFP_17_UFP_0 (2)
+#define TUSB544_EQ_RX_DFP_32_UFP_14 (3)
+#define TUSB544_EQ_RX_DFP_41_UFP_24 (4)
+#define TUSB544_EQ_RX_DFP_52_UFP_35 (5)
+#define TUSB544_EQ_RX_DFP_61_UFP_43 (6)
+#define TUSB544_EQ_RX_DFP_69_UFP_52 (7)
+#define TUSB544_EQ_RX_DFP_77_UFP_60 (8)
+#define TUSB544_EQ_RX_DFP_83_UFP_66 (9)
+#define TUSB544_EQ_RX_DFP_88_UFP_72 (10)
+#define TUSB544_EQ_RX_DFP_94_UFP_77 (11)
+#define TUSB544_EQ_RX_DFP_98_UFP_81 (12)
+#define TUSB544_EQ_RX_DFP_103_UFP_86 (13)
+#define TUSB544_EQ_RX_DFP_106_UFP_90 (14)
+#define TUSB544_EQ_RX_DFP_110_UFP_94 (15)
+#define TUSB544_EQ_RX_MASK (0x0F)
+
+#define TUSB544_EQ_TX_DFP_MINUS14_UFP_MINUS33 (0 << 4)
+#define TUSB544_EQ_TX_DFP_04_UFP_MINUS15 (1 << 4)
+#define TUSB544_EQ_TX_DFP_17_UFP_0 (2 << 4)
+#define TUSB544_EQ_TX_DFP_32_UFP_14 (3 << 4)
+#define TUSB544_EQ_TX_DFP_41_UFP_24 (4 << 4)
+#define TUSB544_EQ_TX_DFP_52_UFP_35 (5 << 4)
+#define TUSB544_EQ_TX_DFP_61_UFP_43 (6 << 4)
+#define TUSB544_EQ_TX_DFP_69_UFP_52 (7 << 4)
+#define TUSB544_EQ_TX_DFP_77_UFP_60 (8 << 4)
+#define TUSB544_EQ_TX_DFP_83_UFP_66 (9 << 4)
+#define TUSB544_EQ_TX_DFP_88_UFP_72 (10 << 4)
+#define TUSB544_EQ_TX_DFP_94_UFP_77 (11 << 4)
+#define TUSB544_EQ_TX_DFP_98_UFP_81 (12 << 4)
+#define TUSB544_EQ_TX_DFP_103_UFP_86 (13 << 4)
+#define TUSB544_EQ_TX_DFP_106_UFP_90 (14 << 4)
+#define TUSB544_EQ_TX_DFP_110_UFP_94 (15 << 4)
+#define TUSB544_EQ_TX_MASK (0xF0)
 
 enum tusb544_ct_sel {
 	TUSB544_CTL_SEL_DISABLED,
@@ -24,8 +65,10 @@ enum tusb544_ct_sel {
 	TUSB544_CTL_SEL_DP_USB,
 };
 
-#define TUSB544_REG_GENERAL6	0x0C
-#define TUSB544_GEN6_DIR_SEL	GENMASK(1, 0)
+#define TUSB544_REG_GENERAL6 0x0C
+#define TUSB544_GEN6_DIR_SEL GENMASK(1, 0)
+#define TUSB544_VOD_DCGAIN_SEL GENMASK(5, 2)
+#define TUSB544_VOD_DCGAIN_OVERRIDE BIT(6)
 
 enum tusb544_dir_sel {
 	TUSB544_DIR_SEL_USB_DP_SRC,
@@ -34,18 +77,32 @@ enum tusb544_dir_sel {
 	TUSB544_DIS_SEL_CUSTOM_SNK,
 };
 
+enum tusb544_vod_dcgain_sel {
+	TUSB544_VOD_DCGAIN_SETTING_1,
+	TUSB544_VOD_DCGAIN_SETTING_2,
+	TUSB544_VOD_DCGAIN_SETTING_3,
+	TUSB544_VOD_DCGAIN_SETTING_4,
+	TUSB544_VOD_DCGAIN_SETTING_5,
+	TUSB544_VOD_DCGAIN_SETTING_6,
+	TUSB544_VOD_DCGAIN_SETTING_7,
+	TUSB544_VOD_DCGAIN_SETTING_8,
+};
+
 /*
  * Note: TUSB544 automatically snoops DP lanes to enable, but may be manually
  * directed which lanes to turn on when snoop is disabled
  */
-#define TUSB544_REG_DP4			0x13
-#define TUSB544_DP4_DP0_DISABLE		BIT(0)
-#define TUSB544_DP4_DP1_DISABLE		BIT(1)
-#define TUSB544_DP4_DP2_DISABLE		BIT(2)
-#define TUSB544_DP4_DP3_DISABLE		BIT(3)
-#define TUSB544_DP4_AUX_SBU_OVR		GENMASK(5, 4)
-#define TUSB544_DP4_AUX_SNOOP_DISABLE	BIT(7)
+#define TUSB544_REG_DP4 0x13
+#define TUSB544_DP4_DP0_DISABLE BIT(0)
+#define TUSB544_DP4_DP1_DISABLE BIT(1)
+#define TUSB544_DP4_DP2_DISABLE BIT(2)
+#define TUSB544_DP4_DP3_DISABLE BIT(3)
+#define TUSB544_DP4_AUX_SBU_OVR GENMASK(5, 4)
+#define TUSB544_DP4_AUX_SNOOP_DISABLE BIT(7)
 
 extern const struct usb_mux_driver tusb544_drv;
 
+int tusb544_i2c_field_update8(const struct usb_mux *me, int offset,
+			      uint8_t field_mask, uint8_t set_value);
+
 #endif
diff --git a/driver/sb_rmi.c b/driver/sb_rmi.c
new file mode 100644
index 0000000000..42c914f4ec
--- /dev/null
+++ b/driver/sb_rmi.c
@@ -0,0 +1,410 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* AMD SB-RMI (Side-band Remote Management Interface) Driver */
+
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "i2c.h"
+#include "sb_rmi.h"
+#include "stdbool.h"
+#include "time.h"
+#include "timer.h"
+#include "util.h"
+
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+#include "task.h"
+#endif
+
+/* Console output macros */
+#define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+#ifndef CONFIG_CUSTOMIZED_DESIGN
+#define SB_RMI_MAILBOX_TIMEOUT_MS 200
+#else
+#define SB_RMI_MAILBOX_TIMEOUT_MS 25
+K_MUTEX_DEFINE(sb_rmi_mutex);
+
+#define CLEAR_MUTEX_RETURN_ERROR(fn)	\
+	do {				\
+		int err = (fn);		\
+		if (err != EC_SUCCESS)	\
+			goto error;	\
+	} while (0)
+#endif
+#define SB_RMI_MAILBOX_RETRY_DELAY_MS 5
+
+/**
+ * Write an SB-RMI register
+ */
+static int sb_rmi_write(const int reg, int data)
+{
+	return i2c_write8(I2C_PORT_THERMAL_AP, SB_RMI_I2C_ADDR_FLAGS0, reg,
+			  data);
+}
+
+/**
+ * Read an SB-RMI register
+ */
+static int sb_rmi_read(const int reg, int *data)
+{
+	return i2c_read8(I2C_PORT_THERMAL_AP, SB_RMI_I2C_ADDR_FLAGS0, reg,
+			 data);
+}
+
+/**
+ * Set SB-RMI software interrupt
+ */
+static int sb_rmi_assert_interrupt(bool assert)
+{
+	return sb_rmi_write(SB_RMI_SW_INTR_REG, assert ? 0x1 : 0x0);
+}
+
+/**
+ * Execute a SB-RMI mailbox transaction
+ *
+ * cmd:
+ *	See "SB-RMI Soft Mailbox Message" table in PPR for command id
+ * msg_in:
+ *	Message In buffer
+ * msg_out:
+ *	Message Out buffer
+ */
+#ifndef CONFIG_CUSTOMIZED_DESIGN
+int sb_rmi_mailbox_xfer(int cmd, uint32_t msg_in, uint32_t *msg_out_ptr)
+{
+	/**
+	 * The sequence is as follows:
+	 * 1. The initiator (BMC) indicates that command is to be serviced by
+	 *    firmware by writing 0x80 to SBRMI::InBndMsg_inst7 (SBRMI_x3F).
+	 * This register must be set to 0x80 after reset.
+	 * 2. The initiator (BMC) writes the command to SBRMI::InBndMsg_inst0
+	 *    (SBRMI_x38).
+	 * 3. For write operations or read operations which require additional
+	 *    addressing information as shown in the table above, the initiator
+	 *    (BMC) writes Command Data In[31:0] to SBRMI::InBndMsg_inst[4:1]
+	 *    {SBRMI_x3C(MSB):SBRMI_x39(LSB)}.
+	 * 4. The initiator (BMC) writes 0x01 to SBRMI::SoftwareInterrupt to
+	 *    notify firmware to perform the requested read or write command.
+	 * 5. Firmware reads the message and performs the defined action.
+	 * 6. Firmware writes the original command to outbound message register
+	 *    SBRMI::OutBndMsg_inst0 (SBRMI_x30).
+	 * 7. Firmware will write SBRMI::Status[SwAlertSts]=1 to generate an
+	 *    ALERT (if enabled) to initiator (BMC) to indicate completion of
+	 * the requested command. Firmware must (if applicable) put the message
+	 *    data into the message registers SBRMI::OutBndMsg_inst[4:1]
+	 *    {SBRMI_x34(MSB):SBRMI_x31(LSB)}.
+	 * 8. For a read operation, the initiator (BMC) reads the firmware
+	 *    response Command Data Out[31:0] from SBRMI::OutBndMsg_inst[4:1]
+	 *    {SBRMI_x34(MSB):SBRMI_x31(LSB)}.
+	 * 9. BMC must write 1'b1 to SBRMI::Status[SwAlertSts] to clear the
+	 *     ALERT to initiator (BMC). It is recommended to clear the ALERT
+	 *     upon completion of the current mailbox command.
+	 */
+	int val;
+	bool alerted;
+	timestamp_t start;
+	const int ap_comm_failure_threshold = 2;
+	static int ap_comm_failure_count;
+
+	if (!chipset_in_state(CHIPSET_STATE_ON) || chipset_in_low_power_mode())
+		return EC_ERROR_NOT_POWERED;
+
+	/**
+	 * Step 1: writing 0x80 to SBRMI::InBndMsg_inst7 (SBRMI_x3F) to
+	 *         indicate that command is to be serviced and to make sure
+	 *         SBRMIx40[Software Interrupt] is cleared
+	 */
+	RETURN_ERROR(sb_rmi_write(SB_RMI_IN_BND_MSG7_REG, 0x80));
+	RETURN_ERROR(sb_rmi_assert_interrupt(0));
+
+	/* Step 2: writes the command to SBRMI::InBndMsg_inst0 (SBRMI_x38) */
+	RETURN_ERROR(sb_rmi_write(SB_RMI_IN_BND_MSG0_REG, cmd));
+	/* Step 3: msgIn to {SBRMI_x3C(MSB):SBRMI_x39(LSB)} */
+	RETURN_ERROR(sb_rmi_write(SB_RMI_IN_BND_MSG1_REG, msg_in & 0xFF));
+	RETURN_ERROR(
+		sb_rmi_write(SB_RMI_IN_BND_MSG2_REG, (msg_in >> 8) & 0xFF));
+	RETURN_ERROR(
+		sb_rmi_write(SB_RMI_IN_BND_MSG3_REG, (msg_in >> 16) & 0xFF));
+	RETURN_ERROR(
+		sb_rmi_write(SB_RMI_IN_BND_MSG4_REG, (msg_in >> 24) & 0xFF));
+
+	/**
+	 * Step 4: writes 0x01 to SBRMIx40[Software Interrupt] to notify
+	 *         firmware to start service.
+	 */
+	RETURN_ERROR(sb_rmi_assert_interrupt(1));
+
+	/**
+	 * Step 5: SoC do the service
+	 * Step 6: The original command will be copied to SBRMI::OutBndMsg_inst0
+	 *         (SBRMI_x30)
+	 * Step 7: wait SBRMIx02[SwAlertSts] to 1 which indicate the completion
+	 *         of a mailbox operation
+	 */
+	alerted = false;
+	start = get_time();
+	do {
+		if (sb_rmi_read(SB_RMI_STATUS_REG, &val))
+			break;
+		if (val & 0x02) {
+			alerted = true;
+			break;
+		}
+		msleep(SB_RMI_MAILBOX_RETRY_DELAY_MS);
+	} while (time_since32(start) < SB_RMI_MAILBOX_TIMEOUT_MS * MSEC);
+
+	if (!alerted) {
+		/**
+		 * Don't spam the EC logs when the AP is hung. Instead, log the
+		 * first few failures, and then indicate the AP is likely hung.
+		 */
+		if (ap_comm_failure_count < ap_comm_failure_threshold) {
+			CPRINTS("SB-SMI: Mailbox transfer timeout");
+		} else if (ap_comm_failure_count == ap_comm_failure_threshold) {
+			CPRINTS("RMI: The AP is failing to respond despite "
+				"being powered on.");
+		}
+		++ap_comm_failure_count;
+
+		return EC_ERROR_TIMEOUT;
+	}
+
+	RETURN_ERROR(sb_rmi_read(SB_RMI_OUT_BND_MSG0_REG, &val));
+	if (val != cmd) {
+		/**
+		 * Don't spam the EC logs when the AP is hung. Instead, log the
+		 * first few failures, and then indicate the AP is likely hung.
+		 */
+		if (ap_comm_failure_count < ap_comm_failure_threshold) {
+			CPRINTS("RMI: Unexpected command value in out bound "
+				"message");
+		} else if (ap_comm_failure_count == ap_comm_failure_threshold) {
+			CPRINTS("RMI: The AP is failing to respond despite "
+				"being powered on.");
+		}
+		++ap_comm_failure_count;
+
+		return EC_ERROR_UNKNOWN;
+	}
+
+	/**
+	 * This AP communication was successful.
+	 * Reset the count to log the next AP communication failure.
+	 */
+	ap_comm_failure_count = 0;
+
+	/* Step 8: read msgOut from {SBRMI_x34(MSB):SBRMI_x31(LSB)} */
+	*msg_out_ptr = 0;
+	RETURN_ERROR(sb_rmi_read(SB_RMI_OUT_BND_MSG1_REG, &val));
+	*msg_out_ptr |= val;
+	RETURN_ERROR(sb_rmi_read(SB_RMI_OUT_BND_MSG2_REG, &val));
+	*msg_out_ptr |= val << 8;
+	RETURN_ERROR(sb_rmi_read(SB_RMI_OUT_BND_MSG3_REG, &val));
+	*msg_out_ptr |= val << 16;
+	RETURN_ERROR(sb_rmi_read(SB_RMI_OUT_BND_MSG4_REG, &val));
+	*msg_out_ptr |= val << 24;
+
+	/**
+	 * Step 9: BMC must write 1'b1 to SBRMI::Status[SwAlertSts] to clear
+	 *          the ALERT to initiator (BMC). It is recommended to clear the
+	 *          ALERT upon completion of the current mailbox command.
+	 */
+	RETURN_ERROR(sb_rmi_write(SB_RMI_STATUS_REG, 0x2));
+
+	/* Step 10: read the return code from OutBndMsg_inst7 (SBRMI_x37) */
+	RETURN_ERROR(sb_rmi_read(SB_RMI_OUT_BND_MSG7_REG, &val));
+
+	switch (val) {
+	case SB_RMI_MAILBOX_SUCCESS:
+		return EC_SUCCESS;
+	case SB_RMI_MAILBOX_ERROR_ABORTED:
+		return EC_ERROR_UNKNOWN;
+	case SB_RMI_MAILBOX_ERROR_UNKNOWN_CMD:
+		return EC_ERROR_INVAL;
+	case SB_RMI_MAILBOX_ERROR_INVALID_CORE:
+		return EC_ERROR_PARAM1;
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+}
+#else
+int sb_rmi_mailbox_xfer(int cmd, uint32_t msg_in, uint32_t *msg_out_ptr)
+{
+	/**
+	 * The sequence is as follows:
+	 * 1. The initiator (BMC) indicates that command is to be serviced by
+	 *    firmware by writing 0x80 to SBRMI::InBndMsg_inst7 (SBRMI_x3F).
+	 * This register must be set to 0x80 after reset.
+	 * 2. The initiator (BMC) writes the command to SBRMI::InBndMsg_inst0
+	 *    (SBRMI_x38).
+	 * 3. For write operations or read operations which require additional
+	 *    addressing information as shown in the table above, the initiator
+	 *    (BMC) writes Command Data In[31:0] to SBRMI::InBndMsg_inst[4:1]
+	 *    {SBRMI_x3C(MSB):SBRMI_x39(LSB)}.
+	 * 4. The initiator (BMC) writes 0x01 to SBRMI::SoftwareInterrupt to
+	 *    notify firmware to perform the requested read or write command.
+	 * 5. Firmware reads the message and performs the defined action.
+	 * 6. Firmware writes the original command to outbound message register
+	 *    SBRMI::OutBndMsg_inst0 (SBRMI_x30).
+	 * 7. Firmware will write SBRMI::Status[SwAlertSts]=1 to generate an
+	 *    ALERT (if enabled) to initiator (BMC) to indicate completion of
+	 * the requested command. Firmware must (if applicable) put the message
+	 *    data into the message registers SBRMI::OutBndMsg_inst[4:1]
+	 *    {SBRMI_x34(MSB):SBRMI_x31(LSB)}.
+	 * 8. For a read operation, the initiator (BMC) reads the firmware
+	 *    response Command Data Out[31:0] from SBRMI::OutBndMsg_inst[4:1]
+	 *    {SBRMI_x34(MSB):SBRMI_x31(LSB)}.
+	 * 9. BMC must write 1'b1 to SBRMI::Status[SwAlertSts] to clear the
+	 *     ALERT to initiator (BMC). It is recommended to clear the ALERT
+	 *     upon completion of the current mailbox command.
+	 */
+	int val;
+	int ret = 0;
+	bool alerted;
+	timestamp_t start;
+	const int ap_comm_failure_threshold = 2;
+	static int ap_comm_failure_count;
+
+	if (!chipset_in_state(CHIPSET_STATE_ON) || chipset_in_low_power_mode())
+		return EC_ERROR_NOT_POWERED;
+
+	mutex_lock(&sb_rmi_mutex);
+
+	/**
+	 * Step 1: writing 0x80 to SBRMI::InBndMsg_inst7 (SBRMI_x3F) to
+	 *         indicate that command is to be serviced and to make sure
+	 *         SBRMIx40[Software Interrupt] is cleared
+	 */
+	CLEAR_MUTEX_RETURN_ERROR(sb_rmi_write(SB_RMI_IN_BND_MSG7_REG, 0x80));
+	CLEAR_MUTEX_RETURN_ERROR(sb_rmi_assert_interrupt(0));
+
+	/* Step 2: writes the command to SBRMI::InBndMsg_inst0 (SBRMI_x38) */
+	CLEAR_MUTEX_RETURN_ERROR(sb_rmi_write(SB_RMI_IN_BND_MSG0_REG, cmd));
+	/* Step 3: msgIn to {SBRMI_x3C(MSB):SBRMI_x39(LSB)} */
+	CLEAR_MUTEX_RETURN_ERROR(sb_rmi_write(SB_RMI_IN_BND_MSG1_REG, msg_in & 0xFF));
+	CLEAR_MUTEX_RETURN_ERROR(
+		sb_rmi_write(SB_RMI_IN_BND_MSG2_REG, (msg_in >> 8) & 0xFF));
+	CLEAR_MUTEX_RETURN_ERROR(
+		sb_rmi_write(SB_RMI_IN_BND_MSG3_REG, (msg_in >> 16) & 0xFF));
+	CLEAR_MUTEX_RETURN_ERROR(
+		sb_rmi_write(SB_RMI_IN_BND_MSG4_REG, (msg_in >> 24) & 0xFF));
+
+	/**
+	 * Step 4: writes 0x01 to SBRMIx40[Software Interrupt] to notify
+	 *         firmware to start service.
+	 */
+	CLEAR_MUTEX_RETURN_ERROR(sb_rmi_assert_interrupt(1));
+
+	/**
+	 * Step 5: SoC do the service
+	 * Step 6: The original command will be copied to SBRMI::OutBndMsg_inst0
+	 *         (SBRMI_x30)
+	 * Step 7: wait SBRMIx02[SwAlertSts] to 1 which indicate the completion
+	 *         of a mailbox operation
+	 */
+	alerted = false;
+	start = get_time();
+	do {
+		if (sb_rmi_read(SB_RMI_STATUS_REG, &val))
+			break;
+		if (val & 0x02) {
+			alerted = true;
+			break;
+		}
+		msleep(SB_RMI_MAILBOX_RETRY_DELAY_MS);
+	} while (time_since32(start) < SB_RMI_MAILBOX_TIMEOUT_MS * MSEC);
+
+	if (!alerted) {
+		/**
+		 * Don't spam the EC logs when the AP is hung. Instead, log the
+		 * first few failures, and then indicate the AP is likely hung.
+		 */
+		if (ap_comm_failure_count < ap_comm_failure_threshold) {
+			CPRINTS("SB-SMI: Mailbox transfer timeout");
+		} else if (ap_comm_failure_count == ap_comm_failure_threshold) {
+			CPRINTS("RMI: The AP is failing to respond despite "
+				"being powered on.");
+		}
+		++ap_comm_failure_count;
+
+		ret = EC_ERROR_TIMEOUT;
+		goto error;
+	}
+
+	CLEAR_MUTEX_RETURN_ERROR(sb_rmi_read(SB_RMI_OUT_BND_MSG0_REG, &val));
+	if (val != cmd) {
+		/**
+		 * Don't spam the EC logs when the AP is hung. Instead, log the
+		 * first few failures, and then indicate the AP is likely hung.
+		 */
+		if (ap_comm_failure_count < ap_comm_failure_threshold) {
+			CPRINTS("RMI: Unexpected command value in out bound "
+				"message");
+		} else if (ap_comm_failure_count == ap_comm_failure_threshold) {
+			CPRINTS("RMI: The AP is failing to respond despite "
+				"being powered on.");
+		}
+		++ap_comm_failure_count;
+
+		ret = EC_ERROR_UNKNOWN;
+		goto error;
+	}
+
+	/**
+	 * This AP communication was successful.
+	 * Reset the count to log the next AP communication failure.
+	 */
+	ap_comm_failure_count = 0;
+
+	/* Step 8: read msgOut from {SBRMI_x34(MSB):SBRMI_x31(LSB)} */
+	*msg_out_ptr = 0;
+	CLEAR_MUTEX_RETURN_ERROR(sb_rmi_read(SB_RMI_OUT_BND_MSG1_REG, &val));
+	*msg_out_ptr |= val;
+	CLEAR_MUTEX_RETURN_ERROR(sb_rmi_read(SB_RMI_OUT_BND_MSG2_REG, &val));
+	*msg_out_ptr |= val << 8;
+	CLEAR_MUTEX_RETURN_ERROR(sb_rmi_read(SB_RMI_OUT_BND_MSG3_REG, &val));
+	*msg_out_ptr |= val << 16;
+	CLEAR_MUTEX_RETURN_ERROR(sb_rmi_read(SB_RMI_OUT_BND_MSG4_REG, &val));
+	*msg_out_ptr |= val << 24;
+
+	/**
+	 * Step 9: BMC must write 1'b1 to SBRMI::Status[SwAlertSts] to clear
+	 *          the ALERT to initiator (BMC). It is recommended to clear the
+	 *          ALERT upon completion of the current mailbox command.
+	 */
+	CLEAR_MUTEX_RETURN_ERROR(sb_rmi_write(SB_RMI_STATUS_REG, 0x2));
+
+	/* Step 10: read the return code from OutBndMsg_inst7 (SBRMI_x37) */
+	CLEAR_MUTEX_RETURN_ERROR(sb_rmi_read(SB_RMI_OUT_BND_MSG7_REG, &val));
+
+	switch (val) {
+	case SB_RMI_MAILBOX_SUCCESS:
+		ret = EC_SUCCESS;
+		break;
+	case SB_RMI_MAILBOX_ERROR_ABORTED:
+		ret = EC_ERROR_UNKNOWN;
+		break;
+	case SB_RMI_MAILBOX_ERROR_UNKNOWN_CMD:
+		ret = EC_ERROR_INVAL;
+		break;
+	case SB_RMI_MAILBOX_ERROR_INVALID_CORE:
+		ret = EC_ERROR_PARAM1;
+		break;
+	default:
+		ret = EC_ERROR_UNKNOWN;
+		break;
+	}
+
+error:
+	mutex_unlock(&sb_rmi_mutex);
+	if (ret)
+		CPRINTS("SB-RMI Error: %d", ret);
+
+	return ret;
+}
+#endif
diff --git a/driver/sb_rmi.h b/driver/sb_rmi.h
new file mode 100644
index 0000000000..d406562f79
--- /dev/null
+++ b/driver/sb_rmi.h
@@ -0,0 +1,58 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* AMD SB-RMI (Side-band Remote Management Interface) Driver */
+
+#ifndef __CROS_EC_SB_RMI_H
+#define __CROS_EC_SB_RMI_H
+
+#include "common.h"
+
+#define SB_RMI_OUT_BND_MSG0_REG 0x30
+#define SB_RMI_OUT_BND_MSG1_REG 0x31
+#define SB_RMI_OUT_BND_MSG2_REG 0x32
+#define SB_RMI_OUT_BND_MSG3_REG 0x33
+#define SB_RMI_OUT_BND_MSG4_REG 0x34
+#define SB_RMI_OUT_BND_MSG5_REG 0x35
+#define SB_RMI_OUT_BND_MSG6_REG 0x36
+#define SB_RMI_OUT_BND_MSG7_REG 0x37
+
+#define SB_RMI_IN_BND_MSG0_REG 0x38
+#define SB_RMI_IN_BND_MSG1_REG 0x39
+#define SB_RMI_IN_BND_MSG2_REG 0x3a
+#define SB_RMI_IN_BND_MSG3_REG 0x3b
+#define SB_RMI_IN_BND_MSG4_REG 0x3c
+#define SB_RMI_IN_BND_MSG5_REG 0x3d
+#define SB_RMI_IN_BND_MSG6_REG 0x3e
+#define SB_RMI_IN_BND_MSG7_REG 0x3f
+
+#define SB_RMI_SW_INTR_REG 0x40
+#define SB_RMI_STATUS_REG 0x02
+
+#define SB_RMI_WRITE_STT_SENSOR_CMD 0x3A
+
+#define SB_RMI_MAILBOX_SUCCESS 0x0
+#define SB_RMI_MAILBOX_ERROR_ABORTED 0x1
+#define SB_RMI_MAILBOX_ERROR_UNKNOWN_CMD 0x2
+#define SB_RMI_MAILBOX_ERROR_INVALID_CORE 0x3
+
+/* Socket ID 0 */
+#define SB_RMI_I2C_ADDR_FLAGS0 0x3c
+/* Socket ID 1 */
+#define SB_RMI_I2C_ADDR_FLAGS1 0x30
+
+/**
+ * Execute a SB-RMI mailbox transaction
+ *
+ * cmd:
+ *	See "SB-RMI Soft Mailbox Message" table in PPR for command id
+ * msg_in:
+ *	Message In buffer
+ * msg_out:
+ *	Message Out buffer
+ */
+int sb_rmi_mailbox_xfer(int cmd, uint32_t msg_in, uint32_t *msg_out_ptr);
+
+#endif /* __CROS_EC_SB_RMI_H */
diff --git a/driver/sensorhub_lsm6dsm.c b/driver/sensorhub_lsm6dsm.c
index 37072d5970..d801eb85f3 100644
--- a/driver/sensorhub_lsm6dsm.c
+++ b/driver/sensorhub_lsm6dsm.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,10 +13,10 @@
 #include "driver/sensorhub_lsm6dsm.h"
 #include "driver/stm_mems_common.h"
 
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
 
-static int set_reg_bit_field(const struct motion_sensor_t *s,
-					uint8_t reg, uint8_t bit_field)
+static int set_reg_bit_field(const struct motion_sensor_t *s, uint8_t reg,
+			     uint8_t bit_field)
 {
 	int tmp;
 	int ret;
@@ -29,8 +29,8 @@ static int set_reg_bit_field(const struct motion_sensor_t *s,
 	return st_raw_write8(s->port, s->i2c_spi_addr_flags, reg, tmp);
 }
 
-static int clear_reg_bit_field(const struct motion_sensor_t *s,
-					uint8_t reg, uint8_t bit_field)
+static int clear_reg_bit_field(const struct motion_sensor_t *s, uint8_t reg,
+			       uint8_t bit_field)
 {
 	int tmp;
 	int ret;
@@ -45,14 +45,13 @@ static int clear_reg_bit_field(const struct motion_sensor_t *s,
 
 static inline int enable_sensorhub_func(const struct motion_sensor_t *s)
 {
-	return set_reg_bit_field(s, LSM6DSM_CTRL10_ADDR,
-						LSM6DSM_EMBED_FUNC_EN);
+	return set_reg_bit_field(s, LSM6DSM_CTRL10_ADDR, LSM6DSM_EMBED_FUNC_EN);
 }
 
 static inline int disable_sensorhub_func(const struct motion_sensor_t *s)
 {
 	return clear_reg_bit_field(s, LSM6DSM_CTRL10_ADDR,
-						LSM6DSM_EMBED_FUNC_EN);
+				   LSM6DSM_EMBED_FUNC_EN);
 }
 
 /*
@@ -65,44 +64,43 @@ static inline int disable_sensorhub_func(const struct motion_sensor_t *s)
 static inline int enable_ereg_bank_acc(const struct motion_sensor_t *s)
 {
 	return set_reg_bit_field(s, LSM6DSM_FUNC_CFG_ACC_ADDR,
-							LSM6DSM_FUNC_CFG_EN);
+				 LSM6DSM_FUNC_CFG_EN);
 }
 
 static inline int disable_ereg_bank_acc(const struct motion_sensor_t *s)
 {
 	return clear_reg_bit_field(s, LSM6DSM_FUNC_CFG_ACC_ADDR,
-							LSM6DSM_FUNC_CFG_EN);
+				   LSM6DSM_FUNC_CFG_EN);
 }
 
-static inline int enable_aux_i2c_master(const struct motion_sensor_t *s)
+static inline int enable_aux_i2c_controller(const struct motion_sensor_t *s)
 {
-	return set_reg_bit_field(s, LSM6DSM_MASTER_CFG_ADDR,
-							LSM6DSM_I2C_MASTER_ON);
+	return set_reg_bit_field(s, LSM6DSM_CONTROLLER_CFG_ADDR,
+				 LSM6DSM_I2C_CONTROLLER_ON);
 }
 
-static inline int disable_aux_i2c_master(const struct motion_sensor_t *s)
+static inline int disable_aux_i2c_controller(const struct motion_sensor_t *s)
 {
-	return clear_reg_bit_field(s, LSM6DSM_MASTER_CFG_ADDR,
-							LSM6DSM_I2C_MASTER_ON);
+	return clear_reg_bit_field(s, LSM6DSM_CONTROLLER_CFG_ADDR,
+				   LSM6DSM_I2C_CONTROLLER_ON);
 }
 
-static inline int restore_master_cfg(const struct motion_sensor_t *s,
-								int cache)
+static inline int restore_controller_cfg(const struct motion_sensor_t *s,
+					 int cache)
 {
 	return st_raw_write8(s->port, s->i2c_spi_addr_flags,
-			     LSM6DSM_MASTER_CFG_ADDR, cache);
+			     LSM6DSM_CONTROLLER_CFG_ADDR, cache);
 }
 
-static int enable_i2c_pass_through(const struct motion_sensor_t *s,
-							int *cache)
+static int enable_i2c_pass_through(const struct motion_sensor_t *s, int *cache)
 {
 	int ret;
 
 	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags,
-			   LSM6DSM_MASTER_CFG_ADDR, cache);
+			   LSM6DSM_CONTROLLER_CFG_ADDR, cache);
 	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x MCR error ret: %d\n",
-			__func__, s->name, s->type, ret);
+		CPRINTF("%s: %s type:0x%x MCR error ret: %d\n", __func__,
+			s->name, s->type, ret);
 		return ret;
 	}
 
@@ -112,75 +110,73 @@ static int enable_i2c_pass_through(const struct motion_sensor_t *s,
 	 * so that there is no bus contention.
 	 */
 	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-			    LSM6DSM_MASTER_CFG_ADDR,
+			    LSM6DSM_CONTROLLER_CFG_ADDR,
 			    *cache | LSM6DSM_EXT_TRIGGER_EN);
 	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x MCETEN error ret: %d\n",
-			__func__, s->name, s->type, ret);
+		CPRINTF("%s: %s type:0x%x MCETEN error ret: %d\n", __func__,
+			s->name, s->type, ret);
 		return ret;
 	}
 	msleep(10);
 
-	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-			    LSM6DSM_MASTER_CFG_ADDR,
-				 *cache & ~(LSM6DSM_EXT_TRIGGER_EN
-					    | LSM6DSM_I2C_MASTER_ON));
+	ret = st_raw_write8(
+		s->port, s->i2c_spi_addr_flags, LSM6DSM_CONTROLLER_CFG_ADDR,
+		*cache & ~(LSM6DSM_EXT_TRIGGER_EN | LSM6DSM_I2C_CONTROLLER_ON));
 	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x MCC error ret: %d\n",
-			__func__, s->name, s->type, ret);
-		restore_master_cfg(s, *cache);
+		CPRINTF("%s: %s type:0x%x MCC error ret: %d\n", __func__,
+			s->name, s->type, ret);
+		restore_controller_cfg(s, *cache);
 		return ret;
 	}
 
 	return st_raw_write8(s->port, s->i2c_spi_addr_flags,
-			LSM6DSM_MASTER_CFG_ADDR, LSM6DSM_I2C_PASS_THRU_MODE);
+			     LSM6DSM_CONTROLLER_CFG_ADDR,
+			     LSM6DSM_I2C_PASS_THRU_MODE);
 }
 
-static inline int power_down_accel(const struct motion_sensor_t *s,
-						int *cache)
+static inline int power_down_accel(const struct motion_sensor_t *s, int *cache)
 {
 	int ret;
 
-	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags,
-			   LSM6DSM_CTRL1_ADDR, cache);
+	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, LSM6DSM_CTRL1_ADDR,
+			   cache);
 	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x CTRL1R error ret: %d\n",
-			__func__, s->name, s->type, ret);
+		CPRINTF("%s: %s type:0x%x CTRL1R error ret: %d\n", __func__,
+			s->name, s->type, ret);
 		return ret;
 	}
 
-	return st_raw_write8(s->port, s->i2c_spi_addr_flags,
-			     LSM6DSM_CTRL1_ADDR,
+	return st_raw_write8(s->port, s->i2c_spi_addr_flags, LSM6DSM_CTRL1_ADDR,
 			     *cache & ~LSM6DSM_XL_ODR_MASK);
 }
 
 static inline int restore_ctrl1(const struct motion_sensor_t *s, int cache)
 {
-	return st_raw_write8(s->port, s->i2c_spi_addr_flags,
-			     LSM6DSM_CTRL1_ADDR, cache);
+	return st_raw_write8(s->port, s->i2c_spi_addr_flags, LSM6DSM_CTRL1_ADDR,
+			     cache);
 }
 
 static int config_slv0_read(const struct motion_sensor_t *s,
-			    const uint16_t slv_addr_flags,
-			    uint16_t reg, uint8_t len)
+			    const uint16_t slv_addr_flags, uint16_t reg,
+			    uint8_t len)
 {
 	int ret;
-	uint16_t addr_8bit = I2C_GET_ADDR(slv_addr_flags) << 1;
+	uint16_t addr_8bit = I2C_STRIP_FLAGS(slv_addr_flags) << 1;
 
 	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
 			    LSM6DSM_SLV0_ADD_ADDR,
 			    (addr_8bit | LSM6DSM_SLV0_RD_BIT));
 	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x SA error ret: %d\n",
-			__func__, s->name, s->type, ret);
+		CPRINTF("%s: %s type:0x%x SA error ret: %d\n", __func__,
+			s->name, s->type, ret);
 		return ret;
 	}
 
 	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
 			    LSM6DSM_SLV0_SUBADD_ADDR, reg);
 	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x RA error ret: %d\n",
-			__func__, s->name, s->type, ret);
+		CPRINTF("%s: %s type:0x%x RA error ret: %d\n", __func__,
+			s->name, s->type, ret);
 		return ret;
 	}
 
@@ -192,8 +188,8 @@ static int config_slv0_read(const struct motion_sensor_t *s,
 			    LSM6DSM_SLV0_CONFIG_ADDR,
 			    (len & LSM6DSM_SLV0_NUM_OPS_MASK));
 	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x CFG error ret: %d\n",
-			__func__, s->name, s->type, ret);
+		CPRINTF("%s: %s type:0x%x CFG error ret: %d\n", __func__,
+			s->name, s->type, ret);
 		return ret;
 	}
 
@@ -201,21 +197,21 @@ static int config_slv0_read(const struct motion_sensor_t *s,
 }
 
 int sensorhub_config_ext_reg(const struct motion_sensor_t *s,
-			     const uint16_t slv_addr_flags,
-			     uint8_t reg, uint8_t val)
+			     const uint16_t slv_addr_flags, uint8_t reg,
+			     uint8_t val)
 {
 	int ret;
 	int tmp;
 
 	ret = enable_i2c_pass_through(s, &tmp);
 	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x ENI2C error ret: %d\n",
-			__func__, s->name, s->type, ret);
+		CPRINTF("%s: %s type:0x%x ENI2C error ret: %d\n", __func__,
+			s->name, s->type, ret);
 		return ret;
 	}
 
 	ret = st_raw_write8(s->port, slv_addr_flags, reg, val);
-	restore_master_cfg(s, tmp);
+	restore_controller_cfg(s, tmp);
 	return ret;
 }
 
@@ -226,44 +222,44 @@ int sensorhub_config_slv0_read(const struct motion_sensor_t *s,
 	int ret;
 
 	if (len <= 0 || len > OUT_XYZ_SIZE) {
-		CPRINTF("%s: %s type:0x%x Invalid length: %d\n",
-			__func__, s->name, s->type, len);
+		CPRINTF("%s: %s type:0x%x Invalid length: %d\n", __func__,
+			s->name, s->type, len);
 		return EC_ERROR_INVAL;
 	}
 
 	ret = power_down_accel(s, &tmp_xl_cfg);
 	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x PDXL error ret: %d\n",
-			__func__, s->name, s->type, ret);
+		CPRINTF("%s: %s type:0x%x PDXL error ret: %d\n", __func__,
+			s->name, s->type, ret);
 		return ret;
 	}
 
 	ret = enable_ereg_bank_acc(s);
 	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x ENERB error ret: %d\n",
-			__func__, s->name, s->type, ret);
+		CPRINTF("%s: %s type:0x%x ENERB error ret: %d\n", __func__,
+			s->name, s->type, ret);
 		goto out_restore_ctrl1;
 	}
 
 	ret = config_slv0_read(s, slv_addr_flags, reg, len);
 	disable_ereg_bank_acc(s);
 	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x CS0R error ret: %d\n",
-			__func__, s->name, s->type, ret);
+		CPRINTF("%s: %s type:0x%x CS0R error ret: %d\n", __func__,
+			s->name, s->type, ret);
 		goto out_restore_ctrl1;
 	}
 
 	ret = enable_sensorhub_func(s);
 	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x ENSH error ret: %d\n",
-			__func__, s->name, s->type, ret);
+		CPRINTF("%s: %s type:0x%x ENSH error ret: %d\n", __func__,
+			s->name, s->type, ret);
 		goto out_restore_ctrl1;
 	}
 
-	ret = enable_aux_i2c_master(s);
+	ret = enable_aux_i2c_controller(s);
 	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x ENI2CM error ret: %d\n",
-			__func__, s->name, s->type, ret);
+		CPRINTF("%s: %s type:0x%x ENI2CM error ret: %d\n", __func__,
+			s->name, s->type, ret);
 		disable_sensorhub_func(s);
 	}
 out_restore_ctrl1:
@@ -281,47 +277,46 @@ int sensorhub_slv0_data_read(const struct motion_sensor_t *s, uint8_t *raw)
 	 * contents of that register.
 	 */
 	ret = st_raw_read_n_noinc(s->port, s->i2c_spi_addr_flags,
-				  LSM6DSM_SENSORHUB1_REG,
-				  raw, OUT_XYZ_SIZE);
+				  LSM6DSM_SENSORHUB1_REG, raw, OUT_XYZ_SIZE);
 	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x SH1R error ret: %d\n",
-			__func__, s->name, s->type, ret);
+		CPRINTF("%s: %s type:0x%x SH1R error ret: %d\n", __func__,
+			s->name, s->type, ret);
 		return ret;
 	}
 	return EC_SUCCESS;
 }
 
 int sensorhub_check_and_rst(const struct motion_sensor_t *s,
-			    const uint16_t slv_addr_flags,
-			    uint8_t whoami_reg, uint8_t whoami_val,
-			    uint8_t rst_reg, uint8_t rst_val)
+			    const uint16_t slv_addr_flags, uint8_t whoami_reg,
+			    uint8_t whoami_val, uint8_t rst_reg,
+			    uint8_t rst_val)
 {
 	int ret, tmp;
-	int tmp_master_cfg;
+	int tmp_controller_cfg;
 
-	ret = enable_i2c_pass_through(s, &tmp_master_cfg);
+	ret = enable_i2c_pass_through(s, &tmp_controller_cfg);
 	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x ENI2C error ret: %d\n",
-			__func__, s->name, s->type, ret);
+		CPRINTF("%s: %s type:0x%x ENI2C error ret: %d\n", __func__,
+			s->name, s->type, ret);
 		return ret;
 	}
 
 	ret = st_raw_read8(s->port, slv_addr_flags, whoami_reg, &tmp);
 	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x WAIR error ret: %d\n",
-			__func__, s->name, s->type, ret);
-		goto err_restore_master_cfg;
+		CPRINTF("%s: %s type:0x%x WAIR error ret: %d\n", __func__,
+			s->name, s->type, ret);
+		goto err_restore_controller_cfg;
 	}
 
 	if (tmp != whoami_val) {
-		CPRINTF("%s: %s type:0x%x WAIC error ret: %d\n",
-			__func__, s->name, s->type, ret);
+		CPRINTF("%s: %s type:0x%x WAIC error ret: %d\n", __func__,
+			s->name, s->type, ret);
 		ret = EC_ERROR_UNKNOWN;
-		goto err_restore_master_cfg;
+		goto err_restore_controller_cfg;
 	}
 
 	ret = st_raw_write8(s->port, slv_addr_flags, rst_reg, rst_val);
-err_restore_master_cfg:
-	restore_master_cfg(s, tmp_master_cfg);
+err_restore_controller_cfg:
+	restore_controller_cfg(s, tmp_controller_cfg);
 	return ret;
 }
diff --git a/driver/sensorhub_lsm6dsm.h b/driver/sensorhub_lsm6dsm.h
index 07b19046df..9f1b7671ac 100644
--- a/driver/sensorhub_lsm6dsm.h
+++ b/driver/sensorhub_lsm6dsm.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,8 +25,8 @@
  * @return EC_SUCCESS on success, EC error codes on failure.
  */
 int sensorhub_config_ext_reg(const struct motion_sensor_t *s,
-			     const uint16_t slv_addr_flags,
-			     uint8_t reg, uint8_t val);
+			     const uint16_t slv_addr_flags, uint8_t reg,
+			     uint8_t val);
 
 /**
  * Configure the sensor hub to read data from a specific register of an
@@ -39,8 +39,8 @@ int sensorhub_config_ext_reg(const struct motion_sensor_t *s,
  * @return EC_SUCCESS on success, EC error codes on failure.
  */
 int sensorhub_config_slv0_read(const struct motion_sensor_t *s,
-			       const uint16_t slv_addr_flags,
-			       uint8_t reg, int len);
+			       const uint16_t slv_addr_flags, uint8_t reg,
+			       int len);
 
 /**
  * Reads the data from the register bank that is associated with the slave0
@@ -65,7 +65,7 @@ int sensorhub_slv0_data_read(const struct motion_sensor_t *s, uint8_t *raw);
  * @return EC_SUCCESS on success, EC error codes on failure.
  */
 int sensorhub_check_and_rst(const struct motion_sensor_t *s,
-			    const uint16_t slv_addr_flags,
-			    uint8_t whoami_reg, uint8_t whoami_val,
-			    uint8_t rst_reg, uint8_t rst_val);
+			    const uint16_t slv_addr_flags, uint8_t whoami_reg,
+			    uint8_t whoami_val, uint8_t rst_reg,
+			    uint8_t rst_val);
 #endif /* __CROS_EC_SENSORHUB_LSM6DSM_H */
diff --git a/driver/sha256/sha256_it8xxx2.c b/driver/sha256/sha256_it8xxx2.c
new file mode 100644
index 0000000000..eb9d83e948
--- /dev/null
+++ b/driver/sha256/sha256_it8xxx2.c
@@ -0,0 +1,150 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "builtin/assert.h"
+#include "builtin/endian.h"
+#include "common.h"
+#include "console.h"
+#include "sha256.h"
+#include "util.h"
+
+#ifdef CONFIG_ZTEST
+static uint8_t emulated_registers[3];
+#define IT8XXX2_GCTRL_SHA1HASHCTRLR emulated_registers[0]
+#define IT8XXX2_GCTRL_SHA1HBADDR emulated_registers[1]
+#define IT8XXX2_GCTRL_SHA2HBADDR emulated_registers[2]
+uint8_t it8xxx2_sha256_get_sha1hbaddr(void)
+{
+	return IT8XXX2_GCTRL_SHA1HBADDR;
+}
+
+uint8_t it8xxx2_sha256_get_sha2hbaddr(void)
+{
+	return IT8XXX2_GCTRL_SHA2HBADDR;
+}
+#else
+#define IT8XXX2_GCTRL_SHA1HASHCTRLR REG8(0x00f0202d)
+#define IT8XXX2_GCTRL_SHA1HBADDR REG8(0x00f0202e)
+#define IT8XXX2_GCTRL_SHA2HBADDR REG8(0x00f0202f)
+#endif
+
+static const uint32_t sha256_h0[8] = { 0x6a09e667, 0xbb67ae85, 0x3c6ef372,
+				       0xa54ff53a, 0x510e527f, 0x9b05688c,
+				       0x1f83d9ab, 0x5be0cd19 };
+
+static const uint32_t sha256_k[64] = {
+	0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5, 0x3956c25b, 0x59f111f1,
+	0x923f82a4, 0xab1c5ed5, 0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3,
+	0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174, 0xe49b69c1, 0xefbe4786,
+	0x0fc19dc6, 0x240ca1cc, 0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da,
+	0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7, 0xc6e00bf3, 0xd5a79147,
+	0x06ca6351, 0x14292967, 0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13,
+	0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85, 0xa2bfe8a1, 0xa81a664b,
+	0xc24b8b70, 0xc76c51a3, 0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070,
+	0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5, 0x391c0cb3, 0x4ed8aa4a,
+	0x5b9cca4f, 0x682e6ff3, 0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208,
+	0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2
+};
+
+void SHA256_init(struct sha256_ctx *ctx)
+{
+	int i;
+
+	ctx->total_len = 0;
+	ctx->w_index = 0;
+
+	for (i = 0; i < ARRAY_SIZE(sha256_h0); i++)
+		ctx->h[i] = sha256_h0[i];
+	for (i = 0; i < ARRAY_SIZE(sha256_k); i++)
+		ctx->k[i] = sha256_k[i];
+
+	IT8XXX2_GCTRL_SHA1HBADDR = ((uint32_t)ctx >> 6) & 0xffc;
+	IT8XXX2_GCTRL_SHA2HBADDR = ((uint32_t)&ctx->k >> 6) & 0xffc;
+}
+
+static void SHA256_chip_calculation(struct sha256_ctx *ctx)
+{
+	uint8_t hash_ctrl __unused;
+	uint32_t key;
+
+	key = irq_lock();
+	IT8XXX2_GCTRL_SHA1HASHCTRLR |= BIT(1);
+	hash_ctrl = IT8XXX2_GCTRL_SHA1HASHCTRLR;
+	ctx->w_index = 0;
+	irq_unlock(key);
+}
+
+void SHA256_update(struct sha256_ctx *ctx, const uint8_t *data, uint32_t len)
+{
+	uint32_t rem_len = len, data_index = 0;
+	uint32_t *p = (uint32_t *)data;
+
+	/* Requires 4-byte alignment */
+	ASSERT(len % 4 == 0);
+
+	while (rem_len) {
+		uint32_t tmp, x = p[data_index++];
+
+		/*
+		 * htobe32(x); manually inlining this saves several instructions
+		 * when compared to a call to __bswapsi2, saving function call
+		 * overhead and reloading of the mask constants (because there
+		 * are registers to spare in this function). It's written as
+		 * inline assembly to ensure that it won't get lowered to a
+		 * __builtin_bswap32 that might not be inlined.
+		 *
+		 * x = ((x << 8) & 0xFF00FF00) | ((x >> 8) & 0xFF00FF);
+		 * x = (x << 16) | (x >> 16)
+		 */
+		if (IS_ENABLED(CONFIG_RISCV) &&
+		    IS_ENABLED(CONFIG_LITTLE_ENDIAN)) {
+			__asm__(" slli %[scratch], %[x], 8\n"
+				" srli %[x], %[x], 8\n"
+				" and %[scratch], %[scratch], %[hi]\n"
+				" and %[x], %[x], %[lo]\n"
+				" or %[x], %[scratch], %[x]\n"
+				" slli %[scratch], %[x], 16\n"
+				" srli %[x], %[x], 16\n"
+				" or %[x], %[x], %[scratch]\n"
+				: [x] "+r"(x), [scratch] "=&r"(tmp)
+				: [hi] "r"(0xFF00FF00), [lo] "r"(0x00FF00FF));
+		} else {
+			x = htobe32(x);
+		}
+		ctx->w[ctx->w_index++] = x;
+		if (ctx->w_index >= 16) {
+			SHA256_chip_calculation(ctx);
+		}
+		rem_len -= 4;
+	}
+	ctx->total_len += len;
+}
+
+void SHA256_abort(struct sha256_ctx *ctx)
+{
+	ARG_UNUSED(ctx);
+}
+
+uint8_t *SHA256_final(struct sha256_ctx *ctx)
+{
+	int i;
+
+	memset(&ctx->w[ctx->w_index], 0, SHA256_BLOCK_SIZE - ctx->w_index * 4);
+	ctx->w[ctx->w_index] = 0x80000000;
+
+	if (ctx->w_index >= 14) {
+		SHA256_chip_calculation(ctx);
+		memset(&ctx->w[ctx->w_index], 0,
+		       SHA256_BLOCK_SIZE - ctx->w_index * 4);
+	}
+	ctx->w[15] = ctx->total_len * 8;
+	SHA256_chip_calculation(ctx);
+
+	for (i = 0; i < 8; i++) {
+		ctx->h[i] = be32toh(ctx->h[i]);
+	}
+
+	return (uint8_t *)ctx->h;
+}
diff --git a/driver/stm_mems_common.c b/driver/stm_mems_common.c
index 6cee29977d..93a0b4dc2f 100644
--- a/driver/stm_mems_common.c
+++ b/driver/stm_mems_common.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,28 +11,24 @@
 /**
  * st_raw_read_n - Read n bytes for read
  */
-int st_raw_read_n(const int port,
-		  const uint16_t i2c_addr_flags,
+int st_raw_read_n(const int port, const uint16_t i2c_addr_flags,
 		  const uint8_t reg, uint8_t *data_ptr, const int len)
 {
 	/* TODO: Implement SPI interface support */
-	return i2c_read_block(port, i2c_addr_flags,
-			      reg | 0x80, data_ptr, len);
+	return i2c_read_block(port, i2c_addr_flags, reg | 0x80, data_ptr, len);
 }
 
 /**
  * st_raw_read_n_noinc - Read n bytes for read (no auto inc address)
  */
-int st_raw_read_n_noinc(const int port,
-			const uint16_t i2c_addr_flags,
+int st_raw_read_n_noinc(const int port, const uint16_t i2c_addr_flags,
 			const uint8_t reg, uint8_t *data_ptr, const int len)
 {
 	/* TODO: Implement SPI interface support */
-	return i2c_read_block(port, i2c_addr_flags,
-			      reg, data_ptr, len);
+	return i2c_read_block(port, i2c_addr_flags, reg, data_ptr, len);
 }
 
- /**
+/**
  * st_write_data_with_mask - Write register with mask
  * @s: Motion sensor pointer
  * @reg: Device register
@@ -40,24 +36,22 @@ int st_raw_read_n_noinc(const int port,
  * @data: Data pointer
  */
 int st_write_data_with_mask(const struct motion_sensor_t *s, int reg,
-			 uint8_t mask, uint8_t data)
+			    uint8_t mask, uint8_t data)
 {
 	int err;
 	int new_data = 0x00, old_data = 0x00;
 
-	err = st_raw_read8(s->port, s->i2c_spi_addr_flags,
-			   reg, &old_data);
+	err = st_raw_read8(s->port, s->i2c_spi_addr_flags, reg, &old_data);
 	if (err != EC_SUCCESS)
 		return err;
 
-	new_data = ((old_data & (~mask)) |
-		    ((data << __builtin_ctz(mask)) & mask));
+	new_data =
+		((old_data & (~mask)) | ((data << __builtin_ctz(mask)) & mask));
 
 	if (new_data == old_data)
 		return EC_SUCCESS;
 
-	return st_raw_write8(s->port, s->i2c_spi_addr_flags,
-			     reg, new_data);
+	return st_raw_write8(s->port, s->i2c_spi_addr_flags, reg, new_data);
 }
 
 /**
@@ -77,8 +71,8 @@ int st_get_resolution(const struct motion_sensor_t *s)
  * @offset: offset vector
  * @temp: Temp
  */
-int st_set_offset(const struct motion_sensor_t *s,
-	       const int16_t *offset, int16_t temp)
+int st_set_offset(const struct motion_sensor_t *s, const int16_t *offset,
+		  int16_t temp)
 {
 	struct stprivate_data *data = s->drv_data;
 
@@ -94,8 +88,8 @@ int st_set_offset(const struct motion_sensor_t *s,
  * @offset: offset vector
  * @temp: Temp
  */
-int st_get_offset(const struct motion_sensor_t *s,
-	       int16_t *offset, int16_t *temp)
+int st_get_offset(const struct motion_sensor_t *s, int16_t *offset,
+		  int16_t *temp)
 {
 	struct stprivate_data *data = s->drv_data;
 
@@ -125,7 +119,7 @@ int st_get_data_rate(const struct motion_sensor_t *s)
  */
 void st_normalize(const struct motion_sensor_t *s, intv3_t v, uint8_t *data)
 {
-	int i, range;
+	int i;
 	struct stprivate_data *drvdata = s->drv_data;
 	/*
 	 * Data is left-aligned and the bottom bits need to be
@@ -139,8 +133,23 @@ void st_normalize(const struct motion_sensor_t *s, intv3_t v, uint8_t *data)
 
 	rotate(v, *s->rot_standard_ref, v);
 
-	/* apply offset in the device coordinates */
-	range = s->drv->get_range(s);
 	for (i = X; i <= Z; i++)
-		v[i] += (drvdata->offset[i] << 5) / range;
+		v[i] += (drvdata->offset[i] << 5) / s->current_range;
+}
+
+#ifdef CONFIG_GESTURE_HOST_DETECTION
+/**
+ * st_list_activities - Apply to LSB data sensitivity and rotation
+ * @s: Motion sensor pointer
+ * @enabled: Activities that are enabled (bitmap)
+ * @disabled: Activities that are disabled (bitmap)
+ */
+int st_list_activities(const struct motion_sensor_t *s, uint32_t *enabled,
+		       uint32_t *disabled)
+{
+	struct stprivate_data *data = s->drv_data;
+	*enabled = data->enabled_activities;
+	*disabled = data->disabled_activities;
+	return EC_RES_SUCCESS;
 }
+#endif /* CONFIG_GESTURE_HOST_DETECTION */
diff --git a/driver/stm_mems_common.h b/driver/stm_mems_common.h
index 1984e5e070..58e039bdd2 100644
--- a/driver/stm_mems_common.h
+++ b/driver/stm_mems_common.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,35 +8,32 @@
 #ifndef __CROS_EC_ST_COMMONS_H
 #define __CROS_EC_ST_COMMONS_H
 
-#include "common.h"
-#include "util.h"
 #include "accelgyro.h"
+#include "common.h"
 #include "console.h"
 #include "i2c.h"
+#include "util.h"
 
 /* X, Y, Z axis data len */
-#define OUT_XYZ_SIZE			6
+#define OUT_XYZ_SIZE 6
 
-#define ST_NORMALIZE_RATE(_fs)    (1 << __fls(_fs))
+#define ST_NORMALIZE_RATE(_fs) (1 << __fls(_fs))
 
-#ifdef CONFIG_ACCEL_FIFO
-#define FIFO_BUFFER_NUM_PATTERN		32
+#define FIFO_BUFFER_NUM_PATTERN 8
 /* Define number of data to be read from FIFO each time
  * It must be a multiple of OUT_XYZ_SIZE.
  * In case of LSM6DSM FIFO contains pattern depending ODR
  * of Acc/gyro, be sure that FIFO can contains almost
  * FIFO_BUFFER_NUM_PATTERNpattern
  */
-#define FIFO_READ_LEN			(FIFO_BUFFER_NUM_PATTERN * OUT_XYZ_SIZE)
-
-#endif /* CONFIG_ACCEL_FIFO */
+#define FIFO_READ_LEN (FIFO_BUFFER_NUM_PATTERN * OUT_XYZ_SIZE)
 
 /**
  * Read single register
  */
 static inline int st_raw_read8(const int port,
-			       const uint16_t i2c_spi_addr_flags,
-			       const int reg, int *data_ptr)
+			       const uint16_t i2c_spi_addr_flags, const int reg,
+			       int *data_ptr)
 {
 	/* TODO: Implement SPI interface support */
 	return i2c_read8(port, i2c_spi_addr_flags, reg, data_ptr);
@@ -56,18 +53,16 @@ static inline int st_raw_write8(const int port,
 /**
  * st_raw_read_n - Read n bytes for read
  */
-int st_raw_read_n(const int port,
-		  const uint16_t i2c_spi_addr_flags,
+int st_raw_read_n(const int port, const uint16_t i2c_spi_addr_flags,
 		  const uint8_t reg, uint8_t *data_ptr, const int len);
 
 /**
  * st_raw_read_n_noinc - Read n bytes for read (no auto inc address)
  */
-int st_raw_read_n_noinc(const int port,
-			const uint16_t i2c_spi_addr_flags,
+int st_raw_read_n_noinc(const int port, const uint16_t i2c_spi_addr_flags,
 			const uint8_t reg, uint8_t *data_ptr, const int len);
 
- /**
+/**
  * st_write_data_with_mask - Write register with mask
  * @s: Motion sensor pointer
  * @reg: Device register
@@ -75,9 +70,9 @@ int st_raw_read_n_noinc(const int port,
  * @data: Data pointer
  */
 int st_write_data_with_mask(const struct motion_sensor_t *s, int reg,
-			 uint8_t mask, uint8_t data);
+			    uint8_t mask, uint8_t data);
 
- /**
+/**
  * st_get_resolution - Get bit resolution
  * @s: Motion sensor pointer
  */
@@ -89,8 +84,8 @@ int st_get_resolution(const struct motion_sensor_t *s);
  * @offset: offset vector
  * @temp: Temp
  */
-int st_set_offset(const struct motion_sensor_t *s,
-		  const int16_t *offset, int16_t temp);
+int st_set_offset(const struct motion_sensor_t *s, const int16_t *offset,
+		  int16_t temp);
 
 /**
  * st_get_offset - Get data offset
@@ -98,8 +93,8 @@ int st_set_offset(const struct motion_sensor_t *s,
  * @offset: offset vector
  * @temp: Temp
  */
-int st_get_offset(const struct motion_sensor_t *s,
-		  int16_t *offset, int16_t *temp);
+int st_get_offset(const struct motion_sensor_t *s, int16_t *offset,
+		  int16_t *temp);
 
 /**
  * st_get_data_rate - Get data rate (ODR)
@@ -115,9 +110,22 @@ int st_get_data_rate(const struct motion_sensor_t *s);
  */
 void st_normalize(const struct motion_sensor_t *s, intv3_t v, uint8_t *data);
 
+/**
+ * st_list_activities - Apply to LSB data sensitivity and rotation
+ * @s: Motion sensor pointer
+ * @enabled: Activities that are enabled (bitmap)
+ * @disabled: Activities that are disabled (bitmap)
+ */
+int st_list_activities(const struct motion_sensor_t *s, uint32_t *enabled,
+		       uint32_t *disabled);
+
 /* Internal data structure for sensors */
 struct stprivate_data {
 	struct accelgyro_saved_data_t base;
+#ifdef CONFIG_GESTURE_HOST_DETECTION
+	uint8_t enabled_activities;
+	uint8_t disabled_activities;
+#endif /* CONFIG_GESTURE_HOST_DETECTION */
 	int16_t offset[3];
 	uint8_t resol;
 };
diff --git a/driver/sync.c b/driver/sync.c
index 91d161765a..6c48096a18 100644
--- a/driver/sync.c
+++ b/driver/sync.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -17,17 +17,13 @@
 #include "task.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_MOTION_SENSE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_MOTION_SENSE, format, ##args)
 
 #ifndef CONFIG_ACCEL_FIFO
 #error This driver needs CONFIG_ACCEL_FIFO
 #endif
 
-#ifndef CONFIG_ACCEL_INTERRUPTS
-#error This driver needs CONFIG_ACCEL_INTERRUPTS
-#endif
-
 struct sync_event_t {
 	uint32_t timestamp;
 	int counter;
@@ -37,8 +33,11 @@ static struct queue const sync_event_queue =
 	QUEUE_NULL(CONFIG_SYNC_QUEUE_SIZE, struct sync_event_t);
 
 struct sync_event_t next_event;
-struct ec_response_motion_sensor_data vector =
-	{.flags = MOTIONSENSE_SENSOR_FLAG_WAKEUP, .data = {0, 0, 0} };
+struct ec_response_motion_sensor_data vector = {
+	.flags = MOTIONSENSE_SENSOR_FLAG_BYPASS_FIFO,
+	.data = { 0, 0, 0 }
+};
+
 int sync_enabled;
 
 static int sync_read(const struct motion_sensor_t *s, intv3_t v)
@@ -52,8 +51,8 @@ static int sync_read(const struct motion_sensor_t *s, intv3_t v)
  * still depends on being able to set this to 0 to disable it, we'll just use
  * non 0 rate values as an enable boolean.
  */
-static int sync_set_data_rate(const struct motion_sensor_t *s,
-				int rate, int roundup)
+static int sync_set_data_rate(const struct motion_sensor_t *s, int rate,
+			      int roundup)
 {
 	sync_enabled = !!rate;
 	CPRINTF("sync event driver enabling=%d\n", sync_enabled);
@@ -76,7 +75,7 @@ void sync_interrupt(enum gpio_signal signal)
 	next_event.counter++;
 	queue_add_unit(&sync_event_queue, &next_event);
 
-	task_set_event(TASK_ID_MOTIONSENSE, CONFIG_SYNC_INT_EVENT, 0);
+	task_set_event(TASK_ID_MOTIONSENSE, CONFIG_SYNC_INT_EVENT);
 }
 
 /* Bottom half of the irq handler */
@@ -89,15 +88,15 @@ static int motion_irq_handler(struct motion_sensor_t *s, uint32_t *event)
 
 	while (queue_remove_unit(&sync_event_queue, &sync_event)) {
 		vector.data[X] = sync_event.counter;
-		motion_sense_fifo_stage_data(
-			&vector, s, 1, sync_event.timestamp);
+		motion_sense_fifo_stage_data(&vector, s, 1,
+					     sync_event.timestamp);
 	}
 	motion_sense_fifo_commit_data();
 
 	return EC_SUCCESS;
 }
 
-static int sync_init(const struct motion_sensor_t *s)
+static int sync_init(struct motion_sensor_t *s)
 {
 	vector.sensor_num = s - motion_sensors;
 	sync_enabled = 0;
@@ -107,7 +106,7 @@ static int sync_init(const struct motion_sensor_t *s)
 }
 
 #ifdef CONFIG_SYNC_COMMAND
-static int command_sync(int argc, char **argv)
+static int command_sync(int argc, const char **argv)
 {
 	int count = 1, i;
 
@@ -119,9 +118,7 @@ static int command_sync(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(sync, command_sync,
-	"[count]",
-	"Simulates sync events");
+DECLARE_CONSOLE_COMMAND(sync, command_sync, "[count]", "Simulates sync events");
 #endif
 
 const struct accelgyro_drv sync_drv = {
@@ -131,4 +128,3 @@ const struct accelgyro_drv sync_drv = {
 	.get_data_rate = sync_get_data_rate,
 	.irq_handler = motion_irq_handler,
 };
-
diff --git a/driver/sync.h b/driver/sync.h
index 1f6115a086..76aa225cc1 100644
--- a/driver/sync.h
+++ b/driver/sync.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -14,5 +14,4 @@ extern const struct accelgyro_drv sync_drv;
 
 void sync_interrupt(enum gpio_signal signal);
 
-#endif	/* __CROS_EC_VSYNC_H */
-
+#endif /* __CROS_EC_VSYNC_H */
diff --git a/driver/tcpm/anx7406.c b/driver/tcpm/anx7406.c
new file mode 100644
index 0000000000..b33e8a65d8
--- /dev/null
+++ b/driver/tcpm/anx7406.c
@@ -0,0 +1,416 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* ANX7406 port manager */
+
+#include "anx7406.h"
+#include "assert.h"
+#include "common.h"
+#include "console.h"
+#include "hooks.h"
+#include "tcpm/tcpci.h"
+#include "tcpm/tcpm.h"
+#include "timer.h"
+#include "usb_pd.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBPD, "ANX7406: " format, ##args)
+
+const struct anx7406_i2c_addr anx7406_i2c_addrs_flags[] = {
+	{ ANX7406_TCPC0_I2C_ADDR_FLAGS, ANX7406_TOP0_I2C_ADDR_FLAGS },
+	{ ANX7406_TCPC1_I2C_ADDR_FLAGS, ANX7406_TOP1_I2C_ADDR_FLAGS },
+	{ ANX7406_TCPC2_I2C_ADDR_FLAGS, ANX7406_TOP2_I2C_ADDR_FLAGS },
+	{ ANX7406_TCPC3_I2C_ADDR_FLAGS, ANX7406_TOP3_I2C_ADDR_FLAGS },
+	{ ANX7406_TCPC4_I2C_ADDR_FLAGS, ANX7406_TOP4_I2C_ADDR_FLAGS },
+	{ ANX7406_TCPC5_I2C_ADDR_FLAGS, ANX7406_TOP5_I2C_ADDR_FLAGS },
+	{ ANX7406_TCPC6_I2C_ADDR_FLAGS, ANX7406_TOP6_I2C_ADDR_FLAGS },
+	{ ANX7406_TCPC7_I2C_ADDR_FLAGS, ANX7406_TOP7_I2C_ADDR_FLAGS },
+};
+
+static struct anx7406_i2c_addr i2c_peripheral[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+enum ec_error_list anx7406_set_gpio(int port, uint8_t gpio, bool value)
+{
+	if (gpio != 0) {
+		CPRINTS("C%d: Setting GPIO%d not supported", port, gpio);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTS("C%d: Setting GPIO%u %s", port, gpio, value ? "high" : "low");
+
+	return i2c_write8(tcpc_config[port].i2c_info.port,
+			  i2c_peripheral[port].top_addr_flags,
+			  ANX7406_REG_GPIO0,
+			  value ? GPIO0_OUTPUT_HIGH : GPIO0_OUTPUT_LOW);
+}
+
+static int anx7406_set_hpd(int port, int hpd_lvl)
+{
+	int val;
+
+	if (hpd_lvl) {
+		CPRINTS("set hpd to HIGH");
+		val = ANX7406_REG_HPD_OEN | HPD_DEGLITCH_TIME;
+	} else {
+		CPRINTS("set hpd to LOW");
+		val = HPD_DEGLITCH_TIME;
+	}
+
+	return i2c_write8(tcpc_config[port].i2c_info.port,
+			  i2c_peripheral[port].top_addr_flags,
+			  ANX7406_REG_HPD_DEGLITCH_H, val);
+}
+
+int anx7406_hpd_reset(const int port)
+{
+	int rv;
+
+	CPRINTS("HPD reset");
+	rv = i2c_write8(tcpc_config[port].i2c_info.port,
+			i2c_peripheral[port].top_addr_flags,
+			ANX7406_REG_HPD_CTRL_0, 0);
+	if (rv) {
+		CPRINTS("Clear HPD_MODE failed: %d", rv);
+		return rv;
+	}
+
+	return anx7406_set_hpd(port, 0);
+}
+
+/*
+ * timestamp of the next possible toggle to ensure the 2-ms spacing
+ * between IRQ_HPD.
+ */
+static uint64_t hpd_timestamp[CONFIG_USB_PD_PORT_MAX_COUNT];
+void anx7406_update_hpd_status(const struct usb_mux *mux, mux_state_t mux_state)
+{
+	int port = mux->usb_port;
+	int hpd_lvl = (mux_state & USB_PD_MUX_HPD_LVL) ? 1 : 0;
+	int hpd_irq = (mux_state & USB_PD_MUX_HPD_IRQ) ? 1 : 0;
+	int rv;
+
+	/*
+	 * All calls within this method need to update to a mux_read/write calls
+	 * that use the secondary address. This is a non-trival change and no
+	 * one is using the anx7406 as a mux only (and probably never will since
+	 * it doesn't have a re-driver). If that changes, we need to update this
+	 * code.
+	 */
+	ASSERT(!(mux->flags & USB_MUX_FLAG_NOT_TCPC));
+
+	anx7406_set_hpd(port, hpd_lvl);
+
+	if (hpd_irq) {
+		uint64_t now = get_time().val;
+		/* wait for the minimum spacing between IRQ_HPD if needed */
+		if (now < hpd_timestamp[port])
+			usleep(hpd_timestamp[port] - now);
+
+		/*
+		 * For generate hardware HPD IRQ, need set bit
+		 * ANX7406_REG_HPD_IRQ0 first, then clear it. This bit is not
+		 * write clear.
+		 */
+		rv = i2c_write8(tcpc_config[port].i2c_info.port,
+				i2c_peripheral[port].top_addr_flags,
+				ANX7406_REG_HPD_CTRL_0, ANX7406_REG_HPD_IRQ0);
+		rv |= i2c_write8(tcpc_config[port].i2c_info.port,
+				 i2c_peripheral[port].top_addr_flags,
+				 ANX7406_REG_HPD_CTRL_0, 0);
+		if (rv)
+			CPRINTS("Generate HPD IRQ failed: %d", rv);
+	}
+	/* enforce 2-ms delay between HPD pulses */
+	hpd_timestamp[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
+}
+
+static int anx7406_init(int port)
+{
+	int rv, i;
+
+	CPRINTS("C%d: init", port);
+	/*
+	 * find corresponding anx7406 TOP address according to
+	 * specified TCPC address
+	 */
+	for (i = 0; i < ARRAY_SIZE(anx7406_i2c_addrs_flags); i++) {
+		if (I2C_STRIP_FLAGS(tcpc_config[port].i2c_info.addr_flags) ==
+		    I2C_STRIP_FLAGS(
+			    anx7406_i2c_addrs_flags[i].tcpc_addr_flags)) {
+			i2c_peripheral[port].tcpc_addr_flags =
+				anx7406_i2c_addrs_flags[i].tcpc_addr_flags;
+			i2c_peripheral[port].top_addr_flags =
+				anx7406_i2c_addrs_flags[i].top_addr_flags;
+			break;
+		}
+	}
+	if (!I2C_STRIP_FLAGS(i2c_peripheral[port].top_addr_flags)) {
+		CPRINTS("C%d: 0x%x is invalid", port,
+			i2c_peripheral[port].top_addr_flags);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	/*
+	 * Set VBUS OCP
+	 *
+	 * This is retried in case the TCPC just woke up from LPM. If you add
+	 * I2C above, you need to retry that instead.
+	 */
+	rv = tcpc_write(port, ANX7406_REG_VBUS_OCP, OCP_THRESHOLD);
+	if (rv) {
+		/* Failed but this is expected if the chip is in LPM. */
+		CPRINTS("C%d: Retrying to set OCP", port);
+		msleep(5);
+		rv = tcpc_write(port, ANX7406_REG_VBUS_OCP, OCP_THRESHOLD);
+		if (rv)
+			return rv;
+	}
+
+	rv = tcpc_update8(port, TCPC_REG_TCPC_CTRL,
+			  TCPC_REG_TCPC_CTRL_DEBUG_ACC_CONTROL, MASK_SET);
+	if (rv)
+		return rv;
+
+	/* Disable CAP write protect */
+	rv = tcpc_update8(port, ANX7406_REG_TCPCCTRL, ANX7406_REG_CAP_WP,
+			  MASK_CLR);
+	/* Disable bleed discharge */
+	rv |= tcpc_update16(port, TCPC_REG_DEV_CAP_1,
+			    TCPC_REG_DEV_CAP_1_BLEED_DISCHARGE, MASK_CLR);
+	CPRINTS("C%d: TCPC config disable bleed discharge", port);
+	/* Enable CAP write protect */
+	rv |= tcpc_update8(port, ANX7406_REG_TCPCCTRL, ANX7406_REG_CAP_WP,
+			   MASK_SET);
+	if (rv)
+		return rv;
+
+	rv = tcpc_update8(port, TCPC_REG_POWER_STATUS,
+			  TCPC_REG_POWER_STATUS_UNINIT, MASK_CLR);
+	if (rv)
+		return rv;
+
+	rv = tcpci_tcpm_init(port);
+	if (rv)
+		return rv;
+
+	rv = board_anx7406_init(port);
+	if (rv)
+		return rv;
+
+	/* Let sink_ctrl & source_ctrl GPIO pin controlled by TCPC */
+	tcpc_write(port, ANX7406_REG_VBUS_SOURCE_CTRL, SOURCE_GPIO_OEN);
+	tcpc_write(port, ANX7406_REG_VBUS_SINK_CTRL, SINK_GPIO_OEN);
+
+	if (IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE)) {
+		rv = tcpc_update8(port, TCPC_REG_ROLE_CTRL,
+				  TCPC_REG_ROLE_CTRL_DRP_MASK, MASK_SET);
+		if (rv)
+			return rv;
+	}
+
+	/*
+	 * Specifically disable voltage alarms, as VBUS_VOLTAGE_ALARM_HI may
+	 * trigger repeatedly despite being masked (b/153989733)
+	 */
+	rv = tcpc_update16(port, TCPC_REG_POWER_CTRL,
+			   TCPC_REG_POWER_CTRL_VBUS_VOL_MONITOR_DIS, MASK_SET);
+	if (rv)
+		return rv;
+
+	/* TCPC Filter set to 512uS */
+	rv = tcpc_write(port, ANX7406_REG_TCPCFILTER, 0xFF);
+	rv |= tcpc_update8(port, ANX7406_REG_TCPCCTRL,
+			   ANX7406_REG_TCPCFILTERBIT8, MASK_SET);
+	if (rv)
+		CPRINTS("C%d: TCPC filter set failed: %d", port, rv);
+
+	rv = anx7406_hpd_reset(port);
+
+	CPRINTS("C%d: init success", port);
+	return rv;
+}
+
+static int anx7406_release(int port)
+{
+	return EC_SUCCESS;
+}
+
+static int anx7406_set_polarity(int port, enum tcpc_cc_polarity polarity)
+{
+	int rv;
+
+	if (polarity_rm_dts(polarity))
+		rv = tcpc_write(port, ANX7406_REG_VCONN_CTRL,
+				VCONN_PWR_CTRL_SEL | VCONN_CC1_PWR_ENABLE);
+	else
+		rv = tcpc_write(port, ANX7406_REG_VCONN_CTRL,
+				VCONN_PWR_CTRL_SEL | VCONN_CC2_PWR_ENABLE);
+
+	rv |= anx7406_set_aux(port, polarity);
+
+	if (rv)
+		CPRINTS("Update VCONN power failed: %d, polarity: %d", rv,
+			polarity);
+
+	return tcpci_tcpm_set_polarity(port, polarity);
+}
+
+static int anx7406_m1_config(int port, int slave, int offset)
+{
+	int rv;
+
+	/* Configure external I2C slave address */
+	rv = i2c_write8(tcpc_config[port].i2c_info.port,
+			i2c_peripheral[port].top_addr_flags, EXT_I2C1_ADDR,
+			slave);
+	/* Configure external I2C slave offset */
+	rv |= i2c_write8(tcpc_config[port].i2c_info.port,
+			 i2c_peripheral[port].top_addr_flags, EXT_I2C1_OFFSET,
+			 offset);
+	/* Configure external I2C transfer byte count */
+	rv |= i2c_write8(tcpc_config[port].i2c_info.port,
+			 i2c_peripheral[port].top_addr_flags,
+			 EXT_I2C1_ACCESS_DATA_BYTE_CNT, 1);
+	/* Clear DATA buffer */
+	rv |= i2c_write8(tcpc_config[port].i2c_info.port,
+			 i2c_peripheral[port].top_addr_flags,
+			 EXT_I2C1_ACCESS_CTRL, I2C1_DATA_CLR);
+	/* Clear release */
+	rv |= i2c_write8(tcpc_config[port].i2c_info.port,
+			 i2c_peripheral[port].top_addr_flags,
+			 EXT_I2C1_ACCESS_CTRL, 0);
+
+	return rv;
+}
+
+int anx7406_m1_read(int port, int slave, int offset)
+{
+	int rv, val;
+
+	rv = anx7406_m1_config(port, slave, offset);
+
+	/* Send I2C read command */
+	rv |= i2c_write8(tcpc_config[port].i2c_info.port,
+			 i2c_peripheral[port].top_addr_flags, EXT_I2C1_CTRL,
+			 I2C1_CMD_READ | I2C1_SPEED_100K);
+	if (rv) {
+		CPRINTS("initial cisco I2C master failed!");
+		return rv;
+	}
+
+	usleep(1000);
+
+	/* Read I2C data out */
+	rv = i2c_read8(tcpc_config[port].i2c_info.port,
+		       i2c_peripheral[port].top_addr_flags,
+		       EXT_I2C1_ACCESS_DATA, &val);
+	if (rv) {
+		CPRINTS("read cisco register failed!");
+		return rv;
+	}
+
+	return val;
+}
+
+static int anx7406_m1_write(int port, int slave, int offset, int data)
+{
+	int rv;
+
+	/* Configure external I2C slave address */
+	rv = anx7406_m1_config(port, slave, offset);
+
+	/* Configure I2C data */
+	rv |= i2c_write8(tcpc_config[port].i2c_info.port,
+			 i2c_peripheral[port].top_addr_flags,
+			 EXT_I2C1_ACCESS_DATA, data);
+	/* Send I2C write command */
+	rv |= i2c_write8(tcpc_config[port].i2c_info.port,
+			 i2c_peripheral[port].top_addr_flags, EXT_I2C1_CTRL,
+			 I2C1_CMD_WRITE | I2C1_SPEED_100K);
+	if (rv) {
+		CPRINTS("write data to cisco register failed!");
+		return rv;
+	}
+
+	return 0;
+}
+
+int anx7406_set_aux(int port, int flip)
+{
+	int rv;
+
+	CPRINTS("Set SBU %s flip", flip ? "" : "un");
+	/* Configure SBU orientation */
+	rv = anx7406_m1_write(port, I2C1_CISCO_SLAVE, I2C1_CISCO_LOCAL_REG,
+			      SELECT_SBU_1_2);
+	if (rv) {
+		CPRINTS("Config CISCO_LOCAL_REG register failed");
+		return rv;
+	}
+
+	/* Disable pull up/down */
+	rv = anx7406_m1_write(port, I2C1_CISCO_SLAVE, I2C1_CISCO_CTRL_3,
+			      flip ? AUX_FLIP_EN : 0);
+	if (rv) {
+		CPRINTS("Config CISCO_CTRL_3 register failed");
+		return rv;
+	}
+
+	/* Disable pull up/down */
+	rv = anx7406_m1_write(port, I2C1_CISCO_SLAVE, I2C1_CISCO_CTRL_1,
+			      VBUS_PROTECT_750MA | AUX_PULL_DISABLE);
+	if (rv) {
+		CPRINTS("Config CISCO_CTRL_1 register failed");
+		return rv;
+	}
+
+	return 0;
+}
+
+/*
+ * ANX7406 is a TCPCI compatible port controller, with some caveats.
+ * It seems to require both CC lines to be set always, instead of just
+ * one at a time, according to TCPCI spec.  Thus, now that the TCPCI
+ * driver more closely follows the spec, this driver requires
+ * overrides for set_cc and set_polarity.
+ */
+const struct tcpm_drv anx7406_tcpm_drv = {
+	.init = &anx7406_init,
+	.release = &anx7406_release,
+	.get_cc = &tcpci_tcpm_get_cc,
+#ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
+	.check_vbus_level = &tcpci_tcpm_check_vbus_level,
+#endif
+	.select_rp_value = &tcpci_tcpm_select_rp_value,
+	.set_cc = &tcpci_tcpm_set_cc,
+	.set_polarity = &anx7406_set_polarity,
+#ifdef CONFIG_USB_PD_DECODE_SOP
+	.sop_prime_enable = &tcpci_tcpm_sop_prime_enable,
+#endif
+	.set_vconn = &tcpci_tcpm_set_vconn,
+	.set_msg_header = &tcpci_tcpm_set_msg_header,
+	.set_rx_enable = &tcpci_tcpm_set_rx_enable,
+	.get_message_raw = &tcpci_tcpm_get_message_raw,
+	.transmit = &tcpci_tcpm_transmit,
+	.tcpc_alert = &tcpci_tcpc_alert,
+#ifdef CONFIG_USB_PD_DISCHARGE_TCPC
+	.tcpc_discharge_vbus = &tcpci_tcpc_discharge_vbus,
+#endif
+#ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+	.drp_toggle = tcpci_tcpc_drp_toggle,
+#endif
+	.get_chip_info = &tcpci_get_chip_info,
+#ifdef CONFIG_USB_PD_PPC
+	.set_snk_ctrl = &tcpci_tcpm_set_snk_ctrl,
+	.set_src_ctrl = &tcpci_tcpm_set_src_ctrl,
+#endif
+#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
+	.enter_low_power_mode = &tcpci_enter_low_power_mode,
+#endif
+	.set_bist_test_mode = &tcpci_set_bist_test_mode,
+#ifdef CONFIG_CMD_TCPC_DUMP
+	.dump_registers = &tcpc_dump_std_registers,
+#endif
+};
diff --git a/driver/tcpm/anx7406.h b/driver/tcpm/anx7406.h
new file mode 100644
index 0000000000..545bb9024b
--- /dev/null
+++ b/driver/tcpm/anx7406.h
@@ -0,0 +1,158 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_USB_PD_TCPM_ANX7406_H
+#define __CROS_EC_USB_PD_TCPM_ANX7406_H
+
+#include "stdbool.h"
+#include "usb_mux.h"
+
+struct anx7406_i2c_addr {
+	uint16_t tcpc_addr_flags;
+	uint16_t top_addr_flags;
+};
+
+#define ANX7406_TCPC0_I2C_ADDR_FLAGS (0x58 >> 1)
+#define ANX7406_TCPC1_I2C_ADDR_FLAGS (0x56 >> 1)
+#define ANX7406_TCPC2_I2C_ADDR_FLAGS (0x54 >> 1)
+#define ANX7406_TCPC3_I2C_ADDR_FLAGS (0x52 >> 1)
+#define ANX7406_TCPC4_I2C_ADDR_FLAGS (0x90 >> 1)
+#define ANX7406_TCPC5_I2C_ADDR_FLAGS (0x9A >> 1)
+#define ANX7406_TCPC6_I2C_ADDR_FLAGS (0xA4 >> 1)
+#define ANX7406_TCPC7_I2C_ADDR_FLAGS (0xAE >> 1)
+
+#define ANX7406_TOP0_I2C_ADDR_FLAGS (0x7E >> 1)
+#define ANX7406_TOP1_I2C_ADDR_FLAGS (0x6E >> 1)
+#define ANX7406_TOP2_I2C_ADDR_FLAGS (0x64 >> 1)
+#define ANX7406_TOP3_I2C_ADDR_FLAGS (0x62 >> 1)
+#define ANX7406_TOP4_I2C_ADDR_FLAGS (0x92 >> 1)
+#define ANX7406_TOP5_I2C_ADDR_FLAGS (0x9C >> 1)
+#define ANX7406_TOP6_I2C_ADDR_FLAGS (0xA6 >> 1)
+#define ANX7406_TOP7_I2C_ADDR_FLAGS (0xB0 >> 1)
+
+/* Registers: TCPC address used */
+#define ANX7406_REG_ANALOG_SETTING 0x0C
+#define ANX7406_REG_CABLE_DET_DIG BIT(6)
+#define ANX7406_REG_DIGITAL_RDY BIT(5)
+
+#define ANX7406_REG_TCPCFILTER 0x9F
+#define ANX7406_REG_TCPCCTRL 0xCD
+#define ANX7406_REG_TCPCFILTERBIT8 BIT(0)
+#define ANX7406_REG_CAP_WP BIT(2)
+
+#define ANX7406_REG_VBUS_SOURCE_CTRL 0xC2
+#define SOURCE_GPIO_OEN BIT(2)
+#define ANX7406_REG_VBUS_SINK_CTRL 0xC3
+#define SINK_GPIO_OEN BIT(2)
+
+#define ANX7406_REG_VBUS_OCP 0xD2
+#define OCP_THRESHOLD 0xFF
+
+#define ANX7406_REG_ADC_CTRL_1 0xE3
+#define ANX7406_REG_ADC_FSM_EN BIT(0)
+#define ANX7406_REG_ADC_MEASURE_VCONN BIT(1)
+#define ANX7406_REG_ADC_MEASURE_VBUS BIT(2)
+#define ANX7406_REG_ADC_MEASURE_OCP BIT(3)
+
+#define ANX7406_REG_VCONN_CTRL 0xEB
+#define VCONN_PWR_CTRL_SEL BIT(2)
+#define VCONN_CC2_PWR_ENABLE BIT(1)
+#define VCONN_CC1_PWR_ENABLE BIT(0)
+
+/* Registers: TOP address used */
+#define ANX7406_REG_HPD_CTRL_0 0x7E
+#define ANX7406_REG_HPD_IRQ0 BIT(2)
+
+#define ANX7406_REG_HPD_DEGLITCH_H 0x80
+#define ANX7406_REG_HPD_OEN BIT(6)
+#define HPD_DEGLITCH_TIME 0x0D
+
+#define ANX7406_REG_GPIO0 0xCA
+#define GPIO0_OUTPUT_HIGH (BIT(0) | BIT(1))
+#define GPIO0_OUTPUT_LOW BIT(0)
+
+#define EXT_I2C_OP_DELAY 1000
+/* Internal I2C0 master */
+/* External I2C0 address & offset */
+#define EXT_I2C0_ADDR 0x5E
+#define EXT_I2C0_OFFSET 0x5F
+/* External I2C0 master control bit */
+#define EXT_I2C0_CTRL 0x60
+#define I2C0_CMD_RESET BIT(6)
+#define I2C0_CMD_WRITE BIT(4)
+#define I2C0_CMD_READ 0
+#define I2C0_CMD_CISCO_READ (BIT(5) | BIT(6))
+#define I2C0_SPEED_100K (BIT(2) | BIT(3))
+#define I2C0_NO_STOP BIT(1)
+#define I2C0_NO_ACK BIT(0)
+
+#define EXT_I2C0_ACCESS_DATA_BYTE_CNT 0x61
+#define EXT_I2C0_ACCESS_DATA 0x65
+
+#define EXT_I2C0_ACCESS_CTRL 0x66
+#define I2C0_DATA_FULL BIT(7)
+#define I2C0_DATA_EMPTY BIT(6)
+#define I2C0_TIMING_SET_EN BIT(1)
+#define I2C0_DATA_CLR BIT(0)
+
+/* Internal I2C1 master */
+/* External I2C1 address & offset */
+#define EXT_I2C1_ADDR 0xCC
+#define EXT_I2C1_OFFSET 0xCD
+/* External I2C1 master control bit */
+#define EXT_I2C1_CTRL 0xCE
+#define I2C1_CMD_RESET BIT(6)
+#define I2C1_CMD_WRITE BIT(4)
+#define I2C1_CMD_READ 0
+#define I2C1_CMD_CISCO_READ (BIT(5) | BIT(6))
+#define I2C1_SPEED_100K (BIT(2) | BIT(3))
+#define I2C1_NO_STOP BIT(1)
+#define I2C1_NO_ACK BIT(0)
+
+#define EXT_I2C1_ACCESS_DATA_BYTE_CNT 0xCF
+#define EXT_I2C1_ACCESS_DATA 0xD3
+
+#define EXT_I2C1_ACCESS_CTRL 0xD4
+#define I2C1_DATA_FULL BIT(7)
+#define I2C1_DATA_EMPTY BIT(6)
+#define I2C1_TIMING_SET_EN BIT(1)
+#define I2C1_DATA_CLR BIT(0)
+
+#define I2C1_CISCO_SLAVE 0x80
+#define I2C1_CISCO_CTRL_1 0x01
+#define VBUS_PROTECT_750MA BIT(1)
+#define AUX_PULL_DISABLE BIT(3)
+
+#define I2C1_CISCO_CTRL_3 0x03
+#define AUX_FLIP_EN BIT(0)
+
+#define I2C1_CISCO_LOCAL_REG 0x06
+#define SELECT_SBU_1_2 BIT(6)
+
+extern const struct tcpm_drv anx7406_tcpm_drv;
+int anx7406_set_aux(int port, int flip);
+int anx7406_hpd_reset(const int port);
+void anx7406_update_hpd_status(const struct usb_mux *mux,
+			       mux_state_t mux_state);
+
+/**
+ * Set/clear GPIO
+ *
+ * @param port  USB-C port
+ * @param gpio  GPIO number
+ * @param value  true:high false:low
+ * @return  enum ec_error_list
+ */
+enum ec_error_list anx7406_set_gpio(int port, uint8_t gpio, bool value);
+
+/**
+ * Call back for board specific initialization
+ *
+ * @param port USB-C port
+ * @return enum ec_error_list
+ */
+int board_anx7406_init(int port);
+
+#endif /* __CROS_EC_USB_PD_TCPM_ANX7406_H */
diff --git a/driver/tcpm/anx7447.c b/driver/tcpm/anx7447.c
index de9fb5dcfc..4760596eae 100644
--- a/driver/tcpm/anx7447.c
+++ b/driver/tcpm/anx7447.c
@@ -1,71 +1,70 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* ANX7447 port manager */
 
-#include "common.h"
 #include "anx7447.h"
+#include "builtin/assert.h"
+#include "common.h"
 #include "console.h"
 #include "hooks.h"
-#include "tcpci.h"
-#include "tcpm.h"
+#include "tcpm/tcpci.h"
+#include "tcpm/tcpm.h"
 #include "timer.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define vsafe5v_min (3800/25)
-#define vsafe0v_max (800/25)
-/*
- * These interface are workable while ADC is enabled, before
- * calling them should make sure ec driver finished chip initilization.
- */
-#define is_equal_greater_safe5v(port) \
-		(((anx7447_get_vbus_voltage(port))) > vsafe5v_min)
-#define is_equal_greater_safe0v(port) \
-		(((anx7447_get_vbus_voltage(port))) > vsafe0v_max)
+#define VSAFE5V_MIN 3800
+#define VSAFE0V_MAX 800
 
 struct anx_state {
-	uint16_t i2c_slave_addr_flags;
+	uint16_t i2c_addr_flags;
 };
 
 struct anx_usb_mux {
 	int state;
 };
 
-static int anx7447_mux_set(const struct usb_mux *me, mux_state_t mux_state);
+static int anx7447_mux_set(const struct usb_mux *me, mux_state_t mux_state,
+			   bool *ack_required);
 
 static struct anx_state anx[CONFIG_USB_PD_PORT_MAX_COUNT];
 static struct anx_usb_mux mux[CONFIG_USB_PD_PORT_MAX_COUNT];
+static bool anx7447_bist_test_mode[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+#ifdef CONFIG_USB_PD_FRS_TCPC
+/* an array to indicate which port is waiting for FRS disablement. */
+static bool anx_frs_dis[CONFIG_USB_PD_PORT_MAX_COUNT];
+#endif /* CONFIG_USB_PD_FRS_TCPC */
 
 /*
- * ANX7447 has two co-existence I2C slave addresses, TCPC slave address and
- * SPI slave address. The registers of TCPC slave address are partly compliant
- * with standard USB TCPC specification, and the registers in SPI slave
+ * ANX7447 has two co-existence I2C addresses, TCPC address and
+ * SPI address. The registers of TCPC address are partly compliant
+ * with standard USB TCPC specification, and the registers in SPI
  * address controls the other functions (ex, hpd_level, mux_switch, and
- * so on). It can't use tcpc_read() and tcpc_write() to access SPI slave
- * address because its slave address has been set as TCPC in the structure
+ * so on). It can't use tcpc_read() and tcpc_write() to access SPI
+ * address because its address has been set as TCPC in the structure
  * tcpc_config_t.
  * anx7447_reg_write() and anx7447_reg_read() are implemented here to access
- * ANX7447 SPI slave address.
+ * ANX7447 SPI address.
  */
 const struct anx7447_i2c_addr anx7447_i2c_addrs_flags[] = {
-	{AN7447_TCPC0_I2C_ADDR_FLAGS, AN7447_SPI0_I2C_ADDR_FLAGS},
-	{AN7447_TCPC1_I2C_ADDR_FLAGS, AN7447_SPI1_I2C_ADDR_FLAGS},
-	{AN7447_TCPC2_I2C_ADDR_FLAGS, AN7447_SPI2_I2C_ADDR_FLAGS},
-	{AN7447_TCPC3_I2C_ADDR_FLAGS, AN7447_SPI3_I2C_ADDR_FLAGS}
+	{ AN7447_TCPC0_I2C_ADDR_FLAGS, AN7447_SPI0_I2C_ADDR_FLAGS },
+	{ AN7447_TCPC1_I2C_ADDR_FLAGS, AN7447_SPI1_I2C_ADDR_FLAGS },
+	{ AN7447_TCPC2_I2C_ADDR_FLAGS, AN7447_SPI2_I2C_ADDR_FLAGS },
+	{ AN7447_TCPC3_I2C_ADDR_FLAGS, AN7447_SPI3_I2C_ADDR_FLAGS }
 };
 
 static inline int anx7447_reg_write(int port, int reg, int val)
 {
 	int rv = i2c_write8(tcpc_config[port].i2c_info.port,
-			    anx[port].i2c_slave_addr_flags,
-			    reg, val);
+			    anx[port].i2c_addr_flags, reg, val);
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
 	pd_device_accessed(port);
 #endif
@@ -75,8 +74,7 @@ static inline int anx7447_reg_write(int port, int reg, int val)
 static inline int anx7447_reg_read(int port, int reg, int *val)
 {
 	int rv = i2c_read8(tcpc_config[port].i2c_info.port,
-			   anx[port].i2c_slave_addr_flags,
-			   reg, val);
+			   anx[port].i2c_addr_flags, reg, val);
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
 	pd_device_accessed(port);
 #endif
@@ -153,7 +151,7 @@ static inline void anx7447_reg_write_or(int port, int reg, int v_or)
 		anx7447_reg_write(port, reg, (val | v_or));
 }
 
-#define ANX7447_FLASH_DONE_TIMEOUT_US	(100 * MSEC)
+#define ANX7447_FLASH_DONE_TIMEOUT_US (100 * MSEC)
 
 static int anx7447_wait_for_flash_done(int port)
 {
@@ -207,7 +205,7 @@ static int anx7447_flash_is_empty(int port)
 {
 	int r;
 
-	anx7447_reg_read(port, ANX7447_REG_OCM_VERSION, &r);
+	anx7447_reg_read(port, ANX7447_REG_OCM_MAIN_VERSION, &r);
 
 	return ((r == 0) ? 1 : 0);
 }
@@ -252,7 +250,7 @@ int anx7447_flash_erase(int port)
 }
 
 /* Add console command to erase OCM flash if needed. */
-static int command_anx_ocm(int argc, char **argv)
+static int command_anx_ocm(int argc, const char **argv)
 {
 	char *e = NULL;
 	int port;
@@ -272,58 +270,57 @@ static int command_anx_ocm(int argc, char **argv)
 		rv = anx7447_flash_erase_internal(
 			port, 1 /* write to console if empty */);
 		if (rv)
-			ccprintf("C%d: Failed to erase OCM flash (%d)\n",
-				 port, rv);
+			ccprintf("C%d: Failed to erase OCM flash (%d)\n", port,
+				 rv);
 	}
 
-	ccprintf("C%d: OCM flash is %sempty.\n",
-		port, anx7447_flash_is_empty(port) ? "" : "not ");
+	ccprintf("C%d: OCM flash is %sempty.\n", port,
+		 anx7447_flash_is_empty(port) ? "" : "not ");
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(anx_ocm, command_anx_ocm,
-			"port [erase]",
+DECLARE_CONSOLE_COMMAND(anx_ocm, command_anx_ocm, "port [erase]",
 			"Print OCM status or erases OCM for a given port.");
 #endif
 
 static int anx7447_init(int port)
 {
 	int rv, reg, i;
-	const struct usb_mux *me = &usb_muxes[port];
+	const struct usb_mux_chain *me = &usb_muxes[port];
+	bool unused;
 
 	ASSERT(port < CONFIG_USB_PD_PORT_MAX_COUNT);
 
 	memset(&anx[port], 0, sizeof(struct anx_state));
 
 	/*
-	 * find corresponding anx7447 SPI slave address according to
-	 * specified TCPC slave address
+	 * find corresponding anx7447 SPI address according to
+	 * specified TCPC address
 	 */
 	for (i = 0; i < ARRAY_SIZE(anx7447_i2c_addrs_flags); i++) {
-		if (I2C_GET_ADDR(tcpc_config[port].i2c_info.addr_flags) ==
-		    I2C_GET_ADDR(
-			    anx7447_i2c_addrs_flags[i].tcpc_slave_addr_flags)) {
-			anx[port].i2c_slave_addr_flags =
-				anx7447_i2c_addrs_flags[i].spi_slave_addr_flags;
+		if (I2C_STRIP_FLAGS(tcpc_config[port].i2c_info.addr_flags) ==
+		    I2C_STRIP_FLAGS(
+			    anx7447_i2c_addrs_flags[i].tcpc_addr_flags)) {
+			anx[port].i2c_addr_flags =
+				anx7447_i2c_addrs_flags[i].spi_addr_flags;
 			break;
 		}
 	}
-	if (!I2C_GET_ADDR(anx[port].i2c_slave_addr_flags)) {
-		ccprintf("TCPC I2C slave addr 0x%x is invalid for ANX7447\n",
-			 I2C_GET_ADDR(tcpc_config[port]
-				      .i2c_info.addr_flags));
+	if (!I2C_STRIP_FLAGS(anx[port].i2c_addr_flags)) {
+		ccprintf(
+			"TCPC I2C addr 0x%x is invalid for ANX7447\n",
+			I2C_STRIP_FLAGS(tcpc_config[port].i2c_info.addr_flags));
 		return EC_ERROR_UNKNOWN;
 	}
 
-
 	rv = tcpci_tcpm_init(port);
 	if (rv)
 		return rv;
 
 #ifdef CONFIG_USB_PD_TCPM_ANX7447_OCM_ERASE_COMMAND
 	/* Check and print OCM status to console. */
-	CPRINTS("C%d: OCM flash is %sempty",
-		port, anx7447_flash_is_empty(port) ? "" : "not ");
+	CPRINTS("C%d: OCM flash is %sempty", port,
+		anx7447_flash_is_empty(port) ? "" : "not ");
 #endif
 
 	/*
@@ -344,14 +341,11 @@ static int anx7447_init(int port)
 	if (rv)
 		return rv;
 
-	/*
-	 * Specifically disable voltage alarms, as VBUS_VOLTAGE_ALARM_HI may
-	 * trigger repeatedly despite being masked (b/153989733)
-	 */
-	rv = tcpc_update16(port, TCPC_REG_POWER_CTRL,
-			   TCPC_REG_POWER_CTRL_VBUS_VOL_MONITOR_DIS, MASK_SET);
-	if (rv)
-		return rv;
+	/* Set VBUS_VOLTAGE_ALARM_HI threshold */
+	RETURN_ERROR(
+		tcpc_write16(port, TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG, 0x3FF));
+	/* Set VCONN_VOLTAGE_ALARM_HI threshold to 6V */
+	RETURN_ERROR(tcpc_write16(port, VCONN_VOLTAGE_ALARM_HI_CFG, 0xF0));
 
 	/* ADC enable, use to monitor VBUS voltage */
 	rv = tcpc_read(port, ANX7447_REG_ADC_CTRL_1, &reg);
@@ -380,17 +374,25 @@ static int anx7447_init(int port)
 	if (rv)
 		return rv;
 
+	if (IS_ENABLED(CONFIG_USB_PD_FRS_TCPC))
+		/* Unmask FRSWAP signal detect */
+		tcpc_write(port, ANX7447_REG_VD_ALERT_MASK,
+			   ANX7447_FRSWAP_SIGNAL_DETECTED);
+
 #ifdef CONFIG_USB_PD_TCPM_MUX
 	/*
 	 * Run mux_set() here for considering CCD(Case-Closed Debugging) case
 	 * If this TCPC is not also the MUX then don't initialize to NONE
 	 */
-	while ((me != NULL) && (me->driver != &anx7447_usb_mux_driver))
-		me = me->next_mux;
+	while ((me != NULL) && (me->mux->driver != &anx7447_usb_mux_driver))
+		me = me->next;
 
-	if (me != NULL &&
-	    !(me->flags & USB_MUX_FLAG_NOT_TCPC))
-		rv = anx7447_mux_set(me, USB_PD_MUX_NONE);
+	/*
+	 * Note that bypassing the usb_mux API is okay for internal driver calls
+	 * since the task calling init already holds this port's mux lock.
+	 */
+	if (me != NULL && !(me->mux->flags & USB_MUX_FLAG_NOT_TCPC))
+		rv = anx7447_mux_set(me->mux, USB_PD_MUX_NONE, &unused);
 #endif /* CONFIG_USB_PD_TCPM_MUX */
 
 	return rv;
@@ -401,46 +403,104 @@ static int anx7447_release(int port)
 	return EC_SUCCESS;
 }
 
-#ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-static int anx7447_get_vbus_voltage(int port)
+static void anx7447_vendor_defined_alert(int port)
 {
-	int vbus_volt = 0;
+	int alert;
+
+	tcpc_read(port, ANX7447_REG_VD_ALERT, &alert);
 
-	tcpc_read16(port, TCPC_REG_VBUS_VOLTAGE, &vbus_volt);
+	/* write to clear alerts */
+	tcpc_write(port, ANX7447_REG_VD_ALERT, alert);
 
-	return vbus_volt;
+	if (IS_ENABLED(CONFIG_USB_PD_FRS_TCPC) &&
+	    alert & ANX7447_FRSWAP_SIGNAL_DETECTED)
+		pd_got_frs_signal(port);
 }
 
-int anx7447_set_power_supply_ready(int port)
+static void anx7447_tcpc_alert(int port)
 {
-	int count = 0;
+	int alert;
 
-	while (is_equal_greater_safe0v(port)) {
-		if (count >= 10)
-			break;
-		msleep(100);
-		count++;
-	}
+	tcpc_read16(port, TCPC_REG_ALERT, &alert);
+	if (alert & TCPC_REG_ALERT_VENDOR_DEF)
+		anx7447_vendor_defined_alert(port);
 
-	return tcpc_write(port, TCPC_REG_COMMAND, 0x77);
+	/* process and clear alert status */
+	tcpci_tcpc_alert(port);
 }
-#endif /* CONFIG_USB_PD_VBUS_DETECT_TCPC */
 
-int anx7447_power_supply_reset(int port)
+#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
+static int anx7447_tcpc_enter_low_power_mode(int port)
 {
-	return tcpc_write(port, TCPC_REG_COMMAND, 0x66);
+	int rv;
+
+	/*
+	 * if anx7447 is in source mode, need to set Rp to default before
+	 * entering the low power mode.
+	 */
+	if (pd_get_dual_role(port) == PD_DRP_FORCE_SOURCE) {
+		rv = tcpc_write(
+			port, TCPC_REG_ROLE_CTRL,
+			TCPC_REG_ROLE_CTRL_SET(TYPEC_NO_DRP, TYPEC_RP_USB,
+					       TYPEC_CC_RP, TYPEC_CC_RP));
+		if (rv) {
+			return rv;
+		}
+	}
+
+	return tcpci_enter_low_power_mode(port);
 }
+#endif
 
-int anx7447_board_charging_enable(int port, int enable)
+#ifdef CONFIG_USB_PD_FRS_TCPC
+static void anx7447_disable_frs_deferred(void)
 {
-	return tcpc_write(port, TCPC_REG_COMMAND, enable ? 0x55 : 0x44);
+	int i, val;
+
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		if (!anx_frs_dis[i])
+			continue;
+
+		anx_frs_dis[i] = false;
+		anx7447_reg_read(i, ANX7447_REG_ADDR_GPIO_CTRL_1, &val);
+		val &= ~ANX7447_ADDR_GPIO_CTRL_1_FRS_EN_DATA;
+		anx7447_reg_write(i, ANX7447_REG_ADDR_GPIO_CTRL_1, val);
+	}
 }
+DECLARE_DEFERRED(anx7447_disable_frs_deferred);
 
-static void anx7447_tcpc_alert(int port)
+static int anx7447_set_frs_enable(int port, int enable)
 {
-	/* process and clear alert status */
-	tcpci_tcpc_alert(port);
+	int val;
+
+	RETURN_ERROR(tcpc_update8(port, ANX7447_REG_FRSWAP_CTRL,
+				  ANX7447_FRSWAP_DETECT_ENABLE,
+				  enable ? MASK_SET : MASK_CLR));
+
+	if (!enable) {
+		/*
+		 * b/223087277#comment52: delay to disable FRS output to the
+		 * PPC. Some PPCs need the FRS_EN pin to stay asserted until the
+		 * VBUS dropped to a threshold under 5V to successfully source.
+		 * However, on some hubs with a larger cap, the VBUS might take
+		 * more than 10 ms.  This workaround is to delay the FRS_EN
+		 * deassertion to PPC for 30 ms, which should be enough for
+		 * most cases.
+		 */
+		anx_frs_dis[port] = true;
+		hook_call_deferred(&anx7447_disable_frs_deferred_data,
+				   30 * MSEC);
+		return EC_SUCCESS;
+	}
+
+	RETURN_ERROR(
+		anx7447_reg_read(port, ANX7447_REG_ADDR_GPIO_CTRL_1, &val));
+	val |= ANX7447_ADDR_GPIO_CTRL_1_FRS_EN_DATA;
+	RETURN_ERROR(
+		anx7447_reg_write(port, ANX7447_REG_ADDR_GPIO_CTRL_1, val));
+	return EC_SUCCESS;
 }
+#endif /* CONFIG_USB_PD_FRS_TCPC */
 
 /*
  * timestamp of the next possible toggle to ensure the 2-ms spacing
@@ -449,10 +509,15 @@ static void anx7447_tcpc_alert(int port)
 static uint64_t hpd_deadline[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 void anx7447_tcpc_update_hpd_status(const struct usb_mux *me,
-				    int hpd_lvl, int hpd_irq)
+				    mux_state_t mux_state, bool *ack_required)
 {
 	int reg = 0;
 	int port = me->usb_port;
+	int hpd_lvl = (mux_state & USB_PD_MUX_HPD_LVL) ? 1 : 0;
+	int hpd_irq = (mux_state & USB_PD_MUX_HPD_IRQ) ? 1 : 0;
+
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
 
 	/*
 	 * All calls within this method need to update to a mux_read/write calls
@@ -496,6 +561,33 @@ void anx7447_tcpc_clear_hpd_status(int port)
 static int anx7447_mux_init(const struct usb_mux *me)
 {
 	int port = me->usb_port;
+	int i;
+	bool unused;
+	const uint16_t tcpc_i2c_addr =
+		I2C_STRIP_FLAGS(tcpc_config[me->usb_port].i2c_info.addr_flags);
+	const uint16_t mux_i2c_addr =
+		I2C_STRIP_FLAGS(usb_muxes[port].mux->i2c_addr_flags);
+
+	/*
+	 * find corresponding anx7447 SPI address according to
+	 * specified MUX address from mux and tcpc i2c addr config.
+	 */
+	for (i = 0; i < ARRAY_SIZE(anx7447_i2c_addrs_flags); i++) {
+		uint16_t i2c_addr_key = I2C_STRIP_FLAGS(
+			anx7447_i2c_addrs_flags[i].tcpc_addr_flags);
+
+		if (i2c_addr_key == tcpc_i2c_addr ||
+		    i2c_addr_key == mux_i2c_addr) {
+			anx[port].i2c_addr_flags =
+				anx7447_i2c_addrs_flags[i].spi_addr_flags;
+			break;
+		}
+	}
+	if (!I2C_STRIP_FLAGS(anx[port].i2c_addr_flags)) {
+		ccprintf("TCPC I2C addr 0x%x is invalid for ANX7447\n",
+			 I2C_STRIP_FLAGS(usb_muxes[port].mux->i2c_addr_flags));
+		return EC_ERROR_UNKNOWN;
+	}
 
 	ASSERT(port < CONFIG_USB_PD_PORT_MAX_COUNT);
 
@@ -511,7 +603,7 @@ static int anx7447_mux_init(const struct usb_mux *me)
 	 * USB_PD_MUX_DP_ENABLED) when reinitialized, we need to force
 	 * initialize it to USB_PD_MUX_NONE
 	 */
-	return anx7447_mux_set(me, USB_PD_MUX_NONE);
+	return anx7447_mux_set(me, USB_PD_MUX_NONE, &unused);
 }
 
 #ifdef CONFIG_USB_PD_TCPM_ANX7447_AUX_PU_PD
@@ -527,8 +619,8 @@ static void anx7447_mux_safemode(const struct usb_mux *me, int on_off)
 		reg &= ~(ANX7447_REG_SAFE_MODE);
 
 	mux_write(me, ANX7447_REG_ANALOG_CTRL_9, reg);
-	CPRINTS("C%d set mux to safemode %s, reg = 0x%x",
-		me->usb_port, (on_off) ? "on" : "off", reg);
+	CPRINTS("C%d set mux to safemode %s, reg = 0x%x", me->usb_port,
+		(on_off) ? "on" : "off", reg);
 }
 
 static inline void anx7447_configure_aux_src(const struct usb_mux *me,
@@ -545,8 +637,8 @@ static inline void anx7447_configure_aux_src(const struct usb_mux *me,
 
 	mux_write(me, ANX7447_REG_ANALOG_CTRL_9, reg);
 
-	CPRINTS("C%d set aux_src to %s, reg = 0x%x",
-		me->usb_port, (on_off) ? "on" : "off", reg);
+	CPRINTS("C%d set aux_src to %s, reg = 0x%x", me->usb_port,
+		(on_off) ? "on" : "off", reg);
 }
 #endif
 
@@ -559,7 +651,8 @@ static inline void anx7447_configure_aux_src(const struct usb_mux *me,
  *
  * a2, a3, a10, a11, b2, b3, b10, b11 are pins on the USB-C connector.
  */
-static int anx7447_mux_set(const struct usb_mux *me, mux_state_t mux_state)
+static int anx7447_mux_set(const struct usb_mux *me, mux_state_t mux_state,
+			   bool *ack_required)
 {
 	int cc_direction;
 	mux_state_t mux_type;
@@ -567,10 +660,17 @@ static int anx7447_mux_set(const struct usb_mux *me, mux_state_t mux_state)
 	int rv;
 	int port = me->usb_port;
 
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
+	/* This driver treats safe mode as none */
+	if (mux_state & USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
+
 	cc_direction = mux_state & USB_PD_MUX_POLARITY_INVERTED;
 	mux_type = mux_state & USB_PD_MUX_DOCK;
-	CPRINTS("C%d mux_state = 0x%x, mux_type = 0x%x",
-		port, mux_state, mux_type);
+	CPRINTS("C%d mux_state = 0x%x, mux_type = 0x%x", port, mux_state,
+		mux_type);
 	if (cc_direction == 0) {
 		/* cc1 connection */
 		if (mux_type == USB_PD_MUX_DOCK) {
@@ -694,14 +794,10 @@ static int anx7447_set_cc(int port, int pull)
 }
 
 /* Override for tcpci_tcpm_set_polarity */
-static int anx7447_set_polarity(int port,
-				enum tcpc_cc_polarity polarity)
+static int anx7447_set_polarity(int port, enum tcpc_cc_polarity polarity)
 {
-	return tcpc_update8(port,
-			    TCPC_REG_TCPC_CTRL,
-			    TCPC_REG_TCPC_CTRL_SET(1),
-			    polarity_rm_dts(polarity)
-					? MASK_SET : MASK_CLR);
+	return tcpc_update8(port, TCPC_REG_TCPC_CTRL, TCPC_REG_TCPC_CTRL_SET(1),
+			    polarity_rm_dts(polarity) ? MASK_SET : MASK_CLR);
 }
 
 #ifdef CONFIG_CMD_TCPC_DUMP
@@ -771,6 +867,14 @@ const struct {
 		.name = "PAD_INTP_CTRL",
 		.addr = ANX7447_REG_PAD_INTP_CTRL,
 	},
+	{
+		.name = "OCM_MAIN_VERSION",
+		.addr = ANX7447_REG_OCM_MAIN_VERSION,
+	},
+	{
+		.name = "OCM_BUILD_VERSION",
+		.addr = ANX7447_REG_OCM_BUILD_VERSION,
+	},
 };
 
 /*
@@ -785,13 +889,73 @@ static void anx7447_dump_registers(int port)
 	for (i = 0; i < ARRAY_SIZE(anx7447_alt_regs); i++) {
 		anx7447_reg_read(port, anx7447_alt_regs[i].addr, &val);
 		ccprintf("  %-26s(ALT/0x%02x) =   0x%02x\n",
-				anx7447_alt_regs[i].name,
-				anx7447_alt_regs[i].addr, (uint8_t)val);
+			 anx7447_alt_regs[i].name, anx7447_alt_regs[i].addr,
+			 (uint8_t)val);
 		cflush();
 	}
 }
 #endif /* defined(CONFIG_CMD_TCPC_DUMP) */
 
+static int anx7447_get_chip_info(int port, int live,
+				 struct ec_response_pd_chip_info_v1 *chip_info)
+{
+	int main_version = 0x0, build_version = 0x0;
+
+	RETURN_ERROR(tcpci_get_chip_info(port, live, chip_info));
+
+	if (chip_info == NULL)
+		return EC_SUCCESS;
+
+	if (chip_info->fw_version_number == -1 || live) {
+		/*
+		 * Before reading ANX7447 SPI target address 0x7e for
+		 * new added FW version, need to read ANX7447 I2c
+		 * target address 0x58 first to wake up ANX7447.
+		 */
+		tcpc_read(port, ANX7447_REG_OCM_MAIN_VERSION, &main_version);
+
+		RETURN_ERROR(anx7447_reg_read(
+			port, ANX7447_REG_OCM_MAIN_VERSION, &main_version));
+		RETURN_ERROR(anx7447_reg_read(
+			port, ANX7447_REG_OCM_BUILD_VERSION, &build_version));
+	}
+
+	chip_info->fw_version_number = (main_version << 8) | build_version;
+
+	/* The minimum OCM firmware version to support FRS. */
+	if (IS_ENABLED(CONFIG_USB_PD_FRS))
+		chip_info->min_req_fw_version_number = 0x0115;
+
+	return EC_SUCCESS;
+}
+
+enum ec_error_list anx7447_set_bist_test_mode(const int port, const bool enable)
+{
+	/*
+	 * Set CC debounce type as millisecond if enable BIST mode,
+	 * otherwise microsecond
+	 */
+	RETURN_ERROR(tcpc_update8(port, ANX7447_REG_TCPC_CTRL_1, CC_DEBOUNCE_MS,
+				  enable ? MASK_SET : MASK_CLR));
+	/*
+	 * Set CC debounce time to 2ms if enable BIST mode,
+	 * otherwise set debounce time to 10us
+	 */
+	RETURN_ERROR(tcpc_write(port, ANX7447_REG_CC_DEBOUNCE_TIME,
+				enable ? 2 : 10));
+
+	anx7447_bist_test_mode[port] = enable;
+
+	return EC_SUCCESS;
+}
+
+enum ec_error_list anx7447_get_bist_test_mode(const int port, bool *enable)
+{
+	*enable = anx7447_bist_test_mode[port];
+
+	return EC_SUCCESS;
+}
+
 /*
  * ANX7447 is a TCPCI compatible port controller, with some caveats.
  * It seems to require both CC lines to be set always, instead of just
@@ -800,40 +964,50 @@ static void anx7447_dump_registers(int port)
  * overrides for set_cc and set_polarity.
  */
 const struct tcpm_drv anx7447_tcpm_drv = {
-	.init			= &anx7447_init,
-	.release		= &anx7447_release,
-	.get_cc			= &tcpci_tcpm_get_cc,
+	.init = &anx7447_init,
+	.release = &anx7447_release,
+	.get_cc = &tcpci_tcpm_get_cc,
 #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	.check_vbus_level	= &tcpci_tcpm_check_vbus_level,
+	.check_vbus_level = &tcpci_tcpm_check_vbus_level,
 #endif
-	.select_rp_value	= &tcpci_tcpm_select_rp_value,
-	.set_cc			= &anx7447_set_cc,
-	.set_polarity		= &anx7447_set_polarity,
+	/*
+	 * b:214893572#comment33: ANX7447 dev_cap_1 reports VBUS_MEASURE
+	 * unsupported, however, it actually does.
+	 */
+	.get_vbus_voltage = &tcpci_get_vbus_voltage_no_check,
+	.select_rp_value = &tcpci_tcpm_select_rp_value,
+	.set_cc = &anx7447_set_cc,
+	.set_polarity = &anx7447_set_polarity,
 #ifdef CONFIG_USB_PD_DECODE_SOP
-	.sop_prime_disable	= &tcpci_tcpm_sop_prime_disable,
+	.sop_prime_enable = &tcpci_tcpm_sop_prime_enable,
 #endif
-	.set_vconn		= &tcpci_tcpm_set_vconn,
-	.set_msg_header		= &tcpci_tcpm_set_msg_header,
-	.set_rx_enable		= &tcpci_tcpm_set_rx_enable,
-	.get_message_raw	= &tcpci_tcpm_get_message_raw,
-	.transmit		= &tcpci_tcpm_transmit,
-	.tcpc_alert		= &anx7447_tcpc_alert,
+	.set_vconn = &tcpci_tcpm_set_vconn,
+	.set_msg_header = &tcpci_tcpm_set_msg_header,
+	.set_rx_enable = &tcpci_tcpm_set_rx_enable,
+	.get_message_raw = &tcpci_tcpm_get_message_raw,
+	.transmit = &tcpci_tcpm_transmit,
+	.tcpc_alert = &anx7447_tcpc_alert,
 #ifdef CONFIG_USB_PD_DISCHARGE_TCPC
-	.tcpc_discharge_vbus	= &tcpci_tcpc_discharge_vbus,
+	.tcpc_discharge_vbus = &tcpci_tcpc_discharge_vbus,
 #endif
 #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-	.drp_toggle		= anx7447_tcpc_drp_toggle,
-#endif
-	.get_chip_info		= &tcpci_get_chip_info,
-#ifdef CONFIG_USBC_PPC
-	.set_snk_ctrl		= &tcpci_tcpm_set_snk_ctrl,
-	.set_src_ctrl		= &tcpci_tcpm_set_src_ctrl,
+	.drp_toggle = anx7447_tcpc_drp_toggle,
 #endif
+	.get_chip_info = &anx7447_get_chip_info,
+	.set_snk_ctrl = &tcpci_tcpm_set_snk_ctrl,
+	.set_src_ctrl = &tcpci_tcpm_set_src_ctrl,
+	.get_snk_ctrl = &tcpci_tcpm_get_snk_ctrl,
+	.get_src_ctrl = &tcpci_tcpm_get_src_ctrl,
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	.enter_low_power_mode	= &tcpci_enter_low_power_mode,
+	.enter_low_power_mode = &anx7447_tcpc_enter_low_power_mode,
+#endif
+#ifdef CONFIG_USB_PD_FRS_TCPC
+	.set_frs_enable = &anx7447_set_frs_enable,
 #endif
+	.set_bist_test_mode = &anx7447_set_bist_test_mode,
+	.get_bist_test_mode = &anx7447_get_bist_test_mode,
 #ifdef CONFIG_CMD_TCPC_DUMP
-	.dump_registers		= &anx7447_dump_registers,
+	.dump_registers = &anx7447_dump_registers,
 #endif
 };
 
@@ -842,6 +1016,6 @@ const struct usb_mux_driver anx7447_usb_mux_driver = {
 	.init = anx7447_mux_init,
 	.set = anx7447_mux_set,
 	.get = anx7447_mux_get,
+	.enter_low_power_mode = &tcpci_tcpm_mux_enter_low_power,
 };
 #endif /* CONFIG_USB_PD_TCPM_MUX */
-
diff --git a/driver/tcpm/anx7447.h b/driver/tcpm/anx7447.h
index 94b8bd994b..0fd546e264 100644
--- a/driver/tcpm/anx7447.h
+++ b/driver/tcpm/anx7447.h
@@ -1,8 +1,9 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "driver/tcpm/anx7447_public.h"
 #include "usb_mux.h"
 
 /* USB Power delivery port management */
@@ -10,140 +11,161 @@
 #ifndef __CROS_EC_USB_PD_TCPM_ANX7447_H
 #define __CROS_EC_USB_PD_TCPM_ANX7447_H
 
-/* Registers: TCPC slave address used */
-#define ANX7447_REG_TCPC_SWITCH_0	0xB4
-#define ANX7447_REG_TCPC_SWITCH_1	0xB5
-#define ANX7447_REG_TCPC_AUX_SWITCH	0xB6
-
-#define ANX7447_REG_INTR_ALERT_MASK_0	0xC9
-
-#define ANX7447_REG_TCPC_CTRL_2		0xCD
-#define ANX7447_REG_ENABLE_VBUS_PROTECT	0x20
-
-#define ANX7447_REG_ADC_CTRL_1		0xBF
-#define ANX7447_REG_ADCFSM_EN		0x20
-
-/* Registers: SPI slave address used */
-#define ANX7447_REG_INTP_SOURCE_0	0x67
-
-#define ANX7447_REG_HPD_CTRL_0		0x7E
-#define ANX7447_REG_HPD_MODE		0x01
-#define ANX7447_REG_HPD_OUT		0x02
-#define ANX7447_REG_HPD_IRQ0		0x04
-#define ANX7447_REG_HPD_PLUG		0x08
-#define ANX7447_REG_HPD_UNPLUG		0x10
-
-#define ANX7447_REG_HPD_DEGLITCH_H	0x80
-#define ANX7447_REG_HPD_DETECT		0x80
-#define ANX7447_REG_HPD_OEN		0x40
-
-#define ANX7447_REG_PAD_INTP_CTRL	0x85
-
-#define ANX7447_REG_INTP_MASK_0		0x86
-
-#define ANX7447_REG_INTP_CTRL_0		0x9E
-
-#define ANX7447_REG_ANALOG_CTRL_8	0xA8
-#define ANX7447_REG_VCONN_OCP_MASK	0x0C
-#define ANX7447_REG_VCONN_OCP_240mA	0x00
-#define ANX7447_REG_VCONN_OCP_310mA	0x04
-#define ANX7447_REG_VCONN_OCP_370mA	0x08
-#define ANX7447_REG_VCONN_OCP_440mA	0x0C
-
-#define ANX7447_REG_ANALOG_CTRL_10	0xAA
-#define ANX7447_REG_CABLE_DET_DIG	0x40
-
-#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_MASK	0x38
-#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_19US	0x00
-#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_38US	0x08
-#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_76US    0x10
-#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_152US   0x18
-#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_303US   0x20
-#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_607US	0x28
-#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_1210US	0x30
-#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_2430US	0x38
-
-#define ANX7447_REG_ANALOG_CTRL_9	0xA9
-#define ANX7447_REG_SAFE_MODE		0x80
-#define ANX7447_REG_R_AUX_RES_PULL_SRC	0x20
+/* Registers: TCPC address used */
+#define ANX7447_REG_TCPC_SWITCH_0 0xB4
+#define ANX7447_REG_TCPC_SWITCH_1 0xB5
+#define ANX7447_REG_TCPC_AUX_SWITCH 0xB6
+#define VCONN_VOLTAGE_ALARM_HI_CFG 0xB7
+
+#define ANX7447_REG_INTR_ALERT_MASK_0 0xC9
+
+#define ANX7447_REG_TCPC_CTRL_2 0xCD
+#define ANX7447_REG_ENABLE_VBUS_PROTECT 0x20
+
+#define ANX7447_REG_ADC_CTRL_1 0xBF
+#define ANX7447_REG_ADCFSM_EN 0x20
+
+/* Registers: SPI address used */
+#define ANX7447_REG_INTP_SOURCE_0 0x67
+
+#define ANX7447_REG_HPD_CTRL_0 0x7E
+#define ANX7447_REG_HPD_MODE 0x01
+#define ANX7447_REG_HPD_OUT 0x02
+#define ANX7447_REG_HPD_IRQ0 0x04
+#define ANX7447_REG_HPD_PLUG 0x08
+#define ANX7447_REG_HPD_UNPLUG 0x10
+
+#define ANX7447_REG_HPD_DEGLITCH_H 0x80
+#define ANX7447_REG_HPD_DETECT 0x80
+#define ANX7447_REG_HPD_OEN 0x40
+
+#define ANX7447_REG_PAD_INTP_CTRL 0x85
+
+#define ANX7447_REG_INTP_MASK_0 0x86
+
+#define ANX7447_REG_ADDR_GPIO_CTRL_1 0x89
+
+#define ANX7447_REG_TCPC_CTRL_1 0x9D
+#define CC_DEBOUNCE_MS BIT(3)
+#define CC_DEBOUNCE_TIME_HI_BIT BIT(0)
+#define ANX7447_REG_INTP_CTRL_0 0x9E
+#define ANX7447_REG_CC_DEBOUNCE_TIME 0x9F
+
+#define ANX7447_REG_ANALOG_CTRL_8 0xA8
+#define ANX7447_REG_VCONN_OCP_MASK 0x0C
+#define ANX7447_REG_VCONN_OCP_240mA 0x00
+#define ANX7447_REG_VCONN_OCP_310mA 0x04
+#define ANX7447_REG_VCONN_OCP_370mA 0x08
+#define ANX7447_REG_VCONN_OCP_440mA 0x0C
+
+#define ANX7447_REG_ANALOG_CTRL_10 0xAA
+#define ANX7447_REG_CABLE_DET_DIG 0x40
+
+#define ANX7447_REG_FRSWAP_CTRL 0xAB
+
+#define ANX7447_REG_T_CHK_VBUS_TIMER 0xBB
+
+#define ANX7447_REG_VD_ALERT_MASK 0xC7
+#define ANX7447_REG_VD_ALERT 0xC8
+
+#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_MASK 0x38
+#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_19US 0x00
+#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_38US 0x08
+#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_76US 0x10
+#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_152US 0x18
+#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_303US 0x20
+#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_607US 0x28
+#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_1210US 0x30
+#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_2430US 0x38
+
+#define ANX7447_REG_ANALOG_CTRL_9 0xA9
+#define ANX7447_REG_SAFE_MODE 0x80
+#define ANX7447_REG_R_AUX_RES_PULL_SRC 0x20
+
+/* FRSWAP_CTRL bit definitions */
+#define ANX7447_FR_SWAP BIT(7)
+#define ANX7447_FR_SWAP_EN BIT(6)
+#define ANX7447_R_FRSWAP_CONTROL_SELECT BIT(3)
+#define ANX7447_R_SIGNAL_FRSWAP BIT(2)
+#define ANX7447_TRANSMIT_FRSWAP_SIGNAL BIT(1)
+#define ANX7447_FRSWAP_DETECT_ENABLE BIT(0)
+
+/* ADDR_GPIO_CTRL_1 bit definitions */
+#define ANX7447_ADDR_GPIO_CTRL_1_FRS_EN_DATA BIT(3)
+#define ANX7447_ADDR_GPIO_CTRL_1_FRS_EN_OEN BIT(2)
+
+/* VD_ALERT and VD_ALERT_MASK  bit definitions */
+#define ANX7447_TIMER_1_DONE BIT(7)
+#define ANX7447_TIMER_0_DONE BIT(6)
+#define ANX7447_SOFT_INTP BIT(5)
+#define ANX7447_VCONN_VOLTAGE_ALARM_LO BIT(4)
+#define ANX7447_VCONN_VOLTAGE_ALARM_HI BIT(3)
+#define ANX7447_VCONN_OCP_OCCURRED BIT(2)
+#define ANX7447_VBUS_OCP_OCCURRED BIT(1)
+#define ANX7447_FRSWAP_SIGNAL_DETECTED BIT(0)
 
 /*
  * This section of defines are only required to support the config option
  * CONFIG_USB_PD_TCPM_ANX7447_OCM_ERASE_COMMAND.
  */
 /* SPI registers used for OCM flash operations */
-#define ANX7447_DELAY_IN_US		(20*1000)
-
-#define ANX7447_REG_R_RAM_CTRL			0x05
-#define ANX7447_REG_R_FLASH_RW_CTRL		0x30
-#define ANX7447_REG_R_FLASH_STATUS_0		0x31
-#define ANX7447_REG_FLASH_INST_TYPE		0x33
-#define ANX7447_REG_FLASH_ERASE_TYPE		0x34
-#define ANX7447_REG_OCM_CTRL_0			0x6E
-#define ANX7447_REG_ADDR_GPIO_CTRL_0		0x88
-#define ANX7447_REG_OCM_VERSION			0xB4
+#define ANX7447_DELAY_IN_US (20 * 1000)
+
+#define ANX7447_REG_R_RAM_CTRL 0x05
+#define ANX7447_REG_R_FLASH_RW_CTRL 0x30
+#define ANX7447_REG_R_FLASH_STATUS_0 0x31
+#define ANX7447_REG_FLASH_INST_TYPE 0x33
+#define ANX7447_REG_FLASH_ERASE_TYPE 0x34
+#define ANX7447_REG_OCM_CTRL_0 0x6E
+#define ANX7447_REG_ADDR_GPIO_CTRL_0 0x88
+#define ANX7447_REG_OCM_MAIN_VERSION 0xB4
+#define ANX7447_REG_OCM_BUILD_VERSION 0xB5
 
 /* R_RAM_CTRL bit definitions */
-#define ANX7447_R_RAM_CTRL_FLASH_DONE			(1<<7)
+#define ANX7447_R_RAM_CTRL_FLASH_DONE (1 << 7)
 
 /* R_FLASH_RW_CTRL bit definitions */
-#define ANX7447_R_FLASH_RW_CTRL_GENERAL_INST_EN		(1<<6)
-#define ANX7447_R_FLASH_RW_CTRL_FLASH_ERASE_EN		(1<<5)
-#define ANX7447_R_FLASH_RW_CTRL_WRITE_STATUS_EN		(1<<2)
-#define ANX7447_R_FLASH_RW_CTRL_FLASH_READ		(1<<1)
-#define ANX7447_R_FLASH_RW_CTRL_FLASH_WRITE		(1<<0)
+#define ANX7447_R_FLASH_RW_CTRL_GENERAL_INST_EN (1 << 6)
+#define ANX7447_R_FLASH_RW_CTRL_FLASH_ERASE_EN (1 << 5)
+#define ANX7447_R_FLASH_RW_CTRL_WRITE_STATUS_EN (1 << 2)
+#define ANX7447_R_FLASH_RW_CTRL_FLASH_READ (1 << 1)
+#define ANX7447_R_FLASH_RW_CTRL_FLASH_WRITE (1 << 0)
 
 /* R_FLASH_STATUS_0 definitions */
-#define ANX7447_FLASH_STATUS_SPI_STATUS_0		0x43
+#define ANX7447_FLASH_STATUS_SPI_STATUS_0 0x43
 
 /* FLASH_ERASE_TYPE bit definitions */
-#define ANX7447_FLASH_INST_TYPE_WRITEENABLE		0x06
-#define ANX7447_FLASH_ERASE_TYPE_CHIPERASE		0x60
+#define ANX7447_FLASH_INST_TYPE_WRITEENABLE 0x06
+#define ANX7447_FLASH_ERASE_TYPE_CHIPERASE 0x60
 
 /* OCM_CTRL_0 bit definitions */
-#define ANX7447_OCM_CTRL_OCM_RESET			(1<<6)
+#define ANX7447_OCM_CTRL_OCM_RESET (1 << 6)
 
 /* ADDR_GPIO_CTRL_0 bit definitions */
-#define ANX7447_ADDR_GPIO_CTRL_0_SPI_WP			(1<<7)
-#define ANX7447_ADDR_GPIO_CTRL_0_SPI_CLK_ENABLE		(1<<6)
+#define ANX7447_ADDR_GPIO_CTRL_0_SPI_WP (1 << 7)
+#define ANX7447_ADDR_GPIO_CTRL_0_SPI_CLK_ENABLE (1 << 6)
 /* End of defines used for CONFIG_USB_PD_TCPM_ANX7447_OCM_ERASE_COMMAND */
 
 struct anx7447_i2c_addr {
-	uint16_t	tcpc_slave_addr_flags;
-	uint16_t	spi_slave_addr_flags;
+	uint16_t tcpc_addr_flags;
+	uint16_t spi_addr_flags;
 };
 
-#define AN7447_TCPC0_I2C_ADDR_FLAGS	0x2C
-#define AN7447_TCPC1_I2C_ADDR_FLAGS	0x2B
-#define AN7447_TCPC2_I2C_ADDR_FLAGS	0x2A
-#define AN7447_TCPC3_I2C_ADDR_FLAGS	0x29
-
-#define AN7447_SPI0_I2C_ADDR_FLAGS	0x3F
-#define AN7447_SPI1_I2C_ADDR_FLAGS	0x37
-#define AN7447_SPI2_I2C_ADDR_FLAGS	0x32
-#define AN7447_SPI3_I2C_ADDR_FLAGS	0x31
-
 /*
  * Time TEST_R must be held high for a reset
  */
-#define ANX74XX_RESET_HOLD_MS	1
+#define ANX74XX_RESET_HOLD_MS 1
 /*
  * Time after TEST_R reset to wait for eFuse loading
  */
-#define ANX74XX_RESET_FINISH_MS	2
-
-int anx7447_set_power_supply_ready(int port);
-int anx7447_power_supply_reset(int port);
-int anx7447_board_charging_enable(int port, int enable);
+#define ANX74XX_RESET_FINISH_MS 2
 
 void anx7447_hpd_mode_en(int port);
 void anx7447_hpd_output_en(int port);
 
-extern const struct tcpm_drv anx7447_tcpm_drv;
-extern const struct usb_mux_driver anx7447_usb_mux_driver;
 void anx7447_tcpc_clear_hpd_status(int port);
 void anx7447_tcpc_update_hpd_status(const struct usb_mux *me,
-				    int hpd_lvl, int hpd_irq);
+				    mux_state_t mux_state, bool *ack_required);
 
 /**
  * Erase OCM flash if it's not empty
diff --git a/driver/tcpm/anx74xx.c b/driver/tcpm/anx74xx.c
index a775abd172..9e3a975754 100644
--- a/driver/tcpm/anx74xx.c
+++ b/driver/tcpm/anx74xx.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -7,16 +7,17 @@
 
 /* Type-C port manager for Analogix's anx74xx chips */
 
-#include "console.h"
 #include "anx74xx.h"
+#include "console.h"
 #include "task.h"
-#include "tcpci.h"
-#include "tcpm.h"
+#include "tcpm/tcpci.h"
+#include "tcpm/tcpm.h"
 #include "timer.h"
 #include "usb_charge.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
 #include "usb_pd_tcpc.h"
+#include "usb_pd_tcpm.h"
 #include "util.h"
 
 #if !defined(CONFIG_USB_PD_TCPM_TCPCI)
@@ -29,23 +30,24 @@
 #error "Please undefine PD 3.0.  See b/159253723 for details"
 #endif
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 struct anx_state {
-	int	polarity;
-	int	vconn_en;
-	int	mux_state;
+	int polarity;
+	int vconn_en;
+	int mux_state;
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	int	prev_mode;
+	int prev_mode;
 #endif
 };
-#define clear_recvd_msg_int(port) do {\
-		int reg, rv; \
+#define clear_recvd_msg_int(port)                                      \
+	do {                                                           \
+		int reg, rv;                                           \
 		rv = tcpc_read(port, ANX74XX_REG_RECVD_MSG_INT, &reg); \
-		if (!rv) \
-			tcpc_write(port, ANX74XX_REG_RECVD_MSG_INT, \
-			reg | 0x01); \
+		if (!rv)                                               \
+			tcpc_write(port, ANX74XX_REG_RECVD_MSG_INT,    \
+				   reg | 0x01);                        \
 	} while (0)
 
 static struct anx_state anx[CONFIG_USB_PD_PORT_MAX_COUNT];
@@ -232,10 +234,15 @@ static void anx74xx_tcpc_discharge_vbus(int port, int enable)
 static uint64_t hpd_deadline[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 void anx74xx_tcpc_update_hpd_status(const struct usb_mux *me,
-				    int hpd_lvl, int hpd_irq)
+				    mux_state_t mux_state, bool *ack_required)
 {
 	int reg;
 	int port = me->usb_port;
+	int hpd_lvl = (mux_state & USB_PD_MUX_HPD_LVL) ? 1 : 0;
+	int hpd_irq = (mux_state & USB_PD_MUX_HPD_IRQ) ? 1 : 0;
+
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
 
 	mux_read(me, ANX74XX_REG_HPD_CTRL_0, &reg);
 	if (hpd_lvl)
@@ -285,37 +292,35 @@ static int anx74xx_tcpm_mux_init(const struct usb_mux *me)
 static int anx74xx_tcpm_mux_enter_safe_mode(int port)
 {
 	int reg;
-	const struct usb_mux *me = &usb_muxes[port];
+	const struct usb_mux *me = usb_muxes[port].mux;
 
 	if (mux_read(me, ANX74XX_REG_ANALOG_CTRL_2, &reg))
 		return EC_ERROR_UNKNOWN;
-	if (mux_write(me, ANX74XX_REG_ANALOG_CTRL_2, reg |
-		       ANX74XX_REG_MODE_TRANS))
+	if (mux_write(me, ANX74XX_REG_ANALOG_CTRL_2,
+		      reg | ANX74XX_REG_MODE_TRANS))
 		return EC_ERROR_UNKNOWN;
 
-
 	return EC_SUCCESS;
 }
 
 static int anx74xx_tcpm_mux_exit_safe_mode(int port)
 {
 	int reg;
-	const struct usb_mux *me = &usb_muxes[port];
+	const struct usb_mux *me = usb_muxes[port].mux;
 
 	if (mux_read(me, ANX74XX_REG_ANALOG_CTRL_2, &reg))
 		return EC_ERROR_UNKNOWN;
-	if (mux_write(me, ANX74XX_REG_ANALOG_CTRL_2, reg &
-		       ~ANX74XX_REG_MODE_TRANS))
+	if (mux_write(me, ANX74XX_REG_ANALOG_CTRL_2,
+		      reg & ~ANX74XX_REG_MODE_TRANS))
 		return EC_ERROR_UNKNOWN;
 
-
 	return EC_SUCCESS;
 }
 
 static int anx74xx_tcpm_mux_exit(int port)
 {
 	int reg;
-	const struct usb_mux *me = &usb_muxes[port];
+	const struct usb_mux *me = usb_muxes[port].mux;
 
 	/*
 	 * Safe mode must be entered before any changes are made to the mux
@@ -350,13 +355,12 @@ static int anx74xx_tcpm_mux_exit(int port)
 	return EC_SUCCESS;
 }
 
-
 static int anx74xx_mux_aux_to_sbu(int port, int polarity, int enabled)
 {
 	int reg;
 	const int aux_mask = ANX74XX_REG_AUX_SWAP_SET_CC2 |
-		ANX74XX_REG_AUX_SWAP_SET_CC1;
-	const struct usb_mux *me = &usb_muxes[port];
+			     ANX74XX_REG_AUX_SWAP_SET_CC1;
+	const struct usb_mux *me = usb_muxes[port].mux;
 
 	/*
 	 * Get the current value of analog_ctrl_2 register. Note, that safe mode
@@ -384,14 +388,21 @@ static int anx74xx_mux_aux_to_sbu(int port, int polarity, int enabled)
 	return EC_SUCCESS;
 }
 
-static int anx74xx_tcpm_mux_set(const struct usb_mux *me,
-				mux_state_t mux_state)
+static int anx74xx_tcpm_mux_set(const struct usb_mux *me, mux_state_t mux_state,
+				bool *ack_required)
 {
 	int ctrl5;
 	int ctrl1 = 0;
 	int rv;
 	int port = me->usb_port;
 
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
+	/* This driver treats safe mode as none */
+	if (mux_state & USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
+
 	if (!(mux_state & ~USB_PD_MUX_POLARITY_INVERTED)) {
 		anx[port].mux_state = mux_state;
 		return anx74xx_tcpm_mux_exit(port);
@@ -437,7 +448,7 @@ static int anx74xx_tcpm_mux_set(const struct usb_mux *me,
 	} else if (!mux_state) {
 		return anx74xx_tcpm_mux_exit(port);
 	} else {
-		return  EC_ERROR_UNIMPLEMENTED;
+		return EC_ERROR_UNIMPLEMENTED;
 	}
 
 	/*
@@ -493,8 +504,7 @@ static int anx74xx_init_analog(int port)
 	/* Analog settings for chip */
 	rv |= tcpc_write(port, ANX74XX_REG_HPD_CONTROL,
 			 ANX74XX_REG_HPD_OP_MODE);
-	rv |= tcpc_write(port, ANX74XX_REG_HPD_CTRL_0,
-			 ANX74XX_REG_HPD_DEFAULT);
+	rv |= tcpc_write(port, ANX74XX_REG_HPD_CTRL_0, ANX74XX_REG_HPD_DEFAULT);
 	if (rv)
 		return rv;
 	rv = tcpc_read(port, ANX74XX_REG_GPIO_CTRL_4_5, &reg);
@@ -515,9 +525,7 @@ static int anx74xx_init_analog(int port)
 }
 
 static int anx74xx_send_message(int port, uint16_t header,
-				const uint32_t *payload,
-				int type,
-				uint8_t len)
+				const uint32_t *payload, int type, uint8_t len)
 {
 	int reg, rv = EC_SUCCESS;
 	uint8_t *buf = NULL;
@@ -526,12 +534,12 @@ static int anx74xx_send_message(int port, uint16_t header,
 	/* Soft Reset Message type = 1101 and Number of Data Object = 0 */
 	if ((header & 0x700f) == 0x000d) {
 		/*
-		* When sending soft reset,
-		* the Rx buffer of ANX3429 shall be clear
-		*/
+		 * When sending soft reset,
+		 * the Rx buffer of ANX3429 shall be clear
+		 */
 		rv = tcpc_read(port, ANX74XX_REG_CTRL_FW, &reg);
-		rv |= tcpc_write(
-			port, ANX74XX_REG_CTRL_FW, reg | CLEAR_RX_BUFFER);
+		rv |= tcpc_write(port, ANX74XX_REG_CTRL_FW,
+				 reg | CLEAR_RX_BUFFER);
 		if (rv)
 			return EC_ERROR_UNKNOWN;
 		tcpc_write(port, ANX74XX_REG_RECVD_MSG_INT, 0xFF);
@@ -563,7 +571,8 @@ static int anx74xx_send_message(int port, uint16_t header,
 						*buf);
 			else
 				rv = tcpc_write(port,
-					ANX74XX_REG_TX_START_ADDR_1 + i - 18,
+						ANX74XX_REG_TX_START_ADDR_1 +
+							i - 18,
 						*buf);
 			if (rv) {
 				num_retry++;
@@ -596,15 +605,13 @@ static int anx74xx_send_message(int port, uint16_t header,
 	return rv;
 }
 
-static int anx74xx_read_pd_obj(int port,
-				uint8_t *buf,
-				int plen)
+static int anx74xx_read_pd_obj(int port, uint8_t *buf, int plen)
 {
 	int rv = EC_SUCCESS, i;
 	int reg, addr = ANX74XX_REG_PD_RX_DATA_OBJ;
 
 	/* Read PD data objects from ANX */
-	for (i = 0; i < plen ; i++) {
+	for (i = 0; i < plen; i++) {
 		/* Register sequence changes for last two bytes, if
 		 * plen is greater than 26
 		 */
@@ -653,7 +660,7 @@ static int anx74xx_check_cc_type(int cc_reg)
 }
 
 static int anx74xx_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2)
+			       enum tcpc_cc_voltage_status *cc2)
 {
 	int rv = EC_SUCCESS;
 	int reg = 0;
@@ -718,7 +725,6 @@ static int anx74xx_tcpm_select_rp_value(int port, int rp)
 	return EC_SUCCESS;
 }
 
-
 static int anx74xx_cc_software_ctrl(int port, int enable)
 {
 	int rv;
@@ -749,7 +755,7 @@ static int anx74xx_tcpm_set_cc(int port, int pull)
 
 	switch (pull) {
 	case TYPEC_CC_RP:
-	/* Enable Rp */
+		/* Enable Rp */
 		rv |= tcpc_read(port, ANX74XX_REG_ANALOG_STATUS, &reg);
 		if (rv)
 			return EC_ERROR_UNKNOWN;
@@ -757,7 +763,7 @@ static int anx74xx_tcpm_set_cc(int port, int pull)
 		rv |= tcpc_write(port, ANX74XX_REG_ANALOG_STATUS, reg);
 		break;
 	case TYPEC_CC_RD:
-	/* Enable Rd */
+		/* Enable Rd */
 		rv |= tcpc_read(port, ANX74XX_REG_ANALOG_STATUS, &reg);
 		if (rv)
 			return EC_ERROR_UNKNOWN;
@@ -775,7 +781,8 @@ static int anx74xx_tcpm_set_cc(int port, int pull)
 static int anx74xx_tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity)
 {
 	int reg, mux_state, rv = EC_SUCCESS;
-	const struct usb_mux *me = &usb_muxes[port];
+	const struct usb_mux *me = usb_muxes[port].mux;
+	bool unused;
 
 	rv |= tcpc_read(port, ANX74XX_REG_CC_SOFTWARE_CTRL, &reg);
 	if (polarity_rm_dts(polarity)) /* Inform ANX to use CC2 */
@@ -791,7 +798,7 @@ static int anx74xx_tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity)
 	mux_state = anx[port].mux_state & ~USB_PD_MUX_POLARITY_INVERTED;
 	if (polarity_rm_dts(polarity))
 		mux_state |= USB_PD_MUX_POLARITY_INVERTED;
-	anx74xx_tcpm_mux_set(me, mux_state);
+	anx74xx_tcpm_mux_set(me, mux_state, &unused);
 #endif
 	return rv;
 }
@@ -823,7 +830,7 @@ static int anx74xx_tcpm_set_vconn(int port, int enable)
 	if (reg & ANX74XX_REG_REPLY_SOP_EN) {
 		if (enable) {
 			reg |= ANX74XX_REG_REPLY_SOP_1_EN |
-				ANX74XX_REG_REPLY_SOP_2_EN;
+			       ANX74XX_REG_REPLY_SOP_2_EN;
 		} else {
 			reg &= ~(ANX74XX_REG_REPLY_SOP_1_EN |
 				 ANX74XX_REG_REPLY_SOP_2_EN);
@@ -838,7 +845,8 @@ static int anx74xx_tcpm_set_vconn(int port, int enable)
 static int anx74xx_tcpm_set_msg_header(int port, int power_role, int data_role)
 {
 	return tcpc_write(port, ANX74XX_REG_TX_AUTO_GOODCRC_1,
-		  ANX74XX_REG_AUTO_GOODCRC_SET(!!data_role, !!power_role));
+			  ANX74XX_REG_AUTO_GOODCRC_SET(!!data_role,
+						       !!power_role));
 }
 
 static int anx74xx_tcpm_set_rx_enable(int port, int enable)
@@ -904,50 +912,48 @@ static int anx74xx_tcpm_get_message_raw(int port, uint32_t *payload, int *head)
 	return anx74xx_read_pd_obj(port, (uint8_t *)payload, len);
 }
 
-static int anx74xx_tcpm_transmit(int port, enum tcpm_transmit_type type,
-		  uint16_t header,
-		  const uint32_t *data)
+static int anx74xx_tcpm_transmit(int port, enum tcpci_msg_type type,
+				 uint16_t header, const uint32_t *data)
 {
 	uint8_t len = 0;
 	int ret = 0, reg = 0;
 
 	switch (type) {
 	/* ANX is aware of type */
-	case TCPC_TX_SOP:
-	case TCPC_TX_SOP_PRIME:
-	case TCPC_TX_SOP_PRIME_PRIME:
+	case TCPCI_MSG_SOP:
+	case TCPCI_MSG_SOP_PRIME:
+	case TCPCI_MSG_SOP_PRIME_PRIME:
 		len = PD_HEADER_CNT(header) * 4 + 2;
-		ret = anx74xx_send_message(port, header,
-						  data, type, len);
+		ret = anx74xx_send_message(port, header, data, type, len);
 		break;
-	case TCPC_TX_HARD_RESET:
-	/* Request HARD RESET */
+	case TCPCI_MSG_TX_HARD_RESET:
+		/* Request HARD RESET */
 		tcpc_read(port, ANX74XX_REG_TX_CTRL_1, &reg);
 		reg |= ANX74XX_REG_TX_HARD_RESET_REQ;
 		ret = tcpc_write(port, ANX74XX_REG_TX_CTRL_1, reg);
-	/*After Hard Reset, TCPM shall disable goodCRC*/
+		/*After Hard Reset, TCPM shall disable goodCRC*/
 		anx74xx_tcpm_set_auto_good_crc(port, 0);
 		break;
-	case TCPC_TX_CABLE_RESET:
-	/* Request CABLE RESET */
+	case TCPCI_MSG_CABLE_RESET:
+		/* Request CABLE RESET */
 		tcpc_read(port, ANX74XX_REG_TX_CTRL_1, &reg);
 		reg |= ANX74XX_REG_TX_CABLE_RESET_REQ;
 		ret = tcpc_write(port, ANX74XX_REG_TX_CTRL_1, reg);
 		break;
-	case TCPC_TX_BIST_MODE_2:
-	/* Request BIST MODE 2 */
-		reg = ANX74XX_REG_TX_BIST_START
-				| ANX74XX_REG_TX_BIXT_FOREVER | (0x02 << 4);
+	case TCPCI_MSG_TX_BIST_MODE_2:
+		/* Request BIST MODE 2 */
+		reg = ANX74XX_REG_TX_BIST_START | ANX74XX_REG_TX_BIXT_FOREVER |
+		      (0x02 << 4);
 		ret = tcpc_write(port, ANX74XX_REG_TX_BIST_CTRL, reg);
 		msleep(1);
 		ret = tcpc_write(port, ANX74XX_REG_TX_BIST_CTRL,
-					reg | ANX74XX_REG_TX_BIST_ENABLE);
+				 reg | ANX74XX_REG_TX_BIST_ENABLE);
 		msleep(30);
 		tcpc_read(port, ANX74XX_REG_TX_BIST_CTRL, &reg);
 		ret = tcpc_write(port, ANX74XX_REG_TX_BIST_CTRL,
-					reg | ANX74XX_REG_TX_BIST_STOP);
+				 reg | ANX74XX_REG_TX_BIST_STOP);
 		ret = tcpc_write(port, ANX74XX_REG_TX_BIST_CTRL,
-					reg & (~ANX74XX_REG_TX_BIST_STOP));
+				 reg & (~ANX74XX_REG_TX_BIST_STOP));
 		ret = tcpc_write(port, ANX74XX_REG_TX_BIST_CTRL, 0);
 		break;
 	default:
@@ -994,7 +1000,8 @@ void anx74xx_tcpc_alert(int port)
 		/* Ensure we don't loop endlessly */
 		if (failed_attempts >= MAX_ALLOW_FAILED_RX_READS) {
 			CPRINTF("C%d Cannot consume RX buffer after %d failed "
-				"attempts!", port, failed_attempts);
+				"attempts!",
+				port, failed_attempts);
 			/*
 			 * The port is in a bad state, we don't want to consume
 			 * all EC resources so suspend the port for a little
@@ -1011,7 +1018,7 @@ void anx74xx_tcpc_alert(int port)
 
 	if (reg & ANX74XX_REG_IRQ_CC_STATUS_INT)
 		/* CC status changed, wake task */
-		task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_CC, 0);
+		task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_CC);
 
 	/* Read and clear extended alert register 1 */
 	reg = 0;
@@ -1020,9 +1027,9 @@ void anx74xx_tcpc_alert(int port)
 
 #ifdef CONFIG_USB_PD_DECODE_SOP
 	if (reg & ANX74XX_REG_EXT_SOP)
-		msg_sop[port] = PD_MSG_SOP;
+		msg_sop[port] = TCPCI_MSG_SOP;
 	else if (reg & ANX74XX_REG_EXT_SOP_PRIME)
-		msg_sop[port] = PD_MSG_SOP_PRIME;
+		msg_sop[port] = TCPCI_MSG_SOP_PRIME;
 #endif
 
 	/* Check for Hard Reset done bit */
@@ -1037,13 +1044,13 @@ void anx74xx_tcpc_alert(int port)
 
 #ifdef CONFIG_USB_PD_DECODE_SOP
 	if (reg & ANX74XX_REG_EXT_SOP_PRIME_PRIME)
-		msg_sop[port] = PD_MSG_SOP_PRIME_PRIME;
+		msg_sop[port] = TCPCI_MSG_SOP_PRIME_PRIME;
 #endif
 
 	if (reg & ANX74XX_REG_EXT_HARD_RST) {
 		/* hard reset received */
 		task_set_event(PD_PORT_TO_TASK_ID(port),
-			PD_EVENT_RX_HARD_RESET, 0);
+			       PD_EVENT_RX_HARD_RESET);
 	}
 }
 
@@ -1072,7 +1079,8 @@ static int anx74xx_tcpm_init(int port)
 
 	/* Initialize interrupt polarity */
 	reg = tcpc_config[port].flags & TCPC_FLAGS_ALERT_ACTIVE_HIGH ?
-		ANX74XX_REG_IRQ_POL_HIGH : ANX74XX_REG_IRQ_POL_LOW;
+		      ANX74XX_REG_IRQ_POL_HIGH :
+		      ANX74XX_REG_IRQ_POL_LOW;
 	rv |= tcpc_write(port, ANX74XX_REG_IRQ_STATUS, reg);
 
 	/* unmask interrupts */
@@ -1119,7 +1127,7 @@ static int anx74xx_tcpm_init(int port)
 }
 
 static int anx74xx_get_chip_info(int port, int live,
-			struct ec_response_pd_chip_info_v1 *chip_info)
+				 struct ec_response_pd_chip_info_v1 *chip_info)
 {
 	int rv = tcpci_get_chip_info(port, live, chip_info);
 	int val;
@@ -1159,30 +1167,34 @@ static int anx74xx_tcpm_release(int port)
 }
 
 const struct tcpm_drv anx74xx_tcpm_drv = {
-	.init			= &anx74xx_tcpm_init,
-	.release		= &anx74xx_tcpm_release,
-	.get_cc			= &anx74xx_tcpm_get_cc,
+	.init = &anx74xx_tcpm_init,
+	.release = &anx74xx_tcpm_release,
+	.get_cc = &anx74xx_tcpm_get_cc,
 #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	.check_vbus_level	= &anx74xx_tcpm_check_vbus_level,
+	.check_vbus_level = &anx74xx_tcpm_check_vbus_level,
 #endif
-	.select_rp_value	= &anx74xx_tcpm_select_rp_value,
-	.set_cc			= &anx74xx_tcpm_set_cc,
-	.set_polarity		= &anx74xx_tcpm_set_polarity,
-	.set_vconn		= &anx74xx_tcpm_set_vconn,
-	.set_msg_header		= &anx74xx_tcpm_set_msg_header,
-	.set_rx_enable		= &anx74xx_tcpm_set_rx_enable,
-	.get_message_raw	= &anx74xx_tcpm_get_message_raw,
-	.transmit		= &anx74xx_tcpm_transmit,
-	.tcpc_alert		= &anx74xx_tcpc_alert,
+	.select_rp_value = &anx74xx_tcpm_select_rp_value,
+	.set_cc = &anx74xx_tcpm_set_cc,
+	.set_polarity = &anx74xx_tcpm_set_polarity,
+#ifdef CONFIG_USB_PD_DECODE_SOP
+	.sop_prime_enable = &tcpci_tcpm_sop_prime_enable,
+#endif
+	.set_vconn = &anx74xx_tcpm_set_vconn,
+	.set_msg_header = &anx74xx_tcpm_set_msg_header,
+	.set_rx_enable = &anx74xx_tcpm_set_rx_enable,
+	.get_message_raw = &anx74xx_tcpm_get_message_raw,
+	.transmit = &anx74xx_tcpm_transmit,
+	.tcpc_alert = &anx74xx_tcpc_alert,
 #ifdef CONFIG_USB_PD_DISCHARGE_TCPC
-	.tcpc_discharge_vbus	= &anx74xx_tcpc_discharge_vbus,
+	.tcpc_discharge_vbus = &anx74xx_tcpc_discharge_vbus,
 #endif
-	.get_chip_info		= &anx74xx_get_chip_info,
+	.get_chip_info = &anx74xx_get_chip_info,
 #if defined(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE) && \
-		defined(CONFIG_USB_PD_TCPC_LOW_POWER)
-	.drp_toggle		= &anx74xx_tcpc_drp_toggle,
-	.enter_low_power_mode	= &anx74xx_enter_low_power_mode,
+	defined(CONFIG_USB_PD_TCPC_LOW_POWER)
+	.drp_toggle = &anx74xx_tcpc_drp_toggle,
+	.enter_low_power_mode = &anx74xx_enter_low_power_mode,
 #endif
+	.set_bist_test_mode = &tcpci_set_bist_test_mode,
 };
 
 #ifdef CONFIG_CMD_I2C_STRESS_TEST_TCPC
diff --git a/driver/tcpm/anx74xx.h b/driver/tcpm/anx74xx.h
index d7ba62bda3..e814d85371 100644
--- a/driver/tcpm/anx74xx.h
+++ b/driver/tcpm/anx74xx.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -18,42 +18,42 @@
 #define ANX74XX_I2C_ADDR3_FLAGS 0x3E
 #define ANX74XX_I2C_ADDR4_FLAGS 0x40
 
-#define ANX74XX_REG_IRQ_POL_LOW		0x00
-#define ANX74XX_REG_IRQ_POL_HIGH		0x02
+#define ANX74XX_REG_IRQ_POL_LOW 0x00
+#define ANX74XX_REG_IRQ_POL_HIGH 0x02
 
-#define ANX74XX_REG_VENDOR_ID_L         0x00
-#define ANX74XX_REG_VENDOR_ID_H         0x01
-#define ANX74XX_VENDOR_ID               0xAAAA
+#define ANX74XX_REG_VENDOR_ID_L 0x00
+#define ANX74XX_REG_VENDOR_ID_H 0x01
+#define ANX74XX_VENDOR_ID 0xAAAA
 
 /* ANX F/W version：0x50:0x44 which contains otp firmware version */
-#define ANX74XX_REG_FW_VERSION          0x44
+#define ANX74XX_REG_FW_VERSION 0x44
 
-#define ANX74XX_REG_IRQ_STATUS		0x53
+#define ANX74XX_REG_IRQ_STATUS 0x53
 
-#define ANX74XX_REG_INTP_VCONN_CTRL	0x33
-#define ANX74XX_REG_VCONN_DISABLE		0x0f
-#define ANX74XX_REG_VCONN_1_ENABLE		BIT(4)
-#define ANX74XX_REG_VCONN_2_ENABLE		BIT(5)
-#define ANX74XX_REG_R_INTERRUPT_OPEN_DRAIN	BIT(2)
+#define ANX74XX_REG_INTP_VCONN_CTRL 0x33
+#define ANX74XX_REG_VCONN_DISABLE 0x0f
+#define ANX74XX_REG_VCONN_1_ENABLE BIT(4)
+#define ANX74XX_REG_VCONN_2_ENABLE BIT(5)
+#define ANX74XX_REG_R_INTERRUPT_OPEN_DRAIN BIT(2)
 
-#define ANX74XX_STANDBY_MODE		(0)
-#define ANX74XX_NORMAL_MODE		(1)
+#define ANX74XX_STANDBY_MODE (0)
+#define ANX74XX_NORMAL_MODE (1)
 
-#define ANX74XX_REG_TX_CTRL_1		0x81
-#define ANX74XX_REG_TX_HARD_RESET_REQ	BIT(1)
-#define ANX74XX_REG_TX_CABLE_RESET_REQ	BIT(2)
+#define ANX74XX_REG_TX_CTRL_1 0x81
+#define ANX74XX_REG_TX_HARD_RESET_REQ BIT(1)
+#define ANX74XX_REG_TX_CABLE_RESET_REQ BIT(2)
 
-#define ANX74XX_REG_TX_CTRL_2		0x82
-#define ANX74XX_REG_TX_WR_FIFO		0x83
-#define ANX74XX_REG_TX_FIFO_CTRL		0x9a
-#define ANX74XX_REG_TX_HEADER_L		0x2c
-#define ANX74XX_REG_TX_HEADER_H		0x2d
-#define ANX74XX_REG_TX_START_ADDR_0		0x6d
-#define ANX74XX_REG_TX_START_ADDR_1		0xd0
+#define ANX74XX_REG_TX_CTRL_2 0x82
+#define ANX74XX_REG_TX_WR_FIFO 0x83
+#define ANX74XX_REG_TX_FIFO_CTRL 0x9a
+#define ANX74XX_REG_TX_HEADER_L 0x2c
+#define ANX74XX_REG_TX_HEADER_H 0x2d
+#define ANX74XX_REG_TX_START_ADDR_0 0x6d
+#define ANX74XX_REG_TX_START_ADDR_1 0xd0
 
-#define ANX74XX_REG_CTRL_COMMAND		0xdb
-#define ANX74XX_REG_TX_SEND_DATA_REQ	BIT(0)
-#define ANX74XX_REG_TX_HARD_RST_REQ	BIT(1)
+#define ANX74XX_REG_CTRL_COMMAND 0xdb
+#define ANX74XX_REG_TX_SEND_DATA_REQ BIT(0)
+#define ANX74XX_REG_TX_HARD_RST_REQ BIT(1)
 
 #define ANX74XX_REG_TX_BIST_CTRL 0x9D
 #define ANX74XX_REG_TX_BIST_MODE BIT(4)
@@ -62,165 +62,163 @@
 #define ANX74XX_REG_TX_BIST_ENABLE BIT(1)
 #define ANX74XX_REG_TX_BIST_START BIT(0)
 
-#define ANX74XX_REG_PD_HEADER		0x69
-#define ANX74XX_REG_PD_RX_DATA_OBJ		0x11
-#define ANX74XX_REG_PD_RX_DATA_OBJ_M	0x4d
-
-#define ANX74XX_REG_ANALOG_STATUS		0x40
-#define ANX74XX_REG_VBUS_STATUS		BIT(4)
-#define ANX74XX_REG_CC_PULL_RD		0xfd
-#define ANX74XX_REG_CC_PULL_RP		0x02
-
-
-#define ANX74XX_REG_TX_AUTO_GOODCRC_2	0x94
-#define ANX74XX_REG_REPLY_SOP_EN        BIT(3)
-#define ANX74XX_REG_REPLY_SOP_1_EN      BIT(4)
-#define ANX74XX_REG_REPLY_SOP_2_EN      BIT(5)
-
-#define ANX74XX_REG_TX_AUTO_GOODCRC_1	0x9c
-#define ANX74XX_REG_SPEC_REV_BIT_POS	(3)
-#define ANX74XX_REG_DATA_ROLE_BIT_POS	(2)
-#define ANX74XX_REG_PWR_ROLE_BIT_POS	(1)
-#define ANX74XX_REG_AUTO_GOODCRC_EN	BIT(0)
+#define ANX74XX_REG_PD_HEADER 0x69
+#define ANX74XX_REG_PD_RX_DATA_OBJ 0x11
+#define ANX74XX_REG_PD_RX_DATA_OBJ_M 0x4d
+
+#define ANX74XX_REG_ANALOG_STATUS 0x40
+#define ANX74XX_REG_VBUS_STATUS BIT(4)
+#define ANX74XX_REG_CC_PULL_RD 0xfd
+#define ANX74XX_REG_CC_PULL_RP 0x02
+
+#define ANX74XX_REG_TX_AUTO_GOODCRC_2 0x94
+#define ANX74XX_REG_REPLY_SOP_EN BIT(3)
+#define ANX74XX_REG_REPLY_SOP_1_EN BIT(4)
+#define ANX74XX_REG_REPLY_SOP_2_EN BIT(5)
+
+#define ANX74XX_REG_TX_AUTO_GOODCRC_1 0x9c
+#define ANX74XX_REG_SPEC_REV_BIT_POS (3)
+#define ANX74XX_REG_DATA_ROLE_BIT_POS (2)
+#define ANX74XX_REG_PWR_ROLE_BIT_POS (1)
+#define ANX74XX_REG_AUTO_GOODCRC_EN BIT(0)
 #define ANX74XX_REG_AUTO_GOODCRC_SET(drole, prole)    \
 	((PD_REV20 << ANX74XX_REG_SPEC_REV_BIT_POS) | \
-	((drole) << ANX74XX_REG_DATA_ROLE_BIT_POS)  | \
-	((prole) << ANX74XX_REG_PWR_ROLE_BIT_POS)   | \
-	ANX74XX_REG_AUTO_GOODCRC_EN)
-
-
-#define ANX74XX_REG_ANALOG_CTRL_0		0x41
-#define ANX74XX_REG_R_PIN_CABLE_DET		BIT(7)
-
-#define ANX74XX_REG_ANALOG_CTRL_1		0x42
-#define ANX74XX_REG_ANALOG_CTRL_5		0x46
-#define ANX74XX_REG_ANALOG_CTRL_6		0x47
-#define ANX74XX_REG_CC_PULL_RP_36K	0x00
-#define ANX74XX_REG_CC_PULL_RP_12K	0x01
-#define ANX74XX_REG_CC_PULL_RP_4K	0x02
-
-#define ANX74XX_REG_R_SWITCH_CC_CLR	0x0f
-#define ANX74XX_REG_R_SWITCH_CC2_SET	0x10
-#define ANX74XX_REG_R_SWITCH_CC1_SET	0x20
-#define ANX74XX_REG_AUX_SWAP_SET_CC1	0x30
-#define ANX74XX_REG_AUX_SWAP_SET_CC2	0xc0
-
-#define ANX74XX_REG_ANALOG_CTRL_11		0x4c
-#define ANX74XX_REG_ANALOG_CTRL_12		0x4d
-
-#define ANX74XX_REG_MUX_ML0_RX2		BIT(0)
-#define ANX74XX_REG_MUX_ML0_RX1		BIT(1)
-#define ANX74XX_REG_MUX_ML3_RX2		BIT(2)
-#define ANX74XX_REG_MUX_ML3_RX1		BIT(3)
-#define ANX74XX_REG_MUX_SSRX_RX2	BIT(4)
-#define ANX74XX_REG_MUX_SSRX_RX1	BIT(5)
-#define ANX74XX_REG_MUX_ML1_TX2		BIT(6)
-#define ANX74XX_REG_MUX_ML1_TX1		BIT(7)
-
-#define ANX74XX_REG_MUX_ML2_TX2		BIT(4)
-#define ANX74XX_REG_MUX_ML2_TX1		BIT(5)
-#define ANX74XX_REG_MUX_SSTX_TX2	BIT(6)
-#define ANX74XX_REG_MUX_SSTX_TX1	BIT(7)
-
-#define ANX74XX_REG_CC_SOFTWARE_CTRL	0x4a
-#define ANX74XX_REG_CC_SW_CTRL_ENABLE	0x01
-#define ANX74XX_REG_TX_MODE_ENABLE		0x04
-
-#define ANX74XX_REG_SELECT_CC1		0x02
-
-#define ANX74XX_REG_GPIO_CTRL_4_5		0x3f
-#define ANX74XX_REG_VBUS_OP_ENABLE		0x04
-#define ANX74XX_REG_VBUS_GPIO_MODE		0xfe
-
-#define ANX74XX_REG_IRQ_EXT_MASK_1		0x3b
-#define ANX74XX_REG_IRQ_EXT_MASK_2		0x3c
-#define ANX74XX_REG_IRQ_EXT_SOURCE_1	0x3e
-#define ANX74XX_REG_EXT_SOP                     BIT(6)
-#define ANX74XX_REG_EXT_SOP_PRIME               BIT(7)
-#define ANX74XX_REG_IRQ_EXT_SOURCE_2	0x4e
-#define ANX74XX_REG_EXT_SOP_PRIME_PRIME         BIT(0)
-#define ANX74XX_REG_EXT_HARD_RST		BIT(2)
-#define ANX74XX_REG_IRQ_EXT_SOURCE_3	0x4f
-#define ANX74XX_REG_CLEAR_SOFT_IRQ		BIT(2)
-
-#define ANX74XX_REG_IRQ_SOURCE_RECV_MSG	0x6b
-#define ANX74XX_REG_IRQ_CC_MSG_INT		BIT(0)
-#define ANX74XX_REG_IRQ_CC_STATUS_INT	BIT(1)
-#define ANX74XX_REG_IRQ_GOOD_CRC_INT	BIT(2)
-#define ANX74XX_REG_IRQ_TX_FAIL_INT	BIT(3)
-#define ANX74XX_REG_IRQ_SOURCE_RECV_MSG_MASK	0x6c
-
-#define ANX74XX_REG_CLEAR_SET_BITS		0xff
-#define ANX74XX_REG_ALERT_HARD_RST_RECV		BIT(6)
-#define ANX74XX_REG_ALERT_MSG_RECV		BIT(5)
-#define ANX74XX_REG_ALERT_TX_MSG_ERROR	BIT(4)
-#define ANX74XX_REG_ALERT_TX_ACK_RECV	BIT(3)
-#define ANX74XX_REG_ALERT_TX_CABLE_RESETOK	BIT(2)
-#define ANX74XX_REG_ALERT_TX_HARD_RESETOK	BIT(1)
-#define ANX74XX_REG_ALERT_CC_CHANGE	BIT(0)
-
-#define ANX74XX_REG_ANALOG_CTRL_2		0x43
-#define ANX74XX_REG_MODE_TRANS		0x01
-
-#define ANX74XX_REG_SET_VBUS		0x20
-
-#define ANX74XX_REG_ANALOG_CTRL_7		0x48
-#define ANX74XX_REG_STATUS_CC_RD		0x01
-#define ANX74XX_REG_STATUS_CC_RA		0x03
-#define ANX74XX_REG_STATUS_CC1(reg)	((reg & 0x0C) >> 2)
-#define ANX74XX_REG_STATUS_CC2(reg)	((reg & 0x03) >> 0)
-
-#define ANX74XX_REG_HPD_CONTROL		0xfd
-
-#define ANX74XX_REG_HPD_CTRL_0		0x36
-#define ANX74XX_REG_DISCHARGE_CTRL     0x80
-#define ANX74XX_REG_HPD_OP_MODE		0x08
-#define ANX74XX_REG_HPD_DEFAULT		0x00
-#define ANX74XX_REG_HPD_OUT_DATA		0x10
+	 ((drole) << ANX74XX_REG_DATA_ROLE_BIT_POS) | \
+	 ((prole) << ANX74XX_REG_PWR_ROLE_BIT_POS) |  \
+	 ANX74XX_REG_AUTO_GOODCRC_EN)
+
+#define ANX74XX_REG_ANALOG_CTRL_0 0x41
+#define ANX74XX_REG_R_PIN_CABLE_DET BIT(7)
+
+#define ANX74XX_REG_ANALOG_CTRL_1 0x42
+#define ANX74XX_REG_ANALOG_CTRL_5 0x46
+#define ANX74XX_REG_ANALOG_CTRL_6 0x47
+#define ANX74XX_REG_CC_PULL_RP_36K 0x00
+#define ANX74XX_REG_CC_PULL_RP_12K 0x01
+#define ANX74XX_REG_CC_PULL_RP_4K 0x02
+
+#define ANX74XX_REG_R_SWITCH_CC_CLR 0x0f
+#define ANX74XX_REG_R_SWITCH_CC2_SET 0x10
+#define ANX74XX_REG_R_SWITCH_CC1_SET 0x20
+#define ANX74XX_REG_AUX_SWAP_SET_CC1 0x30
+#define ANX74XX_REG_AUX_SWAP_SET_CC2 0xc0
+
+#define ANX74XX_REG_ANALOG_CTRL_11 0x4c
+#define ANX74XX_REG_ANALOG_CTRL_12 0x4d
+
+#define ANX74XX_REG_MUX_ML0_RX2 BIT(0)
+#define ANX74XX_REG_MUX_ML0_RX1 BIT(1)
+#define ANX74XX_REG_MUX_ML3_RX2 BIT(2)
+#define ANX74XX_REG_MUX_ML3_RX1 BIT(3)
+#define ANX74XX_REG_MUX_SSRX_RX2 BIT(4)
+#define ANX74XX_REG_MUX_SSRX_RX1 BIT(5)
+#define ANX74XX_REG_MUX_ML1_TX2 BIT(6)
+#define ANX74XX_REG_MUX_ML1_TX1 BIT(7)
+
+#define ANX74XX_REG_MUX_ML2_TX2 BIT(4)
+#define ANX74XX_REG_MUX_ML2_TX1 BIT(5)
+#define ANX74XX_REG_MUX_SSTX_TX2 BIT(6)
+#define ANX74XX_REG_MUX_SSTX_TX1 BIT(7)
+
+#define ANX74XX_REG_CC_SOFTWARE_CTRL 0x4a
+#define ANX74XX_REG_CC_SW_CTRL_ENABLE 0x01
+#define ANX74XX_REG_TX_MODE_ENABLE 0x04
+
+#define ANX74XX_REG_SELECT_CC1 0x02
+
+#define ANX74XX_REG_GPIO_CTRL_4_5 0x3f
+#define ANX74XX_REG_VBUS_OP_ENABLE 0x04
+#define ANX74XX_REG_VBUS_GPIO_MODE 0xfe
+
+#define ANX74XX_REG_IRQ_EXT_MASK_1 0x3b
+#define ANX74XX_REG_IRQ_EXT_MASK_2 0x3c
+#define ANX74XX_REG_IRQ_EXT_SOURCE_1 0x3e
+#define ANX74XX_REG_EXT_SOP BIT(6)
+#define ANX74XX_REG_EXT_SOP_PRIME BIT(7)
+#define ANX74XX_REG_IRQ_EXT_SOURCE_2 0x4e
+#define ANX74XX_REG_EXT_SOP_PRIME_PRIME BIT(0)
+#define ANX74XX_REG_EXT_HARD_RST BIT(2)
+#define ANX74XX_REG_IRQ_EXT_SOURCE_3 0x4f
+#define ANX74XX_REG_CLEAR_SOFT_IRQ BIT(2)
+
+#define ANX74XX_REG_IRQ_SOURCE_RECV_MSG 0x6b
+#define ANX74XX_REG_IRQ_CC_MSG_INT BIT(0)
+#define ANX74XX_REG_IRQ_CC_STATUS_INT BIT(1)
+#define ANX74XX_REG_IRQ_GOOD_CRC_INT BIT(2)
+#define ANX74XX_REG_IRQ_TX_FAIL_INT BIT(3)
+#define ANX74XX_REG_IRQ_SOURCE_RECV_MSG_MASK 0x6c
+
+#define ANX74XX_REG_CLEAR_SET_BITS 0xff
+#define ANX74XX_REG_ALERT_HARD_RST_RECV BIT(6)
+#define ANX74XX_REG_ALERT_MSG_RECV BIT(5)
+#define ANX74XX_REG_ALERT_TX_MSG_ERROR BIT(4)
+#define ANX74XX_REG_ALERT_TX_ACK_RECV BIT(3)
+#define ANX74XX_REG_ALERT_TX_CABLE_RESETOK BIT(2)
+#define ANX74XX_REG_ALERT_TX_HARD_RESETOK BIT(1)
+#define ANX74XX_REG_ALERT_CC_CHANGE BIT(0)
+
+#define ANX74XX_REG_ANALOG_CTRL_2 0x43
+#define ANX74XX_REG_MODE_TRANS 0x01
+
+#define ANX74XX_REG_SET_VBUS 0x20
+
+#define ANX74XX_REG_ANALOG_CTRL_7 0x48
+#define ANX74XX_REG_STATUS_CC_RD 0x01
+#define ANX74XX_REG_STATUS_CC_RA 0x03
+#define ANX74XX_REG_STATUS_CC1(reg) ((reg & 0x0C) >> 2)
+#define ANX74XX_REG_STATUS_CC2(reg) ((reg & 0x03) >> 0)
+
+#define ANX74XX_REG_HPD_CONTROL 0xfd
+
+#define ANX74XX_REG_HPD_CTRL_0 0x36
+#define ANX74XX_REG_DISCHARGE_CTRL 0x80
+#define ANX74XX_REG_HPD_OP_MODE 0x08
+#define ANX74XX_REG_HPD_DEFAULT 0x00
+#define ANX74XX_REG_HPD_OUT_DATA 0x10
 
 #define ANX74XX_REG_RECVD_MSG_INT 0x98
-#define ANX74XX_REG_CC_STATUS     0x99
-#define ANX74XX_REG_CTRL_FW  0x2E
+#define ANX74XX_REG_CC_STATUS 0x99
+#define ANX74XX_REG_CTRL_FW 0x2E
 #define CLEAR_RX_BUFFER (1)
-#define ANX74XX_REG_POWER_DOWN_CTRL	0x0d
-#define ANX74XX_REG_STATUS_CC1_VRD_USB	BIT(7)
-#define ANX74XX_REG_STATUS_CC1_VRD_1P5	BIT(6)
-#define ANX74XX_REG_STATUS_CC1_VRD_3P0	BIT(5)
-#define ANX74XX_REG_STATUS_CC2_VRD_USB	BIT(4)
-#define ANX74XX_REG_STATUS_CC2_VRD_1P5	BIT(3)
-#define ANX74XX_REG_STATUS_CC2_VRD_3P0	BIT(2)
+#define ANX74XX_REG_POWER_DOWN_CTRL 0x0d
+#define ANX74XX_REG_STATUS_CC1_VRD_USB BIT(7)
+#define ANX74XX_REG_STATUS_CC1_VRD_1P5 BIT(6)
+#define ANX74XX_REG_STATUS_CC1_VRD_3P0 BIT(5)
+#define ANX74XX_REG_STATUS_CC2_VRD_USB BIT(4)
+#define ANX74XX_REG_STATUS_CC2_VRD_1P5 BIT(3)
+#define ANX74XX_REG_STATUS_CC2_VRD_3P0 BIT(2)
 
 /* defined in the inter-bock Spec: 4.2.10 CC Detect Status */
-#define ANX74XX_REG_CC_STATUS_MASK  0xf
-#define BIT_VALUE_OF_SRC_CC_RD      0x01
-#define BIT_VALUE_OF_SRC_CC_RA      0x02
+#define ANX74XX_REG_CC_STATUS_MASK 0xf
+#define BIT_VALUE_OF_SRC_CC_RD 0x01
+#define BIT_VALUE_OF_SRC_CC_RA 0x02
 #define BIT_VALUE_OF_SNK_CC_DEFAULT 0x04
-#define BIT_VALUE_OF_SNK_CC_1_P_5   0x08
-#define BIT_VALUE_OF_SNK_CC_3_P_0   0x0C
-#define ANX74XX_CC_RA_MASK (BIT_VALUE_OF_SRC_CC_RA | \
-			    (BIT_VALUE_OF_SRC_CC_RA << 4))
-#define ANX74XX_CC_RD_MASK (BIT_VALUE_OF_SRC_CC_RD | \
-			    (BIT_VALUE_OF_SRC_CC_RD << 4))
+#define BIT_VALUE_OF_SNK_CC_1_P_5 0x08
+#define BIT_VALUE_OF_SNK_CC_3_P_0 0x0C
+#define ANX74XX_CC_RA_MASK \
+	(BIT_VALUE_OF_SRC_CC_RA | (BIT_VALUE_OF_SRC_CC_RA << 4))
+#define ANX74XX_CC_RD_MASK \
+	(BIT_VALUE_OF_SRC_CC_RD | (BIT_VALUE_OF_SRC_CC_RD << 4))
 
 /*
  * RESETN low to PWR_EN low delay
  */
-#define ANX74XX_RST_L_PWR_L_DELAY_MS	1
+#define ANX74XX_RST_L_PWR_L_DELAY_MS 1
 /*
  * minimum power off-to-on delay to reset chip
  */
-#define ANX74XX_PWR_L_PWR_H_DELAY_MS	10
+#define ANX74XX_PWR_L_PWR_H_DELAY_MS 10
 /*
  * parameter T4: PWR_EN high to RESETN high delay
  */
-#define ANX74XX_PWR_H_RST_H_DELAY_MS	10
+#define ANX74XX_PWR_H_RST_H_DELAY_MS 10
 
 extern const struct tcpm_drv anx74xx_tcpm_drv;
 extern const struct usb_mux_driver anx74xx_tcpm_usb_mux_driver;
 void anx74xx_tcpc_set_vbus(int port, int enable);
 void anx74xx_tcpc_clear_hpd_status(int port);
 void anx74xx_tcpc_update_hpd_status(const struct usb_mux *me,
-				    int hpd_lvl, int hpd_irq);
+				    mux_state_t mux_state, bool *ack_required);
 
 #ifdef CONFIG_CMD_I2C_STRESS_TEST_TCPC
 extern struct i2c_stress_test_dev anx74xx_i2c_stress_test_dev;
diff --git a/driver/tcpm/anx7688.c b/driver/tcpm/anx7688.c
index 1c6785f406..277edd0217 100644
--- a/driver/tcpm/anx7688.c
+++ b/driver/tcpm/anx7688.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,30 +6,30 @@
 /* ANX7688 port manager */
 
 #include "hooks.h"
-#include "tcpci.h"
-#include "tcpm.h"
+#include "tcpm/tcpci.h"
+#include "tcpm/tcpm.h"
 #include "timer.h"
 #include "usb_mux.h"
 
 #if defined(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE) || \
-	defined(CONFIG_USB_PD_TCPC_LOW_POWER) || \
+	defined(CONFIG_USB_PD_TCPC_LOW_POWER) ||    \
 	defined(CONFIG_USB_PD_DISCHARGE_TCPC)
 #error "Unsupported config options of anx7688 PD driver"
 #endif
 
-#define ANX7688_VENDOR_ALERT    BIT(15)
+#define ANX7688_VENDOR_ALERT BIT(15)
 
-#define ANX7688_REG_STATUS      0x82
+#define ANX7688_REG_STATUS 0x82
 #define ANX7688_REG_STATUS_LINK BIT(0)
 
-#define ANX7688_REG_HPD         0x83
-#define ANX7688_REG_HPD_HIGH    BIT(0)
-#define ANX7688_REG_HPD_IRQ     BIT(1)
-#define ANX7688_REG_HPD_ENABLE  BIT(2)
+#define ANX7688_REG_HPD 0x83
+#define ANX7688_REG_HPD_HIGH BIT(0)
+#define ANX7688_REG_HPD_IRQ BIT(1)
+#define ANX7688_REG_HPD_ENABLE BIT(2)
 
-#define ANX7688_USBC_ADDR_FLAGS		0x28
-#define ANX7688_REG_RAMCTRL		0xe7
-#define ANX7688_REG_RAMCTRL_BOOT_DONE	BIT(6)
+#define ANX7688_USBC_ADDR_FLAGS 0x28
+#define ANX7688_REG_RAMCTRL 0xe7
+#define ANX7688_REG_RAMCTRL_BOOT_DONE BIT(6)
 
 static int anx7688_init(int port)
 {
@@ -85,9 +85,9 @@ static void anx7688_update_hpd_enable(int port)
 	    !(status & ANX7688_REG_STATUS_LINK)) {
 		reg &= ~ANX7688_REG_HPD_IRQ;
 		tcpc_write(port, ANX7688_REG_HPD,
-			   (status & ANX7688_REG_STATUS_LINK)
-			   ? reg | ANX7688_REG_HPD_ENABLE
-			   : reg & ~ANX7688_REG_HPD_ENABLE);
+			   (status & ANX7688_REG_STATUS_LINK) ?
+				   reg | ANX7688_REG_HPD_ENABLE :
+				   reg & ~ANX7688_REG_HPD_ENABLE);
 	}
 }
 
@@ -144,11 +144,19 @@ static void anx7688_tcpc_alert(int port)
 		anx7688_update_hpd_enable(port);
 }
 
-static int anx7688_mux_set(const struct usb_mux *me, mux_state_t mux_state)
+static int anx7688_mux_set(const struct usb_mux *me, mux_state_t mux_state,
+			   bool *ack_required)
 {
 	int reg = 0;
 	int rv, polarity;
 
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
+	/* This driver treats safe mode as none */
+	if (mux_state & USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
+
 	rv = mux_read(me, TCPC_REG_CONFIG_STD_OUTPUT, &reg);
 	if (rv != EC_SUCCESS)
 		return rv;
@@ -191,24 +199,26 @@ static bool anx7688_tcpm_check_vbus_level(int port, enum vbus_level level)
 
 /* ANX7688 is a TCPCI compatible port controller */
 const struct tcpm_drv anx7688_tcpm_drv = {
-	.init			= &anx7688_init,
-	.release		= &anx7688_release,
-	.get_cc			= &tcpci_tcpm_get_cc,
+	.init = &anx7688_init,
+	.release = &anx7688_release,
+	.get_cc = &tcpci_tcpm_get_cc,
 #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	.check_vbus_level	= &anx7688_tcpm_check_vbus_level,
+	.check_vbus_level = &anx7688_tcpm_check_vbus_level,
 #endif
-	.select_rp_value	= &tcpci_tcpm_select_rp_value,
-	.set_cc			= &tcpci_tcpm_set_cc,
-	.set_polarity		= &tcpci_tcpm_set_polarity,
+	.select_rp_value = &tcpci_tcpm_select_rp_value,
+	.set_cc = &tcpci_tcpm_set_cc,
+	.set_polarity = &tcpci_tcpm_set_polarity,
 #ifdef CONFIG_USB_PD_DECODE_SOP
-	.sop_prime_disable	= &tcpci_tcpm_sop_prime_disable,
+	.sop_prime_enable = &tcpci_tcpm_sop_prime_enable,
 #endif
-	.set_vconn		= &tcpci_tcpm_set_vconn,
-	.set_msg_header		= &tcpci_tcpm_set_msg_header,
-	.set_rx_enable		= &tcpci_tcpm_set_rx_enable,
-	.get_message_raw	= &tcpci_tcpm_get_message_raw,
-	.transmit		= &tcpci_tcpm_transmit,
-	.tcpc_alert		= &anx7688_tcpc_alert,
+	.set_vconn = &tcpci_tcpm_set_vconn,
+	.set_msg_header = &tcpci_tcpm_set_msg_header,
+	.set_rx_enable = &tcpci_tcpm_set_rx_enable,
+	.get_message_raw = &tcpci_tcpm_get_message_raw,
+	.transmit = &tcpci_tcpm_transmit,
+	.tcpc_alert = &anx7688_tcpc_alert,
+	.set_bist_test_mode = &tcpci_set_bist_test_mode,
+	.get_bist_test_mode = &tcpci_get_bist_test_mode,
 };
 
 #ifdef CONFIG_USB_PD_TCPM_MUX
diff --git a/driver/tcpm/anx7688.h b/driver/tcpm/anx7688.h
index 534e4155b1..8a7d2e1d03 100644
--- a/driver/tcpm/anx7688.h
+++ b/driver/tcpm/anx7688.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/driver/tcpm/ccgxxf.c b/driver/tcpm/ccgxxf.c
new file mode 100644
index 0000000000..34670e12ef
--- /dev/null
+++ b/driver/tcpm/ccgxxf.c
@@ -0,0 +1,129 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Cypress CCGXXF PD chip driver source
+ */
+
+#include "ccgxxf.h"
+#include "console.h"
+#include "tcpm/tcpci.h"
+
+/*
+ * TODO (b/236994474): Once the PD negotiation completes, CCGXXF chip stops
+ * responding over I2C for about 10 seconds. As DRP is enabled, TCPM algorithm
+ * constantly looks for any CC status changes even after negotiation completes.
+ * Hence, cache the CC state and return the cached values in case of I2C
+ * failures. This workaround will be removed once the fix is added in the
+ * physical layer firmware of CCGXXF.
+ */
+
+struct ccgxxf_cc {
+	bool good_cc;
+	enum tcpc_cc_voltage_status cc1;
+	enum tcpc_cc_voltage_status cc2;
+};
+
+static struct ccgxxf_cc ccgxxf_cc_cache[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+static int ccgxxf_tcpci_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
+				    enum tcpc_cc_voltage_status *cc2)
+{
+	int rv = tcpci_tcpm_get_cc(port, cc1, cc2);
+
+	if (rv) {
+		if (!ccgxxf_cc_cache[port].good_cc)
+			return rv;
+
+		*cc1 = ccgxxf_cc_cache[port].cc1;
+		*cc2 = ccgxxf_cc_cache[port].cc2;
+	} else {
+		ccgxxf_cc_cache[port].good_cc = true;
+		ccgxxf_cc_cache[port].cc1 = *cc1;
+		ccgxxf_cc_cache[port].cc2 = *cc2;
+	}
+
+	return EC_SUCCESS;
+}
+
+static int ccgxxf_tcpci_tcpm_init(int port)
+{
+	ccgxxf_cc_cache[port].good_cc = false;
+
+	return tcpci_tcpm_init(port);
+}
+
+#ifdef CONFIG_USB_PD_TCPM_SBU
+static int ccgxxf_tcpc_set_sbu(int port, bool enable)
+{
+	return tcpc_write(port, CCGXXF_REG_SBU_MUX_CTL, enable);
+}
+#endif
+
+#ifdef CONFIG_CMD_TCPC_DUMP
+static void ccgxxf_dump_registers(int port)
+{
+	int fw_ver, fw_build;
+
+	tcpc_dump_std_registers(port);
+
+	/* Get the F/W version and build ID */
+	if (!tcpc_read16(port, CCGXXF_REG_FW_VERSION, &fw_ver) &&
+	    !tcpc_read16(port, CCGXXF_REG_FW_VERSION_BUILD, &fw_build)) {
+		ccprintf("  FW_VERSION(build.major.minor)        = %d.%d.%d\n",
+			 fw_build & 0xFF, (fw_ver >> 8) & 0xFF, fw_ver & 0xFF);
+	}
+}
+#endif
+
+int ccgxxf_reset(int port)
+{
+	return tcpc_write16(port, CCGXXF_REG_FWU_COMMAND, CCGXXF_FWU_CMD_RESET);
+}
+
+const struct tcpm_drv ccgxxf_tcpm_drv = {
+	.init = &ccgxxf_tcpci_tcpm_init,
+	.release = &tcpci_tcpm_release,
+	.get_cc = &ccgxxf_tcpci_tcpm_get_cc,
+#ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
+	.check_vbus_level = &tcpci_tcpm_check_vbus_level,
+#endif
+	.select_rp_value = &tcpci_tcpm_select_rp_value,
+	.set_cc = &tcpci_tcpm_set_cc,
+	.set_polarity = &tcpci_tcpm_set_polarity,
+#ifdef CONFIG_USB_PD_DECODE_SOP
+	.sop_prime_enable = &tcpci_tcpm_sop_prime_enable,
+#endif
+	.set_vconn = &tcpci_tcpm_set_vconn,
+	.set_msg_header = &tcpci_tcpm_set_msg_header,
+	.set_rx_enable = &tcpci_tcpm_set_rx_enable,
+	.get_message_raw = &tcpci_tcpm_get_message_raw,
+	.transmit = &tcpci_tcpm_transmit,
+	.tcpc_alert = &tcpci_tcpc_alert,
+#ifdef CONFIG_USB_PD_DISCHARGE_TCPC
+	.tcpc_discharge_vbus = &tcpci_tcpc_discharge_vbus,
+#endif
+	.tcpc_enable_auto_discharge_disconnect =
+		&tcpci_tcpc_enable_auto_discharge_disconnect,
+#ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+	.drp_toggle = &tcpci_tcpc_drp_toggle,
+#endif
+	.get_chip_info = &tcpci_get_chip_info,
+#ifdef CONFIG_USB_PD_PPC
+	.get_snk_ctrl = &tcpci_tcpm_get_snk_ctrl,
+	.set_snk_ctrl = &tcpci_tcpm_set_snk_ctrl,
+	.get_src_ctrl = &tcpci_tcpm_get_src_ctrl,
+	.set_src_ctrl = &tcpci_tcpm_set_src_ctrl,
+#endif
+#ifdef CONFIG_USB_PD_TCPM_SBU
+	.set_sbu = &ccgxxf_tcpc_set_sbu,
+#endif
+#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
+	.enter_low_power_mode = &tcpci_enter_low_power_mode,
+#endif
+	.set_bist_test_mode = &tcpci_set_bist_test_mode,
+	.get_bist_test_mode = &tcpci_get_bist_test_mode,
+#ifdef CONFIG_CMD_TCPC_DUMP
+	.dump_registers = &ccgxxf_dump_registers,
+#endif
+};
diff --git a/driver/tcpm/ccgxxf.h b/driver/tcpm/ccgxxf.h
new file mode 100644
index 0000000000..9342dc9a98
--- /dev/null
+++ b/driver/tcpm/ccgxxf.h
@@ -0,0 +1,93 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * USB Power delivery port management For Cypress EZ-PD CCG6DF, CCG6SF
+ * CCGXXF FW is designed to adapt standard TCPM driver procedures.
+ */
+#ifndef __CROS_EC_DRIVER_TCPM_CCGXXF_H
+#define __CROS_EC_DRIVER_TCPM_CCGXXF_H
+
+#define CCGXXF_I2C_ADDR1_FLAGS 0x0B
+#define CCGXXF_I2C_ADDR2_FLAGS 0x1B
+
+/* SBU FET control register */
+#define CCGXXF_REG_SBU_MUX_CTL 0xBB
+
+/* F/W info register */
+#define CCGXXF_REG_FW_VERSION 0x94
+#define CCGXXF_REG_FW_VERSION_BUILD 0x96
+
+/* Firmware update / reset control register */
+#define CCGXXF_REG_FWU_COMMAND 0x92
+#define CCGXXF_FWU_CMD_RESET 0x0077
+
+/**
+ * Reset CCGXXF chip
+ *
+ * CCGXXF's reset line is connected to an internal LDO hence external GPIOs
+ * should not control the reset line as it can prevent it booting from dead
+ * battery, instead a software mechanism can be used to reset the chip.
+ * Care must be taken by board level function in below scenarios;
+ * 1. During dead battery boot from CCGXXF ports, do not reset the chip as
+ *    it will lose the dead battery boot scenario content.
+ * 2. If dual port solution chip is used, resetting one port resets other port
+ *    as well.
+ * 3. Built-in I/O expander also gets reset.
+ *
+ * @param port Type-C port number
+ * @return EC_SUCCESS or error
+ */
+int ccgxxf_reset(int port);
+
+extern const struct tcpm_drv ccgxxf_tcpm_drv;
+
+/* CCGXXF built in I/O expander definitions */
+#ifdef CONFIG_IO_EXPANDER_CCGXXF
+
+/* CCGXXF I/O ports that can be referenced in gpio.inc */
+enum ccgxxf_io_ports {
+	CCGXXF_PORT_0,
+	CCGXXF_PORT_1,
+	CCGXXF_PORT_2,
+	CCGXXF_PORT_3
+};
+
+/* CCGXXF I/O pins that can be referenced in gpio.inc */
+enum ccgxxf_io_pins {
+	CCGXXF_IO_0,
+	CCGXXF_IO_1,
+	CCGXXF_IO_2,
+	CCGXXF_IO_3,
+	CCGXXF_IO_4,
+	CCGXXF_IO_5,
+	CCGXXF_IO_6,
+	CCGXXF_IO_7
+};
+
+#define CCGXXF_REG_GPIO_CONTROL(port) ((port) + 0x80)
+#define CCGXXF_REG_GPIO_STATUS(port) ((port) + 0x84)
+
+#define CCGXXF_REG_GPIO_MODE 0x88
+#define CCGXXF_GPIO_PIN_MASK_SHIFT 8
+#define CCGXXF_GPIO_PIN_MODE_SHIFT 2
+#define CCGXXF_GPIO_1P8V_SEL BIT(7)
+
+enum ccgxxf_gpio_mode {
+	CCGXXF_GPIO_MODE_HIZ_ANALOG,
+	CCGXXF_GPIO_MODE_HIZ_DIGITAL,
+	CCGXXF_GPIO_MODE_RES_UP,
+	CCGXXF_GPIO_MODE_RES_DWN,
+	CCGXXF_GPIO_MODE_OD_LOW,
+	CCGXXF_GPIO_MODE_OD_HIGH,
+	CCGXXF_GPIO_MODE_STRONG,
+	CCGXXF_GPIO_MODE_RES_UPDOWN
+};
+
+extern const struct ioexpander_drv ccgxxf_ioexpander_drv;
+
+#endif /* CONFIG_IO_EXPANDER_CCGXXF */
+
+#endif /* __CROS_EC_DRIVER_TCPM_CCGXXF_H */
diff --git a/driver/tcpm/fusb302.c b/driver/tcpm/fusb302.c
index 5ec8c284c2..3f11e568d0 100644
--- a/driver/tcpm/fusb302.c
+++ b/driver/tcpm/fusb302.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -9,14 +9,15 @@
 
 #include "console.h"
 #include "fusb302.h"
-#include "task.h"
 #include "hooks.h"
-#include "tcpci.h"
-#include "tcpm.h"
+#include "task.h"
+#include "tcpm/tcpci.h"
+#include "tcpm/tcpm.h"
 #include "timer.h"
 #include "usb_charge.h"
 #include "usb_pd.h"
 #include "usb_pd_tcpc.h"
+#include "usb_pd_tcpm.h"
 #include "util.h"
 
 #if defined(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE) || \
@@ -24,8 +25,8 @@
 #error "Unsupported config options of fusb302 PD driver"
 #endif
 
-#define PACKET_IS_GOOD_CRC(head) (PD_HEADER_TYPE(head) == PD_CTRL_GOOD_CRC && \
-				 PD_HEADER_CNT(head) == 0)
+#define PACKET_IS_GOOD_CRC(head) \
+	(PD_HEADER_TYPE(head) == PD_CTRL_GOOD_CRC && PD_HEADER_CNT(head) == 0)
 
 static struct fusb302_chip_state {
 	int cc_polarity;
@@ -37,7 +38,7 @@ static struct fusb302_chip_state {
 	uint8_t mdac_rd;
 } state[CONFIG_USB_PD_PORT_MAX_COUNT];
 
-static struct mutex measure_lock;
+K_MUTEX_DEFINE(measure_lock);
 
 /*
  * Bring the FUSB302 out of reset after Hard Reset signaling. This will
@@ -76,7 +77,7 @@ static void fusb302_auto_goodcrc_enable(int port, int enable)
 {
 	int reg;
 
-	tcpc_read(port,	TCPC_REG_SWITCHES1, &reg);
+	tcpc_read(port, TCPC_REG_SWITCHES1, &reg);
 
 	if (enable)
 		reg |= TCPC_REG_SWITCHES1_AUTO_GCRC;
@@ -157,8 +158,8 @@ static int measure_cc_pin_source(int port, int cc_measure)
 		/* Read status register */
 		tcpc_read(port, TCPC_REG_STATUS0, &reg);
 
-		cc_lvl = (reg & TCPC_REG_STATUS0_COMP) ? TYPEC_CC_VOLT_RD
-						       : TYPEC_CC_VOLT_RA;
+		cc_lvl = (reg & TCPC_REG_STATUS0_COMP) ? TYPEC_CC_VOLT_RD :
+							 TYPEC_CC_VOLT_RA;
 	}
 
 	/* Restore SWITCHES0 register to its value prior */
@@ -171,8 +172,8 @@ static int measure_cc_pin_source(int port, int cc_measure)
 
 /* Determine cc pin state for source when in manual detect mode */
 static void detect_cc_pin_source_manual(int port,
-	enum tcpc_cc_voltage_status *cc1_lvl,
-	enum tcpc_cc_voltage_status *cc2_lvl)
+					enum tcpc_cc_voltage_status *cc1_lvl,
+					enum tcpc_cc_voltage_status *cc2_lvl)
 {
 	int cc1_measure = TCPC_REG_SWITCHES0_MEAS_CC1;
 	int cc2_measure = TCPC_REG_SWITCHES0_MEAS_CC2;
@@ -188,12 +189,11 @@ static void detect_cc_pin_source_manual(int port,
 		*cc1_lvl = measure_cc_pin_source(port, cc1_measure);
 		*cc2_lvl = measure_cc_pin_source(port, cc2_measure);
 	}
-
 }
 
 /* Determine cc pin state for sink */
 static void detect_cc_pin_sink(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2)
+			       enum tcpc_cc_voltage_status *cc2)
 {
 	int reg;
 	int orig_meas_cc1;
@@ -219,7 +219,6 @@ static void detect_cc_pin_sink(int port, enum tcpc_cc_voltage_status *cc1,
 	else
 		orig_meas_cc2 = 0;
 
-
 	/* Disable CC2 measurement switch, enable CC1 measurement switch */
 	reg &= ~TCPC_REG_SWITCHES0_MEAS_CC2;
 	reg |= TCPC_REG_SWITCHES0_MEAS_CC1;
@@ -295,7 +294,7 @@ static int get_num_bytes(uint16_t header)
 }
 
 static int fusb302_send_message(int port, uint16_t header, const uint32_t *data,
-				 uint8_t *buf, int buf_pos)
+				uint8_t *buf, int buf_pos)
 {
 	int rv;
 	int reg;
@@ -471,7 +470,7 @@ static int fusb302_tcpm_release(int port)
 }
 
 static int fusb302_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2)
+			       enum tcpc_cc_voltage_status *cc2)
 {
 	if (state[port].pulling_up) {
 		/* Source mode? */
@@ -503,12 +502,12 @@ static int fusb302_tcpm_set_cc(int port, int pull)
 			 TCPC_REG_SWITCHES0_VCONN_CC2);
 
 		reg |= TCPC_REG_SWITCHES0_CC1_PU_EN |
-			TCPC_REG_SWITCHES0_CC2_PU_EN;
+		       TCPC_REG_SWITCHES0_CC2_PU_EN;
 
 		if (state[port].vconn_enabled)
 			reg |= state[port].cc_polarity ?
-			       TCPC_REG_SWITCHES0_VCONN_CC1 :
-			       TCPC_REG_SWITCHES0_VCONN_CC2;
+				       TCPC_REG_SWITCHES0_VCONN_CC1 :
+				       TCPC_REG_SWITCHES0_VCONN_CC2;
 
 		tcpc_write(port, TCPC_REG_SWITCHES0, reg);
 
@@ -607,6 +606,22 @@ static int fusb302_tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity)
 	return 0;
 }
 
+__maybe_unused static int fusb302_tcpm_decode_sop_prime_enable(int port,
+							       bool enable)
+{
+	int reg;
+
+	if (tcpc_read(port, TCPC_REG_CONTROL1, &reg))
+		return EC_ERROR_UNKNOWN;
+
+	if (enable)
+		reg |= (TCPC_REG_CONTROL1_ENSOP1 | TCPC_REG_CONTROL1_ENSOP2);
+	else
+		reg &= ~(TCPC_REG_CONTROL1_ENSOP1 | TCPC_REG_CONTROL1_ENSOP2);
+
+	return tcpc_write(port, TCPC_REG_CONTROL1, reg);
+}
+
 static int fusb302_tcpm_set_vconn(int port, int enable)
 {
 	/*
@@ -626,18 +641,14 @@ static int fusb302_tcpm_set_vconn(int port, int enable)
 		/* set to saved polarity */
 		tcpm_set_polarity(port, state[port].cc_polarity);
 
-#ifdef CONFIG_USB_PD_DECODE_SOP
-		if (state[port].rx_enable) {
-			if (tcpc_read(port, TCPC_REG_CONTROL1, &reg))
-				return EC_ERROR_UNKNOWN;
-
-			reg |= (TCPC_REG_CONTROL1_ENSOP1 |
-				TCPC_REG_CONTROL1_ENSOP2);
-			tcpc_write(port, TCPC_REG_CONTROL1, reg);
+		if (IS_ENABLED(CONFIG_USB_PD_DECODE_SOP)) {
+			if (state[port].rx_enable) {
+				if (fusb302_tcpm_decode_sop_prime_enable(port,
+									 true))
+					return EC_ERROR_UNKNOWN;
+			}
 		}
-#endif
 	} else {
-
 		tcpc_read(port, TCPC_REG_SWITCHES0, &reg);
 
 		/* clear VCONN switch bits */
@@ -646,16 +657,13 @@ static int fusb302_tcpm_set_vconn(int port, int enable)
 
 		tcpc_write(port, TCPC_REG_SWITCHES0, reg);
 
-#ifdef CONFIG_USB_PD_DECODE_SOP
-		if (state[port].rx_enable) {
-			if (tcpc_read(port, TCPC_REG_CONTROL1, &reg))
-				return EC_ERROR_UNKNOWN;
-
-			reg &= ~(TCPC_REG_CONTROL1_ENSOP1 |
-				TCPC_REG_CONTROL1_ENSOP2);
-			tcpc_write(port, TCPC_REG_CONTROL1, reg);
+		if (IS_ENABLED(CONFIG_USB_PD_DECODE_SOP)) {
+			if (state[port].rx_enable) {
+				if (fusb302_tcpm_decode_sop_prime_enable(port,
+									 false))
+					return EC_ERROR_UNKNOWN;
+			}
 		}
-#endif
 	}
 
 	return 0;
@@ -718,7 +726,6 @@ static int fusb302_tcpm_set_rx_enable(int port, int enable)
 		/* flush rx fifo in case messages have been coming our way */
 		fusb302_flush_rx_fifo(port);
 
-
 	} else {
 		tcpc_write(port, TCPC_REG_SWITCHES0, reg);
 
@@ -801,7 +808,8 @@ static int fusb302_tcpm_get_message_raw(int port, uint32_t *payload, int *head)
 		 * No START, but do issue a STOP at the end.
 		 * add 4 to len to read CRC out
 		 */
-		rv |= tcpc_xfer_unlocked(port, 0, 0, buf, len+4, I2C_XFER_STOP);
+		rv |= tcpc_xfer_unlocked(port, 0, 0, buf, len + 4,
+					 I2C_XFER_STOP);
 
 		tcpc_lock(port, 0);
 	} while (!rv && PACKET_IS_GOOD_CRC(*head) &&
@@ -823,16 +831,16 @@ static int fusb302_tcpm_get_message_raw(int port, uint32_t *payload, int *head)
 			return EC_ERROR_UNKNOWN;
 
 		if (reg & TCPC_REG_STATUS1_RXSOP1)
-			*head |= PD_HEADER_SOP(PD_MSG_SOP_PRIME);
+			*head |= PD_HEADER_SOP(TCPCI_MSG_SOP_PRIME);
 		else if (reg & TCPC_REG_STATUS1_RXSOP2)
-			*head |= PD_HEADER_SOP(PD_MSG_SOP_PRIME_PRIME);
+			*head |= PD_HEADER_SOP(TCPCI_MSG_SOP_PRIME_PRIME);
 	}
 #endif
 
 	return rv;
 }
 
-static int fusb302_tcpm_transmit(int port, enum tcpm_transmit_type type,
+static int fusb302_tcpm_transmit(int port, enum tcpci_msg_type type,
 				 uint16_t header, const uint32_t *data)
 {
 	/*
@@ -858,7 +866,7 @@ static int fusb302_tcpm_transmit(int port, enum tcpm_transmit_type type,
 	fusb302_flush_tx_fifo(port);
 
 	switch (type) {
-	case TCPC_TX_SOP:
+	case TCPCI_MSG_SOP:
 
 		/* put register address first for of burst tcpc write */
 		buf[buf_pos++] = TCPC_REG_FIFOS;
@@ -870,14 +878,38 @@ static int fusb302_tcpm_transmit(int port, enum tcpm_transmit_type type,
 		buf[buf_pos++] = FUSB302_TKN_SYNC2;
 
 		return fusb302_send_message(port, header, data, buf, buf_pos);
-	case TCPC_TX_HARD_RESET:
+	case TCPCI_MSG_SOP_PRIME:
+
+		/* put register address first for of burst tcpc write */
+		buf[buf_pos++] = TCPC_REG_FIFOS;
+
+		/* Write the SOP' Ordered Set into TX FIFO */
+		buf[buf_pos++] = FUSB302_TKN_SYNC1;
+		buf[buf_pos++] = FUSB302_TKN_SYNC1;
+		buf[buf_pos++] = FUSB302_TKN_SYNC3;
+		buf[buf_pos++] = FUSB302_TKN_SYNC3;
+
+		return fusb302_send_message(port, header, data, buf, buf_pos);
+	case TCPCI_MSG_SOP_PRIME_PRIME:
+
+		/* put register address first for of burst tcpc write */
+		buf[buf_pos++] = TCPC_REG_FIFOS;
+
+		/* Write the SOP'' Ordered Set into TX FIFO */
+		buf[buf_pos++] = FUSB302_TKN_SYNC1;
+		buf[buf_pos++] = FUSB302_TKN_SYNC3;
+		buf[buf_pos++] = FUSB302_TKN_SYNC1;
+		buf[buf_pos++] = FUSB302_TKN_SYNC3;
+
+		return fusb302_send_message(port, header, data, buf, buf_pos);
+	case TCPCI_MSG_TX_HARD_RESET:
 		/* Simply hit the SEND_HARD_RESET bit */
 		tcpc_read(port, TCPC_REG_CONTROL3, &reg);
 		reg |= TCPC_REG_CONTROL3_SEND_HARDRESET;
 		tcpc_write(port, TCPC_REG_CONTROL3, reg);
 
 		break;
-	case TCPC_TX_BIST_MODE_2:
+	case TCPCI_MSG_TX_BIST_MODE_2:
 		/* Hit the BIST_MODE2 bit and start TX */
 		tcpc_read(port, TCPC_REG_CONTROL1, &reg);
 		reg |= TCPC_REG_CONTROL1_BIST_MODE2;
@@ -939,7 +971,7 @@ void fusb302_tcpc_alert(int port)
 
 	if (interrupt & TCPC_REG_INTERRUPT_BC_LVL) {
 		/* CC Status change */
-		task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_CC, 0);
+		task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_CC);
 	}
 
 	if (interrupt & TCPC_REG_INTERRUPT_COLLISION) {
@@ -951,9 +983,8 @@ void fusb302_tcpc_alert(int port)
 	if (interrupt & TCPC_REG_INTERRUPT_VBUSOK) {
 		/* VBUS crossed threshold */
 #ifdef CONFIG_USB_CHARGER
-		usb_charger_vbus_change(port,
-					fusb302_tcpm_check_vbus_level(port,
-							VBUS_PRESENT));
+		usb_charger_vbus_change(port, fusb302_tcpm_check_vbus_level(
+						      port, VBUS_PRESENT));
 #else
 		if (!fusb302_tcpm_check_vbus_level(port, VBUS_PRESENT))
 			pd_vbus_low(port);
@@ -988,7 +1019,7 @@ void fusb302_tcpc_alert(int port)
 		/* bring FUSB302 out of reset */
 		fusb302_pd_reset(port);
 		task_set_event(PD_PORT_TO_TASK_ID(port),
-			PD_EVENT_RX_HARD_RESET, 0);
+			       PD_EVENT_RX_HARD_RESET);
 	}
 
 	if (interruptb & TCPC_REG_INTERRUPTB_GCRCSENT) {
@@ -1003,7 +1034,6 @@ void fusb302_tcpc_alert(int port)
 			fusb302_flush_rx_fifo(port);
 		}
 	}
-
 }
 
 /* For BIST receiving */
@@ -1027,16 +1057,16 @@ static int fusb302_set_toggle_mode(int port, int mode)
 	int reg, rv;
 
 	rv = i2c_read8(tcpc_config[port].i2c_info.port,
-		tcpc_config[port].i2c_info.addr_flags,
-		TCPC_REG_CONTROL2, &reg);
+		       tcpc_config[port].i2c_info.addr_flags, TCPC_REG_CONTROL2,
+		       &reg);
 	if (rv)
 		return rv;
 
 	reg &= ~TCPC_REG_CONTROL2_MODE_MASK;
 	reg |= mode << TCPC_REG_CONTROL2_MODE_POS;
 	return i2c_write8(tcpc_config[port].i2c_info.port,
-		tcpc_config[port].i2c_info.addr_flags,
-		TCPC_REG_CONTROL2, reg);
+			  tcpc_config[port].i2c_info.addr_flags,
+			  TCPC_REG_CONTROL2, reg);
 }
 
 static int fusb302_tcpm_enter_low_power_mode(int port)
@@ -1050,8 +1080,8 @@ static int fusb302_tcpm_enter_low_power_mode(int port)
 	 * - start toggling
 	 */
 	rv = i2c_write8(tcpc_config[port].i2c_info.port,
-			  tcpc_config[port].i2c_info.addr_flags,
-			  TCPC_REG_POWER, TCPC_REG_POWER_PWR_LOW);
+			tcpc_config[port].i2c_info.addr_flags, TCPC_REG_POWER,
+			TCPC_REG_POWER_PWR_LOW);
 	if (rv)
 		return rv;
 
@@ -1064,8 +1094,8 @@ static int fusb302_tcpm_enter_low_power_mode(int port)
 		break;
 	case PD_DRP_FREEZE:
 		mode = pd_get_power_role(port) == PD_ROLE_SINK ?
-			TCPC_REG_CONTROL2_MODE_UFP :
-			TCPC_REG_CONTROL2_MODE_DFP;
+			       TCPC_REG_CONTROL2_MODE_UFP :
+			       TCPC_REG_CONTROL2_MODE_DFP;
 		break;
 	case PD_DRP_FORCE_SINK:
 		mode = TCPC_REG_CONTROL2_MODE_UFP;
@@ -1081,14 +1111,14 @@ static int fusb302_tcpm_enter_low_power_mode(int port)
 	usleep(250);
 
 	rv = i2c_read8(tcpc_config[port].i2c_info.port,
-		tcpc_config[port].i2c_info.addr_flags,
-		TCPC_REG_CONTROL2, &reg);
+		       tcpc_config[port].i2c_info.addr_flags, TCPC_REG_CONTROL2,
+		       &reg);
 	if (rv)
 		return rv;
 	reg |= TCPC_REG_CONTROL2_TOGGLE;
 	return i2c_write8(tcpc_config[port].i2c_info.port,
-		tcpc_config[port].i2c_info.addr_flags,
-		TCPC_REG_CONTROL2, reg);
+			  tcpc_config[port].i2c_info.addr_flags,
+			  TCPC_REG_CONTROL2, reg);
 }
 #endif
 
@@ -1106,7 +1136,7 @@ static int fusb302_compare_mdac(int port, int mdac)
 	tcpc_read(port, TCPC_REG_MEASURE, &orig_reg);
 	/* set reg_measure bit 0~5 to mdac, and bit6 to 1(measure vbus) */
 	tcpc_write(port, TCPC_REG_MEASURE,
-		(mdac & TCPC_REG_MEASURE_MDAC_MASK) | TCPC_REG_MEASURE_VBUS);
+		   (mdac & TCPC_REG_MEASURE_MDAC_MASK) | TCPC_REG_MEASURE_VBUS);
 
 	/* Wait on measurement */
 	usleep(350);
@@ -1124,7 +1154,7 @@ static int fusb302_compare_mdac(int port, int mdac)
 	return status0 & TCPC_REG_STATUS0_COMP;
 }
 
-int tcpc_get_vbus_voltage(int port)
+int fusb302_get_vbus_voltage(int port, int *vbus)
 {
 	int mdac = 0, i;
 
@@ -1140,26 +1170,32 @@ int tcpc_get_vbus_voltage(int port)
 			mdac |= BIT(i);
 	}
 
-	return (mdac + 1) * 420;
+	*vbus = (mdac + 1) * 420;
+
+	return EC_SUCCESS;
 }
 
 const struct tcpm_drv fusb302_tcpm_drv = {
-	.init			= &fusb302_tcpm_init,
-	.release		= &fusb302_tcpm_release,
-	.get_cc			= &fusb302_tcpm_get_cc,
+	.init = &fusb302_tcpm_init,
+	.release = &fusb302_tcpm_release,
+	.get_cc = &fusb302_tcpm_get_cc,
 #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	.check_vbus_level	= &fusb302_tcpm_check_vbus_level,
+	.check_vbus_level = &fusb302_tcpm_check_vbus_level,
+#endif
+	.get_vbus_voltage = &fusb302_get_vbus_voltage,
+	.select_rp_value = &fusb302_tcpm_select_rp_value,
+	.set_cc = &fusb302_tcpm_set_cc,
+	.set_polarity = &fusb302_tcpm_set_polarity,
+#ifdef CONFIG_USB_PD_DECODE_SOP
+	.sop_prime_enable = &fusb302_tcpm_decode_sop_prime_enable,
 #endif
-	.select_rp_value	= &fusb302_tcpm_select_rp_value,
-	.set_cc			= &fusb302_tcpm_set_cc,
-	.set_polarity		= &fusb302_tcpm_set_polarity,
-	.set_vconn		= &fusb302_tcpm_set_vconn,
-	.set_msg_header		= &fusb302_tcpm_set_msg_header,
-	.set_rx_enable		= &fusb302_tcpm_set_rx_enable,
-	.get_message_raw	= &fusb302_tcpm_get_message_raw,
-	.transmit		= &fusb302_tcpm_transmit,
-	.tcpc_alert		= &fusb302_tcpc_alert,
+	.set_vconn = &fusb302_tcpm_set_vconn,
+	.set_msg_header = &fusb302_tcpm_set_msg_header,
+	.set_rx_enable = &fusb302_tcpm_set_rx_enable,
+	.get_message_raw = &fusb302_tcpm_get_message_raw,
+	.transmit = &fusb302_tcpm_transmit,
+	.tcpc_alert = &fusb302_tcpc_alert,
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	.enter_low_power_mode	= &fusb302_tcpm_enter_low_power_mode,
+	.enter_low_power_mode = &fusb302_tcpm_enter_low_power_mode,
 #endif
 };
diff --git a/driver/tcpm/fusb302.h b/driver/tcpm/fusb302.h
index 8db9f86c20..ac4fb96e19 100644
--- a/driver/tcpm/fusb302.h
+++ b/driver/tcpm/fusb302.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -14,183 +14,183 @@
 #define FUSB302_DEVID_302A 0x08
 #define FUSB302_DEVID_302B 0x09
 
-/* I2C slave address varies by part number */
+/* I2C address varies by part number */
 /* FUSB302BUCX / FUSB302BMPX */
-#define FUSB302_I2C_SLAVE_ADDR_FLAGS 0x22
+#define FUSB302_I2C_ADDR_FLAGS 0x22
 /* FUSB302B01MPX */
-#define FUSB302_I2C_SLAVE_ADDR_B01_FLAGS 0x23
+#define FUSB302_I2C_ADDR_B01_FLAGS 0x23
 /* FUSB302B10MPX */
-#define FUSB302_I2C_SLAVE_ADDR_B10_FLAGS 0x24
+#define FUSB302_I2C_ADDR_B10_FLAGS 0x24
 /* FUSB302B11MPX */
-#define FUSB302_I2C_SLAVE_ADDR_B11_FLAGS 0x25
-
-#define TCPC_REG_DEVICE_ID	0x01
-
-#define TCPC_REG_SWITCHES0	0x02
-#define TCPC_REG_SWITCHES0_CC2_PU_EN	(1<<7)
-#define TCPC_REG_SWITCHES0_CC1_PU_EN	(1<<6)
-#define TCPC_REG_SWITCHES0_VCONN_CC2	(1<<5)
-#define TCPC_REG_SWITCHES0_VCONN_CC1	(1<<4)
-#define TCPC_REG_SWITCHES0_MEAS_CC2	(1<<3)
-#define TCPC_REG_SWITCHES0_MEAS_CC1	(1<<2)
-#define TCPC_REG_SWITCHES0_CC2_PD_EN	(1<<1)
-#define TCPC_REG_SWITCHES0_CC1_PD_EN	(1<<0)
-
-#define TCPC_REG_SWITCHES1	0x03
-#define TCPC_REG_SWITCHES1_POWERROLE	(1<<7)
-#define TCPC_REG_SWITCHES1_SPECREV1	(1<<6)
-#define TCPC_REG_SWITCHES1_SPECREV0	(1<<5)
-#define TCPC_REG_SWITCHES1_DATAROLE	(1<<4)
-#define TCPC_REG_SWITCHES1_AUTO_GCRC	(1<<2)
-#define TCPC_REG_SWITCHES1_TXCC2_EN	(1<<1)
-#define TCPC_REG_SWITCHES1_TXCC1_EN	(1<<0)
-
-#define TCPC_REG_MEASURE	0x04
-#define TCPC_REG_MEASURE_MDAC_MASK	0x3F
-#define TCPC_REG_MEASURE_VBUS		(1<<6)
+#define FUSB302_I2C_ADDR_B11_FLAGS 0x25
+
+#define TCPC_REG_DEVICE_ID 0x01
+
+#define TCPC_REG_SWITCHES0 0x02
+#define TCPC_REG_SWITCHES0_CC2_PU_EN (1 << 7)
+#define TCPC_REG_SWITCHES0_CC1_PU_EN (1 << 6)
+#define TCPC_REG_SWITCHES0_VCONN_CC2 (1 << 5)
+#define TCPC_REG_SWITCHES0_VCONN_CC1 (1 << 4)
+#define TCPC_REG_SWITCHES0_MEAS_CC2 (1 << 3)
+#define TCPC_REG_SWITCHES0_MEAS_CC1 (1 << 2)
+#define TCPC_REG_SWITCHES0_CC2_PD_EN (1 << 1)
+#define TCPC_REG_SWITCHES0_CC1_PD_EN (1 << 0)
+
+#define TCPC_REG_SWITCHES1 0x03
+#define TCPC_REG_SWITCHES1_POWERROLE (1 << 7)
+#define TCPC_REG_SWITCHES1_SPECREV1 (1 << 6)
+#define TCPC_REG_SWITCHES1_SPECREV0 (1 << 5)
+#define TCPC_REG_SWITCHES1_DATAROLE (1 << 4)
+#define TCPC_REG_SWITCHES1_AUTO_GCRC (1 << 2)
+#define TCPC_REG_SWITCHES1_TXCC2_EN (1 << 1)
+#define TCPC_REG_SWITCHES1_TXCC1_EN (1 << 0)
+
+#define TCPC_REG_MEASURE 0x04
+#define TCPC_REG_MEASURE_MDAC_MASK 0x3F
+#define TCPC_REG_MEASURE_VBUS (1 << 6)
 /*
  * MDAC reference voltage step size is 42 mV. Round our thresholds to reduce
  * maximum error, which also matches suggested thresholds in datasheet
  * (Table 3. Host Interrupt Summary).
  */
-#define TCPC_REG_MEASURE_MDAC_MV(mv)	(DIV_ROUND_NEAREST((mv), 42) & 0x3f)
-
-#define TCPC_REG_CONTROL0	0x06
-#define TCPC_REG_CONTROL0_TX_FLUSH	(1<<6)
-#define TCPC_REG_CONTROL0_INT_MASK	(1<<5)
-#define TCPC_REG_CONTROL0_HOST_CUR_MASK (3<<2)
-#define TCPC_REG_CONTROL0_HOST_CUR_3A0  (3<<2)
-#define TCPC_REG_CONTROL0_HOST_CUR_1A5  (2<<2)
-#define TCPC_REG_CONTROL0_HOST_CUR_USB  (1<<2)
-#define TCPC_REG_CONTROL0_TX_START	(1<<0)
-
-#define TCPC_REG_CONTROL1	0x07
-#define TCPC_REG_CONTROL1_ENSOP2DB	(1<<6)
-#define TCPC_REG_CONTROL1_ENSOP1DB	(1<<5)
-#define TCPC_REG_CONTROL1_BIST_MODE2	(1<<4)
-#define TCPC_REG_CONTROL1_RX_FLUSH	(1<<2)
-#define TCPC_REG_CONTROL1_ENSOP2	(1<<1)
-#define TCPC_REG_CONTROL1_ENSOP1	(1<<0)
-
-#define TCPC_REG_CONTROL2	0x08
+#define TCPC_REG_MEASURE_MDAC_MV(mv) (DIV_ROUND_NEAREST((mv), 42) & 0x3f)
+
+#define TCPC_REG_CONTROL0 0x06
+#define TCPC_REG_CONTROL0_TX_FLUSH (1 << 6)
+#define TCPC_REG_CONTROL0_INT_MASK (1 << 5)
+#define TCPC_REG_CONTROL0_HOST_CUR_MASK (3 << 2)
+#define TCPC_REG_CONTROL0_HOST_CUR_3A0 (3 << 2)
+#define TCPC_REG_CONTROL0_HOST_CUR_1A5 (2 << 2)
+#define TCPC_REG_CONTROL0_HOST_CUR_USB (1 << 2)
+#define TCPC_REG_CONTROL0_TX_START (1 << 0)
+
+#define TCPC_REG_CONTROL1 0x07
+#define TCPC_REG_CONTROL1_ENSOP2DB (1 << 6)
+#define TCPC_REG_CONTROL1_ENSOP1DB (1 << 5)
+#define TCPC_REG_CONTROL1_BIST_MODE2 (1 << 4)
+#define TCPC_REG_CONTROL1_RX_FLUSH (1 << 2)
+#define TCPC_REG_CONTROL1_ENSOP2 (1 << 1)
+#define TCPC_REG_CONTROL1_ENSOP1 (1 << 0)
+
+#define TCPC_REG_CONTROL2 0x08
 /* two-bit field, valid values below */
-#define TCPC_REG_CONTROL2_MODE_MASK	(0x3<<TCPC_REG_CONTROL2_MODE_POS)
-#define TCPC_REG_CONTROL2_MODE_DFP	(0x3)
-#define TCPC_REG_CONTROL2_MODE_UFP	(0x2)
-#define TCPC_REG_CONTROL2_MODE_DRP	(0x1)
-#define TCPC_REG_CONTROL2_MODE_POS	(1)
-#define TCPC_REG_CONTROL2_TOGGLE	(1<<0)
-
-#define TCPC_REG_CONTROL3	0x09
-#define TCPC_REG_CONTROL3_SEND_HARDRESET	(1<<6)
-#define TCPC_REG_CONTROL3_BIST_TMODE		(1<<5) /* 302B Only */
-#define TCPC_REG_CONTROL3_AUTO_HARDRESET	(1<<4)
-#define TCPC_REG_CONTROL3_AUTO_SOFTRESET	(1<<3)
+#define TCPC_REG_CONTROL2_MODE_MASK (0x3 << TCPC_REG_CONTROL2_MODE_POS)
+#define TCPC_REG_CONTROL2_MODE_DFP (0x3)
+#define TCPC_REG_CONTROL2_MODE_UFP (0x2)
+#define TCPC_REG_CONTROL2_MODE_DRP (0x1)
+#define TCPC_REG_CONTROL2_MODE_POS (1)
+#define TCPC_REG_CONTROL2_TOGGLE (1 << 0)
+
+#define TCPC_REG_CONTROL3 0x09
+#define TCPC_REG_CONTROL3_SEND_HARDRESET (1 << 6)
+#define TCPC_REG_CONTROL3_BIST_TMODE (1 << 5) /* 302B Only */
+#define TCPC_REG_CONTROL3_AUTO_HARDRESET (1 << 4)
+#define TCPC_REG_CONTROL3_AUTO_SOFTRESET (1 << 3)
 /* two-bit field */
-#define TCPC_REG_CONTROL3_N_RETRIES		(1<<1)
-#define TCPC_REG_CONTROL3_N_RETRIES_POS		(1)
-#define TCPC_REG_CONTROL3_N_RETRIES_SIZE	(2)
-#define TCPC_REG_CONTROL3_AUTO_RETRY		(1<<0)
-
-#define TCPC_REG_MASK		0x0A
-#define TCPC_REG_MASK_VBUSOK		(1<<7)
-#define TCPC_REG_MASK_ACTIVITY		(1<<6)
-#define TCPC_REG_MASK_COMP_CHNG		(1<<5)
-#define TCPC_REG_MASK_CRC_CHK		(1<<4)
-#define TCPC_REG_MASK_ALERT		(1<<3)
-#define TCPC_REG_MASK_WAKE		(1<<2)
-#define TCPC_REG_MASK_COLLISION		(1<<1)
-#define TCPC_REG_MASK_BC_LVL		(1<<0)
-
-#define TCPC_REG_POWER		0x0B
-#define TCPC_REG_POWER_PWR		(1<<0)	/* four-bit field */
-#define TCPC_REG_POWER_PWR_LOW		0x1 /* Bandgap + Wake circuitry */
-#define TCPC_REG_POWER_PWR_MEDIUM	0x3 /* LOW + Receiver + Current refs */
-#define TCPC_REG_POWER_PWR_HIGH		0x7 /* MEDIUM + Measure block */
-#define TCPC_REG_POWER_PWR_ALL		0xF /* HIGH + Internal Oscillator */
-
-#define TCPC_REG_RESET		0x0C
-#define TCPC_REG_RESET_PD_RESET		(1<<1)
-#define TCPC_REG_RESET_SW_RESET		(1<<0)
-
-#define TCPC_REG_MASKA		0x0E
-#define TCPC_REG_MASKA_OCP_TEMP		(1<<7)
-#define TCPC_REG_MASKA_TOGDONE		(1<<6)
-#define TCPC_REG_MASKA_SOFTFAIL		(1<<5)
-#define TCPC_REG_MASKA_RETRYFAIL	(1<<4)
-#define TCPC_REG_MASKA_HARDSENT		(1<<3)
-#define TCPC_REG_MASKA_TX_SUCCESS	(1<<2)
-#define TCPC_REG_MASKA_SOFTRESET	(1<<1)
-#define TCPC_REG_MASKA_HARDRESET	(1<<0)
-
-#define TCPC_REG_MASKB		0x0F
-#define TCPC_REG_MASKB_GCRCSENT		(1<<0)
-
-#define TCPC_REG_STATUS0A	0x3C
-#define TCPC_REG_STATUS0A_SOFTFAIL	(1<<5)
-#define TCPC_REG_STATUS0A_RETRYFAIL	(1<<4)
-#define TCPC_REG_STATUS0A_POWER		(1<<2) /* two-bit field */
-#define TCPC_REG_STATUS0A_RX_SOFT_RESET	(1<<1)
-#define TCPC_REG_STATUS0A_RX_HARD_RESEt	(1<<0)
-
-#define TCPC_REG_STATUS1A	0x3D
+#define TCPC_REG_CONTROL3_N_RETRIES (1 << 1)
+#define TCPC_REG_CONTROL3_N_RETRIES_POS (1)
+#define TCPC_REG_CONTROL3_N_RETRIES_SIZE (2)
+#define TCPC_REG_CONTROL3_AUTO_RETRY (1 << 0)
+
+#define TCPC_REG_MASK 0x0A
+#define TCPC_REG_MASK_VBUSOK (1 << 7)
+#define TCPC_REG_MASK_ACTIVITY (1 << 6)
+#define TCPC_REG_MASK_COMP_CHNG (1 << 5)
+#define TCPC_REG_MASK_CRC_CHK (1 << 4)
+#define TCPC_REG_MASK_ALERT (1 << 3)
+#define TCPC_REG_MASK_WAKE (1 << 2)
+#define TCPC_REG_MASK_COLLISION (1 << 1)
+#define TCPC_REG_MASK_BC_LVL (1 << 0)
+
+#define TCPC_REG_POWER 0x0B
+#define TCPC_REG_POWER_PWR (1 << 0) /* four-bit field */
+#define TCPC_REG_POWER_PWR_LOW 0x1 /* Bandgap + Wake circuitry */
+#define TCPC_REG_POWER_PWR_MEDIUM 0x3 /* LOW + Receiver + Current refs */
+#define TCPC_REG_POWER_PWR_HIGH 0x7 /* MEDIUM + Measure block */
+#define TCPC_REG_POWER_PWR_ALL 0xF /* HIGH + Internal Oscillator */
+
+#define TCPC_REG_RESET 0x0C
+#define TCPC_REG_RESET_PD_RESET (1 << 1)
+#define TCPC_REG_RESET_SW_RESET (1 << 0)
+
+#define TCPC_REG_MASKA 0x0E
+#define TCPC_REG_MASKA_OCP_TEMP (1 << 7)
+#define TCPC_REG_MASKA_TOGDONE (1 << 6)
+#define TCPC_REG_MASKA_SOFTFAIL (1 << 5)
+#define TCPC_REG_MASKA_RETRYFAIL (1 << 4)
+#define TCPC_REG_MASKA_HARDSENT (1 << 3)
+#define TCPC_REG_MASKA_TX_SUCCESS (1 << 2)
+#define TCPC_REG_MASKA_SOFTRESET (1 << 1)
+#define TCPC_REG_MASKA_HARDRESET (1 << 0)
+
+#define TCPC_REG_MASKB 0x0F
+#define TCPC_REG_MASKB_GCRCSENT (1 << 0)
+
+#define TCPC_REG_STATUS0A 0x3C
+#define TCPC_REG_STATUS0A_SOFTFAIL (1 << 5)
+#define TCPC_REG_STATUS0A_RETRYFAIL (1 << 4)
+#define TCPC_REG_STATUS0A_POWER (1 << 2) /* two-bit field */
+#define TCPC_REG_STATUS0A_RX_SOFT_RESET (1 << 1)
+#define TCPC_REG_STATUS0A_RX_HARD_RESEt (1 << 0)
+
+#define TCPC_REG_STATUS1A 0x3D
 /* three-bit field, valid values below */
-#define TCPC_REG_STATUS1A_TOGSS		(1<<3)
-#define TCPC_REG_STATUS1A_TOGSS_RUNNING		0x0
-#define TCPC_REG_STATUS1A_TOGSS_SRC1		0x1
-#define TCPC_REG_STATUS1A_TOGSS_SRC2		0x2
-#define TCPC_REG_STATUS1A_TOGSS_SNK1		0x5
-#define TCPC_REG_STATUS1A_TOGSS_SNK2		0x6
-#define TCPC_REG_STATUS1A_TOGSS_AA		0x7
-#define TCPC_REG_STATUS1A_TOGSS_POS		(3)
-#define TCPC_REG_STATUS1A_TOGSS_MASK		(0x7)
-
-#define TCPC_REG_STATUS1A_RXSOP2DB	(1<<2)
-#define TCPC_REG_STATUS1A_RXSOP1DB	(1<<1)
-#define TCPC_REG_STATUS1A_RXSOP		(1<<0)
-
-#define TCPC_REG_INTERRUPTA	0x3E
-#define TCPC_REG_INTERRUPTA_OCP_TEMP	(1<<7)
-#define TCPC_REG_INTERRUPTA_TOGDONE	(1<<6)
-#define TCPC_REG_INTERRUPTA_SOFTFAIL	(1<<5)
-#define TCPC_REG_INTERRUPTA_RETRYFAIL	(1<<4)
-#define TCPC_REG_INTERRUPTA_HARDSENT	(1<<3)
-#define TCPC_REG_INTERRUPTA_TX_SUCCESS	(1<<2)
-#define TCPC_REG_INTERRUPTA_SOFTRESET	(1<<1)
-#define TCPC_REG_INTERRUPTA_HARDRESET	(1<<0)
-
-#define TCPC_REG_INTERRUPTB	0x3F
-#define TCPC_REG_INTERRUPTB_GCRCSENT		(1<<0)
-
-#define TCPC_REG_STATUS0	0x40
-#define TCPC_REG_STATUS0_VBUSOK		(1<<7)
-#define TCPC_REG_STATUS0_ACTIVITY	(1<<6)
-#define TCPC_REG_STATUS0_COMP		(1<<5)
-#define TCPC_REG_STATUS0_CRC_CHK	(1<<4)
-#define TCPC_REG_STATUS0_ALERT		(1<<3)
-#define TCPC_REG_STATUS0_WAKE		(1<<2)
-#define TCPC_REG_STATUS0_BC_LVL1	(1<<1) /* two-bit field */
-#define TCPC_REG_STATUS0_BC_LVL0	(1<<0) /* two-bit field */
-
-#define TCPC_REG_STATUS1	0x41
-#define TCPC_REG_STATUS1_RXSOP2		(1<<7)
-#define TCPC_REG_STATUS1_RXSOP1		(1<<6)
-#define TCPC_REG_STATUS1_RX_EMPTY	(1<<5)
-#define TCPC_REG_STATUS1_RX_FULL	(1<<4)
-#define TCPC_REG_STATUS1_TX_EMPTY	(1<<3)
-#define TCPC_REG_STATUS1_TX_FULL	(1<<2)
-
-#define TCPC_REG_INTERRUPT	0x42
-#define TCPC_REG_INTERRUPT_VBUSOK	(1<<7)
-#define TCPC_REG_INTERRUPT_ACTIVITY	(1<<6)
-#define TCPC_REG_INTERRUPT_COMP_CHNG	(1<<5)
-#define TCPC_REG_INTERRUPT_CRC_CHK	(1<<4)
-#define TCPC_REG_INTERRUPT_ALERT	(1<<3)
-#define TCPC_REG_INTERRUPT_WAKE		(1<<2)
-#define TCPC_REG_INTERRUPT_COLLISION	(1<<1)
-#define TCPC_REG_INTERRUPT_BC_LVL	(1<<0)
-
-#define TCPC_REG_FIFOS		0x43
+#define TCPC_REG_STATUS1A_TOGSS (1 << 3)
+#define TCPC_REG_STATUS1A_TOGSS_RUNNING 0x0
+#define TCPC_REG_STATUS1A_TOGSS_SRC1 0x1
+#define TCPC_REG_STATUS1A_TOGSS_SRC2 0x2
+#define TCPC_REG_STATUS1A_TOGSS_SNK1 0x5
+#define TCPC_REG_STATUS1A_TOGSS_SNK2 0x6
+#define TCPC_REG_STATUS1A_TOGSS_AA 0x7
+#define TCPC_REG_STATUS1A_TOGSS_POS (3)
+#define TCPC_REG_STATUS1A_TOGSS_MASK (0x7)
+
+#define TCPC_REG_STATUS1A_RXSOP2DB (1 << 2)
+#define TCPC_REG_STATUS1A_RXSOP1DB (1 << 1)
+#define TCPC_REG_STATUS1A_RXSOP (1 << 0)
+
+#define TCPC_REG_INTERRUPTA 0x3E
+#define TCPC_REG_INTERRUPTA_OCP_TEMP (1 << 7)
+#define TCPC_REG_INTERRUPTA_TOGDONE (1 << 6)
+#define TCPC_REG_INTERRUPTA_SOFTFAIL (1 << 5)
+#define TCPC_REG_INTERRUPTA_RETRYFAIL (1 << 4)
+#define TCPC_REG_INTERRUPTA_HARDSENT (1 << 3)
+#define TCPC_REG_INTERRUPTA_TX_SUCCESS (1 << 2)
+#define TCPC_REG_INTERRUPTA_SOFTRESET (1 << 1)
+#define TCPC_REG_INTERRUPTA_HARDRESET (1 << 0)
+
+#define TCPC_REG_INTERRUPTB 0x3F
+#define TCPC_REG_INTERRUPTB_GCRCSENT (1 << 0)
+
+#define TCPC_REG_STATUS0 0x40
+#define TCPC_REG_STATUS0_VBUSOK (1 << 7)
+#define TCPC_REG_STATUS0_ACTIVITY (1 << 6)
+#define TCPC_REG_STATUS0_COMP (1 << 5)
+#define TCPC_REG_STATUS0_CRC_CHK (1 << 4)
+#define TCPC_REG_STATUS0_ALERT (1 << 3)
+#define TCPC_REG_STATUS0_WAKE (1 << 2)
+#define TCPC_REG_STATUS0_BC_LVL1 (1 << 1) /* two-bit field */
+#define TCPC_REG_STATUS0_BC_LVL0 (1 << 0) /* two-bit field */
+
+#define TCPC_REG_STATUS1 0x41
+#define TCPC_REG_STATUS1_RXSOP2 (1 << 7)
+#define TCPC_REG_STATUS1_RXSOP1 (1 << 6)
+#define TCPC_REG_STATUS1_RX_EMPTY (1 << 5)
+#define TCPC_REG_STATUS1_RX_FULL (1 << 4)
+#define TCPC_REG_STATUS1_TX_EMPTY (1 << 3)
+#define TCPC_REG_STATUS1_TX_FULL (1 << 2)
+
+#define TCPC_REG_INTERRUPT 0x42
+#define TCPC_REG_INTERRUPT_VBUSOK (1 << 7)
+#define TCPC_REG_INTERRUPT_ACTIVITY (1 << 6)
+#define TCPC_REG_INTERRUPT_COMP_CHNG (1 << 5)
+#define TCPC_REG_INTERRUPT_CRC_CHK (1 << 4)
+#define TCPC_REG_INTERRUPT_ALERT (1 << 3)
+#define TCPC_REG_INTERRUPT_WAKE (1 << 2)
+#define TCPC_REG_INTERRUPT_COLLISION (1 << 1)
+#define TCPC_REG_INTERRUPT_BC_LVL (1 << 0)
+
+#define TCPC_REG_FIFOS 0x43
 
 /* Tokens defined for the FUSB302 TX FIFO */
 enum fusb302_txfifo_tokens {
diff --git a/driver/tcpm/fusb307.c b/driver/tcpm/fusb307.c
index 9a578637a9..2573e81fb3 100644
--- a/driver/tcpm/fusb307.c
+++ b/driver/tcpm/fusb307.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,13 +9,13 @@
 #include "fusb307.h"
 #include "hooks.h"
 #include "task.h"
-#include "tcpci.h"
-#include "tcpm.h"
+#include "tcpm/tcpci.h"
+#include "tcpm/tcpm.h"
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int fusb307_power_supply_reset(int port)
 {
@@ -28,7 +28,7 @@ static int fusb307_tcpm_init(int port)
 
 	rv = tcpci_tcpm_init(port);
 
-	rv = tcpci_set_role_ctrl(port, 1, TYPEC_RP_USB, TYPEC_CC_RD);
+	rv = tcpci_set_role_ctrl(port, TYPEC_DRP, TYPEC_RP_USB, TYPEC_CC_RD);
 	pd_set_dual_role(port, PD_DRP_TOGGLE_ON);
 
 	return rv;
@@ -44,25 +44,29 @@ int fusb307_tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity)
 	tcpm_get_cc(port, &cc1, &cc2);
 	if (cc1) {
 		if (pd_get_power_role(port) == PD_ROLE_SINK) {
-			int role = TCPC_REG_ROLE_CTRL_SET(0,
-			tcpci_get_cached_rp(port), TYPEC_CC_RD, TYPEC_CC_OPEN);
+			int role = TCPC_REG_ROLE_CTRL_SET(
+				0, tcpci_get_cached_rp(port), TYPEC_CC_RD,
+				TYPEC_CC_OPEN);
 
 			tcpc_write(port, TCPC_REG_ROLE_CTRL, role);
 		} else {
-			int role = TCPC_REG_ROLE_CTRL_SET(0,
-			tcpci_get_cached_rp(port), TYPEC_CC_RP, TYPEC_CC_OPEN);
+			int role = TCPC_REG_ROLE_CTRL_SET(
+				0, tcpci_get_cached_rp(port), TYPEC_CC_RP,
+				TYPEC_CC_OPEN);
 
 			tcpc_write(port, TCPC_REG_ROLE_CTRL, role);
 		}
 	} else if (cc2) {
 		if (pd_get_power_role(port) == PD_ROLE_SINK) {
-			int role = TCPC_REG_ROLE_CTRL_SET(0,
-			tcpci_get_cached_rp(port), TYPEC_CC_OPEN, TYPEC_CC_RD);
+			int role = TCPC_REG_ROLE_CTRL_SET(
+				0, tcpci_get_cached_rp(port), TYPEC_CC_OPEN,
+				TYPEC_CC_RD);
 
 			tcpc_write(port, TCPC_REG_ROLE_CTRL, role);
 		} else {
-			int role = TCPC_REG_ROLE_CTRL_SET(0,
-			tcpci_get_cached_rp(port), TYPEC_CC_OPEN, TYPEC_CC_RP);
+			int role = TCPC_REG_ROLE_CTRL_SET(
+				0, tcpci_get_cached_rp(port), TYPEC_CC_OPEN,
+				TYPEC_CC_RP);
 
 			tcpc_write(port, TCPC_REG_ROLE_CTRL, role);
 		}
@@ -77,26 +81,27 @@ int fusb307_tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity)
 }
 
 const struct tcpm_drv fusb307_tcpm_drv = {
-	.init			= &fusb307_tcpm_init,
-	.release		= &tcpci_tcpm_release,
-	.get_cc			= &tcpci_tcpm_get_cc,
+	.init = &fusb307_tcpm_init,
+	.release = &tcpci_tcpm_release,
+	.get_cc = &tcpci_tcpm_get_cc,
 #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	.check_vbus_level	= &tcpci_tcpm_check_vbus_level,
+	.check_vbus_level = &tcpci_tcpm_check_vbus_level,
 #endif
-	.select_rp_value	= &tcpci_tcpm_select_rp_value,
-	.set_cc			= &tcpci_tcpm_set_cc,
-	.set_polarity		= &fusb307_tcpm_set_polarity,
-	.set_vconn		= &tcpci_tcpm_set_vconn,
-	.set_msg_header		= &tcpci_tcpm_set_msg_header,
-	.set_rx_enable		= &tcpci_tcpm_set_rx_enable,
-	.get_message_raw	= &tcpci_tcpm_get_message_raw,
-	.transmit		= &tcpci_tcpm_transmit,
-	.tcpc_alert		= &tcpci_tcpc_alert,
+	.select_rp_value = &tcpci_tcpm_select_rp_value,
+	.set_cc = &tcpci_tcpm_set_cc,
+	.set_polarity = &fusb307_tcpm_set_polarity,
+	.set_vconn = &tcpci_tcpm_set_vconn,
+	.set_msg_header = &tcpci_tcpm_set_msg_header,
+	.set_rx_enable = &tcpci_tcpm_set_rx_enable,
+	.get_message_raw = &tcpci_tcpm_get_message_raw,
+	.transmit = &tcpci_tcpm_transmit,
+	.tcpc_alert = &tcpci_tcpc_alert,
 	.tcpc_enable_auto_discharge_disconnect =
-				  &tcpci_tcpc_enable_auto_discharge_disconnect,
-	.get_chip_info		= &tcpci_get_chip_info,
+		&tcpci_tcpc_enable_auto_discharge_disconnect,
+	.get_chip_info = &tcpci_get_chip_info,
 #if defined(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE)
-	.drp_toggle		= &tcpci_tcpc_drp_toggle,
+	.drp_toggle = &tcpci_tcpc_drp_toggle,
 #endif
+	.set_bist_test_mode = &tcpci_set_bist_test_mode,
+	.get_bist_test_mode = &tcpci_get_bist_test_mode,
 };
-
diff --git a/driver/tcpm/fusb307.h b/driver/tcpm/fusb307.h
index 943b12d5ed..38114c8caa 100644
--- a/driver/tcpm/fusb307.h
+++ b/driver/tcpm/fusb307.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,16 +10,16 @@
 
 #include "usb_pd.h"
 
-#define FUSB307_I2C_SLAVE_ADDR_FLAGS 0x50
+#define FUSB307_I2C_ADDR_FLAGS 0x50
 
-#define TCPC_REG_RESET		0xA2
-#define TCPC_REG_RESET_PD_RESET	BIT(1)
-#define TCPC_REG_RESET_SW_RESET	BIT(0)
+#define TCPC_REG_RESET 0xA2
+#define TCPC_REG_RESET_PD_RESET BIT(1)
+#define TCPC_REG_RESET_SW_RESET BIT(0)
 
-#define TCPC_REG_GPIO1_CFG		0xA4
-#define TCPC_REG_GPIO1_CFG_GPO1_VAL	BIT(2)
-#define TCPC_REG_GPIO1_CFG_GPI1_EN	BIT(1)
-#define TCPC_REG_GPIO1_CFG_GPO1_EN	BIT(0)
+#define TCPC_REG_GPIO1_CFG 0xA4
+#define TCPC_REG_GPIO1_CFG_GPO1_VAL BIT(2)
+#define TCPC_REG_GPIO1_CFG_GPI1_EN BIT(1)
+#define TCPC_REG_GPIO1_CFG_GPO1_EN BIT(0)
 
 int fusb307_power_supply_reset(int port);
 
diff --git a/driver/tcpm/it83xx.c b/driver/tcpm/it83xx.c
index 47c8f3a998..d04cb2f597 100644
--- a/driver/tcpm/it83xx.c
+++ b/driver/tcpm/it83xx.c
@@ -1,28 +1,30 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* TCPM for MCU also running TCPC */
 
+#include "builtin/assert.h"
 #include "common.h"
 #include "config.h"
 #include "console.h"
+#include "hooks.h"
 #include "it83xx_pd.h"
 #include "registers.h"
 #include "system.h"
 #include "task.h"
-#include "tcpci.h"
+#include "tcpm/tcpci.h"
 #include "timer.h"
-#include "util.h"
+#include "usb_common.h"
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
-#include "hooks.h"
+#include "util.h"
 
 #ifdef CONFIG_USB_PD_TCPMV1
 #if defined(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE) || \
-	defined(CONFIG_USB_PD_VBUS_DETECT_TCPC) || \
-	defined(CONFIG_USB_PD_TCPC_LOW_POWER) || \
+	defined(CONFIG_USB_PD_VBUS_DETECT_TCPC) ||  \
+	defined(CONFIG_USB_PD_TCPC_LOW_POWER) ||    \
 	defined(CONFIG_USB_PD_DISCHARGE_TCPC)
 #error "Unsupported config options of IT83xx PD driver"
 #endif
@@ -35,17 +37,19 @@
 #endif
 #endif
 
-/* Wait time for vconn power switch to turn off. */
-#ifndef PD_IT83XX_VCONN_TURN_OFF_DELAY_US
-#define PD_IT83XX_VCONN_TURN_OFF_DELAY_US 500
-#endif
+int rx_en[IT83XX_USBPD_PHY_PORT_COUNT];
+STATIC_IF(CONFIG_USB_PD_DECODE_SOP)
+bool sop_prime_en[IT83XX_USBPD_PHY_PORT_COUNT];
 
 const struct usbpd_ctrl_t usbpd_ctrl_regs[] = {
-	{&IT83XX_GPIO_GPCRF4, &IT83XX_GPIO_GPCRF5, IT83XX_IRQ_USBPD0},
-	{&IT83XX_GPIO_GPCRH1, &IT83XX_GPIO_GPCRH2, IT83XX_IRQ_USBPD1},
+	{ &IT83XX_GPIO_GPCRF4, &IT83XX_GPIO_GPCRF5, IT83XX_IRQ_USBPD0 },
+	{ &IT83XX_GPIO_GPCRH1, &IT83XX_GPIO_GPCRH2, IT83XX_IRQ_USBPD1 },
 };
 BUILD_ASSERT(ARRAY_SIZE(usbpd_ctrl_regs) == IT83XX_USBPD_PHY_PORT_COUNT);
 
+static int it83xx_tcpm_set_rx_enable(int port, int enable);
+static int it83xx_tcpm_set_vconn(int port, int enable);
+
 /*
  * Disable cc analog and pd digital module, but only left Rd_5.1K (Not
  * Dead Battery) analog module alive to assert Rd on CCs. EC reset or
@@ -55,7 +59,7 @@ void it83xx_Rd_5_1K_only_for_hibernate(int port)
 {
 	/* This only apply to active PD port */
 	if (*usbpd_ctrl_regs[port].cc1 == IT83XX_USBPD_CC_PIN_CONFIG &&
-		*usbpd_ctrl_regs[port].cc2 == IT83XX_USBPD_CC_PIN_CONFIG) {
+	    *usbpd_ctrl_regs[port].cc2 == IT83XX_USBPD_CC_PIN_CONFIG) {
 		/* Disable PD PHY */
 		IT83XX_USBPD_GCR(port) &= ~(BIT(0) | BIT(4));
 		/*
@@ -78,9 +82,8 @@ void it83xx_Rd_5_1K_only_for_hibernate(int port)
 	}
 }
 
-static enum tcpc_cc_voltage_status it83xx_get_cc(
-	enum usbpd_port port,
-	enum usbpd_cc_pin cc_pin)
+static enum tcpc_cc_voltage_status it83xx_get_cc(enum usbpd_port port,
+						 enum usbpd_cc_pin cc_pin)
 {
 	enum usbpd_ufp_volt_status ufp_volt;
 	enum usbpd_dfp_volt_status dfp_volt;
@@ -88,8 +91,8 @@ static enum tcpc_cc_voltage_status it83xx_get_cc(
 	int pull;
 
 	pull = (cc_pin == USBPD_CC_PIN_1) ?
-		USBPD_GET_CC1_PULL_REGISTER_SELECTION(port) :
-		USBPD_GET_CC2_PULL_REGISTER_SELECTION(port);
+		       USBPD_GET_CC1_PULL_REGISTER_SELECTION(port) :
+		       USBPD_GET_CC2_PULL_REGISTER_SELECTION(port);
 
 	/* select Rp */
 	if (pull)
@@ -122,7 +125,7 @@ static enum tcpc_cc_voltage_status it83xx_get_cc(
 			cc_state = TYPEC_CC_VOLT_OPEN;
 			break;
 		}
-	/* source */
+		/* source */
 	} else {
 		if (cc_pin == USBPD_CC_PIN_1)
 			dfp_volt = IT83XX_USBPD_DFPVDR(port) & 0xf;
@@ -174,11 +177,10 @@ static int it83xx_tcpm_get_message_raw(int port, uint32_t *buf, int *head)
 	return EC_SUCCESS;
 }
 
-static enum tcpc_transmit_complete it83xx_tx_data(
-	enum usbpd_port port,
-	enum tcpm_transmit_type type,
-	uint16_t header,
-	const uint32_t *buf)
+static enum tcpc_transmit_complete it83xx_tx_data(enum usbpd_port port,
+						  enum tcpci_msg_type type,
+						  uint16_t header,
+						  const uint32_t *buf)
 {
 	int r;
 	uint32_t evt;
@@ -195,10 +197,10 @@ static enum tcpc_transmit_complete it83xx_tx_data(
 	 * on dx version:
 	 * 000b=SOP, 001b=SOP', 010b=SOP", 011b=Debug SOP', 100b=Debug SOP''.
 	 */
-	IT83XX_USBPD_MTSR1(port) =
-		(IT83XX_USBPD_MTSR1(port) & ~0x70) | ((type & 0x7) << 4);
+	IT83XX_USBPD_MTSR1(port) = (IT83XX_USBPD_MTSR1(port) & ~0x70) |
+				   ((type & 0x7) << 4);
 	/* bit7: transmit message is send to cable or not */
-	if (TCPC_TX_SOP == type)
+	if (type == TCPCI_MSG_SOP)
 		IT83XX_USBPD_MTSR0(port) &= ~USBPD_REG_MASK_CABLE_ENABLE;
 	else
 		IT83XX_USBPD_MTSR0(port) |= USBPD_REG_MASK_CABLE_ENABLE;
@@ -220,7 +222,7 @@ static enum tcpc_transmit_complete it83xx_tx_data(
 		/* Start TX */
 		USBPD_KICK_TX_START(port);
 		evt = task_wait_event_mask(TASK_EVENT_PHY_TX_DONE,
-					PD_T_TCPC_TX_TIMEOUT);
+					   PD_T_TCPC_TX_TIMEOUT);
 		/* check TX status */
 		if (USBPD_IS_TX_ERR(port) || (evt & TASK_EVENT_TIMER)) {
 			/*
@@ -244,10 +246,10 @@ static enum tcpc_transmit_complete it83xx_tx_data(
 	return TCPC_TX_COMPLETE_SUCCESS;
 }
 
-static enum tcpc_transmit_complete it83xx_send_hw_reset(enum usbpd_port port,
-				enum tcpm_transmit_type reset_type)
+static enum tcpc_transmit_complete
+it83xx_send_hw_reset(enum usbpd_port port, enum tcpci_msg_type reset_type)
 {
-	if (reset_type == TCPC_TX_CABLE_RESET)
+	if (reset_type == TCPCI_MSG_CABLE_RESET)
 		IT83XX_USBPD_MTSR0(port) |= USBPD_REG_MASK_CABLE_ENABLE;
 	else
 		IT83XX_USBPD_MTSR0(port) &= ~USBPD_REG_MASK_CABLE_ENABLE;
@@ -256,10 +258,13 @@ static enum tcpc_transmit_complete it83xx_send_hw_reset(enum usbpd_port port,
 	USBPD_SEND_HARD_RESET(port);
 	usleep(MSEC);
 
-	if (IT83XX_USBPD_MTSR0(port) & USBPD_REG_MASK_SEND_HW_RESET)
-		return TCPC_TX_COMPLETE_FAILED;
+	if (USBPD_IS_HARD_CABLE_RESET_TX_DONE(port)) {
+		IT83XX_USBPD_ISR(port) =
+			USBPD_REG_MASK_HARD_CABLE_RESET_TX_DONE;
+		return TCPC_TX_COMPLETE_SUCCESS;
+	}
 
-	return TCPC_TX_COMPLETE_SUCCESS;
+	return TCPC_TX_COMPLETE_FAILED;
 }
 
 static void it83xx_send_bist_mode2_pattern(enum usbpd_port port)
@@ -282,21 +287,23 @@ static void it83xx_enable_vconn(enum usbpd_port port, int enabled)
 		/* Disable unused CC to become VCONN */
 		if (cc_pin == USBPD_CC_PIN_1) {
 			IT83XX_USBPD_CCCSR(port) = USBPD_CC2_DISCONNECTED(port);
-			IT83XX_USBPD_CCPSR(port) = (IT83XX_USBPD_CCPSR(port)
-				& ~USBPD_REG_MASK_DISCONNECT_POWER_CC2)
-				| USBPD_REG_MASK_DISCONNECT_POWER_CC1;
+			IT83XX_USBPD_CCPSR(port) =
+				(IT83XX_USBPD_CCPSR(port) &
+				 ~USBPD_REG_MASK_DISCONNECT_POWER_CC2) |
+				USBPD_REG_MASK_DISCONNECT_POWER_CC1;
 		} else {
 			IT83XX_USBPD_CCCSR(port) = USBPD_CC1_DISCONNECTED(port);
-			IT83XX_USBPD_CCPSR(port) = (IT83XX_USBPD_CCPSR(port)
-				& ~USBPD_REG_MASK_DISCONNECT_POWER_CC1)
-				| USBPD_REG_MASK_DISCONNECT_POWER_CC2;
+			IT83XX_USBPD_CCPSR(port) =
+				(IT83XX_USBPD_CCPSR(port) &
+				 ~USBPD_REG_MASK_DISCONNECT_POWER_CC1) |
+				USBPD_REG_MASK_DISCONNECT_POWER_CC2;
 		}
 	} else {
 		/* Enable cc1 and cc2 */
 		IT83XX_USBPD_CCCSR(port) &= ~0xaa;
 		IT83XX_USBPD_CCPSR(port) |=
 			(USBPD_REG_MASK_DISCONNECT_POWER_CC1 |
-			USBPD_REG_MASK_DISCONNECT_POWER_CC2);
+			 USBPD_REG_MASK_DISCONNECT_POWER_CC2);
 	}
 }
 
@@ -353,8 +360,8 @@ static void it83xx_set_power_role(enum usbpd_port port, int power_role)
 static void it83xx_set_data_role(enum usbpd_port port, int pd_role)
 {
 	/* 0: PD_ROLE_UFP 1: PD_ROLE_DFP */
-	IT83XX_USBPD_PDMSR(port) =
-		(IT83XX_USBPD_PDMSR(port) & ~0xc) | ((pd_role & 0x1) << 2);
+	IT83XX_USBPD_PDMSR(port) = (IT83XX_USBPD_PDMSR(port) & ~0xc) |
+				   ((pd_role & 0x1) << 2);
 }
 
 #ifdef CONFIG_USB_PD_FRS_TCPC
@@ -372,15 +379,18 @@ static int it83xx_tcpm_set_frs_enable(int port, int enable)
 		/* W/C status */
 		IT83XX_USBPD_PD30IR(port) = 0x3f;
 		/* Enable FRS detection (cc to GND) interrupt */
-		IT83XX_USBPD_MPD30IR(port) &= ~(USBPD_REG_MASK_PD30_ISR |
-					USBPD_REG_MASK_FAST_SWAP_DETECT_ISR);
+		IT83XX_USBPD_MPD30IR(port) &=
+			~(USBPD_REG_MASK_PD30_ISR |
+			  USBPD_REG_MASK_FAST_SWAP_DETECT_ISR);
 		/* Enable FRS detection (cc to GND) */
-		IT83XX_USBPD_PDQSCR(port) = (IT83XX_USBPD_PDQSCR(port) & ~mask)
-					| USBPD_REG_FAST_SWAP_DETECT_ENABLE;
+		IT83XX_USBPD_PDQSCR(port) =
+			(IT83XX_USBPD_PDQSCR(port) & ~mask) |
+			USBPD_REG_FAST_SWAP_DETECT_ENABLE;
 	} else {
 		/* Disable FRS detection (cc to GND) interrupt */
-		IT83XX_USBPD_MPD30IR(port) |= (USBPD_REG_MASK_PD30_ISR |
-					USBPD_REG_MASK_FAST_SWAP_DETECT_ISR);
+		IT83XX_USBPD_MPD30IR(port) |=
+			(USBPD_REG_MASK_PD30_ISR |
+			 USBPD_REG_MASK_FAST_SWAP_DETECT_ISR);
 		/* Disable FRS detection and requestion */
 		IT83XX_USBPD_PDQSCR(port) &= ~mask;
 	}
@@ -403,13 +413,25 @@ static void it83xx_init(enum usbpd_port port, int role)
 	 * (= retry count + 1)
 	 */
 	IT83XX_USBPD_BMCSR(port) = (IT83XX_USBPD_BMCSR(port) & ~0x70) |
-					((CONFIG_PD_RETRY_COUNT + 1) << 4);
-	/* set SOP: receive SOP message only.
-	 * bit[7]: SOP" support enable.
-	 * bit[6]: SOP' support enable.
-	 * bit[5]: SOP  support enable.
-	 */
-	IT83XX_USBPD_PDMSR(port) = USBPD_REG_MASK_SOP_ENABLE;
+				   ((CONFIG_PD_RETRY_COUNT + 1) << 4);
+	/* Disable Rx decode */
+	it83xx_tcpm_set_rx_enable(port, 0);
+	if (IS_ENABLED(CONFIG_USB_PD_TCPMV1)) {
+		uint8_t flags = 0;
+		/*
+		 * If explicit contract is set in bbram when EC boot up, then
+		 * TCPMv1 set soft reset as first state instead of
+		 * unattached.SNK, so we need to enable BMC PHY for tx module.
+		 *
+		 * NOTE: If the platform is without battery and connects to
+		 * adapter, then cold reset EC, our Rd is always asserted on cc,
+		 * so adapter keeps providing 5v and data in BBRAM are still
+		 * alive.
+		 */
+		if ((pd_get_saved_port_flags(port, &flags) == EC_SUCCESS) &&
+		    (flags & PD_BBRMFLG_EXPLICIT_CONTRACT))
+			USBPD_ENABLE_BMC_PHY(port);
+	}
 	/* W/C status */
 	IT83XX_USBPD_ISR(port) = 0xff;
 	/* enable cc, select cc1 and Rd. */
@@ -422,7 +444,7 @@ static void it83xx_init(enum usbpd_port port, int role)
 	IT83XX_USBPD_IMR(port) = 0xff;
 	/* enable tx done and reset detect interrupt */
 	IT83XX_USBPD_IMR(port) &= ~(USBPD_REG_MASK_MSG_TX_DONE |
-					USBPD_REG_MASK_HARD_RESET_DETECT);
+				    USBPD_REG_MASK_HARD_RESET_DETECT);
 #ifdef IT83XX_INTC_PLUG_IN_OUT_SUPPORT
 	/*
 	 * when tcpc detect type-c plug in (cc lines voltage change), it will
@@ -436,7 +458,7 @@ static void it83xx_init(enum usbpd_port port, int role)
 	/* cc connect */
 	IT83XX_USBPD_CCCSR(port) = 0;
 	/* disable vconn */
-	it83xx_enable_vconn(port, 0);
+	it83xx_tcpm_set_vconn(port, 0);
 	/* TX start from high */
 	IT83XX_USBPD_CCADCR(port) |= BIT(6);
 	/* enable cc1/cc2 */
@@ -455,7 +477,7 @@ static void it83xx_init(enum usbpd_port port, int role)
 }
 
 static void it83xx_select_polarity(enum usbpd_port port,
-					enum usbpd_cc_pin cc_pin)
+				   enum usbpd_cc_pin cc_pin)
 {
 	/* cc1/cc2 selection */
 	if (cc_pin == USBPD_CC_PIN_1)
@@ -501,7 +523,7 @@ static int it83xx_tcpm_release(int port)
 }
 
 static int it83xx_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2)
+			      enum tcpc_cc_voltage_status *cc2)
 {
 	*cc2 = it83xx_get_cc(port, USBPD_CC_PIN_2);
 	*cc1 = it83xx_get_cc(port, USBPD_CC_PIN_1);
@@ -549,13 +571,34 @@ static int it83xx_tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity)
 {
 	enum usbpd_cc_pin cc_pin =
 		(polarity == POLARITY_CC1 || polarity == POLARITY_CC1_DTS) ?
-		USBPD_CC_PIN_1 : USBPD_CC_PIN_2;
+			USBPD_CC_PIN_1 :
+			USBPD_CC_PIN_2;
 
 	it83xx_select_polarity(port, cc_pin);
 
 	return EC_SUCCESS;
 }
 
+__maybe_unused static int it83xx_tcpm_decode_sop_prime_enable(int port,
+							      bool enable)
+{
+	/* Save SOP'/SOP'' enable state */
+	sop_prime_en[port] = enable;
+
+	if (rx_en[port]) {
+		if (enable)
+			IT83XX_USBPD_PDMSR(port) |=
+				(USBPD_REG_MASK_SOPP_ENABLE |
+				 USBPD_REG_MASK_SOPPP_ENABLE);
+		else
+			IT83XX_USBPD_PDMSR(port) &=
+				~(USBPD_REG_MASK_SOPP_ENABLE |
+				  USBPD_REG_MASK_SOPPP_ENABLE);
+	}
+
+	return EC_SUCCESS;
+}
+
 static int it83xx_tcpm_set_vconn(int port, int enable)
 {
 	/*
@@ -570,27 +613,35 @@ static int it83xx_tcpm_set_vconn(int port, int enable)
 			 */
 			it83xx_enable_vconn(port, enable);
 			if (IS_ENABLED(CONFIG_USB_PD_DECODE_SOP))
-				/* Enable tcpc receive SOP' packet */
-				IT83XX_USBPD_PDMSR(port) |=
-					USBPD_REG_MASK_SOPP_ENABLE;
-		}
-
-		/* Turn on/off vconn power switch. */
-		board_pd_vconn_ctrl(port,
-			USBPD_GET_PULL_CC_SELECTION(port) ?
-				USBPD_CC_PIN_2 : USBPD_CC_PIN_1, enable);
-
-		if (!enable) {
-			/* Disable tcpc receive SOP' packet */
+				/* Enable tcpc receive SOP' and SOP'' packet */
+				it83xx_tcpm_decode_sop_prime_enable(port, true);
+			/* Turn on Vconn power switch. */
+			board_pd_vconn_ctrl(port,
+					    USBPD_GET_PULL_CC_SELECTION(port) ?
+						    USBPD_CC_PIN_2 :
+						    USBPD_CC_PIN_1,
+					    enable);
+		} else {
+			/*
+			 * If the pd port has previous connection and supplies
+			 * Vconn, then RO jumping to RW reset the system,
+			 * we never know which cc is the previous Vconn pin,
+			 * so we always turn both cc pins off when disable
+			 * Vconn power switch.
+			 */
+			board_pd_vconn_ctrl(port, USBPD_CC_PIN_1, enable);
+			board_pd_vconn_ctrl(port, USBPD_CC_PIN_2, enable);
+			/* Disable tcpc receive SOP' and SOP'' packet */
 			if (IS_ENABLED(CONFIG_USB_PD_DECODE_SOP))
-				IT83XX_USBPD_PDMSR(port) &=
-					~USBPD_REG_MASK_SOPP_ENABLE;
+				it83xx_tcpm_decode_sop_prime_enable(port,
+								    false);
 			/*
-			 * We need to make sure cc voltage detector is enabled
-			 * after vconn is turned off to avoid the potential risk
-			 * of voltage fed back into Vcore.
+			 * Before disabling cc 5v tolerant, we need to make
+			 * sure cc voltage detector is enabled and Vconn is
+			 * dropped below 3.3v (>500us) to avoid the potential
+			 * risk of voltage fed back into Vcore.
 			 */
-			usleep(PD_IT83XX_VCONN_TURN_OFF_DELAY_US);
+			usleep(IT83XX_USBPD_T_VCONN_BELOW_3_3V);
 			/*
 			 * Since our cc are not Vconn SRC, enable cc analog
 			 * module (ex.UP/RD/DET/Tx/Rx) and disable 5v tolerant.
@@ -619,81 +670,46 @@ static int it83xx_tcpm_set_msg_header(int port, int power_role, int data_role)
 
 static int it83xx_tcpm_set_rx_enable(int port, int enable)
 {
-	int i;
-	bool prevent_deep_sleep = false;
+	/* Save rx_on */
+	rx_en[port] = enable;
 
 	if (enable) {
 		IT83XX_USBPD_IMR(port) &= ~USBPD_REG_MASK_MSG_RX_DONE;
-		USBPD_ENABLE_BMC_PHY(port);
+		IT83XX_USBPD_PDMSR(port) |= USBPD_REG_MASK_SOP_ENABLE;
+		IT83XX_USBPD_VDMMCSR(port) |= USBPD_REG_MASK_HARD_RESET_DECODE;
+		if (IS_ENABLED(CONFIG_USB_PD_DECODE_SOP))
+			it83xx_tcpm_decode_sop_prime_enable(port,
+							    sop_prime_en[port]);
 	} else {
 		IT83XX_USBPD_IMR(port) |= USBPD_REG_MASK_MSG_RX_DONE;
-		USBPD_DISABLE_BMC_PHY(port);
-	}
-
-	/*
-	 * TCPMv1/TCPMv2 handle SLEEP_MASK_USB_PD and Rx_enable order for deep
-	 * sleep mode:
-	 * 1.Exit deep sleep mode, Rx enable -> deep sleep disable:
-	 * In deep sleep mode, ITE TCPC clock is turned off, so we should
-	 * disable deep sleep to leave the mode first then enable Rx, otherwise
-	 * we'll miss packet in the mode.
-	 * 2.Enter deep sleep mode, deep sleep enable -> Rx disable:
-	 * This is OK, but before set Rx disable, our Rx is disabled in deep
-	 * sleep mode period.
-	 *
-	 * So now, we set the SLEEP_MASK_USB_PD only by ITE driver. If any ITE
-	 * PD port Rx is enabled, then disable EC deep sleep.
-	 */
-	for (i = 0; i < CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT; ++i) {
-		if (IT83XX_USBPD_GCR(i) & USBPD_REG_MASK_BMC_PHY) {
-			prevent_deep_sleep = true;
-			break;
-		}
+		IT83XX_USBPD_PDMSR(port) &= ~(USBPD_REG_MASK_SOP_ENABLE |
+					      USBPD_REG_MASK_SOPP_ENABLE |
+					      USBPD_REG_MASK_SOPPP_ENABLE);
+		IT83XX_USBPD_VDMMCSR(port) &= ~USBPD_REG_MASK_HARD_RESET_DECODE;
 	}
 
-	/*
-	 * Check if any other ports have a PD port partner connected.  Deep
-	 * sleep is forbidden if any PD port partner is connected.  Above, we
-	 * only checked for the ITE ports.
-	 */
-	if (!prevent_deep_sleep) {
-		for (; i < board_get_usb_pd_port_count(); i++)
-			if (pd_capable(i))
-				prevent_deep_sleep = true;
-	}
-
-	if (prevent_deep_sleep)
-		disable_sleep(SLEEP_MASK_USB_PD);
-	else
-		enable_sleep(SLEEP_MASK_USB_PD);
-
 	return EC_SUCCESS;
 }
 
-static int it83xx_tcpm_transmit(int port,
-			enum tcpm_transmit_type type,
-			uint16_t header,
-			const uint32_t *data)
+static int it83xx_tcpm_transmit(int port, enum tcpci_msg_type type,
+				uint16_t header, const uint32_t *data)
 {
 	int status = TCPC_TX_COMPLETE_FAILED;
 
 	switch (type) {
-	case TCPC_TX_SOP:
-	case TCPC_TX_SOP_PRIME:
-	case TCPC_TX_SOP_PRIME_PRIME:
-	case TCPC_TX_SOP_DEBUG_PRIME:
-	case TCPC_TX_SOP_DEBUG_PRIME_PRIME:
-		status = it83xx_tx_data(port,
-					type,
-					header,
-					data);
+	case TCPCI_MSG_SOP:
+	case TCPCI_MSG_SOP_PRIME:
+	case TCPCI_MSG_SOP_PRIME_PRIME:
+	case TCPCI_MSG_SOP_DEBUG_PRIME:
+	case TCPCI_MSG_SOP_DEBUG_PRIME_PRIME:
+		status = it83xx_tx_data(port, type, header, data);
 		break;
-	case TCPC_TX_BIST_MODE_2:
+	case TCPCI_MSG_TX_BIST_MODE_2:
 		it83xx_send_bist_mode2_pattern(port);
 		status = TCPC_TX_COMPLETE_SUCCESS;
 		break;
-	case TCPC_TX_HARD_RESET:
-	case TCPC_TX_CABLE_RESET:
+	case TCPCI_MSG_TX_HARD_RESET:
+	case TCPCI_MSG_CABLE_RESET:
 		status = it83xx_send_hw_reset(port, type);
 		break;
 	default:
@@ -705,12 +721,13 @@ static int it83xx_tcpm_transmit(int port,
 	return EC_SUCCESS;
 }
 
-static int it83xx_tcpm_get_chip_info(int port, int live,
-			struct ec_response_pd_chip_info_v1 *chip_info)
+static int
+it83xx_tcpm_get_chip_info(int port, int live,
+			  struct ec_response_pd_chip_info_v1 *chip_info)
 {
 	chip_info->vendor_id = USB_VID_ITE;
-	chip_info->product_id = ((IT83XX_GCTRL_CHIPID1 << 8) |
-				 IT83XX_GCTRL_CHIPID2);
+	chip_info->product_id =
+		((IT83XX_GCTRL_CHIPID1 << 8) | IT83XX_GCTRL_CHIPID2);
 	chip_info->device_id = IT83XX_GCTRL_CHIPVER & 0xf;
 	chip_info->fw_version_number = 0xEC;
 
@@ -721,10 +738,12 @@ static int it83xx_tcpm_get_chip_info(int port, int live,
 static int it83xx_tcpm_enter_low_power_mode(int port)
 {
 	/*
-	 * ITE embedded TCPC do low power mode in idle_task(), when all ITE
-	 * ports are Rx disabled (means not in Attach.SRC/SNK state or
-	 * pd_disabled_mask be set). In deep sleep mode, the timer wakeup PD
-	 * task every 5ms, then PD task change the CC lines termination.
+	 * ITE embedded TCPC SLEEP_MASK_USB_PD flag is only controlled by
+	 * it83xx driver in tc_update_pd_sleep_mask(), and do low power
+	 * mode in idle_task().
+	 * In deep sleep mode, ITE TCPC clock is turned off, and the
+	 * timer every 5ms to exit the mode and wakeup PD task to run
+	 * (ex. change the CC lines termination).
 	 */
 	return EC_SUCCESS;
 }
@@ -740,16 +759,18 @@ static void it83xx_tcpm_switch_plug_out_type(int port)
 	if ((cc1 == TYPEC_CC_VOLT_RD && cc2 == TYPEC_CC_VOLT_RD) ||
 	    (cc1 == TYPEC_CC_VOLT_RA && cc2 == TYPEC_CC_VOLT_RA))
 		/* We're source, switch to detect audio/debug plug out. */
-		IT83XX_USBPD_TCDCR(port) = (IT83XX_USBPD_TCDCR(port) &
-				~USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE) |
-				USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT |
-				USBPD_REG_PLUG_OUT_SELECT;
+		IT83XX_USBPD_TCDCR(port) =
+			(IT83XX_USBPD_TCDCR(port) &
+			 ~USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE) |
+			USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT |
+			USBPD_REG_PLUG_OUT_SELECT;
 	else if (cc1 == TYPEC_CC_VOLT_RD || cc2 == TYPEC_CC_VOLT_RD)
 		/* We're source, switch to detect sink plug out. */
-		IT83XX_USBPD_TCDCR(port) = (IT83XX_USBPD_TCDCR(port) &
-				~USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE &
-				~USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT) |
-				USBPD_REG_PLUG_OUT_SELECT;
+		IT83XX_USBPD_TCDCR(port) =
+			(IT83XX_USBPD_TCDCR(port) &
+			 ~USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE &
+			 ~USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT) |
+			USBPD_REG_PLUG_OUT_SELECT;
 	else if (cc1 >= TYPEC_CC_VOLT_RP_DEF || cc2 >= TYPEC_CC_VOLT_RP_DEF)
 		/*
 		 * We're sink, disable detect interrupt, so messages on cc line
@@ -769,11 +790,59 @@ void switch_plug_out_type(enum usbpd_port port)
 	it83xx_tcpm_switch_plug_out_type(port);
 }
 
-#ifdef CONFIG_USB_PD_TCPMV2
+__override void tc_update_pd_sleep_mask(int port)
+{
+	int i;
+	bool prevent_deep_sleep = false;
+
+	/*
+	 * Check ITE embedded pd ports to set SLEEP_MASK_USB_PD:
+	 * In tc_attached_[src, snk]_entry states, calling HOOK_CONNECT
+	 * to enable BMC PHY, and if one of ITE pd ports BMC PHY is enable,
+	 * then EC deep doze mode will be disabled.
+	 * Otherwise, EC deep doze mode will be enabled.
+	 */
+	for (i = 0; i < CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT; ++i) {
+		if (IT83XX_USBPD_GCR(i) & USBPD_REG_MASK_BMC_PHY) {
+			prevent_deep_sleep = true;
+			break;
+		}
+	}
+
+	/*
+	 * Check Other stand alone pd ports to set SLEEP_MASK_USB_PD:
+	 * In [pe_src_send_capabilities_run, pe_snk_select_capability_entry]
+	 * states receive [GoodCRC, SRC_CAP] from port partner, then EC deep
+	 * doze mode will be disabled.
+	 * Otherwise, EC deep doze mode will be enabled.
+	 */
+	if (!prevent_deep_sleep) {
+		for (; i < board_get_usb_pd_port_count(); i++)
+			if (pd_capable(i))
+				prevent_deep_sleep = true;
+	}
+
+	if (prevent_deep_sleep)
+		disable_sleep(SLEEP_MASK_USB_PD);
+	else
+		enable_sleep(SLEEP_MASK_USB_PD);
+}
+
 static void it83xx_tcpm_hook_connect(void)
 {
 	int port = TASK_ID_TO_PD_PORT(task_get_current());
 
+	/*
+	 * If it isn't ITE active port, then return.
+	 *
+	 * NOTE: If we don't use all the ITE pd ports on a board, then we
+	 *       need to start from port0 to use the ITE pd port. If we
+	 *       start from port1, then port1 HOOK function never works.
+	 */
+	if (port > (CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT - 1))
+		return;
+
+#ifdef CONFIG_USB_PD_TCPMV2
 	/*
 	 * There are five cases that hook_connect() be called by TCPMv2:
 	 * 1)AttachWait.SNK -> Attached.SNK: disable detect interrupt.
@@ -789,52 +858,91 @@ static void it83xx_tcpm_hook_connect(void)
 	 * SRC_DISCONNECT and SNK_DISCONNECT in TCPMv1. Every time we go to
 	 * Try.SRC/TryWait.SNK state, the plug in interrupt will be enabled and
 	 * fire for 3), 4), 5) cases, then set correctly for the SRC detect plug
-	 * out or the SNK disable detect, so TCPMv1 needn't hook connection.
+	 * out or the SNK disable detect, so TCPMv1 needn't this.
 	 */
 	it83xx_tcpm_switch_plug_out_type(port);
+#endif
+	/* Enable PD PHY Tx and Rx module since type-c has connected. */
+	USBPD_ENABLE_BMC_PHY(port);
+	/*
+	 * After we're in attached.[SRC, SNK] states and before we receive
+	 * [GoodCRC of SRC_CAP, SRC_CAP] this period time, if EC goes to
+	 * deep doze mode, the pd clock will be gated, then pd can't
+	 * transmit and receive any messages, so we disable deep doze mode
+	 * to make sure that pd won't miss any messages.
+	 */
+	tc_update_pd_sleep_mask(port);
 }
 
 DECLARE_HOOK(HOOK_USB_PD_CONNECT, it83xx_tcpm_hook_connect, HOOK_PRIO_DEFAULT);
-#endif
 
-static void it83xx_tcpm_sw_reset(void)
+static void it83xx_tcpm_hook_disconnect(void)
 {
 	int port = TASK_ID_TO_PD_PORT(task_get_current());
 
+	/*
+	 * If it isn't ITE active port, then return.
+	 *
+	 * NOTE: If we don't use all the ITE pd ports on a board, then we
+	 *       need to start from port0 to use the ITE pd port. If we
+	 *       start from port1, then port1 HOOK function never works.
+	 */
+	if (port > (CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT - 1))
+		return;
+
 	if (IS_ENABLED(IT83XX_INTC_PLUG_IN_OUT_SUPPORT))
 		/*
 		 * Switch to detect plug in and enable detect plug in interrupt,
 		 * since pd task has detected a type-c physical disconnected.
 		 */
-		IT83XX_USBPD_TCDCR(port) &= ~(USBPD_REG_PLUG_OUT_SELECT |
-			USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE);
+		IT83XX_USBPD_TCDCR(port) &=
+			~(USBPD_REG_PLUG_OUT_SELECT |
+			  USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE);
 
 	/* exit BIST test data mode */
 	USBPD_SW_RESET(port);
+
+	/*
+	 * Init rx status and disable PD PHY Tx and Rx module for better power
+	 * consumption since type-c has disconnected.
+	 */
+	rx_en[port] = 0;
+	if (IS_ENABLED(CONFIG_USB_PD_DECODE_SOP))
+		sop_prime_en[port] = 0;
+	USBPD_DISABLE_BMC_PHY(port);
+	/*
+	 * Since PD BMC PHY is off, then EC can go to deep doze mode and
+	 * turn off pd clock.
+	 */
+	tc_update_pd_sleep_mask(port);
 }
 
-DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, it83xx_tcpm_sw_reset, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, it83xx_tcpm_hook_disconnect,
+	     HOOK_PRIO_DEFAULT);
 
 const struct tcpm_drv it83xx_tcpm_drv = {
-	.init			= &it83xx_tcpm_init,
-	.release		= &it83xx_tcpm_release,
-	.get_cc			= &it83xx_tcpm_get_cc,
-	.select_rp_value	= &it83xx_tcpm_select_rp_value,
-	.set_cc			= &it83xx_tcpm_set_cc,
-	.set_polarity		= &it83xx_tcpm_set_polarity,
-	.set_vconn		= &it83xx_tcpm_set_vconn,
-	.set_msg_header		= &it83xx_tcpm_set_msg_header,
-	.set_rx_enable		= &it83xx_tcpm_set_rx_enable,
-	.get_message_raw	= &it83xx_tcpm_get_message_raw,
-	.transmit		= &it83xx_tcpm_transmit,
+	.init = &it83xx_tcpm_init,
+	.release = &it83xx_tcpm_release,
+	.get_cc = &it83xx_tcpm_get_cc,
+	.select_rp_value = &it83xx_tcpm_select_rp_value,
+	.set_cc = &it83xx_tcpm_set_cc,
+	.set_polarity = &it83xx_tcpm_set_polarity,
+#ifdef CONFIG_USB_PD_DECODE_SOP
+	.sop_prime_enable = &it83xx_tcpm_decode_sop_prime_enable,
+#endif
+	.set_vconn = &it83xx_tcpm_set_vconn,
+	.set_msg_header = &it83xx_tcpm_set_msg_header,
+	.set_rx_enable = &it83xx_tcpm_set_rx_enable,
+	.get_message_raw = &it83xx_tcpm_get_message_raw,
+	.transmit = &it83xx_tcpm_transmit,
 #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-	.drp_toggle		= NULL,
+	.drp_toggle = NULL,
 #endif
-	.get_chip_info		= &it83xx_tcpm_get_chip_info,
+	.get_chip_info = &it83xx_tcpm_get_chip_info,
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	.enter_low_power_mode	= &it83xx_tcpm_enter_low_power_mode,
+	.enter_low_power_mode = &it83xx_tcpm_enter_low_power_mode,
 #endif
 #ifdef CONFIG_USB_PD_FRS_TCPC
-	.set_frs_enable		= &it83xx_tcpm_set_frs_enable,
+	.set_frs_enable = &it83xx_tcpm_set_frs_enable,
 #endif
 };
diff --git a/driver/tcpm/it83xx_pd.h b/driver/tcpm/it83xx_pd.h
index b04570a65d..db9dda6285 100644
--- a/driver/tcpm/it83xx_pd.h
+++ b/driver/tcpm/it83xx_pd.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,201 +7,212 @@
 #ifndef __CROS_EC_DRIVER_TCPM_IT83XX_H
 #define __CROS_EC_DRIVER_TCPM_IT83XX_H
 
+#include "driver/tcpm/it8xxx2_pd_public.h"
+
+#include <stdint.h>
+
 /* USBPD Controller */
 #if defined(CONFIG_USB_PD_TCPM_DRIVER_IT83XX)
-#define IT83XX_USBPD_BASE(port)   (0x00F03700 + (0x100 * (port)))
+#define IT83XX_USBPD_BASE(port) (0x00F03700 + (0x100 * (port)))
 
-#define IT83XX_USBPD_GCR(p)       REG8(IT83XX_USBPD_BASE(p)+0x0)
-#define USBPD_REG_MASK_SW_RESET_BIT               BIT(7)
-#define USBPD_REG_MASK_TYPE_C_DETECT_RESET        BIT(6)
-#define USBPD_REG_MASK_BMC_PHY                    BIT(4)
-#define USBPD_REG_MASK_AUTO_SEND_SW_RESET         BIT(3)
-#define USBPD_REG_MASK_AUTO_SEND_HW_RESET         BIT(2)
-#define USBPD_REG_MASK_SNIFFER_MODE               BIT(1)
-#define USBPD_REG_MASK_GLOBAL_ENABLE              BIT(0)
-#define IT83XX_USBPD_PDMSR(p)     REG8(IT83XX_USBPD_BASE(p)+0x01)
-#define USBPD_REG_MASK_SOPPP_ENABLE               BIT(7)
-#define USBPD_REG_MASK_SOPP_ENABLE                BIT(6)
-#define USBPD_REG_MASK_SOP_ENABLE                 BIT(5)
-#define IT83XX_USBPD_CCGCR(p)     REG8(IT83XX_USBPD_BASE(p)+0x04)
-#define USBPD_REG_MASK_DISABLE_CC                 BIT(4)
-#define IT83XX_USBPD_CCCSR(p)     REG8(IT83XX_USBPD_BASE(p)+0x05)
-#define USBPD_REG_MASK_CC2_DISCONNECT             BIT(7)
+#define IT83XX_USBPD_GCR(p) REG8(IT83XX_USBPD_BASE(p) + 0x0)
+#define USBPD_REG_MASK_SW_RESET_BIT BIT(7)
+#define USBPD_REG_MASK_TYPE_C_DETECT_RESET BIT(6)
+#define USBPD_REG_MASK_BMC_PHY BIT(4)
+#define USBPD_REG_MASK_AUTO_SEND_SW_RESET BIT(3)
+#define USBPD_REG_MASK_AUTO_SEND_HW_RESET BIT(2)
+#define USBPD_REG_MASK_SNIFFER_MODE BIT(1)
+#define USBPD_REG_MASK_GLOBAL_ENABLE BIT(0)
+#define IT83XX_USBPD_PDMSR(p) REG8(IT83XX_USBPD_BASE(p) + 0x01)
+#define USBPD_REG_MASK_SOPPP_ENABLE BIT(7)
+#define USBPD_REG_MASK_SOPP_ENABLE BIT(6)
+#define USBPD_REG_MASK_SOP_ENABLE BIT(5)
+#define IT83XX_USBPD_CCGCR(p) REG8(IT83XX_USBPD_BASE(p) + 0x04)
+#define USBPD_REG_MASK_DISABLE_CC BIT(4)
+#define IT83XX_USBPD_CCCSR(p) REG8(IT83XX_USBPD_BASE(p) + 0x05)
+#define USBPD_REG_MASK_CC2_DISCONNECT BIT(7)
 #define USBPD_REG_MASK_CC2_DISCONNECT_5_1K_TO_GND BIT(6)
-#define USBPD_REG_MASK_CC1_DISCONNECT             BIT(3)
+#define USBPD_REG_MASK_CC1_DISCONNECT BIT(3)
 #define USBPD_REG_MASK_CC1_DISCONNECT_5_1K_TO_GND BIT(2)
 #ifdef IT83XX_USBPD_CC_VOLTAGE_DETECTOR_INDEPENDENT
-#define USBPD_REG_MASK_DISABLE_CC_VOL_DETECTOR    (BIT(5) | BIT(1))
+#define USBPD_REG_MASK_DISABLE_CC_VOL_DETECTOR (BIT(5) | BIT(1))
 #else
-#define USBPD_REG_MASK_DISABLE_CC_VOL_DETECTOR    BIT(1)
+#define USBPD_REG_MASK_DISABLE_CC_VOL_DETECTOR BIT(1)
 #endif
-#define IT83XX_USBPD_CCPSR(p)     REG8(IT83XX_USBPD_BASE(p)+0x06)
-#define USBPD_REG_MASK_DISCONNECT_5_1K_CC2_DB     BIT(6)
-#define USBPD_REG_MASK_DISCONNECT_POWER_CC2       BIT(5)
-#define USBPD_REG_MASK_DISCONNECT_5_1K_CC1_DB     BIT(2)
-#define USBPD_REG_MASK_DISCONNECT_POWER_CC1       BIT(1)
-#define IT83XX_USBPD_DFPVDR(p)    REG8(IT83XX_USBPD_BASE(p)+0x08)
-#define IT83XX_USBPD_UFPVDR(p)    REG8(IT83XX_USBPD_BASE(p)+0x09)
-#define IT83XX_USBPD_PDPSR(p)     REG8(IT83XX_USBPD_BASE(p)+0x0B)
-#define USBPD_REG_MASK_AUTO_FRS_DISABLE           BIT(7)
-#define IT83XX_USBPD_CCADCR(p)    REG8(IT83XX_USBPD_BASE(p)+0x0C)
-#define IT83XX_USBPD_ISR(p)       REG8(IT83XX_USBPD_BASE(p)+0x14)
-#define USBPD_REG_MASK_TYPE_C_DETECT              BIT(7)
-#define USBPD_REG_MASK_CABLE_RESET_DETECT         BIT(6)
-#define USBPD_REG_MASK_HARD_RESET_DETECT          BIT(5)
-#define USBPD_REG_MASK_MSG_RX_DONE                BIT(4)
-#define USBPD_REG_MASK_AUTO_SOFT_RESET_TX_DONE    BIT(3)
-#define USBPD_REG_MASK_HARD_RESET_TX_DONE         BIT(2)
-#define USBPD_REG_MASK_MSG_TX_DONE                BIT(1)
-#define USBPD_REG_MASK_TIMER_TIMEOUT              BIT(0)
-#define IT83XX_USBPD_IMR(p)       REG8(IT83XX_USBPD_BASE(p)+0x15)
-#define IT83XX_USBPD_MTCR(p)      REG8(IT83XX_USBPD_BASE(p)+0x18)
-#define USBPD_REG_MASK_SW_RESET_TX_STAT           BIT(3)
-#define USBPD_REG_MASK_TX_BUSY_STAT               BIT(2)
-#define USBPD_REG_MASK_TX_DISCARD_STAT            BIT(2)
+#define IT83XX_USBPD_CCPSR(p) REG8(IT83XX_USBPD_BASE(p) + 0x06)
+#define USBPD_REG_MASK_DISCONNECT_5_1K_CC2_DB BIT(6)
+#define USBPD_REG_MASK_DISCONNECT_POWER_CC2 BIT(5)
+#define USBPD_REG_MASK_DISCONNECT_5_1K_CC1_DB BIT(2)
+#define USBPD_REG_MASK_DISCONNECT_POWER_CC1 BIT(1)
+#define IT83XX_USBPD_DFPVDR(p) REG8(IT83XX_USBPD_BASE(p) + 0x08)
+#define IT83XX_USBPD_UFPVDR(p) REG8(IT83XX_USBPD_BASE(p) + 0x09)
+#define IT83XX_USBPD_PDPSR(p) REG8(IT83XX_USBPD_BASE(p) + 0x0B)
+#define USBPD_REG_MASK_AUTO_FRS_DISABLE BIT(7)
+#define IT83XX_USBPD_CCADCR(p) REG8(IT83XX_USBPD_BASE(p) + 0x0C)
+#define IT83XX_USBPD_ISR(p) REG8(IT83XX_USBPD_BASE(p) + 0x14)
+#define USBPD_REG_MASK_TYPE_C_DETECT BIT(7)
+#define USBPD_REG_MASK_CABLE_RESET_DETECT BIT(6)
+#define USBPD_REG_MASK_HARD_RESET_DETECT BIT(5)
+#define USBPD_REG_MASK_MSG_RX_DONE BIT(4)
+#define USBPD_REG_MASK_AUTO_SOFT_RESET_TX_DONE BIT(3)
+#define USBPD_REG_MASK_HARD_CABLE_RESET_TX_DONE BIT(2)
+#define USBPD_REG_MASK_MSG_TX_DONE BIT(1)
+#define USBPD_REG_MASK_TIMER_TIMEOUT BIT(0)
+#define IT83XX_USBPD_IMR(p) REG8(IT83XX_USBPD_BASE(p) + 0x15)
+#define IT83XX_USBPD_MTCR(p) REG8(IT83XX_USBPD_BASE(p) + 0x18)
+#define USBPD_REG_MASK_SW_RESET_TX_STAT BIT(3)
+#define USBPD_REG_MASK_TX_BUSY_STAT BIT(2)
+#define USBPD_REG_MASK_TX_DISCARD_STAT BIT(2)
 #ifdef IT83XX_PD_TX_ERROR_STATUS_BIT5
-#define USBPD_REG_MASK_TX_ERR_STAT                BIT(5)
+#define USBPD_REG_MASK_TX_ERR_STAT BIT(5)
 #else
-#define USBPD_REG_MASK_TX_ERR_STAT                BIT(1)
+#define USBPD_REG_MASK_TX_ERR_STAT BIT(1)
 #endif
-#define USBPD_REG_MASK_TX_START                   BIT(0)
-#define IT83XX_USBPD_MTSR0(p)     REG8(IT83XX_USBPD_BASE(p)+0x19)
-#define USBPD_REG_MASK_CABLE_ENABLE               BIT(7)
-#define USBPD_REG_MASK_SEND_HW_RESET              BIT(6)
-#define USBPD_REG_MASK_SEND_BIST_MODE_2           BIT(5)
-#define IT83XX_USBPD_MTSR1(p)     REG8(IT83XX_USBPD_BASE(p)+0x1A)
-#define IT83XX_USBPD_VDMMCSR(p)   REG8(IT83XX_USBPD_BASE(p)+0x1B)
-#define IT83XX_USBPD_MRSR(p)      REG8(IT83XX_USBPD_BASE(p)+0x1C)
-#define USBPD_REG_GET_SOP_TYPE_RX(mrsr)           (((mrsr) >> 4) & 0x7)
-#define USBPD_REG_MASK_RX_MSG_VALID               BIT(0)
-#define IT83XX_USBPD_PEFSMR(p)    REG8(IT83XX_USBPD_BASE(p)+0x1D)
-#define IT83XX_USBPD_PES0R(p)     REG8(IT83XX_USBPD_BASE(p)+0x1E)
-#define IT83XX_USBPD_PES1R(p)     REG8(IT83XX_USBPD_BASE(p)+0x1F)
-#define IT83XX_USBPD_TDO(p)       REG32(IT83XX_USBPD_BASE(p)+0x20)
-#define IT83XX_USBPD_AGTMHLR(p)   REG8(IT83XX_USBPD_BASE(p)+0x3C)
-#define IT83XX_USBPD_AGTMHHR(p)   REG8(IT83XX_USBPD_BASE(p)+0x3D)
-#define IT83XX_USBPD_TMHLR(p)     REG8(IT83XX_USBPD_BASE(p)+0x3E)
-#define IT83XX_USBPD_TMHHR(p)     REG8(IT83XX_USBPD_BASE(p)+0x3F)
-#define IT83XX_USBPD_RDO0(p)      REG32(IT83XX_USBPD_BASE(p)+0x40)
-#define IT83XX_USBPD_RMH(p)       REG16(IT83XX_USBPD_BASE(p)+0x5E)
-#define IT83XX_USBPD_CCPSR0(p)    REG8(IT83XX_USBPD_BASE(p)+0x60)
-#define IT83XX_USBPD_BMCSR(p)     REG8(IT83XX_USBPD_BASE(p)+0x64)
-#define IT83XX_USBPD_PDMHSR(p)    REG8(IT83XX_USBPD_BASE(p)+0x65)
-#define IT83XX_USBPD_TCDCR(p)     REG8(IT83XX_USBPD_BASE(p)+0x67)
-#define USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT     BIT(7)
-#define USBPD_REG_MASK_TYPEC_PLUG_IN_OUT_ISR      BIT(4)
-#define USBPD_REG_PLUG_OUT_SELECT                 BIT(3)
-#define USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE      BIT(1)
-#define USBPD_REG_PLUG_IN_OUT_DETECT_STAT         BIT(0)
-#define IT83XX_USBPD_PDQSCR(p)    REG8(IT83XX_USBPD_BASE(p)+0x70)
-#define USBPD_REG_FAST_SWAP_REQUEST_ENABLE     BIT(1)
-#define USBPD_REG_FAST_SWAP_DETECT_ENABLE      BIT(0)
-#define IT83XX_USBPD_PD30IR(p)    REG8(IT83XX_USBPD_BASE(p)+0x78)
-#define USBPD_REG_FAST_SWAP_DETECT_STAT        BIT(4)
-#define IT83XX_USBPD_MPD30IR(p)   REG8(IT83XX_USBPD_BASE(p)+0x7A)
-#define USBPD_REG_MASK_PD30_ISR                BIT(7)
-#define USBPD_REG_MASK_FAST_SWAP_DETECT_ISR    BIT(4)
+#define USBPD_REG_MASK_TX_START BIT(0)
+#define IT83XX_USBPD_MTSR0(p) REG8(IT83XX_USBPD_BASE(p) + 0x19)
+#define USBPD_REG_MASK_CABLE_ENABLE BIT(7)
+#define USBPD_REG_MASK_SEND_HW_RESET BIT(6)
+#define USBPD_REG_MASK_SEND_BIST_MODE_2 BIT(5)
+#define IT83XX_USBPD_MTSR1(p) REG8(IT83XX_USBPD_BASE(p) + 0x1A)
+#define IT83XX_USBPD_VDMMCSR(p) REG8(IT83XX_USBPD_BASE(p) + 0x1B)
+#define USBPD_REG_MASK_HARD_RESET_DECODE BIT(0)
+#define IT83XX_USBPD_MRSR(p) REG8(IT83XX_USBPD_BASE(p) + 0x1C)
+#define USBPD_REG_GET_SOP_TYPE_RX(mrsr) (((mrsr) >> 4) & 0x7)
+#define USBPD_REG_MASK_RX_MSG_VALID BIT(0)
+#define IT83XX_USBPD_PEFSMR(p) REG8(IT83XX_USBPD_BASE(p) + 0x1D)
+#define IT83XX_USBPD_PES0R(p) REG8(IT83XX_USBPD_BASE(p) + 0x1E)
+#define IT83XX_USBPD_PES1R(p) REG8(IT83XX_USBPD_BASE(p) + 0x1F)
+#define IT83XX_USBPD_TDO(p) REG32(IT83XX_USBPD_BASE(p) + 0x20)
+#define IT83XX_USBPD_AGTMHLR(p) REG8(IT83XX_USBPD_BASE(p) + 0x3C)
+#define IT83XX_USBPD_AGTMHHR(p) REG8(IT83XX_USBPD_BASE(p) + 0x3D)
+#define IT83XX_USBPD_TMHLR(p) REG8(IT83XX_USBPD_BASE(p) + 0x3E)
+#define IT83XX_USBPD_TMHHR(p) REG8(IT83XX_USBPD_BASE(p) + 0x3F)
+#define IT83XX_USBPD_RDO0(p) REG32(IT83XX_USBPD_BASE(p) + 0x40)
+#define IT83XX_USBPD_RMH(p) REG16(IT83XX_USBPD_BASE(p) + 0x5E)
+#define IT83XX_USBPD_CCPSR0(p) REG8(IT83XX_USBPD_BASE(p) + 0x60)
+#define IT83XX_USBPD_BMCSR(p) REG8(IT83XX_USBPD_BASE(p) + 0x64)
+#define IT83XX_USBPD_PDMHSR(p) REG8(IT83XX_USBPD_BASE(p) + 0x65)
+#define IT83XX_USBPD_TCDCR(p) REG8(IT83XX_USBPD_BASE(p) + 0x67)
+#define USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT BIT(7)
+#define USBPD_REG_MASK_TYPEC_PLUG_IN_OUT_ISR BIT(4)
+#define USBPD_REG_PLUG_OUT_SELECT BIT(3)
+#define USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE BIT(1)
+#define USBPD_REG_PLUG_IN_OUT_DETECT_STAT BIT(0)
+#define IT83XX_USBPD_PDQSCR(p) REG8(IT83XX_USBPD_BASE(p) + 0x70)
+#define USBPD_REG_FAST_SWAP_REQUEST_ENABLE BIT(1)
+#define USBPD_REG_FAST_SWAP_DETECT_ENABLE BIT(0)
+#define IT83XX_USBPD_PD30IR(p) REG8(IT83XX_USBPD_BASE(p) + 0x78)
+#define USBPD_REG_FAST_SWAP_DETECT_STAT BIT(4)
+#define IT83XX_USBPD_MPD30IR(p) REG8(IT83XX_USBPD_BASE(p) + 0x7A)
+#define USBPD_REG_MASK_PD30_ISR BIT(7)
+#define USBPD_REG_MASK_FAST_SWAP_DETECT_ISR BIT(4)
 
 #elif defined(CONFIG_USB_PD_TCPM_DRIVER_IT8XXX2)
-#define IT83XX_USBPD_BASE(port)     (0x00F03700 + (0x100 * (port) * (port)))
+#define IT83XX_USBPD_BASE(port) (0x00F03700 + (0x100 * (port) * (port)))
 
-#define IT83XX_USBPD_PDGCR(p)       REG8(IT83XX_USBPD_BASE(p)+0x0)
-#define USBPD_REG_MASK_SW_RESET_BIT               BIT(7)
-#define USBPD_REG_MASK_PROTOCOL_STATE_CLEAR       BIT(6)
-#define USBPD_REG_MASK_BIST_DATA_MODE             BIT(4)
-#define USBPD_REG_MASK_AUTO_BIST_RESPONSE         BIT(3)
-#define USBPD_REG_MASK_TX_MESSAGE_ENABLE          BIT(2)
-#define USBPD_REG_MASK_SNIFFER_MODE               BIT(1)
-#define USBPD_REG_MASK_BMC_PHY                    BIT(0)
-#define IT83XX_USBPD_PDCSR0(p)      REG8(IT83XX_USBPD_BASE(p)+0x01)
-#define IT83XX_USBPD_PDMSR(p)       REG8(IT83XX_USBPD_BASE(p)+0x02)
+#define IT83XX_USBPD_PDGCR(p) REG8(IT83XX_USBPD_BASE(p) + 0x0)
+#define USBPD_REG_MASK_SW_RESET_BIT BIT(7)
+#define USBPD_REG_MASK_PROTOCOL_STATE_CLEAR BIT(6)
+#define USBPD_REG_MASK_BIST_DATA_MODE BIT(4)
+#define USBPD_REG_MASK_AUTO_BIST_RESPONSE BIT(3)
+#define USBPD_REG_MASK_TX_MESSAGE_ENABLE BIT(2)
+#define USBPD_REG_MASK_SNIFFER_MODE BIT(1)
+#define USBPD_REG_MASK_BMC_PHY BIT(0)
+#define IT83XX_USBPD_PDCSR0(p) REG8(IT83XX_USBPD_BASE(p) + 0x01)
+#define IT83XX_USBPD_PDMSR(p) REG8(IT83XX_USBPD_BASE(p) + 0x02)
 #define USBPD_REG_MASK_DISABLE_AUTO_GEN_TX_HEADER BIT(7)
-#define USBPD_REG_MASK_AUTO_FRS_DISABLE           BIT(6)
-#define IT83XX_USBPD_PDCSR1(p)      REG8(IT83XX_USBPD_BASE(p)+0x03)
-#define USBPD_REG_MASK_CABLE_RESET_RX_ENABLE      BIT(6)
-#define USBPD_REG_MASK_HARD_RESET_RX_ENABLE       BIT(5)
-#define USBPD_REG_MASK_SOPPP_RX_ENABLE            BIT(2)
-#define USBPD_REG_MASK_SOPP_RX_ENABLE             BIT(1)
-#define USBPD_REG_MASK_SOP_RX_ENABLE              BIT(0)
-#define IT83XX_USBPD_CCGCR(p)       REG8(IT83XX_USBPD_BASE(p)+0x04)
-#define USBPD_REG_MASK_DISABLE_CC                 BIT(7)
-#define USBPD_REG_MASK_DISABLE_CC_VOL_DETECTOR    BIT(6)
-#define USBPD_REG_MASK_CC_SELECT_RP_RESERVED      (BIT(3) | BIT(2) | BIT(1))
-#define USBPD_REG_MASK_CC_SELECT_RP_DEF           (BIT(3) | BIT(2))
-#define USBPD_REG_MASK_CC_SELECT_RP_1A5           BIT(3)
-#define USBPD_REG_MASK_CC_SELECT_RP_3A0           BIT(2)
-#define USBPD_REG_MASK_CC1_CC2_SELECTION          BIT(0)
-#define IT83XX_USBPD_CCCSR(p)       REG8(IT83XX_USBPD_BASE(p)+0x05)
-#define USBPD_REG_MASK_CC2_DISCONNECT             BIT(7)
+#define USBPD_REG_MASK_AUTO_FRS_DISABLE BIT(6)
+#define IT83XX_USBPD_PDCSR1(p) REG8(IT83XX_USBPD_BASE(p) + 0x03)
+#define USBPD_REG_MASK_CABLE_RESET_RX_ENABLE BIT(6)
+#define USBPD_REG_MASK_HARD_RESET_RX_ENABLE BIT(5)
+#define USBPD_REG_MASK_SOPPP_RX_ENABLE BIT(2)
+#define USBPD_REG_MASK_SOPP_RX_ENABLE BIT(1)
+#define USBPD_REG_MASK_SOP_RX_ENABLE BIT(0)
+#define IT83XX_USBPD_CCGCR(p) REG8(IT83XX_USBPD_BASE(p) + 0x04)
+#define USBPD_REG_MASK_DISABLE_CC BIT(7)
+#define USBPD_REG_MASK_DISABLE_CC_VOL_DETECTOR BIT(6)
+#define USBPD_REG_MASK_CC_SELECT_RP_RESERVED (BIT(3) | BIT(2) | BIT(1))
+#define USBPD_REG_MASK_CC_SELECT_RP_DEF (BIT(3) | BIT(2))
+#define USBPD_REG_MASK_CC_SELECT_RP_1A5 BIT(3)
+#ifdef IT8XXX2_USBPD_RP_3A0_VALUE_IS_ZERO
+#define USBPD_REG_MASK_CC_SELECT_RP_3A0 0
+#else
+#define USBPD_REG_MASK_CC_SELECT_RP_3A0 BIT(2)
+#endif
+#define USBPD_REG_MASK_CC1_CC2_SELECTION BIT(0)
+#define IT83XX_USBPD_CCCSR(p) REG8(IT83XX_USBPD_BASE(p) + 0x05)
+#define USBPD_REG_MASK_CC2_DISCONNECT BIT(7)
 #define USBPD_REG_MASK_CC2_DISCONNECT_5_1K_TO_GND BIT(6)
-#define USBPD_REG_MASK_CC1_DISCONNECT             BIT(3)
+#define USBPD_REG_MASK_CC1_DISCONNECT BIT(3)
 #define USBPD_REG_MASK_CC1_DISCONNECT_5_1K_TO_GND BIT(2)
 #ifdef IT83XX_USBPD_CC1_CC2_RESISTANCE_SEPARATE
-#define USBPD_REG_MASK_CC1_CC2_RP_RD_SELECT       (BIT(1) | BIT(5))
+#define USBPD_REG_MASK_CC1_CC2_RP_RD_SELECT (BIT(1) | BIT(5))
 #else
-#define USBPD_REG_MASK_CC1_CC2_RP_RD_SELECT       BIT(1)
+#define USBPD_REG_MASK_CC1_CC2_RP_RD_SELECT BIT(1)
 #endif
-#define IT83XX_USBPD_CCPSR(p)       REG8(IT83XX_USBPD_BASE(p)+0x06)
-#define USBPD_REG_MASK_DISCONNECT_5_1K_CC2_DB     BIT(6)
-#define USBPD_REG_MASK_DISCONNECT_POWER_CC2       BIT(5)
-#define USBPD_REG_MASK_DISCONNECT_5_1K_CC1_DB     BIT(2)
-#define USBPD_REG_MASK_DISCONNECT_POWER_CC1       BIT(1)
-#define IT83XX_USBPD_SRCVCRR(p)     REG8(IT83XX_USBPD_BASE(p)+0x08)
-#define USBPD_REG_MASK_SRC_COMPARE_CC2_VOLT_H     BIT(5)
-#define USBPD_REG_MASK_SRC_COMPARE_CC2_VOLT_L     BIT(4)
-#define USBPD_REG_MASK_SRC_COMPARE_CC1_VOLT_H     BIT(1)
-#define USBPD_REG_MASK_SRC_COMPARE_CC1_VOLT_L     BIT(0)
-#define IT83XX_USBPD_SNKVCRR(p)     REG8(IT83XX_USBPD_BASE(p)+0x09)
-#define USBPD_REG_MASK_SNK_COMPARE_CC2_VOLT_H     BIT(6)
-#define USBPD_REG_MASK_SNK_COMPARE_CC2_VOLT_M     BIT(5)
-#define USBPD_REG_MASK_SNK_COMPARE_CC2_VOLT_L     BIT(4)
-#define USBPD_REG_MASK_SNK_COMPARE_CC1_VOLT_H     BIT(2)
-#define USBPD_REG_MASK_SNK_COMPARE_CC1_VOLT_M     BIT(1)
-#define USBPD_REG_MASK_SNK_COMPARE_CC1_VOLT_L     BIT(0)
-#define IT83XX_USBPD_PDFSCR(p)      REG8(IT83XX_USBPD_BASE(p)+0x0C)
-#define USBPD_REG_FAST_SWAP_REQUEST_ENABLE        BIT(1)
-#define USBPD_REG_FAST_SWAP_DETECT_ENABLE         BIT(0)
-#define IT83XX_USBPD_IFS(p)         REG8(IT83XX_USBPD_BASE(p)+0x12)
-#define USBPD_REG_FAST_SWAP_DETECT_STAT           BIT(4)
-#define IT83XX_USBPD_MIFS(p)        REG8(IT83XX_USBPD_BASE(p)+0x13)
-#define USBPD_REG_MASK_FAST_SWAP_ISR              BIT(7)
-#define USBPD_REG_MASK_FAST_SWAP_DETECT_ISR       BIT(4)
-#define IT83XX_USBPD_ISR(p)         REG8(IT83XX_USBPD_BASE(p)+0x14)
-#define USBPD_REG_MASK_CABLE_RESET_DETECT         BIT(6)
-#define USBPD_REG_MASK_HARD_RESET_DETECT          BIT(5)
-#define USBPD_REG_MASK_MSG_RX_DONE                BIT(4)
-#define USBPD_REG_MASK_TX_ERROR_STAT              BIT(3)
-#define USBPD_REG_MASK_CABLE_RESET_TX_DONE        BIT(2)
-#define USBPD_REG_MASK_HARD_RESET_TX_DONE         BIT(1)
-#define USBPD_REG_MASK_MSG_TX_DONE                BIT(0)
-#define IT83XX_USBPD_IMR(p)         REG8(IT83XX_USBPD_BASE(p)+0x15)
-#define IT83XX_USBPD_MTCR(p)        REG8(IT83XX_USBPD_BASE(p)+0x18)
-#define USBPD_REG_MASK_TX_DISCARD_STAT            BIT(7)
-#define USBPD_REG_MASK_TX_NO_RESPONSE_STAT        BIT(6)
-#define USBPD_REG_MASK_TX_NOT_EN_STAT             BIT(5)
-#define USBPD_REG_MASK_CABLE_RESET                BIT(3)
-#define USBPD_REG_MASK_SEND_HW_RESET              BIT(2)
-#define USBPD_REG_MASK_SEND_BIST_MODE_2           BIT(1)
-#define USBPD_REG_MASK_TX_START                   BIT(0)
-#define IT83XX_USBPD_MTSR0(p)       REG8(IT83XX_USBPD_BASE(p)+0x19)
-#define IT83XX_USBPD_MHSR0(p)       REG8(IT83XX_USBPD_BASE(p)+0x1A)
-#define USBPD_REG_MASK_SOP_PORT_DATA_ROLE         BIT(5)
-#define IT83XX_USBPD_MHSR1(p)       REG8(IT83XX_USBPD_BASE(p)+0x1B)
-#define USBPD_REG_MASK_SOP_PORT_POWER_ROLE        BIT(0)
-#define IT83XX_USBPD_TDO(p)         REG32(IT83XX_USBPD_BASE(p)+0x22)
-#define IT83XX_USBPD_RMH(p)         REG16(IT83XX_USBPD_BASE(p)+0x42)
-#define IT83XX_USBPD_RDO(p)         REG32(IT83XX_USBPD_BASE(p)+0x44)
-#define IT83XX_USBPD_BMCDR0(p)      REG8(IT83XX_USBPD_BASE(p)+0x61)
-#define USBPD_REG_MASK_BMC_RX_THRESHOLD_SRC       BIT(5)
-#define USBPD_REG_MASK_BMC_RX_THRESHOLD_SNK       BIT(1)
-#define IT83XX_USBPD_TCDCR(p)       REG8(IT83XX_USBPD_BASE(p)+0x67)
-#define USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT     BIT(7)
-#define USBPD_REG_PLUG_OUT_SELECT                 BIT(6)
-#define USBPD_REG_PD3_0_SNK_TX_OK_DISABLE         BIT(5)
-#define USBPD_REG_PD3_0_SNK_TX_NG_DISABLE         BIT(3)
-#define USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE      BIT(1)
-#define USBPD_REG_PLUG_IN_OUT_DETECT_STAT         BIT(0)
-#define IT83XX_USBPD_CCPSR0(p)      REG8(IT83XX_USBPD_BASE(p)+0x70)
+#define IT83XX_USBPD_CCPSR(p) REG8(IT83XX_USBPD_BASE(p) + 0x06)
+#define USBPD_REG_MASK_DISCONNECT_5_1K_CC2_DB BIT(6)
+#define USBPD_REG_MASK_DISCONNECT_POWER_CC2 BIT(5)
+#define USBPD_REG_MASK_DISCONNECT_5_1K_CC1_DB BIT(2)
+#define USBPD_REG_MASK_DISCONNECT_POWER_CC1 BIT(1)
+#define IT83XX_USBPD_SRCVCRR(p) REG8(IT83XX_USBPD_BASE(p) + 0x08)
+#define USBPD_REG_MASK_SRC_COMPARE_CC2_VOLT_H BIT(5)
+#define USBPD_REG_MASK_SRC_COMPARE_CC2_VOLT_L BIT(4)
+#define USBPD_REG_MASK_SRC_COMPARE_CC1_VOLT_H BIT(1)
+#define USBPD_REG_MASK_SRC_COMPARE_CC1_VOLT_L BIT(0)
+#define IT83XX_USBPD_SNKVCRR(p) REG8(IT83XX_USBPD_BASE(p) + 0x09)
+#define USBPD_REG_MASK_SNK_COMPARE_CC2_VOLT_H BIT(6)
+#define USBPD_REG_MASK_SNK_COMPARE_CC2_VOLT_M BIT(5)
+#define USBPD_REG_MASK_SNK_COMPARE_CC2_VOLT_L BIT(4)
+#define USBPD_REG_MASK_SNK_COMPARE_CC1_VOLT_H BIT(2)
+#define USBPD_REG_MASK_SNK_COMPARE_CC1_VOLT_M BIT(1)
+#define USBPD_REG_MASK_SNK_COMPARE_CC1_VOLT_L BIT(0)
+#define IT83XX_USBPD_PDFSCR(p) REG8(IT83XX_USBPD_BASE(p) + 0x0C)
+#define USBPD_REG_FAST_SWAP_REQUEST_ENABLE BIT(1)
+#define USBPD_REG_FAST_SWAP_DETECT_ENABLE BIT(0)
+#define IT83XX_USBPD_IFS(p) REG8(IT83XX_USBPD_BASE(p) + 0x12)
+#define USBPD_REG_FAST_SWAP_DETECT_STAT BIT(4)
+#define IT83XX_USBPD_MIFS(p) REG8(IT83XX_USBPD_BASE(p) + 0x13)
+#define USBPD_REG_MASK_FAST_SWAP_ISR BIT(7)
+#define USBPD_REG_MASK_FAST_SWAP_DETECT_ISR BIT(4)
+#define IT83XX_USBPD_ISR(p) REG8(IT83XX_USBPD_BASE(p) + 0x14)
+#define USBPD_REG_MASK_CABLE_RESET_DETECT BIT(6)
+#define USBPD_REG_MASK_HARD_RESET_DETECT BIT(5)
+#define USBPD_REG_MASK_MSG_RX_DONE BIT(4)
+#define USBPD_REG_MASK_TX_ERROR_STAT BIT(3)
+#define USBPD_REG_MASK_CABLE_RESET_TX_DONE BIT(2)
+#define USBPD_REG_MASK_HARD_RESET_TX_DONE BIT(1)
+#define USBPD_REG_MASK_MSG_TX_DONE BIT(0)
+#define IT83XX_USBPD_IMR(p) REG8(IT83XX_USBPD_BASE(p) + 0x15)
+#define IT83XX_USBPD_MTCR(p) REG8(IT83XX_USBPD_BASE(p) + 0x18)
+#define USBPD_REG_MASK_TX_DISCARD_STAT BIT(7)
+#define USBPD_REG_MASK_TX_NO_RESPONSE_STAT BIT(6)
+#define USBPD_REG_MASK_TX_NOT_EN_STAT BIT(5)
+#define USBPD_REG_MASK_CABLE_RESET BIT(3)
+#define USBPD_REG_MASK_SEND_HW_RESET BIT(2)
+#define USBPD_REG_MASK_SEND_BIST_MODE_2 BIT(1)
+#define USBPD_REG_MASK_TX_START BIT(0)
+#define IT83XX_USBPD_MTSR0(p) REG8(IT83XX_USBPD_BASE(p) + 0x19)
+#define IT83XX_USBPD_MHSR0(p) REG8(IT83XX_USBPD_BASE(p) + 0x1A)
+#define USBPD_REG_MASK_SOP_PORT_DATA_ROLE BIT(5)
+#define IT83XX_USBPD_MHSR1(p) REG8(IT83XX_USBPD_BASE(p) + 0x1B)
+#define USBPD_REG_MASK_SOP_PORT_POWER_ROLE BIT(0)
+#define IT83XX_USBPD_TDO(p) REG32(IT83XX_USBPD_BASE(p) + 0x22)
+#define IT83XX_USBPD_RMH(p) REG16(IT83XX_USBPD_BASE(p) + 0x42)
+#define IT83XX_USBPD_RDO(p) REG32(IT83XX_USBPD_BASE(p) + 0x44)
+#define IT83XX_USBPD_BMCDR0(p) REG8(IT83XX_USBPD_BASE(p) + 0x61)
+#define USBPD_REG_MASK_BMC_RX_THRESHOLD_SRC BIT(5)
+#define USBPD_REG_MASK_BMC_RX_THRESHOLD_SNK BIT(1)
+#define IT83XX_USBPD_TCDCR(p) REG8(IT83XX_USBPD_BASE(p) + 0x67)
+#define USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT BIT(7)
+#define USBPD_REG_PLUG_OUT_SELECT BIT(6)
+#define USBPD_REG_PD3_0_SNK_TX_OK_DISABLE BIT(5)
+#define USBPD_REG_PD3_0_SNK_TX_NG_DISABLE BIT(3)
+#define USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE BIT(1)
+#define USBPD_REG_PLUG_IN_OUT_DETECT_STAT BIT(0)
+#define IT83XX_USBPD_CCPSR0(p) REG8(IT83XX_USBPD_BASE(p) + 0x70)
+#define IT83XX_USBPD_CCPSR3_RISE(p) REG8(IT83XX_USBPD_BASE(p) + 0x73)
+#define IT83XX_USBPD_CCPSR4_FALL(p) REG8(IT83XX_USBPD_BASE(p) + 0x74)
 #endif /* !defined(CONFIG_USB_PD_TCPM_DRIVER_IT83XX) */
 
 /*
@@ -209,161 +220,170 @@
  * This setting will connect CC pin to internal PD module directly without
  * applying any GPIO/ALT configuration.
  */
-#define IT83XX_USBPD_CC_PIN_CONFIG  0x86
+#define IT83XX_USBPD_CC_PIN_CONFIG 0x86
 #define IT83XX_USBPD_CC_PIN_CONFIG2 0x06
 
+/*
+ * Before disabling cc 5v tolerant, we need to make sure cc voltage
+ * detector is enabled and Vconn is dropped below 3.3v (>500us) to avoid
+ * the potential risk of voltage fed back into Vcore.
+ */
+#define IT83XX_USBPD_T_VCONN_BELOW_3_3V 500 /* us */
+
 #ifndef CONFIG_USB_PD_TCPM_ITE_ON_CHIP
-#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT   0
+#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 0
 #endif
 
 #define TASK_EVENT_PHY_TX_DONE TASK_EVENT_CUSTOM_BIT(PD_EVENT_FIRST_FREE_BIT)
 
-#define SET_MASK(reg, bit_mask)      ((reg) |= (bit_mask))
-#define CLEAR_MASK(reg, bit_mask)    ((reg) &= (~(bit_mask)))
-#define IS_MASK_SET(reg, bit_mask)   (((reg) & (bit_mask)) != 0)
+#define SET_MASK(reg, bit_mask) ((reg) |= (bit_mask))
+#define CLEAR_MASK(reg, bit_mask) ((reg) &= (~(bit_mask)))
+#define IS_MASK_SET(reg, bit_mask) (((reg) & (bit_mask)) != 0)
 #define IS_MASK_CLEAR(reg, bit_mask) (((reg) & (bit_mask)) == 0)
 
 #if defined(CONFIG_USB_PD_TCPM_DRIVER_IT83XX)
 /* macros for set */
-#define USBPD_KICK_TX_START(port)            \
-	SET_MASK(IT83XX_USBPD_MTCR(port),    \
-		USBPD_REG_MASK_TX_START)
-#define USBPD_SEND_HARD_RESET(port)          \
-	SET_MASK(IT83XX_USBPD_MTSR0(port),   \
-		USBPD_REG_MASK_SEND_HW_RESET)
-#define USBPD_SW_RESET(port)                 \
-	SET_MASK(IT83XX_USBPD_GCR(port),     \
-		USBPD_REG_MASK_SW_RESET_BIT)
-#define USBPD_ENABLE_BMC_PHY(port)           \
-	SET_MASK(IT83XX_USBPD_GCR(port),     \
-		USBPD_REG_MASK_BMC_PHY)
-#define USBPD_DISABLE_BMC_PHY(port)          \
-	CLEAR_MASK(IT83XX_USBPD_GCR(port),   \
-		USBPD_REG_MASK_BMC_PHY)
-#define USBPD_START(port)                    \
-	CLEAR_MASK(IT83XX_USBPD_CCGCR(port), \
-		USBPD_REG_MASK_DISABLE_CC)
-#define USBPD_ENABLE_SEND_BIST_MODE_2(port)  \
-	SET_MASK(IT83XX_USBPD_MTSR0(port),   \
-		USBPD_REG_MASK_SEND_BIST_MODE_2)
+#define USBPD_KICK_TX_START(port) \
+	SET_MASK(IT83XX_USBPD_MTCR(port), USBPD_REG_MASK_TX_START)
+#define USBPD_SEND_HARD_RESET(port) \
+	SET_MASK(IT83XX_USBPD_MTSR0(port), USBPD_REG_MASK_SEND_HW_RESET)
+#define USBPD_SW_RESET(port) \
+	SET_MASK(IT83XX_USBPD_GCR(port), USBPD_REG_MASK_SW_RESET_BIT)
+#define USBPD_ENABLE_BMC_PHY(port) \
+	SET_MASK(IT83XX_USBPD_GCR(port), USBPD_REG_MASK_BMC_PHY)
+#define USBPD_DISABLE_BMC_PHY(port) \
+	CLEAR_MASK(IT83XX_USBPD_GCR(port), USBPD_REG_MASK_BMC_PHY)
+#define USBPD_START(port) \
+	CLEAR_MASK(IT83XX_USBPD_CCGCR(port), USBPD_REG_MASK_DISABLE_CC)
+#define USBPD_ENABLE_SEND_BIST_MODE_2(port) \
+	SET_MASK(IT83XX_USBPD_MTSR0(port), USBPD_REG_MASK_SEND_BIST_MODE_2)
 #define USBPD_DISABLE_SEND_BIST_MODE_2(port) \
-	CLEAR_MASK(IT83XX_USBPD_MTSR0(port), \
-		USBPD_REG_MASK_SEND_BIST_MODE_2)
-#define USBPD_CLEAR_FRS_DETECT_STATUS(port)  \
+	CLEAR_MASK(IT83XX_USBPD_MTSR0(port), USBPD_REG_MASK_SEND_BIST_MODE_2)
+#define USBPD_CLEAR_FRS_DETECT_STATUS(port) \
 	(IT83XX_USBPD_PD30IR(port) = USBPD_REG_FAST_SWAP_DETECT_STAT)
-#define USBPD_CC1_DISCONNECTED(p) \
+#define USBPD_CC1_DISCONNECTED(p)                                  \
 	((IT83XX_USBPD_CCCSR(p) | USBPD_REG_MASK_CC1_DISCONNECT) & \
-	~USBPD_REG_MASK_CC2_DISCONNECT)
-#define USBPD_CC2_DISCONNECTED(p) \
+	 ~USBPD_REG_MASK_CC2_DISCONNECT)
+#define USBPD_CC2_DISCONNECTED(p)                                  \
 	((IT83XX_USBPD_CCCSR(p) | USBPD_REG_MASK_CC2_DISCONNECT) & \
-	~USBPD_REG_MASK_CC1_DISCONNECT)
+	 ~USBPD_REG_MASK_CC1_DISCONNECT)
 
 /* macros for get */
-#define USBPD_GET_POWER_ROLE(port)                  \
-	(IT83XX_USBPD_PDMSR(port) & 1)
+#define USBPD_GET_POWER_ROLE(port) (IT83XX_USBPD_PDMSR(port) & 1)
 #define USBPD_GET_CC1_PULL_REGISTER_SELECTION(port) \
 	(IT83XX_USBPD_CCGCR(port) & BIT(1))
 #define USBPD_GET_CC2_PULL_REGISTER_SELECTION(port) \
 	(IT83XX_USBPD_BMCSR(port) & BIT(3))
-#define USBPD_GET_PULL_CC_SELECTION(port)           \
-	(IT83XX_USBPD_CCGCR(port) & 1)
+#define USBPD_GET_PULL_CC_SELECTION(port) (IT83XX_USBPD_CCGCR(port) & 1)
 
 /* macros for check */
-#define USBPD_IS_TX_ERR(port)       \
+#define USBPD_IS_TX_ERR(port) \
 	IS_MASK_SET(IT83XX_USBPD_MTCR(port), USBPD_REG_MASK_TX_ERR_STAT)
-#define USBPD_IS_TX_DISCARD(port)   \
+#define USBPD_IS_TX_DISCARD(port) \
 	IS_MASK_SET(IT83XX_USBPD_MTCR(port), USBPD_REG_MASK_TX_DISCARD_STAT)
 
 #elif defined(CONFIG_USB_PD_TCPM_DRIVER_IT8XXX2)
 /* macros for set */
-#define USBPD_SW_RESET(port)                 \
-	SET_MASK(IT83XX_USBPD_PDGCR(port),   \
-		USBPD_REG_MASK_SW_RESET_BIT)
-#define USBPD_ENABLE_BMC_PHY(port)           \
-	SET_MASK(IT83XX_USBPD_PDGCR(port),   \
-		USBPD_REG_MASK_BMC_PHY)
-#define USBPD_DISABLE_BMC_PHY(port)          \
-	CLEAR_MASK(IT83XX_USBPD_PDGCR(port), \
-		USBPD_REG_MASK_BMC_PHY)
-#define USBPD_START(port)                    \
-	CLEAR_MASK(IT83XX_USBPD_CCGCR(port), \
-		USBPD_REG_MASK_DISABLE_CC)
-#define USBPD_SEND_HARD_RESET(port)          \
-	SET_MASK(IT83XX_USBPD_MTCR(port),    \
-		USBPD_REG_MASK_SEND_HW_RESET)
-#define USBPD_SEND_CABLE_RESET(port)         \
-	SET_MASK(IT83XX_USBPD_MTCR(port),    \
-		USBPD_REG_MASK_CABLE_RESET)
-#define USBPD_ENABLE_SEND_BIST_MODE_2(port)  \
-	SET_MASK(IT83XX_USBPD_MTCR(port),    \
-		USBPD_REG_MASK_SEND_BIST_MODE_2)
+#define USBPD_SW_RESET(port) \
+	SET_MASK(IT83XX_USBPD_PDGCR(port), USBPD_REG_MASK_SW_RESET_BIT)
+#define USBPD_ENABLE_BMC_PHY(port) \
+	SET_MASK(IT83XX_USBPD_PDGCR(port), USBPD_REG_MASK_BMC_PHY)
+#define USBPD_DISABLE_BMC_PHY(port) \
+	CLEAR_MASK(IT83XX_USBPD_PDGCR(port), USBPD_REG_MASK_BMC_PHY)
+#define USBPD_START(port) \
+	CLEAR_MASK(IT83XX_USBPD_CCGCR(port), USBPD_REG_MASK_DISABLE_CC)
+#define USBPD_SEND_HARD_RESET(port) \
+	SET_MASK(IT83XX_USBPD_MTCR(port), USBPD_REG_MASK_SEND_HW_RESET)
+#define USBPD_SEND_CABLE_RESET(port) \
+	SET_MASK(IT83XX_USBPD_MTCR(port), USBPD_REG_MASK_CABLE_RESET)
+#define USBPD_ENABLE_SEND_BIST_MODE_2(port) \
+	SET_MASK(IT83XX_USBPD_MTCR(port), USBPD_REG_MASK_SEND_BIST_MODE_2)
 #define USBPD_DISABLE_SEND_BIST_MODE_2(port) \
-	CLEAR_MASK(IT83XX_USBPD_MTCR(port),  \
-		USBPD_REG_MASK_SEND_BIST_MODE_2)
-#define USBPD_KICK_TX_START(port)            \
-	SET_MASK(IT83XX_USBPD_MTCR(port),    \
-		USBPD_REG_MASK_TX_START)
-#define USBPD_CLEAR_FRS_DETECT_STATUS(port)  \
+	CLEAR_MASK(IT83XX_USBPD_MTCR(port), USBPD_REG_MASK_SEND_BIST_MODE_2)
+#define USBPD_KICK_TX_START(port) \
+	SET_MASK(IT83XX_USBPD_MTCR(port), USBPD_REG_MASK_TX_START)
+#define USBPD_CLEAR_FRS_DETECT_STATUS(port) \
 	(IT83XX_USBPD_IFS(port) = USBPD_REG_FAST_SWAP_DETECT_STAT)
-#define USBPD_CC1_DISCONNECTED(p) \
+#define USBPD_CC1_DISCONNECTED(p)                                  \
 	((IT83XX_USBPD_CCCSR(p) | USBPD_REG_MASK_CC1_DISCONNECT) & \
-	~USBPD_REG_MASK_CC2_DISCONNECT)
-#define USBPD_CC2_DISCONNECTED(p) \
+	 ~USBPD_REG_MASK_CC2_DISCONNECT)
+#define USBPD_CC2_DISCONNECTED(p)                                  \
 	((IT83XX_USBPD_CCCSR(p) | USBPD_REG_MASK_CC2_DISCONNECT) & \
-	~USBPD_REG_MASK_CC1_DISCONNECT)
+	 ~USBPD_REG_MASK_CC1_DISCONNECT)
 
 /* macros for get */
-#define USBPD_GET_POWER_ROLE(port)                  \
-	(IT83XX_USBPD_MHSR1(port) & BIT(0))
+#define USBPD_GET_POWER_ROLE(port) (IT83XX_USBPD_MHSR1(port) & BIT(0))
 #define USBPD_GET_CC1_PULL_REGISTER_SELECTION(port) \
 	(IT83XX_USBPD_CCCSR(port) & BIT(1))
 #define USBPD_GET_CC2_PULL_REGISTER_SELECTION(port) \
 	(IT83XX_USBPD_CCCSR(port) & BIT(1))
-#define USBPD_GET_PULL_CC_SELECTION(port)           \
-	(IT83XX_USBPD_CCGCR(port) & BIT(0))
-#define USBPD_GET_SNK_COMPARE_CC1_VOLT(port)        \
-	(IT83XX_USBPD_SNKVCRR(port) &               \
-		(USBPD_REG_MASK_SNK_COMPARE_CC1_VOLT_L |  \
-		USBPD_REG_MASK_SNK_COMPARE_CC1_VOLT_M |   \
-		USBPD_REG_MASK_SNK_COMPARE_CC1_VOLT_H))
-#define USBPD_GET_SNK_COMPARE_CC2_VOLT(port)        \
-	((IT83XX_USBPD_SNKVCRR(port) &              \
-		(USBPD_REG_MASK_SNK_COMPARE_CC2_VOLT_L |  \
-		USBPD_REG_MASK_SNK_COMPARE_CC2_VOLT_M |   \
-		USBPD_REG_MASK_SNK_COMPARE_CC2_VOLT_H)) >> 4)
-#define USBPD_GET_SRC_COMPARE_CC1_VOLT(port)        \
-	(IT83XX_USBPD_SRCVCRR(port) &               \
-		(USBPD_REG_MASK_SRC_COMPARE_CC1_VOLT_L |  \
-		USBPD_REG_MASK_SRC_COMPARE_CC1_VOLT_H))
-#define USBPD_GET_SRC_COMPARE_CC2_VOLT(port)        \
-	((IT83XX_USBPD_SRCVCRR(port) &              \
-		(USBPD_REG_MASK_SRC_COMPARE_CC2_VOLT_L |  \
-		USBPD_REG_MASK_SRC_COMPARE_CC2_VOLT_H)) >> 4)
+#define USBPD_GET_PULL_CC_SELECTION(port) (IT83XX_USBPD_CCGCR(port) & BIT(0))
+#define USBPD_GET_SNK_COMPARE_CC1_VOLT(port)                                   \
+	(IT83XX_USBPD_SNKVCRR(port) & (USBPD_REG_MASK_SNK_COMPARE_CC1_VOLT_L | \
+				       USBPD_REG_MASK_SNK_COMPARE_CC1_VOLT_M | \
+				       USBPD_REG_MASK_SNK_COMPARE_CC1_VOLT_H))
+#define USBPD_GET_SNK_COMPARE_CC2_VOLT(port)          \
+	((IT83XX_USBPD_SNKVCRR(port) &                \
+	  (USBPD_REG_MASK_SNK_COMPARE_CC2_VOLT_L |    \
+	   USBPD_REG_MASK_SNK_COMPARE_CC2_VOLT_M |    \
+	   USBPD_REG_MASK_SNK_COMPARE_CC2_VOLT_H)) >> \
+	 4)
+#define USBPD_GET_SRC_COMPARE_CC1_VOLT(port)                                   \
+	(IT83XX_USBPD_SRCVCRR(port) & (USBPD_REG_MASK_SRC_COMPARE_CC1_VOLT_L | \
+				       USBPD_REG_MASK_SRC_COMPARE_CC1_VOLT_H))
+#define USBPD_GET_SRC_COMPARE_CC2_VOLT(port)          \
+	((IT83XX_USBPD_SRCVCRR(port) &                \
+	  (USBPD_REG_MASK_SRC_COMPARE_CC2_VOLT_L |    \
+	   USBPD_REG_MASK_SRC_COMPARE_CC2_VOLT_H)) >> \
+	 4)
 
 /* macros for check */
-#define USBPD_IS_TX_ERR(port)           \
+#define USBPD_IS_TX_ERR(port) \
 	IS_MASK_SET(IT83XX_USBPD_ISR(port), USBPD_REG_MASK_TX_ERROR_STAT)
 #endif /* !defined(CONFIG_USB_PD_TCPM_DRIVER_IT83XX) */
 
 /* macros for PD ISR */
 #define USBPD_IS_HARD_RESET_DETECT(port) \
 	IS_MASK_SET(IT83XX_USBPD_ISR(port), USBPD_REG_MASK_HARD_RESET_DETECT)
-#define USBPD_IS_TX_DONE(port)           \
+#define USBPD_IS_HARD_CABLE_RESET_TX_DONE(port) \
+	IS_MASK_SET(IT83XX_USBPD_ISR(port),     \
+		    USBPD_REG_MASK_HARD_CABLE_RESET_TX_DONE)
+#define USBPD_IS_TX_DONE(port) \
 	IS_MASK_SET(IT83XX_USBPD_ISR(port), USBPD_REG_MASK_MSG_TX_DONE)
-#define USBPD_IS_RX_DONE(port)           \
+#define USBPD_IS_RX_DONE(port) \
 	IS_MASK_SET(IT83XX_USBPD_ISR(port), USBPD_REG_MASK_MSG_RX_DONE)
-#define USBPD_IS_PLUG_IN_OUT_DETECT(port)\
+#define USBPD_IS_PLUG_IN_OUT_DETECT(port) \
 	IS_MASK_SET(IT83XX_USBPD_TCDCR(port), USBPD_REG_PLUG_IN_OUT_DETECT_STAT)
-#define USBPD_IS_PLUG_IN(port)           \
+#define USBPD_IS_PLUG_IN(port) \
 	IS_MASK_CLEAR(IT83XX_USBPD_TCDCR(port), USBPD_REG_PLUG_OUT_SELECT)
 #if defined(CONFIG_USB_PD_TCPM_DRIVER_IT83XX)
-#define USBPD_IS_FAST_SWAP_DETECT(port)  \
+#define USBPD_IS_FAST_SWAP_DETECT(port) \
 	IS_MASK_SET(IT83XX_USBPD_PD30IR(port), USBPD_REG_FAST_SWAP_DETECT_STAT)
 #elif defined(CONFIG_USB_PD_TCPM_DRIVER_IT8XXX2)
-#define USBPD_IS_FAST_SWAP_DETECT(port)  \
+#define USBPD_IS_FAST_SWAP_DETECT(port) \
 	IS_MASK_SET(IT83XX_USBPD_IFS(port), USBPD_REG_FAST_SWAP_DETECT_STAT)
 #endif
 
+#if defined(CONFIG_USB_PD_TCPM_ITE_ON_CHIP) && defined(CONFIG_ZEPHYR)
+/* Use the Zephyr names here. When upstreaming we can update this */
+#include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
+
+#define IT83XX_GPIO_GPCRF4 GPCRF4
+#define IT83XX_GPIO_GPCRF5 GPCRF5
+#define IT83XX_GPIO_GPCRH1 GPCRH1
+#define IT83XX_GPIO_GPCRH2 GPCRH2
+#define IT83XX_GPIO_GPCRP0 IT8XXX2_GPIO_GPCRP0
+#define IT83XX_GPIO_GPCRP1 IT8XXX2_GPIO_GPCRP1
+#define IT83XX_IRQ_USBPD0 IT8XXX2_IRQ_USBPD0
+#define IT83XX_IRQ_USBPD1 IT8XXX2_IRQ_USBPD1
+#define IT83XX_IRQ_USBPD2 IT8XXX2_IRQ_USBPD2
+#define USB_VID_ITE 0x048d
+
+/* ITE chip supports PD features */
+#define IT83XX_INTC_FAST_SWAP_SUPPORT
+#define IT83XX_INTC_PLUG_IN_OUT_SUPPORT
+#endif
+
 enum usbpd_port {
 	USBPD_PORT_A,
 	USBPD_PORT_B,
@@ -372,14 +392,14 @@ enum usbpd_port {
 
 enum usbpd_ufp_volt_status {
 	USBPD_UFP_STATE_SNK_OPEN = 0,
-	USBPD_UFP_STATE_SNK_DEF  = 1,
-	USBPD_UFP_STATE_SNK_1_5  = 3,
-	USBPD_UFP_STATE_SNK_3_0  = 7,
+	USBPD_UFP_STATE_SNK_DEF = 1,
+	USBPD_UFP_STATE_SNK_1_5 = 3,
+	USBPD_UFP_STATE_SNK_3_0 = 7,
 };
 
 enum usbpd_dfp_volt_status {
-	USBPD_DFP_STATE_SRC_RA   = 0,
-	USBPD_DFP_STATE_SRC_RD   = 1,
+	USBPD_DFP_STATE_SRC_RA = 0,
+	USBPD_DFP_STATE_SRC_RD = 1,
 	USBPD_DFP_STATE_SRC_OPEN = 3,
 };
 
@@ -390,19 +410,34 @@ enum usbpd_power_role {
 	USBPD_POWER_ROLE_PROVIDER_CONSUMER,
 };
 
+enum tuning_unit {
+	IT83XX_TX_PRE_DRIVING_TIME_DEFAULT,
+	IT83XX_TX_PRE_DRIVING_TIME_1_UNIT,
+	IT83XX_TX_PRE_DRIVING_TIME_2_UNIT,
+	IT83XX_TX_PRE_DRIVING_TIME_3_UNIT,
+};
+
 struct usbpd_ctrl_t {
 	volatile uint8_t *cc1;
 	volatile uint8_t *cc2;
 	uint8_t irq;
 };
 
+/* Data structure for board to adjust pd port rising and falling time */
+struct cc_para_t {
+	enum tuning_unit rising_time;
+	enum tuning_unit falling_time;
+};
+
 extern const struct usbpd_ctrl_t usbpd_ctrl_regs[];
-extern const struct tcpm_drv it83xx_tcpm_drv;
+void it8xxx2_clear_tx_error_status(enum usbpd_port port);
+void it8xxx2_get_tx_error_status(enum usbpd_port port);
 void it83xx_Rd_5_1K_only_for_hibernate(int port);
-#ifdef CONFIG_USB_PD_TCPM_DRIVER_IT8XXX2
-void it83xx_clear_tx_error_status(enum usbpd_port port);
-void it83xx_get_tx_error_status(enum usbpd_port port);
-#endif
 void switch_plug_out_type(enum usbpd_port port);
+/*
+ * Board-level callback function to get cc tuning parameters
+ * NOTE: board must define CONFIG_IT83XX_TUNE_CC_PHY
+ */
+const struct cc_para_t *board_get_cc_tuning_parameter(enum usbpd_port port);
 
 #endif /* __CROS_EC_DRIVER_TCPM_IT83XX_H */
diff --git a/driver/tcpm/it8xxx2.c b/driver/tcpm/it8xxx2.c
index 1cfa184a11..2029659de0 100644
--- a/driver/tcpm/it8xxx2.c
+++ b/driver/tcpm/it8xxx2.c
@@ -1,52 +1,53 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* TCPM on ITE chip it8xxx2 with embedded TCPC */
 
+#include "builtin/assert.h"
 #include "common.h"
 #include "config.h"
 #include "console.h"
+#include "hooks.h"
 #include "it83xx_pd.h"
+#include "ite_pd_intc.h"
 #include "registers.h"
 #include "system.h"
 #include "task.h"
 #include "timer.h"
-#include "util.h"
+#include "usb_common.h"
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
-#include "hooks.h"
+#include "util.h"
 
 #ifdef CONFIG_USB_PD_TCPMV1
 #if defined(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE) || \
-	defined(CONFIG_USB_PD_VBUS_DETECT_TCPC) || \
-	defined(CONFIG_USB_PD_TCPC_LOW_POWER) || \
+	defined(CONFIG_USB_PD_VBUS_DETECT_TCPC) ||  \
+	defined(CONFIG_USB_PD_TCPC_LOW_POWER) ||    \
 	defined(CONFIG_USB_PD_DISCHARGE_TCPC)
-#error "Unsupported config options of IT83xx PD driver"
+#error "Unsupported config options of IT8xxx2 PD driver"
 #endif
 #endif
 
 #ifdef CONFIG_USB_PD_TCPMV2
 #if defined(CONFIG_USB_PD_VBUS_DETECT_TCPC) || \
 	defined(CONFIG_USB_PD_DISCHARGE_TCPC)
-#error "Unsupported config options of IT83xx PD driver"
+#error "Unsupported config options of IT8xxx2 PD driver"
 #endif
 #endif
 
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-/* Wait time for vconn power switch to turn off. */
-#ifndef PD_IT83XX_VCONN_TURN_OFF_DELAY_US
-#define PD_IT83XX_VCONN_TURN_OFF_DELAY_US 500
-#endif
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
-static uint8_t tx_error_status[IT83XX_USBPD_PHY_PORT_COUNT] = {0};
+bool rx_en[IT83XX_USBPD_PHY_PORT_COUNT];
+STATIC_IF(CONFIG_USB_PD_DECODE_SOP)
+bool sop_prime_en[IT83XX_USBPD_PHY_PORT_COUNT];
+static uint8_t tx_error_status[IT83XX_USBPD_PHY_PORT_COUNT] = { 0 };
 
 const struct usbpd_ctrl_t usbpd_ctrl_regs[] = {
-	{&IT83XX_GPIO_GPCRF4, &IT83XX_GPIO_GPCRF5, IT83XX_IRQ_USBPD0},
-	{&IT83XX_GPIO_GPCRH1, &IT83XX_GPIO_GPCRH2, IT83XX_IRQ_USBPD1},
-	{&IT83XX_GPIO_GPCRP0, &IT83XX_GPIO_GPCRP1, IT83XX_IRQ_USBPD2},
+	{ &IT83XX_GPIO_GPCRF4, &IT83XX_GPIO_GPCRF5, IT83XX_IRQ_USBPD0 },
+	{ &IT83XX_GPIO_GPCRH1, &IT83XX_GPIO_GPCRH2, IT83XX_IRQ_USBPD1 },
+	{ &IT83XX_GPIO_GPCRP0, &IT83XX_GPIO_GPCRP1, IT83XX_IRQ_USBPD2 },
 };
 BUILD_ASSERT(ARRAY_SIZE(usbpd_ctrl_regs) >= IT83XX_USBPD_PHY_PORT_COUNT);
 
@@ -58,8 +59,8 @@ BUILD_ASSERT(ARRAY_SIZE(usbpd_ctrl_regs) >= IT83XX_USBPD_PHY_PORT_COUNT);
 void it83xx_Rd_5_1K_only_for_hibernate(int port)
 {
 	uint8_t cc_config = (port == USBPD_PORT_C ?
-			     IT83XX_USBPD_CC_PIN_CONFIG2 :
-			     IT83XX_USBPD_CC_PIN_CONFIG);
+				     IT83XX_USBPD_CC_PIN_CONFIG2 :
+				     IT83XX_USBPD_CC_PIN_CONFIG);
 
 	/* This only apply to active PD port */
 	if (*usbpd_ctrl_regs[port].cc1 == cc_config &&
@@ -92,9 +93,8 @@ void it83xx_Rd_5_1K_only_for_hibernate(int port)
 	}
 }
 
-static enum tcpc_cc_voltage_status it83xx_get_cc(
-	enum usbpd_port port,
-	enum usbpd_cc_pin cc_pin)
+static enum tcpc_cc_voltage_status it8xxx2_get_cc(enum usbpd_port port,
+						  enum usbpd_cc_pin cc_pin)
 {
 	enum usbpd_ufp_volt_status ufp_volt;
 	enum usbpd_dfp_volt_status dfp_volt;
@@ -131,7 +131,7 @@ static enum tcpc_cc_voltage_status it83xx_get_cc(
 			cc_state = TYPEC_CC_VOLT_OPEN;
 			break;
 		}
-	/* Source */
+		/* Source */
 	} else {
 		if (cc_pin == USBPD_CC_PIN_1)
 			dfp_volt = USBPD_GET_SRC_COMPARE_CC1_VOLT(port);
@@ -157,7 +157,7 @@ static enum tcpc_cc_voltage_status it83xx_get_cc(
 	return cc_state;
 }
 
-static int it83xx_tcpm_get_message_raw(int port, uint32_t *buf, int *head)
+static int it8xxx2_tcpm_get_message_raw(int port, uint32_t *buf, int *head)
 {
 	int cnt = PD_HEADER_CNT(IT83XX_USBPD_RMH(port));
 
@@ -166,6 +166,17 @@ static int it83xx_tcpm_get_message_raw(int port, uint32_t *buf, int *head)
 
 	/* Store header */
 	*head = IT83XX_USBPD_RMH(port);
+
+	/*
+	 * BIT[6:4] SOP type of Rx message
+	 * 000b=SOP, 001b=SOP', 010b=SOP", 011b=Debug SOP', 100b=Debug SOP"
+	 * 101b=HRDRST, 110b=CBLRST
+	 * 000b~100b is aligned to enum tcpci_msg_type.
+	 *
+	 */
+	if (IS_ENABLED(CONFIG_USB_PD_DECODE_SOP))
+		*head |= PD_HEADER_SOP((IT83XX_USBPD_MTSR0(port) >> 4) & 0x7);
+
 	/* Check data message */
 	if (cnt)
 		memcpy(buf, (uint32_t *)&IT83XX_USBPD_RDO(port), cnt * 4);
@@ -173,12 +184,12 @@ static int it83xx_tcpm_get_message_raw(int port, uint32_t *buf, int *head)
 	return EC_SUCCESS;
 }
 
-void it83xx_clear_tx_error_status(enum usbpd_port port)
+void it8xxx2_clear_tx_error_status(enum usbpd_port port)
 {
 	tx_error_status[port] = 0;
 }
 
-void it83xx_get_tx_error_status(enum usbpd_port port)
+void it8xxx2_get_tx_error_status(enum usbpd_port port)
 {
 	tx_error_status[port] = IT83XX_USBPD_MTCR(port) &
 				(USBPD_REG_MASK_TX_NOT_EN_STAT |
@@ -186,15 +197,15 @@ void it83xx_get_tx_error_status(enum usbpd_port port)
 				 USBPD_REG_MASK_TX_NO_RESPONSE_STAT);
 }
 
-static enum tcpc_transmit_complete it83xx_tx_data(
-	enum usbpd_port port,
-	enum tcpm_transmit_type type,
-	uint16_t header,
-	const uint32_t *buf)
+static enum tcpc_transmit_complete it8xxx2_tx_data(enum usbpd_port port,
+						   enum tcpci_msg_type type,
+						   uint16_t header,
+						   const uint32_t *buf)
 {
 	int r;
 	uint32_t evt;
 	uint8_t length = PD_HEADER_CNT(header);
+	uint8_t retry_count = pd_get_retry_count(port, type);
 
 	/* Set message header */
 	IT83XX_USBPD_MHSR0(port) = (uint8_t)header;
@@ -204,8 +215,12 @@ static enum tcpc_transmit_complete it83xx_tx_data(
 	 * Bit[2:0] Tx message type
 	 * 000b=SOP, 001b=SOP', 010b=SOP", 011b=Debug SOP', 100b=Debug SOP''.
 	 */
-	IT83XX_USBPD_MTSR0(port) =
-		(IT83XX_USBPD_MTSR0(port) & ~0x7) | (type & 0x7);
+	IT83XX_USBPD_MTSR0(port) = (IT83XX_USBPD_MTSR0(port) & ~0x7) |
+				   (type & 0x7);
+
+	/* According PD version set HW auto retry count */
+	IT83XX_USBPD_PDCSR0(port) = (IT83XX_USBPD_PDCSR0(port) & ~0xC0) |
+				    (retry_count << 6);
 
 	/* Limited by PD_HEADER_CNT() */
 	ASSERT(length <= 0x7);
@@ -214,7 +229,7 @@ static enum tcpc_transmit_complete it83xx_tx_data(
 		/* Set data */
 		memcpy((uint32_t *)&IT83XX_USBPD_TDO(port), buf, length * 4);
 
-	for (r = 0; r <= CONFIG_PD_RETRY_COUNT; r++) {
+	for (r = 0; r <= retry_count; r++) {
 		/* Start Tx */
 		USBPD_KICK_TX_START(port);
 		evt = task_wait_event_mask(TASK_EVENT_PHY_TX_DONE,
@@ -230,7 +245,7 @@ static enum tcpc_transmit_complete it83xx_tx_data(
 		 */
 		if (tx_error_status[port] || (evt & TASK_EVENT_TIMER)) {
 			if (tx_error_status[port] &
-					USBPD_REG_MASK_TX_NOT_EN_STAT) {
+			    USBPD_REG_MASK_TX_NOT_EN_STAT) {
 				CPRINTS("p%d TxErr: Tx EN and resend", port);
 				tx_error_status[port] &=
 					~USBPD_REG_MASK_TX_NOT_EN_STAT;
@@ -238,13 +253,13 @@ static enum tcpc_transmit_complete it83xx_tx_data(
 					USBPD_REG_MASK_TX_MESSAGE_ENABLE;
 				continue;
 			} else if (tx_error_status[port] &
-					USBPD_REG_MASK_TX_DISCARD_STAT) {
+				   USBPD_REG_MASK_TX_DISCARD_STAT) {
 				CPRINTS("p%d TxErr: Discard and resend", port);
 				tx_error_status[port] &=
 					~USBPD_REG_MASK_TX_DISCARD_STAT;
 				continue;
 			} else if (tx_error_status[port] &
-					USBPD_REG_MASK_TX_NO_RESPONSE_STAT) {
+				   USBPD_REG_MASK_TX_NO_RESPONSE_STAT) {
 				/* HW had automatically resent message twice */
 				tx_error_status[port] &=
 					~USBPD_REG_MASK_TX_NO_RESPONSE_STAT;
@@ -257,13 +272,13 @@ static enum tcpc_transmit_complete it83xx_tx_data(
 			break;
 	}
 
-	if (r > CONFIG_PD_RETRY_COUNT)
+	if (r > retry_count)
 		return TCPC_TX_COMPLETE_DISCARDED;
 
 	return TCPC_TX_COMPLETE_SUCCESS;
 }
 
-static enum tcpc_transmit_complete it83xx_send_hw_reset(enum usbpd_port port)
+static enum tcpc_transmit_complete it8xxx2_send_hw_reset(enum usbpd_port port)
 {
 	/* Send hard reset */
 	USBPD_SEND_HARD_RESET(port);
@@ -276,7 +291,8 @@ static enum tcpc_transmit_complete it83xx_send_hw_reset(enum usbpd_port port)
 	return TCPC_TX_COMPLETE_SUCCESS;
 }
 
-static enum tcpc_transmit_complete it83xx_send_cable_reset(enum usbpd_port port)
+static enum tcpc_transmit_complete
+it8xxx2_send_cable_reset(enum usbpd_port port)
 {
 	/* Send cable reset */
 	USBPD_SEND_CABLE_RESET(port);
@@ -289,14 +305,14 @@ static enum tcpc_transmit_complete it83xx_send_cable_reset(enum usbpd_port port)
 	return TCPC_TX_COMPLETE_SUCCESS;
 }
 
-static void it83xx_send_bist_mode2_pattern(enum usbpd_port port)
+static void it8xxx2_send_bist_mode2_pattern(enum usbpd_port port)
 {
 	USBPD_ENABLE_SEND_BIST_MODE_2(port);
 	usleep(PD_T_BIST_TRANSMIT);
 	USBPD_DISABLE_SEND_BIST_MODE_2(port);
 }
 
-static void it83xx_enable_vconn(enum usbpd_port port, int enabled)
+static void it8xxx2_enable_vconn(enum usbpd_port port, int enabled)
 {
 	enum usbpd_cc_pin cc_pin;
 
@@ -309,14 +325,16 @@ static void it83xx_enable_vconn(enum usbpd_port port, int enabled)
 		/* Disable unused CC to become VCONN */
 		if (cc_pin == USBPD_CC_PIN_1) {
 			IT83XX_USBPD_CCCSR(port) = USBPD_CC2_DISCONNECTED(port);
-			IT83XX_USBPD_CCPSR(port) = (IT83XX_USBPD_CCPSR(port)
-				& ~USBPD_REG_MASK_DISCONNECT_POWER_CC2)
-				| USBPD_REG_MASK_DISCONNECT_POWER_CC1;
+			IT83XX_USBPD_CCPSR(port) =
+				(IT83XX_USBPD_CCPSR(port) &
+				 ~USBPD_REG_MASK_DISCONNECT_POWER_CC2) |
+				USBPD_REG_MASK_DISCONNECT_POWER_CC1;
 		} else {
 			IT83XX_USBPD_CCCSR(port) = USBPD_CC1_DISCONNECTED(port);
-			IT83XX_USBPD_CCPSR(port) = (IT83XX_USBPD_CCPSR(port)
-				& ~USBPD_REG_MASK_DISCONNECT_POWER_CC1)
-				| USBPD_REG_MASK_DISCONNECT_POWER_CC2;
+			IT83XX_USBPD_CCPSR(port) =
+				(IT83XX_USBPD_CCPSR(port) &
+				 ~USBPD_REG_MASK_DISCONNECT_POWER_CC1) |
+				USBPD_REG_MASK_DISCONNECT_POWER_CC2;
 		}
 	} else {
 		/* Connect cc analog module (ex.UP/RD/DET/TX/RX) */
@@ -325,19 +343,30 @@ static void it83xx_enable_vconn(enum usbpd_port port, int enabled)
 		/* Disable cc 5v tolerant */
 		IT83XX_USBPD_CCPSR(port) |=
 			(USBPD_REG_MASK_DISCONNECT_POWER_CC1 |
-			USBPD_REG_MASK_DISCONNECT_POWER_CC2);
+			 USBPD_REG_MASK_DISCONNECT_POWER_CC2);
 	}
 }
 
-static void it83xx_enable_cc(enum usbpd_port port, int enable)
+static void it8xxx2_enable_cc(enum usbpd_port port, int enable)
 {
-	if (enable)
+	if (enable) {
+#ifdef IT8XXX2_USBPD_CCGCR_BIT7_RESERVED
+		IT83XX_USBPD_CCCSR(port) &= ~(USBPD_REG_MASK_CC1_DISCONNECT |
+					      USBPD_REG_MASK_CC2_DISCONNECT);
+#else
 		IT83XX_USBPD_CCGCR(port) &= ~USBPD_REG_MASK_DISABLE_CC;
-	else
+#endif
+	} else {
+#ifdef IT8XXX2_USBPD_CCGCR_BIT7_RESERVED
+		IT83XX_USBPD_CCCSR(port) |= (USBPD_REG_MASK_CC1_DISCONNECT |
+					     USBPD_REG_MASK_CC2_DISCONNECT);
+#else
 		IT83XX_USBPD_CCGCR(port) |= USBPD_REG_MASK_DISABLE_CC;
+#endif
+	}
 }
 
-static void it83xx_set_power_role(enum usbpd_port port, int power_role)
+static void it8xxx2_set_power_role(enum usbpd_port port, int power_role)
 {
 	/* 0: PD_ROLE_SINK, 1: PD_ROLE_SOURCE */
 	if (power_role == PD_ROLE_SOURCE) {
@@ -376,7 +405,7 @@ static void it83xx_set_power_role(enum usbpd_port port, int power_role)
 	}
 }
 
-static void it83xx_set_data_role(enum usbpd_port port, int data_role)
+static void it8xxx2_set_data_role(enum usbpd_port port, int data_role)
 {
 	/* 0: PD_ROLE_UFP 1: PD_ROLE_DFP */
 	if (data_role == PD_ROLE_DFP)
@@ -387,8 +416,8 @@ static void it83xx_set_data_role(enum usbpd_port port, int data_role)
 		IT83XX_USBPD_MHSR0(port) &= ~USBPD_REG_MASK_SOP_PORT_DATA_ROLE;
 }
 
-static void it83xx_select_polarity(enum usbpd_port port,
-					enum usbpd_cc_pin cc_pin)
+static void it8xxx2_select_polarity(enum usbpd_port port,
+				    enum usbpd_cc_pin cc_pin)
 {
 	/* CC1/CC2 selection */
 	if (cc_pin == USBPD_CC_PIN_1)
@@ -397,16 +426,16 @@ static void it83xx_select_polarity(enum usbpd_port port,
 		IT83XX_USBPD_CCGCR(port) &= ~USBPD_REG_MASK_CC1_CC2_SELECTION;
 }
 
-static int it83xx_set_cc(enum usbpd_port port, int pull)
+static int it8xxx2_set_cc(enum usbpd_port port, int pull)
 {
 	int enable_cc = 1;
 
 	switch (pull) {
 	case TYPEC_CC_RD:
-		it83xx_set_power_role(port, PD_ROLE_SINK);
+		it8xxx2_set_power_role(port, PD_ROLE_SINK);
 		break;
 	case TYPEC_CC_RP:
-		it83xx_set_power_role(port, PD_ROLE_SOURCE);
+		it8xxx2_set_power_role(port, PD_ROLE_SOURCE);
 		break;
 	case TYPEC_CC_OPEN:
 		/* Power-down CC1 & CC2 to remove Rp/Rd */
@@ -416,25 +445,25 @@ static int it83xx_set_cc(enum usbpd_port port, int pull)
 		return EC_ERROR_UNIMPLEMENTED;
 	}
 
-	it83xx_enable_cc(port, enable_cc);
+	it8xxx2_enable_cc(port, enable_cc);
 	return EC_SUCCESS;
 }
 
-static int it83xx_tcpm_release(int port)
+static int it8xxx2_tcpm_release(int port)
 {
 	return EC_ERROR_UNIMPLEMENTED;
 }
 
-static int it83xx_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2)
+static int it8xxx2_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
+			       enum tcpc_cc_voltage_status *cc2)
 {
-	*cc2 = it83xx_get_cc(port, USBPD_CC_PIN_2);
-	*cc1 = it83xx_get_cc(port, USBPD_CC_PIN_1);
+	*cc2 = it8xxx2_get_cc(port, USBPD_CC_PIN_2);
+	*cc1 = it8xxx2_get_cc(port, USBPD_CC_PIN_1);
 
 	return EC_SUCCESS;
 }
 
-static int it83xx_tcpm_select_rp_value(int port, int rp_sel)
+static int it8xxx2_tcpm_select_rp_value(int port, int rp_sel)
 {
 	uint8_t rp;
 
@@ -462,26 +491,46 @@ static int it83xx_tcpm_select_rp_value(int port, int rp_sel)
 	return EC_SUCCESS;
 }
 
-static int it83xx_tcpm_set_cc(int port, int pull)
+static int it8xxx2_tcpm_set_cc(int port, int pull)
 {
-	return it83xx_set_cc(port, pull);
+	return it8xxx2_set_cc(port, pull);
 }
 
-static int it83xx_tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity)
+static int it8xxx2_tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity)
 {
 	enum usbpd_cc_pin cc_pin =
 		(polarity == POLARITY_CC1 || polarity == POLARITY_CC1_DTS) ?
-		USBPD_CC_PIN_1 : USBPD_CC_PIN_2;
+			USBPD_CC_PIN_1 :
+			USBPD_CC_PIN_2;
 
-	it83xx_select_polarity(port, cc_pin);
+	it8xxx2_select_polarity(port, cc_pin);
 
 	return EC_SUCCESS;
 }
 
-static int it83xx_tcpm_set_vconn(int port, int enable)
+__maybe_unused static int it8xxx2_tcpm_decode_sop_prime_enable(int port,
+							       bool enable)
+{
+	/* Save SOP'/SOP'' enable state */
+	sop_prime_en[port] = enable;
+
+	if (!rx_en[port])
+		return EC_SUCCESS;
+
+	if (enable)
+		IT83XX_USBPD_PDCSR1(port) |= (USBPD_REG_MASK_SOPP_RX_ENABLE |
+					      USBPD_REG_MASK_SOPPP_RX_ENABLE);
+	else
+		IT83XX_USBPD_PDCSR1(port) &= ~(USBPD_REG_MASK_SOPP_RX_ENABLE |
+					       USBPD_REG_MASK_SOPPP_RX_ENABLE);
+
+	return EC_SUCCESS;
+}
+
+static int it8xxx2_tcpm_set_vconn(int port, int enable)
 {
 	/*
-	 * IT83XX doesn't have integrated circuit to source CC lines for VCONN.
+	 * IT8xxx2 doesn't have integrated circuit to source CC lines for VCONN.
 	 * An external device like PPC or Power Switch has to source the VCONN.
 	 */
 	if (IS_ENABLED(CONFIG_USBC_VCONN)) {
@@ -490,39 +539,50 @@ static int it83xx_tcpm_set_vconn(int port, int enable)
 			 * Unused cc will become Vconn SRC, disable cc analog
 			 * module (ex.UP/RD/DET/Tx/Rx) and enable 5v tolerant.
 			 */
-			it83xx_enable_vconn(port, enable);
+			it8xxx2_enable_vconn(port, enable);
 			if (IS_ENABLED(CONFIG_USB_PD_DECODE_SOP))
-				/* Enable tcpc receive SOP' packet */
-				IT83XX_USBPD_PDCSR1(port) |=
-					 USBPD_REG_MASK_SOPP_RX_ENABLE;
-		}
-		/* Turn on/off vconn power switch. */
-		board_pd_vconn_ctrl(port,
-				    USBPD_GET_PULL_CC_SELECTION(port) ?
-				    USBPD_CC_PIN_2 : USBPD_CC_PIN_1, enable);
-		if (!enable) {
+				/* Enable tcpc receive SOP' and SOP'' packet */
+				it8xxx2_tcpm_decode_sop_prime_enable(port,
+								     true);
+			/* Turn on Vconn power switch. */
+			board_pd_vconn_ctrl(port,
+					    USBPD_GET_PULL_CC_SELECTION(port) ?
+						    USBPD_CC_PIN_2 :
+						    USBPD_CC_PIN_1,
+					    enable);
+		} else {
+			/*
+			 * If the pd port has previous connection and supplies
+			 * Vconn, then RO jumping to RW reset the system,
+			 * we never know which cc is the previous Vconn pin,
+			 * so we always turn both cc pins off when disable
+			 * Vconn power switch.
+			 */
+			board_pd_vconn_ctrl(port, USBPD_CC_PIN_1, enable);
+			board_pd_vconn_ctrl(port, USBPD_CC_PIN_2, enable);
 			if (IS_ENABLED(CONFIG_USB_PD_DECODE_SOP))
-				/* Disable tcpc receive SOP' packet */
-				IT83XX_USBPD_PDCSR1(port) &=
-					~USBPD_REG_MASK_SOPP_RX_ENABLE;
+				/* Disable tcpc receive SOP' and SOP'' packet */
+				it8xxx2_tcpm_decode_sop_prime_enable(port,
+								     false);
 			/*
-			 * We need to make sure cc voltage detector is enabled
-			 * after vconn is turned off to avoid the potential risk
-			 * of voltage fed back into Vcore.
+			 * Before disabling cc 5v tolerant, we need to make
+			 * sure cc voltage detector is enabled and Vconn is
+			 * dropped below 3.3v (>500us) to avoid the potential
+			 * risk of voltage fed back into Vcore.
 			 */
-			usleep(PD_IT83XX_VCONN_TURN_OFF_DELAY_US);
+			usleep(IT83XX_USBPD_T_VCONN_BELOW_3_3V);
 			/*
 			 * Since our cc are not Vconn SRC, enable cc analog
 			 * module (ex.UP/RD/DET/Tx/Rx) and disable 5v tolerant.
 			 */
-			it83xx_enable_vconn(port, enable);
+			it8xxx2_enable_vconn(port, enable);
 		}
 	}
 
 	return EC_SUCCESS;
 }
 
-static int it83xx_tcpm_set_msg_header(int port, int power_role, int data_role)
+static int it8xxx2_tcpm_set_msg_header(int port, int power_role, int data_role)
 {
 	/* 0: PD_ROLE_SINK, 1: PD_ROLE_SOURCE */
 	if (power_role == PD_ROLE_SOURCE)
@@ -532,77 +592,58 @@ static int it83xx_tcpm_set_msg_header(int port, int power_role, int data_role)
 		/* Bit0: sink */
 		IT83XX_USBPD_MHSR1(port) &= ~USBPD_REG_MASK_SOP_PORT_POWER_ROLE;
 
-	it83xx_set_data_role(port, data_role);
+	it8xxx2_set_data_role(port, data_role);
 
 	return EC_SUCCESS;
 }
 
-static int it83xx_tcpm_set_rx_enable(int port, int enable)
+static int it8xxx2_tcpm_set_rx_enable(int port, int enable)
 {
-	int i;
+	/* Save rx_on */
+	rx_en[port] = !!enable;
 
 	if (enable) {
 		IT83XX_USBPD_IMR(port) &= ~USBPD_REG_MASK_MSG_RX_DONE;
-		USBPD_ENABLE_BMC_PHY(port);
+		IT83XX_USBPD_PDCSR1(port) |=
+			(USBPD_REG_MASK_SOP_RX_ENABLE |
+			 USBPD_REG_MASK_HARD_RESET_RX_ENABLE);
+		if (IS_ENABLED(CONFIG_USB_PD_DECODE_SOP))
+			it8xxx2_tcpm_decode_sop_prime_enable(
+				port, sop_prime_en[port]);
 	} else {
 		IT83XX_USBPD_IMR(port) |= USBPD_REG_MASK_MSG_RX_DONE;
-		USBPD_DISABLE_BMC_PHY(port);
+		IT83XX_USBPD_PDCSR1(port) &=
+			~(USBPD_REG_MASK_SOP_RX_ENABLE |
+			  USBPD_REG_MASK_SOPP_RX_ENABLE |
+			  USBPD_REG_MASK_SOPPP_RX_ENABLE |
+			  USBPD_REG_MASK_HARD_RESET_RX_ENABLE);
 	}
 
-	/*
-	 * TCPMv1/TCPMv2 handle SLEEP_MASK_USB_PD and Rx_enable order for deep
-	 * sleep mode:
-	 * 1.Exit deep sleep mode, Rx enable -> deep sleep disable:
-	 * In deep sleep mode, ITE TCPC clock is turned off, so we should
-	 * disable deep sleep to leave the mode first then enable Rx, otherwise
-	 * we'll miss packet in the mode.
-	 * 2.Enter deep sleep mode, deep sleep enable -> Rx disable:
-	 * This is OK, but before set Rx disable, our Rx is disabled in deep
-	 * sleep mode period.
-	 *
-	 * So now, we set the SLEEP_MASK_USB_PD only by ITE driver. If any ITE
-	 * PD port Rx is enabled, then disable EC deep sleep.
-	 */
-	for (i = 0; i < CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT; ++i) {
-		if (IT83XX_USBPD_PDGCR(i) & USBPD_REG_MASK_BMC_PHY)
-			break;
-	}
-
-	if (i == board_get_usb_pd_port_count())
-		enable_sleep(SLEEP_MASK_USB_PD);
-	else
-		disable_sleep(SLEEP_MASK_USB_PD);
-
 	return EC_SUCCESS;
 }
 
-static int it83xx_tcpm_transmit(int port,
-			enum tcpm_transmit_type type,
-			uint16_t header,
-			const uint32_t *data)
+static int it8xxx2_tcpm_transmit(int port, enum tcpci_msg_type type,
+				 uint16_t header, const uint32_t *data)
 {
 	int status = TCPC_TX_COMPLETE_FAILED;
 
 	switch (type) {
-	case TCPC_TX_SOP:
-	case TCPC_TX_SOP_PRIME:
-	case TCPC_TX_SOP_PRIME_PRIME:
-	case TCPC_TX_SOP_DEBUG_PRIME:
-	case TCPC_TX_SOP_DEBUG_PRIME_PRIME:
-		status = it83xx_tx_data(port,
-					type,
-					header,
-					data);
+	case TCPCI_MSG_SOP:
+	case TCPCI_MSG_SOP_PRIME:
+	case TCPCI_MSG_SOP_PRIME_PRIME:
+	case TCPCI_MSG_SOP_DEBUG_PRIME:
+	case TCPCI_MSG_SOP_DEBUG_PRIME_PRIME:
+		status = it8xxx2_tx_data(port, type, header, data);
 		break;
-	case TCPC_TX_BIST_MODE_2:
-		it83xx_send_bist_mode2_pattern(port);
+	case TCPCI_MSG_TX_BIST_MODE_2:
+		it8xxx2_send_bist_mode2_pattern(port);
 		status = TCPC_TX_COMPLETE_SUCCESS;
 		break;
-	case TCPC_TX_HARD_RESET:
-		status = it83xx_send_hw_reset(port);
+	case TCPCI_MSG_TX_HARD_RESET:
+		status = it8xxx2_send_hw_reset(port);
 		break;
-	case TCPC_TX_CABLE_RESET:
-		status = it83xx_send_cable_reset(port);
+	case TCPCI_MSG_CABLE_RESET:
+		status = it8xxx2_send_cable_reset(port);
 		break;
 	default:
 		status = TCPC_TX_COMPLETE_FAILED;
@@ -613,12 +654,13 @@ static int it83xx_tcpm_transmit(int port,
 	return EC_SUCCESS;
 }
 
-static int it83xx_tcpm_get_chip_info(int port, int live,
-			struct ec_response_pd_chip_info_v1 *chip_info)
+static int
+it8xxx2_tcpm_get_chip_info(int port, int live,
+			   struct ec_response_pd_chip_info_v1 *chip_info)
 {
 	chip_info->vendor_id = USB_VID_ITE;
-	chip_info->product_id = ((IT83XX_GCTRL_CHIPID1 << 8) |
-				 IT83XX_GCTRL_CHIPID2);
+	chip_info->product_id =
+		((IT83XX_GCTRL_CHIPID1 << 8) | IT83XX_GCTRL_CHIPID2);
 	chip_info->device_id = IT83XX_GCTRL_CHIPVER & 0xf;
 	chip_info->fw_version_number = 0xEC;
 
@@ -626,20 +668,22 @@ static int it83xx_tcpm_get_chip_info(int port, int live,
 }
 
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-static int it83xx_tcpm_enter_low_power_mode(int port)
+static int it8xxx2_tcpm_enter_low_power_mode(int port)
 {
 	/*
-	 * ITE embedded TCPC do low power mode in idle_task(), when all ITE
-	 * ports are Rx disabled (means not in Attach.SRC/SNK state or
-	 * pd_disabled_mask be set). In deep sleep mode, the timer wakeup PD
-	 * task every 5ms, then PD task change the CC lines termination.
+	 * ITE embedded TCPC SLEEP_MASK_USB_PD flag is only controlled by
+	 * it8xxx2 driver in tc_update_pd_sleep_mask(), and do low power
+	 * mode in idle_task().
+	 * In deep sleep mode, ITE TCPC clock is turned off, and the
+	 * timer every 5ms to exit the mode and wakeup PD task to run
+	 * (ex. change the CC lines termination).
 	 */
 	return EC_SUCCESS;
 }
 #endif
 
 #ifdef CONFIG_USB_PD_FRS_TCPC
-static int it83xx_tcpm_set_frs_enable(int port, int enable)
+static int it8xxx2_tcpm_set_frs_enable(int port, int enable)
 {
 	uint8_t mask = (USBPD_REG_FAST_SWAP_REQUEST_ENABLE |
 			USBPD_REG_FAST_SWAP_DETECT_ENABLE);
@@ -653,11 +697,13 @@ static int it83xx_tcpm_set_frs_enable(int port, int enable)
 		/* W/C status */
 		IT83XX_USBPD_IFS(port) = 0x33;
 		/* Enable FRS detection (cc to GND) interrupt */
-		IT83XX_USBPD_MIFS(port) &= ~(USBPD_REG_MASK_FAST_SWAP_ISR |
-					USBPD_REG_MASK_FAST_SWAP_DETECT_ISR);
+		IT83XX_USBPD_MIFS(port) &=
+			~(USBPD_REG_MASK_FAST_SWAP_ISR |
+			  USBPD_REG_MASK_FAST_SWAP_DETECT_ISR);
 		/* Enable FRS detection (cc to GND) */
-		IT83XX_USBPD_PDFSCR(port)  = (IT83XX_USBPD_PDFSCR(port) & ~mask)
-					| USBPD_REG_FAST_SWAP_DETECT_ENABLE;
+		IT83XX_USBPD_PDFSCR(port) =
+			(IT83XX_USBPD_PDFSCR(port) & ~mask) |
+			USBPD_REG_FAST_SWAP_DETECT_ENABLE;
 		/*
 		 * TODO(b/160210457): Enable HW auto trigger
 		 * GPH3(port0)/GPH4(port1) output H/L after we detect FRS cc
@@ -665,8 +711,9 @@ static int it83xx_tcpm_set_frs_enable(int port, int enable)
 		 */
 	} else {
 		/* Disable FRS detection (cc to GND) interrupt */
-		IT83XX_USBPD_MIFS(port) |= (USBPD_REG_MASK_FAST_SWAP_ISR |
-					USBPD_REG_MASK_FAST_SWAP_DETECT_ISR);
+		IT83XX_USBPD_MIFS(port) |=
+			(USBPD_REG_MASK_FAST_SWAP_ISR |
+			 USBPD_REG_MASK_FAST_SWAP_DETECT_ISR);
 		/* Disable FRS detection and requestion */
 		IT83XX_USBPD_PDFSCR(port) &= ~mask;
 		/*
@@ -680,26 +727,28 @@ static int it83xx_tcpm_set_frs_enable(int port, int enable)
 }
 #endif
 
-static void it83xx_tcpm_switch_plug_out_type(int port)
+static void it8xxx2_tcpm_switch_plug_out_type(int port)
 {
 	enum tcpc_cc_voltage_status cc1, cc2;
 
 	/* Check what do we and partner cc assert */
-	it83xx_tcpm_get_cc(port, &cc1, &cc2);
+	it8xxx2_tcpm_get_cc(port, &cc1, &cc2);
 
 	if ((cc1 == TYPEC_CC_VOLT_RD && cc2 == TYPEC_CC_VOLT_RD) ||
 	    (cc1 == TYPEC_CC_VOLT_RA && cc2 == TYPEC_CC_VOLT_RA))
 		/* We're source, switch to detect audio/debug plug out. */
-		IT83XX_USBPD_TCDCR(port) = (IT83XX_USBPD_TCDCR(port) &
-				~USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE) |
-				USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT |
-				USBPD_REG_PLUG_OUT_SELECT;
+		IT83XX_USBPD_TCDCR(port) =
+			(IT83XX_USBPD_TCDCR(port) &
+			 ~USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE) |
+			USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT |
+			USBPD_REG_PLUG_OUT_SELECT;
 	else if (cc1 == TYPEC_CC_VOLT_RD || cc2 == TYPEC_CC_VOLT_RD)
 		/* We're source, switch to detect sink plug out. */
-		IT83XX_USBPD_TCDCR(port) = (IT83XX_USBPD_TCDCR(port) &
-				~USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE &
-				~USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT) |
-				USBPD_REG_PLUG_OUT_SELECT;
+		IT83XX_USBPD_TCDCR(port) =
+			(IT83XX_USBPD_TCDCR(port) &
+			 ~USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE &
+			 ~USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT) |
+			USBPD_REG_PLUG_OUT_SELECT;
 	else if (cc1 >= TYPEC_CC_VOLT_RP_DEF || cc2 >= TYPEC_CC_VOLT_RP_DEF)
 		/*
 		 * We're sink, disable detect interrupt, so messages on cc line
@@ -716,24 +765,44 @@ static void it83xx_tcpm_switch_plug_out_type(int port)
 
 void switch_plug_out_type(enum usbpd_port port)
 {
-	it83xx_tcpm_switch_plug_out_type(port);
+	it8xxx2_tcpm_switch_plug_out_type(port);
 }
 
-static void it83xx_init(enum usbpd_port port, int role)
+static void it8xxx2_init(enum usbpd_port port, int role)
 {
 	uint8_t cc_config = (port == USBPD_PORT_C ?
-			     IT83XX_USBPD_CC_PIN_CONFIG2 :
-			     IT83XX_USBPD_CC_PIN_CONFIG);
+				     IT83XX_USBPD_CC_PIN_CONFIG2 :
+				     IT83XX_USBPD_CC_PIN_CONFIG);
+
+	if (IS_ENABLED(CONFIG_IT83XX_TUNE_CC_PHY)) {
+		/* Tune cc Tx pre-driving time */
+		const struct cc_para_t *ptr =
+			board_get_cc_tuning_parameter(port);
 
+		IT83XX_USBPD_CCPSR3_RISE(port) = ptr->rising_time;
+		IT83XX_USBPD_CCPSR4_FALL(port) = ptr->falling_time;
+	}
 	/* Reset and disable HW auto generate message header */
 	IT83XX_USBPD_PDMSR(port) &= ~USBPD_REG_MASK_DISABLE_AUTO_GEN_TX_HEADER;
 	USBPD_SW_RESET(port);
-	/* According PD version set HW auto retry count */
-	IT83XX_USBPD_PDCSR0(port) = (IT83XX_USBPD_PDCSR0(port) & ~0xC0) |
-					(CONFIG_PD_RETRY_COUNT << 6);
-	/* Enable rx decode SOP type packet and hard reset signal */
-	IT83XX_USBPD_PDCSR1(port) = (USBPD_REG_MASK_HARD_RESET_RX_ENABLE |
-				     USBPD_REG_MASK_SOP_RX_ENABLE);
+	/* Disable Rx decode */
+	it8xxx2_tcpm_set_rx_enable(port, 0);
+	if (IS_ENABLED(CONFIG_USB_PD_TCPMV1)) {
+		uint8_t flags = 0;
+		/*
+		 * If explicit contract is set in bbram when EC boot up, then
+		 * TCPMv1 set soft reset as first state instead of
+		 * unattached.SNK, so we need to enable BMC PHY for tx module.
+		 *
+		 * NOTE: If the platform is without battery and connects to
+		 * adapter, then cold reset EC, our Rd is always asserted on cc,
+		 * so adapter keeps providing 5v and data in BBRAM are still
+		 * alive.
+		 */
+		if ((pd_get_saved_port_flags(port, &flags) == EC_SUCCESS) &&
+		    (flags & PD_BBRMFLG_EXPLICIT_CONTRACT))
+			USBPD_ENABLE_BMC_PHY(port);
+	}
 	/* Disable all interrupts */
 	IT83XX_USBPD_IMR(port) = 0xff;
 	/* W/C status */
@@ -741,15 +810,15 @@ static void it83xx_init(enum usbpd_port port, int role)
 	/* Enable cc voltage detector */
 	IT83XX_USBPD_CCGCR(port) &= ~USBPD_REG_MASK_DISABLE_CC_VOL_DETECTOR;
 	/* Select Rp value USB-DEFAULT (Rd value default connect with 5.1k) */
-	it83xx_tcpm_select_rp_value(port, TYPEC_RP_USB);
+	it8xxx2_tcpm_select_rp_value(port, TYPEC_RP_USB);
 	/* Which cc pin connect in attached state. Default to cc1  */
-	it83xx_select_polarity(port, USBPD_CC_PIN_1);
+	it8xxx2_select_polarity(port, USBPD_CC_PIN_1);
 	/* Change data role as the same power role */
-	it83xx_set_data_role(port, role);
+	it8xxx2_set_data_role(port, role);
 	/* Set default power role and assert Rp/Rd */
-	it83xx_set_power_role(port, role);
+	it8xxx2_set_power_role(port, role);
 	/* Disable vconn: connect cc analog module, disable cc 5v tolerant */
-	it83xx_enable_vconn(port, 0);
+	it8xxx2_tcpm_set_vconn(port, 0);
 	/* Enable tx done and hard reset detect interrupt */
 	IT83XX_USBPD_IMR(port) &= ~(USBPD_REG_MASK_MSG_TX_DONE |
 				    USBPD_REG_MASK_HARD_RESET_DETECT);
@@ -763,12 +832,17 @@ static void it83xx_init(enum usbpd_port port, int role)
 	IT83XX_USBPD_TCDCR(port) = (IT83XX_USBPD_TCDCR(port) &
 				    ~(USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE |
 				      USBPD_REG_PLUG_OUT_SELECT)) |
-				    USBPD_REG_PLUG_IN_OUT_DETECT_STAT;
+				   USBPD_REG_PLUG_IN_OUT_DETECT_STAT;
 #endif
 	/* Set cc1/cc2 pins alternate mode */
 	*usbpd_ctrl_regs[port].cc1 = cc_config;
 	*usbpd_ctrl_regs[port].cc2 = cc_config;
 	task_clear_pending_irq(usbpd_ctrl_regs[port].irq);
+#ifdef CONFIG_ZEPHYR
+	irq_connect_dynamic(usbpd_ctrl_regs[port].irq, 0,
+			    (void (*)(const void *))chip_pd_irq, (void *)port,
+			    0);
+#endif
 	task_enable_irq(usbpd_ctrl_regs[port].irq);
 	USBPD_START(port);
 	/*
@@ -780,19 +854,67 @@ static void it83xx_init(enum usbpd_port port, int role)
 				     USBPD_REG_MASK_DISCONNECT_5_1K_CC1_DB);
 }
 
-static int it83xx_tcpm_init(int port)
+static int it8xxx2_tcpm_init(int port)
 {
 	/* Initialize physical layer */
-	it83xx_init(port, PD_ROLE_DEFAULT(port));
+	it8xxx2_init(port, PD_ROLE_DEFAULT(port));
 
 	return EC_SUCCESS;
 }
 
-#ifdef CONFIG_USB_PD_TCPMV2
-static void it83xx_tcpm_hook_connect(void)
+__override void tc_update_pd_sleep_mask(int port)
+{
+	int i;
+	bool prevent_deep_sleep = false;
+
+	/*
+	 * Check ITE embedded pd ports to set SLEEP_MASK_USB_PD:
+	 * In tc_attached_[src, snk]_entry states, calling HOOK_CONNECT
+	 * to enable BMC PHY, and if one of ITE pd ports BMC PHY is enable,
+	 * then EC deep doze mode will be disabled.
+	 * Otherwise, EC deep doze mode will be enabled.
+	 */
+	for (i = 0; i < CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT; ++i) {
+		if (IT83XX_USBPD_PDGCR(i) & USBPD_REG_MASK_BMC_PHY) {
+			prevent_deep_sleep = true;
+			break;
+		}
+	}
+
+	/*
+	 * Check Other stand alone pd ports to set SLEEP_MASK_USB_PD:
+	 * In [pe_src_send_capabilities_run, pe_snk_select_capability_entry]
+	 * states receive [GoodCRC, SRC_CAP] from port partner, then EC deep
+	 * doze mode will be disabled.
+	 * Otherwise, EC deep doze mode will be enabled.
+	 */
+	if (!prevent_deep_sleep) {
+		for (; i < board_get_usb_pd_port_count(); i++)
+			if (pd_capable(i))
+				prevent_deep_sleep = true;
+	}
+
+	if (prevent_deep_sleep)
+		disable_sleep(SLEEP_MASK_USB_PD);
+	else
+		enable_sleep(SLEEP_MASK_USB_PD);
+}
+
+static void it8xxx2_tcpm_hook_connect(void)
 {
 	int port = TASK_ID_TO_PD_PORT(task_get_current());
 
+	/*
+	 * If it isn't ITE active port, then return.
+	 *
+	 * NOTE: If we don't use all the ITE pd ports on a board, then we
+	 *       need to start from port0 to use the ITE pd port. If we
+	 *       start from port1, then port1 HOOK function never works.
+	 */
+	if (port > (CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT - 1))
+		return;
+
+#ifdef CONFIG_USB_PD_TCPMV2
 	/*
 	 * There are five cases that hook_connect() be called by TCPMv2:
 	 * 1)AttachWait.SNK -> Attached.SNK: disable detect interrupt.
@@ -808,52 +930,91 @@ static void it83xx_tcpm_hook_connect(void)
 	 * SRC_DISCONNECT and SNK_DISCONNECT in TCPMv1. Every time we go to
 	 * Try.SRC/TryWait.SNK state, the plug in interrupt will be enabled and
 	 * fire for 3), 4), 5) cases, then set correctly for the SRC detect plug
-	 * out or the SNK disable detect, so TCPMv1 needn't hook connection.
+	 * out or the SNK disable detect, so TCPMv1 needn't this.
+	 */
+	it8xxx2_tcpm_switch_plug_out_type(port);
+#endif
+	/* Enable PD PHY Tx and Rx module since type-c has connected. */
+	USBPD_ENABLE_BMC_PHY(port);
+	/*
+	 * After we're in attached.[SRC, SNK] states and before we receive
+	 * [GoodCRC of SRC_CAP, SRC_CAP] this period time, if EC goes to
+	 * deep doze mode, the pd clock will be gated, then pd can't
+	 * transmit and receive any messages, so we disable deep doze mode
+	 * to make sure that pd won't miss any messages.
 	 */
-	it83xx_tcpm_switch_plug_out_type(port);
+	tc_update_pd_sleep_mask(port);
 }
 
-DECLARE_HOOK(HOOK_USB_PD_CONNECT, it83xx_tcpm_hook_connect, HOOK_PRIO_DEFAULT);
-#endif
+DECLARE_HOOK(HOOK_USB_PD_CONNECT, it8xxx2_tcpm_hook_connect, HOOK_PRIO_DEFAULT);
 
-static void it83xx_tcpm_sw_reset(void)
+static void it8xxx2_tcpm_hook_disconnect(void)
 {
 	int port = TASK_ID_TO_PD_PORT(task_get_current());
 
+	/*
+	 * If it isn't ITE active port, then return.
+	 *
+	 * NOTE: If we don't use all the ITE pd ports on a board, then we
+	 *       need to start from port0 to use the ITE pd port. If we
+	 *       start from port1, then port1 HOOK function never works.
+	 */
+	if (port > (CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT - 1))
+		return;
+
 	if (IS_ENABLED(IT83XX_INTC_PLUG_IN_OUT_SUPPORT))
 		/*
 		 * Switch to detect plug in and enable detect plug in interrupt,
 		 * since pd task has detected a type-c physical disconnected.
 		 */
-		IT83XX_USBPD_TCDCR(port) &= ~(USBPD_REG_PLUG_OUT_SELECT |
-			USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE);
+		IT83XX_USBPD_TCDCR(port) &=
+			~(USBPD_REG_PLUG_OUT_SELECT |
+			  USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE);
 
 	/* Exit BIST test data mode */
 	USBPD_SW_RESET(port);
+
+	/*
+	 * Init rx status and disable PD PHY Tx and Rx module for better power
+	 * consumption since type-c has disconnected.
+	 */
+	rx_en[port] = 0;
+	if (IS_ENABLED(CONFIG_USB_PD_DECODE_SOP))
+		sop_prime_en[port] = 0;
+	USBPD_DISABLE_BMC_PHY(port);
+	/*
+	 * Since PD BMC PHY is off, then EC can go to deep doze mode and
+	 * turn off pd clock.
+	 */
+	tc_update_pd_sleep_mask(port);
 }
 
-DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, it83xx_tcpm_sw_reset, HOOK_PRIO_DEFAULT);
-
-const struct tcpm_drv it83xx_tcpm_drv = {
-	.init			= &it83xx_tcpm_init,
-	.release		= &it83xx_tcpm_release,
-	.get_cc			= &it83xx_tcpm_get_cc,
-	.select_rp_value	= &it83xx_tcpm_select_rp_value,
-	.set_cc			= &it83xx_tcpm_set_cc,
-	.set_polarity		= &it83xx_tcpm_set_polarity,
-	.set_vconn		= &it83xx_tcpm_set_vconn,
-	.set_msg_header		= &it83xx_tcpm_set_msg_header,
-	.set_rx_enable		= &it83xx_tcpm_set_rx_enable,
-	.get_message_raw	= &it83xx_tcpm_get_message_raw,
-	.transmit		= &it83xx_tcpm_transmit,
+DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, it8xxx2_tcpm_hook_disconnect,
+	     HOOK_PRIO_DEFAULT);
+
+const struct tcpm_drv it8xxx2_tcpm_drv = {
+	.init = &it8xxx2_tcpm_init,
+	.release = &it8xxx2_tcpm_release,
+	.get_cc = &it8xxx2_tcpm_get_cc,
+	.select_rp_value = &it8xxx2_tcpm_select_rp_value,
+	.set_cc = &it8xxx2_tcpm_set_cc,
+	.set_polarity = &it8xxx2_tcpm_set_polarity,
+#ifdef CONFIG_USB_PD_DECODE_SOP
+	.sop_prime_enable = &it8xxx2_tcpm_decode_sop_prime_enable,
+#endif
+	.set_vconn = &it8xxx2_tcpm_set_vconn,
+	.set_msg_header = &it8xxx2_tcpm_set_msg_header,
+	.set_rx_enable = &it8xxx2_tcpm_set_rx_enable,
+	.get_message_raw = &it8xxx2_tcpm_get_message_raw,
+	.transmit = &it8xxx2_tcpm_transmit,
 #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-	.drp_toggle		= NULL,
+	.drp_toggle = NULL,
 #endif
-	.get_chip_info		= &it83xx_tcpm_get_chip_info,
+	.get_chip_info = &it8xxx2_tcpm_get_chip_info,
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	.enter_low_power_mode	= &it83xx_tcpm_enter_low_power_mode,
+	.enter_low_power_mode = &it8xxx2_tcpm_enter_low_power_mode,
 #endif
 #ifdef CONFIG_USB_PD_FRS_TCPC
-	.set_frs_enable		= &it83xx_tcpm_set_frs_enable,
+	.set_frs_enable = &it8xxx2_tcpm_set_frs_enable,
 #endif
 };
diff --git a/driver/tcpm/ite_pd_intc.c b/driver/tcpm/ite_pd_intc.c
new file mode 100644
index 0000000000..1b5e090d2f
--- /dev/null
+++ b/driver/tcpm/ite_pd_intc.c
@@ -0,0 +1,87 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "it83xx_pd.h"
+#include "ite_pd_intc.h"
+#include "task.h"
+#include "tcpm/tcpm.h"
+#include "usb_pd.h"
+
+void chip_pd_irq(enum usbpd_port port)
+{
+	task_clear_pending_irq(usbpd_ctrl_regs[port].irq);
+
+	/* check status */
+	if (IS_ENABLED(IT83XX_INTC_FAST_SWAP_SUPPORT) &&
+	    IS_ENABLED(CONFIG_USB_PD_FRS_TCPC) &&
+	    IS_ENABLED(CONFIG_USB_PD_REV30)) {
+		/*
+		 * FRS detection must handle first, because we need to short
+		 * the interrupt -> board_frs_handler latency-critical time.
+		 */
+		if (USBPD_IS_FAST_SWAP_DETECT(port)) {
+			/* clear detect FRS signal (cc to GND) status */
+			USBPD_CLEAR_FRS_DETECT_STATUS(port);
+			if (board_frs_handler)
+				board_frs_handler(port);
+			/* inform TCPMv2 to change state */
+			pd_got_frs_signal(port);
+		}
+	}
+
+	if (USBPD_IS_HARD_RESET_DETECT(port)) {
+		/* clear interrupt */
+		IT83XX_USBPD_ISR(port) = USBPD_REG_MASK_HARD_RESET_DETECT;
+		USBPD_SW_RESET(port);
+		task_set_event(PD_PORT_TO_TASK_ID(port),
+			       PD_EVENT_RX_HARD_RESET);
+	}
+
+	if (USBPD_IS_RX_DONE(port)) {
+		tcpm_enqueue_message(port);
+		/* clear RX done interrupt */
+		IT83XX_USBPD_ISR(port) = USBPD_REG_MASK_MSG_RX_DONE;
+	}
+
+	if (USBPD_IS_TX_DONE(port)) {
+#ifdef CONFIG_USB_PD_TCPM_DRIVER_IT8XXX2
+		it8xxx2_clear_tx_error_status(port);
+		/* check TX status, clear by TX_DONE status too */
+		if (USBPD_IS_TX_ERR(port))
+			it8xxx2_get_tx_error_status(port);
+#endif
+		/* clear TX done interrupt */
+		IT83XX_USBPD_ISR(port) = USBPD_REG_MASK_MSG_TX_DONE;
+		task_set_event(PD_PORT_TO_TASK_ID(port),
+			       TASK_EVENT_PHY_TX_DONE);
+	}
+
+	if (IS_ENABLED(IT83XX_INTC_PLUG_IN_OUT_SUPPORT)) {
+		if (USBPD_IS_PLUG_IN_OUT_DETECT(port)) {
+			if (USBPD_IS_PLUG_IN(port))
+				/*
+				 * When tcpc detect type-c plug in:
+				 * 1)If we are sink, disable detect interrupt,
+				 * messages on cc line won't trigger interrupt.
+				 * 2)If we are source, then set plug out
+				 * detection.
+				 */
+				switch_plug_out_type(port);
+			else
+				/*
+				 * When tcpc detect type-c plug out:
+				 * switch to detect plug in.
+				 */
+				IT83XX_USBPD_TCDCR(port) &=
+					~USBPD_REG_PLUG_OUT_SELECT;
+
+			/* clear type-c device plug in/out detect interrupt */
+			IT83XX_USBPD_TCDCR(port) |=
+				USBPD_REG_PLUG_IN_OUT_DETECT_STAT;
+			task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_CC);
+		}
+	}
+}
diff --git a/driver/tcpm/ite_pd_intc.h b/driver/tcpm/ite_pd_intc.h
new file mode 100644
index 0000000000..55768da446
--- /dev/null
+++ b/driver/tcpm/ite_pd_intc.h
@@ -0,0 +1,22 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* ITE PD INTC control module */
+
+#ifndef __CROS_EC_ITE_PD_INTC_H
+#define __CROS_EC_ITE_PD_INTC_H
+
+/**
+ * ITE embedded PD interrupt routine
+ *
+ * NOTE: Enable ITE embedded PD that it requires CONFIG_USB_PD_TCPM_ITE_ON_CHIP
+ *
+ * @param port Type-C port number
+ *
+ * @return none
+ */
+void chip_pd_irq(enum usbpd_port port);
+
+#endif /* __CROS_EC_ITE_PD_INTC_H */
diff --git a/driver/tcpm/mt6370.c b/driver/tcpm/mt6370.c
index 07ebeac7f9..881b184fad 100644
--- a/driver/tcpm/mt6370.c
+++ b/driver/tcpm/mt6370.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -9,15 +9,15 @@
 #include "hooks.h"
 #include "mt6370.h"
 #include "task.h"
-#include "tcpci.h"
-#include "tcpm.h"
+#include "tcpm/tcpci.h"
+#include "tcpm/tcpm.h"
 #include "timer.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static int mt6370_polarity;
 
@@ -36,7 +36,6 @@ static int mt6370_init(int port)
 
 	/* Only do soft-reset in shipping mode. (b:122017882) */
 	if (!(val & MT6370_REG_SHIPPING_OFF)) {
-
 		/* Software reset. */
 		rv = tcpc_write(port, MT6370_REG_SWRESET, 1);
 		if (rv)
@@ -91,7 +90,7 @@ static inline int mt6370_init_cc_params(int port, int cc_res)
 }
 
 static int mt6370_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2)
+			 enum tcpc_cc_voltage_status *cc2)
 {
 	int status;
 	int rv;
@@ -186,36 +185,36 @@ int mt6370_vconn_discharge(int port)
 
 /* MT6370 is a TCPCI compatible port controller */
 const struct tcpm_drv mt6370_tcpm_drv = {
-	.init			= &mt6370_init,
-	.release		= &tcpci_tcpm_release,
-	.get_cc			= &mt6370_get_cc,
+	.init = &mt6370_init,
+	.release = &tcpci_tcpm_release,
+	.get_cc = &mt6370_get_cc,
 #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	.check_vbus_level	= &tcpci_tcpm_check_vbus_level,
+	.check_vbus_level = &tcpci_tcpm_check_vbus_level,
 #endif
-	.select_rp_value	= &tcpci_tcpm_select_rp_value,
-	.set_cc			= &mt6370_set_cc,
-	.set_polarity		= &mt6370_set_polarity,
+	.select_rp_value = &tcpci_tcpm_select_rp_value,
+	.set_cc = &mt6370_set_cc,
+	.set_polarity = &mt6370_set_polarity,
 #ifdef CONFIG_USB_PD_DECODE_SOP
-	.sop_prime_disable	= &tcpci_tcpm_sop_prime_disable,
+	.sop_prime_enable = &tcpci_tcpm_sop_prime_enable,
 #endif
-	.set_vconn		= &tcpci_tcpm_set_vconn,
-	.set_msg_header		= &tcpci_tcpm_set_msg_header,
-	.set_rx_enable		= &tcpci_tcpm_set_rx_enable,
-	.get_message_raw	= &tcpci_tcpm_get_message_raw,
-	.transmit		= &tcpci_tcpm_transmit,
-	.tcpc_alert		= &tcpci_tcpc_alert,
+	.set_vconn = &tcpci_tcpm_set_vconn,
+	.set_msg_header = &tcpci_tcpm_set_msg_header,
+	.set_rx_enable = &tcpci_tcpm_set_rx_enable,
+	.get_message_raw = &tcpci_tcpm_get_message_raw,
+	.transmit = &tcpci_tcpm_transmit,
+	.tcpc_alert = &tcpci_tcpc_alert,
 #ifdef CONFIG_USB_PD_DISCHARGE_TCPC
-	.tcpc_discharge_vbus	= &tcpci_tcpc_discharge_vbus,
+	.tcpc_discharge_vbus = &tcpci_tcpc_discharge_vbus,
 #endif
 #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-	.drp_toggle		= &tcpci_tcpc_drp_toggle,
-#endif
-	.get_chip_info		= &tcpci_get_chip_info,
-#ifdef CONFIG_USBC_PPC
-	.set_snk_ctrl		= &tcpci_tcpm_set_snk_ctrl,
-	.set_src_ctrl		= &tcpci_tcpm_set_src_ctrl,
+	.drp_toggle = &tcpci_tcpc_drp_toggle,
 #endif
+	.get_chip_info = &tcpci_get_chip_info,
+	.set_snk_ctrl = &tcpci_tcpm_set_snk_ctrl,
+	.set_src_ctrl = &tcpci_tcpm_set_src_ctrl,
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	.enter_low_power_mode	= &mt6370_enter_low_power_mode,
+	.enter_low_power_mode = &mt6370_enter_low_power_mode,
 #endif
+	.set_bist_test_mode = &tcpci_set_bist_test_mode,
+	.get_bist_test_mode = &tcpci_get_bist_test_mode,
 };
diff --git a/driver/tcpm/mt6370.h b/driver/tcpm/mt6370.h
index cdc3112a3e..cc8e14a378 100644
--- a/driver/tcpm/mt6370.h
+++ b/driver/tcpm/mt6370.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,158 +10,158 @@
 
 /* MT6370 Private RegMap */
 
-#define MT6370_REG_PHY_CTRL1			0x80
-#define MT6370_REG_PHY_CTRL2			0x81
-#define MT6370_REG_PHY_CTRL3			0x82
-#define MT6370_REG_PHY_CTRL6			0x85
-
-#define MT6370_REG_CLK_CTRL2			0x87
-#define MT6370_REG_CLK_CTRL3			0x88
-
-#define MT6370_REG_RUST_STATUS			0x8A
-#define MT6370_REG_RUST_INT_EVENT		0x8B
-#define MT6370_REG_RUST_MASK			0x8C
-#define MT6370_REG_BMC_CTRL			0x90
-#define MT6370_REG_BMCIO_RXDZSEL		0x93
-#define MT6370_REG_VCONN_CLIMITEN		0x95
-
-#define MT6370_REG_OVP_FLAG_SEL			0x96
-
-#define MT6370_REG_RT_STATUS			0x97
-#define MT6370_REG_RT_INT			0x98
-#define MT6370_REG_RT_MASK			0x99
-#define RT5081_REG_BMCIO_RXDZEN			0x9A
-#define MT6370_REG_IDLE_CTRL			0x9B
-#define MT6370_REG_INTRST_CTRL			0x9C
-#define MT6370_REG_WATCHDOG_CTRL		0x9D
-#define MT6370_REG_I2CRST_CTRL			0X9E
-
-#define MT6370_REG_SWRESET			0xA0
-#define MT6370_REG_TTCPC_FILTER			0xA1
-#define MT6370_REG_DRP_TOGGLE_CYCLE		0xA2
-#define MT6370_REG_DRP_DUTY_CTRL		0xA3
-#define MT6370_REG_RUST_DETECTION		0xAD
-#define MT6370_REG_RUST_CONTROL			0xAE
-#define MT6370_REG_BMCIO_RXDZEN			0xAF
-#define MT6370_REG_DRP_RUST			0xB9
-
-#define MT6370_REG_UNLOCK_PW2			0xF0
-#define MT6370_REG_UNLOCK_PW1			0xF1
-
-#define MT6370_TCPC_I2C_ADDR_FLAGS		0x4E
+#define MT6370_REG_PHY_CTRL1 0x80
+#define MT6370_REG_PHY_CTRL2 0x81
+#define MT6370_REG_PHY_CTRL3 0x82
+#define MT6370_REG_PHY_CTRL6 0x85
+
+#define MT6370_REG_CLK_CTRL2 0x87
+#define MT6370_REG_CLK_CTRL3 0x88
+
+#define MT6370_REG_RUST_STATUS 0x8A
+#define MT6370_REG_RUST_INT_EVENT 0x8B
+#define MT6370_REG_RUST_MASK 0x8C
+#define MT6370_REG_BMC_CTRL 0x90
+#define MT6370_REG_BMCIO_RXDZSEL 0x93
+#define MT6370_REG_VCONN_CLIMITEN 0x95
+
+#define MT6370_REG_OVP_FLAG_SEL 0x96
+
+#define MT6370_REG_RT_STATUS 0x97
+#define MT6370_REG_RT_INT 0x98
+#define MT6370_REG_RT_MASK 0x99
+#define RT5081_REG_BMCIO_RXDZEN 0x9A
+#define MT6370_REG_IDLE_CTRL 0x9B
+#define MT6370_REG_INTRST_CTRL 0x9C
+#define MT6370_REG_WATCHDOG_CTRL 0x9D
+#define MT6370_REG_I2CRST_CTRL 0X9E
+
+#define MT6370_REG_SWRESET 0xA0
+#define MT6370_REG_TTCPC_FILTER 0xA1
+#define MT6370_REG_DRP_TOGGLE_CYCLE 0xA2
+#define MT6370_REG_DRP_DUTY_CTRL 0xA3
+#define MT6370_REG_RUST_DETECTION 0xAD
+#define MT6370_REG_RUST_CONTROL 0xAE
+#define MT6370_REG_BMCIO_RXDZEN 0xAF
+#define MT6370_REG_DRP_RUST 0xB9
+
+#define MT6370_REG_UNLOCK_PW2 0xF0
+#define MT6370_REG_UNLOCK_PW1 0xF1
+
+#define MT6370_TCPC_I2C_ADDR_FLAGS 0x4E
 
 /*
  * MT6370_REG_PHY_CTRL1				0x80
  */
 
-#define MT6370_REG_PHY_CTRL1_SET(retry_discard, toggle_cnt, bus_idle_cnt,      \
-				 rx_filter)                                    \
-	((retry_discard << 7) | (toggle_cnt << 4) | (bus_idle_cnt << 2) |      \
+#define MT6370_REG_PHY_CTRL1_SET(retry_discard, toggle_cnt, bus_idle_cnt, \
+				 rx_filter)                               \
+	((retry_discard << 7) | (toggle_cnt << 4) | (bus_idle_cnt << 2) | \
 	 (rx_filter & 0x03))
 
 /*
  * MT6370_REG_CLK_CTRL2				0x87
  */
 
-#define MT6370_REG_CLK_DIV_600K_EN		BIT(7)
-#define MT6370_REG_CLK_BCLK2_EN			BIT(6)
-#define MT6370_REG_CLK_BCLK2_TG_EN		BIT(5)
-#define MT6370_REG_CLK_DIV_300K_EN		BIT(3)
-#define MT6370_REG_CLK_CK_300K_EN		BIT(2)
-#define MT6370_REG_CLK_BCLK_EN			BIT(1)
-#define MT6370_REG_CLK_BCLK_TH_EN		BIT(0)
+#define MT6370_REG_CLK_DIV_600K_EN BIT(7)
+#define MT6370_REG_CLK_BCLK2_EN BIT(6)
+#define MT6370_REG_CLK_BCLK2_TG_EN BIT(5)
+#define MT6370_REG_CLK_DIV_300K_EN BIT(3)
+#define MT6370_REG_CLK_CK_300K_EN BIT(2)
+#define MT6370_REG_CLK_BCLK_EN BIT(1)
+#define MT6370_REG_CLK_BCLK_TH_EN BIT(0)
 
 /*
  * MT6370_REG_CLK_CTRL3				0x88
  */
 
-#define MT6370_REG_CLK_OSCMUX_RG_EN		BIT(7)
-#define MT6370_REG_CLK_CK_24M_EN		BIT(6)
-#define MT6370_REG_CLK_OSC_RG_EN		BIT(5)
-#define MT6370_REG_CLK_DIV_2P4M_EN		BIT(4)
-#define MT6370_REG_CLK_CK_2P4M_EN		BIT(3)
-#define MT6370_REG_CLK_PCLK_EN			BIT(2)
-#define MT6370_REG_CLK_PCLK_RG_EN		BIT(1)
-#define MT6370_REG_CLK_PCLK_TG_EN		BIT(0)
+#define MT6370_REG_CLK_OSCMUX_RG_EN BIT(7)
+#define MT6370_REG_CLK_CK_24M_EN BIT(6)
+#define MT6370_REG_CLK_OSC_RG_EN BIT(5)
+#define MT6370_REG_CLK_DIV_2P4M_EN BIT(4)
+#define MT6370_REG_CLK_CK_2P4M_EN BIT(3)
+#define MT6370_REG_CLK_PCLK_EN BIT(2)
+#define MT6370_REG_CLK_PCLK_RG_EN BIT(1)
+#define MT6370_REG_CLK_PCLK_TG_EN BIT(0)
 
 /*
  * MT6370_REG_RX_TX_DBG				0x8b
  */
 
-#define MT6370_REG_RX_TX_DBG_RX_BUSY		BIT(7)
-#define MT6370_REG_RX_TX_DBG_TX_BUSY		BIT(6)
+#define MT6370_REG_RX_TX_DBG_RX_BUSY BIT(7)
+#define MT6370_REG_RX_TX_DBG_TX_BUSY BIT(6)
 
 /*
  * MT6370_REG_BMC_CTRL				0x90
  */
 
-#define MT6370_REG_IDLE_EN			BIT(6)
-#define MT6370_REG_DISCHARGE_EN			BIT(5)
-#define MT6370_REG_BMCIO_LPRPRD			BIT(4)
-#define MT6370_REG_BMCIO_LPEN			BIT(3)
-#define MT6370_REG_BMCIO_BG_EN			BIT(2)
-#define MT6370_REG_VBUS_DET_EN			BIT(1)
-#define MT6370_REG_BMCIO_OSC_EN			BIT(0)
-#define MT6370_REG_BMC_CTRL_DEFAULT                                            \
-	(MT6370_REG_BMCIO_BG_EN | MT6370_REG_VBUS_DET_EN |                     \
+#define MT6370_REG_IDLE_EN BIT(6)
+#define MT6370_REG_DISCHARGE_EN BIT(5)
+#define MT6370_REG_BMCIO_LPRPRD BIT(4)
+#define MT6370_REG_BMCIO_LPEN BIT(3)
+#define MT6370_REG_BMCIO_BG_EN BIT(2)
+#define MT6370_REG_VBUS_DET_EN BIT(1)
+#define MT6370_REG_BMCIO_OSC_EN BIT(0)
+#define MT6370_REG_BMC_CTRL_DEFAULT                        \
+	(MT6370_REG_BMCIO_BG_EN | MT6370_REG_VBUS_DET_EN | \
 	 MT6370_REG_BMCIO_OSC_EN)
 
 /*
  * MT6370_REG_BMCIO_RXDZSEL			0x93
  */
 
-#define MT6370_MASK_OCCTRL_SEL			0xE0
-#define MT6370_OCCTRL_600MA			0x80
-#define MT6370_MASK_BMCIO_RXDZSEL		BIT(0)
+#define MT6370_MASK_OCCTRL_SEL 0xE0
+#define MT6370_OCCTRL_600MA 0x80
+#define MT6370_MASK_BMCIO_RXDZSEL BIT(0)
 
 /*
  * MT6370_REG_OVP_FLAG_SEL			0x96
  */
 
-#define MT6370_MASK_DISCHARGE_LVL		0x03
-#define MT6370_REG_DISCHARGE_LVL		BIT(0)
+#define MT6370_MASK_DISCHARGE_LVL 0x03
+#define MT6370_REG_DISCHARGE_LVL BIT(0)
 
 /*
  * MT6370_REG_RT_STATUS				0x97
  */
 
-#define MT6370_REG_RA_DETACH			BIT(5)
-#define MT6370_REG_VBUS_80			BIT(1)
+#define MT6370_REG_RA_DETACH BIT(5)
+#define MT6370_REG_VBUS_80 BIT(1)
 
 /*
  * MT6370_REG_RT_INT				0x98
  */
 
-#define MT6370_REG_INT_RA_DETACH		BIT(5)
-#define MT6370_REG_INT_WATCHDOG			BIT(2)
-#define MT6370_REG_INT_VBUS_80			BIT(1)
-#define MT6370_REG_INT_WAKEUP			BIT(0)
+#define MT6370_REG_INT_RA_DETACH BIT(5)
+#define MT6370_REG_INT_WATCHDOG BIT(2)
+#define MT6370_REG_INT_VBUS_80 BIT(1)
+#define MT6370_REG_INT_WAKEUP BIT(0)
 
 /*
  * MT6370_REG_RT_MASK				0x99
  */
 
-#define MT6370_REG_M_RA_DETACH			BIT(5)
-#define MT6370_REG_M_WATCHDOG			BIT(2)
-#define MT6370_REG_M_VBUS_80			BIT(1)
-#define MT6370_REG_M_WAKEUP			BIT(0)
+#define MT6370_REG_M_RA_DETACH BIT(5)
+#define MT6370_REG_M_WATCHDOG BIT(2)
+#define MT6370_REG_M_VBUS_80 BIT(1)
+#define MT6370_REG_M_WAKEUP BIT(0)
 
 /*
  * MT6370_REG_IDLE_CTRL				0x9B
  */
 
-#define MT6370_REG_CK_300K_SEL			BIT(7)
-#define MT6370_REG_SHIPPING_OFF			BIT(5)
-#define MT6370_REG_ENEXTMSG			BIT(4)
-#define MT6370_REG_AUTOIDLE_EN			BIT(3)
+#define MT6370_REG_CK_300K_SEL BIT(7)
+#define MT6370_REG_SHIPPING_OFF BIT(5)
+#define MT6370_REG_ENEXTMSG BIT(4)
+#define MT6370_REG_AUTOIDLE_EN BIT(3)
 
 /* timeout = (tout*2+1) * 6.4ms */
 #ifdef CONFIG_USB_PD_REV30
-#define MT6370_REG_IDLE_SET(ck300, ship_dis, auto_idle, tout)                  \
-	((ck300 << 7) | (ship_dis << 5) | (auto_idle << 3) | (tout & 0x07) |   \
+#define MT6370_REG_IDLE_SET(ck300, ship_dis, auto_idle, tout)                \
+	((ck300 << 7) | (ship_dis << 5) | (auto_idle << 3) | (tout & 0x07) | \
 	 MT6370_REG_ENEXTMSG)
 #else
-#define MT6370_REG_IDLE_SET(ck300, ship_dis, auto_idle, tout)                  \
+#define MT6370_REG_IDLE_SET(ck300, ship_dis, auto_idle, tout) \
 	((ck300 << 7) | (ship_dis << 5) | (auto_idle << 3) | (tout & 0x07))
 #endif
 
@@ -169,28 +169,28 @@
  * MT6370_REG_INTRST_CTRL			0x9C
  */
 
-#define MT6370_REG_INTRST_EN			BIT(7)
+#define MT6370_REG_INTRST_EN BIT(7)
 
 /* timeout = (tout+1) * 0.2sec */
-#define MT6370_REG_INTRST_SET(en, tout)		((en << 7) | (tout & 0x03))
+#define MT6370_REG_INTRST_SET(en, tout) ((en << 7) | (tout & 0x03))
 
 /*
  * MT6370_REG_WATCHDOG_CTRL			0x9D
  */
 
-#define MT6370_REG_WATCHDOG_EN			BIT(7)
+#define MT6370_REG_WATCHDOG_EN BIT(7)
 
 /* timeout = (tout+1) * 0.4sec */
-#define MT6370_REG_WATCHDOG_CTRL_SET(en, tout)	((en << 7) | (tout & 0x07))
+#define MT6370_REG_WATCHDOG_CTRL_SET(en, tout) ((en << 7) | (tout & 0x07))
 
 /*
  * MT6370_REG_I2CRST_CTRL			0x9E
  */
 
-#define MT6370_REG_I2CRST_EN			BIT(7)
+#define MT6370_REG_I2CRST_EN BIT(7)
 
 /* timeout = (tout+1) * 12.5ms */
-#define MT6370_REG_I2CRST_SET(en, tout)		((en << 7) | (tout & 0x0f))
+#define MT6370_REG_I2CRST_SET(en, tout) ((en << 7) | (tout & 0x0f))
 
 extern const struct tcpm_drv mt6370_tcpm_drv;
 
diff --git a/driver/tcpm/nct38xx.c b/driver/tcpm/nct38xx.c
index 79e46fa12a..8d2be9af54 100644
--- a/driver/tcpm/nct38xx.c
+++ b/driver/tcpm/nct38xx.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,30 +11,89 @@
 #include "hooks.h"
 #include "nct38xx.h"
 #include "task.h"
-#include "tcpci.h"
+#include "tcpm/tcpci.h"
 #include "usb_common.h"
 
+#ifdef CONFIG_ZEPHYR
+#include "usbc/tcpc_nct38xx.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/gpio/gpio_nct38xx.h>
+#endif
+
+#if defined(CONFIG_ZEPHYR) && defined(CONFIG_IO_EXPANDER_NCT38XX)
+#error CONFIG_IO_EXPANDER_NCT38XX cannot be used with Zephyr.
+#error Enable the Zephyr driver CONFIG_GPIO_NCT38XX instead.
+#endif
+
 #if !defined(CONFIG_USB_PD_TCPM_TCPCI)
 #error "NCT38XX is using part of standard TCPCI control"
 #error "Please upgrade your board configuration"
 #endif
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+static enum nct38xx_boot_type boot_type[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+enum nct38xx_boot_type nct38xx_get_boot_type(int port)
+{
+	return boot_type[port];
+}
+
+void nct38xx_reset_notify(int port)
+{
+	/* A full reset also resets the chip's dead battery boot status */
+	boot_type[port] = NCT38XX_BOOT_UNKNOWN;
+}
 
-static int nct38xx_init(int port)
+int nct38xx_init(int port)
 {
 	int rv;
 	int reg;
 
+	/*
+	 * Detect dead battery boot by the default role control value of 0x0A
+	 * once per EC run
+	 */
+	if (boot_type[port] == NCT38XX_BOOT_UNKNOWN) {
+		RETURN_ERROR(tcpc_read(port, TCPC_REG_ROLE_CTRL, &reg));
+
+		if (reg == NCT38XX_ROLE_CTRL_DEAD_BATTERY)
+			boot_type[port] = NCT38XX_BOOT_DEAD_BATTERY;
+		else
+			boot_type[port] = NCT38XX_BOOT_NORMAL;
+	}
+
+	RETURN_ERROR(tcpc_read(port, TCPC_REG_POWER_STATUS, &reg));
+
+	/*
+	 * Set TCPC_CONTROL.DebugAccessoryControl = 1 to control by TCPM,
+	 * not TCPC in most cases.  This must be left alone if we're on a
+	 * dead battery boot with a debug accessory.  CC line detection will
+	 * be delayed if we have booted from a dead battery with a debug
+	 * accessory and change this bit (see b/186799392).
+	 */
+	if ((boot_type[port] == NCT38XX_BOOT_DEAD_BATTERY) &&
+	    (reg & TCPC_REG_POWER_STATUS_DEBUG_ACC_CON))
+		CPRINTS("C%d: Booted in dead battery mode, not changing debug"
+			" control",
+			port);
+	else if (tcpc_config[port].flags & TCPC_FLAGS_NO_DEBUG_ACC_CONTROL)
+		CPRINTS("C%d: NO_DEBUG_ACC_CONTROL", port);
+	else {
+		RETURN_ERROR(tcpc_update8(port, TCPC_REG_TCPC_CTRL,
+					  TCPC_REG_TCPC_CTRL_DEBUG_ACC_CONTROL,
+					  MASK_SET));
+	}
+
 	/*
 	 * Write to the CONTROL_OUT_EN register to enable:
 	 * [6] - CONNDIREN : Connector direction indication output enable
 	 * [2] - SNKEN     : VBUS sink enable output enable
 	 * [0] - SRCEN     : VBUS source voltage enable output enable
 	 */
-	reg = NCT38XX_REG_CTRL_OUT_EN_SRCEN |
-	      NCT38XX_REG_CTRL_OUT_EN_SNKEN |
+	reg = NCT38XX_REG_CTRL_OUT_EN_SRCEN | NCT38XX_REG_CTRL_OUT_EN_SNKEN |
 	      NCT38XX_REG_CTRL_OUT_EN_CONNDIREN;
 
 	rv = tcpc_write(port, NCT38XX_REG_CTRL_OUT_EN, reg);
@@ -42,16 +101,13 @@ static int nct38xx_init(int port)
 		return rv;
 
 	/* Disable OVP */
-	rv = tcpc_update8(port,
-			  TCPC_REG_FAULT_CTRL,
-			  TCPC_REG_FAULT_CTRL_VBUS_OVP_FAULT_DIS,
-			  MASK_SET);
+	rv = tcpc_update8(port, TCPC_REG_FAULT_CTRL,
+			  TCPC_REG_FAULT_CTRL_VBUS_OVP_FAULT_DIS, MASK_SET);
 	if (rv)
 		return rv;
 
 	/* Enable VBus monitor and Disable FRS */
-	rv = tcpc_update8(port,
-			  TCPC_REG_POWER_CTRL,
+	rv = tcpc_update8(port, TCPC_REG_POWER_CTRL,
 			  (TCPC_REG_POWER_CTRL_VBUS_VOL_MONITOR_DIS |
 			   TCPC_REG_POWER_CTRL_FRS_ENABLE),
 			  MASK_CLR);
@@ -59,12 +115,7 @@ static int nct38xx_init(int port)
 		return rv;
 
 	/* Set FRS direction for SNK detect, if FRS is enabled */
-	if (IS_ENABLED(CONFIG_USB_PD_FRS_TCPC)) {
-		reg = TCPC_REG_DEV_CAP_2_SNK_FR_SWAP;
-		rv = tcpc_write(port, TCPC_REG_DEV_CAP_2, reg);
-		if (rv)
-			return rv;
-
+	if (tcpm_tcpc_has_frs_control(port)) {
 		reg = TCPC_REG_CONFIG_EXT_1_FR_SWAP_SNK_DIR;
 		rv = tcpc_write(port, TCPC_REG_CONFIG_EXT_1, reg);
 		if (rv)
@@ -88,18 +139,36 @@ static int nct38xx_init(int port)
 	 * Enable the Vendor Define alert event only when the IO expander
 	 * feature is defined
 	 */
-	if (IS_ENABLED(CONFIG_IO_EXPANDER_NCT38XX))
+	if (IS_ENABLED(CONFIG_IO_EXPANDER_NCT38XX) ||
+	    IS_ENABLED(CONFIG_GPIO_NCT38XX)) {
+#ifdef CONFIG_ZEPHYR
+		const struct device *dev =
+			nct38xx_get_gpio_device_from_port(port);
+
+		if (!device_is_ready(dev)) {
+			CPRINTS("C%d: device is not ready", port);
+			return EC_ERROR_BUSY;
+		}
+#endif /* CONFIG_ZEPHYR */
 		reg |= TCPC_REG_ALERT_VENDOR_DEF;
+	}
+
+	rv = tcpc_update16(port, TCPC_REG_ALERT_MASK, reg, MASK_SET);
+
+	if (rv)
+		return rv;
 
-	rv = tcpc_update16(port,
-			   TCPC_REG_ALERT_MASK,
-			   reg,
-			   MASK_SET);
+	/* Enable full VCONN protection (Over-Current and Short-Circuit) */
+	reg = NCT38XX_REG_VBC_FAULT_CTL_VC_OCP_EN |
+	      NCT38XX_REG_VBC_FAULT_CTL_VC_SCP_EN |
+	      NCT38XX_REG_VBC_FAULT_CTL_FAULT_VC_OFF;
+
+	rv = tcpc_update8(port, NCT38XX_REG_VBC_FAULT_CTL, reg, MASK_SET);
 
 	return rv;
 }
 
-static int nct38xx_tcpm_init(int port)
+test_export_static int nct38xx_tcpm_init(int port)
 {
 	int rv;
 
@@ -110,7 +179,7 @@ static int nct38xx_tcpm_init(int port)
 	return nct38xx_init(port);
 }
 
-static int nct38xx_tcpm_set_cc(int port, int pull)
+test_export_static int nct38xx_tcpm_set_cc(int port, int pull)
 {
 	/*
 	 * Setting the CC lines to open/open requires that the NCT CTRL_OUT
@@ -135,31 +204,20 @@ static int nct38xx_tcpm_set_cc(int port, int pull)
 	 * SNKEN will be re-enabled in nct38xx_init above (from tcpm_init), or
 	 * when CC lines are set again, or when sinking is disabled.
 	 */
-	enum mask_update_action action = MASK_SET;
 	int rv;
+	enum mask_update_action action =
+		pull == TYPEC_CC_OPEN && tcpm_get_snk_ctrl(port) ? MASK_CLR :
+								   MASK_SET;
 
-	if (pull == TYPEC_CC_OPEN) {
-		bool is_sinking;
-
-		rv = tcpm_get_snk_ctrl(port, &is_sinking);
-		if (rv)
-			return rv;
-
-		if (is_sinking)
-			action = MASK_CLR;
-	}
-
-	rv = tcpc_update8(port,
-			  NCT38XX_REG_CTRL_OUT_EN,
-			  NCT38XX_REG_CTRL_OUT_EN_SNKEN,
-			  action);
+	rv = tcpc_update8(port, NCT38XX_REG_CTRL_OUT_EN,
+			  NCT38XX_REG_CTRL_OUT_EN_SNKEN, action);
 	if (rv)
 		return rv;
 
 	return tcpci_tcpm_set_cc(port, pull);
 }
 
-static int nct38xx_tcpm_set_snk_ctrl(int port, int enable)
+test_export_static int nct38xx_tcpm_set_snk_ctrl(int port, int enable)
 {
 	int rv;
 
@@ -168,10 +226,8 @@ static int nct38xx_tcpm_set_snk_ctrl(int port, int enable)
 	 * USB_Cx_TCPC_VBSNK_EN_L will be driven high.
 	 */
 	if (!enable) {
-		rv = tcpc_update8(port,
-				  NCT38XX_REG_CTRL_OUT_EN,
-				  NCT38XX_REG_CTRL_OUT_EN_SNKEN,
-				  MASK_SET);
+		rv = tcpc_update8(port, NCT38XX_REG_CTRL_OUT_EN,
+				  NCT38XX_REG_CTRL_OUT_EN_SNKEN, MASK_SET);
 		if (rv)
 			return rv;
 	}
@@ -179,32 +235,71 @@ static int nct38xx_tcpm_set_snk_ctrl(int port, int enable)
 	return tcpci_tcpm_set_snk_ctrl(port, enable);
 }
 
+static inline int tcpc_read_alert_no_lpm_exit(int port, int *val)
+{
+	return tcpc_addr_read16_no_lpm_exit(
+		port, tcpc_config[port].i2c_info.addr_flags, TCPC_REG_ALERT,
+		val);
+}
+
+/* Map Type-C port to IOEX port */
+__overridable int board_map_nct38xx_tcpc_port_to_ioex(int port)
+{
+	return port;
+}
+
+static inline void nct38xx_tcpc_vendor_defined_alert(int port)
+{
+#ifdef CONFIG_ZEPHYR
+	const struct device *dev = nct38xx_get_gpio_device_from_port(port);
+
+	nct38xx_gpio_alert_handler(dev);
+#else
+	int ioexport;
+
+	ioexport = board_map_nct38xx_tcpc_port_to_ioex(port);
+	nct38xx_ioex_event_handler(ioexport);
+#endif /* CONFIG_ZEPHYR */
+}
+
 static void nct38xx_tcpc_alert(int port)
 {
 	int alert, rv;
 
 	/*
-	 * If IO expander feature is defined, read the ALERT register first to
-	 * keep the status of Vendor Define bit. Otherwise, the status of ALERT
-	 * register will be cleared after tcpci_tcpc_alert() is executed.
+	 * The nct3808 is a dual port chip with a shared ALERT
+	 * pin. Avoid taking a port out of LPM if it is not alerting.
+	 *
+	 * The nct38xx exits Idle mode when ALERT is signaled, so there
+	 * is no need to run the TCPM LPM exit code to check the ALERT
+	 * register bits (Ref. NCT38n7/8 Datasheet S 2.3.4 "Setting the
+	 * I2C to Idle"). In fact, running the TCPM LPM exit code causes
+	 * a new CC Status ALERT which has the effect of creating a new
+	 * ALERT as a side-effect of handing an ALERT.
 	 */
-	if (IS_ENABLED(CONFIG_IO_EXPANDER_NCT38XX))
-		rv = tcpc_read16(port, TCPC_REG_ALERT, &alert);
+	rv = tcpc_read_alert_no_lpm_exit(port, &alert);
+	if (rv == EC_SUCCESS && alert == TCPC_REG_ALERT_NONE) {
+		/* No ALERT on this port, return early. */
+		return;
+	}
 
-	/* Process normal TCPC ALERT event and clear status */
+	/* Process normal TCPC ALERT event and clear status. */
 	tcpci_tcpc_alert(port);
 
 	/*
-	 * If IO expander feature is defined, check the Vendor Define bit to
-	 * handle the IOEX IO's interrupt event
+	 * If the IO expander feature is enabled, use the ALERT register
+	 * value read before it was cleared by calling
+	 * tcpci_tcpc_alert().  Check the Vendor Defined Alert bit to
+	 * handle the IOEX IO's interrupt event.
 	 */
-	if (IS_ENABLED(CONFIG_IO_EXPANDER_NCT38XX))
-		if (!rv && (alert & TCPC_REG_ALERT_VENDOR_DEF))
-			nct38xx_ioex_event_handler(port);
-
+	if ((IS_ENABLED(CONFIG_IO_EXPANDER_NCT38XX) ||
+	     IS_ENABLED(CONFIG_GPIO_NCT38XX)) &&
+	    rv == EC_SUCCESS && (alert & TCPC_REG_ALERT_VENDOR_DEF)) {
+		nct38xx_tcpc_vendor_defined_alert(port);
+	}
 }
 
-static int nct3807_handle_fault(int port, int fault)
+test_export_static int nct3807_handle_fault(int port, int fault)
 {
 	int rv = EC_SUCCESS;
 
@@ -215,10 +310,10 @@ static int nct3807_handle_fault(int port, int fault)
 		/* We don't use TCPC OVP, so just disable it */
 		if (fault & TCPC_REG_FAULT_STATUS_VBUS_OVER_VOLTAGE) {
 			/* Disable OVP */
-			rv = tcpc_update8(port,
-				  TCPC_REG_FAULT_CTRL,
-				  TCPC_REG_FAULT_CTRL_VBUS_OVP_FAULT_DIS,
-				  MASK_SET);
+			rv = tcpc_update8(
+				port, TCPC_REG_FAULT_CTRL,
+				TCPC_REG_FAULT_CTRL_VBUS_OVP_FAULT_DIS,
+				MASK_SET);
 			if (rv)
 				return rv;
 		}
@@ -229,47 +324,74 @@ static int nct3807_handle_fault(int port, int fault)
 	return rv;
 }
 
+__maybe_unused test_export_static int nct38xx_set_frs_enable(int port,
+							     int enable)
+{
+	if (!tcpm_tcpc_has_frs_control(port))
+		return EC_SUCCESS;
+
+	/*
+	 * From b/192012189: Enabling FRS for this chip should:
+	 *
+	 * 1.  Make sure that the sink will not disconnect if Vbus will drop
+	 * due to the Fast Role Swap by setting VBUS_SINK_DISCONNECT_THRESHOLD
+	 * to 0
+	 * 2. Enable the FRS interrupt (already done in TCPCI alert init)
+	 * 3. Set POWER_CONTORL.FastRoleSwapEnable to 1
+	 */
+	RETURN_ERROR(tcpc_write16(
+		port, TCPC_REG_VBUS_SINK_DISCONNECT_THRESH,
+		enable ? 0x0000 :
+			 TCPC_REG_VBUS_SINK_DISCONNECT_THRESH_DEFAULT));
+
+	return tcpc_update8(port, TCPC_REG_POWER_CTRL,
+			    TCPC_REG_POWER_CTRL_FRS_ENABLE,
+			    enable ? MASK_SET : MASK_CLR);
+}
+
 const struct tcpm_drv nct38xx_tcpm_drv = {
-	.init			= &nct38xx_tcpm_init,
-	.release		= &tcpci_tcpm_release,
-	.get_cc			= &tcpci_tcpm_get_cc,
+	.init = &nct38xx_tcpm_init,
+	.release = &tcpci_tcpm_release,
+	.get_cc = &tcpci_tcpm_get_cc,
 #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	.check_vbus_level	= &tcpci_tcpm_check_vbus_level,
+	.check_vbus_level = &tcpci_tcpm_check_vbus_level,
 #endif
-	.select_rp_value	= &tcpci_tcpm_select_rp_value,
-	.set_cc			= &nct38xx_tcpm_set_cc,
-	.set_polarity		= &tcpci_tcpm_set_polarity,
+	.get_vbus_voltage = &tcpci_get_vbus_voltage,
+	.select_rp_value = &tcpci_tcpm_select_rp_value,
+	.set_cc = &nct38xx_tcpm_set_cc,
+	.set_polarity = &tcpci_tcpm_set_polarity,
 #ifdef CONFIG_USB_PD_DECODE_SOP
-	.sop_prime_disable	= &tcpci_tcpm_sop_prime_disable,
+	.sop_prime_enable = &tcpci_tcpm_sop_prime_enable,
 #endif
-	.set_vconn		= &tcpci_tcpm_set_vconn,
-	.set_msg_header		= &tcpci_tcpm_set_msg_header,
-	.set_rx_enable		= &tcpci_tcpm_set_rx_enable,
-	.get_message_raw	= &tcpci_tcpm_get_message_raw,
-	.transmit		= &tcpci_tcpm_transmit,
-	.tcpc_alert		= &nct38xx_tcpc_alert,
+	.set_vconn = &tcpci_tcpm_set_vconn,
+	.set_msg_header = &tcpci_tcpm_set_msg_header,
+	.set_rx_enable = &tcpci_tcpm_set_rx_enable,
+	.get_message_raw = &tcpci_tcpm_get_message_raw,
+	.transmit = &tcpci_tcpm_transmit,
+	.tcpc_alert = &nct38xx_tcpc_alert,
 #ifdef CONFIG_USB_PD_DISCHARGE_TCPC
-	.tcpc_discharge_vbus	= &tcpci_tcpc_discharge_vbus,
+	.tcpc_discharge_vbus = &tcpci_tcpc_discharge_vbus,
 #endif
 	.tcpc_enable_auto_discharge_disconnect =
-				  &tcpci_tcpc_enable_auto_discharge_disconnect,
-	.debug_accessory	= &tcpci_tcpc_debug_accessory,
+		&tcpci_tcpc_enable_auto_discharge_disconnect,
+	.debug_accessory = &tcpci_tcpc_debug_accessory,
 
 #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-	.drp_toggle		= &tcpci_tcpc_drp_toggle,
-#endif
-#ifdef CONFIG_USBC_PPC
-	.get_snk_ctrl		= &tcpci_tcpm_get_snk_ctrl,
-	.set_snk_ctrl		= &nct38xx_tcpm_set_snk_ctrl,
-	.get_src_ctrl		= &tcpci_tcpm_get_src_ctrl,
-	.set_src_ctrl		= &tcpci_tcpm_set_src_ctrl,
+	.drp_toggle = &tcpci_tcpc_drp_toggle,
 #endif
-	.get_chip_info		= &tcpci_get_chip_info,
+	.get_snk_ctrl = &tcpci_tcpm_get_snk_ctrl,
+	.set_snk_ctrl = &nct38xx_tcpm_set_snk_ctrl,
+	.get_src_ctrl = &tcpci_tcpm_get_src_ctrl,
+	.set_src_ctrl = &tcpci_tcpm_set_src_ctrl,
+	.get_chip_info = &tcpci_get_chip_info,
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	.enter_low_power_mode	= &tcpci_enter_low_power_mode,
+	.enter_low_power_mode = &tcpci_enter_low_power_mode,
 #endif
-#ifdef CONFIG_USB_PD_FRS_TCPC
-	.set_frs_enable         = &tcpci_tcpc_fast_role_swap_enable,
+	.set_bist_test_mode = &tcpci_set_bist_test_mode,
+	.get_bist_test_mode = &tcpci_get_bist_test_mode,
+#ifdef CONFIG_USB_PD_FRS
+	.set_frs_enable = &nct38xx_set_frs_enable,
 #endif
-	.handle_fault		= &nct3807_handle_fault,
+	.handle_fault = &nct3807_handle_fault,
+	.hard_reset_reinit = &tcpci_hard_reset_reinit,
 };
diff --git a/driver/tcpm/nct38xx.h b/driver/tcpm/nct38xx.h
index 65bddf22b1..17f0b9b885 100644
--- a/driver/tcpm/nct38xx.h
+++ b/driver/tcpm/nct38xx.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,58 +10,84 @@
 #define __CROS_EC_USB_PD_TCPM_NCT38XX_H
 
 /* Chip variant ID (Part number)  */
-#define NCT38XX_VARIANT_MASK               0x1C
-#define NCT38XX_VARIANT_3807               0x0
-#define NCT38XX_VARIANT_3808               0x2
+#define NCT38XX_VARIANT_MASK 0x1C
+#define NCT38XX_VARIANT_3807 0x0
+#define NCT38XX_VARIANT_3808 0x2
 
 /* There are two IO ports in NCT3807 */
-#define NCT38XX_NCT3807_MAX_IO_PORT        2
+#define NCT38XX_NCT3807_MAX_IO_PORT 2
 /* There is only one IO port in NCT3808 */
-#define NCT38XX_NCT3808_MAX_IO_PORT        1
+#define NCT38XX_NCT3808_MAX_IO_PORT 1
 
-#define NCT38XX_SUPPORT_GPIO_FLAGS (GPIO_OPEN_DRAIN | GPIO_INPUT | \
-		GPIO_OUTPUT | GPIO_LOW | GPIO_HIGH | GPIO_INT_F_RISING | \
-		GPIO_INT_F_FALLING | GPIO_INT_F_HIGH | GPIO_INT_F_LOW)
+#define NCT38XX_SUPPORT_GPIO_FLAGS                                           \
+	(GPIO_OPEN_DRAIN | GPIO_INPUT | GPIO_OUTPUT | GPIO_LOW | GPIO_HIGH | \
+	 GPIO_INT_F_RISING | GPIO_INT_F_FALLING | GPIO_INT_F_HIGH |          \
+	 GPIO_INT_F_LOW)
 
 /* I2C interface */
-#define NCT38XX_I2C_ADDR1_1_FLAGS          0x70
-#define NCT38XX_I2C_ADDR1_2_FLAGS          0x71
-#define NCT38XX_I2C_ADDR1_3_FLAGS          0x72
-#define NCT38XX_I2C_ADDR1_4_FLAGS          0x73
-
-#define NCT38XX_I2C_ADDR2_1_FLAGS          0x74
-#define NCT38XX_I2C_ADDR2_2_FLAGS          0x75
-#define NCT38XX_I2C_ADDR2_3_FLAGS          0x76
-#define NCT38XX_I2C_ADDR2_4_FLAGS          0x77
-
-#define NCT38XX_REG_VENDOR_ID_L            0x00
-#define NCT38XX_REG_VENDOR_ID_H            0x01
-#define NCT38XX_VENDOR_ID                  0x0416
-
-#define NCT38XX_PRODUCT_ID                 0xC301
-
-#define NCT38XX_REG_GPIO_DATA_IN(n)       (0xC0 + ((n) * 8))
-#define NCT38XX_REG_GPIO_DATA_OUT(n)      (0xC1 + ((n) * 8))
-#define NCT38XX_REG_GPIO_DIR(n)           (0xC2 + ((n) * 8))
-#define NCT38XX_REG_GPIO_OD_SEL(n)        (0xC3 + ((n) * 8))
-#define NCT38XX_REG_GPIO_ALERT_RISE(n)    (0xC4 + ((n) * 8))
-#define NCT38XX_REG_GPIO_ALERT_FALL(n)    (0xC5 + ((n) * 8))
-#define NCT38XX_REG_GPIO_ALERT_LEVEL(n)   (0xC6 + ((n) * 8))
-#define NCT38XX_REG_GPIO_ALERT_MASK(n)    (0xC7 + ((n) * 8))
-#define NCT38XX_REG_MUX_CONTROL            0xD0
-#define NCT38XX_REG_GPIO_ALERT_STAT(n)    (0xD4 + (n))
+#define NCT38XX_I2C_ADDR1_1_FLAGS 0x70
+#define NCT38XX_I2C_ADDR1_2_FLAGS 0x71
+#define NCT38XX_I2C_ADDR1_3_FLAGS 0x72
+#define NCT38XX_I2C_ADDR1_4_FLAGS 0x73
+
+#define NCT38XX_I2C_ADDR2_1_FLAGS 0x74
+#define NCT38XX_I2C_ADDR2_2_FLAGS 0x75
+#define NCT38XX_I2C_ADDR2_3_FLAGS 0x76
+#define NCT38XX_I2C_ADDR2_4_FLAGS 0x77
+
+#define NCT38XX_REG_VENDOR_ID_L 0x00
+#define NCT38XX_REG_VENDOR_ID_H 0x01
+#define NCT38XX_VENDOR_ID 0x0416
+
+#define NCT38XX_PRODUCT_ID 0xC301
+
+/*
+ * Default value from the ROLE_CTRL register on first boot will depend on
+ * whether we're coming from a dead battery state.
+ */
+#define NCT38XX_ROLE_CTRL_DEAD_BATTERY 0x0A
+#define NCT38XX_ROLE_CTRL_GOOD_BATTERY 0x4A
+
+#define NCT38XX_REG_GPIO_DATA_IN(n) (0xC0 + ((n)*8))
+#define NCT38XX_REG_GPIO_DATA_OUT(n) (0xC1 + ((n)*8))
+#define NCT38XX_REG_GPIO_DIR(n) (0xC2 + ((n)*8))
+#define NCT38XX_REG_GPIO_OD_SEL(n) (0xC3 + ((n)*8))
+#define NCT38XX_REG_GPIO_ALERT_RISE(n) (0xC4 + ((n)*8))
+#define NCT38XX_REG_GPIO_ALERT_FALL(n) (0xC5 + ((n)*8))
+#define NCT38XX_REG_GPIO_ALERT_LEVEL(n) (0xC6 + ((n)*8))
+#define NCT38XX_REG_GPIO_ALERT_MASK(n) (0xC7 + ((n)*8))
+#define NCT38XX_REG_MUX_CONTROL 0xD0
+#define NCT38XX_REG_GPIO_ALERT_STAT(n) (0xD4 + (n))
 
 /* NCT3808 only supports GPIO 2/3/4/6/7 */
-#define NCT38XXX_3808_VALID_GPIO_MASK            0xDC
+#define NCT38XXX_3808_VALID_GPIO_MASK 0xDC
 
-#define NCT38XX_REG_CTRL_OUT_EN            0xD2
-#define NCT38XX_REG_CTRL_OUT_EN_SRCEN      (1 << 0)
-#define NCT38XX_REG_CTRL_OUT_EN_FASTEN     (1 << 1)
-#define NCT38XX_REG_CTRL_OUT_EN_SNKEN      (1 << 2)
-#define NCT38XX_REG_CTRL_OUT_EN_CONNDIREN  (1 << 6)
+#define NCT38XX_REG_CTRL_OUT_EN 0xD2
+#define NCT38XX_REG_CTRL_OUT_EN_SRCEN (1 << 0)
+#define NCT38XX_REG_CTRL_OUT_EN_FASTEN (1 << 1)
+#define NCT38XX_REG_CTRL_OUT_EN_SNKEN (1 << 2)
+#define NCT38XX_REG_CTRL_OUT_EN_CONNDIREN (1 << 6)
 
-#define NCT38XX_RESET_HOLD_DELAY_MS	1
-#define NCT38XX_RESET_POST_DELAY_MS	0
+#define NCT38XX_REG_VBC_FAULT_CTL 0xD7
+#define NCT38XX_REG_VBC_FAULT_CTL_VC_OCP_EN (1 << 0)
+#define NCT38XX_REG_VBC_FAULT_CTL_VC_SCP_EN (1 << 1)
+#define NCT38XX_REG_VBC_FAULT_CTL_FAULT_VC_OFF (1 << 3)
+#define NCT38XX_REG_VBC_FAULT_CTL_VB_OCP_OFF (1 << 4)
+#define NCT38XX_REG_VBC_FAULT_CTL_VC_OVP_OFF (1 << 5)
+
+#define NCT38XX_RESET_HOLD_DELAY_MS 1
+
+/*
+ * From the datasheet (section 4.4.2 Reset Timing) as following:
+ *                       |  Min  |  Max  |
+ * ----------------------+-------+-------+
+ * NCT3807 (single port) |   x   | 1.5ms |
+ * ----------------------+-------+-------+
+ * NCT3808 (dual port)   |   x   |   3ms |
+ * ----------------------+-------+-------+
+ */
+#define NCT3807_RESET_POST_DELAY_MS 2
+#define NCT3808_RESET_POST_DELAY_MS 3
 
 extern const struct tcpm_drv nct38xx_tcpm_drv;
 
@@ -78,9 +104,47 @@ void nct38xx_ioex_handle_alert(int ioex);
 /*
  * Check which IO's interrupt event is triggered. If any, call its
  * registered interrupt handler.
+ *
+ * @param ioex	I/O expander number
+ * @return EC_SUCCESS on success else error
  */
 int nct38xx_ioex_event_handler(int ioex);
 
+/*
+ * Board level function to map USB-C port to IOEX port
+ *
+ * Default function assumes USB-C port number to be same as the
+ * I/O expander port number. If this logic differs, add an
+ * overridable function at the board level.
+ *
+ * @param port	USB-C port number
+ * @return IOEX port number
+ */
+__override_proto int board_map_nct38xx_tcpc_port_to_ioex(int port);
+
+enum nct38xx_boot_type {
+	NCT38XX_BOOT_UNKNOWN,
+	NCT38XX_BOOT_DEAD_BATTERY,
+	NCT38XX_BOOT_NORMAL,
+};
+
+/**
+ * Collect our boot type from the driver
+ *
+ * @param port	USB-C port number
+ * @return	Returns the boot type detected for this chip
+ */
+enum nct38xx_boot_type nct38xx_get_boot_type(int port);
+
+/**
+ * Notify the driver that the TCPC has been reset, and any stored state from
+ * the chip should therefore be gathered again.  This should be called when
+ * board_reset_pd_mcu is called after init time.
+ *
+ * @param port	USB-C port number which has been reset
+ */
+void nct38xx_reset_notify(int port);
+
 extern const struct ioexpander_drv nct38xx_ioexpander_drv;
 
 #endif /* defined(__CROS_EC_USB_PD_TCPM_NCT38XX_H) */
diff --git a/driver/tcpm/ps8xxx.c b/driver/tcpm/ps8xxx.c
index 9fb6d31544..c380193237 100644
--- a/driver/tcpm/ps8xxx.c
+++ b/driver/tcpm/ps8xxx.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,6 +8,7 @@
  *
  * Supported TCPCs:
  * - PS8705
+ * - PS8745
  * - PS8751
  * - PS8755
  * - PS8805
@@ -17,13 +18,14 @@
 #include "common.h"
 #include "console.h"
 #include "ps8xxx.h"
-#include "tcpci.h"
-#include "tcpm.h"
+#include "tcpm/tcpci.h"
+#include "tcpm/tcpm.h"
 #include "timer.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
 
-#if !defined(CONFIG_USB_PD_TCPM_PS8705) && \
+#if !defined(CONFIG_USB_PD_TCPM_PS8705) &&     \
+	!defined(CONFIG_USB_PD_TCPM_PS8745) && \
 	!defined(CONFIG_USB_PD_TCPM_PS8751) && \
 	!defined(CONFIG_USB_PD_TCPM_PS8755) && \
 	!defined(CONFIG_USB_PD_TCPM_PS8805) && \
@@ -31,8 +33,7 @@
 #error "Unsupported PS8xxx TCPC."
 #endif
 
-#if !defined(CONFIG_USB_PD_TCPM_TCPCI) || \
-	!defined(CONFIG_USB_PD_TCPM_MUX) || \
+#if !defined(CONFIG_USB_PD_TCPM_TCPCI) || !defined(CONFIG_USB_PD_TCPM_MUX) || \
 	!defined(CONFIG_USBC_SS_MUX)
 
 #error "PS8XXX is using a standard TCPCI interface with integrated mux control"
@@ -48,8 +49,17 @@
 
 #endif /* CONFIG_USB_PD_TCPM_PS8751 */
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#ifdef CONFIG_USB_PD_TCPM_PS8751_CUSTOM_MUX_DRIVER
+#if !defined(CONFIG_USB_PD_TCPM_PS8751)
+#error "Custom MUX driver is available only for PS8751"
+#endif
+
+#endif /* CONFIG_USB_PD_TCPM_PS8751_CUSTOM_MUX_DRIVER */
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+#define PS8XXX_I2C_RECOVERY_DELAY_MS 10
 
 /*
  * The product_id per ports here is expected to be set in callback function -
@@ -60,13 +70,32 @@
  */
 static uint16_t product_id[CONFIG_USB_PD_PORT_MAX_COUNT];
 
+/*
+ * Revisions A1 and A0 of the PS8815 can corrupt the transmit buffer when
+ * updating the transmit buffer within 1ms of writing the ROLE_CONTROL
+ * register. When this version of silicon is detected, add a 1ms delay before
+ * all writes to the transmit buffer.
+ *
+ * See b/171430855 for details.
+ */
+static uint8_t ps8xxx_role_control_delay_ms[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+/*
+ * b/178664884, on PS8815, firmware revision 0x10 and older can report an
+ * incorrect value on the the CC lines. This flag controls when to apply
+ * the workaround.
+ */
+static bool ps8815_disable_rp_detect[CONFIG_USB_PD_PORT_MAX_COUNT];
+static bool ps8815_disconnected[CONFIG_USB_PD_PORT_MAX_COUNT];
 /*
  * timestamp of the next possible toggle to ensure the 2-ms spacing
  * between IRQ_HPD.
  */
 static uint64_t hpd_deadline[CONFIG_USB_PD_PORT_MAX_COUNT];
 
-#if defined(CONFIG_USB_PD_TCPM_PS8705) || \
+void ps8xxx_wake_from_standby(const struct usb_mux *me);
+
+#if defined(CONFIG_USB_PD_TCPM_PS8705) ||     \
 	defined(CONFIG_USB_PD_TCPM_PS8751) || \
 	defined(CONFIG_USB_PD_TCPM_PS8755) || \
 	defined(CONFIG_USB_PD_TCPM_PS8805)
@@ -94,7 +123,7 @@ static int ps8xxx_addr_dci_disable(int port, int i2c_addr, int i2c_reg)
 }
 #endif /* CONFIG_USB_PD_TCPM_PS875[15] || CONFIG_USB_PD_TCPM_PS8[78]05 */
 
-#if defined(CONFIG_USB_PD_TCPM_PS8705) || \
+#if defined(CONFIG_USB_PD_TCPM_PS8705) ||     \
 	defined(CONFIG_USB_PD_TCPM_PS8755) || \
 	defined(CONFIG_USB_PD_TCPM_PS8805)
 static int ps8705_dci_disable(int port)
@@ -138,13 +167,65 @@ static int ps8751_dci_disable(int port)
 }
 #endif /* CONFIG_USB_PD_TCPM_PS8751 */
 
-#ifdef CONFIG_USB_PD_TCPM_PS8815
+#if defined(CONFIG_USB_PD_TCPM_PS8815) || defined(CONFIG_USB_PD_TCPM_PS8745)
 static int ps8815_dci_disable(int port)
 {
-	/* DCI is disabled on the ps8815 */
+	/* DCI is disabled on the ps8815 and ps8745 */
 	return EC_SUCCESS;
 }
-#endif /* CONFIG_USB_PD_TCPM_PS8815 */
+#endif /* CONFIG_USB_PD_TCPM_PS8815 || CONFIG_USB_PD_TCPM_PS8745 */
+
+#ifdef CONFIG_USB_PD_TCPM_PS8805
+static int ps8805_gpio_mask[] = {
+	PS8805_REG_GPIO_0,
+	PS8805_REG_GPIO_1,
+	PS8805_REG_GPIO_2,
+};
+
+int ps8805_gpio_set_level(int port, enum ps8805_gpio signal, int level)
+{
+	int rv;
+	int regval;
+	int mask;
+
+	if (signal >= PS8805_GPIO_NUM)
+		return EC_ERROR_INVAL;
+
+	rv = i2c_read8(tcpc_config[port].i2c_info.port,
+		       PS8805_VENDOR_DEFINED_I2C_ADDR, PS8805_REG_GPIO_CONTROL,
+		       &regval);
+	if (rv)
+		return rv;
+
+	mask = ps8805_gpio_mask[signal];
+	if (level)
+		regval |= mask;
+	else
+		regval &= ~mask;
+
+	return i2c_write8(tcpc_config[port].i2c_info.port,
+			  PS8805_VENDOR_DEFINED_I2C_ADDR,
+			  PS8805_REG_GPIO_CONTROL, regval);
+}
+
+int ps8805_gpio_get_level(int port, enum ps8805_gpio signal, int *level)
+{
+	int regval;
+	int rv;
+
+	if (signal >= PS8805_GPIO_NUM)
+		return EC_ERROR_INVAL;
+
+	rv = i2c_read8(tcpc_config[port].i2c_info.port,
+		       PS8805_VENDOR_DEFINED_I2C_ADDR, PS8805_REG_GPIO_CONTROL,
+		       &regval);
+	if (rv)
+		return rv;
+	*level = !!(regval & ps8805_gpio_mask[signal]);
+
+	return EC_SUCCESS;
+}
+#endif /* CONFIG_USB_PD_TCPM_PS8805 */
 
 enum ps8xxx_variant_regs {
 	REG_FIRST_INDEX = 0,
@@ -165,61 +246,55 @@ struct ps8xxx_variant_map {
  */
 static struct ps8xxx_variant_map variant_map[] = {
 #ifdef CONFIG_USB_PD_TCPM_PS8705
-	{
-		PS8705_PRODUCT_ID,
-		ps8705_dci_disable,
-		{
-		 [REG_FW_VER] = 0x82,
-		}
-	},
+	{ PS8705_PRODUCT_ID,
+	  ps8705_dci_disable,
+	  {
+		  [REG_FW_VER] = 0x82,
+	  } },
+#endif
+#ifdef CONFIG_USB_PD_TCPM_PS8745
+	{ PS8745_PRODUCT_ID, ps8815_dci_disable, { [REG_FW_VER] = 0x82 } },
 #endif
 #ifdef CONFIG_USB_PD_TCPM_PS8751
-	{
-		PS8751_PRODUCT_ID,
-		ps8751_dci_disable,
-		{
-			[REG_FW_VER] = 0x90,
-		}
-	},
+	{ PS8751_PRODUCT_ID,
+	  ps8751_dci_disable,
+	  {
+		  [REG_FW_VER] = 0x90,
+	  } },
 #endif
 #ifdef CONFIG_USB_PD_TCPM_PS8755
-	{
-		PS8755_PRODUCT_ID,
-		ps8705_dci_disable,
-		{
-			[REG_FW_VER] = 0x82,
-		}
-	},
+	{ PS8755_PRODUCT_ID,
+	  ps8705_dci_disable,
+	  {
+		  [REG_FW_VER] = 0x82,
+	  } },
 #endif
 #ifdef CONFIG_USB_PD_TCPM_PS8805
-	{
-		PS8805_PRODUCT_ID,
-		ps8705_dci_disable,
-		{
-			[REG_FW_VER] = 0x82,
-		}
-	},
+	{ PS8805_PRODUCT_ID,
+	  ps8705_dci_disable,
+	  {
+		  [REG_FW_VER] = 0x82,
+	  } },
 #endif
 #ifdef CONFIG_USB_PD_TCPM_PS8815
-	{
-		PS8815_PRODUCT_ID,
-		ps8815_dci_disable,
-		{
-			[REG_FW_VER] = 0x82,
-		}
-	},
+	{ PS8815_PRODUCT_ID,
+	  ps8815_dci_disable,
+	  {
+		  [REG_FW_VER] = 0x82,
+	  } },
 #endif
 };
 
 static int get_reg_by_product(const int port,
-				const enum ps8xxx_variant_regs reg)
+			      const enum ps8xxx_variant_regs reg)
 {
+	int i;
+
 	if (reg < REG_FIRST_INDEX || reg >= REG_MAX_COUNT)
 		return INT32_MAX;
 
-	for (int i = 0; i < ARRAY_SIZE(variant_map); i++) {
-		if (product_id[port] ==
-		      variant_map[i].product_id) {
+	for (i = 0; i < ARRAY_SIZE(variant_map); i++) {
+		if (product_id[port] == variant_map[i].product_id) {
 			return variant_map[i].reg_map[reg];
 		}
 	}
@@ -258,8 +333,8 @@ static int dp_set_irq(const struct usb_mux *me, int enable)
 	return mux_write(me, MUX_IN_HPD_ASSERTION_REG, reg);
 }
 
-__overridable
-uint16_t board_get_ps8xxx_product_id(int port)
+/* LCOV_EXCL_START */
+__overridable uint16_t board_get_ps8xxx_product_id(int port)
 {
 	/* Board supporting multiple chip sources in ps8xxx.c MUST override this
 	 * function to judge the real chip source for this board. For example,
@@ -271,6 +346,8 @@ uint16_t board_get_ps8xxx_product_id(int port)
 		return 0;
 	} else if (IS_ENABLED(CONFIG_USB_PD_TCPM_PS8705)) {
 		return PS8705_PRODUCT_ID;
+	} else if (IS_ENABLED(CONFIG_USB_PD_TCPM_PS8745)) {
+		return PS8745_PRODUCT_ID;
 	} else if (IS_ENABLED(CONFIG_USB_PD_TCPM_PS8751)) {
 		return PS8751_PRODUCT_ID;
 	} else if (IS_ENABLED(CONFIG_USB_PD_TCPM_PS8755)) {
@@ -284,11 +361,37 @@ uint16_t board_get_ps8xxx_product_id(int port)
 	CPRINTS("%s: Any new product id is not defined here?", __func__);
 	return 0;
 }
+/* LCOV_EXCL_STOP */
+
+bool check_ps8755_chip(int port)
+{
+	int val;
+	int p0_addr;
+	int status;
+	bool is_ps8755 = false;
+
+	p0_addr = PS8751_P3_TO_P0_FLAGS(tcpc_config[port].i2c_info.addr_flags);
+	status = tcpc_addr_read(port, p0_addr, PS8755_P0_REG_SM, &val);
+	if (status == EC_SUCCESS && val == PS8755_P0_REG_SM_VALUE)
+		is_ps8755 = true;
+
+	return is_ps8755;
+}
 
 void ps8xxx_tcpc_update_hpd_status(const struct usb_mux *me,
-				   int hpd_lvl, int hpd_irq)
+				   mux_state_t mux_state, bool *ack_required)
 {
 	int port = me->usb_port;
+	int hpd_lvl = (mux_state & USB_PD_MUX_HPD_LVL) ? 1 : 0;
+	int hpd_irq = (mux_state & USB_PD_MUX_HPD_IRQ) ? 1 : 0;
+
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
+	if (IS_ENABLED(CONFIG_USB_PD_TCPM_PS8751_CUSTOM_MUX_DRIVER) &&
+	    product_id[me->usb_port] == PS8751_PRODUCT_ID &&
+	    me->flags & USB_MUX_FLAG_NOT_TCPC)
+		ps8xxx_wake_from_standby(me);
 
 	dp_set_hpd(me, hpd_lvl);
 
@@ -311,26 +414,26 @@ static int ps8xxx_tcpc_bist_mode_2(int port)
 	int rv;
 
 	/* Generate BIST for 50ms. */
-	rv = tcpc_write(port,
-		PS8XXX_REG_BIST_CONT_MODE_BYTE0, PS8751_BIST_COUNTER_BYTE0);
-	rv |= tcpc_write(port,
-		PS8XXX_REG_BIST_CONT_MODE_BYTE1, PS8751_BIST_COUNTER_BYTE1);
-	rv |= tcpc_write(port,
-		PS8XXX_REG_BIST_CONT_MODE_BYTE2, PS8751_BIST_COUNTER_BYTE2);
+	rv = tcpc_write(port, PS8XXX_REG_BIST_CONT_MODE_BYTE0,
+			PS8751_BIST_COUNTER_BYTE0);
+	rv |= tcpc_write(port, PS8XXX_REG_BIST_CONT_MODE_BYTE1,
+			 PS8751_BIST_COUNTER_BYTE1);
+	rv |= tcpc_write(port, PS8XXX_REG_BIST_CONT_MODE_BYTE2,
+			 PS8751_BIST_COUNTER_BYTE2);
 
 	/* Auto stop */
 	rv |= tcpc_write(port, PS8XXX_REG_BIST_CONT_MODE_CTR, 0);
 
 	/* Start BIST MODE 2 */
-	rv |= tcpc_write(port, TCPC_REG_TRANSMIT, TCPC_TX_BIST_MODE_2);
+	rv |= tcpc_write(port, TCPC_REG_TRANSMIT, TCPCI_MSG_TX_BIST_MODE_2);
 
 	return rv;
 }
 
-static int ps8xxx_tcpm_transmit(int port, enum tcpm_transmit_type type,
-			uint16_t header, const uint32_t *data)
+static int ps8xxx_tcpm_transmit(int port, enum tcpci_msg_type type,
+				uint16_t header, const uint32_t *data)
 {
-	if (type == TCPC_TX_BIST_MODE_2)
+	if (type == TCPCI_MSG_TX_BIST_MODE_2)
 		return ps8xxx_tcpc_bist_mode_2(port);
 	else
 		return tcpci_tcpm_transmit(port, type, header, data);
@@ -351,7 +454,32 @@ static int ps8xxx_tcpm_release(int port)
 	return tcpci_tcpm_release(port);
 }
 
+static void ps8xxx_role_control_delay(int port)
+{
+	int delay;
+
+	delay = ps8xxx_role_control_delay_ms[port];
+	if (delay)
+		msleep(delay);
+}
+
 #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+static int ps8xxx_set_role_ctrl(int port, enum tcpc_drp drp,
+				enum tcpc_rp_value rp, enum tcpc_cc_pull pull)
+{
+	int rv;
+
+	rv = tcpci_set_role_ctrl(port, drp, rp, pull);
+
+	/*
+	 * b/171430855 delay 1 ms after ROLE_CONTROL updates to prevent
+	 * transmit buffer corruption
+	 */
+	ps8xxx_role_control_delay(port);
+
+	return rv;
+}
+
 static int ps8xxx_tcpc_drp_toggle(int port)
 {
 	int rv;
@@ -359,12 +487,19 @@ static int ps8xxx_tcpc_drp_toggle(int port)
 	int opposite_pull;
 
 	/*
-	 * Workaround for PS8805/PS8815, which can't restart Connection
+	 * Workaround for PS8805/PS8815/PS8745, which can't restart Connection
 	 * Detection if the partner already presents pull. Now starts with
 	 * the opposite pull. Check b/149570002.
 	 */
 	if (product_id[port] == PS8805_PRODUCT_ID ||
-	    product_id[port] == PS8815_PRODUCT_ID) {
+	    product_id[port] == PS8815_PRODUCT_ID ||
+	    product_id[port] == PS8745_PRODUCT_ID) {
+		if (ps8815_disable_rp_detect[port]) {
+			CPRINTS("TCPC%d: rearm Rp disable detect on connect",
+				port);
+			ps8815_disconnected[port] = true;
+		}
+
 		/* Check CC_STATUS for the current pull */
 		rv = tcpc_read(port, TCPC_REG_CC_STATUS, &status);
 		if (status & TCPC_REG_CC_STATUS_CONNECT_RESULT_MASK) {
@@ -376,7 +511,8 @@ static int ps8xxx_tcpc_drp_toggle(int port)
 		}
 
 		/* Set auto drp toggle, starting with the opposite pull */
-		rv |= tcpci_set_role_ctrl(port, 1, TYPEC_RP_USB, opposite_pull);
+		rv |= ps8xxx_set_role_ctrl(port, TYPEC_DRP, TYPEC_RP_USB,
+					   opposite_pull);
 
 		/* Set Look4Connection command */
 		rv |= tcpc_write(port, TCPC_REG_COMMAND,
@@ -389,6 +525,40 @@ static int ps8xxx_tcpc_drp_toggle(int port)
 }
 #endif
 
+#ifdef CONFIG_USB_PD_TCPM_PS8805_FORCE_DID
+static int ps8805_make_device_id(int port, int *id, int live)
+{
+	static int cached_chip_revision[CONFIG_USB_PD_PORT_MAX_COUNT];
+	static bool cache_valid[CONFIG_USB_PD_PORT_MAX_COUNT];
+	int p0_addr;
+	int val;
+	int status;
+
+	if (live || !cache_valid[port]) {
+		p0_addr = PS8751_P3_TO_P0_FLAGS(
+			tcpc_config[port].i2c_info.addr_flags);
+		status = tcpc_addr_read(port, p0_addr,
+					PS8805_P0_REG_CHIP_REVISION, &val);
+		if (status != EC_SUCCESS)
+			return status;
+		cached_chip_revision[port] = val;
+		cache_valid[port] = true;
+	}
+
+	switch (cached_chip_revision[port] & 0xF0) {
+	case 0x00: /* A2 chip */
+		*id = 1;
+		break;
+	case 0xa0: /* A3 chip */
+		*id = 2;
+		break;
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+	return EC_SUCCESS;
+}
+#endif
+
 #ifdef CONFIG_USB_PD_TCPM_PS8815_FORCE_DID
 /*
  * Early ps8815 A1 firmware reports 0x0001 in the TCPCI Device ID
@@ -397,27 +567,40 @@ static int ps8xxx_tcpc_drp_toggle(int port)
  * identify the chip as A1.
  *
  * See b/159289062.
+ *
+ * The ps8815 A2 reports device ID 0x0001 instead of 0x0003 when the
+ * firmware is bad (mis-programmed).
  */
-static int ps8815_make_device_id(int port, int *id)
+static int ps8815_make_device_id(int port, int *id, int live)
 {
+	static int cached_hw_revision[CONFIG_USB_PD_PORT_MAX_COUNT];
+	static bool cache_valid[CONFIG_USB_PD_PORT_MAX_COUNT];
 	int p1_addr;
 	int val;
 	int status;
 
-	/* P1 registers are always accessible on PS8815 */
-	p1_addr = PS8751_P3_TO_P1_FLAGS(tcpc_config[port].i2c_info.addr_flags);
+	if (live || !cache_valid[port]) {
+		/* P1 registers are always accessible on PS8815 */
+		p1_addr = PS8751_P3_TO_P1_FLAGS(
+			tcpc_config[port].i2c_info.addr_flags);
+		status = tcpc_addr_read16(port, p1_addr,
+					  PS8815_P1_REG_HW_REVISION, &val);
+		if (status != EC_SUCCESS)
+			return status;
+		cached_hw_revision[port] = val;
+		cache_valid[port] = true;
+	}
 
-	status = tcpc_addr_read16(port, p1_addr, PS8815_P1_REG_HW_REVISION,
-				  &val);
-	if (status != EC_SUCCESS)
-		return status;
-	switch (val) {
+	switch (cached_hw_revision[port]) {
 	case 0x0a00:
 		*id = 1;
 		break;
 	case 0x0a01:
 		*id = 2;
 		break;
+	case 0x0a02:
+		*id = 3;
+		break;
 	default:
 		return EC_ERROR_UNKNOWN;
 	}
@@ -425,9 +608,100 @@ static int ps8815_make_device_id(int port, int *id)
 }
 #endif
 
+#ifdef CONFIG_USB_PD_TCPM_PS8745_FORCE_ID
+/*
+ * Some PS8745 firmwares report the same product/device ID and chip rev as
+ * PS8815-A2. This function probes vendor-specific registers to determine
+ * whether the device is a PS8815 or PS8745 and updates the IDs pointed to by
+ * the parameters to be the correct IDs for the detected chip.
+ *
+ * See b/236761058 and the PS8xxx TCPC Family Chip Revision Guide (v0.2)
+ */
+static int ps8745_make_device_id(int port, uint16_t *pid, uint16_t *did,
+				 int live)
+{
+	static int cached_reg_id[CONFIG_USB_PD_PORT_MAX_COUNT];
+	static bool cache_valid[CONFIG_USB_PD_PORT_MAX_COUNT];
+	int status;
+	int val;
+
+	if (live || !cache_valid[port]) {
+		status = tcpc_addr_read(
+			port,
+			PS8751_P3_TO_P0_FLAGS(
+				tcpc_config[port].i2c_info.addr_flags),
+			PS8815_P0_REG_ID, &val);
+		if (status != EC_SUCCESS)
+			return status;
+		cached_reg_id[port] = val;
+		cache_valid[port] = true;
+	}
+
+	if (*pid == PS8815_PRODUCT_ID && (cached_reg_id[port] & BIT(1)) != 0) {
+		/* PS8815 with this bit set is actually PS8745 */
+		*pid = PS8745_PRODUCT_ID;
+	}
+
+	if (*pid == PS8745_PRODUCT_ID && *did == 0x0003) {
+		/*
+		 * Some versions report the correct product ID but the
+		 * device ID is still for PS8815-A2.
+		 */
+		*did = 0x0006;
+	}
+
+	return EC_SUCCESS;
+}
+#endif
+
+/*
+ * The ps8815 can take up to 50ms (FW_INIT_DELAY_MS) to fully wake up
+ * from sleep/low power mode - specially when it contains an application
+ * block firmware update. When the chip is asleep, the 1st I2C
+ * transaction will fail but the chip will begin to wake up within 10ms
+ * (I2C_RECOVERY_DELAY_MS). After this delay, I2C transactions succeed,
+ * but the firmware is still not fully operational. The way to check if
+ * the firmware is ready, is to poll the firmware register for a
+ * non-zero value. This logic applies to all ps8xxx family members
+ * supported by this driver.
+ */
+
+static int ps8xxx_lpm_recovery_delay(int port)
+{
+	int val;
+	int status;
+	int fw_reg;
+	timestamp_t deadline;
+
+	fw_reg = get_reg_by_product(port, REG_FW_VER);
+
+	deadline = get_time();
+	deadline.val += PS8815_FW_INIT_DELAY_MS * 1000;
+
+	val = 0;
+	for (;;) {
+		if (timestamp_expired(deadline, NULL))
+			return EC_ERROR_TIMEOUT;
+
+		status = tcpc_read(port, fw_reg, &val);
+		if (status != EC_SUCCESS) {
+			/* wait for chip to wake up */
+			msleep(PS8XXX_I2C_RECOVERY_DELAY_MS);
+			continue;
+		}
+		if (val != 0)
+			break;
+		msleep(1);
+	}
+
+	return EC_SUCCESS;
+}
+
 static int ps8xxx_get_chip_info(int port, int live,
-			struct ec_response_pd_chip_info_v1 *chip_info)
+				struct ec_response_pd_chip_info_v1 *chip_info)
 {
+	static int cached_fw_version[CONFIG_USB_PD_PORT_MAX_COUNT];
+	static bool cache_valid[CONFIG_USB_PD_PORT_MAX_COUNT];
 	int val;
 	int reg;
 	int rv = tcpci_get_chip_info(port, live, chip_info);
@@ -435,36 +709,68 @@ static int ps8xxx_get_chip_info(int port, int live,
 	if (rv != EC_SUCCESS)
 		return rv;
 
+	if (chip_info == NULL)
+		return EC_SUCCESS;
+
 	if (!live) {
-		product_id[port] = board_get_ps8xxx_product_id(port);
+		uint16_t pid;
+
+		pid = board_get_ps8xxx_product_id(port);
+		if (pid == 0)
+			return EC_ERROR_UNKNOWN;
+		product_id[port] = pid;
 		chip_info->vendor_id = PS8XXX_VENDOR_ID;
 		chip_info->product_id = product_id[port];
 	}
 
-	if (chip_info->fw_version_number == 0 ||
-	    chip_info->fw_version_number == -1 || live) {
+#ifdef CONFIG_USB_PD_TCPM_PS8745_FORCE_ID
+	/* device ID 3 is PS8815 and might be misreported */
+	if (chip_info->product_id == PS8815_PRODUCT_ID ||
+	    chip_info->device_id == 0x0003) {
+		uint16_t pid = chip_info->product_id;
+		uint16_t did = chip_info->device_id;
+
+		rv = ps8745_make_device_id(port, &pid, &did, live);
+		chip_info->product_id = pid;
+		chip_info->device_id = did;
+		if (rv != EC_SUCCESS)
+			return rv;
+	}
+#endif
+#ifdef CONFIG_USB_PD_TCPM_PS8805_FORCE_DID
+	if (chip_info->product_id == PS8805_PRODUCT_ID &&
+	    chip_info->device_id == 0x0001) {
+		rv = ps8805_make_device_id(port, &val, live);
+		if (rv != EC_SUCCESS)
+			return rv;
+		chip_info->device_id = val;
+	}
+#endif
 #ifdef CONFIG_USB_PD_TCPM_PS8815_FORCE_DID
-		if (chip_info->product_id == PS8815_PRODUCT_ID &&
-		    chip_info->device_id == 0x0001) {
-			rv = ps8815_make_device_id(port, &val);
-			if (rv != EC_SUCCESS)
-				return rv;
-			chip_info->device_id = val;
-		}
+	if (chip_info->product_id == PS8815_PRODUCT_ID &&
+	    chip_info->device_id == 0x0001) {
+		rv = ps8815_make_device_id(port, &val, live);
+		if (rv != EC_SUCCESS)
+			return rv;
+		chip_info->device_id = val;
+	}
 #endif
+
+	if (live || !cache_valid[port]) {
 		reg = get_reg_by_product(port, REG_FW_VER);
 		rv = tcpc_read(port, reg, &val);
 		if (rv != EC_SUCCESS)
 			return rv;
-
-		chip_info->fw_version_number = val;
+		cached_fw_version[port] = val;
+		cache_valid[port] = true;
 	}
+	chip_info->fw_version_number = cached_fw_version[port];
 
 	/* Treat unexpected values as error (FW not initiated from reset) */
-	if (live && (
-	    chip_info->vendor_id != PS8XXX_VENDOR_ID ||
-	    chip_info->product_id != board_get_ps8xxx_product_id(port) ||
-	    chip_info->fw_version_number == 0))
+	if (live &&
+	    (chip_info->vendor_id != PS8XXX_VENDOR_ID ||
+	     chip_info->product_id != board_get_ps8xxx_product_id(port) ||
+	     chip_info->fw_version_number == 0))
 		return EC_ERROR_UNKNOWN;
 
 #if defined(CONFIG_USB_PD_TCPM_PS8751) && \
@@ -483,20 +789,41 @@ static int ps8xxx_get_chip_info(int port, int live,
 static int ps8xxx_enter_low_power_mode(int port)
 {
 	/*
-	 * PS8751 has the auto sleep function that enters low power mode on
-	 * its own in ~2 seconds. Other chips don't have it. Stub it out for
-	 * PS8751.
+	 * PS8751/PS8815/PS8745 has the auto sleep function that enters
+	 * low power mode on its own in ~2 seconds. Other chips
+	 * don't have it. Stub it out for PS8751/PS8815.
 	 */
-	if (IS_ENABLED(CONFIG_USB_PD_TCPM_PS8751))
+	if (product_id[port] == PS8751_PRODUCT_ID ||
+	    product_id[port] == PS8815_PRODUCT_ID ||
+	    product_id[port] == PS8745_PRODUCT_ID)
 		return EC_SUCCESS;
 
 	return tcpci_enter_low_power_mode(port);
 }
 #endif
 
+__maybe_unused static int ps8815_tcpc_fast_role_swap_enable(int port,
+							    int enable)
+{
+	int status;
+
+	if (!tcpm_tcpc_has_frs_control(port))
+		return EC_SUCCESS;
+
+	status = tcpc_update8(port, PS8815_REG_RESERVED_F4,
+			      PS8815_REG_RESERVED_F4_FRS_EN,
+			      enable ? MASK_SET : MASK_CLR);
+	if (status != EC_SUCCESS)
+		return status;
+
+	return tcpci_tcpc_fast_role_swap_enable(port, enable);
+}
+
 static int ps8xxx_dci_disable(int port)
 {
-	for (int i = 0; i < ARRAY_SIZE(variant_map); i++) {
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(variant_map); i++) {
 		if (product_id[port] == variant_map[i].product_id)
 			return variant_map[i].dci_disable_ptr(port);
 	}
@@ -505,12 +832,109 @@ static int ps8xxx_dci_disable(int port)
 	return EC_ERROR_INVAL;
 }
 
+__maybe_unused static int ps8815_transmit_buffer_workaround_check(int port)
+{
+	int p1_addr;
+	int val;
+	int status;
+
+	if (product_id[port] != PS8815_PRODUCT_ID)
+		return EC_SUCCESS;
+
+	/* P1 registers are always accessible on PS8815 */
+	p1_addr = PS8751_P3_TO_P1_FLAGS(tcpc_config[port].i2c_info.addr_flags);
+
+	status = tcpc_addr_read16(port, p1_addr, PS8815_P1_REG_HW_REVISION,
+				  &val);
+	if (status != EC_SUCCESS)
+		return status;
+
+	switch (val) {
+	case 0x0a00:
+	case 0x0a01:
+		ps8xxx_role_control_delay_ms[port] = 1;
+		break;
+	default:
+		ps8xxx_role_control_delay_ms[port] = 0;
+		break;
+	}
+
+	return EC_SUCCESS;
+}
+
+__maybe_unused static int ps8815_disable_rp_detect_workaround_check(int port)
+{
+	int val;
+	int rv;
+	int reg;
+
+	ps8815_disable_rp_detect[port] = false;
+	ps8815_disconnected[port] = true;
+
+	if (product_id[port] != PS8815_PRODUCT_ID)
+		return EC_SUCCESS;
+
+	reg = get_reg_by_product(port, REG_FW_VER);
+	rv = tcpc_read(port, reg, &val);
+	if (rv != EC_SUCCESS)
+		return rv;
+
+	/*
+	 * RP detect is a problem in firmware version 0x10 and older.
+	 */
+	if (val <= 0x10)
+		ps8815_disable_rp_detect[port] = true;
+
+	return EC_SUCCESS;
+}
+
+__overridable void board_ps8xxx_tcpc_init(int port)
+{
+}
+
 static int ps8xxx_tcpm_init(int port)
 {
 	int status;
 
 	product_id[port] = board_get_ps8xxx_product_id(port);
 
+	status = ps8xxx_lpm_recovery_delay(port);
+	if (status != EC_SUCCESS) {
+		CPRINTS("C%d: init: LPM recovery failed", port);
+		return status;
+	}
+
+	if (IS_ENABLED(CONFIG_USB_PD_TCPM_PS8815)) {
+		status = ps8815_transmit_buffer_workaround_check(port);
+		if (status != EC_SUCCESS)
+			return status;
+		status = ps8815_disable_rp_detect_workaround_check(port);
+		if (status != EC_SUCCESS)
+			return status;
+	}
+
+	if (IS_ENABLED(CONFIG_USB_PD_TCPM_PS8745) ||
+	    IS_ENABLED(CONFIG_USB_PD_TCPM_PS8815)) {
+		/*
+		 * NOTE(b/183127346): Enable FRS sequence:
+		 *
+		 *  one-time chip config:
+		 *    set reg 0xd1.FRS_EN: enable FRS without waiting for CC
+		 *  on FRS device detect:
+		 *    set reg POWER_CTRL.FRS_ENABLE
+		 *    set reg 0xf4.FRS_EN (drive FRS GPIO to PPC)
+		 */
+		if (tcpm_tcpc_has_frs_control(port)) {
+			status = tcpc_update8(port, PS8815_REG_RESERVED_D1,
+					      PS8815_REG_RESERVED_D1_FRS_EN,
+					      MASK_SET);
+			if (status != EC_SUCCESS)
+				return status;
+		}
+	}
+
+	board_ps8xxx_tcpc_init(port);
+
 	status = tcpci_tcpm_init(port);
 	if (status != EC_SUCCESS)
 		return status;
@@ -536,7 +960,7 @@ static int ps8xxx_tcpm_init(int port)
  * delay will allow the transient to disappear.
  */
 static int ps8751_get_gcc(int port, enum tcpc_cc_voltage_status *cc1,
-			 enum tcpc_cc_voltage_status *cc2)
+			  enum tcpc_cc_voltage_status *cc2)
 {
 	int rv;
 	int status;
@@ -551,8 +975,40 @@ static int ps8751_get_gcc(int port, enum tcpc_cc_voltage_status *cc1,
 }
 #endif
 
+static int ps8xxx_tcpm_set_cc(int port, int pull)
+{
+	int rv;
+
+	/*
+	 * b/178664884: Before presenting Rp on initial connect, disable
+	 * internal function that checks Rp value. This is a workaround
+	 * in the PS8815 firmware that reports an incorrect value on the CC
+	 * lines.
+	 *
+	 * The PS8815 self-clears these bits.
+	 */
+	if (ps8815_disable_rp_detect[port] && ps8815_disconnected[port] &&
+	    pull == TYPEC_CC_RP) {
+		CPRINTS("TCPC%d: disable chip based Rp detect on connection",
+			port);
+		tcpc_write(port, PS8XXX_REG_RP_DETECT_CONTROL,
+			   RP_DETECT_DISABLE);
+		ps8815_disconnected[port] = false;
+	}
+
+	rv = tcpci_tcpm_set_cc(port, pull);
+
+	/*
+	 * b/171430855 delay 1 ms after ROLE_CONTROL updates to prevent
+	 * transmit buffer corruption
+	 */
+	ps8xxx_role_control_delay(port);
+
+	return rv;
+}
+
 static int ps8xxx_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-			 enum tcpc_cc_voltage_status *cc2)
+			      enum tcpc_cc_voltage_status *cc2)
 {
 #ifdef CONFIG_USB_PD_TCPM_PS8751
 	if (product_id[port] == PS8751_PRODUCT_ID)
@@ -562,38 +1018,59 @@ static int ps8xxx_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
 	return tcpci_tcpm_get_cc(port, cc1, cc2);
 }
 
+static int ps8xxx_tcpm_set_vconn(int port, int enable)
+{
+	/*
+	 * Add delay of writing TCPC_REG_POWER_CTRL makes
+	 * CC status being judged correctly when disable VCONN.
+	 * This may be a PS8XXX firmware issue, Parade is still trying.
+	 * https://partnerissuetracker.corp.google.com/issues/185202064
+	 */
+	if (!enable)
+		msleep(PS8XXX_VCONN_TURN_OFF_DELAY_US);
+
+	return tcpci_tcpm_set_vconn(port, enable);
+}
+
 const struct tcpm_drv ps8xxx_tcpm_drv = {
-	.init			= &ps8xxx_tcpm_init,
-	.release		= &ps8xxx_tcpm_release,
-	.get_cc			= &ps8xxx_tcpm_get_cc,
+	.init = ps8xxx_tcpm_init,
+	.release = ps8xxx_tcpm_release,
+	.get_cc = ps8xxx_tcpm_get_cc,
 #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	.check_vbus_level	= &tcpci_tcpm_check_vbus_level,
+	.check_vbus_level = tcpci_tcpm_check_vbus_level,
+#endif
+#ifdef CONFIG_USB_PD_VBUS_MEASURE_TCPC
+	.get_vbus_voltage = tcpci_get_vbus_voltage,
 #endif
-	.select_rp_value	= &tcpci_tcpm_select_rp_value,
-	.set_cc			= &tcpci_tcpm_set_cc,
-	.set_polarity		= &tcpci_tcpm_set_polarity,
+	.select_rp_value = tcpci_tcpm_select_rp_value,
+	.set_cc = ps8xxx_tcpm_set_cc,
+	.set_polarity = tcpci_tcpm_set_polarity,
 #ifdef CONFIG_USB_PD_DECODE_SOP
-	.sop_prime_disable	= &tcpci_tcpm_sop_prime_disable,
+	.sop_prime_enable = tcpci_tcpm_sop_prime_enable,
 #endif
-	.set_vconn		= &tcpci_tcpm_set_vconn,
-	.set_msg_header		= &tcpci_tcpm_set_msg_header,
-	.set_rx_enable		= &tcpci_tcpm_set_rx_enable,
-	.get_message_raw	= &tcpci_tcpm_get_message_raw,
-	.transmit		= &ps8xxx_tcpm_transmit,
-	.tcpc_alert		= &tcpci_tcpc_alert,
+	.set_vconn = ps8xxx_tcpm_set_vconn,
+	.set_msg_header = tcpci_tcpm_set_msg_header,
+	.set_rx_enable = tcpci_tcpm_set_rx_enable,
+	.get_message_raw = tcpci_tcpm_get_message_raw,
+	.transmit = ps8xxx_tcpm_transmit,
+	.tcpc_alert = tcpci_tcpc_alert,
 #ifdef CONFIG_USB_PD_DISCHARGE_TCPC
-	.tcpc_discharge_vbus	= &tcpci_tcpc_discharge_vbus,
+	.tcpc_discharge_vbus = tcpci_tcpc_discharge_vbus,
 #endif
 #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-	.drp_toggle		= &ps8xxx_tcpc_drp_toggle,
+	.drp_toggle = ps8xxx_tcpc_drp_toggle,
 #endif
-#ifdef CONFIG_USBC_PPC
-	.set_snk_ctrl		= &tcpci_tcpm_set_snk_ctrl,
-	.set_src_ctrl		= &tcpci_tcpm_set_src_ctrl,
-#endif
-	.get_chip_info		= &ps8xxx_get_chip_info,
+	.get_chip_info = ps8xxx_get_chip_info,
+	.set_snk_ctrl = tcpci_tcpm_set_snk_ctrl,
+	.set_src_ctrl = tcpci_tcpm_set_src_ctrl,
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	.enter_low_power_mode	= &ps8xxx_enter_low_power_mode,
+	.enter_low_power_mode = ps8xxx_enter_low_power_mode,
+#endif
+	.set_bist_test_mode = tcpci_set_bist_test_mode,
+	.get_bist_test_mode = &tcpci_get_bist_test_mode,
+#if defined(CONFIG_USB_PD_FRS) && (defined(CONFIG_USB_PD_TCPM_PS8815) || \
+				   defined(CONFIG_USB_PD_TCPM_PS8745))
+	.set_frs_enable = ps8815_tcpc_fast_role_swap_enable,
 #endif
 };
 
@@ -604,7 +1081,104 @@ struct i2c_stress_test_dev ps8xxx_i2c_stress_test_dev = {
 		.read_val = PS8XXX_VENDOR_ID & 0xFF,
 		.write_reg = MUX_IN_HPD_ASSERTION_REG,
 	},
-	.i2c_read = &tcpc_i2c_read,
-	.i2c_write = &tcpc_i2c_write,
+	.i2c_read = tcpc_i2c_read,
+	.i2c_write = tcpc_i2c_write,
 };
 #endif /* CONFIG_CMD_I2C_STRESS_TEST_TCPC */
+
+#ifdef CONFIG_USB_PD_TCPM_PS8751_CUSTOM_MUX_DRIVER
+
+static int ps8xxx_mux_init(const struct usb_mux *me)
+{
+	RETURN_ERROR(tcpci_tcpm_mux_init(me));
+
+	/* If this MUX is also the TCPC, then skip init */
+	if (!(me->flags & USB_MUX_FLAG_NOT_TCPC))
+		return EC_SUCCESS;
+
+	product_id[me->usb_port] = board_get_ps8xxx_product_id(me->usb_port);
+
+	return EC_SUCCESS;
+}
+
+/*
+ * PS8751 goes to standby mode automatically when both CC lines are set to RP.
+ * In standby mode it doesn't respond to first I2C access, but next
+ * transactions are working fine (until it goes to sleep again).
+ *
+ * To wake device documentation recommends read content of 0xA0 register.
+ */
+void ps8xxx_wake_from_standby(const struct usb_mux *me)
+{
+	int reg;
+
+	/* Since we are waking up device, this call will most likely fail */
+	mux_read(me, PS8XXX_REG_I2C_DEBUGGING_ENABLE, &reg);
+	msleep(10);
+}
+
+static int ps8xxx_mux_set(const struct usb_mux *me, mux_state_t mux_state,
+			  bool *ack_required)
+{
+	/* This driver treats safe mode as none */
+	if (mux_state & USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
+
+	if (product_id[me->usb_port] == PS8751_PRODUCT_ID &&
+	    me->flags & USB_MUX_FLAG_NOT_TCPC) {
+		ps8xxx_wake_from_standby(me);
+
+		/*
+		 * To operate properly, when working as mux only, PS8751 CC
+		 * lines needs to be RD all the time. Changing to RP after
+		 * setting mux breaks SuperSpeed connection.
+		 */
+		if (mux_state != USB_PD_MUX_NONE)
+			RETURN_ERROR(
+				mux_write(me, TCPC_REG_ROLE_CTRL,
+					  TCPC_REG_ROLE_CTRL_SET(
+						  TYPEC_NO_DRP, TYPEC_RP_USB,
+						  TYPEC_CC_RD, TYPEC_CC_RD)));
+	}
+
+	return tcpci_tcpm_mux_set(me, mux_state, ack_required);
+}
+
+static int ps8xxx_mux_get(const struct usb_mux *me, mux_state_t *mux_state)
+{
+	if (product_id[me->usb_port] == PS8751_PRODUCT_ID &&
+	    me->flags & USB_MUX_FLAG_NOT_TCPC)
+		ps8xxx_wake_from_standby(me);
+
+	return tcpci_tcpm_mux_get(me, mux_state);
+}
+
+static int ps8xxx_mux_enter_low_power(const struct usb_mux *me)
+{
+	/*
+	 * Set PS8751 lines to RP. This allows device to standby
+	 * automatically after ~2 seconds
+	 */
+	if (product_id[me->usb_port] == PS8751_PRODUCT_ID &&
+	    me->flags & USB_MUX_FLAG_NOT_TCPC) {
+		/*
+		 * It may happen that this write will fail, but
+		 * RP seems to be set correctly
+		 */
+		mux_write(me, TCPC_REG_ROLE_CTRL,
+			  TCPC_REG_ROLE_CTRL_SET(TYPEC_NO_DRP, TYPEC_RP_USB,
+						 TYPEC_CC_RP, TYPEC_CC_RP));
+		return EC_SUCCESS;
+	}
+
+	return tcpci_tcpm_mux_enter_low_power(me);
+}
+
+const struct usb_mux_driver ps8xxx_usb_mux_driver = {
+	.init = ps8xxx_mux_init,
+	.set = ps8xxx_mux_set,
+	.get = ps8xxx_mux_get,
+	.enter_low_power_mode = ps8xxx_mux_enter_low_power,
+};
+
+#endif /* CONFIG_USB_PD_TCPM_PS8751_CUSTOM_MUX_DRIVER */
diff --git a/driver/tcpm/ps8xxx.h b/driver/tcpm/ps8xxx.h
index 788e2f2655..ed3197c822 100644
--- a/driver/tcpm/ps8xxx.h
+++ b/driver/tcpm/ps8xxx.h
@@ -1,7 +1,8 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
+#include "driver/tcpm/ps8xxx_public.h"
 #include "usb_mux.h"
 
 /* Parade Tech Type-C port controller */
@@ -9,114 +10,152 @@
 #ifndef __CROS_EC_USB_PD_TCPM_PS8XXX_H
 #define __CROS_EC_USB_PD_TCPM_PS8XXX_H
 
-/* I2C interface */
-#define PS8751_I2C_ADDR1_P1_FLAGS 0x09
-#define PS8751_I2C_ADDR1_P2_FLAGS 0x0A
-#define PS8751_I2C_ADDR1_FLAGS    0x0B	/* P3 */
-#define PS8751_I2C_ADDR2_FLAGS    0x1B
-#define PS8751_I2C_ADDR3_FLAGS    0x2B
-#define PS8751_I2C_ADDR4_FLAGS    0x4B
+#define PS8751_P3_TO_P0_FLAGS(p3_flags) ((p3_flags)-3)
+#define PS8751_P3_TO_P1_FLAGS(p3_flags) ((p3_flags)-2)
 
-#define PS8751_P3_TO_P1_FLAGS(p3_flags)	((p3_flags) - 2)
+#define PS8751_BIST_TIMER_FREQ 15000000
+#define PS8751_BIST_DELAY_MS 50
 
-/* Minimum Delay for reset assertion */
-#define PS8XXX_RESET_DELAY_MS 1
-
-/* Delay between releasing reset and the first I2C read */
-#define PS8805_FW_INIT_DELAY_MS 10
-
-/* Delay from power on to reset de-asserted */
-#define PS8815_PWR_H_RST_H_DELAY_MS 20
-/*
- * Delay between releasing reset and the first I2C read
- *
- * If the delay is too short, I2C fails.
- * If the delay is marginal I2C reads return garbage.
- *
- * With firmware 0x03:
- *   10ms is too short
- *   20ms is marginal
- *   25ms is OK
- */
-#define PS8815_FW_INIT_DELAY_MS 40
-
-#define PS8751_BIST_TIMER_FREQ  15000000
-#define PS8751_BIST_DELAY_MS    50
-
-#define PS8751_BIST_COUNTER (PS8751_BIST_TIMER_FREQ / MSEC \
-				* PS8751_BIST_DELAY_MS)
+#define PS8751_BIST_COUNTER \
+	(PS8751_BIST_TIMER_FREQ / MSEC * PS8751_BIST_DELAY_MS)
 
 #define PS8751_BIST_COUNTER_BYTE0 (PS8751_BIST_COUNTER & 0xff)
 #define PS8751_BIST_COUNTER_BYTE1 ((PS8751_BIST_COUNTER >> 8) & 0xff)
 #define PS8751_BIST_COUNTER_BYTE2 ((PS8751_BIST_COUNTER >> 16) & 0xff)
 
-#define PS8XXX_VENDOR_ID  0x1DA0
-#define PS8XXX_REG_I2C_DEBUGGING_ENABLE         0xA0
-#define PS8XXX_REG_I2C_DEBUGGING_ENABLE_ON      0x30
-#define PS8XXX_REG_I2C_DEBUGGING_ENABLE_OFF     0x31    /* default */
-#define PS8XXX_REG_BIST_CONT_MODE_BYTE0         0xBC
-#define PS8XXX_REG_BIST_CONT_MODE_BYTE1         0xBD
-#define PS8XXX_REG_BIST_CONT_MODE_BYTE2         0xBE
-#define PS8XXX_REG_BIST_CONT_MODE_CTR           0xBF
-#define PS8XXX_REG_DET_CTRL0                    0x08
-
-#define PS8XXX_REG_MUX_USB_DCI_CFG_MODE_MASK    0xC0
-#define PS8XXX_REG_MUX_USB_DCI_CFG_MODE_OFF     0x80
-
-#define MUX_IN_HPD_ASSERTION_REG                0xD0
-#define IN_HPD  BIT(0)
+#define PS8XXX_REG_RP_DETECT_CONTROL 0x9B
+#define RP_DETECT_DISABLE 0x30
+
+#define PS8XXX_REG_I2C_DEBUGGING_ENABLE 0xA0
+#define PS8XXX_REG_I2C_DEBUGGING_ENABLE_ON 0x30
+#define PS8XXX_REG_I2C_DEBUGGING_ENABLE_OFF 0x31 /* default */
+#define PS8XXX_REG_BIST_CONT_MODE_BYTE0 0xBC
+#define PS8XXX_REG_BIST_CONT_MODE_BYTE1 0xBD
+#define PS8XXX_REG_BIST_CONT_MODE_BYTE2 0xBE
+#define PS8XXX_REG_BIST_CONT_MODE_CTR 0xBF
+#define PS8XXX_REG_DET_CTRL0 0x08
+
+#define PS8XXX_REG_MUX_USB_DCI_CFG_MODE_MASK 0xC0
+#define PS8XXX_REG_MUX_USB_DCI_CFG_MODE_OFF 0x80
+
+#define MUX_IN_HPD_ASSERTION_REG 0xD0
+#define IN_HPD BIT(0)
 #define HPD_IRQ BIT(1)
 
-#define PS8XXX_P1_REG_MUX_USB_DCI_CFG           0x4B
+#define PS8XXX_P1_REG_MUX_USB_DCI_CFG 0x4B
 
-/* NOTE: The Product ID will read as 0x8803 if the firmware has malfunctioned in
- * 8705, 8755 and 8805.
- */
-#define PS8705_PRODUCT_ID 0x8705
-#define PS8751_PRODUCT_ID 0x8751
-#define PS8755_PRODUCT_ID 0x8755
-#define PS8805_PRODUCT_ID 0x8805
-#define PS8815_PRODUCT_ID 0x8815
+#define PS8755_P0_REG_SM 0x06
+#define PS8755_P0_REG_SM_VALUE 0x80
 
 #if defined(CONFIG_USB_PD_TCPM_PS8751)
 /* Vendor defined registers */
-#define PS8XXX_REG_VENDOR_ID_L                  0x00
-#define PS8XXX_REG_VENDOR_ID_H                  0x01
-#define PS8XXX_REG_MUX_DP_EQ_CONFIGURATION      0xD3
-#define PS8XXX_REG_MUX_DP_OUTPUT_CONFIGURATION  0xD4
-#define PS8XXX_REG_MUX_USB_C2SS_EQ              0xE7
-#define PS8XXX_REG_MUX_USB_C2SS_HS_THRESHOLD    0xE8
-#define PS8751_REG_MUX_USB_DCI_CFG              0xED
+#define PS8XXX_REG_VENDOR_ID_L 0x00
+#define PS8XXX_REG_VENDOR_ID_H 0x01
+#define PS8XXX_REG_MUX_DP_EQ_CONFIGURATION 0xD3
+#define PS8XXX_REG_MUX_DP_OUTPUT_CONFIGURATION 0xD4
+#define PS8XXX_REG_MUX_USB_C2SS_EQ 0xE7
+#define PS8XXX_REG_MUX_USB_C2SS_HS_THRESHOLD 0xE8
+#define PS8751_REG_MUX_USB_DCI_CFG 0xED
 #endif
 
-#if defined(CONFIG_USB_PD_TCPM_PS8815)
 /* Vendor defined registers */
-#define PS8815_P1_REG_HW_REVISION		0xF0
+#define PS8815_P1_REG_HW_REVISION 0xF0
 
-#endif
+/* Vendor defined registers */
+#define PS8815_REG_APTX_EQ_AT_10G 0x20
+#define PS8815_REG_RX_EQ_AT_10G 0x22
+#define PS8815_REG_APTX_EQ_AT_5G 0x24
+#define PS8815_REG_RX_EQ_AT_5G 0x26
+
+#define PS8815_REG_RESERVED_D1 0xD1
+#define PS8815_REG_RESERVED_D1_FRS_EN BIT(7)
+#define PS8815_REG_RESERVED_F4 0xF4
+#define PS8815_REG_RESERVED_F4_FRS_EN BIT(6)
+
+/*
+ * Below register is defined from Parade PS8815 Register Table,
+ * See b:189587527 for more detail.
+ */
 
-extern const struct tcpm_drv ps8xxx_tcpm_drv;
+/* Displayport related settings */
+#define PS8815_REG_DP_EQ_SETTING 0xF8
+#define PS8815_AUTO_EQ_DISABLE BIT(7)
+#define PS8815_DPEQ_LOSS_UP_21DB 0x09
+#define PS8815_DPEQ_LOSS_UP_20DB 0x08
+#define PS8815_DPEQ_LOSS_UP_19DB 0x07
+#define PS8815_DPEQ_LOSS_UP_18DB 0x06
+#define PS8815_DPEQ_LOSS_UP_17DB 0x05
+#define PS8815_DPEQ_LOSS_UP_16DB 0x04
+#define PS8815_DPEQ_LOSS_UP_13DB 0x03
+#define PS8815_DPEQ_LOSS_UP_12DB 0x02
+#define PS8815_DPEQ_LOSS_UP_10DB 0x01
+#define PS8815_DPEQ_LOSS_UP_9DB 0x00
+#define PS8815_REG_DP_EQ_COMP_SHIFT 3
+#define PS8815_AUX_INTERCEPTION_DISABLE BIT(1)
+
+/*
+ * PS8805 register to distinguish chip revision
+ * bit 7-4: 1010b is A3 chip, 0000b is A2 chip
+ */
+#define PS8805_P0_REG_CHIP_REVISION 0x62
+/*
+ * PS8815 register to differentiate with PS8745: bit 1 = 0 is a PS8815-A2,
+ * 1 is a PS8745-A2.
+ */
+#define PS8815_P0_REG_ID 0x2C
+
+/*
+ * PS8805 GPIO control register. Note the device I2C address of 0x1A is
+ * independent of the ADDR pin on the chip, and not the same address being used
+ * for TCPCI functions.
+ */
+#define PS8805_VENDOR_DEFINED_I2C_ADDR 0x1A
+#define PS8805_REG_GPIO_CONTROL 0x21
+#define PS8805_REG_GPIO_0 BIT(7)
+#define PS8805_REG_GPIO_1 BIT(5)
+#define PS8805_REG_GPIO_2 BIT(6)
+
+enum ps8805_gpio {
+	PS8805_GPIO_0,
+	PS8805_GPIO_1,
+	PS8805_GPIO_2,
+	PS8805_GPIO_NUM,
+};
 
 /**
- * Board specific callback to judge and provide which chip source of PS8XXX
- * series supported by this driver per specific port.
- *
- * If the board supports only one single source then there is no nencessary to
- * provide the __override version.
+ * Set PS8805 gpio signal to desired level
  *
- * If board supports two sources or above (with CONFIG_USB_PD_TCPM_MULTI_PS8XXX)
- * then the __override version is mandatory.
+ * @param port: The Type-C port number.
+ * @param signal PS8805 gpio number (0, 1, or 2)
+ * @param level desired level
+ * @return EC_SUCCESS if I2C accesses are successful
+ */
+int ps8805_gpio_set_level(int port, enum ps8805_gpio signal, int level);
+
+/**
+ * Get PS8805 gpio signal value
  *
- * @param port	TCPC port number.
+ * @param port: The Type-C port number.
+ * @param signal PS8805 gpio number (0, 1, or 2)
+ * @param pointer location to store gpio level
+ * @return EC_SUCCESS if I2C accesses are successful
  */
-__override_proto
-uint16_t board_get_ps8xxx_product_id(int port);
+int ps8805_gpio_get_level(int port, enum ps8805_gpio signal, int *level);
 
-void ps8xxx_tcpc_update_hpd_status(const struct usb_mux *me,
-				   int hpd_lvl, int hpd_irq);
+/**
+ * Check if the chip is PS8755
+ *
+ * @param port: The Type-C port number.
+ * @return true if hidden register sm is 0x80
+ */
+bool check_ps8755_chip(int port);
 
-#ifdef CONFIG_CMD_I2C_STRESS_TEST_TCPC
-extern struct i2c_stress_test_dev ps8xxx_i2c_stress_test_dev;
-#endif /* defined(CONFIG_CMD_I2C_STRESS_TEST_TCPC) */
+/*
+ * Allow boards to customize for PS8XXX initial if board has
+ * specific settings.
+ *
+ * @param port: The Type-C port number.
+ */
+__override_proto void board_ps8xxx_tcpc_init(int port);
 
 #endif /* defined(__CROS_EC_USB_PD_TCPM_PS8XXX_H) */
diff --git a/driver/tcpm/raa489000.c b/driver/tcpm/raa489000.c
index 632c17c78b..282842bd2c 100644
--- a/driver/tcpm/raa489000.c
+++ b/driver/tcpm/raa489000.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -6,19 +6,26 @@
  */
 
 #include "charge_manager.h"
+#include "charger.h"
 #include "common.h"
 #include "console.h"
 #include "driver/charger/isl923x.h"
 #include "i2c.h"
 #include "raa489000.h"
-#include "tcpci.h"
-#include "tcpm.h"
+#include "tcpm/tcpci.h"
+#include "tcpm/tcpm.h"
+#include "timer.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define DEFAULT_R_AC 20
+#define R_AC CONFIG_CHARGER_SENSE_RESISTOR_AC
+#define AC_CURRENT_TO_REG(CUR) ((CUR)*R_AC / DEFAULT_R_AC)
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 static int dev_id[CONFIG_USB_PD_PORT_MAX_COUNT] = { -1 };
 
+#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
 static int raa489000_enter_low_power_mode(int port)
 {
 	int rv;
@@ -33,6 +40,21 @@ static int raa489000_enter_low_power_mode(int port)
 
 	return tcpci_enter_low_power_mode(port);
 }
+#endif /* CONFIG_USB_PD_TCPC_LOW_POWER */
+
+/* Configure output current in the TCPC because it is controlling Vbus */
+int raa489000_set_output_current(int port, enum tcpc_rp_value rp)
+{
+	int regval;
+	int selected_cur = rp == TYPEC_RP_3A0 ?
+				   RAA489000_VBUS_CURRENT_TARGET_3A :
+				   RAA489000_VBUS_CURRENT_TARGET_1_5A;
+
+	regval = AC_CURRENT_TO_REG(selected_cur) +
+		 selected_cur % (DEFAULT_R_AC / R_AC);
+
+	return tcpc_write16(port, RAA489000_VBUS_CURRENT_TARGET, regval);
+}
 
 int raa489000_init(int port)
 {
@@ -41,6 +63,7 @@ int raa489000_init(int port)
 	int device_id;
 	int i2c_port;
 	struct charge_port_info chg = { 0 };
+	int vbus_mv = 0;
 
 	/* Perform unlock sequence */
 	rv = tcpc_write16(port, 0xAA, 0xDAA0);
@@ -60,6 +83,66 @@ int raa489000_init(int port)
 	CPRINTS("%s(%d): DEVICE_ID=%d", __func__, port, device_id);
 	dev_id[port] = device_id;
 
+	/* Enable the ADC */
+	/*
+	 * TODO(b:147316511) Since this register can be accessed by multiple
+	 * tasks, we should add a mutex when modifying this register.
+	 *
+	 * See(b:178981107,b:178728138) When the battery does not exist,
+	 * we must enable ADC function so that charger_get_vbus_voltage
+	 * can get the correct voltage.
+	 */
+	i2c_port = tcpc_config[port].i2c_info.port;
+	rv = i2c_read16(i2c_port, ISL923X_ADDR_FLAGS, ISL9238_REG_CONTROL3,
+			&regval);
+	regval |= RAA489000_ENABLE_ADC;
+	rv |= i2c_write16(i2c_port, ISL923X_ADDR_FLAGS, ISL9238_REG_CONTROL3,
+			  regval);
+	if (rv)
+		CPRINTS("c%d: failed to enable ADCs", port);
+
+	/* Enable Vbus detection */
+	rv = tcpc_write(port, TCPC_REG_COMMAND,
+			TCPC_REG_COMMAND_ENABLE_VBUS_DETECT);
+	if (rv)
+		CPRINTS("c%d: failed to enable vbus detect cmd", port);
+
+	/*
+	 * If VBUS is present, start sinking from it if we haven't already
+	 * chosen a charge port and no battery is connected.  This is
+	 * *kinda hacky* doing it here, but we must start sinking VBUS now,
+	 * otherwise the board may die (See b/150702984, b/178728138).  This
+	 * works as this part is a combined charger IC and TCPC.
+	 */
+	usleep(853);
+	charger_get_vbus_voltage(port, &vbus_mv);
+
+	/*
+	 * Disable the ADC
+	 *
+	 * See(b:178356507)  9mW is reduced on S0iX power consumption
+	 * by clearing 'Enable ADC' bit.
+	 */
+	if (IS_ENABLED(CONFIG_OCPC) && (port != 0)) {
+		i2c_port = tcpc_config[port].i2c_info.port;
+		rv = i2c_read16(i2c_port, ISL923X_ADDR_FLAGS,
+				ISL9238_REG_CONTROL3, &regval);
+		regval &= ~RAA489000_ENABLE_ADC;
+		rv |= i2c_write16(i2c_port, ISL923X_ADDR_FLAGS,
+				  ISL9238_REG_CONTROL3, regval);
+		if (rv)
+			CPRINTS("c%d: failed to disable ADCs", port);
+	}
+
+	if ((vbus_mv > 3900) &&
+	    charge_manager_get_active_charge_port() == CHARGE_PORT_NONE &&
+	    !pd_is_battery_capable()) {
+		chg.current = 500;
+		chg.voltage = 5000;
+		charge_manager_update_charge(CHARGE_SUPPLIER_TYPEC, port, &chg);
+		board_set_active_charge_port(port);
+	}
+
 	if (device_id > 1) {
 		/*
 		 * A1 silicon has a DEVICE_ID of 1.  For B0 and newer, we need
@@ -87,44 +170,23 @@ int raa489000_init(int port)
 	 */
 	if (device_id <= 1) {
 		rv = tcpc_write16(port, RAA489000_TYPEC_SETTING1,
-			     RAA489000_SETTING1_RDOE |
-			     RAA489000_SETTING1_CC2_CMP3_EN |
-			     RAA489000_SETTING1_CC2_CMP2_EN |
-			     RAA489000_SETTING1_CC2_CMP1_EN |
-			     RAA489000_SETTING1_CC1_CMP3_EN |
-			     RAA489000_SETTING1_CC1_CMP2_EN |
-			     RAA489000_SETTING1_CC1_CMP1_EN |
-			     RAA489000_SETTING1_CC_DB_EN);
+				  RAA489000_SETTING1_RDOE |
+					  RAA489000_SETTING1_CC2_CMP3_EN |
+					  RAA489000_SETTING1_CC2_CMP2_EN |
+					  RAA489000_SETTING1_CC2_CMP1_EN |
+					  RAA489000_SETTING1_CC1_CMP3_EN |
+					  RAA489000_SETTING1_CC1_CMP2_EN |
+					  RAA489000_SETTING1_CC1_CMP1_EN |
+					  RAA489000_SETTING1_CC_DB_EN);
 		if (rv)
 			CPRINTS("c%d: failed to enable CC comparators", port);
 	}
 
-	/* Enable the ADC */
-	/*
-	 * TODO(b:147316511) Since this register can be accessed by multiple
-	 * tasks, we should add a mutex when modifying this register.
-	 */
-	i2c_port = tcpc_config[port].i2c_info.port;
-	rv = i2c_read16(i2c_port, ISL923X_ADDR_FLAGS, ISL9238_REG_CONTROL3,
-			&regval);
-	regval |= RAA489000_ENABLE_ADC;
-	rv |= i2c_write16(i2c_port, ISL923X_ADDR_FLAGS, ISL9238_REG_CONTROL3,
-			  regval);
-	if (rv)
-		CPRINTS("c%d: failed to enable ADCs", port);
-
-	/* Enable Vbus detection */
-	rv = tcpc_write(port, TCPC_REG_COMMAND,
-			TCPC_REG_COMMAND_ENABLE_VBUS_DETECT);
-	if (rv)
-		CPRINTS("c%d: failed to enable vbus detect cmd", port);
-
-
 	/* Set Rx enable for receiver comparator */
 	rv = tcpc_read16(port, RAA489000_PD_PHYSICAL_SETTING1, &regval);
 	regval |= RAA489000_PD_PHY_SETTING1_RECEIVER_EN |
-		RAA489000_PD_PHY_SETTING1_SQUELCH_EN |
-		RAA489000_PD_PHY_SETTING1_TX_LDO11_EN;
+		  RAA489000_PD_PHY_SETTING1_SQUELCH_EN |
+		  RAA489000_PD_PHY_SETTING1_TX_LDO11_EN;
 	rv |= tcpc_write16(port, RAA489000_PD_PHYSICAL_SETTING1, regval);
 	if (rv)
 		CPRINTS("c%d: failed to set PD PHY setting1", port);
@@ -164,18 +226,18 @@ int raa489000_init(int port)
 		CPRINTS("c%d: failed to set TCPCIv1.0 mode", port);
 
 	/*
-	 * If VBUS is present, start sinking from it if we haven't already
-	 * chosen a charge port.  This is *kinda hacky* doing it here, but we
-	 * must start sinking VBUS now, otherwise the board may die if there is
-	 * no battery connected. (See b/150702984)
+	 * Set Vbus OCP UV here, PD tasks will set target current
 	 */
-	if (pd_snk_is_vbus_provided(port) &&
-	    charge_manager_get_active_charge_port() == CHARGE_PORT_NONE) {
-		chg.current = 500;
-		chg.voltage = 5000;
-		charge_manager_update_charge(CHARGE_SUPPLIER_VBUS, port, &chg);
-		board_set_active_charge_port(port);
-	}
+	rv = tcpc_write16(port, RAA489000_VBUS_OCP_UV_THRESHOLD,
+			  RAA489000_OCP_THRESHOLD_VALUE);
+	if (rv)
+		CPRINTS("c%d: failed to set OCP threshold", port);
+
+	/* Set Vbus Target Voltage */
+	rv = tcpc_write16(port, RAA489000_VBUS_VOLTAGE_TARGET,
+			  RAA489000_VBUS_VOLTAGE_TARGET_5160MV);
+	if (rv)
+		CPRINTS("c%d: failed to set Vbus Target Voltage", port);
 
 	return rv;
 }
@@ -196,36 +258,124 @@ int raa489000_tcpm_set_cc(int port, int pull)
 	return rv;
 }
 
+#ifdef CONFIG_CMD_TCPC_DUMP
+
+static const struct tcpc_reg_dump_map raa489000_regs[] = {
+	{
+		.addr = RAA489000_TCPC_SETTING1,
+		.name = "TCPC_SETTING1",
+		.size = 2,
+	},
+	{
+		.addr = RAA489000_VBUS_VOLTAGE_TARGET,
+		.name = "VBUS_VOLTAGE_TARGET",
+		.size = 2,
+	},
+	{
+		.addr = RAA489000_VBUS_CURRENT_TARGET,
+		.name = "VBUS_CURRENT_TARGET",
+		.size = 2,
+	},
+	{
+		.addr = RAA489000_VBUS_OCP_UV_THRESHOLD,
+		.name = "VBUS_OCP_UV_THRESHOLD",
+		.size = 2,
+	},
+	{
+		.addr = RAA489000_TYPEC_SETTING1,
+		.name = "TYPEC_SETTING1",
+		.size = 2,
+	},
+	{
+		.addr = RAA489000_PD_PHYSICAL_SETTING1,
+		.name = "PD_PHYSICAL_SETTING1",
+		.size = 2,
+	},
+	{
+		.addr = RAA489000_PD_PHYSICAL_PARAMETER1,
+		.name = "PD_PHYSICAL_PARAMETER1",
+		.size = 2,
+	},
+};
+
+void raa489000_dump_registers(int port)
+{
+	tcpc_dump_std_registers(port);
+	tcpc_dump_registers(port, raa489000_regs, ARRAY_SIZE(raa489000_regs));
+}
+
+#endif
+
+int raa489000_debug_detach(int port)
+{
+	int rv;
+	int power_status;
+
+	/*
+	 * Force RAA489000 to see debug detach by running:
+	 *
+	 * 1. Set POWER_CONTROL. AutoDischargeDisconnect=1
+	 * 2. Set ROLE_CONTROL=0x0F(OPEN,OPEN)
+	 * 3. Set POWER_CONTROL. AutoDischargeDisconnect=0
+	 *
+	 * Only if we have sufficient battery or are not sinking.  Otherwise,
+	 * we would risk brown-out during the CC open set.
+	 */
+	RETURN_ERROR(tcpc_read(port, TCPC_REG_POWER_STATUS, &power_status));
+
+	if (!pd_is_battery_capable() &&
+	    (power_status & TCPC_REG_POWER_STATUS_SINKING_VBUS))
+		return EC_SUCCESS;
+
+	tcpci_tcpc_enable_auto_discharge_disconnect(port, 1);
+
+	rv = tcpci_tcpm_set_cc(port, TYPEC_CC_OPEN);
+
+	tcpci_tcpc_enable_auto_discharge_disconnect(port, 0);
+
+	return rv;
+}
+
 /* RAA489000 is a TCPCI compatible port controller */
 const struct tcpm_drv raa489000_tcpm_drv = {
-	.init                   = &raa489000_init,
-	.release                = &tcpci_tcpm_release,
-	.get_cc                 = &tcpci_tcpm_get_cc,
+	.init = &raa489000_init,
+	.release = &tcpci_tcpm_release,
+	.get_cc = &tcpci_tcpm_get_cc,
 #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	.check_vbus_level       = &tcpci_tcpm_check_vbus_level,
+	.check_vbus_level = &tcpci_tcpm_check_vbus_level,
 #endif
-	.select_rp_value        = &tcpci_tcpm_select_rp_value,
-	.set_cc                 = &raa489000_tcpm_set_cc,
-	.set_polarity           = &tcpci_tcpm_set_polarity,
+	.select_rp_value = &tcpci_tcpm_select_rp_value,
+	.set_cc = &raa489000_tcpm_set_cc,
+	.set_polarity = &tcpci_tcpm_set_polarity,
 #ifdef CONFIG_USB_PD_DECODE_SOP
-	.sop_prime_disable	= &tcpci_tcpm_sop_prime_disable,
+	.sop_prime_enable = &tcpci_tcpm_sop_prime_enable,
 #endif
-	.set_vconn              = &tcpci_tcpm_set_vconn,
-	.set_msg_header         = &tcpci_tcpm_set_msg_header,
-	.set_rx_enable          = &tcpci_tcpm_set_rx_enable,
-	.get_message_raw        = &tcpci_tcpm_get_message_raw,
-	.transmit               = &tcpci_tcpm_transmit,
-	.tcpc_alert             = &tcpci_tcpc_alert,
+	.set_vconn = &tcpci_tcpm_set_vconn,
+	.set_msg_header = &tcpci_tcpm_set_msg_header,
+	.set_rx_enable = &tcpci_tcpm_set_rx_enable,
+	.get_message_raw = &tcpci_tcpm_get_message_raw,
+	.transmit = &tcpci_tcpm_transmit,
+	.tcpc_alert = &tcpci_tcpc_alert,
 #ifdef CONFIG_USB_PD_DISCHARGE_TCPC
-	.tcpc_discharge_vbus    = &tcpci_tcpc_discharge_vbus,
+	.tcpc_discharge_vbus = &tcpci_tcpc_discharge_vbus,
 #endif
 #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-	.drp_toggle             = &tcpci_tcpc_drp_toggle,
+	.drp_toggle = &tcpci_tcpc_drp_toggle,
 #endif
-	.get_chip_info          = &tcpci_get_chip_info,
+	.get_chip_info = &tcpci_get_chip_info,
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	.enter_low_power_mode   = &raa489000_enter_low_power_mode,
+	.enter_low_power_mode = &raa489000_enter_low_power_mode,
+	.wake_low_power_mode = &tcpci_wake_low_power_mode,
 #endif
+	.set_bist_test_mode = &tcpci_set_bist_test_mode,
+	.get_bist_test_mode = &tcpci_get_bist_test_mode,
 	.tcpc_enable_auto_discharge_disconnect =
-	&tcpci_tcpc_enable_auto_discharge_disconnect,
+		&tcpci_tcpc_enable_auto_discharge_disconnect,
+	.debug_detach = &raa489000_debug_detach,
+#ifdef CONFIG_CMD_TCPC_DUMP
+	.dump_registers = &raa489000_dump_registers,
+#endif
+#ifdef CONFIG_USB_PD_FRS
+	.set_frs_enable = &tcpci_tcpc_fast_role_swap_enable,
+#endif
 };
diff --git a/driver/tcpm/raa489000.h b/driver/tcpm/raa489000.h
index 122c6eb37e..b0bb202f98 100644
--- a/driver/tcpm/raa489000.h
+++ b/driver/tcpm/raa489000.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -6,6 +6,7 @@
  */
 
 #include "compile_time_macros.h"
+#include "usb_pd_tcpm.h"
 
 #ifndef __CROS_EC_USB_PD_TCPM_RAA489000_H
 #define __CROS_EC_USB_PD_TCPM_RAA489000_H
@@ -16,41 +17,75 @@
 #define RAA489000_TCPC3_I2C_FLAGS 0x25
 
 /* Vendor registers */
-#define RAA489000_TCPC_SETTING1		 0x80
-#define RAA489000_TYPEC_SETTING1	 0xC0
-#define RAA489000_PD_PHYSICAL_SETTING1	 0xE0
+#define RAA489000_TCPC_SETTING1 0x80
+#define RAA489000_VBUS_VOLTAGE_TARGET 0x90
+#define RAA489000_VBUS_CURRENT_TARGET 0x92
+#define RAA489000_VBUS_OCP_UV_THRESHOLD 0x94
+#define RAA489000_TYPEC_SETTING1 0xC0
+#define RAA489000_PD_PHYSICAL_SETTING1 0xE0
 #define RAA489000_PD_PHYSICAL_PARAMETER1 0xE8
 
+/* TCPC_SETTING_1 */
+#define RAA489000_TCPCV1_0_EN BIT(0)
+#define RAA489000_TCPC_PWR_CNTRL BIT(4)
+
+/* VBUS_CURRENT_TARGET */
+#define RAA489000_VBUS_CURRENT_TARGET_3A 0x66 /* 3.0A + iOvershoot */
+#define RAA489000_VBUS_CURRENT_TARGET_1_5A 0x38 /* 1.5A + iOvershoot */
+
+/* VBUS_VOLTAGE_TARGET */
+#define RAA489000_VBUS_VOLTAGE_TARGET_5160MV 0x102 /* 5.16V */
+#define RAA489000_VBUS_VOLTAGE_TARGET_5220MV 0x105 /* 5.22V */
+
+/* VBUS_OCP_UV_THRESHOLD */
+/* Detect voltage level of overcurrent protection during Sourcing VBUS */
+#ifdef CONFIG_PLATFORM_EC_RAA489000_OCP_UV_THRESHOLD_MV
+#define RAA489000_OCP_THRESHOLD_VALUE \
+	(CONFIG_PLATFORM_EC_RAA489000_OCP_UV_THRESHOLD_MV / 25)
+#else
+#define RAA489000_OCP_THRESHOLD_VALUE 0x00BE /* 4.75V */
+#endif
+
+/* TYPEC_SETTING1 - only older silicon */
 /* Enables for reverse current protection */
-#define RAA489000_SETTING1_IP2_EN	BIT(9)
-#define RAA489000_SETTING1_IP1_EN	BIT(8)
+#define RAA489000_SETTING1_IP2_EN BIT(9)
+#define RAA489000_SETTING1_IP1_EN BIT(8)
 
 /* Switches from dead-battery Rd */
-#define RAA489000_SETTING1_RDOE		BIT(7)
+#define RAA489000_SETTING1_RDOE BIT(7)
 
 /* CC comparator enables */
-#define RAA489000_SETTING1_CC2_CMP3_EN	BIT(6)
-#define RAA489000_SETTING1_CC2_CMP2_EN	BIT(5)
-#define RAA489000_SETTING1_CC2_CMP1_EN	BIT(4)
-#define RAA489000_SETTING1_CC1_CMP3_EN	BIT(3)
-#define RAA489000_SETTING1_CC1_CMP2_EN	BIT(2)
-#define RAA489000_SETTING1_CC1_CMP1_EN	BIT(1)
+#define RAA489000_SETTING1_CC2_CMP3_EN BIT(6)
+#define RAA489000_SETTING1_CC2_CMP2_EN BIT(5)
+#define RAA489000_SETTING1_CC2_CMP1_EN BIT(4)
+#define RAA489000_SETTING1_CC1_CMP3_EN BIT(3)
+#define RAA489000_SETTING1_CC1_CMP2_EN BIT(2)
+#define RAA489000_SETTING1_CC1_CMP1_EN BIT(1)
 
 /* CC debounce enable */
-#define RAA489000_SETTING1_CC_DB_EN	BIT(0)
-
-/* TCPC_SETTING_1 */
-#define RAA489000_TCPCV1_0_EN BIT(0)
-#define RAA489000_TCPC_PWR_CNTRL BIT(4)
+#define RAA489000_SETTING1_CC_DB_EN BIT(0)
 
 /* PD_PHYSICAL_SETTING_1 */
 #define RAA489000_PD_PHY_SETTING1_RECEIVER_EN BIT(9)
-#define RAA489000_PD_PHY_SETTING1_SQUELCH_EN  BIT(8)
+#define RAA489000_PD_PHY_SETTING1_SQUELCH_EN BIT(8)
 #define RAA489000_PD_PHY_SETTING1_TX_LDO11_EN BIT(0)
 
 /* PD_PHYSICAL_PARMETER_1 */
 #define PD_PHY_PARAM1_NOISE_FILTER_CNT_MASK (GENMASK(4, 0))
 
+/**
+ *
+ * Set output current limit on the TCPC.  Note, this chip also offers an OTG
+ * current level register in the charger i2c page but we must use the TCPC
+ * current limit because the TCPC is controlling Vbus.
+ *
+ * @param port	USB-C port number
+ * @param rp	Rp value for current limit (either 1.5A or 3A)
+ *
+ * @return	Zero if the current limit set was successful, non-zero otherwise
+ */
+int raa489000_set_output_current(int port, enum tcpc_rp_value rp);
+
 extern const struct tcpm_drv raa489000_tcpm_drv;
 
 #endif
diff --git a/driver/tcpm/rt1715.c b/driver/tcpm/rt1715.c
index cf98666058..ab21f0e0e1 100644
--- a/driver/tcpm/rt1715.c
+++ b/driver/tcpm/rt1715.c
@@ -1,22 +1,25 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
-
 /* Richtek RT1715 Type-C port controller */
 
 #include "common.h"
 #include "rt1715.h"
-#include "tcpci.h"
-#include "tcpm.h"
+#include "tcpm/tcpci.h"
+#include "tcpm/tcpm.h"
 #include "timer.h"
 #include "usb_pd.h"
+#include "usb_pd_tcpm.h"
 
 #ifndef CONFIG_USB_PD_TCPM_TCPCI
 #error "RT1715 is using a standard TCPCI interface"
 #error "Please upgrade your board configuration"
 #endif
 
+static int rt1715_polarity[CONFIG_USB_PD_PORT_MAX_COUNT];
+static bool rt1715_initialized[CONFIG_USB_PD_PORT_MAX_COUNT];
+
 static int rt1715_enable_ext_messages(int port, int enable)
 {
 	return tcpc_update8(port, RT1715_REG_VENDOR_5,
@@ -27,14 +30,22 @@ static int rt1715_enable_ext_messages(int port, int enable)
 static int rt1715_tcpci_tcpm_init(int port)
 {
 	int rv;
+	/*
+	 * Do not fully reinitialize the registers when leaving low-power mode.
+	 * TODO(b/179234089): Generalize this concept in the tcpm_drv API.
+	 */
 
-	/* RT1715 has a vendor-defined register reset */
-	rv = tcpc_update8(port, RT1715_REG_VENDOR_7,
-			  RT1715_REG_VENDOR_7_SOFT_RESET, MASK_SET);
-	if (rv)
-		return rv;
+	/* Only do soft-reset on first init. */
+	if (!(rt1715_initialized[port])) {
+		/* RT1715 has a vendor-defined register reset */
+		rv = tcpc_update8(port, RT1715_REG_VENDOR_7,
+				  RT1715_REG_VENDOR_7_SOFT_RESET, MASK_SET);
+		if (rv)
+			return rv;
+		rt1715_initialized[port] = true;
+		msleep(10);
+	}
 
-	msleep(10);
 	rv = tcpc_update8(port, RT1715_REG_VENDOR_5,
 			  RT1715_REG_VENDOR_5_SHUTDOWN_OFF, MASK_SET);
 	if (rv)
@@ -42,28 +53,216 @@ static int rt1715_tcpci_tcpm_init(int port)
 
 	if (IS_ENABLED(CONFIG_USB_PD_REV30))
 		rt1715_enable_ext_messages(port, 1);
+
+	rv = tcpc_write(port, RT1715_REG_I2CRST_CTRL,
+			(RT1715_REG_I2CRST_CTRL_EN |
+			 RT1715_REG_I2CRST_CTRL_TOUT_200MS));
+	if (rv)
+		return rv;
+
+	/* Unmask interrupt for LPM wakeup */
+	rv = tcpc_write(port, RT1715_REG_RT_MASK, RT1715_REG_RT_MASK_M_WAKEUP);
+	if (rv)
+		return rv;
+
+	/*
+	 * Set tTCPCFilter (CC debounce time) to 400 us
+	 * (min 250 us, max 500 us).
+	 */
+	rv = tcpc_write(port, RT1715_REG_TTCPC_FILTER,
+			RT1715_REG_TTCPC_FILTER_400US);
+	if (rv)
+		return rv;
+
+	rv = tcpc_write(port, RT1715_REG_DRP_TOGGLE_CYCLE,
+			RT1715_REG_DRP_TOGGLE_CYCLE_76MS);
+	if (rv)
+		return rv;
+
+	/* PHY control */
+	/* Set PHY control registers to Richtek recommended values */
+	rv = tcpc_write(port, RT1715_REG_PHY_CTRL1,
+			(RT1715_REG_PHY_CTRL1_ENRETRY |
+			 RT1715_REG_PHY_CTRL1_TRANSCNT_7 |
+			 RT1715_REG_PHY_CTRL1_TRXFILTER_125NS));
+	if (rv)
+		return rv;
+
+	/* Set PHY control registers to Richtek recommended values */
+	rv = tcpc_write(port, RT1715_REG_PHY_CTRL2,
+			RT1715_REG_PHY_CTRL2_CDRTHRESH_2_58US);
+	if (rv)
+		return rv;
+
 	return tcpci_tcpm_init(port);
 }
 
+/*
+ * Selects the CC PHY noise filter voltage level according to the current
+ * CC voltage level.
+ *
+ * @param cc_level The CC voltage level for the port's current role
+ * @return EC_SUCCESS if writes succeed; failure code otherwise
+ */
+static inline int rt1715_init_cc_params(int port, int cc_level)
+{
+	int rv, en, sel;
+
+	if (cc_level == TYPEC_CC_VOLT_RP_DEF) {
+		/* RXCC threshold : 0.55V */
+		en = RT1715_REG_BMCIO_RXDZEN_DISABLE;
+
+		sel = RT1715_REG_BMCIO_RXDZSEL_OCCTRL_600MA |
+		      RT1715_REG_BMCIO_RXDZSEL_SEL;
+	} else {
+		/* RD threshold : 0.35V & RP threshold : 0.75V */
+		en = RT1715_REG_BMCIO_RXDZEN_ENABLE;
+
+		sel = RT1715_REG_BMCIO_RXDZSEL_OCCTRL_600MA |
+		      RT1715_REG_BMCIO_RXDZSEL_SEL;
+	}
+
+	rv = tcpc_write(port, RT1715_REG_BMCIO_RXDZEN, en);
+	if (!rv)
+		rv = tcpc_write(port, RT1715_REG_BMCIO_RXDZSEL, sel);
+
+	return rv;
+}
+
+static int rt1715_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
+			 enum tcpc_cc_voltage_status *cc2)
+{
+	int rv;
+
+	rv = tcpci_tcpm_get_cc(port, cc1, cc2);
+	if (rv)
+		return rv;
+
+	return rt1715_init_cc_params(port, rt1715_polarity[port] ? *cc2 : *cc1);
+}
+
+/*
+ * See b/179256608#comment26 for explanation.
+ * Disable 24MHz oscillator and enable LPM. Upon exit from LPM, the LPEN will be
+ * reset to 0.
+ *
+ * The exit condition for LPM is CC status change, and the wakeup interrupt will
+ * be set.
+ */
+#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
+static int rt1715_enter_low_power_mode(int port)
+{
+	int regval;
+	int rv;
+
+	rv = tcpc_read(port, RT1715_REG_PWR, &regval);
+	if (rv)
+		return rv;
+
+	regval |= RT1715_REG_PWR_BMCIO_LPEN;
+	regval &= ~RT1715_REG_PWR_BMCIO_OSCEN;
+	rv = tcpc_write(port, RT1715_REG_PWR, regval);
+	if (rv)
+		return rv;
+
+	return tcpci_enter_low_power_mode(port);
+}
+#endif
+
+static int rt1715_set_vconn(int port, int enable)
+{
+	int rv;
+	int regval;
+
+	/*
+	 * Auto-idle cannot be used while sourcing Vconn.
+	 * See b/179256608#comment26 for explanation.
+	 */
+	rv = tcpc_read(port, RT1715_REG_VENDOR_5, &regval);
+	if (rv)
+		return rv;
+
+	if (enable)
+		regval &= ~RT1715_REG_VENDOR_5_AUTOIDLE_EN;
+	else
+		regval |= RT1715_REG_VENDOR_5_AUTOIDLE_EN;
+
+	rv = tcpc_write(port, RT1715_REG_VENDOR_5, regval);
+	if (rv)
+		return rv;
+
+	return tcpci_tcpm_set_vconn(port, enable);
+}
+
+static int rt1715_set_polarity(int port, enum tcpc_cc_polarity polarity)
+{
+	int rv;
+	enum tcpc_cc_voltage_status cc1, cc2;
+
+	rt1715_polarity[port] = polarity;
+
+	rv = tcpci_tcpm_get_cc(port, &cc1, &cc2);
+	if (rv)
+		return rv;
+
+	rv = rt1715_init_cc_params(port, polarity ? cc2 : cc1);
+	if (rv)
+		return rv;
+
+	return tcpci_tcpm_set_polarity(port, polarity);
+}
+
+static void rt1715_alert(int port)
+{
+	/*
+	 * Make sure the wakeup interrupt is cleared. This bit is set on wakeup
+	 * from LPM. See b/179256608#comment16 for explanation.
+	 */
+	tcpc_write(port, RT1715_REG_RT_INT, RT1715_REG_RT_INT_WAKEUP);
+
+	tcpci_tcpc_alert(port);
+}
+
+#ifdef CONFIG_CMD_TCPC_DUMP
+static const struct tcpc_reg_dump_map rt1715_regs[] = {
+	{
+		.addr = RT1715_REG_RT_INT,
+		.name = "RT_INT",
+		.size = 1,
+	},
+	{
+		.addr = RT1715_REG_RT_MASK,
+		.name = "RT_MASK",
+		.size = 1,
+	},
+};
+
+static void rt1715_dump_registers(int port)
+{
+	tcpc_dump_std_registers(port);
+	tcpc_dump_registers(port, rt1715_regs, ARRAY_SIZE(rt1715_regs));
+}
+#endif /* defined(CONFIG_CMD_TCPC_DUMP) */
+
 const struct tcpm_drv rt1715_tcpm_drv = {
 	.init = &rt1715_tcpci_tcpm_init,
 	.release = &tcpci_tcpm_release,
-	.get_cc = &tcpci_tcpm_get_cc,
+	.get_cc = &rt1715_get_cc,
 #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
 	.check_vbus_level = &tcpci_tcpm_check_vbus_level,
 #endif
 	.select_rp_value = &tcpci_tcpm_select_rp_value,
 	.set_cc = &tcpci_tcpm_set_cc,
-	.set_polarity = &tcpci_tcpm_set_polarity,
+	.set_polarity = &rt1715_set_polarity,
 #ifdef CONFIG_USB_PD_DECODE_SOP
-	.sop_prime_disable	= &tcpci_tcpm_sop_prime_disable,
+	.sop_prime_enable = &tcpci_tcpm_sop_prime_enable,
 #endif
-	.set_vconn = &tcpci_tcpm_set_vconn,
+	.set_vconn = &rt1715_set_vconn,
 	.set_msg_header = &tcpci_tcpm_set_msg_header,
 	.set_rx_enable = &tcpci_tcpm_set_rx_enable,
 	.get_message_raw = &tcpci_tcpm_get_message_raw,
 	.transmit = &tcpci_tcpm_transmit,
-	.tcpc_alert = &tcpci_tcpc_alert,
+	.tcpc_alert = &rt1715_alert,
 #ifdef CONFIG_USB_PD_DISCHARGE_TCPC
 	.tcpc_discharge_vbus = &tcpci_tcpc_discharge_vbus,
 #endif
@@ -72,12 +271,15 @@ const struct tcpm_drv rt1715_tcpm_drv = {
 #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
 	.drp_toggle = &tcpci_tcpc_drp_toggle,
 #endif
-#ifdef CONFIG_USBC_PPC
+	.get_chip_info = &tcpci_get_chip_info,
 	.set_snk_ctrl = &tcpci_tcpm_set_snk_ctrl,
 	.set_src_ctrl = &tcpci_tcpm_set_src_ctrl,
-#endif
-	.get_chip_info = &tcpci_get_chip_info,
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	.enter_low_power_mode = &tcpci_enter_low_power_mode,
+	.enter_low_power_mode = &rt1715_enter_low_power_mode,
+#endif
+	.set_bist_test_mode = &tcpci_set_bist_test_mode,
+	.get_bist_test_mode = &tcpci_get_bist_test_mode,
+#ifdef CONFIG_CMD_TCPC_DUMP
+	.dump_registers = &rt1715_dump_registers,
 #endif
 };
diff --git a/driver/tcpm/rt1715.h b/driver/tcpm/rt1715.h
index f9d2395446..d489dc73fd 100644
--- a/driver/tcpm/rt1715.h
+++ b/driver/tcpm/rt1715.h
@@ -1,10 +1,8 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
-
 /* Richtek RT1715 Type-C port controller */
-
 #ifndef __CROS_EC_USB_PD_TCPM_RT1715_H
 #define __CROS_EC_USB_PD_TCPM_RT1715_H
 
@@ -13,12 +11,73 @@
 
 #define RT1715_VENDOR_ID 0x29CF
 
+#define RT1715_REG_VENDOR_7 0xA0
+#define RT1715_REG_VENDOR_7_SOFT_RESET BIT(0)
+
+#define RT1715_REG_PHY_CTRL1 0x80
+/* Wait for tReceive before retrying transmit in response to a bad GoodCRC */
+#define RT1715_REG_PHY_CTRL1_ENRETRY BIT(7)
+/*
+ * Bit 6:4 <TRANSCNT>: Consider CC to be idle if there are 7 or fewer BMC
+ * transients observed in <46.67us>
+ */
+#define RT1715_REG_PHY_CTRL1_TRANSCNT_7 0x70
+/*
+ * Bit 1:0 <TRXFilter>: RX filter to make sure the stable received PD message.
+ * default value is 01b
+ * The debounce time is (register value + 2) * 41.67ns
+ */
+#define RT1715_REG_PHY_CTRL1_TRXFILTER_125NS 0x01
+#define RT1715_REG_PHY_CTRL2 0x81
+/*
+ * Decrease the time that the PHY will wait for a second transition to detect
+ * a BMC-encoded 1 bit from 2.67 us to 2.25 us.
+ * Timeout = register value * .04167 us.
+ */
+#define RT1715_REG_PHY_CTRL2_CDRTHRESH_2_25US 54
+#define RT1715_REG_PHY_CTRL2_CDRTHRESH_2_5US 60
+#define RT1715_REG_PHY_CTRL2_CDRTHRESH_2_58US 62
+
+#define RT1715_REG_PWR 0x90
+#define RT1715_REG_PWR_BMCIO_LPEN BIT(3)
+#define RT1715_REG_PWR_VBUS_DETEN BIT(1)
+#define RT1715_REG_PWR_BMCIO_OSCEN BIT(0)
+
+#define RT1715_REG_BMCIO_RXDZSEL 0x93
+#define RT1715_REG_BMCIO_RXDZSEL_OCCTRL_600MA BIT(7)
+#define RT1715_REG_BMCIO_RXDZSEL_SEL BIT(0)
+
+#define RT1715_REG_RT_INT 0x98
+#define RT1715_REG_RT_INT_WAKEUP BIT(0)
+
+#define RT1715_REG_RT_MASK 0x99
+#define RT1715_REG_RT_MASK_M_WAKEUP BIT(0)
+
 #define RT1715_REG_VENDOR_5 0x9B
 #define RT1715_REG_VENDOR_5_SHUTDOWN_OFF BIT(5)
 #define RT1715_REG_VENDOR_5_ENEXTMSG BIT(4)
+#define RT1715_REG_VENDOR_5_AUTOIDLE_EN BIT(3)
 
-#define RT1715_REG_VENDOR_7 0xA0
-#define RT1715_REG_VENDOR_7_SOFT_RESET BIT(0)
+#define RT1715_REG_I2CRST_CTRL 0x9E
+/* I2C reset : (val + 1) * 12.5ms */
+#define RT1715_REG_I2CRST_CTRL_TOUT_200MS 0x0F
+#define RT1715_REG_I2CRST_CTRL_TOUT_150MS 0x0B
+#define RT1715_REG_I2CRST_CTRL_TOUT_100MS 0x07
+#define RT1715_REG_I2CRST_CTRL_EN BIT(7)
+
+#define RT1715_REG_TTCPC_FILTER 0xA1
+#define RT1715_REG_TTCPC_FILTER_400US 0x0F
+
+#define RT1715_REG_DRP_TOGGLE_CYCLE 0xA2
+/* DRP Duty : (51.2 + 6.4 * val) ms */
+#define RT1715_REG_DRP_TOGGLE_CYCLE_76MS 0x04
+
+#define RT1715_REG_DRP_DUTY_CTRL 0xA3
+#define RT1715_REG_DRP_DUTY_CTRL_40PERCENT 400
+
+#define RT1715_REG_BMCIO_RXDZEN 0xAF
+#define RT1715_REG_BMCIO_RXDZEN_ENABLE 0x01
+#define RT1715_REG_BMCIO_RXDZEN_DISABLE 0x00
 
 extern const struct tcpm_drv rt1715_tcpm_drv;
 
diff --git a/driver/tcpm/rt1718s.c b/driver/tcpm/rt1718s.c
new file mode 100644
index 0000000000..6b83d8821a
--- /dev/null
+++ b/driver/tcpm/rt1718s.c
@@ -0,0 +1,680 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * RT1718S TCPC Driver
+ */
+
+#include "battery.h"
+#include "console.h"
+#include "driver/bc12/rt1718s.h"
+#include "driver/tcpm/rt1718s.h"
+#include "driver/tcpm/tcpci.h"
+#include "driver/tcpm/tcpm.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "stdint.h"
+#include "system.h"
+#include "task.h"
+#include "timer.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pe_sm.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+#define RT1718S_SW_RESET_DELAY_MS 2
+/* Time for delay deasserting EN_FRS after FRS VBUS drop. */
+#define RT1718S_FRS_DIS_DELAY (5 * MSEC)
+
+#define FLAG_FRS_ENABLED BIT(0)
+#define FLAG_FRS_RX_SIGNALLED BIT(1)
+#define FLAG_FRS_VBUS_VALID_FALL BIT(2)
+static atomic_t frs_flag[CONFIG_USB_PD_PORT_MAX_COUNT];
+K_MUTEX_DEFINE(adc_lock);
+
+/* i2c_write function which won't wake TCPC from low power mode. */
+static int rt1718s_write(int port, int reg, int val, int len)
+{
+	if (reg > 0xFF) {
+		return i2c_write_offset16(tcpc_config[port].i2c_info.port,
+					  tcpc_config[port].i2c_info.addr_flags,
+					  reg, val, len);
+	} else if (len == 1) {
+		return tcpc_write(port, reg, val);
+	} else {
+		return tcpc_write16(port, reg, val);
+	}
+}
+
+static int rt1718s_read(int port, int reg, int *val, int len)
+{
+	if (reg > 0xFF) {
+		return i2c_read_offset16(tcpc_config[port].i2c_info.port,
+					 tcpc_config[port].i2c_info.addr_flags,
+					 reg, val, len);
+	} else if (len == 1) {
+		return tcpc_read(port, reg, val);
+	} else {
+		return tcpc_read16(port, reg, val);
+	}
+}
+
+int rt1718s_write8(int port, int reg, int val)
+{
+	return rt1718s_write(port, reg, val, 1);
+}
+
+int rt1718s_read8(int port, int reg, int *val)
+{
+	return rt1718s_read(port, reg, val, 1);
+}
+
+int rt1718s_update_bits8(int port, int reg, int mask, int val)
+{
+	int reg_val;
+
+	if (mask == 0xFF)
+		return rt1718s_write8(port, reg, val);
+
+	RETURN_ERROR(rt1718s_read8(port, reg, &reg_val));
+
+	reg_val &= (~mask);
+	reg_val |= (mask & val);
+	return rt1718s_write8(port, reg, reg_val);
+}
+
+int rt1718s_write16(int port, int reg, int val)
+{
+	return rt1718s_write(port, reg, val, 2);
+}
+
+int rt1718s_read16(int port, int reg, int *val)
+{
+	return rt1718s_read(port, reg, val, 2);
+}
+
+int rt1718s_sw_reset(int port)
+{
+	int rv;
+
+	rv = rt1718s_update_bits8(port, RT1718S_SYS_CTRL3, RT1718S_SWRESET_MASK,
+				  0xFF);
+
+	msleep(RT1718S_SW_RESET_DELAY_MS);
+
+	return rv;
+}
+
+static int rt1718s_workaround(int port)
+{
+	int device_id;
+
+	RETURN_ERROR(tcpc_read16(port, RT1718S_DEVICE_ID, &device_id));
+
+	switch (device_id) {
+	case RT1718S_DEVICE_ID_ES1:
+		RETURN_ERROR(rt1718s_update_bits8(
+			port, RT1718S_VCONN_CONTROL_3,
+			RT1718S_VCONN_CONTROL_3_VCONN_OVP_DEG, 0xFF));
+		__fallthrough;
+	case RT1718S_DEVICE_ID_ES2:
+		RETURN_ERROR(rt1718s_update_bits8(
+			port, TCPC_REG_FAULT_CTRL,
+			TCPC_REG_FAULT_CTRL_VCONN_OCP_FAULT_DIS, 0xFF));
+		RETURN_ERROR(rt1718s_update_bits8(
+			port, RT1718S_VCON_CTRL4,
+			RT1718S_VCON_CTRL4_UVP_CP_EN |
+				RT1718S_VCON_CTRL4_OCP_CP_EN,
+			0));
+		RETURN_ERROR(rt1718s_update_bits8(
+			port, RT1718S_VCONN_CONTROL_2,
+			RT1718S_VCONN_CONTROL_2_OVP_EN_CC1 |
+				RT1718S_VCONN_CONTROL_2_OVP_EN_CC2,
+			0xFF));
+		break;
+	default:
+		/* do nothing */
+		break;
+	}
+
+	return EC_SUCCESS;
+}
+
+static int rt1718s_set_vconn(int port, int enable)
+{
+	if (enable) {
+		/*
+		 * b/233698718#comment9: The initial output spike will be likely
+		 * trigger the Vconn OCP. Workaround this by disabling the OCP
+		 * at the beginning of sourcing Vconn, and then enable OCP back
+		 * after Vconn sourced.
+		 */
+		RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_VCON_CTRL3,
+						  RT1718S_VCON_LIMIT_MODE,
+						  0xFF));
+
+		/* Enable Vconn RVP */
+		RETURN_ERROR(rt1718s_update_bits8(
+			port, RT1718S_VCONN_CONTROL_2,
+			RT1718S_VCONN_CONTROL_2_RVP_EN, 0xFF));
+	}
+
+	RETURN_ERROR(tcpci_tcpm_set_vconn(port, enable));
+
+	if (enable) {
+		/* It takes 10ms that we can switch back to shutdown mode. */
+		msleep(10);
+		RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_VCON_CTRL3,
+						  RT1718S_VCON_LIMIT_MODE, 0));
+	} else {
+		/* Disable Vconn RVP */
+		RETURN_ERROR(rt1718s_update_bits8(
+			port, RT1718S_VCONN_CONTROL_2,
+			RT1718S_VCONN_CONTROL_2_RVP_EN, 0x0));
+	}
+
+	return EC_SUCCESS;
+}
+
+static int rt1718s_init(int port)
+{
+	static bool need_sw_reset = true;
+
+	/* Do not reset the TCPC when device is no battery connected, otherwise
+	 * the SINK GPIO to the PPC may be reset, and cause a brown-out.
+	 */
+	need_sw_reset &= battery_is_present() == BP_YES;
+
+	if (!system_jumped_late() && need_sw_reset) {
+		RETURN_ERROR(rt1718s_sw_reset(port));
+		need_sw_reset = false;
+	}
+
+	if (IS_ENABLED(CONFIG_BC12_DETECT_RT1718S))
+		RETURN_ERROR(rt1718s_bc12_init(port));
+
+	/* Set VBUS_VOL_SEL to 20V */
+	RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_RT2_VBUS_VOL_CTRL,
+					  RT1718S_RT2_VBUS_VOL_CTRL_VOL_SEL,
+					  RT1718S_VBUS_VOL_TO_REG(20)));
+
+	/* Set VCONN_OCP_SEL to 400mA */
+	RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_VCONN_CONTROL_3,
+					  RT1718S_VCONN_CONTROL_3_VCONN_OCP_SEL,
+					  0x7F));
+
+	/* Increase the Vconn OCP shoot detection from 200ns to 3~5us */
+	RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_VCON_CTRL4,
+					  RT1718S_VCON_CTRL4_OCP_CP_EN, 0));
+
+	/* Disable FOD function */
+	RETURN_ERROR(rt1718s_update_bits8(port, 0xCF, 0x40, 0x00));
+
+	/* Tcpc connect invalid disabled. Exit shipping mode */
+	RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_SYS_CTRL1,
+					  RT1718S_SYS_CTRL1_TCPC_CONN_INVALID,
+					  0x00));
+	RETURN_ERROR(rt1718s_update_bits8(
+		port, RT1718S_SYS_CTRL1, RT1718S_SYS_CTRL1_SHIPPING_OFF, 0xFF));
+
+	/* Clear alert and fault */
+	RETURN_ERROR(rt1718s_write8(port, TCPC_REG_FAULT_STATUS, 0xFF));
+	RETURN_ERROR(tcpc_write16(port, TCPC_REG_ALERT, 0xFFFF));
+
+	RETURN_ERROR(tcpci_tcpm_init(port));
+
+	RETURN_ERROR(rt1718s_workaround(port));
+	/*
+	 * Set vendor defined alert unmasked, this must be done after
+	 * tcpci_tcpm_init.
+	 */
+	RETURN_ERROR(tcpc_update16(port, TCPC_REG_ALERT_MASK,
+				   TCPC_REG_ALERT_MASK_VENDOR_DEF, MASK_SET));
+
+	if (IS_ENABLED(CONFIG_USB_PD_FRS)) {
+		memset(frs_flag, 0,
+		       sizeof(atomic_t) * CONFIG_USB_PD_PORT_MAX_COUNT);
+		/* Set Rx frs and valid vbus fall unmasked */
+		RETURN_ERROR(rt1718s_update_bits8(
+			port, RT1718S_RT_MASK1,
+			RT1718S_RT_MASK1_M_RX_FRS |
+				RT1718S_RT_MASK1_M_VBUS_FRS_LOW,
+			0xFF));
+	}
+
+	RETURN_ERROR(board_rt1718s_init(port));
+
+	return EC_SUCCESS;
+}
+
+__overridable int board_rt1718s_init(int port)
+{
+	return EC_SUCCESS;
+}
+
+static void frs_gpio_disable_deferred(void)
+{
+	int i;
+
+	for (i = 0; i < board_get_usb_pd_port_count(); ++i) {
+		if (frs_flag[i] & FLAG_FRS_VBUS_VALID_FALL) {
+			atomic_clear_bits(&frs_flag[i],
+					  FLAG_FRS_RX_SIGNALLED |
+						  FLAG_FRS_VBUS_VALID_FALL);
+			/* If the FRS gets enabled again, do not disable it. */
+			if (!(frs_flag[i] & FLAG_FRS_ENABLED))
+				board_rt1718s_set_frs_enable(i, 0);
+		}
+	}
+}
+DECLARE_DEFERRED(frs_gpio_disable_deferred);
+
+void rt1718s_vendor_defined_alert(int port)
+{
+	int rv, value;
+
+	if (IS_ENABLED(CONFIG_USB_PD_FRS)) {
+		int int1;
+
+		rv = rt1718s_read8(port, RT1718S_RT_INT1, &int1);
+		if (rv)
+			return;
+		rv = rt1718s_write8(port, RT1718S_RT_INT1, int1);
+		if (rv)
+			return;
+
+		if ((int1 & RT1718S_RT_INT1_INT_RX_FRS) &&
+		    frs_flag[port] & FLAG_FRS_ENABLED) {
+			/*
+			 * 1. Sometimes we get Rx signalled even if the
+			 * FRS is disabled, so filter it.
+			 * 2. Only call pd_got_frs_signal when this is the first
+			 * Rx interrupt for this FRS swap, and the FRS is
+			 * enabled.  The Rx interrupt may re-send when the
+			 * sink voltage is 5V, and this will make us re-entry
+			 * the FRS states.
+			 * 3. When a FRS hub detached, RT1718S will
+			 * raise FRS RX alert as well. In this case,
+			 * we are unable to audit the errors in time,
+			 * we will still enter the FRS AMS, but it will
+			 * fail eventually, and back to CC open state.
+			 */
+			if (!(frs_flag[port] & FLAG_FRS_RX_SIGNALLED)) {
+				atomic_or(&frs_flag[port],
+					  FLAG_FRS_RX_SIGNALLED);
+				/* notify TCPM we got FRS signal */
+				pd_got_frs_signal(port);
+			}
+		}
+
+		if ((int1 & RT1718S_RT_INT1_INT_VBUS_FRS_LOW)) {
+			/*
+			 * Only process if have had rx signalled.
+			 * VBUS_FRS_LOW alert could be raised multiple times
+			 * if VBUS 5V is glitched.
+			 */
+			if ((frs_flag[port] & FLAG_FRS_RX_SIGNALLED) &&
+			    !(frs_flag[port] & FLAG_FRS_VBUS_VALID_FALL)) {
+				atomic_or(&frs_flag[port],
+					  FLAG_FRS_VBUS_VALID_FALL);
+				/*
+				 * b/223086905:comment8&comment17
+				 * We deferred the FRS disable
+				 * (called to rt1718s_set_frs_enable()), now we
+				 * can disable it after the VBUS fell.
+				 */
+				rt1718s_set_frs_enable(port, 0);
+				/*
+				 * b/228422539:comment4
+				 * PPC HL5099 (pin-compatible to NX20P3483)
+				 * suggested FRS gpio should be disabled after
+				 * the SRC gpio enabled for 5ms to prevent the
+				 * PPC from stopping sourcing the VBUS.
+				 * Thought this is a workaround for HL5099, but
+				 * it shouldn't affect other PPC chips since
+				 * the DUT started sourcing the partner already.
+				 */
+				hook_call_deferred(
+					&frs_gpio_disable_deferred_data,
+					RT1718S_FRS_DIS_DELAY);
+			}
+		}
+
+		/* ignore other interrupts for faster frs handling */
+		if (int1 & (RT1718S_RT_INT1_INT_RX_FRS |
+			    RT1718S_RT_INT1_INT_VBUS_FRS_LOW)) {
+			tcpc_write16(port, TCPC_REG_ALERT,
+				     TCPC_REG_ALERT_VENDOR_DEF);
+			return;
+		}
+	}
+
+	if (IS_ENABLED(CONFIG_BC12_DETECT_RT1718S)) {
+		/* Process BC12 alert */
+		rv = rt1718s_read8(port, RT1718S_RT_INT6, &value);
+		if (rv)
+			return;
+
+		/* clear BC12 alert */
+		rv = rt1718s_write8(port, RT1718S_RT_INT6, value);
+		if (rv)
+			return;
+
+		/* check snk done */
+		if (value & RT1718S_RT_INT6_INT_BC12_SNK_DONE)
+			usb_charger_task_set_event(port, USB_CHG_EVENT_BC12);
+	}
+
+	/* clear the alerts from rt1718s_workaround() */
+	rv = rt1718s_write8(port, RT1718S_RT_INT2, 0xFF);
+	if (rv)
+		return;
+	/* ES1 workaround: disable Vconn discharge */
+	rv = rt1718s_update_bits8(port, RT1718S_SYS_CTRL2,
+				  RT1718S_SYS_CTRL2_VCONN_DISCHARGE_EN, 0);
+	if (rv)
+		return;
+
+	tcpc_write16(port, TCPC_REG_ALERT, TCPC_REG_ALERT_VENDOR_DEF);
+}
+
+__overridable int board_rt1718s_set_snk_enable(int port, int enable)
+{
+	return EC_SUCCESS;
+}
+
+__overridable int board_rt1718s_set_src_enable(int port, int enable)
+{
+	return EC_SUCCESS;
+}
+
+static int rt1718s_tcpm_set_snk_ctrl(int port, int enable)
+{
+	int rv;
+
+	/* The order matters. Board hook should run after the tcpm call to
+	 * prevent the GPIO config auto-reload overwriting a wrong value.
+	 */
+	rv = tcpci_tcpm_set_snk_ctrl(port, enable);
+	if (rv)
+		return rv;
+
+	return board_rt1718s_set_snk_enable(port, enable);
+}
+
+static int rt1718s_tcpm_set_src_ctrl(int port, int enable)
+{
+	int rv;
+
+	/* The order matters. Board hook should run after the tcpm call to
+	 * prevent the GPIO config auto-reload overwriting a wrong value.
+	 */
+	rv = tcpci_tcpm_set_src_ctrl(port, enable);
+	if (rv)
+		return rv;
+
+	return board_rt1718s_set_src_enable(port, enable);
+}
+
+static void rt1718s_alert(int port)
+{
+	int alert;
+
+	tcpc_read16(port, TCPC_REG_ALERT, &alert);
+	if (alert & TCPC_REG_ALERT_VENDOR_DEF)
+		rt1718s_vendor_defined_alert(port);
+
+	if (alert & ~TCPC_REG_ALERT_VENDOR_DEF)
+		tcpci_tcpc_alert(port);
+}
+
+#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
+static int rt1718s_enter_low_power_mode(int port)
+{
+	/* enter low power mode */
+	RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_SYS_CTRL2,
+					  RT1718S_SYS_CTRL2_LPWR_EN, 0xFF));
+	RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_SYS_CTRL2,
+					  RT1718S_SYS_CTRL2_BMCIO_OSC_EN, 0));
+
+	/* disable DP/DM/SBU swtiches */
+	RETURN_ERROR(rt1718s_write8(port, RT1718S_RT2_SBU_CTRL_01, 0));
+
+	return tcpci_enter_low_power_mode(port);
+}
+#endif
+
+int rt1718s_get_adc(int port, enum rt1718s_adc_channel channel, int *adc_val)
+{
+	int rv;
+	const int max_wait_times = 30;
+
+	if (in_interrupt_context()) {
+		CPRINTS("Err: use ADC in IRQ");
+		return EC_ERROR_INVAL;
+	}
+
+	mutex_lock(&adc_lock);
+
+	/* Start ADC conversation */
+	rv = rt1718s_write16(port, RT1718S_ADC_CTRL_01, BIT(channel));
+	if (rv)
+		goto out;
+
+	/*
+	 * The expected conversion time is 85.3us * number of enabled channels.
+	 * Polling for 3ms should be long enough.
+	 */
+	for (int i = 0; i < max_wait_times; i++) {
+		int adc_done;
+
+		usleep(100);
+		rv = rt1718s_read8(port, RT1718S_RT_INT6, &adc_done);
+		if (rv)
+			goto out;
+		if (adc_done & RT1718S_RT_INT6_INT_ADC_DONE)
+			break;
+		if (i == max_wait_times - 1) {
+			CPRINTS("conversion fail channel=%d", channel);
+			rv = EC_ERROR_TIMEOUT;
+			goto out;
+		}
+	}
+
+	/* Read ADC data */
+	rv = rt1718s_read16(port, RT1718S_ADC_CHX_VOL_L(channel), adc_val);
+	if (rv)
+		goto out;
+
+	/*
+	 * The resolution of VBUS1 ADC is 12.5mV,
+	 * other channels are 4mV.
+	 */
+	if (channel == RT1718S_ADC_VBUS1)
+		*adc_val = *adc_val * 125 / 10;
+	else
+		*adc_val *= 4;
+
+out:
+	/* Cleanup: disable adc and clear interrupt. Error ignored. */
+	rt1718s_write16(port, RT1718S_ADC_CTRL_01, 0);
+	rt1718s_write8(port, RT1718S_RT_INT6, RT1718S_RT_INT6_INT_ADC_DONE);
+
+	mutex_unlock(&adc_lock);
+	return rv;
+}
+
+#ifdef CONFIG_USB_PD_FRS
+
+__overridable int board_rt1718s_set_frs_enable(int port, int enable)
+{
+	return EC_SUCCESS;
+}
+
+int rt1718s_set_frs_enable(int port, int enable)
+{
+	/*
+	 * Use write instead of update to save 2 i2c read.
+	 * Assume other bits are at their reset value.
+	 */
+	int frs_ctrl2 = 0x10, vbus_ctrl_en = 0x3F;
+
+	if (enable) {
+		atomic_or(&frs_flag[port], FLAG_FRS_ENABLED);
+		frs_ctrl2 |= RT1718S_FRS_CTRL2_RX_FRS_EN;
+		frs_ctrl2 |= RT1718S_FRS_CTRL2_VBUS_FRS_EN;
+
+		vbus_ctrl_en |= RT1718S_VBUS_CTRL_EN_GPIO2_VBUS_PATH_EN;
+		vbus_ctrl_en |= RT1718S_VBUS_CTRL_EN_GPIO1_VBUS_PATH_EN;
+	} else {
+		atomic_clear_bits(&frs_flag[port], FLAG_FRS_ENABLED);
+		if (FLAG_FRS_RX_SIGNALLED ==
+		    (frs_flag[port] &
+		     (FLAG_FRS_RX_SIGNALLED | FLAG_FRS_VBUS_VALID_FALL))) {
+			/*
+			 * Skip disable if we had only FRS_RX_SIGNALLED, and
+			 * deferred the FRS register disable process in
+			 * rt1718s_vendor_defined_alert.
+			 */
+			return EC_SUCCESS;
+		}
+	}
+
+	RETURN_ERROR(rt1718s_write8(port, RT1718S_FRS_CTRL2, frs_ctrl2));
+	RETURN_ERROR(rt1718s_write8(port, RT1718S_VBUS_CTRL_EN, vbus_ctrl_en));
+
+	/*
+	 * b/223086905#comment13, b/228422539:comment4
+	 * If this function gets called when FRS RX signalled, then
+	 * we'll deferred the GPIO disabled until the VBUS valid drop. So
+	 * don't disable it here.
+	 */
+	if (enable || !(frs_flag[port] & FLAG_FRS_RX_SIGNALLED))
+		RETURN_ERROR(board_rt1718s_set_frs_enable(port, enable));
+
+	return EC_SUCCESS;
+}
+#endif
+
+void rt1718s_gpio_set_flags(int port, enum rt1718s_gpio signal, uint32_t flags)
+{
+	int val = 0;
+
+	if (!(flags & GPIO_OPEN_DRAIN))
+		val |= RT1718S_GPIO_CTRL_OD_N;
+	if (flags & GPIO_PULL_UP)
+		val |= RT1718S_GPIO_CTRL_PU;
+	if (flags & GPIO_PULL_DOWN)
+		val |= RT1718S_GPIO_CTRL_PD;
+	if (flags & GPIO_HIGH)
+		val |= RT1718S_GPIO_CTRL_O;
+	if (flags & GPIO_OUTPUT)
+		val |= RT1718S_GPIO_CTRL_OE;
+
+	rt1718s_write8(port, RT1718S_GPIO_CTRL(signal), val);
+}
+
+void rt1718s_gpio_set_level(int port, enum rt1718s_gpio signal, int value)
+{
+	rt1718s_update_bits8(port, RT1718S_GPIO_CTRL(signal),
+			     RT1718S_GPIO_CTRL_O, value ? 0xFF : 0);
+}
+
+int rt1718s_gpio_get_level(int port, enum rt1718s_gpio signal)
+{
+	int val;
+
+	rt1718s_read8(port, RT1718S_GPIO_CTRL(signal), &val);
+	return !!(val & RT1718S_GPIO_CTRL_I);
+}
+
+static int command_rt1718s_gpio(int argc, const char **argv)
+{
+	int i, j;
+	uint32_t flags;
+
+	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+		if (tcpc_config[i].drv != &rt1718s_tcpm_drv)
+			continue;
+
+		for (j = 0; j < RT1718S_GPIO_COUNT; j++) {
+			int rv;
+
+			rv = rt1718s_read8(i, RT1718S_GPIO_CTRL(j), &flags);
+			if (rv)
+				return EC_ERROR_UNKNOWN;
+
+			ccprintf("C%d GPIO%d OD=%d PU=%d PD=%d OE=%d HL=%d\n",
+				 i, j + 1, !(flags & RT1718S_GPIO_CTRL_OD_N),
+				 !!(flags & RT1718S_GPIO_CTRL_PU),
+				 !!(flags & RT1718S_GPIO_CTRL_PD),
+				 !!(flags & RT1718S_GPIO_CTRL_OE),
+				 !!(flags & RT1718S_GPIO_CTRL_O));
+		}
+	}
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(rt1718s_gpio, command_rt1718s_gpio, "", "RT1718S GPIO");
+
+#ifdef CONFIG_USB_PD_TCPM_SBU
+static int rt1718s_set_sbu(int port, bool enable)
+{
+	/*
+	 * The `enable` here means to enable the SBU line (set 1)
+	 * - true: connect SBU lines from outer to the host
+	 * - false: isolate the SBU lines
+	 */
+	return rt1718s_update_bits8(port, RT1718S_RT2_SBU_CTRL_01,
+				    RT1718S_RT2_SBU_CTRL_01_SBU_VIEN |
+					    RT1718S_RT2_SBU_CTRL_01_SBU1_SWEN |
+					    RT1718S_RT2_SBU_CTRL_01_SBU2_SWEN,
+				    enable ? 0xFF : 0);
+}
+#endif
+
+/* RT1718S is a TCPCI compatible port controller */
+const struct tcpm_drv rt1718s_tcpm_drv = {
+	.init = &rt1718s_init,
+	.release = &tcpci_tcpm_release,
+	.get_cc = &tcpci_tcpm_get_cc,
+#ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
+	.check_vbus_level = &tcpci_tcpm_check_vbus_level,
+#endif
+	.select_rp_value = &tcpci_tcpm_select_rp_value,
+	.set_cc = &tcpci_tcpm_set_cc,
+	.set_polarity = &tcpci_tcpm_set_polarity,
+#ifdef CONFIG_USB_PD_DECODE_SOP
+	.sop_prime_enable = &tcpci_tcpm_sop_prime_enable,
+#endif
+	.set_vconn = &rt1718s_set_vconn,
+	.set_msg_header = &tcpci_tcpm_set_msg_header,
+	.set_rx_enable = &tcpci_tcpm_set_rx_enable,
+	.get_message_raw = &tcpci_tcpm_get_message_raw,
+	.transmit = &tcpci_tcpm_transmit,
+	.tcpc_alert = &rt1718s_alert,
+#ifdef CONFIG_USB_PD_DISCHARGE_TCPC
+	.tcpc_discharge_vbus = &tcpci_tcpc_discharge_vbus,
+#endif
+#ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+	.drp_toggle = &tcpci_tcpc_drp_toggle,
+#endif
+	.get_chip_info = &tcpci_get_chip_info,
+	.set_snk_ctrl = &rt1718s_tcpm_set_snk_ctrl,
+	.set_src_ctrl = &rt1718s_tcpm_set_src_ctrl,
+#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
+	.enter_low_power_mode = &rt1718s_enter_low_power_mode,
+#endif
+#ifdef CONFIG_USB_PD_FRS_TCPC
+	.set_frs_enable = &rt1718s_set_frs_enable,
+#endif
+	.set_bist_test_mode = &tcpci_set_bist_test_mode,
+	.get_bist_test_mode = &tcpci_get_bist_test_mode,
+#ifdef CONFIG_USB_PD_TCPM_SBU
+	.set_sbu = &rt1718s_set_sbu,
+#endif
+};
diff --git a/driver/tcpm/rt1718s.h b/driver/tcpm/rt1718s.h
new file mode 100644
index 0000000000..d036c6901a
--- /dev/null
+++ b/driver/tcpm/rt1718s.h
@@ -0,0 +1,286 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#ifndef __CROS_EC_USB_PD_TCPM_RT1718S_H
+#define __CROS_EC_USB_PD_TCPM_RT1718S_H
+
+#include "tcpm/rt1718s_public.h"
+#include "usb_charge.h"
+#include "usb_pd_tcpm.h"
+#include "util.h"
+
+/* RT1718S Private RegMap */
+#define RT1718S_PHYCTRL1 0x80
+#define RT1718S_PHYCTRL2 0x81
+#define RT1718S_PHYCTRL3 0x82
+#define RT1718S_PHYCTRL7 0x86
+#define RT1718S_VCON_CTRL1 0x8A
+#define RT1718S_VCON_CTRL3 0x8C
+#define RT1718S_VCON_LIMIT_MODE BIT(0)
+#define RT1718S_SYS_CTRL1 0x8F
+#define RT1718S_SYS_CTRL1_TCPC_CONN_INVALID BIT(6)
+#define RT1718S_SYS_CTRL1_SHIPPING_OFF BIT(5)
+#define RT1718S_SYS_CTRL2 0x90
+#define RT1718S_SYS_CTRL2_BMCIO_OSC_EN BIT(0)
+#define RT1718S_SYS_CTRL2_LPWR_EN BIT(3)
+
+#define RT1718S_VCONN_CONTROL_2 0x8B
+#define RT1718S_VCONN_CONTROL_2_OVP_EN_CC1 BIT(7)
+#define RT1718S_VCONN_CONTROL_2_OVP_EN_CC2 BIT(6)
+#define RT1718S_VCONN_CONTROL_2_RVP_EN BIT(3)
+#define RT1718S_VCONN_CONTROL_3 0x8C
+#define RT1718S_VCONN_CONTROL_3_VCONN_OCP_SEL GENMASK(7, 5)
+#define RT1718S_VCONN_CONTROL_3_VCONN_OVP_DEG BIT(1)
+
+#define RT1718S_SYS_CTRL2 0x90
+#define RT1718S_SYS_CTRL2_VCONN_DISCHARGE_EN BIT(5)
+
+#define RT1718S_RT_MASK1 0x91
+#define RT1718S_RT_MASK1_M_VBUS_FRS_LOW BIT(7)
+#define RT1718S_RT_MASK1_M_RX_FRS BIT(6)
+#define RT1718S_RT_MASK2 0x92
+#define RT1718S_RT_MASK3 0x93
+#define RT1718S_RT_MASK4 0x94
+#define RT1718S_RT_MASK5 0x95
+#define RT1718S_RT_MASK6 0x96
+#define RT1718S_RT_MASK6_M_BC12_SNK_DONE BIT(7)
+#define RT1718S_RT_MASK6_M_HVDCP_CHK_DONE BIT(6)
+#define RT1718S_RT_MASK6_M_BC12_TA_CHG BIT(5)
+#define RT1718S_RT_MASK7 0x97
+
+#define RT1718S_RT_INT1 0x98
+#define RT1718S_RT_INT1_INT_VBUS_FRS_LOW BIT(7)
+#define RT1718S_RT_INT1_INT_RX_FRS BIT(6)
+#define RT1718S_RT_INT2 0x99
+#define RT1718S_RT_INT6 0x9D
+#define RT1718S_RT_INT6_INT_BC12_SNK_DONE BIT(7)
+#define RT1718S_RT_INT6_INT_HVDCP_CHK_DONE BIT(6)
+#define RT1718S_RT_INT6_INT_BC12_TA_CHG BIT(5)
+#define RT1718S_RT_INT6_INT_ADC_DONE BIT(0)
+
+#define RT1718S_RT_ST6 0xA4
+#define RT1718S_RT_ST6_BC12_SNK_DONE BIT(7)
+#define RT1718S_RT_ST6_HVDCP_CHK_DONE BIT(6)
+#define RT1718S_RT_ST6_BC12_TA_CHG BIT(5)
+
+#define RT1718S_PHYCTRL9 0xAC
+
+#define RT1718S_SYS_CTRL3 0xB0
+#define RT1718S_TCPC_CTRL1 0xB1
+#define RT1718S_TCPC_CTRL2 0xB2
+#define RT1718S_TCPC_CTRL3 0xB3
+#define RT1718S_SWRESET_MASK BIT(0)
+#define RT1718S_TCPC_CTRL4 0xB4
+#define RT1718S_SYS_CTRL4 0xB8
+#define RT1718S_WATCHDOG_CTRL 0xBE
+#define RT1718S_I2C_RST_CTRL 0xBF
+
+#define RT1718S_HILO_CTRL9 0xC8
+#define RT1718S_SHILED_CTRL1 0xCA
+#define RT1718S_FRS_CTRL1 0xCB
+#define RT1718S_FRS_CTRL1_FRSWAPRX_MASK 0xF0
+#define RT1718S_FRS_CTRL2 0xCC
+#define RT1718S_FRS_CTRL2_RX_FRS_EN BIT(6)
+#define RT1718S_FRS_CTRL2_FR_VBUS_SELECT BIT(4)
+#define RT1718S_FRS_CTRL2_VBUS_FRS_EN BIT(3)
+#define RT1718S_FRS_CTRL3 0xCE
+#define RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO2 BIT(3)
+#define RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO1 BIT(2)
+
+#define RT1718S_DIS_SRC_VBUS_CTRL 0xE0
+#define RT1718S_ENA_SRC_VBUS_CTRL 0xE1
+#define RT1718S_FAULT_OC1_VBUS_CTRL 0xE3
+#define RT1718S_GPIO1_VBUS_CTRL 0xEA
+#define RT1718S_GPIO_VBUS_CTRL_FRS_RX_VBUS BIT(6)
+#define RT1718S_GPIO_VBUS_CTRL_FRS_TX_VBUS BIT(5)
+#define RT1718S_GPIO_VBUS_CTRL_ENA_SRC_HV_VBUS_GPIO BIT(4)
+#define RT1718S_GPIO_VBUS_CTRL_ENA_SRC_VBUS_GPIO BIT(3)
+#define RT1718S_GPIO_VBUS_CTRL_DIS_SRC_VBUS_GPIO BIT(2)
+#define RT1718S_GPIO_VBUS_CTRL_ENA_SNK_VBUS_GPIO BIT(1)
+#define RT1718S_GPIO_VBUS_CTRL_DIS_SNK_VBUS_GPIO BIT(0)
+#define RT1718S_GPIO2_VBUS_CTRL 0xEB
+#define RT1718S_VBUS_CTRL_EN 0xEC
+#define RT1718S_VBUS_CTRL_EN_GPIO2_VBUS_PATH_EN BIT(7)
+#define RT1718S_VBUS_CTRL_EN_GPIO1_VBUS_PATH_EN BIT(6)
+
+#define RT1718S_GPIO_CTRL(n) (0xED + (n))
+#define RT1718S_GPIO_CTRL_PU BIT(5)
+#define RT1718S_GPIO_CTRL_PD BIT(4)
+#define RT1718S_GPIO_CTRL_OD_N BIT(3)
+#define RT1718S_GPIO_CTRL_OE BIT(2)
+#define RT1718S_GPIO_CTRL_O BIT(1)
+#define RT1718S_GPIO_CTRL_I BIT(0)
+
+#define RT1718S_UNLOCK_PW_2 0xF0
+#define RT1718S_UNLOCK_PW_1 0xF1
+
+#define RT1718S_RT2 0xF2
+
+#define RT1718S_RT2_SYS_CTRL5 0xF210
+
+#define RT1718S_VBUS_VOL_TO_REG(_vol) (CLAMP(_vol, 5, 20) - 5)
+#define RT1718S_VBUS_PCT_TO_REG(_pct) (CLAMP(_pct, 5, 20) / 5 - 1)
+#define RT1718S_RT2_VBUS_VOL_CTRL 0xF213
+#define RT1718S_RT2_VBUS_VOL_CTRL_OVP_SEL (BIT(5) | BIT(4))
+#define RT1718S_RT2_VBUS_VOL_CTRL_VOL_SEL 0x0F
+
+#define RT1718S_VCON_CTRL4 0xF211
+#define RT1718S_VCON_CTRL4_UVP_CP_EN BIT(5)
+#define RT1718S_VCON_CTRL4_OCP_CP_EN BIT(4)
+
+#define RT1718S_RT2_VBUS_OCRC_EN 0xF214
+#define RT1718S_RT2_VBUS_OCRC_EN_VBUS_OCP1_EN BIT(0)
+#define RT1718S_RT2_VBUS_OCP_CTRL1 0xF216
+#define RT1718S_RT2_VBUS_OCP_CTRL4 0xF219
+
+#define RT1718S_RT2_SBU_CTRL_01 0xF23A
+#define RT1718S_RT2_SBU_CTRL_01_SBU_VIEN BIT(7)
+#define RT1718S_RT2_SBU_CTRL_01_DPDM_VIEN BIT(6)
+#define RT1718S_RT2_SBU_CTRL_01_SBU2_SWEN BIT(3)
+#define RT1718S_RT2_SBU_CTRL_01_SBU1_SWEN BIT(2)
+#define RT1718S_RT2_SBU_CTRL_01_DM_SWEN BIT(1)
+#define RT1718S_RT2_SBU_CTRL_01_DP_SWEN BIT(0)
+
+#define RT1718S_RT2_BC12_SNK_FUNC 0xF260
+#define RT1718S_RT2_BC12_SNK_FUNC_BC12_SNK_EN BIT(7)
+#define RT1718S_RT2_BC12_SNK_FUNC_SPEC_TA_EN BIT(6)
+#define RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_MASK 0x30
+#define RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_DISABLE 0x00
+#define RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_300MS 0x10
+#define RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_600MS 0x20
+#define RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_WAIT_DATA 0x30
+#define RT1718S_RT2_BC12_SNK_FUNC_VLGC_OPT BIT(3)
+#define RT1718S_RT2_BC12_SNK_FUNC_VPORT_SEL BIT(2)
+#define RT1718S_RT2_BC12_SNK_FUNC_BC12_WAIT_VBUS BIT(1)
+
+#define RT1718S_RT2_BC12_STAT 0xF261
+#define RT1718S_RT2_BC12_STAT_DCDT BIT(4)
+#define RT1718S_RT2_BC12_STAT_PORT_STATUS_MASK 0x0F
+#define RT1718S_RT2_BC12_STAT_PORT_STATUS_NONE 0x00
+#define RT1718S_RT2_BC12_STAT_PORT_STATUS_SDP 0x0D
+#define RT1718S_RT2_BC12_STAT_PORT_STATUS_CDP 0x0E
+#define RT1718S_RT2_BC12_STAT_PORT_STATUS_DCP 0x0F
+
+#define RT1718S_RT2_DPDM_CTR1_DPDM_SET 0xF263
+#define RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_MASK 0x03
+#define RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_0_55V 0x00
+#define RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_0_60V 0x01
+#define RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_0_65V 0x02
+#define RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_0_70V 0x03
+
+#define RT1718S_RT2_BC12_SRC_FUNC 0xF26D
+#define RT1718S_RT2_BC12_SRC_FUNC_BC12_SRC_EN BIT(7)
+#define RT1718S_RT2_BC12_SRC_FUNC_SRC_MODE_SEL_MASK 0x70
+#define RT1718S_RT2_BC12_SRC_FUNC_SRC_MODE_SEL_BC12_SDP 0x00
+#define RT1718S_RT2_BC12_SRC_FUNC_SRC_MODE_SEL_BC12_CDP 0x10
+#define RT1718S_RT2_BC12_SRC_FUNC_SRC_MODE_SEL_BC12_DCP 0x20
+#define RT1718S_RT2_BC12_SRC_FUNC_WAIT_VBUS_ON BIT(0)
+
+#define RT1718S_ADC_CTRL_01 0xF2A0
+#define RT1718S_ADC_CTRL_02 0xF2A1
+#define RT1718S_ADC_CHX_VOL_L(ch) (0xF2A6 + (ch)*2)
+#define RT1718S_ADC_CHX_VOL_H(ch) (0xF2A7 + (ch)*2)
+
+int rt1718s_write8(int port, int reg, int val);
+int rt1718s_read8(int port, int reg, int *val);
+int rt1718s_update_bits8(int port, int reg, int mask, int val);
+int rt1718s_write16(int port, int reg, int val);
+int rt1718s_read16(int port, int reg, int *val);
+__override_proto int board_rt1718s_init(int port);
+
+enum rt1718s_adc_channel {
+	RT1718S_ADC_VBUS1 = 0,
+	RT1718S_ADC_VBUS2,
+	RT1718S_ADC_VDC,
+	RT1718S_ADC_VBUS_CURRENT,
+	RT1718S_ADC_CC1,
+	RT1718S_ADC_CC2,
+	RT1718S_ADC_SBU1,
+	RT1718S_ADC_SBU2,
+	RT1718S_ADC_DP,
+	RT1718S_ADC_DM,
+	RT1718S_ADC_CH10,
+	RT1718S_ADC_CH11,
+};
+
+int rt1718s_get_adc(int port, enum rt1718s_adc_channel channel, int *adc_val);
+
+enum rt1718s_gpio {
+	RT1718S_GPIO1 = 0,
+	RT1718S_GPIO2,
+	RT1718S_GPIO3,
+	RT1718S_GPIO_COUNT,
+};
+
+/**
+ * Set flags for GPIO
+ *
+ * @param port		rt1718s I2C port
+ * @param signal	gpio pin name in enum rt1718s_gpio
+ * @param flags		GPIO_* flags defined in include/gpio.h
+ */
+void rt1718s_gpio_set_flags(int port, enum rt1718s_gpio signal, uint32_t flags);
+
+/**
+ * Set the value of a signal
+ *
+ * @param port		rt1718s I2C port
+ * @param signal	gpio pin name in enum rt1718s_gpio
+ * @param value		New value for signal (0 = low, non-zero = high)
+ */
+void rt1718s_gpio_set_level(int port, enum rt1718s_gpio signal, int value);
+
+/**
+ * Get the current value of a signal.
+ *
+ * @param port		rt1718s I2C port
+ * @param signal	gpio pin name in enum rt1718s_gpio
+ * @return 0 if low, 1 if high.
+ */
+int rt1718s_gpio_get_level(int port, enum rt1718s_gpio signal);
+
+/**
+ * Set fast role swap.
+ *
+ * @param port		USB-C port
+ * @param enable	enable/disable FRS
+ * @return EC_SUCCESS if success, EC_ERROR_UNKNOWN otherwise.
+ */
+int rt1718s_set_frs_enable(int port, int enable);
+
+/**
+ * Board override for fast role swap.
+ *
+ * @param port		USB-C port
+ * @param enable	enable/disable FRS
+ * @return EC_SUCCESS if success, EC_ERROR_UNKNOWN otherwise.
+ */
+__override_proto int board_rt1718s_set_frs_enable(int port, int enable);
+
+/**
+ * Software reset RT1718S
+ *
+ * @param port		USB-C port
+ * @return EC_SUCCESS if success, EC_ERROR_UNKNOWN otherwise.
+ */
+int rt1718s_sw_reset(int port);
+
+/**
+ * Board hook for rt1718s_set_snk_enable
+ *
+ * @param port		USB-C port
+ * @param enable	enable/disable sink
+ * @return EC_SUCCESS if success, EC_ERROR_UNKNOWN otherwise.
+ */
+__override_proto int board_rt1718s_set_snk_enable(int port, int enable);
+
+/**
+ * Board hook for rt1718s_set_src_enable
+ *
+ * @param port		USB-C port
+ * @param enable	enable/disable source
+ * @return EC_SUCCESS if success, EC_ERROR_UNKNOWN otherwise.
+ */
+__override_proto int board_rt1718s_set_src_enable(int port, int enable);
+#endif /* __CROS_EC_USB_PD_TCPM_MT6370_H */
diff --git a/driver/tcpm/stm32gx.c b/driver/tcpm/stm32gx.c
index 88109329dc..029570faca 100644
--- a/driver/tcpm/stm32gx.c
+++ b/driver/tcpm/stm32gx.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,22 +9,30 @@
 #include "common.h"
 #include "config.h"
 #include "console.h"
+#include "hooks.h"
 #include "registers.h"
 #include "stm32gx.h"
 #include "system.h"
 #include "task.h"
-#include "tcpci.h"
+#include "tcpm/tcpci.h"
 #include "timer.h"
-#include "util.h"
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
-#include "hooks.h"
+#include "util.h"
 
-#if defined(CONFIG_USB_PD_VBUS_DETECT_TCPC) || \
-	defined(CONFIG_USB_PD_TCPC_LOW_POWER)
+/*
+ * STM32G4 UCPD peripheral does not have the ability to detect VBUS, but
+ * CONFIG_USB_PD_VBUS_DETECT_TCPC maybe still be defined for another port on the
+ * same board which uses a TCPC that does have this feature. Therefore, this
+ * config option is not considered an error.
+ */
+#if defined(CONFIG_USB_PD_TCPC_LOW_POWER)
 #error "Unsupported config options of Stm32gx PD driver"
 #endif
 
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
 /* Wait time for vconn power switch to turn off. */
 #ifndef PD_STM32GX_VCONN_TURN_OFF_DELAY_US
 #define PD_STM32GX_VCONN_TURN_OFF_DELAY_US 500
@@ -32,11 +40,9 @@
 
 static int cached_rp[CONFIG_USB_PD_PORT_MAX_COUNT];
 
-
 static int stm32gx_tcpm_get_message_raw(int port, uint32_t *buf, int *head)
 {
-	/* TODO(b/167601672): Need to implement this for USB-PD support */
-	return EC_SUCCESS;
+	return stm32gx_ucpd_get_message_raw(port, buf, head);
 }
 
 static int stm32gx_tcpm_init(int port)
@@ -50,7 +56,7 @@ static int stm32gx_tcpm_release(int port)
 }
 
 static int stm32gx_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2)
+			       enum tcpc_cc_voltage_status *cc2)
 {
 	/* Get cc_state value for each CC line */
 	stm32gx_ucpd_get_cc(port, cc1, cc2);
@@ -77,47 +83,40 @@ static int stm32gx_tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity)
 
 static int stm32gx_tcpm_set_vconn(int port, int enable)
 {
-	/*
-	 * TODO(b/167601672): VCONN is not provided by ucpd peripheral, so the
-	 * only action required here will be to remove Rp from the CC line that
-	 * is supplying VCONN.
-	 */
+	stm32gx_ucpd_vconn_disc_rp(port, enable);
+
+	if (IS_ENABLED(CONFIG_USB_PD_DECODE_SOP))
+		stm32gx_ucpd_sop_prime_enable(port, enable);
+
 	return EC_SUCCESS;
 }
 
 static int stm32gx_tcpm_set_msg_header(int port, int power_role, int data_role)
 {
-	/* TODO(b/167601672): Need to implement this for USB-PD support */
-	return EC_SUCCESS;
+	return stm32gx_ucpd_set_msg_header(port, power_role, data_role);
 }
 
 static int stm32gx_tcpm_set_rx_enable(int port, int enable)
 {
-	/* TODO(b/167601672): Need to implement this for USB-PD support */
-	return EC_SUCCESS;
+	return stm32gx_ucpd_set_rx_enable(port, enable);
 }
 
-static int stm32gx_tcpm_transmit(int port,
-			enum tcpm_transmit_type type,
-			uint16_t header,
-			const uint32_t *data)
+static int stm32gx_tcpm_transmit(int port, enum tcpci_msg_type type,
+				 uint16_t header, const uint32_t *data)
 {
-	/* TODO(b/167601672): Need to implement this for USB-PD support */
-	return EC_SUCCESS;
+	return stm32gx_ucpd_transmit(port, type, header, data);
 }
 
-static int stm32gx_tcpm_sop_prime_disable(int port)
+static int stm32gx_tcpm_sop_prime_enable(int port, bool enable)
 {
-	/* TODO(b/167601672): Need to implement this for USB-PD support */
-	return EC_SUCCESS;
+	return stm32gx_ucpd_sop_prime_enable(port, enable);
 }
 
-
-static int stm32gx_tcpm_get_chip_info(int port, int live,
-			struct ec_response_pd_chip_info_v1 *chip_info)
+static int
+stm32gx_tcpm_get_chip_info(int port, int live,
+			   struct ec_response_pd_chip_info_v1 *chip_info)
 {
-	/* TODO(b/167601672): Need to implement this for USB-PD support */
-	return EC_SUCCESS;
+	return stm32gx_ucpd_get_chip_info(port, live, chip_info);
 }
 
 static void stm32gx_tcpm_sw_reset(void)
@@ -130,21 +129,55 @@ static void stm32gx_tcpm_sw_reset(void)
 }
 DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, stm32gx_tcpm_sw_reset, HOOK_PRIO_DEFAULT);
 
+static int stm32gx_tcpm_reset_bist_type_2(int port)
+{
+	/*
+	 * The UCPD peripheral must be disabled, then enabled, to recover from
+	 * starting BIST type-2 mode. Call the init method to accomplish
+	 * this. Then, need to send a hard reset to port partner.
+	 */
+	stm32gx_ucpd_init(port);
+	pd_execute_hard_reset(port);
+	task_set_event(PD_PORT_TO_TASK_ID(port), TASK_EVENT_WAKE);
+
+	return EC_SUCCESS;
+}
+
+enum ec_error_list stm32gx_tcpm_set_bist_test_mode(const int port,
+						   const bool enable)
+{
+	return stm32gx_ucpd_set_bist_test_mode(port, enable);
+}
+
+bool stm32gx_tcpm_check_vbus_level(int port, enum vbus_level level)
+{
+	/*
+	 * UCPD peripheral can't detect VBUS, so always return 0. Any port which
+	 * uses the stm32g4 UCPD peripheral for its TCPC would also have a PPC
+	 * that will handle VBUS detection. However, there may be products which
+	 * don't have a PPC on some ports that will rely on a TCPC to do VBUS
+	 * detection.
+	 */
+	return 0;
+}
+
 const struct tcpm_drv stm32gx_tcpm_drv = {
-	.init			= &stm32gx_tcpm_init,
-	.release		= &stm32gx_tcpm_release,
-	.get_cc			= &stm32gx_tcpm_get_cc,
-	.select_rp_value	= &stm32gx_tcpm_select_rp_value,
-	.set_cc			= &stm32gx_tcpm_set_cc,
-	.set_polarity		= &stm32gx_tcpm_set_polarity,
+	.init = &stm32gx_tcpm_init,
+	.release = &stm32gx_tcpm_release,
+	.get_cc = &stm32gx_tcpm_get_cc,
+	.check_vbus_level = &stm32gx_tcpm_check_vbus_level,
+	.select_rp_value = &stm32gx_tcpm_select_rp_value,
+	.set_cc = &stm32gx_tcpm_set_cc,
+	.set_polarity = &stm32gx_tcpm_set_polarity,
 #ifdef CONFIG_USB_PD_DECODE_SOP
-       .sop_prime_disable      = &stm32gx_tcpm_sop_prime_disable,
+	.sop_prime_enable = &stm32gx_tcpm_sop_prime_enable,
 #endif
-
-	.set_vconn		= &stm32gx_tcpm_set_vconn,
-	.set_msg_header		= &stm32gx_tcpm_set_msg_header,
-	.set_rx_enable		= &stm32gx_tcpm_set_rx_enable,
-	.get_message_raw	= &stm32gx_tcpm_get_message_raw,
-	.transmit		= &stm32gx_tcpm_transmit,
-	.get_chip_info		= &stm32gx_tcpm_get_chip_info,
+	.set_vconn = &stm32gx_tcpm_set_vconn,
+	.set_msg_header = &stm32gx_tcpm_set_msg_header,
+	.set_rx_enable = &stm32gx_tcpm_set_rx_enable,
+	.get_message_raw = &stm32gx_tcpm_get_message_raw,
+	.transmit = &stm32gx_tcpm_transmit,
+	.get_chip_info = &stm32gx_tcpm_get_chip_info,
+	.reset_bist_type_2 = &stm32gx_tcpm_reset_bist_type_2,
+	.set_bist_test_mode = &stm32gx_tcpm_set_bist_test_mode,
 };
diff --git a/driver/tcpm/stm32gx.h b/driver/tcpm/stm32gx.h
index de6a803d52..a8a1e1a1be 100644
--- a/driver/tcpm/stm32gx.h
+++ b/driver/tcpm/stm32gx.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,8 +7,6 @@
 #ifndef __CROS_EC_DRIVER_TCPM_STM32GX_H
 #define __CROS_EC_DRIVER_TCPM_STM32GX_H
 
-
 extern const struct tcpm_drv stm32gx_tcpm_drv;
 
-
 #endif /* __CROS_EC_DRIVER_TCPM_STM32GX_H */
diff --git a/driver/tcpm/stub.c b/driver/tcpm/stub.c
index 75a9c9ced6..b28d436b51 100644
--- a/driver/tcpm/stub.c
+++ b/driver/tcpm/stub.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,8 +6,8 @@
 /* TCPM for MCU also running TCPC */
 
 #include "task.h"
-#include "tcpci.h"
-#include "tcpm.h"
+#include "tcpm/tcpci.h"
+#include "tcpm/tcpm.h"
 #include "usb_pd.h"
 #include "usb_pd_tcpc.h"
 #include "usb_pd_tcpm.h"
@@ -22,8 +22,8 @@ static int init_alert_mask(int port)
 	 * signal the TCPM via the Alert# gpio line.
 	 */
 	mask = TCPC_REG_ALERT_TX_SUCCESS | TCPC_REG_ALERT_TX_FAILED |
-		TCPC_REG_ALERT_TX_DISCARDED | TCPC_REG_ALERT_RX_STATUS |
-		TCPC_REG_ALERT_RX_HARD_RST | TCPC_REG_ALERT_CC_STATUS;
+	       TCPC_REG_ALERT_TX_DISCARDED | TCPC_REG_ALERT_RX_STATUS |
+	       TCPC_REG_ALERT_RX_HARD_RST | TCPC_REG_ALERT_CC_STATUS;
 	/* Set the alert mask in TCPC */
 	rv = tcpc_alert_mask_set(port, mask);
 
@@ -48,7 +48,7 @@ int tcpm_init(int port)
 }
 
 int tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2)
+		enum tcpc_cc_voltage_status *cc2)
 {
 	return tcpc_get_cc(port, cc1, cc2);
 }
@@ -65,7 +65,7 @@ int tcpm_set_cc(int port, int pull)
 
 int tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity)
 {
-	return tcpc_set_polarity(port, polarity);
+	return tcpc_set_polarity(port, polarity_rm_dts(polarity));
 }
 
 int tcpm_set_vconn(int port, int enable)
@@ -113,7 +113,7 @@ void tcpm_clear_pending_messages(int port)
 	rx_buf_clear(port);
 }
 
-int tcpm_transmit(int port, enum tcpm_transmit_type type, uint16_t header,
+int tcpm_transmit(int port, enum tcpci_msg_type type, uint16_t header,
 		  const uint32_t *data)
 {
 	return tcpc_transmit(port, type, header, data);
@@ -136,7 +136,7 @@ void tcpc_alert(int port)
 
 	if (status & TCPC_REG_ALERT_CC_STATUS) {
 		/* CC status changed, wake task */
-		task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_CC, 0);
+		task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_CC);
 	}
 	if (status & TCPC_REG_ALERT_RX_STATUS) {
 		/*
@@ -148,12 +148,12 @@ void tcpc_alert(int port)
 	if (status & TCPC_REG_ALERT_RX_HARD_RST) {
 		/* hard reset received */
 		task_set_event(PD_PORT_TO_TASK_ID(port),
-			PD_EVENT_RX_HARD_RESET, 0);
+			       PD_EVENT_RX_HARD_RESET);
 	}
 	if (status & TCPC_REG_ALERT_TX_COMPLETE) {
 		/* transmit complete */
 		pd_transmit_complete(port, status & TCPC_REG_ALERT_TX_SUCCESS ?
-					   TCPC_TX_COMPLETE_SUCCESS :
-					   TCPC_TX_COMPLETE_FAILED);
+						   TCPC_TX_COMPLETE_SUCCESS :
+						   TCPC_TX_COMPLETE_FAILED);
 	}
 }
diff --git a/driver/tcpm/tcpci.c b/driver/tcpm/tcpci.c
index fd6a5906a5..ffadcab8c0 100644
--- a/driver/tcpm/tcpci.c
+++ b/driver/tcpm/tcpci.c
@@ -1,38 +1,42 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Type-C port manager */
 
-#include "atomic.h"
 #include "anx74xx.h"
+#include "atomic.h"
 #include "compile_time_macros.h"
 #include "console.h"
 #include "ec_commands.h"
+#include "hooks.h"
+#include "i2c.h"
 #include "ps8xxx.h"
 #include "task.h"
-#include "tcpci.h"
-#include "tcpm.h"
+#include "tcpm/tcpci.h"
+#include "tcpm/tcpm.h"
 #include "timer.h"
 #include "usb_charge.h"
 #include "usb_common.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
+#include "usb_pd_flags.h"
 #include "usb_pd_tcpc.h"
+#include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 STATIC_IF(CONFIG_USB_PD_DECODE_SOP)
-	int sop_prime_en[CONFIG_USB_PD_PORT_MAX_COUNT];
+bool sop_prime_en[CONFIG_USB_PD_PORT_MAX_COUNT];
 STATIC_IF(CONFIG_USB_PD_DECODE_SOP)
-	int rx_en[CONFIG_USB_PD_PORT_MAX_COUNT];
+int rx_en[CONFIG_USB_PD_PORT_MAX_COUNT];
 
-#define TCPC_FLAGS_VSAFE0V(_flags) \
+#define TCPC_FLAGS_VSAFE0V(_flags)             \
 	((_flags & TCPC_FLAGS_TCPCI_REV2_0) && \
-		!(_flags & TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V))
+	 !(_flags & TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V))
 
 /****************************************************************************
  * TCPCI DEBUG Helpers
@@ -53,7 +57,7 @@ struct i2c_wrt_op {
 	int mask;
 };
 STATIC_IF(DEBUG_I2C_FAULT_LAST_WRITE_OP)
-	struct i2c_wrt_op last_write_op[CONFIG_USB_PD_PORT_MAX_COUNT];
+struct i2c_wrt_op last_write_op[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 /*
  * AutoDischargeDisconnect has caused a number of issues with the
@@ -86,7 +90,7 @@ struct get_cc_values {
 	int role;
 };
 STATIC_IF(DEBUG_GET_CC)
-	struct get_cc_values last_get_cc[CONFIG_USB_PD_PORT_MAX_COUNT];
+struct get_cc_values last_get_cc[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 /*
  * Seeing RoleCtrl updates can help determine why GetCC is not
@@ -114,6 +118,9 @@ static int tcpc_vbus[CONFIG_USB_PD_PORT_MAX_COUNT];
 /* Cached RP role values */
 static int cached_rp[CONFIG_USB_PD_PORT_MAX_COUNT];
 
+/* Cache our Device Capabilities at init for later reference */
+static int dev_cap_1[CONFIG_USB_PD_PORT_MAX_COUNT];
+
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
 int tcpc_addr_write(int port, int i2c_addr, int reg, int val)
 {
@@ -123,13 +130,12 @@ int tcpc_addr_write(int port, int i2c_addr, int reg, int val)
 
 	if (IS_ENABLED(DEBUG_I2C_FAULT_LAST_WRITE_OP)) {
 		last_write_op[port].addr = i2c_addr;
-		last_write_op[port].reg  = reg;
-		last_write_op[port].val  = val & 0xFF;
+		last_write_op[port].reg = reg;
+		last_write_op[port].val = val & 0xFF;
 		last_write_op[port].mask = 0;
 	}
 
-	rv = i2c_write8(tcpc_config[port].i2c_info.port,
-			i2c_addr, reg, val);
+	rv = i2c_write8(tcpc_config[port].i2c_info.port, i2c_addr, reg, val);
 
 	pd_device_accessed(port);
 	return rv;
@@ -143,13 +149,12 @@ int tcpc_addr_write16(int port, int i2c_addr, int reg, int val)
 
 	if (IS_ENABLED(DEBUG_I2C_FAULT_LAST_WRITE_OP)) {
 		last_write_op[port].addr = i2c_addr;
-		last_write_op[port].reg  = reg;
-		last_write_op[port].val  = val & 0xFFFF;
+		last_write_op[port].reg = reg;
+		last_write_op[port].val = val & 0xFFFF;
 		last_write_op[port].mask = 0;
 	}
 
-	rv = i2c_write16(tcpc_config[port].i2c_info.port,
-			 i2c_addr, reg, val);
+	rv = i2c_write16(tcpc_config[port].i2c_info.port, i2c_addr, reg, val);
 
 	pd_device_accessed(port);
 	return rv;
@@ -161,8 +166,7 @@ int tcpc_addr_read(int port, int i2c_addr, int reg, int *val)
 
 	pd_wait_exit_low_power(port);
 
-	rv = i2c_read8(tcpc_config[port].i2c_info.port,
-		       i2c_addr, reg, val);
+	rv = i2c_read8(tcpc_config[port].i2c_info.port, i2c_addr, reg, val);
 
 	pd_device_accessed(port);
 	return rv;
@@ -170,12 +174,16 @@ int tcpc_addr_read(int port, int i2c_addr, int reg, int *val)
 
 int tcpc_addr_read16(int port, int i2c_addr, int reg, int *val)
 {
-	int rv;
-
 	pd_wait_exit_low_power(port);
 
-	rv = i2c_read16(tcpc_config[port].i2c_info.port,
-			i2c_addr, reg, val);
+	return tcpc_addr_read16_no_lpm_exit(port, i2c_addr, reg, val);
+}
+
+int tcpc_addr_read16_no_lpm_exit(int port, int i2c_addr, int reg, int *val)
+{
+	int rv;
+
+	rv = i2c_read16(tcpc_config[port].i2c_info.port, i2c_addr, reg, val);
 
 	pd_device_accessed(port);
 	return rv;
@@ -188,8 +196,8 @@ int tcpc_read_block(int port, int reg, uint8_t *in, int size)
 	pd_wait_exit_low_power(port);
 
 	rv = i2c_read_block(tcpc_config[port].i2c_info.port,
-			    tcpc_config[port].i2c_info.addr_flags,
-			    reg, in, size);
+			    tcpc_config[port].i2c_info.addr_flags, reg, in,
+			    size);
 
 	pd_device_accessed(port);
 	return rv;
@@ -202,15 +210,15 @@ int tcpc_write_block(int port, int reg, const uint8_t *out, int size)
 	pd_wait_exit_low_power(port);
 
 	rv = i2c_write_block(tcpc_config[port].i2c_info.port,
-			     tcpc_config[port].i2c_info.addr_flags,
-			     reg, out, size);
+			     tcpc_config[port].i2c_info.addr_flags, reg, out,
+			     size);
 
 	pd_device_accessed(port);
 	return rv;
 }
 
-int tcpc_xfer(int port, const uint8_t *out, int out_size,
-			uint8_t *in, int in_size)
+int tcpc_xfer(int port, const uint8_t *out, int out_size, uint8_t *in,
+	      int in_size)
 {
 	int rv;
 	/* Dispatching to tcpc_xfer_unlocked reduces code size growth. */
@@ -221,23 +229,22 @@ int tcpc_xfer(int port, const uint8_t *out, int out_size,
 	return rv;
 }
 
-int tcpc_xfer_unlocked(int port, const uint8_t *out, int out_size,
-			    uint8_t *in, int in_size, int flags)
+int tcpc_xfer_unlocked(int port, const uint8_t *out, int out_size, uint8_t *in,
+		       int in_size, int flags)
 {
 	int rv;
 
 	pd_wait_exit_low_power(port);
 
 	rv = i2c_xfer_unlocked(tcpc_config[port].i2c_info.port,
-			       tcpc_config[port].i2c_info.addr_flags,
-			       out, out_size, in, in_size, flags);
+			       tcpc_config[port].i2c_info.addr_flags, out,
+			       out_size, in, in_size, flags);
 
 	pd_device_accessed(port);
 	return rv;
 }
 
-int tcpc_update8(int port, int reg,
-		 uint8_t mask,
+int tcpc_update8(int port, int reg, uint8_t mask,
 		 enum mask_update_action action)
 {
 	int rv;
@@ -247,20 +254,19 @@ int tcpc_update8(int port, int reg,
 
 	if (IS_ENABLED(DEBUG_I2C_FAULT_LAST_WRITE_OP)) {
 		last_write_op[port].addr = i2c_addr;
-		last_write_op[port].reg  = reg;
-		last_write_op[port].val  = 0;
+		last_write_op[port].reg = reg;
+		last_write_op[port].val = 0;
 		last_write_op[port].mask = (mask & 0xFF) | (action << 16);
 	}
 
-	rv = i2c_update8(tcpc_config[port].i2c_info.port,
-			 i2c_addr, reg, mask, action);
+	rv = i2c_update8(tcpc_config[port].i2c_info.port, i2c_addr, reg, mask,
+			 action);
 
 	pd_device_accessed(port);
 	return rv;
 }
 
-int tcpc_update16(int port, int reg,
-		  uint16_t mask,
+int tcpc_update16(int port, int reg, uint16_t mask,
 		  enum mask_update_action action)
 {
 	int rv;
@@ -270,13 +276,13 @@ int tcpc_update16(int port, int reg,
 
 	if (IS_ENABLED(DEBUG_I2C_FAULT_LAST_WRITE_OP)) {
 		last_write_op[port].addr = i2c_addr;
-		last_write_op[port].reg  = reg;
-		last_write_op[port].val  = 0;
+		last_write_op[port].reg = reg;
+		last_write_op[port].val = 0;
 		last_write_op[port].mask = (mask & 0xFFFF) | (action << 16);
 	}
 
-	rv = i2c_update16(tcpc_config[port].i2c_info.port,
-			  i2c_addr, reg, mask, action);
+	rv = i2c_update16(tcpc_config[port].i2c_info.port, i2c_addr, reg, mask,
+			  action);
 
 	pd_device_accessed(port);
 	return rv;
@@ -310,25 +316,29 @@ static int init_alert_mask(int port)
 	 * Create mask of alert events that will cause the TCPC to
 	 * signal the TCPM via the Alert# gpio line.
 	 */
-	mask = TCPC_REG_ALERT_TX_SUCCESS | TCPC_REG_ALERT_TX_FAILED |
-		TCPC_REG_ALERT_TX_DISCARDED | TCPC_REG_ALERT_RX_STATUS |
-		TCPC_REG_ALERT_RX_HARD_RST | TCPC_REG_ALERT_CC_STATUS
-#ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-		| TCPC_REG_ALERT_POWER_STATUS
-#endif
-		;
+	if (get_usb_pd_vbus_detect() == USB_PD_VBUS_DETECT_TCPC) {
+		mask = TCPC_REG_ALERT_TX_SUCCESS | TCPC_REG_ALERT_TX_FAILED |
+		       TCPC_REG_ALERT_TX_DISCARDED | TCPC_REG_ALERT_RX_STATUS |
+		       TCPC_REG_ALERT_RX_HARD_RST | TCPC_REG_ALERT_CC_STATUS |
+		       TCPC_REG_ALERT_FAULT | TCPC_REG_ALERT_POWER_STATUS;
+	} else {
+		mask = TCPC_REG_ALERT_TX_SUCCESS | TCPC_REG_ALERT_TX_FAILED |
+		       TCPC_REG_ALERT_TX_DISCARDED | TCPC_REG_ALERT_RX_STATUS |
+		       TCPC_REG_ALERT_RX_HARD_RST | TCPC_REG_ALERT_CC_STATUS |
+		       TCPC_REG_ALERT_FAULT;
+	}
 
 	/* TCPCI Rev2 includes SAFE0V alerts */
 	if (TCPC_FLAGS_VSAFE0V(tcpc_config[port].flags))
 		mask |= TCPC_REG_ALERT_EXT_STATUS;
 
-	if (IS_ENABLED(CONFIG_USB_PD_FRS_TCPC))
+	if (tcpm_tcpc_has_frs_control(port))
 		mask |= TCPC_REG_ALERT_ALERT_EXT;
 
 	/* Set the alert mask in TCPC */
 	rv = tcpc_write16(port, TCPC_REG_ALERT_MASK, mask);
 
-	if (IS_ENABLED(CONFIG_USB_PD_FRS_TCPC)) {
+	if (tcpm_tcpc_has_frs_control(port)) {
 		if (rv)
 			return rv;
 
@@ -349,12 +359,12 @@ static int init_power_status_mask(int port)
 	uint8_t mask;
 	int rv;
 
-#ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	mask = TCPC_REG_POWER_STATUS_VBUS_PRES;
-#else
-	mask = 0;
-#endif
-	rv = tcpc_write(port, TCPC_REG_POWER_STATUS_MASK , mask);
+	if (get_usb_pd_vbus_detect() == USB_PD_VBUS_DETECT_TCPC)
+		mask = TCPC_REG_POWER_STATUS_VBUS_PRES;
+	else
+		mask = 0;
+
+	rv = tcpc_write(port, TCPC_REG_POWER_STATUS_MASK, mask);
 
 	return rv;
 }
@@ -380,11 +390,10 @@ int tcpci_tcpm_select_rp_value(int port, int rp)
 void tcpci_tcpc_discharge_vbus(int port, int enable)
 {
 	if (IS_ENABLED(DEBUG_FORCED_DISCHARGE))
-		CPRINTS("C%d: ForceDischarge %sABLED",
-			port, enable ? "EN" : "DIS");
+		CPRINTS("C%d: ForceDischarge %sABLED", port,
+			enable ? "EN" : "DIS");
 
-	tcpc_update8(port,
-		     TCPC_REG_POWER_CTRL,
+	tcpc_update8(port, TCPC_REG_POWER_CTRL,
 		     TCPC_REG_POWER_CTRL_FORCE_DISCHARGE,
 		     (enable) ? MASK_SET : MASK_CLR);
 }
@@ -397,11 +406,10 @@ void tcpci_tcpc_discharge_vbus(int port, int enable)
 void tcpci_tcpc_enable_auto_discharge_disconnect(int port, int enable)
 {
 	if (IS_ENABLED(DEBUG_AUTO_DISCHARGE_DISCONNECT))
-		CPRINTS("C%d: AutoDischargeDisconnect %sABLED",
-			port, enable ? "EN" : "DIS");
+		CPRINTS("C%d: AutoDischargeDisconnect %sABLED", port,
+			enable ? "EN" : "DIS");
 
-	tcpc_update8(port,
-		     TCPC_REG_POWER_CTRL,
+	tcpc_update8(port, TCPC_REG_POWER_CTRL,
 		     TCPC_REG_POWER_CTRL_AUTO_DISCHARGE_DISCONNECT,
 		     (enable) ? MASK_SET : MASK_CLR);
 }
@@ -414,7 +422,7 @@ int tcpci_tcpc_debug_accessory(int port, bool enable)
 }
 
 int tcpci_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2)
+		      enum tcpc_cc_voltage_status *cc2)
 {
 	int role;
 	int status;
@@ -474,13 +482,11 @@ int tcpci_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
 	*cc2 |= cc2_present_rd << 2;
 
 	if (IS_ENABLED(DEBUG_GET_CC) &&
-	    (last_get_cc[port].cc1 != *cc1 ||
-	     last_get_cc[port].cc2 != *cc2 ||
+	    (last_get_cc[port].cc1 != *cc1 || last_get_cc[port].cc2 != *cc2 ||
 	     last_get_cc[port].cc_sts != status ||
 	     last_get_cc[port].role != role)) {
-
-		CPRINTS("C%d: GET_CC cc1=%d cc2=%d cc_sts=0x%X role=0x%X",
-			port, *cc1, *cc2, status, role);
+		CPRINTS("C%d: GET_CC cc1=%d cc2=%d cc_sts=0x%X role=0x%X", port,
+			*cc1, *cc2, status, role);
 
 		last_get_cc[port].cc1 = *cc1;
 		last_get_cc[port].cc2 = *cc2;
@@ -492,9 +498,8 @@ int tcpci_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
 
 int tcpci_tcpm_set_cc(int port, int pull)
 {
-	int role = TCPC_REG_ROLE_CTRL_SET(0,
-					  tcpci_get_cached_rp(port),
-					  pull, pull);
+	int role = TCPC_REG_ROLE_CTRL_SET(
+		TYPEC_NO_DRP, tcpci_get_cached_rp(port), pull, pull);
 
 	if (IS_ENABLED(DEBUG_ROLE_CTRL_UPDATES))
 		CPRINTS("C%d: SET_CC pull=%d role=0x%X", port, pull, role);
@@ -503,13 +508,14 @@ int tcpci_tcpm_set_cc(int port, int pull)
 }
 
 #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-int tcpci_set_role_ctrl(int port, int toggle, int rp, int pull)
+int tcpci_set_role_ctrl(int port, enum tcpc_drp drp, enum tcpc_rp_value rp,
+			enum tcpc_cc_pull pull)
 {
-	int role = TCPC_REG_ROLE_CTRL_SET(toggle, rp, pull, pull);
+	int role = TCPC_REG_ROLE_CTRL_SET(drp, rp, pull, pull);
 
 	if (IS_ENABLED(DEBUG_ROLE_CTRL_UPDATES))
-		CPRINTS("C%d: SET_ROLE_CTRL toggle=%d rp=%d pull=%d role=0x%X",
-			port, toggle, rp, pull, role);
+		CPRINTS("C%d: SET_ROLE_CTRL drp=%d rp=%d pull=%d role=0x%X",
+			port, drp, rp, pull, role);
 
 	return tcpc_write(port, TCPC_REG_ROLE_CTRL, role);
 }
@@ -532,16 +538,16 @@ int tcpci_tcpc_drp_toggle(int port)
 	 *
 	 * Set the Rp Value to be the minimal to save power
 	 */
-	pull = (tcpc_config[port].flags & TCPC_FLAGS_TCPCI_REV2_0)
-			? TYPEC_CC_RP : TYPEC_CC_RD;
+	pull = (tcpc_config[port].flags & TCPC_FLAGS_TCPCI_REV2_0) ?
+		       TYPEC_CC_RP :
+		       TYPEC_CC_RD;
 
-	rv = tcpci_set_role_ctrl(port, 1, TYPEC_RP_USB, pull);
+	rv = tcpci_set_role_ctrl(port, TYPEC_DRP, TYPEC_RP_USB, pull);
 	if (rv)
 		return rv;
 
 	/* Set up to catch LOOK4CONNECTION alerts */
-	rv = tcpc_update8(port,
-			  TCPC_REG_TCPC_CTRL,
+	rv = tcpc_update8(port, TCPC_REG_TCPC_CTRL,
 			  TCPC_REG_TCPC_CTRL_EN_LOOK4CONNECTION_ALERT,
 			  MASK_SET);
 	if (rv)
@@ -560,62 +566,65 @@ int tcpci_enter_low_power_mode(int port)
 {
 	return tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_I2CIDLE);
 }
+
+void tcpci_wake_low_power_mode(int port)
+{
+	/*
+	 * TCPCI 4.8.1 I2C Interface - wake the TCPC with a throw-away command
+	 *
+	 * TODO(b/205140007): Align LPM exit to TCPCI spec for TCPCs which can
+	 * correctly support it
+	 */
+	i2c_write8(tcpc_config[port].i2c_info.port,
+		   tcpc_config[port].i2c_info.addr_flags, TCPC_REG_COMMAND,
+		   TCPC_REG_COMMAND_WAKE_I2C);
+}
 #endif
 
 int tcpci_tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity)
 {
-	return tcpc_update8(port,
-			    TCPC_REG_TCPC_CTRL,
-			    TCPC_REG_TCPC_CTRL_SET(1),
-			    polarity_rm_dts(polarity)
-					? MASK_SET : MASK_CLR);
+	return tcpc_update8(port, TCPC_REG_TCPC_CTRL, TCPC_REG_TCPC_CTRL_SET(1),
+			    polarity_rm_dts(polarity) ? MASK_SET : MASK_CLR);
 }
 
-#ifdef CONFIG_USBC_PPC
-int tcpci_tcpm_get_snk_ctrl(int port, bool *sinking)
+bool tcpci_tcpm_get_snk_ctrl(int port)
 {
 	int rv;
 	int pwr_sts;
 
 	rv = tcpci_tcpm_get_power_status(port, &pwr_sts);
-	*sinking = (rv != EC_SUCCESS)
-			? 0
-			: pwr_sts & TCPC_REG_POWER_STATUS_SINKING_VBUS;
 
-	return rv;
+	return rv == EC_SUCCESS && pwr_sts & TCPC_REG_POWER_STATUS_SINKING_VBUS;
 }
 
 int tcpci_tcpm_set_snk_ctrl(int port, int enable)
 {
 	int cmd = enable ? TCPC_REG_COMMAND_SNK_CTRL_HIGH :
-		TCPC_REG_COMMAND_SNK_CTRL_LOW;
+			   TCPC_REG_COMMAND_SNK_CTRL_LOW;
 
 	return tcpc_write(port, TCPC_REG_COMMAND, cmd);
 }
 
-int tcpci_tcpm_get_src_ctrl(int port, bool *sourcing)
+bool tcpci_tcpm_get_src_ctrl(int port)
 {
 	int rv;
 	int pwr_sts;
 
 	rv = tcpci_tcpm_get_power_status(port, &pwr_sts);
-	*sourcing = (rv != EC_SUCCESS)
-			? 0
-			: pwr_sts & TCPC_REG_POWER_STATUS_SOURCING_VBUS;
 
-	return rv;
+	return rv == EC_SUCCESS &&
+	       pwr_sts & TCPC_REG_POWER_STATUS_SOURCING_VBUS;
 }
 
 int tcpci_tcpm_set_src_ctrl(int port, int enable)
 {
 	int cmd = enable ? TCPC_REG_COMMAND_SRC_CTRL_HIGH :
-		TCPC_REG_COMMAND_SRC_CTRL_LOW;
+			   TCPC_REG_COMMAND_SRC_CTRL_LOW;
 
 	return tcpc_write(port, TCPC_REG_COMMAND, cmd);
 }
-#endif
 
-__maybe_unused static int tpcm_set_sop_prime_enable(int port, int enable)
+__maybe_unused int tcpci_tcpm_sop_prime_enable(int port, bool enable)
 {
 	/* save SOP'/SOP'' enable state */
 	sop_prime_en[port] = enable;
@@ -634,11 +643,6 @@ __maybe_unused static int tpcm_set_sop_prime_enable(int port, int enable)
 	return EC_SUCCESS;
 }
 
-__maybe_unused int tcpci_tcpm_sop_prime_disable(int port)
-{
-	return tpcm_set_sop_prime_enable(port, 0);
-}
-
 int tcpci_tcpm_set_vconn(int port, int enable)
 {
 	int reg, rv;
@@ -647,14 +651,9 @@ int tcpci_tcpm_set_vconn(int port, int enable)
 	if (rv)
 		return rv;
 
-	if (IS_ENABLED(CONFIG_USB_PD_DECODE_SOP)) {
-		rv = tpcm_set_sop_prime_enable(port, enable);
-		if (rv)
-			return rv;
-	}
-
 	reg &= ~TCPC_REG_POWER_CTRL_VCONN(1);
 	reg |= TCPC_REG_POWER_CTRL_VCONN(enable);
+
 	return tcpc_write(port, TCPC_REG_POWER_CTRL, reg);
 }
 
@@ -691,12 +690,11 @@ int tcpci_tcpm_set_rx_enable(int port, int enable)
 		rx_en[port] = enable;
 	}
 
-
 	if (enable) {
 		detect_sop_en = TCPC_REG_RX_DETECT_SOP_HRST_MASK;
 
 		if (IS_ENABLED(CONFIG_USB_PD_DECODE_SOP) &&
-			sop_prime_en[port]) {
+		    sop_prime_en[port]) {
 			/*
 			 * Only the VCONN Source is allowed to communicate
 			 * with the Cable Plugs.
@@ -710,13 +708,12 @@ int tcpci_tcpm_set_rx_enable(int port, int enable)
 	return tcpc_write(port, TCPC_REG_RX_DETECT, detect_sop_en);
 }
 
-#ifdef CONFIG_USB_PD_FRS_TCPC
+#ifdef CONFIG_USB_PD_FRS
 int tcpci_tcpc_fast_role_swap_enable(int port, int enable)
 {
-	return tcpc_update8(port,
-		     TCPC_REG_POWER_CTRL,
-		     TCPC_REG_POWER_CTRL_FRS_ENABLE,
-		     (enable) ? MASK_SET : MASK_CLR);
+	return tcpc_update8(port, TCPC_REG_POWER_CTRL,
+			    TCPC_REG_POWER_CTRL_FRS_ENABLE,
+			    (enable) ? MASK_SET : MASK_CLR);
 }
 #endif
 
@@ -771,7 +768,7 @@ static int tcpci_rev2_0_tcpm_get_message_raw(int port, uint32_t *payload,
 
 	/* The next two bytes are the header */
 	rv |= tcpc_xfer_unlocked(port, NULL, 0, (uint8_t *)head, 2,
-				cnt ? 0 : I2C_XFER_STOP);
+				 cnt ? 0 : I2C_XFER_STOP);
 
 	/* Encode message address in bits 31 to 28 */
 	*head &= 0x0000ffff;
@@ -858,12 +855,12 @@ struct queue {
 	 * Head points to the index of the first empty slot to put a new RX
 	 * message. Must be masked before used in lookup.
 	 */
-	uint32_t head;
+	atomic_t head;
 	/*
 	 * Tail points to the index of the first message for the PD task to
 	 * consume. Must be masked before used in lookup.
 	 */
-	uint32_t tail;
+	atomic_t tail;
 	struct cached_tcpm_message buffer[CACHE_DEPTH];
 };
 static struct queue cached_messages[CONFIG_USB_PD_PORT_MAX_COUNT];
@@ -892,10 +889,10 @@ int tcpm_enqueue_message(const int port)
 	}
 
 	/* Increment atomically to ensure get_message_raw happens-before */
-	deprecated_atomic_add(&q->head, 1);
+	atomic_add(&q->head, 1);
 
 	/* Wake PD task up so it can process incoming RX messages */
-	task_set_event(PD_PORT_TO_TASK_ID(port), TASK_EVENT_WAKE, 0);
+	task_set_event(PD_PORT_TO_TASK_ID(port), TASK_EVENT_WAKE);
 
 	return EC_SUCCESS;
 }
@@ -924,7 +921,7 @@ int tcpm_dequeue_message(const int port, uint32_t *const payload,
 	memcpy(payload, tail->payload, sizeof(tail->payload));
 
 	/* Increment atomically to ensure memcpy happens-before */
-	deprecated_atomic_add(&q->tail, 1);
+	atomic_add(&q->tail, 1);
 
 	return EC_SUCCESS;
 }
@@ -936,11 +933,11 @@ void tcpm_clear_pending_messages(int port)
 	q->tail = q->head;
 }
 
-int tcpci_tcpm_transmit(int port, enum tcpm_transmit_type type,
-			uint16_t header, const uint32_t *data)
+int tcpci_tcpm_transmit(int port, enum tcpci_msg_type type, uint16_t header,
+			const uint32_t *data)
 {
 	int reg = TCPC_REG_TX_DATA;
-	int rv, cnt = 4*PD_HEADER_CNT(header);
+	int rv, cnt = 4 * PD_HEADER_CNT(header);
 
 	/* If not SOP* transmission, just write to the transmit register */
 	if (type >= NUM_SOP_STAR_TYPES) {
@@ -949,7 +946,7 @@ int tcpci_tcpm_transmit(int port, enum tcpm_transmit_type type,
 		 * should ignore retry field for these 3 types).
 		 */
 		return tcpc_write(port, TCPC_REG_TRANSMIT,
-			TCPC_REG_TRANSMIT_SET_WITHOUT_RETRY(type));
+				  TCPC_REG_TRANSMIT_SET_WITHOUT_RETRY(type));
 	}
 
 	if (tcpc_config[port].flags & TCPC_FLAGS_TCPCI_REV2_0) {
@@ -966,13 +963,14 @@ int tcpci_tcpm_transmit(int port, enum tcpm_transmit_type type,
 		rv |= tcpc_xfer_unlocked(port, (uint8_t *)&cnt, 1, NULL, 0, 0);
 		if (cnt > sizeof(header)) {
 			rv |= tcpc_xfer_unlocked(port, (uint8_t *)&header,
-					 sizeof(header), NULL, 0, 0);
+						 sizeof(header), NULL, 0, 0);
 			rv |= tcpc_xfer_unlocked(port, (uint8_t *)data,
-					 cnt-sizeof(header), NULL, 0,
-					 I2C_XFER_STOP);
+						 cnt - sizeof(header), NULL, 0,
+						 I2C_XFER_STOP);
 		} else {
 			rv |= tcpc_xfer_unlocked(port, (uint8_t *)&header,
-					sizeof(header), NULL, 0, I2C_XFER_STOP);
+						 sizeof(header), NULL, 0,
+						 I2C_XFER_STOP);
 		}
 		tcpc_lock(port, 0);
 
@@ -1000,6 +998,18 @@ int tcpci_tcpm_transmit(int port, enum tcpm_transmit_type type,
 		}
 	}
 
+	/*
+	 * The PRL_RX state machine should force a discard of PRL_TX any time a
+	 * new message comes in.  However, since most of the PRL_RX runs on
+	 * the TCPC, we may receive a RX interrupt between the EC PRL_RX and
+	 * PRL_TX state machines running.  In this case, mark the message
+	 * discarded and don't tell the TCPC to transmit.
+	 */
+	if (tcpm_has_pending_message(port)) {
+		pd_transmit_complete(port, TCPC_TX_COMPLETE_DISCARDED);
+		return EC_ERROR_BUSY;
+	}
+
 	/*
 	 * We always retry in TCPC hardware since the TCPM is too slow to
 	 * respond within tRetry (~195 usec).
@@ -1008,7 +1018,8 @@ int tcpci_tcpm_transmit(int port, enum tcpm_transmit_type type,
 	 * supported at build time.
 	 */
 	return tcpc_write(port, TCPC_REG_TRANSMIT,
-			  TCPC_REG_TRANSMIT_SET_WITH_RETRY(type));
+			  TCPC_REG_TRANSMIT_SET_WITH_RETRY(
+				  pd_get_retry_count(port, type), type));
 }
 
 /*
@@ -1045,26 +1056,68 @@ static int tcpci_handle_fault(int port, int fault)
 	if (IS_ENABLED(DEBUG_I2C_FAULT_LAST_WRITE_OP) &&
 	    fault & TCPC_REG_FAULT_STATUS_I2C_INTERFACE_ERR) {
 		if (last_write_op[port].mask == 0)
-			CPRINTS("C%d I2C WR 0x%02X 0x%02X value=0x%X",
-				port,
+			CPRINTS("C%d I2C WR 0x%02X 0x%02X value=0x%X", port,
 				last_write_op[port].addr,
 				last_write_op[port].reg,
 				last_write_op[port].val);
 		else
 			CPRINTS("C%d I2C UP 0x%02X 0x%02X op=%d mask=0x%X",
-				port,
-				last_write_op[port].addr,
+				port, last_write_op[port].addr,
 				last_write_op[port].reg,
 				last_write_op[port].mask >> 16,
 				last_write_op[port].mask & 0xFFFF);
 	}
 
+	/* Report overcurrent to the OCP module if enabled */
+	if ((dev_cap_1[port] & TCPC_REG_DEV_CAP_1_VBUS_OCP_REPORTING) &&
+	    IS_ENABLED(CONFIG_USBC_OCP) &&
+	    (fault & TCPC_REG_FAULT_STATUS_VBUS_OVER_CURRENT))
+		pd_handle_overcurrent(port);
+
 	if (tcpc_config[port].drv->handle_fault)
 		rv = tcpc_config[port].drv->handle_fault(port, fault);
 
 	return rv;
 }
 
+int tcpci_hard_reset_reinit(int port)
+{
+	int rv;
+
+	/* Initialize power_status_mask */
+	rv = init_power_status_mask(port);
+	/* Initialize alert_mask */
+	rv |= init_alert_mask(port);
+
+	CPRINTS("C%d: Hard Reset re-initialize %s", port,
+		rv ? "failed" : "success");
+
+	return rv;
+}
+
+enum ec_error_list tcpci_set_bist_test_mode(const int port, const bool enable)
+{
+	int rv;
+
+	rv = tcpc_update8(port, TCPC_REG_TCPC_CTRL,
+			  TCPC_REG_TCPC_CTRL_BIST_TEST_MODE,
+			  enable ? MASK_SET : MASK_CLR);
+	rv |= tcpc_update16(port, TCPC_REG_ALERT_MASK, TCPC_REG_ALERT_RX_STATUS,
+			    enable ? MASK_CLR : MASK_SET);
+	return rv;
+}
+
+enum ec_error_list tcpci_get_bist_test_mode(const int port, bool *enable)
+{
+	int rv;
+	int val;
+
+	rv = tcpc_read(port, TCPC_REG_TCPC_CTRL, &val);
+	*enable = !!(val & TCPC_REG_TCPC_CTRL_BIST_TEST_MODE);
+
+	return rv;
+}
+
 static int tcpci_clear_fault(int port, int fault)
 {
 	int rv;
@@ -1114,18 +1167,17 @@ static void tcpci_check_vbus_changed(int port, int alert, uint32_t *pd_event)
 			tcpc_vbus[port] = BIT(VBUS_SAFE0V);
 		}
 
-		if (IS_ENABLED(CONFIG_USB_PD_VBUS_DETECT_TCPC) &&
-		    IS_ENABLED(CONFIG_USB_CHARGER)) {
+		if (get_usb_pd_vbus_detect() == USB_PD_VBUS_DETECT_TCPC) {
 			/* Update charge manager with new VBUS state */
-			usb_charger_vbus_change(port,
-				!!(tcpc_vbus[port] & BIT(VBUS_PRESENT)));
+			if (IS_ENABLED(CONFIG_USB_CHARGER))
+				usb_charger_vbus_change(port,
+							!!(tcpc_vbus[port] &
+							   BIT(VBUS_PRESENT)));
 
-			if (pd_event)
+			if (pd_event) {
 				*pd_event |= TASK_EVENT_WAKE;
+			}
 		}
-
-		if (pwr_status & TCPC_REG_POWER_STATUS_VBUS_DET)
-			board_vbus_present_change();
 	}
 }
 
@@ -1141,6 +1193,8 @@ void tcpci_tcpc_alert(int port)
 	int alert_ext = 0;
 	int failed_attempts;
 	uint32_t pd_event = 0;
+	int retval = 0;
+	bool bist_mode;
 
 	/* Read the Alert register from the TCPC */
 	if (tcpm_alert_status(port, &alert)) {
@@ -1156,8 +1210,7 @@ void tcpci_tcpc_alert(int port)
 	if (alert & TCPC_REG_ALERT_FAULT) {
 		int fault;
 
-		if (tcpci_get_fault(port, &fault) == EC_SUCCESS &&
-		    fault != 0 &&
+		if (tcpci_get_fault(port, &fault) == EC_SUCCESS && fault != 0 &&
 		    tcpci_handle_fault(port, fault) == EC_SUCCESS &&
 		    tcpci_clear_fault(port, fault) == EC_SUCCESS)
 			CPRINTS("C%d FAULT 0x%02X handled", port, fault);
@@ -1168,19 +1221,50 @@ void tcpci_tcpc_alert(int port)
 	 * completion events. This will send an event to the PD tasks
 	 * immediately
 	 */
-	if (alert & TCPC_REG_ALERT_TX_COMPLETE)
-		pd_transmit_complete(port, alert & TCPC_REG_ALERT_TX_SUCCESS ?
-					   TCPC_TX_COMPLETE_SUCCESS :
-					   TCPC_TX_COMPLETE_FAILED);
+	if (alert & TCPC_REG_ALERT_TX_COMPLETE) {
+		int tx_status;
+
+		if (alert & TCPC_REG_ALERT_TX_SUCCESS)
+			tx_status = TCPC_TX_COMPLETE_SUCCESS;
+		else if (alert & TCPC_REG_ALERT_TX_DISCARDED)
+			tx_status = TCPC_TX_COMPLETE_DISCARDED;
+		else
+			tx_status = TCPC_TX_COMPLETE_FAILED;
+
+		pd_transmit_complete(port, tx_status);
+	}
+
+	tcpc_get_bist_test_mode(port, &bist_mode);
 
 	/* Pull all RX messages from TCPC into EC memory */
 	failed_attempts = 0;
 	while (alert & TCPC_REG_ALERT_RX_STATUS) {
-		if (tcpm_enqueue_message(port))
+		/*
+		 * Some TCPCs do not properly disable interrupts during BIST
+		 * test mode. For reducing I2C access time,
+		 * there is no need to read out BIST data, just break.
+		 * (see b/229812911).
+		 */
+		if (bist_mode)
+			break;
+
+		retval = tcpm_enqueue_message(port);
+		if (retval)
 			++failed_attempts;
 		if (tcpm_alert_status(port, &alert))
 			++failed_attempts;
 
+		/*
+		 * EC RX FIFO is full. Deassert ALERT# line to exit interrupt
+		 * handler by discarding pending message from TCPC RX FIFO.
+		 */
+		if (retval == EC_ERROR_OVERFLOW) {
+			CPRINTS("C%d: PD RX OVF!", port);
+			tcpc_write16(port, TCPC_REG_ALERT,
+				     TCPC_REG_ALERT_RX_STATUS |
+					     TCPC_REG_ALERT_RX_BUF_OVF);
+		}
+
 		/* Ensure we don't loop endlessly */
 		if (failed_attempts >= MAX_ALLOW_FAILED_RX_READS) {
 			CPRINTS("C%d Cannot consume RX buffer after %d failed attempts!",
@@ -1234,6 +1318,9 @@ void tcpci_tcpc_alert(int port)
 	if (alert & TCPC_REG_ALERT_RX_HARD_RST) {
 		/* hard reset received */
 		CPRINTS("C%d Hard Reset received", port);
+
+		tcpm_hard_reset_reinit(port);
+
 		pd_event |= PD_EVENT_RX_HARD_RESET;
 	}
 
@@ -1247,15 +1334,19 @@ void tcpci_tcpc_alert(int port)
 	    alert & TCPC_REG_ALERT_TX_FAILED)
 		CPRINTS("C%d Hard Reset sent", port);
 
-	if (IS_ENABLED(CONFIG_USB_PD_FRS_TCPC)
-	    && (alert_ext & TCPC_REG_ALERT_EXT_SNK_FRS))
+	if (tcpm_tcpc_has_frs_control(port) &&
+	    (alert_ext & TCPC_REG_ALERT_EXT_SNK_FRS))
 		pd_got_frs_signal(port);
 
 	/*
 	 * Check registers to see if we can tell that the TCPC has reset. If
 	 * so, perform a tcpc_init.
+	 *
+	 * Some TCPCs do not properly disable interrupts during BIST test mode.
+	 * As TCPC not reset at this moment, no need to check pd reset status to
+	 * reduce I2C access time.(see b/229812911)
 	 */
-	if (register_mask_reset(port))
+	if (!bist_mode && register_mask_reset(port))
 		pd_event |= PD_EVENT_TCPC_RESET;
 
 	/*
@@ -1266,71 +1357,105 @@ void tcpci_tcpc_alert(int port)
 	 * the next I2C transaction to the TCPC will cause it to wake again.
 	 */
 	if (pd_event)
-		task_set_event(PD_PORT_TO_TASK_ID(port), pd_event, 0);
+		task_set_event(PD_PORT_TO_TASK_ID(port), pd_event);
 }
 
-/*
- * This call will wake up the TCPC if it is in low power mode upon accessing the
- * i2c bus (but the pd state machine should put it back into low power mode).
- *
- * Once it's called, the chip info will be stored in cache, which can be
- * accessed by tcpm_get_chip_info without worrying about chip states.
- */
-int tcpci_get_chip_info(int port, int live,
-			struct ec_response_pd_chip_info_v1 *chip_info)
+int tcpci_get_vbus_voltage_no_check(int port, int *vbus)
+{
+	int error, val;
+
+	error = tcpc_read16(port, TCPC_REG_VBUS_VOLTAGE, &val);
+	if (error)
+		return error;
+
+	*vbus = TCPC_REG_VBUS_VOLTAGE_VBUS(val);
+	return EC_SUCCESS;
+}
+
+int tcpci_get_vbus_voltage(int port, int *vbus)
+{
+	if (!(dev_cap_1[port] & TCPC_REG_DEV_CAP_1_VBUS_MEASURE_ALARM_CAPABLE))
+		return EC_ERROR_UNIMPLEMENTED;
+
+	return tcpci_get_vbus_voltage_no_check(port, vbus);
+}
+
+int tcpci_get_chip_info_mutable(
+	int port, int live, struct ec_response_pd_chip_info_v1 *const chip_info,
+	int (*const mutator)(int port, bool live,
+			     struct ec_response_pd_chip_info_v1 *cached))
 {
 	static struct ec_response_pd_chip_info_v1
 		cached_info[CONFIG_USB_PD_PORT_MAX_COUNT];
-	struct ec_response_pd_chip_info_v1 *i;
+	struct ec_response_pd_chip_info_v1 *info;
 	int error;
-	int val;
 
 	if (port >= board_get_usb_pd_port_count())
 		return EC_ERROR_INVAL;
 
-	i = &cached_info[port];
+	info = &cached_info[port];
 
+	/* Fetch live data if nothing is cached or live data was requested */
+	if (!info->vendor_id || live) {
+		int vendor_id, product_id, device_id;
 
-	/* If already cached && live data is not asked, return cached value */
-	if (i->vendor_id && !live) {
 		/*
-		 * If chip_info is NULL, chip info will be stored in cache and
-		 * can be read later by another call.
+		 * The cache is no longer valid because we're fetching. Avoid
+		 * storing the new vendor ID until we've actually succeeded so
+		 * future invocations won't see partial data and assume it's a
+		 * valid cache.
 		 */
-		if (chip_info)
-			memcpy(chip_info, i, sizeof(*i));
+		info->vendor_id = 0;
+		error = tcpc_read16(port, TCPC_REG_VENDOR_ID, &vendor_id);
+		if (error)
+			return error;
 
-		return EC_SUCCESS;
-	}
+		error = tcpc_read16(port, TCPC_REG_PRODUCT_ID, &product_id);
+		if (error)
+			return error;
+		info->product_id = product_id;
 
-	error = tcpc_read16(port, TCPC_REG_VENDOR_ID, &val);
-	if (error)
-		return error;
-	i->vendor_id = val;
-
-	error = tcpc_read16(port, TCPC_REG_PRODUCT_ID, &val);
-	if (error)
-		return error;
-	i->product_id = val;
-
-	error = tcpc_read16(port, TCPC_REG_BCD_DEV, &val);
-	if (error)
-		return error;
-	i->device_id = val;
+		error = tcpc_read16(port, TCPC_REG_BCD_DEV, &device_id);
+		if (error)
+			return error;
+		info->device_id = device_id;
 
+		/*
+		 * This varies chip to chip; more specific driver code is
+		 * expected to override this value if it can by providing a
+		 * mutator.
+		 */
+		info->fw_version_number = -1;
+
+		info->vendor_id = vendor_id;
+		if (mutator != NULL) {
+			error = mutator(port, live, info);
+			if (error) {
+				/*
+				 * Mutator needs to have a complete view, but if
+				 * it fails the cache is invalidated.
+				 */
+				info->vendor_id = 0;
+				return error;
+			}
+		}
+	}
 	/*
-	 * This varies chip to chip; more specific driver code is expected to
-	 * override this value if it can.
+	 * If chip_info is NULL, this invocation will ensure the cache is fresh
+	 * but return nothing.
 	 */
-	i->fw_version_number = -1;
-
-	/* Copy the cached value to return if chip_info is not NULL */
 	if (chip_info)
-		memcpy(chip_info, i, sizeof(*i));
+		memcpy(chip_info, info, sizeof(*info));
 
 	return EC_SUCCESS;
 }
 
+int tcpci_get_chip_info(int port, int live,
+			struct ec_response_pd_chip_info_v1 *chip_info)
+{
+	return tcpci_get_chip_info_mutable(port, live, chip_info, NULL);
+}
+
 /*
  * Dissociate from the TCPC.
  */
@@ -1364,7 +1489,6 @@ int tcpci_tcpm_init(int port)
 	int error;
 	int power_status;
 	int tries = TCPM_INIT_TRIES;
-	int tcpc_ctrl;
 
 	if (port >= board_get_usb_pd_port_count())
 		return EC_ERROR_INVAL;
@@ -1383,25 +1507,19 @@ int tcpci_tcpm_init(int port)
 		msleep(10);
 	}
 
-	/*
-	 * Set TCPC_CONTROL.DebugAccessoryControl = 1 to control by TCPM,
-	 * not TCPC.
-	 */
-	tcpc_ctrl = TCPC_REG_TCPC_CTRL_DEBUG_ACC_CONTROL;
-
 	/*
 	 * For TCPCI Rev 2.0, unless the TCPM sets
 	 * TCPC_CONTROL.EnableLooking4ConnectionAlert bit, TCPC by default masks
 	 * Alert assertion when CC_STATUS.Looking4Connection changes state.
 	 */
 	if (tcpc_config[port].flags & TCPC_FLAGS_TCPCI_REV2_0) {
-		tcpc_ctrl |= TCPC_REG_TCPC_CTRL_EN_LOOK4CONNECTION_ALERT;
+		error = tcpc_update8(
+			port, TCPC_REG_TCPC_CTRL,
+			TCPC_REG_TCPC_CTRL_EN_LOOK4CONNECTION_ALERT, MASK_SET);
+		if (error)
+			CPRINTS("C%d: Failed to init TCPC_CTRL!", port);
 	}
 
-	error = tcpc_update8(port, TCPC_REG_TCPC_CTRL, tcpc_ctrl, MASK_SET);
-	if (error)
-		CPRINTS("C%d: Failed to init TCPC_CTRL!", port);
-
 	/*
 	 * Handle and clear any alerts, since we might be coming out of low
 	 * power mode in response to an alert interrupt from the TCPC.
@@ -1424,18 +1542,27 @@ int tcpci_tcpm_init(int port)
 			tcpc_vbus[port] = 0;
 	} else {
 		/* Initial level, set appropriately */
-		tcpc_vbus[port] = (power_status &
-				   TCPC_REG_POWER_STATUS_VBUS_PRES)
-					? BIT(VBUS_PRESENT)
-					: BIT(VBUS_SAFE0V);
+		tcpc_vbus[port] =
+			(power_status & TCPC_REG_POWER_STATUS_VBUS_PRES) ?
+				BIT(VBUS_PRESENT) :
+				BIT(VBUS_SAFE0V);
 	}
 
+	/* Enable/disable VBUS monitor by the flag */
+	error = tcpc_update8(port, TCPC_REG_POWER_CTRL,
+			     TCPC_REG_POWER_CTRL_VBUS_VOL_MONITOR_DIS,
+			     tcpc_config[port].flags & TCPC_FLAGS_VBUS_MONITOR ?
+				     MASK_CLR :
+				     MASK_SET);
+	if (error)
+		return error;
+
 	/*
 	 * Force an update to the VBUS status in case the TCPC doesn't send a
 	 * power status changed interrupt later.
 	 */
-	tcpci_check_vbus_changed(port,
-		TCPC_REG_ALERT_POWER_STATUS | TCPC_REG_ALERT_EXT_STATUS,
+	tcpci_check_vbus_changed(
+		port, TCPC_REG_ALERT_POWER_STATUS | TCPC_REG_ALERT_EXT_STATUS,
 		NULL);
 
 	error = init_alert_mask(port);
@@ -1445,6 +1572,9 @@ int tcpci_tcpm_init(int port)
 	/* Read chip info here when we know the chip is awake. */
 	tcpm_get_chip_info(port, 1, NULL);
 
+	/* Cache our device capabilities for future reference */
+	tcpc_read16(port, TCPC_REG_DEV_CAP_1, &dev_cap_1[port]);
+
 	return EC_SUCCESS;
 }
 
@@ -1486,7 +1616,7 @@ int tcpci_tcpm_mux_init(const struct usb_mux *me)
 	return error ? EC_ERROR_UNKNOWN : EC_SUCCESS;
 }
 
-static int tcpci_tcpm_mux_enter_low_power(const struct usb_mux *me)
+int tcpci_tcpm_mux_enter_low_power(const struct usb_mux *me)
 {
 	/* If this MUX is also the TCPC, then skip low power */
 	if (!(me->flags & USB_MUX_FLAG_NOT_TCPC))
@@ -1495,11 +1625,19 @@ static int tcpci_tcpm_mux_enter_low_power(const struct usb_mux *me)
 	return mux_write(me, TCPC_REG_COMMAND, TCPC_REG_COMMAND_I2CIDLE);
 }
 
-int tcpci_tcpm_mux_set(const struct usb_mux *me, mux_state_t mux_state)
+int tcpci_tcpm_mux_set(const struct usb_mux *me, mux_state_t mux_state,
+		       bool *ack_required)
 {
 	int rv;
 	int reg = 0;
 
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
+	/* This driver treats safe mode as none */
+	if (mux_state & USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
+
 	/* Parameter is port only */
 	rv = mux_read(me, TCPC_REG_CONFIG_STD_OUTPUT, &reg);
 	if (rv != EC_SUCCESS)
@@ -1602,11 +1740,9 @@ static const struct tcpc_reg_dump_map tcpc_regs[] = {
 		.name = "FAULT_STATUS_MASK",
 		.size = 1,
 	},
-	{
-		.addr = TCPC_REG_EXT_STATUS_MASK,
-		.name = "EXT_STATUS_MASK",
-		.size = 1
-	},
+	{ .addr = TCPC_REG_EXT_STATUS_MASK,
+	  .name = "EXT_STATUS_MASK",
+	  .size = 1 },
 	{
 		.addr = TCPC_REG_ALERT_EXTENDED_MASK,
 		.name = "ALERT_EXTENDED_MASK",
@@ -1742,46 +1878,54 @@ static const struct tcpc_reg_dump_map tcpc_regs[] = {
 /*
  * Dump standard TCPC registers.
  */
-void tcpc_dump_std_registers(int port)
+test_mockable void tcpc_dump_std_registers(int port)
 {
 	tcpc_dump_registers(port, tcpc_regs, ARRAY_SIZE(tcpc_regs));
 }
 #endif
 
 const struct tcpm_drv tcpci_tcpm_drv = {
-	.init			= &tcpci_tcpm_init,
-	.release		= &tcpci_tcpm_release,
-	.get_cc			= &tcpci_tcpm_get_cc,
+	.init = &tcpci_tcpm_init,
+	.release = &tcpci_tcpm_release,
+	.get_cc = &tcpci_tcpm_get_cc,
 #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	.check_vbus_level	= &tcpci_tcpm_check_vbus_level,
+	.check_vbus_level = &tcpci_tcpm_check_vbus_level,
 #endif
-	.select_rp_value	= &tcpci_tcpm_select_rp_value,
-	.set_cc			= &tcpci_tcpm_set_cc,
-	.set_polarity		= &tcpci_tcpm_set_polarity,
+	.get_vbus_voltage = &tcpci_get_vbus_voltage,
+	.select_rp_value = &tcpci_tcpm_select_rp_value,
+	.set_cc = &tcpci_tcpm_set_cc,
+	.set_polarity = &tcpci_tcpm_set_polarity,
 #ifdef CONFIG_USB_PD_DECODE_SOP
-	.sop_prime_disable	= &tcpci_tcpm_sop_prime_disable,
+	.sop_prime_enable = &tcpci_tcpm_sop_prime_enable,
 #endif
-	.set_vconn		= &tcpci_tcpm_set_vconn,
-	.set_msg_header		= &tcpci_tcpm_set_msg_header,
-	.set_rx_enable		= &tcpci_tcpm_set_rx_enable,
-	.get_message_raw	= &tcpci_tcpm_get_message_raw,
-	.transmit		= &tcpci_tcpm_transmit,
-	.tcpc_alert		= &tcpci_tcpc_alert,
+	.set_vconn = &tcpci_tcpm_set_vconn,
+	.set_msg_header = &tcpci_tcpm_set_msg_header,
+	.set_rx_enable = &tcpci_tcpm_set_rx_enable,
+	.get_message_raw = &tcpci_tcpm_get_message_raw,
+	.transmit = &tcpci_tcpm_transmit,
+	.tcpc_alert = &tcpci_tcpc_alert,
 #ifdef CONFIG_USB_PD_DISCHARGE_TCPC
-	.tcpc_discharge_vbus	= &tcpci_tcpc_discharge_vbus,
+	.tcpc_discharge_vbus = &tcpci_tcpc_discharge_vbus,
 #endif
+	.tcpc_enable_auto_discharge_disconnect =
+		&tcpci_tcpc_enable_auto_discharge_disconnect,
 #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-	.drp_toggle		= &tcpci_tcpc_drp_toggle,
-#endif
-	.get_chip_info		= &tcpci_get_chip_info,
-#ifdef CONFIG_USBC_PPC
-	.set_snk_ctrl		= &tcpci_tcpm_set_snk_ctrl,
-	.set_src_ctrl		= &tcpci_tcpm_set_src_ctrl,
+	.drp_toggle = &tcpci_tcpc_drp_toggle,
 #endif
+	.get_chip_info = &tcpci_get_chip_info,
+	.get_snk_ctrl = &tcpci_tcpm_get_snk_ctrl,
+	.set_snk_ctrl = &tcpci_tcpm_set_snk_ctrl,
+	.get_src_ctrl = &tcpci_tcpm_get_src_ctrl,
+	.set_src_ctrl = &tcpci_tcpm_set_src_ctrl,
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	.enter_low_power_mode	= &tcpci_enter_low_power_mode,
+	.enter_low_power_mode = &tcpci_enter_low_power_mode,
+#endif
+#ifdef CONFIG_USB_PD_FRS_TCPC
+	.set_frs_enable = &tcpci_tcpc_fast_role_swap_enable,
 #endif
+	.set_bist_test_mode = &tcpci_set_bist_test_mode,
+	.get_bist_test_mode = &tcpci_get_bist_test_mode,
 #ifdef CONFIG_CMD_TCPC_DUMP
-	.dump_registers		= &tcpc_dump_std_registers,
+	.dump_registers = &tcpc_dump_std_registers,
 #endif
 };
diff --git a/driver/tcpm/tcpci.h b/driver/tcpm/tcpci.h
deleted file mode 100644
index db05c978e8..0000000000
--- a/driver/tcpm/tcpci.h
+++ /dev/null
@@ -1,259 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USB Power delivery port management */
-
-#ifndef __CROS_EC_USB_PD_TCPM_TCPCI_H
-#define __CROS_EC_USB_PD_TCPM_TCPCI_H
-
-#include "config.h"
-#include "tcpm.h"
-#include "usb_mux.h"
-#include "usb_pd_tcpm.h"
-
-#define TCPC_REG_VENDOR_ID         0x0
-#define TCPC_REG_PRODUCT_ID        0x2
-#define TCPC_REG_BCD_DEV           0x4
-#define TCPC_REG_TC_REV            0x6
-#define TCPC_REG_PD_REV            0x8
-#define TCPC_REG_PD_INT_REV        0xa
-
-#define TCPC_REG_ALERT             0x10
-#define TCPC_REG_ALERT_MASK_ALL     0xffff
-#define TCPC_REG_ALERT_VENDOR_DEF   BIT(15)
-#define TCPC_REG_ALERT_ALERT_EXT    BIT(14)
-#define TCPC_REG_ALERT_EXT_STATUS   BIT(13)
-#define TCPC_REG_ALERT_VBUS_DISCNCT BIT(11)
-#define TCPC_REG_ALERT_RX_BUF_OVF   BIT(10)
-#define TCPC_REG_ALERT_FAULT        BIT(9)
-#define TCPC_REG_ALERT_V_ALARM_LO   BIT(8)
-#define TCPC_REG_ALERT_V_ALARM_HI   BIT(7)
-#define TCPC_REG_ALERT_TX_SUCCESS   BIT(6)
-#define TCPC_REG_ALERT_TX_DISCARDED BIT(5)
-#define TCPC_REG_ALERT_TX_FAILED    BIT(4)
-#define TCPC_REG_ALERT_RX_HARD_RST  BIT(3)
-#define TCPC_REG_ALERT_RX_STATUS    BIT(2)
-#define TCPC_REG_ALERT_POWER_STATUS BIT(1)
-#define TCPC_REG_ALERT_CC_STATUS    BIT(0)
-#define TCPC_REG_ALERT_TX_COMPLETE  (TCPC_REG_ALERT_TX_SUCCESS | \
-				      TCPC_REG_ALERT_TX_DISCARDED | \
-				      TCPC_REG_ALERT_TX_FAILED)
-
-#define TCPC_REG_ALERT_MASK        0x12
-#define TCPC_REG_ALERT_MASK_VENDOR_DEF   BIT(15)
-
-#define TCPC_REG_POWER_STATUS_MASK 0x14
-#define TCPC_REG_FAULT_STATUS_MASK 0x15
-#define TCPC_REG_EXT_STATUS_MASK   0x16
-#define TCPC_REG_ALERT_EXTENDED_MASK 0x17
-
-#define TCPC_REG_CONFIG_STD_OUTPUT 0x18
-#define TCPC_REG_CONFIG_STD_OUTPUT_DBG_ACC_CONN_N    BIT(6)
-#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_MASK          (3 << 2)
-#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_NONE          (0 << 2)
-#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_USB           BIT(2)
-#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_DP            (2 << 2)
-#define TCPC_REG_CONFIG_STD_OUTPUT_CONNECTOR_FLIPPED BIT(0)
-
-#define TCPC_REG_TCPC_CTRL         0x19
-#define TCPC_REG_TCPC_CTRL_SET(polarity) (polarity)
-#define TCPC_REG_TCPC_CTRL_POLARITY(reg) ((reg) & 0x1)
-/*
- * In TCPCI Rev 2.0, this bit must be set this to generate CC status alerts when
- * a connection is found.
- */
-#define TCPC_REG_TCPC_CTRL_EN_LOOK4CONNECTION_ALERT  BIT(6)
-#define TCPC_REG_TCPC_CTRL_DEBUG_ACC_CONTROL         BIT(4)
-
-#define TCPC_REG_ROLE_CTRL         0x1a
-#define TCPC_REG_ROLE_CTRL_DRP_MASK                    BIT(6)
-#define TCPC_REG_ROLE_CTRL_RP_MASK                     (BIT(5)|BIT(4))
-#define TCPC_REG_ROLE_CTRL_CC2_MASK                    (BIT(3)|BIT(2))
-#define TCPC_REG_ROLE_CTRL_CC1_MASK                    (BIT(1)|BIT(0))
-#define TCPC_REG_ROLE_CTRL_SET(drp, rp, cc1, cc2) \
-		((drp) << 6 | (rp) << 4 | (cc2) << 2 | (cc1))
-#define TCPC_REG_ROLE_CTRL_DRP(reg) \
-		(((reg) & TCPC_REG_ROLE_CTRL_DRP_MASK) >> 6)
-#define TCPC_REG_ROLE_CTRL_RP(reg) \
-		(((reg) & TCPC_REG_ROLE_CTRL_RP_MASK) >> 4)
-#define TCPC_REG_ROLE_CTRL_CC2(reg) \
-		(((reg) & TCPC_REG_ROLE_CTRL_CC2_MASK) >> 2)
-#define TCPC_REG_ROLE_CTRL_CC1(reg) \
-		((reg) & TCPC_REG_ROLE_CTRL_CC1_MASK)
-
-#define TCPC_REG_FAULT_CTRL        0x1b
-#define TCPC_REG_FAULT_CTRL_VBUS_OVP_FAULT_DIS         BIT(1)
-
-#define TCPC_REG_POWER_CTRL        0x1c
-#define TCPC_REG_POWER_CTRL_FRS_ENABLE                 BIT(7)
-#define TCPC_REG_POWER_CTRL_VBUS_VOL_MONITOR_DIS       BIT(6)
-#define TCPC_REG_POWER_CTRL_AUTO_DISCHARGE_DISCONNECT  BIT(4)
-#define TCPC_REG_POWER_CTRL_FORCE_DISCHARGE            BIT(2)
-#define TCPC_REG_POWER_CTRL_SET(vconn) (vconn)
-#define TCPC_REG_POWER_CTRL_VCONN(reg)    ((reg) & 0x1)
-
-#define TCPC_REG_CC_STATUS         0x1d
-#define TCPC_REG_CC_STATUS_LOOK4CONNECTION_MASK        BIT(5)
-#define TCPC_REG_CC_STATUS_CONNECT_RESULT_MASK         BIT(4)
-#define TCPC_REG_CC_STATUS_CC2_STATE_MASK              (BIT(3)|BIT(2))
-#define TCPC_REG_CC_STATUS_CC1_STATE_MASK              (BIT(1)|BIT(0))
-#define TCPC_REG_CC_STATUS_SET(term, cc1, cc2) \
-		((term) << 4 | ((cc2) & 0x3) << 2 | ((cc1) & 0x3))
-#define TCPC_REG_CC_STATUS_LOOK4CONNECTION(reg) \
-		((reg & TCPC_REG_CC_STATUS_LOOK4CONNECTION_MASK) >> 5)
-#define TCPC_REG_CC_STATUS_TERM(reg) \
-		(((reg) & TCPC_REG_CC_STATUS_CONNECT_RESULT_MASK) >> 4)
-#define TCPC_REG_CC_STATUS_CC2(reg) \
-		(((reg) & TCPC_REG_CC_STATUS_CC2_STATE_MASK) >> 2)
-#define TCPC_REG_CC_STATUS_CC1(reg) \
-		((reg) & TCPC_REG_CC_STATUS_CC1_STATE_MASK)
-
-#define TCPC_REG_POWER_STATUS      0x1e
-#define TCPC_REG_POWER_STATUS_MASK_ALL  0xff
-#define TCPC_REG_POWER_STATUS_UNINIT    BIT(6)
-#define TCPC_REG_POWER_STATUS_SOURCING_VBUS BIT(4)
-#define TCPC_REG_POWER_STATUS_VBUS_DET  BIT(3)
-#define TCPC_REG_POWER_STATUS_VBUS_PRES BIT(2)
-#define TCPC_REG_POWER_STATUS_SINKING_VBUS BIT(0)
-
-#define TCPC_REG_FAULT_STATUS      0x1f
-#define TCPC_REG_FAULT_STATUS_ALL_REGS_RESET            BIT(7)
-#define TCPC_REG_FAULT_STATUS_FORCE_OFF_VBUS            BIT(6)
-#define TCPC_REG_FAULT_STATUS_AUTO_DISCHARGE_FAIL       BIT(5)
-#define TCPC_REG_FAULT_STATUS_FORCE_DISCHARGE_FAIL      BIT(4)
-#define TCPC_REG_FAULT_STATUS_VBUS_OVER_CURRENT         BIT(3)
-#define TCPC_REG_FAULT_STATUS_VBUS_OVER_VOLTAGE         BIT(2)
-#define TCPC_REG_FAULT_STATUS_VCONN_OVER_CURRENT        BIT(1)
-#define TCPC_REG_FAULT_STATUS_I2C_INTERFACE_ERR         BIT(0)
-
-#define TCPC_REG_EXT_STATUS        0x20
-#define TCPC_REG_EXT_STATUS_SAFE0V   BIT(0)
-
-#define TCPC_REG_ALERT_EXT         0x21
-#define TCPC_REG_ALERT_EXT_TIMER_EXPIRED        BIT(2)
-#define TCPC_REG_ALERT_EXT_SRC_FRS              BIT(1)
-#define TCPC_REG_ALERT_EXT_SNK_FRS              BIT(0)
-
-#define TCPC_REG_COMMAND           0x23
-#define TCPC_REG_COMMAND_ENABLE_VBUS_DETECT      0x33
-#define TCPC_REG_COMMAND_SNK_CTRL_LOW            0x44
-#define TCPC_REG_COMMAND_SNK_CTRL_HIGH           0x55
-#define TCPC_REG_COMMAND_SRC_CTRL_LOW            0x66
-#define TCPC_REG_COMMAND_SRC_CTRL_HIGH           0x77
-#define TCPC_REG_COMMAND_LOOK4CONNECTION         0x99
-#define TCPC_REG_COMMAND_I2CIDLE                 0xFF
-
-#define TCPC_REG_DEV_CAP_1         0x24
-
-#define TCPC_REG_DEV_CAP_2         0x26
-#define TCPC_REG_DEV_CAP_2_SNK_FR_SWAP           BIT(9)
-
-#define TCPC_REG_STD_INPUT_CAP     0x28
-#define TCPC_REG_STD_OUTPUT_CAP    0x29
-
-#define TCPC_REG_CONFIG_EXT_1      0x2A
-#define TCPC_REG_CONFIG_EXT_1_FR_SWAP_SNK_DIR	BIT(1)
-
-#define TCPC_REG_MSG_HDR_INFO      0x2e
-#define TCPC_REG_MSG_HDR_INFO_SET(drole, prole) \
-		((drole) << 3 | (PD_REV20 << 1) | (prole))
-#define TCPC_REG_MSG_HDR_INFO_DROLE(reg) (((reg) & 0x8) >> 3)
-#define TCPC_REG_MSG_HDR_INFO_PROLE(reg) ((reg) & 0x1)
-
-#define TCPC_REG_RX_DETECT         0x2f
-#define TCPC_REG_RX_DETECT_SOP_HRST_MASK 0x21
-#define TCPC_REG_RX_DETECT_SOP_SOPP_SOPPP_HRST_MASK 0x27
-
-/* TCPCI Rev 1.0 receive registers */
-#define TCPC_REG_RX_BYTE_CNT       0x30
-#define TCPC_REG_RX_BUF_FRAME_TYPE 0x31
-#define TCPC_REG_RX_HDR            0x32
-#define TCPC_REG_RX_DATA           0x34 /* through 0x4f */
-
-/*
- * In TCPCI Rev 2.0, the RECEIVE_BUFFER is comprised of three sets of registers:
- * READABLE_BYTE_COUNT, RX_BUF_FRAME_TYPE and RX_BUF_BYTE_x. These registers can
- * only be accessed by reading at a common register address 30h.
- */
-#define TCPC_REG_RX_BUFFER         0x30
-
-#define TCPC_REG_TRANSMIT          0x50
-#define TCPC_REG_TRANSMIT_SET_WITH_RETRY(type) \
-		(CONFIG_PD_RETRY_COUNT << 4 | (type))
-#define TCPC_REG_TRANSMIT_SET_WITHOUT_RETRY(type) (type)
-#define TCPC_REG_TRANSMIT_RETRY(reg) (((reg) & 0x30) >> 4)
-#define TCPC_REG_TRANSMIT_TYPE(reg)  ((reg) & 0x7)
-
-/* TCPCI Rev 1.0 transmit registers */
-#define TCPC_REG_TX_BYTE_CNT       0x51
-#define TCPC_REG_TX_HDR            0x52
-#define TCPC_REG_TX_DATA           0x54 /* through 0x6f */
-
-/*
- * In TCPCI Rev 2.0, the TRANSMIT_BUFFER holds the I2C_WRITE_BYTE_COUNT and the
- * portion of the SOP* USB PD message payload (including the header and/or the
- * data bytes) most recently written by the TCPM in TX_BUF_BYTE_x. TX_BUF_BYTE_x
- * is “hidden” and can only be accessed by writing to register address 51h
- */
-#define TCPC_REG_TX_BUFFER         0x51
-
-#define TCPC_REG_VBUS_VOLTAGE                0x70
-#define TCPC_REG_VBUS_SINK_DISCONNECT_THRESH 0x72
-#define TCPC_REG_VBUS_STOP_DISCHARGE_THRESH  0x74
-#define TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG   0x76
-#define TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG   0x78
-
-extern const struct tcpm_drv tcpci_tcpm_drv;
-extern const struct usb_mux_driver tcpci_tcpm_usb_mux_driver;
-
-void tcpci_set_cached_rp(int port, int rp);
-int tcpci_get_cached_rp(int port);
-void tcpci_set_cached_pull(int port, enum tcpc_cc_pull pull);
-enum tcpc_cc_pull tcpci_get_cached_pull(int port);
-
-void tcpci_tcpc_alert(int port);
-int tcpci_tcpm_init(int port);
-int tcpci_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2);
-bool tcpci_tcpm_check_vbus_level(int port, enum vbus_level level);
-int tcpci_tcpm_select_rp_value(int port, int rp);
-int tcpci_tcpm_set_cc(int port, int pull);
-int tcpci_tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity);
-int tcpci_tcpm_sop_prime_disable(int port);
-int tcpci_tcpm_set_vconn(int port, int enable);
-int tcpci_tcpm_set_msg_header(int port, int power_role, int data_role);
-int tcpci_tcpm_set_rx_enable(int port, int enable);
-int tcpci_tcpm_get_message_raw(int port, uint32_t *payload, int *head);
-int tcpci_tcpm_transmit(int port, enum tcpm_transmit_type type,
-			uint16_t header, const uint32_t *data);
-int tcpci_tcpm_release(int port);
-#ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-int tcpci_set_role_ctrl(int port, int toggle, int rp, int pull);
-int tcpci_tcpc_drp_toggle(int port);
-#endif
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-int tcpci_enter_low_power_mode(int port);
-#endif
-#ifdef CONFIG_USB_PD_DISCHARGE_TCPC
-void tcpci_tcpc_discharge_vbus(int port, int enable);
-#endif
-void tcpci_tcpc_enable_auto_discharge_disconnect(int port, int enable);
-int tcpci_tcpc_debug_accessory(int port, bool enable);
-
-int tcpci_tcpm_mux_init(const struct usb_mux *me);
-int tcpci_tcpm_mux_set(const struct usb_mux *me, mux_state_t mux_state);
-int tcpci_tcpm_mux_get(const struct usb_mux *me, mux_state_t *mux_state);
-int tcpci_get_chip_info(int port, int live,
-			struct ec_response_pd_chip_info_v1 *chip_info);
-#ifdef CONFIG_USBC_PPC
-int tcpci_tcpm_get_snk_ctrl(int port, bool *sinking);
-int tcpci_tcpm_set_snk_ctrl(int port, int enable);
-int tcpci_tcpm_get_src_ctrl(int port, bool *sourcing);
-int tcpci_tcpm_set_src_ctrl(int port, int enable);
-#endif
-
-int tcpci_tcpc_fast_role_swap_enable(int port, int enable);
-
-#endif /* __CROS_EC_USB_PD_TCPM_TCPCI_H */
diff --git a/driver/tcpm/tcpm.h b/driver/tcpm/tcpm.h
deleted file mode 100644
index e1db30ecb8..0000000000
--- a/driver/tcpm/tcpm.h
+++ /dev/null
@@ -1,530 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USB Power delivery port management - common header for TCPM drivers */
-
-#ifndef __CROS_EC_USB_PD_TCPM_TCPM_H
-#define __CROS_EC_USB_PD_TCPM_TCPM_H
-
-#include "common.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "i2c.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#if defined(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE) && \
-	!defined(CONFIG_USB_PD_DUAL_ROLE)
-#error "DRP auto toggle requires board to have DRP support"
-#error "Please upgrade your board configuration"
-#endif
-
-#ifndef CONFIG_USB_PD_TCPC
-
-/* I2C wrapper functions - get I2C port / slave addr from config struct. */
-#ifndef CONFIG_USB_PD_TCPC_LOW_POWER
-static inline int tcpc_addr_write(int port, int i2c_addr, int reg, int val)
-{
-	return i2c_write8(tcpc_config[port].i2c_info.port,
-			  i2c_addr, reg, val);
-}
-
-static inline int tcpc_addr_write16(int port, int i2c_addr, int reg, int val)
-{
-	return i2c_write16(tcpc_config[port].i2c_info.port,
-			   i2c_addr, reg, val);
-}
-
-static inline int tcpc_addr_read(int port, int i2c_addr, int reg, int *val)
-{
-	return i2c_read8(tcpc_config[port].i2c_info.port,
-			 i2c_addr, reg, val);
-}
-
-static inline int tcpc_addr_read16(int port, int i2c_addr, int reg, int *val)
-{
-	return i2c_read16(tcpc_config[port].i2c_info.port,
-			  i2c_addr, reg, val);
-}
-
-static inline int tcpc_xfer(int port, const uint8_t *out, int out_size,
-			    uint8_t *in, int in_size)
-{
-	return i2c_xfer(tcpc_config[port].i2c_info.port,
-			tcpc_config[port].i2c_info.addr_flags,
-			out, out_size, in, in_size);
-}
-
-static inline int tcpc_xfer_unlocked(int port, const uint8_t *out, int out_size,
-			    uint8_t *in, int in_size, int flags)
-{
-	return i2c_xfer_unlocked(tcpc_config[port].i2c_info.port,
-				 tcpc_config[port].i2c_info.addr_flags,
-				 out, out_size, in, in_size, flags);
-}
-
-static inline int tcpc_read_block(int port, int reg, uint8_t *in, int size)
-{
-	return i2c_read_block(tcpc_config[port].i2c_info.port,
-			      tcpc_config[port].i2c_info.addr_flags,
-			      reg, in, size);
-}
-
-static inline int tcpc_write_block(int port, int reg,
-		const uint8_t *out, int size)
-{
-	return i2c_write_block(tcpc_config[port].i2c_info.port,
-			       tcpc_config[port].i2c_info.addr_flags,
-			       reg, out, size);
-}
-
-static inline int tcpc_update8(int port, int reg,
-			       uint8_t mask,
-			       enum mask_update_action action)
-{
-	return i2c_update8(tcpc_config[port].i2c_info.port,
-			   tcpc_config[port].i2c_info.addr_flags,
-			   reg, mask, action);
-}
-
-static inline int tcpc_update16(int port, int reg,
-				uint16_t mask,
-				enum mask_update_action action)
-{
-	return i2c_update16(tcpc_config[port].i2c_info.port,
-			    tcpc_config[port].i2c_info.addr_flags,
-			    reg, mask, action);
-}
-
-#else /* !CONFIG_USB_PD_TCPC_LOW_POWER */
-int tcpc_addr_write(int port, int i2c_addr, int reg, int val);
-int tcpc_addr_write16(int port, int i2c_addr, int reg, int val);
-int tcpc_addr_read(int port, int i2c_addr, int reg, int *val);
-int tcpc_addr_read16(int port, int i2c_addr, int reg, int *val);
-int tcpc_read_block(int port, int reg, uint8_t *in, int size);
-int tcpc_write_block(int port, int reg, const uint8_t *out, int size);
-int tcpc_xfer(int port, const uint8_t *out, int out_size,
-		uint8_t *in, int in_size);
-int tcpc_xfer_unlocked(int port, const uint8_t *out, int out_size,
-		uint8_t *in, int in_size, int flags);
-
-int tcpc_update8(int port, int reg,
-		 uint8_t mask, enum mask_update_action action);
-int tcpc_update16(int port, int reg,
-		  uint16_t mask, enum mask_update_action action);
-
-#endif /* CONFIG_USB_PD_TCPC_LOW_POWER */
-
-static inline int tcpc_write(int port, int reg, int val)
-{
-	return tcpc_addr_write(port,
-			       tcpc_config[port].i2c_info.addr_flags, reg, val);
-}
-
-static inline int tcpc_write16(int port, int reg, int val)
-{
-	return tcpc_addr_write16(port,
-			tcpc_config[port].i2c_info.addr_flags, reg, val);
-}
-
-static inline int tcpc_read(int port, int reg, int *val)
-{
-	return tcpc_addr_read(port,
-			      tcpc_config[port].i2c_info.addr_flags, reg, val);
-}
-
-static inline int tcpc_read16(int port, int reg, int *val)
-{
-	return tcpc_addr_read16(port,
-			tcpc_config[port].i2c_info.addr_flags, reg, val);
-}
-
-static inline void tcpc_lock(int port, int lock)
-{
-	i2c_lock(tcpc_config[port].i2c_info.port, lock);
-}
-
-/* TCPM driver wrapper function */
-static inline int tcpm_init(int port)
-{
-	int rv;
-
-	rv = tcpc_config[port].drv->init(port);
-	if (rv)
-		return rv;
-
-	/* Board specific post TCPC init */
-	if (board_tcpc_post_init)
-		rv = board_tcpc_post_init(port);
-
-	return rv;
-}
-
-static inline int tcpm_release(int port)
-{
-	return tcpc_config[port].drv->release(port);
-}
-
-static inline int tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2)
-{
-	return tcpc_config[port].drv->get_cc(port, cc1, cc2);
-}
-
-static inline bool tcpm_check_vbus_level(int port, enum vbus_level level)
-{
-	return tcpc_config[port].drv->check_vbus_level(port, level);
-}
-
-static inline int tcpm_select_rp_value(int port, int rp)
-{
-	return tcpc_config[port].drv->select_rp_value(port, rp);
-}
-
-static inline int tcpm_set_cc(int port, int pull)
-{
-	return tcpc_config[port].drv->set_cc(port, pull);
-}
-
-static inline int tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity)
-{
-	return tcpc_config[port].drv->set_polarity(port, polarity);
-}
-
-static inline int tcpm_sop_prime_disable(int port)
-{
-#ifdef CONFIG_USB_PD_DECODE_SOP
-	return tcpc_config[port].drv->sop_prime_disable(port);
-#else
-	return EC_SUCCESS;
-#endif
-}
-
-static inline int tcpm_set_vconn(int port, int enable)
-{
-	return tcpc_config[port].drv->set_vconn(port, enable);
-}
-
-static inline int tcpm_set_msg_header(int port, int power_role, int data_role)
-{
-	return tcpc_config[port].drv->set_msg_header(port, power_role,
-						     data_role);
-}
-
-static inline int tcpm_set_rx_enable(int port, int enable)
-{
-	return tcpc_config[port].drv->set_rx_enable(port, enable);
-}
-
-static inline void tcpm_enable_auto_discharge_disconnect(int port, int enable)
-{
-	const struct tcpm_drv *tcpc = tcpc_config[port].drv;
-
-	if (tcpc->tcpc_enable_auto_discharge_disconnect)
-		tcpc->tcpc_enable_auto_discharge_disconnect(port, enable);
-}
-
-/**
- * Reads a message using get_message_raw driver method and puts it into EC's
- * cache.
- */
-int tcpm_enqueue_message(int port);
-
-static inline int tcpm_transmit(int port, enum tcpm_transmit_type type,
-				uint16_t header, const uint32_t *data)
-{
-	return tcpc_config[port].drv->transmit(port, type, header, data);
-}
-
-#ifdef CONFIG_USBC_PPC
-static inline int tcpm_get_snk_ctrl(int port, bool *sinking)
-{
-	int rv = EC_ERROR_UNIMPLEMENTED;
-
-	if (tcpc_config[port].drv->get_snk_ctrl != NULL)
-		rv = tcpc_config[port].drv->get_snk_ctrl(port, sinking);
-	else
-		*sinking = false;
-
-	return rv;
-}
-static inline int tcpm_set_snk_ctrl(int port, int enable)
-{
-	if (tcpc_config[port].drv->set_snk_ctrl != NULL)
-		return tcpc_config[port].drv->set_snk_ctrl(port, enable);
-	else
-		return EC_ERROR_UNIMPLEMENTED;
-}
-
-static inline int tcpm_get_src_ctrl(int port, bool *sourcing)
-{
-	int rv = EC_ERROR_UNIMPLEMENTED;
-
-	if (tcpc_config[port].drv->get_src_ctrl != NULL)
-		rv = tcpc_config[port].drv->get_src_ctrl(port, sourcing);
-	else
-		*sourcing = false;
-
-	return rv;
-}
-static inline int tcpm_set_src_ctrl(int port, int enable)
-{
-	if (tcpc_config[port].drv->set_src_ctrl != NULL)
-		return tcpc_config[port].drv->set_src_ctrl(port, enable);
-	else
-		return EC_ERROR_UNIMPLEMENTED;
-}
-#endif
-
-static inline void tcpc_alert(int port)
-{
-	tcpc_config[port].drv->tcpc_alert(port);
-}
-
-static inline void tcpc_discharge_vbus(int port, int enable)
-{
-	tcpc_config[port].drv->tcpc_discharge_vbus(port, enable);
-}
-
-#ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-static inline int tcpm_auto_toggle_supported(int port)
-{
-	return !!tcpc_config[port].drv->drp_toggle;
-}
-
-static inline int tcpm_enable_drp_toggle(int port)
-{
-	return tcpc_config[port].drv->drp_toggle(port);
-}
-#else
-static inline int tcpm_auto_toggle_supported(int port)
-{
-	return false;
-}
-#endif
-
-static inline int tcpm_debug_accessory(int port, bool enable)
-{
-	if (tcpc_config[port].drv->debug_accessory)
-		return tcpc_config[port].drv->debug_accessory(port, enable);
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-static inline int tcpm_enter_low_power_mode(int port)
-{
-	return tcpc_config[port].drv->enter_low_power_mode(port);
-}
-#endif
-
-#ifdef CONFIG_CMD_I2C_STRESS_TEST_TCPC
-static inline int tcpc_i2c_read(const int port, const uint16_t addr_flags,
-				const int reg, int *data)
-{
-	return tcpc_read(port, reg, data);
-}
-
-static inline int tcpc_i2c_write(const int port, const uint16_t addr_flags,
-				 const int reg, int data)
-{
-	return tcpc_write(port, reg, data);
-}
-#endif
-
-static inline int tcpm_get_chip_info(int port, int live,
-				     struct ec_response_pd_chip_info_v1 *info)
-{
-	if (tcpc_config[port].drv->get_chip_info)
-		return tcpc_config[port].drv->get_chip_info(port, live, info);
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-#ifdef CONFIG_USB_PD_FRS_TCPC
-static inline int tcpm_set_frs_enable(int port, int enable)
-{
-	const struct tcpm_drv *tcpc;
-	int rv = EC_SUCCESS;
-
-	/*
-	 * set_frs_enable will be set to tcpci_tcp_fast_role_swap_enable
-	 * if it is handled by the tcpci for the tcpc chipset
-	 */
-	tcpc = tcpc_config[port].drv;
-	if (tcpc->set_frs_enable)
-		rv = tcpc->set_frs_enable(port, enable);
-	return rv;
-}
-#endif /* defined(CONFIG_USB_PD_FRS_TCPC) */
-
-#else
-
-/**
- * Initialize TCPM driver and wait for TCPC readiness.
- *
- * @param port Type-C port number
- *
- * @return EC_SUCCESS or error
- */
-int tcpm_init(int port);
-
-/**
- * Read the CC line status.
- *
- * @param port Type-C port number
- * @param cc1 pointer to CC status for CC1
- * @param cc2 pointer to CC status for CC2
- *
- * @return EC_SUCCESS or error
- */
-int tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2);
-
-/**
- * Check VBUS level
- *
- * @param port Type-C port number
- * @param level safe level voltage to check against
- *
- * @return False => VBUS not at level, True => VBUS at level
- */
-bool tcpm_check_vbus_level(int port, enum vbus_level level);
-
-/**
- * Set the value of the CC pull-up used when we are a source.
- *
- * @param port Type-C port number
- * @param rp One of enum tcpc_rp_value
- *
- * @return EC_SUCCESS or error
- */
-int tcpm_select_rp_value(int port, int rp);
-
-/**
- * Set the CC pull resistor. This sets our role as either source or sink.
- *
- * @param port Type-C port number
- * @param pull One of enum tcpc_cc_pull
- *
- * @return EC_SUCCESS or error
- */
-int tcpm_set_cc(int port, int pull);
-
-/**
- * Set polarity
- *
- * @param port Type-C port number
- * @param polarity port polarity
- *
- * @return EC_SUCCESS or error
- */
-int tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity);
-
-/**
- * Set Vconn.
- *
- * @param port Type-C port number
- * @param enable Enable/Disable Vconn
- *
- * @return EC_SUCCESS or error
- */
-int tcpm_set_vconn(int port, int enable);
-
-/**
- * Set PD message header to use for goodCRC
- *
- * @param port Type-C port number
- * @param power_role Power role to use in header
- * @param data_role Data role to use in header
- *
- * @return EC_SUCCESS or error
- */
-int tcpm_set_msg_header(int port, int power_role, int data_role);
-
-/**
- * Set RX enable flag
- *
- * @param port Type-C port number
- * @enable true for enable, false for disable
- *
- * @return EC_SUCCESS or error
- */
-int tcpm_set_rx_enable(int port, int enable);
-
-/**
- * Enable Auto Discharge Disconnect
- *
- * @param port Type-C port number
- * @param enable true for enable, false for disable
- */
-void tcpm_enable_auto_discharge_disconnect(int port, int enable);
-
-/**
- * Transmit PD message
- *
- * @param port Type-C port number
- * @param type Transmit type
- * @param header Packet header
- * @param cnt Number of bytes in payload
- * @param data Payload
- *
- * @return EC_SUCCESS or error
- */
-int tcpm_transmit(int port, enum tcpm_transmit_type type, uint16_t header,
-		  const uint32_t *data);
-
-/**
- * TCPC is asserting alert
- *
- * @param port Type-C port number
- */
-void tcpc_alert(int port);
-
-#endif
-
-/**
- * Gets the next waiting RX message.
- *
- * @param port Type-C port number
- * @param payload Pointer to location to copy payload of PD message
- * @param header The header of PD message
- *
- * @return EC_SUCCESS or error
- */
-int tcpm_dequeue_message(int port, uint32_t *payload, int *header);
-
-/**
- * Returns true if the tcpm has RX messages waiting to be consumed.
- */
-int tcpm_has_pending_message(int port);
-
-/**
- * Clear any pending messages in the RX queue.  This function must be
- * called from the same context as the caller of tcpm_dequeue_message to avoid
- * race conditions.
- */
-void tcpm_clear_pending_messages(int port);
-
-/**
- * Enable/Disable TCPC Fast Role Swap detection
- *
- * @param port Type-C port number
- * @param enable FRS enable (true) disable (false)
- * @return EC_SUCCESS on success, or an error
- */
-int tcpm_set_frs_enable(int port, int enable);
-
-#ifdef CONFIG_CMD_TCPC_DUMP
-static inline void tcpm_dump_registers(int port)
-{
-	const struct tcpm_drv *tcpc = tcpc_config[port].drv;
-
-	if (tcpc->dump_registers)
-		tcpc->dump_registers(port);
-	else
-		tcpc_dump_std_registers(port);
-}
-#endif /* defined(CONFIG_CMD_TCPC_DUMP) */
-
-#endif
diff --git a/driver/tcpm/tusb422.c b/driver/tcpm/tusb422.c
index 75ffcd1d43..79554bd0cf 100644
--- a/driver/tcpm/tusb422.c
+++ b/driver/tcpm/tusb422.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,10 +6,10 @@
 /* Type-C port manager for TI TUSB422 Port Controller */
 
 #include "common.h"
-#include "tusb422.h"
-#include "tcpci.h"
-#include "tcpm.h"
+#include "tcpm/tcpci.h"
+#include "tcpm/tcpm.h"
 #include "timer.h"
+#include "tusb422.h"
 #include "usb_pd.h"
 
 #ifndef CONFIG_USB_PD_TCPM_TCPCI
@@ -20,14 +20,14 @@
 
 #if defined(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE) && \
 	!defined(CONFIG_USB_PD_TCPC_LOW_POWER)
-#error "TUSB422 driver requires CONFIG_USB_PD_TCPC_LOW_POWER if"
-#error "CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE is enabled"
+#error "TUSB422 driver requires CONFIG_USB_PD_TCPC_LOW_POWER if " \
+		"CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE is enabled"
 #endif
 
 #if defined(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE) && \
 	defined(CONFIG_USB_PD_DISCHARGE_TCPC)
-#error "TUSB422 must disable TCPC discharge to support enabling Auto Discharge"
-#error "Disconnect all the time."
+#error "TUSB422 must disable TCPC discharge to support enabling Auto " \
+		"Discharge Disconnect all the time."
 #endif
 
 enum tusb422_reg_addr {
@@ -36,7 +36,7 @@ enum tusb422_reg_addr {
 
 enum vbus_and_vconn_control_mask {
 	INT_VCONNDIS_DISABLE = BIT(1),
-	INT_VBUSDIS_DISABLE  = BIT(2),
+	INT_VBUSDIS_DISABLE = BIT(2),
 };
 
 /* The TUSB422 cannot drive an FRS GPIO, but can detect FRS */
@@ -51,11 +51,16 @@ static int tusb422_tcpci_tcpm_init(int port)
 {
 	int rv;
 
-	/* TUSB422 has a vendor-defined register reset */
-	rv = tcpc_update8(port, TUSB422_REG_CC_GEN_CTRL,
-			  TUSB422_REG_CC_GEN_CTRL_GLOBAL_SW_RST, MASK_SET);
-	if (rv)
-		return rv;
+	/*
+	 * Do not perform TCPC soft reset while waking from Low Power Mode,
+	 * because it makes DRP incapable of looking for connection correctly
+	 * (see b/176986511) and probably breaks firmware_PDTrySrc test
+	 * (see b/179234089).
+	 *
+	 * TODO(b/179234089): Consider implementing function that performs
+	 * only necessary things when leaving Low Power Mode, so we can perform
+	 * TCPC soft reset here.
+	 */
 
 	rv = tcpci_tcpm_init(port);
 	if (rv)
@@ -81,7 +86,7 @@ static int tusb422_tcpci_tcpm_init(int port)
 		 * Mode.
 		 */
 		tcpc_write(port, TUSB422_REG_VBUS_AND_VCONN_CONTROL,
-				INT_VBUSDIS_DISABLE);
+			   INT_VBUSDIS_DISABLE);
 	}
 	if (IS_ENABLED(CONFIG_USB_PD_FRS_TCPC)) {
 		/* Disable FRS detection, and enable the FRS detection alert */
@@ -98,7 +103,7 @@ static int tusb422_tcpci_tcpm_init(int port)
 	 */
 	/* Enable VBUS detection */
 	return tcpc_write16(port, TCPC_REG_COMMAND,
-				TCPC_REG_COMMAND_ENABLE_VBUS_DETECT);
+			    TCPC_REG_COMMAND_ENABLE_VBUS_DETECT);
 }
 
 static int tusb422_tcpm_set_cc(int port, int pull)
@@ -149,41 +154,41 @@ static void tusb422_tcpci_tcpc_alert(int port)
 }
 
 const struct tcpm_drv tusb422_tcpm_drv = {
-	.init			= &tusb422_tcpci_tcpm_init,
-	.release		= &tcpci_tcpm_release,
-	.get_cc			= &tcpci_tcpm_get_cc,
+	.init = &tusb422_tcpci_tcpm_init,
+	.release = &tcpci_tcpm_release,
+	.get_cc = &tcpci_tcpm_get_cc,
 #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	.check_vbus_level	= &tcpci_tcpm_check_vbus_level,
+	.check_vbus_level = &tcpci_tcpm_check_vbus_level,
 #endif
-	.select_rp_value	= &tcpci_tcpm_select_rp_value,
-	.set_cc			= &tusb422_tcpm_set_cc,
-	.set_polarity		= &tcpci_tcpm_set_polarity,
+	.select_rp_value = &tcpci_tcpm_select_rp_value,
+	.set_cc = &tusb422_tcpm_set_cc,
+	.set_polarity = &tcpci_tcpm_set_polarity,
 #ifdef CONFIG_USB_PD_DECODE_SOP
-	.sop_prime_disable	= &tcpci_tcpm_sop_prime_disable,
+	.sop_prime_enable = &tcpci_tcpm_sop_prime_enable,
 #endif
-	.set_vconn		= &tcpci_tcpm_set_vconn,
-	.set_msg_header		= &tcpci_tcpm_set_msg_header,
-	.set_rx_enable		= &tcpci_tcpm_set_rx_enable,
-	.get_message_raw	= &tcpci_tcpm_get_message_raw,
-	.transmit		= &tcpci_tcpm_transmit,
-	.tcpc_alert		= &tusb422_tcpci_tcpc_alert,
+	.set_vconn = &tcpci_tcpm_set_vconn,
+	.set_msg_header = &tcpci_tcpm_set_msg_header,
+	.set_rx_enable = &tcpci_tcpm_set_rx_enable,
+	.get_message_raw = &tcpci_tcpm_get_message_raw,
+	.transmit = &tcpci_tcpm_transmit,
+	.tcpc_alert = &tusb422_tcpci_tcpc_alert,
 #ifdef CONFIG_USB_PD_DISCHARGE_TCPC
-	.tcpc_discharge_vbus	= &tcpci_tcpc_discharge_vbus,
+	.tcpc_discharge_vbus = &tcpci_tcpc_discharge_vbus,
 #endif
 	.tcpc_enable_auto_discharge_disconnect =
-				  &tcpci_tcpc_enable_auto_discharge_disconnect,
+		&tcpci_tcpc_enable_auto_discharge_disconnect,
 #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-	.drp_toggle		= &tusb422_tcpc_drp_toggle,
-#endif
-#ifdef CONFIG_USBC_PPC
-	.set_snk_ctrl		= &tcpci_tcpm_set_snk_ctrl,
-	.set_src_ctrl		= &tcpci_tcpm_set_src_ctrl,
+	.drp_toggle = &tusb422_tcpc_drp_toggle,
 #endif
-	.get_chip_info		= &tcpci_get_chip_info,
+	.get_chip_info = &tcpci_get_chip_info,
+	.set_snk_ctrl = &tcpci_tcpm_set_snk_ctrl,
+	.set_src_ctrl = &tcpci_tcpm_set_src_ctrl,
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	.enter_low_power_mode	= &tcpci_enter_low_power_mode,
+	.enter_low_power_mode = &tcpci_enter_low_power_mode,
 #endif
+	.set_bist_test_mode = &tcpci_set_bist_test_mode,
+	.get_bist_test_mode = &tcpci_get_bist_test_mode,
 #ifdef CONFIG_USB_PD_FRS_TCPC
-	.set_frs_enable         = &tusb422_set_frs_enable,
+	.set_frs_enable = &tusb422_set_frs_enable,
 #endif
 };
diff --git a/driver/tcpm/tusb422.h b/driver/tcpm/tusb422.h
index 54ae0c7e02..2ce601c866 100644
--- a/driver/tcpm/tusb422.h
+++ b/driver/tcpm/tusb422.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,8 +8,7 @@
 #ifndef __CROS_EC_USB_PD_TCPM_TUSB422_H
 #define __CROS_EC_USB_PD_TCPM_TUSB422_H
 
-/* I2C interface */
-#define TUSB422_I2C_ADDR_FLAGS 0x20
+#include "driver/tcpm/tusb422_public.h"
 
 #define TUSB422_REG_VENDOR_INTERRUPTS_STATUS 0x90
 #define TUSB422_REG_VENDOR_INTERRUPTS_STATUS_FRS_RX BIT(0)
@@ -17,12 +16,7 @@
 #define TUSB422_REG_VENDOR_INTERRUPTS_MASK 0x92
 #define TUSB422_REG_VENDOR_INTERRUPTS_MASK_FRS_RX BIT(0)
 
-#define TUSB422_REG_CC_GEN_CTRL 0x94
-#define TUSB422_REG_CC_GEN_CTRL_GLOBAL_SW_RST BIT(5)
-
 #define TUSB422_REG_PHY_BMC_RX_CTRL 0x96
 #define TUSB422_REG_PHY_BMC_RX_CTRL_FRS_RX_EN BIT(3)
 
-extern const struct tcpm_drv tusb422_tcpm_drv;
-
 #endif /* defined(__CROS_EC_USB_PD_TCPM_TUSB422_H) */
diff --git a/driver/temp_sensor/adt7481.c b/driver/temp_sensor/adt7481.c
index cbd32e5cd5..f0aee1506f 100644
--- a/driver/temp_sensor/adt7481.c
+++ b/driver/temp_sensor/adt7481.c
@@ -1,16 +1,16 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* ADT7481 temperature sensor module for Chrome EC */
 
+#include "adt7481.h"
 #include "common.h"
 #include "console.h"
-#include "adt7481.h"
 #include "gpio.h"
-#include "i2c.h"
 #include "hooks.h"
+#include "i2c.h"
 #include "util.h"
 
 static int temp_val_local;
@@ -25,8 +25,8 @@ static uint8_t is_sensor_shutdown;
  */
 static int has_power(void)
 {
-#ifdef CONFIG_TEMP_SENSOR_POWER_GPIO
-	return gpio_get_level(CONFIG_TEMP_SENSOR_POWER_GPIO);
+#ifdef CONFIG_TEMP_SENSOR_POWER
+	return gpio_get_level(GPIO_TEMP_SENSOR_POWER);
 #else
 	return !is_sensor_shutdown;
 #endif
@@ -34,14 +34,14 @@ static int has_power(void)
 
 static int raw_read8(const int offset, int *data_ptr)
 {
-	return i2c_read8(I2C_PORT_THERMAL, ADT7481_I2C_ADDR_FLAGS,
-			 offset, data_ptr);
+	return i2c_read8(I2C_PORT_THERMAL, ADT7481_I2C_ADDR_FLAGS, offset,
+			 data_ptr);
 }
 
 static int raw_write8(const int offset, int data)
 {
-	return i2c_write8(I2C_PORT_THERMAL, ADT7481_I2C_ADDR_FLAGS,
-			  offset, data);
+	return i2c_write8(I2C_PORT_THERMAL, ADT7481_I2C_ADDR_FLAGS, offset,
+			  data);
 }
 
 static int get_temp(const int offset, int *temp_ptr)
@@ -145,7 +145,7 @@ int adt7481_set_therm_limit(int channel, int limit_c, int hysteresis)
 		return EC_ERROR_INVAL;
 
 	if (hysteresis > ADT7481_HYSTERESIS_HIGH_LIMIT ||
-		hysteresis < ADT7481_HYSTERESIS_LOW_LIMIT)
+	    hysteresis < ADT7481_HYSTERESIS_LOW_LIMIT)
 		return EC_ERROR_INVAL;
 
 	/* hysteresis must be less than high limit */
@@ -197,12 +197,10 @@ static void adt7481_temp_sensor_poll(void)
 DECLARE_HOOK(HOOK_SECOND, adt7481_temp_sensor_poll, HOOK_PRIO_TEMP_SENSOR);
 
 #ifdef CONFIG_CMD_TEMP_SENSOR
-static void print_temps(
-		const char *name,
-		const int adt7481_temp_reg,
-		const int adt7481_therm_limit_reg,
-		const int adt7481_high_limit_reg,
-		const int adt7481_low_limit_reg)
+static void print_temps(const char *name, const int adt7481_temp_reg,
+			const int adt7481_therm_limit_reg,
+			const int adt7481_high_limit_reg,
+			const int adt7481_low_limit_reg)
 {
 	int value;
 
@@ -230,39 +228,33 @@ static int print_status(void)
 {
 	int value;
 
-	print_temps("Local", ADT7481_LOCAL,
-		    ADT7481_LOCAL_THERM_LIMIT,
-		    ADT7481_LOCAL_HIGH_LIMIT_R,
-		    ADT7481_LOCAL_LOW_LIMIT_R);
+	print_temps("Local", ADT7481_LOCAL, ADT7481_LOCAL_THERM_LIMIT,
+		    ADT7481_LOCAL_HIGH_LIMIT_R, ADT7481_LOCAL_LOW_LIMIT_R);
 
-	print_temps("Remote1", ADT7481_REMOTE1,
-		    ADT7481_REMOTE1_THERM_LIMIT,
-		    ADT7481_REMOTE1_HIGH_LIMIT_R,
-		    ADT7481_REMOTE1_LOW_LIMIT_R);
+	print_temps("Remote1", ADT7481_REMOTE1, ADT7481_REMOTE1_THERM_LIMIT,
+		    ADT7481_REMOTE1_HIGH_LIMIT_R, ADT7481_REMOTE1_LOW_LIMIT_R);
 
-	print_temps("Remote2", ADT7481_REMOTE2,
-		    ADT7481_REMOTE2_THERM_LIMIT,
-		    ADT7481_REMOTE2_HIGH_LIMIT,
-		    ADT7481_REMOTE2_LOW_LIMIT);
+	print_temps("Remote2", ADT7481_REMOTE2, ADT7481_REMOTE2_THERM_LIMIT,
+		    ADT7481_REMOTE2_HIGH_LIMIT, ADT7481_REMOTE2_LOW_LIMIT);
 
 	ccprintf("\n");
 
 	if (raw_read8(ADT7481_STATUS1_R, &value) == EC_SUCCESS)
-		ccprintf("STATUS1:  %pb\n", BINARY_VALUE(value, 8));
+		ccprintf("STATUS1:  0x%x\n", value);
 
 	if (raw_read8(ADT7481_STATUS2_R, &value) == EC_SUCCESS)
-		ccprintf("STATUS2:  %pb\n", BINARY_VALUE(value, 8));
+		ccprintf("STATUS2:  0x%x\n", value);
 
 	if (raw_read8(ADT7481_CONFIGURATION1_R, &value) == EC_SUCCESS)
-		ccprintf("CONFIG1: %pb\n", BINARY_VALUE(value, 8));
+		ccprintf("CONFIG1: 0x%x\n", value);
 
 	if (raw_read8(ADT7481_CONFIGURATION2, &value) == EC_SUCCESS)
-		ccprintf("CONFIG2: %pb\n", BINARY_VALUE(value, 8));
+		ccprintf("CONFIG2: 0x%x\n", value);
 
 	return EC_SUCCESS;
 }
 
-static int command_adt7481(int argc, char **argv)
+static int command_adt7481(int argc, const char **argv)
 {
 	char *command;
 	char *e;
@@ -307,8 +299,7 @@ static int command_adt7481(int argc, char **argv)
 		rv = raw_read8(offset, &data);
 		if (rv < 0)
 			return rv;
-		ccprintf("Byte at offset 0x%02x is %pb\n",
-			 offset, BINARY_VALUE(data, 8));
+		ccprintf("Byte at offset 0x%02x is 0x%x\n", offset, data);
 		return rv;
 	}
 
@@ -331,7 +322,8 @@ static int command_adt7481(int argc, char **argv)
 
 	return rv;
 }
-DECLARE_CONSOLE_COMMAND(adt7481, command_adt7481,
+DECLARE_CONSOLE_COMMAND(
+	adt7481, command_adt7481,
 	"[settemp|setbyte <offset> <value>] or [getbyte <offset>] or"
 	"[power <on|off>]. "
 	"Temps in Celsius.",
@@ -340,13 +332,12 @@ DECLARE_CONSOLE_COMMAND(adt7481, command_adt7481,
 
 int adt7481_set_power(enum adt7481_power_state power_on)
 {
-#ifndef CONFIG_TEMP_SENSOR_POWER_GPIO
+#ifndef CONFIG_TEMP_SENSOR_POWER
 	uint8_t shutdown = (power_on == ADT7481_POWER_OFF) ? 1 : 0;
 
 	return adt7481_shutdown(shutdown);
 #else
-	gpio_set_level(CONFIG_TEMP_SENSOR_POWER_GPIO, power_on);
+	gpio_set_level(GPIO_TEMP_SENSOR_POWER, power_on);
 	return EC_SUCCESS;
 #endif
 }
-
diff --git a/driver/temp_sensor/adt7481.h b/driver/temp_sensor/adt7481.h
index 78541a0a3b..af2b676f0d 100644
--- a/driver/temp_sensor/adt7481.h
+++ b/driver/temp_sensor/adt7481.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,120 +8,118 @@
 #ifndef __CROS_EC_ADT7481_H
 #define __CROS_EC_ADT7481_H
 
-#define ADT7481_I2C_ADDR_FLAGS		0x4B
+#define ADT7481_I2C_ADDR_FLAGS 0x4B
 
-#define ADT7481_IDX_LOCAL	0
-#define ADT7481_IDX_REMOTE1	1
-#define ADT7481_IDX_REMOTE2	2
+#define ADT7481_IDX_LOCAL 0
+#define ADT7481_IDX_REMOTE1 1
+#define ADT7481_IDX_REMOTE2 2
 
 /* Chip-specific registers */
-#define ADT7481_LOCAL			0x00
-#define ADT7481_REMOTE1			0x01
-#define ADT7481_STATUS1_R		0x02
-#define ADT7481_CONFIGURATION1_R	0x03
-#define ADT7481_CONVERSION_RATE_R	0x04
-#define ADT7481_LOCAL_HIGH_LIMIT_R	0x05
-#define ADT7481_LOCAL_LOW_LIMIT_R	0x06
-#define ADT7481_REMOTE1_HIGH_LIMIT_R	0x07
-#define ADT7481_REMOTE1_LOW_LIMIT_R	0x08
-#define ADT7481_CONFIGURATION1_W	0x09
-#define ADT7481_CONVERSION_RATE_W	0x0a
-#define ADT7481_LOCAL_HIGH_LIMIT_W	0x0b
-#define ADT7481_LOCAL_LOW_LIMIT_W	0x0c
-#define ADT7481_REMOTE1_HIGH_LIMIT_W	0x0d
-#define ADT7481_REMOTE1_LOW_LIMIT_W	0x0e
-#define ADT7481_ONESHOT_W		0x0f
-#define ADT7481_REMOTE1_EXTD_R		0x10
-#define ADT7481_REMOTE1_OFFSET		0x11
-#define ADT7481_REMOTE1_OFFSET_EXTD	0x12
-#define ADT7481_REMOTE1_HIGH_LIMIT_EXTD	0x13
-#define ADT7481_REMOTE1_LOW_LIMIT_EXTD	0x14
-#define ADT7481_REMOTE1_THERM_LIMIT	0x19
-#define ADT7481_LOCAL_THERM_LIMIT	0x20
-#define ADT7481_THERM_HYSTERESIS	0x21
-#define ADT7481_CONSECUTIVE_ALERT	0x22
-#define ADT7481_STATUS2_R		0x23
-#define ADT7481_CONFIGURATION2		0x24
-#define ADT7481_REMOTE2			0x30
-#define ADT7481_REMOTE2_HIGH_LIMIT	0x31
-#define ADT7481_REMOTE2_LOW_LIMIT	0x32
-#define ADT7481_REMOTE2_EXTD_R		0x33
-#define ADT7481_REMOTE2_OFFSET		0x34
-#define ADT7481_REMOTE2_OFFSET_EXTD	0x35
-#define ADT7481_REMOTE2_HIGH_LIMIT_EXTD	0x36
-#define ADT7481_REMOTE2_LOW_LIMIT_EXTD	0x37
-#define ADT7481_REMOTE2_THERM_LIMIT	0x39
-#define ADT7481_DEVICE_ID		0x3d
-#define ADT7481_MANUFACTURER_ID		0x3e
+#define ADT7481_LOCAL 0x00
+#define ADT7481_REMOTE1 0x01
+#define ADT7481_STATUS1_R 0x02
+#define ADT7481_CONFIGURATION1_R 0x03
+#define ADT7481_CONVERSION_RATE_R 0x04
+#define ADT7481_LOCAL_HIGH_LIMIT_R 0x05
+#define ADT7481_LOCAL_LOW_LIMIT_R 0x06
+#define ADT7481_REMOTE1_HIGH_LIMIT_R 0x07
+#define ADT7481_REMOTE1_LOW_LIMIT_R 0x08
+#define ADT7481_CONFIGURATION1_W 0x09
+#define ADT7481_CONVERSION_RATE_W 0x0a
+#define ADT7481_LOCAL_HIGH_LIMIT_W 0x0b
+#define ADT7481_LOCAL_LOW_LIMIT_W 0x0c
+#define ADT7481_REMOTE1_HIGH_LIMIT_W 0x0d
+#define ADT7481_REMOTE1_LOW_LIMIT_W 0x0e
+#define ADT7481_ONESHOT_W 0x0f
+#define ADT7481_REMOTE1_EXTD_R 0x10
+#define ADT7481_REMOTE1_OFFSET 0x11
+#define ADT7481_REMOTE1_OFFSET_EXTD 0x12
+#define ADT7481_REMOTE1_HIGH_LIMIT_EXTD 0x13
+#define ADT7481_REMOTE1_LOW_LIMIT_EXTD 0x14
+#define ADT7481_REMOTE1_THERM_LIMIT 0x19
+#define ADT7481_LOCAL_THERM_LIMIT 0x20
+#define ADT7481_THERM_HYSTERESIS 0x21
+#define ADT7481_CONSECUTIVE_ALERT 0x22
+#define ADT7481_STATUS2_R 0x23
+#define ADT7481_CONFIGURATION2 0x24
+#define ADT7481_REMOTE2 0x30
+#define ADT7481_REMOTE2_HIGH_LIMIT 0x31
+#define ADT7481_REMOTE2_LOW_LIMIT 0x32
+#define ADT7481_REMOTE2_EXTD_R 0x33
+#define ADT7481_REMOTE2_OFFSET 0x34
+#define ADT7481_REMOTE2_OFFSET_EXTD 0x35
+#define ADT7481_REMOTE2_HIGH_LIMIT_EXTD 0x36
+#define ADT7481_REMOTE2_LOW_LIMIT_EXTD 0x37
+#define ADT7481_REMOTE2_THERM_LIMIT 0x39
+#define ADT7481_DEVICE_ID 0x3d
+#define ADT7481_MANUFACTURER_ID 0x3e
 
 /* Config1 register bits */
-#define ADT7481_CONFIG1_REMOTE1_ALERT_MASK	BIT(0)
-#define ADT7481_CONFIG1_REMOTE2_ALERT_MASK	BIT(1)
-#define ADT7481_CONFIG1_TEMP_RANGE		BIT(2)
-#define ADT7481_CONFIG1_SEL_REMOTE2		BIT(3)
+#define ADT7481_CONFIG1_REMOTE1_ALERT_MASK BIT(0)
+#define ADT7481_CONFIG1_REMOTE2_ALERT_MASK BIT(1)
+#define ADT7481_CONFIG1_TEMP_RANGE BIT(2)
+#define ADT7481_CONFIG1_SEL_REMOTE2 BIT(3)
 /* ADT7481_CONFIG1_MODE bit is use to enable THERM mode */
-#define ADT7481_CONFIG1_MODE			BIT(5)
-#define ADT7481_CONFIG1_RUN_L			BIT(6)
+#define ADT7481_CONFIG1_MODE BIT(5)
+#define ADT7481_CONFIG1_RUN_L BIT(6)
 /* mask all alerts on ALERT# pin */
-#define ADT7481_CONFIG1_ALERT_MASK_L		BIT(7)
+#define ADT7481_CONFIG1_ALERT_MASK_L BIT(7)
 
 /* Config2 register bits */
-#define ADT7481_CONFIG2_LOCK			BIT(7)
+#define ADT7481_CONFIG2_LOCK BIT(7)
 
 /* Conversion Rate/Channel Select Register */
-#define ADT7481_CONV_RATE_MASK		(0x0f)
-#define ADT7481_CONV_RATE_16S		(0x00)
-#define ADT7481_CONV_RATE_8S		(0x01)
-#define ADT7481_CONV_RATE_4S		(0x02)
-#define ADT7481_CONV_RATE_2S		(0x03)
-#define ADT7481_CONV_RATE_1S		(0x04)
-#define ADT7481_CONV_RATE_500MS		(0x05)
-#define ADT7481_CONV_RATE_250MS		(0x06)
-#define ADT7481_CONV_RATE_125MS		(0x07)
-#define ADT7481_CONV_RATE_62500US	(0x08)
-#define ADT7481_CONV_RATE_31250US	(0x09)
-#define ADT7481_CONV_RATE_15500US	(0x0a)
+#define ADT7481_CONV_RATE_MASK (0x0f)
+#define ADT7481_CONV_RATE_16S (0x00)
+#define ADT7481_CONV_RATE_8S (0x01)
+#define ADT7481_CONV_RATE_4S (0x02)
+#define ADT7481_CONV_RATE_2S (0x03)
+#define ADT7481_CONV_RATE_1S (0x04)
+#define ADT7481_CONV_RATE_500MS (0x05)
+#define ADT7481_CONV_RATE_250MS (0x06)
+#define ADT7481_CONV_RATE_125MS (0x07)
+#define ADT7481_CONV_RATE_62500US (0x08)
+#define ADT7481_CONV_RATE_31250US (0x09)
+#define ADT7481_CONV_RATE_15500US (0x0a)
 /* continuous mode 73 ms averaging */
-#define ADT7481_CONV_RATE_73MS_AVE	(0x0b)
-#define ADT7481_CONV_CHAN_SELECT_MASK	(0x30)
-#define ADT7481_CONV_CHAN_SEL_ROUND_ROBIN	(0 << 4)
-#define ADT7481_CONV_CHAN_SEL_LOCAL		BIT(4)
-#define ADT7481_CONV_CHAN_SEL_REMOTE1		(2 << 4)
-#define ADT7481_CONV_CHAN_SEL_REMOTE2		(3 << 4)
-#define ADT7481_CONV_AVERAGING_L	BIT(7)
-
+#define ADT7481_CONV_RATE_73MS_AVE (0x0b)
+#define ADT7481_CONV_CHAN_SELECT_MASK (0x30)
+#define ADT7481_CONV_CHAN_SEL_ROUND_ROBIN (0 << 4)
+#define ADT7481_CONV_CHAN_SEL_LOCAL BIT(4)
+#define ADT7481_CONV_CHAN_SEL_REMOTE1 (2 << 4)
+#define ADT7481_CONV_CHAN_SEL_REMOTE2 (3 << 4)
+#define ADT7481_CONV_AVERAGING_L BIT(7)
 
 /* Status1 register bits */
-#define ADT7481_STATUS1_LOCAL_THERM_ALARM	BIT(0)
-#define ADT7481_STATUS1_REMOTE1_THERM_ALARM	BIT(1)
-#define ADT7481_STATUS1_REMOTE1_OPEN		BIT(2)
-#define ADT7481_STATUS1_REMOTE1_LOW_ALARM	BIT(3)
-#define ADT7481_STATUS1_REMOTE1_HIGH_ALARM	BIT(4)
-#define ADT7481_STATUS1_LOCAL_LOW_ALARM		BIT(5)
-#define ADT7481_STATUS1_LOCAL_HIGH_ALARM	BIT(6)
-#define ADT7481_STATUS1_BUSY			BIT(7)
+#define ADT7481_STATUS1_LOCAL_THERM_ALARM BIT(0)
+#define ADT7481_STATUS1_REMOTE1_THERM_ALARM BIT(1)
+#define ADT7481_STATUS1_REMOTE1_OPEN BIT(2)
+#define ADT7481_STATUS1_REMOTE1_LOW_ALARM BIT(3)
+#define ADT7481_STATUS1_REMOTE1_HIGH_ALARM BIT(4)
+#define ADT7481_STATUS1_LOCAL_LOW_ALARM BIT(5)
+#define ADT7481_STATUS1_LOCAL_HIGH_ALARM BIT(6)
+#define ADT7481_STATUS1_BUSY BIT(7)
 
 /* Status2 register bits */
-#define ADT7481_STATUS2_ALERT			BIT(0)
-#define ADT7481_STATUS2_REMOTE2_THERM_ALARM	BIT(1)
-#define ADT7481_STATUS2_REMOTE2_OPEN		BIT(2)
-#define ADT7481_STATUS2_REMOTE2_LOW_ALARM	BIT(3)
-#define ADT7481_STATUS2_REMOTE2_HIGH_ALARM	BIT(4)
+#define ADT7481_STATUS2_ALERT BIT(0)
+#define ADT7481_STATUS2_REMOTE2_THERM_ALARM BIT(1)
+#define ADT7481_STATUS2_REMOTE2_OPEN BIT(2)
+#define ADT7481_STATUS2_REMOTE2_LOW_ALARM BIT(3)
+#define ADT7481_STATUS2_REMOTE2_HIGH_ALARM BIT(4)
 
 /* Consecutive Alert register */
-#define ADT7481_CONSEC_MASK		(0xf)
-#define ADT7481_CONSEC_1		(0x0)
-#define ADT7481_CONSEC_2		(0x2)
-#define ADT7481_CONSEC_3		(0x6)
-#define ADT7481_CONSEC_4		(0xe)
-#define ADT7481_CONSEC_EN_SCL_TIMEOUT	BIT(5)
-#define ADT7481_CONSEC_EN_SDA_TIMEOUT	BIT(6)
-#define ADT7481_CONSEC_MASK_LOCAL_ALERT	BIT(7)
-
+#define ADT7481_CONSEC_MASK (0xf)
+#define ADT7481_CONSEC_1 (0x0)
+#define ADT7481_CONSEC_2 (0x2)
+#define ADT7481_CONSEC_3 (0x6)
+#define ADT7481_CONSEC_4 (0xe)
+#define ADT7481_CONSEC_EN_SCL_TIMEOUT BIT(5)
+#define ADT7481_CONSEC_EN_SDA_TIMEOUT BIT(6)
+#define ADT7481_CONSEC_MASK_LOCAL_ALERT BIT(7)
 
 /* Limits */
-#define ADT7481_HYSTERESIS_HIGH_LIMIT	255
-#define ADT7481_HYSTERESIS_LOW_LIMIT	0
+#define ADT7481_HYSTERESIS_HIGH_LIMIT 255
+#define ADT7481_HYSTERESIS_LOW_LIMIT 0
 
 enum adt7481_power_state {
 	ADT7481_POWER_OFF = 0,
diff --git a/driver/temp_sensor/amd_r19me4070.c b/driver/temp_sensor/amd_r19me4070.c
index ec606604a5..3ee230da09 100644
--- a/driver/temp_sensor/amd_r19me4070.c
+++ b/driver/temp_sensor/amd_r19me4070.c
@@ -1,26 +1,26 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* R19ME4070 temperature sensor module for Chrome EC */
 
+#include "amd_r19me4070.h"
 #include "chipset.h"
 #include "common.h"
 #include "console.h"
 #include "hooks.h"
 #include "i2c.h"
-#include "amd_r19me4070.h"
 #include "power.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* GPU I2C address */
-#define GPU_ADDR_FLAGS                  0x0041
+#define GPU_ADDR_FLAGS 0x0041
 
-#define GPU_INIT_OFFSET                 0x01
-#define GPU_TEMPERATURE_OFFSET          0x03
+#define GPU_INIT_OFFSET 0x01
+#define GPU_TEMPERATURE_OFFSET 0x03
 
 static int initialized;
 /*
@@ -34,8 +34,8 @@ static void gpu_init_temp_sensor(void)
 {
 	int rv;
 	rv = i2c_write_block(I2C_PORT_GPU, GPU_ADDR_FLAGS, GPU_INIT_OFFSET,
-			  gpu_init_write_value,
-			  ARRAY_SIZE(gpu_init_write_value));
+			     gpu_init_write_value,
+			     ARRAY_SIZE(gpu_init_write_value));
 	if (rv == EC_SUCCESS) {
 		initialized = 1;
 		return;
@@ -53,17 +53,21 @@ int get_temp_R19ME4070(int idx, int *temp_ptr)
 	 * We shouldn't read the GPU temperature when the state
 	 * is not in S0, because GPU is enabled in S0.
 	 */
-	if ((power_get_state()) != POWER_S0)
+	if (!chipset_in_state(CHIPSET_STATE_ON)) {
+		*temp_ptr = C_TO_K(0);
 		return EC_ERROR_BUSY;
+	}
 	/* if no INIT GPU, must init it first and wait 1 sec. */
 	if (!initialized) {
 		gpu_init_temp_sensor();
+		*temp_ptr = C_TO_K(0);
 		return EC_ERROR_BUSY;
 	}
 	rv = i2c_read_block(I2C_PORT_GPU, GPU_ADDR_FLAGS,
-			GPU_TEMPERATURE_OFFSET, reg, ARRAY_SIZE(reg));
+			    GPU_TEMPERATURE_OFFSET, reg, ARRAY_SIZE(reg));
 	if (rv) {
 		CPRINTS("read GPU Temperature fail");
+		*temp_ptr = C_TO_K(0);
 		return rv;
 	}
 	/*
@@ -81,5 +85,6 @@ int get_temp_R19ME4070(int idx, int *temp_ptr)
 	 * reg[0] = 0x04
 	 */
 	*temp_ptr = C_TO_K(reg[3] >> 1);
+
 	return EC_SUCCESS;
 }
diff --git a/driver/temp_sensor/amd_r19me4070.h b/driver/temp_sensor/amd_r19me4070.h
index d3c7977ba5..5460dcb1cc 100644
--- a/driver/temp_sensor/amd_r19me4070.h
+++ b/driver/temp_sensor/amd_r19me4070.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,7 +9,7 @@
 #define __CROS_EC_R19ME4070_H
 
 /* GPU features */
-#define R19ME4070_LOCAL                 0
+#define R19ME4070_LOCAL 0
 
 /*
  * get GPU temperature value and move to *tem_ptr
diff --git a/driver/temp_sensor/bd99992gw.c b/driver/temp_sensor/bd99992gw.c
index 0fc8f094b4..bd152c0441 100644
--- a/driver/temp_sensor/bd99992gw.c
+++ b/driver/temp_sensor/bd99992gw.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,6 +10,7 @@
  */
 
 #include "bd99992gw.h"
+#include "builtin/assert.h"
 #include "chipset.h"
 #include "common.h"
 #include "console.h"
@@ -17,13 +18,13 @@
 #include "hooks.h"
 #include "i2c.h"
 #include "temp_sensor.h"
-#include "thermistor.h"
+#include "temp_sensor/thermistor.h"
 #include "timer.h"
 #include "util.h"
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_THERMAL, outstr)
-#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
 
 /* List of active channels, ordered by pointer register */
 static enum bd99992gw_adc_channel
@@ -39,8 +40,8 @@ static enum bd99992gw_adc_channel
 static int raw_read8(const int offset, int *data_ptr)
 {
 	int ret;
-	ret = i2c_read8(I2C_PORT_THERMAL, BD99992GW_I2C_ADDR_FLAGS,
-			offset, data_ptr);
+	ret = i2c_read8(I2C_PORT_THERMAL, BD99992GW_I2C_ADDR_FLAGS, offset,
+			data_ptr);
 	if (ret != EC_SUCCESS)
 		CPRINTS("bd99992gw read fail %d", ret);
 	return ret;
@@ -49,8 +50,8 @@ static int raw_read8(const int offset, int *data_ptr)
 static int raw_write8(const int offset, int data)
 {
 	int ret;
-	ret = i2c_write8(I2C_PORT_THERMAL, BD99992GW_I2C_ADDR_FLAGS,
-			 offset, data);
+	ret = i2c_write8(I2C_PORT_THERMAL, BD99992GW_I2C_ADDR_FLAGS, offset,
+			 data);
 	if (ret != EC_SUCCESS)
 		CPRINTS("bd99992gw write fail %d", ret);
 	return ret;
@@ -79,9 +80,11 @@ static void bd99992gw_init(void)
 	/* Now write pointer regs with channel to monitor */
 	for (i = 0; i < active_channel_count; ++i)
 		/* Write stop bit on last channel */
-		if (raw_write8(pointer_reg + i, active_channels[i] |
-			  ((i == active_channel_count - 1) ?
-			  BD99992GW_ADC1ADDR_STOP : 0)))
+		if (raw_write8(pointer_reg + i,
+			       active_channels[i] |
+				       ((i == active_channel_count - 1) ?
+						BD99992GW_ADC1ADDR_STOP :
+						0)))
 			return;
 
 	/* Enable ADC interrupts */
@@ -96,7 +99,8 @@ static void bd99992gw_init(void)
 
 	/* Start round-robin conversions at 27ms period */
 	raw_write8(BD99992GW_REG_ADC1CNTL1, ADC_LOOP_PERIOD |
-		   BD99992GW_ADC1CNTL1_ADEN | BD99992GW_ADC1CNTL1_ADSTRT);
+						    BD99992GW_ADC1CNTL1_ADEN |
+						    BD99992GW_ADC1CNTL1_ADSTRT);
 }
 /*
  * Some regs only work in S0, so we must initialize on AP startup in
@@ -130,24 +134,20 @@ int bd99992gw_get_val(int idx, int *temp_ptr)
 	/* Find requested channel */
 	for (i = 0; i < ARRAY_SIZE(active_channels); ++i) {
 		channel = active_channels[i];
-		if (channel == idx ||
-		    channel == BD99992GW_ADC_CHANNEL_NONE)
+		if (channel == idx || channel == BD99992GW_ADC_CHANNEL_NONE)
 			break;
 	}
 
 	/* Make sure we found it */
-	if (i == ARRAY_SIZE(active_channels) ||
-	    active_channels[i] != idx) {
+	if (i == ARRAY_SIZE(active_channels) || active_channels[i] != idx) {
 		CPRINTS("Bad ADC channel %d", idx);
 		return EC_ERROR_INVAL;
 	}
 
 	/* Pause conversions */
-	ret = raw_write8(0x80,
-			 ADC_LOOP_PERIOD |
-			 BD99992GW_ADC1CNTL1_ADEN |
-			 BD99992GW_ADC1CNTL1_ADSTRT |
-			 BD99992GW_ADC1CNTL1_ADPAUSE);
+	ret = raw_write8(0x80, ADC_LOOP_PERIOD | BD99992GW_ADC1CNTL1_ADEN |
+				       BD99992GW_ADC1CNTL1_ADSTRT |
+				       BD99992GW_ADC1CNTL1_ADPAUSE);
 	if (ret)
 		return ret;
 
@@ -173,8 +173,9 @@ int bd99992gw_get_val(int idx, int *temp_ptr)
 		return ret;
 
 	/* Resume conversions */
-	ret = raw_write8(BD99992GW_REG_ADC1CNTL1, ADC_LOOP_PERIOD |
-		   BD99992GW_ADC1CNTL1_ADEN | BD99992GW_ADC1CNTL1_ADSTRT);
+	ret = raw_write8(BD99992GW_REG_ADC1CNTL1,
+			 ADC_LOOP_PERIOD | BD99992GW_ADC1CNTL1_ADEN |
+				 BD99992GW_ADC1CNTL1_ADSTRT);
 	if (ret)
 		return ret;
 
diff --git a/driver/temp_sensor/bd99992gw.h b/driver/temp_sensor/bd99992gw.h
index c461012c45..8ee2c2774c 100644
--- a/driver/temp_sensor/bd99992gw.h
+++ b/driver/temp_sensor/bd99992gw.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,74 +8,74 @@
 #ifndef __CROS_EC_TEMP_SENSOR_BD99992GW_H
 #define __CROS_EC_TEMP_SENSOR_BD99992GW_H
 
-#define BD99992GW_I2C_ADDR_FLAGS	0x30
+#define BD99992GW_I2C_ADDR_FLAGS 0x30
 
 /* ADC channels */
 enum bd99992gw_adc_channel {
-	BD99992GW_ADC_CHANNEL_NONE      = -1,
-	BD99992GW_ADC_CHANNEL_BATTERY   = 0,
-	BD99992GW_ADC_CHANNEL_AC        = 1,
+	BD99992GW_ADC_CHANNEL_NONE = -1,
+	BD99992GW_ADC_CHANNEL_BATTERY = 0,
+	BD99992GW_ADC_CHANNEL_AC = 1,
 	BD99992GW_ADC_CHANNEL_SYSTHERM0 = 2,
 	BD99992GW_ADC_CHANNEL_SYSTHERM1 = 3,
 	BD99992GW_ADC_CHANNEL_SYSTHERM2 = 4,
 	BD99992GW_ADC_CHANNEL_SYSTHERM3 = 5,
-	BD99992GW_ADC_CHANNEL_DIE_TEMP  = 6,
-	BD99992GW_ADC_CHANNEL_VDC       = 7,
-	BD99992GW_ADC_CHANNEL_COUNT     = 8,
+	BD99992GW_ADC_CHANNEL_DIE_TEMP = 6,
+	BD99992GW_ADC_CHANNEL_VDC = 7,
+	BD99992GW_ADC_CHANNEL_COUNT = 8,
 };
 
 /* Registers */
-#define BD99992GW_REG_IRQLVL1		0x02
-#define BD99992GW_IRQLVL1_ADC		 BIT(1) /* ADC IRQ asserted */
+#define BD99992GW_REG_IRQLVL1 0x02
+#define BD99992GW_IRQLVL1_ADC BIT(1) /* ADC IRQ asserted */
 
-#define BD99992GW_REG_ADC1INT		0x03
-#define BD99992GW_ADC1INT_RND		 BIT(0) /* RR cycle completed */
+#define BD99992GW_REG_ADC1INT 0x03
+#define BD99992GW_ADC1INT_RND BIT(0) /* RR cycle completed */
 
-#define BD99992GW_REG_MADC1INT		0x0a
-#define BD99992GW_MADC1INT_RND		 BIT(0) /* RR cycle mask */
+#define BD99992GW_REG_MADC1INT 0x0a
+#define BD99992GW_MADC1INT_RND BIT(0) /* RR cycle mask */
 
-#define BD99992GW_REG_IRQLVL1MSK	0x13
-#define BD99992GW_IRQLVL1MSK_MADC	 BIT(1) /* ADC IRQ mask */
+#define BD99992GW_REG_IRQLVL1MSK 0x13
+#define BD99992GW_IRQLVL1MSK_MADC BIT(1) /* ADC IRQ mask */
 
-#define BD99992GW_REG_ADC1CNTL1		0x80
-#define BD99992GW_ADC1CNTL1_SLP27MS	 (0x6 << 3) /* 27ms between pass */
-#define BD99992GW_ADC1CNTL1_NOLOOP	 (0x7 << 3) /* Single loop pass only */
-#define BD99992GW_ADC1CNTL1_ADPAUSE	 BIT(2)   /* ADC pause */
-#define BD99992GW_ADC1CNTL1_ADSTRT	 BIT(1)   /* ADC start */
-#define BD99992GW_ADC1CNTL1_ADEN	 BIT(0)   /* ADC enable */
+#define BD99992GW_REG_ADC1CNTL1 0x80
+#define BD99992GW_ADC1CNTL1_SLP27MS (0x6 << 3) /* 27ms between pass */
+#define BD99992GW_ADC1CNTL1_NOLOOP (0x7 << 3) /* Single loop pass only */
+#define BD99992GW_ADC1CNTL1_ADPAUSE BIT(2) /* ADC pause */
+#define BD99992GW_ADC1CNTL1_ADSTRT BIT(1) /* ADC start */
+#define BD99992GW_ADC1CNTL1_ADEN BIT(0) /* ADC enable */
 
-#define BD99992GW_REG_ADC1CNTL2		0x81
-#define BD99992GW_ADC1CNTL2_ADCTHERM	 BIT(0) /* Enable ADC sequencing */
+#define BD99992GW_REG_ADC1CNTL2 0x81
+#define BD99992GW_ADC1CNTL2_ADCTHERM BIT(0) /* Enable ADC sequencing */
 
- /* ADC1 Pointer file regs - assign to proper bd99992gw_adc_channel */
-#define BD99992GW_ADC_POINTER_REG_COUNT	8
-#define BD99992GW_REG_ADC1ADDR0		0x82
-#define BD99992GW_REG_ADC1ADDR1		0x83
-#define BD99992GW_REG_ADC1ADDR2		0x84
-#define BD99992GW_REG_ADC1ADDR3		0x85
-#define BD99992GW_REG_ADC1ADDR4		0x86
-#define BD99992GW_REG_ADC1ADDR5		0x87
-#define BD99992GW_REG_ADC1ADDR6		0x88
-#define BD99992GW_REG_ADC1ADDR7		0x89
-#define BD99992GW_ADC1ADDR_STOP		 BIT(3) /* Last conversion channel */
+/* ADC1 Pointer file regs - assign to proper bd99992gw_adc_channel */
+#define BD99992GW_ADC_POINTER_REG_COUNT 8
+#define BD99992GW_REG_ADC1ADDR0 0x82
+#define BD99992GW_REG_ADC1ADDR1 0x83
+#define BD99992GW_REG_ADC1ADDR2 0x84
+#define BD99992GW_REG_ADC1ADDR3 0x85
+#define BD99992GW_REG_ADC1ADDR4 0x86
+#define BD99992GW_REG_ADC1ADDR5 0x87
+#define BD99992GW_REG_ADC1ADDR6 0x88
+#define BD99992GW_REG_ADC1ADDR7 0x89
+#define BD99992GW_ADC1ADDR_STOP BIT(3) /* Last conversion channel */
 
 /* Result registers */
-#define BD99992GW_REG_ADC1DATA0L	0x95
-#define BD99992GW_REG_ADC1DATA0H	0x96
-#define BD99992GW_REG_ADC1DATA1L	0x97
-#define BD99992GW_REG_ADC1DATA1H	0x98
-#define BD99992GW_REG_ADC1DATA2L	0x99
-#define BD99992GW_REG_ADC1DATA2H	0x9a
-#define BD99992GW_REG_ADC1DATA3L	0x9b
-#define BD99992GW_REG_ADC1DATA3H	0x9c
-#define BD99992GW_REG_ADC1DATA4L	0x9d
-#define BD99992GW_REG_ADC1DATA4H	0x9e
-#define BD99992GW_REG_ADC1DATA5L	0x9f
-#define BD99992GW_REG_ADC1DATA5H	0xa0
-#define BD99992GW_REG_ADC1DATA6L	0xa1
-#define BD99992GW_REG_ADC1DATA6H	0xa2
-#define BD99992GW_REG_ADC1DATA7L	0xa3
-#define BD99992GW_REG_ADC1DATA7H	0xa4
+#define BD99992GW_REG_ADC1DATA0L 0x95
+#define BD99992GW_REG_ADC1DATA0H 0x96
+#define BD99992GW_REG_ADC1DATA1L 0x97
+#define BD99992GW_REG_ADC1DATA1H 0x98
+#define BD99992GW_REG_ADC1DATA2L 0x99
+#define BD99992GW_REG_ADC1DATA2H 0x9a
+#define BD99992GW_REG_ADC1DATA3L 0x9b
+#define BD99992GW_REG_ADC1DATA3H 0x9c
+#define BD99992GW_REG_ADC1DATA4L 0x9d
+#define BD99992GW_REG_ADC1DATA4H 0x9e
+#define BD99992GW_REG_ADC1DATA5L 0x9f
+#define BD99992GW_REG_ADC1DATA5H 0xa0
+#define BD99992GW_REG_ADC1DATA6L 0xa1
+#define BD99992GW_REG_ADC1DATA6H 0xa2
+#define BD99992GW_REG_ADC1DATA7L 0xa3
+#define BD99992GW_REG_ADC1DATA7H 0xa4
 
 /**
  * Get the latest value from the sensor.
@@ -87,4 +87,4 @@ enum bd99992gw_adc_channel {
  */
 int bd99992gw_get_val(int idx, int *temp_ptr);
 
-#endif  /* __CROS_EC_TEMP_SENSOR_BD99992GW_H */
+#endif /* __CROS_EC_TEMP_SENSOR_BD99992GW_H */
diff --git a/driver/temp_sensor/ec_adc.c b/driver/temp_sensor/ec_adc.c
index db174e33dc..ca03cd6c6d 100644
--- a/driver/temp_sensor/ec_adc.c
+++ b/driver/temp_sensor/ec_adc.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,7 +9,7 @@
 #include "common.h"
 #include "console.h"
 #include "ec_adc.h"
-#include "thermistor.h"
+#include "temp_sensor/thermistor.h"
 #include "util.h"
 
 /* Get temperature from requested sensor */
@@ -23,15 +23,15 @@ static int get_temp(int idx, int *temp_ptr)
 	if (temp_raw == ADC_READ_ERROR)
 		return EC_ERROR_UNKNOWN;
 
-	/* TODO : Need modification here if the result is not 10-bit */
+		/* TODO : Need modification here if the result is not 10-bit */
 
-	/* If there is no thermistor calculation function.
-	 *  1. Add adjusting function like thermistor_ncp15wb.c
-	 *  2. Place function here with ifdef
-	 *  3. define it on board.h
-	 */
+		/* If there is no thermistor calculation function.
+		 *  1. Add adjusting function like thermistor_ncp15wb.c
+		 *  2. Place function here with ifdef
+		 *  3. define it on board.h
+		 */
 #ifdef CONFIG_THERMISTOR_NCP15WB
-	*temp_ptr = ncp15wb_calculate_temp((uint16_t) temp_raw);
+	*temp_ptr = ncp15wb_calculate_temp((uint16_t)temp_raw);
 #else
 #error "Unknown thermistor for ec_adc"
 	return EC_ERROR_UNKNOWN;
@@ -45,7 +45,7 @@ int ec_adc_get_val(int idx, int *temp_ptr)
 	int ret;
 	int temp_c;
 
-	if(idx < 0 || idx >= ADC_CH_COUNT)
+	if (idx < 0 || idx >= ADC_CH_COUNT)
 		return EC_ERROR_INVAL;
 
 	ret = get_temp(idx, &temp_c);
diff --git a/driver/temp_sensor/ec_adc.h b/driver/temp_sensor/ec_adc.h
index 8ff213e95d..3bea83ffe8 100644
--- a/driver/temp_sensor/ec_adc.h
+++ b/driver/temp_sensor/ec_adc.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,4 +21,4 @@
  */
 int ec_adc_get_val(int idx, int *temp_ptr);
 
-#endif  /* __CROS_EC_TEMP_SENSOR_EC_ADC_H */
+#endif /* __CROS_EC_TEMP_SENSOR_EC_ADC_H */
diff --git a/driver/temp_sensor/f75303.c b/driver/temp_sensor/f75303.c
index 6b8895a252..cffbddad9b 100644
--- a/driver/temp_sensor/f75303.c
+++ b/driver/temp_sensor/f75303.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,24 +6,44 @@
 /* F75303 temperature sensor module for Chrome EC */
 
 #include "common.h"
-#include "f75303.h"
-#include "i2c.h"
+#include "console.h"
 #include "hooks.h"
+#include "i2c.h"
+#include "math_util.h"
+#include "temp_sensor/f75303.h"
 #include "util.h"
-#include "console.h"
+
+#ifdef CONFIG_ZEPHYR
+#include "temp_sensor/temp_sensor.h"
+#endif
+
+#define F75303_RESOLUTION 11
+#define F75303_SHIFT1 (16 - F75303_RESOLUTION)
+#define F75303_SHIFT2 (F75303_RESOLUTION - 8)
 
 static int temps[F75303_IDX_COUNT];
-static int8_t fake_temp[F75303_IDX_COUNT] = {-1, -1, -1};
+static int8_t fake_temp[F75303_IDX_COUNT];
 
+#ifndef CONFIG_ZEPHYR
 /**
  * Read 8 bits register from temp sensor.
  */
 static int raw_read8(const int offset, int *data)
 {
-	return i2c_read8(I2C_PORT_THERMAL, F75303_I2C_ADDR_FLAGS,
-			 offset, data);
+	return i2c_read8(I2C_PORT_THERMAL, F75303_I2C_ADDR_FLAGS, offset, data);
 }
+#else
+/**
+ * Read 8 bits register from temp sensor.
+ */
+static int raw_read8(int sensor, const int offset, int *data)
+{
+	return i2c_read8(f75303_sensors[sensor].i2c_port,
+			 f75303_sensors[sensor].i2c_addr_flags, offset, data);
+}
+#endif /* !CONFIG_ZEPHYR */
 
+#ifndef CONFIG_ZEPHYR
 static int get_temp(const int offset, int *temp)
 {
 	int rv;
@@ -36,6 +56,20 @@ static int get_temp(const int offset, int *temp)
 	*temp = C_TO_K(temp_raw);
 	return EC_SUCCESS;
 }
+#else
+static int get_temp(int sensor, const int offset, int *temp)
+{
+	int rv;
+	int temp_raw = 0;
+
+	rv = raw_read8(sensor, offset, &temp_raw);
+	if (rv != 0)
+		return rv;
+
+	*temp = CELSIUS_TO_MILLI_KELVIN(temp_raw);
+	return EC_SUCCESS;
+}
+#endif /* !CONFIG_ZEPHYR */
 
 int f75303_get_val(int idx, int *temp)
 {
@@ -51,15 +85,69 @@ int f75303_get_val(int idx, int *temp)
 	return EC_SUCCESS;
 }
 
+static inline int f75303_reg_to_mk(int16_t reg)
+{
+	int temp_mc;
+
+	temp_mc = (((reg >> F75303_SHIFT1) * 1000) >> F75303_SHIFT2);
+
+	return MILLI_CELSIUS_TO_MILLI_KELVIN(temp_mc);
+}
+
+int f75303_get_val_k(int idx, int *temp_k_ptr)
+{
+	if (idx >= F75303_IDX_COUNT)
+		return EC_ERROR_INVAL;
+
+	*temp_k_ptr = MILLI_KELVIN_TO_KELVIN(temps[idx]);
+	return EC_SUCCESS;
+}
+
+int f75303_get_val_mk(int idx, int *temp_mk_ptr)
+{
+	if (idx >= F75303_IDX_COUNT)
+		return EC_ERROR_INVAL;
+
+	*temp_mk_ptr = temps[idx];
+	return EC_SUCCESS;
+}
+
+#ifndef CONFIG_ZEPHYR
 static void f75303_sensor_poll(void)
 {
-	get_temp(F75303_TEMP_LOCAL, &temps[F75303_IDX_LOCAL]);
-	get_temp(F75303_TEMP_REMOTE1, &temps[F75303_IDX_REMOTE1]);
-	get_temp(F75303_TEMP_REMOTE2, &temps[F75303_IDX_REMOTE2]);
+	get_temp(F75303_TEMP_LOCAL_REGISTER, &temps[F75303_IDX_LOCAL]);
+	get_temp(F75303_TEMP_REMOTE1_REGISTER, &temps[F75303_IDX_REMOTE1]);
+	get_temp(F75303_TEMP_REMOTE2_REGISTER, &temps[F75303_IDX_REMOTE2]);
 }
 DECLARE_HOOK(HOOK_SECOND, f75303_sensor_poll, HOOK_PRIO_TEMP_SENSOR);
+#else
+void f75303_update_temperature(int idx)
+{
+	int temp_reg = 0;
+	int rv = EC_ERROR_INVAL;
+
+	if (idx >= F75303_IDX_COUNT)
+		return;
+	switch (idx) {
+	case F75303_IDX_LOCAL:
+		rv = get_temp(idx, F75303_TEMP_LOCAL_REGISTER, &temp_reg);
+		break;
+	case F75303_IDX_REMOTE1:
+		rv = get_temp(idx, F75303_TEMP_REMOTE1_REGISTER, &temp_reg);
+		break;
+	case F75303_IDX_REMOTE2:
+		rv = get_temp(idx, F75303_TEMP_REMOTE2_REGISTER, &temp_reg);
+		break;
+	}
+	if (rv == EC_SUCCESS)
+		temps[idx] = temp_reg;
 
-static int f75303_set_fake_temp(int argc, char **argv)
+	if (fake_temp[idx] != -1)
+		temps[idx] = KELVIN_TO_MILLI_KELVIN(C_TO_K(fake_temp[idx]));
+}
+#endif /* CONFIG_ZEPHYR */
+
+static int f75303_set_fake_temp(int argc, const char **argv)
 {
 	int index;
 	int value;
@@ -88,6 +176,14 @@ static int f75303_set_fake_temp(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(f75303, f75303_set_fake_temp,
-		"<index> <value>|off",
-		"Set fake temperature of sensor f75303.");
+DECLARE_CONSOLE_COMMAND(f75303, f75303_set_fake_temp, "<index> <value>|off",
+			"Set fake temperature of sensor f75303.");
+
+static void f75303_init(void)
+{
+	int index;
+
+	for (index = 0; index < F75303_IDX_COUNT; index++)
+		fake_temp[index] = -1;
+}
+DECLARE_HOOK(HOOK_INIT, f75303_init, HOOK_PRIO_TEMP_SENSOR);
diff --git a/driver/temp_sensor/f75303.h b/driver/temp_sensor/f75303.h
deleted file mode 100644
index bdfd2624f0..0000000000
--- a/driver/temp_sensor/f75303.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* F75303 temperature sensor module for Chrome EC */
-
-#ifndef __CROS_EC_F75303_H
-#define __CROS_EC_F75303_H
-
-#ifdef BOARD_MUSHU
-#define F75303_I2C_ADDR_FLAGS		0x4D
-#else
-#define F75303_I2C_ADDR_FLAGS		0x4C
-#endif
-
-enum f75303_index {
-	F75303_IDX_LOCAL = 0,
-	F75303_IDX_REMOTE1,
-	F75303_IDX_REMOTE2,
-	F75303_IDX_COUNT,
-};
-
-/* F75303 register */
-#define F75303_TEMP_LOCAL		0x00
-#define F75303_TEMP_REMOTE1		0x01
-#define F75303_TEMP_REMOTE2		0x23
-
-/**
- * Get the last polled value of a sensor.
- *
- * @param idx	Index to read. Idx indicates whether to read die
- *		temperature or external temperature.
- * @param temp	Destination for temperature in K.
- *
- * @return EC_SUCCESS if successful, non-zero if error.
- */
-int f75303_get_val(int idx, int *temp);
-
-#endif  /* __CROS_EC_F75303_H */
diff --git a/driver/temp_sensor/g753.c b/driver/temp_sensor/g753.c
index 857263c161..f162cbf846 100644
--- a/driver/temp_sensor/g753.c
+++ b/driver/temp_sensor/g753.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,8 +9,8 @@
 #include "console.h"
 #include "g753.h"
 #include "gpio.h"
-#include "i2c.h"
 #include "hooks.h"
+#include "i2c.h"
 #include "util.h"
 
 static int temp_val_local;
@@ -22,8 +22,8 @@ static int temp_val_local;
  */
 static int has_power(void)
 {
-#ifdef CONFIG_TEMP_SENSOR_POWER_GPIO
-	return gpio_get_level(CONFIG_TEMP_SENSOR_POWER_GPIO);
+#ifdef CONFIG_TEMP_SENSOR_POWER
+	return gpio_get_level(GPIO_TEMP_SENSOR_POWER);
 #else
 	return 1;
 #endif
@@ -31,15 +31,14 @@ static int has_power(void)
 
 static int raw_read8(const int offset, int *data_ptr)
 {
-	return i2c_read8(I2C_PORT_THERMAL, G753_I2C_ADDR_FLAGS,
-			 offset, data_ptr);
+	return i2c_read8(I2C_PORT_THERMAL, G753_I2C_ADDR_FLAGS, offset,
+			 data_ptr);
 }
 
 #ifdef CONFIG_CMD_TEMP_SENSOR
 static int raw_write8(const int offset, int data)
 {
-	return i2c_write8(I2C_PORT_THERMAL, G753_I2C_ADDR_FLAGS,
-			  offset, data);
+	return i2c_write8(I2C_PORT_THERMAL, G753_I2C_ADDR_FLAGS, offset, data);
 }
 #endif
 
@@ -93,8 +92,7 @@ static void temp_sensor_poll(void)
 DECLARE_HOOK(HOOK_SECOND, temp_sensor_poll, HOOK_PRIO_TEMP_SENSOR);
 
 #ifdef CONFIG_CMD_TEMP_SENSOR
-static void print_temps(const char *name,
-			const int temp_reg,
+static void print_temps(const char *name, const int temp_reg,
 			const int high_limit_reg)
 {
 	int value;
@@ -106,7 +104,6 @@ static void print_temps(const char *name,
 
 	if (get_temp(high_limit_reg, &value) == EC_SUCCESS)
 		ccprintf("  High Alarm: %3dC\n", value);
-
 }
 
 static int print_status(void)
@@ -118,23 +115,22 @@ static int print_status(void)
 		return EC_ERROR_NOT_POWERED;
 	}
 
-	print_temps("Local", G753_TEMP_LOCAL,
-		    G753_LOCAL_TEMP_HIGH_LIMIT_R);
+	print_temps("Local", G753_TEMP_LOCAL, G753_LOCAL_TEMP_HIGH_LIMIT_R);
 
 	ccprintf("\n");
 
 	if (raw_read8(G753_STATUS, &value) == EC_SUCCESS)
-		ccprintf("STATUS:  %pb\n", BINARY_VALUE(value, 8));
+		ccprintf("STATUS:  0x%x\n", value);
 
 	if (raw_read8(G753_CONFIGURATION_R, &value) == EC_SUCCESS)
-		ccprintf("CONFIG:  %pb\n", BINARY_VALUE(value, 8));
+		ccprintf("CONFIG:  0x%x\n", value);
 
 	return EC_SUCCESS;
 }
 
-static int command_g753(int argc, char **argv)
+static int command_g753(int argc, const char **argv)
 {
-	char *command;
+	const char *command;
 	char *e;
 	int data;
 	int offset;
@@ -161,8 +157,7 @@ static int command_g753(int argc, char **argv)
 		rv = raw_read8(offset, &data);
 		if (rv < 0)
 			return rv;
-		ccprintf("Byte at offset 0x%02x is %pb\n",
-			 offset, BINARY_VALUE(data, 8));
+		ccprintf("Byte at offset 0x%02x is 0x%x\n", offset, data);
 		return rv;
 	}
 
@@ -185,7 +180,8 @@ static int command_g753(int argc, char **argv)
 
 	return rv;
 }
-DECLARE_CONSOLE_COMMAND(g753, command_g753,
+DECLARE_CONSOLE_COMMAND(
+	g753, command_g753,
 	"[settemp|setbyte <offset> <value>] or [getbyte <offset>]. "
 	"Temps in Celsius.",
 	"Print g753 temp sensor status or set parameters.");
diff --git a/driver/temp_sensor/g753.h b/driver/temp_sensor/g753.h
index 04c412bfbb..00f7fec8ac 100644
--- a/driver/temp_sensor/g753.h
+++ b/driver/temp_sensor/g753.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,36 +8,35 @@
 #ifndef __CROS_EC_G753_H
 #define __CROS_EC_G753_H
 
+#define G753_I2C_ADDR_FLAGS 0x48
 
-#define G753_I2C_ADDR_FLAGS			0x48
-
-#define G753_IDX_INTERNAL	0
+#define G753_IDX_INTERNAL 0
 
 /* G753 register */
-#define G753_TEMP_LOCAL				0x00
-#define G753_STATUS				0x02
-#define G753_CONFIGURATION_R			0x03
-#define G753_CONVERSION_RATE_R			0x04
-#define G753_LOCAL_TEMP_HIGH_LIMIT_R		0x05
-#define G753_CONFIGURATION_W			0x09
-#define G753_CONVERSION_RATE_W			0x0A
-#define G753_LOCAL_TEMP_HIGH_LIMIT_W		0x0B
-#define G753_ONESHOT				0x0F
-#define G753_Customer_Data_Log_Register_1	0x2D
-#define G753_Customer_Data_Log_Register_2	0x2E
-#define G753_Customer_Data_Log_Register_3	0x2F
-#define G753_ALERT_MODE				0xBF
-#define G753_CHIP_ID				0xFD
-#define G753_VENDOR_ID				0xFE
-#define G753_DEVICE_ID				0xFF
+#define G753_TEMP_LOCAL 0x00
+#define G753_STATUS 0x02
+#define G753_CONFIGURATION_R 0x03
+#define G753_CONVERSION_RATE_R 0x04
+#define G753_LOCAL_TEMP_HIGH_LIMIT_R 0x05
+#define G753_CONFIGURATION_W 0x09
+#define G753_CONVERSION_RATE_W 0x0A
+#define G753_LOCAL_TEMP_HIGH_LIMIT_W 0x0B
+#define G753_ONESHOT 0x0F
+#define G753_Customer_Data_Log_Register_1 0x2D
+#define G753_Customer_Data_Log_Register_2 0x2E
+#define G753_Customer_Data_Log_Register_3 0x2F
+#define G753_ALERT_MODE 0xBF
+#define G753_CHIP_ID 0xFD
+#define G753_VENDOR_ID 0xFE
+#define G753_DEVICE_ID 0xFF
 
 /* Config register bits */
-#define G753_CONFIGURATION_STANDBY		BIT(6)
-#define G753_CONFIGURATION_ALERT_MASK		BIT(7)
+#define G753_CONFIGURATION_STANDBY BIT(6)
+#define G753_CONFIGURATION_ALERT_MASK BIT(7)
 
 /* Status register bits */
-#define G753_STATUS_LOCAL_TEMP_HIGH_ALARM	BIT(6)
-#define G753_STATUS_BUSY			BIT(7)
+#define G753_STATUS_LOCAL_TEMP_HIGH_ALARM BIT(6)
+#define G753_STATUS_BUSY BIT(7)
 
 /**
  * Get the last polled value of a sensor.
@@ -50,4 +49,4 @@
  */
 int g753_get_val(int idx, int *temp_ptr);
 
-#endif  /* __CROS_EC_G753_H */
+#endif /* __CROS_EC_G753_H */
diff --git a/driver/temp_sensor/g78x.c b/driver/temp_sensor/g78x.c
index aef13d3d68..413e2dda8a 100644
--- a/driver/temp_sensor/g78x.c
+++ b/driver/temp_sensor/g78x.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,8 +9,8 @@
 #include "console.h"
 #include "g78x.h"
 #include "gpio.h"
-#include "i2c.h"
 #include "hooks.h"
+#include "i2c.h"
 #include "util.h"
 
 static int temp_val_local;
@@ -26,8 +26,8 @@ static int temp_val_remote2;
  */
 static int has_power(void)
 {
-#ifdef CONFIG_TEMP_SENSOR_POWER_GPIO
-	return gpio_get_level(CONFIG_TEMP_SENSOR_POWER_GPIO);
+#ifdef CONFIG_TEMP_SENSOR_POWER
+	return gpio_get_level(GPIO_TEMP_SENSOR_POWER);
 #else
 	return 1;
 #endif
@@ -35,15 +35,14 @@ static int has_power(void)
 
 static int raw_read8(const int offset, int *data_ptr)
 {
-	return i2c_read8(I2C_PORT_THERMAL, G78X_I2C_ADDR_FLAGS,
-			 offset, data_ptr);
+	return i2c_read8(I2C_PORT_THERMAL, G78X_I2C_ADDR_FLAGS, offset,
+			 data_ptr);
 }
 
 #ifdef CONFIG_CMD_TEMP_SENSOR
 static int raw_write8(const int offset, int data)
 {
-	return i2c_write8(I2C_PORT_THERMAL, G78X_I2C_ADDR_FLAGS,
-			  offset, data);
+	return i2c_write8(I2C_PORT_THERMAL, G78X_I2C_ADDR_FLAGS, offset, data);
 }
 #endif
 
@@ -113,10 +112,8 @@ static void temp_sensor_poll(void)
 DECLARE_HOOK(HOOK_SECOND, temp_sensor_poll, HOOK_PRIO_TEMP_SENSOR);
 
 #ifdef CONFIG_CMD_TEMP_SENSOR
-static void print_temps(const char *name,
-			const int temp_reg,
-			const int therm_limit_reg,
-			const int high_limit_reg,
+static void print_temps(const char *name, const int temp_reg,
+			const int therm_limit_reg, const int high_limit_reg,
 			const int low_limit_reg)
 {
 	int value;
@@ -145,19 +142,15 @@ static int print_status(void)
 		return EC_ERROR_NOT_POWERED;
 	}
 
-	print_temps("Local", G78X_TEMP_LOCAL,
-		    G78X_LOCAL_TEMP_THERM_LIMIT,
-		    G78X_LOCAL_TEMP_HIGH_LIMIT_R,
-		    G78X_LOCAL_TEMP_LOW_LIMIT_R);
+	print_temps("Local", G78X_TEMP_LOCAL, G78X_LOCAL_TEMP_THERM_LIMIT,
+		    G78X_LOCAL_TEMP_HIGH_LIMIT_R, G78X_LOCAL_TEMP_LOW_LIMIT_R);
 
-	print_temps("Remote1", G78X_TEMP_REMOTE1,
-		    G78X_REMOTE1_TEMP_THERM_LIMIT,
+	print_temps("Remote1", G78X_TEMP_REMOTE1, G78X_REMOTE1_TEMP_THERM_LIMIT,
 		    G78X_REMOTE1_TEMP_HIGH_LIMIT_R,
 		    G78X_REMOTE1_TEMP_LOW_LIMIT_R);
 
 #ifdef CONFIG_TEMP_SENSOR_G782
-	print_temps("Remote2", G78X_TEMP_REMOTE1,
-		    G78X_REMOTE2_TEMP_THERM_LIMIT,
+	print_temps("Remote2", G78X_TEMP_REMOTE1, G78X_REMOTE2_TEMP_THERM_LIMIT,
 		    G78X_REMOTE2_TEMP_HIGH_LIMIT_R,
 		    G78X_REMOTE2_TEMP_LOW_LIMIT_R);
 #endif
@@ -165,20 +158,20 @@ static int print_status(void)
 	ccprintf("\n");
 
 	if (raw_read8(G78X_STATUS, &value) == EC_SUCCESS)
-		ccprintf("STATUS:  %pb\n", BINARY_VALUE(value, 8));
+		ccprintf("STATUS:  0x%x\n", value);
 
 #ifdef CONFIG_TEMP_SENSOR_G782
 	if (raw_read8(G78X_STATUS1, &value) == EC_SUCCESS)
-		ccprintf("STATUS1: %pb\n", BINARY_VALUE(value, 8));
+		ccprintf("STATUS1: 0x%x\n", value);
 #endif
 
 	if (raw_read8(G78X_CONFIGURATION_R, &value) == EC_SUCCESS)
-		ccprintf("CONFIG:  %pb\n", BINARY_VALUE(value, 8));
+		ccprintf("CONFIG:  0x%x\n", value);
 
 	return EC_SUCCESS;
 }
 
-static int command_g78x(int argc, char **argv)
+static int command_g78x(int argc, const char **argv)
 {
 	char *command;
 	char *e;
@@ -207,8 +200,7 @@ static int command_g78x(int argc, char **argv)
 		rv = raw_read8(offset, &data);
 		if (rv < 0)
 			return rv;
-		ccprintf("Byte at offset 0x%02x is %pb\n",
-			 offset, BINARY_VALUE(data, 8));
+		ccprintf("Byte at offset 0x%02x is 0x%x\n", offset, data);
 		return rv;
 	}
 
@@ -231,7 +223,8 @@ static int command_g78x(int argc, char **argv)
 
 	return rv;
 }
-DECLARE_CONSOLE_COMMAND(g78x, command_g78x,
+DECLARE_CONSOLE_COMMAND(
+	g78x, command_g78x,
 	"[settemp|setbyte <offset> <value>] or [getbyte <offset>]. "
 	"Temps in Celsius.",
 	"Print g781/g782 temp sensor status or set parameters.");
diff --git a/driver/temp_sensor/g78x.h b/driver/temp_sensor/g78x.h
index fdd987fcbd..70abc82a3f 100644
--- a/driver/temp_sensor/g78x.h
+++ b/driver/temp_sensor/g78x.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,118 +12,118 @@
 #error Cannot support both G781 and G782 together!
 #endif
 
-#define G78X_I2C_ADDR_FLAGS		0x4C
+#define G78X_I2C_ADDR_FLAGS 0x4C
 
-#define G78X_IDX_INTERNAL	0
-#define G78X_IDX_EXTERNAL1	1
-#define G78X_IDX_EXTERNAL2	2
+#define G78X_IDX_INTERNAL 0
+#define G78X_IDX_EXTERNAL1 1
+#define G78X_IDX_EXTERNAL2 2
 
 #if defined(CONFIG_TEMP_SENSOR_G781)
 /* G781 register */
-#define G78X_TEMP_LOCAL			0x00
-#define G78X_TEMP_REMOTE1		0x01
-#define G78X_STATUS			0x02
-#define G78X_CONFIGURATION_R		0x03
-#define G78X_CONVERSION_RATE_R		0x04
-#define G78X_LOCAL_TEMP_HIGH_LIMIT_R	0x05
-#define G78X_LOCAL_TEMP_LOW_LIMIT_R	0x06
-#define G78X_REMOTE1_TEMP_HIGH_LIMIT_R	0x07
-#define G78X_REMOTE1_TEMP_LOW_LIMIT_R	0x08
-#define G78X_CONFIGURATION_W		0x09
-#define G78X_CONVERSION_RATE_W		0x0a
-#define G78X_LOCAL_TEMP_HIGH_LIMIT_W	0x0b
-#define G78X_LOCAL_TEMP_LOW_LIMIT_W	0x0c
-#define G78X_REMOTE1_TEMP_HIGH_LIMIT_W	0x0d
-#define G78X_REMOTE1_TEMP_LOW_LIMIT_W	0x0e
-#define G78X_ONESHOT			0x0f
-#define G78X_REMOTE1_TEMP_EXTENDED	0x10
-#define G78X_REMOTE1_TEMP_OFFSET_HIGH	0x11
-#define G78X_REMOTE1_TEMP_OFFSET_EXTD	0x12
-#define G78X_REMOTE1_T_HIGH_LIMIT_EXTD	0x13
-#define G78X_REMOTE1_T_LOW_LIMIT_EXTD	0x14
-#define G78X_REMOTE1_TEMP_THERM_LIMIT	0x19
-#define G78X_LOCAL_TEMP_THERM_LIMIT	0x20
-#define G78X_THERM_HYSTERESIS		0x21
-#define G78X_ALERT_FAULT_QUEUE_CODE	0x22
-#define G78X_MANUFACTURER_ID		0xFE
-#define G78X_DEVICE_ID			0xFF
+#define G78X_TEMP_LOCAL 0x00
+#define G78X_TEMP_REMOTE1 0x01
+#define G78X_STATUS 0x02
+#define G78X_CONFIGURATION_R 0x03
+#define G78X_CONVERSION_RATE_R 0x04
+#define G78X_LOCAL_TEMP_HIGH_LIMIT_R 0x05
+#define G78X_LOCAL_TEMP_LOW_LIMIT_R 0x06
+#define G78X_REMOTE1_TEMP_HIGH_LIMIT_R 0x07
+#define G78X_REMOTE1_TEMP_LOW_LIMIT_R 0x08
+#define G78X_CONFIGURATION_W 0x09
+#define G78X_CONVERSION_RATE_W 0x0a
+#define G78X_LOCAL_TEMP_HIGH_LIMIT_W 0x0b
+#define G78X_LOCAL_TEMP_LOW_LIMIT_W 0x0c
+#define G78X_REMOTE1_TEMP_HIGH_LIMIT_W 0x0d
+#define G78X_REMOTE1_TEMP_LOW_LIMIT_W 0x0e
+#define G78X_ONESHOT 0x0f
+#define G78X_REMOTE1_TEMP_EXTENDED 0x10
+#define G78X_REMOTE1_TEMP_OFFSET_HIGH 0x11
+#define G78X_REMOTE1_TEMP_OFFSET_EXTD 0x12
+#define G78X_REMOTE1_T_HIGH_LIMIT_EXTD 0x13
+#define G78X_REMOTE1_T_LOW_LIMIT_EXTD 0x14
+#define G78X_REMOTE1_TEMP_THERM_LIMIT 0x19
+#define G78X_LOCAL_TEMP_THERM_LIMIT 0x20
+#define G78X_THERM_HYSTERESIS 0x21
+#define G78X_ALERT_FAULT_QUEUE_CODE 0x22
+#define G78X_MANUFACTURER_ID 0xFE
+#define G78X_DEVICE_ID 0xFF
 
 /* Config register bits */
-#define G78X_CONFIGURATION_STANDBY	BIT(6)
-#define G78X_CONFIGURATION_ALERT_MASK	BIT(7)
+#define G78X_CONFIGURATION_STANDBY BIT(6)
+#define G78X_CONFIGURATION_ALERT_MASK BIT(7)
 
 /* Status register bits */
-#define G78X_STATUS_LOCAL_TEMP_THERM_ALARM	BIT(0)
-#define G78X_STATUS_REMOTE1_TEMP_THERM_ALARM	BIT(1)
-#define G78X_STATUS_REMOTE1_TEMP_FAULT		BIT(2)
-#define G78X_STATUS_REMOTE1_TEMP_LOW_ALARM	BIT(3)
-#define G78X_STATUS_REMOTE1_TEMP_HIGH_ALARM	BIT(4)
-#define G78X_STATUS_LOCAL_TEMP_LOW_ALARM	BIT(5)
-#define G78X_STATUS_LOCAL_TEMP_HIGH_ALARM	BIT(6)
-#define G78X_STATUS_BUSY			BIT(7)
+#define G78X_STATUS_LOCAL_TEMP_THERM_ALARM BIT(0)
+#define G78X_STATUS_REMOTE1_TEMP_THERM_ALARM BIT(1)
+#define G78X_STATUS_REMOTE1_TEMP_FAULT BIT(2)
+#define G78X_STATUS_REMOTE1_TEMP_LOW_ALARM BIT(3)
+#define G78X_STATUS_REMOTE1_TEMP_HIGH_ALARM BIT(4)
+#define G78X_STATUS_LOCAL_TEMP_LOW_ALARM BIT(5)
+#define G78X_STATUS_LOCAL_TEMP_HIGH_ALARM BIT(6)
+#define G78X_STATUS_BUSY BIT(7)
 
 #elif defined(CONFIG_TEMP_SENSOR_G782)
 /* G782 register */
-#define G78X_TEMP_LOCAL			0x00
-#define G78X_TEMP_REMOTE1		0x01
-#define G78X_TEMP_REMOTE2		0x02
-#define G78X_STATUS			0x03
-#define G78X_CONFIGURATION_R		0x04
-#define G78X_CONFIGURATION_W		0x04
-#define G78X_CONVERSION_RATE_R		0x05
-#define G78X_CONVERSION_RATE_W		0x05
-#define G78X_LOCAL_TEMP_HIGH_LIMIT_R	0x06
-#define G78X_LOCAL_TEMP_HIGH_LIMIT_W	0x06
-#define G78X_LOCAL_TEMP_LOW_LIMIT_R	0x07
-#define G78X_LOCAL_TEMP_LOW_LIMIT_W	0x07
-#define G78X_REMOTE1_TEMP_HIGH_LIMIT_R	0x08
-#define G78X_REMOTE1_TEMP_HIGH_LIMIT_W	0x08
-#define G78X_REMOTE1_TEMP_LOW_LIMIT_R	0x09
-#define G78X_REMOTE1_TEMP_LOW_LIMIT_W	0x09
-#define G78X_REMOTE2_TEMP_HIGH_LIMIT_R	0x0a
-#define G78X_REMOTE2_TEMP_HIGH_LIMIT_W	0x0a
-#define G78X_REMOTE2_TEMP_LOW_LIMIT_R	0x0b
-#define G78X_REMOTE2_TEMP_LOW_LIMIT_W	0x0b
-#define G78X_ONESHOT			0x0c
-#define G78X_REMOTE1_TEMP_EXTENDED	0x0d
-#define G78X_REMOTE1_TEMP_OFFSET_HIGH	0x0e
-#define G78X_REMOTE1_TEMP_OFFSET_EXTD	0x0f
-#define G78X_REMOTE1_T_HIGH_LIMIT_EXTD	0x10
-#define G78X_REMOTE1_T_LOW_LIMIT_EXTD	0x11
-#define G78X_REMOTE1_TEMP_THERM_LIMIT	0x12
-#define G78X_REMOTE2_TEMP_EXTENDED	0x13
-#define G78X_REMOTE2_TEMP_OFFSET_HIGH	0x14
-#define G78X_REMOTE2_TEMP_OFFSET_EXTD	0x15
-#define G78X_REMOTE2_T_HIGH_LIMIT_EXTD	0x16
-#define G78X_REMOTE2_T_LOW_LIMIT_EXTD	0x17
-#define G78X_REMOTE2_TEMP_THERM_LIMIT	0x18
-#define G78X_STATUS1			0x19
-#define G78X_LOCAL_TEMP_THERM_LIMIT	0x20
-#define G78X_THERM_HYSTERESIS		0x21
-#define G78X_ALERT_FAULT_QUEUE_CODE	0x22
-#define G78X_MANUFACTURER_ID		0xFE
-#define G78X_DEVICE_ID			0xFF
+#define G78X_TEMP_LOCAL 0x00
+#define G78X_TEMP_REMOTE1 0x01
+#define G78X_TEMP_REMOTE2 0x02
+#define G78X_STATUS 0x03
+#define G78X_CONFIGURATION_R 0x04
+#define G78X_CONFIGURATION_W 0x04
+#define G78X_CONVERSION_RATE_R 0x05
+#define G78X_CONVERSION_RATE_W 0x05
+#define G78X_LOCAL_TEMP_HIGH_LIMIT_R 0x06
+#define G78X_LOCAL_TEMP_HIGH_LIMIT_W 0x06
+#define G78X_LOCAL_TEMP_LOW_LIMIT_R 0x07
+#define G78X_LOCAL_TEMP_LOW_LIMIT_W 0x07
+#define G78X_REMOTE1_TEMP_HIGH_LIMIT_R 0x08
+#define G78X_REMOTE1_TEMP_HIGH_LIMIT_W 0x08
+#define G78X_REMOTE1_TEMP_LOW_LIMIT_R 0x09
+#define G78X_REMOTE1_TEMP_LOW_LIMIT_W 0x09
+#define G78X_REMOTE2_TEMP_HIGH_LIMIT_R 0x0a
+#define G78X_REMOTE2_TEMP_HIGH_LIMIT_W 0x0a
+#define G78X_REMOTE2_TEMP_LOW_LIMIT_R 0x0b
+#define G78X_REMOTE2_TEMP_LOW_LIMIT_W 0x0b
+#define G78X_ONESHOT 0x0c
+#define G78X_REMOTE1_TEMP_EXTENDED 0x0d
+#define G78X_REMOTE1_TEMP_OFFSET_HIGH 0x0e
+#define G78X_REMOTE1_TEMP_OFFSET_EXTD 0x0f
+#define G78X_REMOTE1_T_HIGH_LIMIT_EXTD 0x10
+#define G78X_REMOTE1_T_LOW_LIMIT_EXTD 0x11
+#define G78X_REMOTE1_TEMP_THERM_LIMIT 0x12
+#define G78X_REMOTE2_TEMP_EXTENDED 0x13
+#define G78X_REMOTE2_TEMP_OFFSET_HIGH 0x14
+#define G78X_REMOTE2_TEMP_OFFSET_EXTD 0x15
+#define G78X_REMOTE2_T_HIGH_LIMIT_EXTD 0x16
+#define G78X_REMOTE2_T_LOW_LIMIT_EXTD 0x17
+#define G78X_REMOTE2_TEMP_THERM_LIMIT 0x18
+#define G78X_STATUS1 0x19
+#define G78X_LOCAL_TEMP_THERM_LIMIT 0x20
+#define G78X_THERM_HYSTERESIS 0x21
+#define G78X_ALERT_FAULT_QUEUE_CODE 0x22
+#define G78X_MANUFACTURER_ID 0xFE
+#define G78X_DEVICE_ID 0xFF
 
 /* Config register bits */
-#define G78X_CONFIGURATION_REMOTE2_DIS	BIT(5)
-#define G78X_CONFIGURATION_STANDBY	BIT(6)
-#define G78X_CONFIGURATION_ALERT_MASK	BIT(7)
+#define G78X_CONFIGURATION_REMOTE2_DIS BIT(5)
+#define G78X_CONFIGURATION_STANDBY BIT(6)
+#define G78X_CONFIGURATION_ALERT_MASK BIT(7)
 
 /* Status register bits */
-#define G78X_STATUS_LOCAL_TEMP_LOW_ALARM	BIT(0)
-#define G78X_STATUS_LOCAL_TEMP_HIGH_ALARM	BIT(1)
-#define G78X_STATUS_LOCAL_TEMP_THERM_ALARM	BIT(2)
-#define G78X_STATUS_REMOTE2_TEMP_THERM_ALARM	BIT(3)
-#define G78X_STATUS_REMOTE1_TEMP_THERM_ALARM	BIT(4)
-#define G78X_STATUS_REMOTE2_TEMP_FAULT		BIT(5)
-#define G78X_STATUS_REMOTE1_TEMP_FAULT		BIT(6)
-#define G78X_STATUS_BUSY			BIT(7)
+#define G78X_STATUS_LOCAL_TEMP_LOW_ALARM BIT(0)
+#define G78X_STATUS_LOCAL_TEMP_HIGH_ALARM BIT(1)
+#define G78X_STATUS_LOCAL_TEMP_THERM_ALARM BIT(2)
+#define G78X_STATUS_REMOTE2_TEMP_THERM_ALARM BIT(3)
+#define G78X_STATUS_REMOTE1_TEMP_THERM_ALARM BIT(4)
+#define G78X_STATUS_REMOTE2_TEMP_FAULT BIT(5)
+#define G78X_STATUS_REMOTE1_TEMP_FAULT BIT(6)
+#define G78X_STATUS_BUSY BIT(7)
 
 /* Status1 register bits */
-#define G78X_STATUS_REMOTE2_TEMP_LOW_ALARM	BIT(4)
-#define G78X_STATUS_REMOTE2_TEMP_HIGH_ALARM	BIT(5)
-#define G78X_STATUS_REMOTE1_TEMP_LOW_ALARM	BIT(6)
-#define G78X_STATUS_REMOTE1_TEMP_HIGH_ALARM	BIT(7)
+#define G78X_STATUS_REMOTE2_TEMP_LOW_ALARM BIT(4)
+#define G78X_STATUS_REMOTE2_TEMP_HIGH_ALARM BIT(5)
+#define G78X_STATUS_REMOTE1_TEMP_LOW_ALARM BIT(6)
+#define G78X_STATUS_REMOTE1_TEMP_HIGH_ALARM BIT(7)
 #endif
 
 /**
@@ -137,4 +137,4 @@
  */
 int g78x_get_val(int idx, int *temp_ptr);
 
-#endif  /* __CROS_EC_G78X_H */
+#endif /* __CROS_EC_G78X_H */
diff --git a/driver/temp_sensor/oti502.c b/driver/temp_sensor/oti502.c
index 8a420363e8..4564ad9257 100644
--- a/driver/temp_sensor/oti502.c
+++ b/driver/temp_sensor/oti502.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,18 +7,18 @@
 
 #include "common.h"
 #include "console.h"
-#include "oti502.h"
-#include "i2c.h"
 #include "hooks.h"
+#include "i2c.h"
+#include "oti502.h"
 #include "util.h"
 
-static int temp_val_ambient;	/* Ambient is chip temperature*/
-static int temp_val_object;		/* Object is IR temperature */
+static int temp_val_ambient; /* Ambient is chip temperature*/
+static int temp_val_object; /* Object is IR temperature */
 
 static int oti502_read_block(const int offset, uint8_t *data, int len)
 {
-	return i2c_read_block(I2C_PORT_THERMAL, OTI502_I2C_ADDR_FLAGS,
-			 offset, data, len);
+	return i2c_read_block(I2C_PORT_THERMAL, OTI502_I2C_ADDR_FLAGS, offset,
+			      data, len);
 }
 
 int oti502_get_val(int idx, int *temp_ptr)
@@ -64,4 +64,3 @@ static void temp_sensor_poll(void)
 	}
 }
 DECLARE_HOOK(HOOK_SECOND, temp_sensor_poll, HOOK_PRIO_TEMP_SENSOR);
-
diff --git a/driver/temp_sensor/oti502.h b/driver/temp_sensor/oti502.h
index 4e846282c1..fd09362589 100644
--- a/driver/temp_sensor/oti502.h
+++ b/driver/temp_sensor/oti502.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,10 +8,10 @@
 #ifndef __CROS_EC_OTI502_H
 #define __CROS_EC_OTI502_H
 
-#define OTI502_I2C_ADDR_FLAGS		0x10
+#define OTI502_I2C_ADDR_FLAGS 0x10
 
-#define OTI502_IDX_AMBIENT	0
-#define OTI502_IDX_OBJECT	1
+#define OTI502_IDX_AMBIENT 0
+#define OTI502_IDX_OBJECT 1
 
 /**
  * Get the last polled value of a sensor.
@@ -24,4 +24,4 @@
  */
 int oti502_get_val(int idx, int *temp_ptr);
 
-#endif  /* __CROS_EC_OTI502_H */
+#endif /* __CROS_EC_OTI502_H */
diff --git a/driver/temp_sensor/pct2075.c b/driver/temp_sensor/pct2075.c
new file mode 100644
index 0000000000..02150ad796
--- /dev/null
+++ b/driver/temp_sensor/pct2075.c
@@ -0,0 +1,108 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* PCT2075 temperature sensor module for Chrome EC */
+
+#include "common.h"
+#include "console.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "math_util.h"
+#include "temp_sensor/pct2075.h"
+#include "util.h"
+
+#ifdef CONFIG_ZEPHYR
+#include "temp_sensor/temp_sensor.h"
+#endif
+
+#define PCT2075_RESOLUTION 11
+#define PCT2075_SHIFT1 (16 - PCT2075_RESOLUTION)
+#define PCT2075_SHIFT2 (PCT2075_RESOLUTION - 8)
+
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
+
+static int temp_mk_local[PCT2075_COUNT];
+
+static int raw_read16(int sensor, const int offset, int *data_ptr)
+{
+#ifdef CONFIG_I2C_BUS_MAY_BE_UNPOWERED
+	/*
+	 * Don't try to read if the port is unpowered
+	 */
+	if (!board_is_i2c_port_powered(pct2075_sensors[sensor].i2c_port))
+		return EC_ERROR_NOT_POWERED;
+#endif
+	return i2c_read16(pct2075_sensors[sensor].i2c_port,
+			  pct2075_sensors[sensor].i2c_addr_flags, offset,
+			  data_ptr);
+}
+
+static int get_reg_temp(int sensor, int *temp_ptr)
+{
+	int temp_raw = 0;
+
+	RETURN_ERROR(raw_read16(sensor, PCT2075_REG_TEMP, &temp_raw));
+
+	*temp_ptr = (int)(int16_t)temp_raw;
+	return EC_SUCCESS;
+}
+
+static inline int pct2075_reg_to_mk(int16_t reg)
+{
+	int temp_mc;
+
+	temp_mc = (((reg >> PCT2075_SHIFT1) * 1000) >> PCT2075_SHIFT2);
+
+	return MILLI_CELSIUS_TO_MILLI_KELVIN(temp_mc);
+}
+
+int pct2075_get_val_k(int idx, int *temp_k_ptr)
+{
+	if (idx >= PCT2075_COUNT)
+		return EC_ERROR_INVAL;
+
+	*temp_k_ptr = MILLI_KELVIN_TO_KELVIN(temp_mk_local[idx]);
+	return EC_SUCCESS;
+}
+
+int pct2075_get_val_mk(int idx, int *temp_mk_ptr)
+{
+	if (idx >= PCT2075_COUNT)
+		return EC_ERROR_INVAL;
+
+	*temp_mk_ptr = temp_mk_local[idx];
+	return EC_SUCCESS;
+}
+
+#ifndef CONFIG_ZEPHYR
+static void pct2075_poll(void)
+{
+	int s;
+	int temp_reg = 0;
+
+	for (s = 0; s < PCT2075_COUNT; s++) {
+		if (get_reg_temp(s, &temp_reg) == EC_SUCCESS)
+			temp_mk_local[s] = pct2075_reg_to_mk(temp_reg);
+	}
+}
+DECLARE_HOOK(HOOK_SECOND, pct2075_poll, HOOK_PRIO_TEMP_SENSOR);
+#else
+void pct2075_update_temperature(int idx)
+{
+	int temp_reg = 0;
+
+	if (idx >= PCT2075_COUNT)
+		return;
+
+	if (get_reg_temp(idx, &temp_reg) == EC_SUCCESS)
+		temp_mk_local[idx] = pct2075_reg_to_mk(temp_reg);
+}
+#endif /* CONFIG_ZEPHYR */
+
+void pct2075_init(void)
+{
+	/* Incase we need to initialize somthing */
+}
+DECLARE_HOOK(HOOK_INIT, pct2075_init, HOOK_PRIO_DEFAULT);
diff --git a/driver/temp_sensor/sb_tsi.c b/driver/temp_sensor/sb_tsi.c
index 308f604435..950d84a493 100644
--- a/driver/temp_sensor/sb_tsi.c
+++ b/driver/temp_sensor/sb_tsi.c
@@ -1,11 +1,11 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /*
  * SB-TSI: SB Temperature Sensor Interface.
- * This is an I2C slave temp sensor on the AMD Stony Ridge FT4 SOC.
+ * This is an I2C temp sensor on the AMD Stony Ridge FT4 SOC.
  */
 
 #include "chipset.h"
@@ -14,13 +14,13 @@
 #include "gpio.h"
 #include "hooks.h"
 #include "i2c.h"
-#include "sb_tsi.h"
+#include "temp_sensor/sb_tsi.h"
 #include "util.h"
 
 static int raw_read8(const int offset, int *data_ptr)
 {
-	return i2c_read8(I2C_PORT_THERMAL_AP, SB_TSI_I2C_ADDR_FLAGS,
-			 offset, data_ptr);
+	return i2c_read8(I2C_PORT_THERMAL_AP, SB_TSI_I2C_ADDR_FLAGS, offset,
+			 data_ptr);
 }
 
 int sb_tsi_get_val(int idx, int *temp_ptr)
@@ -30,7 +30,7 @@ int sb_tsi_get_val(int idx, int *temp_ptr)
 	if (idx != 0)
 		return EC_ERROR_PARAM1;
 	/* FT4 SB-TSI sensor only powered in S0 */
-	if (!chipset_in_state(CHIPSET_STATE_ON))
+	if (!chipset_in_state(CHIPSET_STATE_ON) || chipset_in_low_power_mode())
 		return EC_ERROR_NOT_POWERED;
 	/* Read the value over I2C */
 	ret = raw_read8(SB_TSI_TEMP_H, temp_ptr);
diff --git a/driver/temp_sensor/sb_tsi.h b/driver/temp_sensor/sb_tsi.h
deleted file mode 100644
index ae61e4e34d..0000000000
--- a/driver/temp_sensor/sb_tsi.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * SB-TSI: SB Temperature Sensor Interface.
- * This is an I2C slave temp sensor on the AMD Stony Ridge FT4 SOC.
- */
-
-#ifndef __CROS_EC_SB_TSI_H
-#define __CROS_EC_SB_TSI_H
-
-#define SB_TSI_I2C_ADDR_FLAGS		0x4C
-
-/* G781 register */
-#define SB_TSI_TEMP_H			0x01
-#define SB_TSI_STATUS			0x02
-#define SB_TSI_CONFIG_1			0x03
-#define SB_TSI_UPDATE_RATE		0x04
-#define SB_TSI_HIGH_TEMP_THRESHOLD_H	0x07
-#define SB_TSI_LOW_TEMP_THRESHOLD_H	0x08
-#define SB_TSI_CONFIG_2			0x09
-#define SB_TSI_TEMP_L			0x10
-#define SB_TSI_TEMP_OFFSET_H		0x11
-#define SB_TSI_TEMP_OFFSET_L		0x12
-#define SB_TSI_HIGH_TEMP_THRESHOLD_L	0x13
-#define SB_TSI_LOW_TEMP_THRESHOLD_L	0x14
-#define SB_TSI_TIMEOUT_CONFIG		0x22
-#define SB_TSI_PSTATE_LIMIT_CONFIG	0x2F
-#define SB_TSI_ALERT_THRESHOLD		0x32
-#define SB_TSI_ALERT_CONFIG		0xBF
-#define SB_TSI_MANUFACTURE_ID		0xFE
-#define SB_TSI_REVISION			0xFF
-
-/**
- * Get the value of a sensor in K.
- *
- * @param idx		Index to read. Only 0 is valid for sb_tsi.
- * @param temp_ptr	Destination for temperature in K.
- *
- * @return EC_SUCCESS if successful, non-zero if error.
- */
-int sb_tsi_get_val(int idx, int *temp_ptr);
-
-#endif  /* __CROS_EC_SB_TSI_H */
diff --git a/driver/temp_sensor/thermistor.c b/driver/temp_sensor/thermistor.c
index dab0e985ce..25fe0f56e8 100644
--- a/driver/temp_sensor/thermistor.c
+++ b/driver/temp_sensor/thermistor.c
@@ -1,18 +1,22 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-/* Common thermistor code for Chrome EC */
+/*
+ * Common thermistor code for Chrome EC. See ./thermistor.md for table of
+ * resistance of a 47kΩ B4050 thermistor
+ */
 
 #include "adc.h"
+#include "builtin/assert.h"
 #include "common.h"
 #include "gpio.h"
-#include "thermistor.h"
+#include "temp_sensor/thermistor.h"
 #include "util.h"
 
 int thermistor_linear_interpolate(uint16_t mv,
-		const struct thermistor_info *info)
+				  const struct thermistor_info *info)
 {
 	const struct thermistor_data_pair *data = info->data;
 	int v_high = 0, v_low = 0, t_low, t_high, num_steps;
@@ -63,24 +67,25 @@ int thermistor_linear_interpolate(uint16_t mv,
 	return t_low + num_steps;
 }
 
-#if defined(CONFIG_STEINHART_HART_3V3_51K1_47K_4050B) || \
+#if defined(CONFIG_STEINHART_HART_3V3_51K1_47K_4050B) ||     \
 	defined(CONFIG_STEINHART_HART_3V3_13K7_47K_4050B) || \
 	defined(CONFIG_STEINHART_HART_6V0_51K1_47K_4050B) || \
 	defined(CONFIG_STEINHART_HART_3V0_22K6_47K_4050B) || \
-	defined(CONFIG_STEINHART_HART_3V3_30K9_47K_4050B)
-static int thermistor_get_temperature(int idx_adc, int *temp_ptr,
-		const struct thermistor_info *info)
+	defined(CONFIG_STEINHART_HART_3V3_30K9_47K_4050B) || \
+	defined(CONFIG_ZEPHYR)
+int thermistor_get_temperature(int idx_adc, int *temp_ptr,
+			       const struct thermistor_info *info)
 {
 	int mv;
 
-#ifdef CONFIG_TEMP_SENSOR_POWER_GPIO
+#ifdef CONFIG_TEMP_SENSOR_POWER
 	/*
 	 * If the power rail for the thermistor circuit is not enabled, then
 	 * need to ignore any ADC measurments.
 	 */
-	if (!gpio_get_level(CONFIG_TEMP_SENSOR_POWER_GPIO))
+	if (!gpio_get_level(GPIO_TEMP_SENSOR_POWER))
 		return EC_ERROR_NOT_POWERED;
-#endif /* CONFIG_TEMP_SENSOR_POWER_GPIO */
+#endif /* CONFIG_TEMP_SENSOR_POWER */
 	mv = adc_read_channel(idx_adc);
 	if (mv < 0)
 		return EC_ERROR_UNKNOWN;
@@ -99,19 +104,19 @@ static int thermistor_get_temperature(int idx_adc, int *temp_ptr,
  */
 #define THERMISTOR_SCALING_FACTOR_51_47 11
 static const struct thermistor_data_pair thermistor_data_51_47[] = {
-	{ 2512 / THERMISTOR_SCALING_FACTOR_51_47, 0   },
-	{ 2158 / THERMISTOR_SCALING_FACTOR_51_47, 10  },
-	{ 1772 / THERMISTOR_SCALING_FACTOR_51_47, 20  },
-	{ 1398 / THERMISTOR_SCALING_FACTOR_51_47, 30  },
-	{ 1070 / THERMISTOR_SCALING_FACTOR_51_47, 40  },
-	{  803 / THERMISTOR_SCALING_FACTOR_51_47, 50  },
-	{  597 / THERMISTOR_SCALING_FACTOR_51_47, 60  },
-	{  443 / THERMISTOR_SCALING_FACTOR_51_47, 70  },
-	{  329 / THERMISTOR_SCALING_FACTOR_51_47, 80  },
-	{  285 / THERMISTOR_SCALING_FACTOR_51_47, 85  },
-	{  247 / THERMISTOR_SCALING_FACTOR_51_47, 90  },
-	{  214 / THERMISTOR_SCALING_FACTOR_51_47, 95  },
-	{  187 / THERMISTOR_SCALING_FACTOR_51_47, 100 },
+	{ 2484 / THERMISTOR_SCALING_FACTOR_51_47, 0 },
+	{ 2142 / THERMISTOR_SCALING_FACTOR_51_47, 10 },
+	{ 1767 / THERMISTOR_SCALING_FACTOR_51_47, 20 },
+	{ 1400 / THERMISTOR_SCALING_FACTOR_51_47, 30 },
+	{ 1072 / THERMISTOR_SCALING_FACTOR_51_47, 40 },
+	{ 802 / THERMISTOR_SCALING_FACTOR_51_47, 50 },
+	{ 593 / THERMISTOR_SCALING_FACTOR_51_47, 60 },
+	{ 436 / THERMISTOR_SCALING_FACTOR_51_47, 70 },
+	{ 321 / THERMISTOR_SCALING_FACTOR_51_47, 80 },
+	{ 276 / THERMISTOR_SCALING_FACTOR_51_47, 85 },
+	{ 237 / THERMISTOR_SCALING_FACTOR_51_47, 90 },
+	{ 204 / THERMISTOR_SCALING_FACTOR_51_47, 95 },
+	{ 177 / THERMISTOR_SCALING_FACTOR_51_47, 100 },
 };
 
 static const struct thermistor_info thermistor_info_51_47 = {
@@ -123,7 +128,7 @@ static const struct thermistor_info thermistor_info_51_47 = {
 int get_temp_3v3_51k1_47k_4050b(int idx_adc, int *temp_ptr)
 {
 	return thermistor_get_temperature(idx_adc, temp_ptr,
-			&thermistor_info_51_47);
+					  &thermistor_info_51_47);
 }
 #endif /* CONFIG_STEINHART_HART_3V3_51K1_47K_4050B */
 
@@ -135,19 +140,19 @@ int get_temp_3v3_51k1_47k_4050b(int idx_adc, int *temp_ptr)
  */
 #define THERMISTOR_SCALING_FACTOR_13_47 13
 static const struct thermistor_data_pair thermistor_data_13_47[] = {
-	{ 3044 / THERMISTOR_SCALING_FACTOR_13_47, 0   },
-	{ 2890 / THERMISTOR_SCALING_FACTOR_13_47, 10  },
-	{ 2680 / THERMISTOR_SCALING_FACTOR_13_47, 20  },
-	{ 2418 / THERMISTOR_SCALING_FACTOR_13_47, 30  },
-	{ 2117 / THERMISTOR_SCALING_FACTOR_13_47, 40  },
-	{ 1800 / THERMISTOR_SCALING_FACTOR_13_47, 50  },
-	{ 1490 / THERMISTOR_SCALING_FACTOR_13_47, 60  },
-	{ 1208 / THERMISTOR_SCALING_FACTOR_13_47, 70  },
-	{  966 / THERMISTOR_SCALING_FACTOR_13_47, 80  },
-	{  860 / THERMISTOR_SCALING_FACTOR_13_47, 85  },
-	{  766 / THERMISTOR_SCALING_FACTOR_13_47, 90  },
-	{  679 / THERMISTOR_SCALING_FACTOR_13_47, 95  },
-	{  603 / THERMISTOR_SCALING_FACTOR_13_47, 100 },
+	{ 3033 / THERMISTOR_SCALING_FACTOR_13_47, 0 },
+	{ 2882 / THERMISTOR_SCALING_FACTOR_13_47, 10 },
+	{ 2677 / THERMISTOR_SCALING_FACTOR_13_47, 20 },
+	{ 2420 / THERMISTOR_SCALING_FACTOR_13_47, 30 },
+	{ 2119 / THERMISTOR_SCALING_FACTOR_13_47, 40 },
+	{ 1799 / THERMISTOR_SCALING_FACTOR_13_47, 50 },
+	{ 1485 / THERMISTOR_SCALING_FACTOR_13_47, 60 },
+	{ 1197 / THERMISTOR_SCALING_FACTOR_13_47, 70 },
+	{ 947 / THERMISTOR_SCALING_FACTOR_13_47, 80 },
+	{ 839 / THERMISTOR_SCALING_FACTOR_13_47, 85 },
+	{ 741 / THERMISTOR_SCALING_FACTOR_13_47, 90 },
+	{ 653 / THERMISTOR_SCALING_FACTOR_13_47, 95 },
+	{ 576 / THERMISTOR_SCALING_FACTOR_13_47, 100 },
 };
 
 static const struct thermistor_info thermistor_info_13_47 = {
@@ -159,7 +164,7 @@ static const struct thermistor_info thermistor_info_13_47 = {
 int get_temp_3v3_13k7_47k_4050b(int idx_adc, int *temp_ptr)
 {
 	return thermistor_get_temperature(idx_adc, temp_ptr,
-			&thermistor_info_13_47);
+					  &thermistor_info_13_47);
 }
 #endif /* CONFIG_STEINHART_HART_3V3_13K7_47K_4050B */
 
@@ -171,19 +176,19 @@ int get_temp_3v3_13k7_47k_4050b(int idx_adc, int *temp_ptr)
  */
 #define THERMISTOR_SCALING_FACTOR_6V0_51_47 18
 static const struct thermistor_data_pair thermistor_data_6v0_51_47[] = {
-	{ 4517 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 0   },
-	{ 3895 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 10  },
-	{ 3214 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 20  },
-	{ 2546 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 30  },
-	{ 1950 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 40  },
-	{ 1459 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 50  },
-	{ 1079 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 60  },
-	{  794 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 70  },
-	{  584 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 80  },
-	{  502 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 85  },
-	{  432 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 90  },
-	{  372 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 95  },
-	{  322 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 100 },
+	{ 4517 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 0 },
+	{ 3895 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 10 },
+	{ 3214 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 20 },
+	{ 2546 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 30 },
+	{ 1950 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 40 },
+	{ 1459 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 50 },
+	{ 1079 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 60 },
+	{ 794 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 70 },
+	{ 584 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 80 },
+	{ 502 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 85 },
+	{ 432 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 90 },
+	{ 372 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 95 },
+	{ 322 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 100 },
 };
 
 static const struct thermistor_info thermistor_info_6v0_51_47 = {
@@ -195,7 +200,7 @@ static const struct thermistor_info thermistor_info_6v0_51_47 = {
 int get_temp_6v0_51k1_47k_4050b(int idx_adc, int *temp_ptr)
 {
 	return thermistor_get_temperature(idx_adc, temp_ptr,
-			&thermistor_info_6v0_51_47);
+					  &thermistor_info_6v0_51_47);
 }
 #endif /* CONFIG_STEINHART_HART_6V0_51K1_47K_4050B */
 
@@ -207,19 +212,19 @@ int get_temp_6v0_51k1_47k_4050b(int idx_adc, int *temp_ptr)
  */
 #define THERMISTOR_SCALING_FACTOR_22_47 11
 static const struct thermistor_data_pair thermistor_data_22_47[] = {
-	{ 2625 / THERMISTOR_SCALING_FACTOR_22_47, 0   },
-	{ 2425 / THERMISTOR_SCALING_FACTOR_22_47, 10  },
-	{ 2170 / THERMISTOR_SCALING_FACTOR_22_47, 20  },
-	{ 1875 / THERMISTOR_SCALING_FACTOR_22_47, 30  },
-	{ 1563 / THERMISTOR_SCALING_FACTOR_22_47, 40  },
-	{ 1263 / THERMISTOR_SCALING_FACTOR_22_47, 50  },
-	{  995 / THERMISTOR_SCALING_FACTOR_22_47, 60  },
-	{  770 / THERMISTOR_SCALING_FACTOR_22_47, 70  },
-	{  589 / THERMISTOR_SCALING_FACTOR_22_47, 80  },
-	{  514 / THERMISTOR_SCALING_FACTOR_22_47, 85  },
-	{  448 / THERMISTOR_SCALING_FACTOR_22_47, 90  },
-	{  391 / THERMISTOR_SCALING_FACTOR_22_47, 95  },
-	{  341 / THERMISTOR_SCALING_FACTOR_22_47, 100 },
+	{ 2619 / THERMISTOR_SCALING_FACTOR_22_47, 0 },
+	{ 2421 / THERMISTOR_SCALING_FACTOR_22_47, 10 },
+	{ 2168 / THERMISTOR_SCALING_FACTOR_22_47, 20 },
+	{ 1875 / THERMISTOR_SCALING_FACTOR_22_47, 30 },
+	{ 1563 / THERMISTOR_SCALING_FACTOR_22_47, 40 },
+	{ 1262 / THERMISTOR_SCALING_FACTOR_22_47, 50 },
+	{ 994 / THERMISTOR_SCALING_FACTOR_22_47, 60 },
+	{ 769 / THERMISTOR_SCALING_FACTOR_22_47, 70 },
+	{ 588 / THERMISTOR_SCALING_FACTOR_22_47, 80 },
+	{ 513 / THERMISTOR_SCALING_FACTOR_22_47, 85 },
+	{ 448 / THERMISTOR_SCALING_FACTOR_22_47, 90 },
+	{ 390 / THERMISTOR_SCALING_FACTOR_22_47, 95 },
+	{ 340 / THERMISTOR_SCALING_FACTOR_22_47, 100 },
 };
 
 static const struct thermistor_info thermistor_info_22_47 = {
@@ -231,28 +236,28 @@ static const struct thermistor_info thermistor_info_22_47 = {
 int get_temp_3v0_22k6_47k_4050b(int idx_adc, int *temp_ptr)
 {
 	return thermistor_get_temperature(idx_adc, temp_ptr,
-			&thermistor_info_22_47);
+					  &thermistor_info_22_47);
 }
 #endif /* CONFIG_STEINHART_HART_3V0_22K6_47K_4050B */
 
 #ifdef CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
 /*
  * Data derived from Steinhart-Hart equation in a resistor divider circuit with
- * Vdd=3000mV, R = 30.9Kohm, and thermistor (B = 4050, T0 = 298.15 K, nominal
+ * Vdd=3300mV, R = 30.9Kohm, and thermistor (B = 4050, T0 = 298.15 K, nominal
  * resistance (R0) = 47Kohm).
  */
 #define THERMISTOR_SCALING_FACTOR_31_47 11
 static const struct thermistor_data_pair thermistor_data_31_47[] = {
-	{ 2753 / THERMISTOR_SCALING_FACTOR_31_47, 0   },
-	{ 2487 / THERMISTOR_SCALING_FACTOR_31_47, 10  },
-	{ 2165 / THERMISTOR_SCALING_FACTOR_31_47, 20  },
-	{ 1813 / THERMISTOR_SCALING_FACTOR_31_47, 30  },
-	{ 1145 / THERMISTOR_SCALING_FACTOR_31_47, 50  },
-	{  878 / THERMISTOR_SCALING_FACTOR_31_47, 60  },
-	{  665 / THERMISTOR_SCALING_FACTOR_31_47, 70  },
-	{  500 / THERMISTOR_SCALING_FACTOR_31_47, 80  },
-	{  375 / THERMISTOR_SCALING_FACTOR_31_47, 90  },
-	{  282 / THERMISTOR_SCALING_FACTOR_31_47, 100 },
+	{ 2753 / THERMISTOR_SCALING_FACTOR_31_47, 0 },
+	{ 2487 / THERMISTOR_SCALING_FACTOR_31_47, 10 },
+	{ 2165 / THERMISTOR_SCALING_FACTOR_31_47, 20 },
+	{ 1813 / THERMISTOR_SCALING_FACTOR_31_47, 30 },
+	{ 1145 / THERMISTOR_SCALING_FACTOR_31_47, 50 },
+	{ 878 / THERMISTOR_SCALING_FACTOR_31_47, 60 },
+	{ 665 / THERMISTOR_SCALING_FACTOR_31_47, 70 },
+	{ 500 / THERMISTOR_SCALING_FACTOR_31_47, 80 },
+	{ 375 / THERMISTOR_SCALING_FACTOR_31_47, 90 },
+	{ 282 / THERMISTOR_SCALING_FACTOR_31_47, 100 },
 };
 
 static const struct thermistor_info thermistor_info_31_47 = {
@@ -264,6 +269,6 @@ static const struct thermistor_info thermistor_info_31_47 = {
 int get_temp_3v3_30k9_47k_4050b(int idx_adc, int *temp_ptr)
 {
 	return thermistor_get_temperature(idx_adc, temp_ptr,
-			&thermistor_info_31_47);
+					  &thermistor_info_31_47);
 }
 #endif /* CONFIG_STEINHART_HART_3V3_30K9_47K_4050B */
diff --git a/driver/temp_sensor/thermistor.md b/driver/temp_sensor/thermistor.md
new file mode 100644
index 0000000000..bb9faa04ef
--- /dev/null
+++ b/driver/temp_sensor/thermistor.md
@@ -0,0 +1,106 @@
+We used the following resistance table for a 47kΩ B4050 thermistor in the
+[thermistor.c](./thermistor.c) tables.
+
+C°   | kΩ
+--- | -----
+0   | 155.7
+1   | 147.9
+2   | 140.6
+3   | 133.7
+4   | 127.2
+5   | 121.0
+6   | 115.1
+7   | 109.6
+8   | 104.3
+9   | 99.31
+10  | 94.6
+11  | 90.13
+12  | 85.89
+13  | 81.87
+14  | 78.07
+15  | 74.45
+16  | 71.02
+17  | 67.77
+18  | 64.68
+19  | 61.75
+20  | 58.97
+21  | 56.32
+22  | 53.81
+23  | 51.43
+24  | 49.16
+25  | 47.0
+26  | 44.95
+27  | 42.99
+28  | 41.13
+29  | 39.36
+30  | 37.68
+31  | 36.07
+32  | 34.54
+33  | 33.08
+34  | 31.69
+35  | 30.36
+36  | 29.1
+37  | 27.9
+38  | 26.75
+39  | 25.65
+40  | 24.61
+41  | 23.61
+42  | 22.66
+43  | 21.75
+44  | 20.88
+45  | 20.05
+46  | 19.26
+47  | 18.5
+48  | 17.78
+49  | 17.09
+50  | 16.43
+51  | 15.8
+52  | 15.2
+53  | 14.62
+54  | 14.07
+55  | 13.54
+56  | 13.03
+57  | 12.55
+58  | 12.09
+59  | 11.64
+60  | 11.21
+61  | 10.8
+62  | 10.41
+63  | 10.04
+64  | 9.676
+65  | 9.331
+66  | 8.999
+67  | 8.68
+68  | 8.374
+69  | 8.081
+70  | 7.799
+71  | 7.528
+72  | 7.268
+73  | 7.018
+74  | 6.777
+75  | 6.546
+76  | 6.324
+77  | 6.111
+78  | 5.906
+79  | 5.708
+80  | 5.518
+81  | 5.335
+82  | 5.16
+83  | 4.99
+84  | 4.827
+85  | 4.671
+86  | 4.519
+87  | 4.374
+88  | 4.233
+89  | 4.098
+90  | 3.968
+91  | 3.842
+92  | 3.721
+93  | 3.605
+94  | 3.492
+95  | 3.384
+96  | 3.279
+97  | 3.179
+98  | 3.082
+99  | 2.988
+100 | 2.898
diff --git a/driver/temp_sensor/thermistor_ncp15wb.c b/driver/temp_sensor/thermistor_ncp15wb.c
index 51e884ed35..93896cfcc2 100644
--- a/driver/temp_sensor/thermistor_ncp15wb.c
+++ b/driver/temp_sensor/thermistor_ncp15wb.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,7 @@
 /* NCP15WB thermistor module for Chrome EC */
 
 #include "common.h"
-#include "thermistor.h"
+#include "temp_sensor/thermistor.h"
 #include "util.h"
 
 /*
@@ -15,30 +15,30 @@
  * For 50C through 100C, use linear interpolation from discreet points
  * in table below. For temps < 50C, use a simplified linear function.
  */
-#define ADC_DISCREET_RANGE_START_TEMP	50
+#define ADC_DISCREET_RANGE_START_TEMP 50
 /* 10 bit ADC result corresponding to START_TEMP */
-#define ADC_DISCREET_RANGE_START_RESULT	407
+#define ADC_DISCREET_RANGE_START_RESULT 407
 
-#define ADC_DISCREET_RANGE_LIMIT_TEMP	100
+#define ADC_DISCREET_RANGE_LIMIT_TEMP 100
 /* 10 bit ADC result corresponding to LIMIT_TEMP */
-#define ADC_DISCREET_RANGE_LIMIT_RESULT	107
+#define ADC_DISCREET_RANGE_LIMIT_RESULT 107
 
 /* Table entries in steppings of 5C */
-#define ADC_DISCREET_RANGE_STEP		5
+#define ADC_DISCREET_RANGE_STEP 5
 
 /* Discreet range ADC results (9 bit) per temperature, in 5 degree steps */
 static const uint8_t adc_result[] = {
-	203,	/* 50 C */
-	178,	/* 55 C */
-	157,	/* 60 C */
-	138,	/* 65 C */
-	121,	/* 70 C */
-	106,	/* 75 C */
-	93,	/* 80 C */
-	81,	/* 85 C */
-	70,	/* 90 C */
-	61,	/* 95 C */
-	53,	/* 100 C */
+	203, /* 50 C */
+	178, /* 55 C */
+	157, /* 60 C */
+	138, /* 65 C */
+	121, /* 70 C */
+	106, /* 75 C */
+	93, /* 80 C */
+	81, /* 85 C */
+	70, /* 90 C */
+	61, /* 95 C */
+	53, /* 100 C */
 };
 
 /*
@@ -46,8 +46,9 @@ static const uint8_t adc_result[] = {
  * to 50C, the temperature curve is roughly linear, so we don't need to include
  * data points in our table.
  */
-#define adc_to_temp(result) (ADC_DISCREET_RANGE_START_TEMP - \
-	(((result) - ADC_DISCREET_RANGE_START_RESULT) * 3 + 16) / 32)
+#define adc_to_temp(result)              \
+	(ADC_DISCREET_RANGE_START_TEMP - \
+	 (((result)-ADC_DISCREET_RANGE_START_RESULT) * 3 + 16) / 32)
 
 /* Convert ADC result (10 bit) to temperature in celsius */
 int ncp15wb_calculate_temp(uint16_t adc)
@@ -72,8 +73,7 @@ int ncp15wb_calculate_temp(uint16_t adc)
 		tail = ARRAY_SIZE(adc_result) - 1;
 		while (head != tail) {
 			mid = (head + tail) / 2;
-			if (adc_result[mid] >= adc &&
-			    adc_result[mid+1] < adc)
+			if (adc_result[mid] >= adc && adc_result[mid + 1] < adc)
 				break;
 			if (adc_result[mid] > adc)
 				head = mid + 1;
@@ -85,7 +85,9 @@ int ncp15wb_calculate_temp(uint16_t adc)
 		if (head != tail) {
 			delta = adc_result[mid] - adc_result[mid + 1];
 			step = ((adc_result[mid] - adc) *
-				ADC_DISCREET_RANGE_STEP + delta / 2) / delta;
+					ADC_DISCREET_RANGE_STEP +
+				delta / 2) /
+			       delta;
 		} else {
 			/* Edge case where adc = max */
 			mid = head;
diff --git a/driver/temp_sensor/tmp006.c b/driver/temp_sensor/tmp006.c
index e4794ccc4a..e3cb62276a 100644
--- a/driver/temp_sensor/tmp006.c
+++ b/driver/temp_sensor/tmp006.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,7 +19,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_THERMAL, outstr)
-#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
 
 /*
  * Alg 0 was what's in the TMP006 User's Guide.  Alg 1 is Alg 0, but with
@@ -30,23 +30,23 @@
 #define ALGORITHM_PARAMS 12
 
 /* Flags for tdata->fail */
-#define FAIL_INIT        BIT(0)  /* Just initialized */
-#define FAIL_POWER       BIT(1)  /* Sensor not powered */
-#define FAIL_I2C         BIT(2)  /* I2C communication error */
-#define FAIL_NOT_READY   BIT(3)  /* Data not ready */
+#define FAIL_INIT BIT(0) /* Just initialized */
+#define FAIL_POWER BIT(1) /* Sensor not powered */
+#define FAIL_I2C BIT(2) /* I2C communication error */
+#define FAIL_NOT_READY BIT(3) /* Data not ready */
 
 /* State and conversion factors to track for each sensor */
 struct tmp006_data_t {
 	/* chip info */
-	int16_t v_raw;		 /* TMP006_REG_VOBJ */
-	int16_t t_raw0;		 /* TMP006_REG_TDIE */
-	int fail;		 /* Fail flags; non-zero if last read failed */
+	int16_t v_raw; /* TMP006_REG_VOBJ */
+	int16_t t_raw0; /* TMP006_REG_TDIE */
+	int fail; /* Fail flags; non-zero if last read failed */
 	/* calibration params */
-	float s0, a1, a2;	 /* Sensitivity factors */
-	float b0, b1, b2;	 /* Self-heating correction */
-	float c2;		 /* Seebeck effect */
-	float d0, d1, ds;	 /* Tdie filter and slope adjustment */
-	float e0, e1;		 /* Tobj output filter */
+	float s0, a1, a2; /* Sensitivity factors */
+	float b0, b1, b2; /* Self-heating correction */
+	float c2; /* Seebeck effect */
+	float d0, d1, ds; /* Tdie filter and slope adjustment */
+	float e0, e1; /* Tobj output filter */
 	/* FIR filter stages */
 	float tdie1, tobj1;
 };
@@ -57,7 +57,7 @@ static const struct tmp006_data_t tmp006_data_default = {
 	.fail = FAIL_INIT,
 
 	/* Alg 0 params from User's Guide */
-	.s0 = 0.0f,				/* zero == "uncalibrated" */
+	.s0 = 0.0f, /* zero == "uncalibrated" */
 	.a1 = 1.75e-3f,
 	.a2 = -1.678e-5f,
 	.b0 = -2.94e-5f,
@@ -75,8 +75,8 @@ static const struct tmp006_data_t tmp006_data_default = {
 
 static int tmp006_has_power(int idx)
 {
-#ifdef CONFIG_TEMP_SENSOR_POWER_GPIO
-	return gpio_get_level(CONFIG_TEMP_SENSOR_POWER_GPIO);
+#ifdef CONFIG_TEMP_SENSOR_POWER
+	return gpio_get_level(GPIO_TEMP_SENSOR_POWER);
 #else
 	return 1;
 #endif
@@ -104,8 +104,7 @@ static void tmp006_poll_sensor(int sensor_id)
 	 * data ready; otherwise, we read garbage data.
 	 */
 	if (tdata->fail & (FAIL_POWER | FAIL_INIT)) {
-		rv = i2c_read16(TMP006_PORT(addr_flags),
-				TMP006_REG(addr_flags),
+		rv = i2c_read16(TMP006_PORT(addr_flags), TMP006_REG(addr_flags),
 				TMP006_REG_CONFIG, &v);
 		if (rv) {
 			tdata->fail |= FAIL_I2C;
@@ -117,16 +116,14 @@ static void tmp006_poll_sensor(int sensor_id)
 		}
 	}
 
-	rv = i2c_read16(TMP006_PORT(addr_flags),
-			TMP006_REG(addr_flags),
+	rv = i2c_read16(TMP006_PORT(addr_flags), TMP006_REG(addr_flags),
 			TMP006_REG_TDIE, &t);
 	if (rv) {
 		tdata->fail |= FAIL_I2C;
 		return;
 	}
 
-	rv = i2c_read16(TMP006_PORT(addr_flags),
-			TMP006_REG(addr_flags),
+	rv = i2c_read16(TMP006_PORT(addr_flags), TMP006_REG(addr_flags),
 			TMP006_REG_VOBJ, &v);
 	if (rv) {
 		tdata->fail |= FAIL_I2C;
@@ -179,8 +176,7 @@ static int tmp006_read_die_temp_k(const struct tmp006_data_t *tdata,
  * This uses Tdie and Vobj and a bunch of magic parameters to calculate the
  * object temperature, Tobj.
  */
-static int tmp006_read_object_temp_k(struct tmp006_data_t *tdata,
-				     int *temp_ptr)
+static int tmp006_read_object_temp_k(struct tmp006_data_t *tdata, int *temp_ptr)
 {
 	float tdie, vobj;
 	float tx, s, vos, vx, fv, tobj, t4;
@@ -251,7 +247,7 @@ int tmp006_get_val(int idx, int *temp_ptr)
 		 * an I2C error.
 		 */
 		return (tdata->fail & FAIL_I2C) ? EC_ERROR_UNKNOWN :
-			EC_ERROR_NOT_POWERED;
+						  EC_ERROR_NOT_POWERED;
 	}
 
 	/* Check the low bit to determine which temperature to read. */
@@ -264,7 +260,7 @@ int tmp006_get_val(int idx, int *temp_ptr)
 /*****************************************************************************/
 /* Host commands */
 
-enum ec_status tmp006_get_calibration(struct host_cmd_handler_args *args)
+static enum ec_status tmp006_get_calibration(struct host_cmd_handler_args *args)
 {
 	const struct ec_params_tmp006_get_calibration *p = args->params;
 	struct ec_response_tmp006_get_calibration_v1 *r1 = args->response;
@@ -277,29 +273,27 @@ enum ec_status tmp006_get_calibration(struct host_cmd_handler_args *args)
 
 	r1->algorithm = ALGORITHM_NUM;
 	r1->num_params = ALGORITHM_PARAMS;
-	r1->val[0]  = tdata->s0;
-	r1->val[1]  = tdata->a1;
-	r1->val[2]  = tdata->a2;
-	r1->val[3]  = tdata->b0;
-	r1->val[4]  = tdata->b1;
-	r1->val[5]  = tdata->b2;
-	r1->val[6]  = tdata->c2;
-	r1->val[7]  = tdata->d0;
-	r1->val[8]  = tdata->d1;
-	r1->val[9]  = tdata->ds;
+	r1->val[0] = tdata->s0;
+	r1->val[1] = tdata->a1;
+	r1->val[2] = tdata->a2;
+	r1->val[3] = tdata->b0;
+	r1->val[4] = tdata->b1;
+	r1->val[5] = tdata->b2;
+	r1->val[6] = tdata->c2;
+	r1->val[7] = tdata->d0;
+	r1->val[8] = tdata->d1;
+	r1->val[9] = tdata->ds;
 	r1->val[10] = tdata->e0;
 	r1->val[11] = tdata->e1;
 
-	args->response_size = sizeof(*r1) +
-		r1->num_params * sizeof(r1->val[0]);
+	args->response_size = sizeof(*r1) + r1->num_params * sizeof(r1->val[0]);
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_TMP006_GET_CALIBRATION,
-		     tmp006_get_calibration,
+DECLARE_HOST_COMMAND(EC_CMD_TMP006_GET_CALIBRATION, tmp006_get_calibration,
 		     EC_VER_MASK(1));
 
-enum ec_status tmp006_set_calibration(struct host_cmd_handler_args *args)
+static enum ec_status tmp006_set_calibration(struct host_cmd_handler_args *args)
 {
 	const struct ec_params_tmp006_set_calibration_v1 *p1 = args->params;
 	struct tmp006_data_t *tdata;
@@ -329,11 +323,10 @@ enum ec_status tmp006_set_calibration(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_TMP006_SET_CALIBRATION,
-		     tmp006_set_calibration,
+DECLARE_HOST_COMMAND(EC_CMD_TMP006_SET_CALIBRATION, tmp006_set_calibration,
 		     EC_VER_MASK(1));
 
-enum ec_status tmp006_get_raw(struct host_cmd_handler_args *args)
+static enum ec_status tmp006_get_raw(struct host_cmd_handler_args *args)
 {
 	const struct ec_params_tmp006_get_raw *p = args->params;
 	struct ec_response_tmp006_get_raw *r = args->response;
@@ -356,9 +349,7 @@ enum ec_status tmp006_get_raw(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_TMP006_GET_RAW,
-		     tmp006_get_raw,
-		     EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_TMP006_GET_RAW, tmp006_get_raw, EC_VER_MASK(0));
 
 /*****************************************************************************/
 /* Console commands */
@@ -375,7 +366,6 @@ static int tmp006_print(int idx)
 	int d;
 	int addr_flags = tmp006_sensors[idx].addr_flags;
 
-
 	ccprintf("Debug data from %s:\n", tmp006_sensors[idx].name);
 
 	if (!tmp006_has_power(idx)) {
@@ -383,41 +373,36 @@ static int tmp006_print(int idx)
 		return EC_ERROR_UNKNOWN;
 	}
 
-	rv = i2c_read16(TMP006_PORT(addr_flags),
-			TMP006_REG(addr_flags),
+	rv = i2c_read16(TMP006_PORT(addr_flags), TMP006_REG(addr_flags),
 			TMP006_REG_MANUFACTURER_ID, &d);
 	if (rv)
 		return rv;
 	ccprintf("  Manufacturer ID: 0x%04x\n", d);
 
-	rv = i2c_read16(TMP006_PORT(addr_flags),
-			TMP006_REG(addr_flags),
+	rv = i2c_read16(TMP006_PORT(addr_flags), TMP006_REG(addr_flags),
 			TMP006_REG_DEVICE_ID, &d);
 	ccprintf("  Device ID:       0x%04x\n", d);
 
-	rv = i2c_read16(TMP006_PORT(addr_flags),
-			TMP006_REG(addr_flags),
+	rv = i2c_read16(TMP006_PORT(addr_flags), TMP006_REG(addr_flags),
 			TMP006_REG_CONFIG, &d);
 	ccprintf("  Config:          0x%04x\n", d);
 
-	rv = i2c_read16(TMP006_PORT(addr_flags),
-			TMP006_REG(addr_flags),
+	rv = i2c_read16(TMP006_PORT(addr_flags), TMP006_REG(addr_flags),
 			TMP006_REG_VOBJ, &vraw);
 
 	v = ((int)vraw * 15625) / 100;
 	ccprintf("  Voltage:         0x%04x = %d nV\n", vraw, v);
 
-	rv = i2c_read16(TMP006_PORT(addr_flags),
-			TMP006_REG(addr_flags),
+	rv = i2c_read16(TMP006_PORT(addr_flags), TMP006_REG(addr_flags),
 			TMP006_REG_TDIE, &traw);
 	t = (int)traw;
-	ccprintf("  Temperature:     0x%04x = %d.%02d C\n",
-		 traw, t / 128, t > 0 ? t % 128 : 128 - (t % 128));
+	ccprintf("  Temperature:     0x%04x = %d.%02d C\n", traw, t / 128,
+		 t > 0 ? t % 128 : 128 - (t % 128));
 
 	return EC_SUCCESS;
 }
 
-static int command_sensor_info(int argc, char **argv)
+static int command_sensor_info(int argc, const char **argv)
 {
 	int i;
 	int rv, rv1;
@@ -442,14 +427,13 @@ static int command_sensor_info(int argc, char **argv)
 
 	return rv1;
 }
-DECLARE_CONSOLE_COMMAND(tmp006, command_sensor_info,
-			"[ <index> ]",
+DECLARE_CONSOLE_COMMAND(tmp006, command_sensor_info, "[ <index> ]",
 			"Print TMP006 sensors");
 #endif
 
 /* Disable the t6cal command until/unless we have FP support in printf */
 #if 0
-static int command_t6cal(int argc, char **argv)
+static int command_t6cal(int argc, const char **argv)
 {
 	struct tmp006_data_t *tdata;
 	char *e;
diff --git a/driver/temp_sensor/tmp006.h b/driver/temp_sensor/tmp006.h
index 594dbc711a..c3409dde59 100644
--- a/driver/temp_sensor/tmp006.h
+++ b/driver/temp_sensor/tmp006.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,11 +9,11 @@
 #define __CROS_EC_TMP006_H
 
 /* Registers within the TMP006 chip */
-#define TMP006_REG_VOBJ            0x00
-#define TMP006_REG_TDIE            0x01
-#define TMP006_REG_CONFIG          0x02
+#define TMP006_REG_VOBJ 0x00
+#define TMP006_REG_TDIE 0x01
+#define TMP006_REG_CONFIG 0x02
 #define TMP006_REG_MANUFACTURER_ID 0xfe
-#define TMP006_REG_DEVICE_ID       0xff
+#define TMP006_REG_DEVICE_ID 0xff
 
 /* I2C address components */
 #define TMP006_ADDR(PORT, REG) ((PORT << 16) + REG)
@@ -22,7 +22,7 @@
 
 struct tmp006_t {
 	const char *name;
-	int addr_flags;	/* I2C address formed by TMP006_ADDR macro. */
+	int addr_flags; /* I2C address formed by TMP006_ADDR macro. */
 };
 
 /* Names and addresses of the sensors we have */
@@ -40,4 +40,4 @@ extern const struct tmp006_t tmp006_sensors[];
  */
 int tmp006_get_val(int idx, int *temp_ptr);
 
-#endif  /* __CROS_EC_TMP006_H */
+#endif /* __CROS_EC_TMP006_H */
diff --git a/driver/temp_sensor/tmp112.c b/driver/temp_sensor/tmp112.c
index 045aca8c9c..267227f6f3 100644
--- a/driver/temp_sensor/tmp112.c
+++ b/driver/temp_sensor/tmp112.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,69 +7,119 @@
 
 #include "common.h"
 #include "console.h"
-#include "tmp112.h"
-#include "i2c.h"
 #include "hooks.h"
+#include "i2c.h"
+#include "math_util.h"
+#include "temp_sensor/tmp112.h"
 #include "util.h"
 
+#ifdef CONFIG_ZEPHYR
+#include "temp_sensor/temp_sensor.h"
+#endif
+
 #define TMP112_RESOLUTION 12
 #define TMP112_SHIFT1 (16 - TMP112_RESOLUTION)
 #define TMP112_SHIFT2 (TMP112_RESOLUTION - 8)
 
-static int temp_val_local;
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
+
+static int temp_mk_local[TMP112_COUNT];
 
-static int raw_read16(const int offset, int *data_ptr)
+static int raw_read16(int sensor, const int offset, int *data_ptr)
 {
-	return i2c_read16(I2C_PORT_THERMAL, TMP112_I2C_ADDR_FLAGS,
-			  offset, data_ptr);
+#ifdef CONFIG_I2C_BUS_MAY_BE_UNPOWERED
+	/*
+	 * Don't try to read if the port is unpowered
+	 */
+	if (!board_is_i2c_port_powered(tmp112_sensors[sensor].i2c_port))
+		return EC_ERROR_NOT_POWERED;
+#endif
+	return i2c_read16(tmp112_sensors[sensor].i2c_port,
+			  tmp112_sensors[sensor].i2c_addr_flags, offset,
+			  data_ptr);
 }
 
-static int raw_write16(const int offset, int data)
+static int raw_write16(int sensor, const int offset, int data)
 {
-	return i2c_write16(I2C_PORT_THERMAL, TMP112_I2C_ADDR_FLAGS,
-			   offset, data);
+#ifdef CONFIG_I2C_BUS_MAY_BE_UNPOWERED
+	/*
+	 * Don't try to write if the port is unpowered
+	 */
+	if (!board_is_i2c_port_powered(tmp112_sensors[sensor].i2c_port))
+		return EC_ERROR_NOT_POWERED;
+#endif
+	return i2c_write16(tmp112_sensors[sensor].i2c_port,
+			   tmp112_sensors[sensor].i2c_addr_flags, offset, data);
 }
 
-static int get_temp(int *temp_ptr)
+static int get_reg_temp(int sensor, int *temp_ptr)
 {
 	int rv;
 	int temp_raw = 0;
 
-	rv = raw_read16(TMP112_REG_TEMP, &temp_raw);
-	if (rv < 0)
+	rv = raw_read16(sensor, TMP112_REG_TEMP, &temp_raw);
+	if (rv)
 		return rv;
 
 	*temp_ptr = (int)(int16_t)temp_raw;
 	return EC_SUCCESS;
 }
 
-static inline int tmp112_reg_to_c(int16_t reg)
+static inline int tmp112_reg_to_mk(int16_t reg)
 {
-	int tmp;
+	int temp_mc;
+
+	temp_mc = (((reg >> TMP112_SHIFT1) * 1000) >> TMP112_SHIFT2);
+
+	return MILLI_CELSIUS_TO_MILLI_KELVIN(temp_mc);
+}
 
-	tmp = (((reg >> TMP112_SHIFT1) * 1000 ) >> TMP112_SHIFT2);
+int tmp112_get_val_k(int idx, int *temp_k_ptr)
+{
+	if (idx >= TMP112_COUNT)
+		return EC_ERROR_INVAL;
 
-	return tmp / 1000;
+	*temp_k_ptr = MILLI_KELVIN_TO_KELVIN(temp_mk_local[idx]);
+	return EC_SUCCESS;
 }
 
-int tmp112_get_val(int idx, int *temp_ptr)
+int tmp112_get_val_mk(int idx, int *temp_mk_ptr)
 {
-	*temp_ptr = temp_val_local;
+	if (idx >= TMP112_COUNT)
+		return EC_ERROR_INVAL;
+
+	*temp_mk_ptr = temp_mk_local[idx];
 	return EC_SUCCESS;
 }
 
+#ifndef CONFIG_ZEPHYR
 static void tmp112_poll(void)
 {
-	int temp_c = 0;
+	int s;
+	int temp_reg = 0;
 
-	if (get_temp(&temp_c) == EC_SUCCESS)
-		temp_val_local = C_TO_K(tmp112_reg_to_c(temp_c));
+	for (s = 0; s < TMP112_COUNT; s++) {
+		if (get_reg_temp(s, &temp_reg) == EC_SUCCESS)
+			temp_mk_local[s] = tmp112_reg_to_mk(temp_reg);
+	}
 }
 DECLARE_HOOK(HOOK_SECOND, tmp112_poll, HOOK_PRIO_TEMP_SENSOR);
+#else
+static void tmp112_update_temperature(int idx)
+{
+	int temp_reg = 0;
+
+	if (idx >= TMP112_COUNT)
+		return;
+
+	if (get_reg_temp(idx, &temp_reg) == EC_SUCCESS)
+		temp_mk_local[idx] = tmp112_reg_to_mk(temp_reg);
+}
+#endif /* CONFIG_ZEPHYR */
 
-static void tmp112_init(void)
+void tmp112_init(void)
 {
-	int tmp;
+	int tmp, s, rv;
 	int set_mask, clr_mask;
 
 	/* 12 bit mode */
@@ -78,7 +128,13 @@ static void tmp112_init(void)
 	/* not oneshot mode */
 	clr_mask = BIT(7);
 
-	raw_read16(TMP112_REG_CONF, &tmp);
-	raw_write16(TMP112_REG_CONF, (tmp & ~clr_mask) | set_mask);
+	for (s = 0; s < TMP112_COUNT; s++) {
+		rv = raw_read16(s, TMP112_REG_CONF, &tmp);
+		if (rv != EC_SUCCESS) {
+			CPRINTS("TMP112-%d: Failed to init (rv %d)", s, rv);
+			continue;
+		}
+		raw_write16(s, TMP112_REG_CONF, (tmp & ~clr_mask) | set_mask);
+	}
 }
 DECLARE_HOOK(HOOK_INIT, tmp112_init, HOOK_PRIO_DEFAULT);
diff --git a/driver/temp_sensor/tmp112.h b/driver/temp_sensor/tmp112.h
deleted file mode 100644
index 35f5909045..0000000000
--- a/driver/temp_sensor/tmp112.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_TMP112_H
-#define __CROS_EC_TMP112_H
-
-#include "i2c.h"
-
-#define TMP112_I2C_ADDR_FLAGS (0x48 | I2C_FLAG_BIG_ENDIAN)
-
-#define TMP112_REG_TEMP	0x00
-#define TMP112_REG_CONF	0x01
-#define TMP112_REG_HYST	0x02
-#define TMP112_REG_MAX	0x03
-
-/**
- * Get the last polled value of a sensor.
- *
- * @param idx		Index to read. (Ignored)
- *
- * @param temp_ptr	Destination for temperature in K.
- *
- * @return EC_SUCCESS if successful, non-zero if error.
- */
-int tmp112_get_val(int idx, int *temp_ptr);
-
-#endif /* __CROS_EC_TMP112_H */
diff --git a/driver/temp_sensor/tmp411.c b/driver/temp_sensor/tmp411.c
index ef22052da8..4f8a08a181 100644
--- a/driver/temp_sensor/tmp411.c
+++ b/driver/temp_sensor/tmp411.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,10 +7,10 @@
 
 #include "common.h"
 #include "console.h"
-#include "tmp411.h"
 #include "gpio.h"
-#include "i2c.h"
 #include "hooks.h"
+#include "i2c.h"
+#include "tmp411.h"
 #include "util.h"
 
 static int temp_val_local;
@@ -24,8 +24,8 @@ static uint8_t is_sensor_shutdown;
  */
 static int has_power(void)
 {
-#ifdef CONFIG_TEMP_SENSOR_POWER_GPIO
-	return gpio_get_level(CONFIG_TEMP_SENSOR_POWER_GPIO);
+#ifdef CONFIG_TEMP_SENSOR_POWER
+	return gpio_get_level(GPIO_TEMP_SENSOR_POWER);
 #else
 	return !is_sensor_shutdown;
 #endif
@@ -139,7 +139,7 @@ int tmp411_set_therm_limit(int channel, int limit_c, int hysteresis)
 		return EC_ERROR_INVAL;
 
 	if (hysteresis > TMP411_HYSTERESIS_HIGH_LIMIT ||
-		hysteresis < TMP411_HYSTERESIS_LOW_LIMIT)
+	    hysteresis < TMP411_HYSTERESIS_LOW_LIMIT)
 		return EC_ERROR_INVAL;
 
 	/* hysteresis must be less than high limit */
@@ -181,17 +181,14 @@ static void tmp411_temp_sensor_poll(void)
 
 	if (get_temp(TMP411_REMOTE1, &temp_c) == EC_SUCCESS)
 		temp_val_remote1 = C_TO_K(temp_c);
-
 }
 DECLARE_HOOK(HOOK_SECOND, tmp411_temp_sensor_poll, HOOK_PRIO_TEMP_SENSOR);
 
 #ifdef CONFIG_CMD_TEMP_SENSOR
-static void print_temps(
-		const char *name,
-		const int tmp411_temp_reg,
-		const int tmp411_therm_limit_reg,
-		const int tmp411_high_limit_reg,
-		const int tmp411_low_limit_reg)
+static void print_temps(const char *name, const int tmp411_temp_reg,
+			const int tmp411_therm_limit_reg,
+			const int tmp411_high_limit_reg,
+			const int tmp411_low_limit_reg)
 {
 	int value;
 
@@ -219,28 +216,24 @@ static int print_status(void)
 {
 	int value;
 
-	print_temps("Local", TMP411_LOCAL,
-		    TMP411_LOCAL_THERM_LIMIT,
-		    TMP411_LOCAL_HIGH_LIMIT_R,
-		    TMP411_LOCAL_LOW_LIMIT_R);
+	print_temps("Local", TMP411_LOCAL, TMP411_LOCAL_THERM_LIMIT,
+		    TMP411_LOCAL_HIGH_LIMIT_R, TMP411_LOCAL_LOW_LIMIT_R);
 
-	print_temps("Remote1", TMP411_REMOTE1,
-		    TMP411_REMOTE1_THERM_LIMIT,
-		    TMP411_REMOTE1_HIGH_LIMIT_R,
-		    TMP411_REMOTE1_LOW_LIMIT_R);
+	print_temps("Remote1", TMP411_REMOTE1, TMP411_REMOTE1_THERM_LIMIT,
+		    TMP411_REMOTE1_HIGH_LIMIT_R, TMP411_REMOTE1_LOW_LIMIT_R);
 
 	ccprintf("\n");
 
 	if (raw_read8(TMP411_STATUS_R, &value) == EC_SUCCESS)
-		ccprintf("STATUS:  %pb\n", BINARY_VALUE(value, 8));
+		ccprintf("STATUS:  0x%x\n", value);
 
 	if (raw_read8(TMP411_CONFIGURATION1_R, &value) == EC_SUCCESS)
-		ccprintf("CONFIG1: %pb\n", BINARY_VALUE(value, 8));
+		ccprintf("CONFIG1: 0x%x\n", value);
 
 	return EC_SUCCESS;
 }
 
-static int command_tmp411(int argc, char **argv)
+static int command_tmp411(int argc, const char **argv)
 {
 	char *command;
 	char *e;
@@ -285,8 +278,7 @@ static int command_tmp411(int argc, char **argv)
 		rv = raw_read8(offset, &data);
 		if (rv < 0)
 			return rv;
-		ccprintf("Byte at offset 0x%02x is %pb\n",
-			 offset, BINARY_VALUE(data, 8));
+		ccprintf("Byte at offset 0x%02x is 0x%x\n", offset, data);
 		return rv;
 	}
 
@@ -309,7 +301,8 @@ static int command_tmp411(int argc, char **argv)
 
 	return rv;
 }
-DECLARE_CONSOLE_COMMAND(tmp411, command_tmp411,
+DECLARE_CONSOLE_COMMAND(
+	tmp411, command_tmp411,
 	"[settemp|setbyte <offset> <value>] or [getbyte <offset>] or"
 	"[power <on|off>]. "
 	"Temps in Celsius.",
@@ -318,13 +311,12 @@ DECLARE_CONSOLE_COMMAND(tmp411, command_tmp411,
 
 int tmp411_set_power(enum tmp411_power_state power_on)
 {
-#ifndef CONFIG_TEMP_SENSOR_POWER_GPIO
+#ifndef CONFIG_TEMP_SENSOR_POWER
 	uint8_t shutdown = (power_on == TMP411_POWER_OFF) ? 1 : 0;
 
 	return tmp411_shutdown(shutdown);
 #else
-	gpio_set_level(CONFIG_TEMP_SENSOR_POWER_GPIO, power_on);
+	gpio_set_level(GPIO_TEMP_SENSOR_POWER, power_on);
 	return EC_SUCCESS;
 #endif
 }
-
diff --git a/driver/temp_sensor/tmp411.h b/driver/temp_sensor/tmp411.h
index ef1b23278c..0716a2846d 100644
--- a/driver/temp_sensor/tmp411.h
+++ b/driver/temp_sensor/tmp411.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,83 +8,83 @@
 #ifndef __CROS_EC_TMP411_H
 #define __CROS_EC_TMP411_H
 
-#define TMP411_I2C_ADDR_FLAGS		0x4C
+#define TMP411_I2C_ADDR_FLAGS 0x4C
 
-#define TMP411_IDX_LOCAL	0
-#define TMP411_IDX_REMOTE1	1
-#define TMP411_IDX_REMOTE2	2
+#define TMP411_IDX_LOCAL 0
+#define TMP411_IDX_REMOTE1 1
+#define TMP411_IDX_REMOTE2 2
 
 /* Chip-specific registers */
-#define TMP411_LOCAL			0x00
-#define TMP411_REMOTE1			0x01
-#define TMP411_STATUS_R			0x02
-#define TMP411_CONFIGURATION1_R		0x03
-#define TMP411_CONVERSION_RATE_R	0x04
-#define TMP411_LOCAL_HIGH_LIMIT_R	0x05
-#define TMP411_LOCAL_LOW_LIMIT_R	0x06
-#define TMP411_REMOTE1_HIGH_LIMIT_R	0x07
-#define TMP411_REMOTE1_LOW_LIMIT_R	0x08
-#define TMP411_CONFIGURATION1_W		0x09
-#define TMP411_CONVERSION_RATE_W	0x0a
-#define TMP411_LOCAL_HIGH_LIMIT_W	0x0b
-#define TMP411_LOCAL_LOW_LIMIT_W	0x0c
-#define TMP411_REMOTE1_HIGH_LIMIT_W	0x0d
-#define TMP411_REMOTE1_LOW_LIMIT_W	0x0e
-#define TMP411_ONESHOT			0x0f
-#define TMP411_REMOTE1_EXTD		0x10
-#define TMP411_REMOTE1_HIGH_LIMIT_EXTD	0x13
-#define TMP411_REMOTE1_LOW_LIMIT_EXTD	0x14
-#define TMP411_REMOTE2_HIGH_LIMIT_R	0x15
-#define TMP411_REMOTE2_HIGH_LIMIT_W	0x15
-#define TMP411_REMOTE2_LOW_LIMIT_R	0x16
-#define TMP411_REMOTE2_LOW_LIMIT_W	0x16
-#define TMP411_REMOTE2_HIGH_LIMIT_EXTD	0x17
-#define TMP411_REMOTE2_LOW_LIMIT_EXTD	0x18
-#define TMP411_REMOTE1_THERM_LIMIT	0x19
-#define TMP411_REMOTE2_THERM_LIMIT	0x1a
-#define TMP411_STATUS_FAULT		0x1b
-#define TMP411_CHANNEL_MASK		0x1f
-#define TMP411_LOCAL_THERM_LIMIT	0x20
-#define TMP411_THERM_HYSTERESIS		0x21
-#define TMP411_CONSECUTIVE_ALERT	0x22
-#define TMP411_REMOTE2			0x23
-#define TMP411_REMOTE2_EXTD		0x24
-#define TMP411_BETA_RANGE_CH1		0x25
-#define TMP411_BETA_RANGE_CH2		0x26
-#define TMP411_NFACTOR_REMOTE1		0x27
-#define TMP411_NFACTOR_REMOTE2		0x28
-#define TMP411_LOCAL_EXTD		0x29
-#define TMP411_STATUS_LIMIT_HIGH	0x35
-#define TMP411_STATUS_LIMIT_LOW		0x36
-#define TMP411_STATUS_THERM		0x37
-#define TMP411_RESET_W			0xfc
-#define TMP411_MANUFACTURER_ID		0xfe
-#define TMP411_DEVICE_ID		0xff
+#define TMP411_LOCAL 0x00
+#define TMP411_REMOTE1 0x01
+#define TMP411_STATUS_R 0x02
+#define TMP411_CONFIGURATION1_R 0x03
+#define TMP411_CONVERSION_RATE_R 0x04
+#define TMP411_LOCAL_HIGH_LIMIT_R 0x05
+#define TMP411_LOCAL_LOW_LIMIT_R 0x06
+#define TMP411_REMOTE1_HIGH_LIMIT_R 0x07
+#define TMP411_REMOTE1_LOW_LIMIT_R 0x08
+#define TMP411_CONFIGURATION1_W 0x09
+#define TMP411_CONVERSION_RATE_W 0x0a
+#define TMP411_LOCAL_HIGH_LIMIT_W 0x0b
+#define TMP411_LOCAL_LOW_LIMIT_W 0x0c
+#define TMP411_REMOTE1_HIGH_LIMIT_W 0x0d
+#define TMP411_REMOTE1_LOW_LIMIT_W 0x0e
+#define TMP411_ONESHOT 0x0f
+#define TMP411_REMOTE1_EXTD 0x10
+#define TMP411_REMOTE1_HIGH_LIMIT_EXTD 0x13
+#define TMP411_REMOTE1_LOW_LIMIT_EXTD 0x14
+#define TMP411_REMOTE2_HIGH_LIMIT_R 0x15
+#define TMP411_REMOTE2_HIGH_LIMIT_W 0x15
+#define TMP411_REMOTE2_LOW_LIMIT_R 0x16
+#define TMP411_REMOTE2_LOW_LIMIT_W 0x16
+#define TMP411_REMOTE2_HIGH_LIMIT_EXTD 0x17
+#define TMP411_REMOTE2_LOW_LIMIT_EXTD 0x18
+#define TMP411_REMOTE1_THERM_LIMIT 0x19
+#define TMP411_REMOTE2_THERM_LIMIT 0x1a
+#define TMP411_STATUS_FAULT 0x1b
+#define TMP411_CHANNEL_MASK 0x1f
+#define TMP411_LOCAL_THERM_LIMIT 0x20
+#define TMP411_THERM_HYSTERESIS 0x21
+#define TMP411_CONSECUTIVE_ALERT 0x22
+#define TMP411_REMOTE2 0x23
+#define TMP411_REMOTE2_EXTD 0x24
+#define TMP411_BETA_RANGE_CH1 0x25
+#define TMP411_BETA_RANGE_CH2 0x26
+#define TMP411_NFACTOR_REMOTE1 0x27
+#define TMP411_NFACTOR_REMOTE2 0x28
+#define TMP411_LOCAL_EXTD 0x29
+#define TMP411_STATUS_LIMIT_HIGH 0x35
+#define TMP411_STATUS_LIMIT_LOW 0x36
+#define TMP411_STATUS_THERM 0x37
+#define TMP411_RESET_W 0xfc
+#define TMP411_MANUFACTURER_ID 0xfe
+#define TMP411_DEVICE_ID 0xff
 
-#define TMP411A_DEVICE_ID_VAL		0x12
-#define TMP411B_DEVICE_ID_VAL		0x13
-#define TMP411C_DEVICE_ID_VAL		0x10
-#define TMP411d_DEVICE_ID_VAL		0x12
+#define TMP411A_DEVICE_ID_VAL 0x12
+#define TMP411B_DEVICE_ID_VAL 0x13
+#define TMP411C_DEVICE_ID_VAL 0x10
+#define TMP411d_DEVICE_ID_VAL 0x12
 
 /* Config register bits */
-#define TMP411_CONFIG1_TEMP_RANGE	BIT(2)
+#define TMP411_CONFIG1_TEMP_RANGE BIT(2)
 /* TMP411_CONFIG1_MODE bit is use to enable THERM mode */
-#define TMP411_CONFIG1_MODE		BIT(5)
-#define TMP411_CONFIG1_RUN_L		BIT(6)
-#define TMP411_CONFIG1_ALERT_MASK_L	BIT(7)
+#define TMP411_CONFIG1_MODE BIT(5)
+#define TMP411_CONFIG1_RUN_L BIT(6)
+#define TMP411_CONFIG1_ALERT_MASK_L BIT(7)
 
 /* Status register bits */
-#define TMP411_STATUS_TEMP_THERM_ALARM	BIT(1)
-#define TMP411_STATUS_OPEN		BIT(2)
-#define TMP411_STATUS_TEMP_LOW_ALARM	BIT(3)
-#define TMP411_STATUS_TEMP_HIGH_ALARM	BIT(4)
-#define TMP411_STATUS_LOCAL_TEMP_LOW_ALARM	BIT(5)
-#define TMP411_STATUS_LOCAL_TEMP_HIGH_ALARM	BIT(6)
-#define TMP411_STATUS_BUSY		BIT(7)
+#define TMP411_STATUS_TEMP_THERM_ALARM BIT(1)
+#define TMP411_STATUS_OPEN BIT(2)
+#define TMP411_STATUS_TEMP_LOW_ALARM BIT(3)
+#define TMP411_STATUS_TEMP_HIGH_ALARM BIT(4)
+#define TMP411_STATUS_LOCAL_TEMP_LOW_ALARM BIT(5)
+#define TMP411_STATUS_LOCAL_TEMP_HIGH_ALARM BIT(6)
+#define TMP411_STATUS_BUSY BIT(7)
 
 /* Limits */
-#define TMP411_HYSTERESIS_HIGH_LIMIT	255
-#define TMP411_HYSTERESIS_LOW_LIMIT	0
+#define TMP411_HYSTERESIS_HIGH_LIMIT 255
+#define TMP411_HYSTERESIS_LOW_LIMIT 0
 
 enum tmp411_power_state {
 	TMP411_POWER_OFF = 0,
diff --git a/driver/temp_sensor/tmp432.c b/driver/temp_sensor/tmp432.c
index 6260678dcd..581e33b979 100644
--- a/driver/temp_sensor/tmp432.c
+++ b/driver/temp_sensor/tmp432.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,19 +7,19 @@
 
 #include "common.h"
 #include "console.h"
-#include "tmp432.h"
 #include "gpio.h"
-#include "i2c.h"
 #include "hooks.h"
+#include "i2c.h"
+#include "tmp432.h"
 #include "util.h"
 
 static int temp_val_local;
 static int temp_val_remote1;
 static int temp_val_remote2;
-#ifndef CONFIG_TEMP_SENSOR_POWER_GPIO
+#ifndef CONFIG_TEMP_SENSOR_POWER
 static uint8_t is_sensor_shutdown;
 #endif
-static int fake_temp[TMP432_IDX_COUNT] = {-1, -1, -1};
+static int fake_temp[TMP432_IDX_COUNT] = { -1, -1, -1 };
 
 /**
  * Determine whether the sensor is powered.
@@ -28,8 +28,8 @@ static int fake_temp[TMP432_IDX_COUNT] = {-1, -1, -1};
  */
 static int has_power(void)
 {
-#ifdef CONFIG_TEMP_SENSOR_POWER_GPIO
-	return gpio_get_level(CONFIG_TEMP_SENSOR_POWER_GPIO);
+#ifdef CONFIG_TEMP_SENSOR_POWER
+	return gpio_get_level(GPIO_TEMP_SENSOR_POWER);
 #else
 	return !is_sensor_shutdown;
 #endif
@@ -37,14 +37,14 @@ static int has_power(void)
 
 static int raw_read8(const int offset, int *data_ptr)
 {
-	return i2c_read8(I2C_PORT_THERMAL, TMP432_I2C_ADDR_FLAGS,
-			 offset, data_ptr);
+	return i2c_read8(I2C_PORT_THERMAL, TMP432_I2C_ADDR_FLAGS, offset,
+			 data_ptr);
 }
 
 static int raw_write8(const int offset, int data)
 {
-	return i2c_write8(I2C_PORT_THERMAL, TMP432_I2C_ADDR_FLAGS,
-			  offset, data);
+	return i2c_write8(I2C_PORT_THERMAL, TMP432_I2C_ADDR_FLAGS, offset,
+			  data);
 }
 
 static int get_temp(const int offset, int *temp_ptr)
@@ -92,7 +92,7 @@ int tmp432_get_val(int idx, int *temp_ptr)
 	return EC_SUCCESS;
 }
 
-#ifndef CONFIG_TEMP_SENSOR_POWER_GPIO
+#ifndef CONFIG_TEMP_SENSOR_POWER
 static int tmp432_shutdown(uint8_t want_shutdown)
 {
 	int ret, value;
@@ -150,7 +150,7 @@ int tmp432_set_therm_limit(int channel, int limit_c, int hysteresis)
 		return EC_ERROR_INVAL;
 
 	if (hysteresis > TMP432_HYSTERESIS_HIGH_LIMIT ||
-		hysteresis < TMP432_HYSTERESIS_LOW_LIMIT)
+	    hysteresis < TMP432_HYSTERESIS_LOW_LIMIT)
 		return EC_ERROR_INVAL;
 
 	/* hysteresis must be less than high limit */
@@ -228,12 +228,10 @@ static int tmp432_set_fake_temp(int index, int degree_c)
 	return EC_SUCCESS;
 }
 
-static void print_temps(
-		const char *name,
-		const int tmp432_temp_reg,
-		const int tmp432_therm_limit_reg,
-		const int tmp432_high_limit_reg,
-		const int tmp432_low_limit_reg)
+static void print_temps(const char *name, const int tmp432_temp_reg,
+			const int tmp432_therm_limit_reg,
+			const int tmp432_high_limit_reg,
+			const int tmp432_low_limit_reg)
 {
 	int value;
 
@@ -261,20 +259,14 @@ static int print_status(void)
 {
 	int value, i;
 
-	print_temps("Local", TMP432_LOCAL,
-		    TMP432_LOCAL_THERM_LIMIT,
-		    TMP432_LOCAL_HIGH_LIMIT_R,
-		    TMP432_LOCAL_LOW_LIMIT_R);
+	print_temps("Local", TMP432_LOCAL, TMP432_LOCAL_THERM_LIMIT,
+		    TMP432_LOCAL_HIGH_LIMIT_R, TMP432_LOCAL_LOW_LIMIT_R);
 
-	print_temps("Remote1", TMP432_REMOTE1,
-		    TMP432_REMOTE1_THERM_LIMIT,
-		    TMP432_REMOTE1_HIGH_LIMIT_R,
-		    TMP432_REMOTE1_LOW_LIMIT_R);
+	print_temps("Remote1", TMP432_REMOTE1, TMP432_REMOTE1_THERM_LIMIT,
+		    TMP432_REMOTE1_HIGH_LIMIT_R, TMP432_REMOTE1_LOW_LIMIT_R);
 
-	print_temps("Remote2", TMP432_REMOTE2,
-		    TMP432_REMOTE2_THERM_LIMIT,
-		    TMP432_REMOTE2_HIGH_LIMIT_R,
-		    TMP432_REMOTE2_LOW_LIMIT_R);
+	print_temps("Remote2", TMP432_REMOTE2, TMP432_REMOTE2_THERM_LIMIT,
+		    TMP432_REMOTE2_HIGH_LIMIT_R, TMP432_REMOTE2_LOW_LIMIT_R);
 
 	ccprintf("\n");
 
@@ -294,22 +286,22 @@ static int print_status(void)
 	ccprintf("\n");
 
 	if (raw_read8(TMP432_STATUS, &value) == EC_SUCCESS)
-		ccprintf("STATUS:  %pb\n", BINARY_VALUE(value, 8));
+		ccprintf("STATUS:  0x%x\n", value);
 
 	if (raw_read8(TMP432_CONFIGURATION1_R, &value) == EC_SUCCESS)
-		ccprintf("CONFIG1: %pb\n", BINARY_VALUE(value, 8));
+		ccprintf("CONFIG1: 0x%x\n", value);
 
 	if (raw_read8(TMP432_CONFIGURATION2_R, &value) == EC_SUCCESS)
-		ccprintf("CONFIG2: %pb\n", BINARY_VALUE(value, 8));
+		ccprintf("CONFIG2: 0x%x\n", value);
 
 	return EC_SUCCESS;
 }
 
-static int command_tmp432(int argc, char **argv)
+static int command_tmp432(int argc, const char **argv)
 {
-	char *command;
+	const char *command;
 	char *e;
-	char *power;
+	const char *power;
 	int data;
 	int offset;
 	int rv;
@@ -321,8 +313,7 @@ static int command_tmp432(int argc, char **argv)
 			rv = tmp432_set_power(TMP432_POWER_ON);
 			if (!rv)
 				print_status();
-		}
-		else if (!strncasecmp(power, "off", sizeof("off")))
+		} else if (!strncasecmp(power, "off", sizeof("off")))
 			rv = tmp432_set_power(TMP432_POWER_OFF);
 		else
 			return EC_ERROR_PARAM2;
@@ -351,8 +342,7 @@ static int command_tmp432(int argc, char **argv)
 		rv = raw_read8(offset, &data);
 		if (rv < 0)
 			return rv;
-		ccprintf("Byte at offset 0x%02x is %pb\n",
-			 offset, BINARY_VALUE(data, 8));
+		ccprintf("Byte at offset 0x%02x is 0x%x\n", offset, data);
 		return rv;
 	}
 
@@ -379,7 +369,8 @@ static int command_tmp432(int argc, char **argv)
 
 	return rv;
 }
-DECLARE_CONSOLE_COMMAND(tmp432, command_tmp432,
+DECLARE_CONSOLE_COMMAND(
+	tmp432, command_tmp432,
 	"[settemp|setbyte <offset> <value>] or [getbyte <offset>] or"
 	"[fake <index> <value>] or [power <on|off>]. "
 	"Temps in Celsius.",
@@ -388,12 +379,11 @@ DECLARE_CONSOLE_COMMAND(tmp432, command_tmp432,
 
 int tmp432_set_power(enum tmp432_power_state power_on)
 {
-#ifndef CONFIG_TEMP_SENSOR_POWER_GPIO
+#ifndef CONFIG_TEMP_SENSOR_POWER
 	uint8_t shutdown = (power_on == TMP432_POWER_OFF) ? 1 : 0;
 	return tmp432_shutdown(shutdown);
 #else
-	gpio_set_level(CONFIG_TEMP_SENSOR_POWER_GPIO, power_on);
+	gpio_set_level(GPIO_TEMP_SENSOR_POWER, power_on);
 	return EC_SUCCESS;
 #endif
 }
-
diff --git a/driver/temp_sensor/tmp432.h b/driver/temp_sensor/tmp432.h
index e58e39a4a0..d4c99f1129 100644
--- a/driver/temp_sensor/tmp432.h
+++ b/driver/temp_sensor/tmp432.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,85 +8,85 @@
 #ifndef __CROS_EC_TMP432_H
 #define __CROS_EC_TMP432_H
 
-#define TMP432_I2C_ADDR_FLAGS		0x4C
+#define TMP432_I2C_ADDR_FLAGS 0x4C
 
-#define TMP432_IDX_LOCAL	0
-#define TMP432_IDX_REMOTE1	1
-#define TMP432_IDX_REMOTE2	2
-#define TMP432_IDX_COUNT	3
+#define TMP432_IDX_LOCAL 0
+#define TMP432_IDX_REMOTE1 1
+#define TMP432_IDX_REMOTE2 2
+#define TMP432_IDX_COUNT 3
 
 /* Chip-specific registers */
-#define TMP432_LOCAL			0x00
-#define TMP432_REMOTE1			0x01
-#define TMP432_STATUS			0x02
-#define TMP432_CONFIGURATION1_R		0x03
-#define TMP432_CONVERSION_RATE_R	0x04
-#define TMP432_LOCAL_HIGH_LIMIT_R	0x05
-#define TMP432_LOCAL_LOW_LIMIT_R	0x06
-#define TMP432_REMOTE1_HIGH_LIMIT_R	0x07
-#define TMP432_REMOTE1_LOW_LIMIT_R	0x08
-#define TMP432_CONFIGURATION1_W		0x09
-#define TMP432_CONVERSION_RATE_W	0x0a
-#define TMP432_LOCAL_HIGH_LIMIT_W	0x0b
-#define TMP432_LOCAL_LOW_LIMIT_W	0x0c
-#define TMP432_REMOTE1_HIGH_LIMIT_W	0x0d
-#define TMP432_REMOTE1_LOW_LIMIT_W	0x0e
-#define TMP432_ONESHOT			0x0f
-#define TMP432_REMOTE1_EXTD		0x10
-#define TMP432_REMOTE1_HIGH_LIMIT_EXTD	0x13
-#define TMP432_REMOTE1_LOW_LIMIT_EXTD	0x14
-#define TMP432_REMOTE2_HIGH_LIMIT_R	0x15
-#define TMP432_REMOTE2_HIGH_LIMIT_W	0x15
-#define TMP432_REMOTE2_LOW_LIMIT_R	0x16
-#define TMP432_REMOTE2_LOW_LIMIT_W	0x16
-#define TMP432_REMOTE2_HIGH_LIMIT_EXTD	0x17
-#define TMP432_REMOTE2_LOW_LIMIT_EXTD	0x18
-#define TMP432_REMOTE1_THERM_LIMIT	0x19
-#define TMP432_REMOTE2_THERM_LIMIT	0x1a
-#define TMP432_STATUS_FAULT		0x1b
-#define TMP432_CHANNEL_MASK		0x1f
-#define TMP432_LOCAL_THERM_LIMIT	0x20
-#define TMP432_THERM_HYSTERESIS		0x21
-#define TMP432_CONSECUTIVE_ALERT	0x22
-#define TMP432_REMOTE2			0x23
-#define TMP432_REMOTE2_EXTD		0x24
-#define TMP432_BETA_RANGE_CH1		0x25
-#define TMP432_BETA_RANGE_CH2		0x26
-#define TMP432_NFACTOR_REMOTE1		0x27
-#define TMP432_NFACTOR_REMOTE2		0x28
-#define TMP432_LOCAL_EXTD		0x29
-#define TMP432_STATUS_LIMIT_HIGH	0x35
-#define TMP432_STATUS_LIMIT_LOW		0x36
-#define TMP432_STATUS_THERM		0x37
-#define TMP432_LOCAL_HIGH_LIMIT_EXTD	0x3d
-#define TMP432_LOCAL_LOW_LIMIT_EXTD	0x3e
-#define TMP432_CONFIGURATION2_R		0x3f
-#define TMP432_CONFIGURATION2_W		0x3f
-#define TMP432_RESET_W			0xfc
-#define TMP432_DEVICE_ID		0xfd
-#define TMP432_MANUFACTURER_ID		0xfe
+#define TMP432_LOCAL 0x00
+#define TMP432_REMOTE1 0x01
+#define TMP432_STATUS 0x02
+#define TMP432_CONFIGURATION1_R 0x03
+#define TMP432_CONVERSION_RATE_R 0x04
+#define TMP432_LOCAL_HIGH_LIMIT_R 0x05
+#define TMP432_LOCAL_LOW_LIMIT_R 0x06
+#define TMP432_REMOTE1_HIGH_LIMIT_R 0x07
+#define TMP432_REMOTE1_LOW_LIMIT_R 0x08
+#define TMP432_CONFIGURATION1_W 0x09
+#define TMP432_CONVERSION_RATE_W 0x0a
+#define TMP432_LOCAL_HIGH_LIMIT_W 0x0b
+#define TMP432_LOCAL_LOW_LIMIT_W 0x0c
+#define TMP432_REMOTE1_HIGH_LIMIT_W 0x0d
+#define TMP432_REMOTE1_LOW_LIMIT_W 0x0e
+#define TMP432_ONESHOT 0x0f
+#define TMP432_REMOTE1_EXTD 0x10
+#define TMP432_REMOTE1_HIGH_LIMIT_EXTD 0x13
+#define TMP432_REMOTE1_LOW_LIMIT_EXTD 0x14
+#define TMP432_REMOTE2_HIGH_LIMIT_R 0x15
+#define TMP432_REMOTE2_HIGH_LIMIT_W 0x15
+#define TMP432_REMOTE2_LOW_LIMIT_R 0x16
+#define TMP432_REMOTE2_LOW_LIMIT_W 0x16
+#define TMP432_REMOTE2_HIGH_LIMIT_EXTD 0x17
+#define TMP432_REMOTE2_LOW_LIMIT_EXTD 0x18
+#define TMP432_REMOTE1_THERM_LIMIT 0x19
+#define TMP432_REMOTE2_THERM_LIMIT 0x1a
+#define TMP432_STATUS_FAULT 0x1b
+#define TMP432_CHANNEL_MASK 0x1f
+#define TMP432_LOCAL_THERM_LIMIT 0x20
+#define TMP432_THERM_HYSTERESIS 0x21
+#define TMP432_CONSECUTIVE_ALERT 0x22
+#define TMP432_REMOTE2 0x23
+#define TMP432_REMOTE2_EXTD 0x24
+#define TMP432_BETA_RANGE_CH1 0x25
+#define TMP432_BETA_RANGE_CH2 0x26
+#define TMP432_NFACTOR_REMOTE1 0x27
+#define TMP432_NFACTOR_REMOTE2 0x28
+#define TMP432_LOCAL_EXTD 0x29
+#define TMP432_STATUS_LIMIT_HIGH 0x35
+#define TMP432_STATUS_LIMIT_LOW 0x36
+#define TMP432_STATUS_THERM 0x37
+#define TMP432_LOCAL_HIGH_LIMIT_EXTD 0x3d
+#define TMP432_LOCAL_LOW_LIMIT_EXTD 0x3e
+#define TMP432_CONFIGURATION2_R 0x3f
+#define TMP432_CONFIGURATION2_W 0x3f
+#define TMP432_RESET_W 0xfc
+#define TMP432_DEVICE_ID 0xfd
+#define TMP432_MANUFACTURER_ID 0xfe
 
 /* Config register bits */
-#define TMP432_CONFIG1_TEMP_RANGE	BIT(2)
+#define TMP432_CONFIG1_TEMP_RANGE BIT(2)
 /* TMP432_CONFIG1_MODE bit is use to enable THERM mode */
-#define TMP432_CONFIG1_MODE		BIT(5)
-#define TMP432_CONFIG1_RUN_L		BIT(6)
-#define TMP432_CONFIG1_ALERT_MASK_L	BIT(7)
-#define TMP432_CONFIG2_RESISTANCE_CORRECTION	BIT(2)
-#define TMP432_CONFIG2_LOCAL_ENABLE	BIT(3)
-#define TMP432_CONFIG2_REMOTE1_ENABLE	BIT(4)
-#define TMP432_CONFIG2_REMOTE2_ENABLE	BIT(5)
+#define TMP432_CONFIG1_MODE BIT(5)
+#define TMP432_CONFIG1_RUN_L BIT(6)
+#define TMP432_CONFIG1_ALERT_MASK_L BIT(7)
+#define TMP432_CONFIG2_RESISTANCE_CORRECTION BIT(2)
+#define TMP432_CONFIG2_LOCAL_ENABLE BIT(3)
+#define TMP432_CONFIG2_REMOTE1_ENABLE BIT(4)
+#define TMP432_CONFIG2_REMOTE2_ENABLE BIT(5)
 
 /* Status register bits */
-#define TMP432_STATUS_TEMP_THERM_ALARM	BIT(1)
-#define TMP432_STATUS_OPEN		BIT(2)
-#define TMP432_STATUS_TEMP_LOW_ALARM	BIT(3)
-#define TMP432_STATUS_TEMP_HIGH_ALARM	BIT(4)
-#define TMP432_STATUS_BUSY		BIT(7)
+#define TMP432_STATUS_TEMP_THERM_ALARM BIT(1)
+#define TMP432_STATUS_OPEN BIT(2)
+#define TMP432_STATUS_TEMP_LOW_ALARM BIT(3)
+#define TMP432_STATUS_TEMP_HIGH_ALARM BIT(4)
+#define TMP432_STATUS_BUSY BIT(7)
 
 /* Limintaions */
-#define TMP432_HYSTERESIS_HIGH_LIMIT	255
-#define TMP432_HYSTERESIS_LOW_LIMIT	0
+#define TMP432_HYSTERESIS_HIGH_LIMIT 255
+#define TMP432_HYSTERESIS_LOW_LIMIT 0
 
 enum tmp432_power_state {
 	TMP432_POWER_OFF = 0,
diff --git a/driver/temp_sensor/tmp468.c b/driver/temp_sensor/tmp468.c
index 46e77ca696..3bfaeeedbb 100644
--- a/driver/temp_sensor/tmp468.c
+++ b/driver/temp_sensor/tmp468.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,17 +7,16 @@
 
 #include "common.h"
 #include "console.h"
-#include "tmp432.h"
 #include "gpio.h"
-#include "i2c.h"
 #include "hooks.h"
-#include "util.h"
-
+#include "i2c.h"
+#include "tmp432.h"
 #include "tmp468.h"
+#include "util.h"
 
-
-static int fake_temp[TMP468_CHANNEL_COUNT] = {-1, -1, -1, -1, -1, -1, -1 , -1, -1};
-static int temp_val[TMP468_CHANNEL_COUNT]  = {0, 0, 0, 0, 0, 0, 0 , 0, 0};
+static int fake_temp[TMP468_CHANNEL_COUNT] = { -1, -1, -1, -1, -1,
+					       -1, -1, -1, -1 };
+static int temp_val[TMP468_CHANNEL_COUNT] = { 0, 0, 0, 0, 0, 0, 0, 0, 0 };
 static uint8_t is_sensor_shutdown;
 
 static int has_power(void)
@@ -27,14 +26,14 @@ static int has_power(void)
 
 static int raw_read16(const int offset, int *data_ptr)
 {
-	return i2c_read16(I2C_PORT_THERMAL, TMP468_I2C_ADDR_FLAGS,
-			  offset, data_ptr);
+	return i2c_read16(I2C_PORT_THERMAL, TMP468_I2C_ADDR_FLAGS, offset,
+			  data_ptr);
 }
 
 static int raw_write16(const int offset, int data_ptr)
 {
-	return i2c_write16(I2C_PORT_THERMAL, TMP468_I2C_ADDR_FLAGS,
-			   offset, data_ptr);
+	return i2c_write16(I2C_PORT_THERMAL, TMP468_I2C_ADDR_FLAGS, offset,
+			   data_ptr);
 }
 
 static int tmp468_shutdown(uint8_t want_shutdown)
@@ -64,7 +63,7 @@ static int tmp468_shutdown(uint8_t want_shutdown)
 
 int tmp468_get_val(int idx, int *temp_ptr)
 {
-	if(!has_power())
+	if (!has_power())
 		return EC_ERROR_NOT_POWERED;
 
 	if (idx < TMP468_CHANNEL_COUNT) {
diff --git a/driver/temp_sensor/tmp468.h b/driver/temp_sensor/tmp468.h
index 59fbd20477..3a2c154066 100644
--- a/driver/temp_sensor/tmp468.h
+++ b/driver/temp_sensor/tmp468.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,73 +11,73 @@
 #define TMP468_I2C_ADDR_FLAGS (0x48 | I2C_FLAG_BIG_ENDIAN)
 #define TMP468_SHIFT1 7
 
-#define TMP468_LOCAL			0x00
-#define TMP468_REMOTE1			0x01
-#define TMP468_REMOTE2			0x02
-#define TMP468_REMOTE3			0x03
-#define TMP468_REMOTE4			0x04
-#define TMP468_REMOTE5			0x05
-#define TMP468_REMOTE6			0x06
-#define TMP468_REMOTE7			0x07
-#define TMP468_REMOTE8			0x08
-
-#define TMP468_SRST			0x20
-#define TMP468_THERM			0x21
-#define TMP468_THERM2			0x22
-#define TMP468_ROPEN			0x23
-
-#define TMP468_CONFIGURATION		0x30
-#define TMP468_THERM_HYST		0x38
-
-#define TMP468_LOCAL_LOW_LIMIT		0x39
-#define TMP468_LOCAL_HIGH_LIMT		0x3a
-
-#define TMP468_REMOTE1_OFFSET		0x40
-#define TMP468_REMOTE1_NFACTOR		0x41
-#define TMP468_REMOTE1_LOW_LIMIT	0x41
-#define TMP468_REMOTE1_HIGH_LIMIT	0x42
-
-#define TMP468_REMOTE2_OFFSET		0x48
-#define TMP468_REMOTE2_NFACTOR		0x49
-#define TMP468_REMOTE2_LOW_LIMIT	0x4a
-#define TMP468_REMOTE2_HIGH_LIMIT	0x4b
-
-#define TMP468_REMOTE3_OFFSET		0x50
-#define TMP468_REMOTE3_NFACTOR		0x51
-#define TMP468_REMOTE3_LOW_LIMIT	0x52
-#define TMP468_REMOTE3_HIGH_LIMIT	0x53
-
-#define TMP468_REMOTE4_OFFSET		0x58
-#define TMP468_REMOTE4_NFACTOR		0x59
-#define TMP468_REMOTE4_LOW_LIMIT	0x59
-#define TMP468_REMOTE4_HIGH_LIMIT	0x5a
-
-#define TMP468_REMOTE5_OFFSET		0x60
-#define TMP468_REMOTE5_NFACTOR		0x61
-#define TMP468_REMOTE5_LOW_LIMIT	0x62
-#define TMP468_REMOTE5_HIGH_LIMIT	0x63
-
-#define TMP468_REMOTE6_OFFSET		0x68
-#define TMP468_REMOTE6_NFACTOR		0x69
-#define TMP468_REMOTE6_LOW_LIMIT	0x6a
-#define TMP468_REMOTE6_HIGH_LIMIT	0x6b
-
-#define TMP468_REMOTE7_OFFSET		0x70
-#define TMP468_REMOTE7_NFACTOR		0x71
-#define TMP468_REMOTE7_LOW_LIMIT	0x72
-#define TMP468_REMOTE7_HIGH_LIMIT	0x73
-
-#define TMP468_REMOTE8_OFFSET		0x78
-#define TMP468_REMOTE8_NFACTOR		0x79
-#define TMP468_REMOTE8_LOW_LIMIT	0x7a
-#define TMP468_REMOTE8_HIGH_LIMIT	0x7b
-
-#define TMP468_LOCK			0xc4
-
-#define TMP468_DEVICE_ID		0xfd
-#define TMP468_MANUFACTURER_ID		0xfe
-
-#define TMP468_SHUTDOWN			BIT(5)
+#define TMP468_LOCAL 0x00
+#define TMP468_REMOTE1 0x01
+#define TMP468_REMOTE2 0x02
+#define TMP468_REMOTE3 0x03
+#define TMP468_REMOTE4 0x04
+#define TMP468_REMOTE5 0x05
+#define TMP468_REMOTE6 0x06
+#define TMP468_REMOTE7 0x07
+#define TMP468_REMOTE8 0x08
+
+#define TMP468_SRST 0x20
+#define TMP468_THERM 0x21
+#define TMP468_THERM2 0x22
+#define TMP468_ROPEN 0x23
+
+#define TMP468_CONFIGURATION 0x30
+#define TMP468_THERM_HYST 0x38
+
+#define TMP468_LOCAL_LOW_LIMIT 0x39
+#define TMP468_LOCAL_HIGH_LIMT 0x3a
+
+#define TMP468_REMOTE1_OFFSET 0x40
+#define TMP468_REMOTE1_NFACTOR 0x41
+#define TMP468_REMOTE1_LOW_LIMIT 0x41
+#define TMP468_REMOTE1_HIGH_LIMIT 0x42
+
+#define TMP468_REMOTE2_OFFSET 0x48
+#define TMP468_REMOTE2_NFACTOR 0x49
+#define TMP468_REMOTE2_LOW_LIMIT 0x4a
+#define TMP468_REMOTE2_HIGH_LIMIT 0x4b
+
+#define TMP468_REMOTE3_OFFSET 0x50
+#define TMP468_REMOTE3_NFACTOR 0x51
+#define TMP468_REMOTE3_LOW_LIMIT 0x52
+#define TMP468_REMOTE3_HIGH_LIMIT 0x53
+
+#define TMP468_REMOTE4_OFFSET 0x58
+#define TMP468_REMOTE4_NFACTOR 0x59
+#define TMP468_REMOTE4_LOW_LIMIT 0x59
+#define TMP468_REMOTE4_HIGH_LIMIT 0x5a
+
+#define TMP468_REMOTE5_OFFSET 0x60
+#define TMP468_REMOTE5_NFACTOR 0x61
+#define TMP468_REMOTE5_LOW_LIMIT 0x62
+#define TMP468_REMOTE5_HIGH_LIMIT 0x63
+
+#define TMP468_REMOTE6_OFFSET 0x68
+#define TMP468_REMOTE6_NFACTOR 0x69
+#define TMP468_REMOTE6_LOW_LIMIT 0x6a
+#define TMP468_REMOTE6_HIGH_LIMIT 0x6b
+
+#define TMP468_REMOTE7_OFFSET 0x70
+#define TMP468_REMOTE7_NFACTOR 0x71
+#define TMP468_REMOTE7_LOW_LIMIT 0x72
+#define TMP468_REMOTE7_HIGH_LIMIT 0x73
+
+#define TMP468_REMOTE8_OFFSET 0x78
+#define TMP468_REMOTE8_NFACTOR 0x79
+#define TMP468_REMOTE8_LOW_LIMIT 0x7a
+#define TMP468_REMOTE8_HIGH_LIMIT 0x7b
+
+#define TMP468_LOCK 0xc4
+
+#define TMP468_DEVICE_ID 0xfd
+#define TMP468_MANUFACTURER_ID 0xfe
+
+#define TMP468_SHUTDOWN BIT(5)
 
 enum tmp468_channel_id {
 	TMP468_CHANNEL_LOCAL,
@@ -101,7 +101,6 @@ enum tmp468_power_state {
 	TMP468_POWER_COUNT
 };
 
-
 /**
  * Get the last polled value of a sensor.
  *
diff --git a/driver/touchpad_elan.c b/driver/touchpad_elan.c
index 8838130c60..f9229465e5 100644
--- a/driver/touchpad_elan.c
+++ b/driver/touchpad_elan.c
@@ -1,96 +1,115 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#ifdef CONFIG_ZEPHYR
+#include <zephyr/devicetree.h>
+#else
+#include "byteorder.h"
+#endif
+
 #include "common.h"
 #include "console.h"
 #include "gpio.h"
-#include "hwtimer.h"
 #include "hooks.h"
+#include "hwtimer.h"
 #include "i2c.h"
+#include "math_util.h"
 #include "sha256.h"
 #include "shared_mem.h"
-#include "task.h"
 #include "tablet_mode.h"
+#include "task.h"
 #include "timer.h"
 #include "touchpad.h"
 #include "update_fw.h"
-#include "util.h"
 #include "usb_api.h"
 #include "usb_hid_touchpad.h"
+#include "util.h"
 #include "watchdog.h"
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_TOUCHPAD, outstr)
-#define CPRINTF(format, args...) cprintf(CC_TOUCHPAD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_TOUCHPAD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_TOUCHPAD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_TOUCHPAD, format, ##args)
 
-#define TASK_EVENT_POWER  TASK_EVENT_CUSTOM_BIT(0)
+#define TASK_EVENT_POWER TASK_EVENT_CUSTOM_BIT(0)
 
 /******************************************************************************/
 /* How to talk to the controller */
 /******************************************************************************/
 
-#define ELAN_VENDOR_ID			0x04f3
+#define ELAN_VENDOR_ID 0x04f3
 
-#define ETP_I2C_RESET			0x0100
-#define ETP_I2C_WAKE_UP			0x0800
-#define ETP_I2C_SLEEP			0x0801
+#define ETP_I2C_RESET 0x0100
+#define ETP_I2C_WAKE_UP 0x0800
+#define ETP_I2C_SLEEP 0x0801
 
-#define ETP_I2C_STAND_CMD		0x0005
-#define ETP_I2C_UNIQUEID_CMD		0x0101
-#define ETP_I2C_FW_VERSION_CMD		0x0102
-#define ETP_I2C_OSM_VERSION_CMD		0x0103
-#define ETP_I2C_XY_TRACENUM_CMD		0x0105
-#define ETP_I2C_MAX_X_AXIS_CMD		0x0106
-#define ETP_I2C_MAX_Y_AXIS_CMD		0x0107
-#define ETP_I2C_RESOLUTION_CMD		0x0108
-#define ETP_I2C_PRESSURE_CMD		0x010A
-#define ETP_I2C_SET_CMD			0x0300
-#define ETP_I2C_POWER_CMD		0x0307
-#define ETP_I2C_FW_CHECKSUM_CMD		0x030F
+#define ETP_I2C_STAND_CMD 0x0005
+#define ETP_I2C_UNIQUEID_CMD 0x0101
+#define ETP_I2C_FW_VERSION_CMD 0x0102
+#define ETP_I2C_OSM_VERSION_CMD 0x0103
+#define ETP_I2C_XY_TRACENUM_CMD 0x0105
+#define ETP_I2C_MAX_X_AXIS_CMD 0x0106
+#define ETP_I2C_MAX_Y_AXIS_CMD 0x0107
+#define ETP_I2C_RESOLUTION_CMD 0x0108
+#define ETP_I2C_IAP_VERSION_CMD 0x0110
+#define ETP_I2C_PRESSURE_CMD 0x010A
+#define ETP_I2C_SET_CMD 0x0300
+#define ETP_I2C_IAP_TYPE_CMD 0x0304
+#define ETP_I2C_POWER_CMD 0x0307
+#define ETP_I2C_FW_CHECKSUM_CMD 0x030F
 
-#define ETP_ENABLE_ABS		0x0001
+#define ETP_ENABLE_ABS 0x0001
 
-#define ETP_DISABLE_POWER	0x0001
+#define ETP_DISABLE_POWER 0x0001
 
-#define ETP_I2C_REPORT_LEN	34
+#define ETP_I2C_REPORT_LEN 34
 
-#define ETP_MAX_FINGERS		5
-#define ETP_FINGER_DATA_LEN	5
+#define ETP_MAX_FINGERS 5
+#define ETP_FINGER_DATA_LEN 5
 
-#define ETP_PRESSURE_OFFSET	25
-#define ETP_FWIDTH_REDUCE	90
+#define ETP_PRESSURE_OFFSET 25
+#define ETP_FWIDTH_REDUCE 90
 
-#define ETP_REPORT_ID		0x5D
-#define ETP_REPORT_ID_OFFSET	2
-#define ETP_TOUCH_INFO_OFFSET	3
-#define ETP_FINGER_DATA_OFFSET	4
-#define ETP_HOVER_INFO_OFFSET	30
-#define ETP_MAX_REPORT_LEN	34
+#define ETP_REPORT_ID 0x5D
+#define ETP_REPORT_ID_OFFSET 2
+#define ETP_TOUCH_INFO_OFFSET 3
+#define ETP_FINGER_DATA_OFFSET 4
+#define ETP_HOVER_INFO_OFFSET 30
+#define ETP_MAX_REPORT_LEN 34
 
-#define ETP_IAP_START_ADDR		0x0083
+#define ETP_IAP_START_ADDR 0x0083
 
-#define ETP_I2C_IAP_RESET_CMD		0x0314
-#define ETP_I2C_IAP_RESET		0xF0F0
-#define ETP_I2C_IAP_CTRL_CMD		0x0310
-#define ETP_I2C_MAIN_MODE_ON		BIT(9)
-#define ETP_I2C_IAP_CMD			0x0311
-#define ETP_I2C_IAP_PASSWORD		0x1EA5
+#define ETP_I2C_IAP_RESET_CMD 0x0314
+#define ETP_I2C_IAP_RESET 0xF0F0
+#define ETP_I2C_IAP_CTRL_CMD 0x0310
+#define ETP_I2C_MAIN_MODE_ON BIT(9)
+#define ETP_I2C_IAP_CMD 0x0311
+#define ETP_I2C_IAP_PASSWORD 0x1EA5
 
-#define ETP_I2C_IAP_REG_L		0x01
-#define ETP_I2C_IAP_REG_H		0x06
+#define ETP_I2C_IAP_REG_L 0x01
+#define ETP_I2C_IAP_REG_H 0x06
 
-#define ETP_FW_IAP_PAGE_ERR		BIT(5)
-#define ETP_FW_IAP_INTF_ERR		BIT(4)
+#define ETP_FW_IAP_PAGE_ERR BIT(5)
+#define ETP_FW_IAP_INTF_ERR BIT(4)
 
 #ifdef CONFIG_USB_UPDATE
 /* The actual FW_SIZE depends on IC. */
-#define FW_SIZE			CONFIG_TOUCHPAD_VIRTUAL_SIZE
-#define FW_PAGE_SIZE		64
+#define FW_SIZE CONFIG_TOUCHPAD_VIRTUAL_SIZE
 #endif
 
+#ifdef CONFIG_ZEPHYR
+#if DT_HAS_COMPAT_STATUS_OKAY(elan_ekth3000)
+
+#define TP_NODE DT_INST(0, elan_ekth3000)
+#define GPIO_TOUCHPAD_INT GPIO_SIGNAL(DT_PROP(DT_PROP(TP_NODE, irq), irq_pin))
+#define CONFIG_TOUCHPAD_I2C_ADDR_FLAGS DT_REG_ADDR(TP_NODE)
+#define CONFIG_TOUCHPAD_I2C_PORT I2C_PORT_BY_DEV(TP_NODE)
+
+#endif /* DT_HAS_COMPAT_STATUS_OKAY(elan_ekth3000) */
+#endif /* CONFIG_ZEPHYR */
+
 struct {
 	/* Max X/Y position */
 	uint16_t max_x;
@@ -100,6 +119,10 @@ struct {
 	uint16_t width_y;
 	/* Pressure adjustment */
 	uint8_t pressure_adj;
+	uint16_t ic_type;
+	uint16_t page_count;
+	uint16_t page_size;
+	uint16_t iap_version;
 } elan_tp_params;
 
 /*
@@ -117,8 +140,8 @@ static int elan_tp_read_cmd(uint16_t reg, uint16_t *val)
 	buf[1] = reg >> 8;
 
 	return i2c_xfer(CONFIG_TOUCHPAD_I2C_PORT,
-			CONFIG_TOUCHPAD_I2C_ADDR_FLAGS,
-			buf, sizeof(buf), (uint8_t *)val, sizeof(*val));
+			CONFIG_TOUCHPAD_I2C_ADDR_FLAGS, buf, sizeof(buf),
+			(uint8_t *)val, sizeof(*val));
 }
 
 static int elan_tp_write_cmd(uint16_t reg, uint16_t val)
@@ -131,8 +154,8 @@ static int elan_tp_write_cmd(uint16_t reg, uint16_t val)
 	buf[3] = val >> 8;
 
 	return i2c_xfer(CONFIG_TOUCHPAD_I2C_PORT,
-			CONFIG_TOUCHPAD_I2C_ADDR_FLAGS,
-			buf, sizeof(buf), NULL, 0);
+			CONFIG_TOUCHPAD_I2C_ADDR_FLAGS, buf, sizeof(buf), NULL,
+			0);
 }
 
 /* Power is on by default. */
@@ -164,7 +187,7 @@ static int elan_tp_set_power(int enable)
 	return rv;
 }
 
-static int finger_status[ETP_MAX_FINGERS] = {0};
+static int finger_status[ETP_MAX_FINGERS] = { 0 };
 
 /*
  * Timestamp of last interrupt (32 bits are enough as we divide the value by 100
@@ -185,15 +208,14 @@ static int elan_tp_read_report(void)
 	int i, ri;
 	uint8_t touch_info;
 	uint8_t hover_info;
-	uint8_t *finger = tp_buf+ETP_FINGER_DATA_OFFSET;
+	uint8_t *finger = tp_buf + ETP_FINGER_DATA_OFFSET;
 	struct usb_hid_touchpad_report report;
 	uint16_t timestamp;
 
 	/* Compute and save timestamp early in case another interrupt comes. */
 	timestamp = irq_ts / USB_HID_TOUCHPAD_TIMESTAMP_UNIT;
 
-	rv = i2c_xfer(CONFIG_TOUCHPAD_I2C_PORT,
-		      CONFIG_TOUCHPAD_I2C_ADDR_FLAGS,
+	rv = i2c_xfer(CONFIG_TOUCHPAD_I2C_PORT, CONFIG_TOUCHPAD_I2C_ADDR_FLAGS,
 		      NULL, 0, tp_buf, ETP_I2C_REPORT_LEN);
 
 	if (rv) {
@@ -214,14 +236,14 @@ static int elan_tp_read_report(void)
 	hover_info = tp_buf[ETP_HOVER_INFO_OFFSET];
 
 	for (i = 0; i < ETP_MAX_FINGERS; i++) {
-		int valid = touch_info & (1 << (3+i));
+		int valid = touch_info & (1 << (3 + i));
 
 		if (valid) {
 			int width = finger[3] & 0x0f;
 			int height = (finger[3] & 0xf0) >> 4;
 			int pressure = finger[4] + elan_tp_params.pressure_adj;
 			pressure = DIV_ROUND_NEAREST(pressure * pressure_mult,
-						pressure_div);
+						     pressure_div);
 
 			width = MIN(4095, width * elan_tp_params.width_x);
 			height = MIN(4095, height * elan_tp_params.width_y);
@@ -233,8 +255,8 @@ static int elan_tp_read_report(void)
 			report.finger[ri].id = i;
 			report.finger[ri].width = width;
 			report.finger[ri].height = height;
-			report.finger[ri].x =
-				((finger[0] & 0xf0) << 4) | finger[1];
+			report.finger[ri].x = ((finger[0] & 0xf0) << 4) |
+					      finger[1];
 			report.finger[ri].y =
 				elan_tp_params.max_y -
 				(((finger[0] & 0x0f) << 8) | finger[2]);
@@ -270,6 +292,49 @@ static int elan_tp_read_report(void)
 	return 0;
 }
 
+static void elan_get_fwinfo(void)
+{
+	uint16_t ic_type = elan_tp_params.ic_type;
+	uint16_t iap_version = elan_tp_params.iap_version;
+
+	switch (ic_type) {
+	case 0x09:
+		elan_tp_params.page_count = 768;
+		break;
+	case 0x0D:
+		elan_tp_params.page_count = 896;
+		break;
+	case 0x00:
+	case 0x10:
+	case 0x14:
+	case 0x15:
+		elan_tp_params.page_count = 1024;
+		break;
+	default:
+		elan_tp_params.page_count = -1;
+		CPRINTS("unknown ic_type: %d", ic_type);
+	}
+
+	if ((ic_type == 0x14 || ic_type == 0x15) && iap_version >= 2) {
+		elan_tp_params.page_count /= 8;
+		elan_tp_params.page_size = 512;
+	} else if (ic_type >= 0x0D && iap_version >= 1) {
+		elan_tp_params.page_count /= 2;
+		elan_tp_params.page_size = 128;
+	} else {
+		elan_tp_params.page_size = 64;
+	}
+}
+
+/*
+ * - dpi == logical dimension / physical dimension (inches)
+ *   (254 tenths of mm per inch)
+ */
+__maybe_unused static int calc_physical_dimension(int dpi, int logical_dim)
+{
+	return round_divide(254 * logical_dim, dpi);
+}
+
 /* Initialize the controller ICs after reset */
 static void elan_tp_init(void)
 {
@@ -281,14 +346,29 @@ static void elan_tp_init(void)
 
 	elan_tp_write_cmd(ETP_I2C_STAND_CMD, ETP_I2C_RESET);
 	msleep(100);
-	rv = i2c_xfer(CONFIG_TOUCHPAD_I2C_PORT,
-		      CONFIG_TOUCHPAD_I2C_ADDR_FLAGS,
+	rv = i2c_xfer(CONFIG_TOUCHPAD_I2C_PORT, CONFIG_TOUCHPAD_I2C_ADDR_FLAGS,
 		      NULL, 0, val, sizeof(val));
 
 	CPRINTS("reset rv %d buf=%04x", rv, *((uint16_t *)val));
 	if (rv)
 		goto out;
 
+	/* Read IC type, IAP version */
+	rv = elan_tp_read_cmd(ETP_I2C_OSM_VERSION_CMD, &elan_tp_params.ic_type);
+	CPRINTS("%s: ic_type:%04X.", __func__, elan_tp_params.ic_type);
+	elan_tp_params.ic_type >>= 8;
+	if (rv)
+		goto out;
+
+	rv = elan_tp_read_cmd(ETP_I2C_IAP_VERSION_CMD,
+			      &elan_tp_params.iap_version);
+	CPRINTS("%s: iap_version:%04X.", __func__, elan_tp_params.iap_version);
+	elan_tp_params.iap_version >>= 8;
+	if (rv)
+		goto out;
+
+	elan_get_fwinfo();
+
 	/* Read min/max */
 	rv = elan_tp_read_cmd(ETP_I2C_MAX_X_AXIS_CMD, &elan_tp_params.max_x);
 	if (rv)
@@ -323,26 +403,22 @@ static void elan_tp_init(void)
 	if (rv)
 		goto out;
 
-	dpi_x = 10*val[0] + 790;
-	dpi_y = 10*val[1] + 790;
+	dpi_x = 10 * val[0] + 790;
+	dpi_y = 10 * val[1] + 790;
 
-	CPRINTS("max=%d/%d width=%d/%d adj=%d dpi=%d/%d",
-		elan_tp_params.max_x, elan_tp_params.max_y,
-		elan_tp_params.width_x, elan_tp_params.width_y,
-		elan_tp_params.pressure_adj, dpi_x, dpi_y);
+	CPRINTS("max=%d/%d width=%d/%d adj=%d dpi=%d/%d", elan_tp_params.max_x,
+		elan_tp_params.max_y, elan_tp_params.width_x,
+		elan_tp_params.width_y, elan_tp_params.pressure_adj, dpi_x,
+		dpi_y);
 
 #ifdef CONFIG_USB_HID_TOUCHPAD
-	/*
-	 * Validity check dimensions provided at build time.
-	 * - dpi == logical dimension / physical dimension (inches)
-	 *   (254 tenths of mm per inch)
-	 */
+	/* Validity check dimensions provided at build time. */
 	if (elan_tp_params.max_x != CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X ||
 	    elan_tp_params.max_y != CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y ||
-	    dpi_x != 254*CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X /
-				CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X ||
-	    dpi_y != 254*CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y /
-				CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y) {
+	    calc_physical_dimension(dpi_x, elan_tp_params.max_x) !=
+		    CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X ||
+	    calc_physical_dimension(dpi_y, elan_tp_params.max_y) !=
+		    CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y) {
 		CPRINTS("*** TP mismatch!");
 	}
 #endif
@@ -401,22 +477,22 @@ static int elan_in_main_mode(void)
 	return val & ETP_I2C_MAIN_MODE_ON;
 }
 
-static int elan_get_ic_page_count(void)
+static int elan_read_write_iap_type(void)
 {
-	uint16_t ic_type;
+	for (int retry = 0; retry < 3; ++retry) {
+		uint16_t val;
 
-	elan_tp_read_cmd(ETP_I2C_OSM_VERSION_CMD, &ic_type);
-	CPRINTS("%s: ic_type:%04X.", __func__, ic_type);
-	switch (ic_type >> 8) {
-	case 0x09:
-		return 768;
-	case 0x0D:
-		return 896;
-	case 0x00:
-	case 0x10:
-		return 1024;
+		if (elan_tp_write_cmd(ETP_I2C_IAP_TYPE_CMD,
+				      elan_tp_params.page_size / 2))
+			return EC_ERROR_UNKNOWN;
+
+		if (elan_tp_read_cmd(ETP_I2C_IAP_TYPE_CMD, &val))
+			return EC_ERROR_UNKNOWN;
+
+		if (val == elan_tp_params.page_size / 2)
+			return EC_SUCCESS;
 	}
-	return -1;
+	return EC_ERROR_UNKNOWN;
 }
 
 static int elan_prepare_for_update(void)
@@ -440,6 +516,11 @@ static int elan_prepare_for_update(void)
 		return EC_ERROR_UNKNOWN;
 	}
 
+	if (elan_tp_params.ic_type >= 0x0D && elan_tp_params.iap_version >= 1) {
+		if (elan_read_write_iap_type())
+			return EC_ERROR_UNKNOWN;
+	}
+
 	/* Send the passphrase again */
 	elan_tp_write_cmd(ETP_I2C_IAP_CMD, ETP_I2C_IAP_PASSWORD);
 	msleep(30);
@@ -459,32 +540,44 @@ static int elan_prepare_for_update(void)
 
 static int touchpad_update_page(const uint8_t *data)
 {
-	uint8_t page_store[FW_PAGE_SIZE + 4];
+	const uint8_t cmd[2] = { ETP_I2C_IAP_REG_L, ETP_I2C_IAP_REG_H };
 	uint16_t checksum = 0;
 	uint16_t rx_buf;
 	int i, rv;
 
-	for (i = 0; i < FW_PAGE_SIZE; i += 2)
+	for (i = 0; i < elan_tp_params.page_size; i += 2)
 		checksum += ((uint16_t)(data[i + 1]) << 8) | (data[i]);
+	checksum = htole16(checksum);
+
+	i2c_lock(CONFIG_TOUCHPAD_I2C_PORT, 1);
 
-	page_store[0] = ETP_I2C_IAP_REG_L;
-	page_store[1] = ETP_I2C_IAP_REG_H;
-	memcpy(page_store + 2, data, FW_PAGE_SIZE);
-	page_store[FW_PAGE_SIZE + 2 + 0] = checksum & 0xff;
-	page_store[FW_PAGE_SIZE + 2 + 1] = (checksum >> 8) & 0xff;
+	rv = i2c_xfer_unlocked(CONFIG_TOUCHPAD_I2C_PORT,
+			       CONFIG_TOUCHPAD_I2C_ADDR_FLAGS, cmd, sizeof(cmd),
+			       NULL, 0, I2C_XFER_START);
+	if (rv)
+		goto fail;
+	rv = i2c_xfer_unlocked(CONFIG_TOUCHPAD_I2C_PORT,
+			       CONFIG_TOUCHPAD_I2C_ADDR_FLAGS, data,
+			       elan_tp_params.page_size, NULL, 0, 0);
+	if (rv)
+		goto fail;
+	rv = i2c_xfer_unlocked(CONFIG_TOUCHPAD_I2C_PORT,
+			       CONFIG_TOUCHPAD_I2C_ADDR_FLAGS,
+			       (uint8_t *)&checksum, sizeof(checksum), NULL, 0,
+			       I2C_XFER_STOP);
+	if (rv)
+		goto fail;
 
-	rv = i2c_xfer(CONFIG_TOUCHPAD_I2C_PORT,
-		      CONFIG_TOUCHPAD_I2C_ADDR_FLAGS,
-		      page_store, sizeof(page_store), NULL, 0);
+fail:
+	i2c_lock(CONFIG_TOUCHPAD_I2C_PORT, 0);
 	if (rv)
 		return rv;
-	msleep(20);
+	msleep(elan_tp_params.page_size >= 512 ? 50 : 35);
 
 	rv = elan_tp_read_cmd(ETP_I2C_IAP_CTRL_CMD, &rx_buf);
 
 	if (rv || (rx_buf & (ETP_FW_IAP_PAGE_ERR | ETP_FW_IAP_INTF_ERR))) {
-		CPRINTS("%s: IAP reports failed write : %x.",
-			__func__, rx_buf);
+		CPRINTS("%s: IAP reports failed write : %x.", __func__, rx_buf);
 		return EC_ERROR_UNKNOWN;
 	}
 	return 0;
@@ -493,16 +586,17 @@ static int touchpad_update_page(const uint8_t *data)
 int touchpad_update_write(int offset, int size, const uint8_t *data)
 {
 	static int iap_addr = -1;
-	int addr, rv, page_count;
+	int addr, rv;
 
 	CPRINTS("%s %08x %d", __func__, offset, size);
 
 	if (offset == 0) {
 		/* Verify the IC type is aligned with defined firmware size */
-		page_count = elan_get_ic_page_count();
-		if (FW_PAGE_SIZE * page_count != FW_SIZE) {
+		if (elan_tp_params.page_size * elan_tp_params.page_count !=
+		    FW_SIZE) {
 			CPRINTS("%s: IC(%d*%d) size and FW_SIZE(%d) mismatch",
-				__func__, page_count, FW_PAGE_SIZE, FW_SIZE);
+				__func__, elan_tp_params.page_count,
+				elan_tp_params.page_size, FW_SIZE);
 			return EC_ERROR_UNKNOWN;
 		}
 
@@ -517,22 +611,23 @@ int touchpad_update_write(int offset, int size, const uint8_t *data)
 	if (offset <= (ETP_IAP_START_ADDR * 2) &&
 	    (ETP_IAP_START_ADDR * 2) < (offset + size)) {
 		iap_addr = ((data[ETP_IAP_START_ADDR * 2 - offset + 1] << 8) |
-			data[ETP_IAP_START_ADDR * 2 - offset]) << 1;
+			    data[ETP_IAP_START_ADDR * 2 - offset])
+			   << 1;
 		CPRINTS("%s: payload starts from 0x%x.", __func__, iap_addr);
 	}
 
-	/* Data that comes in must align with FW_PAGE_SIZE */
-	if (offset % FW_PAGE_SIZE)
+	/* Data that comes in must align with page_size */
+	if (offset % elan_tp_params.page_size)
 		return EC_ERROR_INVAL;
 
-	for (addr = (offset / FW_PAGE_SIZE) * FW_PAGE_SIZE;
-			addr < (offset + size); addr += FW_PAGE_SIZE) {
+	for (addr = offset; addr < (offset + size);
+	     addr += elan_tp_params.page_size) {
 		if (iap_addr > addr) /* Skip chunk */
 			continue;
 		rv = touchpad_update_page(data + addr - offset);
 		if (rv)
 			return rv;
-		CPRINTF("/p%d", addr / FW_PAGE_SIZE);
+		CPRINTF("/p%d", addr / elan_tp_params.page_size);
 		watchdog_reload();
 	}
 	CPRINTF("\n");
@@ -550,21 +645,17 @@ int touchpad_update_write(int offset, int size, const uint8_t *data)
 #define TOUCHPAD_ELAN_DEBUG_CMD_LENGTH 50
 #define TOUCHPAD_ELAN_DEBUG_NUM_CMD 2
 
-static const uint8_t
-allowed_command_hashes[TOUCHPAD_ELAN_DEBUG_NUM_CMD][SHA256_DIGEST_SIZE] = {
-	{
-		0x0a, 0xf6, 0x37, 0x03, 0x93, 0xb2, 0xde, 0x8c,
-		0x56, 0x7b, 0x86, 0xba, 0xa6, 0x79, 0xe3, 0xa3,
-		0x8b, 0xc7, 0x15, 0xf2, 0x53, 0xcf, 0x71, 0x8b,
-		0x3d, 0xe4, 0x81, 0xf9, 0xd9, 0xa8, 0x78, 0x48
-	},
-	{
-		0xac, 0xe5, 0xbf, 0x17, 0x1f, 0xde, 0xce, 0x76,
-		0x0c, 0x0e, 0xf8, 0xa2, 0xe9, 0x67, 0x2d, 0xc9,
-		0x1b, 0xd4, 0xba, 0x34, 0x51, 0xca, 0xf6, 0x6d,
-		0x7b, 0xb2, 0x1f, 0x14, 0x82, 0x1c, 0x0b, 0x74
-	},
-};
+static const uint8_t allowed_command_hashes
+	[TOUCHPAD_ELAN_DEBUG_NUM_CMD][SHA256_DIGEST_SIZE] = {
+		{ 0x0a, 0xf6, 0x37, 0x03, 0x93, 0xb2, 0xde, 0x8c,
+		  0x56, 0x7b, 0x86, 0xba, 0xa6, 0x79, 0xe3, 0xa3,
+		  0x8b, 0xc7, 0x15, 0xf2, 0x53, 0xcf, 0x71, 0x8b,
+		  0x3d, 0xe4, 0x81, 0xf9, 0xd9, 0xa8, 0x78, 0x48 },
+		{ 0xac, 0xe5, 0xbf, 0x17, 0x1f, 0xde, 0xce, 0x76,
+		  0x0c, 0x0e, 0xf8, 0xa2, 0xe9, 0x67, 0x2d, 0xc9,
+		  0x1b, 0xd4, 0xba, 0x34, 0x51, 0xca, 0xf6, 0x6d,
+		  0x7b, 0xb2, 0x1f, 0x14, 0x82, 0x1c, 0x0b, 0x74 },
+	};
 
 /* Debugging commands need to allocate a <=1k buffer. */
 SHARED_MEM_CHECK_SIZE(1024);
@@ -595,8 +686,8 @@ int touchpad_debug(const uint8_t *param, unsigned int param_size,
 		uint8_t *command_hash;
 		unsigned int offset = param[1];
 		unsigned int write_length = param[2];
-		unsigned int read_length =
-			((unsigned int)param[3] << 8) | param[4];
+		unsigned int read_length = ((unsigned int)param[3] << 8) |
+					   param[4];
 		int i;
 		int match;
 		int rv;
@@ -606,13 +697,14 @@ int touchpad_debug(const uint8_t *param, unsigned int param_size,
 			return EC_RES_INVALID_PARAM;
 
 		SHA256_init(&ctx);
-		SHA256_update(&ctx, param+5, TOUCHPAD_ELAN_DEBUG_CMD_LENGTH-5);
+		SHA256_update(&ctx, param + 5,
+			      TOUCHPAD_ELAN_DEBUG_CMD_LENGTH - 5);
 		command_hash = SHA256_final(&ctx);
 
 		match = 0;
 		for (i = 0; i < TOUCHPAD_ELAN_DEBUG_NUM_CMD; i++) {
 			if (!memcmp(command_hash, allowed_command_hashes[i],
-					sizeof(allowed_command_hashes[i]))) {
+				    sizeof(allowed_command_hashes[i]))) {
 				match = 1;
 				break;
 			}
@@ -629,8 +721,8 @@ int touchpad_debug(const uint8_t *param, unsigned int param_size,
 		buffer_size = read_length;
 
 		if (read_length > 0) {
-			if (shared_mem_acquire(buffer_size,
-				    (char **)&buffer) != EC_SUCCESS) {
+			if (shared_mem_acquire(buffer_size, (char **)&buffer) !=
+			    EC_SUCCESS) {
 				buffer = NULL;
 				buffer_size = 0;
 				return EC_RES_BUSY;
@@ -640,9 +732,8 @@ int touchpad_debug(const uint8_t *param, unsigned int param_size,
 		}
 
 		rv = i2c_xfer(CONFIG_TOUCHPAD_I2C_PORT,
-			      CONFIG_TOUCHPAD_I2C_ADDR_FLAGS,
-			      &param[offset], write_length,
-			      buffer, read_length);
+			      CONFIG_TOUCHPAD_I2C_ADDR_FLAGS, &param[offset],
+			      write_length, buffer, read_length);
 
 		if (rv)
 			return EC_RES_BUS_ERROR;
@@ -714,7 +805,7 @@ static void touchpad_power_control(void)
 
 #ifdef CONFIG_USB_SUSPEND
 	enable = enable &&
-		(!usb_is_suspended() || usb_is_remote_wakeup_enabled());
+		 (!usb_is_suspended() || usb_is_remote_wakeup_enabled());
 #endif
 
 #ifdef CONFIG_TABLET_MODE
@@ -754,7 +845,7 @@ void touchpad_task(void *u)
 #if defined(CONFIG_USB_SUSPEND) || defined(CONFIG_TABLET_MODE)
 static void touchpad_power_change(void)
 {
-	task_set_event(TASK_ID_TOUCHPAD, TASK_EVENT_POWER, 0);
+	task_set_event(TASK_ID_TOUCHPAD, TASK_EVENT_POWER);
 }
 #endif
 #ifdef CONFIG_USB_SUSPEND
diff --git a/driver/touchpad_gt7288.c b/driver/touchpad_gt7288.c
index ccc98622d5..f225c5b7eb 100644
--- a/driver/touchpad_gt7288.c
+++ b/driver/touchpad_gt7288.c
@@ -1,10 +1,8 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <stdbool.h>
-
 #include "common.h"
 #include "console.h"
 #include "hooks.h"
@@ -13,12 +11,14 @@
 #include "touchpad_gt7288.h"
 #include "util.h"
 
+#include <stdbool.h>
+
 /* Define this to enable various warning messages during report parsing. */
 #undef DEBUG_CHECKS
 
-#define CPRINTS(format, args...) cprints(CC_TOUCHPAD, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_TOUCHPAD, format, ##args)
 
-#define GT7288_SLAVE_ADDRESS 0x14
+#define GT7288_I2C_ADDR_FLAGS 0x14
 
 #define GT7288_REPORT_ID_PTP 0x04
 
@@ -44,10 +44,9 @@
 static int gt7288_read_desc(uint16_t register_id, uint8_t *data,
 			    size_t max_length)
 {
-	uint8_t reg_bytes[] = {
-		register_id & 0xFF, (register_id & 0xFF00) >> 8
-	};
-	return i2c_xfer(CONFIG_TOUCHPAD_I2C_PORT, GT7288_SLAVE_ADDRESS,
+	uint8_t reg_bytes[] = { register_id & 0xFF,
+				(register_id & 0xFF00) >> 8 };
+	return i2c_xfer(CONFIG_TOUCHPAD_I2C_PORT, GT7288_I2C_ADDR_FLAGS,
 			reg_bytes, sizeof(reg_bytes), data, max_length);
 }
 
@@ -88,8 +87,8 @@ static void gt7288_translate_contact(const uint8_t *data,
 
 static int gt7288_read(uint8_t *data, size_t max_length)
 {
-	return i2c_xfer(CONFIG_TOUCHPAD_I2C_PORT, GT7288_SLAVE_ADDRESS,
-			NULL, 0, data, max_length);
+	return i2c_xfer(CONFIG_TOUCHPAD_I2C_PORT, GT7288_I2C_ADDR_FLAGS, NULL,
+			0, data, max_length);
 }
 
 int gt7288_read_ptp_report(struct gt7288_ptp_report *report)
@@ -102,8 +101,8 @@ int gt7288_read_ptp_report(struct gt7288_ptp_report *report)
 
 	if (data[10] > GT7288_MAX_CONTACTS) {
 		if (IS_ENABLED(DEBUG_CHECKS))
-			CPRINTS("ERROR: too many contacts (%d > %d).",
-				data[10], GT7288_MAX_CONTACTS);
+			CPRINTS("ERROR: too many contacts (%d > %d).", data[10],
+				GT7288_MAX_CONTACTS);
 		return EC_ERROR_HW_INTERNAL;
 	}
 	report->num_contacts = data[10];
@@ -126,7 +125,7 @@ int gt7288_read_ptp_report(struct gt7288_ptp_report *report)
 }
 
 #ifdef CONFIG_CMD_GT7288
-static int command_gt7288_read_desc(int argc, char **argv)
+static int command_gt7288_read_desc(int argc, const char **argv)
 {
 	uint16_t register_id;
 	long parsed_arg;
@@ -150,11 +149,10 @@ static int command_gt7288_read_desc(int argc, char **argv)
 	ccprintf("\n");
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(gt7288_desc, command_gt7288_read_desc,
-			"register",
+DECLARE_CONSOLE_COMMAND(gt7288_desc, command_gt7288_read_desc, "register",
 			"Read a descriptor on the GT7288");
 
-static int command_gt7288_read_report_descriptor(int argc, char **argv)
+static int command_gt7288_read_report_descriptor(int argc, const char **argv)
 {
 	int i;
 	uint8_t data[64];
@@ -185,7 +183,7 @@ static int command_gt7288_read_report_descriptor(int argc, char **argv)
 DECLARE_CONSOLE_COMMAND(gt7288_repdesc, command_gt7288_read_report_descriptor,
 			"", "Read the report descriptor on the GT7288");
 
-static int command_gt7288_ver(int argc, char **argv)
+static int command_gt7288_ver(int argc, const char **argv)
 {
 	struct gt7288_version_info info;
 
@@ -200,7 +198,7 @@ static int command_gt7288_ver(int argc, char **argv)
 DECLARE_CONSOLE_COMMAND(gt7288_ver, command_gt7288_ver, "",
 			"Read version information from the GT7288");
 
-static int command_gt7288_report(int argc, char **argv)
+static int command_gt7288_report(int argc, const char **argv)
 {
 	int i;
 	struct gt7288_ptp_report report;
diff --git a/driver/touchpad_gt7288.h b/driver/touchpad_gt7288.h
index c89c586784..ad8d43636e 100644
--- a/driver/touchpad_gt7288.h
+++ b/driver/touchpad_gt7288.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/driver/touchpad_st.c b/driver/touchpad_st.c
index c5211dcead..f71b952f86 100644
--- a/driver/touchpad_st.c
+++ b/driver/touchpad_st.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,13 +8,14 @@
 #include "common.h"
 #include "console.h"
 #include "gpio.h"
-#include "hwtimer.h"
 #include "hooks.h"
+#include "hwtimer.h"
 #include "i2c.h"
+#include "printf.h"
 #include "registers.h"
 #include "spi.h"
-#include "task.h"
 #include "tablet_mode.h"
+#include "task.h"
 #include "timer.h"
 #include "touchpad.h"
 #include "touchpad_st.h"
@@ -28,11 +29,11 @@
 /* Console output macros */
 #define CC_TOUCHPAD CC_USB
 #define CPUTS(outstr) cputs(CC_TOUCHPAD, outstr)
-#define CPRINTF(format, args...) cprintf(CC_TOUCHPAD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_TOUCHPAD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_TOUCHPAD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_TOUCHPAD, format, ##args)
 
-#define TASK_EVENT_POWER  TASK_EVENT_CUSTOM_BIT(0)
-#define TASK_EVENT_TP_UPDATED  TASK_EVENT_CUSTOM_BIT(1)
+#define TASK_EVENT_POWER TASK_EVENT_CUSTOM_BIT(0)
+#define TASK_EVENT_TP_UPDATED TASK_EVENT_CUSTOM_BIT(1)
 
 #define SPI (&(spi_devices[SPI_ST_TP_DEVICE_ID]))
 
@@ -55,26 +56,26 @@ static void touchpad_power_control(void);
  */
 static int system_state;
 
-#define SYSTEM_STATE_DEBUG_MODE		BIT(0)
-#define SYSTEM_STATE_ENABLE_HEAT_MAP	BIT(1)
-#define SYSTEM_STATE_ENABLE_DOME_SWITCH	BIT(2)
-#define SYSTEM_STATE_ACTIVE_MODE	BIT(3)
-#define SYSTEM_STATE_DOME_SWITCH_LEVEL	BIT(4)
-#define SYSTEM_STATE_READY		BIT(5)
+#define SYSTEM_STATE_DEBUG_MODE BIT(0)
+#define SYSTEM_STATE_ENABLE_HEAT_MAP BIT(1)
+#define SYSTEM_STATE_ENABLE_DOME_SWITCH BIT(2)
+#define SYSTEM_STATE_ACTIVE_MODE BIT(3)
+#define SYSTEM_STATE_DOME_SWITCH_LEVEL BIT(4)
+#define SYSTEM_STATE_READY BIT(5)
 
 /*
  * Pending action for touchpad.
  */
 static int tp_control;
 
-#define TP_CONTROL_SHALL_HALT		BIT(0)
-#define TP_CONTROL_SHALL_RESET		BIT(1)
-#define TP_CONTROL_SHALL_INIT		BIT(2)
-#define TP_CONTROL_SHALL_INIT_FULL	BIT(3)
-#define TP_CONTROL_SHALL_DUMP_ERROR	BIT(4)
-#define TP_CONTROL_RESETTING		BIT(5)
-#define TP_CONTROL_INIT			BIT(6)
-#define TP_CONTROL_INIT_FULL		BIT(7)
+#define TP_CONTROL_SHALL_HALT BIT(0)
+#define TP_CONTROL_SHALL_RESET BIT(1)
+#define TP_CONTROL_SHALL_INIT BIT(2)
+#define TP_CONTROL_SHALL_INIT_FULL BIT(3)
+#define TP_CONTROL_SHALL_DUMP_ERROR BIT(4)
+#define TP_CONTROL_RESETTING BIT(5)
+#define TP_CONTROL_INIT BIT(6)
+#define TP_CONTROL_INIT_FULL BIT(7)
 
 /*
  * Number of times we have reset the touchpad because of errors.
@@ -112,10 +113,9 @@ static struct {
 		struct st_tp_host_data_header_t data_header;
 		struct st_tp_event_t events[32];
 		uint32_t dump_info[32];
-	} /* anonymous */;
+	} __packed /* anonymous */;
 } __packed rx_buf;
 
-
 #ifdef CONFIG_USB_ISOCHRONOUS
 #define USB_ISO_PACKET_SIZE 256
 /*
@@ -124,7 +124,7 @@ static struct {
 struct packet_header_t {
 	uint8_t index;
 
-#define HEADER_FLAGS_NEW_FRAME	BIT(0)
+#define HEADER_FLAGS_NEW_FRAME BIT(0)
 	uint8_t flags;
 } __packed;
 BUILD_ASSERT(sizeof(struct packet_header_t) < USB_ISO_PACKET_SIZE);
@@ -133,7 +133,7 @@ static struct packet_header_t packet_header;
 
 /* What will be sent to USB interface. */
 struct st_tp_usb_packet_t {
-#define USB_FRAME_FLAGS_BUTTON	BIT(0)
+#define USB_FRAME_FLAGS_BUTTON BIT(0)
 	/*
 	 * This will be true if user clicked on touchpad.
 	 * TODO(b/70482333): add corresponding code for button signal.
@@ -165,7 +165,6 @@ static void st_tp_interrupt_send(void);
 DECLARE_DEFERRED(st_tp_interrupt_send);
 #endif
 
-
 /* Function implementations */
 
 static void set_bits(int *lvalue, int rvalue, int mask)
@@ -184,8 +183,7 @@ static void set_bits(int *lvalue, int rvalue, int mask)
  * @return array index of next finger (i.e. (i + 1) if a finger is added).
  */
 static int st_tp_parse_finger(struct usb_hid_touchpad_report *report,
-			      struct st_tp_event_t *event,
-			      int i)
+			      struct st_tp_event_t *event, int i)
 {
 	const int id = event->finger.touch_id;
 
@@ -193,9 +191,9 @@ static int st_tp_parse_finger(struct usb_hid_touchpad_report *report,
 	if (event->finger.touch_type == ST_TP_TOUCH_TYPE_INVALID)
 		return i;
 
-	if (event->evt_id ==  ST_TP_EVENT_ID_ENTER_POINTER)
+	if (event->evt_id == ST_TP_EVENT_ID_ENTER_POINTER)
 		touch_slot |= 1 << id;
-	else if (event->evt_id ==  ST_TP_EVENT_ID_LEAVE_POINTER)
+	else if (event->evt_id == ST_TP_EVENT_ID_LEAVE_POINTER)
 		touch_slot &= ~BIT(id);
 
 	/* We cannot report more fingers */
@@ -213,10 +211,10 @@ static int st_tp_parse_finger(struct usb_hid_touchpad_report *report,
 		report->finger[i].inrange = 1;
 		report->finger[i].id = id;
 		report->finger[i].pressure = event->finger.z;
-		report->finger[i].width = (event->finger.minor |
-					   (event->minor_high << 4)) << 5;
-		report->finger[i].height = (event->finger.major |
-					    (event->major_high << 4)) << 5;
+		report->finger[i].width =
+			(event->finger.minor | (event->minor_high << 4)) << 5;
+		report->finger[i].height =
+			(event->finger.major | (event->major_high << 4)) << 5;
 
 		report->finger[i].x = (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X -
 				       event->finger.x);
@@ -253,8 +251,7 @@ static int st_tp_check_domeswitch_state(void)
 	 * Domeswitch level from device is inverted.
 	 * That is, 0 => pressed, 1 => released.
 	 */
-	set_bits(&system_state,
-		 ret ? 0 : SYSTEM_STATE_DOME_SWITCH_LEVEL,
+	set_bits(&system_state, ret ? 0 : SYSTEM_STATE_DOME_SWITCH_LEVEL,
 		 SYSTEM_STATE_DOME_SWITCH_LEVEL);
 	return 0;
 }
@@ -295,7 +292,7 @@ static int st_tp_write_hid_report(void)
 		}
 	}
 
-	if (!num_finger && !domeswitch_changed)  /* nothing changed */
+	if (!num_finger && !domeswitch_changed) /* nothing changed */
 		return 0;
 
 	/* Don't report 0 finger click. */
@@ -343,8 +340,8 @@ static int st_tp_read_host_buffer_header(void)
 	const uint8_t tx_buf[] = { ST_TP_CMD_READ_SPI_HOST_BUFFER, 0x00, 0x00 };
 	int rx_len = ST_TP_EXTRA_BYTE + sizeof(rx_buf.buffer_header);
 
-	return spi_transaction(SPI, tx_buf, sizeof(tx_buf),
-			       (uint8_t *)&rx_buf, rx_len);
+	return spi_transaction(SPI, tx_buf, sizeof(tx_buf), (uint8_t *)&rx_buf,
+			       rx_len);
 }
 
 static int st_tp_send_ack(void)
@@ -368,11 +365,7 @@ static int st_tp_update_system_state(int new_state, int mask)
 
 	mask = SYSTEM_STATE_ENABLE_HEAT_MAP | SYSTEM_STATE_ENABLE_DOME_SWITCH;
 	if ((new_state & mask) != (system_state & mask)) {
-		uint8_t tx_buf[] = {
-			ST_TP_CMD_WRITE_FEATURE_SELECT,
-			0x05,
-			0
-		};
+		uint8_t tx_buf[] = { ST_TP_CMD_WRITE_FEATURE_SELECT, 0x05, 0 };
 		if (new_state & SYSTEM_STATE_ENABLE_HEAT_MAP) {
 			CPRINTS("Heatmap enabled");
 			tx_buf[2] |= BIT(0);
@@ -423,8 +416,8 @@ static int st_tp_update_system_state(int new_state, int mask)
 
 static void st_tp_enable_interrupt(int enable)
 {
-	uint8_t tx_buf[] = {
-		ST_TP_CMD_WRITE_SYSTEM_COMMAND, 0x01, enable ? 1 : 0};
+	uint8_t tx_buf[] = { ST_TP_CMD_WRITE_SYSTEM_COMMAND, 0x01,
+			     enable ? 1 : 0 };
 	if (enable)
 		gpio_enable_interrupt(GPIO_TOUCHPAD_INT);
 	spi_transaction(SPI, tx_buf, sizeof(tx_buf), NULL, 0);
@@ -434,8 +427,8 @@ static void st_tp_enable_interrupt(int enable)
 
 static int st_tp_start_scan(void)
 {
-	int new_state = (SYSTEM_STATE_ACTIVE_MODE |
-			 SYSTEM_STATE_ENABLE_DOME_SWITCH);
+	int new_state =
+		(SYSTEM_STATE_ACTIVE_MODE | SYSTEM_STATE_ENABLE_DOME_SWITCH);
 	int mask = new_state;
 	int ret;
 
@@ -451,9 +444,8 @@ static int st_tp_start_scan(void)
 
 static int st_tp_read_host_data_memory(uint16_t addr, void *rx_buf, int len)
 {
-	uint8_t tx_buf[] = {
-		ST_TP_CMD_READ_HOST_DATA_MEMORY, addr >> 8, addr & 0xFF
-	};
+	uint8_t tx_buf[] = { ST_TP_CMD_READ_HOST_DATA_MEMORY, addr >> 8,
+			     addr & 0xFF };
 
 	return spi_transaction(SPI, tx_buf, sizeof(tx_buf), rx_buf, len);
 }
@@ -473,9 +465,7 @@ static int st_tp_stop_scan(void)
 
 static int st_tp_load_host_data(uint8_t mem_id)
 {
-	uint8_t tx_buf[] = {
-		ST_TP_CMD_WRITE_SYSTEM_COMMAND, 0x06, mem_id
-	};
+	uint8_t tx_buf[] = { ST_TP_CMD_WRITE_SYSTEM_COMMAND, 0x06, mem_id };
 	int retry, ret;
 	uint16_t count;
 	struct st_tp_host_data_header_t *header = &rx_buf.data_header;
@@ -559,24 +549,24 @@ static int st_tp_read_system_info(int reload)
  */
 static void enable_deep_sleep(int enable)
 {
-	uint8_t cmd[] = {0xFA, 0x20, 0x00, 0x00, 0x68, enable ? 0x0B : 0x08};
+	uint8_t cmd[] = { 0xFA, 0x20, 0x00, 0x00, 0x68, enable ? 0x0B : 0x08 };
 
 	spi_transaction(SPI, cmd, sizeof(cmd), NULL, 0);
 }
 
 static void dump_error(void)
 {
-	uint8_t tx_buf[] = {0xFB, 0x20, 0x01, 0xEF, 0x80};
+	uint8_t tx_buf[] = { 0xFB, 0x20, 0x01, 0xEF, 0x80 };
 	int rx_len = sizeof(rx_buf.dump_info) + ST_TP_EXTRA_BYTE;
 	int i;
 
-	spi_transaction(SPI, tx_buf, sizeof(tx_buf),
-			(uint8_t *)&rx_buf, rx_len);
+	spi_transaction(SPI, tx_buf, sizeof(tx_buf), (uint8_t *)&rx_buf,
+			rx_len);
 
 	for (i = 0; i < ARRAY_SIZE(rx_buf.dump_info); i += 4)
-		CPRINTS("%08x %08x %08x %08x",
-			rx_buf.dump_info[i + 0], rx_buf.dump_info[i + 1],
-			rx_buf.dump_info[i + 2], rx_buf.dump_info[i + 3]);
+		CPRINTS("%08x %08x %08x %08x", rx_buf.dump_info[i + 0],
+			rx_buf.dump_info[i + 1], rx_buf.dump_info[i + 2],
+			rx_buf.dump_info[i + 3]);
 	msleep(8);
 }
 
@@ -589,8 +579,8 @@ static void dump_error(void)
 static void dump_memory(void)
 {
 	uint32_t size = 0x10000, rx_len = 512 + ST_TP_EXTRA_BYTE;
-	uint32_t offset, i;
-	uint8_t cmd[] = {0xFB, 0x00, 0x10, 0x00, 0x00};
+	uint32_t offset, i, j;
+	uint8_t cmd[] = { 0xFB, 0x00, 0x10, 0x00, 0x00 };
 
 	if (!dump_memory_on_error)
 		return;
@@ -598,20 +588,20 @@ static void dump_memory(void)
 	for (offset = 0; offset < size; offset += 512) {
 		cmd[3] = (offset >> 8) & 0xFF;
 		cmd[4] = (offset >> 0) & 0xFF;
-		spi_transaction(SPI, cmd, sizeof(cmd),
-				(uint8_t *)&rx_buf, rx_len);
+		spi_transaction(SPI, cmd, sizeof(cmd), (uint8_t *)&rx_buf,
+				rx_len);
 
 		for (i = 0; i < rx_len - ST_TP_EXTRA_BYTE; i += 32) {
-			CPRINTF("%ph %ph %ph %ph "
-				"%ph %ph %ph %ph\n",
-				HEX_BUF(rx_buf.bytes + i + 4 * 0, 4),
-				HEX_BUF(rx_buf.bytes + i + 4 * 1, 4),
-				HEX_BUF(rx_buf.bytes + i + 4 * 2, 4),
-				HEX_BUF(rx_buf.bytes + i + 4 * 3, 4),
-				HEX_BUF(rx_buf.bytes + i + 4 * 4, 4),
-				HEX_BUF(rx_buf.bytes + i + 4 * 5, 4),
-				HEX_BUF(rx_buf.bytes + i + 4 * 6, 4),
-				HEX_BUF(rx_buf.bytes + i + 4 * 7, 4));
+			for (j = 0; j < 8; j++) {
+				char str_buf[hex_str_buf_size(4)];
+
+				snprintf_hex_buffer(
+					str_buf, sizeof(str_buf),
+					HEX_BUF(rx_buf.bytes + i + 4 * j, 4));
+
+				CPRINTF("%s ", str_buf);
+			}
+			CPRINTF("\n");
 			msleep(8);
 		}
 	}
@@ -629,11 +619,8 @@ static void st_tp_handle_error(uint8_t error_type)
 	/*
 	 * Suggest action: memory dump and power cycle.
 	 */
-	if (error_type <= 0x06 ||
-	    error_type == 0xF1 ||
-	    error_type == 0xF2 ||
-	    error_type == 0xF3 ||
-	    (error_type >= 0x47 && error_type <= 0x4E)) {
+	if (error_type <= 0x06 || error_type == 0xF1 || error_type == 0xF2 ||
+	    error_type == 0xF3 || (error_type >= 0x47 && error_type <= 0x4E)) {
 		tp_control |= TP_CONTROL_SHALL_RESET;
 		return;
 	}
@@ -641,8 +628,7 @@ static void st_tp_handle_error(uint8_t error_type)
 	/*
 	 * Suggest action: FW shall halt, consult ST.
 	 */
-	if ((error_type >= 0x20 && error_type <= 0x23) ||
-	    error_type == 0x25 ||
+	if ((error_type >= 0x20 && error_type <= 0x23) || error_type == 0x25 ||
 	    (error_type >= 0x2E && error_type <= 0x46)) {
 		CPRINTS("tp shall halt");
 		tp_control |= TP_CONTROL_SHALL_HALT;
@@ -697,15 +683,13 @@ static void st_tp_handle_error_report(struct st_tp_event_t *e)
 static void st_tp_handle_status_report(struct st_tp_event_t *e)
 {
 	static uint32_t prev_idle_count;
-	uint32_t info = ((e->report.info[0] << 0) |
-			 (e->report.info[1] << 8) |
-			 (e->report.info[2] << 16) |
-			 (e->report.info[3] << 24));
+	uint32_t info = ((e->report.info[0] << 0) | (e->report.info[1] << 8) |
+			 (e->report.info[2] << 16) | (e->report.info[3] << 24));
 
 	if (e->report.report_type == ST_TP_STATUS_FCAL ||
 	    e->report.report_type == ST_TP_STATUS_FRAME_DROP)
-		CPRINTS("TP STATUS REPORT: %02x %08x",
-			e->report.report_type, info);
+		CPRINTS("TP STATUS REPORT: %02x %08x", e->report.report_type,
+			info);
 
 	/*
 	 * Idle count might not change if ST FW is busy (for example, when the
@@ -742,7 +726,7 @@ static void st_tp_handle_status_report(struct st_tp_event_t *e)
  *
  * When there are error events, suggested action will be saved in `tp_control`.
  *
- * @param show_error: weather EC should read and dump error or not.
+ * @param show_error: whether EC should read and dump error or not.
  *   ***If this is true, rx_buf.events[] will be cleared.***
  *
  * @return number of events available
@@ -803,8 +787,8 @@ static int st_tp_reset(void)
 		 * suggest us to reset or halt.
 		 */
 		if (!(tp_control & (TP_CONTROL_INIT | TP_CONTROL_INIT_FULL)) &&
-		    (tp_control & (TP_CONTROL_SHALL_HALT |
-				   TP_CONTROL_SHALL_RESET)))
+		    (tp_control &
+		     (TP_CONTROL_SHALL_HALT | TP_CONTROL_SHALL_RESET)))
 			break;
 
 		for (i = 0; i < num_events; i++) {
@@ -883,14 +867,10 @@ int touchpad_get_info(struct touchpad_info *tp)
 static int write_hwreg_cmd32(uint32_t address, uint32_t data)
 {
 	uint8_t tx_buf[] = {
-		ST_TP_CMD_WRITE_HW_REG,
-		(address >> 24) & 0xFF,
-		(address >> 16) & 0xFF,
-		(address >> 8) & 0xFF,
-		(address >> 0) & 0xFF,
-		(data >> 24) & 0xFF,
-		(data >> 16) & 0xFF,
-		(data >> 8) & 0xFF,
+		ST_TP_CMD_WRITE_HW_REG, (address >> 24) & 0xFF,
+		(address >> 16) & 0xFF, (address >> 8) & 0xFF,
+		(address >> 0) & 0xFF,	(data >> 24) & 0xFF,
+		(data >> 16) & 0xFF,	(data >> 8) & 0xFF,
 		(data >> 0) & 0xFF,
 	};
 
@@ -900,12 +880,9 @@ static int write_hwreg_cmd32(uint32_t address, uint32_t data)
 static int write_hwreg_cmd8(uint32_t address, uint8_t data)
 {
 	uint8_t tx_buf[] = {
-		ST_TP_CMD_WRITE_HW_REG,
-		(address >> 24) & 0xFF,
-		(address >> 16) & 0xFF,
-		(address >> 8) & 0xFF,
-		(address >> 0) & 0xFF,
-		data,
+		ST_TP_CMD_WRITE_HW_REG, (address >> 24) & 0xFF,
+		(address >> 16) & 0xFF, (address >> 8) & 0xFF,
+		(address >> 0) & 0xFF,	data,
 	};
 
 	return spi_transaction(SPI, tx_buf, sizeof(tx_buf), NULL, 0);
@@ -914,8 +891,7 @@ static int write_hwreg_cmd8(uint32_t address, uint8_t data)
 static int wait_for_flash_ready(uint8_t type)
 {
 	uint8_t tx_buf[] = {
-		ST_TP_CMD_READ_HW_REG,
-		0x20, 0x00, 0x00, type,
+		ST_TP_CMD_READ_HW_REG, 0x20, 0x00, 0x00, type,
 	};
 	int ret = EC_SUCCESS, retry = 200;
 
@@ -973,8 +949,8 @@ static int st_tp_start_flash_dma(void)
 	return ret;
 }
 
-static int st_tp_write_one_chunk(const uint8_t *head,
-				 uint32_t addr, uint32_t chunk_size)
+static int st_tp_write_one_chunk(const uint8_t *head, uint32_t addr,
+				 uint32_t chunk_size)
 {
 	uint8_t tx_buf[ST_TP_DMA_CHUNK_SIZE + 5];
 	uint32_t index = 0;
@@ -1000,13 +976,13 @@ static int st_tp_write_one_chunk(const uint8_t *head,
  */
 static int st_tp_write_flash(int offset, int size, const uint8_t *data)
 {
-	uint8_t tx_buf[12] = {0};
+	uint8_t tx_buf[12] = { 0 };
 	const uint8_t *head = data, *tail = data + size;
 	uint32_t addr, index, chunk_size;
 	uint32_t flash_buffer_size;
 	int ret;
 
-	offset >>= 2;  /* offset should be count in words */
+	offset >>= 2; /* offset should be count in words */
 	/*
 	 * To write to flash, the data has to be separated into several chunks.
 	 * Each chunk will be no more than `ST_TP_DMA_CHUNK_SIZE` bytes.
@@ -1039,7 +1015,7 @@ static int st_tp_write_flash(int offset, int size, const uint8_t *data)
 		tx_buf[index++] = 0x20;
 		tx_buf[index++] = 0x00;
 		tx_buf[index++] = 0x00;
-		tx_buf[index++] = 0x72;  /* flash DMA config */
+		tx_buf[index++] = 0x72; /* flash DMA config */
 		tx_buf[index++] = 0x00;
 		tx_buf[index++] = 0x00;
 
@@ -1108,9 +1084,7 @@ static uint8_t get_cx_version(uint8_t tp_version)
  */
 static int st_tp_panel_init(int full)
 {
-	uint8_t tx_buf[] = {
-		ST_TP_CMD_WRITE_SYSTEM_COMMAND, 0x00, 0x02
-	};
+	uint8_t tx_buf[] = { ST_TP_CMD_WRITE_SYSTEM_COMMAND, 0x00, 0x02 };
 	int ret, retry;
 
 	if (tp_control & (TP_CONTROL_INIT | TP_CONTROL_INIT_FULL))
@@ -1149,8 +1123,8 @@ static int st_tp_panel_init(int full)
 			return EC_SUCCESS;
 		} else if (ret == EC_ERROR_BUSY) {
 			CPRINTS("Panel initialization on going...");
-		} else if (tp_control & ~(TP_CONTROL_INIT |
-					  TP_CONTROL_INIT_FULL)) {
+		} else if (tp_control &
+			   ~(TP_CONTROL_INIT | TP_CONTROL_INIT_FULL)) {
 			/* there are other kind of errors. */
 			CPRINTS("Panel initialization failed, tp_control: %x",
 				tp_control);
@@ -1223,7 +1197,7 @@ int touchpad_update_write(int offset, int size, const uint8_t *data)
 		CPRINTS("%s: End update, wait for reset.", __func__);
 
 		ret = st_tp_panel_init(full_init_required);
-		task_set_event(TASK_ID_TOUCHPAD, TASK_EVENT_TP_UPDATED, 0);
+		task_set_event(TASK_ID_TOUCHPAD, TASK_EVENT_TP_UPDATED);
 		return ret;
 	}
 
@@ -1262,21 +1236,25 @@ int touchpad_debug(const uint8_t *param, unsigned int param_size,
 		*data_size = 0;
 		st_tp_stop_scan();
 		return EC_SUCCESS;
-	case ST_TP_DEBUG_CMD_READ_BUF_HEADER:
+	case ST_TP_DEBUG_CMD_READ_BUF_HEADER: {
+		char str_buf[hex_str_buf_size(8)];
 		*data = buf;
 		*data_size = 8;
 		st_tp_read_host_buffer_header();
 		memcpy(buf, rx_buf.bytes, *data_size);
-		CPRINTS("header: %ph", HEX_BUF(buf, *data_size));
+		snprintf_hex_buffer(str_buf, sizeof(str_buf),
+				    HEX_BUF(buf, *data_size));
+		CPRINTS("header: %s", str_buf);
 		return EC_SUCCESS;
+	}
 	case ST_TP_DEBUG_CMD_READ_EVENTS:
 		num_events = st_tp_read_all_events(0);
 		if (num_events) {
 			int i;
 
 			for (i = 0; i < num_events; i++) {
-				CPRINTS("event[%d]: id=%d, type=%d",
-					i, rx_buf.events[i].evt_id,
+				CPRINTS("event[%d]: id=%d, type=%d", i,
+					rx_buf.events[i].evt_id,
 					rx_buf.events[i].report.report_type);
 			}
 		}
@@ -1336,9 +1314,7 @@ static void touchpad_read_idle_count(void)
 	uint32_t count;
 	int ret;
 	int rx_len = 2 + ST_TP_EXTRA_BYTE;
-	uint8_t cmd_read_counter[] = {
-		0xFB, 0x00, 0x10, 0xff, 0xff
-	};
+	uint8_t cmd_read_counter[] = { 0xFB, 0x00, 0x10, 0xff, 0xff };
 
 	/* Find address of idle count. */
 	ret = st_tp_load_host_data(ST_TP_MEM_ID_SYSTEM_INFO);
@@ -1373,13 +1349,9 @@ static void touchpad_read_idle_count(void)
  */
 static void touchpad_collect_error(void)
 {
-	const uint8_t tx_dump_error[] = {
-		0xFB, 0x20, 0x01, 0xEF, 0x80
-	};
+	const uint8_t tx_dump_error[] = { 0xFB, 0x20, 0x01, 0xEF, 0x80 };
 	uint32_t dump_info[2];
-	const uint8_t tx_dump_memory[] = {
-		0xFB, 0x00, 0x10, 0x00, 0x00
-	};
+	const uint8_t tx_dump_memory[] = { 0xFB, 0x00, 0x10, 0x00, 0x00 };
 	uint32_t dump_memory[16];
 	int i;
 
@@ -1398,14 +1370,10 @@ static void touchpad_collect_error(void)
 	CPRINTS("check memory dump:");
 	for (i = 0; i < ARRAY_SIZE(dump_memory); i += 8) {
 		CPRINTF("%08x %08x %08x %08x %08x %08x %08x %08x\n",
-			dump_memory[i + 0],
-			dump_memory[i + 1],
-			dump_memory[i + 2],
-			dump_memory[i + 3],
-			dump_memory[i + 4],
-			dump_memory[i + 5],
-			dump_memory[i + 6],
-			dump_memory[i + 7]);
+			dump_memory[i + 0], dump_memory[i + 1],
+			dump_memory[i + 2], dump_memory[i + 3],
+			dump_memory[i + 4], dump_memory[i + 5],
+			dump_memory[i + 6], dump_memory[i + 7]);
 	}
 
 	for (i = 0; i < 3; i++)
@@ -1509,7 +1477,7 @@ void touchpad_task(void *u)
 #if defined(CONFIG_USB_SUSPEND) || defined(CONFIG_TABLET_MODE)
 static void touchpad_power_change(void)
 {
-	task_set_event(TASK_ID_TOUCHPAD, TASK_EVENT_POWER, 0);
+	task_set_event(TASK_ID_TOUCHPAD, TASK_EVENT_POWER);
 }
 #endif
 #ifdef CONFIG_USB_SUSPEND
@@ -1522,9 +1490,9 @@ DECLARE_HOOK(HOOK_TABLET_MODE_CHANGE, touchpad_power_change, HOOK_PRIO_DEFAULT);
 #ifdef CONFIG_USB_ISOCHRONOUS
 static void st_tp_enable_heat_map(void)
 {
-	int new_state = (SYSTEM_STATE_ENABLE_HEAT_MAP |
-			 SYSTEM_STATE_ENABLE_DOME_SWITCH |
-			 SYSTEM_STATE_ACTIVE_MODE);
+	int new_state =
+		(SYSTEM_STATE_ENABLE_HEAT_MAP |
+		 SYSTEM_STATE_ENABLE_DOME_SWITCH | SYSTEM_STATE_ACTIVE_MODE);
 	int mask = new_state;
 
 	st_tp_update_system_state(new_state, mask);
@@ -1619,8 +1587,8 @@ static int st_tp_read_frame(void)
 	 * valid, but the data should always be ready when interrupt pin is low.
 	 * Let's skip this check for now.
 	 */
-	ret = spi_transaction(SPI, tx_buf, sizeof(tx_buf),
-			      (uint8_t *)rx_buf, rx_len);
+	ret = spi_transaction(SPI, tx_buf, sizeof(tx_buf), (uint8_t *)rx_buf,
+			      rx_len);
 	if (ret == EC_SUCCESS) {
 		int i;
 		uint8_t *dest = usb_packet[spi_buffer_index & 1].frame;
@@ -1649,16 +1617,12 @@ static int heatmap_send_packet(struct usb_isochronous_config const *config);
 static void st_tp_usb_tx_callback(struct usb_isochronous_config const *config);
 
 /* USB descriptors */
-USB_ISOCHRONOUS_CONFIG_FULL(usb_st_tp_heatmap_config,
-			    USB_IFACE_ST_TOUCHPAD,
-			    USB_CLASS_VENDOR_SPEC,
-			    USB_SUBCLASS_GOOGLE_HEATMAP,
+USB_ISOCHRONOUS_CONFIG_FULL(usb_st_tp_heatmap_config, USB_IFACE_ST_TOUCHPAD,
+			    USB_CLASS_VENDOR_SPEC, USB_SUBCLASS_GOOGLE_HEATMAP,
 			    USB_PROTOCOL_GOOGLE_HEATMAP,
-			    USB_STR_HEATMAP_NAME,  /* interface name */
-			    USB_EP_ST_TOUCHPAD,
-			    USB_ISO_PACKET_SIZE,
-			    st_tp_usb_tx_callback,
-			    st_tp_usb_set_interface,
+			    USB_STR_HEATMAP_NAME, /* interface name */
+			    USB_EP_ST_TOUCHPAD, USB_ISO_PACKET_SIZE,
+			    st_tp_usb_tx_callback, st_tp_usb_set_interface,
 			    1 /* 1 extra EP for interrupts */)
 
 /* ***This function will be executed in interrupt context*** */
@@ -1703,13 +1667,10 @@ static int heatmap_send_packet(struct usb_isochronous_config const *config)
 	if (num_byte_available > 0) {
 		if (transmit_report_offset == 0)
 			packet_header.flags |= HEADER_FLAGS_NEW_FRAME;
-		ret = usb_isochronous_write_buffer(
-				config,
-				(uint8_t *)&packet_header,
-				sizeof(packet_header),
-				offset,
-				&buffer_id,
-				0);
+		ret = usb_isochronous_write_buffer(config,
+						   (uint8_t *)&packet_header,
+						   sizeof(packet_header),
+						   offset, &buffer_id, 0);
 		/*
 		 * Since USB_ISO_PACKET_SIZE > sizeof(packet_header), this must
 		 * be true.
@@ -1721,12 +1682,8 @@ static int heatmap_send_packet(struct usb_isochronous_config const *config)
 		packet_header.index++;
 
 		ret = usb_isochronous_write_buffer(
-				config,
-				(uint8_t *)packet + transmit_report_offset,
-				num_byte_available,
-				offset,
-				&buffer_id,
-				1);
+			config, (uint8_t *)packet + transmit_report_offset,
+			num_byte_available, offset, &buffer_id, 1);
 		if (ret < 0) {
 			/*
 			 * TODO(b/70482333): handle this error, it might be:
@@ -1766,7 +1723,7 @@ static int st_tp_usb_set_interface(usb_uint alternate_setting,
 	} else if (alternate_setting == 0) {
 		hook_call_deferred(&st_tp_disable_heat_map_data, 0);
 		return 0;
-	} else  /* we only have two settings. */
+	} else /* we only have two settings. */
 		return -1;
 }
 
@@ -1785,12 +1742,12 @@ static int get_heat_map_addr(void)
 }
 
 struct st_tp_interrupt_t {
-#define ST_TP_INT_FRAME_AVAILABLE	BIT(0)
+#define ST_TP_INT_FRAME_AVAILABLE BIT(0)
 	uint8_t flags;
 } __packed;
 
-static usb_uint st_tp_usb_int_buffer[
-	DIV_ROUND_UP(sizeof(struct st_tp_interrupt_t), 2)] __usb_ram;
+static usb_uint st_tp_usb_int_buffer[DIV_ROUND_UP(
+	sizeof(struct st_tp_interrupt_t), 2)] __usb_ram;
 
 const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_ST_TOUCHPAD, 81) = {
 	.bLength = USB_DT_ENDPOINT_SIZE,
@@ -1809,8 +1766,8 @@ static void st_tp_interrupt_send(void)
 
 	if (usb_buffer_index < spi_buffer_index)
 		report.flags |= ST_TP_INT_FRAME_AVAILABLE;
-	memcpy_to_usbram((void *)usb_sram_addr(st_tp_usb_int_buffer),
-			 &report, sizeof(report));
+	memcpy_to_usbram((void *)usb_sram_addr(st_tp_usb_int_buffer), &report,
+			 sizeof(report));
 	/* enable TX */
 	STM32_TOGGLE_EP(USB_EP_ST_TOUCHPAD_INT, EP_TX_MASK, EP_TX_VALID, 0);
 	usb_wake();
@@ -1833,10 +1790,8 @@ static void st_tp_interrupt_event(enum usb_ep_event evt)
 		btable_ep[ep].tx_addr = usb_sram_addr(st_tp_usb_int_buffer);
 		btable_ep[ep].tx_count = sizeof(struct st_tp_interrupt_t);
 
-		STM32_USB_EP(ep) = ((ep << 0) |
-				    EP_TX_VALID |
-				    (3 << 9) /* interrupt EP */ |
-				    EP_RX_DISAB);
+		STM32_USB_EP(ep) = ((ep << 0) | EP_TX_VALID |
+				    (3 << 9) /* interrupt EP */ | EP_RX_DISAB);
 	}
 }
 
@@ -1846,7 +1801,7 @@ USB_DECLARE_EP(USB_EP_ST_TOUCHPAD_INT, st_tp_interrupt_tx, st_tp_interrupt_tx,
 #endif
 
 /* Debugging commands */
-static int command_touchpad_st(int argc, char **argv)
+static int command_touchpad_st(int argc, const char **argv)
 {
 	if (argc < 2)
 		return EC_ERROR_PARAM_COUNT;
diff --git a/driver/touchpad_st.h b/driver/touchpad_st.h
index a6534f278f..ec3fe0686b 100644
--- a/driver/touchpad_st.h
+++ b/driver/touchpad_st.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,75 +6,73 @@
 #ifndef __CROS_EC_TOUCHPAD_ST_H
 #define __CROS_EC_TOUCHPAD_ST_H
 
-#include <stdint.h>
-
 #include "common.h"
 
-#define ST_VENDOR_ID		0x0483
+#include <stdint.h>
+
+#define ST_VENDOR_ID 0x0483
 
-#define ST_TP_EXTRA_BYTE	1
+#define ST_TP_EXTRA_BYTE 1
 
-#define ST_TP_CMD_READ_ALL_EVENTS		0x87
-#define ST_TP_CMD_WRITE_SCAN_MODE_SELECT	0xA0
-#define ST_TP_CMD_WRITE_FEATURE_SELECT		0xA2
-#define ST_TP_CMD_WRITE_SYSTEM_COMMAND		0xA4
-#define ST_TP_CMD_WRITE_HOST_DATA_MEMORY	0xA6
-#define ST_TP_CMD_READ_HOST_DATA_MEMORY		0xA7
-#define ST_TP_CMD_WRITE_FW_CONFIG		0xA8
-#define ST_TP_CMD_READ_FW_CONFIG		0xA9
-#define ST_TP_CMD_SPI_HOST_BUFFER_ACK		0xC0
-#define ST_TP_CMD_READ_SPI_HOST_BUFFER		0xC1
+#define ST_TP_CMD_READ_ALL_EVENTS 0x87
+#define ST_TP_CMD_WRITE_SCAN_MODE_SELECT 0xA0
+#define ST_TP_CMD_WRITE_FEATURE_SELECT 0xA2
+#define ST_TP_CMD_WRITE_SYSTEM_COMMAND 0xA4
+#define ST_TP_CMD_WRITE_HOST_DATA_MEMORY 0xA6
+#define ST_TP_CMD_READ_HOST_DATA_MEMORY 0xA7
+#define ST_TP_CMD_WRITE_FW_CONFIG 0xA8
+#define ST_TP_CMD_READ_FW_CONFIG 0xA9
+#define ST_TP_CMD_SPI_HOST_BUFFER_ACK 0xC0
+#define ST_TP_CMD_READ_SPI_HOST_BUFFER 0xC1
 
-#define ST_TP_CMD_WRITE_HW_REG			0xFA
-#define ST_TP_CMD_READ_HW_REG			0xFB
+#define ST_TP_CMD_WRITE_HW_REG 0xFA
+#define ST_TP_CMD_READ_HW_REG 0xFB
 
 /* Max number of bytes that the DMA can burn on the flash in one shot in FTI */
-#define ST_TP_FLASH_BUFFER_SIZE		(64 * 1024)
+#define ST_TP_FLASH_BUFFER_SIZE (64 * 1024)
 /* Max number of bytes that can be written in I2C to the DMA */
-#define ST_TP_DMA_CHUNK_SIZE		32
+#define ST_TP_DMA_CHUNK_SIZE 32
 
-#define ST_HOST_BUFFER_DATA_VALID	BIT(0)
-#define ST_HOST_BUFFER_MT_READY		BIT(3)
-#define ST_HOST_BUFFER_SF_READY		BIT(4)
-#define ST_HOST_BUFFER_SS_READY		BIT(5)
+#define ST_HOST_BUFFER_DATA_VALID BIT(0)
+#define ST_HOST_BUFFER_MT_READY BIT(3)
+#define ST_HOST_BUFFER_SF_READY BIT(4)
+#define ST_HOST_BUFFER_SS_READY BIT(5)
 
-#define ST_TP_SCAN_MODE_ACTIVE		0x00
-#define ST_TP_SCAN_MODE_LOW_POWER	0x01
-#define ST_TP_SCAN_MODE_TUNING_WIZARD	0x02
-#define ST_TP_SCAN_MODE_LOCKED		0x03
+#define ST_TP_SCAN_MODE_ACTIVE 0x00
+#define ST_TP_SCAN_MODE_LOW_POWER 0x01
+#define ST_TP_SCAN_MODE_TUNING_WIZARD 0x02
+#define ST_TP_SCAN_MODE_LOCKED 0x03
 
-#define ST_TOUCH_ROWS		(18)  /* force len */
-#define ST_TOUCH_COLS		(25)  /* sense len */
+#define ST_TOUCH_ROWS (18) /* force len */
+#define ST_TOUCH_COLS (25) /* sense len */
 
-#define ST_TOUCH_HEADER_SIZE	32
+#define ST_TOUCH_HEADER_SIZE 32
 
-#define BYTES_PER_PIXEL		1
+#define BYTES_PER_PIXEL 1
 /* Number of bits per pixel, this value is decided by experiments. */
-#define BITS_PER_PIXEL		8
-
-#define ST_TOUCH_FRAME_SIZE	(ST_TOUCH_ROWS * ST_TOUCH_COLS * \
-				 BYTES_PER_PIXEL)
-#define ST_TOUCH_FORCE_SIZE	(ST_TOUCH_ROWS * BYTES_PER_PIXEL)
-#define ST_TOUCH_SENSE_SIZE	(ST_TOUCH_COLS * BYTES_PER_PIXEL)
+#define BITS_PER_PIXEL 8
 
-#define ST_TP_MEM_ID_SYSTEM_INFO	0x01
+#define ST_TOUCH_FRAME_SIZE (ST_TOUCH_ROWS * ST_TOUCH_COLS * BYTES_PER_PIXEL)
+#define ST_TOUCH_FORCE_SIZE (ST_TOUCH_ROWS * BYTES_PER_PIXEL)
+#define ST_TOUCH_SENSE_SIZE (ST_TOUCH_COLS * BYTES_PER_PIXEL)
 
-#define ST_TP_FLASH_OFFSET_CODE		(0x0000 << 2)
-#define ST_TP_FLASH_OFFSET_PANEL_CFG	(0x6800 << 2)
-#define ST_TP_FLASH_OFFSET_CX		(0x7000 << 2)
-#define ST_TP_FLASH_OFFSET_CONFIG	(0x7C00 << 2)
+#define ST_TP_MEM_ID_SYSTEM_INFO 0x01
 
+#define ST_TP_FLASH_OFFSET_CODE (0x0000 << 2)
+#define ST_TP_FLASH_OFFSET_PANEL_CFG (0x6800 << 2)
+#define ST_TP_FLASH_OFFSET_CX (0x7000 << 2)
+#define ST_TP_FLASH_OFFSET_CONFIG (0x7C00 << 2)
 
 struct st_tp_host_data_header_t {
-#define ST_TP_HEADER_MAGIC	0xA5
-	uint8_t magic;  /* this should always be ST_TP_HEADER_MAGIC */
+#define ST_TP_HEADER_MAGIC 0xA5
+	uint8_t magic; /* this should always be ST_TP_HEADER_MAGIC */
 	uint8_t host_data_mem_id;
 	uint16_t count;
 } __packed;
 
 /* Compute offset of end of a member in given type */
-#define endof(type, member) (offsetof(type, member) + \
-			     sizeof(((type *)NULL)->member))
+#define endof(type, member) \
+	(offsetof(type, member) + sizeof(((type *)NULL)->member))
 
 struct st_tp_system_info_t {
 	/* Part 1, basic info */
@@ -83,7 +81,7 @@ struct st_tp_system_info_t {
 	uint8_t api_ver_minor;
 	uint8_t api_ver_major;
 	uint16_t chip0_ver;
-	uint8_t chip0_id[2];  /* should be 0x3936 */
+	uint8_t chip0_id[2]; /* should be 0x3936 */
 	uint16_t chip1_ver;
 	uint16_t chip1_id;
 	uint16_t fw_ver;
@@ -101,7 +99,7 @@ struct st_tp_system_info_t {
 	uint32_t fw_crc;
 	uint32_t cfg_crc;
 #define ST_TP_SYSTEM_INFO_PART_1_SIZE endof(struct st_tp_system_info_t, cfg_crc)
-#define ST_TP_SYSTEM_INFO_PART_1_RESERVED	16
+#define ST_TP_SYSTEM_INFO_PART_1_RESERVED 16
 
 	uint16_t scr_res_x;
 	uint16_t scr_res_y;
@@ -109,20 +107,18 @@ struct st_tp_system_info_t {
 	uint8_t scr_rx_len;
 	uint8_t key_len;
 	uint8_t frc_len;
-#define ST_TP_SYSTEM_INFO_PART_2_SIZE (endof(struct st_tp_system_info_t, \
-					     frc_len) - \
-				       offsetof(struct st_tp_system_info_t, \
-						scr_res_x))
-#define ST_TP_SYSTEM_INFO_PART_2_RESERVED	40
+#define ST_TP_SYSTEM_INFO_PART_2_SIZE                 \
+	(endof(struct st_tp_system_info_t, frc_len) - \
+	 offsetof(struct st_tp_system_info_t, scr_res_x))
+#define ST_TP_SYSTEM_INFO_PART_2_RESERVED 40
 
-#if 0  /* the following parts are defined in spec, but not currently used. */
+#if 0 /* the following parts are defined in spec, but not currently used. */
 
 	uint16_t dbg_frame_addr;
-#define ST_TP_SYSTEM_INFO_PART_3_SIZE (endof(struct st_tp_system_info_t, \
-					     dbg_frame_addr) - \
-				       offsetof(struct st_tp_system_info_t, \
-						dbg_frame_addr))
-#define ST_TP_SYSTEM_INFO_PART_3_RESERVED	6
+#define ST_TP_SYSTEM_INFO_PART_3_SIZE                        \
+	(endof(struct st_tp_system_info_t, dbg_frame_addr) - \
+	 offsetof(struct st_tp_system_info_t, dbg_frame_addr))
+#define ST_TP_SYSTEM_INFO_PART_3_RESERVED 6
 
 	uint16_t ms_scr_raw_addr;
 	uint16_t ms_scr_filter_addr;
@@ -160,24 +156,23 @@ struct st_tp_system_info_t {
 	uint16_t ss_prx_rx_filter_addr;
 	uint16_t ss_prx_rx_str_addr;
 	uint16_t ss_prx_rx_bl_addr;
-#define ST_TP_SYSTEM_INFO_PART_4_SIZE (endof(struct st_tp_system_info_t, \
-					     ss_prx_rx_bl_addr) - \
-				       offsetof(struct st_tp_system_info_t, \
-						ms_scr_raw_addr))
-#endif  /* if 0 */
+#define ST_TP_SYSTEM_INFO_PART_4_SIZE                           \
+	(endof(struct st_tp_system_info_t, ss_prx_rx_bl_addr) - \
+	 offsetof(struct st_tp_system_info_t, ms_scr_raw_addr))
+#endif /* if 0 */
 } __packed;
 
-#define ST_TP_SYSTEM_INFO_LEN	(sizeof(struct st_tp_system_info_t) + \
-				 ST_TP_SYSTEM_INFO_PART_1_RESERVED)
+#define ST_TP_SYSTEM_INFO_LEN \
+	(sizeof(struct st_tp_system_info_t) + ST_TP_SYSTEM_INFO_PART_1_RESERVED)
 
 struct st_tp_host_buffer_header_t {
-#define ST_TP_BUFFER_HEADER_DATA_VALID		BIT(0)
-#define ST_TP_BUFFER_HEADER_EVT_FIFO_NOT_EMPTY	BIT(1)
-#define ST_TP_BUFFER_HEADER_SYS_FAULT		BIT(2)
-#define ST_TP_BUFFER_HEADER_HEAT_MAP_MT_RDY	BIT(3)
-#define ST_TP_BUFFER_HEADER_HEAT_MAP_SF_RDY	BIT(4)
-#define ST_TP_BUFFER_HEADER_HEAT_MAP_SS_RDY	BIT(5)
-#define ST_TP_BUFFER_HEADER_DOMESWITCH_LVL	BIT(6)
+#define ST_TP_BUFFER_HEADER_DATA_VALID BIT(0)
+#define ST_TP_BUFFER_HEADER_EVT_FIFO_NOT_EMPTY BIT(1)
+#define ST_TP_BUFFER_HEADER_SYS_FAULT BIT(2)
+#define ST_TP_BUFFER_HEADER_HEAT_MAP_MT_RDY BIT(3)
+#define ST_TP_BUFFER_HEADER_HEAT_MAP_SF_RDY BIT(4)
+#define ST_TP_BUFFER_HEADER_HEAT_MAP_SS_RDY BIT(5)
+#define ST_TP_BUFFER_HEADER_DOMESWITCH_LVL BIT(6)
 	uint8_t flags;
 	uint8_t reserved[3];
 	uint8_t heatmap_miss_count;
@@ -187,56 +182,56 @@ struct st_tp_host_buffer_header_t {
 
 struct st_tp_host_buffer_heat_map_t {
 	uint8_t frame[ST_TOUCH_FRAME_SIZE];
-#if 0  /* we are not using these now */
+#if 0 /* we are not using these now */
 	uint8_t force[ST_TOUCH_FORCE_SIZE];
 	uint8_t sense[ST_TOUCH_SENSE_SIZE];
 #endif
 } __packed;
 
 struct st_tp_event_t {
-#define ST_TP_EVENT_MAGIC		0x3
-	unsigned magic:2;  /* should always be 0x3 */
-	unsigned major_high:2;
-#define ST_TP_EVENT_ID_CONTROLLER_READY	0x0
-#define ST_TP_EVENT_ID_ENTER_POINTER	0x1
-#define ST_TP_EVENT_ID_MOTION_POINTER	0x2
-#define ST_TP_EVENT_ID_LEAVE_POINTER	0x3
-#define ST_TP_EVENT_ID_STATUS_REPORT	0x4
-#define ST_TP_EVENT_ID_USER_REPORT	0x5
-#define ST_TP_EVENT_ID_DEBUG_REPORT	0xe
-#define ST_TP_EVENT_ID_ERROR_REPORT	0xf
-	unsigned evt_id:4;
+#define ST_TP_EVENT_MAGIC 0x3
+	unsigned int magic : 2; /* should always be 0x3 */
+	unsigned int major_high : 2;
+#define ST_TP_EVENT_ID_CONTROLLER_READY 0x0
+#define ST_TP_EVENT_ID_ENTER_POINTER 0x1
+#define ST_TP_EVENT_ID_MOTION_POINTER 0x2
+#define ST_TP_EVENT_ID_LEAVE_POINTER 0x3
+#define ST_TP_EVENT_ID_STATUS_REPORT 0x4
+#define ST_TP_EVENT_ID_USER_REPORT 0x5
+#define ST_TP_EVENT_ID_DEBUG_REPORT 0xe
+#define ST_TP_EVENT_ID_ERROR_REPORT 0xf
+	unsigned int evt_id : 4;
 
 	union {
 		struct {
-#define ST_TP_TOUCH_TYPE_INVALID	0x0
-#define ST_TP_TOUCH_TYPE_FINGER		0x1
-#define ST_TP_TOUCH_TYPE_GLOVE		0x2
-#define ST_TP_TOUCH_TYPE_STYLUS		0x3
-#define ST_TP_TOUCH_TYPE_PALM		0x4
-			unsigned touch_type:4;
-			unsigned touch_id:4;
-			unsigned y:12;
-			unsigned x:12;
+#define ST_TP_TOUCH_TYPE_INVALID 0x0
+#define ST_TP_TOUCH_TYPE_FINGER 0x1
+#define ST_TP_TOUCH_TYPE_GLOVE 0x2
+#define ST_TP_TOUCH_TYPE_STYLUS 0x3
+#define ST_TP_TOUCH_TYPE_PALM 0x4
+			unsigned int touch_type : 4;
+			unsigned int touch_id : 4;
+			unsigned int y : 12;
+			unsigned int x : 12;
 			uint8_t z;
-			uint8_t minor:4;  // need to be concat with minor_high
-			uint8_t major:4;  // need to be concat with major_high
+			uint8_t minor : 4; // need to be concat with minor_high
+			uint8_t major : 4; // need to be concat with major_high
 		} __packed finger;
 
 		struct {
-#define ST_TP_STATUS_CMD_ECHO	0x1
-#define ST_TP_STATUS_FRAME_DROP	0x3
-#define ST_TP_STATUS_FCAL	0x5
-#define ST_TP_STATUS_BEACON	0x9
+#define ST_TP_STATUS_CMD_ECHO 0x1
+#define ST_TP_STATUS_FRAME_DROP 0x3
+#define ST_TP_STATUS_FCAL 0x5
+#define ST_TP_STATUS_BEACON 0x9
 			uint8_t report_type;
 			uint8_t info[4];
 			uint8_t reserved;
 		} __packed report;
-	} __packed ; /* anonymous */
+	} __packed; /* anonymous */
 
-	unsigned minor_high:2;
-	unsigned reserved:1;
-	unsigned evt_left:5;
+	unsigned int minor_high : 2;
+	unsigned int reserved : 1;
+	unsigned int evt_left : 5;
 } __packed;
 
 struct st_tp_fw_header_t {
@@ -258,12 +253,12 @@ enum ST_TP_MODE {
 	HEAT_MAP_MODE,
 };
 
-#define ST_TP_DEBUG_CMD_RESET_TOUCHPAD		0x00
-#define ST_TP_DEBUG_CMD_CALIBRATE		0x01
-#define ST_TP_DEBUG_CMD_START_SCAN		0x02
-#define ST_TP_DEBUG_CMD_STOP_SCAN		0x03
-#define ST_TP_DEBUG_CMD_READ_BUF_HEADER		0x04
-#define ST_TP_DEBUG_CMD_READ_EVENTS		0x05
+#define ST_TP_DEBUG_CMD_RESET_TOUCHPAD 0x00
+#define ST_TP_DEBUG_CMD_CALIBRATE 0x01
+#define ST_TP_DEBUG_CMD_START_SCAN 0x02
+#define ST_TP_DEBUG_CMD_STOP_SCAN 0x03
+#define ST_TP_DEBUG_CMD_READ_BUF_HEADER 0x04
+#define ST_TP_DEBUG_CMD_READ_EVENTS 0x05
 
 #define ST_TP_HEAT_MAP_THRESHOLD 10
 
@@ -271,4 +266,3 @@ enum ST_TP_MODE {
 #define ST_TP_MIN_HEATMAP_VERSION 0x12
 
 #endif /* __CROS_EC_TOUCHPAD_ST_H */
-
diff --git a/driver/usb_mux/amd_fp5.c b/driver/usb_mux/amd_fp5.c
index 92c7e682a4..b5aa6d2669 100644
--- a/driver/usb_mux/amd_fp5.c
+++ b/driver/usb_mux/amd_fp5.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,6 +8,7 @@
 #include "amd_fp5.h"
 #include "chipset.h"
 #include "common.h"
+#include "console.h"
 #include "hooks.h"
 #include "i2c.h"
 #include "queue.h"
@@ -21,8 +22,7 @@ static inline int amd_fp5_mux_read(const struct usb_mux *me, uint8_t *val)
 	uint8_t buf[3] = { 0 };
 	int rv;
 
-	rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags,
-		      NULL, 0, buf, 3);
+	rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags, NULL, 0, buf, 3);
 	if (rv)
 		return rv;
 
@@ -33,8 +33,7 @@ static inline int amd_fp5_mux_read(const struct usb_mux *me, uint8_t *val)
 
 static inline int amd_fp5_mux_write(const struct usb_mux *me, uint8_t val)
 {
-	return i2c_write8(me->i2c_port, me->i2c_addr_flags,
-			  me->usb_port, val);
+	return i2c_write8(me->i2c_port, me->i2c_addr_flags, me->usb_port, val);
 }
 
 static int amd_fp5_init(const struct usb_mux *me)
@@ -42,10 +41,18 @@ static int amd_fp5_init(const struct usb_mux *me)
 	return EC_SUCCESS;
 }
 
-static int amd_fp5_set_mux(const struct usb_mux *me, mux_state_t mux_state)
+static int amd_fp5_set_mux(const struct usb_mux *me, mux_state_t mux_state,
+			   bool *ack_required)
 {
 	uint8_t val = 0;
 
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
+	/* This driver treats safe mode as none */
+	if (mux_state & USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
+
 	saved_mux_state[me->usb_port] = mux_state;
 
 	/*
@@ -55,20 +62,22 @@ static int amd_fp5_set_mux(const struct usb_mux *me, mux_state_t mux_state)
 	 * it because a powered down MUX is off.
 	 */
 	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
-		return (mux_state == USB_PD_MUX_NONE)
-			? EC_SUCCESS
-			: EC_ERROR_NOT_POWERED;
+		return (mux_state == USB_PD_MUX_NONE) ? EC_SUCCESS :
+							EC_ERROR_NOT_POWERED;
 
 	if ((mux_state & USB_PD_MUX_USB_ENABLED) &&
-		(mux_state & USB_PD_MUX_DP_ENABLED))
-		val = (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-			? AMD_FP5_MUX_DOCK_INVERTED : AMD_FP5_MUX_DOCK;
+	    (mux_state & USB_PD_MUX_DP_ENABLED))
+		val = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ?
+			      AMD_FP5_MUX_DOCK_INVERTED :
+			      AMD_FP5_MUX_DOCK;
 	else if (mux_state & USB_PD_MUX_USB_ENABLED)
-		val = (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-			? AMD_FP5_MUX_USB_INVERTED : AMD_FP5_MUX_USB;
+		val = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ?
+			      AMD_FP5_MUX_USB_INVERTED :
+			      AMD_FP5_MUX_USB;
 	else if (mux_state & USB_PD_MUX_DP_ENABLED)
-		val = (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-			? AMD_FP5_MUX_DP_INVERTED : AMD_FP5_MUX_DP;
+		val = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ?
+			      AMD_FP5_MUX_DP_INVERTED :
+			      AMD_FP5_MUX_DP;
 
 	return amd_fp5_mux_write(me, val);
 }
@@ -96,21 +105,21 @@ static int amd_fp5_get_mux(const struct usb_mux *me, mux_state_t *mux_state)
 		break;
 	case AMD_FP5_MUX_USB_INVERTED:
 		*mux_state = USB_PD_MUX_USB_ENABLED |
-				USB_PD_MUX_POLARITY_INVERTED;
+			     USB_PD_MUX_POLARITY_INVERTED;
 		break;
 	case AMD_FP5_MUX_DOCK:
 		*mux_state = USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED;
 		break;
 	case AMD_FP5_MUX_DOCK_INVERTED:
-		*mux_state = USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED
-			     | USB_PD_MUX_POLARITY_INVERTED;
+		*mux_state = USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED |
+			     USB_PD_MUX_POLARITY_INVERTED;
 		break;
 	case AMD_FP5_MUX_DP:
 		*mux_state = USB_PD_MUX_DP_ENABLED;
 		break;
 	case AMD_FP5_MUX_DP_INVERTED:
 		*mux_state = USB_PD_MUX_DP_ENABLED |
-				USB_PD_MUX_POLARITY_INVERTED;
+			     USB_PD_MUX_POLARITY_INVERTED;
 		break;
 	case AMD_FP5_MUX_SAFE:
 	default:
@@ -121,16 +130,18 @@ static int amd_fp5_get_mux(const struct usb_mux *me, mux_state_t *mux_state)
 	return EC_SUCCESS;
 }
 
-static struct queue const chipset_reset_queue
-	= QUEUE_NULL(CONFIG_USB_PD_PORT_MAX_COUNT, struct usb_mux *);
+static struct queue const chipset_reset_queue =
+	QUEUE_NULL(CONFIG_USB_PD_PORT_MAX_COUNT, struct usb_mux *);
 
 static void amd_fp5_chipset_reset_delay(void)
 {
 	struct usb_mux *me;
 	int rv;
+	bool unused;
 
 	while (queue_remove_unit(&chipset_reset_queue, &me)) {
-		rv = amd_fp5_set_mux(me, saved_mux_state[me->usb_port]);
+		rv = amd_fp5_set_mux(me, saved_mux_state[me->usb_port],
+				     &unused);
 		if (rv)
 			ccprints("C%d restore mux rv:%d", me->usb_port, rv);
 	}
diff --git a/driver/usb_mux/amd_fp5.h b/driver/usb_mux/amd_fp5.h
index 7534ea0d8a..9a23cf57b0 100644
--- a/driver/usb_mux/amd_fp5.h
+++ b/driver/usb_mux/amd_fp5.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,14 +8,14 @@
 #ifndef __CROS_EC_USB_MUX_AMD_FP5_H
 #define __CROS_EC_USB_MUX_AMD_FP5_H
 
-#define AMD_FP5_MUX_I2C_ADDR_FLAGS	0x5C
+#define AMD_FP5_MUX_I2C_ADDR_FLAGS 0x5C
 
-#define AMD_FP5_MUX_SAFE		0x00
-#define AMD_FP5_MUX_USB			0x02
-#define AMD_FP5_MUX_USB_INVERTED	0x11
-#define AMD_FP5_MUX_DOCK		0x06
-#define AMD_FP5_MUX_DOCK_INVERTED	0x19
-#define AMD_FP5_MUX_DP			0x0C
-#define AMD_FP5_MUX_DP_INVERTED		0x1C
+#define AMD_FP5_MUX_SAFE 0x00
+#define AMD_FP5_MUX_USB 0x02
+#define AMD_FP5_MUX_USB_INVERTED 0x11
+#define AMD_FP5_MUX_DOCK 0x06
+#define AMD_FP5_MUX_DOCK_INVERTED 0x19
+#define AMD_FP5_MUX_DP 0x0C
+#define AMD_FP5_MUX_DP_INVERTED 0x1C
 
 #endif /* __CROS_EC_USB_MUX_AMD_FP5_H */
diff --git a/driver/usb_mux/amd_fp6.c b/driver/usb_mux/amd_fp6.c
new file mode 100644
index 0000000000..ff3b6eacb8
--- /dev/null
+++ b/driver/usb_mux/amd_fp6.c
@@ -0,0 +1,236 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * AMD FP6 USB/DP Mux.
+ */
+
+#include "amd_fp6.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "queue.h"
+#include "timer.h"
+#include "usb_mux.h"
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/*
+ * The recommendation from "3.3.2 Command Timeout" is 250ms,
+ * however empirical testing found that a 100ms timeout is sufficient.
+ */
+#define WRITE_CMD_TIMEOUT_MS 100
+
+/* Command retry interval */
+#define CMD_RETRY_INTERVAL_MS 1000
+
+/*
+ * Local data structure for saving mux state so it can be restored after
+ * an AP reset.
+ */
+static struct {
+	const struct usb_mux *mux;
+	uint8_t val;
+	bool write_pending;
+} saved_mux_state[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+static int amd_fp6_mux_port0_read(const struct usb_mux *me, uint8_t *val)
+{
+	uint8_t payload[3] = { 0 };
+	bool mux_ready;
+
+	RETURN_ERROR(i2c_xfer(me->i2c_port, me->i2c_addr_flags, NULL, 0,
+			      payload, 3));
+
+	/*
+	 * payload[0]: Status/ID
+	 * payload[1]: Port 0 Control/Status
+	 * payload[2]: Port 1 Control/Status (unused on FP6)
+	 */
+	mux_ready = !!((payload[0] >> AMD_FP6_MUX_PD_STATUS_OFFSET) &
+		       AMD_FP6_MUX_PD_STATUS_READY);
+
+	if (!mux_ready)
+		return EC_ERROR_BUSY;
+	*val = payload[1];
+
+	return EC_SUCCESS;
+}
+
+static int amd_fp6_mux_port0_write(const struct usb_mux *me, uint8_t write_val)
+{
+	uint8_t read_val;
+	uint8_t port_status;
+	timestamp_t start;
+
+	/* Check if mux is ready */
+	RETURN_ERROR(amd_fp6_mux_port0_read(me, &read_val));
+
+	/* Write control register */
+	RETURN_ERROR(
+		i2c_write8(me->i2c_port, me->i2c_addr_flags, 0, write_val));
+
+	/*
+	 * Read status until write command finishes or times out.
+	 * The mux has an internal opaque timeout, which we wrap with our own
+	 * timeout to be safe.
+	 */
+	start = get_time();
+	while (time_since32(start) < WRITE_CMD_TIMEOUT_MS * MSEC) {
+		RETURN_ERROR(amd_fp6_mux_port0_read(me, &read_val));
+		port_status = read_val >> AMD_FP6_MUX_PORT_STATUS_OFFSET;
+
+		if (port_status == AMD_FP6_MUX_PORT_CMD_COMPLETE)
+			return EC_SUCCESS;
+		else if (port_status == AMD_FP6_MUX_PORT_CMD_TIMEOUT)
+			return EC_ERROR_TIMEOUT;
+		else if (port_status == AMD_FP6_MUX_PORT_CMD_BUSY)
+			msleep(5);
+		else
+			return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_ERROR_TIMEOUT;
+}
+
+/*
+ * Keep trying to write the saved mux state until successful or SOC leaves
+ * S0 power state.
+ */
+static void amd_fp6_set_mux_retry(void);
+DECLARE_DEFERRED(amd_fp6_set_mux_retry);
+static void amd_fp6_set_mux_retry(void)
+{
+	int rv;
+	bool try_again = false;
+
+	/*
+	 * Mux can only be written in S0, stop trying.
+	 * Will try again on chipset_resume.
+	 */
+	if (!chipset_in_state(CHIPSET_STATE_ON))
+		return;
+
+	for (int i = 0; i < ARRAY_SIZE(saved_mux_state); i++) {
+		/* Make sure mux_state is initialized */
+		if (saved_mux_state[i].mux == NULL ||
+		    !saved_mux_state[i].write_pending)
+			continue;
+
+		rv = amd_fp6_mux_port0_write(saved_mux_state[i].mux,
+					     saved_mux_state[i].val);
+
+		if (rv)
+			try_again = true;
+		else
+			saved_mux_state[i].write_pending = false;
+	}
+	if (try_again)
+		hook_call_deferred(&amd_fp6_set_mux_retry_data,
+				   CMD_RETRY_INTERVAL_MS * MSEC);
+}
+
+static int amd_fp6_set_mux(const struct usb_mux *me, mux_state_t mux_state,
+			   bool *ack_required)
+{
+	uint8_t val;
+
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
+	/* This driver treats safe mode as none */
+	if (mux_state & USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
+
+	if (mux_state == USB_PD_MUX_NONE)
+		/*
+		 * LOW_POWER must be set when connection mode is
+		 * set to 00b (safe state)
+		 */
+		val = AMD_FP6_MUX_MODE_SAFE | AMD_FP6_MUX_LOW_POWER;
+	else if ((mux_state & USB_PD_MUX_USB_ENABLED) &&
+		 (mux_state & USB_PD_MUX_DP_ENABLED))
+		val = AMD_FP6_MUX_MODE_DOCK;
+	else if (mux_state & USB_PD_MUX_USB_ENABLED)
+		val = AMD_FP6_MUX_MODE_USB;
+	else if (mux_state & USB_PD_MUX_DP_ENABLED)
+		val = AMD_FP6_MUX_MODE_DP;
+	else {
+		CPRINTSUSB("C%d: unhandled mux_state %x\n", me->usb_port,
+			   mux_state);
+		return EC_ERROR_INVAL;
+	}
+
+	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
+		val |= AMD_FP6_MUX_ORIENTATION;
+
+	saved_mux_state[me->usb_port].mux = me;
+	saved_mux_state[me->usb_port].val = val;
+
+	/* Mux is not powered in Z1 */
+	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
+		return (mux_state == USB_PD_MUX_NONE) ? EC_SUCCESS :
+							EC_ERROR_NOT_POWERED;
+
+	saved_mux_state[me->usb_port].write_pending = true;
+	amd_fp6_set_mux_retry();
+
+	return EC_SUCCESS;
+}
+
+static int amd_fp6_get_mux(const struct usb_mux *me, mux_state_t *mux_state)
+{
+	uint8_t val;
+	bool inverted;
+	uint8_t mode;
+
+	/* Mux is not powered in Z1 */
+	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
+		return USB_PD_MUX_NONE;
+
+	RETURN_ERROR(amd_fp6_mux_port0_read(me, &val));
+
+	mode = (val & AMD_FP6_MUX_MODE_MASK);
+	inverted = !!(val & AMD_FP6_MUX_ORIENTATION);
+
+	if (mode == AMD_FP6_MUX_MODE_USB)
+		*mux_state = USB_PD_MUX_USB_ENABLED;
+	else if (mode == AMD_FP6_MUX_MODE_DP)
+		*mux_state = USB_PD_MUX_DP_ENABLED;
+	else if (mode == AMD_FP6_MUX_MODE_DOCK)
+		*mux_state = USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED;
+	else /* AMD_FP6_MUX_MODE_SAFE */
+		*mux_state = USB_PD_MUX_NONE;
+
+	if (inverted)
+		*mux_state |= USB_PD_MUX_POLARITY_INVERTED;
+
+	return EC_SUCCESS;
+}
+
+/*
+ * The FP6 USB Mux will not be ready for writing until *sometime* after S0.
+ */
+static void amd_fp6_chipset_resume(void)
+{
+	for (int i = 0; i < ARRAY_SIZE(saved_mux_state); i++)
+		saved_mux_state[i].write_pending = true;
+	hook_call_deferred(&amd_fp6_set_mux_retry_data,
+			   CMD_RETRY_INTERVAL_MS * MSEC);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, amd_fp6_chipset_resume, HOOK_PRIO_DEFAULT);
+
+static int amd_fp6_chipset_reset(const struct usb_mux *me)
+{
+	amd_fp6_chipset_resume();
+	return EC_SUCCESS;
+}
+
+const struct usb_mux_driver amd_fp6_usb_mux_driver = {
+	.set = &amd_fp6_set_mux,
+	.get = &amd_fp6_get_mux,
+	.chipset_reset = &amd_fp6_chipset_reset
+};
diff --git a/driver/usb_mux/amd_fp6.h b/driver/usb_mux/amd_fp6.h
new file mode 100644
index 0000000000..ba2b791ba5
--- /dev/null
+++ b/driver/usb_mux/amd_fp6.h
@@ -0,0 +1,31 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * AMD FP6 USB/DP Mux.
+ */
+
+#ifndef __CROS_EC_USB_MUX_AMD_FP6_H
+#define __CROS_EC_USB_MUX_AMD_FP6_H
+
+#define AMD_FP6_C0_MUX_I2C_ADDR 0x5C
+#define AMD_FP6_C4_MUX_I2C_ADDR 0x52
+
+#define AMD_FP6_MUX_MODE_SAFE 0x0
+#define AMD_FP6_MUX_MODE_USB 0x1
+#define AMD_FP6_MUX_MODE_DP 0x2
+#define AMD_FP6_MUX_MODE_DOCK 0x3
+#define AMD_FP6_MUX_MODE_MASK GENMASK(1, 0)
+
+#define AMD_FP6_MUX_ORIENTATION BIT(4)
+#define AMD_FP6_MUX_LOW_POWER BIT(5)
+
+#define AMD_FP6_MUX_PORT_STATUS_OFFSET 6
+#define AMD_FP6_MUX_PORT_CMD_BUSY 0x0
+#define AMD_FP6_MUX_PORT_CMD_COMPLETE 0x1
+#define AMD_FP6_MUX_PORT_CMD_TIMEOUT 0x2
+
+#define AMD_FP6_MUX_PD_STATUS_READY BIT(5)
+#define AMD_FP6_MUX_PD_STATUS_OFFSET 1
+
+#endif /* __CROS_EC_USB_MUX_AMD_FP6_H */
diff --git a/driver/usb_mux/anx3443.c b/driver/usb_mux/anx3443.c
new file mode 100644
index 0000000000..e8c2621a54
--- /dev/null
+++ b/driver/usb_mux/anx3443.c
@@ -0,0 +1,225 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * ANX3443: 10G Active Mux (6x4) with
+ * Integrated Re-timers for USB3.2/DisplayPort
+ */
+
+#include "anx3443.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "time.h"
+#include "usb_mux.h"
+#include "util.h"
+
+/*
+ * Empirical testing found it takes ~12ms to wake mux.
+ * Setting timeout to 20ms for some buffer.
+ */
+#define ANX3443_I2C_WAKE_TIMEOUT_MS 20
+#define ANX3443_I2C_WAKE_RETRY_DELAY_US 500
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+static struct {
+	mux_state_t mux_state;
+	bool awake;
+} saved_mux_state[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+static inline int anx3443_read(const struct usb_mux *me, uint8_t reg, int *val)
+{
+	return i2c_read8(me->i2c_port, me->i2c_addr_flags, reg, val);
+}
+
+static inline int anx3443_write(const struct usb_mux *me, uint8_t reg,
+				uint8_t val)
+{
+	return i2c_write8(me->i2c_port, me->i2c_addr_flags, reg, val);
+}
+
+static int anx3443_power_off(const struct usb_mux *me)
+{
+	/**
+	 * No-op if the mux is already down.
+	 *
+	 * Writing or reading any register wakes the mux up.
+	 */
+	if (!saved_mux_state[me->usb_port].awake)
+		return EC_SUCCESS;
+
+	/*
+	 * The mux will not send an acknowledgment when powered off, so ignore
+	 * response and always return success.
+	 */
+	anx3443_write(me, ANX3443_REG_POWER_CNTRL, ANX3443_POWER_CNTRL_OFF);
+	saved_mux_state[me->usb_port].awake = false;
+	return EC_SUCCESS;
+}
+
+static int anx3443_wake_up(const struct usb_mux *me)
+{
+	timestamp_t start;
+	int rv;
+	int val;
+
+	/* Keep reading top register until mux wakes up or timesout */
+	start = get_time();
+	do {
+		rv = anx3443_read(me, 0x0, &val);
+		if (!rv)
+			break;
+		usleep(ANX3443_I2C_WAKE_RETRY_DELAY_US);
+	} while (time_since32(start) < ANX3443_I2C_WAKE_TIMEOUT_MS * MSEC);
+	if (rv) {
+		CPRINTS("ANX3443: Failed to wake mux rv:%d", rv);
+		return EC_ERROR_TIMEOUT;
+	}
+
+	/* ULTRA_LOW_POWER must always be disabled (Fig 2-2) */
+	RETURN_ERROR(anx3443_write(me, ANX3443_REG_ULTRA_LOW_POWER,
+				   ANX3443_ULTRA_LOW_POWER_DIS));
+	saved_mux_state[me->usb_port].awake = true;
+
+	return EC_SUCCESS;
+}
+
+static int anx3443_set_mux(const struct usb_mux *me, mux_state_t mux_state,
+			   bool *ack_required)
+{
+	int reg;
+
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
+	/* This driver treats safe mode as none */
+	if (mux_state & USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
+
+	saved_mux_state[me->usb_port].mux_state = mux_state;
+
+	/* To disable both DP and USB the mux must be powered off. */
+	if (!(mux_state & (USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED)))
+		return anx3443_power_off(me);
+
+	/**
+	 * If the request state is not NONE, process it after we back to
+	 * S0.
+	 */
+	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
+		return EC_SUCCESS;
+
+	RETURN_ERROR(anx3443_wake_up(me));
+
+	/* ULP_CFG_MODE_EN overrides pin control. Always set it */
+	reg = ANX3443_ULP_CFG_MODE_EN;
+	if (mux_state & USB_PD_MUX_USB_ENABLED)
+		reg |= ANX3443_ULP_CFG_MODE_USB_EN;
+	if (mux_state & USB_PD_MUX_DP_ENABLED)
+		reg |= ANX3443_ULP_CFG_MODE_DP_EN;
+	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
+		reg |= ANX3443_ULP_CFG_MODE_FLIP;
+
+	return anx3443_write(me, ANX3443_REG_ULP_CFG_MODE, reg);
+}
+
+static int anx3443_get_mux(const struct usb_mux *me, mux_state_t *mux_state)
+{
+	int reg;
+
+	/* Mux is not powered in Z1 */
+	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
+		return USB_PD_MUX_NONE;
+
+	RETURN_ERROR(anx3443_wake_up(me));
+
+	*mux_state = 0;
+	RETURN_ERROR(anx3443_read(me, ANX3443_REG_ULP_CFG_MODE, &reg));
+
+	if (reg & ANX3443_ULP_CFG_MODE_USB_EN)
+		*mux_state |= USB_PD_MUX_USB_ENABLED;
+	if (reg & ANX3443_ULP_CFG_MODE_DP_EN)
+		*mux_state |= USB_PD_MUX_DP_ENABLED;
+	if (reg & ANX3443_ULP_CFG_MODE_FLIP)
+		*mux_state |= USB_PD_MUX_POLARITY_INVERTED;
+
+	return EC_SUCCESS;
+}
+
+static int anx3443_init(const struct usb_mux *me)
+{
+	uint64_t now;
+	bool unused;
+
+	/*
+	 * ANX3443 requires 30ms to power on. EC and ANX3443 are on the same
+	 * power rail, so just wait 30ms since EC boot.
+	 */
+	now = get_time().val;
+	if (now < ANX3443_I2C_READY_DELAY)
+		usleep(ANX3443_I2C_READY_DELAY - now);
+
+	RETURN_ERROR(anx3443_wake_up(me));
+
+	/*
+	 * Note that bypassing the usb_mux API is okay for internal driver calls
+	 * since the task calling init already holds this port's mux lock.
+	 */
+	/* Default to USB mode */
+	RETURN_ERROR(anx3443_set_mux(me, USB_PD_MUX_USB_ENABLED, &unused));
+
+	return EC_SUCCESS;
+}
+
+const struct usb_mux_driver anx3443_usb_mux_driver = {
+	.init = anx3443_init,
+	.set = anx3443_set_mux,
+	.get = anx3443_get_mux,
+};
+
+static bool anx3443_port_is_usb2_only(const struct usb_mux *me)
+{
+	int val;
+	int port = me->usb_port;
+
+	if (!(saved_mux_state[port].mux_state & USB_PD_MUX_USB_ENABLED))
+		return false;
+
+	if (anx3443_read(me, ANX3443_REG_USB_STATUS, &val))
+		return false;
+
+	return !(val & ANX3443_UP_EN_RTERM_ST);
+}
+
+static void anx3443_suspend(void)
+{
+	for (int i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		const struct usb_mux *mux = usb_muxes[i].mux;
+
+		if (mux->driver != &anx3443_usb_mux_driver)
+			continue;
+
+		if (anx3443_port_is_usb2_only(mux))
+			anx3443_power_off(mux);
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, anx3443_suspend, HOOK_PRIO_DEFAULT);
+
+static void anx3443_resume(void)
+{
+	for (int i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		int port = usb_muxes[i].mux->usb_port;
+		bool ack_required;
+
+		if (usb_muxes[i].mux->driver != &anx3443_usb_mux_driver)
+			continue;
+
+		anx3443_set_mux(usb_muxes[i].mux,
+				saved_mux_state[port].mux_state, &ack_required);
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, anx3443_resume, HOOK_PRIO_DEFAULT);
diff --git a/driver/usb_mux/anx3443.h b/driver/usb_mux/anx3443.h
new file mode 100644
index 0000000000..bd2dc2bf45
--- /dev/null
+++ b/driver/usb_mux/anx3443.h
@@ -0,0 +1,45 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * ANX3443: 10G Active Mux (6x4) with
+ * Integrated Re-timers for USB3.2/DisplayPort
+ */
+
+#ifndef __CROS_EC_USB_MUX_ANX3443_H
+#define __CROS_EC_USB_MUX_ANX3443_H
+
+#define ANX3443_I2C_READY_DELAY (30 * MSEC)
+
+/* I2C interface addresses */
+#define ANX3443_I2C_ADDR0_FLAGS 0x10
+#define ANX3443_I2C_ADDR1_FLAGS 0x14
+#define ANX3443_I2C_ADDR2_FLAGS 0x16
+#define ANX3443_I2C_ADDR3_FLAGS 0x11
+
+/* This register is not documented in datasheet. */
+#define ANX3443_REG_POWER_CNTRL 0x2B
+#define ANX3443_POWER_CNTRL_OFF 0xFF
+
+#define ANX3443_REG_USB_STATUS 0xD7
+/* status of downstream RX term */
+#define ANX3443_DN_EN_RTERM_ST BIT(7)
+/* status of upstream RX term */
+#define ANX3443_UP_EN_RTERM_ST BIT(6)
+
+/* Ultra low power control register  */
+#define ANX3443_REG_ULTRA_LOW_POWER 0xE6
+#define ANX3443_ULTRA_LOW_POWER_EN 0x06
+#define ANX3443_ULTRA_LOW_POWER_DIS 0x00
+
+/* Mux control register  */
+#define ANX3443_REG_ULP_CFG_MODE 0xF8
+#define ANX3443_ULP_CFG_MODE_EN BIT(4)
+#define ANX3443_ULP_CFG_MODE_SWAP BIT(3)
+#define ANX3443_ULP_CFG_MODE_FLIP BIT(2)
+#define ANX3443_ULP_CFG_MODE_DP_EN BIT(1)
+#define ANX3443_ULP_CFG_MODE_USB_EN BIT(0)
+
+extern const struct usb_mux_driver anx3443_usb_mux_driver;
+
+#endif /* __CROS_EC_USB_MUX_ANX3443_H */
diff --git a/driver/usb_mux/anx7440.c b/driver/usb_mux/anx7440.c
index df3a9c2682..5a80487e05 100644
--- a/driver/usb_mux/anx7440.c
+++ b/driver/usb_mux/anx7440.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -13,17 +13,16 @@
 #include "usb_mux.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-static inline int anx7440_read(const struct usb_mux *me,
-			       uint8_t reg, int *val)
+static inline int anx7440_read(const struct usb_mux *me, uint8_t reg, int *val)
 {
 	return i2c_read8(me->i2c_port, me->i2c_addr_flags, reg, val);
 }
 
-static inline int anx7440_write(const struct usb_mux *me,
-				uint8_t reg, uint8_t val)
+static inline int anx7440_write(const struct usb_mux *me, uint8_t reg,
+				uint8_t val)
 {
 	return i2c_write8(me->i2c_port, me->i2c_addr_flags, reg, val);
 }
@@ -61,10 +60,18 @@ static int anx7440_init(const struct usb_mux *me)
 }
 
 /* Writes control register to set switch mode */
-static int anx7440_set_mux(const struct usb_mux *me, mux_state_t mux_state)
+static int anx7440_set_mux(const struct usb_mux *me, mux_state_t mux_state,
+			   bool *ack_required)
 {
 	int reg, res;
 
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
+	/* This driver treats safe mode as none */
+	if (mux_state & USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
+
 	res = anx7440_read(me, ANX7440_REG_CHIP_CTRL, &reg);
 	if (res)
 		return res;
diff --git a/driver/usb_mux/anx7440.h b/driver/usb_mux/anx7440.h
index 2147e3146a..3849837cd2 100644
--- a/driver/usb_mux/anx7440.h
+++ b/driver/usb_mux/anx7440.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -16,25 +16,25 @@
 #define I2C_ADDR_USB_MUX1_FLAGS ANX7440_I2C_ADDR2_FLAGS
 
 /* Vendor / Device Id registers and expected fused values */
-#define ANX7440_REG_VENDOR_ID_L    0x00
-#define ANX7440_VENDOR_ID_L        0xaa
-#define ANX7440_REG_VENDOR_ID_H    0x01
-#define ANX7440_VENDOR_ID_H        0xaa
-#define ANX7440_REG_DEVICE_ID_L    0x02
-#define ANX7440_DEVICE_ID_L        0x40
-#define ANX7440_REG_DEVICE_ID_H    0x03
-#define ANX7440_DEVICE_ID_H        0x74
+#define ANX7440_REG_VENDOR_ID_L 0x00
+#define ANX7440_VENDOR_ID_L 0xaa
+#define ANX7440_REG_VENDOR_ID_H 0x01
+#define ANX7440_VENDOR_ID_H 0xaa
+#define ANX7440_REG_DEVICE_ID_L 0x02
+#define ANX7440_DEVICE_ID_L 0x40
+#define ANX7440_REG_DEVICE_ID_H 0x03
+#define ANX7440_DEVICE_ID_H 0x74
 #define ANX7440_REG_DEVICE_VERSION 0x04
-#define ANX7440_DEVICE_VERSION     0xCB
+#define ANX7440_DEVICE_VERSION 0xCB
 
 /* Chip control register for checking mux state */
-#define ANX7440_REG_CHIP_CTRL               0x05
-#define ANX7440_CHIP_CTRL_FINAL_FLIP        BIT(6)
-#define ANX7440_CHIP_CTRL_OP_MODE_FINAL_DP  BIT(5)
+#define ANX7440_REG_CHIP_CTRL 0x05
+#define ANX7440_CHIP_CTRL_FINAL_FLIP BIT(6)
+#define ANX7440_CHIP_CTRL_OP_MODE_FINAL_DP BIT(5)
 #define ANX7440_CHIP_CTRL_OP_MODE_FINAL_USB BIT(4)
-#define ANX7440_CHIP_CTRL_SW_FLIP           BIT(2)
-#define ANX7440_CHIP_CTRL_SW_OP_MODE_DP     BIT(1)
-#define ANX7440_CHIP_CTRL_SW_OP_MODE_USB    BIT(0)
-#define ANX7440_CHIP_CTRL_SW_OP_MODE_CLEAR  0x7
+#define ANX7440_CHIP_CTRL_SW_FLIP BIT(2)
+#define ANX7440_CHIP_CTRL_SW_OP_MODE_DP BIT(1)
+#define ANX7440_CHIP_CTRL_SW_OP_MODE_USB BIT(0)
+#define ANX7440_CHIP_CTRL_SW_OP_MODE_CLEAR 0x7
 
 #endif /* __CROS_EC_USB_MUX_ANX7440_H */
diff --git a/driver/usb_mux/anx7451.c b/driver/usb_mux/anx7451.c
new file mode 100644
index 0000000000..127f0b8e67
--- /dev/null
+++ b/driver/usb_mux/anx7451.c
@@ -0,0 +1,156 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * ANX7451: 10G Active Mux (4x4) with
+ * Integrated Re-timers for USB3.2/DisplayPort
+ */
+
+#include "anx7451.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "i2c.h"
+#include "timer.h"
+#include "usb_mux.h"
+#include "util.h"
+
+/*
+ * Empirical testing found it takes ~12ms to wake mux.
+ * Setting timeout to 20ms for some buffer.
+ */
+#define ANX7451_I2C_WAKE_TIMEOUT_MS 20
+#define ANX7451_I2C_WAKE_RETRY_DELAY_US 500
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+static inline int anx7451_read(const struct usb_mux *me, uint8_t reg, int *val)
+{
+	return i2c_read8(me->i2c_port, me->i2c_addr_flags, reg, val);
+}
+
+static inline int anx7451_write(const struct usb_mux *me, uint8_t reg,
+				uint8_t val)
+{
+	return i2c_write8(me->i2c_port, me->i2c_addr_flags, reg, val);
+}
+
+static int anx7451_power_off(const struct usb_mux *me)
+{
+	/*
+	 * The mux will not send an acknowledgment when powered off, so ignore
+	 * response and always return success.
+	 */
+	anx7451_write(me, ANX7451_REG_POWER_CNTRL, ANX7451_POWER_CNTRL_OFF);
+	return EC_SUCCESS;
+}
+
+static int anx7451_wake_up(const struct usb_mux *me)
+{
+	timestamp_t start;
+	int rv;
+	int val;
+	uint16_t usb_i2c_addr = board_anx7451_get_usb_i2c_addr(me);
+
+	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	/* Keep reading top register until mux wakes up or timesout */
+	start = get_time();
+	do {
+		rv = anx7451_read(me, 0x0, &val);
+		if (!rv)
+			break;
+		usleep(ANX7451_I2C_WAKE_RETRY_DELAY_US);
+	} while (time_since32(start) < ANX7451_I2C_WAKE_TIMEOUT_MS * MSEC);
+	if (rv) {
+		CPRINTS("ANX7451: Failed to wake mux rv:%d", rv);
+		return EC_ERROR_TIMEOUT;
+	}
+
+	/* ULTRA_LOW_POWER must always be disabled (Fig 2-2) */
+	RETURN_ERROR(anx7451_write(me, ANX7451_REG_ULTRA_LOW_POWER,
+				   ANX7451_ULTRA_LOW_POWER_DIS));
+
+	/*
+	 * Configure ANX7451 USB I2C address.
+	 * Shift 1 bit to make 7 bit address an 8 bit address.
+	 */
+	RETURN_ERROR(
+		anx7451_write(me, ANX7451_REG_USB_I2C_ADDR, usb_i2c_addr << 1));
+
+	/* b/185276137: Fix ANX7451 upstream AUX FLIP */
+	RETURN_ERROR(i2c_write8(me->i2c_port, usb_i2c_addr,
+				ANX7451_REG_USB_AUX_FLIP_CTRL,
+				ANX7451_USB_AUX_FLIP_EN));
+
+	return EC_SUCCESS;
+}
+
+static int anx7451_set_mux(const struct usb_mux *me, mux_state_t mux_state,
+			   bool *ack_required)
+{
+	int reg;
+
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
+	/* This driver treats safe mode as none */
+	if (mux_state & USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
+
+	/*
+	 * Mux is not powered in Z1, and will start up in USB mode.  Ensure any
+	 * mux sets when off get run again so we don't leave the retimer on with
+	 * the None mode set
+	 */
+	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	/* To disable both DP and USB the mux must be powered off. */
+	if (!(mux_state & (USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED)))
+		return anx7451_power_off(me);
+
+	RETURN_ERROR(anx7451_wake_up(me));
+
+	/* ULP_CFG_MODE_EN overrides pin control. Always set it */
+	reg = ANX7451_ULP_CFG_MODE_EN;
+	if (mux_state & USB_PD_MUX_USB_ENABLED)
+		reg |= ANX7451_ULP_CFG_MODE_USB_EN;
+	if (mux_state & USB_PD_MUX_DP_ENABLED)
+		reg |= ANX7451_ULP_CFG_MODE_DP_EN;
+	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
+		reg |= ANX7451_ULP_CFG_MODE_FLIP;
+
+	return anx7451_write(me, ANX7451_REG_ULP_CFG_MODE, reg);
+}
+
+static int anx7451_get_mux(const struct usb_mux *me, mux_state_t *mux_state)
+{
+	int reg;
+
+	/* Mux is not powered in Z1 */
+	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
+		return USB_PD_MUX_NONE;
+
+	RETURN_ERROR(anx7451_wake_up(me));
+
+	*mux_state = 0;
+	RETURN_ERROR(anx7451_read(me, ANX7451_REG_ULP_CFG_MODE, &reg));
+
+	if (reg & ANX7451_ULP_CFG_MODE_USB_EN)
+		*mux_state |= USB_PD_MUX_USB_ENABLED;
+	if (reg & ANX7451_ULP_CFG_MODE_DP_EN)
+		*mux_state |= USB_PD_MUX_DP_ENABLED;
+	if (reg & ANX7451_ULP_CFG_MODE_FLIP)
+		*mux_state |= USB_PD_MUX_POLARITY_INVERTED;
+
+	return EC_SUCCESS;
+}
+
+const struct usb_mux_driver anx7451_usb_mux_driver = {
+	.set = anx7451_set_mux,
+	.get = anx7451_get_mux,
+	/* Low power mode is not supported on ANX7451 */
+};
diff --git a/driver/usb_mux/anx7451.h b/driver/usb_mux/anx7451.h
new file mode 100644
index 0000000000..4b63d513fd
--- /dev/null
+++ b/driver/usb_mux/anx7451.h
@@ -0,0 +1,58 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * ANX7451: 10G Active Mux (4x4) with
+ * Integrated Re-timers for USB3.2/DisplayPort
+ */
+
+#ifndef __CROS_EC_USB_MUX_ANX7451_H
+#define __CROS_EC_USB_MUX_ANX7451_H
+
+#include "usb_mux.h"
+
+/* I2C interface addresses */
+#define ANX7451_I2C_ADDR0_FLAGS 0x10
+#define ANX7451_I2C_ADDR1_FLAGS 0x14
+#define ANX7451_I2C_ADDR2_FLAGS 0x16
+#define ANX7451_I2C_ADDR3_FLAGS 0x11
+
+/* This register is not documented in datasheet. */
+#define ANX7451_REG_POWER_CNTRL 0x2B
+#define ANX7451_POWER_CNTRL_OFF 0xFF
+
+/*
+ * Ultra low power control register.
+ * On ANX7451, this register should always be 0 (disabled).
+ * See figure 2-2 in family programming guide.
+ */
+#define ANX7451_REG_ULTRA_LOW_POWER 0xE6
+/* #define ANX7451_ULTRA_LOW_POWER_EN	0x06 */
+#define ANX7451_ULTRA_LOW_POWER_DIS 0x00
+
+/* Mux control register  */
+#define ANX7451_REG_ULP_CFG_MODE 0xF8
+#define ANX7451_ULP_CFG_MODE_EN BIT(4)
+#define ANX7451_ULP_CFG_MODE_SWAP BIT(3)
+#define ANX7451_ULP_CFG_MODE_FLIP BIT(2)
+#define ANX7451_ULP_CFG_MODE_DP_EN BIT(1)
+#define ANX7451_ULP_CFG_MODE_USB_EN BIT(0)
+
+/* Register to set USB I2C address, defaults to 0x29 (7-bit) */
+#define ANX7451_REG_USB_I2C_ADDR 0x38
+
+/* ANX7451 AUX FLIP control */
+#define ANX7451_REG_USB_AUX_FLIP_CTRL 0xA4
+#define ANX7451_USB_AUX_FLIP_EN 0x20
+
+extern const struct usb_mux_driver anx7451_usb_mux_driver;
+
+/*
+ * ANX7451 uses a separate i2c address for USB configuration registers.
+ * This address is not controlled by address straps and defaults to 0x29.
+ * This address may conflict with other ANX74* parts. Implement
+ * board_anx7451_get_usb_i2c_addr to set a non-conflicting 7-bit address.
+ */
+uint16_t board_anx7451_get_usb_i2c_addr(const struct usb_mux *me);
+
+#endif /* __CROS_EC_USB_MUX_ANX7451_H */
diff --git a/driver/usb_mux/it5205.c b/driver/usb_mux/it5205.c
index f275568313..a773a51d0e 100644
--- a/driver/usb_mux/it5205.c
+++ b/driver/usb_mux/it5205.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -25,15 +25,15 @@ static int it5205_write(const struct usb_mux *me, uint8_t reg, uint8_t val)
 static int it5205h_sbu_update(const struct usb_mux *me, uint8_t reg,
 			      uint8_t mask, enum mask_update_action action)
 {
-	return i2c_update8(me->i2c_port, IT5205H_SBU_I2C_ADDR_FLAGS,
-			   reg, mask, action);
+	return i2c_update8(me->i2c_port, IT5205H_SBU_I2C_ADDR_FLAGS, reg, mask,
+			   action);
 }
 
 static int it5205h_sbu_field_update(const struct usb_mux *me, uint8_t reg,
 				    uint8_t field_mask, uint8_t set_value)
 {
-	return i2c_field_update8(me->i2c_port, IT5205H_SBU_I2C_ADDR_FLAGS,
-				 reg, field_mask, set_value);
+	return i2c_field_update8(me->i2c_port, IT5205H_SBU_I2C_ADDR_FLAGS, reg,
+				 field_mask, set_value);
 }
 
 struct mux_chip_id_t {
@@ -42,10 +42,10 @@ struct mux_chip_id_t {
 };
 
 static const struct mux_chip_id_t mux_chip_id_verify[] = {
-	{ '5', IT5205_REG_CHIP_ID3},
-	{ '2', IT5205_REG_CHIP_ID2},
-	{ '0', IT5205_REG_CHIP_ID1},
-	{ '5', IT5205_REG_CHIP_ID0},
+	{ '5', IT5205_REG_CHIP_ID3 },
+	{ '2', IT5205_REG_CHIP_ID2 },
+	{ '0', IT5205_REG_CHIP_ID1 },
+	{ '5', IT5205_REG_CHIP_ID0 },
 };
 
 static int it5205_init(const struct usb_mux *me)
@@ -67,16 +67,16 @@ static int it5205_init(const struct usb_mux *me)
 	}
 
 	if (IS_ENABLED(CONFIG_USB_MUX_IT5205H_SBU_OVP)) {
-		RETURN_ERROR(it5205h_sbu_field_update(me, IT5205H_REG_VSR,
-				IT5205H_VREF_SELECT_MASK,
-				IT5205H_VREF_SELECT_3_3V));
+		RETURN_ERROR(it5205h_sbu_field_update(
+			me, IT5205H_REG_VSR, IT5205H_VREF_SELECT_MASK,
+			IT5205H_VREF_SELECT_3_3V));
 
 		RETURN_ERROR(it5205h_sbu_field_update(me, IT5205H_REG_CSBUOVPSR,
-				IT5205H_OVP_SELECT_MASK,
-				IT5205H_OVP_3_68V));
+						      IT5205H_OVP_SELECT_MASK,
+						      IT5205H_OVP_3_68V));
 
-		RETURN_ERROR(it5205h_sbu_update(me, IT5205H_REG_ISR,
-				IT5205H_ISR_CSBU_MASK, MASK_CLR));
+		RETURN_ERROR(it5205h_sbu_update(
+			me, IT5205H_REG_ISR, IT5205H_ISR_CSBU_MASK, MASK_CLR));
 
 		RETURN_ERROR(it5205h_enable_csbu_switch(me, true));
 	}
@@ -86,15 +86,23 @@ static int it5205_init(const struct usb_mux *me)
 
 enum ec_error_list it5205h_enable_csbu_switch(const struct usb_mux *me, bool en)
 {
-	return it5205h_sbu_update(me, IT5205H_REG_CSBUSR,
-			IT5205H_CSBUSR_SWITCH, en ? MASK_SET : MASK_CLR);
+	return it5205h_sbu_update(me, IT5205H_REG_CSBUSR, IT5205H_CSBUSR_SWITCH,
+				  en ? MASK_SET : MASK_CLR);
 }
 
 /* Writes control register to set switch mode */
-static int it5205_set_mux(const struct usb_mux *me, mux_state_t mux_state)
+static int it5205_set_mux(const struct usb_mux *me, mux_state_t mux_state,
+			  bool *ack_required)
 {
 	uint8_t reg;
 
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
+	/* This driver treats safe mode as none */
+	if (mux_state & USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
+
 	switch (mux_state & MUX_STATE_DP_USB_MASK) {
 	case USB_PD_MUX_USB_ENABLED:
 		reg = IT5205_USB;
diff --git a/driver/usb_mux/it5205.h b/driver/usb_mux/it5205.h
index c4fdc6ce49..6a8fc2bb24 100644
--- a/driver/usb_mux/it5205.h
+++ b/driver/usb_mux/it5205.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,10 +10,7 @@
 
 #include "stdbool.h"
 #include "usb_mux.h"
-
-/* I2C interface */
-#define IT5205_I2C_ADDR1_FLAGS 0x48
-#define IT5205_I2C_ADDR2_FLAGS 0x58
+#include "usb_mux/it5205_public.h"
 
 /* Chip ID registers */
 #define IT5205_REG_CHIP_ID3 0x4
@@ -22,18 +19,17 @@
 #define IT5205_REG_CHIP_ID0 0x7
 
 /* MUX power down register */
-#define IT5205_REG_MUXPDR        0x10
-#define IT5205_MUX_POWER_DOWN    BIT(0)
+#define IT5205_REG_MUXPDR 0x10
+#define IT5205_MUX_POWER_DOWN BIT(0)
 
 /* MUX control register */
-#define IT5205_REG_MUXCR         0x11
+#define IT5205_REG_MUXCR 0x11
 #define IT5205_POLARITY_INVERTED BIT(4)
 
-#define IT5205_DP_USB_CTRL_MASK  0x0f
-#define IT5205_DP                0x0f
-#define IT5205_DP_USB            0x03
-#define IT5205_USB               0x07
-
+#define IT5205_DP_USB_CTRL_MASK 0x0f
+#define IT5205_DP 0x0f
+#define IT5205_DP_USB 0x03
+#define IT5205_USB 0x07
 
 /* IT5205-H SBU module */
 
@@ -41,27 +37,27 @@
 #define IT5205H_SBU_I2C_ADDR_FLAGS 0x6a
 
 /* Vref Select Register */
-#define IT5205H_REG_VSR            0x10
-#define IT5205H_VREF_SELECT_MASK   0x30
-#define IT5205H_VREF_SELECT_3_3V   0x00
-#define IT5205H_VREF_SELECT_OFF    0x20
+#define IT5205H_REG_VSR 0x10
+#define IT5205H_VREF_SELECT_MASK 0x30
+#define IT5205H_VREF_SELECT_3_3V 0x00
+#define IT5205H_VREF_SELECT_OFF 0x20
 
 /* CSBU OVP Select Register */
-#define IT5205H_REG_CSBUOVPSR      0x1e
-#define IT5205H_OVP_SELECT_MASK    0x30
-#define IT5205H_OVP_3_90V          0x00
-#define IT5205H_OVP_3_68V          0x10
-#define IT5205H_OVP_3_62V          0x20
-#define IT5205H_OVP_3_57V          0x30
+#define IT5205H_REG_CSBUOVPSR 0x1e
+#define IT5205H_OVP_SELECT_MASK 0x30
+#define IT5205H_OVP_3_90V 0x00
+#define IT5205H_OVP_3_68V 0x10
+#define IT5205H_OVP_3_62V 0x20
+#define IT5205H_OVP_3_57V 0x30
 
 /* CSBU Switch Register */
-#define IT5205H_REG_CSBUSR         0x22
-#define IT5205H_CSBUSR_SWITCH      BIT(0)
+#define IT5205H_REG_CSBUSR 0x22
+#define IT5205H_CSBUSR_SWITCH BIT(0)
 
 /* Interrupt Switch Register */
-#define IT5205H_REG_ISR            0x25
-#define IT5205H_ISR_CSBU_MASK      BIT(4)
-#define IT5205H_ISR_CSBU_OVP       BIT(0)
+#define IT5205H_REG_ISR 0x25
+#define IT5205H_ISR_CSBU_MASK BIT(4)
+#define IT5205H_ISR_CSBU_OVP BIT(0)
 
 enum ec_error_list it5205h_enable_csbu_switch(const struct usb_mux *me,
 					      bool en);
diff --git a/driver/usb_mux/pi3usb3x532.c b/driver/usb_mux/pi3usb3x532.c
index c3d22b8f61..42d13ca835 100644
--- a/driver/usb_mux/pi3usb3x532.c
+++ b/driver/usb_mux/pi3usb3x532.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,13 +11,12 @@
 #include "usb_mux.h"
 #include "util.h"
 
-static int pi3usb3x532_read(const struct usb_mux *me,
-			    uint8_t reg, uint8_t *val)
+static int pi3usb3x532_read(const struct usb_mux *me, uint8_t reg, uint8_t *val)
 {
 	int read, res;
 
 	/*
-	 * First byte read will be slave address (ignored).
+	 * First byte read will be i2c address (ignored).
 	 * Second byte read will be vendor ID.
 	 * Third byte read will be selection control.
 	 */
@@ -33,8 +32,7 @@ static int pi3usb3x532_read(const struct usb_mux *me,
 	return EC_SUCCESS;
 }
 
-static int pi3usb3x532_write(const struct usb_mux *me,
-			     uint8_t reg, uint8_t val)
+static int pi3usb3x532_write(const struct usb_mux *me, uint8_t reg, uint8_t val)
 {
 	if (reg != PI3USB3X532_REG_CONTROL)
 		return EC_ERROR_UNKNOWN;
@@ -42,13 +40,26 @@ static int pi3usb3x532_write(const struct usb_mux *me,
 	return i2c_write8(me->i2c_port, me->i2c_addr_flags, 0, val);
 }
 
+int pi3usb3x532_check_vendor(const struct usb_mux *me, int *val)
+{
+	int res;
+	uint8_t read;
+
+	res = pi3usb3x532_read(me, PI3USB3X532_REG_VENDOR, &read);
+	if (res)
+		return res;
+
+	*val = read;
+
+	return EC_SUCCESS;
+}
+
 static int pi3usb3x532_reset(const struct usb_mux *me)
 {
-	return pi3usb3x532_write(
-		me,
-		PI3USB3X532_REG_CONTROL,
-		(PI3USB3X532_MODE_POWERDOWN & PI3USB3X532_CTRL_MASK) |
-		PI3USB3X532_CTRL_RSVD);
+	return pi3usb3x532_write(me, PI3USB3X532_REG_CONTROL,
+				 (PI3USB3X532_MODE_POWERDOWN &
+				  PI3USB3X532_CTRL_MASK) |
+					 PI3USB3X532_CTRL_RSVD);
 }
 
 static int pi3usb3x532_init(const struct usb_mux *me)
@@ -69,11 +80,18 @@ static int pi3usb3x532_init(const struct usb_mux *me)
 }
 
 /* Writes control register to set switch mode */
-static int pi3usb3x532_set_mux(const struct usb_mux *me,
-			       mux_state_t mux_state)
+static int pi3usb3x532_set_mux(const struct usb_mux *me, mux_state_t mux_state,
+			       bool *ack_required)
 {
 	uint8_t reg = 0;
 
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
+	/* This driver treats safe mode as none */
+	if (mux_state & USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
+
 	if (mux_state & USB_PD_MUX_USB_ENABLED)
 		reg |= PI3USB3X532_MODE_USB;
 	if (mux_state & USB_PD_MUX_DP_ENABLED)
@@ -86,8 +104,7 @@ static int pi3usb3x532_set_mux(const struct usb_mux *me,
 }
 
 /* Reads control register and updates mux_state accordingly */
-static int pi3usb3x532_get_mux(const struct usb_mux *me,
-			       mux_state_t *mux_state)
+static int pi3usb3x532_get_mux(const struct usb_mux *me, mux_state_t *mux_state)
 {
 	uint8_t reg = 0;
 	uint8_t res;
diff --git a/driver/usb_mux/pi3usb3x532.h b/driver/usb_mux/pi3usb3x532.h
index b8a8fc1691..d0a7abaa89 100644
--- a/driver/usb_mux/pi3usb3x532.h
+++ b/driver/usb_mux/pi3usb3x532.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -12,6 +12,7 @@
 #ifndef __CROS_EC_PI3USB3X532_H
 #define __CROS_EC_PI3USB3X532_H
 
+#include "usb_mux.h"
 #include "usb_pd.h"
 
 /* I2C Addresses */
@@ -69,7 +70,9 @@
  * dp0-1 : rx1, tx1
  * hpd+/-: rfu2, rfu1
  */
-#define PI3USB3X532_MODE_DP_USB_SWAP (PI3USB3X532_MODE_DP_USB | \
-				      PI3USB3X532_BIT_SWAP)
+#define PI3USB3X532_MODE_DP_USB_SWAP \
+	(PI3USB3X532_MODE_DP_USB | PI3USB3X532_BIT_SWAP)
 
+/* Get Vendor ID */
+int pi3usb3x532_check_vendor(const struct usb_mux *me, int *val);
 #endif /* __CROS_EC_PI3USB3X532_H */
diff --git a/driver/usb_mux/ps8740.c b/driver/usb_mux/ps8740.c
index b99c107610..2b412ac35a 100644
--- a/driver/usb_mux/ps8740.c
+++ b/driver/usb_mux/ps8740.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -14,14 +14,12 @@
 
 int ps8740_read(const struct usb_mux *me, uint8_t reg, int *val)
 {
-	return i2c_read8(me->i2c_port, me->i2c_addr_flags,
-			 reg, val);
+	return i2c_read8(me->i2c_port, me->i2c_addr_flags, reg, val);
 }
 
 int ps8740_write(const struct usb_mux *me, uint8_t reg, uint8_t val)
 {
-	return i2c_write8(me->i2c_port, me->i2c_addr_flags,
-			  reg, val);
+	return i2c_write8(me->i2c_port, me->i2c_addr_flags, reg, val);
 }
 
 static int ps8740_init(const struct usb_mux *me)
@@ -42,7 +40,7 @@ static int ps8740_init(const struct usb_mux *me)
 	if (res)
 		return res;
 
-	res  = ps8740_read(me, PS8740_REG_CHIP_ID2, &id2);
+	res = ps8740_read(me, PS8740_REG_CHIP_ID2, &id2);
 	if (res)
 		return res;
 
@@ -70,10 +68,18 @@ static int ps8740_init(const struct usb_mux *me)
 }
 
 /* Writes control register to set switch mode */
-static int ps8740_set_mux(const struct usb_mux *me, mux_state_t mux_state)
+static int ps8740_set_mux(const struct usb_mux *me, mux_state_t mux_state,
+			  bool *ack_required)
 {
 	uint8_t reg = 0;
 
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
+	/* This driver treats safe mode as none */
+	if (mux_state & USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
+
 	if (mux_state & USB_PD_MUX_USB_ENABLED)
 		reg |= PS8740_MODE_USB_ENABLED;
 	if (mux_state & USB_PD_MUX_DP_ENABLED)
@@ -106,10 +112,9 @@ static int ps8740_get_mux(const struct usb_mux *me, mux_state_t *mux_state)
 }
 
 /* Tune USB Tx/Rx Equalization */
-int ps8740_tune_usb_eq(int port, uint8_t tx, uint8_t rx)
+int ps8740_tune_usb_eq(const struct usb_mux *me, uint8_t tx, uint8_t rx)
 {
 	int ret;
-	const struct usb_mux *me = &usb_muxes[port];
 
 	ret = ps8740_write(me, PS8740_REG_USB_EQ_TX, tx);
 	ret |= ps8740_write(me, PS8740_REG_USB_EQ_RX, rx);
diff --git a/driver/usb_mux/ps8740.h b/driver/usb_mux/ps8740.h
index 084719d03e..0b29a80cf1 100644
--- a/driver/usb_mux/ps8740.h
+++ b/driver/usb_mux/ps8740.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,67 +11,67 @@
 
 #include "usb_mux.h"
 
-#define PS8740_I2C_ADDR0_FLAG    0x10
-#define PS8740_I2C_ADDR1_FLAG    0x11
-#define PS8740_I2C_ADDR2_FLAG    0x19
-#define PS8740_I2C_ADDR3_FLAG    0x1a
+#define PS8740_I2C_ADDR0_FLAG 0x10
+#define PS8740_I2C_ADDR1_FLAG 0x11
+#define PS8740_I2C_ADDR2_FLAG 0x19
+#define PS8740_I2C_ADDR3_FLAG 0x1a
 
 /* Mode register for setting mux */
 #define PS8740_REG_MODE 0x00
 #define PS8740_MODE_POLARITY_INVERTED BIT(4)
-#define PS8740_MODE_USB_ENABLED       BIT(5)
-#define PS8740_MODE_DP_ENABLED        BIT(6)
+#define PS8740_MODE_USB_ENABLED BIT(5)
+#define PS8740_MODE_DP_ENABLED BIT(6)
 #ifdef CONFIG_USB_MUX_PS8740
-	#define PS8740_MODE_POWER_DOWN        BIT(7)
+#define PS8740_MODE_POWER_DOWN BIT(7)
 #elif defined(CONFIG_USB_MUX_PS8742)
-	#define PS8740_MODE_CE_DP_ENABLED     BIT(7)
-	/* To reset the state machine to default */
-	#define PS8740_MODE_POWER_DOWN        0
+#define PS8740_MODE_CE_DP_ENABLED BIT(7)
+/* To reset the state machine to default */
+#define PS8740_MODE_POWER_DOWN 0
 #endif
 
 /* Status register for checking mux state */
 #define PS8740_REG_STATUS 0x09
 #define PS8740_STATUS_POLARITY_INVERTED BIT(2)
-#define PS8740_STATUS_USB_ENABLED       BIT(3)
-#define PS8740_STATUS_DP_ENABLED        BIT(4)
-#define PS8740_STATUS_HPD_ASSERTED      BIT(7)
+#define PS8740_STATUS_USB_ENABLED BIT(3)
+#define PS8740_STATUS_DP_ENABLED BIT(4)
+#define PS8740_STATUS_HPD_ASSERTED BIT(7)
 
 /* Chip ID / revision registers and expected fused values */
 #define PS8740_REG_REVISION_ID1 0xf0
 #define PS8740_REG_REVISION_ID2 0xf1
-#define PS8740_REG_CHIP_ID1     0xf2
-#define PS8740_REG_CHIP_ID2     0xf3
+#define PS8740_REG_CHIP_ID1 0xf2
+#define PS8740_REG_CHIP_ID2 0xf3
 #ifdef CONFIG_USB_MUX_PS8740
-	#define PS8740_REVISION_ID1   0x00
-	#define PS8740_REVISION_ID2_0 0x0a
-	#define PS8740_REVISION_ID2_1 0x0b
-	#define PS8740_CHIP_ID1       0x40
+#define PS8740_REVISION_ID1 0x00
+#define PS8740_REVISION_ID2_0 0x0a
+#define PS8740_REVISION_ID2_1 0x0b
+#define PS8740_CHIP_ID1 0x40
 #elif defined(CONFIG_USB_MUX_PS8742)
-	#define PS8740_REVISION_ID1   0x01
-	#define PS8740_REVISION_ID2_0 0x0a
-	#define PS8740_REVISION_ID2_1 0x0a
-	#define PS8740_CHIP_ID1       0x42
+#define PS8740_REVISION_ID1 0x01
+#define PS8740_REVISION_ID2_0 0x0a
+#define PS8740_REVISION_ID2_1 0x0a
+#define PS8740_CHIP_ID1 0x42
 #endif
-#define PS8740_CHIP_ID2         0x87
+#define PS8740_CHIP_ID2 0x87
 
 /* USB equalization settings for Host to Mux */
-#define PS8740_REG_USB_EQ_TX     0x32
+#define PS8740_REG_USB_EQ_TX 0x32
 #define PS8740_USB_EQ_TX_10_1_DB 0x00
 #define PS8740_USB_EQ_TX_14_3_DB 0x20
-#define PS8740_USB_EQ_TX_8_5_DB  0x40
-#define PS8740_USB_EQ_TX_6_5_DB  0x60
+#define PS8740_USB_EQ_TX_8_5_DB 0x40
+#define PS8740_USB_EQ_TX_6_5_DB 0x60
 #define PS8740_USB_EQ_TX_11_5_DB 0x80
-#define PS8740_USB_EQ_TX_9_5_DB  0xc0
-#define PS8740_USB_EQ_TX_7_5_DB  0xe0
+#define PS8740_USB_EQ_TX_9_5_DB 0xc0
+#define PS8740_USB_EQ_TX_7_5_DB 0xe0
 #define PS8740_USB_EQ_TERM_100_OHM (0 << 2)
-#define PS8740_USB_EQ_TERM_85_OHM  BIT(2)
+#define PS8740_USB_EQ_TERM_85_OHM BIT(2)
 
 /* USB equalization settings for Connector to Mux */
-#define PS8740_REG_USB_EQ_RX     0x3b
-#define PS8740_USB_EQ_RX_4_4_DB  0x00
-#define PS8740_USB_EQ_RX_7_0_DB  0x10
-#define PS8740_USB_EQ_RX_8_2_DB  0x20
-#define PS8740_USB_EQ_RX_9_4_DB  0x30
+#define PS8740_REG_USB_EQ_RX 0x3b
+#define PS8740_USB_EQ_RX_4_4_DB 0x00
+#define PS8740_USB_EQ_RX_7_0_DB 0x10
+#define PS8740_USB_EQ_RX_8_2_DB 0x20
+#define PS8740_USB_EQ_RX_9_4_DB 0x30
 #define PS8740_USB_EQ_RX_10_2_DB 0x40
 #define PS8740_USB_EQ_RX_11_4_DB 0x50
 #define PS8740_USB_EQ_RX_14_3_DB 0x60
@@ -84,7 +84,7 @@
 #define PS8740_USB_EQ_RX_20_1_DB 0xd0
 #define PS8740_USB_EQ_RX_21_3_DB 0xe0
 
-int ps8740_tune_usb_eq(int i2c_addr, uint8_t tx, uint8_t rx);
+int ps8740_tune_usb_eq(const struct usb_mux *me, uint8_t tx, uint8_t rx);
 int ps8740_write(const struct usb_mux *me, uint8_t reg, uint8_t val);
 int ps8740_read(const struct usb_mux *me, uint8_t reg, int *val);
 
diff --git a/driver/usb_mux/ps8743.c b/driver/usb_mux/ps8743.c
index 3a9eb1ae40..6c123bb50c 100644
--- a/driver/usb_mux/ps8743.c
+++ b/driver/usb_mux/ps8743.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -6,21 +6,60 @@
  */
 
 #include "common.h"
+#include "hooks.h"
 #include "i2c.h"
 #include "ps8743.h"
 #include "usb_mux.h"
+#include "usb_mux/ps8743_public.h"
+#include "usb_pd.h"
 #include "util.h"
 
+enum usb_conn_status {
+	NO_DEVICE,
+	USB2_CONNECTED,
+	USB3_CONNECTED,
+	UNKNOWN,
+};
+
+static enum usb_conn_status saved_usb_conn_status[CONFIG_USB_PD_PORT_MAX_COUNT];
+
 int ps8743_read(const struct usb_mux *me, uint8_t reg, int *val)
 {
-	return i2c_read8(me->i2c_port, me->i2c_addr_flags,
-			 reg, val);
+	return i2c_read8(me->i2c_port, me->i2c_addr_flags, reg, val);
 }
 
 int ps8743_write(const struct usb_mux *me, uint8_t reg, uint8_t val)
 {
-	return i2c_write8(me->i2c_port, me->i2c_addr_flags,
-			  reg, val);
+	return i2c_write8(me->i2c_port, me->i2c_addr_flags, reg, val);
+}
+
+int ps8743_field_update(const struct usb_mux *me, uint8_t reg, uint8_t mask,
+			uint8_t val)
+{
+	return i2c_field_update8(me->i2c_port, me->i2c_addr_flags, reg, mask,
+				 val);
+}
+
+int ps8743_check_chip_id(const struct usb_mux *me, int *val)
+{
+	int id1;
+	int id2;
+	int res;
+
+	/*
+	 * Verify chip ID registers.
+	 */
+	res = ps8743_read(me, PS8743_REG_CHIP_ID1, &id1);
+	if (res)
+		return res;
+
+	res = ps8743_read(me, PS8743_REG_CHIP_ID2, &id2);
+	if (res)
+		return res;
+
+	*val = (id2 << 8) + id1;
+
+	return EC_SUCCESS;
 }
 
 static int ps8743_init(const struct usb_mux *me)
@@ -41,7 +80,7 @@ static int ps8743_init(const struct usb_mux *me)
 	if (res)
 		return res;
 
-	res  = ps8743_read(me, PS8743_REG_CHIP_ID2, &id2);
+	res = ps8743_read(me, PS8743_REG_CHIP_ID2, &id2);
 	if (res)
 		return res;
 
@@ -72,19 +111,29 @@ static int ps8743_init(const struct usb_mux *me)
 }
 
 /* Writes control register to set switch mode */
-static int ps8743_set_mux(const struct usb_mux *me, mux_state_t mux_state)
+static int ps8743_set_mux(const struct usb_mux *me, mux_state_t mux_state,
+			  bool *ack_required)
 {
 	/*
 	 * For CE_DP, CE_USB, and FLIP, disable pin control and enable I2C
 	 * control.
 	 */
-	uint8_t reg = (PS8743_MODE_IN_HPD_CONTROL |
-		       PS8743_MODE_DP_REG_CONTROL |
-		       PS8743_MODE_USB_REG_CONTROL |
-		       PS8743_MODE_FLIP_REG_CONTROL);
+	uint8_t reg =
+		(PS8743_MODE_IN_HPD_CONTROL | PS8743_MODE_DP_REG_CONTROL |
+		 PS8743_MODE_USB_REG_CONTROL | PS8743_MODE_FLIP_REG_CONTROL);
+
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
+	/* This driver treats safe mode as none */
+	if (mux_state & USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
 
 	if (mux_state & USB_PD_MUX_USB_ENABLED)
 		reg |= PS8743_MODE_USB_ENABLE;
+	else
+		saved_usb_conn_status[me->usb_port] = NO_DEVICE;
+
 	if (mux_state & USB_PD_MUX_DP_ENABLED)
 		reg |= PS8743_MODE_DP_ENABLE | PS8743_MODE_IN_HPD_ASSERT;
 	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
@@ -115,10 +164,9 @@ static int ps8743_get_mux(const struct usb_mux *me, mux_state_t *mux_state)
 }
 
 /* Tune USB Tx/Rx Equalization */
-int ps8743_tune_usb_eq(int port, uint8_t tx, uint8_t rx)
+int ps8743_tune_usb_eq(const struct usb_mux *me, uint8_t tx, uint8_t rx)
 {
 	int ret;
-	const struct usb_mux *me = &usb_muxes[port];
 
 	ret = ps8743_write(me, PS8743_REG_USB_EQ_TX, tx);
 	ret |= ps8743_write(me, PS8743_REG_USB_EQ_RX, rx);
@@ -131,3 +179,74 @@ const struct usb_mux_driver ps8743_usb_mux_driver = {
 	.set = ps8743_set_mux,
 	.get = ps8743_get_mux,
 };
+
+static bool ps8743_port_is_usb_mode_only(const struct usb_mux *me)
+{
+	int val;
+
+	if (ps8743_read(me, PS8743_MISC_HPD_DP_USB_FLIP, &val))
+		return false;
+
+	val &= (PS8743_USB_MODE_STATUS | PS8743_DP_MODE_STATUS);
+
+	return val == PS8743_USB_MODE_STATUS;
+}
+
+static enum usb_conn_status ps8743_get_usb_conn_status(const struct usb_mux *me)
+{
+	int val;
+
+	if (ps8743_read(me, PS8743_MISC_DCI_SS_MODES, &val))
+		return UNKNOWN;
+
+	if (val == 0)
+		return NO_DEVICE;
+
+	val &= (PS8743_SSTX_NORMAL_OPERATION_MODE |
+		PS8743_SSTX_POWER_SAVING_MODE | PS8743_SSTX_SUSPEND_MODE);
+
+	return (val != PS8743_SSTX_NORMAL_OPERATION_MODE &&
+		val != PS8743_SSTX_POWER_SAVING_MODE) ?
+		       USB2_CONNECTED :
+		       USB3_CONNECTED;
+}
+
+static void ps8743_suspend(void)
+{
+	for (int i = 0; i < board_get_usb_pd_port_count(); i++) {
+		const struct usb_mux *mux = usb_muxes[i].mux;
+
+		if (mux->driver != &ps8743_usb_mux_driver)
+			continue;
+
+		saved_usb_conn_status[i] = ps8743_get_usb_conn_status(mux);
+
+		if (ps8743_port_is_usb_mode_only(mux) &&
+		    saved_usb_conn_status[i] == USB2_CONNECTED) {
+			ps8743_field_update(mux, PS8743_REG_MODE,
+					    PS8743_MODE_USB_ENABLE, 0);
+		}
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, ps8743_suspend, HOOK_PRIO_DEFAULT);
+
+static void ps8743_resume(void)
+{
+	for (int i = 0; i < board_get_usb_pd_port_count(); i++) {
+		const struct usb_mux *mux = usb_muxes[i].mux;
+
+		if (mux->driver != &ps8743_usb_mux_driver)
+			continue;
+
+		if (saved_usb_conn_status[i] != NO_DEVICE) {
+			ps8743_field_update(mux, PS8743_REG_MODE,
+					    PS8743_MODE_USB_ENABLE,
+					    PS8743_MODE_USB_ENABLE);
+		}
+	}
+}
+#ifdef CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK
+DECLARE_HOOK(HOOK_CHIPSET_RESUME_INIT, ps8743_resume, HOOK_PRIO_DEFAULT);
+#else
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, ps8743_resume, HOOK_PRIO_DEFAULT);
+#endif
diff --git a/driver/usb_mux/ps8743.h b/driver/usb_mux/ps8743.h
index bd8db20167..e34d4f93e4 100644
--- a/driver/usb_mux/ps8743.h
+++ b/driver/usb_mux/ps8743.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -9,74 +9,35 @@
 #define __CROS_EC_PS8743_H
 
 #include "usb_mux.h"
-
-#define PS8743_I2C_ADDR0_FLAG    0x10
-#define PS8743_I2C_ADDR1_FLAG    0x11
-#define PS8743_I2C_ADDR2_FLAG    0x19
-#define PS8743_I2C_ADDR3_FLAG    0x1a
-
-/* Mode register for setting mux */
-#define PS8743_REG_MODE 0x00
-#define PS8743_MODE_IN_HPD_ASSERT    BIT(0)
-#define PS8743_MODE_IN_HPD_CONTROL   BIT(1)
-#define PS8743_MODE_FLIP_ENABLE      BIT(2)
-#define PS8743_MODE_FLIP_REG_CONTROL BIT(3)
-#define PS8743_MODE_USB_ENABLE       BIT(4)
-#define PS8743_MODE_USB_REG_CONTROL  BIT(5)
-#define PS8743_MODE_DP_ENABLE        BIT(6)
-#define PS8743_MODE_DP_REG_CONTROL   BIT(7)
-/* To reset the state machine to default */
-#define PS8743_MODE_POWER_DOWN (PS8743_MODE_USB_REG_CONTROL |  \
-				PS8743_MODE_DP_REG_CONTROL)
+#include "usb_mux/ps8743_public.h"
 
 /* Status register for checking mux state */
 #define PS8743_REG_STATUS 0x09
 #define PS8743_STATUS_POLARITY_INVERTED BIT(2)
-#define PS8743_STATUS_USB_ENABLED       BIT(3)
-#define PS8743_STATUS_DP_ENABLED        BIT(4)
-#define PS8743_STATUS_HPD_ASSERTED      BIT(7)
+#define PS8743_STATUS_USB_ENABLED BIT(3)
+#define PS8743_STATUS_DP_ENABLED BIT(4)
+#define PS8743_STATUS_HPD_ASSERTED BIT(7)
 
 /* Chip ID / revision registers and expected fused values */
 #define PS8743_REG_REVISION_ID1 0xf0
 #define PS8743_REG_REVISION_ID2 0xf1
-#define PS8743_REG_CHIP_ID1     0xf2
-#define PS8743_REG_CHIP_ID2     0xf3
-#define PS8743_REVISION_ID1_0   0x00
-#define PS8743_REVISION_ID1_1   0x01
-#define PS8743_REVISION_ID2     0x0b
-#define PS8743_CHIP_ID1         0x41
-#define PS8743_CHIP_ID2         0x87
-
-/* USB equalization settings for Host to Mux */
-#define PS8743_REG_USB_EQ_TX     0x32
-#define PS8743_USB_EQ_TX_12_8_DB 0x00
-#define PS8743_USB_EQ_TX_17_DB   0x20
-#define PS8743_USB_EQ_TX_7_7_DB  0x40
-#define PS8743_USB_EQ_TX_3_6_DB  0x60
-#define PS8743_USB_EQ_TX_15_DB   0x80
-#define PS8743_USB_EQ_TX_10_9_DB 0xc0
-#define PS8743_USB_EQ_TX_4_5_DB  0xe0
-
-/* USB equalization settings for Connector to Mux */
-#define PS8743_REG_USB_EQ_RX     0x3b
-#define PS8743_USB_EQ_RX_2_4_DB  0x00
-#define PS8743_USB_EQ_RX_5_DB    0x10
-#define PS8743_USB_EQ_RX_6_5_DB  0x20
-#define PS8743_USB_EQ_RX_7_4_DB  0x30
-#define PS8743_USB_EQ_RX_8_7_DB  0x40
-#define PS8743_USB_EQ_RX_10_9_DB 0x50
-#define PS8743_USB_EQ_RX_12_8_DB 0x60
-#define PS8743_USB_EQ_RX_13_8_DB 0x70
-#define PS8743_USB_EQ_RX_14_8_DB 0x80
-#define PS8743_USB_EQ_RX_15_4_DB 0x90
-#define PS8743_USB_EQ_RX_16_0_DB 0xa0
-#define PS8743_USB_EQ_RX_16_7_DB 0xb0
-#define PS8743_USB_EQ_RX_18_8_DB 0xc0
-#define PS8743_USB_EQ_RX_21_3_DB 0xd0
-#define PS8743_USB_EQ_RX_22_2_DB 0xe0
-
-int ps8743_tune_usb_eq(int i2c_addr, uint8_t tx, uint8_t rx);
-int ps8743_write(const struct usb_mux *me, uint8_t reg, uint8_t val);
-int ps8743_read(const struct usb_mux *me, uint8_t reg, int *val);
+#define PS8743_REG_CHIP_ID1 0xf2
+#define PS8743_REG_CHIP_ID2 0xf3
+#define PS8743_REVISION_ID1_0 0x00
+#define PS8743_REVISION_ID1_1 0x01
+#define PS8743_REVISION_ID2 0x0b
+#define PS8743_CHIP_ID1 0x41
+#define PS8743_CHIP_ID2 0x87
+
+/* Misc register for checking DCI / SS pair mode status */
+#define PS8743_MISC_DCI_SS_MODES 0x42
+#define PS8743_SSTX_NORMAL_OPERATION_MODE BIT(4)
+#define PS8743_SSTX_POWER_SAVING_MODE BIT(5)
+#define PS8743_SSTX_SUSPEND_MODE BIT(6)
+
+/* Misc resiger for checking HPD / DP / USB / FLIP mode status */
+#define PS8743_MISC_HPD_DP_USB_FLIP 0x09
+#define PS8743_USB_MODE_STATUS BIT(3)
+#define PS8743_DP_MODE_STATUS BIT(4)
 
 #endif /* __CROS_EC_PS8743_H */
diff --git a/driver/usb_mux/ps8822.c b/driver/usb_mux/ps8822.c
new file mode 100644
index 0000000000..97d1158f99
--- /dev/null
+++ b/driver/usb_mux/ps8822.c
@@ -0,0 +1,132 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Parade PS8822
+ * USB Type-C Redriving Switch for USB Host / DisplayPort.
+ */
+
+#include "common.h"
+#include "i2c.h"
+#include "ps8822.h"
+#include "usb_mux.h"
+#include "util.h"
+
+static int ps8822_read(const struct usb_mux *me, int page, uint8_t reg,
+		       int *val)
+{
+	return i2c_read8(me->i2c_port, me->i2c_addr_flags + page, reg, val);
+}
+
+static int ps8822_write(const struct usb_mux *me, int page, uint8_t reg,
+			int val)
+{
+	return i2c_write8(me->i2c_port, me->i2c_addr_flags + page, reg, val);
+}
+
+int ps8822_set_dp_rx_eq(const struct usb_mux *me, int db)
+{
+	int dpeq_reg;
+	int rv;
+
+	/* Read DP EQ register */
+	rv = ps8822_read(me, PS8822_REG_PAGE1, PS8822_REG_DP_EQ, &dpeq_reg);
+	if (rv)
+		return rv;
+
+	if (db < PS8822_DPEQ_LEVEL_UP_9DB || db > PS8822_DPEQ_LEVEL_UP_21DB)
+		return EC_ERROR_INVAL;
+
+	/* Disable auto eq */
+	dpeq_reg &= ~PS8822_DP_EQ_AUTO_EN;
+
+	/* Set gain to the requested value */
+	dpeq_reg &= ~(PS8822_DPEQ_LEVEL_UP_MASK << PS8822_REG_DP_EQ_SHIFT);
+	dpeq_reg |= (db << PS8822_REG_DP_EQ_SHIFT);
+
+	/* Apply new EQ setting */
+	return ps8822_write(me, PS8822_REG_PAGE1, PS8822_REG_DP_EQ, dpeq_reg);
+}
+
+static int ps8822_init(const struct usb_mux *me)
+{
+	char id[PS8822_ID_LEN + 1];
+	int reg;
+	int i;
+	int rv = 0;
+
+	/* Read ID registers */
+	for (i = 0; i < PS8822_ID_LEN; i++) {
+		rv |= ps8822_read(me, PS8822_REG_PAGE0, PS8822_REG_DEV_ID1 + i,
+				  &reg);
+		if (!rv)
+			id[i] = reg;
+	}
+
+	if (!rv) {
+		id[PS8822_ID_LEN] = '\0';
+		/* Set mode register to default value */
+		rv = ps8822_write(me, PS8822_REG_PAGE0, PS8822_REG_MODE, 0);
+		rv |= strcasecmp("PS8822", id);
+	}
+
+	return rv;
+}
+
+/* Writes control register to set switch mode */
+static int ps8822_set_mux(const struct usb_mux *me, mux_state_t mux_state,
+			  bool *ack_required)
+{
+	int reg;
+	int rv;
+
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
+	/* This driver treats safe mode as none */
+	if (mux_state & USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
+
+	rv = ps8822_read(me, PS8822_REG_PAGE0, PS8822_REG_MODE, &reg);
+	if (rv)
+		return rv;
+
+	/* Assume standby, preserve PIN_E config bit */
+	reg &= ~(PS8822_MODE_ALT_DP_EN | PS8822_MODE_USB_EN | PS8822_MODE_FLIP);
+
+	if (mux_state & USB_PD_MUX_USB_ENABLED)
+		reg |= PS8822_MODE_USB_EN;
+	if (mux_state & USB_PD_MUX_DP_ENABLED)
+		reg |= PS8822_MODE_ALT_DP_EN;
+	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
+		reg |= PS8822_MODE_FLIP;
+
+	return ps8822_write(me, PS8822_REG_PAGE0, PS8822_REG_MODE, reg);
+}
+
+/* Reads control register and updates mux_state accordingly */
+static int ps8822_get_mux(const struct usb_mux *me, mux_state_t *mux_state)
+{
+	int reg;
+	int res;
+
+	res = ps8822_read(me, PS8822_REG_PAGE0, PS8822_REG_MODE, &reg);
+	if (res)
+		return res;
+
+	*mux_state = 0;
+	if (reg & PS8822_MODE_USB_EN)
+		*mux_state |= USB_PD_MUX_USB_ENABLED;
+	if (reg & PS8822_MODE_ALT_DP_EN)
+		*mux_state |= USB_PD_MUX_DP_ENABLED;
+	if (reg & PS8822_MODE_FLIP)
+		*mux_state |= USB_PD_MUX_POLARITY_INVERTED;
+
+	return EC_SUCCESS;
+}
+
+const struct usb_mux_driver ps8822_usb_mux_driver = {
+	.init = ps8822_init,
+	.set = ps8822_set_mux,
+	.get = ps8822_get_mux,
+};
diff --git a/driver/usb_mux/ps8822.h b/driver/usb_mux/ps8822.h
new file mode 100644
index 0000000000..4f7503b21b
--- /dev/null
+++ b/driver/usb_mux/ps8822.h
@@ -0,0 +1,66 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Parade PS8822
+ * USB Type-C Retiming Switch for USB Device / DisplayPort Sink
+ */
+
+#ifndef __CROS_EC_PS8822_H
+#define __CROS_EC_PS8822_H
+
+#include "usb_mux.h"
+
+#define PS8822_I2C_ADDR0_FLAG 0x10
+#define PS8822_I2C_ADDR1_FLAG 0x18
+#define PS8822_I2C_ADDR2_FLAG 0x58
+#define PS8822_I2C_ADDR3_FLAG 0x60
+
+#define PS8822_REG_PAGE0 0x00
+
+/* Mode register for setting mux */
+#define PS8822_REG_MODE 0x01
+#define PS8822_MODE_ALT_DP_EN BIT(7)
+#define PS8822_MODE_USB_EN BIT(6)
+#define PS8822_MODE_FLIP BIT(5)
+#define PS8822_MODE_PIN_E BIT(4)
+
+#define PS8822_REG_CONFIG 0x02
+#define PS8822_CONFIG_HPD_IN_DIS BIT(7)
+#define PS8822_CONFIG_DP_PLUG BIT(6)
+
+#define PS8822_REG_DEV_ID1 0x06
+#define PS8822_REG_DEV_ID2 0x07
+#define PS8822_REG_DEV_ID3 0x08
+#define PS8822_REG_DEV_ID4 0x09
+#define PS8822_REG_DEV_ID5 0x0A
+#define PS8822_REG_DEV_ID6 0x0B
+
+#define PS8822_ID_LEN 6
+
+#define PS8822_REG_PAGE1 0x01
+#define PS8822_REG_DP_EQ 0xB6
+#define PS8822_DP_EQ_AUTO_EN BIT(7)
+
+#define PS8822_DPEQ_LEVEL_UP_9DB 0x00
+#define PS8822_DPEQ_LEVEL_UP_11DB 0x01
+#define PS8822_DPEQ_LEVEL_UP_12DB 0x02
+#define PS8822_DPEQ_LEVEL_UP_14DB 0x03
+#define PS8822_DPEQ_LEVEL_UP_17DB 0x04
+#define PS8822_DPEQ_LEVEL_UP_18DB 0x05
+#define PS8822_DPEQ_LEVEL_UP_19DB 0x06
+#define PS8822_DPEQ_LEVEL_UP_20DB 0x07
+#define PS8822_DPEQ_LEVEL_UP_21DB 0x08
+#define PS8822_DPEQ_LEVEL_UP_MASK 0x0F
+#define PS8822_REG_DP_EQ_SHIFT 3
+
+/**
+ * Set DP Rx Equalization value
+ *
+ * @param *me pointer to usb_mux descriptor
+ * @param db requested gain setting for DP Rx path
+ * @return EC_SUCCESS if db param is valid and I2C is successful
+ */
+int ps8822_set_dp_rx_eq(const struct usb_mux *me, int db);
+
+#endif /* __CROS_EC_PS8822_H */
diff --git a/driver/usb_mux/tusb1064.c b/driver/usb_mux/tusb1064.c
new file mode 100644
index 0000000000..266e36a2eb
--- /dev/null
+++ b/driver/usb_mux/tusb1064.c
@@ -0,0 +1,189 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "i2c.h"
+#include "tusb1064.h"
+#include "usb_mux.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+#if defined(CONFIG_USB_MUX_TUSB1044) + defined(CONFIG_USB_MUX_TUSB1064) + \
+		defined(CONFIG_USB_MUX_TUSB546) !=                        \
+	1
+#error "Must choose exactly one of CONFIG_USB_MUX_TUSB{546,1044,1064}"
+#endif
+
+static int tusb1064_read(const struct usb_mux *me, uint8_t reg, uint8_t *val)
+{
+	int buffer = 0xee;
+	int res =
+		i2c_read8(me->i2c_port, me->i2c_addr_flags, (int)reg, &buffer);
+	*val = buffer;
+	return res;
+}
+
+static int tusb1064_write(const struct usb_mux *me, uint8_t reg, uint8_t val)
+{
+	return i2c_write8(me->i2c_port, me->i2c_addr_flags, (int)reg, (int)val);
+}
+
+#if defined(CONFIG_USB_MUX_TUSB1044)
+void tusb1044_hpd_update(const struct usb_mux *me, mux_state_t mux_state,
+			 bool *ack_required)
+{
+	int res;
+	uint8_t reg;
+
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
+	res = tusb1064_read(me, TUSB1064_REG_GENERAL, &reg);
+	if (res)
+		return;
+
+	/*
+	 *  Overrides HPDIN pin state.
+		Settings of this bit will enable the Display port lanes.
+		0h = HPD_IN based on HPD_IN pin.
+		1h = HPD_IN high.
+	 */
+	if (mux_state & USB_PD_MUX_HPD_LVL)
+		reg |= REG_GENERAL_HPDIN_OVERRIDE;
+	else
+		reg &= ~REG_GENERAL_HPDIN_OVERRIDE;
+
+	tusb1064_write(me, TUSB1064_REG_GENERAL, reg);
+}
+#endif
+
+int tusb1064_set_dp_rx_eq(const struct usb_mux *me, int db)
+{
+	uint8_t reg;
+	int rv;
+
+	if (db < TUSB1064_DP_EQ_RX_NEG_0_3_DB || db > TUSB1064_DP_EQ_RX_12_1_DB)
+		return EC_ERROR_INVAL;
+
+	/* Set the requested gain values */
+	reg = TUSB1064_DP1EQ(db) | TUSB1064_DP3EQ(db);
+	rv = tusb1064_write(me, TUSB1064_REG_DP1DP3EQ_SEL, reg);
+	if (rv)
+		return rv;
+
+	reg = TUSB1064_DP0EQ(db) | TUSB1064_DP2EQ(db);
+	rv = tusb1064_write(me, TUSB1064_REG_DP0DP2EQ_SEL, reg);
+	if (rv)
+		return rv;
+
+	/* Enable EQ_OVERRIDE so the gain registers are used */
+	rv = tusb1064_read(me, TUSB1064_REG_GENERAL, &reg);
+	if (rv)
+		return rv;
+
+	reg |= REG_GENERAL_EQ_OVERRIDE;
+
+	return tusb1064_write(me, TUSB1064_REG_GENERAL, reg);
+}
+
+/* Writes control register to set switch mode */
+int tusb1064_set_mux(const struct usb_mux *me, mux_state_t mux_state,
+		     bool *ack_required)
+{
+	uint8_t reg;
+	int rv;
+	int mask;
+
+	/* This driver treats safe mode as none */
+	if (mux_state & USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
+
+	rv = tusb1064_read(me, TUSB1064_REG_GENERAL, &reg);
+	if (rv)
+		return rv;
+
+	/* Mask bits that may be set in this function */
+	mask = REG_GENERAL_CTLSEL_USB3 | REG_GENERAL_CTLSEL_ANYDP |
+	       REG_GENERAL_FLIPSEL;
+#if defined(CONFIG_USB_MUX_TUSB1044) || defined(CONFIG_USB_MUX_TUSB546)
+	mask |= REG_GENERAL_HPDIN_OVERRIDE;
+#endif
+	reg &= ~mask;
+
+	/* This driver does not use host command ACKs */
+	*ack_required = false;
+
+	if (mux_state & USB_PD_MUX_USB_ENABLED)
+		reg |= REG_GENERAL_CTLSEL_USB3;
+	if (mux_state & USB_PD_MUX_DP_ENABLED) {
+		reg |= REG_GENERAL_CTLSEL_ANYDP;
+#ifdef CONFIG_USB_MUX_TUSB546
+		reg |= REG_GENERAL_HPDIN_OVERRIDE;
+#endif
+	}
+	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
+		reg |= REG_GENERAL_FLIPSEL;
+#if defined(CONFIG_USB_MUX_TUSB1044)
+	if (mux_state & USB_PD_MUX_HPD_LVL)
+		reg |= REG_GENERAL_HPDIN_OVERRIDE;
+#endif
+
+	return tusb1064_write(me, TUSB1064_REG_GENERAL, reg);
+}
+
+/* Reads control register and updates mux_state accordingly */
+static int tusb1064_get_mux(const struct usb_mux *me, mux_state_t *mux_state)
+{
+	uint8_t reg;
+	int res;
+
+	res = tusb1064_read(me, TUSB1064_REG_GENERAL, &reg);
+	if (res)
+		return EC_ERROR_INVAL;
+
+	*mux_state = 0;
+	if (reg & REG_GENERAL_CTLSEL_USB3)
+		*mux_state |= USB_PD_MUX_USB_ENABLED;
+	if (reg & REG_GENERAL_CTLSEL_ANYDP)
+		*mux_state |= USB_PD_MUX_DP_ENABLED;
+	if (reg & REG_GENERAL_FLIPSEL)
+		*mux_state |= USB_PD_MUX_POLARITY_INVERTED;
+#if defined(CONFIG_USB_MUX_TUSB1044)
+	if (reg & REG_GENERAL_HPDIN_OVERRIDE)
+		*mux_state |= USB_PD_MUX_HPD_LVL;
+#endif
+
+	return EC_SUCCESS;
+}
+
+/* Generic driver init function */
+static int tusb1064_init(const struct usb_mux *me)
+{
+	int res;
+	bool unused;
+
+	/*
+	 * Note that bypassing the usb_mux API is okay for internal driver calls
+	 * since the task calling init already holds this port's mux lock.
+	 */
+	/* Disconnect USB3.1 and DP */
+	res = tusb1064_set_mux(me, USB_PD_MUX_NONE, &unused);
+	if (res)
+		return res;
+
+	/* Disable AUX mux override */
+	res = tusb1064_write(me, TUSB1064_REG_AUXDPCTRL, 0);
+	if (res)
+		return res;
+
+	return EC_SUCCESS;
+}
+
+const struct usb_mux_driver tusb1064_usb_mux_driver = {
+	/* CAUTION: This is an UFP/RX/SINK redriver mux */
+	.init = tusb1064_init,
+	.set = tusb1064_set_mux,
+	.get = tusb1064_get_mux,
+};
diff --git a/driver/usb_mux/tusb1064.h b/driver/usb_mux/tusb1064.h
new file mode 100644
index 0000000000..8e8518c197
--- /dev/null
+++ b/driver/usb_mux/tusb1064.h
@@ -0,0 +1,155 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_TUSB1064_H
+#define __CROS_EC_TUSB1064_H
+
+#include "usb_mux.h"
+
+#include <stdint.h>
+
+/*
+ * TUSB1064 Has 16 possible device addresses which are selected by A1|A0 lines
+ * using 4 level inputs.
+ *    0 -> tied directly to GND
+ *    R -> tied to GND via a 20k pulldown
+ *    F -> floating
+ *    1 -> tied to VCC
+ */
+#define TUSB1064_I2C_ADDR0_FLAGS 0x44
+#define TUSB1064_I2C_ADDR1_FLAGS 0x45
+#define TUSB1064_I2C_ADDR2_FLAGS 0x46
+#define TUSB1064_I2C_ADDR3_FLAGS 0x47
+#define TUSB1064_I2C_ADDR4_FLAGS 0x20
+#define TUSB1064_I2C_ADDR5_FLAGS 0x21
+#define TUSB1064_I2C_ADDR6_FLAGS 0x22
+#define TUSB1064_I2C_ADDR7_FLAGS 0x23
+#define TUSB1064_I2C_ADDR8_FLAGS 0x10
+#define TUSB1064_I2C_ADDR9_FLAGS 0x11
+#define TUSB1064_I2C_ADDR10_FLAGS 0x12
+#define TUSB1064_I2C_ADDR11_FLAGS 0x13
+#define TUSB1064_I2C_ADDR12_FLAGS 0x0C
+#define TUSB1064_I2C_ADDR13_FLAGS 0x0D
+#define TUSB1064_I2C_ADDR14_FLAGS 0x0E
+#define TUSB1064_I2C_ADDR15_FLAGS 0x0F
+
+/* TUSB1064 General Register */
+#define TUSB1064_REG_GENERAL 0x0a
+#define REG_GENERAL_CTLSEL_USB3 BIT(0)
+#define REG_GENERAL_CTLSEL_ANYDP BIT(1)
+#define REG_GENERAL_FLIPSEL BIT(2)
+#if defined(CONFIG_USB_MUX_TUSB1044) || defined(CONFIG_USB_MUX_TUSB546)
+#define REG_GENERAL_HPDIN_OVERRIDE BIT(3)
+#else
+#define REG_GENERAL_DP_EN_CTRL BIT(3)
+#endif
+#define REG_GENERAL_EQ_OVERRIDE BIT(4)
+
+/* AUX and DP Lane Control Register */
+#define TUSB1064_REG_AUXDPCTRL 0x13
+#define TUSB1064_AUXDPCTRL_AUX_SNOOP_DISABLE BIT(7)
+#define TUSB1064_AUXDPCTRL_AUX_SBU_OVR 0x30
+#define TUSB1064_AUXDPCTRL_DP3_DISABLE BIT(3)
+#define TUSB1064_AUXDPCTRL_DP2_DISABLE BIT(2)
+#define TUSB1064_AUXDPCTRL_DP1_DISABLE BIT(1)
+#define TUSB1064_AUXDPCTRL_DP0_DISABLE BIT(0)
+
+/* Receiver Equalization GPIO Control */
+#define TUSB1064_REG_DP1DP3EQ_SEL 0x10
+#define TUSB1064_REG_DP0DP2EQ_SEL 0x11
+
+/* DP Receiver equalization settings */
+#define TUSB1064_DP_EQ_RX_NEG_0_3_DB 0x0
+#define TUSB1064_DP_EQ_RX_1_6_DB 0x1
+#define TUSB1064_DP_EQ_RX_3_0_DB 0x2
+#define TUSB1064_DP_EQ_RX_4_4_DB 0x3
+#define TUSB1064_DP_EQ_RX_5_4_DB 0x4
+#define TUSB1064_DP_EQ_RX_6_5_DB 0x5
+#define TUSB1064_DP_EQ_RX_7_3_DB 0x6
+#define TUSB1064_DP_EQ_RX_8_1_DB 0x7
+#define TUSB1064_DP_EQ_RX_8_9_DB 0x8
+#define TUSB1064_DP_EQ_RX_9_5_DB 0x9
+#define TUSB1064_DP_EQ_RX_10_0_DB 0xA
+#define TUSB1064_DP_EQ_RX_10_6_DB 0xB
+#define TUSB1064_DP_EQ_RX_11_0_DB 0xC
+#define TUSB1064_DP_EQ_RX_11_4_DB 0xD
+#define TUSB1064_DP_EQ_RX_11_8_DB 0xE
+#define TUSB1064_DP_EQ_RX_12_1_DB 0xF
+
+#ifndef TUSB1064_DP1EQ
+#define TUSB1064_DP1EQ(nr) ((nr) << 4)
+#endif
+#ifndef TUSB1064_DP3EQ
+#define TUSB1064_DP3EQ(nr) ((nr) << 0)
+#endif
+#ifndef TUSB1064_DP0EQ
+#define TUSB1064_DP0EQ(nr) ((nr) << 4)
+#endif
+#ifndef TUSB1064_DP2EQ
+#define TUSB1064_DP2EQ(nr) ((nr) << 0)
+#endif
+
+/* TUSB1064 Receiver Equalization GPIO Control */
+#define TUSB1064_REG_SSRX2RX1EQ_SEL 0x20
+#define TUSB1064_REG_SSTXEQ_SEL 0x21
+
+/* USB equalization settings for Mux DFP (TX) */
+#define TUSB1064_USB_EQ_DFP_NEG_3_0_DB 0x0
+#define TUSB1064_USB_EQ_DFP_NEG_0_8_DB 0x1
+#define TUSB1064_USB_EQ_DFP_NEG_0_7_DB 0x2
+#define TUSB1064_USB_EQ_DFP_2_2_DB 0x3
+#define TUSB1064_USB_EQ_DFP_3_3_DB 0x4
+#define TUSB1064_USB_EQ_DFP_4_3_DB 0x5
+#define TUSB1064_USB_EQ_DFP_5_1_DB 0x6
+#define TUSB1064_USB_EQ_DFP_6_0_DB 0x7
+#define TUSB1064_USB_EQ_DFP_6_7_DB 0x8
+#define TUSB1064_USB_EQ_DFP_7_3_DB 0x9
+#define TUSB1064_USB_EQ_DFP_7_8_DB 0xA
+#define TUSB1064_USB_EQ_DFP_8_3_DB 0xB
+#define TUSB1064_USB_EQ_DFP_8_6_DB 0xC
+#define TUSB1064_USB_EQ_DFP_9_0_DB 0xD
+#define TUSB1064_USB_EQ_DFP_9_3_DB 0xE
+#define TUSB1064_USB_EQ_DFP_9_7_DB 0xF
+
+/* USB equalization settings for Mux UFP (RX) */
+#define TUSB1064_USB_EQ_UFP_NEG_1_5_DB 0x0
+#define TUSB1064_USB_EQ_UFP_0_7_DB 0x1
+#define TUSB1064_USB_EQ_UFP_2_2_DB 0x2
+#define TUSB1064_USB_EQ_UFP_3_7_DB 0x3
+#define TUSB1064_USB_EQ_UFP_4_7_DB 0x4
+#define TUSB1064_USB_EQ_UFP_5_8_DB 0x5
+#define TUSB1064_USB_EQ_UFP_6_6_DB 0x6
+#define TUSB1064_USB_EQ_UFP_7_4_DB 0x7
+#define TUSB1064_USB_EQ_UFP_8_1_DB 0x8
+#define TUSB1064_USB_EQ_UFP_8_7_DB 0x9
+#define TUSB1064_USB_EQ_UFP_9_2_DB 0xA
+#define TUSB1064_USB_EQ_UFP_9_7_DB 0xB
+#define TUSB1064_USB_EQ_UFP_10_0_DB 0xC
+#define TUSB1064_USB_EQ_UFP_10_4_DB 0xD
+#define TUSB1064_USB_EQ_UFP_10_7_DB 0xE
+#define TUSB1064_USB_EQ_UFP_11_1_DB 0xF
+
+#if defined(CONFIG_USB_MUX_TUSB1044)
+/*
+ * This api is used to override the HPD infomartion received on HPD_IN pin
+ * or when no HPD physical pin is connected.
+ * Writes HPD infomration to the General_1 Registor.
+ */
+void tusb1044_hpd_update(const struct usb_mux *me, mux_state_t mux_state,
+			 bool *ack_required);
+#endif
+
+/**
+ * Set DP Rx Equalization value
+ *
+ * @param *me pointer to usb_mux descriptor
+ * @param db requested gain setting for DP Rx path
+ * @return EC_SUCCESS if db param is valid and I2C is successful
+ */
+int tusb1064_set_dp_rx_eq(const struct usb_mux *me, int db);
+
+int tusb1064_set_mux(const struct usb_mux *me, mux_state_t mux_state,
+		     bool *ack_required);
+#endif /* __CROS_EC_TUSB1064_H */
diff --git a/driver/usb_mux/usb_mux.c b/driver/usb_mux/usb_mux.c
index c4af3b2ed9..ceabe7f8c8 100644
--- a/driver/usb_mux/usb_mux.c
+++ b/driver/usb_mux/usb_mux.c
@@ -1,21 +1,28 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* USB mux high-level driver. */
 
+#include "atomic.h"
+#include "builtin/assert.h"
+#include "chipset.h"
 #include "common.h"
 #include "console.h"
+#include "ec_commands.h"
 #include "hooks.h"
 #include "host_command.h"
+#include "queue.h"
+#include "task.h"
+#include "timer.h"
 #include "usb_mux.h"
 #include "usbc_ppc.h"
 #include "util.h"
 
 #ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 #else
 #define CPRINTS(format, args...)
 #define CPRINTF(format, args...)
@@ -27,28 +34,233 @@ static int enable_debug_prints;
  * Flags will reset to 0 after sysjump; This works for current flags as LPM will
  * get reset in the init method which is called during PD task startup.
  */
-static uint8_t flags[CONFIG_USB_PD_PORT_MAX_COUNT];
+static atomic_t flags[CONFIG_USB_PD_PORT_MAX_COUNT];
 
-#define USB_MUX_FLAG_IN_LPM BIT(0) /* Device is in low power mode. */
+/* Device is in low power mode. */
+#define USB_MUX_FLAG_IN_LPM BIT(0)
+
+/* Device initialized at least once */
+#define USB_MUX_FLAG_INIT BIT(1)
+
+/* Coordinate mux accesses by-port among the tasks */
+static mutex_t mux_lock[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+/* Coordinate which task requires an ACK event */
+static task_id_t ack_task[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	[0 ... CONFIG_USB_PD_PORT_MAX_COUNT - 1] = TASK_ID_INVALID
+};
+
+static void perform_mux_set(int port, int index, mux_state_t mux_mode,
+			    enum usb_switch usb_mode, int polarity);
+static void perform_mux_hpd_update(int port, int index, mux_state_t hpd_state);
 
 enum mux_config_type {
 	USB_MUX_INIT,
 	USB_MUX_LOW_POWER,
 	USB_MUX_SET_MODE,
 	USB_MUX_GET_MODE,
+	USB_MUX_CHIPSET_IDLE,
+	USB_MUX_CHIPSET_ACTIVE,
 	USB_MUX_CHIPSET_RESET,
+	USB_MUX_HPD_UPDATE,
 };
 
+/* Define a USB mux task ID for the purpose of linking */
+#ifndef HAS_TASK_USB_MUX
+#define TASK_ID_USB_MUX TASK_ID_INVALID
+#endif
+
+/*
+ * USB mux task
+ *
+ * Since USB mux sets can take extended periods of time (on the order of 100s of
+ * ms for some muxes), run a small task to complete those mux sets in order to
+ * not block the PD task.  Run HPD sets from this task as well, since they
+ * should be sequenced behind setting up the mux pins for DP.
+ *
+ * Depth must be a power of 2, which is normally enforced by the queue init
+ * code, but must be manually enforced here.
+ */
+#define MUX_QUEUE_DEPTH 4
+BUILD_ASSERT(POWER_OF_TWO(MUX_QUEUE_DEPTH));
+
+/* Define in order to enable debug info about how long the queue takes */
+#undef DEBUG_MUX_QUEUE_TIME
+
+struct mux_queue_entry {
+	enum mux_config_type type;
+	int index; /* Index to set, or TYPEC_USB_MUX_SET_ALL_CHIPS */
+	mux_state_t mux_mode; /* For both HPD and mux set */
+	enum usb_switch usb_config; /* Set only */
+	int polarity; /* Set only */
+#ifdef DEBUG_MUX_QUEUE_TIME
+	timestamp_t enqueued_time;
+#endif
+};
+
+/*
+ * Note: test builds won't optimize out the mux task code and thereby require
+ * the queue to link
+ */
+#if defined(TEST_BUILD) || defined(HAS_TASK_USB_MUX)
+/*
+ * Note: QUEUE macros cannot be used to initialize this array, since they rely
+ * on anonymous data structs for allocation which results in all entries
+ * sharing the same state pointer and data buffers.
+ */
+static struct queue mux_queue[CONFIG_USB_PD_PORT_MAX_COUNT];
+__maybe_unused static struct queue_state
+	queue_states[CONFIG_USB_PD_PORT_MAX_COUNT];
+__maybe_unused static struct mux_queue_entry
+	queue_buffers[CONFIG_USB_PD_PORT_MAX_COUNT][MUX_QUEUE_DEPTH];
+static mutex_t queue_lock[CONFIG_USB_PD_PORT_MAX_COUNT];
+#else
+extern struct queue const mux_queue[];
+extern mutex_t queue_lock[];
+#endif
+
+#ifdef CONFIG_ZEPHYR
+static int init_mux_mutex(void)
+{
+	int port;
+
+	for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++) {
+		k_mutex_init(&mux_lock[port]);
+
+		if (IS_ENABLED(HAS_TASK_USB_MUX))
+			k_mutex_init(&queue_lock[port]);
+	}
+
+	return 0;
+}
+SYS_INIT(init_mux_mutex, POST_KERNEL, 50);
+#endif /* CONFIG_ZEPHYR */
+
+__maybe_unused static void
+mux_task_enqueue(int port, int index, enum mux_config_type type,
+		 mux_state_t mux_mode, enum usb_switch usb_config, int polarity)
+{
+	struct mux_queue_entry new_entry;
+
+	if (!IS_ENABLED(HAS_TASK_USB_MUX))
+		return;
+
+	new_entry.type = type;
+	new_entry.index = index;
+	new_entry.mux_mode = mux_mode;
+	new_entry.usb_config = usb_config;
+	new_entry.polarity = polarity;
+#ifdef DEBUG_MUX_QUEUE_TIME
+	new_entry.enqueued_time = get_time();
+#endif
+
+	mutex_lock(&queue_lock[port]);
+
+	if (queue_add_unit(&mux_queue[port], &new_entry) == 0)
+		CPRINTS("Error: Dropping port %d mux %d", port, type);
+	else
+		task_wake(TASK_ID_USB_MUX);
+
+	mutex_unlock(&queue_lock[port]);
+}
+
+#ifdef HAS_TASK_USB_MUX
+static void init_queue_structs(void)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		mux_queue[i].state = &queue_states[i];
+		mux_queue[i].policy = &queue_policy_null;
+		mux_queue[i].buffer_units = MUX_QUEUE_DEPTH;
+		mux_queue[i].buffer_units_mask = MUX_QUEUE_DEPTH - 1;
+		mux_queue[i].unit_bytes = sizeof(struct mux_queue_entry);
+		mux_queue[i].buffer = (uint8_t *)&queue_buffers[i][0];
+	}
+}
+DECLARE_HOOK(HOOK_INIT, init_queue_structs, HOOK_PRIO_FIRST);
+#endif
+
+__maybe_unused void usb_mux_task(void *u)
+{
+	bool items_waiting = true;
+
+	while (1) {
+		int port;
+
+		/* Wait if we had no queue items to service */
+		if (!items_waiting)
+			task_wait_event(-1);
+
+		items_waiting = false;
+
+		/*
+		 * Round robin the ports, so no one port can monopolize the task
+		 */
+		for (port = 0; port < board_get_usb_pd_port_count(); port++) {
+			if (queue_count(&mux_queue[port])) {
+				/*
+				 * Process our first item.  Leave it in the
+				 * queue until we've completed its operation so
+				 * the PD task can tell it is still pending.
+				 * Note this should be safe to do unlocked, as
+				 * this task is the only one which changes the
+				 * queue head.
+				 */
+				struct mux_queue_entry next;
+
+				queue_peek_units(&mux_queue[port], &next, 0, 1);
+
+#ifdef DEBUG_MUX_QUEUE_TIME
+				CPRINTS("C%d: Start mux set queued %d us ago",
+					port, time_since32(next.enqueued_time));
+#endif
+				if (next.type == USB_MUX_SET_MODE)
+					perform_mux_set(port, next.index,
+							next.mux_mode,
+							next.usb_config,
+							next.polarity);
+				else if (next.type == USB_MUX_HPD_UPDATE)
+					perform_mux_hpd_update(port, next.index,
+							       next.mux_mode);
+				else
+					CPRINTS("Error: Unknown mux task type:"
+						"%d",
+						next.type);
+
+#ifdef DEBUG_MUX_QUEUE_TIME
+				CPRINTS("C%d: Completed mux set queued %d "
+					"us ago",
+					port, time_since32(next.enqueued_time));
+#endif
+				/*
+				 * Lock since the tail is changing, which would
+				 * disrupt any calls iterating the queue.
+				 */
+				mutex_lock(&queue_lock[port]);
+				queue_advance_head(&mux_queue[port], 1);
+				mutex_unlock(&queue_lock[port]);
+
+				/*
+				 * Force the task to run again if this queue has
+				 * more items to process.
+				 */
+				if (queue_count(&mux_queue[port]))
+					items_waiting = true;
+			}
+		}
+	}
+}
+
 /* Configure the MUX */
-static int configure_mux(int port,
-			 enum mux_config_type config,
+static int configure_mux(int port, int index, enum mux_config_type config,
 			 mux_state_t *mux_state)
 {
 	int rv = EC_SUCCESS;
-	const struct usb_mux *mux_ptr;
+	const struct usb_mux_chain *mux_chain;
+	int chip = 0;
 
-	if (config == USB_MUX_SET_MODE ||
-	    config == USB_MUX_GET_MODE) {
+	if (config == USB_MUX_SET_MODE || config == USB_MUX_GET_MODE) {
 		if (mux_state == NULL)
 			return EC_ERROR_INVAL;
 
@@ -61,11 +273,19 @@ static int configure_mux(int port,
 	 * MUXes.  So when we change one, we traverse the whole list
 	 * to make sure they are all updated appropriately.
 	 */
-	for (mux_ptr = &usb_muxes[port];
-	     rv == EC_SUCCESS && mux_ptr != NULL;
-	     mux_ptr = mux_ptr->next_mux) {
+	for (mux_chain = &usb_muxes[port];
+	     rv == EC_SUCCESS && mux_chain != NULL && mux_chain->mux != NULL;
+	     mux_chain = mux_chain->next, chip++) {
 		mux_state_t lcl_state;
+		const struct usb_mux *mux_ptr = mux_chain->mux;
 		const struct usb_mux_driver *drv = mux_ptr->driver;
+		bool ack_required = false;
+
+		if (index != TYPEC_USB_MUX_SET_ALL_CHIPS && index != chip)
+			continue;
+
+		/* Action time!  Lock this mux */
+		mutex_lock(&mux_lock[port]);
 
 		switch (config) {
 		case USB_MUX_INIT:
@@ -87,6 +307,20 @@ static int configure_mux(int port,
 
 			break;
 
+		case USB_MUX_CHIPSET_IDLE:
+			if ((mux_ptr->flags & USB_MUX_FLAG_CAN_IDLE) && drv &&
+			    drv->set_idle_mode)
+				rv = drv->set_idle_mode(mux_ptr, true);
+
+			break;
+
+		case USB_MUX_CHIPSET_ACTIVE:
+			if ((mux_ptr->flags & USB_MUX_FLAG_CAN_IDLE) && drv &&
+			    drv->set_idle_mode)
+				rv = drv->set_idle_mode(mux_ptr, false);
+
+			break;
+
 		case USB_MUX_CHIPSET_RESET:
 			if (drv && drv->chipset_reset)
 				rv = drv->chipset_reset(mux_ptr);
@@ -99,8 +333,13 @@ static int configure_mux(int port,
 			if (mux_ptr->flags & USB_MUX_FLAG_SET_WITHOUT_FLIP)
 				lcl_state &= ~USB_PD_MUX_POLARITY_INVERTED;
 
+			if ((lcl_state != USB_PD_MUX_NONE) &&
+			    (mux_ptr->flags & USB_MUX_FLAG_POLARITY_INVERTED))
+				lcl_state ^= USB_PD_MUX_POLARITY_INVERTED;
+
 			if (drv && drv->set) {
-				rv = drv->set(mux_ptr, lcl_state);
+				rv = drv->set(mux_ptr, lcl_state,
+					      &ack_required);
 				if (rv)
 					break;
 			}
@@ -109,6 +348,18 @@ static int configure_mux(int port,
 			if (mux_ptr->board_set)
 				rv = mux_ptr->board_set(mux_ptr, lcl_state);
 
+			/* Inform the AP its selected mux is set */
+			if (IS_ENABLED(CONFIG_USB_MUX_AP_CONTROL)) {
+				if (chip == 0)
+					pd_notify_event(
+						port,
+						PD_STATUS_EVENT_MUX_0_SET_DONE);
+				else if (chip == 1)
+					pd_notify_event(
+						port,
+						PD_STATUS_EVENT_MUX_1_SET_DONE);
+			}
+
 			break;
 
 		case USB_MUX_GET_MODE:
@@ -125,12 +376,53 @@ static int configure_mux(int port,
 				*mux_state |= lcl_state;
 			}
 			break;
+
+		case USB_MUX_HPD_UPDATE:
+			if (mux_ptr->hpd_update)
+				mux_ptr->hpd_update(mux_ptr, *mux_state,
+						    &ack_required);
+		}
+
+		/* Unlock before any host command waits */
+		mutex_unlock(&mux_lock[port]);
+
+		if (ack_required) {
+			ack_task[port] = task_get_current();
+
+			/*
+			 * This should only be called from the PD task or usb
+			 * mux task
+			 */
+			if (IS_ENABLED(HAS_TASK_USB_MUX)) {
+				assert(task_get_current() == TASK_ID_USB_MUX);
+			} else {
+#if defined(CONFIG_ZEPHYR) && defined(TEST_BUILD)
+				assert(port == TASK_ID_TO_PD_PORT(
+						       task_get_current()) ||
+				       task_get_current() ==
+					       TASK_ID_TEST_RUNNER);
+#else
+				assert(port ==
+				       TASK_ID_TO_PD_PORT(task_get_current()));
+#endif /* defined(CONFIG_ZEPHYR) && defined(TEST_BUILD) */
+			}
+
+			/*
+			 * Note: This task event could be generalized for more
+			 * purposes beyond host command ACKs.  For now, these
+			 * wait times are tuned for the purposes of the TCSS
+			 * mux, but could be made configurable for other
+			 * purposes.
+			 */
+			task_wait_event_mask(PD_EVENT_AP_MUX_DONE, 100 * MSEC);
+			ack_task[port] = TASK_ID_INVALID;
+
+			usleep(12.5 * MSEC);
 		}
 	}
 
 	if (rv)
-		CPRINTS("mux config:%d, port:%d, rv:%d",
-			config, port, rv);
+		CPRINTS("mux config:%d, port:%d, rv:%d", config, port, rv);
 
 	return rv;
 }
@@ -142,17 +434,30 @@ static void enter_low_power_mode(int port)
 	 * want know know that we tried to put the device in low power mode
 	 * so we can re-initialize the device on the next access.
 	 */
-	flags[port] |= USB_MUX_FLAG_IN_LPM;
+	atomic_or(&flags[port], USB_MUX_FLAG_IN_LPM);
 
 	/* Apply any low power customization if present */
-	configure_mux(port, USB_MUX_LOW_POWER, NULL);
+	configure_mux(port, TYPEC_USB_MUX_SET_ALL_CHIPS, USB_MUX_LOW_POWER,
+		      NULL);
 }
 
-static inline void exit_low_power_mode(int port)
+static int exit_low_power_mode(int port)
 {
 	/* If we are in low power, initialize device (which clears LPM flag) */
 	if (flags[port] & USB_MUX_FLAG_IN_LPM)
 		usb_mux_init(port);
+
+	if (!(flags[port] & USB_MUX_FLAG_INIT)) {
+		CPRINTS("C%d: USB_MUX_FLAG_INIT not set", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	if (flags[port] & USB_MUX_FLAG_IN_LPM) {
+		CPRINTS("C%d: USB_MUX_FLAG_IN_LPM not cleared", port);
+		return EC_ERROR_NOT_POWERED;
+	}
+
+	return EC_SUCCESS;
 }
 
 void usb_mux_init(int port)
@@ -165,33 +470,33 @@ void usb_mux_init(int port)
 		return;
 	}
 
-	rv = configure_mux(port, USB_MUX_INIT, NULL);
+	rv = configure_mux(port, TYPEC_USB_MUX_SET_ALL_CHIPS, USB_MUX_INIT,
+			   NULL);
+
+	if (rv == EC_SUCCESS)
+		atomic_or(&flags[port], USB_MUX_FLAG_INIT);
 
 	/*
 	 * Mux may fail initialization if it's not powered. Mark this port
 	 * as in LPM mode to try initialization again.
 	 */
 	if (rv == EC_ERROR_NOT_POWERED)
-		flags[port] |= USB_MUX_FLAG_IN_LPM;
+		atomic_or(&flags[port], USB_MUX_FLAG_IN_LPM);
 	else
-		flags[port] &= ~USB_MUX_FLAG_IN_LPM;
+		atomic_clear_bits(&flags[port], USB_MUX_FLAG_IN_LPM);
 }
 
-/*
- * TODO(crbug.com/505480): Setting muxes often involves I2C transcations,
- * which can block. Consider implementing an asynchronous task.
- */
-void usb_mux_set(int port, mux_state_t mux_mode,
-		 enum usb_switch usb_mode, int polarity)
+static void perform_mux_set(int port, int index, mux_state_t mux_mode,
+			    enum usb_switch usb_mode, int polarity)
 {
 	mux_state_t mux_state;
 	const int should_enter_low_power_mode =
 		(mux_mode == USB_PD_MUX_NONE &&
-		usb_mode == USB_SWITCH_DISCONNECT);
+		 usb_mode == USB_SWITCH_DISCONNECT);
 
-	if (port >= board_get_usb_pd_port_count()) {
-		return;
-	}
+	/* Perform initialization if not initialized yet */
+	if (!(flags[port] & USB_MUX_FLAG_INIT))
+		usb_mux_init(port);
 
 	/* Configure USB2.0 */
 	if (IS_ENABLED(CONFIG_USB_CHARGER))
@@ -205,20 +510,20 @@ void usb_mux_set(int port, mux_state_t mux_mode,
 	if (should_enter_low_power_mode && (flags[port] & USB_MUX_FLAG_IN_LPM))
 		return;
 
-	exit_low_power_mode(port);
+	if (exit_low_power_mode(port) != EC_SUCCESS)
+		return;
 
 	/* Configure superspeed lanes */
-	mux_state = ((mux_mode != USB_PD_MUX_NONE) && polarity)
-			? mux_mode | USB_PD_MUX_POLARITY_INVERTED
-			: mux_mode;
+	mux_state = ((mux_mode != USB_PD_MUX_NONE) && polarity) ?
+			    mux_mode | USB_PD_MUX_POLARITY_INVERTED :
+			    mux_mode;
 
-	if (configure_mux(port, USB_MUX_SET_MODE, &mux_state))
+	if (configure_mux(port, index, USB_MUX_SET_MODE, &mux_state))
 		return;
 
 	if (enable_debug_prints)
-		CPRINTS(
-		     "usb/dp mux: port(%d) typec_mux(%d) usb2(%d) polarity(%d)",
-		     port, mux_mode, usb_mode, polarity);
+		CPRINTS("usb/dp mux: port(%d) typec_mux(%d) usb2(%d) polarity(%d)",
+			port, mux_mode, usb_mode, polarity);
 
 	/*
 	 * If we are completely disconnecting the mux, then we should put it in
@@ -228,29 +533,88 @@ void usb_mux_set(int port, mux_state_t mux_mode,
 		enter_low_power_mode(port);
 }
 
-mux_state_t usb_mux_get(int port)
+void usb_mux_set(int port, mux_state_t mux_mode, enum usb_switch usb_mode,
+		 int polarity)
 {
-	mux_state_t mux_state;
-	bool is_low_power_mode;
-	int rv;
+	if (port >= board_get_usb_pd_port_count())
+		return;
 
-	if (port >= board_get_usb_pd_port_count()) {
-		return USB_PD_MUX_NONE;
+	/* Block if we have no mux task, but otherwise queue it up and return */
+	if (IS_ENABLED(HAS_TASK_USB_MUX))
+		mux_task_enqueue(port, TYPEC_USB_MUX_SET_ALL_CHIPS,
+				 USB_MUX_SET_MODE, mux_mode, usb_mode,
+				 polarity);
+	else
+		perform_mux_set(port, TYPEC_USB_MUX_SET_ALL_CHIPS, mux_mode,
+				usb_mode, polarity);
+}
+
+void usb_mux_set_single(int port, int index, mux_state_t mux_mode,
+			enum usb_switch usb_mode, int polarity)
+{
+	if (port >= board_get_usb_pd_port_count())
+		return;
+
+	/* Block if we have no mux task, but otherwise queue it up and return */
+	if (IS_ENABLED(HAS_TASK_USB_MUX))
+		mux_task_enqueue(port, index, USB_MUX_SET_MODE, mux_mode,
+				 usb_mode, polarity);
+	else
+		perform_mux_set(port, index, mux_mode, usb_mode, polarity);
+}
+
+bool usb_mux_set_completed(int port)
+{
+	bool sets_pending = false;
+	struct queue_iterator it;
+
+	/* No mux task, no items waiting to process */
+	if (!IS_ENABLED(HAS_TASK_USB_MUX))
+		return true;
+
+	/* Lock the queue so we can scroll through the items left to do */
+	mutex_lock(&queue_lock[port]);
+
+	for (queue_begin(&mux_queue[port], &it); it.ptr != NULL;
+	     queue_next(&mux_queue[port], &it)) {
+		const struct mux_queue_entry *check =
+			(struct mux_queue_entry *)it.ptr;
+
+		if (check->type == USB_MUX_SET_MODE) {
+			sets_pending = true;
+			break;
+		}
 	}
 
-	/* Store the status of LPM flag (low power mode) */
-	is_low_power_mode = flags[port] & USB_MUX_FLAG_IN_LPM;
+	mutex_unlock(&queue_lock[port]);
 
-	exit_low_power_mode(port);
+	return !sets_pending;
+}
 
-	rv = configure_mux(port, USB_MUX_GET_MODE, &mux_state);
+static enum ec_error_list try_usb_mux_get(int port, mux_state_t *mux_state)
+{
+	if (port >= board_get_usb_pd_port_count())
+		return EC_ERROR_INVAL;
 
-	/*
-	 * If the LPM flag was set prior to reading the mux state, re-enter the
-	 * low power mode.
-	 */
-	if (is_low_power_mode)
-		enter_low_power_mode(port);
+	/* Perform initialization if not initialized yet */
+	if (!(flags[port] & USB_MUX_FLAG_INIT))
+		usb_mux_init(port);
+
+	if (flags[port] & USB_MUX_FLAG_IN_LPM) {
+		*mux_state = USB_PD_MUX_NONE;
+		return EC_SUCCESS;
+	}
+
+	return configure_mux(port, TYPEC_USB_MUX_SET_ALL_CHIPS,
+			     USB_MUX_GET_MODE, mux_state);
+}
+
+mux_state_t usb_mux_get(int port)
+{
+	mux_state_t mux_state;
+	enum ec_status rv;
+
+	rv = try_usb_mux_get(port, &mux_state);
 
 	return rv ? USB_PD_MUX_NONE : mux_state;
 }
@@ -263,9 +627,15 @@ void usb_mux_flip(int port)
 		return;
 	}
 
-	exit_low_power_mode(port);
+	/* Perform initialization if not initialized yet */
+	if (!(flags[port] & USB_MUX_FLAG_INIT))
+		usb_mux_init(port);
+
+	if (exit_low_power_mode(port) != EC_SUCCESS)
+		return;
 
-	if (configure_mux(port, USB_MUX_GET_MODE, &mux_state))
+	if (configure_mux(port, TYPEC_USB_MUX_SET_ALL_CHIPS, USB_MUX_GET_MODE,
+			  &mux_state))
 		return;
 
 	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
@@ -273,27 +643,55 @@ void usb_mux_flip(int port)
 	else
 		mux_state |= USB_PD_MUX_POLARITY_INVERTED;
 
-	configure_mux(port, USB_MUX_SET_MODE, &mux_state);
+	configure_mux(port, TYPEC_USB_MUX_SET_ALL_CHIPS, USB_MUX_SET_MODE,
+		      &mux_state);
 }
 
-void usb_mux_hpd_update(int port, int hpd_lvl, int hpd_irq)
+static void perform_mux_hpd_update(int port, int index, mux_state_t hpd_state)
 {
-	mux_state_t mux_state;
-	const struct usb_mux *mux_ptr = &usb_muxes[port];
+	/* Perform initialization if not initialized yet */
+	if (!(flags[port] & USB_MUX_FLAG_INIT))
+		usb_mux_init(port);
 
-	if (port >= board_get_usb_pd_port_count()) {
+	if (exit_low_power_mode(port) != EC_SUCCESS)
 		return;
-	}
 
-	for (; mux_ptr; mux_ptr = mux_ptr->next_mux)
-		if (mux_ptr->hpd_update)
-			mux_ptr->hpd_update(mux_ptr, hpd_lvl, hpd_irq);
+	configure_mux(port, index, USB_MUX_HPD_UPDATE, &hpd_state);
+}
 
-	if (!configure_mux(port, USB_MUX_GET_MODE, &mux_state)) {
-		mux_state |= (hpd_lvl ? USB_PD_MUX_HPD_LVL : 0) |
-			     (hpd_irq ? USB_PD_MUX_HPD_IRQ : 0);
-		configure_mux(port, USB_MUX_SET_MODE, &mux_state);
+void usb_mux_hpd_update(int port, mux_state_t hpd_state)
+{
+	if (port >= board_get_usb_pd_port_count())
+		return;
+
+	/* Send to the mux task if present to maintain sequencing with sets */
+	if (IS_ENABLED(HAS_TASK_USB_MUX))
+		mux_task_enqueue(port, TYPEC_USB_MUX_SET_ALL_CHIPS,
+				 USB_MUX_HPD_UPDATE, hpd_state, 0, 0);
+	else
+		perform_mux_hpd_update(port, TYPEC_USB_MUX_SET_ALL_CHIPS,
+				       hpd_state);
+}
+
+int usb_mux_retimer_fw_update_port_info(void)
+{
+	int i;
+	int port_info = 0;
+	const struct usb_mux *mux_ptr;
+	const struct usb_mux_chain *mux_chain;
+
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		mux_chain = &usb_muxes[i];
+		while (mux_chain && mux_chain->mux) {
+			mux_ptr = mux_chain->mux;
+			if (mux_ptr->driver &&
+			    mux_ptr->driver->is_retimer_fw_update_capable &&
+			    mux_ptr->driver->is_retimer_fw_update_capable())
+				port_info |= BIT(i);
+			mux_chain = mux_chain->next;
+		}
 	}
+	return port_info;
 }
 
 static void mux_chipset_reset(void)
@@ -301,14 +699,69 @@ static void mux_chipset_reset(void)
 	int port;
 
 	for (port = 0; port < board_get_usb_pd_port_count(); ++port)
-		configure_mux(port, USB_MUX_CHIPSET_RESET, NULL);
+		configure_mux(port, TYPEC_USB_MUX_SET_ALL_CHIPS,
+			      USB_MUX_CHIPSET_RESET, NULL);
 }
 DECLARE_HOOK(HOOK_CHIPSET_RESET, mux_chipset_reset, HOOK_PRIO_DEFAULT);
 
+static void mux_chipset_suspend(void)
+{
+	int port;
+
+	for (port = 0; port < board_get_usb_pd_port_count(); ++port) {
+		if (flags[port] & USB_MUX_FLAG_IN_LPM)
+			continue;
+
+		configure_mux(port, TYPEC_USB_MUX_SET_ALL_CHIPS,
+			      USB_MUX_CHIPSET_IDLE, NULL);
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, mux_chipset_suspend, HOOK_PRIO_DEFAULT);
+
+static void mux_chipset_resume(void)
+{
+	int port;
+
+	for (port = 0; port < board_get_usb_pd_port_count(); ++port) {
+		if (flags[port] & USB_MUX_FLAG_IN_LPM)
+			continue;
+
+		configure_mux(port, TYPEC_USB_MUX_SET_ALL_CHIPS,
+			      USB_MUX_CHIPSET_ACTIVE, NULL);
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, mux_chipset_resume, HOOK_PRIO_DEFAULT);
+
+/*
+ * For muxes which have powered off in G3, clear any cached INIT and LPM flags
+ * since the chip will need reset.
+ */
+static void usb_mux_reset_in_g3(void)
+{
+	int port;
+	const struct usb_mux *mux_ptr;
+	const struct usb_mux_chain *mux_chain;
+
+	for (port = 0; port < board_get_usb_pd_port_count(); port++) {
+		mux_chain = &usb_muxes[port];
+
+		while (mux_chain && mux_chain->mux) {
+			mux_ptr = mux_chain->mux;
+			if (mux_ptr->flags & USB_MUX_FLAG_RESETS_IN_G3) {
+				atomic_clear_bits(&flags[port],
+						  USB_MUX_FLAG_INIT |
+							  USB_MUX_FLAG_IN_LPM);
+			}
+			mux_chain = mux_chain->next;
+		}
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_HARD_OFF, usb_mux_reset_in_g3, HOOK_PRIO_DEFAULT);
+
 #ifdef CONFIG_CMD_TYPEC
-static int command_typec(int argc, char **argv)
+static int command_typec(int argc, const char **argv)
 {
-	const char * const mux_name[] = {"none", "usb", "dp", "dock"};
+	const char *const mux_name[] = { "none", "usb", "dp", "dock" };
 	char *e;
 	int port;
 	mux_state_t mux = USB_PD_MUX_NONE;
@@ -331,16 +784,16 @@ static int command_typec(int argc, char **argv)
 
 		mux_state = usb_mux_get(port);
 		ccprintf("Port %d: USB=%d DP=%d POLARITY=%s HPD_IRQ=%d "
-			"HPD_LVL=%d SAFE=%d TBT=%d USB4=%d\n", port,
-			!!(mux_state & USB_PD_MUX_USB_ENABLED),
-			!!(mux_state & USB_PD_MUX_DP_ENABLED),
-			mux_state & USB_PD_MUX_POLARITY_INVERTED ?
-				"INVERTED" : "NORMAL",
-			!!(mux_state & USB_PD_MUX_HPD_IRQ),
-			!!(mux_state & USB_PD_MUX_HPD_LVL),
-			!!(mux_state & USB_PD_MUX_SAFE_MODE),
-			!!(mux_state & USB_PD_MUX_TBT_COMPAT_ENABLED),
-			!!(mux_state & USB_PD_MUX_USB4_ENABLED));
+			 "HPD_LVL=%d SAFE=%d TBT=%d USB4=%d\n",
+			 port, !!(mux_state & USB_PD_MUX_USB_ENABLED),
+			 !!(mux_state & USB_PD_MUX_DP_ENABLED),
+			 mux_state & USB_PD_MUX_POLARITY_INVERTED ? "INVERTED" :
+								    "NORMAL",
+			 !!(mux_state & USB_PD_MUX_HPD_IRQ),
+			 !!(mux_state & USB_PD_MUX_HPD_LVL),
+			 !!(mux_state & USB_PD_MUX_SAFE_MODE),
+			 !!(mux_state & USB_PD_MUX_TBT_COMPAT_ENABLED),
+			 !!(mux_state & USB_PD_MUX_USB4_ENABLED));
 
 		return EC_SUCCESS;
 	}
@@ -348,14 +801,13 @@ static int command_typec(int argc, char **argv)
 	for (i = 0; i < ARRAY_SIZE(mux_name); i++)
 		if (!strcasecmp(argv[2], mux_name[i]))
 			mux = i;
-	usb_mux_set(port, mux, mux == USB_PD_MUX_NONE ?
-				      USB_SWITCH_DISCONNECT :
-				      USB_SWITCH_CONNECT,
-			  pd_get_polarity(port));
+	usb_mux_set(port, mux,
+		    mux == USB_PD_MUX_NONE ? USB_SWITCH_DISCONNECT :
+					     USB_SWITCH_CONNECT,
+		    polarity_rm_dts(pd_get_polarity(port)));
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(typec, command_typec,
-			"[port|debug] [none|usb|dp|dock]",
+DECLARE_CONSOLE_COMMAND(typec, command_typec, "[port|debug] [none|usb|dp|dock]",
 			"Control type-C connector muxing");
 #endif
 
@@ -364,27 +816,103 @@ static enum ec_status hc_usb_pd_mux_info(struct host_cmd_handler_args *args)
 	const struct ec_params_usb_pd_mux_info *p = args->params;
 	struct ec_response_usb_pd_mux_info *r = args->response;
 	int port = p->port;
-	const struct usb_mux *me = &usb_muxes[port];
 	mux_state_t mux_state;
 
 	if (port >= board_get_usb_pd_port_count())
 		return EC_RES_INVALID_PARAM;
 
-	if (configure_mux(port, USB_MUX_GET_MODE, &mux_state))
+	if (try_usb_mux_get(port, &mux_state))
 		return EC_RES_ERROR;
-
 	r->flags = mux_state;
 
 	/* Clear HPD IRQ event since we're about to inform host of it. */
 	if (IS_ENABLED(CONFIG_USB_MUX_VIRTUAL) &&
-	    (r->flags & USB_PD_MUX_HPD_IRQ) &&
-	    (me->hpd_update == &virtual_hpd_update)) {
-		usb_mux_hpd_update(port, r->flags & USB_PD_MUX_HPD_LVL, 0);
+	    (r->flags & USB_PD_MUX_HPD_IRQ)) {
+		usb_mux_hpd_update(port, r->flags & USB_PD_MUX_HPD_LVL);
 	}
 
 	args->response_size = sizeof(*r);
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_USB_PD_MUX_INFO,
-		     hc_usb_pd_mux_info,
+DECLARE_HOST_COMMAND(EC_CMD_USB_PD_MUX_INFO, hc_usb_pd_mux_info,
 		     EC_VER_MASK(0));
+
+static enum ec_status hc_usb_pd_mux_ack(struct host_cmd_handler_args *args)
+{
+	__maybe_unused const struct ec_params_usb_pd_mux_ack *p = args->params;
+
+	if (!IS_ENABLED(CONFIG_USB_MUX_AP_ACK_REQUEST))
+		return EC_RES_INVALID_COMMAND;
+
+	if (ack_task[p->port] != TASK_ID_INVALID)
+		task_set_event(ack_task[p->port], PD_EVENT_AP_MUX_DONE);
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_USB_PD_MUX_ACK, hc_usb_pd_mux_ack, EC_VER_MASK(0));
+
+#ifdef CONFIG_CMD_RETIMER
+static int console_command_retimer(int argc, const char **argv)
+{
+	char rw, *e;
+	uint32_t reg, data, val = 0;
+	int port, rv = EC_ERROR_UNIMPLEMENTED;
+	const struct usb_mux *mux;
+	const struct usb_mux_chain *mux_chain;
+
+	if (argc < 4 || argc > 5)
+		return EC_ERROR_PARAM_COUNT;
+
+	/* Get port number */
+	port = strtoi(argv[1], &e, 0);
+	if (*e || !board_is_usb_pd_port_present(port))
+		return EC_ERROR_PARAM1;
+
+	mux_chain = &usb_muxes[port];
+	if (!mux_chain)
+		return EC_ERROR_PARAM1;
+
+	/* Validate r/w selection */
+	rw = argv[2][0];
+	if (rw != 'w' && rw != 'r')
+		return EC_ERROR_PARAM2;
+
+	/* Get register address */
+	reg = strtoull(argv[3], &e, 0);
+	if (*e)
+		return EC_ERROR_PARAM3;
+
+	/* Get value to be written */
+	if (rw == 'w') {
+		val = strtoull(argv[4], &e, 0);
+		if (*e)
+			return EC_ERROR_PARAM4;
+	}
+
+	/*
+	 * It is assumed that similar chips are connected in chain and the
+	 * same set of data is written to all the chained chips.
+	 */
+	for (; mux_chain != NULL; mux_chain = mux_chain->next) {
+		mux = mux_chain->mux;
+		if (mux->driver && mux->driver->retimer_read &&
+		    mux->driver->retimer_write) {
+			if (rw == 'r') {
+				rv = mux->driver->retimer_read(mux, reg, &data);
+				if (rv == EC_SUCCESS) {
+					CPRINTS("Addr 0x%x register %d = 0x%x",
+						mux->i2c_addr_flags, reg, data);
+				}
+			} else {
+				rv = mux->driver->retimer_write(mux, reg, val);
+			}
+		}
+	}
+
+	return rv;
+}
+DECLARE_CONSOLE_COMMAND(retimer, console_command_retimer,
+			"<port> r <reg>"
+			"\n<port> w <reg> <val>",
+			"Read or write to retimer register");
+#endif /* CONFIG_CMD_RETIMER */
diff --git a/driver/usb_mux/virtual.c b/driver/usb_mux/virtual.c
index ac41686e1f..43e4b0042f 100644
--- a/driver/usb_mux/virtual.c
+++ b/driver/usb_mux/virtual.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,6 +8,8 @@
 #include "common.h"
 #include "console.h"
 #include "host_command.h"
+#include "task.h"
+#include "timer.h"
 #include "usb_mux.h"
 #include "util.h"
 
@@ -16,19 +18,55 @@
  * configures the HPD mux state. Both states are independent of each other
  * may differ when the PD role changes when in dock mode.
  */
-#define USB_PD_MUX_HPD_STATE	(USB_PD_MUX_HPD_LVL | USB_PD_MUX_HPD_IRQ)
-#define USB_PD_MUX_USB_DP_STATE	(USB_PD_MUX_USB_ENABLED | \
-			USB_PD_MUX_DP_ENABLED | USB_PD_MUX_POLARITY_INVERTED | \
-			USB_PD_MUX_SAFE_MODE | USB_PD_MUX_TBT_COMPAT_ENABLED | \
-			USB_PD_MUX_USB4_ENABLED)
+#define USB_PD_MUX_HPD_STATE (USB_PD_MUX_HPD_LVL | USB_PD_MUX_HPD_IRQ)
+#define USB_PD_MUX_USB_DP_STATE                                \
+	(USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED |      \
+	 USB_PD_MUX_POLARITY_INVERTED | USB_PD_MUX_SAFE_MODE | \
+	 USB_PD_MUX_TBT_COMPAT_ENABLED | USB_PD_MUX_USB4_ENABLED)
 
 static mux_state_t virtual_mux_state[CONFIG_USB_PD_PORT_MAX_COUNT];
 
-static inline void virtual_mux_update_state(int port, mux_state_t mux_state)
+static inline void virtual_mux_update_state(int port, mux_state_t mux_state,
+					    bool *ack_required)
 {
+	mux_state_t previous_mux_state = virtual_mux_state[port];
+
+	/*
+	 * Initialize ack_required to false to start, and set on necessary
+	 * conditions
+	 */
+	*ack_required = false;
+
+	/*
+	 * If there is no state change, and the mux status is
+	 * clear, do not send a host event.
+	 */
+	if (mux_state == 0 && previous_mux_state == 0)
+		return;
+
 	virtual_mux_state[port] = mux_state;
 
+	if (!IS_ENABLED(CONFIG_HOSTCMD_EVENTS))
+		return;
+
 	host_set_single_event(EC_HOST_EVENT_USB_MUX);
+
+	if (!IS_ENABLED(CONFIG_USB_MUX_AP_ACK_REQUEST))
+		return;
+
+	/*
+	 * EC waits for the ACK from kernel indicating that TCSS Mux
+	 * configuration is completed. This mechanism is implemented for
+	 * entering, exiting the safe mode and entering the disconnect mode
+	 * This is needed to remove timing senstivity between BB retimer and
+	 * TCSS Mux to allow better synchronization between them and thereby
+	 * remain in the same state for achieving proper safe state
+	 * terminations.
+	 *
+	 * Note the AP will only ACK if the mux state changed in some way.
+	 */
+	if (previous_mux_state != mux_state)
+		*ack_required = true;
 }
 
 static int virtual_init(const struct usb_mux *me)
@@ -40,15 +78,24 @@ static int virtual_init(const struct usb_mux *me)
  * Set the state of our 'virtual' mux. The EC does not actually control this
  * mux, so update the desired state, then notify the host of the update.
  */
-static int virtual_set_mux(const struct usb_mux *me, mux_state_t mux_state)
+static int virtual_set_mux(const struct usb_mux *me, mux_state_t mux_state,
+			   bool *ack_required)
 {
 	int port = me->usb_port;
+	mux_state_t new_mux_state;
 
-	/* Current USB & DP mux status + existing HPD related mux status */
-	mux_state_t new_mux_state = (mux_state & ~USB_PD_MUX_HPD_STATE) |
-		(virtual_mux_state[port] & USB_PD_MUX_HPD_STATE);
+	/*
+	 * Current USB & DP mux status + existing HPD related mux status if DP
+	 * is still active.  Otherwise, don't preserve HPD state.
+	 */
+	if (mux_state & USB_PD_MUX_DP_ENABLED)
+		new_mux_state =
+			(mux_state & ~USB_PD_MUX_HPD_STATE) |
+			(virtual_mux_state[port] & USB_PD_MUX_HPD_STATE);
+	else
+		new_mux_state = mux_state;
 
-	virtual_mux_update_state(port, new_mux_state);
+	virtual_mux_update_state(port, new_mux_state, ack_required);
 
 	return EC_SUCCESS;
 }
@@ -67,16 +114,16 @@ static int virtual_get_mux(const struct usb_mux *me, mux_state_t *mux_state)
 	return EC_SUCCESS;
 }
 
-void virtual_hpd_update(const struct usb_mux *me, int hpd_lvl, int hpd_irq)
+void virtual_hpd_update(const struct usb_mux *me, mux_state_t hpd_state,
+			bool *ack_required)
 {
 	int port = me->usb_port;
 
 	/* Current HPD related mux status + existing USB & DP mux status */
-	mux_state_t new_mux_state = (hpd_lvl ? USB_PD_MUX_HPD_LVL : 0) |
-			(hpd_irq ? USB_PD_MUX_HPD_IRQ : 0) |
-			(virtual_mux_state[port] & USB_PD_MUX_USB_DP_STATE);
+	mux_state_t new_mux_state =
+		hpd_state | (virtual_mux_state[port] & USB_PD_MUX_USB_DP_STATE);
 
-	virtual_mux_update_state(port, new_mux_state);
+	virtual_mux_update_state(port, new_mux_state, ack_required);
 }
 
 const struct usb_mux_driver virtual_usb_mux_driver = {
diff --git a/driver/wpc/cps8100.c b/driver/wpc/cps8100.c
new file mode 100644
index 0000000000..006a42f131
--- /dev/null
+++ b/driver/wpc/cps8100.c
@@ -0,0 +1,978 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "cps8200_bootloader.h"
+#include "crc.h"
+#include "gpio.h"
+#include "i2c.h"
+#include "peripheral_charger.h"
+#include "printf.h"
+#include "task.h"
+#include "timer.h"
+#include "util.h"
+#include "watchdog.h"
+
+/* Print additional data */
+#define CPS8100_DEBUG
+
+#define CPUTS(outstr) cputs(CC_PCHG, outstr)
+#define CPRINTS(fmt, args...) cprints(CC_PCHG, "CPS8100: " fmt, ##args)
+#define CPRINTFP(fmt, args...) cprintf(CC_PCHG, "CPS8100: " fmt, ##args)
+#define CPRINTF(fmt, args...) cprintf(CC_PCHG, fmt, ##args)
+
+/*
+ * Configuration
+ */
+#define CPS8100_I2C_ADDR_H 0x31
+#define CPS8100_I2C_ADDR_L 0x30
+#define CPS8200_I2C_ADDR 0x30
+
+/* High address registers (commands?) */
+#define CPS8100_REGH_PASSWORD 0xf500
+#define CPS8100_REGH_ACCESS_MODE 0xf505
+#define CPS8100_REGH_ADDRESS 0xf503
+
+#define CPS8100_ACCESS_MODE_8 0x00
+#define CPS8100_ACCESS_MODE_16 0x01
+#define CPS8100_ACCESS_MODE_32 0x02
+#define CPS8100_PASSWORD 0x19e5
+#define CPS8100_CHIPID 0x8100
+#define CPS8200_CHIPID 0x8200
+
+#define CPS8200_I2C_ENABLE 0x0000000E
+#define CPS8200_PASSWORD 0x00001250
+
+/* Registers */
+#define CPS8100_REG_IC_INFO 0x20000000
+#define CPS8100_REG_FW_INFO 0x20000004
+#define CPS8100_REG_FUNC_EN 0x2000003c
+#define CPS8100_REG_ALERT_INFO 0x20000158
+#define CPS8100_REG_INT_ENABLE 0x20000160
+#define CPS8100_REG_INT_FLAG 0x20000164
+
+#define CPS8200_REG_I2C_ENABLE 0xFFFFFF00
+#define CPS8200_REG_PASSWORD 0x400140FC
+
+/* Firmware update */
+#define CPS8200_ADDR_SRAM 0x20000000
+#define CPS8200_ADDR_BUFFER0 0x20002800
+#define CPS8200_ADDR_BUFFER1 0x20003000
+#define CPS8200_ADDR_CMD 0x200038F8
+#define CPS8200_ADDR_CMD_STATUS 0x200038FC
+#define CPS8200_ADDR_BUF_SIZE 0x200038F4
+#define CFG_BUFF_SIZE 128
+#define CPS8200_CMD_TIMEOUT (3 * SECOND)
+/* CMD and CMD status. Lower 4 bits are for command ID */
+#define CMD_PGM_BUFFER0 (0x1 << 4)
+#define CMD_PGM_BUFFER1 (0x2 << 4)
+#define CMD_PGM_WR_FLAG (0x8 << 4)
+#define CMD_CACL_CRC_APP (0x9 << 4)
+#define CMD_CACL_CRC_BOOT (0xB << 4)
+#define CMD_STATUS_RUNNING (0x1 << 4)
+#define CMD_STATUS_PASS (0x2 << 4)
+#define CMD_STATUS_FAIL (0x3 << 4)
+#define CMD_STATUS_ILLEGAL (0x4 << 4)
+
+#define CPS8100_STATUS_PROFILE(r) (((r)&GENMASK(5, 4)) >> 4)
+#define CPS8100_STATUS_CHARGE(r) ((r)&BIT(6))
+#define CPS8100_STATUS_DEVICE(r) ((r)&BIT(7))
+#define CPS8100_STATUS_BATTERY(r) (((r)&GENMASK(15, 8)) >> 8)
+#define CPS8100_IRQ_TYPE(r) (((r)&GENMASK(23, 20)) >> 20)
+#define CPS8200_CMD_STATUS(flag) ((flag)&GENMASK(7, 4))
+#define CPS8X00_GET_FW_VER(value) ((value)&GENMASK(7, 0))
+#define CPS8X00_BAD_FW_VERSION 0xff
+#define CPS8200_CMD_MASK GENMASK(7, 4)
+#define CPS8200_CMD_ID_MASK GENMASK(3, 0)
+
+/* Status flags in ALERT_INFO register */
+#define CPS8100_STATUS_FOD BIT(0)
+#define CPS8100_STATUS_OCP BIT(1)
+#define CPS8100_STATUS_OVP BIT(2)
+#define CPS8100_STATUS_OTP BIT(3)
+#define CPS8100_STATUS_UVP BIT(16)
+
+/* Buffer size for i2c read & write */
+#define CPS8100_MESSAGE_BUFFER_SIZE 0x20
+
+/*
+ * CPS8100 needs 100~120ms delay and CPS8200 needs 40~50ms delay between
+ * reset and the first access to I2C register.
+ */
+#define CPS8200_POWER_ON_DELAY_MS 50
+#define CPS8100_POWER_ON_DELAY_MS 120
+
+static uint32_t chip_id;
+static const int short_sleep_ms = 2;
+
+/* TODO: Check datasheet how to wake up and how long it takes to wake up. */
+static const int cps8100_wake_up_delay_ms = 10;
+
+/* TODO: This should belong to PCHG context. Driver should be state-less. */
+struct cps8100_state {
+	struct mutex mtx;
+	uint32_t reg;
+};
+
+/* Note: Assume there is only one port. */
+static struct cps8100_state cps8100_state;
+
+struct cps8100_msg {
+	/* Data address */
+	uint8_t addr[2];
+	/* Data. Can be used for read as well. */
+	uint8_t data[2];
+} __packed;
+
+static int (*cps8x00_read32)(int port, uint32_t reg, uint32_t *val);
+
+/* This driver isn't compatible with big endian. */
+BUILD_ASSERT(__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__);
+
+static const char *const cps8100_func_names[] = {
+	[0] = "DPL",	 [1] = "OPP",	[2] = "OTP",  [3] = "OVPK",
+	[4] = "OCP",	 [5] = "UVP",	[6] = "OVP",  [7] = "FOD",
+	[8] = "SAMSUNG", [9] = "APPLE", [10] = "EPP", [11] = "HUAWEI",
+	[12] = "CPS",
+};
+
+enum cps8100_irq_type {
+	CPS8100_IRQ_TYPE_FOD = 0,
+	CPS8100_IRQ_TYPE_OCP = 1,
+	CPS8100_IRQ_TYPE_OVP = 2,
+	CPS8100_IRQ_TYPE_OTP = 3,
+	CPS8100_IRQ_TYPE_PROFILE = 4,
+	CPS8100_IRQ_TYPE_CHARGE = 5,
+	CPS8100_IRQ_TYPE_DEVICE = 6,
+	CPS8100_IRQ_TYPE_BATTERY = 7,
+	CPS8100_IRQ_TYPE_UVP = 8,
+	CPS8100_IRQ_TYPE_RESET = 9,
+	CPS8100_IRQ_TYPE_COUNT
+};
+
+static const char *const cps8100_irq_type_names[] = {
+	[CPS8100_IRQ_TYPE_FOD] = "FOD",
+	[CPS8100_IRQ_TYPE_OCP] = "OCP",
+	[CPS8100_IRQ_TYPE_OVP] = "OVP",
+	[CPS8100_IRQ_TYPE_OTP] = "OTP",
+	[CPS8100_IRQ_TYPE_PROFILE] = "PROFILE",
+	[CPS8100_IRQ_TYPE_CHARGE] = "CHARGE",
+	[CPS8100_IRQ_TYPE_DEVICE] = "DEVICE",
+	[CPS8100_IRQ_TYPE_BATTERY] = "BATTERY",
+	[CPS8100_IRQ_TYPE_UVP] = "UVP",
+	[CPS8100_IRQ_TYPE_RESET] = "RESET",
+};
+
+static const char *const cps8100_profile_names[] = {
+	[0] = "NONE",
+	[1] = "BPP",
+	[2] = "EPP",
+	[3] = "PRIVATE",
+};
+
+static void cps8100_print_func_names(const char *preamble, uint32_t reg)
+{
+	int i;
+
+	CPRINTFP("%s", preamble);
+
+	for (i = 0; i < ARRAY_SIZE(cps8100_func_names); i++) {
+		if (reg & BIT(i)) {
+			reg &= ~BIT(i);
+			CPRINTF("%s,", cps8100_func_names[i]);
+		}
+	}
+
+	if (reg)
+		CPRINTF("UNKNOWN(0x%x)", reg);
+
+	CPUTS("\n");
+}
+
+static void cps8100_print_status_flag_names(const char *preamble, uint32_t reg)
+{
+	CPRINTFP("%s", preamble);
+
+	if (reg & CPS8100_STATUS_FOD)
+		CPRINTF("FOD,");
+	if (reg & CPS8100_STATUS_OCP)
+		CPRINTF("OCP,");
+	if (reg & CPS8100_STATUS_OVP)
+		CPRINTF("OVP,");
+	if (reg & CPS8100_STATUS_OTP)
+		CPRINTF("OTP,");
+	if (reg & CPS8100_STATUS_UVP)
+		CPRINTF("UVP,");
+
+	CPUTS("\n");
+}
+
+static void cps8100_print_irq_type_names(const char *preamble, uint32_t reg)
+{
+	int type;
+
+	CPRINTFP("%s", preamble);
+
+	type = CPS8100_IRQ_TYPE(reg);
+	if (type >= CPS8100_IRQ_TYPE_COUNT)
+		CPRINTF("UNKNOWN(%d), ", type);
+	else
+		CPRINTF("%s", cps8100_irq_type_names[type]);
+	CPUTS("\n");
+}
+
+static void cps8100_status_update(struct pchg *ctx, uint32_t reg)
+{
+	mutex_lock(&cps8100_state.mtx);
+	cps8100_state.reg = reg;
+	mutex_unlock(&cps8100_state.mtx);
+}
+
+static int cps8100_i2c_write(int port, int addr, const uint8_t *buf, size_t len)
+{
+	int rv;
+
+	/* Assumes a write is always 2 bytes. */
+	rv = i2c_xfer(port, addr, buf, len, NULL, 0);
+
+	if (rv) {
+		msleep(cps8100_wake_up_delay_ms);
+		rv = i2c_xfer(port, addr, buf, len, NULL, 0);
+	}
+	if (rv)
+		CPRINTS("Failed to write: %d", rv);
+
+	return rv;
+}
+
+static int cps8100_set_unlock(int port)
+{
+	const uint8_t cps8100_unlock_cmd[] = {
+		/* Password register address */
+		(CPS8100_REGH_PASSWORD >> 8) & 0xff,
+		(CPS8100_REGH_PASSWORD >> 0) & 0xff,
+		/* Password */
+		(CPS8100_PASSWORD >> 0) & 0xff,
+		(CPS8100_PASSWORD >> 8) & 0xff,
+	};
+
+	return cps8100_i2c_write(port, CPS8100_I2C_ADDR_H, cps8100_unlock_cmd,
+				 4);
+}
+
+static int cps8200_set_unlock(int port)
+{
+	const uint8_t cps8200_unlock_cmd[] = {
+		/* Password register addr */
+		(CPS8200_REG_PASSWORD >> 24) & 0xff,
+		(CPS8200_REG_PASSWORD >> 16) & 0xff,
+		(CPS8200_REG_PASSWORD >> 8) & 0xff,
+		(CPS8200_REG_PASSWORD >> 0) & 0xff,
+		/* Password */
+		(CPS8200_PASSWORD >> 0) & 0xff,
+		(CPS8200_PASSWORD >> 8) & 0xff,
+		(CPS8200_PASSWORD >> 16) & 0xff,
+		(CPS8200_PASSWORD >> 24) & 0xff,
+	};
+
+	return cps8100_i2c_write(port, CPS8200_I2C_ADDR, cps8200_unlock_cmd, 8);
+}
+
+static int cps8200_i2c_enable(int port)
+{
+	const uint8_t cps8200_i2c_enable_cmd[] = {
+		/* addr */
+		(CPS8200_REG_I2C_ENABLE >> 24) & 0xff,
+		(CPS8200_REG_I2C_ENABLE >> 16) & 0xff,
+		(CPS8200_REG_I2C_ENABLE >> 8) & 0xff,
+		(CPS8200_REG_I2C_ENABLE >> 0) & 0xff,
+		/* data */
+		(CPS8200_I2C_ENABLE >> 0) & 0xff,
+		(CPS8200_I2C_ENABLE >> 8) & 0xff,
+		(CPS8200_I2C_ENABLE >> 16) & 0xff,
+		(CPS8200_I2C_ENABLE >> 24) & 0xff,
+	};
+
+	return cps8100_i2c_write(port, CPS8200_I2C_ADDR, cps8200_i2c_enable_cmd,
+				 8);
+}
+
+static int cps8100_set_write_mode(int port, uint8_t mode)
+{
+	uint8_t buf[4];
+
+	buf[0] = 0xf5;
+	buf[1] = 0x05;
+	buf[2] = mode;
+	buf[3] = 0x00;
+
+	return cps8100_i2c_write(port, CPS8100_I2C_ADDR_H, buf, 4);
+}
+
+static int cps8100_set_high_address(int port, uint32_t addr)
+{
+	uint8_t buf[4];
+
+	buf[0] = 0xf5;
+	buf[1] = 0x03;
+	buf[2] = (addr >> 16) & 0xff;
+	buf[3] = (addr >> 24) & 0xff;
+
+	return cps8100_i2c_write(port, CPS8100_I2C_ADDR_H, buf, 4);
+}
+
+static int cps8100_read32(int port, uint32_t reg, uint32_t *val)
+{
+	uint8_t buf[CPS8100_MESSAGE_BUFFER_SIZE];
+
+	if (cps8100_set_high_address(port, reg))
+		return EC_ERROR_UNKNOWN;
+
+	/* Set low 16 bits of register address and read a byte. */
+	buf[0] = (reg >> 8) & 0xff;
+	buf[1] = (reg >> 0) & 0xff;
+
+	return i2c_xfer(port, CPS8100_I2C_ADDR_L, buf, 2, (void *)val,
+			sizeof(*val));
+}
+
+static int cps8200_write32(int port, uint32_t reg, uint32_t val)
+{
+	uint8_t buf[8];
+
+	buf[0] = (reg >> 24) & 0xff;
+	buf[1] = (reg >> 16) & 0xff;
+	buf[2] = (reg >> 8) & 0xff;
+	buf[3] = (reg >> 0) & 0xff;
+
+	buf[4] = (val >> 0) & 0xff;
+	buf[5] = (val >> 8) & 0xff;
+	buf[6] = (val >> 16) & 0xff;
+	buf[7] = (val >> 24) & 0xff;
+
+	return cps8100_i2c_write(port, CPS8200_I2C_ADDR, buf, sizeof(buf));
+}
+
+static int cps8200_read32(int port, uint32_t reg, uint32_t *val)
+{
+	uint8_t buf[4];
+
+	buf[0] = (reg >> 24) & 0xff;
+	buf[1] = (reg >> 16) & 0xff;
+	buf[2] = (reg >> 8) & 0xff;
+	buf[3] = (reg >> 0) & 0xff;
+
+	return i2c_xfer(port, CPS8200_I2C_ADDR, buf, sizeof(buf), (void *)val,
+			sizeof(*val));
+}
+
+static int cps8200_write_mem(int port, uint32_t addr, uint8_t *data, size_t len)
+{
+	int rv;
+	uint8_t buf[4];
+
+	buf[0] = (addr >> 24) & 0xff;
+	buf[1] = (addr >> 16) & 0xff;
+	buf[2] = (addr >> 8) & 0xff;
+	buf[3] = (addr >> 0) & 0xff;
+
+	i2c_lock(port, 1);
+	/* Addr */
+	rv = i2c_xfer_unlocked(port, CPS8200_I2C_ADDR, buf, sizeof(buf), NULL,
+			       0, I2C_XFER_START);
+	if (rv) {
+		i2c_lock(port, 0);
+		return rv;
+	}
+	/* Data */
+	rv = i2c_xfer_unlocked(port, CPS8200_I2C_ADDR, data, len, NULL, 0,
+			       I2C_XFER_STOP);
+	i2c_lock(port, 0);
+
+	return rv;
+}
+
+static int cps8100_unlock(int port)
+{
+	int rv;
+
+	rv = cps8100_set_unlock(port);
+	return rv ? rv : cps8100_set_write_mode(port, CPS8100_ACCESS_MODE_32);
+}
+
+static int cps8200_unlock(int port)
+{
+	int rv;
+
+	rv = cps8200_i2c_enable(port);
+	return rv ? rv : cps8200_set_unlock(port);
+}
+
+/*
+ * Send command to CPS8200 by writing command to CPS8200_ADDR_CMD register.
+ * command = cmd (higher 4 bits) + id (lower 4 bits), id needs to be increased
+ * every time.
+ */
+static uint8_t cps8200_send_cmd(struct pchg *ctx, uint8_t cmd, uint8_t *id)
+{
+	uint8_t port = ctx->cfg->i2c_port;
+	struct cps8x00_update *upd = &(ctx->update.driver_data.cps8200_update);
+
+	*id = upd->cmd_id;
+	cmd &= CPS8200_CMD_MASK;
+	cmd |= *id;
+	upd->cmd_id++;
+	upd->cmd_id &= CPS8200_CMD_ID_MASK;
+
+	return cps8200_write32(port, CPS8200_ADDR_CMD, (uint32_t)cmd);
+}
+
+/*
+ * Read the response of command by reading CPS8200_ADDR_CMD_STATUS register.
+ * Return EC_SUCCESS if the status is CMD_STATUS_PASS and the id matches to
+ * the id which is expected.
+ */
+static int cps8200_wait_cmd_done(int port, uint8_t id)
+{
+	int rv;
+	uint32_t u32;
+	timestamp_t deadline;
+
+	deadline.val = get_time().val + CPS8200_CMD_TIMEOUT;
+	while (1) {
+		msleep(10);
+		rv = cps8200_read32(port, CPS8200_ADDR_CMD_STATUS, &u32);
+		if (rv)
+			return EC_ERROR_UNKNOWN;
+
+		if ((CMD_STATUS_PASS | id) == (u32 & 0x00ff))
+			break;
+		if (CPS8200_CMD_STATUS(u32) == CMD_STATUS_FAIL ||
+		    CPS8200_CMD_STATUS(u32) == CMD_STATUS_ILLEGAL) {
+			CPRINTS("Command failed or illegal: %02x",
+				CPS8200_CMD_STATUS(u32));
+			return EC_ERROR_UNKNOWN;
+		}
+
+		rv = timestamp_expired(deadline, NULL);
+		if (rv) {
+			CPRINTS("Command timeout!");
+			return EC_ERROR_TIMEOUT;
+		}
+	}
+	return EC_SUCCESS;
+}
+
+static int cps8x00_read_firmware_ver(struct pchg *ctx)
+{
+	uint32_t u32;
+	int port = ctx->cfg->i2c_port;
+	int rv;
+
+	rv = cps8x00_read32(port, CPS8100_REG_FW_INFO, &u32);
+	if (!rv) {
+		ctx->fw_version = CPS8X00_GET_FW_VER(u32);
+	} else {
+		ctx->fw_version = CPS8X00_BAD_FW_VERSION;
+		CPRINTS("Failed to read FW info: %d", rv);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+static int cps8x00_reset(struct pchg *ctx)
+{
+	gpio_set_level(GPIO_QI_RESET_L, 0);
+	cps8100_status_update(ctx, 0);
+	udelay(15);
+	gpio_set_level(GPIO_QI_RESET_L, 1);
+
+	return EC_SUCCESS;
+}
+
+static int cps8x00_init(struct pchg *ctx)
+{
+	int port = ctx->cfg->i2c_port;
+
+	/* Enable I2C, unlock and set mode */;
+	if (chip_id == CPS8100_CHIPID)
+		return cps8100_unlock(port);
+	else if (chip_id == CPS8200_CHIPID)
+		return cps8200_unlock(port);
+	else
+		return EC_ERROR_UNKNOWN;
+}
+
+static int cps8x00_enable(struct pchg *ctx, bool enable)
+{
+	return EC_SUCCESS;
+}
+
+static int cps8100_get_alert_info(struct pchg *ctx, uint32_t *reg)
+{
+	int rv;
+
+	rv = cps8x00_read32(ctx->cfg->i2c_port, CPS8100_REG_ALERT_INFO, reg);
+	if (rv) {
+		CPRINTS("Failed to get alert info (%d)", rv);
+		return rv;
+	}
+
+	return EC_SUCCESS;
+}
+
+static int cps8x00_get_chip_info(struct pchg *ctx)
+{
+	uint32_t u32;
+	int port = ctx->cfg->i2c_port;
+	int rv = EC_ERROR_UNKNOWN;
+
+	if (chip_id == CPS8100_CHIPID) {
+		/*
+		 * already probed but unlock again in case it's turned
+		 * off.
+		 */
+		msleep(CPS8100_POWER_ON_DELAY_MS);
+		return cps8100_unlock(port);
+	} else if (chip_id == CPS8200_CHIPID) {
+		msleep(CPS8200_POWER_ON_DELAY_MS);
+		return cps8200_unlock(port);
+	}
+
+	/* not probed yet, need to unlock blindly first. */
+	msleep(MAX(CPS8100_POWER_ON_DELAY_MS, CPS8200_POWER_ON_DELAY_MS));
+	if (!cps8100_unlock(port))
+		rv = cps8100_read32(port, CPS8100_REG_IC_INFO, &u32);
+	else if (!cps8200_unlock(port))
+		rv = cps8200_read32(port, CPS8100_REG_IC_INFO, &u32);
+
+	if (rv) {
+		CPRINTS("Failed to read IC info!");
+		return rv;
+	}
+
+	/* Probe */
+	CPRINTS("IC=0x%08x", u32);
+	if ((u32 & 0xffff) == CPS8100_CHIPID) {
+		cps8x00_read32 = cps8100_read32;
+		chip_id = CPS8100_CHIPID;
+	} else if ((u32 & 0xffff) == CPS8200_CHIPID) {
+		cps8x00_read32 = cps8200_read32;
+		chip_id = CPS8200_CHIPID;
+	} else {
+		CPRINTS("Unknown chip!");
+		return EC_ERROR_UNKNOWN;
+	}
+
+	rv = cps8x00_read_firmware_ver(ctx);
+	if (!rv)
+		CPRINTS("FW=0x%02x", ctx->fw_version);
+
+	return EC_SUCCESS;
+}
+
+static void cps8100_print_alert_info(uint32_t reg)
+{
+	cps8100_print_irq_type_names("IRQ_TYPE: ", reg);
+	cps8100_print_status_flag_names("ERRORS: ", reg);
+
+	CPRINTFP("Profile: %s\n",
+		 cps8100_profile_names[CPS8100_STATUS_PROFILE(reg)]);
+	CPRINTFP("%sCharging\n", CPS8100_STATUS_CHARGE(reg) ? "" : "Not ");
+	CPRINTFP("Device %sPresent\n",
+		 CPS8100_STATUS_DEVICE(reg) ? "" : "Not ");
+	CPRINTFP("Battery: %d%%\n", CPS8100_STATUS_BATTERY(reg));
+}
+
+static int cps8x00_get_event(struct pchg *ctx)
+{
+	uint32_t r1, r2;
+	int rv;
+
+	r1 = cps8100_state.reg;
+	rv = cps8100_get_alert_info(ctx, &r2);
+	if (rv)
+		return rv;
+
+	if (IS_ENABLED(CPS8100_DEBUG))
+		cps8100_print_alert_info(r2);
+
+	/* Check status change in the order of priority. */
+	if (CPS8100_IRQ_TYPE(r2) == CPS8100_IRQ_TYPE_RESET) {
+		ctx->event = PCHG_EVENT_RESET;
+	} else if (!CPS8100_STATUS_DEVICE(r1) && CPS8100_STATUS_DEVICE(r2)) {
+		ctx->event = PCHG_EVENT_DEVICE_CONNECTED;
+	} else if (CPS8100_STATUS_DEVICE(r1) && !CPS8100_STATUS_DEVICE(r2)) {
+		ctx->event = PCHG_EVENT_DEVICE_LOST;
+	} else if (CPS8100_STATUS_PROFILE(r1) != CPS8100_STATUS_PROFILE(r2)) {
+		ctx->event = PCHG_EVENT_CHARGE_UPDATE;
+		ctx->battery_percent = CPS8100_STATUS_BATTERY(r2);
+	} else if (!CPS8100_STATUS_CHARGE(r1) && CPS8100_STATUS_CHARGE(r2)) {
+		ctx->event = PCHG_EVENT_CHARGE_STARTED;
+	} else if (CPS8100_STATUS_CHARGE(r1) && !CPS8100_STATUS_CHARGE(r2)) {
+		ctx->event = PCHG_EVENT_CHARGE_STOPPED;
+	} else if (CPS8100_STATUS_BATTERY(r1) != CPS8100_STATUS_BATTERY(r2)) {
+		ctx->event = PCHG_EVENT_CHARGE_UPDATE;
+		ctx->battery_percent = CPS8100_STATUS_BATTERY(r2);
+	} else if (ctx->state == PCHG_STATE_RESET) {
+		ctx->event = PCHG_EVENT_RESET;
+	} else {
+		ctx->event = PCHG_EVENT_NONE;
+	}
+
+	cps8100_status_update(ctx, r2);
+
+	return EC_SUCCESS;
+}
+
+static int cps8x00_get_soc(struct pchg *ctx)
+{
+	ctx->battery_percent = CPS8100_STATUS_BATTERY(cps8100_state.reg);
+
+	return EC_SUCCESS;
+}
+
+/*
+ * This function does the preparation for firmware update, the steps are:
+ * 1. Enable i2c and unlock.
+ * 2. Reset MCU, reset watchdog, disable DCDC and reset MCU clock.
+ * 3. Program bootloader to SRAM.
+ * 4. Run bootloader.
+ * 5. Check CRC of bootloader.
+ * 6. Ready for firmware download. Configure buffer size for firmware download.
+ */
+static int cps8200_update_open(struct pchg *ctx)
+{
+	uint32_t u32;
+	uint8_t id;
+	int port = ctx->cfg->i2c_port;
+	int rv;
+	struct cps8x00_update *upd = &(ctx->update.driver_data.cps8200_update);
+
+	upd->cmd_id = 0;
+	upd->crc = 0;
+	upd->firmware_len = 0;
+
+	/* enable i2c and unlock */
+	rv = cps8200_unlock(port);
+	if (rv)
+		return rv;
+
+	/*
+	 * The value and address of the registers are from the sample code
+	 * and programming guide provided by the vendor in
+	 * https://issuetracker.google.com/issues/195708351#comment32
+	 */
+
+	/* Reset MCU and halt */
+	rv = cps8200_write32(port, 0x40014028, 0x00010000);
+	if (rv)
+		return rv;
+	msleep(50);
+
+	/* Reset watchdog */
+	rv = cps8200_write32(port, 0x40008400, 0x1ACCE551);
+	if (rv)
+		return rv;
+	msleep(short_sleep_ms);
+	rv = cps8200_write32(port, 0x40008008, 0x0);
+	if (rv)
+		return rv;
+	msleep(short_sleep_ms);
+
+	/* Disable DCDC module */
+	rv = cps8200_write32(port, 0x4000F0A4, 0x0);
+	if (rv)
+		return rv;
+	msleep(50);
+
+	/* Reset MCU clock */
+	rv = cps8200_write32(port, 0x40014020, 0x0);
+	if (rv)
+		return rv;
+	msleep(short_sleep_ms);
+	rv = cps8200_write32(port, 0x40014024, 0x0);
+	if (rv)
+		return rv;
+	msleep(short_sleep_ms);
+	rv = cps8200_write32(port, 0x400140A8, 0x0);
+	if (rv)
+		return rv;
+	msleep(short_sleep_ms);
+
+	/* Program bootloader to SRAM */
+	CPRINTS("Loading bootloader hex!");
+	if (cps8200_write_mem(port, CPS8200_ADDR_SRAM, (uint8_t *)&boot_hex,
+			      boot_hex_len * 4)) {
+		CPRINTS("Failed to write bootloader!");
+		return EC_ERROR_UNKNOWN;
+	}
+	msleep(short_sleep_ms);
+
+	/* disable trim */
+	rv = cps8200_write32(port, 0x4001F01C, 0x0);
+	if (rv)
+		return rv;
+	msleep(short_sleep_ms);
+
+	/* enable address remap */
+	rv = cps8200_write32(port, 0x4001F030, 0xFFFFFF00);
+	if (rv)
+		return rv;
+	msleep(short_sleep_ms);
+	rv = cps8200_write32(port, 0x4001F034, 0xFFFFFFFF);
+	if (rv)
+		return rv;
+	msleep(short_sleep_ms);
+	rv = cps8200_write32(port, 0x4001F038, 0xFFFFFFFF);
+	if (rv)
+		return rv;
+	msleep(short_sleep_ms);
+	rv = cps8200_write32(port, 0x4001F03C, 0xFFFFFFFF);
+	if (rv)
+		return rv;
+	msleep(short_sleep_ms);
+
+	/* disable mcu halt, run bootloader */
+	rv = cps8200_write32(port, 0x40014028, 0x101);
+	if (rv)
+		return rv;
+	msleep(short_sleep_ms);
+
+	/* enable i2c and unlock */
+	rv = cps8200_i2c_enable(port);
+	if (rv)
+		return rv;
+	msleep(short_sleep_ms);
+
+	/* write bootloader length */
+	rv = cps8200_write32(port, CPS8200_ADDR_BUFFER0, boot_hex_len * 4);
+	if (rv)
+		return rv;
+	msleep(short_sleep_ms);
+
+	/* calculate CRC of bootloader */
+	rv = cps8200_send_cmd(ctx, CMD_CACL_CRC_BOOT, &id);
+	if (rv)
+		return rv;
+
+	/* check command status */
+	rv = cps8200_wait_cmd_done(port, id);
+	if (rv)
+		return rv;
+	msleep(100);
+
+	/* check CRC */
+	rv = cps8200_read32(port, CPS8200_ADDR_BUFFER0, &u32);
+	if (rv)
+		return rv;
+	upd->crc = cros_crc16((uint8_t *)boot_hex, boot_hex_len * 4, 0);
+	if (upd->crc != (u32 & 0x0000ffff)) {
+		CPRINTS("crc = %04x, expect %04x", u32, upd->crc);
+		CPRINTS("CRC of bootloader is wroing!");
+		return EC_ERROR_UNKNOWN;
+	}
+	CPRINTS("Successfully load bootloader!");
+
+	upd->crc = 0x0000;
+	/* Prepare to download firmware and program flash, change buffer size */
+	rv = cps8200_write32(port, CPS8200_ADDR_BUF_SIZE,
+			     ctx->cfg->block_size / 4);
+	if (rv) {
+		CPRINTS("Failed to change buffer size (%d)", rv);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+/*
+ * This function writes the firmware block to the chip and returns only after
+ * the write is complete. The steps are:
+ * 1. Write firmware block to the chip buffer.
+ * 2. Send command to the chip.
+ * 3. The chip program the flash.
+ * 4. Calculate and update CRC.
+ */
+static int cps8200_update_write(struct pchg *ctx)
+{
+	int port = ctx->cfg->i2c_port;
+	int rv;
+	uint8_t id;
+	uint8_t *buf = ctx->update.data;
+	struct cps8x00_update *upd = &(ctx->update.driver_data.cps8200_update);
+
+	/* Write data to buffer */
+	if (cps8200_write_mem(port, CPS8200_ADDR_BUFFER0, buf,
+			      ctx->update.size))
+		return EC_ERROR_UNKNOWN;
+	msleep(short_sleep_ms);
+
+	/* Write buffer to flash */
+	rv = cps8200_send_cmd(ctx, CMD_PGM_BUFFER0, &id);
+	if (rv)
+		return rv;
+
+	/* Check the program result */
+	rv = cps8200_wait_cmd_done(port, id);
+	if (rv) {
+		CPRINTS("Failed to write flash : %d", rv);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	/* Calculate and update CRC */
+	upd->firmware_len += ctx->update.size;
+	upd->crc = cros_crc16(ctx->update.data, ctx->update.size, upd->crc);
+
+	return EC_SUCCESS;
+}
+
+/*
+ * This function checks firmware update result, power on and power off the chip
+ * if firmware update is successful. The steps are:
+ * 1. Send command to the chip to calculate the firmware CRC.
+ * 2. Read the CRC value from the chip and compare.
+ * 3. If CRC is correct, power off and power on the chip.
+ */
+static int cps8200_update_close(struct pchg *ctx)
+{
+	int port = ctx->cfg->i2c_port;
+	int rv;
+	uint32_t u32;
+	uint8_t id;
+	struct cps8x00_update *upd = &(ctx->update.driver_data.cps8200_update);
+	uint32_t len = upd->firmware_len;
+
+	/* Write firmware length */
+	rv = cps8200_write32(port, CPS8200_ADDR_BUFFER0, len);
+	if (rv)
+		return rv;
+	msleep(short_sleep_ms);
+
+	/* Check firmware CRC */
+	CPRINTS("Checking Firmware CRC...");
+	rv = cps8200_send_cmd(ctx, CMD_CACL_CRC_APP, &id);
+	if (rv)
+		return rv;
+
+	rv = cps8200_wait_cmd_done(port, id);
+	if (rv) {
+		CPRINTS("Command to calculate CRC timeout or failed: %d", rv);
+		return EC_ERROR_UNKNOWN;
+	}
+	msleep(100);
+
+	cps8200_read32(port, CPS8200_ADDR_BUFFER0, &u32);
+	if (upd->crc != (u32 & 0x0000ffff)) {
+		CPRINTS("crc = %04x, expect %04x", u32, upd->crc);
+		CPRINTS("CRC of firmware is wroing!");
+		return EC_ERROR_UNKNOWN;
+	}
+	CPRINTS("Firmware CRC is correct!");
+	CPRINTS("Successfully update the firmware");
+
+	rv = cps8200_send_cmd(ctx, CMD_PGM_WR_FLAG, &id);
+	if (rv)
+		return rv;
+
+	rv = cps8200_wait_cmd_done(port, id);
+	if (rv) {
+		CPRINTS("Command to program flash failed: %d", rv);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	/*
+	 * Due to the CPS8200 issue
+	 * (https://issuetracker.google.com/issues/258093708), we can't simply
+	 * reset CPS8200. CPS8200 needs to be powered off to completely reset
+	 * its internal modules after completing the firmware update, and then
+	 * power on after some delay. We need 50ms delay after power on to
+	 * ensure there is enough delay before first I2C command
+	 */
+
+	/* power off MCU */
+	board_pchg_power_on(PCHG_CTX_TO_PORT(ctx), 0);
+	msleep(short_sleep_ms);
+	/* power on MCU */
+	board_pchg_power_on(PCHG_CTX_TO_PORT(ctx), 1);
+	msleep(CPS8200_POWER_ON_DELAY_MS);
+	/* Update the information of firmware version */
+	cps8200_unlock(port);
+	rv = cps8x00_read_firmware_ver(ctx);
+	if (!rv)
+		CPRINTS("FW=0x%02x", ctx->fw_version);
+
+	return EC_SUCCESS;
+}
+
+const struct pchg_drv cps8100_drv = {
+	.reset = cps8x00_reset,
+	.init = cps8x00_init,
+	.enable = cps8x00_enable,
+	.get_chip_info = cps8x00_get_chip_info,
+	.get_event = cps8x00_get_event,
+	.get_soc = cps8x00_get_soc,
+};
+
+const struct pchg_drv cps8200_drv = {
+	.reset = cps8x00_reset,
+	.init = cps8x00_init,
+	.enable = cps8x00_enable,
+	.get_chip_info = cps8x00_get_chip_info,
+	.get_event = cps8x00_get_event,
+	.get_soc = cps8x00_get_soc,
+	.update_open = cps8200_update_open,
+	.update_write = cps8200_update_write,
+	.update_close = cps8200_update_close,
+};
+
+static void cps8100_dump(struct pchg *ctx)
+{
+	uint32_t val;
+	int rv;
+
+	rv = cps8x00_read32(ctx->cfg->i2c_port, CPS8100_REG_FUNC_EN, &val);
+	if (rv == EC_SUCCESS)
+		cps8100_print_func_names("FEATURES: ", val);
+
+	rv = cps8100_get_alert_info(ctx, &val);
+	if (rv == EC_SUCCESS)
+		cps8100_print_alert_info(val);
+}
+
+static int cc_cps8100(int argc, const char **argv)
+{
+	struct pchg *ctx;
+	char *end;
+	int port;
+
+	if (argc < 2 || 3 < argc)
+		return EC_ERROR_PARAM_COUNT;
+
+	port = strtoi(argv[1], &end, 0);
+	if (*end || port < 0 || board_get_pchg_count() <= port)
+		return EC_ERROR_PARAM2;
+
+	ctx = &pchgs[port];
+
+	if (argc == 2) {
+		cps8100_dump(ctx);
+		return EC_SUCCESS;
+	}
+
+	if (!strcasecmp(argv[2], "reset")) {
+		cps8x00_reset(ctx);
+		cps8x00_init(ctx);
+	} else {
+		return EC_ERROR_PARAM3;
+	}
+
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(cps8100, cc_cps8100, "<port> [reset]",
+			"Print status of or reset CPS8100");
diff --git a/driver/wpc/cps8100.h b/driver/wpc/cps8100.h
new file mode 100644
index 0000000000..644ee37089
--- /dev/null
+++ b/driver/wpc/cps8100.h
@@ -0,0 +1,16 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* cps8100 Qi wireless power transmitter module for Chrome EC */
+
+#ifndef __CROS_EC_WPC_CPS8100_H
+#define __CROS_EC_WPC_CPS8100_H
+
+#include "peripheral_charger.h"
+
+extern struct pchg_drv cps8100_drv;
+extern struct pchg_drv cps8200_drv;
+
+#endif /* __CROS_EC_WPC_CPS8100_H */
diff --git a/driver/wpc/cps8200_bootloader.h b/driver/wpc/cps8200_bootloader.h
new file mode 100644
index 0000000000..32b0af4a23
--- /dev/null
+++ b/driver/wpc/cps8200_bootloader.h
@@ -0,0 +1,85 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+const uint32_t boot_hex[] = {
+	0x20003D00, 0x20000149, 0x20000157, 0x20000159, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x2000015B,
+	0x00000000, 0x00000000, 0x2000015D, 0x2000015F, 0x20000161, 0x20000161,
+	0x20000161, 0x20000161, 0x20000161, 0x20000161, 0x20000161, 0x20000161,
+	0x20000161, 0x20000161, 0x20000161, 0x20000161, 0x20000161, 0x20000161,
+	0x20000161, 0x20000161, 0x20000161, 0x20000161, 0x20000161, 0x20000161,
+	0x20000161, 0x20000161, 0x20000161, 0x20000161, 0x20000161, 0x20000161,
+	0x20000161, 0x20000161, 0x20000161, 0x20000161, 0x20000161, 0x20000161,
+	0xF802F000, 0xF830F000, 0xC830A00C, 0x18243808, 0x46A2182D, 0x46AB1E67,
+	0x465D4654, 0xD10142AC, 0xF822F000, 0x3E0F467E, 0x46B6CC0F, 0x42332601,
+	0x1AFBD000, 0x46AB46A2, 0x47184333, 0x0000061C, 0x0000062C, 0x24002300,
+	0x26002500, 0xD3013A10, 0xD8FBC178, 0xD3000752, 0xD500C130, 0x4770600B,
+	0xBD1FB51F, 0xBD10B510, 0xFAC3F000, 0xF7FF4611, 0xF000FFF7, 0xF000FA8C,
+	0xB403FADB, 0xFFF2F7FF, 0xF000BC03, 0x0000FAE1, 0x490A4809, 0x480A6001,
+	0x480A4780, 0xE7FE4700, 0xE7FEE7FE, 0xE7FEE7FE, 0x0000E7FE, 0x49074806,
+	0x4B084A07, 0x00004770, 0x4001F030, 0xFFFFFFFF, 0x200006AB, 0x200000C1,
+	0x20002060, 0x20003D00, 0x20002460, 0x20003900, 0x48FD49FE, 0x49FE63C8,
+	0x60082000, 0x202049FC, 0x60083914, 0x210B48FB, 0x60416001, 0x60812100,
+	0x48F760C1, 0x698130E8, 0x04522201, 0x61814391, 0x09096981, 0x1C490109,
+	0x49F16181, 0x680A3168, 0x439A0583, 0x6981600A, 0x0112223F, 0x31C04391,
+	0x69826181, 0x430A1399, 0x69826182, 0x431A1403, 0x4AE96182, 0x1C402000,
+	0xD3FC4290, 0x38C048E3, 0x438A6B02, 0x6B026302, 0x01D209D2, 0x6302325F,
+	0x430A6B02, 0x68026302, 0x6002438A, 0x09526802, 0x60020152, 0x430A6802,
+	0x6A026002, 0x431A2301, 0x68426202, 0x6042438A, 0x09126842, 0x60420112,
+	0x430A6842, 0x47706042, 0x210348D2, 0x4AD162C1, 0x32C02100, 0x61816391,
+	0x61C22201, 0x48CB6102, 0x460863C1, 0x4ACB4770, 0x62516210, 0x20082163,
+	0x43036AD3, 0x1E4962D3, 0x6AD1D2FA, 0x62D14301, 0x43016AD1, 0x6AD162D1,
+	0x62D14381, 0x06806BD0, 0x2062D4FC, 0xD2FD1E40, 0x47702000, 0x48BA49BB,
+	0x49BC63C8, 0x62C82003, 0x210148BA, 0x638130C0, 0x63C149BA, 0x47702000,
+	0x4604B570, 0x4DB82000, 0xE00E4602, 0x021B5CA3, 0x23004058, 0xD5020406,
+	0x40680040, 0x0040E000, 0xB2801C5B, 0xDBF52B08, 0x428A1C52, 0xBD70D3EE,
+	0x260048A8, 0x463449A6, 0x4AA863C1, 0x63C661D6, 0xFFD0F7FF, 0x48AA49A9,
+	0xFFB1F7FF, 0xFFA0F7FF, 0x680849A8, 0xD0FB2800, 0x600A2200, 0x600849A6,
+	0x400121F0, 0x0F000700, 0x42A04615, 0x48A3D105, 0x22016800, 0x42900252,
+	0x2040DD05, 0x48A04304, 0x24006004, 0x2010E7E4, 0x43204A9D, 0x4A916010,
+	0x63D0488F, 0xD01C2990, 0x2910DC06, 0x2920D036, 0x2980D051, 0xE029D163,
+	0xD02329A0, 0xD15E29B0, 0x68284D94, 0x03092101, 0xDD034288, 0x43C02000,
+	0xE03C6028, 0x20016829, 0xF7FF0740, 0x6028FF99, 0x4982E052, 0x61C82001,
+	0x62784F8B, 0x68294D89, 0x07002003, 0xFF8CF7FF, 0x62792100, 0x487B6028,
+	0xE04161C1, 0x20004983, 0xE03D6008, 0xFF72F7FF, 0x487B4982, 0xFF53F7FF,
+	0xE0124605, 0xFF6AF7FF, 0xE0082700, 0x00B9487B, 0x46305841, 0xFF47F7FF,
+	0x1D364305, 0x48751C7F, 0x42876800, 0x4875DBF2, 0xF7FFE01B, 0x1C68FF2D,
+	0x2D00D019, 0x4620D01C, 0x43082130, 0xF7FFE01A, 0x2700FF4D, 0x4870E008,
+	0x584100B9, 0xF7FF4630, 0x4305FF2A, 0x1C7F1D36, 0x68004866, 0xDBF24287,
+	0x60064869, 0x4964E7E1, 0x60082040, 0xE0062400, 0x43202020, 0x60084960,
+	0x07241C64, 0x49530F24, 0x63C82000, 0x2100E760, 0x43C9485D, 0x63416301,
+	0x63C16381, 0x62422201, 0x20004A4E, 0x62506210, 0x62D32303, 0x6313230E,
+	0x4A4A6350, 0x635032C0, 0x63D06390, 0x38404845, 0x08926802, 0x1C520092,
+	0x68026002, 0x439A230C, 0x60021D12, 0x23306802, 0x3210439A, 0x68026002,
+	0x439A23C0, 0x60023240, 0x009B6802, 0x6002439A, 0x009B6802, 0x6002439A,
+	0x009B6802, 0x6002439A, 0x009B6802, 0x6002439A, 0x009B6802, 0x6002439A,
+	0x009B6802, 0x6002439A, 0x009B6802, 0x6002439A, 0x009B6802, 0x6002439A,
+	0x009B6802, 0x6002439A, 0x009B6802, 0x6002439A, 0x009B6802, 0x0543439A,
+	0x600218D2, 0x05C36802, 0x08920092, 0x600218D2, 0x08D26842, 0x1C5200D2,
+	0x68426042, 0x439A2318, 0x60423208, 0x6101482B, 0x61416041, 0x47702000,
+	0x4B18B570, 0x63D84816, 0x48274928, 0x4A286008, 0x60902000, 0x49136008,
+	0x62883940, 0x39C04911, 0x62086248, 0x2201680C, 0x43940412, 0x680C600C,
+	0x01640964, 0x600C3409, 0x4314680C, 0x684C600C, 0x604C4394, 0x0924684C,
+	0x1D240124, 0x684C604C, 0x604C4314, 0x60084905, 0x22016048, 0xE029608A,
+	0x00001250, 0x400140C0, 0x4000F018, 0x40012000, 0x000061A8, 0x00008888,
+	0x00001021, 0x12345678, 0x000100F8, 0x200038F8, 0x200038F0, 0x200038F4,
+	0x200038FC, 0x20002800, 0x4001F000, 0x5724E185, 0x20003000, 0x40010000,
+	0x1ACCE551, 0x40008400, 0x40008000, 0x610A60CA, 0x62CA2203, 0x630A220E,
+	0x63484923, 0x63C86388, 0x4C234922, 0x49236BCA, 0xD10A42A2, 0x22004C1F,
+	0x19153C40, 0x682D1856, 0x60351D12, 0xDDF82A28, 0x2200E007, 0x1D121854,
+	0x2A286020, 0x4A1ADDFA, 0x4A1861CA, 0x32802100, 0x1D09188C, 0x29D46020,
+	0x63D8DDFA, 0x4B152100, 0x25014C15, 0x008A026D, 0x50A05098, 0x42A91C49,
+	0x2000DBF9, 0x4911BD70, 0x60082040, 0x20004910, 0x49106008, 0x60082020,
+	0x480F4910, 0xF7FF6008, 0xF7FFFF5F, 0xF7FFFD91, 0xF7FFFEEA, 0x0000FE39,
+	0x400120C0, 0x000100C0, 0x7455874E, 0x4000F000, 0x00005030, 0x20002800,
+	0x20003000, 0x200038F4, 0x200038F8, 0x200038FC, 0x12345678, 0x200038F0,
+	0x47704770, 0x47704770, 0x46754770, 0xF824F000, 0x000546AE, 0x46534669,
+	0x00C008C0, 0xB0184685, 0xF7FFB520, 0xBC60FD4B, 0x08492700, 0x260046B6,
+	0xC5C0C5C0, 0xC5C0C5C0, 0xC5C0C5C0, 0xC5C0C5C0, 0x00493D40, 0x4770468D,
+	0x4604B510, 0x46C046C0, 0xF7FF4620, 0xBD10FD1E, 0x47704800, 0x20002000,
+	0x20184901, 0xE7FEBEAB, 0x00020026, 0x00004770, 0x20000728, 0x20002000,
+	0x00001D00, 0x20000104
+};
+const size_t boot_hex_len = ARRAY_SIZE(boot_hex);
+BUILD_ASSERT(ARRAY_SIZE(boot_hex) == 458);
diff --git a/driver/wpc/p9221.c b/driver/wpc/p9221.c
deleted file mode 100644
index 5e98737565..0000000000
--- a/driver/wpc/p9221.c
+++ /dev/null
@@ -1,808 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * IDT P9221-R7 Wireless Power Receiver driver.
- */
-
-#include "p9221.h"
-#include "charge_manager.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "power.h"
-#include "tcpm.h"
-#include "timer.h"
-#include "usb_charge.h"
-#include "usb_pd.h"
-#include "util.h"
-#include <stdbool.h>
-#include "printf.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBPD, "WPC " format, ## args)
-
-#define P9221_TX_TIMEOUT_MS		(20 * 1000*1000)
-#define P9221_DCIN_TIMEOUT_MS		(2 * 1000*1000)
-#define P9221_VRECT_TIMEOUT_MS		(2 * 1000*1000)
-#define P9221_NOTIFIER_DELAY_MS		(80*1000)
-#define P9221R7_ILIM_MAX_UA		(1600 * 1000)
-#define P9221R7_OVER_CHECK_NUM		3
-
-#define OVC_LIMIT			1
-#define OVC_THRESHOLD			1400000
-#define OVC_BACKOFF_LIMIT		900000
-#define OVC_BACKOFF_AMOUNT		100000
-
-/* P9221  parameters */
-static struct wpc_charger_info p9221_charger_info = {
-	.online = false,
-	.i2c_port = I2C_PORT_WPC,
-	.pp_buf_valid = false,
-};
-
-static struct wpc_charger_info *wpc = &p9221_charger_info;
-
-static void p9221_set_offline(void);
-
-static const uint32_t p9221_ov_set_lut[] = {
-	17000000, 20000000, 15000000, 13000000,
-	11000000, 11000000, 11000000, 11000000
-};
-
-static int p9221_reg_is_8_bit(uint16_t reg)
-{
-	switch (reg) {
-	case P9221_CHIP_REVISION_REG:
-	case P9221R7_VOUT_SET_REG:
-	case P9221R7_ILIM_SET_REG:
-	case P9221R7_CHARGE_STAT_REG:
-	case P9221R7_EPT_REG:
-	case P9221R7_SYSTEM_MODE_REG:
-	case P9221R7_COM_CHAN_RESET_REG:
-	case P9221R7_COM_CHAN_SEND_SIZE_REG:
-	case P9221R7_COM_CHAN_SEND_IDX_REG:
-	case P9221R7_COM_CHAN_RECV_SIZE_REG:
-	case P9221R7_COM_CHAN_RECV_IDX_REG:
-	case P9221R7_DEBUG_REG:
-	case P9221R7_EPP_Q_FACTOR_REG:
-	case P9221R7_EPP_TX_GUARANTEED_POWER_REG:
-	case P9221R7_EPP_TX_POTENTIAL_POWER_REG:
-	case P9221R7_EPP_TX_CAPABILITY_FLAGS_REG:
-	case P9221R7_EPP_RENEGOTIATION_REG:
-	case P9221R7_EPP_CUR_RPP_HEADER_REG:
-	case P9221R7_EPP_CUR_NEGOTIATED_POWER_REG:
-	case P9221R7_EPP_CUR_MAXIMUM_POWER_REG:
-	case P9221R7_EPP_CUR_FSK_MODULATION_REG:
-	case P9221R7_EPP_REQ_RPP_HEADER_REG:
-	case P9221R7_EPP_REQ_NEGOTIATED_POWER_REG:
-	case P9221R7_EPP_REQ_MAXIMUM_POWER_REG:
-	case P9221R7_EPP_REQ_FSK_MODULATION_REG:
-	case P9221R7_VRECT_TARGET_REG:
-	case P9221R7_VRECT_KNEE_REG:
-	case P9221R7_FOD_SECTION_REG:
-	case P9221R7_VRECT_ADJ_REG:
-	case P9221R7_ALIGN_X_ADC_REG:
-	case P9221R7_ALIGN_Y_ADC_REG:
-	case P9221R7_ASK_MODULATION_DEPTH_REG:
-	case P9221R7_OVSET_REG:
-	case P9221R7_EPP_TX_SPEC_REV_REG:
-		return true;
-	default:
-		return false;
-	}
-}
-
-static int p9221_read8(uint16_t reg, int *val)
-{
-	return i2c_read_offset16(wpc->i2c_port, P9221_R7_ADDR_FLAGS,
-				 reg, val, 1);
-}
-
-static int p9221_write8(uint16_t reg, int val)
-{
-	return i2c_write_offset16(wpc->i2c_port, P9221_R7_ADDR_FLAGS,
-				  reg, val, 1);
-}
-
-static int p9221_read16(uint16_t reg, int *val)
-{
-	return i2c_read_offset16(wpc->i2c_port, P9221_R7_ADDR_FLAGS,
-				 reg, val, 2);
-}
-
-static int p9221_write16(uint16_t reg, int val)
-{
-	return i2c_write_offset16(wpc->i2c_port, P9221_R7_ADDR_FLAGS,
-				  reg, val, 2);
-}
-
-static int p9221_block_read(uint16_t reg, uint8_t *data, int len)
-{
-	return i2c_read_offset16_block(wpc->i2c_port, P9221_R7_ADDR_FLAGS,
-				       reg, data, len);
-}
-
-static int p9221_block_write(uint16_t reg, uint8_t *data, int len)
-{
-	return i2c_write_offset16_block(wpc->i2c_port, P9221_R7_ADDR_FLAGS,
-					reg, data, len);
-}
-
-static int p9221_set_cmd_reg(uint8_t cmd)
-{
-	int cur_cmd;
-	int retry;
-	int ret;
-
-	for (retry = 0; retry < P9221_COM_CHAN_RETRIES; retry++) {
-		ret = p9221_read8(P9221_COM_REG, &cur_cmd);
-		if (ret == EC_SUCCESS && cur_cmd == 0)
-			break;
-		msleep(25);
-	}
-
-	if (retry >= P9221_COM_CHAN_RETRIES) {
-		CPRINTS("Failed to wait for cmd free %02x", cur_cmd);
-		return EC_ERROR_TIMEOUT;
-	}
-
-	ret = p9221_write8(P9221_COM_REG, cmd);
-	if (ret)
-		CPRINTS("Failed to set cmd reg %02x: %d", cmd, ret);
-
-	return ret;
-}
-
-/* Convert a register value to uV, Hz, or uA */
-static int p9221_convert_reg_r7(uint16_t reg, uint16_t raw_data, uint32_t *val)
-{
-	switch (reg) {
-	case P9221R7_ALIGN_X_ADC_REG:	/* raw */
-	case P9221R7_ALIGN_Y_ADC_REG:	/* raw */
-		*val = raw_data;
-		break;
-	case P9221R7_VOUT_ADC_REG:	/* 12-bit ADC raw */
-	case P9221R7_IOUT_ADC_REG:	/* 12-bit ADC raw */
-	case P9221R7_DIE_TEMP_ADC_REG:	/* 12-bit ADC raw */
-	case P9221R7_EXT_TEMP_REG:
-		*val = raw_data & 0xFFF;
-		break;
-	case P9221R7_VOUT_SET_REG:	/* 0.1V -> uV */
-		*val = raw_data * 100 * 1000;
-		break;
-	case P9221R7_IOUT_REG:		/* mA -> uA */
-	case P9221R7_VRECT_REG:		/* mV -> uV */
-	case P9221R7_VOUT_REG:		/* mV -> uV */
-	case P9221R7_OP_FREQ_REG:	/* kHz -> Hz */
-	case P9221R7_TX_PINGFREQ_REG:	/* kHz -> Hz */
-		*val = raw_data * 1000;
-		break;
-	case P9221R7_ILIM_SET_REG:	/* 100mA -> uA, 200mA offset */
-		*val = ((raw_data * 100) + 200) * 1000;
-		break;
-	case P9221R7_OVSET_REG:		/* uV */
-		raw_data &= P9221R7_OVSET_MASK;
-		*val = p9221_ov_set_lut[raw_data];
-		break;
-	default:
-		return -2;
-	}
-
-	return 0;
-}
-
-static int p9221_reg_read_converted(uint16_t reg, uint32_t *val)
-{
-	int ret;
-	int data;
-
-	if (p9221_reg_is_8_bit(reg))
-		ret = p9221_read8(reg, &data);
-	else
-		ret = p9221_read16(reg, &data);
-
-	if (ret)
-		return ret;
-
-	return p9221_convert_reg_r7(reg, data, val);
-}
-
-static int p9221_is_online(void)
-{
-	int chip_id;
-
-	if (p9221_read16(P9221_CHIP_ID_REG, &chip_id)
-			|| chip_id != P9221_CHIP_ID)
-		return false;
-	else
-		return true;
-}
-
-int wpc_chip_is_online(void)
-{
-	return p9221_is_online();
-}
-
-
-void p9221_interrupt(enum gpio_signal signal)
-{
-	task_wake(TASK_ID_WPC);
-}
-
-static int p9221r7_clear_interrupts(uint16_t mask)
-{
-	int ret;
-
-	ret = p9221_write16(P9221R7_INT_CLEAR_REG, mask);
-	if (ret) {
-		CPRINTS("Failed to clear INT reg: %d", ret);
-		return ret;
-	}
-
-	ret = p9221_set_cmd_reg(P9221_COM_CLEAR_INT_MASK);
-	if (ret)
-		CPRINTS("Failed to reset INT: %d", ret);
-
-	return ret;
-}
-
-/*
- * Enable interrupts on the P9221 R7, note we don't really need to disable
- * interrupts since when the device goes out of field, the P9221 is reset.
- */
-static int p9221_enable_interrupts_r7(void)
-{
-	uint16_t mask = 0;
-	int ret;
-
-	CPRINTS("Enable interrupts");
-
-	mask = P9221R7_STAT_LIMIT_MASK | P9221R7_STAT_CC_MASK
-		| P9221_STAT_VRECT;
-
-	p9221r7_clear_interrupts(mask);
-
-	ret = p9221_write8(P9221_INT_ENABLE_REG, mask);
-	if (ret)
-		CPRINTS("Failed to enable INTs: %d", ret);
-	return ret;
-}
-
-static int p9221_send_csp(uint8_t status)
-{
-	int ret;
-
-	CPRINTS("Send CSP=%d", status);
-	mutex_lock(&wpc->cmd_lock);
-
-	ret = p9221_write8(P9221R7_CHARGE_STAT_REG, status);
-	if (ret == EC_SUCCESS)
-		ret = p9221_set_cmd_reg(P9221R7_COM_SENDCSP);
-
-	mutex_unlock(&wpc->cmd_lock);
-	return ret;
-}
-
-static int p9221_send_eop(uint8_t reason)
-{
-	int rv;
-
-	CPRINTS("Send EOP reason=%d", reason);
-	mutex_lock(&wpc->cmd_lock);
-
-	rv = p9221_write8(P9221R7_EPT_REG, reason);
-	if (rv == EC_SUCCESS)
-		rv = p9221_set_cmd_reg(P9221R7_COM_SENDEPT);
-
-	mutex_unlock(&wpc->cmd_lock);
-	return rv;
-}
-
-static void print_current_samples(uint32_t *iout_val, int count)
-{
-	int i;
-	char temp[P9221R7_OVER_CHECK_NUM * 9 + 1] = { 0 };
-
-	for (i = 0; i < count ; i++)
-		snprintf(temp + i * 9, sizeof(temp) - i * 9,
-			  "%08x ", iout_val[i]);
-	CPRINTS("OVER IOUT_SAMPLES: %s", temp);
-}
-
-
-/*
- * Number of times to poll the status to see if the current limit condition
- * was transient or not.
- */
-static void p9221_limit_handler_r7(uint16_t orign_irq_src)
-{
-	uint8_t reason;
-	int i;
-	int ret;
-	int ovc_count = 0;
-	uint32_t iout_val[P9221R7_OVER_CHECK_NUM] = { 0 };
-	int irq_src = (int)orign_irq_src;
-
-	CPRINTS("OVER INT: %02x", irq_src);
-
-	if (irq_src & P9221R7_STAT_OVV) {
-		reason = P9221_EOP_OVER_VOLT;
-		goto send_eop;
-	}
-
-	if (irq_src & P9221R7_STAT_OVT) {
-		reason = P9221_EOP_OVER_TEMP;
-		goto send_eop;
-	}
-
-	if ((irq_src & P9221R7_STAT_UV) && !(irq_src & P9221R7_STAT_OVC))
-		return;
-
-	reason = P9221_EOP_OVER_CURRENT;
-	for (i = 0; i < P9221R7_OVER_CHECK_NUM; i++) {
-		ret = p9221r7_clear_interrupts(
-				irq_src & P9221R7_STAT_LIMIT_MASK);
-		msleep(50);
-		if (ret)
-			continue;
-
-		ret = p9221_reg_read_converted(P9221R7_IOUT_REG, &iout_val[i]);
-		if (ret) {
-			CPRINTS("Failed to read IOUT[%d]: %d", i, ret);
-			continue;
-		} else if (iout_val[i] > OVC_THRESHOLD) {
-			ovc_count++;
-		}
-
-		ret = p9221_read16(P9221_STATUS_REG, &irq_src);
-		if (ret) {
-			CPRINTS("Failed to read status: %d", ret);
-			continue;
-		}
-
-		if ((irq_src & P9221R7_STAT_OVC) == 0) {
-			print_current_samples(iout_val, i + 1);
-			CPRINTS("OVER condition %04x cleared after %d tries",
-				irq_src, i);
-			return;
-		}
-
-		CPRINTS("OVER status is still %04x, retry", irq_src);
-	}
-
-	if (ovc_count < OVC_LIMIT) {
-		print_current_samples(iout_val, P9221R7_OVER_CHECK_NUM);
-		CPRINTS("ovc_threshold=%d, ovc_count=%d, ovc_limit=%d",
-			OVC_THRESHOLD, ovc_count, OVC_LIMIT);
-		return;
-	}
-
-send_eop:
-	CPRINTS("OVER is %04x, sending EOP %d", irq_src, reason);
-
-	ret = p9221_send_eop(reason);
-	if (ret)
-		CPRINTS("Failed to send EOP %d: %d", reason, ret);
-}
-
-static void p9221_abort_transfers(void)
-{
-	wpc->tx_busy = false;
-	wpc->tx_done = true;
-	wpc->rx_done = true;
-	wpc->rx_len = 0;
-}
-
-/* Handler for r7 and R7 chips */
-static void p9221r7_irq_handler(uint16_t irq_src)
-{
-	int res;
-
-	if (irq_src & P9221R7_STAT_LIMIT_MASK)
-		p9221_limit_handler_r7(irq_src);
-
-	/* Receive complete */
-	if (irq_src & P9221R7_STAT_CCDATARCVD) {
-		int rxlen = 0;
-
-		res = p9221_read8(P9221R7_COM_CHAN_RECV_SIZE_REG, &rxlen);
-		if (res)
-			CPRINTS("Failed to read len: %d", res);
-
-		if (rxlen) {
-			res = p9221_block_read(P9221R7_DATA_RECV_BUF_START,
-					       wpc->rx_buf, rxlen);
-			if (res) {
-				CPRINTS("Failed to read CC data: %d", res);
-				rxlen = 0;
-			}
-
-			wpc->rx_len = rxlen;
-			wpc->rx_done = true;
-		}
-	}
-
-	/* Send complete */
-	if (irq_src & P9221R7_STAT_CCSENDBUSY) {
-		wpc->tx_busy = false;
-		wpc->tx_done = true;
-	}
-
-	/* Proprietary packet */
-	if (irq_src & P9221R7_STAT_PPRCVD) {
-		res = p9221_block_read(P9221R7_DATA_RECV_BUF_START,
-				       wpc->pp_buf, sizeof(wpc->pp_buf));
-		if (res) {
-			CPRINTS("Failed to read PP: %d", res);
-			wpc->pp_buf_valid = false;
-			return;
-		}
-
-		/* We only care about PP which come with 0x4F header */
-		wpc->pp_buf_valid = (wpc->pp_buf[0] == 0x4F);
-
-		hexdump(wpc->pp_buf, sizeof(wpc->pp_buf));
-	}
-
-	/* CC Reset complete */
-	if (irq_src & P9221R7_STAT_CCRESET)
-		p9221_abort_transfers();
-}
-
-static int p9221_is_epp(void)
-{
-	int ret, reg;
-	uint32_t vout_uv;
-
-	if (p9221_read8(P9221R7_SYSTEM_MODE_REG, &reg) == EC_SUCCESS)
-		return reg & P9221R7_SYSTEM_MODE_EXTENDED_MASK;
-
-	/* Check based on power supply voltage */
-	ret = p9221_reg_read_converted(P9221R7_VOUT_ADC_REG, &vout_uv);
-	if (ret) {
-		CPRINTS("Failed to read VOUT_ADC: %d", ret);
-		return false;
-	}
-
-	CPRINTS("Voltage is %duV", vout_uv);
-	if (vout_uv > P9221_EPP_THRESHOLD_UV)
-		return true;
-
-	return false;
-}
-
-static void p9221_config_fod(void)
-{
-
-	int epp;
-	uint8_t *fod;
-	int fod_len;
-	int ret;
-	int retries = 3;
-
-	CPRINTS("Config FOD");
-
-	epp = p9221_is_epp();
-	fod_len = epp ? board_get_epp_fod(&fod) : board_get_fod(&fod);
-	if (!fod_len || !fod) {
-		CPRINTS("FOD data not found");
-		return;
-	}
-
-	while (retries) {
-		uint8_t fod_read[fod_len];
-
-		CPRINTS("Writing %s FOD (n=%d try=%d)",
-			epp ? "EPP" : "BPP", fod_len, retries);
-
-		ret = p9221_block_write(P9221R7_FOD_REG, fod, fod_len);
-		if (ret)
-			goto no_fod;
-
-		/* Verify the FOD has been written properly */
-		ret = p9221_block_read(P9221R7_FOD_REG, fod_read, fod_len);
-		if (ret)
-			goto no_fod;
-
-		if (memcmp(fod, fod_read, fod_len) == 0)
-			return;
-
-		hexdump(fod_read, fod_len);
-
-		retries--;
-		msleep(100);
-	}
-
-no_fod:
-	CPRINTS("Failed to set FOD. retries:%d ret:%d", retries, ret);
-}
-
-static void p9221_set_online(void)
-{
-	int ret;
-
-	CPRINTS("Set online");
-
-	wpc->online = true;
-
-	wpc->tx_busy = false;
-	wpc->tx_done = true;
-	wpc->rx_done = false;
-	wpc->charge_supplier = CHARGE_SUPPLIER_WPC_BPP;
-
-	ret = p9221_enable_interrupts_r7();
-	if (ret)
-		CPRINTS("Failed to enable INT: %d", ret);
-
-	/* NOTE: depends on _is_epp() which is not valid until DC_IN */
-	p9221_config_fod();
-}
-
-static void p9221_vbus_check_timeout(void)
-{
-	CPRINTS("Timeout VBUS, online=%d", wpc->online);
-	if (wpc->online)
-		p9221_set_offline();
-
-}
-DECLARE_DEFERRED(p9221_vbus_check_timeout);
-
-static void p9221_set_offline(void)
-{
-	CPRINTS("Set offline");
-
-	wpc->online = false;
-	/* Reset PP buf so we can get a new serial number next time around */
-	wpc->pp_buf_valid = false;
-
-	p9221_abort_transfers();
-
-	hook_call_deferred(&p9221_vbus_check_timeout_data, -1);
-}
-
-/* P9221_NOTIFIER_DELAY_MS from VRECTON */
-static int p9221_notifier_check_det(void)
-{
-	if (wpc->online)
-		goto done;
-
-	/* send out a FOD but is_epp() is still invalid */
-	p9221_set_online();
-
-	/* Give the vbus 2 seconds to come up. */
-	CPRINTS("Waiting VBUS");
-	hook_call_deferred(&p9221_vbus_check_timeout_data, -1);
-	hook_call_deferred(&p9221_vbus_check_timeout_data,
-			   P9221_DCIN_TIMEOUT_MS);
-
-done:
-	wpc->p9221_check_det = false;
-	return 0;
-}
-
-static int p9221_get_charge_supplier(void)
-{
-	if (!wpc->online)
-		return EC_ERROR_UNKNOWN;
-
-	if (p9221_is_epp()) {
-		uint32_t tx_id;
-		int txmf_id;
-		int ret;
-
-		wpc->charge_supplier = CHARGE_SUPPLIER_WPC_EPP;
-
-		ret = p9221_read16(P9221R7_EPP_TX_MFG_CODE_REG, &txmf_id);
-		if (ret || txmf_id != P9221_GPP_TX_MF_ID)
-			return ret;
-
-		ret = p9221_block_read(P9221R7_PROP_TX_ID_REG,
-				       (uint8_t *) &tx_id,
-				       P9221R7_PROP_TX_ID_SIZE);
-		if (ret)
-			return ret;
-
-		if (tx_id & P9221R7_PROP_TX_ID_GPP_MASK)
-			wpc->charge_supplier = CHARGE_SUPPLIER_WPC_GPP;
-
-		CPRINTS("txmf_id=0x%04x tx_id=0x%08x supplier=%d",
-			txmf_id, tx_id, wpc->charge_supplier);
-	} else {
-		wpc->charge_supplier = CHARGE_SUPPLIER_WPC_BPP;
-		CPRINTS("supplier=%d", wpc->charge_supplier);
-	}
-
-	return EC_SUCCESS;
-}
-
-static int p9221_get_icl(int charge_supplier)
-{
-	switch (charge_supplier) {
-	case CHARGE_SUPPLIER_WPC_EPP:
-	case CHARGE_SUPPLIER_WPC_GPP:
-		return P9221_DC_ICL_EPP_MA;
-	case CHARGE_SUPPLIER_WPC_BPP:
-	default:
-		return P9221_DC_ICL_BPP_MA;
-	}
-}
-
-static int p9221_get_ivl(int charge_supplier)
-{
-	switch (charge_supplier) {
-	case CHARGE_SUPPLIER_WPC_EPP:
-	case CHARGE_SUPPLIER_WPC_GPP:
-		return P9221_DC_IVL_EPP_MV;
-	case CHARGE_SUPPLIER_WPC_BPP:
-	default:
-		return P9221_DC_IVL_BPP_MV;
-	}
-}
-
-static void p9221_update_charger(int type, struct charge_port_info *chg)
-{
-	if (!chg)
-		charge_manager_update_dualrole(0, CAP_UNKNOWN);
-	else
-		charge_manager_update_dualrole(0, CAP_DEDICATED);
-
-	charge_manager_update_charge(type, 0, chg);
-}
-
-static int p9221_reg_write_converted_r7(uint16_t reg, uint32_t val)
-{
-	int ret = 0;
-	uint16_t data;
-	int i;
-	/* Do the appropriate conversion */
-	switch (reg) {
-	case P9221R7_ILIM_SET_REG:
-		/* uA -> 0.1A, offset 0.2A */
-		if ((val < 200000) || (val > 1600000))
-			return -EC_ERROR_INVAL;
-		data = (val / (100 * 1000)) - 2;
-		break;
-	case P9221R7_VOUT_SET_REG:
-		/* uV -> 0.1V */
-		val /= 1000;
-		if (val < 3500 || val > 9000)
-			return -EC_ERROR_INVAL;
-		data = val / 100;
-		break;
-	case P9221R7_OVSET_REG:
-		/* uV */
-		for (i = 0; i < ARRAY_SIZE(p9221_ov_set_lut); i++) {
-			if (val == p9221_ov_set_lut[i])
-				break;
-		}
-		if (i == ARRAY_SIZE(p9221_ov_set_lut))
-			return -EC_ERROR_INVAL;
-		data = i;
-		break;
-	default:
-		return -EC_ERROR_INVAL;
-	}
-	if (p9221_reg_is_8_bit(reg))
-		ret = p9221_write8(reg, data);
-	else
-		ret = p9221_write16(reg, data);
-	return ret;
-}
-
-static int p9221_set_dc_icl(void)
-{
-	/* Increase the IOUT limit */
-	if (p9221_reg_write_converted_r7(P9221R7_ILIM_SET_REG,
-					 P9221R7_ILIM_MAX_UA))
-		CPRINTS("%s set rx_iout limit fail.", __func__);
-
-	return EC_SUCCESS;
-}
-
-
-static void p9221_notifier_check_vbus(void)
-{
-	struct charge_port_info chg;
-
-	wpc->p9221_check_vbus = false;
-
-	CPRINTS("%s online:%d vbus:%d", __func__, wpc->online,
-		wpc->vbus_status);
-
-	/*
-	 * We now have confirmation from DC_IN, kill the timer, p9221_online
-	 * will be set by this function.
-	 */
-	hook_call_deferred(&p9221_vbus_check_timeout_data, -1);
-
-	if (wpc->vbus_status) {
-		/* WPC VBUS on ,Always write FOD, check dc_icl, send CSP */
-		p9221_set_dc_icl();
-		p9221_config_fod();
-
-		p9221_send_csp(1);
-
-		/* when wpc vbus attached after 2s, set wpc online */
-		if (!wpc->online)
-			p9221_set_online();
-
-		/* WPC VBUS on , update charge voltage and current */
-		p9221_get_charge_supplier();
-		chg.voltage = p9221_get_ivl(wpc->charge_supplier);
-		chg.current = p9221_get_icl(wpc->charge_supplier);
-
-		p9221_update_charger(wpc->charge_supplier, &chg);
-	} else {
-		/*
-		 * Vbus detached, set wpc offline and update wpc charge voltage
-		 * and current to zero.
-		 */
-		if (wpc->online) {
-			p9221_set_offline();
-			p9221_update_charger(wpc->charge_supplier, NULL);
-		}
-	}
-
-	CPRINTS("check_vbus changed on:%d vbus:%d", wpc->online,
-		wpc->vbus_status);
-
-}
-
-static void p9221_detect_work(void)
-{
-
-	CPRINTS("%s online:%d check_vbus:%d check_det:%d vbus:%d", __func__,
-		wpc->online, wpc->p9221_check_vbus, wpc->p9221_check_det,
-		wpc->vbus_status);
-
-	/* Step 1 */
-	if (wpc->p9221_check_det)
-		p9221_notifier_check_det();
-
-	/* Step 2 */
-	if (wpc->p9221_check_vbus)
-		p9221_notifier_check_vbus();
-
-}
-DECLARE_DEFERRED(p9221_detect_work);
-
-void p9221_notify_vbus_change(int vbus)
-{
-	wpc->p9221_check_vbus = true;
-	wpc->vbus_status = vbus;
-	hook_call_deferred(&p9221_detect_work_data, P9221_NOTIFIER_DELAY_MS);
-}
-
-void wireless_power_charger_task(void *u)
-{
-	while (1) {
-		int ret, irq_src;
-		task_wait_event(-1);
-
-		ret = p9221_read16(P9221_INT_REG, &irq_src);
-		if (ret) {
-			CPRINTS("Failed to read INT REG");
-			continue;
-		}
-
-		CPRINTS("INT SRC 0x%04x", irq_src);
-
-		if (p9221r7_clear_interrupts(irq_src))
-			continue;
-
-		if (irq_src & P9221_STAT_VRECT) {
-			CPRINTS("VRECTON, online=%d", wpc->online);
-			if (!wpc->online) {
-				wpc->p9221_check_det = true;
-				hook_call_deferred(&p9221_detect_work_data,
-						   P9221_NOTIFIER_DELAY_MS);
-			}
-		}
-
-		p9221r7_irq_handler(irq_src);
-	}
-}
diff --git a/driver/wpc/p9221.h b/driver/wpc/p9221.h
index 0bb0571b38..1360c54ee7 100644
--- a/driver/wpc/p9221.h
+++ b/driver/wpc/p9221.h
@@ -1,9 +1,8 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-
 /*
  * IDT P9221-R7 Wireless Power Receiver driver definitions.
  */
@@ -11,253 +10,248 @@
 #ifndef __P9221_R7_H
 #define __P9221_R7_H
 
+#include "charge_manager.h"
 #include "common.h"
 #include "gpio.h"
-#include "charge_manager.h"
 #include "task.h"
 
-
 /* ========== Variant-specific configuration ============ */
 
-#define P9221_R7_ADDR_FLAGS			0x61
+#define P9221_R7_ADDR_FLAGS 0x61
 
 /*
  * P9221 common registers
  */
-#define P9221_CHIP_ID_REG			0x00
-#define P9221_CHIP_ID				0x9220
-#define P9221_CHIP_REVISION_REG			0x02
-#define P9221_CUSTOMER_ID_REG			0x03
-#define P9221R7_CUSTOMER_ID_VAL			0x05
-#define P9221_OTP_FW_MAJOR_REV_REG		0x04
-#define P9221_OTP_FW_MINOR_REV_REG		0x06
-#define P9221_OTP_FW_DATE_REG			0x08
-#define P9221_OTP_FW_DATE_SIZE			12
-#define P9221_OTP_FW_TIME_REG			0x14
-#define P9221_OTP_FW_TIME_SIZE			8
-#define P9221_SRAM_FW_MAJOR_REV_REG		0x1C
-#define P9221_SRAM_FW_MINOR_REV_REG		0x1E
-#define P9221_SRAM_FW_DATE_REG			0x20
-#define P9221_SRAM_FW_DATE_SIZE			12
-#define P9221_SRAM_FW_TIME_REG			0x2C
-#define P9221_SRAM_FW_TIME_SIZE			8
-#define P9221_STATUS_REG			0x34
-#define P9221_INT_REG				0x36
-#define P9221_INT_MASK				0xF7
-#define P9221_INT_ENABLE_REG			0x38
-#define P9221_GPP_TX_MF_ID			0x0072
+#define P9221_CHIP_ID_REG 0x00
+#define P9221_CHIP_ID 0x9220
+#define P9221_CHIP_REVISION_REG 0x02
+#define P9221_CUSTOMER_ID_REG 0x03
+#define P9221R7_CUSTOMER_ID_VAL 0x05
+#define P9221_OTP_FW_MAJOR_REV_REG 0x04
+#define P9221_OTP_FW_MINOR_REV_REG 0x06
+#define P9221_OTP_FW_DATE_REG 0x08
+#define P9221_OTP_FW_DATE_SIZE 12
+#define P9221_OTP_FW_TIME_REG 0x14
+#define P9221_OTP_FW_TIME_SIZE 8
+#define P9221_SRAM_FW_MAJOR_REV_REG 0x1C
+#define P9221_SRAM_FW_MINOR_REV_REG 0x1E
+#define P9221_SRAM_FW_DATE_REG 0x20
+#define P9221_SRAM_FW_DATE_SIZE 12
+#define P9221_SRAM_FW_TIME_REG 0x2C
+#define P9221_SRAM_FW_TIME_SIZE 8
+#define P9221_STATUS_REG 0x34
+#define P9221_INT_REG 0x36
+#define P9221_INT_MASK 0xF7
+#define P9221_INT_ENABLE_REG 0x38
+#define P9221_GPP_TX_MF_ID 0x0072
 
 /*
  * P9221 Rx registers (x != 5)
  */
-#define P9221_CHARGE_STAT_REG			0x3A
-#define P9221_EPT_REG				0x3B
-#define P9221_VOUT_ADC_REG			0x3C
-#define P9221_VOUT_ADC_MASK			0x0FFF
-#define P9221_VOUT_SET_REG			0x3E
-#define P9221_MAX_VOUT_SET_MV_DEFAULT		9000
-#define P9221_VRECT_ADC_REG			0x40
-#define P9221_VRECT_ADC_MASK			0x0FFF
-#define P9221_OVSET_REG				0x42
-#define P9221_OVSET_MASK			0x70
-#define P9221_OVSET_SHIFT			4
-#define P9221_RX_IOUT_REG			0x44
-#define P9221_DIE_TEMP_ADC_REG			0x46
-#define P9221_DIE_TEMP_ADC_MASK			0x0FFF
-#define P9221_OP_FREQ_REG			0x48
-#define P9221_ILIM_SET_REG			0x4A
-#define P9221_ALIGN_X_ADC_REG			0x4B
-#define P9221_ALIGN_Y_ADC_REG			0x4C
-#define P9221_OP_MODE_REG			0x4D
-#define P9221_COM_REG				0x4E
-#define P9221_FW_SWITCH_KEY_REG			0x4F
-#define P9221_INT_CLEAR_REG			0x56
-#define P9221_RXID_REG				0x5C
-#define P9221_RXID_LEN				6
-#define P9221_MPREQ_REG				0x5C
-#define P9221_MPREQ_LEN				6
-#define P9221_FOD_REG				0x68
-#define P9221_NUM_FOD				16
-#define P9221_RX_RAWIOUT_REG			0x7A
-#define P9221_RX_RAWIOUT_MASK			0xFFF
-#define P9221_PMA_AD_REG			0x7C
-#define P9221_RX_PINGFREQ_REG			0xFC
-#define P9221_RX_PINGFREQ_MASK			0xFFF
-#define P9221_LAST_REG				0xFF
+#define P9221_CHARGE_STAT_REG 0x3A
+#define P9221_EPT_REG 0x3B
+#define P9221_VOUT_ADC_REG 0x3C
+#define P9221_VOUT_ADC_MASK 0x0FFF
+#define P9221_VOUT_SET_REG 0x3E
+#define P9221_MAX_VOUT_SET_MV_DEFAULT 9000
+#define P9221_VRECT_ADC_REG 0x40
+#define P9221_VRECT_ADC_MASK 0x0FFF
+#define P9221_OVSET_REG 0x42
+#define P9221_OVSET_MASK 0x70
+#define P9221_OVSET_SHIFT 4
+#define P9221_RX_IOUT_REG 0x44
+#define P9221_DIE_TEMP_ADC_REG 0x46
+#define P9221_DIE_TEMP_ADC_MASK 0x0FFF
+#define P9221_OP_FREQ_REG 0x48
+#define P9221_ILIM_SET_REG 0x4A
+#define P9221_ALIGN_X_ADC_REG 0x4B
+#define P9221_ALIGN_Y_ADC_REG 0x4C
+#define P9221_OP_MODE_REG 0x4D
+#define P9221_COM_REG 0x4E
+#define P9221_FW_SWITCH_KEY_REG 0x4F
+#define P9221_INT_CLEAR_REG 0x56
+#define P9221_RXID_REG 0x5C
+#define P9221_RXID_LEN 6
+#define P9221_MPREQ_REG 0x5C
+#define P9221_MPREQ_LEN 6
+#define P9221_FOD_REG 0x68
+#define P9221_NUM_FOD 16
+#define P9221_RX_RAWIOUT_REG 0x7A
+#define P9221_RX_RAWIOUT_MASK 0xFFF
+#define P9221_PMA_AD_REG 0x7C
+#define P9221_RX_PINGFREQ_REG 0xFC
+#define P9221_RX_PINGFREQ_MASK 0xFFF
+#define P9221_LAST_REG 0xFF
 
 /*
  * P9221R7 unique registers
  */
-#define P9221R7_INT_CLEAR_REG			0x3A
-#define P9221R7_VOUT_SET_REG			0x3C
-#define P9221R7_ILIM_SET_REG			0x3D
-#define P9221R7_ILIM_SET_MAX			0x0E	/* 0x0E = 1.6A */
-#define P9221R7_CHARGE_STAT_REG			0x3E
-#define P9221R7_EPT_REG				0x3F
-#define P9221R7_VRECT_REG			0x40
-#define P9221R7_VOUT_REG			0x42
-#define P9221R7_IOUT_REG			0x44
-#define P9221R7_OP_FREQ_REG			0x48
-#define P9221R7_SYSTEM_MODE_REG			0x4C
-#define P9221R7_COM_CHAN_RESET_REG		0x50
-#define P9221R7_COM_CHAN_SEND_SIZE_REG		0x58
-#define P9221R7_COM_CHAN_SEND_IDX_REG		0x59
-#define P9221R7_COM_CHAN_RECV_SIZE_REG		0x5A
-#define P9221R7_COM_CHAN_RECV_IDX_REG		0x5B
-#define P9221R7_VRECT_ADC_REG			0x60
-#define P9221R7_VOUT_ADC_REG			0x62
-#define P9221R7_VOUT_ADC_MASK			0xFFF
-#define P9221R7_IOUT_ADC_REG			0x64
-#define P9221R7_IOUT_ADC_MASK			0xFFF
-#define P9221R7_DIE_TEMP_ADC_REG		0x66
-#define P9221R7_DIE_TEMP_ADC_MASK		0xFFF
-#define P9221R7_AC_PERIOD_REG			0x68
-#define P9221R7_TX_PINGFREQ_REG			0x6A
-#define P9221R7_EXT_TEMP_REG			0x6C
-#define P9221R7_EXT_TEMP_MASK			0xFFF
-#define P9221R7_FOD_REG				0x70
-#define P9221R7_NUM_FOD				16
-#define P9221R7_DEBUG_REG			0x80
-#define P9221R7_EPP_Q_FACTOR_REG		0x83
-#define P9221R7_EPP_TX_GUARANTEED_POWER_REG	0x84
-#define P9221R7_EPP_TX_POTENTIAL_POWER_REG	0x85
-#define P9221R7_EPP_TX_CAPABILITY_FLAGS_REG	0x86
-#define P9221R7_EPP_RENEGOTIATION_REG		0x87
-#define P9221R7_EPP_CUR_RPP_HEADER_REG		0x88
-#define P9221R7_EPP_CUR_NEGOTIATED_POWER_REG	0x89
-#define P9221R7_EPP_CUR_MAXIMUM_POWER_REG	0x8A
-#define P9221R7_EPP_CUR_FSK_MODULATION_REG	0x8B
-#define P9221R7_EPP_REQ_RPP_HEADER_REG		0x8C
-#define P9221R7_EPP_REQ_NEGOTIATED_POWER_REG	0x8D
-#define P9221R7_EPP_REQ_MAXIMUM_POWER_REG	0x8E
-#define P9221R7_EPP_REQ_FSK_MODULATION_REG	0x8F
-#define P9221R7_VRECT_TARGET_REG		0x90
-#define P9221R7_VRECT_KNEE_REG			0x92
-#define P9221R7_VRECT_CORRECTION_FACTOR_REG	0x93
-#define P9221R7_VRECT_MAX_CORRECTION_FACTOR_REG	0x94
-#define P9221R7_VRECT_MIN_CORRECTION_FACTOR_REG	0x96
-#define P9221R7_FOD_SECTION_REG			0x99
-#define P9221R7_VRECT_ADJ_REG			0x9E
-#define P9221R7_ALIGN_X_ADC_REG			0xA0
-#define P9221R7_ALIGN_Y_ADC_REG			0xA1
-#define P9221R7_ASK_MODULATION_DEPTH_REG	0xA2
-#define P9221R7_OVSET_REG			0xA3
-#define P9221R7_OVSET_MASK			0x7
-#define P9221R7_EPP_TX_SPEC_REV_REG		0xA9
-#define P9221R7_EPP_TX_MFG_CODE_REG		0xAA
-#define P9221R7_GP0_RESET_VOLT_REG		0xAC
-#define P9221R7_GP1_RESET_VOLT_REG		0xAE
-#define P9221R7_GP2_RESET_VOLT_REG		0xB0
-#define P9221R7_GP3_RESET_VOLT_REG		0xB2
-#define P9221R7_PROP_TX_ID_REG			0xB4
-#define P9221R7_PROP_TX_ID_SIZE			4
-#define P9221R7_DATA_SEND_BUF_START		0x100
-#define P9221R7_DATA_SEND_BUF_SIZE		0x80
-#define P9221R7_DATA_RECV_BUF_START		0x180
-#define P9221R7_DATA_RECV_BUF_SIZE		0x80
-#define P9221R7_MAX_PP_BUF_SIZE			16
-#define P9221R7_LAST_REG			0x1FF
+#define P9221R7_INT_CLEAR_REG 0x3A
+#define P9221R7_VOUT_SET_REG 0x3C
+#define P9221R7_ILIM_SET_REG 0x3D
+#define P9221R7_ILIM_SET_MAX 0x0E /* 0x0E = 1.6A */
+#define P9221R7_CHARGE_STAT_REG 0x3E
+#define P9221R7_EPT_REG 0x3F
+#define P9221R7_VRECT_REG 0x40
+#define P9221R7_VOUT_REG 0x42
+#define P9221R7_IOUT_REG 0x44
+#define P9221R7_OP_FREQ_REG 0x48
+#define P9221R7_SYSTEM_MODE_REG 0x4C
+#define P9221R7_COM_CHAN_RESET_REG 0x50
+#define P9221R7_COM_CHAN_SEND_SIZE_REG 0x58
+#define P9221R7_COM_CHAN_SEND_IDX_REG 0x59
+#define P9221R7_COM_CHAN_RECV_SIZE_REG 0x5A
+#define P9221R7_COM_CHAN_RECV_IDX_REG 0x5B
+#define P9221R7_VRECT_ADC_REG 0x60
+#define P9221R7_VOUT_ADC_REG 0x62
+#define P9221R7_VOUT_ADC_MASK 0xFFF
+#define P9221R7_IOUT_ADC_REG 0x64
+#define P9221R7_IOUT_ADC_MASK 0xFFF
+#define P9221R7_DIE_TEMP_ADC_REG 0x66
+#define P9221R7_DIE_TEMP_ADC_MASK 0xFFF
+#define P9221R7_AC_PERIOD_REG 0x68
+#define P9221R7_TX_PINGFREQ_REG 0x6A
+#define P9221R7_EXT_TEMP_REG 0x6C
+#define P9221R7_EXT_TEMP_MASK 0xFFF
+#define P9221R7_FOD_REG 0x70
+#define P9221R7_NUM_FOD 16
+#define P9221R7_DEBUG_REG 0x80
+#define P9221R7_EPP_Q_FACTOR_REG 0x83
+#define P9221R7_EPP_TX_GUARANTEED_POWER_REG 0x84
+#define P9221R7_EPP_TX_POTENTIAL_POWER_REG 0x85
+#define P9221R7_EPP_TX_CAPABILITY_FLAGS_REG 0x86
+#define P9221R7_EPP_RENEGOTIATION_REG 0x87
+#define P9221R7_EPP_CUR_RPP_HEADER_REG 0x88
+#define P9221R7_EPP_CUR_NEGOTIATED_POWER_REG 0x89
+#define P9221R7_EPP_CUR_MAXIMUM_POWER_REG 0x8A
+#define P9221R7_EPP_CUR_FSK_MODULATION_REG 0x8B
+#define P9221R7_EPP_REQ_RPP_HEADER_REG 0x8C
+#define P9221R7_EPP_REQ_NEGOTIATED_POWER_REG 0x8D
+#define P9221R7_EPP_REQ_MAXIMUM_POWER_REG 0x8E
+#define P9221R7_EPP_REQ_FSK_MODULATION_REG 0x8F
+#define P9221R7_VRECT_TARGET_REG 0x90
+#define P9221R7_VRECT_KNEE_REG 0x92
+#define P9221R7_VRECT_CORRECTION_FACTOR_REG 0x93
+#define P9221R7_VRECT_MAX_CORRECTION_FACTOR_REG 0x94
+#define P9221R7_VRECT_MIN_CORRECTION_FACTOR_REG 0x96
+#define P9221R7_FOD_SECTION_REG 0x99
+#define P9221R7_VRECT_ADJ_REG 0x9E
+#define P9221R7_ALIGN_X_ADC_REG 0xA0
+#define P9221R7_ALIGN_Y_ADC_REG 0xA1
+#define P9221R7_ASK_MODULATION_DEPTH_REG 0xA2
+#define P9221R7_OVSET_REG 0xA3
+#define P9221R7_OVSET_MASK 0x7
+#define P9221R7_EPP_TX_SPEC_REV_REG 0xA9
+#define P9221R7_EPP_TX_MFG_CODE_REG 0xAA
+#define P9221R7_GP0_RESET_VOLT_REG 0xAC
+#define P9221R7_GP1_RESET_VOLT_REG 0xAE
+#define P9221R7_GP2_RESET_VOLT_REG 0xB0
+#define P9221R7_GP3_RESET_VOLT_REG 0xB2
+#define P9221R7_PROP_TX_ID_REG 0xB4
+#define P9221R7_PROP_TX_ID_SIZE 4
+#define P9221R7_DATA_SEND_BUF_START 0x100
+#define P9221R7_DATA_SEND_BUF_SIZE 0x80
+#define P9221R7_DATA_RECV_BUF_START 0x180
+#define P9221R7_DATA_RECV_BUF_SIZE 0x80
+#define P9221R7_MAX_PP_BUF_SIZE 16
+#define P9221R7_LAST_REG 0x1FF
 
 /*
  * System Mode Mask (r7+/0x4C)
  */
-#define P9221R7_SYSTEM_MODE_EXTENDED_MASK	(1 << 3)
+#define P9221R7_SYSTEM_MODE_EXTENDED_MASK (1 << 3)
 
 /*
  * TX ID GPP Mask (r7+/0xB4->0xB7)
  */
-#define P9221R7_PROP_TX_ID_GPP_MASK		(1 << 29)
+#define P9221R7_PROP_TX_ID_GPP_MASK (1 << 29)
 
 /*
  * Com Channel Commands
  */
-#define P9221R7_COM_CHAN_CCRESET		BIT(7)
-#define P9221_COM_CHAN_RETRIES			5
+#define P9221R7_COM_CHAN_CCRESET BIT(7)
+#define P9221_COM_CHAN_RETRIES 5
 
 /*
  * End of Power packet types
  */
-#define P9221_EOP_UNKNOWN			0x00
-#define P9221_EOP_EOC				0x01
-#define P9221_EOP_INTERNAL_FAULT		0x02
-#define P9221_EOP_OVER_TEMP			0x03
-#define P9221_EOP_OVER_VOLT			0x04
-#define P9221_EOP_OVER_CURRENT			0x05
-#define P9221_EOP_BATT_FAIL			0x06
-#define P9221_EOP_RECONFIG			0x07
-#define P9221_EOP_NO_RESPONSE			0x08
-#define P9221_EOP_NEGOTIATION_FAIL		0x0A
-#define P9221_EOP_RESTART_POWER			0x0B
+#define P9221_EOP_UNKNOWN 0x00
+#define P9221_EOP_EOC 0x01
+#define P9221_EOP_INTERNAL_FAULT 0x02
+#define P9221_EOP_OVER_TEMP 0x03
+#define P9221_EOP_OVER_VOLT 0x04
+#define P9221_EOP_OVER_CURRENT 0x05
+#define P9221_EOP_BATT_FAIL 0x06
+#define P9221_EOP_RECONFIG 0x07
+#define P9221_EOP_NO_RESPONSE 0x08
+#define P9221_EOP_NEGOTIATION_FAIL 0x0A
+#define P9221_EOP_RESTART_POWER 0x0B
 
 /*
  * Command flags
  */
-#define P9221R7_COM_RENEGOTIATE			P9221_COM_RENEGOTIATE
-#define P9221R7_COM_SWITCH2RAM			P9221_COM_SWITCH_TO_RAM_MASK
-#define P9221R7_COM_CLRINT			P9221_COM_CLEAR_INT_MASK
-#define P9221R7_COM_SENDCSP			P9221_COM_SEND_CHG_STAT_MASK
-#define P9221R7_COM_SENDEPT			P9221_COM_SEND_EOP_MASK
-#define P9221R7_COM_LDOTGL			P9221_COM_LDO_TOGGLE
-#define P9221R7_COM_CCACTIVATE			BIT(0)
+#define P9221R7_COM_RENEGOTIATE P9221_COM_RENEGOTIATE
+#define P9221R7_COM_SWITCH2RAM P9221_COM_SWITCH_TO_RAM_MASK
+#define P9221R7_COM_CLRINT P9221_COM_CLEAR_INT_MASK
+#define P9221R7_COM_SENDCSP P9221_COM_SEND_CHG_STAT_MASK
+#define P9221R7_COM_SENDEPT P9221_COM_SEND_EOP_MASK
+#define P9221R7_COM_LDOTGL P9221_COM_LDO_TOGGLE
+#define P9221R7_COM_CCACTIVATE BIT(0)
 
-#define P9221_COM_RENEGOTIATE			BIT(7)
-#define P9221_COM_SWITCH_TO_RAM_MASK		BIT(6)
-#define P9221_COM_CLEAR_INT_MASK		BIT(5)
-#define P9221_COM_SEND_CHG_STAT_MASK		BIT(4)
-#define P9221_COM_SEND_EOP_MASK			BIT(3)
-#define P9221_COM_LDO_TOGGLE			BIT(1)
+#define P9221_COM_RENEGOTIATE BIT(7)
+#define P9221_COM_SWITCH_TO_RAM_MASK BIT(6)
+#define P9221_COM_CLEAR_INT_MASK BIT(5)
+#define P9221_COM_SEND_CHG_STAT_MASK BIT(4)
+#define P9221_COM_SEND_EOP_MASK BIT(3)
+#define P9221_COM_LDO_TOGGLE BIT(1)
 
 /*
  * Interrupt/Status flags for P9221
  */
-#define P9221_STAT_VOUT				BIT(7)
-#define P9221_STAT_VRECT			BIT(6)
-#define P9221_STAT_ACMISSING			BIT(5)
-#define P9221_STAT_OV_TEMP			BIT(2)
-#define P9221_STAT_OV_VOLT			BIT(1)
-#define P9221_STAT_OV_CURRENT			BIT(0)
-#define P9221_STAT_LIMIT_MASK			(P9221_STAT_OV_TEMP | \
-						 P9221_STAT_OV_VOLT | \
-						 P9221_STAT_OV_CURRENT)
+#define P9221_STAT_VOUT BIT(7)
+#define P9221_STAT_VRECT BIT(6)
+#define P9221_STAT_ACMISSING BIT(5)
+#define P9221_STAT_OV_TEMP BIT(2)
+#define P9221_STAT_OV_VOLT BIT(1)
+#define P9221_STAT_OV_CURRENT BIT(0)
+#define P9221_STAT_LIMIT_MASK \
+	(P9221_STAT_OV_TEMP | P9221_STAT_OV_VOLT | P9221_STAT_OV_CURRENT)
 /*
  * Interrupt/Status flags for P9221R7
  */
-#define P9221R7_STAT_CCRESET			BIT(12)
-#define P9221R7_STAT_CCERROR			BIT(11)
-#define P9221R7_STAT_PPRCVD			BIT(10)
-#define P9221R7_STAT_CCDATARCVD			BIT(9)
-#define P9221R7_STAT_CCSENDBUSY			BIT(8)
-#define P9221R7_STAT_VOUTCHANGED		BIT(7)
-#define P9221R7_STAT_VRECTON			BIT(6)
-#define P9221R7_STAT_MODECHANGED		BIT(5)
-#define P9221R7_STAT_UV				BIT(3)
-#define P9221R7_STAT_OVT			BIT(2)
-#define P9221R7_STAT_OVV			BIT(1)
-#define P9221R7_STAT_OVC			BIT(0)
-#define P9221R7_STAT_MASK			0x1FFF
-#define P9221R7_STAT_CC_MASK			(P9221R7_STAT_CCRESET | \
-						 P9221R7_STAT_PPRCVD | \
-						 P9221R7_STAT_CCERROR | \
-						 P9221R7_STAT_CCDATARCVD | \
-						 P9221R7_STAT_CCSENDBUSY)
-#define P9221R7_STAT_LIMIT_MASK			(P9221R7_STAT_UV | \
-						 P9221R7_STAT_OVV | \
-						 P9221R7_STAT_OVT | \
-						 P9221R7_STAT_OVC)
+#define P9221R7_STAT_CCRESET BIT(12)
+#define P9221R7_STAT_CCERROR BIT(11)
+#define P9221R7_STAT_PPRCVD BIT(10)
+#define P9221R7_STAT_CCDATARCVD BIT(9)
+#define P9221R7_STAT_CCSENDBUSY BIT(8)
+#define P9221R7_STAT_VOUTCHANGED BIT(7)
+#define P9221R7_STAT_VRECTON BIT(6)
+#define P9221R7_STAT_MODECHANGED BIT(5)
+#define P9221R7_STAT_UV BIT(3)
+#define P9221R7_STAT_OVT BIT(2)
+#define P9221R7_STAT_OVV BIT(1)
+#define P9221R7_STAT_OVC BIT(0)
+#define P9221R7_STAT_MASK 0x1FFF
+#define P9221R7_STAT_CC_MASK                                                 \
+	(P9221R7_STAT_CCRESET | P9221R7_STAT_PPRCVD | P9221R7_STAT_CCERROR | \
+	 P9221R7_STAT_CCDATARCVD | P9221R7_STAT_CCSENDBUSY)
+#define P9221R7_STAT_LIMIT_MASK                                  \
+	(P9221R7_STAT_UV | P9221R7_STAT_OVV | P9221R7_STAT_OVT | \
+	 P9221R7_STAT_OVC)
 
-#define P9221_DC_ICL_BPP_MA			1000
-#define P9221_DC_ICL_EPP_MA			1100
-#define P9221_DC_IVL_BPP_MV			5000
-#define P9221_DC_IVL_EPP_MV			9000
-#define P9221_EPP_THRESHOLD_UV			7000000
+#define P9221_DC_ICL_BPP_MA 1000
+#define P9221_DC_ICL_EPP_MA 1100
+#define P9221_DC_IVL_BPP_MV 5000
+#define P9221_DC_IVL_EPP_MV 9000
+#define P9221_EPP_THRESHOLD_UV 7000000
 
-#define true    1
-#define false   0
+#define true 1
+#define false 0
 
 struct wpc_charger_info {
-	uint8_t online;				 /* wpc is online */
-	uint8_t cust_id;			 /* customer id */
-	uint8_t i2c_port;			 /* i2c port */
+	uint8_t online; /* wpc is online */
+	uint8_t cust_id; /* customer id */
+	uint8_t i2c_port; /* i2c port */
 	/* Proprietary Packets receive buffer, to get Proprietary data from TX*/
 	uint8_t pp_buf[P9221R7_MAX_PP_BUF_SIZE];
 	uint8_t pp_buf_valid;
@@ -267,8 +261,8 @@ struct wpc_charger_info {
 	uint8_t rx_done;
 	/* Message packets send buffer, used when send messages from RX to TX*/
 	uint8_t tx_buf[P9221R7_DATA_SEND_BUF_SIZE];
-	uint8_t tx_id;				/* TX device id */
-	uint8_t tx_len;	 /* The data size need send to TX */
+	uint8_t tx_id; /* TX device id */
+	uint8_t tx_len; /* The data size need send to TX */
 	uint8_t tx_done; /* TX data send has done */
 	uint8_t tx_busy; /* when tx_busy=1, can't transfer data from RX to TX */
 	/* p9221_check_vbus=1 when VBUS has changed, need update charge state */
diff --git a/extra/cr50_rma_open/cr50_rma_open.py b/extra/cr50_rma_open/cr50_rma_open.py
index 42ddbbac2d..14cd26134f 100755
--- a/extra/cr50_rma_open/cr50_rma_open.py
+++ b/extra/cr50_rma_open/cr50_rma_open.py
@@ -1,6 +1,6 @@
 #!/usr/bin/env python3
 # -*- coding: utf-8 -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -50,23 +50,23 @@
 import sys
 import time
 
-import serial
+import serial  # pylint:disable=import-error
+
 
 SCRIPT_VERSION = 5
 CCD_IS_UNRESTRICTED = 1 << 0
 WP_IS_DISABLED = 1 << 1
 TESTLAB_IS_ENABLED = 1 << 2
 RMA_OPENED = CCD_IS_UNRESTRICTED | WP_IS_DISABLED
-URL = ('https://www.google.com/chromeos/partner/console/cr50reset?'
-       'challenge=%s&hwid=%s')
-RMA_SUPPORT_PROD = '0.3.3'
-RMA_SUPPORT_PREPVT = '0.4.5'
-DEV_MODE_OPEN_PROD = '0.3.9'
-DEV_MODE_OPEN_PREPVT = '0.4.7'
-TESTLAB_PROD = '0.3.10'
-CR50_USB = '18d1:5014'
-CR50_LSUSB_CMD = ['lsusb', '-vd', CR50_USB]
-ERASED_BID = 'ffffffff'
+URL = "https://www.google.com/chromeos/partner/console/cr50reset?challenge=%s&hwid=%s"
+RMA_SUPPORT_PROD = "0.3.3"
+RMA_SUPPORT_PREPVT = "0.4.5"
+DEV_MODE_OPEN_PROD = "0.3.9"
+DEV_MODE_OPEN_PREPVT = "0.4.7"
+TESTLAB_PROD = "0.3.10"
+CR50_USB = "18d1:5014"
+CR50_LSUSB_CMD = ["lsusb", "-vd", CR50_USB]
+ERASED_BID = "ffffffff"
 
 DEBUG_MISSING_USB = """
 Unable to find Cr50 Device 18d1:5014
@@ -128,13 +128,14 @@
 Run from chroot if you are trying to use a /dev/pts ccd servo console
 """
 
+
 class RMAOpen(object):
     """Used to find the cr50 console and run RMA open"""
 
-    ENABLE_TESTLAB_CMD = 'ccd testlab enabled\n'
+    ENABLE_TESTLAB_CMD = "ccd testlab enabled\n"
 
     def __init__(self, device=None, usb_serial=None, servo_port=None, ip=None):
-        self.servo_port = servo_port if servo_port else '9999'
+        self.servo_port = servo_port if servo_port else "9999"
         self.ip = ip
         if device:
             self.set_cr50_device(device)
@@ -142,18 +143,18 @@ def __init__(self, device=None, usb_serial=None, servo_port=None, ip=None):
             self.find_cr50_servo_uart()
         else:
             self.find_cr50_device(usb_serial)
-        logging.info('DEVICE: %s', self.device)
+        logging.info("DEVICE: %s", self.device)
         self.check_version()
         self.print_platform_info()
-        logging.info('Cr50 setup ok')
+        logging.info("Cr50 setup ok")
         self.update_ccd_state()
         self.using_ccd = self.device_is_running_with_servo_ccd()
 
     def _dut_control(self, control):
         """Run dut-control and return the response"""
         try:
-            cmd = ['dut-control', '-p', self.servo_port, control]
-            return subprocess.check_output(cmd, encoding='utf-8').strip()
+            cmd = ["dut-control", "-p", self.servo_port, control]
+            return subprocess.check_output(cmd, encoding="utf-8").strip()
         except OSError:
             logging.warning(DEBUG_DUT_CONTROL_OSERROR)
             raise
@@ -163,8 +164,8 @@ def find_cr50_servo_uart(self):
 
         Find the console and configure it, so it can be used with this script.
         """
-        self._dut_control('cr50_uart_timestamp:off')
-        self.device = self._dut_control('cr50_uart_pty').split(':')[-1]
+        self._dut_control("cr50_uart_timestamp:off")
+        self.device = self._dut_control("cr50_uart_pty").split(":")[-1]
 
     def set_cr50_device(self, device):
         """Save the device used for the console"""
@@ -183,38 +184,38 @@ def send_cmd_get_output(self, cmd, nbytes=0):
         try:
             ser = serial.Serial(self.device, timeout=1)
         except OSError:
-            logging.warning('Permission denied %s', self.device)
-            logging.warning('Try running cr50_rma_open with sudo')
+            logging.warning("Permission denied %s", self.device)
+            logging.warning("Try running cr50_rma_open with sudo")
             raise
-        write_cmd = cmd + '\n\n'
-        ser.write(write_cmd.encode('utf-8'))
+        write_cmd = cmd + "\n\n"
+        ser.write(write_cmd.encode("utf-8"))
         if nbytes:
             output = ser.read(nbytes)
         else:
             output = ser.readall()
         ser.close()
 
-        output = output.decode('utf-8').strip() if output else ''
+        output = output.decode("utf-8").strip() if output else ""
         # Return only the command output
-        split_cmd = cmd + '\r'
+        split_cmd = cmd + "\r"
         if cmd and split_cmd in output:
-            return ''.join(output.rpartition(split_cmd)[1::]).split('>')[0]
+            return "".join(output.rpartition(split_cmd)[1::]).split(">")[0]
         return output
 
     def device_is_running_with_servo_ccd(self):
         """Return True if the device is a servod ccd console"""
         # servod uses /dev/pts consoles. Non-servod uses /dev/ttyUSBX
-        if '/dev/pts' not in self.device:
+        if "/dev/pts" not in self.device:
             return False
         # If cr50 doesn't show rdd is connected, cr50 the device must not be
         # a ccd device
-        if 'Rdd:     connected' not in self.send_cmd_get_output('ccdstate'):
+        if "Rdd:     connected" not in self.send_cmd_get_output("ccdstate"):
             return False
         # Check if the servod is running with ccd. This requires the script
         # is run in the chroot, so run it last.
-        if 'ccd_cr50' not in self._dut_control('servo_type'):
+        if "ccd_cr50" not in self._dut_control("servo_type"):
             return False
-        logging.info('running through servod ccd')
+        logging.info("running through servod ccd")
         return True
 
     def get_rma_challenge(self):
@@ -239,14 +240,14 @@ def get_rma_challenge(self):
         Returns:
             The RMA challenge with all whitespace removed.
         """
-        output = self.send_cmd_get_output('rma_auth').strip()
-        logging.info('rma_auth output:\n%s', output)
+        output = self.send_cmd_get_output("rma_auth").strip()
+        logging.info("rma_auth output:\n%s", output)
         # Extract the challenge from the console output
-        if 'generated challenge:' in output:
-            return output.split('generated challenge:')[-1].strip()
-        challenge = ''.join(re.findall(r' \S{5}' * 4, output))
+        if "generated challenge:" in output:
+            return output.split("generated challenge:")[-1].strip()
+        challenge = "".join(re.findall(r" \S{5}" * 4, output))
         # Remove all whitespace
-        return re.sub(r'\s', '', challenge)
+        return re.sub(r"\s", "", challenge)
 
     def generate_challenge_url(self, hwid):
         """Get the rma_auth challenge
@@ -257,12 +258,14 @@ def generate_challenge_url(self, hwid):
 
         challenge = self.get_rma_challenge()
         self.print_platform_info()
-        logging.info('CHALLENGE: %s', challenge)
-        logging.info('HWID: %s', hwid)
+        logging.info("CHALLENGE: %s", challenge)
+        logging.info("HWID: %s", hwid)
         url = URL % (challenge, hwid)
-        logging.info('GOTO:\n %s', url)
-        logging.info('If the server fails to debug the challenge make sure the '
-                     'RLZ is allowlisted')
+        logging.info("GOTO:\n %s", url)
+        logging.info(
+            "If the server fails to debug the challenge make sure the "
+            "RLZ is allowlisted"
+        )
 
     def try_authcode(self, authcode):
         """Try opening cr50 with the authcode
@@ -272,48 +275,48 @@ def try_authcode(self, authcode):
         """
         # rma_auth may cause the system to reboot. Don't wait to read all that
         # output. Read the first 300 bytes and call it a day.
-        output = self.send_cmd_get_output('rma_auth ' + authcode, nbytes=300)
-        logging.info('CR50 RESPONSE: %s', output)
-        logging.info('waiting for cr50 reboot')
+        output = self.send_cmd_get_output("rma_auth " + authcode, nbytes=300)
+        logging.info("CR50 RESPONSE: %s", output)
+        logging.info("waiting for cr50 reboot")
         # Cr50 may be rebooting. Wait a bit
         time.sleep(5)
         if self.using_ccd:
             # After reboot, reset the ccd endpoints
-            self._dut_control('power_state:ccd_reset')
+            self._dut_control("power_state:ccd_reset")
         # Update the ccd state after the authcode attempt
         self.update_ccd_state()
 
-        authcode_match = 'process_response: success!' in output
+        authcode_match = "process_response: success!" in output
         if not self.check(CCD_IS_UNRESTRICTED):
             if not authcode_match:
                 logging.warning(DEBUG_AUTHCODE_MISMATCH)
-                message = 'Authcode mismatch. Check args and url'
+                message = "Authcode mismatch. Check args and url"
             else:
-                message = 'Could not set all capability privileges to Always'
+                message = "Could not set all capability privileges to Always"
             raise ValueError(message)
 
     def wp_is_force_disabled(self):
         """Returns True if write protect is forced disabled"""
-        output = self.send_cmd_get_output('wp')
-        wp_state = output.split('Flash WP:', 1)[-1].split('\n', 1)[0].strip()
-        logging.info('wp: %s', wp_state)
-        return wp_state == 'forced disabled'
+        output = self.send_cmd_get_output("wp")
+        wp_state = output.split("Flash WP:", 1)[-1].split("\n", 1)[0].strip()
+        logging.info("wp: %s", wp_state)
+        return wp_state == "forced disabled"
 
     def testlab_is_enabled(self):
         """Returns True if testlab mode is enabled"""
-        output = self.send_cmd_get_output('ccd testlab')
-        testlab_state = output.split('mode')[-1].strip().lower()
-        logging.info('testlab: %s', testlab_state)
-        return testlab_state == 'enabled'
+        output = self.send_cmd_get_output("ccd testlab")
+        testlab_state = output.split("mode")[-1].strip().lower()
+        logging.info("testlab: %s", testlab_state)
+        return testlab_state == "enabled"
 
     def ccd_is_restricted(self):
         """Returns True if any of the capabilities are still restricted"""
-        output = self.send_cmd_get_output('ccd')
-        if 'Capabilities' not in output:
-            raise ValueError('Could not get ccd output')
-        logging.debug('CURRENT CCD SETTINGS:\n%s', output)
-        restricted = 'IfOpened' in output or 'IfUnlocked' in output
-        logging.info('ccd: %srestricted', '' if restricted else 'Un')
+        output = self.send_cmd_get_output("ccd")
+        if "Capabilities" not in output:
+            raise ValueError("Could not get ccd output")
+        logging.debug("CURRENT CCD SETTINGS:\n%s", output)
+        restricted = "IfOpened" in output or "IfUnlocked" in output
+        logging.info("ccd: %srestricted", "" if restricted else "Un")
         return restricted
 
     def update_ccd_state(self):
@@ -339,9 +342,10 @@ def _has_testlab_support(self):
 
     def _capabilities_allow_open_from_console(self):
         """Return True if ccd open is Always allowed from usb"""
-        output = self.send_cmd_get_output('ccd')
-        return (re.search('OpenNoDevMode.*Always', output) and
-                re.search('OpenFromUSB.*Always', output))
+        output = self.send_cmd_get_output("ccd")
+        return re.search("OpenNoDevMode.*Always", output) and re.search(
+            "OpenFromUSB.*Always", output
+        )
 
     def _requires_dev_mode_open(self):
         """Return True if the image requires dev mode to open"""
@@ -354,78 +358,83 @@ def _requires_dev_mode_open(self):
 
     def _run_on_dut(self, command):
         """Run the command on the DUT."""
-        return subprocess.check_output(['ssh', self.ip, command],
-                                       encoding='utf-8')
+        return subprocess.check_output(
+            ["ssh", self.ip, command], encoding="utf-8"
+        )
 
     def _open_in_dev_mode(self):
         """Open Cr50 when it's in dev mode"""
-        output = self.send_cmd_get_output('ccd')
+        output = self.send_cmd_get_output("ccd")
         # If the device is already open, nothing needs to be done.
-        if 'State: Open' not in output:
+        if "State: Open" not in output:
             # Verify the device is in devmode before trying to run open.
-            if 'dev_mode' not in output:
-                logging.warning('Enter dev mode to open ccd or update to %s',
-                                TESTLAB_PROD)
-                raise ValueError('DUT not in dev mode')
+            if "dev_mode" not in output:
+                logging.warning(
+                    "Enter dev mode to open ccd or update to %s", TESTLAB_PROD
+                )
+                raise ValueError("DUT not in dev mode")
             if not self.ip:
-                logging.warning("If your DUT doesn't have ssh support, run "
-                                "'gsctool -a -o' from the AP")
-                raise ValueError('Cannot run ccd open without dut ip')
-            self._run_on_dut('gsctool -a -o')
+                logging.warning(
+                    "If your DUT doesn't have ssh support, run "
+                    "'gsctool -a -o' from the AP"
+                )
+                raise ValueError("Cannot run ccd open without dut ip")
+            self._run_on_dut("gsctool -a -o")
             # Wait >1 second for cr50 to update ccd state
             time.sleep(3)
-            output = self.send_cmd_get_output('ccd')
-            if 'State: Open' not in output:
-                raise ValueError('Could not open cr50')
-        logging.info('ccd is open')
+            output = self.send_cmd_get_output("ccd")
+            if "State: Open" not in output:
+                raise ValueError("Could not open cr50")
+        logging.info("ccd is open")
 
     def enable_testlab(self):
         """Disable write protect"""
         if not self._has_testlab_support():
-            logging.warning('Testlab mode is not supported in prod iamges')
+            logging.warning("Testlab mode is not supported in prod iamges")
             return
         # Some cr50 images need to be in dev mode before they can be opened.
         if self._requires_dev_mode_open():
             self._open_in_dev_mode()
         else:
-            self.send_cmd_get_output('ccd open')
-        logging.info('Enabling testlab mode reqires pressing the power button.')
-        logging.info('Once the process starts keep tapping the power button '
-                     'for 10 seconds.')
+            self.send_cmd_get_output("ccd open")
+        logging.info("Enabling testlab mode reqires pressing the power button.")
+        logging.info(
+            "Once the process starts keep tapping the power button for 10 seconds."
+        )
         input("Press Enter when you're ready to start...")
         end_time = time.time() + 15
 
         ser = serial.Serial(self.device, timeout=1)
-        printed_lines = ''
-        output = ''
+        printed_lines = ""
+        output = ""
         # start ccd testlab enable
-        ser.write(self.ENABLE_TESTLAB_CMD.encode('utf-8'))
-        logging.info('start pressing the power button\n\n')
+        ser.write(self.ENABLE_TESTLAB_CMD.encode("utf-8"))
+        logging.info("start pressing the power button\n\n")
         # Print all of the cr50 output as we get it, so the user will have more
         # information about pressing the power button. Tapping the power button
         # a couple of times should do it, but this will give us more confidence
         # the process is still running/worked.
         try:
             while time.time() < end_time:
-                output += ser.read(100).decode('utf-8')
-                full_lines = output.rsplit('\n', 1)[0]
+                output += ser.read(100).decode("utf-8")
+                full_lines = output.rsplit("\n", 1)[0]
                 new_lines = full_lines
                 if printed_lines:
                     new_lines = full_lines.split(printed_lines, 1)[-1].strip()
-                logging.info('\n%s', new_lines)
+                logging.info("\n%s", new_lines)
                 printed_lines = full_lines
 
                 # Make sure the process hasn't ended. If it has, print the last
                 # of the output and exit.
                 new_lines = output.split(printed_lines, 1)[-1]
-                if 'CCD test lab mode enabled' in output:
+                if "CCD test lab mode enabled" in output:
                     # print the last of the ou
                     logging.info(new_lines)
                     break
-                elif 'Physical presence check timeout' in output:
+                elif "Physical presence check timeout" in output:
                     logging.info(new_lines)
-                    logging.warning('Did not detect power button press in time')
-                    raise ValueError('Could not enable testlab mode try again')
+                    logging.warning("Did not detect power button press in time")
+                    raise ValueError("Could not enable testlab mode try again")
         finally:
             ser.close()
         # Wait for the ccd hook to update things
@@ -433,44 +442,50 @@ def enable_testlab(self):
         # Update the state after attempting to disable write protect
         self.update_ccd_state()
         if not self.check(TESTLAB_IS_ENABLED):
-            raise ValueError('Could not enable testlab mode try again')
+            raise ValueError("Could not enable testlab mode try again")
 
     def wp_disable(self):
         """Disable write protect"""
-        logging.info('Disabling write protect')
-        self.send_cmd_get_output('wp disable')
+        logging.info("Disabling write protect")
+        self.send_cmd_get_output("wp disable")
         # Update the state after attempting to disable write protect
         self.update_ccd_state()
         if not self.check(WP_IS_DISABLED):
-            raise ValueError('Could not disable write protect')
+            raise ValueError("Could not disable write protect")
 
     def check_version(self):
         """Make sure cr50 is running a version that supports RMA Open"""
-        output = self.send_cmd_get_output('version')
+        output = self.send_cmd_get_output("version")
         if not output.strip():
             logging.warning(DEBUG_DEVICE, self.device)
-            raise ValueError('Could not communicate with %s' % self.device)
+            raise ValueError("Could not communicate with %s" % self.device)
 
-        version = re.search(r'RW.*\* ([\d\.]+)/', output).group(1)
-        logging.info('Running Cr50 Version: %s', version)
-        self.running_ver_fields = [int(field) for field in version.split('.')]
+        version = re.search(r"RW.*\* ([\d\.]+)/", output).group(1)
+        logging.info("Running Cr50 Version: %s", version)
+        self.running_ver_fields = [int(field) for field in version.split(".")]
 
         # prePVT images have even major versions. Prod have odd
         self.is_prepvt = self.running_ver_fields[1] % 2 == 0
         rma_support = RMA_SUPPORT_PREPVT if self.is_prepvt else RMA_SUPPORT_PROD
 
-        logging.info('%s RMA support added in: %s',
-                     'prePVT' if self.is_prepvt else 'prod', rma_support)
+        logging.info(
+            "%s RMA support added in: %s",
+            "prePVT" if self.is_prepvt else "prod",
+            rma_support,
+        )
         if not self.is_prepvt and self._running_version_is_older(TESTLAB_PROD):
-            raise ValueError('Update cr50. No testlab support in old prod '
-                             'images.')
+            raise ValueError(
+                "Update cr50. No testlab support in old prod images."
+            )
         if self._running_version_is_older(rma_support):
-            raise ValueError('%s does not have RMA support. Update to at '
-                             'least %s' % (version, rma_support))
+            raise ValueError(
+                "%s does not have RMA support. Update to at least %s"
+                % (version, rma_support)
+            )
 
     def _running_version_is_older(self, target_ver):
         """Returns True if running version is older than target_ver."""
-        target_ver_fields = [int(field) for field in target_ver.split('.')]
+        target_ver_fields = [int(field) for field in target_ver.split(".")]
         for i, field in enumerate(self.running_ver_fields):
             if field > int(target_ver_fields[i]):
                 return False
@@ -486,11 +501,11 @@ def device_matches_devid(self, devid, device):
             is no output or sysinfo doesn't contain the devid.
         """
         self.set_cr50_device(device)
-        sysinfo = self.send_cmd_get_output('sysinfo')
+        sysinfo = self.send_cmd_get_output("sysinfo")
         # Make sure there is some output, and it shows it's from Cr50
-        if not sysinfo or 'cr50' not in sysinfo:
+        if not sysinfo or "cr50" not in sysinfo:
             return False
-        logging.debug('Sysinfo output: %s', sysinfo)
+        logging.debug("Sysinfo output: %s", sysinfo)
         # The cr50 device id should be in the sysinfo output, if we found
         # the right console. Make sure it is
         return devid in sysinfo
@@ -508,104 +523,150 @@ def find_cr50_device(self, usb_serial):
             ValueError if the console can't be found with the given serialname
         """
         usb_serial = self.find_cr50_usb(usb_serial)
-        logging.info('SERIALNAME: %s', usb_serial)
-        devid = '0x' + ' 0x'.join(usb_serial.lower().split('-'))
-        logging.info('DEVID: %s', devid)
+        logging.info("SERIALNAME: %s", usb_serial)
+        devid = "0x" + " 0x".join(usb_serial.lower().split("-"))
+        logging.info("DEVID: %s", devid)
 
         # Get all the usb devices
-        devices = glob.glob('/dev/ttyUSB*')
+        devices = glob.glob("/dev/ttyUSB*")
         # Typically Cr50 has the lowest number. Sort the devices, so we're more
         # likely to try the cr50 console first.
         devices.sort()
 
         # Find the one that is the cr50 console
         for device in devices:
-            logging.info('testing %s', device)
+            logging.info("testing %s", device)
             if self.device_matches_devid(devid, device):
-                logging.info('found device: %s', device)
+                logging.info("found device: %s", device)
                 return
         logging.warning(DEBUG_CONNECTION)
-        raise ValueError('Found USB device, but could not communicate with '
-                         'cr50 console')
+        raise ValueError(
+            "Found USB device, but could not communicate with cr50 console"
+        )
 
     def print_platform_info(self):
         """Print the cr50 BID RLZ code"""
-        bid_output = self.send_cmd_get_output('bid')
-        bid = re.search(r'Board ID: (\S+?)[:,]', bid_output).group(1)
+        bid_output = self.send_cmd_get_output("bid")
+        bid = re.search(r"Board ID: (\S+?)[:,]", bid_output).group(1)
         if bid == ERASED_BID:
             logging.warning(DEBUG_ERASED_BOARD_ID)
-            raise ValueError('Cannot run RMA Open when board id is erased')
+            raise ValueError("Cannot run RMA Open when board id is erased")
         bid = int(bid, 16)
-        chrs = [chr((bid >> (8 * i)) & 0xff) for i in range(4)]
-        logging.info('RLZ: %s', ''.join(chrs[::-1]))
+        chrs = [chr((bid >> (8 * i)) & 0xFF) for i in range(4)]
+        logging.info("RLZ: %s", "".join(chrs[::-1]))
 
     @staticmethod
     def find_cr50_usb(usb_serial):
         """Make sure the Cr50 USB device exists"""
         try:
-            output = subprocess.check_output(CR50_LSUSB_CMD, encoding='utf-8')
+            output = subprocess.check_output(CR50_LSUSB_CMD, encoding="utf-8")
         except:
             logging.warning(DEBUG_MISSING_USB)
-            raise ValueError('Could not find Cr50 USB device')
-        serialnames = re.findall(r'iSerial +\d+ (\S+)\s', output)
+            raise ValueError("Could not find Cr50 USB device")
+        serialnames = re.findall(r"iSerial +\d+ (\S+)\s", output)
         if usb_serial:
             if usb_serial not in serialnames:
                 logging.warning(DEBUG_SERIALNAME)
                 raise ValueError('Could not find usb device "%s"' % usb_serial)
             return usb_serial
         if len(serialnames) > 1:
-            logging.info('Found Cr50 device serialnames %s',
-                         ', '.join(serialnames))
+            logging.info(
+                "Found Cr50 device serialnames %s", ", ".join(serialnames)
+            )
             logging.warning(DEBUG_TOO_MANY_USB_DEVICES)
-            raise ValueError('Too many cr50 usb devices')
+            raise ValueError("Too many cr50 usb devices")
         return serialnames[0]
 
     def print_dut_state(self):
         """Print CCD RMA and testlab mode state."""
         if not self.check(CCD_IS_UNRESTRICTED):
-            logging.info('CCD is still restricted.')
-            logging.info('Run cr50_rma_open.py -g -i $HWID to generate a url')
-            logging.info('Run cr50_rma_open.py -a $AUTHCODE to open cr50 with '
-                         'an authcode')
+            logging.info("CCD is still restricted.")
+            logging.info("Run cr50_rma_open.py -g -i $HWID to generate a url")
+            logging.info(
+                "Run cr50_rma_open.py -a $AUTHCODE to open cr50 with an authcode"
+            )
         elif not self.check(WP_IS_DISABLED):
-            logging.info('WP is still enabled.')
-            logging.info('Run cr50_rma_open.py -w to disable write protect')
+            logging.info("WP is still enabled.")
+            logging.info("Run cr50_rma_open.py -w to disable write protect")
         if self.check(RMA_OPENED):
-            logging.info('RMA Open complete')
+            logging.info("RMA Open complete")
 
         if not self.check(TESTLAB_IS_ENABLED) and self.is_prepvt:
-            logging.info('testlab mode is disabled.')
-            logging.info('If you are prepping a device for the testlab, you '
-                         'should enable testlab mode.')
-            logging.info('Run cr50_rma_open.py -t to enable testlab mode')
+            logging.info("testlab mode is disabled.")
+            logging.info(
+                "If you are prepping a device for the testlab, you "
+                "should enable testlab mode."
+            )
+            logging.info("Run cr50_rma_open.py -t to enable testlab mode")
 
 
 def parse_args(argv):
     """Get cr50_rma_open args."""
     parser = argparse.ArgumentParser(
-        description=__doc__, formatter_class=argparse.RawTextHelpFormatter)
-    parser.add_argument('-g', '--generate_challenge', action='store_true',
-                        help='Generate Cr50 challenge. Must be used with -i')
-    parser.add_argument('-t', '--enable_testlab', action='store_true',
-                        help='enable testlab mode')
-    parser.add_argument('-w', '--wp_disable', action='store_true',
-                        help='Disable write protect')
-    parser.add_argument('-c', '--check_connection', action='store_true',
-                        help='Check cr50 console connection works')
-    parser.add_argument('-s', '--serialname', type=str, default='',
-                        help='The cr50 usb serialname')
-    parser.add_argument('-D', '--debug', action='store_true',
-                        help='print debug messages')
-    parser.add_argument('-d', '--device', type=str, default='',
-                        help='cr50 console device ex /dev/ttyUSB0')
-    parser.add_argument('-i', '--hwid', type=str, default='',
-                        help='The board hwid. Needed to generate a challenge')
-    parser.add_argument('-a', '--authcode', type=str, default='',
-                        help='The authcode string from the challenge url')
-    parser.add_argument('-P', '--servo_port', type=str, default='',
-                        help='the servo port')
-    parser.add_argument('-I', '--ip', type=str, default='',
-                        help='The DUT IP. Necessary to do ccd open')
+        description=__doc__, formatter_class=argparse.RawTextHelpFormatter
+    )
+    parser.add_argument(
+        "-g",
+        "--generate_challenge",
+        action="store_true",
+        help="Generate Cr50 challenge. Must be used with -i",
+    )
+    parser.add_argument(
+        "-t",
+        "--enable_testlab",
+        action="store_true",
+        help="enable testlab mode",
+    )
+    parser.add_argument(
+        "-w", "--wp_disable", action="store_true", help="Disable write protect"
+    )
+    parser.add_argument(
+        "-c",
+        "--check_connection",
+        action="store_true",
+        help="Check cr50 console connection works",
+    )
+    parser.add_argument(
+        "-s",
+        "--serialname",
+        type=str,
+        default="",
+        help="The cr50 usb serialname",
+    )
+    parser.add_argument(
+        "-D", "--debug", action="store_true", help="print debug messages"
+    )
+    parser.add_argument(
+        "-d",
+        "--device",
+        type=str,
+        default="",
+        help="cr50 console device ex /dev/ttyUSB0",
+    )
+    parser.add_argument(
+        "-i",
+        "--hwid",
+        type=str,
+        default="",
+        help="The board hwid. Needed to generate a challenge",
+    )
+    parser.add_argument(
+        "-a",
+        "--authcode",
+        type=str,
+        default="",
+        help="The authcode string from the challenge url",
+    )
+    parser.add_argument(
+        "-P", "--servo_port", type=str, default="", help="the servo port"
+    )
+    parser.add_argument(
+        "-I",
+        "--ip",
+        type=str,
+        default="",
+        help="The DUT IP. Necessary to do ccd open",
+    )
     return parser.parse_args(argv)
 
 
@@ -614,52 +675,59 @@ def main(argv):
     opts = parse_args(argv)
 
     loglevel = logging.INFO
-    log_format = '%(levelname)7s'
+    log_format = "%(levelname)7s"
     if opts.debug:
         loglevel = logging.DEBUG
-        log_format += ' - %(lineno)3d:%(funcName)-15s'
-    log_format += ' - %(message)s'
+        log_format += " - %(lineno)3d:%(funcName)-15s"
+    log_format += " - %(message)s"
     logging.basicConfig(level=loglevel, format=log_format)
 
     tried_authcode = False
-    logging.info('Running cr50_rma_open version %s', SCRIPT_VERSION)
+    logging.info("Running cr50_rma_open version %s", SCRIPT_VERSION)
 
-    cr50_rma_open = RMAOpen(opts.device, opts.serialname, opts.servo_port,
-                            opts.ip)
+    cr50_rma_open = RMAOpen(
+        opts.device, opts.serialname, opts.servo_port, opts.ip
+    )
     if opts.check_connection:
         sys.exit(0)
 
     if not cr50_rma_open.check(CCD_IS_UNRESTRICTED):
         if opts.generate_challenge:
             if not opts.hwid:
-                logging.warning('--hwid necessary to generate challenge url')
+                logging.warning("--hwid necessary to generate challenge url")
                 sys.exit(0)
             cr50_rma_open.generate_challenge_url(opts.hwid)
             sys.exit(0)
         elif opts.authcode:
-            logging.info('Using authcode: %s', opts.authcode)
+            logging.info("Using authcode: %s", opts.authcode)
             cr50_rma_open.try_authcode(opts.authcode)
             tried_authcode = True
 
-    if not cr50_rma_open.check(WP_IS_DISABLED) and (tried_authcode or
-                                                    opts.wp_disable):
+    if not cr50_rma_open.check(WP_IS_DISABLED) and (
+        tried_authcode or opts.wp_disable
+    ):
         if not cr50_rma_open.check(CCD_IS_UNRESTRICTED):
-            raise ValueError("Can't disable write protect unless ccd is "
-                             "open. Run through the rma open process first")
+            raise ValueError(
+                "Can't disable write protect unless ccd is "
+                "open. Run through the rma open process first"
+            )
         if tried_authcode:
-            logging.warning('RMA Open did not disable write protect. File a '
-                            'bug')
-            logging.warning('Trying to disable it manually')
+            logging.warning(
+                "RMA Open did not disable write protect. File a bug"
+            )
+            logging.warning("Trying to disable it manually")
         cr50_rma_open.wp_disable()
 
     if not cr50_rma_open.check(TESTLAB_IS_ENABLED) and opts.enable_testlab:
         if not cr50_rma_open.check(CCD_IS_UNRESTRICTED):
-            raise ValueError("Can't enable testlab mode unless ccd is open."
-                             "Run through the rma open process first")
+            raise ValueError(
+                "Can't enable testlab mode unless ccd is open."
+                "Run through the rma open process first"
+            )
         cr50_rma_open.enable_testlab()
 
     cr50_rma_open.print_dut_state()
 
 
-if __name__ == '__main__':
+if __name__ == "__main__":
     sys.exit(main(sys.argv[1:]))
diff --git a/extra/ftdi_hostcmd/Makefile b/extra/ftdi_hostcmd/Makefile
index d46b4b1c72..10f0e2d390 100644
--- a/extra/ftdi_hostcmd/Makefile
+++ b/extra/ftdi_hostcmd/Makefile
@@ -1,4 +1,4 @@
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/extra/ftdi_hostcmd/test_cmds.c b/extra/ftdi_hostcmd/test_cmds.c
index 9ee27cd6d4..62291e938d 100644
--- a/extra/ftdi_hostcmd/test_cmds.c
+++ b/extra/ftdi_hostcmd/test_cmds.c
@@ -1,18 +1,18 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "ec_commands.h"
+#include "mpsse.h"
+
 #include <signal.h>
 #include <stdint.h>
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
-#include <unistd.h>
 
-#include "mpsse.h"
-
-#include "ec_commands.h"
+#include <unistd.h>
 
 static int opt_verbose;
 
@@ -22,7 +22,7 @@ static struct mpsse_context *mpsse;
 /* enum ec_status meaning */
 static const char *ec_strerr(enum ec_status r)
 {
-	static const char * const strs[] = {
+	static const char *const strs[] = {
 		"SUCCESS",
 		"INVALID_COMMAND",
 		"ERROR",
@@ -47,7 +47,6 @@ static const char *ec_strerr(enum ec_status r)
 	return "<undefined result>";
 };
 
-
 /****************************************************************************
  * Debugging output
  */
@@ -64,8 +63,7 @@ static void showline(uint8_t *buf, int len)
 		printf("   ");
 	printf("    ");
 	for (i = 0; i < len; i++)
-		printf("%c",
-		       (buf[i] >= ' ' && buf[i] <= '~') ? buf[i] : '.');
+		printf("%c", (buf[i] >= ' ' && buf[i] <= '~') ? buf[i] : '.');
 	printf("\n");
 }
 
@@ -104,8 +102,8 @@ static uint8_t txbuf[128];
  * Load the output buffer with a proto v3 request (header, then data, with
  * checksum correct in header).
  */
-static size_t prepare_request(int cmd, int version,
-			      const uint8_t *data, size_t data_len)
+static size_t prepare_request(int cmd, int version, const uint8_t *data,
+			      size_t data_len)
 {
 	struct ec_host_request *request;
 	size_t i, total_len;
@@ -113,8 +111,8 @@ static size_t prepare_request(int cmd, int version,
 
 	total_len = sizeof(*request) + data_len;
 	if (total_len > sizeof(txbuf)) {
-		printf("Request too large (%zd > %zd)\n",
-		       total_len, sizeof(txbuf));
+		printf("Request too large (%zd > %zd)\n", total_len,
+		       sizeof(txbuf));
 		return -1;
 	}
 
@@ -153,8 +151,7 @@ static int send_request(uint8_t *txbuf, size_t len)
 	tptr = Transfer(mpsse, txbuf, len);
 
 	if (!tptr) {
-		fprintf(stderr, "Transfer failed: %s\n",
-			ErrorString(mpsse));
+		fprintf(stderr, "Transfer failed: %s\n", ErrorString(mpsse));
 		return -1;
 	}
 
@@ -178,7 +175,6 @@ static int send_request(uint8_t *txbuf, size_t len)
 	return ret;
 }
 
-
 /* Timeout flag, so we don't wait forever */
 static int timedout;
 static void alarm_handler(int sig)
@@ -195,8 +191,8 @@ static void alarm_handler(int sig)
  *   0   = response received (check hdr for EC result and body size)
  *   -1  = problems
  */
-static int get_response(struct ec_host_response *hdr,
-			uint8_t *bodydest, size_t bodylen)
+static int get_response(struct ec_host_response *hdr, uint8_t *bodydest,
+			size_t bodylen)
 {
 	uint8_t *hptr = 0, *bptr = 0;
 	uint8_t sum = 0;
@@ -237,8 +233,7 @@ static int get_response(struct ec_host_response *hdr,
 	/* Now read the response header */
 	hptr = Read(mpsse, sizeof(*hdr));
 	if (!hptr) {
-		fprintf(stderr, "Read failed: %s\n",
-			ErrorString(mpsse));
+		fprintf(stderr, "Read failed: %s\n", ErrorString(mpsse));
 		goto out;
 	}
 	show("Header(%d):\n", hptr, sizeof(*hdr));
@@ -247,14 +242,12 @@ static int get_response(struct ec_host_response *hdr,
 	/* Check the header */
 	if (hdr->struct_version != EC_HOST_RESPONSE_VERSION) {
 		printf("response version %d (should be %d)\n",
-		       hdr->struct_version,
-		       EC_HOST_RESPONSE_VERSION);
+		       hdr->struct_version, EC_HOST_RESPONSE_VERSION);
 		goto out;
 	}
 
 	if (hdr->data_len > bodylen) {
-		printf("response data_len %d is > %zd\n",
-		       hdr->data_len,
+		printf("response data_len %d is > %zd\n", hdr->data_len,
 		       bodylen);
 		goto out;
 	}
@@ -290,19 +283,13 @@ static int get_response(struct ec_host_response *hdr,
 	return ret;
 }
 
-
 /*
  * Send command, wait for result. Return zero if communication succeeded; check
  * response to see if the EC liked the command.
  */
-static int send_cmd(int cmd, int version,
-		    void *outbuf,
-		    size_t outsize,
-		    struct ec_host_response *resp,
-		    void *inbuf,
-		    size_t insize)
+static int send_cmd(int cmd, int version, void *outbuf, size_t outsize,
+		    struct ec_host_response *resp, void *inbuf, size_t insize)
 {
-
 	size_t len;
 	int ret = -1;
 
@@ -312,8 +299,7 @@ static int send_cmd(int cmd, int version,
 		return -1;
 
 	if (MPSSE_OK != Start(mpsse)) {
-		fprintf(stderr, "Start failed: %s\n",
-			ErrorString(mpsse));
+		fprintf(stderr, "Start failed: %s\n", ErrorString(mpsse));
 		return -1;
 	}
 
@@ -322,15 +308,13 @@ static int send_cmd(int cmd, int version,
 		ret = 0;
 
 	if (MPSSE_OK != Stop(mpsse)) {
-		fprintf(stderr, "Stop failed: %s\n",
-			ErrorString(mpsse));
+		fprintf(stderr, "Stop failed: %s\n", ErrorString(mpsse));
 		return -1;
 	}
 
 	return ret;
 }
 
-
 /****************************************************************************
  * Probe for basic protocol info
  */
@@ -352,10 +336,8 @@ static int probe_v3(void)
 	if (opt_verbose)
 		printf("Trying EC_CMD_GET_PROTOCOL_INFO...\n");
 
-	ret = send_cmd(EC_CMD_GET_PROTOCOL_INFO, 0,
-		       0, 0,
-		       &resp,
-		       &info, sizeof(info));
+	ret = send_cmd(EC_CMD_GET_PROTOCOL_INFO, 0, 0, 0, &resp, &info,
+		       sizeof(info));
 
 	if (ret) {
 		printf("EC_CMD_GET_PROTOCOL_INFO failed\n");
@@ -363,8 +345,8 @@ static int probe_v3(void)
 	}
 
 	if (EC_RES_SUCCESS != resp.result) {
-		printf("EC result is %d: %s\n",
-		       resp.result, ec_strerr(resp.result));
+		printf("EC result is %d: %s\n", resp.result,
+		       ec_strerr(resp.result));
 		return -1;
 	}
 
@@ -378,8 +360,7 @@ static int probe_v3(void)
 	       info.max_request_packet_size);
 	printf("  max_response_packet_size:   %d\n",
 	       info.max_response_packet_size);
-	printf("  flags:                      0x%x\n",
-	       info.flags);
+	printf("  flags:                      0x%x\n", info.flags);
 
 	return 0;
 }
@@ -390,119 +371,112 @@ static int probe_v3(void)
 
 struct lookup {
 	uint16_t cmd;
-	const char * const desc;
+	const char *const desc;
 };
 
 static struct lookup cmd_table[] = {
-	{0x00, "EC_CMD_PROTO_VERSION"},
-	{0x01, "EC_CMD_HELLO"},
-	{0x02, "EC_CMD_GET_VERSION"},
-	{0x03, "EC_CMD_READ_TEST"},
-	{0x04, "EC_CMD_GET_BUILD_INFO"},
-	{0x05, "EC_CMD_GET_CHIP_INFO"},
-	{0x06, "EC_CMD_GET_BOARD_VERSION"},
-	{0x07, "EC_CMD_READ_MEMMAP"},
-	{0x08, "EC_CMD_GET_CMD_VERSIONS"},
-	{0x09, "EC_CMD_GET_COMMS_STATUS"},
-	{0x0a, "EC_CMD_TEST_PROTOCOL"},
-	{0x0b, "EC_CMD_GET_PROTOCOL_INFO"},
-	{0x0c, "EC_CMD_GSV_PAUSE_IN_S5"},
-	{0x0d, "EC_CMD_GET_FEATURES"},
-	{0x10, "EC_CMD_FLASH_INFO"},
-	{0x11, "EC_CMD_FLASH_READ"},
-	{0x12, "EC_CMD_FLASH_WRITE"},
-	{0x13, "EC_CMD_FLASH_ERASE"},
-	{0x15, "EC_CMD_FLASH_PROTECT"},
-	{0x16, "EC_CMD_FLASH_REGION_INFO"},
-	{0x17, "EC_CMD_VBNV_CONTEXT"},
-	{0x20, "EC_CMD_PWM_GET_FAN_TARGET_RPM"},
-	{0x21, "EC_CMD_PWM_SET_FAN_TARGET_RPM"},
-	{0x22, "EC_CMD_PWM_GET_KEYBOARD_BACKLIGHT"},
-	{0x23, "EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT"},
-	{0x24, "EC_CMD_PWM_SET_FAN_DUTY"},
-	{0x28, "EC_CMD_LIGHTBAR_CMD"},
-	{0x29, "EC_CMD_LED_CONTROL"},
-	{0x2a, "EC_CMD_VBOOT_HASH"},
-	{0x2b, "EC_CMD_MOTION_SENSE_CMD"},
-	{0x2c, "EC_CMD_FORCE_LID_OPEN"},
-	{0x30, "EC_CMD_USB_CHARGE_SET_MODE"},
-	{0x40, "EC_CMD_PSTORE_INFO"},
-	{0x41, "EC_CMD_PSTORE_READ"},
-	{0x42, "EC_CMD_PSTORE_WRITE"},
-	{0x44, "EC_CMD_RTC_GET_VALUE"},
-	{0x45, "EC_CMD_RTC_GET_ALARM"},
-	{0x46, "EC_CMD_RTC_SET_VALUE"},
-	{0x47, "EC_CMD_RTC_SET_ALARM"},
-	{0x48, "EC_CMD_PORT80_LAST_BOOT"},
-	{0x48, "EC_CMD_PORT80_READ"},
-	{0x50, "EC_CMD_THERMAL_SET_THRESHOLD"},
-	{0x51, "EC_CMD_THERMAL_GET_THRESHOLD"},
-	{0x52, "EC_CMD_THERMAL_AUTO_FAN_CTRL"},
-	{0x53, "EC_CMD_TMP006_GET_CALIBRATION"},
-	{0x54, "EC_CMD_TMP006_SET_CALIBRATION"},
-	{0x55, "EC_CMD_TMP006_GET_RAW"},
-	{0x60, "EC_CMD_MKBP_STATE"},
-	{0x61, "EC_CMD_MKBP_INFO"},
-	{0x62, "EC_CMD_MKBP_SIMULATE_KEY"},
-	{0x64, "EC_CMD_MKBP_SET_CONFIG"},
-	{0x65, "EC_CMD_MKBP_GET_CONFIG"},
-	{0x66, "EC_CMD_KEYSCAN_SEQ_CTRL"},
-	{0x67, "EC_CMD_GET_NEXT_EVENT"},
-	{0x70, "EC_CMD_TEMP_SENSOR_GET_INFO"},
-	{0x87, "EC_CMD_HOST_EVENT_GET_B"},
-	{0x88, "EC_CMD_HOST_EVENT_GET_SMI_MASK"},
-	{0x89, "EC_CMD_HOST_EVENT_GET_SCI_MASK"},
-	{0x8d, "EC_CMD_HOST_EVENT_GET_WAKE_MASK"},
-	{0x8a, "EC_CMD_HOST_EVENT_SET_SMI_MASK"},
-	{0x8b, "EC_CMD_HOST_EVENT_SET_SCI_MASK"},
-	{0x8c, "EC_CMD_HOST_EVENT_CLEAR"},
-	{0x8e, "EC_CMD_HOST_EVENT_SET_WAKE_MASK"},
-	{0x8f, "EC_CMD_HOST_EVENT_CLEAR_B"},
-	{0x90, "EC_CMD_SWITCH_ENABLE_BKLIGHT"},
-	{0x91, "EC_CMD_SWITCH_ENABLE_WIRELESS"},
-	{0x92, "EC_CMD_GPIO_SET"},
-	{0x93, "EC_CMD_GPIO_GET"},
-	{0x94, "EC_CMD_I2C_READ"},
-	{0x95, "EC_CMD_I2C_WRITE"},
-	{0x96, "EC_CMD_CHARGE_CONTROL"},
-	{0x97, "EC_CMD_CONSOLE_SNAPSHOT"},
-	{0x98, "EC_CMD_CONSOLE_READ"},
-	{0x99, "EC_CMD_BATTERY_CUT_OFF"},
-	{0x9a, "EC_CMD_USB_MUX"},
-	{0x9b, "EC_CMD_LDO_SET"},
-	{0x9c, "EC_CMD_LDO_GET"},
-	{0x9d, "EC_CMD_POWER_INFO"},
-	{0x9e, "EC_CMD_I2C_PASSTHRU"},
-	{0x9f, "EC_CMD_HANG_DETECT"},
-	{0xa0, "EC_CMD_CHARGE_STATE"},
-	{0xa1, "EC_CMD_CHARGE_CURRENT_LIMIT"},
-	{0xa2, "EC_CMD_EXT_POWER_CURRENT_LIMIT"},
-	{0xb0, "EC_CMD_SB_READ_WORD"},
-	{0xb1, "EC_CMD_SB_WRITE_WORD"},
-	{0xb2, "EC_CMD_SB_READ_BLOCK"},
-	{0xb3, "EC_CMD_SB_WRITE_BLOCK"},
-	{0xb4, "EC_CMD_BATTERY_VENDOR_PARAM"},
-	{0xb5, "EC_CMD_SB_FW_UPDATE"},
-	{0xd2, "EC_CMD_REBOOT_EC"},
-	{0xd3, "EC_CMD_GET_PANIC_INFO"},
-	{0xd1, "EC_CMD_REBOOT"},
-	{0xdb, "EC_CMD_RESEND_RESPONSE"},
-	{0xdc, "EC_CMD_VERSION0"},
-	{0x100, "EC_CMD_PD_EXCHANGE_STATUS"},
-	{0x104, "EC_CMD_PD_HOST_EVENT_STATUS"},
-	{0x101, "EC_CMD_USB_PD_CONTROL"},
-	{0x102, "EC_CMD_USB_PD_PORTS"},
-	{0x103, "EC_CMD_USB_PD_POWER_INFO"},
-	{0x110, "EC_CMD_USB_PD_FW_UPDATE"},
-	{0x111, "EC_CMD_USB_PD_RW_HASH_ENTRY"},
-	{0x112, "EC_CMD_USB_PD_DEV_INFO"},
-	{0x113, "EC_CMD_USB_PD_DISCOVERY"},
-	{0x114, "EC_CMD_PD_CHARGE_PORT_OVERRIDE"},
-	{0x115, "EC_CMD_PD_GET_LOG_ENTRY"},
-	{0x116, "EC_CMD_USB_PD_GET_AMODE"},
-	{0x117, "EC_CMD_USB_PD_SET_AMODE"},
-	{0x118, "EC_CMD_PD_WRITE_LOG_ENTRY"},
-	{0x200, "EC_CMD_BLOB"},
+	{ 0x00, "EC_CMD_PROTO_VERSION" },
+	{ 0x01, "EC_CMD_HELLO" },
+	{ 0x02, "EC_CMD_GET_VERSION" },
+	{ 0x04, "EC_CMD_GET_BUILD_INFO" },
+	{ 0x05, "EC_CMD_GET_CHIP_INFO" },
+	{ 0x06, "EC_CMD_GET_BOARD_VERSION" },
+	{ 0x07, "EC_CMD_READ_MEMMAP" },
+	{ 0x08, "EC_CMD_GET_CMD_VERSIONS" },
+	{ 0x09, "EC_CMD_GET_COMMS_STATUS" },
+	{ 0x0a, "EC_CMD_TEST_PROTOCOL" },
+	{ 0x0b, "EC_CMD_GET_PROTOCOL_INFO" },
+	{ 0x0c, "EC_CMD_GSV_PAUSE_IN_S5" },
+	{ 0x0d, "EC_CMD_GET_FEATURES" },
+	{ 0x10, "EC_CMD_FLASH_INFO" },
+	{ 0x11, "EC_CMD_FLASH_READ" },
+	{ 0x12, "EC_CMD_FLASH_WRITE" },
+	{ 0x13, "EC_CMD_FLASH_ERASE" },
+	{ 0x15, "EC_CMD_FLASH_PROTECT" },
+	{ 0x16, "EC_CMD_FLASH_REGION_INFO" },
+	{ 0x20, "EC_CMD_PWM_GET_FAN_TARGET_RPM" },
+	{ 0x21, "EC_CMD_PWM_SET_FAN_TARGET_RPM" },
+	{ 0x22, "EC_CMD_PWM_GET_KEYBOARD_BACKLIGHT" },
+	{ 0x23, "EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT" },
+	{ 0x24, "EC_CMD_PWM_SET_FAN_DUTY" },
+	{ 0x28, "EC_CMD_LIGHTBAR_CMD" },
+	{ 0x29, "EC_CMD_LED_CONTROL" },
+	{ 0x2a, "EC_CMD_VBOOT_HASH" },
+	{ 0x2b, "EC_CMD_MOTION_SENSE_CMD" },
+	{ 0x2c, "EC_CMD_FORCE_LID_OPEN" },
+	{ 0x30, "EC_CMD_USB_CHARGE_SET_MODE" },
+	{ 0x40, "EC_CMD_PSTORE_INFO" },
+	{ 0x41, "EC_CMD_PSTORE_READ" },
+	{ 0x42, "EC_CMD_PSTORE_WRITE" },
+	{ 0x44, "EC_CMD_RTC_GET_VALUE" },
+	{ 0x45, "EC_CMD_RTC_GET_ALARM" },
+	{ 0x46, "EC_CMD_RTC_SET_VALUE" },
+	{ 0x47, "EC_CMD_RTC_SET_ALARM" },
+	{ 0x48, "EC_CMD_PORT80_LAST_BOOT" },
+	{ 0x48, "EC_CMD_PORT80_READ" },
+	{ 0x50, "EC_CMD_THERMAL_SET_THRESHOLD" },
+	{ 0x51, "EC_CMD_THERMAL_GET_THRESHOLD" },
+	{ 0x52, "EC_CMD_THERMAL_AUTO_FAN_CTRL" },
+	{ 0x53, "EC_CMD_TMP006_GET_CALIBRATION" },
+	{ 0x54, "EC_CMD_TMP006_SET_CALIBRATION" },
+	{ 0x55, "EC_CMD_TMP006_GET_RAW" },
+	{ 0x60, "EC_CMD_MKBP_STATE" },
+	{ 0x61, "EC_CMD_MKBP_INFO" },
+	{ 0x62, "EC_CMD_MKBP_SIMULATE_KEY" },
+	{ 0x64, "EC_CMD_MKBP_SET_CONFIG" },
+	{ 0x65, "EC_CMD_MKBP_GET_CONFIG" },
+	{ 0x66, "EC_CMD_KEYSCAN_SEQ_CTRL" },
+	{ 0x67, "EC_CMD_GET_NEXT_EVENT" },
+	{ 0x70, "EC_CMD_TEMP_SENSOR_GET_INFO" },
+	{ 0x87, "EC_CMD_HOST_EVENT_GET_B" },
+	{ 0x88, "EC_CMD_HOST_EVENT_GET_SMI_MASK" },
+	{ 0x89, "EC_CMD_HOST_EVENT_GET_SCI_MASK" },
+	{ 0x8d, "EC_CMD_HOST_EVENT_GET_WAKE_MASK" },
+	{ 0x8a, "EC_CMD_HOST_EVENT_SET_SMI_MASK" },
+	{ 0x8b, "EC_CMD_HOST_EVENT_SET_SCI_MASK" },
+	{ 0x8c, "EC_CMD_HOST_EVENT_CLEAR" },
+	{ 0x8e, "EC_CMD_HOST_EVENT_SET_WAKE_MASK" },
+	{ 0x8f, "EC_CMD_HOST_EVENT_CLEAR_B" },
+	{ 0x90, "EC_CMD_SWITCH_ENABLE_BKLIGHT" },
+	{ 0x91, "EC_CMD_SWITCH_ENABLE_WIRELESS" },
+	{ 0x92, "EC_CMD_GPIO_SET" },
+	{ 0x93, "EC_CMD_GPIO_GET" },
+	{ 0x94, "EC_CMD_I2C_READ" },
+	{ 0x95, "EC_CMD_I2C_WRITE" },
+	{ 0x96, "EC_CMD_CHARGE_CONTROL" },
+	{ 0x97, "EC_CMD_CONSOLE_SNAPSHOT" },
+	{ 0x98, "EC_CMD_CONSOLE_READ" },
+	{ 0x99, "EC_CMD_BATTERY_CUT_OFF" },
+	{ 0x9a, "EC_CMD_USB_MUX" },
+	{ 0x9b, "EC_CMD_LDO_SET" },
+	{ 0x9c, "EC_CMD_LDO_GET" },
+	{ 0x9d, "EC_CMD_POWER_INFO" },
+	{ 0x9e, "EC_CMD_I2C_PASSTHRU" },
+	{ 0x9f, "EC_CMD_HANG_DETECT" },
+	{ 0xa0, "EC_CMD_CHARGE_STATE" },
+	{ 0xa1, "EC_CMD_CHARGE_CURRENT_LIMIT" },
+	{ 0xa2, "EC_CMD_EXT_POWER_CURRENT_LIMIT" },
+	{ 0xb4, "EC_CMD_BATTERY_VENDOR_PARAM" },
+	{ 0xd2, "EC_CMD_REBOOT_EC" },
+	{ 0xd3, "EC_CMD_GET_PANIC_INFO" },
+	{ 0xd1, "EC_CMD_REBOOT" },
+	{ 0xdb, "EC_CMD_RESEND_RESPONSE" },
+	{ 0xdc, "EC_CMD_VERSION0" },
+	{ 0x100, "EC_CMD_PD_EXCHANGE_STATUS" },
+	{ 0x104, "EC_CMD_PD_HOST_EVENT_STATUS" },
+	{ 0x101, "EC_CMD_USB_PD_CONTROL" },
+	{ 0x102, "EC_CMD_USB_PD_PORTS" },
+	{ 0x103, "EC_CMD_USB_PD_POWER_INFO" },
+	{ 0x110, "EC_CMD_USB_PD_FW_UPDATE" },
+	{ 0x111, "EC_CMD_USB_PD_RW_HASH_ENTRY" },
+	{ 0x112, "EC_CMD_USB_PD_DEV_INFO" },
+	{ 0x113, "EC_CMD_USB_PD_DISCOVERY" },
+	{ 0x114, "EC_CMD_PD_CHARGE_PORT_OVERRIDE" },
+	{ 0x115, "EC_CMD_PD_GET_LOG_ENTRY" },
+	{ 0x116, "EC_CMD_USB_PD_GET_AMODE" },
+	{ 0x117, "EC_CMD_USB_PD_SET_AMODE" },
+	{ 0x118, "EC_CMD_PD_WRITE_LOG_ENTRY" },
+	{ 0x200, "EC_CMD_BLOB" },
 };
 
 #define ARRAY_SIZE(A) (sizeof(A) / sizeof(A[0]))
@@ -532,15 +506,13 @@ static void scan_commands(uint16_t start, uint16_t stop)
 
 	printf("Supported host commands:\n");
 	for (i = start; i <= stop; i++) {
-
 		if (opt_verbose)
 			printf("Querying CMD %02x\n", i);
 
 		q_vers.cmd = i;
-		if (0 != send_cmd(EC_CMD_GET_CMD_VERSIONS, 1,
-				  &q_vers, sizeof(q_vers),
-				  &ec_resp,
-				  &r_vers, sizeof(r_vers))) {
+		if (0 != send_cmd(EC_CMD_GET_CMD_VERSIONS, 1, &q_vers,
+				  sizeof(q_vers), &ec_resp, &r_vers,
+				  sizeof(r_vers))) {
 			printf("query failed on cmd %02x - aborting\n", i);
 			return;
 		}
@@ -557,8 +529,7 @@ static void scan_commands(uint16_t start, uint16_t stop)
 			break;
 		default:
 			printf("lookup of cmd %02x returned %d %s\n", i,
-			       ec_resp.result,
-			       ec_strerr(ec_resp.result));
+			       ec_resp.result, ec_strerr(ec_resp.result));
 		}
 	}
 }
@@ -596,9 +567,9 @@ int main(int argc, char *argv[])
 
 	/* Range (no error checking) */
 	if (optind < argc)
-		start = (uint16_t)strtoul(argv[optind++], 0, 0);
+		start = (uint16_t)strtoull(argv[optind++], 0, 0);
 	if (optind < argc)
-		stop = (uint16_t)strtoul(argv[optind++], 0, 0);
+		stop = (uint16_t)strtoull(argv[optind++], 0, 0);
 
 	/* Find something to talk to */
 	mpsse = MPSSE(SPI0, 1000000, 0);
diff --git a/extra/i2c_pseudo/Documentation.md b/extra/i2c_pseudo/Documentation.md
new file mode 100644
index 0000000000..ebcef6a01e
--- /dev/null
+++ b/extra/i2c_pseudo/Documentation.md
@@ -0,0 +1,279 @@
+# i2c-pseudo driver
+
+Usually I2C adapters are implemented in a kernel driver.  It is also possible to
+implement an adapter in userspace, through the /dev/i2c-pseudo-controller
+interface.  Load module i2c-pseudo for this.
+
+Use cases for this module include:
+
+* Using local I2C device drivers, particularly i2c-dev, with I2C busses on
+  remote systems.  For example, interacting with a Device Under Test (DUT)
+  connected to a Linux host through a debug interface, or interacting with a
+  remote host over a network.
+
+* Implementing I2C device driver tests that are impractical with the i2c-stub
+  module.  For example, when simulating an I2C device where its driver might
+  issue a sequence of reads and writes without interruption, and the value at a
+  certain address must change during the sequence.
+
+This is not intended to replace kernel drivers for actual I2C busses on the
+local host machine.
+
+## Details
+
+Each time /dev/i2c-pseudo-controller is opened, and the correct initialization
+command is written to it (ADAPTER_START), a new I2C adapter is created.  The
+adapter will live until its file descriptor is closed.  Multiple pseudo adapters
+can co-exist simultaneously, controlled by the same or different userspace
+processes.  When an I2C device driver sends an I2C message to a pseudo adapter,
+the message becomes readable from its file descriptor.  If a reply is written
+before the adapter timeout expires, that reply will be sent back to the I2C
+device driver.
+
+Reads and writes are buffered inside i2c-pseudo such that userspace controllers
+may split them up into arbitrarily small chunks.  Multiple commands, or portions
+of multiple commands, may be read or written together.
+
+Blocking I/O is the default.  Non-blocking I/O is supported as well, enabled by
+O_NONBLOCK.  Polling is supported, with or without non-blocking I/O.  A special
+command (ADAPTER_SHUTDOWN) is available to unblock any pollers or blocked
+reads or writes, as a convenience for a multi-threaded or multi-process program
+that wants to exit.
+
+It is safe to access a single controller fd from multiple threads or processes
+concurrently, though it is up to the controller to ensure proper ordering, and
+to ensure that writes for different commands do not get interleaved.  However,
+it is recommended (not required) that controller implementations have only one
+reader thread and one writer thread, which may or may not be the same thread.
+Avoiding multiple readers and multiple writers greatly simplifies controller
+implementation, and there is likely no performance benefit to be gained from
+concurrent reads or concurrent writes due to how i2c-pseudo serializes them
+internally.  After all, on a real I2C bus only one I2C message can be active at
+a time.
+
+Commands are newline-terminated, both those read from the controller device, and
+those written to it.
+
+## Read Commands
+
+The commands that may be read from a pseudo controller device are:
+
+
+---
+
+Read Command
+
+:   `I2C_ADAPTER_NUM <num>`
+
+Example
+
+:   `"I2C_ADAPTER_NUM 5\\n"`
+
+Details
+
+
+---
+
+Read Command
+
+:   `I2C_PSEUDO_ID <num>`
+
+Example
+
+:   `"I2C_PSEUDO_ID 98\\n"`
+
+Details
+
+
+---
+
+Read Command
+
+:   `I2C_BEGIN_XFER`
+
+Example
+
+:   `"I2C_BEGIN_XFER\\n"`
+
+Details
+
+
+---
+
+Read Command
+
+:   `I2C_XFER_REQ <xfer_id> <msg_id> <addr> <flags> <data_len> [<write_byte>[:...]]`
+
+Example
+
+:   `"I2C_XFER_REQ 3 0 0x0070 0x0000 2 AB:9F\\n"`
+
+Example
+
+:   `"I2C_XFER_REQ 3 1 0x0070 0x0001 4\\n"`
+
+Details
+
+
+---
+
+Read Command
+
+:   `I2C_COMMIT_XFER`
+
+Example
+
+:   `"I2C_COMMIT_XFER\\n"`
+
+Details
+
+## Write Commands
+
+The commands that may be written to a pseudo controller device are:
+
+Write Command
+
+:   `SET_ADAPTER_NAME_SUFFIX <suffix>`
+
+Example
+
+:   `"SET_ADAPTER_NAME_SUFFIX My Adapter\\n"`
+
+Details
+
+
+---
+
+Write Command
+
+:   `SET_ADAPTER_TIMEOUT_MS <ms>`
+
+Example
+
+:   `"SET_ADAPTER_TIMEOUT_MS 2000\\n"`
+
+Details
+
+
+---
+
+Write Command
+
+:   `ADAPTER_START`
+
+Example
+
+:   `"ADAPTER_START\\n"`
+
+Details
+
+
+---
+
+Write Command
+
+:   `GET_ADAPTER_NUM`
+
+Example
+
+:   `"GET_ADAPTER_NUM\\n"`
+
+Details
+
+
+---
+
+Write Command
+
+:   `GET_PSEUDO_ID`
+
+Example
+
+:   `"GET_PSEUDO_ID\\n"`
+
+Details
+
+
+---
+
+Write Command
+
+:   `I2C_XFER_REPLY <xfer_id> <msg_id> <addr> <flags> <errno> [<read_byte>[:...]]`
+
+Example
+
+:   `"I2C_XFER_REPLY 3 0 0x0070 0x0000 0\\n"`
+
+Example
+
+:   `"I2C_XFER_REPLY 3 1 0x0070 0x0001 0 0B:29:02:D9\\n"`
+
+Details
+
+
+---
+
+Write Command
+
+:   `ADAPTER_SHUTDOWN`
+
+Example
+
+:   `"ADAPTER_SHUTDOWN\\n"`
+
+Details
+
+## Example userspace controller code
+
+In C, a simple exchange between i2c-pseudo and userspace might look like the
+example below.  Note that for brevity this lacks any error checking and
+handling, which a real pseudo controller implementation should have.
+
+```
+int fd;
+char buf[1<<12];
+
+fd = open("/dev/i2c-pseudo-controller", O_RDWR);
+/* Create the I2C adapter. */
+dprintf(fd, "ADAPTER_START\n");
+
+/*
+ * Pretend this I2C adapter number is 5, and the first I2C xfer sent to it was
+ * from this command (using its i2c-dev interface):
+ * $ i2cset -y 5 0x70 0xC2
+ *
+ * Then this read would place the following into *buf:
+ * "I2C_BEGIN_XFER\n"
+ * "I2C_XFER_REQ 0 0 0x0070 0x0000 1 C2\n"
+ * "I2C_COMMIT_XFER\n"
+ */
+read(fd, buf, sizeof(buf));
+
+/* This reply would allow the i2cset command above to exit successfully. */
+dprintf(fd, "I2C_XFER_REPLY 0 0 0x0070 0x0000 0\n");
+
+/*
+ * Now pretend the next I2C xfer sent to this adapter was from:
+ * $ i2cget -y 5 0x70 0xAB
+ *
+ * Then this read would place the following into *buf:
+ * "I2C_BEGIN_XFER\n"
+ * "I2C_XFER_REQ 1 0 0x0070 0x0000 1 AB\n"
+ * "I2C_XFER_REQ 1 1 0x0070 0x0001 1\n'"
+ * "I2C_COMMIT_XFER\n"
+ */
+read(fd, buf, sizeof(buf));
+
+/*
+ * These replies would allow the i2cget command above to print the following to
+ * stdout and exit successfully:
+ * 0x0b
+ *
+ * Note that it is also valid to write these together in one write().
+ */
+dprintf(fd, "I2C_XFER_REPLY 1 0 0x0070 0x0000 0\n");
+dprintf(fd, "I2C_XFER_REPLY 1 1 0x0070 0x0001 0 0B\n");
+
+/* Destroy the I2C adapter. */
+close(fd);
+```
diff --git a/extra/i2c_pseudo/Documentation.rst b/extra/i2c_pseudo/Documentation.rst
new file mode 100644
index 0000000000..2527eb5337
--- /dev/null
+++ b/extra/i2c_pseudo/Documentation.rst
@@ -0,0 +1,306 @@
+=================
+i2c-pseudo driver
+=================
+
+Usually I2C adapters are implemented in a kernel driver.  It is also possible to
+implement an adapter in userspace, through the /dev/i2c-pseudo-controller
+interface.  Load module i2c-pseudo for this.
+
+Use cases for this module include:
+
+- Using local I2C device drivers, particularly i2c-dev, with I2C busses on
+  remote systems.  For example, interacting with a Device Under Test (DUT)
+  connected to a Linux host through a debug interface, or interacting with a
+  remote host over a network.
+
+- Implementing I2C device driver tests that are impractical with the i2c-stub
+  module.  For example, when simulating an I2C device where its driver might
+  issue a sequence of reads and writes without interruption, and the value at a
+  certain address must change during the sequence.
+
+This is not intended to replace kernel drivers for actual I2C busses on the
+local host machine.
+
+
+Details
+=======
+
+Each time /dev/i2c-pseudo-controller is opened, and the correct initialization
+command is written to it (ADAPTER_START), a new I2C adapter is created.  The
+adapter will live until its file descriptor is closed.  Multiple pseudo adapters
+can co-exist simultaneously, controlled by the same or different userspace
+processes.  When an I2C device driver sends an I2C message to a pseudo adapter,
+the message becomes readable from its file descriptor.  If a reply is written
+before the adapter timeout expires, that reply will be sent back to the I2C
+device driver.
+
+Reads and writes are buffered inside i2c-pseudo such that userspace controllers
+may split them up into arbitrarily small chunks.  Multiple commands, or portions
+of multiple commands, may be read or written together.
+
+Blocking I/O is the default.  Non-blocking I/O is supported as well, enabled by
+O_NONBLOCK.  Polling is supported, with or without non-blocking I/O.  A special
+command (ADAPTER_SHUTDOWN) is available to unblock any pollers or blocked
+reads or writes, as a convenience for a multi-threaded or multi-process program
+that wants to exit.
+
+It is safe to access a single controller fd from multiple threads or processes
+concurrently, though it is up to the controller to ensure proper ordering, and
+to ensure that writes for different commands do not get interleaved.  However,
+it is recommended (not required) that controller implementations have only one
+reader thread and one writer thread, which may or may not be the same thread.
+Avoiding multiple readers and multiple writers greatly simplifies controller
+implementation, and there is likely no performance benefit to be gained from
+concurrent reads or concurrent writes due to how i2c-pseudo serializes them
+internally.  After all, on a real I2C bus only one I2C message can be active at
+a time.
+
+Commands are newline-terminated, both those read from the controller device, and
+those written to it.
+
+
+Read Commands
+=============
+
+The commands that may be read from a pseudo controller device are:
+
+----
+
+:Read Command: ``I2C_ADAPTER_NUM <num>``
+:Example: ``"I2C_ADAPTER_NUM 5\n"``
+:Details:
+  | This is read in response to the GET_ADAPTER_NUM command being written.
+    The number is the I2C adapter number in decimal.  This can only occur after
+    ADAPTER_START, because before that the number is not known and cannot be
+    predicted reliably.
+
+----
+
+:Read Command: ``I2C_PSEUDO_ID <num>``
+:Example: ``"I2C_PSEUDO_ID 98\n"``
+:Details:
+  | This is read in response to the GET_PSEUDO_ID command being written.
+    The number is the pseudo ID in decimal.
+
+----
+
+:Read Command: ``I2C_BEGIN_XFER``
+:Example: ``"I2C_BEGIN_XFER\n"``
+:Details:
+  | This indicates the start of an I2C transaction request, in other words
+    the start of the I2C messages from a single invocation of the I2C adapter's
+    master_xfer() callback.  This can only occur after ADAPTER_START.
+
+----
+
+:Read Command: ``I2C_XFER_REQ <xfer_id> <msg_id> <addr> <flags> <data_len> [<write_byte>[:...]]``
+:Example: ``"I2C_XFER_REQ 3 0 0x0070 0x0000 2 AB:9F\n"``
+:Example: ``"I2C_XFER_REQ 3 1 0x0070 0x0001 4\n"``
+:Details:
+  | This is a single I2C message that a device driver requested be sent on
+    the bus, in other words a single struct i2c_msg from master_xfer() msgs arg.
+  |
+  | The xfer_id is a number representing the whole I2C transaction, thus all
+    I2C_XFER_REQ between a I2C_BEGIN_XFER + I2C_COMMIT_XFER pair share an
+    xfer_id.  The purpose is to ensure replies from the userspace controller are
+    always properly matched to the intended master_xfer() request.  The first
+    transaction has xfer_id 0, and it increases by 1 with each transaction,
+    however it will eventually wrap back to 0 if enough transactions happen
+    during the lifetime of a pseudo adapter.  It is guaranteed to have a large
+    enough maximum value such that there can never be multiple outstanding
+    transactions with the same ID, due to an internal limit in i2c-pseudo that
+    will block master_xfer() calls when the controller is falling behind in its
+    replies.
+  |
+  | The msg_id is a decimal number representing the index of the I2C message
+    within its transaction, in other words the index in master_xfer() \*msgs
+    array arg.  This starts at 0 after each I2C_BEGIN_XFER.  This is guaranteed
+    to not wrap.
+  |
+  | The addr is the hexadecimal I2C address for this I2C message.  The address
+    is right-aligned without any read/write bit.
+  |
+  | The flags are the same bitmask flags used in struct i2c_msg, in hexadecimal
+    form.  Of particular importance to any pseudo controller is the read bit,
+    which is guaranteed to be 0x1 per Linux I2C documentation.
+  |
+  | The data_len is the decimal number of either how many bytes to write that
+    will follow, or how many bytes to read and reply with if this is a read
+    request.
+  |
+  | If this is a read, data_len will be the final field in this command.  If
+    this is a write, data_len will be followed by the given number of
+    colon-separated hexadecimal byte values, in the format shown in the example
+    above.
+
+----
+
+:Read Command: ``I2C_COMMIT_XFER``
+:Example: ``"I2C_COMMIT_XFER\n"``
+:Details:
+  | This indicates the end of an I2C transaction request, in other words the
+    end of the I2C messages from a single invocation of the I2C adapter's
+    master_xfer() callback.  This should be read exactly once after each
+    I2C_BEGIN_XFER, with a varying number of I2C_XFER_REQ between them.
+
+
+Write Commands
+==============
+
+The commands that may be written to a pseudo controller device are:
+
+
+:Write Command: ``SET_ADAPTER_NAME_SUFFIX <suffix>``
+:Example: ``"SET_ADAPTER_NAME_SUFFIX My Adapter\n"``
+:Details:
+  | Sets a suffix to append to the auto-generated I2C adapter name.  Only
+    valid before ADAPTER_START.  A space or other separator character will be
+    placed between the auto-generated name and the suffix, so there is no need
+    to include a leading separator in the suffix.  If the resulting name is too
+    long for the I2C adapter name field, it will be quietly truncated.
+
+----
+
+:Write Command: ``SET_ADAPTER_TIMEOUT_MS <ms>``
+:Example: ``"SET_ADAPTER_TIMEOUT_MS 2000\n"``
+:Details:
+  | Sets the timeout in milliseconds for each I2C transaction, in other words
+    for each master_xfer() reply.  Only valid before ADAPTER_START.  The I2C
+    subsystem will automatically time out transactions based on this setting.
+    Set to 0 to use the I2C subsystem default timeout.  The default timeout for
+    new pseudo adapters where this command has not been used is configurable at
+    i2c-pseudo module load time, and itself has a default independent from the
+    I2C subsystem default.  (If the i2c-pseudo module level default is set to 0,
+    that has the same meaning as here.)
+
+----
+
+:Write Command: ``ADAPTER_START``
+:Example: ``"ADAPTER_START\n"``
+:Details:
+  | Tells i2c-pseudo to actually create the I2C adapter.  Only valid once per
+    open controller fd.
+
+----
+
+:Write Command: ``GET_ADAPTER_NUM``
+:Example: ``"GET_ADAPTER_NUM\n"``
+:Details:
+  | Asks i2c-pseudo for the number assigned to this I2C adapter by the I2C
+    subsystem.  Only valid after ADAPTER_START, because before that the number
+    is not known and cannot be predicted reliably.
+
+----
+
+:Write Command: ``GET_PSEUDO_ID``
+:Example: ``"GET_PSEUDO_ID\n"``
+:Details:
+  | Asks i2c-pseudo for the pseudo ID of this I2C adapter.  The pseudo ID will
+    not be reused for the lifetime of the i2c-pseudo module, unless an internal
+    counter wraps.  I2C clients can use this to track specific instances of
+    pseudo adapters, even when adapter numbers have been reused.
+
+----
+
+:Write Command: ``I2C_XFER_REPLY <xfer_id> <msg_id> <addr> <flags> <errno> [<read_byte>[:...]]``
+:Example: ``"I2C_XFER_REPLY 3 0 0x0070 0x0000 0\n"``
+:Example: ``"I2C_XFER_REPLY 3 1 0x0070 0x0001 0 0B:29:02:D9\n"``
+:Details:
+  | This is how a pseudo controller can reply to I2C_XFER_REQ.  Only valid
+    after I2C_XFER_REQ.  A pseudo controller should write one of these for each
+    I2C_XFER_REQ it reads, including for failures, so that I2C device drivers
+    need not wait for the adapter timeout upon failure (if failure is known
+    sooner).
+  |
+  | The fields in common with I2C_XFER_REQ have their same meanings, and their
+    values are expected to exactly match what was read in the I2C_XFER_REQ
+    command that this is in reply to.
+  |
+  | The errno field is how the pseudo controller indicates success or failure
+    for this I2C message.  A 0 value indicates success.  A non-zero value
+    indicates a failure.  Pseudo controllers are encouraged to use errno values
+    to encode some meaning in a failure response, but that is not a requirement,
+    and the I2C adapter interface does not provide a way to pass per-message
+    errno values to a device driver anyways.
+  |
+  | Pseudo controllers are encouraged to reply in the same order as messages
+    were received, however i2c-pseudo will properly match up out-of-order
+    replies with their original requests.
+
+----
+
+:Write Command: ``ADAPTER_SHUTDOWN``
+:Example: ``"ADAPTER_SHUTDOWN\n"``
+:Details:
+  | This tells i2c-pseudo that the pseudo controller wants to shutdown and
+    intends to close the controller device fd soon.  Use of this is OPTIONAL, it
+    is perfectly valid to close the controller device fd without ever using this
+    command.
+  |
+  | This commands unblocks any blocked controller I/O (reads, writes, or polls),
+    and that is its main purpose.
+  |
+  | Any I2C transactions attempted by a device driver after this command will
+    fail, and will not be passed on to the userspace controller.
+  |
+  | This DOES NOT delete the I2C adapter.  Only closing the fd will do that.
+    That MAY CHANGE in the future, such that this does delete the I2C adapter.
+    (However this will never be required, it will always be okay to simply close
+    the fd.)
+
+
+Example userspace controller code
+=================================
+
+In C, a simple exchange between i2c-pseudo and userspace might look like the
+example below.  Note that for brevity this lacks any error checking and
+handling, which a real pseudo controller implementation should have.
+
+::
+
+  int fd;
+  char buf[1<<12];
+
+  fd = open("/dev/i2c-pseudo-controller", O_RDWR);
+  /* Create the I2C adapter. */
+  dprintf(fd, "ADAPTER_START\n");
+
+  /*
+   * Pretend this I2C adapter number is 5, and the first I2C xfer sent to it was
+   * from this command (using its i2c-dev interface):
+   * $ i2cset -y 5 0x70 0xC2
+   *
+   * Then this read would place the following into *buf:
+   * "I2C_BEGIN_XFER\n"
+   * "I2C_XFER_REQ 0 0 0x0070 0x0000 1 C2\n"
+   * "I2C_COMMIT_XFER\n"
+   */
+  read(fd, buf, sizeof(buf));
+
+  /* This reply would allow the i2cset command above to exit successfully. */
+  dprintf(fd, "I2C_XFER_REPLY 0 0 0x0070 0x0000 0\n");
+
+  /*
+   * Now pretend the next I2C xfer sent to this adapter was from:
+   * $ i2cget -y 5 0x70 0xAB
+   *
+   * Then this read would place the following into *buf:
+   * "I2C_BEGIN_XFER\n"
+   * "I2C_XFER_REQ 1 0 0x0070 0x0000 1 AB\n"
+   * "I2C_XFER_REQ 1 1 0x0070 0x0001 1\n'"
+   * "I2C_COMMIT_XFER\n"
+   */
+  read(fd, buf, sizeof(buf));
+
+  /*
+   * These replies would allow the i2cget command above to print the following to
+   * stdout and exit successfully:
+   * 0x0b
+   *
+   * Note that it is also valid to write these together in one write().
+   */
+  dprintf(fd, "I2C_XFER_REPLY 1 0 0x0070 0x0000 0\n");
+  dprintf(fd, "I2C_XFER_REPLY 1 1 0x0070 0x0001 0 0B\n");
+
+  /* Destroy the I2C adapter. */
+  close(fd);
diff --git a/extra/i2c_pseudo/Makefile b/extra/i2c_pseudo/Makefile
index f7fda6e2de..b53085a970 100644
--- a/extra/i2c_pseudo/Makefile
+++ b/extra/i2c_pseudo/Makefile
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/extra/i2c_pseudo/README b/extra/i2c_pseudo/README
index 96efa062b1..1d1ef75641 100644
--- a/extra/i2c_pseudo/README
+++ b/extra/i2c_pseudo/README
@@ -2,12 +2,16 @@ This directory contains the i2c-pseudo Linux kernel module.
 
 The i2c-pseudo module was written with the intention of being submitted upstream
 in the Linux kernel.  This copy exists because of as 2019-03 this module is not
-yet in the upstream kernel, and even if/when this is included, it may take years
-before making its way to the prepackaged Linux distribution kernels typically
-used by CrOS developers.
+yet in the upstream kernel, and even if/when this is included, it may take a
+long time to get included in prepackaged Linux distribution kernels, especially
+those based on Linux LTS branches.
 
-See Documentation.txt for more information about the module itself.  That file
-is Documentation/i2c/pseudo-controller-interface in the upstream patch.
+See Documentation.rst or Documentation.md for more information about the module
+itself.  The reStructuredText (.rst) file is
+Documentation/i2c/pseudo-controller-interface.rst in the upstream patch.  The
+Markdown file (.md) is generated using rst2md from
+nb2plots (https://github.com/matthew-brett/nb2plots) which uses
+Sphinx (https://www.sphinx-doc.org/).
 
 When servod starts, if the i2c-pseudo module is loaded servod will automatically
 create an I2C pseudo adapter for the Servo I2C bus.  That I2C adapter may then
diff --git a/extra/i2c_pseudo/check_stream_open.sh b/extra/i2c_pseudo/check_stream_open.sh
index da802cb282..70cffd7c73 100755
--- a/extra/i2c_pseudo/check_stream_open.sh
+++ b/extra/i2c_pseudo/check_stream_open.sh
@@ -1,6 +1,6 @@
 #!/bin/sh
 #
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/extra/i2c_pseudo/dkms.conf b/extra/i2c_pseudo/dkms.conf
new file mode 100644
index 0000000000..b846577b35
--- /dev/null
+++ b/extra/i2c_pseudo/dkms.conf
@@ -0,0 +1,15 @@
+# DKMS configuration file for i2c-pseudo.
+#
+# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+PACKAGE_NAME="i2c-pseudo"
+PACKAGE_VERSION="1"
+
+BUILT_MODULE_NAME[0]="${PACKAGE_NAME}"
+MAKE[0]="make -C ${kernel_source_dir} M=${dkms_tree}/${PACKAGE_NAME}/${PACKAGE_VERSION}/build"
+CLEAN="make -C ${kernel_source_dir} M=${dkms_tree}/${PACKAGE_NAME}/${PACKAGE_VERSION}/build clean"
+DEST_MODULE_LOCATION[0]=/extra
+
+AUTOINSTALL=yes
diff --git a/extra/i2c_pseudo/i2c-pseudo.c b/extra/i2c_pseudo/i2c-pseudo.c
index e4f1852cd8..7cb2904322 100644
--- a/extra/i2c_pseudo/i2c-pseudo.c
+++ b/extra/i2c_pseudo/i2c-pseudo.c
@@ -22,55 +22,55 @@
 #include <linux/mutex.h>
 #include <linux/poll.h>
 #include <linux/slab.h>
+#include <linux/stdarg.h>
 #include <linux/string.h>
 #include <linux/time64.h>
 #include <linux/types.h>
 #include <linux/uaccess.h>
 #include <linux/wait.h>
-#include <stdarg.h>
 
 /* Minimum i2cp_limit module parameter value. */
-#define I2CP_ADAPTERS_MIN	0
+#define I2CP_ADAPTERS_MIN 0
 /* Maximum i2cp_limit module parameter value. */
-#define I2CP_ADAPTERS_MAX	256
+#define I2CP_ADAPTERS_MAX 256
 /* Default i2cp_limit module parameter value. */
-#define I2CP_DEFAULT_LIMIT	8
+#define I2CP_DEFAULT_LIMIT 8
 /* Value for alloc_chrdev_region() baseminor arg. */
-#define I2CP_CDEV_BASEMINOR	0
-#define I2CP_TIMEOUT_MS_MIN	0
-#define I2CP_TIMEOUT_MS_MAX	(60 * MSEC_PER_SEC)
-#define I2CP_DEFAULT_TIMEOUT_MS	(3 * MSEC_PER_SEC)
+#define I2CP_CDEV_BASEMINOR 0
+#define I2CP_TIMEOUT_MS_MIN 0
+#define I2CP_TIMEOUT_MS_MAX (60 * MSEC_PER_SEC)
+#define I2CP_DEFAULT_TIMEOUT_MS (3 * MSEC_PER_SEC)
 
 /* Used in struct device.kobj.name field. */
-#define I2CP_DEVICE_NAME	"i2c-pseudo-controller"
+#define I2CP_DEVICE_NAME "i2c-pseudo-controller"
 /* Value for alloc_chrdev_region() name arg. */
-#define I2CP_CHRDEV_NAME	"i2c_pseudo"
+#define I2CP_CHRDEV_NAME "i2c_pseudo"
 /* Value for class_create() name arg. */
-#define I2CP_CLASS_NAME		"i2c-pseudo"
+#define I2CP_CLASS_NAME "i2c-pseudo"
 /* Value for alloc_chrdev_region() count arg.  Should always be 1. */
-#define I2CP_CDEV_COUNT		1
-
-#define I2CP_ADAP_START_CMD		"ADAPTER_START"
-#define I2CP_ADAP_SHUTDOWN_CMD		"ADAPTER_SHUTDOWN"
-#define I2CP_GET_NUMBER_CMD		"GET_ADAPTER_NUM"
-#define I2CP_NUMBER_REPLY_CMD		"I2C_ADAPTER_NUM"
-#define I2CP_GET_PSEUDO_ID_CMD		"GET_PSEUDO_ID"
-#define I2CP_PSEUDO_ID_REPLY_CMD	"I2C_PSEUDO_ID"
-#define I2CP_SET_NAME_SUFFIX_CMD	"SET_ADAPTER_NAME_SUFFIX"
-#define I2CP_SET_TIMEOUT_CMD		"SET_ADAPTER_TIMEOUT_MS"
-#define I2CP_BEGIN_MXFER_REQ_CMD	"I2C_BEGIN_XFER"
-#define I2CP_COMMIT_MXFER_REQ_CMD	"I2C_COMMIT_XFER"
-#define I2CP_MXFER_REQ_CMD		"I2C_XFER_REQ"
-#define I2CP_MXFER_REPLY_CMD		"I2C_XFER_REPLY"
+#define I2CP_CDEV_COUNT 1
+
+#define I2CP_ADAP_START_CMD "ADAPTER_START"
+#define I2CP_ADAP_SHUTDOWN_CMD "ADAPTER_SHUTDOWN"
+#define I2CP_GET_NUMBER_CMD "GET_ADAPTER_NUM"
+#define I2CP_NUMBER_REPLY_CMD "I2C_ADAPTER_NUM"
+#define I2CP_GET_PSEUDO_ID_CMD "GET_PSEUDO_ID"
+#define I2CP_PSEUDO_ID_REPLY_CMD "I2C_PSEUDO_ID"
+#define I2CP_SET_NAME_SUFFIX_CMD "SET_ADAPTER_NAME_SUFFIX"
+#define I2CP_SET_TIMEOUT_CMD "SET_ADAPTER_TIMEOUT_MS"
+#define I2CP_BEGIN_MXFER_REQ_CMD "I2C_BEGIN_XFER"
+#define I2CP_COMMIT_MXFER_REQ_CMD "I2C_COMMIT_XFER"
+#define I2CP_MXFER_REQ_CMD "I2C_XFER_REQ"
+#define I2CP_MXFER_REPLY_CMD "I2C_XFER_REPLY"
 
 /* Maximum size of a controller command. */
-#define I2CP_CTRLR_CMD_LIMIT		255
+#define I2CP_CTRLR_CMD_LIMIT 255
 /* Maximum number of controller read responses to allow enqueued at once. */
-#define I2CP_CTRLR_RSP_QUEUE_LIMIT	256
+#define I2CP_CTRLR_RSP_QUEUE_LIMIT 256
 /* The maximum size of a single controller read response. */
-#define I2CP_MAX_MSG_BUF_SIZE		16384
+#define I2CP_MAX_MSG_BUF_SIZE 16384
 /* Maximum size of a controller read or write. */
-#define I2CP_RW_SIZE_LIMIT		1048576
+#define I2CP_RW_SIZE_LIMIT 1048576
 
 /*
  * Marks the end of a controller command or read response.
@@ -85,11 +85,11 @@
  * because of an assertion that the copy size (1) must match the size of the
  * string literal (2 with its trailing null).
  */
-static const char i2cp_ctrlr_end_char		= '\n';
+static const char i2cp_ctrlr_end_char = '\n';
 /* Separator between I2C message header fields in the controller bytestream. */
-static const char i2cp_ctrlr_header_sep_char	= ' ';
+static const char i2cp_ctrlr_header_sep_char = ' ';
 /* Separator between I2C message data bytes in the controller bytestream. */
-static const char i2cp_ctrlr_data_sep_char	= ':';
+static const char i2cp_ctrlr_data_sep_char = ':';
 
 /*
  * This used instead of strcmp(in_str, other_str) because in_str may have null
@@ -99,10 +99,10 @@ static const char i2cp_ctrlr_data_sep_char	= ':';
 #define STRING_NEQ(in_str, in_size, other_str) \
 	(in_size != strlen(other_str) || memcmp(other_str, in_str, in_size))
 
-#define STR_HELPER(num)		#num
-#define STR(num)		STR_HELPER(num)
+#define STR_HELPER(num) #num
+#define STR(num) STR_HELPER(num)
 
-#define CONST_STRLEN(str)	(sizeof(str) - 1)
+#define CONST_STRLEN(str) (sizeof(str) - 1)
 
 /*
  * The number of pseudo I2C adapters permitted.  This default value can be
@@ -207,8 +207,8 @@ struct i2cp_cmd {
 	 * behavior with duplicate command names is undefined, subject to
 	 * change, and subject to become either a build-time or runtime error.
 	 */
-	char *cmd_string;  /* Must be non-NULL. */
-	size_t cmd_size;  /* Must be non-zero. */
+	char *cmd_string; /* Must be non-NULL. */
+	size_t cmd_size; /* Must be non-zero. */
 
 	/*
 	 * This is called once for each I2C pseudo controller to initialize
@@ -308,7 +308,7 @@ struct i2cp_cmd {
 	 * This callback MUST NOT be NULL.
 	 */
 	int (*header_receiver)(void *data, char *in, size_t in_size,
-		bool non_blocking);
+			       bool non_blocking);
 	/*
 	 * This is called to process write command data, when requested by the
 	 * header_receiver() return value.
@@ -347,7 +347,7 @@ struct i2cp_cmd {
 	 * should be NULL.  Otherwise, this callback MUST NOT be NULL.
 	 */
 	int (*data_receiver)(void *data, char *in, size_t in_size,
-		bool non_blocking);
+			     bool non_blocking);
 	/*
 	 * This is called to complete processing of a command, after it has been
 	 * received in its entirety.
@@ -394,7 +394,7 @@ struct i2cp_cmd {
 	 * This callback may be NULL.
 	 */
 	int (*cmd_completer)(void *data, struct i2cp_controller *pdata,
-		int receive_status, bool non_blocking);
+			     int receive_status, bool non_blocking);
 };
 
 /*
@@ -749,13 +749,13 @@ struct i2cp_rsp_master_xfer {
 	 * Always initialize fields below here to zero.  They are for internal
 	 * use by i2cp_rsp_master_xfer_formatter().
 	 */
-	int num_msgs_done;  /* type of @num field */
+	int num_msgs_done; /* type of @num field */
 	size_t buf_start_plus_one;
 };
 
 /* vanprintf - See anprintf() documentation. */
 static ssize_t vanprintf(char **out, ssize_t max_size, gfp_t gfp,
-	const char *fmt, va_list ap)
+			 const char *fmt, va_list ap)
 {
 	int ret;
 	ssize_t buf_size;
@@ -790,9 +790,9 @@ static ssize_t vanprintf(char **out, ssize_t max_size, gfp_t gfp,
 	*out = buf;
 	return ret;
 
- fail_before_args1:
+fail_before_args1:
 	va_end(args1);
- fail_after_args1:
+fail_after_args1:
 	kfree(buf);
 	if (ret >= 0)
 		ret = -ENOTRECOVERABLE;
@@ -833,7 +833,7 @@ static ssize_t vanprintf(char **out, ssize_t max_size, gfp_t gfp,
  *        a bug.
  */
 static ssize_t anprintf(char **out, ssize_t max_size, gfp_t gfp,
-	const char *fmt, ...)
+			const char *fmt, ...)
 {
 	ssize_t ret;
 	va_list args;
@@ -905,24 +905,26 @@ static ssize_t i2cp_rsp_master_xfer_formatter(void *data, char **out)
 		 * that no bytes were lost in kernel->userspace transmission.
 		 */
 		ret = anprintf(&buf_start, I2CP_MAX_MSG_BUF_SIZE, GFP_KERNEL,
-			"%*s%c%u%c%d%c0x%04X%c0x%04X%c%u",
-			(int)strlen(I2CP_MXFER_REQ_CMD), I2CP_MXFER_REQ_CMD,
-			i2cp_ctrlr_header_sep_char, mxfer_rsp->id,
-			i2cp_ctrlr_header_sep_char, mxfer_rsp->num_msgs_done,
-			i2cp_ctrlr_header_sep_char, i2c_msg->addr,
-			i2cp_ctrlr_header_sep_char, i2c_msg->flags,
-			i2cp_ctrlr_header_sep_char, i2c_msg->len);
+			       "%*s%c%u%c%d%c0x%04X%c0x%04X%c%u",
+			       (int)strlen(I2CP_MXFER_REQ_CMD),
+			       I2CP_MXFER_REQ_CMD, i2cp_ctrlr_header_sep_char,
+			       mxfer_rsp->id, i2cp_ctrlr_header_sep_char,
+			       mxfer_rsp->num_msgs_done,
+			       i2cp_ctrlr_header_sep_char, i2c_msg->addr,
+			       i2cp_ctrlr_header_sep_char, i2c_msg->flags,
+			       i2cp_ctrlr_header_sep_char, i2c_msg->len);
 		if (ret > 0) {
 			*out = buf_start;
 			mxfer_rsp->buf_start_plus_one = 1;
-		/*
-		 * If we have a zero return value, it means the output buffer
-		 * was allocated as size one, containing only a terminating null
-		 * character.  This would be a bug given the requested format
-		 * string above.  Also, formatter functions must not mutate *out
-		 * when returning zero.  So if this matches, free the useless
-		 * buffer and return an error.
-		 */
+			/*
+			 * If we have a zero return value, it means the output
+			 * buffer was allocated as size one, containing only a
+			 * terminating null character.  This would be a bug
+			 * given the requested format string above.  Also,
+			 * formatter functions must not mutate *out when
+			 * returning zero.  So if this matches, free the useless
+			 * buffer and return an error.
+			 */
 		} else if (ret == 0) {
 			ret = -EINVAL;
 			kfree(buf_start);
@@ -932,7 +934,7 @@ static ssize_t i2cp_rsp_master_xfer_formatter(void *data, char **out)
 
 	byte_start = mxfer_rsp->buf_start_plus_one - 1;
 	byte_limit = min_t(size_t, i2c_msg->len - byte_start,
-		I2CP_MAX_MSG_BUF_SIZE / 3);
+			   I2CP_MAX_MSG_BUF_SIZE / 3);
 	/* 3 chars per byte == 2 chars for hex + 1 char for separator */
 	buf_size = byte_limit * 3;
 
@@ -943,34 +945,34 @@ static ssize_t i2cp_rsp_master_xfer_formatter(void *data, char **out)
 	}
 
 	for (buf_pos = buf_start, i = 0; i < byte_limit; ++i) {
-		*buf_pos++ = (i || byte_start) ?
-			i2cp_ctrlr_data_sep_char : i2cp_ctrlr_header_sep_char;
-		buf_pos = hex_byte_pack_upper(
-			buf_pos, i2c_msg->buf[byte_start + i]);
+		*buf_pos++ = (i || byte_start) ? i2cp_ctrlr_data_sep_char :
+						 i2cp_ctrlr_header_sep_char;
+		buf_pos = hex_byte_pack_upper(buf_pos,
+					      i2c_msg->buf[byte_start + i]);
 	}
 	*out = buf_start;
 	ret = buf_size;
 	mxfer_rsp->buf_start_plus_one += i;
 
- maybe_free:
+maybe_free:
 	if (ret <= 0) {
 		if (mxfer_rsp->num_msgs_done >= mxfer_rsp->num) {
 			kfree(mxfer_rsp->msgs);
 			kfree(mxfer_rsp);
-		/*
-		 * If we are returning an error but have not consumed all of
-		 * mxfer_rsp yet, we must not attempt to output any more I2C
-		 * messages from the same mxfer_rsp.  Setting mxfer_rsp->msgs to
-		 * NULL tells the remaining invocations with this mxfer_rsp to
-		 * output nothing.
-		 *
-		 * There can be more invocations with the same mxfer_rsp even
-		 * after returning an error here because
-		 * i2cp_adapter_master_xfer() reuses a single
-		 * struct i2cp_rsp_master_xfer (mxfer_rsp) across multiple
-		 * struct i2cp_rsp (rsp_wrappers), one for each struct i2c_msg
-		 * within the mxfer_rsp.
-		 */
+			/*
+			 * If we are returning an error but have not consumed
+			 * all of mxfer_rsp yet, we must not attempt to output
+			 * any more I2C messages from the same mxfer_rsp.
+			 * Setting mxfer_rsp->msgs to NULL tells the remaining
+			 * invocations with this mxfer_rsp to output nothing.
+			 *
+			 * There can be more invocations with the same mxfer_rsp
+			 * even after returning an error here because
+			 * i2cp_adapter_master_xfer() reuses a single
+			 * struct i2cp_rsp_master_xfer (mxfer_rsp) across
+			 * multiple struct i2cp_rsp (rsp_wrappers), one for each
+			 * struct i2c_msg within the mxfer_rsp.
+			 */
 		} else if (ret < 0) {
 			kfree(mxfer_rsp->msgs);
 			mxfer_rsp->msgs = NULL;
@@ -980,7 +982,7 @@ static ssize_t i2cp_rsp_master_xfer_formatter(void *data, char **out)
 }
 
 static ssize_t i2cp_id_show(struct device *dev, struct device_attribute *attr,
-	char *buf)
+			    char *buf)
 {
 	int ret;
 	struct i2c_adapter *adap;
@@ -1039,9 +1041,10 @@ static void i2cp_cmd_mxfer_reply_data_shutdown(void *data)
 
 	cmd_data = data;
 	mutex_lock(&cmd_data->reply_queue_lock);
-	list_for_each(list_ptr, &cmd_data->reply_queue_head) {
+	list_for_each(list_ptr, &cmd_data->reply_queue_head)
+	{
 		mxfer_reply = list_entry(list_ptr, struct i2cp_cmd_mxfer_reply,
-			reply_queue_item);
+					 reply_queue_item);
 		mutex_lock(&mxfer_reply->lock);
 		complete_all(&mxfer_reply->data_filled);
 		mutex_unlock(&mxfer_reply->lock);
@@ -1059,29 +1062,30 @@ static void i2cp_cmd_mxfer_reply_data_destroyer(void *data)
 	kfree(data);
 }
 
-static inline bool i2cp_mxfer_reply_is_current(
-	struct i2cp_cmd_mxfer_reply_data *cmd_data,
-	struct i2cp_cmd_mxfer_reply *mxfer_reply)
+static inline bool
+i2cp_mxfer_reply_is_current(struct i2cp_cmd_mxfer_reply_data *cmd_data,
+			    struct i2cp_cmd_mxfer_reply *mxfer_reply)
 {
 	int i;
 
 	i = cmd_data->current_msg_idx;
-	return cmd_data->current_id == mxfer_reply->id &&
-		i >= 0 && i < mxfer_reply->num_msgs &&
-		cmd_data->current_addr == mxfer_reply->msgs[i].addr &&
-		cmd_data->current_flags == mxfer_reply->msgs[i].flags;
+	return cmd_data->current_id == mxfer_reply->id && i >= 0 &&
+	       i < mxfer_reply->num_msgs &&
+	       cmd_data->current_addr == mxfer_reply->msgs[i].addr &&
+	       cmd_data->current_flags == mxfer_reply->msgs[i].flags;
 }
 
 /* cmd_data->reply_queue_lock must be held. */
-static inline struct i2cp_cmd_mxfer_reply *i2cp_mxfer_reply_find_current(
-	struct i2cp_cmd_mxfer_reply_data *cmd_data)
+static inline struct i2cp_cmd_mxfer_reply *
+i2cp_mxfer_reply_find_current(struct i2cp_cmd_mxfer_reply_data *cmd_data)
 {
 	struct list_head *list_ptr;
 	struct i2cp_cmd_mxfer_reply *mxfer_reply;
 
-	list_for_each(list_ptr, &cmd_data->reply_queue_head) {
+	list_for_each(list_ptr, &cmd_data->reply_queue_head)
+	{
 		mxfer_reply = list_entry(list_ptr, struct i2cp_cmd_mxfer_reply,
-			reply_queue_item);
+					 reply_queue_item);
 		if (i2cp_mxfer_reply_is_current(cmd_data, mxfer_reply))
 			return mxfer_reply;
 	}
@@ -1089,17 +1093,18 @@ static inline struct i2cp_cmd_mxfer_reply *i2cp_mxfer_reply_find_current(
 }
 
 /* cmd_data->reply_queue_lock must NOT already be held. */
-static inline void i2cp_mxfer_reply_update_current(
-	struct i2cp_cmd_mxfer_reply_data *cmd_data)
+static inline void
+i2cp_mxfer_reply_update_current(struct i2cp_cmd_mxfer_reply_data *cmd_data)
 {
 	mutex_lock(&cmd_data->reply_queue_lock);
-	cmd_data->reply_queue_current_item = i2cp_mxfer_reply_find_current(
-		cmd_data);
+	cmd_data->reply_queue_current_item =
+		i2cp_mxfer_reply_find_current(cmd_data);
 	mutex_unlock(&cmd_data->reply_queue_lock);
 }
 
 static int i2cp_cmd_mxfer_reply_header_receiver(void *data, char *in,
-	size_t in_size, bool non_blocking)
+						size_t in_size,
+						bool non_blocking)
 {
 	int ret, reply_errno = 0;
 	struct i2cp_cmd_mxfer_reply_data *cmd_data;
@@ -1218,10 +1223,10 @@ static int i2cp_cmd_mxfer_reply_header_receiver(void *data, char *in,
 }
 
 static int i2cp_cmd_mxfer_reply_data_receiver(void *data, char *in,
-	size_t in_size, bool non_blocking)
+					      size_t in_size, bool non_blocking)
 {
 	int ret;
-	char u8_hex[3] = {0};
+	char u8_hex[3] = { 0 };
 	struct i2cp_cmd_mxfer_reply_data *cmd_data;
 	struct i2cp_cmd_mxfer_reply *mxfer_reply;
 	struct i2c_msg *i2c_msg;
@@ -1333,7 +1338,7 @@ static int i2cp_cmd_mxfer_reply_data_receiver(void *data, char *in,
 		 * I2C_M_DMA_SAFE bit? Do we ever need to use copy_to_user()?
 		 */
 		ret = kstrtou8(u8_hex, 16,
-			&i2c_msg->buf[cmd_data->current_buf_idx]);
+			       &i2c_msg->buf[cmd_data->current_buf_idx]);
 		if (ret < 0)
 			goto unlock;
 		if (i2c_msg->flags & I2C_M_RECV_LEN)
@@ -1346,13 +1351,15 @@ static int i2cp_cmd_mxfer_reply_data_receiver(void *data, char *in,
 	/* Quietly ignore any bytes beyond the buffer size. */
 	ret = 0;
 
- unlock:
+unlock:
 	mutex_unlock(&mxfer_reply->lock);
 	return ret;
 }
 
 static int i2cp_cmd_mxfer_reply_cmd_completer(void *data,
-	struct i2cp_controller *pdata, int receive_status, bool non_blocking)
+					      struct i2cp_controller *pdata,
+					      int receive_status,
+					      bool non_blocking)
 {
 	int ret;
 	struct i2cp_cmd_mxfer_reply_data *cmd_data;
@@ -1399,7 +1406,7 @@ static int i2cp_cmd_mxfer_reply_cmd_completer(void *data,
 	mutex_unlock(&mxfer_reply->lock);
 	ret = 0;
 
- reset_cmd_data:
+reset_cmd_data:
 	cmd_data->state = I2CP_CMD_MXFER_REPLY_STATE_CMD_NEXT;
 	cmd_data->current_id = 0;
 	cmd_data->current_addr = 0;
@@ -1410,7 +1417,8 @@ static int i2cp_cmd_mxfer_reply_cmd_completer(void *data,
 }
 
 static int i2cp_cmd_adap_start_header_receiver(void *data, char *in,
-	size_t in_size, bool non_blocking)
+					       size_t in_size,
+					       bool non_blocking)
 {
 	/*
 	 * No more header fields or data are expected.  This directs any further
@@ -1421,7 +1429,7 @@ static int i2cp_cmd_adap_start_header_receiver(void *data, char *in,
 }
 
 static int i2cp_cmd_adap_start_data_receiver(void *data, char *in,
-	size_t in_size, bool non_blocking)
+					     size_t in_size, bool non_blocking)
 {
 	/*
 	 * Reaching here means the controller wrote extra data in the command
@@ -1432,7 +1440,9 @@ static int i2cp_cmd_adap_start_data_receiver(void *data, char *in,
 }
 
 static int i2cp_cmd_adap_start_cmd_completer(void *data,
-	struct i2cp_controller *pdata, int receive_status, bool non_blocking)
+					     struct i2cp_controller *pdata,
+					     int receive_status,
+					     bool non_blocking)
 {
 	int ret;
 
@@ -1466,13 +1476,14 @@ static int i2cp_cmd_adap_start_cmd_completer(void *data,
 
 	ret = 0;
 
- unlock:
+unlock:
 	mutex_unlock(&pdata->startstop_lock);
 	return ret;
 }
 
 static int i2cp_cmd_adap_shutdown_header_receiver(void *data, char *in,
-	size_t in_size, bool non_blocking)
+						  size_t in_size,
+						  bool non_blocking)
 {
 	/*
 	 * No more header fields or data are expected.  This directs any further
@@ -1483,7 +1494,8 @@ static int i2cp_cmd_adap_shutdown_header_receiver(void *data, char *in,
 }
 
 static int i2cp_cmd_adap_shutdown_data_receiver(void *data, char *in,
-	size_t in_size, bool non_blocking)
+						size_t in_size,
+						bool non_blocking)
 {
 	/*
 	 * Reaching here means the controller wrote extra data in the command
@@ -1494,7 +1506,9 @@ static int i2cp_cmd_adap_shutdown_data_receiver(void *data, char *in,
 }
 
 static int i2cp_cmd_adap_shutdown_cmd_completer(void *data,
-	struct i2cp_controller *pdata, int receive_status, bool non_blocking)
+						struct i2cp_controller *pdata,
+						int receive_status,
+						bool non_blocking)
 {
 	/* Refuse to shutdown if there were errors processing this command. */
 	if (receive_status)
@@ -1512,7 +1526,8 @@ static int i2cp_cmd_adap_shutdown_cmd_completer(void *data,
 }
 
 static int i2cp_cmd_get_number_header_receiver(void *data, char *in,
-	size_t in_size, bool non_blocking)
+					       size_t in_size,
+					       bool non_blocking)
 {
 	/*
 	 * No more header fields or data are expected.  This directs any further
@@ -1523,7 +1538,7 @@ static int i2cp_cmd_get_number_header_receiver(void *data, char *in,
 }
 
 static int i2cp_cmd_get_number_data_receiver(void *data, char *in,
-	size_t in_size, bool non_blocking)
+					     size_t in_size, bool non_blocking)
 {
 	/*
 	 * Reaching here means the controller wrote extra data in the command
@@ -1534,7 +1549,9 @@ static int i2cp_cmd_get_number_data_receiver(void *data, char *in,
 }
 
 static int i2cp_cmd_get_number_cmd_completer(void *data,
-	struct i2cp_controller *pdata, int receive_status, bool non_blocking)
+					     struct i2cp_controller *pdata,
+					     int receive_status,
+					     bool non_blocking)
 {
 	ssize_t ret;
 	int i2c_adap_nr;
@@ -1572,9 +1589,9 @@ static int i2cp_cmd_get_number_cmd_completer(void *data,
 	}
 
 	ret = anprintf(&rsp_buf->buf, I2CP_MAX_MSG_BUF_SIZE, GFP_KERNEL,
-		"%*s%c%d",
-		(int)strlen(I2CP_NUMBER_REPLY_CMD), I2CP_NUMBER_REPLY_CMD,
-		i2cp_ctrlr_header_sep_char, i2c_adap_nr);
+		       "%*s%c%d", (int)strlen(I2CP_NUMBER_REPLY_CMD),
+		       I2CP_NUMBER_REPLY_CMD, i2cp_ctrlr_header_sep_char,
+		       i2c_adap_nr);
 	if (ret < 0) {
 		goto fail_after_rsp_buf_alloc;
 	} else if (ret == 0) {
@@ -1600,17 +1617,18 @@ static int i2cp_cmd_get_number_cmd_completer(void *data,
 	mutex_unlock(&pdata->read_rsp_queue_lock);
 	return 0;
 
- fail_after_buf_alloc:
+fail_after_buf_alloc:
 	kfree(rsp_buf->buf);
- fail_after_rsp_buf_alloc:
+fail_after_rsp_buf_alloc:
 	kfree(rsp_buf);
- fail_after_rsp_wrapper_alloc:
+fail_after_rsp_wrapper_alloc:
 	kfree(rsp_wrapper);
 	return ret;
 }
 
 static int i2cp_cmd_get_pseudo_id_header_receiver(void *data, char *in,
-	size_t in_size, bool non_blocking)
+						  size_t in_size,
+						  bool non_blocking)
 {
 	/*
 	 * No more header fields or data are expected.  This directs any further
@@ -1621,7 +1639,8 @@ static int i2cp_cmd_get_pseudo_id_header_receiver(void *data, char *in,
 }
 
 static int i2cp_cmd_get_pseudo_id_data_receiver(void *data, char *in,
-	size_t in_size, bool non_blocking)
+						size_t in_size,
+						bool non_blocking)
 {
 	/*
 	 * Reaching here means the controller wrote extra data in the command
@@ -1632,7 +1651,9 @@ static int i2cp_cmd_get_pseudo_id_data_receiver(void *data, char *in,
 }
 
 static int i2cp_cmd_get_pseudo_id_cmd_completer(void *data,
-	struct i2cp_controller *pdata, int receive_status, bool non_blocking)
+						struct i2cp_controller *pdata,
+						int receive_status,
+						bool non_blocking)
 {
 	ssize_t ret;
 	struct i2cp_rsp_buffer *rsp_buf;
@@ -1653,9 +1674,9 @@ static int i2cp_cmd_get_pseudo_id_cmd_completer(void *data,
 	}
 
 	ret = anprintf(&rsp_buf->buf, I2CP_MAX_MSG_BUF_SIZE, GFP_KERNEL,
-		"%*s%c%u",
-		(int)strlen(I2CP_PSEUDO_ID_REPLY_CMD), I2CP_PSEUDO_ID_REPLY_CMD,
-		i2cp_ctrlr_header_sep_char, pdata->id);
+		       "%*s%c%u", (int)strlen(I2CP_PSEUDO_ID_REPLY_CMD),
+		       I2CP_PSEUDO_ID_REPLY_CMD, i2cp_ctrlr_header_sep_char,
+		       pdata->id);
 	if (ret < 0) {
 		goto fail_after_rsp_buf_alloc;
 	} else if (ret == 0) {
@@ -1681,11 +1702,11 @@ static int i2cp_cmd_get_pseudo_id_cmd_completer(void *data,
 	mutex_unlock(&pdata->read_rsp_queue_lock);
 	return 0;
 
- fail_after_buf_alloc:
+fail_after_buf_alloc:
 	kfree(rsp_buf->buf);
- fail_after_rsp_buf_alloc:
+fail_after_rsp_buf_alloc:
 	kfree(rsp_buf);
- fail_after_rsp_wrapper_alloc:
+fail_after_rsp_wrapper_alloc:
 	kfree(rsp_wrapper);
 	return ret;
 }
@@ -1707,13 +1728,15 @@ static void i2cp_cmd_set_name_suffix_data_destroyer(void *data)
 }
 
 static int i2cp_cmd_set_name_suffix_header_receiver(void *data, char *in,
-	size_t in_size, bool non_blocking)
+						    size_t in_size,
+						    bool non_blocking)
 {
 	return 1;
 }
 
 static int i2cp_cmd_set_name_suffix_data_receiver(void *data, char *in,
-	size_t in_size, bool non_blocking)
+						  size_t in_size,
+						  bool non_blocking)
 {
 	size_t remaining;
 	struct i2cp_cmd_set_name_suffix_data *cmd_data;
@@ -1730,7 +1753,9 @@ static int i2cp_cmd_set_name_suffix_data_receiver(void *data, char *in,
 }
 
 static int i2cp_cmd_set_name_suffix_cmd_completer(void *data,
-	struct i2cp_controller *pdata, int receive_status, bool non_blocking)
+						  struct i2cp_controller *pdata,
+						  int receive_status,
+						  bool non_blocking)
 {
 	int ret;
 	struct i2cp_cmd_set_name_suffix_data *cmd_data;
@@ -1753,14 +1778,14 @@ static int i2cp_cmd_set_name_suffix_cmd_completer(void *data,
 
 	cmd_data = data;
 	ret = snprintf(pdata->i2c_adapter.name, sizeof(pdata->i2c_adapter.name),
-		"I2C pseudo ID %u %*s", pdata->id,
-		(int)cmd_data->name_suffix_len, cmd_data->name_suffix);
+		       "I2C pseudo ID %u %*s", pdata->id,
+		       (int)cmd_data->name_suffix_len, cmd_data->name_suffix);
 	if (ret < 0)
 		goto unlock;
 
 	ret = 0;
 
- unlock:
+unlock:
 	mutex_unlock(&pdata->startstop_lock);
 	return ret;
 }
@@ -1782,7 +1807,8 @@ static void i2cp_cmd_set_timeout_data_destroyer(void *data)
 }
 
 static int i2cp_cmd_set_timeout_header_receiver(void *data, char *in,
-	size_t in_size, bool non_blocking)
+						size_t in_size,
+						bool non_blocking)
 {
 	int ret;
 	struct i2cp_cmd_set_timeout_data *cmd_data;
@@ -1802,7 +1828,7 @@ static int i2cp_cmd_set_timeout_header_receiver(void *data, char *in,
 }
 
 static int i2cp_cmd_set_timeout_data_receiver(void *data, char *in,
-	size_t in_size, bool non_blocking)
+					      size_t in_size, bool non_blocking)
 {
 	/*
 	 * Reaching here means the controller wrote extra data in the command
@@ -1812,7 +1838,9 @@ static int i2cp_cmd_set_timeout_data_receiver(void *data, char *in,
 }
 
 static int i2cp_cmd_set_timeout_cmd_completer(void *data,
-	struct i2cp_controller *pdata, int receive_status, bool non_blocking)
+					      struct i2cp_controller *pdata,
+					      int receive_status,
+					      bool non_blocking)
 {
 	int ret;
 	struct i2cp_cmd_set_timeout_data *cmd_data;
@@ -1835,7 +1863,7 @@ static int i2cp_cmd_set_timeout_cmd_completer(void *data,
 
 	cmd_data = data;
 	if (cmd_data->timeout_ms < I2CP_TIMEOUT_MS_MIN ||
-		cmd_data->timeout_ms > I2CP_TIMEOUT_MS_MAX) {
+	    cmd_data->timeout_ms > I2CP_TIMEOUT_MS_MAX) {
 		ret = -ERANGE;
 		goto unlock;
 	}
@@ -1843,7 +1871,7 @@ static int i2cp_cmd_set_timeout_cmd_completer(void *data,
 	pdata->i2c_adapter.timeout = msecs_to_jiffies(cmd_data->timeout_ms);
 	ret = 0;
 
- unlock:
+unlock:
 	mutex_unlock(&pdata->startstop_lock);
 	return ret;
 }
@@ -1914,11 +1942,12 @@ static const struct i2cp_cmd i2cp_cmds[] = {
 static inline bool i2cp_poll_in(struct i2cp_controller *pdata)
 {
 	return pdata->rsp_invalidated || pdata->rsp_buf_remaining != 0 ||
-		!list_empty(&pdata->read_rsp_queue_head);
+	       !list_empty(&pdata->read_rsp_queue_head);
 }
 
 static inline int i2cp_fill_rsp_buf(struct i2cp_rsp *rsp_wrapper,
-	struct i2cp_rsp_buffer *rsp_buf, char *contents, size_t size)
+				    struct i2cp_rsp_buffer *rsp_buf,
+				    char *contents, size_t size)
 {
 	rsp_buf->buf = kmemdup(contents, size, GFP_KERNEL);
 	if (!rsp_buf->buf)
@@ -1929,19 +1958,19 @@ static inline int i2cp_fill_rsp_buf(struct i2cp_rsp *rsp_wrapper,
 	return 0;
 }
 
-#define I2CP_FILL_RSP_BUF_WITH_LITERAL(rsp_wrapper, rsp_buf, str_literal)\
-	i2cp_fill_rsp_buf(\
-		rsp_wrapper, rsp_buf, str_literal, strlen(str_literal))
+#define I2CP_FILL_RSP_BUF_WITH_LITERAL(rsp_wrapper, rsp_buf, str_literal) \
+	i2cp_fill_rsp_buf(rsp_wrapper, rsp_buf, str_literal,              \
+			  strlen(str_literal))
 
 static int i2cp_adapter_master_xfer(struct i2c_adapter *adap,
-	struct i2c_msg *msgs, int num)
+				    struct i2c_msg *msgs, int num)
 {
 	int i, ret = 0;
 	long wait_ret;
 	size_t wrappers_length, wrapper_idx = 0, rsp_bufs_idx = 0;
 	struct i2cp_controller *pdata;
 	struct i2cp_rsp **rsp_wrappers;
-	struct i2cp_rsp_buffer *rsp_bufs[2] = {0};
+	struct i2cp_rsp_buffer *rsp_bufs[2] = { 0 };
 	struct i2cp_rsp_master_xfer *mxfer_rsp;
 	struct i2cp_cmd_mxfer_reply_data *cmd_data;
 	struct i2cp_cmd_mxfer_reply *mxfer_reply;
@@ -1966,8 +1995,8 @@ static int i2cp_adapter_master_xfer(struct i2c_adapter *adap,
 	}
 
 	wrappers_length = (size_t)num + ARRAY_SIZE(rsp_bufs);
-	rsp_wrappers = kcalloc(wrappers_length, sizeof(*rsp_wrappers),
-		GFP_KERNEL);
+	rsp_wrappers =
+		kcalloc(wrappers_length, sizeof(*rsp_wrappers), GFP_KERNEL);
 	if (!rsp_wrappers)
 		return -ENOMEM;
 
@@ -1981,15 +2010,15 @@ static int i2cp_adapter_master_xfer(struct i2c_adapter *adap,
 	init_completion(&mxfer_reply->data_filled);
 	mutex_init(&mxfer_reply->lock);
 
-	mxfer_reply->msgs = kcalloc(num, sizeof(*mxfer_reply->msgs),
-		GFP_KERNEL);
+	mxfer_reply->msgs =
+		kcalloc(num, sizeof(*mxfer_reply->msgs), GFP_KERNEL);
 	if (!mxfer_reply->msgs) {
 		ret = -ENOMEM;
 		goto return_after_mxfer_reply_alloc;
 	}
 
-	mxfer_reply->completed = kcalloc(num, sizeof(*mxfer_reply->completed),
-		GFP_KERNEL);
+	mxfer_reply->completed =
+		kcalloc(num, sizeof(*mxfer_reply->completed), GFP_KERNEL);
 	if (!mxfer_reply->completed) {
 		ret = -ENOMEM;
 		goto return_after_reply_msgs_alloc;
@@ -2034,8 +2063,8 @@ static int i2cp_adapter_master_xfer(struct i2c_adapter *adap,
 		if (msgs[i].flags & I2C_M_RD)
 			continue;
 		/* Copy the data, not the address. */
-		mxfer_rsp->msgs[i].buf = kmemdup(msgs[i].buf, msgs[i].len,
-			GFP_KERNEL);
+		mxfer_rsp->msgs[i].buf =
+			kmemdup(msgs[i].buf, msgs[i].len, GFP_KERNEL);
 		if (!mxfer_rsp->msgs[i].buf) {
 			ret = -ENOMEM;
 			goto fail_after_rsp_msgs_alloc;
@@ -2051,7 +2080,8 @@ static int i2cp_adapter_master_xfer(struct i2c_adapter *adap,
 	}
 
 	ret = I2CP_FILL_RSP_BUF_WITH_LITERAL(rsp_wrappers[wrapper_idx++],
-		rsp_bufs[rsp_bufs_idx++], I2CP_BEGIN_MXFER_REQ_CMD);
+					     rsp_bufs[rsp_bufs_idx++],
+					     I2CP_BEGIN_MXFER_REQ_CMD);
 	if (ret < 0)
 		goto fail_after_individual_rsp_wrappers_alloc;
 
@@ -2062,7 +2092,8 @@ static int i2cp_adapter_master_xfer(struct i2c_adapter *adap,
 	}
 
 	ret = I2CP_FILL_RSP_BUF_WITH_LITERAL(rsp_wrappers[wrapper_idx++],
-		rsp_bufs[rsp_bufs_idx++], I2CP_COMMIT_MXFER_REQ_CMD);
+					     rsp_bufs[rsp_bufs_idx++],
+					     I2CP_COMMIT_MXFER_REQ_CMD);
 	if (ret < 0)
 		goto fail_after_individual_rsp_wrappers_alloc;
 
@@ -2082,12 +2113,12 @@ static int i2cp_adapter_master_xfer(struct i2c_adapter *adap,
 
 	mxfer_reply->id = mxfer_rsp->id;
 	list_add_tail(&mxfer_reply->reply_queue_item,
-		&cmd_data->reply_queue_head);
+		      &cmd_data->reply_queue_head);
 	++cmd_data->reply_queue_length;
 
 	for (i = 0; i < wrappers_length; ++i) {
 		list_add_tail(&rsp_wrappers[i]->queue,
-			&pdata->read_rsp_queue_head);
+			      &pdata->read_rsp_queue_head);
 		complete(&pdata->read_rsp_queued);
 	}
 	pdata->read_rsp_queue_length += wrappers_length;
@@ -2132,31 +2163,31 @@ static int i2cp_adapter_master_xfer(struct i2c_adapter *adap,
 	mutex_unlock(&cmd_data->reply_queue_lock);
 	goto return_after_reply_msgs_alloc;
 
- fail_with_reply_queue_lock:
+fail_with_reply_queue_lock:
 	mutex_unlock(&cmd_data->reply_queue_lock);
- fail_with_read_rsp_queue_lock:
+fail_with_read_rsp_queue_lock:
 	mutex_unlock(&pdata->read_rsp_queue_lock);
- fail_after_individual_rsp_wrappers_alloc:
+fail_after_individual_rsp_wrappers_alloc:
 	for (i = 0; i < wrappers_length; ++i)
 		kfree(rsp_wrappers[i]);
- fail_after_rsp_msgs_alloc:
+fail_after_rsp_msgs_alloc:
 	for (i = 0; i < num; ++i)
 		kfree(mxfer_rsp->msgs[i].buf);
 	kfree(mxfer_rsp->msgs);
- fail_after_mxfer_rsp_alloc:
+fail_after_mxfer_rsp_alloc:
 	kfree(mxfer_rsp);
- fail_after_individual_rsp_bufs_alloc:
+fail_after_individual_rsp_bufs_alloc:
 	for (i = 0; i < ARRAY_SIZE(rsp_bufs); ++i) {
 		kfree(rsp_bufs[i]->buf);
 		kfree(rsp_bufs[i]);
 	}
- return_after_reply_completed_alloc:
+return_after_reply_completed_alloc:
 	kfree(mxfer_reply->completed);
- return_after_reply_msgs_alloc:
+return_after_reply_msgs_alloc:
 	kfree(mxfer_reply->msgs);
- return_after_mxfer_reply_alloc:
+return_after_mxfer_reply_alloc:
 	kfree(mxfer_reply);
- return_after_rsp_wrappers_ptrs_alloc:
+return_after_rsp_wrappers_ptrs_alloc:
 	kfree(rsp_wrappers);
 	return ret;
 }
@@ -2183,9 +2214,8 @@ static const struct i2c_algorithm i2cp_algorithm = {
 
 /* this_pseudo->counters.lock must _not_ be held when calling this. */
 static void i2cp_remove_from_counters(struct i2cp_controller *pdata,
-	struct i2cp_device *this_pseudo)
+				      struct i2cp_device *this_pseudo)
 {
-
 	mutex_lock(&this_pseudo->counters.lock);
 	this_pseudo->counters.all_controllers[pdata->index] = NULL;
 	--this_pseudo->counters.count;
@@ -2290,7 +2320,7 @@ static int i2cp_cdev_open(struct inode *inodep, struct file *filep)
 	pdata->i2c_adapter.timeout = msecs_to_jiffies(i2cp_default_timeout_ms);
 	pdata->i2c_adapter.dev.parent = &this_pseudo->device;
 	ret = snprintf(pdata->i2c_adapter.name, sizeof(pdata->i2c_adapter.name),
-		"I2C pseudo ID %u", pdata->id);
+		       "I2C pseudo ID %u", pdata->id);
 	if (ret < 0)
 		goto fail_after_counters_update;
 
@@ -2298,9 +2328,9 @@ static int i2cp_cdev_open(struct inode *inodep, struct file *filep)
 	filep->private_data = pdata;
 	return 0;
 
- fail_after_counters_update:
+fail_after_counters_update:
 	i2cp_remove_from_counters(pdata, this_pseudo);
- fail_after_cmd_data_created:
+fail_after_cmd_data_created:
 	for (i = 0; i < num_cmd_data_created; ++i)
 		if (i2cp_cmds[i].data_destroyer)
 			i2cp_cmds[i].data_destroyer(pdata->cmd_data[i]);
@@ -2317,7 +2347,7 @@ static int i2cp_cdev_release(struct inode *inodep, struct file *filep)
 
 	pdata = filep->private_data;
 	this_pseudo = container_of(pdata->i2c_adapter.dev.parent,
-		struct i2cp_device, device);
+				   struct i2cp_device, device);
 
 	/*
 	 * The select(2) man page makes it clear that the behavior of pending
@@ -2378,7 +2408,8 @@ static int i2cp_cdev_release(struct inode *inodep, struct file *filep)
 /* The caller must hold pdata->rsp_lock. */
 /* Return value is whether or not to continue in calling loop. */
 static bool i2cp_cdev_read_iteration(char __user **buf, size_t *count,
-	ssize_t *ret, bool non_blocking, struct i2cp_controller *pdata)
+				     ssize_t *ret, bool non_blocking,
+				     struct i2cp_controller *pdata)
 {
 	long wait_ret;
 	ssize_t copy_size;
@@ -2450,9 +2481,9 @@ static bool i2cp_cdev_read_iteration(char __user **buf, size_t *count,
 
 		mutex_lock(&pdata->read_rsp_queue_lock);
 		if (!list_empty(&pdata->read_rsp_queue_head))
-			rsp_wrapper = list_first_entry(
-				&pdata->read_rsp_queue_head,
-				struct i2cp_rsp, queue);
+			rsp_wrapper =
+				list_first_entry(&pdata->read_rsp_queue_head,
+						 struct i2cp_rsp, queue);
 		/*
 		 * Avoid holding pdata->read_rsp_queue_lock while
 		 * executing a formatter, allocating memory, or doing
@@ -2543,7 +2574,7 @@ static bool i2cp_cdev_read_iteration(char __user **buf, size_t *count,
 			return false;
 		}
 
- write_end_char:
+	write_end_char:
 		copy_size = sizeof(i2cp_ctrlr_end_char);
 		/*
 		 * This assertion is just in case someone changes
@@ -2554,8 +2585,7 @@ static bool i2cp_cdev_read_iteration(char __user **buf, size_t *count,
 		 * block, we already know it's greater than zero.
 		 */
 		BUILD_BUG_ON(copy_size != 1);
-		copy_ret = copy_to_user(*buf, &i2cp_ctrlr_end_char,
-			copy_size);
+		copy_ret = copy_to_user(*buf, &i2cp_ctrlr_end_char, copy_size);
 		copy_size -= copy_ret;
 		/*
 		 * After writing to the userspace buffer, we need to
@@ -2571,7 +2601,7 @@ static bool i2cp_cdev_read_iteration(char __user **buf, size_t *count,
 	}
 
 	copy_size = max_t(ssize_t, 0,
-		min_t(ssize_t, *count, pdata->rsp_buf_remaining));
+			  min_t(ssize_t, *count, pdata->rsp_buf_remaining));
 	copy_ret = copy_to_user(*buf, pdata->rsp_buf_pos, copy_size);
 	copy_size -= copy_ret;
 	pdata->rsp_buf_remaining -= copy_size;
@@ -2584,14 +2614,14 @@ static bool i2cp_cdev_read_iteration(char __user **buf, size_t *count,
 		pdata->rsp_buf_pos = NULL;
 	}
 
- /*
-  * When jumping here, the following variables should be set:
-  *   copy_ret: Return value from copy_to_user() (bytes not copied).
-  *   copy_size: The number of bytes successfully copied by copy_to_user().  In
-  *       other words, this should be the size arg to copy_to_user() minus its
-  *       return value (bytes not copied).
-  */
- after_copy_to_user:
+/*
+ * When jumping here, the following variables should be set:
+ *   copy_ret: Return value from copy_to_user() (bytes not copied).
+ *   copy_size: The number of bytes successfully copied by copy_to_user().  In
+ *       other words, this should be the size arg to copy_to_user() minus its
+ *       return value (bytes not copied).
+ */
+after_copy_to_user:
 	*ret += copy_size;
 	*count -= copy_size;
 	*buf += copy_size;
@@ -2600,7 +2630,7 @@ static bool i2cp_cdev_read_iteration(char __user **buf, size_t *count,
 }
 
 static ssize_t i2cp_cdev_read(struct file *filep, char __user *buf,
-		size_t count, loff_t *f_ps)
+			      size_t count, loff_t *f_ps)
 {
 	ssize_t ret = 0;
 	bool non_blocking;
@@ -2638,20 +2668,20 @@ static ssize_t i2cp_cdev_read(struct file *filep, char __user *buf,
 		goto unlock;
 	}
 
-	while (count > 0 && i2cp_cdev_read_iteration(
-		&buf, &count, &ret, non_blocking, pdata))
+	while (count > 0 && i2cp_cdev_read_iteration(&buf, &count, &ret,
+						     non_blocking, pdata))
 		;
 
- unlock:
+unlock:
 	mutex_unlock(&pdata->rsp_lock);
 	return ret;
 }
 
 /* Must be called with pdata->cmd_lock held. */
 /* Must never consume past first i2cp_ctrlr_end_char in @start. */
-static ssize_t i2cp_receive_ctrlr_cmd_header(
-	struct i2cp_controller *pdata, char *start, size_t remaining,
-	bool non_blocking)
+static ssize_t i2cp_receive_ctrlr_cmd_header(struct i2cp_controller *pdata,
+					     char *start, size_t remaining,
+					     bool non_blocking)
 {
 	int found_deliminator_char = 0;
 	int i, cmd_idx;
@@ -2665,7 +2695,7 @@ static ssize_t i2cp_receive_ctrlr_cmd_header(
 		    start[i] == i2cp_ctrlr_header_sep_char) {
 			found_deliminator_char = 1;
 			break;
-	}
+		}
 
 	if (i <= buf_remaining) {
 		copy_size = i;
@@ -2695,7 +2725,7 @@ static ssize_t i2cp_receive_ctrlr_cmd_header(
 		for (i = 0; i < ARRAY_SIZE(i2cp_cmds); ++i)
 			if (i2cp_cmds[i].cmd_size == pdata->cmd_size &&
 			    !memcmp(i2cp_cmds[i].cmd_string, pdata->cmd_buf,
-					pdata->cmd_size))
+				    pdata->cmd_size))
 				break;
 		if (i >= ARRAY_SIZE(i2cp_cmds)) {
 			/* unrecognized command */
@@ -2725,7 +2755,7 @@ static ssize_t i2cp_receive_ctrlr_cmd_header(
 		}
 	}
 
- clear_buffer:
+clear_buffer:
 	pdata->cmd_size = 0;
 	/*
 	 * Ensure a trailing null character for the next header_receiver() or
@@ -2745,7 +2775,8 @@ static ssize_t i2cp_receive_ctrlr_cmd_header(
 /* Must be called with pdata->cmd_lock held. */
 /* Must never consume past first i2cp_ctrlr_end_char in @start. */
 static ssize_t i2cp_receive_ctrlr_cmd_data(struct i2cp_controller *pdata,
-	char *start, size_t remaining, bool non_blocking)
+					   char *start, size_t remaining,
+					   bool non_blocking)
 {
 	ssize_t i, ret, size_holder;
 	int cmd_idx;
@@ -2755,13 +2786,14 @@ static ssize_t i2cp_receive_ctrlr_cmd_data(struct i2cp_controller *pdata,
 	if (cmd_idx < 0)
 		return -EINVAL;
 
-	size_holder = min_t(size_t,
+	size_holder = min_t(
+		size_t,
 		(I2CP_CTRLR_CMD_LIMIT -
 		 (I2CP_CTRLR_CMD_LIMIT % pdata->cmd_data_increment)) -
-		pdata->cmd_size,
-		(((pdata->cmd_size + remaining) /
-		  pdata->cmd_data_increment) *
-		 pdata->cmd_data_increment) - pdata->cmd_size);
+			pdata->cmd_size,
+		(((pdata->cmd_size + remaining) / pdata->cmd_data_increment) *
+		 pdata->cmd_data_increment) -
+			pdata->cmd_size);
 
 	/* Size of current buffer plus all remaining write bytes. */
 	size_holder = pdata->cmd_size + remaining;
@@ -2791,8 +2823,10 @@ static ssize_t i2cp_receive_ctrlr_cmd_data(struct i2cp_controller *pdata,
 	 * buffer to end up with if there were unlimited write bytes
 	 * remaining (computed in-line below).
 	 */
-	size_holder = min_t(ssize_t, size_holder, (I2CP_CTRLR_CMD_LIMIT - (
-		I2CP_CTRLR_CMD_LIMIT % pdata->cmd_data_increment)));
+	size_holder =
+		min_t(ssize_t, size_holder,
+		      (I2CP_CTRLR_CMD_LIMIT -
+		       (I2CP_CTRLR_CMD_LIMIT % pdata->cmd_data_increment)));
 	/*
 	 * Subtract the existing buffer size to get the number of bytes we
 	 * actually want to copy from the remaining write bytes in this loop
@@ -2843,7 +2877,7 @@ static ssize_t i2cp_receive_ctrlr_cmd_data(struct i2cp_controller *pdata,
 
 /* Must be called with pdata->cmd_lock held. */
 static int i2cp_receive_ctrlr_cmd_complete(struct i2cp_controller *pdata,
-	bool non_blocking)
+					   bool non_blocking)
 {
 	int ret = 0, cmd_idx;
 
@@ -2851,8 +2885,9 @@ static int i2cp_receive_ctrlr_cmd_complete(struct i2cp_controller *pdata,
 	cmd_idx = pdata->cmd_idx_plus_one - 1;
 
 	if (cmd_idx >= 0 && i2cp_cmds[cmd_idx].cmd_completer) {
-		ret = i2cp_cmds[cmd_idx].cmd_completer(pdata->cmd_data[cmd_idx],
-			pdata, pdata->cmd_receive_status, non_blocking);
+		ret = i2cp_cmds[cmd_idx].cmd_completer(
+			pdata->cmd_data[cmd_idx], pdata,
+			pdata->cmd_receive_status, non_blocking);
 		if (ret > 0)
 			ret = 0;
 	}
@@ -2872,7 +2907,7 @@ static int i2cp_receive_ctrlr_cmd_complete(struct i2cp_controller *pdata,
 }
 
 static ssize_t i2cp_cdev_write(struct file *filep, const char __user *buf,
-		size_t count, loff_t *f_ps)
+			       size_t count, loff_t *f_ps)
 {
 	ssize_t ret = 0;
 	bool non_blocking;
@@ -2949,8 +2984,8 @@ static ssize_t i2cp_cdev_write(struct file *filep, const char __user *buf,
 		start += ret;
 
 		if (ret > 0 && start[-1] == i2cp_ctrlr_end_char) {
-			ret = i2cp_receive_ctrlr_cmd_complete(
-				pdata, non_blocking);
+			ret = i2cp_receive_ctrlr_cmd_complete(pdata,
+							      non_blocking);
 			if (ret < 0)
 				break;
 		}
@@ -2963,7 +2998,7 @@ static ssize_t i2cp_cdev_write(struct file *filep, const char __user *buf,
 		/* If successful the whole write is always consumed. */
 		ret = count;
 
- free_kbuf:
+free_kbuf:
 	kfree(kbuf);
 	return ret;
 }
@@ -3056,7 +3091,7 @@ static const struct file_operations i2cp_fileops = {
 };
 
 static ssize_t i2cp_limit_show(struct device *dev,
-	struct device_attribute *attr, char *buf)
+			       struct device_attribute *attr, char *buf)
 {
 	int ret;
 
@@ -3075,7 +3110,7 @@ static struct device_attribute i2cp_limit_dev_attr = {
 };
 
 static ssize_t i2cp_count_show(struct device *dev,
-	struct device_attribute *attr, char *buf)
+			       struct device_attribute *attr, char *buf)
 {
 	int count, ret;
 	struct i2cp_device *this_pseudo;
@@ -3138,9 +3173,9 @@ static int __init i2cp_init(void)
 	int ret = -1;
 
 	if (i2cp_limit < I2CP_ADAPTERS_MIN || i2cp_limit > I2CP_ADAPTERS_MAX) {
-		pr_err("%s: i2cp_limit=%u, must be in range ["
-			STR(I2CP_ADAPTERS_MIN) ", " STR(I2CP_ADAPTERS_MAX)
-			"]\n", __func__, i2cp_limit);
+		pr_err("%s: i2cp_limit=%u, must be in range [" STR(
+			       I2CP_ADAPTERS_MIN) ", " STR(I2CP_ADAPTERS_MAX) "]\n",
+		       __func__, i2cp_limit);
 		return -EINVAL;
 	}
 
@@ -3151,7 +3186,7 @@ static int __init i2cp_init(void)
 	i2cp_class->dev_groups = i2cp_device_sysfs_groups;
 
 	ret = alloc_chrdev_region(&i2cp_dev_num, I2CP_CDEV_BASEMINOR,
-		I2CP_CDEV_COUNT, I2CP_CHRDEV_NAME);
+				  I2CP_CDEV_COUNT, I2CP_CHRDEV_NAME);
 	if (ret < 0)
 		goto fail_after_class_create;
 
@@ -3171,8 +3206,9 @@ static int __init i2cp_init(void)
 		goto fail_after_device_init;
 
 	mutex_init(&i2cp_device->counters.lock);
-	i2cp_device->counters.all_controllers = kcalloc(i2cp_limit,
-		sizeof(*i2cp_device->counters.all_controllers), GFP_KERNEL);
+	i2cp_device->counters.all_controllers = kcalloc(
+		i2cp_limit, sizeof(*i2cp_device->counters.all_controllers),
+		GFP_KERNEL);
 	if (!i2cp_device->counters.all_controllers) {
 		ret = -ENOMEM;
 		goto fail_after_device_init;
@@ -3187,11 +3223,11 @@ static int __init i2cp_init(void)
 
 	return 0;
 
- fail_after_device_init:
+fail_after_device_init:
 	put_device(&i2cp_device->device);
- fail_after_chrdev_register:
+fail_after_chrdev_register:
 	unregister_chrdev_region(i2cp_dev_num, I2CP_CDEV_COUNT);
- fail_after_class_create:
+fail_after_class_create:
 	i2c_p_class_destroy();
 	return ret;
 }
diff --git a/extra/i2c_pseudo/install b/extra/i2c_pseudo/install
index e66dcbd719..98e242a17e 100755
--- a/extra/i2c_pseudo/install
+++ b/extra/i2c_pseudo/install
@@ -2,37 +2,52 @@
 #
 # This attempts to build and install the i2c-pseudo Linux kernel module.
 # Installs a udev rule making i2c-pseudo devices read-write by users in plugdev.
+#
+# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
 
 set -e
 cd "$(dirname "$0")"
 
-make clean
-make
-ret=0
-sudo make modules_install || ret="$?"
-
 # Only install udev rule if plugdev group exists.
 if getent group plugdev > /dev/null; then
   sudo cp -iv 50-i2c-pseudo.rules /etc/udev/rules.d/ \
     || echo 1>&2 "NOTICE: Failed to copy udev rules file."
 fi
 
-if [ "$ret" -eq 0 ]; then
-  make clean
-  sudo depmod -a
+if which dkms >/dev/null
+then
+  # Install with DKMS
+  sudo dkms add ./
+  sudo dkms build i2c-pseudo/1
+  sudo dkms install i2c-pseudo/1
   sudo modprobe i2c-pseudo
-  echo "SUCCESS: installed and loaded i2c-pseudo module"
+  echo "SUCCESS: installed i2c-pseudo module with DKMS and loaded"
 else
-  echo 1>&2 "WARNING: make modules_install failed with exit status $ret."
-  echo 1>&2 "The module has not been installed for future reuse."
-  echo 1>&2 "Will still attempt to load the module, using insmod instead of "\
-"modprobe."
+  # Install manually
+  make clean
+  make
   ret=0
-  sudo insmod i2c-pseudo.ko || ret="$?"
-  if [ "$ret" -ne 0 ]; then
+  sudo make modules_install || ret="$?"
+
+  if [ "$ret" -eq 0 ]; then
+    make clean
+    sudo depmod -a
+    sudo modprobe i2c-pseudo
+    echo "SUCCESS: installed and loaded i2c-pseudo module"
+  else
+    echo 1>&2 "WARNING: make modules_install failed with exit status $ret."
+    echo 1>&2 "The module has not been installed for future reuse."
+    echo 1>&2 "Will still attempt to load the module, using insmod instead of "\
+  "modprobe."
+    ret=0
+    sudo insmod i2c-pseudo.ko || ret="$?"
+    if [ "$ret" -ne 0 ]; then
+      make clean
+      exit "$ret"
+    fi
+    echo "PARTIAL SUCCESS: loaded i2c-pseudo module (not installed)"
     make clean
-    exit "$ret"
   fi
-  echo "PARTIAL SUCCESS: loaded i2c-pseudo module (not installed)"
-  make clean
 fi
diff --git a/extra/lightbar/Makefile b/extra/lightbar/Makefile
index ce84428869..628f19ab81 100644
--- a/extra/lightbar/Makefile
+++ b/extra/lightbar/Makefile
@@ -1,4 +1,4 @@
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
+# Copyright 2014 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/extra/lightbar/input.c b/extra/lightbar/input.c
index e6c5485e39..1ddfe2e1b3 100644
--- a/extra/lightbar/input.c
+++ b/extra/lightbar/input.c
@@ -1,19 +1,19 @@
 /*
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
+ * Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
+#include "simulation.h"
+
 #include <stdint.h>
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
 #include <time.h>
 
-#include "simulation.h"
-
 #ifdef HAS_GNU_READLINE
-#include <readline/readline.h>
 #include <readline/history.h>
+#include <readline/readline.h>
 
 char *get_input(const char *prompt)
 {
@@ -32,7 +32,7 @@ char *get_input(const char *prompt)
 	return line;
 }
 
-#else  /* no readline */
+#else /* no readline */
 
 char *get_input(const char *prompt)
 {
diff --git a/extra/lightbar/main.c b/extra/lightbar/main.c
index 7ef3d07c9e..e08aefc114 100644
--- a/extra/lightbar/main.c
+++ b/extra/lightbar/main.c
@@ -1,20 +1,21 @@
 /*
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
+ * Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
+#include "simulation.h"
+
 #include <assert.h>
 #include <errno.h>
 #include <inttypes.h>
-#include <pthread.h>
+#include <stdarg.h>
 #include <stdint.h>
-#include <string.h>
 #include <stdio.h>
 #include <stdlib.h>
-#include <stdarg.h>
+#include <string.h>
 #include <time.h>
 
-#include "simulation.h"
+#include <pthread.h>
 
 static void *(*thread_fns[])(void *) = {
 	entry_windows,
@@ -55,7 +56,7 @@ void *entry_lightbar(void *ptr)
 /* timespec uses nanoseconds */
 #define TS_USEC 1000L
 #define TS_MSEC 1000000L
-#define TS_SEC  1000000000L
+#define TS_SEC 1000000000L
 
 static void timespec_incr(struct timespec *v, time_t secs, long nsecs)
 {
@@ -66,7 +67,6 @@ static void timespec_incr(struct timespec *v, time_t secs, long nsecs)
 	v->tv_nsec %= TS_SEC;
 }
 
-
 static pthread_mutex_t task_mutex = PTHREAD_MUTEX_INITIALIZER;
 static pthread_cond_t task_cond = PTHREAD_COND_INITIALIZER;
 static uint32_t task_event;
@@ -82,8 +82,8 @@ uint32_t task_wait_event(int timeout_us)
 		clock_gettime(CLOCK_REALTIME, &t);
 		timespec_incr(&t, timeout_us / SECOND, timeout_us * TS_USEC);
 
-		if (ETIMEDOUT == pthread_cond_timedwait(&task_cond,
-							&task_mutex, &t))
+		if (ETIMEDOUT ==
+		    pthread_cond_timedwait(&task_cond, &task_mutex, &t))
 			task_event |= TASK_EVENT_TIMER;
 	} else {
 		pthread_cond_wait(&task_cond, &task_mutex);
@@ -95,19 +95,15 @@ uint32_t task_wait_event(int timeout_us)
 	return event;
 }
 
-uint32_t task_set_event(task_id_t tskid,	/* always LIGHTBAR */
-			uint32_t event,
-			int wait_for_reply)	/* always 0 */
+void task_set_event(task_id_t tskid, /* always LIGHTBAR */
+		    uint32_t event)
 {
 	pthread_mutex_lock(&task_mutex);
 	task_event = event;
 	pthread_cond_signal(&task_cond);
 	pthread_mutex_unlock(&task_mutex);
-	return 0;
 }
 
-
-
 /* Stubbed functions */
 
 void cprintf(int zero, const char *fmt, ...)
@@ -148,7 +144,7 @@ timestamp_t get_time(void)
 		clock_gettime(CLOCK_REALTIME, &t_start);
 	clock_gettime(CLOCK_REALTIME, &t);
 	ret.val = (t.tv_sec - t_start.tv_sec) * SECOND +
-		(t.tv_nsec - t_start.tv_nsec) / TS_USEC;
+		  (t.tv_nsec - t_start.tv_nsec) / TS_USEC;
 	return ret;
 }
 
@@ -164,8 +160,7 @@ uint8_t *system_get_jump_tag(uint16_t tag, int *version, int *size)
 }
 
 /* Copied from util/ectool.c */
-int lb_read_params_from_file(const char *filename,
-			     struct lightbar_params_v1 *p)
+int lb_read_params_from_file(const char *filename, struct lightbar_params_v1 *p)
 {
 	FILE *fp;
 	char buf[80];
@@ -177,46 +172,65 @@ int lb_read_params_from_file(const char *filename,
 
 	fp = fopen(filename, "rb");
 	if (!fp) {
-		fprintf(stderr, "Can't open %s: %s\n",
-			filename, strerror(errno));
+		fprintf(stderr, "Can't open %s: %s\n", filename,
+			strerror(errno));
 		return 1;
 	}
 
 	/* We must read the correct number of params from each line */
-#define READ(N) do {							\
-		line++;							\
-		want = (N);						\
-		got = -1;						\
-		if (!fgets(buf, sizeof(buf), fp))			\
-			goto done;					\
-		got = sscanf(buf, "%i %i %i %i",			\
-			     &val[0], &val[1], &val[2], &val[3]);	\
-		if (want != got)					\
-			goto done;					\
+#define READ(N)                                                             \
+	do {                                                                \
+		line++;                                                     \
+		want = (N);                                                 \
+		got = -1;                                                   \
+		if (!fgets(buf, sizeof(buf), fp))                           \
+			goto done;                                          \
+		got = sscanf(buf, "%i %i %i %i", &val[0], &val[1], &val[2], \
+			     &val[3]);                                      \
+		if (want != got)                                            \
+			goto done;                                          \
 	} while (0)
 
-
 	/* Do it */
-	READ(1); p->google_ramp_up = val[0];
-	READ(1); p->google_ramp_down = val[0];
-	READ(1); p->s3s0_ramp_up = val[0];
-	READ(1); p->s0_tick_delay[0] = val[0];
-	READ(1); p->s0_tick_delay[1] = val[0];
-	READ(1); p->s0a_tick_delay[0] = val[0];
-	READ(1); p->s0a_tick_delay[1] = val[0];
-	READ(1); p->s0s3_ramp_down = val[0];
-	READ(1); p->s3_sleep_for = val[0];
-	READ(1); p->s3_ramp_up = val[0];
-	READ(1); p->s3_ramp_down = val[0];
-	READ(1); p->tap_tick_delay = val[0];
-	READ(1); p->tap_gate_delay = val[0];
-	READ(1); p->tap_display_time = val[0];
-
-	READ(1); p->tap_pct_red = val[0];
-	READ(1); p->tap_pct_green = val[0];
-	READ(1); p->tap_seg_min_on = val[0];
-	READ(1); p->tap_seg_max_on = val[0];
-	READ(1); p->tap_seg_osc = val[0];
+	READ(1);
+	p->google_ramp_up = val[0];
+	READ(1);
+	p->google_ramp_down = val[0];
+	READ(1);
+	p->s3s0_ramp_up = val[0];
+	READ(1);
+	p->s0_tick_delay[0] = val[0];
+	READ(1);
+	p->s0_tick_delay[1] = val[0];
+	READ(1);
+	p->s0a_tick_delay[0] = val[0];
+	READ(1);
+	p->s0a_tick_delay[1] = val[0];
+	READ(1);
+	p->s0s3_ramp_down = val[0];
+	READ(1);
+	p->s3_sleep_for = val[0];
+	READ(1);
+	p->s3_ramp_up = val[0];
+	READ(1);
+	p->s3_ramp_down = val[0];
+	READ(1);
+	p->tap_tick_delay = val[0];
+	READ(1);
+	p->tap_gate_delay = val[0];
+	READ(1);
+	p->tap_display_time = val[0];
+
+	READ(1);
+	p->tap_pct_red = val[0];
+	READ(1);
+	p->tap_pct_green = val[0];
+	READ(1);
+	p->tap_seg_min_on = val[0];
+	READ(1);
+	p->tap_seg_max_on = val[0];
+	READ(1);
+	p->tap_seg_osc = val[0];
 	READ(3);
 	p->tap_idx[0] = val[0];
 	p->tap_idx[1] = val[1];
@@ -300,19 +314,18 @@ int lb_load_program(const char *filename, struct lightbar_program *prog)
 
 	fp = fopen(filename, "rb");
 	if (!fp) {
-		fprintf(stderr, "Can't open %s: %s\n",
-			filename, strerror(errno));
+		fprintf(stderr, "Can't open %s: %s\n", filename,
+			strerror(errno));
 		return 1;
 	}
 
 	rc = fseek(fp, 0, SEEK_END);
 	if (rc) {
-		fprintf(stderr, "Couldn't find end of file %s",
-				filename);
+		fprintf(stderr, "Couldn't find end of file %s", filename);
 		fclose(fp);
 		return 1;
 	}
-	rc = (int) ftell(fp);
+	rc = (int)ftell(fp);
 	if (rc > EC_LB_PROG_LEN) {
 		fprintf(stderr, "File %s is too long, aborting\n", filename);
 		fclose(fp);
diff --git a/extra/lightbar/simulation.h b/extra/lightbar/simulation.h
index eb878ed04e..93f0a957c0 100644
--- a/extra/lightbar/simulation.h
+++ b/extra/lightbar/simulation.h
@@ -1,20 +1,21 @@
 /*
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
+ * Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 #ifndef __EXTRA_SIMULATION_H
 #define __EXTRA_SIMULATION_H
 
+#include "lb_common.h"
+#include "lightbar.h"
+
 #include <stdint.h>
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
 #include <time.h>
-#include <unistd.h>
 
-#include "lb_common.h"
-#include "lightbar.h"
+#include <unistd.h>
 
 /* Functions specific to our simulation environment */
 void *entry_windows(void *);
@@ -38,13 +39,12 @@ int fake_consolecmd_lightbar(int argc, char *argv[]);
 #define CONFIG_LIGHTBAR_POWER_RAILS
 #endif
 
-
 /* Stuff that's too interleaved with the rest of the EC to just include */
 
 /* Test an important condition at compile time, not run time */
-#define _BA1_(cond, line) \
-	extern int __build_assertion_ ## line[1 - 2*!(cond)]	\
-	__attribute__ ((unused))
+#define _BA1_(cond, line)                                    \
+	extern int __build_assertion_##line[1 - 2 * !(cond)] \
+		__attribute__((unused))
 #define _BA0_(c, x) _BA1_(c, x)
 #define BUILD_ASSERT(cond) _BA0_(cond, __LINE__)
 
@@ -61,14 +61,14 @@ void cprints(int zero, const char *fmt, ...);
 
 /* Task events */
 #define TASK_EVENT_CUSTOM_BIT(x) BUILD_CHECK_INLINE(BIT(x), BIT(x) & 0x0fffffff)
-#define TASK_EVENT_I2C_IDLE      0x10000000
-#define TASK_EVENT_WAKE          0x20000000
-#define TASK_EVENT_MUTEX         0x40000000
-#define TASK_EVENT_TIMER         0x80000000
+#define TASK_EVENT_I2C_IDLE 0x10000000
+#define TASK_EVENT_WAKE 0x20000000
+#define TASK_EVENT_MUTEX 0x40000000
+#define TASK_EVENT_TIMER 0x80000000
 
 /* Time units in usecs */
-#define MSEC         1000
-#define SECOND    1000000
+#define MSEC 1000
+#define SECOND 1000000
 
 #define TASK_ID_LIGHTBAR 0
 #define CC_LIGHTBAR 0
@@ -97,21 +97,28 @@ struct host_cmd_handler_args {
 
 /* EC functions that we have to provide */
 uint32_t task_wait_event(int timeout_us);
-uint32_t task_set_event(task_id_t tskid, uint32_t event, int wait_for_reply);
+void task_set_event(task_id_t tskid, uint32_t event);
 timestamp_t get_time(void);
 int system_add_jump_tag(uint16_t tag, int version, int size, const void *data);
 uint8_t *system_get_jump_tag(uint16_t tag, int *version, int *size);
 
 /* Export unused static functions to avoid compiler warnings. */
-#define DECLARE_HOOK(X, fn, Y) \
-	void fake_hook_##fn(void) { fn(); }
+#define DECLARE_HOOK(X, fn, Y)    \
+	void fake_hook_##fn(void) \
+	{                         \
+		fn();             \
+	}
 
-#define DECLARE_HOST_COMMAND(X, fn, Y) \
+#define DECLARE_HOST_COMMAND(X, fn, Y)                                       \
 	enum ec_status fake_hostcmd_##fn(struct host_cmd_handler_args *args) \
-	{ return fn(args); }
+	{                                                                    \
+		return fn(args);                                             \
+	}
 
-#define DECLARE_CONSOLE_COMMAND(X, fn, Y...) \
+#define DECLARE_CONSOLE_COMMAND(X, fn, Y...)            \
 	int fake_consolecmd_##X(int argc, char *argv[]) \
-	{ return fn(argc, argv); }
+	{                                               \
+		return fn(argc, argv);                  \
+	}
 
-#endif	/* __EXTRA_SIMULATION_H */
+#endif /* __EXTRA_SIMULATION_H */
diff --git a/extra/lightbar/windows.c b/extra/lightbar/windows.c
index 115074363c..3371cd42f5 100644
--- a/extra/lightbar/windows.c
+++ b/extra/lightbar/windows.c
@@ -1,18 +1,19 @@
 /*
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
+ * Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
+#include "simulation.h"
+
 #include <assert.h>
-#include <pthread.h>
 #include <stdint.h>
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
 #include <time.h>
-#include <xcb/xcb.h>
 
-#include "simulation.h"
+#include <pthread.h>
+#include <xcb/xcb.h>
 
 /*****************************************************************************/
 /* Window drawing stuff */
@@ -42,8 +43,8 @@ void init_windows(void)
 
 	/* Get a colormap */
 	colormap_id = xcb_generate_id(c);
-	xcb_create_colormap(c, XCB_COLORMAP_ALLOC_NONE,
-			    colormap_id, screen->root, screen->root_visual);
+	xcb_create_colormap(c, XCB_COLORMAP_ALLOC_NONE, colormap_id,
+			    screen->root, screen->root_visual);
 
 	/* Create foreground GC */
 	foreground = xcb_generate_id(c);
@@ -57,16 +58,16 @@ void init_windows(void)
 	mask = XCB_CW_BACK_PIXEL | XCB_CW_EVENT_MASK;
 	values[0] = screen->black_pixel;
 	values[1] = XCB_EVENT_MASK_EXPOSURE | XCB_EVENT_MASK_BUTTON_PRESS;
-	xcb_create_window(c,				 /* Connection */
-			  XCB_COPY_FROM_PARENT,		 /* depth */
-			  win,				 /* window Id */
-			  screen->root,			 /* parent window */
-			  0, 0,				 /* x, y */
-			  win_w, win_h,			 /* width, height */
-			  10,				 /* border_width */
+	xcb_create_window(c, /* Connection */
+			  XCB_COPY_FROM_PARENT, /* depth */
+			  win, /* window Id */
+			  screen->root, /* parent window */
+			  0, 0, /* x, y */
+			  win_w, win_h, /* width, height */
+			  10, /* border_width */
 			  XCB_WINDOW_CLASS_INPUT_OUTPUT, /* class */
-			  screen->root_visual,		 /* visual */
-			  mask, values);		 /* masks */
+			  screen->root_visual, /* visual */
+			  mask, values); /* masks */
 
 	/* Map the window on the screen */
 	xcb_map_window(c, win);
@@ -88,10 +89,10 @@ void cleanup(void)
 
 /* xcb likes 16-bit colors */
 uint16_t leds[NUM_LEDS][3] = {
-	{0xffff, 0x0000, 0x0000},
-	{0x0000, 0xffff, 0x0000},
-	{0x0000, 0x0000, 0xffff},
-	{0xffff, 0xffff, 0x0000},
+	{ 0xffff, 0x0000, 0x0000 },
+	{ 0x0000, 0xffff, 0x0000 },
+	{ 0x0000, 0x0000, 0xffff },
+	{ 0xffff, 0xffff, 0x0000 },
 };
 pthread_mutex_t leds_mutex = PTHREAD_MUTEX_INITIALIZER;
 
@@ -101,10 +102,8 @@ void change_gc_color(uint16_t red, uint16_t green, uint16_t blue)
 	uint32_t values[2];
 	xcb_alloc_color_reply_t *reply;
 
-	reply = xcb_alloc_color_reply(c,
-				      xcb_alloc_color(c, colormap_id,
-						      red, green, blue),
-				      NULL);
+	reply = xcb_alloc_color_reply(
+		c, xcb_alloc_color(c, colormap_id, red, green, blue), NULL);
 	assert(reply);
 
 	mask = XCB_GC_FOREGROUND;
@@ -116,8 +115,8 @@ void change_gc_color(uint16_t red, uint16_t green, uint16_t blue)
 void update_window(void)
 {
 	xcb_segment_t segments[] = {
-		{0, 0, win_w, win_h},
-		{0, win_h, win_w, 0},
+		{ 0, 0, win_w, win_h },
+		{ 0, win_h, win_w, 0 },
 	};
 	xcb_rectangle_t rect;
 	int w = win_w / NUM_LEDS;
@@ -135,8 +134,7 @@ void update_window(void)
 			rect.width = w;
 			rect.height = win_h;
 
-			change_gc_color(copyleds[i][0],
-					copyleds[i][1],
+			change_gc_color(copyleds[i][0], copyleds[i][1],
 					copyleds[i][2]);
 
 			xcb_poly_fill_rectangle(c, win, foreground, 1, &rect);
@@ -184,8 +182,6 @@ void setrgb(int led, int red, int green, int blue)
 /*****************************************************************************/
 /* lb_common stubs */
 
-
-
 /* Brightness serves no purpose here. It's automatic on the Chromebook. */
 static int brightness = 0xc0;
 void lb_set_brightness(unsigned int newval)
@@ -238,14 +234,13 @@ void lb_hc_cmd_dump(struct ec_response_lightbar *out)
 	printf("lightbar is %s\n", fake_power ? "on" : "off");
 	memset(out, fake_power, sizeof(*out));
 };
-void lb_hc_cmd_reg(const struct ec_params_lightbar *in) { };
+void lb_hc_cmd_reg(const struct ec_params_lightbar *in){};
 
 int lb_power(int enabled)
 {
 	return fake_power;
 }
 
-
 /*****************************************************************************/
 /* Event handling stuff */
 
@@ -257,7 +252,6 @@ void *entry_windows(void *ptr)
 	int chg = 1;
 
 	while ((e = xcb_wait_for_event(c))) {
-
 		switch (e->response_type & ~0x80) {
 		case XCB_EXPOSE:
 			ev = (xcb_expose_event_t *)e;
diff --git a/extra/rma_reset/Makefile b/extra/rma_reset/Makefile
index 4a640c5b4c..d4644e91c8 100644
--- a/extra/rma_reset/Makefile
+++ b/extra/rma_reset/Makefile
@@ -1,4 +1,4 @@
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -19,7 +19,7 @@ CFLAGS  := -std=gnu99 \
         -Wredundant-decls \
         -Wmissing-declarations
 
-ifeq ($(DEBUG),1)
+ifneq ($(DEBUG),)
 CFLAGS += -g -O0
 else
 CFLAGS += -O3
diff --git a/extra/rma_reset/board.h b/extra/rma_reset/board.h
index f969ad0c56..38e3e7b382 100644
--- a/extra/rma_reset/board.h
+++ b/extra/rma_reset/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/extra/rma_reset/rma_reset.c b/extra/rma_reset/rma_reset.c
index fe1eb5e909..4c2ce76803 100644
--- a/extra/rma_reset/rma_reset.c
+++ b/extra/rma_reset/rma_reset.c
@@ -1,50 +1,49 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "base32.h"
+#include "curve25519.h"
+#include "rma_auth.h"
+#include "sha256.h"
+
 #include <ctype.h>
-#include <endian.h>
 #include <errno.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <time.h>
+
+#include <endian.h>
 #include <fcntl.h>
 #include <getopt.h>
 #include <openssl/bn.h>
 #include <openssl/ec.h>
 #include <openssl/obj_mac.h>
 #include <openssl/rand.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <time.h>
 #include <unistd.h>
 
-#include "rma_auth.h"
-#include "curve25519.h"
-#include "sha256.h"
-#include "base32.h"
-
 #define EC_COORDINATE_SZ 32
 #define EC_PRIV_KEY_SZ 32
 #define EC_P256_UNCOMPRESSED_PUB_KEY_SZ (EC_COORDINATE_SZ * 2 + 1)
-#define EC_P256_COMPRESSED_PUB_KEY_SZ (EC_COORDINATE_SZ  + 1)
+#define EC_P256_COMPRESSED_PUB_KEY_SZ (EC_COORDINATE_SZ + 1)
 
 #define SERVER_ADDRESS \
 	"https://www.google.com/chromeos/partner/console/cr50reset/request"
 
 /* Test server keys for x25519 and p256 curves. */
 static const uint8_t rma_test_server_x25519_public_key[] = {
-	0x03, 0xae, 0x2d, 0x2c, 0x06, 0x23, 0xe0, 0x73,
-	0x0d, 0xd3, 0xb7, 0x92, 0xac, 0x54, 0xc5, 0xfd,
-	0x7e, 0x9c, 0xf0, 0xa8, 0xeb, 0x7e, 0x2a, 0xb5,
-	0xdb, 0xf4, 0x79, 0x5f, 0x8a, 0x0f, 0x28, 0x3f
+	0x03, 0xae, 0x2d, 0x2c, 0x06, 0x23, 0xe0, 0x73, 0x0d, 0xd3, 0xb7,
+	0x92, 0xac, 0x54, 0xc5, 0xfd, 0x7e, 0x9c, 0xf0, 0xa8, 0xeb, 0x7e,
+	0x2a, 0xb5, 0xdb, 0xf4, 0x79, 0x5f, 0x8a, 0x0f, 0x28, 0x3f
 };
 
 static const uint8_t rma_test_server_x25519_private_key[] = {
-	0x47, 0x3b, 0xa5, 0xdb, 0xc4, 0xbb, 0xd6, 0x77,
-	0x20, 0xbd, 0xd8, 0xbd, 0xc8, 0x7a, 0xbb, 0x07,
-	0x03, 0x79, 0xba, 0x7b, 0x52, 0x8c, 0xec, 0xb3,
-	0x4d, 0xaa, 0x69, 0xf5, 0x65, 0xb4, 0x31, 0xad
+	0x47, 0x3b, 0xa5, 0xdb, 0xc4, 0xbb, 0xd6, 0x77, 0x20, 0xbd, 0xd8,
+	0xbd, 0xc8, 0x7a, 0xbb, 0x07, 0x03, 0x79, 0xba, 0x7b, 0x52, 0x8c,
+	0xec, 0xb3, 0x4d, 0xaa, 0x69, 0xf5, 0x65, 0xb4, 0x31, 0xad
 };
 
 #define RMA_TEST_SERVER_X25519_KEY_ID 0x10
@@ -57,10 +56,9 @@ static const uint8_t rma_test_server_x25519_private_key[] = {
  * openssl ec -in key.pem -text -noout
  */
 static const uint8_t rma_test_server_p256_private_key[] = {
-	0x54, 0xb0, 0x82, 0x92, 0x54, 0x92, 0xfc, 0x4a,
-	0xa7, 0x6b, 0xea, 0x8f, 0x30, 0xcc, 0xf7, 0x3d,
-	0xa2, 0xf6, 0xa7, 0xad, 0xf0, 0xec, 0x7d, 0xe9,
-	0x26, 0x75, 0xd1, 0xec, 0xde, 0x20, 0x8f, 0x81
+	0x54, 0xb0, 0x82, 0x92, 0x54, 0x92, 0xfc, 0x4a, 0xa7, 0x6b, 0xea,
+	0x8f, 0x30, 0xcc, 0xf7, 0x3d, 0xa2, 0xf6, 0xa7, 0xad, 0xf0, 0xec,
+	0x7d, 0xe9, 0x26, 0x75, 0xd1, 0xec, 0xde, 0x20, 0x8f, 0x81
 };
 
 /*
@@ -68,15 +66,12 @@ static const uint8_t rma_test_server_p256_private_key[] = {
  * prefix, 65 bytes total.
  */
 static const uint8_t rma_test_server_p256_public_key[] = {
-	0x04, 0xe7, 0xbe, 0x37, 0xaa, 0x68, 0xca, 0xcc,
-	0x68, 0xf4, 0x8c, 0x56, 0x65, 0x5a, 0xcb, 0xf8,
-	0xf4, 0x65, 0x3c, 0xd3, 0xc6, 0x1b, 0xae, 0xd6,
-	0x51, 0x7a, 0xcc, 0x00, 0x8d, 0x59, 0x6d, 0x1b,
-	0x0a, 0x66, 0xe8, 0x68, 0x5e, 0x6a, 0x82, 0x19,
-	0x81, 0x76, 0x84, 0x92, 0x7f, 0x8d, 0xb2, 0xbe,
-	0xf5, 0x39, 0x50, 0xd5, 0xfe, 0xee, 0x00, 0x67,
-	0xcf, 0x40, 0x5f, 0x68, 0x12, 0x83, 0x4f, 0xa4,
-	0x35
+	0x04, 0xe7, 0xbe, 0x37, 0xaa, 0x68, 0xca, 0xcc, 0x68, 0xf4, 0x8c,
+	0x56, 0x65, 0x5a, 0xcb, 0xf8, 0xf4, 0x65, 0x3c, 0xd3, 0xc6, 0x1b,
+	0xae, 0xd6, 0x51, 0x7a, 0xcc, 0x00, 0x8d, 0x59, 0x6d, 0x1b, 0x0a,
+	0x66, 0xe8, 0x68, 0x5e, 0x6a, 0x82, 0x19, 0x81, 0x76, 0x84, 0x92,
+	0x7f, 0x8d, 0xb2, 0xbe, 0xf5, 0x39, 0x50, 0xd5, 0xfe, 0xee, 0x00,
+	0x67, 0xcf, 0x40, 0x5f, 0x68, 0x12, 0x83, 0x4f, 0xa4, 0x35
 };
 
 #define RMA_TEST_SERVER_P256_KEY_ID 0x20
@@ -84,8 +79,8 @@ static const uint8_t rma_test_server_p256_public_key[] = {
 
 /* Default values which can change based on command line arguments. */
 static uint8_t server_key_id = RMA_TEST_SERVER_X25519_KEY_ID;
-static uint8_t board_id[4] = {'Z', 'Z', 'C', 'R'};
-static uint8_t device_id[8] = {'T', 'H', 'X', 1, 1, 3, 8, 0xfe};
+static uint8_t board_id[4] = { 'Z', 'Z', 'C', 'R' };
+static uint8_t device_id[8] = { 'T', 'H', 'X', 1, 1, 3, 8, 0xfe };
 static uint8_t hw_id[20] = "TESTSAMUS1234";
 
 static char challenge[RMA_CHALLENGE_BUF_SIZE];
@@ -95,20 +90,15 @@ static char *progname;
 static char *short_opts = "a:b:c:d:hpk:tw:";
 static const struct option long_opts[] = {
 	/* name    hasarg *flag val */
-	{"auth_code",  1,   NULL, 'a'},
-	{"board_id",   1,   NULL, 'b'},
-	{"challenge",  1,   NULL, 'c'},
-	{"device_id",  1,   NULL, 'd'},
-	{"help",       0,   NULL, 'h'},
-	{"hw_id",      1,   NULL, 'w'},
-	{"key_id",     1,   NULL, 'k'},
-	{"p256",       0,   NULL, 'p'},
-	{"test",       0,   NULL, 't'},
-	{},
+	{ "auth_code", 1, NULL, 'a' }, { "board_id", 1, NULL, 'b' },
+	{ "challenge", 1, NULL, 'c' }, { "device_id", 1, NULL, 'd' },
+	{ "help", 0, NULL, 'h' },      { "hw_id", 1, NULL, 'w' },
+	{ "key_id", 1, NULL, 'k' },    { "p256", 0, NULL, 'p' },
+	{ "test", 0, NULL, 't' },      {},
 };
 
 void panic_assert_fail(const char *fname, int linenum);
-void rand_bytes(void *buffer, size_t len);
+void trng_rand_bytes(void *buffer, size_t len);
 int safe_memcmp(const void *s1, const void *s2, size_t size);
 
 void panic_assert_fail(const char *fname, int linenum)
@@ -131,7 +121,7 @@ int safe_memcmp(const void *s1, const void *s2, size_t size)
 	return result != 0;
 }
 
-void rand_bytes(void *buffer, size_t len)
+void trng_rand_bytes(void *buffer, size_t len)
 {
 	RAND_bytes(buffer, len);
 }
@@ -173,8 +163,8 @@ static void p256_key_and_secret_seed(uint8_t pub_key[32],
 
 		/* Extract public key into an octal array. */
 		EC_POINT_point2oct(group, EC_KEY_get0_public_key(key),
-				   POINT_CONVERSION_UNCOMPRESSED,
-				   buf, sizeof(buf), NULL);
+				   POINT_CONVERSION_UNCOMPRESSED, buf,
+				   sizeof(buf), NULL);
 
 		/* If Y coordinate is an odd value, we are done. */
 	} while (!(buf[sizeof(buf) - 1] & 1));
@@ -195,8 +185,8 @@ static void p256_key_and_secret_seed(uint8_t pub_key[32],
 	secret_point = EC_POINT_new(group);
 
 	/* Multiply server public key by our private key. */
-	EC_POINT_mul(group, secret_point, 0, pub,
-		     EC_KEY_get0_private_key(key), 0);
+	EC_POINT_mul(group, secret_point, 0, pub, EC_KEY_get0_private_key(key),
+		     0);
 
 	/* Pull the result back into the octal buffer. */
 	EC_POINT_point2oct(group, secret_point, POINT_CONVERSION_UNCOMPRESSED,
@@ -252,9 +242,8 @@ static void p256_calculate_secret(uint8_t secret[32],
 	secret_point = EC_POINT_new(group);
 
 	/* Multiply client's point by our private key. */
-	EC_POINT_mul(group, secret_point, 0,
-		     EC_KEY_get0_public_key(key),
-		     priv, 0);
+	EC_POINT_mul(group, secret_point, 0, EC_KEY_get0_public_key(key), priv,
+		     0);
 
 	/* Pull the result back into the octal buffer. */
 	EC_POINT_point2oct(group, secret_point, POINT_CONVERSION_UNCOMPRESSED,
@@ -274,7 +263,7 @@ static int rma_server_side(const char *generated_challenge)
 
 	/* Convert the challenge back into binary */
 	if (base32_decode(cptr, 8 * sizeof(c), generated_challenge, 9) !=
-		8 * sizeof(c)) {
+	    8 * sizeof(c)) {
 		printf("Error decoding challenge\n");
 		return -1;
 	}
@@ -311,8 +300,8 @@ static int rma_server_side(const char *generated_challenge)
 	 * and DeviceID.
 	 */
 	hmac_SHA256(hmac, secret, sizeof(secret), cptr + 1, sizeof(c) - 1);
-	if (base32_encode(authcode, RMA_AUTHCODE_BUF_SIZE,
-			  hmac, RMA_AUTHCODE_CHARS * 5, 0)) {
+	if (base32_encode(authcode, RMA_AUTHCODE_BUF_SIZE, hmac,
+			  RMA_AUTHCODE_CHARS * 5, 0)) {
 		printf("Error encoding auth code\n");
 		return -1;
 	}
@@ -323,7 +312,7 @@ static int rma_server_side(const char *generated_challenge)
 
 static int rma_create_test_challenge(int p256_mode)
 {
-	uint8_t temp[32];   /* Private key or HMAC */
+	uint8_t temp[32]; /* Private key or HMAC */
 	uint8_t secret_seed[32];
 	struct rma_challenge c;
 	uint8_t *cptr = (uint8_t *)&c;
@@ -334,8 +323,8 @@ static int rma_create_test_challenge(int p256_mode)
 	memset(authcode, 0, sizeof(authcode));
 
 	memset(&c, 0, sizeof(c));
-	c.version_key_id = RMA_CHALLENGE_VKID_BYTE(
-		RMA_CHALLENGE_VERSION, server_key_id);
+	c.version_key_id =
+		RMA_CHALLENGE_VKID_BYTE(RMA_CHALLENGE_VERSION, server_key_id);
 
 	memcpy(&bid, board_id, sizeof(bid));
 	bid = be32toh(bid);
@@ -361,8 +350,8 @@ static int rma_create_test_challenge(int p256_mode)
 	 * and DeviceID.  Those are all in the right order in the challenge
 	 * struct, after the version/key id byte.
 	 */
-	hmac_SHA256(temp, secret_seed, sizeof(secret_seed),
-		    cptr + 1, sizeof(c) - 1);
+	hmac_SHA256(temp, secret_seed, sizeof(secret_seed), cptr + 1,
+		    sizeof(c) - 1);
 	if (base32_encode(authcode, sizeof(authcode), temp,
 			  RMA_AUTHCODE_CHARS * 5, 0))
 		return 1;
@@ -382,7 +371,8 @@ static void dump_key(const char *title, const uint8_t *key, size_t key_size)
 
 	printf("\n\n\%s\n", title);
 	for (i = 0; i < key_size; i++)
-		printf("%02x%c", key[i], ((i + 1) % bytes_per_line) ? ' ':'\n');
+		printf("%02x%c", key[i],
+		       ((i + 1) % bytes_per_line) ? ' ' : '\n');
 
 	if (i % bytes_per_line)
 		printf("\n");
@@ -453,25 +443,26 @@ static void usage(void)
 	       "--device_id <arg> --hw_id <arg> |\n"
 	       "                           --auth_code <arg> |\n"
 	       "                           --challenge <arg>\n"
-		"\n"
-		"This is used to generate the cr50 or server responses for rma "
-		"open.\n"
-		"The cr50 side can be used to generate a challenge response "
-		"and sends authoriztion code to reset device.\n"
-		"The server side can generate an authcode from cr50's "
-		"rma challenge.\n"
-		"\n"
-		"  -c,--challenge    The challenge generated by cr50\n"
-		"  -k,--key_id       Index of the server private key\n"
-		"  -b,--board_id     BoardID type field\n"
-		"  -d,--device_id    Device-unique identifier\n"
-		"  -a,--auth_code    Reset authorization code\n"
-		"  -w,--hw_id        Hardware id\n"
-		"  -h,--help         Show this message\n"
-		"  -p,--p256         Use prime256v1 curve instead of x25519\n"
-		"  -t,--test         "
-			"Generate challenge using default test inputs\n"
-	       "\n", progname);
+	       "\n"
+	       "This is used to generate the cr50 or server responses for rma "
+	       "open.\n"
+	       "The cr50 side can be used to generate a challenge response "
+	       "and sends authoriztion code to reset device.\n"
+	       "The server side can generate an authcode from cr50's "
+	       "rma challenge.\n"
+	       "\n"
+	       "  -c,--challenge    The challenge generated by cr50\n"
+	       "  -k,--key_id       Index of the server private key\n"
+	       "  -b,--board_id     BoardID type field\n"
+	       "  -d,--device_id    Device-unique identifier\n"
+	       "  -a,--auth_code    Reset authorization code\n"
+	       "  -w,--hw_id        Hardware id\n"
+	       "  -h,--help         Show this message\n"
+	       "  -p,--p256         Use prime256v1 curve instead of x25519\n"
+	       "  -t,--test         "
+	       "Generate challenge using default test inputs\n"
+	       "\n",
+	       progname);
 }
 
 static int atoh(char *v)
@@ -498,7 +489,7 @@ static int set_server_key_id(char *id)
 		return 1;
 
 	/* verify digits */
-	if (!isxdigit(*id) || !isxdigit(*(id+1)))
+	if (!isxdigit(*id) || !isxdigit(*(id + 1)))
 		return 1;
 
 	server_key_id = atoh(id);
@@ -520,7 +511,7 @@ static int set_board_id(char *id)
 			return 1;
 
 	for (i = 0; i < 4; i++)
-		board_id[i] = atoh((id + (i*2)));
+		board_id[i] = atoh((id + (i * 2)));
 
 	return 0;
 }
@@ -538,7 +529,7 @@ static int set_device_id(char *id)
 			return 1;
 
 	for (i = 0; i < 8; i++)
-		device_id[i] = atoh((id + (i*2)));
+		device_id[i] = atoh((id + (i * 2)));
 
 	return 0;
 }
@@ -635,14 +626,14 @@ int main(int argc, char **argv)
 		case 'h':
 			usage();
 			return 0;
-		case 0:                         /* auto-handled option */
+		case 0: /* auto-handled option */
 			break;
 		case '?':
 			if (optopt)
 				printf("Unrecognized option: -%c\n", optopt);
 			else
 				printf("Unrecognized option: %s\n",
-							argv[optind - 1]);
+				       argv[optind - 1]);
 			break;
 		case ':':
 			printf("Missing argument to %s\n", argv[optind - 1]);
@@ -683,7 +674,7 @@ int main(int argc, char **argv)
 			if (!k_flag || !b_flag || !d_flag || !w_flag) {
 				printf("server-side: Flag -c is mandatory\n");
 				printf("cr50-side: Flags -k, -b, -d, and -w "
-					"are mandatory\n");
+				       "are mandatory\n");
 				return 1;
 			}
 		}
diff --git a/extra/sps_errs/Makefile b/extra/sps_errs/Makefile
index 12224ad803..b25eecbdab 100644
--- a/extra/sps_errs/Makefile
+++ b/extra/sps_errs/Makefile
@@ -1,4 +1,4 @@
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/extra/sps_errs/prog.c b/extra/sps_errs/prog.c
index b649199068..40621f0843 100644
--- a/extra/sps_errs/prog.c
+++ b/extra/sps_errs/prog.c
@@ -1,18 +1,18 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "ec_commands.h"
+#include "mpsse.h"
+
 #include <signal.h>
 #include <stdint.h>
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
-#include <unistd.h>
-
-#include "mpsse.h"
 
-#include "ec_commands.h"
+#include <unistd.h>
 
 static int opt_verbose;
 static size_t stop_after = -1;
@@ -23,7 +23,7 @@ static struct mpsse_context *mpsse;
 /* enum ec_status meaning */
 static const char *ec_strerr(enum ec_status r)
 {
-	static const char * const strs[] = {
+	static const char *const strs[] = {
 		"SUCCESS",
 		"INVALID_COMMAND",
 		"ERROR",
@@ -48,7 +48,6 @@ static const char *ec_strerr(enum ec_status r)
 	return "<undefined result>";
 };
 
-
 /****************************************************************************
  * Debugging output
  */
@@ -65,8 +64,7 @@ static void showline(uint8_t *buf, int len)
 		printf("   ");
 	printf("    ");
 	for (i = 0; i < len; i++)
-		printf("%c",
-		       (buf[i] >= ' ' && buf[i] <= '~') ? buf[i] : '.');
+		printf("%c", (buf[i] >= ' ' && buf[i] <= '~') ? buf[i] : '.');
 	printf("\n");
 }
 
@@ -105,8 +103,8 @@ static uint8_t txbuf[128];
  * Load the output buffer with a proto v3 request (header, then data, with
  * checksum correct in header).
  */
-static size_t prepare_request(int cmd, int version,
-			      const uint8_t *data, size_t data_len)
+static size_t prepare_request(int cmd, int version, const uint8_t *data,
+			      size_t data_len)
 {
 	struct ec_host_request *request;
 	size_t i, total_len;
@@ -114,8 +112,8 @@ static size_t prepare_request(int cmd, int version,
 
 	total_len = sizeof(*request) + data_len;
 	if (total_len > sizeof(txbuf)) {
-		printf("Request too large (%zd > %zd)\n",
-		       total_len, sizeof(txbuf));
+		printf("Request too large (%zd > %zd)\n", total_len,
+		       sizeof(txbuf));
 		return -1;
 	}
 
@@ -139,7 +137,6 @@ static size_t prepare_request(int cmd, int version,
 	return total_len;
 }
 
-
 /* Timeout flag, so we don't wait forever */
 static int timedout;
 static void alarm_handler(int sig)
@@ -151,11 +148,8 @@ static void alarm_handler(int sig)
  * Send command, wait for result. Return zero if communication succeeded; check
  * response to see if the EC liked the command.
  */
-static int send_cmd(int cmd, int version,
-		    void *outbuf,
-		    size_t outsize,
-		    struct ec_host_response *hdr,
-		    void *bodydest,
+static int send_cmd(int cmd, int version, void *outbuf, size_t outsize,
+		    struct ec_host_response *hdr, void *bodydest,
 		    size_t bodylen)
 {
 	uint8_t *tptr, *hptr = 0, *bptr = 0;
@@ -166,15 +160,13 @@ static int send_cmd(int cmd, int version,
 	size_t bytes_left = stop_after;
 	size_t bytes_sent = 0;
 
-
 	/* Load up the txbuf with the stuff to send */
 	len = prepare_request(cmd, version, outbuf, outsize);
 	if (len < 0)
 		return -1;
 
 	if (MPSSE_OK != Start(mpsse)) {
-		fprintf(stderr, "Start failed: %s\n",
-			ErrorString(mpsse));
+		fprintf(stderr, "Start failed: %s\n", ErrorString(mpsse));
 		return -1;
 	}
 
@@ -189,8 +181,7 @@ static int send_cmd(int cmd, int version,
 	bytes_left -= len;
 	bytes_sent += len;
 	if (!tptr) {
-		fprintf(stderr, "Transfer failed: %s\n",
-			ErrorString(mpsse));
+		fprintf(stderr, "Transfer failed: %s\n", ErrorString(mpsse));
 		goto out;
 	}
 
@@ -278,8 +269,7 @@ static int send_cmd(int cmd, int version,
 	bytes_left -= len;
 	bytes_sent += len;
 	if (!hptr) {
-		fprintf(stderr, "Read failed: %s\n",
-			ErrorString(mpsse));
+		fprintf(stderr, "Read failed: %s\n", ErrorString(mpsse));
 		goto out;
 	}
 	show("Header(%d):\n", hptr, sizeof(*hdr));
@@ -288,14 +278,12 @@ static int send_cmd(int cmd, int version,
 	/* Check the header */
 	if (hdr->struct_version != EC_HOST_RESPONSE_VERSION) {
 		printf("HEY: response version %d (should be %d)\n",
-		       hdr->struct_version,
-		       EC_HOST_RESPONSE_VERSION);
+		       hdr->struct_version, EC_HOST_RESPONSE_VERSION);
 		goto out;
 	}
 
 	if (hdr->data_len > bodylen) {
-		printf("HEY: response data_len %d is > %zd\n",
-		       hdr->data_len,
+		printf("HEY: response data_len %d is > %zd\n", hdr->data_len,
 		       bodylen);
 		goto out;
 	}
@@ -341,15 +329,13 @@ static int send_cmd(int cmd, int version,
 		free(bptr);
 
 	if (MPSSE_OK != Stop(mpsse)) {
-		fprintf(stderr, "Stop failed: %s\n",
-			ErrorString(mpsse));
+		fprintf(stderr, "Stop failed: %s\n", ErrorString(mpsse));
 		return -1;
 	}
 
 	return 0;
 }
 
-
 /****************************************************************************/
 
 /**
@@ -372,10 +358,7 @@ static int hello(void)
 	p.in_data = 0xa5a5a5a5;
 	expected = p.in_data + 0x01020304;
 
-	retval = send_cmd(EC_CMD_HELLO, 0,
-			  &p, sizeof(p),
-			  &resp,
-			  &r, sizeof(r));
+	retval = send_cmd(EC_CMD_HELLO, 0, &p, sizeof(p), &resp, &r, sizeof(r));
 
 	if (retval) {
 		printf("Transmission error\n");
@@ -383,14 +366,13 @@ static int hello(void)
 	}
 
 	if (EC_RES_SUCCESS != resp.result) {
-		printf("EC result is %d: %s\n",
-		       resp.result, ec_strerr(resp.result));
+		printf("EC result is %d: %s\n", resp.result,
+		       ec_strerr(resp.result));
 		return -1;
 	}
 
-	printf("sent %08x, expected %08x, got %08x => %s\n",
-	       p.in_data, expected, r.out_data,
-	       expected == r.out_data ? "yay" : "boo");
+	printf("sent %08x, expected %08x, got %08x => %s\n", p.in_data,
+	       expected, r.out_data, expected == r.out_data ? "yay" : "boo");
 
 	return !(expected == r.out_data);
 }
diff --git a/extra/stack_analyzer/README.md b/extra/stack_analyzer/README.md
index bead6d10b4..d1c77b57d2 100644
--- a/extra/stack_analyzer/README.md
+++ b/extra/stack_analyzer/README.md
@@ -1,27 +1,22 @@
-Stack Size Analysis Tool for EC Firmware
-========================================
+# Stack Size Analysis Tool for EC Firmware
 
 This tool does static analysis on EC firmwares to get the maximum stack usage of
 each function and task. The maximum stack usage of a function includes the stack
 used by itself and the functions it calls.
 
-Usage
------
+## Usage
 
 Make sure the firmware of your target board has been built.
 
-In `src/platform/ec`, run
-```
-make BOARD=${BOARD} SECTION=${SECTION} ANNOTATION=${ANNOTATION} analyzestack
-```
-The `${SECTION}` can be `RO` or `RW`. The `${ANNOTATION}` is a optional
-annotation file, see the example_annotation.yaml, by default,
-board/$BOARD/analyzestack.yaml is used.
+In `src/platform/ec`, run `make BOARD=${BOARD} SECTION=${SECTION}
+ANNOTATION=${ANNOTATION} analyzestack` The `${SECTION}` can be `RO` or `RW`. The
+`${ANNOTATION}` is a optional annotation file, see the example_annotation.yaml,
+by default, board/$BOARD/analyzestack.yaml is used.
 
-Output
-------
+## Output
 
 For each task, it will output the result like below,
+
 ```
 Task: PD_C1, Max size: 1156 (932 + 224), Allocated size: 640
 Call Trace:
@@ -34,9 +29,12 @@ Call Trace:
     pd_send_request_msg.lto_priv.263 (56) [common/usb_pd_protocol.c:653] 1009a0b4
         -> pd_send_request_msg.lto_priv.263[common/usb_pd_protocol.c:712] 1009a22e0
 ```
-The `pd_task` uses 160 bytes on the stack and calls `pd_send_request_msg.lto_priv.263`.
+
+The `pd_task` uses 160 bytes on the stack and calls
+`pd_send_request_msg.lto_priv.263`.
 
 The callsites to the next function will be shown like below,
+
 ```
 -> pd_task[common/usb_pd_protocol.c:1808] 1008ac8a
    - handle_request[common/usb_pd_protocol.c:1191]
@@ -44,37 +42,42 @@ The callsites to the next function will be shown like below,
 -> pd_task[common/usb_pd_protocol.c:2672] 1008c222
 -> [annotation]
 ```
-This means one callsite to the next function is at `usb_pd_protocol.c:798`,
-but it is inlined to the current function and you can follow the trace:
+
+This means one callsite to the next function is at `usb_pd_protocol.c:798`, but
+it is inlined to the current function and you can follow the trace:
 `usb_pd_protocol.c:1808 -> usb_pd_protocol.c:1191 -> usb_pd_protocol.c:798` to
 find the callsite. The second callsite is at `usb_pd_protocol.c:2672`. And the
 third one is added by annotation.
 
 The unresolved indirect callsites have the similar format to the above.
 
-Annotating Indirect Call
-------------------------
+## Annotating Indirect Call
 
 To annotate an indirect call like this,
+
 ```
 Unresolved indirect callsites:
     pd_transmit
         -> pd_transmit[common/usb_pd_protocol.c:407] 802c9c8
            - tcpm_transmit[driver/tcpm/tcpm.h:142]
 ```
-It is an indirect call in the `tcpm_transmit`, which is inlined to the `pd_transmit`.
+
+It is an indirect call in the `tcpm_transmit`, which is inlined to the
+`pd_transmit`.
 
 You can add a annotation like the below to eliminate it.
+
 ```
 add:
   tcpm_transmit[driver/tcpm/tcpm.h:142]:
   - anx74xx_tcpm_transmit
 ```
-The source `tcpm_transmit[driver/tcpm/tcpm.h:142]` must be a full signature (function_name[path:line number]).
-So the resolver can know which indirect call you want to annotate and eliminate (even if it is inlined).
 
-Annotating arrays (hooks, console commands, host commands)
-----------------------------------------------------------
+The source `tcpm_transmit[driver/tcpm/tcpm.h:142]` must be a full signature
+(function_name[path:line number]). So the resolver can know which indirect call
+you want to annotate and eliminate (even if it is inlined).
+
+## Annotating arrays (hooks, console commands, host commands)
 
 When a callsite calls a number of functions based on values from an constant
 array (in `.rodata` section), one can use the following syntax:
@@ -89,8 +92,8 @@ array (in `.rodata` section), one can use the following syntax:
 Where `name` is the symbol name for the start of the array (the end of the array
 is `<name>_end`), stride is the array element size, and offset is the offset of
 the function pointer in the structure. For example, above, `__deferred_funcs` is
-a simple array of function pointers, while `__hooks_tick` is an array of
-`struct hook_data` (size 8, pointer at offset 0):
+a simple array of function pointers, while `__hooks_tick` is an array of `struct
+hook_data` (size 8, pointer at offset 0):
 
 ```
 struct hook_data {
diff --git a/extra/stack_analyzer/run_tests.sh b/extra/stack_analyzer/run_tests.sh
index 5662f60b8b..d5e65045c3 100755
--- a/extra/stack_analyzer/run_tests.sh
+++ b/extra/stack_analyzer/run_tests.sh
@@ -1,6 +1,6 @@
 #!/bin/bash
 #
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/extra/stack_analyzer/stack_analyzer.py b/extra/stack_analyzer/stack_analyzer.py
index f455a50e23..72db999cd4 100755
--- a/extra/stack_analyzer/stack_analyzer.py
+++ b/extra/stack_analyzer/stack_analyzer.py
@@ -1,5 +1,5 @@
 #!/usr/bin/env python3
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -21,1748 +21,2091 @@
 import os
 import re
 import subprocess
-import yaml
 
+import yaml  # pylint:disable=import-error
 
-SECTION_RO = 'RO'
-SECTION_RW = 'RW'
+
+SECTION_RO = "RO"
+SECTION_RW = "RW"
 # Default size of extra stack frame needed by exception context switch.
 # This value is for cortex-m with FPU enabled.
 DEFAULT_EXCEPTION_FRAME_SIZE = 224
 
 
 class StackAnalyzerError(Exception):
-  """Exception class for stack analyzer utility."""
+    """Exception class for stack analyzer utility."""
 
 
 class TaskInfo(ctypes.Structure):
-  """Taskinfo ctypes structure.
-
-  The structure definition is corresponding to the "struct taskinfo"
-  in "util/export_taskinfo.so.c".
-  """
-  _fields_ = [('name', ctypes.c_char_p),
-              ('routine', ctypes.c_char_p),
-              ('stack_size', ctypes.c_uint32)]
+    """Taskinfo ctypes structure.
 
+    The structure definition is corresponding to the "struct taskinfo"
+    in "util/export_taskinfo.so.c".
+    """
 
-class Task(object):
-  """Task information.
+    _fields_ = [
+        ("name", ctypes.c_char_p),
+        ("routine", ctypes.c_char_p),
+        ("stack_size", ctypes.c_uint32),
+    ]
 
-  Attributes:
-    name: Task name.
-    routine_name: Routine function name.
-    stack_max_size: Max stack size.
-    routine_address: Resolved routine address. None if it hasn't been resolved.
-  """
 
-  def __init__(self, name, routine_name, stack_max_size, routine_address=None):
-    """Constructor.
+class Task(object):
+    """Task information.
 
-    Args:
+    Attributes:
       name: Task name.
       routine_name: Routine function name.
       stack_max_size: Max stack size.
-      routine_address: Resolved routine address.
+      routine_address: Resolved routine address. None if it hasn't been resolved.
     """
-    self.name = name
-    self.routine_name = routine_name
-    self.stack_max_size = stack_max_size
-    self.routine_address = routine_address
 
-  def __eq__(self, other):
-    """Task equality.
-
-    Args:
-      other: The compared object.
-
-    Returns:
-      True if equal, False if not.
-    """
-    if not isinstance(other, Task):
-      return False
-
-    return (self.name == other.name and
-            self.routine_name == other.routine_name and
-            self.stack_max_size == other.stack_max_size and
-            self.routine_address == other.routine_address)
+    def __init__(
+        self, name, routine_name, stack_max_size, routine_address=None
+    ):
+        """Constructor.
+
+        Args:
+          name: Task name.
+          routine_name: Routine function name.
+          stack_max_size: Max stack size.
+          routine_address: Resolved routine address.
+        """
+        self.name = name
+        self.routine_name = routine_name
+        self.stack_max_size = stack_max_size
+        self.routine_address = routine_address
+
+    def __eq__(self, other):
+        """Task equality.
+
+        Args:
+          other: The compared object.
+
+        Returns:
+          True if equal, False if not.
+        """
+        if not isinstance(other, Task):
+            return False
+
+        return (
+            self.name == other.name
+            and self.routine_name == other.routine_name
+            and self.stack_max_size == other.stack_max_size
+            and self.routine_address == other.routine_address
+        )
 
 
 class Symbol(object):
-  """Symbol information.
-
-  Attributes:
-    address: Symbol address.
-    symtype: Symbol type, 'O' (data, object) or 'F' (function).
-    size: Symbol size.
-    name: Symbol name.
-  """
+    """Symbol information.
 
-  def __init__(self, address, symtype, size, name):
-    """Constructor.
-
-    Args:
+    Attributes:
       address: Symbol address.
-      symtype: Symbol type.
+      symtype: Symbol type, 'O' (data, object) or 'F' (function).
       size: Symbol size.
       name: Symbol name.
     """
-    assert symtype in ['O', 'F']
-    self.address = address
-    self.symtype = symtype
-    self.size = size
-    self.name = name
 
-  def __eq__(self, other):
-    """Symbol equality.
-
-    Args:
-      other: The compared object.
-
-    Returns:
-      True if equal, False if not.
-    """
-    if not isinstance(other, Symbol):
-      return False
-
-    return (self.address == other.address and
-            self.symtype == other.symtype and
-            self.size == other.size and
-            self.name == other.name)
+    def __init__(self, address, symtype, size, name):
+        """Constructor.
+
+        Args:
+          address: Symbol address.
+          symtype: Symbol type.
+          size: Symbol size.
+          name: Symbol name.
+        """
+        assert symtype in ["O", "F"]
+        self.address = address
+        self.symtype = symtype
+        self.size = size
+        self.name = name
+
+    def __eq__(self, other):
+        """Symbol equality.
+
+        Args:
+          other: The compared object.
+
+        Returns:
+          True if equal, False if not.
+        """
+        if not isinstance(other, Symbol):
+            return False
+
+        return (
+            self.address == other.address
+            and self.symtype == other.symtype
+            and self.size == other.size
+            and self.name == other.name
+        )
 
 
 class Callsite(object):
-  """Function callsite.
-
-  Attributes:
-    address: Address of callsite location. None if it is unknown.
-    target: Callee address. None if it is unknown.
-    is_tail: A bool indicates that it is a tailing call.
-    callee: Resolved callee function. None if it hasn't been resolved.
-  """
-
-  def __init__(self, address, target, is_tail, callee=None):
-    """Constructor.
+    """Function callsite.
 
-    Args:
+    Attributes:
       address: Address of callsite location. None if it is unknown.
       target: Callee address. None if it is unknown.
-      is_tail: A bool indicates that it is a tailing call. (function jump to
-               another function without restoring the stack frame)
-      callee: Resolved callee function.
+      is_tail: A bool indicates that it is a tailing call.
+      callee: Resolved callee function. None if it hasn't been resolved.
     """
-    # It makes no sense that both address and target are unknown.
-    assert not (address is None and target is None)
-    self.address = address
-    self.target = target
-    self.is_tail = is_tail
-    self.callee = callee
 
-  def __eq__(self, other):
-    """Callsite equality.
-
-    Args:
-      other: The compared object.
-
-    Returns:
-      True if equal, False if not.
-    """
-    if not isinstance(other, Callsite):
-      return False
-
-    if not (self.address == other.address and
-            self.target == other.target and
-            self.is_tail == other.is_tail):
-      return False
-
-    if self.callee is None:
-      return other.callee is None
-    elif other.callee is None:
-      return False
-
-    # Assume the addresses of functions are unique.
-    return self.callee.address == other.callee.address
+    def __init__(self, address, target, is_tail, callee=None):
+        """Constructor.
+
+        Args:
+          address: Address of callsite location. None if it is unknown.
+          target: Callee address. None if it is unknown.
+          is_tail: A bool indicates that it is a tailing call. (function jump to
+                   another function without restoring the stack frame)
+          callee: Resolved callee function.
+        """
+        # It makes no sense that both address and target are unknown.
+        assert not (address is None and target is None)
+        self.address = address
+        self.target = target
+        self.is_tail = is_tail
+        self.callee = callee
+
+    def __eq__(self, other):
+        """Callsite equality.
+
+        Args:
+          other: The compared object.
+
+        Returns:
+          True if equal, False if not.
+        """
+        if not isinstance(other, Callsite):
+            return False
+
+        if not (
+            self.address == other.address
+            and self.target == other.target
+            and self.is_tail == other.is_tail
+        ):
+            return False
+
+        if self.callee is None:
+            return other.callee is None
+        elif other.callee is None:
+            return False
+
+        # Assume the addresses of functions are unique.
+        return self.callee.address == other.callee.address
 
 
 class Function(object):
-  """Function.
-
-  Attributes:
-    address: Address of function.
-    name: Name of function from its symbol.
-    stack_frame: Size of stack frame.
-    callsites: Callsite list.
-    stack_max_usage: Max stack usage. None if it hasn't been analyzed.
-    stack_max_path: Max stack usage path. None if it hasn't been analyzed.
-  """
+    """Function.
 
-  def __init__(self, address, name, stack_frame, callsites):
-    """Constructor.
-
-    Args:
+    Attributes:
       address: Address of function.
       name: Name of function from its symbol.
       stack_frame: Size of stack frame.
       callsites: Callsite list.
+      stack_max_usage: Max stack usage. None if it hasn't been analyzed.
+      stack_max_path: Max stack usage path. None if it hasn't been analyzed.
     """
-    self.address = address
-    self.name = name
-    self.stack_frame = stack_frame
-    self.callsites = callsites
-    self.stack_max_usage = None
-    self.stack_max_path = None
-
-  def __eq__(self, other):
-    """Function equality.
 
-    Args:
-      other: The compared object.
+    def __init__(self, address, name, stack_frame, callsites):
+        """Constructor.
+
+        Args:
+          address: Address of function.
+          name: Name of function from its symbol.
+          stack_frame: Size of stack frame.
+          callsites: Callsite list.
+        """
+        self.address = address
+        self.name = name
+        self.stack_frame = stack_frame
+        self.callsites = callsites
+        self.stack_max_usage = None
+        self.stack_max_path = None
+
+    def __eq__(self, other):
+        """Function equality.
+
+        Args:
+          other: The compared object.
+
+        Returns:
+          True if equal, False if not.
+        """
+        if not isinstance(other, Function):
+            return False
+
+        if not (
+            self.address == other.address
+            and self.name == other.name
+            and self.stack_frame == other.stack_frame
+            and self.callsites == other.callsites
+            and self.stack_max_usage == other.stack_max_usage
+        ):
+            return False
+
+        if self.stack_max_path is None:
+            return other.stack_max_path is None
+        elif other.stack_max_path is None:
+            return False
+
+        if len(self.stack_max_path) != len(other.stack_max_path):
+            return False
+
+        for self_func, other_func in zip(
+            self.stack_max_path, other.stack_max_path
+        ):
+            # Assume the addresses of functions are unique.
+            if self_func.address != other_func.address:
+                return False
+
+        return True
+
+    def __hash__(self):
+        return id(self)
 
-    Returns:
-      True if equal, False if not.
-    """
-    if not isinstance(other, Function):
-      return False
-
-    if not (self.address == other.address and
-            self.name == other.name and
-            self.stack_frame == other.stack_frame and
-            self.callsites == other.callsites and
-            self.stack_max_usage == other.stack_max_usage):
-      return False
-
-    if self.stack_max_path is None:
-      return other.stack_max_path is None
-    elif other.stack_max_path is None:
-      return False
-
-    if len(self.stack_max_path) != len(other.stack_max_path):
-      return False
-
-    for self_func, other_func in zip(self.stack_max_path, other.stack_max_path):
-      # Assume the addresses of functions are unique.
-      if self_func.address != other_func.address:
-        return False
-
-    return True
-
-  def __hash__(self):
-    return id(self)
 
 class AndesAnalyzer(object):
-  """Disassembly analyzer for Andes architecture.
-
-  Public Methods:
-    AnalyzeFunction: Analyze stack frame and callsites of the function.
-  """
-
-  GENERAL_PURPOSE_REGISTER_SIZE = 4
-
-  # Possible condition code suffixes.
-  CONDITION_CODES = [ 'eq', 'eqz', 'gez', 'gtz', 'lez', 'ltz', 'ne', 'nez',
-                      'eqc', 'nec', 'nezs', 'nes', 'eqs']
-  CONDITION_CODES_RE = '({})'.format('|'.join(CONDITION_CODES))
-
-  IMM_ADDRESS_RE = r'([0-9A-Fa-f]+)\s+<([^>]+)>'
-  # Branch instructions.
-  JUMP_OPCODE_RE = re.compile(r'^(b{0}|j|jr|jr.|jrnez)(\d?|\d\d)$' \
-                  .format(CONDITION_CODES_RE))
-  # Call instructions.
-  CALL_OPCODE_RE = re.compile \
-                  (r'^(jal|jral|jral.|jralnez|beqzal|bltzal|bgezal)(\d)?$')
-  CALL_OPERAND_RE = re.compile(r'^{}$'.format(IMM_ADDRESS_RE))
-  # Ignore lp register because it's for return.
-  INDIRECT_CALL_OPERAND_RE = re.compile \
-                  (r'^\$r\d{1,}$|\$fp$|\$gp$|\$ta$|\$sp$|\$pc$')
-  # TODO: Handle other kinds of store instructions.
-  PUSH_OPCODE_RE = re.compile(r'^push(\d{1,})$')
-  PUSH_OPERAND_RE = re.compile(r'^\$r\d{1,}, \#\d{1,}    \! \{([^\]]+)\}')
-  SMW_OPCODE_RE = re.compile(r'^smw(\.\w\w|\.\w\w\w)$')
-  SMW_OPERAND_RE = re.compile(r'^(\$r\d{1,}|\$\wp), \[\$\wp\], '
-                   r'(\$r\d{1,}|\$\wp), \#\d\w\d    \! \{([^\]]+)\}')
-  OPERANDGROUP_RE = re.compile(r'^\$r\d{1,}\~\$r\d{1,}')
-
-  LWI_OPCODE_RE = re.compile(r'^lwi(\.\w\w)$')
-  LWI_PC_OPERAND_RE = re.compile(r'^\$pc, \[([^\]]+)\]')
-  # Example: "34280:  3f c8 0f ec   addi.gp $fp, #0xfec"
-  # Assume there is always a "\t" after the hex data.
-  DISASM_REGEX_RE = re.compile(r'^(?P<address>[0-9A-Fa-f]+):\s+'
-                    r'(?P<words>[0-9A-Fa-f ]+)'
-                    r'\t\s*(?P<opcode>\S+)(\s+(?P<operand>[^;]*))?')
-
-  def ParseInstruction(self, line, function_end):
-    """Parse the line of instruction.
+    """Disassembly analyzer for Andes architecture.
 
-    Args:
-      line: Text of disassembly.
-      function_end: End address of the current function. None if unknown.
-
-    Returns:
-      (address, words, opcode, operand_text): The instruction address, words,
-                                        opcode, and the text of operands.
-                                        None if it isn't an instruction line.
+    Public Methods:
+      AnalyzeFunction: Analyze stack frame and callsites of the function.
     """
-    result = self.DISASM_REGEX_RE.match(line)
-    if result is None:
-      return None
-
-    address = int(result.group('address'), 16)
-    # Check if it's out of bound.
-    if function_end is not None and address >= function_end:
-      return None
-
-    opcode = result.group('opcode').strip()
-    operand_text = result.group('operand')
-    words = result.group('words')
-    if operand_text is None:
-      operand_text = ''
-    else:
-      operand_text = operand_text.strip()
-
-    return (address, words, opcode, operand_text)
-
-  def AnalyzeFunction(self, function_symbol, instructions):
-
-    stack_frame = 0
-    callsites = []
-    for address, words, opcode, operand_text in instructions:
-      is_jump_opcode = self.JUMP_OPCODE_RE.match(opcode) is not None
-      is_call_opcode = self.CALL_OPCODE_RE.match(opcode) is not None
-
-      if is_jump_opcode or is_call_opcode:
-        is_tail = is_jump_opcode
-
-        result = self.CALL_OPERAND_RE.match(operand_text)
 
+    GENERAL_PURPOSE_REGISTER_SIZE = 4
+
+    # Possible condition code suffixes.
+    CONDITION_CODES = [
+        "eq",
+        "eqz",
+        "gez",
+        "gtz",
+        "lez",
+        "ltz",
+        "ne",
+        "nez",
+        "eqc",
+        "nec",
+        "nezs",
+        "nes",
+        "eqs",
+    ]
+    CONDITION_CODES_RE = "({})".format("|".join(CONDITION_CODES))
+
+    IMM_ADDRESS_RE = r"([0-9A-Fa-f]+)\s+<([^>]+)>"
+    # Branch instructions.
+    JUMP_OPCODE_RE = re.compile(
+        r"^(b{0}|j|jr|jr.|jrnez)(\d?|\d\d)$".format(CONDITION_CODES_RE)
+    )
+    # Call instructions.
+    CALL_OPCODE_RE = re.compile(
+        r"^(jal|jral|jral.|jralnez|beqzal|bltzal|bgezal)(\d)?$"
+    )
+    CALL_OPERAND_RE = re.compile(r"^{}$".format(IMM_ADDRESS_RE))
+    # Ignore lp register because it's for return.
+    INDIRECT_CALL_OPERAND_RE = re.compile(
+        r"^\$r\d{1,}$|\$fp$|\$gp$|\$ta$|\$sp$|\$pc$"
+    )
+    # TODO: Handle other kinds of store instructions.
+    PUSH_OPCODE_RE = re.compile(r"^push(\d{1,})$")
+    PUSH_OPERAND_RE = re.compile(r"^\$r\d{1,}, \#\d{1,}    \! \{([^\]]+)\}")
+    SMW_OPCODE_RE = re.compile(r"^smw(\.\w\w|\.\w\w\w)$")
+    SMW_OPERAND_RE = re.compile(
+        r"^(\$r\d{1,}|\$\wp), \[\$\wp\], "
+        r"(\$r\d{1,}|\$\wp), \#\d\w\d    \! \{([^\]]+)\}"
+    )
+    OPERANDGROUP_RE = re.compile(r"^\$r\d{1,}\~\$r\d{1,}")
+
+    LWI_OPCODE_RE = re.compile(r"^lwi(\.\w\w)$")
+    LWI_PC_OPERAND_RE = re.compile(r"^\$pc, \[([^\]]+)\]")
+    # Example: "34280:  3f c8 0f ec   addi.gp $fp, #0xfec"
+    # Assume there is always a "\t" after the hex data.
+    DISASM_REGEX_RE = re.compile(
+        r"^(?P<address>[0-9A-Fa-f]+):\s+"
+        r"(?P<words>[0-9A-Fa-f ]+)"
+        r"\t\s*(?P<opcode>\S+)(\s+(?P<operand>[^;]*))?"
+    )
+
+    def ParseInstruction(self, line, function_end):
+        """Parse the line of instruction.
+
+        Args:
+          line: Text of disassembly.
+          function_end: End address of the current function. None if unknown.
+
+        Returns:
+          (address, words, opcode, operand_text): The instruction address, words,
+                                            opcode, and the text of operands.
+                                            None if it isn't an instruction line.
+        """
+        result = self.DISASM_REGEX_RE.match(line)
         if result is None:
-          if (self.INDIRECT_CALL_OPERAND_RE.match(operand_text) is not None):
-            # Found an indirect call.
-            callsites.append(Callsite(address, None, is_tail))
-
+            return None
+
+        address = int(result.group("address"), 16)
+        # Check if it's out of bound.
+        if function_end is not None and address >= function_end:
+            return None
+
+        opcode = result.group("opcode").strip()
+        operand_text = result.group("operand")
+        words = result.group("words")
+        if operand_text is None:
+            operand_text = ""
         else:
-          target_address = int(result.group(1), 16)
-          # Filter out the in-function target (branches and in-function calls,
-          # which are actually branches).
-          if not (function_symbol.size > 0 and
-                  function_symbol.address < target_address <
-                  (function_symbol.address + function_symbol.size)):
-            # Maybe it is a callsite.
-            callsites.append(Callsite(address, target_address, is_tail))
-
-      elif self.LWI_OPCODE_RE.match(opcode) is not None:
-        result = self.LWI_PC_OPERAND_RE.match(operand_text)
-        if result is not None:
-          # Ignore "lwi $pc, [$sp], xx" because it's usually a return.
-          if result.group(1) != '$sp':
-            # Found an indirect call.
-            callsites.append(Callsite(address, None, True))
-
-      elif self.PUSH_OPCODE_RE.match(opcode) is not None:
-        # Example: fc 20    push25 $r8, #0    ! {$r6~$r8, $fp, $gp, $lp}
-        if self.PUSH_OPERAND_RE.match(operand_text) is not None:
-          # capture fc 20
-          imm5u = int(words.split(' ')[1], 16)
-          # sp = sp - (imm5u << 3)
-          imm8u = (imm5u<<3) & 0xff
-          stack_frame += imm8u
-
-          result = self.PUSH_OPERAND_RE.match(operand_text)
-          operandgroup_text = result.group(1)
-          # capture $rx~$ry
-          if self.OPERANDGROUP_RE.match(operandgroup_text) is not None:
-            # capture number & transfer string to integer
-            oprandgrouphead = operandgroup_text.split(',')[0]
-            rx=int(''.join(filter(str.isdigit, oprandgrouphead.split('~')[0])))
-            ry=int(''.join(filter(str.isdigit, oprandgrouphead.split('~')[1])))
-
-            stack_frame += ((len(operandgroup_text.split(','))+ry-rx) *
-                          self.GENERAL_PURPOSE_REGISTER_SIZE)
-          else:
-            stack_frame += (len(operandgroup_text.split(',')) *
-                          self.GENERAL_PURPOSE_REGISTER_SIZE)
-
-      elif self.SMW_OPCODE_RE.match(opcode) is not None:
-        # Example: smw.adm $r6, [$sp], $r10, #0x2    ! {$r6~$r10, $lp}
-        if self.SMW_OPERAND_RE.match(operand_text) is not None:
-          result = self.SMW_OPERAND_RE.match(operand_text)
-          operandgroup_text = result.group(3)
-          # capture $rx~$ry
-          if self.OPERANDGROUP_RE.match(operandgroup_text) is not None:
-            # capture number & transfer string to integer
-            oprandgrouphead = operandgroup_text.split(',')[0]
-            rx=int(''.join(filter(str.isdigit, oprandgrouphead.split('~')[0])))
-            ry=int(''.join(filter(str.isdigit, oprandgrouphead.split('~')[1])))
-
-            stack_frame += ((len(operandgroup_text.split(','))+ry-rx) *
-                          self.GENERAL_PURPOSE_REGISTER_SIZE)
-          else:
-            stack_frame += (len(operandgroup_text.split(',')) *
-                          self.GENERAL_PURPOSE_REGISTER_SIZE)
-
-    return (stack_frame, callsites)
+            operand_text = operand_text.strip()
+
+        return (address, words, opcode, operand_text)
+
+    def AnalyzeFunction(self, function_symbol, instructions):
+
+        stack_frame = 0
+        callsites = []
+        for address, words, opcode, operand_text in instructions:
+            is_jump_opcode = self.JUMP_OPCODE_RE.match(opcode) is not None
+            is_call_opcode = self.CALL_OPCODE_RE.match(opcode) is not None
+
+            if is_jump_opcode or is_call_opcode:
+                is_tail = is_jump_opcode
+
+                result = self.CALL_OPERAND_RE.match(operand_text)
+
+                if result is None:
+                    if (
+                        self.INDIRECT_CALL_OPERAND_RE.match(operand_text)
+                        is not None
+                    ):
+                        # Found an indirect call.
+                        callsites.append(Callsite(address, None, is_tail))
+
+                else:
+                    target_address = int(result.group(1), 16)
+                    # Filter out the in-function target (branches and in-function calls,
+                    # which are actually branches).
+                    if not (
+                        function_symbol.size > 0
+                        and function_symbol.address
+                        < target_address
+                        < (function_symbol.address + function_symbol.size)
+                    ):
+                        # Maybe it is a callsite.
+                        callsites.append(
+                            Callsite(address, target_address, is_tail)
+                        )
+
+            elif self.LWI_OPCODE_RE.match(opcode) is not None:
+                result = self.LWI_PC_OPERAND_RE.match(operand_text)
+                if result is not None:
+                    # Ignore "lwi $pc, [$sp], xx" because it's usually a return.
+                    if result.group(1) != "$sp":
+                        # Found an indirect call.
+                        callsites.append(Callsite(address, None, True))
+
+            elif self.PUSH_OPCODE_RE.match(opcode) is not None:
+                # Example: fc 20    push25 $r8, #0    ! {$r6~$r8, $fp, $gp, $lp}
+                if self.PUSH_OPERAND_RE.match(operand_text) is not None:
+                    # capture fc 20
+                    imm5u = int(words.split(" ")[1], 16)
+                    # sp = sp - (imm5u << 3)
+                    imm8u = (imm5u << 3) & 0xFF
+                    stack_frame += imm8u
+
+                    result = self.PUSH_OPERAND_RE.match(operand_text)
+                    operandgroup_text = result.group(1)
+                    # capture $rx~$ry
+                    if (
+                        self.OPERANDGROUP_RE.match(operandgroup_text)
+                        is not None
+                    ):
+                        # capture number & transfer string to integer
+                        oprandgrouphead = operandgroup_text.split(",")[0]
+                        rx = int(
+                            "".join(
+                                filter(
+                                    str.isdigit, oprandgrouphead.split("~")[0]
+                                )
+                            )
+                        )
+                        ry = int(
+                            "".join(
+                                filter(
+                                    str.isdigit, oprandgrouphead.split("~")[1]
+                                )
+                            )
+                        )
+
+                        stack_frame += (
+                            len(operandgroup_text.split(",")) + ry - rx
+                        ) * self.GENERAL_PURPOSE_REGISTER_SIZE
+                    else:
+                        stack_frame += (
+                            len(operandgroup_text.split(","))
+                            * self.GENERAL_PURPOSE_REGISTER_SIZE
+                        )
+
+            elif self.SMW_OPCODE_RE.match(opcode) is not None:
+                # Example: smw.adm $r6, [$sp], $r10, #0x2    ! {$r6~$r10, $lp}
+                if self.SMW_OPERAND_RE.match(operand_text) is not None:
+                    result = self.SMW_OPERAND_RE.match(operand_text)
+                    operandgroup_text = result.group(3)
+                    # capture $rx~$ry
+                    if (
+                        self.OPERANDGROUP_RE.match(operandgroup_text)
+                        is not None
+                    ):
+                        # capture number & transfer string to integer
+                        oprandgrouphead = operandgroup_text.split(",")[0]
+                        rx = int(
+                            "".join(
+                                filter(
+                                    str.isdigit, oprandgrouphead.split("~")[0]
+                                )
+                            )
+                        )
+                        ry = int(
+                            "".join(
+                                filter(
+                                    str.isdigit, oprandgrouphead.split("~")[1]
+                                )
+                            )
+                        )
+
+                        stack_frame += (
+                            len(operandgroup_text.split(",")) + ry - rx
+                        ) * self.GENERAL_PURPOSE_REGISTER_SIZE
+                    else:
+                        stack_frame += (
+                            len(operandgroup_text.split(","))
+                            * self.GENERAL_PURPOSE_REGISTER_SIZE
+                        )
+
+        return (stack_frame, callsites)
 
-class ArmAnalyzer(object):
-  """Disassembly analyzer for ARM architecture.
-
-  Public Methods:
-    AnalyzeFunction: Analyze stack frame and callsites of the function.
-  """
-
-  GENERAL_PURPOSE_REGISTER_SIZE = 4
-
-  # Possible condition code suffixes.
-  CONDITION_CODES = ['', 'eq', 'ne', 'cs', 'hs', 'cc', 'lo', 'mi', 'pl', 'vs',
-                     'vc', 'hi', 'ls', 'ge', 'lt', 'gt', 'le']
-  CONDITION_CODES_RE = '({})'.format('|'.join(CONDITION_CODES))
-  # Assume there is no function name containing ">".
-  IMM_ADDRESS_RE = r'([0-9A-Fa-f]+)\s+<([^>]+)>'
-
-  # Fuzzy regular expressions for instruction and operand parsing.
-  # Branch instructions.
-  JUMP_OPCODE_RE = re.compile(
-      r'^(b{0}|bx{0})(\.\w)?$'.format(CONDITION_CODES_RE))
-  # Call instructions.
-  CALL_OPCODE_RE = re.compile(
-      r'^(bl{0}|blx{0})(\.\w)?$'.format(CONDITION_CODES_RE))
-  CALL_OPERAND_RE = re.compile(r'^{}$'.format(IMM_ADDRESS_RE))
-  CBZ_CBNZ_OPCODE_RE = re.compile(r'^(cbz|cbnz)(\.\w)?$')
-  # Example: "r0, 1009bcbe <host_cmd_motion_sense+0x1d2>"
-  CBZ_CBNZ_OPERAND_RE = re.compile(r'^[^,]+,\s+{}$'.format(IMM_ADDRESS_RE))
-  # Ignore lr register because it's for return.
-  INDIRECT_CALL_OPERAND_RE = re.compile(r'^r\d+|sb|sl|fp|ip|sp|pc$')
-  # TODO(cheyuw): Handle conditional versions of following
-  #               instructions.
-  # TODO(cheyuw): Handle other kinds of pc modifying instructions (e.g. mov pc).
-  LDR_OPCODE_RE = re.compile(r'^ldr(\.\w)?$')
-  # Example: "pc, [sp], #4"
-  LDR_PC_OPERAND_RE = re.compile(r'^pc, \[([^\]]+)\]')
-  # TODO(cheyuw): Handle other kinds of stm instructions.
-  PUSH_OPCODE_RE = re.compile(r'^push$')
-  STM_OPCODE_RE = re.compile(r'^stmdb$')
-  # Stack subtraction instructions.
-  SUB_OPCODE_RE = re.compile(r'^sub(s|w)?(\.\w)?$')
-  SUB_OPERAND_RE = re.compile(r'^sp[^#]+#(\d+)')
-  # Example: "44d94:  f893 0068   ldrb.w  r0, [r3, #104]  ; 0x68"
-  # Assume there is always a "\t" after the hex data.
-  DISASM_REGEX_RE = re.compile(r'^(?P<address>[0-9A-Fa-f]+):\s+[0-9A-Fa-f ]+'
-                               r'\t\s*(?P<opcode>\S+)(\s+(?P<operand>[^;]*))?')
-
-  def ParseInstruction(self, line, function_end):
-    """Parse the line of instruction.
 
-    Args:
-      line: Text of disassembly.
-      function_end: End address of the current function. None if unknown.
+class ArmAnalyzer(object):
+    """Disassembly analyzer for ARM architecture.
 
-    Returns:
-      (address, opcode, operand_text): The instruction address, opcode,
-                                       and the text of operands. None if it
-                                       isn't an instruction line.
+    Public Methods:
+      AnalyzeFunction: Analyze stack frame and callsites of the function.
     """
-    result = self.DISASM_REGEX_RE.match(line)
-    if result is None:
-      return None
-
-    address = int(result.group('address'), 16)
-    # Check if it's out of bound.
-    if function_end is not None and address >= function_end:
-      return None
-
-    opcode = result.group('opcode').strip()
-    operand_text = result.group('operand')
-    if operand_text is None:
-      operand_text = ''
-    else:
-      operand_text = operand_text.strip()
 
-    return (address, opcode, operand_text)
-
-  def AnalyzeFunction(self, function_symbol, instructions):
-    """Analyze function, resolve the size of stack frame and callsites.
+    GENERAL_PURPOSE_REGISTER_SIZE = 4
+
+    # Possible condition code suffixes.
+    CONDITION_CODES = [
+        "",
+        "eq",
+        "ne",
+        "cs",
+        "hs",
+        "cc",
+        "lo",
+        "mi",
+        "pl",
+        "vs",
+        "vc",
+        "hi",
+        "ls",
+        "ge",
+        "lt",
+        "gt",
+        "le",
+    ]
+    CONDITION_CODES_RE = "({})".format("|".join(CONDITION_CODES))
+    # Assume there is no function name containing ">".
+    IMM_ADDRESS_RE = r"([0-9A-Fa-f]+)\s+<([^>]+)>"
+
+    # Fuzzy regular expressions for instruction and operand parsing.
+    # Branch instructions.
+    JUMP_OPCODE_RE = re.compile(
+        r"^(b{0}|bx{0})(\.\w)?$".format(CONDITION_CODES_RE)
+    )
+    # Call instructions.
+    CALL_OPCODE_RE = re.compile(
+        r"^(bl{0}|blx{0})(\.\w)?$".format(CONDITION_CODES_RE)
+    )
+    CALL_OPERAND_RE = re.compile(r"^{}$".format(IMM_ADDRESS_RE))
+    CBZ_CBNZ_OPCODE_RE = re.compile(r"^(cbz|cbnz)(\.\w)?$")
+    # Example: "r0, 1009bcbe <host_cmd_motion_sense+0x1d2>"
+    CBZ_CBNZ_OPERAND_RE = re.compile(r"^[^,]+,\s+{}$".format(IMM_ADDRESS_RE))
+    # Ignore lr register because it's for return.
+    INDIRECT_CALL_OPERAND_RE = re.compile(r"^r\d+|sb|sl|fp|ip|sp|pc$")
+    # TODO(cheyuw): Handle conditional versions of following
+    #               instructions.
+    # TODO(cheyuw): Handle other kinds of pc modifying instructions (e.g. mov pc).
+    LDR_OPCODE_RE = re.compile(r"^ldr(\.\w)?$")
+    # Example: "pc, [sp], #4"
+    LDR_PC_OPERAND_RE = re.compile(r"^pc, \[([^\]]+)\]")
+    # TODO(cheyuw): Handle other kinds of stm instructions.
+    PUSH_OPCODE_RE = re.compile(r"^push$")
+    STM_OPCODE_RE = re.compile(r"^stmdb$")
+    # Stack subtraction instructions.
+    SUB_OPCODE_RE = re.compile(r"^sub(s|w)?(\.\w)?$")
+    SUB_OPERAND_RE = re.compile(r"^sp[^#]+#(\d+)")
+    # Example: "44d94:  f893 0068   ldrb.w  r0, [r3, #104]  ; 0x68"
+    # Assume there is always a "\t" after the hex data.
+    DISASM_REGEX_RE = re.compile(
+        r"^(?P<address>[0-9A-Fa-f]+):\s+[0-9A-Fa-f ]+"
+        r"\t\s*(?P<opcode>\S+)(\s+(?P<operand>[^;]*))?"
+    )
+
+    def ParseInstruction(self, line, function_end):
+        """Parse the line of instruction.
+
+        Args:
+          line: Text of disassembly.
+          function_end: End address of the current function. None if unknown.
+
+        Returns:
+          (address, opcode, operand_text): The instruction address, opcode,
+                                           and the text of operands. None if it
+                                           isn't an instruction line.
+        """
+        result = self.DISASM_REGEX_RE.match(line)
+        if result is None:
+            return None
 
-    Args:
-      function_symbol: Function symbol.
-      instructions: Instruction list.
+        address = int(result.group("address"), 16)
+        # Check if it's out of bound.
+        if function_end is not None and address >= function_end:
+            return None
 
-    Returns:
-      (stack_frame, callsites): Size of stack frame, callsite list.
-    """
-    stack_frame = 0
-    callsites = []
-    for address, opcode, operand_text in instructions:
-      is_jump_opcode = self.JUMP_OPCODE_RE.match(opcode) is not None
-      is_call_opcode = self.CALL_OPCODE_RE.match(opcode) is not None
-      is_cbz_cbnz_opcode = self.CBZ_CBNZ_OPCODE_RE.match(opcode) is not None
-      if is_jump_opcode or is_call_opcode or is_cbz_cbnz_opcode:
-        is_tail = is_jump_opcode or is_cbz_cbnz_opcode
-
-        if is_cbz_cbnz_opcode:
-          result = self.CBZ_CBNZ_OPERAND_RE.match(operand_text)
+        opcode = result.group("opcode").strip()
+        operand_text = result.group("operand")
+        if operand_text is None:
+            operand_text = ""
         else:
-          result = self.CALL_OPERAND_RE.match(operand_text)
+            operand_text = operand_text.strip()
+
+        return (address, opcode, operand_text)
+
+    def AnalyzeFunction(self, function_symbol, instructions):
+        """Analyze function, resolve the size of stack frame and callsites.
+
+        Args:
+          function_symbol: Function symbol.
+          instructions: Instruction list.
+
+        Returns:
+          (stack_frame, callsites): Size of stack frame, callsite list.
+        """
+        stack_frame = 0
+        callsites = []
+        for address, opcode, operand_text in instructions:
+            is_jump_opcode = self.JUMP_OPCODE_RE.match(opcode) is not None
+            is_call_opcode = self.CALL_OPCODE_RE.match(opcode) is not None
+            is_cbz_cbnz_opcode = (
+                self.CBZ_CBNZ_OPCODE_RE.match(opcode) is not None
+            )
+            if is_jump_opcode or is_call_opcode or is_cbz_cbnz_opcode:
+                is_tail = is_jump_opcode or is_cbz_cbnz_opcode
+
+                if is_cbz_cbnz_opcode:
+                    result = self.CBZ_CBNZ_OPERAND_RE.match(operand_text)
+                else:
+                    result = self.CALL_OPERAND_RE.match(operand_text)
+
+                if result is None:
+                    # Failed to match immediate address, maybe it is an indirect call.
+                    # CBZ and CBNZ can't be indirect calls.
+                    if (
+                        not is_cbz_cbnz_opcode
+                        and self.INDIRECT_CALL_OPERAND_RE.match(operand_text)
+                        is not None
+                    ):
+                        # Found an indirect call.
+                        callsites.append(Callsite(address, None, is_tail))
+
+                else:
+                    target_address = int(result.group(1), 16)
+                    # Filter out the in-function target (branches and in-function calls,
+                    # which are actually branches).
+                    if not (
+                        function_symbol.size > 0
+                        and function_symbol.address
+                        < target_address
+                        < (function_symbol.address + function_symbol.size)
+                    ):
+                        # Maybe it is a callsite.
+                        callsites.append(
+                            Callsite(address, target_address, is_tail)
+                        )
+
+            elif self.LDR_OPCODE_RE.match(opcode) is not None:
+                result = self.LDR_PC_OPERAND_RE.match(operand_text)
+                if result is not None:
+                    # Ignore "ldr pc, [sp], xx" because it's usually a return.
+                    if result.group(1) != "sp":
+                        # Found an indirect call.
+                        callsites.append(Callsite(address, None, True))
+
+            elif self.PUSH_OPCODE_RE.match(opcode) is not None:
+                # Example: "{r4, r5, r6, r7, lr}"
+                stack_frame += (
+                    len(operand_text.split(","))
+                    * self.GENERAL_PURPOSE_REGISTER_SIZE
+                )
+            elif self.SUB_OPCODE_RE.match(opcode) is not None:
+                result = self.SUB_OPERAND_RE.match(operand_text)
+                if result is not None:
+                    stack_frame += int(result.group(1))
+                else:
+                    # Unhandled stack register subtraction.
+                    assert not operand_text.startswith("sp")
+
+            elif self.STM_OPCODE_RE.match(opcode) is not None:
+                if operand_text.startswith("sp!"):
+                    # Subtract and writeback to stack register.
+                    # Example: "sp!, {r4, r5, r6, r7, r8, r9, lr}"
+                    # Get the text of pushed register list.
+                    (
+                        unused_sp,
+                        unused_sep,
+                        parameter_text,
+                    ) = operand_text.partition(",")
+                    stack_frame += (
+                        len(parameter_text.split(","))
+                        * self.GENERAL_PURPOSE_REGISTER_SIZE
+                    )
+
+        return (stack_frame, callsites)
+
+
+class RiscvAnalyzer(object):
+    """Disassembly analyzer for RISC-V architecture.
+
+    Public Methods:
+      AnalyzeFunction: Analyze stack frame and callsites of the function.
+    """
 
+    # Possible condition code suffixes.
+    CONDITION_CODES = [
+        "eqz",
+        "nez",
+        "lez",
+        "gez",
+        "ltz",
+        "gtz",
+        "gt",
+        "le",
+        "gtu",
+        "leu",
+        "eq",
+        "ne",
+        "ge",
+        "lt",
+        "ltu",
+        "geu",
+    ]
+    CONDITION_CODES_RE = "({})".format("|".join(CONDITION_CODES))
+    # Branch instructions.
+    JUMP_OPCODE_RE = re.compile(r"^(b{0}|j|jr)$".format(CONDITION_CODES_RE))
+    # Call instructions.
+    CALL_OPCODE_RE = re.compile(r"^(jal|jalr)$")
+    # Example: "j		8009b318 <set_state_prl_hr>" or
+    #          "jal	ra,800a4394 <power_get_signals>" or
+    #          "bltu	t0,t1,80080300 <data_loop>"
+    JUMP_ADDRESS_RE = r"((\w(\w|\d\d),){0,2})([0-9A-Fa-f]+)\s+<([^>]+)>"
+    CALL_OPERAND_RE = re.compile(r"^{}$".format(JUMP_ADDRESS_RE))
+    # Capture address, Example:  800a4394
+    CAPTURE_ADDRESS = re.compile(r"[0-9A-Fa-f]{8}")
+    # Indirect jump, Example: jalr	a5
+    INDIRECT_CALL_OPERAND_RE = re.compile(r"^t\d+|s\d+|a\d+$")
+    # Example:  addi
+    ADDI_OPCODE_RE = re.compile(r"^addi$")
+    # Allocate stack instructions.
+    ADDI_OPERAND_RE = re.compile(r"^(sp,sp,-\d+)$")
+    # Example: "800804b6:	1101                	addi	sp,sp,-32"
+    DISASM_REGEX_RE = re.compile(
+        r"^(?P<address>[0-9A-Fa-f]+):\s+[0-9A-Fa-f ]+"
+        r"\t\s*(?P<opcode>\S+)(\s+(?P<operand>[^;]*))?"
+    )
+
+    def ParseInstruction(self, line, function_end):
+        """Parse the line of instruction.
+
+        Args:
+          line: Text of disassembly.
+          function_end: End address of the current function. None if unknown.
+
+        Returns:
+          (address, opcode, operand_text):  The instruction address, opcode,
+                                            and the text of operands. None if it
+                                            isn't an instruction line.
+        """
+        result = self.DISASM_REGEX_RE.match(line)
         if result is None:
-          # Failed to match immediate address, maybe it is an indirect call.
-          # CBZ and CBNZ can't be indirect calls.
-          if (not is_cbz_cbnz_opcode and
-              self.INDIRECT_CALL_OPERAND_RE.match(operand_text) is not None):
-            # Found an indirect call.
-            callsites.append(Callsite(address, None, is_tail))
-
-        else:
-          target_address = int(result.group(1), 16)
-          # Filter out the in-function target (branches and in-function calls,
-          # which are actually branches).
-          if not (function_symbol.size > 0 and
-                  function_symbol.address < target_address <
-                  (function_symbol.address + function_symbol.size)):
-            # Maybe it is a callsite.
-            callsites.append(Callsite(address, target_address, is_tail))
-
-      elif self.LDR_OPCODE_RE.match(opcode) is not None:
-        result = self.LDR_PC_OPERAND_RE.match(operand_text)
-        if result is not None:
-          # Ignore "ldr pc, [sp], xx" because it's usually a return.
-          if result.group(1) != 'sp':
-            # Found an indirect call.
-            callsites.append(Callsite(address, None, True))
-
-      elif self.PUSH_OPCODE_RE.match(opcode) is not None:
-        # Example: "{r4, r5, r6, r7, lr}"
-        stack_frame += (len(operand_text.split(',')) *
-                        self.GENERAL_PURPOSE_REGISTER_SIZE)
-      elif self.SUB_OPCODE_RE.match(opcode) is not None:
-        result = self.SUB_OPERAND_RE.match(operand_text)
-        if result is not None:
-          stack_frame += int(result.group(1))
-        else:
-          # Unhandled stack register subtraction.
-          assert not operand_text.startswith('sp')
+            return None
 
-      elif self.STM_OPCODE_RE.match(opcode) is not None:
-        if operand_text.startswith('sp!'):
-          # Subtract and writeback to stack register.
-          # Example: "sp!, {r4, r5, r6, r7, r8, r9, lr}"
-          # Get the text of pushed register list.
-          unused_sp, unused_sep, parameter_text = operand_text.partition(',')
-          stack_frame += (len(parameter_text.split(',')) *
-                          self.GENERAL_PURPOSE_REGISTER_SIZE)
+        address = int(result.group("address"), 16)
+        # Check if it's out of bound.
+        if function_end is not None and address >= function_end:
+            return None
 
-    return (stack_frame, callsites)
+        opcode = result.group("opcode").strip()
+        operand_text = result.group("operand")
+        if operand_text is None:
+            operand_text = ""
+        else:
+            operand_text = operand_text.strip()
+
+        return (address, opcode, operand_text)
+
+    def AnalyzeFunction(self, function_symbol, instructions):
+
+        stack_frame = 0
+        callsites = []
+        for address, opcode, operand_text in instructions:
+            is_jump_opcode = self.JUMP_OPCODE_RE.match(opcode) is not None
+            is_call_opcode = self.CALL_OPCODE_RE.match(opcode) is not None
+
+            if is_jump_opcode or is_call_opcode:
+                is_tail = is_jump_opcode
+
+                result = self.CALL_OPERAND_RE.match(operand_text)
+                if result is None:
+                    if (
+                        self.INDIRECT_CALL_OPERAND_RE.match(operand_text)
+                        is not None
+                    ):
+                        # Found an indirect call.
+                        callsites.append(Callsite(address, None, is_tail))
+
+                else:
+                    # Capture address form operand_text and then convert to string
+                    address_str = "".join(
+                        self.CAPTURE_ADDRESS.findall(operand_text)
+                    )
+                    # String to integer
+                    target_address = int(address_str, 16)
+                    # Filter out the in-function target (branches and in-function calls,
+                    # which are actually branches).
+                    if not (
+                        function_symbol.size > 0
+                        and function_symbol.address
+                        < target_address
+                        < (function_symbol.address + function_symbol.size)
+                    ):
+                        # Maybe it is a callsite.
+                        callsites.append(
+                            Callsite(address, target_address, is_tail)
+                        )
+
+            elif self.ADDI_OPCODE_RE.match(opcode) is not None:
+                # Example: sp,sp,-32
+                if self.ADDI_OPERAND_RE.match(operand_text) is not None:
+                    stack_frame += abs(int(operand_text.split(",")[2]))
+
+        return (stack_frame, callsites)
 
 
 class StackAnalyzer(object):
-  """Class to analyze stack usage.
-
-  Public Methods:
-    Analyze: Run the stack analysis.
-  """
-
-  C_FUNCTION_NAME = r'_A-Za-z0-9'
-
-  # Assume there is no ":" in the path.
-  # Example: "driver/accel_kionix.c:321 (discriminator 3)"
-  ADDRTOLINE_RE = re.compile(
-      r'^(?P<path>[^:]+):(?P<linenum>\d+)(\s+\(discriminator\s+\d+\))?$')
-  # To eliminate the suffix appended by compilers, try to extract the
-  # C function name from the prefix of symbol name.
-  # Example: "SHA256_transform.constprop.28"
-  FUNCTION_PREFIX_NAME_RE = re.compile(
-      r'^(?P<name>[{0}]+)([^{0}].*)?$'.format(C_FUNCTION_NAME))
-
-  # Errors of annotation resolving.
-  ANNOTATION_ERROR_INVALID = 'invalid signature'
-  ANNOTATION_ERROR_NOTFOUND = 'function is not found'
-  ANNOTATION_ERROR_AMBIGUOUS = 'signature is ambiguous'
-
-  def __init__(self, options, symbols, rodata, tasklist, annotation):
-    """Constructor.
-
-    Args:
-      options: Namespace from argparse.parse_args().
-      symbols: Symbol list.
-      rodata: Content of .rodata section (offset, data)
-      tasklist: Task list.
-      annotation: Annotation config.
-    """
-    self.options = options
-    self.symbols = symbols
-    self.rodata_offset = rodata[0]
-    self.rodata = rodata[1]
-    self.tasklist = tasklist
-    self.annotation = annotation
-    self.address_to_line_cache = {}
-
-  def AddressToLine(self, address, resolve_inline=False):
-    """Convert address to line.
-
-    Args:
-      address: Target address.
-      resolve_inline: Output the stack of inlining.
-
-    Returns:
-      lines: List of the corresponding lines.
-
-    Raises:
-      StackAnalyzerError: If addr2line is failed.
-    """
-    cache_key = (address, resolve_inline)
-    if cache_key in self.address_to_line_cache:
-      return self.address_to_line_cache[cache_key]
-
-    try:
-      args = [self.options.addr2line,
-              '-f',
-              '-e',
-              self.options.elf_path,
-              '{:x}'.format(address)]
-      if resolve_inline:
-        args.append('-i')
-
-      line_text = subprocess.check_output(args, encoding='utf-8')
-    except subprocess.CalledProcessError:
-      raise StackAnalyzerError('addr2line failed to resolve lines.')
-    except OSError:
-      raise StackAnalyzerError('Failed to run addr2line.')
-
-    lines = [line.strip() for line in line_text.splitlines()]
-    # Assume the output has at least one pair like "function\nlocation\n", and
-    # they always show up in pairs.
-    # Example: "handle_request\n
-    #           common/usb_pd_protocol.c:1191\n"
-    assert len(lines) >= 2 and len(lines) % 2 == 0
-
-    line_infos = []
-    for index in range(0, len(lines), 2):
-      (function_name, line_text) = lines[index:index + 2]
-      if line_text in ['??:0', ':?']:
-        line_infos.append(None)
-      else:
-        result = self.ADDRTOLINE_RE.match(line_text)
-        # Assume the output is always well-formed.
-        assert result is not None
-        line_infos.append((function_name.strip(),
-                           os.path.realpath(result.group('path').strip()),
-                           int(result.group('linenum'))))
-
-    self.address_to_line_cache[cache_key] = line_infos
-    return line_infos
-
-  def AnalyzeDisassembly(self, disasm_text):
-    """Parse the disassembly text, analyze, and build a map of all functions.
-
-    Args:
-      disasm_text: Disassembly text.
-
-    Returns:
-      function_map: Dict of functions.
-    """
-    disasm_lines = [line.strip() for line in disasm_text.splitlines()]
-
-    if 'nds' in disasm_lines[1]:
-      analyzer = AndesAnalyzer()
-    elif 'arm' in disasm_lines[1]:
-      analyzer = ArmAnalyzer()
-    else:
-      raise StackAnalyzerError('Unsupported architecture.')
-
-    # Example: "08028c8c <motion_lid_calc>:"
-    function_signature_regex = re.compile(
-        r'^(?P<address>[0-9A-Fa-f]+)\s+<(?P<name>[^>]+)>:$')
-
-    def DetectFunctionHead(line):
-      """Check if the line is a function head.
-
-      Args:
-        line: Text of disassembly.
-
-      Returns:
-        symbol: Function symbol. None if it isn't a function head.
-      """
-      result = function_signature_regex.match(line)
-      if result is None:
-        return None
-
-      address = int(result.group('address'), 16)
-      symbol = symbol_map.get(address)
-
-      # Check if the function exists and matches.
-      if symbol is None or symbol.symtype != 'F':
-        return None
-
-      return symbol
-
-    # Build symbol map, indexed by symbol address.
-    symbol_map = {}
-    for symbol in self.symbols:
-      # If there are multiple symbols with same address, keeping any of them is
-      # good enough.
-      symbol_map[symbol.address] = symbol
-
-    # Parse the disassembly text. We update the variable "line" to next line
-    # when needed. There are two steps of parser:
-    #
-    # Step 1: Searching for the function head. Once reach the function head,
-    # move to the next line, which is the first line of function body.
-    #
-    # Step 2: Parsing each instruction line of function body. Once reach a
-    # non-instruction line, stop parsing and analyze the parsed instructions.
-    #
-    # Finally turn back to the step 1 without updating the line, because the
-    # current non-instruction line can be another function head.
-    function_map = {}
-    # The following three variables are the states of the parsing processing.
-    # They will be initialized properly during the state changes.
-    function_symbol = None
-    function_end = None
-    instructions = []
-
-    # Remove heading and tailing spaces for each line.
-    line_index = 0
-    while line_index < len(disasm_lines):
-      # Get the current line.
-      line = disasm_lines[line_index]
-
-      if function_symbol is None:
-        # Step 1: Search for the function head.
-
-        function_symbol = DetectFunctionHead(line)
-        if function_symbol is not None:
-          # Assume there is no empty function. If the function head is followed
-          # by EOF, it is an empty function.
-          assert line_index + 1 < len(disasm_lines)
-
-          # Found the function head, initialize and turn to the step 2.
-          instructions = []
-          # If symbol size exists, use it as a hint of function size.
-          if function_symbol.size > 0:
-            function_end = function_symbol.address + function_symbol.size
-          else:
-            function_end = None
-
-      else:
-        # Step 2: Parse the function body.
-
-        instruction = analyzer.ParseInstruction(line, function_end)
-        if instruction is not None:
-          instructions.append(instruction)
-
-        if instruction is None or line_index + 1 == len(disasm_lines):
-          # Either the invalid instruction or EOF indicates the end of the
-          # function, finalize the function analysis.
-
-          # Assume there is no empty function.
-          assert len(instructions) > 0
-
-          (stack_frame, callsites) = analyzer.AnalyzeFunction(function_symbol,
-                                                              instructions)
-          # Assume the function addresses are unique in the disassembly.
-          assert function_symbol.address not in function_map
-          function_map[function_symbol.address] = Function(
-              function_symbol.address,
-              function_symbol.name,
-              stack_frame,
-              callsites)
-
-          # Initialize and turn back to the step 1.
-          function_symbol = None
-
-          # If the current line isn't an instruction, it can be another function
-          # head, skip moving to the next line.
-          if instruction is None:
-            continue
+    """Class to analyze stack usage.
 
-      # Move to the next line.
-      line_index += 1
-
-    # Resolve callees of functions.
-    for function in function_map.values():
-      for callsite in function.callsites:
-        if callsite.target is not None:
-          # Remain the callee as None if we can't resolve it.
-          callsite.callee = function_map.get(callsite.target)
-
-    return function_map
-
-  def MapAnnotation(self, function_map, signature_set):
-    """Map annotation signatures to functions.
-
-    Args:
-      function_map: Function map.
-      signature_set: Set of annotation signatures.
-
-    Returns:
-      Map of signatures to functions, map of signatures which can't be resolved.
+    Public Methods:
+      Analyze: Run the stack analysis.
     """
-    # Build the symbol map indexed by symbol name. If there are multiple symbols
-    # with the same name, add them into a set. (e.g. symbols of static function
-    # with the same name)
-    symbol_map = collections.defaultdict(set)
-    for symbol in self.symbols:
-      if symbol.symtype == 'F':
-        # Function symbol.
-        result = self.FUNCTION_PREFIX_NAME_RE.match(symbol.name)
-        if result is not None:
-          function = function_map.get(symbol.address)
-          # Ignore the symbol not in disassembly.
-          if function is not None:
-            # If there are multiple symbol with the same name and point to the
-            # same function, the set will deduplicate them.
-            symbol_map[result.group('name').strip()].add(function)
-
-    # Build the signature map indexed by annotation signature.
-    signature_map = {}
-    sig_error_map = {}
-    symbol_path_map = {}
-    for sig in signature_set:
-      (name, path, _) = sig
-
-      functions = symbol_map.get(name)
-      if functions is None:
-        sig_error_map[sig] = self.ANNOTATION_ERROR_NOTFOUND
-        continue
-
-      if name not in symbol_path_map:
-        # Lazy symbol path resolving. Since the addr2line isn't fast, only
-        # resolve needed symbol paths.
-        group_map = collections.defaultdict(list)
-        for function in functions:
-          line_info = self.AddressToLine(function.address)[0]
-          if line_info is None:
-            continue
 
-          (_, symbol_path, _) = line_info
+    C_FUNCTION_NAME = r"_A-Za-z0-9"
 
-          # Group the functions with the same symbol signature (symbol name +
-          # symbol path). Assume they are the same copies and do the same
-          # annotation operations of them because we don't know which copy is
-          # indicated by the users.
-          group_map[symbol_path].append(function)
+    # Assume there is no ":" in the path.
+    # Example: "driver/accel_kionix.c:321 (discriminator 3)"
+    ADDRTOLINE_RE = re.compile(
+        r"^(?P<path>[^:]+):(?P<linenum>\d+)(\s+\(discriminator\s+\d+\))?$"
+    )
+    # To eliminate the suffix appended by compilers, try to extract the
+    # C function name from the prefix of symbol name.
+    # Example: "SHA256_transform.constprop.28"
+    FUNCTION_PREFIX_NAME_RE = re.compile(
+        r"^(?P<name>[{0}]+)([^{0}].*)?$".format(C_FUNCTION_NAME)
+    )
+
+    # Errors of annotation resolving.
+    ANNOTATION_ERROR_INVALID = "invalid signature"
+    ANNOTATION_ERROR_NOTFOUND = "function is not found"
+    ANNOTATION_ERROR_AMBIGUOUS = "signature is ambiguous"
+
+    def __init__(self, options, symbols, rodata, tasklist, annotation):
+        """Constructor.
+
+        Args:
+          options: Namespace from argparse.parse_args().
+          symbols: Symbol list.
+          rodata: Content of .rodata section (offset, data)
+          tasklist: Task list.
+          annotation: Annotation config.
+        """
+        self.options = options
+        self.symbols = symbols
+        self.rodata_offset = rodata[0]
+        self.rodata = rodata[1]
+        self.tasklist = tasklist
+        self.annotation = annotation
+        self.address_to_line_cache = {}
+
+    def AddressToLine(self, address, resolve_inline=False):
+        """Convert address to line.
+
+        Args:
+          address: Target address.
+          resolve_inline: Output the stack of inlining.
+
+        Returns:
+          lines: List of the corresponding lines.
+
+        Raises:
+          StackAnalyzerError: If addr2line is failed.
+        """
+        cache_key = (address, resolve_inline)
+        if cache_key in self.address_to_line_cache:
+            return self.address_to_line_cache[cache_key]
+
+        try:
+            args = [
+                self.options.addr2line,
+                "-f",
+                "-e",
+                self.options.elf_path,
+                "{:x}".format(address),
+            ]
+            if resolve_inline:
+                args.append("-i")
+
+            line_text = subprocess.check_output(args, encoding="utf-8")
+        except subprocess.CalledProcessError:
+            raise StackAnalyzerError("addr2line failed to resolve lines.")
+        except OSError:
+            raise StackAnalyzerError("Failed to run addr2line.")
+
+        lines = [line.strip() for line in line_text.splitlines()]
+        # Assume the output has at least one pair like "function\nlocation\n", and
+        # they always show up in pairs.
+        # Example: "handle_request\n
+        #           common/usb_pd_protocol.c:1191\n"
+        assert len(lines) >= 2 and len(lines) % 2 == 0
+
+        line_infos = []
+        for index in range(0, len(lines), 2):
+            (function_name, line_text) = lines[index : index + 2]
+            if line_text in ["??:0", ":?"]:
+                line_infos.append(None)
+            else:
+                result = self.ADDRTOLINE_RE.match(line_text)
+                # Assume the output is always well-formed.
+                assert result is not None
+                line_infos.append(
+                    (
+                        function_name.strip(),
+                        os.path.realpath(result.group("path").strip()),
+                        int(result.group("linenum")),
+                    )
+                )
+
+        self.address_to_line_cache[cache_key] = line_infos
+        return line_infos
+
+    def AnalyzeDisassembly(self, disasm_text):
+        """Parse the disassembly text, analyze, and build a map of all functions.
+
+        Args:
+          disasm_text: Disassembly text.
+
+        Returns:
+          function_map: Dict of functions.
+        """
+        disasm_lines = [line.strip() for line in disasm_text.splitlines()]
+
+        if "nds" in disasm_lines[1]:
+            analyzer = AndesAnalyzer()
+        elif "arm" in disasm_lines[1]:
+            analyzer = ArmAnalyzer()
+        elif "riscv" in disasm_lines[1]:
+            analyzer = RiscvAnalyzer()
+        else:
+            raise StackAnalyzerError("Unsupported architecture.")
 
-        symbol_path_map[name] = group_map
+        # Example: "08028c8c <motion_lid_calc>:"
+        function_signature_regex = re.compile(
+            r"^(?P<address>[0-9A-Fa-f]+)\s+<(?P<name>[^>]+)>:$"
+        )
 
-      # Symbol matching.
-      function_group = None
-      group_map = symbol_path_map[name]
-      if len(group_map) > 0:
-        if path is None:
-          if len(group_map) > 1:
-            # There is ambiguity but the path isn't specified.
-            sig_error_map[sig] = self.ANNOTATION_ERROR_AMBIGUOUS
-            continue
+        def DetectFunctionHead(line):
+            """Check if the line is a function head.
 
-          # No path signature but all symbol signatures of functions are same.
-          # Assume they are the same functions, so there is no ambiguity.
-          (function_group,) = group_map.values()
-        else:
-          function_group = group_map.get(path)
+            Args:
+              line: Text of disassembly.
 
-      if function_group is None:
-        sig_error_map[sig] = self.ANNOTATION_ERROR_NOTFOUND
-        continue
+            Returns:
+              symbol: Function symbol. None if it isn't a function head.
+            """
+            result = function_signature_regex.match(line)
+            if result is None:
+                return None
 
-      # The function_group is a list of all the same functions (according to
-      # our assumption) which should be annotated together.
-      signature_map[sig] = function_group
+            address = int(result.group("address"), 16)
+            symbol = symbol_map.get(address)
 
-    return (signature_map, sig_error_map)
+            # Check if the function exists and matches.
+            if symbol is None or symbol.symtype != "F":
+                return None
 
-  def LoadAnnotation(self):
-    """Load annotation rules.
+            return symbol
 
-    Returns:
-      Map of add rules, set of remove rules, set of text signatures which can't
-      be parsed.
-    """
-    # Assume there is no ":" in the path.
-    # Example: "get_range.lto.2501[driver/accel_kionix.c:327]"
-    annotation_signature_regex = re.compile(
-        r'^(?P<name>[^\[]+)(\[(?P<path>[^:]+)(:(?P<linenum>\d+))?\])?$')
-
-    def NormalizeSignature(signature_text):
-      """Parse and normalize the annotation signature.
-
-      Args:
-        signature_text: Text of the annotation signature.
-
-      Returns:
-        (function name, path, line number) of the signature. The path and line
-        number can be None if not exist. None if failed to parse.
-      """
-      result = annotation_signature_regex.match(signature_text.strip())
-      if result is None:
-        return None
-
-      name_result = self.FUNCTION_PREFIX_NAME_RE.match(
-          result.group('name').strip())
-      if name_result is None:
-        return None
-
-      path = result.group('path')
-      if path is not None:
-        path = os.path.realpath(path.strip())
-
-      linenum = result.group('linenum')
-      if linenum is not None:
-        linenum = int(linenum.strip())
-
-      return (name_result.group('name').strip(), path, linenum)
-
-    def ExpandArray(dic):
-      """Parse and expand a symbol array
-
-      Args:
-        dic: Dictionary for the array annotation
-
-      Returns:
-        array of (symbol name, None, None).
-      """
-      # TODO(drinkcat): This function is quite inefficient, as it goes through
-      # the symbol table multiple times.
-
-      begin_name = dic['name']
-      end_name = dic['name'] + "_end"
-      offset = dic['offset'] if 'offset' in dic else 0
-      stride = dic['stride']
-
-      begin_address = None
-      end_address = None
-
-      for symbol in self.symbols:
-        if (symbol.name == begin_name):
-          begin_address = symbol.address
-        if (symbol.name == end_name):
-          end_address = symbol.address
-
-      if (not begin_address or not end_address):
-        return None
-
-      output = []
-      # TODO(drinkcat): This is inefficient as we go from address to symbol
-      # object then to symbol name, and later on we'll go back from symbol name
-      # to symbol object.
-      for addr in range(begin_address+offset, end_address, stride):
-        # TODO(drinkcat): Not all architectures need to drop the first bit.
-        val = self.rodata[(addr-self.rodata_offset) // 4] & 0xfffffffe
-        name = None
+        # Build symbol map, indexed by symbol address.
+        symbol_map = {}
         for symbol in self.symbols:
-          if (symbol.address == val):
-            result = self.FUNCTION_PREFIX_NAME_RE.match(symbol.name)
-            name = result.group('name')
-            break
-
-        if not name:
-          raise StackAnalyzerError('Cannot find function for address %s.',
-                                   hex(val))
-
-        output.append((name, None, None))
-
-      return output
-
-    add_rules = collections.defaultdict(set)
-    remove_rules = list()
-    invalid_sigtxts = set()
-
-    if 'add' in self.annotation and self.annotation['add'] is not None:
-      for src_sigtxt, dst_sigtxts in self.annotation['add'].items():
-        src_sig = NormalizeSignature(src_sigtxt)
-        if src_sig is None:
-          invalid_sigtxts.add(src_sigtxt)
-          continue
-
-        for dst_sigtxt in dst_sigtxts:
-          if isinstance(dst_sigtxt, dict):
-            dst_sig = ExpandArray(dst_sigtxt)
-            if dst_sig is None:
-              invalid_sigtxts.add(str(dst_sigtxt))
+            # If there are multiple symbols with same address, keeping any of them is
+            # good enough.
+            symbol_map[symbol.address] = symbol
+
+        # Parse the disassembly text. We update the variable "line" to next line
+        # when needed. There are two steps of parser:
+        #
+        # Step 1: Searching for the function head. Once reach the function head,
+        # move to the next line, which is the first line of function body.
+        #
+        # Step 2: Parsing each instruction line of function body. Once reach a
+        # non-instruction line, stop parsing and analyze the parsed instructions.
+        #
+        # Finally turn back to the step 1 without updating the line, because the
+        # current non-instruction line can be another function head.
+        function_map = {}
+        # The following three variables are the states of the parsing processing.
+        # They will be initialized properly during the state changes.
+        function_symbol = None
+        function_end = None
+        instructions = []
+
+        # Remove heading and tailing spaces for each line.
+        line_index = 0
+        while line_index < len(disasm_lines):
+            # Get the current line.
+            line = disasm_lines[line_index]
+
+            if function_symbol is None:
+                # Step 1: Search for the function head.
+
+                function_symbol = DetectFunctionHead(line)
+                if function_symbol is not None:
+                    # Assume there is no empty function. If the function head is followed
+                    # by EOF, it is an empty function.
+                    assert line_index + 1 < len(disasm_lines)
+
+                    # Found the function head, initialize and turn to the step 2.
+                    instructions = []
+                    # If symbol size exists, use it as a hint of function size.
+                    if function_symbol.size > 0:
+                        function_end = (
+                            function_symbol.address + function_symbol.size
+                        )
+                    else:
+                        function_end = None
+
             else:
-              add_rules[src_sig].update(dst_sig)
-          else:
-            dst_sig = NormalizeSignature(dst_sigtxt)
-            if dst_sig is None:
-              invalid_sigtxts.add(dst_sigtxt)
+                # Step 2: Parse the function body.
+
+                instruction = analyzer.ParseInstruction(line, function_end)
+                if instruction is not None:
+                    instructions.append(instruction)
+
+                if instruction is None or line_index + 1 == len(disasm_lines):
+                    # Either the invalid instruction or EOF indicates the end of the
+                    # function, finalize the function analysis.
+
+                    # Assume there is no empty function.
+                    assert len(instructions) > 0
+
+                    (stack_frame, callsites) = analyzer.AnalyzeFunction(
+                        function_symbol, instructions
+                    )
+                    # Assume the function addresses are unique in the disassembly.
+                    assert function_symbol.address not in function_map
+                    function_map[function_symbol.address] = Function(
+                        function_symbol.address,
+                        function_symbol.name,
+                        stack_frame,
+                        callsites,
+                    )
+
+                    # Initialize and turn back to the step 1.
+                    function_symbol = None
+
+                    # If the current line isn't an instruction, it can be another function
+                    # head, skip moving to the next line.
+                    if instruction is None:
+                        continue
+
+            # Move to the next line.
+            line_index += 1
+
+        # Resolve callees of functions.
+        for function in function_map.values():
+            for callsite in function.callsites:
+                if callsite.target is not None:
+                    # Remain the callee as None if we can't resolve it.
+                    callsite.callee = function_map.get(callsite.target)
+
+        return function_map
+
+    def MapAnnotation(self, function_map, signature_set):
+        """Map annotation signatures to functions.
+
+        Args:
+          function_map: Function map.
+          signature_set: Set of annotation signatures.
+
+        Returns:
+          Map of signatures to functions, map of signatures which can't be resolved.
+        """
+        # Build the symbol map indexed by symbol name. If there are multiple symbols
+        # with the same name, add them into a set. (e.g. symbols of static function
+        # with the same name)
+        symbol_map = collections.defaultdict(set)
+        for symbol in self.symbols:
+            if symbol.symtype == "F":
+                # Function symbol.
+                result = self.FUNCTION_PREFIX_NAME_RE.match(symbol.name)
+                if result is not None:
+                    function = function_map.get(symbol.address)
+                    # Ignore the symbol not in disassembly.
+                    if function is not None:
+                        # If there are multiple symbol with the same name and point to the
+                        # same function, the set will deduplicate them.
+                        symbol_map[result.group("name").strip()].add(function)
+
+        # Build the signature map indexed by annotation signature.
+        signature_map = {}
+        sig_error_map = {}
+        symbol_path_map = {}
+        for sig in signature_set:
+            (name, path, _) = sig
+
+            functions = symbol_map.get(name)
+            if functions is None:
+                sig_error_map[sig] = self.ANNOTATION_ERROR_NOTFOUND
+                continue
+
+            if name not in symbol_path_map:
+                # Lazy symbol path resolving. Since the addr2line isn't fast, only
+                # resolve needed symbol paths.
+                group_map = collections.defaultdict(list)
+                for function in functions:
+                    line_info = self.AddressToLine(function.address)[0]
+                    if line_info is None:
+                        continue
+
+                    (_, symbol_path, _) = line_info
+
+                    # Group the functions with the same symbol signature (symbol name +
+                    # symbol path). Assume they are the same copies and do the same
+                    # annotation operations of them because we don't know which copy is
+                    # indicated by the users.
+                    group_map[symbol_path].append(function)
+
+                symbol_path_map[name] = group_map
+
+            # Symbol matching.
+            function_group = None
+            group_map = symbol_path_map[name]
+            if len(group_map) > 0:
+                if path is None:
+                    if len(group_map) > 1:
+                        # There is ambiguity but the path isn't specified.
+                        sig_error_map[sig] = self.ANNOTATION_ERROR_AMBIGUOUS
+                        continue
+
+                    # No path signature but all symbol signatures of functions are same.
+                    # Assume they are the same functions, so there is no ambiguity.
+                    (function_group,) = group_map.values()
+                else:
+                    function_group = group_map.get(path)
+
+            if function_group is None:
+                sig_error_map[sig] = self.ANNOTATION_ERROR_NOTFOUND
+                continue
+
+            # The function_group is a list of all the same functions (according to
+            # our assumption) which should be annotated together.
+            signature_map[sig] = function_group
+
+        return (signature_map, sig_error_map)
+
+    def LoadAnnotation(self):
+        """Load annotation rules.
+
+        Returns:
+          Map of add rules, set of remove rules, set of text signatures which can't
+          be parsed.
+        """
+        # Assume there is no ":" in the path.
+        # Example: "get_range.lto.2501[driver/accel_kionix.c:327]"
+        annotation_signature_regex = re.compile(
+            r"^(?P<name>[^\[]+)(\[(?P<path>[^:]+)(:(?P<linenum>\d+))?\])?$"
+        )
+
+        def NormalizeSignature(signature_text):
+            """Parse and normalize the annotation signature.
+
+            Args:
+              signature_text: Text of the annotation signature.
+
+            Returns:
+              (function name, path, line number) of the signature. The path and line
+              number can be None if not exist. None if failed to parse.
+            """
+            result = annotation_signature_regex.match(signature_text.strip())
+            if result is None:
+                return None
+
+            name_result = self.FUNCTION_PREFIX_NAME_RE.match(
+                result.group("name").strip()
+            )
+            if name_result is None:
+                return None
+
+            path = result.group("path")
+            if path is not None:
+                path = os.path.realpath(path.strip())
+
+            linenum = result.group("linenum")
+            if linenum is not None:
+                linenum = int(linenum.strip())
+
+            return (name_result.group("name").strip(), path, linenum)
+
+        def ExpandArray(dic):
+            """Parse and expand a symbol array
+
+            Args:
+              dic: Dictionary for the array annotation
+
+            Returns:
+              array of (symbol name, None, None).
+            """
+            # TODO(drinkcat): This function is quite inefficient, as it goes through
+            # the symbol table multiple times.
+
+            begin_name = dic["name"]
+            end_name = dic["name"] + "_end"
+            offset = dic["offset"] if "offset" in dic else 0
+            stride = dic["stride"]
+
+            begin_address = None
+            end_address = None
+
+            for symbol in self.symbols:
+                if symbol.name == begin_name:
+                    begin_address = symbol.address
+                if symbol.name == end_name:
+                    end_address = symbol.address
+
+            if not begin_address or not end_address:
+                return None
+
+            output = []
+            # TODO(drinkcat): This is inefficient as we go from address to symbol
+            # object then to symbol name, and later on we'll go back from symbol name
+            # to symbol object.
+            for addr in range(begin_address + offset, end_address, stride):
+                # TODO(drinkcat): Not all architectures need to drop the first bit.
+                val = self.rodata[(addr - self.rodata_offset) // 4] & 0xFFFFFFFE
+                name = None
+                for symbol in self.symbols:
+                    if symbol.address == val:
+                        result = self.FUNCTION_PREFIX_NAME_RE.match(symbol.name)
+                        name = result.group("name")
+                        break
+
+                if not name:
+                    raise StackAnalyzerError(
+                        "Cannot find function for address %s." % hex(val)
+                    )
+
+                output.append((name, None, None))
+
+            return output
+
+        add_rules = collections.defaultdict(set)
+        remove_rules = list()
+        invalid_sigtxts = set()
+
+        if "add" in self.annotation and self.annotation["add"] is not None:
+            for src_sigtxt, dst_sigtxts in self.annotation["add"].items():
+                src_sig = NormalizeSignature(src_sigtxt)
+                if src_sig is None:
+                    invalid_sigtxts.add(src_sigtxt)
+                    continue
+
+                for dst_sigtxt in dst_sigtxts:
+                    if isinstance(dst_sigtxt, dict):
+                        dst_sig = ExpandArray(dst_sigtxt)
+                        if dst_sig is None:
+                            invalid_sigtxts.add(str(dst_sigtxt))
+                        else:
+                            add_rules[src_sig].update(dst_sig)
+                    else:
+                        dst_sig = NormalizeSignature(dst_sigtxt)
+                        if dst_sig is None:
+                            invalid_sigtxts.add(dst_sigtxt)
+                        else:
+                            add_rules[src_sig].add(dst_sig)
+
+        if (
+            "remove" in self.annotation
+            and self.annotation["remove"] is not None
+        ):
+            for sigtxt_path in self.annotation["remove"]:
+                if isinstance(sigtxt_path, str):
+                    # The path has only one vertex.
+                    sigtxt_path = [sigtxt_path]
+
+                if len(sigtxt_path) == 0:
+                    continue
+
+                # Generate multiple remove paths from all the combinations of the
+                # signatures of each vertex.
+                sig_paths = [[]]
+                broken_flag = False
+                for sigtxt_node in sigtxt_path:
+                    if isinstance(sigtxt_node, str):
+                        # The vertex has only one signature.
+                        sigtxt_set = {sigtxt_node}
+                    elif isinstance(sigtxt_node, list):
+                        # The vertex has multiple signatures.
+                        sigtxt_set = set(sigtxt_node)
+                    else:
+                        # Assume the format of annotation is verified. There should be no
+                        # invalid case.
+                        assert False
+
+                    sig_set = set()
+                    for sigtxt in sigtxt_set:
+                        sig = NormalizeSignature(sigtxt)
+                        if sig is None:
+                            invalid_sigtxts.add(sigtxt)
+                            broken_flag = True
+                        elif not broken_flag:
+                            sig_set.add(sig)
+
+                    if broken_flag:
+                        continue
+
+                    # Append each signature of the current node to the all previous
+                    # remove paths.
+                    sig_paths = [
+                        path + [sig] for path in sig_paths for sig in sig_set
+                    ]
+
+                if not broken_flag:
+                    # All signatures are normalized. The remove path has no error.
+                    remove_rules.extend(sig_paths)
+
+        return (add_rules, remove_rules, invalid_sigtxts)
+
+    def ResolveAnnotation(self, function_map):
+        """Resolve annotation.
+
+        Args:
+          function_map: Function map.
+
+        Returns:
+          Set of added call edges, list of remove paths, set of eliminated
+          callsite addresses, set of annotation signatures which can't be resolved.
+        """
+
+        def StringifySignature(signature):
+            """Stringify the tupled signature.
+
+            Args:
+              signature: Tupled signature.
+
+            Returns:
+              Signature string.
+            """
+            (name, path, linenum) = signature
+            bracket_text = ""
+            if path is not None:
+                path = os.path.relpath(path)
+                if linenum is None:
+                    bracket_text = "[{}]".format(path)
+                else:
+                    bracket_text = "[{}:{}]".format(path, linenum)
+
+            return name + bracket_text
+
+        (add_rules, remove_rules, invalid_sigtxts) = self.LoadAnnotation()
+
+        signature_set = set()
+        for src_sig, dst_sigs in add_rules.items():
+            signature_set.add(src_sig)
+            signature_set.update(dst_sigs)
+
+        for remove_sigs in remove_rules:
+            signature_set.update(remove_sigs)
+
+        # Map signatures to functions.
+        (signature_map, sig_error_map) = self.MapAnnotation(
+            function_map, signature_set
+        )
+
+        # Build the indirect callsite map indexed by callsite signature.
+        indirect_map = collections.defaultdict(set)
+        for function in function_map.values():
+            for callsite in function.callsites:
+                if callsite.target is not None:
+                    continue
+
+                # Found an indirect callsite.
+                line_info = self.AddressToLine(callsite.address)[0]
+                if line_info is None:
+                    continue
+
+                (name, path, linenum) = line_info
+                result = self.FUNCTION_PREFIX_NAME_RE.match(name)
+                if result is None:
+                    continue
+
+                indirect_map[(result.group("name").strip(), path, linenum)].add(
+                    (function, callsite.address)
+                )
+
+        # Generate the annotation sets.
+        add_set = set()
+        remove_list = list()
+        eliminated_addrs = set()
+
+        for src_sig, dst_sigs in add_rules.items():
+            src_funcs = set(signature_map.get(src_sig, []))
+            # Try to match the source signature to the indirect callsites. Even if it
+            # can't be found in disassembly.
+            indirect_calls = indirect_map.get(src_sig)
+            if indirect_calls is not None:
+                for function, callsite_address in indirect_calls:
+                    # Add the caller of the indirect callsite to the source functions.
+                    src_funcs.add(function)
+                    # Assume each callsite can be represented by a unique address.
+                    eliminated_addrs.add(callsite_address)
+
+                if src_sig in sig_error_map:
+                    # Assume the error is always the not found error. Since the signature
+                    # found in indirect callsite map must be a full signature, it can't
+                    # happen the ambiguous error.
+                    assert (
+                        sig_error_map[src_sig] == self.ANNOTATION_ERROR_NOTFOUND
+                    )
+                    # Found in inline stack, remove the not found error.
+                    del sig_error_map[src_sig]
+
+            for dst_sig in dst_sigs:
+                dst_funcs = signature_map.get(dst_sig)
+                if dst_funcs is None:
+                    continue
+
+                # Duplicate the call edge for all the same source and destination
+                # functions.
+                for src_func in src_funcs:
+                    for dst_func in dst_funcs:
+                        add_set.add((src_func, dst_func))
+
+        for remove_sigs in remove_rules:
+            # Since each signature can be mapped to multiple functions, generate
+            # multiple remove paths from all the combinations of these functions.
+            remove_paths = [[]]
+            skip_flag = False
+            for remove_sig in remove_sigs:
+                # Transform each signature to the corresponding functions.
+                remove_funcs = signature_map.get(remove_sig)
+                if remove_funcs is None:
+                    # There is an unresolved signature in the remove path. Ignore the
+                    # whole broken remove path.
+                    skip_flag = True
+                    break
+                else:
+                    # Append each function of the current signature to the all previous
+                    # remove paths.
+                    remove_paths = [
+                        p + [f] for p in remove_paths for f in remove_funcs
+                    ]
+
+            if skip_flag:
+                # Ignore the broken remove path.
+                continue
+
+            for remove_path in remove_paths:
+                # Deduplicate the remove paths.
+                if remove_path not in remove_list:
+                    remove_list.append(remove_path)
+
+        # Format the error messages.
+        failed_sigtxts = set()
+        for sigtxt in invalid_sigtxts:
+            failed_sigtxts.add((sigtxt, self.ANNOTATION_ERROR_INVALID))
+
+        for sig, error in sig_error_map.items():
+            failed_sigtxts.add((StringifySignature(sig), error))
+
+        return (add_set, remove_list, eliminated_addrs, failed_sigtxts)
+
+    def PreprocessAnnotation(
+        self, function_map, add_set, remove_list, eliminated_addrs
+    ):
+        """Preprocess the annotation and callgraph.
+
+        Add the missing call edges, and delete simple remove paths (the paths have
+        one or two vertices) from the function_map.
+
+        Eliminate the annotated indirect callsites.
+
+        Return the remaining remove list.
+
+        Args:
+          function_map: Function map.
+          add_set: Set of missing call edges.
+          remove_list: List of remove paths.
+          eliminated_addrs: Set of eliminated callsite addresses.
+
+        Returns:
+          List of remaining remove paths.
+        """
+
+        def CheckEdge(path):
+            """Check if all edges of the path are on the callgraph.
+
+            Args:
+              path: Path.
+
+            Returns:
+              True or False.
+            """
+            for index in range(len(path) - 1):
+                if (path[index], path[index + 1]) not in edge_set:
+                    return False
+
+            return True
+
+        for src_func, dst_func in add_set:
+            # TODO(cheyuw): Support tailing call annotation.
+            src_func.callsites.append(
+                Callsite(None, dst_func.address, False, dst_func)
+            )
+
+        # Delete simple remove paths.
+        remove_simple = set(tuple(p) for p in remove_list if len(p) <= 2)
+        edge_set = set()
+        for function in function_map.values():
+            cleaned_callsites = []
+            for callsite in function.callsites:
+                if (callsite.callee,) in remove_simple or (
+                    function,
+                    callsite.callee,
+                ) in remove_simple:
+                    continue
+
+                if (
+                    callsite.target is None
+                    and callsite.address in eliminated_addrs
+                ):
+                    continue
+
+                cleaned_callsites.append(callsite)
+                if callsite.callee is not None:
+                    edge_set.add((function, callsite.callee))
+
+            function.callsites = cleaned_callsites
+
+        return [p for p in remove_list if len(p) >= 3 and CheckEdge(p)]
+
+    def AnalyzeCallGraph(self, function_map, remove_list):
+        """Analyze callgraph.
+
+        It will update the max stack size and path for each function.
+
+        Args:
+          function_map: Function map.
+          remove_list: List of remove paths.
+
+        Returns:
+          List of function cycles.
+        """
+
+        def Traverse(curr_state):
+            """Traverse the callgraph and calculate the max stack usages of functions.
+
+            Args:
+              curr_state: Current state.
+
+            Returns:
+              SCC lowest link.
+            """
+            scc_index = scc_index_counter[0]
+            scc_index_counter[0] += 1
+            scc_index_map[curr_state] = scc_index
+            scc_lowlink = scc_index
+            scc_stack.append(curr_state)
+            # Push the current state in the stack. We can use a set to maintain this
+            # because the stacked states are unique; otherwise we will find a cycle
+            # first.
+            stacked_states.add(curr_state)
+
+            (curr_address, curr_positions) = curr_state
+            curr_func = function_map[curr_address]
+
+            invalid_flag = False
+            new_positions = list(curr_positions)
+            for index, position in enumerate(curr_positions):
+                remove_path = remove_list[index]
+
+                # The position of each remove path in the state is the length of the
+                # longest matching path between the prefix of the remove path and the
+                # suffix of the current traversing path. We maintain this length when
+                # appending the next callee to the traversing path. And it can be used
+                # to check if the remove path appears in the traversing path.
+
+                # TODO(cheyuw): Implement KMP algorithm to match remove paths
+                #               efficiently.
+                if remove_path[position] is curr_func:
+                    # Matches the current function, extend the length.
+                    new_positions[index] = position + 1
+                    if new_positions[index] == len(remove_path):
+                        # The length of the longest matching path is equal to the length of
+                        # the remove path, which means the suffix of the current traversing
+                        # path matches the remove path.
+                        invalid_flag = True
+                        break
+
+                else:
+                    # We can't get the new longest matching path by extending the previous
+                    # one directly. Fallback to search the new longest matching path.
+
+                    # If we can't find any matching path in the following search, reset
+                    # the matching length to 0.
+                    new_positions[index] = 0
+
+                    # We want to find the new longest matching prefix of remove path with
+                    # the suffix of the current traversing path. Because the new longest
+                    # matching path won't be longer than the prevous one now, and part of
+                    # the suffix matches the prefix of remove path, we can get the needed
+                    # suffix from the previous matching prefix of the invalid path.
+                    suffix = remove_path[:position] + [curr_func]
+                    for offset in range(1, len(suffix)):
+                        length = position - offset
+                        if remove_path[:length] == suffix[offset:]:
+                            new_positions[index] = length
+                            break
+
+            new_positions = tuple(new_positions)
+
+            # If the current suffix is invalid, set the max stack usage to 0.
+            max_stack_usage = 0
+            max_callee_state = None
+            self_loop = False
+
+            if not invalid_flag:
+                # Max stack usage is at least equal to the stack frame.
+                max_stack_usage = curr_func.stack_frame
+                for callsite in curr_func.callsites:
+                    callee = callsite.callee
+                    if callee is None:
+                        continue
+
+                    callee_state = (callee.address, new_positions)
+                    if callee_state not in scc_index_map:
+                        # Unvisited state.
+                        scc_lowlink = min(scc_lowlink, Traverse(callee_state))
+                    elif callee_state in stacked_states:
+                        # The state is shown in the stack. There is a cycle.
+                        sub_stack_usage = 0
+                        scc_lowlink = min(
+                            scc_lowlink, scc_index_map[callee_state]
+                        )
+                        if callee_state == curr_state:
+                            self_loop = True
+
+                    done_result = done_states.get(callee_state)
+                    if done_result is not None:
+                        # Already done this state and use its result. If the state reaches a
+                        # cycle, reusing the result will cause inaccuracy (the stack usage
+                        # of cycle depends on where the entrance is). But it's fine since we
+                        # can't get accurate stack usage under this situation, and we rely
+                        # on user-provided annotations to break the cycle, after which the
+                        # result will be accurate again.
+                        (sub_stack_usage, _) = done_result
+
+                        if callsite.is_tail:
+                            # For tailing call, since the callee reuses the stack frame of the
+                            # caller, choose the larger one directly.
+                            stack_usage = max(
+                                curr_func.stack_frame, sub_stack_usage
+                            )
+                        else:
+                            stack_usage = (
+                                curr_func.stack_frame + sub_stack_usage
+                            )
+
+                        if stack_usage > max_stack_usage:
+                            max_stack_usage = stack_usage
+                            max_callee_state = callee_state
+
+            if scc_lowlink == scc_index:
+                group = []
+                while scc_stack[-1] != curr_state:
+                    scc_state = scc_stack.pop()
+                    stacked_states.remove(scc_state)
+                    group.append(scc_state)
+
+                scc_stack.pop()
+                stacked_states.remove(curr_state)
+
+                # If the cycle is not empty, record it.
+                if len(group) > 0 or self_loop:
+                    group.append(curr_state)
+                    cycle_groups.append(group)
+
+            # Store the done result.
+            done_states[curr_state] = (max_stack_usage, max_callee_state)
+
+            if curr_positions == initial_positions:
+                # If the current state is initial state, we traversed the callgraph by
+                # using the current function as start point. Update the stack usage of
+                # the function.
+                # If the function matches a single vertex remove path, this will set its
+                # max stack usage to 0, which is not expected (we still calculate its
+                # max stack usage, but prevent any function from calling it). However,
+                # all the single vertex remove paths have been preprocessed and removed.
+                curr_func.stack_max_usage = max_stack_usage
+
+                # Reconstruct the max stack path by traversing the state transitions.
+                max_stack_path = [curr_func]
+                callee_state = max_callee_state
+                while callee_state is not None:
+                    # The first element of state tuple is function address.
+                    max_stack_path.append(function_map[callee_state[0]])
+                    done_result = done_states.get(callee_state)
+                    # All of the descendants should be done.
+                    assert done_result is not None
+                    (_, callee_state) = done_result
+
+                curr_func.stack_max_path = max_stack_path
+
+            return scc_lowlink
+
+        # The state is the concatenation of the current function address and the
+        # state of matching position.
+        initial_positions = (0,) * len(remove_list)
+        done_states = {}
+        stacked_states = set()
+        scc_index_counter = [0]
+        scc_index_map = {}
+        scc_stack = []
+        cycle_groups = []
+        for function in function_map.values():
+            if function.stack_max_usage is None:
+                Traverse((function.address, initial_positions))
+
+        cycle_functions = []
+        for group in cycle_groups:
+            cycle = set(function_map[state[0]] for state in group)
+            if cycle not in cycle_functions:
+                cycle_functions.append(cycle)
+
+        return cycle_functions
+
+    def Analyze(self):
+        """Run the stack analysis.
+
+        Raises:
+          StackAnalyzerError: If disassembly fails.
+        """
+
+        def OutputInlineStack(address, prefix=""):
+            """Output beautiful inline stack.
+
+            Args:
+              address: Address.
+              prefix: Prefix of each line.
+
+            Returns:
+              Key for sorting, output text
+            """
+            line_infos = self.AddressToLine(address, True)
+
+            if line_infos[0] is None:
+                order_key = (None, None)
             else:
-              add_rules[src_sig].add(dst_sig)
-
-    if 'remove' in self.annotation and self.annotation['remove'] is not None:
-      for sigtxt_path in self.annotation['remove']:
-        if isinstance(sigtxt_path, str):
-          # The path has only one vertex.
-          sigtxt_path = [sigtxt_path]
-
-        if len(sigtxt_path) == 0:
-          continue
-
-        # Generate multiple remove paths from all the combinations of the
-        # signatures of each vertex.
-        sig_paths = [[]]
-        broken_flag = False
-        for sigtxt_node in sigtxt_path:
-          if isinstance(sigtxt_node, str):
-            # The vertex has only one signature.
-            sigtxt_set = {sigtxt_node}
-          elif isinstance(sigtxt_node, list):
-            # The vertex has multiple signatures.
-            sigtxt_set = set(sigtxt_node)
-          else:
-            # Assume the format of annotation is verified. There should be no
-            # invalid case.
-            assert False
-
-          sig_set = set()
-          for sigtxt in sigtxt_set:
-            sig = NormalizeSignature(sigtxt)
-            if sig is None:
-              invalid_sigtxts.add(sigtxt)
-              broken_flag = True
-            elif not broken_flag:
-              sig_set.add(sig)
-
-          if broken_flag:
-            continue
+                (_, path, linenum) = line_infos[0]
+                order_key = (linenum, path)
+
+            line_texts = []
+            for line_info in reversed(line_infos):
+                if line_info is None:
+                    (function_name, path, linenum) = ("??", "??", 0)
+                else:
+                    (function_name, path, linenum) = line_info
+
+                line_texts.append(
+                    "{}[{}:{}]".format(
+                        function_name, os.path.relpath(path), linenum
+                    )
+                )
+
+            output = "{}-> {} {:x}\n".format(prefix, line_texts[0], address)
+            for depth, line_text in enumerate(line_texts[1:]):
+                output += "{}   {}- {}\n".format(
+                    prefix, "  " * depth, line_text
+                )
+
+            # Remove the last newline character.
+            return (order_key, output.rstrip("\n"))
+
+        # Analyze disassembly.
+        try:
+            disasm_text = subprocess.check_output(
+                [self.options.objdump, "-d", self.options.elf_path],
+                encoding="utf-8",
+            )
+        except subprocess.CalledProcessError:
+            raise StackAnalyzerError("objdump failed to disassemble.")
+        except OSError:
+            raise StackAnalyzerError("Failed to run objdump.")
+
+        function_map = self.AnalyzeDisassembly(disasm_text)
+        result = self.ResolveAnnotation(function_map)
+        (add_set, remove_list, eliminated_addrs, failed_sigtxts) = result
+        remove_list = self.PreprocessAnnotation(
+            function_map, add_set, remove_list, eliminated_addrs
+        )
+        cycle_functions = self.AnalyzeCallGraph(function_map, remove_list)
+
+        # Print the results of task-aware stack analysis.
+        extra_stack_frame = self.annotation.get(
+            "exception_frame_size", DEFAULT_EXCEPTION_FRAME_SIZE
+        )
+        for task in self.tasklist:
+            routine_func = function_map[task.routine_address]
+            print(
+                "Task: {}, Max size: {} ({} + {}), Allocated size: {}".format(
+                    task.name,
+                    routine_func.stack_max_usage + extra_stack_frame,
+                    routine_func.stack_max_usage,
+                    extra_stack_frame,
+                    task.stack_max_size,
+                )
+            )
+
+            print("Call Trace:")
+            max_stack_path = routine_func.stack_max_path
+            # Assume the routine function is resolved.
+            assert max_stack_path is not None
+            for depth, curr_func in enumerate(max_stack_path):
+                line_info = self.AddressToLine(curr_func.address)[0]
+                if line_info is None:
+                    (path, linenum) = ("??", 0)
+                else:
+                    (_, path, linenum) = line_info
+
+                print(
+                    "    {} ({}) [{}:{}] {:x}".format(
+                        curr_func.name,
+                        curr_func.stack_frame,
+                        os.path.relpath(path),
+                        linenum,
+                        curr_func.address,
+                    )
+                )
+
+                if depth + 1 < len(max_stack_path):
+                    succ_func = max_stack_path[depth + 1]
+                    text_list = []
+                    for callsite in curr_func.callsites:
+                        if callsite.callee is succ_func:
+                            indent_prefix = "        "
+                            if callsite.address is None:
+                                order_text = (
+                                    None,
+                                    "{}-> [annotation]".format(indent_prefix),
+                                )
+                            else:
+                                order_text = OutputInlineStack(
+                                    callsite.address, indent_prefix
+                                )
+
+                            text_list.append(order_text)
+
+                    for _, text in sorted(text_list, key=lambda item: item[0]):
+                        print(text)
+
+        print("Unresolved indirect callsites:")
+        for function in function_map.values():
+            indirect_callsites = []
+            for callsite in function.callsites:
+                if callsite.target is None:
+                    indirect_callsites.append(callsite.address)
+
+            if len(indirect_callsites) > 0:
+                print("    In function {}:".format(function.name))
+                text_list = []
+                for address in indirect_callsites:
+                    text_list.append(OutputInlineStack(address, "        "))
+
+                for _, text in sorted(text_list, key=lambda item: item[0]):
+                    print(text)
+
+        print("Unresolved annotation signatures:")
+        for sigtxt, error in failed_sigtxts:
+            print("    {}: {}".format(sigtxt, error))
+
+        if len(cycle_functions) > 0:
+            print("There are cycles in the following function sets:")
+            for functions in cycle_functions:
+                print(
+                    "[{}]".format(
+                        ", ".join(function.name for function in functions)
+                    )
+                )
 
-          # Append each signature of the current node to the all previous
-          # remove paths.
-          sig_paths = [path + [sig] for path in sig_paths for sig in sig_set]
 
-        if not broken_flag:
-          # All signatures are normalized. The remove path has no error.
-          remove_rules.extend(sig_paths)
-
-    return (add_rules, remove_rules, invalid_sigtxts)
-
-  def ResolveAnnotation(self, function_map):
-    """Resolve annotation.
-
-    Args:
-      function_map: Function map.
+def ParseArgs():
+    """Parse commandline arguments.
 
     Returns:
-      Set of added call edges, list of remove paths, set of eliminated
-      callsite addresses, set of annotation signatures which can't be resolved.
+      options: Namespace from argparse.parse_args().
     """
-    def StringifySignature(signature):
-      """Stringify the tupled signature.
-
-      Args:
-        signature: Tupled signature.
-
-      Returns:
-        Signature string.
-      """
-      (name, path, linenum) = signature
-      bracket_text = ''
-      if path is not None:
-        path = os.path.relpath(path)
-        if linenum is None:
-          bracket_text = '[{}]'.format(path)
-        else:
-          bracket_text = '[{}:{}]'.format(path, linenum)
-
-      return name + bracket_text
-
-    (add_rules, remove_rules, invalid_sigtxts) = self.LoadAnnotation()
-
-    signature_set = set()
-    for src_sig, dst_sigs in add_rules.items():
-      signature_set.add(src_sig)
-      signature_set.update(dst_sigs)
-
-    for remove_sigs in remove_rules:
-      signature_set.update(remove_sigs)
-
-    # Map signatures to functions.
-    (signature_map, sig_error_map) = self.MapAnnotation(function_map,
-                                                        signature_set)
-
-    # Build the indirect callsite map indexed by callsite signature.
-    indirect_map = collections.defaultdict(set)
-    for function in function_map.values():
-      for callsite in function.callsites:
-        if callsite.target is not None:
-          continue
-
-        # Found an indirect callsite.
-        line_info = self.AddressToLine(callsite.address)[0]
-        if line_info is None:
-          continue
-
-        (name, path, linenum) = line_info
-        result = self.FUNCTION_PREFIX_NAME_RE.match(name)
-        if result is None:
-          continue
-
-        indirect_map[(result.group('name').strip(), path, linenum)].add(
-            (function, callsite.address))
-
-    # Generate the annotation sets.
-    add_set = set()
-    remove_list = list()
-    eliminated_addrs = set()
-
-    for src_sig, dst_sigs in add_rules.items():
-      src_funcs = set(signature_map.get(src_sig, []))
-      # Try to match the source signature to the indirect callsites. Even if it
-      # can't be found in disassembly.
-      indirect_calls = indirect_map.get(src_sig)
-      if indirect_calls is not None:
-        for function, callsite_address in indirect_calls:
-          # Add the caller of the indirect callsite to the source functions.
-          src_funcs.add(function)
-          # Assume each callsite can be represented by a unique address.
-          eliminated_addrs.add(callsite_address)
-
-        if src_sig in sig_error_map:
-          # Assume the error is always the not found error. Since the signature
-          # found in indirect callsite map must be a full signature, it can't
-          # happen the ambiguous error.
-          assert sig_error_map[src_sig] == self.ANNOTATION_ERROR_NOTFOUND
-          # Found in inline stack, remove the not found error.
-          del sig_error_map[src_sig]
-
-      for dst_sig in dst_sigs:
-        dst_funcs = signature_map.get(dst_sig)
-        if dst_funcs is None:
-          continue
-
-        # Duplicate the call edge for all the same source and destination
-        # functions.
-        for src_func in src_funcs:
-          for dst_func in dst_funcs:
-            add_set.add((src_func, dst_func))
-
-    for remove_sigs in remove_rules:
-      # Since each signature can be mapped to multiple functions, generate
-      # multiple remove paths from all the combinations of these functions.
-      remove_paths = [[]]
-      skip_flag = False
-      for remove_sig in remove_sigs:
-        # Transform each signature to the corresponding functions.
-        remove_funcs = signature_map.get(remove_sig)
-        if remove_funcs is None:
-          # There is an unresolved signature in the remove path. Ignore the
-          # whole broken remove path.
-          skip_flag = True
-          break
-        else:
-          # Append each function of the current signature to the all previous
-          # remove paths.
-          remove_paths = [p + [f] for p in remove_paths for f in remove_funcs]
-
-      if skip_flag:
-        # Ignore the broken remove path.
-        continue
-
-      for remove_path in remove_paths:
-        # Deduplicate the remove paths.
-        if remove_path not in remove_list:
-          remove_list.append(remove_path)
+    parser = argparse.ArgumentParser(description="EC firmware stack analyzer.")
+    parser.add_argument("elf_path", help="the path of EC firmware ELF")
+    parser.add_argument(
+        "--export_taskinfo",
+        required=True,
+        help="the path of export_taskinfo.so utility",
+    )
+    parser.add_argument(
+        "--section",
+        required=True,
+        help="the section.",
+        choices=[SECTION_RO, SECTION_RW],
+    )
+    parser.add_argument(
+        "--objdump", default="objdump", help="the path of objdump"
+    )
+    parser.add_argument(
+        "--addr2line", default="addr2line", help="the path of addr2line"
+    )
+    parser.add_argument(
+        "--annotation", default=None, help="the path of annotation file"
+    )
+
+    # TODO(cheyuw): Add an option for dumping stack usage of all functions.
+
+    return parser.parse_args()
 
-    # Format the error messages.
-    failed_sigtxts = set()
-    for sigtxt in invalid_sigtxts:
-      failed_sigtxts.add((sigtxt, self.ANNOTATION_ERROR_INVALID))
 
-    for sig, error in sig_error_map.items():
-      failed_sigtxts.add((StringifySignature(sig), error))
-
-    return (add_set, remove_list, eliminated_addrs, failed_sigtxts)
-
-  def PreprocessAnnotation(self, function_map, add_set, remove_list,
-                           eliminated_addrs):
-    """Preprocess the annotation and callgraph.
-
-    Add the missing call edges, and delete simple remove paths (the paths have
-    one or two vertices) from the function_map.
-
-    Eliminate the annotated indirect callsites.
-
-    Return the remaining remove list.
+def ParseSymbolText(symbol_text):
+    """Parse the content of the symbol text.
 
     Args:
-      function_map: Function map.
-      add_set: Set of missing call edges.
-      remove_list: List of remove paths.
-      eliminated_addrs: Set of eliminated callsite addresses.
+      symbol_text: Text of the symbols.
 
     Returns:
-      List of remaining remove paths.
+      symbols: Symbol list.
     """
-    def CheckEdge(path):
-      """Check if all edges of the path are on the callgraph.
-
-      Args:
-        path: Path.
-
-      Returns:
-        True or False.
-      """
-      for index in range(len(path) - 1):
-        if (path[index], path[index + 1]) not in edge_set:
-          return False
-
-      return True
-
-    for src_func, dst_func in add_set:
-      # TODO(cheyuw): Support tailing call annotation.
-      src_func.callsites.append(
-          Callsite(None, dst_func.address, False, dst_func))
-
-    # Delete simple remove paths.
-    remove_simple = set(tuple(p) for p in remove_list if len(p) <= 2)
-    edge_set = set()
-    for function in function_map.values():
-      cleaned_callsites = []
-      for callsite in function.callsites:
-        if ((callsite.callee,) in remove_simple or
-            (function, callsite.callee) in remove_simple):
-          continue
-
-        if callsite.target is None and callsite.address in eliminated_addrs:
-          continue
-
-        cleaned_callsites.append(callsite)
-        if callsite.callee is not None:
-          edge_set.add((function, callsite.callee))
+    # Example: "10093064 g     F .text  0000015c .hidden hook_task"
+    symbol_regex = re.compile(
+        r"^(?P<address>[0-9A-Fa-f]+)\s+[lwg]\s+"
+        r"((?P<type>[OF])\s+)?\S+\s+"
+        r"(?P<size>[0-9A-Fa-f]+)\s+"
+        r"(\S+\s+)?(?P<name>\S+)$"
+    )
+
+    symbols = []
+    for line in symbol_text.splitlines():
+        line = line.strip()
+        result = symbol_regex.match(line)
+        if result is not None:
+            address = int(result.group("address"), 16)
+            symtype = result.group("type")
+            if symtype is None:
+                symtype = "O"
 
-      function.callsites = cleaned_callsites
+            size = int(result.group("size"), 16)
+            name = result.group("name")
+            symbols.append(Symbol(address, symtype, size, name))
 
-    return [p for p in remove_list if len(p) >= 3 and CheckEdge(p)]
+    return symbols
 
-  def AnalyzeCallGraph(self, function_map, remove_list):
-    """Analyze callgraph.
 
-    It will update the max stack size and path for each function.
+def ParseRoDataText(rodata_text):
+    """Parse the content of rodata
 
     Args:
-      function_map: Function map.
-      remove_list: List of remove paths.
+      symbol_text: Text of the rodata dump.
 
     Returns:
-      List of function cycles.
+      symbols: Symbol list.
     """
-    def Traverse(curr_state):
-      """Traverse the callgraph and calculate the max stack usages of functions.
-
-      Args:
-        curr_state: Current state.
-
-      Returns:
-        SCC lowest link.
-      """
-      scc_index = scc_index_counter[0]
-      scc_index_counter[0] += 1
-      scc_index_map[curr_state] = scc_index
-      scc_lowlink = scc_index
-      scc_stack.append(curr_state)
-      # Push the current state in the stack. We can use a set to maintain this
-      # because the stacked states are unique; otherwise we will find a cycle
-      # first.
-      stacked_states.add(curr_state)
-
-      (curr_address, curr_positions) = curr_state
-      curr_func = function_map[curr_address]
-
-      invalid_flag = False
-      new_positions = list(curr_positions)
-      for index, position in enumerate(curr_positions):
-        remove_path = remove_list[index]
-
-        # The position of each remove path in the state is the length of the
-        # longest matching path between the prefix of the remove path and the
-        # suffix of the current traversing path. We maintain this length when
-        # appending the next callee to the traversing path. And it can be used
-        # to check if the remove path appears in the traversing path.
-
-        # TODO(cheyuw): Implement KMP algorithm to match remove paths
-        #               efficiently.
-        if remove_path[position] is curr_func:
-          # Matches the current function, extend the length.
-          new_positions[index] = position + 1
-          if new_positions[index] == len(remove_path):
-            # The length of the longest matching path is equal to the length of
-            # the remove path, which means the suffix of the current traversing
-            # path matches the remove path.
-            invalid_flag = True
-            break
-
-        else:
-          # We can't get the new longest matching path by extending the previous
-          # one directly. Fallback to search the new longest matching path.
-
-          # If we can't find any matching path in the following search, reset
-          # the matching length to 0.
-          new_positions[index] = 0
-
-          # We want to find the new longest matching prefix of remove path with
-          # the suffix of the current traversing path. Because the new longest
-          # matching path won't be longer than the prevous one now, and part of
-          # the suffix matches the prefix of remove path, we can get the needed
-          # suffix from the previous matching prefix of the invalid path.
-          suffix = remove_path[:position] + [curr_func]
-          for offset in range(1, len(suffix)):
-            length = position - offset
-            if remove_path[:length] == suffix[offset:]:
-              new_positions[index] = length
-              break
-
-      new_positions = tuple(new_positions)
-
-      # If the current suffix is invalid, set the max stack usage to 0.
-      max_stack_usage = 0
-      max_callee_state = None
-      self_loop = False
-
-      if not invalid_flag:
-        # Max stack usage is at least equal to the stack frame.
-        max_stack_usage = curr_func.stack_frame
-        for callsite in curr_func.callsites:
-          callee = callsite.callee
-          if callee is None:
+    # Examples: 8018ab0 00040048 00010000 10020000 4b8e0108  ...H........K...
+    #           100a7294 00000000 00000000 01000000           ............
+
+    base_offset = None
+    offset = None
+    rodata = []
+    for line in rodata_text.splitlines():
+        line = line.strip()
+        space = line.find(" ")
+        if space < 0:
+            continue
+        try:
+            address = int(line[0:space], 16)
+        except ValueError:
             continue
 
-          callee_state = (callee.address, new_positions)
-          if callee_state not in scc_index_map:
-            # Unvisited state.
-            scc_lowlink = min(scc_lowlink, Traverse(callee_state))
-          elif callee_state in stacked_states:
-            # The state is shown in the stack. There is a cycle.
-            sub_stack_usage = 0
-            scc_lowlink = min(scc_lowlink, scc_index_map[callee_state])
-            if callee_state == curr_state:
-              self_loop = True
-
-          done_result = done_states.get(callee_state)
-          if done_result is not None:
-            # Already done this state and use its result. If the state reaches a
-            # cycle, reusing the result will cause inaccuracy (the stack usage
-            # of cycle depends on where the entrance is). But it's fine since we
-            # can't get accurate stack usage under this situation, and we rely
-            # on user-provided annotations to break the cycle, after which the
-            # result will be accurate again.
-            (sub_stack_usage, _) = done_result
-
-            if callsite.is_tail:
-              # For tailing call, since the callee reuses the stack frame of the
-              # caller, choose the larger one directly.
-              stack_usage = max(curr_func.stack_frame, sub_stack_usage)
-            else:
-              stack_usage = curr_func.stack_frame + sub_stack_usage
-
-            if stack_usage > max_stack_usage:
-              max_stack_usage = stack_usage
-              max_callee_state = callee_state
-
-      if scc_lowlink == scc_index:
-        group = []
-        while scc_stack[-1] != curr_state:
-          scc_state = scc_stack.pop()
-          stacked_states.remove(scc_state)
-          group.append(scc_state)
-
-        scc_stack.pop()
-        stacked_states.remove(curr_state)
-
-        # If the cycle is not empty, record it.
-        if len(group) > 0 or self_loop:
-          group.append(curr_state)
-          cycle_groups.append(group)
-
-      # Store the done result.
-      done_states[curr_state] = (max_stack_usage, max_callee_state)
-
-      if curr_positions == initial_positions:
-        # If the current state is initial state, we traversed the callgraph by
-        # using the current function as start point. Update the stack usage of
-        # the function.
-        # If the function matches a single vertex remove path, this will set its
-        # max stack usage to 0, which is not expected (we still calculate its
-        # max stack usage, but prevent any function from calling it). However,
-        # all the single vertex remove paths have been preprocessed and removed.
-        curr_func.stack_max_usage = max_stack_usage
-
-        # Reconstruct the max stack path by traversing the state transitions.
-        max_stack_path = [curr_func]
-        callee_state = max_callee_state
-        while callee_state is not None:
-          # The first element of state tuple is function address.
-          max_stack_path.append(function_map[callee_state[0]])
-          done_result = done_states.get(callee_state)
-          # All of the descendants should be done.
-          assert done_result is not None
-          (_, callee_state) = done_result
-
-        curr_func.stack_max_path = max_stack_path
-
-      return scc_lowlink
-
-    # The state is the concatenation of the current function address and the
-    # state of matching position.
-    initial_positions = (0,) * len(remove_list)
-    done_states = {}
-    stacked_states = set()
-    scc_index_counter = [0]
-    scc_index_map = {}
-    scc_stack = []
-    cycle_groups = []
-    for function in function_map.values():
-      if function.stack_max_usage is None:
-        Traverse((function.address, initial_positions))
-
-    cycle_functions = []
-    for group in cycle_groups:
-      cycle = set(function_map[state[0]] for state in group)
-      if cycle not in cycle_functions:
-        cycle_functions.append(cycle)
-
-    return cycle_functions
-
-  def Analyze(self):
-    """Run the stack analysis.
-
-    Raises:
-      StackAnalyzerError: If disassembly fails.
-    """
-    def OutputInlineStack(address, prefix=''):
-      """Output beautiful inline stack.
-
-      Args:
-        address: Address.
-        prefix: Prefix of each line.
-
-      Returns:
-        Key for sorting, output text
-      """
-      line_infos = self.AddressToLine(address, True)
-
-      if line_infos[0] is None:
-        order_key = (None, None)
-      else:
-        (_, path, linenum) = line_infos[0]
-        order_key = (linenum, path)
-
-      line_texts = []
-      for line_info in reversed(line_infos):
-        if line_info is None:
-          (function_name, path, linenum) = ('??', '??', 0)
-        else:
-          (function_name, path, linenum) = line_info
-
-        line_texts.append('{}[{}:{}]'.format(function_name,
-                                             os.path.relpath(path),
-                                             linenum))
-
-      output = '{}-> {} {:x}\n'.format(prefix, line_texts[0], address)
-      for depth, line_text in enumerate(line_texts[1:]):
-        output += '{}   {}- {}\n'.format(prefix, '  ' * depth, line_text)
-
-      # Remove the last newline character.
-      return (order_key, output.rstrip('\n'))
-
-    # Analyze disassembly.
-    try:
-      disasm_text = subprocess.check_output([self.options.objdump,
-                                             '-d',
-                                             self.options.elf_path],
-                                            encoding='utf-8')
-    except subprocess.CalledProcessError:
-      raise StackAnalyzerError('objdump failed to disassemble.')
-    except OSError:
-      raise StackAnalyzerError('Failed to run objdump.')
-
-    function_map = self.AnalyzeDisassembly(disasm_text)
-    result = self.ResolveAnnotation(function_map)
-    (add_set, remove_list, eliminated_addrs, failed_sigtxts) = result
-    remove_list = self.PreprocessAnnotation(function_map,
-                                            add_set,
-                                            remove_list,
-                                            eliminated_addrs)
-    cycle_functions = self.AnalyzeCallGraph(function_map, remove_list)
-
-    # Print the results of task-aware stack analysis.
-    extra_stack_frame = self.annotation.get('exception_frame_size',
-                                            DEFAULT_EXCEPTION_FRAME_SIZE)
-    for task in self.tasklist:
-      routine_func = function_map[task.routine_address]
-      print('Task: {}, Max size: {} ({} + {}), Allocated size: {}'.format(
-          task.name,
-          routine_func.stack_max_usage + extra_stack_frame,
-          routine_func.stack_max_usage,
-          extra_stack_frame,
-          task.stack_max_size))
-
-      print('Call Trace:')
-      max_stack_path = routine_func.stack_max_path
-      # Assume the routine function is resolved.
-      assert max_stack_path is not None
-      for depth, curr_func in enumerate(max_stack_path):
-        line_info = self.AddressToLine(curr_func.address)[0]
-        if line_info is None:
-          (path, linenum) = ('??', 0)
-        else:
-          (_, path, linenum) = line_info
-
-        print('    {} ({}) [{}:{}] {:x}'.format(curr_func.name,
-                                                curr_func.stack_frame,
-                                                os.path.relpath(path),
-                                                linenum,
-                                                curr_func.address))
-
-        if depth + 1 < len(max_stack_path):
-          succ_func = max_stack_path[depth + 1]
-          text_list = []
-          for callsite in curr_func.callsites:
-            if callsite.callee is succ_func:
-              indent_prefix = '        '
-              if callsite.address is None:
-                order_text = (None, '{}-> [annotation]'.format(indent_prefix))
-              else:
-                order_text = OutputInlineStack(callsite.address, indent_prefix)
-
-              text_list.append(order_text)
-
-          for _, text in sorted(text_list, key=lambda item: item[0]):
-            print(text)
-
-    print('Unresolved indirect callsites:')
-    for function in function_map.values():
-      indirect_callsites = []
-      for callsite in function.callsites:
-        if callsite.target is None:
-          indirect_callsites.append(callsite.address)
-
-      if len(indirect_callsites) > 0:
-        print('    In function {}:'.format(function.name))
-        text_list = []
-        for address in indirect_callsites:
-          text_list.append(OutputInlineStack(address, '        '))
-
-        for _, text in sorted(text_list, key=lambda item: item[0]):
-          print(text)
-
-    print('Unresolved annotation signatures:')
-    for sigtxt, error in failed_sigtxts:
-      print('    {}: {}'.format(sigtxt, error))
-
-    if len(cycle_functions) > 0:
-      print('There are cycles in the following function sets:')
-      for functions in cycle_functions:
-        print('[{}]'.format(', '.join(function.name for function in functions)))
-
-
-def ParseArgs():
-  """Parse commandline arguments.
-
-  Returns:
-    options: Namespace from argparse.parse_args().
-  """
-  parser = argparse.ArgumentParser(description="EC firmware stack analyzer.")
-  parser.add_argument('elf_path', help="the path of EC firmware ELF")
-  parser.add_argument('--export_taskinfo', required=True,
-                      help="the path of export_taskinfo.so utility")
-  parser.add_argument('--section', required=True, help='the section.',
-                      choices=[SECTION_RO, SECTION_RW])
-  parser.add_argument('--objdump', default='objdump',
-                      help='the path of objdump')
-  parser.add_argument('--addr2line', default='addr2line',
-                      help='the path of addr2line')
-  parser.add_argument('--annotation', default=None,
-                      help='the path of annotation file')
-
-  # TODO(cheyuw): Add an option for dumping stack usage of all functions.
-
-  return parser.parse_args()
-
-
-def ParseSymbolText(symbol_text):
-  """Parse the content of the symbol text.
-
-  Args:
-    symbol_text: Text of the symbols.
-
-  Returns:
-    symbols: Symbol list.
-  """
-  # Example: "10093064 g     F .text  0000015c .hidden hook_task"
-  symbol_regex = re.compile(r'^(?P<address>[0-9A-Fa-f]+)\s+[lwg]\s+'
-                            r'((?P<type>[OF])\s+)?\S+\s+'
-                            r'(?P<size>[0-9A-Fa-f]+)\s+'
-                            r'(\S+\s+)?(?P<name>\S+)$')
-
-  symbols = []
-  for line in symbol_text.splitlines():
-    line = line.strip()
-    result = symbol_regex.match(line)
-    if result is not None:
-      address = int(result.group('address'), 16)
-      symtype = result.group('type')
-      if symtype is None:
-        symtype = 'O'
-
-      size = int(result.group('size'), 16)
-      name = result.group('name')
-      symbols.append(Symbol(address, symtype, size, name))
-
-  return symbols
-
-
-def ParseRoDataText(rodata_text):
-  """Parse the content of rodata
-
-  Args:
-    symbol_text: Text of the rodata dump.
-
-  Returns:
-    symbols: Symbol list.
-  """
-  # Examples: 8018ab0 00040048 00010000 10020000 4b8e0108  ...H........K...
-  #           100a7294 00000000 00000000 01000000           ............
-
-  base_offset = None
-  offset = None
-  rodata = []
-  for line in rodata_text.splitlines():
-    line = line.strip()
-    space = line.find(' ')
-    if space < 0:
-        continue
-    try:
-      address = int(line[0:space], 16)
-    except ValueError:
-      continue
-
-    if not base_offset:
-      base_offset = address
-      offset = address
-    elif address != offset:
-      raise StackAnalyzerError('objdump of rodata not contiguous.')
+        if not base_offset:
+            base_offset = address
+            offset = address
+        elif address != offset:
+            raise StackAnalyzerError("objdump of rodata not contiguous.")
 
-    for i in range(0, 4):
-      num = line[(space + 1 + i*9):(space + 9 + i*9)]
-      if len(num.strip()) > 0:
-        val = int(num, 16)
-      else:
-        val = 0
-      # TODO(drinkcat): Not all platforms are necessarily big-endian
-      rodata.append((val & 0x000000ff) << 24 |
-                    (val & 0x0000ff00) << 8 |
-                    (val & 0x00ff0000) >> 8 |
-                    (val & 0xff000000) >> 24)
+        for i in range(0, 4):
+            num = line[(space + 1 + i * 9) : (space + 9 + i * 9)]
+            if len(num.strip()) > 0:
+                val = int(num, 16)
+            else:
+                val = 0
+            # TODO(drinkcat): Not all platforms are necessarily big-endian
+            rodata.append(
+                (val & 0x000000FF) << 24
+                | (val & 0x0000FF00) << 8
+                | (val & 0x00FF0000) >> 8
+                | (val & 0xFF000000) >> 24
+            )
 
-    offset = offset + 4*4
+        offset = offset + 4 * 4
 
-  return (base_offset, rodata)
+    return (base_offset, rodata)
 
 
 def LoadTasklist(section, export_taskinfo, symbols):
-  """Load the task information.
+    """Load the task information.
 
-  Args:
-    section: Section (RO | RW).
-    export_taskinfo: Handle of export_taskinfo.so.
-    symbols: Symbol list.
+    Args:
+      section: Section (RO | RW).
+      export_taskinfo: Handle of export_taskinfo.so.
+      symbols: Symbol list.
 
-  Returns:
-    tasklist: Task list.
-  """
+    Returns:
+      tasklist: Task list.
+    """
 
-  TaskInfoPointer = ctypes.POINTER(TaskInfo)
-  taskinfos = TaskInfoPointer()
-  if section == SECTION_RO:
-    get_taskinfos_func = export_taskinfo.get_ro_taskinfos
-  else:
-    get_taskinfos_func = export_taskinfo.get_rw_taskinfos
+    TaskInfoPointer = ctypes.POINTER(TaskInfo)
+    taskinfos = TaskInfoPointer()
+    if section == SECTION_RO:
+        get_taskinfos_func = export_taskinfo.get_ro_taskinfos
+    else:
+        get_taskinfos_func = export_taskinfo.get_rw_taskinfos
 
-  taskinfo_num = get_taskinfos_func(ctypes.pointer(taskinfos))
+    taskinfo_num = get_taskinfos_func(ctypes.pointer(taskinfos))
 
-  tasklist = []
-  for index in range(taskinfo_num):
-    taskinfo = taskinfos[index]
-    tasklist.append(Task(taskinfo.name.decode('utf-8'),
-                         taskinfo.routine.decode('utf-8'),
-                         taskinfo.stack_size))
+    tasklist = []
+    for index in range(taskinfo_num):
+        taskinfo = taskinfos[index]
+        tasklist.append(
+            Task(
+                taskinfo.name.decode("utf-8"),
+                taskinfo.routine.decode("utf-8"),
+                taskinfo.stack_size,
+            )
+        )
 
-  # Resolve routine address for each task. It's more efficient to resolve all
-  # routine addresses of tasks together.
-  routine_map = dict((task.routine_name, None) for task in tasklist)
+    # Resolve routine address for each task. It's more efficient to resolve all
+    # routine addresses of tasks together.
+    routine_map = dict((task.routine_name, None) for task in tasklist)
 
-  for symbol in symbols:
-    # Resolve task routine address.
-    if symbol.name in routine_map:
-      # Assume the symbol of routine is unique.
-      assert routine_map[symbol.name] is None
-      routine_map[symbol.name] = symbol.address
+    for symbol in symbols:
+        # Resolve task routine address.
+        if symbol.name in routine_map:
+            # Assume the symbol of routine is unique.
+            assert routine_map[symbol.name] is None
+            routine_map[symbol.name] = symbol.address
 
-  for task in tasklist:
-    address = routine_map[task.routine_name]
-    # Assume we have resolved all routine addresses.
-    assert address is not None
-    task.routine_address = address
+    for task in tasklist:
+        address = routine_map[task.routine_name]
+        # Assume we have resolved all routine addresses.
+        assert address is not None
+        task.routine_address = address
 
-  return tasklist
+    return tasklist
 
 
 def main():
-  """Main function."""
-  try:
-    options = ParseArgs()
-
-    # Load annotation config.
-    if options.annotation is None:
-      annotation = {}
-    elif not os.path.exists(options.annotation):
-      print('Warning: Annotation file {} does not exist.'
-            .format(options.annotation))
-      annotation = {}
-    else:
-      try:
-        with open(options.annotation, 'r') as annotation_file:
-          annotation = yaml.safe_load(annotation_file)
-
-      except yaml.YAMLError:
-        raise StackAnalyzerError('Failed to parse annotation file {}.'
-                                 .format(options.annotation))
-      except IOError:
-        raise StackAnalyzerError('Failed to open annotation file {}.'
-                                 .format(options.annotation))
-
-      # TODO(cheyuw): Do complete annotation format verification.
-      if not isinstance(annotation, dict):
-        raise StackAnalyzerError('Invalid annotation file {}.'
-                                 .format(options.annotation))
-
-    # Generate and parse the symbols.
+    """Main function."""
     try:
-      symbol_text = subprocess.check_output([options.objdump,
-                                             '-t',
-                                             options.elf_path],
-                                            encoding='utf-8')
-      rodata_text = subprocess.check_output([options.objdump,
-                                             '-s',
-                                             '-j', '.rodata',
-                                             options.elf_path],
-                                            encoding='utf-8')
-    except subprocess.CalledProcessError:
-      raise StackAnalyzerError('objdump failed to dump symbol table or rodata.')
-    except OSError:
-      raise StackAnalyzerError('Failed to run objdump.')
-
-    symbols = ParseSymbolText(symbol_text)
-    rodata = ParseRoDataText(rodata_text)
-
-    # Load the tasklist.
-    try:
-      export_taskinfo = ctypes.CDLL(options.export_taskinfo)
-    except OSError:
-      raise StackAnalyzerError('Failed to load export_taskinfo.')
-
-    tasklist = LoadTasklist(options.section, export_taskinfo, symbols)
-
-    analyzer = StackAnalyzer(options, symbols, rodata, tasklist, annotation)
-    analyzer.Analyze()
-  except StackAnalyzerError as e:
-    print('Error: {}'.format(e))
-
-
-if __name__ == '__main__':
-  main()
+        options = ParseArgs()
+
+        # Load annotation config.
+        if options.annotation is None:
+            annotation = {}
+        elif not os.path.exists(options.annotation):
+            print(
+                "Warning: Annotation file {} does not exist.".format(
+                    options.annotation
+                )
+            )
+            annotation = {}
+        else:
+            try:
+                with open(options.annotation, "r") as annotation_file:
+                    annotation = yaml.safe_load(annotation_file)
+
+            except yaml.YAMLError:
+                raise StackAnalyzerError(
+                    "Failed to parse annotation file {}.".format(
+                        options.annotation
+                    )
+                )
+            except IOError:
+                raise StackAnalyzerError(
+                    "Failed to open annotation file {}.".format(
+                        options.annotation
+                    )
+                )
+
+            # TODO(cheyuw): Do complete annotation format verification.
+            if not isinstance(annotation, dict):
+                raise StackAnalyzerError(
+                    "Invalid annotation file {}.".format(options.annotation)
+                )
+
+        # Generate and parse the symbols.
+        try:
+            symbol_text = subprocess.check_output(
+                [options.objdump, "-t", options.elf_path], encoding="utf-8"
+            )
+            rodata_text = subprocess.check_output(
+                [options.objdump, "-s", "-j", ".rodata", options.elf_path],
+                encoding="utf-8",
+            )
+        except subprocess.CalledProcessError:
+            raise StackAnalyzerError(
+                "objdump failed to dump symbol table or rodata."
+            )
+        except OSError:
+            raise StackAnalyzerError("Failed to run objdump.")
+
+        symbols = ParseSymbolText(symbol_text)
+        rodata = ParseRoDataText(rodata_text)
+
+        # Load the tasklist.
+        try:
+            export_taskinfo = ctypes.CDLL(options.export_taskinfo)
+        except OSError:
+            raise StackAnalyzerError("Failed to load export_taskinfo.")
+
+        tasklist = LoadTasklist(options.section, export_taskinfo, symbols)
+
+        analyzer = StackAnalyzer(options, symbols, rodata, tasklist, annotation)
+        analyzer.Analyze()
+    except StackAnalyzerError as e:
+        print("Error: {}".format(e))
+
+
+if __name__ == "__main__":
+    main()
diff --git a/extra/stack_analyzer/stack_analyzer_unittest.py b/extra/stack_analyzer/stack_analyzer_unittest.py
index 09753625c9..23a8fb93ea 100755
--- a/extra/stack_analyzer/stack_analyzer_unittest.py
+++ b/extra/stack_analyzer/stack_analyzer_unittest.py
@@ -1,5 +1,5 @@
 #!/usr/bin/env python3
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -7,820 +7,987 @@
 
 from __future__ import print_function
 
-import mock
 import os
 import subprocess
 import unittest
 
+import mock  # pylint:disable=import-error
 import stack_analyzer as sa
 
 
 class ObjectTest(unittest.TestCase):
-  """Tests for classes of basic objects."""
-
-  def testTask(self):
-    task_a = sa.Task('a', 'a_task', 1234)
-    task_b = sa.Task('b', 'b_task', 5678, 0x1000)
-    self.assertEqual(task_a, task_a)
-    self.assertNotEqual(task_a, task_b)
-    self.assertNotEqual(task_a, None)
-
-  def testSymbol(self):
-    symbol_a = sa.Symbol(0x1234, 'F', 32, 'a')
-    symbol_b = sa.Symbol(0x234, 'O', 42, 'b')
-    self.assertEqual(symbol_a, symbol_a)
-    self.assertNotEqual(symbol_a, symbol_b)
-    self.assertNotEqual(symbol_a, None)
-
-  def testCallsite(self):
-    callsite_a = sa.Callsite(0x1002, 0x3000, False)
-    callsite_b = sa.Callsite(0x1002, 0x3000, True)
-    self.assertEqual(callsite_a, callsite_a)
-    self.assertNotEqual(callsite_a, callsite_b)
-    self.assertNotEqual(callsite_a, None)
-
-  def testFunction(self):
-    func_a = sa.Function(0x100, 'a', 0, [])
-    func_b = sa.Function(0x200, 'b', 0, [])
-    self.assertEqual(func_a, func_a)
-    self.assertNotEqual(func_a, func_b)
-    self.assertNotEqual(func_a, None)
+    """Tests for classes of basic objects."""
+
+    def testTask(self):
+        task_a = sa.Task("a", "a_task", 1234)
+        task_b = sa.Task("b", "b_task", 5678, 0x1000)
+        self.assertEqual(task_a, task_a)
+        self.assertNotEqual(task_a, task_b)
+        self.assertNotEqual(task_a, None)
+
+    def testSymbol(self):
+        symbol_a = sa.Symbol(0x1234, "F", 32, "a")
+        symbol_b = sa.Symbol(0x234, "O", 42, "b")
+        self.assertEqual(symbol_a, symbol_a)
+        self.assertNotEqual(symbol_a, symbol_b)
+        self.assertNotEqual(symbol_a, None)
+
+    def testCallsite(self):
+        callsite_a = sa.Callsite(0x1002, 0x3000, False)
+        callsite_b = sa.Callsite(0x1002, 0x3000, True)
+        self.assertEqual(callsite_a, callsite_a)
+        self.assertNotEqual(callsite_a, callsite_b)
+        self.assertNotEqual(callsite_a, None)
+
+    def testFunction(self):
+        func_a = sa.Function(0x100, "a", 0, [])
+        func_b = sa.Function(0x200, "b", 0, [])
+        self.assertEqual(func_a, func_a)
+        self.assertNotEqual(func_a, func_b)
+        self.assertNotEqual(func_a, None)
 
 
 class ArmAnalyzerTest(unittest.TestCase):
-  """Tests for class ArmAnalyzer."""
-
-  def AppendConditionCode(self, opcodes):
-    rets = []
-    for opcode in opcodes:
-      rets.extend(opcode + cc for cc in sa.ArmAnalyzer.CONDITION_CODES)
-
-    return rets
-
-  def testInstructionMatching(self):
-    jump_list = self.AppendConditionCode(['b', 'bx'])
-    jump_list += (list(opcode + '.n' for opcode in jump_list) +
-                  list(opcode + '.w' for opcode in jump_list))
-    for opcode in jump_list:
-      self.assertIsNotNone(sa.ArmAnalyzer.JUMP_OPCODE_RE.match(opcode))
-
-    self.assertIsNone(sa.ArmAnalyzer.JUMP_OPCODE_RE.match('bl'))
-    self.assertIsNone(sa.ArmAnalyzer.JUMP_OPCODE_RE.match('blx'))
-
-    cbz_list = ['cbz', 'cbnz', 'cbz.n', 'cbnz.n', 'cbz.w', 'cbnz.w']
-    for opcode in cbz_list:
-      self.assertIsNotNone(sa.ArmAnalyzer.CBZ_CBNZ_OPCODE_RE.match(opcode))
-
-    self.assertIsNone(sa.ArmAnalyzer.CBZ_CBNZ_OPCODE_RE.match('cbn'))
-
-    call_list = self.AppendConditionCode(['bl', 'blx'])
-    call_list += list(opcode + '.n' for opcode in call_list)
-    for opcode in call_list:
-      self.assertIsNotNone(sa.ArmAnalyzer.CALL_OPCODE_RE.match(opcode))
-
-    self.assertIsNone(sa.ArmAnalyzer.CALL_OPCODE_RE.match('ble'))
-
-    result = sa.ArmAnalyzer.CALL_OPERAND_RE.match('53f90 <get_time+0x18>')
-    self.assertIsNotNone(result)
-    self.assertEqual(result.group(1), '53f90')
-    self.assertEqual(result.group(2), 'get_time+0x18')
-
-    result = sa.ArmAnalyzer.CBZ_CBNZ_OPERAND_RE.match('r6, 53f90 <get+0x0>')
-    self.assertIsNotNone(result)
-    self.assertEqual(result.group(1), '53f90')
-    self.assertEqual(result.group(2), 'get+0x0')
-
-    self.assertIsNotNone(sa.ArmAnalyzer.PUSH_OPCODE_RE.match('push'))
-    self.assertIsNone(sa.ArmAnalyzer.PUSH_OPCODE_RE.match('pushal'))
-    self.assertIsNotNone(sa.ArmAnalyzer.STM_OPCODE_RE.match('stmdb'))
-    self.assertIsNone(sa.ArmAnalyzer.STM_OPCODE_RE.match('lstm'))
-    self.assertIsNotNone(sa.ArmAnalyzer.SUB_OPCODE_RE.match('sub'))
-    self.assertIsNotNone(sa.ArmAnalyzer.SUB_OPCODE_RE.match('subs'))
-    self.assertIsNotNone(sa.ArmAnalyzer.SUB_OPCODE_RE.match('subw'))
-    self.assertIsNotNone(sa.ArmAnalyzer.SUB_OPCODE_RE.match('sub.w'))
-    self.assertIsNotNone(sa.ArmAnalyzer.SUB_OPCODE_RE.match('subs.w'))
-
-    result = sa.ArmAnalyzer.SUB_OPERAND_RE.match('sp, sp, #1668   ; 0x684')
-    self.assertIsNotNone(result)
-    self.assertEqual(result.group(1), '1668')
-    result = sa.ArmAnalyzer.SUB_OPERAND_RE.match('sp, #1668')
-    self.assertIsNotNone(result)
-    self.assertEqual(result.group(1), '1668')
-    self.assertIsNone(sa.ArmAnalyzer.SUB_OPERAND_RE.match('sl, #1668'))
-
-  def testAnalyzeFunction(self):
-    analyzer = sa.ArmAnalyzer()
-    symbol = sa.Symbol(0x10, 'F', 0x100, 'foo')
-    instructions = [
-        (0x10, 'push', '{r4, r5, r6, r7, lr}'),
-        (0x12, 'subw', 'sp, sp, #16	; 0x10'),
-        (0x16, 'movs', 'lr, r1'),
-        (0x18, 'beq.n', '26 <foo+0x26>'),
-        (0x1a, 'bl', '30 <foo+0x30>'),
-        (0x1e, 'bl', 'deadbeef <bar>'),
-        (0x22, 'blx', '0 <woo>'),
-        (0x26, 'push', '{r1}'),
-        (0x28, 'stmdb', 'sp!, {r4, r5, r6, r7, r8, r9, lr}'),
-        (0x2c, 'stmdb', 'sp!, {r4}'),
-        (0x30, 'stmdb', 'sp, {r4}'),
-        (0x34, 'bx.n', '10 <foo>'),
-        (0x36, 'bx.n', 'r3'),
-        (0x38, 'ldr', 'pc, [r10]'),
-    ]
-    (size, callsites) = analyzer.AnalyzeFunction(symbol, instructions)
-    self.assertEqual(size, 72)
-    expect_callsites = [sa.Callsite(0x1e, 0xdeadbeef, False),
-                        sa.Callsite(0x22, 0x0, False),
-                        sa.Callsite(0x34, 0x10, True),
-                        sa.Callsite(0x36, None, True),
-                        sa.Callsite(0x38, None, True)]
-    self.assertEqual(callsites, expect_callsites)
+    """Tests for class ArmAnalyzer."""
+
+    def AppendConditionCode(self, opcodes):
+        rets = []
+        for opcode in opcodes:
+            rets.extend(opcode + cc for cc in sa.ArmAnalyzer.CONDITION_CODES)
+
+        return rets
+
+    def testInstructionMatching(self):
+        jump_list = self.AppendConditionCode(["b", "bx"])
+        jump_list += list(opcode + ".n" for opcode in jump_list) + list(
+            opcode + ".w" for opcode in jump_list
+        )
+        for opcode in jump_list:
+            self.assertIsNotNone(sa.ArmAnalyzer.JUMP_OPCODE_RE.match(opcode))
+
+        self.assertIsNone(sa.ArmAnalyzer.JUMP_OPCODE_RE.match("bl"))
+        self.assertIsNone(sa.ArmAnalyzer.JUMP_OPCODE_RE.match("blx"))
+
+        cbz_list = ["cbz", "cbnz", "cbz.n", "cbnz.n", "cbz.w", "cbnz.w"]
+        for opcode in cbz_list:
+            self.assertIsNotNone(
+                sa.ArmAnalyzer.CBZ_CBNZ_OPCODE_RE.match(opcode)
+            )
+
+        self.assertIsNone(sa.ArmAnalyzer.CBZ_CBNZ_OPCODE_RE.match("cbn"))
+
+        call_list = self.AppendConditionCode(["bl", "blx"])
+        call_list += list(opcode + ".n" for opcode in call_list)
+        for opcode in call_list:
+            self.assertIsNotNone(sa.ArmAnalyzer.CALL_OPCODE_RE.match(opcode))
+
+        self.assertIsNone(sa.ArmAnalyzer.CALL_OPCODE_RE.match("ble"))
+
+        result = sa.ArmAnalyzer.CALL_OPERAND_RE.match("53f90 <get_time+0x18>")
+        self.assertIsNotNone(result)
+        self.assertEqual(result.group(1), "53f90")
+        self.assertEqual(result.group(2), "get_time+0x18")
+
+        result = sa.ArmAnalyzer.CBZ_CBNZ_OPERAND_RE.match("r6, 53f90 <get+0x0>")
+        self.assertIsNotNone(result)
+        self.assertEqual(result.group(1), "53f90")
+        self.assertEqual(result.group(2), "get+0x0")
+
+        self.assertIsNotNone(sa.ArmAnalyzer.PUSH_OPCODE_RE.match("push"))
+        self.assertIsNone(sa.ArmAnalyzer.PUSH_OPCODE_RE.match("pushal"))
+        self.assertIsNotNone(sa.ArmAnalyzer.STM_OPCODE_RE.match("stmdb"))
+        self.assertIsNone(sa.ArmAnalyzer.STM_OPCODE_RE.match("lstm"))
+        self.assertIsNotNone(sa.ArmAnalyzer.SUB_OPCODE_RE.match("sub"))
+        self.assertIsNotNone(sa.ArmAnalyzer.SUB_OPCODE_RE.match("subs"))
+        self.assertIsNotNone(sa.ArmAnalyzer.SUB_OPCODE_RE.match("subw"))
+        self.assertIsNotNone(sa.ArmAnalyzer.SUB_OPCODE_RE.match("sub.w"))
+        self.assertIsNotNone(sa.ArmAnalyzer.SUB_OPCODE_RE.match("subs.w"))
+
+        result = sa.ArmAnalyzer.SUB_OPERAND_RE.match("sp, sp, #1668   ; 0x684")
+        self.assertIsNotNone(result)
+        self.assertEqual(result.group(1), "1668")
+        result = sa.ArmAnalyzer.SUB_OPERAND_RE.match("sp, #1668")
+        self.assertIsNotNone(result)
+        self.assertEqual(result.group(1), "1668")
+        self.assertIsNone(sa.ArmAnalyzer.SUB_OPERAND_RE.match("sl, #1668"))
+
+    def testAnalyzeFunction(self):
+        analyzer = sa.ArmAnalyzer()
+        symbol = sa.Symbol(0x10, "F", 0x100, "foo")
+        instructions = [
+            (0x10, "push", "{r4, r5, r6, r7, lr}"),
+            (0x12, "subw", "sp, sp, #16	; 0x10"),
+            (0x16, "movs", "lr, r1"),
+            (0x18, "beq.n", "26 <foo+0x26>"),
+            (0x1A, "bl", "30 <foo+0x30>"),
+            (0x1E, "bl", "deadbeef <bar>"),
+            (0x22, "blx", "0 <woo>"),
+            (0x26, "push", "{r1}"),
+            (0x28, "stmdb", "sp!, {r4, r5, r6, r7, r8, r9, lr}"),
+            (0x2C, "stmdb", "sp!, {r4}"),
+            (0x30, "stmdb", "sp, {r4}"),
+            (0x34, "bx.n", "10 <foo>"),
+            (0x36, "bx.n", "r3"),
+            (0x38, "ldr", "pc, [r10]"),
+        ]
+        (size, callsites) = analyzer.AnalyzeFunction(symbol, instructions)
+        self.assertEqual(size, 72)
+        expect_callsites = [
+            sa.Callsite(0x1E, 0xDEADBEEF, False),
+            sa.Callsite(0x22, 0x0, False),
+            sa.Callsite(0x34, 0x10, True),
+            sa.Callsite(0x36, None, True),
+            sa.Callsite(0x38, None, True),
+        ]
+        self.assertEqual(callsites, expect_callsites)
 
 
 class StackAnalyzerTest(unittest.TestCase):
-  """Tests for class StackAnalyzer."""
-
-  def setUp(self):
-    symbols = [sa.Symbol(0x1000, 'F', 0x15C, 'hook_task'),
-               sa.Symbol(0x2000, 'F', 0x51C, 'console_task'),
-               sa.Symbol(0x3200, 'O', 0x124, '__just_data'),
-               sa.Symbol(0x4000, 'F', 0x11C, 'touchpad_calc'),
-               sa.Symbol(0x5000, 'F', 0x12C, 'touchpad_calc.constprop.42'),
-               sa.Symbol(0x12000, 'F', 0x13C, 'trackpad_range'),
-               sa.Symbol(0x13000, 'F', 0x200, 'inlined_mul'),
-               sa.Symbol(0x13100, 'F', 0x200, 'inlined_mul'),
-               sa.Symbol(0x13100, 'F', 0x200, 'inlined_mul_alias'),
-               sa.Symbol(0x20000, 'O', 0x0, '__array'),
-               sa.Symbol(0x20010, 'O', 0x0, '__array_end'),
-    ]
-    tasklist = [sa.Task('HOOKS', 'hook_task', 2048, 0x1000),
-                sa.Task('CONSOLE', 'console_task', 460, 0x2000)]
-    # Array at 0x20000 that contains pointers to hook_task and console_task,
-    # with stride=8, offset=4
-    rodata = (0x20000, [ 0xDEAD1000, 0x00001000, 0xDEAD2000, 0x00002000 ])
-    options = mock.MagicMock(elf_path='./ec.RW.elf',
-                             export_taskinfo='fake',
-                             section='RW',
-                             objdump='objdump',
-                             addr2line='addr2line',
-                             annotation=None)
-    self.analyzer = sa.StackAnalyzer(options, symbols, rodata, tasklist, {})
-
-  def testParseSymbolText(self):
-    symbol_text = (
-        '0 g     F .text  e8 Foo\n'
-        '0000dead  w    F .text  000000e8 .hidden Bar\n'
-        'deadbeef l     O .bss   00000004 .hidden Woooo\n'
-        'deadbee g     O .rodata        00000008 __Hooo_ooo\n'
-        'deadbee g       .rodata        00000000 __foo_doo_coo_end\n'
-    )
-    symbols = sa.ParseSymbolText(symbol_text)
-    expect_symbols = [sa.Symbol(0x0, 'F', 0xe8, 'Foo'),
-                      sa.Symbol(0xdead, 'F', 0xe8, 'Bar'),
-                      sa.Symbol(0xdeadbeef, 'O', 0x4, 'Woooo'),
-                      sa.Symbol(0xdeadbee, 'O', 0x8, '__Hooo_ooo'),
-                      sa.Symbol(0xdeadbee, 'O', 0x0, '__foo_doo_coo_end')]
-    self.assertEqual(symbols, expect_symbols)
-
-  def testParseRoData(self):
-    rodata_text = (
-        '\n'
-        'Contents of section .rodata:\n'
-        ' 20000 dead1000 00100000 dead2000 00200000  He..f.He..s.\n'
-    )
-    rodata = sa.ParseRoDataText(rodata_text)
-    expect_rodata = (0x20000,
-                     [ 0x0010adde, 0x00001000, 0x0020adde, 0x00002000 ])
-    self.assertEqual(rodata, expect_rodata)
-
-  def testLoadTasklist(self):
-    def tasklist_to_taskinfos(pointer, tasklist):
-      taskinfos = []
-      for task in tasklist:
-        taskinfos.append(sa.TaskInfo(name=task.name.encode('utf-8'),
-                                     routine=task.routine_name.encode('utf-8'),
-                                     stack_size=task.stack_max_size))
-
-      TaskInfoArray = sa.TaskInfo * len(taskinfos)
-      pointer.contents.contents = TaskInfoArray(*taskinfos)
-      return len(taskinfos)
-
-    def ro_taskinfos(pointer):
-      return tasklist_to_taskinfos(pointer, expect_ro_tasklist)
-
-    def rw_taskinfos(pointer):
-      return tasklist_to_taskinfos(pointer, expect_rw_tasklist)
-
-    expect_ro_tasklist = [
-        sa.Task('HOOKS', 'hook_task', 2048, 0x1000),
-    ]
-
-    expect_rw_tasklist = [
-        sa.Task('HOOKS', 'hook_task', 2048, 0x1000),
-        sa.Task('WOOKS', 'hook_task', 4096, 0x1000),
-        sa.Task('CONSOLE', 'console_task', 460, 0x2000),
-    ]
-
-    export_taskinfo = mock.MagicMock(
-        get_ro_taskinfos=mock.MagicMock(side_effect=ro_taskinfos),
-        get_rw_taskinfos=mock.MagicMock(side_effect=rw_taskinfos))
-
-    tasklist = sa.LoadTasklist('RO', export_taskinfo, self.analyzer.symbols)
-    self.assertEqual(tasklist, expect_ro_tasklist)
-    tasklist = sa.LoadTasklist('RW', export_taskinfo, self.analyzer.symbols)
-    self.assertEqual(tasklist, expect_rw_tasklist)
-
-  def testResolveAnnotation(self):
-    self.analyzer.annotation = {}
-    (add_rules, remove_rules, invalid_sigtxts) = self.analyzer.LoadAnnotation()
-    self.assertEqual(add_rules, {})
-    self.assertEqual(remove_rules, [])
-    self.assertEqual(invalid_sigtxts, set())
-
-    self.analyzer.annotation = {'add': None, 'remove': None}
-    (add_rules, remove_rules, invalid_sigtxts) = self.analyzer.LoadAnnotation()
-    self.assertEqual(add_rules, {})
-    self.assertEqual(remove_rules, [])
-    self.assertEqual(invalid_sigtxts, set())
-
-    self.analyzer.annotation = {
-        'add': None,
-        'remove': [
-            [['a', 'b'], ['0', '[', '2'], 'x'],
-            [['a', 'b[x:3]'], ['0', '1', '2'], 'x'],
-        ],
-    }
-    (add_rules, remove_rules, invalid_sigtxts) = self.analyzer.LoadAnnotation()
-    self.assertEqual(add_rules, {})
-    self.assertEqual(list.sort(remove_rules), list.sort([
-        [('a', None, None), ('1', None, None), ('x', None, None)],
-        [('a', None, None), ('0', None, None), ('x', None, None)],
-        [('a', None, None), ('2', None, None), ('x', None, None)],
-        [('b', os.path.abspath('x'), 3), ('1', None, None), ('x', None, None)],
-        [('b', os.path.abspath('x'), 3), ('0', None, None), ('x', None, None)],
-        [('b', os.path.abspath('x'), 3), ('2', None, None), ('x', None, None)],
-    ]))
-    self.assertEqual(invalid_sigtxts, {'['})
-
-    self.analyzer.annotation = {
-        'add': {
-          'touchpad_calc': [ dict(name='__array', stride=8, offset=4) ],
+    """Tests for class StackAnalyzer."""
+
+    def setUp(self):
+        symbols = [
+            sa.Symbol(0x1000, "F", 0x15C, "hook_task"),
+            sa.Symbol(0x2000, "F", 0x51C, "console_task"),
+            sa.Symbol(0x3200, "O", 0x124, "__just_data"),
+            sa.Symbol(0x4000, "F", 0x11C, "touchpad_calc"),
+            sa.Symbol(0x5000, "F", 0x12C, "touchpad_calc.constprop.42"),
+            sa.Symbol(0x12000, "F", 0x13C, "trackpad_range"),
+            sa.Symbol(0x13000, "F", 0x200, "inlined_mul"),
+            sa.Symbol(0x13100, "F", 0x200, "inlined_mul"),
+            sa.Symbol(0x13100, "F", 0x200, "inlined_mul_alias"),
+            sa.Symbol(0x20000, "O", 0x0, "__array"),
+            sa.Symbol(0x20010, "O", 0x0, "__array_end"),
+        ]
+        tasklist = [
+            sa.Task("HOOKS", "hook_task", 2048, 0x1000),
+            sa.Task("CONSOLE", "console_task", 460, 0x2000),
+        ]
+        # Array at 0x20000 that contains pointers to hook_task and console_task,
+        # with stride=8, offset=4
+        rodata = (0x20000, [0xDEAD1000, 0x00001000, 0xDEAD2000, 0x00002000])
+        options = mock.MagicMock(
+            elf_path="./ec.RW.elf",
+            export_taskinfo="fake",
+            section="RW",
+            objdump="objdump",
+            addr2line="addr2line",
+            annotation=None,
+        )
+        self.analyzer = sa.StackAnalyzer(options, symbols, rodata, tasklist, {})
+
+    def testParseSymbolText(self):
+        symbol_text = (
+            "0 g     F .text  e8 Foo\n"
+            "0000dead  w    F .text  000000e8 .hidden Bar\n"
+            "deadbeef l     O .bss   00000004 .hidden Woooo\n"
+            "deadbee g     O .rodata        00000008 __Hooo_ooo\n"
+            "deadbee g       .rodata        00000000 __foo_doo_coo_end\n"
+        )
+        symbols = sa.ParseSymbolText(symbol_text)
+        expect_symbols = [
+            sa.Symbol(0x0, "F", 0xE8, "Foo"),
+            sa.Symbol(0xDEAD, "F", 0xE8, "Bar"),
+            sa.Symbol(0xDEADBEEF, "O", 0x4, "Woooo"),
+            sa.Symbol(0xDEADBEE, "O", 0x8, "__Hooo_ooo"),
+            sa.Symbol(0xDEADBEE, "O", 0x0, "__foo_doo_coo_end"),
+        ]
+        self.assertEqual(symbols, expect_symbols)
+
+    def testParseRoData(self):
+        rodata_text = (
+            "\n"
+            "Contents of section .rodata:\n"
+            " 20000 dead1000 00100000 dead2000 00200000  He..f.He..s.\n"
+        )
+        rodata = sa.ParseRoDataText(rodata_text)
+        expect_rodata = (
+            0x20000,
+            [0x0010ADDE, 0x00001000, 0x0020ADDE, 0x00002000],
+        )
+        self.assertEqual(rodata, expect_rodata)
+
+    def testLoadTasklist(self):
+        def tasklist_to_taskinfos(pointer, tasklist):
+            taskinfos = []
+            for task in tasklist:
+                taskinfos.append(
+                    sa.TaskInfo(
+                        name=task.name.encode("utf-8"),
+                        routine=task.routine_name.encode("utf-8"),
+                        stack_size=task.stack_max_size,
+                    )
+                )
+
+            TaskInfoArray = sa.TaskInfo * len(taskinfos)
+            pointer.contents.contents = TaskInfoArray(*taskinfos)
+            return len(taskinfos)
+
+        def ro_taskinfos(pointer):
+            return tasklist_to_taskinfos(pointer, expect_ro_tasklist)
+
+        def rw_taskinfos(pointer):
+            return tasklist_to_taskinfos(pointer, expect_rw_tasklist)
+
+        expect_ro_tasklist = [
+            sa.Task("HOOKS", "hook_task", 2048, 0x1000),
+        ]
+
+        expect_rw_tasklist = [
+            sa.Task("HOOKS", "hook_task", 2048, 0x1000),
+            sa.Task("WOOKS", "hook_task", 4096, 0x1000),
+            sa.Task("CONSOLE", "console_task", 460, 0x2000),
+        ]
+
+        export_taskinfo = mock.MagicMock(
+            get_ro_taskinfos=mock.MagicMock(side_effect=ro_taskinfos),
+            get_rw_taskinfos=mock.MagicMock(side_effect=rw_taskinfos),
+        )
+
+        tasklist = sa.LoadTasklist("RO", export_taskinfo, self.analyzer.symbols)
+        self.assertEqual(tasklist, expect_ro_tasklist)
+        tasklist = sa.LoadTasklist("RW", export_taskinfo, self.analyzer.symbols)
+        self.assertEqual(tasklist, expect_rw_tasklist)
+
+    def testResolveAnnotation(self):
+        self.analyzer.annotation = {}
+        (
+            add_rules,
+            remove_rules,
+            invalid_sigtxts,
+        ) = self.analyzer.LoadAnnotation()
+        self.assertEqual(add_rules, {})
+        self.assertEqual(remove_rules, [])
+        self.assertEqual(invalid_sigtxts, set())
+
+        self.analyzer.annotation = {"add": None, "remove": None}
+        (
+            add_rules,
+            remove_rules,
+            invalid_sigtxts,
+        ) = self.analyzer.LoadAnnotation()
+        self.assertEqual(add_rules, {})
+        self.assertEqual(remove_rules, [])
+        self.assertEqual(invalid_sigtxts, set())
+
+        self.analyzer.annotation = {
+            "add": None,
+            "remove": [
+                [["a", "b"], ["0", "[", "2"], "x"],
+                [["a", "b[x:3]"], ["0", "1", "2"], "x"],
+            ],
         }
-    }
-    (add_rules, remove_rules, invalid_sigtxts) = self.analyzer.LoadAnnotation()
-    self.assertEqual(add_rules, {
-      ('touchpad_calc', None, None):
-        set([('console_task', None, None), ('hook_task', None, None)])})
-
-    funcs = {
-        0x1000: sa.Function(0x1000, 'hook_task', 0, []),
-        0x2000: sa.Function(0x2000, 'console_task', 0, []),
-        0x4000: sa.Function(0x4000, 'touchpad_calc', 0, []),
-        0x5000: sa.Function(0x5000, 'touchpad_calc.constprop.42', 0, []),
-        0x13000: sa.Function(0x13000, 'inlined_mul', 0, []),
-        0x13100: sa.Function(0x13100, 'inlined_mul', 0, []),
-    }
-    funcs[0x1000].callsites = [
-        sa.Callsite(0x1002, None, False, None)]
-    # Set address_to_line_cache to fake the results of addr2line.
-    self.analyzer.address_to_line_cache = {
-        (0x1000, False): [('hook_task', os.path.abspath('a.c'), 10)],
-        (0x1002, False): [('toot_calc', os.path.abspath('t.c'), 1234)],
-        (0x2000, False): [('console_task', os.path.abspath('b.c'), 20)],
-        (0x4000, False): [('toudhpad_calc', os.path.abspath('a.c'), 20)],
-        (0x5000, False): [
-            ('touchpad_calc.constprop.42', os.path.abspath('b.c'), 40)],
-        (0x12000, False): [('trackpad_range', os.path.abspath('t.c'), 10)],
-        (0x13000, False): [('inlined_mul', os.path.abspath('x.c'), 12)],
-        (0x13100, False): [('inlined_mul', os.path.abspath('x.c'), 12)],
-    }
-    self.analyzer.annotation = {
-        'add': {
-            'hook_task.lto.573': ['touchpad_calc.lto.2501[a.c]'],
-            'console_task': ['touchpad_calc[b.c]', 'inlined_mul_alias'],
-            'hook_task[q.c]': ['hook_task'],
-            'inlined_mul[x.c]': ['inlined_mul'],
-            'toot_calc[t.c:1234]': ['hook_task'],
-        },
-        'remove': [
-            ['touchpad?calc['],
-            'touchpad_calc',
-            ['touchpad_calc[a.c]'],
-            ['task_unk[a.c]'],
-            ['touchpad_calc[x/a.c]'],
-            ['trackpad_range'],
-            ['inlined_mul'],
-            ['inlined_mul', 'console_task', 'touchpad_calc[a.c]'],
-            ['inlined_mul', 'inlined_mul_alias', 'console_task'],
-            ['inlined_mul', 'inlined_mul_alias', 'console_task'],
-        ],
-    }
-    (add_rules, remove_rules, invalid_sigtxts) = self.analyzer.LoadAnnotation()
-    self.assertEqual(invalid_sigtxts, {'touchpad?calc['})
-
-    signature_set = set()
-    for src_sig, dst_sigs in add_rules.items():
-      signature_set.add(src_sig)
-      signature_set.update(dst_sigs)
-
-    for remove_sigs in remove_rules:
-      signature_set.update(remove_sigs)
-
-    (signature_map, failed_sigs) = self.analyzer.MapAnnotation(funcs,
-                                                               signature_set)
-    result = self.analyzer.ResolveAnnotation(funcs)
-    (add_set, remove_list, eliminated_addrs, failed_sigs) = result
-
-    expect_signature_map = {
-        ('hook_task', None, None): {funcs[0x1000]},
-        ('touchpad_calc', os.path.abspath('a.c'), None): {funcs[0x4000]},
-        ('touchpad_calc', os.path.abspath('b.c'), None): {funcs[0x5000]},
-        ('console_task', None, None): {funcs[0x2000]},
-        ('inlined_mul_alias', None, None): {funcs[0x13100]},
-        ('inlined_mul', os.path.abspath('x.c'), None): {funcs[0x13000],
-                                                        funcs[0x13100]},
-        ('inlined_mul', None, None): {funcs[0x13000], funcs[0x13100]},
-    }
-    self.assertEqual(len(signature_map), len(expect_signature_map))
-    for sig, funclist in signature_map.items():
-      self.assertEqual(set(funclist), expect_signature_map[sig])
-
-    self.assertEqual(add_set, {
-        (funcs[0x1000], funcs[0x4000]),
-        (funcs[0x1000], funcs[0x1000]),
-        (funcs[0x2000], funcs[0x5000]),
-        (funcs[0x2000], funcs[0x13100]),
-        (funcs[0x13000], funcs[0x13000]),
-        (funcs[0x13000], funcs[0x13100]),
-        (funcs[0x13100], funcs[0x13000]),
-        (funcs[0x13100], funcs[0x13100]),
-    })
-    expect_remove_list = [
-        [funcs[0x4000]],
-        [funcs[0x13000]],
-        [funcs[0x13100]],
-        [funcs[0x13000], funcs[0x2000], funcs[0x4000]],
-        [funcs[0x13100], funcs[0x2000], funcs[0x4000]],
-        [funcs[0x13000], funcs[0x13100], funcs[0x2000]],
-        [funcs[0x13100], funcs[0x13100], funcs[0x2000]],
-    ]
-    self.assertEqual(len(remove_list), len(expect_remove_list))
-    for remove_path in remove_list:
-      self.assertTrue(remove_path in expect_remove_list)
-
-    self.assertEqual(eliminated_addrs, {0x1002})
-    self.assertEqual(failed_sigs, {
-        ('touchpad?calc[', sa.StackAnalyzer.ANNOTATION_ERROR_INVALID),
-        ('touchpad_calc', sa.StackAnalyzer.ANNOTATION_ERROR_AMBIGUOUS),
-        ('hook_task[q.c]', sa.StackAnalyzer.ANNOTATION_ERROR_NOTFOUND),
-        ('task_unk[a.c]', sa.StackAnalyzer.ANNOTATION_ERROR_NOTFOUND),
-        ('touchpad_calc[x/a.c]', sa.StackAnalyzer.ANNOTATION_ERROR_NOTFOUND),
-        ('trackpad_range', sa.StackAnalyzer.ANNOTATION_ERROR_NOTFOUND),
-    })
-
-  def testPreprocessAnnotation(self):
-    funcs = {
-        0x1000: sa.Function(0x1000, 'hook_task', 0, []),
-        0x2000: sa.Function(0x2000, 'console_task', 0, []),
-        0x4000: sa.Function(0x4000, 'touchpad_calc', 0, []),
-    }
-    funcs[0x1000].callsites = [
-        sa.Callsite(0x1002, 0x1000, False, funcs[0x1000])]
-    funcs[0x2000].callsites = [
-        sa.Callsite(0x2002, 0x1000, False, funcs[0x1000]),
-        sa.Callsite(0x2006, None, True, None),
-    ]
-    add_set = {
-        (funcs[0x2000], funcs[0x2000]),
-        (funcs[0x2000], funcs[0x4000]),
-        (funcs[0x4000], funcs[0x1000]),
-        (funcs[0x4000], funcs[0x2000]),
-    }
-    remove_list = [
-        [funcs[0x1000]],
-        [funcs[0x2000], funcs[0x2000]],
-        [funcs[0x4000], funcs[0x1000]],
-        [funcs[0x2000], funcs[0x4000], funcs[0x2000]],
-        [funcs[0x4000], funcs[0x1000], funcs[0x4000]],
-    ]
-    eliminated_addrs = {0x2006}
-
-    remaining_remove_list = self.analyzer.PreprocessAnnotation(funcs,
-                                                               add_set,
-                                                               remove_list,
-                                                               eliminated_addrs)
-
-    expect_funcs = {
-        0x1000: sa.Function(0x1000, 'hook_task', 0, []),
-        0x2000: sa.Function(0x2000, 'console_task', 0, []),
-        0x4000: sa.Function(0x4000, 'touchpad_calc', 0, []),
-    }
-    expect_funcs[0x2000].callsites = [
-        sa.Callsite(None, 0x4000, False, expect_funcs[0x4000])]
-    expect_funcs[0x4000].callsites = [
-        sa.Callsite(None, 0x2000, False, expect_funcs[0x2000])]
-    self.assertEqual(funcs, expect_funcs)
-    self.assertEqual(remaining_remove_list, [
-        [funcs[0x2000], funcs[0x4000], funcs[0x2000]],
-    ])
-
-  def testAndesAnalyzeDisassembly(self):
-    disasm_text = (
-        '\n'
-        'build/{BOARD}/RW/ec.RW.elf:     file format elf32-nds32le'
-        '\n'
-        'Disassembly of section .text:\n'
-        '\n'
-        '00000900 <wook_task>:\n'
-        '   ...\n'
-        '00001000 <hook_task>:\n'
-        '   1000:   fc 42\tpush25 $r10, #16    ! {$r6~$r10, $fp, $gp, $lp}\n'
-        '   1004:   47 70\t\tmovi55 $r0, #1\n'
-        '   1006:   b1 13\tbnezs8 100929de <flash_command_write>\n'
-        '   1008:   00 01 5c fc\tbne    $r6, $r0, 2af6a\n'
-        '00002000 <console_task>:\n'
-        '   2000:   fc 00\t\tpush25 $r6, #0    ! {$r6, $fp, $gp, $lp} \n'
-        '   2002:   f0 0e fc c5\tjal   1000 <hook_task>\n'
-        '   2006:   f0 0e bd 3b\tj  53968 <get_program_memory_addr>\n'
-        '   200a:   de ad be ef\tswi.gp $r0, [ + #-11036]\n'
-        '00004000 <touchpad_calc>:\n'
-        '   4000:   47 70\t\tmovi55 $r0, #1\n'
-        '00010000 <look_task>:'
-    )
-    function_map = self.analyzer.AnalyzeDisassembly(disasm_text)
-    func_hook_task = sa.Function(0x1000, 'hook_task', 48, [
-        sa.Callsite(0x1006, 0x100929de, True, None)])
-    expect_funcmap = {
-        0x1000: func_hook_task,
-        0x2000: sa.Function(0x2000, 'console_task', 16,
-                            [sa.Callsite(0x2002, 0x1000, False, func_hook_task),
-                             sa.Callsite(0x2006, 0x53968, True, None)]),
-        0x4000: sa.Function(0x4000, 'touchpad_calc', 0, []),
-    }
-    self.assertEqual(function_map, expect_funcmap)
-
-  def testArmAnalyzeDisassembly(self):
-    disasm_text = (
-        '\n'
-        'build/{BOARD}/RW/ec.RW.elf:     file format elf32-littlearm'
-        '\n'
-        'Disassembly of section .text:\n'
-        '\n'
-        '00000900 <wook_task>:\n'
-        '	...\n'
-        '00001000 <hook_task>:\n'
-        '   1000:	dead beef\tfake\n'
-        '   1004:	4770\t\tbx	lr\n'
-        '   1006:	b113\tcbz	r3, 100929de <flash_command_write>\n'
-        '   1008:	00015cfc\t.word	0x00015cfc\n'
-        '00002000 <console_task>:\n'
-        '   2000:	b508\t\tpush	{r3, lr} ; malformed comments,; r0, r1 \n'
-        '   2002:	f00e fcc5\tbl	1000 <hook_task>\n'
-        '   2006:	f00e bd3b\tb.w	53968 <get_program_memory_addr>\n'
-        '   200a:	dead beef\tfake\n'
-        '00004000 <touchpad_calc>:\n'
-        '   4000:	4770\t\tbx	lr\n'
-        '00010000 <look_task>:'
-    )
-    function_map = self.analyzer.AnalyzeDisassembly(disasm_text)
-    func_hook_task = sa.Function(0x1000, 'hook_task', 0, [
-        sa.Callsite(0x1006, 0x100929de, True, None)])
-    expect_funcmap = {
-        0x1000: func_hook_task,
-        0x2000: sa.Function(0x2000, 'console_task', 8,
-                            [sa.Callsite(0x2002, 0x1000, False, func_hook_task),
-                             sa.Callsite(0x2006, 0x53968, True, None)]),
-        0x4000: sa.Function(0x4000, 'touchpad_calc', 0, []),
-    }
-    self.assertEqual(function_map, expect_funcmap)
-
-  def testAnalyzeCallGraph(self):
-    funcs = {
-        0x1000: sa.Function(0x1000, 'hook_task', 0, []),
-        0x2000: sa.Function(0x2000, 'console_task', 8, []),
-        0x3000: sa.Function(0x3000, 'task_a', 12, []),
-        0x4000: sa.Function(0x4000, 'task_b', 96, []),
-        0x5000: sa.Function(0x5000, 'task_c', 32, []),
-        0x6000: sa.Function(0x6000, 'task_d', 100, []),
-        0x7000: sa.Function(0x7000, 'task_e', 24, []),
-        0x8000: sa.Function(0x8000, 'task_f', 20, []),
-        0x9000: sa.Function(0x9000, 'task_g', 20, []),
-        0x10000: sa.Function(0x10000, 'task_x', 16, []),
-    }
-    funcs[0x1000].callsites = [
-        sa.Callsite(0x1002, 0x3000, False, funcs[0x3000]),
-        sa.Callsite(0x1006, 0x4000, False, funcs[0x4000])]
-    funcs[0x2000].callsites = [
-        sa.Callsite(0x2002, 0x5000, False, funcs[0x5000]),
-        sa.Callsite(0x2006, 0x2000, False, funcs[0x2000]),
-        sa.Callsite(0x200a, 0x10000, False, funcs[0x10000])]
-    funcs[0x3000].callsites = [
-        sa.Callsite(0x3002, 0x4000, False, funcs[0x4000]),
-        sa.Callsite(0x3006, 0x1000, False, funcs[0x1000])]
-    funcs[0x4000].callsites = [
-        sa.Callsite(0x4002, 0x6000, True, funcs[0x6000]),
-        sa.Callsite(0x4006, 0x7000, False, funcs[0x7000]),
-        sa.Callsite(0x400a, 0x8000, False, funcs[0x8000])]
-    funcs[0x5000].callsites = [
-        sa.Callsite(0x5002, 0x4000, False, funcs[0x4000])]
-    funcs[0x7000].callsites = [
-        sa.Callsite(0x7002, 0x7000, False, funcs[0x7000])]
-    funcs[0x8000].callsites = [
-        sa.Callsite(0x8002, 0x9000, False, funcs[0x9000])]
-    funcs[0x9000].callsites = [
-        sa.Callsite(0x9002, 0x4000, False, funcs[0x4000])]
-    funcs[0x10000].callsites = [
-        sa.Callsite(0x10002, 0x2000, False, funcs[0x2000])]
-
-    cycles = self.analyzer.AnalyzeCallGraph(funcs, [
-        [funcs[0x2000]] * 2,
-        [funcs[0x10000], funcs[0x2000]] * 3,
-        [funcs[0x1000], funcs[0x3000], funcs[0x1000]]
-    ])
-
-    expect_func_stack = {
-        0x1000: (268, [funcs[0x1000],
-                       funcs[0x3000],
-                       funcs[0x4000],
-                       funcs[0x8000],
-                       funcs[0x9000],
-                       funcs[0x4000],
-                       funcs[0x7000]]),
-        0x2000: (208, [funcs[0x2000],
-                       funcs[0x10000],
-                       funcs[0x2000],
-                       funcs[0x10000],
-                       funcs[0x2000],
-                       funcs[0x5000],
-                       funcs[0x4000],
-                       funcs[0x7000]]),
-        0x3000: (280, [funcs[0x3000],
-                       funcs[0x1000],
-                       funcs[0x3000],
-                       funcs[0x4000],
-                       funcs[0x8000],
-                       funcs[0x9000],
-                       funcs[0x4000],
-                       funcs[0x7000]]),
-        0x4000: (120, [funcs[0x4000], funcs[0x7000]]),
-        0x5000: (152, [funcs[0x5000], funcs[0x4000], funcs[0x7000]]),
-        0x6000: (100, [funcs[0x6000]]),
-        0x7000: (24, [funcs[0x7000]]),
-        0x8000: (160, [funcs[0x8000],
-                       funcs[0x9000],
-                       funcs[0x4000],
-                       funcs[0x7000]]),
-        0x9000: (140, [funcs[0x9000], funcs[0x4000], funcs[0x7000]]),
-        0x10000: (200, [funcs[0x10000],
-                        funcs[0x2000],
-                        funcs[0x10000],
-                        funcs[0x2000],
-                        funcs[0x5000],
-                        funcs[0x4000],
-                        funcs[0x7000]]),
-    }
-    expect_cycles = [
-        {funcs[0x4000], funcs[0x8000], funcs[0x9000]},
-        {funcs[0x7000]},
-    ]
-    for func in funcs.values():
-      (stack_max_usage, stack_max_path) = expect_func_stack[func.address]
-      self.assertEqual(func.stack_max_usage, stack_max_usage)
-      self.assertEqual(func.stack_max_path, stack_max_path)
-
-    self.assertEqual(len(cycles), len(expect_cycles))
-    for cycle in cycles:
-      self.assertTrue(cycle in expect_cycles)
-
-  @mock.patch('subprocess.check_output')
-  def testAddressToLine(self, checkoutput_mock):
-    checkoutput_mock.return_value = 'fake_func\n/test.c:1'
-    self.assertEqual(self.analyzer.AddressToLine(0x1234),
-                     [('fake_func', '/test.c', 1)])
-    checkoutput_mock.assert_called_once_with(
-        ['addr2line', '-f', '-e', './ec.RW.elf', '1234'], encoding='utf-8')
-    checkoutput_mock.reset_mock()
-
-    checkoutput_mock.return_value = 'fake_func\n/a.c:1\nbake_func\n/b.c:2\n'
-    self.assertEqual(self.analyzer.AddressToLine(0x1234, True),
-                     [('fake_func', '/a.c', 1), ('bake_func', '/b.c', 2)])
-    checkoutput_mock.assert_called_once_with(
-        ['addr2line', '-f', '-e', './ec.RW.elf', '1234', '-i'],
-        encoding='utf-8')
-    checkoutput_mock.reset_mock()
-
-    checkoutput_mock.return_value = 'fake_func\n/test.c:1 (discriminator 128)'
-    self.assertEqual(self.analyzer.AddressToLine(0x12345),
-                     [('fake_func', '/test.c', 1)])
-    checkoutput_mock.assert_called_once_with(
-        ['addr2line', '-f', '-e', './ec.RW.elf', '12345'], encoding='utf-8')
-    checkoutput_mock.reset_mock()
-
-    checkoutput_mock.return_value = '??\n:?\nbake_func\n/b.c:2\n'
-    self.assertEqual(self.analyzer.AddressToLine(0x123456),
-                     [None, ('bake_func', '/b.c', 2)])
-    checkoutput_mock.assert_called_once_with(
-        ['addr2line', '-f', '-e', './ec.RW.elf', '123456'], encoding='utf-8')
-    checkoutput_mock.reset_mock()
-
-    with self.assertRaisesRegexp(sa.StackAnalyzerError,
-                                 'addr2line failed to resolve lines.'):
-      checkoutput_mock.side_effect = subprocess.CalledProcessError(1, '')
-      self.analyzer.AddressToLine(0x5678)
-
-    with self.assertRaisesRegexp(sa.StackAnalyzerError,
-                                 'Failed to run addr2line.'):
-      checkoutput_mock.side_effect = OSError()
-      self.analyzer.AddressToLine(0x9012)
-
-  @mock.patch('subprocess.check_output')
-  @mock.patch('stack_analyzer.StackAnalyzer.AddressToLine')
-  def testAndesAnalyze(self, addrtoline_mock, checkoutput_mock):
-    disasm_text = (
-        '\n'
-        'build/{BOARD}/RW/ec.RW.elf:     file format elf32-nds32le'
-        '\n'
-        'Disassembly of section .text:\n'
-        '\n'
-        '00000900 <wook_task>:\n'
-        '   ...\n'
-        '00001000 <hook_task>:\n'
-        '   1000:   fc 00\t\tpush25 $r10, #16    ! {$r6~$r10, $fp, $gp, $lp}\n'
-        '   1002:   47 70\t\tmovi55 $r0, #1\n'
-        '   1006:   00 01 5c fc\tbne    $r6, $r0, 2af6a\n'
-        '00002000 <console_task>:\n'
-        '   2000:   fc 00\t\tpush25 $r6, #0    ! {$r6, $fp, $gp, $lp} \n'
-        '   2002:   f0 0e fc c5\tjal   1000 <hook_task>\n'
-        '   2006:   f0 0e bd 3b\tj  53968 <get_program_memory_addr>\n'
-        '   200a:   12 34 56 78\tjral5 $r0\n'
-    )
-
-    addrtoline_mock.return_value = [('??', '??', 0)]
-    self.analyzer.annotation = {
-        'exception_frame_size': 64,
-        'remove': [['fake_func']],
-    }
-
-    with mock.patch('builtins.print') as print_mock:
-      checkoutput_mock.return_value = disasm_text
-      self.analyzer.Analyze()
-      print_mock.assert_has_calls([
-          mock.call(
-              'Task: HOOKS, Max size: 96 (32 + 64), Allocated size: 2048'),
-          mock.call('Call Trace:'),
-          mock.call('    hook_task (32) [??:0] 1000'),
-          mock.call(
-              'Task: CONSOLE, Max size: 112 (48 + 64), Allocated size: 460'),
-          mock.call('Call Trace:'),
-          mock.call('    console_task (16) [??:0] 2000'),
-          mock.call('        -> ??[??:0] 2002'),
-          mock.call('    hook_task (32) [??:0] 1000'),
-          mock.call('Unresolved indirect callsites:'),
-          mock.call('    In function console_task:'),
-          mock.call('        -> ??[??:0] 200a'),
-          mock.call('Unresolved annotation signatures:'),
-          mock.call('    fake_func: function is not found'),
-      ])
-
-    with self.assertRaisesRegexp(sa.StackAnalyzerError,
-                                 'Failed to run objdump.'):
-      checkoutput_mock.side_effect = OSError()
-      self.analyzer.Analyze()
-
-    with self.assertRaisesRegexp(sa.StackAnalyzerError,
-                                 'objdump failed to disassemble.'):
-      checkoutput_mock.side_effect = subprocess.CalledProcessError(1, '')
-      self.analyzer.Analyze()
-
-  @mock.patch('subprocess.check_output')
-  @mock.patch('stack_analyzer.StackAnalyzer.AddressToLine')
-  def testArmAnalyze(self, addrtoline_mock, checkoutput_mock):
-    disasm_text = (
-        '\n'
-        'build/{BOARD}/RW/ec.RW.elf:     file format elf32-littlearm'
-        '\n'
-        'Disassembly of section .text:\n'
-        '\n'
-        '00000900 <wook_task>:\n'
-        '	...\n'
-        '00001000 <hook_task>:\n'
-        '   1000:	b508\t\tpush	{r3, lr}\n'
-        '   1002:	4770\t\tbx	lr\n'
-        '   1006:	00015cfc\t.word	0x00015cfc\n'
-        '00002000 <console_task>:\n'
-        '   2000:	b508\t\tpush	{r3, lr}\n'
-        '   2002:	f00e fcc5\tbl	1000 <hook_task>\n'
-        '   2006:	f00e bd3b\tb.w	53968 <get_program_memory_addr>\n'
-        '   200a:	1234 5678\tb.w  sl\n'
-    )
-
-    addrtoline_mock.return_value = [('??', '??', 0)]
-    self.analyzer.annotation = {
-        'exception_frame_size': 64,
-        'remove': [['fake_func']],
-    }
-
-    with mock.patch('builtins.print') as print_mock:
-      checkoutput_mock.return_value = disasm_text
-      self.analyzer.Analyze()
-      print_mock.assert_has_calls([
-          mock.call(
-              'Task: HOOKS, Max size: 72 (8 + 64), Allocated size: 2048'),
-          mock.call('Call Trace:'),
-          mock.call('    hook_task (8) [??:0] 1000'),
-          mock.call(
-              'Task: CONSOLE, Max size: 80 (16 + 64), Allocated size: 460'),
-          mock.call('Call Trace:'),
-          mock.call('    console_task (8) [??:0] 2000'),
-          mock.call('        -> ??[??:0] 2002'),
-          mock.call('    hook_task (8) [??:0] 1000'),
-          mock.call('Unresolved indirect callsites:'),
-          mock.call('    In function console_task:'),
-          mock.call('        -> ??[??:0] 200a'),
-          mock.call('Unresolved annotation signatures:'),
-          mock.call('    fake_func: function is not found'),
-      ])
-
-    with self.assertRaisesRegexp(sa.StackAnalyzerError,
-                                 'Failed to run objdump.'):
-      checkoutput_mock.side_effect = OSError()
-      self.analyzer.Analyze()
-
-    with self.assertRaisesRegexp(sa.StackAnalyzerError,
-                                 'objdump failed to disassemble.'):
-      checkoutput_mock.side_effect = subprocess.CalledProcessError(1, '')
-      self.analyzer.Analyze()
-
-  @mock.patch('subprocess.check_output')
-  @mock.patch('stack_analyzer.ParseArgs')
-  def testMain(self, parseargs_mock, checkoutput_mock):
-    symbol_text = ('1000 g     F .text  0000015c .hidden hook_task\n'
-                   '2000 g     F .text  0000051c .hidden console_task\n')
-    rodata_text = (
-        '\n'
-        'Contents of section .rodata:\n'
-        ' 20000 dead1000 00100000 dead2000 00200000  He..f.He..s.\n'
-    )
-
-    args = mock.MagicMock(elf_path='./ec.RW.elf',
-                          export_taskinfo='fake',
-                          section='RW',
-                          objdump='objdump',
-                          addr2line='addr2line',
-                          annotation='fake')
-    parseargs_mock.return_value = args
-
-    with mock.patch('os.path.exists') as path_mock:
-      path_mock.return_value = False
-      with mock.patch('builtins.print') as print_mock:
-        with mock.patch('builtins.open', mock.mock_open()) as open_mock:
-          sa.main()
-          print_mock.assert_any_call(
-              'Warning: Annotation file fake does not exist.')
-
-    with mock.patch('os.path.exists') as path_mock:
-      path_mock.return_value = True
-      with mock.patch('builtins.print') as print_mock:
-        with mock.patch('builtins.open', mock.mock_open()) as open_mock:
-          open_mock.side_effect = IOError()
-          sa.main()
-          print_mock.assert_called_once_with(
-              'Error: Failed to open annotation file fake.')
-
-      with mock.patch('builtins.print') as print_mock:
-        with mock.patch('builtins.open', mock.mock_open()) as open_mock:
-          open_mock.return_value.read.side_effect = ['{', '']
-          sa.main()
-          open_mock.assert_called_once_with('fake', 'r')
-          print_mock.assert_called_once_with(
-              'Error: Failed to parse annotation file fake.')
-
-      with mock.patch('builtins.print') as print_mock:
-        with mock.patch('builtins.open',
-                        mock.mock_open(read_data='')) as open_mock:
-          sa.main()
-          print_mock.assert_called_once_with(
-              'Error: Invalid annotation file fake.')
-
-    args.annotation = None
-
-    with mock.patch('builtins.print') as print_mock:
-      checkoutput_mock.side_effect = [symbol_text, rodata_text]
-      sa.main()
-      print_mock.assert_called_once_with(
-          'Error: Failed to load export_taskinfo.')
-
-    with mock.patch('builtins.print') as print_mock:
-      checkoutput_mock.side_effect = subprocess.CalledProcessError(1, '')
-      sa.main()
-      print_mock.assert_called_once_with(
-          'Error: objdump failed to dump symbol table or rodata.')
-
-    with mock.patch('builtins.print') as print_mock:
-      checkoutput_mock.side_effect = OSError()
-      sa.main()
-      print_mock.assert_called_once_with('Error: Failed to run objdump.')
-
-
-if __name__ == '__main__':
-  unittest.main()
+        (
+            add_rules,
+            remove_rules,
+            invalid_sigtxts,
+        ) = self.analyzer.LoadAnnotation()
+        self.assertEqual(add_rules, {})
+        self.assertEqual(
+            list.sort(remove_rules),
+            list.sort(
+                [
+                    [("a", None, None), ("1", None, None), ("x", None, None)],
+                    [("a", None, None), ("0", None, None), ("x", None, None)],
+                    [("a", None, None), ("2", None, None), ("x", None, None)],
+                    [
+                        ("b", os.path.abspath("x"), 3),
+                        ("1", None, None),
+                        ("x", None, None),
+                    ],
+                    [
+                        ("b", os.path.abspath("x"), 3),
+                        ("0", None, None),
+                        ("x", None, None),
+                    ],
+                    [
+                        ("b", os.path.abspath("x"), 3),
+                        ("2", None, None),
+                        ("x", None, None),
+                    ],
+                ]
+            ),
+        )
+        self.assertEqual(invalid_sigtxts, {"["})
+
+        self.analyzer.annotation = {
+            "add": {
+                "touchpad_calc": [dict(name="__array", stride=8, offset=4)],
+            }
+        }
+        (
+            add_rules,
+            remove_rules,
+            invalid_sigtxts,
+        ) = self.analyzer.LoadAnnotation()
+        self.assertEqual(
+            add_rules,
+            {
+                ("touchpad_calc", None, None): set(
+                    [("console_task", None, None), ("hook_task", None, None)]
+                )
+            },
+        )
+
+        funcs = {
+            0x1000: sa.Function(0x1000, "hook_task", 0, []),
+            0x2000: sa.Function(0x2000, "console_task", 0, []),
+            0x4000: sa.Function(0x4000, "touchpad_calc", 0, []),
+            0x5000: sa.Function(0x5000, "touchpad_calc.constprop.42", 0, []),
+            0x13000: sa.Function(0x13000, "inlined_mul", 0, []),
+            0x13100: sa.Function(0x13100, "inlined_mul", 0, []),
+        }
+        funcs[0x1000].callsites = [sa.Callsite(0x1002, None, False, None)]
+        # Set address_to_line_cache to fake the results of addr2line.
+        self.analyzer.address_to_line_cache = {
+            (0x1000, False): [("hook_task", os.path.abspath("a.c"), 10)],
+            (0x1002, False): [("toot_calc", os.path.abspath("t.c"), 1234)],
+            (0x2000, False): [("console_task", os.path.abspath("b.c"), 20)],
+            (0x4000, False): [("toudhpad_calc", os.path.abspath("a.c"), 20)],
+            (0x5000, False): [
+                ("touchpad_calc.constprop.42", os.path.abspath("b.c"), 40)
+            ],
+            (0x12000, False): [("trackpad_range", os.path.abspath("t.c"), 10)],
+            (0x13000, False): [("inlined_mul", os.path.abspath("x.c"), 12)],
+            (0x13100, False): [("inlined_mul", os.path.abspath("x.c"), 12)],
+        }
+        self.analyzer.annotation = {
+            "add": {
+                "hook_task.lto.573": ["touchpad_calc.lto.2501[a.c]"],
+                "console_task": ["touchpad_calc[b.c]", "inlined_mul_alias"],
+                "hook_task[q.c]": ["hook_task"],
+                "inlined_mul[x.c]": ["inlined_mul"],
+                "toot_calc[t.c:1234]": ["hook_task"],
+            },
+            "remove": [
+                ["touchpad?calc["],
+                "touchpad_calc",
+                ["touchpad_calc[a.c]"],
+                ["task_unk[a.c]"],
+                ["touchpad_calc[x/a.c]"],
+                ["trackpad_range"],
+                ["inlined_mul"],
+                ["inlined_mul", "console_task", "touchpad_calc[a.c]"],
+                ["inlined_mul", "inlined_mul_alias", "console_task"],
+                ["inlined_mul", "inlined_mul_alias", "console_task"],
+            ],
+        }
+        (
+            add_rules,
+            remove_rules,
+            invalid_sigtxts,
+        ) = self.analyzer.LoadAnnotation()
+        self.assertEqual(invalid_sigtxts, {"touchpad?calc["})
+
+        signature_set = set()
+        for src_sig, dst_sigs in add_rules.items():
+            signature_set.add(src_sig)
+            signature_set.update(dst_sigs)
+
+        for remove_sigs in remove_rules:
+            signature_set.update(remove_sigs)
+
+        (signature_map, failed_sigs) = self.analyzer.MapAnnotation(
+            funcs, signature_set
+        )
+        result = self.analyzer.ResolveAnnotation(funcs)
+        (add_set, remove_list, eliminated_addrs, failed_sigs) = result
+
+        expect_signature_map = {
+            ("hook_task", None, None): {funcs[0x1000]},
+            ("touchpad_calc", os.path.abspath("a.c"), None): {funcs[0x4000]},
+            ("touchpad_calc", os.path.abspath("b.c"), None): {funcs[0x5000]},
+            ("console_task", None, None): {funcs[0x2000]},
+            ("inlined_mul_alias", None, None): {funcs[0x13100]},
+            ("inlined_mul", os.path.abspath("x.c"), None): {
+                funcs[0x13000],
+                funcs[0x13100],
+            },
+            ("inlined_mul", None, None): {funcs[0x13000], funcs[0x13100]},
+        }
+        self.assertEqual(len(signature_map), len(expect_signature_map))
+        for sig, funclist in signature_map.items():
+            self.assertEqual(set(funclist), expect_signature_map[sig])
+
+        self.assertEqual(
+            add_set,
+            {
+                (funcs[0x1000], funcs[0x4000]),
+                (funcs[0x1000], funcs[0x1000]),
+                (funcs[0x2000], funcs[0x5000]),
+                (funcs[0x2000], funcs[0x13100]),
+                (funcs[0x13000], funcs[0x13000]),
+                (funcs[0x13000], funcs[0x13100]),
+                (funcs[0x13100], funcs[0x13000]),
+                (funcs[0x13100], funcs[0x13100]),
+            },
+        )
+        expect_remove_list = [
+            [funcs[0x4000]],
+            [funcs[0x13000]],
+            [funcs[0x13100]],
+            [funcs[0x13000], funcs[0x2000], funcs[0x4000]],
+            [funcs[0x13100], funcs[0x2000], funcs[0x4000]],
+            [funcs[0x13000], funcs[0x13100], funcs[0x2000]],
+            [funcs[0x13100], funcs[0x13100], funcs[0x2000]],
+        ]
+        self.assertEqual(len(remove_list), len(expect_remove_list))
+        for remove_path in remove_list:
+            self.assertTrue(remove_path in expect_remove_list)
+
+        self.assertEqual(eliminated_addrs, {0x1002})
+        self.assertEqual(
+            failed_sigs,
+            {
+                ("touchpad?calc[", sa.StackAnalyzer.ANNOTATION_ERROR_INVALID),
+                ("touchpad_calc", sa.StackAnalyzer.ANNOTATION_ERROR_AMBIGUOUS),
+                ("hook_task[q.c]", sa.StackAnalyzer.ANNOTATION_ERROR_NOTFOUND),
+                ("task_unk[a.c]", sa.StackAnalyzer.ANNOTATION_ERROR_NOTFOUND),
+                (
+                    "touchpad_calc[x/a.c]",
+                    sa.StackAnalyzer.ANNOTATION_ERROR_NOTFOUND,
+                ),
+                ("trackpad_range", sa.StackAnalyzer.ANNOTATION_ERROR_NOTFOUND),
+            },
+        )
+
+    def testPreprocessAnnotation(self):
+        funcs = {
+            0x1000: sa.Function(0x1000, "hook_task", 0, []),
+            0x2000: sa.Function(0x2000, "console_task", 0, []),
+            0x4000: sa.Function(0x4000, "touchpad_calc", 0, []),
+        }
+        funcs[0x1000].callsites = [
+            sa.Callsite(0x1002, 0x1000, False, funcs[0x1000])
+        ]
+        funcs[0x2000].callsites = [
+            sa.Callsite(0x2002, 0x1000, False, funcs[0x1000]),
+            sa.Callsite(0x2006, None, True, None),
+        ]
+        add_set = {
+            (funcs[0x2000], funcs[0x2000]),
+            (funcs[0x2000], funcs[0x4000]),
+            (funcs[0x4000], funcs[0x1000]),
+            (funcs[0x4000], funcs[0x2000]),
+        }
+        remove_list = [
+            [funcs[0x1000]],
+            [funcs[0x2000], funcs[0x2000]],
+            [funcs[0x4000], funcs[0x1000]],
+            [funcs[0x2000], funcs[0x4000], funcs[0x2000]],
+            [funcs[0x4000], funcs[0x1000], funcs[0x4000]],
+        ]
+        eliminated_addrs = {0x2006}
+
+        remaining_remove_list = self.analyzer.PreprocessAnnotation(
+            funcs, add_set, remove_list, eliminated_addrs
+        )
+
+        expect_funcs = {
+            0x1000: sa.Function(0x1000, "hook_task", 0, []),
+            0x2000: sa.Function(0x2000, "console_task", 0, []),
+            0x4000: sa.Function(0x4000, "touchpad_calc", 0, []),
+        }
+        expect_funcs[0x2000].callsites = [
+            sa.Callsite(None, 0x4000, False, expect_funcs[0x4000])
+        ]
+        expect_funcs[0x4000].callsites = [
+            sa.Callsite(None, 0x2000, False, expect_funcs[0x2000])
+        ]
+        self.assertEqual(funcs, expect_funcs)
+        self.assertEqual(
+            remaining_remove_list,
+            [
+                [funcs[0x2000], funcs[0x4000], funcs[0x2000]],
+            ],
+        )
+
+    def testAndesAnalyzeDisassembly(self):
+        disasm_text = (
+            "\n"
+            "build/{BOARD}/RW/ec.RW.elf:     file format elf32-nds32le"
+            "\n"
+            "Disassembly of section .text:\n"
+            "\n"
+            "00000900 <wook_task>:\n"
+            "   ...\n"
+            "00001000 <hook_task>:\n"
+            "   1000:   fc 42\tpush25 $r10, #16    ! {$r6~$r10, $fp, $gp, $lp}\n"
+            "   1004:   47 70\t\tmovi55 $r0, #1\n"
+            "   1006:   b1 13\tbnezs8 100929de <flash_command_write>\n"
+            "   1008:   00 01 5c fc\tbne    $r6, $r0, 2af6a\n"
+            "00002000 <console_task>:\n"
+            "   2000:   fc 00\t\tpush25 $r6, #0    ! {$r6, $fp, $gp, $lp} \n"
+            "   2002:   f0 0e fc c5\tjal   1000 <hook_task>\n"
+            "   2006:   f0 0e bd 3b\tj  53968 <get_program_memory_addr>\n"
+            "   200a:   de ad be ef\tswi.gp $r0, [ + #-11036]\n"
+            "00004000 <touchpad_calc>:\n"
+            "   4000:   47 70\t\tmovi55 $r0, #1\n"
+            "00010000 <look_task>:"
+        )
+        function_map = self.analyzer.AnalyzeDisassembly(disasm_text)
+        func_hook_task = sa.Function(
+            0x1000,
+            "hook_task",
+            48,
+            [sa.Callsite(0x1006, 0x100929DE, True, None)],
+        )
+        expect_funcmap = {
+            0x1000: func_hook_task,
+            0x2000: sa.Function(
+                0x2000,
+                "console_task",
+                16,
+                [
+                    sa.Callsite(0x2002, 0x1000, False, func_hook_task),
+                    sa.Callsite(0x2006, 0x53968, True, None),
+                ],
+            ),
+            0x4000: sa.Function(0x4000, "touchpad_calc", 0, []),
+        }
+        self.assertEqual(function_map, expect_funcmap)
+
+    def testArmAnalyzeDisassembly(self):
+        disasm_text = (
+            "\n"
+            "build/{BOARD}/RW/ec.RW.elf:     file format elf32-littlearm"
+            "\n"
+            "Disassembly of section .text:\n"
+            "\n"
+            "00000900 <wook_task>:\n"
+            "	...\n"
+            "00001000 <hook_task>:\n"
+            "   1000:	dead beef\tfake\n"
+            "   1004:	4770\t\tbx	lr\n"
+            "   1006:	b113\tcbz	r3, 100929de <flash_command_write>\n"
+            "   1008:	00015cfc\t.word	0x00015cfc\n"
+            "00002000 <console_task>:\n"
+            "   2000:	b508\t\tpush	{r3, lr} ; malformed comments,; r0, r1 \n"
+            "   2002:	f00e fcc5\tbl	1000 <hook_task>\n"
+            "   2006:	f00e bd3b\tb.w	53968 <get_program_memory_addr>\n"
+            "   200a:	dead beef\tfake\n"
+            "00004000 <touchpad_calc>:\n"
+            "   4000:	4770\t\tbx	lr\n"
+            "00010000 <look_task>:"
+        )
+        function_map = self.analyzer.AnalyzeDisassembly(disasm_text)
+        func_hook_task = sa.Function(
+            0x1000,
+            "hook_task",
+            0,
+            [sa.Callsite(0x1006, 0x100929DE, True, None)],
+        )
+        expect_funcmap = {
+            0x1000: func_hook_task,
+            0x2000: sa.Function(
+                0x2000,
+                "console_task",
+                8,
+                [
+                    sa.Callsite(0x2002, 0x1000, False, func_hook_task),
+                    sa.Callsite(0x2006, 0x53968, True, None),
+                ],
+            ),
+            0x4000: sa.Function(0x4000, "touchpad_calc", 0, []),
+        }
+        self.assertEqual(function_map, expect_funcmap)
+
+    def testAnalyzeCallGraph(self):
+        funcs = {
+            0x1000: sa.Function(0x1000, "hook_task", 0, []),
+            0x2000: sa.Function(0x2000, "console_task", 8, []),
+            0x3000: sa.Function(0x3000, "task_a", 12, []),
+            0x4000: sa.Function(0x4000, "task_b", 96, []),
+            0x5000: sa.Function(0x5000, "task_c", 32, []),
+            0x6000: sa.Function(0x6000, "task_d", 100, []),
+            0x7000: sa.Function(0x7000, "task_e", 24, []),
+            0x8000: sa.Function(0x8000, "task_f", 20, []),
+            0x9000: sa.Function(0x9000, "task_g", 20, []),
+            0x10000: sa.Function(0x10000, "task_x", 16, []),
+        }
+        funcs[0x1000].callsites = [
+            sa.Callsite(0x1002, 0x3000, False, funcs[0x3000]),
+            sa.Callsite(0x1006, 0x4000, False, funcs[0x4000]),
+        ]
+        funcs[0x2000].callsites = [
+            sa.Callsite(0x2002, 0x5000, False, funcs[0x5000]),
+            sa.Callsite(0x2006, 0x2000, False, funcs[0x2000]),
+            sa.Callsite(0x200A, 0x10000, False, funcs[0x10000]),
+        ]
+        funcs[0x3000].callsites = [
+            sa.Callsite(0x3002, 0x4000, False, funcs[0x4000]),
+            sa.Callsite(0x3006, 0x1000, False, funcs[0x1000]),
+        ]
+        funcs[0x4000].callsites = [
+            sa.Callsite(0x4002, 0x6000, True, funcs[0x6000]),
+            sa.Callsite(0x4006, 0x7000, False, funcs[0x7000]),
+            sa.Callsite(0x400A, 0x8000, False, funcs[0x8000]),
+        ]
+        funcs[0x5000].callsites = [
+            sa.Callsite(0x5002, 0x4000, False, funcs[0x4000])
+        ]
+        funcs[0x7000].callsites = [
+            sa.Callsite(0x7002, 0x7000, False, funcs[0x7000])
+        ]
+        funcs[0x8000].callsites = [
+            sa.Callsite(0x8002, 0x9000, False, funcs[0x9000])
+        ]
+        funcs[0x9000].callsites = [
+            sa.Callsite(0x9002, 0x4000, False, funcs[0x4000])
+        ]
+        funcs[0x10000].callsites = [
+            sa.Callsite(0x10002, 0x2000, False, funcs[0x2000])
+        ]
+
+        cycles = self.analyzer.AnalyzeCallGraph(
+            funcs,
+            [
+                [funcs[0x2000]] * 2,
+                [funcs[0x10000], funcs[0x2000]] * 3,
+                [funcs[0x1000], funcs[0x3000], funcs[0x1000]],
+            ],
+        )
+
+        expect_func_stack = {
+            0x1000: (
+                268,
+                [
+                    funcs[0x1000],
+                    funcs[0x3000],
+                    funcs[0x4000],
+                    funcs[0x8000],
+                    funcs[0x9000],
+                    funcs[0x4000],
+                    funcs[0x7000],
+                ],
+            ),
+            0x2000: (
+                208,
+                [
+                    funcs[0x2000],
+                    funcs[0x10000],
+                    funcs[0x2000],
+                    funcs[0x10000],
+                    funcs[0x2000],
+                    funcs[0x5000],
+                    funcs[0x4000],
+                    funcs[0x7000],
+                ],
+            ),
+            0x3000: (
+                280,
+                [
+                    funcs[0x3000],
+                    funcs[0x1000],
+                    funcs[0x3000],
+                    funcs[0x4000],
+                    funcs[0x8000],
+                    funcs[0x9000],
+                    funcs[0x4000],
+                    funcs[0x7000],
+                ],
+            ),
+            0x4000: (120, [funcs[0x4000], funcs[0x7000]]),
+            0x5000: (152, [funcs[0x5000], funcs[0x4000], funcs[0x7000]]),
+            0x6000: (100, [funcs[0x6000]]),
+            0x7000: (24, [funcs[0x7000]]),
+            0x8000: (
+                160,
+                [funcs[0x8000], funcs[0x9000], funcs[0x4000], funcs[0x7000]],
+            ),
+            0x9000: (140, [funcs[0x9000], funcs[0x4000], funcs[0x7000]]),
+            0x10000: (
+                200,
+                [
+                    funcs[0x10000],
+                    funcs[0x2000],
+                    funcs[0x10000],
+                    funcs[0x2000],
+                    funcs[0x5000],
+                    funcs[0x4000],
+                    funcs[0x7000],
+                ],
+            ),
+        }
+        expect_cycles = [
+            {funcs[0x4000], funcs[0x8000], funcs[0x9000]},
+            {funcs[0x7000]},
+        ]
+        for func in funcs.values():
+            (stack_max_usage, stack_max_path) = expect_func_stack[func.address]
+            self.assertEqual(func.stack_max_usage, stack_max_usage)
+            self.assertEqual(func.stack_max_path, stack_max_path)
+
+        self.assertEqual(len(cycles), len(expect_cycles))
+        for cycle in cycles:
+            self.assertTrue(cycle in expect_cycles)
+
+    @mock.patch("subprocess.check_output")
+    def testAddressToLine(self, checkoutput_mock):
+        checkoutput_mock.return_value = "fake_func\n/test.c:1"
+        self.assertEqual(
+            self.analyzer.AddressToLine(0x1234), [("fake_func", "/test.c", 1)]
+        )
+        checkoutput_mock.assert_called_once_with(
+            ["addr2line", "-f", "-e", "./ec.RW.elf", "1234"], encoding="utf-8"
+        )
+        checkoutput_mock.reset_mock()
+
+        checkoutput_mock.return_value = "fake_func\n/a.c:1\nbake_func\n/b.c:2\n"
+        self.assertEqual(
+            self.analyzer.AddressToLine(0x1234, True),
+            [("fake_func", "/a.c", 1), ("bake_func", "/b.c", 2)],
+        )
+        checkoutput_mock.assert_called_once_with(
+            ["addr2line", "-f", "-e", "./ec.RW.elf", "1234", "-i"],
+            encoding="utf-8",
+        )
+        checkoutput_mock.reset_mock()
+
+        checkoutput_mock.return_value = (
+            "fake_func\n/test.c:1 (discriminator 128)"
+        )
+        self.assertEqual(
+            self.analyzer.AddressToLine(0x12345), [("fake_func", "/test.c", 1)]
+        )
+        checkoutput_mock.assert_called_once_with(
+            ["addr2line", "-f", "-e", "./ec.RW.elf", "12345"], encoding="utf-8"
+        )
+        checkoutput_mock.reset_mock()
+
+        checkoutput_mock.return_value = "??\n:?\nbake_func\n/b.c:2\n"
+        self.assertEqual(
+            self.analyzer.AddressToLine(0x123456),
+            [None, ("bake_func", "/b.c", 2)],
+        )
+        checkoutput_mock.assert_called_once_with(
+            ["addr2line", "-f", "-e", "./ec.RW.elf", "123456"], encoding="utf-8"
+        )
+        checkoutput_mock.reset_mock()
+
+        with self.assertRaisesRegexp(
+            sa.StackAnalyzerError, "addr2line failed to resolve lines."
+        ):
+            checkoutput_mock.side_effect = subprocess.CalledProcessError(1, "")
+            self.analyzer.AddressToLine(0x5678)
+
+        with self.assertRaisesRegexp(
+            sa.StackAnalyzerError, "Failed to run addr2line."
+        ):
+            checkoutput_mock.side_effect = OSError()
+            self.analyzer.AddressToLine(0x9012)
+
+    @mock.patch("subprocess.check_output")
+    @mock.patch("stack_analyzer.StackAnalyzer.AddressToLine")
+    def testAndesAnalyze(self, addrtoline_mock, checkoutput_mock):
+        disasm_text = (
+            "\n"
+            "build/{BOARD}/RW/ec.RW.elf:     file format elf32-nds32le"
+            "\n"
+            "Disassembly of section .text:\n"
+            "\n"
+            "00000900 <wook_task>:\n"
+            "   ...\n"
+            "00001000 <hook_task>:\n"
+            "   1000:   fc 00\t\tpush25 $r10, #16    ! {$r6~$r10, $fp, $gp, $lp}\n"
+            "   1002:   47 70\t\tmovi55 $r0, #1\n"
+            "   1006:   00 01 5c fc\tbne    $r6, $r0, 2af6a\n"
+            "00002000 <console_task>:\n"
+            "   2000:   fc 00\t\tpush25 $r6, #0    ! {$r6, $fp, $gp, $lp} \n"
+            "   2002:   f0 0e fc c5\tjal   1000 <hook_task>\n"
+            "   2006:   f0 0e bd 3b\tj  53968 <get_program_memory_addr>\n"
+            "   200a:   12 34 56 78\tjral5 $r0\n"
+        )
+
+        addrtoline_mock.return_value = [("??", "??", 0)]
+        self.analyzer.annotation = {
+            "exception_frame_size": 64,
+            "remove": [["fake_func"]],
+        }
+
+        with mock.patch("builtins.print") as print_mock:
+            checkoutput_mock.return_value = disasm_text
+            self.analyzer.Analyze()
+            print_mock.assert_has_calls(
+                [
+                    mock.call(
+                        "Task: HOOKS, Max size: 96 (32 + 64), Allocated size: 2048"
+                    ),
+                    mock.call("Call Trace:"),
+                    mock.call("    hook_task (32) [??:0] 1000"),
+                    mock.call(
+                        "Task: CONSOLE, Max size: 112 (48 + 64), Allocated size: 460"
+                    ),
+                    mock.call("Call Trace:"),
+                    mock.call("    console_task (16) [??:0] 2000"),
+                    mock.call("        -> ??[??:0] 2002"),
+                    mock.call("    hook_task (32) [??:0] 1000"),
+                    mock.call("Unresolved indirect callsites:"),
+                    mock.call("    In function console_task:"),
+                    mock.call("        -> ??[??:0] 200a"),
+                    mock.call("Unresolved annotation signatures:"),
+                    mock.call("    fake_func: function is not found"),
+                ]
+            )
+
+        with self.assertRaisesRegexp(
+            sa.StackAnalyzerError, "Failed to run objdump."
+        ):
+            checkoutput_mock.side_effect = OSError()
+            self.analyzer.Analyze()
+
+        with self.assertRaisesRegexp(
+            sa.StackAnalyzerError, "objdump failed to disassemble."
+        ):
+            checkoutput_mock.side_effect = subprocess.CalledProcessError(1, "")
+            self.analyzer.Analyze()
+
+    @mock.patch("subprocess.check_output")
+    @mock.patch("stack_analyzer.StackAnalyzer.AddressToLine")
+    def testArmAnalyze(self, addrtoline_mock, checkoutput_mock):
+        disasm_text = (
+            "\n"
+            "build/{BOARD}/RW/ec.RW.elf:     file format elf32-littlearm"
+            "\n"
+            "Disassembly of section .text:\n"
+            "\n"
+            "00000900 <wook_task>:\n"
+            "	...\n"
+            "00001000 <hook_task>:\n"
+            "   1000:	b508\t\tpush	{r3, lr}\n"
+            "   1002:	4770\t\tbx	lr\n"
+            "   1006:	00015cfc\t.word	0x00015cfc\n"
+            "00002000 <console_task>:\n"
+            "   2000:	b508\t\tpush	{r3, lr}\n"
+            "   2002:	f00e fcc5\tbl	1000 <hook_task>\n"
+            "   2006:	f00e bd3b\tb.w	53968 <get_program_memory_addr>\n"
+            "   200a:	1234 5678\tb.w  sl\n"
+        )
+
+        addrtoline_mock.return_value = [("??", "??", 0)]
+        self.analyzer.annotation = {
+            "exception_frame_size": 64,
+            "remove": [["fake_func"]],
+        }
+
+        with mock.patch("builtins.print") as print_mock:
+            checkoutput_mock.return_value = disasm_text
+            self.analyzer.Analyze()
+            print_mock.assert_has_calls(
+                [
+                    mock.call(
+                        "Task: HOOKS, Max size: 72 (8 + 64), Allocated size: 2048"
+                    ),
+                    mock.call("Call Trace:"),
+                    mock.call("    hook_task (8) [??:0] 1000"),
+                    mock.call(
+                        "Task: CONSOLE, Max size: 80 (16 + 64), Allocated size: 460"
+                    ),
+                    mock.call("Call Trace:"),
+                    mock.call("    console_task (8) [??:0] 2000"),
+                    mock.call("        -> ??[??:0] 2002"),
+                    mock.call("    hook_task (8) [??:0] 1000"),
+                    mock.call("Unresolved indirect callsites:"),
+                    mock.call("    In function console_task:"),
+                    mock.call("        -> ??[??:0] 200a"),
+                    mock.call("Unresolved annotation signatures:"),
+                    mock.call("    fake_func: function is not found"),
+                ]
+            )
+
+        with self.assertRaisesRegexp(
+            sa.StackAnalyzerError, "Failed to run objdump."
+        ):
+            checkoutput_mock.side_effect = OSError()
+            self.analyzer.Analyze()
+
+        with self.assertRaisesRegexp(
+            sa.StackAnalyzerError, "objdump failed to disassemble."
+        ):
+            checkoutput_mock.side_effect = subprocess.CalledProcessError(1, "")
+            self.analyzer.Analyze()
+
+    @mock.patch("subprocess.check_output")
+    @mock.patch("stack_analyzer.ParseArgs")
+    def testMain(self, parseargs_mock, checkoutput_mock):
+        symbol_text = (
+            "1000 g     F .text  0000015c .hidden hook_task\n"
+            "2000 g     F .text  0000051c .hidden console_task\n"
+        )
+        rodata_text = (
+            "\n"
+            "Contents of section .rodata:\n"
+            " 20000 dead1000 00100000 dead2000 00200000  He..f.He..s.\n"
+        )
+
+        args = mock.MagicMock(
+            elf_path="./ec.RW.elf",
+            export_taskinfo="fake",
+            section="RW",
+            objdump="objdump",
+            addr2line="addr2line",
+            annotation="fake",
+        )
+        parseargs_mock.return_value = args
+
+        with mock.patch("os.path.exists") as path_mock:
+            path_mock.return_value = False
+            with mock.patch("builtins.print") as print_mock:
+                with mock.patch("builtins.open", mock.mock_open()) as open_mock:
+                    sa.main()
+                    print_mock.assert_any_call(
+                        "Warning: Annotation file fake does not exist."
+                    )
+
+        with mock.patch("os.path.exists") as path_mock:
+            path_mock.return_value = True
+            with mock.patch("builtins.print") as print_mock:
+                with mock.patch("builtins.open", mock.mock_open()) as open_mock:
+                    open_mock.side_effect = IOError()
+                    sa.main()
+                    print_mock.assert_called_once_with(
+                        "Error: Failed to open annotation file fake."
+                    )
+
+            with mock.patch("builtins.print") as print_mock:
+                with mock.patch("builtins.open", mock.mock_open()) as open_mock:
+                    open_mock.return_value.read.side_effect = ["{", ""]
+                    sa.main()
+                    open_mock.assert_called_once_with("fake", "r")
+                    print_mock.assert_called_once_with(
+                        "Error: Failed to parse annotation file fake."
+                    )
+
+            with mock.patch("builtins.print") as print_mock:
+                with mock.patch(
+                    "builtins.open", mock.mock_open(read_data="")
+                ) as open_mock:
+                    sa.main()
+                    print_mock.assert_called_once_with(
+                        "Error: Invalid annotation file fake."
+                    )
+
+        args.annotation = None
+
+        with mock.patch("builtins.print") as print_mock:
+            checkoutput_mock.side_effect = [symbol_text, rodata_text]
+            sa.main()
+            print_mock.assert_called_once_with(
+                "Error: Failed to load export_taskinfo."
+            )
+
+        with mock.patch("builtins.print") as print_mock:
+            checkoutput_mock.side_effect = subprocess.CalledProcessError(1, "")
+            sa.main()
+            print_mock.assert_called_once_with(
+                "Error: objdump failed to dump symbol table or rodata."
+            )
+
+        with mock.patch("builtins.print") as print_mock:
+            checkoutput_mock.side_effect = OSError()
+            sa.main()
+            print_mock.assert_called_once_with("Error: Failed to run objdump.")
+
+
+if __name__ == "__main__":
+    unittest.main()
diff --git a/extra/tigertool/README.md b/extra/tigertool/README.md
index e808536e7b..407a58a751 100644
--- a/extra/tigertool/README.md
+++ b/extra/tigertool/README.md
@@ -1,18 +1,28 @@
 # tigertool
 
-tigertool.py is a commandline utility to control the tigertail USB-C mux.
-It supports changing the mux status to port A, B, or off.
-You can set a serial number to use multiple tigertails at once.
+tigertool.py is a commandline utility to control the tigertail USB-C mux. It
+supports changing the mux status to port A, B, or off. You can set a serial
+number to use multiple tigertails at once.
 
 ## Usage
-Typical usage to set the mux port<br>
-```./tigertail.py -m [A|B|off] -s [serialno]```<br>
+
+Typical usage to set the mux port
+
+```
+./tigertail.py -m [A|B|off] -s [serialno]
+```
 
 Reboot the tigertail<br>
-```./tigertail.py --reboot```<br>
 
-Set the serial number, when only one tigertail is plugged<br>
-```./tigertail.py --setserialno=[serialno]```<br>
+```
+./tigertail.py --reboot
+```
+
+Set the serial number, when only one tigertail is plugged
+
+```
+./tigertail.py --setserialno=[serialno]
+```
 
-Tigertail can support up to 20V 3A on the mux and passes through all
-USB-C lines except SBU.
+Tigertail can support up to 20V 3A on the mux and passes through all USB-C lines
+except SBU.
diff --git a/extra/tigertool/ecusb/__init__.py b/extra/tigertool/ecusb/__init__.py
index c2af553d57..9451551f37 100644
--- a/extra/tigertool/ecusb/__init__.py
+++ b/extra/tigertool/ecusb/__init__.py
@@ -1,5 +1,5 @@
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
-__all__ = ['tiny_servo_common', 'stm32usb', 'stm32uart', 'pty_driver']
+__all__ = ["tiny_servo_common", "stm32usb", "stm32uart", "pty_driver"]
diff --git a/extra/tigertool/ecusb/pty_driver.py b/extra/tigertool/ecusb/pty_driver.py
index 63df230e7e..da9ed4ab25 100644
--- a/extra/tigertool/ecusb/pty_driver.py
+++ b/extra/tigertool/ecusb/pty_driver.py
@@ -1,4 +1,4 @@
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -13,282 +13,303 @@
 import errno
 import fcntl
 import os
-import pexpect
-from pexpect import fdpexpect
+import time
+
+import pexpect  # pylint:disable=import-error
+from pexpect import fdpexpect  # pylint:disable=import-error
+
 
 # Expecting a result in 3 seconds is plenty even for slow platforms.
 DEFAULT_UART_TIMEOUT = 3
+FLUSH_UART_TIMEOUT = 1
 
 
 class ptyError(Exception):
-  """Exception class for pty errors."""
+    """Exception class for pty errors."""
 
 
 UART_PARAMS = {
-    'uart_cmd': None,
-    'uart_multicmd': None,
-    'uart_regexp': None,
-    'uart_timeout': DEFAULT_UART_TIMEOUT,
+    "uart_cmd": None,
+    "uart_multicmd": None,
+    "uart_regexp": None,
+    "uart_timeout": DEFAULT_UART_TIMEOUT,
 }
 
 
 class ptyDriver(object):
-  """Automate interactive commands on a pty interface."""
-  def __init__(self, interface, params, fast=False):
-    """Init class variables."""
-    self._child = None
-    self._fd = None
-    self._interface = interface
-    self._pty_path = self._interface.get_pty()
-    self._dict = UART_PARAMS.copy()
-    self._fast = fast
-
-  def __del__(self):
-    self.close()
-
-  def close(self):
-    """Close any open files and interfaces."""
-    if self._fd:
-      self._close()
-    self._interface.close()
-
-  def _open(self):
-    """Connect to serial device and create pexpect interface."""
-    assert self._fd is None
-    self._fd = os.open(self._pty_path, os.O_RDWR | os.O_NONBLOCK)
-    # Don't allow forked processes to access.
-    fcntl.fcntl(self._fd, fcntl.F_SETFD,
-                fcntl.fcntl(self._fd, fcntl.F_GETFD) | fcntl.FD_CLOEXEC)
-    self._child = fdpexpect.fdspawn(self._fd)
-    # pexpect defaults to a 100ms delay before sending characters, to
-    # work around race conditions in ssh. We don't need this feature
-    # so we'll change delaybeforesend from 0.1 to 0.001 to speed things up.
-    if self._fast:
-      self._child.delaybeforesend = 0.001
-
-  def _close(self):
-    """Close serial device connection."""
-    os.close(self._fd)
-    self._fd = None
-    self._child = None
-
-  def _flush(self):
-    """Flush device output to prevent previous messages interfering."""
-    if self._child.sendline('') != 1:
-      raise ptyError('Failed to send newline.')
-    while True:
-      try:
-        self._child.expect('.', timeout=0.2)
-      except (pexpect.TIMEOUT, pexpect.EOF):
-        break
-      except OSError as e:
-        # EAGAIN indicates no data available, maybe we didn't wait long enough.
-        if e.errno != errno.EAGAIN:
-          raise
-        break
-
-  def _send(self, cmds):
-    """Send command to EC.
-
-    This function always flushes serial device before sending, and is used as
-    a wrapper function to make sure the channel is always flushed before
-    sending commands.
-
-    Args:
-      cmds: The commands to send to the device, either a list or a string.
-
-    Raises:
-      ptyError: Raised when writing to the device fails.
-    """
-    self._flush()
-    if not isinstance(cmds, list):
-      cmds = [cmds]
-    for cmd in cmds:
-      if self._child.sendline(cmd) != len(cmd) + 1:
-        raise ptyError('Failed to send command.')
-
-  def _issue_cmd(self, cmds):
-    """Send command to the device and do not wait for response.
-
-    Args:
-      cmds: The commands to send to the device, either a list or a string.
-    """
-    self._issue_cmd_get_results(cmds, [])
-
-  def _issue_cmd_get_results(self, cmds,
-                             regex_list, timeout=DEFAULT_UART_TIMEOUT):
-    """Send command to the device and wait for response.
-
-    This function waits for response message matching a regular
-    expressions.
-
-    Args:
-      cmds: The commands issued, either a list or a string.
-      regex_list: List of Regular expressions used to match response message.
-        Note1, list must be ordered.
-        Note2, empty list sends and returns.
-      timeout: time to wait for matching results before failing.
-
-    Returns:
-      List of tuples, each of which contains the entire matched string and
-      all the subgroups of the match. None if not matched.
-      For example:
-        response of the given command:
-          High temp: 37.2
-          Low temp: 36.4
-        regex_list:
-          ['High temp: (\d+)\.(\d+)', 'Low temp: (\d+)\.(\d+)']
-        returns:
-          [('High temp: 37.2', '37', '2'), ('Low temp: 36.4', '36', '4')]
-
-    Raises:
-      ptyError: If timed out waiting for a response
-    """
-    result_list = []
-    self._open()
-    try:
-      self._send(cmds)
-      for regex in regex_list:
-        self._child.expect(regex, timeout)
-        match = self._child.match
-        lastindex = match.lastindex if match and match.lastindex else 0
-        # Create a tuple which contains the entire matched string and all
-        # the subgroups of the match.
-        result = match.group(*range(lastindex + 1)) if match else None
-        if result:
-          result = tuple(res.decode('utf-8') for res in result)
-        result_list.append(result)
-    except pexpect.TIMEOUT:
-      raise ptyError('Timeout waiting for response.')
-    finally:
-      self._close()
-    return result_list
-
-  def _issue_cmd_get_multi_results(self, cmd, regex):
-    """Send command to the device and wait for multiple response.
-
-    This function waits for arbitrary number of response message
-    matching a regular expression.
-
-    Args:
-      cmd: The command issued.
-      regex: Regular expression used to match response message.
-
-    Returns:
-      List of tuples, each of which contains the entire matched string and
-      all the subgroups of the match. None if not matched.
-    """
-    result_list = []
-    self._open()
-    try:
-      self._send(cmd)
-      while True:
+    """Automate interactive commands on a pty interface."""
+
+    def __init__(self, interface, params, fast=False):
+        """Init class variables."""
+        self._child = None
+        self._fd = None
+        self._interface = interface
+        self._pty_path = self._interface.get_pty()
+        self._dict = UART_PARAMS.copy()
+        self._fast = fast
+
+    def __del__(self):
+        self.close()
+
+    def close(self):
+        """Close any open files and interfaces."""
+        if self._fd:
+            self._close()
+        self._interface.close()
+
+    def _open(self):
+        """Connect to serial device and create pexpect interface."""
+        assert self._fd is None
+        self._fd = os.open(self._pty_path, os.O_RDWR | os.O_NONBLOCK)
+        # Don't allow forked processes to access.
+        fcntl.fcntl(
+            self._fd,
+            fcntl.F_SETFD,
+            fcntl.fcntl(self._fd, fcntl.F_GETFD) | fcntl.FD_CLOEXEC,
+        )
+        self._child = fdpexpect.fdspawn(self._fd)
+        # pexpect defaults to a 100ms delay before sending characters, to
+        # work around race conditions in ssh. We don't need this feature
+        # so we'll change delaybeforesend from 0.1 to 0.001 to speed things up.
+        if self._fast:
+            self._child.delaybeforesend = 0.001
+
+    def _close(self):
+        """Close serial device connection."""
+        os.close(self._fd)
+        self._fd = None
+        self._child = None
+
+    def _flush(self):
+        """Flush device output to prevent previous messages interfering."""
+        if self._child.sendline("") != 1:
+            raise ptyError("Failed to send newline.")
+        # Have a maximum timeout for the flush operation. We should have cleared
+        # all data from the buffer, but if data is regularly being generated, we
+        # can't guarantee it will ever stop.
+        flush_end_time = time.time() + FLUSH_UART_TIMEOUT
+        while time.time() <= flush_end_time:
+            try:
+                self._child.expect(".", timeout=0.01)
+            except (pexpect.TIMEOUT, pexpect.EOF):
+                break
+            except OSError as e:
+                # EAGAIN indicates no data available, maybe we didn't wait long enough.
+                if e.errno != errno.EAGAIN:
+                    raise
+                break
+
+    def _send(self, cmds):
+        """Send command to EC.
+
+        This function always flushes serial device before sending, and is used as
+        a wrapper function to make sure the channel is always flushed before
+        sending commands.
+
+        Args:
+          cmds: The commands to send to the device, either a list or a string.
+
+        Raises:
+          ptyError: Raised when writing to the device fails.
+        """
+        self._flush()
+        if not isinstance(cmds, list):
+            cmds = [cmds]
+        for cmd in cmds:
+            if self._child.sendline(cmd) != len(cmd) + 1:
+                raise ptyError("Failed to send command.")
+
+    def _issue_cmd(self, cmds):
+        """Send command to the device and do not wait for response.
+
+        Args:
+          cmds: The commands to send to the device, either a list or a string.
+        """
+        self._issue_cmd_get_results(cmds, [])
+
+    def _issue_cmd_get_results(
+        self, cmds, regex_list, timeout=DEFAULT_UART_TIMEOUT
+    ):
+        """Send command to the device and wait for response.
+
+        This function waits for response message matching a regular
+        expressions.
+
+        Args:
+          cmds: The commands issued, either a list or a string.
+          regex_list: List of Regular expressions used to match response message.
+            Note1, list must be ordered.
+            Note2, empty list sends and returns.
+          timeout: time to wait for matching results before failing.
+
+        Returns:
+          List of tuples, each of which contains the entire matched string and
+          all the subgroups of the match. None if not matched.
+          For example:
+            response of the given command:
+              High temp: 37.2
+              Low temp: 36.4
+            regex_list:
+              ['High temp: (\d+)\.(\d+)', 'Low temp: (\d+)\.(\d+)']
+            returns:
+              [('High temp: 37.2', '37', '2'), ('Low temp: 36.4', '36', '4')]
+
+        Raises:
+          ptyError: If timed out waiting for a response
+        """
+        result_list = []
+        self._open()
         try:
-          self._child.expect(regex, timeout=0.1)
-          match = self._child.match
-          lastindex = match.lastindex if match and match.lastindex else 0
-          # Create a tuple which contains the entire matched string and all
-          # the subgroups of the match.
-          result = match.group(*range(lastindex + 1)) if match else None
-          if result:
-            result = tuple(res.decode('utf-8') for res in result)
-          result_list.append(result)
+            self._send(cmds)
+            for regex in regex_list:
+                self._child.expect(regex, timeout)
+                match = self._child.match
+                lastindex = match.lastindex if match and match.lastindex else 0
+                # Create a tuple which contains the entire matched string and all
+                # the subgroups of the match.
+                result = match.group(*range(lastindex + 1)) if match else None
+                if result:
+                    result = tuple(res.decode("utf-8") for res in result)
+                result_list.append(result)
         except pexpect.TIMEOUT:
-          break
-    finally:
-      self._close()
-    return result_list
-
-  def _Set_uart_timeout(self, timeout):
-    """Set timeout value for waiting for the device response.
-
-    Args:
-      timeout: Timeout value in second.
-    """
-    self._dict['uart_timeout'] = timeout
-
-  def _Get_uart_timeout(self):
-    """Get timeout value for waiting for the device response.
-
-    Returns:
-      Timeout value in second.
-    """
-    return self._dict['uart_timeout']
-
-  def _Set_uart_regexp(self, regexp):
-    """Set the list of regular expressions which matches the command response.
-
-    Args:
-      regexp: A string which contains a list of regular expressions.
-    """
-    if not isinstance(regexp, str):
-      raise ptyError('The argument regexp should be a string.')
-    self._dict['uart_regexp'] = ast.literal_eval(regexp)
-
-  def _Get_uart_regexp(self):
-    """Get the list of regular expressions which matches the command response.
-
-    Returns:
-      A string which contains a list of regular expressions.
-    """
-    return str(self._dict['uart_regexp'])
-
-  def _Set_uart_cmd(self, cmd):
-    """Set the UART command and send it to the device.
-
-    If ec_uart_regexp is 'None', the command is just sent and it doesn't care
-    about its response.
-
-    If ec_uart_regexp is not 'None', the command is send and its response,
-    which matches the regular expression of ec_uart_regexp, will be kept.
-    Use its getter to obtain this result. If no match after ec_uart_timeout
-    seconds, a timeout error will be raised.
-
-    Args:
-      cmd: A string of UART command.
-    """
-    if self._dict['uart_regexp']:
-      self._dict['uart_cmd'] = self._issue_cmd_get_results(
-          cmd, self._dict['uart_regexp'], self._dict['uart_timeout'])
-    else:
-      self._dict['uart_cmd'] = None
-      self._issue_cmd(cmd)
-
-  def _Set_uart_multicmd(self, cmds):
-    """Set multiple UART commands and send them to the device.
-
-    Note that ec_uart_regexp is not supported to match the results.
-
-    Args:
-      cmds: A semicolon-separated string of UART commands.
-    """
-    self._issue_cmd(cmds.split(';'))
-
-  def _Get_uart_cmd(self):
-    """Get the result of the latest UART command.
-
-    Returns:
-      A string which contains a list of tuples, each of which contains the
-      entire matched string and all the subgroups of the match. 'None' if
-      the ec_uart_regexp is 'None'.
-    """
-    return str(self._dict['uart_cmd'])
-
-  def _Set_uart_capture(self, cmd):
-    """Set UART capture mode (on or off).
-
-    Once capture is enabled, UART output could be collected periodically by
-    invoking _Get_uart_stream() below.
-
-    Args:
-      cmd: True for on, False for off
-    """
-    self._interface.set_capture_active(cmd)
-
-  def _Get_uart_capture(self):
-    """Get the UART capture mode (on or off)."""
-    return self._interface.get_capture_active()
-
-  def _Get_uart_stream(self):
-    """Get uart stream generated since last time."""
-    return self._interface.get_stream()
+            raise ptyError("Timeout waiting for response.")
+        finally:
+            if not regex_list:
+                # Must be longer than delaybeforesend
+                time.sleep(0.1)
+            self._close()
+        return result_list
+
+    def _issue_cmd_get_multi_results(self, cmd, regex):
+        """Send command to the device and wait for multiple response.
+
+        This function waits for arbitrary number of response message
+        matching a regular expression.
+
+        Args:
+          cmd: The command issued.
+          regex: Regular expression used to match response message.
+
+        Returns:
+          List of tuples, each of which contains the entire matched string and
+          all the subgroups of the match. None if not matched.
+        """
+        result_list = []
+        self._open()
+        try:
+            self._send(cmd)
+            while True:
+                try:
+                    self._child.expect(regex, timeout=0.1)
+                    match = self._child.match
+                    lastindex = (
+                        match.lastindex if match and match.lastindex else 0
+                    )
+                    # Create a tuple which contains the entire matched string and all
+                    # the subgroups of the match.
+                    result = (
+                        match.group(*range(lastindex + 1)) if match else None
+                    )
+                    if result:
+                        result = tuple(res.decode("utf-8") for res in result)
+                    result_list.append(result)
+                except pexpect.TIMEOUT:
+                    break
+        finally:
+            self._close()
+        return result_list
+
+    def _Set_uart_timeout(self, timeout):
+        """Set timeout value for waiting for the device response.
+
+        Args:
+          timeout: Timeout value in second.
+        """
+        self._dict["uart_timeout"] = timeout
+
+    def _Get_uart_timeout(self):
+        """Get timeout value for waiting for the device response.
+
+        Returns:
+          Timeout value in second.
+        """
+        return self._dict["uart_timeout"]
+
+    def _Set_uart_regexp(self, regexp):
+        """Set the list of regular expressions which matches the command response.
+
+        Args:
+          regexp: A string which contains a list of regular expressions.
+        """
+        if not isinstance(regexp, str):
+            raise ptyError("The argument regexp should be a string.")
+        self._dict["uart_regexp"] = ast.literal_eval(regexp)
+
+    def _Get_uart_regexp(self):
+        """Get the list of regular expressions which matches the command response.
+
+        Returns:
+          A string which contains a list of regular expressions.
+        """
+        return str(self._dict["uart_regexp"])
+
+    def _Set_uart_cmd(self, cmd):
+        """Set the UART command and send it to the device.
+
+        If ec_uart_regexp is 'None', the command is just sent and it doesn't care
+        about its response.
+
+        If ec_uart_regexp is not 'None', the command is send and its response,
+        which matches the regular expression of ec_uart_regexp, will be kept.
+        Use its getter to obtain this result. If no match after ec_uart_timeout
+        seconds, a timeout error will be raised.
+
+        Args:
+          cmd: A string of UART command.
+        """
+        if self._dict["uart_regexp"]:
+            self._dict["uart_cmd"] = self._issue_cmd_get_results(
+                cmd, self._dict["uart_regexp"], self._dict["uart_timeout"]
+            )
+        else:
+            self._dict["uart_cmd"] = None
+            self._issue_cmd(cmd)
+
+    def _Set_uart_multicmd(self, cmds):
+        """Set multiple UART commands and send them to the device.
+
+        Note that ec_uart_regexp is not supported to match the results.
+
+        Args:
+          cmds: A semicolon-separated string of UART commands.
+        """
+        self._issue_cmd(cmds.split(";"))
+
+    def _Get_uart_cmd(self):
+        """Get the result of the latest UART command.
+
+        Returns:
+          A string which contains a list of tuples, each of which contains the
+          entire matched string and all the subgroups of the match. 'None' if
+          the ec_uart_regexp is 'None'.
+        """
+        return str(self._dict["uart_cmd"])
+
+    def _Set_uart_capture(self, cmd):
+        """Set UART capture mode (on or off).
+
+        Once capture is enabled, UART output could be collected periodically by
+        invoking _Get_uart_stream() below.
+
+        Args:
+          cmd: True for on, False for off
+        """
+        self._interface.set_capture_active(cmd)
+
+    def _Get_uart_capture(self):
+        """Get the UART capture mode (on or off)."""
+        return self._interface.get_capture_active()
+
+    def _Get_uart_stream(self):
+        """Get uart stream generated since last time."""
+        return self._interface.get_stream()
diff --git a/extra/tigertool/ecusb/stm32uart.py b/extra/tigertool/ecusb/stm32uart.py
index cfbbf485a4..64d0234f06 100644
--- a/extra/tigertool/ecusb/stm32uart.py
+++ b/extra/tigertool/ecusb/stm32uart.py
@@ -1,4 +1,4 @@
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -13,229 +13,247 @@
 import threading
 import time
 import tty
-import usb
+
+import usb  # pylint:disable=import-error
 
 from . import stm32usb
 
 
 class SuartError(Exception):
-  """Class for exceptions of Suart."""
-  def __init__(self, msg, value=0):
-    """SuartError constructor.
+    """Class for exceptions of Suart."""
 
-    Args:
-      msg: string, message describing error in detail
-      value: integer, value of error when non-zero status returned.  Default=0
-    """
-    super(SuartError, self).__init__(msg, value)
-    self.msg = msg
-    self.value = value
+    def __init__(self, msg, value=0):
+        """SuartError constructor.
 
+        Args:
+          msg: string, message describing error in detail
+          value: integer, value of error when non-zero status returned.  Default=0
+        """
+        super(SuartError, self).__init__(msg, value)
+        self.msg = msg
+        self.value = value
 
-class Suart(object):
-  """Provide interface to stm32 serial usb endpoint."""
-  def __init__(self, vendor=0x18d1, product=0x501a, interface=0,
-               serialname=None, debuglog=False):
-    """Suart contstructor.
-
-    Initializes stm32 USB stream interface.
-
-    Args:
-      vendor: usb vendor id of stm32 device
-      product: usb product id of stm32 device
-      interface: interface number of stm32 device to use
-      serialname: serial name to target. Defaults to None.
-      debuglog: chatty output. Defaults to False.
-
-    Raises:
-      SuartError: If init fails
-    """
-    self._ptym = None
-    self._ptys = None
-    self._ptyname = None
-    self._rx_thread = None
-    self._tx_thread = None
-    self._debuglog = debuglog
-    self._susb = stm32usb.Susb(vendor=vendor, product=product,
-                               interface=interface, serialname=serialname)
-    self._running = False
-
-  def __del__(self):
-    """Suart destructor."""
-    self.close()
-
-  def close(self):
-    """Stop all running threads."""
-    self._running = False
-    if self._rx_thread:
-      self._rx_thread.join(2)
-      self._rx_thread = None
-    if self._tx_thread:
-      self._tx_thread.join(2)
-      self._tx_thread = None
-    self._susb.close()
-
-  def run_rx_thread(self):
-    """Background loop to pass data from USB to pty."""
-    ep = select.epoll()
-    ep.register(self._ptym, select.EPOLLHUP)
-    try:
-      while self._running:
-        events = ep.poll(0)
-        # Check if the pty is connected to anything, or hungup.
-        if not events:
-          try:
-            r = self._susb._read_ep.read(64, self._susb.TIMEOUT_MS)
-            if r:
-              if self._debuglog:
-                print(''.join([chr(x) for x in r]), end='')
-              os.write(self._ptym, r)
-
-          # If we miss some characters on pty disconnect, that's fine.
-          # ep.read() also throws USBError on timeout, which we discard.
-          except OSError:
-            pass
-          except usb.core.USBError:
-            pass
-        else:
-          time.sleep(.1)
-    except Exception as e:
-      raise e
-
-  def run_tx_thread(self):
-    """Background loop to pass data from pty to USB."""
-    ep = select.epoll()
-    ep.register(self._ptym, select.EPOLLHUP)
-    try:
-      while self._running:
-        events = ep.poll(0)
-        # Check if the pty is connected to anything, or hungup.
-        if not events:
-          try:
-            r = os.read(self._ptym, 64)
-            if r:
-              self._susb._write_ep.write(r, self._susb.TIMEOUT_MS)
-
-          except OSError:
-            pass
-          except usb.core.USBError:
-            pass
-        else:
-          time.sleep(.1)
-    except Exception as e:
-      raise e
-
-  def run(self):
-    """Creates pthreads to poll stm32 & PTY for data."""
-    m, s = os.openpty()
-    self._ptyname = os.ttyname(s)
-
-    self._ptym = m
-    self._ptys = s
-
-    os.fchmod(s, 0o660)
-
-    # Change the owner and group of the PTY to the user who started servod.
-    try:
-      uid = int(os.environ.get('SUDO_UID', -1))
-    except TypeError:
-      uid = -1
 
-    try:
-      gid = int(os.environ.get('SUDO_GID', -1))
-    except TypeError:
-      gid = -1
-    os.fchown(s, uid, gid)
-
-    tty.setraw(self._ptym, termios.TCSADRAIN)
-
-    # Generate a HUP flag on pty slave fd.
-    os.fdopen(s).close()
-
-    self._running = True
-
-    self._rx_thread = threading.Thread(target=self.run_rx_thread, args=[])
-    self._rx_thread.daemon = True
-    self._rx_thread.start()
-
-    self._tx_thread = threading.Thread(target=self.run_tx_thread, args=[])
-    self._tx_thread.daemon = True
-    self._tx_thread.start()
-
-  def get_uart_props(self):
-    """Get the uart's properties.
-
-    Returns:
-      dict where:
-        baudrate: integer of uarts baudrate
-        bits: integer, number of bits of data Can be 5|6|7|8 inclusive
-        parity: integer, parity of 0-2 inclusive where:
-          0: no parity
-          1: odd parity
-          2: even parity
-        sbits: integer, number of stop bits.  Can be 0|1|2 inclusive where:
-          0: 1 stop bit
-          1: 1.5 stop bits
-          2: 2 stop bits
-    """
-    return {
-        'baudrate': 115200,
-        'bits': 8,
-        'parity': 0,
-        'sbits': 1,
-    }
-
-  def set_uart_props(self, line_props):
-    """Set the uart's properties.
-
-    Note that Suart cannot set properties
-    and will fail if the properties are not the default 115200,8n1.
-
-    Args:
-      line_props: dict where:
-        baudrate: integer of uarts baudrate
-        bits: integer, number of bits of data ( prior to stop bit)
-        parity: integer, parity of 0-2 inclusive where
-          0: no parity
-          1: odd parity
-          2: even parity
-        sbits: integer, number of stop bits.  Can be 0|1|2 inclusive where:
-          0: 1 stop bit
-          1: 1.5 stop bits
-          2: 2 stop bits
-
-    Raises:
-      SuartError: If requested line properties are not the default.
-    """
-    curr_props = self.get_uart_props()
-    for prop in line_props:
-      if line_props[prop] != curr_props[prop]:
-        raise SuartError('Line property %s cannot be set from %s to %s' % (
-            prop, curr_props[prop], line_props[prop]))
-    return True
-
-  def get_pty(self):
-    """Gets path to pty for communication to/from uart.
-
-    Returns:
-      String path to the pty connected to the uart
-    """
-    return self._ptyname
+class Suart(object):
+    """Provide interface to stm32 serial usb endpoint."""
+
+    def __init__(
+        self,
+        vendor=0x18D1,
+        product=0x501A,
+        interface=0,
+        serialname=None,
+        debuglog=False,
+    ):
+        """Suart contstructor.
+
+        Initializes stm32 USB stream interface.
+
+        Args:
+          vendor: usb vendor id of stm32 device
+          product: usb product id of stm32 device
+          interface: interface number of stm32 device to use
+          serialname: serial name to target. Defaults to None.
+          debuglog: chatty output. Defaults to False.
+
+        Raises:
+          SuartError: If init fails
+        """
+        self._ptym = None
+        self._ptys = None
+        self._ptyname = None
+        self._rx_thread = None
+        self._tx_thread = None
+        self._debuglog = debuglog
+        self._susb = stm32usb.Susb(
+            vendor=vendor,
+            product=product,
+            interface=interface,
+            serialname=serialname,
+        )
+        self._running = False
+
+    def __del__(self):
+        """Suart destructor."""
+        self.close()
+
+    def close(self):
+        """Stop all running threads."""
+        self._running = False
+        if self._rx_thread:
+            self._rx_thread.join(2)
+            self._rx_thread = None
+        if self._tx_thread:
+            self._tx_thread.join(2)
+            self._tx_thread = None
+        self._susb.close()
+
+    def run_rx_thread(self):
+        """Background loop to pass data from USB to pty."""
+        ep = select.epoll()
+        ep.register(self._ptym, select.EPOLLHUP)
+        try:
+            while self._running:
+                events = ep.poll(0)
+                # Check if the pty is connected to anything, or hungup.
+                if not events:
+                    try:
+                        r = self._susb._read_ep.read(64, self._susb.TIMEOUT_MS)
+                        if r:
+                            if self._debuglog:
+                                print("".join([chr(x) for x in r]), end="")
+                            os.write(self._ptym, r)
+
+                    # If we miss some characters on pty disconnect, that's fine.
+                    # ep.read() also throws USBError on timeout, which we discard.
+                    except OSError:
+                        pass
+                    except usb.core.USBError:
+                        pass
+                else:
+                    time.sleep(0.1)
+        except Exception as e:
+            raise e
+
+    def run_tx_thread(self):
+        """Background loop to pass data from pty to USB."""
+        ep = select.epoll()
+        ep.register(self._ptym, select.EPOLLHUP)
+        try:
+            while self._running:
+                events = ep.poll(0)
+                # Check if the pty is connected to anything, or hungup.
+                if not events:
+                    try:
+                        r = os.read(self._ptym, 64)
+                        # TODO(crosbug.com/936182): Remove when the servo v4/micro console
+                        # issues are fixed.
+                        time.sleep(0.001)
+                        if r:
+                            self._susb._write_ep.write(r, self._susb.TIMEOUT_MS)
+
+                    except OSError:
+                        pass
+                    except usb.core.USBError:
+                        pass
+                else:
+                    time.sleep(0.1)
+        except Exception as e:
+            raise e
+
+    def run(self):
+        """Creates pthreads to poll stm32 & PTY for data."""
+        m, s = os.openpty()
+        self._ptyname = os.ttyname(s)
+
+        self._ptym = m
+        self._ptys = s
+
+        os.fchmod(s, 0o660)
+
+        # Change the owner and group of the PTY to the user who started servod.
+        try:
+            uid = int(os.environ.get("SUDO_UID", -1))
+        except TypeError:
+            uid = -1
+
+        try:
+            gid = int(os.environ.get("SUDO_GID", -1))
+        except TypeError:
+            gid = -1
+        os.fchown(s, uid, gid)
+
+        tty.setraw(self._ptym, termios.TCSADRAIN)
+
+        # Generate a HUP flag on pty slave fd.
+        os.fdopen(s).close()
+
+        self._running = True
+
+        self._rx_thread = threading.Thread(target=self.run_rx_thread, args=[])
+        self._rx_thread.daemon = True
+        self._rx_thread.start()
+
+        self._tx_thread = threading.Thread(target=self.run_tx_thread, args=[])
+        self._tx_thread.daemon = True
+        self._tx_thread.start()
+
+    def get_uart_props(self):
+        """Get the uart's properties.
+
+        Returns:
+          dict where:
+            baudrate: integer of uarts baudrate
+            bits: integer, number of bits of data Can be 5|6|7|8 inclusive
+            parity: integer, parity of 0-2 inclusive where:
+              0: no parity
+              1: odd parity
+              2: even parity
+            sbits: integer, number of stop bits.  Can be 0|1|2 inclusive where:
+              0: 1 stop bit
+              1: 1.5 stop bits
+              2: 2 stop bits
+        """
+        return {
+            "baudrate": 115200,
+            "bits": 8,
+            "parity": 0,
+            "sbits": 1,
+        }
+
+    def set_uart_props(self, line_props):
+        """Set the uart's properties.
+
+        Note that Suart cannot set properties
+        and will fail if the properties are not the default 115200,8n1.
+
+        Args:
+          line_props: dict where:
+            baudrate: integer of uarts baudrate
+            bits: integer, number of bits of data ( prior to stop bit)
+            parity: integer, parity of 0-2 inclusive where
+              0: no parity
+              1: odd parity
+              2: even parity
+            sbits: integer, number of stop bits.  Can be 0|1|2 inclusive where:
+              0: 1 stop bit
+              1: 1.5 stop bits
+              2: 2 stop bits
+
+        Raises:
+          SuartError: If requested line properties are not the default.
+        """
+        curr_props = self.get_uart_props()
+        for prop in line_props:
+            if line_props[prop] != curr_props[prop]:
+                raise SuartError(
+                    "Line property %s cannot be set from %s to %s"
+                    % (prop, curr_props[prop], line_props[prop])
+                )
+        return True
+
+    def get_pty(self):
+        """Gets path to pty for communication to/from uart.
+
+        Returns:
+          String path to the pty connected to the uart
+        """
+        return self._ptyname
 
 
 def main():
-  """Run a suart test with the default parameters."""
-  try:
-    sobj = Suart()
-    sobj.run()
+    """Run a suart test with the default parameters."""
+    try:
+        sobj = Suart()
+        sobj.run()
 
-    # run() is a thread so just busy wait to mimic server.
-    while True:
-      # Ours sleeps to eleven!
-      time.sleep(11)
-  except KeyboardInterrupt:
-    sys.exit(0)
+        # run() is a thread so just busy wait to mimic server.
+        while True:
+            # Ours sleeps to eleven!
+            time.sleep(11)
+    except KeyboardInterrupt:
+        sys.exit(0)
 
 
-if __name__ == '__main__':
-  main()
+if __name__ == "__main__":
+    main()
diff --git a/extra/tigertool/ecusb/stm32usb.py b/extra/tigertool/ecusb/stm32usb.py
index 875251329f..f9c700466a 100644
--- a/extra/tigertool/ecusb/stm32usb.py
+++ b/extra/tigertool/ecusb/stm32usb.py
@@ -1,115 +1,132 @@
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 """Allows creation of an interface via stm32 usb."""
 
-import usb
+import usb  # pylint:disable=import-error
 
 
 class SusbError(Exception):
-  """Class for exceptions of Susb."""
-  def __init__(self, msg, value=0):
-    """SusbError constructor.
+    """Class for exceptions of Susb."""
 
-    Args:
-      msg: string, message describing error in detail
-      value: integer, value of error when non-zero status returned.  Default=0
-    """
-    super(SusbError, self).__init__(msg, value)
-    self.msg = msg
-    self.value = value
+    def __init__(self, msg, value=0):
+        """SusbError constructor.
+
+        Args:
+          msg: string, message describing error in detail
+          value: integer, value of error when non-zero status returned.  Default=0
+        """
+        super(SusbError, self).__init__(msg, value)
+        self.msg = msg
+        self.value = value
 
 
 class Susb(object):
-  """Provide stm32 USB functionality.
-
-  Instance Variables:
-    _read_ep: pyUSB read endpoint for this interface
-    _write_ep: pyUSB write endpoint for this interface
-  """
-  READ_ENDPOINT = 0x81
-  WRITE_ENDPOINT = 0x1
-  TIMEOUT_MS = 100
-
-  def __init__(self, vendor=0x18d1,
-               product=0x5027, interface=1, serialname=None, logger=None):
-    """Susb constructor.
-
-    Discovers and connects to stm32 USB endpoints.
-
-    Args:
-      vendor: usb vendor id of stm32 device.
-      product: usb product id of stm32 device.
-      interface: interface number ( 1 - 4 ) of stm32 device to use.
-      serialname: string of device serialname.
-      logger: none
-
-    Raises:
-      SusbError: An error accessing Susb object
+    """Provide stm32 USB functionality.
+
+    Instance Variables:
+      _read_ep: pyUSB read endpoint for this interface
+      _write_ep: pyUSB write endpoint for this interface
     """
-    self._vendor = vendor
-    self._product = product
-    self._interface = interface
-    self._serialname = serialname
-    self._find_device()
-
-  def _find_device(self):
-    """Set up the usb endpoint"""
-    # Find the stm32.
-    dev_g = usb.core.find(idVendor=self._vendor, idProduct=self._product,
-                             find_all=True)
-    dev_list = list(dev_g)
-
-    if not dev_list:
-      raise SusbError('USB device not found')
-
-    # Check if we have multiple stm32s and we've specified the serial.
-    dev = None
-    if self._serialname:
-      for d in dev_list:
-        dev_serial = usb.util.get_string(d, d.iSerialNumber)
-        if dev_serial == self._serialname:
-          dev = d
-          break
-      if dev is None:
-        raise SusbError('USB device(%s) not found' % self._serialname)
-    else:
-      try:
-        dev = dev_list[0]
-      except StopIteration:
-        raise SusbError('USB device %04x:%04x not found' % (
-            self._vendor, self._product))
-
-    # If we can't set configuration, it's already been set.
-    try:
-      dev.set_configuration()
-    except usb.core.USBError:
-      pass
-
-    self._dev = dev
-
-    # Get an endpoint instance.
-    cfg = dev.get_active_configuration()
-    intf = usb.util.find_descriptor(cfg, bInterfaceNumber=self._interface)
-    self._intf = intf
-    if not intf:
-      raise SusbError('Interface %04x:%04x - 0x%x not found' % (
-          self._vendor, self._product, self._interface))
-
-    # Detach raiden.ko if it is loaded. CCD endpoints support either a kernel
-    # module driver that produces a ttyUSB, or direct endpoint access, but
-    # can't do both at the same time.
-    if dev.is_kernel_driver_active(intf.bInterfaceNumber) is True:
-      dev.detach_kernel_driver(intf.bInterfaceNumber)
-
-    read_ep_number = intf.bInterfaceNumber + self.READ_ENDPOINT
-    read_ep = usb.util.find_descriptor(intf, bEndpointAddress=read_ep_number)
-    self._read_ep = read_ep
-
-    write_ep_number = intf.bInterfaceNumber + self.WRITE_ENDPOINT
-    write_ep = usb.util.find_descriptor(intf, bEndpointAddress=write_ep_number)
-    self._write_ep = write_ep
-
-  def close(self):
-    usb.util.dispose_resources(self._dev)
+
+    READ_ENDPOINT = 0x81
+    WRITE_ENDPOINT = 0x1
+    TIMEOUT_MS = 100
+
+    def __init__(
+        self,
+        vendor=0x18D1,
+        product=0x5027,
+        interface=1,
+        serialname=None,
+        logger=None,
+    ):
+        """Susb constructor.
+
+        Discovers and connects to stm32 USB endpoints.
+
+        Args:
+          vendor: usb vendor id of stm32 device.
+          product: usb product id of stm32 device.
+          interface: interface number ( 1 - 4 ) of stm32 device to use.
+          serialname: string of device serialname.
+          logger: none
+
+        Raises:
+          SusbError: An error accessing Susb object
+        """
+        self._vendor = vendor
+        self._product = product
+        self._interface = interface
+        self._serialname = serialname
+        self._find_device()
+
+    def _find_device(self):
+        """Set up the usb endpoint"""
+        # Find the stm32.
+        dev_g = usb.core.find(
+            idVendor=self._vendor, idProduct=self._product, find_all=True
+        )
+        dev_list = list(dev_g)
+
+        if not dev_list:
+            raise SusbError("USB device not found")
+
+        # Check if we have multiple stm32s and we've specified the serial.
+        dev = None
+        if self._serialname:
+            for d in dev_list:
+                dev_serial = usb.util.get_string(d, d.iSerialNumber)
+                if dev_serial == self._serialname:
+                    dev = d
+                    break
+            if dev is None:
+                raise SusbError("USB device(%s) not found" % self._serialname)
+        else:
+            try:
+                dev = dev_list[0]
+            except StopIteration:
+                raise SusbError(
+                    "USB device %04x:%04x not found"
+                    % (self._vendor, self._product)
+                )
+
+        # If we can't set configuration, it's already been set.
+        try:
+            dev.set_configuration()
+        except usb.core.USBError:
+            pass
+
+        self._dev = dev
+
+        # Get an endpoint instance.
+        cfg = dev.get_active_configuration()
+        intf = usb.util.find_descriptor(cfg, bInterfaceNumber=self._interface)
+        self._intf = intf
+        if not intf:
+            raise SusbError(
+                "Interface %04x:%04x - 0x%x not found"
+                % (self._vendor, self._product, self._interface)
+            )
+
+        # Detach raiden.ko if it is loaded. CCD endpoints support either a kernel
+        # module driver that produces a ttyUSB, or direct endpoint access, but
+        # can't do both at the same time.
+        if dev.is_kernel_driver_active(intf.bInterfaceNumber) is True:
+            dev.detach_kernel_driver(intf.bInterfaceNumber)
+
+        read_ep_number = intf.bInterfaceNumber + self.READ_ENDPOINT
+        read_ep = usb.util.find_descriptor(
+            intf, bEndpointAddress=read_ep_number
+        )
+        self._read_ep = read_ep
+
+        write_ep_number = intf.bInterfaceNumber + self.WRITE_ENDPOINT
+        write_ep = usb.util.find_descriptor(
+            intf, bEndpointAddress=write_ep_number
+        )
+        self._write_ep = write_ep
+
+    def close(self):
+        usb.util.dispose_resources(self._dev)
diff --git a/extra/tigertool/ecusb/tiny_servo_common.py b/extra/tigertool/ecusb/tiny_servo_common.py
index dbbe42fea8..2d87cf043c 100644
--- a/extra/tigertool/ecusb/tiny_servo_common.py
+++ b/extra/tigertool/ecusb/tiny_servo_common.py
@@ -1,4 +1,4 @@
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -7,164 +7,236 @@
 # Note: This is a py2/3 compatible file.
 
 import datetime
-import errno
-import os
-import re
-import subprocess
 import sys
 import time
 
 import six
+import usb  # pylint:disable=import-error
 
 from . import pty_driver
 from . import stm32uart
 
 
 def get_subprocess_args():
-  if six.PY3:
-    return {'encoding': 'utf-8'}
-  return {}
+    if six.PY3:
+        return {"encoding": "utf-8"}
+    return {}
 
 
 class TinyServoError(Exception):
-  """Exceptions."""
+    """Exceptions."""
 
 
 def log(output):
-  """Print output to console, logfiles can be added here.
+    """Print output to console, logfiles can be added here.
+
+    Args:
+      output: string to output.
+    """
+    sys.stdout.write(output)
+    sys.stdout.write("\n")
+    sys.stdout.flush()
 
-  Args:
-    output: string to output.
-  """
-  sys.stdout.write(output)
-  sys.stdout.write('\n')
-  sys.stdout.flush()
 
 def check_usb(vidpid, serialname=None):
-  """Check if |vidpid| is present on the system's USB.
+    """Check if |vidpid| is present on the system's USB.
 
-  Args:
-    vidpid: string representation of the usb vid:pid, eg. '18d1:2001'
-    serialname: serialname if specified.
+    Args:
+      vidpid: string representation of the usb vid:pid, eg. '18d1:2001'
+      serialname: serialname if specified.
 
-  Returns: True if found, False, otherwise.
-  """
-  if serialname:
-    output = subprocess.check_output(['lsusb', '-v', '-d', vidpid],
-                                     **get_subprocess_args())
-    m = re.search(r'^\s*iSerial\s+\d+\s+%s$' % serialname, output, flags=re.M)
-    if m:
-      return True
+    Returns:
+      True if found, False, otherwise.
+    """
+    if get_usb_dev(vidpid, serialname):
+        return True
 
     return False
-  else:
-    if subprocess.call(['lsusb', '-d', vidpid], stdout=open('/dev/null', 'w')):
-      return False
-  return True
+
 
 def check_usb_sn(vidpid):
-  """Return the serial number
+    """Return the serial number
+
+    Return the serial number of the first USB device with VID:PID vidpid,
+    or None if no device is found. This will not work well with two of
+    the same device attached.
+
+    Args:
+      vidpid: string representation of the usb vid:pid, eg. '18d1:2001'
+
+    Returns:
+      string serial number if found, None otherwise.
+    """
+    dev = get_usb_dev(vidpid)
+
+    if dev:
+        dev_serial = usb.util.get_string(dev, dev.iSerialNumber)
+
+        return dev_serial
+
+    return None
+
+
+def get_usb_dev(vidpid, serialname=None):
+    """Return the USB pyusb devie struct
+
+    Return the dev struct of the first USB device with VID:PID vidpid,
+    or None if no device is found. If more than one device check serial
+    if supplied.
+
+    Args:
+      vidpid: string representation of the usb vid:pid, eg. '18d1:2001'
+      serialname: serialname if specified.
+
+    Returns:
+      pyusb device if found, None otherwise.
+    """
+    vidpidst = vidpid.split(":")
+    vid = int(vidpidst[0], 16)
+    pid = int(vidpidst[1], 16)
 
-  Return the serial number of the first USB device with VID:PID vidpid,
-  or None if no device is found. This will not work well with two of
-  the same device attached.
+    dev_g = usb.core.find(idVendor=vid, idProduct=pid, find_all=True)
+    dev_list = list(dev_g)
 
-  Args:
-    vidpid: string representation of the usb vid:pid, eg. '18d1:2001'
+    if not dev_list:
+        return None
 
-  Returns: string serial number if found, None otherwise.
-  """
-  output = subprocess.check_output(['lsusb', '-v', '-d', vidpid],
-                                   **get_subprocess_args())
-  m = re.search(r'^\s*iSerial\s+(.*)$', output, flags=re.M)
-  if m:
-    return m.group(1)
+    # Check if we have multiple devices and we've specified the serial.
+    dev = None
+    if serialname:
+        for d in dev_list:
+            dev_serial = usb.util.get_string(d, d.iSerialNumber)
+            if dev_serial == serialname:
+                dev = d
+                break
+        if dev is None:
+            return None
+    else:
+        try:
+            dev = dev_list[0]
+        except StopIteration:
+            return None
+
+    return dev
+
+
+def check_usb_dev(vidpid, serialname=None):
+    """Return the USB dev number
+
+    Return the dev number of the first USB device with VID:PID vidpid,
+    or None if no device is found. If more than one device check serial
+    if supplied.
+
+    Args:
+      vidpid: string representation of the usb vid:pid, eg. '18d1:2001'
+      serialname: serialname if specified.
+
+    Returns:
+      usb device number if found, None otherwise.
+    """
+    dev = get_usb_dev(vidpid, serialname=serialname)
+
+    if dev:
+        return dev.address
+
+    return None
 
-  return None
 
 def wait_for_usb_remove(vidpid, serialname=None, timeout=None):
-  """Wait for USB device with vidpid to be removed.
+    """Wait for USB device with vidpid to be removed.
+
+    Wrapper for wait_for_usb below
+    """
+    wait_for_usb(
+        vidpid, serialname=serialname, timeout=timeout, desiredpresence=False
+    )
 
-  Wrapper for wait_for_usb below
-  """
-  wait_for_usb(vidpid, serialname=serialname,
-               timeout=timeout, desiredpresence=False)
 
 def wait_for_usb(vidpid, serialname=None, timeout=None, desiredpresence=True):
-  """Wait for usb device with vidpid to be present/absent.
-
-  Args:
-    vidpid: string representation of the usb vid:pid, eg. '18d1:2001'
-    serialname: serialname if specificed.
-    timeout: timeout in seconds, None for no timeout.
-    desiredpresence: True for present, False for not present.
-
-  Raises:
-    TinyServoError: on timeout.
-  """
-  if timeout:
-    finish = datetime.datetime.now() + datetime.timedelta(seconds=timeout)
-  while check_usb(vidpid, serialname) != desiredpresence:
-    time.sleep(.1)
+    """Wait for usb device with vidpid to be present/absent.
+
+    Args:
+      vidpid: string representation of the usb vid:pid, eg. '18d1:2001'
+      serialname: serialname if specificed.
+      timeout: timeout in seconds, None for no timeout.
+      desiredpresence: True for present, False for not present.
+
+    Raises:
+      TinyServoError: on timeout.
+    """
     if timeout:
-      if datetime.datetime.now() > finish:
-        raise TinyServoError('Timeout', 'Timeout waiting for USB %s' % vidpid)
+        finish = datetime.datetime.now() + datetime.timedelta(seconds=timeout)
+    while check_usb(vidpid, serialname) != desiredpresence:
+        time.sleep(0.1)
+        if timeout:
+            if datetime.datetime.now() > finish:
+                raise TinyServoError(
+                    "Timeout", "Timeout waiting for USB %s" % vidpid
+                )
+
 
 def do_serialno(serialno, pty):
-  """Set serialnumber 'serialno' via ec console 'pty'.
-
-  Commands are:
-  # > serialno set 1234
-  # Saving serial number
-  # Serial number: 1234
-
-  Args:
-    serialno: string serial number to set.
-    pty: tinyservo console to send commands.
-
-  Raises:
-    TinyServoError: on failure to set.
-    ptyError: on command interface error.
-  """
-  cmd = 'serialno set %s' % serialno
-  regex = 'Serial number:\s+(\S+)'
-
-  results = pty._issue_cmd_get_results(cmd, [regex])[0]
-  sn = results[1].strip().strip('\n\r')
-
-  if sn == serialno:
-    log('Success !')
-    log('Serial set to %s' % sn)
-  else:
-    log('Serial number set to %s but saved as %s.' % (serialno, sn))
-    raise TinyServoError(
-        'Serial Number',
-        'Serial number set to %s but saved as %s.' % (serialno, sn))
+    """Set serialnumber 'serialno' via ec console 'pty'.
+
+    Commands are:
+    # > serialno set 1234
+    # Saving serial number
+    # Serial number: 1234
+
+    Args:
+      serialno: string serial number to set.
+      pty: tinyservo console to send commands.
+
+    Raises:
+      TinyServoError: on failure to set.
+      ptyError: on command interface error.
+    """
+    cmd = r"serialno set %s" % serialno
+    regex = r"Serial number:\s+(\S+)"
+
+    results = pty._issue_cmd_get_results(cmd, [regex])[0]
+    sn = results[1].strip().strip("\n\r")
+
+    if sn == serialno:
+        log("Success !")
+        log("Serial set to %s" % sn)
+    else:
+        log("Serial number set to %s but saved as %s." % (serialno, sn))
+        raise TinyServoError(
+            "Serial Number",
+            "Serial number set to %s but saved as %s." % (serialno, sn),
+        )
+
 
 def setup_tinyservod(vidpid, interface, serialname=None, debuglog=False):
-  """Set up a pty
-
-  Set up a pty to the ec console in order
-  to send commands. Returns a pty_driver object.
-
-  Args:
-    vidpid: string vidpid of device to access.
-    interface: not used.
-    serialname: string serial name of device requested, optional.
-    debuglog: chatty printout (boolean)
-
-  Returns: pty object
-
-  Raises:
-    UsbError, SusbError: on device not found
-  """
-  vidstr, pidstr = vidpid.split(':')
-  vid = int(vidstr, 16)
-  pid = int(pidstr, 16)
-  suart = stm32uart.Suart(vendor=vid, product=pid,
-                          interface=interface, serialname=serialname,
-                          debuglog=debuglog)
-  suart.run()
-  pty = pty_driver.ptyDriver(suart, [])
-
-  return pty
+    """Set up a pty
+
+    Set up a pty to the ec console in order
+    to send commands. Returns a pty_driver object.
+
+    Args:
+      vidpid: string vidpid of device to access.
+      interface: not used.
+      serialname: string serial name of device requested, optional.
+      debuglog: chatty printout (boolean)
+
+    Returns:
+      pty object
+
+    Raises:
+      UsbError, SusbError: on device not found
+    """
+    vidstr, pidstr = vidpid.split(":")
+    vid = int(vidstr, 16)
+    pid = int(pidstr, 16)
+    suart = stm32uart.Suart(
+        vendor=vid,
+        product=pid,
+        interface=interface,
+        serialname=serialname,
+        debuglog=debuglog,
+    )
+    suart.run()
+    pty = pty_driver.ptyDriver(suart, [])
+
+    return pty
diff --git a/extra/tigertool/ecusb/tiny_servod.py b/extra/tigertool/ecusb/tiny_servod.py
new file mode 100644
index 0000000000..ca84b4474a
--- /dev/null
+++ b/extra/tigertool/ecusb/tiny_servod.py
@@ -0,0 +1,52 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Helper class to facilitate communication to servo ec console."""
+
+from ecusb import pty_driver
+from ecusb import stm32uart
+
+
+class TinyServod(object):
+    """Helper class to wrap a pty_driver with interface."""
+
+    def __init__(self, vid, pid, interface, serialname=None, debug=False):
+        """Build the driver and interface.
+
+        Args:
+          vid: servo device vid
+          pid: servo device pid
+          interface: which usb interface the servo console is on
+          serialname: the servo device serial (if available)
+        """
+        self._vid = vid
+        self._pid = pid
+        self._interface = interface
+        self._serial = serialname
+        self._debug = debug
+        self._init()
+
+    def _init(self):
+        self.suart = stm32uart.Suart(
+            vendor=self._vid,
+            product=self._pid,
+            interface=self._interface,
+            serialname=self._serial,
+            debuglog=self._debug,
+        )
+        self.suart.run()
+        self.pty = pty_driver.ptyDriver(self.suart, [])
+
+    def reinitialize(self):
+        """Reinitialize the connect after a reset/disconnect/etc."""
+        self.close()
+        self._init()
+
+    def close(self):
+        """Close out the connection and release resources.
+
+        Note: if another TinyServod process or servod itself needs the same device
+              it's necessary to call this to ensure the usb device is available.
+        """
+        self.suart.close()
diff --git a/extra/tigertool/flash_dfu.sh b/extra/tigertool/flash_dfu.sh
index 7aa6c24f09..9578ef626e 100755
--- a/extra/tigertool/flash_dfu.sh
+++ b/extra/tigertool/flash_dfu.sh
@@ -1,5 +1,5 @@
 #!/bin/bash
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/extra/tigertool/make_pkg.sh b/extra/tigertool/make_pkg.sh
index d2860f64c1..ae0ae95cfe 100755
--- a/extra/tigertool/make_pkg.sh
+++ b/extra/tigertool/make_pkg.sh
@@ -1,8 +1,10 @@
 #!/bin/bash
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
+set -e
+
 # Make sure we are in the correct dir.
 cd "$( dirname "${BASH_SOURCE[0]}" )" || exit
 
@@ -17,12 +19,15 @@ cp ../usb_serial/console.py "${DEST}"
 cp ../../../../../chroot/usr/bin/dfu-util "${DEST}"
 cp flash_dfu.sh "${DEST}"
 cp tigertool.py "${DEST}"
+cp tigertest.py "${DEST}"
+cp README.md "${DEST}"
 
 cp -r ecusb "${DEST}"
-cp -r ../../../../../chroot/usr/lib64/python2.7/site-packages/usb "${DEST}"
+# Not compatible with glinux as of 4/28/2022.
+# cp -r ../../../../../chroot/usr/lib64/python3.6/site-packages/usb "${DEST}"
 find "${DEST}" -name "*.py[co]" -delete
 cp -r ../usb_serial "${DEST}"
 
-(cd build; tar -czf tigertool_${DATE}.tgz tigertool)
+(cd build && tar -czf tigertool_"${DATE}".tgz tigertool)
 
 echo "Done packaging tigertool_${DATE}.tgz"
diff --git a/extra/tigertool/tigertest.py b/extra/tigertool/tigertest.py
new file mode 100755
index 0000000000..637652de5c
--- /dev/null
+++ b/extra/tigertool/tigertest.py
@@ -0,0 +1,92 @@
+#!/usr/bin/env python3
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Smoke test of tigertool binary."""
+
+import argparse
+import subprocess
+import sys
+
+
+# Script to control tigertail USB-C Mux board.
+#
+# optional arguments:
+#  -h, --help            show this help message and exit
+#  -s SERIALNO, --serialno SERIALNO
+#                        serial number of board to use
+#  -b BUS, --bus BUS     Which rail to log: [vbus|cc1|cc2]
+#  --setserialno SETSERIALNO
+#                        serial number to set on the board.
+#  --check_serial        check serial number set on the board.
+#  -m MUX, --mux MUX     mux selection
+#  -p, --power           check VBUS
+#  -l POWERLOG, --powerlog POWERLOG
+#                        log VBUS
+#  -r SYSJUMP, --sysjump SYSJUMP
+#                        region selection
+#  --reboot              reboot tigertail
+#  --check_version       check tigertail version
+
+
+def testCmd(cmd, expected_results):
+    """Run command on console, check for success.
+
+    Args:
+      cmd: shell command to run.
+      expected_results: a list object of strings expected in the result.
+
+    Raises:
+      Exception on fail.
+    """
+    print("run: " + cmd)
+    try:
+        p = subprocess.run(cmd, shell=True, check=False, capture_output=True)
+        output = p.stdout.decode("utf-8")
+        error = p.stderr.decode("utf-8")
+        assert p.returncode == 0
+        for result in expected_results:
+            output.index(result)
+    except Exception as e:
+        print("FAIL")
+        print("cmd: " + cmd)
+        print("error: " + str(e))
+        print("stdout:\n" + output)
+        print("stderr:\n" + error)
+        print("expected: " + str(expected_results))
+        print("RC: " + str(p.returncode))
+        raise e
+
+
+def test_sequence():
+    testCmd("./tigertool.py --reboot", ["PASS"])
+    testCmd("./tigertool.py --setserialno test", ["PASS"])
+    testCmd("./tigertool.py --check_serial", ["test", "PASS"])
+    testCmd("./tigertool.py -s test --check_serial", ["test", "PASS"])
+    testCmd("./tigertool.py -m A", ["Mux set to A", "PASS"])
+    testCmd("./tigertool.py -m B", ["Mux set to B", "PASS"])
+    testCmd("./tigertool.py -m off", ["Mux set to off", "PASS"])
+    testCmd("./tigertool.py -p", ["PASS"])
+    testCmd("./tigertool.py -r rw", ["PASS"])
+    testCmd("./tigertool.py -r ro", ["PASS"])
+    testCmd("./tigertool.py --check_version", ["RW", "RO", "PASS"])
+
+    print("PASS")
+
+
+def main(argv):
+    parser = argparse.ArgumentParser(description=__doc__)
+    parser.add_argument(
+        "-c", "--count", type=int, default=1, help="loops to run"
+    )
+
+    opts = parser.parse_args(argv)
+
+    for i in range(1, opts.count + 1):
+        print("Iteration: %d" % i)
+        test_sequence()
+
+
+if __name__ == "__main__":
+    main(sys.argv[1:])
diff --git a/extra/tigertool/tigertool.py b/extra/tigertool/tigertool.py
index 21b046c1d3..f036000afe 100755
--- a/extra/tigertool/tigertool.py
+++ b/extra/tigertool/tigertool.py
@@ -1,5 +1,5 @@
-#!/usr/bin/env python
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+#!/usr/bin/env python3
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -13,250 +13,319 @@
 
 import ecusb.tiny_servo_common as c
 
-STM_VIDPID = '18d1:5027'
-serialno = 'Uninitialized'
+
+STM_VIDPID = "18d1:5027"
+serialno = "Uninitialized"
+
 
 def do_mux(mux, pty):
-  """Set mux via ec console 'pty'.
+    """Set mux via ec console 'pty'.
+
+    Args:
+      mux: mux to connect to DUT, 'A', 'B', or 'off'
+      pty: a pty object connected to tigertail
 
-  Args:
-    mux: mux to connect to DUT, 'A', 'B', or 'off'
-    pty: a pty object connected to tigertail
+    Commands are:
+    # > mux A
+    # TYPE-C mux is A
+    """
+    validmux = ["A", "B", "off"]
+    if mux not in validmux:
+        c.log("Mux setting %s invalid, try one of %s" % (mux, validmux))
+        return False
 
-  Commands are:
-  # > mux A
-  # TYPE-C mux is A
-  """
-  validmux = ['A', 'B', 'off']
-  if mux not in validmux:
-    c.log('Mux setting %s invalid, try one of %s' % (mux, validmux))
-    return False
+    cmd = "mux %s" % mux
+    regex = "TYPE\-C mux is ([^\s\r\n]*)\r"
 
-  cmd = '\r\nmux %s\r\n' % mux
-  regex = 'TYPE\-C mux is ([^\s\r\n]*)\r'
+    results = pty._issue_cmd_get_results(cmd, [regex])[0]
+    result = results[1].strip().strip("\n\r")
 
-  results = pty._issue_cmd_get_results(cmd, [regex])[0]
-  result = results[1].strip().strip('\n\r')
+    if result != mux:
+        c.log("Mux set to %s but saved as %s." % (mux, result))
+        return False
+    c.log("Mux set to %s" % result)
+    return True
 
-  if result != mux:
-    c.log('Mux set to %s but saved as %s.' % (mux, result))
-    return False
-  c.log('Mux set to %s' % result)
-  return True
 
 def do_version(pty):
-  """Check version via ec console 'pty'.
-
-  Args:
-    pty: a pty object connected to tigertail
-
-  Commands are:
-  # > version
-  # Chip:    stm stm32f07x
-  # Board:   0
-  # RO:      tigertail_v1.1.6749-74d1a312e
-  # RW:      tigertail_v1.1.6749-74d1a312e
-  # Build:   tigertail_v1.1.6749-74d1a312e
-  #          2017-07-25 20:08:34 nsanders@meatball.mtv.corp.google.com
-
-  """
-  cmd = '\r\nversion\r\n'
-  regex = 'RO:\s+(\S+)\s+RW:\s+(\S+)\s+Build:\s+(\S+)\s+' \
-          '(\d\d\d\d-\d\d-\d\d \d\d:\d\d:\d\d) (\S+)'
-
-  results = pty._issue_cmd_get_results(cmd, [regex])[0]
-  c.log('Version is %s' % results[3])
-  c.log('RO:    %s' % results[1])
-  c.log('RW:    %s' % results[2])
-  c.log('Date:  %s' % results[4])
-  c.log('Src:   %s' % results[5])
-
-  return True
+    """Check version via ec console 'pty'.
+
+    Args:
+      pty: a pty object connected to tigertail
+
+    Commands are:
+    # > version
+    # Chip:    stm stm32f07x
+    # Board:   0
+    # RO:      tigertail_v1.1.6749-74d1a312e
+    # RW:      tigertail_v1.1.6749-74d1a312e
+    # Build:   tigertail_v1.1.6749-74d1a312e
+    #          2017-07-25 20:08:34 nsanders@meatball.mtv.corp.google.com
+    """
+    cmd = "version"
+    regex = (
+        r"RO:\s+(\S+)\s+RW:\s+(\S+)\s+Build:\s+(\S+)\s+"
+        r"(\d\d\d\d-\d\d-\d\d \d\d:\d\d:\d\d) (\S+)"
+    )
+
+    results = pty._issue_cmd_get_results(cmd, [regex])[0]
+    c.log("Version is %s" % results[3])
+    c.log("RO:    %s" % results[1])
+    c.log("RW:    %s" % results[2])
+    c.log("Date:  %s" % results[4])
+    c.log("Src:   %s" % results[5])
+
+    return True
+
 
 def do_check_serial(pty):
-  """Check serial via ec console 'pty'.
+    """Check serial via ec console 'pty'.
 
-  Args:
-    pty: a pty object connected to tigertail
+    Args:
+      pty: a pty object connected to tigertail
 
-  Commands are:
-  # > serialno
-  # Serial number: number
-  """
-  cmd = '\r\nserialno\r\n'
-  regex = 'Serial number: ([^\n\r]+)'
+    Commands are:
+    # > serialno
+    # Serial number: number
+    """
+    cmd = "serialno"
+    regex = r"Serial number: ([^\n\r]+)"
 
-  results = pty._issue_cmd_get_results(cmd, [regex])[0]
-  c.log('Serial is %s' % results[1])
+    results = pty._issue_cmd_get_results(cmd, [regex])[0]
+    c.log("Serial is %s" % results[1])
 
-  return True
+    return True
 
 
 def do_power(count, bus, pty):
-  """Check power usage via ec console 'pty'.
-
-  Args:
-    count: number of samples to capture
-    bus: rail to monitor, 'vbus', 'cc1', or 'cc2'
-    pty: a pty object connected to tigertail
-
-  Commands are:
-  # > ina 0
-  # Configuration: 4127
-  # Shunt voltage: 02c4 => 1770 uV
-  # Bus voltage  : 1008 => 5130 mV
-  # Power        : 0019 => 625 mW
-  # Current      : 0082 => 130 mA
-  # Calibration  : 0155
-  # Mask/Enable  : 0008
-  # Alert limit  : 0000
-  """
-  if bus == 'vbus':
-    ina = 0
-  if bus == 'cc1':
-    ina = 4
-  if bus == 'cc2':
-    ina = 1
-
-  start = time.time()
-
-  c.log('time,\tmV,\tmW,\tmA')
-
-  cmd = '\r\nina %s\r\n' % ina
-  regex = 'Bus voltage  : \S+ \S+ (\d+) mV\s+' \
-          'Power        : \S+ \S+ (\d+) mW\s+' \
-          'Current      : \S+ \S+ (\d+) mA'
-
-  for i in range(0, count):
-    results = pty._issue_cmd_get_results(cmd, [regex])[0]
-    c.log('%.2f,\t%s,\t%s\t%s' % (time.time() - start,
-          results[1], results[2], results[3]))
+    """Check power usage via ec console 'pty'.
+
+    Args:
+      count: number of samples to capture
+      bus: rail to monitor, 'vbus', 'cc1', or 'cc2'
+      pty: a pty object connected to tigertail
+
+    Commands are:
+    # > ina 0
+    # Configuration: 4127
+    # Shunt voltage: 02c4 => 1770 uV
+    # Bus voltage  : 1008 => 5130 mV
+    # Power        : 0019 => 625 mW
+    # Current      : 0082 => 130 mA
+    # Calibration  : 0155
+    # Mask/Enable  : 0008
+    # Alert limit  : 0000
+    """
+    if bus == "vbus":
+        ina = 0
+    if bus == "cc1":
+        ina = 4
+    if bus == "cc2":
+        ina = 1
+
+    start = time.time()
+
+    c.log("time,\tmV,\tmW,\tmA")
+
+    cmd = "ina %s" % ina
+    regex = (
+        r"Bus voltage  : \S+ \S+ (\d+) mV\s+"
+        r"Power        : \S+ \S+ (\d+) mW\s+"
+        r"Current      : \S+ \S+ (\d+) mA"
+    )
+
+    for i in range(0, count):
+        results = pty._issue_cmd_get_results(cmd, [regex])[0]
+        c.log(
+            "%.2f,\t%s,\t%s\t%s"
+            % (time.time() - start, results[1], results[2], results[3])
+        )
+
+    return True
+
+
+def do_reboot(pty, serialname):
+    """Reboot via ec console pty
+
+    Args:
+      pty: a pty object connected to tigertail
+      serialname: serial name, can be None.
+
+    Command is: reboot.
+    """
+    cmd = "reboot"
+
+    # Check usb dev number on current instance.
+    devno = c.check_usb_dev(STM_VIDPID, serialname=serialname)
+    if not devno:
+        c.log("Device not found")
+        return False
 
-  return True
+    try:
+        pty._issue_cmd(cmd)
+    except Exception as e:
+        c.log("Failed to send command: " + str(e))
+        return False
 
-def do_reboot(pty):
-  """Reboot via ec console pty
+    try:
+        c.wait_for_usb_remove(STM_VIDPID, timeout=3.0, serialname=serialname)
+    except Exception as e:
+        # Polling for reboot isn't reliable but if it hasn't happened in 3 seconds
+        # it's not going to. This step just goes faster if it's detected.
+        pass
 
-  Args:
-    pty: a pty object connected to tigertail
+    try:
+        c.wait_for_usb(STM_VIDPID, timeout=3.0, serialname=serialname)
+    except Exception as e:
+        c.log("Failed to return from reboot: " + str(e))
+        return False
+
+    # Check that the device had a new device number, i.e. it's
+    # disconnected and reconnected.
+    newdevno = c.check_usb_dev(STM_VIDPID, serialname=serialname)
+    if newdevno == devno:
+        c.log("Device didn't reboot")
+        return False
+
+    return True
+
+
+def do_sysjump(region, pty, serialname):
+    """Set region via ec console 'pty'.
+
+    Args:
+      region: ec code region to execute, 'ro' or 'rw'
+      pty: a pty object connected to tigertail
+      serialname: serial name, can be None.
+
+    Commands are:
+    # > sysjump rw
+    """
+    validregion = ["ro", "rw"]
+    if region not in validregion:
+        c.log(
+            "Region setting %s invalid, try one of %s" % (region, validregion)
+        )
+        return False
+
+    cmd = "sysjump %s" % region
+    try:
+        pty._issue_cmd(cmd)
+    except Exception as e:
+        c.log("Exception: " + str(e))
+        return False
 
-  Command is: reboot.
-  """
-  cmd = '\r\nreboot\r\n'
-  regex = 'Rebooting'
+    try:
+        c.wait_for_usb_remove(STM_VIDPID, timeout=3.0, serialname=serialname)
+    except Exception as e:
+        # Polling for reboot isn't reliable but if it hasn't happened in 3 seconds
+        # it's not going to. This step just goes faster if it's detected.
+        pass
+
+    try:
+        c.wait_for_usb(STM_VIDPID, timeout=3.0, serialname=serialname)
+    except Exception as e:
+        c.log("Failed to return from restart: " + str(e))
+        return False
+
+    c.log("Region requested %s" % region)
+    return True
 
-  try:
-    results = pty._issue_cmd_get_results(cmd, [regex])[0]
-    time.sleep(1)
-    c.log(results)
-  except Exception as e:
-    c.log(e)
-    return False
-
-  return True
-
-def do_sysjump(region, pty):
-  """Set region via ec console 'pty'.
-
-  Args:
-    region: ec code region to execute, 'ro' or 'rw'
-    pty: a pty object connected to tigertail
-
-  Commands are:
-  # > sysjump rw
-  """
-  validregion = ['ro', 'rw']
-  if region not in validregion:
-    c.log('Region setting %s invalid, try one of %s' % (
-        region, validregion))
-    return False
-
-  cmd = '\r\nsysjump %s\r\n' % region
-  try:
-    pty._issue_cmd(cmd)
-    time.sleep(1)
-  except Exception as e:
-    c.log(e)
-    return False
-
-  c.log('Region requested %s' % region)
-  return True
 
 def get_parser():
-  parser = argparse.ArgumentParser(
-      description=__doc__)
-  parser.add_argument('-s', '--serialno', type=str, default=None,
-                      help='serial number of board to use')
-  parser.add_argument('-b', '--bus', type=str, default='vbus',
-                     help='Which rail to log: [vbus|cc1|cc2]')
-  group = parser.add_mutually_exclusive_group()
-  group.add_argument('--setserialno', type=str, default=None,
-                     help='serial number to set on the board.')
-  group.add_argument('--check_serial', action='store_true',
-                     help='check serial number set on the board.')
-  group.add_argument('-m', '--mux', type=str, default=None,
-                     help='mux selection')
-  group.add_argument('-p', '--power', action='store_true',
-                     help='check VBUS')
-  group.add_argument('-l', '--powerlog', type=int, default=None,
-                     help='log VBUS')
-  group.add_argument('-r', '--sysjump', type=str, default=None,
-                     help='region selection')
-  group.add_argument('--reboot', action='store_true',
-                     help='reboot tigertail')
-  group.add_argument('--check_version', action='store_true',
-                     help='check tigertail version')
-  return parser
+    parser = argparse.ArgumentParser(description=__doc__)
+    parser.add_argument(
+        "-s",
+        "--serialno",
+        type=str,
+        default=None,
+        help="serial number of board to use",
+    )
+    parser.add_argument(
+        "-b",
+        "--bus",
+        type=str,
+        default="vbus",
+        help="Which rail to log: [vbus|cc1|cc2]",
+    )
+    group = parser.add_mutually_exclusive_group()
+    group.add_argument(
+        "--setserialno",
+        type=str,
+        default=None,
+        help="serial number to set on the board.",
+    )
+    group.add_argument(
+        "--check_serial",
+        action="store_true",
+        help="check serial number set on the board.",
+    )
+    group.add_argument(
+        "-m", "--mux", type=str, default=None, help="mux selection"
+    )
+    group.add_argument("-p", "--power", action="store_true", help="check VBUS")
+    group.add_argument(
+        "-l", "--powerlog", type=int, default=None, help="log VBUS"
+    )
+    group.add_argument(
+        "-r", "--sysjump", type=str, default=None, help="region selection"
+    )
+    group.add_argument("--reboot", action="store_true", help="reboot tigertail")
+    group.add_argument(
+        "--check_version", action="store_true", help="check tigertail version"
+    )
+    return parser
+
 
 def main(argv):
-  parser = get_parser()
-  opts = parser.parse_args(argv)
+    parser = get_parser()
+    opts = parser.parse_args(argv)
 
-  result = True
+    result = True
 
-  # Let's make sure there's a tigertail
-  # If nothing found in 5 seconds, fail.
-  c.wait_for_usb(STM_VIDPID, timeout=5., serialname=opts.serialno)
+    # Let's make sure there's a tigertail
+    # If nothing found in 5 seconds, fail.
+    c.wait_for_usb(STM_VIDPID, timeout=5.0, serialname=opts.serialno)
 
-  pty = c.setup_tinyservod(STM_VIDPID, 0, serialname=opts.serialno)
+    pty = c.setup_tinyservod(STM_VIDPID, 0, serialname=opts.serialno)
 
-  if opts.bus not in ('vbus', 'cc1', 'cc2'):
-    c.log('Try --bus [vbus|cc1|cc2]')
-    result = False
+    if opts.bus not in ("vbus", "cc1", "cc2"):
+        c.log("Try --bus [vbus|cc1|cc2]")
+        result = False
 
-  elif opts.setserialno:
-    try:
-      c.do_serialno(opts.setserialno, pty)
-    except Exception:
-      result = False
+    elif opts.setserialno:
+        try:
+            c.do_serialno(opts.setserialno, pty)
+        except Exception:
+            result = False
 
-  elif opts.mux:
-    result &= do_mux(opts.mux, pty)
+    elif opts.mux:
+        result &= do_mux(opts.mux, pty)
 
-  elif opts.sysjump:
-    result &= do_sysjump(opts.sysjump, pty)
+    elif opts.sysjump:
+        result &= do_sysjump(opts.sysjump, pty, serialname=opts.serialno)
 
-  elif opts.reboot:
-    result &= do_reboot(pty)
+    elif opts.reboot:
+        result &= do_reboot(pty, serialname=opts.serialno)
 
-  elif opts.check_version:
-    result &= do_version(pty)
+    elif opts.check_version:
+        result &= do_version(pty)
 
-  elif opts.check_serial:
-    result &= do_check_serial(pty)
+    elif opts.check_serial:
+        result &= do_check_serial(pty)
 
-  elif opts.power:
-    result &= do_power(1, opts.bus, pty)
+    elif opts.power:
+        result &= do_power(1, opts.bus, pty)
 
-  elif opts.powerlog:
-    result &= do_power(opts.powerlog, opts.bus, pty)
+    elif opts.powerlog:
+        result &= do_power(opts.powerlog, opts.bus, pty)
 
-  if result:
-    c.log('PASS')
-  else:
-    c.log('FAIL')
-    exit(-1)
+    if result:
+        c.log("PASS")
+    else:
+        c.log("FAIL")
+        sys.exit(-1)
 
 
-if __name__ == '__main__':
-  sys.exit(main(sys.argv[1:]))
+if __name__ == "__main__":
+    sys.exit(main(sys.argv[1:]))
diff --git a/extra/touchpad_updater/Makefile b/extra/touchpad_updater/Makefile
index ebf9c3212d..df824e8757 100644
--- a/extra/touchpad_updater/Makefile
+++ b/extra/touchpad_updater/Makefile
@@ -1,4 +1,4 @@
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/extra/touchpad_updater/touchpad_updater.c b/extra/touchpad_updater/touchpad_updater.c
index 598f7638e1..608a847cd6 100644
--- a/extra/touchpad_updater/touchpad_updater.c
+++ b/extra/touchpad_updater/touchpad_updater.c
@@ -1,37 +1,40 @@
 /*
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include <errno.h>
-#include <getopt.h>
-#include <poll.h>
 #include <signal.h>
 #include <stdarg.h>
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
-#include <sys/select.h>
-#include <unistd.h>
 
+#include <getopt.h>
 #include <libusb.h>
+#include <poll.h>
+#include <sys/select.h>
+#include <unistd.h>
 
 /* Command line options */
-static uint16_t vid = 0x18d1;			/* Google */
-static uint16_t pid = 0x5022;			/* Hammer */
-static uint8_t ep_num = 4;			/* console endpoint */
-static uint8_t extended_i2c_exercise;		/* non-zero to exercise */
-static char *firmware_binary = "144.0_2.0.bin";	/* firmware blob */
+static uint16_t vid = 0x18d1; /* Google */
+static uint16_t pid = 0x5022; /* Hammer */
+static uint8_t ep_num = 4; /* console endpoint */
+static uint8_t extended_i2c_exercise; /* non-zero to exercise */
+static char *firmware_binary = "144.0_2.0.bin"; /* firmware blob */
 
 /* Firmware binary blob related */
-#define FW_PAGE_SIZE			64
-#define MAX_FW_PAGE_COUNT	1024
-#define MAX_FW_SIZE			(MAX_FW_PAGE_COUNT*FW_PAGE_SIZE)
+#define MAX_FW_PAGE_SIZE 512
+#define MAX_FW_PAGE_COUNT 1024
+#define MAX_FW_SIZE (128 * 1024)
 
 static uint8_t fw_data[MAX_FW_SIZE];
 int fw_page_count;
+int fw_page_size;
 int fw_size;
+uint8_t ic_type;
+int iap_version;
 
 /* Utility functions */
 static int le_bytes_to_int(uint8_t *buf)
@@ -44,13 +47,10 @@ static char *progname;
 static char *short_opts = ":f:v:p:e:hd";
 static const struct option long_opts[] = {
 	/* name    hasarg *flag val */
-	{"file",     1,   NULL, 'f'},
-	{"vid",      1,   NULL, 'v'},
-	{"pid",      1,   NULL, 'p'},
-	{"ep",       1,   NULL, 'e'},
-	{"help",     0,   NULL, 'h'},
-	{"debug",    0,   NULL, 'd'},
-	{NULL,       0,   NULL, 0},
+	{ "file", 1, NULL, 'f' }, { "vid", 1, NULL, 'v' },
+	{ "pid", 1, NULL, 'p' },  { "ep", 1, NULL, 'e' },
+	{ "help", 0, NULL, 'h' }, { "debug", 0, NULL, 'd' },
+	{ NULL, 0, NULL, 0 },
 };
 
 static void usage(int errs)
@@ -68,7 +68,8 @@ static void usage(int errs)
 	       "  -d,--debug              Exercise extended read I2C over USB\n"
 	       "                          and print verbose debug messages.\n"
 	       "  -h,--help               Show this message\n"
-	       "\n", progname, firmware_binary, vid, pid, ep_num);
+	       "\n",
+	       progname, firmware_binary, vid, pid, ep_num);
 
 	exit(!!errs);
 }
@@ -84,28 +85,28 @@ static void parse_cmdline(int argc, char *argv[])
 	else
 		progname = argv[0];
 
-	opterr = 0;				/* quiet, you */
+	opterr = 0; /* quiet, you */
 	while ((i = getopt_long(argc, argv, short_opts, long_opts, 0)) != -1) {
 		switch (i) {
 		case 'f':
 			firmware_binary = optarg;
 			break;
 		case 'p':
-			pid = (uint16_t) strtoul(optarg, &e, 16);
+			pid = (uint16_t)strtoull(optarg, &e, 16);
 			if (!*optarg || (e && *e)) {
 				printf("Invalid argument: \"%s\"\n", optarg);
 				errorcnt++;
 			}
 			break;
 		case 'v':
-			vid = (uint16_t) strtoul(optarg, &e, 16);
+			vid = (uint16_t)strtoull(optarg, &e, 16);
 			if (!*optarg || (e && *e)) {
 				printf("Invalid argument: \"%s\"\n", optarg);
 				errorcnt++;
 			}
 			break;
 		case 'e':
-			ep_num = (uint8_t) strtoul(optarg, &e, 0);
+			ep_num = (uint8_t)strtoull(optarg, &e, 0);
 			if (!*optarg || (e && *e)) {
 				printf("Invalid argument: \"%s\"\n", optarg);
 				errorcnt++;
@@ -117,7 +118,7 @@ static void parse_cmdline(int argc, char *argv[])
 		case 'h':
 			usage(errorcnt);
 			break;
-		case 0:				/* auto-handled option */
+		case 0: /* auto-handled option */
 			break;
 		case '?':
 			if (optopt)
@@ -139,7 +140,6 @@ static void parse_cmdline(int argc, char *argv[])
 
 	if (errorcnt)
 		usage(errorcnt);
-
 }
 
 /* USB transfer related */
@@ -160,7 +160,7 @@ static void request_exit(const char *format, ...)
 	va_start(ap, format);
 	vfprintf(stderr, format, ap);
 	va_end(ap);
-	do_exit++;    /* Why need this ? */
+	do_exit++; /* Why need this ? */
 
 	if (tx_transfer)
 		libusb_free_transfer(tx_transfer);
@@ -175,13 +175,12 @@ static void request_exit(const char *format, ...)
 	exit(1);
 }
 
-#define DIE(msg, r)							\
-	request_exit("%s: line %d, %s\n", msg, __LINE__,		\
-		     libusb_error_name(r))
+#define DIE(msg, r) \
+	request_exit("%s: line %d, %s\n", msg, __LINE__, libusb_error_name(r))
 
 static void sighandler(int signum)
 {
-	request_exit("caught signal %d: %s\n", signum, sys_siglist[signum]);
+	request_exit("caught signal %d: %s\n", signum, strsignal(signum));
 }
 
 static int find_interface_with_endpoint(int want_ep_num)
@@ -256,8 +255,8 @@ static void register_sigaction(void)
 }
 
 /* Transfer over libusb */
-#define I2C_PORT_ON_HAMMER		0x00
-#define I2C_ADDRESS_ON_HAMMER		0x15
+#define I2C_PORT_ON_HAMMER 0x00
+#define I2C_ADDRESS_ON_HAMMER 0x15
 
 static int check_read_status(int r, int expected, int actual)
 {
@@ -288,12 +287,12 @@ static int check_read_status(int r, int expected, int actual)
 	return r;
 }
 
-#define MAX_USB_PACKET_SIZE		64
-#define PRIMITIVE_READING_SIZE		60
+#define MAX_USB_PACKET_SIZE 64
+#define PRIMITIVE_READING_SIZE 60
 
-static int libusb_single_write_and_read(
-		uint8_t *to_write, uint16_t write_length,
-		uint8_t *to_read, uint16_t read_length)
+static int libusb_single_write_and_read(const uint8_t *to_write,
+					uint16_t write_length, uint8_t *to_read,
+					uint16_t read_length)
 {
 	int r;
 	int tx_ready;
@@ -304,18 +303,18 @@ static int libusb_single_write_and_read(
 	tx_transfer = rx_transfer = 0;
 
 	memmove(tx_buf + offset, to_write, write_length);
-	tx_buf[0] = I2C_PORT_ON_HAMMER;
+	tx_buf[0] = I2C_PORT_ON_HAMMER | ((write_length >> 8) << 4);
 	tx_buf[1] = I2C_ADDRESS_ON_HAMMER;
-	tx_buf[2] = write_length;
+	tx_buf[2] = write_length & 0xff;
 	if (read_length > PRIMITIVE_READING_SIZE) {
 		tx_buf[3] = (read_length & 0x7f) | (1 << 7);
 		tx_buf[4] = read_length >> 7;
 		if (extended_i2c_exercise) {
 			printf("Triggering extended reading."
-				"rc:%0x, rc1:%0x\n",
-				tx_buf[3], tx_buf[4]);
+			       "rc:%0x, rc1:%0x\n",
+			       tx_buf[3], tx_buf[4]);
 			printf("Expecting %d Bytes.\n",
-				(tx_buf[3] & 0x7f) | (tx_buf[4] << 7));
+			       (tx_buf[3] & 0x7f) | (tx_buf[4] << 7));
 		}
 	} else {
 		tx_buf[3] = read_length;
@@ -328,19 +327,18 @@ static int libusb_single_write_and_read(
 	while (sent_bytes < (offset + write_length)) {
 		tx_ready = remains = (offset + write_length) - sent_bytes;
 
-		r = libusb_bulk_transfer(devh,
-				(ep_num | LIBUSB_ENDPOINT_OUT),
-				tx_buf + sent_bytes, tx_ready,
-				&actual_length, 5000);
+		r = libusb_bulk_transfer(devh, (ep_num | LIBUSB_ENDPOINT_OUT),
+					 tx_buf + sent_bytes, tx_ready,
+					 &actual_length, 5000);
 		if (r == 0 && actual_length == tx_ready) {
 			r = libusb_bulk_transfer(devh,
-					(ep_num | LIBUSB_ENDPOINT_IN),
-					rx_buf, sizeof(rx_buf),
-					&actual_length, 5000);
+						 (ep_num | LIBUSB_ENDPOINT_IN),
+						 rx_buf, sizeof(rx_buf),
+						 &actual_length, 5000);
 		}
-		r = check_read_status(
-				r, (remains == tx_ready) ? read_length : 0,
-				actual_length);
+		r = check_read_status(r,
+				      (remains == tx_ready) ? read_length : 0,
+				      actual_length);
 		if (r)
 			break;
 		sent_bytes += tx_ready;
@@ -349,21 +347,19 @@ static int libusb_single_write_and_read(
 }
 
 /* Control Elan trackpad I2C over USB */
-#define ETP_I2C_INF_LENGTH		2
+#define ETP_I2C_INF_LENGTH 2
 
-static int elan_write_and_read(
-		int reg, uint8_t *buf, int read_length,
-		int with_cmd, int cmd)
+static int elan_write_and_read(int reg, uint8_t *buf, int read_length,
+			       int with_cmd, int cmd)
 {
-
 	tx_buf[0] = (reg >> 0) & 0xff;
 	tx_buf[1] = (reg >> 8) & 0xff;
 	if (with_cmd) {
 		tx_buf[2] = (cmd >> 0) & 0xff;
 		tx_buf[3] = (cmd >> 8) & 0xff;
 	}
-	return libusb_single_write_and_read(
-			tx_buf, with_cmd ? 4 : 2, rx_buf, read_length);
+	return libusb_single_write_and_read(tx_buf, with_cmd ? 4 : 2, rx_buf,
+					    read_length);
 }
 
 static int elan_read_block(int reg, uint8_t *buf, int read_length)
@@ -382,51 +378,63 @@ static int elan_write_cmd(int reg, int cmd)
 }
 
 /* Elan trackpad firmware information related */
-#define ETP_I2C_IAP_VERSION_CMD		0x0110
-#define ETP_I2C_FW_VERSION_CMD		0x0102
-#define ETP_I2C_IAP_CHECKSUM_CMD	0x0315
-#define ETP_I2C_FW_CHECKSUM_CMD		0x030F
-#define ETP_I2C_OSM_VERSION_CMD		0x0103
+#define ETP_I2C_IAP_VERSION_CMD 0x0110
+#define ETP_I2C_FW_VERSION_CMD 0x0102
+#define ETP_I2C_IAP_CHECKSUM_CMD 0x0315
+#define ETP_I2C_FW_CHECKSUM_CMD 0x030F
+#define ETP_I2C_OSM_VERSION_CMD 0x0103
 
-static int elan_get_ic_page_count(void)
+static int elan_get_version(int is_iap)
 {
-	uint8_t ic_type;
+	elan_read_cmd(is_iap ? ETP_I2C_IAP_VERSION_CMD :
+			       ETP_I2C_FW_VERSION_CMD);
+	return le_bytes_to_int(rx_buf + 4);
+}
 
+static void elan_get_ic_page_count(void)
+{
 	elan_read_cmd(ETP_I2C_OSM_VERSION_CMD);
 
 	ic_type = rx_buf[5];
+	printf("ic_type: %02x\n", ic_type);
 
 	switch (ic_type) {
 	case 0x09:
-		return 768;
+		fw_page_count = 768;
+		break;
 	case 0x0D:
-		return 896;
+		fw_page_count = 896;
+		break;
 	case 0x00:
 	case 0x10:
-		return 1024;
+	case 0x14:
+		fw_page_count = 1024;
+		break;
 	default:
 		request_exit("The IC type is not supported.\n");
 	}
-	return -1;
-}
 
-static int elan_get_version(int is_iap)
-{
-	elan_read_cmd(
-		is_iap ? ETP_I2C_IAP_VERSION_CMD : ETP_I2C_FW_VERSION_CMD);
-	return le_bytes_to_int(rx_buf + 4);
+	iap_version = elan_get_version(1);
+	if (ic_type == 0x14 && iap_version >= 2) {
+		fw_page_count /= 8;
+		fw_page_size = 512;
+	} else if (ic_type >= 0x0D && iap_version >= 1) {
+		fw_page_count /= 2;
+		fw_page_size = 128;
+	} else {
+		fw_page_size = 64;
+	}
 }
 
 static int elan_get_checksum(int is_iap)
 {
-	elan_read_cmd(
-		is_iap ? ETP_I2C_IAP_CHECKSUM_CMD : ETP_I2C_FW_CHECKSUM_CMD);
+	elan_read_cmd(is_iap ? ETP_I2C_IAP_CHECKSUM_CMD :
+			       ETP_I2C_FW_CHECKSUM_CMD);
 	return le_bytes_to_int(rx_buf + 4);
 }
 
 static uint16_t elan_get_fw_info(void)
 {
-	int iap_version = -1;
 	int fw_version = -1;
 	uint16_t iap_checksum = 0xffff;
 	uint16_t fw_checksum = 0xffff;
@@ -436,20 +444,21 @@ static uint16_t elan_get_fw_info(void)
 	iap_checksum = elan_get_checksum(1);
 	fw_version = elan_get_version(0);
 	iap_version = elan_get_version(1);
-	printf("IAP  version: %4x, FW  version: %4x\n",
-			iap_version, fw_version);
-	printf("IAP checksum: %4x, FW checksum: %4x\n",
-			iap_checksum, fw_checksum);
+	printf("IAP  version: %4x, FW  version: %4x\n", iap_version,
+	       fw_version);
+	printf("IAP checksum: %4x, FW checksum: %4x\n", iap_checksum,
+	       fw_checksum);
 	return fw_checksum;
 }
 
 /* Update preparation */
-#define ETP_I2C_IAP_RESET_CMD		0x0314
-#define ETP_I2C_IAP_RESET		0xF0F0
-#define ETP_I2C_IAP_CTRL_CMD		0x0310
-#define ETP_I2C_MAIN_MODE_ON		(1 << 9)
-#define ETP_I2C_IAP_CMD			0x0311
-#define ETP_I2C_IAP_PASSWORD		0x1EA5
+#define ETP_I2C_IAP_RESET_CMD 0x0314
+#define ETP_I2C_IAP_RESET 0xF0F0
+#define ETP_I2C_IAP_CTRL_CMD 0x0310
+#define ETP_I2C_MAIN_MODE_ON (1 << 9)
+#define ETP_I2C_IAP_CMD 0x0311
+#define ETP_I2C_IAP_PASSWORD 0x1EA5
+#define ETP_I2C_IAP_TYPE_CMD 0x0304
 
 static int elan_in_main_mode(void)
 {
@@ -457,6 +466,26 @@ static int elan_in_main_mode(void)
 	return le_bytes_to_int(rx_buf + 4) & ETP_I2C_MAIN_MODE_ON;
 }
 
+static int elan_read_write_iap_type(void)
+{
+	for (int retry = 0; retry < 3; ++retry) {
+		uint16_t val;
+
+		if (elan_write_cmd(ETP_I2C_IAP_TYPE_CMD, fw_page_size / 2))
+			return -1;
+
+		if (elan_read_cmd(ETP_I2C_IAP_TYPE_CMD))
+			return -1;
+
+		val = le_bytes_to_int(rx_buf + 4);
+		if (val == fw_page_size / 2) {
+			printf("%s: OK\n", __func__);
+			return 0;
+		}
+	}
+	return -1;
+}
+
 static void elan_prepare_for_update(void)
 {
 	printf("%s\n", __func__);
@@ -474,7 +503,12 @@ static void elan_prepare_for_update(void)
 
 	/* We should be in the IAP mode now */
 	if (elan_in_main_mode())
-		request_exit("Failure to enter IAP mode, still in main mode");
+		request_exit("Failure to enter IAP mode, still in main mode\n");
+
+	if (ic_type >= 0x0D && iap_version >= 1) {
+		if (elan_read_write_iap_type())
+			request_exit("Failure to set IAP mode\n");
+	}
 
 	/* Send the passphrase again */
 	elan_write_cmd(ETP_I2C_IAP_CMD, ETP_I2C_IAP_PASSWORD);
@@ -485,17 +519,17 @@ static void elan_prepare_for_update(void)
 		request_exit("cannot read iap password.\n");
 	if (le_bytes_to_int(rx_buf + 4) != ETP_I2C_IAP_PASSWORD)
 		request_exit("Got an unexpected IAP password %4x\n",
-			le_bytes_to_int(rx_buf + 4));
+			     le_bytes_to_int(rx_buf + 4));
 }
 
 /* Firmware block update */
-#define ETP_IAP_START_ADDR		0x0083
+#define ETP_IAP_START_ADDR 0x0083
 
 static uint16_t elan_calc_checksum(uint8_t *data, int length)
 {
 	uint16_t checksum = 0;
 	for (int i = 0; i < length; i += 2)
-		checksum += ((uint16_t)(data[i+1]) << 8) | (data[i]);
+		checksum += ((uint16_t)(data[i + 1]) << 8) | (data[i]);
 	return checksum;
 }
 
@@ -504,27 +538,28 @@ static int elan_get_iap_addr(void)
 	return le_bytes_to_int(fw_data + ETP_IAP_START_ADDR * 2) * 2;
 }
 
-#define ETP_I2C_IAP_REG_L		0x01
-#define ETP_I2C_IAP_REG_H		0x06
+#define ETP_I2C_IAP_REG_L 0x01
+#define ETP_I2C_IAP_REG_H 0x06
 
-#define ETP_FW_IAP_PAGE_ERR		(1 << 5)
-#define ETP_FW_IAP_INTF_ERR		(1 << 4)
+#define ETP_FW_IAP_PAGE_ERR (1 << 5)
+#define ETP_FW_IAP_INTF_ERR (1 << 4)
 
 static int elan_write_fw_block(uint8_t *raw_data, uint16_t checksum)
 {
-	uint8_t page_store[FW_PAGE_SIZE + 4];
+	uint8_t page_store[MAX_FW_PAGE_SIZE + 4];
 	int rv;
+
 	page_store[0] = ETP_I2C_IAP_REG_L;
 	page_store[1] = ETP_I2C_IAP_REG_H;
-	memcpy(page_store + 2, raw_data, FW_PAGE_SIZE);
-	page_store[FW_PAGE_SIZE + 2 + 0] = (checksum >> 0) & 0xff;
-	page_store[FW_PAGE_SIZE + 2 + 1] = (checksum >> 8) & 0xff;
+	memcpy(page_store + 2, raw_data, fw_page_size);
+	page_store[fw_page_size + 2 + 0] = (checksum >> 0) & 0xff;
+	page_store[fw_page_size + 2 + 1] = (checksum >> 8) & 0xff;
 
-	rv = libusb_single_write_and_read(
-			page_store, sizeof(page_store), rx_buf, 0);
+	rv = libusb_single_write_and_read(page_store, fw_page_size + 4, rx_buf,
+					  0);
 	if (rv)
 		return rv;
-	usleep(20 * 1000);
+	usleep((fw_page_size >= 512 ? 50 : 35) * 1000);
 	elan_read_cmd(ETP_I2C_IAP_CTRL_CMD);
 	rv = le_bytes_to_int(rx_buf + 4);
 	if (rv & (ETP_FW_IAP_PAGE_ERR | ETP_FW_IAP_INTF_ERR)) {
@@ -534,7 +569,6 @@ static int elan_write_fw_block(uint8_t *raw_data, uint16_t checksum)
 	return 0;
 }
 
-
 static uint16_t elan_update_firmware(void)
 {
 	uint16_t checksum = 0, block_checksum;
@@ -542,13 +576,13 @@ static uint16_t elan_update_firmware(void)
 
 	printf("%s\n", __func__);
 
-	for (int i = elan_get_iap_addr(); i < fw_size; i += FW_PAGE_SIZE) {
-		printf("\rUpdating page %3d...", i / FW_PAGE_SIZE);
+	for (int i = elan_get_iap_addr(); i < fw_size; i += fw_page_size) {
+		printf("\rUpdating page %3d...", i / fw_page_size);
 		fflush(stdout);
-		block_checksum = elan_calc_checksum(fw_data + i, FW_PAGE_SIZE);
+		block_checksum = elan_calc_checksum(fw_data + i, fw_page_size);
 		rv = elan_write_fw_block(fw_data + i, block_checksum);
 		if (rv)
-			request_exit("Failed to update.");
+			request_exit("Failed to update.\n");
 		checksum += block_checksum;
 		printf(" Updated, checksum: %d", checksum);
 		fflush(stdout);
@@ -579,9 +613,9 @@ int main(int argc, char *argv[])
 	 * Judge IC type  and get page count first.
 	 * Then check the FW file.
 	 */
-	fw_page_count = elan_get_ic_page_count();
-	fw_size = fw_page_count * FW_PAGE_SIZE;
-	printf("IC page count is %04X\n", fw_page_count);
+	elan_get_ic_page_count();
+	fw_size = fw_page_count * fw_page_size;
+	printf("FW has %d bytes x %d pages\n", fw_page_size, fw_page_count);
 
 	/* Read the FW file */
 	FILE *f = fopen(firmware_binary, "rb");
@@ -617,7 +651,7 @@ int main(int argc, char *argv[])
 	remote_checksum = elan_get_checksum(1);
 	if (remote_checksum != local_checksum)
 		printf("checksum diff local=[%04X], remote=[%04X]\n",
-				local_checksum, remote_checksum);
+		       local_checksum, remote_checksum);
 
 	/* Print the updated firmware information */
 	elan_get_fw_info();
diff --git a/extra/usb_console/Makefile b/extra/usb_console/Makefile
index bddca1d0a2..bc4c5909a2 100644
--- a/extra/usb_console/Makefile
+++ b/extra/usb_console/Makefile
@@ -1,4 +1,4 @@
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/extra/usb_console/usb_console.c b/extra/usb_console/usb_console.c
index 7d99bc3082..db1f2a4bec 100644
--- a/extra/usb_console/usb_console.c
+++ b/extra/usb_console/usb_console.c
@@ -1,29 +1,29 @@
 /*
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include <errno.h>
-#include <getopt.h>
-#include <poll.h>
 #include <signal.h>
 #include <stdarg.h>
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
-#include <sys/select.h>
-#include <unistd.h>
 
+#include <getopt.h>
 #include <libusb.h>
+#include <poll.h>
+#include <sys/select.h>
+#include <unistd.h>
 
 /* Options */
-static uint16_t vid = 0x18d1;			/* Google */
-static uint16_t pid = 0x500f;			/* discovery-stm32f072 */
-static uint8_t ep_num = 4;			/* console endpoint */
+static uint16_t vid = 0x18d1; /* Google */
+static uint16_t pid = 0x500f; /* discovery-stm32f072 */
+static uint8_t ep_num = 4; /* console endpoint */
 
-static unsigned char rx_buf[1024];		/* much too big */
-static unsigned char tx_buf[1024];		/* much too big */
+static unsigned char rx_buf[1024]; /* much too big */
+static unsigned char tx_buf[1024]; /* much too big */
 static const struct libusb_pollfd **usb_fds;
 static struct libusb_device_handle *devh;
 static struct libusb_transfer *rx_transfer;
@@ -40,13 +40,12 @@ static void request_exit(const char *format, ...)
 	do_exit++;
 }
 
-#define BOO(msg, r)							\
-	request_exit("%s: line %d, %s\n", msg, __LINE__,		\
-		     libusb_error_name(r))
+#define BOO(msg, r) \
+	request_exit("%s: line %d, %s\n", msg, __LINE__, libusb_error_name(r))
 
 static void sighandler(int signum)
 {
-	request_exit("caught signal %d: %s\n", signum, sys_siglist[signum]);
+	request_exit("caught signal %d: %s\n", signum, strsignal(signum));
 }
 
 #if 0
@@ -105,8 +104,8 @@ static void send_tx(int len)
 {
 	int r;
 
-	libusb_fill_bulk_transfer(tx_transfer, devh,
-				  ep_num, tx_buf, len, cb_tx, NULL, 0);
+	libusb_fill_bulk_transfer(tx_transfer, devh, ep_num, tx_buf, len, cb_tx,
+				  NULL, 0);
 
 	r = libusb_submit_transfer(tx_transfer);
 	if (r < 0)
@@ -185,7 +184,7 @@ static int wait_for_stuff_to_happen(void)
 		return -1;
 	}
 
-	if (r == 0)				/* timed out */
+	if (r == 0) /* timed out */
 		return 0;
 
 	/* Ignore stdin until we've finished sending the current line */
@@ -235,11 +234,9 @@ static char *progname;
 static char *short_opts = ":v:p:e:h";
 static const struct option long_opts[] = {
 	/* name    hasarg *flag val */
-	{"vid",      1,   NULL, 'v'},
-	{"pid",      1,   NULL, 'p'},
-	{"ep",       1,   NULL, 'e'},
-	{"help",     0,   NULL, 'h'},
-	{NULL,       0,   NULL, 0},
+	{ "vid", 1, NULL, 'v' }, { "pid", 1, NULL, 'p' },
+	{ "ep", 1, NULL, 'e' },	 { "help", 0, NULL, 'h' },
+	{ NULL, 0, NULL, 0 },
 };
 
 static void usage(int errs)
@@ -254,7 +251,8 @@ static void usage(int errs)
 	       "  -p,--pid    HEXVAL      Product ID (default %04x)\n"
 	       "  -e,--ep     NUM         Endpoint (default %d)\n"
 	       "  -h,--help               Show this message\n"
-	       "\n", progname, vid, pid, ep_num);
+	       "\n",
+	       progname, vid, pid, ep_num);
 
 	exit(!!errs);
 }
@@ -275,25 +273,25 @@ int main(int argc, char *argv[])
 	else
 		progname = argv[0];
 
-	opterr = 0;				/* quiet, you */
+	opterr = 0; /* quiet, you */
 	while ((i = getopt_long(argc, argv, short_opts, long_opts, 0)) != -1) {
 		switch (i) {
 		case 'p':
-			pid = (uint16_t) strtoul(optarg, &e, 16);
+			pid = (uint16_t)strtoull(optarg, &e, 16);
 			if (!*optarg || (e && *e)) {
 				printf("Invalid argument: \"%s\"\n", optarg);
 				errorcnt++;
 			}
 			break;
 		case 'v':
-			vid = (uint16_t) strtoul(optarg, &e, 16);
+			vid = (uint16_t)strtoull(optarg, &e, 16);
 			if (!*optarg || (e && *e)) {
 				printf("Invalid argument: \"%s\"\n", optarg);
 				errorcnt++;
 			}
 			break;
 		case 'e':
-			ep_num = (uint8_t) strtoul(optarg, &e, 0);
+			ep_num = (uint8_t)strtoull(optarg, &e, 0);
 			if (!*optarg || (e && *e)) {
 				printf("Invalid argument: \"%s\"\n", optarg);
 				errorcnt++;
@@ -302,7 +300,7 @@ int main(int argc, char *argv[])
 		case 'h':
 			usage(errorcnt);
 			break;
-		case 0:				/* auto-handled option */
+		case 0: /* auto-handled option */
 			break;
 		case '?':
 			if (optopt)
@@ -368,9 +366,8 @@ int main(int argc, char *argv[])
 		printf("can't alloc rx_transfer");
 		goto out;
 	}
-	libusb_fill_bulk_transfer(rx_transfer, devh,
-				  0x80 | ep_num,
-				  rx_buf, sizeof(rx_buf), cb_rx, NULL, 0);
+	libusb_fill_bulk_transfer(rx_transfer, devh, 0x80 | ep_num, rx_buf,
+				  sizeof(rx_buf), cb_rx, NULL, 0);
 
 	tx_transfer = libusb_alloc_transfer(0);
 	if (!tx_transfer) {
@@ -396,14 +393,14 @@ int main(int argc, char *argv[])
 	while (!do_exit) {
 		r = wait_for_stuff_to_happen();
 		switch (r) {
-		case 0:	/* timed out */
+		case 0: /* timed out */
 			/* printf("."); */
 			/* fflush(stdout); */
 			break;
-		case 1:	/* stdin ready */
+		case 1: /* stdin ready */
 			handle_stdin();
 			break;
-		case 2:	/* libusb ready */
+		case 2: /* libusb ready */
 			handle_libusb();
 			break;
 		}
@@ -440,7 +437,7 @@ int main(int argc, char *argv[])
 
 	printf("bye\n");
 	r = 0;
- out:
+out:
 	if (tx_transfer)
 		libusb_free_transfer(tx_transfer);
 	if (rx_transfer)
diff --git a/extra/usb_gpio/Makefile b/extra/usb_gpio/Makefile
index 644e3ee70f..84a27ccc12 100644
--- a/extra/usb_gpio/Makefile
+++ b/extra/usb_gpio/Makefile
@@ -1,4 +1,4 @@
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
+# Copyright 2014 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/extra/usb_gpio/usb_gpio.c b/extra/usb_gpio/usb_gpio.c
index 8973f3d304..41810a6a0e 100644
--- a/extra/usb_gpio/usb_gpio.c
+++ b/extra/usb_gpio/usb_gpio.c
@@ -1,64 +1,57 @@
 /*
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
+ * Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <libusb.h>
 #include <stdint.h>
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
+
+#include <libusb.h>
 #include <unistd.h>
 
-#define CHECK(expression)					\
-	({							\
-		int error__ = (expression);			\
-								\
-		if (error__ != 0) {				\
-			fprintf(stderr,				\
-				"libusb error: %s:%d %s\n",	\
-				__FILE__,			\
-				__LINE__,			\
-				libusb_error_name(error__));	\
-			return error__;				\
-		}						\
-								\
-		error__;					\
+#define CHECK(expression)                                                     \
+	({                                                                    \
+		int error__ = (expression);                                   \
+                                                                              \
+		if (error__ != 0) {                                           \
+			fprintf(stderr, "libusb error: %s:%d %s\n", __FILE__, \
+				__LINE__, libusb_error_name(error__));        \
+			return error__;                                       \
+		}                                                             \
+                                                                              \
+		error__;                                                      \
 	})
 
 #define TRANSFER_TIMEOUT_MS 100
 
-static int gpio_write(libusb_device_handle *device,
-		      uint32_t set_mask,
+static int gpio_write(libusb_device_handle *device, uint32_t set_mask,
 		      uint32_t clear_mask)
 {
 	uint8_t command[8];
-	int     transferred;
+	int transferred;
 
-	command[0] = (set_mask >>  0) & 0xff;
-	command[1] = (set_mask >>  8) & 0xff;
+	command[0] = (set_mask >> 0) & 0xff;
+	command[1] = (set_mask >> 8) & 0xff;
 	command[2] = (set_mask >> 16) & 0xff;
 	command[3] = (set_mask >> 24) & 0xff;
 
-	command[4] = (clear_mask >>  0) & 0xff;
-	command[5] = (clear_mask >>  8) & 0xff;
+	command[4] = (clear_mask >> 0) & 0xff;
+	command[5] = (clear_mask >> 8) & 0xff;
 	command[6] = (clear_mask >> 16) & 0xff;
 	command[7] = (clear_mask >> 24) & 0xff;
 
-	CHECK(libusb_bulk_transfer(device,
-				   LIBUSB_ENDPOINT_OUT | 2,
-				   command,
-				   sizeof(command),
-				   &transferred,
+	CHECK(libusb_bulk_transfer(device, LIBUSB_ENDPOINT_OUT | 2, command,
+				   sizeof(command), &transferred,
 				   TRANSFER_TIMEOUT_MS));
 
 	if (transferred != sizeof(command)) {
 		fprintf(stderr,
 			"Failed to transfer full command "
 			"(sent %d of %d bytes)\n",
-			transferred,
-			(int)sizeof(command));
+			transferred, (int)sizeof(command));
 		return LIBUSB_ERROR_OTHER;
 	}
 
@@ -68,38 +61,29 @@ static int gpio_write(libusb_device_handle *device,
 static int gpio_read(libusb_device_handle *device, uint32_t *mask)
 {
 	uint8_t response[4];
-	int     transferred;
+	int transferred;
 
 	/*
 	 * The first query does triggers the sampling of the GPIO values, the
 	 * second query reads them back.
 	 */
-	CHECK(libusb_bulk_transfer(device,
-				   LIBUSB_ENDPOINT_IN | 2,
-				   response,
-				   sizeof(response),
-				   &transferred,
+	CHECK(libusb_bulk_transfer(device, LIBUSB_ENDPOINT_IN | 2, response,
+				   sizeof(response), &transferred,
 				   TRANSFER_TIMEOUT_MS));
 
-	CHECK(libusb_bulk_transfer(device,
-				   LIBUSB_ENDPOINT_IN | 2,
-				   response,
-				   sizeof(response),
-				   &transferred,
+	CHECK(libusb_bulk_transfer(device, LIBUSB_ENDPOINT_IN | 2, response,
+				   sizeof(response), &transferred,
 				   TRANSFER_TIMEOUT_MS));
 
 	if (transferred != sizeof(response)) {
 		fprintf(stderr,
 			"Failed to transfer full response "
 			"(read %d of %d bytes)\n",
-			transferred,
-			(int)sizeof(response));
+			transferred, (int)sizeof(response));
 		return LIBUSB_ERROR_OTHER;
 	}
 
-	*mask = (response[0] <<  0 |
-		 response[1] <<  8 |
-		 response[2] << 16 |
+	*mask = (response[0] << 0 | response[1] << 8 | response[2] << 16 |
 		 response[3] << 24);
 
 	return 0;
@@ -107,13 +91,13 @@ static int gpio_read(libusb_device_handle *device, uint32_t *mask)
 
 int main(int argc, char **argv)
 {
-	libusb_context       *context;
+	libusb_context *context;
 	libusb_device_handle *device;
-	uint16_t              vendor_id  = 0x18d1; /* Google */
-	uint16_t              product_id = 0x500f; /* discovery-stm32f072 */
-	int                   interface = 1;	   /* gpio interface */
+	uint16_t vendor_id = 0x18d1; /* Google */
+	uint16_t product_id = 0x500f; /* discovery-stm32f072 */
+	int interface = 1; /* gpio interface */
 
-	if (!(argc == 2 && strcmp(argv[1], "read")  == 0) &&
+	if (!(argc == 2 && strcmp(argv[1], "read") == 0) &&
 	    !(argc == 4 && strcmp(argv[1], "write") == 0)) {
 		puts("Usage: usb_gpio read\n"
 		     "       usb_gpio write <set_mask> <clear_mask>\n");
@@ -122,15 +106,12 @@ int main(int argc, char **argv)
 
 	CHECK(libusb_init(&context));
 
-	device = libusb_open_device_with_vid_pid(context,
-						 vendor_id,
-						 product_id);
+	device =
+		libusb_open_device_with_vid_pid(context, vendor_id, product_id);
 
 	if (device == NULL) {
-		fprintf(stderr,
-			"Unable to find device 0x%04x:0x%04x\n",
-			vendor_id,
-			product_id);
+		fprintf(stderr, "Unable to find device 0x%04x:0x%04x\n",
+			vendor_id, product_id);
 		return 1;
 	}
 
@@ -146,7 +127,7 @@ int main(int argc, char **argv)
 	}
 
 	if (argc == 4 && strcmp(argv[1], "write") == 0) {
-		uint32_t set_mask   = strtol(argv[2], NULL, 0);
+		uint32_t set_mask = strtol(argv[2], NULL, 0);
 		uint32_t clear_mask = strtol(argv[3], NULL, 0);
 
 		CHECK(gpio_write(device, set_mask, clear_mask));
diff --git a/extra/usb_power/convert_power_log_board.py b/extra/usb_power/convert_power_log_board.py
index da0750ea86..f5fb7e925d 100644
--- a/extra/usb_power/convert_power_log_board.py
+++ b/extra/usb_power/convert_power_log_board.py
@@ -1,5 +1,5 @@
 #!/usr/bin/env python
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -10,11 +10,12 @@
 # Note: This is a py2/3 compatible file.
 
 from __future__ import print_function
+
 import json
 import os
 import sys
 
-from powerlog import Spower
+from powerlog import Spower  # pylint:disable=import-error
 
 
 def fetch_records(board_file):
@@ -44,21 +45,29 @@ def write_to_file(file, sweetberry, inas):
       inas: list of inas read from board file.
     """
 
-    with open(file, 'w') as pyfile:
+    with open(file, "w") as pyfile:
 
-        pyfile.write('inas = [\n')
+        pyfile.write("inas = [\n")
 
         for rec in inas:
-            if rec['sweetberry'] != sweetberry:
+            if rec["sweetberry"] != sweetberry:
                 continue
 
             # EX : ('sweetberry', 0x40, 'SB_FW_CAM_2P8', 5.0, 1.000, 3, False),
-            channel, i2c_addr = Spower.CHMAP[rec['channel']]
-            record = ("    ('sweetberry', 0x%02x, '%s', 5.0, %f, %d, 'True')"
-                      ",\n" % (i2c_addr, rec['name'], rec['rs'], channel))
+            channel, i2c_addr = Spower.CHMAP[rec["channel"]]
+            record = (
+                "    ('sweetberry', 0x%02x, '%s', 5.0, %f, %d, 'True')"
+                ",\n"
+                % (
+                    i2c_addr,
+                    rec["name"],
+                    rec["rs"],
+                    channel,
+                )
+            )
             pyfile.write(record)
 
-        pyfile.write(']\n')
+        pyfile.write("]\n")
 
 
 def main(argv):
@@ -72,16 +81,18 @@ def main(argv):
 
     inas = fetch_records(inputf)
 
-    sweetberry = set(rec['sweetberry'] for rec in inas)
+    sweetberry = set(rec["sweetberry"] for rec in inas)
 
     if len(sweetberry) == 2:
-        print("Converting %s to %s and %s" % (inputf, basename + '_a.py',
-                                              basename + '_b.py'))
-        write_to_file(basename + '_a.py', 'A', inas)
-        write_to_file(basename + '_b.py', 'B', inas)
+        print(
+            "Converting %s to %s and %s"
+            % (inputf, basename + "_a.py", basename + "_b.py")
+        )
+        write_to_file(basename + "_a.py", "A", inas)
+        write_to_file(basename + "_b.py", "B", inas)
     else:
-        print("Converting %s to %s" % (inputf, basename + '.py'))
-        write_to_file(basename + '.py', sweetberry.pop(), inas)
+        print("Converting %s to %s" % (inputf, basename + ".py"))
+        write_to_file(basename + ".py", sweetberry.pop(), inas)
 
 
 if __name__ == "__main__":
diff --git a/extra/usb_power/convert_servo_ina.py b/extra/usb_power/convert_servo_ina.py
index 1dae2393a8..1deb75cda4 100755
--- a/extra/usb_power/convert_servo_ina.py
+++ b/extra/usb_power/convert_servo_ina.py
@@ -1,5 +1,5 @@
 #!/usr/bin/env python
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -10,67 +10,74 @@
 # Note: This is a py2/3 compatible file.
 
 from __future__ import print_function
+
 import os
 import sys
 
 
 def fetch_records(basename):
-  """Import records from servo_ina file.
+    """Import records from servo_ina file.
 
-  servo_ina files are python imports, and have a list of tuples with
-  the INA data.
-  (inatype, i2caddr, rail name, bus voltage, shunt ohms, mux, True)
+    servo_ina files are python imports, and have a list of tuples with
+    the INA data.
+    (inatype, i2caddr, rail name, bus voltage, shunt ohms, mux, True)
 
-  Args:
-    basename: python import name (filename -.py)
+    Args:
+      basename: python import name (filename -.py)
 
-  Returns:
-    list of tuples as described above.
-  """
-  ina_desc = __import__(basename)
-  return ina_desc.inas
+    Returns:
+      list of tuples as described above.
+    """
+    ina_desc = __import__(basename)
+    return ina_desc.inas
 
 
 def main(argv):
-  if len(argv) != 2:
-    print("usage:")
-    print(" %s input.py" % argv[0])
-    return
+    if len(argv) != 2:
+        print("usage:")
+        print(" %s input.py" % argv[0])
+        return
 
-  inputf = argv[1]
-  basename = os.path.splitext(inputf)[0]
-  outputf = basename + '.board'
-  outputs = basename + '.scenario'
+    inputf = argv[1]
+    basename = os.path.splitext(inputf)[0]
+    outputf = basename + ".board"
+    outputs = basename + ".scenario"
 
-  print("Converting %s to %s, %s" % (inputf, outputf, outputs))
+    print("Converting %s to %s, %s" % (inputf, outputf, outputs))
 
-  inas = fetch_records(basename)
+    inas = fetch_records(basename)
 
+    boardfile = open(outputf, "w")
+    scenario = open(outputs, "w")
 
-  boardfile = open(outputf, 'w')
-  scenario = open(outputs, 'w')
+    boardfile.write("[\n")
+    scenario.write("[\n")
+    start = True
 
-  boardfile.write('[\n')
-  scenario.write('[\n')
-  start = True
+    for rec in inas:
+        if start:
+            start = False
+        else:
+            boardfile.write(",\n")
+            scenario.write(",\n")
 
-  for rec in inas:
-    if start:
-      start = False
-    else:
-      boardfile.write(',\n')
-      scenario.write(',\n')
+        record = (
+            '  {"name": "%s", "rs": %f, "sweetberry": "A", "channel": %d}'
+            % (
+                rec[2],
+                rec[4],
+                rec[1] - 64,
+            )
+        )
+        boardfile.write(record)
+        scenario.write('"%s"' % rec[2])
 
-    record = '  {"name": "%s", "rs": %f, "sweetberry": "A", "channel": %d}' % (
-             rec[2], rec[4], rec[1] - 64)
-    boardfile.write(record)
-    scenario.write('"%s"' % rec[2])
+    boardfile.write("\n")
+    boardfile.write("]")
 
-  boardfile.write('\n')
-  boardfile.write(']')
+    scenario.write("\n")
+    scenario.write("]")
 
-  scenario.write('\n')
-  scenario.write(']')
 
 if __name__ == "__main__":
-  main(sys.argv)
+    main(sys.argv)
diff --git a/extra/usb_power/powerlog.README.md b/extra/usb_power/powerlog.README.md
index a5ce379670..0f8a6025d2 100644
--- a/extra/usb_power/powerlog.README.md
+++ b/extra/usb_power/powerlog.README.md
@@ -9,57 +9,58 @@ this session, a `.scenario` file.
 
 ## Converting from servo_ina configs
 
-- Method 1 (not limited to chroot)
+-   Method 1 (not limited to chroot)
 
-  Many configs can be found for the servo_ina_board in `hdctools/servo/data/`.
-  Sweetberry is plug compatible with servo_ina headers, and config files can be
-  converted with the following tool:
+    Many configs can be found for the servo_ina_board in `hdctools/servo/data/`.
+    Sweetberry is plug compatible with servo_ina headers, and config files can
+    be converted with the following tool:
 
-  ```
-  ./convert_servo_ina.py <board>_r0_loc.py
-  ```
+    ```
+    ./convert_servo_ina.py <board>_r0_loc.py
+    ```
 
-  This will generate `<board>_r0_loc.board` and `<board>_r0_loc.scenario`
-  locally, which can be used with `powerlog.py`.
+    This will generate `<board>_r0_loc.board` and `<board>_r0_loc.scenario`
+    locally, which can be used with `powerlog.py`.
 
-- Method 2 (recommended for Chrome OS developers, requires chroot)
+-   Method 2 (recommended for Chrome OS developers, requires chroot)
 
-  If you are using `powerlog.py` within the chroot, copy `<board>_r0_loc.py` to
-  `src/third_party/hdctools/servo/data`, then add this line to file:
+    If you are using `powerlog.py` within the chroot, copy `<board>_r0_loc.py`
+    to `src/third_party/hdctools/servo/data`, then add this line to file:
 
-  ```python
-  config_type = 'sweetberry'
-  ```
+    ```python
+    config_type = 'sweetberry'
+    ```
 
-  And run command in chroot:
+    And run command in chroot:
 
-  ```
-  (Anywhere in chroot, just ONCE) cros_workon --host start dev-util/hdctools
-  ```
+    ```
+    (Anywhere in chroot, just ONCE) cros_workon --host start dev-util/hdctools
+    ```
 
-  Then every time you make a change to `<board>_r0_loc.py`, run:
+    Then every time you make a change to `<board>_r0_loc.py`, run:
 
-  ```
-  (Anywhere in chroot) sudo emerge dev-util/hdctools
-  ```
+    ```
+    (Anywhere in chroot) sudo emerge dev-util/hdctools
+    ```
 
-  The command will install the corresponding `.board` and `.scenario` file in
-  the chroot. To use `powerlog.py` use the command:
+    The command will install the corresponding `.board` and `.scenario` file in
+    the chroot. To use `powerlog.py` use the command:
 
-  ```
-  (Anywhere in chroot) powerlog -b <board>_r0_loc.board -c <board>_r0_loc.scenario
-  ```
+    ```
+    (Anywhere in chroot) sudo powerlog -b <board>_r0_loc.board -c <board>_r0_loc.scenario
+    ```
 
-  There is no need to specify the absolute path to the `.board` and `.scenario`
-  file, once they are installed into the chroot. If there is any changes to
-  `<board>_r0_loc.py`, you need to `sudo emerge dev-util/hdctools` again.
+    There is no need to specify the absolute path to the `.board` and
+    `.scenario` file, once they are installed into the chroot. If there is any
+    changes to `<board>_r0_loc.py`, you need to `sudo emerge dev-util/hdctools`
+    again.
 
 ## Board files
 
 Board files contain a list of rails, supporting 48 channels each on up to two
 Sweetberries. For each rail you must specify a name, sense resistor value, and
-channel number. You can optionally list expected voltage and net name.
-The format is as follows, in json:
+channel number. You can optionally list expected voltage and net name. The
+format is as follows, in json:
 
 example.board:
 
@@ -81,9 +82,8 @@ example.board:
 Scenario files contain the set of rails to monitor in this session. The file
 format is simply a list of rail names from the board file.
 
-Optionally, you can specify the type of measurement, from the set of
-`"POWER"`, `"BUSV"`, `"CURRENT"`, `"SHUNTV"`. If not specified, the default is
-power.
+Optionally, you can specify the type of measurement, from the set of `"POWER"`,
+`"BUSV"`, `"CURRENT"`, `"SHUNTV"`. If not specified, the default is power.
 
 example.scenario:
 
@@ -109,93 +109,90 @@ An example run of:
 ./powerlog.py -b board/marlin/marlin.board -c board/marlin/marlin_short.scenario -t 100000
 ```
 
-Will result in:
-```
-ts:32976us, VBAT uW, VDD_MEM uW, VDD_CORE uW, VDD_GFX uW, VDD_1V8_PANEL uW
-0.033004, 12207.03, 4882.81, 9155.27, 2441.41, 0.00
-0.066008, 12207.03, 3662.11, 9155.27, 2441.41, 0.00
-0.099012, 12207.03, 3662.11, 9155.27, 2441.41, 0.00
-...
-```
+Will result in: `ts:32976us, VBAT uW, VDD_MEM uW, VDD_CORE uW, VDD_GFX uW,
+VDD_1V8_PANEL uW 0.033004, 12207.03, 4882.81, 9155.27, 2441.41, 0.00 0.066008,
+12207.03, 3662.11, 9155.27, 2441.41, 0.00 0.099012, 12207.03, 3662.11, 9155.27,
+2441.41, 0.00 ...`
 
 The output format is as follows:
 
-- `ts:32976us`
+-   `ts:32976us`
 
-  Timestamps either zero based or synced to system clock, in seconds. The column
-  header indicates the selected sampling interval. Since the INA231 has specific
-  hardware defines sampling options, this will be the closest supported option
-  lower than the requested `-t` value on the command line.
+    Timestamps either zero based or synced to system clock, in seconds. The
+    column header indicates the selected sampling interval. Since the INA231 has
+    specific hardware defines sampling options, this will be the closest
+    supported option lower than the requested `-t` value on the command line.
 
-- `VBAT uW`
+-   `VBAT uW`
 
-  Microwatt reading from this rail, generated on the INA by integrating the
-  voltage/amperage on the sense resistor over the sampling time, and multiplying
-  by the sampled bus voltage.
+    Microwatt reading from this rail, generated on the INA by integrating the
+    voltage/amperage on the sense resistor over the sampling time, and
+    multiplying by the sampled bus voltage.
 
-- `... uW`
+-   `... uW`
 
-  Further microwatt entry columns for each rail specified in your scenario file.
+    Further microwatt entry columns for each rail specified in your scenario
+    file.
 
-- `... xX`
+-   `... xX`
 
-  Measurement in uW, mW, mV, uA, uV as per config.
+    Measurement in uW, mW, mV, uA, uV as per config.
 
 ## Calculate stats and store data and stats
 
 When appropriate flag is set, powerlog.py is capable of calculating statistics
 and storing statistics and raw data.
 
-- Example 1
+-   Example 1
 
-  ```
-  ./powerlog.py -b board/eve_dvt2_loc/eve_dvt2_loc.board -c board/eve_dvt2_loc/eve_dvt2_loc.scenario --save_stats [<directory>]
-  ```
+    ```
+    ./powerlog.py -b board/eve_dvt2_loc/eve_dvt2_loc.board -c board/eve_dvt2_loc/eve_dvt2_loc.scenario --save_stats [<directory>]
+    ```
 
-  If `<directory>` is specified, this will save stats as:
-  `<directory>/sweetberry<timestemp>/summary.txt`.
-  If `<directory>` does not exist, it will be created.
+    If `<directory>` is specified, this will save stats as:
+    `<directory>/sweetberry<timestamp>/summary.txt`. If `<directory>` does not
+    exist, it will be created.
 
-  If `<directory>` is not specified but the flag is set, this will save stats
-  under the directory which `powerlog.py` is in:
-  `<directory of powerlog.py>/sweetberry<timestemp>/summary.txt`.
+    If `<directory>` is not specified but the flag is set, this will save stats
+    under the directory which `powerlog.py` is in: `<directory of
+    powerlog.py>/sweetberry<timestamp>/summary.txt`.
 
-  If `--save_stats` flag is not set, stats will not be saved.
+    If `--save_stats` flag is not set, stats will not be saved.
 
-- Example 2
+-   Example 2
 
-  ```
-  ./powerlog.py -b board/eve_dvt2_loc/eve_dvt2_loc.board -c board/eve_dvt2_loc/eve_dvt2_loc.scenario --save_raw_data [<directory>]
-  ```
+    ```
+    ./powerlog.py -b board/eve_dvt2_loc/eve_dvt2_loc.board -c board/eve_dvt2_loc/eve_dvt2_loc.scenario --save_raw_data [<directory>]
+    ```
 
-  If `<directory>` is specified, this will save raw data in:
-  `<directory>/sweetberry<timestemp>/raw_data/`.
-  If `<directory>` does not exist, it will be created.
+    If `<directory>` is specified, this will save raw data in:
+    `<directory>/sweetberry<timestamp>/raw_data/`. If `<directory>` does not
+    exist, it will be created.
 
-  If `<directory>` is not specified but the flag is set, this will save raw data
-  under the directory which `powerlog.py` is in:
-  `<directory of powerlog.py>/sweetberry<timestemp>/raw_data/`.
+    If `<directory>` is not specified but the flag is set, this will save raw
+    data under the directory which `powerlog.py` is in: `<directory of
+    powerlog.py>/sweetberry<timestamp>/raw_data/`.
 
-  If `--save_raw_data` flag is not set, raw data will not be saved.
+    If `--save_raw_data` flag is not set, raw data will not be saved.
 
-- Example 3:
+-   Example 3:
 
-  ```
-  ./powerlog.py -b board/eve_dvt2_loc/eve_dvt2_loc.board -c board/eve_dvt2_loc/eve_dvt2_loc.scenario --save_stats_json [<directory>]
-  ```
+    ```
+    ./powerlog.py -b board/eve_dvt2_loc/eve_dvt2_loc.board -c board/eve_dvt2_loc/eve_dvt2_loc.scenario --save_stats_json [<directory>]
+    ```
 
-  If `<directory>` is specified, this will save MEANS in json as:
-  `<directory>/sweetberry<timestemp>/summary.json`.
-  If `<directory>` does not exist, it will be created.
+    If `<directory>` is specified, this will save MEANS in json as:
+    `<directory>/sweetberry<timestamp>/summary.json`. If `<directory>` does not
+    exist, it will be created.
 
-  If `<directory>` is not specified but the flag is set, this will save MEANS in
-  json under the directory which `powerlog.py` is in:
-  `<directory of powerlog.py>/sweetberry<timestemp>/summary.json`.
+    If `<directory>` is not specified but the flag is set, this will save MEANS
+    in json under the directory which `powerlog.py` is in: `<directory of
+    powerlog.py>/sweetberry<timestamp>/summary.json`.
 
-  If `--save_stats` flag is not set, stats will not be saved.
+    If `--save_stats` flag is not set, stats will not be saved.
 
-  `--save_stats_json` is designed for `power_telemetry_logger` for easy reading
-  and writing.
+    `--save_stats_json` is designed for `power_telemetry_logger` for easy
+    reading and writing.
 
 ## Making developer changes to `powerlog.py`
 
diff --git a/extra/usb_power/powerlog.py b/extra/usb_power/powerlog.py
index c7fe7477a7..ded8d83215 100755
--- a/extra/usb_power/powerlog.py
+++ b/extra/usb_power/powerlog.py
@@ -1,5 +1,5 @@
 #!/usr/bin/env python
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -10,6 +10,7 @@
 # Note: This is a py2/3 compatible file.
 
 from __future__ import print_function
+
 import argparse
 import array
 from distutils import sysconfig
@@ -22,883 +23,1040 @@
 import time
 import traceback
 
-import usb
+from stats_manager import StatsManager  # pylint:disable=import-error
+import usb  # pylint:disable=import-error
 
-from stats_manager import StatsManager
 
 # Directory where hdctools installs configuration files into.
-LIB_DIR = os.path.join(sysconfig.get_python_lib(standard_lib=False), 'servo',
-                       'data')
+LIB_DIR = os.path.join(
+    sysconfig.get_python_lib(standard_lib=False), "servo", "data"
+)
 
 # Potential config file locations: current working directory, the same directory
 # as powerlog.py file or LIB_DIR.
-CONFIG_LOCATIONS = [os.getcwd(), os.path.dirname(os.path.realpath(__file__)),
-                    LIB_DIR]
-
-def logoutput(msg):
-  print(msg)
-  sys.stdout.flush()
-
-def process_filename(filename):
-  """Find the file path from the filename.
-
-  If filename is already the complete path, return that directly. If filename is
-  just the short name, look for the file in the current working directory, in
-  the directory of the current .py file, and then in the directory installed by
-  hdctools. If the file is found, return the complete path of the file.
-
-  Args:
-      filename: complete file path or short file name.
-
-  Returns:
-      a complete file path.
-
-  Raises:
-      IOError if filename does not exist.
-  """
-  # Check if filename is absolute path.
-  if os.path.isabs(filename) and os.path.isfile(filename):
-    return filename
-  # Check if filename is relative to a known config location.
-  for dirname in CONFIG_LOCATIONS:
-    file_at_dir = os.path.join(dirname, filename)
-    if os.path.isfile(file_at_dir):
-      return file_at_dir
-  raise IOError('No such file or directory: \'%s\'' % filename)
-
-
-class Spower(object):
-  """Power class to access devices on the bus.
-
-  Usage:
-    bus = Spower()
-
-  Instance Variables:
-    _dev: pyUSB device object
-    _read_ep: pyUSB read endpoint for this interface
-    _write_ep: pyUSB write endpoint for this interface
-  """
-
-  # INA interface type.
-  INA_POWER     = 1
-  INA_BUSV      = 2
-  INA_CURRENT   = 3
-  INA_SHUNTV    = 4
-  # INA_SUFFIX is used to differentiate multiple ina types for the same power
-  # rail. No suffix for when ina type is 0 (non-existent) and when ina type is 1
-  # (power, no suffix for backward compatibility).
-  INA_SUFFIX      = ['', '', '_busv', '_cur', '_shuntv']
-
-  # usb power commands
-  CMD_RESET   = 0x0000
-  CMD_STOP    = 0x0001
-  CMD_ADDINA  = 0x0002
-  CMD_START   = 0x0003
-  CMD_NEXT    = 0x0004
-  CMD_SETTIME = 0x0005
-
-  # Map between header channel number (0-47)
-  # and INA I2C bus/addr on sweetberry.
-  CHMAP = {
-	0: (3, 0x40),
-	1: (1, 0x40),
-	2: (2, 0x40),
-	3: (0, 0x40),
-	4: (3, 0x41),
-	5: (1, 0x41),
-	6: (2, 0x41),
-	7: (0, 0x41),
-	8: (3, 0x42),
-	9: (1, 0x42),
-	10: (2, 0x42),
-	11: (0, 0x42),
-	12: (3, 0x43),
-	13: (1, 0x43),
-	14: (2, 0x43),
-	15: (0, 0x43),
-	16: (3, 0x44),
-	17: (1, 0x44),
-	18: (2, 0x44),
-	19: (0, 0x44),
-	20: (3, 0x45),
-	21: (1, 0x45),
-	22: (2, 0x45),
-	23: (0, 0x45),
-	24: (3, 0x46),
-	25: (1, 0x46),
-	26: (2, 0x46),
-	27: (0, 0x46),
-	28: (3, 0x47),
-	29: (1, 0x47),
-	30: (2, 0x47),
-	31: (0, 0x47),
-	32: (3, 0x48),
-	33: (1, 0x48),
-	34: (2, 0x48),
-	35: (0, 0x48),
-	36: (3, 0x49),
-	37: (1, 0x49),
-	38: (2, 0x49),
-	39: (0, 0x49),
-	40: (3, 0x4a),
-	41: (1, 0x4a),
-	42: (2, 0x4a),
-	43: (0, 0x4a),
-	44: (3, 0x4b),
-	45: (1, 0x4b),
-	46: (2, 0x4b),
-	47: (0, 0x4b),
-  }
-
-  def __init__(self, board, vendor=0x18d1,
-               product=0x5020, interface=1, serialname=None):
-    self._logger = logging.getLogger(__name__)
-    self._board = board
-
-    # Find the stm32.
-    dev_g = usb.core.find(idVendor=vendor, idProduct=product, find_all=True)
-    dev_list = list(dev_g)
-    if dev_list is None:
-      raise Exception("Power", "USB device not found")
-
-    # Check if we have multiple stm32s and we've specified the serial.
-    dev = None
-    if serialname:
-      for d in dev_list:
-        dev_serial = "PyUSB dioesn't have a stable interface"
-        try:
-          dev_serial = usb.util.get_string(d, 256, d.iSerialNumber)
-        except ValueError:
-          # Incompatible pyUsb version.
-          dev_serial = usb.util.get_string(d, d.iSerialNumber)
-        if dev_serial == serialname:
-          dev = d
-          break
-      if dev is None:
-        raise Exception("Power", "USB device(%s) not found" % serialname)
-    else:
-      try:
-        dev = dev_list[0]
-      except TypeError:
-        # Incompatible pyUsb version.
-        dev = dev_list.next()
-
-    self._logger.debug("Found USB device: %04x:%04x", vendor, product)
-    self._dev = dev
-
-    # Get an endpoint instance.
-    try:
-      dev.set_configuration()
-    except usb.USBError:
-      pass
-    cfg = dev.get_active_configuration()
-
-    intf = usb.util.find_descriptor(cfg, custom_match=lambda i: \
-        i.bInterfaceClass==255 and i.bInterfaceSubClass==0x54)
-
-    self._intf = intf
-    self._logger.debug("InterfaceNumber: %s", intf.bInterfaceNumber)
-
-    read_ep = usb.util.find_descriptor(
-      intf,
-      # match the first IN endpoint
-      custom_match = \
-      lambda e: \
-          usb.util.endpoint_direction(e.bEndpointAddress) == \
-          usb.util.ENDPOINT_IN
-    )
-
-    self._read_ep = read_ep
-    self._logger.debug("Reader endpoint: 0x%x", read_ep.bEndpointAddress)
-
-    write_ep = usb.util.find_descriptor(
-      intf,
-      # match the first OUT endpoint
-      custom_match = \
-      lambda e: \
-          usb.util.endpoint_direction(e.bEndpointAddress) == \
-          usb.util.ENDPOINT_OUT
-    )
-
-    self._write_ep = write_ep
-    self._logger.debug("Writer endpoint: 0x%x", write_ep.bEndpointAddress)
-
-    self.clear_ina_struct()
-
-    self._logger.debug("Found power logging USB endpoint.")
-
-  def clear_ina_struct(self):
-    """ Clear INA description struct."""
-    self._inas = []
-
-  def append_ina_struct(self, name, rs, port, addr,
-                        data=None, ina_type=INA_POWER):
-    """Add an INA descriptor into the list of active INAs.
-
-    Args:
-      name:	Readable name of this channel.
-      rs:	Sense resistor value in ohms, floating point.
-      port:	I2C channel this INA is connected to.
-      addr: 	I2C addr of this INA.
-      data:	Misc data for special handling, board specific.
-      ina_type: INA function to use, power, voltage, etc.
-    """
-    ina = {}
-    ina['name'] = name
-    ina['rs'] = rs
-    ina['port'] = port
-    ina['addr'] = addr
-    ina['type'] = ina_type
-    # Calculate INA231 Calibration register
-    # (see INA231 spec p.15)
-    # CurrentLSB = uA per div = 80mV / (Rsh * 2^15)
-    # CurrentLSB uA = 80000000nV / (Rsh mOhm * 0x8000)
-    ina['uAscale'] = 80000000. / (rs * 0x8000);
-    ina['uWscale'] = 25. * ina['uAscale'];
-    ina['mVscale'] = 1.25
-    ina['uVscale'] = 2.5
-    ina['data'] = data
-    self._inas.append(ina)
-
-  def wr_command(self, write_list, read_count=1, wtimeout=100, rtimeout=1000):
-    """Write command to logger logic.
-
-    This function writes byte command values list to stm, then reads
-    byte status.
-
-    Args:
-      write_list: list of command byte values [0~255].
-      read_count: number of status byte values to read.
-
-    Interface:
-      write: [command, data ... ]
-      read: [status ]
-
-    Returns:
-      bytes read, or None on failure.
-    """
-    self._logger.debug("Spower.wr_command(write_list=[%s] (%d), read_count=%s)",
-                       list(bytearray(write_list)), len(write_list), read_count)
-
-    # Clean up args from python style to correct types.
-    write_length = 0
-    if write_list:
-      write_length = len(write_list)
-    if not read_count:
-      read_count = 0
-
-    # Send command to stm32.
-    if write_list:
-      cmd = write_list
-      ret = self._write_ep.write(cmd, wtimeout)
-
-    self._logger.debug("RET: %s ", ret)
-
-    # Read back response if necessary.
-    if read_count:
-      bytesread = self._read_ep.read(512, rtimeout)
-      self._logger.debug("BYTES: [%s]", bytesread)
-
-      if len(bytesread) != read_count:
-        pass
-
-      self._logger.debug("STATUS: 0x%02x", int(bytesread[0]))
-      if read_count == 1:
-        return bytesread[0]
-      else:
-        return bytesread
-
-    return None
-
-  def clear(self):
-    """Clear pending reads on the stm32"""
-    try:
-      while True:
-        ret = self.wr_command(b"", read_count=512, rtimeout=100, wtimeout=50)
-        self._logger.debug("Try Clear: read %s",
-                           "success" if ret == 0 else "failure")
-    except:
-      pass
-
-  def send_reset(self):
-    """Reset the power interface on the stm32"""
-    cmd = struct.pack("<H", self.CMD_RESET)
-    ret = self.wr_command(cmd, rtimeout=50, wtimeout=50)
-    self._logger.debug("Command RESET: %s",
-                       "success" if ret == 0 else "failure")
-
-  def reset(self):
-    """Try resetting the USB interface until success.
-
-    Use linear back off strategy when encounter the error with 10ms increment.
+CONFIG_LOCATIONS = [
+    os.getcwd(),
+    os.path.dirname(os.path.realpath(__file__)),
+    LIB_DIR,
+]
 
-    Raises:
-      Exception on failure.
-    """
-    max_reset_retry = 100
-    for count in range(1, max_reset_retry + 1):
-      self.clear()
-      try:
-        self.send_reset()
-        return
-      except Exception as e:
-        self.clear()
-        self.clear()
-        self._logger.debug("TRY %d of %d: %s", count, max_reset_retry, e)
-        time.sleep(count * 0.01)
-    raise Exception("Power", "Failed to reset")
-
-  def stop(self):
-    """Stop any active data acquisition."""
-    cmd = struct.pack("<H", self.CMD_STOP)
-    ret = self.wr_command(cmd)
-    self._logger.debug("Command STOP: %s",
-                       "success" if ret == 0 else "failure")
-
-  def start(self, integration_us):
-    """Start data acquisition.
 
-    Args:
-      integration_us: int, how many us between samples, and
-                      how often the data block must be read.
+def logoutput(msg):
+    print(msg)
+    sys.stdout.flush()
 
-    Returns:
-      actual sampling interval in ms.
-    """
-    cmd = struct.pack("<HI", self.CMD_START, integration_us)
-    read = self.wr_command(cmd, read_count=5)
-    actual_us = 0
-    if len(read) == 5:
-      ret, actual_us = struct.unpack("<BI", read)
-      self._logger.debug("Command START: %s %dus",
-               "success" if ret == 0 else "failure", actual_us)
-    else:
-      self._logger.debug("Command START: FAIL")
 
-    return actual_us
+def process_filename(filename):
+    """Find the file path from the filename.
 
-  def add_ina_name(self, name_tuple):
-    """Add INA from board config.
+    If filename is already the complete path, return that directly. If filename is
+    just the short name, look for the file in the current working directory, in
+    the directory of the current .py file, and then in the directory installed by
+    hdctools. If the file is found, return the complete path of the file.
 
     Args:
-      name_tuple:	name and type of power rail in board config.
+        filename: complete file path or short file name.
 
     Returns:
-      True if INA added, False if the INA is not on this board.
+        a complete file path.
 
     Raises:
-      Exception on unexpected failure.
-    """
-    name, ina_type = name_tuple
-
-    for datum in self._brdcfg:
-      if datum["name"] == name:
-        rs = int(float(datum["rs"]) * 1000.)
-        board = datum["sweetberry"]
-
-        if board == self._board:
-          if 'port' in datum and 'addr' in datum:
-            port = datum['port']
-            addr = datum['addr']
-          else:
-            channel = int(datum["channel"])
-            port, addr = self.CHMAP[channel]
-          self.add_ina(port, ina_type, addr, 0, rs, data=datum)
-          return True
-        else:
-          return False
-    raise Exception("Power", "Failed to find INA %s" % name)
-
-  def set_time(self, timestamp_us):
-    """Set sweetberry time to match host time.
-
-    Args:
-      timestamp_us: host timestmap in us.
+        IOError if filename does not exist.
     """
-    # 0x0005 , 8 byte timestamp
-    cmd = struct.pack("<HQ", self.CMD_SETTIME, timestamp_us)
-    ret = self.wr_command(cmd)
+    # Check if filename is absolute path.
+    if os.path.isabs(filename) and os.path.isfile(filename):
+        return filename
+    # Check if filename is relative to a known config location.
+    for dirname in CONFIG_LOCATIONS:
+        file_at_dir = os.path.join(dirname, filename)
+        if os.path.isfile(file_at_dir):
+            return file_at_dir
+    raise IOError("No such file or directory: '%s'" % filename)
 
-    self._logger.debug("Command SETTIME: %s",
-                       "success" if ret == 0 else "failure")
 
-  def add_ina(self, bus, ina_type, addr, extra, resistance, data=None):
-    """Add an INA to the data acquisition list.
+class Spower(object):
+    """Power class to access devices on the bus.
 
-    Args:
-      bus: which i2c bus the INA is on. Same ordering as Si2c.
-      ina_type: Ina interface: INA_POWER/BUSV/etc.
-      addr: 7 bit i2c addr of this INA
-      extra: extra data for nonstandard configs.
-      resistance: int, shunt resistance in mOhm
-    """
-    # 0x0002, 1B: bus, 1B:INA type, 1B: INA addr, 1B: extra, 4B: Rs
-    cmd = struct.pack("<HBBBBI", self.CMD_ADDINA,
-                      bus, ina_type, addr, extra, resistance)
-    ret = self.wr_command(cmd)
-    if ret == 0:
-      if data:
-        name = data['name']
-      else:
-        name = "ina%d_%02x" % (bus, addr)
-      self.append_ina_struct(name, resistance, bus, addr,
-                             data=data, ina_type=ina_type)
-    self._logger.debug("Command ADD_INA: %s",
-                       "success" if ret == 0 else "failure")
-
-  def report_header_size(self):
-    """Helper function to calculate power record header size."""
-    result = 2
-    timestamp = 8
-    return result + timestamp
-
-  def report_size(self, ina_count):
-    """Helper function to calculate full power record size."""
-    record = 2
-
-    datasize = self.report_header_size() + ina_count * record
-    # Round to multiple of 4 bytes.
-    datasize = int(((datasize + 3) // 4) * 4)
-
-    return datasize
-
-  def read_line(self):
-    """Read a line of data from the setup INAs
+    Usage:
+      bus = Spower()
 
-    Returns:
-      list of dicts of the values read by ina/type tuple, otherwise None.
-      [{ts:100, (vbat, power):450}, {ts:200, (vbat, power):440}]
+    Instance Variables:
+      _dev: pyUSB device object
+      _read_ep: pyUSB read endpoint for this interface
+      _write_ep: pyUSB write endpoint for this interface
     """
-    try:
-      expected_bytes = self.report_size(len(self._inas))
-      cmd = struct.pack("<H", self.CMD_NEXT)
-      bytesread = self.wr_command(cmd, read_count=expected_bytes)
-    except usb.core.USBError as e:
-      self._logger.error("READ LINE FAILED %s", e)
-      return None
-
-    if len(bytesread) == 1:
-      if bytesread[0] != 0x6:
-        self._logger.debug("READ LINE FAILED bytes: %d ret: %02x",
-                           len(bytesread), bytesread[0])
-      return None
-
-    if len(bytesread) % expected_bytes != 0:
-      self._logger.debug("READ LINE WARNING: expected %d, got %d",
-          expected_bytes, len(bytesread))
-
-    packet_count = len(bytesread) // expected_bytes
-
-    values = []
-    for i in range(0, packet_count):
-      start = i * expected_bytes
-      end = (i + 1) * expected_bytes
-      record = self.interpret_line(bytesread[start:end])
-      values.append(record)
-
-    return values
-
-  def interpret_line(self, data):
-    """Interpret a power record from INAs
 
-    Args:
-      data: one single record of bytes.
+    # INA interface type.
+    INA_POWER = 1
+    INA_BUSV = 2
+    INA_CURRENT = 3
+    INA_SHUNTV = 4
+    # INA_SUFFIX is used to differentiate multiple ina types for the same power
+    # rail. No suffix for when ina type is 0 (non-existent) and when ina type is 1
+    # (power, no suffix for backward compatibility).
+    INA_SUFFIX = ["", "", "_busv", "_cur", "_shuntv"]
+
+    # usb power commands
+    CMD_RESET = 0x0000
+    CMD_STOP = 0x0001
+    CMD_ADDINA = 0x0002
+    CMD_START = 0x0003
+    CMD_NEXT = 0x0004
+    CMD_SETTIME = 0x0005
+
+    # Map between header channel number (0-47)
+    # and INA I2C bus/addr on sweetberry.
+    CHMAP = {
+        0: (3, 0x40),
+        1: (1, 0x40),
+        2: (2, 0x40),
+        3: (0, 0x40),
+        4: (3, 0x41),
+        5: (1, 0x41),
+        6: (2, 0x41),
+        7: (0, 0x41),
+        8: (3, 0x42),
+        9: (1, 0x42),
+        10: (2, 0x42),
+        11: (0, 0x42),
+        12: (3, 0x43),
+        13: (1, 0x43),
+        14: (2, 0x43),
+        15: (0, 0x43),
+        16: (3, 0x44),
+        17: (1, 0x44),
+        18: (2, 0x44),
+        19: (0, 0x44),
+        20: (3, 0x45),
+        21: (1, 0x45),
+        22: (2, 0x45),
+        23: (0, 0x45),
+        24: (3, 0x46),
+        25: (1, 0x46),
+        26: (2, 0x46),
+        27: (0, 0x46),
+        28: (3, 0x47),
+        29: (1, 0x47),
+        30: (2, 0x47),
+        31: (0, 0x47),
+        32: (3, 0x48),
+        33: (1, 0x48),
+        34: (2, 0x48),
+        35: (0, 0x48),
+        36: (3, 0x49),
+        37: (1, 0x49),
+        38: (2, 0x49),
+        39: (0, 0x49),
+        40: (3, 0x4A),
+        41: (1, 0x4A),
+        42: (2, 0x4A),
+        43: (0, 0x4A),
+        44: (3, 0x4B),
+        45: (1, 0x4B),
+        46: (2, 0x4B),
+        47: (0, 0x4B),
+    }
+
+    def __init__(
+        self, board, vendor=0x18D1, product=0x5020, interface=1, serialname=None
+    ):
+        self._logger = logging.getLogger(__name__)
+        self._board = board
+
+        # Find the stm32.
+        dev_g = usb.core.find(idVendor=vendor, idProduct=product, find_all=True)
+        dev_list = list(dev_g)
+        if dev_list is None:
+            raise Exception("Power", "USB device not found")
+
+        # Check if we have multiple stm32s and we've specified the serial.
+        dev = None
+        if serialname:
+            for d in dev_list:
+                dev_serial = "PyUSB dioesn't have a stable interface"
+                try:
+                    dev_serial = usb.util.get_string(d, 256, d.iSerialNumber)
+                except ValueError:
+                    # Incompatible pyUsb version.
+                    dev_serial = usb.util.get_string(d, d.iSerialNumber)
+                if dev_serial == serialname:
+                    dev = d
+                    break
+            if dev is None:
+                raise Exception(
+                    "Power", "USB device(%s) not found" % serialname
+                )
+        else:
+            dev = dev_list[0]
 
-    Output:
-      stdout of the record in csv format.
+        self._logger.debug("Found USB device: %04x:%04x", vendor, product)
+        self._dev = dev
 
-    Returns:
-      dict containing name, value of recorded data.
-    """
-    status, size = struct.unpack("<BB", data[0:2])
-    if len(data) != self.report_size(size):
-      self._logger.error("READ LINE FAILED st:%d size:%d expected:%d len:%d",
-                         status, size, self.report_size(size), len(data))
-    else:
-      pass
+        # Get an endpoint instance.
+        try:
+            dev.set_configuration()
+        except usb.USBError:
+            pass
+        cfg = dev.get_active_configuration()
+
+        intf = usb.util.find_descriptor(
+            cfg,
+            custom_match=lambda i: i.bInterfaceClass == 255
+            and i.bInterfaceSubClass == 0x54,
+        )
+
+        self._intf = intf
+        self._logger.debug("InterfaceNumber: %s", intf.bInterfaceNumber)
+
+        read_ep = usb.util.find_descriptor(
+            intf,
+            # match the first IN endpoint
+            custom_match=lambda e: usb.util.endpoint_direction(
+                e.bEndpointAddress
+            )
+            == usb.util.ENDPOINT_IN,
+        )
+
+        self._read_ep = read_ep
+        self._logger.debug("Reader endpoint: 0x%x", read_ep.bEndpointAddress)
+
+        write_ep = usb.util.find_descriptor(
+            intf,
+            # match the first OUT endpoint
+            custom_match=lambda e: usb.util.endpoint_direction(
+                e.bEndpointAddress
+            )
+            == usb.util.ENDPOINT_OUT,
+        )
+
+        self._write_ep = write_ep
+        self._logger.debug("Writer endpoint: 0x%x", write_ep.bEndpointAddress)
+
+        self.clear_ina_struct()
+
+        self._logger.debug("Found power logging USB endpoint.")
+
+    def clear_ina_struct(self):
+        """Clear INA description struct."""
+        self._inas = []
+
+    def append_ina_struct(
+        self, name, rs, port, addr, data=None, ina_type=INA_POWER
+    ):
+        """Add an INA descriptor into the list of active INAs.
+
+        Args:
+          name:	Readable name of this channel.
+          rs:	Sense resistor value in ohms, floating point.
+          port:	I2C channel this INA is connected to.
+          addr: 	I2C addr of this INA.
+          data:	Misc data for special handling, board specific.
+          ina_type: INA function to use, power, voltage, etc.
+        """
+        ina = {}
+        ina["name"] = name
+        ina["rs"] = rs
+        ina["port"] = port
+        ina["addr"] = addr
+        ina["type"] = ina_type
+        # Calculate INA231 Calibration register
+        # (see INA231 spec p.15)
+        # CurrentLSB = uA per div = 80mV / (Rsh * 2^15)
+        # CurrentLSB uA = 80000000nV / (Rsh mOhm * 0x8000)
+        ina["uAscale"] = 80000000.0 / (rs * 0x8000)
+        ina["uWscale"] = 25.0 * ina["uAscale"]
+        ina["mVscale"] = 1.25
+        ina["uVscale"] = 2.5
+        ina["data"] = data
+        self._inas.append(ina)
+
+    def wr_command(self, write_list, read_count=1, wtimeout=100, rtimeout=1000):
+        """Write command to logger logic.
+
+        This function writes byte command values list to stm, then reads
+        byte status.
+
+        Args:
+          write_list: list of command byte values [0~255].
+          read_count: number of status byte values to read.
+
+        Interface:
+          write: [command, data ... ]
+          read: [status ]
+
+        Returns:
+          bytes read, or None on failure.
+        """
+        self._logger.debug(
+            "Spower.wr_command(write_list=[%s] (%d), read_count=%s)",
+            list(bytearray(write_list)),
+            len(write_list),
+            read_count,
+        )
+
+        # Clean up args from python style to correct types.
+        write_length = 0
+        if write_list:
+            write_length = len(write_list)
+        if not read_count:
+            read_count = 0
+
+        # Send command to stm32.
+        if write_list:
+            cmd = write_list
+            ret = self._write_ep.write(cmd, wtimeout)
+
+        self._logger.debug("RET: %s ", ret)
+
+        # Read back response if necessary.
+        if read_count:
+            bytesread = self._read_ep.read(512, rtimeout)
+            self._logger.debug("BYTES: [%s]", bytesread)
+
+            if len(bytesread) != read_count:
+                pass
+
+            self._logger.debug("STATUS: 0x%02x", int(bytesread[0]))
+            if read_count == 1:
+                return bytesread[0]
+            else:
+                return bytesread
+
+        return None
+
+    def clear(self):
+        """Clear pending reads on the stm32"""
+        try:
+            while True:
+                ret = self.wr_command(
+                    b"", read_count=512, rtimeout=100, wtimeout=50
+                )
+                self._logger.debug(
+                    "Try Clear: read %s", "success" if ret == 0 else "failure"
+                )
+        except:
+            pass
+
+    def send_reset(self):
+        """Reset the power interface on the stm32"""
+        cmd = struct.pack("<H", self.CMD_RESET)
+        ret = self.wr_command(cmd, rtimeout=50, wtimeout=50)
+        self._logger.debug(
+            "Command RESET: %s", "success" if ret == 0 else "failure"
+        )
+
+    def reset(self):
+        """Try resetting the USB interface until success.
+
+        Use linear back off strategy when encounter the error with 10ms increment.
+
+        Raises:
+          Exception on failure.
+        """
+        max_reset_retry = 100
+        for count in range(1, max_reset_retry + 1):
+            self.clear()
+            try:
+                self.send_reset()
+                return
+            except Exception as e:
+                self.clear()
+                self.clear()
+                self._logger.debug(
+                    "TRY %d of %d: %s", count, max_reset_retry, e
+                )
+                time.sleep(count * 0.01)
+        raise Exception("Power", "Failed to reset")
+
+    def stop(self):
+        """Stop any active data acquisition."""
+        cmd = struct.pack("<H", self.CMD_STOP)
+        ret = self.wr_command(cmd)
+        self._logger.debug(
+            "Command STOP: %s", "success" if ret == 0 else "failure"
+        )
+
+    def start(self, integration_us):
+        """Start data acquisition.
+
+        Args:
+          integration_us: int, how many us between samples, and
+                          how often the data block must be read.
+
+        Returns:
+          actual sampling interval in ms.
+        """
+        cmd = struct.pack("<HI", self.CMD_START, integration_us)
+        read = self.wr_command(cmd, read_count=5)
+        actual_us = 0
+        if len(read) == 5:
+            ret, actual_us = struct.unpack("<BI", read)
+            self._logger.debug(
+                "Command START: %s %dus",
+                "success" if ret == 0 else "failure",
+                actual_us,
+            )
+        else:
+            self._logger.debug("Command START: FAIL")
+
+        return actual_us
+
+    def add_ina_name(self, name_tuple):
+        """Add INA from board config.
+
+        Args:
+          name_tuple:	name and type of power rail in board config.
+
+        Returns:
+          True if INA added, False if the INA is not on this board.
+
+        Raises:
+          Exception on unexpected failure.
+        """
+        name, ina_type = name_tuple
+
+        for datum in self._brdcfg:
+            if datum["name"] == name:
+                rs = int(float(datum["rs"]) * 1000.0)
+                board = datum["sweetberry"]
+
+                if board == self._board:
+                    if "port" in datum and "addr" in datum:
+                        port = datum["port"]
+                        addr = datum["addr"]
+                    else:
+                        channel = int(datum["channel"])
+                        port, addr = self.CHMAP[channel]
+                    self.add_ina(port, ina_type, addr, 0, rs, data=datum)
+                    return True
+                else:
+                    return False
+        raise Exception("Power", "Failed to find INA %s" % name)
+
+    def set_time(self, timestamp_us):
+        """Set sweetberry time to match host time.
+
+        Args:
+          timestamp_us: host timestmap in us.
+        """
+        # 0x0005 , 8 byte timestamp
+        cmd = struct.pack("<HQ", self.CMD_SETTIME, timestamp_us)
+        ret = self.wr_command(cmd)
+
+        self._logger.debug(
+            "Command SETTIME: %s", "success" if ret == 0 else "failure"
+        )
+
+    def add_ina(self, bus, ina_type, addr, extra, resistance, data=None):
+        """Add an INA to the data acquisition list.
+
+        Args:
+          bus: which i2c bus the INA is on. Same ordering as Si2c.
+          ina_type: Ina interface: INA_POWER/BUSV/etc.
+          addr: 7 bit i2c addr of this INA
+          extra: extra data for nonstandard configs.
+          resistance: int, shunt resistance in mOhm
+        """
+        # 0x0002, 1B: bus, 1B:INA type, 1B: INA addr, 1B: extra, 4B: Rs
+        cmd = struct.pack(
+            "<HBBBBI", self.CMD_ADDINA, bus, ina_type, addr, extra, resistance
+        )
+        ret = self.wr_command(cmd)
+        if ret == 0:
+            if data:
+                name = data["name"]
+            else:
+                name = "ina%d_%02x" % (bus, addr)
+            self.append_ina_struct(
+                name, resistance, bus, addr, data=data, ina_type=ina_type
+            )
+        self._logger.debug(
+            "Command ADD_INA: %s", "success" if ret == 0 else "failure"
+        )
+
+    def report_header_size(self):
+        """Helper function to calculate power record header size."""
+        result = 2
+        timestamp = 8
+        return result + timestamp
+
+    def report_size(self, ina_count):
+        """Helper function to calculate full power record size."""
+        record = 2
+
+        datasize = self.report_header_size() + ina_count * record
+        # Round to multiple of 4 bytes.
+        datasize = int(((datasize + 3) // 4) * 4)
+
+        return datasize
+
+    def read_line(self):
+        """Read a line of data from the setup INAs
+
+        Returns:
+          list of dicts of the values read by ina/type tuple, otherwise None.
+          [{ts:100, (vbat, power):450}, {ts:200, (vbat, power):440}]
+        """
+        try:
+            expected_bytes = self.report_size(len(self._inas))
+            cmd = struct.pack("<H", self.CMD_NEXT)
+            bytesread = self.wr_command(cmd, read_count=expected_bytes)
+        except usb.core.USBError as e:
+            self._logger.error("READ LINE FAILED %s", e)
+            return None
+
+        if len(bytesread) == 1:
+            if bytesread[0] != 0x6:
+                self._logger.debug(
+                    "READ LINE FAILED bytes: %d ret: %02x",
+                    len(bytesread),
+                    bytesread[0],
+                )
+            return None
+
+        if len(bytesread) % expected_bytes != 0:
+            self._logger.debug(
+                "READ LINE WARNING: expected %d, got %d",
+                expected_bytes,
+                len(bytesread),
+            )
+
+        packet_count = len(bytesread) // expected_bytes
+
+        values = []
+        for i in range(0, packet_count):
+            start = i * expected_bytes
+            end = (i + 1) * expected_bytes
+            record = self.interpret_line(bytesread[start:end])
+            values.append(record)
+
+        return values
+
+    def interpret_line(self, data):
+        """Interpret a power record from INAs
+
+        Args:
+          data: one single record of bytes.
+
+        Output:
+          stdout of the record in csv format.
+
+        Returns:
+          dict containing name, value of recorded data.
+        """
+        status, size = struct.unpack("<BB", data[0:2])
+        if len(data) != self.report_size(size):
+            self._logger.error(
+                "READ LINE FAILED st:%d size:%d expected:%d len:%d",
+                status,
+                size,
+                self.report_size(size),
+                len(data),
+            )
+        else:
+            pass
 
-    timestamp = struct.unpack("<Q", data[2:10])[0]
-    self._logger.debug("READ LINE: st:%d size:%d time:%dus", status, size,
-                       timestamp)
-    ftimestamp = float(timestamp) / 1000000.
+        timestamp = struct.unpack("<Q", data[2:10])[0]
+        self._logger.debug(
+            "READ LINE: st:%d size:%d time:%dus", status, size, timestamp
+        )
+        ftimestamp = float(timestamp) / 1000000.0
 
-    record = {"ts": ftimestamp, "status": status, "berry":self._board}
+        record = {"ts": ftimestamp, "status": status, "berry": self._board}
 
-    for i in range(0, size):
-      idx = self.report_header_size() + 2*i
-      name = self._inas[i]['name']
-      name_tuple = (self._inas[i]['name'], self._inas[i]['type'])
+        for i in range(0, size):
+            idx = self.report_header_size() + 2 * i
+            name = self._inas[i]["name"]
+            name_tuple = (self._inas[i]["name"], self._inas[i]["type"])
 
-      raw_val = struct.unpack("<h", data[idx:idx+2])[0]
+            raw_val = struct.unpack("<h", data[idx : idx + 2])[0]
 
-      if self._inas[i]['type'] == Spower.INA_POWER:
-        val = raw_val * self._inas[i]['uWscale']
-      elif self._inas[i]['type'] == Spower.INA_BUSV:
-        val = raw_val * self._inas[i]['mVscale']
-      elif self._inas[i]['type'] == Spower.INA_CURRENT:
-        val = raw_val * self._inas[i]['uAscale']
-      elif self._inas[i]['type'] == Spower.INA_SHUNTV:
-        val = raw_val * self._inas[i]['uVscale']
+            if self._inas[i]["type"] == Spower.INA_POWER:
+                val = raw_val * self._inas[i]["uWscale"]
+            elif self._inas[i]["type"] == Spower.INA_BUSV:
+                val = raw_val * self._inas[i]["mVscale"]
+            elif self._inas[i]["type"] == Spower.INA_CURRENT:
+                val = raw_val * self._inas[i]["uAscale"]
+            elif self._inas[i]["type"] == Spower.INA_SHUNTV:
+                val = raw_val * self._inas[i]["uVscale"]
 
-      self._logger.debug("READ %d %s: %fs: 0x%04x %f", i, name, ftimestamp,
-                         raw_val, val)
-      record[name_tuple] = val
+            self._logger.debug(
+                "READ %d %s: %fs: 0x%04x %f", i, name, ftimestamp, raw_val, val
+            )
+            record[name_tuple] = val
 
-    return record
+        return record
 
-  def load_board(self, brdfile):
-    """Load a board config.
+    def load_board(self, brdfile):
+        """Load a board config.
 
-    Args:
-      brdfile:	Filename of a json file decribing the INA wiring of this board.
-    """
-    with open(process_filename(brdfile)) as data_file:
-        data = json.load(data_file)
+        Args:
+          brdfile:	Filename of a json file decribing the INA wiring of this board.
+        """
+        with open(process_filename(brdfile)) as data_file:
+            data = json.load(data_file)
 
-    #TODO: validate this.
-    self._brdcfg = data;
-    self._logger.debug(pprint.pformat(data))
+        # TODO: validate this.
+        self._brdcfg = data
+        self._logger.debug(pprint.pformat(data))
 
 
 class powerlog(object):
-  """Power class to log aggregated power.
-
-  Usage:
-    obj = powerlog()
-
-  Instance Variables:
-    _data: a StatsManager object that records sweetberry readings and calculates
-           statistics.
-    _pwr[]: Spower objects for individual sweetberries.
-  """
+    """Power class to log aggregated power.
 
-  def __init__(self, brdfile, cfgfile, serial_a=None, serial_b=None,
-               sync_date=False, use_ms=False, use_mW=False, print_stats=False,
-               stats_dir=None, stats_json_dir=None, print_raw_data=True,
-               raw_data_dir=None):
-    """Init the powerlog class and set the variables.
-
-    Args:
-      brdfile: string name of json file containing board layout.
-      cfgfile: string name of json containing list of rails to read.
-      serial_a: serial number of sweetberry A.
-      serial_b: serial number of sweetberry B.
-      sync_date: report timestamps synced with host datetime.
-      use_ms: report timestamps in ms rather than us.
-      use_mW: report power as milliwatts, otherwise default to microwatts.
-      print_stats: print statistics for sweetberry readings at the end.
-      stats_dir: directory to save sweetberry readings statistics; if None then
-                 do not save the statistics.
-      stats_json_dir: directory to save means of sweetberry readings in json
-                      format; if None then do not save the statistics.
-      print_raw_data: print sweetberry readings raw data in real time, default
-                      is to print.
-      raw_data_dir: directory to save sweetberry readings raw data; if None then
-                    do not save the raw data.
-    """
-    self._logger = logging.getLogger(__name__)
-    self._data = StatsManager()
-    self._pwr = {}
-    self._use_ms = use_ms
-    self._use_mW = use_mW
-    self._print_stats = print_stats
-    self._stats_dir = stats_dir
-    self._stats_json_dir = stats_json_dir
-    self._print_raw_data = print_raw_data
-    self._raw_data_dir = raw_data_dir
-
-    if not serial_a and not serial_b:
-      self._pwr['A'] = Spower('A')
-    if serial_a:
-      self._pwr['A'] = Spower('A', serialname=serial_a)
-    if serial_b:
-      self._pwr['B'] = Spower('B', serialname=serial_b)
-
-    with open(process_filename(cfgfile)) as data_file:
-      names = json.load(data_file)
-    self._names = self.process_scenario(names)
-
-    for key in self._pwr:
-      self._pwr[key].load_board(brdfile)
-      self._pwr[key].reset()
-
-    # Allocate the rails to the appropriate boards.
-    used_boards = []
-    for name in self._names:
-      success = False
-      for key in self._pwr.keys():
-        if self._pwr[key].add_ina_name(name):
-          success = True
-          if key not in used_boards:
-            used_boards.append(key)
-      if not success:
-        raise Exception("Failed to add %s (maybe missing "
-                        "sweetberry, or bad board file?)" % name)
-
-    # Evict unused boards.
-    for key in list(self._pwr.keys()):
-      if key not in used_boards:
-        self._pwr.pop(key)
-
-    for key in self._pwr.keys():
-      if sync_date:
-        self._pwr[key].set_time(time.time() * 1000000)
-      else:
-        self._pwr[key].set_time(0)
-
-  def process_scenario(self, name_list):
-    """Return list of tuples indicating name and type.
+    Usage:
+      obj = powerlog()
 
-    Args:
-      json originated list of names, or [name, type]
-    Returns:
-      list of tuples of (name, type) defaulting to type "POWER"
-    Raises: exception, invalid INA type.
+    Instance Variables:
+      _data: a StatsManager object that records sweetberry readings and calculates
+             statistics.
+      _pwr[]: Spower objects for individual sweetberries.
     """
-    names = []
-    for entry in name_list:
-      if isinstance(entry, list):
-        name = entry[0]
-        if entry[1] == "POWER":
-          type = Spower.INA_POWER
-        elif entry[1] == "BUSV":
-          type = Spower.INA_BUSV
-        elif entry[1] == "CURRENT":
-          type = Spower.INA_CURRENT
-        elif entry[1] == "SHUNTV":
-          type = Spower.INA_SHUNTV
-        else:
-          raise Exception("Invalid INA type", "Type of %s [%s] not recognized,"
-                    " try one of POWER, BUSV, CURRENT" % (entry[0], entry[1]))
-      else:
-        name = entry
-        type = Spower.INA_POWER
 
-      names.append((name, type))
-    return names
+    def __init__(
+        self,
+        brdfile,
+        cfgfile,
+        serial_a=None,
+        serial_b=None,
+        sync_date=False,
+        use_ms=False,
+        use_mW=False,
+        print_stats=False,
+        stats_dir=None,
+        stats_json_dir=None,
+        print_raw_data=True,
+        raw_data_dir=None,
+    ):
+        """Init the powerlog class and set the variables.
+
+        Args:
+          brdfile: string name of json file containing board layout.
+          cfgfile: string name of json containing list of rails to read.
+          serial_a: serial number of sweetberry A.
+          serial_b: serial number of sweetberry B.
+          sync_date: report timestamps synced with host datetime.
+          use_ms: report timestamps in ms rather than us.
+          use_mW: report power as milliwatts, otherwise default to microwatts.
+          print_stats: print statistics for sweetberry readings at the end.
+          stats_dir: directory to save sweetberry readings statistics; if None then
+                     do not save the statistics.
+          stats_json_dir: directory to save means of sweetberry readings in json
+                          format; if None then do not save the statistics.
+          print_raw_data: print sweetberry readings raw data in real time, default
+                          is to print.
+          raw_data_dir: directory to save sweetberry readings raw data; if None then
+                        do not save the raw data.
+        """
+        self._logger = logging.getLogger(__name__)
+        self._data = StatsManager()
+        self._pwr = {}
+        self._use_ms = use_ms
+        self._use_mW = use_mW
+        self._print_stats = print_stats
+        self._stats_dir = stats_dir
+        self._stats_json_dir = stats_json_dir
+        self._print_raw_data = print_raw_data
+        self._raw_data_dir = raw_data_dir
+
+        if not serial_a and not serial_b:
+            self._pwr["A"] = Spower("A")
+        if serial_a:
+            self._pwr["A"] = Spower("A", serialname=serial_a)
+        if serial_b:
+            self._pwr["B"] = Spower("B", serialname=serial_b)
+
+        with open(process_filename(cfgfile)) as data_file:
+            names = json.load(data_file)
+        self._names = self.process_scenario(names)
 
-  def start(self, integration_us_request, seconds, sync_speed=.8):
-    """Starts sampling.
-
-    Args:
-      integration_us_request: requested interval between sample values.
-      seconds: time until exit, or None to run until cancel.
-      sync_speed: A usb request is sent every [.8] * integration_us.
-    """
-    # We will get back the actual integration us.
-    # It should be the same for all devices.
-    integration_us = None
-    for key in self._pwr:
-      integration_us_new = self._pwr[key].start(integration_us_request)
-      if integration_us:
-        if integration_us != integration_us_new:
-          raise Exception("FAIL",
-              "Integration on A: %dus != integration on B %dus" % (
-              integration_us, integration_us_new))
-      integration_us = integration_us_new
-
-    # CSV header
-    title = "ts:%dus" % integration_us
-    for name_tuple in self._names:
-      name, ina_type = name_tuple
-
-      if ina_type == Spower.INA_POWER:
-        unit = "mW" if self._use_mW else "uW"
-      elif ina_type == Spower.INA_BUSV:
-        unit = "mV"
-      elif ina_type == Spower.INA_CURRENT:
-        unit = "uA"
-      elif ina_type == Spower.INA_SHUNTV:
-        unit = "uV"
-
-      title += ", %s %s" % (name, unit)
-      name_type = name + Spower.INA_SUFFIX[ina_type]
-      self._data.SetUnit(name_type, unit)
-    title += ", status"
-    if self._print_raw_data:
-      logoutput(title)
-
-    forever = False
-    if not seconds:
-      forever = True
-    end_time = time.time() + seconds
-    try:
-      pending_records = []
-      while forever or end_time > time.time():
-        if (integration_us > 5000):
-          time.sleep((integration_us / 1000000.) * sync_speed)
         for key in self._pwr:
-          records = self._pwr[key].read_line()
-          if not records:
-            continue
-
-          for record in records:
-            pending_records.append(record)
-
-        pending_records.sort(key=lambda r: r['ts'])
-
-        aggregate_record = {"boards": set()}
-        for record in pending_records:
-          if record["berry"] not in aggregate_record["boards"]:
-            for rkey in record.keys():
-              aggregate_record[rkey] = record[rkey]
-            aggregate_record["boards"].add(record["berry"])
-          else:
-            self._logger.info("break %s, %s", record["berry"],
-                              aggregate_record["boards"])
-            break
-
-          if aggregate_record["boards"] == set(self._pwr.keys()):
-            csv = "%f" % aggregate_record["ts"]
-            for name in self._names:
-              if name in aggregate_record:
-                multiplier = 0.001 if (self._use_mW and
-                    name[1]==Spower.INA_POWER) else 1
-                value = aggregate_record[name] * multiplier
-                csv += ", %.2f" % value
-                name_type = name[0] + Spower.INA_SUFFIX[name[1]]
-                self._data.AddSample(name_type, value)
-              else:
-                csv += ", "
-            csv += ", %d" % aggregate_record["status"]
-            if self._print_raw_data:
-              logoutput(csv)
-
-            aggregate_record = {"boards": set()}
-            for r in range(0, len(self._pwr)):
-              pending_records.pop(0)
-
-    except KeyboardInterrupt:
-      self._logger.info('\nCTRL+C caught.')
-
-    finally:
-      for key in self._pwr:
-        self._pwr[key].stop()
-      self._data.CalculateStats()
-      if self._print_stats:
-        print(self._data.SummaryToString())
-      save_dir = 'sweetberry%s' % time.time()
-      if self._stats_dir:
-        stats_dir = os.path.join(self._stats_dir, save_dir)
-        self._data.SaveSummary(stats_dir)
-      if self._stats_json_dir:
-        stats_json_dir = os.path.join(self._stats_json_dir, save_dir)
-        self._data.SaveSummaryJSON(stats_json_dir)
-      if self._raw_data_dir:
-        raw_data_dir = os.path.join(self._raw_data_dir, save_dir)
-        self._data.SaveRawData(raw_data_dir)
+            self._pwr[key].load_board(brdfile)
+            self._pwr[key].reset()
+
+        # Allocate the rails to the appropriate boards.
+        used_boards = []
+        for name in self._names:
+            success = False
+            for key in self._pwr.keys():
+                if self._pwr[key].add_ina_name(name):
+                    success = True
+                    if key not in used_boards:
+                        used_boards.append(key)
+            if not success:
+                raise Exception(
+                    "Failed to add %s (maybe missing "
+                    "sweetberry, or bad board file?)" % name
+                )
+
+        # Evict unused boards.
+        for key in list(self._pwr.keys()):
+            if key not in used_boards:
+                self._pwr.pop(key)
+
+        for key in self._pwr.keys():
+            if sync_date:
+                self._pwr[key].set_time(time.time() * 1000000)
+            else:
+                self._pwr[key].set_time(0)
+
+    def process_scenario(self, name_list):
+        """Return list of tuples indicating name and type.
+
+        Args:
+          json originated list of names, or [name, type]
+        Returns:
+          list of tuples of (name, type) defaulting to type "POWER"
+        Raises: exception, invalid INA type.
+        """
+        names = []
+        for entry in name_list:
+            if isinstance(entry, list):
+                name = entry[0]
+                if entry[1] == "POWER":
+                    type = Spower.INA_POWER
+                elif entry[1] == "BUSV":
+                    type = Spower.INA_BUSV
+                elif entry[1] == "CURRENT":
+                    type = Spower.INA_CURRENT
+                elif entry[1] == "SHUNTV":
+                    type = Spower.INA_SHUNTV
+                else:
+                    raise Exception(
+                        "Invalid INA type",
+                        "Type of %s [%s] not recognized,"
+                        " try one of POWER, BUSV, CURRENT"
+                        % (entry[0], entry[1]),
+                    )
+            else:
+                name = entry
+                type = Spower.INA_POWER
+
+            names.append((name, type))
+        return names
+
+    def start(self, integration_us_request, seconds, sync_speed=0.8):
+        """Starts sampling.
+
+        Args:
+          integration_us_request: requested interval between sample values.
+          seconds: time until exit, or None to run until cancel.
+          sync_speed: A usb request is sent every [.8] * integration_us.
+        """
+        # We will get back the actual integration us.
+        # It should be the same for all devices.
+        integration_us = None
+        for key in self._pwr:
+            integration_us_new = self._pwr[key].start(integration_us_request)
+            if integration_us:
+                if integration_us != integration_us_new:
+                    raise Exception(
+                        "FAIL",
+                        # pylint:disable=bad-string-format-type
+                        "Integration on A: %dus != integration on B %dus"
+                        % (integration_us, integration_us_new),
+                    )
+            integration_us = integration_us_new
+
+        # CSV header
+        title = "ts:%dus" % integration_us
+        for name_tuple in self._names:
+            name, ina_type = name_tuple
+
+            if ina_type == Spower.INA_POWER:
+                unit = "mW" if self._use_mW else "uW"
+            elif ina_type == Spower.INA_BUSV:
+                unit = "mV"
+            elif ina_type == Spower.INA_CURRENT:
+                unit = "uA"
+            elif ina_type == Spower.INA_SHUNTV:
+                unit = "uV"
+
+            title += ", %s %s" % (name, unit)
+            name_type = name + Spower.INA_SUFFIX[ina_type]
+            self._data.SetUnit(name_type, unit)
+        title += ", status"
+        if self._print_raw_data:
+            logoutput(title)
+
+        forever = False
+        if not seconds:
+            forever = True
+        end_time = time.time() + seconds
+        try:
+            pending_records = []
+            while forever or end_time > time.time():
+                if integration_us > 5000:
+                    time.sleep((integration_us / 1000000.0) * sync_speed)
+                for key in self._pwr:
+                    records = self._pwr[key].read_line()
+                    if not records:
+                        continue
+
+                    for record in records:
+                        pending_records.append(record)
+
+                pending_records.sort(key=lambda r: r["ts"])
+
+                aggregate_record = {"boards": set()}
+                for record in pending_records:
+                    if record["berry"] not in aggregate_record["boards"]:
+                        for rkey in record.keys():
+                            aggregate_record[rkey] = record[rkey]
+                        aggregate_record["boards"].add(record["berry"])
+                    else:
+                        self._logger.info(
+                            "break %s, %s",
+                            record["berry"],
+                            aggregate_record["boards"],
+                        )
+                        break
+
+                    if aggregate_record["boards"] == set(self._pwr.keys()):
+                        csv = "%f" % aggregate_record["ts"]
+                        for name in self._names:
+                            if name in aggregate_record:
+                                multiplier = (
+                                    0.001
+                                    if (
+                                        self._use_mW
+                                        and name[1] == Spower.INA_POWER
+                                    )
+                                    else 1
+                                )
+                                value = aggregate_record[name] * multiplier
+                                csv += ", %.2f" % value
+                                name_type = name[0] + Spower.INA_SUFFIX[name[1]]
+                                self._data.AddSample(name_type, value)
+                            else:
+                                csv += ", "
+                        csv += ", %d" % aggregate_record["status"]
+                        if self._print_raw_data:
+                            logoutput(csv)
+
+                        aggregate_record = {"boards": set()}
+                        for r in range(0, len(self._pwr)):
+                            pending_records.pop(0)
+
+        except KeyboardInterrupt:
+            self._logger.info("\nCTRL+C caught.")
+
+        finally:
+            for key in self._pwr:
+                self._pwr[key].stop()
+            self._data.CalculateStats()
+            if self._print_stats:
+                print(self._data.SummaryToString())
+            save_dir = "sweetberry%s" % time.time()
+            if self._stats_dir:
+                stats_dir = os.path.join(self._stats_dir, save_dir)
+                self._data.SaveSummary(stats_dir)
+            if self._stats_json_dir:
+                stats_json_dir = os.path.join(self._stats_json_dir, save_dir)
+                self._data.SaveSummaryJSON(stats_json_dir)
+            if self._raw_data_dir:
+                raw_data_dir = os.path.join(self._raw_data_dir, save_dir)
+                self._data.SaveRawData(raw_data_dir)
 
 
 def main(argv=None):
-  if argv is None:
-    argv = sys.argv[1:]
-  # Command line argument description.
-  parser = argparse.ArgumentParser(
-      description="Gather CSV data from sweetberry")
-  parser.add_argument('-b', '--board', type=str,
-      help="Board configuration file, eg. my.board", default="")
-  parser.add_argument('-c', '--config', type=str,
-      help="Rail config to monitor, eg my.scenario", default="")
-  parser.add_argument('-A', '--serial', type=str,
-      help="Serial number of sweetberry A", default="")
-  parser.add_argument('-B', '--serial_b', type=str,
-      help="Serial number of sweetberry B", default="")
-  parser.add_argument('-t', '--integration_us', type=int,
-      help="Target integration time for samples", default=100000)
-  parser.add_argument('-s', '--seconds', type=float,
-      help="Seconds to run capture", default=0.)
-  parser.add_argument('--date', default=False,
-      help="Sync logged timestamp to host date", action="store_true")
-  parser.add_argument('--ms', default=False,
-      help="Print timestamp as milliseconds", action="store_true")
-  parser.add_argument('--mW', default=False,
-      help="Print power as milliwatts, otherwise default to microwatts",
-      action="store_true")
-  parser.add_argument('--slow', default=False,
-      help="Intentionally overflow", action="store_true")
-  parser.add_argument('--print_stats', default=False, action="store_true",
-      help="Print statistics for sweetberry readings at the end")
-  parser.add_argument('--save_stats', type=str, nargs='?',
-      dest='stats_dir', metavar='STATS_DIR',
-      const=os.path.dirname(os.path.abspath(__file__)), default=None,
-      help="Save statistics for sweetberry readings to %(metavar)s if "
-           "%(metavar)s is specified, %(metavar)s will be created if it does "
-           "not exist; if %(metavar)s is not specified but the flag is set, "
-           "stats will be saved to where %(prog)s is located; if this flag is "
-           "not set, then do not save stats")
-  parser.add_argument('--save_stats_json', type=str, nargs='?',
-      dest='stats_json_dir', metavar='STATS_JSON_DIR',
-      const=os.path.dirname(os.path.abspath(__file__)), default=None,
-      help="Save means for sweetberry readings in json to %(metavar)s if "
-           "%(metavar)s is specified, %(metavar)s will be created if it does "
-           "not exist; if %(metavar)s is not specified but the flag is set, "
-           "stats will be saved to where %(prog)s is located; if this flag is "
-           "not set, then do not save stats")
-  parser.add_argument('--no_print_raw_data',
-      dest='print_raw_data', default=True, action="store_false",
-      help="Not print raw sweetberry readings at real time, default is to "
-           "print")
-  parser.add_argument('--save_raw_data', type=str, nargs='?',
-      dest='raw_data_dir', metavar='RAW_DATA_DIR',
-      const=os.path.dirname(os.path.abspath(__file__)), default=None,
-      help="Save raw data for sweetberry readings to %(metavar)s if "
-           "%(metavar)s is specified, %(metavar)s will be created if it does "
-           "not exist; if %(metavar)s is not specified but the flag is set, "
-           "raw data will be saved to where %(prog)s is located; if this flag "
-           "is not set, then do not save raw data")
-  parser.add_argument('-v', '--verbose', default=False,
-      help="Very chatty printout", action="store_true")
-
-  args = parser.parse_args(argv)
-
-  root_logger = logging.getLogger(__name__)
-  if args.verbose:
-    root_logger.setLevel(logging.DEBUG)
-  else:
-    root_logger.setLevel(logging.INFO)
-
-  # if powerlog is used through main, log to sys.stdout
-  if __name__ == "__main__":
-    stdout_handler = logging.StreamHandler(sys.stdout)
-    stdout_handler.setFormatter(logging.Formatter('%(levelname)s: %(message)s'))
-    root_logger.addHandler(stdout_handler)
-
-  integration_us_request = args.integration_us
-  if not args.board:
-    raise Exception("Power", "No board file selected, see board.README")
-  if not args.config:
-    raise Exception("Power", "No config file selected, see board.README")
-
-  brdfile = args.board
-  cfgfile = args.config
-  seconds = args.seconds
-  serial_a = args.serial
-  serial_b = args.serial_b
-  sync_date = args.date
-  use_ms = args.ms
-  use_mW = args.mW
-  print_stats = args.print_stats
-  stats_dir = args.stats_dir
-  stats_json_dir = args.stats_json_dir
-  print_raw_data = args.print_raw_data
-  raw_data_dir = args.raw_data_dir
-
-  boards = []
-
-  sync_speed = .8
-  if args.slow:
-    sync_speed = 1.2
-
-  # Set up logging interface.
-  powerlogger = powerlog(brdfile, cfgfile, serial_a=serial_a, serial_b=serial_b,
-      sync_date=sync_date, use_ms=use_ms, use_mW=use_mW,
-      print_stats=print_stats, stats_dir=stats_dir,
-      stats_json_dir=stats_json_dir,
-      print_raw_data=print_raw_data,raw_data_dir=raw_data_dir)
-
-  # Start logging.
-  powerlogger.start(integration_us_request, seconds, sync_speed=sync_speed)
+    if argv is None:
+        argv = sys.argv[1:]
+    # Command line argument description.
+    parser = argparse.ArgumentParser(
+        description="Gather CSV data from sweetberry"
+    )
+    parser.add_argument(
+        "-b",
+        "--board",
+        type=str,
+        help="Board configuration file, eg. my.board",
+        default="",
+    )
+    parser.add_argument(
+        "-c",
+        "--config",
+        type=str,
+        help="Rail config to monitor, eg my.scenario",
+        default="",
+    )
+    parser.add_argument(
+        "-A",
+        "--serial",
+        type=str,
+        help="Serial number of sweetberry A",
+        default="",
+    )
+    parser.add_argument(
+        "-B",
+        "--serial_b",
+        type=str,
+        help="Serial number of sweetberry B",
+        default="",
+    )
+    parser.add_argument(
+        "-t",
+        "--integration_us",
+        type=int,
+        help="Target integration time for samples",
+        default=100000,
+    )
+    parser.add_argument(
+        "-s",
+        "--seconds",
+        type=float,
+        help="Seconds to run capture",
+        default=0.0,
+    )
+    parser.add_argument(
+        "--date",
+        default=False,
+        help="Sync logged timestamp to host date",
+        action="store_true",
+    )
+    parser.add_argument(
+        "--ms",
+        default=False,
+        help="Print timestamp as milliseconds",
+        action="store_true",
+    )
+    parser.add_argument(
+        "--mW",
+        default=False,
+        help="Print power as milliwatts, otherwise default to microwatts",
+        action="store_true",
+    )
+    parser.add_argument(
+        "--slow",
+        default=False,
+        help="Intentionally overflow",
+        action="store_true",
+    )
+    parser.add_argument(
+        "--print_stats",
+        default=False,
+        action="store_true",
+        help="Print statistics for sweetberry readings at the end",
+    )
+    parser.add_argument(
+        "--save_stats",
+        type=str,
+        nargs="?",
+        dest="stats_dir",
+        metavar="STATS_DIR",
+        const=os.path.dirname(os.path.abspath(__file__)),
+        default=None,
+        help="Save statistics for sweetberry readings to %(metavar)s if "
+        "%(metavar)s is specified, %(metavar)s will be created if it does "
+        "not exist; if %(metavar)s is not specified but the flag is set, "
+        "stats will be saved to where %(prog)s is located; if this flag is "
+        "not set, then do not save stats",
+    )
+    parser.add_argument(
+        "--save_stats_json",
+        type=str,
+        nargs="?",
+        dest="stats_json_dir",
+        metavar="STATS_JSON_DIR",
+        const=os.path.dirname(os.path.abspath(__file__)),
+        default=None,
+        help="Save means for sweetberry readings in json to %(metavar)s if "
+        "%(metavar)s is specified, %(metavar)s will be created if it does "
+        "not exist; if %(metavar)s is not specified but the flag is set, "
+        "stats will be saved to where %(prog)s is located; if this flag is "
+        "not set, then do not save stats",
+    )
+    parser.add_argument(
+        "--no_print_raw_data",
+        dest="print_raw_data",
+        default=True,
+        action="store_false",
+        help="Not print raw sweetberry readings at real time, default is to "
+        "print",
+    )
+    parser.add_argument(
+        "--save_raw_data",
+        type=str,
+        nargs="?",
+        dest="raw_data_dir",
+        metavar="RAW_DATA_DIR",
+        const=os.path.dirname(os.path.abspath(__file__)),
+        default=None,
+        help="Save raw data for sweetberry readings to %(metavar)s if "
+        "%(metavar)s is specified, %(metavar)s will be created if it does "
+        "not exist; if %(metavar)s is not specified but the flag is set, "
+        "raw data will be saved to where %(prog)s is located; if this flag "
+        "is not set, then do not save raw data",
+    )
+    parser.add_argument(
+        "-v",
+        "--verbose",
+        default=False,
+        help="Very chatty printout",
+        action="store_true",
+    )
+
+    args = parser.parse_args(argv)
+
+    root_logger = logging.getLogger(__name__)
+    if args.verbose:
+        root_logger.setLevel(logging.DEBUG)
+    else:
+        root_logger.setLevel(logging.INFO)
+
+    # if powerlog is used through main, log to sys.stdout
+    if __name__ == "__main__":
+        stdout_handler = logging.StreamHandler(sys.stdout)
+        stdout_handler.setFormatter(
+            logging.Formatter("%(levelname)s: %(message)s")
+        )
+        root_logger.addHandler(stdout_handler)
+
+    integration_us_request = args.integration_us
+    if not args.board:
+        raise Exception("Power", "No board file selected, see board.README")
+    if not args.config:
+        raise Exception("Power", "No config file selected, see board.README")
+
+    brdfile = args.board
+    cfgfile = args.config
+    seconds = args.seconds
+    serial_a = args.serial
+    serial_b = args.serial_b
+    sync_date = args.date
+    use_ms = args.ms
+    use_mW = args.mW
+    print_stats = args.print_stats
+    stats_dir = args.stats_dir
+    stats_json_dir = args.stats_json_dir
+    print_raw_data = args.print_raw_data
+    raw_data_dir = args.raw_data_dir
+
+    boards = []
+
+    sync_speed = 0.8
+    if args.slow:
+        sync_speed = 1.2
+
+    # Set up logging interface.
+    powerlogger = powerlog(
+        brdfile,
+        cfgfile,
+        serial_a=serial_a,
+        serial_b=serial_b,
+        sync_date=sync_date,
+        use_ms=use_ms,
+        use_mW=use_mW,
+        print_stats=print_stats,
+        stats_dir=stats_dir,
+        stats_json_dir=stats_json_dir,
+        print_raw_data=print_raw_data,
+        raw_data_dir=raw_data_dir,
+    )
+
+    # Start logging.
+    powerlogger.start(integration_us_request, seconds, sync_speed=sync_speed)
 
 
 if __name__ == "__main__":
-  main()
+    main()
diff --git a/extra/usb_power/powerlog_unittest.py b/extra/usb_power/powerlog_unittest.py
index 7058c57aa7..62667e35b8 100644
--- a/extra/usb_power/powerlog_unittest.py
+++ b/extra/usb_power/powerlog_unittest.py
@@ -1,6 +1,7 @@
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
+
 """Unit tests for powerlog."""
 
 import os
@@ -8,42 +9,44 @@
 import tempfile
 import unittest
 
-import powerlog
+from usb_power import powerlog
+
 
 class TestPowerlog(unittest.TestCase):
-  """Test to verify powerlog util methods work as expected."""
-
-  def setUp(self):
-    """Set up data and create a temporary directory to save data and stats."""
-    self.tempdir = tempfile.mkdtemp()
-    self.filename = 'testfile'
-    self.filepath = os.path.join(self.tempdir, self.filename)
-    with open(self.filepath, 'w') as f:
-      f.write('')
-
-  def tearDown(self):
-    """Delete the temporary directory and its content."""
-    shutil.rmtree(self.tempdir)
-
-  def test_ProcessFilenameAbsoluteFilePath(self):
-    """Absolute file path is returned unchanged."""
-    processed_fname = powerlog.process_filename(self.filepath)
-    self.assertEqual(self.filepath, processed_fname)
-
-  def test_ProcessFilenameRelativeFilePath(self):
-    """Finds relative file path inside a known config location."""
-    original = powerlog.CONFIG_LOCATIONS
-    powerlog.CONFIG_LOCATIONS = [self.tempdir]
-    processed_fname = powerlog.process_filename(self.filename)
-    try:
-      self.assertEqual(self.filepath, processed_fname)
-    finally:
-      powerlog.CONFIG_LOCATIONS = original
-
-  def test_ProcessFilenameInvalid(self):
-    """IOError is raised when file cannot be found by any of the four ways."""
-    with self.assertRaises(IOError):
-      powerlog.process_filename(self.filename)
-
-if __name__ == '__main__':
-  unittest.main()
+    """Test to verify powerlog util methods work as expected."""
+
+    def setUp(self):
+        """Set up data and create a temporary directory to save data and stats."""
+        self.tempdir = tempfile.mkdtemp()
+        self.filename = "testfile"
+        self.filepath = os.path.join(self.tempdir, self.filename)
+        with open(self.filepath, "w") as f:
+            f.write("")
+
+    def tearDown(self):
+        """Delete the temporary directory and its content."""
+        shutil.rmtree(self.tempdir)
+
+    def test_ProcessFilenameAbsoluteFilePath(self):
+        """Absolute file path is returned unchanged."""
+        processed_fname = powerlog.process_filename(self.filepath)
+        self.assertEqual(self.filepath, processed_fname)
+
+    def test_ProcessFilenameRelativeFilePath(self):
+        """Finds relative file path inside a known config location."""
+        original = powerlog.CONFIG_LOCATIONS
+        powerlog.CONFIG_LOCATIONS = [self.tempdir]
+        processed_fname = powerlog.process_filename(self.filename)
+        try:
+            self.assertEqual(self.filepath, processed_fname)
+        finally:
+            powerlog.CONFIG_LOCATIONS = original
+
+    def test_ProcessFilenameInvalid(self):
+        """IOError is raised when file cannot be found by any of the four ways."""
+        with self.assertRaises(IOError):
+            powerlog.process_filename(self.filename)
+
+
+if __name__ == "__main__":
+    unittest.main()
diff --git a/extra/usb_power/stats_manager.py b/extra/usb_power/stats_manager.py
index 69fb33f292..fc24ef6cae 100644
--- a/extra/usb_power/stats_manager.py
+++ b/extra/usb_power/stats_manager.py
@@ -1,4 +1,4 @@
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -14,313 +14,410 @@
 import math
 import os
 
-import numpy
+import numpy  # pylint:disable=import-error
 
-STATS_PREFIX = '@@'
-NAN_TAG = '*'
-NAN_DESCRIPTION = '%s domains contain NaN samples' % NAN_TAG
+
+STATS_PREFIX = "@@"
+NAN_TAG = "*"
+NAN_DESCRIPTION = "%s domains contain NaN samples" % NAN_TAG
 
 LONG_UNIT = {
-    '': 'N/A',
-    'mW': 'milliwatt',
-    'uW': 'microwatt',
-    'mV': 'millivolt',
-    'uA': 'microamp',
-    'uV': 'microvolt'
+    "": "N/A",
+    "mW": "milliwatt",
+    "uW": "microwatt",
+    "mV": "millivolt",
+    "uA": "microamp",
+    "uV": "microvolt",
 }
 
 
 class StatsManagerError(Exception):
-  """Errors in StatsManager class."""
-  pass
+    """Errors in StatsManager class."""
+
+    pass
 
 
 class StatsManager(object):
-  """Calculates statistics for several lists of data(float).
-
-  Example usage:
-
-    >>> stats = StatsManager(title='Title Banner')
-    >>> stats.AddSample(TIME_KEY, 50.0)
-    >>> stats.AddSample(TIME_KEY, 25.0)
-    >>> stats.AddSample(TIME_KEY, 40.0)
-    >>> stats.AddSample(TIME_KEY, 10.0)
-    >>> stats.AddSample(TIME_KEY, 10.0)
-    >>> stats.AddSample('frobnicate', 11.5)
-    >>> stats.AddSample('frobnicate', 9.0)
-    >>> stats.AddSample('foobar', 11111.0)
-    >>> stats.AddSample('foobar', 22222.0)
-    >>> stats.CalculateStats()
-    >>> print(stats.SummaryToString())
-  ` @@--------------------------------------------------------------
-  ` @@                        Title Banner
-    @@--------------------------------------------------------------
-    @@            NAME  COUNT      MEAN   STDDEV       MAX       MIN
-    @@   sample_msecs      4     31.25    15.16     50.00     10.00
-    @@         foobar      2  16666.50  5555.50  22222.00  11111.00
-    @@     frobnicate      2     10.25     1.25     11.50      9.00
-  ` @@--------------------------------------------------------------
-
-  Attributes:
-    _data: dict of list of readings for each domain(key)
-    _unit: dict of unit for each domain(key)
-    _smid: id supplied to differentiate data output to other StatsManager
-           instances that potentially save to the same directory
-           if smid all output files will be named |smid|_|fname|
-    _title: title to add as banner to formatted summary. If no title,
-            no banner gets added
-    _order: list of formatting order for domains. Domains not listed are
-            displayed in sorted order
-    _hide_domains: collection of domains to hide when formatting summary string
-    _accept_nan: flag to indicate if NaN samples are acceptable
-    _nan_domains: set to keep track of which domains contain NaN samples
-    _summary: dict of stats per domain (key): min, max, count, mean, stddev
-    _logger = StatsManager logger
-
-  Note:
-    _summary is empty until CalculateStats() is called, and is updated when
-    CalculateStats() is called.
-  """
-
-  # pylint: disable=W0102
-  def __init__(self, smid='', title='', order=[], hide_domains=[],
-               accept_nan=True):
-    """Initialize infrastructure for data and their statistics."""
-    self._title = title
-    self._data = collections.defaultdict(list)
-    self._unit = collections.defaultdict(str)
-    self._smid = smid
-    self._order = order
-    self._hide_domains = hide_domains
-    self._accept_nan = accept_nan
-    self._nan_domains = set()
-    self._summary = {}
-    self._logger = logging.getLogger('StatsManager')
-
-  def AddSample(self, domain, sample):
-    """Add one sample for a domain.
-
-    Args:
-      domain: the domain name for the sample.
-      sample: one time sample for domain, expect type float.
-
-    Raises:
-      StatsManagerError: if trying to add NaN and |_accept_nan| is false
-    """
-    try:
-      sample = float(sample)
-    except ValueError:
-      # if we don't accept nan this will be caught below
-      self._logger.debug('sample %s for domain %s is not a number. Making NaN',
-                         sample, domain)
-      sample = float('NaN')
-    if not self._accept_nan and math.isnan(sample):
-      raise StatsManagerError('accept_nan is false. Cannot add NaN sample.')
-    self._data[domain].append(sample)
-    if math.isnan(sample):
-      self._nan_domains.add(domain)
-
-  def SetUnit(self, domain, unit):
-    """Set the unit for a domain.
-
-    There can be only one unit for each domain. Setting unit twice will
-    overwrite the original unit.
-
-    Args:
-      domain: the domain name.
-      unit: unit of the domain.
+    """Calculates statistics for several lists of data(float).
+
+    Example usage:
+
+      >>> stats = StatsManager(title='Title Banner')
+      >>> stats.AddSample(TIME_KEY, 50.0)
+      >>> stats.AddSample(TIME_KEY, 25.0)
+      >>> stats.AddSample(TIME_KEY, 40.0)
+      >>> stats.AddSample(TIME_KEY, 10.0)
+      >>> stats.AddSample(TIME_KEY, 10.0)
+      >>> stats.AddSample('frobnicate', 11.5)
+      >>> stats.AddSample('frobnicate', 9.0)
+      >>> stats.AddSample('foobar', 11111.0)
+      >>> stats.AddSample('foobar', 22222.0)
+      >>> stats.CalculateStats()
+      >>> print(stats.SummaryToString())
+    ` @@--------------------------------------------------------------
+    ` @@                        Title Banner
+      @@--------------------------------------------------------------
+      @@            NAME  COUNT      MEAN   STDDEV       MAX       MIN
+      @@   sample_msecs      4     31.25    15.16     50.00     10.00
+      @@         foobar      2  16666.50  5555.50  22222.00  11111.00
+      @@     frobnicate      2     10.25     1.25     11.50      9.00
+    ` @@--------------------------------------------------------------
+
+    Attributes:
+      _data: dict of list of readings for each domain(key)
+      _unit: dict of unit for each domain(key)
+      _smid: id supplied to differentiate data output to other StatsManager
+             instances that potentially save to the same directory
+             if smid all output files will be named |smid|_|fname|
+      _title: title to add as banner to formatted summary. If no title,
+              no banner gets added
+      _order: list of formatting order for domains. Domains not listed are
+              displayed in sorted order
+      _hide_domains: collection of domains to hide when formatting summary string
+      _accept_nan: flag to indicate if NaN samples are acceptable
+      _nan_domains: set to keep track of which domains contain NaN samples
+      _summary: dict of stats per domain (key): min, max, count, mean, stddev
+      _logger = StatsManager logger
+
+    Note:
+      _summary is empty until CalculateStats() is called, and is updated when
+      CalculateStats() is called.
     """
-    if domain in self._unit:
-      self._logger.warning('overwriting the unit of %s, old unit is %s, new '
-                           'unit is %s.', domain, self._unit[domain], unit)
-    self._unit[domain] = unit
 
-  def CalculateStats(self):
-    """Calculate stats for all domain-data pairs.
-
-    First erases all previous stats, then calculate stats for all data.
-    """
-    self._summary = {}
-    for domain, data in self._data.items():
-      data_np = numpy.array(data)
-      self._summary[domain] = {
-          'mean': numpy.nanmean(data_np),
-          'min': numpy.nanmin(data_np),
-          'max': numpy.nanmax(data_np),
-          'stddev': numpy.nanstd(data_np),
-          'count': data_np.size,
-      }
-
-  def SummaryToString(self, prefix=STATS_PREFIX):
-    """Format summary into a string, ready for pretty print.
-
-    See class description for format example.
-
-    Args:
-      prefix: start every row in summary string with prefix, for easier reading.
-
-    Returns:
-      formatted summary string.
-    """
-    headers = ('NAME', 'COUNT', 'MEAN', 'STDDEV', 'MAX', 'MIN')
-    table = [headers]
-    # determine what domains to display & and the order
-    domains_to_display = set(self._summary.keys()) - set(self._hide_domains)
-    display_order = [key for key in self._order if key in domains_to_display]
-    domains_to_display -= set(display_order)
-    display_order.extend(sorted(domains_to_display))
-    nan_in_output = False
-    for domain in display_order:
-      stats = self._summary[domain]
-      if not domain.endswith(self._unit[domain]):
-        domain = '%s_%s' % (domain, self._unit[domain])
-      if domain in self._nan_domains:
-        domain = '%s%s' % (domain, NAN_TAG)
-        nan_in_output = True
-      row = [domain]
-      row.append(str(stats['count']))
-      for entry in headers[2:]:
-        row.append('%.2f' % stats[entry.lower()])
-      table.append(row)
-
-    max_col_width = []
-    for col_idx in range(len(table[0])):
-      col_item_widths = [len(row[col_idx]) for row in table]
-      max_col_width.append(max(col_item_widths))
-
-    formatted_lines = []
-    for row in table:
-      formatted_row = prefix + ' '
-      for i in range(len(row)):
-        formatted_row += row[i].rjust(max_col_width[i] + 2)
-      formatted_lines.append(formatted_row)
-    if nan_in_output:
-      formatted_lines.append('%s %s' % (prefix, NAN_DESCRIPTION))
-
-    if self._title:
-      line_length = len(formatted_lines[0])
-      dec_length = len(prefix)
-      # trim title to be at most as long as the longest line without the prefix
-      title = self._title[:(line_length - dec_length)]
-      # line is a seperator line consisting of -----
-      line = '%s%s' % (prefix, '-' * (line_length - dec_length))
-      # prepend the prefix to the centered title
-      padded_title = '%s%s' % (prefix, title.center(line_length)[dec_length:])
-      formatted_lines = [line, padded_title, line] + formatted_lines + [line]
-    formatted_output = '\n'.join(formatted_lines)
-    return formatted_output
-
-  def GetSummary(self):
-    """Getter for summary."""
-    return self._summary
-
-  def _MakeUniqueFName(self, fname):
-    """prepend |_smid| to fname & rotate fname to ensure uniqueness.
-
-    Before saving a file through the StatsManager, make sure that the filename
-    is unique, first by prepending the smid if any and otherwise by appending
-    increasing integer suffixes until the filename is unique.
-
-    If |smid| is defined /path/to/example/file.txt becomes
-    /path/to/example/{smid}_file.txt.
-
-    The rotation works by changing /path/to/example/somename.txt to
-    /path/to/example/somename1.txt if the first one already exists on the
-    system.
-
-    Note: this is not thread-safe. While it makes sense to use StatsManager
-    in a threaded data-collection, the data retrieval should happen in a
-    single threaded environment to ensure files don't get potentially clobbered.
-
-    Args:
-      fname: filename to ensure uniqueness.
-
-    Returns:
-      {smid_}fname{tag}.ext
-      the smid portion gets prepended if |smid| is defined
-      the tag portion gets appended if necessary to ensure unique fname
-    """
-    fdir = os.path.dirname(fname)
-    base, ext = os.path.splitext(os.path.basename(fname))
-    if self._smid:
-      base = '%s_%s' % (self._smid, base)
-    unique_fname = os.path.join(fdir, '%s%s' % (base, ext))
-    tag = 0
-    while os.path.exists(unique_fname):
-      old_fname = unique_fname
-      unique_fname = os.path.join(fdir, '%s%d%s' % (base, tag, ext))
-      self._logger.warning('Attempted to store stats information at %s, but '
-                           'file already exists. Attempting to store at %s '
-                           'now.', old_fname, unique_fname)
-      tag += 1
-    return unique_fname
-
-  def SaveSummary(self, directory, fname='summary.txt', prefix=STATS_PREFIX):
-    """Save summary to file.
-
-    Args:
-      directory: directory to save the summary in.
-      fname: filename to save summary under.
-      prefix: start every row in summary string with prefix, for easier reading.
-
-    Returns:
-      full path of summary save location
-    """
-    summary_str = self.SummaryToString(prefix=prefix) + '\n'
-    if not os.path.exists(directory):
-      os.makedirs(directory)
-    fname = self._MakeUniqueFName(os.path.join(directory, fname))
-    with open(fname, 'w') as f:
-      f.write(summary_str)
-    return fname
-
-  def SaveSummaryJSON(self, directory, fname='summary.json'):
-    """Save summary (only MEAN) into a JSON file.
-
-    Args:
-      directory: directory to save the JSON summary in.
-      fname: filename to save summary under.
-
-    Returns:
-      full path of summary save location
-    """
-    data = {}
-    for domain in self._summary:
-      unit = LONG_UNIT.get(self._unit[domain], self._unit[domain])
-      data_entry = {'mean': self._summary[domain]['mean'], 'unit': unit}
-      data[domain] = data_entry
-    if not os.path.exists(directory):
-      os.makedirs(directory)
-    fname = self._MakeUniqueFName(os.path.join(directory, fname))
-    with open(fname, 'w') as f:
-      json.dump(data, f)
-    return fname
-
-  def GetRawData(self):
-    """Getter for all raw_data."""
-    return self._data
-
-  def SaveRawData(self, directory, dirname='raw_data'):
-    """Save raw data to file.
-
-    Args:
-      directory: directory to create the raw data folder in.
-      dirname: folder in which raw data live.
-
-    Returns:
-      list of full path of each domain's raw data save location
-    """
-    if not os.path.exists(directory):
-      os.makedirs(directory)
-    dirname = os.path.join(directory, dirname)
-    if not os.path.exists(dirname):
-      os.makedirs(dirname)
-    fnames = []
-    for domain, data in self._data.items():
-      if not domain.endswith(self._unit[domain]):
-        domain = '%s_%s' % (domain, self._unit[domain])
-      fname = self._MakeUniqueFName(os.path.join(dirname, '%s.txt' % domain))
-      with open(fname, 'w') as f:
-        f.write('\n'.join('%.2f' % sample for sample in data) + '\n')
-      fnames.append(fname)
-    return fnames
+    # pylint: disable=W0102
+    def __init__(
+        self, smid="", title="", order=[], hide_domains=[], accept_nan=True
+    ):
+        """Initialize infrastructure for data and their statistics."""
+        self._title = title
+        self._data = collections.defaultdict(list)
+        self._unit = collections.defaultdict(str)
+        self._smid = smid
+        self._order = order
+        self._hide_domains = hide_domains
+        self._accept_nan = accept_nan
+        self._nan_domains = set()
+        self._summary = {}
+        self._logger = logging.getLogger(type(self).__name__)
+
+    def AddSample(self, domain, sample):
+        """Add one sample for a domain.
+
+        Args:
+          domain: the domain name for the sample.
+          sample: one time sample for domain, expect type float.
+
+        Raises:
+          StatsManagerError: if trying to add NaN and |_accept_nan| is false
+        """
+        try:
+            sample = float(sample)
+        except ValueError:
+            # if we don't accept nan this will be caught below
+            self._logger.debug(
+                "sample %s for domain %s is not a number. Making NaN",
+                sample,
+                domain,
+            )
+            sample = float("NaN")
+        if not self._accept_nan and math.isnan(sample):
+            raise StatsManagerError(
+                "accept_nan is false. Cannot add NaN sample."
+            )
+        self._data[domain].append(sample)
+        if math.isnan(sample):
+            self._nan_domains.add(domain)
+
+    def SetUnit(self, domain, unit):
+        """Set the unit for a domain.
+
+        There can be only one unit for each domain. Setting unit twice will
+        overwrite the original unit.
+
+        Args:
+          domain: the domain name.
+          unit: unit of the domain.
+        """
+        if domain in self._unit:
+            self._logger.warning(
+                "overwriting the unit of %s, old unit is %s, new "
+                "unit is %s.",
+                domain,
+                self._unit[domain],
+                unit,
+            )
+        self._unit[domain] = unit
+
+    def CalculateStats(self):
+        """Calculate stats for all domain-data pairs.
+
+        First erases all previous stats, then calculate stats for all data.
+        """
+        self._summary = {}
+        for domain, data in self._data.items():
+            data_np = numpy.array(data)
+            self._summary[domain] = {
+                "mean": numpy.nanmean(data_np),
+                "min": numpy.nanmin(data_np),
+                "max": numpy.nanmax(data_np),
+                "stddev": numpy.nanstd(data_np),
+                "count": data_np.size,
+            }
+
+    @property
+    def DomainsToDisplay(self):
+        """List of domains that the manager will output in summaries."""
+        return set(self._summary.keys()) - set(self._hide_domains)
+
+    @property
+    def NanInOutput(self):
+        """Return whether any of the domains to display have NaN values."""
+        return bool(len(set(self._nan_domains) & self.DomainsToDisplay))
+
+    def _SummaryTable(self):
+        """Generate the matrix to output as a summary.
+
+        Returns:
+          A 2d matrix of headers and their data for each domain
+          e.g.
+          [[NAME, COUNT, MEAN, STDDEV, MAX, MIN],
+           [pp5000_mw, 10, 50, 0, 50, 50]]
+        """
+        headers = ("NAME", "COUNT", "MEAN", "STDDEV", "MAX", "MIN")
+        table = [headers]
+        # determine what domains to display & and the order
+        domains_to_display = self.DomainsToDisplay
+        display_order = [
+            key for key in self._order if key in domains_to_display
+        ]
+        domains_to_display -= set(display_order)
+        display_order.extend(sorted(domains_to_display))
+        for domain in display_order:
+            stats = self._summary[domain]
+            if not domain.endswith(self._unit[domain]):
+                domain = "%s_%s" % (domain, self._unit[domain])
+            if domain in self._nan_domains:
+                domain = "%s%s" % (domain, NAN_TAG)
+            row = [domain]
+            row.append(str(stats["count"]))
+            for entry in headers[2:]:
+                row.append("%.2f" % stats[entry.lower()])
+            table.append(row)
+        return table
+
+    def SummaryToMarkdownString(self):
+        """Format the summary into a b/ compatible markdown table string.
+
+        This requires this sort of output format
+
+        | header1   | header2   | header3   | ...
+        | --------- | --------- | --------- | ...
+        | sample1h1 | sample1h2 | sample1h3 | ...
+        .
+        .
+        .
+
+        Returns:
+          formatted summary string.
+        """
+        # All we need to do before processing is insert a row of '-' between
+        # the headers, and the data
+        table = self._SummaryTable()
+        columns = len(table[0])
+        # Using '-:' to allow the numbers to be right aligned
+        sep_row = ["-"] + ["-:"] * (columns - 1)
+        table.insert(1, sep_row)
+        text_rows = ["|".join(r) for r in table]
+        body = "\n".join(["|%s|" % r for r in text_rows])
+        if self._title:
+            title_section = "**%s**  \n\n" % self._title
+            body = title_section + body
+        # Make sure that the body is terminated with a newline.
+        return body + "\n"
+
+    def SummaryToString(self, prefix=STATS_PREFIX):
+        """Format summary into a string, ready for pretty print.
+
+        See class description for format example.
+
+        Args:
+          prefix: start every row in summary string with prefix, for easier reading.
+
+        Returns:
+          formatted summary string.
+        """
+        table = self._SummaryTable()
+        max_col_width = []
+        for col_idx in range(len(table[0])):
+            col_item_widths = [len(row[col_idx]) for row in table]
+            max_col_width.append(max(col_item_widths))
+
+        formatted_lines = []
+        for row in table:
+            formatted_row = prefix + " "
+            for i in range(len(row)):
+                formatted_row += row[i].rjust(max_col_width[i] + 2)
+            formatted_lines.append(formatted_row)
+        if self.NanInOutput:
+            formatted_lines.append("%s %s" % (prefix, NAN_DESCRIPTION))
+
+        if self._title:
+            line_length = len(formatted_lines[0])
+            dec_length = len(prefix)
+            # trim title to be at most as long as the longest line without the prefix
+            title = self._title[: (line_length - dec_length)]
+            # line is a seperator line consisting of -----
+            line = "%s%s" % (prefix, "-" * (line_length - dec_length))
+            # prepend the prefix to the centered title
+            padded_title = "%s%s" % (
+                prefix,
+                title.center(line_length)[dec_length:],
+            )
+            formatted_lines = (
+                [line, padded_title, line] + formatted_lines + [line]
+            )
+        formatted_output = "\n".join(formatted_lines)
+        return formatted_output
+
+    def GetSummary(self):
+        """Getter for summary."""
+        return self._summary
+
+    def _MakeUniqueFName(self, fname):
+        """prepend |_smid| to fname & rotate fname to ensure uniqueness.
+
+        Before saving a file through the StatsManager, make sure that the filename
+        is unique, first by prepending the smid if any and otherwise by appending
+        increasing integer suffixes until the filename is unique.
+
+        If |smid| is defined /path/to/example/file.txt becomes
+        /path/to/example/{smid}_file.txt.
+
+        The rotation works by changing /path/to/example/somename.txt to
+        /path/to/example/somename1.txt if the first one already exists on the
+        system.
+
+        Note: this is not thread-safe. While it makes sense to use StatsManager
+        in a threaded data-collection, the data retrieval should happen in a
+        single threaded environment to ensure files don't get potentially clobbered.
+
+        Args:
+          fname: filename to ensure uniqueness.
+
+        Returns:
+          {smid_}fname{tag}.[b].ext
+          the smid portion gets prepended if |smid| is defined
+          the tag portion gets appended if necessary to ensure unique fname
+        """
+        fdir = os.path.dirname(fname)
+        base, ext = os.path.splitext(os.path.basename(fname))
+        if self._smid:
+            base = "%s_%s" % (self._smid, base)
+        unique_fname = os.path.join(fdir, "%s%s" % (base, ext))
+        tag = 0
+        while os.path.exists(unique_fname):
+            old_fname = unique_fname
+            unique_fname = os.path.join(fdir, "%s%d%s" % (base, tag, ext))
+            self._logger.warning(
+                "Attempted to store stats information at %s, but "
+                "file already exists. Attempting to store at %s "
+                "now.",
+                old_fname,
+                unique_fname,
+            )
+            tag += 1
+        return unique_fname
+
+    def SaveSummary(self, directory, fname="summary.txt", prefix=STATS_PREFIX):
+        """Save summary to file.
+
+        Args:
+          directory: directory to save the summary in.
+          fname: filename to save summary under.
+          prefix: start every row in summary string with prefix, for easier reading.
+
+        Returns:
+          full path of summary save location
+        """
+        summary_str = self.SummaryToString(prefix=prefix) + "\n"
+        return self._SaveSummary(summary_str, directory, fname)
+
+    def SaveSummaryJSON(self, directory, fname="summary.json"):
+        """Save summary (only MEAN) into a JSON file.
+
+        Args:
+          directory: directory to save the JSON summary in.
+          fname: filename to save summary under.
+
+        Returns:
+          full path of summary save location
+        """
+        data = {}
+        for domain in self._summary:
+            unit = LONG_UNIT.get(self._unit[domain], self._unit[domain])
+            data_entry = {"mean": self._summary[domain]["mean"], "unit": unit}
+            data[domain] = data_entry
+        summary_str = json.dumps(data, indent=2)
+        return self._SaveSummary(summary_str, directory, fname)
+
+    def SaveSummaryMD(self, directory, fname="summary.md"):
+        """Save summary into a MD file to paste into b/.
+
+        Args:
+          directory: directory to save the MD summary in.
+          fname: filename to save summary under.
+
+        Returns:
+          full path of summary save location
+        """
+        summary_str = self.SummaryToMarkdownString()
+        return self._SaveSummary(summary_str, directory, fname)
+
+    def _SaveSummary(self, output_str, directory, fname):
+        """Wrote |output_str| to |fname|.
+
+        Args:
+          output_str: formatted output string
+          directory: directory to save the summary in.
+          fname: filename to save summary under.
+
+        Returns:
+          full path of summary save location
+        """
+        if not os.path.exists(directory):
+            os.makedirs(directory)
+        fname = self._MakeUniqueFName(os.path.join(directory, fname))
+        with open(fname, "w") as f:
+            f.write(output_str)
+        return fname
+
+    def GetRawData(self):
+        """Getter for all raw_data."""
+        return self._data
+
+    def SaveRawData(self, directory, dirname="raw_data"):
+        """Save raw data to file.
+
+        Args:
+          directory: directory to create the raw data folder in.
+          dirname: folder in which raw data live.
+
+        Returns:
+          list of full path of each domain's raw data save location
+        """
+        if not os.path.exists(directory):
+            os.makedirs(directory)
+        dirname = os.path.join(directory, dirname)
+        if not os.path.exists(dirname):
+            os.makedirs(dirname)
+        fnames = []
+        for domain, data in self._data.items():
+            if not domain.endswith(self._unit[domain]):
+                domain = "%s_%s" % (domain, self._unit[domain])
+            fname = self._MakeUniqueFName(
+                os.path.join(dirname, "%s.txt" % domain)
+            )
+            with open(fname, "w") as f:
+                f.write("\n".join("%.2f" % sample for sample in data) + "\n")
+            fnames.append(fname)
+        return fnames
diff --git a/extra/usb_power/stats_manager_unittest.py b/extra/usb_power/stats_manager_unittest.py
index f9e5e35c84..2bfaa5c83d 100644
--- a/extra/usb_power/stats_manager_unittest.py
+++ b/extra/usb_power/stats_manager_unittest.py
@@ -1,10 +1,11 @@
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 """Unit tests for StatsManager."""
 
 from __future__ import print_function
+
 import json
 import os
 import re
@@ -12,300 +13,314 @@
 import tempfile
 import unittest
 
-import stats_manager
+import stats_manager  # pylint:disable=import-error
 
 
 class TestStatsManager(unittest.TestCase):
-  """Test to verify StatsManager methods work as expected.
-
-  StatsManager should collect raw data, calculate their statistics, and save
-  them in expected format.
-  """
-
-  def _populate_mock_stats(self):
-    """Create a populated & processed StatsManager to test data retrieval."""
-    self.data.AddSample('A', 99999.5)
-    self.data.AddSample('A', 100000.5)
-    self.data.SetUnit('A', 'uW')
-    self.data.SetUnit('A', 'mW')
-    self.data.AddSample('B', 1.5)
-    self.data.AddSample('B', 2.5)
-    self.data.AddSample('B', 3.5)
-    self.data.SetUnit('B', 'mV')
-    self.data.CalculateStats()
-
-  def _populate_mock_stats_no_unit(self):
-    self.data.AddSample('B', 1000)
-    self.data.AddSample('A', 200)
-    self.data.SetUnit('A', 'blue')
-
-  def setUp(self):
-    """Set up StatsManager and create a temporary directory for test."""
-    self.tempdir = tempfile.mkdtemp()
-    self.data = stats_manager.StatsManager()
-
-  def tearDown(self):
-    """Delete the temporary directory and its content."""
-    shutil.rmtree(self.tempdir)
-
-  def test_AddSample(self):
-    """Adding a sample successfully adds a sample."""
-    self.data.AddSample('Test', 1000)
-    self.data.SetUnit('Test', 'test')
-    self.data.CalculateStats()
-    summary = self.data.GetSummary()
-    self.assertEqual(1, summary['Test']['count'])
-
-  def test_AddSampleNoFloatAcceptNaN(self):
-    """Adding a non-number adds 'NaN' and doesn't raise an exception."""
-    self.data.AddSample('Test', 10)
-    self.data.AddSample('Test', 20)
-    # adding a fake NaN: one that gets converted into NaN internally
-    self.data.AddSample('Test', 'fiesta')
-    # adding a real NaN
-    self.data.AddSample('Test', float('NaN'))
-    self.data.SetUnit('Test', 'test')
-    self.data.CalculateStats()
-    summary = self.data.GetSummary()
-    # assert that 'NaN' as added.
-    self.assertEqual(4, summary['Test']['count'])
-    # assert that mean, min, and max calculatings ignore the 'NaN'
-    self.assertEqual(10, summary['Test']['min'])
-    self.assertEqual(20, summary['Test']['max'])
-    self.assertEqual(15, summary['Test']['mean'])
-
-  def test_AddSampleNoFloatNotAcceptNaN(self):
-    """Adding a non-number raises a StatsManagerError if accept_nan is False."""
-    self.data = stats_manager.StatsManager(accept_nan=False)
-    with self.assertRaisesRegexp(stats_manager.StatsManagerError,
-                                 'accept_nan is false. Cannot add NaN sample.'):
-      # adding a fake NaN: one that gets converted into NaN internally
-      self.data.AddSample('Test', 'fiesta')
-    with self.assertRaisesRegexp(stats_manager.StatsManagerError,
-                                 'accept_nan is false. Cannot add NaN sample.'):
-      # adding a real NaN
-      self.data.AddSample('Test', float('NaN'))
-
-  def test_AddSampleNoUnit(self):
-    """Not adding a unit does not cause an exception on CalculateStats()."""
-    self.data.AddSample('Test', 17)
-    self.data.CalculateStats()
-    summary = self.data.GetSummary()
-    self.assertEqual(1, summary['Test']['count'])
-
-  def test_UnitSuffix(self):
-    """Unit gets appended as a suffix in the displayed summary."""
-    self.data.AddSample('test', 250)
-    self.data.SetUnit('test', 'mw')
-    self.data.CalculateStats()
-    summary_str = self.data.SummaryToString()
-    self.assertIn('test_mw', summary_str)
-
-  def test_DoubleUnitSuffix(self):
-    """If domain already ends in unit, verify that unit doesn't get appended."""
-    self.data.AddSample('test_mw', 250)
-    self.data.SetUnit('test_mw', 'mw')
-    self.data.CalculateStats()
-    summary_str = self.data.SummaryToString()
-    self.assertIn('test_mw', summary_str)
-    self.assertNotIn('test_mw_mw', summary_str)
-
-  def test_GetRawData(self):
-    """GetRawData returns exact same data as fed in."""
-    self._populate_mock_stats()
-    raw_data = self.data.GetRawData()
-    self.assertListEqual([99999.5, 100000.5], raw_data['A'])
-    self.assertListEqual([1.5, 2.5, 3.5], raw_data['B'])
-
-  def test_GetSummary(self):
-    """GetSummary returns expected stats about the data fed in."""
-    self._populate_mock_stats()
-    summary = self.data.GetSummary()
-    self.assertEqual(2, summary['A']['count'])
-    self.assertAlmostEqual(100000.5, summary['A']['max'])
-    self.assertAlmostEqual(99999.5, summary['A']['min'])
-    self.assertAlmostEqual(0.5, summary['A']['stddev'])
-    self.assertAlmostEqual(100000.0, summary['A']['mean'])
-    self.assertEqual(3, summary['B']['count'])
-    self.assertAlmostEqual(3.5, summary['B']['max'])
-    self.assertAlmostEqual(1.5, summary['B']['min'])
-    self.assertAlmostEqual(0.81649658092773, summary['B']['stddev'])
-    self.assertAlmostEqual(2.5, summary['B']['mean'])
-
-  def test_SaveRawData(self):
-    """SaveRawData stores same data as fed in."""
-    self._populate_mock_stats()
-    dirname = 'unittest_raw_data'
-    expected_files = set(['A_mW.txt', 'B_mV.txt'])
-    fnames = self.data.SaveRawData(self.tempdir, dirname)
-    files_returned = set([os.path.basename(f) for f in fnames])
-    # Assert that only the expected files got returned.
-    self.assertEqual(expected_files, files_returned)
-    # Assert that only the returned files are in the outdir.
-    self.assertEqual(set(os.listdir(os.path.join(self.tempdir, dirname))),
-                     files_returned)
-    for fname in fnames:
-      with open(fname, 'r') as f:
-        if 'A_mW' in fname:
-          self.assertEqual('99999.50', f.readline().strip())
-          self.assertEqual('100000.50', f.readline().strip())
-        if 'B_mV' in fname:
-          self.assertEqual('1.50', f.readline().strip())
-          self.assertEqual('2.50', f.readline().strip())
-          self.assertEqual('3.50', f.readline().strip())
-
-  def test_SaveRawDataNoUnit(self):
-    """SaveRawData appends no unit suffix if the unit is not specified."""
-    self._populate_mock_stats_no_unit()
-    self.data.CalculateStats()
-    outdir = 'unittest_raw_data'
-    files = self.data.SaveRawData(self.tempdir, outdir)
-    files = [os.path.basename(f) for f in files]
-    # Verify nothing gets appended to domain for filename if no unit exists.
-    self.assertIn('B.txt', files)
-
-  def test_SaveRawDataSMID(self):
-    """SaveRawData uses the smid when creating output filename."""
-    identifier = 'ec'
-    self.data = stats_manager.StatsManager(smid=identifier)
-    self._populate_mock_stats()
-    files = self.data.SaveRawData(self.tempdir)
-    for fname in files:
-      self.assertTrue(os.path.basename(fname).startswith(identifier))
-
-  def test_SummaryToStringNaNHelp(self):
-    """NaN containing row gets tagged with *, help banner gets added."""
-    help_banner_exp = '%s %s' % (stats_manager.STATS_PREFIX,
-                                 stats_manager.NAN_DESCRIPTION)
-    nan_domain = 'A-domain'
-    nan_domain_exp = '%s%s' % (nan_domain, stats_manager.NAN_TAG)
-    # NaN helper banner is added when a NaN domain is found & domain gets tagged
-    data = stats_manager.StatsManager()
-    data.AddSample(nan_domain, float('NaN'))
-    data.AddSample(nan_domain, 17)
-    data.AddSample('B-domain', 17)
-    data.CalculateStats()
-    summarystr = data.SummaryToString()
-    self.assertIn(help_banner_exp, summarystr)
-    self.assertIn(nan_domain_exp, summarystr)
-    # NaN helper banner is not added when no NaN domain output, no tagging
-    data = stats_manager.StatsManager()
-    # nan_domain in this scenario does not contain any NaN
-    data.AddSample(nan_domain, 19)
-    data.AddSample('B-domain', 17)
-    data.CalculateStats()
-    summarystr = data.SummaryToString()
-    self.assertNotIn(help_banner_exp, summarystr)
-    self.assertNotIn(nan_domain_exp, summarystr)
-
-  def test_SummaryToStringTitle(self):
-    """Title shows up in SummaryToString if title specified."""
-    title = 'titulo'
-    data = stats_manager.StatsManager(title=title)
-    self._populate_mock_stats()
-    summary_str = data.SummaryToString()
-    self.assertIn(title, summary_str)
-
-  def test_SummaryToStringHideDomains(self):
-    """Keys indicated in hide_domains are not printed in the summary."""
-    data = stats_manager.StatsManager(hide_domains=['A-domain'])
-    data.AddSample('A-domain', 17)
-    data.AddSample('B-domain', 17)
-    data.CalculateStats()
-    summary_str = data.SummaryToString()
-    self.assertIn('B-domain', summary_str)
-    self.assertNotIn('A-domain', summary_str)
-
-  def test_SummaryToStringOrder(self):
-    """Order passed into StatsManager is honoured when formatting summary."""
-    # StatsManager that should print D & B first, and the subsequent elements
-    # are sorted.
-    d_b_a_c_regexp = re.compile('D-domain.*B-domain.*A-domain.*C-domain',
-                                re.DOTALL)
-    data = stats_manager.StatsManager(order=['D-domain', 'B-domain'])
-    data.AddSample('A-domain', 17)
-    data.AddSample('B-domain', 17)
-    data.AddSample('C-domain', 17)
-    data.AddSample('D-domain', 17)
-    data.CalculateStats()
-    summary_str = data.SummaryToString()
-    self.assertRegexpMatches(summary_str, d_b_a_c_regexp)
-
-  def test_MakeUniqueFName(self):
-    data = stats_manager.StatsManager()
-    testfile = os.path.join(self.tempdir, 'testfile.txt')
-    with open(testfile, 'w') as f:
-      f.write('')
-    expected_fname = os.path.join(self.tempdir, 'testfile0.txt')
-    self.assertEqual(expected_fname, data._MakeUniqueFName(testfile))
-
-  def test_SaveSummary(self):
-    """SaveSummary properly dumps the summary into a file."""
-    self._populate_mock_stats()
-    fname = 'unittest_summary.txt'
-    expected_fname = os.path.join(self.tempdir, fname)
-    fname = self.data.SaveSummary(self.tempdir, fname)
-    # Assert the reported fname is the same as the expected fname
-    self.assertEqual(expected_fname, fname)
-    # Assert only the reported fname is output (in the tempdir)
-    self.assertEqual(set([os.path.basename(fname)]),
-                     set(os.listdir(self.tempdir)))
-    with open(fname, 'r') as f:
-      self.assertEqual(
-          '@@   NAME  COUNT       MEAN  STDDEV        MAX       MIN\n',
-          f.readline())
-      self.assertEqual(
-          '@@   A_mW      2  100000.00    0.50  100000.50  99999.50\n',
-          f.readline())
-      self.assertEqual(
-          '@@   B_mV      3       2.50    0.82       3.50      1.50\n',
-          f.readline())
-
-  def test_SaveSummarySMID(self):
-    """SaveSummary uses the smid when creating output filename."""
-    identifier = 'ec'
-    self.data = stats_manager.StatsManager(smid=identifier)
-    self._populate_mock_stats()
-    fname = os.path.basename(self.data.SaveSummary(self.tempdir))
-    self.assertTrue(fname.startswith(identifier))
-
-  def test_SaveSummaryJSON(self):
-    """SaveSummaryJSON saves the added data properly in JSON format."""
-    self._populate_mock_stats()
-    fname = 'unittest_summary.json'
-    expected_fname = os.path.join(self.tempdir, fname)
-    fname = self.data.SaveSummaryJSON(self.tempdir, fname)
-    # Assert the reported fname is the same as the expected fname
-    self.assertEqual(expected_fname, fname)
-    # Assert only the reported fname is output (in the tempdir)
-    self.assertEqual(set([os.path.basename(fname)]),
-                     set(os.listdir(self.tempdir)))
-    with open(fname, 'r') as f:
-      summary = json.load(f)
-      self.assertAlmostEqual(100000.0, summary['A']['mean'])
-      self.assertEqual('milliwatt', summary['A']['unit'])
-      self.assertAlmostEqual(2.5, summary['B']['mean'])
-      self.assertEqual('millivolt', summary['B']['unit'])
-
-  def test_SaveSummaryJSONSMID(self):
-    """SaveSummaryJSON uses the smid when creating output filename."""
-    identifier = 'ec'
-    self.data = stats_manager.StatsManager(smid=identifier)
-    self._populate_mock_stats()
-    fname = os.path.basename(self.data.SaveSummaryJSON(self.tempdir))
-    self.assertTrue(fname.startswith(identifier))
-
-  def test_SaveSummaryJSONNoUnit(self):
-    """SaveSummaryJSON marks unknown units properly as N/A."""
-    self._populate_mock_stats_no_unit()
-    self.data.CalculateStats()
-    fname = 'unittest_summary.json'
-    fname = self.data.SaveSummaryJSON(self.tempdir, fname)
-    with open(fname, 'r') as f:
-      summary = json.load(f)
-      self.assertEqual('blue', summary['A']['unit'])
-      # if no unit is specified, JSON should save 'N/A' as the unit.
-      self.assertEqual('N/A', summary['B']['unit'])
-
-if __name__ == '__main__':
-  unittest.main()
+    """Test to verify StatsManager methods work as expected.
+
+    StatsManager should collect raw data, calculate their statistics, and save
+    them in expected format.
+    """
+
+    def _populate_mock_stats(self):
+        """Create a populated & processed StatsManager to test data retrieval."""
+        self.data.AddSample("A", 99999.5)
+        self.data.AddSample("A", 100000.5)
+        self.data.SetUnit("A", "uW")
+        self.data.SetUnit("A", "mW")
+        self.data.AddSample("B", 1.5)
+        self.data.AddSample("B", 2.5)
+        self.data.AddSample("B", 3.5)
+        self.data.SetUnit("B", "mV")
+        self.data.CalculateStats()
+
+    def _populate_mock_stats_no_unit(self):
+        self.data.AddSample("B", 1000)
+        self.data.AddSample("A", 200)
+        self.data.SetUnit("A", "blue")
+
+    def setUp(self):
+        """Set up StatsManager and create a temporary directory for test."""
+        self.tempdir = tempfile.mkdtemp()
+        self.data = stats_manager.StatsManager()
+
+    def tearDown(self):
+        """Delete the temporary directory and its content."""
+        shutil.rmtree(self.tempdir)
+
+    def test_AddSample(self):
+        """Adding a sample successfully adds a sample."""
+        self.data.AddSample("Test", 1000)
+        self.data.SetUnit("Test", "test")
+        self.data.CalculateStats()
+        summary = self.data.GetSummary()
+        self.assertEqual(1, summary["Test"]["count"])
+
+    def test_AddSampleNoFloatAcceptNaN(self):
+        """Adding a non-number adds 'NaN' and doesn't raise an exception."""
+        self.data.AddSample("Test", 10)
+        self.data.AddSample("Test", 20)
+        # adding a fake NaN: one that gets converted into NaN internally
+        self.data.AddSample("Test", "fiesta")
+        # adding a real NaN
+        self.data.AddSample("Test", float("NaN"))
+        self.data.SetUnit("Test", "test")
+        self.data.CalculateStats()
+        summary = self.data.GetSummary()
+        # assert that 'NaN' as added.
+        self.assertEqual(4, summary["Test"]["count"])
+        # assert that mean, min, and max calculatings ignore the 'NaN'
+        self.assertEqual(10, summary["Test"]["min"])
+        self.assertEqual(20, summary["Test"]["max"])
+        self.assertEqual(15, summary["Test"]["mean"])
+
+    def test_AddSampleNoFloatNotAcceptNaN(self):
+        """Adding a non-number raises a StatsManagerError if accept_nan is False."""
+        self.data = stats_manager.StatsManager(accept_nan=False)
+        with self.assertRaisesRegexp(
+            stats_manager.StatsManagerError,
+            "accept_nan is false. Cannot add NaN sample.",
+        ):
+            # adding a fake NaN: one that gets converted into NaN internally
+            self.data.AddSample("Test", "fiesta")
+        with self.assertRaisesRegexp(
+            stats_manager.StatsManagerError,
+            "accept_nan is false. Cannot add NaN sample.",
+        ):
+            # adding a real NaN
+            self.data.AddSample("Test", float("NaN"))
+
+    def test_AddSampleNoUnit(self):
+        """Not adding a unit does not cause an exception on CalculateStats()."""
+        self.data.AddSample("Test", 17)
+        self.data.CalculateStats()
+        summary = self.data.GetSummary()
+        self.assertEqual(1, summary["Test"]["count"])
+
+    def test_UnitSuffix(self):
+        """Unit gets appended as a suffix in the displayed summary."""
+        self.data.AddSample("test", 250)
+        self.data.SetUnit("test", "mw")
+        self.data.CalculateStats()
+        summary_str = self.data.SummaryToString()
+        self.assertIn("test_mw", summary_str)
+
+    def test_DoubleUnitSuffix(self):
+        """If domain already ends in unit, verify that unit doesn't get appended."""
+        self.data.AddSample("test_mw", 250)
+        self.data.SetUnit("test_mw", "mw")
+        self.data.CalculateStats()
+        summary_str = self.data.SummaryToString()
+        self.assertIn("test_mw", summary_str)
+        self.assertNotIn("test_mw_mw", summary_str)
+
+    def test_GetRawData(self):
+        """GetRawData returns exact same data as fed in."""
+        self._populate_mock_stats()
+        raw_data = self.data.GetRawData()
+        self.assertListEqual([99999.5, 100000.5], raw_data["A"])
+        self.assertListEqual([1.5, 2.5, 3.5], raw_data["B"])
+
+    def test_GetSummary(self):
+        """GetSummary returns expected stats about the data fed in."""
+        self._populate_mock_stats()
+        summary = self.data.GetSummary()
+        self.assertEqual(2, summary["A"]["count"])
+        self.assertAlmostEqual(100000.5, summary["A"]["max"])
+        self.assertAlmostEqual(99999.5, summary["A"]["min"])
+        self.assertAlmostEqual(0.5, summary["A"]["stddev"])
+        self.assertAlmostEqual(100000.0, summary["A"]["mean"])
+        self.assertEqual(3, summary["B"]["count"])
+        self.assertAlmostEqual(3.5, summary["B"]["max"])
+        self.assertAlmostEqual(1.5, summary["B"]["min"])
+        self.assertAlmostEqual(0.81649658092773, summary["B"]["stddev"])
+        self.assertAlmostEqual(2.5, summary["B"]["mean"])
+
+    def test_SaveRawData(self):
+        """SaveRawData stores same data as fed in."""
+        self._populate_mock_stats()
+        dirname = "unittest_raw_data"
+        expected_files = set(["A_mW.txt", "B_mV.txt"])
+        fnames = self.data.SaveRawData(self.tempdir, dirname)
+        files_returned = set([os.path.basename(f) for f in fnames])
+        # Assert that only the expected files got returned.
+        self.assertEqual(expected_files, files_returned)
+        # Assert that only the returned files are in the outdir.
+        self.assertEqual(
+            set(os.listdir(os.path.join(self.tempdir, dirname))), files_returned
+        )
+        for fname in fnames:
+            with open(fname, "r") as f:
+                if "A_mW" in fname:
+                    self.assertEqual("99999.50", f.readline().strip())
+                    self.assertEqual("100000.50", f.readline().strip())
+                if "B_mV" in fname:
+                    self.assertEqual("1.50", f.readline().strip())
+                    self.assertEqual("2.50", f.readline().strip())
+                    self.assertEqual("3.50", f.readline().strip())
+
+    def test_SaveRawDataNoUnit(self):
+        """SaveRawData appends no unit suffix if the unit is not specified."""
+        self._populate_mock_stats_no_unit()
+        self.data.CalculateStats()
+        outdir = "unittest_raw_data"
+        files = self.data.SaveRawData(self.tempdir, outdir)
+        files = [os.path.basename(f) for f in files]
+        # Verify nothing gets appended to domain for filename if no unit exists.
+        self.assertIn("B.txt", files)
+
+    def test_SaveRawDataSMID(self):
+        """SaveRawData uses the smid when creating output filename."""
+        identifier = "ec"
+        self.data = stats_manager.StatsManager(smid=identifier)
+        self._populate_mock_stats()
+        files = self.data.SaveRawData(self.tempdir)
+        for fname in files:
+            self.assertTrue(os.path.basename(fname).startswith(identifier))
+
+    def test_SummaryToStringNaNHelp(self):
+        """NaN containing row gets tagged with *, help banner gets added."""
+        help_banner_exp = "%s %s" % (
+            stats_manager.STATS_PREFIX,
+            stats_manager.NAN_DESCRIPTION,
+        )
+        nan_domain = "A-domain"
+        nan_domain_exp = "%s%s" % (nan_domain, stats_manager.NAN_TAG)
+        # NaN helper banner is added when a NaN domain is found & domain gets tagged
+        data = stats_manager.StatsManager()
+        data.AddSample(nan_domain, float("NaN"))
+        data.AddSample(nan_domain, 17)
+        data.AddSample("B-domain", 17)
+        data.CalculateStats()
+        summarystr = data.SummaryToString()
+        self.assertIn(help_banner_exp, summarystr)
+        self.assertIn(nan_domain_exp, summarystr)
+        # NaN helper banner is not added when no NaN domain output, no tagging
+        data = stats_manager.StatsManager()
+        # nan_domain in this scenario does not contain any NaN
+        data.AddSample(nan_domain, 19)
+        data.AddSample("B-domain", 17)
+        data.CalculateStats()
+        summarystr = data.SummaryToString()
+        self.assertNotIn(help_banner_exp, summarystr)
+        self.assertNotIn(nan_domain_exp, summarystr)
+
+    def test_SummaryToStringTitle(self):
+        """Title shows up in SummaryToString if title specified."""
+        title = "titulo"
+        data = stats_manager.StatsManager(title=title)
+        self._populate_mock_stats()
+        summary_str = data.SummaryToString()
+        self.assertIn(title, summary_str)
+
+    def test_SummaryToStringHideDomains(self):
+        """Keys indicated in hide_domains are not printed in the summary."""
+        data = stats_manager.StatsManager(hide_domains=["A-domain"])
+        data.AddSample("A-domain", 17)
+        data.AddSample("B-domain", 17)
+        data.CalculateStats()
+        summary_str = data.SummaryToString()
+        self.assertIn("B-domain", summary_str)
+        self.assertNotIn("A-domain", summary_str)
+
+    def test_SummaryToStringOrder(self):
+        """Order passed into StatsManager is honoured when formatting summary."""
+        # StatsManager that should print D & B first, and the subsequent elements
+        # are sorted.
+        d_b_a_c_regexp = re.compile(
+            "D-domain.*B-domain.*A-domain.*C-domain", re.DOTALL
+        )
+        data = stats_manager.StatsManager(order=["D-domain", "B-domain"])
+        data.AddSample("A-domain", 17)
+        data.AddSample("B-domain", 17)
+        data.AddSample("C-domain", 17)
+        data.AddSample("D-domain", 17)
+        data.CalculateStats()
+        summary_str = data.SummaryToString()
+        self.assertRegexpMatches(summary_str, d_b_a_c_regexp)
+
+    def test_MakeUniqueFName(self):
+        data = stats_manager.StatsManager()
+        testfile = os.path.join(self.tempdir, "testfile.txt")
+        with open(testfile, "w") as f:
+            f.write("")
+        expected_fname = os.path.join(self.tempdir, "testfile0.txt")
+        self.assertEqual(expected_fname, data._MakeUniqueFName(testfile))
+
+    def test_SaveSummary(self):
+        """SaveSummary properly dumps the summary into a file."""
+        self._populate_mock_stats()
+        fname = "unittest_summary.txt"
+        expected_fname = os.path.join(self.tempdir, fname)
+        fname = self.data.SaveSummary(self.tempdir, fname)
+        # Assert the reported fname is the same as the expected fname
+        self.assertEqual(expected_fname, fname)
+        # Assert only the reported fname is output (in the tempdir)
+        self.assertEqual(
+            set([os.path.basename(fname)]), set(os.listdir(self.tempdir))
+        )
+        with open(fname, "r") as f:
+            self.assertEqual(
+                "@@   NAME  COUNT       MEAN  STDDEV        MAX       MIN\n",
+                f.readline(),
+            )
+            self.assertEqual(
+                "@@   A_mW      2  100000.00    0.50  100000.50  99999.50\n",
+                f.readline(),
+            )
+            self.assertEqual(
+                "@@   B_mV      3       2.50    0.82       3.50      1.50\n",
+                f.readline(),
+            )
+
+    def test_SaveSummarySMID(self):
+        """SaveSummary uses the smid when creating output filename."""
+        identifier = "ec"
+        self.data = stats_manager.StatsManager(smid=identifier)
+        self._populate_mock_stats()
+        fname = os.path.basename(self.data.SaveSummary(self.tempdir))
+        self.assertTrue(fname.startswith(identifier))
+
+    def test_SaveSummaryJSON(self):
+        """SaveSummaryJSON saves the added data properly in JSON format."""
+        self._populate_mock_stats()
+        fname = "unittest_summary.json"
+        expected_fname = os.path.join(self.tempdir, fname)
+        fname = self.data.SaveSummaryJSON(self.tempdir, fname)
+        # Assert the reported fname is the same as the expected fname
+        self.assertEqual(expected_fname, fname)
+        # Assert only the reported fname is output (in the tempdir)
+        self.assertEqual(
+            set([os.path.basename(fname)]), set(os.listdir(self.tempdir))
+        )
+        with open(fname, "r") as f:
+            summary = json.load(f)
+            self.assertAlmostEqual(100000.0, summary["A"]["mean"])
+            self.assertEqual("milliwatt", summary["A"]["unit"])
+            self.assertAlmostEqual(2.5, summary["B"]["mean"])
+            self.assertEqual("millivolt", summary["B"]["unit"])
+
+    def test_SaveSummaryJSONSMID(self):
+        """SaveSummaryJSON uses the smid when creating output filename."""
+        identifier = "ec"
+        self.data = stats_manager.StatsManager(smid=identifier)
+        self._populate_mock_stats()
+        fname = os.path.basename(self.data.SaveSummaryJSON(self.tempdir))
+        self.assertTrue(fname.startswith(identifier))
+
+    def test_SaveSummaryJSONNoUnit(self):
+        """SaveSummaryJSON marks unknown units properly as N/A."""
+        self._populate_mock_stats_no_unit()
+        self.data.CalculateStats()
+        fname = "unittest_summary.json"
+        fname = self.data.SaveSummaryJSON(self.tempdir, fname)
+        with open(fname, "r") as f:
+            summary = json.load(f)
+            self.assertEqual("blue", summary["A"]["unit"])
+            # if no unit is specified, JSON should save 'N/A' as the unit.
+            self.assertEqual("N/A", summary["B"]["unit"])
+
+
+if __name__ == "__main__":
+    unittest.main()
diff --git a/extra/usb_serial/README.md b/extra/usb_serial/README.md
index 6806620a62..7cc6030d0a 100644
--- a/extra/usb_serial/README.md
+++ b/extra/usb_serial/README.md
@@ -1,5 +1,4 @@
-Case Closed Debugging Serial Consoles over USB
-==============================================
+# Case Closed Debugging Serial Consoles over USB
 
 Please see the documentation in [case_closed_debugging doc][1]
 
diff --git a/extra/usb_serial/add_usb_serial_id b/extra/usb_serial/add_usb_serial_id
index ef8336afdc..12e0055e0b 100755
--- a/extra/usb_serial/add_usb_serial_id
+++ b/extra/usb_serial/add_usb_serial_id
@@ -1,6 +1,6 @@
 #!/bin/sh -e
 #
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/extra/usb_serial/console.py b/extra/usb_serial/console.py
index bd1fbaacc6..07444c39f3 100755
--- a/extra/usb_serial/console.py
+++ b/extra/usb_serial/console.py
@@ -1,5 +1,5 @@
-#!/usr/bin/env python
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+#!/usr/bin/env python3
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -8,6 +8,7 @@
 # Note: This is a py2/3 compatible file.
 
 from __future__ import print_function
+
 import argparse
 import array
 import os
@@ -15,25 +16,26 @@
 import termios
 import threading
 import time
-import traceback
 import tty
+
+
 try:
-  import usb
-except:
-  print("import usb failed")
-  print("try running these commands:")
-  print(" sudo apt-get install python-pip")
-  print(" sudo pip install --pre pyusb")
-  print()
-  sys.exit(-1)
+    import usb  # pylint:disable=import-error
+except ModuleNotFoundError:
+    print("import usb failed")
+    print("try running these commands:")
+    print(" sudo apt-get install python-pip")
+    print(" sudo pip install --pre pyusb")
+    print()
+    sys.exit(-1)
 
 import six
 
 
 def GetBuffer(stream):
-  if six.PY3:
-    return stream.buffer
-  return stream
+    if six.PY3:
+        return stream.buffer
+    return stream
 
 
 """Class Susb covers USB device discovery and initialization.
@@ -42,99 +44,103 @@ def GetBuffer(stream):
   and interface number.
 """
 
+
 class SusbError(Exception):
-  """Class for exceptions of Susb."""
-  def __init__(self, msg, value=0):
-    """SusbError constructor.
+    """Class for exceptions of Susb."""
 
-    Args:
-      msg: string, message describing error in detail
-      value: integer, value of error when non-zero status returned.  Default=0
-    """
-    super(SusbError, self).__init__(msg, value)
-    self.msg = msg
-    self.value = value
-
-class Susb():
-  """Provide USB functionality.
-
-  Instance Variables:
-  _read_ep: pyUSB read endpoint for this interface
-  _write_ep: pyUSB write endpoint for this interface
-  """
-  READ_ENDPOINT = 0x81
-  WRITE_ENDPOINT = 0x1
-  TIMEOUT_MS = 100
-
-  def __init__(self, vendor=0x18d1,
-               product=0x500f, interface=1, serialname=None):
-    """Susb constructor.
-
-    Discovers and connects to USB endpoints.
-
-    Args:
-      vendor    : usb vendor id of device
-      product   : usb product id of device
-      interface : interface number ( 1 - 8 ) of device to use
-      serialname: string of device serialnumber.
-
-    Raises:
-      SusbError: An error accessing Susb object
+    def __init__(self, msg, value=0):
+        """SusbError constructor.
+
+        Args:
+          msg: string, message describing error in detail
+          value: integer, value of error when non-zero status returned.  Default=0
+        """
+        super(SusbError, self).__init__(msg, value)
+        self.msg = msg
+        self.value = value
+
+
+class Susb:
+    """Provide USB functionality.
+
+    Instance Variables:
+    _read_ep: pyUSB read endpoint for this interface
+    _write_ep: pyUSB write endpoint for this interface
     """
-    # Find the device.
-    dev_g = usb.core.find(idVendor=vendor, idProduct=product, find_all=True)
-    dev_list = list(dev_g)
-    if dev_list is None:
-      raise SusbError("USB device not found")
-
-    # Check if we have multiple devices.
-    dev = None
-    if serialname:
-      for d in dev_list:
-        dev_serial = "PyUSB doesn't have a stable interface"
-        try:
-          dev_serial = usb.util.get_string(d, 256, d.iSerialNumber)
-        except:
-          dev_serial = usb.util.get_string(d, d.iSerialNumber)
-        if dev_serial == serialname:
-          dev = d
-          break
-      if dev is None:
-        raise SusbError("USB device(%s) not found" % (serialname,))
-    else:
-      try:
-        dev = dev_list[0]
-      except:
-        try:
-          dev = dev_list.next()
-        except:
-          raise SusbError("USB device %04x:%04x not found" % (vendor, product))
 
-    # If we can't set configuration, it's already been set.
-    try:
-      dev.set_configuration()
-    except usb.core.USBError:
-      pass
+    READ_ENDPOINT = 0x81
+    WRITE_ENDPOINT = 0x1
+    TIMEOUT_MS = 100
+
+    def __init__(
+        self, vendor=0x18D1, product=0x500F, interface=1, serialname=None
+    ):
+        """Susb constructor.
+
+        Discovers and connects to USB endpoints.
+
+        Args:
+          vendor: usb vendor id of device
+          product: usb product id of device
+          interface: interface number ( 1 - 8 ) of device to use
+          serialname: string of device serialnumber.
+
+        Raises:
+          SusbError: An error accessing Susb object
+        """
+        # Find the device.
+        dev_g = usb.core.find(idVendor=vendor, idProduct=product, find_all=True)
+        dev_list = list(dev_g)
+        if dev_list is None:
+            raise SusbError("USB device not found")
+
+        # Check if we have multiple devices.
+        dev = None
+        if serialname:
+            for d in dev_list:
+                dev_serial = usb.util.get_string(d, d.iSerialNumber)
+                if dev_serial == serialname:
+                    dev = d
+                    break
+            if dev is None:
+                raise SusbError("USB device(%s) not found" % (serialname,))
+        else:
+            try:
+                dev = dev_list[0]
+            except IndexError:
+                raise SusbError(
+                    "USB device %04x:%04x not found" % (vendor, product)
+                )
+
+        # If we can't set configuration, it's already been set.
+        try:
+            dev.set_configuration()
+        except usb.core.USBError:
+            pass
 
-    # Get an endpoint instance.
-    cfg = dev.get_active_configuration()
-    intf = usb.util.find_descriptor(cfg, bInterfaceNumber=interface)
-    self._intf = intf
+        # Get an endpoint instance.
+        cfg = dev.get_active_configuration()
+        intf = usb.util.find_descriptor(cfg, bInterfaceNumber=interface)
+        self._intf = intf
 
-    if not intf:
-      raise SusbError("Interface not found")
+        if not intf:
+            raise SusbError("Interface not found")
 
-    # Detach raiden.ko if it is loaded.
-    if dev.is_kernel_driver_active(intf.bInterfaceNumber) is True:
+        # Detach raiden.ko if it is loaded.
+        if dev.is_kernel_driver_active(intf.bInterfaceNumber) is True:
             dev.detach_kernel_driver(intf.bInterfaceNumber)
 
-    read_ep_number = intf.bInterfaceNumber + self.READ_ENDPOINT
-    read_ep = usb.util.find_descriptor(intf, bEndpointAddress=read_ep_number)
-    self._read_ep = read_ep
+        read_ep_number = intf.bInterfaceNumber + self.READ_ENDPOINT
+        read_ep = usb.util.find_descriptor(
+            intf, bEndpointAddress=read_ep_number
+        )
+        self._read_ep = read_ep
 
-    write_ep_number = intf.bInterfaceNumber + self.WRITE_ENDPOINT
-    write_ep = usb.util.find_descriptor(intf, bEndpointAddress=write_ep_number)
-    self._write_ep = write_ep
+        write_ep_number = intf.bInterfaceNumber + self.WRITE_ENDPOINT
+        write_ep = usb.util.find_descriptor(
+            intf, bEndpointAddress=write_ep_number
+        )
+        self._write_ep = write_ep
 
 
 """Suart class implements a stream interface, to access Google's USB class.
@@ -143,90 +149,96 @@ def __init__(self, vendor=0x18d1,
   and forwards them across. This particular class is hardcoded to stdin/out.
 """
 
-class SuartError(Exception):
-  """Class for exceptions of Suart."""
-  def __init__(self, msg, value=0):
-    """SuartError constructor.
-
-    Args:
-      msg: string, message describing error in detail
-      value: integer, value of error when non-zero status returned.  Default=0
-    """
-    super(SuartError, self).__init__(msg, value)
-    self.msg = msg
-    self.value = value
-
-
-class Suart():
-  """Provide interface to serial usb endpoint."""
-
-  def __init__(self, vendor=0x18d1, product=0x501c, interface=0,
-               serialname=None):
-    """Suart contstructor.
-
-    Initializes USB stream interface.
-
-    Args:
-      vendor: usb vendor id of device
-      product: usb product id of device
-      interface: interface number of device to use
-      serialname: Defaults to None.
-
-    Raises:
-      SuartError: If init fails
-    """
-    self._done = threading.Event()
-    self._susb = Susb(vendor=vendor, product=product,
-        interface=interface, serialname=serialname)
-
-  def wait_until_done(self, timeout=None):
-    return self._done.wait(timeout=timeout)
-
-  def run_rx_thread(self):
-    try:
-      while True:
-          try:
-            r = self._susb._read_ep.read(64, self._susb.TIMEOUT_MS)
-            if r:
-              GetBuffer(sys.stdout).write(r.tostring())
-              GetBuffer(sys.stdout).flush()
-
-          except Exception as e:
-            # If we miss some characters on pty disconnect, that's fine.
-            # ep.read() also throws USBError on timeout, which we discard.
-            if not isinstance(e, (OSError, usb.core.USBError)):
-              print("rx %s" % e)
-    finally:
-      self._done.set()
-
-  def run_tx_thread(self):
-    try:
-      while True:
-          try:
-            r = GetBuffer(sys.stdin).read(1)
-            if not r or r == b"\x03":
-              break
-            if r:
-              self._susb._write_ep.write(array.array('B', r),
-                                         self._susb.TIMEOUT_MS)
-          except Exception as e:
-            print("tx %s" % e)
-    finally:
-      self._done.set()
-
-  def run(self):
-    """Creates pthreads to poll USB & PTY for data.
-    """
-    self._exit = False
-
-    self._rx_thread = threading.Thread(target=self.run_rx_thread)
-    self._rx_thread.daemon = True
-    self._rx_thread.start()
-
-    self._tx_thread = threading.Thread(target=self.run_tx_thread)
-    self._tx_thread.daemon = True
-    self._tx_thread.start()
 
+class SuartError(Exception):
+    """Class for exceptions of Suart."""
+
+    def __init__(self, msg, value=0):
+        """SuartError constructor.
+
+        Args:
+          msg: string, message describing error in detail
+          value: integer, value of error when non-zero status returned.  Default=0
+        """
+        super(SuartError, self).__init__(msg, value)
+        self.msg = msg
+        self.value = value
+
+
+class Suart:
+    """Provide interface to serial usb endpoint."""
+
+    def __init__(
+        self, vendor=0x18D1, product=0x501C, interface=0, serialname=None
+    ):
+        """Suart contstructor.
+
+        Initializes USB stream interface.
+
+        Args:
+          vendor: usb vendor id of device
+          product: usb product id of device
+          interface: interface number of device to use
+          serialname: Defaults to None.
+
+        Raises:
+          SuartError: If init fails
+        """
+        self._done = threading.Event()
+        self._susb = Susb(
+            vendor=vendor,
+            product=product,
+            interface=interface,
+            serialname=serialname,
+        )
+
+    def wait_until_done(self, timeout=None):
+        return self._done.wait(timeout=timeout)
+
+    def run_rx_thread(self):
+        try:
+            while True:
+                try:
+                    r = self._susb._read_ep.read(64, self._susb.TIMEOUT_MS)
+                    if r:
+                        GetBuffer(sys.stdout).write(r.tobytes())
+                        GetBuffer(sys.stdout).flush()
+
+                except Exception as e:
+                    # If we miss some characters on pty disconnect, that's fine.
+                    # ep.read() also throws USBError on timeout, which we discard.
+                    if not isinstance(e, (OSError, usb.core.USBError)):
+                        print("rx %s" % e)
+        finally:
+            self._done.set()
+
+    def run_tx_thread(self):
+        try:
+            while True:
+                try:
+                    r = GetBuffer(sys.stdin).read(1)
+                    if not r or r == b"\x03":
+                        break
+                    if r:
+                        self._susb._write_ep.write(
+                            array.array("B", r), self._susb.TIMEOUT_MS
+                        )
+                except Exception as e:
+                    print("tx %s" % e)
+        finally:
+            self._done.set()
+
+    def run(self):
+        """Creates pthreads to poll USB & PTY for data."""
+        self._exit = False
+
+        self._rx_thread = threading.Thread(target=self.run_rx_thread)
+        self._rx_thread.daemon = True
+        self._rx_thread.start()
+
+        self._tx_thread = threading.Thread(target=self.run_tx_thread)
+        self._tx_thread.daemon = True
+        self._tx_thread.start()
 
 
 """Command line functionality
@@ -235,60 +247,76 @@ def run(self):
   Ctrl-C exits.
 """
 
-parser = argparse.ArgumentParser(description="Open a console to a USB device")
-parser.add_argument('-d', '--device', type=str,
-    help="vid:pid of target device", default="18d1:501c")
-parser.add_argument('-i', '--interface', type=int,
-    help="interface number of console", default=0)
-parser.add_argument('-s', '--serialno', type=str,
-    help="serial number of device", default="")
-parser.add_argument('-S', '--notty-exit-sleep', type=float, default=0.2,
-    help="When stdin is *not* a TTY, wait this many seconds after EOF from "
-    "stdin before exiting, to give time for receiving a reply from the USB "
-    "device.")
+parser = argparse.ArgumentParser(
+    description="Open a console to a USB device",
+    formatter_class=argparse.ArgumentDefaultsHelpFormatter,
+)
+parser.add_argument(
+    "-d",
+    "--device",
+    type=str,
+    help="vid:pid of target device",
+    default="18d1:501c",
+)
+parser.add_argument(
+    "-i", "--interface", type=int, help="interface number of console", default=0
+)
+parser.add_argument(
+    "-s", "--serialno", type=str, help="serial number of device", default=""
+)
+parser.add_argument(
+    "-S",
+    "--notty-exit-sleep",
+    type=float,
+    default=0.2,
+    help="When stdin is *not* a TTY, wait this many seconds "
+    "after EOF from stdin before exiting, to give time for "
+    "receiving a reply from the USB device.",
+)
 
 
 def runconsole():
-  """Run the usb console code
+    """Run the usb console code
 
-  Starts the pty thread, and idles until a ^C is caught.
-  """
-  args = parser.parse_args()
+    Starts the pty thread, and idles until a ^C is caught.
+    """
+    args = parser.parse_args()
 
-  vidstr, pidstr = args.device.split(':')
-  vid = int(vidstr, 16)
-  pid = int(pidstr, 16)
+    vidstr, pidstr = args.device.split(":")
+    vid = int(vidstr, 16)
+    pid = int(pidstr, 16)
 
-  serialno = args.serialno
-  interface = args.interface
+    serialno = args.serialno
+    interface = args.interface
 
-  sobj = Suart(vendor=vid, product=pid, interface=interface,
-               serialname=serialno)
-  if sys.stdin.isatty():
-    tty.setraw(sys.stdin.fileno())
-  sobj.run()
-  sobj.wait_until_done()
-  if not sys.stdin.isatty() and args.notty_exit_sleep > 0:
-    time.sleep(args.notty_exit_sleep)
+    sobj = Suart(
+        vendor=vid, product=pid, interface=interface, serialname=serialno
+    )
+    if sys.stdin.isatty():
+        tty.setraw(sys.stdin.fileno())
+    sobj.run()
+    sobj.wait_until_done()
+    if not sys.stdin.isatty() and args.notty_exit_sleep > 0:
+        time.sleep(args.notty_exit_sleep)
 
 
 def main():
-  stdin_isatty = sys.stdin.isatty()
-  if stdin_isatty:
-    fd = sys.stdin.fileno()
-    os.system("stty -echo")
-    old_settings = termios.tcgetattr(fd)
-
-  try:
-    runconsole()
-  finally:
+    stdin_isatty = sys.stdin.isatty()
     if stdin_isatty:
-      termios.tcsetattr(fd, termios.TCSADRAIN, old_settings)
-      os.system("stty echo")
-    # Avoid having the user's shell prompt start mid-line after the final output
-    # from this program.
-    print()
+        fd = sys.stdin.fileno()
+        os.system("stty -echo")
+        old_settings = termios.tcgetattr(fd)
+
+    try:
+        runconsole()
+    finally:
+        if stdin_isatty:
+            termios.tcsetattr(fd, termios.TCSADRAIN, old_settings)
+            os.system("stty echo")
+        # Avoid having the user's shell prompt start mid-line after the final output
+        # from this program.
+        print()
 
 
-if __name__ == '__main__':
-  main()
+if __name__ == "__main__":
+    main()
diff --git a/extra/usb_serial/install b/extra/usb_serial/install
index eba1d2ac83..b49ad990e1 100755
--- a/extra/usb_serial/install
+++ b/extra/usb_serial/install
@@ -1,6 +1,6 @@
 #!/bin/sh -e
 #
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/extra/usb_serial/raiden.c b/extra/usb_serial/raiden.c
index e4720b4357..131cddb00f 100644
--- a/extra/usb_serial/raiden.c
+++ b/extra/usb_serial/raiden.c
@@ -2,7 +2,7 @@
  * USB Serial module for Raiden USB debug serial console forwarding.
  * SubClass and Protocol allocated in go/usb-ids
  *
- * Copyright 2014 The Chromium OS Authors <chromium-os-dev@chromium.org>
+ * Copyright 2014 The ChromiumOS Authors <chromium-os-dev@chromium.org>
  * Author: Anton Staaf <robotboy@chromium.org>
  *
  * This program is free software; you can redistribute it and/or modify
@@ -19,28 +19,25 @@
 
 MODULE_LICENSE("GPL");
 
-#define USB_VENDOR_ID_GOOGLE		0x18d1
-#define USB_SUBCLASS_GOOGLE_SERIAL	0x50
-#define USB_PROTOCOL_GOOGLE_SERIAL	0x01
+#define USB_VENDOR_ID_GOOGLE 0x18d1
+#define USB_SUBCLASS_GOOGLE_SERIAL 0x50
+#define USB_PROTOCOL_GOOGLE_SERIAL 0x01
 
 static struct usb_device_id const ids[] = {
-	{ USB_VENDOR_AND_INTERFACE_INFO(USB_VENDOR_ID_GOOGLE,
-					USB_CLASS_VENDOR_SPEC,
-					USB_SUBCLASS_GOOGLE_SERIAL,
-					USB_PROTOCOL_GOOGLE_SERIAL) },
-        { 0 }
+	{ USB_VENDOR_AND_INTERFACE_INFO(
+		USB_VENDOR_ID_GOOGLE, USB_CLASS_VENDOR_SPEC,
+		USB_SUBCLASS_GOOGLE_SERIAL, USB_PROTOCOL_GOOGLE_SERIAL) },
+	{ 0 }
 };
 
 MODULE_DEVICE_TABLE(usb, ids);
 
-static struct usb_serial_driver device =
-{
-	.driver    = { .owner = THIS_MODULE,
-		       .name  = "Google" },
-	.id_table  = ids,
+static struct usb_serial_driver device = {
+	.driver = { .owner = THIS_MODULE, .name = "Google" },
+	.id_table = ids,
 	.num_ports = 1,
 };
 
-static struct usb_serial_driver * const drivers[] = { &device, NULL };
+static struct usb_serial_driver *const drivers[] = { &device, NULL };
 
 module_usb_serial_driver(drivers, ids);
diff --git a/extra/usb_updater/Makefile b/extra/usb_updater/Makefile
index 1dfbc55645..5a8dc82c28 100644
--- a/extra/usb_updater/Makefile
+++ b/extra/usb_updater/Makefile
@@ -1,4 +1,4 @@
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -19,10 +19,10 @@ CFLAGS  := -std=gnu99 \
         -Wredundant-decls \
         -Wmissing-declarations
 
-ifeq (DEBUG,)
-CFLAGS += -O3
-else
+ifneq ($(DEBUG),)
 CFLAGS += -O0
+else
+CFLAGS += -O3
 endif
 
 #
@@ -52,4 +52,3 @@ clean:
 
 parser_debug: desc_parser.c
 	gcc -g -O0  -DTEST_PARSER desc_parser.c -o dp
-
diff --git a/extra/usb_updater/desc_parser.c b/extra/usb_updater/desc_parser.c
index 5bd996bdda..d75677f0e0 100644
--- a/extra/usb_updater/desc_parser.c
+++ b/extra/usb_updater/desc_parser.c
@@ -1,18 +1,19 @@
 /*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "desc_parser.h"
+
 #include <ctype.h>
 #include <errno.h>
-#include <malloc.h>
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
-#include <sys/stat.h>
 
-#include "desc_parser.h"
+#include <malloc.h>
+#include <sys/stat.h>
 
 static FILE *hash_file_;
 static int line_count_;
@@ -75,8 +76,7 @@ static int get_next_token(char *input, size_t expected_size, char **output)
 	next_colon = strchr(input, ':');
 	if (next_colon)
 		*next_colon = '\0';
-	if (!next_colon || (expected_size &&
-			    strlen(input) != expected_size)) {
+	if (!next_colon || (expected_size && strlen(input) != expected_size)) {
 		fprintf(stderr, "Invalid entry in section %d\n",
 			section_count_);
 		return -EINVAL;
@@ -98,16 +98,15 @@ static int get_hex_value(char *input, char **output)
 
 	value = strtol(input, &e, 16);
 	if ((e && *e) || (strlen(input) > 8)) {
-		fprintf(stderr, "Invalid hex value %s in section %d\n",
-			input, section_count_);
+		fprintf(stderr, "Invalid hex value %s in section %d\n", input,
+			section_count_);
 		return -EINVAL;
 	}
 
 	return value;
 }
 
-static int parse_range(char *next_line,
-		       size_t line_len,
+static int parse_range(char *next_line, size_t line_len,
 		       struct addr_range *parsed_range)
 {
 	char *line_cursor;
@@ -299,7 +298,6 @@ int parser_get_next_range(struct addr_range **range)
 
 	*range = new_range;
 	return 0;
-
 }
 
 int parser_find_board(const char *hash_file_name, const char *board_id)
diff --git a/extra/usb_updater/desc_parser.h b/extra/usb_updater/desc_parser.h
index faa80d1a63..e459927b57 100644
--- a/extra/usb_updater/desc_parser.h
+++ b/extra/usb_updater/desc_parser.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/extra/usb_updater/fw_update.py b/extra/usb_updater/fw_update.py
index 739fa2fe80..08d579e311 100755
--- a/extra/usb_updater/fw_update.py
+++ b/extra/usb_updater/fw_update.py
@@ -1,5 +1,5 @@
 #!/usr/bin/env python
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -12,411 +12,441 @@
 import array
 import json
 import os
+from pprint import pprint
 import struct
 import sys
 import time
-from pprint import pprint
-import usb
-
-
-debug = False
-def debuglog(msg):
-  if debug:
-    print(msg)
-
-def log(msg):
-  print(msg)
-  sys.stdout.flush()
 
+from ecusb.stm32usb import SusbError
+import usb  # pylint:disable=import-error
 
-"""Sends firmware update to CROS EC usb endpoint."""
-
-class Supdate(object):
-  """Class to access firmware update endpoints.
 
-  Usage:
-    d = Supdate()
-
-  Instance Variables:
-    _dev: pyUSB device object
-    _read_ep: pyUSB read endpoint for this interface
-    _write_ep: pyUSB write endpoint for this interface
-  """
-  USB_SUBCLASS_GOOGLE_UPDATE = 0x53
-  USB_CLASS_VENDOR = 0xFF
-
-  def __init__(self):
-    pass
-
-
-  def connect_usb(self, serialname=None):
-    """Initial discovery and connection to USB endpoint.
-
-    This searches for a USB device matching the VID:PID specified
-    in the config file, optionally matching a specified serialname.
-
-    Args:
-      serialname: Find the device with this serial, in case multiple
-          devices are attached.
-
-    Returns:
-      True on success.
-    Raises:
-      Exception on error.
-    """
-    # Find the stm32.
-    vendor = self._brdcfg['vid']
-    product = self._brdcfg['pid']
-
-    dev_g = usb.core.find(idVendor=vendor, idProduct=product, find_all=True)
-    dev_list = list(dev_g)
-    if dev_list is None:
-      raise Exception("Update", "USB device not found")
-
-    # Check if we have multiple stm32s and we've specified the serial.
-    dev = None
-    if serialname:
-      for d in dev_list:
-        if usb.util.get_string(d, d.iSerialNumber) == serialname:
-          dev = d
-          break
-      if dev is None:
-        raise SusbError("USB device(%s) not found" % serialname)
-    else:
-      try:
-        dev = dev_list[0]
-      except:
-        dev = dev_list.next()
-
-    debuglog("Found stm32: %04x:%04x" % (vendor, product))
-    self._dev = dev
-
-    # Get an endpoint instance.
-    try:
-      dev.set_configuration()
-    except:
-      pass
-    cfg = dev.get_active_configuration()
-
-    intf = usb.util.find_descriptor(cfg, custom_match=lambda i: \
-        i.bInterfaceClass==self.USB_CLASS_VENDOR and \
-        i.bInterfaceSubClass==self.USB_SUBCLASS_GOOGLE_UPDATE)
-
-    self._intf = intf
-    debuglog("Interface: %s" % intf)
-    debuglog("InterfaceNumber: %s" % intf.bInterfaceNumber)
-
-    read_ep = usb.util.find_descriptor(
-      intf,
-      # match the first IN endpoint
-      custom_match = \
-      lambda e: \
-          usb.util.endpoint_direction(e.bEndpointAddress) == \
-          usb.util.ENDPOINT_IN
-    )
-
-    self._read_ep = read_ep
-    debuglog("Reader endpoint: 0x%x" % read_ep.bEndpointAddress)
-
-    write_ep = usb.util.find_descriptor(
-      intf,
-      # match the first OUT endpoint
-      custom_match = \
-      lambda e: \
-          usb.util.endpoint_direction(e.bEndpointAddress) == \
-          usb.util.ENDPOINT_OUT
-    )
-
-    self._write_ep = write_ep
-    debuglog("Writer endpoint: 0x%x" % write_ep.bEndpointAddress)
-
-    return True
-
-
-  def wr_command(self, write_list, read_count=1, wtimeout=100, rtimeout=2000):
-    """Write command to logger logic..
-
-    This function writes byte command values list to stm, then reads
-    byte status.
-
-    Args:
-      write_list: list of command byte values [0~255].
-      read_count: number of status byte values to read.
-      wtimeout: mS to wait for write success
-      rtimeout: mS to wait for read success
-
-    Returns:
-      status byte, if one byte is read,
-      byte list, if multiple bytes are read,
-      None, if no bytes are read.
-
-    Interface:
-      write: [command, data ... ]
-      read: [status ]
-    """
-    debuglog("wr_command(write_list=[%s] (%d), read_count=%s)" % (
-          list(bytearray(write_list)), len(write_list), read_count))
-
-    # Clean up args from python style to correct types.
-    write_length = 0
-    if write_list:
-      write_length = len(write_list)
-    if not read_count:
-      read_count = 0
-
-    # Send command to stm32.
-    if write_list:
-      cmd = write_list
-      ret = self._write_ep.write(cmd, wtimeout)
-      debuglog("RET: %s " % ret)
-
-    # Read back response if necessary.
-    if read_count:
-      bytesread = self._read_ep.read(512, rtimeout)
-      debuglog("BYTES: [%s]" % bytesread)
-
-      if len(bytesread) != read_count:
-        debuglog("Unexpected bytes read: %d, expected: %d" % (len(bytesread), read_count))
-        pass
+debug = False
 
-      debuglog("STATUS: 0x%02x" % int(bytesread[0]))
-      if read_count == 1:
-        return bytesread[0]
-      else:
-        return bytesread
 
-    return None
+def debuglog(msg):
+    if debug:
+        print(msg)
 
-  def stop(self):
-    """Finalize system flash and exit."""
-    cmd = struct.pack(">I", 0xB007AB1E)
-    read = self.wr_command(cmd, read_count=4)
 
-    if len(read) == 4:
-      log("Finished flashing")
-      return
+def log(msg):
+    print(msg)
+    sys.stdout.flush()
 
-    raise Exception("Update", "Stop failed [%s]" % read)
 
+"""Sends firmware update to CROS EC usb endpoint."""
 
-  def write_file(self):
-    """Write the update region packet by packet to USB
 
-    This sends write packets of size 128B out, in 32B chunks.
-    Overall, this will write all data in the inactive code region.
+class Supdate(object):
+    """Class to access firmware update endpoints.
 
-    Raises:
-      Exception if write failed or address out of bounds.
-    """
-    region = self._region
-    flash_base = self._brdcfg["flash"]
-    offset = self._base - flash_base
-    if offset != self._brdcfg['regions'][region][0]:
-      raise Exception("Update", "Region %s offset 0x%x != available offset 0x%x" % (
-          region, self._brdcfg['regions'][region][0], offset))
-
-    length = self._brdcfg['regions'][region][1]
-    log("Sending")
-
-    # Go to the correct region in the ec.bin file.
-    self._binfile.seek(offset)
-
-    # Send 32 bytes at a time. Must be less than the endpoint's max packet size.
-    maxpacket = 32
-
-    # While data is left, create update packets.
-    while length > 0:
-      # Update packets are 128B. We can use any number
-      # but the micro must malloc this memory.
-      pagesize = min(length, 128)
-
-      # Packet is:
-      #  packet size: page bytes transferred plus 3 x 32b values header.
-      #  cmd: n/a
-      #  base: flash address to write this packet.
-      #  data: 128B of data to write into flash_base
-      cmd = struct.pack(">III", pagesize + 12, 0, offset + flash_base)
-      read = self.wr_command(cmd, read_count=0)
-
-      # Push 'todo' bytes out the pipe.
-      todo = pagesize
-      while todo > 0:
-        packetsize = min(maxpacket, todo)
-        data = self._binfile.read(packetsize)
-        if len(data) != packetsize:
-          raise Exception("Update", "No more data from file")
-        for i in range(0, 10):
-          try:
-            self.wr_command(data, read_count=0)
-            break
-          except:
-            log("Timeout fail")
-        todo -= packetsize
-      # Done with this packet, move to the next one.
-      length -= pagesize
-      offset += pagesize
-
-      # Validate that the micro thinks it successfully wrote the data.
-      read = self.wr_command("", read_count=4)
-      result = struct.unpack("<I", read)
-      result = result[0]
-      if result != 0:
-        raise Exception("Update", "Upload failed with rc: 0x%x" % result)
-
-
-  def start(self):
-    """Start a transaction and erase currently inactive region.
-
-    This function sends a start command, and receives the base of the
-    preferred inactive region. This could be RW, RW_B,
-    or RO (if there's no RW_B)
-
-    Note that the region is erased here, so you'd better program the RO if
-    you just erased it. TODO(nsanders): Modify the protocol to allow active
-    region select or query before erase.
-    """
+    Usage:
+      d = Supdate()
 
-    # Size is 3 uint32 fields
-    # packet: [packetsize, cmd, base]
-    size = 4 + 4 + 4
-    # Return value is [status, base_addr]
-    expected = 4 + 4
-
-    cmd = struct.pack("<III", size, 0, 0)
-    read = self.wr_command(cmd, read_count=expected)
-
-    if len(read) == 4:
-      raise Exception("Update", "Protocol version 0 not supported")
-    elif len(read) == expected:
-      base, version = struct.unpack(">II", read)
-      log("Update protocol v. %d" % version)
-      log("Available flash region base: %x" % base)
-    else:
-      raise Exception("Update", "Start command returned %d bytes" % len(read))
-
-    if base < 256:
-      raise Exception("Update", "Start returned error code 0x%x" % base)
-
-    self._base = base
-    flash_base = self._brdcfg["flash"]
-    self._offset = self._base - flash_base
-
-    # Find our active region.
-    for region in self._brdcfg['regions']:
-      if (self._offset >= self._brdcfg['regions'][region][0]) and \
-         (self._offset < (self._brdcfg['regions'][region][0] + \
-          self._brdcfg['regions'][region][1])):
-        log("Active region: %s" % region)
-        self._region = region
-
-
-  def load_board(self, brdfile):
-    """Load firmware layout file.
-
-    example as follows:
-    {
-      "board": "servo micro",
-      "vid": 6353,
-      "pid": 20506,
-      "flash": 134217728,
-      "regions": {
-        "RW": [65536, 65536],
-        "PSTATE": [61440, 4096],
-        "RO": [0, 61440]
-      }
-    }
-
-    Args:
-      brdfile: path to board description file.
+    Instance Variables:
+      _dev: pyUSB device object
+      _read_ep: pyUSB read endpoint for this interface
+      _write_ep: pyUSB write endpoint for this interface
     """
-    with open(brdfile) as data_file:
-        data = json.load(data_file)
-
-    # TODO(nsanders): validate this data before moving on.
-    self._brdcfg = data;
-    if debug:
-      pprint(data)
-
-    log("Board is %s" % self._brdcfg['board'])
-    # Cast hex strings to int.
-    self._brdcfg['flash'] = int(self._brdcfg['flash'], 0)
-    self._brdcfg['vid'] = int(self._brdcfg['vid'], 0)
-    self._brdcfg['pid'] = int(self._brdcfg['pid'], 0)
 
-    log("Flash Base is %x" % self._brdcfg['flash'])
-    self._flashsize = 0
-    for region in self._brdcfg['regions']:
-      base = int(self._brdcfg['regions'][region][0], 0)
-      length = int(self._brdcfg['regions'][region][1], 0)
-      log("region %s\tbase:0x%08x size:0x%08x" % (
-          region, base, length))
-      self._flashsize += length
+    USB_SUBCLASS_GOOGLE_UPDATE = 0x53
+    USB_CLASS_VENDOR = 0xFF
 
-      # Convert these to int because json doesn't support hex.
-      self._brdcfg['regions'][region][0] = base
-      self._brdcfg['regions'][region][1] = length
-
-    log("Flash Size: 0x%x" % self._flashsize)
-
-  def load_file(self, binfile):
-    """Open and verify size of the target ec.bin file.
-
-    Args:
-      binfile: path to ec.bin
-
-    Raises:
-      Exception on file not found or filesize not matching.
-    """
-    self._filesize = os.path.getsize(binfile)
-    self._binfile = open(binfile, 'rb')
-
-    if self._filesize != self._flashsize:
-      raise Exception("Update", "Flash size 0x%x != file size 0x%x" % (self._flashsize, self._filesize))
+    def __init__(self):
+        pass
 
+    def connect_usb(self, serialname=None):
+        """Initial discovery and connection to USB endpoint.
+
+        This searches for a USB device matching the VID:PID specified
+        in the config file, optionally matching a specified serialname.
+
+        Args:
+          serialname: Find the device with this serial, in case multiple
+              devices are attached.
+
+        Returns:
+          True on success.
+        Raises:
+          Exception on error.
+        """
+        # Find the stm32.
+        vendor = self._brdcfg["vid"]
+        product = self._brdcfg["pid"]
+
+        dev_g = usb.core.find(idVendor=vendor, idProduct=product, find_all=True)
+        dev_list = list(dev_g)
+        if dev_list is None:
+            raise Exception("Update", "USB device not found")
+
+        # Check if we have multiple stm32s and we've specified the serial.
+        dev = None
+        if serialname:
+            for d in dev_list:
+                if usb.util.get_string(d, d.iSerialNumber) == serialname:
+                    dev = d
+                    break
+            if dev is None:
+                raise SusbError("USB device(%s) not found" % serialname)
+        else:
+            dev = dev_list[0]
+
+        debuglog("Found stm32: %04x:%04x" % (vendor, product))
+        self._dev = dev
+
+        # Get an endpoint instance.
+        try:
+            dev.set_configuration()
+        except:
+            pass
+        cfg = dev.get_active_configuration()
+
+        intf = usb.util.find_descriptor(
+            cfg,
+            custom_match=lambda i: i.bInterfaceClass == self.USB_CLASS_VENDOR
+            and i.bInterfaceSubClass == self.USB_SUBCLASS_GOOGLE_UPDATE,
+        )
+
+        self._intf = intf
+        debuglog("Interface: %s" % intf)
+        debuglog("InterfaceNumber: %s" % intf.bInterfaceNumber)
+
+        read_ep = usb.util.find_descriptor(
+            intf,
+            # match the first IN endpoint
+            custom_match=lambda e: usb.util.endpoint_direction(
+                e.bEndpointAddress
+            )
+            == usb.util.ENDPOINT_IN,
+        )
+
+        self._read_ep = read_ep
+        debuglog("Reader endpoint: 0x%x" % read_ep.bEndpointAddress)
+
+        write_ep = usb.util.find_descriptor(
+            intf,
+            # match the first OUT endpoint
+            custom_match=lambda e: usb.util.endpoint_direction(
+                e.bEndpointAddress
+            )
+            == usb.util.ENDPOINT_OUT,
+        )
+
+        self._write_ep = write_ep
+        debuglog("Writer endpoint: 0x%x" % write_ep.bEndpointAddress)
+
+        return True
+
+    def wr_command(self, write_list, read_count=1, wtimeout=100, rtimeout=2000):
+        """Write command to logger logic..
+
+        This function writes byte command values list to stm, then reads
+        byte status.
+
+        Args:
+          write_list: list of command byte values [0~255].
+          read_count: number of status byte values to read.
+          wtimeout: mS to wait for write success
+          rtimeout: mS to wait for read success
+
+        Returns:
+          status byte, if one byte is read,
+          byte list, if multiple bytes are read,
+          None, if no bytes are read.
+
+        Interface:
+          write: [command, data ... ]
+          read: [status ]
+        """
+        debuglog(
+            "wr_command(write_list=[%s] (%d), read_count=%s)"
+            % (list(bytearray(write_list)), len(write_list), read_count)
+        )
+
+        # Clean up args from python style to correct types.
+        write_length = 0
+        if write_list:
+            write_length = len(write_list)
+        if not read_count:
+            read_count = 0
+
+        # Send command to stm32.
+        if write_list:
+            cmd = write_list
+            ret = self._write_ep.write(cmd, wtimeout)
+            debuglog("RET: %s " % ret)
+
+        # Read back response if necessary.
+        if read_count:
+            bytesread = self._read_ep.read(512, rtimeout)
+            debuglog("BYTES: [%s]" % bytesread)
+
+            if len(bytesread) != read_count:
+                debuglog(
+                    "Unexpected bytes read: %d, expected: %d"
+                    % (len(bytesread), read_count)
+                )
+                pass
+
+            debuglog("STATUS: 0x%02x" % int(bytesread[0]))
+            if read_count == 1:
+                return bytesread[0]
+            else:
+                return bytesread
+
+        return None
+
+    def stop(self):
+        """Finalize system flash and exit."""
+        cmd = struct.pack(">I", 0xB007AB1E)
+        read = self.wr_command(cmd, read_count=4)
+
+        if len(read) == 4:
+            log("Finished flashing")
+            return
+
+        raise Exception("Update", "Stop failed [%s]" % read)
+
+    def write_file(self):
+        """Write the update region packet by packet to USB
+
+        This sends write packets of size 128B out, in 32B chunks.
+        Overall, this will write all data in the inactive code region.
+
+        Raises:
+          Exception if write failed or address out of bounds.
+        """
+        region = self._region
+        flash_base = self._brdcfg["flash"]
+        offset = self._base - flash_base
+        if offset != self._brdcfg["regions"][region][0]:
+            raise Exception(
+                "Update",
+                "Region %s offset 0x%x != available offset 0x%x"
+                % (region, self._brdcfg["regions"][region][0], offset),
+            )
+
+        length = self._brdcfg["regions"][region][1]
+        log("Sending")
+
+        # Go to the correct region in the ec.bin file.
+        self._binfile.seek(offset)
+
+        # Send 32 bytes at a time. Must be less than the endpoint's max packet size.
+        maxpacket = 32
+
+        # While data is left, create update packets.
+        while length > 0:
+            # Update packets are 128B. We can use any number
+            # but the micro must malloc this memory.
+            pagesize = min(length, 128)
+
+            # Packet is:
+            #  packet size: page bytes transferred plus 3 x 32b values header.
+            #  cmd: n/a
+            #  base: flash address to write this packet.
+            #  data: 128B of data to write into flash_base
+            cmd = struct.pack(">III", pagesize + 12, 0, offset + flash_base)
+            read = self.wr_command(cmd, read_count=0)
+
+            # Push 'todo' bytes out the pipe.
+            todo = pagesize
+            while todo > 0:
+                packetsize = min(maxpacket, todo)
+                data = self._binfile.read(packetsize)
+                if len(data) != packetsize:
+                    raise Exception("Update", "No more data from file")
+                for i in range(0, 10):
+                    try:
+                        self.wr_command(data, read_count=0)
+                        break
+                    except:
+                        log("Timeout fail")
+                todo -= packetsize
+            # Done with this packet, move to the next one.
+            length -= pagesize
+            offset += pagesize
+
+            # Validate that the micro thinks it successfully wrote the data.
+            read = self.wr_command("".encode(), read_count=4)
+            result = struct.unpack("<I", read)
+            result = result[0]
+            if result != 0:
+                raise Exception(
+                    "Update", "Upload failed with rc: 0x%x" % result
+                )
+
+    def start(self):
+        """Start a transaction and erase currently inactive region.
+
+        This function sends a start command, and receives the base of the
+        preferred inactive region. This could be RW, RW_B,
+        or RO (if there's no RW_B)
+
+        Note that the region is erased here, so you'd better program the RO if
+        you just erased it. TODO(nsanders): Modify the protocol to allow active
+        region select or query before erase.
+        """
+
+        # Size is 3 uint32 fields
+        # packet: [packetsize, cmd, base]
+        size = 4 + 4 + 4
+        # Return value is [status, base_addr]
+        expected = 4 + 4
+
+        cmd = struct.pack("<III", size, 0, 0)
+        read = self.wr_command(cmd, read_count=expected)
+
+        if len(read) == 4:
+            raise Exception("Update", "Protocol version 0 not supported")
+        elif len(read) == expected:
+            base, version = struct.unpack(">II", read)
+            log("Update protocol v. %d" % version)
+            log("Available flash region base: %x" % base)
+        else:
+            raise Exception(
+                "Update", "Start command returned %d bytes" % len(read)
+            )
+
+        if base < 256:
+            raise Exception("Update", "Start returned error code 0x%x" % base)
+
+        self._base = base
+        flash_base = self._brdcfg["flash"]
+        self._offset = self._base - flash_base
+
+        # Find our active region.
+        for region in self._brdcfg["regions"]:
+            if (self._offset >= self._brdcfg["regions"][region][0]) and (
+                self._offset
+                < (
+                    self._brdcfg["regions"][region][0]
+                    + self._brdcfg["regions"][region][1]
+                )
+            ):
+                log("Active region: %s" % region)
+                self._region = region
+
+    def load_board(self, brdfile):
+        """Load firmware layout file.
+
+        example as follows:
+        {
+          "board": "servo micro",
+          "vid": 6353,
+          "pid": 20506,
+          "flash": 134217728,
+          "regions": {
+            "RW": [65536, 65536],
+            "PSTATE": [61440, 4096],
+            "RO": [0, 61440]
+          }
+        }
+
+        Args:
+          brdfile: path to board description file.
+        """
+        with open(brdfile) as data_file:
+            data = json.load(data_file)
+
+        # TODO(nsanders): validate this data before moving on.
+        self._brdcfg = data
+        if debug:
+            pprint(data)
+
+        log("Board is %s" % self._brdcfg["board"])
+        # Cast hex strings to int.
+        self._brdcfg["flash"] = int(self._brdcfg["flash"], 0)
+        self._brdcfg["vid"] = int(self._brdcfg["vid"], 0)
+        self._brdcfg["pid"] = int(self._brdcfg["pid"], 0)
+
+        log("Flash Base is %x" % self._brdcfg["flash"])
+        self._flashsize = 0
+        for region in self._brdcfg["regions"]:
+            base = int(self._brdcfg["regions"][region][0], 0)
+            length = int(self._brdcfg["regions"][region][1], 0)
+            log("region %s\tbase:0x%08x size:0x%08x" % (region, base, length))
+            self._flashsize += length
+
+            # Convert these to int because json doesn't support hex.
+            self._brdcfg["regions"][region][0] = base
+            self._brdcfg["regions"][region][1] = length
+
+        log("Flash Size: 0x%x" % self._flashsize)
+
+    def load_file(self, binfile):
+        """Open and verify size of the target ec.bin file.
+
+        Args:
+          binfile: path to ec.bin
+
+        Raises:
+          Exception on file not found or filesize not matching.
+        """
+        self._filesize = os.path.getsize(binfile)
+        self._binfile = open(binfile, "rb")
+
+        if self._filesize != self._flashsize:
+            raise Exception(
+                "Update",
+                "Flash size 0x%x != file size 0x%x"
+                % (self._flashsize, self._filesize),
+            )
 
 
 # Generate command line arguments
 parser = argparse.ArgumentParser(description="Update firmware over usb")
-parser.add_argument('-b', '--board', type=str, help="Board configuration json file", default="board.json")
-parser.add_argument('-f', '--file', type=str, help="Complete ec.bin file", default="ec.bin")
-parser.add_argument('-s', '--serial', type=str, help="Serial number", default="")
-parser.add_argument('-l', '--list', action="store_true", help="List regions")
-parser.add_argument('-v', '--verbose', action="store_true", help="Chatty output")
+parser.add_argument(
+    "-b",
+    "--board",
+    type=str,
+    help="Board configuration json file",
+    default="board.json",
+)
+parser.add_argument(
+    "-f", "--file", type=str, help="Complete ec.bin file", default="ec.bin"
+)
+parser.add_argument(
+    "-s", "--serial", type=str, help="Serial number", default=""
+)
+parser.add_argument("-l", "--list", action="store_true", help="List regions")
+parser.add_argument(
+    "-v", "--verbose", action="store_true", help="Chatty output"
+)
+
 
 def main():
-  global debug
-  args = parser.parse_args()
+    global debug
+    args = parser.parse_args()
 
+    brdfile = args.board
+    serial = args.serial
+    binfile = args.file
+    if args.verbose:
+        debug = True
 
-  brdfile = args.board
-  serial = args.serial
-  binfile = args.file
-  if args.verbose:
-    debug = True
+    with open(brdfile) as data_file:
+        names = json.load(data_file)
 
-  with open(brdfile) as data_file:
-    names = json.load(data_file)
+    p = Supdate()
+    p.load_board(brdfile)
+    p.connect_usb(serialname=serial)
+    p.load_file(binfile)
 
-  p = Supdate()
-  p.load_board(brdfile)
-  p.connect_usb(serialname=serial)
-  p.load_file(binfile)
+    # List solely prints the config.
+    if args.list:
+        return
 
-  # List solely prints the config.
-  if (args.list):
-    return
+    # Start transfer and erase.
+    p.start()
+    # Upload the bin file
+    log("Uploading %s" % binfile)
+    p.write_file()
 
-  # Start transfer and erase.
-  p.start()
-  # Upload the bin file
-  log("Uploading %s" % binfile)
-  p.write_file()
+    # Finalize
+    log("Done. Finalizing.")
+    p.stop()
 
-  # Finalize
-  log("Done. Finalizing.")
-  p.stop()
 
 if __name__ == "__main__":
-  main()
-
-
+    main()
diff --git a/extra/usb_updater/sample_descriptor b/extra/usb_updater/sample_descriptor
index 1566e9e2e1..3be408b642 100644
--- a/extra/usb_updater/sample_descriptor
+++ b/extra/usb_updater/sample_descriptor
@@ -1,4 +1,4 @@
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/extra/usb_updater/servo_updater.py b/extra/usb_updater/servo_updater.py
index 80a63636d8..e53eaac85e 100755
--- a/extra/usb_updater/servo_updater.py
+++ b/extra/usb_updater/servo_updater.py
@@ -1,321 +1,513 @@
 #!/usr/bin/env python
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 # Note: This is a py2/3 compatible file.
 
+"""USB updater tool for servo and similar boards."""
+
 from __future__ import print_function
 
 import argparse
-import errno
+import json
 import os
 import re
 import subprocess
 import time
-import tempfile
 
-import json
-
-import fw_update
+from ecusb import tiny_servod
 import ecusb.tiny_servo_common as c
+import fw_update
 
 
 class ServoUpdaterException(Exception):
-  """Raised on exceptions generated by servo_updater."""
+    """Raised on exceptions generated by servo_updater."""
+
 
-BOARD_C2D2 = 'c2d2'
-BOARD_SERVO_MICRO = 'servo_micro'
-BOARD_SERVO_V4 = 'servo_v4'
-BOARD_SERVO_V4P1 = 'servo_v4p1'
-BOARD_SWEETBERRY = 'sweetberry'
+BOARD_C2D2 = "c2d2"
+BOARD_SERVO_MICRO = "servo_micro"
+BOARD_SERVO_V4 = "servo_v4"
+BOARD_SERVO_V4P1 = "servo_v4p1"
+BOARD_SWEETBERRY = "sweetberry"
 
 DEFAULT_BOARD = BOARD_SERVO_V4
 
-DEFAULT_BASE_PATH = '/usr/'
-TEST_IMAGE_BASE_PATH = '/usr/local/'
+# These lists are to facilitate exposing choices in the command-line tool
+# below.
+BOARDS = [
+    BOARD_C2D2,
+    BOARD_SERVO_MICRO,
+    BOARD_SERVO_V4,
+    BOARD_SERVO_V4P1,
+    BOARD_SWEETBERRY,
+]
+
+# Servo firmware bundles four channels of firmware. We need to make sure the
+# user does not request a non-existing channel, so keep the lists around to
+# guard on command-line usage.
+
+DEFAULT_CHANNEL = STABLE_CHANNEL = "stable"
+
+PREV_CHANNEL = "prev"
 
-COMMON_PATH = 'share/servo_updater'
+# The ordering here matters. From left to right it's the channel that the user
+# is most likely to be running. This is used to inform and warn the user if
+# there are issues. e.g. if the all channels are the same, we want to let the
+# user know they are running the 'stable' version before letting them know they
+# are running 'dev' or even 'alpah' which (while true) might cause confusion.
+
+CHANNELS = [DEFAULT_CHANNEL, PREV_CHANNEL, "dev", "alpha"]
+
+DEFAULT_BASE_PATH = "/usr/"
+TEST_IMAGE_BASE_PATH = "/usr/local/"
+
+COMMON_PATH = "share/servo_updater"
 
 FIRMWARE_DIR = "firmware/"
 CONFIGS_DIR = "configs/"
 
+RETRIES_COUNT = 10
+RETRIES_DELAY = 1
+
+
+def do_with_retries(func, *args):
+    """Try a function several times
+
+    Call function passed as argument and check if no error happened.
+    If exception was raised by function,
+    it will be retried up to RETRIES_COUNT times.
+
+    Args:
+      func: function that will be called
+      args: arguments passed to 'func'
+
+    Returns:
+      If call to function was successful, its result will be returned.
+      If retries count was exceeded, exception will be raised.
+    """
+
+    retry = 0
+    while retry < RETRIES_COUNT:
+        try:
+            return func(*args)
+        except Exception as e:
+            print("Retrying function %s: %s" % (func.__name__, e))
+            retry = retry + 1
+            time.sleep(RETRIES_DELAY)
+            continue
+
+    raise Exception(
+        "'{}' failed after {} retries".format(func.__name__, RETRIES_COUNT)
+    )
+
+
 def flash(brdfile, serialno, binfile):
-  """Call fw_update to upload to updater USB endpoint."""
-  p = fw_update.Supdate()
-  p.load_board(brdfile)
-  p.connect_usb(serialname=serialno)
-  p.load_file(binfile)
-
-  # Start transfer and erase.
-  p.start()
-  # Upload the bin file
-  print("Uploading %s" % binfile)
-  p.write_file()
-
-  # Finalize
-  print("Done. Finalizing.")
-  p.stop()
+    """Call fw_update to upload to updater USB endpoint.
+
+    Args:
+      brdfile: path to board configuration file
+      serialno: device serial number
+      binfile: firmware file
+    """
+
+    p = fw_update.Supdate()
+    p.load_board(brdfile)
+    p.connect_usb(serialname=serialno)
+    p.load_file(binfile)
+
+    # Start transfer and erase.
+    p.start()
+    # Upload the bin file
+    print("Uploading %s" % binfile)
+    p.write_file()
+
+    # Finalize
+    print("Done. Finalizing.")
+    p.stop()
+
 
 def flash2(vidpid, serialno, binfile):
-  """Call fw update via usb_updater2 commandline."""
-  tool = 'usb_updater2'
-  cmd = "%s -d %s" % (tool, vidpid)
-  if serialno:
-    cmd += " -S %s" % serialno
-  cmd += " -n"
-  cmd += " %s" % binfile
-
-  print(cmd)
-  help_cmd = '%s --help' % tool
-  with open('/dev/null') as devnull:
-    valid_check = subprocess.call(help_cmd.split(), stdout=devnull,
-                                  stderr=devnull)
-  if valid_check:
-    raise ServoUpdaterException('%s exit with res = %d. Make sure the tool '
-                                'is available on the device.' % (help_cmd,
-                                                                 valid_check))
-  res = subprocess.call(cmd.split())
-
-  if res in (0, 1, 2):
-    return res
-  else:
-    raise ServoUpdaterException("%s exit with res = %d" % (cmd, res))
-
-def connect(vidpid, iface, serialno, debuglog=False):
-  """Connect to console.
-
-  Args:
-    vidpid: vidpid of desired device.
-    iface: interface to connect.
-    serialno: serial number, to differentiate multiple devices.
-    debuglog: do chatty log.
-
-  Returns:
-    a connected pty object.
-  """
-  # Make sure device is up.
-  c.wait_for_usb(vidpid, serialname=serialno)
-
-  # make a console.
-  pty = c.setup_tinyservod(vidpid, iface,
-            serialname=serialno, debuglog=debuglog)
-
-  return pty
-
-def select(vidpid, iface, serialno, region, debuglog=False):
-  """Ensure the servo is in the expected ro/rw partition."""
-
-  if region not in ["rw", "ro"]:
-    raise Exception("Region must be ro or rw")
-
-  pty = connect(vidpid, iface, serialno)
-
-  if region is "ro":
-    cmd = "reboot"
-  else:
-    cmd = "sysjump %s" % region
-  pty._issue_cmd(cmd)
-  time.sleep(1)
-  pty.close()
-
-def do_version(vidpid, iface, serialno):
-  """Check version via ec console 'pty'.
-
-  Args:
-    see connect()
-
-  Returns:
-    detected version number
-
-  Commands are:
-  # > version
-  # ...
-  # Build:   tigertail_v1.1.6749-74d1a312e
-  """
-  pty = connect(vidpid, iface, serialno)
-
-  cmd = '\r\nversion\r\n'
-  regex = 'Build:\s+(\S+)[\r\n]+'
-
-  results = pty._issue_cmd_get_results(cmd, [regex])[0]
-  pty.close()
-
-  return results[1].strip(' \t\r\n\0')
-
-def do_updater_version(vidpid, iface, serialno):
-  """Check whether this uses python updater or c++ updater
-
-  Args:
-    see connect()
-
-  Returns:
-    updater version number. 2 or 6.
-  """
-  vers = do_version(vidpid, iface, serialno)
-
-  # Servo versions below 58 are from servo-9040.B. Versions starting with _v2
-  # are newer than anything _v1, no need to check the exact number. Updater
-  # version is not directly queryable.
-  if re.search('_v[2-9]\.\d', vers):
-    return 6
-  m = re.search('_v1\.1\.(\d\d\d\d)', vers)
-  if m:
-    version_number = int(m.group(1))
-    if version_number < 5800:
-      return 2
-    else:
-      return 6
-  raise ServoUpdaterException(
-      "Can't determine updater target from vers: [%s]" % vers)
-
-def findfiles(cname, fname):
-  """Select config and firmware binary files.
-
-  This checks default file names and paths.
-  In: /usr/share/servo_updater/[firmware|configs]
-  check for board.json, board.bin
-
-  Args:
-    cname: board name, or config name. eg. "servo_v4" or "servo_v4.json"
-    fname: firmware binary name. Can be None to try default.
-  Returns:
-    cname, fname: validated filenames selected from the path.
-  """
-  for p in (DEFAULT_BASE_PATH, TEST_IMAGE_BASE_PATH):
-    updater_path = os.path.join(p, COMMON_PATH)
-    if os.path.exists(updater_path):
-      break
-  else:
-    raise ServoUpdaterException('servo_updater/ dir not found in known spots.')
-
-  firmware_path = os.path.join(updater_path, FIRMWARE_DIR)
-  configs_path = os.path.join(updater_path, CONFIGS_DIR)
-
-  for p in (firmware_path, configs_path):
-    if not os.path.exists(p):
-      raise ServoUpdaterException('Could not find required path %r' % p)
-
-  if not os.path.isfile(cname):
-    # If not an existing file, try checking on the default path.
-    newname = os.path.join(configs_path, cname)
-    if os.path.isfile(newname):
-      cname = newname
+    """Call fw update via usb_updater2 commandline.
+
+    Args:
+      vidpid: vendor id and product id of device
+      serialno: device serial number (optional)
+      binfile: firmware file
+    """
+
+    tool = "usb_updater2"
+    cmd = "%s -d %s" % (tool, vidpid)
+    if serialno:
+        cmd += " -S %s" % serialno
+    cmd += " -n"
+    cmd += " %s" % binfile
+
+    print(cmd)
+    help_cmd = "%s --help" % tool
+    with open("/dev/null") as devnull:
+        valid_check = subprocess.call(
+            help_cmd.split(), stdout=devnull, stderr=devnull
+        )
+    if valid_check:
+        raise ServoUpdaterException(
+            "%s exit with res = %d. Make sure the tool "
+            "is available on the device." % (help_cmd, valid_check)
+        )
+    res = subprocess.call(cmd.split())
+
+    if res in (0, 1, 2):
+        return res
     else:
-      # Try appending ".json" to convert board name to config file.
-      cname = newname + ".json"
-    if not os.path.isfile(cname):
-      raise ServoUpdaterException("Can't find config file: %s." % cname)
+        raise ServoUpdaterException("%s exit with res = %d" % (cmd, res))
 
-  if not fname:
-    # If None, try to infer board name from config.
-    with open(cname) as data_file:
-      data = json.load(data_file)
-    boardname = data['board']
 
-    binary_file = boardname + ".bin"
-    newname = os.path.join(firmware_path, binary_file)
-    if os.path.isfile(newname):
-      fname = newname
+def select(tinys, region):
+    """Jump to specified boot region
+
+    Ensure the servo is in the expected ro/rw region.
+    This function jumps to the required region and verify if jump was
+    successful by executing 'sysinfo' command and reading current region.
+    If response was not received or region is invalid, exception is raised.
+
+    Args:
+      tinys: TinyServod object
+      region: region to jump to, only "rw" and "ro" is allowed
+    """
+
+    if region not in ["rw", "ro"]:
+        raise Exception("Region must be ro or rw")
+
+    if region == "ro":
+        cmd = "reboot"
     else:
-      raise ServoUpdaterException("Can't find firmware binary: %s." % binary_file)
-  elif not os.path.isfile(fname):
-    # If a name is specified but not found, try the default path.
-    newname = os.path.join(firmware_path, fname)
-    if os.path.isfile(newname):
-      fname = newname
+        cmd = "sysjump %s" % region
+
+    tinys.pty._issue_cmd(cmd)
+
+    tinys.close()
+    time.sleep(2)
+    tinys.reinitialize()
+
+    res = tinys.pty._issue_cmd_get_results("sysinfo", [r"Copy:[\s]+(RO|RW)"])
+    current_region = res[0][1].lower()
+    if current_region != region:
+        raise Exception("Invalid region: %s/%s" % (current_region, region))
+
+
+def do_version(tinys):
+    """Check version via ec console 'pty'.
+
+    Args:
+      tinys: TinyServod object
+
+    Returns:
+      detected version number
+
+    Commands are:
+    # > version
+    # ...
+    # Build:   tigertail_v1.1.6749-74d1a312e
+    """
+    cmd = "version"
+    regex = r"Build:\s+(\S+)[\r\n]+"
+
+    results = tinys.pty._issue_cmd_get_results(cmd, [regex])[0]
+
+    return results[1].strip(" \t\r\n\0")
+
+
+def do_updater_version(tinys):
+    """Check whether this uses python updater or c++ updater
+
+    Args:
+      tinys: TinyServod object
+
+    Returns:
+      updater version number. 2 or 6.
+    """
+    vers = do_version(tinys)
+
+    # Servo versions below 58 are from servo-9040.B. Versions starting with _v2
+    # are newer than anything _v1, no need to check the exact number. Updater
+    # version is not directly queryable.
+    if re.search(r"_v[2-9]\.\d", vers):
+        return 6
+    m = re.search(r"_v1\.1\.(\d\d\d\d)", vers)
+    if m:
+        version_number = int(m.group(1))
+        if version_number < 5800:
+            return 2
+        else:
+            return 6
+    raise ServoUpdaterException(
+        "Can't determine updater target from vers: [%s]" % vers
+    )
+
+
+def _extract_version(boardname, binfile):
+    """Find the version string from |binfile|.
+
+    Args:
+      boardname: the name of the board, eg. "servo_micro"
+      binfile: path to the binary to search
+
+    Returns:
+      the version string.
+    """
+    if boardname is None:
+        # cannot extract the version if the name is None
+        return None
+    rawstrings = subprocess.check_output(
+        ["cbfstool", binfile, "read", "-r", "RO_FRID", "-f", "/dev/stdout"],
+        **c.get_subprocess_args()
+    )
+    m = re.match(r"%s_v\S+" % boardname, rawstrings)
+    if m:
+        newvers = m.group(0).strip(" \t\r\n\0")
     else:
-      raise ServoUpdaterException("Can't find file: %s." % fname)
-
-  return cname, fname
+        raise ServoUpdaterException(
+            "Can't find version from file: %s." % binfile
+        )
+
+    return newvers
+
+
+def get_firmware_channel(bname, version):
+    """Find out which channel |version| for |bname| came from.
+
+    Args:
+      bname: board name
+      version: current version string
+
+    Returns:
+      one of the channel names if |version| came from one of those, or None
+    """
+    for channel in CHANNELS:
+        # Pass |bname| as cname to find the board specific file, and pass None as
+        # fname to ensure the default directory is searched
+        _, _, vers = get_files_and_version(bname, None, channel=channel)
+        if version == vers:
+            return channel
+    # None of the channels matched. This firmware is currently unknown.
+    return None
+
+
+def get_files_and_version(cname, fname=None, channel=DEFAULT_CHANNEL):
+    """Select config and firmware binary files.
+
+    This checks default file names and paths.
+    In: /usr/share/servo_updater/[firmware|configs]
+    check for board.json, board.bin
+
+    Args:
+      cname: board name, or config name. eg. "servo_v4" or "servo_v4.json"
+      fname: firmware binary name. Can be None to try default.
+      channel: the channel requested for servo firmware. See |CHANNELS| above.
+
+    Returns:
+      cname, fname, version: validated filenames selected from the path.
+    """
+    for p in (DEFAULT_BASE_PATH, TEST_IMAGE_BASE_PATH):
+        updater_path = os.path.join(p, COMMON_PATH)
+        if os.path.exists(updater_path):
+            break
+    else:
+        raise ServoUpdaterException(
+            "servo_updater/ dir not found in known spots."
+        )
 
-def find_available_version(boardname, binfile):
-  """Find the version string from the binary file.
+    firmware_path = os.path.join(updater_path, FIRMWARE_DIR)
+    configs_path = os.path.join(updater_path, CONFIGS_DIR)
 
-  Args:
-    boardname: the name of the board, eg. "servo_micro"
-    binfile: the binary to search
+    for p in (firmware_path, configs_path):
+        if not os.path.exists(p):
+            raise ServoUpdaterException("Could not find required path %r" % p)
 
-  Returns:
-    the version string.
-  """
-  rawstrings = subprocess.check_output(
-      ['cbfstool', binfile, 'read', '-r', 'RO_FRID', '-f', '/dev/stdout'],
-      **c.get_subprocess_args())
-  m = re.match(r'%s_v\S+' % boardname, rawstrings)
-  if m:
-    newvers = m.group(0).strip(' \t\r\n\0')
-  else:
-    raise ServoUpdaterException("Can't find version from file: %s." % binfile)
+    if not os.path.isfile(cname):
+        # If not an existing file, try checking on the default path.
+        newname = os.path.join(configs_path, cname)
+        if os.path.isfile(newname):
+            cname = newname
+        else:
+            # Try appending ".json" to convert board name to config file.
+            cname = newname + ".json"
+        if not os.path.isfile(cname):
+            raise ServoUpdaterException("Can't find config file: %s." % cname)
+
+    # Always retrieve the boardname
+    with open(cname) as data_file:
+        data = json.load(data_file)
+    boardname = data["board"]
+
+    if not fname:
+        # If no |fname| supplied, look for the default locations with the board
+        # and channel requested.
+        binary_file = "%s.%s.bin" % (boardname, channel)
+        newname = os.path.join(firmware_path, binary_file)
+        if os.path.isfile(newname):
+            fname = newname
+        else:
+            raise ServoUpdaterException(
+                "Can't find firmware binary: %s." % binary_file
+            )
+    elif not os.path.isfile(fname):
+        # If a name is specified but not found, try the default path.
+        newname = os.path.join(firmware_path, fname)
+        if os.path.isfile(newname):
+            fname = newname
+        else:
+            raise ServoUpdaterException("Can't find file: %s." % fname)
+
+    # Lastly, retrieve the version as well for decision making, debug, and
+    # informational purposes.
+    binvers = _extract_version(boardname, fname)
+
+    return cname, fname, binvers
 
-  return newvers
 
 def main():
-  parser = argparse.ArgumentParser(description="Image a servo micro device")
-  parser.add_argument('-s', '--serialno', type=str,
-      help="serial number to program", default=None)
-  parser.add_argument('-b', '--board', type=str,
-      help="Board configuration json file", default=DEFAULT_BOARD)
-  parser.add_argument('-f', '--file', type=str,
-      help="Complete ec.bin file", default=None)
-  parser.add_argument('--force', action="store_true",
-      help="Update even if version match", default=False)
-  parser.add_argument('-v', '--verbose', action="store_true",
-      help="Chatty output")
-  parser.add_argument('-r', '--reboot', action="store_true",
-      help="Always reboot, even after probe.")
-
-  args = parser.parse_args()
-
-  brdfile, binfile = findfiles(args.board, args.file)
-
-  serialno = args.serialno
-  debuglog = (args.verbose is True)
-
-  with open(brdfile) as data_file:
-      data = json.load(data_file)
-
-  vidpid = "%04x:%04x" % (int(data['vid'], 0), int(data['pid'], 0))
-  iface = int(data['console'], 0)
-  boardname = data['board']
-
-  if not args.force:
-    vers = do_version(vidpid, iface, serialno)
-    print("Current %s version is   %s" % (boardname, vers))
-
-    newvers = find_available_version(boardname, binfile)
-    print("Available %s version is %s" % (boardname, newvers))
-
-    if newvers == vers:
-      print("No version update needed")
-      if args.reboot is True:
-        select(vidpid, iface, serialno, "ro", debuglog=debuglog)
-      return
+    parser = argparse.ArgumentParser(description="Image a servo device")
+    parser.add_argument(
+        "-p",
+        "--print",
+        dest="print_only",
+        action="store_true",
+        default=False,
+        help="only print available firmware for board/channel",
+    )
+    parser.add_argument(
+        "-s",
+        "--serialno",
+        type=str,
+        help="serial number to program",
+        default=None,
+    )
+    parser.add_argument(
+        "-b",
+        "--board",
+        type=str,
+        help="Board configuration json file",
+        default=DEFAULT_BOARD,
+        choices=BOARDS,
+    )
+    parser.add_argument(
+        "-c",
+        "--channel",
+        type=str,
+        help="Firmware channel to use",
+        default=DEFAULT_CHANNEL,
+        choices=CHANNELS,
+    )
+    parser.add_argument(
+        "-f", "--file", type=str, help="Complete ec.bin file", default=None
+    )
+    parser.add_argument(
+        "--force",
+        action="store_true",
+        help="Update even if version match",
+        default=False,
+    )
+    parser.add_argument(
+        "-v", "--verbose", action="store_true", help="Chatty output"
+    )
+    parser.add_argument(
+        "-r",
+        "--reboot",
+        action="store_true",
+        help="Always reboot, even after probe.",
+    )
+
+    args = parser.parse_args()
+
+    brdfile, binfile, newvers = get_files_and_version(
+        args.board, args.file, args.channel
+    )
+
+    # If the user only cares about the information then just print it here,
+    # and exit.
+    if args.print_only:
+        output = ("board: %s\nchannel: %s\nfirmware: %s") % (
+            args.board,
+            args.channel,
+            newvers,
+        )
+        print(output)
+        return
+
+    serialno = args.serialno
+
+    with open(brdfile) as data_file:
+        data = json.load(data_file)
+    vid, pid = int(data["vid"], 0), int(data["pid"], 0)
+    vidpid = "%04x:%04x" % (vid, pid)
+    iface = int(data["console"], 0)
+    boardname = data["board"]
+
+    # Make sure device is up.
+    print("===== Waiting for USB device =====")
+    c.wait_for_usb(vidpid, serialname=serialno)
+    # We need a tiny_servod to query some information. Set it up first.
+    tinys = tiny_servod.TinyServod(vid, pid, iface, serialno, args.verbose)
+
+    if not args.force:
+        vers = do_version(tinys)
+        print("Current %s version is   %s" % (boardname, vers))
+        print("Available %s version is %s" % (boardname, newvers))
+
+        if newvers == vers:
+            print("No version update needed")
+            if args.reboot:
+                select(tinys, "ro")
+            return
+        else:
+            print("Updating to recommended version.")
+
+    # Make sure the servo MCU is in RO
+    print("===== Jumping to RO =====")
+    do_with_retries(select, tinys, "ro")
+
+    print("===== Flashing RW =====")
+    vers = do_with_retries(do_updater_version, tinys)
+    # To make sure that the tiny_servod here does not interfere with other
+    # processes, close it out.
+    tinys.close()
+
+    if vers == 2:
+        flash(brdfile, serialno, binfile)
+    elif vers == 6:
+        do_with_retries(flash2, vidpid, serialno, binfile)
     else:
-      print("Updating to recommended version.")
+        raise ServoUpdaterException("Can't detect updater version")
 
+    # Make sure device is up.
+    c.wait_for_usb(vidpid, serialname=serialno)
+    # After we have made sure that it's back/available, reconnect the tiny servod.
+    tinys.reinitialize()
 
-  select(vidpid, iface, serialno, "ro", debuglog=debuglog)
+    # Make sure the servo MCU is in RW
+    print("===== Jumping to RW =====")
+    do_with_retries(select, tinys, "rw")
 
-  vers = do_updater_version(vidpid, iface, serialno)
-  if vers == 2:
-    flash(brdfile, serialno, binfile)
-  elif vers == 6:
-    flash2(vidpid, serialno, binfile)
-  else:
-    raise ServoUpdaterException("Can't detect updater version")
+    print("===== Flashing RO =====")
+    vers = do_with_retries(do_updater_version, tinys)
+
+    if vers == 2:
+        flash(brdfile, serialno, binfile)
+    elif vers == 6:
+        do_with_retries(flash2, vidpid, serialno, binfile)
+    else:
+        raise ServoUpdaterException("Can't detect updater version")
 
-  select(vidpid, iface, serialno, "rw", debuglog=debuglog)
+    # Make sure the servo MCU is in RO
+    print("===== Rebooting =====")
+    do_with_retries(select, tinys, "ro")
+    # Perform additional reboot to free USB/UART resources, taken by tiny servod.
+    # See https://issuetracker.google.com/196021317 for background.
+    tinys.pty._issue_cmd("reboot")
 
-  vers = do_updater_version(vidpid, iface, serialno)
-  if vers == 2:
-    flash(brdfile, serialno, binfile)
-  elif vers == 6:
-    flash2(vidpid, serialno, binfile)
-  else:
-    raise ServoUpdaterException("Can't detect updater version")
+    print("===== Finished =====")
 
-  select(vidpid, iface, serialno, "ro", debuglog=debuglog)
 
 if __name__ == "__main__":
-  main()
+    main()
diff --git a/extra/usb_updater/usb_updater2.c b/extra/usb_updater/usb_updater2.c
index 10bfeee7bb..b0b6538055 100644
--- a/extra/usb_updater/usb_updater2.c
+++ b/extra/usb_updater/usb_updater2.c
@@ -1,32 +1,32 @@
 /*
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <time.h>
+
 #include <asm/byteorder.h>
 #include <endian.h>
 #include <fcntl.h>
+#include <fmap.h>
 #include <getopt.h>
 #include <libusb.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
 #include <sys/stat.h>
 #include <sys/types.h>
-#include <time.h>
 #include <unistd.h>
 
-#include <fmap.h>
-
 #ifndef __packed
 #define __packed __attribute__((packed))
 #endif
 
 #include "compile_time_macros.h"
 #include "misc_util.h"
-#include "usb_descriptor.h"
 #include "update_fw.h"
+#include "usb_descriptor.h"
 #include "vb21_struct.h"
 
 #ifdef DEBUG
@@ -46,16 +46,16 @@
 #define PROTOCOL USB_PROTOCOL_GOOGLE_UPDATE
 
 enum exit_values {
-	noop = 0,	  /* All up to date, no update needed. */
-	all_updated = 1,  /* Update completed, reboot required. */
-	rw_updated  = 2,  /* RO was not updated, reboot required. */
-	update_error = 3  /* Something went wrong. */
+	noop = 0, /* All up to date, no update needed. */
+	all_updated = 1, /* Update completed, reboot required. */
+	rw_updated = 2, /* RO was not updated, reboot required. */
+	update_error = 3 /* Something went wrong. */
 };
 
 struct usb_endpoint {
 	struct libusb_device_handle *devh;
 	uint8_t ep_num;
-	int     chunk_len;
+	int chunk_len;
 };
 
 struct transfer_descriptor {
@@ -76,22 +76,22 @@ static char *progname;
 static char *short_opts = "bd:efg:hjlnp:rsS:tuw";
 static const struct option long_opts[] = {
 	/* name    hasarg *flag val */
-	{"binvers",	1,   NULL, 'b'},
-	{"device",	1,   NULL, 'd'},
-	{"entropy",	0,   NULL, 'e'},
-	{"fwver",	0,   NULL, 'f'},
-	{"tp_debug",	1,   NULL, 'g'},
-	{"help",	0,   NULL, 'h'},
-	{"jump_to_rw",	0,   NULL, 'j'},
-	{"follow_log",	0,   NULL, 'l'},
-	{"no_reset",	0,   NULL, 'n'},
-	{"tp_update",	1,   NULL, 'p'},
-	{"reboot",	0,   NULL, 'r'},
-	{"stay_in_ro",	0,   NULL, 's'},
-	{"serial",	1,   NULL, 'S'},
-	{"tp_info",	0,   NULL, 't'},
-	{"unlock_rollback",	0,   NULL, 'u'},
-	{"unlock_rw",	0,   NULL, 'w'},
+	{ "binvers", 1, NULL, 'b' },
+	{ "device", 1, NULL, 'd' },
+	{ "entropy", 0, NULL, 'e' },
+	{ "fwver", 0, NULL, 'f' },
+	{ "tp_debug", 1, NULL, 'g' },
+	{ "help", 0, NULL, 'h' },
+	{ "jump_to_rw", 0, NULL, 'j' },
+	{ "follow_log", 0, NULL, 'l' },
+	{ "no_reset", 0, NULL, 'n' },
+	{ "tp_update", 1, NULL, 'p' },
+	{ "reboot", 0, NULL, 'r' },
+	{ "stay_in_ro", 0, NULL, 's' },
+	{ "serial", 1, NULL, 'S' },
+	{ "tp_info", 0, NULL, 't' },
+	{ "unlock_rollback", 0, NULL, 'u' },
+	{ "unlock_rw", 0, NULL, 'w' },
 	{},
 };
 
@@ -113,7 +113,7 @@ static void usage(int errs)
 	       "Options:\n"
 	       "\n"
 	       "  -b,--binvers             Report versions of image's "
-				"RW and RO, do not update\n"
+	       "RW and RO, do not update\n"
 	       "  -d,--device  VID:PID     USB device (default %04x:%04x)\n"
 	       "  -e,--entropy             Add entropy to device secret\n"
 	       "  -f,--fwver               Report running firmware versions.\n"
@@ -128,7 +128,8 @@ static void usage(int errs)
 	       "  -t,--tp_info             Get touchpad information\n"
 	       "  -u,--unlock_rollback     Tell EC to unlock the rollback region\n"
 	       "  -w,--unlock_rw           Tell EC to unlock the RW region\n"
-	       "\n", progname, VID, PID);
+	       "\n",
+	       progname, VID, PID);
 
 	exit(errs ? update_error : noop);
 }
@@ -138,7 +139,7 @@ static void str2hex(const char *str, uint8_t *data, int *len)
 	int i;
 	int slen = strlen(str);
 
-	if (slen/2 > *len) {
+	if (slen / 2 > *len) {
 		fprintf(stderr, "Hex string too long.\n");
 		exit(update_error);
 	}
@@ -153,7 +154,7 @@ static void str2hex(const char *str, uint8_t *data, int *len)
 		char tmp[3];
 
 		tmp[0] = str[i];
-		tmp[1] = str[i+1];
+		tmp[1] = str[i + 1];
 		tmp[2] = 0;
 
 		data[*len] = strtol(tmp, &end, 16);
@@ -250,9 +251,9 @@ static uint8_t *get_file_or_die(const char *filename, size_t *len_ptr)
 	return data;
 }
 
-#define USB_ERROR(m, r) \
-	fprintf(stderr, "%s:%d, %s returned %d (%s)\n", __FILE__, __LINE__, \
-		m, r, libusb_strerror(r))
+#define USB_ERROR(m, r)                                                        \
+	fprintf(stderr, "%s:%d, %s returned %d (%s)\n", __FILE__, __LINE__, m, \
+		r, libusb_strerror(r))
 
 /*
  * Actual USB transfer function, the 'allow_less' flag indicates that the
@@ -261,17 +262,14 @@ static uint8_t *get_file_or_die(const char *filename, size_t *len_ptr)
  * bytes were received.
  */
 static void do_xfer(struct usb_endpoint *uep, void *outbuf, int outlen,
-		    void *inbuf, int inlen, int allow_less,
-		    size_t *rxed_count)
+		    void *inbuf, int inlen, int allow_less, size_t *rxed_count)
 {
-
 	int r, actual;
 
 	/* Send data out */
 	if (outbuf && outlen) {
 		actual = 0;
-		r = libusb_bulk_transfer(uep->devh, uep->ep_num,
-					 outbuf, outlen,
+		r = libusb_bulk_transfer(uep->devh, uep->ep_num, outbuf, outlen,
 					 &actual, 2000);
 		if (r < 0) {
 			USB_ERROR("libusb_bulk_transfer", r);
@@ -286,11 +284,9 @@ static void do_xfer(struct usb_endpoint *uep, void *outbuf, int outlen,
 
 	/* Read reply back */
 	if (inbuf && inlen) {
-
 		actual = 0;
-		r = libusb_bulk_transfer(uep->devh, uep->ep_num | 0x80,
-					 inbuf, inlen,
-					 &actual, 5000);
+		r = libusb_bulk_transfer(uep->devh, uep->ep_num | 0x80, inbuf,
+					 inlen, &actual, 5000);
 		if (r < 0) {
 			USB_ERROR("libusb_bulk_transfer", r);
 			exit(update_error);
@@ -307,8 +303,8 @@ static void do_xfer(struct usb_endpoint *uep, void *outbuf, int outlen,
 	}
 }
 
-static void xfer(struct usb_endpoint *uep, void *outbuf,
-		 size_t outlen, void *inbuf, size_t inlen, int allow_less)
+static void xfer(struct usb_endpoint *uep, void *outbuf, size_t outlen,
+		 void *inbuf, size_t inlen, int allow_less)
 {
 	do_xfer(uep, outbuf, outlen, inbuf, inlen, allow_less, NULL);
 }
@@ -321,8 +317,7 @@ static int find_endpoint(const struct libusb_interface_descriptor *iface,
 
 	if (iface->bInterfaceClass == 255 &&
 	    iface->bInterfaceSubClass == SUBCLASS &&
-	    iface->bInterfaceProtocol == PROTOCOL &&
-	    iface->bNumEndpoints) {
+	    iface->bInterfaceProtocol == PROTOCOL && iface->bNumEndpoints) {
 		ep = &iface->endpoint[0];
 		uep->ep_num = ep->bEndpointAddress & 0x7f;
 		uep->chunk_len = ep->wMaxPacketSize;
@@ -354,7 +349,7 @@ static int find_interface(struct usb_endpoint *uep)
 		for (j = 0; j < iface0->num_altsetting; j++) {
 			iface = &iface0->altsetting[j];
 			if (find_endpoint(iface, uep)) {
-				iface_num = i;
+				iface_num = iface->bInterfaceNumber;
 				goto out;
 			}
 		}
@@ -377,19 +372,19 @@ static int parse_vidpid(const char *input, uint16_t *vid_ptr, uint16_t *pid_ptr)
 		return 0;
 	*s++ = '\0';
 
-	*vid_ptr = (uint16_t) strtoul(copy, &e, 16);
+	*vid_ptr = (uint16_t)strtoull(copy, &e, 16);
 	if (!*optarg || (e && *e))
 		return 0;
 
-	*pid_ptr = (uint16_t) strtoul(s, &e, 16);
+	*pid_ptr = (uint16_t)strtoull(s, &e, 16);
 	if (!*optarg || (e && *e))
 		return 0;
 
 	return 1;
 }
 
-static libusb_device_handle *check_device(libusb_device *dev,
-	uint16_t vid, uint16_t pid, char *serialno)
+static libusb_device_handle *check_device(libusb_device *dev, uint16_t vid,
+					  uint16_t pid, char *serialno)
 {
 	struct libusb_device_descriptor desc;
 	libusb_device_handle *handle = NULL;
@@ -409,7 +404,9 @@ static libusb_device_handle *check_device(libusb_device *dev,
 
 	if (desc.iSerialNumber) {
 		ret = libusb_get_string_descriptor_ascii(handle,
-			desc.iSerialNumber, (unsigned char *)sn, sizeof(sn));
+							 desc.iSerialNumber,
+							 (unsigned char *)sn,
+							 sizeof(sn));
 		if (ret > 0)
 			snvalid = 1;
 	}
@@ -428,8 +425,8 @@ static libusb_device_handle *check_device(libusb_device *dev,
 	return NULL;
 }
 
-static void usb_findit(uint16_t vid, uint16_t pid,
-		char *serialno, struct usb_endpoint *uep)
+static void usb_findit(uint16_t vid, uint16_t pid, char *serialno,
+		       struct usb_endpoint *uep)
 {
 	int iface_num, r, i;
 	libusb_device **devs;
@@ -475,8 +472,8 @@ static void usb_findit(uint16_t vid, uint16_t pid,
 		shut_down(uep);
 	}
 
-	printf("found interface %d endpoint %d, chunk_len %d\n",
-	       iface_num, uep->ep_num, uep->chunk_len);
+	printf("found interface %d endpoint %d, chunk_len %d\n", iface_num,
+	       uep->ep_num, uep->chunk_len);
 
 	libusb_set_auto_detach_kernel_driver(uep->devh, 1);
 	r = libusb_claim_interface(uep->devh, iface_num);
@@ -504,16 +501,16 @@ static int transfer_block(struct usb_endpoint *uep,
 	for (transfer_size = 0; transfer_size < payload_size;) {
 		int chunk_size;
 
-		chunk_size = MIN(uep->chunk_len, payload_size - transfer_size);
+		chunk_size = MIN((size_t)uep->chunk_len,
+				 payload_size - transfer_size);
 		xfer(uep, transfer_data_ptr, chunk_size, NULL, 0, 0);
 		transfer_data_ptr += chunk_size;
 		transfer_size += chunk_size;
 	}
 
 	/* Now get the reply. */
-	r = libusb_bulk_transfer(uep->devh, uep->ep_num | 0x80,
-				 (void *) &reply, sizeof(reply),
-				 &actual, 5000);
+	r = libusb_bulk_transfer(uep->devh, uep->ep_num | 0x80, (void *)&reply,
+				 sizeof(reply), &actual, 5000);
 	if (r) {
 		if (r == -7) {
 			fprintf(stderr, "Timeout!\n");
@@ -541,10 +538,8 @@ static int transfer_block(struct usb_endpoint *uep,
  * data_len     - section size
  * smart_update - non-zero to enable the smart trailing of 0xff.
  */
-static void transfer_section(struct transfer_descriptor *td,
-			     uint8_t *data_ptr,
-			     uint32_t section_addr,
-			     size_t data_len,
+static void transfer_section(struct transfer_descriptor *td, uint8_t *data_ptr,
+			     uint32_t section_addr, size_t data_len,
 			     uint8_t smart_update)
 {
 	/*
@@ -571,17 +566,16 @@ static void transfer_section(struct transfer_descriptor *td,
 		struct update_frame_header ufh;
 
 		ufh.block_size = htobe32(payload_size +
-					sizeof(struct update_frame_header));
+					 sizeof(struct update_frame_header));
 		ufh.cmd.block_base = block_base;
 		ufh.cmd.block_digest = 0;
 		for (max_retries = 10; max_retries; max_retries--)
-			if (!transfer_block(&td->uep, &ufh,
-						data_ptr, payload_size))
+			if (!transfer_block(&td->uep, &ufh, data_ptr,
+					    payload_size))
 				break;
 
 		if (!max_retries) {
-			fprintf(stderr,
-				"Failed to transfer block, %zd to go\n",
+			fprintf(stderr, "Failed to transfer block, %zd to go\n",
 				data_len);
 			exit(update_error);
 		}
@@ -596,30 +590,27 @@ static void transfer_section(struct transfer_descriptor *td,
  * states.
  */
 enum upgrade_status {
-	not_needed = 0,  /* Version below or equal that on the target. */
-	not_possible,    /*
-			  * RO is newer, but can't be transferred due to
-			  * target RW shortcomings.
-			  */
-	needed            /*
-			   * This section needs to be transferred to the
-			   * target.
-			   */
+	not_needed = 0, /* Version below or equal that on the target. */
+	not_possible, /*
+		       * RO is newer, but can't be transferred due to
+		       * target RW shortcomings.
+		       */
+	needed /*
+		* This section needs to be transferred to the
+		* target.
+		*/
 };
 
 /* This array describes all sections of the new image. */
 static struct {
 	const char *name;
-	uint32_t    offset;
-	uint32_t    size;
-	enum upgrade_status  ustatus;
+	uint32_t offset;
+	uint32_t size;
+	enum upgrade_status ustatus;
 	char version[32];
 	int32_t rollback;
 	uint32_t key_version;
-} sections[] = {
-	{"RO"},
-	{"RW"}
-};
+} sections[] = { { "RO" }, { "RW" } };
 
 static const struct fmap_area *fmap_find_area_or_die(const struct fmap *fmap,
 						     const char *name)
@@ -650,7 +641,7 @@ static void fetch_header_versions(const uint8_t *image, size_t len)
 		fprintf(stderr, "Cannot find FMAP in image\n");
 		exit(update_error);
 	}
-	fmap = (const struct fmap *)(image+offset);
+	fmap = (const struct fmap *)(image + offset);
 
 	/* FIXME: validate fmap struct more than this? */
 	if (fmap->size != len) {
@@ -693,15 +684,15 @@ static void fetch_header_versions(const uint8_t *image, size_t len)
 			fprintf(stderr, "Invalid fwid size\n");
 			exit(update_error);
 		}
-		memcpy(sections[i].version, image+fmaparea->offset,
-			fmaparea->size);
+		memcpy(sections[i].version, image + fmaparea->offset,
+		       fmaparea->size);
 
 		sections[i].rollback = -1;
 		if (fmap_rollback_name) {
 			fmaparea = fmap_find_area(fmap, fmap_rollback_name);
 			if (fmaparea)
 				memcpy(&sections[i].rollback,
-				       image+fmaparea->offset,
+				       image + fmaparea->offset,
 				       sizeof(sections[i].rollback));
 		}
 
@@ -710,7 +701,8 @@ static void fetch_header_versions(const uint8_t *image, size_t len)
 			fmaparea = fmap_find_area(fmap, fmap_key_name);
 			if (fmaparea) {
 				const struct vb21_packed_key *key =
-					(const void *)(image+fmaparea->offset);
+					(const void *)(image +
+						       fmaparea->offset);
 				sections[i].key_version = key->key_version;
 			}
 		}
@@ -723,9 +715,9 @@ static int show_headers_versions(const void *image)
 
 	for (i = 0; i < ARRAY_SIZE(sections); i++) {
 		printf("%s off=%08x/%08x v=%.32s rb=%d kv=%d\n",
-			sections[i].name, sections[i].offset, sections[i].size,
-			sections[i].version, sections[i].rollback,
-			sections[i].key_version);
+		       sections[i].name, sections[i].offset, sections[i].size,
+		       sections[i].version, sections[i].rollback,
+		       sections[i].key_version);
 	}
 	return 0;
 }
@@ -772,17 +764,16 @@ static void setup_connection(struct transfer_descriptor *td)
 	int actual = 0;
 
 	/* Flush all data from endpoint to recover in case of error. */
-	while (!libusb_bulk_transfer(td->uep.devh,
-					td->uep.ep_num | 0x80,
-					(void *)&inbuf, td->uep.chunk_len,
-					&actual, 10)) {
+	while (!libusb_bulk_transfer(td->uep.devh, td->uep.ep_num | 0x80,
+				     (void *)&inbuf, td->uep.chunk_len, &actual,
+				     10)) {
 		printf("flush\n");
 	}
 
 	memset(&ufh, 0, sizeof(ufh));
 	ufh.block_size = htobe32(sizeof(ufh));
-	do_xfer(&td->uep, &ufh, sizeof(ufh), &start_resp,
-		sizeof(start_resp), 1, &rxed_size);
+	do_xfer(&td->uep, &ufh, sizeof(ufh), &start_resp, sizeof(start_resp), 1,
+		&rxed_size);
 
 	/* We got something. Check for errors in response */
 	if (rxed_size < 8) {
@@ -803,10 +794,9 @@ static void setup_connection(struct transfer_descriptor *td)
 	header_type = be16toh(start_resp.rpdu.header_type);
 
 	printf("target running protocol version %d (type %d)\n",
-		protocol_version, header_type);
+	       protocol_version, header_type);
 	if (header_type != UPDATE_HEADER_TYPE_COMMON) {
-		fprintf(stderr, "Unsupported header type %d\n",
-			header_type);
+		fprintf(stderr, "Unsupported header type %d\n", header_type);
 		exit(update_error);
 	}
 
@@ -820,7 +810,7 @@ static void setup_connection(struct transfer_descriptor *td)
 
 	td->offset = be32toh(start_resp.rpdu.common.offset);
 	memcpy(targ.common.version, start_resp.rpdu.common.version,
-		sizeof(start_resp.rpdu.common.version));
+	       sizeof(start_resp.rpdu.common.version));
 	targ.common.maximum_pdu_size =
 		be32toh(start_resp.rpdu.common.maximum_pdu_size);
 	targ.common.flash_protection =
@@ -845,21 +835,20 @@ static void setup_connection(struct transfer_descriptor *td)
  * if it is - of what maximum size.
  */
 static int ext_cmd_over_usb(struct usb_endpoint *uep, uint16_t subcommand,
-			    void *cmd_body, size_t body_size,
-			    void *resp, size_t *resp_size,
-			    int allow_less)
+			    void *cmd_body, size_t body_size, void *resp,
+			    size_t *resp_size, int allow_less)
 {
 	struct update_frame_header *ufh;
 	uint16_t *frame_ptr;
 	size_t usb_msg_size;
 
-	usb_msg_size = sizeof(struct update_frame_header) +
-		sizeof(subcommand) + body_size;
+	usb_msg_size = sizeof(struct update_frame_header) + sizeof(subcommand) +
+		       body_size;
 
 	ufh = malloc(usb_msg_size);
 	if (!ufh) {
-		printf("%s: failed to allocate %zd bytes\n",
-		       __func__, usb_msg_size);
+		printf("%s: failed to allocate %zd bytes\n", __func__,
+		       usb_msg_size);
 		return -1;
 	}
 
@@ -895,30 +884,28 @@ static void send_done(struct usb_endpoint *uep)
 }
 
 static void send_subcommand(struct transfer_descriptor *td, uint16_t subcommand,
-			    void *cmd_body, size_t body_size,
-			    uint8_t *response, size_t response_size)
+			    void *cmd_body, size_t body_size, uint8_t *response,
+			    size_t response_size)
 {
 	send_done(&td->uep);
 
-	ext_cmd_over_usb(&td->uep, subcommand,
-			cmd_body, body_size,
-			response, &response_size, 0);
+	ext_cmd_over_usb(&td->uep, subcommand, cmd_body, body_size, response,
+			 &response_size, 0);
 	printf("sent command %x, resp %x\n", subcommand, response[0]);
 }
 
 /* Returns number of successfully transmitted image sections. */
-static int transfer_image(struct transfer_descriptor *td,
-			       uint8_t *data, size_t data_len)
+static int transfer_image(struct transfer_descriptor *td, uint8_t *data,
+			  size_t data_len)
 {
 	size_t i;
 	int num_txed_sections = 0;
 
 	for (i = 0; i < ARRAY_SIZE(sections); i++)
 		if (sections[i].ustatus == needed) {
-			transfer_section(td,
-					 data + sections[i].offset,
-					 sections[i].offset,
-					 sections[i].size, 1);
+			transfer_section(td, data + sections[i].offset,
+					 sections[i].offset, sections[i].size,
+					 1);
 			num_txed_sections++;
 		}
 
@@ -968,9 +955,8 @@ static void generate_reset_request(struct transfer_descriptor *td)
 	command_body_size = 0;
 	response_size = 1;
 	subcommand = UPDATE_EXTRA_CMD_IMMEDIATE_RESET;
-	ext_cmd_over_usb(&td->uep, subcommand,
-			command_body, command_body_size,
-			&response, &response_size, 0);
+	ext_cmd_over_usb(&td->uep, subcommand, command_body, command_body_size,
+			 &response, &response_size, 0);
 
 	printf("reboot not triggered\n");
 }
@@ -987,7 +973,7 @@ static void get_random(uint8_t *data, int len)
 	}
 
 	while (i < len) {
-		int ret = fread(data+i, len-i, 1, fp);
+		int ret = fread(data + i, len - i, 1, fp);
 
 		if (ret < 0) {
 			perror("fread");
@@ -1005,7 +991,8 @@ static void read_console(struct transfer_descriptor *td)
 	uint8_t payload[] = { 0x1 };
 	uint8_t response[64];
 	size_t response_size = 64;
-	struct timespec sleep_duration = {  /* 100 ms */
+	struct timespec sleep_duration = {
+		/* 100 ms */
 		.tv_sec = 0,
 		.tv_nsec = 100l * 1000l * 1000l,
 	};
@@ -1015,17 +1002,15 @@ static void read_console(struct transfer_descriptor *td)
 	printf("\n");
 	while (1) {
 		response_size = 1;
-		ext_cmd_over_usb(&td->uep,
-				 UPDATE_EXTRA_CMD_CONSOLE_READ_INIT,
-				 NULL, 0,
-				 response, &response_size, 0);
+		ext_cmd_over_usb(&td->uep, UPDATE_EXTRA_CMD_CONSOLE_READ_INIT,
+				 NULL, 0, response, &response_size, 0);
 
 		while (1) {
 			response_size = 64;
 			ext_cmd_over_usb(&td->uep,
 					 UPDATE_EXTRA_CMD_CONSOLE_READ_NEXT,
-					 payload, sizeof(payload),
-					 response, &response_size, 1);
+					 payload, sizeof(payload), response,
+					 &response_size, 1);
 			if (response[0] == 0)
 				break;
 			/* make sure it's null-terminated. */
@@ -1067,7 +1052,7 @@ int main(int argc, char *argv[])
 	memset(&td, 0, sizeof(td));
 
 	errorcnt = 0;
-	opterr = 0;				/* quiet, you */
+	opterr = 0; /* quiet, you */
 	while ((i = getopt_long(argc, argv, short_opts, long_opts, 0)) != -1) {
 		switch (i) {
 		case 'b':
@@ -1091,8 +1076,8 @@ int main(int argc, char *argv[])
 			extra_command = UPDATE_EXTRA_CMD_TOUCHPAD_DEBUG;
 			/* Maximum length. */
 			extra_command_data_len = 50;
-			str2hex(optarg,
-				extra_command_data, &extra_command_data_len);
+			str2hex(optarg, extra_command_data,
+				&extra_command_data_len);
 			hexdump(extra_command_data, extra_command_data_len);
 			extra_command_answer_len = 64;
 			break;
@@ -1112,8 +1097,8 @@ int main(int argc, char *argv[])
 			touchpad_update = 1;
 
 			data = get_file_or_die(optarg, &data_len);
-			printf("read %zd(%#zx) bytes from %s\n",
-				data_len, data_len, argv[optind]);
+			printf("read %zd(%#zx) bytes from %s\n", data_len,
+			       data_len, argv[optind - 1]);
 
 			break;
 		case 'r':
@@ -1127,8 +1112,7 @@ int main(int argc, char *argv[])
 			break;
 		case 't':
 			extra_command = UPDATE_EXTRA_CMD_TOUCHPAD_INFO;
-			extra_command_answer_len =
-				sizeof(struct touchpad_info);
+			extra_command_answer_len = sizeof(struct touchpad_info);
 			break;
 		case 'u':
 			extra_command = UPDATE_EXTRA_CMD_UNLOCK_ROLLBACK;
@@ -1136,7 +1120,7 @@ int main(int argc, char *argv[])
 		case 'w':
 			extra_command = UPDATE_EXTRA_CMD_UNLOCK_RW;
 			break;
-		case 0:				/* auto-handled option */
+		case 0: /* auto-handled option */
 			break;
 		case '?':
 			if (optopt)
@@ -1167,8 +1151,8 @@ int main(int argc, char *argv[])
 		}
 
 		data = get_file_or_die(argv[optind], &data_len);
-		printf("read %zd(%#zx) bytes from %s\n",
-		       data_len, data_len, argv[optind]);
+		printf("read %zd(%#zx) bytes from %s\n", data_len, data_len,
+		       argv[optind]);
 
 		fetch_header_versions(data, data_len);
 
@@ -1190,16 +1174,13 @@ int main(int argc, char *argv[])
 
 	if (data) {
 		if (touchpad_update) {
-			transfer_section(&td,
-					data,
-					0x80000000,
-					data_len, 0);
+			transfer_section(&td, data, 0x80000000, data_len, 0);
 			free(data);
 
 			send_done(&td.uep);
 		} else {
-			transferred_sections = transfer_image(&td,
-							data, data_len);
+			transferred_sections =
+				transfer_image(&td, data, data_len);
 			free(data);
 
 			if (transferred_sections && !no_reset_request)
@@ -1208,16 +1189,16 @@ int main(int argc, char *argv[])
 	} else if (extra_command == UPDATE_EXTRA_CMD_CONSOLE_READ_INIT) {
 		read_console(&td);
 	} else if (extra_command > -1) {
-		send_subcommand(&td, extra_command,
-				extra_command_data, extra_command_data_len,
-				extra_command_answer, extra_command_answer_len);
+		send_subcommand(&td, extra_command, extra_command_data,
+				extra_command_data_len, extra_command_answer,
+				extra_command_answer_len);
 
 		switch (extra_command) {
 		case UPDATE_EXTRA_CMD_TOUCHPAD_INFO:
 			dump_touchpad_info(extra_command_answer,
 					   extra_command_answer_len);
 			break;
-		case  UPDATE_EXTRA_CMD_TOUCHPAD_DEBUG:
+		case UPDATE_EXTRA_CMD_TOUCHPAD_DEBUG:
 			hexdump(extra_command_answer, extra_command_answer_len);
 			break;
 		}
diff --git a/firmware_builder.py b/firmware_builder.py
index a55eba6c9a..895873289d 100755
--- a/firmware_builder.py
+++ b/firmware_builder.py
@@ -1,83 +1,431 @@
-#!/usr/bin/env python3
+#!/usr/bin/env -S python3 -u
 # -*- coding: utf-8 -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
-"""Build and test all of the EC boards.
 
-This is the entry point for the custom firmware builder workflow recipe.
+"""Build, bundle, or test all of the EC boards.
+
+This is the entry point for the custom firmware builder workflow recipe.  It
+gets invoked by chromite/api/controller/firmware.py.
 """
 
 import argparse
 import multiprocessing
 import os
+import pathlib
+import shutil
 import subprocess
 import sys
 
+# pylint: disable=import-error
 from google.protobuf import json_format
 
-from chromite.api.gen.chromite.api import firmware_pb2
+from chromite.api.gen_sdk.chromite.api import firmware_pb2
+
+
+DEFAULT_BUNDLE_DIRECTORY = "/tmp/artifact_bundles"
+DEFAULT_BUNDLE_METADATA_FILE = "/tmp/artifact_bundle_metadata"
+
+# The the list of boards whose on-device unit tests we will verify compilation.
+# TODO(b/172501728) On-device unit tests should build for all boards, but
+# they've bit rotted, so we only build the ones that compile.
+BOARDS_UNIT_TEST = [
+    "bloonchipper",
+    "dartmonkey",
+]
+
+# Interesting regions to show in gerrit
+BINARY_SIZE_REGIONS = ["RW_FLASH", "RW_IRAM"]
+
+# The most recently edited boards that should show binary size changes in
+# gerrit
+BINARY_SIZE_BOARDS = [
+    "dibbi",
+    "gaelin",
+    "gladios",
+    "lisbon",
+    "marasov",
+    "moli",
+    "prism",
+    "shotzo",
+    "taranza",
+]
+
 
 def build(opts):
-    """Builds all EC firmware targets"""
-    # TODO(b/169178847): Add appropriate metric information
-    metrics = firmware_pb2.FwBuildMetricList()
-    with open(opts.metrics, 'w') as f:
-        f.write(json_format.MessageToJson(metrics))
-    return subprocess.run(['make', 'buildall_only', '-j{}'.format(opts.cpus)],
-                          cwd=os.path.dirname(__file__)).returncode
+    """Builds all EC firmware targets
+
+    Note that when we are building unit tests for code coverage, we don't
+    need this step. It builds EC **firmware** targets, but unit tests with
+    code coverage are all host-based. So if the --code-coverage flag is set,
+    we don't need to build the firmware targets and we can return without
+    doing anything but creating the metrics file and giving an informational
+    message.
+    """
+    metric_list = firmware_pb2.FwBuildMetricList()
+    ec_dir = pathlib.Path(__file__).parent
+
+    # Run formatting checks on all python files.
+    cmd = ["black", "--check", "."]
+    print(f"# Running {' '.join(cmd)}.")
+    subprocess.run(cmd, cwd=os.path.dirname(__file__), check=True)
+    chromite_dir = ec_dir.resolve().parent.parent.parent / "chromite"
+    cmd = [
+        "isort",
+        f"--settings-file={chromite_dir / '.isort.cfg'}",
+        "--check",
+        "--gitignore",
+        "--dont-follow-links",
+        ".",
+    ]
+    print(f"# Running {' '.join(cmd)}.")
+    subprocess.run(
+        cmd,
+        cwd=os.path.dirname(__file__),
+        check=True,
+    )
+
+    if opts.code_coverage:
+        print(
+            "When --code-coverage is selected, 'build' is a no-op. "
+            "Run 'test' with --code-coverage instead."
+        )
+        with open(opts.metrics, "w", encoding="utf-8") as file:
+            file.write(json_format.MessageToJson(metric_list))
+        return
+
+    subprocess.run([ec_dir / "util" / "check_clang_format.py"], check=True)
+
+    cmd = ["make", "clobber"]
+    print(f"# Running {' '.join(cmd)}.")
+    subprocess.run(cmd, cwd=os.path.dirname(__file__), check=True)
+
+    cmd = ["make", "buildall_only", f"-j{opts.cpus}"]
+    print(f"# Running {' '.join(cmd)}.")
+    subprocess.run(cmd, cwd=os.path.dirname(__file__), check=True)
+
+    # extra/rma_reset is used in chromeos-base/ec-utils-test
+    cmd = ["make", "-C", "extra/rma_reset", "clean"]
+    print(f"# Running {' '.join(cmd)}.")
+    subprocess.run(cmd, cwd=os.path.dirname(__file__), check=True)
+
+    cmd = ["make", "-C", "extra/rma_reset", f"-j{opts.cpus}"]
+    print(f"# Running {' '.join(cmd)}.")
+    subprocess.run(cmd, cwd=os.path.dirname(__file__), check=True)
+
+    # extra/usb_updater is used in chromeos-base/ec-devutils
+    cmd = ["make", "-C", "extra/usb_updater", "clean"]
+    print(f"# Running {' '.join(cmd)}.")
+    subprocess.run(cmd, cwd=os.path.dirname(__file__), check=True)
+
+    cmd = ["make", "-C", "extra/usb_updater", "usb_updater2", f"-j{opts.cpus}"]
+    print(f"# Running {' '.join(cmd)}.")
+    subprocess.run(cmd, cwd=os.path.dirname(__file__), check=True)
+
+    cmd = ["make", "print-all-baseboards", f"-j{opts.cpus}"]
+    print(f"# Running {' '.join(cmd)}.")
+    baseboards = {}
+    for line in subprocess.run(
+        cmd,
+        cwd=os.path.dirname(__file__),
+        check=True,
+        universal_newlines=True,
+        stdout=subprocess.PIPE,
+    ).stdout.splitlines():
+        parts = line.split("=")
+        if len(parts) > 1:
+            baseboards[parts[0]] = parts[1]
+
+    ec_dir = os.path.dirname(__file__)
+    build_dir = os.path.join(ec_dir, "build")
+    for build_target in sorted(os.listdir(build_dir)):
+        metric = metric_list.value.add()
+        metric.target_name = build_target
+        metric.platform_name = build_target
+        if build_target in baseboards and baseboards[build_target]:
+            metric.platform_name = baseboards[build_target]
+
+        for variant in ["RO", "RW"]:
+            memsize_file = (
+                pathlib.Path(build_dir)
+                / build_target
+                / variant
+                / f"ec.{variant}.elf.memsize.txt"
+            )
+            if memsize_file.exists():
+                parse_memsize(
+                    memsize_file,
+                    metric,
+                    variant,
+                    build_target in BINARY_SIZE_BOARDS,
+                )
+    with open(opts.metrics, "w", encoding="utf-8") as file:
+        file.write(json_format.MessageToJson(metric_list))
+
+    # Ensure that there are no regressions for boards that build successfully
+    # with clang: b/172020503.
+    cmd = ["./util/build_with_clang.py"]
+    print(f'# Running {" ".join(cmd)}.')
+    subprocess.run(cmd, cwd=os.path.dirname(__file__), check=True)
+
+
+UNITS = {
+    "B": 1,
+    "KB": 1024,
+    "MB": 1024 * 1024,
+    "GB": 1024 * 1024 * 1024,
+}
+
+
+def parse_memsize(filename, metric, variant, track_on_gerrit):
+    """Parse the output of the build to extract the image size."""
+    with open(filename, "r", encoding="utf-8") as infile:
+        # Skip header line
+        infile.readline()
+        for line in infile.readlines():
+            parts = line.split()
+            fw_section = metric.fw_section.add()
+            fw_section.region = variant + "_" + parts[0][:-1]
+            fw_section.used = int(parts[1]) * UNITS[parts[2]]
+            fw_section.total = int(parts[3]) * UNITS[parts[4]]
+            if track_on_gerrit and fw_section.region in BINARY_SIZE_REGIONS:
+                fw_section.track_on_gerrit = True
+            else:
+                fw_section.track_on_gerrit = False
+
+
+def bundle(opts):
+    """Bundle the artifacts."""
+    if opts.code_coverage:
+        bundle_coverage(opts)
+    else:
+        bundle_firmware(opts)
+
+
+def get_bundle_dir(opts):
+    """Get the directory for the bundle from opts or use the default.
+
+    Also create the directory if it doesn't exist.
+    """
+    if opts.output_dir:
+        bundle_dir = opts.output_dir
+    else:
+        bundle_dir = DEFAULT_BUNDLE_DIRECTORY
+    if not os.path.isdir(bundle_dir):
+        os.mkdir(bundle_dir)
+    return bundle_dir
+
+
+def write_metadata(opts, info):
+    """Write the metadata about the bundle."""
+    bundle_metadata_file = (
+        opts.metadata if opts.metadata else DEFAULT_BUNDLE_METADATA_FILE
+    )
+    with open(bundle_metadata_file, "w", encoding="utf-8") as file:
+        file.write(json_format.MessageToJson(info))
+
+
+def bundle_coverage(opts):
+    """Bundles the artifacts from code coverage into its own tarball."""
+    info = firmware_pb2.FirmwareArtifactInfo()
+    info.bcs_version_info.version_string = opts.bcs_version
+    bundle_dir = get_bundle_dir(opts)
+    ec_dir = os.path.dirname(__file__)
+    tarball_name = "coverage.tbz2"
+    tarball_path = os.path.join(bundle_dir, tarball_name)
+    cmd = ["tar", "cvfj", tarball_path, "lcov.info"]
+    subprocess.run(cmd, cwd=os.path.join(ec_dir, "build/coverage"), check=True)
+    meta = info.objects.add()
+    meta.file_name = tarball_name
+    meta.lcov_info.type = (
+        firmware_pb2.FirmwareArtifactInfo.LcovTarballInfo.LcovType.LCOV
+    )
+
+    write_metadata(opts, info)
+
+
+def bundle_firmware(opts):
+    """Bundles the artifacts from each target into its own tarball."""
+    info = firmware_pb2.FirmwareArtifactInfo()
+    info.bcs_version_info.version_string = opts.bcs_version
+    bundle_dir = get_bundle_dir(opts)
+    ec_dir = os.path.dirname(__file__)
+    for build_target in sorted(os.listdir(os.path.join(ec_dir, "build"))):
+        if build_target in ["host"]:
+            continue
+        tarball_name = "".join([build_target, ".firmware.tbz2"])
+        tarball_path = os.path.join(bundle_dir, tarball_name)
+        cmd = [
+            "tar",
+            "cvfj",
+            tarball_path,
+            "--exclude=*.d",
+            "--exclude=*.o",
+            ".",
+        ]
+        subprocess.run(
+            cmd,
+            cwd=os.path.join(ec_dir, "build", build_target),
+            check=True,
+        )
+        meta = info.objects.add()
+        meta.file_name = tarball_name
+        meta.tarball_info.type = (
+            firmware_pb2.FirmwareArtifactInfo.TarballInfo.FirmwareType.EC
+        )
+        # TODO(kmshelton): Populate the rest of metadata contents as it gets
+        # defined in infra/proto/src/chromite/api/firmware.proto.
+
+    write_metadata(opts, info)
 
 
 def test(opts):
     """Runs all of the unit tests for EC firmware"""
     # TODO(b/169178847): Add appropriate metric information
     metrics = firmware_pb2.FwTestMetricList()
-    with open(opts.metrics, 'w') as f:
-        f.write(json_format.MessageToJson(metrics))
-    return subprocess.run(['make', 'runtests', '-j{}'.format(opts.cpus)],
-                          cwd=os.path.dirname(__file__)).returncode
+    with open(opts.metrics, "w", encoding="utf-8") as file:
+        file.write(json_format.MessageToJson(metrics))
+
+    # Run python unit tests.
+    subprocess.run(
+        ["util/ec3po/run_tests.sh"], cwd=os.path.dirname(__file__), check=True
+    )
+    subprocess.run(
+        ["extra/stack_analyzer/run_tests.sh"],
+        cwd=os.path.dirname(__file__),
+        check=True,
+    )
+    subprocess.run(
+        ["util/run_tests.sh"], cwd=os.path.dirname(__file__), check=True
+    )
+
+    # If building for code coverage, build the 'coverage' target, which
+    # builds the posix-based unit tests for code coverage and assembles
+    # the LCOV information.
+    #
+    # Otherwise, build the 'runtests' target, which verifies all
+    # posix-based unit tests build and pass.
+    target = "coverage" if opts.code_coverage else "runtests"
+    cmd = ["make", target, f"-j{opts.cpus}"]
+    print(f"# Running {' '.join(cmd)}.")
+    subprocess.run(cmd, cwd=os.path.dirname(__file__), check=True)
+
+    if not opts.code_coverage:
+        # Verify compilation of the on-device unit test binaries.
+        # TODO(b/172501728) These should build  for all boards, but they've bit
+        # rotted, so we only build the ones that compile.
+        cmd = ["make", f"-j{opts.cpus}"]
+        cmd.extend(["tests-" + b for b in BOARDS_UNIT_TEST])
+        print(f"# Running {' '.join(cmd)}.")
+        subprocess.run(cmd, cwd=os.path.dirname(__file__), check=True)
+
+        # Verify the tests pass with ASan also
+        ec_dir = os.path.dirname(__file__)
+        build_dir = os.path.join(ec_dir, "build")
+        host_dir = os.path.join(build_dir, "host")
+        print(f"# Deleting {host_dir}")
+        shutil.rmtree(host_dir)
+
+        cmd = ["make", "TEST_ASAN=y", target, f"-j{opts.cpus}"]
+        print(f"# Running {' '.join(cmd)}.")
+        subprocess.run(cmd, cwd=os.path.dirname(__file__), check=True)
+
+        # Use the x86_64-cros-linux-gnu- compiler also
+        cmd = [
+            "make",
+            "clean",
+            "HOST_CROSS_COMPILE=x86_64-cros-linux-gnu-",
+            "TEST_ASAN=y",
+            target,
+            f"-j{opts.cpus}",
+        ]
+        print(f"# Running {' '.join(cmd)}.")
+        subprocess.run(cmd, cwd=os.path.dirname(__file__), check=True)
 
 
 def main(args):
-    """Builds and tests all of the EC targets and reports build metrics"""
+    """Builds, bundles, or tests all of the EC targets.
+
+    Additionally, the tool reports build metrics.
+    """
     opts = parse_args(args)
 
-    if not hasattr(opts, 'func'):
+    if not hasattr(opts, "func"):
         print("Must select a valid sub command!")
         return -1
 
     # Run selected sub command function
-    return opts.func(opts)
+    try:
+        opts.func(opts)
+    except subprocess.CalledProcessError:
+        return 1
+    else:
+        return 0
 
 
 def parse_args(args):
+    """Parse all command line args and return opts dict."""
     parser = argparse.ArgumentParser(description=__doc__)
 
     parser.add_argument(
-        '--cpus',
+        "--cpus",
         default=multiprocessing.cpu_count(),
-        help='The number of cores to use.',
+        help="The number of cores to use.",
     )
 
     parser.add_argument(
-        '--metrics',
-        dest='metrics',
+        "--metrics",
+        dest="metrics",
         required=True,
-        help='File to write the json-encoded MetricsList proto message.',
+        help="File to write the json-encoded MetricsList proto message.",
+    )
+
+    parser.add_argument(
+        "--metadata",
+        required=False,
+        help="Full pathname for the file in which to write build artifact metadata.",
+    )
+
+    parser.add_argument(
+        "--output-dir",
+        required=False,
+        help="Full pathanme for the directory in which to bundle build artifacts.",
+    )
+
+    parser.add_argument(
+        "--code-coverage",
+        required=False,
+        action="store_true",
+        help="Build host-based unit tests for code coverage.",
+    )
+
+    parser.add_argument(
+        "--bcs-version",
+        dest="bcs_version",
+        default="",
+        required=False,
+        # TODO(b/180008931): make this required=True.
+        help="BCS version to include in metadata.",
     )
 
     # Would make this required=True, but not available until 3.7
     sub_cmds = parser.add_subparsers()
 
-    build_cmd = sub_cmds.add_parser('build',
-                                    help='Builds all firmware targets')
+    build_cmd = sub_cmds.add_parser("build", help="Builds all firmware targets")
     build_cmd.set_defaults(func=build)
 
-    test_cmd = sub_cmds.add_parser('test', help='Runs all firmware unit tests')
+    build_cmd = sub_cmds.add_parser(
+        "bundle",
+        help="Creates a tarball containing build artifacts from all firmware targets",
+    )
+    build_cmd.set_defaults(func=bundle)
+
+    test_cmd = sub_cmds.add_parser("test", help="Runs all firmware unit tests")
     test_cmd.set_defaults(func=test)
 
     return parser.parse_args(args)
 
 
-if __name__ == '__main__':
+if __name__ == "__main__":
     sys.exit(main(sys.argv[1:]))
diff --git a/fuzz/build.mk b/fuzz/build.mk
index 44ddb56974..bc79df71e6 100644
--- a/fuzz/build.mk
+++ b/fuzz/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -10,7 +10,7 @@ fuzz-test-list-host =
 # Fuzzers should only be built for architectures that support sanitizers.
 ifeq ($(ARCH),amd64)
 fuzz-test-list-host += host_command_fuzz usb_pd_fuzz usb_tcpm_v2_rev20_fuzz \
-	usb_tcpm_v2_rev30_fuzz
+	usb_tcpm_v2_rev30_fuzz pchg_fuzz
 endif
 
 # For fuzzing targets libec.a is built from the ro objects and hides functions
@@ -31,3 +31,4 @@ usb_tcpm_v2_rev30_fuzz-y = usb_pd_fuzz.o usb_tcpm_v2_rev30_fuzz.o \
 	../test/fake_battery.o
 usb_tcpm_v2_rev20_fuzz-y = usb_pd_fuzz.o usb_tcpm_v2_rev20_fuzz.o \
 	../test/fake_battery.o
+pchg_fuzz-y = pchg_fuzz.o
diff --git a/fuzz/fuzz_config.h b/fuzz/fuzz_config.h
index 88664c8fb6..e7b539b864 100644
--- a/fuzz/fuzz_config.h
+++ b/fuzz/fuzz_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,8 +25,7 @@
 #endif /* ! FUZZ_HOSTCMD_VERBOSE */
 
 /* The following are for fpsensor host commands. */
-#define CONFIG_AES
-#define CONFIG_AES_GCM
+#define CONFIG_BORINGSSL_CRYPTO
 #define CONFIG_ROLLBACK_SECRET_SIZE 32
 #define CONFIG_SHA256
 
@@ -54,12 +53,15 @@
 #define CONFIG_USB_PD_DECODE_SOP
 #define CONFIG_USB_DRP_ACC_TRYSRC
 #define CONFIG_USB_PD_ALT_MODE_DFP
+#define CONFIG_USB_PD_DP_MODE
+#define CONFIG_USB_PD_DISCOVERY
 #define CONFIG_USBC_SS_MUX
 #define CONFIG_USBC_VCONN
 #define CONFIG_USBC_VCONN_SWAP
-#define PD_VCONN_SWAP_DELAY 5000
+#define CONFIG_USBC_VCONN_SWAP_DELAY_US 5000
 #define CONFIG_SHA256
 #define CONFIG_SW_CRC
+#define CONFIG_USB_PD_3A_PORTS 0 /* Host does not define a 3.0 A PDO */
 #endif /* TEST_USB_TCPM_V2_REV30_FUZZ */
 
 #ifdef TEST_USB_TCPM_V2_REV20_FUZZ
@@ -74,13 +76,28 @@
 #define CONFIG_USB_PD_DECODE_SOP
 #define CONFIG_USB_DRP_ACC_TRYSRC
 #define CONFIG_USB_PD_ALT_MODE_DFP
+#define CONFIG_USB_PD_DP_MODE
+#define CONFIG_USB_PD_DISCOVERY
 #define CONFIG_USBC_SS_MUX
 #define CONFIG_USBC_VCONN
 #define CONFIG_USBC_VCONN_SWAP
-#define PD_VCONN_SWAP_DELAY 5000
+#define CONFIG_USBC_VCONN_SWAP_DELAY_US 5000
 #define CONFIG_SHA256
 #define CONFIG_SW_CRC
+#define CONFIG_USB_PD_3A_PORTS 0 /* Host does not define a 3.0 A PDO */
 #endif /* TEST_USB_TCPM_V2_REV20_FUZZ */
 
-#endif  /* TEST_FUZZ */
-#endif  /* __FUZZ_FUZZ_CONFIG_H */
+#ifdef TEST_PCHG_FUZZ
+#define CONFIG_CTN730
+#define CONFIG_DEVICE_EVENT
+#define CONFIG_MKBP_EVENT
+#define CONFIG_MKBP_USE_GPIO
+#define CONFIG_PERIPHERAL_CHARGER
+#define I2C_PORT_WLC 0
+#define GPIO_WLC_IRQ_CONN 1
+#define GPIO_WLC_NRST_CONN 2
+#define GPIO_PCHG_P0 GPIO_WLC_IRQ_CONN
+#endif /* TEST_PCHG_FUZZ */
+
+#endif /* TEST_FUZZ */
+#endif /* __FUZZ_FUZZ_CONFIG_H */
diff --git a/fuzz/host_command_fuzz.c b/fuzz/host_command_fuzz.c
index c4f49c9525..2875c687dd 100644
--- a/fuzz/host_command_fuzz.c
+++ b/fuzz/host_command_fuzz.c
@@ -1,22 +1,24 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Fuzz host command.
  */
 
-#include <pthread.h>
-#include <sys/time.h>
-
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
 #include "host_command.h"
 #include "host_test.h"
+#include "printf.h"
 #include "task.h"
 #include "test_util.h"
 #include "timer.h"
 #include "util.h"
 
+#include <pthread.h>
+#include <sys/time.h>
+
 /* Only test requests with valid size and checksum (makes fuzzing faster) */
 #define VALID_REQUEST_ONLY
 
@@ -34,7 +36,7 @@ static struct ec_host_request *req = (struct ec_host_request *)req_buf;
 
 static void hostcmd_respond(struct host_packet *pkt)
 {
-	task_set_event(TASK_ID_TEST_RUNNER, TASK_EVENT_HOSTCMD_DONE, 0);
+	task_set_event(TASK_ID_TEST_RUNNER, TASK_EVENT_HOSTCMD_DONE);
 }
 
 static char calculate_checksum(const char *buf, int size)
@@ -56,6 +58,9 @@ struct chunk {
 static int hostcmd_fill(const uint8_t *data, size_t size)
 {
 	static int first = 1;
+	int ipos = 0;
+	int i;
+	int req_size = 0;
 
 #ifdef VALID_REQUEST_ONLY
 	const int checksum_offset = offsetof(struct ec_host_request, checksum);
@@ -72,13 +77,9 @@ static int hostcmd_fill(const uint8_t *data, size_t size)
 	chunks[2].start = chunks[1].start + chunks[1].size + data_len_size;
 	chunks[2].size = sizeof(req_buf) - chunks[2].start;
 #else
-	struct chunk chunks[1] = { {0, sizeof(req_buf)} };
+	struct chunk chunks[1] = { { 0, sizeof(req_buf) } };
 #endif
 
-	int ipos = 0;
-	int i;
-	int req_size = 0;
-
 	/*
 	 * TODO(chromium:854975): We should probably malloc req_buf with the
 	 * correct size, to make we do not read uninitialized req_buf data.
@@ -90,7 +91,7 @@ static int hostcmd_fill(const uint8_t *data, size_t size)
 	 * over checksum and data_len.
 	 */
 	for (i = 0; i < ARRAY_SIZE(chunks) && ipos < size; i++) {
-		int cp_size = MIN(chunks[i].size, size-ipos);
+		int cp_size = MIN(chunks[i].size, size - ipos);
 
 		memcpy(req_buf + chunks[i].start, data + ipos, cp_size);
 
@@ -113,8 +114,11 @@ static int hostcmd_fill(const uint8_t *data, size_t size)
 	 * issues.
 	 */
 	if (first) {
-		ccprintf("Request: cmd=%04x data=%ph\n",
-			req->command, HEX_BUF(req_buf, req_size));
+		char str_buf[hex_str_buf_size(req_size)];
+
+		snprintf_hex_buffer(str_buf, sizeof(str_buf),
+				    HEX_BUF(req_buf, req_size));
+		ccprintf("Request: cmd=%04x data=%s\n", req->command, str_buf);
 		first = 0;
 	}
 
@@ -131,7 +135,7 @@ static int hostcmd_fill(const uint8_t *data, size_t size)
 static pthread_cond_t done_cond;
 static pthread_mutex_t lock;
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	ccprints("Fuzzing task started");
 	wait_for_task_started();
@@ -151,7 +155,7 @@ int test_fuzz_one_input(const uint8_t *data, unsigned int size)
 	if (hostcmd_fill(data, size) < 0)
 		return 0;
 
-	task_set_event(TASK_ID_TEST_RUNNER, TASK_EVENT_FUZZ, 0);
+	task_set_event(TASK_ID_TEST_RUNNER, TASK_EVENT_FUZZ);
 	pthread_cond_wait(&done_cond, &lock);
 
 #ifdef VALID_REQUEST_ONLY
@@ -166,4 +170,3 @@ int test_fuzz_one_input(const uint8_t *data, unsigned int size)
 
 	return 0;
 }
-
diff --git a/fuzz/host_command_fuzz.mocklist b/fuzz/host_command_fuzz.mocklist
index 4ffc786b32..9dc068bce7 100644
--- a/fuzz/host_command_fuzz.mocklist
+++ b/fuzz/host_command_fuzz.mocklist
@@ -1,10 +1,10 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
  #define CONFIG_TEST_MOCK_LIST \
-	MOCK(FP_SENSOR)        \
+	MOCK(FPSENSOR)        \
 	MOCK(FPSENSOR_DETECT)  \
 	MOCK(MKBP_EVENTS)      \
 	MOCK(ROLLBACK)
diff --git a/fuzz/host_command_fuzz.tasklist b/fuzz/host_command_fuzz.tasklist
index 2ff8a94d98..1edc0ce0cb 100644
--- a/fuzz/host_command_fuzz.tasklist
+++ b/fuzz/host_command_fuzz.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/fuzz/pchg_fuzz.c b/fuzz/pchg_fuzz.c
new file mode 100644
index 0000000000..9b265066d2
--- /dev/null
+++ b/fuzz/pchg_fuzz.c
@@ -0,0 +1,128 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Test peripheral device charger module.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "driver/nfc/ctn730.h"
+#include "peripheral_charger.h"
+#include "task.h"
+#include "test_util.h"
+#include "timer.h"
+#include "util.h"
+
+#include <stdlib.h>
+#include <string.h>
+
+#include <pthread.h>
+
+#define TASK_EVENT_FUZZ TASK_EVENT_CUSTOM_BIT(0)
+
+extern struct pchg_drv ctn730_drv;
+struct pchg pchgs[] = {
+	[0] = {
+		.cfg = &(const struct pchg_config) {
+			.drv = &ctn730_drv,
+			.i2c_port = I2C_PORT_WLC,
+			.irq_pin = GPIO_WLC_IRQ_CONN,
+			.full_percent = 96,
+			.block_size = 128,
+		},
+		.events = QUEUE_NULL(PCHG_EVENT_QUEUE_SIZE, enum pchg_event),
+	},
+};
+
+static pthread_cond_t done_cond;
+static pthread_mutex_t lock;
+
+#define MAX_MESSAGES 8
+#define MAX_MESSAGE_SIZE             \
+	(sizeof(struct ctn730_msg) + \
+	 member_size(struct ctn730_msg, length) * 256)
+static uint8_t input[MAX_MESSAGE_SIZE * MAX_MESSAGES];
+static uint8_t *head, *tail;
+static bool data_available;
+
+int board_get_pchg_count(void)
+{
+	return ARRAY_SIZE(pchgs);
+}
+
+int pchg_i2c_xfer(int port, uint16_t addr_flags, const uint8_t *out,
+		  int out_size, uint8_t *in, int in_size, int flags)
+{
+	if (port != I2C_PORT_WLC || addr_flags != CTN730_I2C_ADDR)
+		return EC_ERROR_INVAL;
+
+	if (in == NULL || in_size == 0)
+		return EC_SUCCESS;
+
+	if (head + in_size >= tail) {
+		data_available = false;
+		return EC_ERROR_OVERFLOW;
+	}
+
+	memcpy(in, head, in_size);
+	head += in_size;
+
+	return EC_SUCCESS;
+}
+DECLARE_TEST_I2C_XFER(pchg_i2c_xfer);
+
+/*
+ * Task for generating IRQs. The task priority is lower than the PCHG task so
+ * that it can yield the CPU to the PCHG task.
+ */
+void irq_task(int argc, char **argv)
+{
+	ccprints("%s task started", __func__);
+	wait_for_task_started();
+
+	while (1) {
+		int i = 0;
+
+		task_wait_event_mask(TASK_EVENT_FUZZ, -1);
+		test_chipset_on();
+
+		while (data_available && i++ < MAX_MESSAGES)
+			pchg_irq(pchgs[0].cfg->irq_pin);
+
+		test_chipset_off();
+
+		pthread_mutex_lock(&lock);
+		pthread_cond_signal(&done_cond);
+		pthread_mutex_unlock(&lock);
+	}
+}
+
+void run_test(int argc, const char **argv)
+{
+	ccprints("Fuzzing task started");
+	task_wait_event(-1);
+}
+
+int test_fuzz_one_input(const uint8_t *data, unsigned int size)
+{
+	/* We're not interested in too small or too large input. */
+	if (size < sizeof(struct ctn730_msg) || sizeof(input) < size)
+		return 0;
+
+	pthread_mutex_init(&lock, NULL);
+	pthread_cond_init(&done_cond, NULL);
+
+	head = input;
+	tail = input + size;
+	memcpy(input, data, size);
+	data_available = true;
+
+	task_set_event(TASK_ID_IRQ, TASK_EVENT_FUZZ);
+
+	pthread_mutex_lock(&lock);
+	pthread_cond_wait(&done_cond, &lock);
+	pthread_mutex_unlock(&lock);
+
+	return 0;
+}
diff --git a/fuzz/pchg_fuzz.corpus b/fuzz/pchg_fuzz.corpus
new file mode 100644
index 0000000000..0b069baf4f
--- /dev/null
+++ b/fuzz/pchg_fuzz.corpus
@@ -0,0 +1,26 @@
+"\xae\x01"
+"\x18\x01\x00\x00"
+"\xff~"
+"\x01u"
+"\x80\x00\x00\x00"
+"Q\x00"
+"5\x00"
+"\xb7\x01\x00\x00"
+"\x01\x00\x00\x00\x01\x00\x00\x00"
+"\x00\x00\x00\x00\x00\x00\x00\x00"
+"\xff\xff\xff\x00n_\x0b\xc0"
+"\x92\x00"
+"\xff\xdc"
+"\xa6\x01"
+"\x85f\xfc$\x00\x00\x00\x00"
+"\xff\xff\xff\xff\xff\xff\xff\xff"
+"\xff\xff\xff\xff\x00\x00\x00\x00"
+"\xfff"
+"\x01\xcb"
+"\x8f\x00\x00\x00"
+"\xff\xff\xff\x0d"
+"=\x00\x00\x00"
+"\xbc\x00"
+"\x02\x91"
+"\xff\xff\xff\x00\x00\x00\x00\x00"
+"\x00y"
diff --git a/fuzz/pchg_fuzz.tasklist b/fuzz/pchg_fuzz.tasklist
new file mode 100644
index 0000000000..7c57f19854
--- /dev/null
+++ b/fuzz/pchg_fuzz.tasklist
@@ -0,0 +1,12 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST \
+	TASK_TEST(IRQ, irq_task, NULL, TASK_STACK_SIZE) \
+	TASK_TEST(PCHG, pchg_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_TEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/fuzz/span.h b/fuzz/span.h
index 531df832a3..de144efe60 100644
--- a/fuzz/span.h
+++ b/fuzz/span.h
@@ -1,56 +1,83 @@
-// Copyright 2018 The Chromium OS Authors. All rights reserved.
+// Copyright 2018 The ChromiumOS Authors
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #ifndef __FUZZ_SPAN_H
 #define __FUZZ_SPAN_H
 
-#include <unistd.h>
-
 #include <algorithm>
+#include <unistd.h>
 
-namespace fuzz {
+namespace fuzz
+{
 
-template <typename T>
-class span {
- public:
-  typedef T value_type;
+template <typename T> class span {
+    public:
+	typedef T value_type;
 
-  constexpr span() : span<T>(nullptr, nullptr) {}
-  constexpr span(T* begin, size_t size) : begin_(begin), end_(begin + size) {}
-  constexpr span(T* begin, T* end) : begin_(begin), end_(end) {}
+	constexpr span()
+		: span<T>(nullptr, nullptr)
+	{
+	}
+	constexpr span(T *begin, size_t size)
+		: begin_(begin)
+		, end_(begin + size)
+	{
+	}
+	constexpr span(T *begin, T *end)
+		: begin_(begin)
+		, end_(end)
+	{
+	}
 
-  template <class Container>
-  constexpr span(Container& container)
-      : begin_(container.begin()), end_(container.end()){};
+	template <class Container>
+	constexpr span(Container &container)
+		: begin_(container.begin())
+		, end_(container.end()){};
 
-  constexpr T* begin() const { return begin_; }
-  constexpr T* end() const { return end_; }
+	constexpr T *begin() const
+	{
+		return begin_;
+	}
+	constexpr T *end() const
+	{
+		return end_;
+	}
 
-  constexpr T* data() const { return begin_; }
+	constexpr T *data() const
+	{
+		return begin_;
+	}
 
-  constexpr bool empty() const { return begin_ == end_; }
-  constexpr size_t size() const { return end_ - begin_; }
+	constexpr bool empty() const
+	{
+		return begin_ == end_;
+	}
+	constexpr size_t size() const
+	{
+		return end_ - begin_;
+	}
 
- private:
-  T* begin_;
-  T* end_;
+    private:
+	T *begin_;
+	T *end_;
 };
 
 template <typename Source, typename Destination>
-size_t CopyWithPadding(Source source,
-                       Destination destination,
-                       typename Destination::value_type fill_value) {
-  if (source.size() >= destination.size()) {
-    std::copy(source.begin(), source.begin() + destination.size(),
-              destination.begin());
-    return destination.size();
-  }
-  std::copy(source.begin(), source.end(), destination.begin());
-  std::fill(destination.begin() + source.size(), destination.end(), fill_value);
-  return source.size();
+size_t CopyWithPadding(Source source, Destination destination,
+		       typename Destination::value_type fill_value)
+{
+	if (source.size() >= destination.size()) {
+		std::copy(source.begin(), source.begin() + destination.size(),
+			  destination.begin());
+		return destination.size();
+	}
+	std::copy(source.begin(), source.end(), destination.begin());
+	std::fill(destination.begin() + source.size(), destination.end(),
+		  fill_value);
+	return source.size();
 }
 
-}  // namespace fuzz
+} // namespace fuzz
 
-#endif  // __FUZZ_SPAN_H
+#endif // __FUZZ_SPAN_H
diff --git a/fuzz/usb_pd_fuzz.c b/fuzz/usb_pd_fuzz.c
index ab0ab2439e..809e09cdbb 100644
--- a/fuzz/usb_pd_fuzz.c
+++ b/fuzz/usb_pd_fuzz.c
@@ -1,50 +1,77 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Test USB PD module.
  */
-#define HIDE_EC_STDLIB
 #include "common.h"
 #include "task.h"
-#include "tcpm.h"
+#include "tcpm/tcpm.h"
 #include "test_util.h"
 #include "timer.h"
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#include <pthread.h>
 #include <stdlib.h>
 #include <string.h>
 
+#include <pthread.h>
+
 #define TASK_EVENT_FUZZ TASK_EVENT_CUSTOM_BIT(0)
 
-#define PORT0	0
+#define PORT0 0
 
-static int mock_tcpm_init(int port) { return EC_SUCCESS; }
-static int mock_tcpm_release(int port) { return EC_SUCCESS; }
+static int mock_tcpm_init(int port)
+{
+	return EC_SUCCESS;
+}
+static int mock_tcpm_release(int port)
+{
+	return EC_SUCCESS;
+}
 
 static int mock_tcpm_select_rp_value(int port, int rp)
 {
 	return EC_SUCCESS;
 }
 
-static int mock_tcpm_set_cc(int port, int pull) { return EC_SUCCESS; }
+static int mock_tcpm_set_cc(int port, int pull)
+{
+	return EC_SUCCESS;
+}
 static int mock_tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity)
 {
 	return EC_SUCCESS;
 }
 
-static int mock_tcpm_set_vconn(int port, int enable) { return EC_SUCCESS; }
-static int mock_tcpm_set_msg_header(int port,
-			int power_role, int data_role) { return EC_SUCCESS; }
-static int mock_tcpm_set_rx_enable(int port, int enable) { return EC_SUCCESS; }
-static int mock_tcpm_transmit(int port, enum tcpm_transmit_type type,
-		uint16_t header, const uint32_t *data) { return EC_SUCCESS; }
-static void mock_tcpc_alert(int port) {}
+static __maybe_unused int mock_tcpm_sop_prime_enable(int port, bool enable)
+{
+	return EC_SUCCESS;
+}
+
+static int mock_tcpm_set_vconn(int port, int enable)
+{
+	return EC_SUCCESS;
+}
+static int mock_tcpm_set_msg_header(int port, int power_role, int data_role)
+{
+	return EC_SUCCESS;
+}
+static int mock_tcpm_set_rx_enable(int port, int enable)
+{
+	return EC_SUCCESS;
+}
+static int mock_tcpm_transmit(int port, enum tcpci_msg_type type,
+			      uint16_t header, const uint32_t *data)
+{
+	return EC_SUCCESS;
+}
+static void mock_tcpc_alert(int port)
+{
+}
 static int mock_tcpci_get_chip_info(int port, int live,
-		struct ec_response_pd_chip_info_v1 *info)
+				    struct ec_response_pd_chip_info_v1 *info)
 {
 	return EC_ERROR_UNIMPLEMENTED;
 }
@@ -70,7 +97,7 @@ struct tcpc_state {
 static struct tcpc_state mock_tcpc_state[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 static int mock_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2)
+			    enum tcpc_cc_voltage_status *cc2)
 {
 	*cc1 = mock_tcpc_state[port].cc1;
 	*cc2 = mock_tcpc_state[port].cc2;
@@ -114,33 +141,38 @@ int tcpm_enqueue_message(const int port)
 	pending = 1;
 
 	/* Wake PD task up so it can process incoming RX messages */
-	task_set_event(PD_PORT_TO_TASK_ID(port), TASK_EVENT_WAKE, 0);
+	task_set_event(PD_PORT_TO_TASK_ID(port), TASK_EVENT_WAKE);
 
 	return EC_SUCCESS;
 }
 
-void tcpm_clear_pending_messages(int port) {}
+void tcpm_clear_pending_messages(int port)
+{
+}
 
 static const struct tcpm_drv mock_tcpm_drv = {
-	.init                   = &mock_tcpm_init,
-	.release                = &mock_tcpm_release,
-	.get_cc                 = &mock_tcpm_get_cc,
+	.init = &mock_tcpm_init,
+	.release = &mock_tcpm_release,
+	.get_cc = &mock_tcpm_get_cc,
 #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	.check_vbus_level       = &mock_tcpm_check_vbus_level,
+	.check_vbus_level = &mock_tcpm_check_vbus_level,
 #endif
-	.select_rp_value        = &mock_tcpm_select_rp_value,
-	.set_cc                 = &mock_tcpm_set_cc,
-	.set_polarity           = &mock_tcpm_set_polarity,
-	.set_vconn              = &mock_tcpm_set_vconn,
-	.set_msg_header         = &mock_tcpm_set_msg_header,
-	.set_rx_enable          = &mock_tcpm_set_rx_enable,
+	.select_rp_value = &mock_tcpm_select_rp_value,
+	.set_cc = &mock_tcpm_set_cc,
+	.set_polarity = &mock_tcpm_set_polarity,
+#ifdef CONFIG_USB_PD_DECODE_SOP
+	.sop_prime_enable = &mock_tcpm_sop_prime_enable,
+#endif
+	.set_vconn = &mock_tcpm_set_vconn,
+	.set_msg_header = &mock_tcpm_set_msg_header,
+	.set_rx_enable = &mock_tcpm_set_rx_enable,
 	/* The core calls tcpm_dequeue_message. */
-	.get_message_raw        = NULL,
-	.transmit               = &mock_tcpm_transmit,
-	.tcpc_alert             = &mock_tcpc_alert,
-	.get_chip_info          = &mock_tcpci_get_chip_info,
+	.get_message_raw = NULL,
+	.transmit = &mock_tcpm_transmit,
+	.tcpc_alert = &mock_tcpc_alert,
+	.get_chip_info = &mock_tcpci_get_chip_info,
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	.enter_low_power_mode   = &mock_enter_low_power_mode,
+	.enter_low_power_mode = &mock_enter_low_power_mode,
 #endif
 };
 
@@ -158,10 +190,10 @@ static pthread_cond_t done_cond;
 static pthread_mutex_t lock;
 
 enum tcpc_cc_voltage_status next_cc1, next_cc2;
-const int MAX_MESSAGES = 8;
+#define MAX_MESSAGES 8
 static struct message messages[MAX_MESSAGES];
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	uint8_t port = PORT0;
 	int i;
@@ -172,29 +204,30 @@ void run_test(int argc, char **argv)
 	while (1) {
 		task_wait_event_mask(TASK_EVENT_FUZZ, -1);
 
-		memset(&mock_tcpc_state[port],
-			0, sizeof(mock_tcpc_state[port]));
+		memset(&mock_tcpc_state[port], 0,
+		       sizeof(mock_tcpc_state[port]));
 
-		task_set_event(PD_PORT_TO_TASK_ID(port),
-			PD_EVENT_TCPC_RESET, 0);
+		task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_TCPC_RESET);
 		task_wait_event(250 * MSEC);
 
 		mock_tcpc_state[port].cc1 = next_cc1;
 		mock_tcpc_state[port].cc2 = next_cc2;
 
-		task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_CC, 0);
+		task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_CC);
 		task_wait_event(50 * MSEC);
 
 		/* Fake RX messages, one by one. */
 		for (i = 0; i < MAX_MESSAGES && messages[i].cnt; i++) {
 			memcpy(&mock_tcpc_state[port].message, &messages[i],
-				sizeof(messages[i]));
+			       sizeof(messages[i]));
 
 			tcpm_enqueue_message(port);
 			task_wait_event(50 * MSEC);
 		}
 
+		pthread_mutex_lock(&lock);
 		pthread_cond_signal(&done_cond);
+		pthread_mutex_unlock(&lock);
 	}
 }
 
@@ -212,21 +245,23 @@ int test_fuzz_one_input(const uint8_t *data, unsigned int size)
 
 	next_cc1 = data[0] & 0x0f;
 	next_cc2 = (data[0] & 0xf0) >> 4;
-	data++; size--;
+	data++;
+	size--;
 
 	memset(messages, 0, sizeof(messages));
 
 	for (i = 0; i < MAX_MESSAGES && size > 0; i++) {
 		int cnt = data[0];
 
-		if (cnt < 3 || cnt > MAX_TCPC_PAYLOAD+3 || cnt > size) {
+		if (cnt < 3 || cnt > MAX_TCPC_PAYLOAD + 3 || cnt > size) {
 			/* Invalid count, or out of bounds. */
 			return 0;
 		}
 
 		memcpy(&messages[i], data, cnt);
 
-		data += cnt; size -= cnt;
+		data += cnt;
+		size -= cnt;
 	}
 
 	if (size != 0) {
@@ -234,8 +269,17 @@ int test_fuzz_one_input(const uint8_t *data, unsigned int size)
 		return 0;
 	}
 
-	task_set_event(TASK_ID_TEST_RUNNER, TASK_EVENT_FUZZ, 0);
+	pthread_mutex_init(&lock, NULL);
+	pthread_cond_init(&done_cond, NULL);
+
+	task_set_event(TASK_ID_TEST_RUNNER, TASK_EVENT_FUZZ);
+
+	pthread_mutex_lock(&lock);
 	pthread_cond_wait(&done_cond, &lock);
+	pthread_mutex_unlock(&lock);
+
+	pthread_cond_destroy(&done_cond);
+	pthread_mutex_destroy(&lock);
 
 	return 0;
 }
diff --git a/fuzz/usb_pd_fuzz.tasklist b/fuzz/usb_pd_fuzz.tasklist
index 6edeac2f98..c006f00784 100644
--- a/fuzz/usb_pd_fuzz.tasklist
+++ b/fuzz/usb_pd_fuzz.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/fuzz/usb_tcpm_v2_rev20_fuzz.c b/fuzz/usb_tcpm_v2_rev20_fuzz.c
index f5afb92ac1..c4f57432ad 100644
--- a/fuzz/usb_tcpm_v2_rev20_fuzz.c
+++ b/fuzz/usb_tcpm_v2_rev20_fuzz.c
@@ -1,11 +1,10 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Stubs needed for fuzz testing the USB TCPMv2 state machines.
  */
 
-#define HIDE_EC_STDLIB
 #include "charge_manager.h"
 #include "mock/usb_mux_mock.h"
 #include "usb_pd.h"
@@ -17,12 +16,18 @@ const struct svdm_response svdm_rsp = {
 };
 
 /* USB mux configuration */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.driver = &mock_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.driver = &mock_usb_mux_driver,
+			},
 	},
 	{
-		.driver = &mock_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.driver = &mock_usb_mux_driver,
+			},
 	}
 };
 
@@ -30,4 +35,3 @@ int pd_check_vconn_swap(int port)
 {
 	return 1;
 }
-
diff --git a/fuzz/usb_tcpm_v2_rev20_fuzz.mocklist b/fuzz/usb_tcpm_v2_rev20_fuzz.mocklist
index 1b2c615371..fe2a3f8f38 100644
--- a/fuzz/usb_tcpm_v2_rev20_fuzz.mocklist
+++ b/fuzz/usb_tcpm_v2_rev20_fuzz.mocklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/fuzz/usb_tcpm_v2_rev20_fuzz.tasklist b/fuzz/usb_tcpm_v2_rev20_fuzz.tasklist
index e3ad19e719..d20bba1365 100644
--- a/fuzz/usb_tcpm_v2_rev20_fuzz.tasklist
+++ b/fuzz/usb_tcpm_v2_rev20_fuzz.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/2id.h b/include/2id.h
index 8daa4d27db..8d05f96e56 100644
--- a/include/2id.h
+++ b/include/2id.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -25,8 +25,23 @@ struct vb2_id {
 #define EXPECTED_ID_SIZE VB2_ID_NUM_BYTES
 
 /* IDs to use for "keys" with sig_alg==VB2_SIG_NONE */
-#define VB2_ID_NONE_SHA1   {{0x00, 0x01,}}
-#define VB2_ID_NONE_SHA256 {{0x02, 0x56,}}
-#define VB2_ID_NONE_SHA512 {{0x05, 0x12,}}
+#define VB2_ID_NONE_SHA1            \
+	{                           \
+		{                   \
+			0x00, 0x01, \
+		}                   \
+	}
+#define VB2_ID_NONE_SHA256          \
+	{                           \
+		{                   \
+			0x02, 0x56, \
+		}                   \
+	}
+#define VB2_ID_NONE_SHA512          \
+	{                           \
+		{                   \
+			0x05, 0x12, \
+		}                   \
+	}
 
-#endif  /* VBOOT_REFERENCE_VBOOT_2ID_H_ */
+#endif /* VBOOT_REFERENCE_VBOOT_2ID_H_ */
diff --git a/include/accel_cal.h b/include/accel_cal.h
index 80f0161a04..2f7b5d6bbf 100644
--- a/include/accel_cal.h
+++ b/include/accel_cal.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/accelgyro.h b/include/accelgyro.h
index e1226bc3e4..a0bdfa504a 100644
--- a/include/accelgyro.h
+++ b/include/accelgyro.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,8 +6,9 @@
 #ifndef __CROS_EC_ACCELGYRO_H
 #define __CROS_EC_ACCELGYRO_H
 
-#include "motion_sense.h"
+#include "common.h"
 #include "math_util.h"
+#include "motion_sense.h"
 
 /* Header file for accelerometer / gyro drivers. */
 
@@ -22,11 +23,10 @@
 struct accelgyro_drv {
 	/**
 	 * Initialize accelerometers.
-	 * @s Pointer to sensor data pointer. Sensor data will be
-	 * allocated on success.
+	 * @s Pointer to sensor data pointer.
 	 * @return EC_SUCCESS if successful, non-zero if error.
 	 */
-	int (*init)(const struct motion_sensor_t *s);
+	int (*init)(struct motion_sensor_t *s);
 
 	/**
 	 * Read all three accelerations of an accelerometer. Note that all
@@ -48,19 +48,20 @@ struct accelgyro_drv {
 	int (*read_temp)(const struct motion_sensor_t *s, int *temp);
 
 	/**
-	 * Setter and getter methods for the sensor range. The sensor range
+	 * Setter method for the sensor range. The sensor range
 	 * defines the maximum value that can be returned from read(). As the
 	 * range increases, the resolution gets worse.
 	 * @s Pointer to sensor data.
 	 * @range Range (Units are +/- G's for accel, +/- deg/s for gyro)
 	 * @rnd Rounding flag. If true, it rounds up to nearest valid
 	 * value. Otherwise, it rounds down.
+	 *
+	 * sensor->current_range is updated.
+	 * It will be preserved unless EC reboots or AP is shutdown (S5).
+	 *
 	 * @return EC_SUCCESS if successful, non-zero if error.
 	 */
-	int (*set_range)(const struct motion_sensor_t *s,
-			int range,
-			int rnd);
-	int (*get_range)(const struct motion_sensor_t *s);
+	int (*set_range)(struct motion_sensor_t *s, int range, int rnd);
 
 	/**
 	 * Setter and getter methods for the sensor resolution.
@@ -70,9 +71,8 @@ struct accelgyro_drv {
 	 * value. Otherwise, it rounds down.
 	 * @return EC_SUCCESS if successful, non-zero if error.
 	 */
-	int (*set_resolution)(const struct motion_sensor_t *s,
-				int res,
-				int rnd);
+	int (*set_resolution)(const struct motion_sensor_t *s, int res,
+			      int rnd);
 	int (*get_resolution)(const struct motion_sensor_t *s);
 
 	/**
@@ -84,12 +84,10 @@ struct accelgyro_drv {
 	 * value. Otherwise, it rounds down.
 	 * @return EC_SUCCESS if successful, non-zero if error.
 	 */
-	int (*set_data_rate)(const struct motion_sensor_t *s,
-				int rate,
-				int rnd);
+	int (*set_data_rate)(const struct motion_sensor_t *s, int rate,
+			     int rnd);
 	int (*get_data_rate)(const struct motion_sensor_t *s);
 
-
 	/**
 	 * Setter and getter methods for the sensor offset.
 	 * @s Pointer to sensor data.
@@ -98,11 +96,9 @@ struct accelgyro_drv {
 	 * @return EC_SUCCESS if successful, non-zero if error.
 	 */
 	int (*set_offset)(const struct motion_sensor_t *s,
-				const int16_t    *offset,
-				int16_t    temp);
-	int (*get_offset)(const struct motion_sensor_t *s,
-				int16_t    *offset,
-				int16_t    *temp);
+			  const int16_t *offset, int16_t temp);
+	int (*get_offset)(const struct motion_sensor_t *s, int16_t *offset,
+			  int16_t *temp);
 	/**
 	 * Setter and getter methods for the sensor scale.
 	 * @s Pointer to sensor data.
@@ -110,20 +106,33 @@ struct accelgyro_drv {
 	 * @temp: temperature when calibration was done.
 	 * @return EC_SUCCESS if successful, non-zero if error.
 	 */
-	int (*set_scale)(const struct motion_sensor_t *s,
-				const uint16_t    *scale,
-				int16_t    temp);
-	int (*get_scale)(const struct motion_sensor_t *s,
-				uint16_t   *scale,
-				int16_t    *temp);
+	int (*set_scale)(const struct motion_sensor_t *s, const uint16_t *scale,
+			 int16_t temp);
+	int (*get_scale)(const struct motion_sensor_t *s, uint16_t *scale,
+			 int16_t *temp);
 	/**
 	 * Request performing/entering calibration.
 	 * Either a one shot mode (enable is not used),
 	 * or enter/exit a calibration state.
 	 */
-	int (*perform_calib)(const struct motion_sensor_t *s,
-				int        enable);
-#ifdef CONFIG_ACCEL_INTERRUPTS
+	int (*perform_calib)(struct motion_sensor_t *s, int enable);
+
+	/**
+	 * Function that probes if supported chip is present.
+	 * This pointer can be NULL if driver doesn't implement probing.
+	 *
+	 * @s Pointer to sensor data.
+	 * @return EC_SUCCESS if the probe was successful, non-zero otherwise.
+	 */
+	int (*probe)(const struct motion_sensor_t *s);
+
+	/**
+	 * Interrupt handler for GPIO pin.
+	 *
+	 * @signal Signal which caused interrupt.
+	 */
+	void (*interrupt)(enum gpio_signal signal);
+
 	/**
 	 * handler for interrupts triggered by the sensor: it runs in task and
 	 * process the events that triggered an interrupt.
@@ -134,8 +143,6 @@ struct accelgyro_drv {
 	 * when no events have been processed.
 	 */
 	int (*irq_handler)(struct motion_sensor_t *s, uint32_t *event);
-#endif
-#ifdef CONFIG_GESTURE_DETECTION
 	/**
 	 * handler for setting/getting activity information.
 	 * Manage the high level activity detection of the chip.
@@ -145,8 +152,7 @@ struct accelgyro_drv {
 	 * @data additional data if needed, activity dependent.
 	 */
 	int (*manage_activity)(const struct motion_sensor_t *s,
-			       enum motionsensor_activity activity,
-			       int enable,
+			       enum motionsensor_activity activity, int enable,
 			       const struct ec_motion_sense_activity *data);
 	/**
 	 * List activities managed by the sensors.
@@ -155,16 +161,12 @@ struct accelgyro_drv {
 	 * @disabled bit mask of activities currently disabled.
 	 */
 	int (*list_activities)(const struct motion_sensor_t *s,
-			       uint32_t *enabled,
-			       uint32_t *disabled);
+			       uint32_t *enabled, uint32_t *disabled);
 
-#endif
-#ifdef CONFIG_BODY_DETECTION
 	/**
 	 * Get the root mean square of current noise (ug/mdps) in the sensor.
 	 */
 	int (*get_rms_noise)(const struct motion_sensor_t *s);
-#endif
 };
 
 /* Index values for rgb_calibration_t.coeff array */
@@ -187,7 +189,6 @@ enum rgb_index {
 /* Used to save sensor information */
 struct accelgyro_saved_data_t {
 	int odr;
-	int range;
 	uint16_t scale[3];
 };
 
@@ -236,9 +237,9 @@ struct rgb_calibration_t {
 
 /* als driver data */
 struct als_drv_data_t {
-	int rate;          /* holds current sensor rate */
-	int last_value;    /* holds last als clear channel value */
-	struct als_calibration_t als_cal;    /* calibration data */
+	int rate; /* holds current sensor rate */
+	int last_value; /* holds last als clear channel value */
+	struct als_calibration_t als_cal; /* calibration data */
 };
 
 #define SENSOR_APPLY_DIV_SCALE(_input, _scale) \
@@ -248,6 +249,6 @@ struct als_drv_data_t {
 	(((_input) * (uint64_t)(_scale)) / MOTION_SENSE_DEFAULT_SCALE)
 
 /* Individual channel scale value between 0 and 2 represented in 16 bits */
-#define ALS_CHANNEL_SCALE(_x) ((_x) * MOTION_SENSE_DEFAULT_SCALE)
+#define ALS_CHANNEL_SCALE(_x) ((_x)*MOTION_SENSE_DEFAULT_SCALE)
 
 #endif /* __CROS_EC_ACCELGYRO_H */
diff --git a/include/acpi.h b/include/acpi.h
index 56930c4b2d..b99fe9a235 100644
--- a/include/acpi.h
+++ b/include/acpi.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -74,4 +74,4 @@ int acpi_dptf_set_profile_num(int n);
  */
 int acpi_dptf_get_profile_num(void);
 
-#endif	/* __CROS_EC_ACPI_H */
+#endif /* __CROS_EC_ACPI_H */
diff --git a/include/adc.h b/include/adc.h
index 545a5e503b..a73b4ac9aa 100644
--- a/include/adc.h
+++ b/include/adc.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,9 +8,33 @@
 #ifndef __CROS_EC_ADC_H
 #define __CROS_EC_ADC_H
 
+#include "adc_chip.h"
 #include "common.h"
 
-#define ADC_READ_ERROR -1  /* Value returned by adc_read_channel() on error */
+#define ADC_READ_ERROR -1 /* Value returned by adc_read_channel() on error */
+
+#ifdef CONFIG_ZEPHYR
+#include <zephyr_adc.h>
+#endif /* CONFIG_ZEPHYR */
+
+#ifdef CONFIG_ADC
+/*
+ * Boards must provide this list of ADC channel definitions.  This must match
+ * the enum adc_channel list provided by the board.
+ */
+#ifndef CONFIG_ADC_CHANNELS_RUNTIME_CONFIG
+extern const struct adc_t adc_channels[];
+#else
+extern struct adc_t adc_channels[];
+#endif
+#endif /* CONFIG_ADC */
+
+/**
+ * ADC initial.
+ */
+#ifdef CONFIG_KEYBOARD_SCAN_ADC
+void adc_init(void);
+#endif
 
 /*
  * Boards which use the ADC interface must provide enum adc_channel in the
@@ -58,4 +82,4 @@ int adc_disable_watchdog(void);
  */
 int adc_set_watchdog_delay(int delay_ms);
 
-#endif  /* __CROS_EC_ADC_H */
+#endif /* __CROS_EC_ADC_H */
diff --git a/include/aes-gcm.h b/include/aes-gcm.h
deleted file mode 120000
index ba62939792..0000000000
--- a/include/aes-gcm.h
+++ /dev/null
@@ -1 +0,0 @@
-../third_party/boringssl/include/aes-gcm.h
\ No newline at end of file
diff --git a/include/aes.h b/include/aes.h
deleted file mode 120000
index b30c680a6a..0000000000
--- a/include/aes.h
+++ /dev/null
@@ -1 +0,0 @@
-../third_party/boringssl/include/aes.h
\ No newline at end of file
diff --git a/include/als.h b/include/als.h
index 4ff3fcdb4f..21c373c9b6 100644
--- a/include/als.h
+++ b/include/als.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -34,4 +34,4 @@ extern struct als_t als[];
  */
 int als_read(enum als_id id, int *lux);
 
-#endif  /* __CROS_EC_ALS_H */
+#endif /* __CROS_EC_ALS_H */
diff --git a/include/ap_hang_detect.h b/include/ap_hang_detect.h
index 9526bb0a84..8dfcce6d74 100644
--- a/include/ap_hang_detect.h
+++ b/include/ap_hang_detect.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,4 +17,4 @@
  */
 void hang_detect_stop_on_host_command(void);
 
-#endif  /* __CROS_EC_AP_HANG_DETECT_H */
+#endif /* __CROS_EC_AP_HANG_DETECT_H */
diff --git a/include/atkbd_protocol.h b/include/atkbd_protocol.h
new file mode 100644
index 0000000000..a33e6e455e
--- /dev/null
+++ b/include/atkbd_protocol.h
@@ -0,0 +1,45 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * ATKBD keyboard protocol constants.
+ *
+ * See the IBL PC AT Technical Reference Manual Section 4.
+ * i.e., 6183355_PC_AT_Technical_Reference_Mar86.pdf
+ *
+ * https://archive.org/details/bitsavers_ibmpcat618ferenceMar86_25829277/page/n151/mode/2up
+ */
+
+#ifndef __CROS_EC_ATKBD_PROTOCOL_H
+#define __CROS_EC_ATKBD_PROTOCOL_H
+
+#define ATKBD_CMD_OK_GETID 0xe8
+#define ATKBD_CMD_EX_ENABLE 0xea
+#define ATKBD_CMD_EX_SETLEDS 0xeb
+#define ATKBD_CMD_SETLEDS 0xed
+#define ATKBD_CMD_DIAG_ECHO 0xee
+#define ATKBD_CMD_GSCANSET 0xf0
+#define ATKBD_CMD_SSCANSET 0xf0
+#define ATKBD_CMD_GETID 0xf2
+#define ATKBD_CMD_SETREP 0xf3
+#define ATKBD_CMD_ENABLE 0xf4
+#define ATKBD_CMD_RESET_DIS 0xf5
+#define ATKBD_CMD_RESET_DEF 0xf6
+#define ATKBD_CMD_ALL_TYPEM 0xf7
+#define ATKBD_CMD_SETALL_MB 0xf8
+#define ATKBD_CMD_SETALL_MBR 0xfa
+#define ATKBD_CMD_SET_A_KEY_T 0xfb
+#define ATKBD_CMD_SET_A_KEY_MR 0xfc
+#define ATKBD_CMD_SET_A_KEY_M 0xfd
+#define ATKBD_CMD_RESEND 0xfe
+#define ATKBD_CMD_RESET 0xff
+
+#define ATKBD_RET_OVERFLOW 0x00
+#define ATKBD_RET_TEST_SUCCESS 0xaa
+#define ATKBD_RET_ECHO 0xee
+#define ATKBD_RET_ACK 0xfa
+#define ATKBD_RET_TEST_FAIL 0xfc
+#define ATKBD_RET_INTERNAL_FAIL 0xfd
+#define ATKBD_RET_RESEND 0xfe
+
+#endif /* __CROS_EC_ATKBD_PROTOCOL_H */
diff --git a/include/atomic_bit.h b/include/atomic_bit.h
new file mode 100644
index 0000000000..34416a2f89
--- /dev/null
+++ b/include/atomic_bit.h
@@ -0,0 +1,20 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_ATOMIC_BIT_H
+#define __CROS_EC_ATOMIC_BIT_H
+
+#ifndef CONFIG_ZEPHYR
+#include "atomic.h"
+
+static inline atomic_val_t atomic_get(const atomic_t *target)
+{
+	return __atomic_load_n(target, __ATOMIC_SEQ_CST);
+}
+
+#include "third_party/zephyr/atomic.h"
+
+#endif /* CONFIG_ZEPHYR */
+#endif /* __CROS_EC_ATOMIC_BIT_H */
diff --git a/include/atomic_t.h b/include/atomic_t.h
new file mode 100644
index 0000000000..7f95665f46
--- /dev/null
+++ b/include/atomic_t.h
@@ -0,0 +1,22 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* This file is to provide atomic_t definition */
+
+#ifndef __CROS_EC_ATOMIC_T_H
+#define __CROS_EC_ATOMIC_T_H
+
+#ifndef CONFIG_ZEPHYR
+#ifdef TEST_BUILD
+typedef int atomic_t;
+#else
+typedef long atomic_t;
+#endif
+typedef atomic_t atomic_val_t;
+#else
+#include <zephyr/sys/atomic.h>
+#endif
+
+#endif /* __CROS_EC_ATOMIC_T_H */
diff --git a/include/audio_codec.h b/include/audio_codec.h
index b80d1c0f57..431f776247 100644
--- a/include/audio_codec.h
+++ b/include/audio_codec.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -41,8 +41,8 @@ int audio_codec_capable(uint8_t cap);
  *   EC_ERROR_INVAL if invalid cap.
  *   EC_ERROR_BUSY if the shm_id has been registered.
  */
-int audio_codec_register_shm(uint8_t shm_id, uint8_t cap,
-		uintptr_t *addr, uint32_t len, uint8_t type);
+int audio_codec_register_shm(uint8_t shm_id, uint8_t cap, uintptr_t *addr,
+			     uint32_t len, uint8_t type);
 
 /*
  * Translates the physical address from AP to EC's memory space.  Required if
@@ -63,7 +63,6 @@ int audio_codec_memmap_ap_to_ec(uintptr_t ap_addr, uintptr_t *ec_addr);
  */
 int16_t audio_codec_s16_scale_and_clip(int16_t orig, uint8_t scalar);
 
-
 /*
  * DMIC abstract layer
  */
@@ -120,7 +119,6 @@ int audio_codec_dmic_set_gain_idx(uint8_t channel, uint8_t gain);
  */
 int audio_codec_dmic_get_gain_idx(uint8_t channel, uint8_t *gain);
 
-
 /*
  * I2S RX abstract layer
  */
@@ -181,7 +179,6 @@ int audio_codec_i2s_rx_set_daifmt(uint8_t daifmt);
  */
 int audio_codec_i2s_rx_set_bclk(uint32_t bclk);
 
-
 /*
  * WoV abstract layer
  */
diff --git a/include/backlight.h b/include/backlight.h
index 1bfafbdd2c..4d37af01c0 100644
--- a/include/backlight.h
+++ b/include/backlight.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,7 +19,9 @@
 #ifdef CONFIG_BACKLIGHT_REQ_GPIO
 void backlight_interrupt(enum gpio_signal signal);
 #else
-static inline void backlight_interrupt(enum gpio_signal signal) { }
+static inline void backlight_interrupt(enum gpio_signal signal)
+{
+}
 #endif /* !CONFIG_BACKLIGHT_REQ_GPIO */
 
 /**
@@ -27,4 +29,4 @@ static inline void backlight_interrupt(enum gpio_signal signal) { }
  */
 void enable_backlight(int enabled);
 
-#endif  /* __CROS_EC_BACKLIGHT_H */
+#endif /* __CROS_EC_BACKLIGHT_H */
diff --git a/include/base32.h b/include/base32.h
index ac04ce9c70..d1acc6ab95 100644
--- a/include/base32.h
+++ b/include/base32.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,6 +8,8 @@
 #ifndef __CROS_EC_BASE32_H
 #define __CROS_EC_BASE32_H
 
+#include <stdint.h>
+
 /* Symbol map for base32 encoding */
 extern const char base32_map[33];
 
@@ -41,9 +43,8 @@ uint8_t crc5_sym(uint8_t sym, uint8_t previous_crc);
  *				must be a multiple of add_crc_every.
  * @return EC_SUCCESS, or non-zero error code.
  */
-int base32_encode(char *dest, int destlen_chars,
-		  const void *srcbits, int srclen_bits,
-		  int add_crc_every);
+int base32_encode(char *dest, int destlen_chars, const void *srcbits,
+		  int srclen_bits, int add_crc_every);
 
 /**
  * base32-decode data from a null-terminated string
diff --git a/include/base_state.h b/include/base_state.h
index 6363ebdd7a..60b499ecd0 100644
--- a/include/base_state.h
+++ b/include/base_state.h
@@ -1,8 +1,10 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "ec_commands.h"
+
 /**
  * Return 1 if base attached, 0 otherwise.
  */
@@ -19,4 +21,4 @@ void base_set_state(int state);
  * Force the current state of the base, with 0 meaning detached,
  * 1 meaning attached and 2 meaning reset to the original state.
  */
-void base_force_state(int state);
+void base_force_state(enum ec_set_base_state_cmd state);
diff --git a/include/battery.h b/include/battery.h
index 96fa900d4f..93694bf103 100644
--- a/include/battery.h
+++ b/include/battery.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -9,62 +9,74 @@
 #define __CROS_EC_BATTERY_H
 
 #include "common.h"
+#include "compiler.h"
 #include "host_command.h"
 
-/* Battery index, only used with CONFIG_BATTERY_V2. */
-enum battery_index {
-	BATT_IDX_INVALID = -1,
-	BATT_IDX_MAIN = 0,
-	BATT_IDX_BASE = 1,
-};
+/*
+ * If compiling with Zephyr, include the BATTERY_LEVEL_ definitions that are
+ * shared with device tree
+ */
+#ifdef CONFIG_ZEPHYR
 
-#ifdef CONFIG_BATTERY_V2
-extern struct ec_response_battery_static_info
-	battery_static[CONFIG_BATTERY_COUNT];
-extern struct ec_response_battery_dynamic_info
-	battery_dynamic[CONFIG_BATTERY_COUNT];
-#endif
+#include "dt-bindings/battery.h"
 
-/* Stop charge when charging and battery level >= this percentage */
-#define BATTERY_LEVEL_FULL		100
+#else /* !CONFIG_ZEPHYR */
 
-/* Tell host we're charged when battery level >= this percentage */
-#ifdef CONFIG_BATTERY_LEVEL_NEAR_FULL
-#define BATTERY_LEVEL_NEAR_FULL		 CONFIG_BATTERY_LEVEL_NEAR_FULL
-#else
-#define BATTERY_LEVEL_NEAR_FULL		 97
-#endif
+/* Stop charge when charging and battery level >= this percentage */
+#define BATTERY_LEVEL_FULL 100
 
 /*
  * Send battery-low host event when discharging and battery level <= this level
  */
-#define BATTERY_LEVEL_LOW		 10
+#define BATTERY_LEVEL_LOW 10
 
 /*
  * Send battery-critical host event when discharging and battery level <= this
  * level.
  */
-#define BATTERY_LEVEL_CRITICAL		  5
+#define BATTERY_LEVEL_CRITICAL 5
 
 /*
  * Shut down main processor and/or hibernate EC when discharging and battery
- * level < this level.
+ * level < this level. Setting this too low makes the battery discharge too
+ * deeply, which isn't good for the battery health.
  */
-#define BATTERY_LEVEL_SHUTDOWN		  3
+#define BATTERY_LEVEL_SHUTDOWN 3
+
+#endif /* CONFIG_ZEPHYR */
+
+/* Full-capacity change reqd for host event */
+#define LFCC_EVENT_THRESH 5
+
+/* Max string size in the SB spec is 31. */
+#define SB_MAX_STR_SIZE 31
+
+/* Battery index, only used with CONFIG_BATTERY_V2. */
+enum battery_index {
+	BATT_IDX_INVALID = -1,
+	BATT_IDX_MAIN = 0,
+	BATT_IDX_BASE = 1,
+};
 
 /*
  * Sometimes we have hardware to detect battery present, sometimes we have to
  * wait until we've been able to talk to the battery.
  */
-enum battery_present {
+FORWARD_DECLARE_ENUM(battery_present){
 	BP_NOT_INIT = -1,
 	BP_NO = 0,
 	BP_YES = 1,
 	BP_NOT_SURE,
 };
 
+/*
+ * BATTERY_CUTOFF_STATE_IN_PROGRESS: Battery cutoff has begun but not completed.
+ * BATTERY_CUTOFF_STATE_PENDING: Battery cutoff is requested by the
+ * AP but hasn't started.
+ */
 enum battery_cutoff_states {
 	BATTERY_CUTOFF_STATE_NORMAL = 0,
+	BATTERY_CUTOFF_STATE_IN_PROGRESS,
 	BATTERY_CUTOFF_STATE_CUT_OFF,
 	BATTERY_CUTOFF_STATE_PENDING,
 };
@@ -75,20 +87,43 @@ enum battery_disconnect_state {
 	BATTERY_DISCONNECT_ERROR,
 };
 
+struct battery_static_info {
+	uint16_t design_capacity;
+	uint16_t design_voltage;
+	uint32_t cycle_count;
+	/*
+	 * TODO: The fields below should be renamed & re-typed:
+	 * uint16_t serial[32];
+	 * char manufacturer[32];
+	 * char device_name[32];
+	 * char chemistry[32];
+	 */
+	char manufacturer_ext[SB_MAX_STR_SIZE + 1]; /* SB_MANUFACTURER_NAME */
+	char model_ext[SB_MAX_STR_SIZE + 1]; /* SB_DEVICE_NAME */
+	char serial_ext[SB_MAX_STR_SIZE + 1]; /* SB_SERIAL_NUMBER */
+	char type_ext[SB_MAX_STR_SIZE + 1]; /* SB_DEVICE_CHEMISTRY */
+#ifdef CONFIG_BATTERY_VENDOR_PARAM
+	uint8_t vendor_param[SB_MAX_STR_SIZE + 1];
+#endif
+};
+
+extern struct battery_static_info battery_static[];
+extern struct ec_response_battery_dynamic_info battery_dynamic[];
+
 /* Battery parameters */
 struct batt_params {
-	int temperature;      /* Temperature in 0.1 K */
-	int state_of_charge;  /* State of charge (percent, 0-100) */
-	int voltage;          /* Battery voltage (mV) */
-	int current;          /* Battery current (mA); negative=discharging */
-	int desired_voltage;  /* Charging voltage desired by battery (mV) */
-	int desired_current;  /* Charging current desired by battery (mA) */
-	int remaining_capacity;  /* Remaining capacity in mAh */
-	int full_capacity;    /* Capacity in mAh (might change occasionally) */
-	int display_charge;   /* Display charge in 10ths of a % (1000=100.0%) */
-	int status;	      /* Battery status */
+	int temperature; /* Temperature in 0.1 K */
+	int state_of_charge; /* State of charge (percent, 0-100) */
+	int voltage; /* Battery voltage (mV) */
+	int current; /* Battery current (mA); negative=discharging */
+	int desired_voltage; /* Charging voltage desired by battery (mV) */
+	int desired_current; /* Charging current desired by battery (mA) */
+	int remaining_capacity; /* Remaining capacity in mAh */
+	int full_capacity; /* Capacity in mAh (might change occasionally) */
+	int display_charge; /* Display charge in 10ths of a % (1000=100.0%) */
+	int status; /* Battery status */
 	enum battery_present is_present; /* Is the battery physically present */
-	int flags;            /* Flags */
+	int flags; /* Flags */
 };
 
 /*
@@ -104,24 +139,32 @@ int battery_get_avg_voltage(void); /* in mV */
 /* Flags for batt_params */
 
 /* Battery wants to be charged */
-#define BATT_FLAG_WANT_CHARGE			0x00000001
+#define BATT_FLAG_WANT_CHARGE 0x00000001
 
 /* Battery is responsive (talking to us via I2C) */
-#define BATT_FLAG_RESPONSIVE			0x00000002
+#define BATT_FLAG_RESPONSIVE 0x00000002
 
 /* Bits to indicate which parameter(s) could not be read */
-#define BATT_FLAG_BAD_TEMPERATURE		0x00000004
-#define BATT_FLAG_BAD_STATE_OF_CHARGE		0x00000008
-#define BATT_FLAG_BAD_VOLTAGE			0x00000010
-#define BATT_FLAG_BAD_CURRENT			0x00000020
-#define BATT_FLAG_BAD_DESIRED_VOLTAGE		0x00000040
-#define BATT_FLAG_BAD_DESIRED_CURRENT		0x00000080
-#define BATT_FLAG_BAD_REMAINING_CAPACITY	0x00000100
-#define BATT_FLAG_BAD_FULL_CAPACITY		0x00000200
-#define BATT_FLAG_BAD_STATUS			0x00000400
-#define BATT_FLAG_IMBALANCED_CELL		0x00000800
+#define BATT_FLAG_BAD_TEMPERATURE 0x00000004
+#define BATT_FLAG_BAD_STATE_OF_CHARGE 0x00000008
+#define BATT_FLAG_BAD_VOLTAGE 0x00000010
+#define BATT_FLAG_BAD_CURRENT 0x00000020
+#define BATT_FLAG_BAD_DESIRED_VOLTAGE 0x00000040
+#define BATT_FLAG_BAD_DESIRED_CURRENT 0x00000080
+#define BATT_FLAG_BAD_REMAINING_CAPACITY 0x00000100
+#define BATT_FLAG_BAD_FULL_CAPACITY 0x00000200
+#define BATT_FLAG_BAD_STATUS 0x00000400
+#define BATT_FLAG_IMBALANCED_CELL 0x00000800
+#define BATT_FLAG_BAD_AVERAGE_CURRENT 0x00001000
 /* All of the above BATT_FLAG_BAD_* bits */
-#define BATT_FLAG_BAD_ANY			0x000007fc
+#define BATT_FLAG_BAD_ANY 0x000017fc
+/* Flags which are set or unset on every access (via battery_get_params) */
+#define BATT_FLAG_VOLATILE                                                  \
+	(BATT_FLAG_BAD_ANY | BATT_FLAG_WANT_CHARGE | BATT_FLAG_RESPONSIVE | \
+	 BATT_FLAG_IMBALANCED_CELL)
+
+/* The flag of prechare when the battery voltage is lower than voltage_min */
+#define BATT_FLAG_DEEP_CHARGE 0x00010000
 
 /* Battery constants */
 struct battery_info {
@@ -145,6 +188,9 @@ struct battery_info {
 	int8_t charging_max_c;
 	int8_t discharging_min_c;
 	int8_t discharging_max_c;
+#ifdef CONFIG_BATTERY_VENDOR_PARAM
+	uint8_t vendor_param_start;
+#endif
 };
 
 /**
@@ -180,7 +226,7 @@ enum battery_present battery_is_present(void);
  * If battery support is not enabled and the board does not specifically
  * provide its own implementation, assume a battery is never present.
  */
-static inline enum battery_present battery_is_present(void)
+test_mockable_static_inline enum battery_present battery_is_present(void)
 {
 	return BP_NO;
 }
@@ -368,6 +414,23 @@ int battery_device_chemistry(char *dest, int size);
  */
 int battery_manufacturer_date(int *year, int *month, int *day);
 
+/**
+ * Read battery manufacturer data.
+ *
+ * @param dest		Destination buffer.
+ * @param size		Length of destination buffer.
+ * @return non-zero if error.
+ */
+int battery_manufacturer_data(char *data, int size);
+
+/**
+ * Write battery manufacturer access.
+ *
+ * @param cmd		Destiation for battery manufacturer access command.
+ * @retun non-zeor if error.
+ */
+int battery_manufacturer_access(int cmd);
+
 /**
  * Report the absolute difference between the highest and lowest cell voltage in
  * the battery pack, in millivolts.  On error or unimplemented, returns '0'.
@@ -381,6 +444,18 @@ int battery_imbalance_mv(void);
  */
 int board_cut_off_battery(void);
 
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+/**
+ * for board cut off to change state.
+ */
+void set_battery_in_cut_off(void);
+#endif
+
+/**
+ * Return if the battery start cut off.
+ */
+int battery_cutoff_in_progress(void);
+
 /**
  * Return if the battery has been cut off.
  */
@@ -395,7 +470,7 @@ int battery_is_cut_off(void);
  * @param value		Location to store retrieved value.
  * @return non-zero if error.
  */
-int battery_get_vendor_param(uint32_t param, uint32_t *value);
+__override_proto int battery_get_vendor_param(uint32_t param, uint32_t *value);
 
 /**
  * Write battery vendor parameter.
@@ -406,7 +481,7 @@ int battery_get_vendor_param(uint32_t param, uint32_t *value);
  * @param value		Value to write to the battery.
  * @return non-zero if error.
  */
-int battery_set_vendor_param(uint32_t param, uint32_t value);
+__override_proto int battery_set_vendor_param(uint32_t param, uint32_t value);
 
 /**
  * Wait for battery stable.
@@ -471,4 +546,18 @@ void battery_compensate_params(struct batt_params *batt);
  */
 __override_proto void board_battery_compensate_params(struct batt_params *batt);
 
+void battery_validate_params(struct batt_params *batt);
+
+/**
+ * Read static battery info from a main battery and store it in a cache.
+ *
+ * @return EC_SUCCESS or EC_ERROR_*.
+ */
+int update_static_battery_info(void);
+
+/**
+ * Read dynamic battery info from a main battery and store it in a cache.
+ */
+void update_dynamic_battery_info(void);
+
 #endif /* __CROS_EC_BATTERY_H */
diff --git a/include/battery_bq27621_g1.h b/include/battery_bq27621_g1.h
index 0c388d8a52..019a9d2fe4 100644
--- a/include/battery_bq27621_g1.h
+++ b/include/battery_bq27621_g1.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -16,4 +16,3 @@ int bq27621_state_of_charge(int *percent);
  * Returns EC_SUCCESS on success.
  */
 int bq27621_init(void);
-
diff --git a/include/battery_fuel_gauge.h b/include/battery_fuel_gauge.h
index 8b1b7106bd..f3a916bb4e 100644
--- a/include/battery_fuel_gauge.h
+++ b/include/battery_fuel_gauge.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,9 +10,14 @@
 
 #include "battery.h"
 
+#include <stdbool.h>
+
 /* Number of writes needed to invoke battery cutoff command */
 #define SHIP_MODE_WRITES 2
 
+/* When battery type is not initialized */
+#define BATTERY_TYPE_UNINITIALIZED -1
+
 struct ship_mode_info {
 	/*
 	 * Write Block Support. If wb_support is true, then we use a i2c write
@@ -20,26 +25,34 @@ struct ship_mode_info {
 	 * that the i2c transaction will prefix the length (2) when wb_support
 	 * is enabled.
 	 */
-	const uint8_t wb_support;
-	const uint8_t reg_addr;
-	const uint16_t reg_data[SHIP_MODE_WRITES];
+	uint8_t wb_support;
+	uint8_t reg_addr;
+	uint16_t reg_data[SHIP_MODE_WRITES];
+};
+
+struct sleep_mode_info {
+	bool sleep_supported;
+	uint8_t reg_addr;
+	uint16_t reg_data;
 };
 
 struct fet_info {
-	const int mfgacc_support;
-	const uint8_t reg_addr;
-	const uint16_t reg_mask;
-	const uint16_t disconnect_val;
-	const uint16_t cfet_mask; /* CHG FET status mask */
-	const uint16_t cfet_off_val;
+	int mfgacc_support;
+	int mfgacc_smb_block;
+	uint8_t reg_addr;
+	uint16_t reg_mask;
+	uint16_t disconnect_val;
+	uint16_t cfet_mask; /* CHG FET status mask */
+	uint16_t cfet_off_val;
 };
 
 struct fuel_gauge_info {
-	const char *manuf_name;
-	const char *device_name;
-	const uint8_t override_nil;
-	const struct ship_mode_info ship_mode;
-	const struct fet_info fet;
+	char *manuf_name;
+	char *device_name;
+	uint8_t override_nil;
+	struct ship_mode_info ship_mode;
+	struct sleep_mode_info sleep_mode;
+	struct fet_info fet;
 
 #ifdef CONFIG_BATTERY_MEASURE_IMBALANCE
 	/* See battery_*_imbalance_mv() for functions which are suitable. */
@@ -48,15 +61,15 @@ struct fuel_gauge_info {
 };
 
 struct board_batt_params {
-	const struct fuel_gauge_info fuel_gauge;
-	const struct battery_info batt_info;
+	struct fuel_gauge_info fuel_gauge;
+	struct battery_info batt_info;
 };
 
 /* Forward declare board specific data used by common code */
+extern struct board_batt_params default_battery_conf;
 extern const struct board_batt_params board_battery_info[];
 extern const enum battery_type DEFAULT_BATTERY_TYPE;
 
-
 #ifdef CONFIG_BATTERY_MEASURE_IMBALANCE
 /**
  * Report the absolute difference between the highest and lowest cell voltage in
@@ -70,6 +83,32 @@ int battery_bq4050_imbalance_mv(void);
 
 #endif
 
+#ifdef CONFIG_BATTERY_TYPE_NO_AUTO_DETECT
+/*
+ * Set the battery type, when auto-detection cannot be used.
+ *
+ * @param type	Battery type
+ */
+void battery_set_fixed_battery_type(int type);
+#endif
+
+/**
+ * Return the board-specific default battery type.
+ *
+ * @return a value of `enum battery_type`.
+ */
+__override_proto int board_get_default_battery_type(void);
+
+/**
+ * Detect a battery model.
+ */
+void init_battery_type(void);
+
+/**
+ * Return struct board_batt_params of the battery.
+ */
+const struct board_batt_params *get_batt_params(void);
+
 /**
  * Return 1 if CFET is disabled, 0 if enabled. -1 if an error was encountered.
  * If the CFET mask is not defined, it will return 0.
@@ -77,19 +116,31 @@ int battery_bq4050_imbalance_mv(void);
 int battery_is_charge_fet_disabled(void);
 
 /**
- * Battery cut off command via SMBus write block.
+ * Send the fuel gauge sleep command through SMBus.
  *
- * @param ship_mode		Battery ship mode information
- * @return non-zero if error
+ * @return	0 if successful, non-zero if error occurred
  */
-int cut_off_battery_block_write(const struct ship_mode_info *ship_mode);
+enum ec_error_list battery_sleep_fuel_gauge(void);
 
 /**
- * Battery cut off command via SMBus write word.
+ * Return whether BCIC is enabled or not.
+ *
+ * If a board needs to support units with & without battery config in CBI, it
+ * needs to implement this callback so that BCIC can distinguish the two groups.
+ * This is needed because without this callback, BCIC can't tell battery config
+ * is missing because it's an old unit or because the default config is
+ * applicable.
+ *
+ *   bool board_batt_conf_enabled(void)
+ *   {
+ *       if (BOARD_VERSION > 0)
+ *           return true;
+ *       else
+ *           return false;
+ *   }
  *
- * @param ship_mode		Battery ship mode information
- * @return non-zero if error
+ * @return true if board supports BCIC or false otherwise.
  */
-int cut_off_battery_sb_write(const struct ship_mode_info *ship_mode);
+__override_proto bool board_batt_conf_enabled(void);
 
 #endif /* __CROS_EC_BATTERY_FUEL_GAUGE_H */
diff --git a/include/battery_smart.h b/include/battery_smart.h
index 635ac8558a..920578289d 100644
--- a/include/battery_smart.h
+++ b/include/battery_smart.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,146 +11,188 @@
 #include "common.h"
 
 /* Smart battery and charger I2C address */
-#define BATTERY_ADDR_FLAGS	0x0B
-#define CHARGER_ADDR_FLAGS	0x09
+#define BATTERY_ADDR_FLAGS 0x0B
+#define CHARGER_ADDR_FLAGS 0x09
 
 /* Charger functions */
-#define SB_CHARGER_SPEC_INFO            0x11
-#define SB_CHARGE_MODE                  0x12
-#define SB_CHARGER_STATUS               0x13
-#define SB_CHARGING_CURRENT             0x14
-#define SB_CHARGING_VOLTAGE             0x15
-#define SB_ALARM_WARNING                0x16
+#define SB_CHARGER_SPEC_INFO 0x11
+#define SB_CHARGE_MODE 0x12
+#define SB_CHARGER_STATUS 0x13
+#define SB_CHARGING_CURRENT 0x14
+#define SB_CHARGING_VOLTAGE 0x15
+#define SB_ALARM_WARNING 0x16
 
 /* Battery functions */
-#define SB_MANUFACTURER_ACCESS          0x00
-#define SB_REMAINING_CAPACITY_ALARM     0x01
-#define SB_REMAINING_TIME_ALARM         0x02
-#define SB_BATTERY_MODE                 0x03
-#define SB_AT_RATE                      0x04
-#define SB_AT_RATE_TIME_TO_FULL         0x05
-#define SB_AT_RATE_TIME_TO_EMPTY        0x06
-#define SB_AT_RATE_OK                   0x07
-#define SB_TEMPERATURE                  0x08
-#define SB_VOLTAGE                      0x09
-#define SB_CURRENT                      0x0a
-#define SB_AVERAGE_CURRENT              0x0b
-#define SB_MAX_ERROR                    0x0c
-#define SB_RELATIVE_STATE_OF_CHARGE     0x0d
-#define SB_ABSOLUTE_STATE_OF_CHARGE     0x0e
-#define SB_REMAINING_CAPACITY           0x0f
-#define SB_FULL_CHARGE_CAPACITY         0x10
-#define SB_RUN_TIME_TO_EMPTY            0x11
-#define SB_AVERAGE_TIME_TO_EMPTY        0x12
-#define SB_AVERAGE_TIME_TO_FULL         0x13
-#define SB_CHARGING_CURRENT             0x14
-#define SB_CHARGING_VOLTAGE             0x15
-#define SB_BATTERY_STATUS               0x16
-#define SB_CYCLE_COUNT                  0x17
-#define SB_DESIGN_CAPACITY              0x18
-#define SB_DESIGN_VOLTAGE               0x19
-#define SB_SPECIFICATION_INFO           0x1a
-#define SB_MANUFACTURE_DATE             0x1b
-#define SB_SERIAL_NUMBER                0x1c
-#define SB_MANUFACTURER_NAME            0x20
-#define SB_DEVICE_NAME                  0x21
-#define SB_DEVICE_CHEMISTRY             0x22
-#define SB_MANUFACTURER_DATA            0x23
+#define SB_MANUFACTURER_ACCESS 0x00
+#define SB_REMAINING_CAPACITY_ALARM 0x01
+#define SB_REMAINING_TIME_ALARM 0x02
+#define SB_BATTERY_MODE 0x03
+#define SB_AT_RATE 0x04
+#define SB_AT_RATE_TIME_TO_FULL 0x05
+#define SB_AT_RATE_TIME_TO_EMPTY 0x06
+#define SB_AT_RATE_OK 0x07
+#define SB_TEMPERATURE 0x08
+#define SB_VOLTAGE 0x09
+#define SB_CURRENT 0x0a
+#define SB_AVERAGE_CURRENT 0x0b
+#define SB_MAX_ERROR 0x0c
+#define SB_RELATIVE_STATE_OF_CHARGE 0x0d
+#define SB_ABSOLUTE_STATE_OF_CHARGE 0x0e
+#define SB_REMAINING_CAPACITY 0x0f
+#define SB_FULL_CHARGE_CAPACITY 0x10
+#define SB_RUN_TIME_TO_EMPTY 0x11
+#define SB_AVERAGE_TIME_TO_EMPTY 0x12
+#define SB_AVERAGE_TIME_TO_FULL 0x13
+#define SB_CHARGING_CURRENT 0x14
+#define SB_CHARGING_VOLTAGE 0x15
+#define SB_BATTERY_STATUS 0x16
+#define SB_CYCLE_COUNT 0x17
+#define SB_DESIGN_CAPACITY 0x18
+#define SB_DESIGN_VOLTAGE 0x19
+#define SB_SPECIFICATION_INFO 0x1a
+#define SB_MANUFACTURE_DATE 0x1b
+#define SB_SERIAL_NUMBER 0x1c
+#define SB_MANUFACTURER_NAME 0x20
+#define SB_DEVICE_NAME 0x21
+#define SB_DEVICE_CHEMISTRY 0x22
+#define SB_MANUFACTURER_DATA 0x23
+#define SB_OPTIONAL_MFG_FUNC1 0x3C
+#define SB_OPTIONAL_MFG_FUNC2 0x3D
+#define SB_OPTIONAL_MFG_FUNC3 0x3E
+#define SB_OPTIONAL_MFG_FUNC4 0x3F
 /* Extension of smart battery spec, may not be supported on all platforms */
-#define SB_PACK_STATUS                  0x43
-#define SB_ALT_MANUFACTURER_ACCESS      0x44
+#define SB_PACK_STATUS 0x43
+#define SB_ALT_MANUFACTURER_ACCESS 0x44
+#define SB_MANUFACTURE_INFO 0x70
 
 /* Battery mode */
 #define MODE_INTERNAL_CHARGE_CONTROLLER BIT(0)
-#define MODE_PRIMARY_BATTERY_SUPPORT    BIT(1)
-#define MODE_CONDITION_CYCLE            BIT(7)
-#define MODE_CHARGE_CONTROLLER_ENABLED  BIT(8)
-#define MODE_PRIMARY_BATTERY            BIT(9)
-#define MODE_ALARM                      BIT(13)
-#define MODE_CHARGER                    BIT(14)
-#define MODE_CAPACITY                   BIT(15)
+#define MODE_PRIMARY_BATTERY_SUPPORT BIT(1)
+#define MODE_CONDITION_CYCLE BIT(7)
+#define MODE_CHARGE_CONTROLLER_ENABLED BIT(8)
+#define MODE_PRIMARY_BATTERY BIT(9)
+#define MODE_ALARM BIT(13)
+#define MODE_CHARGER BIT(14)
+#define MODE_CAPACITY BIT(15)
 
 /* Battery status */
-#define STATUS_ERR_CODE_MASK            0xf
-#define STATUS_CODE_OK                  0
-#define STATUS_CODE_BUSY                1
-#define STATUS_CODE_RESERVED            2
-#define STATUS_CODE_UNSUPPORTED         3
-#define STATUS_CODE_ACCESS_DENIED       4
-#define STATUS_CODE_OVERUNDERFLOW       5
-#define STATUS_CODE_BADSIZE             6
-#define STATUS_CODE_UNKNOWN_ERROR       7
-#define STATUS_FULLY_DISCHARGED         BIT(4)
-#define STATUS_FULLY_CHARGED            BIT(5)
-#define STATUS_DISCHARGING              BIT(6)
-#define STATUS_INITIALIZED              BIT(7)
-#define STATUS_REMAINING_TIME_ALARM     BIT(8)
+#define STATUS_ERR_CODE_MASK 0xf
+#define STATUS_CODE_OK 0
+#define STATUS_CODE_BUSY 1
+#define STATUS_CODE_RESERVED 2
+#define STATUS_CODE_UNSUPPORTED 3
+#define STATUS_CODE_ACCESS_DENIED 4
+#define STATUS_CODE_OVERUNDERFLOW 5
+#define STATUS_CODE_BADSIZE 6
+#define STATUS_CODE_UNKNOWN_ERROR 7
+#define STATUS_FULLY_DISCHARGED BIT(4)
+#define STATUS_FULLY_CHARGED BIT(5)
+#define STATUS_DISCHARGING BIT(6)
+#define STATUS_INITIALIZED BIT(7)
+#define STATUS_REMAINING_TIME_ALARM BIT(8)
 #define STATUS_REMAINING_CAPACITY_ALARM BIT(9)
 #define STATUS_TERMINATE_DISCHARGE_ALARM BIT(11)
-#define STATUS_OVERTEMP_ALARM           BIT(12)
-#define STATUS_TERMINATE_CHARGE_ALARM   BIT(14)
-#define STATUS_OVERCHARGED_ALARM        BIT(15)
+#define STATUS_OVERTEMP_ALARM BIT(12)
+#define STATUS_TERMINATE_CHARGE_ALARM BIT(14)
+#define STATUS_OVERCHARGED_ALARM BIT(15)
 
 /* Battery Spec Info */
-#define BATTERY_SPEC_VERSION(INFO)      ((INFO >> 4) & 0xF)
+#define BATTERY_SPEC_REVISION_MASK 0x000F
+#define BATTERY_SPEC_REVISION_SHIFT 0
+#define BATTERY_SPEC_VERSION_MASK 0x00F0
+#define BATTERY_SPEC_VERSION_SHIFT 4
+#define BATTERY_SPEC_VSCALE_MASK 0x0F00
+#define BATTERY_SPEC_VSCALE_SHIFT 8
+#define BATTERY_SPEC_IPSCALE_MASK 0xF000
+#define BATTERY_SPEC_IPSCALE_SHIFT 12
+
+#define BATTERY_SPEC_VERSION(INFO) \
+	((INFO & BATTERY_SPEC_VERSION_MASK) >> BATTERY_SPEC_VERSION_SHIFT)
 /* Smart battery version info */
-#define BATTERY_SPEC_VER_1_0            1
-#define BATTERY_SPEC_VER_1_1            2
-#define BATTERY_SPEC_VER_1_1_WITH_PEC   3
+#define BATTERY_SPEC_VER_1_0 1
+#define BATTERY_SPEC_VER_1_1 2
+#define BATTERY_SPEC_VER_1_1_WITH_PEC 3
+/* Smart battery revision info */
+#define BATTERY_SPEC_REVISION_1 1
 
 /* Charger alarm warning */
-#define ALARM_OVER_CHARGED              0x8000
-#define ALARM_TERMINATE_CHARGE          0x4000
-#define ALARM_RESERVED_2000             0x2000
-#define ALARM_OVER_TEMP                 0x1000
-#define ALARM_TERMINATE_DISCHARGE       0x0800
-#define ALARM_RESERVED_0400             0x0400
-#define ALARM_REMAINING_CAPACITY        0x0200
-#define ALARM_REMAINING_TIME            0x0100
-#define ALARM_STATUS_INITIALIZE         0x0080
-#define ALARM_STATUS_DISCHARGING        0x0040
-#define ALARM_STATUS_FULLY_CHARGED      0x0020
-#define ALARM_STATUS_FULLY_DISCHARGED   0x0010
+#define ALARM_OVER_CHARGED 0x8000
+#define ALARM_TERMINATE_CHARGE 0x4000
+#define ALARM_RESERVED_2000 0x2000
+#define ALARM_OVER_TEMP 0x1000
+#define ALARM_TERMINATE_DISCHARGE 0x0800
+#define ALARM_RESERVED_0400 0x0400
+#define ALARM_REMAINING_CAPACITY 0x0200
+#define ALARM_REMAINING_TIME 0x0100
+#define ALARM_STATUS_INITIALIZE 0x0080
+#define ALARM_STATUS_DISCHARGING 0x0040
+#define ALARM_STATUS_FULLY_CHARGED 0x0020
+#define ALARM_STATUS_FULLY_DISCHARGED 0x0010
 /* Charge mode */
-#define CHARGE_FLAG_INHIBIT_CHARGE      BIT(0)
-#define CHARGE_FLAG_ENABLE_POLLING      BIT(1)
-#define CHARGE_FLAG_POR_RESET           BIT(2)
-#define CHARGE_FLAG_RESET_TO_ZERO       BIT(3)
+#define CHARGE_FLAG_INHIBIT_CHARGE BIT(0)
+#define CHARGE_FLAG_ENABLE_POLLING BIT(1)
+#define CHARGE_FLAG_POR_RESET BIT(2)
+#define CHARGE_FLAG_RESET_TO_ZERO BIT(3)
 /* Charger status */
-#define CHARGER_CHARGE_INHIBITED        BIT(0)
-#define CHARGER_POLLING_ENABLED         BIT(1)
-#define CHARGER_VOLTAGE_NOTREG          BIT(2)
-#define CHARGER_CURRENT_NOTREG          BIT(3)
-#define CHARGER_LEVEL_2                 BIT(4)
-#define CHARGER_LEVEL_3                 BIT(5)
-#define CHARGER_CURRENT_OR              BIT(6)
-#define CHARGER_VOLTAGE_OR              BIT(7)
-#define CHARGER_RES_OR                  BIT(8)
-#define CHARGER_RES_COLD                BIT(9)
-#define CHARGER_RES_HOT                 BIT(10)
-#define CHARGER_RES_UR                  BIT(11)
-#define CHARGER_ALARM_INHIBITED         BIT(12)
-#define CHARGER_POWER_FAIL              BIT(13)
-#define CHARGER_BATTERY_PRESENT         BIT(14)
-#define CHARGER_AC_PRESENT              BIT(15)
+#define CHARGER_CHARGE_INHIBITED BIT(0)
+#define CHARGER_POLLING_ENABLED BIT(1)
+#define CHARGER_VOLTAGE_NOTREG BIT(2)
+#define CHARGER_CURRENT_NOTREG BIT(3)
+#define CHARGER_LEVEL_2 BIT(4)
+#define CHARGER_LEVEL_3 BIT(5)
+#define CHARGER_CURRENT_OR BIT(6)
+#define CHARGER_VOLTAGE_OR BIT(7)
+#define CHARGER_RES_OR BIT(8)
+#define CHARGER_RES_COLD BIT(9)
+#define CHARGER_RES_HOT BIT(10)
+#define CHARGER_RES_UR BIT(11)
+#define CHARGER_ALARM_INHIBITED BIT(12)
+#define CHARGER_POWER_FAIL BIT(13)
+#define CHARGER_BATTERY_PRESENT BIT(14)
+#define CHARGER_AC_PRESENT BIT(15)
+#define CHARGER_BYPASS_MODE BIT(16)
 /* Charger specification info */
-#define INFO_CHARGER_SPEC(INFO)         ((INFO) & 0xf)
-#define INFO_SELECTOR_SUPPORT(INFO)     (((INFO) >> 4) & 1)
+#define INFO_CHARGER_SPEC(INFO) ((INFO)&0xf)
+#define INFO_SELECTOR_SUPPORT(INFO) (((INFO) >> 4) & 1)
 
 /* Manufacturer Access parameters */
-#define PARAM_SAFETY_STATUS             0x51
-#define PARAM_OPERATION_STATUS          0x54
+#define PARAM_SAFETY_STATUS 0x51
+#define PARAM_OPERATION_STATUS 0x54
+#define PARAM_FIRMWARE_RUNTIME 0x62
 /* Operation status masks -- 6 byte reply */
 /* reply[3] */
-#define BATTERY_DISCHARGING_DISABLED    0x20
-#define BATTERY_CHARGING_DISABLED       0x40
+#define BATTERY_DISCHARGING_DISABLED 0x20
+#define BATTERY_CHARGING_DISABLED 0x40
+
+/* Battery manufacture date */
+#define MANUFACTURE_DATE_DAY_MASK 0x001F
+#define MANUFACTURE_DATE_DAY_SHIFT 0
+#define MANUFACTURE_DATE_MONTH_MASK 0x01E0
+#define MANUFACTURE_DATE_MONTH_SHIFT 5
+#define MANUFACTURE_DATE_YEAR_MASK 0xFE00
+#define MANUFACTURE_DATE_YEAR_SHIFT 9
+#define MANUFACTURE_DATE_YEAR_OFFSET 1980
+#define MANUFACTURE_RUNTIME_SIZE 4
 
 /* Read from battery */
 int sb_read(int cmd, int *param);
 
-/* Read sequence from battery */
+/**
+ * Read null-terminated string from battery
+ * @param offset	Battery register to read from
+ * @param data		Buffer to hold the string
+ * @param len		Length of data buffer
+ */
 int sb_read_string(int offset, uint8_t *data, int len);
 
+/**
+ * Read sized block of data from battery
+ * @param offset	Battery register to read from
+ * @param data		Buffer to hold read data
+ * @param len		Length of data buffer
+ */
+int sb_read_sized_block(int offset, uint8_t *data, int len);
+
 /* Write to battery */
 int sb_write(int cmd, int param);
 
@@ -167,5 +209,7 @@ int sb_write_block(int reg, const uint8_t *val, int len);
 /* Read manufactures access data from the battery */
 int sb_read_mfgacc(int cmd, int block, uint8_t *data, int len);
 
-#endif /* __CROS_EC_BATTERY_SMART_H */
+/* Read manufactures access data from the battery */
+int sb_read_mfgacc_block(int cmd, int block, uint8_t *data, int len);
 
+#endif /* __CROS_EC_BATTERY_SMART_H */
diff --git a/include/benchmark.h b/include/benchmark.h
new file mode 100644
index 0000000000..a8acc5549c
--- /dev/null
+++ b/include/benchmark.h
@@ -0,0 +1,170 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Benchmark utility functions.
+ */
+
+#ifndef __CROS_EC_BENCHMARK_H
+#define __CROS_EC_BENCHMARK_H
+
+#include <stdint.h>
+
+#include <array>
+#include <functional>
+#include <optional>
+#include <string_view>
+
+extern "C" {
+#include "clock.h"
+#include "console.h"
+#include "timer.h"
+#include "util.h"
+#include "watchdog.h"
+}
+
+/* Benchmark execution options */
+struct BenchmarkOptions {
+	/* Number of test iterations */
+	int num_iterations = 10;
+	/* Whether to reload the watchdog between executions of f() */
+	bool reload_watchdog = true;
+	/* Whether to enable fast CPU clock during the test (when supported) */
+	bool use_fast_cpu = true;
+};
+
+/* The result of a benchmark run with various timing metrics.
+ * All time measurements are in micro seconds, except the average that
+ * is captured in nanoseconds for increased resolution.
+ */
+struct BenchmarkResult {
+	/* Name of the test, used when printing results */
+	std::string_view name;
+	/* Total elapsed time (us) for all iterations */
+	uint32_t elapsed_time;
+	/* Average elapsed time (us) for a single iteration */
+	uint32_t average_time;
+	/* Minimum elapsed time (us) for a single iteration */
+	uint32_t min_time;
+	/* Maximum elapsed time (us) for a single iteration */
+	uint32_t max_time;
+
+	/* Compare two BenchmarkResult structs and print delta between baseline
+	 * and other. */
+	static void compare(const BenchmarkResult &baseline,
+			    const BenchmarkResult &other)
+	{
+		auto print_comparison = [](std::string_view title,
+					   uint32_t baseline, uint32_t other) {
+			ccprintf(" %7s (us): %9u %9u %+9d (%+d%%)\n",
+				 title.data(), baseline, other,
+				 other - baseline,
+				 100 *
+					 (static_cast<int32_t>(other) -
+					  static_cast<int32_t>(baseline)) /
+					 static_cast<int32_t>(baseline));
+		};
+		ccprintf("-----------------------------------------------\n");
+		ccprintf("Compare: %s vs %s\n", baseline.name.data(),
+			 other.name.data());
+		ccprintf("-----------------------------------------------\n");
+		print_comparison("Elapsed", baseline.elapsed_time,
+				 other.elapsed_time);
+		print_comparison("Min", baseline.min_time, other.min_time);
+		print_comparison("Max", baseline.max_time, other.max_time);
+		print_comparison("Avg", baseline.average_time,
+				 other.average_time);
+		cflush();
+	}
+};
+
+/* Benchmark main class responsible for running the experiments and
+ * collecting/printing the results.
+ * Note that the implementation intentionally avoid dynamic memory allocations
+ * and stores up to MAX_NUM_RESULTS results into a std::array.
+ */
+template <int MAX_NUM_RESULTS = 5> class Benchmark {
+    public:
+	explicit Benchmark(const BenchmarkOptions &options = BenchmarkOptions())
+		: options_(options){};
+
+	/* Run benchmark of the function f().
+	 *
+	 * TODO(b/253099367): replace std::optional with StatusOr
+	 */
+	std::optional<BenchmarkResult>
+	run(const std::string_view benchmark_name, std::function<void()> f)
+	{
+		if (benchmark_name.empty()) {
+			ccprintf("%s: benchmark_name cannot be empty\n",
+				 __func__);
+			return {};
+		}
+		if (num_results_ >= MAX_NUM_RESULTS) {
+			ccprintf("%s: cannot store new BenchmarkResults\n",
+				 __func__);
+			return {};
+		}
+
+		BenchmarkResult &result = results_[num_results_++];
+		result.name = benchmark_name;
+		result.elapsed_time = 0;
+
+		if (options_.use_fast_cpu)
+			clock_enable_module(MODULE_FAST_CPU, 1);
+
+		bool valid_min_max = false;
+		for (int i = 0; i < options_.num_iterations; ++i) {
+			timestamp_t start_time = get_time();
+			f();
+			uint32_t iteration_time = time_since32(start_time);
+
+			if (options_.reload_watchdog)
+				watchdog_reload();
+
+			if (valid_min_max) {
+				result.max_time =
+					MAX(result.max_time, iteration_time);
+				result.min_time =
+					MIN(result.min_time, iteration_time);
+			} else {
+				result.max_time = iteration_time;
+				result.min_time = iteration_time;
+				valid_min_max = true;
+			}
+			result.elapsed_time += iteration_time;
+		}
+
+		if (options_.use_fast_cpu)
+			clock_enable_module(MODULE_FAST_CPU, 0);
+
+		result.average_time =
+			(result.elapsed_time) / options_.num_iterations;
+
+		return result;
+	}
+
+	void print_results() const
+	{
+		for (int i = 0; i < num_results_; ++i) {
+			auto &result = results_[i];
+			ccprintf("------------------------------\n");
+			ccprintf("Benchmark: %s\n", result.name.data());
+			ccprintf("------------------------------\n");
+			ccprintf(" Iterations:   %u\n",
+				 options_.num_iterations);
+			ccprintf(" Elapsed (us): %u\n", result.elapsed_time);
+			ccprintf(" Min (us):     %u\n", result.min_time);
+			ccprintf(" Max (us):     %u\n", result.max_time);
+			ccprintf(" Avg (us):     %u\n", result.average_time);
+			cflush();
+		}
+	}
+
+    private:
+	const BenchmarkOptions options_;
+	std::array<BenchmarkResult, MAX_NUM_RESULTS> results_;
+	int num_results_ = 0;
+};
+
+#endif /* __CROS_EC_BENCHMARK_H */
diff --git a/include/bluetooth_le.h b/include/bluetooth_le.h
index 286653dda6..e65b3d448b 100644
--- a/include/bluetooth_le.h
+++ b/include/bluetooth_le.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,69 +23,67 @@
 #include "common.h"
 #include "util.h"
 
-#define BLUETOOTH_ADDR_OCTETS                   6
+#define BLUETOOTH_ADDR_OCTETS 6
 
 /*
  * GAP assigned numbers
  * https://www.bluetooth.org/en-us/specification/
  * assigned-numbers/generic-access-profile
  */
-#define GAP_FLAGS                               0x01
-#define GAP_INCOMP_16_BIT_UUID                  0x02
-#define GAP_COMP_16_BIT_UUID                    0x03
-#define GAP_INCOMP_32_BIT_UUID                  0x04
-#define GAP_COMP_32_BIT_UUID                    0x05
-#define GAP_INCOMP_128_BIT_UUID                 0x06
-#define GAP_COMP_128_BIT_UUID                   0x07
-#define GAP_SHORT_NAME                          0x08
-#define GAP_COMPLETE_NAME                       0x09
-#define GAP_TX_POWER_LEVEL                      0x0A
-#define GAP_CLASS_OF_DEVICE                     0x0D
-#define GAP_SIMPLE_PAIRING_HASH                 0x0E
-#define GAP_SIMPLE_PAIRING_HASH_192             0x0E
-#define GAP_SIMPLE_PAIRING_RAND                 0x0F
-#define GAP_SIMPLE_PAIRING_RAND_192             0x0F
-#define GAP_DEVICE_ID                           0x10
-#define GAP_SECURITY_MANAGER_TK                 0x10
-#define GAP_SECURITY_MANAGER_OOB_FLAGS          0x11
-#define GAP_SLAVE_CONNECTION_INTERVAL_RANGE     0x12
-#define GAP_SERVICE_SOLICITATION_UUID_16        0x14
-#define GAP_SERVICE_SOLICITATION_UUID_32        0x1F
-#define GAP_SERVICE_SOLICITATION_UUID_128       0x15
-#define GAP_SERVICE_DATA                        0x16
-#define GAP_SERVICE_DATA_UUID_16                0x16
-#define GAP_SERVICE_DATA_UUID_32                0x20
-#define GAP_SERVICE_DATA_UUID_128               0x21
-#define GAP_LE_SECURE_CONNECTIONS_CONFIRMATION  0x22
-#define GAP_LE_SECURE_CONNECTIONS_RAND          0x23
-#define GAP_PUBLIC_TARGET_ADDRESS               0x17
-#define GAP_RANDOM_TARGET_ADDRESS               0x18
-#define GAP_APPEARANCE                          0x19
-#define GAP_ADVERTISING_INTERVAL                0x1A
-#define GAP_LE_BLUETOOTH_DEVICE_ADDRESS         0x1B
-#define GAP_LE_ROLE                             0x1C
-#define GAP_SIMPLE_PAIRING_HASH_256             0x1D
-#define GAP_SIMPLE_PAIRING_RAND_256             0x1E
-#define GAP_3D_INFORMATION_DATA                 0x3D
-#define GAP_MANUFACTURER_SPECIFIC_DATA          0xFF
-
+#define GAP_FLAGS 0x01
+#define GAP_INCOMP_16_BIT_UUID 0x02
+#define GAP_COMP_16_BIT_UUID 0x03
+#define GAP_INCOMP_32_BIT_UUID 0x04
+#define GAP_COMP_32_BIT_UUID 0x05
+#define GAP_INCOMP_128_BIT_UUID 0x06
+#define GAP_COMP_128_BIT_UUID 0x07
+#define GAP_SHORT_NAME 0x08
+#define GAP_COMPLETE_NAME 0x09
+#define GAP_TX_POWER_LEVEL 0x0A
+#define GAP_CLASS_OF_DEVICE 0x0D
+#define GAP_SIMPLE_PAIRING_HASH 0x0E
+#define GAP_SIMPLE_PAIRING_HASH_192 0x0E
+#define GAP_SIMPLE_PAIRING_RAND 0x0F
+#define GAP_SIMPLE_PAIRING_RAND_192 0x0F
+#define GAP_DEVICE_ID 0x10
+#define GAP_SECURITY_MANAGER_TK 0x10
+#define GAP_SECURITY_MANAGER_OOB_FLAGS 0x11
+#define GAP_SLAVE_CONNECTION_INTERVAL_RANGE 0x12
+#define GAP_SERVICE_SOLICITATION_UUID_16 0x14
+#define GAP_SERVICE_SOLICITATION_UUID_32 0x1F
+#define GAP_SERVICE_SOLICITATION_UUID_128 0x15
+#define GAP_SERVICE_DATA 0x16
+#define GAP_SERVICE_DATA_UUID_16 0x16
+#define GAP_SERVICE_DATA_UUID_32 0x20
+#define GAP_SERVICE_DATA_UUID_128 0x21
+#define GAP_LE_SECURE_CONNECTIONS_CONFIRMATION 0x22
+#define GAP_LE_SECURE_CONNECTIONS_RAND 0x23
+#define GAP_PUBLIC_TARGET_ADDRESS 0x17
+#define GAP_RANDOM_TARGET_ADDRESS 0x18
+#define GAP_APPEARANCE 0x19
+#define GAP_ADVERTISING_INTERVAL 0x1A
+#define GAP_LE_BLUETOOTH_DEVICE_ADDRESS 0x1B
+#define GAP_LE_ROLE 0x1C
+#define GAP_SIMPLE_PAIRING_HASH_256 0x1D
+#define GAP_SIMPLE_PAIRING_RAND_256 0x1E
+#define GAP_3D_INFORMATION_DATA 0x3D
+#define GAP_MANUFACTURER_SPECIFIC_DATA 0xFF
 
 /* org.bluetooth.characteristic.gap.appearance.xml */
-#define GAP_APPEARANCE_HID_KEYBOARD             961
+#define GAP_APPEARANCE_HID_KEYBOARD 961
 
 /* org.bluetooth.service.human_interface_device.xml */
-#define GATT_SERVICE_HID_UUID                   0x1812
+#define GATT_SERVICE_HID_UUID 0x1812
 
 /* Bluetooth Core Supplement v5 */
 
 /* Bluetooth Core Supplement v5 1.3 */
-#define GAP_FLAGS_LE_LIM_DISC   0x01
-#define GAP_FLAGS_LE_GEN_DISC   0x02
-#define GAP_FLAGS_LE_NO_BR_EDR  0x04
+#define GAP_FLAGS_LE_LIM_DISC 0x01
+#define GAP_FLAGS_LE_GEN_DISC 0x02
+#define GAP_FLAGS_LE_NO_BR_EDR 0x04
 
 /* Bluetooth Core Supplement v5 1.3 */
 
-
 /* BLE 4.1 Vol 6 section 2.3 pg 38+ */
 
 /* Advertising PDU Header
@@ -103,49 +101,48 @@ struct ble_adv_header {
 	uint8_t length;
 };
 
-#define BLE_ADV_HEADER_PDU_TYPE_SHIFT    0
-#define BLE_ADV_HEADER_TXADD_SHIFT       6
-#define BLE_ADV_HEADER_RXADD_SHIFT       7
-#define BLE_ADV_HEADER_LENGTH_SHIFT      8
+#define BLE_ADV_HEADER_PDU_TYPE_SHIFT 0
+#define BLE_ADV_HEADER_TXADD_SHIFT 6
+#define BLE_ADV_HEADER_RXADD_SHIFT 7
+#define BLE_ADV_HEADER_LENGTH_SHIFT 8
 
-#define BLE_ADV_HEADER(type, tx, rx, length) \
-		((uint16_t) \
-		((((length) & 0x3f) << BLE_ADV_HEADER_LENGTH_SHIFT) | \
-		 (((rx) & 0x1) << BLE_ADV_HEADER_RXADD_SHIFT) | \
-		 (((tx) & 0x1) << BLE_ADV_HEADER_TXADD_SHIFT) | \
-		 (((type) & 0xf) << BLE_ADV_HEADER_PDU_TYPE_SHIFT)))
+#define BLE_ADV_HEADER(type, tx, rx, length)                           \
+	((uint16_t)((((length)&0x3f) << BLE_ADV_HEADER_LENGTH_SHIFT) | \
+		    (((rx)&0x1) << BLE_ADV_HEADER_RXADD_SHIFT) |       \
+		    (((tx)&0x1) << BLE_ADV_HEADER_TXADD_SHIFT) |       \
+		    (((type)&0xf) << BLE_ADV_HEADER_PDU_TYPE_SHIFT)))
 
-#define BLE_ADV_HEADER_PDU_TYPE_ADV_IND         0
-#define BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND  1
+#define BLE_ADV_HEADER_PDU_TYPE_ADV_IND 0
+#define BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND 1
 #define BLE_ADV_HEADER_PDU_TYPE_ADV_NONCONN_IND 2
-#define BLE_ADV_HEADER_PDU_TYPE_SCAN_REQ        3
-#define BLE_ADV_HEADER_PDU_TYPE_SCAN_RSP        4
-#define BLE_ADV_HEADER_PDU_TYPE_CONNECT_REQ     5
-#define BLE_ADV_HEADER_PDU_TYPE_ADV_SCAN_IND    6
+#define BLE_ADV_HEADER_PDU_TYPE_SCAN_REQ 3
+#define BLE_ADV_HEADER_PDU_TYPE_SCAN_RSP 4
+#define BLE_ADV_HEADER_PDU_TYPE_CONNECT_REQ 5
+#define BLE_ADV_HEADER_PDU_TYPE_ADV_SCAN_IND 6
 
-#define BLE_ADV_HEADER_PUBLIC_ADDR    0
-#define BLE_ADV_HEADER_RANDOM_ADDR    1
+#define BLE_ADV_HEADER_PUBLIC_ADDR 0
+#define BLE_ADV_HEADER_RANDOM_ADDR 1
 
 /* BLE 4.1 Vol 3 Part C 10.8 */
-#define BLE_RANDOM_ADDR_MSBS_PRIVATE             0x00
-#define BLE_RANDOM_ADDR_MSBS_RESOLVABLE_PRIVATE  0x40
-#define BLE_RANDOM_ADDR_MSBS_RFU                 0x80
-#define BLE_RANDOM_ADDR_MSBS_STATIC              0xC0
+#define BLE_RANDOM_ADDR_MSBS_PRIVATE 0x00
+#define BLE_RANDOM_ADDR_MSBS_RESOLVABLE_PRIVATE 0x40
+#define BLE_RANDOM_ADDR_MSBS_RFU 0x80
+#define BLE_RANDOM_ADDR_MSBS_STATIC 0xC0
 
 #define BLE_ADV_ACCESS_ADDRESS 0x8E89BED6
 #define BLE_ADV_CRCINIT 0x555555
 
-#define BLE_MAX_ADV_PAYLOAD_OCTETS       37
+#define BLE_MAX_ADV_PAYLOAD_OCTETS 37
 
 /* LL SCA Values.  They are shifted left 5 bits for Hop values */
-#define BLE_LL_SCA_251_PPM_TO_500_PPM    (0 << 5)
-#define BLE_LL_SCA_151_PPM_TO_250_PPM    BIT(5)
-#define BLE_LL_SCA_101_PPM_TO_150_PPM    (2 << 5)
-#define BLE_LL_SCA_076_PPM_TO_100_PPM    (3 << 5)
-#define BLE_LL_SCA_051_PPM_TO_075_PPM    (4 << 5)
-#define BLE_LL_SCA_031_PPM_TO_050_PPM    (5 << 5)
-#define BLE_LL_SCA_021_PPM_TO_030_PPM    (6 << 5)
-#define BLE_LL_SCA_000_PPM_TO_020_PPM    (7 << 5)
+#define BLE_LL_SCA_251_PPM_TO_500_PPM (0 << 5)
+#define BLE_LL_SCA_151_PPM_TO_250_PPM BIT(5)
+#define BLE_LL_SCA_101_PPM_TO_150_PPM (2 << 5)
+#define BLE_LL_SCA_076_PPM_TO_100_PPM (3 << 5)
+#define BLE_LL_SCA_051_PPM_TO_075_PPM (4 << 5)
+#define BLE_LL_SCA_031_PPM_TO_050_PPM (5 << 5)
+#define BLE_LL_SCA_021_PPM_TO_030_PPM (6 << 5)
+#define BLE_LL_SCA_000_PPM_TO_020_PPM (7 << 5)
 
 /* BLE 4.1 Vol 6 section 2.4 pg 45 */
 
@@ -169,26 +166,25 @@ struct ble_data_header {
 	uint8_t length;
 };
 
-#define BLE_DATA_HEADER_LLID_SHIFT       0
-#define BLE_DATA_HEADER_NESN_SHIFT       2
-#define BLE_DATA_HEADER_SN_SHIFT         3
-#define BLE_DATA_HEADER_MD_SHIFT         4
-#define BLE_DATA_HEADER_LENGTH_SHIFT     8
+#define BLE_DATA_HEADER_LLID_SHIFT 0
+#define BLE_DATA_HEADER_NESN_SHIFT 2
+#define BLE_DATA_HEADER_SN_SHIFT 3
+#define BLE_DATA_HEADER_MD_SHIFT 4
+#define BLE_DATA_HEADER_LENGTH_SHIFT 8
 
 #define BLE_DATA_HEADER_LLID_DATANOSTART 1
-#define BLE_DATA_HEADER_LLID_DATASTART   2
-#define BLE_DATA_HEADER_LLID_CONTROL     3
+#define BLE_DATA_HEADER_LLID_DATASTART 2
+#define BLE_DATA_HEADER_LLID_CONTROL 3
 
-#define BLE_DATA_HEADER(llid, nesn, sn, md, length) \
-		((uint16_t) \
-		((((length) & 0x1f) << BLE_DATA_HEADER_LENGTH_SHIFT) | \
-		 (((MD) & 0x1) << BLE_DATA_HEADER_MD_SHIFT) | \
-		 (((SN) & 0x1) << BLE_DATA_HEADER_SN_SHIFT) | \
-		 (((NESN) & 0x1) << BLE_DATA_HEADER_NESN_SHIFT) | \
-		 (((llid) & 0x3) << BLE_DATA_HEADER_LLID_SHIFT)))
+#define BLE_DATA_HEADER(llid, nesn, sn, md, length)                     \
+	((uint16_t)((((length)&0x1f) << BLE_DATA_HEADER_LENGTH_SHIFT) | \
+		    (((MD)&0x1) << BLE_DATA_HEADER_MD_SHIFT) |          \
+		    (((SN)&0x1) << BLE_DATA_HEADER_SN_SHIFT) |          \
+		    (((NESN)&0x1) << BLE_DATA_HEADER_NESN_SHIFT) |      \
+		    (((llid)&0x3) << BLE_DATA_HEADER_LLID_SHIFT)))
 
-#define BLE_MAX_DATA_PAYLOAD_OCTETS      31
-#define BLE_MAX_PAYLOAD_OCTETS           BLE_MAX_ADV_PAYLOAD_OCTETS
+#define BLE_MAX_DATA_PAYLOAD_OCTETS 31
+#define BLE_MAX_PAYLOAD_OCTETS BLE_MAX_ADV_PAYLOAD_OCTETS
 
 union ble_header {
 	struct ble_adv_header adv;
@@ -210,34 +206,34 @@ struct ble_packet {
 };
 
 /* LL Control PDU Opcodes BLE 4.1 Vol 6 2.4.2 */
-#define BLE_LL_CONNECTION_UPDATE_REQ     0x00
-#define BLE_LL_CHANNEL_MAP_REQ           0x01
-#define BLE_LL_TERMINATE_IND             0x02
-#define BLE_LL_ENC_REQ                   0x03
-#define BLE_LL_ENC_RSP                   0x04
-#define BLE_LL_START_ENC_REQ             0x05
-#define BLE_LL_START_ENC_RSP             0x06
-#define BLE_LL_UNKNOWN_RSP               0x07
-#define BLE_LL_FEATURE_REQ               0x08
-#define BLE_LL_FEATURE_RSP               0x09
-#define BLE_LL_PAUSE_ENC_REQ             0x0A
-#define BLE_LL_PAUSE_ENC_RSP             0x0B
-#define BLE_LL_VERSION_IND               0x0C
-#define BLE_LL_REJECT_IND                0x0D
-#define BLE_LL_SLAVE_FEATURE_REQ         0x0E
-#define BLE_LL_CONNECTION_PARAM_REQ      0x0F
-#define BLE_LL_CONNECTION_PARAM_RSP      0x10
-#define BLE_LL_REJECT_IND_EXT            0x11
-#define BLE_LL_PING_REQ                  0x12
-#define BLE_LL_PING_RSP                  0x13
-#define BLE_LL_RFU                       0x14
+#define BLE_LL_CONNECTION_UPDATE_REQ 0x00
+#define BLE_LL_CHANNEL_MAP_REQ 0x01
+#define BLE_LL_TERMINATE_IND 0x02
+#define BLE_LL_ENC_REQ 0x03
+#define BLE_LL_ENC_RSP 0x04
+#define BLE_LL_START_ENC_REQ 0x05
+#define BLE_LL_START_ENC_RSP 0x06
+#define BLE_LL_UNKNOWN_RSP 0x07
+#define BLE_LL_FEATURE_REQ 0x08
+#define BLE_LL_FEATURE_RSP 0x09
+#define BLE_LL_PAUSE_ENC_REQ 0x0A
+#define BLE_LL_PAUSE_ENC_RSP 0x0B
+#define BLE_LL_VERSION_IND 0x0C
+#define BLE_LL_REJECT_IND 0x0D
+#define BLE_LL_SLAVE_FEATURE_REQ 0x0E
+#define BLE_LL_CONNECTION_PARAM_REQ 0x0F
+#define BLE_LL_CONNECTION_PARAM_RSP 0x10
+#define BLE_LL_REJECT_IND_EXT 0x11
+#define BLE_LL_PING_REQ 0x12
+#define BLE_LL_PING_RSP 0x13
+#define BLE_LL_RFU 0x14
 
 /* BLE 4.1 Vol 6 4.6 Table 4.3 */
-#define BLE_LL_FEATURE_LE_ENCRYPTION     0x00
-#define BLE_LL_FEATURE_CONN_PARAMS_REQ   0x01
-#define BLE_LL_FEATURE_EXT_REJ_IND       0x02
-#define BLE_LL_FEATURE_SLAVE_FEAT_EXCHG  0x03
-#define BLE_LL_FEATURE_LE_PING           0x04
+#define BLE_LL_FEATURE_LE_ENCRYPTION 0x00
+#define BLE_LL_FEATURE_CONN_PARAMS_REQ 0x01
+#define BLE_LL_FEATURE_EXT_REJ_IND 0x02
+#define BLE_LL_FEATURE_SLAVE_FEAT_EXCHG 0x03
+#define BLE_LL_FEATURE_LE_PING 0x04
 
 struct ble_ll_connection_update_req {
 	uint8_t win_size;
@@ -285,8 +281,8 @@ struct ble_ll_feature_rsp {
 
 /* ble_ll_pause_enc_rsp has no CtrData field */
 
-#define BLE_LL_VERS_NR_4_0     6
-#define BLE_LL_VERS_NR_4_1     7
+#define BLE_LL_VERS_NR_4_0 6
+#define BLE_LL_VERS_NR_4_1 7
 
 struct ble_ll_version_ind {
 	uint8_t vers_nr; /* Version Number */
@@ -348,7 +344,7 @@ int chan2freq(int channel);
 
 /* BLE 4.1 Vol 6 2.3.3.1 */
 void fill_remapping_table(struct remapping_table *rt, uint8_t map[5],
-	int hop_increment);
+			  int hop_increment);
 
 void ble_tx(struct ble_pdu *pdu);
 
@@ -376,7 +372,7 @@ uint8_t *pack_adv_int(uint8_t *dest, int length, int type, int data);
 uint8_t *pack_adv_addr(uint8_t *dest, uint64_t addr);
 
 const uint8_t *unpack_adv(const uint8_t *src, int *length, int *type,
-		    const uint8_t **data);
+			  const uint8_t **data);
 
 void dump_ble_addr(uint8_t *mem, char *name);
 
diff --git a/include/bluetooth_le_ll.h b/include/bluetooth_le_ll.h
index 8e46f1dc22..ec2bb7f7e7 100644
--- a/include/bluetooth_le_ll.h
+++ b/include/bluetooth_le_ll.h
@@ -1,10 +1,10 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include "common.h"
 #include "btle_hci_int.h"
+#include "common.h"
 
 enum ll_state_t {
 	UNINITIALIZED,
@@ -17,33 +17,30 @@ enum ll_state_t {
 	TEST_TX,
 };
 
-#define LL_ADV_INTERVAL_UNIT_US       625
-#define LL_ADV_TIMEOUT_UNIT_US        1000000
+#define LL_ADV_INTERVAL_UNIT_US 625
+#define LL_ADV_TIMEOUT_UNIT_US 1000000
 
-#define LL_ADV_DIRECT_INTERVAL_US     3750    /* 3.75 ms */
-#define LL_ADV_DIRECT_TIMEOUT_US      1280000 /* 1.28 s */
+#define LL_ADV_DIRECT_INTERVAL_US 3750 /* 3.75 ms */
+#define LL_ADV_DIRECT_TIMEOUT_US 1280000 /* 1.28 s */
 
-#define LL_MAX_DATA_PACKET_LENGTH     27
-#define LL_MAX_DATA_PACKETS           4
+#define LL_MAX_DATA_PACKET_LENGTH 27
+#define LL_MAX_DATA_PACKETS 4
 
 /* BTLE Spec 4.0: Vol 6, Part B, Section 4.5.3 */
-#define TRANSMIT_WINDOW_OFFSET_CONSTANT	1250
+#define TRANSMIT_WINDOW_OFFSET_CONSTANT 1250
 
-#define LL_MAX_BUFFER_SIZE  (LL_MAX_DATA_PACKET_LENGTH * LL_MAX_DATA_PACKETS)
+#define LL_MAX_BUFFER_SIZE (LL_MAX_DATA_PACKET_LENGTH * LL_MAX_DATA_PACKETS)
 
-#define LL_SUPPORTED_FEATURES (HCI_LE_FTR_ENCRYPTION | \
-	HCI_LE_FTR_CONNECTION_PARAMETERS_REQUEST | \
-	HCI_LE_FTR_EXTENDED_REJECT_INDICATION | \
-	HCI_LE_FTR_SLAVE_INITIATED_FEATURES_EXCHANGE)
+#define LL_SUPPORTED_FEATURES                                               \
+	(HCI_LE_FTR_ENCRYPTION | HCI_LE_FTR_CONNECTION_PARAMETERS_REQUEST | \
+	 HCI_LE_FTR_EXTENDED_REJECT_INDICATION |                            \
+	 HCI_LE_FTR_SLAVE_INITIATED_FEATURES_EXCHANGE)
 
-#define LL_SUPPORTED_STATES (HCI_LE_STATE_NONCON_ADV | \
-	HCI_LE_STATE_SCANNABLE_ADV | \
-	HCI_LE_STATE_CONNECTABLE_ADV | \
-	HCI_LE_STATE_DIRECT_ADV | \
-	HCI_LE_STATE_PASSIVE_SCAN | \
-	HCI_LE_STATE_ACTIVE_SCAN | \
-	HCI_LE_STATE_INITIATE | \
-	HCI_LE_STATE_SLAVE)
+#define LL_SUPPORTED_STATES                                       \
+	(HCI_LE_STATE_NONCON_ADV | HCI_LE_STATE_SCANNABLE_ADV |   \
+	 HCI_LE_STATE_CONNECTABLE_ADV | HCI_LE_STATE_DIRECT_ADV | \
+	 HCI_LE_STATE_PASSIVE_SCAN | HCI_LE_STATE_ACTIVE_SCAN |   \
+	 HCI_LE_STATE_INITIATE | HCI_LE_STATE_SLAVE)
 
 /*
  * 4.6.1 LE Encryption
@@ -60,64 +57,63 @@ enum ll_state_t {
  */
 
 /*Link Layer Control PDU Opcodes */
-#define LL_CONNECTION_UPDATE_REQ  0x00
-#define LL_CHANNEL_MAP_REQ        0x01
-#define LL_TERMINATE_IND          0x02
-#define LL_ENC_REQ                0x03
-#define LL_ENC_RSP                0x04
-#define LL_START_ENC_REQ          0x05
-#define LL_START_ENC_RSP          0x06
-#define LL_UNKNOWN_RSP            0x07
-#define LL_FEATURE_REQ            0x08
-#define LL_FEATURE_RSP            0x09
-#define LL_PAUSE_ENC_REQ          0x0A
-#define LL_PAUSE_ENC_RSP          0x0B
-#define LL_VERSION_IND            0x0C
-#define LL_REJECT_IND             0x0D
-#define LL_SLAVE_FEATURE_REQ      0x0E
-#define LL_CONNECTION_PARAM_REQ   0x0F
-#define LL_CONNECTION_PARAM_RSP   0x10
-#define LL_REJECT_IND_EXT         0x11
-#define LL_PING_REQ               0x12
-#define LL_PING_RSP               0x13
+#define LL_CONNECTION_UPDATE_REQ 0x00
+#define LL_CHANNEL_MAP_REQ 0x01
+#define LL_TERMINATE_IND 0x02
+#define LL_ENC_REQ 0x03
+#define LL_ENC_RSP 0x04
+#define LL_START_ENC_REQ 0x05
+#define LL_START_ENC_RSP 0x06
+#define LL_UNKNOWN_RSP 0x07
+#define LL_FEATURE_REQ 0x08
+#define LL_FEATURE_RSP 0x09
+#define LL_PAUSE_ENC_REQ 0x0A
+#define LL_PAUSE_ENC_RSP 0x0B
+#define LL_VERSION_IND 0x0C
+#define LL_REJECT_IND 0x0D
+#define LL_SLAVE_FEATURE_REQ 0x0E
+#define LL_CONNECTION_PARAM_REQ 0x0F
+#define LL_CONNECTION_PARAM_RSP 0x10
+#define LL_REJECT_IND_EXT 0x11
+#define LL_PING_REQ 0x12
+#define LL_PING_RSP 0x13
 
 /* BLE 4.1 Vol 6 2.3.3.1 Connection information */
-#define CONNECT_REQ_INITA_LEN					6
-#define CONNECT_REQ_ADVA_LEN					6
-#define CONNECT_REQ_ACCESS_ADDR_LEN				4
-#define CONNECT_REQ_CRC_INIT_VAL_LEN				3
-#define CONNECT_REQ_WIN_SIZE_LEN				1
-#define CONNECT_REQ_WIN_OFFSET_LEN				2
-#define CONNECT_REQ_INTERVAL_LEN				2
-#define CONNECT_REQ_LATENCY_LEN					2
-#define CONNECT_REQ_TIMEOUT_LEN					2
-#define CONNECT_REQ_CHANNEL_MAP_LEN				5
-#define CONNECT_REQ_HOP_INCREMENT_AND_SCA_LEN			1
+#define CONNECT_REQ_INITA_LEN 6
+#define CONNECT_REQ_ADVA_LEN 6
+#define CONNECT_REQ_ACCESS_ADDR_LEN 4
+#define CONNECT_REQ_CRC_INIT_VAL_LEN 3
+#define CONNECT_REQ_WIN_SIZE_LEN 1
+#define CONNECT_REQ_WIN_OFFSET_LEN 2
+#define CONNECT_REQ_INTERVAL_LEN 2
+#define CONNECT_REQ_LATENCY_LEN 2
+#define CONNECT_REQ_TIMEOUT_LEN 2
+#define CONNECT_REQ_CHANNEL_MAP_LEN 5
+#define CONNECT_REQ_HOP_INCREMENT_AND_SCA_LEN 1
 struct ble_connection_params {
-	uint8_t		init_a[CONNECT_REQ_INITA_LEN];
-	uint8_t		adv_a[CONNECT_REQ_ADVA_LEN];
-	uint32_t	access_addr;
-	uint32_t	crc_init_val;
-	uint8_t		win_size;
-	uint16_t	win_offset;
-	uint16_t	interval;
-	uint16_t	latency;
-	uint16_t	timeout;
-	uint64_t	channel_map;
-	uint8_t		hop_increment;
-	uint8_t		sleep_clock_accuracy;
-	uint32_t	transmitWindowOffset;
-	uint32_t	transmitWindowSize;
-	uint32_t	connInterval;
-	uint16_t	connSlaveLatency;
-	uint32_t	connSupervisionTimeout;
+	uint8_t init_a[CONNECT_REQ_INITA_LEN];
+	uint8_t adv_a[CONNECT_REQ_ADVA_LEN];
+	uint32_t access_addr;
+	uint32_t crc_init_val;
+	uint8_t win_size;
+	uint16_t win_offset;
+	uint16_t interval;
+	uint16_t latency;
+	uint16_t timeout;
+	uint64_t channel_map;
+	uint8_t hop_increment;
+	uint8_t sleep_clock_accuracy;
+	uint32_t transmitWindowOffset;
+	uint32_t transmitWindowSize;
+	uint32_t connInterval;
+	uint16_t connLatency;
+	uint32_t connSupervisionTimeout;
 };
 
 uint8_t ll_reset(void);
 
 uint8_t ll_set_tx_power(uint8_t *params);
 
-
 /* LE Information */
 uint8_t ll_read_buffer_size(uint8_t *return_params);
 uint8_t ll_read_local_supported_features(uint8_t *return_params);
diff --git a/include/board_config.h b/include/board_config.h
index 5b21be8236..b20f1fe46c 100644
--- a/include/board_config.h
+++ b/include/board_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/include/body_detection.h b/include/body_detection.h
index d3c1865e36..52a2f61e21 100644
--- a/include/body_detection.h
+++ b/include/body_detection.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,16 +6,20 @@
 #ifndef __CROS_EC_BODY_DETECTION_H
 #define __CROS_EC_BODY_DETECTION_H
 
+#include <stdbool.h>
 #include <stdint.h>
 
-enum body_detect_states {
-	BODY_DETECTION_OFF_BODY,
-	BODY_DETECTION_ON_BODY
+struct body_detect_params {
+	int var_noise_factor;
+	int var_threshold;
+	int confidence_delta;
 };
 
+enum body_detect_states { BODY_DETECTION_OFF_BODY, BODY_DETECTION_ON_BODY };
+
 /* get/set the state of body detection */
 enum body_detect_states body_detect_get_state(void);
-void body_detect_change_state(enum body_detect_states state);
+void body_detect_change_state(enum body_detect_states state, bool spoof);
 
 /* Reset the data. This should be called when ODR is changed*/
 void body_detect_reset(void);
@@ -29,5 +33,7 @@ void body_detect_set_enable(int enable);
 /* get enable state of body detection */
 int body_detect_get_enable(void);
 
+void body_detect_set_spoof(int enable);
+bool body_detect_get_spoof(void);
 
 #endif /* __CROS_EC_BODY_DETECTION_H */
diff --git a/include/btle_hci2.h b/include/btle_hci2.h
index 0b30a0dc48..dc59b72277 100644
--- a/include/btle_hci2.h
+++ b/include/btle_hci2.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,42 +14,40 @@ struct hciCmdHdr {
 	uint16_t opcode;
 	uint8_t paramLen;
 } __packed;
-#define CMD_MAKE_OPCODE(ogf, ocf) ((((uint16_t)((ogf) & 0x3f)) << 10) | ((ocf) & 0x03ff))
-#define CMD_GET_OGF(opcode)       (((opcode) >> 10) & 0x3f)
-#define CMD_GET_OCF(opcode)       ((opcode) & 0x03ff)
-
+#define CMD_MAKE_OPCODE(ogf, ocf) \
+	((((uint16_t)((ogf)&0x3f)) << 10) | ((ocf)&0x03ff))
+#define CMD_GET_OGF(opcode) (((opcode) >> 10) & 0x3f)
+#define CMD_GET_OCF(opcode) ((opcode)&0x03ff)
 
 struct hciAclHdr {
 	uint16_t hdr;
 	uint16_t len;
 } __packed;
-#define ACL_HDR_MASK_CONN_ID      0x0FFF
-#define ACL_HDR_MASK_PB           0x3000
-#define ACL_HDR_MASK_BC           0xC000
-#define ACL_HDR_PB_FIRST_NONAUTO  0x0000
-#define ACL_HDR_PB_CONTINUED      0x1000
-#define ACL_HDR_PB_FIRST_AUTO     0x2000
-#define ACL_HDR_PB_COMPLETE       0x3000
+#define ACL_HDR_MASK_CONN_ID 0x0FFF
+#define ACL_HDR_MASK_PB 0x3000
+#define ACL_HDR_MASK_BC 0xC000
+#define ACL_HDR_PB_FIRST_NONAUTO 0x0000
+#define ACL_HDR_PB_CONTINUED 0x1000
+#define ACL_HDR_PB_FIRST_AUTO 0x2000
+#define ACL_HDR_PB_COMPLETE 0x3000
 
 struct hciScoHdr {
 	uint16_t hdr;
 	uint8_t len;
 } __packed;
-#define SCO_HDR_MASK_CONN_ID      0x0FFF
-#define SCO_HDR_MASK_STATUS       0x3000
-#define SCO_STATUS_ALL_OK         0x0000
-#define SCO_STATUS_UNKNOWN        0x1000
-#define SCO_STATUS_NO_DATA        0x2000
-#define SCO_STATUS_SOME_DATA      0x3000
+#define SCO_HDR_MASK_CONN_ID 0x0FFF
+#define SCO_HDR_MASK_STATUS 0x3000
+#define SCO_STATUS_ALL_OK 0x0000
+#define SCO_STATUS_UNKNOWN 0x1000
+#define SCO_STATUS_NO_DATA 0x2000
+#define SCO_STATUS_SOME_DATA 0x3000
 
 struct hciEvtHdr {
 	uint8_t code;
 	uint8_t len;
 } __packed;
 
-
 void hci_cmd(uint8_t *hciCmdbuf);
 void hci_acl_to_host(uint8_t *data, uint16_t hdr, uint16_t len);
 void hci_acl_from_host(uint8_t *hciAclbuf);
 void hci_event(uint8_t event_code, uint8_t len, uint8_t *params);
-
diff --git a/include/btle_hci_int.h b/include/btle_hci_int.h
index ba0b3e6041..ce3fd6ef41 100644
--- a/include/btle_hci_int.h
+++ b/include/btle_hci_int.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,377 +8,479 @@
  * original author.
  */
 
-
 #ifndef _HCI_INT_H_
 #define _HCI_INT_H_
 
 #include "util.h"
-#define HCI_DEV_NAME_LEN        248
-
-#define HCI_INQUIRY_LENGTH_UNIT                                  1280 /* msec */
-#define HCI_INQUIRY_LENGTH_MAX                                   48 /* units */
-
-#define HCI_LAP_Unlimited_Inquiry                                0x9E8B33
-#define HCI_LAP_Limited_Inquiry                                  0x9E8B00
-
-#define HCI_CLOCK_OFST_VALID                                     0x8000
-
-#define HCI_PKT_TYP_NO_2_DH1                                     0x0002 /* BT 2.1+ */
-#define HCI_PKT_TYP_NO_3_DH1                                     0x0004 /* BT 2.1+ */
-#define HCI_PKT_TYP_DM1                                          0x0008 /* BT 1.1+ */
-#define HCI_PKT_TYP_DH1                                          0x0010 /* BT 1.1+ */
-#define HCI_PKT_TYP_NO_2_DH3                                     0x0100 /* BT 2.1+ */
-#define HCI_PKT_TYP_NO_3_DH3                                     0x0200 /* BT 2.1+ */
-#define HCI_PKT_TYP_DM3                                          0x0400 /* BT 1.1+ */
-#define HCI_PKT_TYP_DH3                                          0x0800 /* BT 1.1+ */
-#define HCI_PKT_TYP_NO_2_DH5                                     0x1000 /* BT 2.1+ */
-#define HCI_PKT_TYP_NO_3_DH5                                     0x1000 /* BT 2.1+ */
-#define HCI_PKT_TYP_DM5                                          0x4000 /* BT 1.1+ */
-#define HCI_PKT_TYP_DH5                                          0x8000 /* BT 1.1+ */
-#define HCI_PKT_TYP_DEFAULT                                      0xCC18
-
-#define HCI_PKT_TYP_SCO_HV1                                      0x0001 /* BT 1.1+ */
-#define HCI_PKT_TYP_SCO_HV2                                      0x0002 /* BT 1.1+ */
-#define HCI_PKT_TYP_SCO_HV3                                      0x0004 /* BT 1.1+ */
-#define HCI_PKT_TYP_SCO_EV3                                      0x0008 /* BT 1.2+ */
-#define HCI_PKT_TYP_SCO_EV4                                      0x0010 /* BT 1.2+ */
-#define HCI_PKT_TYP_SCO_EV5                                      0x0020 /* BT 1.2+ */
-#define HCI_PKT_TYP_SCO_NO_2_EV3                                 0x0040 /* BT 2.1+ */
-#define HCI_PKT_TYP_SCO_NO_3_EV3                                 0x0080 /* BT 2.1+ */
-#define HCI_PKT_TYP_SCO_NO_2_EV5                                 0x0100 /* BT 2.1+ */
-#define HCI_PKT_TYP_SCO_NO_3_EV5                                 0x0200 /* BT 2.1+ */
-
-#define HCI_LINK_POLICY_DISABLE_ALL_LM_MODES                     0x0000
-#define HCI_LINK_POLICY_ENABLE_ROLESWITCH                        0x0001
-#define HCI_LINK_POLICY_ENABLE_HOLD_MODE                         0x0002
-#define HCI_LINK_POLICY_ENABLE_SNIFF_MODE                        0x0004
-#define HCI_LINK_POLICY_ENABLE_PARK_MODE                         0x0008
-
-#define HCI_FILTER_TYPE_CLEAR_ALL                                0x00 /* no subtypes, no data */
-#define HCI_FILTER_INQUIRY_RESULT                                0x01 /* below subtypes */
-#define HCI_FILTER_COND_TYPE_RETURN_ALL_DEVS                     0x00 /* no data */
-#define HCI_FILTER_COND_TYPE_SPECIFIC_DEV_CLS                    0x01 /* uint24_t wanted_class, uint24_t wanted_mask (only set bits are compared to wanted_class) */
-#define HCI_FILTER_COND_TYPE_SPECIFIC_ADDR                       0x02 /* uint8_t mac[6] */
-#define HCI_FILTER_CONNECTION_SETUP                              0x02 /* below subtypes */
-#define HCI_FILTER_COND_TYPE_ALLOW_CONNS_FROM_ALL_DEVS           0x00 /* uint8_t auto_accept_type: 1 - no, 2 - yes w/ no roleswitch, 3 - yes w/ roleswitch */
-#define HCI_FILTER_COND_TYPE_ALLOW_CONNS_FROM_SPECIFIC_DEV_CLS   0x01 /* uint24_t wanted_class, uint24_t wanted_mask (only set bits are compared to wanted_class), auto_accept flag same as above */
-#define HCI_FILTER_COND_TYPE_ALLOW_CONNS_FROM_SPECIFIC_ADDR      0x02 /* uint8_t mac[6], auto_accept flag same as above */
-
-#define HCI_SCAN_ENABLE_INQUIRY                                  0x01 /* discoverable */
-#define HCI_SCAN_ENABLE_PAGE                                     0x02 /* connectable */
-
-#define HCI_HOLD_MODE_SUSPEND_PAGE_SCAN                          0x01
-#define HCI_HOLD_MODE_SUSPEND_INQUIRY_SCAN                       0x02
-#define HCI_HOLD_MODE_SUSPEND_PERIODIC_INQUIRIES                 0x04
-
-#define HCI_TO_HOST_FLOW_CTRL_ACL                                0x01
-#define HCI_TO_HOST_FLOW_CTRL_SCO                                0x02
-
-#define HCI_INQ_MODE_STD                                         0 /* normal mode @ BT 1.1+ */
-#define HCI_INQ_MODE_RSSI                                        1 /* with RSSI   @ BT 1.2+ */
-#define HCI_INQ_MODE_EIR                                         2 /* with EIR    @ BT 2.1+ */
-
-#define HCI_SSP_KEY_ENTRY_STARTED                                0
-#define HCI_SSP_KEY_ENTRY_DIGIT_ENTERED                          1
-#define HCI_SSP_KEY_ENTRY_DIGIT_ERASED                           2
-#define HCI_SSP_KEY_ENTRY_CLEARED                                3
-#define HCI_SSP_KEY_ENTRY_COMPLETED                              4
-
-#define HCI_LOCATION_DOMAIN_OPTION_NONE                          0x20 /* ' ' */
-#define HCI_LOCATION_DOMAIN_OPTION_OUTDOORS_ONLY                 0x4F /* 'O' */
-#define HCI_LOCATION_DOMAIN_OPTION_INDOORS_ONLY                  0x49 /* 'I' */
-#define HCI_LOCATION_DOMAIN_OPTION_NON_COUNTRY_ENTITY            0x58 /* 'X' */
-
-#define HCI_PERIOD_TYPE_DOWNLINK                                 0x00
-#define HCI_PERIOD_TYPE_UPLINK                                   0x01
-#define HCI_PERIOD_TYPE_BIDIRECTIONAL                            0x02
-#define HCI_PERIOD_TYPE_GUARD_PERIOD                             0x03
-
-#define HCI_MWS_INTERVAL_TYPE_NO_RX_NO_TX                        0x00
-#define HCI_MWS_INTERVAL_TYPE_TX_ALLOWED                         0x01
-#define HCI_MWS_INTERVAL_TYPE_RX_ALLOWED                         0x02
-#define HCI_MWS_INTERVAL_TYPE_TX_RX_ALLOWED                      0x03
-#define HCI_MWS_INTERVAL_TYPE_FRAME                              0x04 /* type defined by Set External Frame Configuration command */
-
-#define HCI_CONNLESS_FRAG_TYPE_CONT                              0x00 /* continuation fragment */
-#define HCI_CONNLESS_FRAG_TYPE_START                             0x01 /* first fragment */
-#define HCI_CONNLESS_FRAG_TYPE_END                               0x02 /* last fragment */
-#define HCI_CONNLESS_FRAG_TYPE_COMPLETE                          0x03 /* complete fragment - no fragmentation */
-
-#define HCI_CUR_MODE_ACTIVE                                      0x00
-#define HCI_CUR_MODE_HOLD                                        0x01
-#define HCI_CUR_MODE_SNIFF                                       0x02
-#define HCI_CUR_MODE_PARK                                        0x03
-
-#define HCI_SCO_LINK_TYPE_SCO                                    0x00
-#define HCI_SCO_LINK_TYPE_ESCO                                   0x02
-
-#define HCI_SCO_AIR_MODE_MULAW                                   0x00
-#define HCI_SCO_AIR_MODE_ALAW                                    0x01
-#define HCI_SCO_AIR_MODE_CVSD                                    0x02
-#define HCI_SCO_AIR_MODE_TRANSPARENT                             0x03
-
-#define HCI_MCA_500_PPM                                          0x00
-#define HCI_MCA_250_PPM                                          0x01
-#define HCI_MCA_150_PPM                                          0x02
-#define HCI_MCA_100_PPM                                          0x03
-#define HCI_MCA_75_PPM                                           0x04
-#define HCI_MCA_50_PPM                                           0x05
-#define HCI_MCA_30_PPM                                           0x06
-#define HCI_MCA_20_PPM                                           0x07
-
-#define HCI_EDR_LINK_KEY_COMBO                                   0x00
-#define HCI_EDR_LINK_KEY_LOCAL                                   0x01
-#define HCI_EDR_LINK_KEY_REMOTE                                  0x02
-#define HCI_EDR_LINK_KEY_DEBUG                                   0x03
-#define HCI_EDR_LINK_KEY_UNAUTH_COMBO                            0x04
-#define HCI_EDR_LINK_KEY_AUTH_COMBO                              0x05
-#define HCI_EDR_LINK_KEY_CHANGED                                 0x06
-
-#define HCI_VERSION_1_0_B                                         0 /* BT 1.0b */
-#define HCI_VERSION_1_1                                           1 /* BT 1.1  */
-#define HCI_VERSION_1_2                                           2 /* BT 1.2  */
-#define HCI_VERSION_2_0                                           4 /* BT 2.0  */
-#define HCI_VERSION_2_1                                           3 /* BT 2.1  */
-#define HCI_VERSION_3_0                                           4 /* BT 3.0  */
-#define HCI_VERSION_4_0                                           6 /* BT 4.0  */
-#define HCI_VERSION_4_1                                           7 /* BT 4.1  */
-
-#define HCI_LE_STATE_NONCON_ADV                                  0x0000000000000001ULL /* BT 4.0+ */
-#define HCI_LE_STATE_SCANNABLE_ADV                               0x0000000000000002ULL /* BT 4.0+ */
-#define HCI_LE_STATE_CONNECTABLE_ADV                             0x0000000000000004ULL /* BT 4.0+ */
-#define HCI_LE_STATE_DIRECT_ADV                                  0x0000000000000008ULL /* BT 4.0+ */
-#define HCI_LE_STATE_PASSIVE_SCAN                                0x0000000000000010ULL /* BT 4.0+ */
-#define HCI_LE_STATE_ACTIVE_SCAN                                 0x0000000000000020ULL /* BT 4.0+ */
-#define HCI_LE_STATE_INITIATE                                    0x0000000000000040ULL /* BT 4.0+ */
-#define HCI_LE_STATE_SLAVE                                       0x0000000000000080ULL /* BT 4.0+ */
-#define HCI_LE_STATE_NONCON_ADV_w_PASSIVE_SCAN                   0x0000000000000100ULL /* BT 4.0+ */
-#define HCI_LE_STATE_SCANNABLE_ADV_w_PASSIVE_SCAN                0x0000000000000200ULL /* BT 4.0+ */
-#define HCI_LE_STATE_CONNECTABLE_ADV_w_PASSIVE_SCAN              0x0000000000000400ULL /* BT 4.0+ */
-#define HCI_LE_STATE_DIRECT_ADV_w_PASSIVE_SCAN                   0x0000000000000800ULL /* BT 4.0+ */
-#define HCI_LE_STATE_NONCON_ADV_w_ACTIVE_SCAN                    0x0000000000001000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_SCANNABLE_ADV_w_ACTIVE_SCAN                 0x0000000000002000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_CONNECTABLE_ADV_w_ACTIVE_SCAN               0x0000000000004000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_DIRECT_ADV_w_ACTIVE_SCAN                    0x0000000000008000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_NONCON_ADV_w_INITIATING                     0x0000000000010000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_SCANNABLE_ADV_w_INITIATING                  0x0000000000020000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_NONCON_ADV_w_MASTER                         0x0000000000040000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_SCANNABLE_ADV_w_MASTER                      0x0000000000080000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_NONCON_ADV_w_SLAVE                          0x0000000000100000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_SCANNABLE_ADV_w_SLAVE                       0x0000000000200000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_PASSIVE_SCAN_w_INITIATING                   0x0000000000400000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_ACTIVE_SCAN_w_INITIATING                    0x0000000000800000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_PASSIVE_SCAN_w_MASTER                       0x0000000001000000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_ACTIVE_SCAN_w_MASTER                        0x0000000002000000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_PASSIVE_SCAN_w_SLAVE                        0x0000000004000000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_ACTIVE_SCAN_w_SLAVE                         0x0000000008000000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_INTIATING_w_MASTER                          0x0000000010000000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_LOW_DUTY_CYCLE_DIRECT_ADV                   0x0000000020000000ULL /* BT 4.1+ */
-#define HCI_LE_STATE_PASSIVE_SCAN_w_LOW_DUTY_CYCLE_DIRECT_ADV    0x0000000040000000ULL /* BT 4.1+ */
-#define HCI_LE_STATE_ACTIVE_SCAN_w_LOW_DUTY_CYCLE_DIRECT_ADV     0x0000000080000000ULL /* BT 4.1+ */
-#define HCI_LE_STATE_CONNECTABLE_ADV_w_INITIATING                0x0000000100000000ULL /* BT 4.1+ */
-#define HCI_LE_STATE_DIRECT_ADV_w_INITIATING                     0x0000000200000000ULL /* BT 4.1+ */
-#define HCI_LE_STATE_LOW_DUTY_CYCLE_DIRECT_ADV_w_INITIATING      0x0000000400000000ULL /* BT 4.1+ */
-#define HCI_LE_STATE_CONNECTABLE_ADV_w_MASTER                    0x0000000800000000ULL /* BT 4.1+ */
-#define HCI_LE_STATE_DIRECT_ADV_w_MASTER                         0x0000001000000000ULL /* BT 4.1+ */
-#define HCI_LE_STATE_LOW_DUTY_CYCLE_DIRECT_ADV_w_MASTER          0x0000002000000000ULL /* BT 4.1+ */
-#define HCI_LE_STATE_CONNECTABLE_ADV_w_SLAVE                     0x0000004000000000ULL /* BT 4.1+ */
-#define HCI_LE_STATE_DIRECT_ADV_w_SLAVE                          0x0000008000000000ULL /* BT 4.1+ */
-#define HCI_LE_STATE_LOW_DUTY_CYCLE_DIRECT_ADV_w_SLAVE           0x0000010000000000ULL /* BT 4.1+ */
-#define HCI_LE_STATE_INITIATING_w_SLAVE                          0x0000020000000000ULL /* BT 4.1+ */
-
-#define HCI_LMP_FTR_3_SLOT_PACKETS                               0x0000000000000001ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_5_SLOT_PACKETS                               0x0000000000000002ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_ENCRYPTION                                   0x0000000000000004ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_SLOT_OFFSET                                  0x0000000000000008ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_TIMING_ACCURACY                              0x0000000000000010ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_SWITCH                                       0x0000000000000020ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_HOLD_MODE                                    0x0000000000000040ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_SNIFF_MODE                                   0x0000000000000080ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_PARK_MODE                                    0x0000000000000100ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_RSSI                                         0x0000000000000200ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_CHANNEL_QUALITY_DRIVEN_DATA_RATE             0x0000000000000400ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_SCO_LINKS                                    0x0000000000000800ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_HV2_PACKETS                                  0x0000000000001000ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_HV3_PACKETS                                  0x0000000000002000ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_MU_LAW                                       0x0000000000004000ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_A_LAW                                        0x0000000000008000ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_CVSD                                         0x0000000000010000ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_PAGING_SCHEME                                0x0000000000020000ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_POWER_CONTROL                                0x0000000000040000ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_TRANSPARENT_SCO_DATA                         0x0000000000080000ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_FLOW_CONTROL_LAG_B0                          0x0000000000100000ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_FLOW_CONTROL_LAG_B1                          0x0000000000200000ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_FLOW_CONTROL_LAG_B2                          0x0000000000400000ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_BROADCAST_ENCRYPTION                         0x0000000000800000ULL /* BT 1.2+ */
-#define HCI_LMP_FTR_ACL_2MBPS                                    0x0000000002000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_ACL_3MBPS                                    0x0000000004000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_ENHANCED_INQUIRY_SCAN                        0x0000000008000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_INTERLACED_INQUIRY_SCAN                      0x0000000010000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_INTERLACED_PAGE_SCAN                         0x0000000020000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_RSSI_WITH_INQUIRY_RESULTS                    0x0000000040000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_EXTENDED_SCO_LINK                            0x0000000080000000ULL /* BT 2.1+ */ /* EV3 packets */
-#define HCI_LMP_FTR_EV4_PACKETS                                  0x0000000100000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_EV5_PACKETS                                  0x0000000200000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_AFH_CAPABLE_SLAVE                            0x0000000800000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_AFH_CLASSIFICATION_SLAVE                     0x0000001000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_BR_EDR_NOT_SUPPORTED                         0x0000002000000000ULL /* BT 4.0+ */
-#define HCI_LMP_FTR_LE_SUPPORTED_CONTROLLER                      0x0000004000000000ULL /* BT 4.0+ */
-#define HCI_LMP_FTR_3_SLOT_ACL_PACKETS                           0x0000008000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_5_SLOT_ACL_PACKETS                           0x0000010000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_SNIFF_SUBRATING                              0x0000020000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_PAUSE_ENCRYPTION                             0x0000040000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_AFH_CAPABLE_MASTER                           0x0000080000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_AFH_CLASSIFICATION_MASTER                    0x0000100000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_ESCO_2MBPS                                   0x0000200000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_ESCO_3MBPS                                   0x0000400000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_3_SLOT_ESCO                                  0x0000800000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_EXTENDED_INQUIRY_RESPONSE                    0x0001000000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_SSP                                          0x0008000000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_ENCAPSULATED_PDU                             0x0010000000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_ERRONEOUS_DATA_REPORTING                     0x0020000000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_NON_FLUSHABLE_PACKET_BOUNDARY_FLAG           0x0040000000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_LINK_SUPERVISION_TIMEOUT_CHANGED_EVENT       0x0100000000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_INQUIRY_RESPONSE_TX_POWER_LEVEL              0x0200000000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_EXTENDED_FEATURES                            0x8000000000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_ENHANCED_POWER_CONTROL                       0x0400000000000000ULL /* BT 3.0+ */
-#define HCI_LMP_FTR_SIMUL_LE_EDR_CAPABLE_CONTROLLER              0x0002000000000000ULL /* BT 4.0+ */
-
-#define HCI_LMP_EXT_FTR_P1_SSP_HOST_SUPPORT                      0x0000000000000001ULL /* BT 2.1+ */
-#define HCI_LMP_EXT_FTR_P1_LE_HOST_SUPPORT                       0x0000000000000002ULL /* BT 4.0+ */
-#define HCI_LMP_EXT_FTR_P1_SIMUL_LE_EDR_HOST_SUPPORT             0x0000000000000004ULL /* BT 4.0+ */
-#define HCI_LMP_EXT_FTR_P1_SECURE_CONNECTIONS_HOST_SUPPORT       0x0000000000000008ULL /* BT 4.1+ */
-
-#define HCI_LMP_EXT_FTR_P2_CONNLESS_SLAVE_BROADCAST_MASTER       0x0000000000000001ULL /* BT 4.1+ */
-#define HCI_LMP_EXT_FTR_P2_CONNLESS_SLAVE_BROADCAST_SLAVE        0x0000000000000002ULL /* BT 4.1+ */
-#define HCI_LMP_EXT_FTR_P2_SYNCHRONIZATION_TRAIN                 0x0000000000000004ULL /* BT 4.1+ */
-#define HCI_LMP_EXT_FTR_P2_SYNCHRONIZATION_SCAN                  0x0000000000000008ULL /* BT 4.1+ */
-#define HCI_LMP_EXT_FTR_P2_INQUIRY_RESPONSE_NOTIFICATION_EVT     0x0000000000000010ULL /* BT 4.1+ */
-#define HCI_LMP_EXT_FTR_P2_GENERALIZED_INTERLACED_SCAN           0x0000000000000020ULL /* BT 4.1+ */
-#define HCI_LMP_EXT_FTR_P2_COARSE_CLOCK_ADJUSTMENT               0x0000000000000040ULL /* BT 4.1+ */
-#define HCI_LMP_EXT_FTR_P2_SECURE_CONNECTIONS_CAPABLE_CONTROLLER 0x0000000000000100ULL /* BT 4.1+ */
-#define HCI_LMP_EXT_FTR_P2_PING                                  0x0000000000000200ULL /* BT 4.1+ */
-#define HCI_LMP_EXT_FTR_P2_TRAIN_NUDGING                         0x0000000000000800ULL /* BT 4.1+ */
-
-#define HCI_EVENT_INQUIRY_COMPLETE                               0x0000000000000001ULL /* BT 1.1+ */
-#define HCI_EVENT_INQUIRY_RESULT                                 0x0000000000000002ULL /* BT 1.1+ */
-#define HCI_EVENT_CONN_COMPLETE                                  0x0000000000000004ULL /* BT 1.1+ */
-#define HCI_EVENT_CONN_REQUEST                                   0x0000000000000008ULL /* BT 1.1+ */
-#define HCI_EVENT_DISCONNECTION_COMPLETE                         0x0000000000000010ULL /* BT 1.1+ */
-#define HCI_EVENT_AUTH_COMPLETE                                  0x0000000000000020ULL /* BT 1.1+ */
-#define HCI_EVENT_REMOTE_NAME_REQUEST_COMPLETE                   0x0000000000000040ULL /* BT 1.1+ */
-#define HCI_EVENT_ENCR_CHANGE                                    0x0000000000000080ULL /* BT 1.1+ */
-#define HCI_EVENT_CHANGE_CONN_LINK_KEY_COMPLETE                  0x0000000000000100ULL /* BT 1.1+ */
-#define HCI_EVENT_MASTER_LINK_KEY_COMPLETE                       0x0000000000000200ULL /* BT 1.1+ */
-#define HCI_EVENT_READ_REMOTE_SUPPORTED_FEATURES_COMPLETE        0x0000000000000400ULL /* BT 1.1+ */
-#define HCI_EVENT_READ_REMOTE_VERSION_INFO_COMPLETE              0x0000000000000800ULL /* BT 1.1+ */
-#define HCI_EVENT_QOS_SETUP_COMPLETE                             0x0000000000001000ULL /* BT 1.1+ */
-#define HCI_EVENT_HARDWARE_ERROR                                 0x0000000000008000ULL /* BT 1.1+ */
-#define HCI_EVENT_FLUSH_OCCURRED                                 0x0000000000010000ULL /* BT 1.1+ */
-#define HCI_EVENT_ROLE_CHANGE                                    0x0000000000020000ULL /* BT 1.1+ */
-#define HCI_EVENT_MODE_CHANGE                                    0x0000000000080000ULL /* BT 1.1+ */
-#define HCI_EVENT_RETURN_LINK_KEYS                               0x0000000000100000ULL /* BT 1.1+ */
-#define HCI_EVENT_PIN_CODE_REQUEST                               0x0000000000200000ULL /* BT 1.1+ */
-#define HCI_EVENT_LINK_KEY_REQUEST                               0x0000000000400000ULL /* BT 1.1+ */
-#define HCI_EVENT_LINK_KEY_NOTIFICATION                          0x0000000000800000ULL /* BT 1.1+ */
-#define HCI_EVENT_LOOPBACK_COMMAND                               0x0000000001000000ULL /* BT 1.1+ */
-#define HCI_EVENT_DATA_BUFFER_OVERFLOW                           0x0000000002000000ULL /* BT 1.1+ */
-#define HCI_EVENT_MAX_SLOTS_CHANGE                               0x0000000004000000ULL /* BT 1.1+ */
-#define HCI_EVENT_READ_CLOCK_OFFSET_COMPLETE                     0x0000000008000000ULL /* BT 1.1+ */
-#define HCI_EVENT_CONN_PACKET_TYPE_CHANGED                       0x0000000010000000ULL /* BT 1.1+ */
-#define HCI_EVENT_QOS_VIOLATION                                  0x0000000020000000ULL /* BT 1.1+ */
-#define HCI_EVENT_PAGE_SCAN_MODE_CHANGE                          0x0000000040000000ULL /* BT 1.1+, obsolete @ BT1.2+ */
-#define HCI_EVENT_PAGE_SCAN_REPETITION_MODE_CHANGE               0x0000000080000000ULL /* BT 1.1+ */
-#define HCI_EVENT_ALL_BT_1_1                                     0x00000000FFFFFFFFULL /* also the default for BT 1.1 */
-#define HCI_EVENT_FLOW_SPEC_COMPLETE                             0x0000000100000000ULL /* BT 1.2+ */
-#define HCI_EVENT_INQUIRY_RESULT_WITH_RSSI                       0x0000000200000000ULL /* BT 1.2+ */
-#define HCI_EVENT_READ_REMOTE_EXTENDED_FEATURES_COMPLETE         0x0000000400000000ULL /* BT 1.2+ */
-#define HCI_EVENT_SYNC_CONN_COMPLETE                             0x0000080000000000ULL /* BT 1.2+ */
-#define HCI_EVENT_SYNC_CONN_CHANGED                              0x0000100000000000ULL /* BT 1.2+ */
-#define HCI_EVENT_ALL_BT_1_2                                     0x00001FFFFFFFFFFFULL /* also the default for BT 1.2+ */
-#define HCI_EVENT_SNIFF_SUBRATING                                0x0000200000000000ULL /* BT 2.1+ */
-#define HCI_EVENT_EXTENDED_INQUIRY_RESULT                        0x0000400000000000ULL /* BT 2.1+ */
-#define HCI_EVENT_ENCR_KEY_REFRESH_COMPLETE                      0x0000800000000000ULL /* BT 2.1+ */
-#define HCI_EVENT_IO_CAPABILITY_REQUEST                          0x0001000000000000ULL /* BT 2.1+ */
-#define HCI_EVENT_IO_CAPABILITY_REQUEST_REPLY                    0x0002000000000000ULL /* BT 2.1+ */
-#define HCI_EVENT_USER_CONFIRMATION_REQUEST                      0x0004000000000000ULL /* BT 2.1+ */
-#define HCI_EVENT_USER_PASSKEY_REQUEST                           0x0008000000000000ULL /* BT 2.1+ */
-#define HCI_EVENT_REMOTE_OOB_DATA_REQUEST                        0x0010000000000000ULL /* BT 2.1+ */
-#define HCI_EVENT_SIMPLE_PAIRING_COMPLETE                        0x0020000000000000ULL /* BT 2.1+ */
-#define HCI_EVENT_LINK_SUPERVISION_TIMOUT_CHANGED                0x0080000000000000ULL /* BT 2.1+ */
-#define HCI_EVENT_ENHANCED_FLUSH_COMPLETE                        0x0100000000000000ULL /* BT 2.1+ */
-#define HCI_EVENT_USER_PASSKEY_NOTIFICATION                      0x0400000000000000ULL /* BT 2.1+ */
-#define HCI_EVENT_KEYPRESS_NOTIFICATION                          0x0800000000000000ULL /* BT 2.1+ */
-#define HCI_EVENT_REMOTE_HOST_SUPPORTED_FEATURES                 0x1000000000000000ULL /* BT 2.1+ */
-#define HCI_EVENT_ALL_BT_2_1                                     0x1DBFFFFFFFFFFFFFULL
-#define HCI_EVENT_ALL_BT_3_0                                     0x1DBFFFFFFFFFFFFFULL
-#define HCI_EVENT_LE_META                                        0x2000000000000000ULL /* BT 4.0+ */
-#define HCI_EVENT_ALL_BT_4_0                                     0x3DBFFFFFFFFFFFFFULL
-#define HCI_EVENT_ALL_BT_4_1                                     0x3DBFFFFFFFFFFFFFULL
-
-#define HCI_EVENT_P2_PHYS_LINK_COMPLETE                          0x0000000000000001ULL /* BT 3.0+ */
-#define HCI_EVENT_P2_CHANNEL_SELECTED                            0x0000000000000002ULL /* BT 3.0+ */
-#define HCI_EVENT_P2_DISCONNECTION_PHYSICAL_LINK                 0x0000000000000004ULL /* BT 3.0+ */
-#define HCI_EVENT_P2_PHYSICAL_LINK_LOSS_EARLY_WARNING            0x0000000000000008ULL /* BT 3.0+ */
-#define HCI_EVENT_P2_PHYSICAL_LINK_RECOVERY                      0x0000000000000010ULL /* BT 3.0+ */
-#define HCI_EVENT_P2_LOGICAL_LINK_COMPLETE                       0x0000000000000020ULL /* BT 3.0+ */
-#define HCI_EVENT_P2_DISCONNECTION_LOGICAL_LINK_COMPLETE         0x0000000000000040ULL /* BT 3.0+ */
-#define HCI_EVENT_P2_FLOW_SPEC_MODIFY_COMPLETE                   0x0000000000000080ULL /* BT 3.0+ */
-#define HCI_EVENT_P2_NUMBER_OF_COMPLETED_DATA_BLOCKS             0x0000000000000100ULL /* BT 3.0+ */
-#define HCI_EVENT_P2_AMP_START_TEST                              0x0000000000000200ULL /* BT 3.0+ */
-#define HCI_EVENT_P2_AMP_TEST_END                                0x0000000000000400ULL /* BT 3.0+ */
-#define HCI_EVENT_P2_AMP_RECEIVER_REPORT                         0x0000000000000800ULL /* BT 3.0+ */
-#define HCI_EVENT_P2_SHORT_RANGE_MODE_CHANGE_COMPLETE            0x0000000000001000ULL /* BT 3.0+ */
-#define HCI_EVENT_P2_AMP_STATUS_CHANGE                           0x0000000000002000ULL /* BT 3.0+ */
-#define HCI_EVENT_P2_ALL_BT_3_0                                  0x0000000000003FFFULL
-#define HCI_EVENT_P2_ALL_BT_4_0                                  0x0000000000003FFFULL
-#define HCI_EVENT_P2_TRIGGERED_CLOCK_CAPTURE                     0x0000000000004000ULL /* BT 4.1+ */
-#define HCI_EVENT_P2_SYNCH_TRAIN_COMPLETE                        0x0000000000008000ULL /* BT 4.1+ */
-#define HCI_EVENT_P2_SYNCH_TRAIN_RECEIVED                        0x0000000000010000ULL /* BT 4.1+ */
-#define HCI_EVENT_P2_CONNLESS_SLAVE_BROADCAST_RXED               0x0000000000020000ULL /* BT 4.1+ */
-#define HCI_EVENT_P2_CONNLESS_SLAVE_BROADCAST_TIMEOUT            0x0000000000040000ULL /* BT 4.1+ */
-#define HCI_EVENT_P2_TRUNCATED_PAGE_COMPLETE                     0x0000000000080000ULL /* BT 4.1+ */
-#define HCI_EVENT_P2_SLAVE_PAGE_RESPONSE_TIMEOUT                 0x0000000000100000ULL /* BT 4.1+ */
-#define HCI_EVENT_P2_CONNLESS_SLAVE_BROADCAST_CHANNEL_MAP_CHANGE 0x0000000000200000ULL /* BT 4.1+ */
-#define HCI_EVENT_P2_INQUIRY_RESPONSE_NOTIFICATION               0x0000000000400000ULL /* BT 4.1+ */
-#define HCI_EVENT_P2_AUTHENTICATED_PAYLOAD_TIMEOUT_EXPIRED       0x0000000000800000ULL /* BT 4.1+ */
-#define HCI_EVENT_P2_ALL_BT_4_1                                  0x0000000000FFFFFFULL
-
-#define HCI_LE_EVENT_CONN_COMPLETE                               0x0000000000000001ULL /* BT 4.0+ */
-#define HCI_LE_EVENT_ADV_REPORT                                  0x0000000000000002ULL /* BT 4.0+ */
-#define HCI_LE_EVENT_CONN_UPDATE_COMPLETE                        0x0000000000000004ULL /* BT 4.0+ */
-#define HCI_LE_EVENT_READ_REMOTE_USED_FEATURES_CMPLETE           0x0000000000000008ULL /* BT 4.0+ */
-#define HCI_LE_EVENT_LTK_REQUEST                                 0x0000000000000010ULL /* BT 4.0+ */
-#define HCI_LE_EVENT_REMOTE_CONNECTION_PARAMETER_REQUEST         0x0000000000000020ULL /* BT 4.1+ */
-
-#define HCI_LE_FTR_ENCRYPTION                                    0x0000000000000001ULL /* BT 4.0+ */
-#define HCI_LE_FTR_CONNECTION_PARAMETERS_REQUEST                 0x0000000000000002ULL /* BT 4.1+ */
-#define HCI_LE_FTR_EXTENDED_REJECT_INDICATION                    0x0000000000000004ULL /* BT 4.1+ */
-#define HCI_LE_FTR_SLAVE_INITIATED_FEATURES_EXCHANGE             0x0000000000000008ULL /* BT 4.1+ */
-#define HCI_LE_FTR_LE_PING                                       0x0000000000000010ULL /* BT 4.1+ */
-
-
-
-
-
-#define HCI_OGF_Link_Control                                     1
-
+#define HCI_DEV_NAME_LEN 248
+
+#define HCI_INQUIRY_LENGTH_UNIT 1280 /* msec */
+#define HCI_INQUIRY_LENGTH_MAX 48 /* units */
+
+#define HCI_LAP_Unlimited_Inquiry 0x9E8B33
+#define HCI_LAP_Limited_Inquiry 0x9E8B00
+
+#define HCI_CLOCK_OFST_VALID 0x8000
+
+#define HCI_PKT_TYP_NO_2_DH1 0x0002 /* BT 2.1+ */
+#define HCI_PKT_TYP_NO_3_DH1 0x0004 /* BT 2.1+ */
+#define HCI_PKT_TYP_DM1 0x0008 /* BT 1.1+ */
+#define HCI_PKT_TYP_DH1 0x0010 /* BT 1.1+ */
+#define HCI_PKT_TYP_NO_2_DH3 0x0100 /* BT 2.1+ */
+#define HCI_PKT_TYP_NO_3_DH3 0x0200 /* BT 2.1+ */
+#define HCI_PKT_TYP_DM3 0x0400 /* BT 1.1+ */
+#define HCI_PKT_TYP_DH3 0x0800 /* BT 1.1+ */
+#define HCI_PKT_TYP_NO_2_DH5 0x1000 /* BT 2.1+ */
+#define HCI_PKT_TYP_NO_3_DH5 0x1000 /* BT 2.1+ */
+#define HCI_PKT_TYP_DM5 0x4000 /* BT 1.1+ */
+#define HCI_PKT_TYP_DH5 0x8000 /* BT 1.1+ */
+#define HCI_PKT_TYP_DEFAULT 0xCC18
+
+#define HCI_PKT_TYP_SCO_HV1 0x0001 /* BT 1.1+ */
+#define HCI_PKT_TYP_SCO_HV2 0x0002 /* BT 1.1+ */
+#define HCI_PKT_TYP_SCO_HV3 0x0004 /* BT 1.1+ */
+#define HCI_PKT_TYP_SCO_EV3 0x0008 /* BT 1.2+ */
+#define HCI_PKT_TYP_SCO_EV4 0x0010 /* BT 1.2+ */
+#define HCI_PKT_TYP_SCO_EV5 0x0020 /* BT 1.2+ */
+#define HCI_PKT_TYP_SCO_NO_2_EV3 0x0040 /* BT 2.1+ */
+#define HCI_PKT_TYP_SCO_NO_3_EV3 0x0080 /* BT 2.1+ */
+#define HCI_PKT_TYP_SCO_NO_2_EV5 0x0100 /* BT 2.1+ */
+#define HCI_PKT_TYP_SCO_NO_3_EV5 0x0200 /* BT 2.1+ */
+
+#define HCI_LINK_POLICY_DISABLE_ALL_LM_MODES 0x0000
+#define HCI_LINK_POLICY_ENABLE_ROLESWITCH 0x0001
+#define HCI_LINK_POLICY_ENABLE_HOLD_MODE 0x0002
+#define HCI_LINK_POLICY_ENABLE_SNIFF_MODE 0x0004
+#define HCI_LINK_POLICY_ENABLE_PARK_MODE 0x0008
+
+#define HCI_FILTER_TYPE_CLEAR_ALL 0x00 /* no subtypes, no data */
+#define HCI_FILTER_INQUIRY_RESULT 0x01 /* below subtypes */
+#define HCI_FILTER_COND_TYPE_RETURN_ALL_DEVS 0x00 /* no data */
+#define HCI_FILTER_COND_TYPE_SPECIFIC_DEV_CLS                                  \
+	0x01 /* uint24_t wanted_class, uint24_t wanted_mask (only set bits are \
+		compared to wanted_class) */
+#define HCI_FILTER_COND_TYPE_SPECIFIC_ADDR 0x02 /* uint8_t mac[6] */
+#define HCI_FILTER_CONNECTION_SETUP 0x02 /* below subtypes */
+#define HCI_FILTER_COND_TYPE_ALLOW_CONNS_FROM_ALL_DEVS                        \
+	0x00 /* uint8_t auto_accept_type: 1 - no, 2 - yes w/ no roleswitch, 3 \
+		- yes w/ roleswitch */
+#define HCI_FILTER_COND_TYPE_ALLOW_CONNS_FROM_SPECIFIC_DEV_CLS                 \
+	0x01 /* uint24_t wanted_class, uint24_t wanted_mask (only set bits are \
+		compared to wanted_class), auto_accept flag same as above */
+#define HCI_FILTER_COND_TYPE_ALLOW_CONNS_FROM_SPECIFIC_ADDR \
+	0x02 /* uint8_t mac[6], auto_accept flag same as above */
+
+#define HCI_SCAN_ENABLE_INQUIRY 0x01 /* discoverable */
+#define HCI_SCAN_ENABLE_PAGE 0x02 /* connectable */
+
+#define HCI_HOLD_MODE_SUSPEND_PAGE_SCAN 0x01
+#define HCI_HOLD_MODE_SUSPEND_INQUIRY_SCAN 0x02
+#define HCI_HOLD_MODE_SUSPEND_PERIODIC_INQUIRIES 0x04
+
+#define HCI_TO_HOST_FLOW_CTRL_ACL 0x01
+#define HCI_TO_HOST_FLOW_CTRL_SCO 0x02
+
+#define HCI_INQ_MODE_STD 0 /* normal mode @ BT 1.1+ */
+#define HCI_INQ_MODE_RSSI 1 /* with RSSI   @ BT 1.2+ */
+#define HCI_INQ_MODE_EIR 2 /* with EIR    @ BT 2.1+ */
+
+#define HCI_SSP_KEY_ENTRY_STARTED 0
+#define HCI_SSP_KEY_ENTRY_DIGIT_ENTERED 1
+#define HCI_SSP_KEY_ENTRY_DIGIT_ERASED 2
+#define HCI_SSP_KEY_ENTRY_CLEARED 3
+#define HCI_SSP_KEY_ENTRY_COMPLETED 4
+
+#define HCI_LOCATION_DOMAIN_OPTION_NONE 0x20 /* ' ' */
+#define HCI_LOCATION_DOMAIN_OPTION_OUTDOORS_ONLY 0x4F /* 'O' */
+#define HCI_LOCATION_DOMAIN_OPTION_INDOORS_ONLY 0x49 /* 'I' */
+#define HCI_LOCATION_DOMAIN_OPTION_NON_COUNTRY_ENTITY 0x58 /* 'X' */
+
+#define HCI_PERIOD_TYPE_DOWNLINK 0x00
+#define HCI_PERIOD_TYPE_UPLINK 0x01
+#define HCI_PERIOD_TYPE_BIDIRECTIONAL 0x02
+#define HCI_PERIOD_TYPE_GUARD_PERIOD 0x03
+
+#define HCI_MWS_INTERVAL_TYPE_NO_RX_NO_TX 0x00
+#define HCI_MWS_INTERVAL_TYPE_TX_ALLOWED 0x01
+#define HCI_MWS_INTERVAL_TYPE_RX_ALLOWED 0x02
+#define HCI_MWS_INTERVAL_TYPE_TX_RX_ALLOWED 0x03
+#define HCI_MWS_INTERVAL_TYPE_FRAME \
+	0x04 /* type defined by Set External Frame Configuration command */
+
+#define HCI_CONNLESS_FRAG_TYPE_CONT 0x00 /* continuation fragment */
+#define HCI_CONNLESS_FRAG_TYPE_START 0x01 /* first fragment */
+#define HCI_CONNLESS_FRAG_TYPE_END 0x02 /* last fragment */
+#define HCI_CONNLESS_FRAG_TYPE_COMPLETE \
+	0x03 /* complete fragment - no fragmentation */
+
+#define HCI_CUR_MODE_ACTIVE 0x00
+#define HCI_CUR_MODE_HOLD 0x01
+#define HCI_CUR_MODE_SNIFF 0x02
+#define HCI_CUR_MODE_PARK 0x03
+
+#define HCI_SCO_LINK_TYPE_SCO 0x00
+#define HCI_SCO_LINK_TYPE_ESCO 0x02
+
+#define HCI_SCO_AIR_MODE_MULAW 0x00
+#define HCI_SCO_AIR_MODE_ALAW 0x01
+#define HCI_SCO_AIR_MODE_CVSD 0x02
+#define HCI_SCO_AIR_MODE_TRANSPARENT 0x03
+
+#define HCI_MCA_500_PPM 0x00
+#define HCI_MCA_250_PPM 0x01
+#define HCI_MCA_150_PPM 0x02
+#define HCI_MCA_100_PPM 0x03
+#define HCI_MCA_75_PPM 0x04
+#define HCI_MCA_50_PPM 0x05
+#define HCI_MCA_30_PPM 0x06
+#define HCI_MCA_20_PPM 0x07
+
+#define HCI_EDR_LINK_KEY_COMBO 0x00
+#define HCI_EDR_LINK_KEY_LOCAL 0x01
+#define HCI_EDR_LINK_KEY_REMOTE 0x02
+#define HCI_EDR_LINK_KEY_DEBUG 0x03
+#define HCI_EDR_LINK_KEY_UNAUTH_COMBO 0x04
+#define HCI_EDR_LINK_KEY_AUTH_COMBO 0x05
+#define HCI_EDR_LINK_KEY_CHANGED 0x06
+
+#define HCI_VERSION_1_0_B 0 /* BT 1.0b */
+#define HCI_VERSION_1_1 1 /* BT 1.1  */
+#define HCI_VERSION_1_2 2 /* BT 1.2  */
+#define HCI_VERSION_2_0 4 /* BT 2.0  */
+#define HCI_VERSION_2_1 3 /* BT 2.1  */
+#define HCI_VERSION_3_0 4 /* BT 3.0  */
+#define HCI_VERSION_4_0 6 /* BT 4.0  */
+#define HCI_VERSION_4_1 7 /* BT 4.1  */
+
+#define HCI_LE_STATE_NONCON_ADV 0x0000000000000001ULL /* BT 4.0+ */
+#define HCI_LE_STATE_SCANNABLE_ADV 0x0000000000000002ULL /* BT 4.0+ */
+#define HCI_LE_STATE_CONNECTABLE_ADV 0x0000000000000004ULL /* BT 4.0+ */
+#define HCI_LE_STATE_DIRECT_ADV 0x0000000000000008ULL /* BT 4.0+ */
+#define HCI_LE_STATE_PASSIVE_SCAN 0x0000000000000010ULL /* BT 4.0+ */
+#define HCI_LE_STATE_ACTIVE_SCAN 0x0000000000000020ULL /* BT 4.0+ */
+#define HCI_LE_STATE_INITIATE 0x0000000000000040ULL /* BT 4.0+ */
+#define HCI_LE_STATE_SLAVE 0x0000000000000080ULL /* BT 4.0+ */
+#define HCI_LE_STATE_NONCON_ADV_w_PASSIVE_SCAN \
+	0x0000000000000100ULL /* BT 4.0+ */
+#define HCI_LE_STATE_SCANNABLE_ADV_w_PASSIVE_SCAN \
+	0x0000000000000200ULL /* BT 4.0+ */
+#define HCI_LE_STATE_CONNECTABLE_ADV_w_PASSIVE_SCAN \
+	0x0000000000000400ULL /* BT 4.0+ */
+#define HCI_LE_STATE_DIRECT_ADV_w_PASSIVE_SCAN \
+	0x0000000000000800ULL /* BT 4.0+ */
+#define HCI_LE_STATE_NONCON_ADV_w_ACTIVE_SCAN \
+	0x0000000000001000ULL /* BT 4.0+ */
+#define HCI_LE_STATE_SCANNABLE_ADV_w_ACTIVE_SCAN \
+	0x0000000000002000ULL /* BT 4.0+ */
+#define HCI_LE_STATE_CONNECTABLE_ADV_w_ACTIVE_SCAN \
+	0x0000000000004000ULL /* BT 4.0+ */
+#define HCI_LE_STATE_DIRECT_ADV_w_ACTIVE_SCAN \
+	0x0000000000008000ULL /* BT 4.0+ */
+#define HCI_LE_STATE_NONCON_ADV_w_INITIATING \
+	0x0000000000010000ULL /* BT 4.0+     \
+			       */
+#define HCI_LE_STATE_SCANNABLE_ADV_w_INITIATING \
+	0x0000000000020000ULL /* BT 4.0+ */
+#define HCI_LE_STATE_NONCON_ADV_w_MASTER 0x0000000000040000ULL /* BT 4.0+ */
+#define HCI_LE_STATE_SCANNABLE_ADV_w_MASTER \
+	0x0000000000080000ULL /* BT 4.0+    \
+			       */
+#define HCI_LE_STATE_NONCON_ADV_w_SLAVE 0x0000000000100000ULL /* BT 4.0+ */
+#define HCI_LE_STATE_SCANNABLE_ADV_w_SLAVE 0x0000000000200000ULL /* BT 4.0+ */
+#define HCI_LE_STATE_PASSIVE_SCAN_w_INITIATING \
+	0x0000000000400000ULL /* BT 4.0+ */
+#define HCI_LE_STATE_ACTIVE_SCAN_w_INITIATING \
+	0x0000000000800000ULL /* BT 4.0+ */
+#define HCI_LE_STATE_PASSIVE_SCAN_w_MASTER 0x0000000001000000ULL /* BT 4.0+ */
+#define HCI_LE_STATE_ACTIVE_SCAN_w_MASTER 0x0000000002000000ULL /* BT 4.0+ */
+#define HCI_LE_STATE_PASSIVE_SCAN_w_SLAVE 0x0000000004000000ULL /* BT 4.0+ */
+#define HCI_LE_STATE_ACTIVE_SCAN_w_SLAVE 0x0000000008000000ULL /* BT 4.0+ */
+#define HCI_LE_STATE_INTIATING_w_MASTER 0x0000000010000000ULL /* BT 4.0+ */
+#define HCI_LE_STATE_LOW_DUTY_CYCLE_DIRECT_ADV \
+	0x0000000020000000ULL /* BT 4.1+ */
+#define HCI_LE_STATE_PASSIVE_SCAN_w_LOW_DUTY_CYCLE_DIRECT_ADV \
+	0x0000000040000000ULL /* BT 4.1+ */
+#define HCI_LE_STATE_ACTIVE_SCAN_w_LOW_DUTY_CYCLE_DIRECT_ADV \
+	0x0000000080000000ULL /* BT 4.1+ */
+#define HCI_LE_STATE_CONNECTABLE_ADV_w_INITIATING \
+	0x0000000100000000ULL /* BT 4.1+ */
+#define HCI_LE_STATE_DIRECT_ADV_w_INITIATING \
+	0x0000000200000000ULL /* BT 4.1+     \
+			       */
+#define HCI_LE_STATE_LOW_DUTY_CYCLE_DIRECT_ADV_w_INITIATING \
+	0x0000000400000000ULL /* BT 4.1+ */
+#define HCI_LE_STATE_CONNECTABLE_ADV_w_MASTER \
+	0x0000000800000000ULL /* BT 4.1+ */
+#define HCI_LE_STATE_DIRECT_ADV_w_MASTER 0x0000001000000000ULL /* BT 4.1+ */
+#define HCI_LE_STATE_LOW_DUTY_CYCLE_DIRECT_ADV_w_MASTER \
+	0x0000002000000000ULL /* BT 4.1+ */
+#define HCI_LE_STATE_CONNECTABLE_ADV_w_SLAVE \
+	0x0000004000000000ULL /* BT 4.1+     \
+			       */
+#define HCI_LE_STATE_DIRECT_ADV_w_SLAVE 0x0000008000000000ULL /* BT 4.1+ */
+#define HCI_LE_STATE_LOW_DUTY_CYCLE_DIRECT_ADV_w_SLAVE \
+	0x0000010000000000ULL /* BT 4.1+ */
+#define HCI_LE_STATE_INITIATING_w_SLAVE 0x0000020000000000ULL /* BT 4.1+ */
+
+#define HCI_LMP_FTR_3_SLOT_PACKETS 0x0000000000000001ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_5_SLOT_PACKETS 0x0000000000000002ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_ENCRYPTION 0x0000000000000004ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_SLOT_OFFSET 0x0000000000000008ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_TIMING_ACCURACY 0x0000000000000010ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_SWITCH 0x0000000000000020ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_HOLD_MODE 0x0000000000000040ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_SNIFF_MODE 0x0000000000000080ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_PARK_MODE 0x0000000000000100ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_RSSI 0x0000000000000200ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_CHANNEL_QUALITY_DRIVEN_DATA_RATE \
+	0x0000000000000400ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_SCO_LINKS 0x0000000000000800ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_HV2_PACKETS 0x0000000000001000ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_HV3_PACKETS 0x0000000000002000ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_MU_LAW 0x0000000000004000ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_A_LAW 0x0000000000008000ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_CVSD 0x0000000000010000ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_PAGING_SCHEME 0x0000000000020000ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_POWER_CONTROL 0x0000000000040000ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_TRANSPARENT_SCO_DATA 0x0000000000080000ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_FLOW_CONTROL_LAG_B0 0x0000000000100000ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_FLOW_CONTROL_LAG_B1 0x0000000000200000ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_FLOW_CONTROL_LAG_B2 0x0000000000400000ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_BROADCAST_ENCRYPTION 0x0000000000800000ULL /* BT 1.2+ */
+#define HCI_LMP_FTR_ACL_2MBPS 0x0000000002000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_ACL_3MBPS 0x0000000004000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_ENHANCED_INQUIRY_SCAN 0x0000000008000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_INTERLACED_INQUIRY_SCAN \
+	0x0000000010000000ULL /* BT 2.1+    \
+			       */
+#define HCI_LMP_FTR_INTERLACED_PAGE_SCAN 0x0000000020000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_RSSI_WITH_INQUIRY_RESULTS \
+	0x0000000040000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_EXTENDED_SCO_LINK \
+	0x0000000080000000ULL /* BT 2.1+ */ /* EV3 packets */
+#define HCI_LMP_FTR_EV4_PACKETS 0x0000000100000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_EV5_PACKETS 0x0000000200000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_AFH_CAPABLE_SLAVE 0x0000000800000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_AFH_CLASSIFICATION_SLAVE \
+	0x0000001000000000ULL /* BT 2.1+     \
+			       */
+#define HCI_LMP_FTR_BR_EDR_NOT_SUPPORTED 0x0000002000000000ULL /* BT 4.0+ */
+#define HCI_LMP_FTR_LE_SUPPORTED_CONTROLLER \
+	0x0000004000000000ULL /* BT 4.0+    \
+			       */
+#define HCI_LMP_FTR_3_SLOT_ACL_PACKETS 0x0000008000000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_5_SLOT_ACL_PACKETS 0x0000010000000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_SNIFF_SUBRATING 0x0000020000000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_PAUSE_ENCRYPTION 0x0000040000000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_AFH_CAPABLE_MASTER 0x0000080000000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_AFH_CLASSIFICATION_MASTER \
+	0x0000100000000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_ESCO_2MBPS 0x0000200000000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_ESCO_3MBPS 0x0000400000000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_3_SLOT_ESCO 0x0000800000000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_EXTENDED_INQUIRY_RESPONSE \
+	0x0001000000000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_SSP 0x0008000000000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_ENCAPSULATED_PDU 0x0010000000000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_ERRONEOUS_DATA_REPORTING \
+	0x0020000000000000ULL /* BT 2.1+     \
+			       */
+#define HCI_LMP_FTR_NON_FLUSHABLE_PACKET_BOUNDARY_FLAG \
+	0x0040000000000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_LINK_SUPERVISION_TIMEOUT_CHANGED_EVENT \
+	0x0100000000000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_INQUIRY_RESPONSE_TX_POWER_LEVEL \
+	0x0200000000000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_EXTENDED_FEATURES 0x8000000000000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_ENHANCED_POWER_CONTROL 0x0400000000000000ULL /* BT 3.0+ */
+#define HCI_LMP_FTR_SIMUL_LE_EDR_CAPABLE_CONTROLLER \
+	0x0002000000000000ULL /* BT 4.0+ */
+
+#define HCI_LMP_EXT_FTR_P1_SSP_HOST_SUPPORT \
+	0x0000000000000001ULL /* BT 2.1+    \
+			       */
+#define HCI_LMP_EXT_FTR_P1_LE_HOST_SUPPORT 0x0000000000000002ULL /* BT 4.0+ */
+#define HCI_LMP_EXT_FTR_P1_SIMUL_LE_EDR_HOST_SUPPORT \
+	0x0000000000000004ULL /* BT 4.0+ */
+#define HCI_LMP_EXT_FTR_P1_SECURE_CONNECTIONS_HOST_SUPPORT \
+	0x0000000000000008ULL /* BT 4.1+ */
+
+#define HCI_LMP_EXT_FTR_P2_CONNLESS_SLAVE_BROADCAST_MASTER \
+	0x0000000000000001ULL /* BT 4.1+ */
+#define HCI_LMP_EXT_FTR_P2_CONNLESS_SLAVE_BROADCAST_SLAVE \
+	0x0000000000000002ULL /* BT 4.1+ */
+#define HCI_LMP_EXT_FTR_P2_SYNCHRONIZATION_TRAIN \
+	0x0000000000000004ULL /* BT 4.1+ */
+#define HCI_LMP_EXT_FTR_P2_SYNCHRONIZATION_SCAN \
+	0x0000000000000008ULL /* BT 4.1+ */
+#define HCI_LMP_EXT_FTR_P2_INQUIRY_RESPONSE_NOTIFICATION_EVT \
+	0x0000000000000010ULL /* BT 4.1+ */
+#define HCI_LMP_EXT_FTR_P2_GENERALIZED_INTERLACED_SCAN \
+	0x0000000000000020ULL /* BT 4.1+ */
+#define HCI_LMP_EXT_FTR_P2_COARSE_CLOCK_ADJUSTMENT \
+	0x0000000000000040ULL /* BT 4.1+ */
+#define HCI_LMP_EXT_FTR_P2_SECURE_CONNECTIONS_CAPABLE_CONTROLLER \
+	0x0000000000000100ULL /* BT 4.1+ */
+#define HCI_LMP_EXT_FTR_P2_PING 0x0000000000000200ULL /* BT 4.1+ */
+#define HCI_LMP_EXT_FTR_P2_TRAIN_NUDGING 0x0000000000000800ULL /* BT 4.1+ */
+
+#define HCI_EVENT_INQUIRY_COMPLETE 0x0000000000000001ULL /* BT 1.1+ */
+#define HCI_EVENT_INQUIRY_RESULT 0x0000000000000002ULL /* BT 1.1+ */
+#define HCI_EVENT_CONN_COMPLETE 0x0000000000000004ULL /* BT 1.1+ */
+#define HCI_EVENT_CONN_REQUEST 0x0000000000000008ULL /* BT 1.1+ */
+#define HCI_EVENT_DISCONNECTION_COMPLETE 0x0000000000000010ULL /* BT 1.1+ */
+#define HCI_EVENT_AUTH_COMPLETE 0x0000000000000020ULL /* BT 1.1+ */
+#define HCI_EVENT_REMOTE_NAME_REQUEST_COMPLETE \
+	0x0000000000000040ULL /* BT 1.1+ */
+#define HCI_EVENT_ENCR_CHANGE 0x0000000000000080ULL /* BT 1.1+ */
+#define HCI_EVENT_CHANGE_CONN_LINK_KEY_COMPLETE \
+	0x0000000000000100ULL /* BT 1.1+ */
+#define HCI_EVENT_MASTER_LINK_KEY_COMPLETE 0x0000000000000200ULL /* BT 1.1+ */
+#define HCI_EVENT_READ_REMOTE_SUPPORTED_FEATURES_COMPLETE \
+	0x0000000000000400ULL /* BT 1.1+ */
+#define HCI_EVENT_READ_REMOTE_VERSION_INFO_COMPLETE \
+	0x0000000000000800ULL /* BT 1.1+ */
+#define HCI_EVENT_QOS_SETUP_COMPLETE 0x0000000000001000ULL /* BT 1.1+ */
+#define HCI_EVENT_HARDWARE_ERROR 0x0000000000008000ULL /* BT 1.1+ */
+#define HCI_EVENT_FLUSH_OCCURRED 0x0000000000010000ULL /* BT 1.1+ */
+#define HCI_EVENT_ROLE_CHANGE 0x0000000000020000ULL /* BT 1.1+ */
+#define HCI_EVENT_MODE_CHANGE 0x0000000000080000ULL /* BT 1.1+ */
+#define HCI_EVENT_RETURN_LINK_KEYS 0x0000000000100000ULL /* BT 1.1+ */
+#define HCI_EVENT_PIN_CODE_REQUEST 0x0000000000200000ULL /* BT 1.1+ */
+#define HCI_EVENT_LINK_KEY_REQUEST 0x0000000000400000ULL /* BT 1.1+ */
+#define HCI_EVENT_LINK_KEY_NOTIFICATION 0x0000000000800000ULL /* BT 1.1+ */
+#define HCI_EVENT_LOOPBACK_COMMAND 0x0000000001000000ULL /* BT 1.1+ */
+#define HCI_EVENT_DATA_BUFFER_OVERFLOW 0x0000000002000000ULL /* BT 1.1+ */
+#define HCI_EVENT_MAX_SLOTS_CHANGE 0x0000000004000000ULL /* BT 1.1+ */
+#define HCI_EVENT_READ_CLOCK_OFFSET_COMPLETE \
+	0x0000000008000000ULL /* BT 1.1+     \
+			       */
+#define HCI_EVENT_CONN_PACKET_TYPE_CHANGED 0x0000000010000000ULL /* BT 1.1+ */
+#define HCI_EVENT_QOS_VIOLATION 0x0000000020000000ULL /* BT 1.1+ */
+#define HCI_EVENT_PAGE_SCAN_MODE_CHANGE \
+	0x0000000040000000ULL /* BT 1.1+, obsolete @ BT1.2+ */
+#define HCI_EVENT_PAGE_SCAN_REPETITION_MODE_CHANGE \
+	0x0000000080000000ULL /* BT 1.1+ */
+#define HCI_EVENT_ALL_BT_1_1 \
+	0x00000000FFFFFFFFULL /* also the default for BT 1.1 */
+#define HCI_EVENT_FLOW_SPEC_COMPLETE 0x0000000100000000ULL /* BT 1.2+ */
+#define HCI_EVENT_INQUIRY_RESULT_WITH_RSSI 0x0000000200000000ULL /* BT 1.2+ */
+#define HCI_EVENT_READ_REMOTE_EXTENDED_FEATURES_COMPLETE \
+	0x0000000400000000ULL /* BT 1.2+ */
+#define HCI_EVENT_SYNC_CONN_COMPLETE 0x0000080000000000ULL /* BT 1.2+ */
+#define HCI_EVENT_SYNC_CONN_CHANGED 0x0000100000000000ULL /* BT 1.2+ */
+#define HCI_EVENT_ALL_BT_1_2 \
+	0x00001FFFFFFFFFFFULL /* also the default for BT 1.2+ */
+#define HCI_EVENT_SNIFF_SUBRATING 0x0000200000000000ULL /* BT 2.1+ */
+#define HCI_EVENT_EXTENDED_INQUIRY_RESULT 0x0000400000000000ULL /* BT 2.1+ */
+#define HCI_EVENT_ENCR_KEY_REFRESH_COMPLETE \
+	0x0000800000000000ULL /* BT 2.1+    \
+			       */
+#define HCI_EVENT_IO_CAPABILITY_REQUEST 0x0001000000000000ULL /* BT 2.1+ */
+#define HCI_EVENT_IO_CAPABILITY_REQUEST_REPLY \
+	0x0002000000000000ULL /* BT 2.1+ */
+#define HCI_EVENT_USER_CONFIRMATION_REQUEST \
+	0x0004000000000000ULL /* BT 2.1+    \
+			       */
+#define HCI_EVENT_USER_PASSKEY_REQUEST 0x0008000000000000ULL /* BT 2.1+ */
+#define HCI_EVENT_REMOTE_OOB_DATA_REQUEST 0x0010000000000000ULL /* BT 2.1+ */
+#define HCI_EVENT_SIMPLE_PAIRING_COMPLETE 0x0020000000000000ULL /* BT 2.1+ */
+#define HCI_EVENT_LINK_SUPERVISION_TIMOUT_CHANGED \
+	0x0080000000000000ULL /* BT 2.1+ */
+#define HCI_EVENT_ENHANCED_FLUSH_COMPLETE 0x0100000000000000ULL /* BT 2.1+ */
+#define HCI_EVENT_USER_PASSKEY_NOTIFICATION \
+	0x0400000000000000ULL /* BT 2.1+    \
+			       */
+#define HCI_EVENT_KEYPRESS_NOTIFICATION 0x0800000000000000ULL /* BT 2.1+ */
+#define HCI_EVENT_REMOTE_HOST_SUPPORTED_FEATURES \
+	0x1000000000000000ULL /* BT 2.1+ */
+#define HCI_EVENT_ALL_BT_2_1 0x1DBFFFFFFFFFFFFFULL
+#define HCI_EVENT_ALL_BT_3_0 0x1DBFFFFFFFFFFFFFULL
+#define HCI_EVENT_LE_META 0x2000000000000000ULL /* BT 4.0+ */
+#define HCI_EVENT_ALL_BT_4_0 0x3DBFFFFFFFFFFFFFULL
+#define HCI_EVENT_ALL_BT_4_1 0x3DBFFFFFFFFFFFFFULL
+
+#define HCI_EVENT_P2_PHYS_LINK_COMPLETE 0x0000000000000001ULL /* BT 3.0+ */
+#define HCI_EVENT_P2_CHANNEL_SELECTED 0x0000000000000002ULL /* BT 3.0+ */
+#define HCI_EVENT_P2_DISCONNECTION_PHYSICAL_LINK \
+	0x0000000000000004ULL /* BT 3.0+ */
+#define HCI_EVENT_P2_PHYSICAL_LINK_LOSS_EARLY_WARNING \
+	0x0000000000000008ULL /* BT 3.0+ */
+#define HCI_EVENT_P2_PHYSICAL_LINK_RECOVERY \
+	0x0000000000000010ULL /* BT 3.0+    \
+			       */
+#define HCI_EVENT_P2_LOGICAL_LINK_COMPLETE 0x0000000000000020ULL /* BT 3.0+ */
+#define HCI_EVENT_P2_DISCONNECTION_LOGICAL_LINK_COMPLETE \
+	0x0000000000000040ULL /* BT 3.0+ */
+#define HCI_EVENT_P2_FLOW_SPEC_MODIFY_COMPLETE \
+	0x0000000000000080ULL /* BT 3.0+ */
+#define HCI_EVENT_P2_NUMBER_OF_COMPLETED_DATA_BLOCKS \
+	0x0000000000000100ULL /* BT 3.0+ */
+#define HCI_EVENT_P2_AMP_START_TEST 0x0000000000000200ULL /* BT 3.0+ */
+#define HCI_EVENT_P2_AMP_TEST_END 0x0000000000000400ULL /* BT 3.0+ */
+#define HCI_EVENT_P2_AMP_RECEIVER_REPORT 0x0000000000000800ULL /* BT 3.0+ */
+#define HCI_EVENT_P2_SHORT_RANGE_MODE_CHANGE_COMPLETE \
+	0x0000000000001000ULL /* BT 3.0+ */
+#define HCI_EVENT_P2_AMP_STATUS_CHANGE 0x0000000000002000ULL /* BT 3.0+ */
+#define HCI_EVENT_P2_ALL_BT_3_0 0x0000000000003FFFULL
+#define HCI_EVENT_P2_ALL_BT_4_0 0x0000000000003FFFULL
+#define HCI_EVENT_P2_TRIGGERED_CLOCK_CAPTURE \
+	0x0000000000004000ULL /* BT 4.1+     \
+			       */
+#define HCI_EVENT_P2_SYNCH_TRAIN_COMPLETE 0x0000000000008000ULL /* BT 4.1+ */
+#define HCI_EVENT_P2_SYNCH_TRAIN_RECEIVED 0x0000000000010000ULL /* BT 4.1+ */
+#define HCI_EVENT_P2_CONNLESS_SLAVE_BROADCAST_RXED \
+	0x0000000000020000ULL /* BT 4.1+ */
+#define HCI_EVENT_P2_CONNLESS_SLAVE_BROADCAST_TIMEOUT \
+	0x0000000000040000ULL /* BT 4.1+ */
+#define HCI_EVENT_P2_TRUNCATED_PAGE_COMPLETE \
+	0x0000000000080000ULL /* BT 4.1+     \
+			       */
+#define HCI_EVENT_P2_SLAVE_PAGE_RESPONSE_TIMEOUT \
+	0x0000000000100000ULL /* BT 4.1+ */
+#define HCI_EVENT_P2_CONNLESS_SLAVE_BROADCAST_CHANNEL_MAP_CHANGE \
+	0x0000000000200000ULL /* BT 4.1+ */
+#define HCI_EVENT_P2_INQUIRY_RESPONSE_NOTIFICATION \
+	0x0000000000400000ULL /* BT 4.1+ */
+#define HCI_EVENT_P2_AUTHENTICATED_PAYLOAD_TIMEOUT_EXPIRED \
+	0x0000000000800000ULL /* BT 4.1+ */
+#define HCI_EVENT_P2_ALL_BT_4_1 0x0000000000FFFFFFULL
+
+#define HCI_LE_EVENT_CONN_COMPLETE 0x0000000000000001ULL /* BT 4.0+ */
+#define HCI_LE_EVENT_ADV_REPORT 0x0000000000000002ULL /* BT 4.0+ */
+#define HCI_LE_EVENT_CONN_UPDATE_COMPLETE 0x0000000000000004ULL /* BT 4.0+ */
+#define HCI_LE_EVENT_READ_REMOTE_USED_FEATURES_CMPLETE \
+	0x0000000000000008ULL /* BT 4.0+ */
+#define HCI_LE_EVENT_LTK_REQUEST 0x0000000000000010ULL /* BT 4.0+ */
+#define HCI_LE_EVENT_REMOTE_CONNECTION_PARAMETER_REQUEST \
+	0x0000000000000020ULL /* BT 4.1+ */
+
+#define HCI_LE_FTR_ENCRYPTION 0x0000000000000001ULL /* BT 4.0+ */
+#define HCI_LE_FTR_CONNECTION_PARAMETERS_REQUEST \
+	0x0000000000000002ULL /* BT 4.1+ */
+#define HCI_LE_FTR_EXTENDED_REJECT_INDICATION \
+	0x0000000000000004ULL /* BT 4.1+ */
+#define HCI_LE_FTR_SLAVE_INITIATED_FEATURES_EXCHANGE \
+	0x0000000000000008ULL /* BT 4.1+ */
+#define HCI_LE_FTR_LE_PING 0x0000000000000010ULL /* BT 4.1+ */
+
+#define HCI_OGF_Link_Control 1
 
 /* ==== BT 1.1 ==== */
 
-#define HCI_CMD_Inquiry                                          0x0001 /* status */
+#define HCI_CMD_Inquiry 0x0001 /* status */
 struct hciInquiry {
 	uint8_t lap[3];
 	uint8_t inqLen;
 	uint8_t numResp;
 } __packed;
 
-#define HCI_CMD_Inquiry_Cancel                                   0x0002 /* complete */
+#define HCI_CMD_Inquiry_Cancel 0x0002 /* complete */
 struct hciCmplInquiryCancel {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Periodic_Inquiry_Mode                            0x0003 /* complete */
+#define HCI_CMD_Periodic_Inquiry_Mode 0x0003 /* complete */
 struct hciPeriodicInquiryMode {
 	uint16_t maxPeriodLen;
 	uint16_t minPeriodLen;
@@ -390,10 +492,9 @@ struct hciCmplPeriodicInquiryMode {
 	uint8_t status;
 } __packed;
 
+#define HCI_CMD_Exit_Periodic_Inquiry_Mode 0x0004 /* complete */
 
-#define HCI_CMD_Exit_Periodic_Inquiry_Mode                       0x0004 /* complete */
-
-#define HCI_CMD_Create_Connection                                0x0005 /* status */
+#define HCI_CMD_Create_Connection 0x0005 /* status */
 struct hciCreateConnection {
 	uint8_t mac[6];
 	uint16_t allowedPackets; /* HCI_PKT_TYP_* */
@@ -402,19 +503,20 @@ struct hciCreateConnection {
 	uint8_t allowRoleSwitch;
 } __packed;
 
-#define HCI_CMD_Disconnect                                       0x0006 /* status */
+#define HCI_CMD_Disconnect 0x0006 /* status */
 struct hciDisconnect {
 	uint16_t conn;
 	uint8_t reason;
 } __packed;
 
-#define HCI_CMD_Add_SCO_Connection                               0x0007 /* status */ /* deprecated in BT 1.2+ */
+#define HCI_CMD_Add_SCO_Connection \
+	0x0007 /* status */ /* deprecated in BT 1.2+ */
 struct hciAddScoConnection {
 	uint16_t conn;
 	uint16_t packetTypes; /* HCI_PKT_TYP_SCO_* */
 } __packed;
 
-#define HCI_CMD_Create_Connection_Cancel                         0x0008 /* complete */
+#define HCI_CMD_Create_Connection_Cancel 0x0008 /* complete */
 struct hciCreateConnectionCancel {
 	uint8_t mac[6];
 } __packed;
@@ -423,19 +525,19 @@ struct hciCmplCreateConnectionCancel {
 	uint8_t mac[6];
 } __packed;
 
-#define HCI_CMD_Accept_Connection_Request                        0x0009 /* status */
+#define HCI_CMD_Accept_Connection_Request 0x0009 /* status */
 struct hciAcceptConnection {
 	uint8_t mac[6];
 	uint8_t remainSlave;
 } __packed;
 
-#define HCI_CMD_Reject_Connection_Request                        0x000A /* status */
+#define HCI_CMD_Reject_Connection_Request 0x000A /* status */
 struct hciRejectConnection {
 	uint8_t mac[6];
 	uint8_t reason;
 } __packed;
 
-#define HCI_CMD_Link_Key_Request_Reply                           0x000B /* complete */
+#define HCI_CMD_Link_Key_Request_Reply 0x000B /* complete */
 struct hciLinkKeyRequestReply {
 	uint8_t mac[6];
 	uint8_t key[16];
@@ -445,7 +547,7 @@ struct hciCmplLinkKeyRequestReply {
 	uint8_t mac[6];
 } __packed;
 
-#define HCI_CMD_Link_Key_Request_Negative_Reply                  0x000C /* complete */
+#define HCI_CMD_Link_Key_Request_Negative_Reply 0x000C /* complete */
 struct hciLinkKeyRequestNegativeReply {
 	uint8_t mac[6];
 } __packed;
@@ -454,7 +556,7 @@ struct hciCmplLinkKeyRequestNegativeReply {
 	uint8_t mac[6];
 } __packed;
 
-#define HCI_CMD_PIN_Code_Request_Reply                           0x000D /* complete */
+#define HCI_CMD_PIN_Code_Request_Reply 0x000D /* complete */
 struct hciPinCodeRequestReply {
 	uint8_t mac[6];
 	uint8_t pinCodeLen;
@@ -465,7 +567,7 @@ struct hciCmplPinCodeRequestReply {
 	uint8_t mac[6];
 } __packed;
 
-#define HCI_CMD_PIN_Code_Request_Negative_Reply                  0x000E /* complete */
+#define HCI_CMD_PIN_Code_Request_Negative_Reply 0x000E /* complete */
 struct hciPinCodeRequestNegativeReply {
 	uint8_t mac[6];
 } __packed;
@@ -474,34 +576,34 @@ struct hciCmplPinCodeRequestNegativeReply {
 	uint8_t mac[6];
 } __packed;
 
-#define HCI_CMD_Change_Connection_Packet_Type                    0x000F /* status */
+#define HCI_CMD_Change_Connection_Packet_Type 0x000F /* status */
 struct hciChangeConnectionPacketType {
 	uint16_t conn;
 	uint16_t allowedPackets; /* HCI_PKT_TYP_* */
 } __packed;
 
-#define HCI_CMD_Authentication_Requested                         0x0011 /* status */
+#define HCI_CMD_Authentication_Requested 0x0011 /* status */
 struct hciAuthRequested {
 	uint16_t conn;
 } __packed;
 
-#define HCI_CMD_Set_Connection_Encryption                        0x0013 /* status */
+#define HCI_CMD_Set_Connection_Encryption 0x0013 /* status */
 struct hciSetConnectionEncryption {
 	uint16_t conn;
 	uint8_t encrOn;
 } __packed;
 
-#define HCI_CMD_Change_Connection_Link_Key                       0x0015 /* status */
+#define HCI_CMD_Change_Connection_Link_Key 0x0015 /* status */
 struct hciChangeConnLinkKey {
 	uint16_t conn;
 } __packed;
 
-#define HCI_CMD_Master_Link_Key                                  0x0017 /* status */
+#define HCI_CMD_Master_Link_Key 0x0017 /* status */
 struct hciMasterLinkKey {
 	uint8_t useTempKey;
 } __packed;
 
-#define HCI_CMD_Remote_Name_Request                              0x0019 /* status */
+#define HCI_CMD_Remote_Name_Request 0x0019 /* status */
 struct hciRemoteNameRequest {
 	uint8_t mac[6];
 	uint8_t PSRM;
@@ -509,7 +611,7 @@ struct hciRemoteNameRequest {
 	uint16_t clockOffset; /* possibly | HCI_CLOCK_OFST_VALID */
 } __packed;
 
-#define HCI_CMD_Remote_Name_Request_Cancel                       0x001A /* complete */
+#define HCI_CMD_Remote_Name_Request_Cancel 0x001A /* complete */
 struct hciRemoteNameRequestCancel {
 	uint8_t mac[6];
 } __packed;
@@ -518,31 +620,30 @@ struct hciCmplRemoteNameRequestCancel {
 	uint8_t mac[6];
 } __packed;
 
-#define HCI_CMD_Read_Remote_Supported_Features                   0x001B /* status */
+#define HCI_CMD_Read_Remote_Supported_Features 0x001B /* status */
 struct hciReadRemoteSupportedFeatures {
 	uint16_t conn;
 } __packed;
 
-#define HCI_CMD_Read_Remote_Version_Information                  0x001D /* status */
+#define HCI_CMD_Read_Remote_Version_Information 0x001D /* status */
 struct hciReadRemoteVersionInfo {
 	uint16_t conn;
 } __packed;
 
-#define HCI_CMD_Read_Clock_Offset                                0x001F /* status */
+#define HCI_CMD_Read_Clock_Offset 0x001F /* status */
 struct hciReadClockOffset {
 	uint16_t conn;
 } __packed;
 
-
 /* ==== BT 1.2 ==== */
 
-#define HCI_CMD_Read_Remote_Extended_Features                    0x001C /* status */
+#define HCI_CMD_Read_Remote_Extended_Features 0x001C /* status */
 struct hciReadRemoteExtendedFeatures {
 	uint16_t conn;
 	uint8_t page; /* BT1.2 max: 0 */
 } __packed;
 
-#define HCI_CMD_Read_Lmp_Handle                                  0x0020 /* complete */
+#define HCI_CMD_Read_Lmp_Handle 0x0020 /* complete */
 struct hciReadLmpHandle {
 	uint16_t handle;
 } __packed;
@@ -553,7 +654,7 @@ struct hciCmplReadLmpHandle {
 	uint32_t reserved;
 } __packed;
 
-#define HCI_CMD_Setup_Synchronous_Connection                     0x0028 /* status */
+#define HCI_CMD_Setup_Synchronous_Connection 0x0028 /* status */
 struct hciSetupSyncConn {
 	uint16_t conn;
 	uint32_t txBandwidth;
@@ -564,7 +665,7 @@ struct hciSetupSyncConn {
 	uint16_t allowedPacketsSco; /* HCI_PKT_TYP_SCO_* */
 } __packed;
 
-#define HCI_CMD_Accept_Synchronous_Connection_Request            0x0029 /* status */
+#define HCI_CMD_Accept_Synchronous_Connection_Request 0x0029 /* status */
 struct hciAcceptSyncConn {
 	uint8_t mac[6];
 	uint32_t txBandwidth;
@@ -575,16 +676,15 @@ struct hciAcceptSyncConn {
 	uint16_t allowedPacketsSco; /* HCI_PKT_TYP_SCO_* */
 } __packed;
 
-#define HCI_CMD_Reject_Synchronous_Connection_Request            0x002A /* status */
+#define HCI_CMD_Reject_Synchronous_Connection_Request 0x002A /* status */
 struct hciRejectSyncConn {
 	uint8_t mac[6];
 	uint8_t reason;
 } __packed;
 
-
 /* ==== BR 2.1 ==== */
 
-#define HCI_CMD_IO_Capability_Request_Reply                      0x002B /* complete */
+#define HCI_CMD_IO_Capability_Request_Reply 0x002B /* complete */
 struct hciIoCapabilityRequestReply {
 	uint8_t mac[6];
 	uint8_t cap; /* HCI_DISPLAY_CAP_* */
@@ -596,7 +696,7 @@ struct hciCmplIoCapabilityRequestReply {
 	uint8_t mac[6];
 } __packed;
 
-#define HCI_CMD_User_Confirmation_Request_Reply                  0x002C /* complete */
+#define HCI_CMD_User_Confirmation_Request_Reply 0x002C /* complete */
 struct hciUserConfRequestReply {
 	uint8_t mac[6];
 } __packed;
@@ -605,7 +705,7 @@ struct hciCmplUserConfRequestReply {
 	uint8_t mac[6];
 } __packed;
 
-#define HCI_CMD_User_Confirmation_Request_Negative_Reply         0x002D /* complete */
+#define HCI_CMD_User_Confirmation_Request_Negative_Reply 0x002D /* complete */
 struct hciUserConfRequestNegativeReply {
 	uint8_t mac[6];
 } __packed;
@@ -614,7 +714,7 @@ struct hciCmplUserConfRequestNegativeReply {
 	uint8_t mac[6];
 } __packed;
 
-#define HCI_CMD_User_Passkey_Request_Reply                       0x002E /* complete */
+#define HCI_CMD_User_Passkey_Request_Reply 0x002E /* complete */
 struct hciUserPasskeyRequestReply {
 	uint8_t mac[6];
 	uint32_t num;
@@ -624,7 +724,7 @@ struct hciCmplUserPasskeyRequestReply {
 	uint8_t mac[6];
 } __packed;
 
-#define HCI_CMD_User_Passkey_Request_Negative_Reply              0x002F /* complete */
+#define HCI_CMD_User_Passkey_Request_Negative_Reply 0x002F /* complete */
 struct hciUserPasskeyRequestNegativeReply {
 	uint8_t mac[6];
 } __packed;
@@ -633,7 +733,7 @@ struct hciCmplUserPasskeyRequestNegativeReply {
 	uint8_t mac[6];
 } __packed;
 
-#define HCI_CMD_Remote_OOB_Data_Request_Reply                    0x0030 /* complete */
+#define HCI_CMD_Remote_OOB_Data_Request_Reply 0x0030 /* complete */
 struct hciRemoteOobDataRequestReply {
 	uint8_t mac[6];
 	uint8_t C[16];
@@ -644,7 +744,7 @@ struct hciCmplRemoteOobDataRequestReply {
 	uint8_t mac[6];
 } __packed;
 
-#define HCI_CMD_Remote_OOB_Data_Request_Negative_Reply           0x0033 /* complete */
+#define HCI_CMD_Remote_OOB_Data_Request_Negative_Reply 0x0033 /* complete */
 struct hciRemoteOobDataRequestNegativeReply {
 	uint8_t mac[6];
 } __packed;
@@ -653,7 +753,7 @@ struct hciCmplRemoteOobDataRequestNegativeReply {
 	uint8_t mac[6];
 } __packed;
 
-#define HCI_CMD_IO_Capability_Request_Negative_Reply             0x0034 /* complete */
+#define HCI_CMD_IO_Capability_Request_Negative_Reply 0x0034 /* complete */
 struct hciIoCapabilityRequestNegativeReply {
 	uint8_t mac[6];
 	uint8_t reason;
@@ -663,10 +763,9 @@ struct hciCmplIoCapabilityRequestNegativeReply {
 	uint8_t mac[6];
 } __packed;
 
-
 /* ==== BT 3.0 ==== */
 
-#define HCI_CMD_Create_Physical_link                             0x0035 /* status */
+#define HCI_CMD_Create_Physical_link 0x0035 /* status */
 struct hciCreatePhysicalLink {
 	uint8_t physLinkHandle;
 	uint8_t dedicatedAmpKeyLength;
@@ -674,7 +773,7 @@ struct hciCreatePhysicalLink {
 	uint8_t dedicatedAmpKey;
 } __packed;
 
-#define HCI_CMD_Accept_Physical_link                             0x0036 /* status */
+#define HCI_CMD_Accept_Physical_link 0x0036 /* status */
 struct hciAcceptPhysicalLink {
 	uint8_t physLinkHandle;
 	uint8_t dedicatedAmpKeyLength;
@@ -682,32 +781,32 @@ struct hciAcceptPhysicalLink {
 	uint8_t dedicatedAmpKey;
 } __packed;
 
-#define HCI_CMD_Disconnect_Physical_link                         0x0037 /* status */
+#define HCI_CMD_Disconnect_Physical_link 0x0037 /* status */
 struct hciDisconnectPhysicalLink {
 	uint8_t physLinkHandle;
 	uint8_t reason;
 } __packed;
 
-#define HCI_CMD_Create_Logical_link                              0x0038 /* status */
+#define HCI_CMD_Create_Logical_link 0x0038 /* status */
 struct hciCreateLogicalLink {
 	uint8_t physLinkHandle;
 	uint8_t txFlowSpec[16];
 	uint8_t rxFlowSpec[16];
 } __packed;
 
-#define HCI_CMD_Accept_Logical_Link                              0x0039 /* status */
+#define HCI_CMD_Accept_Logical_Link 0x0039 /* status */
 struct hciAcceptLogicalLink {
 	uint8_t physLinkHandle;
 	uint8_t txFlowSpec[16];
 	uint8_t rxFlowSpec[16];
 } __packed;
 
-#define HCI_CMD_Disconnect_Logical_link                          0x003A /* status */
+#define HCI_CMD_Disconnect_Logical_link 0x003A /* status */
 struct hciDisconnectLogicalLink {
 	uint8_t physLinkHandle;
 } __packed;
 
-#define HCI_CMD_Logical_Link_Cancel                              0x003B /* complete */
+#define HCI_CMD_Logical_Link_Cancel 0x003B /* complete */
 struct hciLogicalLinkCancel {
 	uint8_t physLinkHandle;
 	uint8_t txFlowSpecID;
@@ -718,17 +817,16 @@ struct hciCmplLogicalLinkCancel {
 	uint8_t txFlowSpecID;
 } __packed;
 
-#define HCI_CMD_Flow_Spec_Modify                                 0x003C /* status */
+#define HCI_CMD_Flow_Spec_Modify 0x003C /* status */
 struct hciFlowSpecModify {
 	uint16_t handle;
 	uint8_t txFlowSpec[16];
 	uint8_t rxFlowSpec[16];
 } __packed;
 
-
 /* ==== BT 4.1 ==== */
 
-#define HCI_CMD_Enhanced_Setup_Synchronous_Connection            0x003D /* status */
+#define HCI_CMD_Enhanced_Setup_Synchronous_Connection 0x003D /* status */
 struct hciEnhSetupSyncConn {
 	uint16_t conn;
 	uint32_t txBandwidth;
@@ -756,7 +854,7 @@ struct hciEnhSetupSyncConn {
 	uint8_t retransmissionEffort;
 } __packed;
 
-#define HCI_CMD_Enhanced_Accept_Synchronous_Connection           0x003E /* status */
+#define HCI_CMD_Enhanced_Accept_Synchronous_Connection 0x003E /* status */
 struct hciEnhAcceptSyncConn {
 	uint8_t mac[6];
 	uint32_t txBandwidth;
@@ -784,14 +882,14 @@ struct hciEnhAcceptSyncConn {
 	uint8_t retransmissionEffort;
 } __packed;
 
-#define HCI_CMD_Truncated_Page                                   0x003F /* status */
+#define HCI_CMD_Truncated_Page 0x003F /* status */
 struct hciTruncatedPage {
 	uint8_t mac[6];
 	uint8_t PSRM;
 	uint16_t clockOffset; /* possibly | HCI_CLOCK_OFST_VALID */
 } __packed;
 
-#define HCI_CMD_Truncated_Page_Cancel                            0x0040 /* complete */
+#define HCI_CMD_Truncated_Page_Cancel 0x0040 /* complete */
 struct hciTruncatedPageCancel {
 	uint8_t mac[6];
 } __packed;
@@ -800,7 +898,7 @@ struct hciCmplTruncatedPageCancel {
 	uint8_t mac[6];
 } __packed;
 
-#define HCI_CMD_Set_Connectionless_Slave_Broadcast               0x0041 /* complete */
+#define HCI_CMD_Set_Connectionless_Slave_Broadcast 0x0041 /* complete */
 struct hciSetConnectionlessSlaveBroadcast {
 	uint8_t enabled;
 	uint8_t ltAddr; /* 1..7 */
@@ -816,7 +914,9 @@ struct hciCmplSetConnectionlessSlaveBroadcast {
 	uint16_t interval;
 } __packed;
 
-#define HCI_CMD_Set_Connectionless_Slave_Broadcast_Receive       0x0042 /* complete */
+#define HCI_CMD_Set_Connectionless_Slave_Broadcast_Receive \
+	0x0042 /* complete                                 \
+		*/
 struct hciSetConnectionlessSlaveBroadcastReceive {
 	uint8_t enabled;
 	uint8_t mac[6]; /* add rof tranmitter */
@@ -836,9 +936,9 @@ struct hciCmplSetConnectionlessSlaveBroadcastReceive {
 	uint8_t ltAddr; /* 1..7 */
 } __packed;
 
-#define HCI_CMD_Start_Synchronisation_Train                      0x0043 /* status */
+#define HCI_CMD_Start_Synchronisation_Train 0x0043 /* status */
 
-#define HCI_CMD_Receive_Synchronisation_Train                    0x0044 /* status */
+#define HCI_CMD_Receive_Synchronisation_Train 0x0044 /* status */
 struct hciReceiveSyncTrain {
 	uint8_t mac[6];
 	uint16_t syncScanTimeout;
@@ -846,7 +946,7 @@ struct hciReceiveSyncTrain {
 	uint16_t syncScanInterval;
 } __packed;
 
-#define HCI_CMD_Remote_OOB_Extended_Data_Request_Reply           0x0045 /* complete */
+#define HCI_CMD_Remote_OOB_Extended_Data_Request_Reply 0x0045 /* complete */
 struct hciRemoteOobExtendedDataRequestReply {
 	uint8_t mac[6];
 	uint8_t C_192[16];
@@ -859,23 +959,18 @@ struct hciCmplRemoteOobExtendedDataRequestReply {
 	uint8_t mac[6];
 } __packed;
 
-
-
-
-
-#define HCI_OGF_Link_Policy                                      2
-
+#define HCI_OGF_Link_Policy 2
 
 /* ==== BT 1.1 ==== */
 
-#define HCI_CMD_Hold_Mode                                        0x0001 /* status */
+#define HCI_CMD_Hold_Mode 0x0001 /* status */
 struct hciHoldMode {
 	uint16_t conn;
 	uint16_t holdModeMaxInt;
 	uint16_t holdModeMinInt;
 } __packed;
 
-#define HCI_CMD_Sniff_Mode                                       0x0003 /* status */
+#define HCI_CMD_Sniff_Mode 0x0003 /* status */
 struct hciSniffMode {
 	uint16_t conn;
 	uint16_t sniffMaxInt;
@@ -884,24 +979,24 @@ struct hciSniffMode {
 	uint16_t sniffTimeout;
 } __packed;
 
-#define HCI_CMD_Exit_Sniff_Mode                                  0x0004 /* status */
+#define HCI_CMD_Exit_Sniff_Mode 0x0004 /* status */
 struct hciExitSniffMode {
 	uint16_t conn;
 } __packed;
 
-#define HCI_CMD_Park_State                                       0x0005 /* status */
+#define HCI_CMD_Park_State 0x0005 /* status */
 struct hciParkState {
 	uint16_t conn;
 	uint16_t beaconMaxInt;
 	uint16_t beaconMinInt;
 } __packed;
 
-#define HCI_CMD_Exit_Park_State                                  0x0006 /* status */
+#define HCI_CMD_Exit_Park_State 0x0006 /* status */
 struct hciExitParkState {
 	uint16_t conn;
 } __packed;
 
-#define HCI_CMD_QoS_Setup                                        0x0007 /* status */
+#define HCI_CMD_QoS_Setup 0x0007 /* status */
 struct hisQosSetup {
 	uint16_t conn;
 	uint8_t flags;
@@ -912,7 +1007,7 @@ struct hisQosSetup {
 	uint32_t delayVariation;
 } __packed;
 
-#define HCI_CMD_Role_Discovery                                   0x0009 /* complete */
+#define HCI_CMD_Role_Discovery 0x0009 /* complete */
 struct hciRoleDiscovery {
 	uint16_t conn;
 } __packed;
@@ -920,13 +1015,13 @@ struct hciCmplRoleDiscovery {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Switch_Role                                      0x000B /* status */
+#define HCI_CMD_Switch_Role 0x000B /* status */
 struct hciSwitchRole {
 	uint8_t mac[6];
 	uint8_t becomeSlave;
 } __packed;
 
-#define HCI_CMD_Read_Link_Policy_Settings                        0x000C /* complete */
+#define HCI_CMD_Read_Link_Policy_Settings 0x000C /* complete */
 struct hciReadLinkPolicySettings {
 	uint16_t conn;
 } __packed;
@@ -936,7 +1031,7 @@ struct hciCmplReadLinkPolicySettings {
 	uint16_t policy; /* HCI_LINK_POLICY_* */
 } __packed;
 
-#define HCI_CMD_Write_Link_Policy_Settings                       0x000D /* complete */
+#define HCI_CMD_Write_Link_Policy_Settings 0x000D /* complete */
 struct hciWriteLinkPolicySettings {
 	uint16_t conn;
 	uint16_t policy; /* HCI_LINK_POLICY_* */
@@ -946,16 +1041,15 @@ struct hciCmplWriteLinkPolicySettings {
 	uint16_t conn;
 } __packed;
 
-
 /* ==== BT 1.2 ==== */
 
-#define HCI_CMD_Read_Default_Link_Policy_Settings                0x000E /* complete */
+#define HCI_CMD_Read_Default_Link_Policy_Settings 0x000E /* complete */
 struct hciCmplReadDefaultLinkPolicySettings {
 	uint8_t status;
 	uint16_t policy; /* HCI_LINK_POLICY_* */
 } __packed;
 
-#define HCI_CMD_Write_Default_Link_Policy_Settings               0x000F /* complete */
+#define HCI_CMD_Write_Default_Link_Policy_Settings 0x000F /* complete */
 struct hciWriteDefaultLinkPolicySettings {
 	uint16_t policy; /* HCI_LINK_POLICY_* */
 } __packed;
@@ -963,7 +1057,7 @@ struct hciCmplWriteDefaultLinkPolicySettings {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Flow_Specification                               0x0010 /* status */
+#define HCI_CMD_Flow_Specification 0x0010 /* status */
 struct hisFlowSpecification {
 	uint16_t conn;
 	uint8_t flags;
@@ -975,10 +1069,9 @@ struct hisFlowSpecification {
 	uint32_t accessLatency;
 } __packed;
 
-
 /* ==== BT 2.1 ==== */
 
-#define HCI_CMD_Sniff_Subrating                                  0x0011 /* complete */
+#define HCI_CMD_Sniff_Subrating 0x0011 /* complete */
 struct hciSniffSubrating {
 	uint16_t conn;
 	uint16_t maxLatency;
@@ -990,16 +1083,11 @@ struct hciCmplSniffSubrating {
 	uint16_t conn;
 } __packed;
 
-
-
-
-
-#define HCI_OGF_Controller_and_Baseband                          3
-
+#define HCI_OGF_Controller_and_Baseband 3
 
 /* ==== BT 1.1 ==== */
 
-#define HCI_CMD_Set_Event_Mask                                   0x0001 /* complete */
+#define HCI_CMD_Set_Event_Mask 0x0001 /* complete */
 struct hciSetEventMask {
 	uint64_t mask; /* bitmask of HCI_EVENT_* */
 } __packed;
@@ -1007,12 +1095,12 @@ struct hciCmplSetEventMask {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Reset                                            0x0003 /* complete */
+#define HCI_CMD_Reset 0x0003 /* complete */
 struct hciCmplReset {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Set_Event_Filter                                 0x0005 /* complete */
+#define HCI_CMD_Set_Event_Filter 0x0005 /* complete */
 struct hciSetEventFilter {
 	uint8_t filterType; /* HCI_FILTER_TYPE_* */
 	/* more things are optional here */
@@ -1021,7 +1109,7 @@ struct hciCmplSetEventFiler {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Flush                                            0x0008 /* complete */
+#define HCI_CMD_Flush 0x0008 /* complete */
 struct hciFlush {
 	uint16_t conn;
 } __packed;
@@ -1030,13 +1118,13 @@ struct hciCmplFlush {
 	uint16_t conn;
 } __packed;
 
-#define HCI_CMD_Read_PIN_Type                                    0x0009 /* complete */
+#define HCI_CMD_Read_PIN_Type 0x0009 /* complete */
 struct hciCmplReadPinType {
 	uint8_t status;
 	uint8_t isFixed;
 } __packed;
 
-#define HCI_CMD_Write_PIN_Type                                   0x000A /* complete */
+#define HCI_CMD_Write_PIN_Type 0x000A /* complete */
 struct hciWritePinType {
 	uint8_t isFixed;
 } __packed;
@@ -1044,12 +1132,12 @@ struct hciCmplWritePinType {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Create_New_Unit_Key                              0x000B /* complete */
+#define HCI_CMD_Create_New_Unit_Key 0x000B /* complete */
 struct hciCmplCreateNewUnitKey {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Stored_Link_Key                             0x000D /* complete */
+#define HCI_CMD_Read_Stored_Link_Key 0x000D /* complete */
 struct hciReadStoredLinkKey {
 	uint8_t mac[6];
 	uint8_t readAll;
@@ -1060,7 +1148,7 @@ struct hciCmplReadStoredLinkKey {
 	uint16_t numKeysRead;
 } __packed;
 
-#define HCI_CMD_Write_Stored_Link_Key                            0x0011 /* complete */
+#define HCI_CMD_Write_Stored_Link_Key 0x0011 /* complete */
 struct hciWriteStoredLinkKeyItem {
 	uint8_t mac[6];
 	uint8_t key[16];
@@ -1074,7 +1162,7 @@ struct hciCmplWriteStoredLinkKey {
 	uint8_t numKeysWritten;
 } __packed;
 
-#define HCI_CMD_Delete_Stored_Link_Key                           0x0012 /* complete */
+#define HCI_CMD_Delete_Stored_Link_Key 0x0012 /* complete */
 struct hciDeleteStoredLinkKey {
 	uint8_t mac[6];
 	uint8_t deleteAll;
@@ -1084,7 +1172,7 @@ struct hciCmplDeleteStoredLinkKey {
 	uint8_t numKeysDeleted;
 } __packed;
 
-#define HCI_CMD_Write_Local_Name                                 0x0013 /* complete */
+#define HCI_CMD_Write_Local_Name 0x0013 /* complete */
 struct hciWriteLocalName {
 	char name[HCI_DEV_NAME_LEN];
 } __packed;
@@ -1092,19 +1180,19 @@ struct hciCmplWriteLocalName {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Local_Name                                  0x0014 /* complete */
+#define HCI_CMD_Read_Local_Name 0x0014 /* complete */
 struct hciCmplReadLocalName {
 	uint8_t status;
 	char name[HCI_DEV_NAME_LEN];
 } __packed;
 
-#define HCI_CMD_Read_Connection_Accept_Timeout                   0x0015 /* complete */
+#define HCI_CMD_Read_Connection_Accept_Timeout 0x0015 /* complete */
 struct hciCmplReadConnAcceptTimeout {
 	uint8_t status;
 	uint16_t timeout; /* in units of 0.625ms 1..0xB540 */
 } __packed;
 
-#define HCI_CMD_Write_Connection_Accept_Timeout                  0x0016 /* complete */
+#define HCI_CMD_Write_Connection_Accept_Timeout 0x0016 /* complete */
 struct hciWriteConnAcceptTimeout {
 	uint16_t timeout; /* in units of 0.625ms 1..0xB540 */
 } __packed;
@@ -1112,13 +1200,13 @@ struct hciCmplWriteConnAcceptTimeout {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Page_Timeout                                0x0017 /* complete */
+#define HCI_CMD_Read_Page_Timeout 0x0017 /* complete */
 struct hciCmplReadPageTimeout {
 	uint8_t status;
 	uint16_t timeout;
 } __packed;
 
-#define HCI_CMD_Write_Page_Timeout                               0x0018 /* complete */
+#define HCI_CMD_Write_Page_Timeout 0x0018 /* complete */
 struct hciWritePageTimeout {
 	uint16_t timeout;
 } __packed;
@@ -1126,13 +1214,13 @@ struct hciCmplWritePageTimeout {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Scan_Enable                                 0x0019 /* complete */
+#define HCI_CMD_Read_Scan_Enable 0x0019 /* complete */
 struct hciCmplReadScanEnable {
 	uint8_t status;
 	uint8_t state; /* bitmask of HCI_SCAN_ENABLE_* */
 } __packed;
 
-#define HCI_CMD_Write_Scan_Enable                                0x001A /* complete */
+#define HCI_CMD_Write_Scan_Enable 0x001A /* complete */
 struct hciWriteScanEnable {
 	uint8_t state; /* bitmask of HCI_SCAN_ENABLE_* */
 } __packed;
@@ -1140,14 +1228,14 @@ struct hciCmplWriteScanEnable {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Page_Scan_Activity                          0x001B /* complete */
+#define HCI_CMD_Read_Page_Scan_Activity 0x001B /* complete */
 struct hciCmplReadPageScanActivity {
 	uint8_t status;
 	uint16_t scanInterval;
 	uint16_t scanWindow;
 } __packed;
 
-#define HCI_CMD_Write_Page_Scan_Activity                         0x001C /* complete */
+#define HCI_CMD_Write_Page_Scan_Activity 0x001C /* complete */
 struct hciWritePageScanActivity {
 	uint16_t scanInterval;
 	uint16_t scanWindow;
@@ -1156,14 +1244,14 @@ struct hciCmplWritePageScanActivity {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Inquiry_Scan_Activity                       0x001D /* complete */
+#define HCI_CMD_Read_Inquiry_Scan_Activity 0x001D /* complete */
 struct hciCmplReadInquiryScanActivity {
 	uint8_t status;
 	uint16_t scanInterval;
 	uint16_t scanWindow;
 } __packed;
 
-#define HCI_CMD_Write_Inquiry_Scan_Activity                      0x001E /* complete */
+#define HCI_CMD_Write_Inquiry_Scan_Activity 0x001E /* complete */
 struct hciWriteInquiryScanActivity {
 	uint16_t scanInterval;
 	uint16_t scanWindow;
@@ -1172,13 +1260,13 @@ struct hciCmplWriteInquiryScanActivity {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Authentication_Enable                       0x001F /* complete */
+#define HCI_CMD_Read_Authentication_Enable 0x001F /* complete */
 struct hciCmplReadAuthEnable {
 	uint8_t status;
 	uint8_t authRequired;
 } __packed;
 
-#define HCI_CMD_Write_Authentication_Enable                      0x0020 /* complete */
+#define HCI_CMD_Write_Authentication_Enable 0x0020 /* complete */
 struct hciWriteAuthEnable {
 	uint8_t authRequired;
 } __packed;
@@ -1186,13 +1274,15 @@ struct hciCmplWriteAuthEnable {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Encryption_Mode                             0x0021 /* complete *//* deprecated in BT 2.1+ */
+#define HCI_CMD_Read_Encryption_Mode \
+	0x0021 /* complete */ /* deprecated in BT 2.1+ */
 struct hciCmplReadEncryptionMode {
 	uint8_t status;
 	uint8_t encrRequired;
 } __packed;
 
-#define HCI_CMD_Write_Encryption_Mode                            0x0022 /* complete *//* deprecated in BT 2.1+ */
+#define HCI_CMD_Write_Encryption_Mode \
+	0x0022 /* complete */ /* deprecated in BT 2.1+ */
 struct hciWriteEncryptionMode {
 	uint8_t encrRequired;
 } __packed;
@@ -1200,13 +1290,13 @@ struct hciCmplWriteEncryptionMode {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Class_Of_Device                             0x0023 /* complete */
+#define HCI_CMD_Read_Class_Of_Device 0x0023 /* complete */
 struct hciCmplReadClassOfDevice {
 	uint8_t status;
 	uint8_t cls[3];
 } __packed;
 
-#define HCI_CMD_Write_Class_Of_Device                            0x0024 /* complete */
+#define HCI_CMD_Write_Class_Of_Device 0x0024 /* complete */
 struct hciWriteClassOfDevice {
 	uint8_t cls[3];
 } __packed;
@@ -1214,13 +1304,13 @@ struct hciCmplWriteClassOfDevice {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Voice_Setting                               0x0025 /* complete */
+#define HCI_CMD_Read_Voice_Setting 0x0025 /* complete */
 struct hciCmplReadVoiceSetting {
 	uint8_t status;
 	uint16_t voiceSetting;
 } __packed;
 
-#define HCI_CMD_Write_Voice_Setting                              0x0026 /* complete */
+#define HCI_CMD_Write_Voice_Setting 0x0026 /* complete */
 struct hciWriteVoiceSetting {
 	uint16_t voiceSetting;
 } __packed;
@@ -1228,7 +1318,7 @@ struct hciCmplWriteVoiceSetting {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Automatic_Flush_Timeout                     0x0027 /* complete */
+#define HCI_CMD_Read_Automatic_Flush_Timeout 0x0027 /* complete */
 struct hciReadAutoFlushTimeout {
 	uint16_t conn;
 } __packed;
@@ -1238,7 +1328,7 @@ struct hciCmplReadAutoFlushTimeout {
 	uint16_t timeout;
 } __packed;
 
-#define HCI_CMD_Write_Automatic_Flush_Timeout                    0x0028 /* complete */
+#define HCI_CMD_Write_Automatic_Flush_Timeout 0x0028 /* complete */
 struct hciWriteAutoFlushTimeout {
 	uint16_t conn;
 	uint16_t timeout;
@@ -1248,13 +1338,13 @@ struct hciCmplWriteAutoFlushTimeout {
 	uint16_t conn;
 } __packed;
 
-#define HCI_CMD_Read_Num_Broadcast_Retransmissions               0x0029 /* complete */
+#define HCI_CMD_Read_Num_Broadcast_Retransmissions 0x0029 /* complete */
 struct hciCmplReadNumBroadcastRetransmissions {
 	uint8_t status;
 	uint8_t numRetransmissions; /* 0 .. 0xFE => 1 .. 255 TXes */
 } __packed;
 
-#define HCI_CMD_Write_Num_Broadcast_Retransmissions              0x002A /* complete */
+#define HCI_CMD_Write_Num_Broadcast_Retransmissions 0x002A /* complete */
 struct hciWriteNumBroadcastRetransmissions {
 	uint8_t numRetransmissions; /* 0 .. 0xFE => 1 .. 255 TXes */
 } __packed;
@@ -1262,13 +1352,13 @@ struct hciCmplWriteNumBroadcastRetransmissions {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Hold_Mode_Activity                          0x002B /* complete */
+#define HCI_CMD_Read_Hold_Mode_Activity 0x002B /* complete */
 struct hciCmplReadHoldModeActivity {
 	uint8_t status;
 	uint8_t holdModeActivity; /* bitfield if HCI_HOLD_MODE_SUSPEND_* */
 } __packed;
 
-#define HCI_CMD_Write_Hold_Mode_Activity                         0x002C /* complete */
+#define HCI_CMD_Write_Hold_Mode_Activity 0x002C /* complete */
 struct hciWriteHoldModeActivity {
 	uint8_t holdModeActivity; /* bitfield if HCI_HOLD_MODE_SUSPEND_* */
 } __packed;
@@ -1276,7 +1366,7 @@ struct hciCmplWriteHoldModeActivity {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Transmit_Power_Level                        0x002D /* complete */
+#define HCI_CMD_Read_Transmit_Power_Level 0x002D /* complete */
 struct hciReadTransmitPowerLevel {
 	uint16_t conn;
 	uint8_t max; /* else current */
@@ -1287,13 +1377,13 @@ struct hciCmplReadTransmitPowerLevel {
 	uint8_t txPower; /* actually an int8_t */
 } __packed;
 
-#define HCI_CMD_Read_SCO_Flow_Control_Enable                     0x002E /* complete */
+#define HCI_CMD_Read_SCO_Flow_Control_Enable 0x002E /* complete */
 struct hciCmplReadSyncFlowCtrl {
 	uint8_t status;
 	uint8_t syncFlowCtrlOn;
 } __packed;
 
-#define HCI_CMD_Write_SCO_Flow_Control_Enable                    0x002F /* complete */
+#define HCI_CMD_Write_SCO_Flow_Control_Enable 0x002F /* complete */
 struct hciWriteSyncFlowCtrlEnable {
 	uint8_t syncFlowCtrlOn;
 } __packed;
@@ -1301,7 +1391,7 @@ struct hciCmplWriteSyncFlowCtrlEnable {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Set_Controller_To_Host_Flow_Control              0x0031 /* complete */
+#define HCI_CMD_Set_Controller_To_Host_Flow_Control 0x0031 /* complete */
 struct hciSetControllerToHostFlowControl {
 	uint8_t chipToHostFlowCtrl; /* bitmask of HCI_TO_HOST_FLOW_CTRL_* */
 } __packed;
@@ -1309,7 +1399,7 @@ struct hciCmplSetControllerToHostFlowControl {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Host_Buffer_Size                                 0x0033 /* complete */
+#define HCI_CMD_Host_Buffer_Size 0x0033 /* complete */
 struct hciHostBufferSize {
 	uint16_t maxAclPacket;
 	uint8_t maxScoPacket;
@@ -1320,7 +1410,9 @@ struct hciCmplHostBufferSize {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Host_Number_Of_Completed_Packets                 0x0035 /* special: can be sent anytime (not subj to cmd flow control), does not generate events unless error */
+#define HCI_CMD_Host_Number_Of_Completed_Packets                               \
+	0x0035 /* special: can be sent anytime (not subj to cmd flow control), \
+		  does not generate events unless error */
 struct hciHostNumberOfCompletedPacketsItem {
 	uint16_t conn;
 	uint16_t numCompletedPackets;
@@ -1330,33 +1422,35 @@ struct hciHostNumberOfCompletedPackets {
 	struct hciHostNumberOfCompletedPacketsItem items[];
 } __packed;
 
-#define HCI_CMD_Read_Link_Supervision_Timeout                    0x0036 /* complete */
+#define HCI_CMD_Read_Link_Supervision_Timeout 0x0036 /* complete */
 struct hciReadLinkSupervisionTimeout {
 	uint16_t conn;
 } __packed;
 struct hciCmplReadLinkSupervisionTimeout {
 	uint8_t status;
 	uint16_t conn;
-	uint16_t timeout; /* in units of 0.625ms allowed: 1..0xffff, required support 0x0190 - 0xffff */
+	uint16_t timeout; /* in units of 0.625ms allowed: 1..0xffff, required
+			     support 0x0190 - 0xffff */
 } __packed;
 
-#define HCI_CMD_Write_Link_Supervision_Timeout                   0x0037 /* complete */
+#define HCI_CMD_Write_Link_Supervision_Timeout 0x0037 /* complete */
 struct hciWriteLinkSupervisionTimeout {
 	uint16_t conn;
-	uint16_t timeout; /* in units of 0.625ms allowed: 1..0xffff, required support 0x0190 - 0xffff */
+	uint16_t timeout; /* in units of 0.625ms allowed: 1..0xffff, required
+			     support 0x0190 - 0xffff */
 } __packed;
 struct hciCmplWriteLinkSupervisionTimeout {
 	uint8_t status;
 	uint16_t conn;
 } __packed;
 
-#define HCI_CMD_Read_Number_Of_Supported_IAC                     0x0038 /* complete */
+#define HCI_CMD_Read_Number_Of_Supported_IAC 0x0038 /* complete */
 struct hciCmplReadNumberOfSupportedIac {
 	uint8_t status;
 	uint8_t numSupportedIac;
 } __packed;
 
-#define HCI_CMD_Read_Current_IAC_LAP                             0x0039 /* complete */
+#define HCI_CMD_Read_Current_IAC_LAP 0x0039 /* complete */
 struct hciCmplReadCurrentIacItem {
 	uint8_t iac_lap[3];
 } __packed;
@@ -1366,7 +1460,7 @@ struct hciCmplReadCurrentIac {
 	struct hciCmplReadCurrentIacItem items[];
 } __packed;
 
-#define HCI_CMD_Write_Current_IAC_LAP                            0x003A /* complete */
+#define HCI_CMD_Write_Current_IAC_LAP 0x003A /* complete */
 struct hciWriteCurrentIacLapItem {
 	uint8_t iacLap[3];
 } __packed;
@@ -1378,13 +1472,13 @@ struct hciCmplWriteCurrentIacLap {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Page_Scan_Period_Mode                       0x003B /* complete */
+#define HCI_CMD_Read_Page_Scan_Period_Mode 0x003B /* complete */
 struct hciCmplReadPageScanPeriodMode {
 	uint8_t status;
 	uint8_t mode;
 } __packed;
 
-#define HCI_CMD_Write_Page_Scan_Period_Mode                      0x003C /* complete */
+#define HCI_CMD_Write_Page_Scan_Period_Mode 0x003C /* complete */
 struct hciWritePageScanPeriodMode {
 	uint8_t mode;
 } __packed;
@@ -1392,13 +1486,15 @@ struct hciCmplWritePageScanPeriodMode {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Page_Scan_Mode                              0x003D  /* complete *//* deprecated in BT 1.2+ */
+#define HCI_CMD_Read_Page_Scan_Mode \
+	0x003D /* complete */ /* deprecated in BT 1.2+ */
 struct hciCmplReadPageScanMode {
 	uint8_t status;
 	uint8_t pageScanMode; /* nonzero modes are optional */
 } __packed;
 
-#define HCI_CMD_Write_Page_Scan_Mode                             0x003E  /* complete *//* deprecated in BT 1.2+ */
+#define HCI_CMD_Write_Page_Scan_Mode \
+	0x003E /* complete */ /* deprecated in BT 1.2+ */
 struct hciWritePageScanMode {
 	uint8_t pageScanMode; /* nonzero modes are optional */
 } __packed;
@@ -1406,10 +1502,9 @@ struct hciCmplWritePageScanMode {
 	uint8_t status;
 } __packed;
 
-
 /* ==== BT 1.2 ==== */
 
-#define HCI_CMD_Set_AFH_Host_Channel_Classification              0x003F /* complete */
+#define HCI_CMD_Set_AFH_Host_Channel_Classification 0x003F /* complete */
 struct hciSetAfhHostChannelClassification {
 	uint8_t channels[10];
 } __packed;
@@ -1417,13 +1512,13 @@ struct hciCmplSetAfhHostChannelClassification {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Inquiry_Scan_Type                           0x0042 /* complete */
+#define HCI_CMD_Read_Inquiry_Scan_Type 0x0042 /* complete */
 struct hciCmplReadInquiryScanType {
 	uint8_t status;
 	uint8_t interlaced; /* optional */
 } __packed;
 
-#define HCI_CMD_Write_Inquiry_Scan_Type                          0x0043 /* complete */
+#define HCI_CMD_Write_Inquiry_Scan_Type 0x0043 /* complete */
 struct hciWriteInquiryScanType {
 	uint8_t interlaced; /* optional */
 } __packed;
@@ -1431,13 +1526,13 @@ struct hciCmplWriteInquiryScanType {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Inquiry_Mode                                0x0044 /* complete */
+#define HCI_CMD_Read_Inquiry_Mode 0x0044 /* complete */
 struct hciCmplReadInquryMode {
 	uint8_t status;
 	uint8_t inqMode; /* HCI_INQ_MODE_* */
 } __packed;
 
-#define HCI_CMD_Write_Inquiry_Mode                               0x0045 /* complete */
+#define HCI_CMD_Write_Inquiry_Mode 0x0045 /* complete */
 struct hciWriteInquiryMode {
 	uint8_t inqMode; /* HCI_INQ_MODE_* */
 } __packed;
@@ -1445,13 +1540,13 @@ struct hciCmplWriteInquiryMode {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Page_Scan_Type                              0x0046 /* complete */
+#define HCI_CMD_Read_Page_Scan_Type 0x0046 /* complete */
 struct hciCmplReadPageScanType {
 	uint8_t status;
 	uint8_t interlaced; /* optional */
 } __packed;
 
-#define HCI_CMD_Write_Page_Scan_Type                             0x0047 /* complete */
+#define HCI_CMD_Write_Page_Scan_Type 0x0047 /* complete */
 struct hciWritePageScanType {
 	uint8_t interlaced; /* optional */
 } __packed;
@@ -1459,13 +1554,13 @@ struct hciCmplWritePageScanType {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_AFH_Channel_Assessment_Mode                 0x0048 /* complete */
+#define HCI_CMD_Read_AFH_Channel_Assessment_Mode 0x0048 /* complete */
 struct hciCmplReadAfhChannelAssessment {
 	uint8_t status;
 	uint8_t channelAssessmentEnabled;
 } __packed;
 
-#define HCI_CMD_Write_AFH_Channel_Assessment_Mode                0x0049 /* complete */
+#define HCI_CMD_Write_AFH_Channel_Assessment_Mode 0x0049 /* complete */
 struct hciWriteAfhChannelAssessment {
 	uint8_t channelAssessmentEnabled;
 } __packed;
@@ -1473,17 +1568,16 @@ struct hciCmplWriteAfhChannelAssessment {
 	uint8_t status;
 } __packed;
 
-
 /* ==== BT 2.1 ==== */
 
-#define HCI_CMD_Read_Extended_Inquiry_Response                   0x0051 /* complete */
+#define HCI_CMD_Read_Extended_Inquiry_Response 0x0051 /* complete */
 struct hciCmplReadEIR {
 	uint8_t status;
 	uint8_t useFec;
 	uint8_t data[240];
 } __packed;
 
-#define HCI_CMD_Write_Extended_Inquiry_Response                  0x0052 /* complete */
+#define HCI_CMD_Write_Extended_Inquiry_Response 0x0052 /* complete */
 struct hciWriteEIR {
 	uint8_t useFec;
 	uint8_t data[240];
@@ -1492,18 +1586,18 @@ struct hciCmplWriteEIR {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Refresh_Encryption_Key                           0x0052 /* status */
+#define HCI_CMD_Refresh_Encryption_Key 0x0052 /* status */
 struct hciRefreshEncryptionKey {
 	uint16_t conn;
 } __packed;
 
-#define HCI_CMD_Read_Simple_Pairing_Mode                         0x0055 /* complete */
+#define HCI_CMD_Read_Simple_Pairing_Mode 0x0055 /* complete */
 struct hciCmplReadSimplePairingMore {
 	uint8_t status;
 	uint8_t useSsp;
 } __packed;
 
-#define HCI_CMD_Write_Simple_Pairing_Mode                        0x0056 /* complete */
+#define HCI_CMD_Write_Simple_Pairing_Mode 0x0056 /* complete */
 struct hciWriteSimplePairingMode {
 	uint8_t useSsp;
 } __packed;
@@ -1511,20 +1605,22 @@ struct hciCmplWriteSimplePairingMode {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Local_OOB_Data                              0x0057 /* complete */
+#define HCI_CMD_Read_Local_OOB_Data 0x0057 /* complete */
 struct hciCmplReadLocalOobData {
 	uint8_t status;
 	uint8_t C[16];
 	uint8_t R[16];
 } __packed;
 
-#define HCI_CMD_Read_Inquiry_Response_Transmit_Power_Level       0x0058 /* complete */
+#define HCI_CMD_Read_Inquiry_Response_Transmit_Power_Level \
+	0x0058 /* complete                                 \
+		*/
 struct hciCmplReadInquiryTransmitPowerLevel {
 	uint8_t status;
 	uint8_t power; /* actually an int8_t */
 } __packed;
 
-#define HCI_CMD_Write_Inquiry_Transmit_Power_Level               0x0059 /* complete */
+#define HCI_CMD_Write_Inquiry_Transmit_Power_Level 0x0059 /* complete */
 struct hciWriteInquiryTransmitPowerLevel {
 	uint8_t power; /* actually an int8_t */
 } __packed;
@@ -1532,13 +1628,13 @@ struct hciCmplWriteInquiryTransmitPowerLevel {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Default_Erroneous_Data_Reporting            0x005A /* complete */
+#define HCI_CMD_Read_Default_Erroneous_Data_Reporting 0x005A /* complete */
 struct hciCmplReadErroneousDataReporting {
 	uint8_t status;
 	uint8_t reportingEnabled;
 } __packed;
 
-#define HCI_CMD_Write_Default_Erroneous_Data_Reporting           0x005B /* complete */
+#define HCI_CMD_Write_Default_Erroneous_Data_Reporting 0x005B /* complete */
 struct hciWriteErroneousDataReporting {
 	uint8_t reportingEnabled;
 } __packed;
@@ -1546,13 +1642,14 @@ struct hciCmplWriteErroneousDataReporting {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Enhanced_Flush                                   0x005F /* status */
+#define HCI_CMD_Enhanced_Flush 0x005F /* status */
 struct hciEnhancedFlush {
 	uint16_t conn;
-	uint8_t which; /* 0 is the only value - flush auto-flushable packets only */
+	uint8_t which; /* 0 is the only value - flush auto-flushable packets
+			  only */
 } __packed;
 
-#define HCI_CMD_Send_Keypress_Notification                       0x0060 /* complete */
+#define HCI_CMD_Send_Keypress_Notification 0x0060 /* complete */
 struct hciSendKeypressNotification {
 	uint8_t mac[6];
 	uint8_t notifType; /* HCI_SSP_KEY_ENTRY_* */
@@ -1562,24 +1659,25 @@ struct hciCmplSendKeypressNotification {
 	uint8_t mac[6];
 } __packed;
 
-
 /* ==== BT 3.0 ==== */
 
-#define HCI_CMD_Read_Logical_Link_Accept_Timeout                 0x0061 /* complete */
+#define HCI_CMD_Read_Logical_Link_Accept_Timeout 0x0061 /* complete */
 struct hciCmplReadLogicalLinkTimeout {
 	uint8_t status;
-	uint16_t timeout; /* in units of 0.625ms 1..0xB540. Required support 0x00A0..0xB540 */
+	uint16_t timeout; /* in units of 0.625ms 1..0xB540. Required support
+			     0x00A0..0xB540 */
 } __packed;
 
-#define HCI_CMD_Write_Logical_Link_Accept_Timeout                0x0062 /* complete */
+#define HCI_CMD_Write_Logical_Link_Accept_Timeout 0x0062 /* complete */
 struct hciWriteLogicalLinkTimeout {
-	uint16_t timeout; /* in units of 0.625ms 1..0xB540. Required support 0x00A0..0xB540 */
+	uint16_t timeout; /* in units of 0.625ms 1..0xB540. Required support
+			     0x00A0..0xB540 */
 } __packed;
 struct hciCmplWriteLogicalLinkTimeout {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Set_Event_Mask_Page_2                            0x0063 /* complete */
+#define HCI_CMD_Set_Event_Mask_Page_2 0x0063 /* complete */
 struct hciSetEventMaskPage2 {
 	uint64_t mask; /* bitmask of HCI_EVENT_P2_* */
 } __packed;
@@ -1587,7 +1685,7 @@ struct hciCmplSetEventMaskPage2 {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Location_Data                               0x0064 /* complete */
+#define HCI_CMD_Read_Location_Data 0x0064 /* complete */
 struct hciCmplReadLocationData {
 	uint8_t status;
 	uint8_t regulatoryDomainKnown;
@@ -1596,7 +1694,7 @@ struct hciCmplReadLocationData {
 	uint8_t mainsPowered;
 } __packed;
 
-#define HCI_CMD_Write_Location_Data                              0x0065 /* complete */
+#define HCI_CMD_Write_Location_Data 0x0065 /* complete */
 struct hciWriteLocationData {
 	uint8_t regulatoryDomainKnown;
 	uint16_t domain; /* ISO3166-1 code if known, else 0x5858 'XX' */
@@ -1607,21 +1705,23 @@ struct hciCmplWriteLocationData {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Flow_Control_Mode                           0x0066 /* complete */
+#define HCI_CMD_Read_Flow_Control_Mode 0x0066 /* complete */
 struct hciCmplReadFlowControlMode {
 	uint8_t status;
-	uint8_t blockBased; /* block based is for amp, packed-based is for BR/EDR */
+	uint8_t blockBased; /* block based is for amp, packed-based is for
+			       BR/EDR */
 } __packed;
 
-#define HCI_CMD_Write_Flow_Control_mode                          0x0067 /* complete */
+#define HCI_CMD_Write_Flow_Control_mode 0x0067 /* complete */
 struct hciWriteFlowControlMode {
-	uint8_t blockBased; /* block based is for amp, packed-based is for BR/EDR */
+	uint8_t blockBased; /* block based is for amp, packed-based is for
+			       BR/EDR */
 } __packed;
 struct hciCmplWriteFlowcontrolMode {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Enhanced_Transmit_Power_Level               0x0068 /* complete */
+#define HCI_CMD_Read_Enhanced_Transmit_Power_Level 0x0068 /* complete */
 struct hciReadEnhancedTransmitPowerLevel {
 	uint16_t conn;
 	uint8_t max; /* else currurent is read */
@@ -1634,7 +1734,7 @@ struct hciCmplReadEnhancedTransmitPowerLevel {
 	uint8_t txLevel8DPSK; /* actually an int8_t */
 } __packed;
 
-#define HCI_CMD_Read_Best_Effort_Flush_Timeout                   0x0069 /* complete */
+#define HCI_CMD_Read_Best_Effort_Flush_Timeout 0x0069 /* complete */
 struct hciReadBestEffortFlushTimeout {
 	uint16_t logicalLinkHandle;
 } __packed;
@@ -1643,7 +1743,7 @@ struct hciCmplReadBestEffortFlushTimeout {
 	uint32_t bestEffortFlushTimeout; /* in microseconds */
 } __packed;
 
-#define HCI_CMD_Write_Best_Effort_Flush_Timeout                  0x006A /* complete */
+#define HCI_CMD_Write_Best_Effort_Flush_Timeout 0x006A /* complete */
 struct hciWriteBestEffortFlushTimeout {
 	uint16_t logicalLinkHandle;
 	uint32_t bestEffortFlushTimeout; /* in microseconds */
@@ -1652,23 +1752,22 @@ struct hciCmplWriteBestEffortFlushTimeout {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Short_Range_Mode                                 0x006B /* status */
+#define HCI_CMD_Short_Range_Mode 0x006B /* status */
 struct hciShortRangeMode {
 	uint8_t physicalLinkHandle;
 	uint8_t shortRangeModeEnabled;
 } __packed;
 
-
 /* ==== BT 4.0 ==== */
 
-#define HCI_CMD_Read_LE_Host_Supported                           0x006C /* complete */
+#define HCI_CMD_Read_LE_Host_Supported 0x006C /* complete */
 struct hciCmplReadLeHostSupported {
 	uint8_t status;
 	uint8_t leSupportedHost;
 	uint8_t simultaneousLeHost;
 } __packed;
 
-#define HCI_CMD_Write_LE_Host_Supported                          0x006D /* complete */
+#define HCI_CMD_Write_LE_Host_Supported 0x006D /* complete */
 struct hciWriteLeHostSupported {
 	uint8_t leSupportedHost;
 	uint8_t simultaneousLeHost;
@@ -1677,10 +1776,9 @@ struct hciCmplWriteLeHostSupported {
 	uint8_t status;
 } __packed;
 
-
 /* ==== BT 4.1 ==== */
 
-#define HCI_CMD_Set_MWS_Channel_Parameters                       0x006E /* complete */
+#define HCI_CMD_Set_MWS_Channel_Parameters 0x006E /* complete */
 struct hciSetMwsChannelParams {
 	uint8_t mwsEnabled;
 	uint16_t mwsChannelRxCenterFreq; /* in MHz */
@@ -1693,7 +1791,7 @@ struct hciCmplSetMwsChannelParams {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Set_External_Frame_Configuration                 0x006F /* complete */
+#define HCI_CMD_Set_External_Frame_Configuration 0x006F /* complete */
 struct hciSetExternalFrameConfigItem {
 	uint16_t periodDuration; /* in microseconds */
 	uint8_t periodType; /* HCI_PERIOD_TYPE_* */
@@ -1709,7 +1807,7 @@ struct hciCmplSetExternalFrameConfig {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Set_MWS_Signalling                               0x0070 /* complete */
+#define HCI_CMD_Set_MWS_Signalling 0x0070 /* complete */
 struct hciSetMwsSignalling {
 	uint16_t mwsRxAssertOffset; /* all of these are in microseconds */
 	uint16_t mwsRxAssertJitter;
@@ -1747,7 +1845,7 @@ struct hciCmplSetMwsSignalling {
 	uint16_t _802TxOnDeassertJitter;
 } __packed;
 
-#define HCI_CMD_Set_MWS_Transport_Layer                          0x0071 /* complete */
+#define HCI_CMD_Set_MWS_Transport_Layer 0x0071 /* complete */
 struct hciSetMwsTransportLayer {
 	uint8_t transportLayer;
 	uint32_t toMwsBaudRate; /* in byte/sec */
@@ -1757,7 +1855,7 @@ struct hciCmplSetMwsTransportLayer {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Set_MWS_Scan_Frequency_Table                     0x0072 /* complete */
+#define HCI_CMD_Set_MWS_Scan_Frequency_Table 0x0072 /* complete */
 struct hciSetMwsScanFrequencyTableItem {
 	uint16_t scanFreqLow; /*in MHz */
 	uint16_t scanFreqHigh; /*in MHz */
@@ -1770,7 +1868,7 @@ struct hciCmplSetMwsScanFrequencyTable {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Set_MWS_PATTERN_Configuration                    0x0073 /* complete */
+#define HCI_CMD_Set_MWS_PATTERN_Configuration 0x0073 /* complete */
 struct hciSetMwsPatternConfigItem {
 	uint16_t intervalDuration; /* in microseconds */
 	uint8_t intervalType; /* HCI_MWS_INTERVAL_TYPE_* */
@@ -1784,7 +1882,7 @@ struct hciCmplSetMwsPatternConfig {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Set_Reserved_LT_ADDR                             0x0074 /* complete */
+#define HCI_CMD_Set_Reserved_LT_ADDR 0x0074 /* complete */
 struct hciSetReservedLtAddr {
 	uint8_t ltAddr;
 } __packed;
@@ -1793,7 +1891,7 @@ struct hciCmplSetReservedLtAddr {
 	uint8_t ltAddr;
 } __packed;
 
-#define HCI_CMD_Delete_Reserved_LT_ADDR                          0x0075 /* complete */
+#define HCI_CMD_Delete_Reserved_LT_ADDR 0x0075 /* complete */
 struct hciDeleteReservedLtAddr {
 	uint8_t ltAddr;
 } __packed;
@@ -1802,7 +1900,7 @@ struct hciCmplDeleteReservedLtAddr {
 	uint8_t ltAddr;
 } __packed;
 
-#define HCI_CMD_Set_Connectionless_Slave_Broadcast_Data          0x0076 /* complete */
+#define HCI_CMD_Set_Connectionless_Slave_Broadcast_Data 0x0076 /* complete */
 struct hciSetConnlessSlaveBroadcastData {
 	uint8_t ltAddr;
 	uint8_t fragment; /* HCI_CONNLESS_FRAG_TYPE_* */
@@ -1814,7 +1912,7 @@ struct hciCmplSetConnlessSlaveBroadcastData {
 	uint8_t ltAddr;
 } __packed;
 
-#define HCI_CMD_Read_Synchronisation_Train_Parameters            0x0077 /* complete */
+#define HCI_CMD_Read_Synchronisation_Train_Parameters 0x0077 /* complete */
 struct hciCmplReadSyncTrainParams {
 	uint8_t status;
 	uint16_t interval;
@@ -1822,7 +1920,7 @@ struct hciCmplReadSyncTrainParams {
 	uint8_t serviceData;
 } __packed;
 
-#define HCI_CMD_Write_Synchronisation_Train_Parameters           0x0078 /* complete */
+#define HCI_CMD_Write_Synchronisation_Train_Parameters 0x0078 /* complete */
 struct hciWriteSyncTrainParams {
 	uint16_t intMin;
 	uint16_t intMax;
@@ -1834,13 +1932,13 @@ struct hciCmplWriteSyncTrainParams {
 	uint16_t interval;
 } __packed;
 
-#define HCI_CMD_Read_Secure_Connections_Host_Support             0x0079 /* complete */
+#define HCI_CMD_Read_Secure_Connections_Host_Support 0x0079 /* complete */
 struct hciCmplReadSecureConnectionsHostSupport {
 	uint8_t status;
 	uint8_t secureConnectionsSupported;
 } __packed;
 
-#define HCI_CMD_Write_Secure_Connections_Host_Support            0x007A /* complete */
+#define HCI_CMD_Write_Secure_Connections_Host_Support 0x007A /* complete */
 struct hciWriteSecureConnectionsHostSupport {
 	uint8_t secureConnectionsSupported;
 } __packed;
@@ -1848,7 +1946,7 @@ struct hciCmplWriteSecureConnectionsHostSupport {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Authenticated_Payload_Timeout               0x007B /* complete */
+#define HCI_CMD_Read_Authenticated_Payload_Timeout 0x007B /* complete */
 struct hciReadAuthedPayloadTimeout {
 	uint16_t conn;
 } __packed;
@@ -1858,7 +1956,7 @@ struct hciCmplReadAuthedPayloadTimeout {
 	uint16_t timeout; /* in units of 10ms, 1 .. 0xffff */
 } __packed;
 
-#define HCI_CMD_Write_Authenticated_Payload_Timeout              0x007C /* complete */
+#define HCI_CMD_Write_Authenticated_Payload_Timeout 0x007C /* complete */
 struct hciWriteAuthedPayloadTimeout {
 	uint16_t conn;
 	uint16_t timeout; /* in units of 10ms, 1 .. 0xffff */
@@ -1868,7 +1966,7 @@ struct hciCmplWriteAuthedPayloadTimeout {
 	uint16_t conn;
 } __packed;
 
-#define HCI_CMD_Read_Local_OOB_Extended_Data                     0x007D /* complete */
+#define HCI_CMD_Read_Local_OOB_Extended_Data 0x007D /* complete */
 struct hciCmplReadLocalOobExtendedData {
 	uint8_t status;
 	uint8_t C_192[16];
@@ -1877,13 +1975,13 @@ struct hciCmplReadLocalOobExtendedData {
 	uint8_t R_256[16];
 } __packed;
 
-#define HCI_CMD_Read_Extended_Page_Timeout                       0x007E /* complete */
+#define HCI_CMD_Read_Extended_Page_Timeout 0x007E /* complete */
 struct hciCmplReadExtendedPageTimeout {
 	uint8_t status;
 	uint16_t timeout; /* in units of 0.625ms 0..0xffff */
 } __packed;
 
-#define HCI_CMD_Write_Extended_Page_Timeout                      0x007F /* complete */
+#define HCI_CMD_Write_Extended_Page_Timeout 0x007F /* complete */
 struct hciWriteExtendedPageTimeout {
 	uint16_t timeout; /* in units of 0.625ms 0..0xffff */
 } __packed;
@@ -1891,13 +1989,13 @@ struct hciCmplWriteExtendedPageTimeout {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Extended_Inquiry_Length                     0x0080 /* complete */
+#define HCI_CMD_Read_Extended_Inquiry_Length 0x0080 /* complete */
 struct hciCmplReadExtendedInquiryLength {
 	uint8_t status;
 	uint16_t timeout; /* in units of 0.625ms 0..0xffff */
 } __packed;
 
-#define HCI_CMD_Write_Extended_Inquiry_Length                    0x0081 /* complete */
+#define HCI_CMD_Write_Extended_Inquiry_Length 0x0081 /* complete */
 struct hciWriteExtendedInquiryLength {
 	uint16_t timeout; /* in units of 0.625ms 0..0xffff */
 } __packed;
@@ -1905,16 +2003,11 @@ struct hciCmplWriteExtendedInquiryLength {
 	uint8_t status;
 } __packed;
 
-
-
-
-
-#define HCI_OGF_Informational                                    4
-
+#define HCI_OGF_Informational 4
 
 /* ==== BT 1.1 ==== */
 
-#define HCI_CMD_Read_Local_Version_Information                   0x0001 /* complete */
+#define HCI_CMD_Read_Local_Version_Information 0x0001 /* complete */
 struct hciCmplReadLocalVersion {
 	uint8_t status;
 	uint8_t hciVersion; /* HCI_VERSION_* */
@@ -1924,19 +2017,19 @@ struct hciCmplReadLocalVersion {
 	uint16_t lmpSubversion;
 } __packed;
 
-#define HCI_CMD_Read_Local_Supported_Commands                    0x0002 /* complete */
+#define HCI_CMD_Read_Local_Supported_Commands 0x0002 /* complete */
 struct hciCmplReadLocalSupportedCommands {
 	uint8_t status;
 	uint64_t bitfield;
 } __packed;
 
-#define HCI_CMD_Read_Local_Supported_Features                    0x0003 /* complete */
+#define HCI_CMD_Read_Local_Supported_Features 0x0003 /* complete */
 struct hciCmplReadLocalSupportedFeatures {
 	uint8_t status;
-	uint64_t features;  /* bitmask of HCI_LMP_FTR_* */
+	uint64_t features; /* bitmask of HCI_LMP_FTR_* */
 } __packed;
 
-#define HCI_CMD_Read_Local_Extended_Features                     0x0004 /* complete */
+#define HCI_CMD_Read_Local_Extended_Features 0x0004 /* complete */
 struct hciReadLocalExtendedFeatures {
 	uint8_t page;
 } __packed;
@@ -1947,7 +2040,7 @@ struct hciCmplReadLocalExtendedFeatures {
 	uint64_t features; /* bitmask of HCI_LMP_EXT_FTR_P* */
 } __packed;
 
-#define HCI_CMD_Read_Buffer_Size                                 0x0005 /* complete */
+#define HCI_CMD_Read_Buffer_Size 0x0005 /* complete */
 struct hciCmplReadBufferSize {
 	uint8_t status;
 	uint16_t aclBufferLen;
@@ -1956,16 +2049,15 @@ struct hciCmplReadBufferSize {
 	uint16_t numScoBuffers;
 } __packed;
 
-#define HCI_CMD_Read_BD_ADDR                                     0x0009 /* complete */
+#define HCI_CMD_Read_BD_ADDR 0x0009 /* complete */
 struct hciCmplReadBdAddr {
 	uint8_t status;
 	uint8_t mac[6];
 } __packed;
 
-
 /* ==== BT 3.0 ==== */
 
-#define HCI_CMD_Read_Data_Block_Size                             0x000A /* complete */
+#define HCI_CMD_Read_Data_Block_Size 0x000A /* complete */
 struct hciCmplReadDataBlockSize {
 	uint8_t status;
 	uint16_t maxAclDataPacketLen;
@@ -1973,30 +2065,24 @@ struct hciCmplReadDataBlockSize {
 	uint16_t totalNumDataBlocks;
 } __packed;
 
-
 /* ==== BT 4.1 ==== */
 
-#define HCI_CMD_Read_Local_Supported_Codecs                      0x000B /* complete */
+#define HCI_CMD_Read_Local_Supported_Codecs 0x000B /* complete */
 struct hciCmplReadLocalSupportedCodecs {
 	uint8_t status;
 	uint8_t numSupportedCodecs;
 	uint8_t codecs[];
-/* these follow, but due to var array cannot be declared here:
-	uint8_t numVendorCodecs;
-	uint32_t vendorCodecs[];
-*/
+	/* these follow, but due to var array cannot be declared here:
+		uint8_t numVendorCodecs;
+		uint32_t vendorCodecs[];
+	*/
 } __packed;
 
-
-
-
-
-#define HCI_OGF_Status                                           5
-
+#define HCI_OGF_Status 5
 
 /* == BT 1.1 == */
 
-#define HCI_CMD_Read_Failed_Contact_Counter                      0x0001 /* complete */
+#define HCI_CMD_Read_Failed_Contact_Counter 0x0001 /* complete */
 struct hciReadFailedContactCounter {
 	uint16_t conn;
 } __packed;
@@ -2006,7 +2092,7 @@ struct hciCmplReadFailedContactCounter {
 	uint16_t counter;
 } __packed;
 
-#define HCI_CMD_Reset_Failed_Contact_Counter                     0x0002 /* complete */
+#define HCI_CMD_Reset_Failed_Contact_Counter 0x0002 /* complete */
 struct hciResetFailedContactCounter {
 	uint16_t conn;
 } __packed;
@@ -2015,7 +2101,7 @@ struct hciCmplResetFailedContactCounter {
 	uint16_t conn;
 } __packed;
 
-#define HCI_CMD_Read_Link_Quality                                0x0003 /* complete */
+#define HCI_CMD_Read_Link_Quality 0x0003 /* complete */
 struct hciReadLinkQuality {
 	uint16_t conn;
 } __packed;
@@ -2025,7 +2111,7 @@ struct hciCmplReadLinkQuality {
 	uint8_t quality;
 } __packed;
 
-#define HCI_CMD_Read_RSSI                                        0x0005 /* complete */
+#define HCI_CMD_Read_RSSI 0x0005 /* complete */
 struct hciReadRssi {
 	uint16_t conn;
 } __packed;
@@ -2035,10 +2121,9 @@ struct hciCmplReadRssi {
 	uint8_t RSSI; /* actually an int8_t */
 } __packed;
 
-
 /* ==== BT 1.2 ==== */
 
-#define HCI_CMD_Read_AFH_Channel_Map                             0x0006 /* complete */
+#define HCI_CMD_Read_AFH_Channel_Map 0x0006 /* complete */
 struct hciReadAfhChannelMap {
 	uint16_t conn;
 } __packed;
@@ -2048,7 +2133,7 @@ struct hciCmplReadAfhChannelMap {
 	uint8_t map[10];
 } __packed;
 
-#define HCI_CMD_Read_Clock                                       0x0007 /* complete */
+#define HCI_CMD_Read_Clock 0x0007 /* complete */
 struct hciReadClock {
 	uint16_t conn;
 	uint8_t readRemote; /* else reads local and ignores conn */
@@ -2060,10 +2145,9 @@ struct hciCmplReadClock {
 	uint16_t accuracy;
 } __packed;
 
-
 /* ==== BT 3.0 ==== */
 
-#define HCI_CMD_Read_Encryption_Key_Size                         0x0008 /* complete */
+#define HCI_CMD_Read_Encryption_Key_Size 0x0008 /* complete */
 struct hciReadEncrKeySize {
 	uint16_t conn;
 } __packed;
@@ -2073,7 +2157,7 @@ struct hciCmplReadEncrKeySize {
 	uint8_t keySize;
 } __packed;
 
-#define HCI_CMD_Read_Local_AMP_Info                              0x0009 /* complete */
+#define HCI_CMD_Read_Local_AMP_Info 0x0009 /* complete */
 struct hciCmplReadLocalAmpInfo {
 	uint8_t status;
 	uint8_t ampStatus;
@@ -2088,7 +2172,7 @@ struct hciCmplReadLocalAmpInfo {
 	uint32_t bestEffortFlushTimeout;
 } __packed;
 
-#define HCI_CMD_Read_Local_AMP_ASSOC                             0x000A /* complete */
+#define HCI_CMD_Read_Local_AMP_ASSOC 0x000A /* complete */
 struct hciReadLocalAmpAssoc {
 	uint8_t physicalLinkHandle;
 	uint16_t lengthSoFar;
@@ -2101,7 +2185,7 @@ struct hciCmplReadLocalAmpAssoc {
 	uint8_t ampAssocFragment[]; /* 1.. 248 byutes */
 } __packed;
 
-#define HCI_CMD_Write_Remote_AMP_ASSOC                           0x000B /* complete */
+#define HCI_CMD_Write_Remote_AMP_ASSOC 0x000B /* complete */
 struct hciWriteRemoteAmpAssoc {
 	uint8_t physicalLinkHandle;
 	uint16_t lengthSoFar;
@@ -2115,7 +2199,7 @@ struct hciCmplWriteRemoteAmpAssoc {
 
 /* ==== BT 4.1 ==== */
 
-#define HCI_CMD_Get_MWS_Transport_Layer_Configuration            0x000C /* complete */
+#define HCI_CMD_Get_MWS_Transport_Layer_Configuration 0x000C /* complete */
 struct hciCmplGetMwsTransportLayerConfigItem {
 	uint8_t transportLayer;
 	uint8_t numBaudRates;
@@ -2127,13 +2211,15 @@ struct hciCmplGetMwsTransportLayerConfigBandwidthItem {
 struct hciCmplGetMwsTransportLayerConfig {
 	uint8_t status;
 	uint8_t numTransports;
-	struct hciCmplGetMwsTransportLayerConfigItem items[]; /* numTransports items */
-/* this follows:
-	struct hciCmplGetMwsTransportLayerConfigBandwidthItem items[] // sum(items[].numbaudRates) items
-*/
+	struct hciCmplGetMwsTransportLayerConfigItem items[]; /* numTransports
+								 items */
+	/* this follows:
+		struct hciCmplGetMwsTransportLayerConfigBandwidthItem items[] //
+	   sum(items[].numbaudRates) items
+	*/
 } __packed;
 
-#define HCI_CMD_Set_Triggered_Clock_Capture                      0x000D /* complete */
+#define HCI_CMD_Set_Triggered_Clock_Capture 0x000D /* complete */
 struct hciSetTriggeredClockCapture {
 	uint16_t conn;
 	uint8_t enable;
@@ -2145,16 +2231,11 @@ struct hciCmplSetTriggeredClockCapture {
 	uint8_t status;
 } __packed;
 
-
-
-
-
-#define HCI_OGF_LE                                               8
-
+#define HCI_OGF_LE 8
 
 /* ==== BT 4.0 ==== */
 
-#define HCI_CMD_LE_Set_Event_Mask                                0x0001 /* complete */
+#define HCI_CMD_LE_Set_Event_Mask 0x0001 /* complete */
 struct hciLeSetEventMask {
 	uint64_t events; /* bitmask of HCI_LE_EVENT_* */
 } __packed;
@@ -2162,28 +2243,28 @@ struct hciCmplLeSetEventMask {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_LE_Read_Buffer_Size                              0x0002 /* complete */
+#define HCI_CMD_LE_Read_Buffer_Size 0x0002 /* complete */
 struct hciCmplLeReadBufferSize {
 	uint8_t status;
 	uint16_t leBufferSize;
 	uint8_t leNumBuffers;
 } __packed;
 
-#define HCI_CMD_LE_Read_Local_Supported_Features                 0x0003 /* complete */
+#define HCI_CMD_LE_Read_Local_Supported_Features 0x0003 /* complete */
 struct hciCmplLeReadLocalSupportedFeatures {
 	uint8_t status;
 	uint64_t leFeatures; /* bitmask of HCI_LE_FTR_* */
 } __packed;
 
-#define HCI_CMD_LE_Set_Random_Address                            0x0005 /* complete */
-struct hciLeSetRandomAddress{
+#define HCI_CMD_LE_Set_Random_Address 0x0005 /* complete */
+struct hciLeSetRandomAddress {
 	uint8_t mac[6];
 } __packed;
-struct hciCmplLeSetRandomAddress{
+struct hciCmplLeSetRandomAddress {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_LE_Set_Adv_Params                                0x0006 /* complete */
+#define HCI_CMD_LE_Set_Adv_Params 0x0006 /* complete */
 struct hciLeSetAdvParams {
 	uint16_t advIntervalMin;
 	uint16_t advIntervalMax;
@@ -2198,13 +2279,13 @@ struct hciCmplLeSetAdvParams {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_LE_Read_Adv_Channel_TX_Power                     0x0007 /* complete */
+#define HCI_CMD_LE_Read_Adv_Channel_TX_Power 0x0007 /* complete */
 struct hciCmplLeReadAdvChannelTxPower {
 	uint8_t status;
 	uint8_t txPower; /* actually an int8_t */
 } __packed;
 
-#define HCI_CMD_LE_Set_Advertising_Data                          0x0008 /* complete */
+#define HCI_CMD_LE_Set_Advertising_Data 0x0008 /* complete */
 struct hciLeSetAdvData {
 	uint8_t advDataLen;
 	uint8_t advData[31];
@@ -2213,7 +2294,7 @@ struct hciCmplLeSetAdvData {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_LE_Set_Scan_Response_Data                        0x0009 /* complete */
+#define HCI_CMD_LE_Set_Scan_Response_Data 0x0009 /* complete */
 struct hciSetScanResponseData {
 	uint8_t scanRspDataLen;
 	uint8_t scanRspData[31];
@@ -2222,7 +2303,7 @@ struct hciCmplSetScanResponseData {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_LE_Set_Advertise_Enable                          0x000A /* complete */
+#define HCI_CMD_LE_Set_Advertise_Enable 0x000A /* complete */
 struct hciLeSetAdvEnable {
 	uint8_t advOn;
 } __packed;
@@ -2230,7 +2311,7 @@ struct hciCmplLeSetAdvEnable {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_LE_Set_Scan_Parameters                           0x000B /* complete */
+#define HCI_CMD_LE_Set_Scan_Parameters 0x000B /* complete */
 struct hciLeSetScanParams {
 	uint8_t activeScan;
 	uint16_t scanInterval; /* in units of 0.625ms, 4..0x4000 */
@@ -2242,7 +2323,7 @@ struct hciCmplLeSetScanParams {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_LE_Set_Scan_Enable                               0x000C /* complete */
+#define HCI_CMD_LE_Set_Scan_Enable 0x000C /* complete */
 struct hciLeSetScanEnable {
 	uint8_t scanOn;
 	uint8_t filterDuplicates;
@@ -2251,7 +2332,7 @@ struct hciCmplLeSetScanEnable {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_LE_Create_Connection                             0x000D /* status */
+#define HCI_CMD_LE_Create_Connection 0x000D /* status */
 struct hciLeCreateConnection {
 	uint16_t scanInterval; /* in units of 0.625ms, 4..0x4000 */
 	uint16_t scanWindow; /* in units of 0.625ms, 4..0x4000 */
@@ -2263,27 +2344,29 @@ struct hciLeCreateConnection {
 	uint16_t connIntervalMax; /* in units of 1.25ms, 6..0x0C80 */
 	uint16_t connLatency; /* 0..0x1F4 */
 	uint16_t supervisionTimeout; /* in units of 10ms, 0xA...0x0C80 */
-	uint16_t minConnLen; /* minimum conn len needed in units of 0.625ms 0..0xfff */
-	uint16_t maxConnLen; /* minimum conn len needed in units of 0.625ms 0..0xfff */
+	uint16_t minConnLen; /* minimum conn len needed in units of 0.625ms
+				0..0xfff */
+	uint16_t maxConnLen; /* minimum conn len needed in units of 0.625ms
+				0..0xfff */
 } __packed;
 
-#define HCI_CMD_LE_Create_Connection_Cancel                      0x000E /* complete */
+#define HCI_CMD_LE_Create_Connection_Cancel 0x000E /* complete */
 struct hciCmplLeCreateConnectionCancel {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_LE_Read_Allow_List_Size                          0x000F /* complete */
+#define HCI_CMD_LE_Read_Allow_List_Size 0x000F /* complete */
 struct hciCmplLeReadAllowListSize {
 	uint8_t status;
 	uint8_t allowlistSize;
 } __packed;
 
-#define HCI_CMD_LE_Clear_Allow_List                              0x0010 /* complete */
+#define HCI_CMD_LE_Clear_Allow_List 0x0010 /* complete */
 struct hciCmplLeClearAllowList {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_LE_Add_Device_To_Allow_List                      0x0011 /* complete */
+#define HCI_CMD_LE_Add_Device_To_Allow_List 0x0011 /* complete */
 struct hciLeAddDeviceToAllowList {
 	uint8_t randomAddr;
 	uint8_t mac[6];
@@ -2292,7 +2375,7 @@ struct hciCmplLeAddDeviceToAllowList {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_LE_Remove_Device_From_Allow_List                 0x0012 /* complete */
+#define HCI_CMD_LE_Remove_Device_From_Allow_List 0x0012 /* complete */
 struct hciLeRemoveDeviceFromAllowList {
 	uint8_t randomAddr;
 	uint8_t mac[6];
@@ -2301,18 +2384,20 @@ struct hciCmplLeRemoveDeviceFromAllowList {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_LE_Connection_Update                             0x0013 /* status */
+#define HCI_CMD_LE_Connection_Update 0x0013 /* status */
 struct hciLeConnectionUpdate {
 	uint16_t conn;
 	uint16_t connIntervalMin; /* in units of 1.25ms, 6..0x0C80 */
 	uint16_t connIntervalMax; /* in units of 1.25ms, 6..0x0C80 */
 	uint16_t connLatency; /* 0..0x1F4 */
 	uint16_t supervisionTimeout; /* in units of 10ms, 0xA...0x0C80 */
-	uint16_t minConnLen; /* minimum conn len needed in units of 0.625ms 0..0xfff */
-	uint16_t maxConnLen; /* minimum conn len needed in units of 0.625ms 0..0xfff */
+	uint16_t minConnLen; /* minimum conn len needed in units of 0.625ms
+				0..0xfff */
+	uint16_t maxConnLen; /* minimum conn len needed in units of 0.625ms
+				0..0xfff */
 } __packed;
 
-#define HCI_CMD_LE_Set_Host_Channel_Classification               0x0014 /* complete */
+#define HCI_CMD_LE_Set_Host_Channel_Classification 0x0014 /* complete */
 struct hciLeSetHostChannelClassification {
 	uint8_t chMap[5];
 } __packed;
@@ -2320,7 +2405,7 @@ struct hciCmplLeSetHostChannelClassification {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_LE_Read_Channel_Map                              0x0015 /* complete */
+#define HCI_CMD_LE_Read_Channel_Map 0x0015 /* complete */
 struct hciLeReadChannelMap {
 	uint16_t conn;
 } __packed;
@@ -2330,12 +2415,12 @@ struct hciCmplLeReadChannelMap {
 	uint8_t chMap[5];
 } __packed;
 
-#define HCI_CMD_LE_Read_Remote_Used_Features                     0x0016 /* status */
+#define HCI_CMD_LE_Read_Remote_Used_Features 0x0016 /* status */
 struct hciLeReadRemoteUsedFeatures {
 	uint16_t conn;
 } __packed;
 
-#define HCI_CMD_LE_Encrypt                                       0x0017 /* complete */
+#define HCI_CMD_LE_Encrypt 0x0017 /* complete */
 struct hciLeEncrypt {
 	uint8_t key[16];
 	uint8_t plaintext[16];
@@ -2345,13 +2430,13 @@ struct hciCmplLeEncrypt {
 	uint8_t encryptedData[16];
 } __packed;
 
-#define HCI_CMD_LE_Rand                                          0x0018 /* complete */
+#define HCI_CMD_LE_Rand 0x0018 /* complete */
 struct hciCmplLeRand {
 	uint8_t status;
 	uint64_t rand;
 } __packed;
 
-#define HCI_CMD_LE_Start_Encryption                              0x0019 /* status */
+#define HCI_CMD_LE_Start_Encryption 0x0019 /* status */
 struct hciLeStartEncryption {
 	uint16_t conn;
 	uint64_t rand;
@@ -2359,7 +2444,7 @@ struct hciLeStartEncryption {
 	uint8_t LTK[16];
 } __packed;
 
-#define HCI_CMD_LE_LTK_Request_Reply                             0x001A /* complete */
+#define HCI_CMD_LE_LTK_Request_Reply 0x001A /* complete */
 struct hciLeLtkRequestReply {
 	uint16_t conn;
 	uint8_t LTK[16];
@@ -2369,7 +2454,7 @@ struct hciCmplLeLtkRequestReply {
 	uint16_t conn;
 } __packed;
 
-#define HCI_CMD_LE_LTK_Request_Negative_Reply                    0x001B /* complete */
+#define HCI_CMD_LE_LTK_Request_Negative_Reply 0x001B /* complete */
 struct hciLeLtkRequestNegativeReply {
 	uint16_t conn;
 } __packed;
@@ -2378,13 +2463,13 @@ struct hciCmplLeLtkRequestNegativeReply {
 	uint16_t conn;
 } __packed;
 
-#define HCI_CMD_LE_Read_Supported_States                         0x001C /* complete */
+#define HCI_CMD_LE_Read_Supported_States 0x001C /* complete */
 struct hciCmplLeReadSupportedStates {
 	uint8_t status;
 	uint64_t states; /* bitmask of HCI_LE_STATE_* */
 } __packed;
 
-#define HCI_CMD_LE_Receiver_Test                                 0x001D /* complete */
+#define HCI_CMD_LE_Receiver_Test 0x001D /* complete */
 struct hciLeReceiverTest {
 	uint8_t radioChannelNum; /* 2402 + radioChannelNum * 2 MHz */
 } __packed;
@@ -2392,7 +2477,7 @@ struct hciCmplLeReceiverTest {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_LE_Transmitter_Test                              0x001E /* complete */
+#define HCI_CMD_LE_Transmitter_Test 0x001E /* complete */
 struct hciLeTransmitterTest {
 	uint8_t radioChannelNum; /* 2402 + radioChannelNum * 2 MHz */
 	uint8_t lengthOfTestData;
@@ -2402,31 +2487,33 @@ struct hciCmplLeTransmitterTest {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_LE_Test_End                                      0x001F /* complete */
+#define HCI_CMD_LE_Test_End 0x001F /* complete */
 struct hciCmplLeTestEnd {
 	uint8_t status;
 	uint16_t numPackets;
 } __packed;
 
-
 /* ==== BT 4.1 ==== */
 
-#define HCI_CMD_LE_Remote_Conn_Param_Request_Reply               0x0020 /* complete */
+#define HCI_CMD_LE_Remote_Conn_Param_Request_Reply 0x0020 /* complete */
 struct hciLeRemoteConnParamRequestReply {
 	uint16_t conn;
 	uint16_t connIntervalMin; /* in units of 1.25ms, 6..0x0C80 */
 	uint16_t connIntervalMax; /* in units of 1.25ms, 6..0x0C80 */
 	uint16_t connLatency; /* 0..0x1F4 */
 	uint16_t supervisionTimeout; /* in units of 10ms, 0xA...0x0C80 */
-	uint16_t minConnLen; /* minimum conn len needed in units of 0.625ms 0..0xfff */
-	uint16_t maxConnLen; /* minimum conn len needed in units of 0.625ms 0..0xfff */
+	uint16_t minConnLen; /* minimum conn len needed in units of 0.625ms
+				0..0xfff */
+	uint16_t maxConnLen; /* minimum conn len needed in units of 0.625ms
+				0..0xfff */
 } __packed;
 struct hciCmplLeRemoteConnParamRequestReply {
 	uint8_t status;
 	uint16_t conn;
 } __packed;
 
-#define HCI_CMD_LE_Remote_Conn_Param_Request_Negative_Reply      0x0021 /* complete */
+#define HCI_CMD_LE_Remote_Conn_Param_Request_Negative_Reply \
+	0x0021 /* complete */
 struct hciRemoteConnParamRequestNegativeReply {
 	uint16_t conn;
 	uint8_t reason;
@@ -2436,19 +2523,16 @@ struct hciCmplLeRemoteConnParamRequestNegativeReply {
 	uint16_t conn;
 } __packed;
 
-
-
 /* EVENTS */
 
-
 /* ==== BT 1.1 ==== */
 
-#define HCI_EVT_Inquiry_Complete                                 0x01
+#define HCI_EVT_Inquiry_Complete 0x01
 struct hciEvtInquiryComplete {
 	uint8_t status;
 } __packed;
 
-#define HCI_EVT_Inquiry_Result                                   0x02
+#define HCI_EVT_Inquiry_Result 0x02
 struct hciEvtInquiryResultItem {
 	uint8_t mac[6];
 	uint8_t PSRM;
@@ -2462,7 +2546,7 @@ struct hciEvtInquiryResult {
 	struct hciEvtInquiryResultItem items[];
 } __packed;
 
-#define HCI_EVT_Connection_Complete                              0x03
+#define HCI_EVT_Connection_Complete 0x03
 struct hciEvtConnComplete {
 	uint8_t status;
 	uint16_t conn;
@@ -2471,61 +2555,61 @@ struct hciEvtConnComplete {
 	uint8_t encrypted;
 } __packed;
 
-#define HCI_EVT_Connection_Request                               0x04
+#define HCI_EVT_Connection_Request 0x04
 struct hciEvtConnRequest {
 	uint8_t mac[6];
 	uint8_t deviceClass[3];
 	uint8_t isAclLink;
 } __packed;
 
-#define HCI_EVT_Disconnection_Complete                           0x05
+#define HCI_EVT_Disconnection_Complete 0x05
 struct hciEvtDiscComplete {
 	uint8_t status;
 	uint16_t conn;
 	uint8_t reason;
 } __packed;
 
-#define HCI_EVT_Authentication_Complete                          0x06
+#define HCI_EVT_Authentication_Complete 0x06
 struct hciEvtAuthComplete {
 	uint8_t status;
 	uint16_t handle;
 } __packed;
 
-#define HCI_EVT_Remote_Name_Request_Complete                     0x07
+#define HCI_EVT_Remote_Name_Request_Complete 0x07
 struct hciEvtRemoteNameReqComplete {
 	uint8_t status;
 	uint8_t mac[6];
 	char name[HCI_DEV_NAME_LEN];
 } __packed;
 
-#define HCI_EVT_Encryption_Change                                0x08
+#define HCI_EVT_Encryption_Change 0x08
 struct hciEvtEncrChange {
 	uint8_t status;
 	uint16_t conn;
 	uint8_t encrOn;
 } __packed;
 
-#define HCI_EVT_Change_Connection_Link_Key_Complete              0x09
+#define HCI_EVT_Change_Connection_Link_Key_Complete 0x09
 struct hciEvtChangeConnLinkKeyComplete {
 	uint8_t status;
 	uint16_t handle;
 } __packed;
 
-#define HCI_EVT_Master_Link_Key_Complete                         0x0A
+#define HCI_EVT_Master_Link_Key_Complete 0x0A
 struct hciEvtMasterLinkKeyComplete {
 	uint8_t status;
 	uint16_t conn;
 	uint8_t usingTempKey; /* else using semi-permanent key */
 } __packed;
 
-#define HCI_EVT_Read_Remote_Supported_Features_Complete          0x0B
+#define HCI_EVT_Read_Remote_Supported_Features_Complete 0x0B
 struct hciEvtReadRemoteSupportedFeaturesComplete {
 	uint8_t status;
 	uint16_t conn;
 	uint64_t lmpFeatures; /* bitmask of HCI_LMP_FTR_* */
 } __packed;
 
-#define HCI_EVT_Read_Remote_Version_Complete                     0x0C
+#define HCI_EVT_Read_Remote_Version_Complete 0x0C
 struct hciEvtReadRemoteVersionComplete {
 	uint8_t status;
 	uint16_t conn;
@@ -2534,7 +2618,7 @@ struct hciEvtReadRemoteVersionComplete {
 	uint16_t lmpSubversion;
 } __packed;
 
-#define HCI_EVT_QOS_Setup_Complete                               0x0D
+#define HCI_EVT_QOS_Setup_Complete 0x0D
 struct hciEvtQosSetupComplete {
 	uint8_t status;
 	uint16_t conn;
@@ -2546,37 +2630,37 @@ struct hciEvtQosSetupComplete {
 	uint32_t delayVariation;
 } __packed;
 
-#define HCI_EVT_Command_Complete                                 0x0E
+#define HCI_EVT_Command_Complete 0x0E
 struct hciEvtCmdComplete {
 	uint8_t numCmdCredits;
 	uint16_t opcode;
 } __packed;
 
-#define HCI_EVT_Command_Status                                   0x0F
+#define HCI_EVT_Command_Status 0x0F
 struct hciEvtCmdStatus {
 	uint8_t status;
 	uint8_t numCmdCredits;
 	uint16_t opcode;
 } __packed;
 
-#define HCI_EVT_Hardware_Error                                   0x10
+#define HCI_EVT_Hardware_Error 0x10
 struct hciEvtHwError {
 	uint8_t errCode;
 } __packed;
 
-#define HCI_EVT_Flush_Occurred                                   0x11
+#define HCI_EVT_Flush_Occurred 0x11
 struct hciEvtFlushOccurred {
 	uint16_t conn;
 } __packed;
 
-#define HCI_EVT_Role_Change                                      0x12
+#define HCI_EVT_Role_Change 0x12
 struct hciEvtRoleChange {
 	uint8_t status;
 	uint8_t mac[6];
 	uint8_t amSlave;
 } __packed;
 
-#define HCI_EVT_Number_Of_Completed_Packets                      0x13
+#define HCI_EVT_Number_Of_Completed_Packets 0x13
 struct hciEvtNumCompletedPacketsItem {
 	uint16_t conn;
 	uint16_t numPackets;
@@ -2586,7 +2670,7 @@ struct hciEvtNumCompletedPackets {
 	struct hciEvtNumCompletedPacketsItem items[];
 } __packed;
 
-#define HCI_EVT_Mode_Change                                      0x14
+#define HCI_EVT_Mode_Change 0x14
 struct hciEvtModeChange {
 	uint8_t status;
 	uint16_t conn;
@@ -2594,7 +2678,7 @@ struct hciEvtModeChange {
 	uint16_t interval; /* in units of 0.625ms 0..0xffff */
 } __packed;
 
-#define HCI_EVT_Return_Link_Keys                                 0x15
+#define HCI_EVT_Return_Link_Keys 0x15
 struct hciEvtReturnLinkKeysItem {
 	uint8_t mac[6];
 	uint8_t key[16];
@@ -2604,72 +2688,71 @@ struct hciEvtReturnLinkKeys {
 	struct hciEvtReturnLinkKeysItem items[];
 } __packed;
 
-#define HCI_EVT_PIN_Code_Request                                 0x16
+#define HCI_EVT_PIN_Code_Request 0x16
 struct hciEvtPinCodeReq {
 	uint8_t mac[6];
 } __packed;
 
-#define HCI_EVT_Link_Key_Request                                 0x17
+#define HCI_EVT_Link_Key_Request 0x17
 struct hciEvtLinkKeyReq {
 	uint8_t mac[6];
 } __packed;
 
-#define HCI_EVT_Link_Key_Notification                            0x18
+#define HCI_EVT_Link_Key_Notification 0x18
 struct hciEvtLinkKeyNotif {
 	uint8_t mac[6];
 	uint8_t key[16];
 	uint8_t keyType; /* HCI_KEY_TYPE_ */
 } __packed;
 
-#define HCI_EVT_Loopback_Command                                 0x19
+#define HCI_EVT_Loopback_Command 0x19
 /* data is the sent command, up to 252 bytes of it */
 
-#define HCI_EVT_Data_Buffer_Overflow                             0x1A
+#define HCI_EVT_Data_Buffer_Overflow 0x1A
 struct hciEvtDataBufferOverflow {
 	uint8_t aclLink;
 } __packed;
 
-#define HCI_EVT_Max_Slots_Change                                 0x1B
+#define HCI_EVT_Max_Slots_Change 0x1B
 struct hciEvtMaxSlotsChange {
 	uint16_t conn;
 	uint8_t lmpMaxSlots;
 } __packed;
 
-#define HCI_EVT_Read_Clock_Offset_Complete                       0x1C
+#define HCI_EVT_Read_Clock_Offset_Complete 0x1C
 struct hciEvtReadClockOffsetComplete {
 	uint8_t status;
 	uint16_t conn;
 	uint16_t clockOffset;
 } __packed;
 
-#define HCI_EVT_Connection_Packet_Type_Changed                   0x1D
+#define HCI_EVT_Connection_Packet_Type_Changed 0x1D
 struct hciEvtConnPacketTypeChanged {
 	uint8_t status;
 	uint16_t conn;
 	uint16_t packetsAllowed; /* HCI_PKT_TYP_* */
 } __packed;
 
-#define HCI_EVT_QoS_Violation                                    0x1E
+#define HCI_EVT_QoS_Violation 0x1E
 struct hciEvtQosViolation {
 	uint16_t conn;
 } __packed;
 
-#define HCI_EVT_Page_Scan_Mode_Change                            0x1F /* deprecated in BT 1.2+ */
+#define HCI_EVT_Page_Scan_Mode_Change 0x1F /* deprecated in BT 1.2+ */
 struct hciEvtPsmChange {
 	uint8_t mac[6];
 	uint8_t PSM;
 } __packed;
 
-#define HCI_EVT_Page_Scan_Repetition_Mode_Change                 0x20
+#define HCI_EVT_Page_Scan_Repetition_Mode_Change 0x20
 struct hciEvtPrsmChange {
 	uint8_t mac[6];
 	uint8_t PSRM;
 } __packed;
 
-
 /* ==== BT 1.2 ==== */
 
-#define HCI_EVT_Flow_Specification_Complete                      0x21
+#define HCI_EVT_Flow_Specification_Complete 0x21
 struct hciEvtFlowSpecComplete {
 	uint8_t status;
 	uint16_t conn;
@@ -2681,7 +2764,7 @@ struct hciEvtFlowSpecComplete {
 	uint32_t latency;
 } __packed;
 
-#define HCI_EVT_Inquiry_Result_With_RSSI                         0x22
+#define HCI_EVT_Inquiry_Result_With_RSSI 0x22
 struct hciEvtInquiryResultWithRssiItem {
 	uint8_t mac[6];
 	uint8_t PSRM;
@@ -2695,7 +2778,7 @@ struct hciEvtInquiryResultWithRssi {
 	struct hciEvtInquiryResultWithRssiItem items[];
 } __packed;
 
-#define HCI_EVT_Read_Remote_Extended_Features_Complete           0x23
+#define HCI_EVT_Read_Remote_Extended_Features_Complete 0x23
 struct hciEvtReadRemoteExtFeturesComplete {
 	uint8_t status;
 	uint16_t conn;
@@ -2704,7 +2787,7 @@ struct hciEvtReadRemoteExtFeturesComplete {
 	uint64_t extLmpFeatures; /* HCI_LMP_EXT_FTR_P* & HCI_LMP_FTR_* */
 } __packed;
 
-#define HCI_EVT_Synchronous_Connection_Complete                  0x2C
+#define HCI_EVT_Synchronous_Connection_Complete 0x2C
 struct hciEvtSyncConnComplete {
 	uint8_t status;
 	uint16_t conn;
@@ -2717,7 +2800,7 @@ struct hciEvtSyncConnComplete {
 	uint8_t airMode; /* HCI_SCO_AIR_MODE_* */
 } __packed;
 
-#define HCI_EVT_Synchronous_Connection_Changed                   0x2D
+#define HCI_EVT_Synchronous_Connection_Changed 0x2D
 struct hciEvtSyncConnChanged {
 	uint8_t status;
 	uint16_t conn;
@@ -2727,10 +2810,9 @@ struct hciEvtSyncConnChanged {
 	uint16_t txPacketLen;
 } __packed;
 
-
 /* ==== BT 2.1 ==== */
 
-#define HCI_EVT_Sniff_Subrating                                  0x2E
+#define HCI_EVT_Sniff_Subrating 0x2E
 struct hciEvtSniffSubrating {
 	uint8_t status;
 	uint16_t conn;
@@ -2740,7 +2822,7 @@ struct hciEvtSniffSubrating {
 	uint16_t minLocalTimeout;
 } __packed;
 
-#define HCI_EVT_Extended_Inquiry_Result                          0x2F
+#define HCI_EVT_Extended_Inquiry_Result 0x2F
 struct hciEvtExtendedInquiryResult {
 	uint8_t numResponses; /* must be 1 */
 	uint8_t mac[6];
@@ -2752,18 +2834,18 @@ struct hciEvtExtendedInquiryResult {
 	uint8_t EIR[240];
 } __packed;
 
-#define HCI_EVT_Encryption_Key_Refresh_Complete                  0x30
+#define HCI_EVT_Encryption_Key_Refresh_Complete 0x30
 struct hciEvtEncrKeyRefreshComplete {
 	uint8_t status;
 	uint16_t conn;
 } __packed;
 
-#define HCI_EVT_IO_Capability_Request                            0x31
+#define HCI_EVT_IO_Capability_Request 0x31
 struct hciEvtIoCapRequest {
 	uint8_t mac[6];
 } __packed;
 
-#define HCI_EVT_IO_Capability_Response                           0x32
+#define HCI_EVT_IO_Capability_Response 0x32
 struct hciEvtIoCapResponse {
 	uint8_t mac[6];
 	uint8_t ioCapability; /* HCI_DISPLAY_CAP_* */
@@ -2771,90 +2853,89 @@ struct hciEvtIoCapResponse {
 	uint8_t authReqments; /* HCI_AUTH_REQMENT_ */
 } __packed;
 
-#define HCI_EVT_User_Confirmation_Request                        0x33
+#define HCI_EVT_User_Confirmation_Request 0x33
 struct hciEvtUserConfRequest {
 	uint8_t mac[6];
 	uint32_t numericValue;
 } __packed;
 
-#define HCI_EVT_User_Passkey_Request                             0x34
+#define HCI_EVT_User_Passkey_Request 0x34
 struct hciEvtUserPasskeyRequest {
 	uint8_t mac[6];
 } __packed;
 
-#define HCI_EVT_Remote_OOB_Data_Request                          0x35
+#define HCI_EVT_Remote_OOB_Data_Request 0x35
 struct hciEvtRemoteOobRequest {
 	uint8_t mac[6];
 } __packed;
 
-#define HCI_EVT_Simple_Pairing_Complete                          0x36
+#define HCI_EVT_Simple_Pairing_Complete 0x36
 struct hciEvtSimplePairingComplete {
 	uint8_t status;
 	uint8_t mac[6];
 } __packed;
 
-#define HCI_EVT_Link_Supervision_Timeout_Changed                 0x38
+#define HCI_EVT_Link_Supervision_Timeout_Changed 0x38
 struct hciEvtLinkSupervisionTimeoutChanged {
 	uint16_t conn;
 	uint16_t timeout; /* in units of 0.625 ms 1..0xffff */
 } __packed;
 
-#define HCI_EVT_Enhanced_Flush_Complete                          0x39
+#define HCI_EVT_Enhanced_Flush_Complete 0x39
 struct hciEvtEnahncedFlushComplete {
 	uint16_t conn;
 } __packed;
 
-#define HCI_EVT_User_Passkey_Notification                        0x3B
+#define HCI_EVT_User_Passkey_Notification 0x3B
 struct hciEvtUserPasskeyNotif {
 	uint8_t mac[6];
 	uint32_t passkey;
 } __packed;
 
-#define HCI_EVT_Keypress_Notification                            0x3C
+#define HCI_EVT_Keypress_Notification 0x3C
 struct hciEvtKeypressNotification {
 	uint8_t mac[6];
 	uint8_t notifType; /* HCI_SSP_KEY_ENTRY_* */
 } __packed;
 
-#define HCI_EVT_Remote_Host_Supported_Features_Notification      0x3D
+#define HCI_EVT_Remote_Host_Supported_Features_Notification 0x3D
 struct hciEvtRemoteHostSupportedFeatures {
 	uint8_t mac[6];
 	uint64_t hostSupportedFeatures; /* HCI_LMP_FTR_* */
 } __packed;
 
-
 /* ==== BT 3.0 ==== */
 
-#define HCI_EVT_Physical_Link_Complete                           0x40
+#define HCI_EVT_Physical_Link_Complete 0x40
 struct hciEvtPhysLinkComplete {
 	uint8_t status;
 	uint8_t physLinkHandle;
 } __packed;
 
-#define HIC_EVT_Channel_Selected                                 0x41
+#define HIC_EVT_Channel_Selected 0x41
 struct hciEvtChannelSelected {
 	uint8_t physLinkHandle;
 } __packed;
 
-#define HCI_EVT_Disconnection_Physical_Link_Complete             0x42
+#define HCI_EVT_Disconnection_Physical_Link_Complete 0x42
 struct hciEvtDiscPhysLinkComplete {
 	uint8_t status;
 	uint8_t physLinkHandle;
 	uint8_t reason;
 } __packed;
 
-#define HCI_EVT_Physical_Link_Loss_Early_Warning                 0x43
+#define HCI_EVT_Physical_Link_Loss_Early_Warning 0x43
 struct hciEvtDiscPhysLinkLossEralyWarning {
 	uint8_t physLinkHandle;
 	uint8_t lossReason;
 } __packed;
 
-#define HCI_EVT_Physical_Link_Recovery                           0x44
+#define HCI_EVT_Physical_Link_Recovery 0x44
 struct hciEvtDiscPhysLinkRecovery {
 	uint8_t physLinkHandle;
 } __packed;
 
-#define HCI_EVT_Logical_Link_Complete                            0x45
+#define HCI_EVT_Logical_Link_Complete 0x45
 struct hciEvtLogicalLinkComplete {
 	uint8_t status;
 	uint16_t logicalLinkHandle;
@@ -2862,20 +2943,20 @@ struct hciEvtLogicalLinkComplete {
 	uint8_t txFlowSpecID;
 } __packed;
 
-#define HCI_EVT_Disconnection_Logical_Link_Complete              0x46
+#define HCI_EVT_Disconnection_Logical_Link_Complete 0x46
 struct hciEvtDiscLogicalLinkComplete {
 	uint8_t status;
 	uint16_t logicalLinkHandle;
 	uint8_t reason;
 } __packed;
 
-#define HCI_EVT_Flow_Spec_Modify_Complete                        0x47
+#define HCI_EVT_Flow_Spec_Modify_Complete 0x47
 struct hciEvtFlowSpecModifyComplete {
 	uint8_t status;
 	uint16_t conn;
 } __packed;
 
-#define HCI_EVT_Number_Of_Completed_Data_Blocks                  0x48
+#define HCI_EVT_Number_Of_Completed_Data_Blocks 0x48
 struct hciEvtNumCompletedDataBlocksItem {
 	uint16_t conn;
 	uint16_t numPackets;
@@ -2886,19 +2967,19 @@ struct hciEvtNumCompletedDataBlocks {
 	struct hciEvtNumCompletedDataBlocksItem items[];
 } __packed;
 
-#define HCI_EVT_AMP_Start_Test                                   0x49
+#define HCI_EVT_AMP_Start_Test 0x49
 struct hciEvtAmpStartTest {
 	uint8_t status;
 	uint8_t scenario;
 } __packed;
 
-#define HCI_EVT_AMP_Test_End                                     0x4A
+#define HCI_EVT_AMP_Test_End 0x4A
 struct hciEvtAmpTestEnd {
 	uint8_t status;
 	uint8_t scenario;
 } __packed;
 
-#define HCI_EVT_AMP_Receiver_Report                              0x4B
+#define HCI_EVT_AMP_Receiver_Report 0x4B
 struct hciEvtampReceiverReport {
 	uint8_t controllerType;
 	uint8_t reason;
@@ -2909,28 +2990,27 @@ struct hciEvtampReceiverReport {
 	uint32_t numberOfErrorBits;
 } __packed;
 
-#define HCI_EVT_Short_Range_Mode_Change_Complete                 0x4C
+#define HCI_EVT_Short_Range_Mode_Change_Complete 0x4C
 struct hciEvtshortRangeModeChangeComplete {
 	uint8_t status;
 	uint8_t physLinkHandle;
 	uint8_t shortRangeModeOn;
 } __packed;
 
-#define HCI_EVT_AMP_Status_Change                                0x4D
+#define HCI_EVT_AMP_Status_Change 0x4D
 struct hciEvtAmpStatusChange {
 	uint8_t status;
 	uint8_t ampStatus;
 } __packed;
 
-
 /* ==== BT 4.0 ==== */
 
-#define HCI_EVT_LE_Meta                                          0x3E
+#define HCI_EVT_LE_Meta 0x3E
 struct hciEvtLeMeta {
 	uint8_t subevent;
 } __packed;
 
-#define HCI_EVTLE_Connection_Complete                            0x01
+#define HCI_EVTLE_Connection_Complete 0x01
 struct hciEvtLeConnectionComplete {
 	uint8_t status;
 	uint16_t conn;
@@ -2943,21 +3023,23 @@ struct hciEvtLeConnectionComplete {
 	uint8_t masterClockAccuracy; /* HCI_MCA_* */
 } __packed;
 
-#define HCI_EVTLE_Advertising_Report                             0x02
+#define HCI_EVTLE_Advertising_Report 0x02
 struct hciEvtLeAdvReportItem {
 	uint8_t advType; /* HCI_ADV_TYPE_* */
 	uint8_t randomAddr;
 	uint8_t mac[6];
 	uint8_t dataLen;
 	uint8_t data[];
-/*  int8_t RSSI <-- this cannot be here due to variable data len, but in reality it is there */
+	/*  int8_t RSSI <-- this cannot be here due to variable data len, but in
+	 * reality it is there */
 } __packed;
 struct hciEvtLeAdvReport {
 	uint8_t numReports;
-	/* struct hciEvtLeAdvReportItem items[]; <- this cannot be here since data length is variable */
+	/* struct hciEvtLeAdvReportItem items[]; <- this cannot be here since
+	 * data length is variable */
 } __packed;
 
-#define HCI_EVTLE_Connection_Update_Complete                     0x03
+#define HCI_EVTLE_Connection_Update_Complete 0x03
 struct hciEvtLeConnectionUpdateComplete {
 	uint8_t status;
 	uint16_t conn;
@@ -2966,24 +3048,23 @@ struct hciEvtLeConnectionUpdateComplete {
 	uint16_t supervisionTimeout; /* inunit sof 10ms, 0xA..0x0C80 */
 } __packed;
 
-#define HCI_EVTLE_Read_Remote_Used_Features_Complete             0x04
+#define HCI_EVTLE_Read_Remote_Used_Features_Complete 0x04
 struct hciEvtLeReadRemoteFeaturesComplete {
 	uint8_t status;
 	uint16_t conn;
 	uint64_t leFeatures; /* bitmask of HCI_LE_FTR_* */
 } __packed;
 
-#define HCI_EVTLE_LTK_Request                                    0x05
+#define HCI_EVTLE_LTK_Request 0x05
 struct hciEvtLeLtkRequest {
 	uint16_t conn;
 	uint64_t randomNum;
 	uint16_t diversifier;
 } __packed;
 
-
 /* ==== BT 4.1 ==== */
 
-#define HCI_EVTLE_Read_Remote_Connection_Parameter_Request       0x06
+#define HCI_EVTLE_Read_Remote_Connection_Parameter_Request 0x06
 struct hciEvtLeReadRemoteConnParamRequest {
 	uint16_t conn;
 	uint16_t connIntervalMin; /* in units of 1.25 ms 6..0x0C80 */
@@ -2992,7 +3073,7 @@ struct hciEvtLeReadRemoteConnParamRequest {
 	uint16_t supervisionTimeout; /* inunit sof 10ms, 0xA..0x0C80 */
 } __packed;
 
-#define HCI_EVT_Triggered_Clock_Capture                          0x4E
+#define HCI_EVT_Triggered_Clock_Capture 0x4E
 struct hciEvtTriggeredClockCapture {
 	uint16_t conn;
 	uint8_t piconetClock;
@@ -3000,12 +3081,12 @@ struct hciEvtTriggeredClockCapture {
 	uint16_t slotOffset;
 } __packed;
 
-#define HCI_EVT_Synchronization_Train_Complete                   0x4F
+#define HCI_EVT_Synchronization_Train_Complete 0x4F
 struct hciEvtSyncTrainComplete {
 	uint8_t status;
 } __packed;
 
-#define HCI_EVT_Synchronization_Train_Received                   0x50
+#define HCI_EVT_Synchronization_Train_Received 0x50
 struct hciEvtSyncTrainReceived {
 	uint8_t status;
 	uint8_t mac[6];
@@ -3017,7 +3098,7 @@ struct hciEvtSyncTrainReceived {
 	uint8_t serviceData;
 } __packed;
 
-#define HCI_EVT_Connectionless_Slave_Broadcast_Receive           0x51
+#define HCI_EVT_Connectionless_Slave_Broadcast_Receive 0x51
 struct hciEvtConnectionlessSlaveBroadcastReceive {
 	uint8_t mac[6];
 	uint8_t ltAddr;
@@ -3029,128 +3110,116 @@ struct hciEvtConnectionlessSlaveBroadcastReceive {
 	/* data */
 } __packed;
 
-#define HCI_EVT_Connectionless_Slave_Broadcast_Timeout           0x52
+#define HCI_EVT_Connectionless_Slave_Broadcast_Timeout 0x52
 struct hciEvtConnectionlessSlaveBroadcastTimeout {
 	uint8_t mac[6];
 	uint8_t ltAddr;
 } __packed;
 
-#define HCI_EVT_Truncated_Page_Complete                          0x53
+#define HCI_EVT_Truncated_Page_Complete 0x53
 struct hciEvtTruncatedPageComplete {
 	uint8_t status;
 	uint8_t mac[6];
 } __packed;
 
-#define HCI_EVT_Slave_Page_Response_Timeout                      0x54
+#define HCI_EVT_Slave_Page_Response_Timeout 0x54
 
-#define HCI_EVT_Connless_Slave_Broadcast_Channel_Map_Change      0x55
+#define HCI_EVT_Connless_Slave_Broadcast_Channel_Map_Change 0x55
 struct hciEvtConnlessSlaveBroadcastChannelMapChange {
 	uint8_t map[10];
 } __packed;
 
-#define HCI_EVT_Inquiry_Response_Notification                    0x56
+#define HCI_EVT_Inquiry_Response_Notification 0x56
 struct hciEvtInquiryResponseNotif {
 	uint8_t lap[3];
 	uint8_t RSSI; /* actually an int8_t */
 } __packed;
 
-#define HCI_EVT_Authenticated_Payload_Timeout_Expired            0x57
+#define HCI_EVT_Authenticated_Payload_Timeout_Expired 0x57
 struct hciEvtAuthedPayloadTimeoutExpired {
 	uint16_t conn;
 } __packed;
 
-
-
-
-
 /* ERROR CODES */
 
 /* ==== BT 1.1 ==== */
 
-#define HCI_SUCCESS                                              0x00
-#define HCI_ERR_Unknown_HCI_Command                              0x01
-#define HCI_ERR_No_Connection                                    0x02
-#define HCI_ERR_Hardware_Failure                                 0x03
-#define HCI_ERR_Page_Timeout                                     0x04
-#define HCI_ERR_Authentication_Failure                           0x05
-#define HCI_ERR_Key_Missing                                      0x06
-#define HCI_ERR_Memory_Full                                      0x07
-#define HCI_ERR_Connection_Timeout                               0x08
-#define HCI_ERR_Max_Number_Of_Connections                        0x09
-#define HCI_ERR_Max_Number_Of_SCO_Connections_To_A_Device        0x0A
-#define HCI_ERR_ACL_Connection_Already_Exists                    0x0B
-#define HCI_ERR_Command_Disallowed                               0x0C
-#define HCI_ERR_Host_Rejected_Due_To_Limited_Resources           0x0D
-#define HCI_ERR_Host_Rejected_Due_To_Security_Reasons            0x0E
-#define HCI_ERR_Host_Rejected_Remote_Device_Personal_Device      0x0F
-#define HCI_ERR_Host_Timeout                                     0x10
-#define HCI_ERR_Unsupported_Feature_Or_Parameter_Value           0x11
-#define HCI_ERR_Invalid_HCI_Command_Parameters                   0x12
-#define HCI_ERR_Other_End_Terminated_Connection_User_Requested   0x13
-#define HCI_ERR_Other_End_Terminated_Connection_Low_Resources    0x14
-#define HCI_ERR_Other_End_Terminated_Connection_Soon_Power_Off   0x15
-#define HCI_ERR_Connection_Terminated_By_Local_Host              0x16
-#define HCI_ERR_Repeated_Attempts                                0x17
-#define HCI_ERR_Pairing_Not_Allowed                              0x18
-#define HCI_ERR_Unknown_LMP_PDU                                  0x19
-#define HCI_ERR_Unsupported_Remote_Feature                       0x1A
-#define HCI_ERR_SCO_Offset_Rejected                              0x1B
-#define HCI_ERR_SCO_Interval_Rejected                            0x1C
-#define HCI_ERR_SCO_Air_Mode_Rejected                            0x1D
-#define HCI_ERR_Invalid_LMP_Parameters                           0x1E
-#define HCI_ERR_Unspecified_Error                                0x1F
-#define HCI_ERR_Unsupported_LMP_Parameter                        0x20
-#define HCI_ERR_Role_Change_Not_Allowed                          0x21
-#define HCI_ERR_LMP_Response_Timeout                             0x22
-#define HCI_ERR_LMP_Error_Transaction_Collision                  0x23
-#define HCI_ERR_LMP_PDU_Not_Allowed                              0x24
-#define HCI_ERR_Encryption_Mode_Not_Acceptable                   0x25
-#define HCI_ERR_Unit_Key_Used                                    0x26
-#define HCI_ERR_QoS_Not_Supported                                0x27
-#define HCI_ERR_Instant_Passed                                   0x28
-#define HCI_ERR_Pairing_With_Unit_Key_Not_Supported              0x29
-
+#define HCI_SUCCESS 0x00
+#define HCI_ERR_Unknown_HCI_Command 0x01
+#define HCI_ERR_No_Connection 0x02
+#define HCI_ERR_Hardware_Failure 0x03
+#define HCI_ERR_Page_Timeout 0x04
+#define HCI_ERR_Authentication_Failure 0x05
+#define HCI_ERR_Key_Missing 0x06
+#define HCI_ERR_Memory_Full 0x07
+#define HCI_ERR_Connection_Timeout 0x08
+#define HCI_ERR_Max_Number_Of_Connections 0x09
+#define HCI_ERR_Max_Number_Of_SCO_Connections_To_A_Device 0x0A
+#define HCI_ERR_ACL_Connection_Already_Exists 0x0B
+#define HCI_ERR_Command_Disallowed 0x0C
+#define HCI_ERR_Host_Rejected_Due_To_Limited_Resources 0x0D
+#define HCI_ERR_Host_Rejected_Due_To_Security_Reasons 0x0E
+#define HCI_ERR_Host_Rejected_Remote_Device_Personal_Device 0x0F
+#define HCI_ERR_Host_Timeout 0x10
+#define HCI_ERR_Unsupported_Feature_Or_Parameter_Value 0x11
+#define HCI_ERR_Invalid_HCI_Command_Parameters 0x12
+#define HCI_ERR_Other_End_Terminated_Connection_User_Requested 0x13
+#define HCI_ERR_Other_End_Terminated_Connection_Low_Resources 0x14
+#define HCI_ERR_Other_End_Terminated_Connection_Soon_Power_Off 0x15
+#define HCI_ERR_Connection_Terminated_By_Local_Host 0x16
+#define HCI_ERR_Repeated_Attempts 0x17
+#define HCI_ERR_Pairing_Not_Allowed 0x18
+#define HCI_ERR_Unknown_LMP_PDU 0x19
+#define HCI_ERR_Unsupported_Remote_Feature 0x1A
+#define HCI_ERR_SCO_Offset_Rejected 0x1B
+#define HCI_ERR_SCO_Interval_Rejected 0x1C
+#define HCI_ERR_SCO_Air_Mode_Rejected 0x1D
+#define HCI_ERR_Invalid_LMP_Parameters 0x1E
+#define HCI_ERR_Unspecified_Error 0x1F
+#define HCI_ERR_Unsupported_LMP_Parameter 0x20
+#define HCI_ERR_Role_Change_Not_Allowed 0x21
+#define HCI_ERR_LMP_Response_Timeout 0x22
+#define HCI_ERR_LMP_Error_Transaction_Collision 0x23
+#define HCI_ERR_LMP_PDU_Not_Allowed 0x24
+#define HCI_ERR_Encryption_Mode_Not_Acceptable 0x25
+#define HCI_ERR_Unit_Key_Used 0x26
+#define HCI_ERR_QoS_Not_Supported 0x27
+#define HCI_ERR_Instant_Passed 0x28
+#define HCI_ERR_Pairing_With_Unit_Key_Not_Supported 0x29
 
 /* ==== BT 1.2 ==== */
 
-#define HCI_ERR_Different_Transaction_Collision                  0x2A
-#define HCI_ERR_QoS_Unacceptable_Parameter                       0x2C
-#define HCI_ERR_QoS_Rejected                                     0x2D
-#define HCI_ERR_Channel_Classification_Not_Supported             0x2E
-#define HCI_ERR_Insufficient_Security                            0x2F
-#define HCI_ERR_Parameter_Out_Of_Mandatory_Range                 0x30
-#define HCI_ERR_Role_Switch_Pending                              0x33
-#define HCI_ERR_Reserved_Slot_Violation                          0x34
-#define HIC_ERR_Role_Switch_Failed                               0x35
-
+#define HCI_ERR_Different_Transaction_Collision 0x2A
+#define HCI_ERR_QoS_Unacceptable_Parameter 0x2C
+#define HCI_ERR_QoS_Rejected 0x2D
+#define HCI_ERR_Channel_Classification_Not_Supported 0x2E
+#define HCI_ERR_Insufficient_Security 0x2F
+#define HCI_ERR_Parameter_Out_Of_Mandatory_Range 0x30
+#define HCI_ERR_Role_Switch_Pending 0x33
+#define HCI_ERR_Reserved_Slot_Violation 0x34
+#define HIC_ERR_Role_Switch_Failed 0x35
 
 /* ==== BT 2.1 ==== */
 
-#define HCI_ERR_EIR_Too_Large                                    0x36
-#define HCI_ERR_SSP_Not_Supported_By_Host                        0x37
-#define HCI_ERR_Host_Busy_Pairing                                0x38
-
+#define HCI_ERR_EIR_Too_Large 0x36
+#define HCI_ERR_SSP_Not_Supported_By_Host 0x37
+#define HCI_ERR_Host_Busy_Pairing 0x38
 
 /* ==== BT 3.0 ==== */
 
-#define HCI_ERR_Connection_Rejected_No_Suitable_Channel_Found    0x39
-#define HCI_ERR_Controller_Busy                                  0x3A
-
+#define HCI_ERR_Connection_Rejected_No_Suitable_Channel_Found 0x39
+#define HCI_ERR_Controller_Busy 0x3A
 
 /* ==== BT 4.0 ==== */
 
-#define HCI_ERR_Unacceptable_Connection_Interval                 0x3B
-#define HCI_ERR_Directed_Advertising_Timeout                     0x3C
-#define HCI_ERR_Connection_Terminated_Due_To_MIC_Failure         0x3D
-#define HCI_ERR_Connection_Failed_To_To_Established              0x3E
-#define HCI_ERR_MAC_Connection_Failed                            0x3F
-
+#define HCI_ERR_Unacceptable_Connection_Interval 0x3B
+#define HCI_ERR_Directed_Advertising_Timeout 0x3C
+#define HCI_ERR_Connection_Terminated_Due_To_MIC_Failure 0x3D
+#define HCI_ERR_Connection_Failed_To_To_Established 0x3E
+#define HCI_ERR_MAC_Connection_Failed 0x3F
 
 /* ==== BT 4.1 ==== */
 
-#define HCI_ERR_CoarseClock_AdjFailed_Will_Try_clock_Dragging    0x40
-
-
+#define HCI_ERR_CoarseClock_AdjFailed_Will_Try_clock_Dragging 0x40
 
 #endif
-
diff --git a/include/button.h b/include/button.h
index 3ab5892083..b38191aaf5 100644
--- a/include/button.h
+++ b/include/button.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,14 +10,13 @@
 
 #include "common.h"
 #include "compile_time_macros.h"
-#include "gpio.h"
 #include "ec_commands.h"
+#include "gpio_signal.h"
 
-#define BUTTON_FLAG_ACTIVE_HIGH  BIT(0)
-#define BUTTON_FLAG_DISABLED     BIT(1)   /* Button disabled */
+#define BUTTON_FLAG_ACTIVE_HIGH BIT(0)
+#define BUTTON_FLAG_DISABLED BIT(1) /* Button disabled */
 
-
-#define BUTTON_DEBOUNCE_US (30 * MSEC)
+#define BUTTON_DEBOUNCE_US CONFIG_BUTTON_DEBOUNCE
 
 struct button_config {
 	const char *name;
@@ -103,4 +102,20 @@ int button_is_adc_detected(enum gpio_signal gpio);
  */
 int adc_to_physical_value(enum gpio_signal gpio);
 
-#endif  /* __CROS_EC_BUTTON_H */
+/* Public for testing purposes only, undocumented. */
+enum debug_state {
+	STATE_DEBUG_NONE,
+	STATE_DEBUG_CHECK,
+	STATE_STAGING,
+	STATE_DEBUG_MODE_ACTIVE,
+	STATE_SYSRQ_PATH,
+	STATE_WARM_RESET_PATH,
+	STATE_SYSRQ_EXEC,
+	STATE_WARM_RESET_EXEC,
+};
+
+__test_only void reset_button_debug_state(void);
+
+__test_only enum debug_state get_button_debug_state(void);
+
+#endif /* __CROS_EC_BUTTON_H */
diff --git a/include/byteorder.h b/include/byteorder.h
index 8cfd810e54..7a47cbde65 100644
--- a/include/byteorder.h
+++ b/include/byteorder.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,4 +8,4 @@
 
 #include <endian.h>
 
-#endif  /* __EC_INCLUDE_BYTEORDER_H */
+#endif /* __EC_INCLUDE_BYTEORDER_H */
diff --git a/include/capsense.h b/include/capsense.h
index 2c0734aa4d..cb967c595e 100644
--- a/include/capsense.h
+++ b/include/capsense.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,4 +11,4 @@
 
 void capsense_interrupt(enum gpio_signal signal);
 
-#endif  /* __CROS_EC_CAPSENSE_H */
+#endif /* __CROS_EC_CAPSENSE_H */
diff --git a/include/case_closed_debug.h b/include/case_closed_debug.h
index 53c8b1ed17..ebca79fdc0 100644
--- a/include/case_closed_debug.h
+++ b/include/case_closed_debug.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/include/cec.h b/include/cec.h
index b1ac6dbbb0..bce2288fa4 100644
--- a/include/cec.h
+++ b/include/cec.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,6 +14,49 @@
 #error "Buffer size must not exceed 255 since offsets are uint8_t"
 #endif
 
+/* Notification from interrupt to CEC task that data has been received */
+#define CEC_TASK_EVENT_RECEIVED_DATA TASK_EVENT_CUSTOM_BIT(0)
+#define CEC_TASK_EVENT_OKAY TASK_EVENT_CUSTOM_BIT(1)
+#define CEC_TASK_EVENT_FAILED TASK_EVENT_CUSTOM_BIT(2)
+
+/* CEC broadcast address. Also the highest possible CEC address */
+#define CEC_BROADCAST_ADDR 15
+
+/* Address to indicate that no logical address has been set */
+#define CEC_UNREGISTERED_ADDR 255
+
+/*
+ * The CEC specification requires at least one and a maximum of
+ * five resends attempts
+ */
+#define CEC_MAX_RESENDS 5
+
+/* All return EC_SUCCESS if successful, non-zero if error. */
+struct cec_drv {
+	/* Initialise the CEC port */
+	int (*init)(int port);
+
+	/*
+	 * Get/set enable state.
+	 * enable = 0 means disabled, enable = 1 means enabled.
+	 */
+	int (*get_enable)(int port, uint8_t *enable);
+	int (*set_enable)(int port, uint8_t enable);
+
+	/* Get/set the logical address */
+	int (*get_logical_addr)(int port, uint8_t *logical_addr);
+	int (*set_logical_addr)(int port, uint8_t logical_addr);
+
+	/* Send a CEC message */
+	int (*send)(int port, const uint8_t *msg, uint8_t len);
+
+	/*
+	 * Get the received message. This should be called after the driver sets
+	 * CEC_TASK_EVENT_RECEIVED_DATA to indicate data is ready.
+	 */
+	int (*get_received_message)(int port, uint8_t **msg, uint8_t *len);
+};
+
 /* CEC message during transfer */
 struct cec_msg_transfer {
 	/* Bit offset  */
@@ -40,6 +83,53 @@ struct cec_rx_queue {
 	uint8_t buf[CEC_RX_BUFFER_SIZE];
 };
 
+struct cec_header {
+	uint8_t initiator : 4;
+	uint8_t desitination : 4;
+} __packed;
+
+/* CEC commands */
+#define CEC_MSG_IMAGE_VIEW_ON 0x04
+#define CEC_MSG_TEXT_VIEW_ON 0x0d
+#define CEC_MSG_REPORT_PHYSICAL_ADDRESS 0x84
+#define CEC_MSG_DEVICE_VENDOR_ID 0x87
+
+enum cec_action {
+	CEC_ACTION_NONE = 0,
+	CEC_ACTION_POWER_BUTTON,
+} __packed;
+
+/**
+ * Defines what actions to take for commands received from external devices
+ * when the AP is off.
+ */
+struct cec_offline_policy {
+	/* CEC command to act on */
+	uint8_t command;
+	/* Action taken when <command> is received */
+	enum cec_action action;
+};
+
+/**
+ * CEC configuration.
+ */
+struct cec_config_t {
+	const struct cec_drv *drv;
+	/*
+	 * Actions taken on message received when the system is off.
+	 * Last entry must be null terminated.
+	 */
+	struct cec_offline_policy *offline_policy;
+};
+
+/* CEC config definition. */
+extern const struct cec_config_t cec_config[];
+
+/**
+ * Default policy provided for convenience.
+ */
+extern struct cec_offline_policy cec_default_policy[];
+
 /**
  * Get the current bit of a CEC message transfer
  *
@@ -93,3 +183,14 @@ int cec_rx_queue_push(struct cec_rx_queue *queue, const uint8_t *msg,
  */
 int cec_rx_queue_pop(struct cec_rx_queue *queue, uint8_t *msg,
 		     uint8_t *msg_len);
+
+/**
+ * Process a CEC message when the AP is off.
+ *
+ * @param queue		Queue to retrieve message from
+ * @param msg		Buffer to store retrieved message in
+ * @param msg_len	Number of data bytes in msg
+ * @return EC_SUCCESS if the message is consumed or EC_ERROR_* otherwise.
+ */
+int cec_process_offline_message(struct cec_rx_queue *queue, const uint8_t *msg,
+				uint8_t msg_len);
diff --git a/include/charge_manager.h b/include/charge_manager.h
index f4cadd1b6c..193ff8e80b 100644
--- a/include/charge_manager.h
+++ b/include/charge_manager.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,7 +19,8 @@
 
 /* Only track BC1.2 charge current if we support BC1.2 charging */
 #if defined(HAS_TASK_USB_CHG) || defined(HAS_TASK_USB_CHG_P0) || \
-defined(TEST_BUILD)
+	defined(CONFIG_PLATFORM_EC_USB_CHARGER_SINGLE_TASK) ||   \
+	defined(TEST_BUILD)
 #define CHARGE_MANAGER_BC12
 #endif
 
@@ -27,9 +28,12 @@ defined(TEST_BUILD)
  * Time to delay for detecting the charger type (must be long enough for BC1.2
  * driver to get supplier information and notify charge manager).
  */
-#define CHARGE_DETECT_DELAY (2*SECOND)
+#define CHARGE_DETECT_DELAY (2 * SECOND)
 
-/* Commonly-used charge suppliers listed in no particular order */
+/*
+ * Commonly-used charge suppliers listed in no particular order.
+ * Don't forget to update CHARGE_SUPPLIER_NAME and supplier_priority.
+ */
 enum charge_supplier {
 	CHARGE_SUPPLIER_NONE = -1,
 	CHARGE_SUPPLIER_PD,
@@ -46,15 +50,35 @@ enum charge_supplier {
 #endif /* CHARGE_MANAGER_BC12 */
 #if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
 	CHARGE_SUPPLIER_DEDICATED,
-#endif
-#ifdef CONFIG_WIRELESS_CHARGER_P9221_R7
-	CHARGE_SUPPLIER_WPC_BPP,
-	CHARGE_SUPPLIER_WPC_EPP,
-	CHARGE_SUPPLIER_WPC_GPP,
 #endif
 	CHARGE_SUPPLIER_COUNT
 };
 
+#ifdef CHARGE_MANAGER_BC12
+#define CHARGE_SUPPLIER_NAME_BC12                          \
+	[CHARGE_SUPPLIER_BC12_DCP] = "BC12_DCP",           \
+	[CHARGE_SUPPLIER_BC12_CDP] = "BC12_CDP",           \
+	[CHARGE_SUPPLIER_BC12_SDP] = "BC12_SDP",           \
+	[CHARGE_SUPPLIER_PROPRIETARY] = "BC12_PROP",       \
+	[CHARGE_SUPPLIER_TYPEC_UNDER_1_5A] = "USBC_U1_5A", \
+	[CHARGE_SUPPLIER_OTHER] = "BC12_OTHER", [CHARGE_SUPPLIER_VBUS] = "VBUS",
+#else
+#define CHARGE_SUPPLIER_NAME_BC12
+#endif
+#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
+#define CHARGE_SUPPLIER_NAME_DEDICATED \
+	[CHARGE_SUPPLIER_DEDICATED] = "DEDICATED",
+#else
+#define CHARGE_SUPPLIER_NAME_DEDICATED
+#endif
+#define CHARGE_SUPPLIER_NAME_QI
+
+#define CHARGE_SUPPLIER_NAME                                           \
+	[CHARGE_SUPPLIER_PD] = "PD", [CHARGE_SUPPLIER_TYPEC] = "USBC", \
+	[CHARGE_SUPPLIER_TYPEC_DTS] = "USBC_DTS",                      \
+	CHARGE_SUPPLIER_NAME_BC12 CHARGE_SUPPLIER_NAME_DEDICATED       \
+		CHARGE_SUPPLIER_NAME_QI
+
 /*
  * Charge supplier priority: lower number indicates higher priority.
  * Default priority is in charge_manager.c. It can be overridden by boards.
@@ -75,8 +99,7 @@ struct charge_port_info {
  * @param charge	Charge port current / voltage. If NULL, current = 0
  * 			voltage = 0 will be used.
  */
-void charge_manager_update_charge(int supplier,
-				  int port,
+void charge_manager_update_charge(int supplier, int port,
 				  const struct charge_port_info *charge);
 
 /* Partner port dualrole capabilities */
@@ -113,8 +136,8 @@ enum ceil_requestor {
 	CEIL_REQUESTOR_COUNT,
 };
 
-#define CHARGE_PORT_COUNT (CONFIG_USB_PD_PORT_MAX_COUNT + \
-			   CONFIG_DEDICATED_CHARGE_PORT_COUNT)
+#define CHARGE_PORT_COUNT \
+	(CONFIG_USB_PD_PORT_MAX_COUNT + CONFIG_DEDICATED_CHARGE_PORT_COUNT)
 #if (CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0)
 
 /**
@@ -223,6 +246,23 @@ int charge_manager_get_charger_voltage(void);
  */
 enum charge_supplier charge_manager_get_supplier(void);
 
+/**
+ * Get the current VBUS voltage.
+ *
+ * @param port The USB-C port to query
+ * @return The current VBUS voltage in mV or 0 if it could not be determined
+ */
+int charge_manager_get_vbus_voltage(int port);
+
+/**
+ * Get the current limit of CHARGE_PD_SUPPLIER.
+ *
+ * @return	The CHARGE_SUPPLIER_PD current limit in mA or
+ *		CHARGE_CURRENT_UNINITIALIZED if the supplier is not
+ *		CHARGE_SUPPLIER_PD.
+ */
+int charge_manager_get_pd_current_uncapped(void);
+
 #ifdef CONFIG_USB_PD_LOGGING
 /* Save power state log entry for the given port */
 void charge_manager_save_log(int port);
@@ -260,14 +300,19 @@ int board_set_active_charge_port(int charge_port);
 /**
  * Set the charge current limit.
  *
+ * The default implementation of this function derates charge_ma by
+ * CONFIG_CHARGER_INPUT_CURRENT_PCT (if configured), and clamps charge_ma to
+ * a lower bound of CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT (if configured).
+ *
  * @param port PD port.
  * @param supplier Identified CHARGE_SUPPLIER_*.
  * @param charge_ma Desired charge current limit, <= max_ma.
  * @param max_ma Maximum charge current limit, >= charge_ma.
  * @param charge_mv Negotiated charge voltage (mV).
  */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv);
+__override_proto void board_set_charge_limit(int port, int supplier,
+					     int charge_ma, int max_ma,
+					     int charge_mv);
 
 /**
  * Get whether the port is sourcing power on VBUS.
@@ -311,8 +356,21 @@ __override_proto int board_charge_port_is_connected(int port);
  * @param port	Dedicated charge port.
  * @param r	USB PD power info to be updated.
  */
-__override_proto
-void board_fill_source_power_info(int port,
-				  struct ec_response_usb_pd_power_info *r);
+__override_proto void
+board_fill_source_power_info(int port, struct ec_response_usb_pd_power_info *r);
+
+/**
+ * Board specific callback to get vbus voltage.
+ *
+ * @param port  Dedicated charge port.
+ */
+__override_proto int board_get_vbus_voltage(int port);
+
+int is_pd_port(int port);
+
+/**
+ * Board specific callback to modify the delay time of leaving safe mode
+ */
+__override_proto int board_get_leave_safe_mode_delay_ms(void);
 
 #endif /* __CROS_EC_CHARGE_MANAGER_H */
diff --git a/include/charge_ramp.h b/include/charge_ramp.h
index 0745f5ef98..be456a64ec 100644
--- a/include/charge_ramp.h
+++ b/include/charge_ramp.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,10 +11,7 @@
 #include "timer.h"
 
 /* Charge ramp state used for checking VBUS */
-enum chg_ramp_vbus_state {
-	CHG_RAMP_VBUS_RAMPING,
-	CHG_RAMP_VBUS_STABLE
-};
+enum chg_ramp_vbus_state { CHG_RAMP_VBUS_RAMPING, CHG_RAMP_VBUS_STABLE };
 
 /**
  * Check if VBUS is too low
@@ -81,11 +78,15 @@ int chg_ramp_is_detected(void);
  * @voltage Negotiated charge voltage.
  */
 void chg_ramp_charge_supplier_change(int port, int supplier, int current,
-			     timestamp_t registration_time, int voltage);
+				     timestamp_t registration_time,
+				     int voltage);
 
 #else
-static inline void chg_ramp_charge_supplier_change(
-		int port, int supplier, timestamp_t registration_time) { }
+static inline void
+chg_ramp_charge_supplier_change(int port, int supplier,
+				timestamp_t registration_time)
+{
+}
 #endif
 
 #endif /* __CROS_EC_CHARGE_RAMP_H */
diff --git a/include/charge_state.h b/include/charge_state.h
index 0fa0254071..e2052fb447 100644
--- a/include/charge_state.h
+++ b/include/charge_state.h
@@ -1,11 +1,18 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 #ifndef __CROS_EC_CHARGE_STATE_H
 #define __CROS_EC_CHARGE_STATE_H
 
+#include "battery.h"
+#include "battery_smart.h"
+#include "charger.h"
+#include "chipset.h"
 #include "common.h"
+#include "ec_ec_comm_client.h"
+#include "ocpc.h"
+#include "stdbool.h"
 #include "timer.h"
 
 /* Stuff that's common to all charger implementations can go here. */
@@ -14,38 +21,42 @@
 #define PRECHARGE_TIMEOUT CONFIG_BATTERY_PRECHARGE_TIMEOUT
 
 /* Power state task polling periods in usec */
-#define CHARGE_POLL_PERIOD_VERY_LONG   MINUTE
-#define CHARGE_POLL_PERIOD_LONG        (MSEC * 500)
-#define CHARGE_POLL_PERIOD_CHARGE      (MSEC * 250)
-#define CHARGE_POLL_PERIOD_SHORT       (MSEC * 100)
-#define CHARGE_MIN_SLEEP_USEC          (MSEC * 50)
+#define CHARGE_POLL_PERIOD_VERY_LONG MINUTE
+#define CHARGE_POLL_PERIOD_LONG (MSEC * 500)
+#define CHARGE_POLL_PERIOD_CHARGE (MSEC * 250)
+#define CHARGE_POLL_PERIOD_SHORT (MSEC * 100)
+#define CHARGE_MIN_SLEEP_USEC (MSEC * 50)
 /* If a board hasn't provided a max sleep, use 1 minute as default */
 #ifndef CHARGE_MAX_SLEEP_USEC
-#define CHARGE_MAX_SLEEP_USEC          MINUTE
+#define CHARGE_MAX_SLEEP_USEC MINUTE
 #endif
 
 /* Power states */
-enum charge_state {
+enum led_pwr_state {
 	/* Meta-state; unchanged from previous time through task loop */
-	PWR_STATE_UNCHANGE = 0,
+	LED_PWRS_UNCHANGE = 0,
 	/* Initializing charge state machine at boot */
-	PWR_STATE_INIT,
+	LED_PWRS_INIT,
 	/* Re-initializing charge state machine */
-	PWR_STATE_REINIT,
+	LED_PWRS_REINIT,
 	/* Just transitioned from init to idle */
-	PWR_STATE_IDLE0,
+	LED_PWRS_IDLE0,
 	/* Idle; AC present */
-	PWR_STATE_IDLE,
+	LED_PWRS_IDLE,
+	/* Forced Idle */
+	LED_PWRS_FORCED_IDLE,
 	/* Discharging */
-	PWR_STATE_DISCHARGE,
+	LED_PWRS_DISCHARGE,
 	/* Discharging and fully charged */
-	PWR_STATE_DISCHARGE_FULL,
+	LED_PWRS_DISCHARGE_FULL,
 	/* Charging */
-	PWR_STATE_CHARGE,
+	LED_PWRS_CHARGE,
 	/* Charging, almost fully charged */
-	PWR_STATE_CHARGE_NEAR_FULL,
+	LED_PWRS_CHARGE_NEAR_FULL,
 	/* Charging state machine error */
-	PWR_STATE_ERROR
+	LED_PWRS_ERROR,
+	/*  Count of total states */
+	LED_PWRS_COUNT
 };
 
 /* Charge state flags */
@@ -56,28 +67,70 @@ enum charge_state {
 /* Battery is responsive */
 #define CHARGE_FLAG_BATT_RESPONSIVE BIT(2)
 
-/* Debugging constants, in the same order as enum charge_state. This string
+/* Debugging constants, in the same order as enum pwr_state. This string
  * table was moved here to sync with enum above.
  */
-#define CHARGE_STATE_NAME_TABLE { \
-		"unchange",	\
-		"init",		\
-		"reinit",	\
-		"idle0",	\
-		"idle",		\
-		"discharge",	\
-		"discharge_full",	\
-		"charge",	\
-		"charge_near_full",      \
-		"error"		\
+#define CHARGE_STATE_NAME_TABLE                                             \
+	{                                                                   \
+		"unchange", "init", "reinit", "idle0", "idle", "discharge", \
+			"discharge_full", "charge", "charge_near_full",     \
+			"error"                                             \
 	}
-	/* End of CHARGE_STATE_NAME_TABLE macro */
+/* End of CHARGE_STATE_NAME_TABLE macro */
+
+/*
+ * The values exported by charge_get_state() and charge_get_flags() are used
+ * only to control the LEDs (with one not-quite-correct exception). For V2
+ * we use a different set of states internally.
+ */
+enum charge_state {
+	ST_IDLE = 0,
+	ST_DISCHARGE,
+	ST_CHARGE,
+	ST_PRECHARGE,
+
+	NUM_STATES_V2
+};
+
+struct charge_state_data {
+	timestamp_t ts;
+	int ac;
+	int batt_is_charging;
+	struct charger_params chg;
+	struct batt_params batt;
+	enum charge_state state;
+	int requested_voltage;
+	int requested_current;
+	int desired_input_current;
+#ifdef CONFIG_CHARGER_OTG
+	int output_current;
+#endif
+#ifdef CONFIG_EC_EC_COMM_BATTERY_CLIENT
+	int input_voltage;
+#endif
+#ifdef CONFIG_OCPC
+	struct ocpc_data ocpc;
+#endif
+};
+
+struct sustain_soc {
+	int8_t lower;
+	int8_t upper;
+	uint8_t flags; /* enum ec_charge_control_flag */
+};
 
+#define BAT_MAX_DISCHG_CURRENT 5000 /* mA */
+#define BAT_LOW_VOLTAGE_THRESH 3200 /* mV */
 
 /**
  * Return current charge state.
  */
-enum charge_state charge_get_state(void);
+enum led_pwr_state led_pwr_get_state(void);
+
+/**
+ * Return current charge v2 state.
+ */
+__test_only enum charge_state charge_get_state(void);
 
 /**
  * Return non-zero if battery is so low we want to keep AP off.
@@ -89,17 +142,22 @@ int charge_keep_power_off(void);
  */
 uint32_t charge_get_flags(void);
 
-#if defined(CONFIG_CHARGER)
 /**
  * Return current battery charge percentage.
  */
+#if defined(CONFIG_BATTERY) || defined(TEST_BUILD)
 int charge_get_percent(void);
-#elif defined(CONFIG_BATTERY)
+#else
+static inline int charge_get_percent(void)
+{
+	return 0;
+}
+#endif
+
 /**
  * Return current battery charge if not using charge manager sub-system.
  */
 int board_get_battery_soc(void);
-#endif
 
 /**
  * Return current display charge in 10ths of a percent (e.g. 1000 = 100.0%)
@@ -119,16 +177,52 @@ __override_proto int charge_is_consuming_full_input_current(void);
 /**
  * Return non-zero if discharging and battery so low we should shut down.
  */
+#if defined(CONFIG_CHARGER) && defined(CONFIG_BATTERY)
 int charge_want_shutdown(void);
+#else
+static inline int charge_want_shutdown(void)
+{
+	return 0;
+}
+#endif
+
+/**
+ * Return true if battery level is below threshold, false otherwise,
+ * or if SoC can't be determined.
+ *
+ * @param transitioned	True to check if SoC is previously above threshold
+ */
+enum batt_threshold_type {
+	BATT_THRESHOLD_TYPE_LOW = 0,
+	BATT_THRESHOLD_TYPE_SHUTDOWN
+};
+#if defined(CONFIG_CHARGER) && defined(CONFIG_BATTERY)
+int battery_is_below_threshold(enum batt_threshold_type type,
+			       bool transitioned);
+#else
+static inline int battery_is_below_threshold(enum batt_threshold_type type,
+					     bool transitioned)
+{
+	return 0;
+}
+#endif
 
 /**
- * Return non-zero if the battery level is too low to allow power on, even if
- * a charger is attached.
+ * @brief whether or not the charge state will prevent power-on
  *
  * @param power_button_pressed	True if the power-up attempt is caused by a
  *				power button press.
+ * @return True if the battery level is too low to allow power on, even if a
+ *         charger is attached.
  */
-int charge_prevent_power_on(int power_button_pressed);
+#ifdef CONFIG_BATTERY
+bool charge_prevent_power_on(bool power_button_pressed);
+#else
+static inline bool charge_prevent_power_on(bool power_button_pressed)
+{
+	return false;
+}
+#endif
 
 /**
  * Get the last polled battery/charger temperature.
@@ -147,8 +241,218 @@ int charge_get_battery_temp(int idx, int *temp_ptr);
  */
 const struct batt_params *charger_current_battery_params(void);
 
+/**
+ * Set the output current limit and voltage. This is used to provide power from
+ * the charger chip ("OTG" mode).
+ *
+ * @param chgnum Charger index to act upon
+ * @param ma Maximum current to provide in mA (0 to disable output).
+ * @param mv Voltage in mV (ignored if ma == 0).
+ * @return EC_SUCCESS or error
+ */
+int charge_set_output_current_limit(int chgnum, int ma, int mv);
+
+/**
+ * Set the charge input current limit. This value is stored and sent every
+ * time AC is applied.
+ *
+ * The input current limit is automatically derated by
+ * CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT (if configured), and is clamped to
+ * no less than CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT mA (if configured).
+ *
+ * @param ma New input current limit in mA
+ * @param mv Negotiated charge voltage in mV.
+ * @return EC_SUCCESS or error
+ */
+int charge_set_input_current_limit(int ma, int mv);
+
+/**
+ * Set the desired manual charge current when in idle mode.
+ *
+ * @param curr_ma: Charge current in mA.
+ */
+void chgstate_set_manual_current(int curr_ma);
+
+/**
+ * Set the desired manual charge voltage when in idle mode.
+ *
+ * @param volt_mv: Charge voltage in mV.
+ */
+void chgstate_set_manual_voltage(int volt_mv);
+
+/**
+ * Board-specific routine to indicate if the base is connected.
+ */
+int board_is_base_connected(void);
+
+/**
+ * Board-specific routine to enable power distribution between lid and base
+ * (current can flow both ways).
+ */
+void board_enable_base_power(int enable);
+
+/**
+ * Board-specific routine to reset the base (in case it is unresponsive, e.g.
+ * if we told it to hibernate).
+ */
+void board_base_reset(void);
+
+/**
+ * Callback with which boards determine action on critical low battery
+ *
+ * The default implementation is provided in charge_state.c. Overwrite it
+ * to customize it.
+ *
+ * @param curr Pointer to struct charge_state_data
+ * @return Action to take.
+ */
+enum critical_shutdown
+board_critical_shutdown_check(struct charge_state_data *curr);
+
+/**
+ * Callback to set battery level for shutdown
+ *
+ * A board can implement this to customize shutdown battery level at runtime.
+ *
+ * @return battery level for shutdown
+ */
+uint8_t board_set_battery_level_shutdown(void);
+
+/**
+ * Return system PLT power and battery's desired power.
+ *
+ * @return desired power in mW
+ */
+int charge_get_plt_plus_bat_desired_mw(void);
+
+/**
+ * Get the stable battery charging current. The current will be
+ * CHARGE_CURRENT_UNINITIALIZED if not yet stable.
+ *
+ * @return stable battery charging current in mA
+ */
+int charge_get_stable_current(void);
+
+/**
+ * Select which charger IC will actually be performing the charger switching.
+ *
+ * @param idx The index into the chg_chips table.
+ */
+void charge_set_active_chg_chip(int idx);
+
+/**
+ * Retrieve which charger IC is the active charger IC performing the charger
+ * switching.
+ */
+int charge_get_active_chg_chip(void);
+
+/**
+ * Set the stable current.
+ *
+ * @param ma: battery charging current in mA
+ */
+void charge_set_stable_current(int ma);
+
+/**
+ * Reset stable current counter stable_ts. Calling this function would set
+ * stable_current to CHARGE_CURRENT_UNINITIALIZED.
+ */
+void charge_reset_stable_current(void);
+
+/**
+ * Reset stable current counter stable_ts. Calling this function would set
+ * stable_current to CHARGE_CURRENT_UNINITIALIZED.
+ *
+ * @param us: sample stable current until us later.
+ */
+void charge_reset_stable_current_us(uint64_t us);
+
+/**
+ * Check if the battery charging current is stable by examining the timestamp.
+ *
+ * @return true if stable timestamp expired, false otherwise.
+ */
+bool charge_is_current_stable(void);
+
+/**
+ * Reset the OCPC internal state data and set the target VSYS to the current
+ * battery voltage for the auxiliary chargers.
+ */
+void trigger_ocpc_reset(void);
+
+/* Track problems in communicating with the battery or charger */
+enum problem_type {
+	PR_STATIC_UPDATE,
+	PR_SET_VOLTAGE,
+	PR_SET_CURRENT,
+	PR_SET_MODE,
+	PR_SET_INPUT_CURR,
+	PR_POST_INIT,
+	PR_CHG_FLAGS,
+	PR_BATT_FLAGS,
+	PR_CUSTOM,
+	PR_CFG_SEC_CHG,
+
+	NUM_PROBLEM_TYPES
+};
+
+void charge_problem(enum problem_type p, int v);
+
+struct charge_state_data *charge_get_status(void);
+
+enum ec_charge_control_mode get_chg_ctrl_mode(void);
+
+int set_chg_ctrl_mode(enum ec_charge_control_mode mode);
+
+__test_only void reset_prev_disp_charge(void);
+
+/**
+ * Whether or not the charging progress was shown. Note, calling this function
+ * will reset the value to false.
+ *
+ * @return Whether or not the charging progress was printed to the console
+ */
+__test_only bool charging_progress_displayed(void);
+
+/**
+ * Callback for boards to request charger to enable bypass mode on/off.
+ *
+ * @return True for requesting bypass on. False for requesting bypass off.
+ */
+int board_should_charger_bypass(void);
+
+#ifdef CONFIG_CHARGER_BYPASS_REVERSE_TURBO
+/**
+ * Callback for boards to call the charger_enable_bypass_mode without mode change.
+ *
+ * @return True for requesting change.
+ */
+int board_want_charger_change_mode(void);
+#endif
+
+/**
+ * Set the battery sustainer mode.
+ *
+ * @param lower: lower battery soc charge limit [1-100%] or -1 to disable
+ * @param upper: upper battery soc charge limit [1-100%] or -1 to disable
+ *
+ * @return EC_SUCCESS or EC_ERROR_INVAL
+ */
+int battery_sustainer_set(int8_t lower, int8_t upper);
+
+/**
+ * return the sustainer is active or not
+ * lower and upper == -1 is mean disable
+ *
+ * @return if sustain_soc.lower and sustain_soc.upper != -1 will be true
+ */
+bool battery_sustainer_enabled(void);
 
 /* Config Charger */
-#include "charge_state_v2.h"
+#include "charge_state.h"
+
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+void battery_customize(struct charge_state_data *curr_batt);
+#endif
 
-#endif	/* __CROS_EC_CHARGE_STATE_H */
+#endif /* __CROS_EC_CHARGE_STATE_H */
diff --git a/include/charge_state_v1.h b/include/charge_state_v1.h
deleted file mode 100644
index 6bc8529a6e..0000000000
--- a/include/charge_state_v1.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery.h"
-#include "timer.h"
-
-#ifndef __CROS_EC_CHARGE_STATE_V1_H
-#define __CROS_EC_CHARGE_STATE_V1_H
-
-/* Update period to prevent charger watchdog timeout */
-#define CHARGER_UPDATE_PERIOD (SECOND * 10)
-
-/* Power state error flags */
-#define F_CHARGER_INIT        BIT(0) /* Charger initialization */
-#define F_CHARGER_VOLTAGE     BIT(1) /* Charger maximum output voltage */
-#define F_CHARGER_CURRENT     BIT(2) /* Charger maximum output current */
-#define F_BATTERY_VOLTAGE     BIT(3) /* Battery voltage */
-#define F_BATTERY_MODE        BIT(8) /* Battery mode */
-#define F_BATTERY_CAPACITY    BIT(9) /* Battery capacity */
-#define F_BATTERY_STATE_OF_CHARGE BIT(10) /* State of charge, percentage */
-#define F_BATTERY_UNRESPONSIVE    BIT(11) /* Battery not responding */
-#define F_BATTERY_NOT_CONNECTED   BIT(12) /* Battery not connected */
-#define F_BATTERY_GET_PARAMS  BIT(13) /* Any battery parameter bad */
-
-#define F_BATTERY_MASK (F_BATTERY_VOLTAGE | \
-			F_BATTERY_MODE | \
-			F_BATTERY_CAPACITY | F_BATTERY_STATE_OF_CHARGE | \
-			F_BATTERY_UNRESPONSIVE | F_BATTERY_NOT_CONNECTED | \
-			F_BATTERY_GET_PARAMS)
-#define F_CHARGER_MASK (F_CHARGER_VOLTAGE | F_CHARGER_CURRENT | \
-			F_CHARGER_INIT)
-
-/* Power state data
- * Status collection of charging state machine.
- */
-struct charge_state_data {
-	int ac;
-	int charging_voltage;
-	int charging_current;
-	struct batt_params batt;
-	enum charge_state state;
-	uint32_t error;
-	timestamp_t ts;
-};
-
-/* State context
- * The shared context for state handler. The context contains current and
- * previous state.
- */
-struct charge_state_context {
-	struct charge_state_data curr;
-	struct charge_state_data prev;
-	timestamp_t charge_state_updated_time;
-	uint32_t *memmap_batt_volt;
-	uint32_t *memmap_batt_rate;
-	uint32_t *memmap_batt_cap;
-	uint8_t *memmap_batt_flags;
-	/* Charger and battery pack info */
-	const struct charger_info *charger;
-	const struct battery_info *battery;
-	/* Charging timestamps */
-	timestamp_t charger_update_time;
-	timestamp_t trickle_charging_time;
-	timestamp_t voltage_debounce_time;
-	timestamp_t shutdown_warning_time;
-	int battery_responsive;
-};
-
-#endif /* __CROS_EC_CHARGE_STATE_V1_H */
-
diff --git a/include/charge_state_v2.h b/include/charge_state_v2.h
deleted file mode 100644
index 1cff136ee8..0000000000
--- a/include/charge_state_v2.h
+++ /dev/null
@@ -1,194 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <stdbool.h>
-
-#include "battery.h"
-#include "battery_smart.h"
-#include "charger.h"
-#include "chipset.h"
-#include "ec_ec_comm_master.h"
-#include "ocpc.h"
-#include "timer.h"
-
-#ifndef __CROS_EC_CHARGE_STATE_V2_H
-#define __CROS_EC_CHARGE_STATE_V2_H
-
-/*
- * The values exported by charge_get_state() and charge_get_flags() are used
- * only to control the LEDs (with one not-quite-correct exception). For V2
- * we use a different set of states internally.
- */
-enum charge_state_v2 {
-	ST_IDLE = 0,
-	ST_DISCHARGE,
-	ST_CHARGE,
-	ST_PRECHARGE,
-
-	NUM_STATES_V2
-};
-
-struct charge_state_data {
-	timestamp_t ts;
-	int ac;
-	int batt_is_charging;
-	struct charger_params chg;
-	struct batt_params batt;
-	enum charge_state_v2 state;
-	int requested_voltage;
-	int requested_current;
-	int desired_input_current;
-#ifdef CONFIG_CHARGER_OTG
-	int output_current;
-#endif
-#ifdef CONFIG_EC_EC_COMM_BATTERY_MASTER
-	int input_voltage;
-#endif
-#ifdef CONFIG_OCPC
-	struct ocpc_data ocpc;
-#endif
-};
-
-/**
- * Set the output current limit and voltage. This is used to provide power from
- * the charger chip ("OTG" mode).
- *
- * @param chgnum Charger index to act upon
- * @param ma Maximum current to provide in mA (0 to disable output).
- * @param mv Voltage in mV (ignored if ma == 0).
- * @return EC_SUCCESS or error
- */
-int charge_set_output_current_limit(int chgnum, int ma, int mv);
-
-/**
- * Set the charge input current limit. This value is stored and sent every
- * time AC is applied.
- *
- * @param ma New input current limit in mA
- * @param mv Negotiated charge voltage in mV.
- * @return EC_SUCCESS or error
- */
-int charge_set_input_current_limit(int ma, int mv);
-
-/*
- * Expose charge/battery related state
- *
- * @param param command to get corresponding data
- * @param value the corresponding data
- * @return EC_SUCCESS or error
- */
-#ifdef CONFIG_CHARGE_STATE_DEBUG
-int charge_get_charge_state_debug(int param, uint32_t *value);
-#endif /* CONFIG_CHARGE_STATE_DEBUG */
-
-/**
- * Set the desired manual charge current when in idle mode.
- *
- * @param curr_ma: Charge current in mA.
- */
-void chgstate_set_manual_current(int curr_ma);
-
-/**
- * Set the desired manual charge voltage when in idle mode.
- *
- * @param volt_mv: Charge voltage in mV.
- */
-void chgstate_set_manual_voltage(int volt_mv);
-
-/**
- * Board-specific routine to indicate if the base is connected.
- */
-int board_is_base_connected(void);
-
-/**
- * Board-specific routine to enable power distribution between lid and base
- * (current can flow both ways).
- */
-void board_enable_base_power(int enable);
-
-/**
- * Board-specific routine to reset the base (in case it is unresponsive, e.g.
- * if we told it to hibernate).
- */
-void board_base_reset(void);
-
-/**
- * Callback with which boards determine action on critical low battery
- *
- * The default implementation is provided in charge_state_v2.c. Overwrite it
- * to customize it.
- *
- * @param curr Pointer to struct charge_state_data
- * @return Action to take.
- */
-enum critical_shutdown board_critical_shutdown_check(
-		struct charge_state_data *curr);
-
-/**
- * Callback to set battery level for shutdown
- *
- * A board can implement this to customize shutdown battery level at runtime.
- *
- * @return battery level for shutdown
- */
-uint8_t board_set_battery_level_shutdown(void);
-
-/**
- * Return system PLT power and battery's desired power.
- *
- * @return desired power in mW
- */
-int charge_get_plt_plus_bat_desired_mw(void);
-
-/**
- * Get the stable battery charging current. The current will be
- * CHARGE_CURRENT_UNINITIALIZED if not yet stable.
- *
- * @return stable battery charging current in mA
- */
-int charge_get_stable_current(void);
-
-/**
- * Select which charger IC will actually be performing the charger switching.
- *
- * @param idx The index into the chg_chips table.
- */
-void charge_set_active_chg_chip(int idx);
-
-/**
- * Retrieve which charger IC is the active charger IC performing the charger
- * switching.
- */
-int charge_get_active_chg_chip(void);
-
-/**
- * Set the stable current.
- *
- * @param ma: battery charging current in mA
- */
-void charge_set_stable_current(int ma);
-
-/**
- * Reset stable current counter stable_ts. Calling this function would set
- * stable_current to CHARGE_CURRENT_UNINITIALIZED.
- */
-void charge_reset_stable_current(void);
-
-/**
- * Reset stable current counter stable_ts. Calling this function would set
- * stable_current to CHARGE_CURRENT_UNINITIALIZED.
- *
- * @param us: sample stable current until us later.
- */
-void charge_reset_stable_current_us(uint64_t us);
-
-/**
- * Check if the battery charging current is stable by examining the timestamp.
- *
- * @return true if stable timestamp expired, false otherwise.
- */
-bool charge_is_current_stable(void);
-
-#endif /* __CROS_EC_CHARGE_STATE_V2_H */
diff --git a/include/charger.h b/include/charger.h
index f097f564a9..0f5a9b3e7c 100644
--- a/include/charger.h
+++ b/include/charger.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,6 +10,7 @@
 
 #include "common.h"
 #include "ocpc.h"
+#include "stdbool.h"
 
 /* Charger information
  * voltage unit: mV
@@ -49,7 +50,7 @@ struct charger_drv {
 	enum ec_error_list (*post_init)(int chgnum);
 
 	/* Get charger information */
-	const struct charger_info * (*get_info)(int chgnum);
+	const struct charger_info *(*get_info)(int chgnum);
 
 	/* Get smart battery charger status. Supported flags may vary. */
 	enum ec_error_list (*get_status)(int chgnum, int *status);
@@ -84,6 +85,10 @@ struct charger_drv {
 	enum ec_error_list (*get_voltage)(int chgnum, int *voltage);
 	enum ec_error_list (*set_voltage)(int chgnum, int voltage);
 
+	/* Get the measured charge current and voltage in mA/mV */
+	enum ec_error_list (*get_actual_current)(int chgnum, int *current);
+	enum ec_error_list (*get_actual_voltage)(int chgnum, int *voltage);
+
 	/* Discharge battery when on AC power. */
 	enum ec_error_list (*discharge_on_ac)(int chgnum, int enable);
 
@@ -91,14 +96,24 @@ struct charger_drv {
 	enum ec_error_list (*get_vbus_voltage)(int chgnum, int port,
 					       int *voltage);
 
+	/* Get the Vsys voltage (mV) from the charger */
+	enum ec_error_list (*get_vsys_voltage)(int chgnum, int port,
+					       int *voltage);
+
 	/* Set desired input current value */
-	enum ec_error_list (*set_input_current)(int chgnum, int input_current);
+	enum ec_error_list (*set_input_current_limit)(int chgnum,
+						      int input_current);
+
+	/* Get input current limit */
+	enum ec_error_list (*get_input_current_limit)(int chgnum,
+						      int *input_current);
 
 	/* Get actual input current value */
 	enum ec_error_list (*get_input_current)(int chgnum, int *input_current);
 
 	enum ec_error_list (*manufacturer_id)(int chgnum, int *id);
 	enum ec_error_list (*device_id)(int chgnum, int *id);
+	enum ec_error_list (*set_frequency)(int chgnum, int freq_khz);
 	enum ec_error_list (*get_option)(int chgnum, int *option);
 	enum ec_error_list (*set_option)(int chgnum, int option);
 
@@ -112,11 +127,41 @@ struct charger_drv {
 	/*
 	 * Some chargers can perform VSYS output compensation.  Configure the
 	 * charger IC with the right parameters.
+	 *
+	 * Returns EC_ERROR_UNIMPLEMENTED if further action is required from the
+	 * OCPC control loop (which is typical), EC_SUCCESS if no further action
+	 * is required, or any other status on error.
 	 */
 	enum ec_error_list (*set_vsys_compensation)(int chgnum,
 						    struct ocpc_data *o,
 						    int current_ma,
 						    int voltage_mv);
+
+	/* Is the input current limit reached? */
+	enum ec_error_list (*is_icl_reached)(int chgnum, bool *reached);
+
+	/* Enable/disable linear charging */
+	enum ec_error_list (*enable_linear_charge)(int chgnum, bool enable);
+
+	/*
+	 * Enable/disable bypass mode
+	 *
+	 * Callers are responsible for checking required conditions beforehand.
+	 * (e.g supplier == CHARGE_SUPPLIER_DEDICATED, 20 V < input_voltage)
+	 */
+	enum ec_error_list (*enable_bypass_mode)(int chgnum, bool enable);
+
+	/*
+	 * Get the number of battery cells from charging mode set by sensing an
+	 * external resistor
+	 */
+	enum ec_error_list (*get_battery_cells)(int chgnum, int *cells);
+
+	/* Dumps charger registers */
+	void (*dump_registers)(int chgnum);
+
+	/* Dumps prochot status information */
+	void (*dump_prochot)(int chgnum);
 };
 
 struct charger_config_t {
@@ -151,13 +196,13 @@ enum chg_id {
 void charger_get_params(struct charger_params *chg);
 
 /* Bits to indicate which fields of struct charger_params could not be read */
-#define CHG_FLAG_BAD_CURRENT		0x00000001
-#define CHG_FLAG_BAD_VOLTAGE		0x00000002
-#define CHG_FLAG_BAD_INPUT_CURRENT	0x00000004
-#define CHG_FLAG_BAD_STATUS		0x00000008
-#define CHG_FLAG_BAD_OPTION		0x00000010
+#define CHG_FLAG_BAD_CURRENT 0x00000001
+#define CHG_FLAG_BAD_VOLTAGE 0x00000002
+#define CHG_FLAG_BAD_INPUT_CURRENT 0x00000004
+#define CHG_FLAG_BAD_STATUS 0x00000008
+#define CHG_FLAG_BAD_OPTION 0x00000010
 /* All of the above CHG_FLAG_BAD_* bits */
-#define CHG_FLAG_BAD_ANY                0x0000001f
+#define CHG_FLAG_BAD_ANY 0x0000001f
 
 /**
  * Return the closest match the charger can supply to the requested current.
@@ -238,12 +283,19 @@ enum ec_error_list charger_set_current(int chgnum, int current);
 enum ec_error_list charger_get_voltage(int chgnum, int *voltage);
 enum ec_error_list charger_set_voltage(int chgnum, int voltage);
 
+/* Get the measured charge current and voltage in mA/mV */
+enum ec_error_list charger_get_actual_current(int chgnum, int *current);
+enum ec_error_list charger_get_actual_voltage(int chgnum, int *voltage);
+
 /* Discharge battery when on AC power. */
 enum ec_error_list charger_discharge_on_ac(int enable);
 
 /* Get the VBUS voltage (mV) from the charger */
 enum ec_error_list charger_get_vbus_voltage(int port, int *voltage);
 
+/* Get the Vsys voltage (mV) from the charger */
+enum ec_error_list charger_get_vsys_voltage(int port, int *voltage);
+
 /* Custom board function to discharge battery when on AC power */
 int board_discharge_on_ac(int enable);
 
@@ -255,19 +307,49 @@ int charger_get_system_power(void);
 
 /* Other parameters that may be charger-specific, but are common so far. */
 
-/* Set desired input current value */
-enum ec_error_list charger_set_input_current(int chgnum, int input_current);
+/**
+ * Set desired input current limit
+ *
+ * Sets the hard limit of the input current (from AC).
+ *
+ * @param chgnum		charger IC index
+ * @param input_current		The current limit in mA.
+ *
+ * @return EC_SUCCESS on success, an error otherwise.
+ */
+enum ec_error_list charger_set_input_current_limit(int chgnum,
+						   int input_current);
+
+/**
+ * Get desired input current limit
+ *
+ * Gets the hard limit of the input current (from AC).
+ *
+ * @param chgnum		charger IC index
+ * @param input_current		The current limit in mA.
+ *
+ * @return EC_SUCCESS on success, an error otherwise.
+ */
+enum ec_error_list charger_get_input_current_limit(int chgnum,
+						   int *input_current);
 
-/*
+/**
  * Get actual input current value.
+ *
  * Actual input current may be less than the desired input current set
  * due to current ratings of the wall adapter.
+ *
+ * @param chgnum		charger IC index
+ * @param input_current		The input current in mA.
+ *
+ * @return EC_SUCCESS on success, an error otherwise.
  */
 enum ec_error_list charger_get_input_current(int chgnum, int *input_current);
 
 enum ec_error_list charger_manufacturer_id(int *id);
 enum ec_error_list charger_device_id(int *id);
 enum ec_error_list charger_get_option(int *option);
+enum ec_error_list charger_set_frequency(int freq_khz);
 enum ec_error_list charger_set_option(int option);
 enum ec_error_list charger_set_hw_ramp(int enable);
 
@@ -289,11 +371,81 @@ enum ec_error_list charger_set_vsys_compensation(int chgnum,
 						 int current_ma,
 						 int voltage_mv);
 
+/**
+ * Is the input current limit been reached?
+ *
+ * @param chgnum: Active charge port
+ * @param reached: Pointer to reached
+ * @return EC_SUCCESS on success, error otherwise.
+ */
+enum ec_error_list charger_is_icl_reached(int chgnum, bool *reached);
+
+/**
+ * Enable/disable linear charging
+ *
+ * For charger ICs that support it, this allows the charger IC to operate the
+ * BFET in the linear region.
+ *
+ * @param chgnum: Active charge port
+ * @param enable: Whether to enable or disable linear charging.
+ * @return EC_SUCCESS on success, error otherwise.
+ */
+enum ec_error_list charger_enable_linear_charge(int chgnum, bool enable);
+
+/**
+ * Enable/disable bypass mode
+ *
+ * Bypass mode allows AC power to be supplied directly to the system rail
+ * instead of going through the charger.
+ *
+ * @param chgnum: Active charge port
+ * @param enable: Whether to enable or disable bypass mode.
+ * @return EC_SUCCESS on success, error otherwise.
+ */
+enum ec_error_list charger_enable_bypass_mode(int chgnum, bool enable);
+
+/**
+ * Get the charger configuration for the number of battery cells
+ *
+ * The default charging mode is configured by sensing an external
+ * resistor. The number of battery cells can be determined from the
+ * charging mode.
+ *
+ * @param chgnum: Active charge port.
+ * @param cells: The number of battery cells.
+ *
+ * @return EC_SUCCESS on success, an error otherwise.
+ */
+enum ec_error_list charger_get_battery_cells(int chgnum, int *cells);
+
 /*
  * Print all charger info for debugging purposes
  * @param chgnum: charger IC index.
  */
 void print_charger_debug(int chgnum);
 
-#endif /* __CROS_EC_CHARGER_H */
+/*
+ * Print prochot status for debugging purposes
+ * @param chgnum: charger IC index.
+ */
+void print_charger_prochot(int chgnum);
 
+/**
+ * Get the value of CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON
+ */
+int charger_get_min_bat_pct_for_power_on(void);
+
+/* Wake up the task when something important happens */
+void charge_wakeup(void);
+
+/*
+ * Ask the charger for some voltage and current. If either value is 0,
+ * charging is disabled; otherwise it's enabled. Negative values are ignored.
+ *
+ * @param use_curr Use values from requested voltage and current (otherwise use
+ * 0 for both)
+ * @param is_full Battery is full
+ */
+int charge_request(bool use_curr, bool is_full);
+
+#endif /* __CROS_EC_CHARGER_H */
diff --git a/include/charger_base.h b/include/charger_base.h
new file mode 100644
index 0000000000..efe4a6885f
--- /dev/null
+++ b/include/charger_base.h
@@ -0,0 +1,64 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Charger functions related to a connected keyboard called a 'base' */
+
+#ifndef __CROS_EC_CHARGER_BASE_H
+#define __CROS_EC_CHARGER_BASE_H
+
+#include <stdbool.h>
+
+struct charge_state_data;
+
+/* allocate power between the base and the lid */
+void base_charge_allocate_input_current_limit(
+	const struct charge_state_data *curr, bool is_full, bool debugging);
+
+/*
+ * Check base external-power settings and react as needed
+ *
+ * @param ac Current ac value from struct charge_state_data
+ * @param prev_ac Previous value of ac
+ * Returns true if ac should be zeroed, false to leave it along
+ */
+bool base_check_extpower(int ac, int prev_ac);
+
+/* Update base battery information */
+void base_update_battery_info(void);
+
+#ifdef CONFIG_EC_EC_COMM_BATTERY_CLIENT
+/* Check if there is a base and it is connected */
+bool base_connected(void);
+
+#else
+static inline bool base_connected(void)
+{
+	return false;
+}
+#endif
+
+/* Set up the charger task for the base */
+void charger_base_setup(void);
+
+/* Check if charge_base has changed since last time */
+bool charger_base_charge_changed(void);
+
+/* Update prev_charge_base with charge_base */
+void charger_base_charge_update(void);
+
+/* Show the current charge level of the base on the console */
+void charger_base_show_charge(void);
+
+/* Check if the base charge is near full */
+bool charger_base_charge_near_full(void);
+
+/* Get the base input-voltage */
+int charger_base_get_input_voltage(const struct charge_state_data *curr);
+
+/* Set the input voltage for the base */
+void charger_base_set_input_voltage(struct charge_state_data *curr,
+				    int input_voltage);
+
+#endif /* __CROS_EC_CHARGER_BASE_H */
diff --git a/include/charger_detect.h b/include/charger_detect.h
index ae2001e418..7371583cd8 100644
--- a/include/charger_detect.h
+++ b/include/charger_detect.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/charger_profile_override.h b/include/charger_profile_override.h
index 091eb11946..4648fb0ced 100644
--- a/include/charger_profile_override.h
+++ b/include/charger_profile_override.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,9 +8,9 @@
 #ifndef __CROS_EC_CHARGER_PROFILE_OVERRIDE_H
 #define __CROS_EC_CHARGER_PROFILE_OVERRIDE_H
 
-#include "charge_state_v2.h"
+#include "charge_state.h"
 
-#define TEMPC_TENTHS_OF_DEG(c) ((c) * 10)
+#define TEMPC_TENTHS_OF_DEG(c) ((c)*10)
 
 #define CHARGER_PROF_TEMP_C_LAST_RANGE 0xFFFF
 
@@ -69,10 +69,11 @@ int charger_profile_override(struct charge_state_data *curr);
  *  <0     An error occurred. The poll time will be shorter than usual.
  *         Too many errors in a row may trigger some corrective action.
  */
-int charger_profile_override_common(struct charge_state_data *curr,
-			const struct fast_charge_params *fast_chg_params,
-			const struct fast_charge_profile **prev_chg_prof_info,
-			int batt_vtg_max);
+int charger_profile_override_common(
+	struct charge_state_data *curr,
+	const struct fast_charge_params *fast_chg_params,
+	const struct fast_charge_profile **prev_chg_prof_info,
+	int batt_vtg_max);
 
 /*
  * Access to custom profile params through host commands.
diff --git a/include/chipset.h b/include/chipset.h
index e2c1421ec6..f25ad2c329 100644
--- a/include/chipset.h
+++ b/include/chipset.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,7 @@
 #include "common.h"
 #include "compile_time_macros.h"
 #include "ec_commands.h"
-#include "gpio.h"
+#include "gpio_signal.h"
 #include "stddef.h"
 
 /*
@@ -29,81 +29,18 @@
  * I'll compare it myself with the state(s) I want."
  */
 enum chipset_state_mask {
-	CHIPSET_STATE_HARD_OFF = 0x01,   /* Hard off (G3) */
-	CHIPSET_STATE_SOFT_OFF = 0x02,   /* Soft off (S5) */
-	CHIPSET_STATE_SUSPEND  = 0x04,   /* Suspend (S3) */
-	CHIPSET_STATE_ON       = 0x08,   /* On (S0) */
-	CHIPSET_STATE_STANDBY  = 0x10,   /* Standby (S0ix) */
+	CHIPSET_STATE_HARD_OFF = 0x01, /* Hard off (G3) */
+	CHIPSET_STATE_SOFT_OFF = 0x02, /* Soft off (S5, S4) */
+	CHIPSET_STATE_SUSPEND = 0x04, /* Suspend (S3) */
+	CHIPSET_STATE_ON = 0x08, /* On (S0) */
+	CHIPSET_STATE_STANDBY = 0x10, /* Standby (S0ix) */
 	/* Common combinations */
-	CHIPSET_STATE_ANY_OFF = (CHIPSET_STATE_HARD_OFF |
-				 CHIPSET_STATE_SOFT_OFF),  /* Any off state */
+	CHIPSET_STATE_ANY_OFF =
+		(CHIPSET_STATE_HARD_OFF | CHIPSET_STATE_SOFT_OFF), /* Any off
+								      state */
 	/* This combination covers any kind of suspend i.e. S3 or S0ix. */
-	CHIPSET_STATE_ANY_SUSPEND = (CHIPSET_STATE_SUSPEND |
-				     CHIPSET_STATE_STANDBY),
-};
-
-/*
- * Reason codes used by the AP after a shutdown to figure out why it was reset
- * by the EC.  These are sent in EC commands.  Therefore, to maintain protocol
- * compatibility:
- * - New entries must be inserted prior to the _COUNT field
- * - If an existing entry is no longer in service, it must be replaced with a
- *   RESERVED entry instead.
- * - The semantic meaning of an entry should not change.
- * - Do not exceed 2^15 - 1 for reset reasons or 2^16 - 1 for shutdown reasons.
- */
-enum chipset_reset_reason {
-	CHIPSET_RESET_BEGIN = 0,
-	CHIPSET_RESET_UNKNOWN = CHIPSET_RESET_BEGIN,
-	/* Custom reason defined by a board.c or baseboard.c file */
-	CHIPSET_RESET_BOARD_CUSTOM,
-	/* Believe that the AP has hung */
-	CHIPSET_RESET_HANG_REBOOT,
-	/* Reset by EC console command */
-	CHIPSET_RESET_CONSOLE_CMD,
-	/* Reset by EC host command */
-	CHIPSET_RESET_HOST_CMD,
-	/* Keyboard module reset key combination */
-	CHIPSET_RESET_KB_SYSRESET,
-	/* Keyboard module warm reboot */
-	CHIPSET_RESET_KB_WARM_REBOOT,
-	/* Debug module warm reboot */
-	CHIPSET_RESET_DBG_WARM_REBOOT,
-	/* I cannot self-terminate.  You must lower me into the steel. */
-	CHIPSET_RESET_AP_REQ,
-	/* Reset as side-effect of startup sequence */
-	CHIPSET_RESET_INIT,
-	/* EC detected an AP watchdog event. */
-	CHIPSET_RESET_AP_WATCHDOG,
-	CHIPSET_RESET_COUNT,
-};
-
-/*
- * Hard shutdowns are logged on the same path as resets.
- */
-enum chipset_shutdown_reason {
-	CHIPSET_SHUTDOWN_BEGIN = BIT(15),
-	CHIPSET_SHUTDOWN_POWERFAIL = CHIPSET_SHUTDOWN_BEGIN,
-	/* Forcing a shutdown as part of EC initialization */
-	CHIPSET_SHUTDOWN_INIT,
-	/* Custom reason on a per-board basis. */
-	CHIPSET_SHUTDOWN_BOARD_CUSTOM,
-	/* This is a reason to inhibit startup, not cause shut down. */
-	CHIPSET_SHUTDOWN_BATTERY_INHIBIT,
-	/* A power_wait_signal is being asserted */
-	CHIPSET_SHUTDOWN_WAIT,
-	/* Critical battery level. */
-	CHIPSET_SHUTDOWN_BATTERY_CRIT,
-	/* Because you told me to. */
-	CHIPSET_SHUTDOWN_CONSOLE_CMD,
-	/* Forcing a shutdown to effect entry to G3. */
-	CHIPSET_SHUTDOWN_G3,
-	/* Force shutdown due to over-temperature. */
-	CHIPSET_SHUTDOWN_THERMAL,
-	/* Force a chipset shutdown from the power button through EC */
-	CHIPSET_SHUTDOWN_BUTTON,
-
-	CHIPSET_SHUTDOWN_COUNT,
+	CHIPSET_STATE_ANY_SUSPEND =
+		(CHIPSET_STATE_SUSPEND | CHIPSET_STATE_STANDBY),
 };
 
 enum critical_shutdown {
@@ -112,7 +49,7 @@ enum critical_shutdown {
 	CRITICAL_SHUTDOWN_CUTOFF,
 };
 
-#ifdef HAS_TASK_CHIPSET
+#ifdef CONFIG_AP_POWER_CONTROL
 
 /**
  * Check if chipset is in a given state.
@@ -157,10 +94,17 @@ void chipset_throttle_cpu(int throttle);
  */
 void chipset_force_shutdown(enum chipset_shutdown_reason reason);
 
+/**
+ * Attempt to power on the chipset if it's in S4/S5/G3.
+ *
+ * This does nothing if in S3/S0ix/S0.
+ */
+void chipset_power_on(void);
+
 /**
  * Reset the CPU and/or chipset.
  */
-void chipset_reset(enum chipset_reset_reason reason);
+void chipset_reset(enum chipset_shutdown_reason reason);
 
 /**
  * Interrupt handler to power GPIO inputs.
@@ -182,7 +126,12 @@ void chipset_pre_init_callback(void);
  */
 void init_reset_log(void);
 
-#else /* !HAS_TASK_CHIPSET */
+#else /* !CONFIG_AP_POWER_CONTROL */
+
+#if defined(CONFIG_TEST_USB_PD_POLICY) || defined(CONFIG_SOC_FAMILY_INTEL_ISH)
+int chipset_in_state(int state_mask);
+
+#else
 
 /* When no chipset is present, assume it is always off. */
 static inline int chipset_in_state(int state_mask)
@@ -190,30 +139,56 @@ static inline int chipset_in_state(int state_mask)
 	return state_mask & CHIPSET_STATE_ANY_OFF;
 }
 
+#endif
+
 static inline int chipset_in_or_transitioning_to_state(int state_mask)
 {
 	return state_mask & CHIPSET_STATE_ANY_OFF;
 }
 
-static inline void chipset_exit_hard_off(void) { }
-static inline void chipset_throttle_cpu(int throttle) { }
+static inline void chipset_exit_hard_off(void)
+{
+}
+static inline void chipset_throttle_cpu(int throttle)
+{
+}
 static inline void chipset_force_shutdown(enum chipset_shutdown_reason reason)
 {
 }
 
-static inline void chipset_reset(enum chipset_reset_reason reason) { }
-static inline void power_interrupt(enum gpio_signal signal) { }
-static inline void chipset_handle_espi_reset_assert(void) { }
-static inline void chipset_handle_reboot(void) { }
-static inline void chipset_reset_request_interrupt(enum gpio_signal signal) { }
-static inline void chipset_warm_reset_interrupt(enum gpio_signal signal) { }
-static inline void chipset_ap_rst_interrupt(enum gpio_signal signal) { }
-static inline void chipset_power_good_interrupt(enum gpio_signal signal) { }
-static inline void chipset_watchdog_interrupt(enum gpio_signal signal) { }
+static inline void chipset_reset(enum chipset_shutdown_reason reason)
+{
+}
+static inline void power_interrupt(enum gpio_signal signal)
+{
+}
+static inline void chipset_handle_espi_reset_assert(void)
+{
+}
+static inline void chipset_handle_reboot(void)
+{
+}
+static inline void chipset_reset_request_interrupt(enum gpio_signal signal)
+{
+}
+static inline void chipset_warm_reset_interrupt(enum gpio_signal signal)
+{
+}
+static inline void chipset_ap_rst_interrupt(enum gpio_signal signal)
+{
+}
+static inline void chipset_power_good_interrupt(enum gpio_signal signal)
+{
+}
+static inline void chipset_watchdog_interrupt(enum gpio_signal signal)
+{
+}
 
-static inline void init_reset_log(void) { }
+static inline void init_reset_log(void)
+{
+}
 
-#endif /* !HAS_TASK_CHIPSET */
+#endif /* !CONFIG_AP_POWER_CONTROL */
 
 /**
  * Optional chipset check if PLTRST# is valid.
@@ -245,7 +220,7 @@ void chipset_ap_rst_interrupt(enum gpio_signal signal);
 /**
  * GPIO interrupt handler of warm reset signal from servo or H1.
  *
- * It is used in Qualcomm chipset power sequence.
+ * It is used in Qualcomm/MediaTek chipset power sequence.
  */
 void chipset_warm_reset_interrupt(enum gpio_signal signal);
 
@@ -272,8 +247,24 @@ void chipset_watchdog_interrupt(enum gpio_signal signal);
  * @param now                Current time
  * @return Action to take
  */
-__override_proto enum critical_shutdown board_system_is_idle(
-		uint64_t last_shutdown_time, uint64_t *target, uint64_t now);
+__override_proto enum critical_shutdown
+board_system_is_idle(uint64_t last_shutdown_time, uint64_t *target,
+		     uint64_t now);
+
+/**
+ * Check if chipset is in low power mode
+ *
+ * Newer AMD SoCs support modern standby as well as the AMD version of runtime
+ * low power states. To coordinate these runtime low-power states with EC, the
+ * APU communicates the transition through the eSPI virtual wires. On transition
+ * to the low power state, APU transmits the corresponding virtual wire to EC.
+ * Any downstream transaction to EC or assertion of ESPI_ALERT# is treated as exit
+ * from the low power state.
+ * Sequence for all low power state (modern standby/SLP_MSC, Z8/9/10) are identical.
+ *
+ * @return non-zero if the chipset is in low power mode
+ */
+__override_proto int chipset_in_low_power_mode(void);
 
 #ifdef CONFIG_CMD_AP_RESET_LOG
 
@@ -289,14 +280,24 @@ void report_ap_reset(enum chipset_shutdown_reason reason);
  * @param num_reset_log_entries   Number of items in reset_log_entries.
  * @param resets_since_ec_boot    Number of AP resets since EC boot.
  */
-test_mockable enum ec_error_list
+enum ec_error_list
 get_ap_reset_stats(struct ap_reset_log_entry *reset_log_entries,
 		   size_t num_reset_log_entries,
 		   uint32_t *resets_since_ec_boot);
 
+/**
+ * Check the reason given in the last call to report_ap_reset() .
+ *
+ * @return Reason argument that was passed to the last call to
+ * report_ap_reset(). Zero if report_ap_reset() has not been called.
+ */
+enum chipset_shutdown_reason chipset_get_shutdown_reason(void);
+
 #else
 
-static inline void report_ap_reset(enum chipset_shutdown_reason reason) { }
+static inline void report_ap_reset(enum chipset_shutdown_reason reason)
+{
+}
 
 test_mockable_static_inline enum ec_error_list
 get_ap_reset_stats(struct ap_reset_log_entry *reset_log_entries,
@@ -305,6 +306,27 @@ get_ap_reset_stats(struct ap_reset_log_entry *reset_log_entries,
 	return EC_SUCCESS;
 }
 
+static inline enum chipset_shutdown_reason chipset_get_shutdown_reason(void)
+{
+	return CHIPSET_RESET_UNKNOWN;
+}
+
 #endif /* !CONFIG_CMD_AP_RESET_LOG */
 
-#endif  /* __CROS_EC_CHIPSET_H */
+#ifdef TEST_BUILD
+/**
+ * @brief Gets the number of AP resets since the EC booted. Takes the reset log
+ *        mutex for thread safety.
+ *
+ * @return uint32_t AP reset count
+ */
+uint32_t test_chipset_get_ap_resets_since_ec_boot(void);
+
+/**
+ * @brief Corrupts the stored reset log checksum, which forces init_reset_log()
+ *        to wipe the log and fully reset.
+ */
+void test_chipset_corrupt_reset_log_checksum(void);
+#endif /* TEST_BUILD */
+
+#endif /* __CROS_EC_CHIPSET_H */
diff --git a/include/clock.h b/include/clock.h
index acbd3fbcf5..3829beb6ec 100644
--- a/include/clock.h
+++ b/include/clock.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,6 +10,10 @@
 
 #include "common.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /**
  * Set the CPU clocks and PLLs.
  */
@@ -36,6 +40,13 @@ int clock_get_freq(void);
  */
 void clock_enable_module(enum module_id module, int enable);
 
+/**
+ * Query whether clock is enabled for given module.
+ *
+ * @return Non-zero if enabled, zero if disabled.
+ */
+int clock_is_module_enabled(enum module_id module);
+
 /**
  * Enable or disable the PLL.
  *
@@ -71,10 +82,10 @@ enum bus_type {
 void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles);
 
 /* Clock gate control modes for clock_enable_peripheral() */
-#define CGC_MODE_RUN    BIT(0)
-#define CGC_MODE_SLEEP  BIT(1)
+#define CGC_MODE_RUN BIT(0)
+#define CGC_MODE_SLEEP BIT(1)
 #define CGC_MODE_DSLEEP BIT(2)
-#define CGC_MODE_ALL    (CGC_MODE_RUN | CGC_MODE_SLEEP | CGC_MODE_DSLEEP)
+#define CGC_MODE_ALL (CGC_MODE_RUN | CGC_MODE_SLEEP | CGC_MODE_DSLEEP)
 
 /**
  * Enable clock to peripheral by setting the CGC register pertaining
@@ -101,4 +112,8 @@ void clock_disable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode);
  */
 void clock_refresh_console_in_use(void);
 
-#endif  /* __CROS_EC_CLOCK_H */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CROS_EC_CLOCK_H */
diff --git a/include/common.h b/include/common.h
index cd586465cf..85610be18e 100644
--- a/include/common.h
+++ b/include/common.h
@@ -1,21 +1,44 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* common.h - Common includes for Chrome EC */
 
+/*
+ * TODO(b/272518464): Work around coreboot GCC preprocessor bug.
+ * #line marks the *next* line, so it is off by one.
+ */
+#line 13
+
 #ifndef __CROS_EC_COMMON_H
 #define __CROS_EC_COMMON_H
 
-#include <stdint.h>
-#include <inttypes.h>
-
 #include "compile_time_macros.h"
 
+#include <inttypes.h>
+#include <stdint.h>
+
 #ifdef CONFIG_ZEPHYR
-#include <sys/util.h>
-#include <toolchain.h>
+#include "fpu.h"
+
+#include <zephyr/sys/util.h>
+#include <zephyr/toolchain.h>
+#ifdef CONFIG_ZTEST
+#define TEST_BUILD
+#endif /* CONFIG_ZTEST */
+#endif /* CONFIG_ZEPHYR */
+
+/*
+ * Define a new macro (FIXED_SECTION) to abstract away the linker details
+ * between platform/ec builds and Zephyr. Each build has a slightly different
+ * way of ensuring that the given section is in the same relative location in
+ * both the RO/RW images.
+ */
+#if defined(CONFIG_ZEPHYR) && !defined(CONFIG_SOC_FAMILY_INTEL_ISH)
+#define FIXED_SECTION(name) __attribute__((section(".fixed." name)))
+#else
+#define FIXED_SECTION(name) __attribute__((section(".rodata." name)))
 #endif
 
 /*
@@ -30,7 +53,7 @@
  *     #define BAZ CONCAT2(BAR, FOO)
  * Will evaluate to BAR1, which then evaluates to 42.
  */
-#define CONCAT_STAGE_1(w, x, y, z) w ## x ## y ## z
+#define CONCAT_STAGE_1(w, x, y, z) w##x##y##z
 #define CONCAT2(w, x) CONCAT_STAGE_1(w, x, , )
 #define CONCAT3(w, x, y) CONCAT_STAGE_1(w, x, y, )
 #define CONCAT4(w, x, y, z) CONCAT_STAGE_1(w, x, y, z)
@@ -42,20 +65,20 @@
  * is safe with regards to using nested macros and defined arguments.
  */
 #ifndef CONFIG_ZEPHYR
-#define STRINGIFY0(name)  #name
-#define STRINGIFY(name)  STRINGIFY0(name)
-#endif   /* CONFIG_ZEPHYR */
+#define STRINGIFY0(name) #name
+#define STRINGIFY(name) STRINGIFY0(name)
+#endif /* CONFIG_ZEPHYR */
 
 /* Macros to access registers */
 #define REG64_ADDR(addr) ((volatile uint64_t *)(addr))
 #define REG32_ADDR(addr) ((volatile uint32_t *)(addr))
 #define REG16_ADDR(addr) ((volatile uint16_t *)(addr))
-#define REG8_ADDR(addr)  ((volatile uint8_t  *)(addr))
+#define REG8_ADDR(addr) ((volatile uint8_t *)(addr))
 
 #define REG64(addr) (*REG64_ADDR(addr))
 #define REG32(addr) (*REG32_ADDR(addr))
 #define REG16(addr) (*REG16_ADDR(addr))
-#define REG8(addr)  (*REG8_ADDR(addr))
+#define REG8(addr) (*REG8_ADDR(addr))
 
 /*
  * Define __aligned(n) and __packed if someone hasn't beat us to it.  Linux
@@ -106,17 +129,7 @@
  * Useful for C functions called only from assembly or through special sections.
  */
 #ifndef __keep
-#define __keep __attribute__((used)) __visible
-#endif
-
-/*
- * Place the object in the .bss.slow region.
- *
- * On boards with unoptimized RAM there is no penalty and it simply is appended
- * to the .bss section.
- */
-#ifndef __bss_slow
-#define __bss_slow __attribute__((section(".bss.slow")))
+#define __keep __attribute__((used))
 #endif
 
 /*
@@ -129,7 +142,11 @@
  * linked into the .rodata section.
  */
 #ifndef __init_rom
+#ifndef CONFIG_ZEPHYR
 #define __init_rom __attribute__((section(".init.rom")))
+#else
+#define __init_rom
+#endif
 #endif
 
 /* gcc does not support __has_feature */
@@ -174,7 +191,24 @@
  */
 #define __override_proto
 #define __override
-#define __overridable	__attribute__((weak))
+#define __overridable __attribute__((weak))
+
+/*
+ * Attribute that will generate a compiler warning if the return value is not
+ * used.
+ */
+#define __warn_unused_result __attribute__((warn_unused_result))
+
+/**
+ * @brief Attribute used to annotate intentional fallthrough between switch
+ * labels.
+ *
+ * See https://clang.llvm.org/docs/AttributeReference.html#fallthrough and
+ * https://gcc.gnu.org/onlinedocs/gcc/Statement-Attributes.html.
+ */
+#ifndef __fallthrough
+#define __fallthrough __attribute__((fallthrough))
+#endif
 
 /*
  * Macros for combining bytes into larger integers. _LE and _BE signify little
@@ -188,35 +222,94 @@
 
 #define UINT32_FROM_BYTES(lsb, byte1, byte2, msb) \
 	((lsb) | (byte1) << 8 | (byte2) << 16 | (msb) << 24)
-#define UINT32_FROM_BYTE_ARRAY_LE(data, lsb_index) \
+#define UINT32_FROM_BYTE_ARRAY_LE(data, lsb_index)                      \
 	UINT32_FROM_BYTES((data)[(lsb_index)], (data)[(lsb_index) + 1], \
 			  (data)[(lsb_index) + 2], (data)[(lsb_index) + 3])
-#define UINT32_FROM_BYTE_ARRAY_BE(data, msb_index) \
+#define UINT32_FROM_BYTE_ARRAY_BE(data, msb_index)                          \
 	UINT32_FROM_BYTES((data)[(msb_index) + 3], (data)[(msb_index) + 2], \
 			  (data)[(msb_index) + 1], (data)[(msb_index)])
 
 /* There isn't really a better place for this */
 #define C_TO_K(temp_c) ((temp_c) + 273)
-#define K_TO_C(temp_c) ((temp_c) - 273)
-#define CELSIUS_TO_DECI_KELVIN(temp_c) ((temp_c) * 10 + 2731)
-#define DECI_KELVIN_TO_CELSIUS(temp_dk) ((temp_dk - 2731) / 10)
+#define K_TO_C(temp_c) ((temp_c)-273)
+/*
+ * round_divide is part of math_utils, so you may need to import math_utils.h
+ * and link math_utils.o if you use the following macros.
+ */
+#define CELSIUS_TO_DECI_KELVIN(temp_c) \
+	(round_divide(CELSIUS_TO_MILLI_KELVIN(temp_c), 100))
+#define DECI_KELVIN_TO_CELSIUS(temp_dk) (MILLI_KELVIN_TO_CELSIUS((temp_dk)*100))
+#define MILLI_KELVIN_TO_MILLI_CELSIUS(temp_mk) ((temp_mk)-273150)
+#define MILLI_CELSIUS_TO_MILLI_KELVIN(temp_mc) ((temp_mc) + 273150)
+#define MILLI_KELVIN_TO_KELVIN(temp_mk) (round_divide((temp_mk), 1000))
+#define KELVIN_TO_MILLI_KELVIN(temp_k) ((temp_k)*1000)
+#define CELSIUS_TO_MILLI_KELVIN(temp_c) \
+	(MILLI_CELSIUS_TO_MILLI_KELVIN((temp_c)*1000))
+#define MILLI_KELVIN_TO_CELSIUS(temp_mk) \
+	(round_divide(MILLI_KELVIN_TO_MILLI_CELSIUS(temp_mk), 1000))
 
 /* Calculate a value with error margin considered. For example,
  * TARGET_WITH_MARGIN(X, 5) returns X' where X' * 100.5% is almost equal to
  * but does not exceed X. */
 #define TARGET_WITH_MARGIN(target, tenths_percent) \
-	(((target) * 1000) / (1000 + (tenths_percent)))
+	(((target)*1000) / (1000 + (tenths_percent)))
 
 /* Call a function, and return the error value unless it returns EC_SUCCESS. */
-#define RETURN_ERROR(fn) do { \
-	int error = (fn); \
-	if (error != EC_SUCCESS) \
-		return error; \
-} while (0)
+#define RETURN_ERROR(fn)                 \
+	do {                             \
+		int error = (fn);        \
+		if (error != EC_SUCCESS) \
+			return error;    \
+	} while (0)
+
+/*
+ * Define test_mockable and test_mockable_static for mocking
+ * functions. Don't use test_mockable in .h files.
+ */
+#ifdef TEST_BUILD
+#define test_mockable __attribute__((weak))
+#define test_mockable_static __attribute__((weak))
+#define test_mockable_static_inline __attribute__((weak))
+/*
+ * Tests implemented with ztest add mock implementations that actually return,
+ * so they should not be marked "noreturn". See
+ * test/drivers/default/src/panic_output.c.
+ */
+#ifdef CONFIG_ZTEST
+#define test_mockable_noreturn __attribute__((weak))
+#define test_mockable_static_noreturn __attribute__((weak))
+#else
+#define test_mockable_noreturn noreturn __attribute__((weak))
+#define test_mockable_static_noreturn noreturn __attribute__((weak))
+#endif
+#define test_export_static
+#else
+#define test_mockable
+#define test_mockable_static static
+#define test_mockable_static_inline static inline
+#define test_mockable_noreturn noreturn
+#define test_mockable_static_noreturn static noreturn
+#define test_export_static static
+#endif
 
 /* Include top-level configuration file */
 #include "config.h"
 
+/*
+ * When CONFIG_CHIP_DATA_IN_INIT_ROM is enabled the .data section is linked
+ * into an unused are of flash and excluded from the executable portion of
+ * the RO and RW images to save space.
+ *
+ * The __const_data attribute can be used to force constant data objects
+ * into the .data section instead of the .rodata section for additional
+ * savings.
+ */
+#ifdef CONFIG_CHIP_DATA_IN_INIT_ROM
+#define __const_data __attribute__((section(".data#")))
+#else
+#define __const_data
+#endif
+
 /* Canonical list of module IDs */
 #include "module_id.h"
 
@@ -270,6 +363,9 @@ enum ec_error_list {
 	/* Sometimes operation is expected to have to be repeated. */
 	EC_ERROR_TRY_AGAIN = 26,
 
+	/* Operation was successful but completion is pending. */
+	EC_SUCCESS_IN_PROGRESS = 27,
+
 	/* Verified boot errors */
 	EC_ERROR_VBOOT_SIGNATURE = 0x1000, /* 4096 */
 	EC_ERROR_VBOOT_SIG_MAGIC = 0x1001,
@@ -293,22 +389,6 @@ enum ec_error_list {
 	EC_ERROR_INTERNAL_LAST = 0x1FFFF
 };
 
-/*
- * Define test_mockable and test_mockable_static for mocking
- * functions.
- */
-#ifdef TEST_BUILD
-#define test_mockable __attribute__((weak))
-#define test_mockable_static __attribute__((weak))
-#define test_mockable_static_inline __attribute__((weak))
-#define test_export_static
-#else
-#define test_mockable
-#define test_mockable_static static
-#define test_mockable_static_inline static inline
-#define test_export_static static
-#endif
-
 /*
  * Attribute to define functions to only be used in test code, causing
  * a compiler error if used without TEST_BUILD defined.
@@ -324,8 +404,7 @@ enum ec_error_list {
 
 /*
  * Mark functions that collide with stdlib so they can be hidden when linking
- * against libraries that require stdlib. HIDE_EC_STDLIB should be defined
- * before including common.h from code that links to cstdlib.
+ * against libraries that require stdlib.
  */
 #ifdef TEST_FUZZ
 #define __stdlib_compat __attribute__((visibility("hidden")))
@@ -349,12 +428,12 @@ enum ec_error_list {
  * undefined, rather than defined to something else. This usually
  * involves tricks with __builtin_strcmp.
  */
-#define __cfg_select(cfg, empty, otherwise)     \
+#define __cfg_select(cfg, empty, otherwise) \
 	__cfg_select_1(cfg, empty, otherwise)
 #define __cfg_select_placeholder_ _,
-#define __cfg_select_1(value, empty, otherwise)			  \
+#define __cfg_select_1(value, empty, otherwise) \
 	__cfg_select_2(__cfg_select_placeholder_##value, empty, otherwise)
-#define __cfg_select_2(arg1_or_junk, empty, otherwise)		\
+#define __cfg_select_2(arg1_or_junk, empty, otherwise) \
 	__cfg_select_3(arg1_or_junk _, empty, otherwise)
 #define __cfg_select_3(_ignore1, _ignore2, select, ...) select
 
@@ -363,13 +442,10 @@ enum ec_error_list {
  * handling the __builtin_strcmp trickery where a BUILD_ASSERT is
  * appropriate in the context.
  */
-#define __cfg_select_build_assert(cfg, value, empty, undef)	\
-	__cfg_select(						\
-		value,						\
-		empty,						\
-		BUILD_ASSERT(					\
-			__builtin_strcmp(cfg, #value) == 0);	\
-		undef)
+#define __cfg_select_build_assert(cfg, value, empty, undef)            \
+	__cfg_select(value, empty,                                     \
+		     BUILD_ASSERT(__builtin_strcmp(cfg, #value) == 0); \
+		     undef)
 
 /*
  * Attribute for generating an error if a function is used.
@@ -394,16 +470,16 @@ enum ec_error_list {
  * technique requires that the optimizer be enabled so it can remove
  * the undefined function call.
  */
-#define __config_enabled(cfg, value)					      \
-	__cfg_select(							      \
-		value, 1, ({						      \
-			int __undefined = __builtin_strcmp(cfg, #value) == 0; \
-			extern int IS_ENABLED_BAD_ARGS(void) __error(	      \
-				cfg " must be <blank>, or not defined.");     \
-			if (!__undefined)				      \
-				IS_ENABLED_BAD_ARGS();			      \
-			0;						      \
-		}))
+#define __config_enabled(cfg, value)                                           \
+	__cfg_select(value, 1, ({                                              \
+			     int __undefined =                                 \
+				     __builtin_strcmp(cfg, #value) == 0;       \
+			     extern int IS_ENABLED_BAD_ARGS(void) __error(     \
+				     cfg " must be <blank>, or not defined."); \
+			     if (!__undefined)                                 \
+				     IS_ENABLED_BAD_ARGS();                    \
+			     0;                                                \
+		     }))
 
 /**
  * Checks if a config option is enabled or disabled
@@ -436,7 +512,7 @@ enum ec_error_list {
  * if the config option is enabled by Zephyr's definition.
  */
 #define IS_ENABLED(option) __cfg_select(option, 1, Z_IS_ENABLED1(option))
-#endif  /* CONFIG_ZEPHYR */
+#endif /* CONFIG_ZEPHYR */
 
 /**
  * Makes a global variable static when a config option is enabled,
@@ -447,8 +523,19 @@ enum ec_error_list {
  * This follows the same constraints as IS_ENABLED, the config option
  * should be defined to nothing or undefined.
  */
-#define STATIC_IF(option)						\
+#ifndef CONFIG_ZEPHYR
+#define STATIC_IF(option) \
 	__cfg_select_build_assert(#option, option, static, extern)
+#else
+/*
+ * Version of STATIC_IF for Zephyr, with similar considerations to IS_ENABLED.
+ *
+ * Note, if __cfg_select fails, then we check using Zephyr's COND_CODE_1 macro
+ * to determine if the config option is enabled by Zephyr's definition.
+ */
+#define STATIC_IF(option) \
+	__cfg_select(option, static, COND_CODE_1(option, (static), (extern)))
+#endif /* CONFIG_ZEPHYR */
 
 /**
  * STATIC_IF_NOT is just like STATIC_IF, but makes the variable static
@@ -457,7 +544,16 @@ enum ec_error_list {
  * This is to assert that a variable will go unused with a certain
  * config option.
  */
-#define STATIC_IF_NOT(option)						\
+#ifndef CONFIG_ZEPHYR
+#define STATIC_IF_NOT(option) \
 	__cfg_select_build_assert(#option, option, extern, static)
+#else
+/*
+ * Version of STATIC_IF_NOT for Zephyr, with similar considerations to STATIC_IF
+ * and IS_ENABLED.
+ */
+#define STATIC_IF_NOT(option) \
+	__cfg_select(option, extern, COND_CODE_1(option, (extern), (static)))
+#endif /* CONFIG_ZEPHYR */
 
-#endif  /* __CROS_EC_COMMON_H */
+#endif /* __CROS_EC_COMMON_H */
diff --git a/include/compile_time_macros.h b/include/compile_time_macros.h
index 15432549d3..308498886e 100644
--- a/include/compile_time_macros.h
+++ b/include/compile_time_macros.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,14 +8,24 @@
 #ifndef __CROS_EC_COMPILE_TIME_MACROS_H
 #define __CROS_EC_COMPILE_TIME_MACROS_H
 
+#if defined(__cplusplus) && !defined(CONFIG_ZEPHYR)
+#include <type_traits>
+#endif
+
 /* sys/util.h in zephyr provides equivalents to most of these macros */
 #ifdef CONFIG_ZEPHYR
-#include <sys/util.h>
+#include <zephyr/sys/util.h>
+#endif
+
+#ifdef __cplusplus
+#define _STATIC_ASSERT static_assert
+#else
+#define _STATIC_ASSERT _Static_assert
 #endif
 
 /* Test an important condition at compile time, not run time */
 #define _BA1_(cond, file, line, msg) \
-	_Static_assert(cond, file ":" #line ": " msg)
+	_STATIC_ASSERT(cond, file ":" #line ": " msg)
 #define _BA0_(c, f, l, msg) _BA1_(c, f, l, msg)
 /* Pass in an option message to display after condition */
 
@@ -30,8 +40,12 @@
 #define BUILD_CHECK_INLINE(value, cond_true) ((value) / (!!(cond_true)))
 
 /* Check that the value is an array (not a pointer) */
+#ifdef __cplusplus
+#define _IS_ARRAY(arr) (std::is_array<decltype(arr)>::value)
+#else
 #define _IS_ARRAY(arr) \
 	!__builtin_types_compatible_p(typeof(arr), typeof(&(arr)[0]))
+#endif
 
 /**
  * ARRAY_SIZE - Number of elements in an array.
@@ -55,7 +69,7 @@
 
 /* Just in case - http://gcc.gnu.org/onlinedocs/gcc/Offsetof.html */
 #ifndef offsetof
-#define offsetof(type, member)  __builtin_offsetof(type, member)
+#define offsetof(type, member) __builtin_offsetof(type, member)
 #endif
 
 #define member_size(type, member) sizeof(((type *)0)->member)
@@ -64,9 +78,19 @@
  * Bit operation macros.
  */
 #ifndef CONFIG_ZEPHYR
-#define BIT(nr)			(1U << (nr))
+#define BIT(nr) (1U << (nr))
+/* Set <mask> for <var> if <set> is true or clear <mask> if <set> is false. */
+#define WRITE_MASK(var, mask, set) \
+	((var) = (set) ? ((var) | (mask)) : ((var) & ~(mask)))
+
+/*
+ * Set or clear <bit> of <var> depending on <set>.
+ * It also supports setting and clearing (e.g. SET_BIT, CLR_BIT) macros.
+ */
+#define WRITE_BIT(var, bit, set) WRITE_MASK(var, BIT(bit), set)
+
 #endif
-#define BIT_ULL(nr)		(1ULL << (nr))
+#define BIT_ULL(nr) (1ULL << (nr))
 
 /*
  * Create a bit mask from least significant bit |l|
@@ -82,8 +106,8 @@
  * warnings for BIT(31+1).
  */
 #ifndef CONFIG_ZEPHYR
-#define GENMASK(h, l)     (((BIT(h)<<1)     - 1) ^ (BIT(l)     - 1))
+#define GENMASK(h, l) (((BIT(h) << 1) - 1) ^ (BIT(l) - 1))
+#define GENMASK_ULL(h, l) (((BIT_ULL(h) << 1) - 1) ^ (BIT_ULL(l) - 1))
 #endif
-#define GENMASK_ULL(h, l) (((BIT_ULL(h)<<1) - 1) ^ (BIT_ULL(l) - 1))
 
 #endif /* __CROS_EC_COMPILE_TIME_MACROS_H */
diff --git a/include/compiler.h b/include/compiler.h
index 21e5ae4a47..736fac4850 100644
--- a/include/compiler.h
+++ b/include/compiler.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,7 +9,88 @@
 /*
  * See https://gcc.gnu.org/onlinedocs/cpp/Common-Predefined-Macros.html
  */
+#ifndef CONFIG_ZEPHYR
+/* If building with Zephyr, use its GCC version. */
 #define GCC_VERSION \
 	(__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__)
+#endif /* !CONFIG_ZEPHYR */
+
+/*
+ * The EC codebase assumes that typeof() is available but it is not in Zephyr.
+ * We use an #ifdef since arch/arm/include/aarch32/cortex_m/cmse.h defines this
+ * macro.
+ */
+#ifndef typeof
+#define typeof(x) __typeof__(x)
+#endif
+
+/**
+ * ISO C forbids forward references to enum types, but gcc allows it as long as
+ * the "-pedantic" flag is not used.
+ *
+ * In C++11 and newer, forward references to enums are only allowed if the
+ * underlying type is specified.
+ *
+ * New uses of this macro are strongly discouraged; instead of forward
+ * declaring the enum, provide the definition.
+ *
+ * TODO(http://b/187105190): Remove uses of this macro.
+ */
+#ifdef __cplusplus
+#define FORWARD_DECLARE_ENUM(x) enum x : int
+#else
+#define FORWARD_DECLARE_ENUM(x) enum x
+#endif /* __cplusplus */
+
+#define _DO_PRAGMA(x) _Pragma(#x)
+
+#define _DISABLE_COMPILER_WARNING(compiler, warning) \
+	_DO_PRAGMA(compiler diagnostic push)         \
+	_DO_PRAGMA(compiler diagnostic ignored warning)
+
+#define _ENABLE_COMPILER_WARNING(compiler, warning) \
+	_DO_PRAGMA(compiler diagnostic pop)
+
+/**
+ * Disable the specified compiler warning for both clang and gcc.
+ */
+#define DISABLE_COMPILER_WARNING(warning) \
+	_DISABLE_COMPILER_WARNING(GCC, warning)
+
+/**
+ * Re-enable the specified compiler warning for both clang and gcc. Can only be
+ * used after a call to DISABLE_COMPILER_WARNING.
+ */
+#define ENABLE_COMPILER_WARNING(warning) _ENABLE_COMPILER_WARNING(GCC, warning)
+
+#ifdef __clang__
+/**
+ * Disable the specified compiler warning for clang.
+ */
+#define DISABLE_CLANG_WARNING(warning) _DISABLE_COMPILER_WARNING(clang, warning)
+/**
+ * Re-enable the specified compiler warning for clang. Can only be used after
+ * a call to DISABLE_CLANG_WARNING.
+ */
+#define ENABLE_CLANG_WARNING(warning) _ENABLE_COMPILER_WARNING(clang, warning)
+#else
+#define DISABLE_CLANG_WARNING(warning)
+#define ENABLE_CLANG_WARNING(warning)
+#endif
+
+#if defined(__GNUC__) && !defined(__clang__)
+/**
+ * Disable the specified compiler warning for gcc.
+ */
+#define DISABLE_GCC_WARNING(warning) _DISABLE_COMPILER_WARNING(GCC, warning)
+/**
+ * Re-enable the specified compiler warning for clang. Can only be used after
+ * a call to DISABLE_GCC_WARNING.
+ */
+#define ENABLE_GCC_WARNING(warning) _ENABLE_COMPILER_WARNING(GCC, warning)
+#else
+#define DISABLE_GCC_WARNING(warning)
+#define ENABLE_GCC_WARNING(warning)
+#endif
 
 #endif /* __CROS_EC_COMPILER_H */
diff --git a/include/config.h b/include/config.h
index 02709510ab..44cd80dd33 100644
--- a/include/config.h
+++ b/include/config.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,6 +18,15 @@
 #ifndef __CROS_EC_CONFIG_H
 #define __CROS_EC_CONFIG_H
 
+/*
+ * When building for Zephyr tests, a shimmed_tasks.h header is defined
+ * to create all the HAS_TASK_* definitions.  Since those are used in
+ * config.h, we need to include that header first.
+ */
+#ifdef CONFIG_ZEPHYR
+#include "shimmed_tasks.h"
+#endif /* CONFIG_ZEPHYR */
+
 #ifdef INCLUDE_ENV_CONFIG
 /*
  * When building for an EC target, pick up the .h file which allows to
@@ -70,8 +79,10 @@
 
 /* Specify type of accelerometers attached. */
 #undef CONFIG_ACCEL_BMA255
+#undef CONFIG_ACCEL_BMA4XX
 #undef CONFIG_ACCEL_KXCJ9
 #undef CONFIG_ACCEL_KX022
+
 /*
  * lis2dh/lis2de/lng2dm have the same register interface but different
  * supported resolution. In normal mode, lis2dh works in 10-bit resolution,
@@ -101,20 +112,33 @@
 #undef CONFIG_ACCEL_LIS2DWL
 #undef CONFIG_ACCEL_LIS2DW_COMMON
 
-/* lis2dw driver support fifo and interrupt, but letting lid accel sensor work
- * at polling mode is a common selection in current usage model. We need get a
- * option to be able to select interrupt or polling (foced mode).
- */
-#undef CONFIG_ACCEL_LIS2DW_AS_BASE
-
 #undef CONFIG_ACCELGYRO_BMI160
+#undef CONFIG_ACCELGYRO_BMI220
 #undef CONFIG_ACCELGYRO_BMI260
+#undef CONFIG_ACCELGYRO_BMI3XX
 #undef CONFIG_ACCELGYRO_ICM426XX
+#undef CONFIG_ACCELGYRO_ICM42607
 #undef CONFIG_ACCELGYRO_LSM6DS0
 /* Use CONFIG_ACCELGYRO_LSM6DSM for LSM6DSL, LSM6DSM, and/or LSM6DS3 */
 #undef CONFIG_ACCELGYRO_LSM6DSM
 #undef CONFIG_ACCELGYRO_LSM6DSO
 
+/* Select the communication mode for the accelgyro ICM. Only one of these should
+ * be set. To set the value manually, simply define one or the other. If neither
+ * is defined, but I2C_PORT_ACCEL is defined, then CONFIG_ACCELGYRO_ICM_I2C will
+ * automatically be set.
+ */
+#undef CONFIG_ACCELGYRO_ICM_COMM_SPI
+#undef CONFIG_ACCELGYRO_ICM_COMM_I2C
+
+/* Select the communication mode for the accelgyro BMI. Only one of these should
+ * be set. To set the value manually, simply define one or the other. If neither
+ * is defined, but I2C_PORT_ACCEL is defined, then CONFIG_ACCELGYRO_BMI_I2C will
+ * automatically be set.
+ */
+#undef CONFIG_ACCELGYRO_BMI_COMM_SPI
+#undef CONFIG_ACCELGYRO_BMI_COMM_I2C
+
 /*
  * Some chips have a portion of memory which will remain powered even
  * during a reset.  This is called Always-On, or AON memory, and
@@ -166,8 +190,8 @@
 #undef CONFIG_ACCELGYRO_SEC_ADDR_FLAGS
 
 /*
- * Define if either CONFIG_BMI_ORIENTATION_SUPPORT or
- * CONFIG_KX022_ORIENTATION_SUPPORT is set.
+ * Define if either CONFIG_BMI_ORIENTATION_SENSOR or
+ * CONFIG_KX022_ORIENTATION_SENSOR is set.
  */
 #undef CONFIG_ORIENTATION_SENSOR
 
@@ -180,9 +204,6 @@
 /* Which sensor body_detection use */
 #undef CONFIG_BODY_DETECTION_SENSOR
 
-/* Support custom setting of body_detection */
-#undef CONFIG_BODY_DETECTION_CUSTOM
-
 /* The max number of sampling data for 1 second */
 #undef CONFIG_BODY_DETECTION_MAX_WINDOW_SIZE
 
@@ -200,6 +221,15 @@
 /* The threshold duration to change to off_body */
 #undef CONFIG_BODY_DETECTION_STATIONARY_DURATION
 
+/* Send the SCI event to notify host when body status change */
+#undef CONFIG_BODY_DETECTION_NOTIFY_MODE_CHANGE
+
+/* Send the MKBP event to notify host when body status change */
+#undef CONFIG_BODY_DETECTION_NOTIFY_MKBP
+
+/* Always enable the body detection function in S0 */
+#undef CONFIG_BODY_DETECTION_ALWAYS_ENABLE_IN_S0
+
 /*
  * Use the old standard reference frame for accelerometers. The old
  * reference frame is:
@@ -266,11 +296,15 @@
  */
 #undef CONFIG_SYNC_INT_EVENT
 
+#ifndef CONFIG_ZEPHYR
 /* Compile chip support for digital-to-analog converter */
 #undef CONFIG_DAC
+#endif /* CONFIG_ZEPHYR */
 
-/* Compile chip support for analog-to-digital convertor */
-#undef CONFIG_ADC
+/*
+ * Allow runtime configuration of the adc_channels[] array
+ */
+#undef CONFIG_ADC_CHANNELS_RUNTIME_CONFIG
 
 /*
  * ADC sample time selection. The value is chip-dependent.
@@ -293,12 +327,6 @@
 #define CONFIG_ADC_PROFILE_SINGLE
 #undef CONFIG_ADC_PROFILE_FAST_CONTINUOUS
 
-/* Support AES symmetric-key algorithm */
-#undef CONFIG_AES
-
-/* Support AES-GCM */
-#undef CONFIG_AES_GCM
-
 /*
  * Some ALS modules may be connected to the EC. We need the command, and
  * specific drivers for each module.
@@ -317,6 +345,7 @@
 #undef CONFIG_ALS_BH1730_LUXTH_PARAMS
 #undef CONFIG_ALS_ISL29035
 #undef CONFIG_ALS_OPT3001
+#undef CONFIG_ALS_CM32183
 /* Define the exact model ID present on the board: SI1141 = 41, SI1142 = 42, */
 #undef CONFIG_ALS_SI114X
 /* Check if the device revision is supported */
@@ -325,22 +354,16 @@
 /* Define to include the clear channel driver for the tcs3400 light sensor */
 #undef CONFIG_ALS_TCS3400
 
-/*
- * Define to use atime tables in anti-saturation algos in the tcs3400 driver.
- * Defining this for a board makes the anti-saturation algorithm much more
- * efficient, but requires the board to have it's lens cover scale and k_channel
- * scales to be determined.  Define this for a board once it's added its
- * cover_scale and k_channel scale factors.
- */
-#undef CONFIG_TCS_USE_LUX_TABLE
-
 /*
  * Define the event to raise when a sensor interrupt triggers.
  * Must be within TASK_EVENT_MOTION_INTERRUPT_MASK.
  */
 #undef CONFIG_ACCELGYRO_BMI160_INT_EVENT
 #undef CONFIG_ACCELGYRO_BMI260_INT_EVENT
+#undef CONFIG_ACCELGYRO_BMI3XX_INT_EVENT
 #undef CONFIG_ACCELGYRO_ICM426XX_INT_EVENT
+#undef CONFIG_ACCELGYRO_ICM42607_INT_EVENT
+#undef CONFIG_ACCEL_BMA4XX_INT_EVENT
 #undef CONFIG_ACCEL_LSM6DSM_INT_EVENT
 #undef CONFIG_ACCEL_LSM6DSO_INT_EVENT
 #undef CONFIG_ACCEL_LIS2DS_INT_EVENT
@@ -389,8 +412,10 @@
  */
 #undef CONFIG_ASSEMBLY_MULA32
 
+#ifndef CONFIG_ZEPHYR
 /* Support audio codec. */
 #undef CONFIG_AUDIO_CODEC
+#endif /* CONFIG_ZEPHYR */
 /* Audio codec caps. */
 #undef CONFIG_AUDIO_CODEC_CAP_WOV_AUDIO_SHM
 #undef CONFIG_AUDIO_CODEC_CAP_WOV_LANG_SHM
@@ -445,6 +470,16 @@
  */
 #undef CONFIG_BATTERY
 
+/**
+ * Enable Battery-config-in-CBI. It makes a board read battery info from CBI.
+ */
+#undef CONFIG_BATTERY_CONFIG_IN_CBI
+
+/*
+ * Config to indicate the battery type that cannot be auto detected.
+ */
+#undef CONFIG_BATTERY_TYPE_NO_AUTO_DETECT
+
 /*
  * Compile battery-specific code.
  *
@@ -577,10 +612,25 @@
 #undef CONFIG_BATTERY_REVIVE_DISCONNECT
 
 /*
- * Specify the battery percentage at which the host is told it is full.
- * If this value is not specified the default is 97% set in battery.h.
+ * Low voltage protection for a battery (a.k.a. deep charge inspection):
+ * If battery voltage is lower than voltage_min, deep charge for more
+ * than precharge time The battery voltage is still lower than voltage_min,
+ * the system will stop charging
+ */
+#undef CONFIG_BATTERY_LOW_VOLTAGE_PROTECTION
+
+/*
+ * If battery voltage is lower than voltage_min, precharge voltage & current
+ * are supplied and charging will be disabled after
+ * CONFIG_BATTERY_LOW_VOLTAGE_TIMEOUT seconds.
+ */
+#define CONFIG_BATTERY_LOW_VOLTAGE_TIMEOUT (30 * 60 * SECOND)
+
+/*
+ * Use memory mapped region to store battery information. It supports only
+ * single battery systems. V2 should be used unless there is a reason not to.
  */
-#undef CONFIG_BATTERY_LEVEL_NEAR_FULL
+#undef CONFIG_BATTERY_V1
 
 /*
  * Use an alternative method to store battery information: Instead of writing
@@ -589,18 +639,10 @@
  * using host commands, or via EC_ACPI_MEM_BATTERY_INDEX command, which tells
  * the EC to update the shared memory.
  *
- * This is required on dual-battery systems, and on on hostless bases with a
- * battery.
+ * This is required on dual-battery systems and hostless bases with a battery.
  */
 #undef CONFIG_BATTERY_V2
 
-/*
- * Some fuel gauges in battery take some time to return valid battery params
- * when wake form dead battery.
- * It need to do precharge to take valid battery params.
- */
-#undef CONFIG_BATTERY_DEAD_UNTIL_VALUE
-
 /*
  * Number of batteries, only matters when CONFIG_BATTERY_V2 is used.
  */
@@ -613,26 +655,56 @@
 #undef CONFIG_BATTERY_MEASURE_IMBALANCE
 
 /*
- * If remaining capacity is x% of full capacity, remaining capacity is set
- * equal to full capacity.
- *
+ * Some boards needs to lower input voltage when battery is full and chipset
+ * is in S5/G3. This should be defined to integer value in mV.
+ */
+#undef CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV
+
+/*
+ * Check the specific battery status to judge whether the battery is
+ * initialized and stable when the battery wakes up from ship mode.
+ */
+#undef CONFIG_BATTERY_STBL_STAT
+
+/*
  * Some batteries don't update full capacity timely or don't update it at all.
  * On such systems, compensation is required to guarantee remaining_capacity
  * will be equal to full_capacity eventually. This used to be done in ACPI.
+ *
+ * Powerd uses CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE as the threshold for low
+ * battery shutdown.
+ *
+ * We want to show the low battery alert whenever we can. Thus, we make EC not
+ * inhibit power-on even if it knows the host would immediately shut down. To
+ * get that behavior, we need:
+ *
+ *   MIN_BAT_PCT_FOR_POWER_ON < HOST_SHUTDOWN_PER = BATTERY_LEVEL_SHUTDOWN
+ *
+ * Thus, we set them as follows by default:
+ *
+ *   CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON = 2 (don't boot if soc < 2%)
+ *   CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE = 4    (shutdown if soc <= 4%)
+ *   BATTERY_LEVEL_SHUTDOWN = 3                  (shutdown if soc < 3%)
+ *
+ * This produces the following behavior:
+ *
+ * - If soc = 1%, system doesn't boot. User wouldn't know why.
+ * - If soc = 2~4%, system boots. Alert is shown. System immediately shuts down.
+ * - If battery discharges to 4% while the system is running, system shuts down.
+ *   If that happens while a user is away, they can press the power button to
+ *   learn what happened.
+ * - If system fails to shutdown for some reason and battery further discharges
+ *   to 2%, EC will trigger shutdown.
  */
-#define CONFIG_BATT_FULL_FACTOR			98
-#define CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE	4
+#define CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE 4 /* shutdown if soc <= 4% */
 
 /*
  * Powerd's full_factor. The value comes from:
  *   src/platform2/power_manager/default_prefs/power_supply_full_factor
+ *
+ * This value is used by the host to calculate the ETA for full charge.
  */
-#define CONFIG_BATT_HOST_FULL_FACTOR		97
-
-/*
- * Smart battery pass-through host commands.
- */
-#undef CONFIG_SB_PASSTHROUGH
+#define CONFIG_BATT_HOST_FULL_FACTOR 97
 
 /*
  * Expose some data when it is needed.
@@ -687,24 +759,16 @@
  */
 #undef CONFIG_BOARD_PRE_INIT
 
-/*
- * EC has the notion of board version either through resistors or EEPROM.
- * The common CONFIG_BOARD_VERSION is defined automatically when one of the
- * specific options is used.
- */
-#undef CONFIG_BOARD_VERSION
 /* The board version comes from Cros Board Info within EEPROM. */
 #undef CONFIG_BOARD_VERSION_CBI
-/* The board version function is defined in board code. */
-#undef CONFIG_BOARD_VERSION_CUSTOM
 /*
  * The board version is encoded with 3 GPIO signals where GPIO_BOARD_VERSION1
  * is the LSB.
  */
 #undef CONFIG_BOARD_VERSION_GPIO
 
-/* EC responses to a board defined I2C slave address */
-#undef CONFIG_BOARD_I2C_SLAVE_ADDR_FLAGS
+/* EC responses to a board defined I2C address */
+#undef CONFIG_BOARD_I2C_ADDR_FLAGS
 
 /*
  * The board is unable to distinguish EC reset from power-on so it should treat
@@ -720,7 +784,7 @@
  * On the second reset, the saved flag is used to detect the previous
  * power-on, and treat the second reset as a power-on instead of a reset.
  *
- * NOTE: Implemented only for npcx
+ * NOTE: Implemented only for npcx and ite
  */
 #undef CONFIG_BOARD_RESET_AFTER_POWER_ON
 
@@ -764,6 +828,24 @@
 #undef CONFIG_DEDICATED_RECOVERY_BUTTON
 #undef CONFIG_DEDICATED_RECOVERY_BUTTON_2
 
+/* Configure recovery button. e.g. BUTTON_FLAG_ACTIVE_HIGH */
+#undef CONFIG_DEDICATED_RECOVERY_BUTTON_FLAGS
+#undef CONFIG_DEDICATED_RECOVERY_BUTTON_2_FLAGS
+
+/*
+ * RISC-V core specific panic data is bigger than Cortex-M core specific panic
+ * data. Including this into union in panic_data structure causes whole
+ * to grow by 28 bytes. In many boards EC RO is still obtaining pointer to
+ * beginning of panic data by subtracting its panic data structure size from
+ * the end of RAM. When EC RW saves panic data it will be corrupted by EC RO.
+ * Moreover, during next boot EC RW won't be able to find jump data (see
+ * b/165773837 for more details).
+ *
+ * This config allows boards to not include RV32I panic data if their EC RO
+ * doesn't include it to keep panic data structure in sync.
+ */
+#undef CONFIG_DO_NOT_INCLUDE_RV32I_PANIC_DATA
+
 /*
  * The board has volume up and volume down buttons.  Note, these are *buttons*
  * and not keys in the keyboard matrix.
@@ -789,6 +871,9 @@
  */
 #undef CONFIG_SIMULATED_BUTTON
 
+/* Set the default button debounce time in us */
+#define CONFIG_BUTTON_DEBOUNCE (30 * MSEC)
+
 /*
  * Capsense chip has buttons, too.
  */
@@ -797,6 +882,10 @@
 /*****************************************************************************/
 /* Support CEC */
 #undef CONFIG_CEC
+#undef CONFIG_CEC_DEBUG
+
+/* CEC drivers */
+#undef CONFIG_CEC_BITBANG
 
 /*****************************************************************************/
 
@@ -831,6 +920,11 @@
 /* Compile input current ramping support using software control */
 #undef CONFIG_CHARGE_RAMP_SW
 
+/* Enable EC support for charging splashscreen */
+#undef CONFIG_CHARGESPLASH
+#undef CONFIG_CHARGESPLASH_PERIOD
+#undef CONFIG_CHARGESPLASH_MAX_REQUESTS_PER_PERIOD
+
 /*****************************************************************************/
 /* Charger config */
 
@@ -843,21 +937,26 @@
 #undef CONFIG_CHARGER_BQ24770
 #undef CONFIG_CHARGER_BQ24773
 #undef CONFIG_CHARGER_BQ25710
+#undef CONFIG_CHARGER_BQ25720
 #undef CONFIG_CHARGER_ISL9237
 #undef CONFIG_CHARGER_ISL9238 /* For ISL9238 A/B */
 #undef CONFIG_CHARGER_ISL9238C
 #undef CONFIG_CHARGER_ISL9241
 #undef CONFIG_CHARGER_MT6370
 #undef CONFIG_CHARGER_RAA489000
+#undef CONFIG_CHARGER_RAA489110
 #undef CONFIG_CHARGER_RT9466
 #undef CONFIG_CHARGER_RT9467
+#undef CONFIG_CHARGER_RT9490
 #undef CONFIG_CHARGER_SM5803
 #undef CONFIG_CHARGER_SY21612
 
-
 /* Allow run-time completion of the charger driver structure */
 #undef CONFIG_CHARGER_RUNTIME_CONFIG
 
+/* Allow the customized initial configuration */
+#undef CONFIG_CHARGER_INIT_CUSTOM
+
 /*
  * Board has only one charger chip (default, undef when board contains multiple
  * charger chips
@@ -943,7 +1042,48 @@
  * this should be set to 512 mA in order to not brown-out low-current USB
  * charge ports in accordance with USB-PD r3.0 Sec. 7.3
  */
-#undef CONFIG_CHARGER_INPUT_CURRENT
+#undef CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT
+
+/*
+ * Minimum current limit that will ever be set for chargers, even if a lower
+ * limit is requested. This will allow the charger to draw more power than
+ * the requested limit.
+ *
+ * If set, this should usually be set to no more than 2.5W divided by the
+ * maximum supported input voltage in order to satisfy USB-PD pSnkStdby
+ * requirements. Higher values may help devices stay alive under low-battery
+ * conditions at the cost of violating standby power limits.
+ *
+ * Many boards set this to large values, since historically this number was
+ * usually equal to CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT. New boards should
+ * avoid doing so if possible.
+ */
+#undef CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT
+
+/*
+ * Percentage derating factor applied to charger input current limits.
+ *
+ * Desired charger current is reduced by this many percent when programming
+ * chargers via the charge manager, which is usually used to account for
+ * chargers that draw slightly more current than the programmed limit or to
+ * provide some margin for accuracy. For example, if this value is set to 4
+ * and input current is limited to 1000 mA, the charger will be given a limit
+ * of 960 mA.
+ *
+ * The default value is set to prevent most overcurrent conditions during load
+ * transients, because power supplies vary in their tolerance to such
+ * short-lived overcurrent conditions and many chargers respond slowly to those
+ * transients.
+ *
+ * Projects SHOULD characterize system behavior to tune for system
+ * behavior and charger response in order to optimize this (allowing the
+ * derating to be reduced) and ensure transients do not exceed the range of
+ * acceptable current (which might require greater derating).
+ *
+ * Boards requiring more complex control over input current should leave this
+ * undefined and override board_set_charge_limit instead.
+ */
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT 5
 
 /*
  * This config option is used to enable IDCHG trigger for prochot. This macro
@@ -955,6 +1095,164 @@
  */
 #undef CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA
 
+/* Enable if CONFIG_CHARGER_BQ25720_VSYS_TH2_DV should be applied */
+#undef CONFIG_CHARGER_BQ25720_VSYS_TH2_CUSTOM
+
+/*
+ * This config option is used to set the charger's VSYS voltage
+ * threshold. When the voltage drops to this level, PROCHOT is asserted
+ * by the charger to request reduced system power demand and hopefully
+ * avoid a voltage droop leading to system instability. The voltage is
+ * specified in deci-volts, so a value of 80 would set the threshold to
+ * 8.0v.
+ */
+#undef CONFIG_CHARGER_BQ25720_VSYS_TH2_DV
+
+/* Enable if CONFIG_CHARGER_BQ25720_VSYS_UVP should be applied */
+#undef CONFIG_CHARGER_BQ25720_VSYS_UVP_CUSTOM
+
+/*
+ * This config option is used to set the VSYS under voltage (VSYS_UVP)
+ * lockout threshold. This is a 3 bit field with default value 0. The
+ * actual voltage encoded is (0.8 * <value> + 2.4), allowing a threshold
+ * in the range of 2.4 V to 8.0 V to be specified.
+ */
+#undef CONFIG_CHARGER_BQ25720_VSYS_UVP
+
+/* Enable if CONFIG_CHARGER_BQ25720_IDCHG_DEG2 should be applied */
+#undef CONFIG_CHARGER_BQ25720_IDCHG_DEG2_CUSTOM
+
+/*
+ * This config option is used to set the 2nd battery discharge current
+ * limit (IDCHG_TH2) deglitch time (IDCHG_DEG2). This is a 2 bit field
+ * with default value 1 (1.6 ms). The encoded value ranges from 100 us
+ * to 12 ms.
+ */
+#undef CONFIG_CHARGER_BQ25720_IDCHG_DEG2
+
+/* Enable if CONFIG_CHARGER_BQ25720_IDCHG_TH2 should be applied */
+#undef CONFIG_CHARGER_BQ25720_IDCHG_TH2_CUSTOM
+
+/*
+ * This config option is used to set the charger's 2nd battery discharge
+ * current limit (IDCHG_TH2) as a percentage of IDCHG_TH1. This is a 3
+ * bit field with default value 1 (150%). The encoded value ranges from
+ * 125% to 400%.
+ */
+#undef CONFIG_CHARGER_BQ25720_IDCHG_TH2
+
+/* Value of the bq25710 charge sense resistor, in mOhms */
+#undef CONFIG_CHARGER_BQ25710_SENSE_RESISTOR
+
+/* Value of the bq25710 input current sense resistor, in mOhms */
+#undef CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC
+
+/*
+ * This config option is used to enable the PSYS sensing circuit on the
+ * BQ25710 and BQ25720 chargers. This is used for system power
+ * monitoring on board designs that support this capability. This
+ * circuit is disabled by default (reset) and needs to be explicitly
+ * enabled for meaningful results.
+ */
+#undef CONFIG_CHARGER_BQ25710_PSYS_SENSING
+
+/*
+ * This config option is used to change the charger's internal
+ * comparator reference voltage to 1.2 V. The power-on default is 2.3
+ * V. This must be enabled if the board was designed for 1.2 V instead
+ * of 2.3 V.
+ */
+#undef CONFIG_CHARGER_BQ25710_CMP_REF_1P2
+
+/*
+ * This config option is used to change the charger's independent comparator
+ * output polarity. The default setting is CMPIN is above internal threshold,
+ * CMPOUT is LOW (internal hysteresis).
+ */
+#undef CONFIG_CHARGER_BQ25710_CMP_POL_EXTERNAL
+
+/* Enable if CONFIG_CHARGER_BQ25710_PKPWR_TOVLD_DEG should be applied */
+#undef CONFIG_CHARGER_BQ25710_PKPWR_TOVLD_DEG_CUSTOM
+
+/*
+ * Input overload time when in peak power mode (PKPWR_TOVLD_DEG). This
+ * limits how long the charger can draw ILIM2 from the adapter. This is
+ * a 2 bit field. On the bq25710 1 ms to 20 ms can be encoded. On the
+ * bq25720 1 ms to 10 ms can be encoded.
+ */
+#undef CONFIG_CHARGER_BQ25710_PKPWR_TOVLD_DEG
+
+/*
+ * This config option is used to enable the charger's AC over-current
+ * protection. The converter turns off when the OC threshold is
+ * reached. The threshold is selected using the ACOC_VTH bit.
+ */
+#undef CONFIG_CHARGER_BQ25710_EN_ACOC
+
+/*
+ * This config option selects which ACOC protection threshold is used
+ * with EN_ACOC. Enabling this option selects 133% of ILIM2. Otherwise,
+ * the default is 200% of ILIM2.
+ */
+#undef CONFIG_CHARGER_BQ25710_ACOC_VTH_1P33
+
+/*
+ * This config option selects the minimum BATOC protection threshold to
+ * be used with EN_BATOC. The minimum threshold is 150% of PROCHOT IDCHG
+ * on the bq25710 and 133% of PROCHOT IDCHG_TH2 on the bq25720. The
+ * default threshold is 200% on both chips.
+ */
+#undef CONFIG_CHARGER_BQ25710_BATOC_VTH_MINIMUM
+
+/*
+ * This config option sets the PP_INOM bit in Prochot Option 1
+ * register. This causes PROCHOT to be pulsed when the nominal adapter
+ * current threshold is reached. INOM is 110% of IDPM/IIN_DPM (input
+ * current setting).
+ */
+#undef CONFIG_CHARGER_BQ25710_PP_INOM
+
+/*
+ * This config option sets the PP_BATPRES bit in Prochot Option 1
+ * register. This causes PROCHOT to be pulsed when the battery is
+ * removed.
+ */
+#undef CONFIG_CHARGER_BQ25710_PP_BATPRES
+
+/*
+ * This config option sets the PP_ACOK in Prochot Option 1
+ * register. This causes PROCHOT to be pulsed when the AC adapter is
+ * removed.
+ */
+#undef CONFIG_CHARGER_BQ25710_PP_ACOK
+
+/*
+ * This config option sets the PP_COMP in Prochot Option 1
+ * register. Need to use EN_PROCHOT_LPWR to enable independent comparator
+ * and its PROCHOT profile.
+ */
+#undef CONFIG_CHARGER_BQ25710_PP_COMP
+
+/*
+ * This config option sets the PP_IDCHG2 bit in the Charge Option 4
+ * register. This causes PROCHOT to be pulsed when IDCHG_TH2 is reached.
+ */
+
+#undef CONFIG_CHARGER_BQ25720_PP_IDCHG2
+
+/* Enable if CONFIG_CHARGER_BQ25710_VSYS_MIN_VOLTAGE_MV should be applied */
+#undef CONFIG_CHARGER_BQ25710_VSYS_MIN_VOLTAGE_CUSTOM
+
+/*
+ * This config option sets the minimum system voltage in
+ * milli-volts. The bq25710 uses 6 bits of resolution and can be
+ * configured from 1.024 V to 16.128 V in 256 mV increments. The bq25720
+ * uses 8 bits of resolution and can be set from 1.0 V to 19.2 V in 100
+ * mV increments. The default value depends on configured number of
+ * battery cells connected in series using the CELL_BATPRESZ strap.
+ */
+#undef CONFIG_CHARGER_BQ25710_VSYS_MIN_VOLTAGE_MV
+
 /*
  * Board specific maximum input current limit, in mA.
  */
@@ -986,8 +1284,8 @@
  * analog signaling.  If the AP requires greater than 15W to boot, then see
  * CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW.
  */
-#undef CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON
-#undef CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC
+#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 2 /* Don't boot if soc < 2% */
+#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC 1
 /* Default: 15000 */
 #undef CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
 /* Default: Disabled */
@@ -1002,6 +1300,13 @@
  */
 #undef CONFIG_BATTERY_MAX_IMBALANCE_MV
 
+/*
+ * Select this option if the charger will be used in a bypass mode in
+ * order to pass the input current from AC directly to the system
+ * power rail for efficiency.
+ */
+#undef CONFIG_CHARGER_BYPASS_MODE
+
 /* Set this option when using a Narrow VDC (NVDC) charger, such as ISL9237/8. */
 #undef CONFIG_CHARGER_NARROW_VDC
 
@@ -1065,6 +1370,13 @@
 /* Charger enable GPIO is active low */
 #undef CONFIG_CHARGER_EN_ACTIVE_LOW
 
+/*
+ * Enable reverse turbo boost to allow battery to suppliment
+ * the AC adapter power when an adapter is connected and
+ * the charger is running in bypass mode
+ */
+#undef CONFIG_CHARGER_BYPASS_REVERSE_TURBO
+
 /*
  * OCPC - One Charger IC Per Type-C
  *
@@ -1083,17 +1395,23 @@
  */
 #undef CONFIG_OCPC_DEF_RBATT_MOHMS
 
+/* Set a default OCPC drive limit for legacy boards */
+#define CONFIG_OCPC_DEF_DRIVELIMIT_MILLIVOLTS 10
+
 /* Enable trickle charging */
 #undef CONFIG_TRICKLE_CHARGING
 
+/* Set trickle charge current by taking integer value */
+#define CONFIG_RAA489000_TRICKLE_CHARGE_CURRENT 128
+
 /* Wireless chargers */
-#undef CONFIG_WIRELESS_CHARGER_P9221_R7
+#undef CONFIG_CPS8100
 
-/*
- * Workaround npcx9 A1 chip's bug for download_from_flash API in th booter.
- * This can be removed when A2 chip is available.
- */
-#undef CONFIG_WORKAROUND_FLASH_DOWNLOAD_API
+/* Enable customized design */
+#undef CONFIG_CUSTOMIZED_DESIGN
+
+/* Enable the GPU feature */
+#undef CONFIG_GPU
 
 /*****************************************************************************/
 
@@ -1152,30 +1470,40 @@
 /* Chipset config */
 
 /* AP chipset support; pick at most one */
-#undef CONFIG_CHIPSET_APOLLOLAKE	/* Intel Apollolake (x86) */
-#undef CONFIG_CHIPSET_BRASWELL		/* Intel Braswell (x86) */
-#undef CONFIG_CHIPSET_CANNONLAKE	/* Intel Cannonlake (x86) */
-#undef CONFIG_CHIPSET_COMETLAKE		/* Intel Cometlake (x86) */
-#undef CONFIG_CHIPSET_COMETLAKE_DISCRETE	/* Intel Cometlake (x86),
-						 * discrete EC control
-						 */
-#undef CONFIG_CHIPSET_ECDRIVEN		/* Mock power module */
-#undef CONFIG_CHIPSET_GEMINILAKE	/* Intel Geminilake (x86) */
-#undef CONFIG_CHIPSET_ICELAKE		/* Intel Icelake (x86) */
-#undef CONFIG_CHIPSET_JASPERLAKE	/* Intel Jasperlake (x86) */
-#undef CONFIG_CHIPSET_MT817X		/* MediaTek MT817x */
-#undef CONFIG_CHIPSET_MT8183		/* MediaTek MT8183 */
-#undef CONFIG_CHIPSET_MT8192		/* MediaTek MT8192 */
-#undef CONFIG_CHIPSET_RK3288		/* Rockchip rk3288 */
-#undef CONFIG_CHIPSET_RK3399		/* Rockchip rk3399 */
-#undef CONFIG_CHIPSET_SKYLAKE		/* Intel Skylake (x86) */
-#undef CONFIG_CHIPSET_SC7180            /* Qualcomm SC7180 */
-#undef CONFIG_CHIPSET_SDM845            /* Qualcomm SDM845 */
-#undef CONFIG_CHIPSET_STONEY		/* AMD Stoney (x86)*/
-#undef CONFIG_CHIPSET_TIGERLAKE		/* Intel Tigerlake (x86) */
+#undef CONFIG_CHIPSET_ALDERLAKE /* Intel Alderlake (x86) */
+#ifndef CONFIG_ZEPHYR
+#undef CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540 /* Intel Alderlake (x86) \
+					     * with power sequencer  \
+					     * chip                  \
+					     */
+#endif /* CONFIG_ZEPHYR */
+#undef CONFIG_CHIPSET_APOLLOLAKE /* Intel Apollolake (x86) */
+#undef CONFIG_CHIPSET_CANNONLAKE /* Intel Cannonlake (x86) */
+#undef CONFIG_CHIPSET_COMETLAKE /* Intel Cometlake (x86) */
+#undef CONFIG_CHIPSET_COMETLAKE_DISCRETE /* Intel Cometlake (x86), \
+					  * discrete EC control    \
+					  */
+#undef CONFIG_CHIPSET_ECDRIVEN /* Mock power module */
+#undef CONFIG_CHIPSET_FALCONLITE /* Falcon-lite*/
+#undef CONFIG_CHIPSET_GEMINILAKE /* Intel Geminilake (x86) */
+#undef CONFIG_CHIPSET_ICELAKE /* Intel Icelake (x86) */
+#undef CONFIG_CHIPSET_JASPERLAKE /* Intel Jasperlake (x86) */
+#undef CONFIG_CHIPSET_METEORLAKE /* Intel Meteorlake (x86) */
+#undef CONFIG_CHIPSET_MT817X /* MediaTek MT817x */
+#undef CONFIG_CHIPSET_MT8183 /* MediaTek MT8183 */
+#undef CONFIG_CHIPSET_MT8192 /* MediaTek MT8192 */
+#undef CONFIG_CHIPSET_CEZANNE /* AMD Cezanne (x86) */
+#undef CONFIG_CHIPSET_RK3288 /* Rockchip rk3288 */
+#undef CONFIG_CHIPSET_RK3399 /* Rockchip rk3399 */
+#undef CONFIG_CHIPSET_SKYLAKE /* Intel Skylake (x86) */
+#undef CONFIG_CHIPSET_SC7180 /* Qualcomm SC7180 */
+#undef CONFIG_CHIPSET_SC7280 /* Qualcomm SC7280 */
+#undef CONFIG_CHIPSET_SDM845 /* Qualcomm SDM845 */
+#undef CONFIG_CHIPSET_STONEY /* AMD Stoney (x86)*/
+#undef CONFIG_CHIPSET_TIGERLAKE /* Intel Tigerlake (x86) */
 
 /* Shared chipset support; automatically gets defined below. */
-#undef CONFIG_CHIPSET_APL_GLK		/* Apollolake & Geminilake */
+#undef CONFIG_CHIPSET_APL_GLK /* Apollolake & Geminilake */
 
 /* Support chipset throttling */
 #undef CONFIG_CHIPSET_CAN_THROTTLE
@@ -1214,6 +1542,9 @@
  */
 #undef CONFIG_CHIPSET_X86_RSMRST_DELAY
 
+/* Passthrough RSMRST_L de-assertion after S5 */
+#undef CONFIG_CHIPSET_X86_RSMRST_AFTER_S5
+
 /* Support PMIC reset(using LDO_EN) in chipset */
 #undef CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET
 
@@ -1223,6 +1554,16 @@
 /* Redefine when we need a different power-on sequence on the same chipset. */
 #define CONFIG_CHIPSET_POWER_SEQ_VERSION 0
 
+/*
+ * Allow fake control of the power states.
+ *
+ * Note: This should NOT be used on platforms which have an SoC present.
+ */
+#undef CONFIG_POWERSEQ_FAKE_CONTROL
+
+/* AMD Side-Band Remote Management Interface (SB-RMI) support */
+#undef CONFIG_AMD_SB_RMI
+
 /*****************************************************************************/
 /*
  * Chip config for clock circuitry
@@ -1274,8 +1615,8 @@
  * Required Configuration:
  * - CONFIG_BLINK_LEDS        --> List of LEDs (gpio enum names) to use as bits
  */
-#undef  CONFIG_BLINK
-#undef  CONFIG_BLINK_LEDS                     /* Ex: GPIO_LED1, GPIO_LED2 */
+#undef CONFIG_BLINK
+#undef CONFIG_BLINK_LEDS /* Ex: GPIO_LED1, GPIO_LED2 */
 
 /*****************************************************************************/
 /*
@@ -1285,123 +1626,133 @@
  * console.
  */
 
-#undef  CONFIG_CMD_ACCELS
-#undef  CONFIG_CMD_ACCEL_FIFO
-#undef  CONFIG_CMD_ACCEL_INFO
+#undef CONFIG_CMD_ACCELS
+#undef CONFIG_CMD_ACCEL_FIFO
+#undef CONFIG_CMD_ACCEL_INFO
 #define CONFIG_CMD_ACCELSPOOF
 #define CONFIG_CMD_ADC
-#undef  CONFIG_CMD_ALS
+#undef CONFIG_CMD_ALS
 #define CONFIG_CMD_APTHROTTLE
-#undef  CONFIG_CMD_BATDEBUG
+#undef CONFIG_CMD_BATDEBUG
 #define CONFIG_CMD_BATTFAKE
-#undef  CONFIG_CMD_BATT_MFG_ACCESS
-#define CONFIG_CMD_RETIMER
-#undef  CONFIG_CMD_BUTTON
+#undef CONFIG_CMD_BATT_MFG_ACCESS
+#undef CONFIG_CMD_BATTERY_CONFIG
+#undef CONFIG_CMD_BUTTON
 #define CONFIG_CMD_CBI
-#undef  CONFIG_CMD_CHARGEN
+#undef CONFIG_CMD_PD_SRCCAPS_REDUCED_SIZE
+#undef CONFIG_CMD_VBUS
+
+/*
+ * HAS_TASK_CHIPSET implies the GSC presence.
+ * HAS_TASK_CONSOLE means UART console enabled.
+ * chargen command is needed for UART stress test.
+ */
+#if defined(HAS_TASK_CHIPSET) && defined(HAS_TASK_CONSOLE)
+#define CONFIG_CMD_CHARGEN
+#else
+#undef CONFIG_CMD_CHARGEN
+#endif
 #define CONFIG_CMD_CHARGER
-#undef  CONFIG_CMD_CHARGER_ADC_AMON_BMON
-#undef  CONFIG_CMD_CHARGER_DUMP
-#undef  CONFIG_CMD_CHARGER_PROFILE_OVERRIDE
-#undef  CONFIG_CMD_CHARGER_PROFILE_OVERRIDE_TEST
+
+/* Extra debugging info for the charger */
+#define CONFIG_CHARGE_DEBUG
+
+#undef CONFIG_CMD_CHARGER_ADC_AMON_BMON
+#undef CONFIG_CMD_CHARGER_DUMP
+#undef CONFIG_CMD_CHARGER_PROFILE_OVERRIDE
+#undef CONFIG_CMD_CHARGER_PROFILE_OVERRIDE_TEST
 #define CONFIG_CMD_CHARGE_SUPPLIER_INFO
-#undef  CONFIG_CMD_CHGRAMP
-#undef  CONFIG_CMD_CLOCKGATES
-#undef  CONFIG_CMD_COMXTEST
+#undef CONFIG_CMD_CHGRAMP
+#undef CONFIG_CMD_CLOCKGATES
+#undef CONFIG_CMD_COMXTEST
 #define CONFIG_CMD_CRASH
 #define CONFIG_CMD_DEVICE_EVENT
-#undef  CONFIG_CMD_DLOG
-#undef  CONFIG_CMD_ECTEMP
+#undef CONFIG_CMD_DLOG
+#undef CONFIG_CMD_ECTEMP
 #define CONFIG_CMD_FASTCHARGE
-#undef  CONFIG_CMD_FLASH
+#undef CONFIG_CMD_FLASH
 #define CONFIG_CMD_FLASHINFO
-#undef  CONFIG_CMD_FLASH_LOG
-#undef  CONFIG_CMD_FLASH_TRISTATE
-#undef  CONFIG_CMD_FORCETIME
-#undef  CONFIG_CMD_FPSENSOR_DEBUG
+#undef CONFIG_CMD_FLASH_TRISTATE
+#undef CONFIG_CMD_FORCETIME
+#undef CONFIG_CMD_FPSENSOR_DEBUG
 #define CONFIG_CMD_GETTIME
-#undef  CONFIG_CMD_GPIO_EXTENDED
-#undef  CONFIG_CMD_GSV
-#undef  CONFIG_CMD_GT7288
+#undef CONFIG_CMD_GL3590
+#undef CONFIG_CMD_GPIO_EXTENDED
+#undef CONFIG_CMD_GT7288
 #define CONFIG_CMD_HASH
 #define CONFIG_CMD_HCDEBUG
-#undef  CONFIG_CMD_HOSTCMD
-#undef  CONFIG_CMD_I2CWEDGE
-#undef  CONFIG_CMD_I2C_PROTECT
+#undef CONFIG_CMD_HOSTCMD
+#undef CONFIG_CMD_I2CWEDGE
+#undef CONFIG_CMD_I2C_PROTECT
 #define CONFIG_CMD_I2C_SCAN
-#undef  CONFIG_CMD_I2C_STRESS_TEST
-#undef  CONFIG_CMD_I2C_STRESS_TEST_ACCEL
-#undef  CONFIG_CMD_I2C_STRESS_TEST_ALS
-#undef  CONFIG_CMD_I2C_STRESS_TEST_BATTERY
-#undef  CONFIG_CMD_I2C_STRESS_TEST_CHARGER
-#undef  CONFIG_CMD_I2C_STRESS_TEST_TCPC
+#undef CONFIG_CMD_I2C_SPEED
+#undef CONFIG_CMD_I2C_STRESS_TEST
+#undef CONFIG_CMD_I2C_STRESS_TEST_ACCEL
+#undef CONFIG_CMD_I2C_STRESS_TEST_ALS
+#undef CONFIG_CMD_I2C_STRESS_TEST_BATTERY
+#undef CONFIG_CMD_I2C_STRESS_TEST_CHARGER
+#undef CONFIG_CMD_I2C_STRESS_TEST_TCPC
 #define CONFIG_CMD_I2C_XFER
+#undef CONFIG_CMD_I2C_XFER_RAW
 #define CONFIG_CMD_IDLE_STATS
-#undef  CONFIG_CMD_ILIM
 #define CONFIG_CMD_INA
-#undef  CONFIG_CMD_JUMPTAGS
+#undef CONFIG_CMD_JUMPTAGS
 #define CONFIG_CMD_KEYBOARD
-#undef  CONFIG_CMD_LEDTEST
-#undef  CONFIG_CMD_LID_ANGLE
-#undef  CONFIG_CMD_MCDP
+#undef CONFIG_CMD_LEDTEST
+#undef CONFIG_CMD_MCDP
 #define CONFIG_CMD_MD
 #define CONFIG_CMD_MEM
+#define CONFIG_CMD_MFALLOW
 #define CONFIG_CMD_MMAPINFO
 #define CONFIG_CMD_PD
-#undef  CONFIG_CMD_PD_DEV_DUMP_INFO
-#undef  CONFIG_CMD_PD_FLASH
+#undef CONFIG_CMD_PD_DEV_DUMP_INFO
+#undef CONFIG_CMD_PD_FLASH
+#undef CONFIG_CMD_PD_TIMER
 #define CONFIG_CMD_PECI
-#undef  CONFIG_CMD_PLL
-#undef  CONFIG_CMD_PMU
+#undef CONFIG_CMD_PLL
 #define CONFIG_CMD_POWERINDEBUG
-#undef  CONFIG_CMD_POWERLED
+#undef CONFIG_CMD_POWERLED
 #define CONFIG_CMD_PWR_AVG
 #define CONFIG_CMD_POWER_AP
-#undef  CONFIG_CMD_PPC_DUMP
-#undef  CONFIG_CMD_PS2
-#undef  CONFIG_CMD_RAND
+#undef CONFIG_CMD_PPC_DUMP
+#undef CONFIG_CMD_PS2
+#undef CONFIG_CMD_RAND
 #define CONFIG_CMD_REGULATOR
-#undef  CONFIG_CMD_RESET_FLAGS
-#undef  CONFIG_CMD_RTC
-#undef  CONFIG_CMD_RTC_ALARM
+#undef CONFIG_CMD_RESET_FLAGS
+#undef CONFIG_CMD_RETIMER
+#undef CONFIG_CMD_RTC
+#undef CONFIG_CMD_RTC_ALARM
 #define CONFIG_CMD_RW
-#undef  CONFIG_CMD_SCRATCHPAD
-#undef	CONFIG_CMD_SEVEN_SEG_DISPLAY
+#undef CONFIG_CMD_S5_TIMEOUT
+#undef CONFIG_CMD_SCRATCHPAD
+#undef CONFIG_CMD_SEVEN_SEG_DISPLAY
 #define CONFIG_CMD_SHMEM
-#undef  CONFIG_CMD_SLEEP
+#undef CONFIG_CMD_SLEEP
 #define CONFIG_CMD_SLEEPMASK
 #define CONFIG_CMD_SLEEPMASK_SET
-#undef  CONFIG_CMD_SPI_FLASH
-#undef  CONFIG_CMD_SPI_NOR
-#undef  CONFIG_CMD_SPI_XFER
-#undef  CONFIG_CMD_STACKOVERFLOW
+#undef CONFIG_CMD_SPI_FLASH
+#undef CONFIG_CMD_SPI_NOR
+#undef CONFIG_CMD_SPI_XFER
 #define CONFIG_CMD_SYSINFO
 #define CONFIG_CMD_SYSJUMP
 #define CONFIG_CMD_SYSLOCK
-#undef  CONFIG_CMD_TASK_RESET
-#undef  CONFIG_CMD_TASKREADY
-#undef  CONFIG_CMD_TCPC_DUMP
+#undef CONFIG_CMD_TASK_RESET
+#undef CONFIG_CMD_TASKREADY
+#undef CONFIG_CMD_TCPC_DUMP
 #define CONFIG_CMD_TEMP_SENSOR
 #define CONFIG_CMD_TIMERINFO
 #define CONFIG_CMD_TYPEC
-#undef  CONFIG_CMD_USART_INFO
-#define CONFIG_CMD_USBMUX
-#undef  CONFIG_CMD_USB_PD_CABLE
-#undef  CONFIG_CMD_USB_PD_PE
+#undef CONFIG_CMD_USART_INFO
+#undef CONFIG_CMD_USB_PD_CABLE
+#undef CONFIG_CMD_USB_PD_PE
 #define CONFIG_CMD_WAITMS
-#undef  CONFIG_CMD_AP_RESET_LOG
+#undef CONFIG_CMD_AP_RESET_LOG
 
 /*****************************************************************************/
 
 /* Provide common core code to output panic information without interrupts. */
 #define CONFIG_COMMON_PANIC_OUTPUT
 
-/*
- * Store a panic log and halt the system for a software-related reasons, such as
- * stack overflow or assertion failure.
- */
-#undef CONFIG_SOFTWARE_PANIC
-
 /*
  * Certain platforms(e.g. eve, poppy) cannot retain panic info in data ram since
  * VCC is powered down on EC reset. On such platforms, panic data needs to be
@@ -1411,6 +1762,27 @@
  */
 #undef CONFIG_CHIP_PANIC_BACKUP
 
+/* Don't save General Purpose Registers during panic */
+#undef CONFIG_PANIC_STRIP_GPR
+
+/* Provide another output method of panic information by console channel */
+#undef CONFIG_PANIC_CONSOLE_OUTPUT
+
+/* When defined, it enables build assert for panic data structure size */
+#undef CONFIG_RO_PANIC_DATA_SIZE
+
+/*
+ * When defined, it enables system safe mode. System safe mode allows the AP to
+ * capture the EC state after a panic.
+ */
+#undef CONFIG_SYSTEM_SAFE_MODE
+#define CONFIG_SYSTEM_SAFE_MODE_TIMEOUT_MSEC 2000
+/*
+ * Prints the stack of the faulting task to the console buffer in system safe
+ * mode.
+ */
+#define CONFIG_SYSTEM_SAFE_MODE_PRINT_STACK
+
 /*
  * Provide the default GPIO abstraction layer.
  * You want this unless you are doing a really tiny firmware.
@@ -1439,6 +1811,13 @@
  */
 #undef CONFIG_IO_EXPANDER
 
+/*
+ * Enable reading levels for whole IO expander port with one call.
+ * This adds 'get_port' function pointer to 'ioexpander_drv' structure.
+ * Most drivers don't implement this functionality.
+ */
+#undef CONFIG_IO_EXPANDER_SUPPORT_GET_PORT
+
 /*
  * EC's supporting powering down GPIO pins.
  * Add flag GPIO_POWER_DOWN and additional API's.
@@ -1451,6 +1830,9 @@
  */
 #define CONFIG_COMMON_RUNTIME
 
+/* Allow deferred (async) flash protect*/
+#define CONFIG_FLASH_PROTECT_DEFERRED
+
 /* Provide common core code to handle the operating system timers. */
 #define CONFIG_COMMON_TIMER
 
@@ -1515,10 +1897,10 @@
 /* Support for EC-EC communication */
 
 /*
- * Board is master or slave in EC-EC communication.
+ * Board is client or server in EC-EC communication.
  */
-#undef CONFIG_EC_EC_COMM_MASTER
-#undef CONFIG_EC_EC_COMM_SLAVE
+#undef CONFIG_EC_EC_COMM_CLIENT
+#undef CONFIG_EC_EC_COMM_SERVER
 
 /*
  * Board support battery-related functions in EC-EC communication.
@@ -1629,7 +2011,7 @@
 #undef CONFIG_DEVICE_STATE
 
 /* Support DMA transfers inside the EC */
-#undef CONFIG_DMA
+#undef CONFIG_DMA_CROS
 
 /* Use the common interrupt handlers for DMA IRQs */
 #define CONFIG_DMA_DEFAULT_HANDLERS
@@ -1658,8 +2040,10 @@
 /* Maximal EC sampling rate */
 #undef CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ
 
+#ifndef CONFIG_ZEPHYR
 /* Support EC chip internal data EEPROM */
 #undef CONFIG_EEPROM
+#endif /* CONFIG_ZEPHYR */
 
 /*
  * Support for sending emulated sysrq events to AP (on designs with a keyboard,
@@ -1676,6 +2060,9 @@
 /* Default debounce time for external power signal */
 #define CONFIG_EXTPOWER_DEBOUNCE_MS 30
 
+/* Enable fake shared memory buffer, which is used by emulators. */
+#undef CONFIG_FAKE_SHMEM
+
 /*****************************************************************************/
 /* Number of cooling fans. Undef if none. */
 #undef CONFIG_FANS
@@ -1707,11 +2094,20 @@
  */
 #undef CONFIG_FAN_UPDATE_PERIOD
 
+/*
+ * Enable fan slow response control mechanism.
+ * A specific type of fan needs a longer time to output the TACH
+ * signal to EC after EC outputs the PWM signal to the fan.
+ * During this period, the driver will read two consecutive RPM = 0.
+ * In this case, don't step the PWM duty too aggressively
+ */
+#undef CONFIG_FAN_BYPASS_SLOW_RESPONSE
+
 /*****************************************************************************/
 /* Flash configuration */
 
 /* This enables console commands and higher-level features */
-#define CONFIG_FLASH
+#define CONFIG_FLASH_CROS
 /* This enables chip-specific access functions */
 #define CONFIG_FLASH_PHYSICAL
 #undef CONFIG_FLASH_BANK_SIZE
@@ -1728,6 +2124,11 @@
 
 /* Base address of program memory */
 #undef CONFIG_PROGRAM_MEMORY_BASE
+/* Base address of program memory (physical address of AP) */
+#undef CONFIG_PROGRAM_MEMORY_BASE_LOAD
+
+/* ec.bin image will be padded to match flash size. */
+#define CONFIG_IMAGE_PADDING
 
 /*
  * EC code can reside on internal or external storage. Only one of these
@@ -1757,6 +2158,13 @@
  */
 #undef CONFIG_FLASH_PROTECT_RW
 
+/*
+ * Enable Flash Write Protect by default. Some platforms like Servo_v4
+ * development tools do not use write protection. This enables the feature
+ * to be removed to save flash space
+ */
+#define CONFIG_CMD_FLASH_WP
+
 /*
  * Store persistent write protect for the flash inside the flash data itself.
  * This allows ECs with internal flash to emulate something closer to a SPI
@@ -1813,7 +2221,7 @@
 #undef CONFIG_FLASH_REGION_TYPE_COUNT
 
 /* Total size of writable flash */
-#undef CONFIG_FLASH_SIZE
+#undef CONFIG_FLASH_SIZE_BYTES
 
 /* Minimum flash write size (in bytes) */
 #undef CONFIG_FLASH_WRITE_SIZE
@@ -1830,10 +2238,12 @@
 
 /*****************************************************************************/
 /* Fingerprint Sensor Configuration */
-#undef CONFIG_FP_SENSOR
+#undef CONFIG_FINGERPRINT_MCU
 #undef CONFIG_FP_SENSOR_FPC1025
 #undef CONFIG_FP_SENSOR_FPC1035
 #undef CONFIG_FP_SENSOR_FPC1145
+#undef CONFIG_FP_SENSOR_ELAN80
+#undef CONFIG_FP_SENSOR_ELAN515
 
 /*****************************************************************************/
 
@@ -1843,8 +2253,13 @@
 /* Allow EC serial console input to wake up the EC from STOP mode */
 #undef CONFIG_FORCE_CONSOLE_RESUME
 
+#ifndef CONFIG_ZEPHYR
 /* Enable support for floating point unit */
 #undef CONFIG_FPU
+#endif /* CONFIG_ZEPHYR */
+
+/* Enable warnings on FPU exceptions */
+#undef CONFIG_FPU_WARNINGS
 
 /*****************************************************************************/
 /* Firmware region configuration */
@@ -1898,6 +2313,16 @@
 #undef CONFIG_RO_HDR_MEM_OFF
 #undef CONFIG_RO_HDR_SIZE
 
+/*
+ * Support for saving extended reset flags in backup RAM.
+ *
+ * Please undefine it when RO firmware doesn't support extended reset flags.
+ * Otherwise, compatibility between RO and RW will be broken, because
+ * BKPDATA_INDEX_SAVED_RESET_FLAGS_2 was defined in the middle of bkpdata_index
+ * enum.
+ */
+#define CONFIG_STM32_EXTENDED_RESET_FLAGS
+
 /*
  * Write protect region offset / size. This region normally encompasses the
  * RO image, but may also contain additional images or data.
@@ -1920,7 +2345,6 @@
 /* If defined, protect rollback region readback using MPU. */
 #undef CONFIG_ROLLBACK_MPU_PROTECT
 
-
 /*
  * If defined, inject some locally generated entropy when secret is updated,
  * using board_get_entropy function.
@@ -1961,6 +2385,11 @@
  */
 #undef CONFIG_FW_RESET_VECTOR
 
+/*
+ * Always disable the write protect function
+ */
+#undef CONFIG_WP_DISABLE
+
 /*****************************************************************************/
 /* Motion sensor based gesture recognition information */
 /* These all require HAS_TASK_MOTIONSENSE to work */
@@ -1980,12 +2409,9 @@
 /* Sensor sampling interval for gesture recognition */
 #undef CONFIG_GESTURE_SAMPLING_INTERVAL_MS
 
-/* Which sensor to look for double tap recognition */
+/* Enable double tap support. */
 #undef CONFIG_GESTURE_SENSOR_DOUBLE_TAP
 
-/* Use for waking up host */
-#undef CONFIG_GESTURE_SENSOR_DOUBLE_TAP_FOR_HOST
-
 /*
  * Double tap detection parameters
  * Double tap works by looking for two isolated Z-axis accelerometer impulses
@@ -1997,15 +2423,19 @@
  * which to check for relatively calm periods. In between the two impulses
  * there is a minimum and maximum interstice time allowed.
  *
- * Define an acceleration threshold to dectect a tap, in mg.
+ * Define an acceleration threshold to detect a tap, in mg.
+ * Which sensor to look for double tap recognition.
+ * Use for waking up host.
  */
 #undef CONFIG_GESTURE_TAP_OUTER_WINDOW_T
 #undef CONFIG_GESTURE_TAP_INNER_WINDOW_T
 #undef CONFIG_GESTURE_TAP_MIN_INTERSTICE_T
 #undef CONFIG_GESTURE_TAP_MAX_INTERSTICE_T
 #undef CONFIG_GESTURE_TAP_THRES_MG
+#undef CONFIG_GESTURE_TAP_SENSOR
+#undef CONFIG_GESTURE_TAP_FOR_HOST
 
-/* Which sensor to look for significant motion activity */
+/* Significant motion activity */
 #undef CONFIG_GESTURE_SIGMO
 
 /*
@@ -2014,12 +2444,18 @@
  * and check for movement again with proof milli-seconds.
  */
 #undef CONFIG_GESTURE_SIGMO_PROOF_MS
+#undef CONFIG_GESTURE_SIGMO_SENSOR
 #undef CONFIG_GESTURE_SIGMO_SKIP_MS
 #undef CONFIG_GESTURE_SIGMO_THRES_MG
 
 /* Support getting gpio flags. */
 #undef CONFIG_GPIO_GET_EXTENDED
 
+/*
+ * GPU Drivers
+ */
+#undef CONFIG_GPU_NVIDIA
+
 /* Do we want to detect the lid angle? */
 #undef CONFIG_LID_ANGLE
 
@@ -2084,11 +2520,7 @@
 #undef CONFIG_HOST_COMMAND_STATUS
 
 /* clear bit(s) to mask reporting of an EC_HOST_EVENT_XXX event(s) */
-#define CONFIG_HOST_EVENT_REPORT_MASK 0xffffffff
-#define CONFIG_HOST_EVENT64_REPORT_MASK 0xffffffffffffffffULL
-
-/* Config option to support 64-bit hostevents and wake-masks. */
-#define CONFIG_HOST_EVENT64
+#define CONFIG_HOST_EVENT_REPORT_MASK 0xffffffffffffffffULL
 
 /*
  * The host commands are sorted in the .rodata.hcmds section so use the binary
@@ -2116,7 +2548,7 @@
 #ifdef HAS_TASK_HOSTCMD
 #define CONFIG_HOSTCMD_EVENTS
 #else
-#undef  CONFIG_HOSTCMD_EVENTS
+#undef CONFIG_HOSTCMD_EVENTS
 #endif
 
 /*
@@ -2127,15 +2559,16 @@
 #undef CONFIG_HOSTCMD_FLASH_SPI_INFO
 
 /*
- * For ECs where the host command interface is I2C, slave
+ * For ECs where the host command interface is I2C, peripheral
  * address which the EC will respond to.
  */
-#undef CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS
+#undef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
 
 /*
- * Accept EC host commands over the SPI slave (SPS) interface.
+ * Accept EC host commands over the SPI host interface.  The AP is SPI
+ * controller and the EC is the SPI peripheral for this configuration.
  */
-#undef CONFIG_HOSTCMD_SPS
+#undef CONFIG_HOST_INTERFACE_SHI
 
 /*
  * Host command rate limiting assures EC will have time to process lower
@@ -2145,9 +2578,9 @@
  * recess period of CONFIG_HOSTCMD_RATE_LIMITING_RECESS will be
  * enforced.
  */
-#define CONFIG_HOSTCMD_RATE_LIMITING_PERIOD   (500 * MSEC)
-#define CONFIG_HOSTCMD_RATE_LIMITING_MIN_REST (3   * MSEC)
-#define CONFIG_HOSTCMD_RATE_LIMITING_RECESS   (20  * MSEC)
+#define CONFIG_HOSTCMD_RATE_LIMITING_PERIOD (500 * MSEC)
+#define CONFIG_HOSTCMD_RATE_LIMITING_MIN_REST (3 * MSEC)
+#define CONFIG_HOSTCMD_RATE_LIMITING_RECESS (20 * MSEC)
 
 /* PD MCU supports host commands */
 #undef CONFIG_HOSTCMD_PD
@@ -2167,9 +2600,6 @@
 /* Board supports RTC host commands */
 #undef CONFIG_HOSTCMD_RTC
 
-/* For access to VBNV on-EC battery-backed storage */
-#undef CONFIG_HOSTCMD_VBNV_CONTEXT
-
 /* EC controls the board's SKU ID and can report that to the AP */
 #undef CONFIG_HOSTCMD_SKUID
 
@@ -2195,16 +2625,24 @@
 /* Set entry in PD MCU's device rw_hash table */
 #define CONFIG_HOSTCMD_RWHASHPD
 
-#if !defined(TEST_BUILD) && !defined(TEST_FUZZ)
 /* Enable EC_CMD_LOCATE_CHIP */
 #define CONFIG_HOSTCMD_LOCATE_CHIP
-#endif
 
 /* Command to get the EC uptime (and optionally AP reset stats) */
 #define CONFIG_HOSTCMD_GET_UPTIME_INFO
 
-/* List of host commands whose debug output will be suppressed */
-#undef CONFIG_SUPPRESSED_HOST_COMMANDS
+/* Include host command to control I2C busses (get, set speed, etc.) */
+#undef CONFIG_HOSTCMD_I2C_CONTROL
+
+/*
+ * List of host commands whose debug output will be suppressed
+ * By default remove periodic commands and commands called often (SENSE).
+ */
+#define CONFIG_SUPPRESSED_HOST_COMMANDS                                        \
+	EC_CMD_CONSOLE_SNAPSHOT, EC_CMD_CONSOLE_READ, EC_CMD_USB_PD_DISCOVERY, \
+		EC_CMD_USB_PD_POWER_INFO, EC_CMD_PD_GET_LOG_ENTRY,             \
+		EC_CMD_MOTION_SENSE_CMD, EC_CMD_GET_NEXT_EVENT,                \
+		EC_CMD_GET_UPTIME_INFO
 
 /*****************************************************************************/
 
@@ -2269,6 +2707,13 @@
  */
 #undef CONFIG_HIBERNATE_PSL_VCC1_RST_WAKEUP
 
+/*
+ * Compensate the elapsed time for the RTC which couldn't work in hibernate PSL
+ * after hibernation wake-up. Currently, NPCX9 supports LCT to compensate the
+ * elapsed time for the RTC.
+ */
+#undef CONFIG_HIBERNATE_PSL_COMPENSATE_RTC
+
 /*
  * Chip supports a 64-bit hardware timer and implements
  * __hw_clock_source_read64 and __hw_clock_source_set64.
@@ -2285,12 +2730,20 @@
 /*****************************************************************************/
 /* I2C configuration */
 
+#ifndef CONFIG_ZEPHYR
 #undef CONFIG_I2C
+#endif /* CONFIG_ZEPHYR */
 #undef CONFIG_I2C_DEBUG
 #undef CONFIG_I2C_DEBUG_PASSTHRU
 #undef CONFIG_I2C_PASSTHRU_RESTRICTED
 #undef CONFIG_I2C_VIRTUAL_BATTERY
 
+/*
+ * Define this configuration to support smart battery MFG function
+ * for virtual battery.
+ */
+#undef CONFIG_SMART_BATTERY_OPTIONAL_MFG_FUNC
+
 /*
  * Define this option if an i2c bus may be unpowered at a certain point during
  * runtime.  An example could be, a sensor bus which is not needed in lower
@@ -2301,16 +2754,16 @@
 #undef CONFIG_I2C_BUS_MAY_BE_UNPOWERED
 
 /*
- * Conservative I2C reading size per single transaction. For example, register
- * of stm32f0 and stm32l4 are limited to be 8 bits for this field.
+ * Conservative I2C transmission size per single transaction. For example,
+ * register of stm32f0 and stm32l4 are limited to be 8 bits for this field.
  */
-#define CONFIG_I2C_CHIP_MAX_READ_SIZE 255
+#define CONFIG_I2C_CHIP_MAX_TRANSFER_SIZE 255
 
 /*
  * Enable i2c_xfer() for receiving request larger than
- * CONFIG_I2C_CHIP_MAX_READ_SIZE.
+ * CONFIG_I2C_CHIP_MAX_TRANSFER_SIZE.
  */
-#undef CONFIG_I2C_XFER_LARGE_READ
+#undef CONFIG_I2C_XFER_LARGE_TRANSFER
 
 /*
  * If defined, makes i2c_xfer callback into board-provided functions before the
@@ -2321,14 +2774,14 @@
 #undef CONFIG_I2C_XFER_BOARD_CALLBACK
 
 /*
- * EC uses an I2C master interface.
+ * EC uses an I2C controller interface.
  * Note: if this is defined, i2c_init() will be called
  * automatically at board boot.
  */
-#undef CONFIG_I2C_MASTER
+#undef CONFIG_I2C_CONTROLLER
 
-/* EC uses an I2C slave interface */
-#undef CONFIG_I2C_SLAVE
+/* EC uses an I2C peripheral interface */
+#undef CONFIG_I2C_PERIPHERAL
 
 /* Defines I2C operation retry count when slave nack'd(EC_ERROR_BUSY) */
 #define CONFIG_I2C_NACK_RETRY_COUNT 0
@@ -2361,6 +2814,7 @@
  */
 #undef CONFIG_I2C_MULTI_PORT_CONTROLLER
 
+#ifndef CONFIG_ZEPHYR
 /*
  * Enable I2C bitbang driver.
  *
@@ -2372,6 +2826,7 @@
  * {"battery", 2, 100, GPIO_I2C3_SCL, GPIO_I2C3_SDA, .drv = &bitbang_drv},
  */
 #undef CONFIG_I2C_BITBANG
+#endif /* CONFIG_ZEPHYR */
 
 /*
  * If defined, reduce I2C traffic from update functions (i2c_update8/16
@@ -2429,10 +2884,17 @@
  * Compile driver for INA219 or INA231 or INA3221.
  * Only one of these may be defined (if any).
  */
+#ifndef CONFIG_ZEPHYR
+/*
+ * These symbols also exist as Kconfigs in Zephyr. Zephyr based boards
+ * need to use the upstream driver, or these symbols need to be changed
+ * downstream to not conflict.
+ */
 #undef CONFIG_INA219
-#undef CONFIG_INA231
+#undef CONFIG_INA236
 #undef CONFIG_INA3221
-
+#endif /* CONFIG_ZEPHYR */
+#undef CONFIG_INA231
 
 /*****************************************************************************/
 /* Inductive charging */
@@ -2442,7 +2904,18 @@
 
 /******************************************************************************/
 
-/* Support IT8801 I/O expander. */
+/* Support CCGXXF I/O expander built inside PD chip */
+#undef CONFIG_IO_EXPANDER_CCGXXF
+
+/*
+ * Support IT8801 I/O expander.
+ *
+ * I2C address KB_DISCRETE_I2C_ADDR_FLAGS and I2C port
+ * I2C_PORT_KB_DISCRETE must be defined as well.
+ * Note: these values are only used when accessing the keyboard and PWM
+ * function of the IT8801 chip.  I/O expander functions are accessed using
+ * the ioex_config[] array.
+ */
 #undef CONFIG_IO_EXPANDER_IT8801
 
 /* Support Nuvoton NCT38xx I/O expander. */
@@ -2451,9 +2924,15 @@
 /* Support NXP PCA9534 I/O expander. */
 #undef CONFIG_IO_EXPANDER_PCA9534
 
+/* Support NXP PCA9675 I/O expander. */
+#undef CONFIG_IO_EXPANDER_PCA9675
+
 /* Support NXP PCAL6408 I/O expander. */
 #undef CONFIG_IO_EXPANDER_PCAL6408
 
+/* Support TI TCA64xxA I/O expander. */
+#undef CONFIG_IO_EXPANDER_TCA64XXA
+
 /* Number of IO Expander ports */
 #undef CONFIG_IO_EXPANDER_PORT_COUNT
 
@@ -2473,6 +2952,23 @@
  */
 #undef CONFIG_IT83XX_FLASH_CLOCK_48MHZ
 
+/*
+ * If this option is enabled, EC will assert GPG1 pin to reset itself instead of
+ * triggering an internal reset while receiving a reset request.
+ *
+ * IMPORTANT:
+ * - Don't enable this option if board doesn't support the mechanism.
+ * - If this option is enabled, please don't declare GPG1 signal in gpio.inc to
+ *   keep its output level is low after reset.
+ */
+#undef CONFIG_IT83XX_HARD_RESET_BY_GPG1
+
+/*
+ * Use i2c command queue mode for a single i2c transaction.
+ * (Applied to port D, E, and F)
+ */
+#undef CONFIG_IT83XX_I2C_CMD_QUEUE
+
 /*
  * Enable it if EC's VBAT won't go low when system's power isn't
  * presented (no battery and no AC)
@@ -2487,6 +2983,32 @@
 /* To define it, if I2C channel C and PECI used at the same time. */
 #undef CONFIG_IT83XX_SMCLK2_ON_GPC7
 
+/*
+ * Enable board to tune cc physical parameters (ex.rising, falling time).
+ * NOTE: board must define board_get_cc_tuning_parameter(enum usbpd_port port)
+ *       function.
+ */
+#undef CONFIG_IT83XX_TUNE_CC_PHY
+
+/*
+ * Enable the corresponding config option, according to EC's VCC is connected
+ * to 1.8V or 3.3V
+ */
+#undef CONFIG_IT83XX_VCC_1P8V
+#undef CONFIG_IT83XX_VCC_3P3V
+
+/*
+ * Overwrite integer multiplication and division arithmetic library routines
+ * with using hardware multiplication and division and nop instructions.
+ */
+#undef CONFIG_IT8XXX2_MUL_WORKAROUND
+
+/*
+ * Support the standard integer multiplication and division instruction
+ * extension.
+ */
+#define CONFIG_RISCV_EXTENSION_M
+
 /*
  * If this is not defined, the firmware will revert the JTAG selection
  * triggered by the hardware strap pin.
@@ -2536,7 +3058,7 @@
  * chip. You might want this enabled if the keyboard is indirectly connected
  * to the EC, perhaps through an I2C controller.
  */
-#undef CONFIG_KEYBOARD_NOT_RAW
+#undef CONFIG_KEYBOARD_DISCRETE
 
 /* The board uses a negative edge-triggered GPIO for keyboard interrupts. */
 #undef CONFIG_KEYBOARD_IRQ_GPIO
@@ -2553,6 +3075,7 @@
  *  - A response to EC_CMD_GET_KEYBD_CONFIG command from coreboot
  *  - Boards can specify their custom layout for top keys.
  */
+/* Keyboard features */
 #define CONFIG_KEYBOARD_VIVALDI
 
 /* Compile code for MKBP keyboard protocol */
@@ -2561,12 +3084,6 @@
 /* Support keyboard factory test scanning */
 #undef CONFIG_KEYBOARD_FACTORY_TEST
 
-/*
- * Keyboard config (struct keyboard_scan_config) is in board.c.  If this is
- * not defined, default values from common/keyboard_scan.c will be used.
- */
-#undef CONFIG_KEYBOARD_BOARD_CONFIG
-
 /*
  * Support for boot key combinations (e.g. refresh key being held on boot to
  * trigger recovery).
@@ -2595,6 +3112,9 @@
  */
 #define CONFIG_KEYBOARD_RUNTIME_KEYS
 
+/* Add support for ADC based antighost feature */
+#undef CONFIG_KEYBOARD_SCAN_ADC
+
 /*
  * Allow the board layer keyboard customization. If define, the board layer
  * needs to implement:
@@ -2610,16 +3130,14 @@
 #undef CONFIG_KEYBOARD_CUSTOMIZATION
 
 /*
- * Allow board-specific 8042 keyboard callback when a key state is changed.
+ * Allow support multiple keyboard matrix for speical key.
  */
-#undef CONFIG_KEYBOARD_SCANCODE_CALLBACK
+#undef CONFIG_KEYBOARD_MULTIPLE
 
 /*
- * Call board-supplied keyboard_suppress_noise() function when the debounced
- * keyboard state changes.  Some boards use this to send a signal to the audio
- * codec to suppress typing noise picked up by the microphone.
+ * Allow board-specific 8042 keyboard callback when a key state is changed.
  */
-#undef CONFIG_KEYBOARD_SUPPRESS_NOISE
+#undef CONFIG_KEYBOARD_SCANCODE_CALLBACK
 
 /*
  * Enable keyboard testing functionality. This enables a message which receives
@@ -2641,14 +3159,24 @@
 #undef CONFIG_KEYBOARD_KSO_HIGH_DRIVE
 
 /*
- * Add support for keyboards with language ID pins
+ * Enable keypad (a palm-sized keyboard section usually placed on the far right)
  */
-#undef CONFIG_KEYBOARD_LANGUAGE_ID
+#undef CONFIG_KEYBOARD_KEYPAD
 
 /*
- * Enable keypad (a palm-sized keyboard section usually placed on the far right)
+ * Enable strict debouncer. A strict debouncer waits until debounce is done
+ * before registering key up/down while a non-strict debouncer registers a key
+ * up/down as soon as a key is pressed or released.
+ *
+ * A strict debouncer is robust against unintentional key presses, caused by a
+ * device drop, for example. However, its latency isn't as fast as a non-strict
+ * debouncer.
+ *
+ * If a strict debouncer is used, it's recommended to set debounce_down_us and
+ * debounce_up_us to an equal value. This guarantees key events are registered
+ * in the order the keys are pressed.
  */
-#undef CONFIG_KEYBOARD_KEYPAD
+#undef CONFIG_KEYBOARD_STRICT_DEBOUNCE
 
 /*
  * Enable the 8042 AUX port. This is typically used for PS/2 mouse devices.
@@ -2673,11 +3201,19 @@
  */
 #undef CONFIG_LED_POLICY_STD
 
+#ifndef CONFIG_ZEPHYR
 /*
  * Support common PWM-controlled LEDs that conform to the Chrome OS LED
  * behaviour specification.
  */
 #undef CONFIG_LED_PWM
+#endif /* CONFIG_ZEPHYR */
+
+/*
+ * Support common PWM-controlled LEDs that do not conform to the Chrom OS LED
+ * behavior specification
+ */
+#undef CONFIG_LED_PWM_TASK_DISABLED
 
 /*
  * Here are some recommended color settings by default, but a board can change
@@ -2690,6 +3226,10 @@
 #define CONFIG_LED_PWM_SOC_SUSPEND_COLOR EC_LED_COLOR_GREEN
 #define CONFIG_LED_PWM_LOW_BATT_COLOR EC_LED_COLOR_AMBER
 
+/* By default, 500 ms period, 50% duty cycle. */
+#define LED_CHARGER_ERROR_ON_TIME 1
+#define LED_CHARGER_ERROR_PERIOD 2
+
 /*
  * By default the PWM LED behaviour is reflected on both LEDs and includes the
  * chipset state, battery state, as well as the charging state.  Enable
@@ -2723,12 +3263,6 @@
  */
 #undef CONFIG_LED_ONOFF_STATES_BAT_LOW
 
-/*
- * Adds a power LED under the control of the board-defined lookup table.
- * Must be used with the CONFIG_LED_ONOFF_STATES option.
- */
-#undef CONFIG_LED_POWER_LED
-
 /*
  * LEDs for LED_POLICY STD may be inverted.  In this case they are active low
  * and the GPIO names will be GPIO_LED..._L.
@@ -2737,11 +3271,19 @@
 #undef CONFIG_LED_POWER_ACTIVE_LOW
 
 /* Support for LED driver chip(s) */
-#undef CONFIG_LED_DRIVER_DS2413  /* Maxim DS2413, on one-wire interface */
-#undef CONFIG_LED_DRIVER_LM3509  /* LM3509, on I2C interface */
+#undef CONFIG_LED_DRIVER_DS2413 /* Maxim DS2413, on one-wire interface */
+#undef CONFIG_LED_DRIVER_LM3509 /* LM3509, on I2C interface */
 #undef CONFIG_LED_DRIVER_LM3630A /* LM3630A, on I2C interface */
-#undef CONFIG_LED_DRIVER_LP5562  /* LP5562, on I2C interface */
-#undef CONFIG_LED_DRIVER_OZ554   /* O2Micro OZ554, on I2C */
+#undef CONFIG_LED_DRIVER_LP5562 /* LP5562, on I2C interface */
+#undef CONFIG_LED_DRIVER_MP3385 /* MPS MP3385, on I2C */
+#undef CONFIG_LED_DRIVER_OZ554 /* O2Micro OZ554, on I2C */
+#undef CONFIG_LED_DRIVER_IS31FL3733B /* Lumissil IS31FL3733B on I2C */
+#undef CONFIG_LED_DRIVER_IS31FL3743B /* Lumissil IS31FL3743B on SPI */
+#undef CONFIG_LED_DRIVER_AW20198 /* Awinic AW20198 on I2C */
+#undef CONFIG_LED_DRIVER_TLC59116F /* TLC59116F on I2C */
+
+/* Enable late init for is31fl3743b. Work around b:232443638. */
+#undef CONFIG_IS31FL3743B_LATE_INIT
 
 /* Offset in flash where little firmware will live. */
 #undef CONFIG_LFW_OFFSET
@@ -2822,32 +3364,35 @@
 #undef CONFIG_HID_HECI
 
 /* Support host command interface over HECI */
-#undef CONFIG_HOSTCMD_HECI
+#undef CONFIG_HOST_INTERFACE_HECI
 
 /*
  * EC supports x86 host communication with AP. This can either be through LPC
  * or eSPI. The CONFIG_HOSTCMD_X86 will get automatically defined if either
- * CONFIG_HOSTCMD_LPC or CONFIG_HOSTCMD_ESPI are defined. LPC and eSPI are
- * mutually exclusive.
+ * CONFIG_HOST_INTERFACE_LPC or CONFIG_HOST_INTERFACE_ESPI are defined.
+ * LPC and eSPI are mutually exclusive.
  */
 #undef CONFIG_HOSTCMD_X86
 /* Support host command interface over LPC bus. */
-#undef CONFIG_HOSTCMD_LPC
+#undef CONFIG_HOST_INTERFACE_LPC
 /* Support host command interface over eSPI bus. */
-#undef CONFIG_HOSTCMD_ESPI
+#undef CONFIG_HOST_INTERFACE_ESPI
+/* Support host command interface over USB. */
+#undef CONFIG_HOST_INTERFACE_USB
 
 /*
- * SLP signals (SLP_S3 and SLP_S4) use virtual wires intead of physical pins
- * with eSPI interface.
+ * SLP signals (SLP_S3, SLP_S4, and SLP_S5) use virtual wires instead of
+ * physical pins with eSPI interface.
  */
-#undef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#undef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#undef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+#undef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
+#undef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S5
 
 /* MCHP next two items are EC eSPI slave configuration */
 /* Maximum clock frequence eSPI EC slave advertises
  * Values in MHz are 20, 25, 33, 50, and 66
  */
-#undef CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ
+#undef CONFIG_HOST_INTERFACE_ESPI_EC_MAX_FREQ
 
 /* EC eSPI slave advertises IO lanes
  * 0 = Single
@@ -2855,7 +3400,7 @@
  * 2 = Single and Quad
  * 3 = Single, Dual, and Quad
  */
-#undef CONFIG_HOSTCMD_ESPI_EC_MODE
+#undef CONFIG_HOST_INTERFACE_ESPI_EC_MODE
 
 /* Bit map of eSPI channels EC advertises
  * bit[0] = 1 Peripheral channel
@@ -2863,7 +3408,38 @@
  * bit[2] = 1 OOB channel
  * bit[3] = 1 Flash channel
  */
-#undef CONFIG_HOSTCMD_ESPI_EC_CHAN_BITMAP
+#undef CONFIG_HOST_INTERFACE_ESPI_EC_CHAN_BITMAP
+
+/*
+ * Background information (from Intel eSPI Compatibility Specification):
+ * eSPI_Reset# may be asserted as part of:
+ * (1) a normal Deep-Sx entry:
+ *    A normal eSPI_Reset# assertion is preceded by {Host,OOB}_Reset_Warn/Ack
+ *    handshakes (using tunneled VWs) between the PCH/SoC and the EC/BMC.
+ *    The eSPI Specification states that the SLP_* signals are reset based on
+ *    eSPI_Reset#. However, for platforms that support Deep Sleep Well (DSW),
+ *    the SLP_{S3,S4,S5,LAN,WLAN}# signals reside in the DSW power well and are
+ *    reset by DSW_PWROK.
+ *    In PCH/SoC, the states of these pins will be communicated to the EC/BMC
+ *    as Virtual Wires over the eSPI interface. As a result, the EC/BMC needs
+ *    to handle/maintain these pins' states during Deep-Sx.
+ *
+ * (2) a Global Reset event:
+ *    It could happen in the middle of an on-going eSPI transaction, which is
+ *    immediately truncated. All tunneled VWs, including
+ *    SLP_{S3,S4,S5,LAN,WLAN}#, are returned to their default reset default
+ *    state upon entry into Global Reset. Note that in the case of a Global
+ *    Reset event, eSPI Virtual Wire messages deasserting the states of these
+ *    wires will not be issued by the eSPI-MC. The eSPI Slave device is
+ *    responsible for resetting the states of all its VWs at the appropriate
+ *    platform reset events.
+ *
+ * Enable this config to reset SLP* VW when eSPI_RST is asserted for the Global
+ * Reset event case.
+ * Don't enable this config if the platform implements the Deep-Sx entry as EC
+ * needs to maintain these pins' states per request.
+ */
+#undef CONFIG_HOST_INTERFACE_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST
 
 /* Base address of low power RAM. */
 #undef CONFIG_LPRAM_BASE
@@ -2871,8 +3447,10 @@
 /* Size of low power RAM. */
 #undef CONFIG_LPRAM_SIZE
 
+#ifndef CONFIG_ZEPHYR
 /* Use Link-Time Optimizations to try to reduce the firmware code size */
 #undef CONFIG_LTO
+#endif /* CONFIG_ZEPHYR */
 
 /* Provide rudimentary malloc/free like services for shared memory. */
 #undef CONFIG_MALLOC
@@ -2883,6 +3461,19 @@
 /* Include sensor online calibration (requires CONFIG_FPU) */
 #undef CONFIG_ONLINE_CALIB
 
+/*
+ * Spoof the data for online calibration. When this flag is enabled, every
+ * reading with the flag MOTIONSENSE_FLAG_IN_SPOOF_MODE will be treated as a
+ * new calibration point. This should be used in conjunction with
+ * CONFIG_ACCEL_SPOOF_MODE. To trigger an accelerometer calibration for
+ * example, enable both config flags, connect to the cr50 terminal and run:
+ * $ accelspoof id on X Y Z
+ * This will spoof a reading of (X, Y, Z) from the sensor and treat those
+ * values as the calibration result (bypassing the calibration for the given
+ * sensor ID).
+ */
+#undef CONFIG_ONLINE_CALIB_SPOOF_MODE
+
 /*
  * Duration after which an entry in the temperature cache is considered stale.
  * Defaults to 5 minutes if not set.
@@ -2932,12 +3523,29 @@
  */
 #undef CONFIG_MCDP28X0
 
-/* Define clock input to MFT module. */
-#undef CONFIG_MFT_INPUT_LFCLK
-
 /* Minute-IA watchdog timer vector number. */
 #define CONFIG_MIA_WDT_VEC 0xFF
 
+/*
+ * ISL9241 Configures the switching frequency and overrides the default
+ * switching frequency set by PROG pin. The valid frequency settings are
+ * find in driver/charger/isl9241.h.
+ */
+#undef CONFIG_ISL9241_SWITCHING_FREQ
+
+/*
+ * ISL9238C disable the CMOUT latch function.
+ */
+#undef CONFIG_ISL9238C_DISABLE_CMOUT_LATCH
+
+/*
+ * ISL9238C enable Force Buck mode.
+ */
+#undef CONFIG_ISL9238C_ENABLE_BUCK_MODE
+
+/* ISL9238C adjusts phase comparator threshold offset */
+#define CONFIG_ISL9238C_BUCK_PHASE_VOLTAGE 0
+
 /* Support MKBP event */
 #undef CONFIG_MKBP_EVENT
 
@@ -2947,6 +3555,9 @@
 /* MKBP events are sent by using GPIO */
 #undef CONFIG_MKBP_USE_GPIO
 
+/* MKBP events GPIO is active high */
+#undef CONFIG_MKBP_USE_GPIO_ACTIVE_HIGH
+
 /*
  * MKBP events are notified by using both a GPIO and a host event.
  *
@@ -2990,8 +3601,15 @@
  */
 #undef CONFIG_MKBP_EVENT_WAKEUP_MASK
 
+/*
+ * Send button, switch and sysrq events via MKBP protocol to the host.
+ */
+#undef CONFIG_MKBP_INPUT_DEVICES
+
+#ifndef CONFIG_ZEPHYR
 /* Support memory protection unit (MPU) */
 #undef CONFIG_MPU
+#endif /* CONFIG_ZEPHYR */
 
 /* Do not try hold I/O pins at frozen level during deep sleep */
 #undef CONFIG_NO_PINHOLD
@@ -3009,8 +3627,10 @@
 #undef CONFIG_PANIC_DATA_BASE
 #undef CONFIG_PANIC_DATA_SIZE
 
+#ifndef CONFIG_ZEPHYR
 /* Support PECI interface to x86 processor */
 #undef CONFIG_PECI
+#endif /* CONFIG_ZEPHYR */
 
 /* Common code for PECI interface to x86 processor */
 #undef CONFIG_PECI_COMMON
@@ -3024,6 +3644,18 @@
  */
 #undef CONFIG_PECI_TJMAX
 
+/*
+ * Enable peripheral charge manager (e.g. NFC/WLC, WPC Qi)
+ */
+#undef CONFIG_PERIPHERAL_CHARGER
+
+/*
+ * Enable CTN730 driver
+ *
+ * CTN730 is NXP's NFC/WLC power transmitter (a.k.a. poller).
+ */
+#undef CONFIG_CTN730
+
 /*****************************************************************************/
 /* PMU config */
 
@@ -3054,6 +3686,12 @@
  */
 #define CONFIG_PORT80_PRINT_IN_INT 0
 
+/*
+ * Allow Port80 common layer to dump 4-byte Port80 code. This is only supported
+ * on NPCX9 (and latter) chips.
+ */
+#undef CONFIG_PORT80_4_BYTE
+
 /* MAX695x 7 segment driver */
 #undef CONFIG_MAX695X_SEVEN_SEGMENT_DISPLAY
 
@@ -3076,7 +3714,7 @@
 #undef CONFIG_POWER_BUTTON_INIT_IDLE
 
 /* Timeout before power button task gives up starting system */
-#define CONFIG_POWER_BUTTON_INIT_TIMEOUT	1
+#define CONFIG_POWER_BUTTON_INIT_TIMEOUT 1
 
 /*
  * Enable delay between DSW_PWROK and PWRBTN assertion.
@@ -3119,6 +3757,9 @@
 /* Support S0ix */
 #undef CONFIG_POWER_S0IX
 
+/* Advertise S4 residency */
+#undef CONFIG_POWER_S4_RESIDENCY
+
 /* Support detecting failure to enter a sleep state (S0ix/S3) */
 #undef CONFIG_POWER_SLEEP_FAILURE_DETECTION
 
@@ -3130,10 +3771,12 @@
 #undef CONFIG_POWER_TRACK_HOST_SLEEP_STATE
 
 /*
- * Implement the '%li' printf format as a *32-bit* integer format,
- * as it might be expected by non-EC code.
+ * Allow the use of the "long" printf length modifier ('l') to be in 32-bit
+ * systems along with any supported conversion specifiers. Note that this also
+ * reenables support for the 'i' printf format. This config will only take
+ * effect if sizeof(long) == sizeof(uint32_t).
  */
-#undef CONFIG_PRINTF_LEGACY_LI_FORMAT
+#undef CONFIG_PRINTF_LONG_IS_32BITS
 
 /*
  * On x86 systems, define this option if the CPU_PROCHOT signal is active low.
@@ -3142,8 +3785,21 @@
  */
 #undef CONFIG_CPU_PROCHOT_ACTIVE_LOW
 
+/*
+ * When the AP enters C10, the power rails VCCIO, VCCSTG, and VCCPLL_OC may be
+ * turned off by the board.  If the PROCHOT# signal is pulled up by any of
+ * these rails, PROCHOT cannot be relied upon while C10 is active.
+ * Enable this option to gate PROCHOT detection when C10 is active.
+ */
+#undef CONFIG_CPU_PROCHOT_GATE_ON_C10
+
+#ifndef CONFIG_ZEPHYR
 /* Support PS/2 interface */
 #undef CONFIG_PS2
+#endif /* CONFIG_ZEPHYR */
+
+/* Support Power Sourcing Equipment */
+#undef CONFIG_PSE_LTC4291
 
 /*
  * Define this option to enable programmable voltage detector which will
@@ -3154,8 +3810,10 @@
 #undef CONFIG_PVD
 
 /*****************************************************************************/
+#ifndef CONFIG_ZEPHYR
 /* Support PWM control */
 #undef CONFIG_PWM
+#endif /* CONFIG_ZEPHYR */
 
 /* Define clock input to PWM module. */
 #undef CONFIG_PWM_INPUT_LFCLK
@@ -3179,8 +3837,39 @@
  */
 #undef CONFIG_PWM_KBLIGHT
 
+/*
+ * Support a GPIO enable pin (set as GPIO_EN_KEYBOARD_BACKLIGHT) for the
+ * keyboard backlight.
+ */
+#undef CONFIG_KBLIGHT_ENABLE_PIN
+
+/*
+ * RGB Keyboard
+ */
+#undef CONFIG_RGB_KEYBOARD
+
+/*
+ * Enable debug messages from a RGB keyboard task.
+ */
+#undef CONFIG_RGB_KEYBOARD_DEBUG
+
+/*
+ * Enable demo for RGB keyboard to run on reset.
+ *
+ * FLOW: In each iteration, a new color is placed in (0,0) and the rest of LEDs
+ * copy colors from adjacent LEDs.
+ *
+ * DOT: A red dot is placed on (0,0) and traverses the grid from top to bottom
+ * left to right. After the entire matrix is traversed, it's repeated with a
+ * new color.
+ */
+#undef CONFIG_RGBKBD_DEMO_FLOW
+#undef CONFIG_RGBKBD_DEMO_DOT
+
+#ifndef CONFIG_ZEPHYR
 /* Support Real-Time Clock (RTC) */
 #undef CONFIG_RTC
+#endif /* CONFIG_ZEPHYR */
 
 /* Size of each RAM bank in chip, default is CONFIG_RAM_SIZE */
 #undef CONFIG_RAM_BANK_SIZE
@@ -3287,9 +3976,11 @@
  * override those defaults with these.
  */
 #undef CONFIG_RO_PUBKEY_ADDR
+#undef CONFIG_RO_PUBKEY_READ_ADDR
 #undef CONFIG_RO_PUBKEY_SIZE
 #undef CONFIG_RW_SIG_ADDR
 #undef CONFIG_RW_SIG_SIZE
+#undef CONFIG_RWSIG_READ_ADDR
 
 /* Size of the serial number if needed */
 #undef CONFIG_SERIALNO_LEN
@@ -3315,18 +4006,15 @@
 /* Storage  offset of sharedobjects library. */
 #undef CONFIG_SHAREDLIB_STORAGE_OFF
 
-/*
- * If defined, the hash module will save its last computed hash when jumping
- * between EC images.
- */
-#undef CONFIG_SAVE_VBOOT_HASH
-
 /* Allow the board to use a GPIO for the SCI# signal. */
 #undef CONFIG_SCI_GPIO
 
 /* Support computing of other hash sizes (without the VBOOT code) */
 #undef CONFIG_SHA256
 
+/* Compute SHA256 by using chip's hardware accelerator */
+#undef CONFIG_SHA256_HW_ACCELERATE
+
 /* Unroll some loops in SHA256_transform for better performance. */
 #undef CONFIG_SHA256_UNROLLED
 
@@ -3354,8 +4042,10 @@
  */
 /* #undef CONFIG_SMBUS */
 
+#ifndef CONFIG_ZEPHYR
 /* Support SPI interfaces */
 #undef CONFIG_SPI
+#endif /* CONFIG_ZEPHYR */
 
 /* Support deprecated SPI protocol version 2. */
 #undef CONFIG_SPI_PROTOCOL_V2
@@ -3387,8 +4077,10 @@
 /* Define the SPI port to use to access the fingerprint sensor */
 #undef CONFIG_SPI_FP_PORT
 
+#ifndef CONFIG_ZEPHYR
 /* Support JEDEC SFDP based Serial NOR flash */
 #undef CONFIG_SPI_NOR
+#endif /* CONFIG_ZEPHYR */
 
 /* Enable SPI_NOR debugging providing additional console output while
  * initializing Serial NOR Flash devices including SFDP discovery. */
@@ -3416,21 +4108,14 @@
  */
 #undef CONFIG_SPI_NOR_SMART_ERASE
 
-/* SPI master feature */
-#undef CONFIG_SPI_MASTER
+/* SPI controller feature */
+#undef CONFIG_SPI_CONTROLLER
 
-/* SPI master halfduplex/3-wire mode */
+/* SPI controller halfduplex/3-wire mode */
 #undef CONFIG_SPI_HALFDUPLEX
 
-/* Support STM32 SPI1 as master. */
-#undef CONFIG_STM32_SPI1_MASTER
-
-/* SPI master configure gpios on init */
-#undef CONFIG_SPI_MASTER_CONFIGURE_GPIOS
-
-/* Support SPI masters without GPIO-specified Chip Selects, instead rely on the
- * SPI master port's hardwired CS pin. */
-#undef CONFIG_SPI_MASTER_NO_CS_GPIOS
+/* Support STM32 SPI1 as controller. */
+#undef CONFIG_STM32_SPI1_CONTROLLER
 
 /* Support MCHP MEC family GP-SPI master(s)
  * Define to 0x01 for GPSPI0 only.
@@ -3439,12 +4124,20 @@
  */
 #undef CONFIG_MCHP_GPSPI
 
+/*
+ * Configure SPI flash read wait time as 1ms
+ * Chip or board can redefine it per design
+ */
+#define CONFIG_SPI_FLASH_READ_WAIT_MS 1
+
+/*
+ * Allow modification to e.g. clock divisor or other fields of spi_devices[].
+ */
+#undef CONFIG_SPI_MUTABLE_DEVICE_LIST
+
 /* Default stack size to use for tasks, in bytes */
 #undef CONFIG_STACK_SIZE
 
-/* Use 32-bit timer for clock source on stm32. */
-#undef CONFIG_STM_HWTIMER32
-
 /* Compile charger detect for STM32 */
 #undef CONFIG_STM32_CHARGER_DETECT
 
@@ -3472,6 +4165,12 @@
  * Also, this will enable PD in RO for TCPMv2.
  */
 #undef CONFIG_SYSTEM_UNLOCKED
+/*
+ * Some systems decouple the CBI eeprom write protection from the
+ * H1_FLASH_WP_ODL via the hardware change. Adds this config to
+ * bypass the cbi eeprom write protection check.
+ */
+#undef CONFIG_BYPASS_CBI_EEPROM_WP_CHECK
 
 /*
  * Device can be a tablet as well as a clamshell.
@@ -3485,13 +4184,13 @@
 
 /*
  * Config to identify what devices use GMR sensor to detect tablet mode. If a
- * board selects this config, it also needs to provide GMR_TABLET_MODE_GPIO_L
+ * board selects this config, it also needs to provide GPIO_TABLET_MODE_L
  * and direct its interrupt to gmr_tablet_switch_isr.
  */
 #undef CONFIG_GMR_TABLET_MODE
 
 /*
- * Board provides board_sensor_at_360 method instead of GMR_TABLET_MODE_GPIO_L
+ * Board provides board_sensor_at_360 method instead of GPIO_TABLET_MODE_L
  * as the means for determining the state of the flipped-360-degree mode.
  */
 #undef CONFIG_GMR_TABLET_MODE_CUSTOM
@@ -3502,6 +4201,12 @@
  */
 #undef CONFIG_BASE_ATTACHED_SWITCH
 
+/*
+ * Add a virtual switch to indicate whether a nearby object is present in front
+ * of the device.
+ */
+#undef CONFIG_FRONT_PROXIMITY_SWITCH
+
 /*
  * Microchip Trace FIFO Debug Port
  */
@@ -3598,26 +4303,28 @@
 #undef CONFIG_TEMP_SENSOR
 
 /* Support particular temperature sensor chips */
-#undef CONFIG_TEMP_SENSOR_ADT7481	/* ADT 7481 sensor, on I2C bus */
-#undef CONFIG_TEMP_SENSOR_BD99992GW	/* BD99992GW PMIC, on I2C bus */
-#undef CONFIG_TEMP_SENSOR_EC_ADC        /* Thermistors on EC's own ADC */
-#undef CONFIG_TEMP_SENSOR_G753		/* G753 sensor, on I2C bus */
-#undef CONFIG_TEMP_SENSOR_G781		/* G781 sensor, on I2C bus */
-#undef CONFIG_TEMP_SENSOR_G782		/* G782 sensor, on I2C bus */
-#undef CONFIG_TEMP_SENSOR_OTI502	/* OTI502 sensor, on I2C bus */
-#undef CONFIG_TEMP_SENSOR_SB_TSI	/* SB_TSI sensor, on I2C bus */
-#undef CONFIG_TEMP_SENSOR_TMP006	/* TI TMP006 sensor, on I2C bus */
-#undef CONFIG_TEMP_SENSOR_TMP411	/* TI TMP411 sensor, on I2C bus */
-#undef CONFIG_TEMP_SENSOR_TMP432	/* TI TMP432 sensor, on I2C bus */
-#undef CONFIG_TEMP_SENSOR_TMP468	/* TI TMP468 sensor, on I2C bus */
-#undef CONFIG_TEMP_SENSOR_F75303	/* Fintek  F75303 sensor, on I2C bus */
-#undef CONFIG_TEMP_SENSOR_AMD_R19ME4070	/* AMD_R19ME4070 sensor, on I2C bus */
+#undef CONFIG_TEMP_SENSOR_ADT7481 /* ADT 7481 sensor, on I2C bus */
+#undef CONFIG_TEMP_SENSOR_BD99992GW /* BD99992GW PMIC, on I2C bus */
+#undef CONFIG_TEMP_SENSOR_EC_ADC /* Thermistors on EC's own ADC */
+#undef CONFIG_TEMP_SENSOR_G753 /* G753 sensor, on I2C bus */
+#undef CONFIG_TEMP_SENSOR_G781 /* G781 sensor, on I2C bus */
+#undef CONFIG_TEMP_SENSOR_G782 /* G782 sensor, on I2C bus */
+#undef CONFIG_TEMP_SENSOR_OTI502 /* OTI502 sensor, on I2C bus */
+#undef CONFIG_TEMP_SENSOR_PCT2075 /* PCT2075 sensor, on I2C bus */
+#undef CONFIG_TEMP_SENSOR_SB_TSI /* SB_TSI sensor, on I2C bus */
+#undef CONFIG_TEMP_SENSOR_TMP006 /* TI TMP006 sensor, on I2C bus */
+#undef CONFIG_TEMP_SENSOR_TMP112 /* TI TMP112 sensor, on I2C bus */
+#undef CONFIG_TEMP_SENSOR_TMP411 /* TI TMP411 sensor, on I2C bus */
+#undef CONFIG_TEMP_SENSOR_TMP432 /* TI TMP432 sensor, on I2C bus */
+#undef CONFIG_TEMP_SENSOR_TMP468 /* TI TMP468 sensor, on I2C bus */
+#undef CONFIG_TEMP_SENSOR_F75303 /* Fintek  F75303 sensor, on I2C bus */
+#undef CONFIG_TEMP_SENSOR_AMD_R19ME4070 /* AMD_R19ME4070 sensor, on I2C bus */
 
 /* Compile common code for thermistor support */
 #undef CONFIG_THERMISTOR
 
 /* Support particular thermistors */
-#undef CONFIG_THERMISTOR_NCP15WB	/* NCP15WB thermistor */
+#undef CONFIG_THERMISTOR_NCP15WB /* NCP15WB thermistor */
 
 /*
  * If defined, image includes lookup tables and helper functions that convert
@@ -3632,10 +4339,14 @@
 
 /*
  * If defined, active-high GPIO which indicates temperature sensor chips are
- * powered.  If not defined, temperature sensors are assumed to be always
+ * powered. The GPIO pin must be defined as GPIO_TEMP_SENSOR_POWER.
+ * If not defined, temperature sensors are assumed to be always
  * powered.
  */
-#undef CONFIG_TEMP_SENSOR_POWER_GPIO
+#undef CONFIG_TEMP_SENSOR_POWER
+
+/* AMD STT (Skin Temperature Tracking) */
+#undef CONFIG_AMD_STT
 
 /* Compile common code for throttling the CPU based on the temp sensors */
 #undef CONFIG_THROTTLE_AP
@@ -3680,6 +4391,15 @@
  */
 #undef CONFIG_DPTF_MULTI_PROFILE
 
+/*
+ * Sometime EC was already driver thermal sensor power pin to high, but sensor
+ * power is still not ready. That cause the system will thermal shutdown when
+ * first boot EC.
+ *
+ * This config can be used to delay thermal sensor read in the first time.
+ */
+#undef CONFIG_TEMP_SENSOR_FIRST_READ_DELAY_MS
+
 /*****************************************************************************/
 /* Touchpad config */
 
@@ -3724,6 +4444,7 @@
 #undef CONFIG_STREAM_USART2
 #undef CONFIG_STREAM_USART3
 #undef CONFIG_STREAM_USART4
+#undef CONFIG_STREAM_USART5
 
 /*****************************************************************************/
 /* USB stream config */
@@ -3751,8 +4472,10 @@
 /* Baud rate for UARTs */
 #define CONFIG_UART_BAUD_RATE 115200
 
+#ifndef CONFIG_ZEPHYR
 /* UART index (number) for EC console */
 #undef CONFIG_UART_CONSOLE
+#endif /* CONFIG_ZEPHYR */
 
 /* UART index (number) for host UART, if present */
 #undef CONFIG_UART_HOST
@@ -3768,11 +4491,10 @@
 #undef CONFIG_UART_PAD_SWITCH
 
 /**
- * This will only be used for Kukui and cortex-m0. Preserve EC reset logs and
- * console logs on SRAM so that the logs will be preserved after EC shutting
- * down or sysjumped. It will keep the contents across EC resets, so we have
- * more information about system states. The contents on SRAM will be cleared
- * when checksum or validity check fails.
+ * Preserve EC reset logs and console logs on SRAM/FLASH so that the logs will
+ * be preserved after EC shutting down or sysjumped. It will keep the contents
+ * across EC resets, so we have more information about system states. The
+ * contents on SRAM will be cleared when checksum or validity check fails.
  */
 #undef CONFIG_PRESERVE_LOGS
 
@@ -3817,6 +4539,12 @@
 /* Driver of LN9310 switchcap */
 #undef CONFIG_LN9310
 
+/* Use this to include support for MP4245 buck boost converter */
+#undef CONFIG_MP4245
+
+/* Use this to include support for MP2964 IMVP9.1 PMIC */
+#undef CONFIG_MP2964
+
 /*****************************************************************************/
 /* USB PD config */
 
@@ -3852,6 +4580,15 @@
  */
 #undef CONFIG_USB_PD_TCPMV2
 
+/*
+ * Enable dynamic PDO selection.
+ *
+ * DPS picks a power efficient voltage regarding to the battery configuration
+ * and the system loading. It monitors PIn (Power In), so VBUS/IBUS ADC
+ * should be supported on the platform.
+ */
+#undef CONFIG_USB_PD_DPS
+
 /*
  * Device Types for TCPMv2.
  *
@@ -3875,23 +4612,45 @@
  * TYPEC_SM - Type-C deals with CC lines voltage level connections
  * PRL_SM - Protocol handles flow and chunking TX and RX messages
  * PE - Policy Engine handles PD communication flow
+ * DPM - Device Policy Manager layer is used to determine port policy
  */
 #define CONFIG_USB_TYPEC_SM
 #define CONFIG_USB_PRL_SM
 #define CONFIG_USB_PE_SM
+#define CONFIG_USB_DPM_SM
 
 /* Enables PD Console commands */
 #define CONFIG_USB_PD_CONSOLE_CMD
 
 /* Enables PD Host commands */
+#ifdef HAS_TASK_HOSTCMD
 #define CONFIG_USB_PD_HOST_CMD
+#endif
 
-/* Support for USB PD alternate mode */
+/* Support for USB PD alternate mode entry */
 #undef CONFIG_USB_PD_ALT_MODE
 
-/* Support for USB PD alternate mode of Downward Facing Port */
+/* Support for USB PD alternate mode entry by a Downward Facing Port */
 #undef CONFIG_USB_PD_ALT_MODE_DFP
 
+/* Support for USB PD alternate mode entry from an Upward Facing Port */
+#undef CONFIG_USB_PD_ALT_MODE_UFP
+
+/* Support for automatic USB PD Discovery VDM probing and storage */
+#undef CONFIG_USB_PD_DISCOVERY
+
+/*
+ * Do not enter USB PD alternate modes or USB4 automatically. Wait for the AP to
+ * direct the EC to enter a mode. This requires AP software support.
+ */
+#undef CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
+
+/* Allow the AP to compose VDMs for us to send */
+#undef CONFIG_USB_PD_VDM_AP_CONTROL
+
+/* Supports DP as UFP-D and requires HPD to DP_ATTEN converter */
+#undef CONFIG_USB_PD_ALT_MODE_UFP_DP
+
 /* HPD is sent to the GPU from the EC via a GPIO */
 #undef CONFIG_USB_PD_DP_HPD_GPIO
 
@@ -3941,6 +4700,25 @@
  */
 #undef CONFIG_USB_PD_DEBUG_LEVEL
 
+/*
+ * Set to a nonzero value to delay PD task startup by the given
+ * amount of time.
+ */
+#define CONFIG_USB_PD_STARTUP_DELAY_MS 0
+
+/*
+ * Define if this board is using runtime flags instead of build time configs
+ * to control USB PD properties.
+ */
+#define CONFIG_USB_PD_FLAGS
+#undef CONFIG_USB_PD_RUNTIME_FLAGS
+
+/*
+ * Define to enable the PD Data Reset Message. This is mandatory for
+ * USB4 and optional for USB 3.2
+ */
+#undef CONFIG_USB_PD_DATA_RESET_MSG
+
 /*
  * Define if this board can enable VBUS discharge (eg. through a GPIO-controlled
  * discharge circuit, or through port controller registers) to discharge VBUS
@@ -4022,8 +4800,8 @@
 #undef CONFIG_USB_PD_IDENTITY_HW_VERS
 #undef CONFIG_USB_PD_IDENTITY_SW_VERS
 
-/* USB PD MCU slave address for host commands */
-#define CONFIG_USB_PD_I2C_SLAVE_ADDR_FLAGS 0x1E
+/* USB PD MCU I2C address for host commands */
+#define CONFIG_USB_PD_I2C_ADDR_FLAGS 0x1E
 
 /* Define if using internal comparator for PD receive */
 #undef CONFIG_USB_PD_INTERNAL_COMP
@@ -4031,6 +4809,17 @@
 /* Record main PD events in a circular buffer */
 #undef CONFIG_USB_PD_LOGGING
 
+/*
+ * Record PRL state transitions in a ring buffer, readable via the `prllog`
+ * console command.
+ */
+#undef CONFIG_USB_PD_PRL_EVENT_LOG
+/*
+ * Number of events that can be stored in the PRL log (after this many, the
+ * oldest entries will be replaced with new ones).
+ */
+#define CONFIG_USB_PD_PRL_EVENT_LOG_CAPACITY 128
+
 /* The size in bytes of the FIFO used for event logging */
 #define CONFIG_EVENT_LOG_SIZE 512
 
@@ -4069,14 +4858,20 @@
  * Some TCPCs need additional time following a VBUS change to internally
  * debounce the CC line status and updating the CC_STATUS register.
  */
-#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE	(25*MSEC)
+#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (25 * MSEC)
 
 /* Define EC and TCPC modules are in one integrated chip */
 #undef CONFIG_USB_PD_TCPC_ON_CHIP
 
+/* If VCONN is enabled, the TCPC will provide VCONN */
+#define CONFIG_USB_PD_TCPC_VCONN
+
 /* Enable the encoding of msg SOP* in bits 31-28 of 32-bit msg header type */
 #undef CONFIG_USB_PD_DECODE_SOP
 
+/* Enable to support DisplayPort mode from the EC */
+#undef CONFIG_USB_PD_DP_MODE
+
 /*
  * The USB4 specification defines compatibility support for USB4 products to
  * interact with existing Thunderbolt 3 products. Enable this config to enter
@@ -4099,6 +4894,9 @@
 /* Enable PCIE tunneling if Thunderbolt-Compatible mode is enabled*/
 #undef CONFIG_USB_PD_PCIE_TUNNELING
 
+/* Enable Power Path Control from PD */
+#undef CONFIG_USB_PD_PPC
+
 /*
  * The following two macros are ASCII text strings that matches what appears
  * in the USB-IF Product Registration form for this device. These macros are
@@ -4164,6 +4962,7 @@
 #undef CONFIG_USB_PD_TCPM_FUSB302
 #undef CONFIG_USB_PD_TCPM_ITE_ON_CHIP
 #undef CONFIG_USB_PD_TCPM_ANX3429
+#undef CONFIG_USB_PD_TCPM_ANX7406
 #undef CONFIG_USB_PD_TCPM_ANX740X
 #undef CONFIG_USB_PD_TCPM_ANX741X
 #undef CONFIG_USB_PD_TCPM_ANX7447
@@ -4173,8 +4972,10 @@
 #undef CONFIG_USB_PD_TCPM_TUSB422
 #undef CONFIG_USB_PD_TCPM_RAA489000
 #undef CONFIG_USB_PD_TCPM_RT1715
+#undef CONFIG_USB_PD_TCPM_RT1718S
 #undef CONFIG_USB_PD_TCPM_FUSB307
 #undef CONFIG_USB_PD_TCPM_STM32GX
+#undef CONFIG_USB_PD_TCPM_CCGXXF
 
 /* PS8XXX series are all supported by a single driver with a build time config
  * listed below (CONFIG_USB_PD_TCPM_PS*) defined to enable the specific product.
@@ -4186,12 +4987,24 @@
  * to provide the product id per port.
  */
 #undef CONFIG_USB_PD_TCPM_MULTI_PS8XXX
+#undef CONFIG_USB_PD_TCPM_PS8745
 #undef CONFIG_USB_PD_TCPM_PS8751
 #undef CONFIG_USB_PD_TCPM_PS8755
 #undef CONFIG_USB_PD_TCPM_PS8705
 #undef CONFIG_USB_PD_TCPM_PS8805
 #undef CONFIG_USB_PD_TCPM_PS8815
 
+/*
+ * Enable PS8751 custom mux driver. It was designed to make use of Low Power
+ * Mode on PS8751 TCPC/MUX chip when running as MUX only (CC lines are not
+ * connected, eg. Ampton).
+ *
+ * If your PS8751 is working in the ordinary way (as TCPC and MUX) or you don't
+ * need to take advantage of Low Power Mode when working as MUX only, standard
+ * TCPC MUX driver (CONFIG_USB_PD_TCPM_MUX) will work fine.
+ */
+#undef CONFIG_USB_PD_TCPM_PS8751_CUSTOM_MUX_DRIVER
+
 /*
  * Defined automatically by chip and depends on chip. This guards the onboard
  * TCPM driver, but CONFIG_USB_PD_TCPM_ITE_ON_CHIP needs to be defined in
@@ -4204,17 +5017,55 @@
 /*
  * Type-C retimer drivers to be used.
  */
+#undef CONFIG_USBC_RETIMER_ANX7483
+#undef CONFIG_USBC_RETIMER_ANX7452
 #undef CONFIG_USBC_RETIMER_INTEL_BB
+#undef CONFIG_USBC_RETIMER_KB800X
+#undef CONFIG_USBC_RETIMER_KB8010
 #undef CONFIG_USBC_RETIMER_NB7V904M
 #undef CONFIG_USBC_RETIMER_PI3DPX1207
 #undef CONFIG_USBC_RETIMER_PI3HDX1204
 #undef CONFIG_USBC_RETIMER_PS8802
+#undef CONFIG_USBC_RETIMER_PS8811
 #undef CONFIG_USBC_RETIMER_PS8818
 #undef CONFIG_USBC_RETIMER_TUSB544
 
+/*
+ * DP redriver drivers to be used.
+ */
+#undef CONFIG_DP_REDRIVER_TDP142
+
+/*
+ * Define this to enable Type-C retimer firmware update. Each Type-C retimer
+ * indicates its capability of supporting firmware update in usb_mux_driver.
+ * This feature is available to TCPMv2 PD stack, also requires
+ * CONFIG_USBC_SS_MUX is enabled.
+ * This feature includes changes in EC, Coreboot and Kernel. During AP boot
+ * up, AP scans each PD port for retimers if no Type-C device attached;
+ * and firmware update can be performed on retimers showing up in AP
+ * thunderbolt device entries. If PD port has device attached, no retimer
+ * scan on that port.
+ */
+#undef CONFIG_USBC_RETIMER_FW_UPDATE
+
+/* Prevent enabling LPM of NB7V904M */
+#undef CONFIG_NB7V904M_LPM_OVERRIDE
+
+/* Enable retimer TUSB544 tune EQ setting by register  */
+#undef CONFIG_TUSB544_EQ_BY_REGISTER
+
 /* Allow run-time configuration of the Burnside Bridge driver structure */
 #undef CONFIG_USBC_RETIMER_INTEL_BB_RUNTIME_CONFIG
 
+/* Enable vPro support for Intel Burnside Bridge on vPro supported platform */
+#undef CONFIG_USBC_RETIMER_INTEL_BB_VPRO_CAPABLE
+
+/* Require manual configuration of the KB800x crossbar mapping. */
+#undef CONFIG_KB800X_CUSTOM_XBAR
+
+/* Enables debug console commands for the STM32 UCPD driver */
+#undef CONFIG_STM32G4_UCPD_DEBUG
+
 /*
  * Adds an EC console command to erase the ANX7447 OCM flash.
  * Note: this is intended to be a temporary option and
@@ -4231,6 +5082,12 @@
  */
 #undef CONFIG_USB_PD_TCPM_ANX7447_AUX_PU_PD
 
+/*
+ * Use this to override the TCPCI Device ID value to be 0x0002 for
+ * chip rev A3. Early A3 firmware misreports the DID as 0x0001.
+ */
+#undef CONFIG_USB_PD_TCPM_PS8805_FORCE_DID
+
 /*
  * Use this to override the TCPCI Device ID value to be 0x0002 for
  * chip rev A1. Early A1 firmware misreports the DID as 0x0001.
@@ -4243,6 +5100,13 @@
  */
 #undef CONFIG_USB_PD_TCPM_MUX
 
+/*
+ * Some PD chips have integrated port protection for SBU lines.
+ * If the switches to enable those SBU lines are controlled by the PD
+ * chip, enable this config.
+ */
+#undef CONFIG_USB_PD_TCPM_SBU
+
 /*
  * The TCPM must know whether VBUS is present in order to make proper state
  * transitions. In addition, charge_manager must know about VBUS presence in
@@ -4274,6 +5138,9 @@
 /* Define if tcpc on the board supports VBUS measurement */
 #undef CONFIG_USB_PD_VBUS_MEASURE_TCPC
 
+/* Define if there is a specific method to measure Vbus voltage */
+#undef CONFIG_USB_PD_VBUS_MEASURE_BY_BOARD
+
 /* Define the type-c port controller I2C base address. */
 #define CONFIG_TCPC_I2C_BASE_ADDR_FLAGS 0x4E
 
@@ -4283,6 +5150,18 @@
 /* Set the default minimum battery percentage for Try.Src to be enabled */
 #define CONFIG_USB_PD_TRY_SRC_MIN_BATT_SOC 5
 
+/* Index for temperature sensor used in PD messages. Defaults to 0. */
+#define CONFIG_USB_PD_TEMP_SENSOR 0
+
+/*
+ * Time limit in ms for a USB PD power button press to be considered a short
+ * press
+ */
+#define CONFIG_USB_PD_SHORT_PRESS_MAX_MS 4000
+
+/* Time limit in ms for a USB PD power button press to be considered valid. */
+#define CONFIG_USB_PD_LONG_PRESS_MAX_MS 8000
+
 /*
  * Set the minimum battery percentage to allow a PD port to send resets as a
  * sink (and risk a hard reset, losing Vbus).  Note this may cause a high-power
@@ -4317,16 +5196,32 @@
 #undef CONFIG_USB_PD_FRS_PPC
 #undef CONFIG_USB_PD_FRS
 
+/*
+ * Enable USB-PD extended power range.
+ */
+#undef CONFIG_USB_PD_EPR
+
 /*
  * USB Product ID. Each platform (e.g. baseboard set) should have a single
  * VID/PID combination. If there is a big enough change within a platform,
  * then we can differentiate USB topologies by varying the HW version field
  * in the Sink and Source Capabilities Extended messages.
  *
- * To reserve a new PID, use go/usb.
+ * To reserve a new PID, use go/usb-pid.
  */
 #undef CONFIG_USB_PID
 
+/*
+ * USB Vendor ID used for USB endpoints.
+ */
+#define CONFIG_USB_VID USB_VID_GOOGLE
+
+/*
+ * Track overcurrent events for sinking partners coming from some component on
+ * the board.  Auto-enabled for drivers which contain support for this feature.
+ */
+#undef CONFIG_USBC_OCP
+
 /* PPC needs to be informed of CC polarity */
 #undef CONFIG_USBC_PPC_POLARITY
 
@@ -4339,10 +5234,20 @@
 
 /* USB Type-C Power Path Controllers (PPC) */
 #undef CONFIG_USBC_PPC_AOZ1380
+#undef CONFIG_USBC_PPC_KTU1125
 #undef CONFIG_USBC_PPC_NX20P3481
 #undef CONFIG_USBC_PPC_NX20P3483
+#undef CONFIG_USBC_PPC_RT1718S
 #undef CONFIG_USBC_PPC_SN5S330
+#undef CONFIG_USBC_PPC_SYV682C
 #undef CONFIG_USBC_PPC_SYV682X
+#undef CONFIG_USBC_PPC_TCPCI
+
+/*
+ * NX20P348x 5V SRC RCP trigger level at 10mV. Define to enable 5V SRC RCP
+ * mask for can't trigger interrupt signal.
+ */
+#undef CONFIG_USBC_NX20P348X_RCP_5VSRC_MASK_ENABLE
 
 /*
  * SYV682x PPC high voltage power path current limit.  Default limit is
@@ -4350,6 +5255,12 @@
  */
 #define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_3_30
 
+/* SYV682 does not pass through CC, instead it bypasses to the TCPC */
+#undef CONFIG_USBC_PPC_SYV682X_NO_CC
+
+/* Define to enable SYV682X VBUS smart discharge. */
+#undef CONFIG_USBC_PPC_SYV682X_SMART_DISCHARGE
+
 /* PPC is capable of gating the SBU lines. */
 #undef CONFIG_USBC_PPC_SBU
 
@@ -4359,6 +5270,9 @@
 /* PPC has level interrupts and has a dedicated interrupt pin to check */
 #undef CONFIG_USBC_PPC_DEDICATED_INT
 
+/* Enable logging related to the PPC. Undefine to reduce EC image size */
+#define CONFIG_USBC_PPC_LOGGING
+
 /* Support for USB type-c superspeed mux */
 #undef CONFIG_USBC_SS_MUX
 
@@ -4368,6 +5282,9 @@
  */
 #undef CONFIG_USBC_SS_MUX_DFP_ONLY
 
+/* Only configure USB type-c superspeed mux when UFP */
+#undef CONFIG_USBC_SS_MUX_UFP_ONLY
+
 /* Support v1.1 type-C connection state machine */
 #undef CONFIG_USBC_BACKWARDS_COMPATIBLE_DFP
 
@@ -4377,12 +5294,26 @@
 /* Support VCONN swap */
 #undef CONFIG_USBC_VCONN_SWAP
 
+/*
+ * The amount of time in microseconds that the board takes to turn VCONN on or
+ * off after being directed to do so. Typically a property of the PPC. Default
+ * to 5 ms.
+ */
+#define CONFIG_USBC_VCONN_SWAP_DELAY_US 5000
+
 /* USB Binary device Object Store support */
 #undef CONFIG_USB_BOS
 
 /* USB Device version of product */
 #undef CONFIG_USB_BCD_DEV
 
+/*
+ * Intel Reference Validation Platform's (RVP) Modular Embedded Control
+ * Card (MECC) versions
+ */
+#undef CONFIG_INTEL_RVP_MECC_VERSION_1_0
+#undef CONFIG_INTEL_RVP_MECC_VERSION_1_1
+
 /*****************************************************************************/
 
 /* Compile chip support for the USB device controller */
@@ -4394,6 +5325,9 @@
 /* Common USB / BC1.2 charger detection routines */
 #undef CONFIG_USB_CHARGER
 
+/* Only allow PI3USB9201 to advertise itself as BC1.2 client */
+#undef CONFIG_BC12_CLIENT_MODE_ONLY_PI3USB9201
+
 /*
  * Used for bc1.2 chips that need to be triggered from data role swaps instead
  * of just VBUS changes.
@@ -4414,9 +5348,11 @@
 #undef CONFIG_BC12_DETECT_MT6360
 #undef CONFIG_BC12_DETECT_PI3USB9201
 #undef CONFIG_BC12_DETECT_PI3USB9281
+#undef CONFIG_BC12_DETECT_RT1718S
 /* Number of Pericom PI3USB9281 chips present in system */
 #undef CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT
-
+/* The delay in ms from power off to power on for MAX14637 */
+#define CONFIG_BC12_MAX14637_DELAY_FROM_OFF_TO_ON_MS 1
 
 /* Enable USB serial console module. */
 #undef CONFIG_USB_CONSOLE
@@ -4446,6 +5382,15 @@
 /* Support USB HID keyboard backlight. */
 #undef CONFIG_USB_HID_KEYBOARD_BACKLIGHT
 
+/*
+ * Support vivaldi compatible HID keyboard.
+ * If defined, the board must implement a function board_vivaldi_keybd_config(),
+ * and define a macro CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS which is equal to
+ * board_vivaldi_keybd_config()->num_top_row_keys.
+ */
+#undef CONFIG_USB_HID_KEYBOARD_VIVALDI
+#undef CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS
+
 /* Support USB HID touchpad interface. */
 #undef CONFIG_USB_HID_TOUCHPAD
 
@@ -4472,6 +5417,12 @@
 /* Support simple control of power to the device's USB ports */
 #undef CONFIG_USB_PORT_POWER_DUMB
 
+/*
+ * Let board customize the timing to enable/disable usb port, instead
+ * of using the default S3 hook.
+ */
+#undef CONFIG_USB_PORT_POWER_DUMB_CUSTOM_HOOK
+
 /*
  * Support smart power control to the device's USB ports, using
  * dedicated power control chips.  This potentially enables automatic
@@ -4524,12 +5475,22 @@
 /* Support reporting of configuration bMaxPower in mA */
 #define CONFIG_USB_MAXPOWER_MA 500
 
+#ifndef CONFIG_ZEPHYR
 /* Support reporting as self powered in USB configuration. */
 #undef CONFIG_USB_SELF_POWERED
+#endif /* CONFIG_ZEPHYR */
 
 /* Support correct handling of USB suspend (host-initiated). */
 #undef CONFIG_USB_SUSPEND
 
+/*
+ * Enable this config for a USB-EP device that needs to interop properly with a
+ * MS Windows OS host machine. This config will enable a special string
+ * descriptor so Windows OS will know to retreieve an Extended Compat ID OS
+ * Feature descriptor.
+ */
+#undef CONFIG_USB_MS_EXTENDED_COMPAT_ID_DESCRIPTOR
+
 /* Default pull-up value on the USB-C ports when they are used as source. */
 #define CONFIG_USB_PD_PULLUP TYPEC_RP_1A5
 /*
@@ -4540,6 +5501,12 @@
  */
 #undef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
 
+/*
+ * Ignore all non-fixed PDOs received from a src_caps message. Enable this for
+ * boards (like servo_v4) which only support FIXED PDO types.
+ */
+#undef CONFIG_USB_PD_ONLY_FIXED_PDOS
+
 /*
  * Total current in mA the board can supply to external devices through
  * USB-C ports
@@ -4562,15 +5529,33 @@
 /* Allow run-time completion of the usb mux driver structure */
 #undef CONFIG_USB_MUX_RUNTIME_CONFIG
 
+/* Allow the AP to send commands for mux control */
+#undef CONFIG_USB_MUX_AP_CONTROL
+
 /* Support the AMD FP5 USB/DP Mux */
 #undef CONFIG_USB_MUX_AMD_FP5
 
+/* Support the AMD FP6 USB/DP Mux */
+#undef CONFIG_USB_MUX_AMD_FP6
+
+/*
+ * Support the Analogix ANX3443 USB Type-C Active mux (6x4) with
+ * Integrated Re-timers for USB3.2/DisplayPort.
+ */
+#undef CONFIG_USB_MUX_ANX3443
+
 /*
  * Support the Analogix ANX7440 USB Type-C Active mux with
  * Integrated Re-timers for USB3.1/DisplayPort.
  */
 #undef CONFIG_USB_MUX_ANX7440
 
+/*
+ * Support the Analogix ANX7451 10G Active Mux (4x4) with
+ * Integrated Re-timers for USB3.2/DisplayPort
+ */
+#undef CONFIG_USB_MUX_ANX7451
+
 /* Support the ITE IT5205 Type-C USB alternate mode mux. */
 #undef CONFIG_USB_MUX_IT5205
 
@@ -4589,12 +5574,34 @@
 /* Support the Parade PS8743 Type-C Redriving Switch */
 #undef CONFIG_USB_MUX_PS8743
 
+/* Config to enable TUSB1044 Type-c USB redriver */
+#undef CONFIG_USB_MUX_TUSB1044
+
+/* Support the Texas Instrument TUSB1064 Type-C Redriving Switch (UFP) */
+#undef CONFIG_USB_MUX_TUSB1064
+
+/*
+ * Support TI TUSB546 USB Type-C DP ALT Mode Linear Redriver Crosspoint
+ * Switch
+ */
+#undef CONFIG_USB_MUX_TUSB546
+
+/* Support the Parade PS8822 Type-C Redriving Demux Switch */
+#undef CONFIG_USB_MUX_PS8822
+
 /* 'Virtual' USB mux under host (not EC) control */
 #undef CONFIG_USB_MUX_VIRTUAL
 
 /* Enable IT5205H SBU protection switch */
 #undef CONFIG_USB_MUX_IT5205H_SBU_OVP
 
+/*
+ * Enable to inform the AP that an ACK is needed on configuring the TCSS mux.
+ * The config is enabled automatically when the board has CONFIG_USB_MUX_VIRTUAL
+ * and CONFIG_USBC_RETIMER_INTEL_BB enabled.
+ */
+#undef CONFIG_USB_MUX_AP_ACK_REQUEST
+
 /*****************************************************************************/
 /* USB GPIO config */
 #undef CONFIG_USB_GPIO
@@ -4603,6 +5610,14 @@
 /* USB SPI config */
 #undef CONFIG_USB_SPI
 
+/*
+ * Use when you want the SPI subsystem to be enabled even when the USB SPI
+ * endpoint is not enabled by the host. This means that when this firmware
+ * enables SPI, then the HW SPI module is enabled (i.e. SPE bit is set) until
+ * this firmware disables the SPI module; it ignores the host's enables state.
+ */
+#undef CONFIG_USB_SPI_IGNORE_HOST_SIDE_ENABLE
+
 /*****************************************************************************/
 /* USB I2C config */
 #undef CONFIG_USB_I2C
@@ -4623,7 +5638,6 @@
  */
 #undef CONFIG_STREAM_SIGNATURE
 
-
 /*****************************************************************************/
 
 /*
@@ -4664,7 +5678,9 @@
  * if the hook task (which is the lowest-priority task on the system) gets
  * starved for CPU time and isn't able to fire its HOOK_TICK event.
  */
+#ifndef CONFIG_ZEPHYR
 #define CONFIG_WATCHDOG
+#endif
 
 /*
  * Try to detect a watchdog that is about to fire, and print a trace.  This is
@@ -4683,11 +5699,15 @@
 /* Watchdog period in ms; see also AUX_TIMER_PERIOD_MS */
 #define CONFIG_WATCHDOG_PERIOD_MS 1600
 
+/* The leading time of watchdog warning timer. */
+#define CONFIG_WATCHDOG_WARNING_LEADING_TIME_MS 500
+
 /*
- * Fire auxiliary timer 500ms before watchdog timer expires. This leaves
- * some time for debug trace to be printed.
+ * Fire auxiliary timer before watchdog timer expires. This leaves some time for
+ * debug trace to be printed.
  */
-#define CONFIG_AUX_TIMER_PERIOD_MS (CONFIG_WATCHDOG_PERIOD_MS - 500)
+#define CONFIG_AUX_TIMER_PERIOD_MS \
+	(CONFIG_WATCHDOG_PERIOD_MS - CONFIG_WATCHDOG_WARNING_LEADING_TIME_MS)
 
 /*****************************************************************************/
 /* WebUSB config */
@@ -4730,13 +5750,6 @@
  */
 #undef CONFIG_WP_ALWAYS
 
-/*
- * If needed to allocate some free space in the base of the RO or RW section
- * of the image, define these to be equal the required size of the free space.
- */
-#define CONFIG_RO_HEAD_ROOM 0
-#define CONFIG_RW_HEAD_ROOM 0
-
 /* Firmware upgrade options. */
 /* A different config for the same update. TODO(vbendeb): dedupe these */
 #undef CONFIG_USB_UPDATE
@@ -4750,6 +5763,30 @@
 /* PDU size for fw update over USB (or TPM). */
 #define CONFIG_UPDATE_PDU_SIZE 1024
 
+/* DFU firmware upgrade options */
+/*
+ * Enables DFU USB Runtime identifier.
+ */
+#undef CONFIG_DFU_RUNTIME
+
+/*
+ * Indicates this region is a DFU Boot Manager and is a minimal runtime.
+ */
+#undef CONFIG_DFU_BOOTMANAGER_MAIN
+/*
+ * Enables DFU Boot Manager reboot loop protection. When unexpected reboots
+ * occur, a counter is incremented which will enter DFU once it exceeds
+ * the value defined. This parameter should only be enabled on setups which
+ * can issue the command to exit DFU.
+ */
+#undef CONFIG_DFU_BOOTMANAGER_MAX_REBOOT_COUNT
+
+/*
+ * Enables access to shared utilities required for the application
+ * and DFU Boot Manager. This allows the application to enter DFU.
+ */
+#undef CONFIG_DFU_BOOTMANAGER_SHARED
+
 /*
  * If defined, charge_get_state returns a special status if battery is
  * discharging and battery is nearly full.
@@ -4763,10 +5800,26 @@
 #undef CONFIG_EXTENDED_VERSION_INFO
 
 /*
- * Define this to enable Cros Board Info support. I2C_EEPROM_PORT and
- * I2C_EEPROM_ADDR must be defined as well.
+ * Include CROS_FWID in version output.
+ */
+#define CONFIG_CROS_FWID_VERSION
+
+/*
+ * Define this to support Cros Board Info from EEPROM. I2C_PORT_EEPROM
+ * and I2C_ADDR_EEPROM_FLAGS must be defined as well.
+ */
+#undef CONFIG_CBI_EEPROM
+
+/*
+ * Define this if the EC has exclusive control over the CBI EEPROM WP signal.
+ * The accompanying hardware must ensure that the CBI WP gets latched and is
+ * only reset when EC_RST_ODL is asserted.  GPIO_EC_CBI_WP must be set up for
+ * the board.
  */
-#undef CONFIG_CROS_BOARD_INFO
+#undef CONFIG_EEPROM_CBI_WP
+
+/* Define this to support Cros Board Info from GPIO. */
+#undef CONFIG_CBI_GPIO
 
 /*****************************************************************************/
 /*
@@ -4826,23 +5879,13 @@
  */
 #undef CONFIG_ISH_DW_UART
 
-/*
- * On Intel devices EC's USB-C port numbers may not be physically equal to
- * AP's USB3 & USB2 port number. Because there can be MAX 15 USB2 ports on
- * PCH and MAX 15 USB3 ports on SOC, based on the complexity of the physical
- * layout of the board, USB3 & USB2 port signals of AP are routed to respective
- * USB-C port of EC. Hence, to configure the Intel Virtual MUX, information of
- * USB3 and USB2 port numbers of the respective USB-C port is needed.
- */
-#undef CONFIG_INTEL_VIRTUAL_MUX
-
 /*
  * TEST ONLY defines (CONFIG_TEST_*)
  *
  * Used to include files for unit and other builds tests.
  */
 
- /* Define to enable Policy Engine State Machine. */
+/* Define to enable Policy Engine State Machine. */
 #undef CONFIG_TEST_USB_PE_SM
 
 /* Define to enable USB State Machine framework. */
@@ -4851,8 +5894,41 @@
 /*
  * This build is not a complete platform/ec based EC, but instead
  * using the platform/ec zephyr module.
+ *
+ * Note: this is here purely for stylistic purposes and documentation.
  */
+#ifndef CONFIG_ZEPHYR
 #undef CONFIG_ZEPHYR
+#endif
+
+/*
+ * Define the following to drive CCD_MODE_ODL when a DTS accessory is
+ * connected to the CCD USBC port.
+ *
+ * GPIO_CCD_MODE_ODL should be configured with GPIO_ODR_HIGH flag
+ */
+#undef CONFIG_ASSERT_CCD_MODE_ON_DTS_CONNECT
+
+#ifndef CONFIG_ZEPHYR
+/* Define this to enable system boot time logging */
+#undef CONFIG_SYSTEM_BOOT_TIME_LOGGING
+#endif /* CONFIG_ZEPHYR */
+
+/*
+ * The USB port used for CCD. Defaults to 0/C0.
+ */
+#define CONFIG_CCD_USBC_PORT_NUMBER 0
+
+/*
+ * The historical default SCI pulse width to the host is 65 microseconds, but
+ * some chipsets may require different widths.
+ */
+#define CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US 65
+
+/*
+ * Build and link *test* images with googletest.
+ */
+#undef CONFIG_GOOGLETEST
 
 /*****************************************************************************/
 /*
@@ -4872,18 +5948,40 @@
 #endif
 
 #include "config_chip.h"
+#ifdef CONFIG_ZEPHYR
+#include "zephyr_shim.h"
+#else
 #include "board.h"
+#endif
 
 /*
  * Define CONFIG_HOST_ESPI_VW_POWER_SIGNAL if any power signals from the host
  * are configured as virtual wires.
  */
-#if defined(CONFIG_HOSTCMD_ESPI_VW_SLP_S3) || \
-	defined(CONFIG_HOSTCMD_ESPI_VW_SLP_S4)
+#if defined(CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3) ||     \
+	defined(CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4) || \
+	defined(CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S5)
 #define CONFIG_HOST_ESPI_VW_POWER_SIGNAL
 #endif
 
-#if defined(CONFIG_HOST_ESPI_VW_POWER_SIGNAL) && !defined(CONFIG_HOSTCMD_ESPI)
+/*
+ * S4 residency works by observing SLP_S5 via virtual wire (as SLP_S5 has not
+ * traditionally been routed to the EC). If the board family wants S4 residency,
+ * they need to use ECs that support eSPI. Note that S4 residency is not
+ * strictly a requirement to support suspend-to-disk, except on Intel platforms
+ * with Key Locker support (TGL+).
+ */
+#if defined(CONFIG_POWER_S4_RESIDENCY) && \
+	!defined(CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S5)
+#error "S4_RESIDENCY needs eSPI support or SLP_S5 routed"
+#endif
+
+/*
+ * Note that in Zephyr OS, eSPI can be enabled for virtual wires
+ * without using eSPI for host commands.
+ */
+#if (!defined(CONFIG_ZEPHYR) && defined(CONFIG_HOST_ESPI_VW_POWER_SIGNAL) && \
+     !defined(CONFIG_HOST_INTERFACE_ESPI))
 #error Must enable eSPI to enable virtual wires.
 #endif
 
@@ -4914,11 +6012,31 @@
 #if !defined(CONFIG_USBC_SS_MUX)
 #error CONFIG_USBC_SS_MUX must be enabled for USB4 mode support
 #endif
-# if !defined(CONFIG_USB_PD_ALT_MODE_DFP)
+#if !defined(CONFIG_USB_PD_ALT_MODE_DFP)
 #error CONFIG_USB_PD_ALT_MODE_DFP must be enabled for USB4 mode support
 #endif
 #endif
 
+/******************************************************************************/
+/*
+ * If CONFIG_USB_PD_ALT_MODE_DFP is set and this isn't a zephyr build (which
+ * already did its preprocessing earlier), then enable DP Mode by default and
+ * also enable discovery by default.
+ */
+#if defined(CONFIG_USB_PD_ALT_MODE_DFP) && !defined(CONFIG_ZEPHYR)
+#define CONFIG_USB_PD_DP_MODE
+#define CONFIG_USB_PD_DISCOVERY
+#endif
+
+/******************************************************************************/
+/*
+ * If CONFIG_USBC_SS_MUX_DFP_ONLY is enabled, make sure
+ * CONFIG_USB_PD_ALT_MODE_UFP is not enabled
+ */
+#if defined(CONFIG_USBC_SS_MUX_DFP_ONLY) && defined(CONFIG_USB_PD_ALT_MODE_UFP)
+#error port cannot be UFP when CONFIG_USBC_SS_MUX_DFP_ONLY is enabled
+#endif
+
 /******************************************************************************/
 /*
  * Automatically define CONFIG_USB_PD_FRS if FRS is enabled in the TCPC or PPC
@@ -4939,6 +6057,7 @@
  * PD 2.0 retires three times (for a total of 4 attempts).
  *
  * Note must be [0-3] since it must fit within 2 bits.
+ * TODO(b/175236718): Set retry count dynamically based on active spec revision.
  */
 #ifdef CONFIG_USB_PD_REV30
 #define CONFIG_PD_RETRY_COUNT 2
@@ -4951,29 +6070,62 @@
  * Ensure that CONFIG_USB_PD_TCPMV2 is being used with exactly one device type
  */
 #ifdef CONFIG_USB_PD_TCPMV2
-#if defined(CONFIG_USB_VPD) + \
-	defined(CONFIG_USB_CTVPD) + \
-	defined(CONFIG_USB_DRP_ACC_TRYSRC) != 1
+#if defined(CONFIG_USB_VPD) + defined(CONFIG_USB_CTVPD) + \
+		defined(CONFIG_USB_DRP_ACC_TRYSRC) !=     \
+	1
 #error Must define exactly one CONFIG_USB_ device type.
 #endif
 #endif
 
+/******************************************************************************/
+/*
+ * Ensure that CONFIG_USB_PD_TCPMV2 is not being used with charge_manager source
+ * defines, and define a default number of 3.0 A ports if not selected.  Note
+ * that the functionality of this default of 1 is equivalent to both previous
+ * defines, which only ever allocated one 3.0 A port.
+ *
+ * To turn off the TCPMv2 3.0 A current allocation from the DPM, set
+ * CONFIG_USB_PD_3A_PORTS to 0.
+ */
+#ifdef CONFIG_USB_PD_TCPMV2
+#if defined(CONFIG_USB_PD_MAX_TOTAL_SOURCE_CURRENT) || \
+	defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT)
+#error Define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT is limited to TCPMv1
+#endif
+#ifndef CONFIG_USB_PD_3A_PORTS
+#define CONFIG_USB_PD_3A_PORTS 1
+#endif
+/* USB4 support requires at least one port providing 3.0 A */
+#if defined(CONFIG_USB_PD_USB4) && CONFIG_USB_PD_3A_PORTS == 0
+#error USB4 support requires at least one 3.0 A port
+#endif
+#endif
+
+/******************************************************************************/
+/*
+ * Ensure CONFIG_USB_PD_TCPMV2 and CONFIG_USBC_SS_MUX both are defined. USBC
+ * retimer firmware update feature requires both.
+ */
+#if (defined(CONFIG_USBC_RETIMER_FW_UPDATE) && \
+     (!(defined(CONFIG_USB_PD_TCPMV2) && defined(CONFIG_USBC_SS_MUX))))
+#error Retimer firmware update requires TCPMv2 and USBC_SS_MUX
+#endif
+
 /******************************************************************************/
 /*
  * Automatically define CONFIG_HOSTCMD_X86 if either child option is defined.
  * Ensure LPC and eSPI are mutually exclusive
  */
-#if defined(CONFIG_HOSTCMD_LPC) || defined(CONFIG_HOSTCMD_ESPI)
+#if defined(CONFIG_HOST_INTERFACE_LPC) || defined(CONFIG_HOST_INTERFACE_ESPI)
 #define CONFIG_HOSTCMD_X86
 #endif
 
-#if defined(CONFIG_HOSTCMD_LPC) && defined(CONFIG_HOSTCMD_ESPI)
+#if defined(CONFIG_HOST_INTERFACE_LPC) && defined(CONFIG_HOST_INTERFACE_ESPI)
 #error Must select only one type of host communication bus.
 #endif
 
-#if defined(CONFIG_HOSTCMD_X86) && \
-	!defined(CONFIG_HOSTCMD_LPC) && \
-	!defined(CONFIG_HOSTCMD_ESPI)
+#if defined(CONFIG_HOSTCMD_X86) && !defined(CONFIG_HOST_INTERFACE_LPC) && \
+	!defined(CONFIG_HOST_INTERFACE_ESPI)
 #error Must select one type of host communication bus.
 #endif
 
@@ -4996,11 +6148,11 @@
 /* Automatic configuration of RAM banks **************************************/
 /* Assume one RAM bank if not specified, auto-compute number of banks        */
 #ifndef CONFIG_RAM_BANK_SIZE
-#define CONFIG_RAM_BANK_SIZE	CONFIG_RAM_SIZE
+#define CONFIG_RAM_BANK_SIZE CONFIG_RAM_SIZE
 #endif
 
 #ifndef CONFIG_RAM_BANKS
-#define CONFIG_RAM_BANKS	(CONFIG_RAM_SIZE / CONFIG_RAM_BANK_SIZE)
+#define CONFIG_RAM_BANKS (CONFIG_RAM_SIZE / CONFIG_RAM_BANK_SIZE)
 #endif
 
 /******************************************************************************/
@@ -5011,13 +6163,12 @@
  * the beginning of RAM.
  */
 #ifndef CONFIG_PANIC_DATA_SIZE
-#define CONFIG_PANIC_DATA_SIZE	sizeof(struct panic_data)
+#define CONFIG_PANIC_DATA_SIZE sizeof(struct panic_data)
 #endif
 
 #ifndef CONFIG_PANIC_DATA_BASE
-#define CONFIG_PANIC_DATA_BASE (CONFIG_RAM_BASE			\
-				+ CONFIG_RAM_SIZE			\
-				- CONFIG_PANIC_DATA_SIZE)
+#define CONFIG_PANIC_DATA_BASE \
+	(CONFIG_RAM_BASE + CONFIG_RAM_SIZE - CONFIG_PANIC_DATA_SIZE)
 #endif
 
 /******************************************************************************/
@@ -5049,7 +6200,6 @@
 #endif
 #endif /* !CONFIG_SHAREDMEM_MINIMUM_SIZE */
 
-
 /******************************************************************************/
 /*
  * Disable the built-in console history if using the experimental console.
@@ -5062,19 +6212,6 @@
 #define CONFIG_CRC8
 #endif /* defined(CONFIG_EXPERIMENTAL_CONSOLE) */
 
-
-/******************************************************************************/
-/*
- * Automatically define common CONFIG_BOARD_VERSION if any specific option is
- * used.
- */
-
-#if defined(CONFIG_BOARD_VERSION_CBI) || \
-	defined(CONFIG_BOARD_VERSION_CUSTOM) || \
-	defined(CONFIG_BOARD_VERSION_GPIO)
-#define CONFIG_BOARD_VERSION
-#endif
-
 /******************************************************************************/
 /*
  * Thermal throttling AP must have temperature sensor enabled to get
@@ -5093,28 +6230,31 @@
 #define CONFIG_TEMP_SENSOR
 #endif
 
-
 /******************************************************************************/
-/* The Matrix Keyboard Protocol depends on MKBP events. */
+/* The Matrix Keyboard Protocol depends on MKBP input devices and events. */
 #ifdef CONFIG_KEYBOARD_PROTOCOL_MKBP
+#define CONFIG_MKBP_INPUT_DEVICES
+#endif
+
+#if defined(CONFIG_KEYBOARD_PROTOCOL_MKBP) || defined(CONFIG_MKBP_INPUT_DEVICES)
 #define CONFIG_MKBP_EVENT
 #endif
 
 /******************************************************************************/
 /* MKBP events delivery methods. */
 #ifdef CONFIG_MKBP_EVENT
-#if !defined(CONFIG_MKBP_USE_CUSTOM) && \
-	!defined(CONFIG_MKBP_USE_HOST_EVENT) && \
-	!defined(CONFIG_MKBP_USE_GPIO) && \
+#if !defined(CONFIG_MKBP_USE_CUSTOM) &&                  \
+	!defined(CONFIG_MKBP_USE_HOST_EVENT) &&          \
+	!defined(CONFIG_MKBP_USE_GPIO) &&                \
 	!defined(CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT) && \
 	!defined(CONFIG_MKBP_USE_HECI)
 #error Please define one of CONFIG_MKBP_USE_* macro.
 #endif
 
-#if defined(CONFIG_MKBP_USE_CUSTOM) + \
-	defined(CONFIG_MKBP_USE_GPIO) + \
-	defined(CONFIG_MKBP_USE_HOST_EVENT) + \
-	defined(CONFIG_MKBP_USE_HOST_HECI) > 1
+#if defined(CONFIG_MKBP_USE_CUSTOM) + defined(CONFIG_MKBP_USE_GPIO) + \
+		defined(CONFIG_MKBP_USE_HOST_EVENT) +                 \
+		defined(CONFIG_MKBP_USE_HOST_HECI) >                  \
+	1
 #error Must select only one type of MKBP event delivery method.
 #endif
 #endif /* CONFIG_MKBP_EVENT */
@@ -5131,24 +6271,26 @@
 
 /*****************************************************************************/
 /* Define CONFIG_BATTERY if board has a battery. */
-#if defined(CONFIG_BATTERY_BQ20Z453) || \
-	defined(CONFIG_BATTERY_BQ27541) || \
-	defined(CONFIG_BATTERY_BQ27621) || \
-	defined(CONFIG_BATTERY_BQ4050) || \
-	defined(CONFIG_BATTERY_MAX17055) || \
-	defined(CONFIG_BATTERY_MM8013) || \
+#if defined(CONFIG_BATTERY_BQ20Z453) || defined(CONFIG_BATTERY_BQ27541) ||    \
+	defined(CONFIG_BATTERY_BQ27621) || defined(CONFIG_BATTERY_BQ4050) ||  \
+	defined(CONFIG_BATTERY_MAX17055) || defined(CONFIG_BATTERY_MM8013) || \
 	defined(CONFIG_BATTERY_SMART)
 #define CONFIG_BATTERY
 #endif
 
 /*****************************************************************************/
 /* Define CONFIG_USBC_PPC if board has a USB Type-C Power Path Controller. */
-#if defined(CONFIG_USBC_PPC_AOZ1380) || \
-	defined(CONFIG_USBC_PPC_NX20P3483) || \
-	defined(CONFIG_USBC_PPC_SN5S330)
+#if defined(CONFIG_USBC_PPC_AOZ1380) || defined(CONFIG_USBC_PPC_NX20P3483) || \
+	defined(CONFIG_USBC_PPC_SN5S330) || defined(CONFIG_USBC_PPC_TCPCI)
 #define CONFIG_USBC_PPC
 #endif /* "has a PPC" */
 
+/* Following chips use Power Path Control information from TCPC chip */
+#if defined(CONFIG_USBC_PPC_AOZ1380) || defined(CONFIG_USBC_PPC_NX20P3481) || \
+	defined(CONFIG_USBC_PPC_NX20P3483) || defined(CONFIG_USBC_PPC_TCPCI)
+#define CONFIG_USB_PD_PPC
+#endif
+
 /* The TI SN5S330 supports VCONN and needs to be informed of CC polarity */
 #if defined(CONFIG_USBC_PPC_SN5S330)
 #define CONFIG_USBC_PPC_POLARITY
@@ -5156,32 +6298,81 @@
 #define CONFIG_USBC_PPC_VCONN
 #endif
 
-/* The SYV682X supports VCONN and needs to be informed of CC polarity */
+/*****************************************************************************/
+/* PPC SYV682C is a subset of SYV682X. */
+#if defined(CONFIG_USBC_PPC_SYV682C)
+#define CONFIG_USBC_PPC_SYV682X
+#endif
+
+/*
+ * The SYV682X supports VCONN and needs to be informed of CC polarity.
+ * There is a 3.6V limit on the HOST_CC signals, so the TCPC should not source
+ * 5V VCONN.
+ *
+ * For the ITE integrated TCPC, it wants to be notified of VCONN but won't
+ * source VCONN itself, so is safe to keep enabled.
+ */
 #if defined(CONFIG_USBC_PPC_SYV682X)
 #define CONFIG_USBC_PPC_POLARITY
 #define CONFIG_USBC_PPC_VCONN
+#if !defined(CONFIG_USB_PD_TCPM_ITE_ON_CHIP) && \
+	!defined(CONFIG_USBC_PPC_SYV682X_NO_CC)
+#undef CONFIG_USB_PD_TCPC_VCONN
+#endif
+#endif
+
+/* CCGXXF standard default defines */
+#if defined(CONFIG_USB_PD_TCPM_CCGXXF)
+#define CONFIG_USB_PD_DISCHARGE_TCPC
+#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+#define CONFIG_USB_PD_PPC
+#define CONFIG_USB_PD_TCPM_SBU
+#define CONFIG_USB_PD_TCPC_LOW_POWER
+#define CONFIG_USB_PD_TCPM_TCPCI
+#define CONFIG_USB_PD_VBUS_DETECT_TCPC
+#endif
+
+/*****************************************************************************/
+/* Define CONFIG_USBC_OCP if a component can detect overcurrent */
+#if defined(CONFIG_USBC_PPC_AOZ1380) || defined(CONFIG_USBC_PPC_KTU1125) ||   \
+	defined(CONFIG_USBC_PPC_NX20P3481) ||                                 \
+	defined(CONFIG_USBC_PPC_NX20P3483) ||                                 \
+	defined(CONFIG_USBC_PPC_SN5S330) ||                                   \
+	defined(CONFIG_USBC_PPC_SYV682X) || defined(CONFIG_CHARGER_SM5803) || \
+	defined(CONFIG_USB_PD_TCPM_TCPCI) ||                                  \
+	defined(CONFIG_USB_PD_TCPM_ANX7406)
+#define CONFIG_USBC_OCP
 #endif
 
+#ifndef CONFIG_ZEPHYR
 /*****************************************************************************/
 /*
  * Define CONFIG_USB_PD_VBUS_MEASURE_CHARGER if the charger on the board
  * supports VBUS measurement.
  */
-#if defined(CONFIG_CHARGER_BD9995X) || \
-	defined(CONFIG_CHARGER_RT9466) || \
-	defined(CONFIG_CHARGER_RT9467) || \
-	defined(CONFIG_CHARGER_MT6370) || \
-	defined(CONFIG_CHARGER_BQ25710) || \
-	defined(CONFIG_CHARGER_ISL9241)
+#if defined(CONFIG_CHARGER_BD9995X) || defined(CONFIG_CHARGER_RT9466) ||      \
+	defined(CONFIG_CHARGER_RT9467) || defined(CONFIG_CHARGER_RT9490) ||   \
+	defined(CONFIG_CHARGER_MT6370) || defined(CONFIG_CHARGER_BQ25710) ||  \
+	defined(CONFIG_CHARGER_BQ25720) || defined(CONFIG_CHARGER_ISL9241) || \
+	defined(CONFIG_CHARGER_RAA489110)
+#if !defined(CONFIG_USB_PD_VBUS_MEASURE_TCPC) &&              \
+	!defined(CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT) && \
+	!defined(CONFIG_USB_PD_VBUS_MEASURE_BY_BOARD)
 #define CONFIG_USB_PD_VBUS_MEASURE_CHARGER
-#endif
+#endif /* VBUS_MEASURE options */
 
+#ifdef CONFIG_USB_PD_VBUS_MEASURE_NOT_PRESENT
+#error CONFIG_USB_PD_VBUS_MEASURE_NOT_PRESENT defined, but charger can measure
+#endif /* VBUS_NOT_PRESENT */
+#endif /* Charger chips */
+#endif /* CONFIG_ZEPHYR */
 /*****************************************************************************/
 /*
  * Define CONFIG_USB_PD_VBUS_MEASURE_TCPC if the tcpc on the board supports
  * VBUS measurement.
  */
-#if defined(CONFIG_USB_PD_TCPM_FUSB302)
+#if defined(CONFIG_USB_PD_TCPM_FUSB302) && \
+	!defined(CONFIG_USB_PD_VBUS_MEASURE_CHARGER)
 #define CONFIG_USB_PD_VBUS_MEASURE_TCPC
 #endif
 
@@ -5189,9 +6380,17 @@
 /*
  * Define CONFIG_USB_PD_TCPC_ON_CHIP if we use ITE series TCPM driver
  * on the board.
+ *
+ * NOTE: If we don't use all the ITE pd ports on a board, then we need to
+ *       start from port0 to use the ITE pd port. If we start from port1,
+ *       then port1 HOOK function never works.
  */
 #ifdef CONFIG_USB_PD_TCPM_ITE_ON_CHIP
 #define CONFIG_USB_PD_TCPC_ON_CHIP
+#if !defined(CONFIG_USB_PD_TCPM_DRIVER_IT8XXX2) && \
+	!defined(CONFIG_USB_PD_TCPM_DRIVER_IT83XX)
+#error "No drivers for ITE ON CHIP"
+#endif
 #endif
 
 /*****************************************************************************/
@@ -5199,9 +6398,11 @@
  * Define CONFIG_CHARGER_NARROW_VDC for chargers that use a Narrow VDC power
  * architecture.
  */
-#if defined(CONFIG_CHARGER_ISL9237) || defined(CONFIG_CHARGER_ISL9238) || \
+#if defined(CONFIG_CHARGER_ISL9237) || defined(CONFIG_CHARGER_ISL9238) ||      \
 	defined(CONFIG_CHARGER_ISL9238C) || defined(CONFIG_CHARGER_ISL9241) || \
-	defined(CONFIG_CHARGER_RAA489000) || defined(CONFIG_CHARGER_SM5803)
+	defined(CONFIG_CHARGER_RAA489000) || defined(CONFIG_CHARGER_SM5803) || \
+	defined(CONFIG_CHARGER_BQ25710) || defined(CONFIG_CHARGER_BQ25720) ||  \
+	defined(CONFIG_CHARGER_RAA489110)
 #define CONFIG_CHARGER_NARROW_VDC
 #endif
 
@@ -5214,10 +6415,11 @@
 #define CONFIG_BUTTON_TRIGGERED_RECOVERY
 #endif /* defined(CONFIG_DEDICATED_RECOVERY_BUTTON) */
 
-
+#ifndef CONFIG_ZEPHYR
 #ifdef CONFIG_LED_PWM_COUNT
 #define CONFIG_LED_PWM
 #endif /* defined(CONFIG_LED_PWM_COUNT) */
+#endif /* CONFIG_ZEPHYR */
 
 #ifdef CONFIG_LED_PWM_ACTIVE_CHARGE_PORT_ONLY
 #define CONFIG_LED_PWM_CHARGE_STATE_ONLY
@@ -5228,22 +6430,55 @@
  * Define derived configuration options for EC-EC communication
  */
 #ifdef CONFIG_EC_EC_COMM_BATTERY
-#ifdef CONFIG_EC_EC_COMM_MASTER
-#define CONFIG_EC_EC_COMM_BATTERY_MASTER
+#ifdef CONFIG_EC_EC_COMM_CLIENT
+#define CONFIG_EC_EC_COMM_BATTERY_CLIENT
 #define CONFIG_BATTERY_V2
 #define CONFIG_BATTERY_COUNT 2
 #endif
 
-#ifdef CONFIG_EC_EC_COMM_SLAVE
-#define CONFIG_EC_EC_COMM_BATTERY_SLAVE
+#ifdef CONFIG_EC_EC_COMM_SERVER
+#define CONFIG_EC_EC_COMM_BATTERY_SERVER
 #define CONFIG_BATTERY_V2
 #define CONFIG_BATTERY_COUNT 1
 #endif
 #endif /* CONFIG_EC_EC_COMM_BATTERY */
 
+/*****************************************************************************/
+/* If battery_v2 isn't used, it's v1. */
+#if defined(CONFIG_BATTERY) && !defined(CONFIG_BATTERY_V2)
+#define CONFIG_BATTERY_V1
+#endif
+
+/*
+ * Check the specific battery status to judge whether the battery is
+ * initialized and stable when the battery wakes up from ship mode.
+ * Use two MASKs to provide logical AND and logical OR options for different
+ * status. For example:
+ *
+ * Logical OR -- just check one of TCA/TDA mask:
+ *   #define CONFIG_BATT_ALARM_MASK1 \
+ *       (STATUS_TERMINATE_CHARGE_ALARM | STATUS_TERMINATE_DISCHARGE_ALARM)
+ *   #define CONFIG_BATT_ALARM_MASK2 0xFFFF
+ *
+ * Logical AND -- check both TCA/TDA mask:
+ *   #define CONFIG_BATT_ALARM_MASK1 STATUS_TERMINATE_CHARGE_ALARM
+ *   #define CONFIG_BATT_ALARM_MASK2 STATUS_TERMINATE_DISCHARGE_ALARM
+ *
+ * The default configuration is logical OR.
+ */
+#ifdef CONFIG_BATTERY_STBL_STAT
+#ifndef CONFIG_BATT_ALARM_MASK1
+#define CONFIG_BATT_ALARM_MASK1 \
+	(STATUS_TERMINATE_CHARGE_ALARM | STATUS_TERMINATE_DISCHARGE_ALARM)
+#endif
+#ifndef CONFIG_BATT_ALARM_MASK2
+#define CONFIG_BATT_ALARM_MASK2 0xFFFF
+#endif
+#endif
+
 /*****************************************************************************/
 /* Define derived USB PD Discharge common path */
-#if defined(CONFIG_USB_PD_DISCHARGE_GPIO) || \
+#if defined(CONFIG_USB_PD_DISCHARGE_GPIO) ||     \
 	defined(CONFIG_USB_PD_DISCHARGE_TCPC) || \
 	defined(CONFIG_USB_PD_DISCHARGE_PPC)
 #define CONFIG_USB_PD_DISCHARGE
@@ -5265,23 +6500,7 @@
 /* Define derived config options for BC1.2 detection */
 #ifdef CONFIG_BC12_DETECT_PI3USB9201
 #define CONFIG_BC12_DETECT_DATA_ROLE_TRIGGER
-#endif
-
-/*****************************************************************************/
-/*
- * Define CONFIG_LIBCRYPTOC if a board needs to read secret data from the
- * anti-rollback block.
- */
-#ifdef CONFIG_ROLLBACK_SECRET_SIZE
-#define CONFIG_LIBCRYPTOC
-#endif
-
-/*****************************************************************************/
-/* Fingerprint Sensor Configuration */
-#if defined(CONFIG_FP_SENSOR_FPC1025) || \
-	defined(CONFIG_FP_SENSOR_FPC1035) || \
-	defined(CONFIG_FP_SENSOR_FPC1145)
-#define CONFIG_FP_SENSOR
+#undef CONFIG_BC12_CLIENT_MODE_ONLY_PI3USB9201
 #endif
 
 /*****************************************************************************/
@@ -5294,16 +6513,21 @@
 
 #ifndef HAS_TASK_CHIPSET
 #undef CONFIG_AP_HANG_DETECT
+#undef CONFIG_CHIPSET_ALDERLAKE
+#ifndef CONFIG_ZEPHYR
+#undef CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540
+#endif /* CONFIG_ZEPHYR */
 #undef CONFIG_CHIPSET_APOLLOLAKE
-#undef CONFIG_CHIPSET_BRASWELL
 #undef CONFIG_CHIPSET_CANNONLAKE
 #undef CONFIG_CHIPSET_COMETLAKE
 #undef CONFIG_CHIPSET_GEMINILAKE
 #undef CONFIG_CHIPSET_ICELAKE
 #undef CONFIG_CHIPSET_JASPERLAKE
+#undef CONFIG_CHIPSET_METEORLAKE
 #undef CONFIG_CHIPSET_MT817X
 #undef CONFIG_CHIPSET_MT8183
 #undef CONFIG_CHIPSET_MT8192
+#undef CONFIG_CHIPSET_CEZANNE
 #undef CONFIG_CHIPSET_RK3399
 #undef CONFIG_CHIPSET_RK3288
 #undef CONFIG_CHIPSET_SDM845
@@ -5313,6 +6537,19 @@
 #undef CONFIG_POWER_COMMON
 #endif
 
+/*
+ * If the chipset task is enabled, this implies there is an AP to manage power
+ * for. In Zephyr this can be implied by multiple options, so we provide the
+ * same symbol here instead of making code examine HAS_TASK_CHIPSET.
+ */
+#ifndef CONFIG_ZEPHYR
+#ifndef CONFIG_AP_POWER_CONTROL
+#ifdef HAS_TASK_CHIPSET
+#define CONFIG_AP_POWER_CONTROL
+#endif /* HAS_TASK_CHIPSET */
+#endif /* CONFIG_AP_POWER_CONTROL */
+#endif /* CONFIG_ZEPHYR */
+
 /*
  * If a board has a chipset task, set the minimum charger power required for
  * powering on to 15W.  This is also the highest power discovered over Type-C by
@@ -5331,12 +6568,11 @@
 #endif /* !defined(CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON) */
 #endif /* defined(HAS_TASK_CHIPSET) */
 
-
 #ifdef CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW
-# ifndef CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT
-#  define CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT \
+#ifndef CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT
+#define CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT \
 	(CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON)
-# endif
+#endif
 #endif
 
 #ifndef CONFIG_CHARGER_MIN_BAT_PCT_IMBALANCED_POWER_ON
@@ -5405,38 +6641,39 @@
 
 /*****************************************************************************/
 /* Define derived Chipset configs */
-#if defined(CONFIG_CHIPSET_APOLLOLAKE) || \
-	defined(CONFIG_CHIPSET_GEMINILAKE)
+#if defined(CONFIG_CHIPSET_APOLLOLAKE) || defined(CONFIG_CHIPSET_GEMINILAKE)
 #define CONFIG_CHIPSET_APL_GLK
 #endif
 
-#if defined(CONFIG_CHIPSET_JASPERLAKE) || \
-	defined(CONFIG_CHIPSET_TIGERLAKE)
+#if defined(CONFIG_CHIPSET_JASPERLAKE) || defined(CONFIG_CHIPSET_TIGERLAKE) || \
+	defined(CONFIG_CHIPSET_ALDERLAKE)
 #define CONFIG_CHIPSET_ICELAKE
 #endif
 
 #if defined(CONFIG_CHIPSET_APL_GLK)
 #define CONFIG_CHIPSET_HAS_PRE_INIT_CALLBACK
+#define CONFIG_CHIPSET_X86_RSMRST_AFTER_S5
 #endif
 
-#if defined(CONFIG_CHIPSET_APOLLOLAKE) || \
-	defined(CONFIG_CHIPSET_BRASWELL) || \
-	defined(CONFIG_CHIPSET_CANNONLAKE) || \
-	defined(CONFIG_CHIPSET_COMETLAKE) || \
+#if defined(CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540) ||  \
+	defined(CONFIG_CHIPSET_APOLLOLAKE) ||         \
+	defined(CONFIG_CHIPSET_CANNONLAKE) ||         \
+	defined(CONFIG_CHIPSET_COMETLAKE) ||          \
 	defined(CONFIG_CHIPSET_COMETLAKE_DISCRETE) || \
-	defined(CONFIG_CHIPSET_GEMINILAKE) || \
-	defined(CONFIG_CHIPSET_ICELAKE) || \
-	defined(CONFIG_CHIPSET_SKYLAKE)
+	defined(CONFIG_CHIPSET_GEMINILAKE) ||         \
+	defined(CONFIG_CHIPSET_ICELAKE) ||            \
+	defined(CONFIG_CHIPSET_METEORLAKE) || defined(CONFIG_CHIPSET_SKYLAKE)
 #define CONFIG_POWER_COMMON
 #endif
 
-#if defined(CONFIG_CHIPSET_CANNONLAKE) || \
-	defined(CONFIG_CHIPSET_ICELAKE) || \
-	defined(CONFIG_CHIPSET_SKYLAKE)
+#if defined(CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540) || \
+	defined(CONFIG_CHIPSET_CANNONLAKE) ||        \
+	defined(CONFIG_CHIPSET_ICELAKE) ||           \
+	defined(CONFIG_CHIPSET_METEORLAKE) || defined(CONFIG_CHIPSET_SKYLAKE)
 #define CONFIG_CHIPSET_X86_RSMRST_DELAY
 #endif
 
-#if defined(CONFIG_HOSTCMD_ESPI_VW_SLP_S3) && \
+#if defined(CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3) && \
 	defined(CONFIG_CHIPSET_SLP_S3_L_OVERRIDE)
 #error "Cannot use CONFIG_CHIPSET_SLP_S3_L_OVERRIDE if SLP_S3 is a virtual wire"
 #endif
@@ -5445,7 +6682,7 @@
 #error "Must enable CONFIG_POWER_TRACK_HOST_SLEEP_STATE for S0ix"
 #endif
 
-#if defined(CONFIG_CHIPSET_SC7180)
+#if defined(CONFIG_CHIPSET_SC7180) || defined(CONFIG_CHIPSET_SC7280)
 #if defined(CONFIG_POWER_SLEEP_FAILURE_DETECTION) && \
 	!defined(CONFIG_CHIPSET_RESUME_INIT_HOOK)
 #error "Require resume init hook to enable sleep failure detection"
@@ -5461,8 +6698,7 @@
 /*
  * Automatically define CONFIG_ACCEL_LIS2D_COMMON if a child option is defined.
  */
-#if defined(CONFIG_ACCEL_LIS2DH) || \
-	defined(CONFIG_ACCEL_LIS2DE) || \
+#if defined(CONFIG_ACCEL_LIS2DH) || defined(CONFIG_ACCEL_LIS2DE) || \
 	defined(CONFIG_ACCEL_LNG2DM)
 #define CONFIG_ACCEL_LIS2D_COMMON
 #endif
@@ -5470,8 +6706,7 @@
 /*
  * Automatically define CONFIG_ACCEL_LIS2DW_COMMON if a child option is defined.
  */
-#if defined(CONFIG_ACCEL_LIS2DW12) || \
-	defined(CONFIG_ACCEL_LIS2DWL)
+#if defined(CONFIG_ACCEL_LIS2DW12) || defined(CONFIG_ACCEL_LIS2DWL)
 #define CONFIG_ACCEL_LIS2DW_COMMON
 #endif
 
@@ -5479,8 +6714,7 @@
  * CONFIG_ACCEL_LIS2DW12 and CONFIG_ACCEL_LIS2DWL can't be defined at the same
  * time.
  */
-#if defined(CONFIG_ACCEL_LIS2DW12) && \
-	defined(CONFIG_ACCEL_LIS2DWL)
+#if defined(CONFIG_ACCEL_LIS2DW12) && defined(CONFIG_ACCEL_LIS2DWL)
 #error "Define only one of CONFIG_ACCEL_LIS2DW12 and CONFIG_ACCEL_LIS2DWL"
 #endif
 
@@ -5506,8 +6740,8 @@
  */
 #ifdef CONFIG_CHIP_INIT_ROM_REGION
 
-#ifndef CONFIG_FLASH
-#error CONFIG_CHIP_INIT_ROM_REGION requires CONFIG_FLASH
+#ifndef CONFIG_FLASH_CROS
+#error CONFIG_CHIP_INIT_ROM_REGION requires CONFIG_FLASH_CROS
 #endif
 
 #ifndef CONFIG_RO_ROM_RESIDENT_SIZE
@@ -5518,7 +6752,6 @@
 #error CONFIG_CHIP_INIT_ROM_REGION requires CONFIG_RW_ROM_RESIDENT_SIZE
 #endif
 
-
 #if (CONFIG_RO_ROM_RESIDENT_SIZE == 0)
 #error CONFIG_RO_ROM_RESIDENT_SIZE is 0 with CONFIG_CHIP_INIT_ROM_REGION defined
 #endif
@@ -5536,6 +6769,22 @@
 #endif
 #endif /* CONFIG_CHIP_INIT_ROM_REGION */
 
+/*
+ * By default, enable a request for an ACK from AP, on setting the mux, if the
+ * board supports Intel retimer.
+ */
+#if (defined(CONFIG_USBC_RETIMER_INTEL_BB) ||  \
+     defined(CONFIG_USBC_RETIMER_INTEL_HB)) && \
+	defined(CONFIG_USB_MUX_VIRTUAL)
+#define CONFIG_USB_MUX_AP_ACK_REQUEST
+#endif /* CONFIG_USBC_RETIMER_INTEL_BB || CONFIG_USBC_RETIMER_INTEL_HB */
+
+/* Enable retimer console command */
+#if (defined(CONFIG_USBC_RETIMER_INTEL_BB) || \
+     defined(CONFIG_USBC_RETIMER_KB800X))
+#define CONFIG_CMD_RETIMER
+#endif
+
 /*****************************************************************************/
 
 /*
@@ -5550,9 +6799,16 @@
  * Validity checks to make sure some of the configs above make sense.
  */
 
-#if (CONFIG_AUX_TIMER_PERIOD_MS) < ((HOOK_TICK_INTERVAL_MS) * 2)
+/*
+ * Chromium ec uses hook tick to reload the watchdog. The interval between
+ * reloads of the watchdog timer should be less than half of the watchdog
+ * period.
+ */
+#ifdef CONFIG_WATCHDOG
+#if (CONFIG_AUX_TIMER_PERIOD_MS) < ((HOOK_TICK_INTERVAL_MS)*2)
 #error "CONFIG_AUX_TIMER_PERIOD_MS must be at least 2x HOOK_TICK_INTERVAL_MS"
 #endif
+#endif
 
 #ifdef CONFIG_USB_SERIALNO
 #define CONFIG_SERIALNO_LEN 28
@@ -5568,20 +6824,17 @@
 #endif
 
 /* Enable BMI secondary port if needed. */
-#if defined(CONFIG_MAG_BMI_BMM150) || \
-	defined(CONFIG_MAG_BMI_LIS2MDL)
+#if defined(CONFIG_MAG_BMI_BMM150) || defined(CONFIG_MAG_BMI_LIS2MDL)
 #define CONFIG_BMI_SEC_I2C
 #endif
 
 /* Enable LSM2MDL secondary port if needed. */
-#if defined(CONFIG_MAG_LSM6DSM_BMM150) || \
-	defined(CONFIG_MAG_LSM6DSM_LIS2MDL)
+#if defined(CONFIG_MAG_LSM6DSM_BMM150) || defined(CONFIG_MAG_LSM6DSM_LIS2MDL)
 #define CONFIG_LSM6DSM_SEC_I2C
 #endif
 
 /* Load LIS2MDL driver if needed */
-#if defined(CONFIG_MAG_BMI_LIS2MDL) || \
-	defined(CONFIG_MAG_LSM6DSM_LIS2MDL)
+#if defined(CONFIG_MAG_BMI_LIS2MDL) || defined(CONFIG_MAG_LSM6DSM_LIS2MDL)
 #define CONFIG_MAG_LIS2MDL
 #ifndef CONFIG_ACCELGYRO_SEC_ADDR_FLAGS
 #error "The i2c address of the magnetometer is not set."
@@ -5589,8 +6842,7 @@
 #endif
 
 /* Load BMM150 driver if needed */
-#if defined(CONFIG_MAG_BMI_BMM150) || \
-	defined(CONFIG_MAG_LSM6DSM_BMM150)
+#if defined(CONFIG_MAG_BMI_BMM150) || defined(CONFIG_MAG_LSM6DSM_BMM150)
 #define CONFIG_MAG_BMM150
 #ifndef CONFIG_ACCELGYRO_SEC_ADDR_FLAGS
 #error "The i2c address of the magnetometer is not set."
@@ -5618,12 +6870,13 @@
 #error "Flash readout protection and PSTATE may not work as intended."
 #endif
 
-#if !defined(CHIP_FAMILY_STM32H7) && !defined(CHIP_FAMILY_STM32F4)
-#error "Flash readout protection only implemented on STM32H7 and STM32F4."
+#if !defined(CHIP_FAMILY_STM32H7) && !defined(CHIP_FAMILY_STM32F4) && \
+	!defined(CHIP_FAMILY_NPCX9)
+#error "Flash readout protection only implemented on STM32H7, STM32F4 and NPCX9"
 #endif
 #endif /* CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE */
 
-#if defined(CONFIG_USB_PD_TCPM_ANX3429) || \
+#if defined(CONFIG_USB_PD_TCPM_ANX3429) ||     \
 	defined(CONFIG_USB_PD_TCPM_ANX740X) || \
 	defined(CONFIG_USB_PD_TCPM_ANX7471)
 /* Note: ANX7447 is handled by its own driver, not ANX74XX. */
@@ -5640,7 +6893,7 @@
  * SLP_S0 did not assert.
  */
 #ifndef CONFIG_SLEEP_TIMEOUT_MS
-#define CONFIG_SLEEP_TIMEOUT_MS 10000
+#define CONFIG_SLEEP_TIMEOUT_MS 15000
 #endif
 
 #ifdef CONFIG_PWM_KBLIGHT
@@ -5649,10 +6902,8 @@
 
 /*****************************************************************************/
 /* ISH power management related definitions */
-#if defined(CONFIG_ISH_PM_D0I2) || \
-	defined(CONFIG_ISH_PM_D0I3) || \
-	defined(CONFIG_ISH_PM_D3) || \
-	defined(CONFIG_ISH_PM_RESET_PREP)
+#if defined(CONFIG_ISH_PM_D0I2) || defined(CONFIG_ISH_PM_D0I3) || \
+	defined(CONFIG_ISH_PM_D3) || defined(CONFIG_ISH_PM_RESET_PREP)
 
 #ifndef CONFIG_LOW_POWER_IDLE
 #error "Must define CONFIG_LOW_POWER_IDLE if enable ISH low power states"
@@ -5685,12 +6936,12 @@
 
 #endif /* CONFIG_ACCEL_FIFO */
 
-
 /*
  * If USB PD Discharge is enabled, verify that CONFIG_USB_PD_DISCHARGE_GPIO
  * and CONFIG_USB_PD_PORT_MAX_COUNT, CONFIG_USB_PD_DISCHARGE_TCPC, or
  * CONFIG_USB_PD_DISCHARGE_PPC is defined.
  */
+#ifndef CONFIG_TEST_ENABLE_USB_PD_DISCHARGE
 #ifdef CONFIG_USB_PD_DISCHARGE
 #ifdef CONFIG_USB_PD_DISCHARGE_GPIO
 #if !defined(CONFIG_USB_PD_PORT_MAX_COUNT)
@@ -5703,6 +6954,17 @@
 #endif
 #endif /* CONFIG_USB_PD_DISCHARGE_GPIO */
 #endif /* CONFIG_USB_PD_DISCHARGE */
+#endif /* CONFIG_TEST_ENABLE_USB_PD_DISCHARGE */
+
+/* Chargesplash defaults */
+#ifdef CONFIG_CHARGESPLASH
+#ifndef CONFIG_CHARGESPLASH_PERIOD
+#define CONFIG_CHARGESPLASH_PERIOD 900
+#endif
+#ifndef CONFIG_CHARGESPLASH_MAX_REQUESTS_PER_PERIOD
+#define CONFIG_CHARGESPLASH_MAX_REQUESTS_PER_PERIOD 5
+#endif
+#endif
 
 /* EC Codec Wake-on-Voice related definitions */
 #ifdef CONFIG_AUDIO_CODEC_WOV
@@ -5746,21 +7008,21 @@
 #endif
 
 #if defined(CONFIG_USB_PD_TCPM_MULTI_PS8XXX)
-#if defined(CONFIG_USB_PD_TCPM_PS8705) + \
-	defined(CONFIG_USB_PD_TCPM_PS8751) + \
-	defined(CONFIG_USB_PD_TCPM_PS8755) + \
-	defined(CONFIG_USB_PD_TCPM_PS8805) + \
-	defined(CONFIG_USB_PD_TCPM_PS8815) < 2
+#if defined(CONFIG_USB_PD_TCPM_PS8705) + defined(CONFIG_USB_PD_TCPM_PS8751) + \
+		defined(CONFIG_USB_PD_TCPM_PS8755) +                          \
+		defined(CONFIG_USB_PD_TCPM_PS8805) +                          \
+		defined(CONFIG_USB_PD_TCPM_PS8815) <                          \
+	2
 #error "Must select 2 CONFIG_USB_PD_TCPM_PS8* or above if " \
 	"CONFIG_USB_PD_TCPM_MULTI_PS8XXX is defined."
 #endif
 #endif /* CONFIG_USB_PD_TCPM_MULTI_PS8XXX  */
 
-#if defined(CONFIG_USB_PD_TCPM_PS8705) + \
-	defined(CONFIG_USB_PD_TCPM_PS8751) + \
-	defined(CONFIG_USB_PD_TCPM_PS8755) + \
-	defined(CONFIG_USB_PD_TCPM_PS8805) + \
-	defined(CONFIG_USB_PD_TCPM_PS8815) > 1
+#if defined(CONFIG_USB_PD_TCPM_PS8705) + defined(CONFIG_USB_PD_TCPM_PS8751) + \
+		defined(CONFIG_USB_PD_TCPM_PS8755) +                          \
+		defined(CONFIG_USB_PD_TCPM_PS8805) +                          \
+		defined(CONFIG_USB_PD_TCPM_PS8815) >                          \
+	1
 #if !defined(CONFIG_USB_PD_TCPM_MULTI_PS8XXX)
 #error "CONFIG_USB_PD_TCPM_MULTI_PS8XXX MUST be defined if more than one " \
 	"CONFIG_USB_PD_TCPM_PS8* are intended to support in a board."
@@ -5773,16 +7035,149 @@
 #ifndef CONFIG_BODY_DETECTION_SENSOR
 #error CONFIG_BODY_DETECTION_SENSOR must be defined to use body detection
 #endif /* ifndef(CONFIG_BODY_DETECTION_SENSOR) */
-/* Use default setting if CONFIG_BODY_DETECTION_CUSTOM is not set. */
-#ifndef CONFIG_BODY_DETECTION_CUSTOM
-#define CONFIG_BODY_DETECTION_MAX_WINDOW_SIZE     250 /* max sensor odr (Hz) */
-#define CONFIG_BODY_DETECTION_VAR_THRESHOLD       550 /* (mm/s^2)^2 */
-#define CONFIG_BODY_DETECTION_CONFIDENCE_DELTA    525 /* (mm/s^2)^2 */
-#define CONFIG_BODY_DETECTION_VAR_NOISE_FACTOR    120 /* % */
-#define CONFIG_BODY_DETECTION_ON_BODY_CON         50  /* % */
-#define CONFIG_BODY_DETECTION_OFF_BODY_CON        10  /* % */
-#define CONFIG_BODY_DETECTION_STATIONARY_DURATION 15  /* second */
-#endif /* ifndef(CONFIG_BODY_DETECTION_CUSTOM) */
+
+#ifndef CONFIG_BODY_DETECTION_MAX_WINDOW_SIZE
+#define CONFIG_BODY_DETECTION_MAX_WINDOW_SIZE 250 /* max sensor odr (Hz) */
+#endif
+#ifndef CONFIG_BODY_DETECTION_VAR_THRESHOLD
+#define CONFIG_BODY_DETECTION_VAR_THRESHOLD 550 /* (mm/s^2)^2 */
+#endif
+#ifndef CONFIG_BODY_DETECTION_CONFIDENCE_DELTA
+#define CONFIG_BODY_DETECTION_CONFIDENCE_DELTA 525 /* (mm/s^2)^2 */
+#endif
+#ifndef CONFIG_BODY_DETECTION_VAR_NOISE_FACTOR
+#define CONFIG_BODY_DETECTION_VAR_NOISE_FACTOR 120 /* % */
+#endif
+#ifndef CONFIG_BODY_DETECTION_ON_BODY_CON
+#define CONFIG_BODY_DETECTION_ON_BODY_CON 50 /* % */
+#endif
+#ifndef CONFIG_BODY_DETECTION_OFF_BODY_CON
+#define CONFIG_BODY_DETECTION_OFF_BODY_CON 10 /* % */
+#endif
+#ifndef CONFIG_BODY_DETECTION_STATIONARY_DURATION
+#define CONFIG_BODY_DETECTION_STATIONARY_DURATION 15 /* second */
+#endif
+
+#else /* CONFIG_BODY_DETECTION */
+#ifdef CONFIG_BODY_DETECTION_SENSOR
+#error "Unexpected body detection property set"
+#else
+#define CONFIG_BODY_DETECTION_SENSOR 0
+#endif
 #endif /* CONFIG_BODY_DETECTION */
 
-#endif  /* __CROS_EC_CONFIG_H */
+/*
+ * Set parameters to dummy values to use IS_ENABLED().
+ * If a parameter is already set, it will trigger a compilatin error.
+ */
+
+/* To be able to use IS_ENABLED(CONFIG_GESTURE_SENSOR_DOUBLE_TAP) */
+#ifndef CONFIG_GESTURE_SENSOR_DOUBLE_TAP
+#define CONFIG_GESTURE_TAP_THRES_MG 0
+#define CONFIG_GESTURE_TAP_MAX_INTERSTICE_T 0
+#define CONFIG_GESTURE_TAP_SENSOR 0
+#endif /* CONFIG_GESTURE_SENSOR_DOUBLE_TAP */
+
+#ifndef CONFIG_ACCEL_FIFO
+#define CONFIG_ACCEL_FIFO_SIZE 0
+#endif
+
+#ifndef CONFIG_GESTURE_DETECTION
+#define CONFIG_GESTURE_DETECTION_MASK 0
+#endif /* CONFIG_GESTURE_DETECTION */
+
+#ifndef CONFIG_GESTURE_SIGMO
+#define CONFIG_GESTURE_SIGMO_SENSOR 0
+#endif /* CONFIG_GESTURE_SIGMO */
+
+#ifdef CONFIG_LID_ANGLE
+#if !defined(CONFIG_LID_ANGLE_SENSOR_BASE) || \
+	!defined(CONFIG_LID_ANGLE_SENSOR_LID)
+#error "Sensors must be identified for calculating lid angle."
+#endif
+#else /* CONFIG_LID_ANGLE */
+#define CONFIG_LID_ANGLE_SENSOR_BASE 0
+#define CONFIG_LID_ANGLE_SENSOR_LID 0
+#endif /* CONFIG_LID_ANGLE */
+
+#if defined(CONFIG_LID_ANGLE_UPDATE) && !defined(CONFIG_LID_ANGLE)
+#error "CONFIG_LID_ANGLE is needed for CONFIG_LID_ANGLE_UPDATE."
+#endif
+
+#ifndef CONFIG_ALS
+#define ALS_COUNT 0
+#endif /* CONFIG_ALS */
+
+/*
+ * If the EC has exclusive control over CBI EEPROM WP, don't consult the main
+ * flash WP.
+ */
+#ifdef CONFIG_EEPROM_CBI_WP
+#define CONFIG_BYPASS_CBI_EEPROM_WP_CHECK
+#endif
+
+#if defined(CONFIG_EEPROM_CBI_WP) && !defined(CONFIG_CBI_EEPROM)
+#error "CONFIG_EEPROM_CBI_WP requires CONFIG_CBI_EEPROM to be defined!"
+#endif
+
+#if defined(CONFIG_BYPASS_CBI_EEPROM_WP_CHECK) && \
+	!defined(CONFIG_SYSTEM_UNLOCKED) && !defined(CONFIG_EEPROM_CBI_WP)
+#error "CONFIG_BYPASS_CBI_EEPROM_WP_CHECK is only permitted " \
+	"when CONFIG_SYSTEM_UNLOCK or CONFIG_EEPROM_CBI_WP is also enabled."
+#endif /* CONFIG_BYPASS_CBI_EEPROM_WP_CHECK && !CONFIG_SYSTEM_UNLOCK */
+
+#if defined(CONFIG_BOARD_VERSION_CBI) && defined(CONFIG_BOARD_VERSION_GPIO)
+#error "CONFIG_BOARD_VERSION_CBI and CONFIG_BOARD_VERSION_GPIO " \
+	"are mutually exclusive. "
+#endif /* CONFIG_BOARD_VERSION_CBI && CONFIG_BOARD_VERSION_GPIO */
+
+#if defined(CONFIG_CBI_EEPROM) && defined(CONFIG_CBI_GPIO)
+#error "CONFIG_CBI_EEPROM and CONFIG_CBI_GPIO are mutually exclusive."
+#endif
+
+#if !defined(CONFIG_ZEPHYR) && !defined(CONFIG_ACCELGYRO_ICM_COMM_SPI) && \
+	!defined(CONFIG_ACCELGYRO_ICM_COMM_I2C)
+#ifdef I2C_PORT_ACCEL
+#define CONFIG_ACCELGYRO_ICM_COMM_I2C
+#else
+#define CONFIG_ACCELGYRO_ICM_COMM_SPI
+#endif
+#endif /* !CONFIG_ZEPHYR && !CONFIG_ACCELGYRO_ICM_COMM_SPI && \
+	* !CONFIG_ACCELGYRO_ICM_COMM_I2C                      \
+	*/
+
+#if !defined(CONFIG_ZEPHYR) && !defined(CONFIG_ACCELGYRO_BMI_COMM_SPI) && \
+	!defined(CONFIG_ACCELGYRO_BMI_COMM_I2C)
+#ifdef I2C_PORT_ACCEL
+#define CONFIG_ACCELGYRO_BMI_COMM_I2C
+#else
+#define CONFIG_ACCELGYRO_BMI_COMM_SPI
+#endif
+#endif /* !CONFIG_ZEPHYR && !CONFIG_ACCELGYRO_BMI_SPI && \
+	* !CONFIG_ACCELGYRO_BMI_I2C                      \
+	*/
+
+/* AMD STT requires AMD SB-RMI to be enabled */
+#if defined(CONFIG_AMD_STT) && !defined(CONFIG_AMD_SB_RMI)
+#define CONFIG_AMD_SB_RMI
+#endif
+
+/*
+ * Default timeout value for which EC has to wait for system to exit from S5
+ * before performing RTC reset and moving the system to G3.
+ */
+#if defined(CONFIG_BOARD_HAS_RTC_RESET) && !defined(CONFIG_S5_EXIT_WAIT)
+#define CONFIG_S5_EXIT_WAIT 4
+#endif
+
+/* HAS_GPU_DRIVER enables D-Notify and throttling. */
+#if defined(CONFIG_GPU_NVIDIA)
+#define HAS_GPU_DRIVER
+#endif
+
+/* Default to 1024 for end of ram data (panic and jump data) */
+#ifndef CONFIG_PRESERVED_END_OF_RAM_SIZE
+#define CONFIG_PRESERVED_END_OF_RAM_SIZE 1024
+#endif
+
+#endif /* __CROS_EC_CONFIG_H */
diff --git a/include/config_std_internal_flash.h b/include/config_std_internal_flash.h
index 4b722f86d9..5da01a4d16 100644
--- a/include/config_std_internal_flash.h
+++ b/include/config_std_internal_flash.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -37,42 +37,38 @@
  * This is NOT a globally defined config, and is only used in this file
  * for convenience.
  */
-#define _IMAGE_SIZE		((CONFIG_FLASH_SIZE - \
-				  CONFIG_SHAREDLIB_SIZE) / 2)
+#define _IMAGE_SIZE ((CONFIG_FLASH_SIZE_BYTES - CONFIG_SHAREDLIB_SIZE) / 2)
 
 /*
  * The EC uses the one bank of flash to emulate a SPI-like write protect
  * register with persistent state.
  */
 #define CONFIG_FLASH_PSTATE
-#define CONFIG_FW_PSTATE_SIZE	CONFIG_FLASH_BANK_SIZE
-#define CONFIG_FW_PSTATE_OFF	(_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
+#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE
+#define CONFIG_FW_PSTATE_OFF (_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
 
 /*
  * By default, there is no shared objects library.  However, if configured, the
  * shared objects library will be placed after the RO image.
  */
-#define CONFIG_SHAREDLIB_MEM_OFF	(CONFIG_RO_MEM_OFF + \
-					 _IMAGE_SIZE)
-#define CONFIG_SHAREDLIB_STORAGE_OFF	(CONFIG_RO_STORAGE_OFF + \
-					 _IMAGE_SIZE)
-#define CONFIG_SHAREDLIB_SIZE	0
+#define CONFIG_SHAREDLIB_MEM_OFF (CONFIG_RO_MEM_OFF + _IMAGE_SIZE)
+#define CONFIG_SHAREDLIB_STORAGE_OFF (CONFIG_RO_STORAGE_OFF + _IMAGE_SIZE)
+#define CONFIG_SHAREDLIB_SIZE 0
 
-#define CONFIG_RO_MEM_OFF	0
-#define CONFIG_RO_STORAGE_OFF	0
-#define CONFIG_RO_SIZE		(_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
-#define CONFIG_RW_MEM_OFF	(CONFIG_SHAREDLIB_MEM_OFF + \
-				 CONFIG_SHAREDLIB_SIZE)
-#define CONFIG_RW_STORAGE_OFF	0
-#define CONFIG_RW_SIZE		_IMAGE_SIZE
+#define CONFIG_RO_MEM_OFF 0
+#define CONFIG_RO_STORAGE_OFF 0
+#define CONFIG_RO_SIZE (_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
+#define CONFIG_RW_MEM_OFF (CONFIG_SHAREDLIB_MEM_OFF + CONFIG_SHAREDLIB_SIZE)
+#define CONFIG_RW_STORAGE_OFF 0
+#define CONFIG_RW_SIZE _IMAGE_SIZE
 
-#define CONFIG_EC_PROTECTED_STORAGE_OFF		0
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE	CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_OFF		CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE		(CONFIG_FLASH_SIZE - \
-						 CONFIG_EC_WRITABLE_STORAGE_OFF)
+#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
+#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE \
+	(CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF)
 
-#define CONFIG_WP_STORAGE_OFF		CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE		CONFIG_EC_PROTECTED_STORAGE_SIZE
+#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
+#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
 
 #endif /* __CROS_EC_CONFIG_STD_INTERNAL_FLASH_H */
diff --git a/include/console.h b/include/console.h
index 2c8503f0ee..03abbe5732 100644
--- a/include/console.h
+++ b/include/console.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,10 +11,48 @@
 #include "common.h"
 #include "config.h"
 
+#include <stdbool.h>
+
 #ifdef CONFIG_ZEPHYR
 #include "zephyr_console_shim.h"
 #endif
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Define uart_shell_stop(), uart_shell_start(), and
+ * uart_shell_rx_bypass(enable) functions to start/stop/bypass the running
+ * shell. To avoid having a guard on the build type, non-Zephyr builds will
+ * have a stubbed function for these which is safe to call. These functions
+ * will stop/start/stop the Zephyr shell from processing, they should be used
+ * for briefly taking control of the uart.
+ */
+#ifdef CONFIG_ZEPHYR
+int uart_shell_stop(void);
+void uart_shell_start(void);
+void uart_shell_rx_bypass(bool enable);
+
+#ifdef TEST_BUILD
+/* Gets the pointer to the zephyr shell, since it might not always be
+ * the uart backend.
+ */
+const struct shell *get_ec_shell(void);
+#endif
+#else
+static inline int uart_shell_stop(void)
+{
+	return 0;
+}
+static inline void uart_shell_start(void)
+{
+}
+static inline void uart_shell_rx_bypass(bool enable)
+{
+}
+#endif
+
 /*
  * The EC code base has been using %h to print a hex buffer. Encode the
  * parameters to do that in a pointer to a structure that's passed as the
@@ -26,25 +64,9 @@ struct hex_buffer_params {
 	uint16_t size;
 };
 
-#define HEX_BUF(_buffer, _size) (&(const struct hex_buffer_params){ \
-	.buffer = (_buffer), \
-	.size = (_size) \
-})
-
-/*
- * Define parameters to printing in binary: the value to print, and the number
- * of digits to print.
- */
-
-struct binary_print_params {
-	unsigned int value;
-	uint8_t count;
-};
-
-#define BINARY_VALUE(_value, _count) (&(const struct binary_print_params){ \
-	.value = (_value), \
-	.count = (_count) \
-})
+#define HEX_BUF(_buffer, _size)                                  \
+	(&(const struct hex_buffer_params){ .buffer = (_buffer), \
+					    .size = (_size) })
 
 #define PRINTF_TIMESTAMP_NOW NULL
 
@@ -53,7 +75,7 @@ struct console_command {
 	/* Command name.  Case-insensitive. */
 	const char *name;
 	/* Handler for the command.  argv[0] will be the command name. */
-	int (*handler)(int argc, char **argv);
+	int (*handler)(int argc, const char **argv);
 #ifdef CONFIG_CONSOLE_CMDHELP
 	/* Description of args */
 	const char *argdesc;
@@ -66,7 +88,7 @@ struct console_command {
 };
 
 /* Flag bits for when CONFIG_CONSOLE_COMMAND_FLAGS is enabled */
-#define CMD_FLAG_RESTRICTED  0x00000001
+#define CMD_FLAG_RESTRICTED 0x00000001
 
 /* The default .flags value can be overridden in board.h */
 #ifndef CONFIG_CONSOLE_COMMAND_FLAGS_DEFAULT
@@ -88,19 +110,49 @@ static inline int console_is_restricted(void)
 
 /* Console channels */
 enum console_channel {
-	#define CONSOLE_CHANNEL(enumeration, string) enumeration,
-	#include "console_channel.inc"
-	#undef CONSOLE_CHANNEL
+#define CONSOLE_CHANNEL(enumeration, string) enumeration,
+#include "console_channel.inc"
+#undef CONSOLE_CHANNEL
 
 	/* Channel count; not itself a channel */
 	CC_CHANNEL_COUNT
 };
 
 /* Mask in channel_mask for a particular channel */
-#define CC_MASK(channel)	(1U << (channel))
+#define CC_MASK(channel) (1U << (channel))
 
 /* Mask to use to enable all channels */
-#define CC_ALL			0xffffffffU
+#define CC_ALL 0xffffffffU
+
+/**
+ * Enable a console channel by name
+ *
+ * @param name		Console channel name
+ */
+void console_channel_enable(const char *name);
+
+/**
+ * Disable a console channel by name
+ *
+ * @param name		Console channel name
+ */
+void console_channel_disable(const char *name);
+
+/**
+ * Check if channel is disabled.
+ *
+ * @param channel	Output channel
+ *
+ * @return true if channel is disabled, false if not.
+ */
+#ifdef CONFIG_CONSOLE_CHANNEL
+bool console_channel_is_disabled(enum console_channel channel);
+#else
+static inline bool console_channel_is_disabled(enum console_channel channel)
+{
+	return false;
+}
+#endif
 
 /**
  * Put a string to the console channel.
@@ -120,20 +172,20 @@ int cputs(enum console_channel channel, const char *outstr);
  *
  * @return non-zero if output was truncated.
  */
-__attribute__((__format__(__printf__, 2, 3)))
-int cprintf(enum console_channel channel, const char *format, ...);
+__attribute__((__format__(__printf__, 2, 3))) int
+cprintf(enum console_channel channel, const char *format, ...);
 
 /**
  * Print formatted output with timestamp. This is like:
- *   cprintf(channel, "[%pT " + format + "]\n", PRINTF_TIMESTAMP_NOW, ...)
+ *   cprintf(channel, "[<TIMESTAMP> " + format + "]\n", ...)
  *
  * @param channel	Output channel
  * @param format	Format string; see printf.h for valid formatting codes
  *
  * @return non-zero if output was truncated.
  */
-__attribute__((__format__(__printf__, 2, 3)))
-int cprints(enum console_channel channel, const char *format, ...);
+__attribute__((__format__(__printf__, 2, 3))) int
+cprints(enum console_channel channel, const char *format, ...);
 
 /**
  * Flush the console output for all channels.
@@ -147,8 +199,8 @@ void cflush(void);
 #define ccputs(outstr) cputs(CC_COMMAND, outstr)
 /* gcc allows variable arg lists in macros; see
  * http://gcc.gnu.org/onlinedocs/gcc/Variadic-Macros.html */
-#define ccprintf(format, args...) cprintf(CC_COMMAND, format, ## args)
-#define ccprints(format, args...) cprints(CC_COMMAND, format, ## args)
+#define ccprintf(format, args...) cprintf(CC_COMMAND, format, ##args)
+#define ccprints(format, args...) cprints(CC_COMMAND, format, ##args)
 
 /**
  * Called by UART when a line of input is pending.
@@ -163,50 +215,47 @@ void console_has_input(void);
  *                      long (excluding null terminator).  Note this is NOT in
  *                      quotes so it can be concatenated to form a struct name.
  * @param routine       Command handling routine, of the form
- *                      int handler(int argc, char **argv)
+ *                      int handler(int argc, const char **argv)
  * @param argdesc       String describing arguments to command; NULL if none.
  * @param help          String with one-line description of command, or NULL.
  * @param flags         Per-command flags, if needed.
  */
 #if !defined(HAS_TASK_CONSOLE) && !defined(CONFIG_ZEPHYR)
-#define DECLARE_CONSOLE_COMMAND(NAME, ROUTINE, ARGDESC, HELP)		\
-	int (ROUTINE)(int argc, char **argv) __attribute__((unused))
-#define DECLARE_SAFE_CONSOLE_COMMAND(NAME, ROUTINE, ARGDESC, HELP)	\
-	int (ROUTINE)(int argc, char **argv) __attribute__((unused))
+#define DECLARE_CONSOLE_COMMAND(NAME, ROUTINE, ARGDESC, HELP) \
+	static int(ROUTINE)(int argc, const char **argv) __attribute__((unused))
+#define DECLARE_SAFE_CONSOLE_COMMAND(NAME, ROUTINE, ARGDESC, HELP) \
+	static int(ROUTINE)(int argc, const char **argv) __attribute__((unused))
 #define DECLARE_CONSOLE_COMMAND_FLAGS(NAME, ROUTINE, ARGDESC, HELP, FLAGS) \
-	int (ROUTINE)(int argc, char **argv) __attribute__((unused))
+	static int(ROUTINE)(int argc, const char **argv) __attribute__((unused))
 #elif defined(HAS_TASK_CONSOLE)
 
 /* We always provde help args, but we may discard them to save space. */
 #if defined(CONFIG_CONSOLE_CMDHELP)
-#define _HELP_ARGS(A, H)						\
-	.argdesc = A,							\
-	.help = H,
+#define _HELP_ARGS(A, H) .argdesc = A, .help = H,
 #else
 #define _HELP_ARGS(A, H)
 #endif
 
 /* We may or may not have a .flags field */
 #ifdef CONFIG_CONSOLE_COMMAND_FLAGS
-#define _FLAG_ARGS(F)							\
-	.flags = F,
+#define _FLAG_ARGS(F) .flags = F,
 #else
 #define _FLAG_ARGS(F)
 #endif
 
 /* This macro takes all possible args and discards the ones we don't use */
-#define _DCL_CON_CMD_ALL(NAME, ROUTINE, ARGDESC, HELP, FLAGS)		\
-	static const char __con_cmd_label_##NAME[] = #NAME;		\
-	_Static_assert(sizeof(__con_cmd_label_##NAME) < 16,		\
-		       "command name '" #NAME "' is too long");		\
-	const struct console_command __keep __no_sanitize_address	\
-	__con_cmd_##NAME						\
-	__attribute__((section(".rodata.cmds." #NAME))) =		\
-	{ .name = __con_cmd_label_##NAME,				\
-	  .handler = ROUTINE,						\
-	  _HELP_ARGS(ARGDESC, HELP)					\
-	  _FLAG_ARGS(FLAGS)						\
-	}
+#define _DCL_CON_CMD_ALL(NAME, ROUTINE, ARGDESC, HELP, FLAGS)       \
+	static int(ROUTINE)(int argc, const char **argv);           \
+	static const char __con_cmd_label_##NAME[] = #NAME;         \
+	_STATIC_ASSERT(sizeof(__con_cmd_label_##NAME) < 16,         \
+		       "command name '" #NAME "' is too long");     \
+	const struct console_command __keep __no_sanitize_address   \
+		__con_cmd_##NAME                                    \
+		__attribute__((section(".rodata.cmds." #NAME))) = { \
+			.name = __con_cmd_label_##NAME,             \
+			.handler = ROUTINE,                         \
+			_HELP_ARGS(ARGDESC, HELP) _FLAG_ARGS(FLAGS) \
+		}
 
 /*
  * If the .flags field exists, we can use this to specify its value. If not,
@@ -216,8 +265,8 @@ void console_has_input(void);
 	_DCL_CON_CMD_ALL(NAME, ROUTINE, ARGDESC, HELP, FLAGS)
 
 /* This works as before, for the same reason. */
-#define DECLARE_CONSOLE_COMMAND(NAME, ROUTINE, ARGDESC, HELP)	\
-	_DCL_CON_CMD_ALL(NAME, ROUTINE, ARGDESC, HELP,		\
+#define DECLARE_CONSOLE_COMMAND(NAME, ROUTINE, ARGDESC, HELP) \
+	_DCL_CON_CMD_ALL(NAME, ROUTINE, ARGDESC, HELP,        \
 			 CONFIG_CONSOLE_COMMAND_FLAGS_DEFAULT)
 
 /*
@@ -225,11 +274,15 @@ void console_has_input(void);
  * the command is never restricted. BE CAREFUL! You should only use this for
  * commands that either do nothing or that do only safe things.
  */
-#define DECLARE_SAFE_CONSOLE_COMMAND(NAME, ROUTINE, ARGDESC, HELP)	\
-	_DCL_CON_CMD_ALL(NAME, ROUTINE, ARGDESC, HELP,			\
-			 (CONFIG_CONSOLE_COMMAND_FLAGS_DEFAULT &	\
+#define DECLARE_SAFE_CONSOLE_COMMAND(NAME, ROUTINE, ARGDESC, HELP) \
+	_DCL_CON_CMD_ALL(NAME, ROUTINE, ARGDESC, HELP,             \
+			 (CONFIG_CONSOLE_COMMAND_FLAGS_DEFAULT &   \
 			  ~CMD_FLAG_RESTRICTED))
 
-#endif	/* HAS_TASK_CONSOLE */
+#endif /* HAS_TASK_CONSOLE */
+
+#ifdef __cplusplus
+}
+#endif
 
-#endif  /* __CROS_EC_CONSOLE_H */
+#endif /* __CROS_EC_CONSOLE_H */
diff --git a/include/console_channel.inc b/include/console_channel.inc
index e240bf4546..7f37800fd8 100644
--- a/include/console_channel.inc
+++ b/include/console_channel.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,13 +27,14 @@ CONSOLE_CHANNEL(CC_CHARGER,      "charger")
 CONSOLE_CHANNEL(CC_CHIPSET,      "chipset")
 #endif
 CONSOLE_CHANNEL(CC_CLOCK,        "clock")
-#ifdef CONFIG_DMA
+#ifdef CONFIG_DMA_CROS
 CONSOLE_CHANNEL(CC_DMA,          "dma")
 #endif
 #if defined(CONFIG_DEVICE_EVENT) || defined(CONFIG_HOSTCMD_EVENTS)
 CONSOLE_CHANNEL(CC_EVENTS,       "events")
 #endif
-#if defined(HAS_TASK_FPSENSOR) || defined(CONFIG_FP_SENSOR)
+#if defined(HAS_TASK_FPSENSOR) || defined(CONFIG_FINGERPRINT_MCU) || \
+	defined(TEST_BUILD)
 CONSOLE_CHANNEL(CC_FP,           "fingerprint")
 #endif
 #ifdef CONFIG_GESTURE_SW_DETECTION
@@ -56,9 +57,15 @@ CONSOLE_CHANNEL(CC_KEYSCAN,      "keyscan")
 #ifdef CONFIG_LID_ANGLE_UPDATE
 CONSOLE_CHANNEL(CC_LIDANGLE,     "lidangle")
 #endif
+#ifdef HAS_TASK_LOGOLED
+CONSOLE_CHANNEL(CC_LOGOLED,      "logoled")
+#endif
 #ifdef HAS_TASK_LIGHTBAR
 CONSOLE_CHANNEL(CC_LIGHTBAR,     "lightbar")
 #endif
+#ifdef HAS_TASK_RGBKBD
+CONSOLE_CHANNEL(CC_RGBKBD,     "rgbkbd")
+#endif
 /*
    Use CC_LPC for any host communication channels to x86,
    like LPC, eSPI, or IPC...
@@ -75,6 +82,9 @@ CONSOLE_CHANNEL(CC_PORT80,       "port80")
 #ifdef CONFIG_PS2
 CONSOLE_CHANNEL(CC_PS2,          "ps2")
 #endif
+#ifdef CONFIG_PERIPHERAL_CHARGER
+CONSOLE_CHANNEL(CC_PCHG,         "pchg")
+#endif
 #if defined(CONFIG_PWM) || defined(CONFIG_FANS)
 CONSOLE_CHANNEL(CC_PWM,          "pwm")
 #endif
@@ -101,3 +111,6 @@ CONSOLE_CHANNEL(CC_USBPD,        "usbpd")
 #endif
 CONSOLE_CHANNEL(CC_VBOOT,        "vboot")
 CONSOLE_CHANNEL(CC_HOOK,         "hook")
+#ifdef HAS_GPU_DRIVER
+CONSOLE_CHANNEL(CC_GPU,          "gpu")
+#endif
diff --git a/include/consumer.h b/include/consumer.h
index f6d164649e..a331e83a93 100644
--- a/include/consumer.h
+++ b/include/consumer.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/include/crc.h b/include/crc.h
index 511a7cdb9b..04ddfed0c9 100644
--- a/include/crc.h
+++ b/include/crc.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,9 +8,12 @@
 /* CRC-32 implementation with USB constants */
 /* Note: it's a stateful CRC-32 to match the hardware block interface */
 
-#ifdef CONFIG_HW_CRC
+#if defined(CONFIG_HW_CRC) && !defined(HOST_TOOLS_BUILD)
 #include "crc_hw.h"
 #else
+#ifdef CONFIG_ZEPHYR
+#include <stdint.h>
+#endif /* CONFIG_ZEPHYR */
 
 /* Use software implementation */
 
@@ -18,6 +21,14 @@
 
 void crc32_init(void);
 
+/**
+ * Calculate CRC32 of data in arbitrary length.
+ *
+ * @param buf   Data for CRC32 to be calculated for.
+ * @param size  Size of <buf> in bytes.
+ */
+void crc32_hash(const void *buf, int size);
+
 void crc32_hash32(uint32_t val);
 
 void crc32_hash16(uint16_t val);
@@ -28,6 +39,15 @@ uint32_t crc32_result(void);
 
 void crc32_ctx_init(uint32_t *ctx);
 
+/**
+ * Calculate CRC32 of data in arbitrary length using given context.
+ *
+ * @param crc   CRC32 context.
+ * @param buf   Data for CRC32 to be calculated for.
+ * @param size  Size of <buf> in bytes.
+ */
+void crc32_ctx_hash(uint32_t *crc, const void *buf, int size);
+
 void crc32_ctx_hash32(uint32_t *ctx, uint32_t val);
 
 void crc32_ctx_hash16(uint32_t *ctx, uint16_t val);
@@ -36,6 +56,17 @@ void crc32_ctx_hash8(uint32_t *ctx, uint8_t val);
 
 uint32_t crc32_ctx_result(uint32_t *ctx);
 
-#endif /* CONFIG_HW_CRC */
+/**
+ * Return CRC-16 of the data using X^16 + X^15 + X^2 + 1 polynomial, based
+ * upon pre-calculated partial CRC of previous data.
+ * @param data uint8_t *, input, a pointer to input data
+ * @param len int, input, size of input data in bytes
+ * @param previous_crc uint16_t, input, pre-calculated CRC of previous data.
+ *        Seed with zero for a new calculation.
+ * @return the crc-16 of the input data.
+ */
+uint16_t cros_crc16(const uint8_t *data, int len, uint16_t previous_crc);
+
+#endif /* CONFIG_HW_CRC && !HOST_TOOLS_BUILD */
 
 #endif /* __CROS_EC_CRC_H */
diff --git a/include/crc8.h b/include/crc8.h
index e6e70e2bf3..ca1a98eb43 100644
--- a/include/crc8.h
+++ b/include/crc8.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -7,6 +7,8 @@
 #ifndef __CROS_EC_CRC8_H
 #define __CROS_EC_CRC8_H
 
+#include <stdint.h>
+
 /**
  * crc8
  * Return CRC-8 of the data, using x^8 + x^2 + x + 1 polynomial.  A table-based
@@ -16,7 +18,7 @@
  * @param len int, input, size of input data in bytes
  * @return the crc-8 of the input data.
  */
-uint8_t crc8(const uint8_t *data, int len);
+uint8_t cros_crc8(const uint8_t *data, int len);
 
 /**
  * crc8_arg
@@ -25,9 +27,10 @@ uint8_t crc8(const uint8_t *data, int len);
  * @param data uint8_t *, input, a pointer to input data
  * @param len int, input, size of input data in bytes
  * @param previous_crc uint8_t, input, pre-calculated CRC of previous data.
- *        Seed with zero for a new calculation (or use the result of crc8()).
+ *        Seed with zero for a new calculation (or use the result of
+ *        cros_crc8()).
  * @return the crc-8 of the input data.
  */
-uint8_t crc8_arg(const uint8_t *data, int len, uint8_t previous_crc);
+uint8_t cros_crc8_arg(const uint8_t *data, int len, uint8_t previous_crc);
 
 #endif /* __CROS_EC_CRC8_H */
diff --git a/include/cros_board_info.h b/include/cros_board_info.h
index ed5967b0d6..2624cc86d0 100644
--- a/include/cros_board_info.h
+++ b/include/cros_board_info.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,10 +10,24 @@
 #include "common.h"
 #include "ec_commands.h"
 
-#define CBI_VERSION_MAJOR	0
-#define CBI_VERSION_MINOR	0
-#define CBI_EEPROM_SIZE		256
-static const uint8_t cbi_magic[] = { 0x43, 0x42, 0x49 };  /* 'C' 'B' 'I' */
+#define CBI_VERSION_MAJOR 0
+#define CBI_VERSION_MINOR 0
+
+#ifdef CONFIG_CBI_GPIO
+/*
+ * if CBI is sourced from GPIO, the CBI cache only needs to accomondate
+ * BOARD_VERSION and SKU_ID
+ */
+#define CBI_IMAGE_SIZE               \
+	(sizeof(struct cbi_header) + \
+	 (2 * (sizeof(struct cbi_data) + sizeof(uint32_t))))
+#elif defined(CONFIG_CBI_FLASH)
+#define CBI_IMAGE_SIZE DT_PROP(DT_NODELABEL(cbi_flash), size)
+#else
+#define CBI_IMAGE_SIZE 256
+#endif
+
+static const uint8_t cbi_magic[] = { 0x43, 0x42, 0x49 }; /* 'C' 'B' 'I' */
 
 struct cbi_header {
 	uint8_t magic[3];
@@ -36,16 +50,47 @@ struct cbi_header {
 } __attribute__((packed));
 
 struct cbi_data {
-	uint8_t tag;		/* enum cbi_data_tag */
-	uint8_t size;		/* size of value[] */
-	uint8_t value[];	/* data value */
+	uint8_t tag; /* enum cbi_data_tag */
+	uint8_t size; /* size of value[] */
+	uint8_t value[]; /* data value */
 } __attribute__((packed));
 
+enum cbi_cache_status {
+	CBI_CACHE_STATUS_SYNCED = 0,
+	CBI_CACHE_STATUS_INVALID = 1
+};
+
+enum cbi_storage_type {
+	CBI_STORAGE_TYPE_EEPROM = 0,
+	CBI_STORAGE_TYPE_GPIO = 1,
+	CBI_STORAGE_TYPE_FLASH = 2,
+};
+
+/*
+ * Driver for storage media access
+ */
+struct cbi_storage_driver {
+	/* Write the whole CBI from RAM to storage media (i.e. sync) */
+	int (*store)(uint8_t *cache);
+	/*
+	 * Read blocks from storage media to RAM. Note that the granularity
+	 * of load function is asymmetrical to that of the store function.
+	 */
+	int (*load)(uint8_t offset, uint8_t *data, int len);
+	/* Return write protect status for the storage media */
+	int (*is_protected)(void);
+};
+
+extern const struct cbi_storage_config_t {
+	enum cbi_storage_type storage_type;
+	const struct cbi_storage_driver *drv;
+} cbi_config;
+
 /**
  * Board info accessors
  *
- * @param version/sku_id/oem_id/id/fw_config/pcb_supplier/ssfc [OUT] Data read
- *        from EEPROM
+ * @param version/sku_id/oem_id/id/fw_config/pcb_supplier/ssfc/rework_id [OUT]
+ *        Data_read from EEPROM.
  * @return EC_SUCCESS on success or EC_ERROR_* otherwise.
  *         EC_ERROR_BUSY to indicate data is not ready.
  */
@@ -56,6 +101,8 @@ int cbi_get_model_id(uint32_t *id);
 int cbi_get_fw_config(uint32_t *fw_config);
 int cbi_get_pcb_supplier(uint32_t *pcb_supplier);
 int cbi_get_ssfc(uint32_t *ssfc);
+int cbi_get_rework_id(uint64_t *id);
+int cbi_get_factory_calibration_data(uint32_t *calibration_data);
 
 /**
  * Get data from CBI store
@@ -101,8 +148,8 @@ uint8_t cbi_crc8(const struct cbi_header *h);
  * @return	Address of the byte following the stored data in the
  * 		destination buffer
  */
-uint8_t *cbi_set_data(uint8_t *p, enum cbi_data_tag tag,
-		      const void *buf, int size);
+uint8_t *cbi_set_data(uint8_t *p, enum cbi_data_tag tag, const void *buf,
+		      int size);
 
 /**
  * Store string data in memory in CBI data format.
@@ -146,13 +193,65 @@ struct cbi_data *cbi_find_tag(const void *cbi, enum cbi_data_tag tag);
  */
 int cbi_board_override(enum cbi_data_tag tag, uint8_t *buf, uint8_t *size);
 
-#ifdef TEST_BUILD
 /**
- * Test only declarations. Firmware shouldn't need them.
+ * Set and update FW_CONFIG tag field
+ *
+ * This function is only included when CONFIG_AP_POWER_CONTROL is disabled. It
+ * is intended to be used for projects which want CBI functions, but do not
+ * have an AP and ectool host command access.
+ *
+ * @param fw_config	updated value for FW_CONFIG tag
+ * @return EC_SUCCESS to indicate the field was written correctly.
+ *         EC_ERROR_ACCESS_DENIED to indicate WP is active
+ *         EC_ERROR_UNKNOWN to indicate that the write operation failed
+ */
+int cbi_set_fw_config(uint32_t fw_config);
+
+/**
+ * Set and update SSFC tag field
+ *
+ * This function is only included when CONFIG_AP_POWER_CONTROL is disabled. It
+ * is intended to be used for projects which want CBI functions, but do not
+ * have an AP and ectool host command access.
+ *
+ * @param ssfc	updated value for SSFC tag
+ * @return EC_SUCCESS to indicate the field was written correctly.
+ *         EC_ERROR_ACCESS_DENIED to indicate WP is active
+ *         EC_ERROR_UNKNOWN to indicate that the write operation failed
+ */
+int cbi_set_ssfc(uint32_t ssfc);
+
+/**
+ * Initialize CBI cache
  */
 int cbi_create(void);
-int cbi_write(void);
+
+/**
+ * Override CBI cache status to EC_CBI_CACHE_INVALID
+ */
 void cbi_invalidate_cache(void);
+
+/**
+ * Return CBI cache status
+ */
+int cbi_get_cache_status(void);
+
+/**
+ * Latch the CBI EEPROM WP
+ *
+ * This function assumes that the EC has a pin to set the CBI EEPROM WP signal
+ * (GPIO_EC_CBI_WP).  Note that once the WP is set, the EC must be reset via
+ * EC_RST_ODL in order for the WP to become unset since the signal is latched.
+ */
+void cbi_latch_eeprom_wp(void);
+
+#ifdef TEST_BUILD
+/**
+ * Write the locally cached CBI to EEPROM.
+ *
+ * @return EC_RES_SUCCESS on success or EC_RES_* otherwise.
+ */
+int cbi_write(void);
 #endif
 
 #endif /* __CROS_EC_CROS_BOARD_INFO_H */
diff --git a/include/cros_version.h b/include/cros_version.h
new file mode 100644
index 0000000000..8e3429773a
--- /dev/null
+++ b/include/cros_version.h
@@ -0,0 +1,43 @@
+/* Copyright 2012 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Version number for Chrome EC */
+
+#ifndef __CROS_EC_VERSION_H
+#define __CROS_EC_VERSION_H
+
+#include "common.h"
+#include "system.h"
+
+#define CROS_EC_IMAGE_DATA_COOKIE1 0xce778899
+#define CROS_EC_IMAGE_DATA_COOKIE2 0xceaabbdd
+#define CROS_EC_IMAGE_DATA_COOKIE3 0xceeeff00
+#define CROS_EC_IMAGE_DATA_COOKIE3_MASK GENMASK(31, 8)
+#define CROS_EC_IMAGE_DATA_COOKIE3_VERSION GENMASK(7, 0)
+
+#define CROS_FWID_MISSING_STR "CROS_FWID_MISSING"
+
+struct image_data {
+	uint32_t cookie1;
+	char version[32];
+	uint32_t size;
+	int32_t rollback_version;
+	uint32_t cookie2;
+	char cros_fwid[32];
+	uint32_t cookie3;
+} __packed;
+
+extern const struct image_data current_image_data;
+extern const char build_info[];
+extern const char __image_data_offset[];
+extern const void *__image_size;
+
+/**
+ * Get the number of commits of an image
+ *
+ * @return Number of commits in integer or 0 on error
+ */
+int ver_get_num_commits(enum ec_image copy);
+#endif /* __CROS_EC_VERSION_H */
diff --git a/include/crypto/cleanse_wrapper.h b/include/crypto/cleanse_wrapper.h
new file mode 100644
index 0000000000..f5dd0c9496
--- /dev/null
+++ b/include/crypto/cleanse_wrapper.h
@@ -0,0 +1,46 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* A drop-in replacement wrapper for OPENSSL_cleanse. */
+
+#ifndef __CROS_EC_CRYPTO_CLEANSE_WRAPPER_H
+#define __CROS_EC_CRYPTO_CLEANSE_WRAPPER_H
+
+#include "openssl/mem.h"
+
+#include <type_traits>
+#include <utility>
+
+/* TODO(b/283907495): replace with upstream version. */
+/**
+ * CleanseWrapper is a drop-in replacement to make sure the data is cleaned
+ * after use.
+ *
+ * @tparam T The type of the data to be wrapped.
+ * @tparam Enable The enable_if_t helper field.
+ */
+template <typename T> class CleanseWrapper : public T {
+    public:
+	static_assert(
+		std::is_trivial_v<T> &&std::is_standard_layout_v<T>,
+		"This only works for the type that is trivial and standard layout.");
+
+	/* Inherit all existing constructor and assign operator. */
+	using T::T;
+
+	/* Allow implicit conversions. */
+	constexpr CleanseWrapper(const T &t)
+		: T(t)
+	{
+	}
+
+	/* Clean the data. */
+	~CleanseWrapper()
+	{
+		OPENSSL_cleanse(this, sizeof(*this));
+	}
+};
+
+#endif /* __CROS_EC_CRYPTO_CLEANSE_WRAPPER_H */
diff --git a/include/crypto/elliptic_curve_key.h b/include/crypto/elliptic_curve_key.h
new file mode 100644
index 0000000000..1e56f5d428
--- /dev/null
+++ b/include/crypto/elliptic_curve_key.h
@@ -0,0 +1,20 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Helpers for the boringssl elliptic curve key interface. */
+
+#ifndef __CROS_EC_ELLIPTIC_CURVE_KEY_H
+#define __CROS_EC_ELLIPTIC_CURVE_KEY_H
+
+#include "openssl/ec_key.h"
+#include "openssl/mem.h"
+
+/**
+ * Generate a p256 ECC key.
+ * @return key on success, nullptr on failure
+ */
+bssl::UniquePtr<EC_KEY> generate_elliptic_curve_key();
+
+#endif /* __CROS_EC_ELLIPTIC_CURVE_KEY_H */
diff --git a/include/crypto_api.h b/include/crypto_api.h
index 8a8ccacf99..c6374ebee4 100644
--- a/include/crypto_api.h
+++ b/include/crypto_api.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,8 +26,8 @@ extern "C" {
  *		    value exceeds SHA1 size (20 bytes), the rest of the
  *		    hash is filled up with zeros.
  */
-void app_compute_hash(uint8_t *p_buf, size_t num_bytes,
-		      uint8_t *p_hash, size_t hash_len);
+void app_compute_hash(uint8_t *p_buf, size_t num_bytes, uint8_t *p_hash,
+		      size_t hash_len);
 
 #define CIPHER_SALT_SIZE 16
 
diff --git a/include/device_event.h b/include/device_event.h
index 81b949076c..7a9992b0df 100644
--- a/include/device_event.h
+++ b/include/device_event.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,6 +19,8 @@ uint32_t device_get_events(void);
 /**
  * Set one or more device event bits.
  *
+ * Call device_clear_events to unset event bits.
+ *
  * @param mask          Event bits to set (use EC_DEVICE_EVENT_MASK()).
  */
 void device_set_events(uint32_t mask);
@@ -41,4 +43,11 @@ static inline void device_set_single_event(int event)
 	device_set_events(EC_DEVICE_EVENT_MASK(event));
 }
 
-#endif  /* __CROS_EC_DEVICE_EVENT_H */
+/**
+ * Enable device event.
+ *
+ * @param event         Event to enable (EC_DEVICE_EVENT_*)
+ */
+void device_enable_event(enum ec_device_event event);
+
+#endif /* __CROS_EC_DEVICE_EVENT_H */
diff --git a/include/device_state.h b/include/device_state.h
index e7894ba998..7df80b374d 100644
--- a/include/device_state.h
+++ b/include/device_state.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -84,4 +84,4 @@ int device_set_state(enum device_type device, enum device_state state);
  */
 void board_update_device_state(enum device_type device);
 
-#endif  /* __CROS_DEVICE_STATE_H */
+#endif /* __CROS_DEVICE_STATE_H */
diff --git a/include/display_7seg.h b/include/display_7seg.h
index cbaf33f458..976d496ccb 100644
--- a/include/display_7seg.h
+++ b/include/display_7seg.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,9 +9,9 @@
 #define __CROS_EC_DISPLAY_7SEG_H
 
 enum seven_seg_module_display {
-	SEVEN_SEG_CONSOLE_DISPLAY,	/* Console data */
-	SEVEN_SEG_EC_DISPLAY,		/* power state */
-	SEVEN_SEG_PORT80_DISPLAY,	/* port80 data */
+	SEVEN_SEG_CONSOLE_DISPLAY, /* Console data */
+	SEVEN_SEG_EC_DISPLAY, /* power state */
+	SEVEN_SEG_PORT80_DISPLAY, /* port80 data */
 };
 
 /**
@@ -23,5 +23,4 @@ enum seven_seg_module_display {
  */
 int display_7seg_write(enum seven_seg_module_display module, uint16_t data);
 
-#endif  /* __CROS_EC_DISPLAY_7SEG_H */
-
+#endif /* __CROS_EC_DISPLAY_7SEG_H */
diff --git a/include/dma.h b/include/dma.h
index 1687b5f899..dd77801dff 100644
--- a/include/dma.h
+++ b/include/dma.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,7 +8,7 @@
 #ifndef __CROS_EC_DMA_H
 #define __CROS_EC_DMA_H
 
-#ifdef CONFIG_DMA
+#ifdef CONFIG_DMA_CROS
 
 #include "common.h"
 #include "registers.h"
@@ -17,14 +17,14 @@
 
 /* DMA channel options */
 struct dma_option {
-	enum dma_channel channel;	/* DMA channel */
-	void *periph;		/* Pointer to peripheral data register */
-	unsigned flags;		/* DMA flags for the control register. Normally
-				   used to select memory size. */
+	enum dma_channel channel; /* DMA channel */
+	void *periph; /* Pointer to peripheral data register */
+	unsigned int flags; /* DMA flags for the control register. Normally
+			   used to select memory size. */
 };
 
-#define DMA_POLLING_INTERVAL_US	100	/* us */
-#define DMA_TRANSFER_TIMEOUT_US	(100 * MSEC) /* us */
+#define DMA_POLLING_INTERVAL_US 100 /* us */
+#define DMA_TRANSFER_TIMEOUT_US (100 * MSEC) /* us */
 
 /**
  * Get a pointer to a DMA channel.
@@ -45,7 +45,7 @@ dma_chan_t *dma_get_channel(enum dma_channel channel);
  *
  * @return pointer to prepared channel
  */
-void dma_prepare_tx(const struct dma_option *option, unsigned count,
+void dma_prepare_tx(const struct dma_option *option, unsigned int count,
 		    const void *memory);
 
 /**
@@ -55,7 +55,7 @@ void dma_prepare_tx(const struct dma_option *option, unsigned count,
  * @param count		Number of bytes to transfer
  * @param memory	Pointer to memory address
  */
-void dma_start_rx(const struct dma_option *option, unsigned count,
+void dma_start_rx(const struct dma_option *option, unsigned int count,
 		  void *memory);
 
 /**
@@ -117,7 +117,7 @@ void dma_dump(enum dma_channel channel);
  * Testing: Test that DMA works correctly for memory to memory transfers
  */
 void dma_test(enum dma_channel channel);
-#endif  /* CONFIG_DMA_HELP */
+#endif /* CONFIG_DMA_HELP */
 
 /**
  * Clear the DMA interrupt/event flags for a given channel
@@ -167,5 +167,5 @@ int dma_wait(enum dma_channel channel);
  */
 void dma_init(void);
 
-#endif /* CONFIG_DMA */
+#endif /* CONFIG_DMA_CROS */
 #endif
diff --git a/include/dps.h b/include/dps.h
new file mode 100644
index 0000000000..c4d2c884b1
--- /dev/null
+++ b/include/dps.h
@@ -0,0 +1,90 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_DPS__H
+#define __CROS_EC_DPS__H
+
+#include "common.h"
+
+#include <stdbool.h>
+
+#define DPS_FLAG_DISABLED BIT(0)
+#define DPS_FLAG_NO_SRCCAP BIT(1)
+#define DPS_FLAG_WAITING BIT(2)
+#define DPS_FLAG_SAMPLED BIT(3)
+#define DPS_FLAG_NEED_MORE_PWR BIT(4)
+#define DPS_FLAG_NO_BATTERY BIT(5)
+
+/* Dynamic PDO Selection config. */
+struct dps_config_t {
+	/* (0, 100) coeff for transition to a lower power PDO*/
+	uint32_t k_less_pwr;
+	/* (0, 100) coeff for transition to a higher power PDO*/
+	uint32_t k_more_pwr;
+	/* Number for how many the same consecutive sample to transist */
+	uint32_t k_sample;
+	/* Number for moving average window for the power and the current. */
+	uint32_t k_window;
+	/* Power stabilized time after a new contract in us */
+	uint32_t t_stable;
+	/* Next power evaluation time interval in us */
+	uint32_t t_check;
+	/*
+	 * If the current voltage is more efficient than the previous voltage
+	 *
+	 * @param curr_mv: current PDO voltage
+	 * @param prev_mv: previous PDO voltage
+	 * @param batt_mv: battery desired voltage
+	 * @param batt_mw: current battery power
+	 * @param input_mw: current adapter input power
+	 * @return true is curr_mv is more efficient otherwise false
+	 */
+	bool (*is_more_efficient)(int curr_mv, int prev_mv, int batt_mv,
+				  int batt_mw, int input_mw);
+};
+
+/*
+ * Get voltage in the current system load
+ *
+ * @return a voltage(mV) that the adapter supports to charge at the given port.
+ */
+int dps_get_dynamic_voltage(void);
+
+/*
+ * Get DPS charge port
+ *
+ * @return the DPS charge port, or CHARGE_PORT_NONE if unavailable.
+ */
+int dps_get_charge_port(void);
+
+/*
+ * Check if DPS is enabled.
+ *
+ * @return true if enabled, false otherwise.
+ */
+bool dps_is_enabled(void);
+
+/*
+ * Update DPS stablized timeout
+ *
+ * This is called at the exit of PE_SNK_TRANSITION_SINK
+ *
+ * @param port: the port for timer reset.
+ */
+void dps_update_stabilized_time(int port);
+
+#ifdef TEST_BUILD
+__test_only void dps_enable(bool en);
+__test_only int dps_init(void);
+__test_only struct dps_config_t *dps_get_config(void);
+__test_only bool dps_is_fake_enabled(void);
+__test_only int dps_get_fake_mv(void);
+__test_only int dps_get_fake_ma(void);
+__test_only int *dps_get_debug_level(void);
+__test_only int dps_get_flag(void);
+
+#endif
+
+#endif /* __CROS_EC_DPS__H */
diff --git a/include/dptf.h b/include/dptf.h
index c34e8ea47a..b71b4cf5c0 100644
--- a/include/dptf.h
+++ b/include/dptf.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,10 +27,10 @@ int dptf_get_fan_duty_target(void);
 /**
  * Set/enable the thresholds.
  */
-void dptf_set_temp_threshold(int sensor_id,	/* zero-based sensor index */
-			     int temp,		/* in degrees K */
-			     int idx,		/* which threshold (0 or 1) */
-			     int enable);	/* true = on, false = off */
+void dptf_set_temp_threshold(int sensor_id, /* zero-based sensor index */
+			     int temp, /* in degrees K */
+			     int idx, /* which threshold (0 or 1) */
+			     int enable); /* true = on, false = off */
 
 /**
  * Return the ID of a temp sensor that has crossed its threshold since the last
@@ -48,4 +48,4 @@ void dptf_set_charging_current_limit(int ma);
  */
 int dptf_get_charging_current_limit(void);
 
-#endif	/* __CROS_EC_DPTF_H */
+#endif /* __CROS_EC_DPTF_H */
diff --git a/include/driver/accel_bma2x2.h b/include/driver/accel_bma2x2.h
new file mode 100644
index 0000000000..c6be3b0c87
--- /dev/null
+++ b/include/driver/accel_bma2x2.h
@@ -0,0 +1,154 @@
+/* Copyright 2016 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* BMA2x2 gsensor module for Chrome EC */
+
+#ifndef __CROS_EC_ACCEL_BMA2x2_H
+#define __CROS_EC_ACCEL_BMA2x2_H
+
+#include "accel_bma2x2_public.h"
+
+/*** Chip-specific registers ***/
+/* REGISTER ADDRESS DEFINITIONS */
+#define BMA2x2_EEP_OFFSET 0x16
+#define BMA2x2_IMAGE_BASE 0x38
+#define BMA2x2_IMAGE_LEN 22
+#define BMA2x2_CHIP_ID_ADDR 0x00
+#define BMA255_CHIP_ID_MAJOR 0xfa
+
+/* DATA ADDRESS DEFINITIONS */
+#define BMA2x2_X_AXIS_LSB_ADDR 0x02
+#define BMA2x2_X_AXIS_MSB_ADDR 0x03
+#define BMA2x2_Y_AXIS_LSB_ADDR 0x04
+#define BMA2x2_Y_AXIS_MSB_ADDR 0x05
+#define BMA2x2_Z_AXIS_LSB_ADDR 0x06
+#define BMA2x2_Z_AXIS_MSB_ADDR 0x07
+#define BMA2x2_TEMP_ADDR 0x08
+
+#define BMA2x2_AXIS_LSB_NEW_DATA 0x01
+
+/* STATUS ADDRESS DEFINITIONS */
+#define BMA2x2_STAT1_ADDR 0x09
+#define BMA2x2_STAT2_ADDR 0x0A
+#define BMA2x2_STAT_TAP_SLOPE_ADDR 0x0B
+#define BMA2x2_STAT_ORIENT_HIGH_ADDR 0x0C
+#define BMA2x2_STAT_FIFO_ADDR 0x0E
+#define BMA2x2_RANGE_SELECT_ADDR 0x0F
+#define BMA2x2_RANGE_SELECT_MSK 0x0F
+#define BMA2x2_RANGE_2G 3
+#define BMA2x2_RANGE_4G 5
+#define BMA2x2_RANGE_8G 8
+#define BMA2x2_RANGE_16G 12
+
+#define BMA2x2_RANGE_TO_REG(_range)                            \
+	((_range) < 8 ? BMA2x2_RANGE_2G + ((_range) / 4) * 2 : \
+			BMA2x2_RANGE_8G + ((_range) / 16) * 4)
+
+#define BMA2x2_REG_TO_RANGE(_reg)                                \
+	((_reg) < BMA2x2_RANGE_8G ? 2 + (_reg)-BMA2x2_RANGE_2G : \
+				    8 + ((_reg)-BMA2x2_RANGE_8G) * 2)
+
+#define BMA2x2_BW_SELECT_ADDR 0x10
+#define BMA2x2_BW_MSK 0x1F
+#define BMA2x2_BW_7_81HZ 0x08 /* LowPass   7.8125HZ */
+#define BMA2x2_BW_15_63HZ 0x09 /* LowPass  15.625HZ */
+#define BMA2x2_BW_31_25HZ 0x0A /* LowPass  31.25HZ */
+#define BMA2x2_BW_62_50HZ 0x0B /* LowPass  62.50HZ */
+#define BMA2x2_BW_125HZ 0x0C /* LowPass 125HZ */
+#define BMA2x2_BW_250HZ 0x0D /* LowPass 250HZ */
+#define BMA2x2_BW_500HZ 0x0E /* LowPass 500HZ */
+#define BMA2x2_BW_1000HZ 0x0F /* LowPass 1000HZ */
+
+/* Do not use BW lower than 7813, because __fls cannot be call for 0 */
+#define BMA2x2_BW_TO_REG(_bw)                                            \
+	((_bw) < 125000 ? BMA2x2_BW_7_81HZ + __fls(((_bw)*10) / 78125) : \
+			  BMA2x2_BW_125HZ + __fls((_bw) / 125000))
+
+#define BMA2x2_REG_TO_BW(_reg)                               \
+	((_reg) < BMA2x2_BW_125HZ ?                          \
+		 (78125 << ((_reg)-BMA2x2_BW_7_81HZ)) / 10 : \
+		 125000 << ((_reg)-BMA2x2_BW_125HZ))
+
+#define BMA2x2_MODE_CTRL_ADDR 0x11
+#define BMA2x2_LOW_NOISE_CTRL_ADDR 0x12
+#define BMA2x2_DATA_CTRL_ADDR 0x13
+#define BMA2x2_DATA_HIGH_BW 0x80
+#define BMA2x2_DATA_SHADOW_DIS 0x40
+#define BMA2x2_RST_ADDR 0x14
+#define BMA2x2_CMD_SOFT_RESET 0xb6
+
+/* INTERRUPT ADDRESS DEFINITIONS */
+#define BMA2x2_INTR_ENABLE1_ADDR 0x16
+#define BMA2x2_INTR_ENABLE2_ADDR 0x17
+#define BMA2x2_INTR_SLOW_NO_MOTION_ADDR 0x18
+#define BMA2x2_INTR1_PAD_SELECT_ADDR 0x19
+#define BMA2x2_INTR_DATA_SELECT_ADDR 0x1A
+#define BMA2x2_INTR2_PAD_SELECT_ADDR 0x1B
+#define BMA2x2_INTR_SOURCE_ADDR 0x1E
+#define BMA2x2_INTR_SET_ADDR 0x20
+#define BMA2x2_INTR_CTRL_ADDR 0x21
+#define BMA2x2_INTR_CTRL_RST_INT 0x80
+
+/* FEATURE ADDRESS DEFINITIONS */
+#define BMA2x2_LOW_DURN_ADDR 0x22
+#define BMA2x2_LOW_THRES_ADDR 0x23
+#define BMA2x2_LOW_HIGH_HYST_ADDR 0x24
+#define BMA2x2_HIGH_DURN_ADDR 0x25
+#define BMA2x2_HIGH_THRES_ADDR 0x26
+#define BMA2x2_SLOPE_DURN_ADDR 0x27
+#define BMA2x2_SLOPE_THRES_ADDR 0x28
+#define BMA2x2_SLOW_NO_MOTION_THRES_ADDR 0x29
+#define BMA2x2_TAP_PARAM_ADDR 0x2A
+#define BMA2x2_TAP_THRES_ADDR 0x2B
+#define BMA2x2_ORIENT_PARAM_ADDR 0x2C
+#define BMA2x2_THETA_BLOCK_ADDR 0x2D
+#define BMA2x2_THETA_FLAT_ADDR 0x2E
+#define BMA2x2_FLAT_HOLD_TIME_ADDR 0x2F
+#define BMA2x2_SELFTEST_ADDR 0x32
+#define BMA2x2_EEPROM_CTRL_ADDR 0x33
+#define BMA2x2_EEPROM_REMAIN_OFF 4
+#define BMA2x2_EEPROM_REMAIN_MSK 0xF0
+#define BMA2x2_EEPROM_LOAD 0x08
+#define BMA2x2_EEPROM_RDY 0x04
+#define BMA2x2_EEPROM_PROG 0x02
+#define BMA2x2_EEPROM_PROG_EN 0x01
+#define BMA2x2_SERIAL_CTRL_ADDR 0x34
+
+/* OFFSET ADDRESS DEFINITIONS */
+#define BMA2x2_OFFSET_CTRL_ADDR 0x36
+#define BMA2x2_OFFSET_RESET 0x80
+#define BMA2x2_OFFSET_TRIGGER_OFF 5
+#define BMA2x2_OFFSET_TRIGGER_MASK (0x3 << BMA2x2_OFFSET_TRIGGER_OFF)
+#define BMA2x2_OFFSET_CAL_READY 0x10
+#define BMA2x2_OFFSET_CAL_SLOW_X 0x04
+#define BMA2x2_OFFSET_CAL_SLOW_Y 0x02
+#define BMA2x2_OFFSET_CAL_SLOW_Z 0x01
+
+#define BMA2x2_OFC_SETTING_ADDR 0x37
+#define BMA2x2_OFC_TARGET_AXIS_OFF 1
+#define BMA2x2_OFC_TARGET_AXIS_LEN 2
+#define BMA2x2_OFC_TARGET_AXIS(_axis) \
+	(BMA2x2_OFC_TARGET_AXIS_LEN * (_axis) + BMA2x2_OFC_TARGET_AXIS_OFF)
+#define BMA2x2_OFC_TARGET_0G 0
+#define BMA2x2_OFC_TARGET_PLUS_1G 1
+#define BMA2x2_OFC_TARGET_MINUS_1G 2
+
+#define BMA2x2_OFFSET_X_AXIS_ADDR 0x38
+#define BMA2x2_OFFSET_Y_AXIS_ADDR 0x39
+#define BMA2x2_OFFSET_Z_AXIS_ADDR 0x3A
+
+/* GP ADDRESS DEFINITIONS */
+#define BMA2x2_GP0_ADDR 0x3B
+#define BMA2x2_GP1_ADDR 0x3C
+
+/* FIFO ADDRESS DEFINITIONS */
+#define BMA2x2_FIFO_MODE_ADDR 0x3E
+#define BMA2x2_FIFO_DATA_OUTPUT_ADDR 0x3F
+#define BMA2x2_FIFO_WML_TRIG 0x30
+
+/* Sensor resolution in number of bits. This sensor has fixed resolution. */
+#define BMA2x2_RESOLUTION 12
+
+#endif /* __CROS_EC_ACCEL_BMA2x2_H */
diff --git a/include/driver/accel_bma2x2_public.h b/include/driver/accel_bma2x2_public.h
new file mode 100644
index 0000000000..04d7a33e4c
--- /dev/null
+++ b/include/driver/accel_bma2x2_public.h
@@ -0,0 +1,49 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* BMA2x2 gsensor module for Chrome EC */
+
+#ifndef __CROS_EC_DRIVER_ACCEL_BMA2x2_PUBLIC_H
+#define __CROS_EC_DRIVER_ACCEL_BMA2x2_PUBLIC_H
+
+#include "accelgyro.h"
+
+extern const struct accelgyro_drv bma2x2_accel_drv;
+
+/* I2C ADDRESS DEFINITIONS    */
+/* The following definition of I2C address is used for the following sensors
+ * BMA253
+ * BMA255
+ * BMA355
+ * BMA280
+ * BMA282
+ * BMA223
+ * BMA254
+ * BMA284
+ * BMA250E
+ * BMA222E
+ */
+#define BMA2x2_I2C_ADDR1_FLAGS 0x18
+#define BMA2x2_I2C_ADDR2_FLAGS 0x19
+
+/* The following definition of I2C address is used for the following sensors
+ * BMC150
+ * BMC056
+ * BMC156
+ */
+#define BMA2x2_I2C_ADDR3_FLAGS 0x10
+#define BMA2x2_I2C_ADDR4_FLAGS 0x11
+
+/*
+ * Min and Max sampling frequency in mHz.
+ * Given BMA255 is polled, we limit max frequency to 125Hz.
+ * If set to 250Hz, given we can read up to 3ms before the due time
+ * (see CONFIG_MOTION_MIN_SENSE_WAIT_TIME), we may read too early when
+ * other sensors are active.
+ */
+#define BMA255_ACCEL_MIN_FREQ 7810
+#define BMA255_ACCEL_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(125000, 15625)
+
+#endif /* CROS_EC_DRIVER_ACCEL_BMA2x2_PUBLIC_H */
diff --git a/include/driver/accel_lis2dw12_public.h b/include/driver/accel_lis2dw12_public.h
new file mode 100644
index 0000000000..163bc8ae21
--- /dev/null
+++ b/include/driver/accel_lis2dw12_public.h
@@ -0,0 +1,37 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* LIS2DW12 gsensor module for Chrome EC */
+
+#ifndef __CROS_EC_DRIVER_ACCEL_LIS2DW12_PUBLIC_H
+#define __CROS_EC_DRIVER_ACCEL_LIS2DW12_PUBLIC_H
+
+#include "config.h"
+#include "gpio_signal.h"
+
+extern const struct accelgyro_drv lis2dw12_drv;
+
+/* I2C ADDRESS DEFINITIONS
+ *
+ * 7-bit address is 011000Xb. Where 'X' is determined
+ * by the voltage on the ADDR pin.
+ */
+#define LIS2DW12_ADDR0 0x18
+#define LIS2DW12_ADDR1 0x19
+
+#define LIS2DWL_ADDR0_FLAGS 0x18
+#define LIS2DWL_ADDR1_FLAGS 0x19
+
+#define LIS2DW12_EN_BIT 0x01
+#define LIS2DW12_DIS_BIT 0x00
+
+/* Absolute Acc rate. */
+#define LIS2DW12_ODR_MIN_VAL 12500
+#define LIS2DW12_ODR_MAX_VAL \
+	MOTION_MAX_SENSOR_FREQUENCY(1600000, LIS2DW12_ODR_MIN_VAL)
+
+void lis2dw12_interrupt(enum gpio_signal signal);
+
+#endif /* __CROS_EC_DRIVER_ACCEL_LIS2DW12_PUBLIC_H */
diff --git a/include/driver/accelgyro_bmi160.h b/include/driver/accelgyro_bmi160.h
new file mode 100644
index 0000000000..8c6310e65b
--- /dev/null
+++ b/include/driver/accelgyro_bmi160.h
@@ -0,0 +1,408 @@
+/* Copyright 2015 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* BMI160 accelerometer and gyro and BMM150 compass module for Chrome EC */
+
+#ifndef __CROS_EC_ACCELGYRO_BMI160_H
+#define __CROS_EC_ACCELGYRO_BMI160_H
+
+#include "accelgyro.h"
+#include "driver/accelgyro_bmi160_public.h"
+#include "mag_bmm150.h"
+
+#define BMI160_CHIP_ID 0x00
+#define BMI160_CHIP_ID_MAJOR 0xd1
+#define BMI168_CHIP_ID_MAJOR 0xd2
+
+#define BMI160_SPEC_ACC_STARTUP_TIME_MS 10
+#define BMI160_SPEC_GYR_STARTUP_TIME_MS 80
+#define BMI160_SPEC_MAG_STARTUP_TIME_MS 60
+
+#define BMI160_ERR_REG 0x02
+#define BMI160_PMU_STATUS 0x03
+#define BMI160_PMU_MAG_OFFSET 0
+#define BMI160_PMU_GYR_OFFSET 2
+#define BMI160_PMU_ACC_OFFSET 4
+#define BMI160_PMU_SENSOR_STATUS(_sensor_type, _val) \
+	(((_val) >> (4 - 2 * (_sensor_type))) & 0x3)
+#define BMI160_PMU_SUSPEND 0
+#define BMI160_PMU_NORMAL 1
+#define BMI160_PMU_LOW_POWER 2
+#define BMI160_PMU_FAST_STARTUP 3
+
+#define BMI160_MAG_X_L_G 0x04
+#define BMI160_MAG_X_H_G 0x05
+#define BMI160_MAG_Y_L_G 0x06
+#define BMI160_MAG_Y_H_G 0x07
+#define BMI160_MAG_Z_L_G 0x08
+#define BMI160_MAG_Z_H_G 0x09
+#define BMI160_RHALL_L_G 0x0a
+#define BMI160_RHALL_H_G 0x0b
+#define BMI160_GYR_X_L_G 0x0c
+#define BMI160_GYR_X_H_G 0x0d
+#define BMI160_GYR_Y_L_G 0x0e
+#define BMI160_GYR_Y_H_G 0x0f
+#define BMI160_GYR_Z_L_G 0x10
+#define BMI160_GYR_Z_H_G 0x11
+#define BMI160_ACC_X_L_G 0x12
+#define BMI160_ACC_X_H_G 0x13
+#define BMI160_ACC_Y_L_G 0x14
+#define BMI160_ACC_Y_H_G 0x15
+#define BMI160_ACC_Z_L_G 0x16
+#define BMI160_ACC_Z_H_G 0x17
+
+#define BMI160_SENSORTIME_0 0x18
+#define BMI160_SENSORTIME_1 0x19
+#define BMI160_SENSORTIME_2 0x1a
+
+#define BMI160_STATUS 0x1b
+#define BMI160_POR_DETECTED BIT(0)
+#define BMI160_GYR_SLF_TST BIT(1)
+#define BMI160_MAG_MAN_OP BIT(2)
+#define BMI160_FOC_RDY BIT(3)
+#define BMI160_NVM_RDY BIT(4)
+#define BMI160_DRDY_MAG BIT(5)
+#define BMI160_DRDY_GYR BIT(6)
+#define BMI160_DRDY_ACC BIT(7)
+#define BMI160_DRDY_OFF(_sensor) (7 - (_sensor))
+#define BMI160_DRDY_MASK(_sensor) (1 << BMI160_DRDY_OFF(_sensor))
+
+/* first 2 bytes are the interrupt reasons, next 2 some qualifier */
+#define BMI160_INT_STATUS_0 0x1c
+#define BMI160_STEP_INT BIT(0)
+#define BMI160_SIGMOT_INT BIT(1)
+#define BMI160_ANYM_INT BIT(2)
+#define BMI160_PMU_TRIGGER_INT BIT(3)
+#define BMI160_D_TAP_INT BIT(4)
+#define BMI160_S_TAP_INT BIT(5)
+#define BMI160_ORIENT_INT BIT(6)
+#define BMI160_FLAT_INT BIT(7)
+#define BMI160_ORIENT_XY_MASK 0x30
+#define BMI160_ORIENT_PORTRAIT (0 << 4)
+#define BMI160_ORIENT_PORTRAIT_INVERT BIT(4)
+#define BMI160_ORIENT_LANDSCAPE (2 << 4)
+#define BMI160_ORIENT_LANDSCAPE_INVERT (3 << 4)
+
+#define BMI160_INT_STATUS_1 0x1d
+#define BMI160_HIGHG_INT (1 << (2 + 8))
+#define BMI160_LOWG_INT (1 << (3 + 8))
+#define BMI160_DRDY_INT (1 << (4 + 8))
+#define BMI160_FFULL_INT (1 << (5 + 8))
+#define BMI160_FWM_INT (1 << (6 + 8))
+#define BMI160_NOMO_INT (1 << (7 + 8))
+
+#define BMI160_INT_MASK 0xFFFF
+
+#define BMI160_INT_STATUS_2 0x1e
+#define BMI160_INT_STATUS_3 0x1f
+#define BMI160_FIRST_X (1 << (0 + 16))
+#define BMI160_FIRST_Y (1 << (1 + 16))
+#define BMI160_FIRST_Z (1 << (2 + 16))
+#define BMI160_SIGN (1 << (3 + 16))
+#define BMI160_ANYM_OFFSET 0
+#define BMI160_TAP_OFFSET 4
+#define BMI160_HIGH_OFFSET 8
+#define BMI160_INT_INFO(_type, _data) \
+	(CONCAT2(BMI160_, _data) << CONCAT3(BMI160_, _type, _OFFSET))
+
+#define BMI160_ORIENT_Z (1 << (6 + 24))
+#define BMI160_FLAT (1 << (7 + 24))
+
+#define BMI160_TEMPERATURE_0 0x20
+#define BMI160_TEMPERATURE_1 0x21
+
+#define BMI160_FIFO_LENGTH_0 0x22
+#define BMI160_FIFO_LENGTH_1 0x23
+#define BMI160_FIFO_LENGTH_MASK (BIT(11) - 1)
+#define BMI160_FIFO_DATA 0x24
+
+#define BMI160_ACC_CONF 0x40
+#define BMI160_ACC_BW_OFFSET 4
+#define BMI160_ACC_BW_MASK (0x7 << BMI160_ACC_BW_OFFSET)
+
+#define BMI160_ACC_RANGE 0x41
+#define BMI160_GSEL_2G 0x03
+#define BMI160_GSEL_4G 0x05
+#define BMI160_GSEL_8G 0x08
+#define BMI160_GSEL_16G 0x0c
+
+#define BMI160_GYR_CONF 0x42
+#define BMI160_GYR_BW_OFFSET 4
+#define BMI160_GYR_BW_MASK (0x3 << BMI160_GYR_BW_OFFSET)
+
+#define BMI160_GYR_RANGE 0x43
+#define BMI160_DPS_SEL_2000 0x00
+#define BMI160_DPS_SEL_1000 0x01
+#define BMI160_DPS_SEL_500 0x02
+#define BMI160_DPS_SEL_250 0x03
+#define BMI160_DPS_SEL_125 0x04
+
+#define BMI160_MAG_CONF 0x44
+
+#define BMI160_FIFO_DOWNS 0x45
+#define BMI160_FIFO_CONFIG_0 0x46
+#define BMI160_FIFO_CONFIG_1 0x47
+#define BMI160_FIFO_TAG_TIME_EN BIT(1)
+#define BMI160_FIFO_TAG_INT2_EN BIT(2)
+#define BMI160_FIFO_TAG_INT1_EN BIT(3)
+#define BMI160_FIFO_HEADER_EN BIT(4)
+#define BMI160_FIFO_MAG_EN BIT(5)
+#define BMI160_FIFO_ACC_EN BIT(6)
+#define BMI160_FIFO_GYR_EN BIT(7)
+#define BMI160_FIFO_TARG_INT(_i) CONCAT3(BMI160_FIFO_TAG_INT, _i, _EN)
+#define BMI160_FIFO_SENSOR_EN(_sensor)                                      \
+	((_sensor) == MOTIONSENSE_TYPE_ACCEL ?                              \
+		 BMI160_FIFO_ACC_EN :                                       \
+		 ((_sensor) == MOTIONSENSE_TYPE_GYRO ? BMI160_FIFO_GYR_EN : \
+						       BMI160_FIFO_MAG_EN))
+
+#define BMI160_MAG_IF_0 0x4b
+#define BMI160_MAG_I2C_ADDRESS BMI160_MAG_IF_0
+#define BMI160_MAG_IF_1 0x4c
+#define BMI160_MAG_I2C_CONTROL BMI160_MAG_IF_1
+#define BMI160_MAG_READ_BURST_MASK 3
+#define BMI160_MAG_READ_BURST_1 0
+#define BMI160_MAG_READ_BURST_2 1
+#define BMI160_MAG_READ_BURST_6 2
+#define BMI160_MAG_READ_BURST_8 3
+#define BMI160_MAG_OFFSET_OFF 3
+#define BMI160_MAG_OFFSET_MASK (0xf << BMI160_MAG_OFFSET_OFF)
+#define BMI160_MAG_MANUAL_EN BIT(7)
+
+#define BMI160_MAG_IF_2 0x4d
+#define BMI160_MAG_I2C_READ_ADDR BMI160_MAG_IF_2
+#define BMI160_MAG_IF_3 0x4e
+#define BMI160_MAG_I2C_WRITE_ADDR BMI160_MAG_IF_3
+#define BMI160_MAG_IF_4 0x4f
+#define BMI160_MAG_I2C_WRITE_DATA BMI160_MAG_IF_4
+#define BMI160_MAG_I2C_READ_DATA BMI160_MAG_X_L_G
+
+#define BMI160_INT_EN_0 0x50
+#define BMI160_INT_ANYMO_X_EN BIT(0)
+#define BMI160_INT_ANYMO_Y_EN BIT(1)
+#define BMI160_INT_ANYMO_Z_EN BIT(2)
+#define BMI160_INT_D_TAP_EN BIT(4)
+#define BMI160_INT_S_TAP_EN BIT(5)
+#define BMI160_INT_ORIENT_EN BIT(6)
+#define BMI160_INT_FLAT_EN BIT(7)
+#define BMI160_INT_EN_1 0x51
+#define BMI160_INT_HIGHG_X_EN BIT(0)
+#define BMI160_INT_HIGHG_Y_EN BIT(1)
+#define BMI160_INT_HIGHG_Z_EN BIT(2)
+#define BMI160_INT_LOW_EN BIT(3)
+#define BMI160_INT_DRDY_EN BIT(4)
+#define BMI160_INT_FFUL_EN BIT(5)
+#define BMI160_INT_FWM_EN BIT(6)
+#define BMI160_INT_EN_2 0x52
+#define BMI160_INT_NOMOX_EN BIT(0)
+#define BMI160_INT_NOMOY_EN BIT(1)
+#define BMI160_INT_NOMOZ_EN BIT(2)
+#define BMI160_INT_STEP_DET_EN BIT(3)
+
+#define BMI160_INT_OUT_CTRL 0x53
+#define BMI160_INT_EDGE_CTRL BIT(0)
+#define BMI160_INT_LVL_CTRL BIT(1)
+#define BMI160_INT_OD BIT(2)
+#define BMI160_INT_OUTPUT_EN BIT(3)
+#define BMI160_INT1_CTRL_OFFSET 0
+#define BMI160_INT2_CTRL_OFFSET 4
+#define BMI160_INT_CTRL(_i, _bit) \
+	(CONCAT2(BMI160_INT_, _bit) << CONCAT3(BMI160_INT, _i, _CTRL_OFFSET))
+
+#define BMI160_INT_LATCH 0x54
+#define BMI160_INT1_INPUT_EN BIT(4)
+#define BMI160_INT2_INPUT_EN BIT(5)
+#define BMI160_LATCH_MASK 0xf
+#define BMI160_LATCH_NONE 0
+#define BMI160_LATCH_5MS 5
+#define BMI160_LATCH_FOREVER 0xf
+
+#define BMI160_INT_MAP_0 0x55
+#define BMI160_INT_LOWG_STEP BIT(0)
+#define BMI160_INT_HIGHG BIT(1)
+#define BMI160_INT_ANYMOTION BIT(2)
+#define BMI160_INT_NOMOTION BIT(3)
+#define BMI160_INT_D_TAP BIT(4)
+#define BMI160_INT_S_TAP BIT(5)
+#define BMI160_INT_ORIENT BIT(6)
+#define BMI160_INT_FLAT BIT(7)
+
+#define BMI160_INT_MAP_1 0x56
+#define BMI160_INT_PMU_TRIG BIT(0)
+#define BMI160_INT_FFULL BIT(1)
+#define BMI160_INT_FWM BIT(2)
+#define BMI160_INT_DRDY BIT(3)
+#define BMI160_INT1_MAP_OFFSET 4
+#define BMI160_INT2_MAP_OFFSET 0
+#define BMI160_INT_MAP(_i, _bit) \
+	(CONCAT2(BMI160_INT_, _bit) << CONCAT3(BMI160_INT, _i, _MAP_OFFSET))
+#define BMI160_INT_FIFO_MAP BMI160_INT_MAP_1
+
+#define BMI160_INT_MAP_2 0x57
+
+#define BMI160_INT_MAP_INT_1 BMI160_INT_MAP_0
+#define BMI160_INT_MAP_INT_2 BMI160_INT_MAP_2
+#define BMI160_INT_MAP_REG(_i) CONCAT2(BMI160_INT_MAP_INT_, _i)
+
+#define BMI160_INT_DATA_0 0x58
+#define BMI160_INT_DATA_1 0x59
+
+#define BMI160_INT_LOW_HIGH_0 0x5a
+#define BMI160_INT_LOW_HIGH_1 0x5b
+#define BMI160_INT_LOW_HIGH_2 0x5c
+#define BMI160_INT_LOW_HIGH_3 0x5d
+#define BMI160_INT_LOW_HIGH_4 0x5e
+
+#define BMI160_INT_MOTION_0 0x5f
+#define BMI160_INT_MOTION_1 0x60
+/*
+ * The formula is defined in 2.11.25 (any motion interrupt [1]).
+ *
+ * if we want threshold at a (in mg), the register should be x, where
+ * x * 7.81mg = a, assuming a range of 4G, which is
+ * x * 4 * 1.953 = a so
+ * x = a * 1000 / range * 1953
+ */
+#define BMI160_MOTION_TH(_s, _mg) \
+	(MIN(((_mg)*1000) / ((_s)->current_range * 1953), 0xff))
+#define BMI160_INT_MOTION_2 0x61
+#define BMI160_INT_MOTION_3 0x62
+#define BMI160_MOTION_NO_MOT_SEL BIT(0)
+#define BMI160_MOTION_SIG_MOT_SEL BIT(1)
+#define BMI160_MOTION_SKIP_OFF 2
+#define BMI160_MOTION_SKIP_MASK 0x3
+#define BMI160_MOTION_SKIP_TIME(_ms) \
+	(MIN(__fls((_ms) / 1500), BMI160_MOTION_SKIP_MASK))
+#define BMI160_MOTION_PROOF_OFF 4
+#define BMI160_MOTION_PROOF_MASK 0x3
+#define BMI160_MOTION_PROOF_TIME(_ms) \
+	(MIN(__fls((_ms) / 250), BMI160_MOTION_PROOF_MASK))
+
+#define BMI160_INT_TAP_0 0x63
+#define BMI160_TAP_DUR(_s, _ms)                   \
+	((_ms) <= 250 ? MAX((_ms), 50) / 50 - 1 : \
+	 (_ms) <= 500 ? 4 + ((_ms)-250) / 125 :   \
+	 (_ms) < 700  ? 6 :                       \
+			7)
+
+#define BMI160_INT_TAP_1 0x64
+#define BMI160_TAP_TH(_s, _mg) \
+	(MIN(((_mg)*1000) / ((_s)->current_range * 31250), 0x1f))
+
+#define BMI160_INT_ORIENT_0 0x65
+
+/* No hysterisis, theta block, int on slope > 0.2 or axis > 1.5, symmetrical */
+#define BMI160_INT_ORIENT_0_INIT_VAL 0x48
+
+#define BMI160_INT_ORIENT_1 0x66
+
+/* no axes remap, no int on up/down, no blocking angle */
+#define BMI160_INT_ORIENT_1_INIT_VAL 0x00
+
+#define BMI160_INT_FLAT_0 0x67
+#define BMI160_INT_FLAT_1 0x68
+
+#define BMI160_FOC_CONF 0x69
+#define BMI160_FOC_GYRO_EN BIT(6)
+#define BMI160_FOC_ACC_PLUS_1G 1
+#define BMI160_FOC_ACC_MINUS_1G 2
+#define BMI160_FOC_ACC_0G 3
+#define BMI160_FOC_ACC_Z_OFFSET 0
+#define BMI160_FOC_ACC_Y_OFFSET 2
+#define BMI160_FOC_ACC_X_OFFSET 4
+
+#define BMI160_CONF 0x6a
+#define BMI160_IF_CONF 0x6b
+#define BMI160_IF_MODE_OFF 4
+#define BMI160_IF_MODE_MASK 3
+#define BMI160_IF_MODE_AUTO_OFF 0
+#define BMI160_IF_MODE_I2C_IOS 1
+#define BMI160_IF_MODE_AUTO_I2C 2
+
+#define BMI160_PMU_TRIGGER 0x6c
+#define BMI160_SELF_TEST 0x6d
+
+#define BMI160_NV_CONF 0x70
+
+#define BMI160_OFFSET_ACC70 0x71
+#define BMI160_OFFSET_GYR70 0x74
+#define BMI160_OFFSET_EN_GYR98 0x77
+#define BMI160_OFFSET_ACC_EN BIT(6)
+#define BMI160_OFFSET_GYRO_EN BIT(7)
+
+#define BMI160_STEP_CNT_0 0x78
+#define BMI160_STEP_CNT_1 0x79
+#define BMI160_STEP_CONF_0 0x7a
+#define BMI160_STEP_CONF_1 0x7b
+
+#define BMI160_CMD_REG 0x7e
+#define BMI160_CMD_SOFT_RESET 0xb6
+#define BMI160_CMD_NOOP 0x00
+#define BMI160_CMD_START_FOC 0x03
+#define BMI160_CMD_ACC_MODE_OFFSET 0x10
+#define BMI160_CMD_ACC_MODE_SUSP 0x10
+#define BMI160_CMD_ACC_MODE_NORMAL 0x11
+#define BMI160_CMD_ACC_MODE_LOWPOWER 0x12
+#define BMI160_CMD_GYR_MODE_SUSP 0x14
+#define BMI160_CMD_GYR_MODE_NORMAL 0x15
+#define BMI160_CMD_GYR_MODE_FAST_STARTUP 0x17
+#define BMI160_CMD_MAG_MODE_SUSP 0x18
+#define BMI160_CMD_MAG_MODE_NORMAL 0x19
+#define BMI160_CMD_MAG_MODE_LOWPOWER 0x1a
+#define BMI160_CMD_MODE_SUSPEND(_sensor_type) \
+	(BMI160_CMD_ACC_MODE_OFFSET | (_sensor_type) << 2 | BMI160_PMU_SUSPEND)
+#define BMI160_CMD_MODE_NORMAL(_sensor_type) \
+	(BMI160_CMD_ACC_MODE_OFFSET | (_sensor_type) << 2 | BMI160_PMU_NORMAL)
+
+#define BMI160_CMD_FIFO_FLUSH 0xb0
+#define BMI160_CMD_INT_RESET 0xb1
+#define BMI160_CMD_SOFT_RESET 0xb6
+#define BMI160_CMD_EXT_MODE_EN_B0 0x37
+#define BMI160_CMD_EXT_MODE_EN_B1 0x9a
+#define BMI160_CMD_EXT_MODE_EN_B2 0xc0
+
+#define BMI160_CMD_EXT_MODE_ADDR 0x7f
+#define BMI160_CMD_PAGING_EN BIT(7)
+#define BMI160_CMD_TARGET_PAGE BIT(4)
+#define BMI160_COM_C_TRIM_ADDR 0x85
+#define BMI160_COM_C_TRIM (3 << 4)
+
+#define BMI160_CMD_TGT_PAGE 0
+#define BMI160_CMD_TGT_PAGE_COM 1
+#define BMI160_CMD_TGT_PAGE_ACC 2
+#define BMI160_CMD_TGT_PAGE_GYR 3
+
+#define BMI160_FF_FRAME_LEN_TS 4
+#define BMI160_FF_DATA_LEN_ACC 6
+#define BMI160_FF_DATA_LEN_GYR 6
+#define BMI160_FF_DATA_LEN_MAG 8
+
+/* Root mean square noise of 100 Hz accelerometer, units: ug */
+#define BMI160_ACCEL_RMS_NOISE_100HZ 1300
+
+/* Functions to access the secondary device through the accel/gyro. */
+int bmi160_sec_raw_read8(const int port, const uint16_t addr_flags,
+			 const uint8_t reg, int *data_ptr);
+int bmi160_sec_raw_write8(const int port, const uint16_t addr_flags,
+			  const uint8_t reg, int data);
+
+#if defined(CONFIG_ZEPHYR)
+#if DT_NODE_EXISTS(DT_ALIAS(bmi160_int))
+/* Get the motion sensor ID of the BMI160 sensor that generates the interrupt.
+ * The interrupt is converted to the event and transferred to motion sense task
+ * that actually handles the interrupt.
+ *
+ * Here we use an alias (bmi160_int) to get the motion sensor ID. This alias
+ * MUST be defined for this driver to work.
+ * aliases {
+ *   bmi160-int = &base_accel;
+ * };
+ */
+#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(SENSOR_ID(DT_ALIAS(bmi160_int)))
+#endif
+#endif /* CONFIG_ZEPHYR */
+
+#endif /* __CROS_EC_ACCELGYRO_BMI160_H */
diff --git a/include/driver/accelgyro_bmi160_public.h b/include/driver/accelgyro_bmi160_public.h
new file mode 100644
index 0000000000..551e351fea
--- /dev/null
+++ b/include/driver/accelgyro_bmi160_public.h
@@ -0,0 +1,32 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* BMI160 accelerometer and gyro for Chrome EC */
+
+#ifndef __CROS_EC_DRIVER_ACCELGYRO_BMI160_PUBLIC_H
+#define __CROS_EC_DRIVER_ACCELGYRO_BMI160_PUBLIC_H
+
+/*
+ * The addr field of motion_sensor support both SPI and I2C:
+ * This is defined in include/i2c.h and is no longer an 8bit
+ * address. The 7/10 bit address starts at bit 0 and leaves
+ * room for a 10 bit address, although we don't currently
+ * have any 10 bit peripherals. I2C or SPI is indicated by a
+ * more significant bit
+ */
+
+/* I2C addresses */
+#define BMI160_ADDR0_FLAGS 0x68
+
+extern const struct accelgyro_drv bmi160_drv;
+
+void bmi160_interrupt(enum gpio_signal signal);
+int bmi160_get_sensor_temp(int idx, int *temp_ptr);
+
+#ifdef CONFIG_CMD_I2C_STRESS_TEST_ACCEL
+extern struct i2c_stress_test_dev bmi160_i2c_stress_test_dev;
+#endif
+
+#endif /* __CROS_EC_DRIVER_ACCELGYRO_BMI260_PUBLIC_H */
diff --git a/include/driver/accelgyro_bmi260.h b/include/driver/accelgyro_bmi260.h
new file mode 100644
index 0000000000..baf78e9e00
--- /dev/null
+++ b/include/driver/accelgyro_bmi260.h
@@ -0,0 +1,351 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* BMI260 accelerometer and gyro for Chrome EC */
+
+#ifndef __CROS_EC_ACCELGYRO_BMI260_H
+#define __CROS_EC_ACCELGYRO_BMI260_H
+
+#include "accelgyro.h"
+#include "common.h"
+#include "driver/accelgyro_bmi260_public.h"
+#include "mag_bmm150.h"
+
+#define BMI260_CHIP_ID 0x00
+/* BMI260 chip identifier */
+#define BMI260_CHIP_ID_MAJOR 0x27
+/* BMI220 chip identifier */
+#define BMI220_CHIP_ID_MAJOR 0x26
+
+#define BMI260_ERR_REG 0x02
+
+#define BMI260_STATUS 0x03
+#define BMI260_AUX_BUSY BIT(2)
+#define BMI260_CMD_RDY BIT(4)
+#define BMI260_DRDY_AUX BIT(5)
+#define BMI260_DRDY_GYR BIT(6)
+#define BMI260_DRDY_ACC BIT(7)
+#define BMI260_DRDY_OFF(_sensor) (7 - (_sensor))
+#define BMI260_DRDY_MASK(_sensor) (1 << BMI260_DRDY_OFF(_sensor))
+
+#define BMI260_AUX_X_L_G 0x04
+#define BMI260_AUX_X_H_G 0x05
+#define BMI260_AUX_Y_L_G 0x06
+#define BMI260_AUX_Y_H_G 0x07
+#define BMI260_AUX_Z_L_G 0x08
+#define BMI260_AUX_Z_H_G 0x09
+#define BMI260_AUX_R_L_G 0x0a
+#define BMI260_AUX_R_H_G 0x0b
+#define BMI260_ACC_X_L_G 0x0c
+#define BMI260_ACC_X_H_G 0x0d
+#define BMI260_ACC_Y_L_G 0x0e
+#define BMI260_ACC_Y_H_G 0x0f
+#define BMI260_ACC_Z_L_G 0x10
+#define BMI260_ACC_Z_H_G 0x11
+#define BMI260_GYR_X_L_G 0x12
+#define BMI260_GYR_X_H_G 0x13
+#define BMI260_GYR_Y_L_G 0x14
+#define BMI260_GYR_Y_H_G 0x15
+#define BMI260_GYR_Z_L_G 0x16
+#define BMI260_GYR_Z_H_G 0x17
+
+#define BMI260_SENSORTIME_0 0x18
+#define BMI260_SENSORTIME_1 0x19
+#define BMI260_SENSORTIME_2 0x1a
+
+#define BMI260_EVENT 0x1b
+
+/* 2 bytes interrupt reasons*/
+#define BMI260_INT_STATUS_0 0x1c
+#define BMI260_SIG_MOTION_OUT BIT(0)
+#define BMI260_STEP_COUNTER_OUT BIT(1)
+#define BMI260_HIGH_LOW_G_OUT BIT(2)
+#define BMI260_TAP_OUT BIT(3)
+#define BMI260_FLAT_OUT BIT(4)
+#define BMI260_NO_MOTION_OUT BIT(5)
+#define BMI260_ANY_MOTION_OUT BIT(6)
+#define BMI260_ORIENTATION_OUT BIT(7)
+
+#define BMI260_INT_STATUS_1 0x1d
+#define BMI260_FFULL_INT BIT(0 + 8)
+#define BMI260_FWM_INT BIT(1 + 8)
+#define BMI260_ERR_INT BIT(2 + 8)
+#define BMI260_AUX_DRDY_INT BIT(5 + 8)
+#define BMI260_GYR_DRDY_INT BIT(6 + 8)
+#define BMI260_ACC_DRDY_INT BIT(7 + 8)
+
+#define BMI260_INT_MASK 0xFFFF
+
+#define BMI260_SC_OUT_0 0x1e
+#define BMI260_SC_OUT_1 0x1f
+
+#define BMI260_ORIENT_ACT 0x20
+
+#define BMI260_INTERNAL_STATUS 0X21
+#define BMI260_MESSAGE_MASK 0xf
+#define BMI260_NOT_INIT 0x00
+#define BMI260_INIT_OK 0x01
+#define BMI260_INIT_ERR 0x02
+#define BMI260_DRV_ERR 0x03
+#define BMI260_SNS_STOP 0x04
+#define BMI260_NVM_ERROR 0x05
+#define BMI260_START_UP_ERROR 0x06
+#define BMI260_COMPAT_ERROR 0x07
+
+#define BMI260_TEMPERATURE_0 0x22
+#define BMI260_TEMPERATURE_1 0x23
+
+#define BMI260_FIFO_LENGTH_0 0x24
+#define BMI260_FIFO_LENGTH_1 0x25
+#define BMI260_FIFO_LENGTH_MASK (BIT(14) - 1)
+#define BMI260_FIFO_DATA 0x26
+
+#define BMI260_FEAT_PAGE 0x2f
+/*
+ * The register of feature page should be read/write as 16-bit register
+ * Otherwise, there can be invalid data
+ */
+/* Features page 0 */
+#define BMI260_ORIENT_OUT 0x36
+#define BMI260_ORIENT_OUT_PORTRAIT_LANDSCAPE_MASK 3
+#define BMI260_ORIENT_PORTRAIT 0x0
+#define BMI260_ORIENT_LANDSCAPE 0x1
+#define BMI260_ORIENT_PORTRAIT_INVERT 0x2
+#define BMI260_ORIENT_LANDSCAPE_INVERT 0x3
+
+/* Features page 1 */
+#define BMI260_GEN_SET_1 0x34
+#define BMI260_GYR_SELF_OFF BIT(9)
+
+#define BMI260_TAP_1 0x3e
+#define BMI260_TAP_1_EN BIT(0)
+#define BMI260_TAP_1_SENSITIVITY_OFFSET 1
+#define BMI260_TAP_1_SENSITIVITY_MASK (0x7 << BMI260_TAP_1_SENSITIVITY_OFFSET)
+
+/* Features page 2 */
+#define BMI260_ORIENT_1 0x30
+#define BMI260_ORIENT_1_EN BIT(0)
+#define BMI260_ORIENT_1_UD_EN BIT(1)
+#define BMI260_ORIENT_1_MODE_OFFSET 2
+#define BMI260_ORIENT_1_MODE_MASK (0x3 << BMI260_ORIENT_1_MODE_OFFSET)
+#define BMI260_ORIENT_1_BLOCK_OFFSET 4
+#define BMI260_ORIENT_1_BLOCK_MASK (0x3 << BMI260_ORIENT_1_BLOCK_OFFSET)
+#define BMI260_ORIENT_1_THETA_OFFSET 6
+#define BMI260_ORIENT_1_THETA_MASK \
+	((BIT(6) - 1) << BMI260_ORIENT_1_THETA_OFFSET)
+
+#define BMI260_ORIENT_2 0x32
+/* hysteresis(10...0) range is 0~1g, default is 128 (0.0625g) */
+#define BMI260_ORIENT_2_HYSTERESIS_MASK (BIT(11) - 1)
+
+#define BMI260_ACC_CONF 0x40
+#define BMI260_ACC_BW_OFFSET 4
+#define BMI260_ACC_BW_MASK (0x7 << BMI260_ACC_BW_OFFSET)
+#define BMI260_FILTER_PERF BIT(7)
+#define BMI260_ULP 0x0
+#define BMI260_HP 0x1
+
+#define BMI260_ACC_RANGE 0x41
+#define BMI260_GSEL_2G 0x00
+#define BMI260_GSEL_4G 0x01
+#define BMI260_GSEL_8G 0x02
+#define BMI260_GSEL_16G 0x03
+
+/* The max positvie value of accel data is 0x7FFF, equal to range(g) */
+/* So, in order to get +1g, divide the 0x7FFF by range */
+#define BMI260_ACC_DATA_PLUS_1G(range) (0x7FFF / (range))
+#define BMI260_ACC_DATA_MINUS_1G(range) (-BMI260_ACC_DATA_PLUS_1G(range))
+
+#define BMI260_GYR_CONF 0x42
+#define BMI260_GYR_BW_OFFSET 4
+#define BMI260_GYR_BW_MASK (0x3 << BMI260_GYR_BW_OFFSET)
+#define BMI260_GYR_NOISE_PERF BIT(6)
+
+#define BMI260_GYR_RANGE 0x43
+#define BMI260_DPS_SEL_2000 0x00
+#define BMI260_DPS_SEL_1000 0x01
+#define BMI260_DPS_SEL_500 0x02
+#define BMI260_DPS_SEL_250 0x03
+#define BMI260_DPS_SEL_125 0x04
+
+#define BMI260_AUX_CONF 0x44
+
+#define BMI260_FIFO_DOWNS 0x45
+
+#define BMI260_FIFO_WTM_0 0x46
+#define BMI260_FIFO_WTM_1 0x47
+
+#define BMI260_FIFO_CONFIG_0 0x48
+#define BMI260_FIFO_STOP_ON_FULL BIT(0)
+#define BMI260_FIFO_TIME_EN BIT(1)
+
+#define BMI260_FIFO_CONFIG_1 0x49
+#define BMI260_FIFO_TAG_INT1_EN_OFFSET 0
+#define BMI260_FIFO_TAG_INT1_EN_MASK (0x3 << BMI260_FIFO_TAG_INT1_EN_OFFSET)
+#define BMI260_FIFO_TAG_INT2_EN_OFFSET 2
+#define BMI260_FIFO_TAG_INT2_EN_MASK (0x3 << BMI260_FIFO_TAG_INT2_EN_OFFSET)
+#define BMI260_FIFO_TAG_INT_EDGE 0x0
+#define BMI260_FIFO_TAG_INT_LEVEL 0x1
+#define BMI260_FIFO_TAG_ACC_SAT 0x2
+#define BMI260_FIFO_TAG_GYR_SAT 0x3
+#define BMI260_FIFO_HEADER_EN BIT(4)
+#define BMI260_FIFO_AUX_EN BIT(5)
+#define BMI260_FIFO_ACC_EN BIT(6)
+#define BMI260_FIFO_GYR_EN BIT(7)
+#define BMI260_FIFO_SENSOR_EN(_sensor)                                      \
+	((_sensor) == MOTIONSENSE_TYPE_ACCEL ?                              \
+		 BMI260_FIFO_ACC_EN :                                       \
+		 ((_sensor) == MOTIONSENSE_TYPE_GYRO ? BMI260_FIFO_GYR_EN : \
+						       BMI260_FIFO_AUX_EN))
+
+#define BMI260_SATURATION 0x4a
+
+#define BMI260_AUX_DEV_ID 0x4b
+#define BMI260_AUX_I2C_ADDRESS BMI260_AUX_DEV_ID
+
+#define BMI260_AUX_IF_CONF 0x4c
+#define BMI260_AUX_I2C_CONTROL BMI260_AUX_IF_CONF
+#define BMI260_AUX_READ_BURST_MASK 3
+#define BMI260_AUX_MAN_READ_BURST_OFF 2
+#define BMI260_AUX_MAN_READ_BURST_MASK (0x3 << BMI280_AUX_MAN_READ_BURST_OFF)
+#define BMI260_AUX_READ_BURST_1 0
+#define BMI260_AUX_READ_BURST_2 1
+#define BMI260_AUX_READ_BURST_6 2
+#define BMI260_AUX_READ_BURST_8 3
+#define BMI260_AUX_FCU_WRITE_EN BIT(6)
+#define BMI260_AUX_MANUAL_EN BIT(7)
+
+#define BMI260_AUX_RD_ADDR 0x4d
+#define BMI260_AUX_I2C_READ_ADDR BMI260_AUX_RD_ADDR
+#define BMI260_AUX_WR_ADDR 0x4e
+#define BMI260_AUX_I2C_WRITE_ADDR BMI260_AUX_WR_ADDR
+#define BMI260_AUX_WR_DATA 0x4f
+#define BMI260_AUX_I2C_WRITE_DATA BMI260_AUX_WR_DATA
+#define BMI260_AUX_I2C_READ_DATA BMI260_AUX_X_L_G
+
+#define BMI260_ERR_REG_MSK 0x52
+#define BMI260_FATAL_ERR BIT(0)
+#define BMI260_INTERNAL_ERR_OFF 1
+#define BMI260_INTERNAL_ERR_MASK (0xf << BMI260_INTERNAL_ERR_OFF)
+#define BMI260_FIFO_ERR BIT(6)
+#define BMI260_AUX_ERR BIT(7)
+
+#define BMI260_INT1_IO_CTRL 0x53
+#define BMI260_INT1_LVL BIT(1)
+#define BMI260_INT1_OD BIT(2)
+#define BMI260_INT1_OUTPUT_EN BIT(3)
+#define BMI260_INT1_INPUT_EN BIT(4)
+
+#define BMI260_INT2_IO_CTRL 0x54
+#define BMI260_INT2_LVL BIT(1)
+#define BMI260_INT2_OD BIT(2)
+#define BMI260_INT2_OUTPUT_EN BIT(3)
+#define BMI260_INT2_INPUT_EN BIT(4)
+
+#define BMI260_INT_LATCH 0x55
+#define BMI260_INT_LATCH_EN BIT(0)
+
+#define BMI260_INT1_MAP_FEAT 0x56
+#define BMI260_INT2_MAP_FEAT 0x57
+#define BMI260_MAP_SIG_MOTION_OUT BIT(0)
+#define BMI260_MAP_STEP_COUNTER_OUT BIT(1)
+#define BMI260_MAP_HIGH_LOW_G_OUT BIT(2)
+#define BMI260_MAP_TAP_OUT BIT(3)
+#define BMI260_MAP_FLAT_OUT BIT(4)
+#define BMI260_MAP_NO_MOTION_OUT BIT(5)
+#define BMI260_MAP_ANY_MOTION_OUT BIT(6)
+#define BMI260_MAP_ORIENTAION_OUT BIT(7)
+
+#define BMI260_INT_MAP_DATA 0x58
+#define BMI260_MAP_FFULL_INT BIT(0)
+#define BMI260_MAP_FWM_INT BIT(1)
+#define BMI260_MAP_DRDY_INT BIT(2)
+#define BMI260_MAP_ERR_INT BIT(3)
+#define BMI260_INT_MAP_DATA_INT1_OFFSET 0
+#define BMI260_INT_MAP_DATA_INT2_OFFSET 4
+#define BMI260_INT_MAP_DATA_REG(_i, _bit) \
+	(CONCAT3(BMI260_MAP_, _bit, _INT) \
+	 << CONCAT3(BMI260_INT_MAP_DATA_INT, _i, _OFFSET))
+
+#define BMI260_INIT_CTRL 0x59
+#define BMI260_INIT_ADDR_0 0x5b
+#define BMI260_INIT_ADDR_1 0x5c
+#define BMI260_INIT_DATA 0x5e
+#define BMI260_INTERNAL_ERROR 0x5f
+#define BMI260_INT_ERR_1 BIT(1)
+#define BMI260_INT_ERR_2 BIT(2)
+#define BMI260_FEAT_ENG_DISABLED BIT(4)
+
+#define BMI260_AUX_IF_TRIM 0x68
+#define BMI260_GYR_CRT_CONF 0x69
+
+#define BMI260_NVM_CONF 0x6a
+#define BMI260_NVM_PROG_EN BIT(1)
+
+#define BMI260_IF_CONF 0x6b
+#define BMI260_IF_SPI3 BIT(0)
+#define BMI260_IF_SPI3_OIS BIT(1)
+#define BMI260_IF_OIS_EN BIT(4)
+#define BMI260_IF_AUX_EN BIT(5)
+
+#define BMI260_DRV 0x6c
+#define BMI260_ACC_SELF_TEST 0x6d
+
+#define BMI260_GYR_SELF_TEST_AXES 0x6e
+
+#define BMI260_NV_CONF 0x70
+#define BMI260_ACC_OFFSET_EN BIT(3)
+
+#define BMI260_OFFSET_ACC70 0x71
+#define BMI260_OFFSET_GYR70 0x74
+#define BMI260_OFFSET_EN_GYR98 0x77
+#define BMI260_OFFSET_GYRO_EN BIT(6)
+#define BMI260_GYR_GAIN_EN BIT(7)
+
+#define BMI260_PWR_CONF 0x7c
+#define BMI260_ADV_POWER_SAVE BIT(0)
+#define BMI260_FIFO_SELF_WAKE_UP BIT(1)
+#define BMI260_FUP_EN BIT(2)
+
+#define BMI260_PWR_CTRL 0x7d
+#define BMI260_AUX_EN BIT(0)
+#define BMI260_GYR_EN BIT(1)
+#define BMI260_ACC_EN BIT(2)
+#define BMI260_PWR_EN(_sensor_type) BIT(2 - _sensor_type)
+#define BMI260_TEMP_EN BIT(3)
+
+#define BMI260_CMD_REG 0x7e
+#define BMI260_CMD_FIFO_FLUSH 0xb0
+#define BMI260_CMD_SOFT_RESET 0xb6
+
+#define BMI260_FF_FRAME_LEN_TS 4
+#define BMI260_FF_DATA_LEN_ACC 6
+#define BMI260_FF_DATA_LEN_GYR 6
+#define BMI260_FF_DATA_LEN_MAG 8
+
+/* Root mean square noise of 100Hz accelerometer, units: ug */
+#define BMI260_ACCEL_RMS_NOISE_100HZ 1060
+
+#if defined(CONFIG_ZEPHYR)
+#if DT_NODE_EXISTS(DT_ALIAS(bmi260_int))
+/*
+ * Get the motion sensor ID of the BMI260 sensor that
+ * generates the interrupt.
+ * The interrupt is converted to the event and transferred to motion
+ * sense task that actually handles the interrupt.
+ *
+ * Here, we use alias to get the motion sensor ID
+ *
+ * e.g) base_accel is the label of a child node in /motionsense-sensors
+ * aliases {
+ *     bmi260-int = &base_accel;
+ * };
+ */
+#define CONFIG_ACCELGYRO_BMI260_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(SENSOR_ID(DT_ALIAS(bmi260_int)))
+#endif
+#endif /* CONFIG_ZEPHYR */
+
+#endif /* __CROS_EC_ACCELGYRO_BMI260_H */
diff --git a/include/driver/accelgyro_bmi260_public.h b/include/driver/accelgyro_bmi260_public.h
new file mode 100644
index 0000000000..33fc55300d
--- /dev/null
+++ b/include/driver/accelgyro_bmi260_public.h
@@ -0,0 +1,31 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* BMI260 accelerometer and gyro for Chrome EC */
+
+#ifndef __CROS_EC_DRIVER_ACCELGYRO_BMI260_PUBLIC_H
+#define __CROS_EC_DRIVER_ACCELGYRO_BMI260_PUBLIC_H
+
+/*
+ * The addr field of motion_sensor support both SPI and I2C:
+ * This is defined in include/i2c.h and is no longer an 8bit
+ * address. The 7/10 bit address starts at bit 0 and leaves
+ * room for a 10 bit address, although we don't currently
+ * have any 10 bit peripherals. I2C or SPI is indicated by a
+ * more significant bit
+ */
+
+/* I2C addresses */
+#define BMI260_ADDR0_FLAGS 0x68
+
+extern const struct accelgyro_drv bmi260_drv;
+
+void bmi260_interrupt(enum gpio_signal signal);
+
+#ifdef CONFIG_CMD_I2C_STRESS_TEST_ACCEL
+extern struct i2c_stress_test_dev bmi260_i2c_stress_test_dev;
+#endif
+
+#endif /* __CROS_EC_DRIVER_ACCELGYRO_BMI260_PUBLIC_H */
diff --git a/include/driver/accelgyro_bmi_common.h b/include/driver/accelgyro_bmi_common.h
new file mode 100644
index 0000000000..01a9ecffd6
--- /dev/null
+++ b/include/driver/accelgyro_bmi_common.h
@@ -0,0 +1,319 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* BMI accelerometer and gyro common definitions for Chrome EC */
+
+#ifndef __CROS_EC_ACCELGYRO_BMI_COMMON_H
+#define __CROS_EC_ACCELGYRO_BMI_COMMON_H
+
+#include "accelgyro.h"
+#include "accelgyro_bmi160.h"
+#include "accelgyro_bmi260.h"
+#include "accelgyro_bmi_common_public.h"
+#include "mag_bmm150.h"
+
+#if !defined(CONFIG_ACCELGYRO_BMI_COMM_SPI) && \
+	!defined(CONFIG_ACCELGYRO_BMI_COMM_I2C)
+#error "BMI must use either SPI or I2C communication"
+#endif
+
+#define BMI_CONF_REG(_sensor) (0x40 + 2 * (_sensor))
+#define BMI_RANGE_REG(_sensor) (0x41 + 2 * (_sensor))
+
+#define BMI_ODR_MASK 0x0F
+/* odr = 100 / (1 << (8 - reg)) , within limit */
+#define BMI_ODR_0_78HZ 0x01
+#define BMI_ODR_100HZ 0x08
+
+#define BMI_REG_TO_ODR(_regval)                                        \
+	((_regval) < BMI_ODR_100HZ ? 100000 / (1 << (8 - (_regval))) : \
+				     100000 * (1 << ((_regval)-8)))
+#define BMI_ODR_TO_REG(_odr)                                             \
+	((_odr) < 100000 ? (__builtin_clz(100000 / ((_odr) + 1)) - 24) : \
+			   (39 - __builtin_clz((_odr) / 100000)))
+
+enum fifo_header {
+	BMI_FH_EMPTY = 0x80,
+	BMI_FH_SKIP = 0x40,
+	BMI_FH_TIME = 0x44,
+	BMI_FH_CONFIG = 0x48
+};
+
+#define BMI_FH_MODE_MASK 0xc0
+#define BMI_FH_PARM_OFFSET 2
+#define BMI_FH_PARM_MASK (0x7 << BMI_FH_PARM_OFFSET)
+#define BMI_FH_EXT_MASK 0x03
+
+/* Sensor resolution in number of bits. This sensor has fixed resolution. */
+#define BMI_RESOLUTION 16
+/* Min and Max sampling frequency in mHz */
+#define BMI_ACCEL_MIN_FREQ 12500
+#define BMI_ACCEL_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(1600000, 100000)
+#define BMI_GYRO_MIN_FREQ 25000
+#define BMI_GYRO_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(3200000, 100000)
+
+enum bmi_running_mode {
+	STANDARD_UI_9DOF_FIFO = 0,
+	STANDARD_UI_IMU_FIFO = 1,
+	STANDARD_UI_IMU = 2,
+	STANDARD_UI_ADVANCEPOWERSAVE = 3,
+	ACCEL_PEDOMETER = 4,
+	APPLICATION_HEAD_TRACKING = 5,
+	APPLICATION_NAVIGATION = 6,
+	APPLICATION_REMOTE_CONTROL = 7,
+	APPLICATION_INDOOR_NAVIGATION = 8,
+};
+
+#define BMI_FLAG_SEC_I2C_ENABLED BIT(0)
+#define BMI_FIFO_FLAG_OFFSET 4
+#define BMI_FIFO_ALL_MASK 7
+
+#define BMI_GET_DATA(_s) ((struct bmi_drv_data_t *)(_s)->drv_data)
+#define BMI_GET_SAVED_DATA(_s) (&BMI_GET_DATA(_s)->saved_data[(_s)->type])
+
+#define BMI_ACC_DATA(v) \
+	(BMI160_ACC_X_L_G + (v) * (BMI260_ACC_X_L_G - BMI160_ACC_X_L_G))
+#define BMI_GYR_DATA(v) \
+	(BMI160_GYR_X_L_G + (v) * (BMI260_GYR_X_L_G - BMI160_GYR_X_L_G))
+#define BMI_AUX_DATA(v) \
+	(BMI160_MAG_X_L_G + (v) * (BMI260_AUX_X_L_G - BMI160_MAG_X_L_G))
+
+#define BMI_FIFO_CONFIG_0(v)    \
+	(BMI160_FIFO_CONFIG_0 + \
+	 (v) * (BMI260_FIFO_CONFIG_0 - BMI160_FIFO_CONFIG_0))
+#define BMI_FIFO_CONFIG_1(v)    \
+	(BMI160_FIFO_CONFIG_1 + \
+	 (v) * (BMI260_FIFO_CONFIG_1 - BMI160_FIFO_CONFIG_1))
+#define BMI_FIFO_SENSOR_EN(v, _sensor)           \
+	(BMI160_FIFO_SENSOR_EN(_sensor) +        \
+	 (v) * (BMI260_FIFO_SENSOR_EN(_sensor) - \
+		BMI160_FIFO_SENSOR_EN(_sensor)))
+
+#define BMI_TEMPERATURE_0(v)    \
+	(BMI160_TEMPERATURE_0 + \
+	 (v) * (BMI260_TEMPERATURE_0 - BMI160_TEMPERATURE_0))
+#define BMI_INVALID_TEMP 0x8000
+
+#define BMI_STATUS(v) (BMI160_STATUS + (v) * (BMI260_STATUS - BMI160_STATUS))
+#define BMI_DRDY_OFF(_sensor) (7 - (_sensor))
+#define BMI_DRDY_MASK(_sensor) (1 << BMI160_DRDY_OFF(_sensor))
+
+#define BMI_OFFSET_ACC70(v)    \
+	(BMI160_OFFSET_ACC70 + \
+	 (v) * (BMI260_OFFSET_ACC70 - BMI160_OFFSET_ACC70))
+#define BMI_OFFSET_GYR70(v)    \
+	(BMI160_OFFSET_GYR70 + \
+	 (v) * (BMI260_OFFSET_GYR70 - BMI160_OFFSET_GYR70))
+/*
+ * There is some bits in this register that differ between BMI160 and BMI260
+ * Only use this macro for gyro offset 9:8 (BMI_OFFSET_EN_GYR98 5:0).
+ */
+#define BMI_OFFSET_EN_GYR98(v)    \
+	(BMI160_OFFSET_EN_GYR98 + \
+	 (v) * (BMI260_OFFSET_EN_GYR98 - BMI160_OFFSET_EN_GYR98))
+#define BMI_OFFSET_GYR98_MASK (BIT(6) - 1)
+#define BMI_OFFSET_ACC_MULTI_MG (3900 * 1024)
+#define BMI_OFFSET_ACC_DIV_MG 1000000
+#define BMI_OFFSET_GYRO_MULTI_MDS (61 * 1024)
+#define BMI_OFFSET_GYRO_DIV_MDS 1000
+
+#define BMI_FIFO_LENGTH_0(v)    \
+	(BMI160_FIFO_LENGTH_0 + \
+	 (v) * (BMI260_FIFO_LENGTH_0 - BMI160_FIFO_LENGTH_0))
+#define BMI_FIFO_LENGTH_MASK(v)    \
+	(BMI160_FIFO_LENGTH_MASK + \
+	 (v) * (BMI260_FIFO_LENGTH_MASK - BMI160_FIFO_LENGTH_MASK))
+#define BMI_FIFO_DATA(v) \
+	(BMI160_FIFO_DATA + (v) * (BMI260_FIFO_DATA - BMI160_FIFO_DATA))
+
+#define BMI_CMD_REG(v) \
+	(BMI160_CMD_REG + (v) * (BMI260_CMD_REG - BMI160_CMD_REG))
+#define BMI_CMD_FIFO_FLUSH 0xb0
+
+#define BMI_ACCEL_100HZ 100
+
+/*
+ * Struct for pairing an engineering value with the register value for a
+ * parameter.
+ */
+struct bmi_accel_param_pair {
+	int val; /* Value in engineering units. */
+	int reg_val; /* Corresponding register value. */
+};
+
+int bmi_get_xyz_reg(const struct motion_sensor_t *s);
+
+/**
+ * @param type   Accel/Gyro
+ * @param psize  Size of the table
+ *
+ * @return       Range table of the type.
+ */
+const struct bmi_accel_param_pair *
+bmi_get_range_table(const struct motion_sensor_t *s, int *psize);
+
+/**
+ * @return reg value that matches the given engineering value passed in.
+ * The round_up flag is used to specify whether to round up or down.
+ * Note, this function always returns a valid reg value. If the request is
+ * outside the range of values, it returns the closest valid reg value.
+ */
+int bmi_get_reg_val(const int eng_val, const int round_up,
+		    const struct bmi_accel_param_pair *pairs, const int size);
+
+/**
+ * @return engineering value that matches the given reg val
+ */
+int bmi_get_engineering_val(const int reg_val,
+			    const struct bmi_accel_param_pair *pairs,
+			    const int size);
+
+/**
+ * Read 8bit register from accelerometer.
+ */
+int bmi_read8(const int port, const uint16_t i2c_spi_addr_flags, const int reg,
+	      int *data_ptr);
+
+/**
+ * Write 8bit register from accelerometer.
+ */
+int bmi_write8(const int port, const uint16_t i2c_spi_addr_flags, const int reg,
+	       int data);
+
+/**
+ * Read 16bit register from accelerometer.
+ */
+int bmi_read16(const int port, const uint16_t i2c_spi_addr_flags,
+	       const uint8_t reg, int *data_ptr);
+
+/**
+ * Write 16bit register from accelerometer.
+ */
+int bmi_write16(const int port, const uint16_t i2c_spi_addr_flags,
+		const int reg, int data);
+
+/**
+ * Read 32bit register from accelerometer.
+ */
+int bmi_read32(const int port, const uint16_t i2c_spi_addr_flags,
+	       const uint8_t reg, int *data_ptr);
+
+/**
+ * Read n bytes from accelerometer.
+ */
+int bmi_read_n(const int port, const uint16_t i2c_spi_addr_flags,
+	       const uint8_t reg, uint8_t *data_ptr, const int len);
+
+/**
+ * Write n bytes from accelerometer.
+ */
+int bmi_write_n(const int port, const uint16_t i2c_spi_addr_flags,
+		const uint8_t reg, const uint8_t *data_ptr, const int len);
+
+/*
+ * Enable/Disable specific bit set of a 8-bit reg.
+ */
+int bmi_enable_reg8(const struct motion_sensor_t *s, int reg, uint8_t bits,
+		    int enable);
+
+/*
+ * Set specific bit set to certain value of a 8-bit reg.
+ */
+int bmi_set_reg8(const struct motion_sensor_t *s, int reg, uint8_t bits,
+		 int mask);
+
+/*
+ * @s: base sensor.
+ * @v: output vector.
+ * @input: 6-bits array input.
+ */
+void bmi_normalize(const struct motion_sensor_t *s, intv3_t v, uint8_t *input);
+
+/*
+ * Decode the header from the fifo.
+ * Return 0 if we need further processing.
+ * Sensor mutex must be held during processing, to protect the fifos.
+ *
+ * @accel: base sensor
+ * @hdr: the header to decode
+ * @last_ts: the last timestamp of fifo interrupt.
+ * @bp: current pointer in the buffer, updated when processing the header.
+ * @ep: pointer to the end of the valid data in the buffer.
+ */
+int bmi_decode_header(struct motion_sensor_t *accel, enum fifo_header hdr,
+		      uint32_t last_ts, uint8_t **bp, uint8_t *ep);
+/**
+ * Retrieve hardware FIFO from sensor,
+ * - put data in Sensor Hub fifo.
+ * - update sensor raw_xyz vector with the last information.
+ * We put raw data in hub fifo and process data from there.
+ * @s: Pointer to sensor data.
+ * @last_ts: The last timestamp of fifo interrupt.
+ *
+ * Read only up to  bmi_buffer. If more reads are needed, we will be called
+ * again by the interrupt routine.
+ *
+ * NOTE: If a new driver supports this function, be sure to add a check
+ * for spoof_mode in order to load the sensor stack with the spoofed
+ * data.  See accelgyro_bmi260.c::load_fifo for an example.
+ */
+int bmi_load_fifo(struct motion_sensor_t *s, uint32_t last_ts);
+
+int bmi_set_range(struct motion_sensor_t *s, int range, int rnd);
+
+int bmi_get_data_rate(const struct motion_sensor_t *s);
+
+int bmi_get_offset(const struct motion_sensor_t *s, int16_t *offset,
+		   int16_t *temp);
+
+int bmi_get_resolution(const struct motion_sensor_t *s);
+
+int bmi_get_rms_noise(const struct motion_sensor_t *accel,
+		      int rms_noise_100hz_mg);
+
+int bmi_set_scale(const struct motion_sensor_t *s, const uint16_t *scale,
+		  int16_t temp);
+
+int bmi_get_scale(const struct motion_sensor_t *s, uint16_t *scale,
+		  int16_t *temp);
+
+/* Start/Stop the FIFO collecting events */
+int bmi_enable_fifo(const struct motion_sensor_t *s, int enable);
+
+/* Read the xyz data of accel/gyro */
+int bmi_read(const struct motion_sensor_t *s, intv3_t v);
+
+/* Read temperature of sensor s */
+int bmi_read_temp(const struct motion_sensor_t *s, int *temp_ptr);
+
+/* Read temperature of sensor idx */
+int bmi_get_sensor_temp(int idx, int *temp_ptr);
+
+/*
+ * Get the normalized rate according to input rate and input rnd
+ * @rate: input rate
+ * @rnd: round up
+ * @normalized_rate_ptr: normalized rate pointer for output
+ * @reg_val_ptr: pointer to the actual register value of normalized rate for
+ *               output.
+ */
+int bmi_get_normalized_rate(const struct motion_sensor_t *s, int rate, int rnd,
+			    int *normalized_rate_ptr, uint8_t *reg_val_ptr);
+
+/* Get the accelerometer offset */
+int bmi_accel_get_offset(const struct motion_sensor_t *accel, intv3_t v);
+
+/* Get the gyroscope offset */
+int bmi_gyro_get_offset(const struct motion_sensor_t *gyro, intv3_t v);
+
+/* Set the accelerometer offset */
+int bmi_set_accel_offset(const struct motion_sensor_t *accel, intv3_t v);
+
+/* Set the gyroscope offset */
+int bmi_set_gyro_offset(const struct motion_sensor_t *gyro, intv3_t v,
+			int *val98_ptr);
+
+int bmi_list_activities(const struct motion_sensor_t *s, uint32_t *enabled,
+			uint32_t *disabled);
+#endif /* __CROS_EC_ACCELGYRO_BMI_COMMON_H */
diff --git a/include/driver/accelgyro_bmi_common_public.h b/include/driver/accelgyro_bmi_common_public.h
new file mode 100644
index 0000000000..b3965d4dc5
--- /dev/null
+++ b/include/driver/accelgyro_bmi_common_public.h
@@ -0,0 +1,31 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* BMI accelerometer and gyro common definitions for Chrome EC */
+
+#ifndef __CROS_EC_DRIVER_ACCELGYRO_BMI_COMMON_PUBLIC_H
+#define __CROS_EC_DRIVER_ACCELGYRO_BMI_COMMON_PUBLIC_H
+
+/* Min and Max sampling frequency in mHz */
+#define BMI_ACCEL_MIN_FREQ 12500
+#define BMI_ACCEL_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(1600000, 100000)
+#define BMI_GYRO_MIN_FREQ 25000
+#define BMI_GYRO_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(3200000, 100000)
+
+struct bmi_drv_data_t {
+	struct accelgyro_saved_data_t saved_data[3];
+	uint8_t flags;
+	uint8_t enabled_activities;
+	uint8_t disabled_activities;
+#ifdef CONFIG_MAG_BMI_BMM150
+	struct bmm150_private_data compass;
+#endif
+#ifdef CONFIG_BMI_ORIENTATION_SENSOR
+	uint8_t raw_orientation;
+	enum motionsensor_orientation orientation;
+	enum motionsensor_orientation last_orientation;
+#endif
+};
+
+#endif /* __CROS_EC_DRIVER_ACCELGYRO_BMI_COMMON_PUBLIC_H */
diff --git a/include/driver/accelgyro_lsm6dso_public.h b/include/driver/accelgyro_lsm6dso_public.h
new file mode 100644
index 0000000000..f2c1b2bc4e
--- /dev/null
+++ b/include/driver/accelgyro_lsm6dso_public.h
@@ -0,0 +1,24 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* LSM6DSO Accel and Gyro driver for Chrome EC */
+
+#ifndef __CROS_EC_ACCELGYRO_LSM6DSO_PUBLIC_H
+#define __CROS_EC_ACCELGYRO_LSM6DSO_PUBLIC_H
+
+#include "driver/accelgyro_lsm6dso_public.h"
+
+/*
+ * 7-bit address is 110101xb. Where 'x' is determined
+ * by the voltage on the ADDR pin
+ */
+#define LSM6DSO_ADDR0_FLAGS 0x6a
+#define LSM6DSO_ADDR1_FLAGS 0x6b
+
+/* Absolute maximum rate for Acc and Gyro sensors */
+#define LSM6DSO_ODR_MIN_VAL 13000
+#define LSM6DSO_ODR_MAX_VAL MOTION_MAX_SENSOR_FREQUENCY(416000, 13000)
+
+#endif /* __CROS_EC_ACCELGYRO_LSM6DSO_PUBLIC_H */
diff --git a/include/driver/als_tcs3400.h b/include/driver/als_tcs3400.h
new file mode 100644
index 0000000000..ab28d7e7d5
--- /dev/null
+++ b/include/driver/als_tcs3400.h
@@ -0,0 +1,141 @@
+/* Copyright 2019 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * AMS TCS3400 light sensor driver
+ */
+
+#ifndef __CROS_EC_ALS_TCS3400_H
+#define __CROS_EC_ALS_TCS3400_H
+
+#include "driver/als_tcs3400_public.h"
+
+/* ID for TCS34001 and TCS34005 */
+#define TCS340015_DEVICE_ID 0x90
+
+/* ID for TCS34003 and TCS34007 */
+#define TCS340037_DEVICE_ID 0x93
+
+/* Register Map */
+#define TCS_I2C_ENABLE 0x80 /* R/W Enables states and interrupts */
+#define TCS_I2C_ATIME 0x81 /* R/W RGBC integration time */
+#define TCS_I2C_WTIME 0x83 /* R/W Wait time */
+#define TCS_I2C_AILTL 0x84 /* R/W Clear irq low threshold low byte */
+#define TCS_I2C_AILTH 0x85 /* R/W Clear irq low threshold high byte */
+#define TCS_I2C_AIHTL 0x86 /* R/W Clear irq high threshold low byte */
+#define TCS_I2C_AIHTH 0x87 /* R/W Clear irq high threshold high byte */
+#define TCS_I2C_PERS 0x8C /* R/W Interrupt persistence filter */
+#define TCS_I2C_CONFIG 0x8D /* R/W Configuration */
+#define TCS_I2C_CONTROL 0x8F /* R/W Gain control register */
+#define TCS_I2C_AUX 0x90 /* R/W Auxiliary control register */
+#define TCS_I2C_REVID 0x91 /* R Revision ID */
+#define TCS_I2C_ID 0x92 /* R Device ID */
+#define TCS_I2C_STATUS 0x93 /* R Device status */
+#define TCS_I2C_CDATAL 0x94 /* R Clear / IR channel low data register */
+#define TCS_I2C_CDATAH 0x95 /* R Clear / IR channel high data register */
+#define TCS_I2C_RDATAL 0x96 /* R Red ADC low data register */
+#define TCS_I2C_RDATAH 0x97 /* R Red ADC high data register */
+#define TCS_I2C_GDATAL 0x98 /* R Green ADC low data register */
+#define TCS_I2C_GDATAH 0x99 /* R Green ADC high data register */
+#define TCS_I2C_BDATAL 0x9A /* R Blue ADC low data register */
+#define TCS_I2C_BDATAH 0x9B /* R Blue ADC high data register */
+#define TCS_I2C_IR 0xC0 /* R/W Access IR Channel */
+#define TCS_I2C_IFORCE 0xE4 /* W Force Interrupt */
+#define TCS_I2C_CICLEAR 0xE6 /* W Clear channel interrupt clear */
+#define TCS_I2C_AICLEAR 0xE7 /* W Clear all interrupts */
+
+#define TCS_I2C_ENABLE_POWER_ON BIT(0)
+#define TCS_I2C_ENABLE_ADC_ENABLE BIT(1)
+#define TCS_I2C_ENABLE_WAIT_ENABLE BIT(3)
+#define TCS_I2C_ENABLE_INT_ENABLE BIT(4)
+#define TCS_I2C_ENABLE_SLEEP_AFTER_INT BIT(6)
+#define TCS_I2C_ENABLE_MASK                                       \
+	(TCS_I2C_ENABLE_POWER_ON | TCS_I2C_ENABLE_ADC_ENABLE |    \
+	 TCS_I2C_ENABLE_WAIT_ENABLE | TCS_I2C_ENABLE_INT_ENABLE | \
+	 TCS_I2C_ENABLE_SLEEP_AFTER_INT)
+
+enum tcs3400_mode {
+	TCS3400_MODE_SUSPEND = 0,
+	TCS3400_MODE_IDLE =
+		(TCS_I2C_ENABLE_POWER_ON | TCS_I2C_ENABLE_ADC_ENABLE),
+	TCS3400_MODE_COLLECTING =
+		(TCS_I2C_ENABLE_POWER_ON | TCS_I2C_ENABLE_ADC_ENABLE |
+		 TCS_I2C_ENABLE_INT_ENABLE),
+};
+
+#define TCS_I2C_CONTROL_MASK 0x03
+#define TCS_I2C_STATUS_RGBC_VALID BIT(0)
+#define TCS_I2C_STATUS_ALS_IRQ BIT(4)
+#define TCS_I2C_STATUS_ALS_SATURATED BIT(7)
+
+#define TCS_I2C_AUX_ASL_INT_ENABLE BIT(5)
+
+/* Light data resides at 0x94 thru 0x98 */
+#define TCS_DATA_START_LOCATION TCS_I2C_CDATAL
+#define TCS_CLEAR_DATA_SIZE 2
+#define TCS_RGBC_DATA_SIZE 8
+
+#define TCS3400_DRV_DATA(_s) ((struct als_drv_data_t *)(_s)->drv_data)
+#define TCS3400_RGB_DRV_DATA(_s) \
+	((struct tcs3400_rgb_drv_data_t *)(_s)->drv_data)
+
+/*
+ * Factor to multiply light value by to determine if an increase in gain
+ * would cause the next value to saturate.
+ *
+ * On the TCS3400, gain increases 4x each time again register setting is
+ * incremented.  However, I see cases where values that are 24% of saturation
+ * go into saturation after increasing gain, causing a back-and-forth cycle to
+ * occur :
+ *
+ * [134.654994 tcs3400_adjust_sensor_for_saturation value=65535 100% Gain=2 ]
+ * [135.655064 tcs3400_adjust_sensor_for_saturation value=15750 24% Gain=1 ]
+ * [136.655107 tcs3400_adjust_sensor_for_saturation value=65535 100% Gain=2 ]
+ *
+ * To avoid this, we require value to be <= 20% of saturation level
+ * (TCS_GAIN_SAT_LEVEL) before allowing gain to be increased.
+ */
+#define TCS_GAIN_ADJUST_FACTOR 5
+#define TCS_GAIN_SAT_LEVEL (TCS_SATURATION_LEVEL / TCS_GAIN_ADJUST_FACTOR)
+#define TCS_UPSHIFT_FACTOR_N 25 /* upshift factor = 2.5 */
+#define TCS_UPSHIFT_FACTOR_D 10
+#define TCS_GAIN_UPSHIFT_LEVEL \
+	(TCS_SATURATION_LEVEL * TCS_UPSHIFT_FACTOR_D / TCS_UPSHIFT_FACTOR_N)
+
+/*
+ * Percentage of saturation level that the auto-adjusting anti-saturation
+ * method will drive towards.
+ */
+#define TSC_SATURATION_LOW_BAND_PERCENT 90
+#define TSC_SATURATION_LOW_BAND_LEVEL \
+	(TCS_SATURATION_LEVEL * TSC_SATURATION_LOW_BAND_PERCENT / 100)
+
+enum crbg_index {
+	CLEAR_CRGB_IDX = 0,
+	RED_CRGB_IDX,
+	GREEN_CRGB_IDX,
+	BLUE_CRGB_IDX,
+	CRGB_COUNT,
+};
+
+#if defined(CONFIG_ZEPHYR)
+#if DT_NODE_EXISTS(DT_ALIAS(tcs3400_int))
+/*
+ * Get the mostion sensor ID of the TCS3400 sensor that
+ * generates the interrupt.
+ * The interrupt is converted to the event and transferred to motion
+ * sense task that actually handles the interrupt.
+ *
+ * Here, we use alias to get the motion sensor ID
+ *
+ * e.g) als_clear below is the label of a child node in /motionsense-sensors
+ * aliases {
+ *     tcs3400-int = &als_clear;
+ * };
+ */
+#define CONFIG_ALS_TCS3400_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(SENSOR_ID(DT_ALIAS(tcs3400_int)))
+#endif
+#endif /* CONFIG_ZEPHYR */
+
+#endif /* __CROS_EC_ALS_TCS3400_H */
diff --git a/include/driver/als_tcs3400_public.h b/include/driver/als_tcs3400_public.h
new file mode 100644
index 0000000000..2cf9aed45f
--- /dev/null
+++ b/include/driver/als_tcs3400_public.h
@@ -0,0 +1,76 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * AMS TCS3400 light sensor driver
+ */
+
+#ifndef __CROS_EC_DRIVER_ALS_TCS3400_PUBLIC_H
+#define __CROS_EC_DRIVER_ALS_TCS3400_PUBLIC_H
+
+#include "accelgyro.h"
+
+/* I2C Interface */
+#define TCS3400_I2C_ADDR_FLAGS 0x39
+
+/* NOTE: The higher the ATIME value in reg, the shorter the accumulation time */
+#define TCS_MIN_ATIME 0x00 /* 712 ms */
+#define TCS_MAX_ATIME 0x70 /* 400 ms */
+#define TCS_ATIME_GRANULARITY 256 /* 256 atime settings */
+#define TCS_SATURATION_LEVEL 0xffff /* for 0 < atime < 0x70 */
+#define TCS_DEFAULT_ATIME TCS_MIN_ATIME /* 712 ms */
+#define TCS_CALIBRATION_ATIME TCS_MIN_ATIME
+#define TCS_GAIN_UPSHIFT_ATIME TCS_MAX_ATIME
+
+/* Number of different ranges supported for atime adjustment support */
+#define TCS_MAX_ATIME_RANGES 13
+#define TCS_GAIN_TABLE_MAX_LUX 12999
+#define TCS_ATIME_GAIN_FACTOR 100 /* table values are 100x actual value */
+
+#define TCS_MIN_AGAIN 0x00 /* 1x gain */
+#define TCS_MAX_AGAIN 0x03 /* 64x gain */
+#define TCS_CALIBRATION_AGAIN 0x02 /* 16x gain */
+#define TCS_DEFAULT_AGAIN TCS_CALIBRATION_AGAIN
+
+#define TCS_MAX_INTEGRATION_TIME 2780 /* 2780us */
+#define TCS_ATIME_DEC_STEP 5
+#define TCS_ATIME_INC_STEP TCS_GAIN_UPSHIFT_ATIME
+
+/* Min and Max sampling frequency in mHz */
+#define TCS3400_LIGHT_MIN_FREQ 149
+#define TCS3400_LIGHT_MAX_FREQ 1000
+#if (CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ <= TCS3400_LIGHT_MAX_FREQ)
+#error "EC too slow for light sensor"
+#endif
+
+/* saturation auto-adjustment */
+struct tcs_saturation_t {
+	/*
+	 * Gain Scaling; must be value between 0 and 3
+	 *      0 - 1x scaling
+	 *      1 - 4x scaling
+	 *      2 - 16x scaling
+	 *      3 - 64x scaling
+	 */
+	uint8_t again;
+
+	/* Acquisition Time, controlled by the ATIME register */
+	uint8_t atime; /* ATIME register setting */
+};
+
+/* tcs3400 rgb als driver data */
+struct tcs3400_rgb_drv_data_t {
+	uint8_t calibration_mode; /* 0 = normal run mode, 1 = calibration mode
+				   */
+
+	struct rgb_calibration_t calibration;
+	struct tcs_saturation_t saturation; /* saturation adjustment */
+};
+
+extern const struct accelgyro_drv tcs3400_drv;
+extern const struct accelgyro_drv tcs3400_rgb_drv;
+
+void tcs3400_interrupt(enum gpio_signal signal);
+int tcs3400_get_integration_time(int atime);
+
+#endif /* __CROS_EC_DRIVER_ALS_TCS3400_PUBLIC_H */
diff --git a/include/driver/amd_stt.h b/include/driver/amd_stt.h
new file mode 100644
index 0000000000..0a407cb213
--- /dev/null
+++ b/include/driver/amd_stt.h
@@ -0,0 +1,28 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* AMD STT (Skin Temperature Tracking) Manager */
+
+#ifndef __CROS_EC_AMD_STT_H
+#define __CROS_EC_AMD_STT_H
+
+#define AMD_STT_WRITE_SENSOR_VALUE_CMD 0x3A
+
+enum amd_stt_pcb_sensor {
+	AMD_STT_PCB_SENSOR_APU = 0x0,
+	AMD_STT_PCB_SENSOR_REMOTE = 0x1,
+	AMD_STT_PCB_SENSOR_GPU = 0x2
+};
+
+/**
+ * Boards must implement these callbacks for SOC and Ambient temperature.
+ * Temperature must be returned in Milli Kelvin.
+ * TODO(b/192391025): Replace with direct calls to temp_sensor_read_mk
+ */
+int board_get_soc_temp_mk(int *temp_mk);
+int board_get_ambient_temp_mk(int *temp_mk);
+int board_get_gpu_temp_mk(int *temp_mk);
+
+#endif /* __CROS_EC_AMD_STT_H */
diff --git a/include/driver/bc12/mt6360_public.h b/include/driver/bc12/mt6360_public.h
new file mode 100644
index 0000000000..fbceb74dd6
--- /dev/null
+++ b/include/driver/bc12/mt6360_public.h
@@ -0,0 +1,62 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_DRIVER_BC12_MT6360_PUBLIC_H
+#define __CROS_EC_DRIVER_BC12_MT6360_PUBLIC_H
+
+#include <inttypes.h>
+
+#define MT6360_PMU_I2C_ADDR_FLAGS 0x34
+#define MT6360_PMIC_I2C_ADDR_FLAGS 0x1a
+#define MT6360_LDO_I2C_ADDR_FLAGS 0x64
+#define MT6360_PD_I2C_ADDR_FLAGS 0x4e
+
+enum mt6360_regulator_id {
+	MT6360_LDO3,
+	MT6360_LDO5,
+	MT6360_LDO6,
+	MT6360_LDO7,
+	MT6360_BUCK1,
+	MT6360_BUCK2,
+
+	MT6360_REGULATOR_COUNT,
+};
+
+int mt6360_regulator_get_info(enum mt6360_regulator_id id, char *name,
+			      uint16_t *voltage_count, uint16_t *voltages_mv);
+
+int mt6360_regulator_enable(enum mt6360_regulator_id id, uint8_t enable);
+
+int mt6360_regulator_is_enabled(enum mt6360_regulator_id id, uint8_t *enabled);
+
+int mt6360_regulator_set_voltage(enum mt6360_regulator_id id, int min_mv,
+				 int max_mv);
+
+int mt6360_regulator_get_voltage(enum mt6360_regulator_id id, int *voltage_mv);
+
+enum mt6360_led_id {
+	MT6360_LED_RGB1,
+	MT6360_LED_RGB2,
+	MT6360_LED_RGB3,
+	MT6360_LED_RGB_ML,
+
+	MT6360_LED_COUNT,
+};
+
+#define MT6360_LED_BRIGHTNESS_MAX 15
+
+int mt6360_led_enable(enum mt6360_led_id led_id, int enable);
+
+int mt6360_led_set_brightness(enum mt6360_led_id led_id, int brightness);
+
+extern const struct mt6360_config_t mt6360_config;
+
+struct mt6360_config_t {
+	int i2c_port;
+	int i2c_addr_flags;
+};
+extern const struct bc12_drv mt6360_drv;
+
+#endif /* __CROS_EC_DRIVER_BC12_MT6360_PUBLIC_H */
diff --git a/include/driver/bc12/pi3usb9201_public.h b/include/driver/bc12/pi3usb9201_public.h
new file mode 100644
index 0000000000..20788aa5e3
--- /dev/null
+++ b/include/driver/bc12/pi3usb9201_public.h
@@ -0,0 +1,28 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* PI3USB9201 USB BC 1.2 Charger Detector public definitions */
+
+#ifndef __CROS_EC_DRIVER_BC12_PI3USB9201_PUBLIC_H
+#define __CROS_EC_DRIVER_BC12_PI3USB9201_PUBLIC_H
+
+/* I2C address */
+#define PI3USB9201_I2C_ADDR_0_FLAGS 0x5C
+#define PI3USB9201_I2C_ADDR_1_FLAGS 0x5D
+#define PI3USB9201_I2C_ADDR_2_FLAGS 0x5E
+#define PI3USB9201_I2C_ADDR_3_FLAGS 0x5F
+
+struct pi3usb9201_config_t {
+	const int i2c_port;
+	const int i2c_addr_flags;
+	const int flags;
+};
+
+/* Configuration struct defined at board level */
+extern const struct pi3usb9201_config_t pi3usb9201_bc12_chips[];
+
+extern const struct bc12_drv pi3usb9201_drv;
+
+#endif /* __CROS_EC_DRIVER_BC12_PI3USB9201_PUBLIC_H */
diff --git a/include/driver/charger/isl923x_public.h b/include/driver/charger/isl923x_public.h
new file mode 100644
index 0000000000..f582f188a5
--- /dev/null
+++ b/include/driver/charger/isl923x_public.h
@@ -0,0 +1,76 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Renesas (Intersil) ISL-9237/38 battery charger public header
+ */
+
+#ifndef __CROS_EC_DRIVER_CHARGER_ISL923X_PUBLIC_H
+#define __CROS_EC_DRIVER_CHARGER_ISL923X_PUBLIC_H
+
+#include "common.h"
+#include "stdbool.h"
+
+#define ISL923X_ADDR_FLAGS (0x09)
+
+extern const struct charger_drv isl923x_drv;
+
+/**
+ * Initialize AC & DC prochot threshold
+ *
+ * @param	chgnum: Index into charger chips
+ * @param	AC Prochot threshold current in mA:
+ *			multiple of 128 up to 6400 mA
+ *			DC Prochot threshold current in mA:
+ *			multiple of 128 up to 12800 mA
+ *		Bits below 128mA are truncated (ignored).
+ * @return enum ec_error_list
+ */
+int isl923x_set_ac_prochot(int chgnum, uint16_t ma);
+int isl923x_set_dc_prochot(int chgnum, uint16_t ma);
+
+/**
+ * Set the general comparator output polarity when asserted.
+ *
+ * @param chgnum: Index into charger chips
+ * @param invert: Non-zero to invert polarity, zero to non-invert.
+ * @return EC_SUCCESS, error otherwise.
+ */
+int isl923x_set_comparator_inversion(int chgnum, int invert);
+
+/**
+ * Return whether ACOK is high or low.
+ *
+ * @param chgnum index into chg_chips table.
+ * @param acok will be set to true if ACOK is asserted, otherwise false.
+ * @return EC_SUCCESS, error otherwise.
+ */
+enum ec_error_list raa489000_is_acok(int chgnum, bool *acok);
+
+/**
+ * Prepare the charger IC for battery ship mode.  Battery ship mode sets the
+ * lowest power state for the IC. Battery ship mode can only be entered from
+ * battery only mode.
+ *
+ * @param chgnum index into chg_chips table.
+ */
+void raa489000_hibernate(int chgnum, bool disable_adc);
+
+/**
+ * Enable or Disable the ASGATE in the READY state.
+ *
+ * @param chgnum: Index into charger chips
+ * @param enable: whether to enable ASGATE
+ */
+int raa489000_enable_asgate(int chgnum, bool enable);
+
+/**
+ * Check whether the comparator output needs to
+ * be inverted for the AC_PRESENT signal.
+ */
+void raa489000_check_ac_present(void);
+
+enum ec_error_list isl9238c_hibernate(int chgnum);
+enum ec_error_list isl9238c_resume(int chgnum);
+
+#endif /* __CROS_EC_DRIVER_CHARGER_ISL923X_PUBLIC_H */
diff --git a/include/driver/charger/isl9241_public.h b/include/driver/charger/isl9241_public.h
new file mode 100644
index 0000000000..19b5af6297
--- /dev/null
+++ b/include/driver/charger/isl9241_public.h
@@ -0,0 +1,52 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Renesas (Intersil) ISL-9241 battery charger public header
+ */
+
+#ifndef __CROS_EC_DRIVER_CHARGER_ISL9241_PUBLIC_H
+#define __CROS_EC_DRIVER_CHARGER_ISL9241_PUBLIC_H
+
+#define ISL9241_ADDR_FLAGS 0x09
+
+/* Default minimum VIN voltage controlled by ISL9241_REG_VIN_VOLTAGE */
+#define ISL9241_BC12_MIN_VOLTAGE 4096
+
+extern const struct charger_drv isl9241_drv;
+
+/**
+ * Set AC prochot threshold
+ *
+ * @param chgnum: Index into charger chips
+ * @param ma: AC prochot threshold current in mA, multiple of 128mA
+ * @return EC_SUCCESS or error
+ */
+int isl9241_set_ac_prochot(int chgnum, int ma);
+
+/**
+ * Set DC prochot threshold
+ *
+ * @param chgnum: Index into charger chips
+ * @param ma: DC prochot threshold current in mA, multiple of 256mA
+ * @return EC_SUCCESS or error
+ */
+int isl9241_set_dc_prochot(int chgnum, int ma);
+
+/**
+ * Check if charger is currently in bypass mode
+ *
+ * @return true/false
+ */
+bool isl9241_is_in_bypass_mode(int chgnum);
+
+#ifdef CONFIG_CHARGER_RAA489110
+#define ISL9241_AC_PROCHOT_CURRENT_MIN 32 /* mA */
+#else /* CONFIG_CHARGER_ISL9241 */
+#define ISL9241_AC_PROCHOT_CURRENT_MIN 128 /* mA */
+#endif
+#define ISL9241_AC_PROCHOT_CURRENT_MAX 6400 /* mA */
+#define ISL9241_DC_PROCHOT_CURRENT_MIN 256 /* mA */
+#define ISL9241_DC_PROCHOT_CURRENT_MAX 12800 /* mA */
+
+#endif /* __CROS_EC_DRIVER_CHARGER_ISL9241_PUBLIC_H */
diff --git a/include/driver/ln9310.h b/include/driver/ln9310.h
new file mode 100644
index 0000000000..dacdf95a91
--- /dev/null
+++ b/include/driver/ln9310.h
@@ -0,0 +1,244 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * LION Semiconductor LN-9310 switched capacitor converter.
+ */
+
+#ifndef __CROS_EC_LN9310_H
+#define __CROS_EC_LN9310_H
+
+#include "common.h"
+#include "gpio_signal.h"
+
+/* I2C address */
+#define LN9310_I2C_ADDR_0_FLAGS 0x72
+#define LN9310_I2C_ADDR_1_FLAGS 0x73
+#define LN9310_I2C_ADDR_2_FLAGS 0x53
+#define LN9310_I2C_ADDR_3_FLAGS 0x54
+
+/* Registers */
+#define LN9310_REG_CHIP_ID 0x00
+#define LN9310_CHIP_ID 0x44
+#define LN9310_REG_INT1 0x01
+#define LN9310_REG_INT1_MSK 0x02
+#define LN9310_INT1_TIMER BIT(0)
+#define LN9310_INT1_INFET BIT(1)
+#define LN9310_INT1_TEMP BIT(2)
+#define LN9310_INT1_REV_CURR BIT(3)
+#define LN9310_INT1_MODE BIT(4)
+#define LN9310_INT1_ALARM BIT(5)
+#define LN9310_INT1_OK BIT(6)
+#define LN9310_INT1_FAULT BIT(7)
+
+#define LN9310_REG_SYSGPIO_MSK 0x03
+
+#define LN9310_REG_SYS_STS 0x04
+#define LN9310_SYS_STANDBY BIT(0)
+#define LN9310_SYS_SWITCHING21_ACTIVE BIT(1)
+#define LN9310_SYS_SWITCHING31_ACTIVE BIT(2)
+#define LN9310_SYS_BYPASS_ACTIVE BIT(3)
+#define LN9310_SYS_INFET_OK BIT(4)
+#define LN9310_SYS_SC_OUT_SWITCH_OK BIT(5)
+#define LN9310_SYS_INFET_OUT_SWITCH_OK BIT(6)
+
+#define LN9310_REG_SAFETY_STS 0x05
+#define LN9310_REG_FAULT1_STS 0x06
+#define LN9310_REG_FAULT2_STS 0x07
+
+#define LN9310_REG_PWR_CTRL 0x1d
+#define LN9310_PWR_OP_MODE0 BIT(0)
+#define LN9310_PWR_OP_MODE1 BIT(1)
+#define LN9310_PWR_INFET_EN BIT(2)
+#define LN9310_PWR_INFET_AUTO_MODE BIT(3)
+#define LN9310_PWR_REVERSE_MODE BIT(4)
+#define LN9310_PWR_VIN_OV_IGNORE BIT(5)
+#define LN9310_PWR_OP_MANUAL_UPDATE BIT(6)
+#define LN9310_PWR_FORCE_INSNS_EN BIT(7)
+#define LN9310_PWR_OP_MODE_MASK 0x03
+#define LN9310_PWR_OP_MODE_DISABLED 0x00
+#define LN9310_PWR_OP_MODE_BYPASS 0x01
+#define LN9310_PWR_OP_MODE_SWITCH21 0x02
+#define LN9310_PWR_OP_MODE_SWITCH31 0x03
+#define LN9310_PWR_OP_MODE_MANUAL_UPDATE_MASK 0x40
+#define LN9310_PWR_OP_MODE_MANUAL_UPDATE_OFF 0x00
+#define LN9310_PWR_INFET_AUTO_MODE_MASK 0x08
+#define LN9310_PWR_INFET_AUTO_MODE_ON 0x08
+#define LN9310_PWR_INFET_AUTO_MODE_OFF 0x00
+
+#define LN9310_REG_SYS_CTRL 0x1e
+
+#define LN9310_REG_STARTUP_CTRL 0x1f
+#define LN9310_STARTUP_STANDBY_EN BIT(0)
+#define LN9310_STARTUP_SELECT_EXT_5V_FOR_VDR BIT(3)
+
+#define LN9310_REG_IIN_CTRL 0x20
+#define LN9310_REG_VIN_CTRL 0x21
+
+#define LN9310_REG_TRACK_CTRL 0x22
+#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN BIT(7)
+#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG2 BIT(6)
+#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG1 BIT(5)
+#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG0 BIT(4)
+#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_MASK 0x80
+#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_ON 0x80
+#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_OFF 0x00
+#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG_MASK 0x70
+#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG_10V 0x10
+
+#define LN9310_REG_OCP_CTRL 0x23
+
+#define LN9310_REG_TIMER_CTRL 0x24
+#define LN9310_TIMER_OP_SELF_SYNC_EN BIT(3)
+#define LN9310_TIMER_OP_SELF_SYNC_EN_MASK 0x08
+#define LN9310_TIMER_OP_SELF_SYNC_EN_ON 0x08
+
+#define LN9310_REG_RECOVERY_CTRL 0x25
+
+#define LN9310_REG_LB_CTRL 0x26
+#define LN9310_LB_MIN_FREQ_EN BIT(2)
+#define LN9310_LB_DELTA_MASK 0x38
+#define LN9310_LB_DELTA_2S 0x20
+#define LN9310_LB_DELTA_3S 0x20
+
+#define LN9310_REG_SC_OUT_OV_CTRL 0x29
+#define LN9310_REG_STS_CTRL 0x2d
+
+#define LN9310_REG_MODE_CHANGE_CFG 0x2e
+#define LN9310_MODE_TM_VIN_OV_CFG0 BIT(0)
+#define LN9310_MODE_TM_VIN_OV_CFG1 BIT(1)
+#define LN9310_MODE_TM_VIN_OV_CFG2 BIT(2)
+#define LN9310_MODE_TM_SC_OUT_PRECHG_CFG0 BIT(3)
+#define LN9310_MODE_TM_SC_OUT_PRECHG_CFG1 BIT(4)
+#define LN9310_MODE_TM_TRACK_CFG0 BIT(5)
+#define LN9310_MODE_TM_TRACK_CFG1 BIT(6)
+#define LN9310_MODE_FORCE_MODE_CFG BIT(7)
+#define LN9310_MODE_TM_TRACK_MASK 0x60
+#define LN9310_MODE_TM_TRACK_BYPASS 0x00
+#define LN9310_MODE_TM_TRACK_SWITCH21 0x20
+#define LN9310_MODE_TM_TRACK_SWITCH31 0x60
+#define LN9310_MODE_TM_SC_OUT_PRECHG_MASK 0x18
+#define LN9310_MODE_TM_SC_OUT_PRECHG_BYPASS 0x0
+#define LN9310_MODE_TM_SC_OUT_PRECHG_SWITCH21 0x08
+#define LN9310_MODE_TM_SC_OUT_PRECHG_SWITCH31 0x18
+#define LN9310_MODE_TM_VIN_OV_CFG_MASK 0x07
+#define LN9310_MODE_TM_VIN_OV_CFG_2S 0x0 /* 14V */
+#define LN9310_MODE_TM_VIN_OV_CFG_3S 0x2 /* 20V */
+
+#define LN9310_REG_SPARE_0 0x2A
+#define LN9310_SPARE_0_SW4_BEFORE_BSTH_BSTL_EN_CFG_MASK 0x40
+#define LN9310_SPARE_0_SW4_BEFORE_BSTH_BSTL_EN_CFG_ON 0x40
+#define LN9310_SPARE_0_LB_MIN_FREQ_SEL_MASK 0x10
+#define LN9310_SPARE_0_LB_MIN_FREQ_SEL_ON 0x10
+
+#define LN9310_REG_SC_DITHER_CTRL 0x2f
+
+#define LN9310_REG_LION_CTRL 0x30
+#define LN9310_LION_CTRL_MASK 0xFF
+#define LN9310_LION_CTRL_UNLOCK_AND_EN_TM 0xAA
+#define LN9310_LION_CTRL_UNLOCK 0x5B
+/*
+ * value changed to 0x22 to distinguish from reset value of 0x00
+ * 0x22 and 0x00 are functionally equivalent within LN9310
+ */
+#define LN9310_LION_CTRL_LOCK 0x22
+
+#define LN9310_REG_CFG_0 0x3C
+#define LN9310_CFG_0_LS_HELPER_IDLE_MSK_MASK 0x20
+#define LN9310_CFG_0_LS_HELPER_IDLE_MSK_ON 0x20
+
+#define LN9310_REG_CFG_4 0x40
+#define LN9310_CFG_4_SC_OUT_PRECHARGE_EN_TIME_CFG BIT(2)
+#define LN9310_CFG_4_SW1_VGS_SHORT_EN_MSK BIT(3)
+#define LN9310_CFG_4_SC_OUT_PRECHARGE_EN_TIME_CFG_MASK 0x04
+#define LN9310_CFG_4_SW1_VGS_SHORT_EN_MSK_MASK 0x08
+#define LN9310_CFG_4_BSTH_BSTL_HIGH_ROUT_CFG_MASK 0xC0
+#define LN9310_CFG_4_SC_OUT_PRECHARGE_EN_TIME_CFG_ON 0x04
+#define LN9310_CFG_4_SW1_VGS_SHORT_EN_MSK_OFF 0x00
+#define LN9310_CFG_4_BSTH_BSTL_HIGH_ROUT_CFG_LOWEST 0x00
+
+#define LN9310_REG_CFG_5 0x41
+#define LN9310_CFG_5_INGATE_PD_EN_MASK 0xC0
+#define LN9310_CFG_5_INGATE_PD_EN_OFF 0x00
+#define LN9310_CFG_5_INFET_CP_PD_BIAS_CFG_MASK 0x30
+#define LN9310_CFG_5_INFET_CP_PD_BIAS_CFG_LOWEST 0x00
+
+#define LN9310_REG_TEST_MODE_CTRL 0x46
+#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_MASK 0x40
+#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_ON 0x40
+#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_OFF 0x00
+#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_MASK 0x20
+#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_ON 0x20
+#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_OFF 0x00
+
+#define LN9310_REG_FORCE_SC21_CTRL_1 0x49
+#define LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_MASK 0xFF
+#define LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_ON 0x59
+#define LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_OFF 0x40
+
+#define LN9310_REG_FORCE_SC21_CTRL_2 0x4A
+#define LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_MASK 0x80
+#define LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_ON 0x80
+#define LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_OFF 0x00
+
+#define LN9310_REG_SWAP_CTRL_0 0x58
+#define LN9310_REG_SWAP_CTRL_1 0x59
+#define LN9310_REG_SWAP_CTRL_2 0x5A
+#define LN9310_REG_SWAP_CTRL_3 0x5B
+
+#define LN9310_REG_BC_STS_B 0x51
+#define LN9310_BC_STS_B_INFET_OUT_SWITCH_OK BIT(5)
+#define LN9310_BC_STS_B_INFET_OUT_SWITCH_OK_MASK 0x20
+
+#define LN9310_REG_BC_STS_C 0x52
+#define LN9310_BC_STS_C_CHIP_REV_MASK 0xF0
+#define LN9310_BC_STS_C_CHIP_REV_FIXED 0x40
+
+/* LN9310 Timing definition */
+#define LN9310_CDC_DELAY 120 /* 120us */
+#define LN9310_CFLY_PRECHARGE_DELAY (12 * MSEC)
+#define LN9310_CFLY_PRECHARGE_TIMEOUT (100 * MSEC)
+
+/* LN9310 Driver Configuration */
+#define LN9310_INIT_RETRY_COUNT 3
+
+/* Define configuration of LN9310 part */
+struct ln9310_config_t {
+	const int i2c_port;
+	const int i2c_addr_flags;
+};
+
+/* Configuration struct defined at board level */
+extern const struct ln9310_config_t ln9310_config;
+
+/**
+ * @brief Init the driver
+ *
+ * @return EC_SUCCESS when initialization was complete.
+ */
+int ln9310_init(void);
+
+/* Enable/disable the ln9310 output */
+void ln9310_software_enable(int enable);
+
+/* Interrupt handler */
+void ln9310_interrupt(enum gpio_signal signal);
+
+/* Return the POWER_GOOD status */
+int ln9310_power_good(void);
+
+/* Battery cell type */
+enum battery_cell_type {
+	BATTERY_CELL_TYPE_UNKNOWN = 0,
+	BATTERY_CELL_TYPE_2S = 2,
+	BATTERY_CELL_TYPE_3S = 3
+};
+
+enum battery_cell_type board_get_battery_cell_type(void);
+
+/**
+ *  @brief Resets LN9310 Driver State
+ */
+__test_only void ln9310_reset_to_initial_state(void);
+
+#endif /* __CROS_EC_LN9310_H */
diff --git a/include/driver/mag_bmm150.h b/include/driver/mag_bmm150.h
new file mode 100644
index 0000000000..0325e6c5fc
--- /dev/null
+++ b/include/driver/mag_bmm150.h
@@ -0,0 +1,146 @@
+/* Copyright 2015 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* BMM150 magnetometer definition */
+
+#ifndef __CROS_EC_MAG_BMM150_H
+#define __CROS_EC_MAG_BMM150_H
+
+#include "accelgyro.h"
+#include "mag_cal.h"
+
+#define BMM150_ADDR0_FLAGS 0x10
+#define BMM150_ADDR1_FLAGS 0x11
+#define BMM150_ADDR2_FLAGS 0x12
+#define BMM150_ADDR3_FLAGS 0x13
+
+#define BMM150_CHIP_ID 0x40
+#define BMM150_CHIP_ID_MAJOR 0x32
+
+#define BMM150_BASE_DATA 0x42
+
+#define BMM150_INT_STATUS 0x4a
+#define BMM150_PWR_CTRL 0x4b
+#define BMM150_SRST (BIT(7) | BIT(1))
+#define BMM150_PWR_ON BIT(0)
+
+#define BMM150_OP_CTRL 0x4c
+#define BMM150_OP_MODE_OFFSET 1
+#define BMM150_OP_MODE_MASK 3
+#define BMM150_OP_MODE_NORMAL 0x00
+#define BMM150_OP_MODE_FORCED 0x01
+#define BMM150_OP_MODE_SLEEP 0x03
+
+#define BMM150_INT_CTRL 0x4d
+
+#define BMM150_REPXY 0x51
+#define BMM150_LOW_POWER_nXY 3
+#define BMM150_REGULAR_nXY 9
+#define BMM150_ENHANCED_nXY 15
+#define BMM150_HIGH_ACCURACY_nXY 47
+#define BMM150_SPECIAL_nXY 75
+#define BMM150_REPZ 0x52
+#define BMM150_LOW_POWER_nZ 3
+#define BMM150_REGULAR_nZ 15
+#define BMM150_ENHANCED_nZ 27
+#define BMM150_HIGH_ACCURACY_nZ 83
+#define BMM150_SPECIAL_nZ 27
+
+#define BMM150_REP(_preset, _axis) CONCAT4(BMM150_, _preset, _n, _axis)
+
+/* Hidden registers for RHALL calculation */
+#define BMM150_REGA_DIG_X1 0x5d
+#define BMM150_REGA_DIG_Y1 0x5e
+#define BMM150_REGA_DIG_Z4_LSB 0x62
+#define BMM150_REGA_DIG_Z4_MSB 0x63
+#define BMM150_REGA_DIG_X2 0x64
+#define BMM150_REGA_DIG_Y2 0x65
+#define BMM150_REGA_DIG_Z2_LSB 0x68
+#define BMM150_REGA_DIG_Z2_MSB 0x69
+#define BMM150_REGA_DIG_Z1_LSB 0x6a
+#define BMM150_REGA_DIG_Z1_MSB 0x6b
+#define BMM150_REGA_DIG_XYZ1_LSB 0x6c
+#define BMM150_REGA_DIG_XYZ1_MSB 0x6d
+#define BMM150_REGA_DIG_Z3_LSB 0x6e
+#define BMM150_REGA_DIG_Z3_MSB 0x6f
+#define BMM150_REGA_DIG_XY2 0x70
+#define BMM150_REGA_DIG_XY1 0x71
+
+/* Overflow */
+
+#define BMM150_FLIP_OVERFLOW_ADCVAL (-4096)
+#define BMM150_HALL_OVERFLOW_ADCVAL (-16384)
+#define BMM150_OVERFLOW_OUTPUT (0x8000)
+
+/* Min and Max sampling frequency in mHz */
+#define BMM150_MAG_MIN_FREQ 781
+
+/*
+ * From Section 4.2.4, max frequency depends on the preset.
+ *
+ *  Fmax ~= 1 / (145us * nXY + 500us * nZ + 980us)
+ *
+ *  To be safe, declare only 75% of the value.
+ */
+#define __BMM150_MAG_MAX_FREQ(_preset) \
+	(750000000 /                   \
+	 (145 * BMM150_REP(_preset, XY) + 500 * BMM150_REP(_preset, Z) + 980))
+
+#if (__BMM150_MAG_MAX_FREQ(SPECIAL) > CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ)
+#error "EC too slow for magnetometer"
+#endif
+
+struct bmm150_comp_registers {
+	/* Local copy of the compensation registers. */
+	int8_t dig1[2];
+	int8_t dig2[2];
+
+	uint16_t dig_z1;
+	int16_t dig_z2;
+	int16_t dig_z3;
+	int16_t dig_z4;
+
+	uint8_t dig_xy1;
+	int8_t dig_xy2;
+
+	uint16_t dig_xyz1;
+};
+
+struct bmm150_private_data {
+	/* lsm6dsm_data union requires cal be first element */
+	struct mag_cal_t cal;
+	struct bmm150_comp_registers comp;
+};
+
+#ifdef CONFIG_MAG_BMI_BMM150
+#include "accelgyro_bmi_common.h"
+
+#define BMM150_COMP_REG(_s) (&BMI_GET_DATA(_s)->compass.comp)
+
+#define BMM150_CAL(_s) (&BMI_GET_DATA(_s)->compass.cal)
+/*
+ * Behind a BMI, the BMM150 is in forced mode. Be sure to choose a frequency
+ * compatible with BMI.
+ */
+#define BMM150_MAG_MAX_FREQ(_preset) \
+	BMI_REG_TO_ODR(BMI_ODR_TO_REG(__BMM150_MAG_MAX_FREQ(_preset)))
+#else
+#define BMM150_COMP_REG(_s) NULL
+#define BMM150_CAL(_s) NULL
+#define BMM150_MAG_MAX_FREQ(_preset) __BMM150_MAG_MAX_FREQ(_preset)
+#endif
+
+/* Specific initialization of BMM150 when behing BMI160 */
+int bmm150_init(struct motion_sensor_t *s);
+
+/* Command to normalize and apply temperature compensation */
+void bmm150_normalize(const struct motion_sensor_t *s, intv3_t v,
+		      uint8_t *data);
+
+int bmm150_set_offset(const struct motion_sensor_t *s, const intv3_t offset);
+
+int bmm150_get_offset(const struct motion_sensor_t *s, intv3_t offset);
+
+#endif /* __CROS_EC_MAG_BMM150_H */
diff --git a/include/driver/ppc/aoz1380_public.h b/include/driver/ppc/aoz1380_public.h
new file mode 100644
index 0000000000..aa617054fe
--- /dev/null
+++ b/include/driver/ppc/aoz1380_public.h
@@ -0,0 +1,43 @@
+/* Copyright 2019 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * AOZ1380 USB-C Power Path Controller
+ *
+ * This is a basic TCPM controlled PPC driver.  It could easily be
+ * renamed and repurposed to be generic, if there are other TCPM
+ * controlled PPC chips that are similar to the AOZ1380
+ */
+
+#ifndef __CROS_EC_AOZ1380_PUBLIC_H
+#define __CROS_EC_AOZ1380_PUBLIC_H
+
+#include "usb_pd_tcpm.h"
+
+struct ppc_drv;
+extern const struct ppc_drv aoz1380_drv;
+
+/**
+ * AOZ1380 Set VBus Source Current Limit.
+ *
+ * Using this driver requires a board_aoz1380_set_vbus_source_limit
+ * function due to the lack of programability of this device and
+ * requirement for hardware specific code to handle setting this limit.
+ *
+ * @param port The Type-C port
+ * @param rp The Type-C RP value
+ * @return EC_SUCCESS for success, otherwise error
+ */
+int board_aoz1380_set_vbus_source_current_limit(int port,
+						enum tcpc_rp_value rp);
+
+/**
+ * Interrupt Handler for the AOZ1380.
+ *
+ * @param port: The Type-C port which triggered the interrupt.
+ */
+void aoz1380_interrupt(int port);
+
+#endif /* defined(__CROS_EC_AOZ1380_H) */
diff --git a/include/driver/ppc/ktu1125_public.h b/include/driver/ppc/ktu1125_public.h
new file mode 100644
index 0000000000..28ecfc7c23
--- /dev/null
+++ b/include/driver/ppc/ktu1125_public.h
@@ -0,0 +1,25 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Kinetic KTU1125 USB-C Power Path Controller */
+
+#ifndef __CROS_EC_DRIVER_PPC_KTU1125_PUBLIC_H
+#define __CROS_EC_DRIVER_PPC_KTU1125_PUBLIC_H
+
+#define KTU1125_ADDR0_FLAGS 0x78
+#define KTU1125_ADDR1_FLAGS 0x79
+#define KTU1125_ADDR2_FLAGS 0x7A
+#define KTU1125_ADDR3_FLAGS 0x7B
+
+extern const struct ppc_drv ktu1125_drv;
+
+/**
+ * Interrupt Handler for the KTU1125.
+ *
+ * @param port: The Type-C port which triggered the interrupt.
+ */
+void ktu1125_interrupt(int port);
+
+#endif /* __CROS_EC_DRIVER_PPC_KTU1125_PUBLIC_H */
diff --git a/include/driver/ppc/nx20p348x_public.h b/include/driver/ppc/nx20p348x_public.h
new file mode 100644
index 0000000000..145896aca1
--- /dev/null
+++ b/include/driver/ppc/nx20p348x_public.h
@@ -0,0 +1,32 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* TI NX20P348X USB-C Power Path Controller */
+
+#ifndef __CROS_EC_DRIVER_PPC_NX20P348X_PUBLIC_H
+#define __CROS_EC_DRIVER_PPC_NX20P348X_PUBLIC_H
+
+#include "usbc_ppc.h"
+
+#define NX20P3483_ADDR0_FLAGS 0x70
+#define NX20P3483_ADDR1_FLAGS 0x71
+#define NX20P3483_ADDR2_FLAGS 0x72
+#define NX20P3483_ADDR3_FLAGS 0x73
+
+#define NX20P3481_ADDR0_FLAGS 0x74
+#define NX20P3481_ADDR1_FLAGS 0x75
+#define NX20P3481_ADDR2_FLAGS 0x76
+#define NX20P3481_ADDR3_FLAGS 0x77
+
+extern const struct ppc_drv nx20p348x_drv;
+
+/**
+ * Interrupt Handler for the NX20P348x.
+ *
+ * @param port: The Type-C port which triggered the interrupt.
+ */
+void nx20p348x_interrupt(int port);
+
+#endif /* __CROS_EC_DRIVER_PPC_NX20P348X_PUBLIC_H */
diff --git a/include/driver/ppc/sn5s330_public.h b/include/driver/ppc/sn5s330_public.h
new file mode 100644
index 0000000000..62652d99b2
--- /dev/null
+++ b/include/driver/ppc/sn5s330_public.h
@@ -0,0 +1,29 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* TI SN5S330 USB-C Power Path Controller */
+
+#ifndef __CROS_EC_DRIVER_PPC_SN5S330_PUBLIC_H
+#define __CROS_EC_DRIVER_PPC_SN5S330_PUBLIC_H
+
+#define SN5S330_ADDR0_FLAGS 0x40
+#define SN5S330_ADDR1_FLAGS 0x41
+#define SN5S330_ADDR2_FLAGS 0x42
+#define SN5S330_ADDR3_FLAGS 0x43
+
+extern const struct ppc_drv sn5s330_drv;
+
+/**
+ * Interrupt Handler for the SN5S330.
+ *
+ * By default, the only interrupt sources that are unmasked are overcurrent
+ * conditions for PP1, and VBUS_GOOD if PPC is being used to detect VBUS
+ * (CONFIG_USB_PD_VBUS_DETECT_PPC).
+ *
+ * @param port: The Type-C port which triggered the interrupt.
+ */
+void sn5s330_interrupt(int port);
+
+#endif /* __CROS_EC_DRIVER_PPC_SN5S330_PUBLIC_H */
diff --git a/include/driver/ppc/syv682x_public.h b/include/driver/ppc/syv682x_public.h
new file mode 100644
index 0000000000..a97d412478
--- /dev/null
+++ b/include/driver/ppc/syv682x_public.h
@@ -0,0 +1,21 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Silergy SYV682x Type-C Power Path Controller */
+
+#ifndef __CROS_EC_DRIVER_PPC_SYV682X_PUBLIC_H
+#define __CROS_EC_DRIVER_PPC_SYV682X_PUBLIC_H
+
+/* I2C addresses */
+#define SYV682X_ADDR0_FLAGS 0x40
+#define SYV682X_ADDR1_FLAGS 0x41
+#define SYV682X_ADDR2_FLAGS 0x42
+#define SYV682X_ADDR3_FLAGS 0x43
+
+extern const struct ppc_drv syv682x_drv;
+
+void syv682x_interrupt(int port);
+
+#endif /* __CROS_EC_DRIVER_PPC_SYV682X_PUBLIC_H */
diff --git a/include/driver/pse_ltc4291.h b/include/driver/pse_ltc4291.h
new file mode 100644
index 0000000000..4db9ac4998
--- /dev/null
+++ b/include/driver/pse_ltc4291.h
@@ -0,0 +1,60 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * The LTC4291 is a power over ethernet (PoE) power sourcing equipment (PSE)
+ * controller.
+ */
+
+#include "i2c.h"
+#include "timer.h"
+#include "util.h"
+
+#define LTC4291_I2C_ADDR 0x2C
+
+#define LTC4291_REG_SUPEVN_COR 0x0B
+#define LTC4291_REG_STATPWR 0x10
+#define LTC4291_REG_STATPIN 0x11
+#define LTC4291_REG_OPMD 0x12
+#define LTC4291_REG_DISENA 0x13
+#define LTC4291_REG_DETENA 0x14
+#define LTC4291_REG_DETPB 0x18
+#define LTC4291_REG_PWRPB 0x19
+#define LTC4291_REG_RSTPB 0x1A
+#define LTC4291_REG_ID 0x1B
+#define LTC4291_REG_DEVID 0x43
+#define LTC4291_REG_HPMD1 0x46
+#define LTC4291_REG_HPMD2 0x4B
+#define LTC4291_REG_HPMD3 0x50
+#define LTC4291_REG_HPMD4 0x55
+#define LTC4291_REG_LPWRPB 0x6E
+
+#define LTC4291_FLD_STATPIN_AUTO BIT(0)
+#define LTC4291_FLD_RSTPB_RSTALL BIT(4)
+
+#define LTC4291_STATPWR_ON_PORT(port) (0x01 << (port))
+#define LTC4291_DETENA_EN_PORT(port) (0x11 << (port))
+#define LTC4291_DETPB_EN_PORT(port) (0x11 << (port))
+#define LTC4291_PWRPB_OFF_PORT(port) (0x10 << (port))
+
+#define LTC4291_OPMD_AUTO 0xFF
+#define LTC4291_DISENA_ALL 0x0F
+#define LTC4291_DETENA_ALL 0xFF
+#define LTC4291_ID 0x64
+#define LTC4291_DEVID 0x38
+#define LTC4291_HPMD_MIN 0x00
+#define LTC4291_HPMD_MAX 0xA8
+
+#define LTC4291_PORT_MAX 4
+
+#define LTC4291_RESET_DELAY_US (20 * MSEC)
+
+#define I2C_PSE_READ(reg, data) \
+	i2c_read8(I2C_PORT_PSE, LTC4291_I2C_ADDR, LTC4291_REG_##reg, (data))
+
+#define I2C_PSE_WRITE(reg, data) \
+	i2c_write8(I2C_PORT_PSE, LTC4291_I2C_ADDR, LTC4291_REG_##reg, (data))
+
+extern const int pse_port_hpmd[LTC4291_PORT_MAX];
diff --git a/include/driver/retimer/anx7452_public.h b/include/driver/retimer/anx7452_public.h
new file mode 100644
index 0000000000..ffd8497836
--- /dev/null
+++ b/include/driver/retimer/anx7452_public.h
@@ -0,0 +1,26 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * ANX7452: Active redriver
+ *
+ * Public functions, definitions, and structures.
+ */
+
+#ifndef __CROS_EC_USB_RETIMER_ANX7452_PUBLIC_H
+#define __CROS_EC_USB_RETIMER_ANX7452_PUBLIC_H
+
+#include "usb_mux.h"
+
+extern const struct usb_mux_driver anx7452_usb_retimer_driver;
+
+/* Retimer driver hardware specific controls */
+struct anx7452_control {
+	/* USB enable */
+	const enum gpio_signal usb_enable_gpio;
+	/* DP enable */
+	const enum gpio_signal dp_enable_gpio;
+};
+extern const struct anx7452_control anx7452_controls[];
+
+#endif /* __CROS_EC_USB_RETIMER_ANX7452_PUBLIC_H */
diff --git a/include/driver/retimer/anx7483_public.h b/include/driver/retimer/anx7483_public.h
new file mode 100644
index 0000000000..4f44c4d180
--- /dev/null
+++ b/include/driver/retimer/anx7483_public.h
@@ -0,0 +1,75 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * ANX7483: Active redriver with linear equilzation
+ *
+ * Public functions, definitions, and structures.
+ */
+
+#ifndef __CROS_EC_USB_RETIMER_ANX7483_PUBLIC_H
+#define __CROS_EC_USB_RETIMER_ANX7483_PUBLIC_H
+
+#include "usb_mux.h"
+
+/* I2C interface addresses */
+#define ANX7483_I2C_ADDR0_FLAGS 0x3E
+#define ANX7483_I2C_ADDR1_FLAGS 0x38
+#define ANX7483_I2C_ADDR2_FLAGS 0x40
+#define ANX7483_I2C_ADDR3_FLAGS 0x44
+
+/* Equalization tuning */
+enum anx7483_eq_setting {
+	ANX7483_EQ_SETTING_3_9DB = 0,
+	ANX7483_EQ_SETTING_4_7DB = 1,
+	ANX7483_EQ_SETTING_5_5DB = 2,
+	ANX7483_EQ_SETTING_6_1DB = 3,
+	ANX7483_EQ_SETTING_6_8DB = 4,
+	ANX7483_EQ_SETTING_7_3DB = 5,
+	ANX7483_EQ_SETTING_7_8DB = 6,
+	ANX7483_EQ_SETTING_8_1DB = 7,
+	ANX7483_EQ_SETTING_8_4DB = 8,
+	ANX7483_EQ_SETTING_8_7DB = 9,
+	ANX7483_EQ_SETTING_9_2DB = 10,
+	ANX7483_EQ_SETTING_9_7DB = 11,
+	ANX7483_EQ_SETTING_10_3DB = 12,
+	ANX7483_EQ_SETTING_11_1DB = 13,
+	ANX7483_EQ_SETTING_11_8DB = 14,
+	ANX7483_EQ_SETTING_12_5DB = 15,
+};
+
+/* Flat gain tuning */
+enum anx7483_fg_setting {
+	ANX7483_FG_SETTING_NEG_1_5DB = 0,
+	ANX7483_FG_SETTING_0_5DB = 1,
+	ANX7483_FG_SETTING_0_3DB = 2,
+	ANX7483_FG_SETTING_1_2DB = 3,
+};
+
+enum anx7483_tune_pin {
+	ANX7483_PIN_UTX1,
+	ANX7483_PIN_UTX2,
+	ANX7483_PIN_URX1,
+	ANX7483_PIN_URX2,
+	ANX7483_PIN_DRX1,
+	ANX7483_PIN_DRX2,
+};
+
+/* Adjust the equalization for a pin */
+enum ec_error_list anx7483_set_eq(const struct usb_mux *me,
+				  enum anx7483_tune_pin pin,
+				  enum anx7483_eq_setting eq);
+
+/* Adjust the flat gain for a pin */
+enum ec_error_list anx7483_set_fg(const struct usb_mux *me,
+				  enum anx7483_tune_pin pin,
+				  enum anx7483_fg_setting fg);
+
+/*
+ * Configure datasheet defaults for tuning registers at this mux setting.
+ * Return int so function can be used directly for board_set.
+ */
+int anx7483_set_default_tuning(const struct usb_mux *me, mux_state_t mux_state);
+
+extern const struct usb_mux_driver anx7483_usb_retimer_driver;
+#endif /* __CROS_EC_USB_RETIMER_ANX7483_PUBLIC_H */
diff --git a/include/driver/retimer/bb_retimer.h b/include/driver/retimer/bb_retimer.h
new file mode 100644
index 0000000000..b47743f882
--- /dev/null
+++ b/include/driver/retimer/bb_retimer.h
@@ -0,0 +1,55 @@
+/* Copyright 2019 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Driver header for Intel Burnside Bridge - Thunderbolt/USB/DisplayPort Retimer
+ */
+
+#ifndef __CROS_EC_BB_RETIMER_H
+#define __CROS_EC_BB_RETIMER_H
+
+#include "driver/retimer/bb_retimer_public.h"
+#include "usb_mux.h"
+
+/* Burnside Bridge I2C Configuration Space */
+#define BB_RETIMER_REG_VENDOR_ID 0
+#define BB_RETIMER_VENDOR_ID_1 0x8086
+#define BB_RETIMER_VENDOR_ID_2 0x8087
+
+#define BB_RETIMER_REG_DEVICE_ID 1
+#ifdef CONFIG_USBC_RETIMER_INTEL_HB
+/* HB has no Device ID field instead it is combined with Vendor ID */
+#define BB_RETIMER_DEVICE_ID 0x0D9C8087
+#else
+#define BB_RETIMER_DEVICE_ID 0x15EE
+#endif
+
+/* Connection State Register Attributes */
+#define BB_RETIMER_REG_CONNECTION_STATE 4
+#define BB_RETIMER_DATA_CONNECTION_PRESENT BIT(0)
+#define BB_RETIMER_CONNECTION_ORIENTATION BIT(1)
+#define BB_RETIMER_RE_TIMER_DRIVER BIT(2)
+#define BB_RETIMER_USB_2_CONNECTION BIT(4)
+#define BB_RETIMER_USB_3_CONNECTION BIT(5)
+#define BB_RETIMER_USB_3_SPEED BIT(6)
+#define BB_RETIMER_USB_DATA_ROLE BIT(7)
+#define BB_RETIMER_DP_CONNECTION BIT(8)
+#define BB_RETIMER_DP_PIN_ASSIGNMENT BIT(10)
+#define BB_RETIMER_IRQ_HPD BIT(14)
+#define BB_RETIMER_HPD_LVL BIT(15)
+#define BB_RETIMER_TBT_CONNECTION BIT(16)
+#define BB_RETIMER_TBT_TYPE BIT(17)
+#define BB_RETIMER_TBT_CABLE_TYPE BIT(18)
+#define BB_RETIMER_VPRO_DOCK_DP_OVERDRIVE BIT(19)
+#define BB_RETIMER_TBT_ACTIVE_LINK_TRAINING BIT(20)
+#define BB_RETIMER_ACTIVE_PASSIVE BIT(22)
+#define BB_RETIMER_USB4_ENABLED BIT(23)
+#define BB_RETIMER_USB4_TBT_CABLE_SPEED_SUPPORT(x) (((x)&0x7) << 25)
+#define BB_RETIMER_TBT_CABLE_GENERATION(x) (((x)&0x3) << 28)
+
+#define BB_RETIMER_REG_TBT_CONTROL 5
+#define BB_RETIMER_REG_EXT_CONNECTION_MODE 7
+
+#define BB_RETIMER_REG_COUNT 8
+
+#endif /* __CROS_EC_BB_RETIMER_H */
diff --git a/include/driver/retimer/bb_retimer_public.h b/include/driver/retimer/bb_retimer_public.h
new file mode 100644
index 0000000000..fd63d81a35
--- /dev/null
+++ b/include/driver/retimer/bb_retimer_public.h
@@ -0,0 +1,67 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Public header for Intel Burnside Bridge - Thunderbolt/USB/DisplayPort Retimer
+ */
+
+#ifndef __CROS_EC_DRIVER_RETIMER_BB_RETIMER_PUBLIC_H
+#define __CROS_EC_DRIVER_RETIMER_BB_RETIMER_PUBLIC_H
+
+#include "usb_mux.h"
+
+struct usb_mux;
+
+/* Supported USB retimer drivers */
+extern const struct usb_mux_driver bb_usb_retimer;
+
+/* Retimer driver hardware specific controls */
+struct bb_usb_control {
+	/* Load switch enable */
+	enum gpio_signal usb_ls_en_gpio;
+	/* Retimer reset */
+	enum gpio_signal retimer_rst_gpio;
+};
+
+#ifndef CONFIG_USBC_RETIMER_INTEL_BB_RUNTIME_CONFIG
+extern const struct bb_usb_control bb_controls[];
+#else
+extern struct bb_usb_control bb_controls[];
+#endif
+
+/**
+ * Enable/disable the power state of BB retimer
+ *
+ * Define override function at board level if the platform specific changes
+ * are needed to enable/disable the power state of BB retimer.
+ *
+ * @param me     Pointer to USB mux
+ * @param enable BB retimer power state to be changed
+ *
+ * @return EC_SUCCESS, or non-zero on error.
+ */
+__override_proto int bb_retimer_power_enable(const struct usb_mux *me,
+					     bool enable);
+
+/**
+ * Set HPD on the BB retimer
+ *
+ * Set the HPD related fields in the BB retimer
+ *
+ * @param[in]  me		Pointer to USB mux
+ * @param[in]  mux_state	USB mux state containing HPD level and IRQ
+ * @param[out] ack_required	Outputs whether the given change will require
+ *				the AP to ACK before proceeding
+ */
+void bb_retimer_hpd_update(const struct usb_mux *me, mux_state_t hpd_state,
+			   bool *ack_required);
+
+/**
+ * Enable/disable the DP state of BB retimer
+ *
+ * @param me     Pointer to USB mux
+ * @param enable BB retimer DP state to be changed
+ */
+int bb_retimer_set_dp_connection(const struct usb_mux *me, bool enable);
+
+#endif /* __CROS_EC_DRIVER_RETIMER_BB_RETIMER_PUBLIC_H */
diff --git a/include/driver/retimer/kb8010_public.h b/include/driver/retimer/kb8010_public.h
new file mode 100644
index 0000000000..401e5d85ff
--- /dev/null
+++ b/include/driver/retimer/kb8010_public.h
@@ -0,0 +1,24 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * KB8010: Active redriver
+ *
+ * Public functions, definitions, and structures.
+ */
+
+#ifndef __CROS_EC_USB_RETIMER_KB8010_PUBLIC_H
+#define __CROS_EC_USB_RETIMER_KB8010_PUBLIC_H
+
+#include "usb_mux.h"
+
+extern const struct usb_mux_driver kb8010_usb_retimer_driver;
+
+/* Retimer driver hardware specific controls */
+struct kb8010_control {
+	/* Retimer reset */
+	enum gpio_signal retimer_rst_gpio;
+};
+extern const struct kb8010_control kb8010_controls[];
+
+#endif /* __CROS_EC_USB_RETIMER_KB8010_PUBLIC_H */
diff --git a/include/driver/retimer/ps8818_public.h b/include/driver/retimer/ps8818_public.h
new file mode 100644
index 0000000000..bdecb7a0d4
--- /dev/null
+++ b/include/driver/retimer/ps8818_public.h
@@ -0,0 +1,99 @@
+/* Copyright 2019 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * PS8818 retimer.
+ */
+#include "usb_mux.h"
+
+#ifndef __CROS_EC_USB_RETIMER_PS8818_H
+#define __CROS_EC_USB_RETIMER_PS8818_H
+
+#define PS8818_I2C_ADDR0_FLAGS 0x28
+#define PS8818_I2C_ADDR1_FLAGS 0x30
+#define PS8818_I2C_ADDR2_FLAGS 0x58
+#define PS8818_I2C_ADDR3_FLAGS 0x70
+
+/*
+ * PAGE 0 Register Definitions
+ */
+#define PS8818_REG_PAGE0 0x00
+
+#define PS8818_REG0_FLIP 0x00
+#define PS8818_FLIP_CONFIG BIT(7)
+#define PS8818_FLIP_NON_RESERVED_MASK 0xE0
+
+#define PS8818_REG0_MODE 0x01
+#define PS8818_MODE_DP_ENABLE BIT(7)
+#define PS8818_MODE_USB_ENABLE BIT(6)
+#define PS8818_MODE_NON_RESERVED_MASK 0xC0
+
+#define PS8818_REG0_DPHPD_CONFIG 0x02
+#define PS8818_DPHPD_CONFIG_INHPD_DISABLE BIT(7)
+#define PS8818_DPHPD_PLUGGED BIT(6)
+#define PS8818_DPHPD_NON_RESERVED_MASK 0xFC
+
+/*
+ * PAGE 1 Register Definitions
+ */
+#define PS8818_REG_PAGE1 0x01
+
+#define PS8818_REG1_APTX1EQ_10G_LEVEL 0x00
+#define PS8818_REG1_APTX2EQ_10G_LEVEL 0x02
+#define PS8818_REG1_CRX1EQ_10G_LEVEL 0x08
+#define PS8818_REG1_CRX2EQ_10G_LEVEL 0x0A
+#define PS8818_REG1_APRX1_DE_LEVEL 0x0C
+#define PS8818_REG1_APTX1EQ_5G_LEVEL 0x70
+#define PS8818_REG1_APTX2EQ_5G_LEVEL 0x72
+#define PS8818_REG1_CRX1EQ_5G_LEVEL 0x78
+#define PS8818_REG1_CRX2EQ_5G_LEVEL 0x7A
+#define PS8818_EQ_LEVEL_UP_9DB (0)
+#define PS8818_EQ_LEVEL_UP_10DB (1)
+#define PS8818_EQ_LEVEL_UP_12DB (2)
+#define PS8818_EQ_LEVEL_UP_13DB (3)
+#define PS8818_EQ_LEVEL_UP_16DB (4)
+#define PS8818_EQ_LEVEL_UP_17DB (5)
+#define PS8818_EQ_LEVEL_UP_18DB (6)
+#define PS8818_EQ_LEVEL_UP_19DB (7)
+#define PS8818_EQ_LEVEL_UP_20DB (8)
+#define PS8818_EQ_LEVEL_UP_21DB (9)
+#define PS8818_EQ_LEVEL_UP_MASK (0x0F)
+
+#define PS8818_REG1_RX_PHY 0x6D
+#define PS8818_RX_INPUT_TERM_112_OHM (0 << 6)
+#define PS8818_RX_INPUT_TERM_104_OHM (1 << 6)
+#define PS8818_RX_INPUT_TERM_96_OHM (2 << 6)
+#define PS8818_RX_INPUT_TERM_85_OHM (3 << 6)
+#define PS8818_RX_INPUT_TERM_MASK (3 << 6)
+
+#define PS8818_REG1_DPEQ_LEVEL 0xB6
+#define PS8818_DPEQ_LEVEL_UP_9DB (0 << 3)
+#define PS8818_DPEQ_LEVEL_UP_10DB (1 << 3)
+#define PS8818_DPEQ_LEVEL_UP_12DB (2 << 3)
+#define PS8818_DPEQ_LEVEL_UP_13DB (3 << 3)
+#define PS8818_DPEQ_LEVEL_UP_16DB (4 << 3)
+#define PS8818_DPEQ_LEVEL_UP_17DB (5 << 3)
+#define PS8818_DPEQ_LEVEL_UP_18DB (6 << 3)
+#define PS8818_DPEQ_LEVEL_UP_19DB (7 << 3)
+#define PS8818_DPEQ_LEVEL_UP_20DB (8 << 3)
+#define PS8818_DPEQ_LEVEL_UP_21DB (9 << 3)
+#define PS8818_DPEQ_LEVEL_UP_MASK (0x0F << 3)
+
+/*
+ * PAGE 2 Register Definitions
+ */
+#define PS8818_REG_PAGE2 0x02
+
+#define PS8818_REG2_TX_STATUS 0x42
+#define PS8818_REG2_RX_STATUS 0x46
+#define PS8818_STATUS_NORMAL_OPERATION BIT(7)
+#define PS8818_STATUS_10_GBPS BIT(5)
+
+extern const struct usb_mux_driver ps8818_usb_retimer_driver;
+
+int ps8818_i2c_read(const struct usb_mux *me, int page, int offset, int *data);
+int ps8818_i2c_write(const struct usb_mux *me, int page, int offset, int data);
+int ps8818_i2c_field_update8(const struct usb_mux *me, int page, int offset,
+			     uint8_t field_mask, uint8_t set_value);
+
+#endif /* __CROS_EC_USB_RETIMER_PS8818_H */
diff --git a/include/driver/tcpm/anx7447_public.h b/include/driver/tcpm/anx7447_public.h
new file mode 100644
index 0000000000..5ea1eebd35
--- /dev/null
+++ b/include/driver/tcpm/anx7447_public.h
@@ -0,0 +1,28 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Analogix Type-C port controller */
+
+#ifndef __CROS_EC_DRIVER_TCPM_ANX7447_PUBLIC_H
+#define __CROS_EC_DRIVER_TCPM_ANX7447_PUBLIC_H
+
+#include "usb_mux.h"
+
+#define AN7447_TCPC0_I2C_ADDR_FLAGS 0x2C
+#define AN7447_TCPC1_I2C_ADDR_FLAGS 0x2B
+#define AN7447_TCPC2_I2C_ADDR_FLAGS 0x2A
+#define AN7447_TCPC3_I2C_ADDR_FLAGS 0x29
+
+#define AN7447_SPI0_I2C_ADDR_FLAGS 0x3F
+#define AN7447_SPI1_I2C_ADDR_FLAGS 0x37
+#define AN7447_SPI2_I2C_ADDR_FLAGS 0x32
+#define AN7447_SPI3_I2C_ADDR_FLAGS 0x31
+
+extern const struct tcpm_drv anx7447_tcpm_drv;
+extern const struct usb_mux_driver anx7447_usb_mux_driver;
+
+void anx7447_tcpc_update_hpd_status(const struct usb_mux *me,
+				    mux_state_t mux_state, bool *ack_required);
+#endif /* __CROS_EC_DRIVER_TCPM_ANX7447_PUBLIC_H */
diff --git a/include/driver/tcpm/it8xxx2_pd_public.h b/include/driver/tcpm/it8xxx2_pd_public.h
new file mode 100644
index 0000000000..0c28127cdb
--- /dev/null
+++ b/include/driver/tcpm/it8xxx2_pd_public.h
@@ -0,0 +1,12 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_DRIVER_TCPM_IT8XXX2_PD_PUBLIC_H
+#define __CROS_EC_DRIVER_TCPM_IT8XXX2_PD_PUBLIC_H
+
+extern const struct tcpm_drv it83xx_tcpm_drv;
+extern const struct tcpm_drv it8xxx2_tcpm_drv;
+
+#endif /* __CROS_EC_DRIVER_TCPM_IT8XXX2_PD_PUBLIC_H */
diff --git a/include/driver/tcpm/ps8xxx_public.h b/include/driver/tcpm/ps8xxx_public.h
new file mode 100644
index 0000000000..1fdd264acd
--- /dev/null
+++ b/include/driver/tcpm/ps8xxx_public.h
@@ -0,0 +1,94 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Parade Tech Type-C port controller */
+
+#ifndef __CROS_EC_DRIVER_TCPM_PS8XXX_PUBLIC_H
+#define __CROS_EC_DRIVER_TCPM_PS8XXX_PUBLIC_H
+
+#include "usb_mux.h"
+
+/* I2C interface */
+#define PS8XXX_I2C_ADDR1_P1_FLAGS 0x09
+#define PS8XXX_I2C_ADDR1_P2_FLAGS 0x0A
+#define PS8XXX_I2C_ADDR1_FLAGS 0x0B /* P3 */
+#define PS8XXX_I2C_ADDR2_FLAGS 0x1B
+#define PS8XXX_I2C_ADDR3_FLAGS 0x2B
+#define PS8XXX_I2C_ADDR4_FLAGS 0x4B
+
+#define PS8XXX_VENDOR_ID 0x1DA0
+
+/* Minimum Delay for reset assertion */
+#define PS8XXX_RESET_DELAY_MS 1
+
+/* Delay between releasing reset and the first I2C read */
+#define PS8805_FW_INIT_DELAY_MS 10
+
+/* Delay from power on to reset de-asserted */
+#define PS8815_PWR_H_RST_H_DELAY_MS 20
+
+/*
+ * Add delay of writing TCPC_REG_POWER_CTRL makes
+ * CC status being judged correctly when disable VCONN.
+ * This may be a PS8XXX firmware issue, Parade is still trying.
+ * https://partnerissuetracker.corp.google.com/issues/185202064
+ */
+#define PS8XXX_VCONN_TURN_OFF_DELAY_US 10
+
+/*
+ * Delay between releasing reset and the first I2C read
+ *
+ * If the delay is too short, I2C fails.
+ * If the delay is marginal I2C reads return garbage.
+ *
+ * With firmware 0x03:
+ *   10ms is too short
+ *   20ms is marginal
+ *   25ms is OK
+ */
+#define PS8815_FW_INIT_DELAY_MS 50
+
+/* NOTE: The Product ID will read as 0x8803 if the firmware has malfunctioned in
+ * 8705, 8755 and 8805.
+ */
+#define PS8705_PRODUCT_ID 0x8705
+#define PS8745_PRODUCT_ID 0x8745
+#define PS8751_PRODUCT_ID 0x8751
+#define PS8755_PRODUCT_ID 0x8755
+#define PS8805_PRODUCT_ID 0x8805
+#define PS8815_PRODUCT_ID 0x8815
+
+extern const struct tcpm_drv ps8xxx_tcpm_drv;
+
+/**
+ * Board-specific callback to judge and provide which chip source of PS8XXX
+ * series supported by this driver per specific port.
+ *
+ * If the board supports only one single source then there is no nencessary to
+ * provide the __override version.
+ *
+ * If board supports two sources or above (with CONFIG_USB_PD_TCPM_MULTI_PS8XXX)
+ * then the __override version is mandatory.
+ *
+ * @param port	TCPC port number.
+ */
+__override_proto uint16_t board_get_ps8xxx_product_id(int port);
+
+void ps8xxx_tcpc_update_hpd_status(const struct usb_mux *me,
+				   mux_state_t mux_state, bool *ack_required);
+
+#ifdef CONFIG_CMD_I2C_STRESS_TEST_TCPC
+extern struct i2c_stress_test_dev ps8xxx_i2c_stress_test_dev;
+#endif /* defined(CONFIG_CMD_I2C_STRESS_TEST_TCPC) */
+
+/*
+ * This driver was designed to use Low Power Mode on PS8751 TCPC/MUX chip
+ * when running as MUX only (CC lines are not connected, eg. Ampton).
+ * To achieve this RP on CC lines is set when device should enter LPM and
+ * RD when mux should work.
+ */
+extern const struct usb_mux_driver ps8xxx_usb_mux_driver;
+
+#endif /* __CROS_EC_DRIVER_TCPM_PS8XXX_PUBLIC_H */
diff --git a/include/driver/tcpm/rt1715_public.h b/include/driver/tcpm/rt1715_public.h
new file mode 100644
index 0000000000..2f3af95443
--- /dev/null
+++ b/include/driver/tcpm/rt1715_public.h
@@ -0,0 +1,18 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Richtek RT1715 Type-C port controller */
+
+#ifndef __CROS_EC_DRIVER_TCPM_RT1715_PUBLIC_H
+#define __CROS_EC_DRIVER_TCPM_RT1715_PUBLIC_H
+
+/* I2C interface */
+#define RT1715_I2C_ADDR_FLAGS 0x4E
+
+#define RT1715_VENDOR_ID 0x29CF
+
+extern const struct tcpm_drv rt1715_tcpm_drv;
+
+#endif /* __CROS_EC_DRIVER_TCPM_RT1715_PUBLIC_H */
diff --git a/include/driver/tcpm/rt1718s_public.h b/include/driver/tcpm/rt1718s_public.h
new file mode 100644
index 0000000000..7a76c24af3
--- /dev/null
+++ b/include/driver/tcpm/rt1718s_public.h
@@ -0,0 +1,26 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Richtek Type-C port controller */
+
+#ifndef __CROS_EC_DRIVER_TCPM_RT1718S_PUBLIC_H
+#define __CROS_EC_DRIVER_TCPM_RT1718S_PUBLIC_H
+
+#include "usb_pd_tcpm.h"
+
+#define RT1718S_I2C_ADDR1_FLAGS 0x43
+#define RT1718S_I2C_ADDR2_FLAGS 0x40
+
+#define RT1718S_VID 0x29CF
+#define RT1718S_PID 0x1718
+
+#define RT1718S_DEVICE_ID 0x04
+#define RT1718S_DEVICE_ID_ES1 0x4511
+#define RT1718S_DEVICE_ID_ES2 0x4513
+
+extern const struct tcpm_drv rt1718s_tcpm_drv;
+extern const struct bc12_drv rt1718s_bc12_drv;
+
+#endif /* __CROS_EC_DRIVER_TCPM_RT1718S_PUBLIC_H */
diff --git a/include/driver/tcpm/tcpci.h b/include/driver/tcpm/tcpci.h
new file mode 100644
index 0000000000..b6fd23019a
--- /dev/null
+++ b/include/driver/tcpm/tcpci.h
@@ -0,0 +1,403 @@
+/* Copyright 2015 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* USB Power delivery port management */
+
+#ifndef __CROS_EC_USB_PD_TCPM_TCPCI_H
+#define __CROS_EC_USB_PD_TCPM_TCPCI_H
+
+#include "config.h"
+#include "ec_commands.h"
+#include "tcpm/tcpm.h"
+#include "usb_mux.h"
+#include "usb_pd_tcpm.h"
+
+#define TCPC_REG_VENDOR_ID 0x0
+#define TCPC_REG_PRODUCT_ID 0x2
+#define TCPC_REG_BCD_DEV 0x4
+#define TCPC_REG_TC_REV 0x6
+#define TCPC_REG_PD_REV 0x8
+#define TCPC_REG_PD_INT_REV 0xa
+
+#define TCPC_REG_PD_INT_REV_REV_MASK 0xff00
+#define TCPC_REG_PD_INT_REV_REV_1_0 0x10
+#define TCPC_REG_PD_INT_REV_REV_2_0 0x20
+#define TCPC_REG_PD_INT_REV_VER_MASK 0x00ff
+#define TCPC_REG_PD_INT_REV_VER_1_0 0x10
+#define TCPC_REG_PD_INT_REV_VER_1_1 0x11
+#define TCPC_REG_PD_INT_REV_REV(reg) ((reg & TCPC_REG_PD_INT_REV_REV_MASK) >> 8)
+#define TCPC_REG_PD_INT_REV_VER(reg) (reg & TCPC_REG_PD_INT_REV_VER_MASK)
+
+#define TCPC_REG_ALERT 0x10
+#define TCPC_REG_ALERT_NONE 0x0000
+#define TCPC_REG_ALERT_MASK_ALL 0xffff
+#define TCPC_REG_ALERT_VENDOR_DEF BIT(15)
+#define TCPC_REG_ALERT_ALERT_EXT BIT(14)
+#define TCPC_REG_ALERT_EXT_STATUS BIT(13)
+#define TCPC_REG_ALERT_RX_BEGINNING BIT(12)
+#define TCPC_REG_ALERT_VBUS_DISCNCT BIT(11)
+#define TCPC_REG_ALERT_RX_BUF_OVF BIT(10)
+#define TCPC_REG_ALERT_FAULT BIT(9)
+#define TCPC_REG_ALERT_V_ALARM_LO BIT(8)
+#define TCPC_REG_ALERT_V_ALARM_HI BIT(7)
+#define TCPC_REG_ALERT_TX_SUCCESS BIT(6)
+#define TCPC_REG_ALERT_TX_DISCARDED BIT(5)
+#define TCPC_REG_ALERT_TX_FAILED BIT(4)
+#define TCPC_REG_ALERT_RX_HARD_RST BIT(3)
+#define TCPC_REG_ALERT_RX_STATUS BIT(2)
+#define TCPC_REG_ALERT_POWER_STATUS BIT(1)
+#define TCPC_REG_ALERT_CC_STATUS BIT(0)
+#define TCPC_REG_ALERT_TX_COMPLETE                                 \
+	(TCPC_REG_ALERT_TX_SUCCESS | TCPC_REG_ALERT_TX_DISCARDED | \
+	 TCPC_REG_ALERT_TX_FAILED)
+
+#define TCPC_REG_ALERT_MASK 0x12
+#define TCPC_REG_ALERT_MASK_VENDOR_DEF BIT(15)
+
+#define TCPC_REG_POWER_STATUS_MASK 0x14
+#define TCPC_REG_FAULT_STATUS_MASK 0x15
+#define TCPC_REG_EXT_STATUS_MASK 0x16
+#define TCPC_REG_ALERT_EXTENDED_MASK 0x17
+
+#define TCPC_REG_CONFIG_STD_OUTPUT 0x18
+#define TCPC_REG_CONFIG_STD_OUTPUT_DBG_ACC_CONN_N BIT(6)
+#define TCPC_REG_CONFIG_STD_OUTPUT_AUDIO_CONN_N BIT(5)
+#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_MASK (3 << 2)
+#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_NONE (0 << 2)
+#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_USB BIT(2)
+#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_DP (2 << 2)
+#define TCPC_REG_CONFIG_STD_OUTPUT_CONNECTOR_FLIPPED BIT(0)
+
+#define TCPC_REG_TCPC_CTRL 0x19
+#define TCPC_REG_TCPC_CTRL_SET(polarity) (polarity)
+#define TCPC_REG_TCPC_CTRL_POLARITY(reg) ((reg)&0x1)
+/*
+ * In TCPCI Rev 2.0, this bit must be set this to generate CC status alerts when
+ * a connection is found.
+ */
+#define TCPC_REG_TCPC_CTRL_EN_LOOK4CONNECTION_ALERT BIT(6)
+#define TCPC_REG_TCPC_CTRL_DEBUG_ACC_CONTROL BIT(4)
+#define TCPC_REG_TCPC_CTRL_BIST_TEST_MODE BIT(1)
+
+#define TCPC_REG_ROLE_CTRL 0x1a
+#define TCPC_REG_ROLE_CTRL_DRP_MASK BIT(6)
+#define TCPC_REG_ROLE_CTRL_RP_MASK (BIT(5) | BIT(4))
+#define TCPC_REG_ROLE_CTRL_CC2_MASK (BIT(3) | BIT(2))
+#define TCPC_REG_ROLE_CTRL_CC1_MASK (BIT(1) | BIT(0))
+#define TCPC_REG_ROLE_CTRL_SET(drp, rp, cc1, cc2)       \
+	((((drp) << 6) & TCPC_REG_ROLE_CTRL_DRP_MASK) | \
+	 (((rp) << 4) & TCPC_REG_ROLE_CTRL_RP_MASK) |   \
+	 (((cc2) << 2) & TCPC_REG_ROLE_CTRL_CC2_MASK) | \
+	 ((cc1)&TCPC_REG_ROLE_CTRL_CC1_MASK))
+#define TCPC_REG_ROLE_CTRL_DRP(reg) (((reg)&TCPC_REG_ROLE_CTRL_DRP_MASK) >> 6)
+#define TCPC_REG_ROLE_CTRL_RP(reg) (((reg)&TCPC_REG_ROLE_CTRL_RP_MASK) >> 4)
+#define TCPC_REG_ROLE_CTRL_CC2(reg) (((reg)&TCPC_REG_ROLE_CTRL_CC2_MASK) >> 2)
+#define TCPC_REG_ROLE_CTRL_CC1(reg) ((reg)&TCPC_REG_ROLE_CTRL_CC1_MASK)
+
+#define TCPC_REG_FAULT_CTRL 0x1b
+#define TCPC_REG_FAULT_CTRL_VBUS_OVP_FAULT_DIS BIT(1)
+#define TCPC_REG_FAULT_CTRL_VCONN_OCP_FAULT_DIS BIT(0)
+
+#define TCPC_REG_POWER_CTRL 0x1c
+#define TCPC_REG_POWER_CTRL_FRS_ENABLE BIT(7)
+#define TCPC_REG_POWER_CTRL_VBUS_VOL_MONITOR_DIS BIT(6)
+#define TCPC_REG_POWER_CTRL_VOLT_ALARM_DIS BIT(5)
+#define TCPC_REG_POWER_CTRL_AUTO_DISCHARGE_DISCONNECT BIT(4)
+#define TCPC_REG_POWER_CTRL_FORCE_DISCHARGE BIT(2)
+#define TCPC_REG_POWER_CTRL_SET(vconn) (vconn)
+#define TCPC_REG_POWER_CTRL_VCONN(reg) ((reg)&0x1)
+
+#define TCPC_REG_CC_STATUS 0x1d
+#define TCPC_REG_CC_STATUS_LOOK4CONNECTION_MASK BIT(5)
+#define TCPC_REG_CC_STATUS_CONNECT_RESULT_MASK BIT(4)
+#define TCPC_REG_CC_STATUS_CC2_STATE_MASK (BIT(3) | BIT(2))
+#define TCPC_REG_CC_STATUS_CC1_STATE_MASK (BIT(1) | BIT(0))
+#define TCPC_REG_CC_STATUS_SET(term, cc1, cc2) \
+	((term) << 4 | ((cc2)&0x3) << 2 | ((cc1)&0x3))
+#define TCPC_REG_CC_STATUS_LOOK4CONNECTION(reg) \
+	((reg & TCPC_REG_CC_STATUS_LOOK4CONNECTION_MASK) >> 5)
+#define TCPC_REG_CC_STATUS_TERM(reg) \
+	(((reg)&TCPC_REG_CC_STATUS_CONNECT_RESULT_MASK) >> 4)
+#define TCPC_REG_CC_STATUS_CC2(reg) \
+	(((reg)&TCPC_REG_CC_STATUS_CC2_STATE_MASK) >> 2)
+#define TCPC_REG_CC_STATUS_CC1(reg) ((reg)&TCPC_REG_CC_STATUS_CC1_STATE_MASK)
+
+#define TCPC_REG_POWER_STATUS 0x1e
+#define TCPC_REG_POWER_STATUS_MASK_ALL 0xff
+#define TCPC_REG_POWER_STATUS_DEBUG_ACC_CON BIT(7)
+#define TCPC_REG_POWER_STATUS_UNINIT BIT(6)
+#define TCPC_REG_POWER_STATUS_SOURCING_VBUS BIT(4)
+#define TCPC_REG_POWER_STATUS_VBUS_DET BIT(3)
+#define TCPC_REG_POWER_STATUS_VBUS_PRES BIT(2)
+#define TCPC_REG_POWER_STATUS_SINKING_VBUS BIT(0)
+
+#define TCPC_REG_FAULT_STATUS 0x1f
+#define TCPC_REG_FAULT_STATUS_ALL_REGS_RESET BIT(7)
+#define TCPC_REG_FAULT_STATUS_FORCE_OFF_VBUS BIT(6)
+#define TCPC_REG_FAULT_STATUS_AUTO_DISCHARGE_FAIL BIT(5)
+#define TCPC_REG_FAULT_STATUS_FORCE_DISCHARGE_FAIL BIT(4)
+#define TCPC_REG_FAULT_STATUS_VBUS_OVER_CURRENT BIT(3)
+#define TCPC_REG_FAULT_STATUS_VBUS_OVER_VOLTAGE BIT(2)
+#define TCPC_REG_FAULT_STATUS_VCONN_OVER_CURRENT BIT(1)
+#define TCPC_REG_FAULT_STATUS_I2C_INTERFACE_ERR BIT(0)
+
+#define TCPC_REG_EXT_STATUS 0x20
+#define TCPC_REG_EXT_STATUS_SAFE0V BIT(0)
+
+#define TCPC_REG_ALERT_EXT 0x21
+#define TCPC_REG_ALERT_EXT_TIMER_EXPIRED BIT(2)
+#define TCPC_REG_ALERT_EXT_SRC_FRS BIT(1)
+#define TCPC_REG_ALERT_EXT_SNK_FRS BIT(0)
+
+#define TCPC_REG_COMMAND 0x23
+#define TCPC_REG_COMMAND_WAKE_I2C 0x11
+#define TCPC_REG_COMMAND_DISABLE_VBUS_DETECT 0x22
+#define TCPC_REG_COMMAND_ENABLE_VBUS_DETECT 0x33
+#define TCPC_REG_COMMAND_SNK_CTRL_LOW 0x44
+#define TCPC_REG_COMMAND_SNK_CTRL_HIGH 0x55
+#define TCPC_REG_COMMAND_SRC_CTRL_LOW 0x66
+#define TCPC_REG_COMMAND_SRC_CTRL_HIGH 0x77
+#define TCPC_REG_COMMAND_LOOK4CONNECTION 0x99
+#define TCPC_REG_COMMAND_RESET_TRANSMIT_BUF 0xDD
+#define TCPC_REG_COMMAND_RESET_RECEIVE_BUF 0xEE
+#define TCPC_REG_COMMAND_I2CIDLE 0xFF
+
+#define TCPC_REG_DEV_CAP_1 0x24
+#define TCPC_REG_DEV_CAP_1_VBUS_NONDEFAULT_TARGET BIT(15)
+#define TCPC_REG_DEV_CAP_1_VBUS_OCP_REPORTING BIT(14)
+#define TCPC_REG_DEV_CAP_1_VBUS_OVP_REPORTING BIT(13)
+#define TCPC_REG_DEV_CAP_1_BLEED_DISCHARGE BIT(12)
+#define TCPC_REG_DEV_CAP_1_FORCE_DISCHARGE BIT(11)
+#define TCPC_REG_DEV_CAP_1_VBUS_MEASURE_ALARM_CAPABLE BIT(10)
+#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_MASK (BIT(8) | BIT(9))
+#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_DEF (0 << 8)
+#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_1P5_DEF (1 << 8)
+#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_3P0_1P5_DEF (2 << 8)
+#define TCPC_REG_DEV_CAP_1_PWRROLE_MASK (BIT(5) | BIT(6) | BIT(7))
+#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC_OR_SNK (0 << 5)
+#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC (1 << 5)
+#define TCPC_REG_DEV_CAP_1_PWRROLE_SNK (2 << 5)
+#define TCPC_REG_DEV_CAP_1_PWRROLE_SNK_ACC (3 << 5)
+#define TCPC_REG_DEV_CAP_1_PWRROLE_DRP (4 << 5)
+#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP_ADPT_CBL (5 << 5)
+#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP (6 << 5)
+#define TCPC_REG_DEV_CAP_1_ALL_SOP_STAR_MSGS_SUPPORTED BIT(4)
+#define TCPC_REG_DEV_CAP_1_SOURCE_VCONN BIT(3)
+#define TCPC_REG_DEV_CAP_1_SINK_VBUS BIT(2)
+#define TCPC_REG_DEV_CAP_1_SOURCE_NONDEFAULT_VBUS BIT(1)
+#define TCPC_REG_DEV_CAP_1_SOURCE_VBUS BIT(0)
+
+#define TCPC_REG_DEV_CAP_2 0x26
+#define TCPC_REG_DEV_CAP_2_LONG_MSG BIT(12)
+#define TCPC_REG_DEV_CAP_2_SNK_FR_SWAP BIT(9)
+
+#define TCPC_REG_STD_INPUT_CAP 0x28
+#define TCPC_REG_STD_INPUT_CAP_SRC_FR_SWAP (BIT(4) | BIT(3))
+#define TCPC_REG_STD_INPUT_CAP_EXT_OVR_V_F BIT(2)
+#define TCPC_REG_STD_INPUT_CAP_EXT_OVR_C_F BIT(1)
+#define TCPC_REG_STD_INPUT_CAP_FORCE_OFF_VBUS BIT(0)
+
+#define TCPC_REG_STD_OUTPUT_CAP 0x29
+#define TCPC_REG_STD_OUTPUT_CAP_SNK_DISC_DET BIT(7)
+#define TCPC_REG_STD_OUTPUT_CAP_DBG_ACCESSORY BIT(6)
+#define TCPC_REG_STD_OUTPUT_CAP_VBUS_PRESENT_MON BIT(5)
+#define TCPC_REG_STD_OUTPUT_CAP_AUDIO_ACCESSORY BIT(4)
+#define TCPC_REG_STD_OUTPUT_CAP_ACTIVE_CABLE BIT(3)
+#define TCPC_REG_STD_OUTPUT_CAP_MUX_CONF_CTRL BIT(2)
+#define TCPC_REG_STD_OUTPUT_CAP_CONN_PRESENT BIT(1)
+#define TCPC_REG_STD_OUTPUT_CAP_CONN_ORIENTATION BIT(0)
+
+#define TCPC_REG_CONFIG_EXT_1 0x2A
+#define TCPC_REG_CONFIG_EXT_1_FR_SWAP_SNK_DIR BIT(1)
+
+#define TCPC_REG_GENERIC_TIMER 0x2c
+
+#define TCPC_REG_MSG_HDR_INFO 0x2e
+#define TCPC_REG_MSG_HDR_INFO_SET(drole, prole) \
+	((drole) << 3 | (PD_REV20 << 1) | (prole))
+#define TCPC_REG_MSG_HDR_INFO_DROLE(reg) (((reg)&0x8) >> 3)
+#define TCPC_REG_MSG_HDR_INFO_PROLE(reg) ((reg)&0x1)
+
+#define TCPC_REG_RX_DETECT 0x2f
+#define TCPC_REG_RX_DETECT_MSG_DISABLE_DISCONNECT BIT(7)
+#define TCPC_REG_RX_DETECT_CABLE_RST BIT(6)
+#define TCPC_REG_RX_DETECT_HRST BIT(5)
+#define TCPC_REG_RX_DETECT_SOPPP_DBG BIT(4)
+#define TCPC_REG_RX_DETECT_SOPP_DBG BIT(3)
+#define TCPC_REG_RX_DETECT_SOPPP BIT(2)
+#define TCPC_REG_RX_DETECT_SOPP BIT(1)
+#define TCPC_REG_RX_DETECT_SOP BIT(0)
+#define TCPC_REG_RX_DETECT_SOP_HRST_MASK \
+	(TCPC_REG_RX_DETECT_SOP | TCPC_REG_RX_DETECT_HRST)
+#define TCPC_REG_RX_DETECT_SOP_SOPP_SOPPP_HRST_MASK         \
+	(TCPC_REG_RX_DETECT_SOP | TCPC_REG_RX_DETECT_SOPP | \
+	 TCPC_REG_RX_DETECT_SOPPP | TCPC_REG_RX_DETECT_HRST)
+#define TCPC_REG_RX_DETECT_NONE 0xff
+
+/* TCPCI Rev 1.0 receive registers */
+#define TCPC_REG_RX_BYTE_CNT 0x30
+#define TCPC_REG_RX_BUF_FRAME_TYPE 0x31
+#define TCPC_REG_RX_HDR 0x32
+#define TCPC_REG_RX_DATA 0x34 /* through 0x4f */
+
+/*
+ * In TCPCI Rev 2.0, the RECEIVE_BUFFER is comprised of three sets of registers:
+ * READABLE_BYTE_COUNT, RX_BUF_FRAME_TYPE and RX_BUF_BYTE_x. These registers can
+ * only be accessed by reading at a common register address 30h.
+ */
+#define TCPC_REG_RX_BUFFER 0x30
+
+#define TCPC_REG_TRANSMIT 0x50
+#define TCPC_REG_TRANSMIT_SET_WITH_RETRY(retries, type) \
+	((retries) << 4 | (type))
+#define TCPC_REG_TRANSMIT_SET_WITHOUT_RETRY(type) (type)
+#define TCPC_REG_TRANSMIT_RETRY(reg) (((reg)&0x30) >> 4)
+#define TCPC_REG_TRANSMIT_TYPE(reg) ((reg)&0x7)
+
+/* TCPCI Rev 1.0 transmit registers */
+#define TCPC_REG_TX_BYTE_CNT 0x51
+#define TCPC_REG_TX_HDR 0x52
+#define TCPC_REG_TX_DATA 0x54 /* through 0x6f */
+
+/*
+ * In TCPCI Rev 2.0, the TRANSMIT_BUFFER holds the I2C_WRITE_BYTE_COUNT and the
+ * portion of the SOP* USB PD message payload (including the header and/or the
+ * data bytes) most recently written by the TCPM in TX_BUF_BYTE_x. TX_BUF_BYTE_x
+ * is “hidden” and can only be accessed by writing to register address 51h
+ */
+#define TCPC_REG_TX_BUFFER 0x51
+
+#define TCPC_REG_VBUS_VOLTAGE 0x70
+#define TCPC_REG_VBUS_VOLTAGE_MEASUREMENT GENMASK(9, 0)
+#define TCPC_REG_VBUS_VOLTAGE_SCALE_FACTOR GENMASK(11, 10)
+#define TCPC_REG_VBUS_VOLTAGE_LSB 25
+
+/*
+ * 00: the measurement is not scaled
+ * 01: the measurement is divided by 2
+ * 10: the measurement is divided by 4
+ * 11: reserved
+ */
+#define TCPC_REG_VBUS_VOLTAGE_SCALE(x) \
+	(1 << (((x)&TCPC_REG_VBUS_VOLTAGE_SCALE_FACTOR) >> 10))
+#define TCPC_REG_VBUS_VOLTAGE_MEASURE(x) ((x)&TCPC_REG_VBUS_VOLTAGE_MEASUREMENT)
+#define TCPC_REG_VBUS_VOLTAGE_VBUS(x)                                        \
+	(TCPC_REG_VBUS_VOLTAGE_SCALE(x) * TCPC_REG_VBUS_VOLTAGE_MEASURE(x) * \
+	 TCPC_REG_VBUS_VOLTAGE_LSB)
+
+#define TCPC_REG_VBUS_SINK_DISCONNECT_THRESH 0x72
+#define TCPC_REG_VBUS_SINK_DISCONNECT_THRESH_DEFAULT 0x008C /* 3.5 V */
+
+#define TCPC_REG_VBUS_STOP_DISCHARGE_THRESH 0x74
+#define TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG 0x76
+#define TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG 0x78
+
+#define TCPC_REG_VBUS_NONDEFAULT_TARGET 0x7a
+
+extern const struct tcpm_drv tcpci_tcpm_drv;
+extern const struct usb_mux_driver tcpci_tcpm_usb_mux_driver;
+
+void tcpci_set_cached_rp(int port, int rp);
+int tcpci_get_cached_rp(int port);
+void tcpci_set_cached_pull(int port, enum tcpc_cc_pull pull);
+enum tcpc_cc_pull tcpci_get_cached_pull(int port);
+
+void tcpci_tcpc_alert(int port);
+int tcpci_tcpm_init(int port);
+int tcpci_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
+		      enum tcpc_cc_voltage_status *cc2);
+bool tcpci_tcpm_check_vbus_level(int port, enum vbus_level level);
+int tcpci_tcpm_select_rp_value(int port, int rp);
+int tcpci_tcpm_set_cc(int port, int pull);
+int tcpci_tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity);
+int tcpci_tcpm_sop_prime_enable(int port, bool enable);
+int tcpci_tcpm_set_vconn(int port, int enable);
+int tcpci_tcpm_set_msg_header(int port, int power_role, int data_role);
+int tcpci_tcpm_set_rx_enable(int port, int enable);
+int tcpci_tcpm_get_message_raw(int port, uint32_t *payload, int *head);
+int tcpci_tcpm_transmit(int port, enum tcpci_msg_type type, uint16_t header,
+			const uint32_t *data);
+int tcpci_tcpm_release(int port);
+#ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+int tcpci_set_role_ctrl(int port, enum tcpc_drp drp, enum tcpc_rp_value rp,
+			enum tcpc_cc_pull pull);
+int tcpci_tcpc_drp_toggle(int port);
+#endif
+#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
+int tcpci_enter_low_power_mode(int port);
+void tcpci_wake_low_power_mode(int port);
+#endif
+int tcpci_hard_reset_reinit(int port);
+
+enum ec_error_list tcpci_set_bist_test_mode(const int port, const bool enable);
+enum ec_error_list tcpci_get_bist_test_mode(const int port, bool *enable);
+void tcpci_tcpc_discharge_vbus(int port, int enable);
+void tcpci_tcpc_enable_auto_discharge_disconnect(int port, int enable);
+int tcpci_tcpc_debug_accessory(int port, bool enable);
+
+int tcpci_tcpm_mux_init(const struct usb_mux *me);
+int tcpci_tcpm_mux_set(const struct usb_mux *me, mux_state_t mux_state,
+		       bool *ack_required);
+int tcpci_tcpm_mux_get(const struct usb_mux *me, mux_state_t *mux_state);
+int tcpci_tcpm_mux_enter_low_power(const struct usb_mux *me);
+
+/**
+ * Get the TCPC chip information (chip IDs, etc) for the given port.
+ *
+ * The returned value is cached internally, so subsequent calls to this function
+ * will not access the TCPC. If live is true, data will be fetched from the TCPC
+ * regardless of whether any cached data is available.
+ *
+ * If chip_info is NULL, this will ensure the cache is up to date but avoid
+ * writing the output chip_info.
+ *
+ * If the TCPC is accessed (live data is retrieved), this will wake the chip up
+ * from low power mode on I2C access. It is expected that the USB-PD state
+ * machine will return it to low power mode as appropriate afterward.
+ *
+ * Returns EC_SUCCESS or an error; chip_info is not updated on error.
+ */
+int tcpci_get_chip_info(int port, int live,
+			struct ec_response_pd_chip_info_v1 *chip_info);
+
+/**
+ * Equivalent to tcpci_get_chip_info, but allows the caller to modify the cache
+ * if new data is fetched.
+ *
+ * If mutator is non-NULL and data is read from the TCPC (either because live
+ * data is requested or nothing was cached), then it is called with a pointer
+ * to the cached information for the port. It can then make changes to the
+ * cached data (for example correcting IDs that are known to be reported
+ * incorrectly by some chips, possibly requiring more communication with the
+ * TCPC). Any error returned by mutator causes this function to return with the
+ * same error.
+ *
+ * If mutator writes through the cached data pointer, those changes will be
+ * retained until live data is requested again.
+ */
+int tcpci_get_chip_info_mutable(
+	int port, int live, struct ec_response_pd_chip_info_v1 *chip_info,
+	int (*mutator)(int port, bool live,
+		       struct ec_response_pd_chip_info_v1 *cached));
+
+/**
+ * This function is identical to the tcpci_get_vbus_voltage without
+ * checking the DEV_CAP_1.
+ *
+ * @param port: The USB-C port to query
+ * @param vbus: VBUS voltage in mV the TCPC sensed
+ *
+ * @return EC_SUCCESS on success, and otherwise on failure.
+ */
+int tcpci_get_vbus_voltage_no_check(int port, int *vbus);
+int tcpci_get_vbus_voltage(int port, int *vbus);
+bool tcpci_tcpm_get_snk_ctrl(int port);
+int tcpci_tcpm_set_snk_ctrl(int port, int enable);
+bool tcpci_tcpm_get_src_ctrl(int port);
+int tcpci_tcpm_set_src_ctrl(int port, int enable);
+
+int tcpci_tcpc_fast_role_swap_enable(int port, int enable);
+
+#endif /* __CROS_EC_USB_PD_TCPM_TCPCI_H */
diff --git a/include/driver/tcpm/tcpm.h b/include/driver/tcpm/tcpm.h
new file mode 100644
index 0000000000..e750c23124
--- /dev/null
+++ b/include/driver/tcpm/tcpm.h
@@ -0,0 +1,665 @@
+/* Copyright 2015 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* USB Power delivery port management - common header for TCPM drivers */
+
+#ifndef __CROS_EC_USB_PD_TCPM_TCPM_H
+#define __CROS_EC_USB_PD_TCPM_TCPM_H
+
+#include "common.h"
+#include "ec_commands.h"
+#include "i2c.h"
+#include "usb_pd_tcpm.h"
+#include "util.h"
+
+#if defined(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE) && \
+	!defined(CONFIG_USB_PD_DUAL_ROLE)
+#error "DRP auto toggle requires board to have DRP support"
+#error "Please upgrade your board configuration"
+#endif
+
+#ifndef CONFIG_USB_PD_TCPC
+
+/* I2C wrapper functions - get I2C port / peripheral addr from config struct. */
+#ifndef CONFIG_USB_PD_TCPC_LOW_POWER
+static inline int tcpc_addr_write(int port, int i2c_addr, int reg, int val)
+{
+	return i2c_write8(tcpc_config[port].i2c_info.port, i2c_addr, reg, val);
+}
+
+static inline int tcpc_addr_write16(int port, int i2c_addr, int reg, int val)
+{
+	return i2c_write16(tcpc_config[port].i2c_info.port, i2c_addr, reg, val);
+}
+
+static inline int tcpc_addr_read(int port, int i2c_addr, int reg, int *val)
+{
+	return i2c_read8(tcpc_config[port].i2c_info.port, i2c_addr, reg, val);
+}
+
+static inline int tcpc_addr_read16(int port, int i2c_addr, int reg, int *val)
+{
+	return i2c_read16(tcpc_config[port].i2c_info.port, i2c_addr, reg, val);
+}
+
+/*
+ * The *_no_lpm_exit() routines are intende to be used where the TCPC
+ * needs to be accessed without being being taken out of LPM. The main
+ * use case is to check the alert register to determine if a TCPC is the
+ * source of an interrupt in a shared interrupt implementation. If the
+ * TCPC is taken out of LPM, it may generate a new alert which can lead
+ * to successive unintended interrupts. The TCPC is placed back into the
+ * idle state after the LPM timer expires similar to other tcpc_*()
+ * routines.
+ *
+ * The caller must guarantee that the chip responds to I2C as expected:
+ *  - some TCPCs wake up when they alert and do not need special handing
+ *  - some TCPCs wake up on I2C and respond as expected
+ *  - some TCPCs wake up on I2C and throw away the transaction - these
+ *    need an explicit by the caller.
+ */
+
+static inline int tcpc_addr_read16_no_lpm_exit(int port, int i2c_addr, int reg,
+					       int *val)
+{
+	return tcpc_addr_read16(port, i2c_addr, reg, val);
+}
+
+static inline int tcpc_xfer(int port, const uint8_t *out, int out_size,
+			    uint8_t *in, int in_size)
+{
+	return i2c_xfer(tcpc_config[port].i2c_info.port,
+			tcpc_config[port].i2c_info.addr_flags, out, out_size,
+			in, in_size);
+}
+
+static inline int tcpc_xfer_unlocked(int port, const uint8_t *out, int out_size,
+				     uint8_t *in, int in_size, int flags)
+{
+	return i2c_xfer_unlocked(tcpc_config[port].i2c_info.port,
+				 tcpc_config[port].i2c_info.addr_flags, out,
+				 out_size, in, in_size, flags);
+}
+
+static inline int tcpc_read_block(int port, int reg, uint8_t *in, int size)
+{
+	return i2c_read_block(tcpc_config[port].i2c_info.port,
+			      tcpc_config[port].i2c_info.addr_flags, reg, in,
+			      size);
+}
+
+static inline int tcpc_write_block(int port, int reg, const uint8_t *out,
+				   int size)
+{
+	return i2c_write_block(tcpc_config[port].i2c_info.port,
+			       tcpc_config[port].i2c_info.addr_flags, reg, out,
+			       size);
+}
+
+static inline int tcpc_update8(int port, int reg, uint8_t mask,
+			       enum mask_update_action action)
+{
+	return i2c_update8(tcpc_config[port].i2c_info.port,
+			   tcpc_config[port].i2c_info.addr_flags, reg, mask,
+			   action);
+}
+
+static inline int tcpc_update16(int port, int reg, uint16_t mask,
+				enum mask_update_action action)
+{
+	return i2c_update16(tcpc_config[port].i2c_info.port,
+			    tcpc_config[port].i2c_info.addr_flags, reg, mask,
+			    action);
+}
+
+#else /* !CONFIG_USB_PD_TCPC_LOW_POWER */
+int tcpc_addr_write(int port, int i2c_addr, int reg, int val);
+int tcpc_addr_write16(int port, int i2c_addr, int reg, int val);
+int tcpc_addr_read(int port, int i2c_addr, int reg, int *val);
+int tcpc_addr_read16(int port, int i2c_addr, int reg, int *val);
+int tcpc_addr_read16_no_lpm_exit(int port, int i2c_addr, int reg, int *val);
+int tcpc_read_block(int port, int reg, uint8_t *in, int size);
+int tcpc_write_block(int port, int reg, const uint8_t *out, int size);
+int tcpc_xfer(int port, const uint8_t *out, int out_size, uint8_t *in,
+	      int in_size);
+int tcpc_xfer_unlocked(int port, const uint8_t *out, int out_size, uint8_t *in,
+		       int in_size, int flags);
+
+int tcpc_update8(int port, int reg, uint8_t mask,
+		 enum mask_update_action action);
+int tcpc_update16(int port, int reg, uint16_t mask,
+		  enum mask_update_action action);
+
+#endif /* CONFIG_USB_PD_TCPC_LOW_POWER */
+
+static inline int tcpc_write(int port, int reg, int val)
+{
+	return tcpc_addr_write(port, tcpc_config[port].i2c_info.addr_flags, reg,
+			       val);
+}
+
+static inline int tcpc_write16(int port, int reg, int val)
+{
+	return tcpc_addr_write16(port, tcpc_config[port].i2c_info.addr_flags,
+				 reg, val);
+}
+
+static inline int tcpc_read(int port, int reg, int *val)
+{
+	return tcpc_addr_read(port, tcpc_config[port].i2c_info.addr_flags, reg,
+			      val);
+}
+
+static inline int tcpc_read16(int port, int reg, int *val)
+{
+	return tcpc_addr_read16(port, tcpc_config[port].i2c_info.addr_flags,
+				reg, val);
+}
+
+static inline void tcpc_lock(int port, int lock)
+{
+	i2c_lock(tcpc_config[port].i2c_info.port, lock);
+}
+
+/* TCPM driver wrapper function */
+static inline int tcpm_init(int port)
+{
+	int rv;
+
+	rv = tcpc_config[port].drv->init(port);
+	if (rv)
+		return rv;
+
+	/* Board specific post TCPC init */
+	if (board_tcpc_post_init)
+		rv = board_tcpc_post_init(port);
+
+	return rv;
+}
+
+static inline int tcpm_release(int port)
+{
+	return tcpc_config[port].drv->release(port);
+}
+
+static inline int tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
+			      enum tcpc_cc_voltage_status *cc2)
+{
+	return tcpc_config[port].drv->get_cc(port, cc1, cc2);
+}
+
+static inline bool tcpm_check_vbus_level(int port, enum vbus_level level)
+{
+	return tcpc_config[port].drv->check_vbus_level(port, level);
+}
+
+static inline int tcpm_select_rp_value(int port, int rp)
+{
+	return tcpc_config[port].drv->select_rp_value(port, rp);
+}
+
+static inline int tcpm_set_cc(int port, int pull)
+{
+	return tcpc_config[port].drv->set_cc(port, pull);
+}
+
+static inline int tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity)
+{
+	return tcpc_config[port].drv->set_polarity(port, polarity);
+}
+
+static inline int tcpm_sop_prime_enable(int port, bool enable)
+{
+#ifdef CONFIG_USB_PD_DECODE_SOP
+	return tcpc_config[port].drv->sop_prime_enable(port, enable);
+#else
+	return EC_SUCCESS;
+#endif
+}
+
+static inline int tcpm_set_vconn(int port, int enable)
+{
+	if (IS_ENABLED(CONFIG_USB_PD_TCPC_VCONN) ||
+	    tcpc_config[port].flags & TCPC_FLAGS_CONTROL_VCONN) {
+		int rv;
+
+		rv = tcpc_config[port].drv->set_vconn(port, enable);
+		if (rv)
+			return rv;
+	}
+
+	return tcpm_sop_prime_enable(port, enable);
+}
+
+static inline int tcpm_set_msg_header(int port, int power_role, int data_role)
+{
+	return tcpc_config[port].drv->set_msg_header(port, power_role,
+						     data_role);
+}
+
+static inline int tcpm_set_rx_enable(int port, int enable)
+{
+	return tcpc_config[port].drv->set_rx_enable(port, enable);
+}
+
+static inline void tcpm_enable_auto_discharge_disconnect(int port, int enable)
+{
+	const struct tcpm_drv *tcpc = tcpc_config[port].drv;
+
+	if (tcpc->tcpc_enable_auto_discharge_disconnect)
+		tcpc->tcpc_enable_auto_discharge_disconnect(port, enable);
+}
+
+static inline int tcpm_reset_bist_type_2(int port)
+{
+	if (tcpc_config[port].drv->reset_bist_type_2 != NULL)
+		return tcpc_config[port].drv->reset_bist_type_2(port);
+	else
+		return EC_SUCCESS;
+}
+
+/**
+ * Reads a message using get_message_raw driver method and puts it into EC's
+ * cache.
+ */
+int tcpm_enqueue_message(int port);
+
+static inline int tcpm_transmit(int port, enum tcpci_msg_type type,
+				uint16_t header, const uint32_t *data)
+{
+	return tcpc_config[port].drv->transmit(port, type, header, data);
+}
+
+static inline bool tcpm_get_snk_ctrl(int port)
+{
+	return tcpc_config[port].drv->get_snk_ctrl ?
+		       tcpc_config[port].drv->get_snk_ctrl(port) :
+		       false;
+}
+static inline int tcpm_set_snk_ctrl(int port, int enable)
+{
+	if (tcpc_config[port].drv->set_snk_ctrl != NULL)
+		return tcpc_config[port].drv->set_snk_ctrl(port, enable);
+	else
+		return EC_ERROR_UNIMPLEMENTED;
+}
+
+test_mockable_static_inline bool tcpm_get_src_ctrl(int port)
+{
+	return tcpc_config[port].drv->get_src_ctrl ?
+		       tcpc_config[port].drv->get_src_ctrl(port) :
+		       false;
+}
+
+static inline int tcpm_set_src_ctrl(int port, int enable)
+{
+	if (tcpc_config[port].drv->set_src_ctrl != NULL)
+		return tcpc_config[port].drv->set_src_ctrl(port, enable);
+	else
+		return EC_ERROR_UNIMPLEMENTED;
+}
+
+static inline int tcpc_get_vbus_voltage(int port)
+{
+	int vbus;
+
+	if (tcpc_config[port].drv->get_vbus_voltage != NULL)
+		tcpc_config[port].drv->get_vbus_voltage(port, &vbus);
+	else
+		return 0;
+	return vbus;
+}
+
+static inline void tcpc_alert(int port)
+{
+	tcpc_config[port].drv->tcpc_alert(port);
+}
+
+static inline void tcpc_discharge_vbus(int port, int enable)
+{
+	tcpc_config[port].drv->tcpc_discharge_vbus(port, enable);
+}
+
+#ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+static inline int tcpm_auto_toggle_supported(int port)
+{
+	return !!tcpc_config[port].drv->drp_toggle;
+}
+
+static inline int tcpm_enable_drp_toggle(int port)
+{
+	return tcpc_config[port].drv->drp_toggle(port);
+}
+#else
+static inline int tcpm_auto_toggle_supported(int port)
+{
+	return false;
+}
+int tcpm_enable_drp_toggle(int port);
+#endif
+
+static inline int tcpm_debug_accessory(int port, bool enable)
+{
+	if (tcpc_config[port].drv->debug_accessory)
+		return tcpc_config[port].drv->debug_accessory(port, enable);
+	return EC_SUCCESS;
+}
+
+static inline int tcpm_debug_detach(int port)
+{
+	if (tcpc_config[port].drv->debug_detach)
+		return tcpc_config[port].drv->debug_detach(port);
+
+	/* No special handling for debug disconnections?  Success! */
+	return EC_SUCCESS;
+}
+
+#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
+static inline int tcpm_enter_low_power_mode(int port)
+{
+	return tcpc_config[port].drv->enter_low_power_mode(port);
+}
+
+static inline void tcpm_wake_low_power_mode(int port)
+{
+	if (tcpc_config[port].drv->wake_low_power_mode)
+		tcpc_config[port].drv->wake_low_power_mode(port);
+}
+#else
+int tcpm_enter_low_power_mode(int port);
+void tcpm_wake_low_power_mode(int port);
+#endif
+
+#ifdef CONFIG_CMD_I2C_STRESS_TEST_TCPC
+static inline int tcpc_i2c_read(const int port, const uint16_t addr_flags,
+				const int reg, int *data)
+{
+	return tcpc_read(port, reg, data);
+}
+
+static inline int tcpc_i2c_write(const int port, const uint16_t addr_flags,
+				 const int reg, int data)
+{
+	return tcpc_write(port, reg, data);
+}
+#endif
+
+static inline int tcpm_get_chip_info(int port, int live,
+				     struct ec_response_pd_chip_info_v1 *info)
+{
+	if (tcpc_config[port].drv->get_chip_info)
+		return tcpc_config[port].drv->get_chip_info(port, live, info);
+	return EC_ERROR_UNIMPLEMENTED;
+}
+
+static inline int tcpm_hard_reset_reinit(int port)
+{
+	if (tcpc_config[port].drv->hard_reset_reinit)
+		return tcpc_config[port].drv->hard_reset_reinit(port);
+	return EC_ERROR_UNIMPLEMENTED;
+}
+
+static inline enum ec_error_list tcpc_set_bist_test_mode(int port, bool enable)
+{
+	const struct tcpm_drv *tcpc;
+	int rv = EC_SUCCESS;
+
+	tcpc = tcpc_config[port].drv;
+	if (tcpc->set_bist_test_mode)
+		rv = tcpc->set_bist_test_mode(port, enable);
+	return rv;
+}
+
+static inline enum ec_error_list tcpc_get_bist_test_mode(int port, bool *enable)
+{
+	const struct tcpm_drv *tcpc;
+
+	tcpc = tcpc_config[port].drv;
+	if (tcpc->get_bist_test_mode)
+		return tcpc->get_bist_test_mode(port, enable);
+
+	*enable = false;
+
+	return EC_ERROR_UNIMPLEMENTED;
+}
+
+/*
+ * Returns true if the port controls FRS using the TCPC.
+ */
+static inline int tcpm_tcpc_has_frs_control(int port)
+{
+	if (!IS_ENABLED(CONFIG_USB_PD_FRS))
+		return 0;
+
+	if (IS_ENABLED(CONFIG_USB_PD_FRS_TCPC))
+		return 1;
+
+	if (tcpc_config[port].flags & TCPC_FLAGS_CONTROL_FRS)
+		return 1;
+
+	return 0;
+}
+
+#ifdef CONFIG_USB_PD_FRS
+static inline int tcpm_set_frs_enable(int port, int enable)
+{
+	const struct tcpm_drv *tcpc;
+	int rv = EC_SUCCESS;
+
+	/*
+	 * set_frs_enable will be set to tcpci_tcp_fast_role_swap_enable
+	 * if it is handled by the tcpci for the tcpc chipset
+	 */
+	tcpc = tcpc_config[port].drv;
+	if (tcpc->set_frs_enable)
+		rv = tcpc->set_frs_enable(port, enable);
+	return rv;
+}
+#endif /* defined(CONFIG_USB_PD_FRS) */
+
+#ifdef CONFIG_USB_PD_TCPM_SBU
+/**
+ * Turn on/off the SBU FETs
+ *
+ * @param port Type-C port number
+ * @param enable true:enable, false:disable
+ *
+ * @return EC_SUCCESS or error
+ */
+static inline int tcpc_set_sbu(int port, bool enable)
+{
+	return tcpc_config[port].drv->set_sbu ?
+		       tcpc_config[port].drv->set_sbu(port, enable) :
+		       EC_SUCCESS;
+}
+#endif /* CONFIG_USB_PD_TCPM_SBU */
+
+#else /* CONFIG_USB_PD_TCPC */
+
+/**
+ * Initialize TCPM driver and wait for TCPC readiness.
+ *
+ * @param port Type-C port number
+ *
+ * @return EC_SUCCESS or error
+ */
+int tcpm_init(int port);
+
+/**
+ * Read the CC line status.
+ *
+ * @param port Type-C port number
+ * @param cc1 pointer to CC status for CC1
+ * @param cc2 pointer to CC status for CC2
+ *
+ * @return EC_SUCCESS or error
+ */
+int tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
+		enum tcpc_cc_voltage_status *cc2);
+
+/**
+ * Check VBUS level
+ *
+ * @param port Type-C port number
+ * @param level safe level voltage to check against
+ *
+ * @return False => VBUS not at level, True => VBUS at level
+ */
+bool tcpm_check_vbus_level(int port, enum vbus_level level);
+
+/**
+ * Set the value of the CC pull-up used when we are a source.
+ *
+ * @param port Type-C port number
+ * @param rp One of enum tcpc_rp_value
+ *
+ * @return EC_SUCCESS or error
+ */
+int tcpm_select_rp_value(int port, int rp);
+
+/**
+ * Set the CC pull resistor. This sets our role as either source or sink.
+ *
+ * @param port Type-C port number
+ * @param pull One of enum tcpc_cc_pull
+ *
+ * @return EC_SUCCESS or error
+ */
+int tcpm_set_cc(int port, int pull);
+
+/**
+ * Set polarity
+ *
+ * @param port Type-C port number
+ * @param polarity port polarity
+ *
+ * @return EC_SUCCESS or error
+ */
+int tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity);
+
+/**
+ * Enable SOP' message transmit/receive.
+ *
+ * @param port Type-C port number
+ * @param enable Enable/Disable SOP' and SOP'' messages
+ *
+ * @return EC_SUCCESS or error
+ */
+int tcpm_sop_prime_enable(int port, int enable);
+
+/**
+ * Set Vconn.
+ *
+ * @param port Type-C port number
+ * @param enable Enable/Disable Vconn
+ *
+ * @return EC_SUCCESS or error
+ */
+int tcpm_set_vconn(int port, int enable);
+
+/**
+ * Set PD message header to use for goodCRC
+ *
+ * @param port Type-C port number
+ * @param power_role Power role to use in header
+ * @param data_role Data role to use in header
+ *
+ * @return EC_SUCCESS or error
+ */
+int tcpm_set_msg_header(int port, int power_role, int data_role);
+
+/**
+ * Set RX enable flag
+ *
+ * @param port Type-C port number
+ * @enable true for enable, false for disable
+ *
+ * @return EC_SUCCESS or error
+ */
+int tcpm_set_rx_enable(int port, int enable);
+
+/**
+ * Enable Auto Discharge Disconnect
+ *
+ * @param port Type-C port number
+ * @param enable true for enable, false for disable
+ */
+void tcpm_enable_auto_discharge_disconnect(int port, int enable);
+
+/**
+ * Transmit PD message
+ *
+ * @param port Type-C port number
+ * @param type Transmit type
+ * @param header Packet header
+ * @param cnt Number of bytes in payload
+ * @param data Payload
+ *
+ * @return EC_SUCCESS or error
+ */
+int tcpm_transmit(int port, enum tcpci_msg_type type, uint16_t header,
+		  const uint32_t *data);
+
+/**
+ * TCPC is asserting alert
+ *
+ * @param port Type-C port number
+ */
+void tcpc_alert(int port);
+#endif /* CONFIG_USB_PD_TCPC */
+
+/**
+ * Gets the next waiting RX message.
+ *
+ * @param port Type-C port number
+ * @param payload Pointer to location to copy payload of PD message
+ * @param header The header of PD message
+ *
+ * @return EC_SUCCESS or error
+ */
+int tcpm_dequeue_message(int port, uint32_t *payload, int *header);
+
+/**
+ * Returns true if the tcpm has RX messages waiting to be consumed.
+ */
+int tcpm_has_pending_message(int port);
+
+/**
+ * Clear any pending messages in the RX queue.  This function must be
+ * called from the same context as the caller of tcpm_dequeue_message to avoid
+ * race conditions.
+ */
+void tcpm_clear_pending_messages(int port);
+
+/**
+ * Enable/Disable TCPC Fast Role Swap detection
+ *
+ * @param port Type-C port number
+ * @param enable FRS enable (true) disable (false)
+ * @return EC_SUCCESS on success, or an error
+ */
+int tcpm_set_frs_enable(int port, int enable);
+
+#ifdef CONFIG_CMD_TCPC_DUMP
+static inline void tcpm_dump_registers(int port)
+{
+	const struct tcpm_drv *tcpc = tcpc_config[port].drv;
+
+	if (tcpc->dump_registers)
+		tcpc->dump_registers(port);
+	else
+		tcpc_dump_std_registers(port);
+}
+#endif /* defined(CONFIG_CMD_TCPC_DUMP) */
+
+/**
+ * Disable BIST type-2 mode
+ *
+ * @param port Type-C port number
+ * @return EC_SUCCESS on success, or an error
+ */
+int tcpm_reset_bist_type_2(int port);
+
+#endif
diff --git a/include/driver/tcpm/tusb422_public.h b/include/driver/tcpm/tusb422_public.h
new file mode 100644
index 0000000000..004abdd5c9
--- /dev/null
+++ b/include/driver/tcpm/tusb422_public.h
@@ -0,0 +1,16 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* TI TUSB422 Type-C port controller */
+
+#ifndef __CROS_EC_DRIVER_TCPM_TUSB422_PUBLIC_H
+#define __CROS_EC_DRIVER_TCPM_TUSB422_PUBLIC_H
+
+/* I2C interface */
+#define TUSB422_I2C_ADDR_FLAGS 0x20
+
+extern const struct tcpm_drv tusb422_tcpm_drv;
+
+#endif /* __CROS_EC_DRIVER_TCPM_TUSB422_PUBLIC_H */
diff --git a/include/driver/temp_sensor/f75303.h b/include/driver/temp_sensor/f75303.h
new file mode 100644
index 0000000000..3f2c3c1c17
--- /dev/null
+++ b/include/driver/temp_sensor/f75303.h
@@ -0,0 +1,99 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_F75303_H
+#define __CROS_EC_F75303_H
+
+#include "i2c.h"
+
+#ifdef BOARD_MUSHU
+#define F75303_I2C_ADDR_FLAGS 0x4D
+#else
+#define F75303_I2C_ADDR_FLAGS 0x4C
+#endif
+
+/*
+ * I2C port and address information for all the board F75303 sensors should be
+ * defined in an array of the following structures, with an enum f75303_sensor
+ * indexing the array.  The enum f75303_sensor shall end with a F75303_IDX_COUNT
+ * defining the maximum number of sensors for the board.
+ */
+
+struct f75303_sensor_t {
+	int i2c_port;
+	int i2c_addr_flags;
+};
+
+extern const struct f75303_sensor_t f75303_sensors[];
+
+/*
+ * The F75303 driver only supports a single device instance on the board.
+ * Each device supports 3 temperature sensor types: local, remote1, and
+ * remote2. The f75303_index selects the temperature sensor type to read.
+ */
+enum f75303_index {
+	F75303_IDX_LOCAL,
+	F75303_IDX_REMOTE1,
+	F75303_IDX_REMOTE2,
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+	F75303_IDX_GPU_LOCAL,
+	F75303_IDX_GPU_REMOTE1,
+	F75303_IDX_GPU_REMOTE2,
+#endif
+	F75303_IDX_COUNT,
+};
+
+#define F75303_TEMP_LOCAL_REGISTER 0x00
+#define F75303_TEMP_LOCAL_LOW_REGISTER 0x29
+#define F75303_TEMP_REMOTE1_REGISTER 0x01
+#define F75303_TEMP_REMOTE1_LOW_REGISTER 0x10
+#define F75303_TEMP_REMOTE2_REGISTER 0x23
+#define F75303_TEMP_REMOTE2_LOW_REGISTER 0x24
+
+#define F75303_ALERT_CHANNEL_MASK 0x1F
+#define F75303_DP2_MASK BIT(2)
+#define F75303_DP1_MASK BIT(1)
+#define F75303_LOCAL_MASK BIT(0)
+
+/**
+ * Get the last polled value of a sensor.
+ *
+ * @param idx	Index to read. Idx indicates whether to read die
+ *		temperature or external temperature.
+ * @param temp	Destination for temperature in K.
+ *
+ * @return EC_SUCCESS if successful, non-zero if error.
+ */
+int f75303_get_val(int idx, int *temp);
+
+/**
+ * Get the last polled value of a sensor.
+ *
+ * @param idx		Index to read, from board's enum f75303_sensor
+ *			definition
+ *
+ * @param temp_k_ptr	Destination for temperature in K.
+ *
+ * @return EC_SUCCESS if successful, non-zero if error.
+ */
+int f75303_get_val_k(int idx, int *temp_k_ptr);
+
+/**
+ * Get the last polled value of a sensor.
+ *
+ * @param idx		Index to read, from board's enum f75303_sensor
+ *			definition
+ *
+ * @param temp_mk_ptr	Destination for temperature in mK.
+ *
+ * @return EC_SUCCESS if successful, non-zero if error.
+ */
+int f75303_get_val_mk(int idx, int *temp_mk_ptr);
+
+#ifdef CONFIG_ZEPHYR
+void f75303_update_temperature(int idx);
+#endif /* CONFIG_ZEPHYR */
+
+#endif /* __CROS_EC_F75303_H */
diff --git a/include/driver/temp_sensor/pct2075.h b/include/driver/temp_sensor/pct2075.h
new file mode 100644
index 0000000000..2d374bb2ba
--- /dev/null
+++ b/include/driver/temp_sensor/pct2075.h
@@ -0,0 +1,75 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_PCT2075_H
+#define __CROS_EC_PCT2075_H
+
+#include "i2c.h"
+
+#define PCT2075_I2C_ADDR_FLAGS0 (0x48 | I2C_FLAG_BIG_ENDIAN)
+#define PCT2075_I2C_ADDR_FLAGS1 (0x49 | I2C_FLAG_BIG_ENDIAN)
+#define PCT2075_I2C_ADDR_FLAGS2 (0x4A | I2C_FLAG_BIG_ENDIAN)
+#define PCT2075_I2C_ADDR_FLAGS3 (0x4B | I2C_FLAG_BIG_ENDIAN)
+#define PCT2075_I2C_ADDR_FLAGS4 (0x4C | I2C_FLAG_BIG_ENDIAN)
+#define PCT2075_I2C_ADDR_FLAGS5 (0x4D | I2C_FLAG_BIG_ENDIAN)
+#define PCT2075_I2C_ADDR_FLAGS6 (0x4E | I2C_FLAG_BIG_ENDIAN)
+#define PCT2075_I2C_ADDR_FLAGS7 (0x4F | I2C_FLAG_BIG_ENDIAN)
+
+#define PCT2075_REG_TEMP 0x00
+#define PCT2075_REG_CONF 0x01
+#define PCT2075_REG_THYST 0x02
+#define PCT2075_REG_TOS 0x03
+#define PCT2075_REG_TIDLE 0x04
+
+/*
+ * I2C port and address information for all the board PCT2075 sensors should be
+ * defined in an array of the following structures, with an enum PCT2075_sensor
+ * indexing the array.  The enum PCT2075_sensor shall end with a PCT2075_COUNT
+ * defining the maximum number of sensors for the board.
+ */
+
+struct pct2075_sensor_t {
+	int i2c_port;
+	int i2c_addr_flags;
+};
+
+extern const struct pct2075_sensor_t pct2075_sensors[];
+
+/**
+ * Get the last polled value of a sensor.
+ *
+ * @param idx		Index to read, from board's enum PCT2075_sensor
+ *			definition
+ *
+ * @param temp_k_ptr	Destination for temperature in K.
+ *
+ * @return EC_SUCCESS if successful, non-zero if error.
+ */
+int pct2075_get_val_k(int idx, int *temp_k_ptr);
+
+/**
+ * Get the last polled value of a sensor.
+ *
+ * @param idx		Index to read, from board's enum PCT2075_sensor
+ *			definition
+ *
+ * @param temp_mk_ptr	Destination for temperature in mK.
+ *
+ * @return EC_SUCCESS if successful, non-zero if error.
+ */
+int pct2075_get_val_mk(int idx, int *temp_mk_ptr);
+
+/**
+ * Init the sensors.  Note, this will run automatically on HOOK_INIT, but is
+ * made available for boards which may not always power the sensor in all
+ * states.
+ */
+void pct2075_init(void);
+
+#ifdef CONFIG_ZEPHYR
+void pct2075_update_temperature(int idx);
+#endif /* CONFIG_ZEPHYR */
+
+#endif /* __CROS_EC_PCT2075_H */
diff --git a/include/driver/temp_sensor/sb_tsi.h b/include/driver/temp_sensor/sb_tsi.h
new file mode 100644
index 0000000000..d8b015d200
--- /dev/null
+++ b/include/driver/temp_sensor/sb_tsi.h
@@ -0,0 +1,46 @@
+/* Copyright 2016 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * SB-TSI: SB Temperature Sensor Interface.
+ * This is an I2C temp sensor on the AMD Stony Ridge FT4 SOC.
+ */
+
+#ifndef __CROS_EC_SB_TSI_H
+#define __CROS_EC_SB_TSI_H
+
+#define SB_TSI_I2C_ADDR_FLAGS 0x4C
+
+/* G781 register */
+#define SB_TSI_TEMP_H 0x01
+#define SB_TSI_STATUS 0x02
+#define SB_TSI_CONFIG_1 0x03
+#define SB_TSI_UPDATE_RATE 0x04
+#define SB_TSI_HIGH_TEMP_THRESHOLD_H 0x07
+#define SB_TSI_LOW_TEMP_THRESHOLD_H 0x08
+#define SB_TSI_CONFIG_2 0x09
+#define SB_TSI_TEMP_L 0x10
+#define SB_TSI_TEMP_OFFSET_H 0x11
+#define SB_TSI_TEMP_OFFSET_L 0x12
+#define SB_TSI_HIGH_TEMP_THRESHOLD_L 0x13
+#define SB_TSI_LOW_TEMP_THRESHOLD_L 0x14
+#define SB_TSI_TIMEOUT_CONFIG 0x22
+#define SB_TSI_PSTATE_LIMIT_CONFIG 0x2F
+#define SB_TSI_ALERT_THRESHOLD 0x32
+#define SB_TSI_ALERT_CONFIG 0xBF
+#define SB_TSI_MANUFACTURE_ID 0xFE
+#define SB_TSI_REVISION 0xFF
+
+/**
+ * Get the value of a sensor in K.
+ *
+ * @param idx		Index to read. Only 0 is valid for sb_tsi.
+ * @param temp_ptr	Destination for temperature in K.
+ *
+ * @return EC_SUCCESS if successful, non-zero if error.
+ */
+int sb_tsi_get_val(int idx, int *temp_ptr);
+
+#endif /* __CROS_EC_SB_TSI_H */
diff --git a/driver/temp_sensor/thermistor.h b/include/driver/temp_sensor/thermistor.h
similarity index 83%
rename from driver/temp_sensor/thermistor.h
rename to include/driver/temp_sensor/thermistor.h
index 7ebe2b42ac..3e220b2505 100644
--- a/driver/temp_sensor/thermistor.h
+++ b/include/driver/temp_sensor/thermistor.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,14 +8,16 @@
 #ifndef __CROS_EC_TEMP_SENSOR_THERMISTOR_H
 #define __CROS_EC_TEMP_SENSOR_THERMISTOR_H
 
+#include <stdint.h>
+
 struct thermistor_data_pair {
-	uint8_t mv;	/* Scaled voltage level at ADC (in mV) */
-	uint8_t temp;	/* Temperature in Celsius */
+	uint8_t mv; /* Scaled voltage level at ADC (in mV) */
+	uint8_t temp; /* Temperature in Celsius */
 };
 
 struct thermistor_info {
-	uint8_t scaling_factor;	/* Scaling factor for voltage in data pair. */
-	uint8_t num_pairs;	/* Number of data pairs. */
+	uint8_t scaling_factor; /* Scaling factor for voltage in data pair. */
+	uint8_t num_pairs; /* Number of data pairs. */
 
 	/*
 	 * Values between given data pairs will be calculated as points on
@@ -147,4 +149,20 @@ int get_temp_3v0_22k6_47k_4050b(int idx_adc, int *temp_ptr);
 int get_temp_3v3_30k9_47k_4050b(int idx_adc, int *temp_ptr);
 #endif
 
-#endif  /* __CROS_EC_TEMP_SENSOR_THERMISTOR_NCP15WB_H */
+/**
+ * Reads the sensor's ADC channel and uses a lookup table and interpolation to
+ * argument thermistor_info for interpolation to return a temperature in degrees
+ * K.
+ *
+ * @param idx_adc	The idx value from the temp_sensor_t struct, which is
+ *			the ADC channel to read and convert to degrees K
+ * @param temp_ptr	Destination for temperature (in degrees K)
+ * @param info	Structure containing information about the underlying thermistor
+ * that is necessary to interpolate temperature
+ *
+ * @return EC_SUCCESS, or non-zero if error.
+ */
+int thermistor_get_temperature(int idx_adc, int *temp_ptr,
+			       const struct thermistor_info *info);
+
+#endif /* __CROS_EC_TEMP_SENSOR_THERMISTOR_NCP15WB_H */
diff --git a/include/driver/temp_sensor/tmp112.h b/include/driver/temp_sensor/tmp112.h
new file mode 100644
index 0000000000..3c9a0a004b
--- /dev/null
+++ b/include/driver/temp_sensor/tmp112.h
@@ -0,0 +1,70 @@
+/* Copyright 2016 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_TMP112_H
+#define __CROS_EC_TMP112_H
+
+#include "i2c.h"
+
+#define TMP112_I2C_ADDR_FLAGS0 (0x48 | I2C_FLAG_BIG_ENDIAN)
+#define TMP112_I2C_ADDR_FLAGS1 (0x49 | I2C_FLAG_BIG_ENDIAN)
+#define TMP112_I2C_ADDR_FLAGS2 (0x4A | I2C_FLAG_BIG_ENDIAN)
+#define TMP112_I2C_ADDR_FLAGS3 (0x4B | I2C_FLAG_BIG_ENDIAN)
+
+#define TMP112_REG_TEMP 0x00
+#define TMP112_REG_CONF 0x01
+#define TMP112_REG_HYST 0x02
+#define TMP112_REG_MAX 0x03
+
+/*
+ * I2C port and address information for all the board TMP112 sensors should be
+ * defined in an array of the following structures, with an enum tmp112_sensor
+ * indexing the array.  The enum tmp112_sensor shall end with a TMP112_COUNT
+ * defining the maximum number of sensors for the board.
+ */
+
+struct tmp112_sensor_t {
+	int i2c_port;
+	int i2c_addr_flags;
+};
+
+extern const struct tmp112_sensor_t tmp112_sensors[];
+
+/**
+ * Get the last polled value of a sensor.
+ *
+ * @param idx		Index to read, from board's enum tmp112_sensor
+ *			definition
+ *
+ * @param temp_k_ptr	Destination for temperature in K.
+ *
+ * @return EC_SUCCESS if successful, non-zero if error.
+ */
+int tmp112_get_val_k(int idx, int *temp_k_ptr);
+
+/**
+ * Get the last polled value of a sensor.
+ *
+ * @param idx		Index to read, from board's enum tmp112_sensor
+ *			definition
+ *
+ * @param temp_mk_ptr	Destination for temperature in mK.
+ *
+ * @return EC_SUCCESS if successful, non-zero if error.
+ */
+int tmp112_get_val_mk(int idx, int *temp_mk_ptr);
+
+/**
+ * Init the sensors.  Note, this will run automatically on HOOK_INIT, but is
+ * made available for boards which may not always power the sensor in all
+ * states.
+ */
+void tmp112_init(void);
+
+#ifdef CONFIG_ZEPHYR
+void tmp112_update_temperature(int idx);
+#endif /* CONFIG_ZEPHYR */
+
+#endif /* __CROS_EC_TMP112_H */
diff --git a/include/driver/usb_mux/it5205_public.h b/include/driver/usb_mux/it5205_public.h
new file mode 100644
index 0000000000..40590194c4
--- /dev/null
+++ b/include/driver/usb_mux/it5205_public.h
@@ -0,0 +1,15 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * ITE IT5205 Type-C USB alternate mode mux public header
+ */
+
+#ifndef __CROS_EC_DRIVER_USB_MUX_IT5205_PUBLIC_H
+#define __CROS_EC_DRIVER_USB_MUX_IT5205_PUBLIC_H
+
+/* I2C interface */
+#define IT5205_I2C_ADDR1_FLAGS 0x48
+#define IT5205_I2C_ADDR2_FLAGS 0x58
+
+#endif /* __CROS_EC_DRIVER_USB_MUX_IT5205_PUBLIC_H */
diff --git a/include/driver/usb_mux/ps8743_public.h b/include/driver/usb_mux/ps8743_public.h
new file mode 100644
index 0000000000..6459ecc973
--- /dev/null
+++ b/include/driver/usb_mux/ps8743_public.h
@@ -0,0 +1,115 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Parade PS8743 USB Type-C Redriving Switch for USB Host / DisplayPort.
+ */
+
+#ifndef __CROS_EC_DRIVER_USB_MUX_PS8743_PUBLIC_H
+#define __CROS_EC_DRIVER_USB_MUX_PS8743_PUBLIC_H
+
+#include "usb_mux.h"
+
+#include <inttypes.h>
+
+#define PS8743_I2C_ADDR0_FLAG 0x10
+#define PS8743_I2C_ADDR1_FLAG 0x11
+#define PS8743_I2C_ADDR2_FLAG 0x19
+#define PS8743_I2C_ADDR3_FLAG 0x1a
+
+/* Mode register for setting mux */
+#define PS8743_REG_MODE 0x00
+#define PS8743_MODE_IN_HPD_ASSERT BIT(0)
+#define PS8743_MODE_IN_HPD_CONTROL BIT(1)
+#define PS8743_MODE_FLIP_ENABLE BIT(2)
+#define PS8743_MODE_FLIP_REG_CONTROL BIT(3)
+#define PS8743_MODE_USB_ENABLE BIT(4)
+#define PS8743_MODE_USB_REG_CONTROL BIT(5)
+#define PS8743_MODE_DP_ENABLE BIT(6)
+#define PS8743_MODE_DP_REG_CONTROL BIT(7)
+/* To reset the state machine to default */
+#define PS8743_MODE_POWER_DOWN \
+	(PS8743_MODE_USB_REG_CONTROL | PS8743_MODE_DP_REG_CONTROL)
+/* DP output setting */
+#define PS8743_REG_DP_SETTING 0x07
+#define PS8743_DP_SWG_ADJ_DFLT 0x00
+#define PS8743_DP_SWG_ADJ_N20P 0x40
+#define PS8743_DP_SWG_ADJ_N15P 0x80
+#define PS8743_DP_SWG_ADJ_P15P 0xc0
+#define PS8743_DP_OUT_SWG_400 0x00
+#define PS8743_DP_OUT_SWG_600 0x10
+#define PS8743_DP_OUT_SWG_800 0x20
+#define PS8743_DP_OUT_SWG_1000 0x30
+#define PS8743_DP_OUT_PRE_EM_0_DB 0x00
+#define PS8743_DP_OUT_PRE_EM_3_5_DB 0x04
+#define PS8743_DP_OUT_PRE_EM_6_0_DB 0x08
+#define PS8743_DP_OUT_PRE_EM_9_5_DB 0x0c
+#define PS8743_DP_POST_CUR2_0_DB 0x00
+#define PS8743_DP_POST_CUR2_NEG_0_9_DB 0x01
+#define PS8743_DP_POST_CUR2_NEG_1_9_DB 0x02
+#define PS8743_DP_POST_CUR2_NEG_3_1_DB 0x03
+
+/* USB equalization settings for Host to Mux */
+#define PS8743_REG_USB_EQ_TX 0x32
+#define PS8743_USB_EQ_TX_12_8_DB 0x00
+#define PS8743_USB_EQ_TX_17_DB 0x20
+#define PS8743_USB_EQ_TX_7_7_DB 0x40
+#define PS8743_USB_EQ_TX_3_6_DB 0x60
+#define PS8743_USB_EQ_TX_15_DB 0x80
+#define PS8743_USB_EQ_TX_10_9_DB 0xc0
+#define PS8743_USB_EQ_TX_4_5_DB 0xe0
+
+/* USB swing adjust for Mux to Type-C connector */
+#define PS8743_REG_USB_SWING 0x36
+#define PS8743_OUT_SWG_DEFAULT 0x00
+#define PS8743_OUT_SWG_NEG_20 0x40
+#define PS8743_OUT_SWG_NEG_15 0x80
+#define PS8743_OUT_SWG_POS_15 0xc0
+#define PS8743_LFPS_SWG_DEFAULT 0x00
+#define PS8743_LFPS_SWG_TD 0x08
+
+/* USB equalization settings for Connector to Mux */
+#define PS8743_REG_USB_EQ_RX 0x3b
+#define PS8743_USB_EQ_RX_2_4_DB 0x00
+#define PS8743_USB_EQ_RX_5_DB 0x10
+#define PS8743_USB_EQ_RX_6_5_DB 0x20
+#define PS8743_USB_EQ_RX_7_4_DB 0x30
+#define PS8743_USB_EQ_RX_8_7_DB 0x40
+#define PS8743_USB_EQ_RX_10_9_DB 0x50
+#define PS8743_USB_EQ_RX_12_8_DB 0x60
+#define PS8743_USB_EQ_RX_13_8_DB 0x70
+#define PS8743_USB_EQ_RX_14_8_DB 0x80
+#define PS8743_USB_EQ_RX_15_4_DB 0x90
+#define PS8743_USB_EQ_RX_16_0_DB 0xa0
+#define PS8743_USB_EQ_RX_16_7_DB 0xb0
+#define PS8743_USB_EQ_RX_18_8_DB 0xc0
+#define PS8743_USB_EQ_RX_21_3_DB 0xd0
+#define PS8743_USB_EQ_RX_22_2_DB 0xe0
+
+/* USB High Speed Signal Detector thershold adjustment */
+#define PS8743_REG_HS_DET_THRESHOLD 0x3c
+#define PS8743_USB_HS_THRESH_DEFAULT 0x00
+#define PS8743_USB_HS_THRESH_POS_10 0x20
+#define PS8743_USB_HS_THRESH_POS_33 0x40
+#define PS8743_USB_HS_THRESH_NEG_10 0x60
+#define PS8743_USB_HS_THRESH_NEG_25 0x80
+#define PS8743_USB_HS_THRESH_POS_25 0xa0
+#define PS8743_USB_HS_THRESH_NEG_45 0xc0
+#define PS8743_USB_HS_THRESH_NEG_35 0xe0
+
+/* DCI config: 0x45~0x4D */
+#define PS8743_REG_DCI_CONFIG_2 0x47
+#define PS8743_AUTO_DCI_MODE_SHIFT 6
+#define PS8743_AUTO_DCI_MODE_MASK (3 << PS8743_AUTO_DCI_MODE_SHIFT)
+#define PS8743_AUTO_DCI_MODE_ENABLE (0 << PS8743_AUTO_DCI_MODE_SHIFT)
+#define PS8743_AUTO_DCI_MODE_FORCE_USB (2 << PS8743_AUTO_DCI_MODE_SHIFT)
+#define PS8743_AUTO_DCI_MODE_FORCE_DCI (3 << PS8743_AUTO_DCI_MODE_SHIFT)
+
+int ps8743_tune_usb_eq(const struct usb_mux *me, uint8_t tx, uint8_t rx);
+int ps8743_write(const struct usb_mux *me, uint8_t reg, uint8_t val);
+int ps8743_read(const struct usb_mux *me, uint8_t reg, int *val);
+int ps8743_field_update(const struct usb_mux *me, uint8_t reg, uint8_t mask,
+			uint8_t val);
+int ps8743_check_chip_id(const struct usb_mux *me, int *val);
+
+#endif /* __CROS_EC_DRIVER_USB_MUX_PS8743_PUBLIC_H */
diff --git a/include/ec_cmd_api.h b/include/ec_cmd_api.h
new file mode 100644
index 0000000000..5c8fcb65df
--- /dev/null
+++ b/include/ec_cmd_api.h
@@ -0,0 +1,415 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_EC_CMD_API_H
+#define __CROS_EC_EC_CMD_API_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * This file consists of 3 sections corresponding to the different
+ * methods used to determine the host command API function signature:
+ *
+ * 1. This section consists of functions that do not follow a simple
+ *    pattern and need to be specified explicitly.
+ *
+ * 2. This section consists of functions that can be generated with the
+ *    help of template macros.
+ *
+ * Note:
+ *
+ * A CROS_EC_COMMAND_INFO macro must be defined before including this
+ * file. This is the data type holding the context info identifying the
+ * EC performing the command.
+ *
+ * A CROS_EC_COMMAND macro must be defined before including this file
+ * with the following signature:
+ *
+ * int CROS_EC_COMMAND(CROS_EC_COMMAND_INFO *h,
+ *		       int command, int version,
+ *		       const void *outdata, int outsize,
+ *		       void *indata, int insize)
+ *
+ * This is the function implementing host command messaging with the EC.
+ */
+
+/*
+ * Section 1: Functions that need to be implemented explicitly because
+ * they do not adhere to simple naming that would permit
+ * auto-generation.
+ *
+ * Please keep this list sorted by function name.
+ */
+
+static inline int ec_cmd_get_sku_id(CROS_EC_COMMAND_INFO *h,
+				    struct ec_sku_id_info *r)
+{
+	return CROS_EC_COMMAND(h, EC_CMD_GET_SKU_ID, 0, NULL, 0, r, sizeof(*r));
+}
+
+static inline int
+ec_cmd_mkbp_info_get_next_data(CROS_EC_COMMAND_INFO *h,
+			       const struct ec_params_mkbp_info *p,
+			       union ec_response_get_next_data *r)
+{
+	return CROS_EC_COMMAND(h, EC_CMD_MKBP_INFO, 0, p, sizeof(*p), r,
+			       sizeof(*r));
+}
+
+static inline int ec_cmd_set_sku_id(CROS_EC_COMMAND_INFO *h,
+				    const struct ec_sku_id_info *p)
+{
+	return CROS_EC_COMMAND(h, EC_CMD_SET_SKU_ID, 0, p, sizeof(*p), NULL, 0);
+}
+
+static inline int ec_cmd_thermal_get_threshold_v1(
+	CROS_EC_COMMAND_INFO *h,
+	const struct ec_params_thermal_get_threshold_v1 *p,
+	struct ec_thermal_config *r)
+{
+	return CROS_EC_COMMAND(h, EC_CMD_THERMAL_GET_THRESHOLD, 1, p,
+			       sizeof(*p), r, sizeof(*r));
+}
+
+static inline int
+ec_cmd_usb_pd_dev_info(CROS_EC_COMMAND_INFO *h,
+		       const struct ec_params_usb_pd_info_request *p,
+		       struct ec_params_usb_pd_rw_hash_entry *r)
+{
+	return CROS_EC_COMMAND(h, EC_CMD_USB_PD_DEV_INFO, 0, p, sizeof(*p), r,
+			       sizeof(*r));
+}
+
+static inline int
+ec_cmd_usb_pd_discovery(CROS_EC_COMMAND_INFO *h,
+			const struct ec_params_usb_pd_info_request *p,
+			struct ec_params_usb_pd_discovery_entry *r)
+{
+	return CROS_EC_COMMAND(h, EC_CMD_USB_PD_DISCOVERY, 0, p, sizeof(*p), r,
+			       sizeof(*r));
+}
+
+static inline int
+ec_cmd_usb_pd_set_amode(CROS_EC_COMMAND_INFO *h,
+			const struct ec_params_usb_pd_set_mode_request *p)
+{
+	return CROS_EC_COMMAND(h, EC_CMD_USB_PD_SET_AMODE, 0, p, sizeof(*p),
+			       NULL, 0);
+}
+
+/*
+ * Section 2: EC interface functions that can be generated with the help
+ * of template macros.
+ *
+ * _cmd    host command name
+ * _v      host command version number
+ * _fn     host command function name (will be prefixed with ec_cmd_)
+ * _in     host command input (param) data type (will be prefixed with
+ *         ec_params_)
+ * _out    host command output (response) data type (will be prefixed with
+ *         ec_response_)
+ *
+ * Template macros follow a naming scheme based on the arguments they
+ * require:
+ *
+ * C0      host command version 0, does not need to be specified (most
+ *         common/default case)
+ * CV      host command with specified version
+ *         one of C0, CV is required
+ * F       function name generated (the lower case version of the _cmd arg)
+ *         (required)
+ * PF      parameter type derived from function name (_fn arg)
+ * P       parameter type specified explicitly (i.e. can not be derived from
+ *         _fn arg)
+ *         PF, P are mutually exclusive and optional
+ * RF      response type derived from function name (_fn arg)
+ * R       response type specified explicitly (i.e. can not be derived from
+ *         _fn arg)
+ *         RF, R are mutually exclusive and optional
+ */
+
+/*
+ * Template for EC interface functions that take a param and returns a
+ * response.
+ */
+#define _CROS_EC_CV_F_P_R(_cmd, _v, _fn, _in, _out)                       \
+	static inline int ec_cmd_##_fn(CROS_EC_COMMAND_INFO *h,           \
+				       const struct ec_params_##_in *p,   \
+				       struct ec_response_##_out *r)      \
+	{                                                                 \
+		return CROS_EC_COMMAND(h, (_cmd), (_v), p, sizeof(*p), r, \
+				       sizeof(*r));                       \
+	}
+
+/*
+ * Template for EC interface functions that take a param but do not
+ * return a response.
+ */
+#define _CROS_EC_CV_F_P(_cmd, _v, _fn, _in)                                  \
+	static inline int ec_cmd_##_fn(CROS_EC_COMMAND_INFO *h,              \
+				       const struct ec_params_##_in *p)      \
+	{                                                                    \
+		return CROS_EC_COMMAND(h, (_cmd), (_v), p, sizeof(*p), NULL, \
+				       0);                                   \
+	}
+
+/*
+ * Template for EC interface functions that do not take a param but do
+ * return a response.
+ */
+#define _CROS_EC_CV_F_R(_cmd, _v, _fn, _out)                         \
+	static inline int ec_cmd_##_fn(CROS_EC_COMMAND_INFO *h,      \
+				       struct ec_response_##_out *r) \
+	{                                                            \
+		return CROS_EC_COMMAND(h, (_cmd), (_v), NULL, 0, r,  \
+				       sizeof(*r));                  \
+	}
+
+/*
+ * Template for EC interface functions that do not take a param and do
+ * not return a response.
+ */
+#define _CROS_EC_CV_F(_cmd, _v, _fn)                                       \
+	static inline int ec_cmd_##_fn(CROS_EC_COMMAND_INFO *h)            \
+	{                                                                  \
+		return CROS_EC_COMMAND(h, (_cmd), (_v), NULL, 0, NULL, 0); \
+	}
+
+/*
+ * Shorthand for host command version 0 where param and response name is
+ * derived from the function name.
+ */
+#define _CROS_EC_C0_F_PF_RF(_cmd, _fn) _CROS_EC_CV_F_P_R(_cmd, 0, _fn, _fn, _fn)
+
+/*
+ * Shorthand for host command version 1 where param and response name is
+ * derived from the function name.
+ */
+#define _CROS_EC_C1_F_PF_RF(_cmd, _fn) \
+	_CROS_EC_CV_F_P_R(_cmd, 1, _fn##_v1, _fn##_v1, _fn##_v1)
+
+/*
+ * Shorthand for host command version 0 where param name is
+ * derived from the function name and there is no response.
+ */
+#define _CROS_EC_C0_F_PF(_cmd, _fn) _CROS_EC_CV_F_P(_cmd, 0, _fn, _fn)
+
+/*
+ * Shorthand for host command version 1 where param name is
+ * derived from the function name and there is no response.
+ */
+#define _CROS_EC_C1_F_PF(_cmd, _fn) _CROS_EC_CV_F_P(_cmd, 1, _fn##_v1, _fn##_v1)
+
+/*
+ * Shorthand for host command version 0 where response name is derived
+ * from the function name and there is no param.
+ */
+#define _CROS_EC_C0_F_RF(_cmd, _fn) _CROS_EC_CV_F_R(_cmd, 0, _fn, _fn)
+
+/*
+ * Shorthand for host command version 1 where response name is derived
+ * from the function name and there is no param.
+ */
+#define _CROS_EC_C1_F_RF(_cmd, _fn) _CROS_EC_CV_F_R(_cmd, 1, _fn##_v1, _fn##_v1)
+
+/*
+ * Shorthand for host command version 0 where response and there are no
+ * params or response.
+ */
+#define _CROS_EC_C0_F(_cmd, _fn) _CROS_EC_CV_F(_cmd, 0, _fn)
+
+/*
+ * Please keep this list sorted by host command. Sort with:
+ *
+ * clang-format '--style={BasedOnStyle: InheritParentConfig,
+ * ColumnLimit: 888 }' include/ec_cmd_api.h | grep '^_CROS' |
+ * LC_COLLATE=C sort -t '(' -k 2,2 | clang-format
+ */
+
+_CROS_EC_C0_F_PF_RF(EC_CMD_ADC_READ, adc_read);
+_CROS_EC_CV_F_P(EC_CMD_ADD_ENTROPY, 0, add_entropy, rollback_add_entropy);
+_CROS_EC_C0_F(EC_CMD_AP_RESET, ap_reset);
+_CROS_EC_CV_F_P(EC_CMD_BATTERY_CUT_OFF, 1, battery_cut_off_v1, battery_cutoff);
+_CROS_EC_C0_F(EC_CMD_BATTERY_CUT_OFF, battery_cut_off);
+_CROS_EC_CV_F_P_R(EC_CMD_BATTERY_GET_DYNAMIC, 0, battery_get_dynamic,
+		  battery_dynamic_info, battery_dynamic_info);
+_CROS_EC_CV_F_P_R(EC_CMD_BATTERY_GET_STATIC, 0, battery_get_static,
+		  battery_static_info, battery_static_info);
+_CROS_EC_CV_F_P_R(EC_CMD_BATTERY_GET_STATIC, 1, battery_get_static_v1,
+		  battery_static_info, battery_static_info_v1);
+_CROS_EC_CV_F_P_R(EC_CMD_BATTERY_GET_STATIC, 2, battery_get_static_v2,
+		  battery_static_info, battery_static_info_v2);
+_CROS_EC_C0_F_PF_RF(EC_CMD_BATTERY_VENDOR_PARAM, battery_vendor_param);
+_CROS_EC_C0_F_PF(EC_CMD_BUTTON, button);
+_CROS_EC_C0_F_PF_RF(EC_CMD_CEC_GET, cec_get);
+_CROS_EC_C0_F_PF(EC_CMD_CEC_SET, cec_set);
+_CROS_EC_C0_F_PF_RF(EC_CMD_CHARGESPLASH, chargesplash);
+_CROS_EC_CV_F_P_R(EC_CMD_CHARGE_CONTROL, 2, charge_control_v2, charge_control,
+		  charge_control);
+_CROS_EC_CV_F_P(EC_CMD_CHARGE_CURRENT_LIMIT, 0, charge_current_limit,
+		current_limit);
+_CROS_EC_C0_F_RF(EC_CMD_CHARGE_PORT_COUNT, charge_port_count);
+_CROS_EC_C0_F_PF_RF(EC_CMD_CHARGE_STATE, charge_state);
+_CROS_EC_C0_F_PF(EC_CMD_CONFIG_POWER_BUTTON, config_power_button);
+_CROS_EC_C0_F(EC_CMD_CONSOLE_SNAPSHOT, console_snapshot);
+_CROS_EC_C0_F_PF_RF(EC_CMD_DEVICE_EVENT, device_event);
+_CROS_EC_C0_F_RF(EC_CMD_DISPLAY_SOC, display_soc);
+_CROS_EC_C0_F_PF(EC_CMD_EFS_VERIFY, efs_verify);
+_CROS_EC_C1_F_PF(EC_CMD_EXTERNAL_POWER_LIMIT, external_power_limit);
+_CROS_EC_C0_F_PF(EC_CMD_FLASH_ERASE, flash_erase);
+_CROS_EC_CV_F_R(EC_CMD_FLASH_INFO, 1, flash_info_v1, flash_info_1);
+_CROS_EC_C0_F_RF(EC_CMD_FLASH_INFO, flash_info);
+_CROS_EC_CV_F_P_R(EC_CMD_FLASH_PROTECT, 1, flash_protect_v1, flash_protect,
+		  flash_protect);
+_CROS_EC_C0_F_PF_RF(EC_CMD_FLASH_PROTECT, flash_protect);
+_CROS_EC_CV_F_P_R(EC_CMD_FLASH_REGION_INFO, 1, flash_region_info_v1,
+		  flash_region_info, flash_region_info);
+_CROS_EC_C0_F_RF(EC_CMD_FLASH_SPI_INFO, flash_spi_info);
+_CROS_EC_C0_F_PF(EC_CMD_FORCE_LID_OPEN, force_lid_open);
+_CROS_EC_C0_F_PF_RF(EC_CMD_FP_MODE, fp_mode);
+_CROS_EC_C0_F_PF(EC_CMD_FP_SEED, fp_seed);
+_CROS_EC_C0_F_RF(EC_CMD_FP_STATS, fp_stats);
+_CROS_EC_CV_F_R(EC_CMD_GET_BOARD_VERSION, 0, get_board_version, board_version);
+_CROS_EC_C0_F_RF(EC_CMD_GET_BOOT_TIME, get_boot_time);
+_CROS_EC_C0_F_RF(EC_CMD_GET_CHIP_INFO, get_chip_info);
+_CROS_EC_CV_F_P_R(EC_CMD_GET_CMD_VERSIONS, 1, get_cmd_versions_v1,
+		  get_cmd_versions_v1, get_cmd_versions);
+_CROS_EC_C0_F_PF_RF(EC_CMD_GET_CMD_VERSIONS, get_cmd_versions);
+_CROS_EC_C0_F_RF(EC_CMD_GET_COMMS_STATUS, get_comms_status);
+_CROS_EC_C0_F_RF(EC_CMD_GET_FEATURES, get_features);
+_CROS_EC_CV_F_R(EC_CMD_GET_KEYBD_CONFIG, 0, get_keybd_config, keybd_config);
+_CROS_EC_CV_F_R(EC_CMD_GET_NEXT_EVENT, 2, get_next_event_v2, get_next_event);
+_CROS_EC_C0_F_RF(EC_CMD_GET_NEXT_EVENT, get_next_event);
+_CROS_EC_C0_F_PF_RF(EC_CMD_GET_PD_PORT_CAPS, get_pd_port_caps);
+_CROS_EC_C0_F_RF(EC_CMD_GET_PROTOCOL_INFO, get_protocol_info);
+_CROS_EC_CV_F_R(EC_CMD_GET_UPTIME_INFO, 0, get_uptime_info, uptime_info);
+_CROS_EC_C0_F_RF(EC_CMD_GET_VERSION, get_version);
+_CROS_EC_C1_F_RF(EC_CMD_GET_VERSION, get_version);
+_CROS_EC_C0_F_PF_RF(EC_CMD_GPIO_GET, gpio_get);
+_CROS_EC_C1_F_PF_RF(EC_CMD_GPIO_GET, gpio_get);
+_CROS_EC_C0_F_PF(EC_CMD_GPIO_SET, gpio_set);
+_CROS_EC_CV_F_P_R(EC_CMD_GSV_PAUSE_IN_S5, 0, gsv_pause_in_s5, get_set_value,
+		  get_set_value);
+_CROS_EC_C0_F_PF(EC_CMD_HANG_DETECT, hang_detect);
+_CROS_EC_C0_F_PF_RF(EC_CMD_HELLO, hello);
+_CROS_EC_C0_F_PF_RF(EC_CMD_HIBERNATION_DELAY, hibernation_delay);
+_CROS_EC_C0_F_PF_RF(EC_CMD_HOST_EVENT, host_event);
+_CROS_EC_CV_F_P(EC_CMD_HOST_EVENT_CLEAR, 0, host_event_clear, host_event_mask);
+_CROS_EC_CV_F_P(EC_CMD_HOST_EVENT_CLEAR_B, 0, host_event_clear_b,
+		host_event_mask);
+_CROS_EC_CV_F_R(EC_CMD_HOST_EVENT_GET_B, 0, host_event_get_b, host_event_mask);
+_CROS_EC_CV_F_R(EC_CMD_HOST_EVENT_GET_SCI_MASK, 0, host_event_get_sci_mask,
+		host_event_mask);
+_CROS_EC_CV_F_R(EC_CMD_HOST_EVENT_GET_SMI_MASK, 0, host_event_get_smi_mask,
+		host_event_mask);
+_CROS_EC_CV_F_R(EC_CMD_HOST_EVENT_GET_WAKE_MASK, 0, host_event_get_wake_mask,
+		host_event_mask);
+_CROS_EC_CV_F_P(EC_CMD_HOST_EVENT_SET_SCI_MASK, 0, host_event_set_sci_mask,
+		host_event_mask);
+_CROS_EC_CV_F_P(EC_CMD_HOST_EVENT_SET_SMI_MASK, 0, host_event_set_smi_mask,
+		host_event_mask);
+_CROS_EC_CV_F_P(EC_CMD_HOST_EVENT_SET_WAKE_MASK, 0, host_event_set_wake_mask,
+		host_event_mask);
+_CROS_EC_C0_F_PF(EC_CMD_HOST_SLEEP_EVENT, host_sleep_event);
+_CROS_EC_C1_F_PF_RF(EC_CMD_HOST_SLEEP_EVENT, host_sleep_event);
+_CROS_EC_C0_F_PF_RF(EC_CMD_I2C_CONTROL, i2c_control);
+_CROS_EC_C0_F_PF_RF(EC_CMD_I2C_PASSTHRU_PROTECT, i2c_passthru_protect);
+_CROS_EC_C0_F_RF(EC_CMD_KEYBOARD_FACTORY_TEST, keyboard_factory_test);
+_CROS_EC_CV_F_P_R(EC_CMD_LED_CONTROL, 1, led_control_v1, led_control,
+		  led_control);
+_CROS_EC_C0_F_PF_RF(EC_CMD_LOCATE_CHIP, locate_chip);
+_CROS_EC_C0_F_RF(EC_CMD_MKBP_GET_CONFIG, mkbp_get_config);
+_CROS_EC_C0_F_PF_RF(EC_CMD_MKBP_INFO, mkbp_info);
+_CROS_EC_C0_F_PF(EC_CMD_MKBP_SET_CONFIG, mkbp_set_config);
+_CROS_EC_C0_F_PF(EC_CMD_MKBP_SIMULATE_KEY, mkbp_simulate_key);
+_CROS_EC_CV_F_P_R(EC_CMD_MKBP_WAKE_MASK, 0, mkbp_wake_mask,
+		  mkbp_event_wake_mask, mkbp_event_wake_mask);
+_CROS_EC_CV_F_P_R(EC_CMD_MOTION_SENSE_CMD, 1, motion_sense_cmd_v1, motion_sense,
+		  motion_sense);
+_CROS_EC_CV_F_P_R(EC_CMD_MOTION_SENSE_CMD, 2, motion_sense_cmd_v2, motion_sense,
+		  motion_sense);
+_CROS_EC_CV_F_P_R(EC_CMD_MOTION_SENSE_CMD, 4, motion_sense_cmd_v4, motion_sense,
+		  motion_sense);
+_CROS_EC_CV_F_P(EC_CMD_OVERRIDE_DEDICATED_CHARGER_LIMIT, 0,
+		override_dedicated_charger_limit, dedicated_charger_limit);
+_CROS_EC_C0_F_RF(EC_CMD_PCHG_COUNT, pchg_count);
+_CROS_EC_CV_F_P(EC_CMD_PD_CHARGE_PORT_OVERRIDE, 0, pd_charge_port_override,
+		charge_port_override);
+_CROS_EC_CV_F_P_R(EC_CMD_PD_CHIP_INFO, 1, pd_chip_info_v1, pd_chip_info,
+		  pd_chip_info_v1);
+_CROS_EC_C0_F_PF_RF(EC_CMD_PD_CHIP_INFO, pd_chip_info);
+_CROS_EC_C0_F_PF(EC_CMD_PD_CONTROL, pd_control);
+_CROS_EC_CV_F_R(EC_CMD_PD_HOST_EVENT_STATUS, 0, pd_host_event_status,
+		host_event_status);
+_CROS_EC_C0_F_PF(EC_CMD_PD_WRITE_LOG_ENTRY, pd_write_log_entry);
+_CROS_EC_C0_F_RF(EC_CMD_PORT80_LAST_BOOT, port80_last_boot);
+_CROS_EC_C1_F_RF(EC_CMD_POWER_INFO, power_info);
+_CROS_EC_CV_F_P_R(EC_CMD_PSE, 0, pse, pse, pse_status);
+_CROS_EC_C0_F_RF(EC_CMD_PSTORE_INFO, pstore_info);
+_CROS_EC_C0_F_PF(EC_CMD_PSTORE_WRITE, pstore_write);
+_CROS_EC_C0_F_PF_RF(EC_CMD_PWM_GET_DUTY, pwm_get_duty);
+_CROS_EC_C0_F_RF(EC_CMD_PWM_GET_KEYBOARD_BACKLIGHT, pwm_get_keyboard_backlight);
+_CROS_EC_C0_F_PF(EC_CMD_PWM_SET_DUTY, pwm_set_duty);
+_CROS_EC_C0_F_PF(EC_CMD_PWM_SET_FAN_DUTY, pwm_set_fan_duty_v0);
+_CROS_EC_C0_F_PF(EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT, pwm_set_keyboard_backlight);
+_CROS_EC_C0_F_PF_RF(EC_CMD_RAND_NUM, rand_num);
+_CROS_EC_C0_F(EC_CMD_REBOOT, reboot);
+_CROS_EC_C0_F(EC_CMD_REBOOT_AP_ON_G3, reboot_ap_on_g3);
+_CROS_EC_C1_F_PF(EC_CMD_REBOOT_AP_ON_G3, reboot_ap_on_g3);
+_CROS_EC_C0_F_PF(EC_CMD_REBOOT_EC, reboot_ec);
+_CROS_EC_C0_F_PF(EC_CMD_REGULATOR_ENABLE, regulator_enable);
+_CROS_EC_C0_F_PF_RF(EC_CMD_REGULATOR_GET_VOLTAGE, regulator_get_voltage);
+_CROS_EC_C0_F_PF_RF(EC_CMD_REGULATOR_IS_ENABLED, regulator_is_enabled);
+_CROS_EC_C0_F_PF(EC_CMD_REGULATOR_SET_VOLTAGE, regulator_set_voltage);
+_CROS_EC_C0_F_PF_RF(EC_CMD_RGBKBD, rgbkbd);
+_CROS_EC_C0_F_RF(EC_CMD_ROLLBACK_INFO, rollback_info);
+_CROS_EC_CV_F_R(EC_CMD_RTC_GET_ALARM, 0, rtc_get_alarm, rtc);
+_CROS_EC_CV_F_R(EC_CMD_RTC_GET_VALUE, 0, rtc_get_value, rtc);
+_CROS_EC_CV_F_P(EC_CMD_RTC_SET_ALARM, 0, rtc_set_alarm, rtc);
+_CROS_EC_CV_F_P(EC_CMD_RTC_SET_VALUE, 0, rtc_set_value, rtc);
+_CROS_EC_C0_F_PF(EC_CMD_RWSIG_ACTION, rwsig_action);
+_CROS_EC_C0_F_RF(EC_CMD_RWSIG_CHECK_STATUS, rwsig_check_status);
+_CROS_EC_C0_F_RF(EC_CMD_RWSIG_INFO, rwsig_info);
+_CROS_EC_C0_F_PF(EC_CMD_SET_BASE_STATE, set_base_state);
+_CROS_EC_C0_F_PF(EC_CMD_SET_TABLET_MODE, set_tablet_mode);
+_CROS_EC_C0_F_PF_RF(EC_CMD_SMART_DISCHARGE, smart_discharge);
+_CROS_EC_CV_F_P(EC_CMD_SWITCH_ENABLE_BKLIGHT, 0, switch_enable_bklight,
+		switch_enable_backlight);
+_CROS_EC_CV_F_P(EC_CMD_SWITCH_ENABLE_WIRELESS, 0, switch_enable_wireless,
+		switch_enable_wireless_v0);
+_CROS_EC_C1_F_PF_RF(EC_CMD_SWITCH_ENABLE_WIRELESS, switch_enable_wireless);
+_CROS_EC_C0_F_RF(EC_CMD_SYSINFO, sysinfo);
+_CROS_EC_C0_F_PF_RF(EC_CMD_TEMP_SENSOR_GET_INFO, temp_sensor_get_info);
+_CROS_EC_C0_F_PF_RF(EC_CMD_TEST_PROTOCOL, test_protocol);
+_CROS_EC_C0_F(EC_CMD_THERMAL_AUTO_FAN_CTRL, thermal_auto_fan_ctrl);
+_CROS_EC_C0_F_PF_RF(EC_CMD_THERMAL_GET_THRESHOLD, thermal_get_threshold);
+_CROS_EC_C0_F_PF(EC_CMD_THERMAL_SET_THRESHOLD, thermal_set_threshold);
+_CROS_EC_C1_F_PF(EC_CMD_THERMAL_SET_THRESHOLD, thermal_set_threshold);
+_CROS_EC_C0_F_PF_RF(EC_CMD_TMP006_GET_RAW, tmp006_get_raw);
+_CROS_EC_C0_F_PF(EC_CMD_TYPEC_CONTROL, typec_control);
+_CROS_EC_C0_F_PF_RF(EC_CMD_TYPEC_STATUS, typec_status);
+_CROS_EC_C0_F_PF_RF(EC_CMD_TYPEC_VDM_RESPONSE, typec_vdm_response);
+_CROS_EC_C0_F_PF(EC_CMD_USB_CHARGE_SET_MODE, usb_charge_set_mode);
+_CROS_EC_C0_F_PF(EC_CMD_USB_MUX, usb_mux);
+_CROS_EC_CV_F_P_R(EC_CMD_USB_PD_CONTROL, 2, usb_pd_control_v2, usb_pd_control,
+		  usb_pd_control_v2);
+_CROS_EC_C0_F_PF_RF(EC_CMD_USB_PD_CONTROL, usb_pd_control);
+_CROS_EC_C0_F_PF(EC_CMD_USB_PD_DPS_CONTROL, usb_pd_dps_control);
+_CROS_EC_C0_F_PF(EC_CMD_USB_PD_MUX_ACK, usb_pd_mux_ack);
+_CROS_EC_C0_F_PF_RF(EC_CMD_USB_PD_MUX_INFO, usb_pd_mux_info);
+_CROS_EC_C0_F_RF(EC_CMD_USB_PD_PORTS, usb_pd_ports);
+_CROS_EC_C0_F_PF_RF(EC_CMD_USB_PD_POWER_INFO, usb_pd_power_info);
+_CROS_EC_C0_F_PF(EC_CMD_USB_PD_RW_HASH_ENTRY, usb_pd_rw_hash_entry);
+_CROS_EC_C0_F_PF_RF(EC_CMD_VBOOT_HASH, vboot_hash);
+_CROS_EC_C0_F_PF_RF(EC_CMD_VSTORE_READ, vstore_read);
+_CROS_EC_C0_F_PF(EC_CMD_VSTORE_WRITE, vstore_write);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CROS_EC_EC_CMD_API_H */
diff --git a/include/ec_commands.h b/include/ec_commands.h
index 3b95dcf28a..7fb414870b 100644
--- a/include/ec_commands.h
+++ b/include/ec_commands.h
@@ -1,10 +1,16 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Host communication command constants for Chrome EC */
 
+/*
+ * TODO(b/272518464): Work around coreboot GCC preprocessor bug.
+ * #line marks the *next* line, so it is off by one.
+ */
+#line 13
+
 #ifndef __CROS_EC_EC_COMMANDS_H
 #define __CROS_EC_EC_COMMANDS_H
 
@@ -12,10 +18,6 @@
 #include <stdint.h>
 #endif
 
-#ifdef __cplusplus
-extern "C" {
-#endif
-
 #ifdef CHROMIUM_EC
 /*
  * CHROMIUM_EC is defined by the Makefile system of Chromium EC repository.
@@ -32,8 +34,11 @@ extern "C" {
 #include "compile_time_macros.h"
 
 #else
+/* If BUILD_ASSERT isn't already defined, make it a no-op */
+#ifndef BUILD_ASSERT
 #define BUILD_ASSERT(_cond)
-#endif  /* CHROMIUM_EC */
+#endif /* !BUILD_ASSERT */
+#endif /* CHROMIUM_EC */
 
 #ifdef __KERNEL__
 #include <linux/limits.h>
@@ -46,14 +51,47 @@ extern "C" {
  */
 
 #ifndef BIT
-#define BIT(nr)         (1UL << (nr))
+#define BIT(nr) (1UL << (nr))
 #endif
 
 #ifndef BIT_ULL
-#define BIT_ULL(nr)     (1ULL << (nr))
+#define BIT_ULL(nr) (1ULL << (nr))
+#endif
+
+/*
+ * When building Zephyr, this file ends up being included before Zephyr's
+ * include/sys/util.h so causes a warning there. We don't want to add an #ifdef
+ * in that file since it won't be accepted upstream. So work around it here.
+ */
+#ifndef CONFIG_ZEPHYR
+#ifndef GENMASK
+#define GENMASK(h, l) (((BIT(h) << 1) - 1) ^ (BIT(l) - 1))
+#endif
+
+#ifndef GENMASK_ULL
+#define GENMASK_ULL(h, l) (((BIT_ULL(h) << 1) - 1) ^ (BIT_ULL(l) - 1))
+#endif
+#endif
+
+#endif /* __KERNEL__ */
+
+#ifdef __cplusplus
+extern "C" {
 #endif
 
-#endif  /* __KERNEL__ */
+/**
+ * Constant for creation of flexible array members that work in both C and
+ * C++. Flexible array members were added in C99 and are not part of the C++
+ * standard. However, clang++ supports them for C++.
+ * When compiling with gcc, flexible array members are not allowed to appear
+ * in an otherwise empty struct, so we use the GCC zero-length array
+ * extension that works with both clang/gcc/g++.
+ */
+#if defined(__cplusplus) && defined(__clang__)
+#define FLEXIBLE_ARRAY_MEMBER_SIZE
+#else
+#define FLEXIBLE_ARRAY_MEMBER_SIZE 0
+#endif
 
 /*
  * Current version of this protocol
@@ -62,92 +100,109 @@ extern "C" {
  * determined in other ways.  Remove this once the kernel code no longer
  * depends on it.
  */
-#define EC_PROTO_VERSION          0x00000002
+#define EC_PROTO_VERSION 0x00000002
 
 /* Command version mask */
 #define EC_VER_MASK(version) BIT(version)
 
 /* I/O addresses for ACPI commands */
-#define EC_LPC_ADDR_ACPI_DATA  0x62
-#define EC_LPC_ADDR_ACPI_CMD   0x66
+#define EC_LPC_ADDR_ACPI_DATA 0x62
+#define EC_LPC_ADDR_ACPI_CMD 0x66
 
 /* I/O addresses for host command */
-#define EC_LPC_ADDR_HOST_DATA  0x200
-#define EC_LPC_ADDR_HOST_CMD   0x204
+#define EC_LPC_ADDR_HOST_DATA 0x200
+#define EC_LPC_ADDR_HOST_CMD 0x204
 
 /* I/O addresses for host command args and params */
 /* Protocol version 2 */
-#define EC_LPC_ADDR_HOST_ARGS    0x800  /* And 0x801, 0x802, 0x803 */
-#define EC_LPC_ADDR_HOST_PARAM   0x804  /* For version 2 params; size is
-					 * EC_PROTO2_MAX_PARAM_SIZE
-					 */
+#define EC_LPC_ADDR_HOST_ARGS 0x800 /* And 0x801, 0x802, 0x803 */
+/* For version 2 params; size is EC_PROTO2_MAX_PARAM_SIZE */
+#define EC_LPC_ADDR_HOST_PARAM 0x804
+
 /* Protocol version 3 */
-#define EC_LPC_ADDR_HOST_PACKET  0x800  /* Offset of version 3 packet */
-#define EC_LPC_HOST_PACKET_SIZE  0x100  /* Max size of version 3 packet */
+#define EC_LPC_ADDR_HOST_PACKET 0x800 /* Offset of version 3 packet */
+#define EC_LPC_HOST_PACKET_SIZE 0x100 /* Max size of version 3 packet */
 
 /*
  * The actual block is 0x800-0x8ff, but some BIOSes think it's 0x880-0x8ff
  * and they tell the kernel that so we have to think of it as two parts.
+ *
+ * Other BIOSes report only the I/O port region spanned by the Microchip
+ * MEC series EC; an attempt to address a larger region may fail.
  */
-#define EC_HOST_CMD_REGION0    0x800
-#define EC_HOST_CMD_REGION1    0x880
+#define EC_HOST_CMD_REGION0 0x800
+#define EC_HOST_CMD_REGION1 0x880
 #define EC_HOST_CMD_REGION_SIZE 0x80
+#define EC_HOST_CMD_MEC_REGION_SIZE 0x8
 
 /* EC command register bit functions */
-#define EC_LPC_CMDR_DATA	BIT(0)  /* Data ready for host to read */
-#define EC_LPC_CMDR_PENDING	BIT(1)  /* Write pending to EC */
-#define EC_LPC_CMDR_BUSY	BIT(2)  /* EC is busy processing a command */
-#define EC_LPC_CMDR_CMD		BIT(3)  /* Last host write was a command */
-#define EC_LPC_CMDR_ACPI_BRST	BIT(4)  /* Burst mode (not used) */
-#define EC_LPC_CMDR_SCI		BIT(5)  /* SCI event is pending */
-#define EC_LPC_CMDR_SMI		BIT(6)  /* SMI event is pending */
-
-#define EC_LPC_ADDR_MEMMAP       0x900
-#define EC_MEMMAP_SIZE         255 /* ACPI IO buffer max is 255 bytes */
-#define EC_MEMMAP_TEXT_MAX     8   /* Size of a string in the memory map */
+#define EC_LPC_CMDR_DATA BIT(0) /* Data ready for host to read */
+#define EC_LPC_CMDR_PENDING BIT(1) /* Write pending to EC */
+#define EC_LPC_CMDR_BUSY BIT(2) /* EC is busy processing a command */
+#define EC_LPC_CMDR_CMD BIT(3) /* Last host write was a command */
+#define EC_LPC_CMDR_ACPI_BRST BIT(4) /* Burst mode (not used) */
+#define EC_LPC_CMDR_SCI BIT(5) /* SCI event is pending */
+#define EC_LPC_CMDR_SMI BIT(6) /* SMI event is pending */
+
+#define EC_LPC_ADDR_MEMMAP 0x900
+#define EC_MEMMAP_SIZE 255 /* ACPI IO buffer max is 255 bytes */
+#define EC_MEMMAP_TEXT_MAX 8 /* Size of a string in the memory map */
 
 /* The offset address of each type of data in mapped memory. */
-#define EC_MEMMAP_TEMP_SENSOR      0x00 /* Temp sensors 0x00 - 0x0f */
-#define EC_MEMMAP_FAN              0x10 /* Fan speeds 0x10 - 0x17 */
-#define EC_MEMMAP_TEMP_SENSOR_B    0x18 /* More temp sensors 0x18 - 0x1f */
-#define EC_MEMMAP_ID               0x20 /* 0x20 == 'E', 0x21 == 'C' */
-#define EC_MEMMAP_ID_VERSION       0x22 /* Version of data in 0x20 - 0x2f */
-#define EC_MEMMAP_THERMAL_VERSION  0x23 /* Version of data in 0x00 - 0x1f */
-#define EC_MEMMAP_BATTERY_VERSION  0x24 /* Version of data in 0x40 - 0x7f */
+#define EC_MEMMAP_TEMP_SENSOR 0x00 /* Temp sensors 0x00 - 0x0f */
+#define EC_MEMMAP_FAN 0x10 /* Fan speeds 0x10 - 0x17 */
+#define EC_MEMMAP_TEMP_SENSOR_B 0x18 /* More temp sensors 0x18 - 0x1f */
+#define EC_MEMMAP_ID 0x20 /* 0x20 == 'E', 0x21 == 'C' */
+#define EC_MEMMAP_ID_VERSION 0x22 /* Version of data in 0x20 - 0x2f */
+#define EC_MEMMAP_THERMAL_VERSION 0x23 /* Version of data in 0x00 - 0x1f */
+#define EC_MEMMAP_BATTERY_VERSION 0x24 /* Version of data in 0x40 - 0x7f */
 #define EC_MEMMAP_SWITCHES_VERSION 0x25 /* Version of data in 0x30 - 0x33 */
-#define EC_MEMMAP_EVENTS_VERSION   0x26 /* Version of data in 0x34 - 0x3f */
-#define EC_MEMMAP_HOST_CMD_FLAGS   0x27 /* Host cmd interface flags (8 bits) */
+#define EC_MEMMAP_EVENTS_VERSION 0x26 /* Version of data in 0x34 - 0x3f */
+#define EC_MEMMAP_HOST_CMD_FLAGS 0x27 /* Host cmd interface flags (8 bits) */
 /* Unused 0x28 - 0x2f */
-#define EC_MEMMAP_SWITCHES         0x30	/* 8 bits */
+#define EC_MEMMAP_SWITCHES 0x30 /* 8 bits */
 /* Unused 0x31 - 0x33 */
-#define EC_MEMMAP_HOST_EVENTS      0x34 /* 64 bits */
+#define EC_MEMMAP_HOST_EVENTS 0x34 /* 64 bits */
 /* Battery values are all 32 bits, unless otherwise noted. */
-#define EC_MEMMAP_BATT_VOLT        0x40 /* Battery Present Voltage */
-#define EC_MEMMAP_BATT_RATE        0x44 /* Battery Present Rate */
-#define EC_MEMMAP_BATT_CAP         0x48 /* Battery Remaining Capacity */
-#define EC_MEMMAP_BATT_FLAG        0x4c /* Battery State, see below (8-bit) */
-#define EC_MEMMAP_BATT_COUNT       0x4d /* Battery Count (8-bit) */
-#define EC_MEMMAP_BATT_INDEX       0x4e /* Current Battery Data Index (8-bit) */
+#define EC_MEMMAP_BATT_VOLT 0x40 /* Battery Present Voltage */
+#define EC_MEMMAP_BATT_RATE 0x44 /* Battery Present Rate */
+#define EC_MEMMAP_BATT_CAP 0x48 /* Battery Remaining Capacity */
+#define EC_MEMMAP_BATT_FLAG 0x4c /* Battery State, see below (8-bit) */
+#define EC_MEMMAP_BATT_COUNT 0x4d /* Battery Count (8-bit) */
+#define EC_MEMMAP_BATT_INDEX 0x4e /* Current Battery Data Index (8-bit) */
 /* Unused 0x4f */
-#define EC_MEMMAP_BATT_DCAP        0x50 /* Battery Design Capacity */
-#define EC_MEMMAP_BATT_DVLT        0x54 /* Battery Design Voltage */
-#define EC_MEMMAP_BATT_LFCC        0x58 /* Battery Last Full Charge Capacity */
-#define EC_MEMMAP_BATT_CCNT        0x5c /* Battery Cycle Count */
+#define EC_MEMMAP_BATT_DCAP 0x50 /* Battery Design Capacity */
+#define EC_MEMMAP_BATT_DVLT 0x54 /* Battery Design Voltage */
+#define EC_MEMMAP_BATT_LFCC 0x58 /* Battery Last Full Charge Capacity */
+#define EC_MEMMAP_BATT_CCNT 0x5c /* Battery Cycle Count */
 /* Strings are all 8 bytes (EC_MEMMAP_TEXT_MAX) */
-#define EC_MEMMAP_BATT_MFGR        0x60 /* Battery Manufacturer String */
-#define EC_MEMMAP_BATT_MODEL       0x68 /* Battery Model Number String */
-#define EC_MEMMAP_BATT_SERIAL      0x70 /* Battery Serial Number String */
-#define EC_MEMMAP_BATT_TYPE        0x78 /* Battery Type String */
-#define EC_MEMMAP_ALS              0x80 /* ALS readings in lux (2 X 16 bits) */
+#define EC_MEMMAP_BATT_MFGR 0x60 /* Battery Manufacturer String */
+#define EC_MEMMAP_BATT_MODEL 0x68 /* Battery Model Number String */
+#define EC_MEMMAP_BATT_SERIAL 0x70 /* Battery Serial Number String */
+#define EC_MEMMAP_BATT_TYPE 0x78 /* Battery Type String */
+#define EC_MEMMAP_ALS 0x80 /* ALS readings in lux (2 X 16 bits) */
 /* Unused 0x84 - 0x8f */
-#define EC_MEMMAP_ACC_STATUS       0x90 /* Accelerometer status (8 bits )*/
+#define EC_MEMMAP_ACC_STATUS 0x90 /* Accelerometer status (8 bits )*/
 /* Unused 0x91 */
-#define EC_MEMMAP_ACC_DATA         0x92 /* Accelerometers data 0x92 - 0x9f */
+#define EC_MEMMAP_ACC_DATA 0x92 /* Accelerometers data 0x92 - 0x9f */
 /* 0x92: Lid Angle if available, LID_ANGLE_UNRELIABLE otherwise */
 /* 0x94 - 0x99: 1st Accelerometer */
 /* 0x9a - 0x9f: 2nd Accelerometer */
-#define EC_MEMMAP_GYRO_DATA        0xa0 /* Gyroscope data 0xa0 - 0xa5 */
-/* Unused 0xa6 - 0xdf */
+
+#define EC_MEMMAP_GYRO_DATA 0xa0 /* Gyroscope data 0xa0 - 0xa5 */
+#define EC_MEMMAP_GPU 0xa6 /* GPU-specific, 8 bits */
+
+/*
+ * Bit fields for EC_MEMMAP_GPU
+ * 0:2: D-Notify level (0:D1, ... 4:D5)
+ * 3: Over temperature
+ */
+#define EC_MEMMAP_GPU_D_NOTIFY_MASK GENMASK(2, 0)
+#define EC_MEMMAP_GPU_OVERT_BIT BIT(3)
+
+/* Power Participant related components */
+#define EC_MEMMAP_PWR_SRC 0xa7 /* Power source (8-bit) */
+/* Unused 0xa8 - 0xdf */
 
 /*
  * ACPI is unable to access memory mapped data at or above this offset due to
@@ -157,78 +212,90 @@ extern "C" {
 #define EC_MEMMAP_NO_ACPI 0xe0
 
 /* Define the format of the accelerometer mapped memory status byte. */
-#define EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK  0x0f
-#define EC_MEMMAP_ACC_STATUS_BUSY_BIT        BIT(4)
-#define EC_MEMMAP_ACC_STATUS_PRESENCE_BIT    BIT(7)
+#define EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK 0x0f
+#define EC_MEMMAP_ACC_STATUS_BUSY_BIT BIT(4)
+#define EC_MEMMAP_ACC_STATUS_PRESENCE_BIT BIT(7)
 
 /* Number of temp sensors at EC_MEMMAP_TEMP_SENSOR */
-#define EC_TEMP_SENSOR_ENTRIES     16
+#define EC_TEMP_SENSOR_ENTRIES 16
 /*
  * Number of temp sensors at EC_MEMMAP_TEMP_SENSOR_B.
  *
  * Valid only if EC_MEMMAP_THERMAL_VERSION returns >= 2.
  */
-#define EC_TEMP_SENSOR_B_ENTRIES      8
+#define EC_TEMP_SENSOR_B_ENTRIES 8
+
+/* Max temp sensor entries for host commands */
+#define EC_MAX_TEMP_SENSOR_ENTRIES \
+	(EC_TEMP_SENSOR_ENTRIES + EC_TEMP_SENSOR_B_ENTRIES)
 
 /* Special values for mapped temperature sensors */
-#define EC_TEMP_SENSOR_NOT_PRESENT    0xff
-#define EC_TEMP_SENSOR_ERROR          0xfe
-#define EC_TEMP_SENSOR_NOT_POWERED    0xfd
+#define EC_TEMP_SENSOR_NOT_PRESENT 0xff
+#define EC_TEMP_SENSOR_ERROR 0xfe
+#define EC_TEMP_SENSOR_NOT_POWERED 0xfd
 #define EC_TEMP_SENSOR_NOT_CALIBRATED 0xfc
 /*
  * The offset of temperature value stored in mapped memory.  This allows
  * reporting a temperature range of 200K to 454K = -73C to 181C.
  */
-#define EC_TEMP_SENSOR_OFFSET      200
+#define EC_TEMP_SENSOR_OFFSET 200
 
 /*
  * Number of ALS readings at EC_MEMMAP_ALS
  */
-#define EC_ALS_ENTRIES             2
+#define EC_ALS_ENTRIES 2
 
 /*
  * The default value a temperature sensor will return when it is present but
  * has not been read this boot.  This is a reasonable number to avoid
  * triggering alarms on the host.
  */
-#define EC_TEMP_SENSOR_DEFAULT     (296 - EC_TEMP_SENSOR_OFFSET)
+#define EC_TEMP_SENSOR_DEFAULT (296 - EC_TEMP_SENSOR_OFFSET)
 
-#define EC_FAN_SPEED_ENTRIES       4       /* Number of fans at EC_MEMMAP_FAN */
-#define EC_FAN_SPEED_NOT_PRESENT   0xffff  /* Entry not present */
-#define EC_FAN_SPEED_STALLED       0xfffe  /* Fan stalled */
+#define EC_FAN_SPEED_ENTRIES 4 /* Number of fans at EC_MEMMAP_FAN */
+#define EC_FAN_SPEED_NOT_PRESENT 0xffff /* Entry not present */
+
+/* Report 0 for fan stalled so userspace applications can take
+ * an appropriate action based on this value to control the fan.
+ */
+#define EC_FAN_SPEED_STALLED 0x0
+/* This should be used only for ectool to support old ECs. */
+#define EC_FAN_SPEED_STALLED_DEPRECATED 0xfffe
 
 /* Battery bit flags at EC_MEMMAP_BATT_FLAG. */
-#define EC_BATT_FLAG_AC_PRESENT   0x01
+#define EC_BATT_FLAG_AC_PRESENT 0x01
 #define EC_BATT_FLAG_BATT_PRESENT 0x02
-#define EC_BATT_FLAG_DISCHARGING  0x04
-#define EC_BATT_FLAG_CHARGING     0x08
+#define EC_BATT_FLAG_DISCHARGING 0x04
+#define EC_BATT_FLAG_CHARGING 0x08
 #define EC_BATT_FLAG_LEVEL_CRITICAL 0x10
 /* Set if some of the static/dynamic data is invalid (or outdated). */
 #define EC_BATT_FLAG_INVALID_DATA 0x20
+#define EC_BATT_FLAG_CUT_OFF 0x40
+#define EC_BATT_FLAG_LIMIT_ACTIVE 0x80
 
 /* Switch flags at EC_MEMMAP_SWITCHES */
-#define EC_SWITCH_LID_OPEN               0x01
-#define EC_SWITCH_POWER_BUTTON_PRESSED   0x02
+#define EC_SWITCH_LID_OPEN 0x01
+#define EC_SWITCH_POWER_BUTTON_PRESSED 0x02
 #define EC_SWITCH_WRITE_PROTECT_DISABLED 0x04
 /* Was recovery requested via keyboard; now unused. */
-#define EC_SWITCH_IGNORE1		 0x08
+#define EC_SWITCH_IGNORE1 0x08
 /* Recovery requested via dedicated signal (from servo board) */
-#define EC_SWITCH_DEDICATED_RECOVERY     0x10
+#define EC_SWITCH_DEDICATED_RECOVERY 0x10
 /* Was fake developer mode switch; now unused.  Remove in next refactor. */
-#define EC_SWITCH_IGNORE0                0x20
+#define EC_SWITCH_IGNORE0 0x20
 
 /* Host command interface flags */
 /* Host command interface supports LPC args (LPC interface only) */
-#define EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED  0x01
+#define EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED 0x01
 /* Host command interface supports version 3 protocol */
-#define EC_HOST_CMD_FLAG_VERSION_3   0x02
+#define EC_HOST_CMD_FLAG_VERSION_3 0x02
 
 /* Wireless switch flags */
-#define EC_WIRELESS_SWITCH_ALL       ~0x00  /* All flags */
-#define EC_WIRELESS_SWITCH_WLAN       0x01  /* WLAN radio */
-#define EC_WIRELESS_SWITCH_BLUETOOTH  0x02  /* Bluetooth radio */
-#define EC_WIRELESS_SWITCH_WWAN       0x04  /* WWAN power */
-#define EC_WIRELESS_SWITCH_WLAN_POWER 0x08  /* WLAN power */
+#define EC_WIRELESS_SWITCH_ALL ~0x00 /* All flags */
+#define EC_WIRELESS_SWITCH_WLAN 0x01 /* WLAN radio */
+#define EC_WIRELESS_SWITCH_BLUETOOTH 0x02 /* Bluetooth radio */
+#define EC_WIRELESS_SWITCH_WWAN 0x04 /* WWAN power */
+#define EC_WIRELESS_SWITCH_WLAN_POWER 0x08 /* WLAN power */
 
 /*****************************************************************************/
 /*
@@ -296,19 +363,19 @@ extern "C" {
 /* Valid addresses in ACPI memory space, for read/write commands */
 
 /* Memory space version; set to EC_ACPI_MEM_VERSION_CURRENT */
-#define EC_ACPI_MEM_VERSION            0x00
+#define EC_ACPI_MEM_VERSION 0x00
 /*
  * Test location; writing value here updates test compliment byte to (0xff -
  * value).
  */
-#define EC_ACPI_MEM_TEST               0x01
+#define EC_ACPI_MEM_TEST 0x01
 /* Test compliment; writes here are ignored. */
-#define EC_ACPI_MEM_TEST_COMPLIMENT    0x02
+#define EC_ACPI_MEM_TEST_COMPLIMENT 0x02
 
 /* Keyboard backlight brightness percent (0 - 100) */
 #define EC_ACPI_MEM_KEYBOARD_BACKLIGHT 0x03
 /* DPTF Target Fan Duty (0-100, 0xff for auto/none) */
-#define EC_ACPI_MEM_FAN_DUTY           0x04
+#define EC_ACPI_MEM_FAN_DUTY 0x04
 
 /*
  * DPTF temp thresholds. Any of the EC's temp sensors can have up to two
@@ -325,9 +392,9 @@ extern "C" {
  * have tripped". Setting or enabling the thresholds for a sensor will clear
  * the unread event count for that sensor.
  */
-#define EC_ACPI_MEM_TEMP_ID            0x05
-#define EC_ACPI_MEM_TEMP_THRESHOLD     0x06
-#define EC_ACPI_MEM_TEMP_COMMIT        0x07
+#define EC_ACPI_MEM_TEMP_ID 0x05
+#define EC_ACPI_MEM_TEMP_THRESHOLD 0x06
+#define EC_ACPI_MEM_TEMP_COMMIT 0x07
 /*
  * Here are the bits for the COMMIT register:
  *   bit 0 selects the threshold index for the chosen sensor (0/1)
@@ -352,16 +419,17 @@ extern "C" {
  */
 
 /* DPTF battery charging current limit */
-#define EC_ACPI_MEM_CHARGING_LIMIT     0x08
+#define EC_ACPI_MEM_CHARGING_LIMIT 0x08
 
 /* Charging limit is specified in 64 mA steps */
-#define EC_ACPI_MEM_CHARGING_LIMIT_STEP_MA   64
+#define EC_ACPI_MEM_CHARGING_LIMIT_STEP_MA 64
 /* Value to disable DPTF battery charging limit */
-#define EC_ACPI_MEM_CHARGING_LIMIT_DISABLED  0xff
+#define EC_ACPI_MEM_CHARGING_LIMIT_DISABLED 0xff
 
 /*
  * Report device orientation
  *  Bits       Definition
+ *  4          Off Body/On Body status: 0 = Off Body.
  *  3:1        Device DPTF Profile Number (DDPN)
  *               0   = Reserved for backward compatibility (indicates no valid
  *                     profile number. Host should fall back to using TBMD).
@@ -370,10 +438,12 @@ extern "C" {
  *   0         Tablet Mode Device Indicator (TBMD)
  */
 #define EC_ACPI_MEM_DEVICE_ORIENTATION 0x09
-#define EC_ACPI_MEM_TBMD_SHIFT         0
-#define EC_ACPI_MEM_TBMD_MASK          0x1
-#define EC_ACPI_MEM_DDPN_SHIFT         1
-#define EC_ACPI_MEM_DDPN_MASK          0x7
+#define EC_ACPI_MEM_TBMD_SHIFT 0
+#define EC_ACPI_MEM_TBMD_MASK 0x1
+#define EC_ACPI_MEM_DDPN_SHIFT 1
+#define EC_ACPI_MEM_DDPN_MASK 0x7
+#define EC_ACPI_MEM_STTB_SHIFT 4
+#define EC_ACPI_MEM_STTB_MASK 0x1
 
 /*
  * Report device features. Uses the same format as the host command, except:
@@ -396,7 +466,7 @@ extern "C" {
 #define EC_ACPI_MEM_DEVICE_FEATURES6 0x10
 #define EC_ACPI_MEM_DEVICE_FEATURES7 0x11
 
-#define EC_ACPI_MEM_BATTERY_INDEX    0x12
+#define EC_ACPI_MEM_BATTERY_INDEX 0x12
 
 /*
  * USB Port Power. Each bit indicates whether the corresponding USB ports' power
@@ -407,17 +477,66 @@ extern "C" {
  */
 #define EC_ACPI_MEM_USB_PORT_POWER 0x13
 
+/*
+ * USB Retimer firmware update.
+ * Read:
+ *      Result of last operation AP requested
+ * Write:
+ *      bits[3:0]: USB-C port number
+ *      bits[7:4]: Operation requested by AP
+ *
+ * NDA (no device attached) case:
+ * To update retimer firmware, AP needs set up TBT Alt mode.
+ * AP requests operations in this sequence:
+ * 1. Get port information about which ports support retimer firmware update.
+ * In the query result, each bit represents one port.
+ * 2. Get current MUX mode, it's NDA.
+ * 3. Suspend specified PD port's task.
+ * 4. AP requests EC to enter USB mode -> enter Safe mode -> enter TBT mode ->
+ * update firmware -> disconnect MUX -> resume PD task.
+ *
+ * DA (device attached) cases:
+ * Retimer firmware update is not supported in DA cases.
+ * 1. Get port information about which ports support retimer firmware update
+ * 2. Get current MUX mode, it's DA.
+ * 3. AP continues. No more retimer firmware update activities.
+ *
+ */
+#define EC_ACPI_MEM_USB_RETIMER_FW_UPDATE 0x14
+
+#define USB_RETIMER_FW_UPDATE_OP_SHIFT 4
+#define USB_RETIMER_FW_UPDATE_ERR 0xfe
+#define USB_RETIMER_FW_UPDATE_INVALID_MUX 0xff
+/* Mask to clear unused MUX bits in retimer firmware update  */
+#define USB_RETIMER_FW_UPDATE_MUX_MASK                          \
+	(USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED |       \
+	 USB_PD_MUX_SAFE_MODE | USB_PD_MUX_TBT_COMPAT_ENABLED | \
+	 USB_PD_MUX_USB4_ENABLED)
+
+/* Retimer firmware update operations */
+#define USB_RETIMER_FW_UPDATE_QUERY_PORT 0 /* Which ports has retimer */
+#define USB_RETIMER_FW_UPDATE_SUSPEND_PD 1 /* Suspend PD port */
+#define USB_RETIMER_FW_UPDATE_RESUME_PD 2 /* Resume PD port  */
+#define USB_RETIMER_FW_UPDATE_GET_MUX 3 /* Read current USB MUX  */
+#define USB_RETIMER_FW_UPDATE_SET_USB 4 /* Set MUX to USB mode   */
+#define USB_RETIMER_FW_UPDATE_SET_SAFE 5 /* Set MUX to Safe mode  */
+#define USB_RETIMER_FW_UPDATE_SET_TBT 6 /* Set MUX to TBT mode   */
+#define USB_RETIMER_FW_UPDATE_DISCONNECT 7 /* Set MUX to disconnect */
+
+#define EC_ACPI_MEM_USB_RETIMER_PORT(x) ((x)&0x0f)
+#define EC_ACPI_MEM_USB_RETIMER_OP(x) \
+	(((x)&0xf0) >> USB_RETIMER_FW_UPDATE_OP_SHIFT)
+
 /*
  * ACPI addresses 0x20 - 0xff map to EC_MEMMAP offset 0x00 - 0xdf.  This data
  * is read-only from the AP.  Added in EC_ACPI_MEM_VERSION 2.
  */
-#define EC_ACPI_MEM_MAPPED_BEGIN   0x20
-#define EC_ACPI_MEM_MAPPED_SIZE    0xe0
+#define EC_ACPI_MEM_MAPPED_BEGIN 0x20
+#define EC_ACPI_MEM_MAPPED_SIZE 0xe0
 
 /* Current version of ACPI memory address space */
 #define EC_ACPI_MEM_VERSION_CURRENT 2
 
-
 /*
  * This header file is used in coreboot both in C and ACPI code.  The ACPI code
  * is pre-processed to handle constants but the ASL compiler is unable to
@@ -437,7 +556,7 @@ extern "C" {
 #ifndef __aligned
 #define __aligned(x) __attribute__((aligned(x)))
 #endif
-#endif  /* __KERNEL__ */
+#endif /* __KERNEL__ */
 
 /*
  * Attributes for EC request and response packets.  Just defining __packed
@@ -504,7 +623,7 @@ extern "C" {
 #define __ec_todo_packed __packed
 #define __ec_todo_unpacked
 
-#else  /* !CONFIG_HOSTCMD_ALIGNED */
+#else /* !CONFIG_HOSTCMD_ALIGNED */
 
 /*
  * Packed structures make no assumption about alignment, so they do inefficient
@@ -519,25 +638,25 @@ extern "C" {
 #define __ec_todo_packed __packed
 #define __ec_todo_unpacked
 
-#endif  /* !CONFIG_HOSTCMD_ALIGNED */
+#endif /* !CONFIG_HOSTCMD_ALIGNED */
 
 /* LPC command status byte masks */
 /* EC has written a byte in the data register and host hasn't read it yet */
-#define EC_LPC_STATUS_TO_HOST     0x01
+#define EC_LPC_STATUS_TO_HOST 0x01
 /* Host has written a command/data byte and the EC hasn't read it yet */
-#define EC_LPC_STATUS_FROM_HOST   0x02
+#define EC_LPC_STATUS_FROM_HOST 0x02
 /* EC is processing a command */
-#define EC_LPC_STATUS_PROCESSING  0x04
+#define EC_LPC_STATUS_PROCESSING 0x04
 /* Last write to EC was a command, not data */
-#define EC_LPC_STATUS_LAST_CMD    0x08
+#define EC_LPC_STATUS_LAST_CMD 0x08
 /* EC is in burst mode */
-#define EC_LPC_STATUS_BURST_MODE  0x10
+#define EC_LPC_STATUS_BURST_MODE 0x10
 /* SCI event is pending (requesting SCI query) */
 #define EC_LPC_STATUS_SCI_PENDING 0x20
 /* SMI event is pending (requesting SMI query) */
 #define EC_LPC_STATUS_SMI_PENDING 0x40
 /* (reserved) */
-#define EC_LPC_STATUS_RESERVED    0x80
+#define EC_LPC_STATUS_RESERVED 0x80
 
 /*
  * EC is busy.  This covers both the EC processing a command, and the host has
@@ -558,32 +677,32 @@ enum ec_status {
 	EC_RES_INVALID_RESPONSE = 5,
 	EC_RES_INVALID_VERSION = 6,
 	EC_RES_INVALID_CHECKSUM = 7,
-	EC_RES_IN_PROGRESS = 8,		/* Accepted, command in progress */
-	EC_RES_UNAVAILABLE = 9,		/* No response available */
-	EC_RES_TIMEOUT = 10,		/* We got a timeout */
-	EC_RES_OVERFLOW = 11,		/* Table / data overflow */
-	EC_RES_INVALID_HEADER = 12,     /* Header contains invalid data */
-	EC_RES_REQUEST_TRUNCATED = 13,  /* Didn't get the entire request */
-	EC_RES_RESPONSE_TOO_BIG = 14,   /* Response was too big to handle */
-	EC_RES_BUS_ERROR = 15,		/* Communications bus error */
-	EC_RES_BUSY = 16,		/* Up but too busy.  Should retry */
-	EC_RES_INVALID_HEADER_VERSION = 17,  /* Header version invalid */
-	EC_RES_INVALID_HEADER_CRC = 18,      /* Header CRC invalid */
-	EC_RES_INVALID_DATA_CRC = 19,        /* Data CRC invalid */
-	EC_RES_DUP_UNAVAILABLE = 20,         /* Can't resend response */
-
-	EC_RES_MAX = UINT16_MAX		/**< Force enum to be 16 bits */
+	EC_RES_IN_PROGRESS = 8, /* Accepted, command in progress */
+	EC_RES_UNAVAILABLE = 9, /* No response available */
+	EC_RES_TIMEOUT = 10, /* We got a timeout */
+	EC_RES_OVERFLOW = 11, /* Table / data overflow */
+	EC_RES_INVALID_HEADER = 12, /* Header contains invalid data */
+	EC_RES_REQUEST_TRUNCATED = 13, /* Didn't get the entire request */
+	EC_RES_RESPONSE_TOO_BIG = 14, /* Response was too big to handle */
+	EC_RES_BUS_ERROR = 15, /* Communications bus error */
+	EC_RES_BUSY = 16, /* Up but too busy.  Should retry */
+	EC_RES_INVALID_HEADER_VERSION = 17, /* Header version invalid */
+	EC_RES_INVALID_HEADER_CRC = 18, /* Header CRC invalid */
+	EC_RES_INVALID_DATA_CRC = 19, /* Data CRC invalid */
+	EC_RES_DUP_UNAVAILABLE = 20, /* Can't resend response */
+
+	EC_RES_MAX = UINT16_MAX, /**< Force enum to be 16 bits */
 } __packed;
 BUILD_ASSERT(sizeof(enum ec_status) == sizeof(uint16_t));
 
 /*
- * Host event codes.  Note these are 1-based, not 0-based, because ACPI query
- * EC command uses code 0 to mean "no event pending".  We explicitly specify
- * each value in the enum listing so they won't change if we delete/insert an
- * item or rearrange the list (it needs to be stable across platforms, not
- * just within a single compiled instance).
+ * Host event codes. ACPI query EC command uses code 0 to mean "no event
+ * pending".  We explicitly specify each value in the enum listing so they won't
+ * change if we delete/insert an item or rearrange the list (it needs to be
+ * stable across platforms, not just within a single compiled instance).
  */
 enum host_event_code {
+	EC_HOST_EVENT_NONE = 0,
 	EC_HOST_EVENT_LID_CLOSED = 1,
 	EC_HOST_EVENT_LID_OPEN = 2,
 	EC_HOST_EVENT_POWER_BUTTON = 3,
@@ -596,7 +715,8 @@ enum host_event_code {
 	/* Event generated by a device attached to the EC */
 	EC_HOST_EVENT_DEVICE = 10,
 	EC_HOST_EVENT_THERMAL = 11,
-	EC_HOST_EVENT_USB_CHARGER = 12,
+	/* GPU related event. Formerly named EC_HOST_EVENT_USB_CHARGER. */
+	EC_HOST_EVENT_GPU = 12,
 	EC_HOST_EVENT_KEY_PRESSED = 13,
 	/*
 	 * EC has finished initializing the host interface.  The host can check
@@ -648,6 +768,7 @@ enum host_event_code {
 	 *
 	 * - TABLET/LAPTOP mode
 	 * - detachable base attach/detach event
+	 * - on body/off body transition event
 	 */
 	EC_HOST_EVENT_MODE_CHANGE = 29,
 
@@ -664,10 +785,90 @@ enum host_event_code {
 	 * raw event status via EC_MEMMAP_HOST_EVENTS but the LPC interface is
 	 * not initialized on the EC, or improperly configured on the host.
 	 */
-	EC_HOST_EVENT_INVALID = 32
+	EC_HOST_EVENT_INVALID = 32,
+
+	/* Body detect (lap/desk) change event */
+	EC_HOST_EVENT_BODY_DETECT_CHANGE = 33,
+
+	/* Notify BIOS to change stt table */
+	EC_HOST_EVENT_STT_UPDATE = 57,
+
+	/* For notice host DGPU */
+	EC_HOST_EVENT_DGPU_TYPEC_NOTIFY = 58,
+
+	/* UCSI done */
+	EC_HOST_EVENT_UCSI = 59,
+
+	/* BTP fundtion: update battery capacity */
+	EC_HOST_EVENT_BATT_BTP = 60,
+
+	/* Thermal Qevent fundtion: send Qevent to notice host read acpi temp */
+	EC_HOST_EVENT_THERMAL_QEVENT = 61,
+
+	/* ALS */
+	EC_HOST_EVENT_ALS  = 62,
+
+	/* For modern satndby */
+	EC_HOST_EVENT_PB_RELEASE = 63,
+
+
+	/*
+	 * Only 64 host events are supported. This enum uses 1-based counting so
+	 * it can skip 0 (NONE), so the last legal host event number is 64.
+	 */
 };
+
 /* Host event mask */
-#define EC_HOST_EVENT_MASK(event_code) BIT_ULL((event_code) - 1)
+#define EC_HOST_EVENT_MASK(event_code) BIT_ULL((event_code)-1)
+
+/* clang-format off */
+#define HOST_EVENT_TEXT                                                        \
+	{                                                                      \
+		[EC_HOST_EVENT_NONE] = "NONE",                                 \
+		[EC_HOST_EVENT_LID_CLOSED] = "LID_CLOSED",                     \
+		[EC_HOST_EVENT_LID_OPEN] = "LID_OPEN",                         \
+		[EC_HOST_EVENT_POWER_BUTTON] = "POWER_BUTTON",                 \
+		[EC_HOST_EVENT_AC_CONNECTED] = "AC_CONNECTED",                 \
+		[EC_HOST_EVENT_AC_DISCONNECTED] = "AC_DISCONNECTED",           \
+		[EC_HOST_EVENT_BATTERY_LOW] = "BATTERY_LOW",                   \
+		[EC_HOST_EVENT_BATTERY_CRITICAL] = "BATTERY_CRITICAL",         \
+		[EC_HOST_EVENT_BATTERY] = "BATTERY",                           \
+		[EC_HOST_EVENT_THERMAL_THRESHOLD] = "THERMAL_THRESHOLD",       \
+		[EC_HOST_EVENT_DEVICE] = "DEVICE",                             \
+		[EC_HOST_EVENT_THERMAL] = "THERMAL",                           \
+		[EC_HOST_EVENT_GPU] = "GPU",                                   \
+		[EC_HOST_EVENT_KEY_PRESSED] = "KEY_PRESSED",                   \
+		[EC_HOST_EVENT_INTERFACE_READY] = "INTERFACE_READY",           \
+		[EC_HOST_EVENT_KEYBOARD_RECOVERY] = "KEYBOARD_RECOVERY",       \
+		[EC_HOST_EVENT_THERMAL_SHUTDOWN] = "THERMAL_SHUTDOWN",         \
+		[EC_HOST_EVENT_BATTERY_SHUTDOWN] = "BATTERY_SHUTDOWN",         \
+		[EC_HOST_EVENT_THROTTLE_START] = "THROTTLE_START",             \
+		[EC_HOST_EVENT_THROTTLE_STOP] = "THROTTLE_STOP",               \
+		[EC_HOST_EVENT_HANG_DETECT] = "HANG_DETECT",                   \
+		[EC_HOST_EVENT_HANG_REBOOT] = "HANG_REBOOT",                   \
+		[EC_HOST_EVENT_PD_MCU] = "PD_MCU",                             \
+		[EC_HOST_EVENT_BATTERY_STATUS] = "BATTERY_STATUS",             \
+		[EC_HOST_EVENT_PANIC] = "PANIC",                               \
+		[EC_HOST_EVENT_KEYBOARD_FASTBOOT] = "KEYBOARD_FASTBOOT",       \
+		[EC_HOST_EVENT_RTC] = "RTC",                                   \
+		[EC_HOST_EVENT_MKBP] = "MKBP",                                 \
+		[EC_HOST_EVENT_USB_MUX] = "USB_MUX",                           \
+		[EC_HOST_EVENT_MODE_CHANGE] = "MODE_CHANGE",                   \
+		[EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT] =                  \
+			"KEYBOARD_RECOVERY_HW_REINIT",                         \
+		[EC_HOST_EVENT_WOV] = "WOV",                                   \
+		[EC_HOST_EVENT_INVALID] = "INVALID",                           \
+		[EC_HOST_EVENT_BODY_DETECT_CHANGE] = "BODY_DETECT_CHANGE",     \
+		[EC_HOST_EVENT_STT_UPDATE] =					\
+			"STT_UPDATE",							\
+		[EC_HOST_EVENT_DGPU_TYPEC_NOTIFY] = "DGPU_TYPEC_DETECT",     \
+		[EC_HOST_EVENT_UCSI] = "UCSI",                                 \
+		[EC_HOST_EVENT_BATT_BTP] = "BATTERY_TRIP_POINT",               \
+		[EC_HOST_EVENT_THERMAL_QEVENT] = "THERMAL_QEVENT",             \
+		[EC_HOST_EVENT_ALS] = "ALS_QEVENT",              \
+		[EC_HOST_EVENT_PB_RELEASE] = "POWER_BTN_RELEASE",              \
+	}
+/* clang-format on */
 
 /**
  * struct ec_lpc_host_args - Arguments at EC_LPC_ADDR_HOST_ARGS
@@ -702,7 +903,7 @@ struct ec_lpc_host_args {
  * response.  Command version is 0 and response data from EC is at
  * EC_LPC_ADDR_OLD_PARAM with unknown length.
  */
-#define EC_HOST_ARGS_FLAG_TO_HOST   0x02
+#define EC_HOST_ARGS_FLAG_TO_HOST 0x02
 
 /*****************************************************************************/
 /*
@@ -744,48 +945,52 @@ struct ec_lpc_host_args {
  * request, the AP will clock in bytes until it sees the framing byte, then
  * clock in the response packet.
  */
-#define EC_SPI_FRAME_START    0xec
+#define EC_SPI_FRAME_START 0xec
 
 /*
  * Padding bytes which are clocked out after the end of a response packet.
  */
-#define EC_SPI_PAST_END       0xed
+#define EC_SPI_PAST_END 0xed
 
 /*
- * EC is ready to receive, and has ignored the byte sent by the AP.  EC expects
+ * EC is ready to receive, and has ignored the byte sent by the AP. EC expects
  * that the AP will send a valid packet header (starting with
  * EC_COMMAND_PROTOCOL_3) in the next 32 bytes.
+ *
+ * NOTE: Some SPI configurations place the Most Significant Bit on SDO when
+ *	 CS goes low. This macro has the Most Significant Bit set to zero,
+ *	 so SDO will not be driven high when CS goes low.
  */
-#define EC_SPI_RX_READY       0xf8
+#define EC_SPI_RX_READY 0x78
 
 /*
  * EC has started receiving the request from the AP, but hasn't started
  * processing it yet.
  */
-#define EC_SPI_RECEIVING      0xf9
+#define EC_SPI_RECEIVING 0xf9
 
 /* EC has received the entire request from the AP and is processing it. */
-#define EC_SPI_PROCESSING     0xfa
+#define EC_SPI_PROCESSING 0xfa
 
 /*
  * EC received bad data from the AP, such as a packet header with an invalid
  * length.  EC will ignore all data until chip select deasserts.
  */
-#define EC_SPI_RX_BAD_DATA    0xfb
+#define EC_SPI_RX_BAD_DATA 0xfb
 
 /*
  * EC received data from the AP before it was ready.  That is, the AP asserted
  * chip select and started clocking data before the EC was ready to receive it.
  * EC will ignore all data until chip select deasserts.
  */
-#define EC_SPI_NOT_READY      0xfc
+#define EC_SPI_NOT_READY 0xfc
 
 /*
  * EC was ready to receive a request from the AP.  EC has treated the byte sent
  * by the AP as part of a request packet, or (for old-style ECs) is processing
  * a fully received packet but is not ready to respond yet.
  */
-#define EC_SPI_OLD_READY      0xfd
+#define EC_SPI_OLD_READY 0xfd
 
 /*****************************************************************************/
 
@@ -807,22 +1012,22 @@ struct ec_lpc_host_args {
  */
 #define EC_PROTO2_REQUEST_HEADER_BYTES 3
 #define EC_PROTO2_REQUEST_TRAILER_BYTES 1
-#define EC_PROTO2_REQUEST_OVERHEAD (EC_PROTO2_REQUEST_HEADER_BYTES +	\
-				    EC_PROTO2_REQUEST_TRAILER_BYTES)
+#define EC_PROTO2_REQUEST_OVERHEAD \
+	(EC_PROTO2_REQUEST_HEADER_BYTES + EC_PROTO2_REQUEST_TRAILER_BYTES)
 
 #define EC_PROTO2_RESPONSE_HEADER_BYTES 2
 #define EC_PROTO2_RESPONSE_TRAILER_BYTES 1
-#define EC_PROTO2_RESPONSE_OVERHEAD (EC_PROTO2_RESPONSE_HEADER_BYTES +	\
-				     EC_PROTO2_RESPONSE_TRAILER_BYTES)
+#define EC_PROTO2_RESPONSE_OVERHEAD \
+	(EC_PROTO2_RESPONSE_HEADER_BYTES + EC_PROTO2_RESPONSE_TRAILER_BYTES)
 
 /* Parameter length was limited by the LPC interface */
 #define EC_PROTO2_MAX_PARAM_SIZE 0xfc
 
 /* Maximum request and response packet sizes for protocol version 2 */
-#define EC_PROTO2_MAX_REQUEST_SIZE (EC_PROTO2_REQUEST_OVERHEAD +	\
-				    EC_PROTO2_MAX_PARAM_SIZE)
-#define EC_PROTO2_MAX_RESPONSE_SIZE (EC_PROTO2_RESPONSE_OVERHEAD +	\
-				     EC_PROTO2_MAX_PARAM_SIZE)
+#define EC_PROTO2_MAX_REQUEST_SIZE \
+	(EC_PROTO2_REQUEST_OVERHEAD + EC_PROTO2_MAX_PARAM_SIZE)
+#define EC_PROTO2_MAX_RESPONSE_SIZE \
+	(EC_PROTO2_RESPONSE_OVERHEAD + EC_PROTO2_MAX_PARAM_SIZE)
 
 /*****************************************************************************/
 
@@ -881,7 +1086,7 @@ struct ec_host_response {
  *
  * Packets always start with a request or response header.  They are followed
  * by data_len bytes of data.  If the data_crc_present flag is set, the data
- * bytes are followed by a CRC-8 of that data, using using x^8 + x^2 + x + 1
+ * bytes are followed by a CRC-8 of that data, using x^8 + x^2 + x + 1
  * polynomial.
  *
  * Host algorithm when sending a request q:
@@ -994,15 +1199,15 @@ struct ec_host_response4 {
 } __ec_align4;
 
 /* Fields in fields0 byte */
-#define EC_PACKET4_0_STRUCT_VERSION_MASK	0x0f
-#define EC_PACKET4_0_IS_RESPONSE_MASK		0x10
-#define EC_PACKET4_0_SEQ_NUM_SHIFT		5
-#define EC_PACKET4_0_SEQ_NUM_MASK		0x60
-#define EC_PACKET4_0_SEQ_DUP_MASK		0x80
+#define EC_PACKET4_0_STRUCT_VERSION_MASK 0x0f
+#define EC_PACKET4_0_IS_RESPONSE_MASK 0x10
+#define EC_PACKET4_0_SEQ_NUM_SHIFT 5
+#define EC_PACKET4_0_SEQ_NUM_MASK 0x60
+#define EC_PACKET4_0_SEQ_DUP_MASK 0x80
 
 /* Fields in fields1 byte */
-#define EC_PACKET4_1_COMMAND_VERSION_MASK	0x1f  /* (request only) */
-#define EC_PACKET4_1_DATA_CRC_PRESENT_MASK	0x80
+#define EC_PACKET4_1_COMMAND_VERSION_MASK 0x1f /* (request only) */
+#define EC_PACKET4_1_DATA_CRC_PRESENT_MASK 0x80
 
 /*****************************************************************************/
 /*
@@ -1061,26 +1266,17 @@ struct ec_response_hello {
 /* Get version number */
 #define EC_CMD_GET_VERSION 0x0002
 
-#if !defined(CHROMIUM_EC) && !defined(__KERNEL__)
-/*
- * enum ec_current_image is deprecated and replaced by enum ec_image. This
- * macro exists for backwards compatibility of external projects until they
- * have been updated: b/149987779.
- */
-#define ec_current_image ec_image
-#endif
-
 enum ec_image {
 	EC_IMAGE_UNKNOWN = 0,
 	EC_IMAGE_RO,
 	EC_IMAGE_RW,
 	EC_IMAGE_RW_A = EC_IMAGE_RW,
 	EC_IMAGE_RO_B,
-	EC_IMAGE_RW_B
+	EC_IMAGE_RW_B,
 };
 
 /**
- * struct ec_response_get_version - Response to the get version command.
+ * struct ec_response_get_version - Response to the v0 get version command.
  * @version_string_ro: Null-terminated RO firmware version string.
  * @version_string_rw: Null-terminated RW firmware version string.
  * @reserved: Unused bytes; was previously RW-B firmware version string.
@@ -1089,30 +1285,33 @@ enum ec_image {
 struct ec_response_get_version {
 	char version_string_ro[32];
 	char version_string_rw[32];
-	char reserved[32];
+	char reserved[32]; /* Changed to cros_fwid_ro in version 1 */
 	uint32_t current_image;
 } __ec_align4;
 
-/* Read test */
-#define EC_CMD_READ_TEST 0x0003
-
 /**
- * struct ec_params_read_test - Parameters for the read test command.
- * @offset: Starting value for read buffer.
- * @size: Size to read in bytes.
+ * struct ec_response_get_version_v1 - Response to the v1 get version command.
+ *
+ * ec_response_get_version_v1 is a strict superset of ec_response_get_version.
+ * The v1 response changes the semantics of one field (reserved to cros_fwid_ro)
+ * and adds one additional field (cros_fwid_rw).
+ *
+ * @version_string_ro: Null-terminated RO firmware version string.
+ * @version_string_rw: Null-terminated RW firmware version string.
+ * @cros_fwid_ro: Null-terminated RO CrOS FWID string.
+ * @current_image: One of ec_image.
+ * @cros_fwid_rw: Null-terminated RW CrOS FWID string.
  */
-struct ec_params_read_test {
-	uint32_t offset;
-	uint32_t size;
+struct ec_response_get_version_v1 {
+	char version_string_ro[32];
+	char version_string_rw[32];
+	char cros_fwid_ro[32]; /* Added in version 1 (Used to be reserved) */
+	uint32_t current_image;
+	char cros_fwid_rw[32]; /* Added in version 1 */
 } __ec_align4;
 
-/**
- * struct ec_response_read_test - Response to the read test command.
- * @data: Data returned by the read test command.
- */
-struct ec_response_read_test {
-	uint32_t data[32];
-} __ec_align4;
+/* Read test - OBSOLETE */
+#define EC_CMD_READ_TEST 0x0003
 
 /*
  * Get build information
@@ -1203,11 +1402,11 @@ struct ec_response_get_cmd_versions {
  * lpc must read the status from the command register. Attempting this on
  * lpc will overwrite the args/parameter space and corrupt its data.
  */
-#define EC_CMD_GET_COMMS_STATUS		0x0009
+#define EC_CMD_GET_COMMS_STATUS 0x0009
 
 /* Avoid using ec_status which is for return values */
 enum ec_comms_status {
-	EC_COMMS_STATUS_PROCESSING	= BIT(0),	/* Processing cmd */
+	EC_COMMS_STATUS_PROCESSING = BIT(0), /* Processing cmd */
 };
 
 /**
@@ -1216,11 +1415,11 @@ enum ec_comms_status {
  * @flags: Mask of enum ec_comms_status.
  */
 struct ec_response_get_comms_status {
-	uint32_t flags;		/* Mask of enum ec_comms_status */
+	uint32_t flags; /* Mask of enum ec_comms_status */
 } __ec_align4;
 
 /* Fake a variety of responses, purely for testing purposes. */
-#define EC_CMD_TEST_PROTOCOL		0x000A
+#define EC_CMD_TEST_PROTOCOL 0x000A
 
 /* Tell the EC what to send back to us. */
 struct ec_params_test_protocol {
@@ -1235,7 +1434,7 @@ struct ec_response_test_protocol {
 } __ec_align4;
 
 /* Get protocol information */
-#define EC_CMD_GET_PROTOCOL_INFO	0x000B
+#define EC_CMD_GET_PROTOCOL_INFO 0x000B
 
 /* Flags for ec_response_get_protocol_info.flags */
 /* EC_RES_IN_PROGRESS may be returned if a command is slow */
@@ -1257,12 +1456,11 @@ struct ec_response_get_protocol_info {
 	uint32_t flags;
 } __ec_align4;
 
-
 /*****************************************************************************/
 /* Get/Set miscellaneous values */
 
 /* The upper byte of .flags tells what to do (nothing means "get") */
-#define EC_GSV_SET        0x80000000
+#define EC_GSV_SET 0x80000000
 
 /*
  * The lower three bytes of .flags identifies the parameter, if that has
@@ -1281,11 +1479,11 @@ struct ec_response_get_set_value {
 } __ec_align4;
 
 /* More than one command can use these structs to get/set parameters. */
-#define EC_CMD_GSV_PAUSE_IN_S5	0x000C
+#define EC_CMD_GSV_PAUSE_IN_S5 0x000C
 
 /*****************************************************************************/
 /* List the features supported by the firmware */
-#define EC_CMD_GET_FEATURES  0x000D
+#define EC_CMD_GET_FEATURES 0x000D
 
 /* Supported features */
 enum ec_feature_code {
@@ -1400,6 +1598,38 @@ enum ec_feature_code {
 	EC_FEATURE_SCP = 39,
 	/* The MCU is an Integrated Sensor Hub */
 	EC_FEATURE_ISH = 40,
+	/* New TCPMv2 TYPEC_ prefaced commands supported */
+	EC_FEATURE_TYPEC_CMD = 41,
+	/*
+	 * The EC will wait for direction from the AP to enter Type-C alternate
+	 * modes or USB4.
+	 */
+	EC_FEATURE_TYPEC_REQUIRE_AP_MODE_ENTRY = 42,
+	/*
+	 * The EC will wait for an acknowledge from the AP after setting the
+	 * mux.
+	 */
+	EC_FEATURE_TYPEC_MUX_REQUIRE_AP_ACK = 43,
+	/*
+	 * The EC supports entering and residing in S4.
+	 */
+	EC_FEATURE_S4_RESIDENCY = 44,
+	/*
+	 * The EC supports the AP directing mux sets for the board.
+	 */
+	EC_FEATURE_TYPEC_AP_MUX_SET = 45,
+	/*
+	 * The EC supports the AP composing VDMs for us to send.
+	 */
+	EC_FEATURE_TYPEC_AP_VDM_SEND = 46,
+	/*
+	 * The EC supports system safe mode panic recovery.
+	 */
+	EC_FEATURE_SYSTEM_SAFE_MODE = 47,
+	/*
+	 * The EC will reboot on runtime assertion failures.
+	 */
+	EC_FEATURE_ASSERT_REBOOTS = 48,
 };
 
 #define EC_FEATURE_MASK_0(event_code) BIT(event_code % 32)
@@ -1566,12 +1796,22 @@ struct ec_params_flash_read {
  * struct ec_params_flash_write - Parameters for the flash write command.
  * @offset: Byte offset to write.
  * @size: Size to write in bytes.
+ * @data: Data to write.
+ * @data.words32: uint32_t data to write.
+ * @data.bytes: uint8_t data to write.
  */
 struct ec_params_flash_write {
 	uint32_t offset;
 	uint32_t size;
-	/* Followed by data to write */
+	/* Followed by data to write. This union allows accessing an
+	 * underlying buffer as uint32s or uint8s for convenience.
+	 */
+	union {
+		uint32_t words32[FLEXIBLE_ARRAY_MEMBER_SIZE];
+		uint8_t bytes[FLEXIBLE_ARRAY_MEMBER_SIZE];
+	} data;
 } __ec_align4;
+BUILD_ASSERT(member_size(struct ec_params_flash_write, data) == 0);
 
 /* Erase flash */
 #define EC_CMD_FLASH_ERASE 0x0013
@@ -1604,9 +1844,9 @@ struct ec_params_flash_erase {
  * permitted while erasing. (For instance, STM32F4).
  */
 enum ec_flash_erase_cmd {
-	FLASH_ERASE_SECTOR,     /* Erase and wait for result */
-	FLASH_ERASE_SECTOR_ASYNC,  /* Erase and return immediately. */
-	FLASH_ERASE_GET_RESULT,  /* Ask for last erase result */
+	FLASH_ERASE_SECTOR, /* Erase and wait for result */
+	FLASH_ERASE_SECTOR_ASYNC, /* Erase and return immediately. */
+	FLASH_ERASE_GET_RESULT, /* Ask for last erase result */
 };
 
 /**
@@ -1617,8 +1857,8 @@ enum ec_flash_erase_cmd {
  * @params: Same as v0 parameters.
  */
 struct ec_params_flash_erase_v1 {
-	uint8_t  cmd;
-	uint8_t  reserved;
+	uint8_t cmd;
+	uint8_t reserved;
 	uint16_t flag;
 	struct ec_params_flash_erase params;
 } __ec_align4;
@@ -1634,22 +1874,22 @@ struct ec_params_flash_erase_v1 {
  * If mask=0, simply returns the current flags state.
  */
 #define EC_CMD_FLASH_PROTECT 0x0015
-#define EC_VER_FLASH_PROTECT 1  /* Command version 1 */
+#define EC_VER_FLASH_PROTECT 1 /* Command version 1 */
 
 /* Flags for flash protection */
 /* RO flash code protected when the EC boots */
-#define EC_FLASH_PROTECT_RO_AT_BOOT         BIT(0)
+#define EC_FLASH_PROTECT_RO_AT_BOOT BIT(0)
 /*
  * RO flash code protected now.  If this bit is set, at-boot status cannot
  * be changed.
  */
-#define EC_FLASH_PROTECT_RO_NOW             BIT(1)
+#define EC_FLASH_PROTECT_RO_NOW BIT(1)
 /* Entire flash code protected now, until reboot. */
-#define EC_FLASH_PROTECT_ALL_NOW            BIT(2)
+#define EC_FLASH_PROTECT_ALL_NOW BIT(2)
 /* Flash write protect GPIO is asserted now */
-#define EC_FLASH_PROTECT_GPIO_ASSERTED      BIT(3)
+#define EC_FLASH_PROTECT_GPIO_ASSERTED BIT(3)
 /* Error - at least one bank of flash is stuck locked, and cannot be unlocked */
-#define EC_FLASH_PROTECT_ERROR_STUCK        BIT(4)
+#define EC_FLASH_PROTECT_ERROR_STUCK BIT(4)
 /*
  * Error - flash protection is in inconsistent state.  At least one bank of
  * flash which should be protected is not protected.  Usually fixed by
@@ -1657,16 +1897,17 @@ struct ec_params_flash_erase_v1 {
  */
 #define EC_FLASH_PROTECT_ERROR_INCONSISTENT BIT(5)
 /* Entire flash code protected when the EC boots */
-#define EC_FLASH_PROTECT_ALL_AT_BOOT        BIT(6)
+#define EC_FLASH_PROTECT_ALL_AT_BOOT BIT(6)
 /* RW flash code protected when the EC boots */
-#define EC_FLASH_PROTECT_RW_AT_BOOT         BIT(7)
+#define EC_FLASH_PROTECT_RW_AT_BOOT BIT(7)
 /* RW flash code protected now. */
-#define EC_FLASH_PROTECT_RW_NOW             BIT(8)
+#define EC_FLASH_PROTECT_RW_NOW BIT(8)
 /* Rollback information flash region protected when the EC boots */
-#define EC_FLASH_PROTECT_ROLLBACK_AT_BOOT   BIT(9)
+#define EC_FLASH_PROTECT_ROLLBACK_AT_BOOT BIT(9)
 /* Rollback information flash region protected now */
-#define EC_FLASH_PROTECT_ROLLBACK_NOW       BIT(10)
-
+#define EC_FLASH_PROTECT_ROLLBACK_NOW BIT(10)
+/* Error - Unknown error */
+#define EC_FLASH_PROTECT_ERROR_UNKNOWN BIT(11)
 
 /**
  * struct ec_params_flash_protect - Parameters for the flash protect command.
@@ -1678,6 +1919,19 @@ struct ec_params_flash_protect {
 	uint32_t flags;
 } __ec_align4;
 
+enum flash_protect_action {
+	FLASH_PROTECT_ASYNC = 0,
+	FLASH_PROTECT_GET_RESULT = 1,
+};
+
+/* Version 2 of the command is "asynchronous". */
+struct ec_params_flash_protect_v2 {
+	uint8_t action; /**< enum flash_protect_action */
+	uint8_t reserved[3]; /**< padding for alignment */
+	uint32_t mask;
+	uint32_t flags;
+} __ec_align4;
+
 /**
  * struct ec_response_flash_protect - Response to the flash protect command.
  * @flags: Current value of flash protect flags.
@@ -1745,26 +1999,6 @@ struct ec_response_flash_region_info {
 	uint32_t size;
 } __ec_align4;
 
-/* Read/write VbNvContext */
-#define EC_CMD_VBNV_CONTEXT 0x0017
-#define EC_VER_VBNV_CONTEXT 1
-#define EC_VBNV_BLOCK_SIZE 16
-
-enum ec_vbnvcontext_op {
-	EC_VBNV_CONTEXT_OP_READ,
-	EC_VBNV_CONTEXT_OP_WRITE,
-};
-
-struct ec_params_vbnvcontext {
-	uint32_t op;
-	uint8_t block[EC_VBNV_BLOCK_SIZE];
-} __ec_align4;
-
-struct ec_response_vbnvcontext {
-	uint8_t block[EC_VBNV_BLOCK_SIZE];
-} __ec_align4;
-
-
 /* Get SPI flash information */
 #define EC_CMD_FLASH_SPI_INFO 0x0018
 
@@ -1782,7 +2016,6 @@ struct ec_response_flash_spi_info {
 	uint8_t sr1, sr2;
 } __ec_align1;
 
-
 /* Select flash during flash operations */
 #define EC_CMD_FLASH_SELECT 0x0019
 
@@ -1794,24 +2027,26 @@ struct ec_params_flash_select {
 	uint8_t select;
 } __ec_align4;
 
-
 /**
  * Request random numbers to be generated and returned.
  * Can be used to test the random number generator is truly random.
  * See https://csrc.nist.gov/publications/detail/sp/800-22/rev-1a/final and
  * https://webhome.phy.duke.edu/~rgb/General/dieharder.php.
  */
-#define EC_CMD_RAND_NUM	0x001A
+#define EC_CMD_RAND_NUM 0x001A
 #define EC_VER_RAND_NUM 0
 
 struct ec_params_rand_num {
-	uint16_t num_rand_bytes;	/**< num random bytes to generate */
+	uint16_t num_rand_bytes; /**< num random bytes to generate */
 } __ec_align4;
 
 struct ec_response_rand_num {
-	uint8_t rand[0];		/**< generated random numbers */
-} __ec_align4;
-
+	/**
+	 * generated random numbers in the range of 1 to EC_MAX_INSIZE. The true
+	 * size of rand is determined by ec_params_rand_num's num_rand_bytes.
+	 */
+	uint8_t rand[FLEXIBLE_ARRAY_MEMBER_SIZE];
+} __ec_align1;
 BUILD_ASSERT(sizeof(struct ec_response_rand_num) == 0);
 
 /**
@@ -1867,13 +2102,19 @@ enum sysinfo_flags {
 	SYSTEM_IS_FORCE_LOCKED = BIT(1),
 	SYSTEM_JUMP_ENABLED = BIT(2),
 	SYSTEM_JUMPED_TO_CURRENT_IMAGE = BIT(3),
-	SYSTEM_REBOOT_AT_SHUTDOWN = BIT(4)
+	SYSTEM_REBOOT_AT_SHUTDOWN = BIT(4),
+	/*
+	 * Used internally. It's set when EC_HOST_EVENT_KEYBOARD_RECOVERY is
+	 * set and cleared when the system shuts down (not when the host event
+	 * flag is cleared).
+	 */
+	SYSTEM_IN_MANUAL_RECOVERY = BIT(5),
 };
 
 struct ec_response_sysinfo {
-	uint32_t reset_flags;		/**< EC_RESET_FLAG_* flags */
-	uint32_t current_image;		/**< enum ec_current_image */
-	uint32_t flags;			/**< enum sysinfo_flags */
+	uint32_t reset_flags; /**< EC_RESET_FLAG_* flags */
+	uint32_t current_image; /**< enum ec_image */
+	uint32_t flags; /**< enum sysinfo_flags */
 } __ec_align4;
 
 /*****************************************************************************/
@@ -1946,20 +2187,20 @@ enum ec_pwm_type {
 };
 
 struct ec_params_pwm_set_duty {
-	uint16_t duty;     /* Duty cycle, EC_PWM_MAX_DUTY = 100% */
-	uint8_t pwm_type;  /* ec_pwm_type */
-	uint8_t index;     /* Type-specific index, or 0 if unique */
+	uint16_t duty; /* Duty cycle, EC_PWM_MAX_DUTY = 100% */
+	uint8_t pwm_type; /* ec_pwm_type */
+	uint8_t index; /* Type-specific index, or 0 if unique */
 } __ec_align4;
 
 #define EC_CMD_PWM_GET_DUTY 0x0026
 
 struct ec_params_pwm_get_duty {
-	uint8_t pwm_type;  /* ec_pwm_type */
-	uint8_t index;     /* Type-specific index, or 0 if unique */
+	uint8_t pwm_type; /* ec_pwm_type */
+	uint8_t index; /* Type-specific index, or 0 if unique */
 } __ec_align1;
 
 struct ec_response_pwm_get_duty {
-	uint16_t duty;     /* Duty cycle, EC_PWM_MAX_DUTY = 100% */
+	uint16_t duty; /* Duty cycle, EC_PWM_MAX_DUTY = 100% */
 } __ec_align2;
 
 /*****************************************************************************/
@@ -1986,8 +2227,8 @@ struct lightbar_params_v0 {
 	int32_t google_ramp_up;
 	int32_t google_ramp_down;
 	int32_t s3s0_ramp_up;
-	int32_t s0_tick_delay[2];		/* AC=0/1 */
-	int32_t s0a_tick_delay[2];		/* AC=0/1 */
+	int32_t s0_tick_delay[2]; /* AC=0/1 */
+	int32_t s0a_tick_delay[2]; /* AC=0/1 */
 	int32_t s0s3_ramp_down;
 	int32_t s3_sleep_for;
 	int32_t s3_ramp_up;
@@ -1995,24 +2236,24 @@ struct lightbar_params_v0 {
 
 	/* Oscillation */
 	uint8_t new_s0;
-	uint8_t osc_min[2];			/* AC=0/1 */
-	uint8_t osc_max[2];			/* AC=0/1 */
-	uint8_t w_ofs[2];			/* AC=0/1 */
+	uint8_t osc_min[2]; /* AC=0/1 */
+	uint8_t osc_max[2]; /* AC=0/1 */
+	uint8_t w_ofs[2]; /* AC=0/1 */
 
 	/* Brightness limits based on the backlight and AC. */
-	uint8_t bright_bl_off_fixed[2];		/* AC=0/1 */
-	uint8_t bright_bl_on_min[2];		/* AC=0/1 */
-	uint8_t bright_bl_on_max[2];		/* AC=0/1 */
+	uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */
+	uint8_t bright_bl_on_min[2]; /* AC=0/1 */
+	uint8_t bright_bl_on_max[2]; /* AC=0/1 */
 
 	/* Battery level thresholds */
 	uint8_t battery_threshold[LB_BATTERY_LEVELS - 1];
 
 	/* Map [AC][battery_level] to color index */
-	uint8_t s0_idx[2][LB_BATTERY_LEVELS];	/* AP is running */
-	uint8_t s3_idx[2][LB_BATTERY_LEVELS];	/* AP is sleeping */
+	uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */
+	uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */
 
 	/* Color palette */
-	struct rgb_s color[8];			/* 0-3 are Google colors */
+	struct rgb_s color[8]; /* 0-3 are Google colors */
 } __ec_todo_packed;
 
 struct lightbar_params_v1 {
@@ -2020,8 +2261,8 @@ struct lightbar_params_v1 {
 	int32_t google_ramp_up;
 	int32_t google_ramp_down;
 	int32_t s3s0_ramp_up;
-	int32_t s0_tick_delay[2];		/* AC=0/1 */
-	int32_t s0a_tick_delay[2];		/* AC=0/1 */
+	int32_t s0_tick_delay[2]; /* AC=0/1 */
+	int32_t s0a_tick_delay[2]; /* AC=0/1 */
 	int32_t s0s3_ramp_down;
 	int32_t s3_sleep_for;
 	int32_t s3_ramp_up;
@@ -2041,27 +2282,27 @@ struct lightbar_params_v1 {
 	uint8_t tap_idx[3];
 
 	/* Oscillation */
-	uint8_t osc_min[2];			/* AC=0/1 */
-	uint8_t osc_max[2];			/* AC=0/1 */
-	uint8_t w_ofs[2];			/* AC=0/1 */
+	uint8_t osc_min[2]; /* AC=0/1 */
+	uint8_t osc_max[2]; /* AC=0/1 */
+	uint8_t w_ofs[2]; /* AC=0/1 */
 
 	/* Brightness limits based on the backlight and AC. */
-	uint8_t bright_bl_off_fixed[2];		/* AC=0/1 */
-	uint8_t bright_bl_on_min[2];		/* AC=0/1 */
-	uint8_t bright_bl_on_max[2];		/* AC=0/1 */
+	uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */
+	uint8_t bright_bl_on_min[2]; /* AC=0/1 */
+	uint8_t bright_bl_on_max[2]; /* AC=0/1 */
 
 	/* Battery level thresholds */
 	uint8_t battery_threshold[LB_BATTERY_LEVELS - 1];
 
 	/* Map [AC][battery_level] to color index */
-	uint8_t s0_idx[2][LB_BATTERY_LEVELS];	/* AP is running */
-	uint8_t s3_idx[2][LB_BATTERY_LEVELS];	/* AP is sleeping */
+	uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */
+	uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */
 
 	/* s5: single color pulse on inhibited power-up */
 	uint8_t s5_idx;
 
 	/* Color palette */
-	struct rgb_s color[8];			/* 0-3 are Google colors */
+	struct rgb_s color[8]; /* 0-3 are Google colors */
 } __ec_todo_packed;
 
 /* Lightbar command params v2
@@ -2078,8 +2319,8 @@ struct lightbar_params_v2_timing {
 	int32_t google_ramp_up;
 	int32_t google_ramp_down;
 	int32_t s3s0_ramp_up;
-	int32_t s0_tick_delay[2];		/* AC=0/1 */
-	int32_t s0a_tick_delay[2];		/* AC=0/1 */
+	int32_t s0_tick_delay[2]; /* AC=0/1 */
+	int32_t s0a_tick_delay[2]; /* AC=0/1 */
 	int32_t s0s3_ramp_down;
 	int32_t s3_sleep_for;
 	int32_t s3_ramp_up;
@@ -2103,16 +2344,16 @@ struct lightbar_params_v2_tap {
 
 struct lightbar_params_v2_oscillation {
 	/* Oscillation */
-	uint8_t osc_min[2];			/* AC=0/1 */
-	uint8_t osc_max[2];			/* AC=0/1 */
-	uint8_t w_ofs[2];			/* AC=0/1 */
+	uint8_t osc_min[2]; /* AC=0/1 */
+	uint8_t osc_max[2]; /* AC=0/1 */
+	uint8_t w_ofs[2]; /* AC=0/1 */
 } __ec_todo_packed;
 
 struct lightbar_params_v2_brightness {
 	/* Brightness limits based on the backlight and AC. */
-	uint8_t bright_bl_off_fixed[2];		/* AC=0/1 */
-	uint8_t bright_bl_on_min[2];		/* AC=0/1 */
-	uint8_t bright_bl_on_max[2];		/* AC=0/1 */
+	uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */
+	uint8_t bright_bl_on_min[2]; /* AC=0/1 */
+	uint8_t bright_bl_on_max[2]; /* AC=0/1 */
 } __ec_todo_packed;
 
 struct lightbar_params_v2_thresholds {
@@ -2122,14 +2363,14 @@ struct lightbar_params_v2_thresholds {
 
 struct lightbar_params_v2_colors {
 	/* Map [AC][battery_level] to color index */
-	uint8_t s0_idx[2][LB_BATTERY_LEVELS];	/* AP is running */
-	uint8_t s3_idx[2][LB_BATTERY_LEVELS];	/* AP is sleeping */
+	uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */
+	uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */
 
 	/* s5: single color pulse on inhibited power-up */
 	uint8_t s5_idx;
 
 	/* Color palette */
-	struct rgb_s color[8];			/* 0-3 are Google colors */
+	struct rgb_s color[8]; /* 0-3 are Google colors */
 } __ec_todo_packed;
 
 /* Lightbar program. */
@@ -2140,7 +2381,7 @@ struct lightbar_program {
 } __ec_todo_unpacked;
 
 struct ec_params_lightbar {
-	uint8_t cmd;		      /* Command (see enum lightbar_command) */
+	uint8_t cmd; /* Command (see enum lightbar_command) */
 	union {
 		/*
 		 * The following commands have no args:
@@ -2205,7 +2446,6 @@ struct ec_response_lightbar {
 		struct lightbar_params_v0 get_params_v0;
 		struct lightbar_params_v1 get_params_v1;
 
-
 		struct lightbar_params_v2_timing get_params_v2_timing;
 		struct lightbar_params_v2_tap get_params_v2_tap;
 		struct lightbar_params_v2_oscillation get_params_v2_osc;
@@ -2270,7 +2510,7 @@ enum lightbar_command {
 	LIGHTBAR_CMD_SET_PARAMS_V2_THRESHOLDS = 31,
 	LIGHTBAR_CMD_GET_PARAMS_V2_COLORS = 32,
 	LIGHTBAR_CMD_SET_PARAMS_V2_COLORS = 33,
-	LIGHTBAR_NUM_CMDS
+	LIGHTBAR_NUM_CMDS,
 };
 
 /*****************************************************************************/
@@ -2297,14 +2537,15 @@ enum ec_led_id {
 	/* LED to indicate sysrq debug mode. */
 	EC_LED_ID_SYSRQ_DEBUG_LED,
 
-	EC_LED_ID_COUNT
+	EC_LED_ID_COUNT,
 };
 
 /* LED control flags */
 #define EC_LED_FLAGS_QUERY BIT(0) /* Query LED capability only */
-#define EC_LED_FLAGS_AUTO  BIT(1) /* Switch LED back to automatic control */
+#define EC_LED_FLAGS_AUTO BIT(1) /* Switch LED back to automatic control */
 
 enum ec_led_colors {
+	EC_LED_COLOR_INVALID = -1,
 	EC_LED_COLOR_RED = 0,
 	EC_LED_COLOR_GREEN,
 	EC_LED_COLOR_BLUE,
@@ -2312,12 +2553,12 @@ enum ec_led_colors {
 	EC_LED_COLOR_WHITE,
 	EC_LED_COLOR_AMBER,
 
-	EC_LED_COLOR_COUNT
+	EC_LED_COLOR_COUNT,
 };
 
 struct ec_params_led_control {
-	uint8_t led_id;     /* Which LED to control */
-	uint8_t flags;      /* Control flags */
+	uint8_t led_id; /* Which LED to control */
+	uint8_t flags; /* Control flags */
 
 	uint8_t brightness[EC_LED_COLOR_COUNT];
 } __ec_align1;
@@ -2345,30 +2586,30 @@ struct ec_response_led_control {
 #define EC_CMD_VBOOT_HASH 0x002A
 
 struct ec_params_vboot_hash {
-	uint8_t cmd;             /* enum ec_vboot_hash_cmd */
-	uint8_t hash_type;       /* enum ec_vboot_hash_type */
-	uint8_t nonce_size;      /* Nonce size; may be 0 */
-	uint8_t reserved0;       /* Reserved; set 0 */
-	uint32_t offset;         /* Offset in flash to hash */
-	uint32_t size;           /* Number of bytes to hash */
-	uint8_t nonce_data[64];  /* Nonce data; ignored if nonce_size=0 */
+	uint8_t cmd; /* enum ec_vboot_hash_cmd */
+	uint8_t hash_type; /* enum ec_vboot_hash_type */
+	uint8_t nonce_size; /* Nonce size; may be 0 */
+	uint8_t reserved0; /* Reserved; set 0 */
+	uint32_t offset; /* Offset in flash to hash */
+	uint32_t size; /* Number of bytes to hash */
+	uint8_t nonce_data[64]; /* Nonce data; ignored if nonce_size=0 */
 } __ec_align4;
 
 struct ec_response_vboot_hash {
-	uint8_t status;          /* enum ec_vboot_hash_status */
-	uint8_t hash_type;       /* enum ec_vboot_hash_type */
-	uint8_t digest_size;     /* Size of hash digest in bytes */
-	uint8_t reserved0;       /* Ignore; will be 0 */
-	uint32_t offset;         /* Offset in flash which was hashed */
-	uint32_t size;           /* Number of bytes hashed */
+	uint8_t status; /* enum ec_vboot_hash_status */
+	uint8_t hash_type; /* enum ec_vboot_hash_type */
+	uint8_t digest_size; /* Size of hash digest in bytes */
+	uint8_t reserved0; /* Ignore; will be 0 */
+	uint32_t offset; /* Offset in flash which was hashed */
+	uint32_t size; /* Number of bytes hashed */
 	uint8_t hash_digest[64]; /* Hash digest data */
 } __ec_align4;
 
 enum ec_vboot_hash_cmd {
-	EC_VBOOT_HASH_GET = 0,       /* Get current hash status */
-	EC_VBOOT_HASH_ABORT = 1,     /* Abort calculating current hash */
-	EC_VBOOT_HASH_START = 2,     /* Start computing a new hash */
-	EC_VBOOT_HASH_RECALC = 3,    /* Synchronously compute a new hash */
+	EC_VBOOT_HASH_GET = 0, /* Get current hash status */
+	EC_VBOOT_HASH_ABORT = 1, /* Abort calculating current hash */
+	EC_VBOOT_HASH_START = 2, /* Start computing a new hash */
+	EC_VBOOT_HASH_RECALC = 3, /* Synchronously compute a new hash */
 };
 
 enum ec_vboot_hash_type {
@@ -2386,9 +2627,9 @@ enum ec_vboot_hash_status {
  * If one of these is specified, the EC will automatically update offset and
  * size to the correct values for the specified image (RO or RW).
  */
-#define EC_VBOOT_HASH_OFFSET_RO		0xfffffffe
-#define EC_VBOOT_HASH_OFFSET_ACTIVE	0xfffffffd
-#define EC_VBOOT_HASH_OFFSET_UPDATE	0xfffffffc
+#define EC_VBOOT_HASH_OFFSET_RO 0xfffffffe
+#define EC_VBOOT_HASH_OFFSET_ACTIVE 0xfffffffd
+#define EC_VBOOT_HASH_OFFSET_UPDATE 0xfffffffc
 
 /*
  * 'RW' is vague if there are multiple RW images; we mean the active one,
@@ -2537,7 +2778,7 @@ enum motionsense_command {
 	MOTIONSENSE_CMD_GET_ACTIVITY = 20,
 
 	/* Number of motionsense sub-commands. */
-	MOTIONSENSE_NUM_CMDS
+	MOTIONSENSE_NUM_CMDS,
 };
 
 /* List of motion sensor types. */
@@ -2590,6 +2831,11 @@ enum motionsensor_chip {
 	MOTIONSENSE_CHIP_LIS2DS = 23,
 	MOTIONSENSE_CHIP_BMI260 = 24,
 	MOTIONSENSE_CHIP_ICM426XX = 25,
+	MOTIONSENSE_CHIP_ICM42607 = 26,
+	MOTIONSENSE_CHIP_BMA422 = 27,
+	MOTIONSENSE_CHIP_BMI323 = 28,
+	MOTIONSENSE_CHIP_BMI220 = 29,
+	MOTIONSENSE_CHIP_CM32183 = 30,
 	MOTIONSENSE_CHIP_MAX,
 };
 
@@ -2602,6 +2848,11 @@ enum motionsensor_orientation {
 	MOTIONSENSE_ORIENTATION_UNKNOWN = 4,
 };
 
+struct ec_response_activity_data {
+	uint8_t activity; /* motionsensor_activity */
+	uint8_t state;
+} __ec_todo_packed;
+
 struct ec_response_motion_sensor_data {
 	/* Flags for each sensor. */
 	uint8_t flags;
@@ -2609,17 +2860,16 @@ struct ec_response_motion_sensor_data {
 	uint8_t sensor_num;
 	/* Each sensor is up to 3-axis. */
 	union {
-		int16_t             data[3];
+		int16_t data[3];
 		/* for sensors using unsigned data */
-		uint16_t            udata[3];
+		uint16_t udata[3];
 		struct __ec_todo_packed {
-			uint16_t    reserved;
-			uint32_t    timestamp;
+			uint16_t reserved;
+			uint32_t timestamp;
 		};
 		struct __ec_todo_unpacked {
-			uint8_t     activity; /* motionsensor_activity */
-			uint8_t     state;
-			int16_t     add_info[2];
+			struct ec_response_activity_data activity_data;
+			int16_t add_info[2];
 		};
 	};
 } __ec_todo_packed;
@@ -2663,10 +2913,10 @@ enum motionsensor_activity {
 struct ec_motion_sense_activity {
 	uint8_t sensor_num;
 	uint8_t activity; /* one of enum motionsensor_activity */
-	uint8_t enable;   /* 1: enable, 0: disable */
+	uint8_t enable; /* 1: enable, 0: disable */
 	uint8_t reserved;
-	uint16_t parameters[3]; /* activity dependent parameters */
-} __ec_todo_unpacked;
+	uint16_t parameters[4]; /* activity dependent parameters */
+} __ec_todo_packed;
 
 /* Module flag masks used for the dump sub-command. */
 #define MOTIONSENSE_MODULE_FLAG_ACTIVE BIT(0)
@@ -2684,6 +2934,8 @@ struct ec_motion_sense_activity {
 #define MOTIONSENSE_SENSOR_FLAG_TABLET_MODE BIT(3)
 #define MOTIONSENSE_SENSOR_FLAG_ODR BIT(4)
 
+#define MOTIONSENSE_SENSOR_FLAG_BYPASS_FIFO BIT(7)
+
 /*
  * Send this value for the data element to only perform a read. If you
  * send any other value, the EC will interpret it as data to set and will
@@ -2691,7 +2943,7 @@ struct ec_motion_sense_activity {
  */
 #define EC_MOTION_SENSE_NO_VALUE -1
 
-#define EC_MOTION_SENSE_INVALID_CALIB_TEMP 0x8000
+#define EC_MOTION_SENSE_INVALID_CALIB_TEMP INT16_MIN
 
 /* MOTIONSENSE_CMD_SENSOR_OFFSET subcommand flag */
 /* Set Calibration information */
@@ -2829,7 +3081,6 @@ struct ec_params_motion_sense {
 			uint16_t scale[3];
 		} sensor_scale;
 
-
 		/* Used for MOTIONSENSE_CMD_FIFO_INFO */
 		/* (no params) */
 
@@ -2867,8 +3118,19 @@ struct ec_params_motion_sense {
 			/* Ignored, used for alignment. */
 			uint8_t reserved;
 
-			/* Individual component values to spoof. */
-			int16_t components[3];
+			union {
+				/* Individual component values to spoof. */
+				int16_t components[3];
+
+				/* Used when spoofing an activity */
+				struct {
+					/* enum motionsensor_activity */
+					uint8_t activity_num;
+
+					/* spoof activity state */
+					uint8_t activity_state;
+				};
+			} __ec_todo_packed;
 		} spoof;
 
 		/* Used for MOTIONSENSE_CMD_TABLET_MODE_LID_ANGLE. */
@@ -2902,9 +3164,9 @@ struct ec_params_motion_sense {
 		 */
 		struct __ec_todo_unpacked {
 			uint8_t sensor_num;
-			uint8_t activity;  /* enum motionsensor_activity */
+			uint8_t activity; /* enum motionsensor_activity */
 		} get_activity;
-	};
+	} __ec_todo_packed;
 } __ec_todo_packed;
 
 enum motion_sense_cmd_info_flags {
@@ -3003,19 +3265,19 @@ struct ec_response_motion_sense {
 			/* Current value of the parameter queried. */
 			int32_t ret;
 		} ec_rate, sensor_odr, sensor_range, kb_wake_angle,
-		  fifo_int_enable, spoof;
+			fifo_int_enable, spoof;
 
 		/*
 		 * Used for MOTIONSENSE_CMD_SENSOR_OFFSET,
 		 * PERFORM_CALIB.
 		 */
-		struct __ec_todo_unpacked  {
+		struct __ec_todo_unpacked {
 			int16_t temp;
 			int16_t offset[3];
 		} sensor_offset, perform_calib;
 
 		/* Used for MOTIONSENSE_CMD_SENSOR_SCALE */
-		struct __ec_todo_unpacked  {
+		struct __ec_todo_unpacked {
 			int16_t temp;
 			uint16_t scale[3];
 		} sensor_scale;
@@ -3106,20 +3368,36 @@ enum usb_charge_mode {
 	/* Set USB port to CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE. */
 	USB_CHARGE_MODE_DEFAULT,
 
-	USB_CHARGE_MODE_COUNT
+	USB_CHARGE_MODE_COUNT,
 };
 
 enum usb_suspend_charge {
 	/* Enable charging in suspend */
 	USB_ALLOW_SUSPEND_CHARGE,
 	/* Disable charging in suspend */
-	USB_DISALLOW_SUSPEND_CHARGE
+	USB_DISALLOW_SUSPEND_CHARGE,
 };
 
 struct ec_params_usb_charge_set_mode {
 	uint8_t usb_port_id;
-	uint8_t mode:7;              /* enum usb_charge_mode */
-	uint8_t inhibit_charge:1;    /* enum usb_suspend_charge */
+	uint8_t mode : 7; /* enum usb_charge_mode */
+	uint8_t inhibit_charge : 1; /* enum usb_suspend_charge */
+} __ec_align1;
+
+/*****************************************************************************/
+/* Tablet mode commands */
+
+/* Set tablet mode */
+#define EC_CMD_SET_TABLET_MODE 0x0031
+
+enum tablet_mode_override {
+	TABLET_MODE_DEFAULT,
+	TABLET_MODE_FORCE_TABLET,
+	TABLET_MODE_FORCE_CLAMSHELL,
+};
+
+struct ec_params_set_tablet_mode {
+	uint8_t tablet_mode; /* enum tablet_mode_override */
 } __ec_align1;
 
 /*****************************************************************************/
@@ -3146,16 +3424,16 @@ struct ec_response_pstore_info {
 #define EC_CMD_PSTORE_READ 0x0041
 
 struct ec_params_pstore_read {
-	uint32_t offset;   /* Byte offset to read */
-	uint32_t size;     /* Size to read in bytes */
+	uint32_t offset; /* Byte offset to read */
+	uint32_t size; /* Size to read in bytes */
 } __ec_align4;
 
 /* Write persistent storage */
 #define EC_CMD_PSTORE_WRITE 0x0042
 
 struct ec_params_pstore_write {
-	uint32_t offset;   /* Byte offset to write */
-	uint32_t size;     /* Size to write in bytes */
+	uint32_t offset; /* Byte offset to write */
+	uint32_t size; /* Size to write in bytes */
 	uint8_t data[EC_PSTORE_SIZE_MAX];
 } __ec_align4;
 
@@ -3204,7 +3482,7 @@ struct ec_params_port80_read {
 			uint32_t offset;
 			uint32_t num_entries;
 		} read_buffer;
-	};
+	} __ec_todo_packed;
 } __ec_todo_packed;
 
 struct ec_response_port80_read {
@@ -3298,14 +3576,13 @@ struct ec_response_thermal_get_threshold {
 	uint16_t value;
 } __ec_align2;
 
-
 /* The version 1 structs are visible. */
 enum ec_temp_thresholds {
 	EC_TEMP_THRESH_WARN = 0,
 	EC_TEMP_THRESH_HIGH,
 	EC_TEMP_THRESH_HALT,
 
-	EC_TEMP_THRESH_COUNT
+	EC_TEMP_THRESH_COUNT,
 };
 
 /*
@@ -3333,8 +3610,8 @@ enum ec_temp_thresholds {
 struct ec_thermal_config {
 	uint32_t temp_host[EC_TEMP_THRESH_COUNT]; /* levels of hotness */
 	uint32_t temp_host_release[EC_TEMP_THRESH_COUNT]; /* release levels */
-	uint32_t temp_fan_off;		/* no active cooling needed */
-	uint32_t temp_fan_max;		/* max active cooling needed */
+	uint32_t temp_fan_off; /* no active cooling needed */
+	uint32_t temp_fan_max; /* max active cooling needed */
 } __ec_align4;
 
 /* Version 1 - get config for one sensor. */
@@ -3414,7 +3691,6 @@ struct ec_params_tmp006_set_calibration_v1 {
 	float val[0];
 } __ec_align4;
 
-
 /* Read raw TMP006 data */
 #define EC_CMD_TMP006_GET_RAW 0x0055
 
@@ -3423,8 +3699,8 @@ struct ec_params_tmp006_get_raw {
 } __ec_align1;
 
 struct ec_response_tmp006_get_raw {
-	int32_t t;  /* In 1/100 K */
-	int32_t v;  /* In nV */
+	int32_t t; /* In 1/100 K */
+	int32_t v; /* In nV */
 } __ec_align4;
 
 /*****************************************************************************/
@@ -3507,34 +3783,23 @@ struct ec_params_mkbp_simulate_key {
 	uint8_t pressed;
 } __ec_align1;
 
-#define EC_CMD_GET_KEYBOARD_ID 0x0063
-
-struct ec_response_keyboard_id {
-	uint32_t keyboard_id;
-} __ec_align4;
-
-enum keyboard_id {
-	KEYBOARD_ID_UNSUPPORTED = 0,
-	KEYBOARD_ID_UNREADABLE = 0xffffffff,
-};
-
 /* Configure keyboard scanning */
 #define EC_CMD_MKBP_SET_CONFIG 0x0064
 #define EC_CMD_MKBP_GET_CONFIG 0x0065
 
 /* flags */
 enum mkbp_config_flags {
-	EC_MKBP_FLAGS_ENABLE = 1,	/* Enable keyboard scanning */
+	EC_MKBP_FLAGS_ENABLE = 1, /* Enable keyboard scanning */
 };
 
 enum mkbp_config_valid {
-	EC_MKBP_VALID_SCAN_PERIOD		= BIT(0),
-	EC_MKBP_VALID_POLL_TIMEOUT		= BIT(1),
-	EC_MKBP_VALID_MIN_POST_SCAN_DELAY	= BIT(3),
-	EC_MKBP_VALID_OUTPUT_SETTLE		= BIT(4),
-	EC_MKBP_VALID_DEBOUNCE_DOWN		= BIT(5),
-	EC_MKBP_VALID_DEBOUNCE_UP		= BIT(6),
-	EC_MKBP_VALID_FIFO_MAX_DEPTH		= BIT(7),
+	EC_MKBP_VALID_SCAN_PERIOD = BIT(0),
+	EC_MKBP_VALID_POLL_TIMEOUT = BIT(1),
+	EC_MKBP_VALID_MIN_POST_SCAN_DELAY = BIT(3),
+	EC_MKBP_VALID_OUTPUT_SETTLE = BIT(4),
+	EC_MKBP_VALID_DEBOUNCE_DOWN = BIT(5),
+	EC_MKBP_VALID_DEBOUNCE_UP = BIT(6),
+	EC_MKBP_VALID_FIFO_MAX_DEPTH = BIT(7),
 };
 
 /*
@@ -3544,10 +3809,10 @@ enum mkbp_config_valid {
  * ec_{params/response}_mkbp_get_config.
  */
 struct ec_mkbp_config {
-	uint32_t valid_mask;		/* valid fields */
-	uint8_t flags;		/* some flags (enum mkbp_config_flags) */
-	uint8_t valid_flags;		/* which flags are valid */
-	uint16_t scan_period_us;	/* period between start of scans */
+	uint32_t valid_mask; /* valid fields */
+	uint8_t flags; /* some flags (enum mkbp_config_flags) */
+	uint8_t valid_flags; /* which flags are valid */
+	uint16_t scan_period_us; /* period between start of scans */
 	/* revert to interrupt mode after no activity for this long */
 	uint32_t poll_timeout_us;
 	/*
@@ -3558,8 +3823,8 @@ struct ec_mkbp_config {
 	uint16_t min_post_scan_delay_us;
 	/* delay between setting up output and waiting for it to settle */
 	uint16_t output_settle_us;
-	uint16_t debounce_down_us;	/* time for debounce on key down */
-	uint16_t debounce_up_us;	/* time for debounce on key up */
+	uint16_t debounce_down_us; /* time for debounce on key down */
+	uint16_t debounce_up_us; /* time for debounce on key up */
 	/* maximum depth to allow for fifo (0 = no keyscan output) */
 	uint8_t fifo_max_depth;
 } __ec_align_size1;
@@ -3576,11 +3841,11 @@ struct ec_response_mkbp_get_config {
 #define EC_CMD_KEYSCAN_SEQ_CTRL 0x0066
 
 enum ec_keyscan_seq_cmd {
-	EC_KEYSCAN_SEQ_STATUS = 0,	/* Get status information */
-	EC_KEYSCAN_SEQ_CLEAR = 1,	/* Clear sequence */
-	EC_KEYSCAN_SEQ_ADD = 2,		/* Add item to sequence */
-	EC_KEYSCAN_SEQ_START = 3,	/* Start running sequence */
-	EC_KEYSCAN_SEQ_COLLECT = 4,	/* Collect sequence summary data */
+	EC_KEYSCAN_SEQ_STATUS = 0, /* Get status information */
+	EC_KEYSCAN_SEQ_CLEAR = 1, /* Clear sequence */
+	EC_KEYSCAN_SEQ_ADD = 2, /* Add item to sequence */
+	EC_KEYSCAN_SEQ_START = 3, /* Start running sequence */
+	EC_KEYSCAN_SEQ_COLLECT = 4, /* Collect sequence summary data */
 };
 
 enum ec_collect_flags {
@@ -3588,19 +3853,19 @@ enum ec_collect_flags {
 	 * Indicates this scan was processed by the EC. Due to timing, some
 	 * scans may be skipped.
 	 */
-	EC_KEYSCAN_SEQ_FLAG_DONE	= BIT(0),
+	EC_KEYSCAN_SEQ_FLAG_DONE = BIT(0),
 };
 
 struct ec_collect_item {
-	uint8_t flags;		/* some flags (enum ec_collect_flags) */
+	uint8_t flags; /* some flags (enum ec_collect_flags) */
 } __ec_align1;
 
 struct ec_params_keyscan_seq_ctrl {
-	uint8_t cmd;	/* Command to send (enum ec_keyscan_seq_cmd) */
+	uint8_t cmd; /* Command to send (enum ec_keyscan_seq_cmd) */
 	union {
 		struct __ec_align1 {
-			uint8_t active;		/* still active */
-			uint8_t num_items;	/* number of items */
+			uint8_t active; /* still active */
+			uint8_t num_items; /* number of items */
 			/* Current item being presented */
 			uint8_t cur_item;
 		} status;
@@ -3610,11 +3875,11 @@ struct ec_params_keyscan_seq_ctrl {
 			 * start of the sequence.
 			 */
 			uint32_t time_us;
-			uint8_t scan[0];	/* keyscan data */
+			uint8_t scan[0]; /* keyscan data */
 		} add;
 		struct __ec_align1 {
-			uint8_t start_item;	/* First item to return */
-			uint8_t num_items;	/* Number of items to return */
+			uint8_t start_item; /* First item to return */
+			uint8_t num_items; /* Number of items to return */
 		} collect;
 	};
 } __ec_todo_packed;
@@ -3622,7 +3887,7 @@ struct ec_params_keyscan_seq_ctrl {
 struct ec_result_keyscan_seq_ctrl {
 	union {
 		struct __ec_todo_unpacked {
-			uint8_t num_items;	/* Number of items */
+			uint8_t num_items; /* Number of items */
 			/* Data for each item */
 			struct ec_collect_item item[0];
 		} collect;
@@ -3690,11 +3955,33 @@ enum ec_mkbp_event {
 	/* New online calibration values are available. */
 	EC_MKBP_EVENT_ONLINE_CALIBRATION = 11,
 
+	/* Peripheral device charger event */
+	EC_MKBP_EVENT_PCHG = 12,
+
 	/* Number of MKBP events */
 	EC_MKBP_EVENT_COUNT,
 };
 BUILD_ASSERT(EC_MKBP_EVENT_COUNT <= EC_MKBP_EVENT_TYPE_MASK);
 
+/* clang-format off */
+#define EC_MKBP_EVENT_TEXT                                                     \
+	{                                                                      \
+		[EC_MKBP_EVENT_KEY_MATRIX] = "KEY_MATRIX",                     \
+		[EC_MKBP_EVENT_HOST_EVENT] = "HOST_EVENT",                     \
+		[EC_MKBP_EVENT_SENSOR_FIFO] = "SENSOR_FIFO",                   \
+		[EC_MKBP_EVENT_BUTTON] = "BUTTON",                             \
+		[EC_MKBP_EVENT_SWITCH] = "SWITCH",                             \
+		[EC_MKBP_EVENT_FINGERPRINT] = "FINGERPRINT",                   \
+		[EC_MKBP_EVENT_SYSRQ] = "SYSRQ",                               \
+		[EC_MKBP_EVENT_HOST_EVENT64] = "HOST_EVENT64",                 \
+		[EC_MKBP_EVENT_CEC_EVENT] = "CEC_EVENT",                       \
+		[EC_MKBP_EVENT_CEC_MESSAGE] = "CEC_MESSAGE",                   \
+		[EC_MKBP_EVENT_DP_ALT_MODE_ENTERED] = "DP_ALT_MODE_ENTERED",   \
+		[EC_MKBP_EVENT_ONLINE_CALIBRATION] = "ONLINE_CALIBRATION",     \
+		[EC_MKBP_EVENT_PCHG] = "PCHG",                                 \
+	}
+/* clang-format on */
+
 union __ec_align_offset1 ec_response_get_next_data {
 	uint8_t key_matrix[13];
 
@@ -3762,57 +4049,57 @@ struct ec_response_get_next_event_v1 {
 
 /* Bit indices for buttons and switches.*/
 /* Buttons */
-#define EC_MKBP_POWER_BUTTON	0
-#define EC_MKBP_VOL_UP		1
-#define EC_MKBP_VOL_DOWN	2
-#define EC_MKBP_RECOVERY	3
+#define EC_MKBP_POWER_BUTTON 0
+#define EC_MKBP_VOL_UP 1
+#define EC_MKBP_VOL_DOWN 2
+#define EC_MKBP_RECOVERY 3
 
 /* Switches */
-#define EC_MKBP_LID_OPEN	0
-#define EC_MKBP_TABLET_MODE	1
-#define EC_MKBP_BASE_ATTACHED	2
+#define EC_MKBP_LID_OPEN 0
+#define EC_MKBP_TABLET_MODE 1
+#define EC_MKBP_BASE_ATTACHED 2
+#define EC_MKBP_FRONT_PROXIMITY 3
 
 /* Run keyboard factory test scanning */
 #define EC_CMD_KEYBOARD_FACTORY_TEST 0x0068
 
 struct ec_response_keyboard_factory_test {
-	uint16_t shorted;	/* Keyboard pins are shorted */
+	uint16_t shorted; /* Keyboard pins are shorted */
 } __ec_align2;
 
 /* Fingerprint events in 'fp_events' for EC_MKBP_EVENT_FINGERPRINT */
-#define EC_MKBP_FP_RAW_EVENT(fp_events) ((fp_events) & 0x00FFFFFF)
-#define EC_MKBP_FP_ERRCODE(fp_events)   ((fp_events) & 0x0000000F)
+#define EC_MKBP_FP_RAW_EVENT(fp_events) ((fp_events)&0x00FFFFFF)
+#define EC_MKBP_FP_ERRCODE(fp_events) ((fp_events)&0x0000000F)
 #define EC_MKBP_FP_ENROLL_PROGRESS_OFFSET 4
-#define EC_MKBP_FP_ENROLL_PROGRESS(fpe) (((fpe) & 0x00000FF0) \
-					 >> EC_MKBP_FP_ENROLL_PROGRESS_OFFSET)
+#define EC_MKBP_FP_ENROLL_PROGRESS(fpe) \
+	(((fpe)&0x00000FF0) >> EC_MKBP_FP_ENROLL_PROGRESS_OFFSET)
 #define EC_MKBP_FP_MATCH_IDX_OFFSET 12
 #define EC_MKBP_FP_MATCH_IDX_MASK 0x0000F000
-#define EC_MKBP_FP_MATCH_IDX(fpe) (((fpe) & EC_MKBP_FP_MATCH_IDX_MASK) \
-					 >> EC_MKBP_FP_MATCH_IDX_OFFSET)
-#define EC_MKBP_FP_ENROLL               BIT(27)
-#define EC_MKBP_FP_MATCH                BIT(28)
-#define EC_MKBP_FP_FINGER_DOWN          BIT(29)
-#define EC_MKBP_FP_FINGER_UP            BIT(30)
-#define EC_MKBP_FP_IMAGE_READY          BIT(31)
+#define EC_MKBP_FP_MATCH_IDX(fpe) \
+	(((fpe)&EC_MKBP_FP_MATCH_IDX_MASK) >> EC_MKBP_FP_MATCH_IDX_OFFSET)
+#define EC_MKBP_FP_ENROLL BIT(27)
+#define EC_MKBP_FP_MATCH BIT(28)
+#define EC_MKBP_FP_FINGER_DOWN BIT(29)
+#define EC_MKBP_FP_FINGER_UP BIT(30)
+#define EC_MKBP_FP_IMAGE_READY BIT(31)
 /* code given by EC_MKBP_FP_ERRCODE() when EC_MKBP_FP_ENROLL is set */
-#define EC_MKBP_FP_ERR_ENROLL_OK               0
-#define EC_MKBP_FP_ERR_ENROLL_LOW_QUALITY      1
-#define EC_MKBP_FP_ERR_ENROLL_IMMOBILE         2
-#define EC_MKBP_FP_ERR_ENROLL_LOW_COVERAGE     3
-#define EC_MKBP_FP_ERR_ENROLL_INTERNAL         5
+#define EC_MKBP_FP_ERR_ENROLL_OK 0
+#define EC_MKBP_FP_ERR_ENROLL_LOW_QUALITY 1
+#define EC_MKBP_FP_ERR_ENROLL_IMMOBILE 2
+#define EC_MKBP_FP_ERR_ENROLL_LOW_COVERAGE 3
+#define EC_MKBP_FP_ERR_ENROLL_INTERNAL 5
 /* Can be used to detect if image was usable for enrollment or not. */
-#define EC_MKBP_FP_ERR_ENROLL_PROBLEM_MASK     1
+#define EC_MKBP_FP_ERR_ENROLL_PROBLEM_MASK 1
 /* code given by EC_MKBP_FP_ERRCODE() when EC_MKBP_FP_MATCH is set */
-#define EC_MKBP_FP_ERR_MATCH_NO                0
-#define EC_MKBP_FP_ERR_MATCH_NO_INTERNAL       6
-#define EC_MKBP_FP_ERR_MATCH_NO_TEMPLATES      7
-#define EC_MKBP_FP_ERR_MATCH_NO_LOW_QUALITY    2
-#define EC_MKBP_FP_ERR_MATCH_NO_LOW_COVERAGE   4
-#define EC_MKBP_FP_ERR_MATCH_YES               1
-#define EC_MKBP_FP_ERR_MATCH_YES_UPDATED       3
+#define EC_MKBP_FP_ERR_MATCH_NO 0
+#define EC_MKBP_FP_ERR_MATCH_NO_INTERNAL 6
+#define EC_MKBP_FP_ERR_MATCH_NO_TEMPLATES 7
+#define EC_MKBP_FP_ERR_MATCH_NO_LOW_QUALITY 2
+#define EC_MKBP_FP_ERR_MATCH_NO_LOW_COVERAGE 4
+#define EC_MKBP_FP_ERR_MATCH_YES 1
+#define EC_MKBP_FP_ERR_MATCH_YES_UPDATED 3
 #define EC_MKBP_FP_ERR_MATCH_YES_UPDATE_FAILED 5
 
-
 #define EC_CMD_MKBP_WAKE_MASK 0x0069
 enum ec_mkbp_event_mask_action {
 	/* Retrieve the value of a wake mask. */
@@ -3890,7 +4177,6 @@ struct ec_response_temp_sensor_get_info {
 /*****************************************************************************/
 /* Host event commands */
 
-
 /* Obsolete. New implementation should use EC_CMD_HOST_EVENT instead */
 /*
  * Host event mask params and response structures, shared by all of the host
@@ -3905,17 +4191,17 @@ struct ec_response_host_event_mask {
 } __ec_align4;
 
 /* These all use ec_response_host_event_mask */
-#define EC_CMD_HOST_EVENT_GET_B         0x0087
-#define EC_CMD_HOST_EVENT_GET_SMI_MASK  0x0088
-#define EC_CMD_HOST_EVENT_GET_SCI_MASK  0x0089
+#define EC_CMD_HOST_EVENT_GET_B 0x0087
+#define EC_CMD_HOST_EVENT_GET_SMI_MASK 0x0088
+#define EC_CMD_HOST_EVENT_GET_SCI_MASK 0x0089
 #define EC_CMD_HOST_EVENT_GET_WAKE_MASK 0x008D
 
 /* These all use ec_params_host_event_mask */
-#define EC_CMD_HOST_EVENT_SET_SMI_MASK  0x008A
-#define EC_CMD_HOST_EVENT_SET_SCI_MASK  0x008B
-#define EC_CMD_HOST_EVENT_CLEAR         0x008C
+#define EC_CMD_HOST_EVENT_SET_SMI_MASK 0x008A
+#define EC_CMD_HOST_EVENT_SET_SCI_MASK 0x008B
+#define EC_CMD_HOST_EVENT_CLEAR 0x008C
 #define EC_CMD_HOST_EVENT_SET_WAKE_MASK 0x008E
-#define EC_CMD_HOST_EVENT_CLEAR_B       0x008F
+#define EC_CMD_HOST_EVENT_CLEAR_B 0x008F
 
 /*
  * Unified host event programming interface - Should be used by newer versions
@@ -3927,7 +4213,6 @@ struct ec_response_host_event_mask {
  */
 
 struct ec_params_host_event {
-
 	/* Action requested by host - one of enum ec_host_event_action. */
 	uint8_t action;
 
@@ -3950,7 +4235,6 @@ struct ec_params_host_event {
  */
 
 struct ec_response_host_event {
-
 	/* Mask value in case of get operation */
 	uint64_t value;
 } __ec_align4;
@@ -3999,7 +4283,7 @@ enum ec_host_event_mask_type {
 	EC_HOST_EVENT_LAZY_WAKE_MASK_S5,
 };
 
-#define EC_CMD_HOST_EVENT       0x00A4
+#define EC_CMD_HOST_EVENT 0x00A4
 
 /*****************************************************************************/
 /* Switch commands */
@@ -4145,16 +4429,61 @@ struct ec_params_i2c_write {
  * discharge the battery.
  */
 #define EC_CMD_CHARGE_CONTROL 0x0096
-#define EC_VER_CHARGE_CONTROL 1
+#define EC_VER_CHARGE_CONTROL 3
 
 enum ec_charge_control_mode {
 	CHARGE_CONTROL_NORMAL = 0,
 	CHARGE_CONTROL_IDLE,
 	CHARGE_CONTROL_DISCHARGE,
+	/* Add no more entry below. */
+	CHARGE_CONTROL_COUNT,
+};
+
+#define EC_CHARGE_MODE_TEXT                               \
+	{                                                 \
+		[CHARGE_CONTROL_NORMAL] = "NORMAL",       \
+		[CHARGE_CONTROL_IDLE] = "IDLE",           \
+		[CHARGE_CONTROL_DISCHARGE] = "DISCHARGE", \
+	}
+
+enum ec_charge_control_cmd {
+	EC_CHARGE_CONTROL_CMD_SET = 0,
+	EC_CHARGE_CONTROL_CMD_GET,
+};
+
+enum ec_charge_control_flag {
+	EC_CHARGE_CONTROL_FLAG_NO_IDLE = BIT(0),
 };
 
 struct ec_params_charge_control {
-	uint32_t mode;  /* enum charge_control_mode */
+	uint32_t mode; /* enum charge_control_mode */
+
+	/* Below are the fields added in V2. */
+	uint8_t cmd; /* enum ec_charge_control_cmd. */
+	uint8_t flags; /* enum ec_charge_control_flag (v3+) */
+	/*
+	 * Lower and upper thresholds for battery sustainer. This struct isn't
+	 * named to avoid tainting foreign projects' name spaces.
+	 *
+	 * If charge mode is explicitly set (e.g. DISCHARGE), battery sustainer
+	 * will be disabled. To disable battery sustainer, set mode=NORMAL,
+	 * lower=-1, upper=-1.
+	 */
+	struct {
+		int8_t lower; /* Display SoC in percentage. */
+		int8_t upper; /* Display SoC in percentage. */
+	} sustain_soc;
+} __ec_align4;
+
+/* Added in v2 */
+struct ec_response_charge_control {
+	uint32_t mode; /* enum charge_control_mode */
+	struct { /* Battery sustainer thresholds */
+		int8_t lower;
+		int8_t upper;
+	} sustain_soc;
+	uint8_t flags; /* enum ec_charge_control_flag (v3+) */
+	uint8_t reserved;
 } __ec_align4;
 
 /*****************************************************************************/
@@ -4178,7 +4507,7 @@ struct ec_params_charge_control {
 
 enum ec_console_read_subcmd {
 	CONSOLE_READ_NEXT = 0,
-	CONSOLE_READ_RECENT
+	CONSOLE_READ_RECENT,
 };
 
 struct ec_params_console_read_v1 {
@@ -4196,7 +4525,7 @@ struct ec_params_console_read_v1 {
  */
 #define EC_CMD_BATTERY_CUT_OFF 0x0099
 
-#define EC_BATTERY_CUTOFF_FLAG_AT_SHUTDOWN	BIT(0)
+#define EC_BATTERY_CUTOFF_FLAG_AT_SHUTDOWN BIT(0)
 
 struct ec_params_battery_cutoff {
 	uint8_t flags;
@@ -4218,8 +4547,8 @@ struct ec_params_usb_mux {
 /* LDOs / FETs control. */
 
 enum ec_ldo_state {
-	EC_LDO_STATE_OFF = 0,	/* the LDO / FET is shut down */
-	EC_LDO_STATE_ON = 1,	/* the LDO / FET is ON / providing power */
+	EC_LDO_STATE_OFF = 0, /* the LDO / FET is shut down */
+	EC_LDO_STATE_ON = 1, /* the LDO / FET is ON / providing power */
 };
 
 /*
@@ -4320,33 +4649,33 @@ struct ec_response_power_info_v1 {
 #define EC_CMD_I2C_PASSTHRU 0x009E
 
 /* Read data; if not present, message is a write */
-#define EC_I2C_FLAG_READ	BIT(15)
+#define EC_I2C_FLAG_READ BIT(15)
 
 /* Mask for address */
-#define EC_I2C_ADDR_MASK	0x3ff
+#define EC_I2C_ADDR_MASK 0x3ff
 
-#define EC_I2C_STATUS_NAK	BIT(0) /* Transfer was not acknowledged */
-#define EC_I2C_STATUS_TIMEOUT	BIT(1) /* Timeout during transfer */
+#define EC_I2C_STATUS_NAK BIT(0) /* Transfer was not acknowledged */
+#define EC_I2C_STATUS_TIMEOUT BIT(1) /* Timeout during transfer */
 
 /* Any error */
-#define EC_I2C_STATUS_ERROR	(EC_I2C_STATUS_NAK | EC_I2C_STATUS_TIMEOUT)
+#define EC_I2C_STATUS_ERROR (EC_I2C_STATUS_NAK | EC_I2C_STATUS_TIMEOUT)
 
 struct ec_params_i2c_passthru_msg {
-	uint16_t addr_flags;	/* I2C slave address and flags */
-	uint16_t len;		/* Number of bytes to read or write */
+	uint16_t addr_flags; /* I2C peripheral address and flags */
+	uint16_t len; /* Number of bytes to read or write */
 } __ec_align2;
 
 struct ec_params_i2c_passthru {
-	uint8_t port;		/* I2C port number */
-	uint8_t num_msgs;	/* Number of messages */
+	uint8_t port; /* I2C port number */
+	uint8_t num_msgs; /* Number of messages */
 	struct ec_params_i2c_passthru_msg msg[];
 	/* Data to write for all messages is concatenated here */
 } __ec_align2;
 
 struct ec_response_i2c_passthru {
-	uint8_t i2c_status;	/* Status flags (EC_I2C_STATUS_...) */
-	uint8_t num_msgs;	/* Number of messages processed */
-	uint8_t data[];		/* Data read by messages concatenated here */
+	uint8_t i2c_status; /* Status flags (EC_I2C_STATUS_...) */
+	uint8_t num_msgs; /* Number of messages processed */
+	uint8_t data[]; /* Data read by messages concatenated here */
 } __ec_align1;
 
 /*****************************************************************************/
@@ -4356,16 +4685,16 @@ struct ec_response_i2c_passthru {
 
 /* Reasons to start hang detection timer */
 /* Power button pressed */
-#define EC_HANG_START_ON_POWER_PRESS  BIT(0)
+#define EC_HANG_START_ON_POWER_PRESS BIT(0)
 
 /* Lid closed */
-#define EC_HANG_START_ON_LID_CLOSE    BIT(1)
+#define EC_HANG_START_ON_LID_CLOSE BIT(1)
 
- /* Lid opened */
-#define EC_HANG_START_ON_LID_OPEN     BIT(2)
+/* Lid opened */
+#define EC_HANG_START_ON_LID_OPEN BIT(2)
 
 /* Start of AP S3->S0 transition (booting or resuming from suspend) */
-#define EC_HANG_START_ON_RESUME       BIT(3)
+#define EC_HANG_START_ON_RESUME BIT(3)
 
 /* Reasons to cancel hang detection */
 
@@ -4373,10 +4702,10 @@ struct ec_response_i2c_passthru {
 #define EC_HANG_STOP_ON_POWER_RELEASE BIT(8)
 
 /* Any host command from AP received */
-#define EC_HANG_STOP_ON_HOST_COMMAND  BIT(9)
+#define EC_HANG_STOP_ON_HOST_COMMAND BIT(9)
 
 /* Stop on end of AP S0->S3 transition (suspending or shutting down) */
-#define EC_HANG_STOP_ON_SUSPEND       BIT(10)
+#define EC_HANG_STOP_ON_SUSPEND BIT(10)
 
 /*
  * If this flag is set, all the other fields are ignored, and the hang detect
@@ -4384,14 +4713,14 @@ struct ec_response_i2c_passthru {
  * without reconfiguring any of the other hang detect settings.  Note that
  * you must previously have configured the timeouts.
  */
-#define EC_HANG_START_NOW             BIT(30)
+#define EC_HANG_START_NOW BIT(30)
 
 /*
  * If this flag is set, all the other fields are ignored (including
  * EC_HANG_START_NOW).  This provides the AP a way to stop the hang timer
  * without reconfiguring any of the other hang detect settings.
  */
-#define EC_HANG_STOP_NOW              BIT(31)
+#define EC_HANG_STOP_NOW BIT(31)
 
 struct ec_params_hang_detect {
 	/* Flags; see EC_HANG_* */
@@ -4418,7 +4747,7 @@ enum charge_state_command {
 	CHARGE_STATE_CMD_GET_STATE,
 	CHARGE_STATE_CMD_GET_PARAM,
 	CHARGE_STATE_CMD_SET_PARAM,
-	CHARGE_STATE_NUM_CMDS
+	CHARGE_STATE_NUM_CMDS,
 };
 
 /*
@@ -4426,16 +4755,27 @@ enum charge_state_command {
  * params, which are handled by the particular implementations.
  */
 enum charge_state_params {
-	CS_PARAM_CHG_VOLTAGE,	      /* charger voltage limit */
-	CS_PARAM_CHG_CURRENT,	      /* charger current limit */
-	CS_PARAM_CHG_INPUT_CURRENT,   /* charger input current limit */
-	CS_PARAM_CHG_STATUS,	      /* charger-specific status */
-	CS_PARAM_CHG_OPTION,	      /* charger-specific options */
-	CS_PARAM_LIMIT_POWER,	      /*
-				       * Check if power is limited due to
-				       * low battery and / or a weak external
-				       * charger. READ ONLY.
-				       */
+	/* charger voltage limit */
+	CS_PARAM_CHG_VOLTAGE,
+
+	/* charger current limit */
+	CS_PARAM_CHG_CURRENT,
+
+	/* charger input current limit */
+	CS_PARAM_CHG_INPUT_CURRENT,
+
+	/* charger-specific status */
+	CS_PARAM_CHG_STATUS,
+
+	/* charger-specific options */
+	CS_PARAM_CHG_OPTION,
+
+	/*
+	 * Check if power is limited due to low battery and / or a
+	 * weak external charger. READ ONLY.
+	 */
+	CS_PARAM_LIMIT_POWER,
+
 	/* How many so far? */
 	CS_NUM_BASE_PARAMS,
 
@@ -4458,20 +4798,20 @@ enum charge_state_params {
 };
 
 struct ec_params_charge_state {
-	uint8_t cmd;				/* enum charge_state_command */
+	uint8_t cmd; /* enum charge_state_command */
 	union {
 		/* get_state has no args */
 
 		struct __ec_todo_unpacked {
-			uint32_t param;		/* enum charge_state_param */
+			uint32_t param; /* enum charge_state_param */
 		} get_param;
 
 		struct __ec_todo_unpacked {
-			uint32_t param;		/* param to set */
-			uint32_t value;		/* value to set */
+			uint32_t param; /* param to set */
+			uint32_t value; /* value to set */
 		} set_param;
-	};
-	uint8_t chgnum;				/* Version 1 supports chgnum */
+	} __ec_todo_packed;
+	uint8_t chgnum; /* Version 1 supports chgnum */
 } __ec_todo_packed;
 
 struct ec_response_charge_state {
@@ -4492,16 +4832,26 @@ struct ec_response_charge_state {
 	};
 } __ec_align4;
 
-
 /*
  * Set maximum battery charging current.
  */
 #define EC_CMD_CHARGE_CURRENT_LIMIT 0x00A1
+#define EC_VER_CHARGE_CURRENT_LIMIT 1
 
 struct ec_params_current_limit {
 	uint32_t limit; /* in mA */
 } __ec_align4;
 
+struct ec_params_current_limit_v1 {
+	uint32_t limit; /* in mA */
+	/*
+	 * Battery state of charge is the minimum charge percentage at which
+	 * the battery charge current limit will apply.
+	 * When not set, the limit will apply regardless of state of charge.
+	 */
+	uint8_t battery_soc; /* battery state of charge, 0-100 */
+} __ec_align4;
+
 /*
  * Set maximum external voltage / current.
  */
@@ -4525,6 +4875,39 @@ struct ec_params_dedicated_charger_limit {
 	uint16_t voltage_lim; /* in mV */
 } __ec_align2;
 
+/*
+ * Get and set charging splashscreen variables
+ */
+#define EC_CMD_CHARGESPLASH 0x00A5
+
+enum ec_chargesplash_cmd {
+	/* Get the current state variables */
+	EC_CHARGESPLASH_GET_STATE = 0,
+
+	/* Indicate initialization of the display loop */
+	EC_CHARGESPLASH_DISPLAY_READY,
+
+	/* Manually put the EC into the requested state */
+	EC_CHARGESPLASH_REQUEST,
+
+	/* Reset all state variables */
+	EC_CHARGESPLASH_RESET,
+
+	/* Manually trigger a lockout */
+	EC_CHARGESPLASH_LOCKOUT,
+};
+
+struct __ec_align1 ec_params_chargesplash {
+	/* enum ec_chargesplash_cmd */
+	uint8_t cmd;
+};
+
+struct __ec_align1 ec_response_chargesplash {
+	uint8_t requested;
+	uint8_t display_initialized;
+	uint8_t locked_out;
+};
+
 /*****************************************************************************/
 /* Hibernate/Deep Sleep Commands */
 
@@ -4563,10 +4946,10 @@ struct ec_response_hibernation_delay {
 #define EC_CMD_HOST_SLEEP_EVENT 0x00A9
 
 enum host_sleep_event {
-	HOST_SLEEP_EVENT_S3_SUSPEND   = 1,
-	HOST_SLEEP_EVENT_S3_RESUME    = 2,
+	HOST_SLEEP_EVENT_S3_SUSPEND = 1,
+	HOST_SLEEP_EVENT_S3_RESUME = 2,
 	HOST_SLEEP_EVENT_S0IX_SUSPEND = 3,
-	HOST_SLEEP_EVENT_S0IX_RESUME  = 4,
+	HOST_SLEEP_EVENT_S0IX_RESUME = 4,
 	/* S3 suspend with additional enabled wake sources */
 	HOST_SLEEP_EVENT_S3_WAKEABLE_SUSPEND = 5,
 };
@@ -4640,6 +5023,7 @@ enum ec_device_event {
 	EC_DEVICE_EVENT_TRACKPAD,
 	EC_DEVICE_EVENT_DSP,
 	EC_DEVICE_EVENT_WIFI,
+	EC_DEVICE_EVENT_WLC,
 };
 
 enum ec_device_event_param {
@@ -4663,39 +5047,34 @@ struct ec_response_device_event {
 } __ec_align4;
 
 /*****************************************************************************/
-/* Smart battery pass-through */
-
-/* Get / Set 16-bit smart battery registers */
-#define EC_CMD_SB_READ_WORD   0x00B0
-#define EC_CMD_SB_WRITE_WORD  0x00B1
+/* Get s0ix counter */
+#define EC_CMD_GET_S0IX_COUNTER 0x00AB
 
-/* Get / Set string smart battery parameters
- * formatted as SMBUS "block".
- */
-#define EC_CMD_SB_READ_BLOCK  0x00B2
-#define EC_CMD_SB_WRITE_BLOCK 0x00B3
+/* Flag use to reset the counter */
+#define EC_S0IX_COUNTER_RESET 0x1
 
-struct ec_params_sb_rd {
-	uint8_t reg;
-} __ec_align1;
+struct ec_params_s0ix_cnt {
+	/* If EC_S0IX_COUNTER_RESET then reset otherwise get the counter */
+	uint32_t flags;
+} __ec_align4;
 
-struct ec_response_sb_rd_word {
-	uint16_t value;
-} __ec_align2;
+struct ec_response_s0ix_cnt {
+	/* Value of the s0ix_counter */
+	uint32_t s0ix_counter;
+} __ec_align4;
 
-struct ec_params_sb_wr_word {
-	uint8_t reg;
-	uint16_t value;
-} __ec_align1;
+/*****************************************************************************/
+/* Smart battery pass-through */
 
-struct ec_response_sb_rd_block {
-	uint8_t data[32];
-} __ec_align1;
+/* Get / Set 16-bit smart battery registers  - OBSOLETE */
+#define EC_CMD_SB_READ_WORD 0x00B0
+#define EC_CMD_SB_WRITE_WORD 0x00B1
 
-struct ec_params_sb_wr_block {
-	uint8_t reg;
-	uint16_t data[32];
-} __ec_align1;
+/* Get / Set string smart battery parameters
+ * formatted as SMBUS "block". - OBSOLETE
+ */
+#define EC_CMD_SB_READ_BLOCK 0x00B2
+#define EC_CMD_SB_WRITE_BLOCK 0x00B3
 
 /*****************************************************************************/
 /* Battery vendor parameters
@@ -4725,62 +5104,10 @@ struct ec_response_battery_vendor_param {
 
 /*****************************************************************************/
 /*
- * Smart Battery Firmware Update Commands
+ * Smart Battery Firmware Update Command - OBSOLETE
  */
 #define EC_CMD_SB_FW_UPDATE 0x00B5
 
-enum ec_sb_fw_update_subcmd {
-	EC_SB_FW_UPDATE_PREPARE  = 0x0,
-	EC_SB_FW_UPDATE_INFO     = 0x1, /*query sb info */
-	EC_SB_FW_UPDATE_BEGIN    = 0x2, /*check if protected */
-	EC_SB_FW_UPDATE_WRITE    = 0x3, /*check if protected */
-	EC_SB_FW_UPDATE_END      = 0x4,
-	EC_SB_FW_UPDATE_STATUS   = 0x5,
-	EC_SB_FW_UPDATE_PROTECT  = 0x6,
-	EC_SB_FW_UPDATE_MAX      = 0x7,
-};
-
-#define SB_FW_UPDATE_CMD_WRITE_BLOCK_SIZE 32
-#define SB_FW_UPDATE_CMD_STATUS_SIZE 2
-#define SB_FW_UPDATE_CMD_INFO_SIZE 8
-
-struct ec_sb_fw_update_header {
-	uint16_t subcmd;  /* enum ec_sb_fw_update_subcmd */
-	uint16_t fw_id;   /* firmware id */
-} __ec_align4;
-
-struct ec_params_sb_fw_update {
-	struct ec_sb_fw_update_header hdr;
-	union {
-		/* EC_SB_FW_UPDATE_PREPARE  = 0x0 */
-		/* EC_SB_FW_UPDATE_INFO     = 0x1 */
-		/* EC_SB_FW_UPDATE_BEGIN    = 0x2 */
-		/* EC_SB_FW_UPDATE_END      = 0x4 */
-		/* EC_SB_FW_UPDATE_STATUS   = 0x5 */
-		/* EC_SB_FW_UPDATE_PROTECT  = 0x6 */
-		/* Those have no args */
-
-		/* EC_SB_FW_UPDATE_WRITE    = 0x3 */
-		struct __ec_align4 {
-			uint8_t  data[SB_FW_UPDATE_CMD_WRITE_BLOCK_SIZE];
-		} write;
-	};
-} __ec_align4;
-
-struct ec_response_sb_fw_update {
-	union {
-		/* EC_SB_FW_UPDATE_INFO     = 0x1 */
-		struct __ec_align1 {
-			uint8_t data[SB_FW_UPDATE_CMD_INFO_SIZE];
-		} info;
-
-		/* EC_SB_FW_UPDATE_STATUS   = 0x5 */
-		struct __ec_align1 {
-			uint8_t data[SB_FW_UPDATE_CMD_STATUS_SIZE];
-		} status;
-	};
-} __ec_align1;
-
 /*
  * Entering Verified Boot Mode Command
  * Default mode is VBOOT_MODE_NORMAL if EC did not receive this command.
@@ -4795,9 +5122,9 @@ struct ec_params_entering_mode {
 	int vboot_mode;
 } __ec_align4;
 
-#define VBOOT_MODE_NORMAL    0
+#define VBOOT_MODE_NORMAL 0
 #define VBOOT_MODE_DEVELOPER 1
-#define VBOOT_MODE_RECOVERY  2
+#define VBOOT_MODE_RECOVERY 2
 
 /*****************************************************************************/
 /*
@@ -4814,14 +5141,13 @@ enum ec_i2c_passthru_protect_subcmd {
 
 struct ec_params_i2c_passthru_protect {
 	uint8_t subcmd;
-	uint8_t port;		/* I2C port number */
+	uint8_t port; /* I2C port number */
 } __ec_align1;
 
 struct ec_response_i2c_passthru_protect {
-	uint8_t status;		/* Status flags (0: unlocked, 1: locked) */
+	uint8_t status; /* Status flags (0: unlocked, 1: locked) */
 } __ec_align1;
 
-
 /*****************************************************************************/
 /*
  * HDMI CEC commands
@@ -4891,9 +5217,9 @@ enum cec_command {
 /* Events from CEC to AP */
 enum mkbp_cec_event {
 	/* Outgoing message was acknowledged by a follower */
-	EC_MKBP_CEC_SEND_OK			= BIT(0),
+	EC_MKBP_CEC_SEND_OK = BIT(0),
 	/* Outgoing message was not acknowledged */
-	EC_MKBP_CEC_SEND_FAILED			= BIT(1),
+	EC_MKBP_CEC_SEND_FAILED = BIT(1),
 };
 
 /*****************************************************************************/
@@ -4942,10 +5268,8 @@ struct __ec_align4 ec_param_ec_codec {
 	uint8_t reserved[3];
 
 	union {
-		struct ec_param_ec_codec_get_shm_addr
-				get_shm_addr_param;
-		struct ec_param_ec_codec_set_shm_addr
-				set_shm_addr_param;
+		struct ec_param_ec_codec_get_shm_addr get_shm_addr_param;
+		struct ec_param_ec_codec_set_shm_addr set_shm_addr_param;
 	};
 };
 
@@ -5000,10 +5324,8 @@ struct __ec_align4 ec_param_ec_codec_dmic {
 	uint8_t reserved[3];
 
 	union {
-		struct ec_param_ec_codec_dmic_set_gain_idx
-				set_gain_idx_param;
-		struct ec_param_ec_codec_dmic_get_gain_idx
-				get_gain_idx_param;
+		struct ec_param_ec_codec_dmic_set_gain_idx set_gain_idx_param;
+		struct ec_param_ec_codec_dmic_get_gain_idx get_gain_idx_param;
 	};
 };
 
@@ -5070,11 +5392,9 @@ struct __ec_align4 ec_param_ec_codec_i2s_rx {
 
 	union {
 		struct ec_param_ec_codec_i2s_rx_set_sample_depth
-				set_sample_depth_param;
-		struct ec_param_ec_codec_i2s_rx_set_daifmt
-				set_daifmt_param;
-		struct ec_param_ec_codec_i2s_rx_set_bclk
-				set_bclk_param;
+			set_sample_depth_param;
+		struct ec_param_ec_codec_i2s_rx_set_daifmt set_daifmt_param;
+		struct ec_param_ec_codec_i2s_rx_set_bclk set_bclk_param;
 	};
 };
 
@@ -5119,10 +5439,8 @@ struct __ec_align4 ec_param_ec_codec_wov {
 	uint8_t reserved[3];
 
 	union {
-		struct ec_param_ec_codec_wov_set_lang
-				set_lang_param;
-		struct ec_param_ec_codec_wov_set_lang_shm
-				set_lang_shm_param;
+		struct ec_param_ec_codec_wov_set_lang set_lang_param;
+		struct ec_param_ec_codec_wov_set_lang_shm set_lang_shm_param;
 	};
 };
 
@@ -5153,8 +5471,8 @@ enum ec_pse_subcmd {
 };
 
 struct __ec_align1 ec_params_pse {
-	uint8_t cmd;	/* enum ec_pse_subcmd */
-	uint8_t port;	/* PSE port */
+	uint8_t cmd; /* enum ec_pse_subcmd */
+	uint8_t port; /* PSE port */
 };
 
 enum ec_pse_status {
@@ -5164,7 +5482,7 @@ enum ec_pse_status {
 };
 
 struct __ec_align1 ec_response_pse_status {
-	uint8_t status;	/* enum ec_pse_status */
+	uint8_t status; /* enum ec_pse_status */
 };
 
 /*****************************************************************************/
@@ -5178,24 +5496,31 @@ struct __ec_align1 ec_response_pse_status {
 
 /* Command */
 enum ec_reboot_cmd {
-	EC_REBOOT_CANCEL = 0,        /* Cancel a pending reboot */
-	EC_REBOOT_JUMP_RO = 1,       /* Jump to RO without rebooting */
-	EC_REBOOT_JUMP_RW = 2,       /* Jump to active RW without rebooting */
+	EC_REBOOT_CANCEL = 0, /* Cancel a pending reboot */
+	EC_REBOOT_JUMP_RO = 1, /* Jump to RO without rebooting */
+	EC_REBOOT_JUMP_RW = 2, /* Jump to active RW without rebooting */
 	/* (command 3 was jump to RW-B) */
-	EC_REBOOT_COLD = 4,          /* Cold-reboot */
-	EC_REBOOT_DISABLE_JUMP = 5,  /* Disable jump until next reboot */
-	EC_REBOOT_HIBERNATE = 6,     /* Hibernate EC */
-	EC_REBOOT_HIBERNATE_CLEAR_AP_OFF = 7, /* and clears AP_IDLE flag */
+	EC_REBOOT_COLD = 4, /* Cold-reboot */
+	EC_REBOOT_DISABLE_JUMP = 5, /* Disable jump until next reboot */
+	EC_REBOOT_HIBERNATE = 6, /* Hibernate EC */
+	/*
+	 * DEPRECATED: Hibernate EC and clears AP_IDLE flag.
+	 * Use EC_REBOOT_HIBERNATE and EC_REBOOT_FLAG_CLEAR_AP_IDLE, instead.
+	 */
+	EC_REBOOT_HIBERNATE_CLEAR_AP_OFF = 7,
+	EC_REBOOT_COLD_AP_OFF = 8, /* Cold-reboot and don't boot AP */
+	EC_REBOOT_NO_OP = 9, /* Do nothing but apply the flags. */
 };
 
 /* Flags for ec_params_reboot_ec.reboot_flags */
-#define EC_REBOOT_FLAG_RESERVED0      BIT(0)  /* Was recovery request */
-#define EC_REBOOT_FLAG_ON_AP_SHUTDOWN BIT(1)  /* Reboot after AP shutdown */
-#define EC_REBOOT_FLAG_SWITCH_RW_SLOT BIT(2)  /* Switch RW slot */
+#define EC_REBOOT_FLAG_RESERVED0 BIT(0) /* Was recovery request */
+#define EC_REBOOT_FLAG_ON_AP_SHUTDOWN BIT(1) /* Reboot after AP shutdown */
+#define EC_REBOOT_FLAG_SWITCH_RW_SLOT BIT(2) /* Switch RW slot */
+#define EC_REBOOT_FLAG_CLEAR_AP_IDLE BIT(3) /* Clear AP_IDLE flag */
 
 struct ec_params_reboot_ec {
-	uint8_t cmd;           /* enum ec_reboot_cmd */
-	uint8_t flags;         /* See EC_REBOOT_FLAG_* */
+	uint8_t cmd; /* enum ec_reboot_cmd */
+	uint8_t flags; /* See EC_REBOOT_FLAG_* */
 } __ec_align1;
 
 /*
@@ -5223,7 +5548,7 @@ struct ec_params_reboot_ec {
  *
  * Use EC_CMD_REBOOT_EC to reboot the EC more politely.
  */
-#define EC_CMD_REBOOT 0x00D1  /* Think "die" */
+#define EC_CMD_REBOOT 0x00D1 /* Think "die" */
 
 /*
  * Resend last response (not supported on LPC).
@@ -5246,6 +5571,54 @@ struct ec_params_reboot_ec {
  */
 #define EC_CMD_VERSION0 0x00DC
 
+/*
+ * Memory Dump Commands
+ *
+ * Since the HOSTCMD response size is limited, depending on the
+ * protocol, retrieving a memory dump is split into 3 commands.
+ *
+ * 1. EC_CMD_MEMORY_DUMP_GET_METADATA returns the number of memory dump entries,
+ *    and the total dump size.
+ * 2. EC_CMD_MEMORY_DUMP_GET_ENTRY_INFO returns the address and size for a given
+ *    memory dump entry index.
+ * 3. EC_CMD_MEMORY_DUMP_READ_MEMORY returns the actual memory at a given
+ *    address. The address and size must be within the bounds of the given
+ *    memory dump entry index. Each response is limited to the max response size
+ *    of the host protocol, so this may need to be called repeatedly to retrieve
+ *    the entire memory dump entry.
+ *
+ * Memory entries may overlap and may be out of order.
+ * The host should check for overlaps to optimize transfer rate.
+ */
+#define EC_CMD_MEMORY_DUMP_GET_METADATA 0x00DD
+struct ec_response_memory_dump_get_metadata {
+	uint16_t memory_dump_entry_count;
+	uint32_t memory_dump_total_size;
+} __ec_align4;
+
+#define EC_CMD_MEMORY_DUMP_GET_ENTRY_INFO 0x00DE
+struct ec_params_memory_dump_get_entry_info {
+	uint16_t memory_dump_entry_index;
+} __ec_align4;
+
+struct ec_response_memory_dump_get_entry_info {
+	uint32_t address;
+	uint32_t size;
+} __ec_align4;
+
+#define EC_CMD_MEMORY_DUMP_READ_MEMORY 0x00DF
+
+struct ec_params_memory_dump_read_memory {
+	uint16_t memory_dump_entry_index;
+	uint32_t address;
+	uint32_t size;
+} __ec_align4;
+
+/*
+ * EC_CMD_MEMORY_DUMP_READ_MEMORY response buffer is written directly into
+ * host_cmd_handler_args.response and host_cmd_handler_args.response_size.
+ */
+
 /*****************************************************************************/
 /*
  * PD commands
@@ -5258,50 +5631,66 @@ struct ec_params_reboot_ec {
 #define EC_VER_PD_EXCHANGE_STATUS 2
 
 enum pd_charge_state {
-	PD_CHARGE_NO_CHANGE = 0, /* Don't change charge state */
-	PD_CHARGE_NONE,          /* No charging allowed */
-	PD_CHARGE_5V,            /* 5V charging only */
-	PD_CHARGE_MAX            /* Charge at max voltage */
+	/* Don't change charge state */
+	PD_CHARGE_NO_CHANGE = 0,
+
+	/* No charging allowed */
+	PD_CHARGE_NONE,
+
+	/* 5V charging only */
+	PD_CHARGE_5V,
+
+	/* Charge at max voltage */
+	PD_CHARGE_MAX,
 };
 
 /* Status of EC being sent to PD */
-#define EC_STATUS_HIBERNATING	BIT(0)
+#define EC_STATUS_HIBERNATING BIT(0)
 
 struct ec_params_pd_status {
-	uint8_t status;       /* EC status */
-	int8_t batt_soc;      /* battery state of charge */
-	uint8_t charge_state; /* charging state (from enum pd_charge_state) */
+	/* EC status */
+	uint8_t status;
+
+	/* battery state of charge */
+	int8_t batt_soc;
+
+	/* charging state (from enum pd_charge_state) */
+	uint8_t charge_state;
 } __ec_align1;
 
 /* Status of PD being sent back to EC */
-#define PD_STATUS_HOST_EVENT      BIT(0) /* Forward host event to AP */
-#define PD_STATUS_IN_RW           BIT(1) /* Running RW image */
+#define PD_STATUS_HOST_EVENT BIT(0) /* Forward host event to AP */
+#define PD_STATUS_IN_RW BIT(1) /* Running RW image */
 #define PD_STATUS_JUMPED_TO_IMAGE BIT(2) /* Current image was jumped to */
-#define PD_STATUS_TCPC_ALERT_0    BIT(3) /* Alert active in port 0 TCPC */
-#define PD_STATUS_TCPC_ALERT_1    BIT(4) /* Alert active in port 1 TCPC */
-#define PD_STATUS_TCPC_ALERT_2    BIT(5) /* Alert active in port 2 TCPC */
-#define PD_STATUS_TCPC_ALERT_3    BIT(6) /* Alert active in port 3 TCPC */
-#define PD_STATUS_EC_INT_ACTIVE  (PD_STATUS_TCPC_ALERT_0 | \
-				      PD_STATUS_TCPC_ALERT_1 | \
-				      PD_STATUS_HOST_EVENT)
+#define PD_STATUS_TCPC_ALERT_0 BIT(3) /* Alert active in port 0 TCPC */
+#define PD_STATUS_TCPC_ALERT_1 BIT(4) /* Alert active in port 1 TCPC */
+#define PD_STATUS_TCPC_ALERT_2 BIT(5) /* Alert active in port 2 TCPC */
+#define PD_STATUS_TCPC_ALERT_3 BIT(6) /* Alert active in port 3 TCPC */
+#define PD_STATUS_EC_INT_ACTIVE \
+	(PD_STATUS_TCPC_ALERT_0 | PD_STATUS_TCPC_ALERT_1 | PD_STATUS_HOST_EVENT)
 struct ec_response_pd_status {
-	uint32_t curr_lim_ma;       /* input current limit */
-	uint16_t status;            /* PD MCU status */
-	int8_t active_charge_port;  /* active charging port */
+	/* input current limit */
+	uint32_t curr_lim_ma;
+
+	/* PD MCU status */
+	uint16_t status;
+
+	/* active charging port */
+	int8_t active_charge_port;
 } __ec_align_size1;
 
 /* AP to PD MCU host event status command, cleared on read */
 #define EC_CMD_PD_HOST_EVENT_STATUS 0x0104
 
 /* PD MCU host event status bits */
-#define PD_EVENT_UPDATE_DEVICE		BIT(0)
-#define PD_EVENT_POWER_CHANGE		BIT(1)
-#define PD_EVENT_IDENTITY_RECEIVED	BIT(2)
-#define PD_EVENT_DATA_SWAP		BIT(3)
-#define PD_EVENT_TYPEC			BIT(4)
+#define PD_EVENT_UPDATE_DEVICE BIT(0)
+#define PD_EVENT_POWER_CHANGE BIT(1)
+#define PD_EVENT_IDENTITY_RECEIVED BIT(2)
+#define PD_EVENT_DATA_SWAP BIT(3)
+#define PD_EVENT_TYPEC BIT(4)
 
 struct ec_response_host_event_status {
-	uint32_t status;      /* PD MCU host event status */
+	uint32_t status; /* PD MCU host event status */
 } __ec_align4;
 
 /*
@@ -5320,7 +5709,7 @@ enum usb_pd_control_role {
 	USB_PD_CTRL_ROLE_FORCE_SINK = 3,
 	USB_PD_CTRL_ROLE_FORCE_SOURCE = 4,
 	USB_PD_CTRL_ROLE_FREEZE = 5,
-	USB_PD_CTRL_ROLE_COUNT
+	USB_PD_CTRL_ROLE_COUNT,
 };
 
 enum usb_pd_control_mux {
@@ -5330,7 +5719,7 @@ enum usb_pd_control_mux {
 	USB_PD_CTRL_MUX_DP = 3,
 	USB_PD_CTRL_MUX_DOCK = 4,
 	USB_PD_CTRL_MUX_AUTO = 5,
-	USB_PD_CTRL_MUX_COUNT
+	USB_PD_CTRL_MUX_COUNT,
 };
 
 enum usb_pd_control_swap {
@@ -5338,7 +5727,7 @@ enum usb_pd_control_swap {
 	USB_PD_CTRL_SWAP_DATA = 1,
 	USB_PD_CTRL_SWAP_POWER = 2,
 	USB_PD_CTRL_SWAP_VCONN = 3,
-	USB_PD_CTRL_SWAP_COUNT
+	USB_PD_CTRL_SWAP_COUNT,
 };
 
 struct ec_params_usb_pd_control {
@@ -5348,17 +5737,18 @@ struct ec_params_usb_pd_control {
 	uint8_t swap;
 } __ec_align1;
 
-#define PD_CTRL_RESP_ENABLED_COMMS      BIT(0) /* Communication enabled */
-#define PD_CTRL_RESP_ENABLED_CONNECTED  BIT(1) /* Device connected */
+#define PD_CTRL_RESP_ENABLED_COMMS BIT(0) /* Communication enabled */
+#define PD_CTRL_RESP_ENABLED_CONNECTED BIT(1) /* Device connected */
 #define PD_CTRL_RESP_ENABLED_PD_CAPABLE BIT(2) /* Partner is PD capable */
 
-#define PD_CTRL_RESP_ROLE_POWER         BIT(0) /* 0=SNK/1=SRC */
-#define PD_CTRL_RESP_ROLE_DATA          BIT(1) /* 0=UFP/1=DFP */
-#define PD_CTRL_RESP_ROLE_VCONN         BIT(2) /* Vconn status */
-#define PD_CTRL_RESP_ROLE_DR_POWER      BIT(3) /* Partner is dualrole power */
-#define PD_CTRL_RESP_ROLE_DR_DATA       BIT(4) /* Partner is dualrole data */
-#define PD_CTRL_RESP_ROLE_USB_COMM      BIT(5) /* Partner USB comm capable */
-#define PD_CTRL_RESP_ROLE_UNCONSTRAINED BIT(6) /* Partner unconstrained power */
+#define PD_CTRL_RESP_ROLE_POWER BIT(0) /* 0=SNK/1=SRC */
+#define PD_CTRL_RESP_ROLE_DATA BIT(1) /* 0=UFP/1=DFP */
+#define PD_CTRL_RESP_ROLE_VCONN BIT(2) /* Vconn status */
+#define PD_CTRL_RESP_ROLE_DR_POWER BIT(3) /* Partner is dualrole power */
+#define PD_CTRL_RESP_ROLE_DR_DATA BIT(4) /* Partner is dualrole data */
+#define PD_CTRL_RESP_ROLE_USB_COMM BIT(5) /* Partner USB comm capable */
+/* Partner unconstrained power */
+#define PD_CTRL_RESP_ROLE_UNCONSTRAINED BIT(6)
 
 struct ec_response_usb_pd_control {
 	uint8_t enabled;
@@ -5376,44 +5766,41 @@ struct ec_response_usb_pd_control_v1 {
 
 /* Possible port partner connections based on CC line states */
 enum pd_cc_states {
-	PD_CC_NONE = 0,			/* No port partner attached */
+	PD_CC_NONE = 0, /* No port partner attached */
 
 	/* From DFP perspective */
-	PD_CC_UFP_NONE = 1,		/* No UFP accessory connected */
-	PD_CC_UFP_AUDIO_ACC = 2,	/* UFP Audio accessory connected */
-	PD_CC_UFP_DEBUG_ACC = 3,	/* UFP Debug accessory connected */
-	PD_CC_UFP_ATTACHED = 4,		/* Plain UFP attached */
+	PD_CC_UFP_NONE = 1, /* No UFP accessory connected */
+	PD_CC_UFP_AUDIO_ACC = 2, /* UFP Audio accessory connected */
+	PD_CC_UFP_DEBUG_ACC = 3, /* UFP Debug accessory connected */
+	PD_CC_UFP_ATTACHED = 4, /* Plain UFP attached */
 
 	/* From UFP perspective */
-	PD_CC_DFP_ATTACHED = 5,		/* Plain DFP attached */
-	PD_CC_DFP_DEBUG_ACC = 6,	/* DFP debug accessory connected */
+	PD_CC_DFP_ATTACHED = 5, /* Plain DFP attached */
+	PD_CC_DFP_DEBUG_ACC = 6, /* DFP debug accessory connected */
 };
 
 /* Active/Passive Cable */
-#define USB_PD_CTRL_ACTIVE_CABLE        BIT(0)
+#define USB_PD_CTRL_ACTIVE_CABLE BIT(0)
 /* Optical/Non-optical cable */
-#define USB_PD_CTRL_OPTICAL_CABLE       BIT(1)
+#define USB_PD_CTRL_OPTICAL_CABLE BIT(1)
 /* 3rd Gen TBT device (or AMA)/2nd gen tbt Adapter */
-#define USB_PD_CTRL_TBT_LEGACY_ADAPTER  BIT(2)
+#define USB_PD_CTRL_TBT_LEGACY_ADAPTER BIT(2)
 /* Active Link Uni-Direction */
-#define USB_PD_CTRL_ACTIVE_LINK_UNIDIR  BIT(3)
+#define USB_PD_CTRL_ACTIVE_LINK_UNIDIR BIT(3)
+/* Retimer/Redriver cable */
+#define USB_PD_CTRL_RETIMER_CABLE BIT(4)
 
-/*
- * Underdevelopement :
- * Please remove this tag if using _v2 outside platform/ec
- */
 struct ec_response_usb_pd_control_v2 {
 	uint8_t enabled;
 	uint8_t role;
 	uint8_t polarity;
 	char state[32];
-	uint8_t cc_state;	/* enum pd_cc_states representing cc state */
-	uint8_t dp_mode;	/* Current DP pin mode (MODE_DP_PIN_[A-E]) */
-	uint8_t reserved;	/* Reserved for future use */
-	uint8_t control_flags;	/* USB_PD_CTRL_*flags */
-	/* TODO: b:158234949 Add definitions for cable speed */
-	uint8_t cable_speed;	/* USB_R30_SS/TBT_SS_* cable speed */
-	uint8_t cable_gen;	/* TBT_GEN3_* cable rounded support */
+	uint8_t cc_state; /* enum pd_cc_states representing cc state */
+	uint8_t dp_mode; /* Current DP pin mode (MODE_DP_PIN_[A-E]) */
+	uint8_t reserved; /* Reserved for future use */
+	uint8_t control_flags; /* USB_PD_CTRL_*flags */
+	uint8_t cable_speed; /* TBT_SS_* cable speed */
+	uint8_t cable_gen; /* TBT_GEN3_* cable rounded support */
 } __ec_align1;
 
 #define EC_CMD_USB_PD_PORTS 0x0102
@@ -5468,7 +5855,6 @@ struct ec_response_usb_pd_power_info {
 	uint32_t max_power;
 } __ec_align4;
 
-
 /*
  * This command will return the number of USB PD charge port + the number
  * of dedicated port present.
@@ -5479,6 +5865,15 @@ struct ec_response_charge_port_count {
 	uint8_t port_count;
 } __ec_align1;
 
+/*
+ * This command enable/disable dynamic PDO selection.
+ */
+#define EC_CMD_USB_PD_DPS_CONTROL 0x0106
+
+struct ec_params_usb_pd_dps_control {
+	uint8_t enable;
+} __ec_align1;
+
 /* Write USB-PD device FW */
 #define EC_CMD_USB_PD_FW_UPDATE 0x0110
 
@@ -5493,7 +5888,10 @@ struct ec_params_usb_pd_fw_update {
 	uint16_t dev_id;
 	uint8_t cmd;
 	uint8_t port;
-	uint32_t size;     /* Size to write in bytes */
+
+	/* Size to write in bytes */
+	uint32_t size;
+
 	/* Followed by data to write */
 } __ec_align4;
 
@@ -5504,12 +5902,16 @@ struct ec_params_usb_pd_fw_update {
 struct ec_params_usb_pd_rw_hash_entry {
 	uint16_t dev_id;
 	uint8_t dev_rw_hash[PD_RW_HASH_SIZE];
-	uint8_t reserved;        /*
-				  * For alignment of current_image
-				  * TODO(rspangler) but it's not aligned!
-				  * Should have been reserved[2].
-				  */
-	uint32_t current_image;  /* One of ec_image */
+
+	/*
+	 * Reserved for alignment of current_image
+	 * TODO(rspangler) but it's not aligned!
+	 * Should have been reserved[2].
+	 */
+	uint8_t reserved;
+
+	/* One of ec_image */
+	uint32_t current_image;
 } __ec_align1;
 
 /* Read USB-PD Accessory info */
@@ -5522,8 +5924,8 @@ struct ec_params_usb_pd_info_request {
 /* Read USB-PD Device discovery info */
 #define EC_CMD_USB_PD_DISCOVERY 0x0113
 struct ec_params_usb_pd_discovery_entry {
-	uint16_t vid;  /* USB-IF VID */
-	uint16_t pid;  /* USB-IF PID */
+	uint16_t vid; /* USB-IF VID */
+	uint16_t pid; /* USB-IF PID */
 	uint8_t ptype; /* product type (hub,periph,cable,ama) */
 } __ec_align_size1;
 
@@ -5550,43 +5952,43 @@ struct ec_params_charge_port_override {
 
 struct ec_response_pd_log {
 	uint32_t timestamp; /* relative timestamp in milliseconds */
-	uint8_t type;       /* event type : see PD_EVENT_xx below */
-	uint8_t size_port;  /* [7:5] port number [4:0] payload size in bytes */
-	uint16_t data;      /* type-defined data payload */
+	uint8_t type; /* event type : see PD_EVENT_xx below */
+	uint8_t size_port; /* [7:5] port number [4:0] payload size in bytes */
+	uint16_t data; /* type-defined data payload */
 	uint8_t payload[0]; /* optional additional data payload: 0..16 bytes */
 } __ec_align4;
 
 /* The timestamp is the microsecond counter shifted to get about a ms. */
 #define PD_LOG_TIMESTAMP_SHIFT 10 /* 1 LSB = 1024us */
 
-#define PD_LOG_SIZE_MASK  0x1f
-#define PD_LOG_PORT_MASK  0xe0
-#define PD_LOG_PORT_SHIFT    5
-#define PD_LOG_PORT_SIZE(port, size) (((port) << PD_LOG_PORT_SHIFT) | \
-				      ((size) & PD_LOG_SIZE_MASK))
+#define PD_LOG_SIZE_MASK 0x1f
+#define PD_LOG_PORT_MASK 0xe0
+#define PD_LOG_PORT_SHIFT 5
+#define PD_LOG_PORT_SIZE(port, size) \
+	(((port) << PD_LOG_PORT_SHIFT) | ((size)&PD_LOG_SIZE_MASK))
 #define PD_LOG_PORT(size_port) ((size_port) >> PD_LOG_PORT_SHIFT)
-#define PD_LOG_SIZE(size_port) ((size_port) & PD_LOG_SIZE_MASK)
+#define PD_LOG_SIZE(size_port) ((size_port)&PD_LOG_SIZE_MASK)
 
 /* PD event log : entry types */
 /* PD MCU events */
-#define PD_EVENT_MCU_BASE       0x00
-#define PD_EVENT_MCU_CHARGE             (PD_EVENT_MCU_BASE+0)
-#define PD_EVENT_MCU_CONNECT            (PD_EVENT_MCU_BASE+1)
+#define PD_EVENT_MCU_BASE 0x00
+#define PD_EVENT_MCU_CHARGE (PD_EVENT_MCU_BASE + 0)
+#define PD_EVENT_MCU_CONNECT (PD_EVENT_MCU_BASE + 1)
 /* Reserved for custom board event */
-#define PD_EVENT_MCU_BOARD_CUSTOM       (PD_EVENT_MCU_BASE+2)
+#define PD_EVENT_MCU_BOARD_CUSTOM (PD_EVENT_MCU_BASE + 2)
 /* PD generic accessory events */
-#define PD_EVENT_ACC_BASE       0x20
-#define PD_EVENT_ACC_RW_FAIL   (PD_EVENT_ACC_BASE+0)
-#define PD_EVENT_ACC_RW_ERASE  (PD_EVENT_ACC_BASE+1)
+#define PD_EVENT_ACC_BASE 0x20
+#define PD_EVENT_ACC_RW_FAIL (PD_EVENT_ACC_BASE + 0)
+#define PD_EVENT_ACC_RW_ERASE (PD_EVENT_ACC_BASE + 1)
 /* PD power supply events */
-#define PD_EVENT_PS_BASE        0x40
-#define PD_EVENT_PS_FAULT      (PD_EVENT_PS_BASE+0)
+#define PD_EVENT_PS_BASE 0x40
+#define PD_EVENT_PS_FAULT (PD_EVENT_PS_BASE + 0)
 /* PD video dongles events */
-#define PD_EVENT_VIDEO_BASE     0x60
-#define PD_EVENT_VIDEO_DP_MODE (PD_EVENT_VIDEO_BASE+0)
-#define PD_EVENT_VIDEO_CODEC   (PD_EVENT_VIDEO_BASE+1)
+#define PD_EVENT_VIDEO_BASE 0x60
+#define PD_EVENT_VIDEO_DP_MODE (PD_EVENT_VIDEO_BASE + 0)
+#define PD_EVENT_VIDEO_CODEC (PD_EVENT_VIDEO_BASE + 1)
 /* Returned in the "type" field, when there is no entry available */
-#define PD_EVENT_NO_ENTRY       0xff
+#define PD_EVENT_NO_ENTRY 0xff
 
 /*
  * PD_EVENT_MCU_CHARGE event definition :
@@ -5594,24 +5996,24 @@ struct ec_response_pd_log {
  * the data field contains the port state flags as defined below :
  */
 /* Port partner is a dual role device */
-#define CHARGE_FLAGS_DUAL_ROLE         BIT(15)
+#define CHARGE_FLAGS_DUAL_ROLE BIT(15)
 /* Port is the pending override port */
-#define CHARGE_FLAGS_DELAYED_OVERRIDE  BIT(14)
+#define CHARGE_FLAGS_DELAYED_OVERRIDE BIT(14)
 /* Port is the override port */
-#define CHARGE_FLAGS_OVERRIDE          BIT(13)
+#define CHARGE_FLAGS_OVERRIDE BIT(13)
 /* Charger type */
-#define CHARGE_FLAGS_TYPE_SHIFT               3
-#define CHARGE_FLAGS_TYPE_MASK       (0xf << CHARGE_FLAGS_TYPE_SHIFT)
+#define CHARGE_FLAGS_TYPE_SHIFT 3
+#define CHARGE_FLAGS_TYPE_MASK (0xf << CHARGE_FLAGS_TYPE_SHIFT)
 /* Power delivery role */
-#define CHARGE_FLAGS_ROLE_MASK         (7 <<  0)
+#define CHARGE_FLAGS_ROLE_MASK (7 << 0)
 
 /*
  * PD_EVENT_PS_FAULT data field flags definition :
  */
-#define PS_FAULT_OCP                          1
-#define PS_FAULT_FAST_OCP                     2
-#define PS_FAULT_OVP                          3
-#define PS_FAULT_DISCH                        4
+#define PS_FAULT_OCP 1
+#define PS_FAULT_FAST_OCP 2
+#define PS_FAULT_OVP 3
+#define PS_FAULT_DISCH 4
 
 /*
  * PD_EVENT_VIDEO_CODEC payload is "struct mcdp_info".
@@ -5637,13 +6039,17 @@ struct mcdp_info {
 #define EC_CMD_USB_PD_GET_AMODE 0x0116
 struct ec_params_usb_pd_get_mode_request {
 	uint16_t svid_idx; /* SVID index to get */
-	uint8_t port;      /* port */
+	uint8_t port; /* port */
 } __ec_align_size1;
 
+#define VDO_MAX_SIZE 7
+/* Max number of VDM data objects without VDM header */
+#define VDO_MAX_OBJECTS (VDO_MAX_SIZE - 1)
+
 struct ec_params_usb_pd_get_mode_response {
-	uint16_t svid;   /* SVID */
-	uint16_t opos;    /* Object Position */
-	uint32_t vdo[6]; /* Mode VDOs */
+	uint16_t svid; /* SVID */
+	uint16_t opos; /* Object Position */
+	uint32_t vdo[VDO_MAX_OBJECTS]; /* Mode VDOs */
 } __ec_align4;
 
 #define EC_CMD_USB_PD_SET_AMODE 0x0117
@@ -5656,10 +6062,10 @@ enum pd_mode_cmd {
 };
 
 struct ec_params_usb_pd_set_mode_request {
-	uint32_t cmd;  /* enum pd_mode_cmd */
+	uint32_t cmd; /* enum pd_mode_cmd */
 	uint16_t svid; /* SVID to set */
-	uint8_t opos;  /* Object Position */
-	uint8_t port;  /* port */
+	uint8_t opos; /* Object Position */
+	uint8_t port; /* port */
 } __ec_align4;
 
 /* Ask the PD MCU to record a log of a requested type */
@@ -5670,20 +6076,19 @@ struct ec_params_pd_write_log_entry {
 	uint8_t port; /* port#, or 0 for events unrelated to a given port */
 } __ec_align1;
 
-
 /* Control USB-PD chip */
 #define EC_CMD_PD_CONTROL 0x0119
 
 enum ec_pd_control_cmd {
-	PD_SUSPEND = 0,      /* Suspend the PD chip (EC: stop talking to PD) */
-	PD_RESUME,           /* Resume the PD chip (EC: start talking to PD) */
-	PD_RESET,            /* Force reset the PD chip */
-	PD_CONTROL_DISABLE,  /* Disable further calls to this command */
-	PD_CHIP_ON,          /* Power on the PD chip */
+	PD_SUSPEND = 0, /* Suspend the PD chip (EC: stop talking to PD) */
+	PD_RESUME, /* Resume the PD chip (EC: start talking to PD) */
+	PD_RESET, /* Force reset the PD chip */
+	PD_CONTROL_DISABLE, /* Disable further calls to this command */
+	PD_CHIP_ON, /* Power on the PD chip */
 };
 
 struct ec_params_pd_control {
-	uint8_t chip;         /* chip id */
+	uint8_t chip; /* chip id */
 	uint8_t subcmd;
 } __ec_align1;
 
@@ -5695,27 +6100,29 @@ struct ec_params_usb_pd_mux_info {
 } __ec_align1;
 
 /* Flags representing mux state */
-#define USB_PD_MUX_NONE               0      /* Open switch */
-#define USB_PD_MUX_USB_ENABLED        BIT(0) /* USB connected */
-#define USB_PD_MUX_DP_ENABLED         BIT(1) /* DP connected */
-#define USB_PD_MUX_POLARITY_INVERTED  BIT(2) /* CC line Polarity inverted */
-#define USB_PD_MUX_HPD_IRQ            BIT(3) /* HPD IRQ is asserted */
-#define USB_PD_MUX_HPD_LVL            BIT(4) /* HPD level is asserted */
-#define USB_PD_MUX_SAFE_MODE          BIT(5) /* DP is in safe mode */
+#define USB_PD_MUX_NONE 0 /* Open switch */
+#define USB_PD_MUX_USB_ENABLED BIT(0) /* USB connected */
+#define USB_PD_MUX_DP_ENABLED BIT(1) /* DP connected */
+#define USB_PD_MUX_POLARITY_INVERTED BIT(2) /* CC line Polarity inverted */
+#define USB_PD_MUX_HPD_IRQ BIT(3) /* HPD IRQ is asserted */
+#define USB_PD_MUX_HPD_IRQ_DEASSERTED 0 /* HPD IRQ is deasserted */
+#define USB_PD_MUX_HPD_LVL BIT(4) /* HPD level is asserted */
+#define USB_PD_MUX_HPD_LVL_DEASSERTED 0 /* HPD level is deasserted */
+#define USB_PD_MUX_SAFE_MODE BIT(5) /* DP is in safe mode */
 #define USB_PD_MUX_TBT_COMPAT_ENABLED BIT(6) /* TBT compat enabled */
-#define USB_PD_MUX_USB4_ENABLED       BIT(7) /* USB4 enabled */
+#define USB_PD_MUX_USB4_ENABLED BIT(7) /* USB4 enabled */
 
 /* USB-C Dock connected */
-#define USB_PD_MUX_DOCK		(USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED)
+#define USB_PD_MUX_DOCK (USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED)
 
 struct ec_response_usb_pd_mux_info {
 	uint8_t flags; /* USB_PD_MUX_*-encoded USB mux state */
 } __ec_align1;
 
-#define EC_CMD_PD_CHIP_INFO		0x011B
+#define EC_CMD_PD_CHIP_INFO 0x011B
 
 struct ec_params_pd_chip_info {
-	uint8_t port;	/* USB-C port number */
+	uint8_t port; /* USB-C port number */
 	/*
 	 * Fetch the live chip info or hard-coded + cached chip info
 	 * 0: hardcoded value for VID/PID, cached value for FW version
@@ -5731,7 +6138,7 @@ struct ec_response_pd_chip_info {
 	union {
 		uint8_t fw_version_string[8];
 		uint64_t fw_version_number;
-	};
+	} __ec_align2;
 } __ec_align2;
 
 struct ec_response_pd_chip_info_v1 {
@@ -5741,26 +6148,26 @@ struct ec_response_pd_chip_info_v1 {
 	union {
 		uint8_t fw_version_string[8];
 		uint64_t fw_version_number;
-	};
+	} __ec_align2;
 	union {
 		uint8_t min_req_fw_version_string[8];
 		uint64_t min_req_fw_version_number;
-	};
+	} __ec_align2;
 } __ec_align2;
 
 /* Run RW signature verification and get status */
-#define EC_CMD_RWSIG_CHECK_STATUS	0x011C
+#define EC_CMD_RWSIG_CHECK_STATUS 0x011C
 
 struct ec_response_rwsig_check_status {
 	uint32_t status;
 } __ec_align4;
 
 /* For controlling RWSIG task */
-#define EC_CMD_RWSIG_ACTION	0x011D
+#define EC_CMD_RWSIG_ACTION 0x011D
 
 enum rwsig_action {
-	RWSIG_ACTION_ABORT = 0,		/* Abort RWSIG and prevent jumping */
-	RWSIG_ACTION_CONTINUE = 1,	/* Jump to RW immediately */
+	RWSIG_ACTION_ABORT = 0, /* Abort RWSIG and prevent jumping */
+	RWSIG_ACTION_CONTINUE = 1, /* Jump to RW immediately */
 };
 
 struct ec_params_rwsig_action {
@@ -5768,10 +6175,10 @@ struct ec_params_rwsig_action {
 } __ec_align4;
 
 /* Run verification on a slot */
-#define EC_CMD_EFS_VERIFY	0x011E
+#define EC_CMD_EFS_VERIFY 0x011E
 
 struct ec_params_efs_verify {
-	uint8_t region;		/* enum ec_flash_region */
+	uint8_t region; /* enum ec_flash_region */
 } __ec_align1;
 
 /*
@@ -5779,24 +6186,60 @@ struct ec_params_efs_verify {
  * type. Integers return a uint32. Strings return a string, using the response
  * size to determine how big it is.
  */
-#define EC_CMD_GET_CROS_BOARD_INFO	0x011F
+#define EC_CMD_GET_CROS_BOARD_INFO 0x011F
 /*
  * Write info into Cros Board Info on EEPROM. Write fails if the board has
  * hardware write-protect enabled.
  */
-#define EC_CMD_SET_CROS_BOARD_INFO	0x0120
+#define EC_CMD_SET_CROS_BOARD_INFO 0x0120
 
 enum cbi_data_tag {
 	CBI_TAG_BOARD_VERSION = 0, /* uint32_t or smaller */
-	CBI_TAG_OEM_ID = 1,        /* uint32_t or smaller */
-	CBI_TAG_SKU_ID = 2,        /* uint32_t or smaller */
+	CBI_TAG_OEM_ID = 1, /* uint32_t or smaller */
+	CBI_TAG_SKU_ID = 2, /* uint32_t or smaller */
 	CBI_TAG_DRAM_PART_NUM = 3, /* variable length ascii, nul terminated. */
-	CBI_TAG_OEM_NAME = 4,      /* variable length ascii, nul terminated. */
-	CBI_TAG_MODEL_ID = 5,      /* uint32_t or smaller */
-	CBI_TAG_FW_CONFIG = 6,     /* uint32_t bit field */
-	CBI_TAG_PCB_SUPPLIER = 7,  /* uint32_t or smaller */
+	CBI_TAG_OEM_NAME = 4, /* variable length ascii, nul terminated. */
+	CBI_TAG_MODEL_ID = 5, /* uint32_t or smaller */
+	CBI_TAG_FW_CONFIG = 6, /* uint32_t bit field */
+	CBI_TAG_PCB_SUPPLIER = 7, /* uint32_t or smaller */
 	/* Second Source Factory Cache */
-	CBI_TAG_SSFC = 8,          /* uint32_t bit field */
+	CBI_TAG_SSFC = 8, /* uint32_t bit field */
+	CBI_TAG_REWORK_ID = 9, /* uint64_t or smaller */
+	CBI_TAG_FACTORY_CALIBRATION_DATA = 10, /* uint32_t bit field */
+	/*
+	 * Battery info
+	 */
+	/* struct fuel_gauge_info */
+	CBI_TAG_FUEL_GAUGE_MANUF_NAME,
+	CBI_TAG_FUEL_GAUGE_DEVICE_NAME,
+	CBI_TAG_FUEL_GAUGE_FLAGS,
+	/* struct ship_mod_info */
+	CBI_TAG_BATT_SHIP_MODE_REG_ADDR,
+	CBI_TAG_BATT_SHIP_MODE_REG_DATA,
+	CBI_TAG_BATT_SHIP_MODE_FLAGS, /* enum ship_mode_flag */
+	/* struct sleep_mode_info */
+	CBI_TAG_BATT_SLEEP_MODE_REG_ADDR,
+	CBI_TAG_BATT_SLEEP_MODE_REG_DATA,
+	CBI_TAG_BATT_SLEEP_MODE_FLAGS, /* enum sleep_mode_flag */
+	/* struct fet_info */
+	CBI_TAG_BATT_FET_REG_ADDR,
+	CBI_TAG_BATT_FET_REG_MASK,
+	CBI_TAG_BATT_FET_DISCONNECT_VAL,
+	CBI_TAG_BATT_FET_CFET_MASK,
+	CBI_TAG_BATT_FET_CFET_OFF_VAL,
+	CBI_TAG_BATT_FET_FLAGS, /* enum batt_fet_flag */
+	/* struct battery_info */
+	CBI_TAG_BATT_VOLTAGE_MAX,
+	CBI_TAG_BATT_VOLTAGE_NORMAL,
+	CBI_TAG_BATT_VOLTAGE_MIN,
+	CBI_TAG_BATT_PRECHARGE_VOLTAGE,
+	CBI_TAG_BATT_PRECHARGE_CURRENT,
+	CBI_TAG_BATT_START_CHARGING_MIN_C,
+	CBI_TAG_BATT_START_CHARGING_MAX_C,
+	CBI_TAG_BATT_CHARGING_MIN_C,
+	CBI_TAG_BATT_CHARGING_MAX_C,
+	CBI_TAG_BATT_DISCHARGING_MIN_C,
+	CBI_TAG_BATT_DISCHARGING_MAX_C,
 	CBI_TAG_COUNT,
 };
 
@@ -5806,11 +6249,11 @@ enum cbi_data_tag {
  * RELOAD:  Invalidate cache and read data from EEPROM. Useful to verify
  *          write was successful without reboot.
  */
-#define CBI_GET_RELOAD		BIT(0)
+#define CBI_GET_RELOAD BIT(0)
 
 struct ec_params_get_cbi {
-	uint32_t tag;		/* enum cbi_data_tag */
-	uint32_t flag;		/* CBI_GET_* */
+	uint32_t tag; /* enum cbi_data_tag */
+	uint32_t flag; /* CBI_GET_* */
 } __ec_align4;
 
 /*
@@ -5821,14 +6264,14 @@ struct ec_params_get_cbi {
  * INIT:    Need to be set when creating a new CBI from scratch. All fields
  *          will be initialized to zero first.
  */
-#define CBI_SET_NO_SYNC		BIT(0)
-#define CBI_SET_INIT		BIT(1)
+#define CBI_SET_NO_SYNC BIT(0)
+#define CBI_SET_INIT BIT(1)
 
 struct ec_params_set_cbi {
-	uint32_t tag;		/* enum cbi_data_tag */
-	uint32_t flag;		/* CBI_SET_* */
-	uint32_t size;		/* Data size */
-	uint8_t data[];		/* For string and raw data */
+	uint32_t tag; /* enum cbi_data_tag */
+	uint32_t flag; /* CBI_SET_* */
+	uint32_t size; /* Data size */
+	uint8_t data[]; /* For string and raw data */
 } __ec_align1;
 
 /*
@@ -5836,34 +6279,99 @@ struct ec_params_set_cbi {
  */
 #define EC_CMD_GET_UPTIME_INFO 0x0121
 
-/* Reset causes */
-#define EC_RESET_FLAG_OTHER       BIT(0)   /* Other known reason */
-#define EC_RESET_FLAG_RESET_PIN   BIT(1)   /* Reset pin asserted */
-#define EC_RESET_FLAG_BROWNOUT    BIT(2)   /* Brownout */
-#define EC_RESET_FLAG_POWER_ON    BIT(3)   /* Power-on reset */
-#define EC_RESET_FLAG_WATCHDOG    BIT(4)   /* Watchdog timer reset */
-#define EC_RESET_FLAG_SOFT        BIT(5)   /* Soft reset trigger by core */
-#define EC_RESET_FLAG_HIBERNATE   BIT(6)   /* Wake from hibernate */
-#define EC_RESET_FLAG_RTC_ALARM   BIT(7)   /* RTC alarm wake */
-#define EC_RESET_FLAG_WAKE_PIN    BIT(8)   /* Wake pin triggered wake */
-#define EC_RESET_FLAG_LOW_BATTERY BIT(9)   /* Low battery triggered wake */
-#define EC_RESET_FLAG_SYSJUMP     BIT(10)  /* Jumped directly to this image */
-#define EC_RESET_FLAG_HARD        BIT(11)  /* Hard reset from software */
-#define EC_RESET_FLAG_AP_OFF      BIT(12)  /* Do not power on AP */
-#define EC_RESET_FLAG_PRESERVED   BIT(13)  /* Some reset flags preserved from
-					    * previous boot
-					    */
-#define EC_RESET_FLAG_USB_RESUME  BIT(14)  /* USB resume triggered wake */
-#define EC_RESET_FLAG_RDD         BIT(15)  /* USB Type-C debug cable */
-#define EC_RESET_FLAG_RBOX        BIT(16)  /* Fixed Reset Functionality */
-#define EC_RESET_FLAG_SECURITY    BIT(17)  /* Security threat */
-#define EC_RESET_FLAG_AP_WATCHDOG BIT(18)  /* AP experienced a watchdog reset */
-#define EC_RESET_FLAG_STAY_IN_RO  BIT(19)  /* Do not select RW in EFS. This
-					    * enables PD in RO for Chromebox.
-					    */
-#define EC_RESET_FLAG_EFS         BIT(20)  /* Jumped to this image by EFS */
-#define EC_RESET_FLAG_AP_IDLE     BIT(21)  /* Leave alone AP */
-#define EC_RESET_FLAG_INITIAL_PWR BIT(22)  /* EC had power, then was reset */
+/* EC reset causes */
+#define EC_RESET_FLAG_OTHER BIT(0) /* Other known reason */
+#define EC_RESET_FLAG_RESET_PIN BIT(1) /* Reset pin asserted */
+#define EC_RESET_FLAG_BROWNOUT BIT(2) /* Brownout */
+#define EC_RESET_FLAG_POWER_ON BIT(3) /* Power-on reset */
+#define EC_RESET_FLAG_WATCHDOG BIT(4) /* Watchdog timer reset */
+#define EC_RESET_FLAG_SOFT BIT(5) /* Soft reset trigger by core */
+#define EC_RESET_FLAG_HIBERNATE BIT(6) /* Wake from hibernate */
+#define EC_RESET_FLAG_RTC_ALARM BIT(7) /* RTC alarm wake */
+#define EC_RESET_FLAG_WAKE_PIN BIT(8) /* Wake pin triggered wake */
+#define EC_RESET_FLAG_LOW_BATTERY BIT(9) /* Low battery triggered wake */
+#define EC_RESET_FLAG_SYSJUMP BIT(10) /* Jumped directly to this image */
+#define EC_RESET_FLAG_HARD BIT(11) /* Hard reset from software */
+#define EC_RESET_FLAG_AP_OFF BIT(12) /* Do not power on AP */
+/* Some reset flags preserved from previous boot */
+#define EC_RESET_FLAG_PRESERVED BIT(13)
+#define EC_RESET_FLAG_USB_RESUME BIT(14) /* USB resume triggered wake */
+#define EC_RESET_FLAG_RDD BIT(15) /* USB Type-C debug cable */
+#define EC_RESET_FLAG_RBOX BIT(16) /* Fixed Reset Functionality */
+#define EC_RESET_FLAG_SECURITY BIT(17) /* Security threat */
+/* AP experienced a watchdog reset */
+#define EC_RESET_FLAG_AP_WATCHDOG BIT(18)
+/* Do not select RW in EFS. This enables PD in RO for Chromebox. */
+#define EC_RESET_FLAG_STAY_IN_RO BIT(19)
+#define EC_RESET_FLAG_EFS BIT(20) /* Jumped to this image by EFS */
+#define EC_RESET_FLAG_AP_IDLE BIT(21) /* Leave alone AP */
+#define EC_RESET_FLAG_INITIAL_PWR BIT(22) /* EC had power, then was reset */
+
+/*
+ * Reason codes used by the AP after a shutdown to figure out why it was reset
+ * by the EC.  These are sent in EC commands.  Therefore, to maintain protocol
+ * compatibility:
+ * - New entries must be inserted prior to the _COUNT field
+ * - If an existing entry is no longer in service, it must be replaced with a
+ *   RESERVED entry instead.
+ * - The semantic meaning of an entry should not change.
+ * - Do not exceed 2^15 - 1 for reset reasons or 2^16 - 1 for shutdown reasons.
+ */
+enum chipset_shutdown_reason {
+	/*
+	 * Beginning of reset reasons.
+	 */
+	CHIPSET_RESET_BEGIN = 0,
+	CHIPSET_RESET_UNKNOWN = CHIPSET_RESET_BEGIN,
+	/* Custom reason defined by a board.c or baseboard.c file */
+	CHIPSET_RESET_BOARD_CUSTOM,
+	/* Believe that the AP has hung */
+	CHIPSET_RESET_HANG_REBOOT,
+	/* Reset by EC console command */
+	CHIPSET_RESET_CONSOLE_CMD,
+	/* Reset by EC host command */
+	CHIPSET_RESET_HOST_CMD,
+	/* Keyboard module reset key combination */
+	CHIPSET_RESET_KB_SYSRESET,
+	/* Keyboard module warm reboot */
+	CHIPSET_RESET_KB_WARM_REBOOT,
+	/* Debug module warm reboot */
+	CHIPSET_RESET_DBG_WARM_REBOOT,
+	/* I cannot self-terminate.  You must lower me into the steel. */
+	CHIPSET_RESET_AP_REQ,
+	/* Reset as side-effect of startup sequence */
+	CHIPSET_RESET_INIT,
+	/* EC detected an AP watchdog event. */
+	CHIPSET_RESET_AP_WATCHDOG,
+
+	CHIPSET_RESET_COUNT, /* End of reset reasons. */
+
+	/*
+	 * Beginning of shutdown reasons.
+	 */
+	CHIPSET_SHUTDOWN_BEGIN = BIT(15),
+	CHIPSET_SHUTDOWN_POWERFAIL = CHIPSET_SHUTDOWN_BEGIN,
+	/* Forcing a shutdown as part of EC initialization */
+	CHIPSET_SHUTDOWN_INIT,
+	/* Custom reason on a per-board basis. */
+	CHIPSET_SHUTDOWN_BOARD_CUSTOM,
+	/* This is a reason to inhibit startup, not cause shut down. */
+	CHIPSET_SHUTDOWN_BATTERY_INHIBIT,
+	/* A power_wait_signal is being asserted */
+	CHIPSET_SHUTDOWN_WAIT,
+	/* Critical battery level. */
+	CHIPSET_SHUTDOWN_BATTERY_CRIT,
+	/* Because you told me to. */
+	CHIPSET_SHUTDOWN_CONSOLE_CMD,
+	/* Forcing a shutdown to effect entry to G3. */
+	CHIPSET_SHUTDOWN_G3,
+	/* Force shutdown due to over-temperature. */
+	CHIPSET_SHUTDOWN_THERMAL,
+	/* Force a chipset shutdown from the power button through EC */
+	CHIPSET_SHUTDOWN_BUTTON,
+
+	CHIPSET_SHUTDOWN_COUNT, /* End of shutdown reasons. */
+};
 
 struct ec_response_uptime_info {
 	/*
@@ -5892,10 +6400,7 @@ struct ec_response_uptime_info {
 
 	/* Empty log entries have both the cause and timestamp set to zero. */
 	struct ap_reset_log_entry {
-		/*
-		 * See include/chipset.h: enum chipset_{reset,shutdown}_reason
-		 * for details.
-		 */
+		/* See enum chipset_{reset,shutdown}_reason for details. */
 		uint16_t reset_cause;
 
 		/* Reserved for protocol growth. */
@@ -5916,7 +6421,7 @@ struct ec_response_uptime_info {
  * Depending on the chip, the operation may take a long time (e.g. to erase
  * flash), so the commands are asynchronous.
  */
-#define EC_CMD_ADD_ENTROPY	0x0122
+#define EC_CMD_ADD_ENTROPY 0x0122
 
 enum add_entropy_action {
 	/* Add entropy to the current secret. */
@@ -5938,7 +6443,7 @@ struct ec_params_rollback_add_entropy {
 /*
  * Perform a single read of a given ADC channel.
  */
-#define EC_CMD_ADC_READ		0x0123
+#define EC_CMD_ADC_READ 0x0123
 
 struct ec_params_adc_read {
 	uint8_t adc_channel;
@@ -5951,7 +6456,7 @@ struct ec_response_adc_read {
 /*
  * Read back rollback info
  */
-#define EC_CMD_ROLLBACK_INFO		0x0124
+#define EC_CMD_ROLLBACK_INFO 0x0124
 
 struct ec_response_rollback_info {
 	int32_t id; /* Incrementing number to indicate which region to use. */
@@ -5959,7 +6464,6 @@ struct ec_response_rollback_info {
 	int32_t rw_rollback_version;
 } __ec_align4;
 
-
 /* Issue AP reset */
 #define EC_CMD_AP_RESET 0x0125
 
@@ -5988,23 +6492,22 @@ enum ec_bus_type {
 };
 
 struct ec_i2c_info {
-	uint16_t port;		/* Physical port for device */
-	uint16_t addr_flags;	/* 7-bit (or 10-bit) address */
+	uint16_t port; /* Physical port for device */
+	uint16_t addr_flags; /* 7-bit (or 10-bit) address */
 };
 
 struct ec_params_locate_chip {
-	uint8_t type;		/* enum ec_chip_type */
-	uint8_t index;		/* Specifies one instance of chip type */
+	uint8_t type; /* enum ec_chip_type */
+	uint8_t index; /* Specifies one instance of chip type */
 	/* Used for type specific parameters in future */
 	union {
 		uint16_t reserved;
 	};
 } __ec_align2;
 
-
 struct ec_response_locate_chip {
-	uint8_t bus_type;	/* enum ec_bus_type */
-	uint8_t reserved;	/* Aligning the following union to 2 bytes */
+	uint8_t bus_type; /* enum ec_bus_type */
+	uint8_t reserved; /* Aligning the following union to 2 bytes */
 	union {
 		struct ec_i2c_info i2c_info;
 	};
@@ -6015,13 +6518,21 @@ struct ec_response_locate_chip {
  *
  * This command is used for validation purpose, where the AP needs to be
  * returned back to S0 state from G3 state without using the servo to trigger
- * wake events.For this,there is no request or response struct.
- *
- * Order of command usage:
- * ectool reboot_ap_on_g3 && shutdown -h now
+ * wake events.
+ * - With command version 0:
+ * AP reboots immediately from G3
+ * command usage: ectool reboot_ap_on_g3 && shutdown -h now
+ * - With command version 1:
+ * AP reboots after the user specified delay
+ * command usage: ectool reboot_ap_on_g3 [<delay>] && shutdown -h now
  */
 #define EC_CMD_REBOOT_AP_ON_G3 0x0127
 
+struct ec_params_reboot_ap_on_g3_v1 {
+	/* configurable delay in seconds in G3 state */
+	uint32_t reboot_ap_at_g3_delay;
+} __ec_align4;
+
 /*****************************************************************************/
 /* Get PD port capabilities
  *
@@ -6067,27 +6578,27 @@ enum ec_pd_port_location {
 	 * left side, while BACK_LEFT means the leftmost port on the back of the
 	 * device.
 	 */
-	EC_PD_PORT_LOCATION_LEFT        = 1,
-	EC_PD_PORT_LOCATION_RIGHT       = 2,
-	EC_PD_PORT_LOCATION_BACK        = 3,
-	EC_PD_PORT_LOCATION_FRONT       = 4,
-	EC_PD_PORT_LOCATION_LEFT_FRONT  = 5,
-	EC_PD_PORT_LOCATION_LEFT_BACK   = 6,
+	EC_PD_PORT_LOCATION_LEFT = 1,
+	EC_PD_PORT_LOCATION_RIGHT = 2,
+	EC_PD_PORT_LOCATION_BACK = 3,
+	EC_PD_PORT_LOCATION_FRONT = 4,
+	EC_PD_PORT_LOCATION_LEFT_FRONT = 5,
+	EC_PD_PORT_LOCATION_LEFT_BACK = 6,
 	EC_PD_PORT_LOCATION_RIGHT_FRONT = 7,
-	EC_PD_PORT_LOCATION_RIGHT_BACK  = 8,
-	EC_PD_PORT_LOCATION_BACK_LEFT   = 9,
-	EC_PD_PORT_LOCATION_BACK_RIGHT  = 10,
+	EC_PD_PORT_LOCATION_RIGHT_BACK = 8,
+	EC_PD_PORT_LOCATION_BACK_LEFT = 9,
+	EC_PD_PORT_LOCATION_BACK_RIGHT = 10,
 };
 
 struct ec_params_get_pd_port_caps {
-	uint8_t port;		/* Which port to interrogate */
+	uint8_t port; /* Which port to interrogate */
 } __ec_align1;
 
 struct ec_response_get_pd_port_caps {
-	uint8_t pd_power_role_cap;	/* enum ec_pd_power_role_caps */
-	uint8_t pd_try_power_role_cap;	/* enum ec_pd_try_power_role_caps */
-	uint8_t pd_data_role_cap;	/* enum ec_pd_data_role_caps */
-	uint8_t pd_port_location;	/* enum ec_pd_port_location */
+	uint8_t pd_power_role_cap; /* enum ec_pd_power_role_caps */
+	uint8_t pd_try_power_role_cap; /* enum ec_pd_try_power_role_caps */
+	uint8_t pd_data_role_cap; /* enum ec_pd_data_role_caps */
+	uint8_t pd_port_location; /* enum ec_pd_port_location */
 } __ec_align1;
 
 /*****************************************************************************/
@@ -6104,27 +6615,29 @@ struct ec_response_get_pd_port_caps {
 
 struct ec_params_button {
 	/* Button mask aligned to enum keyboard_button_type */
-	uint32_t  btn_mask;
+	uint32_t btn_mask;
 
 	/* Duration in milliseconds button needs to be pressed */
-	uint32_t  press_ms;
+	uint32_t press_ms;
 } __ec_align1;
 
 enum keyboard_button_type {
-	KEYBOARD_BUTTON_POWER       = 0,
+	KEYBOARD_BUTTON_POWER = 0,
 	KEYBOARD_BUTTON_VOLUME_DOWN = 1,
-	KEYBOARD_BUTTON_VOLUME_UP   = 2,
-	KEYBOARD_BUTTON_RECOVERY    = 3,
-	KEYBOARD_BUTTON_CAPSENSE_1  = 4,
-	KEYBOARD_BUTTON_CAPSENSE_2  = 5,
-	KEYBOARD_BUTTON_CAPSENSE_3  = 6,
-	KEYBOARD_BUTTON_CAPSENSE_4  = 7,
-	KEYBOARD_BUTTON_CAPSENSE_5  = 8,
-	KEYBOARD_BUTTON_CAPSENSE_6  = 9,
-	KEYBOARD_BUTTON_CAPSENSE_7  = 10,
-	KEYBOARD_BUTTON_CAPSENSE_8  = 11,
-
-	KEYBOARD_BUTTON_COUNT
+	KEYBOARD_BUTTON_VOLUME_UP = 2,
+	KEYBOARD_BUTTON_RECOVERY = 3,
+	KEYBOARD_BUTTON_CAPSENSE_1 = 4,
+	KEYBOARD_BUTTON_CAPSENSE_2 = 5,
+	KEYBOARD_BUTTON_CAPSENSE_3 = 6,
+	KEYBOARD_BUTTON_CAPSENSE_4 = 7,
+	KEYBOARD_BUTTON_CAPSENSE_5 = 8,
+	KEYBOARD_BUTTON_CAPSENSE_6 = 9,
+	KEYBOARD_BUTTON_CAPSENSE_7 = 10,
+	KEYBOARD_BUTTON_CAPSENSE_8 = 11,
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+	KEYBOARD_BUTTON_POWER_FAKE  = 11, /* buttons_8042 not use recovery */
+#endif
+	KEYBOARD_BUTTON_COUNT,
 };
 
 /*****************************************************************************/
@@ -6161,6 +6674,9 @@ enum action_key {
 	TK_PLAY_PAUSE = 15,
 	TK_NEXT_TRACK = 16,
 	TK_PREV_TRACK = 17,
+	TK_KBD_BKLIGHT_TOGGLE = 18,
+	TK_MICMUTE = 19,
+	TK_MENU = 20,
 };
 
 /*
@@ -6175,15 +6691,15 @@ enum action_key {
  * action keys. This is possible for e.g. if the keyboard has a
  * dedicated Fn key.
  */
-#define KEYBD_CAP_FUNCTION_KEYS		BIT(0)
+#define KEYBD_CAP_FUNCTION_KEYS BIT(0)
 /*
  * Whether the keyboard has a dedicated numeric keyboard.
  */
-#define KEYBD_CAP_NUMERIC_KEYPAD	BIT(1)
+#define KEYBD_CAP_NUMERIC_KEYPAD BIT(1)
 /*
  * Whether the keyboard has a screenlock key.
  */
-#define KEYBD_CAP_SCRNLOCK_KEY		BIT(2)
+#define KEYBD_CAP_SCRNLOCK_KEY BIT(2)
 
 struct ec_response_keybd_config {
 	/*
@@ -6210,12 +6726,12 @@ struct ec_response_keybd_config {
  */
 #define EC_CMD_SMART_DISCHARGE 0x012B
 
-#define EC_SMART_DISCHARGE_FLAGS_SET	BIT(0)
+#define EC_SMART_DISCHARGE_FLAGS_SET BIT(0)
 
 /* Discharge rates when the system is in cutoff or hibernation. */
 struct discharge_rate {
-	uint16_t cutoff;  /* Discharge rate (uA) in cutoff */
-	uint16_t hibern;  /* Discharge rate (uA) in hibernation */
+	uint16_t cutoff; /* Discharge rate (uA) in cutoff */
+	uint16_t hibern; /* Discharge rate (uA) in hibernation */
 };
 
 struct smart_discharge_zone {
@@ -6226,7 +6742,7 @@ struct smart_discharge_zone {
 };
 
 struct ec_params_smart_discharge {
-	uint8_t flags;  /* EC_SMART_DISCHARGE_FLAGS_* */
+	uint8_t flags; /* EC_SMART_DISCHARGE_FLAGS_* */
 	/*
 	 * Desired hours for the battery to survive before reaching 0%. Set to
 	 * zero to disable smart discharging. That is, the system hibernates as
@@ -6342,6 +6858,7 @@ struct ec_response_regulator_get_voltage {
 enum typec_partner_type {
 	TYPEC_PARTNER_SOP = 0,
 	TYPEC_PARTNER_SOP_PRIME = 1,
+	TYPEC_PARTNER_SOP_PRIME_PRIME = 2,
 };
 
 struct ec_params_typec_discovery {
@@ -6351,15 +6868,15 @@ struct ec_params_typec_discovery {
 
 struct svid_mode_info {
 	uint16_t svid;
-	uint16_t mode_count;  /* Number of modes partner sent */
-	uint32_t mode_vdo[6]; /* Max VDOs allowed after VDM header is 6 */
+	uint16_t mode_count; /* Number of modes partner sent */
+	uint32_t mode_vdo[VDO_MAX_OBJECTS];
 };
 
 struct ec_response_typec_discovery {
-	uint8_t identity_count;    /* Number of identity VDOs partner sent */
-	uint8_t svid_count;	   /* Number of SVIDs partner sent */
+	uint8_t identity_count; /* Number of identity VDOs partner sent */
+	uint8_t svid_count; /* Number of SVIDs partner sent */
 	uint16_t reserved;
-	uint32_t discovery_vdo[6]; /* Max VDOs allowed after VDM header is 6 */
+	uint32_t discovery_vdo[VDO_MAX_OBJECTS];
 	struct svid_mode_info svids[0];
 } __ec_align1;
 
@@ -6369,11 +6886,48 @@ struct ec_response_typec_discovery {
 enum typec_control_command {
 	TYPEC_CONTROL_COMMAND_EXIT_MODES,
 	TYPEC_CONTROL_COMMAND_CLEAR_EVENTS,
+	TYPEC_CONTROL_COMMAND_ENTER_MODE,
+	TYPEC_CONTROL_COMMAND_TBT_UFP_REPLY,
+	TYPEC_CONTROL_COMMAND_USB_MUX_SET,
+	TYPEC_CONTROL_COMMAND_BIST_SHARE_MODE,
+	TYPEC_CONTROL_COMMAND_SEND_VDM_REQ,
+};
+
+/* Modes (USB or alternate) that a type-C port may enter. */
+enum typec_mode {
+	TYPEC_MODE_DP,
+	TYPEC_MODE_TBT,
+	TYPEC_MODE_USB4,
+};
+
+/* Replies the AP may specify to the TBT EnterMode command as a UFP */
+enum typec_tbt_ufp_reply {
+	TYPEC_TBT_UFP_REPLY_NAK,
+	TYPEC_TBT_UFP_REPLY_ACK,
 };
 
+#define TYPEC_USB_MUX_SET_ALL_CHIPS 0xFF
+
+struct typec_usb_mux_set {
+	/* Index of the mux to set in the chain */
+	uint8_t mux_index;
+
+	/* USB_PD_MUX_*-encoded USB mux state to set */
+	uint8_t mux_flags;
+} __ec_align1;
+
+struct typec_vdm_req {
+	/* VDM data, including VDM header */
+	uint32_t vdm_data[VDO_MAX_SIZE];
+	/* Number of 32-bit fields filled in */
+	uint8_t vdm_data_objects;
+	/* Partner to address - see enum typec_partner_type */
+	uint8_t partner_type;
+} __ec_align1;
+
 struct ec_params_typec_control {
 	uint8_t port;
-	uint8_t command;	/* enum typec_control_command */
+	uint8_t command; /* enum typec_control_command */
 	uint16_t reserved;
 
 	/*
@@ -6382,7 +6936,18 @@ struct ec_params_typec_control {
 	 * the command version when adding new sub-commands.
 	 */
 	union {
+		/* Used for CLEAR_EVENTS */
 		uint32_t clear_events_mask;
+		/* Used for ENTER_MODE - enum typec_mode */
+		uint8_t mode_to_enter;
+		/* Used for TBT_UFP_REPLY - enum typec_tbt_ufp_reply */
+		uint8_t tbt_ufp_reply;
+		/* Used for USB_MUX_SET */
+		struct typec_usb_mux_set mux_params;
+		/* Used for BIST_SHARE_MODE */
+		uint8_t bist_share_mode;
+		/* Used for VMD_REQ */
+		struct typec_vdm_req vdm_req_params;
 		uint8_t placeholder[128];
 	};
 } __ec_align1;
@@ -6396,9 +6961,6 @@ struct ec_params_typec_control {
  * EC_CMD_USB_PD_CONTROL command.
  *
  * This also combines in the EC_CMD_USB_PD_MUX_INFO flags.
- *
- * Version 0 of command is under development
- * TODO(b/167700356): Remove this statement when version 0 is finalized
  */
 #define EC_CMD_TYPEC_STATUS 0x0133
 
@@ -6411,7 +6973,7 @@ struct ec_params_typec_control {
  */
 enum pd_power_role {
 	PD_ROLE_SINK = 0,
-	PD_ROLE_SOURCE = 1
+	PD_ROLE_SOURCE = 1,
 };
 
 /*
@@ -6458,45 +7020,537 @@ enum tcpc_cc_polarity {
 	 * that this will give a hint that other places need to be
 	 * adjusted.
 	 */
-	POLARITY_COUNT
+	POLARITY_COUNT,
 };
 
-#define MODE_DP_PIN_A	BIT(0)
-#define MODE_DP_PIN_B	BIT(1)
-#define MODE_DP_PIN_C	BIT(2)
-#define MODE_DP_PIN_D	BIT(3)
-#define MODE_DP_PIN_E	BIT(4)
-#define MODE_DP_PIN_F	BIT(5)
-#define MODE_DP_PIN_ALL	GENMASK(5, 0)
+#define MODE_DP_PIN_A BIT(0)
+#define MODE_DP_PIN_B BIT(1)
+#define MODE_DP_PIN_C BIT(2)
+#define MODE_DP_PIN_D BIT(3)
+#define MODE_DP_PIN_E BIT(4)
+#define MODE_DP_PIN_F BIT(5)
+#define MODE_DP_PIN_ALL GENMASK(5, 0)
 
-#define PD_STATUS_EVENT_SOP_DISC_DONE		BIT(0)
-#define PD_STATUS_EVENT_SOP_PRIME_DISC_DONE	BIT(1)
+#define PD_STATUS_EVENT_SOP_DISC_DONE BIT(0)
+#define PD_STATUS_EVENT_SOP_PRIME_DISC_DONE BIT(1)
+#define PD_STATUS_EVENT_HARD_RESET BIT(2)
+#define PD_STATUS_EVENT_DISCONNECTED BIT(3)
+#define PD_STATUS_EVENT_MUX_0_SET_DONE BIT(4)
+#define PD_STATUS_EVENT_MUX_1_SET_DONE BIT(5)
+#define PD_STATUS_EVENT_VDM_REQ_REPLY BIT(6)
+#define PD_STATUS_EVENT_VDM_REQ_FAILED BIT(7)
+#define PD_STATUS_EVENT_VDM_ATTENTION BIT(8)
+
+/*
+ * Encode and decode for BCD revision response
+ *
+ * Note: the major revision set is written assuming that the value given is the
+ * Specification Revision from the PD header, which currently only maps to PD
+ * 1.0-3.0 with the major revision being one greater than the binary value.
+ */
+#define PD_STATUS_REV_SET_MAJOR(r) ((r + 1) << 12)
+#define PD_STATUS_REV_GET_MAJOR(r) ((r >> 12) & 0xF)
+#define PD_STATUS_REV_GET_MINOR(r) ((r >> 8) & 0xF)
+
+/*
+ * Encode revision from partner RMDO
+ *
+ * Unlike the specification revision given in the PD header, specification and
+ * version information returned in the revision message data object (RMDO) is
+ * not offset.
+ */
+#define PD_STATUS_RMDO_REV_SET_MAJOR(r) (r << 12)
+#define PD_STATUS_RMDO_REV_SET_MINOR(r) (r << 8)
+#define PD_STATUS_RMDO_VER_SET_MAJOR(r) (r << 4)
+#define PD_STATUS_RMDO_VER_SET_MINOR(r) (r)
+
+/*
+ * Decode helpers for Source and Sink Capability PDOs
+ *
+ * Note: The Power Delivery Specification should be considered the ultimate
+ * source of truth on the decoding of these PDOs
+ */
+#define PDO_TYPE_FIXED (0 << 30)
+#define PDO_TYPE_BATTERY (1 << 30)
+#define PDO_TYPE_VARIABLE (2 << 30)
+#define PDO_TYPE_AUGMENTED (3 << 30)
+#define PDO_TYPE_MASK (3 << 30)
+
+/*
+ * From Table 6-9 and Table 6-14 PD Rev 3.0 Ver 2.0
+ *
+ * <31:30> : Fixed Supply
+ * <29>    : Dual-Role Power
+ * <28>    : SNK/SRC dependent
+ * <27>    : Unconstrained Power
+ * <26>    : USB Communications Capable
+ * <25>    : Dual-Role Data
+ * <24:20> : SNK/SRC dependent
+ * <19:10> : Voltage in 50mV Units
+ * <9:0>   : Maximum Current in 10mA units
+ */
+#define PDO_FIXED_DUAL_ROLE BIT(29)
+#define PDO_FIXED_UNCONSTRAINED BIT(27)
+#define PDO_FIXED_COMM_CAP BIT(26)
+#define PDO_FIXED_DATA_SWAP BIT(25)
+#define PDO_FIXED_FRS_CURR_MASK GENMASK(24, 23) /* Sink Cap only */
+#define PDO_FIXED_VOLTAGE(p) ((p >> 10 & 0x3FF) * 50)
+#define PDO_FIXED_CURRENT(p) ((p & 0x3FF) * 10)
+
+/*
+ * From Table 6-12 and Table 6-16 PD Rev 3.0 Ver 2.0
+ *
+ * <31:30> : Battery
+ * <29:20> : Maximum Voltage in 50mV units
+ * <19:10> : Minimum Voltage in 50mV units
+ * <9:0>   : Maximum Allowable Power in 250mW units
+ */
+#define PDO_BATT_MAX_VOLTAGE(p) ((p >> 20 & 0x3FF) * 50)
+#define PDO_BATT_MIN_VOLTAGE(p) ((p >> 10 & 0x3FF) * 50)
+#define PDO_BATT_MAX_POWER(p) ((p & 0x3FF) * 250)
+
+/*
+ * From Table 6-11 and Table 6-15 PD Rev 3.0 Ver 2.0
+ *
+ * <31:30> : Variable Supply (non-Battery)
+ * <29:20> : Maximum Voltage in 50mV units
+ * <19:10> : Minimum Voltage in 50mV units
+ * <9:0>   : Operational Current in 10mA units
+ */
+#define PDO_VAR_MAX_VOLTAGE(p) ((p >> 20 & 0x3FF) * 50)
+#define PDO_VAR_MIN_VOLTAGE(p) ((p >> 10 & 0x3FF) * 50)
+#define PDO_VAR_MAX_CURRENT(p) ((p & 0x3FF) * 10)
+
+/*
+ * From Table 6-13 and Table 6-17 PD Rev 3.0 Ver 2.0
+ *
+ * Note this type is reserved in PD 2.0, and only one type of APDO is
+ * supported as of the cited version.
+ *
+ * <31:30> : Augmented Power Data Object
+ * <29:28> : Programmable Power Supply
+ * <27>    : PPS Power Limited
+ * <26:25> : Reserved
+ * <24:17> : Maximum Voltage in 100mV increments
+ * <16>    : Reserved
+ * <15:8>  : Minimum Voltage in 100mV increments
+ * <7>     : Reserved
+ * <6:0>   : Maximum Current in 50mA increments
+ */
+#define PDO_AUG_MAX_VOLTAGE(p) ((p >> 17 & 0xFF) * 100)
+#define PDO_AUG_MIN_VOLTAGE(p) ((p >> 8 & 0xFF) * 100)
+#define PDO_AUG_MAX_CURRENT(p) ((p & 0x7F) * 50)
 
 struct ec_params_typec_status {
 	uint8_t port;
 } __ec_align1;
 
-struct ec_response_typec_status {
-	uint8_t pd_enabled;	/* PD communication enabled - bool */
-	uint8_t dev_connected;	/* Device connected - bool */
-	uint8_t sop_connected;	/* Device is SOP PD capable - bool */
-	uint8_t reserved1;	/* Reserved for future use */
+/*
+ * ec_response_typec_status is deprecated. Use ec_response_typec_status_v1.
+ * If you need to support old ECs who speak only v0, use
+ * ec_response_typec_status_v0 instead. They're binary-compatible.
+ */
+struct ec_response_typec_status /* DEPRECATED */ {
+	uint8_t pd_enabled; /* PD communication enabled - bool */
+	uint8_t dev_connected; /* Device connected - bool */
+	uint8_t sop_connected; /* Device is SOP PD capable - bool */
+	uint8_t source_cap_count; /* Number of Source Cap PDOs */
+
+	uint8_t power_role; /* enum pd_power_role */
+	uint8_t data_role; /* enum pd_data_role */
+	uint8_t vconn_role; /* enum pd_vconn_role */
+	uint8_t sink_cap_count; /* Number of Sink Cap PDOs */
+
+	uint8_t polarity; /* enum tcpc_cc_polarity */
+	uint8_t cc_state; /* enum pd_cc_states */
+	uint8_t dp_pin; /* DP pin mode (MODE_DP_IN_[A-E]) */
+	uint8_t mux_state; /* USB_PD_MUX* - encoded mux state */
+
+	char tc_state[32]; /* TC state name */
+
+	uint32_t events; /* PD_STATUS_EVENT bitmask */
+
+	/*
+	 * BCD PD revisions for partners
+	 *
+	 * The format has the PD major revision in the upper nibble, and the PD
+	 * minor revision in the next nibble. The following two nibbles hold the
+	 * major and minor specification version. If a partner does not support
+	 * the Revision message, only the major revision will be given.
+	 * ex. PD Revision 3.2 Version 1.9 would map to 0x3219
+	 *
+	 * PD revision/version will be 0 if no PD device is connected.
+	 */
+	uint16_t sop_revision;
+	uint16_t sop_prime_revision;
+
+	uint32_t source_cap_pdos[7]; /* Max 7 PDOs can be present */
+
+	uint32_t sink_cap_pdos[7]; /* Max 7 PDOs can be present */
+} __ec_align1;
+
+struct cros_ec_typec_status {
+	uint8_t pd_enabled; /* PD communication enabled - bool */
+	uint8_t dev_connected; /* Device connected - bool */
+	uint8_t sop_connected; /* Device is SOP PD capable - bool */
+	uint8_t source_cap_count; /* Number of Source Cap PDOs */
+
+	uint8_t power_role; /* enum pd_power_role */
+	uint8_t data_role; /* enum pd_data_role */
+	uint8_t vconn_role; /* enum pd_vconn_role */
+	uint8_t sink_cap_count; /* Number of Sink Cap PDOs */
+
+	uint8_t polarity; /* enum tcpc_cc_polarity */
+	uint8_t cc_state; /* enum pd_cc_states */
+	uint8_t dp_pin; /* DP pin mode (MODE_DP_IN_[A-E]) */
+	uint8_t mux_state; /* USB_PD_MUX* - encoded mux state */
+
+	char tc_state[32]; /* TC state name */
+
+	uint32_t events; /* PD_STATUS_EVENT bitmask */
+
+	/*
+	 * BCD PD revisions for partners
+	 *
+	 * The format has the PD major revision in the upper nibble, and the PD
+	 * minor revision in the next nibble. The following two nibbles hold the
+	 * major and minor specification version. If a partner does not support
+	 * the Revision message, only the major revision will be given.
+	 * ex. PD Revision 3.2 Version 1.9 would map to 0x3219
+	 *
+	 * PD revision/version will be 0 if no PD device is connected.
+	 */
+	uint16_t sop_revision;
+	uint16_t sop_prime_revision;
+} __ec_align1;
+
+struct ec_response_typec_status_v0 {
+	struct cros_ec_typec_status typec_status;
+	uint32_t source_cap_pdos[7]; /* Max 7 PDOs can be present */
+	uint32_t sink_cap_pdos[7]; /* Max 7 PDOs can be present */
+} __ec_align1;
+
+struct ec_response_typec_status_v1 {
+	struct cros_ec_typec_status typec_status;
+	uint32_t source_cap_pdos[11]; /* Max 11 PDOs can be present */
+	uint32_t sink_cap_pdos[11]; /* Max 11 PDOs can be present */
+} __ec_align1;
+
+/**
+ * Get the number of peripheral charge ports
+ */
+#define EC_CMD_PCHG_COUNT 0x0134
+
+#define EC_PCHG_MAX_PORTS 8
+
+struct ec_response_pchg_count {
+	uint8_t port_count;
+} __ec_align1;
+
+/**
+ * Get the status of a peripheral charge port
+ */
+#define EC_CMD_PCHG 0x0135
+
+/* For v1 and v2 */
+struct ec_params_pchg {
+	uint8_t port;
+} __ec_align1;
+
+struct ec_params_pchg_v3 {
+	uint8_t port;
+	/* Below are new in v3. */
+	uint8_t reserved1;
+	uint8_t reserved2;
+	uint8_t reserved3;
+	/* Errors acked by the host (thus to be cleared) */
+	uint32_t error;
+} __ec_align1;
+
+/* For v1 */
+struct ec_response_pchg {
+	uint32_t error; /* enum pchg_error */
+	uint8_t state; /* enum pchg_state state */
+	uint8_t battery_percentage;
+	uint8_t unused0;
+	uint8_t unused1;
+	/* Fields added in version 1 */
+	uint32_t fw_version;
+	uint32_t dropped_event_count;
+} __ec_align4;
+
+/* For v2 and v3 */
+struct ec_response_pchg_v2 {
+	uint32_t error; /* enum pchg_error */
+	uint8_t state; /* enum pchg_state state */
+	uint8_t battery_percentage;
+	uint8_t unused0;
+	uint8_t unused1;
+	/* Fields added in version 1 */
+	uint32_t fw_version;
+	uint32_t dropped_event_count;
+	/* Fields added in version 2 */
+	uint32_t dropped_host_event_count;
+} __ec_align4;
+
+enum pchg_state {
+	/* Charger is reset and not initialized. */
+	PCHG_STATE_RESET = 0,
+	/* Charger is initialized or disabled. */
+	PCHG_STATE_INITIALIZED,
+	/* Charger is enabled and ready to detect a device. */
+	PCHG_STATE_ENABLED,
+	/* Device is in proximity. */
+	PCHG_STATE_DETECTED,
+	/* Device is being charged. */
+	PCHG_STATE_CHARGING,
+	/* Device is fully charged. It implies DETECTED (& not charging). */
+	PCHG_STATE_FULL,
+	/* In download (a.k.a. firmware update) mode */
+	PCHG_STATE_DOWNLOAD,
+	/* In download mode. Ready for receiving data. */
+	PCHG_STATE_DOWNLOADING,
+	/* Device is ready for data communication. */
+	PCHG_STATE_CONNECTED,
+	/* Charger is in Built-In Self Test mode. */
+	PCHG_STATE_BIST,
+	/* Put no more entry below */
+	PCHG_STATE_COUNT,
+};
+
+/* clang-format off */
+#define EC_PCHG_STATE_TEXT                                \
+	{                                                 \
+		[PCHG_STATE_RESET] = "RESET",             \
+		[PCHG_STATE_INITIALIZED] = "INITIALIZED", \
+		[PCHG_STATE_ENABLED] = "ENABLED",         \
+		[PCHG_STATE_DETECTED] = "DETECTED",       \
+		[PCHG_STATE_CHARGING] = "CHARGING",       \
+		[PCHG_STATE_FULL] = "FULL",               \
+		[PCHG_STATE_DOWNLOAD] = "DOWNLOAD",       \
+		[PCHG_STATE_DOWNLOADING] = "DOWNLOADING", \
+		[PCHG_STATE_CONNECTED] = "CONNECTED",     \
+		[PCHG_STATE_BIST] = "BIST",               \
+	}
+/* clang-format on */
+
+/**
+ * Update firmware of peripheral chip
+ */
+#define EC_CMD_PCHG_UPDATE 0x0136
+
+/* Port number is encoded in bit[28:31]. */
+#define EC_MKBP_PCHG_PORT_SHIFT 28
+/* Utility macros for converting MKBP event <-> port number. */
+#define EC_MKBP_PCHG_EVENT_TO_PORT(e) (((e) >> EC_MKBP_PCHG_PORT_SHIFT) & 0xf)
+#define EC_MKBP_PCHG_PORT_TO_EVENT(p) ((p) << EC_MKBP_PCHG_PORT_SHIFT)
+/* Utility macro for extracting event bits. */
+#define EC_MKBP_PCHG_EVENT_MASK(e) ((e)&GENMASK(EC_MKBP_PCHG_PORT_SHIFT - 1, 0))
+
+#define EC_MKBP_PCHG_UPDATE_OPENED BIT(0)
+#define EC_MKBP_PCHG_WRITE_COMPLETE BIT(1)
+#define EC_MKBP_PCHG_UPDATE_CLOSED BIT(2)
+#define EC_MKBP_PCHG_UPDATE_ERROR BIT(3)
+#define EC_MKBP_PCHG_DEVICE_EVENT BIT(4)
+
+enum ec_pchg_update_cmd {
+	/* Reset chip to normal mode. */
+	EC_PCHG_UPDATE_CMD_RESET_TO_NORMAL = 0,
+	/* Reset and put a chip in update (a.k.a. download) mode. */
+	EC_PCHG_UPDATE_CMD_OPEN,
+	/* Write a block of data containing FW image. */
+	EC_PCHG_UPDATE_CMD_WRITE,
+	/* Close update session. */
+	EC_PCHG_UPDATE_CMD_CLOSE,
+	/* Reset chip (without mode change). */
+	EC_PCHG_UPDATE_CMD_RESET,
+	/* Enable pass-through mode. */
+	EC_PCHG_UPDATE_CMD_ENABLE_PASSTHRU,
+	/* End of commands */
+	EC_PCHG_UPDATE_CMD_COUNT,
+};
+
+struct ec_params_pchg_update {
+	/* PCHG port number */
+	uint8_t port;
+	/* enum ec_pchg_update_cmd */
+	uint8_t cmd;
+	/* Padding */
+	uint8_t reserved0;
+	uint8_t reserved1;
+	/* Version of new firmware */
+	uint32_t version;
+	/* CRC32 of new firmware */
+	uint32_t crc32;
+	/* Address in chip memory where <data> is written to */
+	uint32_t addr;
+	/* Size of <data> */
+	uint32_t size;
+	/* Partial data of new firmware */
+	uint8_t data[];
+} __ec_align4;
+
+BUILD_ASSERT(EC_PCHG_UPDATE_CMD_COUNT <
+	     BIT(sizeof(((struct ec_params_pchg_update *)0)->cmd) * 8));
+
+struct ec_response_pchg_update {
+	/* Block size */
+	uint32_t block_size;
+} __ec_align4;
+
+#define EC_CMD_DISPLAY_SOC 0x0137
+
+struct ec_response_display_soc {
+	/* Display charge in 10ths of a % (1000=100.0%) */
+	int16_t display_soc;
+	/* Full factor in 10ths of a % (1000=100.0%) */
+	int16_t full_factor;
+	/* Shutdown SoC in 10ths of a % (1000=100.0%) */
+	int16_t shutdown_soc;
+} __ec_align2;
+
+#define EC_CMD_SET_BASE_STATE 0x0138
+
+struct ec_params_set_base_state {
+	uint8_t cmd; /* enum ec_set_base_state_cmd */
+} __ec_align1;
+
+enum ec_set_base_state_cmd {
+	EC_SET_BASE_STATE_DETACH = 0,
+	EC_SET_BASE_STATE_ATTACH,
+	EC_SET_BASE_STATE_RESET,
+};
+
+#define EC_CMD_I2C_CONTROL 0x0139
+
+/* Subcommands for I2C control */
+
+enum ec_i2c_control_command {
+	EC_I2C_CONTROL_GET_SPEED,
+	EC_I2C_CONTROL_SET_SPEED,
+};
+
+#define EC_I2C_CONTROL_SPEED_UNKNOWN 0
+
+struct ec_params_i2c_control {
+	uint8_t port; /* I2C port number */
+	uint8_t cmd; /* enum ec_i2c_control_command */
+	union {
+		uint16_t speed_khz;
+	} cmd_params;
+} __ec_align_size1;
+
+struct ec_response_i2c_control {
+	union {
+		uint16_t speed_khz;
+	} cmd_response;
+} __ec_align_size1;
+
+#define EC_CMD_RGBKBD_SET_COLOR 0x013A
+#define EC_CMD_RGBKBD 0x013B
+
+#define EC_RGBKBD_MAX_KEY_COUNT 128
+#define EC_RGBKBD_MAX_RGB_COLOR 0xFFFFFF
+#define EC_RGBKBD_MAX_SCALE 0xFF
+
+enum rgbkbd_state {
+	/* RGB keyboard is reset and not initialized. */
+	RGBKBD_STATE_RESET = 0,
+	/* RGB keyboard is initialized but not enabled. */
+	RGBKBD_STATE_INITIALIZED,
+	/* RGB keyboard is disabled. */
+	RGBKBD_STATE_DISABLED,
+	/* RGB keyboard is enabled and ready to receive a command. */
+	RGBKBD_STATE_ENABLED,
 
-	uint8_t power_role;	/* enum pd_power_role */
-	uint8_t data_role;	/* enum pd_data_role */
-	uint8_t vconn_role;	/* enum pd_vconn_role */
-	uint8_t reserved2;	/* Reserved for future use */
+	/* Put no more entry below */
+	RGBKBD_STATE_COUNT,
+};
+
+enum ec_rgbkbd_subcmd {
+	EC_RGBKBD_SUBCMD_CLEAR = 1,
+	EC_RGBKBD_SUBCMD_DEMO = 2,
+	EC_RGBKBD_SUBCMD_SET_SCALE = 3,
+	EC_RGBKBD_SUBCMD_GET_CONFIG = 4,
+	EC_RGBKBD_SUBCMD_COUNT
+};
+
+enum ec_rgbkbd_demo {
+	EC_RGBKBD_DEMO_OFF = 0,
+	EC_RGBKBD_DEMO_FLOW = 1,
+	EC_RGBKBD_DEMO_DOT = 2,
+	EC_RGBKBD_DEMO_COUNT,
+};
+
+BUILD_ASSERT(EC_RGBKBD_DEMO_COUNT <= 255);
+
+enum ec_rgbkbd_type {
+	EC_RGBKBD_TYPE_UNKNOWN = 0,
+	EC_RGBKBD_TYPE_PER_KEY = 1, /* e.g. Vell */
+	EC_RGBKBD_TYPE_FOUR_ZONES_40_LEDS = 2, /* e.g. Taniks */
+	EC_RGBKBD_TYPE_FOUR_ZONES_12_LEDS = 3, /* e.g. Osiris */
+	EC_RGBKBD_TYPE_FOUR_ZONES_4_LEDS = 4, /* e.g. Mithrax */
+	EC_RGBKBD_TYPE_COUNT,
+};
 
-	uint8_t polarity;	/* enum tcpc_cc_polarity */
-	uint8_t cc_state;	/* enum pd_cc_states */
-	uint8_t dp_pin;		/* DP pin mode (MODE_DP_IN_[A-E]) */
-	uint8_t mux_state;	/* USB_PD_MUX* - encoded USB mux state */
+struct ec_rgbkbd_set_scale {
+	uint8_t key;
+	struct rgb_s scale;
+};
+
+struct ec_params_rgbkbd {
+	uint8_t subcmd; /* Sub-command (enum ec_rgbkbd_subcmd) */
+	union {
+		struct rgb_s color; /* EC_RGBKBD_SUBCMD_CLEAR */
+		uint8_t demo; /* EC_RGBKBD_SUBCMD_DEMO */
+		struct ec_rgbkbd_set_scale set_scale;
+	};
+} __ec_align1;
 
-	char tc_state[32];	/* TC state name */
+struct ec_response_rgbkbd {
+	/*
+	 * RGBKBD type supported by the device.
+	 */
 
-	uint32_t events;	/* PD_STATUS_EVENT bitmask */
+	uint8_t rgbkbd_type; /* enum ec_rgbkbd_type */
+} __ec_align1;
 
-	/* TODO(b/167700356): Add revisions and source cap PDOs */
+struct ec_params_rgbkbd_set_color {
+	/* Specifies the starting key ID whose color is being changed. */
+	uint8_t start_key;
+	/* Specifies # of elements in <color>. */
+	uint8_t length;
+	/* RGB color data array of length up to MAX_KEY_COUNT. */
+	struct rgb_s color[];
+} __ec_align1;
+
+/*
+ * Gather the response to the most recent VDM REQ from the AP, as well
+ * as popping the oldest VDM:Attention from the DPM queue
+ */
+#define EC_CMD_TYPEC_VDM_RESPONSE 0x013C
+
+struct ec_params_typec_vdm_response {
+	uint8_t port;
+} __ec_align1;
+
+struct ec_response_typec_vdm_response {
+	/* Number of 32-bit fields filled in */
+	uint8_t vdm_data_objects;
+	/* Partner to address - see enum typec_partner_type */
+	uint8_t partner_type;
+	/* enum ec_status describing VDM response */
+	uint16_t vdm_response_err;
+	/* VDM data, including VDM header */
+	uint32_t vdm_response[VDO_MAX_SIZE];
+	/* Number of 32-bit Attention fields filled in */
+	uint8_t vdm_attention_objects;
+	/* Number of remaining messages to consume */
+	uint8_t vdm_attention_left;
+	/* Reserved */
+	uint16_t reserved1;
+	/* VDM:Attention contents */
+	uint32_t vdm_attention[2];
 } __ec_align1;
 
 /*****************************************************************************/
@@ -6518,71 +7572,72 @@ struct ec_response_typec_status {
 #define EC_FP_FLAG_NOT_COMPLETE 0x1
 
 struct ec_params_fp_passthru {
-	uint16_t len;		/* Number of bytes to write then read */
-	uint16_t flags;		/* EC_FP_FLAG_xxx */
-	uint8_t data[];		/* Data to send */
+	uint16_t len; /* Number of bytes to write then read */
+	uint16_t flags; /* EC_FP_FLAG_xxx */
+	uint8_t data[]; /* Data to send */
 } __ec_align2;
 
 /* Configure the Fingerprint MCU behavior */
 #define EC_CMD_FP_MODE 0x0402
 
 /* Put the sensor in its lowest power mode */
-#define FP_MODE_DEEPSLEEP      BIT(0)
+#define FP_MODE_DEEPSLEEP BIT(0)
 /* Wait to see a finger on the sensor */
-#define FP_MODE_FINGER_DOWN    BIT(1)
+#define FP_MODE_FINGER_DOWN BIT(1)
 /* Poll until the finger has left the sensor */
-#define FP_MODE_FINGER_UP      BIT(2)
+#define FP_MODE_FINGER_UP BIT(2)
 /* Capture the current finger image */
-#define FP_MODE_CAPTURE        BIT(3)
+#define FP_MODE_CAPTURE BIT(3)
 /* Finger enrollment session on-going */
 #define FP_MODE_ENROLL_SESSION BIT(4)
 /* Enroll the current finger image */
-#define FP_MODE_ENROLL_IMAGE   BIT(5)
+#define FP_MODE_ENROLL_IMAGE BIT(5)
 /* Try to match the current finger image */
-#define FP_MODE_MATCH          BIT(6)
+#define FP_MODE_MATCH BIT(6)
 /* Reset and re-initialize the sensor. */
-#define FP_MODE_RESET_SENSOR   BIT(7)
+#define FP_MODE_RESET_SENSOR BIT(7)
 /* Sensor maintenance for dead pixels. */
 #define FP_MODE_SENSOR_MAINTENANCE BIT(8)
 /* special value: don't change anything just read back current mode */
-#define FP_MODE_DONT_CHANGE    BIT(31)
-
-#define FP_VALID_MODES (FP_MODE_DEEPSLEEP      | \
-			FP_MODE_FINGER_DOWN    | \
-			FP_MODE_FINGER_UP      | \
-			FP_MODE_CAPTURE        | \
-			FP_MODE_ENROLL_SESSION | \
-			FP_MODE_ENROLL_IMAGE   | \
-			FP_MODE_MATCH          | \
-			FP_MODE_RESET_SENSOR   | \
-			FP_MODE_SENSOR_MAINTENANCE | \
-			FP_MODE_DONT_CHANGE)
+#define FP_MODE_DONT_CHANGE BIT(31)
+
+#define FP_VALID_MODES                                                       \
+	(FP_MODE_DEEPSLEEP | FP_MODE_FINGER_DOWN | FP_MODE_FINGER_UP |       \
+	 FP_MODE_CAPTURE | FP_MODE_ENROLL_SESSION | FP_MODE_ENROLL_IMAGE |   \
+	 FP_MODE_MATCH | FP_MODE_RESET_SENSOR | FP_MODE_SENSOR_MAINTENANCE | \
+	 FP_MODE_DONT_CHANGE)
 
 /* Capture types defined in bits [30..28] */
 #define FP_MODE_CAPTURE_TYPE_SHIFT 28
-#define FP_MODE_CAPTURE_TYPE_MASK  (0x7 << FP_MODE_CAPTURE_TYPE_SHIFT)
-/*
- * This enum must remain ordered, if you add new values you must ensure that
- * FP_CAPTURE_TYPE_MAX is still the last one.
+#define FP_MODE_CAPTURE_TYPE_MASK (0x7 << FP_MODE_CAPTURE_TYPE_SHIFT)
+/**
+ * enum fp_capture_type - Specifies the "mode" when capturing images.
+ *
+ * @FP_CAPTURE_VENDOR_FORMAT: Capture 1-3 images and choose the best quality
+ * image (produces 'frame_size' bytes)
+ * @FP_CAPTURE_SIMPLE_IMAGE: Simple raw image capture (produces width x height x
+ * bpp bits)
+ * @FP_CAPTURE_PATTERN0: Self test pattern (e.g. checkerboard)
+ * @FP_CAPTURE_PATTERN1: Self test pattern (e.g. inverted checkerboard)
+ * @FP_CAPTURE_QUALITY_TEST: Capture for Quality test with fixed contrast
+ * @FP_CAPTURE_RESET_TEST: Capture for pixel reset value test
+ * @FP_CAPTURE_TYPE_MAX: End of enum
+ *
+ * @note This enum must remain ordered, if you add new values you must ensure
+ * that FP_CAPTURE_TYPE_MAX is still the last one.
  */
 enum fp_capture_type {
-	/* Full blown vendor-defined capture (produces 'frame_size' bytes) */
 	FP_CAPTURE_VENDOR_FORMAT = 0,
-	/* Simple raw image capture (produces width x height x bpp bits) */
 	FP_CAPTURE_SIMPLE_IMAGE = 1,
-	/* Self test pattern (e.g. checkerboard) */
 	FP_CAPTURE_PATTERN0 = 2,
-	/* Self test pattern (e.g. inverted checkerboard) */
 	FP_CAPTURE_PATTERN1 = 3,
-	/* Capture for Quality test with fixed contrast */
 	FP_CAPTURE_QUALITY_TEST = 4,
-	/* Capture for pixel reset value test */
 	FP_CAPTURE_RESET_TEST = 5,
 	FP_CAPTURE_TYPE_MAX,
 };
 /* Extracts the capture type from the sensor 'mode' word */
-#define FP_CAPTURE_TYPE(mode) (((mode) & FP_MODE_CAPTURE_TYPE_MASK) \
-				       >> FP_MODE_CAPTURE_TYPE_SHIFT)
+#define FP_CAPTURE_TYPE(mode) \
+	(((mode)&FP_MODE_CAPTURE_TYPE_MASK) >> FP_MODE_CAPTURE_TYPE_SHIFT)
 
 struct ec_params_fp_mode {
 	uint32_t mode; /* as defined by FP_MODE_ constants */
@@ -6596,15 +7651,15 @@ struct ec_response_fp_mode {
 #define EC_CMD_FP_INFO 0x0403
 
 /* Number of dead pixels detected on the last maintenance */
-#define FP_ERROR_DEAD_PIXELS(errors) ((errors) & 0x3FF)
+#define FP_ERROR_DEAD_PIXELS(errors) ((errors)&0x3FF)
 /* Unknown number of dead pixels detected on the last maintenance */
 #define FP_ERROR_DEAD_PIXELS_UNKNOWN (0x3FF)
 /* No interrupt from the sensor */
-#define FP_ERROR_NO_IRQ    BIT(12)
+#define FP_ERROR_NO_IRQ BIT(12)
 /* SPI communication error */
-#define FP_ERROR_SPI_COMM  BIT(13)
+#define FP_ERROR_SPI_COMM BIT(13)
 /* Invalid sensor Hardware ID */
-#define FP_ERROR_BAD_HWID  BIT(14)
+#define FP_ERROR_BAD_HWID BIT(14)
 /* Sensor initialization failed */
 #define FP_ERROR_INIT_FAIL BIT(15)
 
@@ -6637,8 +7692,8 @@ struct ec_response_fp_info {
 	uint16_t bpp;
 	uint16_t errors; /* see FP_ERROR_ flags above */
 	/* Template/finger current information */
-	uint32_t template_size;  /* max template size in bytes */
-	uint16_t template_max;   /* maximum number of fingers/templates */
+	uint32_t template_size; /* max template size in bytes */
+	uint16_t template_max; /* maximum number of fingers/templates */
 	uint16_t template_valid; /* number of valid fingers/templates */
 	uint32_t template_dirty; /* bitmap of templates with MCU side changes */
 	uint32_t template_version; /* version of the template format */
@@ -6648,13 +7703,13 @@ struct ec_response_fp_info {
 #define EC_CMD_FP_FRAME 0x0404
 
 /* constants defining the 'offset' field which also contains the frame index */
-#define FP_FRAME_INDEX_SHIFT       28
+#define FP_FRAME_INDEX_SHIFT 28
 /* Frame buffer where the captured image is stored */
-#define FP_FRAME_INDEX_RAW_IMAGE    0
+#define FP_FRAME_INDEX_RAW_IMAGE 0
 /* First frame buffer holding a template */
-#define FP_FRAME_INDEX_TEMPLATE     1
+#define FP_FRAME_INDEX_TEMPLATE 1
 #define FP_FRAME_GET_BUFFER_INDEX(offset) ((offset) >> FP_FRAME_INDEX_SHIFT)
-#define FP_FRAME_OFFSET_MASK       0x0FFFFFFF
+#define FP_FRAME_OFFSET_MASK 0x0FFFFFFF
 
 /* Version of the format of the encrypted templates. */
 #define FP_TEMPLATE_FORMAT_VERSION 4
@@ -6721,14 +7776,14 @@ enum fp_context_action {
 
 /* Version 1 of the command is "asynchronous". */
 struct ec_params_fp_context_v1 {
-	uint8_t action;		/**< enum fp_context_action */
-	uint8_t reserved[3];    /**< padding for alignment */
+	uint8_t action; /**< enum fp_context_action */
+	uint8_t reserved[3]; /**< padding for alignment */
 	uint32_t userid[FP_CONTEXT_USERID_WORDS];
 } __ec_align4;
 
 #define EC_CMD_FP_STATS 0x0407
 
-#define FPSTATS_CAPTURE_INV  BIT(0)
+#define FPSTATS_CAPTURE_INV BIT(0)
 #define FPSTATS_MATCHING_INV BIT(1)
 
 struct ec_response_fp_stats {
@@ -6778,6 +7833,65 @@ struct ec_response_fp_read_match_secret {
 	uint8_t positive_match_secret[FP_POSITIVE_MATCH_SECRET_BYTES];
 } __ec_align4;
 
+#define FP_ELLIPTIC_CURVE_PUBLIC_KEY_POINT_LEN 32
+
+struct fp_elliptic_curve_public_key {
+	uint8_t x[FP_ELLIPTIC_CURVE_PUBLIC_KEY_POINT_LEN];
+	uint8_t y[FP_ELLIPTIC_CURVE_PUBLIC_KEY_POINT_LEN];
+} __ec_align4;
+
+#define FP_AES_KEY_ENC_METADATA_VERSION 1
+#define FP_AES_KEY_NONCE_BYTES 12
+#define FP_AES_KEY_ENCRYPTION_SALT_BYTES 16
+#define FP_AES_KEY_TAG_BYTES 16
+
+struct fp_auth_command_encryption_metadata {
+	/* Version of the structure format */
+	uint16_t struct_version;
+	/* Reserved bytes, set to 0. */
+	uint16_t reserved;
+	/*
+	 * The salt is *only* ever used for key derivation. The nonce is unique,
+	 * a different one is used for every message.
+	 */
+	uint8_t nonce[FP_AES_KEY_NONCE_BYTES];
+	uint8_t encryption_salt[FP_AES_KEY_ENCRYPTION_SALT_BYTES];
+	uint8_t tag[FP_AES_KEY_TAG_BYTES];
+} __ec_align4;
+
+#define FP_ELLIPTIC_CURVE_PRIVATE_KEY_LEN 32
+#define FP_ELLIPTIC_CURVE_PUBLIC_KEY_IV_LEN 16
+
+struct fp_encrypted_private_key {
+	struct fp_auth_command_encryption_metadata info;
+	uint8_t data[FP_ELLIPTIC_CURVE_PRIVATE_KEY_LEN];
+} __ec_align4;
+
+#define EC_CMD_FP_ESTABLISH_PAIRING_KEY_KEYGEN 0x0410
+
+struct ec_response_fp_establish_pairing_key_keygen {
+	struct fp_elliptic_curve_public_key pubkey;
+	struct fp_encrypted_private_key encrypted_private_key;
+} __ec_align4;
+
+#define FP_PAIRING_KEY_LEN 32
+
+struct ec_fp_encrypted_pairing_key {
+	struct fp_auth_command_encryption_metadata info;
+	uint8_t data[FP_PAIRING_KEY_LEN];
+} __ec_align4;
+
+#define EC_CMD_FP_ESTABLISH_PAIRING_KEY_WRAP 0x0411
+
+struct ec_params_fp_establish_pairing_key_wrap {
+	struct fp_elliptic_curve_public_key peers_pubkey;
+	struct fp_encrypted_private_key encrypted_private_key;
+} __ec_align4;
+
+struct ec_response_fp_establish_pairing_key_wrap {
+	struct ec_fp_encrypted_pairing_key encrypted_pairing_key;
+} __ec_align4;
+
 /*****************************************************************************/
 /* Touchpad MCU commands: range 0x0500-0x05FF */
 
@@ -6844,6 +7958,54 @@ struct ec_response_battery_static_info {
 	uint32_t cycle_count;
 } __ec_align4;
 
+/**
+ * struct ec_response_battery_static_info_v1 - hostcmd v1 battery static info
+ * Equivalent to struct ec_response_battery_static_info, but with longer
+ * strings.
+ * @design_capacity: battery design capacity (in mAh)
+ * @design_voltage: battery design voltage (in mV)
+ * @cycle_count: battery cycle count
+ * @manufacturer_ext: battery manufacturer string
+ * @model_ext: battery model string
+ * @serial_ext: battery serial number string
+ * @type_ext: battery type string
+ */
+struct ec_response_battery_static_info_v1 {
+	uint16_t design_capacity;
+	uint16_t design_voltage;
+	uint32_t cycle_count;
+	char manufacturer_ext[12];
+	char model_ext[12];
+	char serial_ext[12];
+	char type_ext[12];
+} __ec_align4;
+
+/**
+ * struct ec_response_battery_static_info_v2 - hostcmd v2 battery static info
+ *
+ * Equivalent to struct ec_response_battery_static_info, but with strings
+ * further lengthened (relative to v1) to accommodate the maximum string length
+ * permitted by the Smart Battery Data Specification revision 1.1 and fields
+ * renamed to better match that specification.
+ *
+ * @design_capacity: battery design capacity (in mAh)
+ * @design_voltage: battery design voltage (in mV)
+ * @cycle_count: battery cycle count
+ * @manufacturer: battery manufacturer string
+ * @device_name: battery model string
+ * @serial: battery serial number string
+ * @chemistry: battery type string
+ */
+struct ec_response_battery_static_info_v2 {
+	uint16_t design_capacity;
+	uint16_t design_voltage;
+	uint32_t cycle_count;
+	char manufacturer[32];
+	char device_name[32];
+	char serial[32];
+	char chemistry[32];
+} __ec_align4;
+
 /*
  * Get battery dynamic information, i.e. information that is likely to change
  * every time it is read.
@@ -6879,7 +8041,7 @@ struct ec_response_battery_dynamic_info {
 } __ec_align2;
 
 /*
- * Control charger chip. Used to control charger chip on the slave.
+ * Control charger chip. Used to control charger chip on the peripheral.
  */
 #define EC_CMD_CHARGER_CONTROL 0x0602
 
@@ -6899,6 +8061,31 @@ struct ec_params_charger_control {
 	uint8_t allow_charging;
 } __ec_align_size1;
 
+/* Get ACK from the USB-C SS muxes */
+#define EC_CMD_USB_PD_MUX_ACK 0x0603
+
+struct ec_params_usb_pd_mux_ack {
+	uint8_t port; /* USB-C port number */
+} __ec_align1;
+
+/* Get boot time */
+#define EC_CMD_GET_BOOT_TIME 0x0604
+
+enum boot_time_param {
+	ARAIL = 0,
+	RSMRST,
+	ESPIRST,
+	PLTRST_LOW,
+	PLTRST_HIGH,
+	EC_CUR_TIME,
+	RESET_CNT,
+};
+
+struct ec_response_get_boot_time {
+	uint64_t timestamp[RESET_CNT];
+	uint16_t cnt;
+} __ec_align4;
+
 /*****************************************************************************/
 /*
  * Reserve a range of host commands for board-specific, experimental, or
@@ -6969,14 +8156,14 @@ struct ec_params_charger_control {
  * switch to the new names soon, as the old names may not be carried forward
  * forever.
  */
-#define EC_HOST_PARAM_SIZE      EC_PROTO2_MAX_PARAM_SIZE
-#define EC_LPC_ADDR_OLD_PARAM   EC_HOST_CMD_REGION1
-#define EC_OLD_PARAM_SIZE       EC_HOST_CMD_REGION_SIZE
+#define EC_HOST_PARAM_SIZE EC_PROTO2_MAX_PARAM_SIZE
+#define EC_LPC_ADDR_OLD_PARAM EC_HOST_CMD_REGION1
+#define EC_OLD_PARAM_SIZE EC_HOST_CMD_REGION_SIZE
 
-#endif  /* !__ACPI__ */
+#endif /* !__ACPI__ */
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif  /* __CROS_EC_EC_COMMANDS_H */
+#endif /* __CROS_EC_EC_COMMANDS_H */
diff --git a/include/ec_ec_comm_client.h b/include/ec_ec_comm_client.h
new file mode 100644
index 0000000000..57c599a365
--- /dev/null
+++ b/include/ec_ec_comm_client.h
@@ -0,0 +1,58 @@
+/* Copyright 2017 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * EC-EC communication, functions for client.
+ */
+
+#ifndef EC_EC_COMM_CLIENT_H_
+#define EC_EC_COMM_CLIENT_H_
+
+#include "config.h"
+
+#include <stdint.h>
+
+/**
+ * Sends EC_CMD_BATTERY_GET_DYNAMIC command to server, and writes the
+ * battery dynamic information into battery_dynamic[BATT_IDX_BASE].
+ *
+ * Leaves battery_dynamic[BATT_IDX_BASE] intact on error: it is the callers
+ * responsibility to clear the data or ignore it.
+
+ * @return EC_RES_SUCCESS on success, EC_RES_ERROR on communication error,
+ * else forwards the error code from the server.
+ */
+int ec_ec_client_base_get_dynamic_info(void);
+
+/**
+ * Sends EC_CMD_BATTERY_GET_STATIC command to server, and writes the
+ * battery static information into battery_static[BATT_IDX_BASE].
+ *
+ * Leaves battery_static[BATT_IDX_BASE] intact on error: it is the callers
+ * responsibility to clear the data or ignore it.
+ *
+ * @return EC_RES_SUCCESS on success, EC_RES_ERROR on communication error,
+ * else forwards the error code from the server.
+ */
+int ec_ec_client_base_get_static_info(void);
+
+/**
+ * Sends EC_CMD_CHARGER_CONTROL command to server, with the given parameters
+ * (see ec_commands.h/ec_params_charger_control for description).
+ *
+ * @return EC_RES_SUCCESS on success, EC_RES_ERROR on communication error,
+ * else forwards the error code from the server.
+ */
+int ec_ec_client_base_charge_control(int max_current, int otg_voltage,
+				     int allow_charging);
+
+/**
+ * Sends EC_CMD_REBOOT_EC command to server, with EC_REBOOT_HIBERNATE parameter.
+ *
+ * @return EC_RES_ERROR on communication error (should always be the case if the
+ * server successfully hibernates, as it will not be able to write back the
+ * response, else forwards the error code from the server.
+ */
+int ec_ec_client_hibernate(void);
+
+#endif /* EC_EC_COMM_CLIENT_H_ */
diff --git a/include/ec_ec_comm_master.h b/include/ec_ec_comm_master.h
deleted file mode 100644
index ccd46a9bc2..0000000000
--- a/include/ec_ec_comm_master.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * EC-EC communication, functions for master.
- */
-
-#ifndef EC_EC_COMM_MASTER_H_
-#define EC_EC_COMM_MASTER_H_
-
-#include <stdint.h>
-#include "config.h"
-
-/**
- * Sends EC_CMD_BATTERY_GET_DYNAMIC command to slave, and writes the
- * battery dynamic information into battery_dynamic[BATT_IDX_BASE].
- *
- * Leaves battery_dynamic[BATT_IDX_BASE] intact on error: it is the callers
- * responsibility to clear the data or ignore it.
-
- * @return EC_RES_SUCCESS on success, EC_RES_ERROR on communication error,
- * else forwards the error code from the slave.
- */
-int ec_ec_master_base_get_dynamic_info(void);
-
-/**
- * Sends EC_CMD_BATTERY_GET_STATIC command to slave, and writes the
- * battery static information into battery_static[BATT_IDX_BASE].
- *
- * Leaves battery_static[BATT_IDX_BASE] intact on error: it is the callers
- * responsibility to clear the data or ignore it.
- *
- * @return EC_RES_SUCCESS on success, EC_RES_ERROR on communication error,
- * else forwards the error code from the slave.
- */
-int ec_ec_master_base_get_static_info(void);
-
-/**
- * Sends EC_CMD_CHARGER_CONTROL command to slave, with the given parameters
- * (see ec_commands.h/ec_params_charger_control for description).
- *
- * @return EC_RES_SUCCESS on success, EC_RES_ERROR on communication error,
- * else forwards the error code from the slave.
- */
-int ec_ec_master_base_charge_control(int max_current,
-				     int otg_voltage,
-				     int allow_charging);
-
-/**
- * Sends EC_CMD_REBOOT_EC command to slave, with EC_REBOOT_HIBERNATE parameter.
- *
- * @return EC_RES_ERROR on communication error (should always be the case if the
- * slave successfully hibernates, as it will not be able to write back the
- * response, else forwards the error code from the slave.
- */
-int ec_ec_master_hibernate(void);
-
-#endif /* EC_EC_COMM_MASTER_H_ */
diff --git a/include/ec_ec_comm_server.h b/include/ec_ec_comm_server.h
new file mode 100644
index 0000000000..9728e021a8
--- /dev/null
+++ b/include/ec_ec_comm_server.h
@@ -0,0 +1,21 @@
+/* Copyright 2017 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * EC-EC communication, functions and definition for server.
+ */
+
+#ifndef EC_EC_COMM_SERVER_H_
+#define EC_EC_COMM_SERVER_H_
+
+#include "consumer.h"
+#include "queue.h"
+
+#include <stdint.h>
+
+extern struct queue const ec_ec_comm_server_input;
+extern struct queue const ec_ec_comm_server_output;
+
+void ec_ec_comm_server_written(struct consumer const *consumer, size_t count);
+
+#endif /* EC_EC_COMM_SERVER_H_ */
diff --git a/include/ec_ec_comm_slave.h b/include/ec_ec_comm_slave.h
deleted file mode 100644
index 19e1912d94..0000000000
--- a/include/ec_ec_comm_slave.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * EC-EC communication, functions and definition for slave.
- */
-
-#ifndef EC_EC_COMM_SLAVE_H_
-#define EC_EC_COMM_SLAVE_H_
-
-#include <stdint.h>
-#include "consumer.h"
-#include "queue.h"
-
-extern struct queue const ec_ec_comm_slave_input;
-extern struct queue const ec_ec_comm_slave_output;
-
-void ec_ec_comm_slave_written(struct consumer const *consumer, size_t count);
-
-#endif /* EC_EC_COMM_SLAVE_H_ */
diff --git a/include/eeprom.h b/include/eeprom.h
index 368491c959..41e464c1f5 100644
--- a/include/eeprom.h
+++ b/include/eeprom.h
@@ -1,4 +1,4 @@
-/* Copyright 2011 The Chromium OS Authors. All rights reserved.
+/* Copyright 2011 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -52,4 +52,4 @@ int eeprom_write(int block, int offset, int size, const char *data);
  */
 int eeprom_hide(int block);
 
-#endif  /* __CROS_EC_EEPROM_H */
+#endif /* __CROS_EC_EEPROM_H */
diff --git a/include/espi.h b/include/espi.h
index 6d4de73330..03e7025c27 100644
--- a/include/espi.h
+++ b/include/espi.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,29 +14,29 @@
 enum espi_vw_signal {
 	/* The first valid VW signal is 0x2000 */
 	VW_SIGNAL_START = IOEX_LIMIT + 1,
-	VW_SLP_S3_L = VW_SIGNAL_START,	/* index 02h (In)  */
+	VW_SLP_S3_L = VW_SIGNAL_START, /* index 02h (In)  */
 	VW_SLP_S4_L,
 	VW_SLP_S5_L,
-	VW_SUS_STAT_L,			/* index 03h (In)  */
+	VW_SUS_STAT_L, /* index 03h (In)  */
 	VW_PLTRST_L,
 	VW_OOB_RST_WARN,
-	VW_OOB_RST_ACK,			/* index 04h (Out) */
+	VW_OOB_RST_ACK, /* index 04h (Out) */
 	VW_WAKE_L,
 	VW_PME_L,
-	VW_ERROR_FATAL,			/* index 05h (Out) */
+	VW_ERROR_FATAL, /* index 05h (Out) */
 	VW_ERROR_NON_FATAL,
 	/* Merge bit 3/0 into one signal. Need to set them simultaneously */
-	VW_SLAVE_BTLD_STATUS_DONE,
-	VW_SCI_L,			/* index 06h (Out) */
+	VW_PERIPHERAL_BTLD_STATUS_DONE,
+	VW_SCI_L, /* index 06h (Out) */
 	VW_SMI_L,
 	VW_RCIN_L,
 	VW_HOST_RST_ACK,
-	VW_HOST_RST_WARN,		/* index 07h (In)  */
-	VW_SUS_ACK,			/* index 40h (Out) */
-	VW_SUS_WARN_L,			/* index 41h (In)  */
+	VW_HOST_RST_WARN, /* index 07h (In)  */
+	VW_SUS_ACK, /* index 40h (Out) */
+	VW_SUS_WARN_L, /* index 41h (In)  */
 	VW_SUS_PWRDN_ACK_L,
 	VW_SLP_A_L,
-	VW_SLP_LAN,                     /* index 42h (In)  */
+	VW_SLP_LAN, /* index 42h (In)  */
 	VW_SLP_WLAN,
 	VW_SIGNAL_END,
 	VW_LIMIT = 0x2FFF
@@ -93,5 +93,19 @@ const char *espi_vw_get_wire_name(enum espi_vw_signal signal);
  */
 int espi_signal_is_vw(int signal);
 
+/**
+ * Wait for the specified VW's DIRTY bit to be cleared.
+ * @param signal VW to poll DIRTY bit for
+ * @param timeout max time in microseconds to poll.
+ */
+void espi_wait_vw_not_dirty(enum espi_vw_signal signal,
+			    unsigned int timeout_us);
+
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+/* Workaround for ADM fw18 known issue */
+int get_espi_virtual_wire_channel_status(void);
+
+void clear_espi_virtual_wire_channel_status(void);
+#endif
 
-#endif  /* __CROS_EC_ESPI_H */
+#endif /* __CROS_EC_ESPI_H */
diff --git a/include/event_log.h b/include/event_log.h
index 45b10a3a2d..5438a34414 100644
--- a/include/event_log.h
+++ b/include/event_log.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,16 +6,18 @@
 #ifndef __CROS_EC_EVENT_LOG_H
 #define __CROS_EC_EVENT_LOG_H
 
+#include <stdint.h>
+
 struct event_log_entry {
 	uint32_t timestamp; /* relative timestamp in milliseconds */
-	uint8_t type;       /* event type, caller-defined */
-	uint8_t size;       /* [7:5] caller-def'd [4:0] payload size in bytes */
-	uint16_t data;      /* type-defined data payload */
+	uint8_t type; /* event type, caller-defined */
+	uint8_t size; /* [7:5] caller-def'd [4:0] payload size in bytes */
+	uint16_t data; /* type-defined data payload */
 	uint8_t payload[0]; /* optional additional data payload: 0..16 bytes */
 } __packed;
 
-#define EVENT_LOG_SIZE_MASK  0x1f
-#define EVENT_LOG_SIZE(size) ((size) & EVENT_LOG_SIZE_MASK)
+#define EVENT_LOG_SIZE_MASK 0x1f
+#define EVENT_LOG_SIZE(size) ((size)&EVENT_LOG_SIZE_MASK)
 
 /* The timestamp is the microsecond counter shifted to get about a ms. */
 #define EVENT_LOG_TIMESTAMP_SHIFT 10 /* 1 LSB = 1024us */
@@ -23,8 +25,8 @@ struct event_log_entry {
 #define EVENT_LOG_NO_ENTRY 0xff
 
 /* Add an entry to the event log. */
-void log_add_event(uint8_t type, uint8_t size, uint16_t data,
-		   void *payload, uint32_t timestamp);
+void log_add_event(uint8_t type, uint8_t size, uint16_t data, void *payload,
+		   uint32_t timestamp);
 
 /*
  * Remove and return an entry from the event log, if available.
diff --git a/include/extpower.h b/include/extpower.h
index 5a10898c70..4740e6033d 100644
--- a/include/extpower.h
+++ b/include/extpower.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,6 +10,14 @@
 
 #include "common.h"
 
+enum gpio_signal; /* from gpio_signal.h */
+
+/**
+ * Run board specific code to update extpower status.  The default
+ * implementation does nothing, but a board may override it.
+ */
+__override_proto void board_check_extpower(void);
+
 /**
  * Return non-zero if external power is present.
  */
@@ -29,4 +37,4 @@ void extpower_interrupt(enum gpio_signal signal);
  */
 void extpower_handle_update(int is_present);
 
-#endif  /* __CROS_EC_EXTPOWER_H */
+#endif /* __CROS_EC_EXTPOWER_H */
diff --git a/include/fan.h b/include/fan.h
index fd49649547..29552e0e6a 100644
--- a/include/fan.h
+++ b/include/fan.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,6 +8,60 @@
 #ifndef __CROS_EC_FAN_H
 #define __CROS_EC_FAN_H
 
+#include "config.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#ifdef CONFIG_ZEPHYR
+#ifdef CONFIG_PLATFORM_EC_FAN
+
+#include <zephyr/devicetree.h>
+#define NODE_ID_AND_COMMA(node_id) node_id,
+enum fan_channel {
+#if DT_NODE_EXISTS(DT_INST(0, cros_ec_fans))
+	DT_FOREACH_CHILD(DT_INST(0, cros_ec_fans), NODE_ID_AND_COMMA)
+#endif /* cros_ec_fans */
+		FAN_CH_COUNT
+};
+
+BUILD_ASSERT(FAN_CH_COUNT == CONFIG_PLATFORM_EC_NUM_FANS);
+
+#endif /* CONFIG_PLATFORM_EC_FAN */
+#endif /* CONFIG_ZEPHYR */
+
+/**
+ * STOPPED means not spinning.
+ *
+ * When setting fan rpm, some implementations in chip layer (npcx and it83xx)
+ * is to adjust fan pwm duty steps by steps. In this period, fan_status will
+ * be marked as CHANGING. After change is done, fan_status will become LOCKED.
+ *
+ * In the period of changing pwm duty, if it's trying to increase/decrease duty
+ * even when duty is already in upper/lower bound. Then this action won't work,
+ * and fan_status will be marked as FRUSTRATED.
+ *
+ * For other implementations in chip layer (mchp), there is no
+ * changing period. So they don't have CHANGING status.
+ * Just return status as LOCKED in normal spinning case, return STOPPED when
+ * not spinning, return FRUSTRATED when the related flags (which is read from
+ * chip's register) is set.
+ */
+enum fan_status {
+	FAN_STATUS_STOPPED = 0,
+	FAN_STATUS_CHANGING = 1,
+	FAN_STATUS_LOCKED = 2,
+	FAN_STATUS_FRUSTRATED = 3
+};
+
+/* Fan mode */
+enum fan_mode {
+	/* FAN rpm mode */
+	FAN_RPM = 0,
+	/* FAN duty mode */
+	FAN_DUTY,
+};
+
 struct fan_conf {
 	unsigned int flags;
 	/* Hardware channel number (the meaning is chip-specific) */
@@ -23,6 +77,7 @@ struct fan_rpm {
 	int rpm_min;
 	int rpm_start;
 	int rpm_max;
+	uint8_t rpm_deviation;
 };
 
 /* Characteristic of each physical fan */
@@ -31,9 +86,29 @@ struct fan_t {
 	const struct fan_rpm *rpm;
 };
 
+/* Fan status data structure */
+struct fan_data {
+	/* Fan mode */
+	enum fan_mode current_fan_mode;
+	/* Actual rpm */
+	int rpm_actual;
+	/* Previous rpm */
+	int rpm_pre;
+	/* Target rpm */
+	int rpm_target;
+	/* Fan config flags */
+	unsigned int flags;
+	/* Automatic fan status */
+	enum fan_status auto_status;
+	/* Current PWM duty cycle percentage */
+	int pwm_percent;
+	/* Whether the PWM channel is enabled */
+	bool pwm_enabled;
+};
+
 /* Values for .flags field */
 /*   Enable automatic RPM control using tach input */
-#define FAN_USE_RPM_MODE   BIT(0)
+#define FAN_USE_RPM_MODE BIT(0)
 /*   Require a higher duty cycle to start up than to keep running */
 #define FAN_USE_FAST_START BIT(1)
 
@@ -45,7 +120,19 @@ extern const struct fan_t fans[];
 #endif
 
 /* For convenience */
-#define FAN_CH(fan)	fans[fan].conf->ch
+#define FAN_CH(fan) fans[fan].conf->ch
+/* Calculate temp_ratio as a macro. common/thermal.c defines the same
+ * function, but it cannot be used at file scope.
+ */
+#define THERMAL_FAN_PERCENT(low, high, cur)                   \
+	(((low) < (cur) && (cur) < (high)) ?                  \
+		 (100 * ((cur) - (low)) / ((high) - (low))) : \
+		 ((cur) <= (low) ? 0 : 100))
+/* Convert a temperature in centigrade to a temp_ratio, assuming constants
+ * temp_fan_off, temp_fan_max, already in Kelvin.  Helpful for fan tables.
+ */
+#define TEMP_TO_RATIO(temp_c) \
+	(THERMAL_FAN_PERCENT((temp_fan_off), (temp_fan_max), (C_TO_K(temp_c))))
 
 /**
  * Set the amount of active cooling needed. The thermal control task will call
@@ -57,16 +144,57 @@ extern const struct fan_t fans[];
 void fan_set_percent_needed(int fan, int pct);
 
 /**
- * This function translates the percentage of cooling needed into a target RPM.
+ * Convert temp_ratio (temperature as a percentage of the ec_thermal_config
+ * .temp_fan_off to .temp_fan_max range, also cooling effort needed) into a
+ * target fan RPM.
  * The default implementation should be sufficient for most needs, but
  * individual boards may provide a custom version if needed (see config.h).
  *
- * @param fan   Fan number (index into fans[])
- * @param pct   Percentage of cooling effort needed (always in [0,100])
- * Return       Target RPM for fan
+ * @param fan          Fan number (index into fans[])
+ * @param temp_ratio   Temperature as fraction of temp_fan_off to
+ *                     temp_fan_max range, expressed as a percent ([0,100]).
+ * Return              Target RPM for fan
  */
-int fan_percent_to_rpm(int fan, int pct);
-
+int fan_percent_to_rpm(int fan, int temp_ratio);
+/* Data structure to hold a tuple of parameters for one sensor and one fan. */
+struct fan_step_1_1 {
+	/* lowest temp_ratio (exclusive) to apply this rpm when decreasing.
+	 * Use this rpm until temp_ratio falls to or below this threshold.
+	 */
+	int decreasing_temp_ratio_threshold;
+	/* lowest temp_ratio (inclusive) to apply this rpm when increasing.
+	 * Use this rpm when temp_ratio exceeds this threshold.
+	 */
+	int increasing_temp_ratio_threshold;
+	int rpm;
+};
+/**
+ * Convert temp_ratio (temperature as a percentage of the ec_thermal_config
+ * .temp_fan_off to .temp_fan_max range) into a target fan RPM.
+ *
+ * This function adapts the most popular custom version of fan_percent_to_rpm,
+ * which provides hysteresis to reduce temperature/fan speed oscillations.
+ *
+ * To refactor to this, convert the fan_step-based fan_table to fan_step_1_1 by
+ * removing the first (.rpm = 0) element and using
+ * decreasing/increasing_temp_ratio_threshold for off/on respectively.
+ * See example in ../test/fan.c.
+ *
+ * @param fan_table        Pointer to ordered array of fan_step_1_1 structs.
+ *                         There is no need to have any element with .rpm = 0.
+ *                         Function assumes 0 when temp_ratio is below the
+ *                         thresholds in the index-0 element.
+ * @param num_fan_levels   Size of fan_table
+ * @param fan_index        Fan number (index into fans[])
+ * @param temp_ratio       Temperature as fraction of temp_fan_off to
+ *                         temp_fan_max range, expressed as a percent ([0,100]).
+ * @param on_change        Pointer to function to be run when the target fan
+ *                         rpm changes, such as ezkinil board_print_temps().
+ * Return                  Target RPM for fan
+ */
+int temp_ratio_to_rpm_hysteresis(const struct fan_step_1_1 *fan_table,
+				 int num_fan_levels, int fan_index,
+				 int temp_ratio, void (*on_change)(void));
 
 /**
  * These functions require chip-specific implementations.
@@ -92,29 +220,6 @@ int fan_get_rpm_target(int ch);
 /* Is the fan stalled when it shouldn't be? */
 int fan_is_stalled(int ch);
 
-/**
- * STOPPED means not spinning.
- *
- * When setting fan rpm, some implementations in chip layer (npcx and it83xx)
- * is to adjust fan pwm duty steps by steps. In this period, fan_status will
- * be marked as CHANGING. After change is done, fan_status will become LOCKED.
- *
- * In the period of changing pwm duty, if it's trying to increase/decrease duty
- * even when duty is already in upper/lower bound. Then this action won't work,
- * and fan_status will be marked as FRUSTRATED.
- *
- * For other implementations in chip layer (mchp and mec1322), there is no
- * changing period. So they don't have CHANGING status.
- * Just return status as LOCKED in normal spinning case, return STOPPED when
- * not spinning, return FRUSTRATED when the related flags (which is read from
- * chip's register) is set.
- */
-enum fan_status {
-	FAN_STATUS_STOPPED = 0,
-	FAN_STATUS_CHANGING = 1,
-	FAN_STATUS_LOCKED = 2,
-	FAN_STATUS_FRUSTRATED = 3
-};
 enum fan_status fan_get_status(int ch);
 
 /* Initialize the HW according to the desired flags */
@@ -126,4 +231,20 @@ void fan_set_count(int count);
 
 int is_thermal_control_enabled(int idx);
 
-#endif  /* __CROS_EC_FAN_H */
+#ifdef CONFIG_ZEPHYR
+extern struct fan_data fan_data[];
+
+/**
+ * This function sets PWM duty based on target RPM.
+ *
+ * The target and current RPM values in fan_data entry that
+ * corresponds to selected fan has to be updated before this
+ * function is called.
+ *
+ * @param ch    Fan number (index into fan_data[] and fans[])
+ * Return       Fan status (see fan_status enum definition)
+ */
+enum fan_status board_override_fan_control_duty(int ch);
+#endif
+
+#endif /* __CROS_EC_FAN_H */
diff --git a/include/flash.h b/include/flash.h
index 7dfb309122..08f70182d7 100644
--- a/include/flash.h
+++ b/include/flash.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,17 +9,19 @@
 #define __CROS_EC_FLASH_H
 
 #include "common.h"
-#include "ec_commands.h"  /* For EC_FLASH_PROTECT_* flags */
+#include "ec_commands.h" /* For EC_FLASH_PROTECT_* flags */
 
 #ifdef CONFIG_FLASH_MULTIPLE_REGION
-extern struct ec_flash_bank const flash_bank_array[
-	CONFIG_FLASH_REGION_TYPE_COUNT];
+#ifndef CONFIG_ZEPHYR
+extern struct ec_flash_bank const
+	flash_bank_array[CONFIG_FLASH_REGION_TYPE_COUNT];
+#endif
 
 /*
  * Return the bank the offset is in.
  * Return -1 if the offset is not at the beginning of that bank.
  */
-int flash_bank_index(int offset);
+int crec_flash_bank_index(int offset);
 
 /*
  * Number of banks between offset and offset+size.
@@ -38,38 +40,70 @@ int flash_bank_index(int offset);
  * begin = 0, end = -1....
  * The idea is to prevent erasing more than you think.
  */
-int flash_bank_count(int offset, int size);
+int crec_flash_bank_count(int offset, int size);
 
 /*
  * Return the size of the specified bank in bytes.
  * Return -1 if the bank is too large.
  */
-int flash_bank_size(int bank);
+int crec_flash_bank_size(int bank);
+
+int crec_flash_bank_start_offset(int bank);
 
-int flash_bank_start_offset(int bank);
+int crec_flash_bank_erase_size(int bank);
 
-int flash_bank_erase_size(int bank);
+void crec_flash_print_region_info(void);
 
 /* Number of physical flash banks */
-#define PHYSICAL_BANKS  CONFIG_FLASH_MULTIPLE_REGION
+#define PHYSICAL_BANKS CONFIG_FLASH_MULTIPLE_REGION
 
 /* WP region offset and size in units of flash banks */
-#define WP_BANK_OFFSET	flash_bank_index(CONFIG_WP_STORAGE_OFF)
+#define WP_BANK_OFFSET crec_flash_bank_index(CONFIG_WP_STORAGE_OFF)
 #define WP_BANK_COUNT \
-	(flash_bank_count(CONFIG_WP_STORAGE_OFF, CONFIG_WP_STORAGE_SIZE))
+	(crec_flash_bank_count(CONFIG_WP_STORAGE_OFF, CONFIG_WP_STORAGE_SIZE))
 
-#else  /* CONFIG_FLASH_MULTIPLE_REGION */
+#else /* CONFIG_FLASH_MULTIPLE_REGION */
 /* Number of physical flash banks */
 #ifndef PHYSICAL_BANKS
-#define PHYSICAL_BANKS (CONFIG_FLASH_SIZE / CONFIG_FLASH_BANK_SIZE)
+#define PHYSICAL_BANKS (CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE)
 #endif
 
 /* WP region offset and size in units of flash banks */
-#define WP_BANK_OFFSET	(CONFIG_WP_STORAGE_OFF / CONFIG_FLASH_BANK_SIZE)
+#define WP_BANK_OFFSET (CONFIG_WP_STORAGE_OFF / CONFIG_FLASH_BANK_SIZE)
 #ifndef WP_BANK_COUNT
-#define WP_BANK_COUNT	(CONFIG_WP_STORAGE_SIZE / CONFIG_FLASH_BANK_SIZE)
+#define WP_BANK_COUNT (CONFIG_WP_STORAGE_SIZE / CONFIG_FLASH_BANK_SIZE)
 #endif
-#endif  /* CONFIG_FLASH_MULTIPLE_REGION */
+#endif /* CONFIG_FLASH_MULTIPLE_REGION */
+
+/**
+ * Get number of flash banks
+ *
+ * @return number of flash banks
+ */
+int crec_flash_total_banks(void);
+
+/**
+ * Fill flash info response structure (version 2)
+ *
+ * The function is responsible for filling 'num_banks_desc', 'num_banks_total'
+ * and 'banks' fields with information about flash layout.
+ *
+ * We are passing the whole response structure because it is marked
+ * as '__ec_align4', so it's packed, and should be aligned also but on most
+ * systems it's not because CONFIG_HOSTCMD_OPTION is not enabled. It means that
+ * the structure can be placed at ANY address. Passing the response structure
+ * gives information to the compiler how members should be accessed.
+ * Passing pointer to structure member is an error, and compiler will warn
+ * about it. Taking pointer to structure member, passing it as uint8_t and
+ * casting it is dangerous because the compiler will assume that the address
+ * is aligned and you won't get any warning about it.
+ *
+ * @param pointer to flash info version 2 response structure
+ * @param size of 'banks' array inside response structure
+ * @return EC_RES_SUCCESS or other error code.
+ */
+int crec_flash_response_fill_banks(struct ec_response_flash_info_2 *r,
+				   int num_banks);
 
 /* Persistent protection state flash offset / size / bank */
 #if defined(CONFIG_FLASH_PSTATE) && defined(CONFIG_FLASH_PSTATE_BANK)
@@ -82,33 +116,33 @@ int flash_bank_erase_size(int bank);
  * When there is a dedicated flash bank used to store persistent state,
  * ensure the RO flash region excludes the PSTATE bank.
  */
-#define EC_FLASH_REGION_RO_SIZE		CONFIG_RO_SIZE
+#define EC_FLASH_REGION_RO_SIZE CONFIG_RO_SIZE
 
 #ifndef PSTATE_BANK
-#define PSTATE_BANK	    (CONFIG_FW_PSTATE_OFF / CONFIG_FLASH_BANK_SIZE)
+#define PSTATE_BANK (CONFIG_FW_PSTATE_OFF / CONFIG_FLASH_BANK_SIZE)
 #endif
 #ifndef PSTATE_BANK_COUNT
-#define PSTATE_BANK_COUNT   (CONFIG_FW_PSTATE_SIZE / CONFIG_FLASH_BANK_SIZE)
+#define PSTATE_BANK_COUNT (CONFIG_FW_PSTATE_SIZE / CONFIG_FLASH_BANK_SIZE)
 #endif
-#else   /* CONFIG_FLASH_PSTATE && CONFIG_FLASH_PSTATE_BANK */
+#else /* CONFIG_FLASH_PSTATE && CONFIG_FLASH_PSTATE_BANK */
 /* Allow flashrom to program the entire write protected area */
-#define EC_FLASH_REGION_RO_SIZE		CONFIG_WP_STORAGE_SIZE
-#define PSTATE_BANK_COUNT		0
-#endif  /* CONFIG_FLASH_PSTATE && CONFIG_FLASH_PSTATE_BANK */
+#define EC_FLASH_REGION_RO_SIZE CONFIG_WP_STORAGE_SIZE
+#define PSTATE_BANK_COUNT 0
+#endif /* CONFIG_FLASH_PSTATE && CONFIG_FLASH_PSTATE_BANK */
 
 #ifdef CONFIG_ROLLBACK
 /*
  * ROLLBACK region offset and size in units of flash banks.
  */
 #ifdef CONFIG_FLASH_MULTIPLE_REGION
-#define ROLLBACK_BANK_OFFSET	flash_bank_index(CONFIG_ROLLBACK_OFF)
-#define ROLLBACK_BANK_COUNT	\
-	flash_bank_count(CONFIG_ROLLBACK_OFF, CONFIG_ROLLBACK_SIZE)
+#define ROLLBACK_BANK_OFFSET crec_flash_bank_index(CONFIG_ROLLBACK_OFF)
+#define ROLLBACK_BANK_COUNT \
+	crec_flash_bank_count(CONFIG_ROLLBACK_OFF, CONFIG_ROLLBACK_SIZE)
 #else
-#define ROLLBACK_BANK_OFFSET	(CONFIG_ROLLBACK_OFF / CONFIG_FLASH_BANK_SIZE)
-#define ROLLBACK_BANK_COUNT	(CONFIG_ROLLBACK_SIZE / CONFIG_FLASH_BANK_SIZE)
-#endif	/* CONFIG_FLASH_MULTIPLE_REGION */
-#endif	/* CONFIG_ROLLBACK */
+#define ROLLBACK_BANK_OFFSET (CONFIG_ROLLBACK_OFF / CONFIG_FLASH_BANK_SIZE)
+#define ROLLBACK_BANK_COUNT (CONFIG_ROLLBACK_SIZE / CONFIG_FLASH_BANK_SIZE)
+#endif /* CONFIG_FLASH_MULTIPLE_REGION */
+#endif /* CONFIG_ROLLBACK */
 
 /* This enum is useful to identify different regions during verification. */
 enum flash_region {
@@ -130,7 +164,7 @@ enum flash_region {
  * @param size	        Number of bytes to write.
  * @param data          Destination buffer for data.  Must be 32-bit aligned.
  */
-int flash_physical_read(int offset, int size, char *data);
+int crec_flash_physical_read(int offset, int size, char *data);
 
 /**
  * Write to physical flash.
@@ -141,7 +175,7 @@ int flash_physical_read(int offset, int size, char *data);
  * @param size	        Number of bytes to write.
  * @param data          Data to write to flash.  Must be 32-bit aligned.
  */
-int flash_physical_write(int offset, int size, const char *data);
+int crec_flash_physical_write(int offset, int size, const char *data);
 
 /**
  * Erase physical flash.
@@ -151,7 +185,7 @@ int flash_physical_write(int offset, int size, const char *data);
  * @param offset	Flash offset to erase.
  * @param size	        Number of bytes to erase.
  */
-int flash_physical_erase(int offset, int size);
+int crec_flash_physical_erase(int offset, int size);
 
 /**
  * Read physical write protect setting for a flash bank.
@@ -159,7 +193,7 @@ int flash_physical_erase(int offset, int size);
  * @param bank	        Bank index to check.
  * @return non-zero if bank is protected until reboot.
  */
-int flash_physical_get_protect(int bank);
+int crec_flash_physical_get_protect(int bank);
 
 /**
  * Return flash protect state flags from the physical layer.
@@ -168,7 +202,7 @@ int flash_physical_get_protect(int bank);
  *
  * Uses the EC_FLASH_PROTECT_* flags from ec_commands.h
  */
-uint32_t flash_physical_get_protect_flags(void);
+uint32_t crec_flash_physical_get_protect_flags(void);
 
 /**
  * Enable/disable protecting firmware/pstate at boot.
@@ -177,7 +211,7 @@ uint32_t flash_physical_get_protect_flags(void);
  * taken care of)
  * @return non-zero if error.
  */
-int flash_physical_protect_at_boot(uint32_t new_flags);
+int crec_flash_physical_protect_at_boot(uint32_t new_flags);
 
 /**
  * Protect flash now.
@@ -185,7 +219,7 @@ int flash_physical_protect_at_boot(uint32_t new_flags);
  * @param all		Protect all (=1) or just read-only and pstate (=0).
  * @return non-zero if error.
  */
-int flash_physical_protect_now(int all);
+int crec_flash_physical_protect_now(int all);
 
 /**
  * Force reload of flash protection bits.
@@ -196,21 +230,21 @@ int flash_physical_protect_now(int all);
  *
  * Only returns (with EC_ERROR_ACCESS_DENIED) if the command is locked.
  */
-int flash_physical_force_reload(void);
+int crec_flash_physical_force_reload(void);
 
 /**
  * Restore flash physical layer state after sysjump.
  *
  * @return non-zero if restored.
  */
-int flash_physical_restore_state(void);
+int crec_flash_physical_restore_state(void);
 
 /**
  * Return the valid flash protect flags.
  *
  * @return a combination of EC_FLASH_PROTECT_* flags from ec_commands.h
  */
-uint32_t flash_physical_get_valid_flags(void);
+uint32_t crec_flash_physical_get_valid_flags(void);
 
 /**
  * Return the writable flash protect flags.
@@ -218,7 +252,7 @@ uint32_t flash_physical_get_valid_flags(void);
  * @param cur_flags The current flash protect flags.
  * @return a combination of EC_FLASH_PROTECT_* flags from ec_commands.h
  */
-uint32_t flash_physical_get_writable_flags(uint32_t cur_flags);
+uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags);
 
 /*****************************************************************************/
 /* Low-level common code for use by flash modules. */
@@ -232,7 +266,7 @@ uint32_t flash_physical_get_writable_flags(uint32_t cur_flags);
  * @param size		Number of bytes to check (word-aligned)
  * @return 1 if erased, 0 if not erased
  */
-int flash_is_erased(uint32_t offset, int size);
+int crec_flash_is_erased(uint32_t offset, int size);
 
 /**
  * Enable write protect for the specified range.
@@ -246,7 +280,7 @@ int flash_is_erased(uint32_t offset, int size);
  * taken care of)
  * @return EC_SUCCESS, or nonzero if error.
  */
-int flash_protect_at_boot(uint32_t new_flags);
+int crec_flash_protect_at_boot(uint32_t new_flags);
 
 /*****************************************************************************/
 /* High-level interface for use by other modules. */
@@ -256,13 +290,13 @@ int flash_protect_at_boot(uint32_t new_flags);
  *
  * Applies at-boot protection settings if necessary.
  */
-int flash_pre_init(void);
+int crec_flash_pre_init(void);
 
 /**
  * Return the usable size of flash in bytes.  Note that this may be smaller
  * than the physical flash size.
  */
-int flash_get_size(void);
+int crec_flash_get_size(void);
 
 /**
  * Get the physical memory address of a flash offset
@@ -283,7 +317,22 @@ int flash_get_size(void);
  *			in memory, unless function fails, iwc it is unset.
  * @return size of flash region available at *ptrp, or -1 on error
  */
-int flash_dataptr(int offset, int size_req, int align, const char **ptrp);
+int crec_flash_dataptr(int offset, int size_req, int align, const char **ptrp);
+
+/**
+ * Read from flash without hiding protected sections data
+ *
+ * If flash is mapped (CONFIG_MAPPED_STORAGE), it is usually more efficient to
+ * use flash_dataptr() to get a pointer directly to the flash memory rather
+ * than use flash_read(), since the former saves a memcpy() operation.
+ *
+ * This method won't hide the protected flash sections data.
+ *
+ * @param offset	Flash offset to read.
+ * @param size		Number of bytes to read.
+ * @param data		Destination buffer for data.  Must be 32-bit aligned.
+ */
+int crec_flash_unprotected_read(int offset, int size, char *data);
 
 /**
  * Read from flash.
@@ -292,11 +341,13 @@ int flash_dataptr(int offset, int size_req, int align, const char **ptrp);
  * use flash_dataptr() to get a pointer directly to the flash memory rather
  * than use flash_read(), since the former saves a memcpy() operation.
  *
- * @param offset	Flash offset to write.
- * @param size	        Number of bytes to write.
- * @param data          Destination buffer for data.  Must be 32-bit aligned.
+ * This method hides the protected flash sections data.
+ *
+ * @param offset	Flash offset to read.
+ * @param size		Number of bytes to read.
+ * @param data		Destination buffer for data.  Must be 32-bit aligned.
  */
-int flash_read(int offset, int size, char *data);
+int crec_flash_read(int offset, int size, char *data);
 
 /**
  * Write to flash.
@@ -307,7 +358,7 @@ int flash_read(int offset, int size, char *data);
  * @param size	        Number of bytes to write.
  * @param data          Data to write to flash.  Must be 32-bit aligned.
  */
-int flash_write(int offset, int size, const char *data);
+int crec_flash_write(int offset, int size, const char *data);
 
 /**
  * Erase flash.
@@ -317,14 +368,14 @@ int flash_write(int offset, int size, const char *data);
  * @param offset	Flash offset to erase.
  * @param size	        Number of bytes to erase.
  */
-int flash_erase(int offset, int size);
+int crec_flash_erase(int offset, int size);
 
 /**
  * Return the flash protect state.
  *
  * Uses the EC_FLASH_PROTECT_* flags from ec_commands.h
  */
-uint32_t flash_get_protect(void);
+uint32_t crec_flash_get_protect(void);
 
 /**
  * Set the flash protect state.
@@ -332,7 +383,7 @@ uint32_t flash_get_protect(void);
  * @param mask		Bits in flags to apply.
  * @param flags		New values for flags.
  */
-int flash_set_protect(uint32_t mask, uint32_t flags);
+int crec_flash_set_protect(uint32_t mask, uint32_t flags);
 
 /**
  * Get the serial number from flash.
@@ -340,7 +391,7 @@ int flash_set_protect(uint32_t mask, uint32_t flags);
  * @return char * ascii serial number string.
  *     NULL if error.
  */
-const char *flash_read_pstate_serial(void);
+const char *crec_flash_read_pstate_serial(void);
 
 /**
  * Set the serial number in flash.
@@ -349,7 +400,7 @@ const char *flash_read_pstate_serial(void);
  *
  * @return success status.
  */
-int flash_write_pstate_serial(const char *serialno);
+int crec_flash_write_pstate_serial(const char *serialno);
 
 /**
  * Get the MAC address from flash.
@@ -358,7 +409,7 @@ int flash_write_pstate_serial(const char *serialno);
  *     Format: "01:23:45:67:89:AB"
  *     NULL if error.
  */
-const char *flash_read_pstate_mac_addr(void);
+const char *crec_flash_read_pstate_mac_addr(void);
 
 /**
  * Set the MAC address in flash.
@@ -368,7 +419,7 @@ const char *flash_read_pstate_mac_addr(void);
  *
  * @return success status.
  */
-int flash_write_pstate_mac_addr(const char *mac_addr);
+int crec_flash_write_pstate_mac_addr(const char *mac_addr);
 
 /**
  * Lock or unlock HW necessary for mapped storage read.
@@ -376,9 +427,9 @@ int flash_write_pstate_mac_addr(const char *mac_addr);
  * @param lock          1 to lock, 0 to unlock.
  */
 #ifdef CONFIG_EXTERNAL_STORAGE
-void flash_lock_mapped_storage(int lock);
+void crec_flash_lock_mapped_storage(int lock);
 #else
-static inline void flash_lock_mapped_storage(int lock) { };
+static inline void crec_flash_lock_mapped_storage(int lock){};
 #endif /* CONFIG_EXTERNAL_STORAGE */
 
 /**
@@ -388,6 +439,6 @@ static inline void flash_lock_mapped_storage(int lock) { };
  * @param select   1 to select flash, 0 to deselect (disable).
  * @return EC_RES_* status code.
  */
-int board_flash_select(int select);
+int crec_board_flash_select(int select);
 
-#endif  /* __CROS_EC_FLASH_H */
+#endif /* __CROS_EC_FLASH_H */
diff --git a/include/flash_log.h b/include/flash_log.h
index e504df6ee7..36e3be6738 100644
--- a/include/flash_log.h
+++ b/include/flash_log.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,9 +6,9 @@
 #ifndef __CROS_EC_EVENT_LOG_H
 #define __CROS_EC_EVENT_LOG_H
 
-#include "config.h"
 #include "common.h"
 #include "compile_time_macros.h"
+#include "config.h"
 #include "stddef.h"
 
 enum flash_event_type {
@@ -16,10 +16,10 @@ enum flash_event_type {
 	FE_LOG_CORRUPTED = 1,
 	FE_TPM_I2C_ERROR = 2,
 	FE_LOG_OVERFLOWS = 3, /* A single byte, overflow counter. */
-	FE_LOG_LOCKS = 4,     /* A single byte, lock failures counter. */
-	FE_LOG_NVMEM = 5,     /* NVMEM failure, variable structure. */
-	FE_LOG_TPM_WIPE_ERROR = 6,     /* Failed to wipe the TPM */
-	FE_LOG_TRNG_STALL = 7,     /* Stall while retrieving a random number. */
+	FE_LOG_LOCKS = 4, /* A single byte, lock failures counter. */
+	FE_LOG_NVMEM = 5, /* NVMEM failure, variable structure. */
+	FE_LOG_TPM_WIPE_ERROR = 6, /* Failed to wipe the TPM */
+	FE_LOG_TRNG_STALL = 7, /* Stall while retrieving a random number. */
 	FE_LOG_DCRYPTO_FAILURE = 8, /* Dcrypto had to be reset. */
 
 	/*
@@ -92,9 +92,9 @@ struct nvmem_failure_payload {
 
 #define FLASH_LOG_PAYLOAD_SIZE(size) ((size)&FLASH_LOG_PAYLOAD_SIZE_MASK)
 /* Size of log entry for a specific payload size. */
-#define FLASH_LOG_ENTRY_SIZE(payload_sz)                                       \
-	((FLASH_LOG_PAYLOAD_SIZE(payload_sz) +                                 \
-	  sizeof(struct flash_log_entry) + CONFIG_FLASH_WRITE_SIZE - 1) &      \
+#define FLASH_LOG_ENTRY_SIZE(payload_sz)                                  \
+	((FLASH_LOG_PAYLOAD_SIZE(payload_sz) +                            \
+	  sizeof(struct flash_log_entry) + CONFIG_FLASH_WRITE_SIZE - 1) & \
 	 ~(CONFIG_FLASH_WRITE_SIZE - 1))
 
 /*
diff --git a/include/fpsensor.h b/include/fpsensor.h
index 2c5baa2679..df212d8b0b 100644
--- a/include/fpsensor.h
+++ b/include/fpsensor.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,38 +8,62 @@
 #ifndef __CROS_EC_FPSENSOR_H
 #define __CROS_EC_FPSENSOR_H
 
-#include <stdint.h>
 #include "common.h"
 #include "ec_commands.h"
+#include "fpsensor_alg.h"
+#include "fpsensor_types.h"
+#include "fpsensor_utils.h"
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
 
 #ifndef SPI_FP_DEVICE
 #define SPI_FP_DEVICE (&spi_devices[0])
 #endif
 
 /*  Four-character-code */
-#define FOURCC(a, b, c, d) ((uint32_t)(a) | ((uint32_t)(b) << 8) | \
-			   ((uint32_t)(c) << 16) | ((uint32_t)(d) << 24))
+#define FOURCC(a, b, c, d)                                              \
+	((uint32_t)(a) | ((uint32_t)(b) << 8) | ((uint32_t)(c) << 16) | \
+	 ((uint32_t)(d) << 24))
 
 /* 8-bit greyscale pixel format as defined by V4L2 headers */
 #define V4L2_PIX_FMT_GREY FOURCC('G', 'R', 'E', 'Y')
 
 /* --- functions provided by the sensor-specific driver --- */
 
-/* Initialize the connected sensor hardware and put it in a low power mode. */
+/**
+ * Initialize the connected sensor hardware and put it in a low power mode.
+ *
+ * @return EC_SUCCESS always
+ */
 int fp_sensor_init(void);
 
-/* De-initialize the sensor hardware. */
+/**
+ * De-initialize the sensor hardware.
+ *
+ * @return 0 on success
+ * @return negative value on error
+ */
 int fp_sensor_deinit(void);
 
-/*
- * Fill the 'ec_response_fp_info' buffer with the sensor information
+/**
+ * Fill the @p ec_response_fp_info buffer with the sensor information
  * as required by the EC_CMD_FP_INFO host command.
  *
- * Put both the static information and the ones read from the sensor at runtime.
+ * Fills both the static information and information read from the sensor at
+ * runtime.
+ *
+ * @param[out] resp sensor info
+ *
+ * @return EC_SUCCESS on success
+ * @return EC_RES_ERROR on error
  */
 int fp_sensor_get_info(struct ec_response_fp_info *resp);
 
-/*
+/**
  * Put the sensor in its lowest power state.
  *
  * fp_sensor_configure_detect needs to be called to restore finger detection
@@ -47,7 +71,7 @@ int fp_sensor_get_info(struct ec_response_fp_info *resp);
  */
 void fp_sensor_low_power(void);
 
-/*
+/**
  * Configure finger detection.
  *
  * Send the settings to the sensor, so it is properly configured to detect
@@ -55,104 +79,61 @@ void fp_sensor_low_power(void);
  */
 void fp_sensor_configure_detect(void);
 
-/*
+/**
  * Returns the status of the finger on the sensor.
  * (assumes fp_sensor_configure_detect was called before)
+ *
+ * @return finger_state
  */
-enum finger_state {
-	FINGER_NONE = 0,
-	FINGER_PARTIAL = 1,
-	FINGER_PRESENT = 2,
-};
 enum finger_state fp_sensor_finger_status(void);
 
-/*
+/**
+ * Image captured but quality is too low
+ */
+#define FP_SENSOR_LOW_IMAGE_QUALITY 1
+/**
+ * Finger removed before image was captured
+ */
+#define FP_SENSOR_TOO_FAST 2
+
+/**
+ * Sensor not fully covered by finger
+ */
+#define FP_SENSOR_LOW_SENSOR_COVERAGE 3
+
+/**
  * Acquires a fingerprint image.
  *
  * This function is called once the finger has been detected and cover enough
- * area of the sensor (ie fp_sensor_finger_status returned FINGER_PRESENT).
+ * area of the sensor (i.e., fp_sensor_finger_status returned FINGER_PRESENT).
  * It does the acquisition immediately.
- * The image_data parameter points to an image data buffer of size
- *
- * FP_SENSOR_IMAGE_SIZE allocated by the caller.
- * Returns:
- * - 0 on success
- * - negative value on error
- * - FP_SENSOR_LOW_IMAGE_QUALITY on image captured but quality is too low
- * - FP_SENSOR_TOO_FAST on finger removed before image was captured
- * - FP_SENSOR_LOW_SENSOR_COVERAGE on sensor not fully covered by finger
+ *
+ * @param[out] image_data Image from sensor. Buffer must be allocated by
+ * caller with size FP_SENSOR_IMAGE_SIZE.
+ *
+ * @return 0 on success
+ * @return negative value on error
+ * @return FP_SENSOR_LOW_IMAGE_QUALITY on image captured but quality is too low
+ * @return FP_SENSOR_TOO_FAST on finger removed before image was captured
+ * @return FP_SENSOR_LOW_SENSOR_COVERAGE on sensor not fully covered by finger
  */
-#define FP_SENSOR_LOW_IMAGE_QUALITY 1
-#define FP_SENSOR_TOO_FAST 2
-#define FP_SENSOR_LOW_SENSOR_COVERAGE 3
 int fp_sensor_acquire_image(uint8_t *image_data);
 
-/*
+/**
  * Acquires a fingerprint image with specific capture mode.
  *
- * Same as the fp_sensor_acquire_image function above,
- * excepted 'mode' can be set to one of the FP_CAPTURE_ constants
+ * Same as the fp_sensor_acquire_image function(),
+ * except @p mode can be set to one of the fp_capture_type constants
  * to get a specific image type (e.g. a pattern) rather than the default one.
- */
-int fp_sensor_acquire_image_with_mode(uint8_t *image_data, int mode);
-
-/*
- * Compares given finger image against enrolled templates.
- *
- * The matching algorithm can update the template with additional biometric data
- * from the image, if it chooses to do so.
- *
- * @param templ a pointer to the array of template buffers.
- * @param templ_count the number of buffers in the array of templates.
- * @param image the buffer containing the finger image
- * @param match_index index of the matched finger in the template array if any.
- * @param update_bitmap contains one bit per template, the bit is set if the
- * match has updated the given template.
- * @return negative value on error, else one of the following code :
- * - EC_MKBP_FP_ERR_MATCH_NO on non-match
- * - EC_MKBP_FP_ERR_MATCH_YES for match when template was not updated with
- *   new data
- * - EC_MKBP_FP_ERR_MATCH_YES_UPDATED for match when template was updated
- * - EC_MKBP_FP_ERR_MATCH_YES_UPDATE_FAILED match, but update failed (not saved)
- * - EC_MKBP_FP_ERR_MATCH_LOW_QUALITY when matching could not be performed due
- *   to low image quality
- * - EC_MKBP_FP_ERR_MATCH_LOW_COVERAGE when matching could not be performed
- *   due to finger covering too little area of the sensor
- */
-int fp_finger_match(void *templ, uint32_t templ_count, uint8_t *image,
-		    int32_t *match_index, uint32_t *update_bitmap);
-
-/*
- * Start a finger enrollment session.
- *
- * @return 0 on success or a negative error code.
- */
-int fp_enrollment_begin(void);
-
-/*
- * Generate a template from the finger whose enrollment has just being
- * completed.
  *
- * @param templ the buffer which will receive the template.
- * templ can be set to NULL to abort the current enrollment process.
+ * @param[out] image_data Image from sensor. Buffer must be allocated by
+ * caller with size FP_SENSOR_IMAGE_SIZE.
+ * @param mode  enum fp_capture_type
  *
- * @return 0 on success or a negative error code.
- */
-int fp_enrollment_finish(void *templ);
-
-/*
- * Adds fingerprint image to the current enrollment session.
- *
- * @return a negative value on error or one of the following codes:
- * - EC_MKBP_FP_ERR_ENROLL_OK when image was successfully enrolled
- * - EC_MKBP_FP_ERR_ENROLL_IMMOBILE when image added, but user should be
- *   advised to move finger
- * - EC_MKBP_FP_ERR_ENROLL_LOW_QUALITY when image could not be used due to low
- *   image quality
- * - EC_MKBP_FP_ERR_ENROLL_LOW_COVERAGE when image could not be used due to
- *   finger covering too little area of the sensor
+ * @return 0 on success
+ * @return negative value on error
  */
-int fp_finger_enroll(uint8_t *image, int *completion);
+int fp_sensor_acquire_image_with_mode(uint8_t *image_data, int mode);
 
 /**
  * Runs a test for defective pixels.
@@ -165,4 +146,8 @@ int fp_finger_enroll(uint8_t *image, int *completion);
  */
 int fp_maintenance(void);
 
+#ifdef __cplusplus
+}
+#endif
+
 #endif /* __CROS_EC_FPSENSOR_H */
diff --git a/include/fpsensor_alg.h b/include/fpsensor_alg.h
new file mode 100644
index 0000000000..725798f8d3
--- /dev/null
+++ b/include/fpsensor_alg.h
@@ -0,0 +1,86 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Fingerprint sensor interface */
+
+#ifndef __CROS_EC_FPSENSOR_ALG_H
+#define __CROS_EC_FPSENSOR_ALG_H
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Compares given finger image against enrolled templates.
+ *
+ * The matching algorithm can update the template with additional biometric data
+ * from the image, if it chooses to do so.
+ *
+ * @param[in,out] templ a pointer to the array of template buffers.
+ * @param templ_count the number of buffers in the array of templates.
+ * @param[in] image the buffer containing the finger image
+ * @param match_index index of the matched finger in the template array if any.
+ * @param[out] update_bitmap contains one bit per template, the bit is set if
+ * the match has updated the given template.
+ *
+ * @return EC_MKBP_FP_ERR_MATCH_NO on non-match
+ * @return EC_MKBP_FP_ERR_MATCH_YES for match when template was not updated with
+ * new data
+ * @return EC_MKBP_FP_ERR_MATCH_YES_UPDATED for match when template was updated
+ * @return EC_MKBP_FP_ERR_MATCH_YES_UPDATE_FAILED match, but update failed (not
+ * saved)
+ * @return EC_MKBP_FP_ERR_MATCH_LOW_QUALITY when matching could not be performed
+ * due to low image quality
+ * @return EC_MKBP_FP_ERR_MATCH_LOW_COVERAGE when matching could not be
+ * performed due to finger covering too little area of the sensor
+ * @return negative value on error
+ */
+int fp_finger_match(void *templ, uint32_t templ_count, uint8_t *image,
+		    int32_t *match_index, uint32_t *update_bitmap);
+
+/**
+ * Start a finger enrollment session.
+ *
+ * @return 0 on success
+ * @return negative value on error
+ */
+int fp_enrollment_begin(void);
+
+/**
+ * Generate a template from the finger whose enrollment has just being
+ * completed.
+ *
+ * @param[out] templ template buffer, which can be set to NULL to abort current
+ * enrollment process.
+ *
+ * @return 0 on success, negative value on error
+ */
+int fp_enrollment_finish(void *templ);
+
+/**
+ * Adds fingerprint image to the current enrollment session.
+ *
+ * @param[in] image Image to add to enrollment
+ * @param[out] completion The percentage of the enrollment process that is
+ * complete: [0-100].
+ *
+ * @return 0 on success
+ * @return EC_MKBP_FP_ERR_ENROLL_OK when image was successfully enrolled
+ * @return EC_MKBP_FP_ERR_ENROLL_IMMOBILE when image added, but user should be
+ * advised to move finger
+ * @return EC_MKBP_FP_ERR_ENROLL_LOW_QUALITY when image could not be used due to
+ * low image quality
+ * @return EC_MKBP_FP_ERR_ENROLL_LOW_COVERAGE when image could not be used
+ * due to finger covering too little area of the sensor
+ */
+int fp_finger_enroll(uint8_t *image, int *completion);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CROS_EC_FPSENSOR_ALG_H */
diff --git a/include/fpsensor_auth_commands.h b/include/fpsensor_auth_commands.h
new file mode 100644
index 0000000000..a0307072bf
--- /dev/null
+++ b/include/fpsensor_auth_commands.h
@@ -0,0 +1,23 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Fingerprint sensor interface */
+
+#ifndef __CROS_EC_FPSENSOR_AUTH_COMMANDS_H
+#define __CROS_EC_FPSENSOR_AUTH_COMMANDS_H
+
+extern "C" {
+#include "common.h"
+}
+
+/**
+ * Check the context has been cleared or not.
+ *
+ * @return EC_SUCCESS if the context has been cleared
+ * @return EC_ERROR_ACCESS_DENIED on the other cases.
+ */
+enum ec_error_list check_context_cleared();
+
+#endif /* __CROS_EC_FPSENSOR_AUTH_COMMANDS_H */
diff --git a/include/fpsensor_auth_crypto.h b/include/fpsensor_auth_crypto.h
new file mode 100644
index 0000000000..42d23e91af
--- /dev/null
+++ b/include/fpsensor_auth_crypto.h
@@ -0,0 +1,202 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Fingerprint sensor interface */
+
+#ifndef __CROS_EC_FPSENSOR_AUTH_CRYPTO_H
+#define __CROS_EC_FPSENSOR_AUTH_CRYPTO_H
+
+#include "openssl/ec.h"
+
+extern "C" {
+#include "ec_commands.h"
+}
+
+#include <optional>
+
+/**
+ * Create a @fp_elliptic_curve_public_key with the content of boringssl @p
+ * EC_KEY.
+ *
+ * @param[in] key boringssl key
+ *
+ * @return @p fp_elliptic_curve_public_key on success
+ * @return std::nullopt on error
+ */
+std::optional<fp_elliptic_curve_public_key>
+create_pubkey_from_ec_key(const EC_KEY &key);
+
+/**
+ * Create a boringssl @EC_KEY from the @p fp_elliptic_curve_public_key content.
+ *
+ * @param[in] pubkey public key structure
+ *
+ * @return @p EC_KEY on success
+ * @return nullptr on error
+ */
+bssl::UniquePtr<EC_KEY>
+create_ec_key_from_pubkey(const fp_elliptic_curve_public_key &pubkey);
+
+/**
+ * Create a boringssl @EC_KEY from a private key.
+ *
+ * @param[in] privkey private key
+ *
+ * @return @p EC_KEY on success
+ * @return nullptr on error
+ */
+bssl::UniquePtr<EC_KEY> create_ec_key_from_privkey(const uint8_t *privkey,
+						   size_t privkey_size);
+
+/**
+ * Encrypt the data in place with a specific version of encryption method and
+ * output the metadata and encrypted data.
+ *
+ * version 1 is 128 bit AES-GCM, and the encryption key is bound to the TPM
+ * seed, rollback secret and user_id.
+ *
+ * @param[in] version the version of the encryption method
+ * @param[out] info the metadata of the encryption output
+ * @param[in,out] data the data that need to be encrypted in place
+ * @param[in] data_size the size of data
+ *
+ * @return EC_SUCCESS on success
+ * @return EC_ERROR_* on error
+ */
+enum ec_error_list
+encrypt_data_in_place(uint16_t version,
+		      struct fp_auth_command_encryption_metadata &info,
+		      uint8_t *data, size_t data_size);
+
+/**
+ * Encrypt the @p EC_KEY with a specific version of encryption method.
+ *
+ * version 1 is 128 bit AES-GCM, and the encryption key is bound to the TPM
+ * seed, rollback secret and user_id.
+ *
+ * @param[in] key the private
+ * @param[in] version the version of the encryption method
+ * @param[out] enc_key the encryption output
+ *
+ * @return @p fp_encrypted_private_key on success
+ * @return std::nullopt on error
+ */
+std::optional<fp_encrypted_private_key>
+create_encrypted_private_key(const EC_KEY &key, uint16_t version);
+
+/**
+ * Decrypt the encrypted data.
+ *
+ * version 1 is 128 bit AES-GCM, and the encryption key is bound to the TPM
+ * seed, rollback secret and user_id.
+ *
+ * @param[in] info the metadata of the encryption output
+ * @param[in] enc_data the encrypted data
+ * @param[in] enc_data_size the size of encrypted data
+ * @param[in] version the version of the encryption method
+ * @param[out] data the decrypted data
+ * @param[in] data_size the size of decrypted data
+ *
+ * @return EC_SUCCESS on success
+ * @return EC_ERROR_* on error
+ */
+enum ec_error_list
+decrypt_data(const struct fp_auth_command_encryption_metadata &info,
+	     const uint8_t *enc_data, size_t enc_data_size, uint8_t *data,
+	     size_t data_size);
+
+/**
+ * Decrypt the encrypted private key.
+ *
+ * version 1 is 128 bit AES-GCM, and the encryption key is bound to the TPM
+ * seed, rollback secret and user_id.
+ *
+ * @param[in] info the metadata of the encryption output
+ * @param[in] enc_data the encrypted data
+ * @param[in] enc_data_size the size of encrypted data
+ * @param[in] version the version of the encryption method
+ * @param[out] data the decrypted data
+ * @param[in] data_size the size of decrypted data
+ *
+ * @return EC_SUCCESS on success
+ * @return EC_ERROR_* on error
+ */
+bssl::UniquePtr<EC_KEY> decrypt_private_key(
+	const struct fp_encrypted_private_key &encrypted_private_key);
+
+/**
+ * Generate the ECDH shared secret from private key and public key.
+ *
+ * @param[in] private_key the private key of the ECDH
+ * @param[in] public_key the public key of the ECDH
+ * @param[out] shared_secret the shared secret
+ * @param[in] share_secret_size the size of shared secret
+ *
+ * @return EC_SUCCESS on success
+ * @return EC_ERROR_* on error
+ */
+enum ec_error_list generate_ecdh_shared_secret(const EC_KEY &private_key,
+					       const EC_KEY &public_key,
+					       uint8_t *shared_secret,
+					       uint8_t share_secret_size);
+
+/**
+ * Generate a gsc_session_key that is derived from auth nonce, GSC nonce and
+ * pairing key.
+ *
+ * @param[in] auth_nonce the auth nonce
+ * @param[in] auth_nonce_size the size of auth nonce
+ * @param[in] gsc_nonce the auth nonce
+ * @param[in] gsc_nonce_size the size of gsc nonce
+ * @param[in] pairing_key the auth nonce
+ * @param[in] pairing_key_size the size of pairing key
+ * @param[in,out] gsc_session_key the output key
+ * @param[in] gsc_session_key_size the output key size
+ *
+ * @return EC_SUCCESS on success
+ * @return EC_ERROR_* on error
+ */
+enum ec_error_list
+generate_gsc_session_key(const uint8_t *auth_nonce, size_t auth_nonce_size,
+			 const uint8_t *gsc_nonce, size_t gsc_nonce_size,
+			 const uint8_t *pairing_key, size_t pairing_key_size,
+			 uint8_t *gsc_session_key, size_t gsc_session_key_size);
+
+/**
+ * Decrypt the data in place with a GSC session key.
+ * Note: The GSC session key is equal to the CK in the original design doc.
+ *
+ * @param[in] gsc_session_key the GSC session key
+ * @param[in] gsc_session_key_size the size of GSC session key
+ * @param[in] iv the IV of the encrypted data
+ * @param[in] iv_size the size of the IV
+ * @param[in,out] data the encrypted data
+ * @param[in] data_size the output data size
+ *
+ * @return EC_SUCCESS on success
+ * @return EC_ERROR_* on error
+ */
+enum ec_error_list decrypt_data_with_gsc_session_key_in_place(
+	const uint8_t *gsc_session_key, size_t gsc_session_key_size,
+	const uint8_t *iv, size_t iv_size, uint8_t *data, size_t data_size);
+/**
+ * Encrypt the data with a ECDH public key.
+ *
+ * @param[in] in_pubkey the input public key
+ * @param[in,out] data the data to be encrypted
+ * @param[in] data_size the data size
+ * @param[out] iv the output IV
+ * @param[in] iv_size the IV size
+ * @param[out] out_pubkey the output public key
+ *
+ * @return EC_SUCCESS on success
+ * @return EC_ERROR_* on error
+ */
+enum ec_error_list encrypt_data_with_ecdh_key_in_place(
+	const struct fp_elliptic_curve_public_key &in_pubkey, uint8_t *data,
+	size_t data_size, uint8_t *iv, size_t iv_size,
+	struct fp_elliptic_curve_public_key &out_pubkey);
+
+#endif /* __CROS_EC_FPSENSOR_AUTH_CRYPTO_H */
diff --git a/include/fpsensor_crypto.h b/include/fpsensor_crypto.h
index b6252b3fd2..f755578eb1 100644
--- a/include/fpsensor_crypto.h
+++ b/include/fpsensor_crypto.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,10 +8,15 @@
 #ifndef __CROS_EC_FPSENSOR_CRYPTO_H
 #define __CROS_EC_FPSENSOR_CRYPTO_H
 
-#include <stddef.h>
+#include "compile_time_macros.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
 
 #include "sha256.h"
 
+#include <stddef.h>
 #define HKDF_MAX_INFO_SIZE 128
 #define HKDF_SHA256_MAX_BLOCK_COUNT 255
 
@@ -28,8 +33,9 @@
  * HKDF_MAX_INFO_SIZE bytes.
  * @return EC_SUCCESS on success and error code otherwise.
  */
-int hkdf_expand(uint8_t *out_key, size_t out_key_size, const uint8_t *prk,
-		size_t prk_size, const uint8_t *info, size_t info_size);
+enum ec_error_list hkdf_expand(uint8_t *out_key, size_t out_key_size,
+			       const uint8_t *prk, size_t prk_size,
+			       const uint8_t *info, size_t info_size);
 
 /**
  * Derive hardware encryption key from rollback secret and |salt|.
@@ -38,7 +44,7 @@ int hkdf_expand(uint8_t *out_key, size_t out_key_size, const uint8_t *prk,
  * @param salt the salt to use in HKDF.
  * @return EC_SUCCESS on success and error code otherwise.
  */
-int derive_encryption_key(uint8_t *out_key, const uint8_t *salt);
+enum ec_error_list derive_encryption_key(uint8_t *out_key, const uint8_t *salt);
 
 /**
  * Derive positive match secret from |input_positive_match_salt| and
@@ -50,8 +56,9 @@ int derive_encryption_key(uint8_t *out_key, const uint8_t *salt);
  * least FP_POSITIVE_MATCH_SALT_BYTES in size.
  * @return EC_SUCCESS on success and error code otherwise.
  */
-int derive_positive_match_secret(uint8_t *output,
-				 const uint8_t *input_positive_match_salt);
+enum ec_error_list
+derive_positive_match_secret(uint8_t *output,
+			     const uint8_t *input_positive_match_salt);
 
 /**
  * Encrypt |plaintext| using AES-GCM128.
@@ -67,11 +74,11 @@ int derive_positive_match_secret(uint8_t *output,
  * @param tag_size the size of |tag|.
  * @return EC_SUCCESS on success and error code otherwise.
  */
-int aes_gcm_encrypt(const uint8_t *key, int key_size,
-		    const uint8_t *plaintext,
-		    uint8_t *ciphertext, int text_size,
-		    const uint8_t *nonce, int nonce_size,
-		    uint8_t *tag, int tag_size);
+enum ec_error_list aes_gcm_encrypt(const uint8_t *key, int key_size,
+				   const uint8_t *plaintext,
+				   uint8_t *ciphertext, int text_size,
+				   const uint8_t *nonce, int nonce_size,
+				   uint8_t *tag, int tag_size);
 
 /**
  * Decrypt |plaintext| using AES-GCM128.
@@ -87,9 +94,14 @@ int aes_gcm_encrypt(const uint8_t *key, int key_size,
  * @param tag_size the length of tag to compare against.
  * @return EC_SUCCESS on success and error code otherwise.
  */
-int aes_gcm_decrypt(const uint8_t *key, int key_size, uint8_t *plaintext,
-		    const uint8_t *ciphertext, int text_size,
-		    const uint8_t *nonce, int nonce_size,
-		    const uint8_t *tag, int tag_size);
+enum ec_error_list aes_gcm_decrypt(const uint8_t *key, int key_size,
+				   uint8_t *plaintext,
+				   const uint8_t *ciphertext, int text_size,
+				   const uint8_t *nonce, int nonce_size,
+				   const uint8_t *tag, int tag_size);
+
+#ifdef __cplusplus
+}
+#endif
 
 #endif /* __CROS_EC_FPSENSOR_CRYPTO_H */
diff --git a/include/fpsensor_detect.h b/include/fpsensor_detect.h
index e12ff76595..13ee1f73f6 100644
--- a/include/fpsensor_detect.h
+++ b/include/fpsensor_detect.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,21 +8,21 @@
 #ifndef __CROS_EC_FPSENSOR_DETECT_H
 #define __CROS_EC_FPSENSOR_DETECT_H
 
-enum fp_sensor_type {
-	FP_SENSOR_TYPE_UNKNOWN = -1,
-	FP_SENSOR_TYPE_FPC,
-	FP_SENSOR_TYPE_ELAN,
-};
+#ifdef __cplusplus
+extern "C" {
+#endif
 
-enum fp_transport_type {
-	FP_TRANSPORT_TYPE_UNKNOWN = -1,
-	FP_TRANSPORT_TYPE_SPI,
-	FP_TRANSPORT_TYPE_UART
-};
+#include "fpsensor_types.h"
 
 const char *fp_transport_type_to_str(enum fp_transport_type type);
 const char *fp_sensor_type_to_str(enum fp_sensor_type type);
-enum fp_sensor_type get_fp_sensor_type(void);
+const char *fp_sensor_spi_select_to_str(enum fp_sensor_spi_select type);
+enum fp_sensor_type fpsensor_detect_get_type(void);
 enum fp_transport_type get_fp_transport_type(void);
+enum fp_sensor_spi_select fpsensor_detect_get_spi_select(void);
+
+#ifdef __cplusplus
+}
+#endif
 
 #endif /* __CROS_EC_FPSENSOR_DETECT_H */
diff --git a/include/fpsensor_state.h b/include/fpsensor_state.h
index 6b752bc86d..3165bffa92 100644
--- a/include/fpsensor_state.h
+++ b/include/fpsensor_state.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,14 +8,20 @@
 #ifndef __CROS_EC_FPSENSOR_STATE_H
 #define __CROS_EC_FPSENSOR_STATE_H
 
-#include <stdbool.h>
-#include <stdint.h>
+#include "atomic.h"
 #include "common.h"
 #include "ec_commands.h"
+#include "fpsensor_driver.h"
+#include "fpsensor_state_without_driver_info.h"
 #include "link_defs.h"
 #include "timer.h"
 
-#include "driver/fingerprint/fpsensor.h"
+#include <stdbool.h>
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
 
 /* if no special memory regions are defined, fallback on regular SRAM */
 #ifndef FP_FRAME_SECTION
@@ -25,17 +31,13 @@
 #define FP_TEMPLATE_SECTION
 #endif
 
-#define SBP_ENC_KEY_LEN 16
-#define FP_ALGORITHM_ENCRYPTED_TEMPLATE_SIZE \
-	(FP_ALGORITHM_TEMPLATE_SIZE + \
-		FP_POSITIVE_MATCH_SALT_BYTES + \
-		sizeof(struct ec_fp_template_encryption_metadata))
+#define FP_ALGORITHM_ENCRYPTED_TEMPLATE_SIZE                         \
+	(FP_ALGORITHM_TEMPLATE_SIZE + FP_POSITIVE_MATCH_SALT_BYTES + \
+	 sizeof(struct ec_fp_template_encryption_metadata))
 
 /* Events for the FPSENSOR task */
-#define TASK_EVENT_SENSOR_IRQ     TASK_EVENT_CUSTOM_BIT(0)
-#define TASK_EVENT_UPDATE_CONFIG  TASK_EVENT_CUSTOM_BIT(1)
-
-#define FP_NO_SUCH_TEMPLATE -1
+#define TASK_EVENT_SENSOR_IRQ TASK_EVENT_CUSTOM_BIT(0)
+#define TASK_EVENT_UPDATE_CONFIG TASK_EVENT_CUSTOM_BIT(1)
 
 /* --- Global variables defined in fpsensor_state.c --- */
 
@@ -51,33 +53,8 @@ extern uint8_t fp_template[FP_MAX_FINGER_COUNT][FP_ALGORITHM_TEMPLATE_SIZE];
  */
 extern uint8_t fp_enc_buffer[FP_ALGORITHM_ENCRYPTED_TEMPLATE_SIZE];
 /* Salt used in derivation of positive match secret. */
-extern uint8_t fp_positive_match_salt
-	[FP_MAX_FINGER_COUNT][FP_POSITIVE_MATCH_SALT_BYTES];
-/* Index of the last enrolled but not retrieved template. */
-extern int8_t template_newly_enrolled;
-/* Number of used templates */
-extern uint32_t templ_valid;
-/* Bitmap of the templates with local modifications */
-extern uint32_t templ_dirty;
-/* Current user ID */
-extern uint32_t user_id[FP_CONTEXT_USERID_WORDS];
-/* Part of the IKM used to derive encryption keys received from the TPM. */
-extern uint8_t tpm_seed[FP_CONTEXT_TPM_BYTES];
-
-extern uint32_t fp_events;
-
-extern uint32_t sensor_mode;
-
-struct positive_match_secret_state {
-	/* Index of the most recently matched template. */
-	int8_t template_matched;
-	/* Flag indicating positive match secret can be read. */
-	bool readable;
-	/* Deadline to read positive match secret. */
-	timestamp_t deadline;
-};
-
-extern struct positive_match_secret_state positive_match_secret_state;
+extern uint8_t fp_positive_match_salt[FP_MAX_FINGER_COUNT]
+				     [FP_POSITIVE_MATCH_SALT_BYTES];
 
 /* Simulation for unit tests. */
 void fp_task_simulate(void);
@@ -87,7 +64,7 @@ void fp_task_simulate(void);
  *
  * @param idx the index of the template to clear.
  */
-void fp_clear_finger_context(int idx);
+void fp_clear_finger_context(uint16_t idx);
 
 /**
  * Clear all fingerprint templates associated with the current user id and
@@ -102,13 +79,6 @@ void fp_reset_and_clear_context(void);
  */
 int fp_get_next_event(uint8_t *out);
 
-/*
- * Check if FP TPM seed has been set.
- *
- * @return 1 if the seed has been set, 0 otherwise.
- */
-int fp_tpm_seed_is_set(void);
-
 /**
  * Change the sensor mode.
  *
@@ -116,7 +86,7 @@ int fp_tpm_seed_is_set(void);
  * @param mode_output   resulting mode
  * @return EC_RES_SUCCESS on success. Error code on failure.
  */
-int fp_set_sensor_mode(uint32_t mode, uint32_t *mode_output);
+enum ec_status fp_set_sensor_mode(uint32_t mode, uint32_t *mode_output);
 
 /**
  * Allow reading positive match secret for |fgr| in the next 5 seconds.
@@ -125,15 +95,28 @@ int fp_set_sensor_mode(uint32_t mode, uint32_t *mode_output);
  * @param state the state of positive match secret, e.g. readable or not.
  * @return EC_SUCCESS if the request is valid, error code otherwise.
  */
-int fp_enable_positive_match_secret(uint32_t fgr,
-	struct positive_match_secret_state *state);
+int fp_enable_positive_match_secret(uint16_t fgr,
+				    struct positive_match_secret_state *state);
 
 /**
  * Disallow positive match secret for any finger to be read.
  *
  * @param state the state of positive match secret, e.g. readable or not.
  */
-void fp_disable_positive_match_secret(
-	struct positive_match_secret_state *state);
+void fp_disable_positive_match_secret(struct positive_match_secret_state *state);
+
+/**
+ * Read the match secret from the positive match salt.
+ *
+ * @param fgr the index of positive match salt.
+ * @param positive_match_secret the match secret that derived from the salt.
+ */
+enum ec_status fp_read_match_secret(
+	int8_t fgr,
+	uint8_t positive_match_secret[FP_POSITIVE_MATCH_SECRET_BYTES]);
+
+#ifdef __cplusplus
+}
+#endif
 
 #endif /* __CROS_EC_FPSENSOR_STATE_H */
diff --git a/include/fpsensor_state_without_driver_info.h b/include/fpsensor_state_without_driver_info.h
new file mode 100644
index 0000000000..85f5bda074
--- /dev/null
+++ b/include/fpsensor_state_without_driver_info.h
@@ -0,0 +1,66 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Fingerprint sensor states interface without driver info */
+
+#ifndef __CROS_EC_FPSENSOR_STATE_WITHOUT_DRIVER_INFO_H
+#define __CROS_EC_FPSENSOR_STATE_WITHOUT_DRIVER_INFO_H
+
+#include "atomic.h"
+#include "ec_commands.h"
+#include "link_defs.h"
+#include "stdbool.h"
+#include "stdint.h"
+#include "timer.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SBP_ENC_KEY_LEN 16
+#define FP_NO_SUCH_TEMPLATE (UINT16_MAX)
+
+/* --- Global variables defined in fpsensor_state_without_driver_info.c --- */
+
+/* Index of the last enrolled but not retrieved template. */
+extern uint16_t template_newly_enrolled;
+/* Number of used templates */
+extern uint16_t templ_valid;
+/* Bitmap of the templates with local modifications */
+extern uint32_t templ_dirty;
+/* Current user ID */
+extern uint32_t user_id[FP_CONTEXT_USERID_WORDS];
+/* Part of the IKM used to derive encryption keys received from the TPM. */
+extern uint8_t tpm_seed[FP_CONTEXT_TPM_BYTES];
+/* Status of the FP encryption engine & context. */
+extern uint32_t fp_encryption_status;
+
+extern atomic_t fp_events;
+
+extern uint32_t sensor_mode;
+
+struct positive_match_secret_state {
+	/* Index of the most recently matched template. */
+	uint16_t template_matched;
+	/* Flag indicating positive match secret can be read. */
+	bool readable;
+	/* Deadline to read positive match secret. */
+	timestamp_t deadline;
+};
+
+extern struct positive_match_secret_state positive_match_secret_state;
+
+/*
+ * Check if FP TPM seed has been set.
+ *
+ * @return 1 if the seed has been set, 0 otherwise.
+ */
+int fp_tpm_seed_is_set(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CROS_EC_FPSENSOR_STATE_WITHOUT_DRIVER_INFO_H */
diff --git a/include/fpsensor_types.h b/include/fpsensor_types.h
new file mode 100644
index 0000000000..87ae4dd7c3
--- /dev/null
+++ b/include/fpsensor_types.h
@@ -0,0 +1,35 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Fingerprint sensor type identifiers */
+
+#ifndef __CROS_EC_FPSENSOR_TYPES_H
+#define __CROS_EC_FPSENSOR_TYPES_H
+
+enum fp_sensor_type {
+	FP_SENSOR_TYPE_UNKNOWN = -1,
+	FP_SENSOR_TYPE_FPC,
+	FP_SENSOR_TYPE_ELAN,
+};
+
+enum fp_transport_type {
+	FP_TRANSPORT_TYPE_UNKNOWN = -1,
+	FP_TRANSPORT_TYPE_SPI,
+	FP_TRANSPORT_TYPE_UART
+};
+
+enum fp_sensor_spi_select {
+	FP_SENSOR_SPI_SELECT_UNKNOWN = -1,
+	FP_SENSOR_SPI_SELECT_DEVELOPMENT,
+	FP_SENSOR_SPI_SELECT_PRODUCTION
+};
+
+enum finger_state {
+	FINGER_NONE = 0,
+	FINGER_PARTIAL = 1,
+	FINGER_PRESENT = 2,
+};
+
+#endif /* __CROS_EC_FPSENSOR_TYPES_H */
diff --git a/include/fpsensor_utils.h b/include/fpsensor_utils.h
new file mode 100644
index 0000000000..87e496bc63
--- /dev/null
+++ b/include/fpsensor_utils.h
@@ -0,0 +1,44 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Misc utilities for fingerprint management */
+
+#ifndef __CROS_EC_FPSENSOR_UTILS_H
+#define __CROS_EC_FPSENSOR_UTILS_H
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define CPRINTF(format, args...) cprintf(CC_FP, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_FP, format, ##args)
+
+/**
+ * Test that size+offset does not exceed buffer_size
+ *
+ * Returns:
+ *   EC_ERROR_OVERFLOW: if size+offset does not fit in uint32_t
+ *   EC_ERROR_INVAL: if size+offset > buffer_size
+ *   EC_SUCCESS: otherwise
+ */
+enum ec_error_list validate_fp_buffer_offset(uint32_t buffer_size,
+					     uint32_t offset, uint32_t size);
+
+#ifdef __cplusplus
+}
+#endif
+
+#define FP_MODE_ANY_CAPTURE \
+	(FP_MODE_CAPTURE | FP_MODE_ENROLL_IMAGE | FP_MODE_MATCH)
+#define FP_MODE_ANY_DETECT_FINGER \
+	(FP_MODE_FINGER_DOWN | FP_MODE_FINGER_UP | FP_MODE_ANY_CAPTURE)
+#define FP_MODE_ANY_WAIT_IRQ (FP_MODE_FINGER_DOWN | FP_MODE_ANY_CAPTURE)
+
+bool fp_match_success(int match_result);
+
+#endif /* __CROS_EC_FPSENSOR_UTILS_H */
diff --git a/include/gesture.h b/include/gesture.h
index bc0186887c..8744f3efcd 100644
--- a/include/gesture.h
+++ b/include/gesture.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/gettimeofday.h b/include/gettimeofday.h
new file mode 100644
index 0000000000..d808aeaf7d
--- /dev/null
+++ b/include/gettimeofday.h
@@ -0,0 +1,27 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_GETTIMEOFDAY_H
+#define __CROS_EC_GETTIMEOFDAY_H
+
+#include "common.h"
+
+#include <sys/time.h>
+
+/**
+ * Get the time.
+ *
+ * @warning This does not match gettimeofday() exactly; it does not return the
+ * time since the Unix Epoch.
+ *
+ * @param[out] tv time
+ * @param[in] tz ignored
+ * @return EC_SUCCESS on success
+ * @return EC_ERROR_INVAL on invalid parameters
+ */
+enum ec_error_list ec_gettimeofday(struct timeval *restrict tv,
+				   void *restrict tz);
+
+#endif /* __CROS_EC_GETTIMEOFDAY_H */
diff --git a/include/gpio.h b/include/gpio.h
index 92c851f91a..5fc0b07d66 100644
--- a/include/gpio.h
+++ b/include/gpio.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,53 +11,162 @@
 #include "common.h"
 #include "console.h"
 
-/* Flag definitions for gpio_info and gpio_alt_func */
-#define GPIO_FLAG_NONE     0       /* No flag needed, default setting */
-/* The following are valid for both gpio_info and gpio_alt_func: */
-#define GPIO_OPEN_DRAIN    BIT(0)  /* Output type is open-drain */
-#define GPIO_PULL_UP       BIT(1)  /* Enable on-chip pullup */
-#define GPIO_PULL_DOWN     BIT(2)  /* Enable on-chip pulldown */
-/* The following are valid for gpio_alt_func only */
-#define GPIO_ANALOG        BIT(3)  /* Set pin to analog-mode */
-/* The following are valid for gpio_info only */
-#define GPIO_INPUT         BIT(4)  /* Input */
-#define GPIO_OUTPUT        BIT(5)  /* Output */
-#define GPIO_LOW           BIT(6)  /* If GPIO_OUTPUT, set level low */
-#define GPIO_HIGH          BIT(7)  /* If GPIO_OUTPUT, set level high */
-#define GPIO_INT_F_RISING  BIT(8)  /* Interrupt on rising edge */
-#define GPIO_INT_F_FALLING BIT(9)  /* Interrupt on falling edge */
-#define GPIO_INT_F_LOW     BIT(11) /* Interrupt on low level */
-#define GPIO_INT_F_HIGH    BIT(12) /* Interrupt on high level */
-#define GPIO_DEFAULT       BIT(13) /* Don't set up on boot */
-#define GPIO_INT_DSLEEP    BIT(14) /* Interrupt in deep sleep */
-#define GPIO_INT_SHARED    BIT(15) /* Shared among multiple pins */
-#define GPIO_SEL_1P8V      BIT(16) /* Support 1.8v */
-#define GPIO_ALTERNATE     BIT(17) /* GPIO used for alternate function. */
-#define GPIO_LOCKED        BIT(18) /* Lock GPIO output and configuration */
-#define GPIO_HIB_WAKE_HIGH    BIT(19) /* Hibernate wake on high level */
-#define GPIO_HIB_WAKE_LOW     BIT(20) /* Hibernate wake on low level */
-#define GPIO_HIB_WAKE_RISING  BIT(21) /* Hibernate wake on rising edge */
+#ifdef __REQUIRE_ZEPHYR_GPIOS__
+#error "Zephyr source files must use the Zephyr GPIO API"
+#endif
+
+/*
+ * If compiling with Zephyr, include the GPIO_ definitions to deal with name
+ * conflicts
+ */
+#ifdef CONFIG_ZEPHYR
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/dt-bindings/gpio/ite-it8xxx2-gpio.h>
+#include <zephyr/dt-bindings/gpio/nuvoton-npcx-gpio.h>
+
+#include <dt-bindings/native-posix-gpio.h>
+
+/*
+ * Some flag definitions are duplicated by our private devicetree binding
+ * in zephyr/include/dt-bindings/gpio_defines.h.
+ *
+ * Validate that these definitions haven't changed.
+ */
+/* Validate that Zephyr's definition are the same for overlapping defines */
+#if BIT(16) != GPIO_INPUT
+#error GPIO_INPUT values are not the same!
+#elif BIT(17) != GPIO_OUTPUT
+#error GPIO_OUTPUT values are not the same!
+#elif BIT(18) != GPIO_OUTPUT_INIT_LOW
+#error GPIO_OUTPUT_INIT_LOW values are not the same!
+#elif BIT(19) != GPIO_OUTPUT_INIT_HIGH
+#error GPIO_OUTPUT_INIT_HIGH values are not the same!
+#elif BIT(20) != GPIO_OUTPUT_INIT_LOGICAL
+#error GPIO_OUTPUT_INIT_LOGICAL values are not the same!
+#elif BIT(21) != GPIO_INT_DISABLE
+#error GPIO_INT_DISABLE values are not the same!
+#elif BIT(22) != GPIO_INT_ENABLE
+#error GPIO_INT_ENABLE values are not the same!
+#elif BIT(23) != GPIO_INT_LEVELS_LOGICAL
+#error GPIO_INT_LEVELS_LOGICAL values are not the same!
+#elif BIT(24) != GPIO_INT_EDGE
+#error GPIO_INT_EDGE values are not the same!
+#elif BIT(25) != GPIO_INT_LOW_0
+#error GPIO_INT_LOW_0 values are not the same!
+#elif BIT(26) != GPIO_INT_HIGH_1
+#error GPIO_INT_HIGH_1 values are not the same!
+#endif
+
+/*
+ * Map the legacy EC GPIO flags to the Zephyr equivalent.
+ * Refer to the descriptions below.
+ */
+#define GPIO_FLAG_NONE GPIO_DISCONNECTED
+/* GPIO_ANALOG	           not supported by Zephyr */
+/* GPIO_OPEN_DRAIN         already defined by Zephyr */
+/* GPIO_DEFAULT            not supported by Zephyr */
+/* GPIO_PULL_UP            already defined by Zephyr */
+/* GPIO_PULL_DOWN          already defined by Zephyr */
+#define GPIO_LOW GPIO_OUTPUT_INIT_LOW
+#define GPIO_HIGH GPIO_OUTPUT_INIT_HIGH
+/* GPIO_INPUT              already defined by Zephyr */
+/* GPIO_OUTPUT             already defined by Zephyr */
+
+/*
+ * One to one mapping of interrupt flags isn't possible. So map these
+ * flags to not conflict with any Zephyr flags.
+ */
+#define GPIO_INT_F_RISING BIT(28)
+#define GPIO_INT_F_FALLING BIT(29)
+#define GPIO_INT_F_LOW BIT(30)
+#define GPIO_INT_F_HIGH BIT(31)
+/* GPIO_INT_DSLEEP         not supported by Zephyr */
+/* GPIO_INT_SHARED         not supported by Zephyr */
+
+#if DT_HAS_COMPAT_STATUS_OKAY(nuvoton_npcx_gpio)
+#define GPIO_VOLTAGE_1P8 NPCX_GPIO_VOLTAGE_1P8
+#define GPIO_SEL_1P8V GPIO_VOLTAGE_1P8
+#elif DT_HAS_COMPAT_STATUS_OKAY(ite_it8xxx2_gpio)
+#define GPIO_VOLTAGE_1P8 IT8XXX2_GPIO_VOLTAGE_1P8
+#define GPIO_SEL_1P8V GPIO_VOLTAGE_1P8
+#elif DT_HAS_COMPAT_STATUS_OKAY(zephyr_gpio_emul)
+#define GPIO_VOLTAGE_1P8 NATIVE_POSIX_GPIO_VOLTAGE_1P8
+#define GPIO_SEL_1P8V GPIO_VOLTAGE_1P8
+#elif DT_HAS_COMPAT_STATUS_OKAY(microchip_xec_gpio_v2)
+/*
+ * Add GPIO_VOLTAGE_1P8 and GPIO_SEL_1P8V used in common code.
+ * In MEC1727, GPIO_VOLTAGE_1P8 feature is not supported in GPIO control
+ * register, GPIO driver will skip this bit configuration, but MEC1727
+ * supports a group of GPIOs with 1.8V power rail, 1.8V design will be
+ * considered and supported in board circuit design state.
+ */
+#define GPIO_VOLTAGE_1P8 (1U << 11)
+#define GPIO_SEL_1P8V GPIO_VOLTAGE_1P8
+#endif
+/* GPIO_ALTERNATE          not supported by Zephyr */
+/* GPIO_LOCKED             not supported by Zephyr */
+/* GPIO_HIB_WAKE_HIGH      not supported by Zephyr */
+/* GPIO_HIB_WAKE_LOW       not supported by Zephyr */
+/* GPIO_HIB_WAKE_RISING    not supported by Zephyr */
+/* GPIO_HIB_WAKE_FALLING   not supported by Zephyr */
+/* GPIO_POWER_DOWN         not supported by Zephyr */
+
+#else /* !CONFIG_ZEPHYR */
+/*
+ * All flags supported by gpio_info expect GPIO_ANALOG
+ *
+ * Only 4 flags are supported by gpio_alt_func:
+ *   GPIO_OPEN_DRAIN
+ *   GPIO_PULL_UP
+ *   GPIO_PULL_DOWN
+ *   GPIO_PULL_ANALOG
+ */
+#define GPIO_FLAG_NONE 0 /* No flag needed, default setting */
+#define GPIO_ANALOG BIT(0) /* Set pin to analog-mode */
+#define GPIO_OPEN_DRAIN (BIT(1) | BIT(2)) /* Output type is open-drain  */
+#define GPIO_DEFAULT BIT(3) /* Don't set up on boot */
+#define GPIO_PULL_UP BIT(4) /* Enable on-chip pullup */
+#define GPIO_PULL_DOWN BIT(5) /* Enable on-chip pulldown */
+#define GPIO_LOW BIT(6) /* If GPIO_OUTPUT, set level low */
+#define GPIO_HIGH BIT(7) /* If GPIO_OUTPUT, set level high */
+#define GPIO_INPUT BIT(8) /* Input */
+#define GPIO_OUTPUT BIT(9) /* Output */
+#define GPIO_INT_F_RISING BIT(10) /* Interrupt on rising edge */
+#define GPIO_INT_F_FALLING BIT(11) /* Interrupt on falling edge */
+#define GPIO_INT_F_LOW BIT(12) /* Interrupt on low level */
+#define GPIO_INT_F_HIGH BIT(13) /* Interrupt on high level */
+#define GPIO_INT_DSLEEP BIT(14) /* Interrupt in deep sleep */
+#define GPIO_INT_SHARED BIT(15) /* Shared among multiple pins */
+#define GPIO_SEL_1P8V BIT(16) /* Support 1.8v */
+#define GPIO_ALTERNATE BIT(17) /* GPIO used for alternate function. */
+#define GPIO_LOCKED BIT(18) /* Lock GPIO output and configuration */
+#define GPIO_HIB_WAKE_HIGH BIT(19) /* Hibernate wake on high level */
+#define GPIO_HIB_WAKE_LOW BIT(20) /* Hibernate wake on low level */
+#define GPIO_HIB_WAKE_RISING BIT(21) /* Hibernate wake on rising edge */
 #define GPIO_HIB_WAKE_FALLING BIT(22) /* Hibernate wake on falling edge */
 #ifdef CONFIG_GPIO_POWER_DOWN
-#define GPIO_POWER_DOWN    BIT(23) /* Pin and pad is powered off */
+#define GPIO_POWER_DOWN BIT(23) /* Pin and pad is powered off */
 #endif
 
+#endif /* CONFIG_ZEPHYR */
+
 /* Common flag combinations */
-#define GPIO_OUT_LOW        (GPIO_OUTPUT | GPIO_LOW)
-#define GPIO_OUT_HIGH       (GPIO_OUTPUT | GPIO_HIGH)
-#define GPIO_ODR_HIGH       (GPIO_OUTPUT | GPIO_OPEN_DRAIN | GPIO_HIGH)
-#define GPIO_ODR_LOW        (GPIO_OUTPUT | GPIO_OPEN_DRAIN | GPIO_LOW)
-#define GPIO_INT_RISING     (GPIO_INPUT | GPIO_INT_F_RISING)
-#define GPIO_INT_FALLING    (GPIO_INPUT | GPIO_INT_F_FALLING)
+#define GPIO_OUT_LOW (GPIO_OUTPUT | GPIO_LOW)
+#define GPIO_OUT_HIGH (GPIO_OUTPUT | GPIO_HIGH)
+#define GPIO_ODR_HIGH (GPIO_OUTPUT | GPIO_OPEN_DRAIN | GPIO_HIGH)
+#define GPIO_ODR_LOW (GPIO_OUTPUT | GPIO_OPEN_DRAIN | GPIO_LOW)
+#define GPIO_INT_RISING (GPIO_INPUT | GPIO_INT_F_RISING)
+#define GPIO_INT_FALLING (GPIO_INPUT | GPIO_INT_F_FALLING)
 /* TODO(crosbug.com/p/24204): "EDGE" would have been clearer than "BOTH". */
-#define GPIO_INT_BOTH       (GPIO_INT_RISING | GPIO_INT_FALLING)
-#define GPIO_INT_LOW        (GPIO_INPUT | GPIO_INT_F_LOW)
-#define GPIO_INT_HIGH       (GPIO_INPUT | GPIO_INT_F_HIGH)
-#define GPIO_INT_LEVEL      (GPIO_INT_LOW | GPIO_INT_HIGH)
-#define GPIO_INT_ANY        (GPIO_INT_BOTH | GPIO_INT_LEVEL)
+#define GPIO_INT_BOTH (GPIO_INT_RISING | GPIO_INT_FALLING)
+#define GPIO_INT_LOW (GPIO_INPUT | GPIO_INT_F_LOW)
+#define GPIO_INT_HIGH (GPIO_INPUT | GPIO_INT_F_HIGH)
+#define GPIO_INT_LEVEL (GPIO_INT_LOW | GPIO_INT_HIGH)
+#define GPIO_INT_ANY (GPIO_INT_BOTH | GPIO_INT_LEVEL)
 #define GPIO_INT_BOTH_DSLEEP (GPIO_INT_BOTH | GPIO_INT_DSLEEP)
-#define GPIO_HIB_WAKE_MASK   (GPIO_HIB_WAKE_HIGH | GPIO_HIB_WAKE_LOW | \
-			      GPIO_HIB_WAKE_RISING|GPIO_HIB_WAKE_FALLING)
+#define GPIO_HIB_WAKE_MASK                                               \
+	(GPIO_HIB_WAKE_HIGH | GPIO_HIB_WAKE_LOW | GPIO_HIB_WAKE_RISING | \
+	 GPIO_HIB_WAKE_FALLING)
 
 /* Convert GPIO mask to GPIO number / index. */
 #define GPIO_MASK_TO_NUM(mask) (__fls(mask))
@@ -66,9 +175,7 @@
  * some boards and unit tests don't have a gpio_signal enum defined, so we
  * define an emtpy one here.*/
 #ifndef __CROS_EC_GPIO_SIGNAL_H
-enum gpio_signal {
-	GPIO_COUNT
-};
+enum gpio_signal { GPIO_COUNT };
 #endif /* __CROS_EC_GPIO_SIGNAL_H */
 
 /* Alternate functions for GPIOs */
@@ -122,7 +229,7 @@ extern const int unused_pin_count;
  * If the signal's interrupt is enabled, this will be called in the
  * context of the GPIO interrupt handler.
  */
-extern void (* const gpio_irq_handlers[])(enum gpio_signal signal);
+extern void (*const gpio_irq_handlers[])(enum gpio_signal signal);
 extern const int gpio_ih_count;
 #define GPIO_IH_COUNT gpio_ih_count
 
@@ -200,9 +307,8 @@ void gpio_set_flags(enum gpio_signal signal, int flags);
 #define CONFIG_GPIO_GET_EXTENDED
 #endif
 
-#ifdef CONFIG_GPIO_GET_EXTENDED
 /**
- * Get the current flags for a signal.
+ * Get the current flags for a signal. Requires CONFIG_GPIO_GET_EXTENDED.
  *
  * @param signal	Signal to get flags for
  * @returns The flags that are currently defined for this signal
@@ -210,12 +316,31 @@ void gpio_set_flags(enum gpio_signal signal, int flags);
 int gpio_get_flags(enum gpio_signal signal);
 
 /**
- * Get flags for GPIO by port and mask.
+ * Get flags for GPIO by port and mask. Requires CONFIG_GPIO_GET_EXTENDED.
  *
  * @param port		GPIO port to set (GPIO_*)
  * @param mask		Bitmask of pins on that port to check: one only.
  */
 int gpio_get_flags_by_mask(uint32_t port, uint32_t mask);
+
+#ifdef CONFIG_ZEPHYR
+
+/**
+ * Convert flags from Zephyr to CrOS EC format
+ *
+ * @param zephyr	flags in Zephyr format
+ * @returns		flags in CrOS EC format
+ */
+int convert_from_zephyr_flags(const gpio_flags_t zephyr);
+
+/**
+ * Convert flags from CrOS EC to Zephyr format
+ *
+ * @param ec_flags	flags in CrOS EC format
+ * @returns		flags in Zephyr format
+ */
+gpio_flags_t convert_to_zephyr_flags(int ec_flags);
+
 #endif
 
 /**
@@ -274,6 +399,42 @@ int gpio_or_ioex_get_level(int signal, int *value);
  */
 void gpio_reset(enum gpio_signal signal);
 
+#ifdef CONFIG_ZEPHYR
+
+/**
+ * @brief Save state of a GPIO controller port
+ *
+ * This function saves all pins current state from selected port.
+ *
+ * @param port	Port to save
+ * @param flags	Buffer to hold gpio flags
+ */
+int gpio_save_port_config(const struct device *port, gpio_flags_t *flags,
+			  int buff_size);
+
+/**
+ * @brief Restore state of a GPIO controller port
+ *
+ * This function restore all pins current state from selected port.
+ *
+ * @param port	Port to restore
+ * @param flags	Buffer with gpio flags saved by ioex_save_gpio_config
+ */
+int gpio_restore_port_config(const struct device *port, gpio_flags_t *flags,
+			     int buff_size);
+
+/**
+ * @brief Reset all the GPIOs to default state
+ *
+ * This returns all pins from selected port to default state. The default flags
+ * are specified by the "named-gpios" node in the board devicetree.
+ *
+ * @param port	Port to reset
+ */
+void gpio_reset_port(const struct device *port);
+
+#endif /* CONFIG_ZEPHYR */
+
 /**
  * Enable interrupts for the signal.
  *
@@ -323,7 +484,6 @@ int gpio_clear_pending_interrupt(enum gpio_signal signal);
  */
 void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags);
 
-
 /**
  * Set alternate function for GPIO(s).
  *
@@ -337,7 +497,7 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags);
  *                      the specified GPIOs for normal GPIO operation.
  */
 void gpio_set_alternate_function(uint32_t port, uint32_t mask,
-				enum gpio_alternate_func func);
+				 enum gpio_alternate_func func);
 
 #ifdef CONFIG_GPIO_POWER_DOWN
 /**
@@ -369,4 +529,4 @@ int signal_is_gpio(int signal);
  */
 void gpio_set_wakepin(enum gpio_signal signal, uint32_t flags);
 
-#endif  /* __CROS_EC_GPIO_H */
+#endif /* __CROS_EC_GPIO_H */
diff --git a/include/gpio.wrap b/include/gpio.wrap
index cca72ba7b0..84055d3ba3 100644
--- a/include/gpio.wrap
+++ b/include/gpio.wrap
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
+ * Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,9 +22,9 @@
  * - ALTERNATE
  * - UNUSED
  *
- * @note You cannot have dependencies bewteen these macros. For example,
+ * @note You cannot have dependencies between these macros. For example,
  *       you cannot define GPIO_INT in terms of GPIO. All macros must be
- *       independently evaluatable.
+ *       independently evaluable.
  *       This is due to the reorganization mechanism at the bottom of this file.
  *
  * @see include/gpio_list.h
@@ -42,7 +42,7 @@
 
 /**
  * @def GPIO
- * @brief The GPIO macro is used to define a new GPIO pin name and function.
+ * @brief The GPIO macro defines a GPIO pin name and function.
  *
  * The name is used to populate the gpio_signal enum by first
  * prepending GPIO_ to the name.  It is also used to construct the
@@ -57,7 +57,7 @@
 
 /**
  * @def GPIO_INT
- * @brief The GPIO_INT macro is used to define a GPIO that has an IRQ handler.
+ * @brief The GPIO_INT macro defines a GPIO that has an IRQ handler.
  *
  * The IRQ handler pointers are stored as elements in the gpio_irq_handlers
  * array.
@@ -68,8 +68,7 @@
 
 /**
  * @def ALTERNATE
- * @brief The ALTERNATE macro is used associate a GPIO with an alternate
- *        function.
+ * @brief The ALTERNATE macro associates a GPIO with an alternate function.
  *
  * Alternate functions allow hardware peripherals access to GPIO pins.
  * Modules use gpio_config_module to enable and disable the alternate functions
@@ -87,7 +86,7 @@
 
 /**
  * @def UNIMPLEMENTED
- * @brief The UNIMPLEMENTED macro is used to define a GPIO that doesn't actually exist.
+ * @brief The UNIMPLEMENTED macro defines a GPIO that doesn't actually exist.
  *
  * Some GPIO names are well known and used by generic code, ENTERING_RW and WP_L
  * are examples.  If a particular board doesn't have a GPIO assigned to such a
@@ -107,7 +106,7 @@
 
 /**
  * @def UNUSED
- * @brief The UNUSED macro is used to define a pin as unused.
+ * @brief The UNUSED macro defines a pin as unused.
  *
  * This allows the chip specific code to provision these pins for
  * the lowest power state.
@@ -121,7 +120,7 @@
 
 /**
  * @def IOEX
- * @brief The IOEX macro is used to define a new IO Expander GPIO pin.
+ * @brief The IOEX macro defines an IO Expander GPIO.
  *
  * The name is used to populate enum ioex_signal by prepending "IOEX_".
  */
@@ -131,7 +130,7 @@
 
 /**
  * @def IOEX_INT
- * @brief The IOEX_INT macro is used to define a GPIOs that have an IRQ handler.
+ * @brief The IOEX_INT macro defines an IO Expander GPIO that has an IRQ handler.
  *
  * The IRQ handler pointers are stored as elements in the ioex_irq_handlers
  * array.
diff --git a/include/gpio_list.h b/include/gpio_list.h
index 3c71c3b0e2..e5a90b4e89 100644
--- a/include/gpio_list.h
+++ b/include/gpio_list.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,35 +8,35 @@
 #include "gpio_signal.h"
 
 #ifdef CONFIG_COMMON_GPIO_SHORTNAMES
-#define GPIO(name, pin, flags) {GPIO_NAME_BY_##pin, GPIO_##pin, flags},
+#define GPIO(name, pin, flags) { GPIO_NAME_BY_##pin, GPIO_##pin, flags },
 #define GPIO_INT(name, pin, flags, signal) \
-		{GPIO_NAME_BY_##pin, GPIO_##pin, flags},
+	{ GPIO_NAME_BY_##pin, GPIO_##pin, flags },
 #else
-#define GPIO(name, pin, flags) {#name, GPIO_##pin, flags},
-#define GPIO_INT(name, pin, flags, signal) {#name, GPIO_##pin, flags},
+#define GPIO(name, pin, flags) { #name, GPIO_##pin, flags },
+#define GPIO_INT(name, pin, flags, signal) { #name, GPIO_##pin, flags },
 #endif
 
-#define UNIMPLEMENTED(name) {#name, UNIMPLEMENTED_GPIO_BANK, 0, GPIO_DEFAULT},
+#define UNIMPLEMENTED(name) { #name, UNIMPLEMENTED_GPIO_BANK, 0, GPIO_DEFAULT },
 
 /* GPIO signal list. */
-const struct gpio_info gpio_list[] = {
-	#include "gpio.wrap"
+__const_data const struct gpio_info gpio_list[] = {
+#include "gpio.wrap"
 };
 
 BUILD_ASSERT(ARRAY_SIZE(gpio_list) == GPIO_COUNT);
 
-#define UNUSED(pin) {GPIO_##pin},
+#define UNUSED(pin) { GPIO_##pin },
 /* Unconnected pin list. */
-const struct unused_pin_info unused_pin_list[] = {
-	#include "gpio.wrap"
+__const_data const struct unused_pin_info unused_pin_list[] = {
+#include "gpio.wrap"
 };
 
 const int unused_pin_count = ARRAY_SIZE(unused_pin_list);
 
 /* GPIO Interrupt Handlers */
 #define GPIO_INT(name, pin, flags, signal) signal,
-void (* const gpio_irq_handlers[])(enum gpio_signal signal) = {
-	#include "gpio.wrap"
+void (*const gpio_irq_handlers[])(enum gpio_signal signal) = {
+#include "gpio.wrap"
 };
 const int gpio_ih_count = ARRAY_SIZE(gpio_irq_handlers);
 
@@ -47,7 +47,7 @@ const int gpio_ih_count = ARRAY_SIZE(gpio_irq_handlers);
  *
  * This constraint is handled within gpio.wrap.
  */
-#define GPIO_INT(name, pin, flags, signal)	\
+#define GPIO_INT(name, pin, flags, signal) \
 	BUILD_ASSERT(GPIO_##name < ARRAY_SIZE(gpio_irq_handlers));
 #include "gpio.wrap"
 
@@ -64,11 +64,12 @@ const int gpio_ih_count = ARRAY_SIZE(gpio_irq_handlers);
  * The compiler will complain if we use the same name twice. The linker ignores
  * anything that gets by.
  */
-#define PIN(a, b...) static const int _pin_ ## a ## _ ## b \
-	__attribute__((unused, section(".unused"))) = __LINE__;
-#include "gpio.wrap"
-
+#define PIN(a, b...)                    \
+	static const int _pin_##a##_##b \
+		__attribute__((unused, section(".unused"))) = __LINE__;
 #include "ioexpander.h"
+
+#include "gpio.wrap"
 #define IOEX_EXPIN(ioex, port, index) (ioex), (port), BIT(index)
 
 /*
@@ -83,7 +84,7 @@ const int gpio_ih_count = ARRAY_SIZE(gpio_irq_handlers);
  *      - flags: the same as the flags of GPIO.
  *
  */
-#define IOEX(name, expin, flags) {#name, IOEX_##expin, flags},
+#define IOEX(name, expin, flags) { #name, IOEX_##expin, flags },
 /*
  *  Define the IO expander IO which supports interrupt in gpio.inc by
  *  the format:
@@ -97,18 +98,18 @@ const int gpio_ih_count = ARRAY_SIZE(gpio_irq_handlers);
  *      - flags: the same as the flags of GPIO.
  *      - handler: the IOEX IO's interrupt handler.
  */
-#define IOEX_INT(name, expin, flags, handler) {#name, IOEX_##expin, flags},
+#define IOEX_INT(name, expin, flags, handler) { #name, IOEX_##expin, flags },
 
 /* IO expander signal list. */
 const struct ioex_info ioex_list[] = {
-	#include "gpio.wrap"
+#include "gpio.wrap"
 };
 BUILD_ASSERT(ARRAY_SIZE(ioex_list) == IOEX_COUNT);
 
 /* IO Expander Interrupt Handlers */
 #define IOEX_INT(name, expin, flags, handler) handler,
-void (* const ioex_irq_handlers[])(enum ioex_signal signal) = {
-	#include "gpio.wrap"
+void (*const ioex_irq_handlers[])(enum ioex_signal signal) = {
+#include "gpio.wrap"
 };
 const int ioex_ih_count = ARRAY_SIZE(ioex_irq_handlers);
 /*
@@ -116,9 +117,9 @@ const int ioex_ih_count = ARRAY_SIZE(ioex_irq_handlers);
  * IOEX's declaration in the gpio.inc
  * file.
  */
-#define IOEX_INT(name, expin, flags, handler)		\
-	BUILD_ASSERT(IOEX_##name - IOEX_SIGNAL_START	\
-		     < ARRAY_SIZE(ioex_irq_handlers));
+#define IOEX_INT(name, expin, flags, handler)          \
+	BUILD_ASSERT(IOEX_##name - IOEX_SIGNAL_START < \
+		     ARRAY_SIZE(ioex_irq_handlers));
 #include "gpio.wrap"
 
 #define IOEX(name, expin, flags) expin
@@ -128,9 +129,9 @@ const int ioex_ih_count = ARRAY_SIZE(ioex_irq_handlers);
  * number declared is greater or equal to CONFIG_IO_EXPANDER_PORT_COUNT.
  * The linker ignores anything that gets by.
  */
-#define EXPIN(a, b, c...) \
-	static const int _expin_ ## a ## _ ## b ## _ ## c \
-	__attribute__((unused, section(".unused"))) = __LINE__; \
+#define EXPIN(a, b, c...)                                               \
+	static const int _expin_##a##_##b##_##c                         \
+		__attribute__((unused, section(".unused"))) = __LINE__; \
 	BUILD_ASSERT(a < CONFIG_IO_EXPANDER_PORT_COUNT);
 
 #include "gpio.wrap"
diff --git a/include/gpio_signal.h b/include/gpio_signal.h
index 478e83dca5..f48cf4abf0 100644
--- a/include/gpio_signal.h
+++ b/include/gpio_signal.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,6 +8,10 @@
 
 #include "compile_time_macros.h"
 
+#ifdef CONFIG_ZEPHYR
+#include "zephyr_gpio_signal.h"
+#else
+
 /*
  * There are 3 different IO signal types used by the EC.
  * Ensure they each use a unique range of values so we can tell them apart.
@@ -20,10 +24,11 @@
 #define UNIMPLEMENTED(name) GPIO_##name,
 #define GPIO_INT(name, pin, flags, signal) GPIO_##name,
 
+#define GPIO_SIGNAL_NONE -1 /* Invalid signal */
 #define GPIO_SIGNAL_START 0 /* The first valid GPIO signal is 0 */
 
 enum gpio_signal {
-	#include "gpio.wrap"
+#include "gpio.wrap"
 	GPIO_COUNT,
 	/* Ensure that sizeof gpio_signal is large enough for ioex_signal */
 	GPIO_LIMIT = 0x0FFF
@@ -38,7 +43,7 @@ enum ioex_signal {
 	IOEX_SIGNAL_START = GPIO_LIMIT + 1,
 	/* Used to ensure that the first IOEX signal is same as start */
 	__IOEX_PLACEHOLDER = GPIO_LIMIT,
-	#include "gpio.wrap"
+#include "gpio.wrap"
 	IOEX_SIGNAL_END,
 	IOEX_LIMIT = 0x1FFF
 };
@@ -46,4 +51,6 @@ BUILD_ASSERT(IOEX_SIGNAL_END < IOEX_LIMIT);
 
 #define IOEX_COUNT (IOEX_SIGNAL_END - IOEX_SIGNAL_START)
 
+#endif /* !CONFIG_ZEPHYR */
+
 #endif /* __CROS_EC_GPIO_SIGNAL_H */
diff --git a/include/gyro_cal.h b/include/gyro_cal.h
index fb69464aec..fe48d71360 100644
--- a/include/gyro_cal.h
+++ b/include/gyro_cal.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/gyro_still_det.h b/include/gyro_still_det.h
index a776da7ae7..a0332d598a 100644
--- a/include/gyro_still_det.h
+++ b/include/gyro_still_det.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/hooks.h b/include/hooks.h
index 39f558fe12..ea4eb0b480 100644
--- a/include/hooks.h
+++ b/include/hooks.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,9 +12,12 @@
 
 enum hook_priority {
 	/* Generic values across all hooks */
-	HOOK_PRIO_FIRST = 1,       /* Highest priority */
-	HOOK_PRIO_DEFAULT = 5000,  /* Default priority */
-	HOOK_PRIO_LAST = 9999,     /* Lowest priority */
+	HOOK_PRIO_FIRST = 1, /* Highest priority */
+	HOOK_PRIO_POST_FIRST = HOOK_PRIO_FIRST + 1,
+	HOOK_PRIO_DEFAULT = 5000, /* Default priority */
+	HOOK_PRIO_PRE_DEFAULT = HOOK_PRIO_DEFAULT - 1,
+	HOOK_PRIO_POST_DEFAULT = HOOK_PRIO_DEFAULT + 1,
+	HOOK_PRIO_LAST = 9999, /* Lowest priority */
 
 	/* Specific hook vales for HOOK_INIT */
 	/* DMA inits before ADC, I2C, SPI */
@@ -28,18 +31,24 @@ enum hook_priority {
 	 * ones more semantically.
 	 */
 	HOOK_PRIO_INIT_I2C = HOOK_PRIO_FIRST + 2,
+	HOOK_PRIO_PRE_I2C = HOOK_PRIO_INIT_I2C - 1,
+	HOOK_PRIO_POST_I2C = HOOK_PRIO_INIT_I2C + 1,
 	/* Chipset inits before modules which need to know its initial state. */
 	HOOK_PRIO_INIT_CHIPSET = HOOK_PRIO_FIRST + 3,
+	HOOK_PRIO_POST_CHIPSET = HOOK_PRIO_INIT_CHIPSET + 1,
 	/* Lid switch inits before power button */
 	HOOK_PRIO_INIT_LID = HOOK_PRIO_FIRST + 4,
+	HOOK_PRIO_POST_LID = HOOK_PRIO_INIT_LID + 1,
 	/* Power button inits before chipset and switch */
 	HOOK_PRIO_INIT_POWER_BUTTON = HOOK_PRIO_FIRST + 5,
+	HOOK_PRIO_POST_POWER_BUTTON = HOOK_PRIO_INIT_POWER_BUTTON + 1,
 	/* Init switch states after power button / lid */
 	HOOK_PRIO_INIT_SWITCH = HOOK_PRIO_FIRST + 6,
 	/* Init fan before PWM */
 	HOOK_PRIO_INIT_FAN = HOOK_PRIO_FIRST + 7,
 	/* PWM inits before modules which might use it (LEDs) */
 	HOOK_PRIO_INIT_PWM = HOOK_PRIO_FIRST + 8,
+	HOOK_PRIO_POST_PWM = HOOK_PRIO_INIT_PWM + 1,
 	/* SPI inits before modules which might use it (sensors) */
 	HOOK_PRIO_INIT_SPI = HOOK_PRIO_FIRST + 9,
 	/* Extpower inits before modules which might use it (battery, LEDs) */
@@ -47,7 +56,8 @@ enum hook_priority {
 	/* Init VBOOT hash later, since it depends on deferred functions */
 	HOOK_PRIO_INIT_VBOOT_HASH = HOOK_PRIO_FIRST + 11,
 	/* Init charge manager before usage in board init */
-	HOOK_PRIO_CHARGE_MANAGER_INIT = HOOK_PRIO_FIRST + 12,
+	HOOK_PRIO_INIT_CHARGE_MANAGER = HOOK_PRIO_FIRST + 12,
+	HOOK_PRIO_POST_CHARGE_MANAGER = HOOK_PRIO_INIT_CHARGE_MANAGER + 1,
 
 	HOOK_PRIO_INIT_ADC = HOOK_PRIO_DEFAULT,
 	HOOK_PRIO_INIT_DAC = HOOK_PRIO_DEFAULT,
@@ -151,6 +161,13 @@ enum hook_type {
 	 */
 	HOOK_CHIPSET_SHUTDOWN_COMPLETE,
 
+	/*
+	 * System is in G3.  All power rails are now turned off.
+	 *
+	 * Hook routines are called from the chipset task.
+	 */
+	HOOK_CHIPSET_HARD_OFF,
+
 	/*
 	 * System reset in S0.  All rails are still up.
 	 *
@@ -180,6 +197,15 @@ enum hook_type {
 	 */
 	HOOK_TABLET_MODE_CHANGE,
 
+#ifdef CONFIG_BODY_DETECTION
+	/*
+	 * Body dectection mode change.
+	 *
+	 * Hook routines are called from the HOOKS task.
+	 */
+	HOOK_BODY_DETECT_CHANGE,
+#endif
+
 	/*
 	 * Detachable device connected to a base.
 	 *
@@ -196,7 +222,7 @@ enum hook_type {
 	HOOK_POWER_BUTTON_CHANGE,
 
 	/*
-	 * Battery state of charge changed
+	 * Battery state-of-charge changed
 	 *
 	 * Hook routines are called from the charger task.
 	 */
@@ -235,6 +261,27 @@ enum hook_type {
 	 * USB PD cc connection event.
 	 */
 	HOOK_USB_PD_CONNECT,
+
+	/*
+	 * Power supply change event.
+	 */
+	HOOK_POWER_SUPPLY_CHANGE,
+
+#ifdef TEST_BUILD
+	/*
+	 * Special hook types to be used by unit tests of the hooks
+	 * implementation only.
+	 */
+	HOOK_TEST_1,
+	HOOK_TEST_2,
+	HOOK_TEST_3,
+#endif /* TEST_BUILD */
+
+	/*
+	 * Not a hook type (instead the number of hooks). This should
+	 * always be placed at the end of this enumeration.
+	 */
+	HOOK_TYPE_COUNT,
 };
 
 struct hook_data {
@@ -258,6 +305,14 @@ struct hook_data {
  */
 void hook_notify(enum hook_type type);
 
+/*
+ * CONFIG_PLATFORM_EC_HOOKS is enabled by default during a Zephyr
+ * build, but can be disabled via Kconfig if desired (leaving the stub
+ * implementation at the bottom of this file).
+ */
+#if defined(CONFIG_PLATFORM_EC_HOOKS)
+#include "zephyr_hooks_shim.h"
+#elif defined(CONFIG_COMMON_RUNTIME)
 struct deferred_data {
 	/* Deferred function pointer */
 	void (*routine)(void);
@@ -279,12 +334,6 @@ struct deferred_data {
  */
 int hook_call_deferred(const struct deferred_data *data, int us);
 
-/*
- * Hooks are not currently supported by the Zephyr shim.
- * TODO(b/168799177): Implement compatible DECLARE_HOOK macro for
- * Zephyr OS.
- */
-#if defined(CONFIG_COMMON_RUNTIME) && !defined(CONFIG_ZEPHYR)
 /**
  * Register a hook routine.
  *
@@ -311,11 +360,12 @@ int hook_call_deferred(const struct deferred_data *data, int us);
  *			unless there's a compelling reason to care about the
  *			order in which hooks are called.
  */
-#define DECLARE_HOOK(hooktype, routine, priority)			\
-	const struct hook_data __keep __no_sanitize_address		\
-	CONCAT4(__hook_, hooktype, _, routine)				\
-	__attribute__((section(".rodata." STRINGIFY(hooktype))))	\
-	     = {routine, priority}
+#define DECLARE_HOOK(hooktype, routine, priority)                            \
+	const struct hook_data __keep __no_sanitize_address CONCAT4(         \
+		__hook_, hooktype, _, routine)                               \
+		__attribute__((section(".rodata." STRINGIFY(hooktype)))) = { \
+			routine, priority                                    \
+		}
 
 /**
  * Register a deferred function call.
@@ -336,16 +386,26 @@ int hook_call_deferred(const struct deferred_data *data, int us);
  *
  * @param routine	Function pointer, with prototype void routine(void)
  */
-#define DECLARE_DEFERRED(routine)					\
-	const struct deferred_data __keep __no_sanitize_address		\
-	CONCAT2(routine, _data)						\
-	__attribute__((section(".rodata.deferred")))			\
-	     = {routine}
-#else  /* !defined(CONFIG_COMMON_RUNTIME) || defined(CONFIG_ZEPHYR) */
-#define DECLARE_HOOK(t, func, p)				\
-	void CONCAT2(unused_hook_, func)(void) { func(); }
-#define DECLARE_DEFERRED(func)					\
-	void CONCAT2(unused_deferred_, func)(void) { func(); }
+#define DECLARE_DEFERRED(routine)                                        \
+	const struct deferred_data __keep __no_sanitize_address CONCAT2( \
+		routine, _data)                                          \
+		__attribute__((section(".rodata.deferred"))) = { routine }
+#else
+/*
+ * Stub implementation in case hooks are disabled (neither
+ * CONFIG_COMMON_RUNTIME nor CONFIG_PLATFORM_EC_HOOKS is defined)
+ */
+#define hook_call_deferred(unused1, unused2) -1
+#define DECLARE_HOOK(t, func, p)                     \
+	void CONCAT4(unused_hook_, t, _, func)(void) \
+	{                                            \
+		func();                              \
+	}
+#define DECLARE_DEFERRED(func)                     \
+	void CONCAT2(unused_deferred_, func)(void) \
+	{                                          \
+		func();                            \
+	}
 #endif
 
-#endif  /* __CROS_EC_HOOKS_H */
+#endif /* __CROS_EC_HOOKS_H */
diff --git a/include/host_command.h b/include/host_command.h
index 363dd050db..3de47c37ce 100644
--- a/include/host_command.h
+++ b/include/host_command.h
@@ -1,16 +1,26 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Host command module for Chrome EC */
 
+/*
+ * TODO(b/272518464): Work around coreboot GCC preprocessor bug.
+ * #line marks the *next* line, so it is off by one.
+ */
+#line 13
+
 #ifndef __CROS_EC_HOST_COMMAND_H
 #define __CROS_EC_HOST_COMMAND_H
 
 #include "common.h"
+#include "compiler.h"
 #include "ec_commands.h"
-enum power_state;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
 
 /* Args for host command handler */
 struct host_cmd_handler_args {
@@ -20,11 +30,11 @@ struct host_cmd_handler_args {
 	 * send the response back to the host.
 	 */
 	void (*send_response)(struct host_cmd_handler_args *args);
-	uint16_t command;      /* Command (e.g., EC_CMD_FLASH_GET_INFO) */
-	uint8_t version;       /* Version of command (0-31) */
+	uint16_t command; /* Command (e.g., EC_CMD_FLASH_GET_INFO) */
+	uint8_t version; /* Version of command (0-31) */
 
 	const void *params; /* Input parameters */
-	uint16_t params_size;  /* Size of input parameters in bytes */
+	uint16_t params_size; /* Size of input parameters in bytes */
 
 	/*
 	 * Pointer to output response data buffer.  On input to the handler,
@@ -128,17 +138,9 @@ struct host_command {
 	int version_mask;
 };
 
-#ifdef CONFIG_HOST_EVENT64
 typedef uint64_t host_event_t;
-#define HOST_EVENT_CPRINTS(str, e)	CPRINTS("%s 0x%016" PRIx64, str, e)
-#define HOST_EVENT_CCPRINTF(str, e) \
-	ccprintf("%s 0x%016" PRIx64 "\n", str, e)
-
-#else
-typedef uint32_t host_event_t;
-#define HOST_EVENT_CPRINTS(str, e)	CPRINTS("%s 0x%08x", str, e)
-#define HOST_EVENT_CCPRINTF(str, e)	ccprintf("%s 0x%08x\n", str, e)
-#endif
+#define HOST_EVENT_CPRINTS(str, e) CPRINTS("%s 0x%016" PRIx64, str, e)
+#define HOST_EVENT_CCPRINTF(str, e) ccprintf("%s 0x%016" PRIx64 "\n", str, e)
 
 /**
  * Return a pointer to the memory-mapped buffer.
@@ -192,6 +194,8 @@ int host_is_event_set(enum host_event_code event);
 
 #ifdef CONFIG_HOSTCMD_X86
 
+FORWARD_DECLARE_ENUM(power_state);
+
 /*
  * Get lazy wake masks for the sleep state provided
  *
@@ -244,40 +248,58 @@ int host_request_expected_size(const struct ec_host_request *r);
  */
 void host_packet_receive(struct host_packet *pkt);
 
-#ifdef HAS_TASK_HOSTCMD
+/**
+ * Find the handler for a command in Zephyr OS.
+ *
+ * @command		Command to handle (EC_CMD_...)
+ *
+ * Return: handler for the command, or NULL if not found.
+ */
+#ifndef CONFIG_ZEPHYR
+__error("This function should only be called from Zephyr OS code")
+#endif
+	struct host_command *zephyr_find_host_command(int command);
+
+#if defined(CONFIG_ZEPHYR)
+#include "zephyr_host_command.h"
+#elif defined(HAS_TASK_HOSTCMD)
 #define EXPAND(off, cmd) __host_cmd_(off, cmd)
 #define __host_cmd_(off, cmd) __host_cmd_##off##cmd
-#define EXPANDSTR(off, cmd) "__host_cmd_"#off#cmd
+#define EXPANDSTR(off, cmd) "__host_cmd_" #off #cmd
 
 /*
  * Register a host command handler with
  * commands starting at offset 0x0000
  */
-#define DECLARE_HOST_COMMAND(command, routine, version_mask)		\
-	const struct host_command __keep __no_sanitize_address		\
-	EXPAND(0x0000, command)						\
-	__attribute__((section(".rodata.hcmds."EXPANDSTR(0x0000, command)))) \
-		= {routine, command, version_mask}
+#define DECLARE_HOST_COMMAND(command, routine, version_mask)                   \
+	static enum ec_status(routine)(struct host_cmd_handler_args * args);   \
+	const struct host_command __keep __no_sanitize_address EXPAND(0x0000,  \
+								      command) \
+		__attribute__((section(".rodata.hcmds." EXPANDSTR(             \
+			0x0000, command)))) = { routine, command,              \
+						version_mask }
 
 /*
  * Register a private host command handler with
  * commands starting at offset EC_CMD_BOARD_SPECIFIC_BASE,
  */
-#define DECLARE_PRIVATE_HOST_COMMAND(command, routine, version_mask) \
-	const struct host_command __keep __no_sanitize_address	     \
-	EXPAND(EC_CMD_BOARD_SPECIFIC_BASE, command) \
-	__attribute__((section(".rodata.hcmds."\
-	EXPANDSTR(EC_CMD_BOARD_SPECIFIC_BASE, command)))) \
-		= {routine, EC_PRIVATE_HOST_COMMAND_VALUE(command), \
-		   version_mask}
-#else
-#define DECLARE_HOST_COMMAND(command, routine, version_mask)    \
-	enum ec_status (routine)(struct host_cmd_handler_args *args)       \
+#define DECLARE_PRIVATE_HOST_COMMAND(command, routine, version_mask)         \
+	static enum ec_status(routine)(struct host_cmd_handler_args * args); \
+	const struct host_command __keep __no_sanitize_address EXPAND(       \
+		EC_CMD_BOARD_SPECIFIC_BASE, command)                         \
+		__attribute__((section(".rodata.hcmds." EXPANDSTR(           \
+			EC_CMD_BOARD_SPECIFIC_BASE, command)))) = {          \
+			routine, EC_PRIVATE_HOST_COMMAND_VALUE(command),     \
+			version_mask                                         \
+		}
+#else /* !CONFIG_ZEPHYR && !HAS_TASK_HOSTCMD */
+#define DECLARE_HOST_COMMAND(command, routine, version_mask)                \
+	static enum ec_status(routine)(struct host_cmd_handler_args * args) \
 		__attribute__((unused))
 
-#define DECLARE_PRIVATE_HOST_COMMAND(command, routine, version_mask)	\
+#define DECLARE_PRIVATE_HOST_COMMAND(command, routine, version_mask) \
 	DECLARE_HOST_COMMAND(command, routine, version_mask)
-#endif
+#endif /* CONFIG_ZEPHYR */
 
 /**
  * Politely ask the CPU to enable/disable its own throttling.
@@ -286,7 +308,6 @@ void host_packet_receive(struct host_packet *pkt);
  */
 void host_throttle_cpu(int throttle);
 
-
 /**
  * Signal host command task to send status to PD MCU.
  *
@@ -317,8 +338,7 @@ int pd_get_active_charge_port(void);
  * @param indata Pointer to buffer to store response
  * @param insize Size of buffer to store response
  */
-int pd_host_command(int command, int version,
-		    const void *outdata, int outsize,
+int pd_host_command(int command, int version, const void *outdata, int outsize,
 		    void *indata, int insize);
 
 /*
@@ -333,4 +353,73 @@ void host_send_sysrq(uint8_t key);
 uint32_t get_feature_flags0(void);
 uint32_t get_feature_flags1(void);
 
-#endif  /* __CROS_EC_HOST_COMMAND_H */
+#ifdef CONFIG_ZTEST
+static inline void
+stub_send_response_callback(struct host_cmd_handler_args *args)
+{
+	ARG_UNUSED(args);
+}
+
+#define BUILD_HOST_COMMAND(CMD, VERSION, RESPONSE, PARAMS)          \
+	{                                                           \
+		.send_response = stub_send_response_callback,       \
+		.command = (CMD), .version = (VERSION),             \
+		COND_CODE_0(IS_EMPTY(PARAMS),                       \
+			    (.params = &(PARAMS),                   \
+			     .params_size = sizeof(PARAMS)),        \
+			    (.params = NULL, .params_size = 0)),    \
+		COND_CODE_0(IS_EMPTY(RESPONSE),                     \
+			    (.response = &(RESPONSE),               \
+			     .response_max = sizeof(RESPONSE)),     \
+			    (.response = NULL, .response_max = 0)), \
+		.response_size = 0,                                 \
+	}
+
+#define BUILD_HOST_COMMAND_RESPONSE(CMD, VERSION, RESPONSE) \
+	BUILD_HOST_COMMAND(CMD, VERSION, RESPONSE, EMPTY)
+
+#define BUILD_HOST_COMMAND_PARAMS(CMD, VERSION, PARAMS) \
+	BUILD_HOST_COMMAND(CMD, VERSION, EMPTY, PARAMS)
+
+#define BUILD_HOST_COMMAND_SIMPLE(CMD, VERSION) \
+	BUILD_HOST_COMMAND(CMD, VERSION, EMPTY, EMPTY)
+
+#define CROS_EC_COMMAND_INFO struct host_cmd_handler_args
+
+static inline int CROS_EC_COMMAND(CROS_EC_COMMAND_INFO *handle,
+				  uint16_t command, uint8_t version,
+				  const void *params, uint16_t params_size,
+				  void *response, uint16_t response_size)
+{
+	struct host_cmd_handler_args args;
+	int rv;
+
+	if (handle == NULL)
+		handle = &args;
+
+	handle->send_response = stub_send_response_callback;
+	handle->command = command;
+	handle->version = version;
+	handle->params = params;
+	handle->params_size = params_size;
+	handle->response = response;
+	handle->response_max = response_size;
+	handle->response_size = 0;
+	handle->result = 0;
+
+	rv = host_command_process(handle);
+	if (handle->result != EC_RES_SUCCESS)
+		return handle->result;
+
+	return rv;
+}
+
+#include "ec_cmd_api.h"
+
+#endif /* CONFIG_ZTEST */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CROS_EC_HOST_COMMAND_H */
diff --git a/include/host_command_heci.h b/include/host_command_heci.h
index 1dcb054ff6..5595724b59 100644
--- a/include/host_command_heci.h
+++ b/include/host_command_heci.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/host_command_memory_dump.h b/include/host_command_memory_dump.h
new file mode 100644
index 0000000000..3d6db5e091
--- /dev/null
+++ b/include/host_command_memory_dump.h
@@ -0,0 +1,29 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Commands for dumping EC memory */
+
+#ifndef __CROS_EC_HOST_COMMAND_MEMORY_DUMP_H
+#define __CROS_EC_HOST_COMMAND_MEMORY_DUMP_H
+
+#include "stdint.h"
+
+/**
+ * Register a memory range to be included in the memory dump.
+ *
+ * Do not register memory that could potentially contain sensitive data.
+ *
+ * @returns EC_SUCCESS or EC_XXX on error
+ */
+int register_memory_dump(uint32_t address, uint32_t size);
+
+/**
+ * Clear previously registered memory dump.
+ *
+ * @returns EC_SUCCESS or EC_XXX on error
+ */
+int clear_memory_dump(void);
+
+#endif /* __CROS_EC_HOST_COMMAND_MEMORY_DUMP_H */
diff --git a/include/hotword_dsp_api.h b/include/hotword_dsp_api.h
index 369af00ede..311add6675 100644
--- a/include/hotword_dsp_api.h
+++ b/include/hotword_dsp_api.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -44,4 +44,4 @@ int GoogleHotwordDspGetMaximumAudioPreambleMs(void);
 /* Returns an internal version number that this library was built at. */
 extern int GoogleHotwordVersion(void);
 
-#endif  /* SPEECH_MICRO_API_HOTWORD_DSP_API_H_ */
+#endif /* SPEECH_MICRO_API_HOTWORD_DSP_API_H_ */
diff --git a/include/hwtimer.h b/include/hwtimer.h
index 3c0e9aaf8a..9058563e7a 100644
--- a/include/hwtimer.h
+++ b/include/hwtimer.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,6 +8,8 @@
 #ifndef __CROS_EC_HWTIMER_H
 #define __CROS_EC_HWTIMER_H
 
+#include <stdint.h>
+
 /**
  * Programs when the next timer should fire an interrupt.
  *
@@ -34,7 +36,8 @@ void __hw_clock_event_clear(void);
 #ifdef CONFIG_HWTIMER_64BIT
 __override_proto
 #endif
-uint32_t __hw_clock_source_read(void);
+	uint32_t
+	__hw_clock_source_read(void);
 
 /**
  * Override the lower 32-bits of the hardware counter
@@ -115,4 +118,4 @@ void hwtimer_setup_watchdog(void);
 /* Reset the watchdog timer, to avoid the watchdog warning */
 void hwtimer_reset_watchdog(void);
 
-#endif  /* __CROS_EC_HWTIMER_H */
+#endif /* __CROS_EC_HWTIMER_H */
diff --git a/include/i2c.h b/include/i2c.h
index 1ba56e51bf..5ac57ba5b0 100644
--- a/include/i2c.h
+++ b/include/i2c.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,40 +9,42 @@
 #define __CROS_EC_I2C_H
 
 #include "common.h"
-#include "gpio.h"
+#include "gpio_signal.h"
 #include "host_command.h"
 #include "stddef.h"
 
 /*
- * I2C Slave Address encoding
+ * I2C Peripheral Address encoding
  *
  * EC will favor 7bit I2C/SPI address encoding.  The variable/define
  * naming should follow the pattern, if it is just the 7 bit address
  * then end the variable as "addr".  This can be addr, i2c_addr,
- * slave_addr, etc.  If the 7 bit address contains flags for BIG
+ * etc.  If the 7 bit address contains flags for BIG
  * ENDIAN or overloading the address to be a SPI address, then it
  * will be customary to end the variable as "addr_flags".  This can
- * be addr_flags, i2c_addr_flags, slave_addr_flags, etc.
+ * be addr_flags, i2c_addr_flags, etc.
  *
  * Some of the drivers use an 8bit left shifted 7bit address.  Since
  * this is driver specific, it will be up to the driver to make this
  * clear.  I suggest, since this is a very small amount of usage, that
  * ending the variable as "addr_8bit" would make this clear.
  *
- * NOTE: Slave addresses are always 16 bit values.  The least significant
+ * NOTE: Peripheral addresses are always 16 bit values.  The least significant
  * 10 bits are available as an address.  More significant bits are
  * used here and in motion_sense to give specific meaning to the
  * address that is pertinent to its use.
  */
-#define I2C_ADDR_MASK		0x03FF
-#define I2C_FLAG_PEC		BIT(13)
-#define I2C_FLAG_BIG_ENDIAN	BIT(14)
+#define I2C_ADDR_MASK 0x03FF
+#define I2C_FLAG_ADDR16_LITTLE_ENDIAN BIT(12)
+#define I2C_FLAG_PEC BIT(13)
+#define I2C_FLAG_BIG_ENDIAN BIT(14)
 /* BIT(15) SPI_FLAG - used in motion_sense to overload address */
-#define I2C_FLAG_ADDR_IS_SPI	BIT(15)
+#define I2C_FLAG_ADDR_IS_SPI BIT(15)
 
-#define I2C_GET_ADDR(addr_flags)	((addr_flags) & I2C_ADDR_MASK)
-#define I2C_USE_PEC(addr_flags)		((addr_flags) & I2C_FLAG_PEC)
-#define I2C_IS_BIG_ENDIAN(addr_flags)	((addr_flags) & I2C_FLAG_BIG_ENDIAN)
+#define I2C_STRIP_FLAGS(addr_flags) ((addr_flags)&I2C_ADDR_MASK)
+#define I2C_IS_ADDR16_LITTLE_ENDIAN(addr_flags)	((addr_flags) & I2C_FLAG_ADDR16_LITTLE_ENDIAN)
+#define I2C_USE_PEC(addr_flags) ((addr_flags)&I2C_FLAG_PEC)
+#define I2C_IS_BIG_ENDIAN(addr_flags) ((addr_flags)&I2C_FLAG_BIG_ENDIAN)
 
 /*
  * All 7-bit addresses in the following formats
@@ -51,8 +53,8 @@
  * are reserved for various purposes. Valid 7-bit client adderesses start at
  * 0x08 and end at 0x77 inclusive.
  */
-#define I2C_FIRST_VALID_ADDR	0x08
-#define I2C_LAST_VALID_ADDR	0x77
+#define I2C_FIRST_VALID_ADDR 0x08
+#define I2C_LAST_VALID_ADDR 0x77
 
 /*
  * Max data size for a version 3 request/response packet. This is
@@ -67,7 +69,7 @@
 #define I2C_RESPONSE_HEADER_SIZE 2
 
 /* This port allows changing speed at runtime */
-#define I2C_PORT_FLAG_DYNAMIC_SPEED	BIT(0)
+#define I2C_PORT_FLAG_DYNAMIC_SPEED BIT(0)
 
 /*
  * Supported I2C CLK frequencies.
@@ -85,13 +87,10 @@ enum i2c_freq {
  *      MASK_SET will OR the mask into the old value
  *      MASK_CLR will AND the ~mask from the old value
  */
-enum mask_update_action {
-	MASK_CLR,
-	MASK_SET
-};
+enum mask_update_action { MASK_CLR, MASK_SET };
 
 struct i2c_info_t {
-	uint16_t port;	/* Physical port for device */
+	uint16_t port; /* Physical port for device */
 	uint16_t addr_flags;
 };
 
@@ -99,24 +98,25 @@ struct i2c_port_t; /* forward declaration */
 
 struct i2c_drv {
 	int (*xfer)(const struct i2c_port_t *i2c_port,
-		    const uint16_t slave_addr_flags,
-		    const uint8_t *out, int out_size,
+		    const uint16_t addr_flags, const uint8_t *out, int out_size,
 		    uint8_t *in, int in_size, int flags);
 };
 
 /* Data structure to define I2C port configuration. */
 struct i2c_port_t {
-	const char *name;     /* Port name */
-	int port;             /* Port */
-	int kbps;             /* Speed in kbps */
+	int port; /* Port */
+#ifndef CONFIG_ZEPHYR
+	const char *name; /* Port name */
+	int kbps; /* Speed in kbps */
 	enum gpio_signal scl; /* Port SCL GPIO line */
 	enum gpio_signal sda; /* Port SDA GPIO line */
+#endif /* CONFIG_ZEPHYR */
 	/* When bus is protected, returns true if passthru allowed for address.
 	 * If the function is not defined, the default value is true. */
 	int (*passthru_allowed)(const struct i2c_port_t *port,
 				uint16_t addr_flags);
 	const struct i2c_drv *drv;
-	uint16_t flags;       /* I2C_PORT_FLAG_* flags */
+	uint16_t flags; /* I2C_PORT_FLAG_* flags */
 };
 
 extern const struct i2c_port_t i2c_ports[];
@@ -124,27 +124,25 @@ extern const unsigned int i2c_ports_used;
 
 #ifdef CONFIG_CMD_I2C_STRESS_TEST
 struct i2c_test_reg_info {
-	int read_reg;      /* Read register (WHO_AM_I, DEV_ID, MAN_ID) */
-	int read_val;      /* Expected val (WHO_AM_I, DEV_ID, MAN_ID) */
-	int write_reg;     /* Read/Write reg which doesn't impact the system */
+	int read_reg; /* Read register (WHO_AM_I, DEV_ID, MAN_ID) */
+	int read_val; /* Expected val (WHO_AM_I, DEV_ID, MAN_ID) */
+	int write_reg; /* Read/Write reg which doesn't impact the system */
 };
 
 struct i2c_test_results {
-	int read_success;  /* Successful read count */
-	int read_fail;     /* Read fail count */
+	int read_success; /* Successful read count */
+	int read_fail; /* Read fail count */
 	int write_success; /* Successful write count */
-	int write_fail;    /* Write fail count */
+	int write_fail; /* Write fail count */
 };
 
 /* Data structure to define I2C test configuration. */
 struct i2c_stress_test_dev {
 	struct i2c_test_reg_info reg_info;
 	struct i2c_test_results test_results;
-	int (*i2c_read)(const int port,
-			const uint16_t slave_addr_flags,
+	int (*i2c_read)(const int port, const uint16_t addr_flags,
 			const int reg, int *data);
-	int (*i2c_write)(const int port,
-			 const uint16_t slave_addr_flags,
+	int (*i2c_write)(const int port, const uint16_t addr_flags,
 			 const int reg, int data);
 	int (*i2c_read_dev)(const int reg, int *data);
 	int (*i2c_write_dev)(const int reg, int data);
@@ -160,29 +158,36 @@ extern struct i2c_stress_test i2c_stress_tests[];
 extern const int i2c_test_dev_used;
 #endif
 
+/*
+ * Data structure to define I2C Parameters for a command
+ */
+struct i2c_cmd_desc_t {
+	uint8_t port; /* I2C port */
+	uint16_t addr_flags; /* Peripheral address and flags */
+	uint8_t cmd; /* command, only valid on write operations */
+};
+
 /* Flags for i2c_xfer_unlocked() */
-#define I2C_XFER_START BIT(0)  /* Start smbus session from idle state */
-#define I2C_XFER_STOP BIT(1)  /* Terminate smbus session with stop bit */
-#define I2C_XFER_SINGLE (I2C_XFER_START | I2C_XFER_STOP)  /* One transaction */
+#define I2C_XFER_START BIT(0) /* Start smbus session from idle state */
+#define I2C_XFER_STOP BIT(1) /* Terminate smbus session with stop bit */
+#define I2C_XFER_SINGLE (I2C_XFER_START | I2C_XFER_STOP) /* One transaction */
 
 /**
  * Transmit one block of raw data, then receive one block of raw data. However,
- * received data might be capped at CONFIG_I2C_CHIP_MAX_READ_SIZE if
- * CONFIG_I2C_XFER_LARGE_READ is not defined.  The transfer is strictly atomic,
- * by locking the I2C port and performing an I2C_XFER_SINGLE transfer.
+ * transferred data might be capped at CONFIG_I2C_CHIP_MAX_TRANSFER_SIZE if
+ * CONFIG_I2C_XFER_LARGE_TRANSFER is not defined.  The transfer is strictly
+ * atomic, by locking the I2C port and performing an I2C_XFER_SINGLE transfer.
  *
  * @param port		Port to access
- * @param slave_addr	Slave device address
+ * @param addr_flags	Peripheral device address
  * @param out		Data to send
  * @param out_size	Number of bytes to send
  * @param in		Destination buffer for received data
  * @param in_size	Number of bytes to receive
  * @return EC_SUCCESS, or non-zero if error.
  */
-int i2c_xfer(const int port,
-	     const uint16_t slave_addr_flags,
-	     const uint8_t *out, int out_size,
-	     uint8_t *in, int in_size);
+int i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out,
+	     int out_size, uint8_t *in, int in_size);
 
 /**
  * Same as i2c_xfer, but the bus is not implicitly locked.  It must be called
@@ -190,10 +195,9 @@ int i2c_xfer(const int port,
  *
  * @param flags		Flags (see I2C_XFER_* above)
  */
-int i2c_xfer_unlocked(const int port,
-		      const uint16_t slave_addr_flags,
-		      const uint8_t *out, int out_size,
-		      uint8_t *in, int in_size, int flags);
+int i2c_xfer_unlocked(const int port, const uint16_t addr_flags,
+		      const uint8_t *out, int out_size, uint8_t *in,
+		      int in_size, int flags);
 
 #define I2C_LINE_SCL_HIGH BIT(0)
 #define I2C_LINE_SDA_HIGH BIT(1)
@@ -290,124 +294,108 @@ void i2c_prepare_sysjump(void);
 void i2c_set_timeout(int port, uint32_t timeout);
 
 /**
- * Read a 32-bit register from the slave at 7-bit slave address <slaveaddr>, at
- * the specified 8-bit <offset> in the slave's address space.
+ * Read a 32-bit register from the peripheral at 7-bit peripheral address
+ * <addr_flags>, at the specified 8-bit <offset> in the peripheral's address
+ * space.
  */
-int i2c_read32(const int port,
-	       const uint16_t slave_addr_flags,
-	       int offset, int *data);
+int i2c_read32(const int port, const uint16_t addr_flags, int offset,
+	       int *data);
 
 /**
- * Write a 32-bit register to the slave at 7-bit slave address <slaveaddr>, at
- * the specified 8-bit <offset> in the slave's address space.
+ * Write a 32-bit register to the peripheral at 7-bit peripheral address
+ * <addr_flags>, at the specified 8-bit <offset> in the peripheral's address
+ * space.
  */
-int i2c_write32(const int port,
-		const uint16_t slave_addr_flags,
-		int offset, int data);
+int i2c_write32(const int port, const uint16_t addr_flags, int offset,
+		int data);
 
 /**
- * Read a 16-bit register from the slave at 7-bit slave address <slaveaddr>, at
- * the specified 8-bit <offset> in the slave's address space.
+ * Read a 16-bit register from the peripheral at 7-bit peripheral address
+ * <addr_flags>, at the specified 8-bit <offset> in the peripheral's address
+ * space.
  */
-int i2c_read16(const int port,
-	       const uint16_t slave_addr_flags,
-	       int offset, int *data);
+int i2c_read16(const int port, const uint16_t addr_flags, int offset,
+	       int *data);
 
 /**
- * Write a 16-bit register to the slave at 7-bit slave address <slaveaddr>, at
- * the specified 8-bit <offset> in the slave's address space.
+ * Write a 16-bit register to the peripheral at 7-bit peripheral address
+ * <addr_flags>, at the specified 8-bit <offset> in the peripheral's address
+ * space.
  */
-int i2c_write16(const int port,
-		const uint16_t slave_addr_flags,
-		int offset, int data);
+int i2c_write16(const int port, const uint16_t addr_flags, int offset,
+		int data);
 
 /**
- * Read an 8-bit register from the slave at 7-bit slave address <slaveaddr>, at
- * the specified 8-bit <offset> in the slave's address space.
+ * Read an 8-bit register from the peripheral at 7-bit peripheral address
+ * <addr_flags>, at the specified 8-bit <offset> in the peripheral's address
+ * space.
  */
-int i2c_read8(const int port,
-	      const uint16_t slave_addr_flags,
-	      int offset, int *data);
+int i2c_read8(const int port, const uint16_t addr_flags, int offset, int *data);
 
 /**
- * Write an 8-bit register to the slave at 7-bit slave address <slaveaddr>, at
- * the specified 8-bit <offset> in the slave's address space.
+ * Write an 8-bit register to the peripheral at 7-bit peripheral address
+ * <addr_flags>, at the specified 8-bit <offset> in the peripheral's address
+ * space.
  */
-int i2c_write8(const int port,
-	       const uint16_t slave_addr_flags,
-	       int offset, int data);
+int i2c_write8(const int port, const uint16_t addr_flags, int offset, int data);
 
 /**
- * Read, modify, write an i2c register to the slave at 7-bit slave address
- * <slave_addr_flags>, at the specified 8-bit <offset> in the slave's
- * address space.  The <action> will specify whether this is setting the
- * <mask> bit value(s) or clearing them. If the value to be written is the
- * same as the original value of the register, the write will not be
+ * Read, modify, write an i2c register to the peripheral at 7-bit peripheral
+ * address <addr_flags> at the specified 8-bit <offset> in the
+ * peripheral's address space.  The <action> will specify whether this is
+ * setting the <mask> bit value(s) or clearing them. If the value to be written
+ * is the same as the original value of the register, the write will not be
  * performed.
  */
-int i2c_update8(const int port,
-		const uint16_t slave_addr_flags,
-		const int offset,
-		const uint8_t mask,
-		const enum mask_update_action action);
+int i2c_update8(const int port, const uint16_t addr_flags, const int offset,
+		const uint8_t mask, const enum mask_update_action action);
 
-int i2c_update16(const int port,
-		 const uint16_t slave_addr_flags,
-		 const int offset,
-		 const uint16_t mask,
-		 const enum mask_update_action action);
+int i2c_update16(const int port, const uint16_t addr_flags, const int offset,
+		 const uint16_t mask, const enum mask_update_action action);
 
 /**
- * Read, modify, write field of an i2c register to the slave at 7-bit
- * slave address <slave_addr_flags>, at the specified 8-bit <offset> in
- * the slave's address space.  The register will be read, the <field_mask>
+ * Read, modify, write field of an i2c register to the peripheral at 7-bit
+ * peripheral address <addr_flags>, at the specified 8-bit <offset> in
+ * the peripheral's address space.  The register will be read, the <field_mask>
  * will be cleared and then the <set_value> will be set.  The field mask
  * and the set value do not have to be in the same bit locations.  If the
  * new value is not the same as the original value, the new value will be
  * written back out to the device, otherwise no write will be performed.
  */
-int i2c_field_update8(const int port,
-		      const uint16_t slave_addr_flags,
-		      const int offset,
-		      const uint8_t field_mask,
+int i2c_field_update8(const int port, const uint16_t addr_flags,
+		      const int offset, const uint8_t field_mask,
 		      const uint8_t set_value);
 
-int i2c_field_update16(const int port,
-		       const uint16_t slave_addr_flags,
-		       const int offset,
-		       const uint16_t field_mask,
+int i2c_field_update16(const int port, const uint16_t addr_flags,
+		       const int offset, const uint16_t field_mask,
 		       const uint16_t set_value);
 
 /**
- * Read one or two bytes data from the slave at 7-bit slave address
- * * <slaveaddr>, at 16-bit <offset> in the slave's address space.
+ * Read one or two bytes data from the peripheral at 7-bit peripheral address
+ * <addr_flags>, at 16-bit <offset> in the peripheral's address space.
  */
-int i2c_read_offset16(const int port,
-		      const uint16_t slave_addr_flags,
+int i2c_read_offset16(const int port, const uint16_t addr_flags,
 		      uint16_t offset, int *data, int len);
 
 /**
- * Write one or two bytes data to the slave at 7-bit slave address
- * <slaveaddr>, at 16-bit <offset> in the slave's address space.
+ * Write one or two bytes data to the peripheral at 7-bit peripheral address
+ * <addr_flags>, at 16-bit <offset> in the peripheral's address space.
  */
-int i2c_write_offset16(const int port,
-		       const uint16_t slave_addr_flags,
+int i2c_write_offset16(const int port, const uint16_t addr_flags,
 		       uint16_t offset, int data, int len);
 
 /**
- * Read <len> bytes block data from the slave at 7-bit slave address
- * * <slaveaddr>, at 16-bit <offset> in the slave's address space.
+ * Read <len> bytes block data from the peripheral at 7-bit peripheral address
+ * * <addr_flags>, at 16-bit <offset> in the peripheral's address space.
  */
-int i2c_read_offset16_block(const int port,
-			    const uint16_t slave_addr_flags,
+int i2c_read_offset16_block(const int port, const uint16_t addr_flags,
 			    uint16_t offset, uint8_t *data, int len);
 
 /**
- * Write <len> bytes block data to the slave at 7-bit slave address
- * <slaveaddr>, at 16-bit <offset> in the slave's address space.
+ * Write <len> bytes block data to the peripheral at 7-bit peripheral address
+ * <addr_flags>, at 16-bit <offset> in the peripheral's address space.
  */
-int i2c_write_offset16_block(const int port,
-			     const uint16_t slave_addr_flags,
+int i2c_write_offset16_block(const int port, const uint16_t addr_flags,
 			     uint16_t offset, const uint8_t *data, int len);
 
 /**
@@ -424,38 +412,44 @@ int i2c_is_busy(int port);
  */
 int i2c_unwedge(int port);
 
+/**
+ * Read read using  smbus read block protocol.
+ * Read bytestream from <addr_flags>:<offset> with format:
+ *     [length_N] [byte_0] [byte_1] ... [byte_N]
+ *
+ * <len>      : the max length of receiving buffer
+ */
+int i2c_read_sized_block(const int port, const uint16_t addr_flags, int offset,
+			 uint8_t *data, int max_len, int *read_len);
+
 /**
  * Read ascii string using smbus read block protocol.
- * Read bytestream from <slaveaddr>:<offset> with format:
+ * Read bytestream from <addr_flags>:<offset> with format:
  *     [length_N] [byte_0] [byte_1] ... [byte_N-1]
  *
  * <len>      : the max length of receiving buffer. to read N bytes
  *              ascii, len should be at least N+1 to include the
  *              terminating 0.  Similar to strlcpy, the terminating null is
  *              always written into the output buffer.
- * <len> == 0 : buffer size > 255
  */
-int i2c_read_string(const int port,
-		    const uint16_t slave_addr_flags,
-		    int offset, uint8_t *data, int len);
+int i2c_read_string(const int port, const uint16_t addr_flags, int offset,
+		    uint8_t *data, int len);
 
 /**
- * Read a data block of <len> 8-bit transfers from the slave at 7-bit slave
- * address <slaveaddr>, at the specified 8-bit <offset> in the slave's address
- * space.
+ * Read a data block of <len> 8-bit transfers from the peripheral at 7-bit
+ * peripheral address <addr_flags>, at the specified 8-bit <offset> in the
+ * peripheral's address space.
  */
-int i2c_read_block(const int port,
-		   const uint16_t slave_addr_flags,
-		   int offset, uint8_t *data, int len);
+int i2c_read_block(const int port, const uint16_t addr_flags, int offset,
+		   uint8_t *data, int len);
 
 /**
- * Write a data block of <len> 8-bit transfers to the slave at 7-bit slave
- * address <slaveaddr>, at the specified 8-bit <offset> in the slave's address
- * space.
+ * Write a data block of <len> 8-bit transfers to the peripheral at 7-bit
+ * peripheral address <addr_flags>, at the specified 8-bit <offset> in the
+ * peripheral's address space.
  */
-int i2c_write_block(const int port,
-		    const uint16_t slave_addr_flags,
-		    int offset, const uint8_t *data, int len);
+int i2c_write_block(const int port, const uint16_t addr_flags, int offset,
+		    const uint8_t *data, int len);
 
 /**
  * Convert port number to controller number, for multi-port controllers.
@@ -468,22 +462,15 @@ int i2c_write_block(const int port,
  */
 int i2c_port_to_controller(int port);
 
-/**
- * Command handler to get host command protocol information
- *
- * @param args:	host command handler arguments
- * @return	EC_SUCCESS
- */
-enum ec_status i2c_get_protocol_info(struct host_cmd_handler_args *args);
-
 /**
  * Callbacks processing received data and response
  *
- * i2c_data_recived will be called when a slave finishes receiving data and
- * i2c_set_response will be called when a slave is expected to send response.
+ * i2c_data_received will be called when a peripheral finishes receiving data
+ * and i2c_set_response will be called when a peripheral is expected to send a
+ * response.
  *
  * Using these, Chrome OS host command protocol should be separated from
- * i2c slave drivers (e.g. i2c-stm32f0.c, i2c-stm32f3.c).
+ * i2c peripheral drivers (e.g. i2c-stm32f0.c, i2c-stm32f3.c).
  *
  * @param port: I2C port number
  * @param buf:	Buffer containing received data on call and response on return
@@ -494,26 +481,20 @@ void i2c_data_received(int port, uint8_t *buf, int len);
 int i2c_set_response(int port, uint8_t *buf, int len);
 
 /*
- * Initialize i2c master controller. Automatically called at board boot
- * if CONFIG_I2C_MASTER is defined.
+ * Initialize i2c controller. Automatically called at board boot
+ * if CONFIG_I2C_CONTROLLER is defined.
  */
 void i2c_init(void);
 
-/**
- * Initialize i2c master ports. This function can be called for cases where i2c
- * ports are not initialized by default from main.c.
- */
-void i2cm_init(void);
-
 /**
  * Board-level function to determine whether i2c passthru should be allowed
- * on a given port.
+ * on a given I2C command.
  *
- * @parm port I2C port
+ * @parm cmd_desc I2C command
  *
- * @return true, if passthru should be allowed on the port.
+ * @return true, if passthru should be allowed on the I2C command.
  */
-int board_allow_i2c_passthru(int port);
+int board_allow_i2c_passthru(const struct i2c_cmd_desc_t *cmd_desc);
 
 /**
  * Board level function that can indicate if a particular i2c bus is known to be
@@ -531,11 +512,10 @@ int board_is_i2c_port_powered(int port);
  * CONFIG_I2C_XFER_BOARD_CALLBACK.
  *
  * @param port: I2C port number
- * @param slave_addr: Slave device address
+ * @param addr_flags: Peripheral device address
  *
  */
-void i2c_start_xfer_notify(const int port,
-			   const uint16_t slave_addr_flags);
+void i2c_start_xfer_notify(const int port, const uint16_t addr_flags);
 
 /**
  * Function to allow board to take any action after an i2c transaction on a
@@ -543,26 +523,46 @@ void i2c_start_xfer_notify(const int port,
  * CONFIG_I2C_XFER_BOARD_CALLBACK.
  *
  * @param port: I2C port number
- * @param slave_addr: Slave device address
+ * @param addr_flags: Peripheral device address
  *
  */
-void i2c_end_xfer_notify(const int port,
-			 const uint16_t slave_addr_flags);
+void i2c_end_xfer_notify(const int port, const uint16_t addr_flags);
 
 /**
- * Defined in common/i2c_trace.c, used by i2c master to notify tracing
+ * Defined in common/i2c_trace.c, used by i2c controller to notify tracing
  * functionality of transactions.
  *
  * @param port: I2C port number
- * @param slave_addr: slave device address
+ * @param addr_flags: peripheral device address
  * @param out_data: pointer to data written
  * @param out_size: size of data written
  * @param in_data: pointer to data read
  * @param in_size: size of data read
+ * @param ret: return of i2c transaction (EC_SUCCESS or otherwise on failure)
  */
-void i2c_trace_notify(int port, uint16_t slave_addr_flags,
-		      const uint8_t *out_data, size_t out_size,
-		      const uint8_t *in_data, size_t in_size);
+void i2c_trace_notify(int port, uint16_t addr_flags, const uint8_t *out_data,
+		      size_t out_size, const uint8_t *in_data, size_t in_size,
+		      int ret);
+
+/**
+ * Convert an enum i2c_freq constant to numeric frequency in kHz.
+ *
+ * @param freq		An enum i2c_freq constant
+ *
+ * @return The frequency in kHz, or 0 if the input is not a valid
+ *			speed.
+ */
+int i2c_freq_to_khz(enum i2c_freq freq);
+
+/**
+ * Convert a numeric frequency in kHz to an enum i2c_freq constant.
+ *
+ * @param speed_khz	The frequency in kHz
+ *
+ * @return The frequency as an enum i2c_freq constant, or I2C_FREQ_COUNT
+ *			if the input is not a valid speed.
+ */
+enum i2c_freq i2c_khz_to_freq(int speed_khz);
 
 /**
  * Set bus speed. Only support for ports with I2C_PORT_FLAG_DYNAMIC_SPEED
@@ -587,4 +587,10 @@ enum i2c_freq i2c_get_freq(int port);
 /* Find the matching port in i2c_ports[] table. */
 const struct i2c_port_t *get_i2c_port(const int port);
 
-#endif  /* __CROS_EC_I2C_H */
+#ifdef CONFIG_ZTEST
+int i2c_port_is_locked(int port);
+#endif
+
+__test_only void i2c_passthru_protect_reset(void);
+
+#endif /* __CROS_EC_I2C_H */
diff --git a/include/i2c_bitbang.h b/include/i2c_bitbang.h
index f3c07baf76..c9b0587410 100644
--- a/include/i2c_bitbang.h
+++ b/include/i2c_bitbang.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,11 +7,32 @@
 
 #include "i2c.h"
 
+#include <stdbool.h>
+
 extern const struct i2c_drv bitbang_drv;
 
 extern const struct i2c_port_t i2c_bitbang_ports[];
 extern const unsigned int i2c_bitbang_ports_used;
 
+/**
+ * Enable I2C raw mode for the ports which need pre-task
+ * I2C transactions in bitbang mode.
+ *
+ * @param enable Enable/disable the I2C raw mode
+ */
+void enable_i2c_raw_mode(bool enable);
+
+/**
+ * Board level function to initialize I2C peripherals before task starts.
+ *
+ * Note: This requires CONFIG_I2C_BITBANG to be enabled, as the task event
+ * based I2C transactions can only be done in bitbang mode if accessed pre-task.
+ *
+ * Example: I/O expanders can be initialized to utilize GPIOs earlier
+ * than the HOOK task starts.
+ */
+__override_proto void board_pre_task_i2c_peripheral_init(void);
+
 /* expose static functions for testing */
 #ifdef TEST_BUILD
 int bitbang_start_cond(const struct i2c_port_t *i2c_port);
diff --git a/include/i2c_hid.h b/include/i2c_hid.h
index 8568b42837..03b216d3c5 100644
--- a/include/i2c_hid.h
+++ b/include/i2c_hid.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,25 +26,25 @@
  * I2C_HID_HID_DESC_REGISTER is defined in the ACPI table so please make sure
  * you have put in the same value there.
  */
-#define I2C_HID_HID_DESC_REGISTER	0x0001
-#define I2C_HID_REPORT_DESC_REGISTER	0x1000
-#define I2C_HID_INPUT_REPORT_REGISTER	0x2000
-#define I2C_HID_COMMAND_REGISTER	0x3000
-#define I2C_HID_DATA_REGISTER		0x3000
+#define I2C_HID_HID_DESC_REGISTER 0x0001
+#define I2C_HID_REPORT_DESC_REGISTER 0x1000
+#define I2C_HID_INPUT_REPORT_REGISTER 0x2000
+#define I2C_HID_COMMAND_REGISTER 0x3000
+#define I2C_HID_DATA_REGISTER 0x3000
 
 /* I2C-HID commands */
-#define I2C_HID_CMD_RESET		0x01
-#define I2C_HID_CMD_GET_REPORT		0x02
-#define I2C_HID_CMD_SET_REPORT		0x03
-#define I2C_HID_CMD_GET_IDLE		0x04
-#define I2C_HID_CMD_SET_IDLE		0x05
-#define I2C_HID_CMD_GET_PROTOCOL	0x06
-#define I2C_HID_CMD_SET_PROTOCOL	0x07
-#define I2C_HID_CMD_SET_POWER		0x08
+#define I2C_HID_CMD_RESET 0x01
+#define I2C_HID_CMD_GET_REPORT 0x02
+#define I2C_HID_CMD_SET_REPORT 0x03
+#define I2C_HID_CMD_GET_IDLE 0x04
+#define I2C_HID_CMD_SET_IDLE 0x05
+#define I2C_HID_CMD_GET_PROTOCOL 0x06
+#define I2C_HID_CMD_SET_PROTOCOL 0x07
+#define I2C_HID_CMD_SET_POWER 0x08
 
 /* Common HID fields */
-#define I2C_HID_DESC_LENGTH		sizeof(struct i2c_hid_descriptor)
-#define I2C_HID_BCD_VERSION		0x0100
+#define I2C_HID_DESC_LENGTH sizeof(struct i2c_hid_descriptor)
+#define I2C_HID_BCD_VERSION 0x0100
 
 /* I2C-HID HID descriptor */
 struct __packed i2c_hid_descriptor {
diff --git a/include/i2c_hid_touchpad.h b/include/i2c_hid_touchpad.h
index d5d728a488..d425650c40 100644
--- a/include/i2c_hid_touchpad.h
+++ b/include/i2c_hid_touchpad.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,7 +13,7 @@
 #include "stdint.h"
 
 /* Max fingers to support */
-#define I2C_HID_TOUCHPAD_MAX_FINGERS	5
+#define I2C_HID_TOUCHPAD_MAX_FINGERS 5
 
 /*
  * Struct holding a touchpad event
diff --git a/include/i2c_ite_flash_support.h b/include/i2c_ite_flash_support.h
index f70bec877a..241524f4b9 100644
--- a/include/i2c_ite_flash_support.h
+++ b/include/i2c_ite_flash_support.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/i2c_peripheral.h b/include/i2c_peripheral.h
new file mode 100644
index 0000000000..dd4e4b0c7b
--- /dev/null
+++ b/include/i2c_peripheral.h
@@ -0,0 +1,21 @@
+/* Copyright 2019 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* I2C peripheral interface for Chrome EC */
+
+#ifndef __CROS_EC_I2C_PERIPHERAL_H
+#define __CROS_EC_I2C_PERIPHERAL_H
+
+/* Data structure to define I2C peripheral port configuration. */
+struct i2c_periph_port_t {
+	const char *name; /* Port name */
+	int port; /* Port */
+	uint8_t addr; /* address(7-bit without R/W) */
+};
+
+extern const struct i2c_periph_port_t i2c_periph_ports[];
+extern const unsigned int i2c_periphs_used;
+
+#endif /* __CROS_EC_I2C_PERIPHERAL_H */
diff --git a/include/i2c_private.h b/include/i2c_private.h
index 8a92884c16..269b6810bd 100644
--- a/include/i2c_private.h
+++ b/include/i2c_private.h
@@ -1,11 +1,11 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /*
  * Private chipset-specific implementations that only accessible by
- * i2c_master.c. Don't include this directly unless you are implementing
+ * i2c_controller.c. Don't include this directly unless you are implementing
  * these functions.
  */
 #ifndef __CROS_EC_I2C_PRIVATE_H
@@ -21,7 +21,7 @@
  * i2c_xfer().
  *
  * @param port		Port to access
- * @param slave_addr	Slave device address
+ * @param addr_flags	Peripheral device address
  * @param out		Data to send
  * @param out_size	Number of bytes to send
  * @param in		Destination buffer for received data
@@ -29,10 +29,8 @@
  * @param flags		Flags (see I2C_XFER_* above)
  * @return EC_SUCCESS, or non-zero if error.
  */
-int chip_i2c_xfer(const int port,
-		  const uint16_t slave_addr_flags,
-		  const uint8_t *out, int out_size,
-		  uint8_t *in, int in_size, int flags);
+int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out,
+		  int out_size, uint8_t *in, int in_size, int flags);
 
 /**
  * Chip level function to set bus speed.
diff --git a/include/i2c_slave.h b/include/i2c_slave.h
deleted file mode 100644
index 3145d4679b..0000000000
--- a/include/i2c_slave.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* I2C slave interface for Chrome EC */
-
-#ifndef __CROS_EC_I2CSLV_H
-#define __CROS_EC_I2CSLV_H
-
-/* Data structure to define I2C slave port configuration. */
-struct i2c_slv_port_t {
-	const char *name;     /* Port name */
-	int port;             /* Port */
-	uint8_t slave_adr;    /* slave address(7-bit without R/W) */
-};
-
-extern const struct i2c_slv_port_t i2c_slv_ports[];
-extern const unsigned int i2c_slvs_used;
-
-#endif /* __CROS_EC_I2CSLV_H */
diff --git a/include/i8042_protocol.h b/include/i8042_protocol.h
index 7e554fc03e..23f500da17 100644
--- a/include/i8042_protocol.h
+++ b/include/i8042_protocol.h
@@ -1,8 +1,12 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
- * i8042 keyboard protocol constants
+ * i8042 keyboard protocol constants.
+ *
+ * See the IBM PS/2 Hardware Interface Technical Reference Manual
+ *
+ * https://archive.org/details/ps-2-hardware-interface-technical-reference-ocr/PS2HardwareInterfaceTechnicalReference-OCR/page/n371/mode/1up
  */
 
 #ifndef __CROS_EC_I8042_PROTOCOL_H
@@ -10,83 +14,52 @@
 
 /* Some commands appear more than once.  Why? */
 
-/* port 0x60 */
-#define I8042_CMD_MOUSE_1_1     0xe6
-#define I8042_CMD_MOUSE_2_1     0xe7
-#define I8042_CMD_MOUSE_RES     0xe8
-#define I8042_CMD_OK_GETID      0xe8
-#define I8042_CMD_GET_MOUSE     0xe9
-#define I8042_CMD_EX_ENABLE     0xea
-#define I8042_CMD_EX_SETLEDS    0xeb
-#define I8042_CMD_SETLEDS       0xed
-#define I8042_CMD_DIAG_ECHO     0xee
-#define I8042_CMD_GSCANSET      0xf0
-#define I8042_CMD_SSCANSET      0xf0
-#define I8042_CMD_GETID         0xf2
-#define I8042_CMD_SETREP        0xf3
-#define I8042_CMD_ENABLE        0xf4
-#define I8042_CMD_RESET_DIS     0xf5
-#define I8042_CMD_RESET_DEF     0xf6
-#define I8042_CMD_ALL_TYPEM     0xf7
-#define I8042_CMD_SETALL_MB     0xf8
-#define I8042_CMD_SETALL_MBR    0xfa
-#define I8042_CMD_SET_A_KEY_T   0xfb
-#define I8042_CMD_SET_A_KEY_MR  0xfc
-#define I8042_CMD_SET_A_KEY_M   0xfd
-#define I8042_CMD_RESET         0xff
-#define I8042_CMD_RESEND        0xfe
-
 /* port 0x64 */
-#define I8042_READ_CMD_BYTE     0x20
-#define I8042_READ_CTL_RAM      0x21
-#define I8042_READ_CTL_RAM_END  0x3f
-#define I8042_WRITE_CMD_BYTE    0x60  /* expect a byte on port 0x60 */
-#define I8042_WRITE_CTL_RAM     0x61
+#define I8042_READ_CMD_BYTE 0x20
+#define I8042_READ_CTL_RAM 0x21
+#define I8042_READ_CTL_RAM_END 0x3f
+#define I8042_WRITE_CMD_BYTE 0x60 /* expect a byte on port 0x60 */
+#define I8042_WRITE_CTL_RAM 0x61
 #define I8042_WRITE_CTL_RAM_END 0x7f
-#define I8042_ROUTE_AUX0        0x90
-#define I8042_ROUTE_AUX1        0x91
-#define I8042_ROUTE_AUX2        0x92
-#define I8042_ROUTE_AUX3        0x93
-#define I8042_ENA_PASSWORD      0xa6
-#define I8042_DIS_MOUSE         0xa7
-#define I8042_ENA_MOUSE         0xa8
-#define I8042_TEST_MOUSE        0xa9
-#define I8042_RESET_SELF_TEST   0xaa
-#define I8042_TEST_KB_PORT      0xab
-#define I8042_DIS_KB            0xad
-#define I8042_ENA_KB            0xae
-#define I8042_READ_OUTPUT_PORT  0xd0
+#define I8042_ROUTE_AUX0 0x90
+#define I8042_ROUTE_AUX1 0x91
+#define I8042_ROUTE_AUX2 0x92
+#define I8042_ROUTE_AUX3 0x93
+#define I8042_ENA_PASSWORD 0xa6
+#define I8042_DIS_MOUSE 0xa7
+#define I8042_ENA_MOUSE 0xa8
+#define I8042_TEST_MOUSE 0xa9
+#define I8042_TEST_MOUSE_NO_ERROR 0x00
+#define I8042_TEST_MOUSE_CLK_STUCK_LOW 0x01
+#define I8042_TEST_MOUSE_CLK_STUCK_HIGH 0x02
+#define I8042_TEST_MOUSE_DATA_STUCK_LOW 0x03
+#define I8042_TEST_MOUSE_DATA_STUCK_HIGH 0x04
+#define I8042_RESET_SELF_TEST 0xaa
+#define I8042_TEST_KB_PORT 0xab
+#define I8042_DIS_KB 0xad
+#define I8042_ENA_KB 0xae
+#define I8042_READ_OUTPUT_PORT 0xd0
 #define I8042_WRITE_OUTPUT_PORT 0xd1
-#define I8042_ECHO_MOUSE        0xd3  /* expect a byte on port 0x60 */
-#define I8042_SEND_TO_MOUSE     0xd4  /* expect a byte on port 0x60 */
-#define I8042_DISABLE_A20       0xdd
-#define I8042_ENABLE_A20        0xdf
-#define I8042_PULSE_START       0xf0
-#define I8042_SYSTEM_RESET      0xfe
-#define I8042_PULSE_END         0xff
+#define I8042_ECHO_MOUSE 0xd3 /* expect a byte on port 0x60 */
+#define I8042_SEND_TO_MOUSE 0xd4 /* expect a byte on port 0x60 */
+#define I8042_DISABLE_A20 0xdd
+#define I8042_ENABLE_A20 0xdf
+#define I8042_PULSE_START 0xf0
+#define I8042_SYSTEM_RESET 0xfe
+#define I8042_PULSE_END 0xff
 
 /* port 0x60 return value */
-#define I8042_RET_EMUL0         0xe0
-#define I8042_RET_EMUL1         0xe1
-#define I8042_RET_ECHO          0xee
-#define I8042_RET_RELEASE       0xf0
-#define I8042_RET_HANJA         0xf1
-#define I8042_RET_HANGEUL       0xf2
-#define I8042_RET_ACK           0xfa
-#define I8042_RET_TEST_FAIL     0xfc
-#define I8042_RET_INTERNAL_FAIL 0xfd
-#define I8042_RET_NAK           0xfe
-#define I8042_RET_ERR           0xff
+#define I8042_RET_NAK 0xfe
 
 /* port 64 - command byte bits */
-#define I8042_XLATE             BIT(6)
-#define I8042_AUX_DIS           BIT(5)
-#define I8042_KBD_DIS           BIT(4)
-#define I8042_SYS_FLAG          BIT(2)
-#define I8042_ENIRQ12           BIT(1)
-#define I8042_ENIRQ1            BIT(0)
+#define I8042_XLATE BIT(6)
+#define I8042_AUX_DIS BIT(5)
+#define I8042_KBD_DIS BIT(4)
+#define I8042_SYS_FLAG BIT(2)
+#define I8042_ENIRQ12 BIT(1)
+#define I8042_ENIRQ1 BIT(0)
 
 /* Status Flags */
-#define I8042_AUX_DATA		BIT(5)
+#define I8042_AUX_DATA BIT(5)
 
 #endif /* __CROS_EC_I8042_PROTOCOL_H */
diff --git a/include/inductive_charging.h b/include/inductive_charging.h
index 5c44e410aa..d4d1dd4d71 100644
--- a/include/inductive_charging.h
+++ b/include/inductive_charging.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/init_rom.h b/include/init_rom.h
index 6d54e6aec4..8dc6faa630 100644
--- a/include/init_rom.h
+++ b/include/init_rom.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,7 +26,11 @@
  * @return Pointer to data object in memory. Return NULL if the object
  * is not memory mapped.
  */
+#ifdef CONFIG_CHIP_INIT_ROM_REGION
 const void *init_rom_map(const void *addr, int size);
+#else
+#define init_rom_map(addr, size) (addr)
+#endif
 
 /**
  * Unmaps an .init_rom data object. Must be called when init_rom_map() is
@@ -35,7 +39,11 @@ const void *init_rom_map(const void *addr, int size);
  * @param offset	Address of the data object assigned by the linker.
  * @param size	        Size of the data object.
  */
+#ifdef CONFIG_CHIP_INIT_ROM_REGION
 void init_rom_unmap(const void *addr, int size);
+#else
+#define init_rom_unmap(addr, size) (void)0
+#endif
 
 /**
  * Copy an .init_rom data object into a RAM location. This routine must be used
@@ -48,6 +56,10 @@ void init_rom_unmap(const void *addr, int size);
  *
  * @return 0 on success.
  */
+#ifdef CONFIG_CHIP_INIT_ROM_REGION
 int init_rom_copy(int offset, int size, char *data);
+#else
+#define init_rom_copy(offset, size, data) 0
+#endif
 
 #endif /* __CROS_EC_INIT_ROM_H */
diff --git a/include/ioexpander.h b/include/ioexpander.h
index ebdb4ac652..5717b10743 100644
--- a/include/ioexpander.h
+++ b/include/ioexpander.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,6 +7,13 @@
 #ifndef __CROS_EC_IOEXPANDER_H
 #define __CROS_EC_IOEXPANDER_H
 
+#ifdef CONFIG_ZEPHYR
+#define ioex_signal gpio_signal
+#include "gpio.h"
+#else
+enum ioex_signal; /* from gpio_signal.h */
+#endif
+
 /* IO expander signal definition structure */
 struct ioex_info {
 	/* Signal name */
@@ -27,9 +34,12 @@ struct ioex_info {
 
 /* Signal information from board.c.  Must match order from enum ioex_signal. */
 extern const struct ioex_info ioex_list[];
-extern void (* const ioex_irq_handlers[])(enum ioex_signal signal);
+extern void (*const ioex_irq_handlers[])(enum ioex_signal signal);
 extern const int ioex_ih_count;
 
+/* Get ioex_info structure for specified signal */
+#define IOEX_GET_INFO(signal) (ioex_list + (signal)-IOEX_SIGNAL_START)
+
 struct ioexpander_drv {
 	/* Initialize IO expander chip/driver */
 	int (*init)(int ioex);
@@ -43,16 +53,28 @@ struct ioexpander_drv {
 	int (*set_flags_by_mask)(int ioex, int port, int mask, int flags);
 	/* Enable/disable interrupt for the IOEX pin */
 	int (*enable_interrupt)(int ioex, int port, int mask, int enable);
+#ifdef CONFIG_IO_EXPANDER_SUPPORT_GET_PORT
+	/* Read levels for whole IOEX port */
+	int (*get_port)(int ioex, int port, int *val);
+#endif
 };
 
-/* IO expander chip disabled. No I2C communication will be attempted. */
-#define IOEX_FLAGS_DISABLED	BIT(0)
+/* IO expander default init disabled. No I2C communication will be attempted. */
+#define IOEX_FLAGS_DEFAULT_INIT_DISABLED BIT(0)
+/* IO Expander has been initialized */
+#define IOEX_FLAGS_INITIALIZED BIT(1)
+
+/*
+ * BITS 24 to 31 are used by io-expander drivers that need to control multiple
+ * devices
+ */
+#define IOEX_FLAGS_CUSTOM_BIT(x) BUILD_CHECK_INLINE(BIT(x), BIT(x) & 0xff000000)
 
 struct ioexpander_config_t {
 	/* Physical I2C port connects to the IO expander chip. */
 	int i2c_host_port;
-	/* I2C slave address */
-	int i2c_slave_addr;
+	/* I2C address */
+	int i2c_addr_flags;
 	/*
 	 * Pointer to the specific IO expander chip's ops defined in
 	 * the struct ioexpander_drv.
@@ -64,6 +86,46 @@ struct ioexpander_config_t {
 
 extern struct ioexpander_config_t ioex_config[];
 
+#ifdef CONFIG_ZEPHYR
+
+#define ioex_enable_interrupt gpio_enable_interrupt
+#define ioex_disable_interrupt gpio_disable_interrupt
+
+#ifdef CONFIG_GPIO_GET_EXTENDED
+static inline int ioex_get_flags(enum gpio_signal signal, int *flags)
+{
+	*flags = gpio_get_flags(signal);
+	return EC_SUCCESS;
+}
+#endif
+
+static inline int ioex_set_flags(enum gpio_signal signal, int flags)
+{
+	gpio_set_flags(signal, flags);
+	return EC_SUCCESS;
+}
+
+static inline int ioex_get_level(enum gpio_signal signal, int *val)
+{
+	*val = gpio_get_level(signal);
+	return EC_SUCCESS;
+}
+
+static inline int ioex_set_level(enum gpio_signal signal, int val)
+{
+	gpio_set_level(signal, val);
+	return EC_SUCCESS;
+}
+
+int ioex_init(int ioex);
+
+static inline const char *ioex_get_name(enum ioex_signal signal)
+{
+	return gpio_get_name(signal);
+}
+
+#else
+
 /*
  * Enable the interrupt for the IOEX signal
  *
@@ -80,6 +142,16 @@ int ioex_enable_interrupt(enum ioex_signal signal);
  */
 int ioex_disable_interrupt(enum ioex_signal signal);
 
+/*
+ * Get io expander flags (IOEX_FLAGS_*) for chip that specified IOEX signal
+ * belongs to. They contain information if port was disabled or initialized.
+ *
+ * @param signal IOEX signal that belongs to chip which flags will be returned
+ * @param val	 Pointer to memory where flags will be stored
+ * @return	 EC_SUCCESS if successful, non-zero if error.
+ */
+int ioex_get_ioex_flags(enum ioex_signal signal, int *val);
+
 /*
  * Get flags for the IOEX signal
  *
@@ -116,6 +188,18 @@ int ioex_get_level(enum ioex_signal signal, int *val);
  */
 int ioex_set_level(enum ioex_signal signal, int value);
 
+#ifdef CONFIG_IO_EXPANDER_SUPPORT_GET_PORT
+/*
+ * Get the current levels on the IOEX port
+ *
+ * @param ioex		Number of I/O expander
+ * @param port		Number of port in ioex
+ * @param val		Pointer to variable where port will be read
+ * @return			EC_SUCCESS if successful, non-zero if error.
+ */
+int ioex_get_port(int ioex, int port, int *val);
+#endif
+
 /*
  * Initialize IO expander chip/driver
  *
@@ -140,4 +224,26 @@ const char *ioex_get_name(enum ioex_signal signal);
  */
 int signal_is_ioex(int signal);
 
+/*
+ * Save gpio state of IO expander
+ *
+ * @param ioex		IO expander chip's port number
+ * @param state		Buffer to hold gpio state
+ * @param state_len	Length of state buffer, IOEX_COUNT is recommended
+ * @return		EC_SUCCESS if successful, non-zero if error.
+ */
+int ioex_save_gpio_state(int ioex, int *state, int state_len);
+
+/*
+ * Restore gpio state of IO expander
+ *
+ * @param ioex		IO expander chip's port number
+ * @param state		Buffer with gpio state saved by ioex_save_gpio_state
+ * @param state_len	Length of state buffer, IOEX_COUNT is recommended
+ * @return		EC_SUCCESS if successful, non-zero if error.
+ */
+int ioex_restore_gpio_state(int ioex, const int *state, int state_len);
+
+#endif /* CONFIG_ZEPHYR */
+
 #endif /* __CROS_EC_IOEXPANDER_H */
diff --git a/include/kasa.h b/include/kasa.h
index 6157b5632d..06e5c29dbe 100644
--- a/include/kasa.h
+++ b/include/kasa.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/keyboard_8042.h b/include/keyboard_8042.h
index 8c54122e81..68a1c1a74e 100644
--- a/include/keyboard_8042.h
+++ b/include/keyboard_8042.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,8 +8,9 @@
 #ifndef __CROS_EC_KEYBOARD_8042_H
 #define __CROS_EC_KEYBOARD_8042_H
 
-#include "common.h"
 #include "button.h"
+#include "common.h"
+#include "stdbool.h"
 
 /**
  * Called by power button handler and button interrupt handler.
@@ -58,14 +59,47 @@ void send_aux_data_to_host_interrupt(uint8_t data);
  * @param data	Aux data to send to device.
  */
 void send_aux_data_to_device(uint8_t data);
+#ifdef CONFIG_BOARD_AZALEA
+/**
+ * Pauses or resumes the i8042 device -> host queue.
+ *
+ * We cannot send any IRQs before the eSPI virtual wire channel has been
+ * enabled. This method will allow deferring sending data to the host.
+ *
+ */
+void i8042_pause_to_host_queue(bool pause);
+#endif
+/**
+ * Get the amount of free 8042 buffer slots
+ * this is used to put backpressure on the host
+ * if the keyboard task gets too slow
+ * @return bytes_avaliable
+ */
+int keyboard_host_write_avaliable(void);
 
-/*
- * This function can help change the keyboard top row layout as presented to the
- * AP. If changing the position of the "Refresh" key from T3, you may also need
- * to change KEYBOARD_ROW_REFRESH accordingly so that recovery mode can work on
- * the EC side of things (also see related CONFIG_KEYBOARD_REFRESH_ROW3)
+#ifdef TEST_BUILD
+
+/**
+ * @brief Expose function for testing to set typematic scan code
+ *
+ * @param scan_code Pointer to byte array with scan code
+ * @param len Length of scan code in number of bytes
+ */
+void set_typematic_key(const uint8_t *scan_code, int32_t len);
+
+/**
+ * @brief Force-set the resend command buffer for testing.
+ *
+ * @param data Pointer to command to copy from
+ * @param length Number of bytes to copy (capped at MAX_SCAN_CODE_LEN)
+ */
+__test_only void test_keyboard_8042_set_resend_command(const uint8_t *data,
+						       int length);
+
+/**
+ * @brief Reset typematic, RAM, and scancode set for testing purposes.
  */
-__override_proto
-const struct ec_response_keybd_config *board_vivaldi_keybd_config(void);
+__test_only void test_keyboard_8042_reset(void);
+#endif /* TEST_BUILD */
 
-#endif  /* __CROS_EC_KEYBOARD_8042_H */
+#endif /* __CROS_EC_KEYBOARD_8042_H */
diff --git a/include/keyboard_8042_sharedlib.h b/include/keyboard_8042_sharedlib.h
index 8abde3d1d5..d5ade8f0c6 100644
--- a/include/keyboard_8042_sharedlib.h
+++ b/include/keyboard_8042_sharedlib.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -12,11 +12,21 @@
 #include "keyboard_config.h"
 #include "keyboard_protocol.h"
 
+#include <stddef.h>
+
 struct button_8042_t {
 	uint16_t scancode;
 	int repeat;
 };
 
+/**
+ * Register scancode set for the standard ChromeOS keyboard matrix set 2.
+ *
+ * @param scancode_set	Scancode set to register.
+ * @param size		Size of the scancode set in bytes.
+ */
+void register_scancode_set2(uint16_t *scancode_set, size_t size);
+
 /**
  * Get the standard Chrome OS keyboard matrix set 2 scanset
  * @param row	Row number
@@ -37,42 +47,42 @@ extern const uint8_t scancode_translate_table[];
 extern uint8_t scancode_translate_set2_to_1(uint8_t code);
 
 #ifdef CONFIG_KEYBOARD_DEBUG
-#define KEYCAP_LONG_LABEL_BIT   (0x80)
-#define KEYCAP_LONG_LABEL_INDEX_BITMASK		(~KEYCAP_LONG_LABEL_BIT)
+#define KEYCAP_LONG_LABEL_BIT (0x80)
+#define KEYCAP_LONG_LABEL_INDEX_BITMASK (~KEYCAP_LONG_LABEL_BIT)
 
 enum keycap_long_label_idx {
-	KLLI_UNKNO = 0x80,		/* UNKNOWN */
-	KLLI_F1    = 0x81,		/* F1 or PREVIOUS */
-	KLLI_F2    = 0x82,		/* F2 or NEXT */
-	KLLI_F3    = 0x83,		/* F3 or REFRESH */
-	KLLI_F4    = 0x84,		/* F4 or FULL_SCREEN */
-	KLLI_F5    = 0x85,		/* F5 or OVERVIEW */
-	KLLI_F6    = 0x86,		/* F6 or DIM */
-	KLLI_F7    = 0x87,		/* F7 or BRIGHT */
-	KLLI_F8    = 0x88,		/* F8 or MUTE */
-	KLLI_F9    = 0x89,		/* F9 or VOLUME DOWN */
-	KLLI_F10   = 0x8A,		/* F10 or VOLUME UP */
-	KLLI_F11   = 0x8B,		/* F11 or POWER */
-	KLLI_F12   = 0x8C,		/* F12 or DEV TOOLS */
-	KLLI_F13   = 0x8D,		/* F13 or GOOGLE ASSISTANT */
-	KLLI_F14   = 0x8E,		/* F14 */
-	KLLI_F15   = 0x8F,		/* F15 */
-	KLLI_L_ALT = 0x90,		/* LEFT ALT */
-	KLLI_R_ALT = 0x91,		/* RIGHT ALT */
-	KLLI_L_CTR = 0x92,		/* LEFT CONTROL */
-	KLLI_R_CTR = 0x93,		/* RIGHT CONTROL */
-	KLLI_L_SHT = 0x94,		/* LEFT SHIFT */
-	KLLI_R_SHT = 0x95,		/* RIGHT SHIFT */
-	KLLI_ENTER = 0x96,		/* ENTER */
-	KLLI_SPACE = 0x97,		/* SPACE */
-	KLLI_B_SPC = 0x98,		/* BACk SPACE*/
-	KLLI_TAB   = 0x99,		/* TAB */
-	KLLI_SEARC = 0x9A,		/* SEARCH */
-	KLLI_LEFT  = 0x9B,		/* LEFT ARROW */
-	KLLI_RIGHT = 0x9C,		/* RIGHT ARROW */
-	KLLI_DOWN  = 0x9D,		/* DOWN ARROW */
-	KLLI_UP    = 0x9E,		/* UP ARROW */
-	KLLI_ESC   = 0x9F,		/* ESCAPE */
+	KLLI_UNKNO = 0x80, /* UNKNOWN */
+	KLLI_F1 = 0x81, /* F1 or PREVIOUS */
+	KLLI_F2 = 0x82, /* F2 or NEXT */
+	KLLI_F3 = 0x83, /* F3 or REFRESH */
+	KLLI_F4 = 0x84, /* F4 or FULL_SCREEN */
+	KLLI_F5 = 0x85, /* F5 or OVERVIEW */
+	KLLI_F6 = 0x86, /* F6 or DIM */
+	KLLI_F7 = 0x87, /* F7 or BRIGHT */
+	KLLI_F8 = 0x88, /* F8 or MUTE */
+	KLLI_F9 = 0x89, /* F9 or VOLUME DOWN */
+	KLLI_F10 = 0x8A, /* F10 or VOLUME UP */
+	KLLI_F11 = 0x8B, /* F11 or POWER */
+	KLLI_F12 = 0x8C, /* F12 or DEV TOOLS */
+	KLLI_F13 = 0x8D, /* F13 or GOOGLE ASSISTANT */
+	KLLI_F14 = 0x8E, /* F14 */
+	KLLI_F15 = 0x8F, /* F15 */
+	KLLI_L_ALT = 0x90, /* LEFT ALT */
+	KLLI_R_ALT = 0x91, /* RIGHT ALT */
+	KLLI_L_CTR = 0x92, /* LEFT CONTROL */
+	KLLI_R_CTR = 0x93, /* RIGHT CONTROL */
+	KLLI_L_SHT = 0x94, /* LEFT SHIFT */
+	KLLI_R_SHT = 0x95, /* RIGHT SHIFT */
+	KLLI_ENTER = 0x96, /* ENTER */
+	KLLI_SPACE = 0x97, /* SPACE */
+	KLLI_B_SPC = 0x98, /* BACk SPACE*/
+	KLLI_TAB = 0x99, /* TAB */
+	KLLI_SEARC = 0x9A, /* SEARCH */
+	KLLI_LEFT = 0x9B, /* LEFT ARROW */
+	KLLI_RIGHT = 0x9C, /* RIGHT ARROW */
+	KLLI_DOWN = 0x9D, /* DOWN ARROW */
+	KLLI_UP = 0x9E, /* UP ARROW */
+	KLLI_ESC = 0x9F, /* ESCAPE */
 	KLLI_MAX
 };
 
@@ -89,14 +99,14 @@ const char *get_keycap_long_label(uint8_t idx);
  * @param col	Column number
  * @return	KLLI_UNKNO on error, label for the (row,col) if successful
  */
-char get_keycap_label(uint8_t row, uint8_t col);
+uint8_t get_keycap_label(uint8_t row, uint8_t col);
 /**
  * Set the keycap label
  * @param row	Row number
  * @param col	Column number
  * @param val	Value to set
  */
-void set_keycap_label(uint8_t row, uint8_t col, char val);
+void set_keycap_label(uint8_t row, uint8_t col, uint8_t val);
 #endif
 
 /* Button scancodes (Power, Volume Down, Volume Up, etc.) */
@@ -117,39 +127,41 @@ enum scancode_values {
 	SCANCODE_B = 0x0032,
 	SCANCODE_T = 0x002c,
 
-	SCANCODE_F1 = 0x0005,	/* Translates to 3b in codeset 1 */
-	SCANCODE_F2 = 0x0006,	/* Translates to 3c in codeset 1 */
-	SCANCODE_F3 = 0x0004,	/* Translates to 3d in codeset 1 */
-	SCANCODE_F4 = 0x000c,	/* Translates to 3e in codeset 1 */
-	SCANCODE_F5 = 0x0003,	/* Translates to 3f in codeset 1 */
-	SCANCODE_F6 = 0x000b,	/* Translates to 40 in codeset 1 */
-	SCANCODE_F7 = 0x0083,	/* Translates to 41 in codeset 1 */
-	SCANCODE_F8 = 0x000a,	/* Translates to 42 in codeset 1 */
-	SCANCODE_F9 = 0x0001,	/* Translates to 43 in codeset 1 */
-	SCANCODE_F10 = 0x0009,	/* Translates to 44 in codeset 1 */
-	SCANCODE_F11 = 0x0078,	/* Translates to 57 in codeset 1 */
-	SCANCODE_F12 = 0x0007,	/* Translates to 58 in codeset 1 */
-	SCANCODE_F13 = 0x000f,	/* Translates to 59 in codeset 1 */
-	SCANCODE_F14 = 0x0017,	/* Translates to 5a in codeset 1 */
-	SCANCODE_F15 = 0x001f,	/* Translates to 5b in codeset 1 */
-
-	SCANCODE_BACK =	0xe038,			/* e06a in codeset 1 */
-	SCANCODE_REFRESH = 0xe020,		/* e067 in codeset 1 */
-	SCANCODE_FORWARD = 0xe030,		/* e069 in codeset 1 */
-	SCANCODE_FULLSCREEN = 0xe01d,		/* e011 in codeset 1 */
-	SCANCODE_OVERVIEW = 0xe024,		/* e012 in codeset 1 */
-	SCANCODE_SNAPSHOT = 0xe02d,		/* e013 in codeset 1 */
-	SCANCODE_BRIGHTNESS_DOWN = 0xe02c,	/* e014 in codeset 1 */
-	SCANCODE_BRIGHTNESS_UP = 0xe035,	/* e015 in codeset 1 */
-	SCANCODE_PRIVACY_SCRN_TOGGLE = 0xe03c,	/* e016 in codeset 1 */
-	SCANCODE_VOLUME_MUTE = 0xe023,		/* e020 in codeset 1 */
-	SCANCODE_VOLUME_DOWN = 0xe021,		/* e02e in codeset 1 */
-	SCANCODE_VOLUME_UP = 0xe032,		/* e030 in codeset 1 */
-	SCANCODE_KBD_BKLIGHT_DOWN = 0xe043,	/* e017 in codeset 1 */
-	SCANCODE_KBD_BKLIGHT_UP = 0xe044,	/* e018 in codeset 1 */
-	SCANCODE_NEXT_TRACK = 0xe04d,		/* e019 in codeset 1 */
-	SCANCODE_PREV_TRACK = 0xe015,		/* e010 in codeset 1 */
-	SCANCODE_PLAY_PAUSE = 0xe054,		/* e01a in codeset 1 */
+	SCANCODE_F1 = 0x0005, /* Translates to 3b in codeset 1 */
+	SCANCODE_F2 = 0x0006, /* Translates to 3c in codeset 1 */
+	SCANCODE_F3 = 0x0004, /* Translates to 3d in codeset 1 */
+	SCANCODE_F4 = 0x000c, /* Translates to 3e in codeset 1 */
+	SCANCODE_F5 = 0x0003, /* Translates to 3f in codeset 1 */
+	SCANCODE_F6 = 0x000b, /* Translates to 40 in codeset 1 */
+	SCANCODE_F7 = 0x0083, /* Translates to 41 in codeset 1 */
+	SCANCODE_F8 = 0x000a, /* Translates to 42 in codeset 1 */
+	SCANCODE_F9 = 0x0001, /* Translates to 43 in codeset 1 */
+	SCANCODE_F10 = 0x0009, /* Translates to 44 in codeset 1 */
+	SCANCODE_F11 = 0x0078, /* Translates to 57 in codeset 1 */
+	SCANCODE_F12 = 0x0007, /* Translates to 58 in codeset 1 */
+	SCANCODE_F13 = 0x000f, /* Translates to 59 in codeset 1 */
+	SCANCODE_F14 = 0x0017, /* Translates to 5a in codeset 1 */
+	SCANCODE_F15 = 0x001f, /* Translates to 5b in codeset 1 */
+
+	SCANCODE_BACK = 0xe038, /* e06a in codeset 1 */
+	SCANCODE_REFRESH = 0xe020, /* e067 in codeset 1 */
+	SCANCODE_FORWARD = 0xe030, /* e069 in codeset 1 */
+	SCANCODE_FULLSCREEN = 0xe01d, /* e011 in codeset 1 */
+	SCANCODE_OVERVIEW = 0xe024, /* e012 in codeset 1 */
+	SCANCODE_SNAPSHOT = 0xe02d, /* e013 in codeset 1 */
+	SCANCODE_BRIGHTNESS_DOWN = 0xe02c, /* e014 in codeset 1 */
+	SCANCODE_BRIGHTNESS_UP = 0xe035, /* e015 in codeset 1 */
+	SCANCODE_PRIVACY_SCRN_TOGGLE = 0xe03c, /* e016 in codeset 1 */
+	SCANCODE_VOLUME_MUTE = 0xe023, /* e020 in codeset 1 */
+	SCANCODE_VOLUME_DOWN = 0xe021, /* e02e in codeset 1 */
+	SCANCODE_VOLUME_UP = 0xe032, /* e030 in codeset 1 */
+	SCANCODE_KBD_BKLIGHT_DOWN = 0xe043, /* e017 in codeset 1 */
+	SCANCODE_KBD_BKLIGHT_UP = 0xe044, /* e018 in codeset 1 */
+	SCANCODE_KBD_BKLIGHT_TOGGLE = 0xe01c, /* e01e in codeset 1 */
+	SCANCODE_NEXT_TRACK = 0xe04d, /* e019 in codeset 1 */
+	SCANCODE_PREV_TRACK = 0xe015, /* e010 in codeset 1 */
+	SCANCODE_PLAY_PAUSE = 0xe054, /* e01a in codeset 1 */
+	SCANCODE_MICMUTE = 0xe05b, /* e01b in codeset 1 */
 
 	SCANCODE_UP = 0xe075,
 	SCANCODE_DOWN = 0xe072,
@@ -161,7 +173,7 @@ enum scancode_values {
 	SCANCODE_LEFT_ALT = 0x0011,
 	SCANCODE_RIGHT_ALT = 0xe011,
 
-	SCANCODE_LEFT_WIN = 0xe01f,  /* Also known as GUI or Super key. */
+	SCANCODE_LEFT_WIN = 0xe01f, /* Also known as GUI or Super key. */
 	SCANCODE_RIGHT_WIN = 0xe027,
 	SCANCODE_MENU = 0xe02f,
 
@@ -172,6 +184,23 @@ enum scancode_values {
 	SCANCODE_SCROLL_LOCK = 0x007e,
 
 	SCANCODE_CTRL_BREAK = 0xe07e,
-};
 
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+	SCANCODE_FN = 0x00ff,
+	SCANCODE_ESC = 0x0076,
+	SCANCODE_DELETE = 0xe071,
+	SCANCODE_K = 0x0042,
+	SCANCODE_P = 0x004D,
+	SCANCODE_S = 0x001B,
+	SCANCODE_SPACE = 0x0029,
+
+	SCANCODE_FAKE_FN = 0xe016,
+	SCANCODE_FAKE_POWER = 0xe025,
+	SCANCODE_UNASSIGNED = 0x0040,
+#endif /* CONFIG_CUSTOMIZED_DESIGN */
+};
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+void board_caps_led_control(int data);
+void simulate_keyboard(uint16_t scancode, int is_pressed);
+#endif /* CONFIG_CUSTOMIZED_DESIGN */
 #endif /* __CROS_EC_KEYBOARD_8042_SHAREDLIB_H */
diff --git a/include/keyboard_backlight.h b/include/keyboard_backlight.h
index 2389b3dfe0..929dbfa90e 100644
--- a/include/keyboard_backlight.h
+++ b/include/keyboard_backlight.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,6 +6,13 @@
 #ifndef __CROS_EC_KEYBOARD_BACKLIGHT_H
 #define __CROS_EC_KEYBOARD_BACKLIGHT_H
 
+/**
+ * If GPIO_EN_KEYBOARD_BACKLIGHT is defined, this GPIO will be set when
+ * the the keyboard backlight is enabled or disabled. This GPIO is used
+ * to enable or disable the power to the keyboard backlight circuitry.
+ * GPIO_EN_KEYBOARD_BACKLIGHT must be active high.
+ */
+
 struct kblight_conf {
 	const struct kblight_drv *drv;
 };
@@ -24,24 +31,29 @@ struct kblight_drv {
 	 */
 	int (*set)(int percent);
 
-	/**
-	 * Get the current brightness
-	 * @return Brightness in percentage
-	 */
-	int (*get)(void);
-
 	/**
 	 * Enable or disable keyboard backlight
 	 * @param enable: 1=Enable, 0=Disable.
 	 * @return EC_SUCCESS or EC_ERROR_*
 	 */
 	int (*enable)(int enable);
+
+	/**
+	 * Get the enabled state.
+	 * @return 1=Enable, 0=Disable, -1=Failed to read enabled state.
+	 */
+	int (*get_enabled)(void);
 };
 
 /**
  * Initialize keyboard backlight per board
  */
-void board_kblight_init(void);
+__override_proto void board_kblight_init(void);
+
+/**
+ * Shutdown keyboard backlight
+ */
+__override_proto void board_kblight_shutdown(void);
 
 /**
  * Set keyboard backlight brightness
@@ -76,4 +88,16 @@ int kblight_register(const struct kblight_drv *drv);
 
 extern const struct kblight_drv kblight_pwm;
 
+#ifdef TEST_BUILD
+/**
+ * @brief Get internal backlight enabled state. The value reported by
+ *        kblight_get_enabled() can be outdated due to a deferred function call
+ *        being required to update it. Using this function in tests improves
+ *        reliability and reduces the need to sleep.
+ *
+ * @return uint8_t 0 if disabled, 1 otherwise.
+ */
+uint8_t kblight_get_current_enable(void);
+#endif /* TEST_BUILD */
+
 #endif /* __CROS_EC_KEYBOARD_BACKLIGHT_H */
diff --git a/include/keyboard_config.h b/include/keyboard_config.h
index 2e6a6eb80d..997fe88a2b 100644
--- a/include/keyboard_config.h
+++ b/include/keyboard_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,14 +14,10 @@
 /* include the board layer keyboard header file */
 #include "keyboard_customization.h"
 #else /* CONFIG_KEYBOARD_CUSTOMIZATION */
-#ifdef CONFIG_KEYBOARD_LANGUAGE_ID
-/* Keyboard matrix support for language ID pins */
-#define KEYBOARD_IDS 2
-#endif
 
 /* Keyboard matrix is 13 (or 15 with keypad) output columns x 8 input rows */
-#define KEYBOARD_COLS_WITH_KEYPAD	15
-#define KEYBOARD_COLS_NO_KEYPAD		13
+#define KEYBOARD_COLS_WITH_KEYPAD 15
+#define KEYBOARD_COLS_NO_KEYPAD 13
 
 /*
  * KEYBOARD_COLS_MAX has the build time column size. It's used to allocate
@@ -44,59 +40,59 @@ extern uint8_t keyboard_cols;
 #define KEYBOARD_ROW_TO_MASK(r) (1 << (r))
 
 /* Columns and masks for keys we particularly care about */
-#define KEYBOARD_COL_DOWN	11
-#define KEYBOARD_ROW_DOWN	6
-#define KEYBOARD_MASK_DOWN	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_DOWN)
-#define KEYBOARD_COL_ESC	1
-#define KEYBOARD_ROW_ESC	1
-#define KEYBOARD_MASK_ESC	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_ESC)
-#define KEYBOARD_COL_KEY_H	6
-#define KEYBOARD_ROW_KEY_H	1
-#define KEYBOARD_MASK_KEY_H	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_H)
-#define KEYBOARD_COL_KEY_R	3
-#define KEYBOARD_ROW_KEY_R	7
-#define KEYBOARD_MASK_KEY_R	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_R)
-#define KEYBOARD_COL_LEFT_ALT	10
-#define KEYBOARD_ROW_LEFT_ALT	6
-#define KEYBOARD_MASK_LEFT_ALT	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_ALT)
-#define KEYBOARD_COL_REFRESH	2
+#define KEYBOARD_COL_DOWN 11
+#define KEYBOARD_ROW_DOWN 6
+#define KEYBOARD_MASK_DOWN KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_DOWN)
+#define KEYBOARD_COL_ESC 1
+#define KEYBOARD_ROW_ESC 1
+#define KEYBOARD_MASK_ESC KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_ESC)
+#define KEYBOARD_COL_KEY_H 6
+#define KEYBOARD_ROW_KEY_H 1
+#define KEYBOARD_MASK_KEY_H KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_H)
+#define KEYBOARD_COL_KEY_R 3
+#define KEYBOARD_ROW_KEY_R 7
+#define KEYBOARD_MASK_KEY_R KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_R)
+#define KEYBOARD_COL_LEFT_ALT 10
+#define KEYBOARD_ROW_LEFT_ALT 6
+#define KEYBOARD_MASK_LEFT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_ALT)
+#define KEYBOARD_COL_REFRESH 2
 #ifdef CONFIG_KEYBOARD_REFRESH_ROW3
-#define KEYBOARD_ROW_REFRESH	3
+#define KEYBOARD_ROW_REFRESH 3
 #else
-#define KEYBOARD_ROW_REFRESH	2
+#define KEYBOARD_ROW_REFRESH 2
 #endif
-#define KEYBOARD_MASK_REFRESH	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_REFRESH)
-#define KEYBOARD_COL_RIGHT_ALT	10
-#define KEYBOARD_ROW_RIGHT_ALT	0
-#define KEYBOARD_MASK_RIGHT_ALT	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_ALT)
-#define KEYBOARD_DEFAULT_COL_VOL_UP	4
-#define KEYBOARD_DEFAULT_ROW_VOL_UP	0
-#define KEYBOARD_COL_LEFT_CTRL  0
-#define KEYBOARD_ROW_LEFT_CTRL  2
+#define KEYBOARD_MASK_REFRESH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_REFRESH)
+#define KEYBOARD_COL_RIGHT_ALT 10
+#define KEYBOARD_ROW_RIGHT_ALT 0
+#define KEYBOARD_MASK_RIGHT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_ALT)
+#define KEYBOARD_DEFAULT_COL_VOL_UP 4
+#define KEYBOARD_DEFAULT_ROW_VOL_UP 0
+#define KEYBOARD_COL_LEFT_CTRL 0
+#define KEYBOARD_ROW_LEFT_CTRL 2
 #define KEYBOARD_MASK_LEFT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_CTRL)
 #define KEYBOARD_COL_RIGHT_CTRL 0
 #define KEYBOARD_ROW_RIGHT_CTRL 4
 #define KEYBOARD_MASK_RIGHT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_CTRL)
-#define KEYBOARD_COL_SEARCH     1
-#define KEYBOARD_ROW_SEARCH     0
-#define KEYBOARD_MASK_SEARCH    KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_SEARCH)
-#define KEYBOARD_COL_KEY_0      8
-#define KEYBOARD_ROW_KEY_0      6
-#define KEYBOARD_MASK_KEY_0     KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_0)
-#define KEYBOARD_COL_KEY_1      1
-#define KEYBOARD_ROW_KEY_1      6
-#define KEYBOARD_MASK_KEY_1     KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_1)
-#define KEYBOARD_COL_KEY_2      4
-#define KEYBOARD_ROW_KEY_2      6
-#define KEYBOARD_MASK_KEY_2     KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_2)
+#define KEYBOARD_COL_SEARCH 1
+#define KEYBOARD_ROW_SEARCH 0
+#define KEYBOARD_MASK_SEARCH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_SEARCH)
+#define KEYBOARD_COL_KEY_0 8
+#define KEYBOARD_ROW_KEY_0 6
+#define KEYBOARD_MASK_KEY_0 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_0)
+#define KEYBOARD_COL_KEY_1 1
+#define KEYBOARD_ROW_KEY_1 6
+#define KEYBOARD_MASK_KEY_1 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_1)
+#define KEYBOARD_COL_KEY_2 4
+#define KEYBOARD_ROW_KEY_2 6
+#define KEYBOARD_MASK_KEY_2 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_2)
 #define KEYBOARD_COL_LEFT_SHIFT 7
 #define KEYBOARD_ROW_LEFT_SHIFT 5
 #define KEYBOARD_MASK_LEFT_SHIFT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_SHIFT)
 #ifdef CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2
-#define KEYBOARD_MASK_PWRBTN	KEYBOARD_ROW_TO_MASK(2)
+#define KEYBOARD_MASK_PWRBTN KEYBOARD_ROW_TO_MASK(2)
 #elif defined(CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI3)
-#define KEYBOARD_MASK_PWRBTN	KEYBOARD_ROW_TO_MASK(3)
+#define KEYBOARD_MASK_PWRBTN KEYBOARD_ROW_TO_MASK(3)
 #endif
 
 #endif /* CONFIG_KEYBOARD_CUSTOMIZATION */
-#endif  /* __CROS_EC_KEYBOARD_CONFIG_H */
+#endif /* __CROS_EC_KEYBOARD_CONFIG_H */
diff --git a/include/keyboard_mkbp.h b/include/keyboard_mkbp.h
index cc1dec04b2..ff2344937b 100644
--- a/include/keyboard_mkbp.h
+++ b/include/keyboard_mkbp.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -9,6 +9,7 @@
 #define __CROS_EC_KEYBOARD_MKBP_H
 
 #include "common.h"
+#include "ec_commands.h"
 #include "keyboard_config.h"
 
 /**
@@ -16,37 +17,10 @@
  *
  * @return EC_SUCCESS if entry added, EC_ERROR_OVERFLOW if FIFO is full
  */
-int keyboard_fifo_add(const uint8_t *buffp);
+int mkbp_keyboard_add(const uint8_t *buffp);
 
-/**
- * Add an element to the common MKBP FIFO.
- *
- * @param event_type	The MKBP event type.
- * @param buffp		Pointer to the event data to enqueue.
- * @return EC_SUCCESS if entry added, EC_ERROR_OVERFLOW if FIFO is full.
- */
-int mkbp_fifo_add(uint8_t event_type, const uint8_t *buffp);
-
-/**
- * Clear the MKBP common FIFO.
- */
-void mkbp_clear_fifo(void);
-
-/**
- * Send KEY_BATTERY keystroke.
- */
-#ifdef CONFIG_KEYBOARD_PROTOCOL_MKBP
-void keyboard_send_battery_key(void);
-#else
-static inline void keyboard_send_battery_key(void) { }
+#ifdef TEST_BUILD
+void get_keyscan_config(struct ec_mkbp_config *dst);
 #endif
 
-/**
- * Update the state of the switches.
- *
- * @param sw		The switch that changed.
- * @param state		The state of the switch.
- */
-void mkbp_update_switches(uint32_t sw, int state);
-
-#endif  /* __CROS_EC_KEYBOARD_MKBP_H */
+#endif /* __CROS_EC_KEYBOARD_MKBP_H */
diff --git a/include/keyboard_protocol.h b/include/keyboard_protocol.h
index 2e3fcf205b..8f10c7bd0e 100644
--- a/include/keyboard_protocol.h
+++ b/include/keyboard_protocol.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,8 +8,8 @@
 #ifndef __CROS_EC_KEYBOARD_PROTOCOL_H
 #define __CROS_EC_KEYBOARD_PROTOCOL_H
 
-#include "common.h"
 #include "button.h"
+#include "common.h"
 
 /* Routines common to all protocols */
 
@@ -39,7 +39,9 @@ void keyboard_update_button(enum keyboard_button_type button, int is_pressed);
 /* MKBP protocol takes the whole keyboard matrix, and does not care about
  * individual key presses.
  */
-static inline void keyboard_state_changed(int row, int col, int is_pressed) {}
+static inline void keyboard_state_changed(int row, int col, int is_pressed)
+{
+}
 #else
 /**
  * Called by keyboard scan code once any key state change (after de-bounce),
@@ -54,4 +56,13 @@ void keyboard_state_changed(int row, int col, int is_pressed);
  */
 int board_has_keyboard_backlight(void);
 
-#endif  /* __CROS_EC_KEYBOARD_PROTOCOL_H */
+/*
+ * This function can help change the keyboard top row layout as presented to the
+ * AP. If changing the position of the "Refresh" key from T3, you may also need
+ * to change KEYBOARD_ROW_REFRESH accordingly so that recovery mode can work on
+ * the EC side of things (also see related CONFIG_KEYBOARD_REFRESH_ROW3)
+ */
+__override_proto const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void);
+
+#endif /* __CROS_EC_KEYBOARD_PROTOCOL_H */
diff --git a/include/keyboard_raw.h b/include/keyboard_raw.h
index 6c8ecc3b2a..8ce26c5d39 100644
--- a/include/keyboard_raw.h
+++ b/include/keyboard_raw.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,14 +11,16 @@
 #ifndef __CROS_EC_KEYBOARD_RAW_H
 #define __CROS_EC_KEYBOARD_RAW_H
 
-#include "assert.h"
+#include "builtin/assert.h"
 #include "common.h"
-#include "gpio.h"
+#include "gpio_signal.h"
 #include "keyboard_config.h"
 
+#include <stdbool.h>
+
 /* Column values for keyboard_raw_drive_column() */
 enum keyboard_column_index {
-	KEYBOARD_COLUMN_ALL = -2,  /* Drive all columns */
+	KEYBOARD_COLUMN_ALL = -2, /* Drive all columns */
 	KEYBOARD_COLUMN_NONE = -1, /* Drive no columns (tri-state all) */
 	/* 0 ~ KEYBOARD_COLS_MAX-1 for the corresponding column */
 };
@@ -62,6 +64,14 @@ int keyboard_raw_read_rows(void);
  */
 void keyboard_raw_enable_interrupt(int enable);
 
+/**
+ * Enable or disable keyboard alternative function.
+ *
+ * @param enable 1 enable KSI/KSO alternative function,
+ *               0 set all KSI/KSO pins to normal GPIO.
+ */
+void keybaord_raw_config_alt(bool enable);
+
 #ifdef HAS_TASK_KEYSCAN
 
 /**
@@ -70,7 +80,9 @@ void keyboard_raw_enable_interrupt(int enable);
 void keyboard_raw_gpio_interrupt(enum gpio_signal signal);
 
 #else
-static inline void keyboard_raw_gpio_interrupt(enum gpio_signal signal) { }
+static inline void keyboard_raw_gpio_interrupt(enum gpio_signal signal)
+{
+}
 #endif /* !HAS_TASK_KEYSCAN */
 
 /**
@@ -89,20 +101,17 @@ int keyboard_factory_test_scan(void);
  */
 int keyboard_raw_is_input_low(int port, int id);
 
-static inline int keyboard_raw_get_cols(void) {
+static inline int keyboard_raw_get_cols(void)
+{
 	return keyboard_cols;
 }
 
-static inline void keyboard_raw_set_cols(int cols) {
-#ifdef CONFIG_KEYBOARD_LANGUAGE_ID
-	/* Keyboard ID is probably encoded right after the last column. Scanner
-	 * would read keyboard ID if the column size is decreased. */
-	assert(cols == KEYBOARD_COLS_MAX);
-#else
+static inline void keyboard_raw_set_cols(int cols)
+{
 	/* We can only decrease the column size. You have to assume a larger
 	 * grid (and reduce scanning size if the keyboard has no keypad). */
 	assert(cols <= KEYBOARD_COLS_MAX);
-#endif
+
 	keyboard_cols = cols;
 }
 
@@ -118,4 +127,4 @@ static inline void keyboard_raw_set_cols(int cols) {
 void board_keyboard_drive_col(int col);
 #endif
 
-#endif  /* __CROS_EC_KEYBOARD_RAW_H */
+#endif /* __CROS_EC_KEYBOARD_RAW_H */
diff --git a/include/keyboard_scan.h b/include/keyboard_scan.h
index e74bfcea33..544f973946 100644
--- a/include/keyboard_scan.h
+++ b/include/keyboard_scan.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -32,6 +32,16 @@ struct keyboard_scan_config {
 	uint32_t poll_timeout_us;
 	/* Mask with 1 bits only for keys that actually exist */
 	uint8_t actual_key_mask[KEYBOARD_COLS_MAX];
+#ifdef CONFIG_KEYBOARD_SCAN_ADC
+	/* KSI threshold ADC voltage in mV */
+	uint16_t ksi_threshold_mv;
+#endif
+};
+
+/* Boot key list.  Must be in same order as enum boot_key. */
+struct boot_key_entry {
+	uint8_t col;
+	uint8_t row;
 };
 
 /**
@@ -46,7 +56,7 @@ struct keyboard_scan_config *keyboard_scan_get_config(void);
 /*
  * Which is probably this.
  */
-extern struct keyboard_scan_config keyscan_config;
+__override_proto extern struct keyboard_scan_config keyscan_config;
 
 /* Key held down at keyboard-controlled reset boot time. */
 enum boot_key {
@@ -85,10 +95,10 @@ const uint8_t *keyboard_scan_get_state(void);
 
 enum kb_scan_disable_masks {
 	/* Reasons why keyboard scanning should be disabled */
-	KB_SCAN_DISABLE_LID_CLOSED   = (1<<0),
-	KB_SCAN_DISABLE_POWER_BUTTON = (1<<1),
-	KB_SCAN_DISABLE_LID_ANGLE    = (1<<2),
-	KB_SCAN_DISABLE_USB_SUSPENDED = (1<<3),
+	KB_SCAN_DISABLE_LID_CLOSED = (1 << 0),
+	KB_SCAN_DISABLE_POWER_BUTTON = (1 << 1),
+	KB_SCAN_DISABLE_LID_ANGLE = (1 << 2),
+	KB_SCAN_DISABLE_USB_SUSPENDED = (1 << 3),
 };
 
 #ifdef HAS_TASK_KEYSCAN
@@ -107,32 +117,79 @@ void keyboard_scan_enable(int enable, enum kb_scan_disable_masks mask);
 void clear_typematic_key(void);
 #else
 static inline void keyboard_scan_enable(int enable,
-		enum kb_scan_disable_masks mask) { }
+					enum kb_scan_disable_masks mask)
+{
+}
+#endif
+
+#ifdef CONFIG_KEYBOARD_RUNTIME_KEYS
+void set_vol_up_key(uint8_t row, uint8_t col);
+#else
+static inline void set_vol_up_key(uint8_t row, uint8_t col)
+{
+}
+#endif
+
+#ifdef CONFIG_KEYBOARD_FACTORY_TEST
+/*
+ * Map keyboard connector pins to EC GPIO pins for factory test.
+ * Pins mapped to {-1, -1} are skipped.
+ */
+extern const int keyboard_factory_scan_pins[][2];
+extern const int keyboard_factory_scan_pins_used;
 #endif
 
-#ifdef CONFIG_KEYBOARD_SUPPRESS_NOISE
+#ifdef CONFIG_KEYBOARD_MULTIPLE
+extern struct boot_key_entry boot_key_list[3];
+
+struct keyboard_type {
+	int col_esc;
+	int row_esc;
+	int col_down;
+	int row_down;
+	int col_left_shift;
+	int row_left_shift;
+	int col_refresh;
+	int row_refresh;
+	int col_right_alt;
+	int row_right_alt;
+	int col_left_alt;
+	int row_left_alt;
+	int col_key_r;
+	int row_key_r;
+	int col_key_h;
+	int row_key_h;
+};
+
+extern struct keyboard_type key_typ;
+#endif
+
+#ifdef TEST_BUILD
 /**
- * Indicate to audio codec that a key has been pressed.
+ * @brief Get the value of print_state_changes
  *
- * Boards may supply this function to suppress audio noise.
+ * @return non-zero if state change printing is enabled, zero if not.
  */
-void keyboard_suppress_noise(void);
-#endif
+__test_only int keyboard_scan_get_print_state_changes(void);
 
-#ifdef CONFIG_KEYBOARD_LANGUAGE_ID
 /**
- * Get the KEYBOARD ID for a keyboard
+ * @brief Forcibly set the value of print_state_changes
  *
- * @return A value that identifies keyboard variants. Its meaning and
- * the number of bits actually used is the supported keyboard layout.
+ * @param val Value to set
  */
-int keyboard_get_keyboard_id(void);
-#endif
+__test_only void keyboard_scan_set_print_state_changes(int val);
 
-#ifdef CONFIG_KEYBOARD_RUNTIME_KEYS
-void set_vol_up_key(uint8_t row, uint8_t col);
-#else
-static inline void set_vol_up_key(uint8_t row, uint8_t col) {}
-#endif
+/**
+ * @brief Checks if keyboard scanning is currently enabled.
+ *
+ * @return int non-zero if enabled, zero otherwise.
+ */
+int keyboard_scan_is_enabled(void);
+
+/**
+ * @brief Reset key debouncing logic
+ */
+void test_keyboard_scan_debounce_reset(void);
+#endif /* TEST_BUILD */
 
-#endif  /* __CROS_EC_KEYBOARD_SCAN_H */
+#endif /* __CROS_EC_KEYBOARD_SCAN_H */
diff --git a/include/keyboard_test.h b/include/keyboard_test.h
index 142cff5e53..be12f08372 100644
--- a/include/keyboard_test.h
+++ b/include/keyboard_test.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2013 The Chromium OS Authors. All rights reserved.
+ * Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,9 +16,9 @@
  * logic.
  */
 struct keyscan_item {
-	timestamp_t abs_time;	/* absolute timestamp to present this item */
-	uint32_t time_us;	/* time for this item relative to test start */
-	uint8_t done;		/* 1 if we managed to present this */
+	timestamp_t abs_time; /* absolute timestamp to present this item */
+	uint32_t time_us; /* time for this item relative to test start */
+	uint8_t done; /* 1 if we managed to present this */
 	uint8_t scan[KEYBOARD_COLS_MAX];
 };
 
diff --git a/include/lb_common.h b/include/lb_common.h
index 327c810cad..29f666d33b 100644
--- a/include/lb_common.h
+++ b/include/lb_common.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
+ * Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -38,4 +38,4 @@ void lb_hc_cmd_reg(const struct ec_params_lightbar *in);
  */
 int lb_power(int enabled);
 
-#endif  /* __CROS_EC_LB_COMMON_H */
+#endif /* __CROS_EC_LB_COMMON_H */
diff --git a/include/led_common.h b/include/led_common.h
index a66455b008..71c8211fec 100644
--- a/include/led_common.h
+++ b/include/led_common.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,12 +10,22 @@
 
 #include "ec_commands.h"
 
-/* Defined in led_<board>.c */
+/* Defined in led_<board>.c, not needed if led_is_supported is overridden */
 extern const enum ec_led_id supported_led_ids[];
 
-/* Defined in led_<board>.c */
+/* Defined in led_<board>.c, not needed if led_is_supported is overridden */
 extern const int supported_led_ids_count;
 
+/**
+ * Whether an LED is supported.
+ *
+ * @param led_id	ID of LED to query.
+ *
+ * @returns		1 if LED is supported. 0 if it is not.
+ *
+ */
+__override_proto int led_is_supported(enum ec_led_id led_id);
+
 /**
  * Enable or disable automatic control of an LED.
  *
@@ -69,11 +79,17 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness);
 void led_enable(int enable);
 
 enum ec_led_state {
-	LED_STATE_OFF   = 0,
-	LED_STATE_ON    = 1,
+	LED_STATE_OFF = 0,
+	LED_STATE_ON = 1,
 	LED_STATE_RESET = 2,
 };
 
+/**
+ * Check the LED state while receive the auto control
+ * command.
+ */
+void board_led_auto_control(void);
+
 /**
  * Control state of LED.
  *
diff --git a/include/led_onoff_states.h b/include/led_onoff_states.h
index e8c3e67cb2..bfad06aabc 100644
--- a/include/led_onoff_states.h
+++ b/include/led_onoff_states.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,19 +10,15 @@
 
 #include "ec_commands.h"
 
-#define LED_INDEFINITE	UINT8_MAX
-#define LED_ONE_SEC	(1000 / HOOK_TICK_INTERVAL_MS)
-#define LED_OFF         EC_LED_COLOR_COUNT
+#define LED_INDEFINITE UINT8_MAX
+#define LED_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS)
+#define LED_OFF EC_LED_COLOR_COUNT
 
 /*
  * All LED states should have one phase defined,
  * and an additional phase can be defined for blinking
  */
-enum led_phase {
-	LED_PHASE_0,
-	LED_PHASE_1,
-	LED_NUM_PHASES
-};
+enum led_phase { LED_PHASE_0, LED_PHASE_1, LED_NUM_PHASES };
 
 /*
  * STATE_CHARGING_LVL_1 is when 0 <= charge_percentage < led_charge_level_1
@@ -53,45 +49,36 @@ struct led_descriptor {
 	uint8_t time;
 };
 
-
-/* Charging LED state table - defined in board's led.c */
-extern struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES];
-
-/* Charging LED state level 1 - defined in board's led.c */
 extern const int led_charge_lvl_1;
-
-/* Charging LED state level 2 - defined in board's led.c */
 extern const int led_charge_lvl_2;
 
-#ifdef CONFIG_LED_POWER_LED
 enum pwr_led_states {
 	PWR_LED_STATE_ON,
 	PWR_LED_STATE_SUSPEND_AC,
 	PWR_LED_STATE_SUSPEND_NO_AC,
 	PWR_LED_STATE_OFF,
+	PWR_LED_STATE_OFF_LOW_POWER, /* Falls back to OFF if not defined */
 	PWR_LED_NUM_STATES
 };
 
-/* Power LED state table - defined in board's led.c */
-extern const struct led_descriptor
-			led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES];
-
-#endif
-
 /**
- * Set battery LED color - defined in board's led.c
+ * Set battery LED color - defined in board's led.c if supported, along with:
+ *	- led_bat_state_table
+ *	- led_charge_lvl_1
+ *	- led_charge_lvl_2
  *
  * @param color		Color to set on battery LED
  *
  */
-void led_set_color_battery(enum ec_led_colors color);
+__override_proto void led_set_color_battery(enum ec_led_colors color);
 
-#ifdef CONFIG_LED_POWER_LED
 /**
- * Set power LED color - defined in board's led.c
+ * Set power LED color - defined in board's led.c if supported, along with:
+ *	- led_pwr_state_table
  */
-void led_set_color_power(enum ec_led_colors color);
-#endif
+__override_proto void led_set_color_power(enum ec_led_colors color);
+
+__override_proto enum led_states
+board_get_led_state(enum led_states desired_state);
 
 #endif /* __CROS_EC_ONOFFSTATES_LED_H */
diff --git a/include/led_pwm.h b/include/led_pwm.h
index 42f2f5caad..1c8cec9ff4 100644
--- a/include/led_pwm.h
+++ b/include/led_pwm.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,7 +8,22 @@
 
 #include "ec_commands.h"
 
-#define PWM_LED_NO_CHANNEL -1
+#ifdef CONFIG_ZEPHYR
+#include <zephyr/drivers/pwm.h>
+#endif
+
+#ifdef CONFIG_ZEPHYR
+#define PWM_LED_NO_CHANNEL NULL
+
+struct pwm_led {
+	const struct pwm_dt_spec *ch0;
+	const struct pwm_dt_spec *ch1;
+	const struct pwm_dt_spec *ch2;
+
+	void (*set_duty)(const struct pwm_dt_spec *pwm, int percent);
+};
+#else
+#define PWM_LED_NO_CHANNEL ((enum pwm_channel)(-1))
 
 struct pwm_led {
 	enum pwm_channel ch0;
@@ -18,6 +33,13 @@ struct pwm_led {
 	void (*enable)(enum pwm_channel ch, int enabled);
 	void (*set_duty)(enum pwm_channel ch, int percent);
 };
+#endif
+
+struct pwm_led_color_map {
+	uint8_t ch0;
+	uint8_t ch1;
+	uint8_t ch2;
+};
 
 enum pwm_led_id {
 	PWM_LED0 = 0,
@@ -35,7 +57,7 @@ enum pwm_led_id {
  * all applicable channels.  (e.g. A bi-color LED which has a red and green
  * channel should define all 0s for EC_LED_COLOR_BLUE and EC_LED_COLOR_WHITE.)
  */
-extern struct pwm_led led_color_map[EC_LED_COLOR_COUNT];
+extern struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT];
 
 /*
  * A map of the PWM channels to logical PWM LEDs.
diff --git a/include/libsharedobjs.h b/include/libsharedobjs.h
index 3801ccaca0..ee767ff127 100644
--- a/include/libsharedobjs.h
+++ b/include/libsharedobjs.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -17,7 +17,7 @@
  * NOTE: I know that this doesn't cover all possible cases, but it will catch
  *       an obvious case.
  */
-#if (CONFIG_RO_MEM_OFF ==  CONFIG_RW_MEM_OFF)
+#if (CONFIG_RO_MEM_OFF == CONFIG_RW_MEM_OFF)
 #error "The shared library is NOT compatible with this EC."
 #endif
 
@@ -28,12 +28,12 @@
  */
 #undef SHAREDLIB
 #ifdef SHAREDLIB_IMAGE
-#define SHAREDLIB(...) __attribute__ ((section(".roshared"))) __VA_ARGS__
+#define SHAREDLIB(...) __attribute__((section(".roshared"))) __VA_ARGS__
 #else /* !defined(SHAREDLIB_IMAGE) */
 #define SHAREDLIB(...)
 #endif /* defined(SHAREDLIB_IMAGE) */
 #define SHAREDLIB_FUNC(...) \
-	extern __VA_ARGS__ __attribute__ ((section(".roshared.text")))
+	extern __VA_ARGS__ __attribute__((section(".roshared.text")))
 
 #else /* !defined(CONFIG_SHAREDLIB) */
 
diff --git a/include/lid_angle.h b/include/lid_angle.h
index 22eec683f7..8836c91238 100644
--- a/include/lid_angle.h
+++ b/include/lid_angle.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -30,6 +30,6 @@ void lid_angle_set_wake_angle(int ang);
  *
  * @param enable Flag that enables or disables peripherals.
  */
-void lid_angle_peripheral_enable(int enable);
+__override_proto void lid_angle_peripheral_enable(int enable);
 
-#endif  /* __CROS_EC_LID_ANGLE_H */
+#endif /* __CROS_EC_LID_ANGLE_H */
diff --git a/include/lid_switch.h b/include/lid_switch.h
index a999abdda7..8b62d89949 100644
--- a/include/lid_switch.h
+++ b/include/lid_switch.h
@@ -1,14 +1,26 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Lid switch API for Chrome EC */
 
+/*
+ * TODO(b/272518464): Work around coreboot GCC preprocessor bug.
+ * #line marks the *next* line, so it is off by one.
+ */
+#line 13
+
 #ifndef __CROS_EC_LID_SWITCH_H
 #define __CROS_EC_LID_SWITCH_H
 
 #include "common.h"
+#include "stdbool.h"
+
+/**
+ * Debounce time for lid switch
+ */
+#define LID_DEBOUNCE_US (30 * MSEC)
 
 /**
  * Return non-zero if lid is open.
@@ -24,4 +36,11 @@ int lid_is_open(void);
  */
 void lid_interrupt(enum gpio_signal signal);
 
-#endif  /* __CROS_EC_LID_SWITCH_H */
+/**
+ * Disable lid interrupt and set the lid open, when base is disconnected.
+ *
+ * @param enable    Flag that enables or disables lid interrupt.
+ */
+void enable_lid_detect(bool enable);
+
+#endif /* __CROS_EC_LID_SWITCH_H */
diff --git a/include/lightbar.h b/include/lightbar.h
index 2c8c143922..e86701cac2 100644
--- a/include/lightbar.h
+++ b/include/lightbar.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,26 +13,13 @@
 /* Define the types of sequences */
 #define LBMSG(state) LIGHTBAR_##state
 #include "lightbar_msg_list.h"
-enum lightbar_sequence {
-	LIGHTBAR_MSG_LIST
-	LIGHTBAR_NUM_SEQUENCES
-};
+enum lightbar_sequence { LIGHTBAR_MSG_LIST LIGHTBAR_NUM_SEQUENCES };
 #undef LBMSG
 
 /* Bytecode field constants */
-enum lb_color {
-	LB_COL_RED,
-	LB_COL_GREEN,
-	LB_COL_BLUE,
-	LB_COL_ALL
-};
+enum lb_color { LB_COL_RED, LB_COL_GREEN, LB_COL_BLUE, LB_COL_ALL };
 
-enum lb_control {
-	LB_CONT_COLOR0,
-	LB_CONT_COLOR1,
-	LB_CONT_PHASE,
-	LB_CONT_MAX
-};
+enum lb_control { LB_CONT_COLOR0, LB_CONT_COLOR1, LB_CONT_PHASE, LB_CONT_MAX };
 
 #ifdef CONFIG_ALS_LIGHTBAR_DIMMING
 /*
@@ -51,7 +38,7 @@ struct lb_brightness_def {
 };
 
 extern const struct lb_brightness_def lb_brightness_levels[];
-extern const unsigned lb_brightness_levels_count;
+extern const unsigned int lb_brightness_levels_count;
 #endif
 
 /* Request a preset sequence from the lightbar task. */
@@ -67,4 +54,4 @@ extern void demo_battery_level(int inc);
 extern void demo_is_charging(int ischarge);
 extern void demo_brightness(int inc);
 extern void demo_tap(void);
-#endif  /* __CROS_EC_LIGHTBAR_H */
+#endif /* __CROS_EC_LIGHTBAR_H */
diff --git a/include/lightbar_msg_list.h b/include/lightbar_msg_list.h
index 15c7d14bf6..be87913c83 100644
--- a/include/lightbar_msg_list.h
+++ b/include/lightbar_msg_list.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -6,17 +6,17 @@
  * we can automatically derive the correct constants, functions, and message
  * types.
  */
-#define LIGHTBAR_MSG_LIST                       \
-	LBMSG(ERROR),		/* 0 */		\
-	LBMSG(S5),		/* 1 */		\
-	LBMSG(S3),		/* 2 */		\
-	LBMSG(S0),		/* 3 */		\
-	LBMSG(S5S3),		/* 4 */		\
-	LBMSG(S3S0),		/* 5 */		\
-	LBMSG(S0S3),		/* 6 */		\
-	LBMSG(S3S5),		/* 7 */		\
-	LBMSG(STOP),		/* 8 */		\
-	LBMSG(RUN),		/* 9 */		\
-	LBMSG(KONAMI),		/* A */         \
-	LBMSG(TAP),		/* B */		\
-	LBMSG(PROGRAM),		/* C */
+#define LIGHTBAR_MSG_LIST              \
+	LBMSG(ERROR), /* 0 */          \
+		LBMSG(S5), /* 1 */     \
+		LBMSG(S3), /* 2 */     \
+		LBMSG(S0), /* 3 */     \
+		LBMSG(S5S3), /* 4 */   \
+		LBMSG(S3S0), /* 5 */   \
+		LBMSG(S0S3), /* 6 */   \
+		LBMSG(S3S5), /* 7 */   \
+		LBMSG(STOP), /* 8 */   \
+		LBMSG(RUN), /* 9 */    \
+		LBMSG(KONAMI), /* A */ \
+		LBMSG(TAP), /* B */    \
+		LBMSG(PROGRAM), /* C */
diff --git a/include/lightbar_opcode_list.h b/include/lightbar_opcode_list.h
index 5d75feb459..c8feae682f 100644
--- a/include/lightbar_opcode_list.h
+++ b/include/lightbar_opcode_list.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -6,21 +6,21 @@
  */
 
 /* 	   NAME			OPERAND BYTES	MNEMONIC*/
-#define LIGHTBAR_OPCODE_TABLE					\
-	OP(ON,			0,		"on"		)\
-	OP(OFF,			0,		"off"		)\
-	OP(JUMP,		1,		"jump"		)\
-	OP(JUMP_BATTERY,	2,		"jbat"		)\
-	OP(JUMP_IF_CHARGING,	1,		"jcharge"	)\
-	OP(SET_WAIT_DELAY,	4,		"delay.w"	)\
-	OP(SET_RAMP_DELAY,	4,		"delay.r"	)\
-	OP(WAIT,		0,		"wait"		)\
-	OP(SET_BRIGHTNESS,	1,		"bright"	)\
-	OP(SET_COLOR_SINGLE,	2,		"set.1"		)\
-	OP(SET_COLOR_RGB,	4,		"set.rgb"	)\
-	OP(GET_COLORS,		0,		"get"		)\
-	OP(SWAP_COLORS,		0,		"swap"		)\
-	OP(RAMP_ONCE,		0,		"ramp.1"	)\
-	OP(CYCLE_ONCE,		0,		"cycle.1"	)\
-	OP(CYCLE,		0,		"cycle"		)\
-	OP(HALT,		0,		"halt"		)
+#define LIGHTBAR_OPCODE_TABLE              \
+	OP(ON, 0, "on")                    \
+	OP(OFF, 0, "off")                  \
+	OP(JUMP, 1, "jump")                \
+	OP(JUMP_BATTERY, 2, "jbat")        \
+	OP(JUMP_IF_CHARGING, 1, "jcharge") \
+	OP(SET_WAIT_DELAY, 4, "delay.w")   \
+	OP(SET_RAMP_DELAY, 4, "delay.r")   \
+	OP(WAIT, 0, "wait")                \
+	OP(SET_BRIGHTNESS, 1, "bright")    \
+	OP(SET_COLOR_SINGLE, 2, "set.1")   \
+	OP(SET_COLOR_RGB, 4, "set.rgb")    \
+	OP(GET_COLORS, 0, "get")           \
+	OP(SWAP_COLORS, 0, "swap")         \
+	OP(RAMP_ONCE, 0, "ramp.1")         \
+	OP(CYCLE_ONCE, 0, "cycle.1")       \
+	OP(CYCLE, 0, "cycle")              \
+	OP(HALT, 0, "halt")
diff --git a/include/link_defs.h b/include/link_defs.h
index 5b04b857bb..e54d23d974 100644
--- a/include/link_defs.h
+++ b/include/link_defs.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -15,6 +15,10 @@
 #include "task.h"
 #include "test_util.h"
 
+#ifdef CONFIG_ZEPHYR
+#include <linker.h>
+#endif
+
 /* Console commands */
 extern const struct console_command __cmds[];
 extern const struct console_command __cmds_end[];
@@ -50,6 +54,8 @@ extern const struct hook_data __hooks_chipset_shutdown[];
 extern const struct hook_data __hooks_chipset_shutdown_end[];
 extern const struct hook_data __hooks_chipset_shutdown_complete[];
 extern const struct hook_data __hooks_chipset_shutdown_complete_end[];
+extern const struct hook_data __hooks_chipset_hard_off[];
+extern const struct hook_data __hooks_chipset_hard_off_end[];
 extern const struct hook_data __hooks_chipset_reset[];
 extern const struct hook_data __hooks_chipset_reset_end[];
 extern const struct hook_data __hooks_ac_change[];
@@ -58,6 +64,10 @@ extern const struct hook_data __hooks_lid_change[];
 extern const struct hook_data __hooks_lid_change_end[];
 extern const struct hook_data __hooks_tablet_mode_change[];
 extern const struct hook_data __hooks_tablet_mode_change_end[];
+#ifdef CONFIG_BODY_DETECTION
+extern const struct hook_data __hooks_body_detect_change[];
+extern const struct hook_data __hooks_body_detect_change_end[];
+#endif
 extern const struct hook_data __hooks_base_attached_change[];
 extern const struct hook_data __hooks_base_attached_change_end[];
 extern const struct hook_data __hooks_pwrbtn_change[];
@@ -76,6 +86,8 @@ extern const struct hook_data __hooks_usb_pd_disconnect[];
 extern const struct hook_data __hooks_usb_pd_disconnect_end[];
 extern const struct hook_data __hooks_usb_pd_connect[];
 extern const struct hook_data __hooks_usb_pd_connect_end[];
+extern const struct hook_data __hooks_power_supply_change[];
+extern const struct hook_data __hooks_power_supply_change_end[];
 
 /* Deferrable functions and firing times*/
 extern const struct deferred_data __deferred_funcs[];
@@ -102,7 +114,7 @@ extern const void *__irqhandler[];
 extern const struct irq_def __irq_data[], __irq_data_end[];
 
 /* Shared memory buffer.  Use via shared_mem.h interface. */
-extern uint8_t __shared_mem_buf[];
+extern char __shared_mem_buf[];
 
 /* Image sections used by the TPM2 library */
 extern uint8_t *__bss_libtpm2_start;
@@ -125,7 +137,7 @@ extern void *__dram_bss_end;
 /* Helper for special chip-specific memory sections */
 #if defined(CONFIG_CHIP_MEMORY_REGIONS) || defined(CONFIG_DRAM_BASE)
 #define __SECTION(name) __attribute__((section("." STRINGIFY(name) ".50_auto")))
-#define __SECTION_KEEP(name)                                                   \
+#define __SECTION_KEEP(name) \
 	__keep __attribute__((section("." STRINGIFY(name) ".keep.50_auto")))
 #else
 #define __SECTION(name)
@@ -140,8 +152,11 @@ extern void *__dram_bss_end;
 #endif /* __CROS_EC_LINK_DEFS_H */
 
 #ifdef CONFIG_PRESERVE_LOGS
-#define __preserved_logs(name)                                                 \
+#define __preserved_logs(name) \
 	__attribute__((section(".preserved_logs." STRINGIFY(name))))
+/* preserved_logs section. */
+extern const char __preserved_logs_start[];
+extern const char __preserved_logs_size[];
 #else
 #define __preserved_logs(name)
 #endif
diff --git a/include/lpc.h b/include/lpc.h
index 2a69cbced8..a6cd8602d6 100644
--- a/include/lpc.h
+++ b/include/lpc.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -67,7 +67,13 @@ int lpc_comx_get_char(void);
  * Put a character to the COMx LPC interface.
  */
 void lpc_comx_put_char(int c);
-
+#if defined(CONFIG_THIRD_PARTY_CUSTOMIZED_DESIGN)
+/**
+ * Read kbc data from DBBIN this action will clear ibf
+ * also can use ibf to control host send data speed.
+ */
+void lpc_kbc_ibf_clear(void);
+#endif
 /*
  * Low-level LPC interface for host events.
  *
@@ -89,6 +95,13 @@ enum lpc_host_event_type {
  */
 host_event_t lpc_get_host_events(void);
 
+#ifdef TEST_BUILD
+/**
+ * Set host events.
+ */
+void lpc_set_host_event_state(host_event_t events);
+#endif
+
 /**
  * Get host events that are set based on the type provided.
  *
@@ -162,4 +175,4 @@ void lpc_init_mask(void);
  */
 void lpc_s3_resume_clear_masks(void);
 
-#endif  /* __CROS_EC_LPC_H */
+#endif /* __CROS_EC_LPC_H */
diff --git a/include/mag_cal.h b/include/mag_cal.h
index 61b24c7da9..82453c5235 100644
--- a/include/mag_cal.h
+++ b/include/mag_cal.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,14 +8,14 @@
 #ifndef __CROS_EC_MAG_CAL_H
 #define __CROS_EC_MAG_CAL_H
 
-#include "math_util.h"
+#include "kasa.h"
 #include "mat44.h"
+#include "math_util.h"
 #include "vec4.h"
-#include "kasa.h"
 
 #define MAG_CAL_MAX_SAMPLES 0xffff
-#define MAG_CAL_MIN_BATCH_WINDOW_US    (2 * SECOND)
-#define MAG_CAL_MIN_BATCH_SIZE      50      /* samples */
+#define MAG_CAL_MIN_BATCH_WINDOW_US (2 * SECOND)
+#define MAG_CAL_MIN_BATCH_SIZE 50 /* samples */
 
 struct mag_cal_t {
 	struct kasa_fit kasa_fit;
@@ -38,4 +38,4 @@ void init_mag_cal(struct mag_cal_t *moc);
  * @return    1 if a new calibration value is available, 0 otherwise.
  */
 int mag_cal_update(struct mag_cal_t *moc, const intv3_t v);
-#endif  /* __CROS_EC_MAG_CAL_H */
+#endif /* __CROS_EC_MAG_CAL_H */
diff --git a/include/mat33.h b/include/mat33.h
index fdd7e954ac..43826af1b1 100644
--- a/include/mat33.h
+++ b/include/mat33.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,6 +26,6 @@ void mat33_fp_get_eigenbasis(mat33_fp_t S, fpv3_t eigenvals,
 
 size_t mat33_fp_maxind(mat33_fp_t A, size_t k);
 
-void mat33_fp_rotate(mat33_fp_t A, fp_t c, fp_t s,
-		     size_t k, size_t l, size_t i, size_t j);
-#endif  /* __CROS_EC_MAT_33_H */
+void mat33_fp_rotate(mat33_fp_t A, fp_t c, fp_t s, size_t k, size_t l, size_t i,
+		     size_t j);
+#endif /* __CROS_EC_MAT_33_H */
diff --git a/include/mat44.h b/include/mat44.h
index 2faa093c8e..909c6e0ee7 100644
--- a/include/mat44.h
+++ b/include/mat44.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,4 +22,4 @@ void mat44_fp_swap_rows(mat44_fp_t A, const size_t i, const size_t j);
 
 void mat44_fp_solve(mat44_fp_t A, fpv4_t x, const fpv4_t b,
 		    const sizev4_t pivot);
-#endif  /* __CROS_EC_MAT_44_H */
+#endif /* __CROS_EC_MAT_44_H */
diff --git a/include/math_util.h b/include/math_util.h
index 266bde6743..6b4b8cb3e5 100644
--- a/include/math_util.h
+++ b/include/math_util.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,6 +8,9 @@
 #ifndef __CROS_EC_MATH_UTIL_H
 #define __CROS_EC_MATH_UTIL_H
 
+#include "config.h"
+#include "limits.h"
+
 #include <stdint.h>
 
 #ifdef CONFIG_FPU
@@ -39,9 +42,9 @@ typedef int64_t fp_inter_t;
 #define INT_TO_FP(x) ((fp_t)(x) << FP_BITS)
 #define FP_TO_INT(x) ((int32_t)((x) >> FP_BITS))
 /* Float to fixed-point, only for compile-time constants and unit tests */
-#define FLOAT_TO_FP(x) ((fp_t)((x) * (float)(1<<FP_BITS)))
+#define FLOAT_TO_FP(x) ((fp_t)((x) * (float)(1 << FP_BITS)))
 /* Fixed-point to float, for unit tests */
-#define FP_TO_FLOAT(x) ((float)(x) / (float)(1<<FP_BITS))
+#define FP_TO_FLOAT(x) ((float)(x) / (float)(1 << FP_BITS))
 
 #define FLT_MAX INT32_MAX
 #define FLT_MIN INT32_MIN
@@ -135,6 +138,11 @@ static inline int ceil_for(int n, int m)
 	return (((n - 1) / m) + 1);
 }
 
+/**
+ * Integer square root
+ */
+int int_sqrtf(fp_inter_t x);
+
 /**
  * Square root
  */
@@ -152,9 +160,7 @@ typedef fp_t mat33_fp_t[3][3];
 typedef int intv3_t[3];
 
 /* For vectors, define which coordinates are in which location. */
-enum {
-	X, Y, Z, W
-};
+enum { X, Y, Z, W };
 /*
  * Return absolute value of x.  Note that as a macro expansion, this may have
  * side effects if x includes function calls, which is why inline functions
@@ -188,7 +194,6 @@ void cross_product(const intv3_t v1, const intv3_t v2, intv3_t v);
  */
 void vector_scale(intv3_t v, fp_t s);
 
-
 /**
  * Find the cosine of the angle between two vectors.
  *
@@ -225,4 +230,13 @@ void rotate_inv(const intv3_t v, const mat33_fp_t R, intv3_t res);
  */
 int round_divide(int64_t dividend, int divisor);
 
+/**
+ * Create a 64 bit bitmask of 2^offset
+ */
+#if ULONG_MAX == 0xFFFFFFFFUL
+uint64_t bitmask_uint64(int offset);
+#else
+#define bitmask_uint64(o) ((uint64_t)1 << (o))
+#endif
+
 #endif /* __CROS_EC_MATH_UTIL_H */
diff --git a/include/memory_commands.h b/include/memory_commands.h
index 91020d8920..666a6ef508 100644
--- a/include/memory_commands.h
+++ b/include/memory_commands.h
@@ -1,4 +1,4 @@
-/* Copyright 2011 The Chromium OS Authors. All rights reserved.
+/* Copyright 2011 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,4 +13,4 @@
 /* Initializes the module. */
 int memory_commands_init(void);
 
-#endif  /* __CROS_EC_MEMORY_COMMANDS_H */
+#endif /* __CROS_EC_MEMORY_COMMANDS_H */
diff --git a/include/mkbp_event.h b/include/mkbp_event.h
index 5bfe7ac505..d31bd82cb2 100644
--- a/include/mkbp_event.h
+++ b/include/mkbp_event.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,6 +8,8 @@
 #ifndef __CROS_EC_MKBP_EVENT_H
 #define __CROS_EC_MKBP_EVENT_H
 
+#include "common.h"
+
 /*
  * Last time the host received an interrupt.
  *
@@ -46,10 +48,25 @@ struct mkbp_event_source {
 	int (*get_data)(uint8_t *data);
 };
 
-#define DECLARE_EVENT_SOURCE(type, func)                       \
-	const struct mkbp_event_source __keep		       \
-	__no_sanitize_address _evt_src_##type		       \
-	__attribute__((section(".rodata.evtsrcs")))            \
-		 = {type, func}
+#ifdef CONFIG_PLATFORM_EC_MKBP_EVENT
+#include "zephyr_mkbp_event.h"
+#else
+#define DECLARE_EVENT_SOURCE(type, func)                            \
+	const struct mkbp_event_source __keep __no_sanitize_address \
+		_evt_src_##type                                     \
+		__attribute__((section(".rodata.evtsrcs"))) = { type, func }
+#endif
+
+#ifdef TEST_BUILD
+/* Allow directly raising events in unit tests */
+void activate_mkbp_with_events(uint32_t events_to_add);
+
+/**
+ * @brief Force the event bits to zero, causing the event handling code to
+ *        believe there are no pending events to service. This has no effect on
+ *        any event sources' internal queues or logic.
+ */
+__test_only void mkbp_event_clear_all(void);
+#endif /* TEST_BUILD */
 
-#endif  /* __CROS_EC_MKBP_EVENT_H */
+#endif /* __CROS_EC_MKBP_EVENT_H */
diff --git a/include/mkbp_fifo.h b/include/mkbp_fifo.h
new file mode 100644
index 0000000000..cd27b1c8d5
--- /dev/null
+++ b/include/mkbp_fifo.h
@@ -0,0 +1,52 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* FIFO buffer of MKBP events for Chrome EC */
+
+#ifndef __CROS_EC_MKBP_FIFO_H
+#define __CROS_EC_MKBP_FIFO_H
+
+#include "common.h"
+#include "ec_commands.h"
+
+#define FIFO_DEPTH 16
+
+/**
+ * Update the "soft" FIFO depth (size). The new depth should be less or
+ * equal FIFO_DEPTH
+ *
+ * @param new_max_depth		New FIFO depth.
+ */
+void mkbp_fifo_depth_update(uint8_t new_max_depth);
+
+/**
+ * Clear all keyboard events from the MKBP common FIFO
+ */
+void mkbp_fifo_clear_keyboard(void);
+
+/**
+ * Clear the entire MKBP common FIFO.
+ */
+void mkbp_clear_fifo(void);
+
+/**
+ * Add an element to the common MKBP FIFO.
+ *
+ * @param event_type	The MKBP event type.
+ * @param buffp		Pointer to the event data to enqueue.
+ * @return EC_SUCCESS if entry added, EC_ERROR_OVERFLOW if FIFO is full.
+ */
+int mkbp_fifo_add(uint8_t event_type, const uint8_t *buffp);
+
+/**
+ * Remove an element from the common MKBP FIFO.
+ *
+ * @param out		Pointer to the event data to dequeue.
+ * @param event_type	The MKBP event type.
+ * @return size of the returned event, EC_ERROR_BUSY if type mismatch.
+ */
+int mkbp_fifo_get_next_event(uint8_t *out, enum ec_mkbp_event evt);
+
+#endif /* __CROS_EC_MKBP_FIFO_H */
diff --git a/include/mkbp_info.h b/include/mkbp_info.h
new file mode 100644
index 0000000000..61378f9c22
--- /dev/null
+++ b/include/mkbp_info.h
@@ -0,0 +1,27 @@
+/* Copyright 2022 The ChromiumOS Authors.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* MKBP info host command for Chrome EC */
+
+#ifndef __CROS_EC_MKBP_INFO_H
+#define __CROS_EC_MKBP_INFO_H
+
+/**
+ * Board specific function to set support volume buttons.
+ *
+ * Although we're able to define CONFIG_VOLUME_BUTTONS for ec volume buttons,
+ * some boards might need to configure this settings at run time by several
+ * cases such as sharing the firmware with different designs.
+ *
+ * @return 1 if volume buttons supported else 0
+ */
+__override_proto int mkbp_support_volume_buttons(void);
+
+#ifdef TEST_BUILD
+uint32_t get_supported_buttons(void);
+uint32_t get_supported_switches(void);
+#endif /* TEST_BUILD */
+
+#endif /* __CROS_EC_MKBP_INFO_H */
diff --git a/include/mkbp_input_devices.h b/include/mkbp_input_devices.h
new file mode 100644
index 0000000000..41b5697898
--- /dev/null
+++ b/include/mkbp_input_devices.h
@@ -0,0 +1,32 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Input devices using Matrix Keyboard Protocol [MKBP] events for Chrome EC */
+
+#ifndef __CROS_EC_MKBP_INPUT_DEVICES_H
+#define __CROS_EC_MKBP_INPUT_DEVICES_H
+
+#include "common.h"
+#include "ec_commands.h"
+
+/**
+ * Update the state of buttons
+ *
+ * @param button	The button that changed.
+ * @param is_pressed	Whether the button is now pressed.
+ */
+void mkbp_button_update(enum keyboard_button_type button, int is_pressed);
+
+/**
+ * Retrieve state of buttons [Power, Volume up/down, etc]
+ */
+uint32_t mkbp_get_button_state(void);
+
+/**
+ * Retrieve state of switches [Lid open/closed, tablet mode switch, etc]
+ */
+uint32_t mkbp_get_switch_state(void);
+
+#endif /* __CROS_EC_MKBP_INPUT_DEVICES_H */
diff --git a/include/mock/charge_manager_mock.h b/include/mock/charge_manager_mock.h
new file mode 100644
index 0000000000..afae5a19a2
--- /dev/null
+++ b/include/mock/charge_manager_mock.h
@@ -0,0 +1,27 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ * @brief Controls for the mock charge_manager
+ */
+
+#ifndef __MOCK_CHARGE_MANAGER_MOCK_H
+#define __MOCK_CHARGE_MANAGER_MOCK_H
+
+struct mock_ctrl_charge_manager {
+	int vbus_voltage_mv;
+};
+
+#define MOCK_CTRL_DEFAULT_CHARGE_MANAGER    \
+	((struct mock_ctrl_charge_manager){ \
+		.vbus_voltage_mv = 0,       \
+	})
+
+extern struct mock_ctrl_charge_manager mock_ctrl_charge_manager;
+
+void mock_charge_manager_set_vbus_voltage(int voltage_mv);
+
+#endif /* __MOCK_CHARGE_MANAGER_MOCK_H */
diff --git a/include/mock/clock_mock.h b/include/mock/clock_mock.h
new file mode 100644
index 0000000000..803be32fc2
--- /dev/null
+++ b/include/mock/clock_mock.h
@@ -0,0 +1,23 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __MOCK_CLOCK_MOCK_H
+#define __MOCK_CLOCK_MOCK_H
+
+#include "clock.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void clock_enable_module(enum module_id module, int enable);
+
+int get_mock_fast_cpu_status(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MOCK_CLOCK_MOCK_H */
diff --git a/include/mock/dp_alt_mode_mock.h b/include/mock/dp_alt_mode_mock.h
index 27811140c7..152d5d8b37 100644
--- a/include/mock/dp_alt_mode_mock.h
+++ b/include/mock/dp_alt_mode_mock.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/mock/fp_sensor_mock.h b/include/mock/fp_sensor_mock.h
deleted file mode 100644
index 432802348c..0000000000
--- a/include/mock/fp_sensor_mock.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- * @brief Controls for the mock fpsensor private driver
- */
-
-#ifndef __MOCK_FP_SENSOR_MOCK_H
-#define __MOCK_FP_SENSOR_MOCK_H
-
-#include "common.h"
-#include "fpsensor.h"
-
-struct mock_ctrl_fp_sensor {
-	int fp_sensor_init_return;
-	int fp_sensor_deinit_return;
-	int fp_sensor_get_info_return;
-	enum finger_state fp_sensor_finger_status_return;
-	int fp_sensor_acquire_image_return;
-	int fp_sensor_acquire_image_with_mode_return;
-	int fp_finger_match_return;
-	int fp_enrollment_begin_return;
-	int fp_enrollment_finish_return;
-	int fp_finger_enroll_return;
-	int fp_maintenance_return;
-};
-
-#define MOCK_CTRL_DEFAULT_FP_SENSOR                                    \
-(struct mock_ctrl_fp_sensor) {                                         \
-	.fp_sensor_init_return                       = EC_SUCCESS,     \
-	.fp_sensor_deinit_return                     = EC_SUCCESS,     \
-	.fp_sensor_get_info_return                   = EC_SUCCESS,     \
-	.fp_sensor_finger_status_return              = FINGER_NONE,    \
-	.fp_sensor_acquire_image_return              = 0,              \
-	.fp_sensor_acquire_image_with_mode_return    = 0,              \
-	.fp_finger_match_return    = EC_MKBP_FP_ERR_MATCH_YES_UPDATED, \
-	.fp_enrollment_begin_return                  = 0,              \
-	.fp_enrollment_finish_return                 = 0,              \
-	.fp_finger_enroll_return   = EC_MKBP_FP_ERR_ENROLL_OK,         \
-	.fp_maintenance_return			     = EC_SUCCESS      \
-}
-
-extern struct mock_ctrl_fp_sensor mock_ctrl_fp_sensor;
-
-#endif /* __MOCK_FP_SENSOR_MOCK_H */
diff --git a/include/mock/fpsensor_crypto_mock.h b/include/mock/fpsensor_crypto_mock.h
new file mode 100644
index 0000000000..8462dc1baf
--- /dev/null
+++ b/include/mock/fpsensor_crypto_mock.h
@@ -0,0 +1,30 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file fpsensor_crypto_mock.h
+ * @brief Controls for the mock fpsensor_crypto library
+ */
+
+#ifndef __MOCK_FPSENSOR_CRYPTO_MOCK_H
+#define __MOCK_FPSENSOR_CRYPTO_MOCK_H
+
+enum mock_ctrl_fpsensor_crypto_sha256_type {
+	MOCK_CTRL_FPSENSOR_CRYPTO_SHA256_TYPE_REAL,
+	MOCK_CTRL_FPSENSOR_CRYPTO_SHA256_TYPE_ZEROS,
+	MOCK_CTRL_FPSENSOR_CRYPTO_SHA256_TYPE_FF,
+};
+
+struct mock_ctrl_fpsensor_crypto {
+	enum mock_ctrl_fpsensor_crypto_sha256_type output_type;
+};
+
+#define MOCK_CTRL_DEFAULT_FPSENSOR_CRYPTO    \
+	((struct mock_ctrl_fpsensor_crypto){ \
+		.output_type = MOCK_CTRL_FPSENSOR_CRYPTO_SHA256_TYPE_REAL })
+
+extern struct mock_ctrl_fpsensor_crypto mock_ctrl_fpsensor_crypto;
+
+#endif /* __MOCK_FPSENSOR_CRYPTO_MOCK_H */
diff --git a/include/mock/fpsensor_detect_mock.h b/include/mock/fpsensor_detect_mock.h
index 5ffa2b4431..e68704115c 100644
--- a/include/mock/fpsensor_detect_mock.h
+++ b/include/mock/fpsensor_detect_mock.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,14 +9,18 @@
 #include "fpsensor_detect.h"
 
 struct mock_ctrl_fpsensor_detect {
-	enum fp_sensor_type get_fp_sensor_type_return;
+	enum fp_sensor_type fpsensor_detect_get_type_return;
 	enum fp_transport_type get_fp_transport_type_return;
+	enum fp_sensor_spi_select get_fp_sensor_spi_select_return;
 };
 
-#define MOCK_CTRL_DEFAULT_FPSENSOR_DETECT {				\
-	.get_fp_sensor_type_return = FP_SENSOR_TYPE_UNKNOWN,		\
-	.get_fp_transport_type_return = FP_TRANSPORT_TYPE_UNKNOWN,	\
-}
+#define MOCK_CTRL_DEFAULT_FPSENSOR_DETECT                                  \
+	{                                                                  \
+		.fpsensor_detect_get_type_return = FP_SENSOR_TYPE_UNKNOWN, \
+		.get_fp_transport_type_return = FP_TRANSPORT_TYPE_UNKNOWN, \
+		.get_fp_sensor_spi_select_return =                         \
+			FP_SENSOR_SPI_SELECT_UNKNOWN                       \
+	}
 
 extern struct mock_ctrl_fpsensor_detect mock_ctrl_fpsensor_detect;
 
diff --git a/include/mock/fpsensor_mock.h b/include/mock/fpsensor_mock.h
new file mode 100644
index 0000000000..dae485b859
--- /dev/null
+++ b/include/mock/fpsensor_mock.h
@@ -0,0 +1,49 @@
+/* Copyright 2019 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ * @brief Controls for the mock fpsensor private driver
+ */
+
+#ifndef __MOCK_FPSENSOR_MOCK_H
+#define __MOCK_FPSENSOR_MOCK_H
+
+#include "common.h"
+#include "fpsensor.h"
+
+struct mock_ctrl_fp_sensor {
+	int fp_sensor_init_return;
+	int fp_sensor_deinit_return;
+	int fp_sensor_get_info_return;
+	enum finger_state fp_sensor_finger_status_return;
+	int fp_sensor_acquire_image_return;
+	int fp_sensor_acquire_image_with_mode_return;
+	int fp_finger_match_return;
+	int fp_enrollment_begin_return;
+	int fp_enrollment_finish_return;
+	int fp_finger_enroll_return;
+	int fp_maintenance_return;
+};
+
+#define MOCK_CTRL_DEFAULT_FP_SENSOR                                         \
+	(struct mock_ctrl_fp_sensor)                                        \
+	{                                                                   \
+		.fp_sensor_init_return = EC_SUCCESS,                        \
+		.fp_sensor_deinit_return = EC_SUCCESS,                      \
+		.fp_sensor_get_info_return = EC_SUCCESS,                    \
+		.fp_sensor_finger_status_return = FINGER_NONE,              \
+		.fp_sensor_acquire_image_return = 0,                        \
+		.fp_sensor_acquire_image_with_mode_return = 0,              \
+		.fp_finger_match_return = EC_MKBP_FP_ERR_MATCH_YES_UPDATED, \
+		.fp_enrollment_begin_return = 0,                            \
+		.fp_enrollment_finish_return = 0,                           \
+		.fp_finger_enroll_return = EC_MKBP_FP_ERR_ENROLL_OK,        \
+		.fp_maintenance_return = EC_SUCCESS                         \
+	}
+
+extern struct mock_ctrl_fp_sensor mock_ctrl_fp_sensor;
+
+#endif /* __MOCK_FP_SENSOR_MOCK_H */
diff --git a/include/mock/fpsensor_state_mock.h b/include/mock/fpsensor_state_mock.h
index eafe01851c..c377983a58 100644
--- a/include/mock/fpsensor_state_mock.h
+++ b/include/mock/fpsensor_state_mock.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,13 +6,21 @@
 #ifndef __MOCK_FPSENSOR_STATE_MOCK_H
 #define __MOCK_FPSENSOR_STATE_MOCK_H
 
+#include "ec_commands.h"
+#include "fpsensor_driver.h"
+
 #include <stdbool.h>
 #include <stdint.h>
-#include "ec_commands.h"
 
 extern const uint8_t default_fake_tpm_seed[FP_CONTEXT_TPM_BYTES];
+extern const uint8_t
+	default_fake_fp_positive_match_salt[FP_MAX_FINGER_COUNT]
+					   [FP_POSITIVE_MATCH_SALT_BYTES];
+extern const uint8_t
+	trivial_fp_positive_match_salt[FP_MAX_FINGER_COUNT]
+				      [FP_POSITIVE_MATCH_SALT_BYTES];
 
 int fpsensor_state_mock_set_tpm_seed(
 	const uint8_t tpm_seed[FP_CONTEXT_TPM_BYTES]);
 
-#endif  /* __MOCK_FPSENSOR_STATE_MOCK_H */
+#endif /* __MOCK_FPSENSOR_STATE_MOCK_H */
diff --git a/include/mock/mkbp_events_mock.h b/include/mock/mkbp_events_mock.h
index 3d686e3618..22600e4f96 100644
--- a/include/mock/mkbp_events_mock.h
+++ b/include/mock/mkbp_events_mock.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,10 +15,11 @@ struct mock_ctrl_mkbp_events {
 	int mkbp_send_event_return;
 };
 
-#define MOCK_CTRL_DEFAULT_MKBP_EVENTS          \
-(struct mock_ctrl_mkbp_events) {               \
-	.mkbp_send_event_return = 1,           \
-}
+#define MOCK_CTRL_DEFAULT_MKBP_EVENTS        \
+	(struct mock_ctrl_mkbp_events)       \
+	{                                    \
+		.mkbp_send_event_return = 1, \
+	}
 
 extern struct mock_ctrl_mkbp_events mock_ctrl_mkbp_events;
 
diff --git a/include/mock/rollback_latest_mock.h b/include/mock/rollback_latest_mock.h
new file mode 100644
index 0000000000..82c4c5aadc
--- /dev/null
+++ b/include/mock/rollback_latest_mock.h
@@ -0,0 +1,36 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ * @brief Controls for the mock rollback block library
+ */
+
+#ifndef __MOCK_ROLLBACK_LATEST_MOCK_H
+#define __MOCK_ROLLBACK_LATEST_MOCK_H
+
+#include <stdbool.h>
+
+enum mock_ctrl_latest_rollback_type {
+	GET_LATEST_ROLLBACK_FAIL,
+	GET_LATEST_ROLLBACK_ZEROS,
+	GET_LATEST_ROLLBACK_REAL,
+};
+
+struct mock_ctrl_latest_rollback {
+	enum mock_ctrl_latest_rollback_type output_type;
+};
+
+#define MOCK_CTRL_DEFAULT_LATEST_ROLLBACK    \
+	((struct mock_ctrl_latest_rollback){ \
+		.output_type = GET_LATEST_ROLLBACK_REAL })
+
+extern struct mock_ctrl_latest_rollback mock_ctrl_latest_rollback;
+
+extern const struct rollback_data fake_latest_rollback_zeros;
+
+extern const struct rollback_data fake_latest_rollback_real;
+
+#endif /* __MOCK_ROLLBACK_LATEST_MOCK_H */
diff --git a/include/mock/rollback_mock.h b/include/mock/rollback_mock.h
index 576f87e6b9..890e2539a7 100644
--- a/include/mock/rollback_mock.h
+++ b/include/mock/rollback_mock.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,11 +17,12 @@ struct mock_ctrl_rollback {
 	bool get_secret_fail;
 };
 
-#define MOCK_CTRL_DEFAULT_ROLLBACK             \
-(struct mock_ctrl_rollback) {                  \
-	.get_secret_fail = false,              \
-}
+#define MOCK_CTRL_DEFAULT_ROLLBACK        \
+	(struct mock_ctrl_rollback)       \
+	{                                 \
+		.get_secret_fail = false, \
+	}
 
 extern struct mock_ctrl_rollback mock_ctrl_rollback;
 
-#endif  /* __MOCK_ROLLBACK_MOCK_H */
+#endif /* __MOCK_ROLLBACK_MOCK_H */
diff --git a/include/mock/tcpc_mock.h b/include/mock/tcpc_mock.h
index 9098fe1ba3..fef45b492b 100644
--- a/include/mock/tcpc_mock.h
+++ b/include/mock/tcpc_mock.h
@@ -1,11 +1,11 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
- /* Mock for the TCPC interface */
+/* Mock for the TCPC interface */
 
-#include "usb_pd_tcpm.h"
 #include "usb_pd.h"
+#include "usb_pd_tcpm.h"
 
 /* Controller for TCPC state */
 struct mock_tcpc_ctrl {
@@ -15,6 +15,7 @@ struct mock_tcpc_ctrl {
 	int num_calls_to_set_header;
 	bool should_print_call;
 	uint64_t first_call_to_enable_auto_toggle;
+	bool lpm_wake_requested;
 
 	/* Set to function pointer if callback is needed for test code */
 	struct tcpm_drv callbacks;
@@ -27,7 +28,6 @@ struct mock_tcpc_ctrl {
 		enum tcpc_rp_value rp;
 		enum tcpc_cc_polarity polarity;
 	} last;
-
 };
 
 /* Reset this TCPC mock */
diff --git a/include/mock/tcpci_i2c_mock.h b/include/mock/tcpci_i2c_mock.h
index 4864c7fc96..ae86a8c50b 100644
--- a/include/mock/tcpci_i2c_mock.h
+++ b/include/mock/tcpci_i2c_mock.h
@@ -1,30 +1,50 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "common.h"
 #include "usb_pd.h"
+#include "usb_pd_tcpm.h"
 
 #define MOCK_TCPCI_I2C_ADDR_FLAGS 0x99
 
 void mock_tcpci_reset(void);
 
 void mock_tcpci_set_reg(int reg, uint16_t value);
+void mock_tcpci_set_reg_bits(int reg_offset, uint16_t mask);
+void mock_tcpci_clr_reg_bits(int reg_offset, uint16_t mask);
 
 uint16_t mock_tcpci_get_reg(int reg_offset);
 
-int verify_tcpci_transmit(enum tcpm_transmit_type tx_type,
+int verify_tcpci_transmit(enum tcpci_msg_type tx_type,
 			  enum pd_ctrl_msg_type ctrl_msg,
 			  enum pd_data_msg_type data_msg);
 
-int verify_tcpci_tx_retry_count(enum tcpm_transmit_type tx_type,
+int verify_tcpci_tx_retry_count(enum tcpci_msg_type tx_type,
+				enum pd_ctrl_msg_type ctrl_msg,
+				enum pd_data_msg_type data_msg,
 				int retry_count);
 
-int verify_tcpci_tx_timeout(enum tcpm_transmit_type tx_type,
+int verify_tcpci_tx_timeout(enum tcpci_msg_type tx_type,
 			    enum pd_ctrl_msg_type ctrl_msg,
-			    enum pd_data_msg_type data_msg,
-			    int timeout);
+			    enum pd_data_msg_type data_msg, int timeout);
 
-void mock_tcpci_receive(enum pd_msg_type sop, uint16_t header,
+int verify_tcpci_tx_with_data(enum tcpci_msg_type tx_type,
+			      enum pd_data_msg_type data_msg, uint8_t *data,
+			      int data_bytes, int *msg_len, int timeout);
+
+struct possible_tx {
+	enum tcpci_msg_type tx_type;
+	enum pd_ctrl_msg_type ctrl_msg;
+	enum pd_data_msg_type data_msg;
+};
+
+int verify_tcpci_possible_tx(struct possible_tx possible[], int possible_cnt,
+			     int *found_index, uint8_t *data, int data_bytes,
+			     int *msg_len, int timeout);
+
+void mock_tcpci_receive(enum tcpci_msg_type sop, uint16_t header,
 			uint32_t *payload);
+
+void tcpci_register_dump(void);
diff --git a/include/mock/tcpm_mock.h b/include/mock/tcpm_mock.h
index 05af6aec48..2733863b62 100644
--- a/include/mock/tcpm_mock.h
+++ b/include/mock/tcpm_mock.h
@@ -1,11 +1,11 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
- /* Mock for the TCPM interface */
+/* Mock for the TCPM interface */
 
 #include "common.h"
-#include "tcpm.h"
+#include "tcpm/tcpm.h"
 
 /* Copied from usb_prl_sm.c, line 99. */
 #define MOCK_CHK_BUF_SIZE 7
diff --git a/include/mock/timer_mock.h b/include/mock/timer_mock.h
index 04dc01e9ab..cc294521cc 100644
--- a/include/mock/timer_mock.h
+++ b/include/mock/timer_mock.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,4 +12,4 @@ void set_time(timestamp_t now_);
 
 timestamp_t get_time(void);
 
-#endif  /* __MOCK_TIMER_MOCK_H */
+#endif /* __MOCK_TIMER_MOCK_H */
diff --git a/include/mock/usb_mux_mock.h b/include/mock/usb_mux_mock.h
index 128286796b..c2d154ad72 100644
--- a/include/mock/usb_mux_mock.h
+++ b/include/mock/usb_mux_mock.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/mock/usb_pd_dpm_mock.h b/include/mock/usb_pd_dpm_mock.h
index c61594fd2b..266cad4aef 100644
--- a/include/mock/usb_pd_dpm_mock.h
+++ b/include/mock/usb_pd_dpm_mock.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,7 +8,7 @@
 #define __MOCK_USB_PD_DPM_MOCK_H
 
 #include "common.h"
-#include "usb_pd_dpm.h"
+#include "usb_pd_dpm_sm.h"
 
 /* Defaults should all be 0 values. */
 struct mock_dpm_port_t {
diff --git a/include/mock/usb_pd_mock.h b/include/mock/usb_pd_mock.h
deleted file mode 100644
index 353437d3e3..0000000000
--- a/include/mock/usb_pd_mock.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Mock USB PD */
-
-#ifndef __MOCK_USB_PD_MOCK_H
-#define __MOCK_USB_PD_MOCK_H
-
-#include "common.h"
-#include "usb_pd.h"
-
-/* Defaults should all be 0 values. */
-struct mock_pd_port_t {
-	enum pd_data_role data_role;
-	enum pd_power_role power_role;
-};
-
-extern struct mock_pd_port_t mock_pd_port[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-void mock_pd_reset(void);
-
-#endif /* __MOCK_USB_PD_MOCK_H */
diff --git a/include/mock/usb_pe_sm_mock.h b/include/mock/usb_pe_sm_mock.h
index 8b1e790d9c..778e7943c4 100644
--- a/include/mock/usb_pe_sm_mock.h
+++ b/include/mock/usb_pe_sm_mock.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,10 +8,11 @@
 #define __MOCK_USB_PE_SM_MOCK_H
 
 #include "common.h"
+#include "usb_pd_tcpm.h"
 #include "usb_pe_sm.h"
 
 struct mock_pe_port_t {
-	enum tcpm_transmit_type sop;
+	enum tcpci_msg_type sop;
 
 	int mock_pe_message_sent;
 	int mock_pe_error;
diff --git a/include/mock/usb_prl_mock.h b/include/mock/usb_prl_mock.h
index 5479fbd164..7758700d3a 100644
--- a/include/mock/usb_prl_mock.h
+++ b/include/mock/usb_prl_mock.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,21 +9,27 @@
 
 #include "common.h"
 #include "usb_emsg.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usb_pe_sm.h"
 
 void mock_prl_reset(void);
 
-enum pd_ctrl_msg_type fake_prl_get_last_sent_ctrl_msg(int port);
+int mock_prl_wait_for_tx_msg(int port, enum tcpci_msg_type tx_type,
+			     enum pd_ctrl_msg_type ctrl_msg,
+			     enum pd_data_msg_type data_msg, int timeout);
 
-void fake_prl_clear_last_sent_ctrl_msg(int port);
+enum pd_ctrl_msg_type mock_prl_get_last_sent_ctrl_msg(int port);
 
-enum pd_data_msg_type fake_prl_get_last_sent_data_msg_type(int port);
+enum pd_data_msg_type mock_prl_get_last_sent_data_msg(int port);
 
-void fake_prl_clear_last_sent_data_msg(int port);
+void mock_prl_clear_last_sent_msg(int port);
 
-void fake_prl_message_sent(int port);
+void mock_prl_message_sent(int port);
 
-void fake_prl_message_received(int port);
+void mock_prl_message_received(int port);
 
-void fake_prl_report_error(int port, enum pe_error e);
+void mock_prl_report_error(int port, enum pe_error e,
+			   enum tcpci_msg_type tx_type);
 
 #endif /* __MOCK_DP_ALT_MODE_MOCK_H */
diff --git a/include/mock/usb_tc_sm_mock.h b/include/mock/usb_tc_sm_mock.h
index beefa40c74..2dc09ade8b 100644
--- a/include/mock/usb_tc_sm_mock.h
+++ b/include/mock/usb_tc_sm_mock.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,6 +8,8 @@
 #define __MOCK_USB_TC_SM_MOCK_H
 
 #include "common.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
 #include "usb_tc_sm.h"
 
 struct mock_tc_port_t {
@@ -15,10 +17,13 @@ struct mock_tc_port_t {
 	int pd_enable;
 	int msg_tx_id;
 	int msg_rx_id;
-	enum tcpm_transmit_type sop;
+	enum tcpci_msg_type sop;
 	enum tcpc_rp_value lcl_rp;
 	int attached_snk;
 	int attached_src;
+	bool vconn_src;
+	enum pd_data_role data_role;
+	enum pd_power_role power_role;
 };
 
 extern struct mock_tc_port_t mock_tc_port[CONFIG_USB_PD_PORT_MAX_COUNT];
diff --git a/include/mock_filter.h b/include/mock_filter.h
index 113c227a3b..83beead6c7 100644
--- a/include/mock_filter.h
+++ b/include/mock_filter.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,5 +18,4 @@
 CONFIG_TEST_MOCK_LIST
 #endif
 
-
 #endif /*  __CROS_EC_MOCK_FILTER_H */
diff --git a/include/module_id.h b/include/module_id.h
index 02c91451e7..bfc780e70f 100644
--- a/include/module_id.h
+++ b/include/module_id.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -41,7 +41,7 @@ enum module_id {
 	MODULE_RBOX,
 	MODULE_SPI,
 	MODULE_SPI_FLASH,
-	MODULE_SPI_MASTER,
+	MODULE_SPI_CONTROLLER,
 	MODULE_SWITCH,
 	MODULE_SYSTEM,
 	MODULE_TASK,
diff --git a/include/motion_lid.h b/include/motion_lid.h
index ed7fd4b741..917a545ab6 100644
--- a/include/motion_lid.h
+++ b/include/motion_lid.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -34,6 +34,4 @@ enum ec_status host_cmd_motion_lid(struct host_cmd_handler_args *args);
 
 void motion_lid_calc(void);
 
-#endif  /* __CROS_EC_MOTION_LID_H */
-
-
+#endif /* __CROS_EC_MOTION_LID_H */
diff --git a/include/motion_orientation.h b/include/motion_orientation.h
new file mode 100644
index 0000000000..4b1daaa58c
--- /dev/null
+++ b/include/motion_orientation.h
@@ -0,0 +1,24 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* header for an orientation sensor. */
+#ifndef __CROS_EC_MOTION_ORIENTATION_H
+#define __CROS_EC_MOTION_ORIENTATION_H
+
+#include "chipset.h"
+#include "common.h"
+#include "ec_commands.h"
+#include "motion_sense.h"
+
+enum motionsensor_orientation
+motion_orientation_remap(const struct motion_sensor_t *s,
+			 enum motionsensor_orientation orientation);
+
+bool motion_orientation_changed(const struct motion_sensor_t *s);
+enum motionsensor_orientation *
+motion_orientation_ptr(const struct motion_sensor_t *s);
+void motion_orientation_update(const struct motion_sensor_t *s);
+
+#endif /* __CROS_EC_MOTION_ORIENTATION_H */
diff --git a/include/motion_sense.h b/include/motion_sense.h
index f6a4911239..a8ec859455 100644
--- a/include/motion_sense.h
+++ b/include/motion_sense.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,13 +8,15 @@
 #ifndef __CROS_EC_MOTION_SENSE_H
 #define __CROS_EC_MOTION_SENSE_H
 
+#include "atomic.h"
+#include "body_detection.h"
 #include "chipset.h"
 #include "common.h"
 #include "ec_commands.h"
-#include "gpio.h"
 #include "i2c.h"
 #include "math_util.h"
 #include "queue.h"
+#include "task.h"
 #include "timer.h"
 #include "util.h"
 
@@ -38,7 +40,6 @@ enum sensor_config {
 #define SENSOR_ACTIVE_S0_S3 (SENSOR_ACTIVE_S3 | SENSOR_ACTIVE_S0)
 #define SENSOR_ACTIVE_S0_S3_S5 (SENSOR_ACTIVE_S0_S3 | SENSOR_ACTIVE_S5)
 
-
 /*
  * Events layout:
  * 0                       8              10
@@ -48,57 +49,49 @@ enum sensor_config {
  */
 
 /* First 8 events for sensor interrupt lines */
-#define TASK_EVENT_MOTION_INTERRUPT_NUM      8
+#define TASK_EVENT_MOTION_INTERRUPT_NUM 8
 #define TASK_EVENT_MOTION_INTERRUPT_MASK \
 	((1 << TASK_EVENT_MOTION_INTERRUPT_NUM) - 1)
-#define TASK_EVENT_MOTION_SENSOR_INTERRUPT(_sensor_id) \
-	BUILD_CHECK_INLINE( \
-		TASK_EVENT_CUSTOM_BIT(_sensor_id), \
-		_sensor_id < TASK_EVENT_MOTION_INTERRUPT_NUM)
+#define TASK_EVENT_MOTION_SENSOR_INTERRUPT(_sensor_id)        \
+	BUILD_CHECK_INLINE(TASK_EVENT_CUSTOM_BIT(_sensor_id), \
+			   _sensor_id < TASK_EVENT_MOTION_INTERRUPT_NUM)
 
 /* Internal events to motion sense task.*/
 #define TASK_EVENT_MOTION_FIRST_INTERNAL_EVENT TASK_EVENT_MOTION_INTERRUPT_NUM
-#define TASK_EVENT_MOTION_INTERNAL_EVENT_NUM    2
+#define TASK_EVENT_MOTION_INTERNAL_EVENT_NUM 2
 #define TASK_EVENT_MOTION_FLUSH_PENDING \
 	TASK_EVENT_CUSTOM_BIT(TASK_EVENT_MOTION_FIRST_INTERNAL_EVENT)
 #define TASK_EVENT_MOTION_ODR_CHANGE \
 	TASK_EVENT_CUSTOM_BIT(TASK_EVENT_MOTION_FIRST_INTERNAL_EVENT + 1)
 
 /* Activity events */
-#define TASK_EVENT_MOTION_FIRST_SW_EVENT   \
+#define TASK_EVENT_MOTION_FIRST_SW_EVENT \
 	(TASK_EVENT_MOTION_INTERRUPT_NUM + TASK_EVENT_MOTION_INTERNAL_EVENT_NUM)
-#define TASK_EVENT_MOTION_ACTIVITY_INTERRUPT(_activity_id) \
-	(TASK_EVENT_CUSTOM_BIT( \
-		TASK_EVENT_MOTION_FIRST_SW_EVENT + (_activity_id)))
-
+#define TASK_EVENT_MOTION_ACTIVITY_INTERRUPT(_activity_id)        \
+	(TASK_EVENT_CUSTOM_BIT(TASK_EVENT_MOTION_FIRST_SW_EVENT + \
+			       (_activity_id)))
 
-#define ROUND_UP_FLAG BIT(31)
+#define ROUND_UP_FLAG ((uint32_t)BIT(31))
 #define BASE_ODR(_odr) ((_odr) & ~ROUND_UP_FLAG)
 #define BASE_RANGE(_range) ((_range) & ~ROUND_UP_FLAG)
 
-#ifdef CONFIG_ACCEL_FIFO
-#define MAX_FIFO_EVENT_COUNT CONFIG_ACCEL_FIFO_SIZE
-#else
-#define MAX_FIFO_EVENT_COUNT 0
-#endif
-
 /*
- * I2C/SPI Slave Address encoding for motion sensors
+ * I2C/SPI Address flags encoding for motion sensors
  * - The generic defines, I2C_ADDR_MASK and I2C_IS_BIG_ENDIAN_MASK
  *   are defined in i2c.h.
  * - Motion sensors support some sensors on the SPI bus, so this
  *   overloads the I2C Address to use a single bit to indicate
  *   it is a SPI address instead of an I2C.  Since SPI does not
- *   use slave addressing, it is up to the driver to use this
+ *   use peripheral addressing, it is up to the driver to use this
  *   field as it sees fit
  */
-#define SLAVE_MK_I2C_ADDR_FLAGS(addr)	(addr)
-#define SLAVE_MK_SPI_ADDR_FLAGS(addr)	((addr) | I2C_FLAG_ADDR_IS_SPI)
+#define ACCEL_MK_I2C_ADDR_FLAGS(addr) (addr)
+#define ACCEL_MK_SPI_ADDR_FLAGS(addr) ((addr) | I2C_FLAG_ADDR_IS_SPI)
 
-#define SLAVE_GET_I2C_ADDR(addr_flags)	(I2C_GET_ADDR(addr_flags))
-#define SLAVE_GET_SPI_ADDR(addr_flags)	((addr_flags) & I2C_ADDR_MASK)
+#define ACCEL_GET_I2C_ADDR(addr_flags) (I2C_STRIP_FLAGS(addr_flags))
+#define ACCEL_GET_SPI_ADDR(addr_flags) ((addr_flags)&I2C_ADDR_MASK)
 
-#define SLAVE_IS_SPI(addr_flags)	((addr_flags) & I2C_FLAG_ADDR_IS_SPI)
+#define ACCEL_ADDR_IS_SPI(addr_flags) ((addr_flags)&I2C_FLAG_ADDR_IS_SPI)
 
 /*
  * Define the frequency to use in max_frequency based on the maximal frequency
@@ -106,9 +99,10 @@ enum sensor_config {
  * Return a frequency the sensor supports.
  * Trigger a compilation error when the EC way to slow for the sensor.
  */
-#define MOTION_MAX_SENSOR_FREQUENCY(_max, _step) GENERIC_MIN( \
-	(_max) / (CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ >= (_step)), \
-	(_step) << __fls(CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ / (_step)))
+#define MOTION_MAX_SENSOR_FREQUENCY(_max, _step)                         \
+	GENERIC_MIN(                                                     \
+		(_max) / (CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ >= (_step)), \
+		(_step) << __fls(CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ / (_step)))
 
 struct motion_data_t {
 	/*
@@ -131,9 +125,7 @@ struct motion_data_t {
  * When set, spoof mode will allow the EC to report arbitrary values for any of
  * the components.
  */
-#define MOTIONSENSE_FLAG_IN_SPOOF_MODE		BIT(1)
-#define MOTIONSENSE_FLAG_INT_SIGNAL		BIT(2)
-#define MOTIONSENSE_FLAG_INT_ACTIVE_HIGH	BIT(3)
+#define MOTIONSENSE_FLAG_IN_SPOOF_MODE BIT(1)
 
 struct online_calib_data {
 	/**
@@ -166,17 +158,15 @@ struct motion_sensor_t {
 	enum motionsensor_location location;
 	const struct accelgyro_drv *drv;
 	/* One mutex per physical chip. */
-	struct mutex *mutex;
+	mutex_t *mutex;
 	void *drv_data;
-	/* Only valid if flags & MOTIONSENSE_FLAG_INT_SIGNAL is true. */
-	enum gpio_signal int_signal;
 	/* Data used for online calibraiton, must match the sensor type. */
 	struct online_calib_data
 		online_calib_data[__cfg_select(CONFIG_ONLINE_CALIB, 1, 0)];
 
 	/* i2c port */
 	uint8_t port;
-	/* i2c address or SPI slave logic GPIO. */
+	/* i2c address or SPI port */
 	uint16_t i2c_spi_addr_flags;
 
 	/*
@@ -192,6 +182,9 @@ struct motion_sensor_t {
 	 */
 	int default_range;
 
+	/* Range currently used by the sensor. */
+	int current_range;
+
 	/*
 	 * There are 4 configuration parameters to deal with different
 	 * configuration
@@ -210,6 +203,11 @@ struct motion_sensor_t {
 	 */
 	struct motion_data_t config[SENSOR_CONFIG_MAX];
 
+#ifdef CONFIG_BODY_DETECTION
+	/* Body detection sensor configuration. */
+	const struct body_detect_params *bd_params;
+#endif
+
 	/* state parameters */
 	enum sensor_state state;
 	intv3_t raw_xyz;
@@ -217,7 +215,7 @@ struct motion_sensor_t {
 	intv3_t spoof_xyz;
 
 	/* How many flush events are pending */
-	uint32_t flush_pending;
+	atomic_t flush_pending;
 
 	/*
 	 * Allow EC to request an higher frequency for the sensors than the AP.
@@ -227,12 +225,6 @@ struct motion_sensor_t {
 	uint16_t oversampling;
 	uint16_t oversampling_ratio;
 
-	/*
-	 * How many vector events are lost in the FIFO since last time
-	 * FIFO info has been transmitted.
-	 */
-	uint16_t lost;
-
 	/*
 	 * For sensors in forced mode the ideal time to collect the next
 	 * measurement.
@@ -259,20 +251,18 @@ struct motion_sensor_t {
  * When we process CMD_DUMP, we want to be sure the motion sense
  * task is not updating the sensor values at the same time.
  */
-extern struct mutex g_sensor_mutex;
+extern mutex_t g_sensor_mutex;
 
 /* Defined at board level. */
 extern struct motion_sensor_t motion_sensors[];
 
 #ifdef CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-extern unsigned motion_sensor_count;
+extern unsigned int motion_sensor_count;
 #else
-extern const unsigned motion_sensor_count;
+extern const unsigned int motion_sensor_count;
 #endif
-#if (!defined HAS_TASK_ALS) && (defined CONFIG_ALS)
 /* Needed if reading ALS via LPC is needed */
 extern const struct motion_sensor_t *motion_als_sensors[];
-#endif
 
 /* optionally defined at board level */
 extern unsigned int motion_min_interval;
@@ -281,7 +271,7 @@ extern unsigned int motion_min_interval;
  * Priority of the motion sense resume/suspend hooks, to be sure associated
  * hooks are scheduled properly.
  */
-#define MOTION_SENSE_HOOK_PRIO (HOOK_PRIO_DEFAULT)
+#define MOTION_SENSE_HOOK_PRIO HOOK_PRIO_DEFAULT
 
 /**
  * Take actions at end of sensor initialization:
@@ -290,7 +280,7 @@ extern unsigned int motion_min_interval;
  *
  * @param sensor sensor which was just initialized
  */
-int sensor_init_done(const struct motion_sensor_t *sensor);
+int sensor_init_done(struct motion_sensor_t *sensor);
 
 /**
  * Board specific function that is called when a double_tap event is detected.
@@ -298,11 +288,19 @@ int sensor_init_done(const struct motion_sensor_t *sensor);
  */
 void sensor_board_proc_double_tap(void);
 
-#ifdef CONFIG_ORIENTATION_SENSOR
-enum motionsensor_orientation motion_sense_remap_orientation(
-		const struct motion_sensor_t *s,
-		enum motionsensor_orientation orientation);
-#endif
+/**
+ * Board specific function to double check lid angle calculation is possible.
+ *
+ */
+int sensor_board_is_lid_angle_available(void);
+
+/**
+ * Commit the data in a sensor's raw_xyz vector. This operation might have
+ * different meanings depending on the CONFIG_ACCEL_FIFO flag.
+ *
+ * @param s Pointer to the sensor.
+ */
+void motion_sense_push_raw_xyz(struct motion_sensor_t *s);
 
 /*
  * There are 4 variables that represent the number of sensors:
@@ -319,6 +317,7 @@ enum motionsensor_orientation motion_sense_remap_orientation(
 #define ALL_MOTION_SENSORS (MOTION_SENSE_ACTIVITY_SENSOR_ID + 1)
 #define MAX_MOTION_SENSORS (SENSOR_COUNT + 1)
 #else
+#define MOTION_SENSE_ACTIVITY_SENSOR_ID (-1)
 #define ALL_MOTION_SENSORS (motion_sensor_count)
 #define MAX_MOTION_SENSORS (SENSOR_COUNT)
 #endif
@@ -358,12 +357,17 @@ static inline void ec_motion_sensor_clamp_i16s(int16_t *arr, const int32_t *v)
 }
 
 /* direct assignment */
-static inline void ec_motion_sensor_fill_values(
-		struct ec_response_motion_sensor_data *dst, const int32_t *v)
+static inline void
+ec_motion_sensor_fill_values(struct ec_response_motion_sensor_data *dst,
+			     const int32_t *v)
 {
 	dst->data[0] = v[0];
 	dst->data[1] = v[1];
 	dst->data[2] = v[2];
 }
 
+#ifdef CONFIG_ZTEST
+enum sensor_config motion_sense_get_ec_config(void);
+#endif
+
 #endif /* __CROS_EC_MOTION_SENSE_H */
diff --git a/include/motion_sense_fifo.h b/include/motion_sense_fifo.h
index 554475d9f3..4f0e88ed5b 100644
--- a/include/motion_sense_fifo.h
+++ b/include/motion_sense_fifo.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,8 +12,8 @@
 enum motion_sense_async_event {
 	ASYNC_EVENT_FLUSH = MOTIONSENSE_SENSOR_FLAG_FLUSH |
 			    MOTIONSENSE_SENSOR_FLAG_TIMESTAMP,
-	ASYNC_EVENT_ODR =   MOTIONSENSE_SENSOR_FLAG_ODR |
-			    MOTIONSENSE_SENSOR_FLAG_TIMESTAMP,
+	ASYNC_EVENT_ODR = MOTIONSENSE_SENSOR_FLAG_ODR |
+			  MOTIONSENSE_SENSOR_FLAG_TIMESTAMP,
 };
 
 /**
@@ -21,17 +21,44 @@ enum motion_sense_async_event {
  */
 void motion_sense_fifo_init(void);
 
+/**
+ * Set the expected period between samples. Must be call under
+ * g_mutex_lock each time the sensor ODR changes.
+ *
+ * @param sensor_num Affected sensor
+ * @param data_period expected milliseconds between samples.
+ */
+void motion_sense_set_data_period(int sensor_num, uint32_t data_period);
+
+/**
+ * Whether or not we need to bypass the FIFO to send an important message.
+ *
+ * @return Non zero when a bypass is needed.
+ */
+int motion_sense_fifo_bypass_needed(void);
+
+/**
+ * Whether or not we need to interrupt the AP
+ *
+ * Return true when we have not send FIFO event for a long time.
+ *
+ * @return Non zero when a wake-up is needed.
+ */
+int motion_sense_fifo_interrupt_needed(void);
+
 /**
  * Whether or not we need to wake up the AP.
  *
+ * When the wakeup flag is set, the bypass flag must be set to.
+ *
  * @return Non zero when a wake-up is needed.
  */
 int motion_sense_fifo_wake_up_needed(void);
 
 /**
- * Resets the flag for wake up needed.
+ * Resets the flag for wake up and bypass needed.
  */
-void motion_sense_fifo_reset_wake_up_needed(void);
+void motion_sense_fifo_reset_needed_flags(void);
 
 /**
  * Insert an async event into the fifo.
@@ -39,9 +66,8 @@ void motion_sense_fifo_reset_wake_up_needed(void);
  * @param sensor The sensor that generated the async event.
  * @param event The event to insert.
  */
-void motion_sense_fifo_insert_async_event(
-	struct motion_sensor_t *sensor,
-	enum motion_sense_async_event event);
+void motion_sense_fifo_insert_async_event(struct motion_sensor_t *sensor,
+					  enum motion_sense_async_event event);
 
 /**
  * Insert a timestamp into the fifo.
@@ -60,11 +86,9 @@ void motion_sense_fifo_add_timestamp(uint32_t timestamp);
  * @param time accurate time (ideally measured in an interrupt) the sample
  *             was taken at
  */
-void motion_sense_fifo_stage_data(
-	struct ec_response_motion_sensor_data *data,
-	struct motion_sensor_t *sensor,
-	int valid_data,
-	uint32_t time);
+void motion_sense_fifo_stage_data(struct ec_response_motion_sensor_data *data,
+				  struct motion_sensor_t *sensor,
+				  int valid_data, uint32_t time);
 
 /**
  * Commit all the currently staged data to the fifo. Doing so makes it readable
@@ -76,12 +100,12 @@ void motion_sense_fifo_commit_data(void);
  * Get information about the fifo.
  *
  * @param fifo_info The struct to modify with the current information about the
- *	  fifo.
+ *	  fifo. WARNING: This must point to a buffer big enough for the struct
+ *	  and also sizeof(uint16_t) * MAX_MOTION_SENSORS of extra space.
  * @param reset Whether or not to reset statistics after reading them.
  */
 void motion_sense_fifo_get_info(
-	struct ec_response_motion_sense_fifo_info *fifo_info,
-	int reset);
+	struct ec_response_motion_sense_fifo_info *fifo_info, int reset);
 
 /**
  * Check whether or not the fifo has gone over its threshold.
diff --git a/include/newton_fit.h b/include/newton_fit.h
index b4db64c814..dc0a8ffe6e 100644
--- a/include/newton_fit.h
+++ b/include/newton_fit.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,8 +9,8 @@
 #define __CROS_EC_NEWTON_FIT_H
 
 #include "queue.h"
-#include "vec3.h"
 #include "stdbool.h"
+#include "vec3.h"
 
 struct newton_fit_orientation {
 	/** An orientations. */
diff --git a/include/ocpc.h b/include/ocpc.h
index a2c4d3a644..050a40c099 100644
--- a/include/ocpc.h
+++ b/include/ocpc.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,6 +10,8 @@
 #ifndef __CROS_EC_OCPC_H_
 #define __CROS_EC_OCPC_H_
 
+#include "battery.h"
+
 #define OCPC_UNINIT 0xdededede
 
 struct ocpc_data {
@@ -17,7 +19,7 @@ struct ocpc_data {
 	int active_chg_chip;
 
 	int combined_rsys_rbatt_mo; /* System resistance b/w output and Vbatt */
-	int rsys_mo;  /* System resistance b/w output and VSYS node */
+	int rsys_mo; /* System resistance b/w output and VSYS node */
 	int rbatt_mo; /* Resistance between VSYS node and battery */
 
 	/* ADC values */
@@ -38,19 +40,20 @@ struct ocpc_data {
 #endif /* HAS_TASK_PD_C1 */
 };
 
-#define OCPC_NO_ISYS_MEAS_CAP	BIT(0)
+#define OCPC_NO_ISYS_MEAS_CAP BIT(0)
 
 /** Set the VSYS target for the secondary charger IC.
  *
- * @param curr: Pointer to desired_input_current
+ * @param desired_charger_input_current: Pointer to desired_input_current
  * @param ocpc: Pointer to OCPC data
- * @param voltage_mv: The desired voltage
- * @param current_ma: The desired current
+ * @param desired_batt_current_ma: The desired voltage
+ * @param desired_batt_voltage_mv: The desired current
  * @return EC_SUCCESS on success, error otherwise.
  */
-int ocpc_config_secondary_charger(int *desired_input_current,
+int ocpc_config_secondary_charger(int *desired_charger_input_current,
 				  struct ocpc_data *ocpc,
-				  int voltage_mv, int current_ma);
+				  int desired_batt_voltage_mv,
+				  int desired_batt_current_ma);
 
 /** Get the runtime data from the various ADCs.
  *
@@ -59,9 +62,8 @@ int ocpc_config_secondary_charger(int *desired_input_current,
 void ocpc_get_adcs(struct ocpc_data *ocpc);
 
 /* Set the PID constants for the charging loop */
-__overridable void ocpc_get_pid_constants(int *kp, int *kp_div,
-					  int *ki, int *ki_div,
-					  int *kd, int *kd_div);
+__override_proto void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+					     int *ki_div, int *kd, int *kd_div);
 
 /*
  ** Set up some initial values for the OCPC data structure.  This will call off
@@ -71,6 +73,14 @@ __overridable void ocpc_get_pid_constants(int *kp, int *kp_div,
  */
 void ocpc_init(struct ocpc_data *ocpc);
 
+/**
+ * Reset the OCPC module.  This also sets the initial VSYS target to the current
+ * battery voltage
+ *
+ * @param ocpc: Pointer to OCPC data
+ */
+void ocpc_reset(struct ocpc_data *ocpc);
+
 /**
  * Board specific OCPC data structure initialization.  This can be used to set
  * up and charger flags.  The default implementation does nothing.
@@ -78,4 +88,41 @@ void ocpc_init(struct ocpc_data *ocpc);
  * @param ocpc: Pointer to OCPC data
  */
 __override_proto void board_ocpc_init(struct ocpc_data *ocpc);
+
+#ifdef TEST_BUILD
+/**
+ * @brief Force a reload of PID constants by calling ocpc_get_pid_constants().
+ */
+void ocpc_set_pid_constants(void);
+
+/**
+ * @brief Return the value of viz_output
+ *
+ * @return int
+ */
+int test_ocpc_get_viz_output(void);
+
+/**
+ * @brief Return the value of debug_output
+ *
+ * @return int
+ */
+int test_ocpc_get_debug_output(void);
+
+/**
+ * @brief Reset state used to track resistance calculations.
+ */
+void test_ocpc_reset_resistance_state(void);
+
+/**
+ * @brief Calculate the system impedance
+ *
+ * @param ocpc OCPC data struct pointer
+ * @param battery Battery params pointer
+ * @return enum ec_error_list Success or error code
+ */
+enum ec_error_list ocpc_calc_resistances(struct ocpc_data *ocpc,
+					 struct batt_params *battery);
+#endif
+
 #endif /* __CROS_EC_OCPC_H */
diff --git a/include/onewire.h b/include/onewire.h
index e2fda26b7b..0b328ceedc 100644
--- a/include/onewire.h
+++ b/include/onewire.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,7 +10,7 @@
  * functions are run at low priority, communication may be garbled.  However,
  * these functions are also slow enough (~1ms per call) that it's really not
  * desirable to put them at high priority.  So make sure you check the
- * confirmation code from the slave for any communication, and retry a few
+ * confirmation code from the peripheral for any communication, and retry a few
  * times in case of failure.
  */
 
@@ -40,4 +40,4 @@ int onewire_read(void);
  */
 void onewire_write(int data);
 
-#endif  /* __CROS_EC_ONEWIRE_H */
+#endif /* __CROS_EC_ONEWIRE_H */
diff --git a/include/online_calibration.h b/include/online_calibration.h
index 6f8fad33a7..abeb192b75 100644
--- a/include/online_calibration.h
+++ b/include/online_calibration.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,10 +22,9 @@ void online_calibration_init(void);
  * @param timestamp The time associated with the sample
  * @return EC_SUCCESS when successful.
  */
-int online_calibration_process_data(
-	struct ec_response_motion_sensor_data *data,
-	struct motion_sensor_t *sensor,
-	uint32_t timestamp);
+int online_calibration_process_data(struct ec_response_motion_sensor_data *data,
+				    struct motion_sensor_t *sensor,
+				    uint32_t timestamp);
 
 /**
  * Check if new calibration values are available since the last read.
@@ -41,6 +40,7 @@ bool online_calibration_has_new_values(void);
  * @param out The target to copy the data into.
  * @return True if a value was written to `out`.
  */
-bool online_calibration_read(int sensor_num, int16_t out[3]);
+bool online_calibration_read(struct motion_sensor_t *sensor,
+			     struct ec_response_online_calibration_data *out);
 
 #endif /* __CROS_EC_ONLINE_CALIBRATION_H */
diff --git a/include/otp.h b/include/otp.h
index 7851411202..2047a2e19f 100644
--- a/include/otp.h
+++ b/include/otp.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -29,4 +29,4 @@ int otp_write_serial(const char *serialno);
  */
 const char *otp_read_serial(void);
 
-#endif  /* __CROS_EC_OTP_H */
+#endif /* __CROS_EC_OTP_H */
diff --git a/include/overflow.h b/include/overflow.h
index 42eab6a094..884eec884a 100644
--- a/include/overflow.h
+++ b/include/overflow.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,7 +26,7 @@
 	__has_builtin(__builtin_mul_overflow)
 #define COMPILER_HAS_GENERIC_BUILTIN_OVERFLOW 1
 #endif
-#endif  /* __clang__ */
+#endif /* __clang__ */
 
 #include "third_party/linux/overflow.h"
 
diff --git a/include/panic.h b/include/panic.h
index b6e1c0d8cd..ce357eafad 100644
--- a/include/panic.h
+++ b/include/panic.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -9,113 +9,26 @@
 #ifndef __CROS_EC_PANIC_H
 #define __CROS_EC_PANIC_H
 
+#include "common.h"
+#include "panic_defs.h"
+#include "software_panic.h"
+
 #include <stdarg.h>
 #include <stdint.h>
-#include <stdnoreturn.h>
 
-#include "software_panic.h"
+#include <stdnoreturn.h>
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-/* ARM Cortex-Mx registers saved on panic */
-struct cortex_panic_data {
-	uint32_t regs[12];        /* psp, ipsr, msp, r4-r11, lr(=exc_return).
-				   * In version 1, that was uint32_t regs[11] =
-				   * psp, ipsr, lr, r4-r11
-				   */
-	uint32_t frame[8];        /* r0-r3, r12, lr, pc, xPSR */
-
-	uint32_t cfsr;
-	uint32_t bfar;
-	uint32_t mfar;
-	uint32_t shcsr;
-	uint32_t hfsr;
-	uint32_t dfsr;
-};
-
-/* NDS32 N8 registers saved on panic */
-struct nds32_n8_panic_data {
-	uint32_t itype;
-	uint32_t regs[16];        /* r0-r10, r15, fp, gp, lp, sp */
-	uint32_t ipc;
-	uint32_t ipsw;
-};
-
-/* RISC-V RV32I registers saved on panic */
-struct rv32i_panic_data {
-	uint32_t regs[31];        /* sp, ra, gp, tp, a0-a7, t0-t6 s0-s11 */
-	uint32_t mepc;            /* mepc */
-	uint32_t mcause;          /* mcause */
-};
-
-/* x86 registers saved on panic */
-struct x86_panic_data {
-	uint32_t vector;          /* Exception vector number */
-
-	/* Data pushed when exception handler called */
-	uint32_t error_code;
-	uint32_t eip;
-	uint32_t cs;
-	uint32_t eflags;
-
-	/* General purpose registers */
-	uint32_t eax;
-	uint32_t ebx;
-	uint32_t ecx;
-	uint32_t edx;
-	uint32_t esi;
-	uint32_t edi;
-
-	/* Task id at time of panic */
-	uint8_t task_id;
-};
-
-/* Data saved across reboots */
-struct panic_data {
-	uint8_t arch;             /* Architecture (PANIC_ARCH_*) */
-	uint8_t struct_version;   /* Structure version (currently 2) */
-	uint8_t flags;            /* Flags (PANIC_DATA_FLAG_*) */
-	uint8_t reserved;         /* Reserved; set 0 */
-
-	/* core specific panic data */
-	union {
-		struct cortex_panic_data cm;       /* Cortex-Mx registers */
-		struct nds32_n8_panic_data nds_n8; /* NDS32 N8 registers */
-		struct x86_panic_data x86;         /* Intel x86 */
-		struct rv32i_panic_data riscv;     /* RISC-V RV32I */
-	};
-
-	/*
-	 * These fields go at the END of the struct so we can find it at the
-	 * end of memory.
-	 */
-	uint32_t struct_size;     /* Size of this struct */
-	uint32_t magic;           /* PANIC_SAVE_MAGIC if valid */
-};
-
-#define PANIC_DATA_MAGIC 0x21636e50  /* "Pnc!" */
-enum panic_arch {
-	PANIC_ARCH_CORTEX_M = 1,     /* Cortex-M architecture */
-	PANIC_ARCH_NDS32_N8 = 2,     /* NDS32 N8 architecture */
-	PANIC_ARCH_X86 = 3,          /* Intel x86 */
-	PANIC_ARCH_RISCV_RV32I = 4,  /* RISC-V RV32I */
-};
+#ifdef CONFIG_RO_PANIC_DATA_SIZE
+BUILD_ASSERT(sizeof(struct panic_data) == CONFIG_RO_PANIC_DATA_SIZE);
+#endif
 
 /* Use PANIC_DATA_PTR to refer to the persistent storage location */
 #define PANIC_DATA_PTR ((struct panic_data *)CONFIG_PANIC_DATA_BASE)
 
-/* Flags for panic_data.flags */
-/* panic_data.frame is valid */
-#define PANIC_DATA_FLAG_FRAME_VALID    BIT(0)
-/* Already printed at console */
-#define PANIC_DATA_FLAG_OLD_CONSOLE    BIT(1)
-/* Already returned via host command */
-#define PANIC_DATA_FLAG_OLD_HOSTCMD    BIT(2)
-/* Already reported via host event */
-#define PANIC_DATA_FLAG_OLD_HOSTEVENT  BIT(3)
-
 /**
  * Write a string to the panic reporting device
  *
@@ -134,8 +47,8 @@ void panic_puts(const char *s);
  * @param format	printf-style format string
  * @param ...		Arguments to process
  */
-__attribute__((__format__(__printf__, 1, 2)))
-void panic_printf(const char *format, ...);
+__attribute__((__format__(__printf__, 1, 2))) void
+panic_printf(const char *format, ...);
 
 /*
  * Print saved panic information
@@ -144,6 +57,14 @@ void panic_printf(const char *format, ...);
  */
 void panic_data_print(const struct panic_data *pdata);
 
+/*
+ * Print saved panic information on console channel to observe panic
+ * information
+ *
+ * @param pdata pointer to saved panic data
+ */
+void panic_data_ccprint(const struct panic_data *pdata);
+
 /**
  * Report an assertion failure and reset
  *
@@ -153,10 +74,18 @@ void panic_data_print(const struct panic_data *pdata);
  * @param linenum	Line number where assertion happened
  */
 #ifdef CONFIG_DEBUG_ASSERT_BRIEF
-noreturn void panic_assert_fail(const char *fname, int linenum);
+#if !(defined(TEST_FUZZ) || defined(CONFIG_ZTEST))
+noreturn
+#endif
+	void
+	panic_assert_fail(const char *fname, int linenum);
 #else
-noreturn void panic_assert_fail(const char *msg, const char *func,
-				const char *fname, int linenum);
+#if !(defined(TEST_FUZZ) || defined(CONFIG_ZTEST))
+noreturn
+#endif
+	void
+	panic_assert_fail(const char *msg, const char *func, const char *fname,
+			  int linenum);
 #endif
 
 /**
@@ -164,19 +93,30 @@ noreturn void panic_assert_fail(const char *msg, const char *func,
  *
  * @param msg	Panic message
  */
-noreturn void panic(const char *msg);
+#if !(defined(TEST_FUZZ) || defined(CONFIG_ZTEST))
+noreturn
+#endif
+	void
+	panic(const char *msg);
 
 /**
  * Display a default message and reset
  */
-noreturn void panic_reboot(void);
+#if !(defined(TEST_FUZZ) || defined(CONFIG_ZTEST))
+noreturn
+#endif
+	void
+	panic_reboot(void);
 
-#ifdef CONFIG_SOFTWARE_PANIC
 /**
  * Store a panic log and halt the system for a software-related reason, such as
  * stack overflow or assertion failure.
  */
-noreturn void software_panic(uint32_t reason, uint32_t info);
+#if !(defined(TEST_FUZZ) || defined(CONFIG_ZTEST))
+noreturn
+#endif
+	void
+	software_panic(uint32_t reason, uint32_t info);
 
 /**
  * Log a panic in the panic log, but don't halt the system. Normally
@@ -188,7 +128,15 @@ void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception);
  * Retrieve the currently stored panic reason + info.
  */
 void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception);
-#endif
+
+#ifdef CONFIG_ZEPHYR
+/**
+ * Zephyr utility for architecture specific logic to run when setting panic
+ * reason.
+ */
+__override_proto void arch_panic_set_reason(uint32_t reason, uint32_t info,
+					    uint8_t exception);
+#endif /* CONFIG_ZEPHYR */
 
 /**
  * Enable/disable bus fault handler
@@ -201,8 +149,8 @@ void ignore_bus_fault(int ignored);
  * Return a pointer to the saved data from a previous panic that can be
  * safely interpreted
  *
- * @param pointer to the valid panic data, or NULL if none available (for example,
- * the last reboot was not caused by a panic).
+ * @param pointer to the valid panic data, or NULL if none available (for
+ * example, the last reboot was not caused by a panic).
  */
 struct panic_data *panic_get_data(void);
 
@@ -217,16 +165,36 @@ struct panic_data *panic_get_data(void);
  */
 uintptr_t get_panic_data_start(void);
 
-/*
- * Return a pointer to panic_data structure that can be safely written.
- * Please note that this function can move jump data and jump tags.
- * It can also delete panic data from previous boot, so this function
- * should be used when we are sure that we don't need it.
+#ifdef CONFIG_BOARD_NATIVE_POSIX
+/**
+ * @brief Test-only function for accessing the pdata_ptr object.
+ *
+ * @return struct panic_data* pdata_ptr
+ */
+struct panic_data *test_get_panic_data_pointer(void);
+#endif
+
+/**
+ * Return a pointer to panic_data structure that can be safely written.  Please
+ * note that this function can move jump data and jump tags.  It can also delete
+ * panic data from previous boot, so this function should be used when we are
+ * sure that we don't need it.
+ *
+ * NOTE: Invoking this function without subsequently setting the rest of the
+ * panic data is unsafe because it leaves the panic data in an unfinished state
+ * that may be inappropriately reported to the AP.
+ * TODO(b/274661193): Finalize panic data with panic magic.
  *
  * @param pointer to panic_data structure that can be safely written
  */
 struct panic_data *get_panic_data_write(void);
 
+/**
+ * Return a pointer to the stack of the process that caused the panic.
+ * The implementation of this function will depend on the architecture.
+ */
+uint32_t get_panic_stack_pointer(const struct panic_data *pdata);
+
 /**
  * Chip-specific implementation for backing up panic data to persistent
  * storage. This function is used to ensure that the panic data can survive loss
@@ -241,4 +209,20 @@ void chip_panic_data_backup(void);
 }
 #endif
 
-#endif  /* __CROS_EC_PANIC_H */
+#ifdef TEST_BUILD
+/**
+ * @brief Wrapper for accessing the command_crash() console command
+ * implementation directly in unit tests. It cannot be called normally through
+ * the shell interface because it upsets the shell's internal state when the
+ * command doesn't return after a crash. command_crash() cannot be marked
+ * test_export_static directly due to an implementation detail in
+ * DECLARE_CONSOLE_COMMAND().
+ *
+ * @param argc Number of CLI args in `argv`
+ * @param argv CLI arguments
+ * @return int Return value
+ */
+int test_command_crash(int argc, const char **argv);
+#endif /* TEST_BUILD*/
+
+#endif /* __CROS_EC_PANIC_H */
diff --git a/include/panic_defs.h b/include/panic_defs.h
new file mode 100644
index 0000000000..64cfd9ecc8
--- /dev/null
+++ b/include/panic_defs.h
@@ -0,0 +1,153 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Panic handling macros and structures.
+ */
+
+#ifndef __CROS_EC_PANIC_DEFS_H
+#define __CROS_EC_PANIC_DEFS_H
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+enum cortex_panic_frame_registers {
+	CORTEX_PANIC_FRAME_REGISTER_R0 = 0,
+	CORTEX_PANIC_FRAME_REGISTER_R1,
+	CORTEX_PANIC_FRAME_REGISTER_R2,
+	CORTEX_PANIC_FRAME_REGISTER_R3,
+	CORTEX_PANIC_FRAME_REGISTER_R12,
+	CORTEX_PANIC_FRAME_REGISTER_LR,
+	CORTEX_PANIC_FRAME_REGISTER_PC,
+	CORTEX_PANIC_FRAME_REGISTER_PSR,
+	NUM_CORTEX_PANIC_FRAME_REGISTERS
+};
+
+enum cortex_panic_registers {
+	CORTEX_PANIC_REGISTER_PSP = 0,
+	CORTEX_PANIC_REGISTER_IPSR,
+	CORTEX_PANIC_REGISTER_MSP,
+	CORTEX_PANIC_REGISTER_R4,
+	CORTEX_PANIC_REGISTER_R5,
+	CORTEX_PANIC_REGISTER_R6,
+	CORTEX_PANIC_REGISTER_R7,
+	CORTEX_PANIC_REGISTER_R8,
+	CORTEX_PANIC_REGISTER_R9,
+	CORTEX_PANIC_REGISTER_R10,
+	CORTEX_PANIC_REGISTER_R11,
+	CORTEX_PANIC_REGISTER_LR,
+	NUM_CORTEX_PANIC_REGISTERS
+};
+
+/* ARM Cortex-Mx registers saved on panic */
+struct cortex_panic_data {
+	/* See cortex_panic_registers enum for information about registers */
+	uint32_t regs[NUM_CORTEX_PANIC_REGISTERS];
+
+	/* See cortex_panic_frame_registers enum for more information */
+	uint32_t frame[NUM_CORTEX_PANIC_FRAME_REGISTERS];
+
+	uint32_t cfsr;
+	uint32_t bfar;
+	uint32_t mfar;
+	uint32_t shcsr;
+	uint32_t hfsr;
+	uint32_t dfsr;
+};
+
+/* NDS32 N8 registers saved on panic */
+struct nds32_n8_panic_data {
+	uint32_t itype;
+	uint32_t regs[16]; /* r0-r10, r15, fp, gp, lp, sp */
+	uint32_t ipc;
+	uint32_t ipsw;
+};
+
+/* RISC-V RV32I registers saved on panic */
+struct rv32i_panic_data {
+	uint32_t regs[31]; /* sp, ra, gp, tp, a0-a7, t0-t6, s0-s11 */
+	uint32_t mepc; /* mepc */
+	uint32_t mcause; /* mcause */
+};
+
+/* x86 registers saved on panic */
+struct x86_panic_data {
+	uint32_t vector; /* Exception vector number */
+
+	/* Data pushed when exception handler called */
+	uint32_t error_code;
+	uint32_t eip;
+	uint32_t cs;
+	uint32_t eflags;
+
+	/* General purpose registers */
+	uint32_t eax;
+	uint32_t ebx;
+	uint32_t ecx;
+	uint32_t edx;
+	uint32_t esi;
+	uint32_t edi;
+
+	/* Task id at time of panic */
+	uint8_t task_id;
+};
+
+/* Data saved across reboots */
+struct panic_data {
+	uint8_t arch; /* Architecture (PANIC_ARCH_*) */
+	uint8_t struct_version; /* Structure version (currently 2) */
+	uint8_t flags; /* Flags (PANIC_DATA_FLAG_*) */
+	uint8_t reserved; /* Reserved; set 0 */
+
+	/* core specific panic data */
+	union {
+		struct cortex_panic_data cm; /* Cortex-Mx registers */
+		struct nds32_n8_panic_data nds_n8; /* NDS32 N8 registers */
+		struct x86_panic_data x86; /* Intel x86 */
+#ifndef CONFIG_DO_NOT_INCLUDE_RV32I_PANIC_DATA
+		struct rv32i_panic_data riscv; /* RISC-V RV32I */
+#endif
+	};
+
+	/*
+	 * These fields go at the END of the struct so we can find it at the
+	 * end of memory.
+	 */
+	uint32_t struct_size; /* Size of this struct */
+	uint32_t magic; /* PANIC_SAVE_MAGIC if valid */
+};
+
+#define PANIC_DATA_MAGIC 0x21636e50 /* "Pnc!" */
+enum panic_arch {
+	PANIC_ARCH_CORTEX_M = 1, /* Cortex-M architecture */
+	PANIC_ARCH_NDS32_N8 = 2, /* NDS32 N8 architecture */
+	PANIC_ARCH_X86 = 3, /* Intel x86 */
+#ifndef CONFIG_DO_NOT_INCLUDE_RV32I_PANIC_DATA
+	PANIC_ARCH_RISCV_RV32I = 4, /* RISC-V RV32I */
+#endif
+};
+
+/* Flags for panic_data.flags */
+/* panic_data.frame is valid */
+#define PANIC_DATA_FLAG_FRAME_VALID BIT(0)
+/* Already printed at console */
+#define PANIC_DATA_FLAG_OLD_CONSOLE BIT(1)
+/* Already returned via host command */
+#define PANIC_DATA_FLAG_OLD_HOSTCMD BIT(2)
+/* Already reported via host event */
+#define PANIC_DATA_FLAG_OLD_HOSTEVENT BIT(3)
+/* The data was truncated to fit panic info host cmd */
+#define PANIC_DATA_FLAG_TRUNCATED BIT(4)
+/* System safe mode was started after a panic */
+#define PANIC_DATA_FLAG_SAFE_MODE_STARTED BIT(5)
+/* System safe mode failed to start */
+#define PANIC_DATA_FLAG_SAFE_MODE_FAIL_PRECONDITIONS BIT(6)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CROS_EC_PANIC_DEFS_H */
diff --git a/include/peci.h b/include/peci.h
index 993e7d637d..401e3f999f 100644
--- a/include/peci.h
+++ b/include/peci.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,37 +10,37 @@
 
 #include "common.h"
 
-#define PECI_TARGET_ADDRESS         0x30
-#define PECI_WRITE_DATA_FIFO_SIZE   15
-#define PECI_READ_DATA_FIFO_SIZE    16
+#define PECI_TARGET_ADDRESS 0x30
+#define PECI_WRITE_DATA_FIFO_SIZE 15
+#define PECI_READ_DATA_FIFO_SIZE 16
 
-#define PECI_GET_TEMP_READ_LENGTH   2
-#define PECI_GET_TEMP_WRITE_LENGTH  0
-#define PECI_GET_TEMP_TIMEOUT_US    200
+#define PECI_GET_TEMP_READ_LENGTH 2
+#define PECI_GET_TEMP_WRITE_LENGTH 0
+#define PECI_GET_TEMP_TIMEOUT_US 200
 
 /* PECI Command Code */
 enum peci_command_code {
-	PECI_CMD_PING             = 0x00,
-	PECI_CMD_GET_DIB          = 0xF7,
-	PECI_CMD_GET_TEMP         = 0x01,
-	PECI_CMD_RD_PKG_CFG       = 0xA1,
-	PECI_CMD_WR_PKG_CFG       = 0xA5,
-	PECI_CMD_RD_IAMSR         = 0xB1,
-	PECI_CMD_WR_IAMSR         = 0xB5,
-	PECI_CMD_RD_PCI_CFG       = 0x61,
-	PECI_CMD_WR_PCI_CFG       = 0x65,
+	PECI_CMD_PING = 0x00,
+	PECI_CMD_GET_DIB = 0xF7,
+	PECI_CMD_GET_TEMP = 0x01,
+	PECI_CMD_RD_PKG_CFG = 0xA1,
+	PECI_CMD_WR_PKG_CFG = 0xA5,
+	PECI_CMD_RD_IAMSR = 0xB1,
+	PECI_CMD_WR_IAMSR = 0xB5,
+	PECI_CMD_RD_PCI_CFG = 0x61,
+	PECI_CMD_WR_PCI_CFG = 0x65,
 	PECI_CMD_RD_PCI_CFG_LOCAL = 0xE1,
 	PECI_CMD_WR_PCI_CFG_LOCAL = 0xE5,
 };
 
 struct peci_data {
 	enum peci_command_code cmd_code; /* command code */
-	uint8_t addr;	/* client address */
-	uint8_t w_len;	/* write length */
-	uint8_t r_len;	/* read length */
-	uint8_t *w_buf;	/* buffer pointer of write data */
-	uint8_t *r_buf;	/* buffer pointer of read data */
-	int timeout_us;	/* transaction timeout unit:us */
+	uint8_t addr; /* client address */
+	uint8_t w_len; /* write length */
+	uint8_t r_len; /* read length */
+	uint8_t *w_buf; /* buffer pointer of write data */
+	uint8_t *r_buf; /* buffer pointer of read data */
+	int timeout_us; /* transaction timeout unit:us */
 };
 
 /**
@@ -62,4 +62,4 @@ int peci_temp_sensor_get_val(int idx, int *temp_ptr);
  */
 int peci_transaction(struct peci_data *peci);
 
-#endif  /* __CROS_EC_PECI_H */
+#endif /* __CROS_EC_PECI_H */
diff --git a/include/peripheral_charger.h b/include/peripheral_charger.h
new file mode 100644
index 0000000000..588027cf18
--- /dev/null
+++ b/include/peripheral_charger.h
@@ -0,0 +1,401 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_PERIPHERAL_CHARGER_H
+#define __CROS_EC_PERIPHERAL_CHARGER_H
+
+#include "atomic.h"
+#include "common.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "queue.h"
+#include "stdbool.h"
+#include "task.h"
+
+/*
+ * Peripheral charge manager
+ *
+ * Peripheral charge manager (PCHG) is a state machine (SM), which manages
+ * charge ports to charge peripheral devices. Events can be generated
+ * externally (by a charger chip) or internally (by a host command or the SM
+ * itself). Events are queued and handled first-come-first-serve basis.
+ *
+ * Peripheral charger drivers should implement struct pchg_drv. Each operation
+ * can be synchronous or asynchronous depending on the chip. If a function
+ * works synchronously, it should return EC_SUCCESS. That'll make the SM
+ * immediately queue the next event (if applicable) and transition to the next
+ * state. If a function works asynchronously, it should return
+ * EC_SUCCESS_IN_PROGRESS. That'll make the SM stay in the same state. The SM
+ * is expected to receive IRQ for further information about the operation,
+ * which may or may not make the SM transition to the next state.
+ *
+ * Roughly speaking the SM looks as follows:
+ *
+ *                  +---------------+
+ *                  |     RESET     |
+ *                  +-------+-------+
+ *                          |
+ *                          | INITIALIZED
+ *                          v
+ *                  +---------------+
+ *                  |  INITIALIZED  |<--------------+
+ *                  +------+--------+               |
+ *                         | ^                      |
+ *                 ENABLED | | DISABLED             |
+ *                         v |                      |
+ *                  +--------+------+               |
+ *   +------------->|    ENABLED    |               |
+ *   |              +-----+------+--+               |
+ *   |                    |      |                  |
+ *   |    DEVICE_DETECTED |      | DEVICE_CONNECTED |
+ *   |                    v      |                  |
+ *   | DEVICE_LOST  +----------+ |                  |
+ *   +--------------+ DETECTED +-|------------------+
+ *   |              +-----+----+ |     ERROR        |
+ *   |                    |      |                  |
+ *   |    DEVICE_CONNECTED|      |                  |
+ *   |                    v      v                  |
+ *   |              +---------------+               |
+ *   +--------------+   CONNECTED   +---------------+
+ *   | DEVICE_LOST  +------+--------+  ERROR        |
+ *   |                     | ^                      |
+ *   |      CHARGE_STARTED | | CHARGE_ENDED         |
+ *   |                     | | CHARGE_STOPPED       |
+ *   |                     v |                      |
+ *   |              +--------+------+               |
+ *   +--------------+   CHARGING    +---------------+
+ *     DEVICE_LOST  +---------------+  ERROR
+ *
+ *
+ * In download (firmware update) mode, the state machine transitions as follows:
+ *
+ *                  +---------------+
+ *                  |   DOWNLOAD    |
+ *                  +------+--------+
+ *                         | ^
+ *             UPDATE_OPEN | |
+ *                         | | UPDATE_CLOSE
+ *                         v |
+ *                  +--------+------+
+ *              +-->|  DOWNLOADING  |
+ *              |   +------+--------+
+ *              |          |
+ *              +----------+
+ *              UPDATE_WRITE
+ */
+
+/*
+ * BIST Mode
+ *
+ * BIST mode is implemented as follows. Note == means comparison (i.e. mode
+ * check) and = means assignment (i.e. mode change).
+ *
+ *
+ *                  +---------------+
+ *   +------------->|     RESET     |<-----------------------+
+ *   |              +-------+-------+                        |
+ *   |                      |                                |
+ *   |                      | INITIALIZED                    |
+ *   |                      v                                |
+ *   |              +---------------+  mode==BIST            |
+ *   |              |  INITIALIZED  |---------------+        |
+ *   |              +-------+-------+               |        |
+ *   |                      |                       |        |
+ *   |                      | mode==NORMAL          |        | mode=NORMAL
+ *   |                      |                       |        | bist_cmd=NONE
+ *   | DEVICE_DETECTED      |                       |        |
+ *   | && bist_cmd!=NONE    V                       V        |
+ *   | mode=BIST    +---------------+         +-----------+  |
+ *   +--------------|   ENABLED(*1) |         |    BIST   |--+
+ *   +------------->+------+--------+         +-----------+
+ *   |                     |
+ *   |                     | DEVICE_DETECTED
+ *   |                     |
+ *   | DEVICE_LOST         |
+ *   | bist_cmd=RF_CHARGE  V
+ *   | (*2)          +----------+
+ *   +---------------+ DETECTED |
+ *                   +----------+
+ *
+ * *1 BIST mode is entered on device detection when a BIST command is already
+ *    requested (bist_cmd!=NONE).
+ * *2 Whenever a device is lost, we reset bist_cmd to RF_CHARGE. This makes next
+ *    device detection trigger BIST mode.
+ */
+
+/* Size of event queue. Use it to initialize struct pchg.events. */
+#define PCHG_EVENT_QUEUE_SIZE 8
+
+enum pchg_event {
+	/* No event */
+	PCHG_EVENT_NONE = 0,
+
+	/* IRQ is pending. */
+	PCHG_EVENT_IRQ,
+
+	/* External Events */
+	PCHG_EVENT_RESET,
+	PCHG_EVENT_INITIALIZED,
+	PCHG_EVENT_ENABLED,
+	PCHG_EVENT_DISABLED,
+	PCHG_EVENT_DEVICE_DETECTED,
+	PCHG_EVENT_DEVICE_CONNECTED,
+	PCHG_EVENT_DEVICE_LOST,
+	PCHG_EVENT_CHARGE_STARTED,
+	PCHG_EVENT_CHARGE_UPDATE,
+	PCHG_EVENT_CHARGE_ENDED,
+	PCHG_EVENT_CHARGE_STOPPED,
+	PCHG_EVENT_UPDATE_OPENED,
+	PCHG_EVENT_UPDATE_CLOSED,
+	PCHG_EVENT_UPDATE_WRITTEN,
+	PCHG_EVENT_IN_NORMAL,
+
+	/* Errors */
+	PCHG_EVENT_ERROR,
+
+	/* Internal (a.k.a. Host) Events */
+	PCHG_EVENT_ENABLE,
+	PCHG_EVENT_DISABLE,
+	PCHG_EVENT_BIST_RUN,
+	PCHG_EVENT_BIST_DONE,
+	PCHG_EVENT_UPDATE_OPEN,
+	PCHG_EVENT_UPDATE_WRITE,
+	PCHG_EVENT_UPDATE_CLOSE,
+	PCHG_EVENT_UPDATE_ERROR,
+
+	/* Counter. Add new entry above. */
+	PCHG_EVENT_COUNT
+};
+BUILD_ASSERT(PCHG_EVENT_COUNT <= sizeof(uint32_t) * 8);
+
+enum pchg_error {
+	/* Communication error in link layer (i2c, spi, etc.). */
+	PCHG_ERROR_COMMUNICATION,
+
+	PCHG_ERROR_OVER_TEMPERATURE,
+	PCHG_ERROR_OVER_CURRENT,
+	PCHG_ERROR_FOREIGN_OBJECT,
+
+	/* Protocol error (e.g. NACK returned from a chip). */
+	PCHG_ERROR_RESPONSE,
+	/* Other errors reported by a chip. */
+	PCHG_ERROR_FW_VERSION,
+	PCHG_ERROR_INVALID_FW,
+	PCHG_ERROR_WRITE_FLASH,
+
+	/* All other errors */
+	PCHG_ERROR_OTHER,
+
+	/* Add no entries below here. */
+	PCHG_ERROR_COUNT
+};
+
+#define PCHG_ERROR_MASK(e) BIT(e)
+
+enum pchg_mode {
+	PCHG_MODE_NORMAL = 0,
+	PCHG_MODE_DOWNLOAD,
+	PCHG_MODE_PASSTHRU,
+	PCHG_MODE_BIST,
+	/* Add no more entries below here. */
+	PCHG_MODE_COUNT
+};
+
+enum pchg_bist_cmd {
+	PCHG_BIST_CMD_ANTENNA = 0x00,
+	PCHG_BIST_CMD_RF_CHARGE_ON = 0x01,
+	PCHG_BIST_CMD_RF_CHARGE_OFF = 0x02,
+
+	/* Add no more entries below here. */
+	PCHG_BIST_CMD_NONE = 0xff
+};
+
+enum pchg_chipset_state {
+	PCHG_CHIPSET_STATE_ON = 0,
+	PCHG_CHIPSET_STATE_SUSPEND,
+	/* No more new entries below here */
+	PCHG_CHIPSET_STATE_COUNT
+};
+
+enum pchg_cfg {
+	/*
+	 * IRQ is not required for firmware update, update_open, update_write
+	 * and update_close may block and must return after completion.
+	 */
+	PCHG_CFG_FW_UPDATE_SYNC = BIT(0),
+};
+
+/**
+ * Data struct describing the configuration of a peripheral charging port.
+ */
+struct pchg_config {
+	/* Charger driver */
+	struct pchg_drv *drv;
+	/* I2C port number */
+	int i2c_port;
+	/* GPIO pin used for IRQ */
+	enum gpio_signal irq_pin;
+	/* Full battery percentage */
+	uint8_t full_percent;
+	/* Update block size */
+	uint32_t block_size;
+	/* RF charge duration in msec. Set it to 0 to disable RF charge. */
+	uint16_t rf_charge_msec;
+	enum pchg_cfg flags;
+};
+
+struct cps8x00_update {
+	/**
+	 * Command id needs to be increased by 1 and sent to chip together
+	 * with the command code.
+	 */
+	uint8_t cmd_id;
+	/* crc16 of the firmware */
+	uint16_t crc;
+	/* The firmware length which has been written to chip */
+	uint32_t firmware_len;
+};
+
+struct pchg_update {
+	/* Version of new firmware. Usually used by EC_PCHG_UPDATE_CMD_OPEN. */
+	uint32_t version;
+	/* CRC32 of new firmware. Usually used by EC_PCHG_UPDATE_CMD_CLOSE. */
+	uint32_t crc32;
+	/* Address which <data> will be written to. */
+	uint32_t addr;
+	/* Size of <data> */
+	uint32_t size;
+	/* 0: No data. 1: Data is ready for write. */
+	uint8_t data_ready;
+	/* Partial data of new firmware */
+	uint8_t data[128];
+	/* Driver data for firmware update */
+	union {
+		struct cps8x00_update cps8200_update;
+		/* other driver data follows in the future */
+	} driver_data;
+};
+
+struct pchg_policy_t {
+	uint32_t evt_mask;
+	uint32_t err_mask;
+};
+
+extern struct pchg_policy_t pchg_policy_on;
+extern struct pchg_policy_t pchg_policy_suspend;
+
+/**
+ * Data struct describing the status of a peripheral charging port. It provides
+ * the state machine and a charger driver with a context to work on.
+ */
+struct pchg {
+	/* Static configuration */
+	const struct pchg_config *const cfg;
+	/* Event & error report policy. */
+	struct pchg_policy_t *policy[PCHG_CHIPSET_STATE_COUNT];
+	/* Current state of the port */
+	enum pchg_state state;
+	/* Event queue */
+	struct queue const events;
+	/* Event queue mutex */
+	struct mutex mtx;
+	/* 1:Pending IRQ 0:No pending IRQ */
+	atomic_t irq;
+	/* Event currently being handled */
+	enum pchg_event event;
+	/* Error (enum pchg_error). Port is disabled until it's cleared. */
+	uint32_t error;
+	/* Battery percentage (0% ~ 100%) of the connected peripheral device */
+	uint8_t battery_percent;
+	/* Number of dropped events (due to queue overflow) */
+	uint32_t dropped_event_count;
+	/* Number of dropped host events (due to queue overflow) */
+	uint32_t dropped_host_event_count;
+	/* enum pchg_mode */
+	uint8_t mode;
+	/* enum pchg_bist_cmd */
+	uint8_t bist_cmd;
+	/* FW version */
+	uint32_t fw_version;
+	/* Context related to FW update */
+	struct pchg_update update;
+};
+
+/**
+ * Peripheral charger driver
+ *
+ * These functions shall return only communication errors (e.g. i2c error). If
+ * the error is internal to PCHG, they should return EC_SUCCESS and set
+ * ctx->event to PCHG_EVENT_ERROR and set a flag in ctx->error.
+ */
+struct pchg_drv {
+	/*
+	 * Reset charger chip. External reset (e.g by GPIO). No
+	 * communication or data access is expected (e.g. no I2C access).
+	 */
+	int (*reset)(struct pchg *ctx);
+	/*
+	 * Initialize the charger. Run setup needed only once per reset
+	 * (e.g. enable I2C, unlock I2C).
+	 */
+	int (*init)(struct pchg *ctx);
+	/* Enable/disable the charger. */
+	int (*enable)(struct pchg *ctx, bool enable);
+	/*
+	 * Get chip info, identify chip and setup function pointers
+	 * (e.g. I2C read function). It needs to work without IRQ.
+	 */
+	int (*get_chip_info)(struct pchg *ctx);
+	/* Get event info. */
+	int (*get_event)(struct pchg *ctx);
+	/* Get battery level. */
+	int (*get_soc)(struct pchg *ctx);
+	/* open update session */
+	int (*update_open)(struct pchg *ctx);
+	/* write update image */
+	int (*update_write)(struct pchg *ctx);
+	/* close update session */
+	int (*update_close)(struct pchg *ctx);
+	/* Toggle pass-through mode. */
+	int (*passthru)(struct pchg *ctx, bool enable);
+	/* Control BIST commands. */
+	int (*bist)(struct pchg *ctx, uint8_t test_id);
+};
+
+/**
+ * Array storing configs and states of all the peripheral charging ports.
+ * Should be defined in board.c.
+ */
+extern struct pchg pchgs[];
+
+/* Utility macro converting port config to port number. */
+#define PCHG_CTX_TO_PORT(ctx) ((ctx) - &pchgs[0])
+
+/**
+ * Interrupt handler for a peripheral charger.
+ *
+ * @param signal
+ */
+void pchg_irq(enum gpio_signal signal);
+
+/**
+ * Task running a state machine for charging peripheral devices.
+ */
+void pchg_task(void *u);
+
+/**
+ * Turn on/off power for a PCHG charger.
+ *
+ * @param port  Port number of the PCHG charger.
+ * @param on
+ */
+__override_proto void board_pchg_power_on(int port, bool on);
+
+/**
+ * Return counts for PCHG charger.
+ */
+int board_get_pchg_count(void);
+
+#endif /* __CROS_EC_PERIPHERAL_CHARGER_H */
diff --git a/include/physical_presence.h b/include/physical_presence.h
index 0acbc65691..4f93eaea62 100644
--- a/include/physical_presence.h
+++ b/include/physical_presence.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/include/port80.h b/include/port80.h
index e6212ab593..023b4e3841 100644
--- a/include/port80.h
+++ b/include/port80.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,9 +11,9 @@
 #include "common.h"
 
 enum port_80_event {
-	PORT_80_EVENT_RESUME = 0x1001,  /* S3->S0 transition */
-	PORT_80_EVENT_RESET = 0x1002,   /* RESET transition */
-	PORT_80_IGNORE = 0xffff,	/* Invalid POST CODE */
+	PORT_80_EVENT_RESUME = 0x1001, /* S3->S0 transition */
+	PORT_80_EVENT_RESET = 0x1002, /* RESET transition */
+	PORT_80_IGNORE = 0xffff, /* Invalid POST CODE */
 };
 
 /**
@@ -31,4 +31,20 @@ void port_80_write(int data);
  */
 int port_80_read(void);
 
-#endif  /* __CROS_EC_PORT80_H */
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+/**
+ * Get last boot code
+ *
+ * @return Last port 80 code from boot
+ */
+int port_80_last(void);
+
+/**
+ * return amd initialized check result
+ *
+ * @return 0: ddr detect; 1: ddr no detect.
+ */
+int amd_ddr_initialized_check(void);
+#endif
+
+#endif /* __CROS_EC_PORT80_H */
diff --git a/include/power.h b/include/power.h
index 4a267ed8ad..384eb0e906 100644
--- a/include/power.h
+++ b/include/power.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,32 +8,43 @@
 #ifndef __CROS_EC_POWER_H
 #define __CROS_EC_POWER_H
 
+#include "chipset.h"
 #include "common.h"
-#include "gpio.h"
+#include "compiler.h"
+#include "gpio_signal.h"
 #include "task_id.h"
 
-enum power_state {
+FORWARD_DECLARE_ENUM(power_state){
 	/* Steady states */
-	POWER_G3 = 0,	/*
-			 * System is off (not technically all the way into G3,
-			 * which means totally unpowered...)
-			 */
-	POWER_S5,		/* System is soft-off */
-	POWER_S3,		/* Suspend; RAM on, processor is asleep */
-	POWER_S0,		/* System is on */
+	POWER_G3 = 0, /*
+		       * System is off (not technically all the way into G3,
+		       * which means totally unpowered...)
+		       */
+	POWER_S5, /* System is soft-off */
+	POWER_S4, /* System is suspended to disk */
+	POWER_S3, /* Suspend; RAM on, processor is asleep */
+	POWER_S0, /* System is on */
 #ifdef CONFIG_POWER_S0IX
 	POWER_S0ix,
 #endif
 	/* Transitions */
-	POWER_G3S5,	/* G3 -> S5 (at system init time) */
-	POWER_S5S3,	/* S5 -> S3 */
-	POWER_S3S0,	/* S3 -> S0 */
-	POWER_S0S3,	/* S0 -> S3 */
-	POWER_S3S5,	/* S3 -> S5 */
-	POWER_S5G3,	/* S5 -> G3 */
+	POWER_G3S5, /* G3 -> S5 (at system init time) */
+	POWER_S5S3, /* S5 -> S3 (skips S4 on non-Intel systems) */
+	POWER_S3S0, /* S3 -> S0 */
+	POWER_S0S3, /* S0 -> S3 */
+	POWER_S3S5, /* S3 -> S5 (skips S4 on non-Intel systems) */
+	POWER_S5G3, /* S5 -> G3 */
+	POWER_S3S4, /* S3 -> S4 */
+	POWER_S4S3, /* S4 -> S3 */
+	POWER_S4S5, /* S4 -> S5 */
+	POWER_S5S4, /* S5 -> S4 */
 #ifdef CONFIG_POWER_S0IX
-	POWER_S0ixS0,   /* S0ix -> S0 */
-	POWER_S0S0ix,   /* S0 -> S0ix */
+	POWER_S0ixS0, /* S0ix -> S0 */
+	POWER_S0S0ix, /* S0 -> S0ix */
+#endif
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+	POWER_S0ixS3, /* S0ix -> S3 */
+	POWER_S3S0ix, /* S3 -> S0ix */
 #endif
 };
 
@@ -47,22 +58,26 @@ enum power_state {
  * +------------------------------------------------------+
  * |       1         |    Signal interrupt state at boot  |
  * +------------------------------------------------------+
- * |     2 : 32      |            Reserved                |
+ * |       2         |     Do not log the signal change   |
+ * +------------------------------------------------------+
+ * |     3 : 32      |            Reserved                |
  * +-----------------+------------------------------------+
  */
 
-#define POWER_SIGNAL_ACTIVE_STATE	BIT(0)
-#define POWER_SIGNAL_ACTIVE_LOW	(0 << 0)
-#define POWER_SIGNAL_ACTIVE_HIGH	BIT(0)
+#define POWER_SIGNAL_ACTIVE_STATE BIT(0)
+#define POWER_SIGNAL_ACTIVE_LOW (0 << 0)
+#define POWER_SIGNAL_ACTIVE_HIGH BIT(0)
+
+#define POWER_SIGNAL_INTR_STATE BIT(1)
+#define POWER_SIGNAL_DISABLE_AT_BOOT BIT(1)
 
-#define POWER_SIGNAL_INTR_STATE	BIT(1)
-#define POWER_SIGNAL_DISABLE_AT_BOOT	BIT(1)
+#define POWER_SIGNAL_NO_LOG BIT(2)
 
 /* Information on an power signal */
 struct power_signal_info {
-	enum gpio_signal gpio;	/* GPIO for signal */
-	uint32_t flags;		/* See POWER_SIGNAL_* macros */
-	const char *name;	/* Name of signal */
+	enum gpio_signal gpio; /* GPIO for signal */
+	uint32_t flags; /* See POWER_SIGNAL_* macros */
+	const char *name; /* Name of signal */
 };
 
 /*
@@ -95,7 +110,7 @@ int power_signal_is_asserted(const struct power_signal_info *s);
 /**
  * Get the level of provided input signal.
  */
-__overridable int power_signal_get_level(enum gpio_signal signal);
+__override_proto int power_signal_get_level(enum gpio_signal signal);
 
 /**
  * Enable interrupt for provided input signal.
@@ -154,7 +169,6 @@ int power_wait_signals_timeout(uint32_t want, int timeout);
  */
 int power_wait_mask_signals_timeout(uint32_t want, uint32_t mask, int timeout);
 
-
 /**
  * Set the low-level power chipset state.
  *
@@ -162,15 +176,23 @@ int power_wait_mask_signals_timeout(uint32_t want, uint32_t mask, int timeout);
  */
 void power_set_state(enum power_state new_state);
 
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+/**
+ * Reboot the ap if detect the system has hung
+ */
+void board_reboot_ap_on_g3(void);
+#endif
+
 /**
  * Set the low-level chipset power state.
  *
  * @return Current chipset power state
  */
-#ifdef HAS_TASK_CHIPSET
+#ifdef CONFIG_AP_POWER_CONTROL
 enum power_state power_get_state(void);
 #else
-static inline enum power_state power_get_state(void) {
+static inline enum power_state power_get_state(void)
+{
 	return POWER_G3;
 }
 #endif
@@ -198,11 +220,24 @@ enum power_state power_handle_state(enum power_state state);
 /**
  * Interrupt handler for power signal GPIOs.
  */
-#ifdef HAS_TASK_CHIPSET
+#ifdef CONFIG_AP_POWER_CONTROL
 void power_signal_interrupt(enum gpio_signal signal);
 #else
-static inline void power_signal_interrupt(enum gpio_signal signal) { }
-#endif /* !HAS_TASK_CHIPSET */
+static inline void power_signal_interrupt(enum gpio_signal signal)
+{
+}
+#endif /* !CONFIG_AP_POWER_CONTROL */
+
+/**
+ * Interrupt handler for pwrok signal. This interrupt handler should be used
+ * when there is a requirement to have minimum pass through delay between the
+ * pwrok coming to the EC and the pwrok that goes to the PCH for high->low
+ * transitions. Low->high transitions are still handled from within the chipset
+ * task power state machine.
+ *
+ * @param signal - The gpio signal that triggered the interrupt.
+ */
+void intel_x86_pwrok_signal_interrupt(enum gpio_signal signal);
 
 /**
  * Interrupt handler for rsmrst signal GPIO. This interrupt handler should be
@@ -247,7 +282,7 @@ void power_set_host_sleep_state(enum host_sleep_event state);
 /* Context to pass to a host sleep command handler. */
 struct host_sleep_event_context {
 	uint32_t sleep_transitions; /* Number of sleep transitions observed */
-	uint16_t sleep_timeout_ms;  /* Timeout in milliseconds */
+	uint16_t sleep_timeout_ms; /* Timeout in milliseconds */
 };
 
 /**
@@ -257,9 +292,9 @@ struct host_sleep_event_context {
  * @param state Current host sleep state updated by the host.
  * @param ctx Possible sleep parameters and return values, depending on state.
  */
-__override_proto void power_chipset_handle_host_sleep_event(
-		enum host_sleep_event state,
-		struct host_sleep_event_context *ctx);
+__override_proto void
+power_chipset_handle_host_sleep_event(enum host_sleep_event state,
+				      struct host_sleep_event_context *ctx);
 
 /**
  * Provide callback to allow board to take any action on host sleep event
@@ -267,8 +302,8 @@ __override_proto void power_chipset_handle_host_sleep_event(
  *
  * @param state Current host sleep state updated by the host.
  */
-__override_proto void power_board_handle_host_sleep_event(
-		enum host_sleep_event state);
+__override_proto void
+power_board_handle_host_sleep_event(enum host_sleep_event state);
 
 /*
  * This is the default state of host sleep event. Calls to
@@ -276,7 +311,7 @@ __override_proto void power_board_handle_host_sleep_event(
  * value. EC components listening to host sleep event updates can check for this
  * special value to know if the state was reset.
  */
-#define HOST_SLEEP_EVENT_DEFAULT_RESET		0
+#define HOST_SLEEP_EVENT_DEFAULT_RESET 0
 
 enum sleep_notify_type {
 	SLEEP_NOTIFY_NONE,
@@ -295,12 +330,12 @@ enum sleep_notify_type {
 void sleep_set_notify(enum sleep_notify_type notify);
 
 /**
- * Notify the given hook is the sleep notify is matched.
+ * Notify the given hook if the sleep notify is matched.
  *
  * @param check_state: The sleep notify to check.
  * @param hook_id: The hook to notify.
  */
-void sleep_notify_transition(int check_state, int hook_id);
+void sleep_notify_transition(enum sleep_notify_type check_state, int hook_id);
 
 /**
  * Called during the suspend transition, to increase the transition counter.
@@ -312,17 +347,55 @@ void sleep_suspend_transition(void);
  */
 void sleep_resume_transition(void);
 
+/**
+ * Type of sleep hang detected
+ */
+enum sleep_hang_type {
+	SLEEP_HANG_NONE,
+	SLEEP_HANG_S0IX_SUSPEND,
+	SLEEP_HANG_S0IX_RESUME
+};
+
+/**
+ * Provide callback to allow chipset to take action on host sleep hang
+ * detection.
+ *
+ * power_chipset_handle_sleep_hang will be called first.
+ * power_board_handle_sleep_hang will be called second.
+ *
+ * @param hang_type Host sleep hang type detected.
+ */
+__override_proto void
+power_chipset_handle_sleep_hang(enum sleep_hang_type hang_type);
+
+/**
+ * Provide callback to allow board to take action on host sleep hang
+ * detection.
+ *
+ * power_chipset_handle_sleep_hang will be called first.
+ * power_board_handle_sleep_hang will be called second.
+ *
+ * @param hang_type Host sleep hang type detected.
+ */
+__override_proto void
+power_board_handle_sleep_hang(enum sleep_hang_type hang_type);
+
 /**
  * Start the suspend process.
  *
  * It is called in power_chipset_handle_host_sleep_event(), after it receives
  * a host sleep event to hint that the suspend process starts.
  *
+ * power_chipset_handle_sleep_hang() and power_board_handle_sleep_hang() will
+ * be called when a sleep hang is detected.
+ *
+ * If called with a sleep_timeout_ms of EC_HOST_SLEEP_TIMEOUT_DEFAULT, the
+ * timeout will be picked based on CONFIG_SLEEP_TIMEOUT_MS or whatever is set as
+ * the default timeout by the sleeptimeout console command.
+ *
  * @param ctx Possible sleep parameters and return values, depending on state.
- * @param callback Will be called if timed out, i.e. suspend hang.
  */
-void sleep_start_suspend(struct host_sleep_event_context *ctx,
-			 void (*callback)(void));
+void sleep_start_suspend(struct host_sleep_event_context *ctx);
 
 /**
  * Complete the resume process.
@@ -349,6 +422,11 @@ void power_reset_host_sleep_state(void);
 #endif /* CONFIG_POWER_S0IX */
 #endif /* CONFIG_POWER_TRACK_HOST_SLEEP_STATE */
 
+#if defined(CONFIG_AP_PWRSEQ_S0IX_COUNTER) || \
+	defined(CONFIG_POWERSEQ_S0IX_COUNTER)
+extern atomic_t s0ix_counter;
+#endif
+
 /**
  * Board specific implementation to enable/disable the PP5000 rail.
  *
@@ -373,4 +451,31 @@ __override_proto void board_power_5v_enable(int enable);
  */
 void power_5v_enable(task_id_t tid, int enable);
 
-#endif  /* __CROS_EC_POWER_H */
+#ifdef CONFIG_ZTEST
+/**
+ * @brief Perform one state transition with power_common_state() as
+ * chipset_task() would.
+ */
+void test_power_common_state(void);
+#endif
+
+#ifdef CONFIG_POWERSEQ_FAKE_CONTROL
+/**
+ * Enable a fake S0 state
+ *
+ * Set whatever GPIOs or other parameters are required to get the system into a
+ * fake S0 state.  This allows for the S0 power state to be tested before an SoC
+ * is available for the board.
+ */
+void power_fake_s0(void);
+
+/**
+ * Disable any fake power state
+ *
+ * Undo any actions which were taken to force another power state and return
+ * GPIOs and other parameters to their default state.
+ */
+void power_fake_disable(void);
+#endif /* defined(CONFIG_POWER_FAKE_CONTROL) */
+
+#endif /* __CROS_EC_POWER_H */
diff --git a/include/power/alderlake_slg4bd44540.h b/include/power/alderlake_slg4bd44540.h
new file mode 100644
index 0000000000..20a85053fd
--- /dev/null
+++ b/include/power/alderlake_slg4bd44540.h
@@ -0,0 +1,47 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Alder Lake chipset power control module using the SLG4BD44540 power
+ * sequencer chip for Chrome EC
+ */
+
+#ifndef __CROS_EC_ALDERLAKE_SLG4BD44540_H
+#define __CROS_EC_ALDERLAKE_SLG4BD44540_H
+
+/* Input state flags. */
+#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
+#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED)
+#define IN_PCH_SLP_SUS_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_SUS_DEASSERTED)
+
+#define IN_ALL_PM_SLP_DEASSERTED                               \
+	(IN_PCH_SLP_S3_DEASSERTED | IN_PCH_SLP_S4_DEASSERTED | \
+	 IN_PCH_SLP_SUS_DEASSERTED)
+
+#define IN_PGOOD_ALL_CORE POWER_SIGNAL_MASK(X86_DSW_DPWROK)
+
+#define IN_ALL_S0 (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED)
+
+#define CHIPSET_G3S5_POWERUP_SIGNAL IN_PCH_SLP_SUS_DEASSERTED
+
+#define CHARGER_INITIALIZED_DELAY_MS 100
+#define CHARGER_INITIALIZED_TRIES 40
+
+/* Power signals list */
+enum power_signal {
+	X86_SLP_S0_DEASSERTED,
+	X86_SLP_S3_DEASSERTED,
+	X86_SLP_S4_DEASSERTED,
+	X86_SLP_S5_DEASSERTED,
+	X86_SLP_SUS_DEASSERTED,
+	X86_RSMRST_L_PGOOD,
+	X86_DSW_DPWROK,
+	X86_ALL_SYS_PGOOD,
+
+	/* Number of X86 signals */
+	POWER_SIGNAL_COUNT
+};
+
+#endif /* __CROS_EC_ALDERLAKE_SLG4BD44540_H */
diff --git a/include/power/amd_x86.h b/include/power/amd_x86.h
new file mode 100644
index 0000000000..57011d97df
--- /dev/null
+++ b/include/power/amd_x86.h
@@ -0,0 +1,29 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_POWER_AMD_X86_H_
+#define __CROS_EC_POWER_AMD_X86_H_
+
+/*
+ * In legacy EC-OS, the power signals are defined as part of
+ * the board include headers, but with Zephyr, this is common.
+ */
+#if defined(CONFIG_ZEPHYR) && defined(CONFIG_AP_X86_AMD)
+
+/* Power input signals */
+enum power_signal {
+	X86_SLP_S3_N, /* SOC  -> SLP_S3_L */
+	X86_SLP_S5_N, /* SOC  -> SLP_S5_L */
+
+	X86_S0_PGOOD, /* PMIC -> S0_PWROK_OD */
+	X86_S5_PGOOD, /* PMIC -> S5_PWROK */
+
+	/* Number of X86 signals */
+	POWER_SIGNAL_COUNT,
+};
+
+#endif
+
+#endif /* __CROS_EC_POWER_AMD_X86_H_ */
diff --git a/include/power/apollolake.h b/include/power/apollolake.h
new file mode 100644
index 0000000000..d0931a6b84
--- /dev/null
+++ b/include/power/apollolake.h
@@ -0,0 +1,51 @@
+/* Copyright 2016 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Apollolake chipset power control module for Chrome EC */
+
+#ifndef __CROS_EC_APOLLOLAKE_H
+#define __CROS_EC_APOLLOLAKE_H
+
+/*
+ * Input state flags.
+ * TODO: Normalize the power signal masks from board defines to SoC headers.
+ */
+#define IN_RSMRST_N POWER_SIGNAL_MASK(X86_RSMRST_N)
+#define IN_ALL_SYS_PG POWER_SIGNAL_MASK(X86_ALL_SYS_PG)
+#define IN_SLP_S3_N POWER_SIGNAL_MASK(X86_SLP_S3_N)
+#define IN_SLP_S4_N POWER_SIGNAL_MASK(X86_SLP_S4_N)
+#define IN_PCH_SLP_S4_DEASSERTED IN_SLP_S4_N
+#define IN_SUSPWRDNACK POWER_SIGNAL_MASK(X86_SUSPWRDNACK)
+#define IN_SUS_STAT_N POWER_SIGNAL_MASK(X86_SUS_STAT_N)
+
+#define IN_ALL_PM_SLP_DEASSERTED (IN_SLP_S3_N | IN_SLP_S4_N)
+
+#define IN_PGOOD_ALL_CORE (IN_RSMRST_N)
+
+#define IN_ALL_S0 (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED)
+
+#define CHIPSET_G3S5_POWERUP_SIGNAL IN_PGOOD_ALL_CORE
+
+#define CHARGER_INITIALIZED_DELAY_MS 100
+#define CHARGER_INITIALIZED_TRIES 40
+
+enum power_signal {
+#ifdef CONFIG_POWER_S0IX
+	X86_SLP_S0_N, /* PCH  -> SLP_S0_L */
+#endif
+	X86_SLP_S3_N, /* PCH  -> SLP_S3_L */
+	X86_SLP_S4_N, /* PCH  -> SLP_S4_L */
+	X86_SUSPWRDNACK, /* PCH  -> SUSPWRDNACK */
+
+	X86_ALL_SYS_PG, /* PMIC -> PMIC_EC_PWROK_OD */
+	X86_RSMRST_N, /* PMIC -> PMIC_EC_RSMRST_ODL */
+	X86_PGOOD_PP3300, /* PMIC -> PP3300_PG_OD */
+	X86_PGOOD_PP5000, /* PMIC -> PP5000_PG_OD */
+
+	/* Number of X86 signals */
+	POWER_SIGNAL_COUNT
+};
+
+#endif /* __CROS_EC_APOLLOLAKE_H */
diff --git a/include/power/cannonlake.h b/include/power/cannonlake.h
new file mode 100644
index 0000000000..53e9ba2325
--- /dev/null
+++ b/include/power/cannonlake.h
@@ -0,0 +1,31 @@
+/* Copyright 2017 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Cannonlake chipset power control module for Chrome EC */
+
+#ifndef __CROS_EC_CANNONLAKE_H
+#define __CROS_EC_CANNONLAKE_H
+
+/* Input state flags. */
+#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
+#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED)
+#define IN_PCH_SLP_SUS_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_SUS_DEASSERTED)
+
+#define IN_ALL_PM_SLP_DEASSERTED                               \
+	(IN_PCH_SLP_S3_DEASSERTED | IN_PCH_SLP_S4_DEASSERTED | \
+	 IN_PCH_SLP_SUS_DEASSERTED)
+
+#define IN_PGOOD_ALL_CORE POWER_SIGNAL_MASK(X86_PMIC_DPWROK)
+
+#define IN_ALL_S0                                       \
+	(IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED | \
+	 PP5000_PGOOD_POWER_SIGNAL_MASK)
+
+#define CHIPSET_G3S5_POWERUP_SIGNAL IN_PCH_SLP_SUS_DEASSERTED
+
+#define CHARGER_INITIALIZED_DELAY_MS 100
+#define CHARGER_INITIALIZED_TRIES 40
+
+#endif /* __CROS_EC_CANNONLAKE_H */
diff --git a/power/cometlake-discrete.h b/include/power/cometlake-discrete.h
similarity index 98%
rename from power/cometlake-discrete.h
rename to include/power/cometlake-discrete.h
index 6f5370beee..430cb02dce 100644
--- a/power/cometlake-discrete.h
+++ b/include/power/cometlake-discrete.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,7 +9,7 @@
  */
 
 #ifndef __CROS_EC_COMETLAKE_DISCRETE_H
-#define __CROS_EC_COMETLATE_DISCRETE_H
+#define __CROS_EC_COMETLAKE_DISCRETE_H
 
 /* Input state flags. */
 #define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
diff --git a/include/power/cometlake.h b/include/power/cometlake.h
new file mode 100644
index 0000000000..405fe7f0d7
--- /dev/null
+++ b/include/power/cometlake.h
@@ -0,0 +1,47 @@
+/* Copyright 2019 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Cometlake chipset power control module for Chrome EC */
+
+#ifndef __CROS_EC_COMETLAKE_H
+#define __CROS_EC_COMETLAKE_H
+
+/* Input state flags. */
+#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
+#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED)
+
+#define IN_ALL_PM_SLP_DEASSERTED \
+	(IN_PCH_SLP_S3_DEASSERTED | IN_PCH_SLP_S4_DEASSERTED)
+
+#define IN_PGOOD_ALL_CORE POWER_SIGNAL_MASK(X86_RSMRST_L_PGOOD)
+
+#define IN_ALL_S0                                       \
+	(IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED | \
+	 PP5000_PGOOD_POWER_SIGNAL_MASK)
+
+#define CHIPSET_G3S5_POWERUP_SIGNAL              \
+	(POWER_SIGNAL_MASK(X86_RSMRST_L_PGOOD) | \
+	 POWER_SIGNAL_MASK(X86_PP5000_A_PGOOD))
+
+#define CHARGER_INITIALIZED_DELAY_MS 100
+#define CHARGER_INITIALIZED_TRIES 40
+
+/* Power signals list */
+enum power_signal {
+	X86_SLP_S0_DEASSERTED,
+	X86_SLP_S3_DEASSERTED,
+	X86_SLP_S4_DEASSERTED,
+	X86_RSMRST_L_PGOOD,
+	X86_PP5000_A_PGOOD,
+	X86_ALL_SYS_PGOOD,
+
+	/* Number of X86 signals */
+	POWER_SIGNAL_COUNT
+};
+
+void all_sys_pgood_check_reboot(void);
+__override_proto void board_chipset_forced_shutdown(void);
+
+#endif /* __CROS_EC_COMETLAKE_H */
diff --git a/include/power/falconlite.h b/include/power/falconlite.h
new file mode 100644
index 0000000000..6afbbfbb94
--- /dev/null
+++ b/include/power/falconlite.h
@@ -0,0 +1,21 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_POWER_FALCONLITE_H_
+#define __CROS_EC_POWER_FALCONLITE_H_
+
+enum power_signal_falconlite {
+	FCL_AP_WARM_RST_REQ,
+	FCL_AP_SHUTDOWN_REQ,
+	FCL_AP_WATCHDOG,
+	FCL_PG_S5,
+	FCL_PG_VDD1_VDD2,
+	FCL_PG_VDD_MEDIA_ML,
+	FCL_PG_VDD_SOC,
+	FCL_PG_VDD_DDR_OD,
+	POWER_SIGNAL_COUNT,
+};
+
+#endif /* __CROS_EC_POWER_FALCONLITE_H_ */
diff --git a/power/icelake.h b/include/power/icelake.h
similarity index 85%
rename from power/icelake.h
rename to include/power/icelake.h
index 08c14718ec..6a08efbb42 100644
--- a/power/icelake.h
+++ b/include/power/icelake.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,13 +11,13 @@
 #include "stdbool.h"
 
 /* Input state flags. */
-#define IN_PCH_SLP_S3_DEASSERTED  POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
-#define IN_PCH_SLP_S4_DEASSERTED  POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED)
+#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
+#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED)
 #define IN_PCH_SLP_SUS_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_SUS_DEASSERTED)
 
-#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3_DEASSERTED | \
-				  IN_PCH_SLP_S4_DEASSERTED | \
-				  IN_PCH_SLP_SUS_DEASSERTED)
+#define IN_ALL_PM_SLP_DEASSERTED                               \
+	(IN_PCH_SLP_S3_DEASSERTED | IN_PCH_SLP_S4_DEASSERTED | \
+	 IN_PCH_SLP_SUS_DEASSERTED)
 
 #define IN_PGOOD_ALL_CORE POWER_SIGNAL_MASK(X86_DSW_DPWROK)
 
@@ -33,6 +33,7 @@ enum power_signal {
 	X86_SLP_S0_DEASSERTED,
 	X86_SLP_S3_DEASSERTED,
 	X86_SLP_S4_DEASSERTED,
+	X86_SLP_S5_DEASSERTED,
 	X86_SLP_SUS_DEASSERTED,
 	X86_RSMRST_L_PGOOD,
 	X86_DSW_DPWROK,
diff --git a/power/intel_x86.h b/include/power/intel_x86.h
similarity index 77%
rename from power/intel_x86.h
rename to include/power/intel_x86.h
index d50d6a75da..9001cf8d49 100644
--- a/power/intel_x86.h
+++ b/include/power/intel_x86.h
@@ -1,11 +1,10 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Intel X86 chipset power control module for Chrome EC */
 
-
 #ifndef __CROS_EC_INTEL_X86_H
 #define __CROS_EC_INTEL_X86_H
 
@@ -13,8 +12,10 @@
 #include "power.h"
 
 /* Chipset specific header files */
+#if defined(CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540)
+#include "alderlake_slg4bd44540.h"
 /* Geminilake and apollolake use same power sequencing. */
-#ifdef CONFIG_CHIPSET_APL_GLK
+#elif defined(CONFIG_CHIPSET_APL_GLK)
 #include "apollolake.h"
 #elif defined(CONFIG_CHIPSET_CANNONLAKE)
 #include "cannonlake.h"
@@ -24,21 +25,34 @@
 #include "cometlake-discrete.h"
 #elif defined(CONFIG_CHIPSET_ICELAKE)
 #include "icelake.h"
+#elif defined(CONFIG_CHIPSET_METEORLAKE)
+#include "meteorlake.h"
 #elif defined(CONFIG_CHIPSET_SKYLAKE)
 #include "skylake.h"
 #endif
 
 /* GPIO for power signal */
-#ifdef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifdef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 #define SLP_S3_SIGNAL_L VW_SLP_S3_L
 #else
 #define SLP_S3_SIGNAL_L GPIO_PCH_SLP_S3_L
 #endif
-#ifdef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#ifdef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 #define SLP_S4_SIGNAL_L VW_SLP_S4_L
 #else
 #define SLP_S4_SIGNAL_L GPIO_PCH_SLP_S4_L
 #endif
+/*
+ * The SLP_S5 signal has not traditionally been connected to the EC. If virtual
+ * wire support is enabled, then SLP_S5 will be available that way. Otherwise,
+ * use SLP_S4's GPIO as a proxy for SLP_S5. This matches old behavior and
+ * effectively prevents S4 residency.
+ */
+#ifdef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S5
+#define SLP_S5_SIGNAL_L VW_SLP_S5_L
+#else
+#define SLP_S5_SIGNAL_L SLP_S4_SIGNAL_L
+#endif
 
 /**
  * Handle RSMRST signal.
diff --git a/include/power/meteorlake.h b/include/power/meteorlake.h
new file mode 100644
index 0000000000..aedf9824fc
--- /dev/null
+++ b/include/power/meteorlake.h
@@ -0,0 +1,76 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Meteorlake chipset power control module for Chrome EC */
+
+#ifndef __CROS_EC_METEORLAKE_H
+#define __CROS_EC_METEORLAKE_H
+
+#include "stdbool.h"
+
+/* Input state flags. */
+#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
+#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED)
+
+#define IN_ALL_PM_SLP_DEASSERTED \
+	(IN_PCH_SLP_S3_DEASSERTED | IN_PCH_SLP_S4_DEASSERTED)
+
+#define IN_PGOOD_ALL_CORE POWER_SIGNAL_MASK(X86_RSMRST_L_PGOOD)
+
+#define IN_ALL_S0 (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED)
+
+#define CHIPSET_G3S5_POWERUP_SIGNAL POWER_SIGNAL_MASK(X86_RSMRST_L_PGOOD)
+
+#define CHARGER_INITIALIZED_DELAY_MS 100
+#define CHARGER_INITIALIZED_TRIES 40
+
+/* Power signals list */
+enum power_signal {
+	X86_SLP_S0_DEASSERTED,
+	X86_SLP_S3_DEASSERTED,
+	X86_SLP_S4_DEASSERTED,
+	X86_SLP_S5_DEASSERTED,
+	X86_RSMRST_L_PGOOD,
+	X86_ALL_SYS_PGOOD,
+
+	/* Number of X86 signals */
+	POWER_SIGNAL_COUNT
+};
+
+struct intel_x86_pwrok_signal {
+	enum gpio_signal gpio;
+	bool active_low;
+	int delay_ms;
+};
+
+/*
+ * Meteorlake Generic Power delivery implementation
+ * - IMVP provides following power rails
+ *   VccCORE
+ *   VccSA
+ *   VccGT
+ * - Platform logic provides following signals
+ *   SYS_PWROK
+ *   SYS_PWROK
+ *
+ * ALL_SYS_PWRGD is generated by the combination of below signals
+ *   SLP_S4# -> VDD2_VR_PG
+ *   RSMRST#
+ *   SLP_S3#
+ *   SLP_S3# -> S0_VR_PG
+ * ALL_SYS_PWRGD can be implemented as a single GPIO if the platform power logic
+ * combines the above power good signals. Otherwise your board can override
+ * intel_x86_get_pg_ec_all_sys_pwrgd() to check multiple power good signals.
+ *
+ * PLT_PWROK is generated by the combination of below signals
+ *   ALL_SYS_PWRGD
+ *   IMVP_VR_READY
+ */
+extern const struct intel_x86_pwrok_signal pwrok_signal_assert_list[];
+extern const int pwrok_signal_assert_count;
+extern const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[];
+extern const int pwrok_signal_deassert_count;
+
+#endif /* __CROS_EC_METEORLAKE_H */
diff --git a/include/power/mt8186.h b/include/power/mt8186.h
new file mode 100644
index 0000000000..92eb42eff2
--- /dev/null
+++ b/include/power/mt8186.h
@@ -0,0 +1,17 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_POWER_MT8186_H_
+#define __CROS_EC_POWER_MT8186_H_
+
+enum power_signal {
+	AP_IN_RST,
+	AP_IN_S3,
+	AP_WDT_ASSERTED,
+	AP_WARM_RST_REQ,
+	POWER_SIGNAL_COUNT,
+};
+
+#endif /* __CROS_EC_POWER_MT8186_H_ */
diff --git a/include/power/mt8192.h b/include/power/mt8192.h
new file mode 100644
index 0000000000..19f5ce081d
--- /dev/null
+++ b/include/power/mt8192.h
@@ -0,0 +1,20 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_POWER_MT8192_H_
+#define __CROS_EC_POWER_MT8192_H_
+
+#ifndef CONFIG_ZEPHYR
+
+enum power_signal {
+	PMIC_PWR_GOOD,
+	AP_IN_S3_L,
+	AP_WDT_ASSERTED,
+	POWER_SIGNAL_COUNT,
+};
+
+#endif /* !CONFIG_ZEPHYR */
+
+#endif /* __CROS_EC_POWER_MT8192_H_ */
diff --git a/include/power/qcom.h b/include/power/qcom.h
new file mode 100644
index 0000000000..ccf61ab4a5
--- /dev/null
+++ b/include/power/qcom.h
@@ -0,0 +1,28 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_POWER_QCOM_H_
+#define __CROS_EC_POWER_QCOM_H_
+
+#if defined(CONFIG_CHIPSET_SC7180) || defined(CONFIG_CHIPSET_SC7280)
+enum power_signal {
+	SC7X80_AP_RST_ASSERTED = 0,
+	SC7X80_PS_HOLD,
+	SC7X80_POWER_GOOD,
+	SC7X80_AP_SUSPEND,
+#ifdef CONFIG_CHIPSET_SC7180
+	SC7X80_WARM_RESET,
+	SC7X80_DEPRECATED_AP_RST_REQ,
+#endif
+	POWER_SIGNAL_COUNT,
+};
+#endif
+
+/* Swithcap functions */
+void board_set_switchcap_power(int enable);
+int board_is_switchcap_enabled(void);
+int board_is_switchcap_power_good(void);
+
+#endif /* __CROS_EC_POWER_QCOM_H_ */
diff --git a/power/skylake.h b/include/power/skylake.h
similarity index 78%
rename from power/skylake.h
rename to include/power/skylake.h
index c8a656c6c5..4da8ae9ea3 100644
--- a/power/skylake.h
+++ b/include/power/skylake.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,13 +12,13 @@
  * Input state flags.
  * TODO: Normalize the power signal masks from board defines to SoC headers.
  */
-#define IN_PCH_SLP_S3_DEASSERTED  POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
-#define IN_PCH_SLP_S4_DEASSERTED  POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED)
+#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
+#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED)
 #define IN_PCH_SLP_SUS_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_SUS_DEASSERTED)
 
-#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3_DEASSERTED | \
-				  IN_PCH_SLP_S4_DEASSERTED | \
-				  IN_PCH_SLP_SUS_DEASSERTED)
+#define IN_ALL_PM_SLP_DEASSERTED                               \
+	(IN_PCH_SLP_S3_DEASSERTED | IN_PCH_SLP_S4_DEASSERTED | \
+	 IN_PCH_SLP_SUS_DEASSERTED)
 
 /*
  * DPWROK is NC / stuffing option on initial boards.
diff --git a/include/power_button.h b/include/power_button.h
index 167ca21e2b..9ff85abe7f 100644
--- a/include/power_button.h
+++ b/include/power_button.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -69,4 +69,11 @@ int64_t get_time_dsw_pwrok(void);
  */
 void board_pwrbtn_to_pch(int level);
 
-#endif  /* __CROS_EC_POWER_BUTTON_H */
+/**
+ * Simulates a power button press.
+ *
+ * @param duration	Simulated power button press duration in ms.
+ */
+void power_button_simulate_press(unsigned int duration);
+
+#endif /* __CROS_EC_POWER_BUTTON_H */
diff --git a/include/power_led.h b/include/power_led.h
index 05ea7ead3c..d488406cac 100644
--- a/include/power_led.h
+++ b/include/power_led.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -28,7 +28,9 @@ void powerled_set_state(enum powerled_state state);
 
 #else
 
-static inline void powerled_set_state(enum powerled_state state) {}
+static inline void powerled_set_state(enum powerled_state state)
+{
+}
 
 #endif
 
diff --git a/include/printf.h b/include/printf.h
index 91c17b428b..a06d8e1c7b 100644
--- a/include/printf.h
+++ b/include/printf.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,8 +8,18 @@
 #ifndef __CROS_EC_PRINTF_H
 #define __CROS_EC_PRINTF_H
 
-#include <stdarg.h>  /* For va_list */
 #include "common.h"
+#include "console.h"
+
+#include <stdarg.h> /* For va_list */
+#include <stdbool.h>
+#include <stddef.h> /* For size_t */
+#include <stdio.h>
+
+/**
+ * Buffer size in bytes large enough to hold the largest possible timestamp.
+ */
+#define PRINTF_TIMESTAMP_BUF_SIZE 22
 
 /*
  * Printf formatting: % [flags] [width] [.precision] [length] [type]
@@ -43,23 +53,14 @@
  *   - 'c' - character
  *   - 's' - null-terminated ASCII string
  *   - 'd' - signed integer
- *   - 'i' - signed integer if CONFIG_PRINTF_LEGACY_LI_FORMAT is set (ignore l)
+ *   - 'i' - signed integer (if CONFIG_PRINTF_LONG_IS_32BITS is enabled)
  *   - 'u' - unsigned integer
  *   - 'x' - unsigned integer, print as lower-case hexadecimal
  *   - 'X' - unsigned integer, print as upper-case hexadecimal
  *   - 'b' - unsigned integer, print as binary
- *
- * Special format codes:
- *   - '%ph' - binary data, print as hex; Use HEX_BUF(buffer, size) to encode
- *             parameters.
- *   - '%pP' - raw pointer.
- *   - "%pT" - current time in seconds - interpreted as "%.6T" for precision.
- *           Supply PRINTF_TIMESTAMP_NOW to use the current time, or supply a
- *           pointer to a 64-bit timestamp to print.
+ *   - 'p' - pointer
  */
 
-#ifndef HIDE_EC_STDLIB
-
 /**
  * Print formatted output to a function, like vfprintf()
  *
@@ -76,34 +77,78 @@
 __stdlib_compat int vfnprintf(int (*addchar)(void *context, int c),
 			      void *context, const char *format, va_list args);
 
+#ifdef TEST_BUILD
 /**
- * Print formatted outut to a string.
+ * Converts @val to a string written in @buf. The value is converted from
+ * least-significant digit to most-significant digit, so the pointer returned
+ * does not necessarily point to the start of @buf.
  *
- * Guarantees null-termination if size!=0.
+ * This function shouldn't be used directly; it's a helper function for other
+ * printf functions and only exposed for testing.
  *
- * @param str		Destination string
- * @param size		Size of destination in bytes
- * @param format	Format string
- * @return EC_SUCCESS, or EC_ERROR_OVERFLOW if the output was truncated.
+ * @param[out] buf Destination buffer
+ * @param[in] buf_len Length of @buf in bytes
+ * @param[in] val Value to convert
+ * @param[in] precision Fixed point precision; -1 disables fixed point
+ * @param[in] base Base
+ * @param[in] uppercase true to print hex characters uppercase
+ * @return pointer to start of string on success (not necessarily the start of
+ * @buf).
+ * @return NULL on error
  */
-__attribute__((__format__(__printf__, 3, 4)))
-__stdlib_compat int snprintf(char *str, int size, const char *format, ...);
+char *uint64_to_str(char *buf, int buf_len, uint64_t val, int precision,
+		    int base, bool uppercase);
+#endif /* TEST_BUILD */
 
 /**
- * Print formatted output to a string.
+ * Print timestamp as string to the provided buffer.
  *
- * Guarantees null-termination if size!=0.
+ * Guarantees NUL-termination if size != 0.
  *
- * @param str		Destination string
- * @param size		Size of destination in bytes
- * @param format	Format string
- * @param args		Parameters
- * @return The string length written to str, or a negative value on error.
- *         The negative values can be -EC_ERROR_INVAL or -EC_ERROR_OVERFLOW.
+ * @param[out] str Destination string
+ * @param[in] size Size of @str in bytes
+ * @param[in] timestamp Timestamp
+ * @return Length of string written to @str, not including terminating NUL.
+ * @return -EC_ERROR_OVERFLOW when @str buffer is not large enough. @str[0]
+ * is set to '\0'.
+ * @return -EC_ERROR_INVAL when @size is 0.
+ */
+int snprintf_timestamp(char *str, size_t size, uint64_t timestamp);
+
+/**
+ * Print the current time as a string to the provided buffer.
+ *
+ * Guarantees NUL-termination if size != 0.
+ *
+ * @param[out] str Destination string
+ * @param[in] size Size of @str in bytes
+ * @return Length of string written to @str, not including terminating NUL.
+ * @return -EC_ERROR_OVERFLOW when @str buffer is not large enough. @str[0]
+ * is set to '\0'.
+ * @return -EC_ERROR_INVAL when @size is 0.
+ */
+int snprintf_timestamp_now(char *str, size_t size);
+
+/**
+ * Prints bytes as a hex string in the provided buffer.
+ *
+ * Guarantees NUL-termination if size != 0.
+ *
+ * @param[out] str Destination string
+ * @param[in] size Size of @str in bytes
+ * @param[in] params Data to print
+ * @return Length of string written to @str, not including terminating NUL.
+ * @return -EC_ERROR_OVERFLOW when @str buffer is not large enough.
+ * @return -EC_ERROR_INVAL when @size is 0.
  */
-__stdlib_compat int vsnprintf(char *str, int size, const char *format,
-			      va_list args);
+int snprintf_hex_buffer(char *str, size_t size,
+			const struct hex_buffer_params *params);
 
-#endif  /* !HIDE_EC_STDLIB */
+/**
+ * @param[in] num_bytes
+ * @return number of bytes needed to store @num_bytes as a string (including
+ * terminating '\0').
+ */
+size_t hex_str_buf_size(size_t num_bytes);
 
-#endif  /* __CROS_EC_PRINTF_H */
+#endif /* __CROS_EC_PRINTF_H */
diff --git a/include/producer.h b/include/producer.h
index b6a04883d6..81ef93ecf9 100644
--- a/include/producer.h
+++ b/include/producer.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/include/pwm.h b/include/pwm.h
index 401d3dc0ec..b56f9f8c1a 100644
--- a/include/pwm.h
+++ b/include/pwm.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,6 +6,13 @@
 #ifndef __CROS_EC_PWM_H
 #define __CROS_EC_PWM_H
 
+#include "util.h"
+
+#include <inttypes.h>
+
+#define PWM_RAW_TO_PERCENT(v) DIV_ROUND_NEAREST((uint32_t)(v)*100, UINT16_MAX)
+#define PWM_PERCENT_TO_RAW(v) ((uint32_t)(v)*UINT16_MAX / 100)
+
 /* The values are defined in board.h */
 enum pwm_channel;
 
@@ -39,34 +46,33 @@ void pwm_set_duty(enum pwm_channel ch, int percent);
  */
 int pwm_get_duty(enum pwm_channel ch);
 
-
 /* Flags for PWM config table */
 
 /**
  * PWM output signal is inverted, so 100% duty means always low
  */
-#define PWM_CONFIG_ACTIVE_LOW		BIT(0)
+#define PWM_CONFIG_ACTIVE_LOW BIT(0)
 /**
  * PWM channel has a fan controller with a tach input and can auto-adjust
  * its duty cycle to produce a given fan RPM.
  */
-#define PWM_CONFIG_HAS_RPM_MODE		BIT(1)
+#define PWM_CONFIG_HAS_RPM_MODE BIT(1)
 /**
  * PWM clock select alternate source.  The actual clock and alternate
  * source are chip dependent.
  */
-#define PWM_CONFIG_ALT_CLOCK		BIT(2)
+#define PWM_CONFIG_ALT_CLOCK BIT(2)
 /**
  * PWM channel has a complementary output signal which should be enabled in
  * addition to the primary output.
  */
-#define PWM_CONFIG_COMPLEMENTARY_OUTPUT	BIT(3)
+#define PWM_CONFIG_COMPLEMENTARY_OUTPUT BIT(3)
 /**
  * PWM channel must stay active in low-power idle, if enabled.
  */
-#define PWM_CONFIG_DSLEEP		BIT(4)
+#define PWM_CONFIG_DSLEEP BIT(4)
 /**
  * PWM channel's IO type is open-drain, if enabled. (default IO is push-pull.)
  */
-#define PWM_CONFIG_OPEN_DRAIN		BIT(5)
-#endif  /* __CROS_EC_PWM_H */
+#define PWM_CONFIG_OPEN_DRAIN BIT(5)
+#endif /* __CROS_EC_PWM_H */
diff --git a/include/pwr_defs.h b/include/pwr_defs.h
new file mode 100644
index 0000000000..499a5b00e4
--- /dev/null
+++ b/include/pwr_defs.h
@@ -0,0 +1,25 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_PWR_DEFS_H
+#define __CROS_EC_PWR_DEFS_H
+
+#include "system.h"
+
+struct pwr_con_t {
+	uint16_t volts;
+	uint16_t milli_amps;
+};
+
+/*
+ * Return power (in milliwatts) corresponding to input power connection
+ * struct entry.
+ */
+inline int pwr_con_to_milliwatts(struct pwr_con_t *pwr)
+{
+	return (pwr->volts * pwr->milli_amps);
+}
+
+#endif
diff --git a/include/queue.h b/include/queue.h
index 6cf72563cb..6e7d4abbf8 100644
--- a/include/queue.h
+++ b/include/queue.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -75,9 +75,9 @@ struct queue {
 
 	struct queue_policy const *policy;
 
-	size_t  buffer_units; /* size of buffer (in units) */
-	size_t  buffer_units_mask; /* size of buffer (in units) - 1*/
-	size_t  unit_bytes;   /* size of unit   (in byte) */
+	size_t buffer_units; /* size of buffer (in units) */
+	size_t buffer_units_mask; /* size of buffer (in units) - 1*/
+	size_t unit_bytes; /* size of unit   (in byte) */
 	uint8_t *buffer;
 };
 
@@ -86,14 +86,14 @@ struct queue {
  * and state structure.  This macro creates a compound literal that can be used
  * to statically initialize a queue.
  */
-#define QUEUE(SIZE, TYPE, POLICY)				\
-	((struct queue) {					\
-		.state        = &((struct queue_state){}),	\
-		.policy       = &POLICY,			\
+#define QUEUE(SIZE, TYPE, POLICY)                                             \
+	((struct queue){                                                      \
+		.state = &((struct queue_state){}),                           \
+		.policy = &POLICY,                                            \
 		.buffer_units = BUILD_CHECK_INLINE(SIZE, POWER_OF_TWO(SIZE)), \
-		.buffer_units_mask = SIZE - 1,			\
-		.unit_bytes   = sizeof(TYPE),			\
-		.buffer       = (uint8_t *) &((TYPE[SIZE]){}),	\
+		.buffer_units_mask = SIZE - 1,                                \
+		.unit_bytes = sizeof(TYPE),                                   \
+		.buffer = (uint8_t *)&((TYPE[SIZE]){}),                       \
 	})
 
 /* Initialize the queue to empty state. */
@@ -143,7 +143,7 @@ void queue_next(struct queue const *q, struct queue_iterator *it);
  * buffer units.
  */
 struct queue_chunk {
-	size_t  count;
+	size_t count;
 	void *buffer;
 };
 
@@ -206,12 +206,8 @@ size_t queue_add_unit(struct queue const *q, const void *src);
 size_t queue_add_units(struct queue const *q, const void *src, size_t count);
 
 /* Add multiple units to queue using supplied memcpy. */
-size_t queue_add_memcpy(struct queue const *q,
-			const void *src,
-			size_t count,
-			void *(*memcpy)(void *dest,
-					const void *src,
-					size_t n));
+size_t queue_add_memcpy(struct queue const *q, const void *src, size_t count,
+			void *(*memcpy)(void *dest, const void *src, size_t n));
 
 /* Remove one unit from the begin of the queue. */
 size_t queue_remove_unit(struct queue const *q, void *dest);
@@ -220,27 +216,18 @@ size_t queue_remove_unit(struct queue const *q, void *dest);
 size_t queue_remove_units(struct queue const *q, void *dest, size_t count);
 
 /* Remove multiple units from the begin of the queue using supplied memcpy. */
-size_t queue_remove_memcpy(struct queue const *q,
-			   void *dest,
-			   size_t count,
-			   void *(*memcpy)(void *dest,
-					   const void *src,
+size_t queue_remove_memcpy(struct queue const *q, void *dest, size_t count,
+			   void *(*memcpy)(void *dest, const void *src,
 					   size_t n));
 
 /* Peek (return but don't remove) the count elements starting with the i'th. */
-size_t queue_peek_units(struct queue const *q,
-			void *dest,
-			size_t i,
+size_t queue_peek_units(struct queue const *q, void *dest, size_t i,
 			size_t count);
 
 /* Peek (return but don't remove) the count elements starting with the i'th. */
-size_t queue_peek_memcpy(struct queue const *q,
-			 void *dest,
-			 size_t i,
-			 size_t count,
-			 void *(*memcpy)(void *dest,
-				const void *src,
-				size_t n));
+size_t
+queue_peek_memcpy(struct queue const *q, void *dest, size_t i, size_t count,
+		  void *(*memcpy)(void *dest, const void *src, size_t n));
 
 /*
  * These macros will statically select the queue functions based on the number
@@ -248,28 +235,28 @@ size_t queue_peek_memcpy(struct queue const *q,
  * and remove functions are much faster than calling the equivalent generic
  * version with a count of one.
  */
-#define QUEUE_ADD_UNITS(q, src, count)					\
-	({								\
-		size_t result;						\
-									\
-		if (count == 1)						\
-			result = queue_add_unit(q, src);		\
-		else							\
-			result = queue_add_units(q, src, count);	\
-									\
-		result;							\
+#define QUEUE_ADD_UNITS(q, src, count)                           \
+	({                                                       \
+		size_t result;                                   \
+                                                                 \
+		if (count == 1)                                  \
+			result = queue_add_unit(q, src);         \
+		else                                             \
+			result = queue_add_units(q, src, count); \
+                                                                 \
+		result;                                          \
 	})
 
-#define QUEUE_REMOVE_UNITS(q, dest, count)				\
-	({								\
-		size_t result;						\
-									\
-		if (count == 1)						\
-			result = queue_remove_unit(q, dest);		\
-		else							\
-			result = queue_remove_units(q, dest, count);	\
-									\
-		result;							\
+#define QUEUE_REMOVE_UNITS(q, dest, count)                           \
+	({                                                           \
+		size_t result;                                       \
+                                                                     \
+		if (count == 1)                                      \
+			result = queue_remove_unit(q, dest);         \
+		else                                                 \
+			result = queue_remove_units(q, dest, count); \
+                                                                     \
+		result;                                              \
 	})
 
 #endif /* __CROS_EC_QUEUE_H */
diff --git a/include/queue_policies.h b/include/queue_policies.h
index b9d698072f..eb80d3673b 100644
--- a/include/queue_policies.h
+++ b/include/queue_policies.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -7,9 +7,9 @@
 #ifndef __CROS_EC_QUEUE_POLICIES_H
 #define __CROS_EC_QUEUE_POLICIES_H
 
-#include "queue.h"
 #include "consumer.h"
 #include "producer.h"
+#include "queue.h"
 
 /*
  * The direct notification policy manages a 1-to-1 producer consumer model.
@@ -27,7 +27,7 @@ struct queue_policy_direct {
 void queue_add_direct(struct queue_policy const *policy, size_t count);
 void queue_remove_direct(struct queue_policy const *policy, size_t count);
 
-#define QUEUE_POLICY_DIRECT(PRODUCER, CONSUMER)			\
+#define QUEUE_POLICY_DIRECT(PRODUCER, CONSUMER) \
 	((struct queue_policy_direct const) {			\
 		.policy = {					\
 			.add    = queue_add_direct,		\
@@ -37,7 +37,7 @@ void queue_remove_direct(struct queue_policy const *policy, size_t count);
 		.consumer = &CONSUMER,				\
 	})
 
-#define QUEUE_DIRECT(SIZE, TYPE, PRODUCER, CONSUMER)			\
+#define QUEUE_DIRECT(SIZE, TYPE, PRODUCER, CONSUMER) \
 	QUEUE(SIZE, TYPE, QUEUE_POLICY_DIRECT(PRODUCER, CONSUMER).policy)
 
 /*
diff --git a/include/regulator.h b/include/regulator.h
index 9dae7233c1..680239593e 100644
--- a/include/regulator.h
+++ b/include/regulator.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/reset_flag_desc.inc b/include/reset_flag_desc.inc
index ed3ce69a0d..a29f8d8d83 100644
--- a/include/reset_flag_desc.inc
+++ b/include/reset_flag_desc.inc
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/rgb_keyboard.h b/include/rgb_keyboard.h
new file mode 100644
index 0000000000..8c16f6f7e8
--- /dev/null
+++ b/include/rgb_keyboard.h
@@ -0,0 +1,197 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "ec_commands.h"
+#include "stddef.h"
+
+#include <stdbool.h>
+
+/* Use this instead of '3' for readability where applicable. */
+#define SIZE_OF_RGB sizeof(struct rgb_s)
+
+#define RGBKBD_MAX_GCC_LEVEL 0xff
+#define RGBKBD_MAX_SCALE 0xff
+
+#define RGBKBD_CTX_TO_GRID(ctx) ((ctx) - &rgbkbds[0])
+
+struct rgbkbd_cfg {
+	/* Driver for LED IC */
+	const struct rgbkbd_drv *const drv;
+	/* SPI/I2C port (i.e. index of spi_devices[], i2c_ports[]) */
+	union {
+		const uint8_t i2c;
+		const uint8_t spi;
+	};
+	/* Grid size */
+	const uint8_t col_len;
+	const uint8_t row_len;
+};
+
+struct rgbkbd_init {
+	/* Global current control */
+	const uint8_t gcc;
+	/* LED brightness  */
+	const struct rgb_s scale;
+	/* Color */
+	const struct rgb_s color;
+};
+
+/**
+ * Register init settings.
+ *
+ * Must be called before rgbkbd_drv->init() is called.
+ *
+ * @param setting
+ */
+void rgbkbd_register_init_setting(const struct rgbkbd_init *setting);
+
+struct rgbkbd {
+	/* Static configuration */
+	const struct rgbkbd_cfg *const cfg;
+	/* Current state of the port */
+	enum rgbkbd_state state;
+	/* Buffer containing color info for each dot. */
+	struct rgb_s *buf;
+};
+
+struct rgbkbd_drv {
+	/* Reset charger chip. */
+	int (*reset)(struct rgbkbd *ctx);
+	/* Initialize the charger. */
+	int (*init)(struct rgbkbd *ctx);
+	/* Enable/disable the charger. Usually disabled means stand-by. */
+	int (*enable)(struct rgbkbd *ctx, bool enable);
+
+	/**
+	 * Set the colors of multiple RGB-LEDs.
+	 *
+	 * @param ctx    Context.
+	 * @param offset Starting LED position.
+	 * @param color  Array of colors to set. Must be as long as <len>.
+	 * @param len    Length of <color> array.
+	 * @return enum ec_error_list.
+	 */
+	int (*set_color)(struct rgbkbd *ctx, uint8_t offset,
+			 struct rgb_s *color, uint8_t len);
+	/**
+	 * Set the scale of multiple LEDs
+	 *
+	 * @param ctx    Context.
+	 * @param offset Starting LED position.
+	 * @param scale  Scale to be set.
+	 * @param len    Length of LEDs to be set.
+	 * @return enum ec_error_list
+	 */
+	int (*set_scale)(struct rgbkbd *ctx, uint8_t offset, struct rgb_s scale,
+			 uint8_t len);
+	/**
+	 * Set global current control.
+	 *
+	 * @param level Global current control to set.
+	 * @return enum ec_error_list.
+	 */
+	int (*set_gcc)(struct rgbkbd *ctx, uint8_t level);
+};
+
+/* Represents a position of an LED in RGB matrix. */
+struct rgbkbd_coord {
+	uint8_t y : 3;
+	uint8_t x : 5;
+};
+
+/*
+ * For optimization, LED coordinates are encoded in LED IDs. This saves us one
+ * translation.
+ */
+union rgbkbd_coord_u8 {
+	uint8_t u8;
+	struct rgbkbd_coord coord;
+};
+
+#define RGBKBD_COORD(x, y) ((x) << 3 | (y))
+/* Delimiter for rgbkbd_map data */
+#define RGBKBD_DELM 0xff
+/* Non-existent entry indicator for rgbkbd_table */
+#define RGBKBD_NONE 0x00
+
+/*
+ * The matrix consists of multiple grids:
+ *
+ *   +=========-== Matrix =============+
+ *   | +--- Grid1 ---+ +--- Grid2 ---+ |    ^
+ *   | | A C         | | E           | |    |
+ *   | | B           | |             | | rgbkbd_vsize
+ *   | |           D | |             | |    |
+ *   | +-------------+ +-------------+ |    v
+ *   +=================================+
+ *
+ *     <-------- rgbkbd_hsize ------->
+ *
+ * Grids are assumed to be horizontally adjacent. That is, the matrix row size
+ * is fixed and the matrix column size is a multiple of the grid's column size.
+ *
+ * Grid coordinate format is (column, row). In the diagram above,
+ *   A = (0, 0)
+ *   B = (0, 1)
+ *   C = (1, 0)
+ *
+ * In each grid, LEDs are also sequentially indexed. That is,
+ *   A = 0
+ *   B = 1
+ *   C = rgbkbd_vsize
+ *   E = 0
+ *
+ * Matrix coordinate format is (x, y), where x is a horizontal position and y
+ * is a vertical position.
+ *   E = (grid0_hsize, 0)
+ */
+extern struct rgbkbd rgbkbds[];
+extern const uint8_t rgbkbd_count;
+extern const uint8_t rgbkbd_hsize;
+extern const uint8_t rgbkbd_vsize;
+
+/*
+ * rgbkbd_type describes the rgb kb type supported.
+ * i.e. Number of zones and number of LEDs
+ */
+extern enum ec_rgbkbd_type rgbkbd_type;
+
+/*
+ * rgbkbd_map describes a mapping from key IDs to LED IDs.
+ *
+ * Multiple keys can be mapped to one LED and one key can be mapped to multiple
+ * LEDs. For example, if the keyboard is divided into zones, multiple keys point
+ * to the same LED(s). Also, typically larger keys (e.g. space key) should be
+ * allocated multiple LEDs.
+ *
+ * This mapping data (rgbkbd_map[]) is encoded as follows:
+ *
+ *   FF 01 FF 02 03 FF ... FF xx FF
+ *
+ * where LED IDs are in groups, separated by a delimiter (0xff). There are
+ * supposed to be 127 groups, placed in the order of key ID. The first group
+ * (KEY0) is always empty. The above example is interpreted as:
+ *
+ *   KEY0 = {}, KEY1 = {LED1}, KEY2 = {LED2, LED3}, ..., KEY127 = {LEDxx}
+ *
+ * Note the size of rgbkbd_map varies because one key can have multiple LEDs.
+ *
+ * At run time, a translation table is created. This table is an array of the
+ * rgbkbd_map indexes and the table itself is indexed by the key IDs. This
+ * allows a KBMCU to quickly look up LEDs for a given key ID as follows:
+ *
+ *   rgbkbd_map[rgbkbd_table[0]] = FF
+ *   rgbkbd_map[rgbkbd_table[1]] = 01 (followed by FF)
+ *   rgbkbd_map[rgbkbd_table[2]] = 02 (followed by 03 FF)
+ *                   ...
+ */
+extern const uint8_t rgbkbd_map[];
+extern const size_t rgbkbd_map_size;
+
+/*
+ * Driver for keyboard_backlight.
+ */
+extern const struct kblight_drv kblight_rgbkbd;
diff --git a/include/rma_auth.h b/include/rma_auth.h
index 0a4d7c7e71..0b02a1bdc6 100644
--- a/include/rma_auth.h
+++ b/include/rma_auth.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,18 +8,18 @@
 #ifndef __CROS_EC_RMA_AUTH_H
 #define __CROS_EC_RMA_AUTH_H
 
-#include <stdint.h>
+#include "common.h" /* For __packed. */
 
-#include "common.h"  /* For __packed. */
+#include <stdint.h>
 
 /* Current challenge protocol version */
 #define RMA_CHALLENGE_VERSION 0
 
 /* Getters and setters for version_key_id byte */
 #define RMA_CHALLENGE_VKID_BYTE(version, keyid) \
-	(((version) << 6) | ((keyid) & 0x3f))
+	(((version) << 6) | ((keyid)&0x3f))
 #define RMA_CHALLENGE_GET_VERSION(vkidbyte) ((vkidbyte) >> 6)
-#define RMA_CHALLENGE_GET_KEY_ID(vkidbyte) ((vkidbyte) & 0x3f)
+#define RMA_CHALLENGE_GET_KEY_ID(vkidbyte) ((vkidbyte)&0x3f)
 
 #define RMA_DEVICE_ID_SIZE 8
 
diff --git a/include/rollback.h b/include/rollback.h
index 8e439eaac3..14af92dcef 100644
--- a/include/rollback.h
+++ b/include/rollback.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -28,7 +28,7 @@ int rollback_get_minimum_version(void);
  * @return EC_SUCCESS on success, EC_ERROR_* on error (e.g. secret is not
  * initialized)
  */
-int rollback_get_secret(uint8_t *secret);
+enum ec_error_list rollback_get_secret(uint8_t *secret);
 
 /**
  * Update rollback protection block to the version passed as parameter.
@@ -71,4 +71,4 @@ int board_get_entropy(void *buffer, int len);
 
 #endif
 
-#endif  /* __CROS_EC_ROLLBACK_H */
+#endif /* __CROS_EC_ROLLBACK_H */
diff --git a/include/rsa.h b/include/rsa.h
index 60d56711ca..bbc3795c68 100644
--- a/include/rsa.h
+++ b/include/rsa.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -45,23 +45,21 @@
 /* RSA public key definition, VBoot2 packing */
 struct rsa_public_key {
 	uint32_t size;
-	uint32_t n0inv;           /* -1 / n[0] mod 2^32 */
-	uint32_t n[RSANUMWORDS];  /* modulus as little endian array */
+	uint32_t n0inv; /* -1 / n[0] mod 2^32 */
+	uint32_t n[RSANUMWORDS]; /* modulus as little endian array */
 	uint32_t rr[RSANUMWORDS]; /* R^2 as little endian array */
 };
 #else
 /* RSA public key definition */
 struct rsa_public_key {
-	uint32_t n[RSANUMWORDS];  /* modulus as little endian array */
+	uint32_t n[RSANUMWORDS]; /* modulus as little endian array */
 	uint32_t rr[RSANUMWORDS]; /* R^2 as little endian array */
-	uint32_t n0inv;           /* -1 / n[0] mod 2^32 */
+	uint32_t n0inv; /* -1 / n[0] mod 2^32 */
 };
 #endif
 
-int rsa_verify(const struct rsa_public_key *key,
-	       const uint8_t *signature,
-	       const uint8_t *sha,
-	       uint32_t *workbuf32);
+int rsa_verify(const struct rsa_public_key *key, const uint8_t *signature,
+	       const uint8_t *sha, uint32_t *workbuf32);
 
 #endif /* !__ASSEMBLER__ */
 
diff --git a/include/rtc.h b/include/rtc.h
index cff1ee0f64..0225801e71 100644
--- a/include/rtc.h
+++ b/include/rtc.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,14 +10,14 @@
 
 #include "common.h"
 
-#define SECS_PER_MINUTE     60
-#define SECS_PER_HOUR       (60 * SECS_PER_MINUTE)
-#define SECS_PER_DAY        (24 * SECS_PER_HOUR)
-#define SECS_PER_WEEK       (7 * SECS_PER_DAY)
-#define SECS_PER_YEAR       (365 * SECS_PER_DAY)
+#define SECS_PER_MINUTE 60
+#define SECS_PER_HOUR (60 * SECS_PER_MINUTE)
+#define SECS_PER_DAY (24 * SECS_PER_HOUR)
+#define SECS_PER_WEEK (7 * SECS_PER_DAY)
+#define SECS_PER_YEAR (365 * SECS_PER_DAY)
 /* The seconds elapsed from 01-01-1970 to 01-01-2000 */
-#define SECS_TILL_YEAR_2K   (946684800)
-#define IS_LEAP_YEAR(x)     \
+#define SECS_TILL_YEAR_2K (946684800)
+#define IS_LEAP_YEAR(x) \
 	(((x) % 4 == 0) && (((x) % 100 != 0) || ((x) % 400 == 0)))
 
 struct calendar_date {
diff --git a/include/rwsig.h b/include/rwsig.h
index c43932b173..3629c8c667 100644
--- a/include/rwsig.h
+++ b/include/rwsig.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -77,25 +77,34 @@ void rwsig_jump_now(void);
 #endif /* ! CONFIG_RO_PUBKEY_SIZE */
 #ifndef CONFIG_RO_PUBKEY_ADDR
 #ifdef CONFIG_RWSIG_TYPE_RWSIG
-#define CONFIG_RO_PUBKEY_STORAGE_OFF (CONFIG_RO_STORAGE_OFF		\
-				      + CONFIG_RO_SIZE			\
-				      - CONFIG_RO_PUBKEY_SIZE)
+#define CONFIG_RO_PUBKEY_STORAGE_OFF \
+	(CONFIG_RO_STORAGE_OFF + CONFIG_RO_SIZE - CONFIG_RO_PUBKEY_SIZE)
 
 /* The pubkey resides at the end of the RO image */
-#define CONFIG_RO_PUBKEY_ADDR (CONFIG_PROGRAM_MEMORY_BASE		\
-			       + CONFIG_EC_PROTECTED_STORAGE_OFF	\
-			       + CONFIG_RO_PUBKEY_STORAGE_OFF)
+#define CONFIG_RO_PUBKEY_ADDR                                           \
+	(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_EC_PROTECTED_STORAGE_OFF + \
+	 CONFIG_RO_PUBKEY_STORAGE_OFF)
 #else
 /*
  * usbpd1 type assumes pubkey location at the end of first half of flash,
  * which might actually be in the PSTATE region.
  */
-#define CONFIG_RO_PUBKEY_ADDR (CONFIG_PROGRAM_MEMORY_BASE	\
-			       + (CONFIG_FLASH_SIZE / 2)	\
-			       - CONFIG_RO_PUBKEY_SIZE)
+#define CONFIG_RO_PUBKEY_ADDR                                         \
+	(CONFIG_PROGRAM_MEMORY_BASE + (CONFIG_FLASH_SIZE_BYTES / 2) - \
+	 CONFIG_RO_PUBKEY_SIZE)
 #endif
 #endif /* CONFIG_RO_PUBKEY_ADDR */
 
+/* Some chips require reading pubkey from a memory mapped address */
+#ifndef CONFIG_RO_PUBKEY_READ_ADDR
+#define CONFIG_RO_PUBKEY_READ_ADDR CONFIG_RO_PUBKEY_ADDR
+#endif
+
+/* Some chips require reading signature from a memory mapped address */
+#ifndef CONFIG_RWSIG_READ_ADDR
+#define CONFIG_RWSIG_READ_ADDR CONFIG_RW_SIG_ADDR
+#endif
+
 #ifndef CONFIG_RW_SIG_SIZE
 #ifdef CONFIG_RWSIG_TYPE_RWSIG
 /*
@@ -108,19 +117,19 @@ void rwsig_jump_now(void);
 #endif
 #endif /* ! CONFIG_RW_SIG_SIZE */
 /* The signature resides at the end of each RW copy */
-#define RW_SIG_OFFSET		(CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE)
-#define RW_A_ADDR		(CONFIG_PROGRAM_MEMORY_BASE +		\
-				 CONFIG_EC_WRITABLE_STORAGE_OFF +	\
-				 CONFIG_RW_STORAGE_OFF)
+#define RW_SIG_OFFSET (CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE)
+#define RW_A_ADDR                                                      \
+	(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_EC_WRITABLE_STORAGE_OFF + \
+	 CONFIG_RW_STORAGE_OFF)
 /* Assume the layout is same as RW_A and it sits right after RW_A */
-#define RW_B_ADDR		(CONFIG_PROGRAM_MEMORY_BASE + \
-				 CONFIG_EC_WRITABLE_STORAGE_OFF + \
-				 CONFIG_RW_B_STORAGE_OFF)
+#define RW_B_ADDR                                                      \
+	(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_EC_WRITABLE_STORAGE_OFF + \
+	 CONFIG_RW_B_STORAGE_OFF)
 #ifndef CONFIG_RW_SIG_ADDR
-#define CONFIG_RW_SIG_ADDR	(RW_A_ADDR + RW_SIG_OFFSET)
+#define CONFIG_RW_SIG_ADDR (RW_A_ADDR + RW_SIG_OFFSET)
 #endif
 #ifndef CONFIG_RW_B_SIG_ADDR
-#define CONFIG_RW_B_SIG_ADDR	(RW_B_ADDR + RW_SIG_OFFSET)
+#define CONFIG_RW_B_SIG_ADDR (RW_B_ADDR + RW_SIG_OFFSET)
 #endif
 
 #endif /* __CROS_EC_RWSIG_H */
diff --git a/include/scoped_fast_cpu.h b/include/scoped_fast_cpu.h
new file mode 100644
index 0000000000..5c291362b9
--- /dev/null
+++ b/include/scoped_fast_cpu.h
@@ -0,0 +1,36 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* A class to scope the range of boosting CPU. */
+
+#ifndef __CROS_EC_SCOPED_FAST_CPU_H
+#define __CROS_EC_SCOPED_FAST_CPU_H
+
+#include "clock.h"
+
+class ScopedFastCpu {
+    public:
+	ScopedFastCpu()
+		: previous_state_(current_state_)
+	{
+		if (current_state_ != 1) {
+			clock_enable_module(MODULE_FAST_CPU, 1);
+			current_state_ = 1;
+		}
+	}
+	~ScopedFastCpu()
+	{
+		if (current_state_ != previous_state_) {
+			clock_enable_module(MODULE_FAST_CPU, previous_state_);
+			current_state_ = previous_state_;
+		}
+	}
+
+    private:
+	int previous_state_;
+	static inline int current_state_;
+};
+
+#endif /* __CROS_EC_SCOPED_FAST_CPU_H */
diff --git a/include/sfdp.h b/include/sfdp.h
index 087708d799..e1cd6372f2 100644
--- a/include/sfdp.h
+++ b/include/sfdp.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,22 +12,20 @@
  * Helper macros to declare and access SFDP defined bitfields at a JEDEC SFDP
  * defined double word (32b) granularity.
  */
-#define SFDP_DEFINE_BITMASK_32(name, hi, lo)                              \
-	static const uint32_t name = (((1ULL << ((hi) - (lo) + 1)) - 1UL) \
-				      << (lo));
-#define SFDP_DEFINE_SHIFT_32(name, hi, lo) \
-	static const size_t name = (lo);
-#define SFDP_DEFINE_BITFIELD(name, hi, lo)            \
-	SFDP_DEFINE_BITMASK_32(name ## _MASK, hi, lo) \
-	SFDP_DEFINE_SHIFT_32(name ## _SHIFT, hi, lo)
-#define SFDP_GET_BITFIELD(name, dw) \
-	(((dw) & name ## _MASK) >> name ## _SHIFT)
+#define SFDP_DEFINE_BITMASK_32(name, hi, lo) \
+	static const uint32_t name =         \
+		(((1ULL << ((hi) - (lo) + 1)) - 1UL) << (lo));
+#define SFDP_DEFINE_SHIFT_32(name, hi, lo) static const size_t name = (lo);
+#define SFDP_DEFINE_BITFIELD(name, hi, lo)          \
+	SFDP_DEFINE_BITMASK_32(name##_MASK, hi, lo) \
+	SFDP_DEFINE_SHIFT_32(name##_SHIFT, hi, lo)
+#define SFDP_GET_BITFIELD(name, dw) (((dw)&name##_MASK) >> name##_SHIFT)
 
 /**
  * Helper macros to construct SFDP defined double words (32b). Note reserved or
  * unused fields must always be set to all 1's.
  */
-#define SFDP_BITFIELD(name, value) (((value) << name ## _SHIFT) & name ## _MASK)
+#define SFDP_BITFIELD(name, value) (((value) << name##_SHIFT) & name##_MASK)
 #define SFDP_UNUSED(hi, lo) (((1ULL << ((hi) - (lo) + 1)) - 1UL) << (lo))
 
 /******************************************************************************/
@@ -85,10 +83,9 @@ SFDP_DEFINE_BITFIELD(SFDP_HEADER_DW1_S, 7, 0);
 SFDP_DEFINE_BITFIELD(SFDP_HEADER_DW2_NPH, 23, 16);
 SFDP_DEFINE_BITFIELD(SFDP_HEADER_DW2_SFDP_MAJOR, 15, 8);
 SFDP_DEFINE_BITFIELD(SFDP_HEADER_DW2_SFDP_MINOR, 7, 0);
-#define SFDP_HEADER_DWORD_2(nph, major, minor)              \
-	(SFDP_UNUSED(31, 24) |                              \
-	 SFDP_BITFIELD(SFDP_HEADER_DW2_NPH, nph) |          \
-	 SFDP_BITFIELD(SFDP_HEADER_DW2_SFDP_MAJOR, major) | \
+#define SFDP_HEADER_DWORD_2(nph, major, minor)                           \
+	(SFDP_UNUSED(31, 24) | SFDP_BITFIELD(SFDP_HEADER_DW2_NPH, nph) | \
+	 SFDP_BITFIELD(SFDP_HEADER_DW2_SFDP_MAJOR, major) |              \
 	 SFDP_BITFIELD(SFDP_HEADER_DW2_SFDP_MINOR, minor))
 
 /******************************************************************************/
@@ -98,7 +95,7 @@ SFDP_DEFINE_BITFIELD(SFDP_HEADER_DW2_SFDP_MINOR, 7, 0);
 /* In SFDP v1.0, the only reserved ID was the Basic Flash Parameter Table ID of
  * 0x00. Otherwise this field must be set to the vendor's manufacturer ID. Note,
  * the spec does not call out how to report the manufacturer bank number. */
- #define BASIC_FLASH_PARAMETER_TABLE_1_0_ID 0x00
+#define BASIC_FLASH_PARAMETER_TABLE_1_0_ID 0x00
 
 /*
  * SFDP v1.0: Parameter Header 1st DWORD
@@ -178,8 +175,8 @@ SFDP_DEFINE_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW1_ID_LSB, 7, 0);
  */
 SFDP_DEFINE_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW2_ID_MSB, 31, 24);
 SFDP_DEFINE_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW2_PTP, 23, 0);
-#define SFDP_1_5_PARAMETER_HEADER_DWORD_2(idmsb, ptp)                     \
-	(SFDP_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW2_ID_MSB, idmsb) |     \
+#define SFDP_1_5_PARAMETER_HEADER_DWORD_2(idmsb, ptp)                 \
+	(SFDP_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW2_ID_MSB, idmsb) | \
 	 SFDP_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW2_PTP, ptp))
 
 /******************************************************************************/
@@ -226,20 +223,20 @@ SFDP_DEFINE_BITFIELD(BFPT_1_0_DW1_WREN_OPCODE_SELECT, 4, 4);
 SFDP_DEFINE_BITFIELD(BFPT_1_0_DW1_WREN_REQ, 3, 3);
 SFDP_DEFINE_BITFIELD(BFPT_1_0_DW1_WRITE_GRANULARITY, 2, 2);
 SFDP_DEFINE_BITFIELD(BFPT_1_0_DW1_4KIB_AVAILABILITY, 1, 0);
-#define BFPT_1_0_DWORD_1(fr114, fr144, fr122, dtr, addr, fr112,              \
-				    rm4kb, wrenop, wrenrq, wrgr,  ergr)      \
-	(SFDP_UNUSED(31, 23) |                                               \
-	 SFDP_BITFIELD(BFPT_1_0_DW1_1_1_4_SUPPORTED, fr114) |                \
-	 SFDP_BITFIELD(BFPT_1_0_DW1_1_4_4_SUPPORTED, fr144) |                \
-	 SFDP_BITFIELD(BFPT_1_0_DW1_1_2_2_SUPPORTED, fr122) |                \
-	 SFDP_BITFIELD(BFPT_1_0_DW1_DTR_SUPPORTED, dtr) |                    \
-	 SFDP_BITFIELD(BFPT_1_0_DW1_ADDR_BYTES, addr) |                      \
-	 SFDP_BITFIELD(BFPT_1_0_DW1_1_1_2_SUPPORTED, fr112) |                \
-	 SFDP_BITFIELD(BFPT_1_0_DW1_4KIB_ERASE_OPCODE, rm4kb) |              \
-	 SFDP_UNUSED(7, 5) |                                                 \
-	 SFDP_BITFIELD(BFPT_1_0_DW1_WREN_OPCODE_SELECT, wrenop) |            \
-	 SFDP_BITFIELD(BFPT_1_0_DW1_WREN_REQ, wrenrq) |                      \
-	 SFDP_BITFIELD(BFPT_1_0_DW1_WRITE_GRANULARITY, wrgr) |               \
+#define BFPT_1_0_DWORD_1(fr114, fr144, fr122, dtr, addr, fr112, rm4kb, wrenop, \
+			 wrenrq, wrgr, ergr)                                   \
+	(SFDP_UNUSED(31, 23) |                                                 \
+	 SFDP_BITFIELD(BFPT_1_0_DW1_1_1_4_SUPPORTED, fr114) |                  \
+	 SFDP_BITFIELD(BFPT_1_0_DW1_1_4_4_SUPPORTED, fr144) |                  \
+	 SFDP_BITFIELD(BFPT_1_0_DW1_1_2_2_SUPPORTED, fr122) |                  \
+	 SFDP_BITFIELD(BFPT_1_0_DW1_DTR_SUPPORTED, dtr) |                      \
+	 SFDP_BITFIELD(BFPT_1_0_DW1_ADDR_BYTES, addr) |                        \
+	 SFDP_BITFIELD(BFPT_1_0_DW1_1_1_2_SUPPORTED, fr112) |                  \
+	 SFDP_BITFIELD(BFPT_1_0_DW1_4KIB_ERASE_OPCODE, rm4kb) |                \
+	 SFDP_UNUSED(7, 5) |                                                   \
+	 SFDP_BITFIELD(BFPT_1_0_DW1_WREN_OPCODE_SELECT, wrenop) |              \
+	 SFDP_BITFIELD(BFPT_1_0_DW1_WREN_REQ, wrenrq) |                        \
+	 SFDP_BITFIELD(BFPT_1_0_DW1_WRITE_GRANULARITY, wrgr) |                 \
 	 SFDP_BITFIELD(BFPT_1_0_DW1_4KIB_AVAILABILITY, ergr))
 
 /* Basic Flash Parameter Table v1.0 2nd DWORD
@@ -270,13 +267,12 @@ SFDP_DEFINE_BITFIELD(BFPT_1_0_DW3_1_1_4_WAIT_STATE_CLOCKS, 20, 16);
 SFDP_DEFINE_BITFIELD(BFPT_1_0_DW3_1_4_4_OPCODE, 15, 8);
 SFDP_DEFINE_BITFIELD(BFPT_1_0_DW3_1_4_4_MODE_BITS, 7, 5);
 SFDP_DEFINE_BITFIELD(BFPT_1_0_DW3_1_4_4_WAIT_STATE_CLOCKS, 4, 0);
-#define BFPT_1_0_DWORD_3(fr114op, fr114mb, fr114dc,                \
-				    fr144op, fr144mb, fr144dc)     \
-	(SFDP_BITFIELD(BFPT_1_0_DW3_1_1_4_OPCODE, fr114op) |       \
-	 SFDP_BITFIELD(BFPT_1_0_DW3_1_1_4_MODE_BITS, fr114mb) |    \
-	 SFDP_BITFIELD(BFPT_1_0_DW3_1_1_4_WAIT_STATE_CLOCKS, fr114dc) | \
-	 SFDP_BITFIELD(BFPT_1_0_DW3_1_4_4_OPCODE, fr144op) |       \
-	 SFDP_BITFIELD(BFPT_1_0_DW3_1_4_4_MODE_BITS, fr144mb) |    \
+#define BFPT_1_0_DWORD_3(fr114op, fr114mb, fr114dc, fr144op, fr144mb, fr144dc) \
+	(SFDP_BITFIELD(BFPT_1_0_DW3_1_1_4_OPCODE, fr114op) |                   \
+	 SFDP_BITFIELD(BFPT_1_0_DW3_1_1_4_MODE_BITS, fr114mb) |                \
+	 SFDP_BITFIELD(BFPT_1_0_DW3_1_1_4_WAIT_STATE_CLOCKS, fr114dc) |        \
+	 SFDP_BITFIELD(BFPT_1_0_DW3_1_4_4_OPCODE, fr144op) |                   \
+	 SFDP_BITFIELD(BFPT_1_0_DW3_1_4_4_MODE_BITS, fr144mb) |                \
 	 SFDP_BITFIELD(BFPT_1_0_DW3_1_4_4_WAIT_STATE_CLOCKS, fr144dc))
 
 /* Basic Flash Parameter Table v1.0 4th DWORD
@@ -294,13 +290,12 @@ SFDP_DEFINE_BITFIELD(BFPT_1_0_DW4_1_2_2_WAIT_STATE_CLOCKS, 20, 16);
 SFDP_DEFINE_BITFIELD(BFPT_1_0_DW4_1_1_2_OPCODE, 15, 8);
 SFDP_DEFINE_BITFIELD(BFPT_1_0_DW4_1_1_2_MODE_BITS, 7, 5);
 SFDP_DEFINE_BITFIELD(BFPT_1_0_DW4_1_1_2_WAIT_STATE_CLOCKS, 4, 0);
-#define BFPT_1_0_DWORD_4(fr122op, fr122mb, fr122dc,                \
-				    fr112op, fr112mb, fr112dc)     \
-	(SFDP_BITFIELD(BFPT_1_0_DW4_1_2_2_OPCODE, fr122op) |       \
-	 SFDP_BITFIELD(BFPT_1_0_DW4_1_2_2_MODE_BITS, fr122mb) |    \
-	 SFDP_BITFIELD(BFPT_1_0_DW4_1_2_2_WAIT_STATE_CLOCKS, fr122dc) | \
-	 SFDP_BITFIELD(BFPT_1_0_DW4_1_1_2_OPCODE, fr112op) |       \
-	 SFDP_BITFIELD(BFPT_1_0_DW4_1_1_2_MODE_BITS, fr112mb) |    \
+#define BFPT_1_0_DWORD_4(fr122op, fr122mb, fr122dc, fr112op, fr112mb, fr112dc) \
+	(SFDP_BITFIELD(BFPT_1_0_DW4_1_2_2_OPCODE, fr122op) |                   \
+	 SFDP_BITFIELD(BFPT_1_0_DW4_1_2_2_MODE_BITS, fr122mb) |                \
+	 SFDP_BITFIELD(BFPT_1_0_DW4_1_2_2_WAIT_STATE_CLOCKS, fr122dc) |        \
+	 SFDP_BITFIELD(BFPT_1_0_DW4_1_1_2_OPCODE, fr112op) |                   \
+	 SFDP_BITFIELD(BFPT_1_0_DW4_1_1_2_MODE_BITS, fr112mb) |                \
 	 SFDP_BITFIELD(BFPT_1_0_DW4_1_1_2_WAIT_STATE_CLOCKS, fr112dc))
 
 /* Basic Flash Parameter Table v1.0 5th DWORD
@@ -328,9 +323,9 @@ SFDP_DEFINE_BITFIELD(BFPT_1_0_DW5_2_2_2_SUPPORTED, 0, 0);
 SFDP_DEFINE_BITFIELD(BFPT_1_0_DW6_2_2_2_OPCODE, 31, 24);
 SFDP_DEFINE_BITFIELD(BFPT_1_0_DW6_2_2_2_MODE_BITS, 23, 21);
 SFDP_DEFINE_BITFIELD(BFPT_1_0_DW6_2_2_2_WAIT_STATE_CLOCKS, 20, 16);
-#define BFPT_1_0_DWORD_6(fr222op, fr222mb, fr222dc)                \
-	(SFDP_BITFIELD(BFPT_1_0_DW6_2_2_2_OPCODE, fr222op) |       \
-	 SFDP_BITFIELD(BFPT_1_0_DW6_2_2_2_MODE_BITS, fr222mb) |    \
+#define BFPT_1_0_DWORD_6(fr222op, fr222mb, fr222dc)                     \
+	(SFDP_BITFIELD(BFPT_1_0_DW6_2_2_2_OPCODE, fr222op) |            \
+	 SFDP_BITFIELD(BFPT_1_0_DW6_2_2_2_MODE_BITS, fr222mb) |         \
 	 SFDP_BITFIELD(BFPT_1_0_DW6_2_2_2_WAIT_STATE_CLOCKS, fr222dc) | \
 	 SFDP_UNUSED(15, 0))
 
@@ -344,9 +339,9 @@ SFDP_DEFINE_BITFIELD(BFPT_1_0_DW6_2_2_2_WAIT_STATE_CLOCKS, 20, 16);
 SFDP_DEFINE_BITFIELD(BFPT_1_0_DW7_4_4_4_OPCODE, 31, 24);
 SFDP_DEFINE_BITFIELD(BFPT_1_0_DW7_4_4_4_MODE_BITS, 23, 21);
 SFDP_DEFINE_BITFIELD(BFPT_1_0_DW7_4_4_4_WAIT_STATE_CLOCKS, 20, 16);
-#define BFPT_1_0_DWORD_7(fr444op, fr444mb, fr444dc)                \
-	(SFDP_BITFIELD(BFPT_1_0_DW7_4_4_4_OPCODE, fr444op) |       \
-	 SFDP_BITFIELD(BFPT_1_0_DW7_4_4_4_MODE_BITS, fr444mb) |    \
+#define BFPT_1_0_DWORD_7(fr444op, fr444mb, fr444dc)                     \
+	(SFDP_BITFIELD(BFPT_1_0_DW7_4_4_4_OPCODE, fr444op) |            \
+	 SFDP_BITFIELD(BFPT_1_0_DW7_4_4_4_MODE_BITS, fr444mb) |         \
 	 SFDP_BITFIELD(BFPT_1_0_DW7_4_4_4_WAIT_STATE_CLOCKS, fr444dc) | \
 	 SFDP_UNUSED(15, 0))
 
@@ -419,17 +414,16 @@ SFDP_DEFINE_BITFIELD(BFPT_1_5_DW10_ERASE_2_TIME_CNT, 15, 11);
 SFDP_DEFINE_BITFIELD(BFPT_1_5_DW10_ERASE_1_TIME_UNIT, 10, 9);
 SFDP_DEFINE_BITFIELD(BFPT_1_5_DW10_ERASE_1_TIME_CNT, 8, 4);
 SFDP_DEFINE_BITFIELD(BFPT_1_5_DW10_ERASE_TIME_MAX_MULT, 3, 0);
-#define BFPT_1_5_DWORD_10(rm4unit, rm4count, rm3unit,               \
-			  rm3count, rm2unit, rm2count,              \
-			  rm1unit, rm1count, maxmult)               \
-	(SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_4_TIME_UNIT, rm4unit) |  \
-	 SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_4_TIME_CNT, rm4count) |  \
-	 SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_3_TIME_UNIT, rm3unit) |  \
-	 SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_3_TIME_CNT, rm3count) |  \
-	 SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_2_TIME_UNIT, rm2unit) |  \
-	 SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_2_TIME_CNT, rm2count) |  \
-	 SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_1_TIME_UNIT, rm1unit) |  \
-	 SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_1_TIME_CNT, rm1count) |  \
+#define BFPT_1_5_DWORD_10(rm4unit, rm4count, rm3unit, rm3count, rm2unit, \
+			  rm2count, rm1unit, rm1count, maxmult)          \
+	(SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_4_TIME_UNIT, rm4unit) |       \
+	 SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_4_TIME_CNT, rm4count) |       \
+	 SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_3_TIME_UNIT, rm3unit) |       \
+	 SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_3_TIME_CNT, rm3count) |       \
+	 SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_2_TIME_UNIT, rm2unit) |       \
+	 SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_2_TIME_CNT, rm2count) |       \
+	 SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_1_TIME_UNIT, rm1unit) |       \
+	 SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_1_TIME_CNT, rm1count) |       \
 	 SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_TIME_MAX_MULT, maxmult))
 
 /* Basic Flash Parameter Table v1.5 11th DWORD
@@ -464,18 +458,12 @@ SFDP_DEFINE_BITFIELD(BFPT_1_5_DW11_WR_TIME_MAX_MULT, 3, 0);
 #define BFPT_1_5_DWORD_11(crmunit, crmcount, mrbunit, mrbcount, initunit,  \
 			  initcount, pgwrunit, pgwrcount, pagesz, maxmult) \
 	(SFDP_UNUSED(31, 31) |                                             \
-	 SFDP_BITFIELD(BFPT_1_5_DW11_CHIP_ERASE_TIME_UNIT,                 \
-		       crmunit) |                                          \
-	 SFDP_BITFIELD(BFPT_1_5_DW11_CHIP_ERASE_TIME_CNT,                  \
-		       crmcount) |                                         \
-	 SFDP_BITFIELD(BFPT_1_5_DW11_MORE_BYTE_WR_TIME_UNIT,               \
-		       mrbunit) |                                          \
-	 SFDP_BITFIELD(BFPT_1_5_DW11_MORE_BYTE_WR_TIME_CNT,                \
-		       mrbcount) |                                         \
-	 SFDP_BITFIELD(BFPT_1_5_DW11_INIT_BYTE_WR_TIME_UNIT,               \
-		       initunit) |                                         \
-	 SFDP_BITFIELD(BFPT_1_5_DW11_INIT_BYTE_WR_TIME_CNT,                \
-		       initcount) |                                        \
+	 SFDP_BITFIELD(BFPT_1_5_DW11_CHIP_ERASE_TIME_UNIT, crmunit) |      \
+	 SFDP_BITFIELD(BFPT_1_5_DW11_CHIP_ERASE_TIME_CNT, crmcount) |      \
+	 SFDP_BITFIELD(BFPT_1_5_DW11_MORE_BYTE_WR_TIME_UNIT, mrbunit) |    \
+	 SFDP_BITFIELD(BFPT_1_5_DW11_MORE_BYTE_WR_TIME_CNT, mrbcount) |    \
+	 SFDP_BITFIELD(BFPT_1_5_DW11_INIT_BYTE_WR_TIME_UNIT, initunit) |   \
+	 SFDP_BITFIELD(BFPT_1_5_DW11_INIT_BYTE_WR_TIME_CNT, initcount) |   \
 	 SFDP_BITFIELD(BFPT_1_5_DW11_PAGE_WR_TIME_UNIT, pgwrunit) |        \
 	 SFDP_BITFIELD(BFPT_1_5_DW11_PAGE_WR_TIME_CNT, pgwrcount) |        \
 	 SFDP_BITFIELD(BFPT_1_5_DW11_PAGE_SIZE, pagesz) |                  \
@@ -532,26 +520,21 @@ SFDP_DEFINE_BITFIELD(BFPT_1_5_DW12_SUSP_WR_MAX_LAT_CNT, 17, 13);
 SFDP_DEFINE_BITFIELD(BFPT_1_5_DW12_WR_RES_TO_SUSP_LAT_CNT, 12, 9);
 SFDP_DEFINE_BITFIELD(BFPT_1_5_DW12_PROHIB_OPS_DURING_RM_SUSP, 7, 4);
 SFDP_DEFINE_BITFIELD(BFPT_1_5_DW12_PROHIB_OPS_DURING_WR_SUSP, 3, 0);
-#define BFPT_1_5_DWORD_12(unsup, susprmlatun, susprmlatcnt, rmressusplatcnt, \
-			  suspwrmaxlatunit, suspwrmaxlatcnt, wrressuspcnt,   \
-			  prohibopsrmsusp, prohibopswrsusp)                  \
-	(SFDP_BITFIELD(BFPT_1_5_DW12_SUSPEND_UNSUPPORTED, unsup) |           \
-	 SFDP_BITFIELD(BFPT_1_5_DW12_SUSP_RM_MAX_LAT_UNIT,                   \
-		       susprmlatun) |                                        \
-	 SFDP_BITFIELD(BFPT_1_5_DW12_SUSP_RM_MAX_LAT_CNT,                    \
-		       susprmlatcnt) |                                       \
-	 SFDP_BITFIELD(BFPT_1_5_DW12_RM_RES_TO_SUSP_LAT_CNT,                 \
-		       rmressusplatcnt) |                                    \
-	 SFDP_BITFIELD(BFPT_1_5_DW12_SUSP_WR_MAX_LAT_UNIT,                   \
-		       suspwrmaxlatunit) |                                   \
-	 SFDP_BITFIELD(BFPT_1_5_DW12_SUSP_WR_MAX_LAT_CNT,                    \
-		       suspwrmaxlatcnt) |                                    \
-	 SFDP_BITFIELD(BFPT_1_5_DW12_WR_RES_TO_SUSP_LAT_CNT,                 \
-		       wrressuspcnt) |                                       \
-	 SFDP_UNUSED(8, 8) |                                                 \
-	 SFDP_BITFIELD(BFPT_1_5_DW12_PROHIB_OPS_DURING_RM_SUSP,              \
-		       prohibopsrmsusp) |                                    \
-	 SFDP_BITFIELD(BFPT_1_5_DW12_PROHIB_OPS_DURING_WR_SUSP,              \
+#define BFPT_1_5_DWORD_12(unsup, susprmlatun, susprmlatcnt, rmressusplatcnt,   \
+			  suspwrmaxlatunit, suspwrmaxlatcnt, wrressuspcnt,     \
+			  prohibopsrmsusp, prohibopswrsusp)                    \
+	(SFDP_BITFIELD(BFPT_1_5_DW12_SUSPEND_UNSUPPORTED, unsup) |             \
+	 SFDP_BITFIELD(BFPT_1_5_DW12_SUSP_RM_MAX_LAT_UNIT, susprmlatun) |      \
+	 SFDP_BITFIELD(BFPT_1_5_DW12_SUSP_RM_MAX_LAT_CNT, susprmlatcnt) |      \
+	 SFDP_BITFIELD(BFPT_1_5_DW12_RM_RES_TO_SUSP_LAT_CNT,                   \
+		       rmressusplatcnt) |                                      \
+	 SFDP_BITFIELD(BFPT_1_5_DW12_SUSP_WR_MAX_LAT_UNIT, suspwrmaxlatunit) | \
+	 SFDP_BITFIELD(BFPT_1_5_DW12_SUSP_WR_MAX_LAT_CNT, suspwrmaxlatcnt) |   \
+	 SFDP_BITFIELD(BFPT_1_5_DW12_WR_RES_TO_SUSP_LAT_CNT, wrressuspcnt) |   \
+	 SFDP_UNUSED(8, 8) |                                                   \
+	 SFDP_BITFIELD(BFPT_1_5_DW12_PROHIB_OPS_DURING_RM_SUSP,                \
+		       prohibopsrmsusp) |                                      \
+	 SFDP_BITFIELD(BFPT_1_5_DW12_PROHIB_OPS_DURING_WR_SUSP,                \
 		       prohibopswrsusp))
 
 /* Basic Flash Parameter Table v1.5 13th DWORD
@@ -600,12 +583,10 @@ SFDP_DEFINE_BITFIELD(BFPT_1_5_DW14_POWER_UP_TIME_CNT, 12, 8);
 SFDP_DEFINE_BITFIELD(BFPT_1_5_DW14_BUSY_FLAGS, 7, 2);
 #define BFPT_1_5_DWORD_14(pwrdwnunsup, pwrdwnop, pwrupop, pwrupunit, pwrupcnt, \
 			  busypollflags)                                       \
-	(SFDP_BITFIELD(BFPT_1_5_DW14_POWER_DOWN_UNSUPPORTED,                   \
-			pwrdwnunsup) |                                         \
+	(SFDP_BITFIELD(BFPT_1_5_DW14_POWER_DOWN_UNSUPPORTED, pwrdwnunsup) |    \
 	 SFDP_BITFIELD(BFPT_1_5_DW14_POWER_DOWN_OPCODE, pwrdwnop) |            \
 	 SFDP_BITFIELD(BFPT_1_5_DW14_POWER_UP_OPCODE, pwrupop) |               \
-	 SFDP_BITFIELD(BFPT_1_5_DW14_POWER_UP_TIME_UNIT,                       \
-		       pwrupunit) |                                            \
+	 SFDP_BITFIELD(BFPT_1_5_DW14_POWER_UP_TIME_UNIT, pwrupunit) |          \
 	 SFDP_BITFIELD(BFPT_1_5_DW14_POWER_UP_TIME_CNT, pwrupcnt) |            \
 	 SFDP_BITFIELD(BFPT_1_5_DW14_BUSY_FLAGS, busypollflags) |              \
 	 SFDP_UNUSED(1, 0))
@@ -702,7 +683,6 @@ SFDP_DEFINE_BITFIELD(BFPT_1_5_DW15_4_4_4_EXIT, 3, 0);
 	 SFDP_BITFIELD(BFPT_1_5_DW15_4_4_4_ENTRY, fr444entry) |              \
 	 SFDP_BITFIELD(BFPT_1_5_DW15_4_4_4_EXIT, fr444exit))
 
-
 /* Basic Flash Parameter Table v1.5 16th DWORD
  * -------------------------------------------
  * <31:24> : Enter 4-Byte Addressing, where
@@ -804,4 +784,4 @@ SFDP_DEFINE_BITFIELD(BFPT_1_5_DW16_STATUS_REG_1, 6, 0);
 	 SFDP_UNUSED(7, 7) |                                  \
 	 SFDP_BITFIELD(BFPT_1_5_DW16_STATUS_REG_1, statusreg1))
 
-#endif  /* __CROS_EC_SFDP_H */
+#endif /* __CROS_EC_SFDP_H */
diff --git a/include/sha1.h b/include/sha1.h
index 42c0f2612f..12d277d1ac 100644
--- a/include/sha1.h
+++ b/include/sha1.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,7 +11,7 @@
 #include "common.h"
 #ifdef HOST_TOOLS_BUILD
 #include <string.h>
-#define DIV_ROUND_UP(x, y) (((x) + ((y) - 1)) / (y))
+#define DIV_ROUND_UP(x, y) (((x) + ((y)-1)) / (y))
 #else
 #include "util.h"
 #endif
@@ -33,4 +33,4 @@ void sha1_init(struct sha1_ctx *ctx);
 void sha1_update(struct sha1_ctx *ctx, const uint8_t *data, uint32_t len);
 uint8_t *sha1_final(struct sha1_ctx *ctx);
 
-#endif  /* __CROS_EC_SHA1_H */
+#endif /* __CROS_EC_SHA1_H */
diff --git a/include/sha256.h b/include/sha256.h
index 6671c0ae3a..00cdb73446 100644
--- a/include/sha256.h
+++ b/include/sha256.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,14 +13,30 @@
 #define SHA256_DIGEST_SIZE 32
 #define SHA256_BLOCK_SIZE 64
 
+#ifdef CONFIG_PLATFORM_EC_SHA256_HW_ZEPHYR
+/*
+ * The chip's header file must implement the SHA256 context structure and
+ * specific functions for its hardware accelerator module.
+ */
+#include "sha256_hw.h"
+#else
+#ifdef CONFIG_SHA256_HW_ACCELERATE
+/*
+ * The chip's header file must implement the SHA256 context structure and
+ * specific functions for its hardware accelerator module.
+ */
+#include "sha256_chip.h"
+#else
 /* SHA256 context */
 struct sha256_ctx {
 	uint32_t h[8];
 	uint32_t tot_len;
 	uint32_t len;
 	uint8_t block[2 * SHA256_BLOCK_SIZE];
-	uint8_t buf[SHA256_DIGEST_SIZE];  /* Used to store the final digest. */
+	uint8_t buf[SHA256_DIGEST_SIZE]; /* Used to store the final digest. */
 };
+#endif
+#endif
 
 void SHA256_init(struct sha256_ctx *ctx);
 void SHA256_update(struct sha256_ctx *ctx, const uint8_t *data, uint32_t len);
@@ -29,4 +45,4 @@ uint8_t *SHA256_final(struct sha256_ctx *ctx);
 void hmac_SHA256(uint8_t *output, const uint8_t *key, const int key_len,
 		 const uint8_t *message, const int message_len);
 
-#endif  /* __CROS_EC_SHA256_H */
+#endif /* __CROS_EC_SHA256_H */
diff --git a/include/shared_mem.h b/include/shared_mem.h
index eadac22a48..b1364c5332 100644
--- a/include/shared_mem.h
+++ b/include/shared_mem.h
@@ -1,4 +1,4 @@
-/* Copyright 2011 The Chromium OS Authors. All rights reserved.
+/* Copyright 2011 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,6 +18,7 @@
 #define __CROS_EC_SHARED_MEM_H
 
 #include "common.h"
+
 #include <stddef.h>
 
 /**
@@ -29,7 +30,7 @@ int shared_mem_size(void);
 #define SHARED_MEM_CHECK_SIZE(size) \
 	BUILD_ASSERT((size) <= CONFIG_SHAREDMEM_MINIMUM_SIZE)
 
-/*
+/**
  * Acquires a shared memory area of the requested size in bytes.
  *
  * Doing a sysjump between images will corrupt and/or erase shared memory as
@@ -46,14 +47,18 @@ int shared_mem_size(void);
  */
 int shared_mem_acquire(int size, char **dest_ptr);
 
-#define SHARED_MEM_ACQUIRE_CHECK(size, dest_ptr) \
-	({ \
-		SHARED_MEM_CHECK_SIZE(size);				\
-		shared_mem_acquire((size), (dest_ptr));			\
+#define SHARED_MEM_ACQUIRE_CHECK(size, dest_ptr)        \
+	({                                              \
+		SHARED_MEM_CHECK_SIZE(size);            \
+		shared_mem_acquire((size), (dest_ptr)); \
 	})
 
 /**
  * Releases a shared memory area previously allocated via shared_mem_acquire().
+ *
+ * @param ptr pointer to previously acquired memory
+ *
+ * @note If ptr is NULL, this is a no-op.
  */
 void shared_mem_release(void *ptr);
 
@@ -85,4 +90,4 @@ extern struct shm_buffer *free_buf_chain;
 extern struct shm_buffer *allocced_buf_chain;
 #endif
 
-#endif  /* __CROS_EC_SHARED_MEM_H */
+#endif /* __CROS_EC_SHARED_MEM_H */
diff --git a/include/software_panic.h b/include/software_panic.h
index 2702c6dc92..ad17e2ea5d 100644
--- a/include/software_panic.h
+++ b/include/software_panic.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,23 +9,24 @@
 #define __CROS_EC_SOFTWARE_PANIC_H
 
 /* Holds software panic reason PANIC_SW_* */
-#define SOFTWARE_PANIC_REASON_REG	r4
-#define SOFTWARE_PANIC_INFO_REG		r5
+#define SOFTWARE_PANIC_REASON_REG r4
+#define SOFTWARE_PANIC_INFO_REG r5
 
-#define PANIC_SW_BASE		0xDEAD6660
+#define PANIC_SW_BASE 0xDEAD6660
 
 /* Software panic reasons */
-#define PANIC_SW_DIV_ZERO		(PANIC_SW_BASE + 0)
-#define PANIC_SW_STACK_OVERFLOW		(PANIC_SW_BASE + 1)
-#define PANIC_SW_PD_CRASH		(PANIC_SW_BASE + 2)
-#define PANIC_SW_ASSERT			(PANIC_SW_BASE + 3)
-#define PANIC_SW_WATCHDOG		(PANIC_SW_BASE + 4)
-#define PANIC_SW_BAD_RNG		(PANIC_SW_BASE + 5)
-#define PANIC_SW_PMIC_FAULT		(PANIC_SW_BASE + 6)
+#define PANIC_SW_DIV_ZERO (PANIC_SW_BASE + 0)
+#define PANIC_SW_STACK_OVERFLOW (PANIC_SW_BASE + 1)
+#define PANIC_SW_PD_CRASH (PANIC_SW_BASE + 2)
+#define PANIC_SW_ASSERT (PANIC_SW_BASE + 3)
+#define PANIC_SW_WATCHDOG (PANIC_SW_BASE + 4)
+#define PANIC_SW_BAD_RNG (PANIC_SW_BASE + 5)
+#define PANIC_SW_PMIC_FAULT (PANIC_SW_BASE + 6)
+#define PANIC_SW_EXIT (PANIC_SW_BASE + 7)
 
 #ifndef __ASSEMBLER__
-extern const char * const panic_sw_reasons[];
+extern const char *const panic_sw_reasons[];
 extern int panic_sw_reason_is_valid(uint32_t vec);
 #endif
 
-#endif  /* __CROS_EC_SOFTWARE_PANIC_H */
+#endif /* __CROS_EC_SOFTWARE_PANIC_H */
diff --git a/include/spi.h b/include/spi.h
index 79ed7474fa..f117098e81 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -32,7 +32,7 @@ enum spi_clock_mode {
 struct spi_device_t {
 	/*
 	 * SPI port the device is connected to.
-	 * On some architecture, this is SPI master port index,
+	 * On some architecture, this is SPI controller port index,
 	 * on other the SPI port index directly.
 	 */
 	uint8_t port;
@@ -45,9 +45,23 @@ struct spi_device_t {
 
 	/* gpio used for chip selection. */
 	enum gpio_signal gpio_cs;
+
+#ifdef CONFIG_USB_SPI
+	/*
+	 * Flags used by usb_spi.c
+	 */
+	uint8_t usb_flags;
+#endif
+
+	/* Port name */
+	const char *name;
 };
 
-extern const struct spi_device_t spi_devices[];
+extern
+#ifndef CONFIG_SPI_MUTABLE_DEVICE_LIST
+	const
+#endif
+	struct spi_device_t spi_devices[];
 extern const unsigned int spi_devices_used;
 
 /*
@@ -61,10 +75,10 @@ extern const unsigned int spi_devices_used;
  * Enable / disable the SPI port.  When the port is disabled, all its I/O lines
  * are high-Z so the EC won't interfere with other devices on the SPI bus.
  *
- * @param port  port id to work on.
- * @param enable  1 to enable the port, 0 to disable it.
+ * @param spi_device device
+ * @param enable  1 to enable the SPI device's port, 0 to disable it.
  */
-int spi_enable(int port, int enable);
+int spi_enable(const struct spi_device_t *spi_device, int enable);
 
 #define SPI_READBACK_ALL (-1)
 
@@ -85,8 +99,8 @@ int spi_enable(int port, int enable);
  * @param rxlen  number of bytes in rxdata or SPI_READBACK_ALL.
  */
 int spi_transaction(const struct spi_device_t *spi_device,
-		    const uint8_t *txdata, int txlen,
-		    uint8_t *rxdata, int rxlen);
+		    const uint8_t *txdata, int txlen, uint8_t *rxdata,
+		    int rxlen);
 
 /*
  * Similar to spi_transaction(), but hands over to DMA for reading response.
@@ -96,8 +110,8 @@ int spi_transaction(const struct spi_device_t *spi_device,
  * SPI port, it's up to the caller to ensure proper mutual exclusion if needed.
  */
 int spi_transaction_async(const struct spi_device_t *spi_device,
-			  const uint8_t *txdata, int txlen,
-			  uint8_t *rxdata, int rxlen);
+			  const uint8_t *txdata, int txlen, uint8_t *rxdata,
+			  int rxlen);
 
 /* Wait for async response received */
 int spi_transaction_flush(const struct spi_device_t *spi_device);
@@ -127,4 +141,4 @@ static inline void spi_event(enum gpio_signal signal)
 
 #endif
 
-#endif  /* __CROS_EC_SPI_H */
+#endif /* __CROS_EC_SPI_H */
diff --git a/include/spi_flash.h b/include/spi_flash.h
index ca3e796fd3..05fe8c098b 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,40 +12,40 @@
 #define SPI_FLASH_SIZE(x) (1 << (x))
 
 /* SPI flash instructions */
-#define SPI_FLASH_WRITE_ENABLE		0x06
-#define SPI_FLASH_WRITE_DISABLE		0x04
-#define SPI_FLASH_READ_SR1		0x05
-#define SPI_FLASH_READ_SR2		0x35
-#define SPI_FLASH_WRITE_SR		0x01
-#define SPI_FLASH_ERASE_4KB		0x20
-#define SPI_FLASH_ERASE_32KB		0x52
-#define SPI_FLASH_ERASE_64KB		0xD8
-#define SPI_FLASH_ERASE_CHIP		0xC7
-#define SPI_FLASH_READ			0x03
-#define SPI_FLASH_PAGE_PRGRM		0x02
-#define SPI_FLASH_REL_PWRDWN		0xAB
-#define SPI_FLASH_MFR_DEV_ID		0x90
-#define SPI_FLASH_JEDEC_ID		0x9F
-#define SPI_FLASH_UNIQUE_ID		0x4B
-#define SPI_FLASH_SFDP			0x44
-#define SPI_FLASH_ERASE_SEC_REG		0x44
-#define SPI_FLASH_PRGRM_SEC_REG		0x42
-#define SPI_FLASH_READ_SEC_REG		0x48
-#define SPI_FLASH_ENABLE_RESET		0x66
-#define SPI_FLASH_RESET			0x99
+#define SPI_FLASH_WRITE_ENABLE 0x06
+#define SPI_FLASH_WRITE_DISABLE 0x04
+#define SPI_FLASH_READ_SR1 0x05
+#define SPI_FLASH_READ_SR2 0x35
+#define SPI_FLASH_WRITE_SR 0x01
+#define SPI_FLASH_ERASE_4KB 0x20
+#define SPI_FLASH_ERASE_32KB 0x52
+#define SPI_FLASH_ERASE_64KB 0xD8
+#define SPI_FLASH_ERASE_CHIP 0xC7
+#define SPI_FLASH_READ 0x03
+#define SPI_FLASH_PAGE_PRGRM 0x02
+#define SPI_FLASH_REL_PWRDWN 0xAB
+#define SPI_FLASH_MFR_DEV_ID 0x90
+#define SPI_FLASH_JEDEC_ID 0x9F
+#define SPI_FLASH_UNIQUE_ID 0x4B
+#define SPI_FLASH_SFDP 0x44
+#define SPI_FLASH_ERASE_SEC_REG 0x44
+#define SPI_FLASH_PRGRM_SEC_REG 0x42
+#define SPI_FLASH_READ_SEC_REG 0x48
+#define SPI_FLASH_ENABLE_RESET 0x66
+#define SPI_FLASH_RESET 0x99
 
 /* Maximum single write size (in bytes) for the W25Q64FV SPI flash */
-#define SPI_FLASH_MAX_WRITE_SIZE	256
+#define SPI_FLASH_MAX_WRITE_SIZE 256
 
 /*
  * Maximum message size (in bytes) for the W25Q64FV SPI flash
  * Instruction (1) + Address (3) + Data (256) = 260
  * Limited by chip maximum input length of write instruction
  */
-#define SPI_FLASH_MAX_MESSAGE_SIZE	(SPI_FLASH_MAX_WRITE_SIZE + 4)
+#define SPI_FLASH_MAX_MESSAGE_SIZE (SPI_FLASH_MAX_WRITE_SIZE + 4)
 
 /* Maximum single read size in bytes. Limited by size of the message buffer */
-#define SPI_FLASH_MAX_READ_SIZE		(SPI_FLASH_MAX_MESSAGE_SIZE - 4)
+#define SPI_FLASH_MAX_READ_SIZE (SPI_FLASH_MAX_MESSAGE_SIZE - 4)
 
 /* Status register write protect structure */
 enum spi_flash_wp {
@@ -120,7 +120,7 @@ int spi_flash_erase(unsigned int offset, unsigned int bytes);
  * @return EC_SUCCESS, or non-zero if any error.
  */
 int spi_flash_write(unsigned int offset, unsigned int bytes,
-	const uint8_t *data);
+		    const uint8_t *data);
 
 /**
  * Gets the SPI flash JEDEC ID (manufacturer ID, memory type, and capacity)
@@ -185,4 +185,4 @@ int spi_flash_check_protect(unsigned int offset, unsigned int bytes);
  */
 int spi_flash_set_protect(unsigned int offset, unsigned int bytes);
 
-#endif  /* __CROS_EC_SPI_FLASH_H */
+#endif /* __CROS_EC_SPI_FLASH_H */
diff --git a/include/spi_flash_reg.h b/include/spi_flash_reg.h
deleted file mode 100644
index a0ffefc721..0000000000
--- a/include/spi_flash_reg.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * SPI flash protection register translation functions for Chrome OS EC.
- */
-
-#ifndef __CROS_EC_SPI_FLASH_REG_H
-#define __CROS_EC_SPI_FLASH_REG_H
-
-#include "common.h"
-
-/*
- * Common register bits for SPI flash. All registers / bits may not be valid
- * for all parts.
- */
-#define SPI_FLASH_SR2_SUS               BIT(7)
-#define SPI_FLASH_SR2_CMP               BIT(6)
-#define SPI_FLASH_SR2_LB3               BIT(5)
-#define SPI_FLASH_SR2_LB2               BIT(4)
-#define SPI_FLASH_SR2_LB1               BIT(3)
-#define SPI_FLASH_SR2_QE                BIT(1)
-#define SPI_FLASH_SR2_SRP1              BIT(0)
-#define SPI_FLASH_SR1_SRP0              BIT(7)
-#define SPI_FLASH_SR1_SEC               BIT(6)
-#define SPI_FLASH_SR1_TB                BIT(5)
-#define SPI_FLASH_SR1_BP2               BIT(4)
-#define SPI_FLASH_SR1_BP1               BIT(3)
-#define SPI_FLASH_SR1_BP0               BIT(2)
-#define SPI_FLASH_SR1_WEL               BIT(1)
-#define SPI_FLASH_SR1_BUSY              BIT(0)
-
-/* SR2 register existence based upon chip */
-#ifdef CONFIG_SPI_FLASH_W25X40
-#undef CONFIG_SPI_FLASH_HAS_SR2
-#elif defined(CONFIG_SPI_FLASH_W25Q64) || defined(CONFIG_SPI_FLASH_GD25Q41B)
-#define CONFIG_SPI_FLASH_HAS_SR2
-#endif
-
-/* W25Q128 16 Mbyte SPI flash for testing */
-#ifdef CONFIG_SPI_FLASH_W25Q128
-#define CONFIG_SPI_FLASH_HAS_SR2
-#endif
-
-/**
- * Computes block write protection range from registers
- * Returns start == len == 0 for no protection
- *
- * @param sr1 Status register 1
- * @param sr2 Status register 2
- * @param start Output pointer for protection start offset
- * @param len Output pointer for protection length
- *
- * @return EC_SUCCESS, or non-zero if any error.
- */
-int spi_flash_reg_to_protect(uint8_t sr1, uint8_t sr2, unsigned int *start,
-			     unsigned int *len);
-
-/**
- * Computes block write protection registers from range
- *
- * @param start Desired protection start offset
- * @param len Desired protection length
- * @param sr1 Output pointer for status register 1
- * @param sr2 Output pointer for status register 2
- *
- * @return EC_SUCCESS, or non-zero if any error.
- */
-int spi_flash_protect_to_reg(unsigned int start, unsigned int len, uint8_t *sr1,
-			     uint8_t *sr2);
-
-#endif  /* __CROS_EC_SPI_FLASH_REG_H */
diff --git a/include/spi_nor.h b/include/spi_nor.h
index 77347399d7..9ffe3ebac9 100644
--- a/include/spi_nor.h
+++ b/include/spi_nor.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -41,8 +41,10 @@ struct spi_nor_device_t {
 	/* Name of the Serial NOR Flash device. */
 	const char *name;
 
-	/* Index of the SPI master which this device is connected through. */
-	const enum spi_device spi_master;
+	/* Index of the SPI controller which this device is connected
+	 * through.
+	 */
+	const enum spi_device spi_controller;
 
 	/* Maximum timeout per command in microseconds. */
 	const uint32_t timeout_usec;
@@ -61,32 +63,32 @@ extern const unsigned int spi_nor_devices_used;
 
 /* Industry standard Serial NOR Flash opcodes. All other opcodes are part
  * specific and require SFDP discovery. */
-#define SPI_NOR_OPCODE_WRITE_STATUS  0x01 /* Write Status Register (1 Byte) */
-#define SPI_NOR_OPCODE_PAGE_PROGRAM  0x02 /* Page program */
-#define SPI_NOR_OPCODE_SLOW_READ     0x03 /* Read data (low frequency) */
+#define SPI_NOR_OPCODE_WRITE_STATUS 0x01 /* Write Status Register (1 Byte) */
+#define SPI_NOR_OPCODE_PAGE_PROGRAM 0x02 /* Page program */
+#define SPI_NOR_OPCODE_SLOW_READ 0x03 /* Read data (low frequency) */
 #define SPI_NOR_OPCODE_WRITE_DISABLE 0x04
-#define SPI_NOR_OPCODE_READ_STATUS   0x05 /* Read Status Register */
-#define SPI_NOR_OPCODE_WRITE_ENABLE  0x06
-#define SPI_NOR_OPCODE_FAST_READ     0x0b /* Read data (high frequency) */
-#define SPI_NOR_OPCODE_SFDP          0x5a /* Read JEDEC SFDP */
-#define SPI_NOR_OPCODE_JEDEC_ID      0x9f /* Read JEDEC ID */
-#define SPI_NOR_OPCODE_WREAR         0xc5 /* Write extended address register */
-#define SPI_NOR_OPCODE_CHIP_ERASE    0xc7 /* Erase whole flash chip */
-#define SPI_NOR_OPCODE_RDEAR         0xc8 /* Read extended address register */
+#define SPI_NOR_OPCODE_READ_STATUS 0x05 /* Read Status Register */
+#define SPI_NOR_OPCODE_WRITE_ENABLE 0x06
+#define SPI_NOR_OPCODE_FAST_READ 0x0b /* Read data (high frequency) */
+#define SPI_NOR_OPCODE_SFDP 0x5a /* Read JEDEC SFDP */
+#define SPI_NOR_OPCODE_JEDEC_ID 0x9f /* Read JEDEC ID */
+#define SPI_NOR_OPCODE_WREAR 0xc5 /* Write extended address register */
+#define SPI_NOR_OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */
+#define SPI_NOR_OPCODE_RDEAR 0xc8 /* Read extended address register */
 
 /* Flags for SPI_NOR_OPCODE_READ_STATUS */
-#define SPI_NOR_STATUS_REGISTER_WIP BIT(0)  /* Write in progres */
-#define SPI_NOR_STATUS_REGISTER_WEL BIT(1)  /* Write enabled latch */
+#define SPI_NOR_STATUS_REGISTER_WIP BIT(0) /* Write in progres */
+#define SPI_NOR_STATUS_REGISTER_WEL BIT(1) /* Write enabled latch */
 
 /* If needed in the future this driver can be extended to discover SFDP
  * advertised erase sizes and opcodes for SFDP v1.0+. */
-#define SPI_NOR_DRIVER_SPECIFIED_OPCODE_4KIB_ERASE  0x20
+#define SPI_NOR_DRIVER_SPECIFIED_OPCODE_4KIB_ERASE 0x20
 #define SPI_NOR_DRIVER_SPECIFIED_OPCODE_64KIB_ERASE 0xd8
 
 /* If needed in the future this driver can be extended to discover 4B entry and
  * exit methods for SFDP v1.5+. */
 #define SPI_NOR_DRIVER_SPECIFIED_OPCODE_ENTER_4B 0xb7
-#define SPI_NOR_DRIVER_SPECIFIED_OPCODE_EXIT_4B  0xe9
+#define SPI_NOR_DRIVER_SPECIFIED_OPCODE_EXIT_4B 0xe9
 
 /* JEDEC JEP106AR specifies 9 Manufacturer ID banks, read 12 to be sure. */
 #define SPI_NOR_JEDEC_ID_BANKS 12
@@ -109,9 +111,9 @@ int spi_nor_init(void);
  *
  * WARNING:
  * 1) In 3 Byte addressing mode only 16MiB of Serial NOR Flash is accessible.
- * 2) If there's a second SPI master communicating with this Serial NOR Flash
- *    part on the board, the user is responsible for ensuring addressing mode
- *    compatibility and cooperation.
+ * 2) If there's a second SPI controller communicating with this Serial
+ *    NOR Flash part on the board, the user is responsible for ensuring
+ *    addressing mode compatibility and cooperation.
  * 3) The user must ensure that multiple users do not trample on each other
  *    by having multiple parties changing the device's addressing mode.
  *
@@ -142,8 +144,8 @@ int spi_nor_read_jedec_id(const struct spi_nor_device_t *spi_nor_device,
  * @param data Destination buffer for data.
  * @return ec_error_list (non-zero on error and timeout).
  */
-int spi_nor_read(const struct spi_nor_device_t *spi_nor_device,
-		 uint32_t offset, size_t size, uint8_t *data);
+int spi_nor_read(const struct spi_nor_device_t *spi_nor_device, uint32_t offset,
+		 size_t size, uint8_t *data);
 
 /**
  * Erase flash on the Serial Flash Device.
@@ -179,5 +181,4 @@ int spi_nor_write(const struct spi_nor_device_t *spi_nor_device,
 int spi_nor_write_ear(const struct spi_nor_device_t *spi_nor_device,
 		      const uint8_t value);
 
-
-#endif  /* __CROS_EC_SPI_NOR_H */
+#endif /* __CROS_EC_SPI_NOR_H */
diff --git a/include/stack_trace.h b/include/stack_trace.h
index 52ebe3619f..90d20519b9 100644
--- a/include/stack_trace.h
+++ b/include/stack_trace.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,8 +18,12 @@ void task_register_tracedump(void);
 /* Dump current stack trace */
 void task_dump_trace(void);
 #else
-static inline void task_register_tracedump(void) { }
-static inline void task_dump_trace(void) { }
+static inline void task_register_tracedump(void)
+{
+}
+static inline void task_dump_trace(void)
+{
+}
 #endif
 
-#endif  /* __CROS_EC_STACK_TRACE_H */
+#endif /* __CROS_EC_STACK_TRACE_H */
diff --git a/include/stillness_detector.h b/include/stillness_detector.h
index 65598d4d5c..67269c6db4 100644
--- a/include/stillness_detector.h
+++ b/include/stillness_detector.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,6 +9,7 @@
 #include "common.h"
 #include "math_util.h"
 #include "stdbool.h"
+
 #include <stdint.h>
 
 struct still_det {
diff --git a/include/switch.h b/include/switch.h
index e026408af9..97d428e356 100644
--- a/include/switch.h
+++ b/include/switch.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,7 +19,9 @@
  */
 void switch_interrupt(enum gpio_signal signal);
 #else
-static inline void switch_interrupt(enum gpio_signal signal) { }
-#endif  /* !CONFIG_SWITCH */
+static inline void switch_interrupt(enum gpio_signal signal)
+{
+}
+#endif /* !CONFIG_SWITCH */
 
-#endif  /* __CROS_EC_SWITCH_H */
+#endif /* __CROS_EC_SWITCH_H */
diff --git a/include/sysjump.h b/include/sysjump.h
index 0b0bb0ec6b..b7779b9c86 100644
--- a/include/sysjump.h
+++ b/include/sysjump.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,10 +16,20 @@
  * images.
  */
 
-#define JUMP_DATA_MAGIC 0x706d754a  /* "Jump" */
+#define JUMP_DATA_MAGIC 0x706d754a /* "Jump" */
 #define JUMP_DATA_VERSION 3
-#define JUMP_DATA_SIZE_V1 12  /* Size of version 1 jump data struct */
-#define JUMP_DATA_SIZE_V2 16  /* Size of version 2 jump data struct */
+#define JUMP_DATA_SIZE_V1 12 /* Size of version 1 jump data struct */
+#define JUMP_DATA_SIZE_V2 16 /* Size of version 2 jump data struct */
+
+#define JUMP_TAG_MAX_SIZE 255
+
+#if !defined(CONFIG_RAM_SIZE) || !(CONFIG_RAM_SIZE > 0)
+/* Disable check by setting jump data min address to zero */
+#define JUMP_DATA_MIN_ADDRESS 0
+#else
+#define JUMP_DATA_MIN_ADDRESS \
+	(CONFIG_RAM_BASE + CONFIG_RAM_SIZE - CONFIG_PRESERVED_END_OF_RAM_SIZE)
+#endif
 
 struct jump_data {
 	/*
@@ -29,19 +39,24 @@ struct jump_data {
 	 */
 
 	/* Fields from version 3 */
-	uint8_t reserved0;    /* (used in proto1 to signal recovery mode) */
-	int struct_size;      /* Size of struct jump_data */
+	uint8_t reserved0; /* (used in proto1 to signal recovery mode) */
+	int struct_size; /* Size of struct jump_data */
 
 	/* Fields from version 2 */
-	int jump_tag_total;   /* Total size of all jump tags */
+	int jump_tag_total; /* Total size of all jump tags */
 
 	/* Fields from version 1 */
 	uint32_t reset_flags; /* Reset flags from the previous boot */
-	int version;          /* Version (JUMP_DATA_VERSION) */
-	int magic;            /* Magic number (JUMP_DATA_MAGIC).  If this
-			       * doesn't match at pre-init time, assume no valid
-			       * data from the previous image.
-			       */
+	int version; /* Version (JUMP_DATA_VERSION) */
+	int magic; /* Magic number (JUMP_DATA_MAGIC).  If this
+		    * doesn't match at pre-init time, assume no valid
+		    * data from the previous image.
+		    */
 };
 
-#endif  /* __CROS_EC_SYSJUMP_IMPL_H */
+/**
+ * Returns a pointer to the jump data structure.
+ */
+struct jump_data *get_jump_data(void);
+
+#endif /* __CROS_EC_SYSJUMP_IMPL_H */
diff --git a/include/system.h b/include/system.h
index d14f382ee1..25cf0c4bcc 100644
--- a/include/system.h
+++ b/include/system.h
@@ -1,15 +1,19 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* System module for Chrome EC */
 
+/*
+ * TODO(b/272518464): Work around coreboot GCC preprocessor bug.
+ * #line marks the *next* line, so it is off by one.
+ */
+#line 13
+
 #ifndef __CROS_EC_SYSTEM_H
 #define __CROS_EC_SYSTEM_H
 
-#include <stdnoreturn.h>
-
 #include "atomic.h"
 #include "common.h"
 #include "compile_time_macros.h"
@@ -17,6 +21,24 @@
 #include "ec_commands.h"
 #include "timer.h"
 
+#include <stdnoreturn.h>
+
+#ifdef CONFIG_ZEPHYR
+#ifdef CONFIG_CPU_CORTEX_M
+/*
+ * For cortex-m we cannot use irq_lock() for disabling all the interrupts
+ * because it leaves some (NMI and faults) still enabled.
+ */
+#define interrupt_disable_all() __asm__("cpsid i")
+#elif CONFIG_ZTEST
+#define interrupt_disable_all()
+#else /* !CONFIG_CPU_CORTEX_M */
+#define interrupt_disable_all() irq_lock()
+#endif
+#else /* !CONFIG_ZEPHYR */
+#define interrupt_disable_all() interrupt_disable()
+#endif /* CONFIG_ZEPHYR */
+
 /* Per chip implementation to save/read raw EC_RESET_FLAG_ flags. */
 void chip_save_reset_flags(uint32_t flags);
 uint32_t chip_read_reset_flags(void);
@@ -47,6 +69,24 @@ void system_common_pre_init(void);
  */
 int system_is_manual_recovery(void);
 
+/**
+ * Set a flag indicating system is in recovery mode.
+ */
+void system_enter_manual_recovery(void);
+
+/**
+ * Set a flag indicating system left recovery mode.
+ *
+ * WARNING: This flag should be cleared right after a shutdown from recovery
+ *          boot. You most likely shouldn't call this elsewhere.
+ */
+void system_exit_manual_recovery(void);
+
+/**
+ * Make sure AP shutdown completely, before call system_hibernate
+ */
+void system_enter_hibernate(uint32_t seconds, uint32_t microseconds);
+
 /**
  * System common re-initialization; called to reset persistent state
  * left by system_common_pre_init().  This is useful for testing
@@ -54,13 +94,30 @@ int system_is_manual_recovery(void);
  */
 __test_only void system_common_reset_state(void);
 
+/**
+ * Return the value of reboot_at_shutdown and reset its value, useful for
+ * testing.
+ */
+__test_only enum ec_reboot_cmd system_common_get_reset_reboot_at_shutdown(void);
+
+/**
+ * @brief Allow tests to manually set the jump data address.
+ *
+ * This function allows an override of the location of the jump data (which is
+ * normally set by either a panic or at the end of RAM). This function is used
+ * by the zephyr integration to test the shim layer of the system module.
+ *
+ * @param test_jdata Pointer to the jump data memory allocated by the test.
+ */
+__test_only void system_override_jdata(void *test_jdata);
+
 /**
  * Set up flags that should be saved to battery backed RAM.
  *
- * @param reset_flags - flags passed into system_reset
+ * @param flags - flags passed into system_reset (i.e. SYSTEM_RESET_*)
  * @param *save_flags - flags to be saved in battery backed RAM
  */
-void system_encode_save_flags(int reset_flags, uint32_t *save_flags);
+void system_encode_save_flags(int flags, uint32_t *save_flags);
 
 /**
  * Get the reset flags.
@@ -88,6 +145,11 @@ void system_clear_reset_flags(uint32_t flags);
  */
 void system_print_reset_flags(void);
 
+/**
+ * Print a banner at boot, including image type, version, and reset type
+ */
+void system_print_banner(void);
+
 /**
  * Check if system is locked down for normal consumer use.
  *
@@ -135,6 +197,14 @@ uintptr_t get_program_memory_addr(enum ec_image copy);
  */
 int system_jumped_to_this_image(void);
 
+#ifdef CONFIG_ZTEST
+struct system_jumped_late_mock {
+	int ret_val;
+	int call_count;
+};
+extern struct system_jumped_late_mock system_jumped_late_mock;
+#endif
+
 /**
  * Return non-zero if late (legacy) sysjump occurred.
  *
@@ -150,7 +220,7 @@ int system_jumped_late(void);
  * This may ONLY be called from within a HOOK_SYSJUMP handler.
  *
  * @param tag		Data type
- * @param size          Size of data; must be less than 255 bytes.
+ * @param size          Size of data; must be less than JUMP_TAG_MAX_SIZE bytes.
  * @param version       Data version, so that tag data can evolve as firmware
  *			is updated.
  * @param data		Pointer to data to save
@@ -235,6 +305,15 @@ const struct image_data *system_get_image_data(enum ec_image copy);
  */
 const char *system_get_version(enum ec_image copy);
 
+/**
+ * Get the CrOS fwid string for an image
+ *
+ * @param copy		Image copy to get version from, or SYSTEM_IMAGE_UNKNOWN
+ *			to get the version for the currently running image.
+ * @return The fwid string for the image copy, or an empty string if error.
+ */
+const char *system_get_cros_fwid(enum ec_image copy);
+
 /**
  * Get the SKU ID for a device
  *
@@ -261,17 +340,17 @@ const char *system_get_build_info(void);
  * Hard reset.  Cuts power to the entire system.  If not present, does a soft
  * reset which just resets the core and on-chip peripherals.
  */
-#define SYSTEM_RESET_HARD               BIT(0)
+#define SYSTEM_RESET_HARD BIT(0)
 /*
  * Preserve existing reset flags.  Used by flash pre-init when it discovers it
  * needs to do a hard reset to clear write protect registers.
  */
-#define SYSTEM_RESET_PRESERVE_FLAGS     BIT(1)
+#define SYSTEM_RESET_PRESERVE_FLAGS BIT(1)
 /*
  * Leave AP off on next reboot, instead of powering it on to do EC software
  * sync.
  */
-#define SYSTEM_RESET_LEAVE_AP_OFF       BIT(2)
+#define SYSTEM_RESET_LEAVE_AP_OFF BIT(2)
 /*
  * Indicate that this was a manually triggered reset.
  */
@@ -279,25 +358,34 @@ const char *system_get_build_info(void);
 /*
  * Wait for reset pin to be driven, rather that resetting ourselves.
  */
-#define SYSTEM_RESET_WAIT_EXT           BIT(4)
+#define SYSTEM_RESET_WAIT_EXT BIT(4)
 /*
  * Indicate that this reset was triggered by an AP watchdog
  */
-#define SYSTEM_RESET_AP_WATCHDOG        BIT(5)
+#define SYSTEM_RESET_AP_WATCHDOG BIT(5)
 /*
  * Stay in RO next reboot, instead of potentially selecting RW during EFS.
  */
-#define SYSTEM_RESET_STAY_IN_RO         BIT(6)
+#define SYSTEM_RESET_STAY_IN_RO BIT(6)
+/*
+ * Hibernate reset. Reset EC when wake up from hibernate mode
+ * (the most power saving mode).
+ */
+#define SYSTEM_RESET_HIBERNATE BIT(7)
 
 /**
  * Reset the system.
  *
  * @param flags		Reset flags; see SYSTEM_RESET_* above.
  */
-#ifndef TEST_FUZZ
+#if !(defined(TEST_FUZZ) || defined(CONFIG_ZTEST))
+#if defined(__cplusplus) && !defined(__clang__)
+[[noreturn]]
+#else
 noreturn
 #endif
-void system_reset(int flags);
+#endif
+	void system_reset(int flags);
 
 /**
  * Set a scratchpad register to the specified value.
@@ -311,9 +399,15 @@ void system_reset(int flags);
 int system_set_scratchpad(uint32_t value);
 
 /**
- * Return the current scratchpad register value.
+ * Get the scratchpad register value.
+ *
+ * The scratchpad register maintains its contents across a
+ * software-requested warm reset.
+ *
+ * @param value Where to store the content of the register.
+ * @return      EC_SUCCESS, or non-zero if error.
  */
-uint32_t system_get_scratchpad(void);
+int system_get_scratchpad(uint32_t *value);
 
 /**
  * Return the chip vendor/name/revision string.
@@ -331,6 +425,25 @@ const char *system_get_chip_revision(void);
  */
 int system_get_chip_unique_id(uint8_t **id);
 
+/**
+ * Optional board-level function to read SKU ID.
+ */
+__override_proto uint32_t board_get_sku_id(void);
+
+/**
+ * Optional board-level function to read board version.
+ */
+__override_proto int board_get_version(void);
+
+/**
+ * Optional board-level function to pulse EC_ENTERING_RW.
+ *
+ * This should ONLY be overridden in very rare circumstances! AKA there better
+ * be a good reason why you're overriding this!
+ * The function ***MUST*** assert EC_ENTERING_RW for 1ms and then deassert it.
+ */
+__override_proto void board_pulse_entering_rw(void);
+
 /**
  * Optional board-level callback functions to read a unique serial number per
  * chip. Default implementation reads from flash/otp (flash/otp_read_serial).
@@ -343,7 +456,6 @@ __override_proto const char *board_read_serial(void);
  */
 __override_proto int board_write_serial(const char *serial);
 
-
 /**
  * Optional board-level callback functions to read a unique MAC address per
  * chip. Default implementation reads from flash.
@@ -362,18 +474,21 @@ __override_proto int board_write_mac_addr(const char *mac_addr);
  * not implemented.
  */
 enum system_bbram_idx {
-	SYSTEM_BBRAM_IDX_VBNVBLOCK0 = 0,
-	/*
-	 * ...
-	 * 16 total bytes of VB NVRAM.
-	 * ...
-	 */
-	SYSTEM_BBRAM_IDX_VBNVBLOCK15 = 15,
 	/* PD state for CONFIG_USB_PD_DUAL_ROLE uses one byte per port */
 	SYSTEM_BBRAM_IDX_PD0,
 	SYSTEM_BBRAM_IDX_PD1,
 	SYSTEM_BBRAM_IDX_PD2,
 	SYSTEM_BBRAM_IDX_TRY_SLOT,
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+	SYSTEM_BBRAM_IDX_CHARGE_LIMIT_MAX,
+	SYSTEM_BBRAM_IDX_FP_LED_LEVEL,
+	SYSTEM_BBRAM_IDX_KBSTATE,
+	SYSTEM_BBRAM_IDX_BIOS_FUNCTION,
+	SYSTEM_BBRAM_IDX_CHASSIS_WAS_OPEN,
+	SYSTEM_BBRAM_IDX_CHASSIS_MAGIC,
+	SYSTEM_BBRAM_IDX_CHASSIS_TOTAL,
+	SYSTEM_BBRAM_IDX_CHASSIS_VTR_OPEN,
+#endif
 };
 
 /* Maximum number of bbram indexes allotted for PD port state data */
@@ -435,7 +550,9 @@ timestamp_t system_get_rtc(void);
 #ifdef CONFIG_RTC
 void print_system_rtc(enum console_channel channel);
 #else
-static inline void print_system_rtc(enum console_channel channel) { }
+static inline void print_system_rtc(enum console_channel channel)
+{
+}
 #endif /* !defined(CONFIG_RTC) */
 
 /**
@@ -448,39 +565,38 @@ enum {
 	/*
 	 * Sleep masks to prevent going in to deep sleep.
 	 */
-	SLEEP_MASK_AP_RUN     = BIT(0), /* the main CPU is running */
-	SLEEP_MASK_UART       = BIT(1), /* UART communication ongoing */
-	SLEEP_MASK_I2C_MASTER = BIT(2), /* I2C master communication ongoing */
-	SLEEP_MASK_CHARGING   = BIT(3), /* Charging loop ongoing */
-	SLEEP_MASK_USB_PWR    = BIT(4), /* USB power loop ongoing */
-	SLEEP_MASK_USB_PD     = BIT(5), /* USB PD device connected */
-	SLEEP_MASK_SPI        = BIT(6), /* SPI communications ongoing */
-	SLEEP_MASK_I2C_SLAVE  = BIT(7), /* I2C slave communication ongoing */
-	SLEEP_MASK_FAN        = BIT(8), /* Fan control loop ongoing */
+	SLEEP_MASK_AP_RUN = BIT(0), /* the main CPU is running */
+	SLEEP_MASK_UART = BIT(1), /* UART communication ongoing */
+	SLEEP_MASK_I2C_CONTROLLER = BIT(2), /* I2C controller comms ongoing */
+	SLEEP_MASK_CHARGING = BIT(3), /* Charging loop ongoing */
+	SLEEP_MASK_USB_PWR = BIT(4), /* USB power loop ongoing */
+	SLEEP_MASK_USB_PD = BIT(5), /* USB PD device connected */
+	SLEEP_MASK_SPI = BIT(6), /* SPI communications ongoing */
+	SLEEP_MASK_I2C_PERIPHERAL = BIT(7), /* I2C peripheral comms ongoing */
+	SLEEP_MASK_FAN = BIT(8), /* Fan control loop ongoing */
 	SLEEP_MASK_USB_DEVICE = BIT(9), /* Generic USB device in use */
-	SLEEP_MASK_PWM        = BIT(10), /* PWM output is enabled */
-	SLEEP_MASK_PHYSICAL_PRESENCE  = BIT(11), /* Physical presence
-						    * detection ongoing */
-	SLEEP_MASK_PLL        = BIT(12), /* High-speed PLL in-use */
-	SLEEP_MASK_ADC        = BIT(13), /* ADC conversion ongoing */
-	SLEEP_MASK_EMMC       = BIT(14), /* eMMC emulation ongoing */
-	SLEEP_MASK_FORCE_NO_DSLEEP    = BIT(15), /* Force disable. */
-
+	SLEEP_MASK_PWM = BIT(10), /* PWM output is enabled */
+	SLEEP_MASK_PHYSICAL_PRESENCE = BIT(11), /* Physical presence
+						 * detection ongoing */
+	SLEEP_MASK_PLL = BIT(12), /* High-speed PLL in-use */
+	SLEEP_MASK_ADC = BIT(13), /* ADC conversion ongoing */
+	SLEEP_MASK_EMMC = BIT(14), /* eMMC emulation ongoing */
+	SLEEP_MASK_FORCE_NO_DSLEEP = BIT(15), /* Force disable. */
 
 	/*
 	 * Sleep masks to prevent using slow speed clock in deep sleep.
 	 */
-	SLEEP_MASK_JTAG     = BIT(16), /* JTAG is in use. */
-	SLEEP_MASK_CONSOLE  = BIT(17), /* Console is in use. */
+	SLEEP_MASK_JTAG = BIT(16), /* JTAG is in use. */
+	SLEEP_MASK_CONSOLE = BIT(17), /* Console is in use. */
 
-	SLEEP_MASK_FORCE_NO_LOW_SPEED = BIT(31)  /* Force disable. */
+	SLEEP_MASK_FORCE_NO_LOW_SPEED = BIT(31) /* Force disable. */
 };
 
 /*
  * Current sleep mask. You may read from this variable, but must NOT
  * modify it; use enable_sleep() or disable_sleep() to do that.
  */
-extern uint32_t sleep_mask;
+extern atomic_t sleep_mask;
 
 /*
  * Macros to use to get whether deep sleep is allowed or whether
@@ -488,10 +604,9 @@ extern uint32_t sleep_mask;
  */
 
 #ifndef CONFIG_LOW_POWER_S0
-#define DEEP_SLEEP_ALLOWED           (!(sleep_mask & 0x0000ffff))
+#define DEEP_SLEEP_ALLOWED (!(sleep_mask & 0x0000ffff))
 #else
-#define DEEP_SLEEP_ALLOWED           (!(sleep_mask & 0x0000ffff & \
-				       (~SLEEP_MASK_AP_RUN)))
+#define DEEP_SLEEP_ALLOWED (!(sleep_mask & 0x0000ffff & (~SLEEP_MASK_AP_RUN)))
 #endif
 #define LOW_SPEED_DEEP_SLEEP_ALLOWED (!(sleep_mask & 0xffff0000))
 
@@ -503,7 +618,7 @@ extern uint32_t sleep_mask;
  */
 static inline void enable_sleep(uint32_t mask)
 {
-	deprecated_atomic_clear_bits(&sleep_mask, mask);
+	atomic_clear_bits(&sleep_mask, mask);
 }
 
 /**
@@ -514,7 +629,7 @@ static inline void enable_sleep(uint32_t mask)
  */
 static inline void disable_sleep(uint32_t mask)
 {
-	deprecated_atomic_or(&sleep_mask, mask);
+	atomic_or(&sleep_mask, mask);
 }
 
 #ifdef CONFIG_LOW_POWER_IDLE_LIMITED
@@ -523,7 +638,7 @@ static inline void disable_sleep(uint32_t mask)
  * Do NOT access it directly. Use idle_is_disabled() to read it and
  * enable_idle()/disable_idle() to write it.
  */
-extern uint32_t idle_disabled;
+extern atomic_t idle_disabled;
 
 static inline uint32_t idle_is_disabled(void)
 {
@@ -532,12 +647,12 @@ static inline uint32_t idle_is_disabled(void)
 
 static inline void disable_idle(void)
 {
-	deprecated_atomic_or(&idle_disabled, 1);
+	atomic_or(&idle_disabled, 1);
 }
 
 static inline void enable_idle(void)
 {
-	deprecated_atomic_clear_bits(&idle_disabled, 1);
+	atomic_clear_bits(&idle_disabled, 1);
 }
 #endif
 
@@ -559,6 +674,13 @@ void delay_sleep_by(uint32_t us);
 void disable_deep_sleep(void);
 void enable_deep_sleep(void);
 
+/**
+ * This function is made visible for tests only, it allows overriding the RTC.
+ *
+ * @param seconds
+ */
+void system_set_rtc(uint32_t seconds);
+
 /**
  * Use hibernate module to set up an RTC interrupt at a given
  * time from now
@@ -666,4 +788,9 @@ int system_set_active_copy(enum ec_image copy);
  */
 uint32_t flash_get_rw_offset(enum ec_image copy);
 
-#endif  /* __CROS_EC_SYSTEM_H */
+/**
+ * Compensate for the RTC after hibernation wake-up.
+ */
+void system_compensate_rtc(void);
+
+#endif /* __CROS_EC_SYSTEM_H */
diff --git a/include/system_boot_time.h b/include/system_boot_time.h
new file mode 100644
index 0000000000..e57d73d2d7
--- /dev/null
+++ b/include/system_boot_time.h
@@ -0,0 +1,18 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_SYSTEM_BOOT_TIME_H
+#define __CROS_EC_SYSTEM_BOOT_TIME_H
+
+#include "ec_commands.h"
+
+/**
+ * Updates ap boot time data.
+ *
+ * @param boot time param needs to be updated
+ */
+void update_ap_boot_time(enum boot_time_param param);
+
+#endif /* __CROS_EC_SYSTEM_BOOT_TIME_H */
diff --git a/include/system_safe_mode.h b/include/system_safe_mode.h
new file mode 100644
index 0000000000..766d0535af
--- /dev/null
+++ b/include/system_safe_mode.h
@@ -0,0 +1,61 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_SYSTEM_SAFE_MODE_H
+#define __CROS_EC_SYSTEM_SAFE_MODE_H
+
+#include "task.h"
+
+/**
+ * Checks if running in system safe mode
+ *
+ * @return True if system is running in system safe mode
+ */
+bool system_is_in_safe_mode(void);
+
+/**
+ * Checks if command is allowed in system safe mode
+ *
+ * @return True if command is allowed in system safe mode
+ */
+bool command_is_allowed_in_safe_mode(int command);
+
+/**
+ * Checks if a task is critical for system safe mode
+ *
+ * @return True if task is safe mode critical
+ */
+bool is_task_safe_mode_critical(task_id_t task_id);
+
+/**
+ * Disables tasks that are not critical for safe mode
+ *
+ * @return EC_SUCCESS or EC_xxx on error
+ */
+int disable_non_safe_mode_critical_tasks(void);
+
+/**
+ * Start system safe mode.
+ *
+ * System safe mode can only be started after a panic in RW image.
+ * It will only run briefly so the AP can capture EC state.
+ *
+ * @return EC_SUCCESS or EC_xxx on error
+ */
+int start_system_safe_mode(void);
+
+/**
+ * This handler is called when safe mode times out.
+ */
+void handle_system_safe_mode_timeout(void);
+
+#ifdef TEST_BUILD
+/**
+ * Directly set safe mode flag. Only used in tests.
+ */
+void set_system_safe_mode(bool mode);
+#endif
+
+#endif /* __CROS_EC_SYSTEM_SAFE_MODE_H */
diff --git a/include/tablet_mode.h b/include/tablet_mode.h
index b5a2f2f562..e257fedc04 100644
--- a/include/tablet_mode.h
+++ b/include/tablet_mode.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,12 +13,17 @@
  */
 int tablet_get_mode(void);
 
+/* Bit mask of tablet mode trigger */
+#define TABLET_TRIGGER_LID BIT(0)
+#define TABLET_TRIGGER_BASE BIT(1)
+
 /**
  * Set tablet mode state
  *
  * @param mode 1: tablet mode. 0 clamshell mode.
+ * @param trigger: bitmask of the trigger, TABLET_TRIGGER_*.
  */
-void tablet_set_mode(int mode);
+void tablet_set_mode(int mode, uint32_t trigger);
 
 /**
  * Disable tablet mode
@@ -28,7 +33,7 @@ void tablet_disable(void);
 /**
  * Interrupt service routine for gmr sensor.
  *
- * GMR_TABLET_MODE_GPIO_L must be defined.
+ * GPIO_TABLET_MODE_L must be defined.
  *
  * @param signal: GPIO signal
  */
@@ -45,10 +50,13 @@ void gmr_tablet_switch_disable(void);
 /**
  * This must be defined when CONFIG_GMR_TABLET_MODE_CUSTOM is defined. This
  * allows a board to override the default behavior that determines if the
- * 360 sensor is active: !gpio_get_level(GMR_TABLET_MODE_GPIO_L).
+ * 360 sensor is active: !gpio_get_level(GPIO_TABLET_MODE_L).
  *
  * Returns 1 if the 360 sensor is active; otherwise 0.
  */
 int board_sensor_at_360(void);
 
-#endif  /* __CROS_EC_TABLET_MODE_H */
+/** Reset internal tablet mode state, used for testing. */
+__test_only void tablet_reset(void);
+
+#endif /* __CROS_EC_TABLET_MODE_H */
diff --git a/include/task.h b/include/task.h
index 0b244a2a18..72d09e0ddd 100644
--- a/include/task.h
+++ b/include/task.h
@@ -1,17 +1,30 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Task scheduling / events module for Chrome EC operating system */
 
+/*
+ * TODO(b/272518464): Work around coreboot GCC preprocessor bug.
+ * #line marks the *next* line, so it is off by one.
+ */
+#line 13
+
 #ifndef __CROS_EC_TASK_H
 #define __CROS_EC_TASK_H
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "atomic_t.h"
 #include "common.h"
 #include "compile_time_macros.h"
 #include "task_id.h"
 
+#include <stdbool.h>
+
 /* Task event bitmasks */
 /* Tasks may use the bits in TASK_EVENT_CUSTOM_BIT for their own events */
 #define TASK_EVENT_CUSTOM_BIT(x) BUILD_CHECK_INLINE(BIT(x), BIT(x) & 0x0ffff)
@@ -20,48 +33,47 @@
 #define TASK_EVENT_SYSJUMP_READY BIT(16)
 
 /* Used to signal that IPC layer is available for sending new data */
-#define TASK_EVENT_IPC_READY	BIT(17)
+#define TASK_EVENT_IPC_READY BIT(17)
 
-#define TASK_EVENT_PD_AWAKE	BIT(18)
+#define TASK_EVENT_PD_AWAKE BIT(18)
 
 /* npcx peci event */
-#define TASK_EVENT_PECI_DONE	BIT(19)
+#define TASK_EVENT_PECI_DONE BIT(19)
 
 /* I2C tx/rx interrupt handler completion event. */
 #ifdef CHIP_STM32
-#define TASK_EVENT_I2C_COMPLETION(port) \
-				(1 << ((port) + 20))
-#define TASK_EVENT_I2C_IDLE	(TASK_EVENT_I2C_COMPLETION(0))
-#define TASK_EVENT_MAX_I2C	6
+#define TASK_EVENT_I2C_COMPLETION(port) (1 << ((port) + 20))
+#define TASK_EVENT_I2C_IDLE (TASK_EVENT_I2C_COMPLETION(0))
+#define TASK_EVENT_MAX_I2C 6
 #ifdef I2C_PORT_COUNT
 #if (I2C_PORT_COUNT > TASK_EVENT_MAX_I2C)
 #error "Too many i2c ports for i2c events"
 #endif
 #endif
 #else
-#define TASK_EVENT_I2C_IDLE	BIT(20)
-#define TASK_EVENT_PS2_DONE	BIT(21)
+#define TASK_EVENT_I2C_IDLE BIT(20)
+#define TASK_EVENT_PS2_DONE BIT(21)
 #endif
 
 /* DMA transmit complete event */
-#define TASK_EVENT_DMA_TC       BIT(26)
+#define TASK_EVENT_DMA_TC BIT(26)
 /* ADC interrupt handler event */
-#define TASK_EVENT_ADC_DONE	BIT(27)
+#define TASK_EVENT_ADC_DONE BIT(27)
 /*
  * task_reset() that was requested has been completed
  *
  * For test-only builds, may be used by some tasks to restart themselves.
  */
-#define TASK_EVENT_RESET_DONE   BIT(28)
+#define TASK_EVENT_RESET_DONE BIT(28)
 /* task_wake() called on task */
-#define TASK_EVENT_WAKE		BIT(29)
+#define TASK_EVENT_WAKE BIT(29)
 /* Mutex unlocking */
-#define TASK_EVENT_MUTEX	BIT(30)
+#define TASK_EVENT_MUTEX BIT(30)
 /*
  * Timer expired.  For example, task_wait_event() timed out before receiving
  * another event.
  */
-#define TASK_EVENT_TIMER	(1U << 31)
+#define TASK_EVENT_TIMER (1U << 31)
 
 /* Maximum time for task_wait_event() */
 #define TASK_MAX_WAIT_US 0x7fffffff
@@ -79,15 +91,51 @@ void interrupt_disable(void);
  */
 void interrupt_enable(void);
 
+/**
+ * Check if interrupts are enabled
+ */
+bool is_interrupt_enabled(void);
+
+/*
+ * Define irq_lock and irq_unlock that match the function signatures to Zephyr's
+ * functions. In reality, these simply call the current implementation of
+ * interrupt_disable() and interrupt_enable().
+ */
+#ifndef CONFIG_ZEPHYR
+/**
+ * Perform the same operation as interrupt_disable but allow nesting. The
+ * return value from this function should be used as the argument to
+ * irq_unlock. Do not attempt to parse the value, it is a representation
+ * of the state and not an indication of any form of count.
+ *
+ * For more information see:
+ * https://docs.zephyrproject.org/latest/reference/kernel/other/interrupts.html#c.irq_lock
+ *
+ * @return Lock key to use for restoring the state via irq_unlock.
+ */
+uint32_t irq_lock(void);
+
+/**
+ * Perform the same operation as interrupt_enable but allow nesting. The key
+ * should be the unchanged value returned by irq_lock.
+ *
+ * For more information see:
+ * https://docs.zephyrproject.org/latest/reference/kernel/other/interrupts.html#c.irq_unlock
+ *
+ * @param key The lock-out key used to restore the interrupt state.
+ */
+void irq_unlock(uint32_t key);
+#endif /* CONFIG_ZEPHYR */
+
 /**
  * Return true if we are in interrupt context.
  */
-int in_interrupt_context(void);
+bool in_interrupt_context(void);
 
 /**
  * Return true if we are in software interrupt context.
  */
-int in_soft_interrupt_context(void);
+bool in_soft_interrupt_context(void);
 
 /**
  * Return current interrupt mask with disabling interrupt. Meaning is
@@ -111,12 +159,8 @@ void set_int_mask(uint32_t val);
  *
  * @param tskid		Task to set event for
  * @param event		Event bitmap to set (TASK_EVENT_*)
- * @param wait		If non-zero, after setting the event, de-schedule the
- *			calling task to wait for a response event.  Ignored in
- *			interrupt context.
- * @return		The bitmap of events which occurred if wait!=0, else 0.
  */
-uint32_t task_set_event(task_id_t tskid, uint32_t event, int wait);
+void task_set_event(task_id_t tskid, uint32_t event);
 
 /**
  * Wake a task.  This sends it the TASK_EVENT_WAKE event.
@@ -125,7 +169,7 @@ uint32_t task_set_event(task_id_t tskid, uint32_t event, int wait);
  */
 static inline void task_wake(task_id_t tskid)
 {
-	task_set_event(tskid, TASK_EVENT_WAKE, 0);
+	task_set_event(tskid, TASK_EVENT_WAKE);
 }
 
 /**
@@ -133,10 +177,27 @@ static inline void task_wake(task_id_t tskid)
  */
 task_id_t task_get_current(void);
 
+#ifdef CONFIG_ZEPHYR
+/**
+ * Check if this current task is running in deferred context
+ */
+bool in_deferred_context(void);
+#else
+/* All ECOS deferred calls run from the HOOKS task */
+static inline bool in_deferred_context(void)
+{
+#ifdef HAS_TASK_HOOKS
+	return (task_get_current() == TASK_ID_HOOKS);
+#else
+	return false;
+#endif /* HAS_TASK_HOOKS */
+}
+#endif /* CONFIG_ZEPHYR */
+
 /**
  * Return a pointer to the bitmap of events of the task.
  */
-uint32_t *task_get_event_bitmap(task_id_t tskid);
+atomic_t *task_get_event_bitmap(task_id_t tskid);
 
 /**
  * Wait for the next event.
@@ -243,6 +304,11 @@ void task_enable_all_tasks(void);
  */
 void task_enable_task(task_id_t tskid);
 
+/**
+ * Task is enabled.
+ */
+bool task_enabled(task_id_t tskid);
+
 /**
  * Disable a task.
  *
@@ -325,11 +391,34 @@ int task_reset(task_id_t id, int wait);
  */
 void task_clear_pending_irq(int irq);
 
+/**
+ * Check if irq is pending.
+ *
+ * Returns true if interrupt with given number is pending, false otherwise.
+ */
+bool task_is_irq_pending(int irq);
+
+#ifdef CONFIG_ZEPHYR
+typedef struct k_mutex mutex_t;
+
+#define mutex_lock(mtx) (k_mutex_lock(mtx, K_FOREVER))
+#define mutex_unlock(mtx) (k_mutex_unlock(mtx))
+#else
 struct mutex {
 	uint32_t lock;
-	uint32_t waiters;
+	atomic_t waiters;
 };
 
+typedef struct mutex mutex_t;
+
+/**
+ * K_MUTEX_DEFINE is a macro normally provided by the Zephyr kernel,
+ * and allows creation of a static mutex without the need to
+ * initialize it.  We provide the same macro for CrOS EC OS so that we
+ * can use it in shared code.
+ */
+#define K_MUTEX_DEFINE(name) static mutex_t name = {}
+
 /**
  * Lock a mutex.
  *
@@ -338,12 +427,16 @@ struct mutex {
  *
  * Must not be used in interrupt context!
  */
-void mutex_lock(struct mutex *mtx);
+void mutex_lock(mutex_t *mtx);
 
 /**
  * Release a mutex previously locked by the same task.
  */
-void mutex_unlock(struct mutex *mtx);
+void mutex_unlock(mutex_t *mtx);
+
+/** Zephyr will try to init the mutex using `k_mutex_init()`. */
+#define k_mutex_init(mutex) 0
+#endif /* CONFIG_ZEPHYR */
 
 struct irq_priority {
 	uint8_t irq;
@@ -371,6 +464,7 @@ struct irq_def {
  * Implement the DECLARE_IRQ(irq, routine, priority) macro which is
  * a core specific helper macro to declare an interrupt handler "routine".
  */
+#ifndef CONFIG_ZEPHYR
 #ifdef CONFIG_COMMON_RUNTIME
 #include "irq_handler.h"
 #else
@@ -378,11 +472,19 @@ struct irq_def {
 #define IRQ_HANDLER_OPT(irqname) CONCAT3(irq_, irqname, _handler_optional)
 #define DECLARE_IRQ(irq, routine, priority) DECLARE_IRQ_(irq, routine, priority)
 #define DECLARE_IRQ_(irq, routine, priority) \
-	void IRQ_HANDLER_OPT(irq)(void) __attribute__((alias(#routine)));
+	static void __keep routine(void);    \
+	void IRQ_HANDLER_OPT(irq)(void) __attribute__((alias(#routine)))
 
 /* Include ec.irqlist here for compilation dependency */
 #define ENABLE_IRQ(x)
+#if !defined(CONFIG_DFU_BOOTMANAGER_MAIN)
 #include "ec.irqlist"
+#endif /* !defined(CONFIG_DFU_BOOTMANAGER_MAIN) */
+#endif /* CONFIG_COMMON_RUNTIME */
+#endif /* !CONFIG_ZEPHYR */
+
+#ifdef __cplusplus
+}
 #endif
 
-#endif  /* __CROS_EC_TASK_H */
+#endif /* __CROS_EC_TASK_H */
diff --git a/include/task_filter.h b/include/task_filter.h
index 2cd5e8bbf8..50fc46ce7f 100644
--- a/include/task_filter.h
+++ b/include/task_filter.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -50,5 +50,4 @@
 CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST CONFIG_CTS_TASK_LIST
 #endif
 
-
 #endif /*  __CROS_EC_TASK_FILTER_H */
diff --git a/include/task_id.h b/include/task_id.h
index a4d25ff33b..9ddc61678b 100644
--- a/include/task_id.h
+++ b/include/task_id.h
@@ -1,4 +1,4 @@
-/* Copyright 2011 The Chromium OS Authors. All rights reserved.
+/* Copyright 2011 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,13 +8,19 @@
 #ifndef __CROS_EC_TASK_ID_H
 #define __CROS_EC_TASK_ID_H
 
+/* For Zephyr builds just used shimmed tasks ids, otherwise use platform/ec's */
+#ifdef CONFIG_ZEPHYR
+#include "shimmed_task_id.h"
+#else
+
 #include "config.h"
 #include "task_filter.h"
 
+#include <stdint.h>
+
 /* define the name of the header containing the list of tasks */
-#ifndef CONFIG_ZEPHYR
-#define STRINGIFY0(name)  #name
-#define STRINGIFY(name)  STRINGIFY0(name)
+#define STRINGIFY0(name) #name
+#define STRINGIFY(name) STRINGIFY0(name)
 #define CTS_TASK_LIST STRINGIFY(CTS_TASKFILE)
 #define TEST_TASK_LIST STRINGIFY(TEST_TASKFILE)
 #define BOARD_TASK_LIST STRINGIFY(BOARD_TASKFILE)
@@ -26,7 +32,6 @@
 #ifdef TEST_BUILD
 #include TEST_TASK_LIST
 #endif
-#endif /* CONFIG_ZEPHYR */
 
 /* Task identifier (8 bits) */
 typedef uint8_t task_id_t;
@@ -37,29 +42,23 @@ typedef uint8_t task_id_t;
  * the identifier of a task can be retrieved using the following constant:
  * TASK_ID_<taskname> where <taskname> is the first parameter passed to the
  * TASK macro in the TASK_LIST file.
- *
- * For Zephyr, we still need to define TASK_ID_IDLE, TASK_ID_COUNT,
- * and TASK_ID_INVALID, even though we are not using the EC's task
- * system.  These are prolific enough in the codebase that #ifdef'ing
- * out each usage would be infeasible.
  */
 #define TASK(n, ...) TASK_ID_##n,
 enum {
 	TASK_ID_IDLE,
-#ifndef CONFIG_ZEPHYR
 	/* CONFIG_TASK_LIST is a macro coming from the BOARD_TASK_LIST file */
 	CONFIG_TASK_LIST
-	/* CONFIG_TEST_TASK_LIST is a macro from the TEST_TASK_LIST file */
-	CONFIG_TEST_TASK_LIST
-	/* For CTS tasks */
-	CONFIG_CTS_TASK_LIST
+		/* CONFIG_TEST_TASK_LIST is a macro from the TEST_TASK_LIST file
+		 */
+		CONFIG_TEST_TASK_LIST
+			/* For CTS tasks */
+			CONFIG_CTS_TASK_LIST
 #ifdef EMU_BUILD
-	TASK_ID_TEST_RUNNER,
+				TASK_ID_TEST_RUNNER,
 #endif
-#endif  /* CONFIG_ZEPHYR */
 	/* Number of tasks */
 	TASK_ID_COUNT,
-	/* Special task identifiers */
+/* Special task identifiers */
 #ifdef EMU_BUILD
 	TASK_ID_INT_GEN = 0xfe, /* interrupt generator */
 #endif
@@ -67,4 +66,5 @@ enum {
 };
 #undef TASK
 
-#endif  /* __CROS_EC_TASK_ID_H */
+#endif /* CONFIG_ZEPHYR */
+#endif /* __CROS_EC_TASK_ID_H */
diff --git a/include/temp_sensor.h b/include/temp_sensor.h
index f7b5371a1d..4dff6f99b2 100644
--- a/include/temp_sensor.h
+++ b/include/temp_sensor.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -33,8 +33,16 @@ struct temp_sensor_t {
 	const char *name;
 	/* Temperature sensor type. */
 	enum temp_sensor_type type;
+	/*
+	 * TODO(b:201081891) Refactor temp_sensor_t references
+	 * to all use OO style sensor argument to get adc idx.
+	 */
+#ifdef CONFIG_ZEPHYR
+	const struct zephyr_temp_sensor *zephyr_info;
+#else
 	/* Read sensor value in K into temp_ptr; return non-zero if error. */
 	int (*read)(int idx, int *temp_ptr);
+#endif
 	/* Index among the same kind of sensors. */
 	int idx;
 };
@@ -57,4 +65,16 @@ extern const struct temp_sensor_t temp_sensors[];
  */
 int temp_sensor_read(enum temp_sensor_id id, int *temp_ptr);
 
-#endif  /* __CROS_EC_TEMP_SENSOR_H */
+/**
+ * Print all temperature sensor values.
+ *
+ * @return EC_SUCCESS, or non-zero if error.
+ */
+int print_temps(void);
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+/**
+ * Board specific callback when temp sensor condition different with common
+ */
+__override_proto int board_temp_smi_evet(void);
+#endif
+#endif /* __CROS_EC_TEMP_SENSOR_H */
diff --git a/include/temp_sensor_chip.h b/include/temp_sensor_chip.h
index 4f9ddf0bc0..de9cb45452 100644
--- a/include/temp_sensor_chip.h
+++ b/include/temp_sensor_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/test_util.h b/include/test_util.h
index 41299e09d3..54da6a1d6c 100644
--- a/include/test_util.h
+++ b/include/test_util.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,54 +8,80 @@
 #ifndef __CROS_EC_TEST_UTIL_H
 #define __CROS_EC_TEST_UTIL_H
 
+#include "compile_time_macros.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 #include "common.h"
 #include "console.h"
+#include "ec_commands.h"
+#include "math_util.h"
 #include "stack_trace.h"
+#include "string.h"
+
+#ifdef CONFIG_ZTEST
+#include "ec_tasks.h"
+
+#include <zephyr/ztest.h>
+#endif /* CONFIG_ZTEST */
 
 /* This allows tests to be easily commented out in run_test for debugging */
 #define test_static static __attribute__((unused))
 
-#define RUN_TEST(n) \
-	do { \
+#define RUN_TEST(n)                              \
+	do {                                     \
 		ccprintf("Running %s...\n", #n); \
-		cflush(); \
-		before_test(); \
-		if (n() == EC_SUCCESS) { \
-			ccputs("OK\n"); \
-		} else { \
-			ccputs("Fail\n"); \
-			__test_error_count++; \
-		} \
-		after_test(); \
+		cflush();                        \
+		before_test();                   \
+		if (n() == EC_SUCCESS) {         \
+			ccputs("OK\n");          \
+		} else {                         \
+			ccputs("Fail\n");        \
+			__test_error_count++;    \
+		}                                \
+		after_test();                    \
 	} while (0)
 
-#define TEST_ASSERT(n) \
-	do { \
-		if (!(n)) { \
-			ccprintf("%d: ASSERTION failed: %s\n", __LINE__, #n); \
-			task_dump_trace(); \
-			return EC_ERROR_UNKNOWN; \
-		} \
+#define TEST_ASSERT(n)                                                      \
+	do {                                                                \
+		if (!(n)) {                                                 \
+			ccprintf("%s:%d: ASSERTION failed: %s\n", __FILE__, \
+				 __LINE__, #n);                             \
+			task_dump_trace();                                  \
+			return EC_ERROR_UNKNOWN;                            \
+		}                                                           \
 	} while (0)
 
 #if defined(__cplusplus) && !defined(__auto_type)
 #define __auto_type auto
 #endif
 
-#define TEST_OPERATOR(a, b, op, fmt) \
-	do { \
-		__auto_type _a = (a);                                       \
-		__auto_type _b = (b);                                       \
-		if (!(_a op _b)) {                                          \
-			ccprintf("%d: ASSERTION failed: %s " #op " %s\n",   \
-				 __LINE__, #a, #b);                         \
-			ccprintf("\t\tEVAL: " fmt " " #op " " fmt "\n",     \
-				 _a, _b);                                   \
-			task_dump_trace();                                  \
-			return EC_ERROR_UNKNOWN;                            \
-		} else  {                                                   \
-			ccprintf("Pass: %s " #op " %s\n", #a, #b);        \
-		}                                                           \
+/* Tests comparing complex types that cannot be easily formatted for printing
+ * may define TEST_OPERATOR_INHIBIT_PRINT_EVAL to inhibit printing of the
+ * compared values on failure.
+ */
+#ifdef TEST_OPERATOR_INHIBIT_PRINT_EVAL
+#define TEST_OPERATOR_PRINT_EVAL(fmt, op, _a, _b)
+#else
+#define TEST_OPERATOR_PRINT_EVAL(fmt, op, _a, _b) \
+	ccprintf("\t\tEVAL: " fmt " " #op " " fmt "\n", _a, _b)
+#endif
+
+#define TEST_OPERATOR(a, b, op, fmt)                                         \
+	do {                                                                 \
+		__auto_type _a = (a);                                        \
+		__auto_type _b = (b);                                        \
+		if (!(_a op _b)) {                                           \
+			ccprintf("%s:%d: ASSERTION failed: %s " #op " %s\n", \
+				 __FILE__, __LINE__, #a, #b);                \
+			TEST_OPERATOR_PRINT_EVAL(fmt, op, _a, _b);           \
+			task_dump_trace();                                   \
+			return EC_ERROR_UNKNOWN;                             \
+		} else {                                                     \
+			ccprintf("Pass: %s " #op " %s\n", #a, #b);           \
+		}                                                            \
 	} while (0)
 
 #define TEST_EQ(a, b, fmt) TEST_OPERATOR(a, b, ==, fmt)
@@ -64,47 +90,62 @@
 #define TEST_LE(a, b, fmt) TEST_OPERATOR(a, b, <=, fmt)
 #define TEST_GT(a, b, fmt) TEST_OPERATOR(a, b, >, fmt)
 #define TEST_GE(a, b, fmt) TEST_OPERATOR(a, b, >=, fmt)
-#define TEST_BITS_SET(a, bits) TEST_OPERATOR(a & (int)bits, (int)bits, ==, "%u")
-#define TEST_BITS_CLEARED(a, bits) TEST_OPERATOR(a & (int)bits, 0, ==, "%u")
+#define TEST_BITS_SET(a, bits) TEST_OPERATOR(a &(int)bits, (int)bits, ==, "%u")
+#define TEST_BITS_CLEARED(a, bits) TEST_OPERATOR(a &(int)bits, 0, ==, "%u")
 #define TEST_NEAR(a, b, epsilon, fmt) \
 	TEST_OPERATOR(ABS((a) - (b)), epsilon, <, fmt)
 
-#define __ABS(n) ((n) > 0 ? (n) : -(n))
-
-#define TEST_ASSERT_ABS_LESS(n, t) TEST_OPERATOR(__ABS(n), t, <, "%d")
-
-#define TEST_ASSERT_ARRAY_EQ(s, d, n) \
-	do { \
-		int __i; \
-		for (__i = 0; __i < n; ++__i) \
-			if ((s)[__i] != (d)[__i]) { \
-				ccprintf("%d: ASSERT_ARRAY_EQ failed at " \
-					 "index=%d: %d != %d\n", __LINE__, \
-					 __i, (int)(s)[__i], (int)(d)[__i]); \
-				task_dump_trace(); \
-				return EC_ERROR_UNKNOWN; \
-			} \
+#define TEST_ASSERT_ABS_LESS(n, t) TEST_OPERATOR(ABS(n), t, <, "%d")
+
+#define TEST_ASSERT_ARRAY_EQ(s, d, n)                                        \
+	do {                                                                 \
+		if (n < 0)                                                   \
+			return EC_ERROR_UNKNOWN;                             \
+                                                                             \
+		unsigned int __n = n;                                        \
+                                                                             \
+		for (unsigned int __i = 0; __i < __n; ++__i)                 \
+                                                                             \
+			if ((s)[__i] != (d)[__i]) {                          \
+				ccprintf("%s:%d: ASSERT_ARRAY_EQ failed at " \
+					 "index=%u: %d != %d\n",             \
+					 __FILE__, __LINE__, __i,            \
+					 (int)(s)[__i], (int)(d)[__i]);      \
+				task_dump_trace();                           \
+				return EC_ERROR_UNKNOWN;                     \
+			}                                                    \
 	} while (0)
 
-#define TEST_ASSERT_MEMSET(d, c, n) \
-	do { \
-		int __i; \
-		for (__i = 0; __i < n; ++__i) \
-			if ((d)[__i] != (c)) { \
-				ccprintf("%d: ASSERT_MEMSET failed at " \
-					 "index=%d: %d != %d\n", __LINE__, \
-					 __i, (int)(d)[__i], (c)); \
-				task_dump_trace(); \
-				return EC_ERROR_UNKNOWN; \
-			} \
+#define TEST_ASSERT_ARRAY_NE(s, d, n)                                         \
+	do {                                                                  \
+		if (n < 0)                                                    \
+			return EC_ERROR_UNKNOWN;                              \
+                                                                              \
+		if (memcmp(&s[0], &d[0], n) == 0) {                           \
+			ccprintf("%s:%d: ASSERT_ARRAY_NE failed\n", __FILE__, \
+				 __LINE__);                                   \
+			task_dump_trace();                                    \
+			return EC_ERROR_UNKNOWN;                              \
+		}                                                             \
 	} while (0)
 
-#define TEST_CHECK(n) \
-	do { \
-		if (n) \
-			return EC_SUCCESS; \
-		else \
-			return EC_ERROR_UNKNOWN; \
+#define TEST_ASSERT_MEMSET(d, c, n)                                        \
+	do {                                                               \
+		if (n < 0)                                                 \
+			return EC_ERROR_UNKNOWN;                           \
+                                                                           \
+		unsigned int __n = n;                                      \
+                                                                           \
+		for (unsigned int __i = 0; __i < __n; ++__i)               \
+                                                                           \
+			if ((d)[__i] != (c)) {                             \
+				ccprintf("%s:%d: ASSERT_MEMSET failed at " \
+					 "index=%u: %d != %d\n",           \
+					 __FILE__, __LINE__, __i,          \
+					 (int)(d)[__i], (c));              \
+				task_dump_trace();                         \
+				return EC_ERROR_UNKNOWN;                   \
+			}                                                  \
 	} while (0)
 
 /* Mutlistep test states */
@@ -118,6 +159,7 @@ enum test_state_t {
 	TEST_STATE_STEP_7,
 	TEST_STATE_STEP_8,
 	TEST_STATE_STEP_9,
+	TEST_STATE_STEP_10,
 	TEST_STATE_PASSED,
 	TEST_STATE_FAILED,
 };
@@ -139,7 +181,7 @@ void before_test(void);
 void after_test(void);
 
 /* Test entry point */
-void run_test(int argc, char **argv);
+void run_test(int argc, const char **argv);
 
 /* Test entry point for fuzzing tests. */
 int test_fuzz_one_input(const uint8_t *data, unsigned int size);
@@ -148,7 +190,11 @@ int test_fuzz_one_input(const uint8_t *data, unsigned int size);
 void test_reset(void);
 
 /* Reports test pass */
+#ifdef CONFIG_ZEPHYR
+#define test_pass ztest_test_pass
+#else
 void test_pass(void);
+#endif
 
 /* Reports test failure */
 void test_fail(void);
@@ -160,8 +206,9 @@ void test_print_result(void);
 int test_get_error_count(void);
 
 /* Simulates host command sent from the host */
-int test_send_host_command(int command, int version, const void *params,
-			   int params_size, void *resp, int resp_size);
+enum ec_status test_send_host_command(int command, int version,
+				      const void *params, int params_size,
+				      void *resp, int resp_size);
 
 /* Optionally defined interrupt generator entry point */
 void interrupt_generator(void);
@@ -177,14 +224,18 @@ void task_trigger_test_interrupt(void (*isr)(void));
  * to udelay() from interrupt generator are delegated to this function
  * automatically.
  */
-void interrupt_generator_udelay(unsigned us);
+void interrupt_generator_udelay(unsigned int us);
 
 #ifdef EMU_BUILD
 void wait_for_task_started(void);
 void wait_for_task_started_nosleep(void);
 #else
-static inline void wait_for_task_started(void) { }
-static inline void wait_for_task_started_nosleep(void) { }
+static inline void wait_for_task_started(void)
+{
+}
+static inline void wait_for_task_started_nosleep(void)
+{
+}
 #endif
 
 uint32_t prng(uint32_t seed);
@@ -244,6 +295,9 @@ uint32_t test_get_state(void);
  */
 void test_clean_up(void);
 
+/* Set the next step */
+void test_set_next_step(enum test_state_t step);
+
 /* Set the next step and reboot */
 void test_reboot_to_next_step(enum test_state_t step);
 
@@ -256,8 +310,8 @@ struct test_i2c_read_string_dev {
 struct test_i2c_xfer {
 	/* I2C xfer handler */
 	int (*routine)(const int port, const uint16_t i2c_addr_flags,
-		       const uint8_t *out, int out_size,
-		       uint8_t *in, int in_size, int flags);
+		       const uint8_t *out, int out_size, uint8_t *in,
+		       int in_size, int flags);
 };
 
 struct test_i2c_write_dev {
@@ -271,35 +325,209 @@ struct test_i2c_write_dev {
  *
  * When this function is called, it should either perform the desired
  * mock functionality, or return EC_ERROR_INVAL to indicate it does
- * not respond to the specified port and slave address.
+ * not respond to the specified port and peripheral address.
  *
  * @param routine     Function pointer, with the same prototype as i2c_xfer()
  */
-#define DECLARE_TEST_I2C_XFER(routine)					\
-	const struct test_i2c_xfer __no_sanitize_address		\
-	__test_i2c_xfer_##routine					\
-	__attribute__((section(".rodata.test_i2c.xfer")))		\
-		= {routine}
+#define DECLARE_TEST_I2C_XFER(routine)                    \
+	const struct test_i2c_xfer __no_sanitize_address  \
+		__test_i2c_xfer_##routine __attribute__(( \
+			section(".rodata.test_i2c.xfer"))) = { routine }
 
 /*
  * Detach an I2C device. Once detached, any read/write command regarding the
- * specified port and slave address returns error.
+ * specified port and peripheral address returns error.
  *
  * @param port       The port that the detached device is connected to
- * @param slave_addr The address of the detached device
+ * @param addr_flags The address of the detached device
  * @return EC_SUCCESS if detached; EC_ERROR_OVERFLOW if too many devices are
  *         detached.
  */
-int test_detach_i2c(const int port, const uint16_t slave_addr_flags);
+int test_detach_i2c(const int port, const uint16_t addr_flags);
 
 /*
  * Re-attach an I2C device.
  *
  * @param port       The port that the detached device is connected to
- * @param slave_addr The address of the detached device
+ * @param addr_flags The address of the detached device
  * @return EC_SUCCESS if re-attached; EC_ERROR_INVAL if the specified device
  *         is not a detached device.
  */
-int test_attach_i2c(const int port, const uint16_t slave_addr_flags);
+int test_attach_i2c(const int port, const uint16_t addr_flags);
+
+/*
+ * We need these macros so that a test can be built for either Ztest or the
+ * EC test framework.
+ *
+ * EC unit tests return an EC_SUCCESS, or a failure code if one of the
+ * asserts in the test fails. This means that when building for Zephyr, we'll
+ * need to wrap the function returning an int with a Zephyr compatible void
+ * function. This function will simply test the result of the underlying
+ * function agains EC_SUCCESS.
+ *
+ * Usage:
+ * DECLARE_EC_TEST(test_it)
+ * {
+ *   ...
+ *   return EC_SUCCESS;
+ * }
+ */
+#ifdef CONFIG_ZEPHYR
+#define DECLARE_EC_TEST(fname)                                                \
+	static int _stub_##fname(void);                                       \
+	static void fname(void)                                               \
+	{                                                                     \
+		zassert_equal(_stub_##fname(), EC_SUCCESS, #fname " failed"); \
+	}                                                                     \
+	static int _stub_##fname(void)
+#else
+#define DECLARE_EC_TEST(fname) static int fname(void)
+#endif
+
+/*
+ * Create a Zephyr compatible task function. An EC task only has one void
+ * parameter, while Zephyr takes in 3.
+ */
+#ifdef CONFIG_ZEPHYR
+#define TASK_PARAMS void *p1, void *p2, void *p3
+#else
+#define TASK_PARAMS void *p1
+#endif
+
+/*
+ * Create a TEST_MAIN macro to allow for Zephyr's test_main(void) to be used
+ * in Zephyr tests, while using run_test(int, char**) in platform/ec tests.
+ * This macro uses the lowest common denominator of the two (Zephyr) so tests
+ * that migrate from platform/ec to Zephyr will no longer be able to use the
+ * arguments (compile time checked).
+ * TEST_SUITE(name) macro is resolved to TEST_MAIN in platform/ec tests.
+ * In Zephyr tests it allows to use different name for entry point than
+ * test_main(void). Because of that, it is possible to combine multiple test
+ * suites in one test.
+ *
+ * Usage:
+ * TEST_MAIN()
+ * {
+ *   ...
+ * }
+ */
+#ifdef CONFIG_ZEPHYR
+#define TEST_MAIN() void test_main(void)
+#define TEST_SUITE(name) void name(void)
+#else
+#define TEST_MAIN()                                \
+	void test_main(void);                      \
+	void run_test(int argc, const char **argv) \
+	{                                          \
+		test_reset();                      \
+		test_main();                       \
+		test_print_result();               \
+	}                                          \
+	void test_main(void)
+#define TEST_SUITE(name) TEST_MAIN()
+#endif
+
+/*
+ * Declare various Zephyr structs, functions, and macros so the same code can
+ * used in platform/ec tests.
+ */
+#ifndef CONFIG_ZEPHYR
+struct unit_test {
+	const char *name;
+	int (*test)(void);
+	void (*setup)(void);
+	void (*teardown)(void);
+};
+
+/**
+ * Create a unit test for a given function name with provided setup/teardown
+ * functions.
+ *
+ * @param fn The name of the function to run the test for (should be declared
+ * with DECLARE_EC_TEST).
+ * @param setup A function to call before this test function for setting data
+ * up.
+ * @param teardown A function to call after this test function for cleanup.
+ */
+#define ztest_unit_test_setup_teardown(fn, setup, teardown) \
+	{                                                   \
+		#fn, fn, setup, teardown                    \
+	}
+
+/**
+ * Create a unit test for a given function name with noop setup/teardown
+ * functions.
+ *
+ * @param fn The name of the function to run the test for (should be declared
+ * with DECLARE_EC_TEST).
+ * @see ztest_unit_test_setup_teardown
+ */
+#define ztest_unit_test(fn) \
+	ztest_unit_test_setup_teardown(fn, before_test, after_test)
+
+/**
+ * @brief Create a test suite
+ *
+ * Usage:
+ *   ztest_test_suite(my_tests,
+ *     ztest_unit_test(test0),
+ *     ztest_unit_test(test1));
+ *
+ * @param suite The name of the test suite (should be unique inside the given
+ * function).
+ */
+#define ztest_test_suite(suite, ...) \
+	static struct unit_test suite[] = { __VA_ARGS__, { 0 } }
+
+/**
+ * The primary entry point to run a test suite. This function should generally
+ * not be called directly, but should be invoked via
+ * ztest_run_test_suite(my_tests).
+ *
+ * @param name The name of the test suite.
+ * @param suite Pointer to the test suite array.
+ */
+void z_ztest_run_test_suite(const char *name, struct unit_test *suite);
+
+/**
+ * Run a test suite.
+ *
+ * Usage:
+ *   ztest_run_test_suite(my_tests);
+ *
+ * @param suite The name of the test suite to run.
+ */
+#define ztest_run_test_suite(suite) z_ztest_run_test_suite(#suite, suite)
+#endif /* CONFIG_ZEPHYR */
+
+#ifndef CONFIG_ZEPHYR
+/*
+ * Map the Ztest assertions onto EC assertions. There are two significant
+ * issues here.
+ * 1. zassert macros have extra printf-style arguments that the EC macros
+ * don't support, so we just have to drop that.
+ * 2. Some EC macros have an extra `fmt` parameter because they make their
+ * own printf-style string when the assertion fails. For some of them, we
+ * can add the correct format (the zassert_equal_ptr), but others we just
+ * don't know, so I'll just dump out the value in hex.
+ */
+#define zassert(cond, ...) TEST_ASSERT(cond)
+#define zassert_unreachable(...) TEST_ASSERT(0)
+#define zassert_true(cond, ...) TEST_ASSERT(cond)
+#define zassert_false(cond, ...) TEST_ASSERT(!(cond))
+#define zassert_ok(cond, ...) TEST_ASSERT(!(cond))
+#define zassert_is_null(ptr, ...) TEST_ASSERT((ptr) == NULL)
+#define zassert_not_null(ptr, ...) TEST_ASSERT((ptr) != NULL)
+#define zassert_equal(a, b, ...) TEST_EQ((a), (b), "0x%x")
+#define zassert_not_equal(a, b, ...) TEST_NE((a), (b), "0x%x")
+#define zassert_equal_ptr(a, b, ...) TEST_EQ((void *)(a), (void *)(b), "0x%x")
+#define zassert_within(a, b, d, ...) TEST_NEAR((a), (b), (d), "%f")
+#define zassert_mem_equal(buf, exp, size, ...) \
+	TEST_ASSERT_ARRAY_EQ(buf, exp, size)
+#endif /* CONFIG_ZEPHYR */
+
+#ifdef __cplusplus
+}
+#endif
 
 #endif /* __CROS_EC_TEST_UTIL_H */
diff --git a/include/tests/enum_strings.h b/include/tests/enum_strings.h
index ece2df362f..7654dc9377 100644
--- a/include/tests/enum_strings.h
+++ b/include/tests/enum_strings.h
@@ -1,12 +1,12 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Defines helper function that convert Enums to strings for prints in tests */
 
-#include "usb_pd_tcpm.h"
 #include "usb_pd.h"
+#include "usb_pd_tcpm.h"
 
 #ifndef __CROS_EC_TEST_ENUM_STINGS_H
 #define __CROS_EC_TEST_ENUM_STINGS_H
diff --git a/include/thermal.h b/include/thermal.h
index 29d8073ca0..5eb1f3d546 100644
--- a/include/thermal.h
+++ b/include/thermal.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,4 +27,6 @@ int thermal_fan_percent(int low, int high, int cur);
  */
 void board_override_fan_control(int fan, int *tmp);
 
-#endif  /* __CROS_EC_THERMAL_H */
+bool thermal_warn_trigger(void);
+
+#endif /* __CROS_EC_THERMAL_H */
diff --git a/include/throttle_ap.h b/include/throttle_ap.h
index fbfa36aed3..09c85759c2 100644
--- a/include/throttle_ap.h
+++ b/include/throttle_ap.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,6 +8,8 @@
 #ifndef __CROS_EC_THROTTLE_AP_H
 #define __CROS_EC_THROTTLE_AP_H
 
+#define PROCHOT_IN_DEBOUNCE_US (100 * MSEC)
+
 /**
  * Level of throttling desired.
  */
@@ -20,8 +22,8 @@ enum throttle_level {
  * Types of throttling desired. These are independent.
  */
 enum throttle_type {
-	THROTTLE_SOFT = 0,			/* for example, host events */
-	THROTTLE_HARD,				/* for example, PROCHOT */
+	THROTTLE_SOFT = 0, /* for example, host events */
+	THROTTLE_HARD, /* for example, PROCHOT */
 	NUM_THROTTLE_TYPES
 };
 
@@ -32,6 +34,25 @@ enum throttle_sources {
 	THROTTLE_SRC_THERMAL = 0,
 	THROTTLE_SRC_BAT_DISCHG_CURRENT,
 	THROTTLE_SRC_BAT_VOLTAGE,
+	THROTTLE_SRC_AC,
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+	THROTTLE_SRC_UPDATE_PMF,
+#endif
+};
+
+/**
+ * PROCHOT detection GPIOs.  PROCHOT in assumed to be active high unless
+ * CONFIG_CPU_PROCHOT_ACTIVE_LOW is enabled.
+ * C10 input polarity is explicitly specified in the struct below.
+ */
+struct prochot_cfg {
+	enum gpio_signal gpio_prochot_in;
+	void (*callback)(bool asserted, void *data);
+	void *callback_data;
+#ifdef CONFIG_CPU_PROCHOT_GATE_ON_C10
+	enum gpio_signal gpio_c10_in;
+	bool c10_active_high;
+#endif
 };
 
 /**
@@ -44,14 +65,21 @@ enum throttle_sources {
  * @param type          Type of throttling desired
  * @param source        Which task is requesting throttling
  */
-#if defined(CONFIG_THROTTLE_AP) || \
+#if defined(CONFIG_THROTTLE_AP) ||                           \
 	defined(CONFIG_THROTTLE_AP_ON_BAT_DISCHG_CURRENT) || \
 	defined(CONFIG_THROTTLE_AP_ON_BAT_VOLTAGE)
 
-void throttle_ap(enum throttle_level level,
-		 enum throttle_type type,
+void throttle_ap(enum throttle_level level, enum throttle_type type,
 		 enum throttle_sources source);
 
+/**
+ * Configure the GPIOs used to monitor the PROCHOT signal.
+ *
+ * @param cfg	GPIO configuration for the PROCHOT and optional C10
+ *		signals.
+ */
+void throttle_ap_config_prochot(const struct prochot_cfg *cfg);
+
 /**
  * Interrupt handler to monitor PROCHOT input to the EC. The PROCHOT signal
  * can be asserted by the AP or by other devices on the board, such as chargers
@@ -65,11 +93,27 @@ void throttle_ap(enum throttle_level level,
  */
 void throttle_ap_prochot_input_interrupt(enum gpio_signal signal);
 
+/**
+ * Interrupt handler to monitor the C10 input to the EC. The C10 signal
+ * can be asserted by the AP when entering an idle state. This interrupt
+ * is configured for the edge indicating C10 is de-asserting (GPIO_INT_RISING
+ * if the signal is active low, GPIO_INT_FALLING for an active high signal).
+ *
+ * The board initialization is responsible for enabling the interrupt.
+ *
+ * @param signal    GPIO signal connected to C10 input.
+ */
+void throttle_ap_c10_input_interrupt(enum gpio_signal signal);
+
 #else
 static inline void throttle_ap(enum throttle_level level,
 			       enum throttle_type type,
 			       enum throttle_sources source)
-{}
+{
+}
 #endif
 
-#endif	/* __CROS_EC_THROTTLE_AP_H */
+void throttle_gpu(enum throttle_level level, enum throttle_type type,
+		  enum throttle_sources source);
+
+#endif /* __CROS_EC_THROTTLE_AP_H */
diff --git a/include/timer.h b/include/timer.h
index d8bc252ba0..278e3b8c25 100644
--- a/include/timer.h
+++ b/include/timer.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,15 +8,28 @@
 #ifndef __CROS_EC_TIMER_H
 #define __CROS_EC_TIMER_H
 
+#ifndef CONFIG_ZEPHYR
+#include <time.h>
+
+#include <sys/types.h>
+#else
+/* Data type for POSIX style clock() implementation */
+typedef long clock_t;
+#endif
+
 #include "common.h"
 #include "task_id.h"
 
 /* Time units in microseconds */
-#define MSEC         1000
-#define SECOND    1000000
-#define SEC_UL    1000000ul
-#define MINUTE   60000000
-#define HOUR   3600000000ull  /* Too big to fit in a signed int */
+#define MSEC 1000
+#define SECOND 1000000
+#define SEC_UL 1000000ul
+#define MINUTE 60000000
+#define HOUR 3600000000ull /* Too big to fit in a signed int */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
 
 /* Microsecond timestamp. */
 typedef union {
@@ -27,9 +40,6 @@ typedef union {
 	} le /* little endian words */;
 } timestamp_t;
 
-/* Data type for POSIX style clock() implementation */
-typedef long clock_t;
-
 /**
  * Initialize the timer module.
  */
@@ -72,7 +82,7 @@ int timestamp_expired(timestamp_t deadline, const timestamp_t *now);
  *
  * @param us		Number of microseconds to delay.
  */
-void udelay(unsigned us);
+void udelay(unsigned int us);
 
 /**
  * Sleep.
@@ -85,7 +95,7 @@ void udelay(unsigned us);
  *
  * @param us		Number of microseconds to sleep.
  */
-void usleep(unsigned us);
+void usleep(unsigned int us);
 
 /**
  * Sleep for milliseconds.
@@ -94,7 +104,7 @@ void usleep(unsigned us);
  *
  * @param ms		Number of milliseconds to sleep.
  */
-static inline void msleep(unsigned ms)
+static inline void msleep(unsigned int ms)
 {
 	usleep(ms * MSEC);
 }
@@ -106,7 +116,7 @@ static inline void msleep(unsigned ms)
  *
  * @param sec		Number of seconds to sleep.
  */
-static inline void sleep(unsigned sec)
+static inline void sleep(unsigned int sec)
 {
 	usleep(sec * SECOND);
 }
@@ -162,7 +172,7 @@ static inline int time_until(uint32_t from_time, uint32_t to_time)
  * @param start		Start time to compare against
  * @return number of microseconds that have elapsed since that start time
  */
-static inline unsigned time_since32(timestamp_t start)
+static inline unsigned int time_since32(timestamp_t start)
 {
 	return time_until(start.le.lo, get_time().le.lo);
 }
@@ -177,4 +187,21 @@ static inline int time_after(uint32_t a, uint32_t b)
 	return time_until(a, b) < 0;
 }
 
-#endif  /* __CROS_EC_TIMER_H */
+/**
+ * @brief Mock get_time() function.
+ *
+ * Setting to non-NULL makes subsequent calls to get_time() return
+ * its set value.
+ *
+ * When set to NULL, subsequent calls to get_time() return
+ * unmocked values.
+ */
+#ifdef CONFIG_ZTEST
+extern timestamp_t *get_time_mock;
+#endif /* CONFIG_ZTEST */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CROS_EC_TIMER_H */
diff --git a/include/touchpad.h b/include/touchpad.h
index 4e746d8dc1..8ae985318e 100644
--- a/include/touchpad.h
+++ b/include/touchpad.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/trng.h b/include/trng.h
index cea4555b41..06fbcc8544 100644
--- a/include/trng.h
+++ b/include/trng.h
@@ -1,45 +1,53 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 #ifndef __EC_INCLUDE_TRNG_H
 #define __EC_INCLUDE_TRNG_H
 
-#include <common.h>
 #include <stddef.h>
 #include <stdint.h>
 
+#include <common.h>
+
+#ifdef CONFIG_ZEPHYR
+/*
+ * Zephyr driver is responsible for initializing, enabling and disabling
+ * hardware. In this case, trng_init() and trng_exit() does nothing.
+ */
+#define trng_init()
+#define trng_exit()
+#else
 /**
  * Initialize the true random number generator.
  *
  * Not supported by all platforms.
  **/
-void init_trng(void);
+void trng_init(void);
 
 /**
- * Shutdown the true random number generator.
- *
- * The opposite operation of init_trng(), disable the hardware resources
- * used by the TRNG to save power.
+ * Generate true random number.
  *
  * Not supported by all platforms.
  **/
-void exit_trng(void);
+uint32_t trng_rand(void);
 
 /**
- * Retrieve a 32 bit random value.
+ * Shutdown the true random number generator.
  *
- * Not supported on all platforms.
+ * The opposite operation of trng_init(), disable the hardware resources
+ * used by the TRNG to save power.
+ *
+ * Not supported by all platforms.
  **/
-#ifndef HIDE_EC_STDLIB
-uint32_t rand(void);
-#endif
+void trng_exit(void);
+#endif /* CONFIG_ZEPHYR */
 
 /**
  * Output len random bytes into buffer.
  *
  * Not supported on all platforms.
  **/
-void rand_bytes(void *buffer, size_t len);
+void trng_rand_bytes(void *buffer, size_t len);
 
 #endif /* __EC_INCLUDE_TRNG_H */
diff --git a/include/typec_control.h b/include/typec_control.h
new file mode 100644
index 0000000000..849a661490
--- /dev/null
+++ b/include/typec_control.h
@@ -0,0 +1,46 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Type-C control logic header */
+
+#ifndef __CROS_EC_TYPEC_CONTROL_H
+#define __CROS_EC_TYPEC_CONTROL_H
+
+#include "usb_pd_tcpm.h"
+
+/**
+ * Sets the polarity of the port
+ *
+ * @param port USB-C port number
+ * @param polarity Polarity of CC lines
+ */
+void typec_set_polarity(int port, enum tcpc_cc_polarity polarity);
+
+/**
+ * Turn on/off the SBU FETs.
+ *
+ * @param port USB-C port number
+ * @param enable true:enable, false:disable
+ */
+void typec_set_sbu(int port, bool enable);
+
+/**
+ * Set the type-C current limit when sourcing current
+ *
+ * @param port USB-C port number
+ * @param rp Pull-up values to be aplied as a SRC to advertise current limits
+ */
+__override_proto void typec_set_source_current_limit(int port,
+						     enum tcpc_rp_value rp);
+
+/**
+ * Turn on/off the VCONN FET
+ *
+ * @param port USB-C port number
+ * @param enable true:enable, false:disable
+ */
+void typec_set_vconn(int port, bool enable);
+
+#endif /* __CROS_EC_TYPEC_CONTROL_H */
diff --git a/include/uart.h b/include/uart.h
index b6dce4f21f..086c407695 100644
--- a/include/uart.h
+++ b/include/uart.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,9 +8,10 @@
 #ifndef __CROS_EC_UART_H
 #define __CROS_EC_UART_H
 
-#include <stdarg.h>  /* For va_list */
 #include "common.h"
-#include "gpio.h"
+#include "gpio_signal.h"
+
+#include <stdarg.h> /* For va_list */
 
 /**
  * Initialize the UART module.
@@ -52,7 +53,7 @@ int uart_puts(const char *outstr);
  *
  * @param out		Pointer to data to send
  * @param len		Length of transfer in bytes
- * @return EC_SUCCESS, or non-zero if output was truncated.
+ * @return number of characters successfully written.
  */
 int uart_put(const char *out, int len);
 
@@ -61,7 +62,7 @@ int uart_put(const char *out, int len);
  *
  * @param out		Pointer to data to send
  * @param len		Length of transfer in bytes
- * @return EC_SUCCESS, or non-zero if output was truncated.
+ * @return number of characters successfully written.
  */
 int uart_put_raw(const char *out, int len);
 
@@ -72,8 +73,8 @@ int uart_put_raw(const char *out, int len);
  *
  * @return EC_SUCCESS, or non-zero if output was truncated.
  */
-__attribute__((__format__(__printf__, 1, 2)))
-int uart_printf(const char *format, ...);
+__attribute__((__format__(__printf__, 1, 2))) int
+uart_printf(const char *format, ...);
 
 /**
  * Print formatted output to the UART, like vprintf().
@@ -84,6 +85,22 @@ int uart_printf(const char *format, ...);
  */
 int uart_vprintf(const char *format, va_list args);
 
+/**
+ * Put a single character into the transmit buffer.
+ *
+ * Does not enable the transmit interrupt; assumes that happens elsewhere.
+ *
+ * @param context	Context; ignored.
+ * @param c		Character to write.
+ * @return 0 if the character was transmitted, 1 if it was dropped.
+ *
+ * Note: This is intended to be implemented by the UART buffering
+ * module, and called only by the implementations of the uart_*
+ * functions.  You should stick to the higher level functions, such as
+ * uart_putc, outside of the UART implementation.
+ */
+int uart_tx_char_raw(void *context, int c);
+
 /**
  * Flush output.  Blocks until UART has transmitted all output.
  */
@@ -242,7 +259,9 @@ void uart_exit_dsleep(void);
  */
 void uart_deepsleep_interrupt(enum gpio_signal signal);
 #else
-static inline void uart_deepsleep_interrupt(enum gpio_signal signal) { }
+static inline void uart_deepsleep_interrupt(enum gpio_signal signal)
+{
+}
 #endif /* !CONFIG_LOW_POWER_IDLE */
 
 #if defined(HAS_TASK_CONSOLE) && defined(CONFIG_FORCE_CONSOLE_RESUME)
@@ -253,7 +272,9 @@ static inline void uart_deepsleep_interrupt(enum gpio_signal signal) { }
  */
 void uart_enable_wakeup(int enable);
 #elif !defined(CHIP_FAMILY_NPCX5)
-static inline void uart_enable_wakeup(int enable) {}
+static inline void uart_enable_wakeup(int enable)
+{
+}
 #endif
 
 #ifdef CONFIG_UART_INPUT_FILTER
@@ -319,7 +340,7 @@ void uart_reset_default_pad_panic(void);
  *           time specified in timeout_us.
  */
 int uart_alt_pad_write_read(uint8_t *tx, int tx_len, uint8_t *rx, int rx_len,
-			int timeout_us);
+			    int timeout_us);
 
 /**
  * Interrupt handler for default UART RX pin transition when UART is switched
@@ -356,9 +377,7 @@ enum ec_status uart_console_read_buffer_init(void);
  *
  * @return result status (EC_RES_*)
  */
-int uart_console_read_buffer(uint8_t type,
-			     char *dest,
-			     uint16_t dest_size,
+int uart_console_read_buffer(uint8_t type, char *dest, uint16_t dest_size,
 			     uint16_t *write_count);
 
 /**
@@ -366,4 +385,4 @@ int uart_console_read_buffer(uint8_t type,
  */
 void uart_init_buffer(void);
 
-#endif  /* __CROS_EC_UART_H */
+#endif /* __CROS_EC_UART_H */
diff --git a/include/update_fw.h b/include/update_fw.h
index d345c4f667..a4f56942a7 100644
--- a/include/update_fw.h
+++ b/include/update_fw.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,10 +6,10 @@
 #ifndef __CROS_EC_UPDATE_FW_H
 #define __CROS_EC_UPDATE_FW_H
 
-#include <stddef.h>
-
 #include "compile_time_macros.h"
 
+#include <stddef.h>
+
 /*
  * This file contains structures used to facilitate EC firmware updates
  * over USB (and over TPM for cr50).
@@ -43,8 +43,8 @@
  * block_base:   offset of this PDU into the flash SPI.
  */
 struct update_command {
-	uint32_t  block_digest;
-	uint32_t  block_base;
+	uint32_t block_digest;
+	uint32_t block_base;
 	/* The actual payload goes here. */
 } __packed;
 
@@ -112,8 +112,8 @@ struct first_response_pdu {
 		/* cr50 (header_type = UPDATE_HEADER_TYPE_CR50) */
 		struct {
 			/* The below fields are present in versions 3 and up. */
-			uint32_t  backup_ro_offset;
-			uint32_t  backup_rw_offset;
+			uint32_t backup_ro_offset;
+			uint32_t backup_rw_offset;
 
 			/* The below fields are present in versions 4 and up. */
 			/*
@@ -154,8 +154,8 @@ enum first_response_pdu_header_type {
 };
 
 /* TODO: Handle this in update_fw.c, not usb_update.c */
-#define UPDATE_DONE          0xB007AB1E
-#define UPDATE_EXTRA_CMD     0xB007AB1F
+#define UPDATE_DONE 0xB007AB1E
+#define UPDATE_EXTRA_CMD 0xB007AB1F
 
 enum update_extra_command {
 	UPDATE_EXTRA_CMD_IMMEDIATE_RESET = 0,
@@ -235,8 +235,7 @@ struct touchpad_info {
  */
 BUILD_ASSERT(sizeof(struct touchpad_info) <= 50);
 
-void fw_update_command_handler(void *body,
-			       size_t cmd_size,
+void fw_update_command_handler(void *body, size_t cmd_size,
 			       size_t *response_size);
 
 /* Used to tell fw update the update ran successfully and is finished */
@@ -286,4 +285,4 @@ int touchpad_debug(const uint8_t *param, unsigned int param_size,
 /* SHA256 hash of the touchpad firmware expected by this image. */
 extern const uint8_t touchpad_fw_full_hash[32];
 
-#endif  /* ! __CROS_EC_UPDATE_FW_H */
+#endif /* ! __CROS_EC_UPDATE_FW_H */
diff --git a/include/usb_api.h b/include/usb_api.h
index 79ee9406e9..85e82d11e0 100644
--- a/include/usb_api.h
+++ b/include/usb_api.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -76,7 +76,9 @@ void usb_restore_suspended_state(void);
 #ifdef CONFIG_USB_REMOTE_WAKEUP
 void usb_wake(void);
 #else
-static inline void usb_wake(void) {}
+static inline void usb_wake(void)
+{
+}
 #endif
 
 /* Board-specific USB wake, for side-band wake, called by usb_wake above. */
diff --git a/include/usb_bb.h b/include/usb_bb.h
index 24225250be..d28d4be441 100644
--- a/include/usb_bb.h
+++ b/include/usb_bb.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -17,7 +17,6 @@
 #define USB_BB_EP0_PACKET_SIZE 8
 #define USB_BB_CAP_DESC_TYPE 0x0d
 
-
 #define USB_BB_CAPS_SVID_SIZE 4
 struct usb_bb_caps_svid_descriptor {
 	uint16_t wSVID;
@@ -38,17 +37,14 @@ struct usb_bb_caps_base_descriptor {
 	uint32_t bReserved; /* SBZ */
 } __packed;
 
-
-#define USB_BB_VCONN_PWRON(x)    (x << 15)
-#define USB_BB_VCONN_PWR_1W      0
-#define USB_BB_VCONN_PWR_1p5W    1
-#define USB_BB_VCONN_PWR_2W      2
-#define USB_BB_VCONN_PWR_3W      3
-#define USB_BB_VCONN_PWR_4W      4
-#define USB_BB_VCONN_PWR_5W      5
-#define USB_BB_VCONN_PWR_6W      6
+#define USB_BB_VCONN_PWRON(x) (x << 15)
+#define USB_BB_VCONN_PWR_1W 0
+#define USB_BB_VCONN_PWR_1p5W 1
+#define USB_BB_VCONN_PWR_2W 2
+#define USB_BB_VCONN_PWR_3W 3
+#define USB_BB_VCONN_PWR_4W 4
+#define USB_BB_VCONN_PWR_5W 5
+#define USB_BB_VCONN_PWR_6W 6
 /* Note, 7W (111b) is reserved */
 
-
 #endif /* __CROS_EC_USB_BB_H */
-
diff --git a/include/usb_charge.h b/include/usb_charge.h
index dd0f221c28..290471c1c9 100644
--- a/include/usb_charge.h
+++ b/include/usb_charge.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,9 +11,10 @@
 #include "charge_manager.h"
 #include "common.h"
 #include "ec_commands.h"
+#include "task.h"
 
 /* USB charger voltage */
-#define USB_CHARGER_VOLTAGE_MV  5000
+#define USB_CHARGER_VOLTAGE_MV 5000
 /* USB charger minimum current */
 #define USB_CHARGER_MIN_CURR_MA 500
 /*
@@ -54,37 +55,36 @@ extern const int usb_port_enable[USB_PORT_ENABLE_COUNT];
 int usb_charge_set_mode(int usb_port_id, enum usb_charge_mode mode,
 			enum usb_suspend_charge inhibit_charge);
 
-#define USB_CHG_EVENT_BC12	TASK_EVENT_CUSTOM_BIT(0)
-#define USB_CHG_EVENT_VBUS	TASK_EVENT_CUSTOM_BIT(1)
-#define USB_CHG_EVENT_INTR	TASK_EVENT_CUSTOM_BIT(2)
-#define USB_CHG_EVENT_DR_UFP	TASK_EVENT_CUSTOM_BIT(3)
-#define USB_CHG_EVENT_DR_DFP	TASK_EVENT_CUSTOM_BIT(4)
-#define USB_CHG_EVENT_CC_OPEN	TASK_EVENT_CUSTOM_BIT(5)
-#define USB_CHG_EVENT_MUX	TASK_EVENT_CUSTOM_BIT(6)
-
-/* Number of USB_CHG_* tasks */
-#ifdef HAS_TASK_USB_CHG_P2
-#define USB_CHG_TASK_COUNT 3
-#elif defined(HAS_TASK_USB_CHG_P1)
-#define USB_CHG_TASK_COUNT 2
-#elif defined(HAS_TASK_USB_CHG_P0) || defined(HAS_TASK_USB_CHG)
-#define USB_CHG_TASK_COUNT 1
+#ifdef CONFIG_PLATFORM_EC_USB_CHARGER_SINGLE_TASK
+/*
+ * In single task mode we pack the event bits for up to 4 ports in a 32 bit
+ * atomic, make sure we don't define more than 8 event bits per port.
+ */
+#define USB_CHARGER_EVENT_BIT(x) BUILD_CHECK_INLINE(BIT(x), BIT(x) & 0xff)
 #else
-#define USB_CHG_TASK_COUNT 0
+#define USB_CHARGER_EVENT_BIT(x) TASK_EVENT_CUSTOM_BIT(x)
 #endif
 
+#define USB_CHG_EVENT_BC12 USB_CHARGER_EVENT_BIT(0)
+#define USB_CHG_EVENT_VBUS USB_CHARGER_EVENT_BIT(1)
+#define USB_CHG_EVENT_INTR USB_CHARGER_EVENT_BIT(2)
+#define USB_CHG_EVENT_DR_UFP USB_CHARGER_EVENT_BIT(3)
+#define USB_CHG_EVENT_DR_DFP USB_CHARGER_EVENT_BIT(4)
+#define USB_CHG_EVENT_CC_OPEN USB_CHARGER_EVENT_BIT(5)
+#define USB_CHG_EVENT_MUX USB_CHARGER_EVENT_BIT(6)
+
 /*
- * Define USB_CHG_PORT_TO_TASK_ID() and TASK_ID_TO_USB_CHG__PORT() macros to
+ * Define USB_CHG_PORT_TO_TASK_ID() and TASK_ID_TO_USB_CHG_PORT() macros to
  * go between USB_CHG port number and task ID. Assume that TASK_ID_USB_CHG_P0,
  * is the lowest task ID and IDs are on a continuous range.
  */
 #ifdef HAS_TASK_USB_CHG_P0
 #define USB_CHG_PORT_TO_TASK_ID(port) (TASK_ID_USB_CHG_P0 + (port))
-#define TASK_ID_TO_USB_CHG_PORT(id) ((id) - TASK_ID_USB_CHG_P0)
+#define TASK_ID_TO_USB_CHG_PORT(id) ((id)-TASK_ID_USB_CHG_P0)
 #else
 #define USB_CHG_PORT_TO_TASK_ID(port) -1 /* stub task ID */
 #define TASK_ID_TO_USB_CHG_PORT(id) 0
-#endif  /* HAS_TASK_USB_CHG_P0 */
+#endif /* HAS_TASK_USB_CHG_P0 */
 
 /**
  * Returns true if the passed port is a power source.
@@ -103,8 +103,10 @@ enum usb_switch {
 struct bc12_drv {
 	/* All fields below are optional */
 
-	/* BC1.2 detection task for this chip */
-	void (*usb_charger_task)(int port);
+	/* BC1.2 detection task init for this chip */
+	void (*usb_charger_task_init)(int port);
+	/* BC1.2 detection task process for this chip */
+	void (*usb_charger_task_event)(int port, uint32_t evt);
 	/* Configure USB data switches on type-C port */
 	void (*set_switches)(int port, enum usb_switch setting);
 	/* Check if ramping is allowed for given supplier */
@@ -149,7 +151,7 @@ void usb_charger_vbus_change(int port, int vbus_level);
  * Check if ramping is allowed for given supplier
  *
  * @param port port number.
- * @supplier Supplier to check
+ * @param supplier Supplier to check
  *
  * @return Ramping is allowed for given supplier
  */
@@ -164,8 +166,8 @@ static inline int usb_charger_ramp_allowed(int port, int supplier)
  * Get the maximum current limit that we are allowed to ramp to
  *
  * @param port port number.
- * @supplier Active supplier type
- * @sup_curr Input current limit based on supplier
+ * @param supplier Active supplier type
+ * @param sup_curr Input current limit based on supplier
  *
  * @return Maximum current in mA
  */
@@ -176,10 +178,54 @@ static inline int usb_charger_ramp_max(int port, int supplier, int sup_curr)
 	return bc12_ports[port].drv->ramp_max(supplier, sup_curr);
 }
 
+/**
+ * Set a task event for a specific usb charger port
+ *
+ * @param port port number
+ * @param event event bits (USB_CHG_EVENT_*)
+ */
+void usb_charger_task_set_event(int port, uint8_t event);
+
+/**
+ * Synchronously handle an event for a specific USB charger port.
+ *
+ * This is the same as using usb_charger_task_set_event for a given port
+ * and event, but executes synchronously (on the calling thread) instead of
+ * asynchronously (on the dedicated USB charger thread).
+ *
+ * Most users should prefer to use the asynchronous equivalent, but it is
+ * sometimes necessary to use this version in order to avoid priority inversion
+ * when a higher-priority task must ensure BC1.2 processing completes before
+ * continuing.
+ */
+void usb_charger_task_set_event_sync(int port, uint8_t event);
+
 /**
  * Reset available BC 1.2 chargers on all ports
+ *
  * @param port
  */
 void usb_charger_reset_charge(int port);
 
-#endif  /* __CROS_EC_USB_CHARGE_H */
+/**
+ * Check if a particular port is sourcing VBUS
+ *
+ * This function is typically defined in the board file
+ *
+ * @param port port number
+ * @return 0 if not source, non-zero if sourcing
+ */
+int board_is_sourcing_vbus(int port);
+
+/**
+ * Enable VBUS sink for a given port
+ *
+ * This function is typically defined in the board file
+ *
+ * @param port port number
+ * @param enable 0 to disable, 1 to enable
+ * @return EC_SUCCESS if OK, EC_ERROR_INVAL if @port is invalid
+ */
+int board_vbus_sink_enable(int port, int enable);
+
+#endif /* __CROS_EC_USB_CHARGE_H */
diff --git a/include/usb_common.h b/include/usb_common.h
index 1e92a4b22a..f93178322e 100644
--- a/include/usb_common.h
+++ b/include/usb_common.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,6 +6,7 @@
 #define __CROS_EC_USB_COMMON_H
 
 /* Functions that are shared between old and new PD stacks */
+#include "ec_commands.h"
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
@@ -33,10 +34,10 @@ enum pd_drp_next_states {
  *			us of a connection.
  *
  */
-enum pd_drp_next_states drp_auto_toggle_next_state(uint64_t *drp_sink_time,
-	enum pd_power_role power_role, enum pd_dual_role_states drp_state,
-	enum tcpc_cc_voltage_status cc1, enum tcpc_cc_voltage_status cc2,
-	bool auto_toggle_supported);
+enum pd_drp_next_states drp_auto_toggle_next_state(
+	uint64_t *drp_sink_time, enum pd_power_role power_role,
+	enum pd_dual_role_states drp_state, enum tcpc_cc_voltage_status cc1,
+	enum tcpc_cc_voltage_status cc2, bool auto_toggle_supported);
 
 enum pd_pref_type {
 	/* prefer voltage larger than or equal to pd_pref_config.mv */
@@ -67,19 +68,15 @@ struct pd_pref_config_t {
 int hex8tou32(char *str, uint32_t *val);
 
 /*
- * Flash a USB PD device using the ChromeOS Vendor Defined Command.
- *
- * @param argc number arguments in argv. Must be greater than 3.
- * @param argv [1] is the usb port
- *             [2] unused
- *             [3] is the command {"erase", "rebooot", "signature",
- *                                 "info", "version", "write"}
- *             [4] if command was "write", then this will be the
- *                 start of the data that will be written.
- * @return EC_SUCCESS on success, else EC_ERROR_PARAM_COUNT or EC_ERROR_PARAM2
- *         on failure.
+ * When AP requests to suspend PD traffic on the EC so it can do
+ * firmware upgrade (retimer firmware, or TCPC chips firmware),
+ * it calls this function to check if power is ready for performing
+ * the upgrade.
+ * @param port USB-C port number
+ * @dreturn true  - power is ready
+ *          false - power is not ready
  */
-int remote_flashing(int argc, char **argv);
+bool pd_firmware_upgrade_check_power_readiness(int port);
 
 /* Returns the battery percentage [0-100] of the system. */
 int usb_get_battery_soc(void);
@@ -94,7 +91,8 @@ int usb_get_battery_soc(void);
  * @return current limit (mA) with DTS flag set if appropriate
  */
 typec_current_t usb_get_typec_current_limit(enum tcpc_cc_polarity polarity,
-	enum tcpc_cc_voltage_status cc1, enum tcpc_cc_voltage_status cc2);
+					    enum tcpc_cc_voltage_status cc1,
+					    enum tcpc_cc_voltage_status cc2);
 
 /**
  * Returns the polarity of a Sink.
@@ -104,7 +102,7 @@ typec_current_t usb_get_typec_current_limit(enum tcpc_cc_polarity polarity,
  * @return polarity
  */
 enum tcpc_cc_polarity get_snk_polarity(enum tcpc_cc_voltage_status cc1,
-	enum tcpc_cc_voltage_status cc2);
+				       enum tcpc_cc_voltage_status cc2);
 
 /**
  * Returns the polarity of a Source.
@@ -114,7 +112,7 @@ enum tcpc_cc_polarity get_snk_polarity(enum tcpc_cc_voltage_status cc1,
  * @return polarity
  */
 enum tcpc_cc_polarity get_src_polarity(enum tcpc_cc_voltage_status cc1,
-	enum tcpc_cc_voltage_status cc2);
+				       enum tcpc_cc_voltage_status cc2);
 
 /**
  * Find PDO index that offers the most amount of power and stays within
@@ -126,17 +124,19 @@ enum tcpc_cc_polarity get_src_polarity(enum tcpc_cc_voltage_status cc1,
  * @param pdo raw pdo corresponding to index, or index 0 on error (output)
  * @return index of PDO within source cap packet
  */
-int pd_find_pdo_index(uint32_t src_cap_cnt, const uint32_t * const src_caps,
-	int max_mv, uint32_t *selected_pdo);
+int pd_find_pdo_index(uint32_t src_cap_cnt, const uint32_t *const src_caps,
+		      int max_mv, uint32_t *selected_pdo);
 
 /**
  * Extract power information out of a Power Data Object (PDO)
  *
  * @param pdo raw pdo to extract
  * @param ma current of the PDO (output)
- * @param mv voltage of the PDO (output)
+ * @param max_mv maximum voltage of the PDO (output)
+ * @param min_mv minimum voltage of the PDO (output)
  */
-void pd_extract_pdo_power(uint32_t pdo, uint32_t *ma, uint32_t *mv);
+void pd_extract_pdo_power(uint32_t pdo, uint32_t *ma, uint32_t *max_mv,
+			  uint32_t *min_mv);
 
 /**
  * Decide which PDO to choose from the source capabilities.
@@ -148,7 +148,7 @@ void pd_extract_pdo_power(uint32_t pdo, uint32_t *ma, uint32_t *mv);
  * @param port USB-C port number
  */
 void pd_build_request(int32_t vpd_vdo, uint32_t *rdo, uint32_t *ma,
-			uint32_t *mv, int port);
+		      uint32_t *mv, int port);
 
 /**
  * Notifies a task that is waiting on a system jump, that it's complete.
@@ -162,6 +162,16 @@ void notify_sysjump_ready(void);
  */
 void set_usb_mux_with_current_data_role(int port);
 
+/**
+ * Check if the mux should be set to enable USB3.1 mode based only on being in a
+ * UFP data role. This is mode is required when attached to a port partner that
+ * is type-c only, but still needs to enable USB3.1 mode.
+ *
+ * @param port USB-C port number
+ * @return true if USB3 mode should be enabled, false otherwise
+ */
+__override_proto bool usb_ufp_check_usb3_enable(int port);
+
 /**
  * Configure the USB MUX in safe mode.
  * Before entering into alternate mode, state of the USB-C MUX needs to be in
@@ -173,6 +183,17 @@ void set_usb_mux_with_current_data_role(int port);
  */
 void usb_mux_set_safe_mode(int port);
 
+/**
+ * Configure the USB MUX in safe mode while exiting an alternate mode.
+ * Although the TCSS (virtual mux) has a distinct safe mode state, it
+ * needs to be in a disconnected state to properly exit an alternate
+ * mode. Therefore, do not treat the virtual mux as a special case, as
+ * usb_mux_set_safe_mode does.
+ *
+ * @param port The PD port number
+ */
+void usb_mux_set_safe_mode_exit(int port);
+
 /**
  * Get the PD flags stored in BB Ram
  *
@@ -192,12 +213,74 @@ int pd_get_saved_port_flags(int port, uint8_t *flags);
 void pd_update_saved_port_flags(int port, uint8_t flag, uint8_t do_set);
 
 /**
- * Build PD alert message
+ * Sets up and sends PD alert message with given ADO on all ports.
+ *
+ * @param ado - Alert Data Object defining alert sent to the PD partner
+ * @return EC_SUCCESS on success else EC_ERROR_INVAL
+ */
+int pd_broadcast_alert_msg(uint32_t ado);
+
+/**
+ * Sets up and sends PD alert message with given ADO on one port.
  *
- * @param msg pointer where message is stored
- * @param len pointer where length of message is stored in bytes
- * @param pr  current PD power role
+ * @param port - the port to send the alert message on
+ * @param ado - Alert Data Object defining alert sent to the PD partner
  * @return EC_SUCCESS on success else EC_ERROR_INVAL
  */
-int pd_build_alert_msg(uint32_t *msg, uint32_t *len, enum pd_power_role pr);
+int pd_send_alert_msg(int port, uint32_t ado);
+
+/**
+ * Sets up a hard reset to send on the port
+ *
+ * @param port - the port to send the hard reset on
+ */
+void pd_send_hard_reset(int port);
+
+/**
+ * During USB retimer firmware update, process operation
+ * requested by AP
+ *
+ * @param port USB-C port number
+ * @param op
+ *       0 - USB_RETIMER_FW_UPDATE_QUERY_PORT
+ *       1 - USB_RETIMER_FW_UPDATE_SUSPEND_PD
+ *       2 - USB_RETIMER_FW_UPDATE_RESUME_PD
+ *       3 - USB_RETIMER_FW_UPDATE_GET_MUX
+ *       4 - USB_RETIMER_FW_UPDATE_SET_USB
+ *       5 - USB_RETIMER_FW_UPDATE_SET_SAFE
+ *       6 - USB_RETIMER_FW_UPDATE_SET_TBT
+ *       7 - USB_RETIMER_FW_UPDATE_DISCONNECT
+ */
+void usb_retimer_fw_update_process_op(int port, int op);
+
+/**
+ * Get result of last USB retimer firmware update operation requested
+ * by AP. Result is passed to AP via EC_CMD_ACPI_READ.
+ *
+ * @return Result of last operation. It's
+ *         which port has retimer if last operation is
+ *         USB_RETIMER_FW_UPDATE_QUERY_PORT;
+ *         PD task is enabled or not if last operations are
+ *         USB_RETIMER_FW_UPDATE_SUSPEND_PD or
+ *         USB_RETIMER_FW_UPDATE_QUERY_PORT;
+ *         current mux if last operations are
+ *         USB_RETIMER_FW_UPDATE_GET_MUX, USB_RETIMER_FW_UPDATE_SET_USB,
+ *         USB_RETIMER_FW_UPDATE_SET_SAFE, USB_RETIMER_FW_UPDATE_SET_TBT,
+ *         or USB_RETIMER_FW_UPDATE_DISCONNECT.
+ */
+int usb_retimer_fw_update_get_result(void);
+
+/**
+ * Process deferred retimer firmware update operations.
+ *
+ * @param port USB-C port number
+ */
+void usb_retimer_fw_update_process_op_cb(int port);
+
+/**
+ * Dump SourceCap information.
+ *
+ * @param port USB-C port number
+ */
+void pd_srccaps_dump(int port);
 #endif /* __CROS_EC_USB_COMMON_H */
diff --git a/include/usb_console.h b/include/usb_console.h
index 2e0aa7dfa6..cbc322ce6c 100644
--- a/include/usb_console.h
+++ b/include/usb_console.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -80,7 +80,7 @@ int usb_console_tx_blocked(void);
 #define usb_getc(x) (-1)
 #define usb_va_start(x, y)
 #define usb_va_end(x)
-#define usb_console_tx_blocked()	(0)
+#define usb_console_tx_blocked() (0)
 #endif
 
 #endif /* __CROS_EC_USB_CONSOLE_H */
diff --git a/include/usb_descriptor.h b/include/usb_descriptor.h
index 49114c38e0..e11b263b2f 100644
--- a/include/usb_descriptor.h
+++ b/include/usb_descriptor.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,24 +8,24 @@
 #ifndef __CROS_EC_USB_DESCRIPTOR_H
 #define __CROS_EC_USB_DESCRIPTOR_H
 
-#include <stddef.h> /* for wchar_t */
+#include <stdint.h>
 
 #define USB_MAX_PACKET_SIZE 64
 
 /* USB 2.0 chapter 9 definitions */
 
 /* Descriptor types */
-#define USB_DT_DEVICE                     0x01
-#define USB_DT_CONFIGURATION              0x02
-#define USB_DT_STRING                     0x03
-#define USB_DT_INTERFACE                  0x04
-#define USB_DT_ENDPOINT                   0x05
-#define USB_DT_DEVICE_QUALIFIER           0x06
-#define USB_DT_OTHER_SPEED_CONFIG         0x07
-#define USB_DT_INTERFACE_POWER            0x08
-#define USB_DT_DEBUG                      0x0a
-#define USB_DT_BOS                        0x0f
-#define USB_DT_DEVICE_CAPABILITY          0x10
+#define USB_DT_DEVICE 0x01
+#define USB_DT_CONFIGURATION 0x02
+#define USB_DT_STRING 0x03
+#define USB_DT_INTERFACE 0x04
+#define USB_DT_ENDPOINT 0x05
+#define USB_DT_DEVICE_QUALIFIER 0x06
+#define USB_DT_OTHER_SPEED_CONFIG 0x07
+#define USB_DT_INTERFACE_POWER 0x08
+#define USB_DT_DEBUG 0x0a
+#define USB_DT_BOS 0x0f
+#define USB_DT_DEVICE_CAPABILITY 0x10
 
 /* USB Device Descriptor */
 struct usb_device_descriptor {
@@ -44,7 +44,7 @@ struct usb_device_descriptor {
 	uint8_t iSerialNumber;
 	uint8_t bNumConfigurations;
 } __packed;
-#define USB_DT_DEVICE_SIZE                18
+#define USB_DT_DEVICE_SIZE 18
 
 /* BOS Descriptor ( USB3.1 rev1 Section 9.6.2 ) */
 struct bos_context {
@@ -55,280 +55,335 @@ struct bos_context {
 struct usb_bos_hdr_descriptor {
 	uint8_t bLength;
 	uint8_t bDescriptorType; /* USB_DT_BOS */
-	uint16_t wTotalLength;   /* Total length of of hdr + all dev caps */
-	uint8_t bNumDeviceCaps;  /* Container ID Descriptor + others */
+	uint16_t wTotalLength; /* Total length of of hdr + all dev caps */
+	uint8_t bNumDeviceCaps; /* Container ID Descriptor + others */
 } __packed;
 #define USB_DT_BOS_SIZE 5
 
 /* Container ID Descriptor */
 struct usb_contid_caps_descriptor {
-	uint8_t  bLength;
-	uint8_t  bDescriptorType;     /* USB_DT_DEVICE_CAPABILITY */
-	uint8_t  bDevCapabilityType;  /* USB_DC_DTYPE_xxx */
-	uint8_t  bReserved;           /* SBZ */
-	uint8_t  ContainerID[16];     /* UUID */
+	uint8_t bLength;
+	uint8_t bDescriptorType; /* USB_DT_DEVICE_CAPABILITY */
+	uint8_t bDevCapabilityType; /* USB_DC_DTYPE_xxx */
+	uint8_t bReserved; /* SBZ */
+	uint8_t ContainerID[16]; /* UUID */
 } __packed;
-#define USB_DT_CONTID_SIZE         20
+#define USB_DT_CONTID_SIZE 20
 
 /* Device Cap Type Codes ( offset 2 of Device Capability Descriptor */
-#define USB_DC_DTYPE_WIRELESS  0x01
-#define USB_DC_DTYPE_USB20EXT  0x02
-#define USB_DC_DTYPE_USBSS     0x03
-#define USB_DC_DTYPE_CONTID    0x04
-#define USB_DC_DTYPE_PLATFORM  0x05
-#define USB_DC_DTYPE_PD        0x06
-#define USB_DC_DTYPE_BATTINFO  0x07
-#define USB_DC_DTYPE_CONSUMER  0x08
-#define USB_DC_DTYPE_PRODUCER  0x09
-#define USB_DC_DTYPE_USBSSP    0x0a
-#define USB_DC_DTYPE_PCSTIME   0x0b
-#define USB_DC_DTYPE_WUSBEXT   0x0c
+#define USB_DC_DTYPE_WIRELESS 0x01
+#define USB_DC_DTYPE_USB20EXT 0x02
+#define USB_DC_DTYPE_USBSS 0x03
+#define USB_DC_DTYPE_CONTID 0x04
+#define USB_DC_DTYPE_PLATFORM 0x05
+#define USB_DC_DTYPE_PD 0x06
+#define USB_DC_DTYPE_BATTINFO 0x07
+#define USB_DC_DTYPE_CONSUMER 0x08
+#define USB_DC_DTYPE_PRODUCER 0x09
+#define USB_DC_DTYPE_USBSSP 0x0a
+#define USB_DC_DTYPE_PCSTIME 0x0b
+#define USB_DC_DTYPE_WUSBEXT 0x0c
 #define USB_DC_DTYPE_BILLBOARD 0x0d
 /* RESERVED 0x00, 0xOe - 0xff */
 
 /* Platform descriptor */
 struct usb_platform_descriptor {
-	uint8_t  bLength;
-	uint8_t  bDescriptorType;     /* USB_DT_DEVICE_CAPABILITY */
-	uint8_t  bDevCapabilityType;  /* USB_DC_DTYPE_PLATFORM */
-	uint8_t  bReserved;           /* SBZ */
-	uint8_t  PlatformCapUUID[16]; /* USB_PLAT_CAP_xxx */
-	uint16_t bcdVersion;          /* 0x0100 */
-	uint8_t  bVendorCode;
-	uint8_t  iLandingPage;
+	uint8_t bLength;
+	uint8_t bDescriptorType; /* USB_DT_DEVICE_CAPABILITY */
+	uint8_t bDevCapabilityType; /* USB_DC_DTYPE_PLATFORM */
+	uint8_t bReserved; /* SBZ */
+	uint8_t PlatformCapUUID[16]; /* USB_PLAT_CAP_xxx */
+	uint16_t bcdVersion; /* 0x0100 */
+	uint8_t bVendorCode;
+	uint8_t iLandingPage;
 } __packed;
-#define USB_DT_PLATFORM_SIZE   24
+#define USB_DT_PLATFORM_SIZE 24
 
 /* Platform Capability UUIDs */
-#define USB_PLAT_CAP_WEBUSB /*{3408b638-09a9-47a0-8bfd-a0768815b665}*/ \
-	{0x38, 0xB6, 0x08, 0x34, 0xA9, 0x09, 0xA0, 0x47,               \
-	 0x8B, 0xFD, 0xA0, 0x76, 0x88, 0x15, 0xB6, 0x65}
+#define USB_PLAT_CAP_WEBUSB /*{3408b638-09a9-47a0-8bfd-a0768815b665}*/      \
+	{                                                                   \
+		0x38, 0xB6, 0x08, 0x34, 0xA9, 0x09, 0xA0, 0x47, 0x8B, 0xFD, \
+			0xA0, 0x76, 0x88, 0x15, 0xB6, 0x65                  \
+	}
 
 /* Qualifier Descriptor */
 struct usb_qualifier_descriptor {
-	uint8_t  bLength;
-	uint8_t  bDescriptorType;
+	uint8_t bLength;
+	uint8_t bDescriptorType;
 	uint16_t bcdUSB;
-	uint8_t  bDeviceClass;
-	uint8_t  bDeviceSubClass;
-	uint8_t  bDeviceProtocol;
-	uint8_t  bMaxPacketSize0;
-	uint8_t  bNumConfigurations;
-	uint8_t  bReserved;
+	uint8_t bDeviceClass;
+	uint8_t bDeviceSubClass;
+	uint8_t bDeviceProtocol;
+	uint8_t bMaxPacketSize0;
+	uint8_t bNumConfigurations;
+	uint8_t bReserved;
 } __packed;
-#define USB_DT_QUALIFIER_SIZE		10
+#define USB_DT_QUALIFIER_SIZE 10
 
 /* Configuration Descriptor */
 struct usb_config_descriptor {
-	uint8_t  bLength;
-	uint8_t  bDescriptorType;
+	uint8_t bLength;
+	uint8_t bDescriptorType;
 	uint16_t wTotalLength;
-	uint8_t  bNumInterfaces;
-	uint8_t  bConfigurationValue;
-	uint8_t  iConfiguration;
-	uint8_t  bmAttributes;
-	uint8_t  bMaxPower;
+	uint8_t bNumInterfaces;
+	uint8_t bConfigurationValue;
+	uint8_t iConfiguration;
+	uint8_t bmAttributes;
+	uint8_t bMaxPower;
 } __packed;
-#define USB_DT_CONFIG_SIZE                9
+#define USB_DT_CONFIG_SIZE 9
 
 /* String Descriptor */
 struct usb_string_descriptor {
-	uint8_t  bLength;
-	uint8_t  bDescriptorType;
+	uint8_t bLength;
+	uint8_t bDescriptorType;
 	uint16_t wData[1];
 } __packed;
 
 /* Interface Descriptor */
 struct usb_interface_descriptor {
-	uint8_t  bLength;
-	uint8_t  bDescriptorType;
-	uint8_t  bInterfaceNumber;
-	uint8_t  bAlternateSetting;
-	uint8_t  bNumEndpoints;
-	uint8_t  bInterfaceClass;
-	uint8_t  bInterfaceSubClass;
-	uint8_t  bInterfaceProtocol;
-	uint8_t  iInterface;
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	uint8_t bInterfaceNumber;
+	uint8_t bAlternateSetting;
+	uint8_t bNumEndpoints;
+	uint8_t bInterfaceClass;
+	uint8_t bInterfaceSubClass;
+	uint8_t bInterfaceProtocol;
+	uint8_t iInterface;
 } __packed;
-#define USB_DT_INTERFACE_SIZE           9
+#define USB_DT_INTERFACE_SIZE 9
 
 /* Endpoint Descriptor */
 struct usb_endpoint_descriptor {
-	uint8_t  bLength;
-	uint8_t  bDescriptorType;
-	uint8_t  bEndpointAddress;
-	uint8_t  bmAttributes;
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	uint8_t bEndpointAddress;
+	uint8_t bmAttributes;
 	uint16_t wMaxPacketSize;
-	uint8_t  bInterval;
+	uint8_t bInterval;
 } __packed;
-#define USB_DT_ENDPOINT_SIZE            7
+#define USB_DT_ENDPOINT_SIZE 7
 
 /* USB Class codes */
-#define USB_CLASS_PER_INTERFACE           0x00
-#define USB_CLASS_AUDIO                   0x01
-#define USB_CLASS_COMM                    0x02
-#define USB_CLASS_HID                     0x03
-#define USB_CLASS_PHYSICAL                0x05
-#define USB_CLASS_STILL_IMAGE             0x06
-#define USB_CLASS_PRINTER                 0x07
-#define USB_CLASS_MASS_STORAGE            0x08
-#define USB_CLASS_HUB                     0x09
-#define USB_CLASS_CDC_DATA                0x0a
-#define USB_CLASS_CSCID                   0x0b
-#define USB_CLASS_CONTENT_SEC             0x0d
-#define USB_CLASS_VIDEO                   0x0e
-#define USB_CLASS_BILLBOARD               0x11
-#define USB_CLASS_WIRELESS_CONTROLLER     0xe0
-#define USB_CLASS_MISC                    0xef
-#define USB_CLASS_APP_SPEC                0xfe
-#define USB_CLASS_VENDOR_SPEC             0xff
-
-/* USB Vendor ID assigned to Google Inc. */
+#define USB_CLASS_PER_INTERFACE 0x00
+#define USB_CLASS_AUDIO 0x01
+#define USB_CLASS_COMM 0x02
+#define USB_CLASS_HID 0x03
+#define USB_CLASS_PHYSICAL 0x05
+#define USB_CLASS_STILL_IMAGE 0x06
+#define USB_CLASS_PRINTER 0x07
+#define USB_CLASS_MASS_STORAGE 0x08
+#define USB_CLASS_HUB 0x09
+#define USB_CLASS_CDC_DATA 0x0a
+#define USB_CLASS_CSCID 0x0b
+#define USB_CLASS_CONTENT_SEC 0x0d
+#define USB_CLASS_VIDEO 0x0e
+#define USB_CLASS_BILLBOARD 0x11
+#define USB_CLASS_WIRELESS_CONTROLLER 0xe0
+#define USB_CLASS_MISC 0xef
+#define USB_CLASS_APP_SPEC 0xfe
+#define USB_CLASS_VENDOR_SPEC 0xff
+
+/* USB Vendor ID assigned to Google LLC */
 #define USB_VID_GOOGLE 0x18d1
 
 /* Google specific SubClass/Protocol assignments */
 #define USB_SUBCLASS_GOOGLE_SERIAL 0x50
 #define USB_PROTOCOL_GOOGLE_SERIAL 0x01
 
-#define USB_SUBCLASS_GOOGLE_SPI    0x51
-#define USB_PROTOCOL_GOOGLE_SPI    0x02
+#define USB_SUBCLASS_GOOGLE_SPI 0x51
+#define USB_PROTOCOL_GOOGLE_SPI 0x02
 
-#define USB_SUBCLASS_GOOGLE_I2C    0x52
-#define USB_PROTOCOL_GOOGLE_I2C    0x01
+#define USB_SUBCLASS_GOOGLE_I2C 0x52
+#define USB_PROTOCOL_GOOGLE_I2C 0x01
 
 #define USB_SUBCLASS_GOOGLE_UPDATE 0x53
 #define USB_PROTOCOL_GOOGLE_UPDATE 0xff
 
 /* Double define for cr50 code freeze.
  * TODO(vbendeb): dedupe this. */
-#define USB_SUBCLASS_GOOGLE_CR50   0x53
+#define USB_SUBCLASS_GOOGLE_CR50 0x53
 /* We can use any protocol we want */
 #define USB_PROTOCOL_GOOGLE_CR50_NON_HC_FW_UPDATE 0xff
 
-#define USB_SUBCLASS_GOOGLE_POWER  0x54
-#define USB_PROTOCOL_GOOGLE_POWER  0x01
+#define USB_SUBCLASS_GOOGLE_POWER 0x54
+#define USB_PROTOCOL_GOOGLE_POWER 0x01
 
 #define USB_SUBCLASS_GOOGLE_HEATMAP 0x55
 #define USB_PROTOCOL_GOOGLE_HEATMAP 0x01
 
+#define USB_SUBCLASS_GOOGLE_HOSTCMD 0x56
+#define USB_PROTOCOL_GOOGLE_HOSTCMD 0xff
+
 /* Control requests */
 
 /* bRequestType fields */
 /* direction field */
-#define USB_DIR_OUT                0    /* from host to uC */
-#define USB_DIR_IN                 0x80 /* from uC to host */
+#define USB_DIR_OUT 0 /* from host to uC */
+#define USB_DIR_IN 0x80 /* from uC to host */
 /* type field */
-#define USB_TYPE_MASK              (0x03 << 5)
-#define USB_TYPE_STANDARD          (0x00 << 5)
-#define USB_TYPE_CLASS             (0x01 << 5)
-#define USB_TYPE_VENDOR            (0x02 << 5)
-#define USB_TYPE_RESERVED          (0x03 << 5)
+#define USB_TYPE_MASK (0x03 << 5)
+#define USB_TYPE_STANDARD (0x00 << 5)
+#define USB_TYPE_CLASS (0x01 << 5)
+#define USB_TYPE_VENDOR (0x02 << 5)
+#define USB_TYPE_RESERVED (0x03 << 5)
 /* recipient field */
-#define USB_RECIP_MASK             0x1f
-#define USB_RECIP_DEVICE           0x00
-#define USB_RECIP_INTERFACE        0x01
-#define USB_RECIP_ENDPOINT         0x02
-#define USB_RECIP_OTHER            0x03
+#define USB_RECIP_MASK 0x1f
+#define USB_RECIP_DEVICE 0x00
+#define USB_RECIP_INTERFACE 0x01
+#define USB_RECIP_ENDPOINT 0x02
+#define USB_RECIP_OTHER 0x03
 
 /* Standard requests for bRequest field in a SETUP packet. */
-#define USB_REQ_GET_STATUS         0x00
-#define USB_REQ_GET_STATUS_SELF_POWERED  BIT(0)
+#define USB_REQ_GET_STATUS 0x00
+#define USB_REQ_GET_STATUS_SELF_POWERED BIT(0)
 #define USB_REQ_GET_STATUS_REMOTE_WAKEUP BIT(1)
-#define USB_REQ_CLEAR_FEATURE      0x01
-#define USB_REQ_SET_FEATURE        0x03
-#define USB_REQ_FEATURE_ENDPOINT_HALT        0x0000
+#define USB_REQ_CLEAR_FEATURE 0x01
+#define USB_REQ_SET_FEATURE 0x03
+#define USB_REQ_FEATURE_ENDPOINT_HALT 0x0000
 #define USB_REQ_FEATURE_DEVICE_REMOTE_WAKEUP 0x0001
-#define USB_REQ_FEATURE_TEST_MODE            0x0002
-#define USB_REQ_SET_ADDRESS        0x05
-#define USB_REQ_GET_DESCRIPTOR     0x06
-#define USB_REQ_SET_DESCRIPTOR     0x07
-#define USB_REQ_GET_CONFIGURATION  0x08
-#define USB_REQ_SET_CONFIGURATION  0x09
-#define USB_REQ_GET_INTERFACE      0x0A
-#define USB_REQ_SET_INTERFACE      0x0B
-#define USB_REQ_SYNCH_FRAME        0x0C
+#define USB_REQ_FEATURE_TEST_MODE 0x0002
+#define USB_REQ_SET_ADDRESS 0x05
+#define USB_REQ_GET_DESCRIPTOR 0x06
+#define USB_REQ_SET_DESCRIPTOR 0x07
+#define USB_REQ_GET_CONFIGURATION 0x08
+#define USB_REQ_SET_CONFIGURATION 0x09
+#define USB_REQ_GET_INTERFACE 0x0A
+#define USB_REQ_SET_INTERFACE 0x0B
+#define USB_REQ_SYNCH_FRAME 0x0C
 
 /* WebUSB URL descriptors */
-#define WEBUSB_REQ_GET_URL         0x02
-#define USB_DT_WEBUSB_URL          0x03
+#define WEBUSB_REQ_GET_URL 0x02
+#define USB_DT_WEBUSB_URL 0x03
 
-#define USB_URL_SCHEME_HTTP       0x00
-#define USB_URL_SCHEME_HTTPS      0x01
-#define USB_URL_SCHEME_NONE       0xff
+#define USB_URL_SCHEME_HTTP 0x00
+#define USB_URL_SCHEME_HTTPS 0x01
+#define USB_URL_SCHEME_NONE 0xff
 
 /*
  * URL descriptor helper.
  * (similar to string descriptor but UTF-8 instead of UTF-16)
  */
-#define USB_URL_DESC(scheme, str) \
-	(const void *)&(const struct { \
-		uint8_t _len; \
-		uint8_t _type; \
-		uint8_t _scheme; \
-		char _data[sizeof(str)]; \
-	}) { \
-		/* Total size of the descriptor is : \
+#define USB_URL_DESC(scheme, str)                                  \
+	(const void *)&(const struct {                             \
+		uint8_t _len;                                      \
+		uint8_t _type;                                     \
+		uint8_t _scheme;                                   \
+		char _data[sizeof(str)];                           \
+	})                                                         \
+	{                                                          \
+		/* Total size of the descriptor is :               \
 		 * size of the UTF-8 text plus the len/type fields \
-		 * minus the string 0-termination \
-		 */ \
-		sizeof(str) + 3 - 1, \
-		USB_DT_WEBUSB_URL, \
-		USB_URL_SCHEME_##scheme, \
-		str \
+		 * minus the string 0-termination                  \
+		 */                                                \
+		sizeof(str) + 3 - 1, USB_DT_WEBUSB_URL,            \
+			USB_URL_SCHEME_##scheme, str               \
 	}
 
 /* Setup Packet */
 struct usb_setup_packet {
-	uint8_t  bmRequestType;
-	uint8_t  bRequest;
+	uint8_t bmRequestType;
+	uint8_t bRequest;
 	uint16_t wValue;
 	uint16_t wIndex;
 	uint16_t wLength;
 };
 
+/*
+ * Extended Compat ID OS Feature Descriptor Specification for Windows v1.0 USB
+ * Descriptors.
+ */
+#define USB_MS_STRING_DESC_VENDOR_CODE 0x2
+#define USB_MS_EXT_COMPATIBLE_ID_INDEX 0x4
+#define USB_GET_MS_DESCRIPTOR 0xEE
+#define USB_MS_COMPAT_ID 'W', 'I', 'N', 'U', 'S', 'B'
+#define USB_MS_COMPAT_ID_FUNCTION 1
+
+struct usb_function_section {
+	uint8_t bFirstInterfaceNumber;
+	uint8_t reserved_1;
+	uint8_t compatible_id[8];
+	uint8_t subCompatibleID[8];
+	uint8_t reserved_2[6];
+} __packed;
+
+struct usb_ms_ext_compat_id_desc {
+	uint32_t dwLength;
+	uint16_t bcdVersion;
+	uint16_t wIndex;
+	uint8_t bCount;
+	uint8_t Reserved[7];
+	/*
+	 * The spec allows for multiple function sections to be included, but
+	 * the only current use case requires just one function section to
+	 * notify Windows to use the WINUSB driver.
+	 */
+	struct usb_function_section function[USB_MS_COMPAT_ID_FUNCTION];
+} __packed;
+
 /* Helpers for descriptors */
 
 #define WIDESTR(quote) WIDESTR2(quote)
-#define WIDESTR2(quote) L##quote
-
-#define USB_STRING_DESC(str) \
-	(const void *)&(const struct { \
-		uint8_t _len; \
-		uint8_t _type; \
-		wchar_t _data[sizeof(str)]; \
-	}) { \
-		/* Total size of the descriptor is : \
-		 * size of the UTF-16 text plus the len/type fields \
-                 * minus the string 0-termination \
-                 */ \
-		sizeof(WIDESTR(str)) + 2 - 2, \
-		USB_DT_STRING, \
-		WIDESTR(str) \
+#define WIDESTR2(quote) u##quote
+
+#define USB_STRING_DESC(str)                                              \
+	(const void *)&(const struct {                                    \
+		uint8_t _len;                                             \
+		uint8_t _type;                                            \
+		uint16_t _data[sizeof(str)];                              \
+	})                                                                \
+	{                                                                 \
+		/* Total size of the descriptor is :                      \
+		 * size of the UTF-16 text plus the len/type fields       \
+		 * minus the string 0-termination                         \
+		 */                                                       \
+		sizeof(WIDESTR(str)) + 2 - 2, USB_DT_STRING, WIDESTR(str) \
 	}
 
+/*
+ * Macro to generate a string descriptor used by Windows OS which instructs
+ * windows to request a MS Compatible ID Descriptor and then enables Windows OS
+ * to load the correct driver for a USB-EP
+ */
+#define USB_MS_STRING_DESC(str)                                                \
+	((const void *)&(const struct {                                        \
+		uint8_t _len;                                                  \
+		uint8_t _type;                                                 \
+		uint16_t _data[sizeof(str) - 1];                               \
+		uint16_t _vendor;                                              \
+	}){                                                                    \
+		/* Total size of the descriptor is :                           \
+		 * size of the UTF-16 text plus the len/type fields            \
+		 * plus 2 bytes for vendor code minus the string 0-termination \
+		 */                                                            \
+		sizeof(WIDESTR(str)) + 2 - 2 + 2,                              \
+		USB_DT_STRING,                                                 \
+		WIDESTR(str),                                                  \
+		USB_MS_STRING_DESC_VENDOR_CODE,                                \
+	})
+
 #ifdef CONFIG_USB_SERIALNO
 /* String Descriptor for USB, for editable strings. */
 struct usb_string_desc {
 	uint8_t _len;
 	uint8_t _type;
-	wchar_t _data[CONFIG_SERIALNO_LEN];
+	uint16_t _data[CONFIG_SERIALNO_LEN];
 };
-#define USB_WR_STRING_DESC(str) \
-	(&(struct usb_string_desc) { \
+#define USB_WR_STRING_DESC(str)                                         \
+	(&(struct usb_string_desc){                                     \
 		/* As above, two bytes metadata, no null terminator. */ \
-		sizeof(WIDESTR(str)) + 2 - 2, \
-		USB_DT_STRING, \
-		WIDESTR(str) \
-})
+		sizeof(WIDESTR(str)) + 2 - 2, USB_DT_STRING, WIDESTR(str) })
 extern struct usb_string_desc *usb_serialno_desc;
 #endif
 
 /* Use these macros for declaring descriptors, to order them properly */
-#define USB_CONF_DESC_VAR(name, varname) varname		\
-	__keep __attribute__((section(".rodata.usb_desc_" STRINGIFY(name))))
+#define USB_CONF_DESC_VAR(name, varname) \
+	varname __keep                   \
+		__attribute__((section(".rodata.usb_desc_" STRINGIFY(name))))
 #define USB_CONF_DESC(name) USB_CONF_DESC_VAR(name, CONCAT2(usb_desc_, name))
 #define USB_IFACE_DESC(num) USB_CONF_DESC(CONCAT3(iface, num, _0iface))
-#define USB_CUSTOM_DESC_VAR(i, name, varname)			\
+#define USB_CUSTOM_DESC_VAR(i, name, varname) \
 	USB_CONF_DESC_VAR(CONCAT4(iface, i, _1, name), varname)
 #define USB_CUSTOM_DESC(i, name) USB_CONF_DESC(CONCAT4(iface, i, _1, name))
 #define USB_EP_DESC(i, num) USB_CONF_DESC(CONCAT4(iface, i, _2ep, num))
@@ -339,10 +394,10 @@ extern const uint8_t __usb_desc_end[];
 #define USB_DESC_SIZE (__usb_desc_end - __usb_desc)
 
 /* These descriptors defined in board code */
-extern const void * const usb_strings[];
+extern const void *const usb_strings[];
 extern const uint8_t usb_string_desc[];
 /* USB string descriptor with the firmware version */
-extern const void * const usb_fw_version;
+extern const void *const usb_fw_version;
 extern const struct bos_context bos_ctx;
 extern const void *webusb_url;
 
diff --git a/include/usb_dp_alt_mode.h b/include/usb_dp_alt_mode.h
index 4aceecd4ec..eb2d1a25e1 100644
--- a/include/usb_dp_alt_mode.h
+++ b/include/usb_dp_alt_mode.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,10 +12,12 @@
 #ifndef __CROS_EC_USB_DP_ALT_MODE_H
 #define __CROS_EC_USB_DP_ALT_MODE_H
 
-#include <stdint.h>
+#include "tcpm/tcpm.h"
+#include "usb_pd_dpm_sm.h"
 
-#include "tcpm.h"
+#include <stdint.h>
 
+#ifdef CONFIG_USB_PD_DP_MODE
 /*
  * Initialize DP state for the specified port.
  *
@@ -32,6 +34,27 @@ void dp_init(int port);
  */
 bool dp_is_active(int port);
 
+/*
+ * Returns True if DisplayPort mode entry has not started, or mode exit has
+ * already finished.
+ * TODO(b/235984702): Consolidate the DP state API
+ *
+ * @param port      USB-C port number
+ * @return          True if DisplayPort mode is in inactive state
+ *                  False otherwise.
+ */
+bool dp_is_idle(int port);
+
+/*
+ * Checks whether the mode entry sequence for DisplayPort alternate mode is done
+ * for a port.
+ *
+ * @param port      USB-C port number
+ * @return          True if entry sequence for DisplayPort mode is completed
+ *                  False otherwise
+ */
+bool dp_entry_is_done(int port);
+
 /*
  * Handles received DisplayPort VDM ACKs.
  *
@@ -40,8 +63,8 @@ bool dp_is_active(int port);
  * @param vdo_count The number of VDOs in the ACK VDM
  * @param vdm       VDM from ACK
  */
-void dp_vdm_acked(int port, enum tcpm_transmit_type type, int vdo_count,
-		uint32_t *vdm);
+void dp_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count,
+		  uint32_t *vdm);
 
 /*
  * Handles NAKed (or Not Supported or timed out) DisplayPort VDM requests.
@@ -51,25 +74,55 @@ void dp_vdm_acked(int port, enum tcpm_transmit_type type, int vdo_count,
  * @param svid    The SVID of the request
  * @param vdm_cmd The VDM command of the request
  */
-void dp_vdm_naked(int port, enum tcpm_transmit_type type, uint8_t vdm_cmd);
-
-/*
- * Reset the DisplayPort VDM state for the specified port, as when exiting
- * DisplayPort mode.
- *
- * @param port USB-C port number
- */
-void dp_teardown(int port);
+void dp_vdm_naked(int port, enum tcpci_msg_type type, uint8_t vdm_cmd);
 
 /*
  * Construct the next DisplayPort VDM that should be sent.
  *
- * @param port      USB-C port number
- * @param vdo_count The number of VDOs in vdm; must be at least VDO_MAX_SIZE
- * @param vdm       The VDM payload to be sent; output; must point to at least
- *                  VDO_MAX_SIZE elements
- * @return          The number of VDOs written to VDM or -1 to indicate error
+ * @param[in] port	    USB-C port number
+ * @param[in,out] vdo_count The number of VDOs in vdm; must be at least
+ *			    VDO_MAX_SIZE.  On success, number of populated VDOs
+ * @param[out] vdm          The VDM payload to be sent; output; must point to at
+ *			    least VDO_MAX_SIZE elements
+ * @return		    enum dpm_msg_setup_status
  */
-int dp_setup_next_vdm(int port, int vdo_count, uint32_t *vdm);
+enum dpm_msg_setup_status dp_setup_next_vdm(int port, int *vdo_count,
+					    uint32_t *vdm);
+
+#else /* CONFIG_USB_PD_DP_MODE */
+static inline void dp_init(int port)
+{
+}
+
+static inline bool dp_is_active(int port)
+{
+	return false;
+}
+
+static inline bool dp_is_idle(int port)
+{
+	return true;
+}
+
+static inline bool dp_entry_is_done(int port)
+{
+	return false;
+}
+
+static inline void dp_vdm_acked(int port, enum tcpci_msg_type type,
+				int vdo_count, uint32_t *vdm)
+{
+}
+
+static inline void dp_vdm_naked(int port, enum tcpci_msg_type type,
+				uint8_t vdm_cmd)
+{
+}
 
-#endif  /* __CROS_EC_USB_DP_ALT_MODE_H */
+static inline enum dpm_msg_setup_status
+dp_setup_next_vdm(int port, int *vdo_count, uint32_t *vdm)
+{
+	return MSG_SETUP_ERROR;
+}
+#endif /* CONFIG_USB_PD_DP_MODE */
+#endif /* __CROS_EC_USB_DP_ALT_MODE_H */
diff --git a/include/usb_emsg.h b/include/usb_emsg.h
index 7b418cefdc..181065156c 100644
--- a/include/usb_emsg.h
+++ b/include/usb_emsg.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/usb_hid.h b/include/usb_hid.h
index d8626b4dba..0d49a9b38e 100644
--- a/include/usb_hid.h
+++ b/include/usb_hid.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,34 +8,39 @@
 #ifndef __CROS_EC_USB_HID_H
 #define __CROS_EC_USB_HID_H
 
-#define USB_HID_SUBCLASS_BOOT     1
+#define USB_HID_SUBCLASS_BOOT 1
 #define USB_HID_PROTOCOL_KEYBOARD 1
-#define USB_HID_PROTOCOL_MOUSE    2
+#define USB_HID_PROTOCOL_MOUSE 2
 
 /* USB HID Class requests */
-#define USB_HID_REQ_GET_REPORT    0x01
-#define USB_HID_REQ_GET_IDLE      0x02
-#define USB_HID_REQ_GET_PROTOCOL  0x03
-#define USB_HID_REQ_SET_REPORT    0x09
-#define USB_HID_REQ_SET_IDLE      0x0A
-#define USB_HID_REQ_SET_PROTOCOL  0x0B
+#define USB_HID_REQ_GET_REPORT 0x01
+#define USB_HID_REQ_GET_IDLE 0x02
+#define USB_HID_REQ_GET_PROTOCOL 0x03
+#define USB_HID_REQ_SET_REPORT 0x09
+#define USB_HID_REQ_SET_IDLE 0x0A
+#define USB_HID_REQ_SET_PROTOCOL 0x0B
 
 /* USB HID class descriptor types */
-#define USB_HID_DT_HID            (USB_TYPE_CLASS | 0x01)
-#define USB_HID_DT_REPORT         (USB_TYPE_CLASS | 0x02)
-#define USB_HID_DT_PHYSICAL       (USB_TYPE_CLASS | 0x03)
+#define USB_HID_DT_HID (USB_TYPE_CLASS | 0x01)
+#define USB_HID_DT_REPORT (USB_TYPE_CLASS | 0x02)
+#define USB_HID_DT_PHYSICAL (USB_TYPE_CLASS | 0x03)
+
+/* Pre-defined report types */
+#define REPORT_TYPE_INPUT 0x01
+#define REPORT_TYPE_OUTPUT 0x02
+#define REPORT_TYPE_FEATURE 0x03
 
 struct usb_hid_class_descriptor {
-	uint8_t  bDescriptorType;
+	uint8_t bDescriptorType;
 	uint16_t wDescriptorLength;
 } __packed;
 
 struct usb_hid_descriptor {
-	uint8_t  bLength;
-	uint8_t  bDescriptorType;
+	uint8_t bLength;
+	uint8_t bDescriptorType;
 	uint16_t bcdHID;
-	uint8_t  bCountryCode;
-	uint8_t  bNumDescriptors;
+	uint8_t bCountryCode;
+	uint8_t bNumDescriptors;
 	struct usb_hid_class_descriptor desc[1];
 } __packed;
 
diff --git a/include/usb_hid_touchpad.h b/include/usb_hid_touchpad.h
index 1e6d4cf832..0764e32643 100644
--- a/include/usb_hid_touchpad.h
+++ b/include/usb_hid_touchpad.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,29 +8,31 @@
 #ifndef __CROS_EC_USB_HID_TOUCHPAD_H
 #define __CROS_EC_USB_HID_TOUCHPAD_H
 
+#include "common.h"
+
 #define USB_HID_TOUCHPAD_TIMESTAMP_UNIT 100 /* usec */
 
-#define REPORT_ID_TOUCHPAD		0x01
-#define REPORT_ID_DEVICE_CAPS		0x0A
-#define REPORT_ID_DEVICE_CERT		0x0B
+#define REPORT_ID_TOUCHPAD 0x01
+#define REPORT_ID_DEVICE_CAPS 0x0A
+#define REPORT_ID_DEVICE_CERT 0x0B
 
-#define MAX_FINGERS			5
+#define MAX_FINGERS 5
 
 struct usb_hid_touchpad_report {
 	uint8_t id; /* 0x01 */
 	struct {
-		uint16_t confidence:1;
-		uint16_t tip:1;
-		uint16_t inrange:1;
-		uint16_t id:4;
-		uint16_t pressure:9;
-		uint16_t width:12;
-		uint16_t height:12;
-		uint16_t x:12;
-		uint16_t y:12;
+		uint16_t confidence : 1;
+		uint16_t tip : 1;
+		uint16_t inrange : 1;
+		uint16_t id : 4;
+		uint16_t pressure : 9;
+		uint16_t width : 12;
+		uint16_t height : 12;
+		uint16_t x : 12;
+		uint16_t y : 12;
 	} __packed finger[MAX_FINGERS];
-	uint8_t count:7;
-	uint8_t button:1;
+	uint8_t count : 7;
+	uint8_t button : 1;
 	uint16_t timestamp;
 } __packed;
 
diff --git a/include/usb_i2c.h b/include/usb_i2c.h
index 5719ee4333..5c8bf8c874 100644
--- a/include/usb_i2c.h
+++ b/include/usb_i2c.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -53,7 +53,7 @@
  *         counter, the 4 bottom bits are the port address, i2c interface
  *         index.
  *
- *   - addr: slave address, 1 byte, i2c 7-bit bus address.
+ *   - addr: peripheral address, 1 byte, i2c 7-bit bus address.
  *
  *   - wc: write count, 1 byte, zero based count of bytes to write. If the
  *         indicated write count cause the payload + header exceeds 64 bytes,
@@ -99,28 +99,28 @@
  */
 
 enum usb_i2c_error {
-	USB_I2C_SUCCESS             = 0x0000,
-	USB_I2C_TIMEOUT             = 0x0001,
-	USB_I2C_BUSY                = 0x0002,
+	USB_I2C_SUCCESS = 0x0000,
+	USB_I2C_TIMEOUT = 0x0001,
+	USB_I2C_BUSY = 0x0002,
 	USB_I2C_WRITE_COUNT_INVALID = 0x0003,
-	USB_I2C_READ_COUNT_INVALID  = 0x0004,
-	USB_I2C_PORT_INVALID        = 0x0005,
-	USB_I2C_DISABLED            = 0x0006,
-	USB_I2C_MISSING_HANDLER     = 0x0007,
+	USB_I2C_READ_COUNT_INVALID = 0x0004,
+	USB_I2C_PORT_INVALID = 0x0005,
+	USB_I2C_DISABLED = 0x0006,
+	USB_I2C_MISSING_HANDLER = 0x0007,
 	USB_I2C_UNSUPPORTED_COMMAND = 0x0008,
-	USB_I2C_UNKNOWN_ERROR       = 0x8000,
+	USB_I2C_UNKNOWN_ERROR = 0x8000,
 };
 
-
 #define USB_I2C_WRITE_BUFFER (CONFIG_USB_I2C_MAX_WRITE_COUNT + 4)
 /* If read payload is larger or equal to 128 bytes, header contains rc1 */
-#define USB_I2C_READ_BUFFER  ((CONFIG_USB_I2C_MAX_READ_COUNT < 128) ?	\
-	(CONFIG_USB_I2C_MAX_READ_COUNT + 4) :				\
-	(CONFIG_USB_I2C_MAX_READ_COUNT + 6))
+#define USB_I2C_READ_BUFFER                            \
+	((CONFIG_USB_I2C_MAX_READ_COUNT < 128) ?       \
+		 (CONFIG_USB_I2C_MAX_READ_COUNT + 4) : \
+		 (CONFIG_USB_I2C_MAX_READ_COUNT + 6))
 
-#define USB_I2C_BUFFER_SIZE					\
-	(USB_I2C_READ_BUFFER > USB_I2C_WRITE_BUFFER ?	\
-		USB_I2C_READ_BUFFER : USB_I2C_WRITE_BUFFER)
+#define USB_I2C_BUFFER_SIZE                                                 \
+	(USB_I2C_READ_BUFFER > USB_I2C_WRITE_BUFFER ? USB_I2C_READ_BUFFER : \
+						      USB_I2C_WRITE_BUFFER)
 
 BUILD_ASSERT(POWER_OF_TWO(USB_I2C_READ_BUFFER));
 BUILD_ASSERT(POWER_OF_TWO(USB_I2C_WRITE_BUFFER));
@@ -156,28 +156,18 @@ extern struct consumer_ops const usb_i2c_consumer_ops;
  * ENDPOINT is the index of the USB bulk endpoint used for receiving and
  * transmitting bytes.
  */
-#define USB_I2C_CONFIG(NAME,						\
-		       INTERFACE,					\
-		       INTERFACE_NAME,					\
-		       ENDPOINT)					\
-	static uint16_t							\
-		CONCAT2(NAME, _buffer_)					\
-			[USB_I2C_BUFFER_SIZE / 2];			\
-	static void CONCAT2(NAME, _deferred_)(void);			\
-	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_));			\
-	static struct queue const CONCAT2(NAME, _to_usb_);		\
-	static struct queue const CONCAT3(usb_to_, NAME, _);		\
-	USB_STREAM_CONFIG_FULL(CONCAT2(NAME, _usb_),			\
-			       INTERFACE,				\
-			       USB_CLASS_VENDOR_SPEC,			\
-			       USB_SUBCLASS_GOOGLE_I2C,			\
-			       USB_PROTOCOL_GOOGLE_I2C,			\
-			       INTERFACE_NAME,				\
-			       ENDPOINT,				\
-			       USB_MAX_PACKET_SIZE,			\
-			       USB_MAX_PACKET_SIZE,			\
-			       CONCAT3(usb_to_, NAME, _),		\
-			       CONCAT2(NAME, _to_usb_))			\
+#define USB_I2C_CONFIG(NAME, INTERFACE, INTERFACE_NAME, ENDPOINT)              \
+	static uint16_t CONCAT2(NAME, _buffer_)[USB_I2C_BUFFER_SIZE / 2];      \
+	static void CONCAT2(NAME, _deferred_)(void);                           \
+	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_));                           \
+	static struct queue const CONCAT2(NAME, _to_usb_);                     \
+	static struct queue const CONCAT3(usb_to_, NAME, _);                   \
+	USB_STREAM_CONFIG_FULL(CONCAT2(NAME, _usb_), INTERFACE,                \
+			       USB_CLASS_VENDOR_SPEC, USB_SUBCLASS_GOOGLE_I2C, \
+			       USB_PROTOCOL_GOOGLE_I2C, INTERFACE_NAME,        \
+			       ENDPOINT, USB_MAX_PACKET_SIZE,                  \
+			       USB_MAX_PACKET_SIZE, CONCAT3(usb_to_, NAME, _), \
+			       CONCAT2(NAME, _to_usb_))                        \
 	struct usb_i2c_config const NAME = {				\
 		.buffer    = CONCAT2(NAME, _buffer_),			\
 		.deferred  = &CONCAT2(NAME, _deferred__data),		\
@@ -186,15 +176,17 @@ extern struct consumer_ops const usb_i2c_consumer_ops;
 			.ops   = &usb_i2c_consumer_ops,			\
 		},							\
 		.tx_queue = &CONCAT2(NAME, _to_usb_),			\
-	};								\
-	static struct queue const CONCAT2(NAME, _to_usb_) =		\
-		QUEUE_DIRECT(USB_I2C_READ_BUFFER, uint8_t,	\
-		null_producer, CONCAT2(NAME, _usb_).consumer);		\
-	static struct queue const CONCAT3(usb_to_, NAME, _) =		\
-		QUEUE_DIRECT(USB_I2C_WRITE_BUFFER, uint8_t,	\
-		CONCAT2(NAME, _usb_).producer, NAME.consumer);		\
-	static void CONCAT2(NAME, _deferred_)(void)			\
-	{ usb_i2c_deferred(&NAME); }
+	};                              \
+	static struct queue const CONCAT2(NAME, _to_usb_) =                    \
+		QUEUE_DIRECT(USB_I2C_READ_BUFFER, uint8_t, null_producer,      \
+			     CONCAT2(NAME, _usb_).consumer);                   \
+	static struct queue const CONCAT3(usb_to_, NAME, _) =                  \
+		QUEUE_DIRECT(USB_I2C_WRITE_BUFFER, uint8_t,                    \
+			     CONCAT2(NAME, _usb_).producer, NAME.consumer);    \
+	static void CONCAT2(NAME, _deferred_)(void)                            \
+	{                                                                      \
+		usb_i2c_deferred(&NAME);                                       \
+	}
 
 /*
  * Handle I2C request in a deferred callback.
@@ -216,7 +208,7 @@ int usb_i2c_board_is_enabled(void);
 
 /*
  * Special i2c address to use when the client is required to execute some
- * command which does not directly involve the i2c master driver.
+ * command which does not directly involve the i2c controller driver.
  */
 #define USB_I2C_CMD_ADDR_FLAGS 0x78
 
@@ -224,11 +216,7 @@ int usb_i2c_board_is_enabled(void);
  * Function to call to register a handler for commands sent to the special i2c
  * address above.
  */
-int usb_i2c_register_cros_cmd_handler(int (*cmd_handler)
-				      (void *data_in,
-				       size_t in_size,
-				       void *data_out,
-				       size_t out_size));
-
+int usb_i2c_register_cros_cmd_handler(int (*cmd_handler)(
+	void *data_in, size_t in_size, void *data_out, size_t out_size));
 
-#endif  /* __CROS_USB_I2C_H */
+#endif /* __CROS_USB_I2C_H */
diff --git a/include/usb_mode.h b/include/usb_mode.h
index a479c36d5c..5c6f71b372 100644
--- a/include/usb_mode.h
+++ b/include/usb_mode.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,9 +12,10 @@
 #ifndef __CROS_EC_USB_MODE_H
 #define __CROS_EC_USB_MODE_H
 
-#include <stdint.h>
+#include "tcpm/tcpm.h"
+#include "usb_pd_tcpm.h"
 
-#include "tcpm.h"
+#include <stdint.h>
 
 /*
  * Initialize USB4 state for the specified port.
@@ -23,6 +24,23 @@
  */
 void enter_usb_init(int port);
 
+/*
+ * Checks whether the mode entry sequence for USB4 is done for a port.
+ *
+ * @param port      USB-C port number
+ * @return          True if entry sequence for USB4 is completed
+ *                  False otherwise
+ */
+bool enter_usb_entry_is_done(int port);
+
+/*
+ * Requests the retimer and mux to exit USB4 mode and re-initalizes the USB4
+ * state machine.
+ *
+ * @param port USB-C port number
+ */
+void usb4_exit_mode_request(int port);
+
 /*
  * Resets USB4 state and mux state.
  *
@@ -31,13 +49,22 @@ void enter_usb_init(int port);
 void enter_usb_failed(int port);
 
 /*
- * Returns True if port, port partner and cable supports USB4 mode
+ * Returns True if port partner supports USB4 mode
  *
  * @param port    USB-C port number
- * @return        True if USB4 mode is supported,
+ * @return        True if USB4 mode is supported by the port partner,
  *                False otherwise
  */
-bool enter_usb_is_capable(int port);
+bool enter_usb_port_partner_is_capable(int port);
+
+/*
+ * Returns True if cable supports USB4 mode
+ *
+ * @param port    USB-C port number
+ * @return        True if USB4 mode is supported by the cable,
+ *                False otherwise
+ */
+bool enter_usb_cable_is_capable(int port);
 
 /*
  * Handles accepted USB4 response
@@ -45,7 +72,7 @@ bool enter_usb_is_capable(int port);
  * @param port    USB-C port number
  * @param type    Transmit type (SOP, SOP', SOP'') for request
  */
-void enter_usb_accepted(int port, enum tcpm_transmit_type type);
+void enter_usb_accepted(int port, enum tcpci_msg_type type);
 
 /*
  * Handles rejected USB4 response
@@ -53,13 +80,14 @@ void enter_usb_accepted(int port, enum tcpm_transmit_type type);
  * @param port    USB-C port number
  * @param type    Transmit type (SOP, SOP', SOP'') for request
  */
-void enter_usb_rejected(int port, enum tcpm_transmit_type type);
+void enter_usb_rejected(int port, enum tcpci_msg_type type);
 
 /*
  * Constructs the next USB4 EUDO that should be sent.
  *
  * @param port    USB-C port number
+ * @param type    Transmit type (SOP, SOP', SOP'') for request
  */
-uint32_t enter_usb_setup_next_msg(int port);
+uint32_t enter_usb_setup_next_msg(int port, enum tcpci_msg_type *type);
 
 #endif
diff --git a/include/usb_mux.h b/include/usb_mux.h
index 1831c621cb..8d3dbc2f7e 100644
--- a/include/usb_mux.h
+++ b/include/usb_mux.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,13 +10,31 @@
 
 #include "ec_commands.h"
 #include "i2c.h"
-#include "tcpm.h"
+#include "tcpm/tcpm.h"
 #include "usb_charge.h"
 #include "usb_pd.h"
 
+/*
+ * If compiling with Zephyr, include the USB_MUX_FLAG_ definitions that are
+ * shared with device tree
+ */
+#ifdef CONFIG_ZEPHYR
+
+#include "dt-bindings/usbc_mux.h"
+
+#else /* !CONFIG_ZEPHYR */
+
 /* Flags used for usb_mux.flags */
 #define USB_MUX_FLAG_NOT_TCPC BIT(0) /* TCPC/MUX device used only as MUX */
 #define USB_MUX_FLAG_SET_WITHOUT_FLIP BIT(1) /* SET should not flip */
+#define USB_MUX_FLAG_RESETS_IN_G3 BIT(2) /* Mux chip will reset in G3 */
+#define USB_MUX_FLAG_POLARITY_INVERTED BIT(3) /* Mux polarity is inverted */
+#define USB_MUX_FLAG_CAN_IDLE BIT(4) /* MUX supports idle mode */
+
+#endif /* CONFIG_ZEPHYR */
+
+/* usb_mux.hpd_update API only specifies 2 relevant bits in mux_state */
+#define MUX_STATE_HPD_UPDATE_MASK (USB_PD_MUX_HPD_LVL | USB_PD_MUX_HPD_IRQ)
 
 /*
  * USB-C mux state
@@ -42,11 +60,14 @@ struct usb_mux_driver {
 	/**
 	 * Set USB mux state.
 	 *
-	 * @param me usb_mux
-	 * @param mux_state State to set mux to.
+	 * @param[in]  me usb_mux
+	 * @param[in]  mux_state State to set mux to.
+	 * @param[out] bool ack_required - indication of whether this mux needs
+	 * to wait on a host command ACK at the end of a set
 	 * @return EC_SUCCESS on success, non-zero error code on failure.
 	 */
-	int (*set)(const struct usb_mux *me, mux_state_t mux_state);
+	int (*set)(const struct usb_mux *me, mux_state_t mux_state,
+		   bool *ack_required);
 
 	/**
 	 * Get current state of USB mux.
@@ -57,6 +78,14 @@ struct usb_mux_driver {
 	 */
 	int (*get)(const struct usb_mux *me, mux_state_t *mux_state);
 
+	/**
+	 * Return if retimer supports firmware update
+	 *
+	 * @return true  - supported
+	 *         false - not supported
+	 */
+	bool (*is_retimer_fw_update_capable)(void);
+
 	/**
 	 * Optional method that is called after the mux fully disconnects.
 	 *
@@ -76,6 +105,46 @@ struct usb_mux_driver {
 	 * @return EC_SUCCESS on success, non-zero error code on failure.
 	 */
 	int (*chipset_reset)(const struct usb_mux *me);
+
+	/**
+	 * Optional method that is called on HOOK_CHIPSET_{SUSPEND,RESUME}.
+	 *
+	 * Note: This notifies the mux that the rest of the system
+	 * entered (left) a low power state such as S0ix or S3. This
+	 * enables the mux driver to make power optimization decisions
+	 * such as powering down the USB3 retimer when not in use. If
+	 * the associated port is in low power mode, idle mode is not
+	 * used.
+	 *
+	 * @param me usb_mux
+	 * @param idle bool
+	 * @return EC_SUCCESS on success, non-zero error code on failure.
+	 */
+	int (*set_idle_mode)(const struct usb_mux *me, bool idle);
+
+#ifdef CONFIG_CMD_RETIMER
+	/**
+	 * Console command to read the retimer registers
+	 *
+	 * @param me usb_mux
+	 * @param offset Register offset
+	 * @param data Data to be read
+	 * @return EC_SUCCESS on success, non-zero error code on failure.
+	 */
+	int (*retimer_read)(const struct usb_mux *me, const uint32_t offset,
+			    uint32_t *data);
+
+	/**
+	 * Console command to write to the retimer registers
+	 *
+	 * @param me usb_mux
+	 * @param offset Register offset
+	 * @param data Data to be written
+	 * @return EC_SUCCESS on success, non-zero error code on failure.
+	 */
+	int (*retimer_write)(const struct usb_mux *me, const uint32_t offset,
+			     uint32_t data);
+#endif /* CONFIG_CMD_RETIMER */
 };
 
 /* Describes a USB mux present in the system */
@@ -103,9 +172,6 @@ struct usb_mux {
 	/* Mux driver */
 	const struct usb_mux_driver *driver;
 
-	/* Linked list chain of secondary MUXes. NULL terminated */
-	const struct usb_mux *next_mux;
-
 	/**
 	 * Optional method for tuning for USB mux during mux->driver->init().
 	 *
@@ -124,38 +190,51 @@ struct usb_mux {
 	int (*board_set)(const struct usb_mux *me, mux_state_t mux_state);
 
 	/*
-	 * TODO: Consider moving this to usb_mux_driver struct
-	 *
 	 * USB Type-C DP alt mode support. Notify Type-C controller
 	 * there is DP dongle hot-plug.
 	 *
-	 * @param me usb_mux
-	 * @param hpd_lvl Level
-	 * @param hpd_irq IRQ
+	 * @param[in]  me usb_mux
+	 * @param[in]  mux_state with HPD IRQ and HPD LVL flags set
+	 *	       accordingly. Other flags are undefined.
+	 * @param[out] ack_required: indication of whether this function
+	 *	       requires a wait for an AP ACK after
 	 */
-	void (*hpd_update)(const struct usb_mux *me,
-			   int hpd_lvl, int hpd_irq);
+	void (*hpd_update)(const struct usb_mux *me, mux_state_t hpd_state,
+			   bool *ack_required);
+};
+
+/* Linked list chain of secondary MUXes. NULL terminated */
+struct usb_mux_chain {
+	/* Structure describing USB mux */
+	const struct usb_mux *mux;
+
+	/* Pointer to next mux */
+	const struct usb_mux_chain *next;
 };
 
 /* Supported USB mux drivers */
 extern const struct usb_mux_driver amd_fp5_usb_mux_driver;
+extern const struct usb_mux_driver amd_fp6_usb_mux_driver;
 extern const struct usb_mux_driver anx7440_usb_mux_driver;
 extern const struct usb_mux_driver it5205_usb_mux_driver;
 extern const struct usb_mux_driver pi3usb3x532_usb_mux_driver;
 extern const struct usb_mux_driver ps8740_usb_mux_driver;
 extern const struct usb_mux_driver ps8743_usb_mux_driver;
+extern const struct usb_mux_driver ps8822_usb_mux_driver;
 extern const struct usb_mux_driver tcpm_usb_mux_driver;
+extern const struct usb_mux_driver tusb1064_usb_mux_driver;
 extern const struct usb_mux_driver virtual_usb_mux_driver;
 
 /* USB muxes present in system, ordered by PD port #, defined at board-level */
 #ifdef CONFIG_USB_MUX_RUNTIME_CONFIG
-extern struct usb_mux usb_muxes[];
+extern struct usb_mux_chain usb_muxes[];
 #else
-extern const struct usb_mux usb_muxes[];
+extern const struct usb_mux_chain usb_muxes[];
 #endif
 
 /* Supported hpd_update functions */
-void virtual_hpd_update(const struct usb_mux *me, int hpd_lvl, int hpd_irq);
+void virtual_hpd_update(const struct usb_mux *me, mux_state_t hpd_state,
+			bool *ack_required);
 
 /*
  * Helper methods that either use tcpc communication or direct i2c
@@ -164,30 +243,30 @@ void virtual_hpd_update(const struct usb_mux *me, int hpd_lvl, int hpd_irq);
 #ifdef CONFIG_USB_PD_TCPM_MUX
 static inline int mux_write(const struct usb_mux *me, int reg, int val)
 {
-	return me->flags & USB_MUX_FLAG_NOT_TCPC
-		? i2c_write8(me->i2c_port, me->i2c_addr_flags, reg, val)
-		: tcpc_write(me->usb_port, reg, val);
+	return me->flags & USB_MUX_FLAG_NOT_TCPC ?
+		       i2c_write8(me->i2c_port, me->i2c_addr_flags, reg, val) :
+		       tcpc_write(me->usb_port, reg, val);
 }
 
 static inline int mux_read(const struct usb_mux *me, int reg, int *val)
 {
-	return me->flags & USB_MUX_FLAG_NOT_TCPC
-		? i2c_read8(me->i2c_port, me->i2c_addr_flags, reg, val)
-		: tcpc_read(me->usb_port, reg, val);
+	return me->flags & USB_MUX_FLAG_NOT_TCPC ?
+		       i2c_read8(me->i2c_port, me->i2c_addr_flags, reg, val) :
+		       tcpc_read(me->usb_port, reg, val);
 }
 
 static inline int mux_write16(const struct usb_mux *me, int reg, int val)
 {
-	return me->flags & USB_MUX_FLAG_NOT_TCPC
-		? i2c_write16(me->i2c_port, me->i2c_addr_flags, reg, val)
-		: tcpc_write16(me->usb_port, reg, val);
+	return me->flags & USB_MUX_FLAG_NOT_TCPC ?
+		       i2c_write16(me->i2c_port, me->i2c_addr_flags, reg, val) :
+		       tcpc_write16(me->usb_port, reg, val);
 }
 
 static inline int mux_read16(const struct usb_mux *me, int reg, int *val)
 {
-	return me->flags & USB_MUX_FLAG_NOT_TCPC
-		? i2c_read16(me->i2c_port, me->i2c_addr_flags, reg, val)
-		: tcpc_read16(me->usb_port, reg, val);
+	return me->flags & USB_MUX_FLAG_NOT_TCPC ?
+		       i2c_read16(me->i2c_port, me->i2c_addr_flags, reg, val) :
+		       tcpc_read16(me->usb_port, reg, val);
 }
 #endif /* CONFIG_USB_PD_TCPM_MUX */
 
@@ -206,9 +285,21 @@ void usb_mux_init(int port);
  * @param usb_config usb2.0 selected function.
  * @param polarity plug polarity (0=CC1, 1=CC2).
  */
-void usb_mux_set(int port, mux_state_t mux_mode,
-		 enum usb_switch usb_config, int polarity);
+void usb_mux_set(int port, mux_state_t mux_mode, enum usb_switch usb_config,
+		 int polarity);
 
+/**
+ * Configure superspeed muxes on type-C port for only one index in the mux
+ * chain
+ *
+ * @param port port number.
+ * @param index index of mux or retimer to set
+ * @param mux_mode mux selected function.
+ * @param usb_config usb2.0 selected function.
+ * @param polarity plug polarity (0=CC1, 1=CC2).
+ */
+void usb_mux_set_single(int port, int index, mux_state_t mux_mode,
+			enum usb_switch usb_mode, int polarity);
 /**
  * Query superspeed mux status on type-C port.
  *
@@ -234,9 +325,26 @@ void usb_mux_flip(int port);
  * Update the hot-plug event.
  *
  * @param port port number.
- * @param hpd_lvl HPD level.
- * @param hpd_irq HPD IRQ.
+ * @param mux_state HPD IRQ and LVL mux flags
+ */
+void usb_mux_hpd_update(int port, mux_state_t hpd_state);
+
+/**
+ * Port information about retimer firmware update support.
+ *
+ * @return which ports support retimer firmware update
+ *         Bits[7:0]: represent PD ports 0-7;
+ *         each bit
+ *         = 1, this port supports retimer firmware update;
+ *         = 0, not support.
  */
-void usb_mux_hpd_update(int port, int hpd_lvl, int hpd_irq);
+int usb_mux_retimer_fw_update_port_info(void);
 
+/**
+ * Check whether this port has pending mux sets
+ *
+ * @param  port USB-C port number
+ * @return True if all pending mux sets have completed
+ */
+bool usb_mux_set_completed(int port);
 #endif
diff --git a/include/usb_pd.h b/include/usb_pd.h
index 46222ea14a..b5981abc46 100644
--- a/include/usb_pd.h
+++ b/include/usb_pd.h
@@ -1,21 +1,28 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* USB Power delivery module */
 
+/*
+ * TODO(b/272518464): Work around coreboot GCC preprocessor bug.
+ * #line marks the *next* line, so it is off by one.
+ */
+#line 13
+
 #ifndef __CROS_EC_USB_PD_H
 #define __CROS_EC_USB_PD_H
 
-#include <stdbool.h>
-#include <stdint.h>
 #include "common.h"
 #include "ec_commands.h"
 #include "usb_pd_tbt.h"
 #include "usb_pd_tcpm.h"
 #include "usb_pd_vdo.h"
 
+#include <stdbool.h>
+#include <stdint.h>
+
 /* PD Host command timeout */
 #define PD_HOST_COMMAND_TIMEOUT_US SECOND
 
@@ -26,57 +33,60 @@
  */
 #if defined(HAS_TASK_PD_C0) && defined(CONFIG_USB_PD_PORT_MAX_COUNT)
 #define PD_PORT_TO_TASK_ID(port) (TASK_ID_PD_C0 + (port))
-#define TASK_ID_TO_PD_PORT(id) ((id) - TASK_ID_PD_C0)
+#define TASK_ID_TO_PD_PORT(id) ((id)-TASK_ID_PD_C0)
 #else
 #define PD_PORT_TO_TASK_ID(port) -1 /* stub task ID */
 #define TASK_ID_TO_PD_PORT(id) 0
 #endif /* CONFIG_USB_PD_PORT_MAX_COUNT && HAS_TASK_PD_C0 */
 
 enum pd_rx_errors {
-	PD_RX_ERR_INVAL = -1,           /* Invalid packet */
-	PD_RX_ERR_HARD_RESET = -2,      /* Got a Hard-Reset packet */
-	PD_RX_ERR_CRC = -3,             /* CRC mismatch */
-	PD_RX_ERR_ID = -4,              /* Invalid ID number */
+	PD_RX_ERR_INVAL = -1, /* Invalid packet */
+	PD_RX_ERR_HARD_RESET = -2, /* Got a Hard-Reset packet */
+	PD_RX_ERR_CRC = -3, /* CRC mismatch */
+	PD_RX_ERR_ID = -4, /* Invalid ID number */
 	PD_RX_ERR_UNSUPPORTED_SOP = -5, /* Unsupported SOP */
-	PD_RX_ERR_CABLE_RESET = -6      /* Got a Cable-Reset packet */
+	PD_RX_ERR_CABLE_RESET = -6 /* Got a Cable-Reset packet */
 };
 
 /* Events for USB PD task */
 
 /* Outgoing packet event */
-#define PD_EVENT_TX			TASK_EVENT_CUSTOM_BIT(3)
+#define PD_EVENT_TX TASK_EVENT_CUSTOM_BIT(3)
 /* CC line change event */
-#define PD_EVENT_CC			TASK_EVENT_CUSTOM_BIT(4)
+#define PD_EVENT_CC TASK_EVENT_CUSTOM_BIT(4)
 /* TCPC has reset */
-#define PD_EVENT_TCPC_RESET		TASK_EVENT_CUSTOM_BIT(5)
+#define PD_EVENT_TCPC_RESET TASK_EVENT_CUSTOM_BIT(5)
 /* DRP state has changed */
-#define PD_EVENT_UPDATE_DUAL_ROLE	TASK_EVENT_CUSTOM_BIT(6)
+#define PD_EVENT_UPDATE_DUAL_ROLE TASK_EVENT_CUSTOM_BIT(6)
 /*
  * A task, other than the task owning the PD port, accessed the TCPC. The task
  * that owns the port does not send itself this event.
  */
-#define PD_EVENT_DEVICE_ACCESSED	TASK_EVENT_CUSTOM_BIT(7)
+#define PD_EVENT_DEVICE_ACCESSED TASK_EVENT_CUSTOM_BIT(7)
 /* Chipset power state changed */
-#define PD_EVENT_POWER_STATE_CHANGE	TASK_EVENT_CUSTOM_BIT(8)
+#define PD_EVENT_POWER_STATE_CHANGE TASK_EVENT_CUSTOM_BIT(8)
 /* Issue a Hard Reset. */
-#define PD_EVENT_SEND_HARD_RESET	TASK_EVENT_CUSTOM_BIT(9)
+#define PD_EVENT_SEND_HARD_RESET TASK_EVENT_CUSTOM_BIT(9)
 /* Prepare for sysjump */
-#define PD_EVENT_SYSJUMP		TASK_EVENT_CUSTOM_BIT(10)
+#define PD_EVENT_SYSJUMP TASK_EVENT_CUSTOM_BIT(10)
 /* Receive a Hard Reset. */
-#define PD_EVENT_RX_HARD_RESET		TASK_EVENT_CUSTOM_BIT(11)
+#define PD_EVENT_RX_HARD_RESET TASK_EVENT_CUSTOM_BIT(11)
+/* MUX configured notification event */
+#define PD_EVENT_AP_MUX_DONE TASK_EVENT_CUSTOM_BIT(12)
 /* First free event on PD task */
-#define PD_EVENT_FIRST_FREE_BIT		12
+#define PD_EVENT_FIRST_FREE_BIT 13
 
 /* Ensure TCPC is out of low power mode before handling these events. */
-#define PD_EXIT_LOW_POWER_EVENT_MASK \
-	(PD_EVENT_CC | \
-	 PD_EVENT_UPDATE_DUAL_ROLE | \
-	 PD_EVENT_POWER_STATE_CHANGE | \
-	 PD_EVENT_TCPC_RESET)
+#define PD_EXIT_LOW_POWER_EVENT_MASK               \
+	(PD_EVENT_CC | PD_EVENT_UPDATE_DUAL_ROLE | \
+	 PD_EVENT_POWER_STATE_CHANGE | PD_EVENT_TCPC_RESET)
 
 /* --- PD data message helpers --- */
-#define PDO_MAX_OBJECTS   7
-#define PDO_MODES (PDO_MAX_OBJECTS - 1)
+#ifdef CONFIG_USB_PD_EPR
+#define PDO_MAX_OBJECTS 11
+#else
+#define PDO_MAX_OBJECTS 7
+#endif
 
 /* PDO : Power Data Object */
 /*
@@ -89,175 +99,231 @@ enum pd_rx_errors {
  *    if present, shall be sent in Minimum Voltage order; lowest to highest.
  * 5. (PD3.0) The Augmented PDO is defined to allow extension beyond the 4 PDOs
  *     above by examining bits <29:28> to determine the additional PDO function.
+ *
+ * Note: Some bits and decode macros are defined in ec_commands.h
  */
-#define PDO_TYPE_FIXED     (0 << 30)
-#define PDO_TYPE_BATTERY   BIT(30)
-#define PDO_TYPE_VARIABLE  (2 << 30)
-#define PDO_TYPE_AUGMENTED (3 << 30)
-#define PDO_TYPE_MASK      (3 << 30)
-
-#define PDO_FIXED_DUAL_ROLE	BIT(29) /* Dual role device */
-#define PDO_FIXED_SUSPEND	BIT(28) /* USB Suspend supported */
-#define PDO_FIXED_UNCONSTRAINED	BIT(27) /* Unconstrained Power */
-#define PDO_FIXED_COMM_CAP	BIT(26) /* USB Communications Capable */
-#define PDO_FIXED_DATA_SWAP	BIT(25) /* Data role swap command supported */
-#define PDO_FIXED_FRS_CURR_MASK (3 << 23) /* [23..24] FRS current */
-#define PDO_FIXED_FRS_CURR_NOT_SUPPORTED  (0 << 23)
+#define PDO_FIXED_SUSPEND BIT(28) /* USB Suspend supported */
+/* Higher capability in vSafe5V sink PDO */
+#define PDO_FIXED_SNK_HIGHER_CAP BIT(28)
+#define PDO_FIXED_FRS_CURR_NOT_SUPPORTED (0 << 23)
 #define PDO_FIXED_FRS_CURR_DFLT_USB_POWER (1 << 23)
-#define PDO_FIXED_FRS_CURR_1A5_AT_5V      (2 << 23)
-#define PDO_FIXED_FRS_CURR_3A0_AT_5V      (3 << 23)
+#define PDO_FIXED_FRS_CURR_1A5_AT_5V (2 << 23)
+#define PDO_FIXED_FRS_CURR_3A0_AT_5V (3 << 23)
+#define PDO_FIXED_EPR_MODE_CAPABLE BIT(23)
 #define PDO_FIXED_PEAK_CURR () /* [21..20] Peak current */
-#define PDO_FIXED_VOLT(mv)  (((mv)/50) << 10) /* Voltage in 50mV units */
-#define PDO_FIXED_CURR(ma)  (((ma)/10) << 0)  /* Max current in 10mA units */
+#define PDO_FIXED_VOLT(mv) (((mv) / 50) << 10) /* Voltage in 50mV units */
+#define PDO_FIXED_CURR(ma) (((ma) / 10) << 0) /* Max current in 10mA units */
+#define PDO_FIXED_GET_VOLT(pdo) (((pdo >> 10) & 0x3FF) * 50)
+#define PDO_FIXED_GET_CURR(pdo) ((pdo & 0x3FF) * 10)
 
-#define PDO_FIXED(mv, ma, flags) (PDO_FIXED_VOLT(mv) |\
-				  PDO_FIXED_CURR(ma) | (flags))
+#define PDO_FIXED(mv, ma, flags) \
+	(PDO_FIXED_VOLT(mv) | PDO_FIXED_CURR(ma) | (flags))
 
 #define PDO_VAR_MAX_VOLT(mv) ((((mv) / 50) & 0x3FF) << 20)
 #define PDO_VAR_MIN_VOLT(mv) ((((mv) / 50) & 0x3FF) << 10)
-#define PDO_VAR_OP_CURR(ma)  ((((ma) / 10) & 0x3FF) << 0)
+#define PDO_VAR_OP_CURR(ma) ((((ma) / 10) & 0x3FF) << 0)
 
-#define PDO_VAR(min_mv, max_mv, op_ma) \
-				(PDO_VAR_MIN_VOLT(min_mv) | \
-				 PDO_VAR_MAX_VOLT(max_mv) | \
-				 PDO_VAR_OP_CURR(op_ma)   | \
-				 PDO_TYPE_VARIABLE)
+#define PDO_VAR(min_mv, max_mv, op_ma)                         \
+	(PDO_VAR_MIN_VOLT(min_mv) | PDO_VAR_MAX_VOLT(max_mv) | \
+	 PDO_VAR_OP_CURR(op_ma) | PDO_TYPE_VARIABLE)
 
 #define PDO_BATT_MAX_VOLT(mv) ((((mv) / 50) & 0x3FF) << 20)
 #define PDO_BATT_MIN_VOLT(mv) ((((mv) / 50) & 0x3FF) << 10)
 #define PDO_BATT_OP_POWER(mw) ((((mw) / 250) & 0x3FF) << 0)
 
-#define PDO_BATT(min_mv, max_mv, op_mw) \
-				(PDO_BATT_MIN_VOLT(min_mv) | \
-				 PDO_BATT_MAX_VOLT(max_mv) | \
-				 PDO_BATT_OP_POWER(op_mw) | \
-				 PDO_TYPE_BATTERY)
-
-/* RDO : Request Data Object */
-#define RDO_OBJ_POS(n)             (((n) & 0x7) << 28)
-#define RDO_POS(rdo)               (((rdo) >> 28) & 0x7)
-#define RDO_GIVE_BACK              BIT(27)
-#define RDO_CAP_MISMATCH           BIT(26)
-#define RDO_COMM_CAP               BIT(25)
-#define RDO_NO_SUSPEND             BIT(24)
-#define RDO_FIXED_VAR_OP_CURR(ma)  ((((ma) / 10) & 0x3FF) << 10)
-#define RDO_FIXED_VAR_MAX_CURR(ma) ((((ma) / 10) & 0x3FF) << 0)
-
-#define RDO_BATT_OP_POWER(mw)      ((((mw) / 250) & 0x3FF) << 10)
-#define RDO_BATT_MAX_POWER(mw)     ((((mw) / 250) & 0x3FF) << 10)
-
-#define RDO_FIXED(n, op_ma, max_ma, flags) \
-				(RDO_OBJ_POS(n) | (flags) | \
-				RDO_FIXED_VAR_OP_CURR(op_ma) | \
-				RDO_FIXED_VAR_MAX_CURR(max_ma))
-
+#define PDO_BATT(min_mv, max_mv, op_mw)                          \
+	(PDO_BATT_MIN_VOLT(min_mv) | PDO_BATT_MAX_VOLT(max_mv) | \
+	 PDO_BATT_OP_POWER(op_mw) | PDO_TYPE_BATTERY)
 
-#define RDO_BATT(n, op_mw, max_mw, flags) \
-				(RDO_OBJ_POS(n) | (flags) | \
-				RDO_BATT_OP_POWER(op_mw) | \
-				RDO_BATT_MAX_POWER(max_mw))
+#define PDO_AUG_MAX_VOLT(mv) ((((mv) / 100) & 0xFF) << 17)
+#define PDO_AUG_MIN_VOLT(mv) ((((mv) / 100) & 0xFF) << 8)
+#define PDO_AUG_MAX_CURR(ma) ((((ma) / 50) & 0x7F) << 0)
 
-/* BDO : BIST Data Object */
-#define BDO_MODE_RECV       (0 << 28)
-#define BDO_MODE_TRANSMIT   BIT(28)
-#define BDO_MODE_COUNTERS   (2 << 28)
-#define BDO_MODE_CARRIER0   (3 << 28)
-#define BDO_MODE_CARRIER1   (4 << 28)
-#define BDO_MODE_CARRIER2   (5 << 28)
-#define BDO_MODE_CARRIER3   (6 << 28)
-#define BDO_MODE_EYE        (7 << 28)
+#define PDO_AUG(min_mv, max_mv, max_ma)                        \
+	(PDO_AUG_MIN_VOLT(min_mv) | PDO_AUG_MAX_VOLT(max_mv) | \
+	 PDO_AUG_MAX_CURR(max_ma) | PDO_TYPE_AUGMENTED)
 
-#define BDO(mode, cnt)      ((mode) | ((cnt) & 0xFFFF))
+/* RDO : Request Data Object */
+#define RDO_OBJ_POS(n) (((n)&0xF) << 28)
+#define RDO_POS(rdo) (((rdo) >> 28) & 0xF)
+#define RDO_GIVE_BACK BIT(27)
+#define RDO_CAP_MISMATCH BIT(26)
+#define RDO_COMM_CAP BIT(25)
+#define RDO_NO_SUSPEND BIT(24)
+#define RDO_EPR_MODE_CAPABLE BIT(22)
+#define RDO_FIXED_VAR_OP_CURR(ma) ((((ma) / 10) & 0x3FF) << 10)
+#define RDO_FIXED_VAR_MAX_CURR(ma) ((((ma) / 10) & 0x3FF) << 0)
 
-#define BIST_MODE(n)          ((n) >> 28)
-#define BIST_ERROR_COUNTER(n) ((n) & 0xffff)
-#define BIST_RECEIVER_MODE    0
-#define BIST_TRANSMIT_MODE    1
+#define RDO_BATT_OP_POWER(mw) ((((mw) / 250) & 0x3FF) << 10)
+#define RDO_BATT_MAX_POWER(mw) ((((mw) / 250) & 0x3FF) << 0)
+
+#define RDO_FIXED(n, op_ma, max_ma, flags)                         \
+	(RDO_OBJ_POS(n) | (flags) | RDO_FIXED_VAR_OP_CURR(op_ma) | \
+	 RDO_FIXED_VAR_MAX_CURR(max_ma))
+
+#define RDO_BATT(n, op_mw, max_mw, flags)                      \
+	(RDO_OBJ_POS(n) | (flags) | RDO_BATT_OP_POWER(op_mw) | \
+	 RDO_BATT_MAX_POWER(max_mw))
+
+/* BDO : BIST Data Object
+ * 31:28 BIST Mode
+ *       In PD 3.0, all but Carrier Mode 2 (as Carrier Mode) and Test Data are
+ *       reserved, with a new BIST shared mode added
+ * 27:16 Reserved
+ * 15:0  Returned error counters (reserved in PD 3.0)
+ */
+#define BDO_MODE_RECV (BIST_RECEIVER_MODE << 28)
+#define BDO_MODE_TRANSMIT (BIST_TRANSMIT_MODE << 28)
+#define BDO_MODE_COUNTERS (BIST_RETURNED_COUNTER << 28)
+#define BDO_MODE_CARRIER0 (BIST_CARRIER_MODE_0 << 28)
+#define BDO_MODE_CARRIER1 (BIST_CARRIER_MODE_1 << 28)
+#define BDO_MODE_CARRIER2 (BIST_CARRIER_MODE_2 << 28)
+#define BDO_MODE_CARRIER3 (BIST_CARRIER_MODE_3 << 28)
+#define BDO_MODE_EYE (BIST_EYE_PATTERN << 28)
+#define BDO_MODE_TEST_DATA (BIST_TEST_DATA << 28)
+#define BDO_MODE_SHARED_ENTER (BIST_SHARED_MODE_ENTER << 28)
+#define BDO_MODE_SHARED_EXIT (BIST_SHARED_MODE_EXIT << 28)
+
+#define BDO(mode, cnt) ((mode) | ((cnt)&0xFFFF))
+
+#define BIST_MODE(n) ((n) >> 28)
+#define BIST_ERROR_COUNTER(n) ((n)&0xffff)
+#define BIST_RECEIVER_MODE 0
+#define BIST_TRANSMIT_MODE 1
 #define BIST_RETURNED_COUNTER 2
-#define BIST_CARRIER_MODE_0   3
-#define BIST_CARRIER_MODE_1   4
-#define BIST_CARRIER_MODE_2   5
-#define BIST_CARRIER_MODE_3   6
-#define BIST_EYE_PATTERN      7
-#define BIST_TEST_DATA        8
+#define BIST_CARRIER_MODE_0 3
+#define BIST_CARRIER_MODE_1 4
+#define BIST_CARRIER_MODE_2 5
+#define BIST_CARRIER_MODE_3 6
+#define BIST_EYE_PATTERN 7
+#define BIST_TEST_DATA 8
+#define BIST_SHARED_MODE_ENTER 9
+#define BIST_SHARED_MODE_EXIT 10
 
 #define SVID_DISCOVERY_MAX 16
 
 /* Timers */
-#define PD_T_SINK_TX                (18*MSEC) /* between 16ms and 20 */
-#define PD_T_CHUNKING_NOT_SUPPORTED (45*MSEC) /* between 40ms and 50ms */
-#define PD_T_CHUNK_SENDER_RSP       (24*MSEC) /* between 24ms and 30ms */
-#define PD_T_CHUNK_SENDER_REQ       (24*MSEC) /* between 24ms and 30ms */
-#define PD_T_HARD_RESET_COMPLETE     (5*MSEC) /* between 4ms and 5ms*/
-#define PD_T_HARD_RESET_RETRY        (1*MSEC) /* 1ms */
-#define PD_T_SEND_SOURCE_CAP       (100*MSEC) /* between 100ms and 200ms */
-#define PD_T_SINK_WAIT_CAP         (600*MSEC) /* between 310ms and 620ms */
-#define PD_T_SINK_TRANSITION        (35*MSEC) /* between 20ms and 35ms */
-#define PD_T_SOURCE_ACTIVITY        (45*MSEC) /* between 40ms and 50ms */
-#define PD_T_SENDER_RESPONSE        (30*MSEC) /* between 24ms and 30ms */
-#define PD_T_PS_TRANSITION         (500*MSEC) /* between 450ms and 550ms */
-#define PD_T_PS_SOURCE_ON          (480*MSEC) /* between 390ms and 480ms */
-#define PD_T_PS_SOURCE_OFF         (920*MSEC) /* between 750ms and 920ms */
-#define PD_T_PS_HARD_RESET          (25*MSEC) /* between 25ms and 35ms */
-#define PD_T_ERROR_RECOVERY        (240*MSEC) /* min 240ms if sourcing VConn */
-#define PD_T_CC_DEBOUNCE           (100*MSEC) /* between 100ms and 200ms */
+#define PD_T_SINK_TX (18 * MSEC) /* between 16ms and 20 */
+#define PD_T_CHUNKING_NOT_SUPPORTED (45 * MSEC) /* between 40ms and 50ms */
+#define PD_T_HARD_RESET_COMPLETE (5 * MSEC) /* between 4ms and 5ms*/
+#define PD_T_HARD_RESET_RETRY (1 * MSEC) /* 1ms */
+#define PD_T_SEND_SOURCE_CAP (100 * MSEC) /* between 100ms and 200ms */
+#define PD_T_SINK_WAIT_CAP (575 * MSEC) /* between 310ms and 620ms */
+#define PD_T_SINK_TRANSITION (35 * MSEC) /* between 20ms and 35ms */
+#define PD_T_SOURCE_ACTIVITY (45 * MSEC) /* between 40ms and 50ms */
+#define PD_T_ENTER_EPR (500 * MSEC) /* between 450ms and 550ms */
+/*
+ * Adjusting for TCPMv2 PD2 Compliance. In tests like TD.PD.SRC.E5 this
+ * value is the duration before the Hard Reset can be sent. Setting the
+ * timer value to the maximum will delay sending the HardReset until
+ * after the window has closed instead of when it is desired at the
+ * beginning of the window.
+ * Leaving TCPMv1 as it was as there are no current requests to adjust
+ * for compliance on the old stack and making this change  breaks the
+ * usb_pd unit test.
+ */
+#ifndef CONFIG_USB_PD_TCPMV2
+#define PD_T_SENDER_RESPONSE (30 * MSEC) /* between 24ms and 30ms */
+#else
+/*
+ * In USB Power Delivery Specification Revision 3.1, Version 1.5,
+ * the tSenderResponse have changed to min 26/ max 32 ms.
+ */
+#define PD_T_SENDER_RESPONSE (26 * MSEC) /* between 26ms and 32ms */
+#endif
+#define PD_T_PS_TRANSITION (500 * MSEC) /* between 450ms and 550ms */
+/*
+ * This is adjusted for PD3.1 Compliance test TEST.PD.PROT.SRC.10.
+ */
+#define PD_T_PS_SOURCE_ON (435 * MSEC) /* between 390ms and 480ms */
+#define PD_T_PS_SOURCE_OFF (835 * MSEC) /* between 750ms and 920ms */
+#define PD_T_PS_HARD_RESET (25 * MSEC) /* between 25ms and 35ms */
+#define PD_T_ERROR_RECOVERY (240 * MSEC) /* min 240ms if sourcing VConn */
+#define PD_T_CC_DEBOUNCE (100 * MSEC) /* between 100ms and 200ms */
 /* DRP_SNK + DRP_SRC must be between 50ms and 100ms with 30%-70% duty cycle */
-#define PD_T_DRP_SNK                (40*MSEC) /* toggle time for sink DRP */
-#define PD_T_DRP_SRC                (30*MSEC) /* toggle time for source DRP */
-#define PD_T_DEBOUNCE               (15*MSEC) /* between 10ms and 20ms */
-#define PD_T_TRY_CC_DEBOUNCE        (15*MSEC) /* between 10ms and 20ms */
-#define PD_T_SINK_ADJ               (55*MSEC) /* between tPDDebounce and 60ms */
-#define PD_T_SRC_RECOVER           (760*MSEC) /* between 660ms and 1000ms */
-#define PD_T_SRC_RECOVER_MAX      (1000*MSEC) /* 1000ms */
-#define PD_T_SRC_TURN_ON           (275*MSEC) /* 275ms */
-#define PD_T_SAFE_0V               (650*MSEC) /* 650ms */
-#define PD_T_NO_RESPONSE          (5500*MSEC) /* between 4.5s and 5.5s */
-#define PD_T_BIST_TRANSMIT          (50*MSEC) /* 50ms (for task_wait arg) */
-#define PD_T_BIST_RECEIVE           (60*MSEC) /* 60ms (time to process bist) */
-#define PD_T_BIST_CONT_MODE         (60*MSEC) /* 30ms to 60ms */
-#define PD_T_VCONN_SOURCE_ON       (100*MSEC) /* 100ms */
-#define PD_T_DRP_TRY               (125*MSEC) /* between 75ms and 150ms */
-#define PD_T_TRY_TIMEOUT           (550*MSEC) /* between 550ms and 1100ms */
-#define PD_T_TRY_WAIT              (600*MSEC) /* Wait time for TryWait.SNK */
-#define PD_T_SINK_REQUEST          (100*MSEC) /* 100ms before next request */
-#define PD_T_PD_DEBOUNCE            (15*MSEC) /* between 10ms and 20ms */
-#define PD_T_CHUNK_SENDER_RESPONSE  (25*MSEC) /* 25ms */
-#define PD_T_CHUNK_SENDER_REQUEST   (25*MSEC) /* 25ms */
-#define PD_T_SWAP_SOURCE_START      (25*MSEC) /* Min of 20ms */
-#define PD_T_RP_VALUE_CHANGE        (20*MSEC) /* 20ms */
-#define PD_T_SRC_DISCONNECT         (15*MSEC) /* 15ms */
-#define PD_T_VCONN_STABLE           (50*MSEC) /* 50ms */
-#define PD_T_DISCOVER_IDENTITY      (45*MSEC) /* between 40ms and 50ms */
-#define PD_T_SYSJUMP              (1000*MSEC) /* 1s */
-#define PD_T_PR_SWAP_WAIT          (100*MSEC) /* tPRSwapWait 100ms */
+#define PD_T_DRP_SNK (40 * MSEC) /* toggle time for sink DRP */
+#define PD_T_DRP_SRC (30 * MSEC) /* toggle time for source DRP */
+#define PD_T_DEBOUNCE (15 * MSEC) /* between 10ms and 20ms */
+#define PD_T_TRY_CC_DEBOUNCE (15 * MSEC) /* between 10ms and 20ms */
+#define PD_T_SINK_ADJ (55 * MSEC) /* between tPDDebounce and 60ms */
+#define PD_T_SRC_RECOVER (760 * MSEC) /* between 660ms and 1000ms */
+#define PD_T_SRC_RECOVER_MAX (1000 * MSEC) /* 1000ms */
+#define PD_T_SRC_TURN_ON (275 * MSEC) /* 275ms */
+#define PD_T_SAFE_0V (650 * MSEC) /* 650ms */
+#define PD_T_NO_RESPONSE (5500 * MSEC) /* between 4.5s and 5.5s */
+#define PD_T_BIST_TRANSMIT (50 * MSEC) /* 50ms (for task_wait arg) */
+#define PD_T_BIST_RECEIVE (60 * MSEC) /* 60ms (time to process bist) */
+#define PD_T_BIST_CONT_MODE (55 * MSEC) /* 30ms to 60ms */
+#define PD_T_VCONN_SOURCE_ON (100 * MSEC) /* 100ms */
+#define PD_T_DRP_TRY (125 * MSEC) /* between 75ms and 150ms */
+#define PD_T_TRY_TIMEOUT (550 * MSEC) /* between 550ms and 1100ms */
+#define PD_T_TRY_WAIT (600 * MSEC) /* Wait time for TryWait.SNK */
+#define PD_T_SINK_REQUEST (100 * MSEC) /* 100ms before next request */
+#define PD_T_PD_DEBOUNCE (15 * MSEC) /* between 10ms and 20ms */
+#define PD_T_CHUNK_SENDER_RESPONSE (25 * MSEC) /* 25ms */
+#define PD_T_CHUNK_SENDER_REQUEST (25 * MSEC) /* 25ms */
+#define PD_T_SWAP_SOURCE_START (25 * MSEC) /* Min of 20ms */
+#define PD_T_RP_VALUE_CHANGE (20 * MSEC) /* 20ms */
+#define PD_T_SRC_DISCONNECT (15 * MSEC) /* 15ms */
+#define PD_T_SRC_TRANSITION (25 * MSEC) /* 25ms to 35 ms */
+#define PD_T_VCONN_STABLE (50 * MSEC) /* 50ms */
+#define PD_T_DISCOVER_IDENTITY (45 * MSEC) /* between 40ms and 50ms */
+#define PD_T_SYSJUMP (1000 * MSEC) /* 1s */
+#define PD_T_PR_SWAP_WAIT (100 * MSEC) /* tPRSwapWait 100ms */
+#define PD_T_DATA_RESET (225 * MSEC) /* between 200ms and 250ms */
+#define PD_T_DATA_RESET_FAIL (300 * MSEC) /* 300ms */
+#define PD_T_VCONN_REAPPLIED (10 * MSEC) /* between 10ms and 20ms */
+#define PD_T_VCONN_DISCHARGE (240 * MSEC) /* between 160ms and 240ms */
+#define PD_T_SINK_EPR_KEEP_ALIVE (375 * MSEC) /* between 250ms and 500ms */
+
+/*
+ * Non-spec timer to prevent going Unattached if Vbus drops before a partner FRS
+ * signal comes through.  This timer should be shorter than tSinkDisconnect
+ * (40ms) to ensure we still transition out of Attached.SNK in time.
+ */
+#define PD_T_FRS_VBUS_DEBOUNCE (5 * MSEC)
 
 /* number of edges and time window to detect CC line is not idle */
-#define PD_RX_TRANSITION_COUNT  3
+#define PD_RX_TRANSITION_COUNT 3
 #define PD_RX_TRANSITION_WINDOW 20 /* between 12us and 20us */
 
 /* from USB Type-C Specification Table 5-1 */
-#define PD_T_AME (1*SECOND) /* timeout from UFP attach to Alt Mode Entry */
+#define PD_T_AME (1 * SECOND) /* timeout from UFP attach to Alt Mode Entry */
 
 /* VDM Timers ( USB PD Spec Rev2.0 Table 6-30 )*/
-#define PD_T_VDM_BUSY           (50*MSEC) /* at least 50ms */
-#define PD_T_VDM_E_MODE         (25*MSEC) /* enter/exit the same max */
-#define PD_T_VDM_RCVR_RSP       (15*MSEC) /* max of 15ms */
-#define PD_T_VDM_SNDR_RSP       (30*MSEC) /* max of 30ms */
-#define PD_T_VDM_WAIT_MODE_E   (100*MSEC) /* enter/exit the same max */
+#define PD_T_VDM_BUSY (50 * MSEC) /* at least 50ms */
+#define PD_T_VDM_E_MODE (25 * MSEC) /* enter/exit the same max */
+#define PD_T_VDM_RCVR_RSP (15 * MSEC) /* max of 15ms */
+#define PD_T_VDM_SNDR_RSP (30 * MSEC) /* max of 30ms */
+#define PD_T_VDM_WAIT_MODE_E (100 * MSEC) /* enter/exit the same max */
 
 /* CTVPD Timers ( USB Type-C ECN Table 4-27 ) */
-#define PD_T_VPDDETACH        (20*MSEC) /* max of 20*MSEC */
-#define PD_T_VPDCTDD           (4*MSEC) /* max of 4ms */
-#define PD_T_VPDDISABLE       (25*MSEC) /* min of 25ms */
+#define PD_T_VPDDETACH (20 * MSEC) /* max of 20*MSEC */
+#define PD_T_VPDCTDD (4 * MSEC) /* max of 4ms */
+#define PD_T_VPDDISABLE (25 * MSEC) /* min of 25ms */
 
 /* Voltage thresholds in mV (Table 7-24, PD 3.0 Version 2.0 Spec) */
-#define PD_V_SAFE0V_MAX		800
-#define PD_V_SAFE5V_MIN		4750
+#define PD_V_SAFE0V_MAX 800
+#define PD_V_SAFE5V_MIN 4750
+#define PD_V_SAFE5V_NOM 5000
+#define PD_V_SAFE5V_MAX 5500
 
 /* USB Type-C voltages in mV (Table 4-3, USB Type-C Release 2.0 Spec) */
 #define PD_V_SINK_DISCONNECT_MAX 3670
 /* TODO(b/149530538): Add equation for vSinkDisconnectPD */
 
+/* Maximum SPR voltage in mV offered by PD 3.0 Version 2.0 Spec */
+#define PD_REV3_MAX_VOLTAGE 20000
+
+/* Maximum SPR voltage in mV */
+#define PD_MAX_SPR_VOLTAGE 20000
+
+/* Maximum EPR voltage in mV */
+#define PD_MAX_EPR_VOLTAGE 48000
+
+/* Power in mW at which we will automatically charge from a DRP partner */
+#define PD_DRP_CHARGE_POWER_MIN 27000
+
 /* function table for entered mode */
 struct amode_fx {
 	int (*status)(int port, uint32_t *payload);
@@ -289,9 +355,9 @@ struct svdm_response {
  * value after resetting connection information via memset.
  */
 enum pd_discovery_state {
-	PD_DISC_NEEDED = 0,	/* Cable or partner still needs to be probed */
-	PD_DISC_COMPLETE,	/* Successfully probed, valid to read VDO */
-	PD_DISC_FAIL,		/* Cable did not respond, or Discover* NAK */
+	PD_DISC_NEEDED = 0, /* Cable or partner still needs to be probed */
+	PD_DISC_COMPLETE, /* Successfully probed, valid to read VDO */
+	PD_DISC_FAIL, /* Cable did not respond, or Discover* NAK */
 };
 
 /* Mode discovery state for a particular SVID with a particular transmit type */
@@ -301,7 +367,7 @@ struct svid_mode_data {
 	/* The number of modes discovered for this SVID */
 	int mode_cnt;
 	/* The discovered mode VDOs */
-	uint32_t mode_vdo[PDO_MODES];
+	uint32_t mode_vdo[VDO_MAX_OBJECTS];
 	/* State of mode discovery for this SVID */
 	enum pd_discovery_state discovery;
 };
@@ -324,6 +390,7 @@ extern const struct svdm_amode_fx supported_modes[];
 extern const int supported_modes_cnt;
 
 /* 4 entry rw_hash table of type-C devices that AP has firmware updates for. */
+/* This is *NOT* a hash-table, it's a table (ring-buffer) of hashes */
 #ifdef CONFIG_COMMON_RUNTIME
 #define RW_HASH_ENTRIES 4
 extern struct ec_params_usb_pd_rw_hash_entry rw_hash_table[RW_HASH_ENTRIES];
@@ -344,7 +411,7 @@ struct svdm_amode_data {
 	/* VDM object position */
 	int opos;
 	/* mode capabilities specific to SVID amode. */
-	struct svid_mode_data *data;
+	const struct svid_mode_data *data;
 };
 
 enum hpd_event {
@@ -355,8 +422,8 @@ enum hpd_event {
 };
 
 /* DisplayPort flags */
-#define DP_FLAGS_DP_ON              BIT(0) /* Display port mode is on */
-#define DP_FLAGS_HPD_HI_PENDING     BIT(1) /* Pending HPD_HI */
+#define DP_FLAGS_DP_ON BIT(0) /* Display port mode is on */
+#define DP_FLAGS_HPD_HI_PENDING BIT(1) /* Pending HPD_HI */
 
 /* Discover Identity ACK contents after headers */
 union disc_ident_ack {
@@ -369,10 +436,10 @@ union disc_ident_ack {
 		uint32_t product_t3;
 	};
 
-	uint32_t raw_value[PDO_MAX_OBJECTS - 1];
+	uint32_t raw_value[VDO_MAX_OBJECTS];
 };
 BUILD_ASSERT(sizeof(union disc_ident_ack) ==
-				sizeof(uint32_t) * (PDO_MAX_OBJECTS - 1));
+	     sizeof(uint32_t) * (VDO_MAX_OBJECTS));
 
 /* Discover Identity data - ACK plus discovery state */
 struct identity_data {
@@ -391,11 +458,11 @@ enum pd_alternate_modes {
 
 /* Discover and possibly enter modes for all SOP* communications when enabled */
 #ifdef CONFIG_USB_PD_DECODE_SOP
-#define DISCOVERY_TYPE_COUNT (TCPC_TX_SOP_PRIME + 1)
-#define AMODE_TYPE_COUNT     (TCPC_TX_SOP_PRIME_PRIME + 1)
+#define DISCOVERY_TYPE_COUNT (TCPCI_MSG_SOP_PRIME + 1)
+#define AMODE_TYPE_COUNT (TCPCI_MSG_SOP_PRIME_PRIME + 1)
 #else
-#define DISCOVERY_TYPE_COUNT (TCPC_TX_SOP + 1)
-#define AMODE_TYPE_COUNT     (TCPC_TX_SOP + 1)
+#define DISCOVERY_TYPE_COUNT (TCPCI_MSG_SOP + 1)
+#define AMODE_TYPE_COUNT (TCPCI_MSG_SOP + 1)
 #endif
 
 /* Discovery results for a port partner (SOP) or cable plug (SOP') */
@@ -429,7 +496,6 @@ struct partner_active_modes {
  * VDM object is minimum of VDM header + 6 additional data objects.
  */
 #define VDO_HDR_SIZE 1
-#define VDO_MAX_SIZE 7
 
 #define VDM_VER10 0
 #define VDM_VER20 1
@@ -449,56 +515,53 @@ struct partner_active_modes {
  * <4:0>    :: command
  */
 #define VDO(vid, type, custom) \
-	(((vid) << 16) |       \
-	((type) << 15) |       \
-	((custom) & 0x7FFF))
-
-#define VDO_SVDM_TYPE     BIT(15)
-#define VDO_SVDM_VERS(x)  (x << 13)
-#define VDO_OPOS(x)       (x << 8)
-#define VDO_CMDT(x)       (x << 6)
-#define VDO_OPOS_MASK     VDO_OPOS(0x7)
-#define VDO_CMDT_MASK     VDO_CMDT(0x3)
-
-#define CMDT_INIT     0
-#define CMDT_RSP_ACK  1
-#define CMDT_RSP_NAK  2
+	(((vid) << 16) | ((type) << 15) | ((custom)&0x7FFF))
+
+#define VDO_SVDM_TYPE BIT(15)
+#define VDO_SVDM_VERS(x) (x << 13)
+#define VDO_OPOS(x) (x << 8)
+#define VDO_CMDT(x) (x << 6)
+#define VDO_OPOS_MASK VDO_OPOS(0x7)
+#define VDO_CMDT_MASK VDO_CMDT(0x3)
+
+#define CMDT_INIT 0
+#define CMDT_RSP_ACK 1
+#define CMDT_RSP_NAK 2
 #define CMDT_RSP_BUSY 3
 
-
 /* reserved for SVDM ... for Google UVDM */
 #define VDO_SRC_INITIATOR (0 << 5)
 #define VDO_SRC_RESPONDER BIT(5)
 
-#define CMD_DISCOVER_IDENT  1
-#define CMD_DISCOVER_SVID   2
-#define CMD_DISCOVER_MODES  3
-#define CMD_ENTER_MODE      4
-#define CMD_EXIT_MODE       5
-#define CMD_ATTENTION       6
-#define CMD_DP_STATUS      16
-#define CMD_DP_CONFIG      17
+#define CMD_DISCOVER_IDENT 1
+#define CMD_DISCOVER_SVID 2
+#define CMD_DISCOVER_MODES 3
+#define CMD_ENTER_MODE 4
+#define CMD_EXIT_MODE 5
+#define CMD_ATTENTION 6
+#define CMD_DP_STATUS 16
+#define CMD_DP_CONFIG 17
 
-#define VDO_CMD_VENDOR(x)    (((10 + (x)) & 0x1f))
+#define VDO_CMD_VENDOR(x) (((10 + (x)) & 0x1f))
 
 /* ChromeOS specific commands */
-#define VDO_CMD_VERSION      VDO_CMD_VENDOR(0)
-#define VDO_CMD_SEND_INFO    VDO_CMD_VENDOR(1)
-#define VDO_CMD_READ_INFO    VDO_CMD_VENDOR(2)
-#define VDO_CMD_REBOOT       VDO_CMD_VENDOR(5)
-#define VDO_CMD_FLASH_ERASE  VDO_CMD_VENDOR(6)
-#define VDO_CMD_FLASH_WRITE  VDO_CMD_VENDOR(7)
-#define VDO_CMD_ERASE_SIG    VDO_CMD_VENDOR(8)
-#define VDO_CMD_PING_ENABLE  VDO_CMD_VENDOR(10)
-#define VDO_CMD_CURRENT      VDO_CMD_VENDOR(11)
-#define VDO_CMD_FLIP         VDO_CMD_VENDOR(12)
-#define VDO_CMD_GET_LOG      VDO_CMD_VENDOR(13)
-#define VDO_CMD_CCD_EN       VDO_CMD_VENDOR(14)
-
-#define PD_VDO_VID(vdo)  ((vdo) >> 16)
+#define VDO_CMD_VERSION VDO_CMD_VENDOR(0)
+#define VDO_CMD_SEND_INFO VDO_CMD_VENDOR(1)
+#define VDO_CMD_READ_INFO VDO_CMD_VENDOR(2)
+#define VDO_CMD_REBOOT VDO_CMD_VENDOR(5)
+#define VDO_CMD_FLASH_ERASE VDO_CMD_VENDOR(6)
+#define VDO_CMD_FLASH_WRITE VDO_CMD_VENDOR(7)
+#define VDO_CMD_ERASE_SIG VDO_CMD_VENDOR(8)
+#define VDO_CMD_PING_ENABLE VDO_CMD_VENDOR(10)
+#define VDO_CMD_CURRENT VDO_CMD_VENDOR(11)
+#define VDO_CMD_FLIP VDO_CMD_VENDOR(12)
+#define VDO_CMD_GET_LOG VDO_CMD_VENDOR(13)
+#define VDO_CMD_CCD_EN VDO_CMD_VENDOR(14)
+
+#define PD_VDO_VID(vdo) ((vdo) >> 16)
 #define PD_VDO_SVDM(vdo) (((vdo) >> 15) & 1)
 #define PD_VDO_OPOS(vdo) (((vdo) >> 8) & 0x7)
-#define PD_VDO_CMD(vdo)  ((vdo) & 0x1f)
+#define PD_VDO_CMD(vdo) ((vdo)&0x1f)
 #define PD_VDO_CMDT(vdo) (((vdo) >> 6) & 0x3)
 
 /*
@@ -520,33 +583,105 @@ struct partner_active_modes {
  * [6] :: Product type DFP VDO
  *
  */
-#define VDO_INDEX_HDR            0
-#define VDO_INDEX_IDH            1
-#define VDO_INDEX_CSTAT          2
-#define VDO_INDEX_CABLE          3
-#define VDO_INDEX_PRODUCT        3
-#define VDO_INDEX_AMA            4
+#define VDO_INDEX_HDR 0
+#define VDO_INDEX_IDH 1
+#define VDO_INDEX_CSTAT 2
+#define VDO_INDEX_CABLE 3
+#define VDO_INDEX_PRODUCT 3
+#define VDO_INDEX_AMA 4
 #define VDO_INDEX_PTYPE_UFP1_VDO 4
-#define VDO_INDEX_PTYPE_CABLE1   4
-#define VDO_INDEX_PTYPE_UFP2_VDO 4
-#define VDO_INDEX_PTYPE_CABLE2   5
-#define VDO_INDEX_PTYPE_DFP_VDO  6
+#define VDO_INDEX_PTYPE_CABLE1 4
+#define VDO_INDEX_PTYPE_UFP2_VDO 5
+#define VDO_INDEX_PTYPE_CABLE2 5
+#define VDO_INDEX_PTYPE_DFP_VDO 6
 #define VDO_I(name) VDO_INDEX_##name
 
-#define VDO_IDH(usbh, usbd, ptype, is_modal, vid)		\
-	((usbh) << 31 | (usbd) << 30 | ((ptype) & 0x7) << 27	\
-	 | (is_modal) << 26 | ((vid) & 0xffff))
+/* PD Rev 2.0 ID Header VDO */
+#define VDO_IDH(usbh, usbd, ptype, is_modal, vid)            \
+	((usbh) << 31 | (usbd) << 30 | ((ptype)&0x7) << 27 | \
+	 (is_modal) << 26 | ((vid)&0xffff))
+
+/* PD Rev 3.0 ID Header VDO */
+#define VDO_IDH_REV30(usbh, usbd, ptype_u, is_modal, ptype_d, ctype, vid)      \
+	(VDO_IDH(usbh, usbd, ptype_u, is_modal, vid) | ((ptype_d)&0x7) << 23 | \
+	 ((ctype)&0x3) << 21)
 
-#define PD_IDH_PTYPE(vdo)    (((vdo) >> 27) & 0x7)
+#define PD_IDH_PTYPE(vdo) (((vdo) >> 27) & 0x7)
 #define PD_IDH_IS_MODAL(vdo) (((vdo) >> 26) & 0x1)
-#define PD_IDH_VID(vdo)      ((vdo) & 0xffff)
+#define PD_IDH_VID(vdo) ((vdo)&0xffff)
 
-#define VDO_CSTAT(tid)    ((tid) & 0xfffff)
-#define PD_CSTAT_TID(vdo) ((vdo) & 0xfffff)
+#define VDO_CSTAT(tid) ((tid)&0xfffff)
+#define PD_CSTAT_TID(vdo) ((vdo)&0xfffff)
 
-#define VDO_PRODUCT(pid, bcd) (((pid) & 0xffff) << 16 | ((bcd) & 0xffff))
+#define VDO_PRODUCT(pid, bcd) (((pid)&0xffff) << 16 | ((bcd)&0xffff))
 #define PD_PRODUCT_PID(vdo) (((vdo) >> 16) & 0xffff)
 
+/* Max Attention length is header + 1 VDO */
+#define PD_ATTENTION_MAX_VDO 2
+
+/*
+ * 6.4.10 EPR_Mode Message (PD Rev 3.1)
+ */
+
+enum pd_eprmdo_action {
+	/* 0x00: Reserved */
+	PD_EPRMDO_ACTION_ENTER = 0x01,
+	PD_EPRMDO_ACTION_ENTER_ACK = 0x02,
+	PD_EPRMDO_ACTION_ENTER_SUCCESS = 0x03,
+	PD_EPRMDO_ACTION_ENTER_FAILED = 0x04,
+	PD_EPRMDO_ACTION_EXIT = 0x05,
+	/* 0x06 ... 0xFF: Reserved */
+} __packed;
+BUILD_ASSERT(sizeof(enum pd_eprmdo_action) == 1);
+
+enum pd_eprmdo_enter_failed_data {
+	PD_EPRMDO_ENTER_FAILED_DATA_UNKNOWN = 0x00,
+	PD_EPRMDO_ENTER_FAILED_DATA_CABLE = 0x01,
+	PD_EPRMDO_ENTER_FAILED_DATA_VCONN = 0x02,
+	PD_EPRMDO_ENTER_FAILED_DATA_RDO = 0x03,
+	PD_EPRMDO_ENTER_FAILED_DATA_UNABLE = 0x04,
+	PD_EPRMDO_ENTER_FAILED_DATA_PDO = 0x05,
+} __packed;
+BUILD_ASSERT(sizeof(enum pd_eprmdo_enter_failed_data) == 1);
+
+struct eprmdo {
+	uint16_t reserved;
+	enum pd_eprmdo_enter_failed_data data;
+	enum pd_eprmdo_action action;
+};
+BUILD_ASSERT(sizeof(struct eprmdo) == 4);
+
+/*
+ * 6.5.14 Extended Control Message
+ */
+enum pd_ext_ctrl_msg_type {
+	/* 0: Reserved */
+	PD_EXT_CTRL_EPR_GET_SOURCE_CAP = 1,
+	PD_EXT_CTRL_EPR_GET_SINK_CAP = 2,
+	PD_EXT_CTRL_EPR_KEEPALIVE = 3,
+	PD_EXT_CTRL_EPR_KEEPALIVE_ACK = 4,
+	/* 5-255: Reserved */
+} __packed;
+BUILD_ASSERT(sizeof(enum pd_ext_ctrl_msg_type) == 1);
+
+/* Extended Control Data Block (ECDB) */
+struct pd_ecdb {
+	uint8_t type;
+	uint8_t data;
+} __packed;
+
+/* PD Rev 3.1 Revision Message Data Object (RMDO) */
+struct rmdo {
+	uint32_t reserved : 16;
+	uint32_t minor_ver : 4;
+	uint32_t major_ver : 4;
+	uint32_t minor_rev : 4;
+	uint32_t major_rev : 4;
+};
+
+/* Confirm RMDO is 32 bits. */
+BUILD_ASSERT(sizeof(struct rmdo) == 4);
+
 /*
  * Message id starts from 0 to 7. If last_msg_id is initialized to 0,
  * it will lead to repetitive message id with first received packet,
@@ -568,9 +703,9 @@ enum pd_rev_type {
 };
 
 #ifdef CONFIG_USB_PD_REV30
-#define PD_REVISION     PD_REV30
+#define PD_REVISION PD_REV30
 #else
-#define PD_REVISION     PD_REV20
+#define PD_REVISION PD_REV20
 #endif
 
 #if defined(CONFIG_USB_PD_TCPMV1)
@@ -595,18 +730,17 @@ struct pd_cable {
 
 	/* Cable revision */
 	enum pd_rev_type rev;
-
 };
 
 /* Note: These flags are only used for TCPMv1 */
 /* Check if Thunderbolt-compatible mode enabled */
-#define CABLE_FLAGS_TBT_COMPAT_ENABLE	   BIT(0)
+#define CABLE_FLAGS_TBT_COMPAT_ENABLE BIT(0)
 /* Flag to limit speed to TBT Gen 2 passive cable */
 #define CABLE_FLAGS_TBT_COMPAT_LIMIT_SPEED BIT(1)
 /* Flag for checking if device is USB4.0 capable */
-#define CABLE_FLAGS_USB4_CAPABLE           BIT(2)
+#define CABLE_FLAGS_USB4_CAPABLE BIT(2)
 /* Flag for entering ENTER_USB mode */
-#define CABLE_FLAGS_ENTER_USB_MODE         BIT(3)
+#define CABLE_FLAGS_ENTER_USB_MODE BIT(3)
 
 /*
  * SVDM Discover SVIDs request -> response
@@ -616,9 +750,9 @@ struct pd_cable {
  * mark the end of SVIDs.  If more than 12 SVIDs are supported command SHOULD be
  * repeated.
  */
-#define VDO_SVID(svid0, svid1) (((svid0) & 0xffff) << 16 | ((svid1) & 0xffff))
+#define VDO_SVID(svid0, svid1) (((svid0)&0xffff) << 16 | ((svid1)&0xffff))
 #define PD_VDO_SVID_SVID0(vdo) ((vdo) >> 16)
-#define PD_VDO_SVID_SVID1(vdo) ((vdo) & 0xffff)
+#define PD_VDO_SVID_SVID1(vdo) ((vdo)&0xffff)
 
 /*
  * Google modes capabilities
@@ -648,10 +782,9 @@ struct pd_cable {
  *           Other bits are reserved.
  * <1:0>   : signal direction ( 00b=rsv, 01b=sink, 10b=src 11b=both )
  */
-#define VDO_MODE_DP(snkp, srcp, usb, gdr, sign, sdir)			\
-	(((snkp) & 0xff) << 16 | ((srcp) & 0xff) << 8			\
-	 | ((usb) & 1) << 7 | ((gdr) & 1) << 6 | ((sign) & 0xF) << 2	\
-	 | ((sdir) & 0x3))
+#define VDO_MODE_DP(snkp, srcp, usb, gdr, sign, sdir)                \
+	(((snkp)&0xff) << 16 | ((srcp)&0xff) << 8 | ((usb)&1) << 7 | \
+	 ((gdr)&1) << 6 | ((sign)&0xF) << 2 | ((sdir)&0x3))
 
 #define MODE_DP_DFP_PIN_SHIFT 8
 #define MODE_DP_UFP_PIN_SHIFT 16
@@ -665,11 +798,11 @@ struct pd_cable {
 /* Pin configs A/B/C/D/E/F */
 #define MODE_DP_PIN_CAPS_MASK 0x3f
 
-#define MODE_DP_V13  0x1
+#define MODE_DP_V13 0x1
 #define MODE_DP_GEN2 0x2
 
-#define MODE_DP_SNK  0x1
-#define MODE_DP_SRC  0x2
+#define MODE_DP_SNK 0x1
+#define MODE_DP_SRC 0x2
 #define MODE_DP_BOTH 0x3
 
 #define MODE_DP_CABLE_SHIFT 6
@@ -686,9 +819,10 @@ struct pd_cable {
  * or UFP_D (if receptacle==1)
  * Also refer to DisplayPort Alt Mode Capabilities Clarification (4/30/2015)
  */
-#define PD_DP_PIN_CAPS(x) ((((x) >> MODE_DP_CABLE_SHIFT) & 0x1) \
-	? (((x) >> MODE_DP_UFP_PIN_SHIFT) & MODE_DP_PIN_CAPS_MASK) \
-	: (((x) >> MODE_DP_DFP_PIN_SHIFT) & MODE_DP_PIN_CAPS_MASK))
+#define PD_DP_PIN_CAPS(x)                                                   \
+	((((x) >> MODE_DP_CABLE_SHIFT) & 0x1) ?                             \
+		 (((x) >> MODE_DP_UFP_PIN_SHIFT) & MODE_DP_PIN_CAPS_MASK) : \
+		 (((x) >> MODE_DP_DFP_PIN_SHIFT) & MODE_DP_PIN_CAPS_MASK))
 
 /*
  * DisplayPort Status VDO
@@ -704,10 +838,10 @@ struct pd_cable {
  * <1:0>  : connect status : 00b ==  no (DFP|UFP)_D is connected or disabled.
  *          01b == DFP_D connected, 10b == UFP_D connected, 11b == both.
  */
-#define VDO_DP_STATUS(irq, lvl, amode, usbc, mf, en, lp, conn)		\
-	(((irq) & 1) << 8 | ((lvl) & 1) << 7 | ((amode) & 1) << 6	\
-	 | ((usbc) & 1) << 5 | ((mf) & 1) << 4 | ((en) & 1) << 3	\
-	 | ((lp) & 1) << 2 | ((conn & 0x3) << 0))
+#define VDO_DP_STATUS(irq, lvl, amode, usbc, mf, en, lp, conn)             \
+	(((irq)&1) << 8 | ((lvl)&1) << 7 | ((amode)&1) << 6 |              \
+	 ((usbc)&1) << 5 | ((mf)&1) << 4 | ((en)&1) << 3 | ((lp)&1) << 2 | \
+	 ((conn & 0x3) << 0))
 
 #define PD_VDO_DPSTS_MF_MASK BIT(4)
 
@@ -716,9 +850,9 @@ struct pd_cable {
 #define PD_VDO_DPSTS_MF_PREF(x) (((x) >> 4) & 1)
 
 /* Per DisplayPort Spec v1.3 Section 3.3 */
-#define HPD_USTREAM_DEBOUNCE_LVL (2*MSEC)
+#define HPD_USTREAM_DEBOUNCE_LVL (2 * MSEC)
 #define HPD_USTREAM_DEBOUNCE_IRQ (250)
-#define HPD_DSTREAM_DEBOUNCE_IRQ (500)  /* between 500-1000us */
+#define HPD_DSTREAM_DEBOUNCE_IRQ (500) /* between 500-1000us */
 
 /*
  * DisplayPort Configure VDO
@@ -732,7 +866,7 @@ struct pd_cable {
  * <1:0>   : cfg : 00 == USB, 01 == DFP_D, 10 == UFP_D, 11 == reserved
  */
 #define VDO_DP_CFG(pin, sig, cfg) \
-	(((pin) & 0xff) << 8 | ((sig) & 0xf) << 2 | ((cfg) & 0x3))
+	(((pin)&0xff) << 8 | ((sig)&0xf) << 2 | ((cfg)&0x3))
 
 #define PD_DP_CFG_DPON(x) (((x & 0x3) == 1) || ((x & 0x3) == 2))
 /*
@@ -740,18 +874,18 @@ struct pd_cable {
  * for backward compatibility, if it is null,
  * get the former sink pin assignment we used to be in <23:16>.
  */
-#define PD_DP_CFG_PIN(x) ((((x) >> 8) & 0xff) ? (((x) >> 8) & 0xff) \
-					      : (((x) >> 16) & 0xff))
+#define PD_DP_CFG_PIN(x) \
+	((((x) >> 8) & 0xff) ? (((x) >> 8) & 0xff) : (((x) >> 16) & 0xff))
 /*
  * ChromeOS specific PD device Hardware IDs. Used to identify unique
  * products and used in VDO_INFO. Note this field is 10 bits.
  */
-#define USB_PD_HW_DEV_ID_RESERVED    0
-#define USB_PD_HW_DEV_ID_ZINGER      1
-#define USB_PD_HW_DEV_ID_MINIMUFFIN  2
-#define USB_PD_HW_DEV_ID_DINGDONG    3
-#define USB_PD_HW_DEV_ID_HOHO        4
-#define USB_PD_HW_DEV_ID_HONEYBUNS   5
+#define USB_PD_HW_DEV_ID_RESERVED 0
+#define USB_PD_HW_DEV_ID_ZINGER 1
+#define USB_PD_HW_DEV_ID_MINIMUFFIN 2
+#define USB_PD_HW_DEV_ID_DINGDONG 3
+#define USB_PD_HW_DEV_ID_HOHO 4
+#define USB_PD_HW_DEV_ID_HONEYBUNS 5
 
 /*
  * ChromeOS specific VDO_CMD_READ_INFO responds with device info including:
@@ -761,77 +895,91 @@ struct pd_cable {
  * SW Debug Version: Software version useful for debugging (15 bits)
  * IS RW: True if currently in RW, False otherwise (1 bit)
  */
-#define VDO_INFO(id, id_minor, ver, is_rw) ((id_minor) << 26 \
-				  | ((id) & 0x3ff) << 16 \
-				  | ((ver) & 0x7fff) << 1 \
-				  | ((is_rw) & 1))
-#define VDO_INFO_HW_DEV_ID(x)    ((x) >> 16)
-#define VDO_INFO_SW_DBG_VER(x)   (((x) >> 1) & 0x7fff)
-#define VDO_INFO_IS_RW(x)        ((x) & 1)
+#define VDO_INFO(id, id_minor, ver, is_rw)                             \
+	((id_minor) << 26 | ((id)&0x3ff) << 16 | ((ver)&0x7fff) << 1 | \
+	 ((is_rw)&1))
+#define VDO_INFO_HW_DEV_ID(x) ((x) >> 16)
+#define VDO_INFO_SW_DBG_VER(x) (((x) >> 1) & 0x7fff)
+#define VDO_INFO_IS_RW(x) ((x)&1)
 
 #define HW_DEV_ID_MAJ(x) (x & 0x3ff)
 #define HW_DEV_ID_MIN(x) ((x) >> 10)
 
 /* USB-IF SIDs */
-#define USB_SID_PD          0xff00 /* power delivery */
+#define USB_SID_PD 0xff00 /* power delivery */
 #define USB_SID_DISPLAYPORT 0xff01
 
 #define USB_GOOGLE_TYPEC_URL "http://www.google.com/chrome/devices/typec"
-/* USB Vendor ID assigned to Google Inc. */
+/* USB Vendor ID assigned to Google LLC */
 #define USB_VID_GOOGLE 0x18d1
 
 /* Other Vendor IDs */
-#define USB_VID_APPLE  0x05ac
+#define USB_VID_APPLE 0x05ac
 #define USB_PID1_APPLE 0x1012
 #define USB_PID2_APPLE 0x1013
-#define USB_VID_INTEL  0x8087
+
+#define USB_VID_HP 0x03F0
+#define USB_PID_HP_USB_C_DOCK_G5 0x036B
+#define USB_PID_HP_USB_C_A_UNIV_DOCK_G2 0x096B
+#define USB_PID_HP_E24D_DOCK_MONITOR 0x0467
+#define USB_PID_HP_ELITE_E233_MONITOR 0x1747
+#define USB_PID_HP_E244D_DOCK_MONITOR 0x056D
+#define USB_PID_HP_E274D_DOCK_MONITOR 0x016E
+
+#define USB_VID_INTEL 0x8087
+
+#define USB_VID_FRAMEWORK 0X32ac
+#define USB_PID_FRAMEWORK_HDMI_CARD 0X2
+#define USB_PID_FRAMEWORK_DP_CARD 0X3
 
 /* Timeout for message receive in microseconds */
 #define USB_PD_RX_TMOUT_US 1800
 
+/* Power button press length triggered by USB PD short button press */
+#define USB_PD_SHORT_BUTTON_PRESS_MS 500
+
 /* --- Protocol layer functions --- */
 
 enum pd_states {
-	PD_STATE_DISABLED,			/* C0  */
-	PD_STATE_SUSPENDED,			/* C1  */
-	PD_STATE_SNK_DISCONNECTED,		/* C2  */
-	PD_STATE_SNK_DISCONNECTED_DEBOUNCE,	/* C3  */
-	PD_STATE_SNK_HARD_RESET_RECOVER,	/* C4  */
-	PD_STATE_SNK_DISCOVERY,			/* C5  */
-	PD_STATE_SNK_REQUESTED,			/* C6  */
-	PD_STATE_SNK_TRANSITION,		/* C7  */
-	PD_STATE_SNK_READY,			/* C8  */
-	PD_STATE_SNK_SWAP_INIT,			/* C9  */
-	PD_STATE_SNK_SWAP_SNK_DISABLE,		/* C10 */
-	PD_STATE_SNK_SWAP_SRC_DISABLE,		/* C11 */
-	PD_STATE_SNK_SWAP_STANDBY,		/* C12 */
-	PD_STATE_SNK_SWAP_COMPLETE,		/* C13 */
-	PD_STATE_SRC_DISCONNECTED,		/* C14 */
-	PD_STATE_SRC_DISCONNECTED_DEBOUNCE,	/* C15 */
-	PD_STATE_SRC_HARD_RESET_RECOVER,	/* C16 */
-	PD_STATE_SRC_STARTUP,			/* C17 */
-	PD_STATE_SRC_DISCOVERY,			/* C18 */
-	PD_STATE_SRC_NEGOCIATE,			/* C19 */
-	PD_STATE_SRC_ACCEPTED,			/* C20 */
-	PD_STATE_SRC_POWERED,			/* C21 */
-	PD_STATE_SRC_TRANSITION,		/* C22 */
-	PD_STATE_SRC_READY,			/* C23 */
-	PD_STATE_SRC_GET_SINK_CAP,		/* C24 */
-	PD_STATE_DR_SWAP,			/* C25 */
-	PD_STATE_SRC_SWAP_INIT,			/* C26 */
-	PD_STATE_SRC_SWAP_SNK_DISABLE,		/* C27 */
-	PD_STATE_SRC_SWAP_SRC_DISABLE,		/* C28 */
-	PD_STATE_SRC_SWAP_STANDBY,		/* C29 */
-	PD_STATE_VCONN_SWAP_SEND,		/* C30 */
-	PD_STATE_VCONN_SWAP_INIT,		/* C31 */
-	PD_STATE_VCONN_SWAP_READY,		/* C32 */
-	PD_STATE_SOFT_RESET,			/* C33 */
-	PD_STATE_HARD_RESET_SEND,		/* C34 */
-	PD_STATE_HARD_RESET_EXECUTE,		/* C35 */
-	PD_STATE_BIST_RX,			/* C36 */
-	PD_STATE_BIST_TX,			/* C37 */
-	PD_STATE_DRP_AUTO_TOGGLE,		/* C38 */
-	PD_STATE_ENTER_USB,			/* C39 */
+	PD_STATE_DISABLED, /* C0  */
+	PD_STATE_SUSPENDED, /* C1  */
+	PD_STATE_SNK_DISCONNECTED, /* C2  */
+	PD_STATE_SNK_DISCONNECTED_DEBOUNCE, /* C3  */
+	PD_STATE_SNK_HARD_RESET_RECOVER, /* C4  */
+	PD_STATE_SNK_DISCOVERY, /* C5  */
+	PD_STATE_SNK_REQUESTED, /* C6  */
+	PD_STATE_SNK_TRANSITION, /* C7  */
+	PD_STATE_SNK_READY, /* C8  */
+	PD_STATE_SNK_SWAP_INIT, /* C9  */
+	PD_STATE_SNK_SWAP_SNK_DISABLE, /* C10 */
+	PD_STATE_SNK_SWAP_SRC_DISABLE, /* C11 */
+	PD_STATE_SNK_SWAP_STANDBY, /* C12 */
+	PD_STATE_SNK_SWAP_COMPLETE, /* C13 */
+	PD_STATE_SRC_DISCONNECTED, /* C14 */
+	PD_STATE_SRC_DISCONNECTED_DEBOUNCE, /* C15 */
+	PD_STATE_SRC_HARD_RESET_RECOVER, /* C16 */
+	PD_STATE_SRC_STARTUP, /* C17 */
+	PD_STATE_SRC_DISCOVERY, /* C18 */
+	PD_STATE_SRC_NEGOCIATE, /* C19 */
+	PD_STATE_SRC_ACCEPTED, /* C20 */
+	PD_STATE_SRC_POWERED, /* C21 */
+	PD_STATE_SRC_TRANSITION, /* C22 */
+	PD_STATE_SRC_READY, /* C23 */
+	PD_STATE_SRC_GET_SINK_CAP, /* C24 */
+	PD_STATE_DR_SWAP, /* C25 */
+	PD_STATE_SRC_SWAP_INIT, /* C26 */
+	PD_STATE_SRC_SWAP_SNK_DISABLE, /* C27 */
+	PD_STATE_SRC_SWAP_SRC_DISABLE, /* C28 */
+	PD_STATE_SRC_SWAP_STANDBY, /* C29 */
+	PD_STATE_VCONN_SWAP_SEND, /* C30 */
+	PD_STATE_VCONN_SWAP_INIT, /* C31 */
+	PD_STATE_VCONN_SWAP_READY, /* C32 */
+	PD_STATE_SOFT_RESET, /* C33 */
+	PD_STATE_HARD_RESET_SEND, /* C34 */
+	PD_STATE_HARD_RESET_EXECUTE, /* C35 */
+	PD_STATE_BIST_RX, /* C36 */
+	PD_STATE_BIST_TX, /* C37 */
+	PD_STATE_DRP_AUTO_TOGGLE, /* C38 */
 	/* Number of states. Not an actual state. */
 	PD_STATE_COUNT,
 };
@@ -876,23 +1024,23 @@ enum pd_states {
 
 #ifdef CONFIG_USB_PD_TCPMV1
 /* Flags used for TCPMv1 */
-#define PD_FLAGS_PING_ENABLED      BIT(0) /* SRC_READY pings enabled */
-#define PD_FLAGS_PARTNER_DR_POWER  BIT(1) /* port partner is dualrole power */
-#define PD_FLAGS_PARTNER_DR_DATA   BIT(2) /* port partner is dualrole data */
-#define PD_FLAGS_CHECK_IDENTITY    BIT(3) /* discover identity in READY */
-#define PD_FLAGS_SNK_CAP_RECVD     BIT(4) /* sink capabilities received */
-#define PD_FLAGS_TCPC_DRP_TOGGLE   BIT(5) /* TCPC-controlled DRP toggling */
+#define PD_FLAGS_PING_ENABLED BIT(0) /* SRC_READY pings enabled */
+#define PD_FLAGS_PARTNER_DR_POWER BIT(1) /* port partner is dualrole power */
+#define PD_FLAGS_PARTNER_DR_DATA BIT(2) /* port partner is dualrole data */
+#define PD_FLAGS_CHECK_IDENTITY BIT(3) /* discover identity in READY */
+#define PD_FLAGS_SNK_CAP_RECVD BIT(4) /* sink capabilities received */
+#define PD_FLAGS_TCPC_DRP_TOGGLE BIT(5) /* TCPC-controlled DRP toggling */
 #define PD_FLAGS_EXPLICIT_CONTRACT BIT(6) /* explicit pwr contract in place */
-#define PD_FLAGS_VBUS_NEVER_LOW    BIT(7) /* VBUS input has never been low */
-#define PD_FLAGS_PREVIOUS_PD_CONN  BIT(8) /* previously PD connected */
-#define PD_FLAGS_CHECK_PR_ROLE     BIT(9) /* check power role in READY */
-#define PD_FLAGS_CHECK_DR_ROLE     BIT(10)/* check data role in READY */
-#define PD_FLAGS_PARTNER_UNCONSTR  BIT(11)/* port partner unconstrained pwr */
-#define PD_FLAGS_VCONN_ON          BIT(12)/* vconn is being sourced */
-#define PD_FLAGS_TRY_SRC           BIT(13)/* Try.SRC states are active */
-#define PD_FLAGS_PARTNER_USB_COMM  BIT(14)/* port partner is USB comms */
-#define PD_FLAGS_UPDATE_SRC_CAPS   BIT(15)/* send new source capabilities */
-#define PD_FLAGS_TS_DTS_PARTNER    BIT(16)/* partner has rp/rp or rd/rd */
+#define PD_FLAGS_VBUS_NEVER_LOW BIT(7) /* VBUS input has never been low */
+#define PD_FLAGS_PREVIOUS_PD_CONN BIT(8) /* previously PD connected */
+#define PD_FLAGS_CHECK_PR_ROLE BIT(9) /* check power role in READY */
+#define PD_FLAGS_CHECK_DR_ROLE BIT(10) /* check data role in READY */
+#define PD_FLAGS_PARTNER_UNCONSTR BIT(11) /* port partner unconstrained pwr */
+#define PD_FLAGS_VCONN_ON BIT(12) /* vconn is being sourced */
+#define PD_FLAGS_TRY_SRC BIT(13) /* Try.SRC states are active */
+#define PD_FLAGS_PARTNER_USB_COMM BIT(14) /* port partner is USB comms */
+#define PD_FLAGS_UPDATE_SRC_CAPS BIT(15) /* send new source capabilities */
+#define PD_FLAGS_TS_DTS_PARTNER BIT(16) /* partner has rp/rp or rd/rd */
 /*
  * These PD_FLAGS_LPM* flags track the software state (PD_LPM_FLAGS_REQUESTED)
  * and hardware state (PD_LPM_FLAGS_ENGAGED) of the TCPC low power mode.
@@ -900,26 +1048,26 @@ enum pd_states {
  * low power (when PD_LPM_FLAGS_ENGAGED is changing).
  */
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-#define PD_FLAGS_LPM_REQUESTED     BIT(17)/* Tracks SW LPM state */
-#define PD_FLAGS_LPM_ENGAGED       BIT(18)/* Tracks HW LPM state */
-#define PD_FLAGS_LPM_TRANSITION    BIT(19)/* Tracks HW LPM transition */
-#define PD_FLAGS_LPM_EXIT          BIT(19)/* Tracks HW LPM exit */
+#define PD_FLAGS_LPM_REQUESTED BIT(17) /* Tracks SW LPM state */
+#define PD_FLAGS_LPM_ENGAGED BIT(18) /* Tracks HW LPM state */
+#define PD_FLAGS_LPM_TRANSITION BIT(19) /* Tracks HW LPM transition */
+#define PD_FLAGS_LPM_EXIT BIT(19) /* Tracks HW LPM exit */
 #endif
 /*
  * Tracks whether port negotiation may have stalled due to not starting reset
  * timers in SNK_DISCOVERY
  */
-#define PD_FLAGS_SNK_WAITING_BATT  BIT(21)
+#define PD_FLAGS_SNK_WAITING_BATT BIT(21)
 /* Check vconn state in READY */
 #define PD_FLAGS_CHECK_VCONN_STATE BIT(22)
 #endif /* CONFIG_USB_PD_TCPMV1 */
 
 /* Per-port battery backed RAM flags */
 #define PD_BBRMFLG_EXPLICIT_CONTRACT BIT(0)
-#define PD_BBRMFLG_POWER_ROLE        BIT(1)
-#define PD_BBRMFLG_DATA_ROLE         BIT(2)
-#define PD_BBRMFLG_VCONN_ROLE        BIT(3)
-#define PD_BBRMFLG_DBGACC_ROLE       BIT(4)
+#define PD_BBRMFLG_POWER_ROLE BIT(1)
+#define PD_BBRMFLG_DATA_ROLE BIT(2)
+#define PD_BBRMFLG_VCONN_ROLE BIT(3)
+#define PD_BBRMFLG_DBGACC_ROLE BIT(4)
 
 /* Initial value for CC debounce variable */
 #define PD_CC_UNSET -1
@@ -942,27 +1090,33 @@ enum pd_dual_role_states {
  * NOTE: These are usually set by host commands from the AP.
  */
 enum pd_dpm_request {
-	DPM_REQUEST_DR_SWAP             = BIT(0),
-	DPM_REQUEST_PR_SWAP             = BIT(1),
-	DPM_REQUEST_VCONN_SWAP          = BIT(2),
-	DPM_REQUEST_GOTO_MIN            = BIT(3),
-	DPM_REQUEST_SRC_CAP_CHANGE      = BIT(4),
-	DPM_REQUEST_GET_SNK_CAPS        = BIT(5),
-	DPM_REQUEST_SEND_PING           = BIT(6),
-	DPM_REQUEST_SOURCE_CAP          = BIT(7),
-	DPM_REQUEST_NEW_POWER_LEVEL     = BIT(8),
-	DPM_REQUEST_VDM                 = BIT(9),
-	DPM_REQUEST_BIST_RX             = BIT(10),
-	DPM_REQUEST_BIST_TX             = BIT(11),
-	DPM_REQUEST_SNK_STARTUP         = BIT(12),
-	DPM_REQUEST_SRC_STARTUP         = BIT(13),
-	DPM_REQUEST_HARD_RESET_SEND     = BIT(14),
-	DPM_REQUEST_SOFT_RESET_SEND     = BIT(15),
-	DPM_REQUEST_PORT_DISCOVERY      = BIT(16),
-	DPM_REQUEST_SEND_ALERT          = BIT(17),
-	DPM_REQUEST_ENTER_USB           = BIT(18),
-	DPM_REQUEST_GET_SRC_CAPS        = BIT(19),
-	DPM_REQUEST_EXIT_MODES          = BIT(20),
+	DPM_REQUEST_DR_SWAP = BIT(0),
+	DPM_REQUEST_PR_SWAP = BIT(1),
+	DPM_REQUEST_VCONN_SWAP = BIT(2),
+	DPM_REQUEST_GOTO_MIN = BIT(3),
+	DPM_REQUEST_SRC_CAP_CHANGE = BIT(4),
+	DPM_REQUEST_GET_SNK_CAPS = BIT(5),
+	DPM_REQUEST_SEND_PING = BIT(6),
+	DPM_REQUEST_SOURCE_CAP = BIT(7),
+	DPM_REQUEST_NEW_POWER_LEVEL = BIT(8),
+	DPM_REQUEST_VDM = BIT(9),
+	DPM_REQUEST_BIST_TX = BIT(10),
+	DPM_REQUEST_SNK_STARTUP = BIT(11),
+	DPM_REQUEST_SRC_STARTUP = BIT(12),
+	DPM_REQUEST_HARD_RESET_SEND = BIT(13),
+	DPM_REQUEST_SOFT_RESET_SEND = BIT(14),
+	DPM_REQUEST_PORT_DISCOVERY = BIT(15),
+	DPM_REQUEST_SEND_ALERT = BIT(16),
+	DPM_REQUEST_ENTER_USB = BIT(17),
+	DPM_REQUEST_GET_SRC_CAPS = BIT(18),
+	DPM_REQUEST_EXIT_MODES = BIT(19),
+	DPM_REQUEST_SOP_PRIME_SOFT_RESET_SEND = BIT(20),
+	DPM_REQUEST_FRS_DET_ENABLE = BIT(21),
+	DPM_REQUEST_FRS_DET_DISABLE = BIT(22),
+	DPM_REQUEST_DATA_RESET = BIT(23),
+	DPM_REQUEST_GET_REVISION = BIT(24),
+	DPM_REQUEST_EPR_MODE_ENTRY = BIT(25),
+	DPM_REQUEST_EPR_MODE_EXIT = BIT(26),
 };
 
 /**
@@ -995,8 +1149,17 @@ enum pd_data_role pd_get_data_role(int port);
  */
 enum pd_power_role pd_get_power_role(int port);
 
-/*
- * Return true if PD is capable of trying as source else false
+/**
+ * Check if the battery is capable of powering the system
+ *
+ * @return true if capable of, else false.
+ */
+bool pd_is_battery_capable(void);
+
+/**
+ * Check if PD is capable of trying as source
+ *
+ * @return true if capable of, else false.
  */
 bool pd_is_try_source_capable(void);
 
@@ -1057,9 +1220,16 @@ bool pd_get_partner_dual_role_power(int port);
  */
 bool pd_get_partner_unconstr_power(int port);
 
-/* Control Message type */
+/**
+ * Check if poower role swap may be needed on AP resume.
+ *
+ * @param port USB-C Port number
+ */
+void pd_resume_check_pr_swap_needed(int port);
+
+/* Control Message type - USB-PD Spec Rev 3.0, Ver 1.1, Table 6-5 */
 enum pd_ctrl_msg_type {
-	/* 0 Reserved */
+	PD_CTRL_INVALID = 0, /* 0 Reserved - DO NOT PUT IN MESSAGES */
 	PD_CTRL_GOOD_CRC = 1,
 	PD_CTRL_GOTO_MIN = 2,
 	PD_CTRL_ACCEPT = 3,
@@ -1073,44 +1243,119 @@ enum pd_ctrl_msg_type {
 	PD_CTRL_VCONN_SWAP = 11,
 	PD_CTRL_WAIT = 12,
 	PD_CTRL_SOFT_RESET = 13,
-	/* 14-15 Reserved */
-
 	/* Used for REV 3.0 */
+	PD_CTRL_DATA_RESET = 14,
+	PD_CTRL_DATA_RESET_COMPLETE = 15,
 	PD_CTRL_NOT_SUPPORTED = 16,
 	PD_CTRL_GET_SOURCE_CAP_EXT = 17,
 	PD_CTRL_GET_STATUS = 18,
 	PD_CTRL_FR_SWAP = 19,
 	PD_CTRL_GET_PPS_STATUS = 20,
 	PD_CTRL_GET_COUNTRY_CODES = 21,
-	/* 22-31 Reserved */
+	PD_CTRL_GET_SINK_CAP_EXT = 22,
+	/* Used for REV 3.1 */
+	PD_CTRL_GET_SOURCE_INFO = 23,
+	PD_CTRL_GET_REVISION = 24,
+	/* 25-31 Reserved */
 };
 
 /* Control message types which always mark the start of an AMS */
-#define PD_CTRL_AMS_START_MASK ((1 << PD_CTRL_GOTO_MIN) | \
-				(1 << PD_CTRL_GET_SOURCE_CAP) | \
-				(1 << PD_CTRL_GET_SINK_CAP) | \
-				(1 << PD_CTRL_DR_SWAP) | \
-				(1 << PD_CTRL_PR_SWAP) | \
-				(1 << PD_CTRL_VCONN_SWAP) | \
-				(1 << PD_CTRL_GET_SOURCE_CAP_EXT) | \
-				(1 << PD_CTRL_GET_STATUS) | \
-				(1 << PD_CTRL_FR_SWAP) | \
-				(1 << PD_CTRL_GET_PPS_STATUS) | \
-				(1 << PD_CTRL_GET_COUNTRY_CODES))
-
+#define PD_CTRL_AMS_START_MASK                                           \
+	((1 << PD_CTRL_GOTO_MIN) | (1 << PD_CTRL_GET_SOURCE_CAP) |       \
+	 (1 << PD_CTRL_GET_SINK_CAP) | (1 << PD_CTRL_DR_SWAP) |          \
+	 (1 << PD_CTRL_PR_SWAP) | (1 << PD_CTRL_VCONN_SWAP) |            \
+	 (1 << PD_CTRL_GET_SOURCE_CAP_EXT) | (1 << PD_CTRL_GET_STATUS) | \
+	 (1 << PD_CTRL_FR_SWAP) | (1 << PD_CTRL_GET_PPS_STATUS) |        \
+	 (1 << PD_CTRL_GET_COUNTRY_CODES))
 
 /* Battery Status Data Object fields for REV 3.0 */
 #define BSDO_CAP_UNKNOWN 0xffff
-#define BSDO_CAP(n)      (((n) & 0xffff) << 16)
-#define BSDO_INVALID     BIT(8)
-#define BSDO_PRESENT     BIT(9)
+#define BSDO_CAP(n) (((n)&0xffff) << 16)
+#define BSDO_INVALID BIT(8)
+#define BSDO_PRESENT BIT(9)
 #define BSDO_DISCHARGING BIT(10)
-#define BSDO_IDLE        BIT(11)
+#define BSDO_IDLE BIT(11)
+
+/* Battery Capability offsets for 16-bit array indexes */
+#define BCDB_VID 0
+#define BCDB_PID 1
+#define BCDB_DESIGN_CAP 2
+#define BCDB_FULL_CAP 3
+#define BCDB_BATT_TYPE 4
+
+/* Battery Capability Data Block (BCDB) in struct format.
+ * See USB-PD spec Rev 3.1, V 1.3 section 6.5.5
+ */
+struct pd_bcdb {
+	/* Vendor ID*/
+	uint16_t vid;
+	/* Product ID */
+	uint16_t pid;
+	/* Battery’s design capacity in 0.1 Wh (0 = no batt, 0xFFFF = unknown)
+	 */
+	uint16_t design_cap;
+	/* Battery’s last full charge capacity in 0.1 Wh (0 = no batt,
+	 * 0xFFFF = unknown)
+	 */
+	uint16_t last_full_charge_cap;
+	/* Bit 0 indicates if the request was invalid. Other bits reserved. */
+	uint8_t battery_type;
+} __packed;
 
-/* Get Battery Cap Message fields for REV 3.0 */
-#define BATT_CAP_REF(n)  (((n) >> 16) & 0xff)
+/* Maximum number of different batteries that can be queried through Get Battery
+ * Status and Get Battery Capability requests. Indices 0 to 3 are fixed
+ * batteries and indices 4 to 7 are hot-swappable batteries. Not all are
+ * necessarily present.
+ *
+ * See USB-PD spec Rev 3.1, V 1.3 sections 6.5.4 - .5
+ */
+#define PD_BATT_MAX (8)
 
-/* Extended message type for REV 3.0 */
+/*
+ * Get Battery Cap Message fields for REV 3.0 (assumes extended header is
+ * present in first two bytes)
+ */
+#define BATT_CAP_REF(n) (((n) >> 16) & 0xff)
+
+/* SOP SDB fields for PD Rev 3.0 Section 6.5.2.1 */
+enum pd_sdb_temperature_status {
+	PD_SDB_TEMPERATURE_STATUS_NOT_SUPPORTED = 0,
+	PD_SDB_TEMPERATURE_STATUS_NORMAL = 2,
+	PD_SDB_TEMPERATURE_STATUS_WARNING = 4,
+	PD_SDB_TEMPERATURE_STATUS_OVER_TEMPERATURE = 6,
+} __packed;
+BUILD_ASSERT(sizeof(enum pd_sdb_temperature_status) == 1);
+
+struct pd_sdb {
+	/* SDB Fields for PD REV 3.0 */
+	uint8_t internal_temp;
+	uint8_t present_input;
+	uint8_t present_battery_input;
+	uint8_t event_flags;
+	enum pd_sdb_temperature_status temperature_status;
+	uint8_t power_status;
+	/* SDB Fields for PD REV 3.1 */
+	uint8_t power_state_change;
+};
+
+enum pd_sdb_power_state {
+	PD_SDB_POWER_STATE_NOT_SUPPORTED = 0,
+	PD_SDB_POWER_STATE_S0 = 1,
+	PD_SDB_POWER_STATE_MODERN_STANDBY = 2,
+	PD_SDB_POWER_STATE_S3 = 3,
+	PD_SDB_POWER_STATE_S4 = 4,
+	PD_SDB_POWER_STATE_S5 = 5,
+	PD_SDB_POWER_STATE_G3 = 6,
+};
+
+enum pd_sdb_power_indicator {
+	PD_SDB_POWER_INDICATOR_OFF = (0 << 3),
+	PD_SDB_POWER_INDICATOR_ON = (1 << 3),
+	PD_SDB_POWER_INDICATOR_BLINKING = (2 << 3),
+	PD_SDB_POWER_INDICATOR_BREATHING = (3 << 3),
+};
+
+/* Extended message type for REV 3.0 - USB-PD Spec 3.0, Ver 1.1, Table 6-42 */
 enum pd_ext_msg_type {
 	/* 0 Reserved */
 	PD_EXT_SOURCE_CAP = 1,
@@ -1127,44 +1372,64 @@ enum pd_ext_msg_type {
 	PD_EXT_PPS_STATUS = 12,
 	PD_EXT_COUNTRY_INFO = 13,
 	PD_EXT_COUNTRY_CODES = 14,
-	/* 15-31 Reserved */
+	/* Used for REV 3.1 */
+	PD_EXT_SINK_CAP = 15,
+	PD_EXT_CONTROL = 16,
+	PD_EXT_EPR_SOURCE_CAP = 17,
+	PD_EXT_EPR_SINK_CAP = 18,
+	/* 19-29 Reserved */
+	PD_EXT_VENDOR_DEF = 30,
+	/* 31 Reserved */
 };
 
+/* Alert Data Object fields for REV 3.1 */
+#define ADO_EXTENDED_ALERT_EVENT (BIT(24) << 7)
+#define ADO_EXTENDED_ALERT_EVENT_TYPE 0xf
 /* Alert Data Object fields for REV 3.0 */
-#define ADO_OVP_EVENT                   BIT(30)
-#define ADO_SOURCE_INPUT_CHANGE         BIT(29)
-#define ADO_OPERATING_CONDITION_CHANGE  BIT(28)
-#define ADO_OTP_EVENT                   BIT(27)
-#define ADO_OCP_EVENT                   BIT(26)
-#define ADO_BATTERY_STATUS_CHANGE       BIT(25)
-#define ADO_FIXED_BATTERIES(n)          ((n & 0xf) << 20)
-#define ADO_HOT_SWAPPABLE_BATTERIES(n)  ((n & 0xf) << 16)
-
-/* Data message type */
+#define ADO_OVP_EVENT (BIT(24) << 6)
+#define ADO_SOURCE_INPUT_CHANGE (BIT(24) << 5)
+#define ADO_OPERATING_CONDITION_CHANGE (BIT(24) << 4)
+#define ADO_OTP_EVENT (BIT(24) << 3)
+#define ADO_OCP_EVENT (BIT(24) << 2)
+#define ADO_BATTERY_STATUS_CHANGE (BIT(24) << 1)
+#define ADO_FIXED_BATTERIES(n) ((n & 0xf) << 20)
+#define ADO_HOT_SWAPPABLE_BATTERIES(n) ((n & 0xf) << 16)
+
+/* Extended alert event types for REV 3.1 */
+enum ado_extended_alert_event_type {
+	ADO_POWER_STATE_CHANGE = 0x1,
+	ADO_POWER_BUTTON_PRESS = 0x2,
+	ADO_POWER_BUTTON_RELEASE = 0x3,
+	ADO_CONTROLLER_INITIATED_WAKE = 0x4,
+};
+
+/* Data message type - USB-PD Spec Rev 3.0, Ver 1.1, Table 6-6 */
 enum pd_data_msg_type {
 	/* 0 Reserved */
 	PD_DATA_SOURCE_CAP = 1,
 	PD_DATA_REQUEST = 2,
 	PD_DATA_BIST = 3,
 	PD_DATA_SINK_CAP = 4,
-	/* 5-14 Reserved for REV 2.0 */
+	/* Used for REV 3.0 */
 	PD_DATA_BATTERY_STATUS = 5,
 	PD_DATA_ALERT = 6,
 	PD_DATA_GET_COUNTRY_INFO = 7,
-	/* 8-14 Reserved for REV 3.0 */
 	PD_DATA_ENTER_USB = 8,
+	/* Used for REV 3.1 */
+	PD_DATA_EPR_REQUEST = 9,
+	PD_DATA_EPR_MODE = 10,
+	PD_DATA_SOURCE_INFO = 11,
+	PD_DATA_REVISION = 12,
+	/* 13-14 Reserved */
 	PD_DATA_VENDOR_DEF = 15,
+	/* 16-31 Reserved */
 };
 
-
 /*
  * Cable plug. See 6.2.1.1.7 Cable Plug. Only applies to SOP' and SOP".
  * Replaced by pd_power_role for SOP packets.
  */
-enum pd_cable_plug {
-	PD_PLUG_FROM_DFP_UFP = 0,
-	PD_PLUG_FROM_CABLE = 1
-};
+enum pd_cable_plug { PD_PLUG_FROM_DFP_UFP = 0, PD_PLUG_FROM_CABLE = 1 };
 
 enum cable_outlet {
 	CABLE_PLUG = 0,
@@ -1173,11 +1438,11 @@ enum cable_outlet {
 
 /* Vconn role */
 #define PD_ROLE_VCONN_OFF 0
-#define PD_ROLE_VCONN_ON  1
+#define PD_ROLE_VCONN_ON 1
 
 /* chunk is a request or response in REV 3.0 */
 #define CHUNK_RESPONSE 0
-#define CHUNK_REQUEST  1
+#define CHUNK_REQUEST 1
 
 /* collision avoidance Rp values in REV 3.0 */
 #define SINK_TX_OK TYPEC_RP_3A0
@@ -1194,36 +1459,37 @@ enum cable_outlet {
 
 /* Port default state at startup */
 #ifdef CONFIG_USB_PD_DUAL_ROLE
-#define PD_DEFAULT_STATE(port) ((PD_ROLE_DEFAULT(port) == PD_ROLE_SOURCE) ? \
-				PD_STATE_SRC_DISCONNECTED :	      \
-				PD_STATE_SNK_DISCONNECTED)
+#define PD_DEFAULT_STATE(port)                       \
+	((PD_ROLE_DEFAULT(port) == PD_ROLE_SOURCE) ? \
+		 PD_STATE_SRC_DISCONNECTED :         \
+		 PD_STATE_SNK_DISCONNECTED)
 #else
 #define PD_DEFAULT_STATE(port) PD_STATE_SRC_DISCONNECTED
 #endif
 
-/* build extended message header */
-/* All extended messages are chunked, so set bit 15 */
+/* Build extended message header with chunking */
 #define PD_EXT_HEADER(cnum, rchk, dsize) \
-	 (BIT(15) | ((cnum) << 11) | \
-	 ((rchk) << 10) | (dsize))
+	(BIT(15) | ((cnum) << 11) | ((rchk) << 10) | (dsize))
+
+/* Build extended message header without chunking */
+#define PD_EXT_HEADER_UNCHUNKED(dsize) (dsize)
 
 /* build message header */
-#define PD_HEADER(type, prole, drole, id, cnt, rev, ext) \
-	((type) | ((rev) << 6) | \
-	((drole) << 5) | ((prole) << 8) | \
-	((id) << 9) | ((cnt) << 12) | ((ext) << 15))
+#define PD_HEADER(type, prole, drole, id, cnt, rev, ext)           \
+	((type) | ((rev) << 6) | ((drole) << 5) | ((prole) << 8) | \
+	 ((id) << 9) | ((cnt) << 12) | ((ext) << 15))
 
 /* Used for processing pd header */
-#define PD_HEADER_EXT(header)   (((header) >> 15) & 1)
-#define PD_HEADER_CNT(header)   (((header) >> 12) & 7)
+#define PD_HEADER_EXT(header) (((header) >> 15) & 1)
+#define PD_HEADER_CNT(header) (((header) >> 12) & 7)
 /*
  * NOTE: bit 4 was added in PD 3.0, and should be reserved and set to 0 in PD
  * 2.0 messages
  */
-#define PD_HEADER_TYPE(header)  ((header) & 0x1F)
-#define PD_HEADER_ID(header)    (((header) >> 9) & 7)
+#define PD_HEADER_TYPE(header) ((header)&0x1F)
+#define PD_HEADER_ID(header) (((header) >> 9) & 7)
 #define PD_HEADER_PROLE(header) (((header) >> 8) & 1)
-#define PD_HEADER_REV(header)   (((header) >> 6) & 3)
+#define PD_HEADER_REV(header) (((header) >> 6) & 3)
 #define PD_HEADER_DROLE(header) (((header) >> 5) & 1)
 
 /*
@@ -1232,56 +1498,50 @@ enum cable_outlet {
  * NOTE: This is not part of the PD spec.
  */
 #define PD_HEADER_GET_SOP(header) (((header) >> 28) & 0xf)
-#define PD_HEADER_SOP(sop) (((sop) & 0xf) << 28)
-
-enum pd_msg_type {
-	PD_MSG_SOP,
-	PD_MSG_SOP_PRIME,
-	PD_MSG_SOP_PRIME_PRIME,
-	PD_MSG_SOP_DBG_PRIME,
-	PD_MSG_SOP_DBG_PRIME_PRIME,
-	PD_MSG_SOP_CBL_RST,
-};
+#define PD_HEADER_SOP(sop) (((sop)&0xf) << 28)
 
 /* Used for processing pd extended header */
-#define PD_EXT_HEADER_CHUNKED(header)   (((header) >> 15) & 1)
+#define PD_EXT_HEADER_CHUNKED(header) (((header) >> 15) & 1)
 #define PD_EXT_HEADER_CHUNK_NUM(header) (((header) >> 11) & 0xf)
 #define PD_EXT_HEADER_REQ_CHUNK(header) (((header) >> 10) & 1)
-#define PD_EXT_HEADER_DATA_SIZE(header) ((header) & 0x1ff)
+#define PD_EXT_HEADER_DATA_SIZE(header) ((header)&0x1ff)
 
 /* Used to get extended header from the first 32-bit word of the message */
 #define GET_EXT_HEADER(msg) (msg & 0xffff)
 
 /* Extended message constants (PD 3.0, Rev. 2.0, section 6.13) */
-#define PD_MAX_EXTENDED_MSG_LEN       260
-#define PD_MAX_EXTENDED_MSG_CHUNK_LEN  26
+#define PD_MAX_EXTENDED_MSG_LEN 260
+#define PD_MAX_EXTENDED_MSG_CHUNK_LEN 26
 
 /* K-codes for special symbols */
 #define PD_SYNC1 0x18
 #define PD_SYNC2 0x11
 #define PD_SYNC3 0x06
-#define PD_RST1  0x07
-#define PD_RST2  0x19
-#define PD_EOP   0x0D
+#define PD_RST1 0x07
+#define PD_RST2 0x19
+#define PD_EOP 0x0D
 
 /* Minimum PD supply current  (mA) */
-#define PD_MIN_MA	500
+#define PD_MIN_MA 500
 
 /* Minimum PD voltage (mV) */
-#define PD_MIN_MV	5000
+#define PD_MIN_MV 5000
 
 /* No connect voltage threshold for sources based on Rp */
-#define PD_SRC_DEF_VNC_MV        1600
-#define PD_SRC_1_5_VNC_MV        1600
-#define PD_SRC_3_0_VNC_MV        2600
+#define PD_SRC_DEF_VNC_MV 1600
+#define PD_SRC_1_5_VNC_MV 1600
+#define PD_SRC_3_0_VNC_MV 2600
 
 /* Rd voltage threshold for sources based on Rp */
-#define PD_SRC_DEF_RD_THRESH_MV  200
-#define PD_SRC_1_5_RD_THRESH_MV  400
-#define PD_SRC_3_0_RD_THRESH_MV  800
+#define PD_SRC_DEF_RD_THRESH_MV 200
+#define PD_SRC_1_5_RD_THRESH_MV 400
+#define PD_SRC_3_0_RD_THRESH_MV 800
 
 /* Voltage threshold to detect connection when presenting Rd */
-#define PD_SNK_VA_MV             250
+#define PD_SNK_VA_MV 250
+
+/* Maximum power consumption while in Sink Standby */
+#define PD_SNK_STDBY_MW 2500
 
 /* --- Policy layer functions --- */
 
@@ -1297,7 +1557,7 @@ void schedule_deferred_pd_interrupt(int port);
  *         PD_REV20 for PD Revision 2.0
  *         PD_REV30 for PD Revision 3.0
  */
-int pd_get_rev(int port, enum tcpm_transmit_type type);
+int pd_get_rev(int port, enum tcpci_msg_type type);
 
 /**
  * Get current PD VDO Version of Structured VDM
@@ -1307,7 +1567,16 @@ int pd_get_rev(int port, enum tcpm_transmit_type type);
  * @return VDM_VER10 for VDM Version 1.0
  *         VDM_VER20 for VDM Version 2.0
  */
-int pd_get_vdo_ver(int port, enum tcpm_transmit_type type);
+int pd_get_vdo_ver(int port, enum tcpci_msg_type type);
+
+/**
+ * Get transmit retry count for active PD revision.
+ *
+ * @param port The port to query
+ * @param type The partner to query (SOP, SOP', or SOP'')
+ * @return The number of retries to perform when transmitting.
+ */
+int pd_get_retry_count(int port, enum tcpci_msg_type type);
 
 /**
  * Check if max voltage request is allowed (only used if
@@ -1365,19 +1634,19 @@ void pd_process_source_cap(int port, int cnt, uint32_t *src_caps);
  * @param ma reduce current to minimum value.
  * @param mv reduce voltage to minimum value.
  */
-void pd_snk_give_back(int port, uint32_t * const ma, uint32_t * const mv);
+void pd_snk_give_back(int port, uint32_t *const ma, uint32_t *const mv);
 
 /**
  * Put a cap on the max voltage requested as a sink.
  * @param mv maximum voltage in millivolts.
  */
-void pd_set_max_voltage(unsigned mv);
+void pd_set_max_voltage(unsigned int mv);
 
 /**
  * Get the max voltage that can be requested as set by pd_set_max_voltage().
  * @return max voltage
  */
-unsigned pd_get_max_voltage(void);
+unsigned int pd_get_max_voltage(void);
 
 /**
  * Check if this board supports the given input voltage.
@@ -1387,6 +1656,16 @@ unsigned pd_get_max_voltage(void);
  */
 __override_proto int pd_is_valid_input_voltage(int mv);
 
+/*
+ * Return the appropriate set of Source Capability PDOs to offer this
+ * port
+ *
+ * @param src_pdo	Will point to appropriate PDO(s) to offer
+ * @param port		USB-C port number
+ * @return		Number of PDOs
+ */
+int pd_get_source_pdo(const uint32_t **src_pdo_p, const int port);
+
 /**
  * Request a new operating voltage.
  *
@@ -1463,7 +1742,6 @@ void pd_set_external_voltage_limit(int port, int mv);
 void pd_set_input_current_limit(int port, uint32_t max_ma,
 				uint32_t supply_voltage);
 
-
 /**
  * Update the power contract if it exists.
  *
@@ -1487,14 +1765,6 @@ __override_proto void typec_set_input_current_limit(int port,
 						    typec_current_t max_ma,
 						    uint32_t supply_voltage);
 
-/**
- * Set the type-C current limit when sourcing current..
- *
- * @param port USB-C port number
- * @param rp One of enum tcpc_rp_value (eg TYPEC_RP_3A0) defining the limit.
- */
-void typec_set_source_current_limit(int port, enum tcpc_rp_value rp);
-
 /**
  * Verify board specific health status : current, voltages...
  *
@@ -1525,6 +1795,17 @@ void pd_vbus_low(int port);
  */
 __override_proto int pd_check_power_swap(int port);
 
+/**
+ * Check if we are allowed to automatically charge from port partner
+ *
+ * @param port USB-C port number
+ * @pdo_cnt number of source cap PDOs
+ * @*pdos  pointer to source cap PDOs
+ * @return True if port partner can supply power
+ */
+__override_proto bool pd_can_charge_from_device(int port, const int pdo_cnt,
+						const uint32_t *pdos);
+
 /**
  * Check if data swap is allowed.
  *
@@ -1532,8 +1813,7 @@ __override_proto int pd_check_power_swap(int port);
  * @param data_role current data role
  * @return True if data swap is allowed, False otherwise
  */
-__override_proto int pd_check_data_swap(int port,
-				enum pd_data_role data_role);
+__override_proto int pd_check_data_swap(int port, enum pd_data_role data_role);
 
 /**
  * Check if vconn swap is allowed.
@@ -1551,9 +1831,8 @@ int pd_check_vconn_swap(int port);
  * @param pr_role Our power role
  * @param flags PD flags
  */
-__override_proto void pd_check_pr_role(int port,
-				enum pd_power_role pr_role,
-				int flags);
+__override_proto void pd_check_pr_role(int port, enum pd_power_role pr_role,
+				       int flags);
 
 /**
  * Check current data role for potential data swap
@@ -1562,9 +1841,8 @@ __override_proto void pd_check_pr_role(int port,
  * @param dr_role Our data role
  * @param flags PD flags
  */
-__override_proto void pd_check_dr_role(int port,
-				enum pd_data_role dr_role,
-				int flags);
+__override_proto void pd_check_dr_role(int port, enum pd_data_role dr_role,
+				       int flags);
 
 /**
  * Check for a potential Vconn swap if the port isn't
@@ -1575,17 +1853,6 @@ __override_proto void pd_check_dr_role(int port,
  */
 __override_proto void pd_try_execute_vconn_swap(int port, int flags);
 
-/**
- * Check if we should charge from this device. This is
- * basically a allow-list for chargers that are dual-role,
- * don't set the unconstrained bit, but we should charge
- * from by default.
- *
- * @param vid Port partner Vendor ID
- * @param pid Port partner Product ID
- */
-int pd_charge_from_device(uint16_t vid, uint16_t pid);
-
 /**
  * Execute data swap.
  *
@@ -1593,7 +1860,7 @@ int pd_charge_from_device(uint16_t vid, uint16_t pid);
  * @param data_role new data role
  */
 __override_proto void pd_execute_data_swap(int port,
-				enum pd_data_role data_role);
+					   enum pd_data_role data_role);
 
 /**
  * Get desired dual role state when chipset is suspended.
@@ -1603,6 +1870,14 @@ __override_proto void pd_execute_data_swap(int port,
 
 __override_proto enum pd_dual_role_states pd_get_drp_state_in_suspend(void);
 
+/**
+ * Get desired dual role state when chipset is on.
+ *
+ * Under some circumstances we are not allowed to be source
+ * during chipset on. This function should return appropriate state.
+ */
+__override_proto enum pd_dual_role_states pd_get_drp_state_in_s0(void);
+
 /**
  * Get PD device info used for VDO_CMD_SEND_INFO / VDO_CMD_READ_INFO
  *
@@ -1634,7 +1909,7 @@ __override_proto int pd_custom_vdm(int port, int cnt, uint32_t *payload,
  * @return if >0, number of VDOs to send back.
  */
 int pd_svdm(int port, int cnt, uint32_t *payload, uint32_t **rpayload,
-		uint32_t head, enum tcpm_transmit_type *rtype);
+	    uint32_t head, enum tcpci_msg_type *rtype);
 
 /**
  * Handle Custom VDMs for flashing.
@@ -1655,8 +1930,25 @@ int pd_custom_flash_vdm(int port, int cnt, uint32_t *payload);
  * @param opos object position of mode to exit.
  * @return vdm for UFP to be sent to enter mode or zero if not.
  */
-uint32_t pd_dfp_enter_mode(int port, enum tcpm_transmit_type type,
-		uint16_t svid, int opos);
+uint32_t pd_dfp_enter_mode(int port, enum tcpci_msg_type type, uint16_t svid,
+			   int opos);
+
+/**
+ * Save the Enter mode command data received from the port partner for setting
+ * the retimer
+ *
+ * @param port     USB-C port number
+ * @param payload  payload data.
+ */
+void pd_ufp_set_enter_mode(int port, uint32_t *payload);
+
+/**
+ * Return Enter mode command data received from the port partner
+ *
+ * @param port     USB-C port number
+ * @return enter mode raw value requested to the UFP
+ */
+uint32_t pd_ufp_get_enter_mode(int port);
 
 /**
  *  Get DisplayPort pin mode for DFP to request from UFP's capabilities.
@@ -1676,8 +1968,8 @@ int pd_dfp_dp_get_pin_mode(int port, uint32_t status);
  * @param opos object position of mode to exit.
  * @return 1 if UFP should be sent exit mode VDM.
  */
-int pd_dfp_exit_mode(int port, enum tcpm_transmit_type type, uint16_t svid,
-		int opos);
+int pd_dfp_exit_mode(int port, enum tcpci_msg_type type, uint16_t svid,
+		     int opos);
 
 /**
  * Consume the SVDM attention data
@@ -1695,8 +1987,8 @@ void dfp_consume_attention(int port, uint32_t *payload);
  * @param cnt     number of data objects in payload
  * @param payload payload data.
  */
-void dfp_consume_identity(int port, enum tcpm_transmit_type type, int cnt,
-		uint32_t *payload);
+void dfp_consume_identity(int port, enum tcpci_msg_type type, int cnt,
+			  uint32_t *payload);
 
 /**
  * Consume the SVIDs
@@ -1706,8 +1998,8 @@ void dfp_consume_identity(int port, enum tcpm_transmit_type type, int cnt,
  * @param cnt     number of data objects in payload
  * @param payload payload data.
  */
-void dfp_consume_svids(int port, enum tcpm_transmit_type type, int cnt,
-		uint32_t *payload);
+void dfp_consume_svids(int port, enum tcpci_msg_type type, int cnt,
+		       uint32_t *payload);
 
 /**
  * Consume the alternate modes
@@ -1717,8 +2009,16 @@ void dfp_consume_svids(int port, enum tcpm_transmit_type type, int cnt,
  * @param cnt     number of data objects in payload
  * @param payload payload data.
  */
-void dfp_consume_modes(int port, enum tcpm_transmit_type type, int cnt,
-		uint32_t *payload);
+void dfp_consume_modes(int port, enum tcpci_msg_type type, int cnt,
+		       uint32_t *payload);
+
+/**
+ * Returns true if connected VPD supports Charge Through
+ *
+ * @param port  USB-C port number
+ * @return      TRUE if Charge Through is supported, else FALSE
+ */
+bool is_vpd_ct_supported(int port);
 
 /**
  * Initialize alternate mode discovery info for DFP
@@ -1727,6 +2027,20 @@ void dfp_consume_modes(int port, enum tcpm_transmit_type type, int cnt,
  */
 void pd_dfp_discovery_init(int port);
 
+/**
+ * Initialize active mode info (alternate mode or USB mode) for DFP
+ *
+ * @param port USB-C port number
+ */
+void pd_dfp_mode_init(int port);
+
+/**
+ * Mark all discovery types as failed to prevent any further discovery attempts
+ * until a connection change or DPM request triggers discovery again.
+ * @param port USB-C port number
+ */
+void pd_disable_discovery(int port);
+
 /**
  * Set identity discovery state for this type and port
  *
@@ -1734,7 +2048,7 @@ void pd_dfp_discovery_init(int port);
  * @param type	SOP* type to set
  * @param disc  Discovery state to set (failed or complete)
  */
-void pd_set_identity_discovery(int port, enum tcpm_transmit_type type,
+void pd_set_identity_discovery(int port, enum tcpci_msg_type type,
 			       enum pd_discovery_state disc);
 
 /**
@@ -1745,7 +2059,7 @@ void pd_set_identity_discovery(int port, enum tcpm_transmit_type type,
  * @return      Current discovery state (failed or complete)
  */
 enum pd_discovery_state pd_get_identity_discovery(int port,
-						enum tcpm_transmit_type type);
+						  enum tcpci_msg_type type);
 
 /**
  * Set SVID discovery state for this type and port.
@@ -1754,8 +2068,8 @@ enum pd_discovery_state pd_get_identity_discovery(int port,
  * @param type SOP* type to set
  * @param disc Discovery state to set (failed or complete)
  */
-void pd_set_svids_discovery(int port, enum tcpm_transmit_type type,
-		enum pd_discovery_state disc);
+void pd_set_svids_discovery(int port, enum tcpci_msg_type type,
+			    enum pd_discovery_state disc);
 
 /**
  * Get SVID discovery state for this type and port
@@ -1765,7 +2079,7 @@ void pd_set_svids_discovery(int port, enum tcpm_transmit_type type,
  * @return     Current discovery state (failed or complete)
  */
 enum pd_discovery_state pd_get_svids_discovery(int port,
-		enum tcpm_transmit_type type);
+					       enum tcpci_msg_type type);
 
 /**
  * Set Modes discovery state for this port, SOP* type, and SVID.
@@ -1775,8 +2089,8 @@ enum pd_discovery_state pd_get_svids_discovery(int port,
  * @param svid SVID to set mode discovery state for
  * @param disc Discovery state to set (failed or complete)
  */
-void pd_set_modes_discovery(int port, enum tcpm_transmit_type type,
-		uint16_t svid, enum pd_discovery_state disc);
+void pd_set_modes_discovery(int port, enum tcpci_msg_type type, uint16_t svid,
+			    enum pd_discovery_state disc);
 
 /**
  * Get Modes discovery state for this port and SOP* type. Modes discover is
@@ -1792,7 +2106,7 @@ void pd_set_modes_discovery(int port, enum tcpm_transmit_type type,
  *                                       PD_DISC_FAIL)
  */
 enum pd_discovery_state pd_get_modes_discovery(int port,
-		enum tcpm_transmit_type type);
+					       enum tcpci_msg_type type);
 
 /**
  * Returns the mode vdo count of the specified SVID and sets
@@ -1802,12 +2116,12 @@ enum pd_discovery_state pd_get_modes_discovery(int port,
  * @param type     Transmit type (SOP, SOP') for VDM
  * @param svid     SVID to get
  * @param vdo_out  Discover Mode VDO response to set
- *                 Note: It must be able to fit wihin PDO_MODES VDOs.
+ *                 Note: It must be able to fit within PDO_MAX_OBJECTS VDOs.
  * @return         Mode VDO cnt of specified SVID if is discovered,
  *                 0 otherwise
  */
-int pd_get_mode_vdo_for_svid(int port, enum tcpm_transmit_type type,
-		uint16_t svid, uint32_t *vdo_out);
+int pd_get_mode_vdo_for_svid(int port, enum tcpci_msg_type type, uint16_t svid,
+			     uint32_t *vdo_out);
 
 /**
  * Get a pointer to mode data for the next SVID that needs to be discovered.
@@ -1822,7 +2136,8 @@ int pd_get_mode_vdo_for_svid(int port, enum tcpm_transmit_type type,
  *             mode, if any exist and no modes succeeded in discovery;
  *             NULL, otherwise
  */
-struct svid_mode_data *pd_get_next_mode(int port, enum tcpm_transmit_type type);
+const struct svid_mode_data *pd_get_next_mode(int port,
+					      enum tcpci_msg_type type);
 
 /**
  * Return a pointer to the discover identity response structure for this SOP*
@@ -1833,7 +2148,7 @@ struct svid_mode_data *pd_get_next_mode(int port, enum tcpm_transmit_type type);
  * @return      pointer to response structure, which the caller may not alter
  */
 const union disc_ident_ack *pd_get_identity_response(int port,
-					       enum tcpm_transmit_type type);
+						     enum tcpci_msg_type type);
 
 /**
  * Return the VID of the USB PD accessory connected to a specified port
@@ -1866,7 +2181,7 @@ uint8_t pd_get_product_type(int port);
  * @param type	SOP* type to retrieve
  * @return      SVID count
  */
-int pd_get_svid_count(int port, enum tcpm_transmit_type type);
+int pd_get_svid_count(int port, enum tcpci_msg_type type);
 
 /**
  * Return the SVID of given SVID index of port partner connected
@@ -1877,7 +2192,7 @@ int pd_get_svid_count(int port, enum tcpm_transmit_type type);
  * @param type	   SOP* type to retrieve
  * @return         SVID
  */
-uint16_t pd_get_svid(int port, uint16_t svid_idx, enum tcpm_transmit_type type);
+uint16_t pd_get_svid(int port, uint16_t svid_idx, enum tcpci_msg_type type);
 
 /**
  * Return the pointer to modes of VDO of port partner connected
@@ -1888,8 +2203,8 @@ uint16_t pd_get_svid(int port, uint16_t svid_idx, enum tcpm_transmit_type type);
  * @param type     SOP* type to retrieve
  * @return         Pointer to modes of VDO
  */
-uint32_t *pd_get_mode_vdo(int port, uint16_t svid_idx,
-		enum tcpm_transmit_type type);
+const uint32_t *pd_get_mode_vdo(int port, uint16_t svid_idx,
+				enum tcpci_msg_type type);
 
 /*
  * Looks for a discovered mode VDO for the specified SVID.
@@ -1899,8 +2214,8 @@ uint32_t *pd_get_mode_vdo(int port, uint16_t svid_idx,
  * @param svid SVID to look up
  * @return     Whether a mode was discovered for the SVID
  */
-bool pd_is_mode_discovered_for_svid(int port, enum tcpm_transmit_type type,
-		uint16_t svid);
+bool pd_is_mode_discovered_for_svid(int port, enum tcpci_msg_type type,
+				    uint16_t svid);
 
 /**
  * Return the alternate mode entry and exit data
@@ -1910,8 +2225,8 @@ bool pd_is_mode_discovered_for_svid(int port, enum tcpm_transmit_type type,
  * @param svid  SVID
  * @return      pointer to SVDM mode data
  */
-struct svdm_amode_data *pd_get_amode_data(int port,
-		enum tcpm_transmit_type type, uint16_t svid);
+struct svdm_amode_data *pd_get_amode_data(int port, enum tcpci_msg_type type,
+					  uint16_t svid);
 
 /*
  * Returns cable revision
@@ -1952,7 +2267,7 @@ bool consume_sop_prime_prime_repeat_msg(int port, uint8_t msg_id);
  * @param port USB-C port number
  * @param type Transmit type (SOP, SOP')
  */
-void pd_discovery_access_clear(int port, enum tcpm_transmit_type type);
+void pd_discovery_access_clear(int port, enum tcpci_msg_type type);
 
 /*
  * Validate that this current task is the only one which has retrieved the
@@ -1963,7 +2278,7 @@ void pd_discovery_access_clear(int port, enum tcpm_transmit_type type);
  * @param type Transmit type (SOP, SOP')
  * @return     True - No other tasks have accessed the data
  */
-bool pd_discovery_access_validate(int port, enum tcpm_transmit_type type);
+bool pd_discovery_access_validate(int port, enum tcpci_msg_type type);
 
 /*
  * Returns the pointer to PD alternate mode discovery results
@@ -1979,8 +2294,19 @@ bool pd_discovery_access_validate(int port, enum tcpm_transmit_type type);
  * @param type Transmit type (SOP, SOP') for discovered information
  * @return     pointer to PD alternate mode discovery results
  */
-struct pd_discovery *pd_get_am_discovery(int port,
-		enum tcpm_transmit_type type);
+struct pd_discovery *
+pd_get_am_discovery_and_notify_access(int port, enum tcpci_msg_type type);
+
+/*
+ * Returns the constant pointer to PD alternate mode discovery results
+ * Note: Caller function is expected to only read the discovery results.
+ *
+ * @param port USB-C port number
+ * @param type Transmit type (SOP, SOP') for discovered information
+ * @return     pointer to PD alternate mode discovery results
+ */
+const struct pd_discovery *pd_get_am_discovery(int port,
+					       enum tcpci_msg_type type);
 
 /*
  * Returns the pointer to PD active alternate modes.
@@ -1990,16 +2316,32 @@ struct pd_discovery *pd_get_am_discovery(int port,
  * @param type Transmit type (SOP, SOP', SOP'') for active modes
  * @return     Pointer to PD active alternate modes.
  */
-struct partner_active_modes *pd_get_partner_active_modes(int port,
-		enum tcpm_transmit_type type);
+struct partner_active_modes *
+pd_get_partner_active_modes(int port, enum tcpci_msg_type type);
 
 /*
- * Returns True if cable supports USB2 connection
+ * Sets the current object position for DP alt-mode
+ * Note: opos == 0 means the mode is not active
  *
- * @param port  USB-C port number
- * @return      True is usb2_supported, false otherwise
+ * @param port USB-C port number
+ * @param opos Object position for DP alternate mode
  */
-bool is_usb2_cable_support(int port);
+void pd_ufp_set_dp_opos(int port, int opos);
+
+/*
+ * Gets the current object position for DP alt-mode
+ *
+ * @param port USB-C port number
+ * @return Alt-DP object position value for the given port
+ */
+int pd_ufp_get_dp_opos(int port);
+
+/**
+ * Notify hpd->pd converter that display is configured
+ *
+ * @param port     USB-C port number
+ */
+void pd_ufp_enable_hpd_send(int port);
 
 /*
  * Checks if Cable speed is Gen2 or better
@@ -2115,7 +2457,7 @@ enum tbt_compat_rounded_support get_tbt_rounded_support(int port);
  * @return      Discover Mode VDO for Intel SVID if the Intel mode VDO is
  *              discovered, 0 otherwise
  */
-uint32_t pd_get_tbt_mode_vdo(int port, enum tcpm_transmit_type type);
+uint32_t pd_get_tbt_mode_vdo(int port, enum tcpci_msg_type type);
 
 /**
  * Sets the Mux state to Thunderbolt-Compatible mode
@@ -2124,20 +2466,12 @@ uint32_t pd_get_tbt_mode_vdo(int port, enum tcpm_transmit_type type);
  */
 void set_tbt_compat_mode_ready(int port);
 
-/**
- * Checks if the attached cable supports superspeed
- *
- * @param port	USB-C port number
- * @return      True if cable is superspeed, false otherwise
- */
-bool is_tbt_cable_superspeed(int port);
-
 /**
  * Returns Thunderbolt-compatible cable speed according to the port if,
  * port supports lesser speed than the cable
  *
  * @param port USB-C port number
- * @return thunderbolt-cable cable speed
+ * @return Thunderbolt cable speed
  */
 enum tbt_compat_cable_speed get_tbt_cable_speed(int port);
 
@@ -2150,11 +2484,10 @@ enum tbt_compat_cable_speed get_tbt_cable_speed(int port);
  * @param payload   payload data
  * @return          Number of object filled
  */
-int enter_tbt_compat_mode(int port, enum tcpm_transmit_type sop,
-			uint32_t *payload);
+int enter_tbt_compat_mode(int port, enum tcpci_msg_type sop, uint32_t *payload);
 
 /**
- * Return maximum allowed speed for Thunderbolt-compatible mode
+ * Return maximum speed supported by the port to enter into Thunderbolt mode
  *
  * NOTE: Chromebooks require that all USB-C ports support the same features,
  * so the maximum speed returned by this function should be set to the lowest
@@ -2174,6 +2507,20 @@ int enter_tbt_compat_mode(int port, enum tcpm_transmit_type sop,
  */
 __override_proto enum tbt_compat_cable_speed board_get_max_tbt_speed(int port);
 
+/**
+ * Set what this board should be replying to TBT EnterMode requests with, when
+ * it is configured as the UFP (VDM Responder).
+ *
+ * @param port USB-C port number
+ * @param reply AP-selected reply to the TBT EnterMode request
+ * @return EC_RES_SUCCESS if board supports this configuration setting
+ *	   EC_RES_INVALID_PARAM if board supports this feature, but not this
+ *	   option
+ *	   EC_RES_UNAVAILABLE if board does not support this feature
+ */
+__override_proto enum ec_status
+board_set_tbt_ufp_reply(int port, enum typec_tbt_ufp_reply reply);
+
 /**
  * Return true if the board's port supports TBT or USB4
  *
@@ -2279,8 +2626,8 @@ void pd_dpm_request(int port, enum pd_dpm_request req);
  *                must be 1 - 7 inclusive.
  * @return        True if the setup was successful
  */
-bool pd_setup_vdm_request(int port, enum tcpm_transmit_type tx_type,
-		uint32_t *vdm, uint32_t vdo_cnt);
+bool pd_setup_vdm_request(int port, enum tcpci_msg_type tx_type, uint32_t *vdm,
+			  uint32_t vdo_cnt);
 
 /* Power Data Objects for the source and the sink */
 __override_proto extern const uint32_t pd_src_pdo[];
@@ -2290,6 +2637,15 @@ extern const int pd_src_pdo_max_cnt;
 extern const uint32_t pd_snk_pdo[];
 extern const int pd_snk_pdo_cnt;
 
+/**
+ * TEST ONLY: Set PD_CONTROL command to enabled on this port
+ *
+ * @param port USB-C port number
+ */
+#ifdef TEST_BUILD
+void pd_control_port_enable(int port);
+#endif
+
 /**
  * Request that a host event be sent to notify the AP of a PD power event.
  *
@@ -2299,10 +2655,12 @@ extern const int pd_snk_pdo_cnt;
  *
  * @param mask host event mask.
  */
-#if defined(HAS_TASK_HOSTCMD) && !defined(TEST_BUILD)
+#if defined(CONFIG_USB_PD_HOST_CMD) && !defined(CONFIG_USB_PD_TCPM_STUB)
 void pd_send_host_event(int mask);
 #else
-static inline void pd_send_host_event(int mask) { }
+static inline void pd_send_host_event(int mask)
+{
+}
 #endif
 
 /**
@@ -2313,7 +2671,7 @@ static inline void pd_send_host_event(int mask) { }
  * @param svid USB standard or vendor id
  * @return object position of mode chosen in alternate mode otherwise zero.
  */
-int pd_alt_mode(int port, enum tcpm_transmit_type type, uint16_t svid);
+int pd_alt_mode(int port, enum tcpci_msg_type type, uint16_t svid);
 
 /**
  * Send hpd over USB PD.
@@ -2377,7 +2735,6 @@ int pd_write_preamble(int port);
  */
 int pd_write_sym(int port, int bit_off, uint32_t val10);
 
-
 /**
  * Ensure that we have an edge after EOP and we end up at level 0,
  * also fill the last byte.
@@ -2477,6 +2834,16 @@ int pd_rx_started(int port);
  */
 void pd_set_suspend(int port, int suspend);
 
+/**
+ * Request Error Recovery
+ *
+ * Note that Error Recovery will happen on the next cycle of the port's PD task
+ * and may not have started yet at the time of the function return.
+ *
+ * @param port USB-C port number
+ */
+void pd_set_error_recovery(int port);
+
 /**
  * Resume the PD task for a port after a period of time has elapsed.
  * @param port USB-C port number
@@ -2504,6 +2871,11 @@ void pd_rx_enable_monitoring(int port);
 /* stop listening to the CC wire during transmissions */
 void pd_rx_disable_monitoring(int port);
 
+/**
+ * interrupt handler
+ */
+void pd_rx_handler(void);
+
 /* get time since last RX edge interrupt */
 uint64_t get_time_since_last_edge(int port);
 
@@ -2595,6 +2967,14 @@ enum tcpc_cc_polarity pd_get_polarity(int port);
  */
 uint32_t pd_get_events(int port);
 
+/**
+ * Notify the AP of an event on the given port number
+ *
+ * @param port USB-C port number
+ * @param event_mask bitmask of events to set (PD_STATUS_EVENT_* bitmask)
+ */
+void pd_notify_event(int port, uint32_t event_mask);
+
 /**
  * Clear selected port events
  *
@@ -2603,6 +2983,33 @@ uint32_t pd_get_events(int port);
  */
 void pd_clear_events(int port, uint32_t clear_mask);
 
+/*
+ * Requests a VDM REQ message be sent. It is assumed that this message may be
+ * coming from a task outside the PD task.
+ *
+ * @param port USB-C port number
+ * @param *data pointer to the VDM Attention message
+ * @param vdo_count number of VDOs (must be 1 or 2)
+ * @param tx_type partner type to transmit
+ * @return EC_RES_SUCCESS if a VDM message is scheduled.
+ *         EC_RES_BUSY if a message is already pending
+ *         EC_RES_INVALID_PARAM if the parameters given are invalid
+ */
+enum ec_status pd_request_vdm(int port, const uint32_t *data, int vdo_count,
+			      enum tcpci_msg_type tx_type);
+
+/*
+ * Requests that the port enter the specified mode. A successful result just
+ * means that the request was received, not that the mode has been entered yet.
+ *
+ * @param port USB-C port number
+ * @param mode The mode to enter
+ * @return EC_RES_SUCCESS if the request was made
+ *         EC_RES_INVALID_PARAM for an invalid port or mode;
+ *         EC_RES_BUSY if another mode entry request is already in progress
+ */
+enum ec_status pd_request_enter_mode(int port, enum typec_mode mode);
+
 /**
  * Get port partner data swap capable status
  *
@@ -2682,27 +3089,29 @@ void pd_prepare_reset(void);
 void pd_set_new_power_request(int port);
 
 /**
- * Return true if partner port is a DTS or TS capable of entering debug
- * mode (eg. is presenting Rp/Rp or Rd/Rd).
+ * Return true if partner port is known to be PD capable.
  *
  * @param port USB-C port number
+ * @return true if PD capable else false
  */
-int pd_ts_dts_plugged(int port);
+bool pd_capable(int port);
 
 /**
- * Return true if partner port is known to be PD capable.
+ * Return true if we transition through Unattached.SNK, but we're still waiting
+ * to receive source caps from the partner. This indicates that the PD
+ * capabilities are not yet known.
  *
  * @param port USB-C port number
- * @return true if PD capable else false
+ * @return true if partner is SRC, but PD capability not known
  */
-bool pd_capable(int port);
+bool pd_waiting_on_partner_src_caps(int port);
 
 /**
  * Returns the source caps list
  *
  * @param port USB-C port number
  */
-const uint32_t * const pd_get_src_caps(int port);
+const uint32_t *const pd_get_src_caps(int port);
 
 /**
  * Returns the number of source caps
@@ -2721,6 +3130,34 @@ uint8_t pd_get_src_cap_cnt(int port);
  */
 void pd_set_src_caps(int port, int cnt, uint32_t *src_caps);
 
+/**
+ * Returns the sink caps list
+ *
+ * @param port USB-C port number
+ */
+const uint32_t *const pd_get_snk_caps(int port);
+
+/**
+ * Returns the number of sink caps
+ *
+ * @param port USB-C port number
+ */
+uint8_t pd_get_snk_cap_cnt(int port);
+
+/**
+ * Returns requested voltage
+ *
+ * @param port USB-C port number
+ */
+uint32_t pd_get_requested_voltage(int port);
+
+/**
+ * Returns requested current
+ *
+ * @param port USB-C port number
+ */
+uint32_t pd_get_requested_current(int port);
+
 /**
  * Return true if partner port is capable of communication over USB data
  * lines.
@@ -2729,6 +3166,14 @@ void pd_set_src_caps(int port, int cnt, uint32_t *src_caps);
  */
 bool pd_get_partner_usb_comm_capable(int port);
 
+/**
+ * Gets the port partner's RMDO from the PE state.
+ *
+ * @param port USB-C port number
+ * @return port partner's Revision Message Data Object (RMDO).
+ */
+struct rmdo pd_get_partner_rmdo(int port);
+
 /**
  * Return true if PD is in disconnect state
  *
@@ -2779,6 +3224,7 @@ __override_proto int board_pd_set_frs_enable(int port, int enable);
  */
 __overridable void board_frs_handler(int port);
 
+#ifdef CONFIG_USB_PD_DP_MODE
 /**
  * Get current DisplayPort pin mode on the specified port.
  *
@@ -2786,6 +3232,12 @@ __overridable void board_frs_handler(int port);
  * @return MODE_DP_PIN_[A-E] if used else 0
  */
 __override_proto uint8_t get_dp_pin_mode(int port);
+#else
+static inline uint8_t get_dp_pin_mode(int port)
+{
+	return 0;
+}
+#endif /* CONFIG_USB_PD_DP_MODE */
 
 /**
  * Get board specific usb pd port count
@@ -2795,42 +3247,53 @@ __override_proto uint8_t get_dp_pin_mode(int port);
  */
 __override_proto uint8_t board_get_usb_pd_port_count(void);
 
-
 /**
- * Resets external PD chips including TCPCs and MCUs.
+ * Return true if specified PD port is present. This is similar to
+ * checking CONFIG_USB_PD_PORT_MAX_COUNT but handles sparse numbering.
  *
- * Boards must provide this when PDCMD (PD MCUs case) or PD INT (TCPC case)
- * tasks are present.
+ * @param port USB-C port number
+ *
+ * @return true if port is present.
  */
-void board_reset_pd_mcu(void);
+__override_proto bool board_is_usb_pd_port_present(int port);
 
 /**
- * Return true if specified PD port is debug accessory.
+ * Return true if specified PD port is DTS (Debug and Test System
+ * capable).
  *
  * @param port USB-C port number
+ *
+ * @return true if port is DTS capable.
  */
-bool pd_is_debug_acc(int port);
+__override_proto bool board_is_dts_port(int port);
 
 /**
- * Sets the polarity of the port
+ * Process PD-related alerts for a chip which is sharing the TCPC interrupt line
  *
  * @param port USB-C port number
- * @param polarity 0 for CC1, else 1 for CC2
  */
-void pd_set_polarity(int port, enum tcpc_cc_polarity polarity);
+__override_proto void board_process_pd_alert(int port);
+
+/**
+ * Resets external PD chips including TCPCs and MCUs.
+ *
+ * Boards must provide this when PDCMD (PD MCUs case) or PD INT (TCPC case)
+ * tasks are present.
+ */
+void board_reset_pd_mcu(void);
 
 /*
  * Notify the AP that we have entered into DisplayPort Alternate Mode.  This
  * sets a DP_ALT_MODE_ENTERED MKBP event which may wake the AP.
  */
-void pd_notify_dp_alt_mode_entry(void);
+__override_proto void pd_notify_dp_alt_mode_entry(int port);
 
 /*
  * Determines the PD state of the port partner according to Table 4-10 in USB PD
  * specification.
  */
-enum pd_cc_states pd_get_cc_state(
-	enum tcpc_cc_voltage_status cc1, enum tcpc_cc_voltage_status cc2);
+enum pd_cc_states pd_get_cc_state(enum tcpc_cc_voltage_status cc1,
+				  enum tcpc_cc_voltage_status cc2);
 
 /*
  * Optional, get the board-specific SRC DTS polarity.
@@ -2853,8 +3316,8 @@ __override_proto uint8_t board_get_src_dts_polarity(int port);
  * @param data type-defined information
  * @param payload pointer to the optional payload (0..16 bytes)
  */
-void pd_log_event(uint8_t type, uint8_t size_port,
-		  uint16_t data, void *payload);
+void pd_log_event(uint8_t type, uint8_t size_port, uint16_t data,
+		  void *payload);
 
 /**
  * Retrieve one logged event and prepare a VDM with it.
@@ -2865,10 +3328,15 @@ void pd_log_event(uint8_t type, uint8_t size_port,
  * @return number of 32-bit words in the VDM payload.
  */
 int pd_vdm_get_log_entry(uint32_t *payload);
-#else  /* CONFIG_USB_PD_LOGGING */
-static inline void pd_log_event(uint8_t type, uint8_t size_port,
-				uint16_t data, void *payload) {}
-static inline int pd_vdm_get_log_entry(uint32_t *payload) { return 0; }
+#else /* CONFIG_USB_PD_LOGGING */
+static inline void pd_log_event(uint8_t type, uint8_t size_port, uint16_t data,
+				void *payload)
+{
+}
+static inline int pd_vdm_get_log_entry(uint32_t *payload)
+{
+	return 0;
+}
 #endif /* CONFIG_USB_PD_LOGGING */
 
 /**
@@ -2971,6 +3439,14 @@ __override_proto int svdm_dp_attention(int port, uint32_t *payload);
  */
 __override_proto void svdm_exit_dp_mode(int port);
 
+/**
+ * Get the DP mode that's desired on this port
+ *
+ * @param  port The PD port number
+ * @return USB_PD_MUX_DOCK or USB_PD_MUX_DP_ENABLED
+ */
+uint8_t svdm_dp_get_mux_mode(int port);
+
 /* Google Firmware Update Alternate Mode */
 /**
  * Enter Google Firmware Update (GFU) Mode.
@@ -3071,12 +3547,6 @@ __override_proto int svdm_tbt_compat_attention(int port, uint32_t *payload);
 
 __override_proto enum ec_pd_port_location board_get_pd_port_location(int port);
 
-/**
- * Can be called whenever VBUS presence changes.  The default implementation
- * does nothing, but a board may override it.
- */
-__override_proto void board_vbus_present_change(void);
-
 /****************************************************************************
  * TCPC CC/Rp Management
  */
@@ -3090,6 +3560,14 @@ __override_proto void board_vbus_present_change(void);
  */
 void typec_select_src_current_limit_rp(int port, enum tcpc_rp_value rp);
 
+/**
+ * Called to get a port's default current limit Rp.
+ *
+ * @param port The PD port number
+ * @return rp   Rp is the Current Limit to advertise
+ */
+__override_proto int typec_get_default_current_limit_rp(int port);
+
 /**
  * Called to cache Source Collision Rp
  * A call to typec_update_cc will actually update the hardware to reflect the
@@ -3107,6 +3585,17 @@ void typec_select_src_collision_rp(int port, enum tcpc_rp_value rp);
  * @return 0 on success else failure
  */
 int typec_update_cc(int port);
+
+/**
+ * Defines the New power state indicator bits in the Power State Change
+ * field of the Status Data Block (SDB) in USB PD Revision 3.1 and above.
+ *
+ * @param pd_sdb_power_state enum defining the New Power State field of the SDB
+ * @return pd_sdb_power_indicator enum for the SDB
+ */
+__override_proto enum pd_sdb_power_indicator
+board_get_pd_sdb_power_indicator(enum pd_sdb_power_state power_state);
+
 /****************************************************************************/
 
-#endif  /* __CROS_EC_USB_PD_H */
+#endif /* __CROS_EC_USB_PD_H */
diff --git a/include/usb_pd_ap_vdm_control.h b/include/usb_pd_ap_vdm_control.h
new file mode 100644
index 0000000000..7185ec08b5
--- /dev/null
+++ b/include/usb_pd_ap_vdm_control.h
@@ -0,0 +1,82 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * AP VDM Control functions
+ * Note: Stubs of APIs are implemented for linking if feature is not enabled
+ */
+
+#ifndef __CROS_EC_USB_AP_VDM_CONTROL_H
+#define __CROS_EC_USB_AP_VDM_CONTROL_H
+
+#include "ec_commands.h"
+#include "usb_pd_tcpm.h"
+
+#ifdef CONFIG_USB_PD_VDM_AP_CONTROL
+/*
+ * Informs the AP VDM module of a received Attention message.  Note: all
+ * Attention messages are assumed to be SOP since cables are disallowed from
+ * sending this type of VDM.
+ *
+ * @param[in] port		USB-C port number
+ * @param[in] length		Number of objects filled in
+ * @param[in] buf		Buffer containing received VDM (header and VDO)
+ */
+void ap_vdm_attention_enqueue(int port, int length, uint32_t *buf);
+
+/*
+ * Initializes AP VDM state for a port.
+ *
+ * @param port USB-C port number
+ */
+void ap_vdm_init(int port);
+
+/*
+ * Informs the AP VDM module that a VDM ACK was received.
+ *
+ * @param port      USB-C port number
+ * @param type      Transmit type (SOP, SOP') for received ACK
+ * @param vdo_count The number of VDOs in VDM; must be at least 1
+ * @param vdm       The VDM payload of the ACK
+ */
+void ap_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count,
+		  uint32_t *vdm);
+
+/*
+ * Informs the AP VDM module that a VDM NAK was received. Also applies when a
+ * VDM request received a Not Supported response or timed out waiting for a
+ * response.
+ *
+ * @param port		USB-C port number
+ * @param type		Transmit type (SOP, SOP') for request
+ * @param svid		The SVID of the request
+ * @param vdm_cmd	The VDM command of the request
+ * @param vdm_header    VDM header reply (0 if a NAK wasn't actually received)
+ */
+void ap_vdm_naked(int port, enum tcpci_msg_type type, uint16_t svid,
+		  uint8_t vdm_cmd, uint32_t vdm_header);
+
+#else /* else for CONFIG_USB_PD_VDM_AP_CONTROL */
+static inline void ap_vdm_attention_enqueue(int port, int length, uint32_t *buf)
+{
+}
+
+static inline void ap_vdm_init(int port)
+{
+}
+
+static inline void ap_vdm_acked(int port, enum tcpci_msg_type type,
+				int vdo_count, uint32_t *vdm)
+{
+}
+
+static inline void ap_vdm_naked(int port, enum tcpci_msg_type type,
+				uint16_t svid, uint8_t vdm_cmd,
+				uint32_t vdm_header)
+{
+}
+
+#endif /* CONFIG_USB_PD_VDM_AP_CONTROL */
+#endif /* __CROS_EC_USB_AP_VDM_H */
diff --git a/include/usb_pd_dp_hpd_gpio.h b/include/usb_pd_dp_hpd_gpio.h
new file mode 100644
index 0000000000..fa25cade4e
--- /dev/null
+++ b/include/usb_pd_dp_hpd_gpio.h
@@ -0,0 +1,33 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * HPD GPIO control module
+ * Note: Stubs of APIs are implemented for linking if feature is not enabled
+ */
+
+#ifndef __CROS_EC_USB_DP_HPD_GPIO_H
+#define __CROS_EC_USB_DP_HPD_GPIO_H
+
+#ifdef CONFIG_USB_PD_DP_HPD_GPIO
+/*
+ * Informs the AP of HPD activity through at GPIO, including toggling on IRQ if
+ * necessary.
+ *
+ * @param[in] port		USB-C port number
+ * @param[in] level		Level of the HPD line
+ * @param[in] irq		IRQ pulse to the AP needed
+ * @return			EC error code
+ */
+enum ec_error_list dp_hpd_gpio_set(int port, bool level, bool irq);
+
+#else /* else for CONFIG_USB_PD_DP_HPD_GPIO */
+static inline enum ec_error_list dp_hpd_gpio_set(int port, bool level, bool irq)
+{
+	return EC_SUCCESS;
+}
+
+#endif /* CONFIG_USB_PD_DP_HPD_GPIO */
+#endif /* __CROS_EC_USB_DP_HPD_GPIO_H */
diff --git a/include/usb_pd_dp_ufp.h b/include/usb_pd_dp_ufp.h
new file mode 100644
index 0000000000..663f4f1d83
--- /dev/null
+++ b/include/usb_pd_dp_ufp.h
@@ -0,0 +1,35 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Common functions for UFP-D devices.
+ */
+
+#ifndef __CROS_EC_USB_PD_DP_UFP_H
+#define __CROS_EC_USB_PD_DP_UFP_H
+
+struct hpd_to_pd_config_t {
+	int port;
+	enum gpio_signal signal;
+};
+
+extern const struct hpd_to_pd_config_t hpd_config;
+/*
+ * Function used to handle hpd gpio interrupts.
+ *
+ * @param signal -> gpio signal associated with hpd interrupt
+ */
+void usb_pd_hpd_edge_event(int signal);
+
+/*
+ * Function used to enable/disable the hpd->dp attention protocol converter
+ *    - called with enable when enter mode command is processed.
+ *    - called with disable when exit mode command is processed.
+ *
+ * @param enable -> converter on/off
+ */
+void usb_pd_hpd_converter_enable(int enable);
+
+#endif /* __CROS_EC_USB_PD_DP_UFP_H */
diff --git a/include/usb_pd_dpm.h b/include/usb_pd_dpm.h
deleted file mode 100644
index 2948fd3fbd..0000000000
--- a/include/usb_pd_dpm.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Device Policy Manager implementation
- * Refer to USB PD 3.0 spec, version 2.0, sections 8.2 and 8.3
- */
-
-#ifndef __CROS_EC_USB_DPM_H
-#define __CROS_EC_USB_DPM_H
-
-/*
- * Initializes DPM state for a port.
- *
- * @param port USB-C port number
- */
-void dpm_init(int port);
-
-/*
- * Informs the DPM that the mode entry sequence (including appropriate
- * configuration) is done for a port.
- *
- * @param port USB-C port number
- */
-void dpm_set_mode_entry_done(int port);
-
-/*
- * Informs the DPM that Exit Mode request is received
- *
- * @param port USB-C port number
- */
-void dpm_set_mode_exit_request(int port);
-
-/*
- * Informs the DPM that a VDM ACK was received.
- *
- * @param port      USB-C port number
- * @param type      Transmit type (SOP, SOP') for received ACK
- * @param vdo_count The number of VDOs in vdm; must be at least 1
- * @param vdm       The VDM payload of the ACK
- */
-void dpm_vdm_acked(int port, enum tcpm_transmit_type type, int vdo_count,
-		uint32_t *vdm);
-
-/*
- * Informs the DPM that a VDM NAK was received. Also applies when a VDM request
- * received a Not Supported response or timed out waiting for a response.
- *
- * @param port    USB-C port number
- * @param type    Transmit type (SOP, SOP') for request
- * @param svid    The SVID of the request
- * @param vdm_cmd The VDM command of the request
- */
-void dpm_vdm_naked(int port, enum tcpm_transmit_type type, uint16_t svid,
-		uint8_t vdm_cmd);
-
-/*
- * Drives the Policy Engine through entry/exit mode process
- *
- * @param port USB-C port number
- */
-void dpm_run(int port);
-
-#endif  /* __CROS_EC_USB_DPM_H */
diff --git a/include/usb_pd_dpm_sm.h b/include/usb_pd_dpm_sm.h
new file mode 100644
index 0000000000..cb275d65e6
--- /dev/null
+++ b/include/usb_pd_dpm_sm.h
@@ -0,0 +1,237 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Device Policy Manager implementation
+ * Refer to USB PD 3.0 spec, version 2.0, sections 8.2 and 8.3
+ */
+
+/*
+ * TODO(b/272518464): Work around coreboot GCC preprocessor bug.
+ * #line marks the *next* line, so it is off by one.
+ */
+#line 16
+
+#ifndef __CROS_EC_USB_DPM_H
+#define __CROS_EC_USB_DPM_H
+
+#include "ec_commands.h"
+#include "usb_pd_tcpm.h"
+#include "usb_sm.h"
+
+/**
+ * Sets the debug level for the DPM layer
+ *
+ * @param level debug level
+ */
+void dpm_set_debug_level(enum debug_level level);
+
+/*
+ * Initializes DPM state for a port.
+ *
+ * @param port USB-C port number
+ */
+void dpm_init(int port);
+
+/**
+ * Runs the Device Policy Manager State Machine
+ *
+ * @param port USB-C port number
+ * @param evt  system event, ie: PD_EVENT_RX
+ * @param en   0 to disable the machine, 1 to enable the machine
+ */
+void dpm_run(int port, int evt, int en);
+
+/*
+ * Informs the DPM that a mode exit is complete.
+ *
+ * @param port USB-C port number
+ */
+void dpm_mode_exit_complete(int port);
+
+/*
+ * Informs the DPM that Exit Mode request is received
+ *
+ * @param port USB-C port number
+ */
+void dpm_set_mode_exit_request(int port);
+
+/* Informs the DPM that the PE has performed a Data Reset (or at least
+ * determined that the port partner doesn't support one).
+ *
+ * @param port USB-C port number
+ */
+void dpm_data_reset_complete(int port);
+
+/*
+ * Informs the DPM that PE layer is in ready state so that data role can be
+ * checked and DPM can know to exit the idle state.
+ *
+ * @param port USB-C port number
+ */
+void dpm_set_pe_ready(int port, bool enable);
+
+/*
+ * Informs the DPM that a VDM ACK was received.
+ *
+ * @param port      USB-C port number
+ * @param type      Transmit type (SOP, SOP') for received ACK
+ * @param vdo_count The number of VDOs in vdm; must be at least 1
+ * @param vdm       The VDM payload of the ACK
+ */
+void dpm_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count,
+		   uint32_t *vdm);
+
+/*
+ * Informs the DPM that a VDM NAK was received. Also applies when a VDM request
+ * received a Not Supported response or timed out waiting for a response.
+ *
+ * @param port		USB-C port number
+ * @param type		Transmit type (SOP, SOP') for request
+ * @param svid		The SVID of the request
+ * @param vdm_cmd	The VDM command of the request
+ * @param vdm_header    VDM header reply (0 if a NAK wasn't actually received)
+ */
+void dpm_vdm_naked(int port, enum tcpci_msg_type type, uint16_t svid,
+		   uint8_t vdm_cmd, uint32_t vdm_header);
+
+/*
+ * Clears the VDM request in progress bit for this port
+ *
+ * @param[in]  port		USB-C port number
+ */
+void dpm_clear_vdm_request(int port);
+
+/*
+ * Checks the VDM request in progress bit for this port
+ *
+ * @param[in]  port		USB-C port number
+ * @return			true if VDM REQ is set
+ */
+bool dpm_check_vdm_request(int port);
+
+/*
+ * Informs the DPM of a received Attention message.  Note: all Attention
+ * messages are assumed to be SOP since cables are disallowed from sending
+ * this type of VDM.
+ *
+ * @param[in] port		USB-C port number
+ * @param[in] vdo_objects	Number of objects filled in
+ * @param[in] buf		Buffer containing received VDM (header and VDO)
+ */
+void dpm_notify_attention(int port, size_t vdo_objects, uint32_t *buf);
+
+/*
+ * Determines the current allocation for the connection, past the basic
+ * CONFIG_USB_PD_PULLUP value set by the TC (generally 1.5 A)
+ *
+ * @param port		USB-C port number
+ * @param vsafe5v_pdo	Copy of first Sink_Capability PDO, which should
+ *			represent the vSafe5V fixed PDO
+ */
+void dpm_evaluate_sink_fixed_pdo(int port, uint32_t vsafe5v_pdo);
+
+/*
+ * Registers port as a non-PD sink, so that can be taken into account when
+ * allocating current.
+ *
+ * @param port		USB-C port number
+ */
+void dpm_add_non_pd_sink(int port);
+
+/*
+ * Evaluates the request from port partner
+ *
+ * @param port		USB-C port number
+ * @param rdo		Request from port partner
+ */
+void dpm_evaluate_request_rdo(int port, uint32_t rdo);
+
+/*
+ * Remove this port as a sink, and reallocate maximum current as needed.
+ *
+ * @param port		USB-C port number
+ */
+void dpm_remove_sink(int port);
+
+/*
+ * Remove this port as a source, and reallocate reserved FRS maximum current
+ * as needed.
+ *
+ * @param port		USB-C port number
+ */
+void dpm_remove_source(int port);
+
+/*
+ * Return the appropriate Source Capability PDO to offer this port
+ *
+ * @param src_pdo	Will point to appropriate PDO to offer
+ * @param port		USB-C port number
+ * @return		Number of PDOs
+ */
+int dpm_get_source_pdo(const uint32_t **src_pdo, const int port);
+
+/*
+ * Report offered source current for this port
+ *
+ * @param port		USB-C port number
+ * @return		Current offered, in mA
+ */
+int dpm_get_source_current(const int port);
+
+/*
+ * Report we've been asked to enter BIST Shared Test Mode
+ *
+ * @param port		USB-C port number
+ */
+void dpm_bist_shared_mode_enter(int port);
+
+/*
+ * Report we've been asked to exit BIST Shared Test Mode
+ *
+ * @param port		USB-C port number
+ */
+void dpm_bist_shared_mode_exit(int port);
+
+/*
+ * Set BIST Shared Test Mode
+ */
+enum ec_status pd_set_bist_share_mode(uint8_t enable);
+
+/*
+ * Get BIST Shared Test Mode status
+ */
+uint8_t pd_get_bist_share_mode(void);
+/*
+ * Build SOP Status Data Block (SDB)
+ *
+ * @param port		USB-C port number
+ * @param *msg		pointer to pd message
+ * @param *len		pointer to uint32_t holding length of SDB
+ */
+int dpm_get_status_msg(int port, uint8_t *msg, uint32_t *len);
+
+/*
+ * DPM function to handle a received alert message
+ *
+ * @param port		USB-C port number
+ * @param ado		Alert Data Object (ado) received from partner
+ */
+void dpm_handle_alert(int port, uint32_t ado);
+
+/* Enum for modules to describe to the DPM their setup status */
+enum dpm_msg_setup_status {
+	MSG_SETUP_SUCCESS,
+	MSG_SETUP_ERROR,
+	MSG_SETUP_UNSUPPORTED,
+	MSG_SETUP_MUX_WAIT,
+};
+
+/* Enum to describe current state of connected USB PD buttons */
+enum dpm_pd_button_state {
+	DPM_PD_BUTTON_IDLE,
+	DPM_PD_BUTTON_PRESSED,
+};
+#endif /* __CROS_EC_USB_DPM_H */
diff --git a/include/usb_pd_flags.h b/include/usb_pd_flags.h
new file mode 100644
index 0000000000..70e80379a6
--- /dev/null
+++ b/include/usb_pd_flags.h
@@ -0,0 +1,89 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Contains USB PD flags definition and accessors
+ */
+#ifndef __CROS_EC_USB_PD_FLAGS_H
+#define __CROS_EC_USB_PD_FLAGS_H
+
+#include "stdint.h"
+
+/*
+ * USB PD VBUS detect (0-2)
+ */
+enum usb_pd_vbus_detect {
+	USB_PD_VBUS_DETECT_UNKNOWN = 0,
+	USB_PD_VBUS_DETECT_NONE = 1,
+	USB_PD_VBUS_DETECT_TCPC = 2,
+	USB_PD_VBUS_DETECT_GPIO = 3,
+	USB_PD_VBUS_DETECT_PPC = 4,
+	USB_PD_VBUS_DETECT_CHARGER = 5
+};
+
+/*
+ * USB PD DISCHARGE (Bits 3-4)
+ */
+enum usb_pd_discharge {
+	USB_PD_DISCHARGE_NONE = 0,
+	USB_PD_DISCHARGE_TCPC = 1,
+	USB_PD_DISCHARGE_GPIO = 2,
+	USB_PD_DISCHARGE_PPC = 3
+};
+
+/*
+ * USB PD Charger OTG (Bit 5)
+ */
+enum usb_pd_charger_otg {
+	USB_PD_CHARGER_OTG_DISABLED = 0,
+	USB_PD_CHARGER_OTG_ENABLED = 1
+};
+
+union usb_pd_runtime_flags {
+	struct {
+		enum usb_pd_vbus_detect vbus_detect : 3;
+		enum usb_pd_discharge discharge : 2;
+		enum usb_pd_charger_otg charger_otg : 1;
+		uint32_t reserved : 26;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Set VBUS detect type from USB_PD_FLAGS.
+ */
+void set_usb_pd_vbus_detect(enum usb_pd_vbus_detect vbus_detect);
+
+/**
+ * Get VBUS detect type from USB_PD_FLAGS.
+ *
+ * @return the VBUS detect type.
+ */
+enum usb_pd_vbus_detect get_usb_pd_vbus_detect(void);
+
+/**
+ * Set USB PD discharge type from USB_PD_FLAGS.
+ */
+void set_usb_pd_discharge(enum usb_pd_discharge discharge);
+
+/**
+ * Get USB PD discharge type from USB_PD_FLAGS.
+ *
+ * @return the USB PD discharge type.
+ */
+enum usb_pd_discharge get_usb_pd_discharge(void);
+
+/**
+ * Set USB PD charger OTG from USB_PD_FLAGS.
+ */
+void set_usb_pd_charger_otg(enum usb_pd_charger_otg charger_otg);
+
+/**
+ * Get USB PD charger OTG from USB_PD_FLAGS.
+ *
+ * @return the USB PD charger OTG.
+ */
+enum usb_pd_charger_otg get_usb_pd_charger_otg(void);
+#endif /* __CROS_EC_USB_PD_FLAGS_H */
diff --git a/include/usb_pd_pdo.h b/include/usb_pd_pdo.h
new file mode 100644
index 0000000000..9e75555b63
--- /dev/null
+++ b/include/usb_pd_pdo.h
@@ -0,0 +1,19 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_COMMON_USB_PD_PDO_H
+#define __CROS_EC_COMMON_USB_PD_PDO_H
+
+/* ---------------- Power Data Objects (PDOs) ----------------- */
+#ifndef CONFIG_USB_PD_CUSTOM_PDO
+extern const uint32_t pd_src_pdo[1];
+extern const int pd_src_pdo_cnt;
+extern const uint32_t pd_src_pdo_max[1];
+extern const int pd_src_pdo_max_cnt;
+extern const uint32_t pd_snk_pdo[3];
+extern const int pd_snk_pdo_cnt;
+#endif /* CONFIG_USB_PD_CUSTOM_PDO */
+
+#endif /* __CROS_EC_COMMON_USB_PD_PDO_H */
diff --git a/include/usb_pd_policy.h b/include/usb_pd_policy.h
new file mode 100644
index 0000000000..a5675ded4e
--- /dev/null
+++ b/include/usb_pd_policy.h
@@ -0,0 +1,41 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* USBC PD Default Policies  */
+
+#ifndef __CROS_EC_USB_PD_POLICY_H
+#define __CROS_EC_USB_PD_POLICY_H
+
+#include "usb_pe_sm.h"
+
+/**
+ * Port Discovery DR Swap Policy
+ *
+ * Different boards can implement its own DR swap policy during a port discovery
+ * by implementing this function.
+ *
+ * @param port USB-C port number
+ * @param dr   current port data role
+ * @param dr_swap_flag   Data Role Swap Flag bit
+ * @param return True if state machine should perform a DR swap, elsf False
+ */
+__override_proto bool port_discovery_dr_swap_policy(int port,
+						    enum pd_data_role dr,
+						    bool dr_swap_flag);
+
+/**
+ * Port Discovery VCONN Swap Policy
+ *
+ * Different boards can implement its own VCONN swap policy during a port
+ * discovery by implementing this function.
+ *
+ * @param port USB-C port number
+ * @param vconn_swap_to_on_flag   Vconn Swap to On Flag bit
+ * @param return True if state machine should perform a VCONN swap, elsf False
+ */
+__override_proto bool port_discovery_vconn_swap_policy(int port,
+						       bool vconn_swap_flag);
+
+#endif /* __CROS_EC_USB_PD_POLICY_H */
diff --git a/include/usb_pd_tbt.h b/include/usb_pd_tbt.h
index 6aa4f52922..315fccb619 100644
--- a/include/usb_pd_tbt.h
+++ b/include/usb_pd_tbt.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -106,7 +106,7 @@ enum vendor_specific_support {
 
 /* TBT Alternate Mode */
 #define TBT_ALTERNATE_MODE 0x0001
-#define PD_VDO_RESP_MODE_INTEL_TBT(x)	(((x) & 0xff) == TBT_ALTERNATE_MODE)
+#define PD_VDO_RESP_MODE_INTEL_TBT(x) (((x)&0xff) == TBT_ALTERNATE_MODE)
 
 union tbt_mode_resp_device {
 	struct {
@@ -124,7 +124,17 @@ union tbt_mode_resp_device {
 /*
  * Table F-11 TBT3 Cable Discover Mode VDO Responses
  * -------------------------------------------------------------
- * <31:24> : Reserved
+ * <31:26> : Reserved
+ * <25>    : Active Passive
+ *           Errata: Reserved B25 has been changed to Active passive bit
+ *           Refer USB Type-C ENGINEERING CHANGE NOTICE (ECN)
+ *           "USB Type-C ECN Thunderbolt 3 Compatibility Updates.pdf"
+ *           with Title: Thunderbolt 3 Compatibility Updates
+ *           for the document fix published by USB-IF.
+ *           0b = Passive cable
+ *           1b = Active cable
+ *           NOTE: This change is only applicable to rev 3 cables
+ * <24>    : Reserved
  * <23>    : Active Cable Plug Link Training
  *           0 = Active with bi-directional LSRX1 communication or when Passive
  *           1 = Active with uni-directional LSRX1 communication
@@ -148,6 +158,11 @@ union tbt_mode_resp_device {
  * <15:0>  : TBT Alternate Mode
  *           0x0001 = TBT Mode
  */
+enum tbt_active_passive_cable {
+	TBT_CABLE_PASSIVE,
+	TBT_CABLE_ACTIVE,
+};
+
 enum tbt_compat_cable_speed {
 	TBT_SS_RES_0,
 	TBT_SS_U31_GEN1,
@@ -189,7 +204,9 @@ union tbt_mode_resp_cable {
 		enum tbt_cable_type tbt_cable : 1;
 		enum usb_retimer_type retimer_type : 1;
 		enum link_lsrx_comm lsrx_comm : 1;
-		uint8_t reserved0 : 8;
+		uint8_t reserved1 : 1;
+		enum tbt_active_passive_cable tbt_active_passive : 1;
+		uint8_t reserved0 : 6;
 	};
 	uint32_t raw_value;
 };
@@ -203,25 +220,37 @@ union tbt_mode_resp_cable {
  * Table F-13 TBT3 Device Enter Mode Command SOP
  * -------------------------------------------------------------
  * <31>    : Vendor specific B1
- *           0 = Not supported
- *           1 = Supported
+ *           0b = Not supported
+ *           1b = Supported
  * <30>    : Vendor specific B0
- *           0 = Not supported
- *           1 = Supported
+ *           0b = Not supported
+ *           1b = Supported
  * <29:27> : 000b Reserved
  * <26>    : Intel specific B0
- *           0 = Not supported
- *           1 = Supported
- * <25>    : 0b Reserved
- * <24>    : Active_Passive
- *           0 = Passive cable
- *           1 = Active cable
+ *           0b = Not supported
+ *           1b = Supported
+ * <25>    : Active_Passive
+ *           Errata: Active_Passive bit is changed to B25
+ *           Refer USB Type-C ENGINEERING CHANGE NOTICE (ECN)
+ *           "USB Type-C ECN Thunderbolt 3 Compatibility Updates.pdf"
+ *           with Title: Thunderbolt 3 Compatibility Updates
+ *           for the document fix published by USB-IF.
+ *           0b = Passive cable
+ *           1b = Active cable
+ * <24>    : TBT adapter
+ *           Errata: B24 represents Thunderbolt Adapter type
+ *           Refer USB Type-C ENGINEERING CHANGE NOTICE (ECN)
+ *           "USB Type-C ECN Thunderbolt 3 Compatibility Updates.pdf"
+ *           with Title: Thunderbolt 3 Compatibility Updates
+ *           for the document fix published by USB-IF.
+ *           0b = TBT3 Adapter
+ *           1b = TBT2 Legacy Adapter
  * <23>    : Active Cable Link Training
- *           0 = Active with bi-directional LSRX1 communication or when Passive
- *           1 = Active with uni-directional LSRX1 communication
+ *           0b = Active with bi-directional LSRX1 communication or when Passive
+ *           1b = Active with uni-directional LSRX1 communication
  * <22>    : Re-timer
- *           0 = Not re-timer
- *           1 = Re-timer
+ *           0b = Not re-timer
+ *           1b = Re-timer
  * <21>    : Cable Type
  *           0b = Non-Optical
  *           1b = Optical
@@ -252,8 +281,8 @@ union tbt_dev_mode_enter_cmd {
 		enum tbt_cable_type tbt_cable : 1;
 		enum usb_retimer_type retimer_type : 1;
 		enum link_lsrx_comm lsrx_comm : 1;
+		enum tbt_adapter_type tbt_adapter : 1;
 		enum tbt_enter_cable_type cable : 1;
-		uint8_t reserved0 : 1;
 		enum vendor_specific_support intel_spec_b0 : 1;
 		uint8_t reserved1 : 3;
 		enum vendor_specific_support vendor_spec_b0 : 1;
diff --git a/include/usb_pd_tcpc.h b/include/usb_pd_tcpc.h
index 4ac22d4d86..7af0a570e4 100644
--- a/include/usb_pd_tcpc.h
+++ b/include/usb_pd_tcpc.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,21 +8,22 @@
 #ifndef __CROS_EC_USB_PD_TCPC_H
 #define __CROS_EC_USB_PD_TCPC_H
 
-#include <stdint.h>
 #include "usb_pd_tcpm.h"
 
-/* If we are a TCPC but do not a TCPM, then we implement the slave TCPCI */
+#include <stdint.h>
+
+/* If we are a TCPC but not a TCPM, then we implement the peripheral TCPCI */
 #if defined(CONFIG_USB_PD_TCPC) && !defined(CONFIG_USB_PD_TCPM_STUB)
-#define TCPCI_I2C_SLAVE
+#define TCPCI_I2C_PERIPHERAL
 #endif
 
-#ifdef TCPCI_I2C_SLAVE
+#ifdef TCPCI_I2C_PERIPHERAL
 /* Convert TCPC address to type-C port number */
-#define TCPC_ADDR_TO_PORT(addr) ((addr) \
-			- I2C_GET_ADDR(CONFIG_TCPC_I2C_BASE_ADDR_FLAGS))
+#define TCPC_ADDR_TO_PORT(addr) \
+	((addr)-I2C_STRIP_FLAGS(CONFIG_TCPC_I2C_BASE_ADDR_FLAGS))
 /* Check if the i2c address belongs to TCPC */
-#define ADDR_IS_TCPC(addr)      (((addr) & 0x7E) \
-			== I2C_GET_ADDR(CONFIG_TCPC_I2C_BASE_ADDR_FLAGS))
+#define ADDR_IS_TCPC(addr) \
+	(((addr)&0x7E) == I2C_STRIP_FLAGS(CONFIG_TCPC_I2C_BASE_ADDR_FLAGS))
 #endif
 
 /**
@@ -44,12 +45,15 @@ void tcpc_i2c_process(int read, int port, int len, uint8_t *payload,
 void pd_vbus_evt_p0(enum gpio_signal signal);
 void pd_vbus_evt_p1(enum gpio_signal signal);
 
-/* Methods for TCPCI slaves (e.g. zinger) to get/set their internal state */
+/*
+ * Methods for TCPCI peripherals (e.g. zinger) to get/set their internal
+ * state
+ */
 int tcpc_alert_status(int port, int *alert);
 int tcpc_alert_status_clear(int port, uint16_t mask);
 int tcpc_alert_mask_set(int port, uint16_t mask);
 int tcpc_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2);
+		enum tcpc_cc_voltage_status *cc2);
 int tcpc_select_rp_value(int port, int rp);
 int tcpc_set_cc(int port, int pull);
 int tcpc_set_polarity(int port, int polarity);
@@ -58,7 +62,7 @@ int tcpc_set_vconn(int port, int enable);
 int tcpc_set_msg_header(int port, int power_role, int data_role);
 int tcpc_set_rx_enable(int port, int enable);
 int tcpc_get_message(int port, uint32_t *payload, int *head);
-int tcpc_transmit(int port, enum tcpm_transmit_type type, uint16_t header,
+int tcpc_transmit(int port, enum tcpci_msg_type type, uint16_t header,
 		  const uint32_t *data);
 int rx_buf_is_empty(int port);
 void rx_buf_clear(int port);
diff --git a/include/usb_pd_tcpm.h b/include/usb_pd_tcpm.h
index b4cd7654a7..3860ca5d4f 100644
--- a/include/usb_pd_tcpm.h
+++ b/include/usb_pd_tcpm.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,12 +8,15 @@
 #ifndef __CROS_EC_USB_PD_TCPM_H
 #define __CROS_EC_USB_PD_TCPM_H
 
-#include <stdbool.h>
+#include "common.h"
+#include "compiler.h"
 #include "ec_commands.h"
 #include "i2c.h"
 
+#include <stdbool.h>
+
 /* Time to wait for TCPC to complete transmit */
-#define PD_T_TCPC_TX_TIMEOUT  (100*MSEC)
+#define PD_T_TCPC_TX_TIMEOUT (100 * MSEC)
 
 enum usbpd_cc_pin {
 	USBPD_CC_PIN_1,
@@ -23,8 +26,8 @@ enum usbpd_cc_pin {
 /* Detected resistor values of port partner */
 enum tcpc_cc_voltage_status {
 	TYPEC_CC_VOLT_OPEN = 0,
-	TYPEC_CC_VOLT_RA = 1,	  /* Port partner is applying Ra */
-	TYPEC_CC_VOLT_RD = 2,	  /* Port partner is applying Rd */
+	TYPEC_CC_VOLT_RA = 1, /* Port partner is applying Ra */
+	TYPEC_CC_VOLT_RD = 2, /* Port partner is applying Rd */
 	TYPEC_CC_VOLT_RP_DEF = 5, /* Port partner is applying Rp (0.5A) */
 	TYPEC_CC_VOLT_RP_1_5 = 6, /* Port partner is applying Rp (1.5A) */
 	TYPEC_CC_VOLT_RP_3_0 = 7, /* Port partner is applying Rp (3.0A) */
@@ -40,43 +43,58 @@ enum tcpc_cc_pull {
 };
 
 /* Pull-up values we apply as a SRC to advertise different current limits */
-enum tcpc_rp_value {
+FORWARD_DECLARE_ENUM(tcpc_rp_value){
 	TYPEC_RP_USB = 0,
 	TYPEC_RP_1A5 = 1,
 	TYPEC_RP_3A0 = 2,
 	TYPEC_RP_RESERVED = 3,
 };
 
+/* DRP (dual-role-power) setting */
+enum tcpc_drp {
+	TYPEC_NO_DRP = 0,
+	TYPEC_DRP = 1,
+};
+
 /**
  * Returns whether the polarity without the DTS extension
  */
-static inline enum tcpc_cc_polarity polarity_rm_dts(
-	enum tcpc_cc_polarity polarity)
+static inline enum tcpc_cc_polarity
+polarity_rm_dts(enum tcpc_cc_polarity polarity)
 {
 	BUILD_ASSERT(POLARITY_COUNT == 4);
-	return polarity & BIT(0);
+	return (enum tcpc_cc_polarity)(polarity & BIT(0));
 }
 
-enum tcpm_transmit_type {
-	TCPC_TX_SOP = 0,
-	TCPC_TX_SOP_PRIME = 1,
-	TCPC_TX_SOP_PRIME_PRIME = 2,
-	TCPC_TX_SOP_DEBUG_PRIME = 3,
-	TCPC_TX_SOP_DEBUG_PRIME_PRIME = 4,
-	TCPC_TX_HARD_RESET = 5,
-	TCPC_TX_CABLE_RESET = 6,
-	TCPC_TX_BIST_MODE_2 = 7,
-	TCPC_TX_INVALID = 0xf,
+/*
+ * Types of PD data that can be sent or received. The values match the TCPCI bit
+ * field values TRANSMIT[Transmit SOP* Message] (TCPCI r2.0 v1.2, table 4-38)
+ * and RX_BUF_FRAME_TYPE[Received SOP* message] (table 4-37). Note that Hard
+ * Reset, Cable Reset, and BIST Carrier Mode 2 are not really messages.
+ */
+enum tcpci_msg_type {
+	TCPCI_MSG_SOP = 0,
+	TCPCI_MSG_SOP_PRIME = 1,
+	TCPCI_MSG_SOP_PRIME_PRIME = 2,
+	TCPCI_MSG_SOP_DEBUG_PRIME = 3,
+	TCPCI_MSG_SOP_DEBUG_PRIME_PRIME = 4,
+	/* Only a valid register setting for TRANSMIT */
+	TCPCI_MSG_TX_HARD_RESET = 5,
+	TCPCI_MSG_CABLE_RESET = 6,
+	/* Only a valid register setting for TRANSMIT */
+	TCPCI_MSG_TX_BIST_MODE_2 = 7,
+	TCPCI_MSG_INVALID = 0xf,
 };
 
 /* Number of valid Transmit Types */
-#define NUM_SOP_STAR_TYPES (TCPC_TX_SOP_DEBUG_PRIME_PRIME + 1)
+#define NUM_SOP_STAR_TYPES (TCPCI_MSG_SOP_DEBUG_PRIME_PRIME + 1)
 
 enum tcpc_transmit_complete {
 	TCPC_TX_UNSET = -1,
-	TCPC_TX_COMPLETE_SUCCESS =   0,
-	TCPC_TX_COMPLETE_DISCARDED = 1,
-	TCPC_TX_COMPLETE_FAILED =    2,
+	TCPC_TX_WAIT = 0,
+	TCPC_TX_COMPLETE_SUCCESS = 1,
+	TCPC_TX_COMPLETE_DISCARDED = 2,
+	TCPC_TX_COMPLETE_FAILED = 3,
 };
 
 /*
@@ -85,9 +103,9 @@ enum tcpc_transmit_complete {
  * Return true on Vbus check if Vbus is...
  */
 enum vbus_level {
-	VBUS_SAFE0V,	/* less than vSafe0V max */
-	VBUS_PRESENT,	/* at least vSafe5V min */
-	VBUS_REMOVED,	/* less than vSinkDisconnect max */
+	VBUS_SAFE0V, /* less than vSafe0V max */
+	VBUS_PRESENT, /* at least vSafe5V min */
+	VBUS_REMOVED, /* less than vSinkDisconnect max */
 };
 
 /**
@@ -103,16 +121,27 @@ static inline int cc_is_rp(enum tcpc_cc_voltage_status cc)
  * Returns true if both CC lines are completely open.
  */
 static inline int cc_is_open(enum tcpc_cc_voltage_status cc1,
-	enum tcpc_cc_voltage_status cc2)
+			     enum tcpc_cc_voltage_status cc2)
 {
 	return cc1 == TYPEC_CC_VOLT_OPEN && cc2 == TYPEC_CC_VOLT_OPEN;
 }
 
+/**
+ * Returns true if we detect a powered cable without sink attached.
+ * This is a pair of Ra and Open.
+ */
+static inline int cc_is_pwred_cbl_without_snk(enum tcpc_cc_voltage_status cc1,
+					      enum tcpc_cc_voltage_status cc2)
+{
+	return (cc1 == TYPEC_CC_VOLT_RA && cc2 == TYPEC_CC_VOLT_OPEN) ||
+	       (cc1 == TYPEC_CC_VOLT_OPEN && cc2 == TYPEC_CC_VOLT_RA);
+}
+
 /**
  * Returns true if we detect the port partner is a snk debug accessory.
  */
 static inline int cc_is_snk_dbg_acc(enum tcpc_cc_voltage_status cc1,
-	enum tcpc_cc_voltage_status cc2)
+				    enum tcpc_cc_voltage_status cc2)
 {
 	return cc1 == TYPEC_CC_VOLT_RD && cc2 == TYPEC_CC_VOLT_RD;
 }
@@ -121,7 +150,7 @@ static inline int cc_is_snk_dbg_acc(enum tcpc_cc_voltage_status cc1,
  * Returns true if we detect the port partner is a src debug accessory.
  */
 static inline int cc_is_src_dbg_acc(enum tcpc_cc_voltage_status cc1,
-	enum tcpc_cc_voltage_status cc2)
+				    enum tcpc_cc_voltage_status cc2)
 {
 	return cc_is_rp(cc1) && cc_is_rp(cc2);
 }
@@ -130,7 +159,7 @@ static inline int cc_is_src_dbg_acc(enum tcpc_cc_voltage_status cc1,
  * Returns true if the port partner is an audio accessory.
  */
 static inline int cc_is_audio_acc(enum tcpc_cc_voltage_status cc1,
-	enum tcpc_cc_voltage_status cc2)
+				  enum tcpc_cc_voltage_status cc2)
 {
 	return cc1 == TYPEC_CC_VOLT_RA && cc2 == TYPEC_CC_VOLT_RA;
 }
@@ -139,7 +168,7 @@ static inline int cc_is_audio_acc(enum tcpc_cc_voltage_status cc1,
  * Returns true if the port partner is presenting at least one Rd
  */
 static inline int cc_is_at_least_one_rd(enum tcpc_cc_voltage_status cc1,
-	enum tcpc_cc_voltage_status cc2)
+					enum tcpc_cc_voltage_status cc2)
 {
 	return cc1 == TYPEC_CC_VOLT_RD || cc2 == TYPEC_CC_VOLT_RD;
 }
@@ -148,7 +177,7 @@ static inline int cc_is_at_least_one_rd(enum tcpc_cc_voltage_status cc1,
  * Returns true if the port partner is presenting Rd on only one CC line.
  */
 static inline int cc_is_only_one_rd(enum tcpc_cc_voltage_status cc1,
-	enum tcpc_cc_voltage_status cc2)
+				    enum tcpc_cc_voltage_status cc2)
 {
 	return cc_is_at_least_one_rd(cc1, cc2) && cc1 != cc2;
 }
@@ -183,7 +212,7 @@ struct tcpm_drv {
 	 * @return EC_SUCCESS or error
 	 */
 	int (*get_cc)(int port, enum tcpc_cc_voltage_status *cc1,
-		enum tcpc_cc_voltage_status *cc2);
+		      enum tcpc_cc_voltage_status *cc2);
 
 	/**
 	 * Check VBUS level
@@ -195,6 +224,16 @@ struct tcpm_drv {
 	 */
 	bool (*check_vbus_level)(int port, enum vbus_level level);
 
+	/**
+	 * Get VBUS voltage
+	 *
+	 * @param port Type-C port number
+	 * @param vbus read VBUS voltage in mV
+	 *
+	 * @return EC_SUCCESS or error
+	 */
+	int (*get_vbus_voltage)(int port, int *vbus);
+
 	/**
 	 * Set the value of the CC pull-up used when we are a source.
 	 *
@@ -206,7 +245,8 @@ struct tcpm_drv {
 	int (*select_rp_value)(int port, int rp);
 
 	/**
-	 * Set the CC pull resistor. This sets our role as either source or sink.
+	 * Set the CC pull resistor. This sets our role as either source or
+	 * sink.
 	 *
 	 * @param port Type-C port number
 	 * @param pull One of enum tcpc_cc_pull
@@ -227,15 +267,17 @@ struct tcpm_drv {
 
 #ifdef CONFIG_USB_PD_DECODE_SOP
 	/**
-	 * Disable receive of SOP' and SOP'' messages. This is provided
+	 * Control receive of SOP' and SOP'' messages. This is provided
 	 * separately from set_vconn so that we can preemptively disable
-	 * receipt of SOP' messages during a VCONN swap.
+	 * receipt of SOP' messages during a VCONN swap, or disable during spans
+	 * when port partners may erroneously be sending cable messages.
 	 *
 	 * @param port Type-C port number
+	 * @param enable Enable SOP' and SOP'' messages
 	 *
 	 * @return EC_SUCCESS or error
 	 */
-	int (*sop_prime_disable)(int port);
+	int (*sop_prime_enable)(int port, bool enable);
 #endif
 
 	/**
@@ -291,8 +333,8 @@ struct tcpm_drv {
 	 *
 	 * @return EC_SUCCESS or error
 	 */
-	int (*transmit)(int port, enum tcpm_transmit_type type, uint16_t header,
-					const uint32_t *data);
+	int (*transmit)(int port, enum tcpci_msg_type type, uint16_t header,
+			const uint32_t *data);
 
 	/**
 	 * TCPC is asserting alert
@@ -315,8 +357,7 @@ struct tcpm_drv {
 	 * @param port Type-C port number
 	 * @param enable Auto Discharge enable or disable
 	 */
-	void (*tcpc_enable_auto_discharge_disconnect)(int port,
-						      int enable);
+	void (*tcpc_enable_auto_discharge_disconnect)(int port, int enable);
 
 	/**
 	 * Manual control of TCPC DebugAccessory enable
@@ -326,6 +367,14 @@ struct tcpm_drv {
 	 */
 	int (*debug_accessory)(int port, bool enable);
 
+	/**
+	 * Break debug connection, if TCPC requires specific commands to be run
+	 * in order to correctly exit a debug connection.
+	 *
+	 * @param port Type-C port number
+	 */
+	int (*debug_detach)(int port);
+
 #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
 	/**
 	 * Enable TCPC auto DRP toggling.
@@ -347,19 +396,17 @@ struct tcpm_drv {
 	 * @return EC_SUCCESS or error
 	 */
 	int (*get_chip_info)(int port, int live,
-			struct ec_response_pd_chip_info_v1 *info);
+			     struct ec_response_pd_chip_info_v1 *info);
 
-#ifdef CONFIG_USBC_PPC
 	/**
 	 * Request current sinking state of the TCPC
 	 * NOTE: this is most useful for PPCs that can not tell on their own
 	 *
 	 * @param port Type-C port number
-	 * @param is_sinking true for sinking, false for not
 	 *
-	 * @return EC_SUCCESS, EC_ERROR_UNIMPLEMENTED or error
+	 * @return true if sinking else false
 	 */
-	int (*get_snk_ctrl)(int port, bool *sinking);
+	bool (*get_snk_ctrl)(int port);
 
 	/**
 	 * Send SinkVBUS or DisableSinkVBUS command
@@ -376,11 +423,10 @@ struct tcpm_drv {
 	 * NOTE: this is most useful for PPCs that can not tell on their own
 	 *
 	 * @param port Type-C port number
-	 * @param is_sourcing true for sourcing, false for not
 	 *
-	 * @return EC_SUCCESS, EC_ERROR_UNIMPLEMENTED or error
+	 * @return true if sourcing else false
 	 */
-	int (*get_src_ctrl)(int port, bool *sourcing);
+	bool (*get_src_ctrl)(int port);
 
 	/**
 	 * Send SourceVBUS or DisableSourceVBUS command
@@ -391,7 +437,25 @@ struct tcpm_drv {
 	 * @return EC_SUCCESS or error
 	 */
 	int (*set_src_ctrl)(int port, int enable);
-#endif
+
+#ifdef CONFIG_USB_PD_TCPM_SBU
+	/*
+	 * Enable SBU lines.
+	 *
+	 * Some PD chips have integrated port protection for SBU lines and the
+	 * switches to enable the SBU lines coming out of the PD chips are
+	 * controlled by vendor specific registers. Hence, this function has to
+	 * be written in vendor specific driver code and the board specific
+	 * tcpc_config[] has to initialize the function with vendor specific
+	 * function at board level.
+	 *
+	 * @param port Type-C port number
+	 * @enable true for enable, false for disable
+	 *
+	 * @return EC_SUCCESS or error
+	 */
+	int (*set_sbu)(int port, bool enable);
+#endif /* CONFIG_USB_PD_TCPM_SBU */
 
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
 	/**
@@ -405,9 +469,19 @@ struct tcpm_drv {
 	 * @return EC_SUCCESS or error
 	 */
 	int (*enter_low_power_mode)(int port);
+
+	/**
+	 * Starts I2C wake sequence for TCPC
+	 *
+	 * NOTE: Do no use tcpc_(read|write) style helper methods in this
+	 * function. You must use i2c_(read|write) directly.
+	 *
+	 * @param port Type-C port number
+	 */
+	void (*wake_low_power_mode)(int port);
 #endif
 
-#ifdef CONFIG_USB_PD_FRS_TCPC
+#ifdef CONFIG_USB_PD_FRS
 	/**
 	 * Enable/Disable TCPC FRS detection
 	 *
@@ -416,7 +490,7 @@ struct tcpm_drv {
 	 *
 	 * @return EC_SUCCESS or error
 	 */
-	 int (*set_frs_enable)(int port, int enable);
+	int (*set_frs_enable)(int port, int enable);
 #endif
 
 	/**
@@ -427,18 +501,60 @@ struct tcpm_drv {
 	 *
 	 * @return EC_SUCCESS or error
 	 */
-	 int (*handle_fault)(int port, int fault);
+	int (*handle_fault)(int port, int fault);
+
+	/**
+	 * Re-initialize registers during hard reset
+	 *
+	 * NOTE: If the function alters the alert mask and power status mask,
+	 * this indicates the chip does not require a full TCPCI re-init after
+	 * a hard reset.
+	 *
+	 * @param port Type-C port number
+	 *
+	 * @return EC_SUCCESS or error
+	 */
+	int (*hard_reset_reinit)(int port);
 
+	/**
+	 * Controls BIST Test Mode (or analogous functionality) in the TCPC and
+	 * associated behavior changes. Disables message Rx alerts while the
+	 * port is in Test Mode.
+	 *
+	 * @param port   USB-C port number
+	 * @param enable true to enter BIST Test Mode; false to exit
+	 * @return EC_SUCCESS or error code
+	 */
+	enum ec_error_list (*set_bist_test_mode)(int port, bool enable);
+
+	/**
+	 * Get control of BIST Test Mode (or analogous functionality) in the
+	 * TCPC.
+	 *
+	 * @param port   USB-C port number
+	 * @param enable true for BIST Test Mode enabled; false for error
+	 *               occurred or BIST Test Mode disabled.
+	 * @return EC_SUCCESS or error code
+	 */
+	enum ec_error_list (*get_bist_test_mode)(int port, bool *enable);
 #ifdef CONFIG_CMD_TCPC_DUMP
 	/**
 	 * Dump TCPC registers
 	 *
 	 * @param port Type-C port number
 	 */
-	 void (*dump_registers)(int port);
+	void (*dump_registers)(int port);
 #endif /* defined(CONFIG_CMD_TCPC_DUMP) */
+
+	int (*reset_bist_type_2)(int port);
 };
 
+#ifdef CONFIG_ZEPHYR
+
+#include "dt-bindings/usb_pd_tcpm.h"
+
+#else /* !CONFIG_ZEPHYR */
+
 /*
  * Macros for tcpc_config_t flags field.
  *
@@ -448,27 +564,36 @@ struct tcpm_drv {
  * Bit 3 --> Set to 1 if TCPC is using TCPCI Revision 2.0
  * Bit 4 --> Set to 1 if TCPC is using TCPCI Revision 2.0 but does not support
  *           the vSafe0V bit in the EXTENDED_STATUS_REGISTER
+ * Bit 5 --> Set to 1 to prevent TCPC setting debug accessory control
+ * Bit 6 --> TCPC controls VCONN (even when CONFIG_USB_PD_TCPC_VCONN is off)
+ * Bit 7 --> TCPC controls FRS (even when CONFIG_USB_PD_FRS_TCPC is off)
+ * Bit 8 --> TCPC enable VBUS monitoring
  */
-#define TCPC_FLAGS_ALERT_ACTIVE_HIGH	BIT(0)
-#define TCPC_FLAGS_ALERT_OD		BIT(1)
-#define TCPC_FLAGS_RESET_ACTIVE_HIGH	BIT(2)
-#define TCPC_FLAGS_TCPCI_REV2_0		BIT(3)
-#define TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V	BIT(4)
+#define TCPC_FLAGS_ALERT_ACTIVE_HIGH BIT(0)
+#define TCPC_FLAGS_ALERT_OD BIT(1)
+#define TCPC_FLAGS_RESET_ACTIVE_HIGH BIT(2)
+#define TCPC_FLAGS_TCPCI_REV2_0 BIT(3)
+#define TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V BIT(4)
+#define TCPC_FLAGS_NO_DEBUG_ACC_CONTROL BIT(5)
+#define TCPC_FLAGS_CONTROL_VCONN BIT(6)
+#define TCPC_FLAGS_CONTROL_FRS BIT(7)
+#define TCPC_FLAGS_VBUS_MONITOR BIT(8)
+
+#endif /* !CONFIG_ZEPHYR */
 
 struct tcpc_config_t {
-	enum ec_bus_type bus_type;	/* enum ec_bus_type */
+	enum ec_bus_type bus_type; /* enum ec_bus_type */
 	union {
 		struct i2c_info_t i2c_info;
 	};
 	const struct tcpm_drv *drv;
 	/* See TCPC_FLAGS_* above */
 	uint32_t flags;
-#ifdef CONFIG_INTEL_VIRTUAL_MUX
-	/*
-	 * 0-3: Corresponding USB2 port number (1 ~ 15)
-	 * 4-7: Corresponding USB3 port number (1 ~ 15)
-	 */
-	uint8_t usb23;
+#ifdef CONFIG_PLATFORM_EC_TCPC_INTERRUPT
+	struct gpio_dt_spec irq_gpio;
+	struct gpio_dt_spec rst_gpio;
+#else
+	enum gpio_signal alert_signal;
 #endif
 };
 
@@ -536,20 +661,11 @@ int board_tcpc_post_init(int port) __attribute__((weak));
  */
 void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled);
 
-/**
- * Get the VBUS voltage from TCPC
- *
- * @param port Type-C port number
- *
- * @return VBUS voltage in mV.
- */
-int tcpc_get_vbus_voltage(int port);
-
 #ifdef CONFIG_CMD_TCPC_DUMP
 struct tcpc_reg_dump_map {
-	uint8_t		addr;
-	uint8_t		size;
-	const char	*name;
+	uint8_t addr;
+	uint8_t size;
+	const char *name;
 };
 
 /**
@@ -569,6 +685,6 @@ void tcpc_dump_std_registers(int port);
  *
  */
 void tcpc_dump_registers(int port, const struct tcpc_reg_dump_map *reg,
-			  int count);
+			 int count);
 #endif
 #endif /* __CROS_EC_USB_PD_TCPM_H */
diff --git a/include/usb_pd_timer.h b/include/usb_pd_timer.h
new file mode 100644
index 0000000000..60ea3b1479
--- /dev/null
+++ b/include/usb_pd_timer.h
@@ -0,0 +1,383 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* USB Power delivery module */
+
+#ifndef __CROS_EC_USB_PD_TIMER_H
+#define __CROS_EC_USB_PD_TIMER_H
+
+#include "atomic.h"
+#include "atomic_bit.h"
+
+#include <stdbool.h>
+
+/*
+ * List of all timers that will be managed by usb_pd_timer
+ */
+enum pd_task_timer {
+	/*
+	 * Timer to check if a USB PD power button press exceeds the long press
+	 * time limit.
+	 */
+	DPM_TIMER_PD_BUTTON_LONG_PRESS,
+
+	/*
+	 * Timer to check if a USB PD power button press exceeds the short press
+	 * time limit.
+	 */
+	DPM_TIMER_PD_BUTTON_SHORT_PRESS,
+
+	/*
+	 * In BIST_TX mode, this timer is used by a UUT to ensure that a
+	 * Continuous BIST Mode (i.e. BIST Carrier Mode) is exited in a timely
+	 * fashion.
+	 *
+	 * In BIST_RX mode, this timer is used to give the port partner time
+	 * to respond.
+	 */
+	PE_TIMER_BIST_CONT_MODE,
+
+	/*
+	 * PD 3.0, version 2.0, section 6.6.18.1: The ChunkingNotSupportedTimer
+	 * is used by a Source or Sink which does not support multi-chunk
+	 * Chunking but has received a Message Chunk. The
+	 * ChunkingNotSupportedTimer Shall be started when the last bit of the
+	 * EOP of a Message Chunk of a multi-chunk Message is received. The
+	 * Policy Engine Shall Not send its Not_Supported Message before the
+	 * ChunkingNotSupportedTimer expires.
+	 */
+	PE_TIMER_CHUNKING_NOT_SUPPORTED,
+
+	/*
+	 * PD 3.0, rev. 3.1, v. 1.2, section 6.6.10.3: The DataResetFailTimer
+	 * Shall be used by the DFP’s Policy Engine to ensure the Data Reset
+	 * process completes within tDataResetFail of the last bit of the
+	 * GoodCRC acknowledging the Accept Message in response to the
+	 * Data_Reset Message.
+	 */
+	PE_TIMER_DATA_RESET_FAIL,
+
+	/*
+	 * This timer is used during an Explicit Contract when discovering
+	 * whether a Port Partner is PD Capable using SOP'.
+	 */
+	PE_TIMER_DISCOVER_IDENTITY,
+
+	/*
+	 * The NoResponseTimer is used by the Policy Engine in a Source
+	 * to determine that its Port Partner is not responding after a
+	 * Hard Reset.
+	 */
+	PE_TIMER_NO_RESPONSE,
+
+	/*
+	 * This timer tracks the time after receiving a Wait message in
+	 * response to a PR_Swap message.
+	 */
+	PE_TIMER_PR_SWAP_WAIT,
+
+	/*
+	 * This timer is used in a Source to ensure that the Sink has had
+	 * sufficient time to process Hard Reset Signaling before turning
+	 * off its power supply to VBUS.
+	 */
+	PE_TIMER_PS_HARD_RESET,
+
+	/*
+	 * This timer combines the PSSourceOffTimer and PSSourceOnTimer timers.
+	 * For PSSourceOffTimer, when this DRP device is currently acting as a
+	 * Sink, this timer times out on a PS_RDY Message during a Power Role
+	 * Swap sequence.
+	 *
+	 * For PSSourceOnTimer, when this DRP device is currently acting as a
+	 * Source that has just stopped sourcing power and is waiting to start
+	 * sinking power to timeout on a PS_RDY Message during a Power Role
+	 * Swap.
+	 */
+	PE_TIMER_PS_SOURCE,
+
+	/*
+	 * This timer is started when a request for a new Capability has been
+	 * accepted and will timeout after PD_T_PS_TRANSITION if a PS_RDY
+	 * Message has not been received.
+	 */
+	PE_TIMER_PS_TRANSITION,
+
+	/*
+	 * This timer is used to ensure that a Message requesting a response
+	 * (e.g. Get_Source_Cap Message) is responded to within a bounded time
+	 * of PD_T_SENDER_RESPONSE.
+	 */
+	PE_TIMER_SENDER_RESPONSE,
+
+	/*
+	 *  6.6.21 EPR Timers of PD R3.1 V1.6
+	 *  This timer is used to ensure the EPR Mode entry process completes
+	 *  within PD_T_ENTER_EPR.
+	 */
+	PE_TIMER_SINK_EPR_ENTER,
+	PE_TIMER_SINK_EPR_KEEP_ALIVE,
+
+	/*
+	 * This timer is used to ensure that the time before the next Sink
+	 * Request Message, after a Wait Message has been received from the
+	 * Source in response to a Sink Request Message.
+	 */
+	PE_TIMER_SINK_REQUEST,
+
+	/*
+	 * Prior to a successful negotiation, a Source Shall use the
+	 * SourceCapabilityTimer to periodically send out a
+	 * Source_Capabilities Message.
+	 */
+	PE_TIMER_SOURCE_CAP,
+
+	/*
+	 * Used to wait for tSrcTransition between sending an Accept for a
+	 * Request or receiving a GoToMin and transitioning the power supply.
+	 * See PD 3.0, table 7-11 and table 7-22 This is not a named timer in
+	 * the spec.
+	 */
+	PE_TIMER_SRC_TRANSITION,
+
+	/*
+	 * This timer is used by the new Source, after a Power Role Swap or
+	 * Fast Role Swap, to ensure that it does not send Source_Capabilities
+	 * Message before the new Sink is ready to receive the
+	 * Source_Capabilities Message.
+	 */
+	PE_TIMER_SWAP_SOURCE_START,
+
+	/* Temporary available timeout timer */
+	PE_TIMER_TIMEOUT,
+
+	/*
+	 * The amount of timer that the DFP shall wait for the UFP to discharge
+	 * VCONN (and send PS_RDY) during Data Reset. See PD 3.0, rev. 3.1, v.
+	 * 1.2, section 6.6.10.1 VCONNDischargeTimer.
+	 */
+	PE_TIMER_VCONN_DISCHARGE,
+
+	/*
+	 * This timer is used during a VCONN Swap.
+	 */
+	PE_TIMER_VCONN_ON,
+
+	/*
+	 * The amount of time that VCONN shall remain off during the cable reset
+	 * portion of a Data Reset. See PD 3.0, rev. 3.1, v. 1.2, section 7.1.15
+	 * VCONN Power Cycle.
+	 */
+	PE_TIMER_VCONN_REAPPLIED,
+
+	/*
+	 * This timer is used by the Initiator’s Policy Engine to ensure that
+	 * a Structured VDM Command request needing a response (e.g. Discover
+	 * Identity Command request) is responded to within a bounded time of
+	 * tVDMSenderResponse.
+	 */
+	PE_TIMER_VDM_RESPONSE,
+
+	/*
+	 * For PD2.0, this timer is used to wait 400ms and add some
+	 * jitter of up to 100ms before sending a message.
+	 * NOTE: This timer is not part of the TypeC/PD spec.
+	 */
+	PE_TIMER_WAIT_AND_ADD_JITTER,
+
+	/* Chunk Sender Response timer */
+	PR_TIMER_CHUNK_SENDER_RESPONSE,
+
+	/* Chunk Sender Request timer */
+	PR_TIMER_CHUNK_SENDER_REQUEST,
+
+	/* Hard Reset Complete timer */
+	PR_TIMER_HARD_RESET_COMPLETE,
+
+	/* Sink TX timer */
+	PR_TIMER_SINK_TX,
+
+	/* timeout to limit waiting on TCPC response (not in spec) */
+	PR_TIMER_TCPC_TX_TIMEOUT,
+
+	/* Time a port shall wait before it can determine it is attached */
+	TC_TIMER_CC_DEBOUNCE,
+
+	/* Time to debounce exit low power mode */
+	TC_TIMER_LOW_POWER_EXIT_TIME,
+
+	/* Time to enter low power mode */
+	TC_TIMER_LOW_POWER_TIME,
+
+	/* Role toggle timer */
+	TC_TIMER_NEXT_ROLE_SWAP,
+
+	/*
+	 * Time a Sink port shall wait before it can determine it is detached
+	 * due to the potential for USB PD signaling on CC as described in
+	 * the state definitions.
+	 */
+	TC_TIMER_PD_DEBOUNCE,
+
+	/* Generic timer */
+	TC_TIMER_TIMEOUT,
+
+	/*
+	 * Time a port shall wait before it can determine it is
+	 * re-attached during the try-wait process.
+	 */
+	TC_TIMER_TRY_WAIT_DEBOUNCE,
+
+	/*
+	 * Time to ignore Vbus absence due to external IC debounce detection
+	 * logic immediately after a power role swap.
+	 */
+	TC_TIMER_VBUS_DEBOUNCE,
+
+	PD_TIMER_COUNT
+};
+
+enum pd_timer_range {
+	DPM_TIMER_RANGE,
+	PE_TIMER_RANGE,
+	PR_TIMER_RANGE,
+	TC_TIMER_RANGE,
+};
+#define DPM_TIMER_START DPM_TIMER_PD_BUTTON_LONG_PRESS
+#define DPM_TIMER_END DPM_TIMER_PD_BUTTON_SHORT_PRESS
+
+#define PE_TIMER_START PE_TIMER_BIST_CONT_MODE
+#define PE_TIMER_END PE_TIMER_WAIT_AND_ADD_JITTER
+
+#define PR_TIMER_START PR_TIMER_CHUNK_SENDER_RESPONSE
+#define PR_TIMER_END PR_TIMER_TCPC_TX_TIMEOUT
+
+#define TC_TIMER_START TC_TIMER_CC_DEBOUNCE
+#define TC_TIMER_END TC_TIMER_VBUS_DEBOUNCE
+
+/*
+ * pd_timer_init
+ * Initialize Power Delivery Timer module
+ *
+ * @param port USB-C port number
+ */
+void pd_timer_init(int port);
+
+/*
+ * pd_timer_enable
+ * Initiate an enabled timer
+ *
+ * @param port USB-C port number
+ * @param timer Requested pd_task_timer
+ * @param expires_us Expiration time relative to "now"
+ */
+void pd_timer_enable(int port, enum pd_task_timer timer, uint32_t expires_us);
+
+/*
+ * pd_timer_disable
+ * Disable a timer
+ *
+ * @param port USB-C port number
+ * @param timer Requested pd_task_timer
+ */
+void pd_timer_disable(int port, enum pd_task_timer timer);
+
+/*
+ * pd_timer_disable_range
+ * Disable all of the timers in a group range
+ *
+ * @param port USB-C port number
+ * @param range Group range to disable
+ */
+void pd_timer_disable_range(int port, enum pd_timer_range range);
+
+/*
+ * pd_timer_is_disabled
+ * Determine if a timer is currently disabled
+ *
+ * @param port USB-C port number
+ * @param timer Requested pd_task_timer
+ * @return True if the timer is disabled, otherwise false
+ */
+bool pd_timer_is_disabled(int port, enum pd_task_timer timer);
+
+/*
+ * pd_timer_is_expired
+ * Determine if a timer is expired
+ *
+ * @param port USB-C port number
+ * @param timer Requested pd_task_timer
+ * @return True if the timer is enabled and expired, otherwise false
+ */
+bool pd_timer_is_expired(int port, enum pd_task_timer timer);
+
+/*
+ * pd_timer_manage_expired
+ * Convert an active/expired timer to be inactive/expired. This will allow
+ * the code to continue to check for expired without having this timer as
+ * part of the pd_timer_next_expiration decision.
+ *
+ * @param port USB-C port number
+ */
+void pd_timer_manage_expired(int port);
+
+/*
+ * pd_timer_next_expiration
+ * Retrieve the next active expiration time
+ *
+ * @param port USB-C port number
+ * @return >= 0 is the number of uSeconds until we should wake up.
+ *	   -1 no pending timeout
+ */
+int pd_timer_next_expiration(int port);
+
+/*
+ * pd_timer_dump
+ * Debug display of the timers for a given port
+ *
+ * @param port USB-C port number
+ */
+void pd_timer_dump(int port);
+
+#ifdef TEST_BUILD
+/*****************************************************************************
+ * TEST_BUILD section
+ *
+ * This is solely for the use of unit testing.  Most of the inner workings
+ * of PD timer are internal static, so they have to be allowed access in
+ * order to unit test the basics of the code.
+ *
+ * If you are interested in the workings of PD timers please refer to
+ * common/usbc/usb_pd_timer.c
+ */
+
+/* exported: number of USB-C ports */
+#define MAX_PD_PORTS CONFIG_USB_PD_PORT_MAX_COUNT
+
+/* PD timers have three possible states: Active, Inactive and Disabled */
+/* exported: timer_active indicates if a timer is currently active */
+extern ATOMIC_DEFINE(timer_active, PD_TIMER_COUNT *MAX_PD_PORTS);
+/* exported: timer_disabled indicates if a timer is currently disabled */
+extern ATOMIC_DEFINE(timer_disabled, PD_TIMER_COUNT *MAX_PD_PORTS);
+
+/* exported: set/clear/check the current timer_active for a timer */
+#define PD_SET_ACTIVE(p, bit) \
+	atomic_set_bit(timer_active, (p)*PD_TIMER_COUNT + (bit))
+#define PD_CLR_ACTIVE(p, bit) \
+	atomic_clear_bit(timer_active, (p)*PD_TIMER_COUNT + (bit))
+#define PD_CHK_ACTIVE(p, bit) \
+	atomic_test_bit(timer_active, (p)*PD_TIMER_COUNT + (bit))
+
+/* exported: set/clear/check the current timer_disabled for a timer */
+#define PD_SET_DISABLED(p, bit) \
+	atomic_set_bit(timer_disabled, (p)*PD_TIMER_COUNT + (bit))
+#define PD_CLR_DISABLED(p, bit) \
+	atomic_clear_bit(timer_disabled, (p)*PD_TIMER_COUNT + (bit))
+#define PD_CHK_DISABLED(p, bit) \
+	atomic_test_bit(timer_disabled, (p)*PD_TIMER_COUNT + (bit))
+
+#endif /* TEST_BUILD */
+
+#endif /* __CROS_EC_USB_PD_TIMER_H */
diff --git a/include/usb_pd_vdo.h b/include/usb_pd_vdo.h
index 2cecec5d84..ed1bc490f1 100644
--- a/include/usb_pd_vdo.h
+++ b/include/usb_pd_vdo.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,10 +19,60 @@
  * ############################################################################
  *
  * Reference: USB Power Delivery Specification Revision 3.0, Version 2.0
+ * Updated to ECN released on Feb 07, 2020
  *
  * ############################################################################
  */
 
+/*****************************************************************************/
+/*
+ * Table 6-29 ID Header VDO
+ * -------------------------------------------------------------
+ * <31>    : USB Communications Capable as USB Host
+ * <30>    : USB Communications Capable as a USB Device
+ * <29:27> : Product Type (UFP):
+ *           000b = Undefined
+ *           001b = PDUSB Hub
+ *           010b = PDUSB Peripheral
+ *           011b = PSD (PD 3.0)
+ *           101b = Alternate Mode Adapter (AMA)
+ *           110b = Vconn-Powered USB Device (VPD, PD 3.0)
+ *           111b = Reserved, shall NOT be used
+ *
+ *           Product Type (Cable Plug):
+ *           000b = Undefined
+ *           001b...010b = Reserved, Shall NOT be used
+ *           011b = Passive Cable
+ *           100b = Active Cable
+ *           101b...111b = Reserved, Shall NOT be used
+ * <26>    : Modal Operation Supported
+ * <25:23> : Product Type (DFP):
+ *           000b = Undefined
+ *           001b = PDUSB Hub
+ *           010b = PDUSB Host
+ *           011b = Power Brick
+ *           100b = Alternate Mode Controller (AMC)
+ *           101b...111b = Reserved, Shall NOT be used
+ * <22:21> : Connector Type
+ *           00b = Reserved for compatibility with legacy systems
+ *           01b = Reserved, Shall Not be used
+ *           10b = USB Type-C Receptacle
+ *           11b = USB Type-C Captive Plug
+ * <20:16> : Reserved
+ * <15:0>  : USB Vendor ID
+ */
+enum connector_type {
+	USB_TYPEC_RECEPTACLE = 2,
+	USB_TYPEC_CAPTIVE_PLUG,
+};
+
+enum idh_ptype_dfp {
+	IDH_PTYPE_DFP_UNDEFINED,
+	IDH_PTYPE_DFP_HUB,
+	IDH_PTYPE_DFP_HOST,
+	IDH_PTYPE_DFP_POWER_BRICK,
+	IDH_PTYPE_DFP_AMC,
+};
 /*****************************************************************************/
 /*
  * Table 6-33 Cert Stat VDO (Note: same as Revision 2.0)
@@ -50,13 +100,21 @@ struct product_vdo {
  * Table 6-35 UFP VDO 1
  * -------------------------------------------------------------
  * <31:29> : UFP VDO version
+ *           Version 1.0 = 000b
+ *           Version 1.1 = 001b
+ *           Values 010b...111b are Reserved and Shall Not be used
  * <28>    : Reserved
  * <27:24> : Device Capability
  *           0001b = USB2.0 Device capable
  *           0010b = USB2.0 Device capable (Billboard only)
  *           0100b = USB3.2 Device capable
  *           1000b = USB4 Device Capable
- * <23:6>  : Reserved
+ * <23:22> : Connector Type
+ *           00b = Reserved, Shall Not be used
+ *           01b = Reserved, Shall Not be used
+ *           10b = USB Type-C Receptacle
+ *           11b = USB Type-C Captive Plug
+ * <21:6>  : Reserved
  * <5:3>   : Alternate Modes
  *           001b = Supports TBT3 alternate mode
  *           010b = Supports Alternate Modes that reconfigure
@@ -72,7 +130,53 @@ struct product_vdo {
  *           011b = USB4 Gen3
  *           100b…111b = Reserved, Shall Not be used
  */
-#define PD_PRODUCT_IS_USB4(vdo) ((vdo) >> 27 & 0x1)
+#define PD_PRODUCT_IS_USB4(vdo) ((vdo) >> 24 & BIT(3))
+#define PD_PRODUCT_IS_TBT3(vdo) ((vdo) >> 3 & BIT(0))
+
+/* UFP VDO Version 1.2; update the value when UFP VDO version changes */
+#define VDO_UFP1(cap, ctype, alt, speed)                         \
+	((0x2) << 29 | ((cap)&0xf) << 24 | ((ctype)&0x3) << 22 | \
+	 ((alt)&0x7) << 3 | ((speed)&0x7))
+
+/* UFP VDO 1 Alternate Modes */
+#define VDO_UFP1_ALT_MODE_TBT3 BIT(0)
+#define VDO_UFP1_ALT_MODE_RECONFIGURE BIT(1)
+#define VDO_UFP1_ALT_MODE_NO_RECONFIGURE BIT(2)
+
+/* UFP VDO 1 Device Capability */
+#define VDO_UFP1_CAPABILITY_USB20 BIT(0)
+#define VDO_UFP1_CAPABILITY_USB20_BILLBOARD BIT(1)
+#define VDO_UFP1_CAPABILITY_USB32 BIT(2)
+#define VDO_UFP1_CAPABILITY_USB4 BIT(3)
+/*****************************************************************************/
+/*
+ * Table 6-37 DFP VDO
+ * -------------------------------------------------------------
+ * <31:29> : DFP VDO version
+ *           Version 1.0 = 000b
+ *           Version 1.1 = 001b
+ *           Values 010b...111b are Reserved and Shall Not be used
+ * <28:27> : Reserved
+ * <26:24> : Host Capability
+ *           001b = USB2.0 host capable
+ *           010b = USB3.2 host capable
+ *           100b = USB4 host capable
+ * <23:22> : Connector Type
+ *           00b = Reserved, Shall Not be used
+ *           01b = Reserved, Shall Not be used
+ *           10b = USB Type-C Receptacle
+ *           11b = USB Type-C Captive Plug
+ * <21:5>  : Reserved
+ * <4:0>   : Port number
+ */
+/* DFP VDO Version 1.1; update the value when DFP VDO version changes */
+#define VDO_DFP(cap, ctype, port) \
+	((0x1) << 29 | ((cap)&0x7) << 24 | ((ctype)&0x3) << 22 | ((port)&0x1f))
+
+/* DFP VDO Host Capability */
+#define VDO_DFP_HOST_CAPABILITY_USB20 BIT(0)
+#define VDO_DFP_HOST_CAPABILITY_USB32 BIT(1)
+#define VDO_DFP_HOST_CAPABILITY_USB4 BIT(2)
 
 /*****************************************************************************/
 /*
@@ -140,6 +244,19 @@ struct product_vdo {
  * Table 5-1 Certified Cables Where USB4-compatible Operation is Expected
  * This table lists the USB-C cables those support USB4
  */
+enum usb_rev30_plug {
+	USB_REV30_TYPE_C = 2,
+	USB_REV30_CAPTIVE = 3,
+};
+
+enum usb_rev30_latency {
+	USB_REV30_LATENCY_1m = 1,
+	USB_REV30_LATENCY_2m = 2,
+	USB_REV30_LATENCY_3m = 3,
+	USB_REV30_LATENCY_4m = 4,
+	USB_REV30_LATENCY_5m = 5,
+	USB_REV30_LATENCY_6m = 6,
+};
 
 enum usb_rev30_ss {
 	USB_R30_SS_U2_ONLY,
@@ -161,7 +278,7 @@ enum usb_vbus_cur {
 
 union passive_cable_vdo_rev30 {
 	struct {
-		enum usb_rev30_ss ss: 3;
+		enum usb_rev30_ss ss : 3;
 		uint32_t reserved0 : 2;
 		enum usb_vbus_cur vbus_cur : 2;
 		uint32_t reserved1 : 2;
@@ -178,6 +295,11 @@ union passive_cable_vdo_rev30 {
 	uint32_t raw_value;
 };
 
+/* Macro passive VDO generator */
+#define VDO_REV30_PASSIVE(ss, vbus_cur, latency, plug)                \
+	((ss & 0x7) | (vbus_cur & 0x3) << 5 | (latency & 0xf) << 13 | \
+	 (plug & 0x3) << 18)
+
 /*****************************************************************************/
 /*
  * Table 6-39 Active Cable VDO 1
@@ -243,9 +365,13 @@ union passive_cable_vdo_rev30 {
  *           011b = [USB4] Gen3
  *           100b..111b = Reserved, Shall Not be used
  */
+enum vdo_version {
+	VDO_VERSION_1_3 = 3,
+};
+
 union active_cable_vdo1_rev30 {
 	struct {
-		enum usb_rev30_ss ss: 3;
+		enum usb_rev30_ss ss : 3;
 		uint32_t sop_p_p : 1;
 		uint32_t vbus_cable : 1;
 		enum usb_vbus_cur vbus_cur : 2;
@@ -257,7 +383,7 @@ union active_cable_vdo1_rev30 {
 		uint32_t reserved0 : 1;
 		uint32_t connector : 2;
 		uint32_t reserved1 : 1;
-		uint32_t vdo_version : 3;
+		enum vdo_version vdo_ver : 3;
 		uint32_t fw_version : 4;
 		uint32_t hw_version : 4;
 	};
@@ -326,6 +452,11 @@ enum active_cable_usb2_support {
 	USB2_NOT_SUPPORTED,
 };
 
+enum active_cable_usb4_support {
+	USB4_SUPPORTED,
+	USB4_NOT_SUPPORTED,
+};
+
 union active_cable_vdo2_rev30 {
 	struct {
 		uint8_t usb_gen : 1;
@@ -335,7 +466,7 @@ union active_cable_vdo2_rev30 {
 		uint8_t usb_32_support : 1;
 		enum active_cable_usb2_support usb_20_support : 1;
 		uint8_t usb_20_hub_hop : 2;
-		uint8_t usb_40_support : 1;
+		enum active_cable_usb4_support usb_40_support : 1;
 		enum retimer_active_element active_elem : 1;
 		uint8_t physical_conn : 1;
 		uint8_t u3_to_u0 : 1;
@@ -411,7 +542,7 @@ union active_cable_vdo2_rev30 {
  *           0b - 3A capable;
  *           1b - 5A capable
  *           Charge Through Support bit = 0b: Reserved, Shall be set to zero
- * <14:13> : Reserved Shall be set to zero.
+ * <13>    : Reserved Shall be set to zero.
  * <12:7>  : VBUS Impedance
  *           Charge Through Support bit = 1b:
  *           Vbus impedance through the VPD in 2 mΩ increments.
@@ -426,11 +557,11 @@ union active_cable_vdo2_rev30 {
  *           1b – the VPD supports Charge Through
  *           0b – the VPD does not support Charge Through
  */
-#define VDO_VPD(hw, fw, vbus, vbusz, gndz, cts)  \
-	(((hw) & 0xf) << 28 | ((fw) & 0xf) << 24 \
-	 | ((vbus) & 0x3) << 15                  \
-	 | ((vbusz) & 0x3f) << 7                 \
-	 | ((gndz) & 0x3f) << 1 | (cts))
+#define VDO_VPD(hw, fw, vbus, ctc, vbusz, gndz, cts)                \
+	(((hw)&0xf) << 28 | ((fw)&0xf) << 24 | ((vbus)&0x3) << 15 | \
+	 ((ctc)&0x1) << 14 | ((vbusz)&0x3f) << 7 | ((gndz)&0x3f) << 1 | (cts))
+
+enum vpd_ctc_support { VPD_CT_CURRENT_3A, VPD_CT_CURRENT_5A };
 
 enum vpd_vbus {
 	VPD_MAX_VBUS_20V,
@@ -440,16 +571,17 @@ enum vpd_vbus {
 };
 
 enum vpd_cts_support {
-	VPD_CTS_SUPPORTED,
 	VPD_CTS_NOT_SUPPORTED,
+	VPD_CTS_SUPPORTED,
 };
 
 #define VPD_VDO_MAX_VBUS(vdo) (((vdo) >> 15) & 0x3)
+#define VPD_VDO_CURRENT(vdo) (((vdo) >> 14) & 1)
 #define VPD_VDO_VBUS_IMP(vdo) (((vdo) >> 7) & 0x3f)
-#define VPD_VDO_GND_IMP(vdo)  (((vdo) >> 1) & 0x3f)
-#define VPD_VDO_CTS(vdo)      ((vdo) & 1)
-#define VPD_VBUS_IMP(mo)      ((mo + 1) >> 1)
-#define VPD_GND_IMP(mo)       (mo)
+#define VPD_VDO_GND_IMP(vdo) (((vdo) >> 1) & 0x3f)
+#define VPD_VDO_CTS(vdo) ((vdo)&1)
+#define VPD_VBUS_IMP(mo) ((mo + 1) >> 1)
+#define VPD_GND_IMP(mo) (mo)
 
 /*
  * ############################################################################
@@ -503,11 +635,10 @@ enum idh_ptype {
  * - Table 6-29 ID Header VDO PD spec 3.0 version 2.0 and
  * - Table 6-23 ID Header VDO PD spec 2.0 version 1.3.
  */
-#define IS_PD_IDH_UFP_PTYPE(ptype) (ptype == IDH_PTYPE_HUB || \
-				    ptype == IDH_PTYPE_PERIPH || \
-				    ptype == IDH_PTYPE_PSD || \
-				    ptype == IDH_PTYPE_AMA ||  \
-				    ptype == IDH_PTYPE_VPD)
+#define IS_PD_IDH_UFP_PTYPE(ptype)                              \
+	(ptype == IDH_PTYPE_HUB || ptype == IDH_PTYPE_PERIPH || \
+	 ptype == IDH_PTYPE_PSD || ptype == IDH_PTYPE_AMA ||    \
+	 ptype == IDH_PTYPE_VPD)
 
 struct id_header_vdo_rev20 {
 	uint16_t usb_vendor_id;
@@ -593,7 +724,7 @@ enum usb_rev20_ss {
 
 union passive_cable_vdo_rev20 {
 	struct {
-		enum usb_rev20_ss ss: 3;
+		enum usb_rev20_ss ss : 3;
 		uint32_t reserved0 : 1;
 		uint32_t vbus_cable : 1;
 		enum usb_vbus_cur vbus_cur : 2;
@@ -676,7 +807,7 @@ union passive_cable_vdo_rev20 {
  */
 union active_cable_vdo_rev20 {
 	struct {
-		enum usb_rev20_ss ss: 3;
+		enum usb_rev20_ss ss : 3;
 		uint32_t sop_p_p : 1;
 		uint32_t vbus_cable : 1;
 		enum usb_vbus_cur vbus_cur : 2;
@@ -744,14 +875,13 @@ union active_cable_vdo_rev20 {
  *           011b = [USB 2.0] billboard only
  *           100b..111b = Reserved, Shall Not be used
  */
-#define VDO_AMA(hw, fw, tx1d, tx2d, rx1d, rx2d, vcpwr, vcr, vbr, usbss) \
-	(((hw) & 0x7) << 28 | ((fw) & 0x7) << 24			\
-	 | (tx1d) << 11 | (tx2d) << 10 | (rx1d) << 9 | (rx2d) << 8	\
-	 | ((vcpwr) & 0x3) << 5 | (vcr) << 4 | (vbr) << 3		\
-	 | ((usbss) & 0x7))
+#define VDO_AMA(hw, fw, tx1d, tx2d, rx1d, rx2d, vcpwr, vcr, vbr, usbss)      \
+	(((hw)&0x7) << 28 | ((fw)&0x7) << 24 | (tx1d) << 11 | (tx2d) << 10 | \
+	 (rx1d) << 9 | (rx2d) << 8 | ((vcpwr)&0x3) << 5 | (vcr) << 4 |       \
+	 (vbr) << 3 | ((usbss)&0x7))
 
 #define PD_VDO_AMA_VCONN_REQ(vdo) (((vdo) >> 4) & 1)
-#define PD_VDO_AMA_VBUS_REQ(vdo)  (((vdo) >> 3) & 1)
+#define PD_VDO_AMA_VBUS_REQ(vdo) (((vdo) >> 3) & 1)
 
 enum ama_usb_ss {
 	AMA_USBSS_U2_ONLY,
@@ -843,6 +973,22 @@ union enter_usb_data_obj {
 	uint32_t raw_value;
 };
 
+union vpd_vdo {
+	struct {
+		uint32_t ct_support : 1;
+		uint32_t gnd_impedance : 6;
+		uint32_t vbus_impedance : 6;
+		uint32_t reserved0 : 1;
+		uint32_t ct_current_support : 1;
+		uint32_t max_vbus_voltage : 2;
+		uint32_t reserved1 : 4;
+		uint32_t vdo_version : 3;
+		uint32_t firmware_version : 4;
+		uint32_t hw_version : 4;
+	};
+	uint32_t raw_value;
+};
+
 /*
  * ############################################################################
  *
@@ -860,6 +1006,9 @@ union product_type_vdo1 {
 	union active_cable_vdo_rev20 a_rev20;
 	union active_cable_vdo1_rev30 a_rev30;
 
+	/* Vconn Power USB Device VDO */
+	union vpd_vdo vpd;
+
 	uint32_t raw_value;
 };
 BUILD_ASSERT(sizeof(uint32_t) == sizeof(union product_type_vdo1));
diff --git a/include/usb_pe_sm.h b/include/usb_pe_sm.h
index 6a4aea5415..21cc65d43d 100644
--- a/include/usb_pe_sm.h
+++ b/include/usb_pe_sm.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,6 +15,7 @@
 enum pe_error {
 	ERR_RCH_CHUNKED,
 	ERR_RCH_MSG_REC,
+	ERR_RCH_CHUNK_WAIT_TIMEOUT,
 	ERR_TCH_CHUNKED,
 	ERR_TCH_XMIT,
 };
@@ -49,7 +50,7 @@ void pe_message_sent(int port);
  * @param  e    error
  * @param type  port address where error was generated
  */
-void pe_report_error(int port, enum pe_error e, enum tcpm_transmit_type type);
+void pe_report_error(int port, enum pe_error e, enum tcpci_msg_type type);
 
 /**
  * Informs the Policy Engine of a discard.
@@ -139,6 +140,15 @@ int pd_is_port_partner_dualrole(int port);
  */
 void pe_invalidate_explicit_contract(int port);
 
+/*
+ * Return true if the PE is in middle of a fast role swap (FRS). If so, the
+ * Rp/Rd will be flipped from the actual power roles.
+ *
+ *
+ * @param port USB-C port number
+ */
+bool pe_in_frs_mode(int port);
+
 /*
  * Return true if the PE is is within an atomic
  * messaging sequence that it initiated with a SOP* port partner.
@@ -167,12 +177,51 @@ const char *pe_get_current_state(int port);
 uint32_t pe_get_flags(int port);
 
 /**
- * Sets event for PE layer to report and triggers a notification up to the AP.
+ * Sets the Alert Data Object (ADO) in the PE state
  *
  * @param port USB-C port number
- * @param event_mask of bits to set (PD_STATUS_EVENT_* events in ec_commands.h)
+ * @param data - ADO data sent during alert messages
+ * @return EC_SUCCESS if successful and EC_ERROR_BUSY if not
  */
-void pe_notify_event(int port, uint32_t event_mask);
+int pe_set_ado(int port, uint32_t data);
 
-#endif /* __CROS_EC_USB_PE_H */
+/**
+ * Clears the Alert Data Object (ADO) in the PE state
+ *
+ * @param port USB-C port number
+ */
+void pe_clear_ado(int port);
+
+#ifdef TEST_BUILD
+/**
+ * Clears all internal port data, as we would on a detach event
+ *
+ * @param port USB-C port number
+ */
+void pe_clear_port_data(int port);
+#endif /* TEST_BUILD */
 
+/**
+ * Check whether the port is in EPR mode or not.
+ *
+ * @param port USB-C port number
+ * @return true if the port is in EPR mode or false.
+ */
+bool pe_snk_in_epr_mode(int port);
+
+/**
+ * Make a sink exit EPR mode explicitly.
+ *
+ * @param port USB-C port number
+ */
+void pe_snk_epr_explicit_exit(int port);
+
+/**
+ * Checks whether the port is ready for EPR entry.
+ *
+ * @param port USB-C port number
+ * @return true if the port can enter EPR mode or false.
+ */
+bool pe_snk_can_enter_epr_mode(int port);
+
+#endif /* __CROS_EC_USB_PE_H */
diff --git a/include/usb_prl_sm.h b/include/usb_prl_sm.h
index d5d133f250..5dda58a733 100644
--- a/include/usb_prl_sm.h
+++ b/include/usb_prl_sm.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,10 +8,18 @@
 #ifndef __CROS_EC_USB_PRL_H
 #define __CROS_EC_USB_PRL_H
 #include "common.h"
+#include "timer.h"
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 #include "usb_sm.h"
 
+/**
+ * Returns TX success time stamp.
+ *
+ * @param port USB-C port number
+ * @return the time stamp of TCPC tx success.
+ **/
+timestamp_t prl_get_tcpc_tx_success_ts(int port);
 
 /**
  * Returns true if Protocol Layer State Machine is in run mode
@@ -38,18 +46,22 @@ bool prl_is_busy(int port);
 void prl_set_debug_level(enum debug_level level);
 
 /**
- * Resets the Protocol Layer State Machine
+ * Resets the Protocol Layer state machine but does not reset the stored PD
+ * revisions of the partners.
  *
  * @param port USB-C port number
  */
-void prl_reset(int port);
+void prl_reset_soft(int port);
 
 /**
- * Resets the Protocol Layer State Machine (softly)
+ * resets the stored pd revisions for each sop type to their default value, the
+ * highest revision supported by this implementation. per pd r3.0 v2.0,
+ * ss6.2.1.1.5, this should only happen upon detach, hard reset, or error
+ * recovery.
  *
  * @param port USB-C port number
  */
-void prl_reset_soft(int port);
+void prl_set_default_pd_revision(int port);
 
 /**
  * Runs the Protocol Layer State Machine
@@ -67,8 +79,7 @@ void prl_run(int port, int evt, int en);
  * @param type port address
  * @param rev revision
  */
-void prl_set_rev(int port, enum tcpm_transmit_type type,
-					enum pd_rev_type rev);
+void prl_set_rev(int port, enum tcpci_msg_type type, enum pd_rev_type rev);
 
 /**
  * Get the PD revision
@@ -77,7 +88,16 @@ void prl_set_rev(int port, enum tcpm_transmit_type type,
  * @param type port address
  * @return pd rev
  */
-enum pd_rev_type prl_get_rev(int port, enum tcpm_transmit_type type);
+enum pd_rev_type prl_get_rev(int port, enum tcpci_msg_type type);
+
+/**
+ * Reset Tx and Rx message IDs for the specified partner to their initial
+ * values.
+ *
+ * @param port USB-C port number
+ * @param type Transmit type
+ */
+void prl_reset_msg_ids(int port, enum tcpci_msg_type type);
 
 /**
  * Sends a PD control message
@@ -86,8 +106,8 @@ enum pd_rev_type prl_get_rev(int port, enum tcpm_transmit_type type);
  * @param type Transmit type
  * @param msg  Control message type
  */
-void prl_send_ctrl_msg(int port, enum tcpm_transmit_type type,
-	enum pd_ctrl_msg_type msg);
+void prl_send_ctrl_msg(int port, enum tcpci_msg_type type,
+		       enum pd_ctrl_msg_type msg);
 
 /**
  * Sends a PD data message
@@ -96,8 +116,8 @@ void prl_send_ctrl_msg(int port, enum tcpm_transmit_type type,
  * @param type Transmit type
  * @param msg  Data message type
  */
-void prl_send_data_msg(int port, enum tcpm_transmit_type type,
-	enum pd_data_msg_type msg);
+void prl_send_data_msg(int port, enum tcpci_msg_type type,
+		       enum pd_data_msg_type msg);
 
 /**
  * Sends a PD extended data message
@@ -106,8 +126,8 @@ void prl_send_data_msg(int port, enum tcpm_transmit_type type,
  * @param type Transmit type
  * @param msg  Extended data message type
  */
-void prl_send_ext_data_msg(int port, enum tcpm_transmit_type type,
-	enum pd_ext_msg_type msg);
+void prl_send_ext_data_msg(int port, enum tcpci_msg_type type,
+			   enum pd_ext_msg_type msg);
 
 /**
  * Informs the Protocol Layer that a hard reset has completed
@@ -123,28 +143,12 @@ void prl_hard_reset_complete(int port);
  */
 void prl_execute_hard_reset(int port);
 
-#ifdef TEST_BUILD
 /**
- * Fake to track the last sent control message
- */
-enum pd_ctrl_msg_type fake_prl_get_last_sent_ctrl_msg(int port);
-
-/**
- * Fake to set the last sent control message to an invalid value.
- */
-void fake_prl_clear_last_sent_ctrl_msg(int port);
-
-/**
- * Get the type of the last sent data message on the given port.
- */
-enum pd_data_msg_type fake_prl_get_last_sent_data_msg_type(int port);
-
-/**
- * Clear the last sent data message on the given port to an invalid value,
- * making it possible to check that two of the same message were sent in order.
+ * Enables or disables checking the data role on incoming messages.
+ *
+ * @param port USB-C port number
+ * @param enable True to enable checking, false to disable checking
  */
-void fake_prl_clear_last_sent_data_msg(int port);
-#endif
+void prl_set_data_role_check(int port, bool enable);
 
 #endif /* __CROS_EC_USB_PRL_H */
-
diff --git a/include/usb_sm.h b/include/usb_sm.h
index d8eff5190a..d945ebd0ac 100644
--- a/include/usb_sm.h
+++ b/include/usb_sm.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,6 +8,8 @@
 #ifndef __CROS_EC_USB_SM_H
 #define __CROS_EC_USB_SM_H
 
+#include "compiler.h" /* for typeof() on Zephyr */
+
 /* Function pointer that implements a portion of a usb state */
 typedef void (*state_execution)(const int port);
 
@@ -99,13 +101,13 @@ struct test_sm_data {
 	/* Size fo the state machine array above */
 	const int size;
 	/* The array of names for states, can be NULL */
-	const char * const * const names;
+	const char *const *const names;
 	/* The size of the above names array */
 	const int names_size;
 };
 #endif
 
 /* Creates a state machine state that will never link. Useful with IS_ENABLED */
-#define GEN_NOT_SUPPORTED(state) extern typeof(state) state ## _NOT_SUPPORTED
+#define GEN_NOT_SUPPORTED(state) extern typeof(state) state##_NOT_SUPPORTED
 
 #endif /* __CROS_EC_USB_SM_H */
diff --git a/include/usb_tbt_alt_mode.h b/include/usb_tbt_alt_mode.h
index fb3aadb481..ff2ad44ed0 100644
--- a/include/usb_tbt_alt_mode.h
+++ b/include/usb_tbt_alt_mode.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,9 +11,11 @@
 #ifndef __CROS_EC_USB_TBT_ALT_MODE_H
 #define __CROS_EC_USB_TBT_ALT_MODE_H
 
-#include <stdint.h>
+#include "tcpm/tcpm.h"
+#include "usb_pd_dpm_sm.h"
+#include "usb_pd_tcpm.h"
 
-#include "tcpm.h"
+#include <stdint.h>
 
 /*
  * Initialize Thunderbolt state for the specified port.
@@ -23,10 +25,46 @@
 void tbt_init(int port);
 
 /*
- * Returns True if Thunderbolt mode is in active state
+ * Requests to exit the Thunderbolt alternate mode
+ *
+ * @param port USB-C port number
+ */
+void tbt_exit_mode_request(int port);
+
+/*
+ * Checks whether Thunderbolt cable mode entry is required prior to entering
+ * USB4.
+ *
+ * @param port      USB-C port number
+ * @return          True if Thunderbolt cable mode entry is required
+ *		    False otherwise
+ */
+bool tbt_cable_entry_required_for_usb4(int port);
+
+/*
+ * Checks whether the mode entry sequence for Thunderbolt alternate mode is
+ * done for a port.
+ *
+ * @param port      USB-C port number
+ * @return          True if entry sequence for Thunderbolt mode is completed
+ *                  False otherwise
+ */
+bool tbt_entry_is_done(int port);
+
+/*
+ * Checks if the cable entry into Thunderbolt alternate mode is done
  *
  * @param port      USB-C port number
- * @return          True if Thunderbolt mode is in active state
+ * @return          True if TBT_FLAG_CABLE_ENTRY_DONE is set
+ *                  False otherwise
+ */
+bool tbt_cable_entry_is_done(int port);
+
+/*
+ * Returns True if Thunderbolt mode is not in inactive state
+ *
+ * @param port      USB-C port number
+ * @return          True if Thunderbolt mode is not in inactive state
  *                  False otherwise
  */
 bool tbt_is_active(int port);
@@ -39,8 +77,8 @@ bool tbt_is_active(int port);
  * @param vdo_count The number of VDOs in the ACK VDM
  * @param vdm       VDM from ACK
  */
-void intel_vdm_acked(int port, enum tcpm_transmit_type type, int vdo_count,
-		uint32_t *vdm);
+void intel_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count,
+		     uint32_t *vdm);
 
 /*
  * Handles NAKed (or Not Supported or timed out) Thunderbolt VDM requests.
@@ -50,27 +88,22 @@ void intel_vdm_acked(int port, enum tcpm_transmit_type type, int vdo_count,
  * @param svid    The SVID of the request
  * @param vdm_cmd The VDM command of the request
  */
-void intel_vdm_naked(int port, enum tcpm_transmit_type type, uint8_t vdm_cmd);
-
-/*
- * Reset the Thunderbolt mode VDM state for the specified port, as when exiting
- * Thunderbolt mode.
- *
- * @param port USB-C port number
- */
-void tbt_teardown(int port);
+void intel_vdm_naked(int port, enum tcpci_msg_type type, uint8_t vdm_cmd);
 
 /*
  * Construct the next Thunderbolt VDM that should be sent.
  *
- * @param port      USB-C port number
- * @param vdo_count The number of VDOs in vdm; must be at least VDO_MAX_SIZE
- * @param vdm       The VDM payload to be sent; output; must point to at least
- *                  VDO_MAX_SIZE elements
- * @param tx_type   Transmit type(SOP, SOP', SOP'') for next VDM to be sent
- * @return          The number of VDOs written to VDM or -1 to indicate error
+ * @param[in] port          USB-C port number
+ * @param[in,out] vdo_count The number of VDOs in vdm; must be at least
+ *		            VDO_MAX_SIZE.  Filled with VDOs populated on success
+ * @param[out] vdm          The VDM payload to be sent; output; must point to at
+ *			    least VDO_MAX_SIZE elements
+ * @param[out] tx_type	    Transmit type(SOP, SOP', SOP'') for next VDM to be
+ *			    sent
+ * @return		    enum dpm_msg_setup_status
  */
-int tbt_setup_next_vdm(int port, int vdo_count, uint32_t *vdm,
-		enum tcpm_transmit_type *tx_type);
+enum dpm_msg_setup_status tbt_setup_next_vdm(int port, int *vdo_count,
+					     uint32_t *vdm,
+					     enum tcpci_msg_type *tx_type);
 
 #endif
diff --git a/include/usb_tc_sm.h b/include/usb_tc_sm.h
index f325a56e90..009e5db089 100644
--- a/include/usb_tc_sm.h
+++ b/include/usb_tc_sm.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,9 +8,9 @@
 #ifndef __CROS_EC_USB_TC_H
 #define __CROS_EC_USB_TC_H
 
-#include "usb_sm.h"
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
+#include "usb_sm.h"
 
 enum try_src_override_t {
 	TRY_SRC_OVERRIDE_OFF,
@@ -24,7 +24,7 @@ enum try_src_override_t {
  * This is the maximum voltage a sink can request
  * while charging.
  */
-#define TYPE_C_VOLTAGE  5000 /* mV */
+#define TYPE_C_VOLTAGE 5000 /* mV */
 
 /*
  * Type C default sink current (mA)
@@ -32,7 +32,7 @@ enum try_src_override_t {
  * This is the maximum current a sink can draw if charging
  * while in the Audio Accessory State.
  */
-#define TYPE_C_AUDIO_ACC_CURRENT  500 /* mA */
+#define TYPE_C_AUDIO_ACC_CURRENT 500 /* mA */
 
 /**
  * Returns true if TypeC State machine is in attached source state.
@@ -181,20 +181,13 @@ void tc_request_power_swap(int port);
 void tc_pr_swap_complete(int port, bool success);
 
 /**
- * Informs the Type-C State Machine that a Discover Identity is in progress.
- * This function is called from the Policy Engine.
+ * The Type-C state machine updates the SLEEP_MASK_USB_PD mask for the
+ * case that TCPC wants to set/clear SLEEP_MASK_USB_PD mask only by
+ * itself, ex. TCPC embedded in EC.
  *
  * @param port USB_C port number
  */
-void tc_disc_ident_in_progress(int port);
-
-/**
- * Informs the Type-C State Machine that a Discover Identity is complete.
- * This function is called from the Policy Engine.
- *
- * @param port USB_C port number
- */
-void tc_disc_ident_complete(int port);
+__override_proto void tc_update_pd_sleep_mask(int port);
 
 /**
  * Instructs the Attached.SNK to stop drawing power. This function is called
@@ -263,7 +256,7 @@ void pd_request_vconn_swap_off(int port);
  * @return 0 if cc1 is connected, else 1 for cc2
  */
 enum tcpc_cc_polarity get_snk_polarity(enum tcpc_cc_voltage_status cc1,
-	enum tcpc_cc_voltage_status cc2);
+				       enum tcpc_cc_voltage_status cc2);
 
 /**
  * Called by the state machine framework to initialize the
@@ -331,6 +324,14 @@ void tc_start_event_loop(int port);
  */
 void tc_pause_event_loop(int port);
 
+/**
+ * Determine if the state machine event loop is paused
+ *
+ * @param port USB-C port number
+ * @return true if paused, else false
+ */
+bool tc_event_loop_is_paused(int port);
+
 /**
  * Allow system to override the control of TrySrc
  *
@@ -365,6 +366,24 @@ const char *tc_get_current_state(int port);
  */
 uint32_t tc_get_flags(int port);
 
+/**
+ * USB retimer firmware update set run flag
+ * Setting this flag indicates firmware update operations can be
+ * processed unconditionally.
+ *
+ * @param port USB-C port number
+ */
+void tc_usb_firmware_fw_update_run(int port);
+
+/**
+ * USB retimer firmware update set limited run flag
+ * Setting this flag indicates firmware update operations can be
+ * processed under limitation: PD task has to be suspended.
+ *
+ * @param port USB-C port number
+ */
+void tc_usb_firmware_fw_update_limited_run(int port);
+
 #ifdef CONFIG_USB_CTVPD
 
 /**
@@ -384,4 +403,3 @@ void tc_reset_support_timer(int port);
 void tc_ctvpd_detected(int port);
 #endif /* CONFIG_USB_CTVPD */
 #endif /* __CROS_EC_USB_TC_H */
-
diff --git a/include/usbc_ocp.h b/include/usbc_ocp.h
new file mode 100644
index 0000000000..6c1d641931
--- /dev/null
+++ b/include/usbc_ocp.h
@@ -0,0 +1,76 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_USBC_OCP_H
+#define __CROS_EC_USBC_OCP_H
+
+#include "common.h"
+
+/* Common APIs for USB Type-C Overcurrent Protection (OCP) Module */
+
+/*
+ * PD 3.1 Ver 1.3 7.1.7.1 Output Over Current Protection
+ *
+ * "After three consecutive over current events Source Shall go to
+ * ErrorRecovery.
+ *
+ * Sources Should attempt to send a Hard Reset message when over
+ * current protection engages followed by an Alert Message indicating
+ * an OCP event once an Explicit Contract has been established.
+ *
+ * The Source Shall prevent continual system or port cycling if over
+ * current protection continues to engage after initially resuming
+ * either default operation or renegotiation. Latching off the port or
+ * system is an acceptable response to recurring over current."
+ *
+ * Our policy will be first two OCPs -> hard reset
+ * 3rd -> ErrorRecovery
+ * 4th -> port latched off
+ */
+#define OCP_HR_CNT 2
+
+#define OCP_MAX_CNT 4
+
+/**
+ * Increment the overcurrent event counter.
+ *
+ * @param port: The Type-C port that has overcurrented.
+ * @return EC_SUCCESS on success, EC_ERROR_INVAL if non-existent port.
+ */
+int usbc_ocp_add_event(int port);
+
+/**
+ * Clear the overcurrent event counter
+ *
+ * @param port: The Type-C port number.
+ * @return EC_SUCCESS on success, EC_ERROR_INVAL if non-existent port
+ */
+int usbc_ocp_clear_event_counter(int port);
+
+/**
+ * Is the port latched off due to multiple overcurrent events in succession?
+ *
+ * @param port: The Type-C port number.
+ * @return 1 if the port is latched off, 0 if it is not latched off.
+ */
+int usbc_ocp_is_port_latched_off(int port);
+
+/**
+ * Register a port as having a sink connected
+ *
+ * @param port: The Type-C port number.
+ * @param connected: true if sink is now connected on port
+ */
+void usbc_ocp_snk_is_connected(int port, bool connected);
+
+/**
+ * Board specific callback when a port overcurrents.
+ *
+ * @param port: The Type-C port which overcurrented.
+ * @param is_overcurrented: 1 if port overcurrented, 0 if the condition is gone.
+ */
+__override_proto void board_overcurrent_event(int port, int is_overcurrented);
+
+#endif /* !defined(__CROS_EC_USBC_OCP_H) */
diff --git a/include/usbc_ppc.h b/include/usbc_ppc.h
index 00a2911363..ec7e8ad7c0 100644
--- a/include/usbc_ppc.h
+++ b/include/usbc_ppc.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,17 +11,12 @@
 
 /* Common APIs for USB Type-C Power Path Controllers (PPC) */
 
-/*
- * Number of times a port may overcurrent before we latch off the port until a
- * physical disconnect is detected.
- */
-#define PPC_OC_CNT_THRESH 3
-
-/*
- * Number of seconds until a latched-off port is re-enabled for sourcing after
- * detecting a physical disconnect.
- */
-#define PPC_OC_COOLDOWN_DELAY_US (2 * SECOND)
+/* The role of connected device. */
+enum ppc_device_role {
+	PPC_DEV_SNK,
+	PPC_DEV_SRC,
+	PPC_DEV_DISCONNECTED,
+};
 
 /*
  * NOTE: The pointers to functions in the ppc_drv structure can now be NULL
@@ -94,6 +89,17 @@ struct ppc_drv {
 	 */
 	int (*discharge_vbus)(int port, int enable);
 
+	/**
+	 * Inform the PPC of the device is connected or disconnected.
+	 *
+	 * @param port: The Type-C port number.
+	 * @param dev: PPC_DEV_SNK if a sink is connected, PPC_DEV_SRC if a
+	 *             source is connected, PPC_DEV_DISCONNECTED if the device
+	 *             is disconnected.
+	 * @return EC_SUCCESS on success, error otherwise.
+	 */
+	int (*dev_is_connected)(int port, enum ppc_device_role dev);
+
 #ifdef CONFIG_USBC_PPC_SBU
 	/**
 	 * Turn on/off the SBU FETs.
@@ -152,6 +158,13 @@ struct ppc_drv {
 	 * @return EC_SUCCESS on success, error otherwise.
 	 */
 	int (*enter_low_power_mode)(int port);
+
+	/**
+	 * Interrupt handler for GPIO pin.
+	 *
+	 * @port Port The Type-C port which triggered the interrupt.
+	 */
+	void (*interrupt)(int port);
 };
 
 struct ppc_config_t {
@@ -181,30 +194,18 @@ int ppc_prints(const char *string, int port);
  */
 int ppc_err_prints(const char *string, int port, int error);
 
-/**
- * Increment the overcurrent event counter.
- *
- * @param port: The Type-C port that has overcurrented.
- * @return EC_SUCCESS on success, EC_ERROR_INVAL if non-existent port.
- */
-int ppc_add_oc_event(int port);
-
-/**
- * Clear the overcurrent event counter.
- *
- * @param port: The Type-C port's counter to clear.
- * @return EC_SUCCESS on success, EC_ERROR_INVAL if non-existent port.
- */
-int ppc_clear_oc_event_counter(int port);
-
 /**
  * Discharge PD VBUS on src/sink disconnect & power role swap
  *
  * @param port: The Type-C port number.
  * @param enable: 1 -> discharge vbus, 0 -> stop discharging vbus
  * @return EC_SUCCESS on success, error otherwise.
+ *
+ * TODO(b/255413715): Remove test_mockable when it is practical to convert the
+ * usb_pd_flags test to use the unit-testing framework and not require weak
+ * functions for mocking.
  */
-int ppc_discharge_vbus(int port, int enable);
+test_mockable int ppc_discharge_vbus(int port, int enable);
 
 /**
  * Initializes the PPC for the specified port.
@@ -214,21 +215,13 @@ int ppc_discharge_vbus(int port, int enable);
  */
 int ppc_init(int port);
 
-/**
- * Is the port latched off due to multiple overcurrent events in succession?
- *
- * @param port: The Type-C port number.
- * @return 1 if the port is latched off, 0 if it is not latched off.
- */
-int ppc_is_port_latched_off(int port);
-
 /**
  * Is the port sourcing Vbus?
  *
  * @param port: The Type-C port number.
  * @return 1 if sourcing Vbus, 0 if not.
  */
-int ppc_is_sourcing_vbus(int port);
+test_mockable int ppc_is_sourcing_vbus(int port);
 
 /**
  * Determine if VBUS is present or not.
@@ -239,15 +232,15 @@ int ppc_is_sourcing_vbus(int port);
 int ppc_is_vbus_present(int port);
 
 /**
- * Inform the PPC module that a sink is connected.
+ * Inform the PPC module that a device (either sink or source) is connected.
  *
- * This is used such that it can determine when to clear the overcurrent events
- * counter for a port.
+ * This is used such that it can determine when to clear the overcurrent events,
+ * and disable discharge VBUS on a source device connected.
  * @param port: The Type-C port number.
- * @param is_connected: 1: if sink is connected on this port, 0: if not
- *                      connected.
+ * @param dev: PPC_DEV_SNK if a sink is connected, PPC_DEV_SRC if a source is
+ *             connected, PPC_DEV_DISCONNECTED if the device is disconnected.
  */
-void ppc_sink_is_connected(int port, int is_connected);
+int ppc_dev_is_connected(int port, enum ppc_device_role dev);
 
 /**
  * Inform the PPC of the polarity of the CC pins.
@@ -303,14 +296,6 @@ int ppc_vbus_sink_enable(int port, int enable);
  */
 int ppc_vbus_source_enable(int port, int enable);
 
-/**
- * Board specific callback when a port overcurrents.
- *
- * @param port: The Type-C port which overcurrented.
- * @param is_overcurrented: 1 if port overcurrented, 0 if the condition is gone.
- */
-void board_overcurrent_event(int port, int is_overcurrented);
-
 /**
  * Put the PPC into its lowest power state. In this state it should still fire
  * interrupts if Vbus changes etc. This is called by board-specific code when
@@ -337,4 +322,17 @@ int ppc_get_alert_status(int port);
  */
 int ppc_set_frs_enable(int port, int enable);
 
+/**
+ * Board specific function to check if the Type-C port has PPC
+ *
+ * Some PD/TCPC chips have integrated power path control. If the board is
+ * using combination of chips with discrete PPC and integrated PPC add an
+ * overridable board function to return false for integrated PPC ports and
+ * true for discrete PPC port.
+ *
+ * @param port: The Type-C port number to check
+ * @return true if Type-C port has PPC else false
+ */
+__override_proto bool board_port_has_ppc(int port);
+
 #endif /* !defined(__CROS_EC_USBC_PPC_H) */
diff --git a/include/util.h b/include/util.h
index 5594a4a706..8dd23de638 100644
--- a/include/util.h
+++ b/include/util.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,11 +10,21 @@
 
 #include "common.h"
 #include "compile_time_macros.h"
-#include "panic.h"
 
-#include "builtin/assert.h"         /* For ASSERT(). */
+#include <ctype.h>
 #include <stdbool.h>
 #include <stddef.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <strings.h>
+#ifdef CONFIG_ZEPHYR
+#include <zephyr/sys/util.h>
+/**
+ * TODO(b/237712836): Remove once Zephyr's libc has strcasecmp.
+ */
+#include "builtin/strings.h"
+#endif
 
 #ifdef __cplusplus
 extern "C" {
@@ -24,27 +34,30 @@ extern "C" {
 #define GENERIC_MAX(x, y) ((x) > (y) ? (x) : (y))
 #define GENERIC_MIN(x, y) ((x) < (y) ? (x) : (y))
 #ifndef MAX
-#define MAX(a, b)					\
-	({						\
-		__typeof__(a) temp_a = (a);		\
-		__typeof__(b) temp_b = (b);		\
-							\
-		GENERIC_MAX(temp_a, temp_b);		\
+#define MAX(a, b)                            \
+	({                                   \
+		__typeof__(a) temp_a = (a);  \
+		__typeof__(b) temp_b = (b);  \
+                                             \
+		GENERIC_MAX(temp_a, temp_b); \
 	})
 #endif
 #ifndef MIN
-#define MIN(a, b)					\
-	({						\
-		__typeof__(a) temp_a = (a);		\
-		__typeof__(b) temp_b = (b);		\
-							\
-		GENERIC_MIN(temp_a, temp_b);		\
+#define MIN(a, b)                            \
+	({                                   \
+		__typeof__(a) temp_a = (a);  \
+		__typeof__(b) temp_b = (b);  \
+                                             \
+		GENERIC_MIN(temp_a, temp_b); \
 	})
 #endif
 #ifndef NULL
 #define NULL ((void *)0)
 #endif
 
+/* Returns true if string is not null and not empty */
+#define IS_NONEMPTY_STRING(s) ((s) && (s)[0])
+
 /**
  * Ensure that value `v` is between `min` and `max`.
  *
@@ -54,77 +67,40 @@ extern "C" {
  * @return `v` if it is already between `min`/`max`, `min` if `v` was smaller
  * than `min`, `max` if `v` was bigger than `max`.
  */
+#ifndef CONFIG_ZEPHYR
 #define CLAMP(v, min, max) MIN(max, MAX(v, min))
+#endif
 
 /*
  * Convert a pointer to a base struct into a pointer to the struct that
  * contains the base struct.  This requires knowing where in the contained
  * struct the base struct resides, this is the member parameter to downcast.
  */
-#define DOWNCAST(pointer, type, member)					\
-	((type *)(((uint8_t *) pointer) - offsetof(type, member)))
+#define DOWNCAST(pointer, type, member) \
+	((type *)(((uint8_t *)pointer) - offsetof(type, member)))
 
 /* True of x is a power of two */
-#define POWER_OF_TWO(x) ((x) && !((x) & ((x) - 1)))
+#define POWER_OF_TWO(x) ((x) && !((x) & ((x)-1)))
 
 /* Macro to check if the value is in range */
-#define IN_RANGE(x, min, max) ((x) >= (min) && (x) < (max))
+#ifndef CONFIG_ZEPHYR
+#define IN_RANGE(x, min, max) ((x) >= (min) && (x) <= (max))
+#endif
 
 /*
  * macros for integer division with various rounding variants
  * default integer division rounds down.
  */
-#define DIV_ROUND_UP(x, y) (((x) + ((y) - 1)) / (y))
-#define DIV_ROUND_NEAREST(x, y) (((x) + ((y) / 2)) / (y))
-
-/*
- * Swap two variables (requires c99)
- *
- * Swapping composites (e.g. a+b, x++) doesn't make sense. So, <a> and <b>
- * can only be a variable (x) or a pointer reference (*x) without operator.
- */
-#define swap(a, b) \
-	do { \
-		typeof(a) __t__; \
-		__t__ = a; \
-		a = b; \
-		b = __t__; \
-	} while (0)
-
-#ifndef HIDE_EC_STDLIB
-
-/* Standard library functions */
-int atoi(const char *nptr);
-int isdigit(int c);
-int isspace(int c);
-int isalpha(int c);
-int isupper(int c);
-int isprint(int c);
-int memcmp(const void *s1, const void *s2, size_t len);
-void *memcpy(void *dest, const void *src, size_t len);
-void *memset(void *dest, int c, size_t len);
-void *memmove(void *dest, const void *src, size_t len);
-void *memchr(const void *buffer, int c, size_t n);
-int strcasecmp(const char *s1, const char *s2);
-int strncasecmp(const char *s1, const char *s2, size_t size);
-
-/**
- * Find the first occurrence of the substring <s2> in the string <s1>
- *
- * @param s1	String where <s2> is searched.
- * @param s2	Substring to be located in <s1>
- * @return	Pointer to the located substring or NULL if not found.
- */
-char *strstr(const char *s1, const char *s2);
+#ifndef DIV_ROUND_UP
+#define DIV_ROUND_UP(x, y) (((x) + ((y)-1)) / (y))
+#endif
 
-size_t strlen(const char *s);
-size_t strnlen(const char *s, size_t maxlen);
-char *strncpy(char *dest, const char *src, size_t n);
-int strncmp(const char *s1, const char *s2, size_t n);
+#define DIV_ROUND_NEAREST(x, y) (((x) + ((y) / 2)) / (y))
 
 /* Like strtol(), but for integers. */
 int strtoi(const char *nptr, char **endptr, int base);
-uint64_t strtoul(const char *nptr, char **endptr, int base);
+
+unsigned long long int strtoull(const char *nptr, char **endptr, int base);
 
 /* Like strncpy(), but guarantees null termination. */
 char *strzcpy(char *dest, const char *src, int len);
@@ -148,9 +124,6 @@ char *strzcpy(char *dest, const char *src, int len);
  */
 int parse_bool(const char *s, int *dest);
 
-int tolower(int c);
-#endif  /* !HIDE_EC_STDLIB */
-
 /**
  * Constant time implementation of memcmp to avoid timing side channels.
  */
@@ -195,12 +168,22 @@ bool bytes_are_trivial(const uint8_t *buffer, size_t size);
  */
 bool is_aligned(uint32_t addr, uint32_t align);
 
+/**
+ * Get the alignment of x; the number of trailing zero bits.
+ *
+ * x must not be zero, otherwise the result is undefined (and will panic
+ * in debug builds).
+ *
+ * @return the number of consecutive zero bits in x starting from the lsb
+ */
+int alignment_log2(unsigned int x);
+
 /**
  * Reverse's the byte-order of the provided buffer.
  */
 void reverse(void *dest, size_t len);
 
-
+int find_base(int base, int *c, const char **nptr);
 /****************************************************************************/
 /* Conditional stuff.
  *
@@ -227,25 +210,49 @@ typedef uint8_t cond_t;
 
 /* Initialize a conditional to a specific state. Do this first. */
 void cond_init(cond_t *c, int boolean);
-static inline void cond_init_false(cond_t *c) { cond_init(c, 0); }
-static inline void cond_init_true(cond_t *c) { cond_init(c, 1); }
+static inline void cond_init_false(cond_t *c)
+{
+	cond_init(c, 0);
+}
+static inline void cond_init_true(cond_t *c)
+{
+	cond_init(c, 1);
+}
 
 /* Set the current state. Do this as often as you like. */
 void cond_set(cond_t *c, int boolean);
-static inline void cond_set_false(cond_t *c) { cond_set(c, 0); }
-static inline void cond_set_true(cond_t *c) { cond_set(c, 1); }
+static inline void cond_set_false(cond_t *c)
+{
+	cond_set(c, 0);
+}
+static inline void cond_set_true(cond_t *c)
+{
+	cond_set(c, 1);
+}
 
 /* Get the current state. Do this as often as you like. */
 int cond_is(cond_t *c, int boolean);
-static inline int cond_is_false(cond_t *c) { return cond_is(c, 0); }
-static inline int cond_is_true(cond_t *c) { return cond_is(c, 1); }
+static inline int cond_is_false(cond_t *c)
+{
+	return cond_is(c, 0);
+}
+static inline int cond_is_true(cond_t *c)
+{
+	return cond_is(c, 1);
+}
 
 /* See if the state has transitioned. If it has, the corresponding function
  * will return true ONCE only, until it's changed back.
  */
 int cond_went(cond_t *c, int boolean);
-static inline int cond_went_false(cond_t *c) { return cond_went(c, 0); }
-static inline int cond_went_true(cond_t *c) { return cond_went(c, 1); }
+static inline int cond_went_false(cond_t *c)
+{
+	return cond_went(c, 0);
+}
+static inline int cond_went_true(cond_t *c)
+{
+	return cond_went(c, 1);
+}
 
 /****************************************************************************/
 /* Console command parsing */
@@ -253,8 +260,8 @@ static inline int cond_went_true(cond_t *c) { return cond_went(c, 1); }
 /* Parse command-line arguments given integer shift value to obtain
  * offset and size.
  */
-int parse_offset_size(int argc, char **argv, int shift,
-			     int *offset, int *size);
+int parse_offset_size(int argc, const char **argv, int shift, int *offset,
+		      int *size);
 
 /**
  * Print binary in hex and ASCII
@@ -308,8 +315,58 @@ static inline uint64_t mulaa32(uint32_t a, uint32_t b, uint32_t c, uint32_t d)
  */
 void wait_for_ready(volatile uint32_t *reg, uint32_t enable, uint32_t ready);
 
+/**
+ * Convert the ternary bit array (each element is either 0, 1, or 2) to a
+ * non-standard ternary number system where the first 2^n natural numbers are
+ * represented as they would be in a binary system (without any Z digits) and
+ * the following 3^n-2^n numbers use the remaining ternary representations in
+ * the normal ternary system order (skipping the values that were already used
+ * up).
+ *
+ * This function is useful for converting BOARD ID, which is initially used a
+ * binary and later decided to switch to tri-state after some revisions have
+ * already been built.
+ *
+ * Example: For nbits = 2 we get the following representation:
+ *
+ *   Number      X1     X0
+ *     0          0      0
+ *     1          0      1
+ *     2          1      0
+ *     3          1      1	// Start counting ternaries back at 0 after this
+ *     4          0      2	// Skipping 00 and 01 which are already used up
+ *     5          1      2	// Skipping 10 and 11 which are already used up
+ *     6          2      0
+ *     7          2      1
+ *     8          2      2
+ *
+ * @param bits		Array of ternary bits (LSB first).
+ * @param nbits		Total number of bits.
+ * @return Number in the binary-first ternary number system.
+ */
+int binary_first_base3_from_bits(int *bits, int nbits);
+
+/**
+ * Convert the binary bit array to integer value.
+ *
+ * @param bits    array of integers with values of 0 and 1
+ * @param nbits   number of bits to decode
+ * @return        integer decoded from bits
+ */
+int binary_from_bits(int *bits, int nbits);
+
+/**
+ * Convert the ternary bit array to integer value.
+ * This function is used to handle 'Z' state of gpio as value of '2'.
+ *
+ * @param bits    array of integers with values of 0, 1 or 2
+ * @param nbits   number of bits to decode
+ * @return        integer decoded from bits
+ */
+int ternary_from_bits(int *bits, int nbits);
+
 #ifdef __cplusplus
 }
 #endif
 
-#endif  /* __CROS_EC_UTIL_H */
+#endif /* __CROS_EC_UTIL_H */
diff --git a/include/vb21_struct.h b/include/vb21_struct.h
index 74d0ea3ad2..b23eb0cd30 100644
--- a/include/vb21_struct.h
+++ b/include/vb21_struct.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -14,10 +14,10 @@
 
 #ifndef VBOOT_REFERENCE_VB21_STRUCT_H_
 #define VBOOT_REFERENCE_VB21_STRUCT_H_
-#include <stdint.h>
-
 #include "2id.h"
 
+#include <stdint.h>
+
 /*
  * Magic numbers used by vb21_struct_common.magic.
  *
@@ -28,25 +28,24 @@
  */
 enum vb21_struct_common_magic {
 	/* "Vb2B" = vb21_keyblock.c.magic */
-	VB21_MAGIC_KEYBLOCK		= 0x42326256,
+	VB21_MAGIC_KEYBLOCK = 0x42326256,
 
 	/* "Vb2F" = vb21_fw_preamble.c.magic */
-	VB21_MAGIC_FW_PREAMBLE		= 0x46326256,
+	VB21_MAGIC_FW_PREAMBLE = 0x46326256,
 
 	/* "Vb2I" = vb21_packed_private_key.c.magic */
-	VB21_MAGIC_PACKED_PRIVATE_KEY	= 0x49326256,
+	VB21_MAGIC_PACKED_PRIVATE_KEY = 0x49326256,
 
 	/* "Vb2K" = vb2_kernel_preamble.c.magic */
-	VB21_MAGIC_KERNEL_PREAMBLE	= 0x4b326256,
+	VB21_MAGIC_KERNEL_PREAMBLE = 0x4b326256,
 
 	/* "Vb2P" = vb21_packed_key.c.magic */
-	VB21_MAGIC_PACKED_KEY		= 0x50326256,
+	VB21_MAGIC_PACKED_KEY = 0x50326256,
 
 	/* "Vb2S" = vb21_signature.c.magic */
-	VB21_MAGIC_SIGNATURE		= 0x53326256,
+	VB21_MAGIC_SIGNATURE = 0x53326256,
 };
 
-
 /*
  * Generic struct header for all vboot2.1 structs.  This makes it easy to
  * automatically parse and identify vboot structs (e.g., in futility).  This
@@ -145,7 +144,7 @@ struct vb21_packed_key {
 	struct vb2_id id;
 } __attribute__((packed));
 
-#define EXPECTED_VB21_PACKED_KEY_SIZE					\
+#define EXPECTED_VB21_PACKED_KEY_SIZE \
 	(EXPECTED_VB21_STRUCT_COMMON_SIZE + 16 + EXPECTED_ID_SIZE)
 
 /* Current version of vb21_packed_private_key struct */
@@ -184,7 +183,7 @@ struct vb21_packed_private_key {
 	struct vb2_id id;
 } __attribute__((packed));
 
-#define EXPECTED_VB21_PACKED_PRIVATE_KEY_SIZE				\
+#define EXPECTED_VB21_PACKED_PRIVATE_KEY_SIZE \
 	(EXPECTED_VB21_STRUCT_COMMON_SIZE + 12 + EXPECTED_ID_SIZE)
 
 /* Current version of vb21_signature struct */
@@ -232,10 +231,9 @@ struct vb21_signature {
 	struct vb2_id id;
 } __attribute__((packed));
 
-#define EXPECTED_VB21_SIGNATURE_SIZE					\
+#define EXPECTED_VB21_SIGNATURE_SIZE \
 	(EXPECTED_VB21_STRUCT_COMMON_SIZE + 16 + EXPECTED_ID_SIZE)
 
-
 /* Current version of vb21_keyblock struct */
 #define VB21_KEYBLOCK_VERSION_MAJOR 3
 #define VB21_KEYBLOCK_VERSION_MINOR 0
@@ -290,7 +288,6 @@ struct vb21_keyblock {
 
 #define EXPECTED_VB21_KEYBLOCK_SIZE (EXPECTED_VB21_STRUCT_COMMON_SIZE + 16)
 
-
 /* Current version of vb21_fw_preamble struct */
 #define VB21_FW_PREAMBLE_VERSION_MAJOR 3
 #define VB21_FW_PREAMBLE_VERSION_MINOR 0
@@ -343,4 +340,4 @@ struct vb21_fw_preamble {
 
 #define EXPECTED_VB21_FW_PREAMBLE_SIZE (EXPECTED_VB21_STRUCT_COMMON_SIZE + 20)
 
-#endif  /* VBOOT_REFERENCE_VB21_STRUCT_H_ */
+#endif /* VBOOT_REFERENCE_VB21_STRUCT_H_ */
diff --git a/include/vboot.h b/include/vboot.h
index 9c09e1aba2..9a3013ebbc 100644
--- a/include/vboot.h
+++ b/include/vboot.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,11 +7,11 @@
 #define __CROS_EC_INCLUDE_VBOOT_H
 
 #include "common.h"
-#include "vb21_struct.h"
 #include "rsa.h"
 #include "sha256.h"
 #include "stdbool.h"
 #include "timer.h"
+#include "vb21_struct.h"
 
 /**
  * Validate key contents.
@@ -31,7 +31,6 @@ int vb21_is_packed_key_valid(const struct vb21_packed_key *key);
 int vb21_is_signature_valid(const struct vb21_signature *sig,
 			    const struct vb21_packed_key *key);
 
-
 /**
  * Returns the public key in RO that was used to sign RW.
  *
@@ -58,8 +57,8 @@ int vboot_is_padding_valid(const uint8_t *data, uint32_t start, uint32_t end);
  * @param sig  Signature of <data>
  * @return EC_SUCCESS or EC_ERROR_*
  */
-int vboot_verify(const uint8_t *data, int len,
-		 const struct rsa_public_key *key, const uint8_t *sig);
+int vboot_verify(const uint8_t *data, int len, const struct rsa_public_key *key,
+		 const uint8_t *sig);
 
 /**
  * Entry point of EC EFS
@@ -87,6 +86,11 @@ __override_proto void show_critical_error(void);
  */
 __override_proto void show_power_shortage(void);
 
+/*
+ * Board level packet mode enable function.
+ */
+__override_proto void board_enable_packet_mode(bool enable);
+
 /**
  * Interrupt handler for packet mode entry.
  *
@@ -95,19 +99,19 @@ __override_proto void show_power_shortage(void);
 void packet_mode_interrupt(enum gpio_signal signal);
 
 /* Maximum number of times EC retries packet transmission before giving up. */
-#define CR50_COMM_MAX_RETRY	5
+#define CR50_COMM_MAX_RETRY 5
 
 /* EC's timeout for packet transmission to Cr50. */
-#define CR50_COMM_TIMEOUT	(50 * MSEC)
+#define CR50_COMM_TIMEOUT (50 * MSEC)
 
 /* Preamble character repeated before the packet header starts. */
-#define CR50_COMM_PREAMBLE	0xec
+#define CR50_COMM_PREAMBLE 0xec
 
 /* Magic characters used to identify ec-cr50-comm packets */
-#define CR50_PACKET_MAGIC	0x4345	/* 'EC' in little endian */
+#define CR50_PACKET_MAGIC 0x4345 /* 'EC' in little endian */
 
 /* version of struct cr50_comm_request */
-#define CR50_COMM_PACKET_VERSION	(0 << 4 | 0 << 0)	/* 0.0 */
+#define CR50_COMM_PACKET_VERSION (0 << 4 | 0 << 0) /* 0.0 */
 
 /**
  * EC-Cr50 data frame looks like the following:
@@ -120,11 +124,11 @@ void packet_mode_interrupt(enum gpio_signal signal);
  */
 struct cr50_comm_request {
 	/* Header */
-	uint16_t magic;		/* CR50_PACKET_MAGIC */
-	uint8_t struct_version;	/* version of this struct msb:lsb=major:minor */
-	uint8_t crc;		/* checksum computed from all bytes after crc */
-	uint16_t type;		/* CR50_CMD_* */
-	uint8_t size;		/* Payload size. Be easy on Cr50 buffer. */
+	uint16_t magic; /* CR50_PACKET_MAGIC */
+	uint8_t struct_version; /* version of this struct msb:lsb=major:minor */
+	uint8_t crc; /* checksum computed from all bytes after crc */
+	uint16_t type; /* CR50_CMD_* */
+	uint8_t size; /* Payload size. Be easy on Cr50 buffer. */
 	/* Payload */
 	uint8_t data[];
 } __packed;
@@ -133,33 +137,33 @@ struct cr50_comm_response {
 	uint16_t error;
 } __packed;
 
-#define CR50_COMM_MAX_REQUEST_SIZE	(sizeof(struct cr50_comm_request) \
-					 + UINT8_MAX)
-#define CR50_UART_RX_BUFFER_SIZE	32	/* TODO: Get from Cr50 header */
+#define CR50_COMM_MAX_REQUEST_SIZE \
+	(sizeof(struct cr50_comm_request) + UINT8_MAX)
+#define CR50_UART_RX_BUFFER_SIZE 32 /* TODO: Get from Cr50 header */
 
 /* commands */
 enum cr50_comm_cmd {
-	CR50_COMM_CMD_HELLO =		0x0000,
-	CR50_COMM_CMD_SET_BOOT_MODE =	0x0001,
-	CR50_COMM_CMD_VERIFY_HASH =	0x0002,
-	CR50_COMM_CMD_LIMIT =		0xffff,
+	CR50_COMM_CMD_HELLO = 0x0000,
+	CR50_COMM_CMD_SET_BOOT_MODE = 0x0001,
+	CR50_COMM_CMD_VERIFY_HASH = 0x0002,
+	CR50_COMM_CMD_LIMIT = 0xffff,
 } __packed;
 BUILD_ASSERT(sizeof(enum cr50_comm_cmd) == sizeof(uint16_t));
 
-#define CR50_COMM_ERR_PREFIX		0xec
+#define CR50_COMM_ERR_PREFIX 0xec
 
 /* return code */
 enum cr50_comm_err {
-	CR50_COMM_SUCCESS =		0xec00,
-	CR50_COMM_ERR_UNKNOWN =		0xec01,
-	CR50_COMM_ERR_MAGIC =		0xec02,
-	CR50_COMM_ERR_CRC =		0xec03,
-	CR50_COMM_ERR_SIZE =		0xec04,
-	CR50_COMM_ERR_TIMEOUT =		0xec05,	/* Generated by EC */
-	CR50_COMM_ERR_UNDEFINED_CMD =	0xec06,
-	CR50_COMM_ERR_BAD_PAYLOAD =	0xec07,
-	CR50_COMM_ERR_STRUCT_VERSION =	0xec08,
-	CR50_COMM_ERR_NVMEM =		0xec09,
+	CR50_COMM_SUCCESS = 0xec00,
+	CR50_COMM_ERR_UNKNOWN = 0xec01,
+	CR50_COMM_ERR_MAGIC = 0xec02,
+	CR50_COMM_ERR_CRC = 0xec03,
+	CR50_COMM_ERR_SIZE = 0xec04,
+	CR50_COMM_ERR_TIMEOUT = 0xec05, /* Generated by EC */
+	CR50_COMM_ERR_UNDEFINED_CMD = 0xec06,
+	CR50_COMM_ERR_BAD_PAYLOAD = 0xec07,
+	CR50_COMM_ERR_STRUCT_VERSION = 0xec08,
+	CR50_COMM_ERR_NVMEM = 0xec09,
 } __packed;
 BUILD_ASSERT(sizeof(enum cr50_comm_err) == sizeof(uint16_t));
 
@@ -168,8 +172,8 @@ BUILD_ASSERT(sizeof(enum cr50_comm_err) == sizeof(uint16_t));
  * BIT(0) : RECOVERY flag
  */
 enum boot_mode {
-	BOOT_MODE_NORMAL           = 0x00,
-	BOOT_MODE_NO_BOOT          = 0x01,
+	BOOT_MODE_NORMAL = 0x00,
+	BOOT_MODE_NO_BOOT = 0x01,
 } __packed;
 BUILD_ASSERT(sizeof(enum boot_mode) == sizeof(uint8_t));
 
@@ -182,4 +186,11 @@ BUILD_ASSERT(sizeof(enum boot_mode) == sizeof(uint8_t));
  */
 __override_proto bool vboot_allow_usb_pd(void);
 
-#endif  /* __CROS_EC_INCLUDE_VBOOT_H */
+#ifdef TEST_BUILD
+/**
+ * Set the vboot_allow_usb_pd flag to false.
+ */
+__test_only void vboot_disable_pd(void);
+#endif
+
+#endif /* __CROS_EC_INCLUDE_VBOOT_H */
diff --git a/include/vboot_hash.h b/include/vboot_hash.h
index 126872393e..32deb532b3 100644
--- a/include/vboot_hash.h
+++ b/include/vboot_hash.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,6 +27,15 @@
  */
 int vboot_get_rw_hash(const uint8_t **dst);
 
+/**
+ * @brief Computes the hash of the RO image. This blocks until the hash is
+ *        ready.
+ *
+ * @param dst	(OUT) Address where computed hash is stored.
+ * @return	enum ec_error_list.
+ */
+int vboot_get_ro_hash(const uint8_t **dst);
+
 /**
  * Invalidate the hash if the hashed data overlaps the specified region.
  *
@@ -49,4 +58,4 @@ int vboot_hash_in_progress(void);
  */
 void vboot_hash_abort(void);
 
-#endif  /* __CROS_EC_VBOOT_HASH_H */
+#endif /* __CROS_EC_VBOOT_HASH_H */
diff --git a/include/vec3.h b/include/vec3.h
index e7fcf92041..ebdb358cc1 100644
--- a/include/vec3.h
+++ b/include/vec3.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -80,4 +80,4 @@ fp_t fpv3_norm_squared(const fpv3_t v);
  */
 fp_t fpv3_norm(const fpv3_t v);
 
-#endif  /* __CROS_EC_VEC_3_H */
+#endif /* __CROS_EC_VEC_3_H */
diff --git a/include/vec4.h b/include/vec4.h
index b35431c098..e951c0542f 100644
--- a/include/vec4.h
+++ b/include/vec4.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,5 +12,4 @@
 typedef float floatv4_t[4];
 typedef fp_t fpv4_t[4];
 
-#endif  /* __CROS_EC_VEC_4_H */
-
+#endif /* __CROS_EC_VEC_4_H */
diff --git a/include/version.h b/include/version.h
deleted file mode 100644
index 0d3e777dc5..0000000000
--- a/include/version.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Version number for Chrome EC */
-
-#ifndef __CROS_EC_VERSION_H
-#define __CROS_EC_VERSION_H
-
-#include "common.h"
-#include "system.h"
-
-#define CROS_EC_IMAGE_DATA_COOKIE1 0xce778899
-#define CROS_EC_IMAGE_DATA_COOKIE2 0xceaabbdd
-
-struct image_data {
-	uint32_t cookie1;
-	char version[32];
-	uint32_t size;
-	int32_t rollback_version;
-	uint32_t cookie2;
-} __packed;
-
-extern const struct image_data current_image_data;
-extern const char build_info[];
-extern const char __image_data_offset[];
-extern const void *__image_size;
-
-/**
- * Get the number of commits of an image
- *
- * @return Number of commits in integer or 0 on error
- */
-int ver_get_num_commits(enum ec_image copy);
-#endif  /* __CROS_EC_VERSION_H */
diff --git a/include/virtual_battery.h b/include/virtual_battery.h
index 4e7ca31d05..2bd171f43c 100644
--- a/include/virtual_battery.h
+++ b/include/virtual_battery.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,8 @@
 #ifndef __CROS_EC_VIRTUAL_BATTERY_H
 #define __CROS_EC_VIRTUAL_BATTERY_H
 
-#if defined(CONFIG_I2C_VIRTUAL_BATTERY) && defined(CONFIG_BATTERY_SMART)
+#if defined(CONFIG_I2C_VIRTUAL_BATTERY) && defined(CONFIG_BATTERY_SMART) && \
+	!defined(VIRTUAL_BATTERY_ADDR_FLAGS)
 #define VIRTUAL_BATTERY_ADDR_FLAGS BATTERY_ADDR_FLAGS
 #endif
 
@@ -20,10 +21,8 @@
  * @return EC_SUCCESS if successful, non-zero if error.
  *
  */
-int virtual_battery_operation(const uint8_t *batt_cmd_head,
-			      uint8_t *dest,
-			      int read_len,
-			      int write_len);
+int virtual_battery_operation(const uint8_t *batt_cmd_head, uint8_t *dest,
+			      int read_len, int write_len);
 
 /**
  * Parse a command for virtual battery function.
@@ -38,10 +37,9 @@ int virtual_battery_operation(const uint8_t *batt_cmd_head,
  * @param out		Data to send
  * @return EC_SUCCESS if successful, non-zero if error.
  */
-int virtual_battery_handler(struct ec_response_i2c_passthru *resp,
-				   int in_len, int *err_code, int xferflags,
-				   int read_len, int write_len,
-				   const uint8_t *out);
+int virtual_battery_handler(struct ec_response_i2c_passthru *resp, int in_len,
+			    int *err_code, int xferflags, int read_len,
+			    int write_len, const uint8_t *out);
 
 /* Reset the state machine and static variables. */
 void reset_parse_state(void);
diff --git a/include/vstore.h b/include/vstore.h
new file mode 100644
index 0000000000..692d0e3012
--- /dev/null
+++ b/include/vstore.h
@@ -0,0 +1,16 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_VSTORE_H
+#define __CROS_EC_VSTORE_H
+
+#ifdef TEST_BUILD
+
+/* Clear all vstore locks */
+void vstore_clear_lock(void);
+
+#endif /* TEST_BUILD */
+
+#endif /* __CROS_EC_VSTORE_H */
diff --git a/include/watchdog.h b/include/watchdog.h
index 036f722d97..5e6e5626e6 100644
--- a/include/watchdog.h
+++ b/include/watchdog.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,10 +8,10 @@
 #ifndef __CROS_EC_WATCHDOG_H
 #define __CROS_EC_WATCHDOG_H
 
-#include <stdint.h>
-
 #include "config.h"
 
+#include <stdint.h>
+
 /**
  * Initialize the watchdog.
  *
@@ -49,7 +49,9 @@ void watchdog_stop_and_unlock(void);
 #ifdef CONFIG_WATCHDOG
 void watchdog_reload(void);
 #else
-static inline void watchdog_reload(void) { }
+test_mockable_static_inline void watchdog_reload(void)
+{
+}
 #endif
 
 #endif /* __CROS_EC_WATCHDOG_H */
diff --git a/include/wireless.h b/include/wireless.h
index d209d69fed..7232f92763 100644
--- a/include/wireless.h
+++ b/include/wireless.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,11 +11,7 @@
 #include "common.h"
 
 /* Wireless power state for wireless_set_state() */
-enum wireless_power_state {
-	WIRELESS_OFF,
-	WIRELESS_SUSPEND,
-	WIRELESS_ON
-};
+enum wireless_power_state { WIRELESS_OFF, WIRELESS_SUSPEND, WIRELESS_ON };
 
 /**
  * Set wireless power state.
@@ -23,7 +19,9 @@ enum wireless_power_state {
 #ifdef CONFIG_WIRELESS
 void wireless_set_state(enum wireless_power_state state);
 #else
-static inline void wireless_set_state(enum wireless_power_state state) { }
+static inline void wireless_set_state(enum wireless_power_state state)
+{
+}
 #endif
 
-#endif  /* __CROS_EC_WIRELESS_H */
+#endif /* __CROS_EC_WIRELESS_H */
diff --git a/include/write_protect.h b/include/write_protect.h
new file mode 100644
index 0000000000..8e09111974
--- /dev/null
+++ b/include/write_protect.h
@@ -0,0 +1,51 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_WRITE_PROTECT_H
+#define __CROS_EC_WRITE_PROTECT_H
+
+#ifdef CONFIG_ZEPHYR
+#include "zephyr_write_protect.h"
+#else
+#include "gpio.h"
+
+static inline bool write_protect_is_asserted(void)
+{
+#ifdef CONFIG_WP_ALWAYS
+	return true;
+#elif defined(CONFIG_WP_ACTIVE_HIGH)
+	return gpio_get_level(GPIO_WP);
+#else
+	return !gpio_get_level(GPIO_WP_L);
+#endif
+}
+
+static inline int write_protect_enable_interrupt(void)
+{
+#ifdef CONFIG_WP_ACTIVE_HIGH
+	return gpio_enable_interrupt(GPIO_WP);
+#else
+	return gpio_enable_interrupt(GPIO_WP_L);
+#endif
+}
+
+#ifdef TEST_BUILD
+/**
+ * Set the WP state.
+ *
+ * @param value		Logical level of the WP pin
+ */
+static inline void write_protect_set(int value)
+{
+#ifdef CONFIG_WP_ACTIVE_HIGH
+	gpio_set_level(GPIO_WP, value);
+#else
+	gpio_set_level(GPIO_WP_L, !value);
+#endif /* CONFIG_WP_ACTIVE_HIGH */
+}
+#endif /* TEST_BUILD */
+
+#endif /* !CONFIG_ZEPHYR */
+#endif /* __CROS_EC_WRITE_PROTECT_H */
diff --git a/libc/build.mk b/libc/build.mk
new file mode 100644
index 0000000000..594f3061d6
--- /dev/null
+++ b/libc/build.mk
@@ -0,0 +1,5 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+libc-y=syscalls.o
diff --git a/libc/syscalls.c b/libc/syscalls.c
new file mode 100644
index 0000000000..1c13e9915d
--- /dev/null
+++ b/libc/syscalls.c
@@ -0,0 +1,125 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ *@brief Provides implementations of syscalls needed by libc. The newlib
+ * documentation provides a list of the required syscalls:
+ * https://sourceware.org/newlib/libc.html#Syscalls and minimal implementations
+ * can be found in newlib's "nosys" library:
+ * https://sourceware.org/git/?p=newlib-cygwin.git;a=tree;f=libgloss/libnosys.
+ */
+
+#include "gettimeofday.h"
+#include "link_defs.h"
+#include "panic.h"
+#include "shared_mem.h"
+#include "software_panic.h"
+#include "system.h"
+#include "task.h"
+#include "uart.h"
+
+#include <errno.h>
+
+#include <sys/stat.h>
+
+/**
+ * Reboot the system.
+ *
+ * This function is called from libc functions such as abort() or exit().
+ *
+ * @param rc exit code
+ */
+void _exit(int rc)
+{
+	panic_printf("%s called with rc: %d\n", __func__, rc);
+	software_panic(PANIC_SW_EXIT, task_get_current());
+}
+
+/**
+ * Write to the UART.
+ *
+ * This function is called from libc functions such as printf().
+ *
+ * @param fd  ignored
+ * @param buf buffer to write
+ * @param len number of bytes in @buf to write
+ * @return number of bytes successfully written
+ */
+int _write(int fd, char *buf, int len)
+{
+	return uart_put(buf, len);
+}
+
+/**
+ * Create a directory.
+ *
+ * @warning Not implemented.
+ *
+ * @note Unlike the other functions in this file, this is not overriding a
+ * stub version in libnosys. There's no "_mkdir" stub in libnosys, so this
+ * provides the actual "mkdir" function.
+ *
+ * @param pathname directory to create
+ * @param mode mode for the new directory
+ * @return -1 (error) always
+ */
+int mkdir(const char *pathname, mode_t mode)
+{
+	errno = ENOSYS;
+	return -1;
+}
+
+/**
+ * Get the time.
+ *
+ * This function is called from the libc gettimeofday() function.
+ *
+ * @warning This does not match gettimeofday() exactly; it does not return the
+ * time since the Unix Epoch.
+ *
+ * @param[out] tv time
+ * @param[in] tz ignored
+ * @return 0 on success
+ * @return -1 on error (errno is set to indicate error)
+ */
+int _gettimeofday(struct timeval *restrict tv, void *restrict tz)
+{
+	enum ec_error_list ret = ec_gettimeofday(tv, tz);
+
+	if (ret == EC_ERROR_INVAL) {
+		errno = EFAULT;
+		return -1;
+	}
+
+	return 0;
+}
+
+/**
+ * Change program's data space by increment bytes.
+ *
+ * This function is called from the libc sbrk() function (which is in turn
+ * called from malloc() when memory needs to be allocated or released).
+ *
+ * @param incr[in] amount to increment or decrement. 0 means return current
+ * program break.
+ * @return the previous program break (address) on success
+ * @return (void*)-1 on error and errno is set to ENOMEM.
+ */
+void *_sbrk(intptr_t incr)
+{
+	static char *heap_end = __shared_mem_buf;
+	char *prev_heap_end;
+
+	if ((heap_end + incr < __shared_mem_buf) ||
+	    (heap_end + incr > (__shared_mem_buf + shared_mem_size()))) {
+		errno = ENOMEM;
+		return (void *)-1;
+	}
+
+	prev_heap_end = heap_end;
+	heap_end += incr;
+
+	return (void *)prev_heap_end;
+}
diff --git a/navbar.md b/navbar.md
index 4564552a64..f4809aa3be 100644
--- a/navbar.md
+++ b/navbar.md
@@ -1,11 +1,11 @@
 # CrOS EC (Embedded Controller)
 
-[logo]: https://chromium-review.googlesource.com/plugins/chromium-style/static/chromium_logo.png
+[logo]: https://chromium-review.googlesource.com/static/chromium_logo.png
 [home]: /README.md
 
-* [Home][home]
-* [Documentation](/docs/sitemap.md)
-* [Getting Started Quickly](/docs/getting_started_quickly.md)
-* [File a Bug](https://bugs.chromium.org/p/chromium/issues/entry?components=OS%3EFirmware%3EEC)
-* [Report Security Issue](https://chromium.googlesource.com/chromiumos/docs/+/master/reporting_bugs.md#security)
-* [Chromium OS Docs](https://chromium.googlesource.com/chromiumos/docs/+/master/README.md)
+*   [Home][home]
+*   [Documentation](/docs/sitemap.md)
+*   [Getting Started Quickly](/docs/getting_started_quickly.md)
+*   [File a Bug](https://issuetracker.google.com/issues/new?component=960650)
+*   [Report Security Issue](https://chromium.googlesource.com/chromiumos/docs/+/HEAD/reporting_bugs.md#security)
+*   [Chromium OS Docs](https://chromium.googlesource.com/chromiumos/docs/+/HEAD/README.md)
diff --git a/power/alderlake_slg4bd44540.c b/power/alderlake_slg4bd44540.c
new file mode 100644
index 0000000000..09ba6f01e6
--- /dev/null
+++ b/power/alderlake_slg4bd44540.c
@@ -0,0 +1,288 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * This was originally copied form power/icelake.c (also used on TGL and
+ * ADL) and adapted to support ADL designs using the Silergy SLG4BD44540
+ * power sequencer chip.
+ */
+
+#include "board_config.h"
+#include "chipset.h"
+#include "console.h"
+#include "gpio.h"
+#include "power.h"
+#include "power/alderlake_slg4bd44540.h"
+#include "power/intel_x86.h"
+#include "system_boot_time.h"
+#include "timer.h"
+
+/*
+ * These delays are used by the brya power sequence reference design and
+ * should be suitable for variants.
+ */
+
+/* PG_EC_ALL_SYS_PWRGD high to VCCST_PWRGD high delay */
+#define VCCST_PWRGD_DELAY_MS 2
+
+/* IMVP9_VRRDY high to PCH_PWROK high delay */
+#define PCH_PWROK_DELAY_MS 2
+
+/* PG_EC_ALL_SYS_PWRGD high to EC_PCH_SYS_PWROK high delay */
+#define SYS_PWROK_DELAY_MS 45
+
+/* IMVP9_VRRDY high timeout */
+#define VRRDY_TIMEOUT_MS 50
+
+/* Console output macros */
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
+
+#ifdef CONFIG_BRINGUP
+#define GPIO_SET_LEVEL(signal, value) \
+	gpio_set_level_verbose(CC_CHIPSET, signal, value)
+#else
+#define GPIO_SET_LEVEL(signal, value) gpio_set_level(signal, value)
+#endif
+
+/* The wait time is ~150 msec, allow for safety margin. */
+#define IN_PCH_SLP_SUS_WAIT_TIME_USEC (250 * MSEC)
+
+#ifndef CONFIG_POWER_SIGNAL_RUNTIME_CONFIG
+const
+#endif /* !CONFIG_POWER_SIGNAL_RUNTIME_CONFIG */
+/* Power signals list. Must match order of enum power_signal. */
+struct power_signal_info power_signal_list[] = {
+	[X86_SLP_S0_DEASSERTED] = {
+		.gpio = GPIO_PCH_SLP_S0_L,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH |
+			POWER_SIGNAL_DISABLE_AT_BOOT,
+		.name = "SLP_S0_DEASSERTED",
+	},
+	[X86_SLP_S3_DEASSERTED] = {
+		.gpio = SLP_S3_SIGNAL_L,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "SLP_S3_DEASSERTED",
+	},
+	[X86_SLP_S4_DEASSERTED] = {
+		.gpio = (enum gpio_signal)SLP_S4_SIGNAL_L,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "SLP_S4_DEASSERTED",
+	},
+	[X86_SLP_S5_DEASSERTED] = {
+		.gpio = (enum gpio_signal)SLP_S5_SIGNAL_L,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "SLP_S5_DEASSERTED",
+	},
+	[X86_SLP_SUS_DEASSERTED] = {
+		.gpio = GPIO_SLP_SUS_L,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "SLP_SUS_DEASSERTED",
+	},
+	[X86_RSMRST_L_PGOOD] = {
+		.gpio = GPIO_PG_EC_RSMRST_ODL,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "RSMRST_L_PGOOD",
+	},
+	[X86_DSW_DPWROK] = {
+		.gpio = GPIO_PG_EC_DSW_PWROK,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "DSW_DPWROK",
+	},
+	[X86_ALL_SYS_PGOOD] = {
+		.gpio = GPIO_PG_EC_ALL_SYS_PWRGD,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "ALL_SYS_PWRGD",
+	},
+};
+
+BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
+
+__overridable int intel_x86_get_pg_ec_dsw_pwrok(void)
+{
+	return gpio_get_level(GPIO_PG_EC_DSW_PWROK);
+}
+
+__overridable int intel_x86_get_pg_ec_all_sys_pwrgd(void)
+{
+	return gpio_get_level(GPIO_PG_EC_ALL_SYS_PWRGD);
+}
+
+void chipset_force_shutdown(enum chipset_shutdown_reason reason)
+{
+	int timeout_ms = 50;
+
+	CPRINTS("%s() %d", __func__, reason);
+	report_ap_reset(reason);
+
+	/* Turn off RMSRST_L  to meet tPCH12 */
+	board_before_rsmrst(0);
+	GPIO_SET_LEVEL(GPIO_PCH_RSMRST_L, 0);
+	board_after_rsmrst(0);
+
+	/* Turn off S5 rails */
+	GPIO_SET_LEVEL(GPIO_EN_S5_RAILS, 0);
+
+	/*
+	 * TODO(b/179519791): Replace this wait with
+	 * power_wait_signals_timeout()
+	 */
+	/* Now wait for DSW_PWROK and  RSMRST_ODL to go away. */
+	while (intel_x86_get_pg_ec_dsw_pwrok() &&
+	       gpio_get_level(GPIO_PG_EC_RSMRST_ODL) && (timeout_ms > 0)) {
+		msleep(1);
+		timeout_ms--;
+	};
+
+	if (!timeout_ms)
+		CPRINTS("DSW_PWROK or RSMRST_ODL didn't go low!  Assuming G3.");
+}
+
+void chipset_handle_espi_reset_assert(void)
+{
+	/* No special handling needed. */
+}
+
+enum power_state chipset_force_g3(void)
+{
+	chipset_force_shutdown(CHIPSET_SHUTDOWN_G3);
+
+	return POWER_G3;
+}
+
+static void ap_off(void)
+{
+	GPIO_SET_LEVEL(GPIO_VCCST_PWRGD_OD, 0);
+	GPIO_SET_LEVEL(GPIO_PCH_PWROK, 0);
+	GPIO_SET_LEVEL(GPIO_EC_PCH_SYS_PWROK, 0);
+}
+
+/*
+ * We have asserted VCCST_PWRGO_OD, now wait for the IMVP9.1
+ * to assert IMVP9_VRRDY_OD.
+ *
+ * Returns state of VRRDY.
+ */
+
+static int wait_for_vrrdy(void)
+{
+	int timeout_ms = VRRDY_TIMEOUT_MS;
+	int vrrdy;
+
+	for (; timeout_ms > 0; --timeout_ms) {
+		vrrdy = gpio_get_level(GPIO_IMVP9_VRRDY_OD);
+		if (vrrdy != 0)
+			return 1;
+		msleep(1);
+	}
+	return 0;
+}
+
+/*
+ * The relationship between these signals is described in
+ * Intel PDG #627205 rev. 0.81.
+ *
+ * tCPU16: >= 0
+ *	VCCST_PWRGD to PCH_PWROK
+ * tPLT05: >= 0
+ *	SYS_ALL_PWRGD to SYS_PWROK
+ *	PCH_PWROK to SYS_PWROK
+ */
+
+static void all_sys_pwrgd_pass_thru(void)
+{
+	int sys_pg;
+	int vccst_pg;
+	int pch_pok;
+	int sys_pok;
+
+	sys_pg = intel_x86_get_pg_ec_all_sys_pwrgd();
+
+	if (IS_ENABLED(CONFIG_BRINGUP))
+		CPRINTS("PG_EC_ALL_SYS_PWRGD is %d", sys_pg);
+
+	if (sys_pg == 0) {
+		ap_off();
+		return;
+	}
+
+	/* PG_EC_ALL_SYS_PWRGD is asserted, enable VCCST_PWRGD_OD. */
+
+	vccst_pg = gpio_get_level(GPIO_VCCST_PWRGD_OD);
+	if (vccst_pg == 0) {
+		msleep(VCCST_PWRGD_DELAY_MS);
+		GPIO_SET_LEVEL(GPIO_VCCST_PWRGD_OD, 1);
+	}
+
+	/* Enable PCH_PWROK, gated by VRRDY. */
+
+	pch_pok = gpio_get_level(GPIO_PCH_PWROK);
+	if (pch_pok == 0) {
+		if (wait_for_vrrdy() == 0) {
+			CPRINTS("Timed out waiting for VRRDY, "
+				"shutting AP off!");
+			ap_off();
+			return;
+		}
+		msleep(PCH_PWROK_DELAY_MS);
+		GPIO_SET_LEVEL(GPIO_PCH_PWROK, 1);
+	}
+
+	/* Enable PCH_SYS_PWROK. */
+
+	sys_pok = gpio_get_level(GPIO_EC_PCH_SYS_PWROK);
+	if (sys_pok == 0) {
+		msleep(SYS_PWROK_DELAY_MS);
+		/* Check if we lost power while waiting. */
+		sys_pg = intel_x86_get_pg_ec_all_sys_pwrgd();
+		if (sys_pg == 0) {
+			CPRINTS("PG_EC_ALL_SYS_PWRGD deasserted, "
+				"shutting AP off!");
+			ap_off();
+			return;
+		}
+		GPIO_SET_LEVEL(GPIO_EC_PCH_SYS_PWROK, 1);
+		/* PCH will now release PLT_RST */
+	}
+}
+
+enum power_state power_handle_state(enum power_state state)
+{
+	all_sys_pwrgd_pass_thru();
+
+	common_intel_x86_handle_rsmrst(state);
+
+	switch (state) {
+	case POWER_G3S5:
+		GPIO_SET_LEVEL(GPIO_EN_S5_RAILS, 1);
+
+		update_ap_boot_time(ARAIL);
+
+		if (power_wait_signals(IN_PGOOD_ALL_CORE))
+			break;
+
+		/*
+		 * Now wait for SLP_SUS_L to go high based on tPCH32. If this
+		 * signal doesn't go high within 250 msec then go back to G3.
+		 */
+		if (power_wait_signals_timeout(IN_PCH_SLP_SUS_DEASSERTED,
+					       IN_PCH_SLP_SUS_WAIT_TIME_USEC) !=
+		    EC_SUCCESS) {
+			CPRINTS("SLP_SUS_L didn't go high!  Going back to G3.");
+			return POWER_S5G3;
+		}
+		break;
+
+	case POWER_S5:
+		/* If SLP_SUS_L is asserted, we're no longer in S5. */
+		if (!power_has_signals(IN_PCH_SLP_SUS_DEASSERTED))
+			return POWER_S5G3;
+		break;
+
+	default:
+		break;
+	}
+
+	return common_intel_x86_power_handle_state(state);
+}
diff --git a/power/amd_x86.c b/power/amd_x86.c
new file mode 100644
index 0000000000..db74d125ba
--- /dev/null
+++ b/power/amd_x86.c
@@ -0,0 +1,568 @@
+/* Copyright 2017 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* AMD x86 power sequencing module for Chrome EC */
+
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "driver/amd_stb.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "lid_switch.h"
+#include "lpc.h"
+#include "power.h"
+#include "power/amd_x86.h"
+#include "power_button.h"
+#include "registers.h"
+#include "system.h"
+#include "timer.h"
+#include "usb_charge.h"
+#include "util.h"
+#include "wireless.h"
+
+/* Console output macros */
+#define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
+
+#define IN_S5_PGOOD POWER_SIGNAL_MASK(X86_S5_PGOOD)
+
+static int forcing_shutdown; /* Forced shutdown in progress? */
+
+#ifdef CONFIG_POWERSEQ_FAKE_CONTROL
+/* Create fake power states through forcing the SoC SLP signal sequencing */
+void power_fake_s0(void)
+{
+	/* Change the SLP signals to output and drive them */
+	gpio_set_flags(GPIO_PCH_SLP_S5_L, GPIO_OUT_HIGH);
+	gpio_set_flags(GPIO_PCH_SLP_S3_L, GPIO_OUT_HIGH);
+}
+
+void power_fake_disable(void)
+{
+	/* Pins back to inputs */
+	gpio_set_flags(GPIO_PCH_SLP_S5_L, GPIO_INPUT);
+	gpio_set_flags(GPIO_PCH_SLP_S3_L, GPIO_INPUT);
+}
+#endif /* defined(CONFIG_POWERSEQ_FAKE_CONTROL) */
+
+void chipset_force_shutdown(enum chipset_shutdown_reason reason)
+{
+	CPRINTS("%s()", __func__);
+
+	if (!chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF)) {
+		forcing_shutdown = 1;
+		power_button_pch_press();
+		report_ap_reset(reason);
+	}
+}
+
+static void chipset_force_g3(void)
+{
+	/* Disable system power ("*_A" rails) in G3. */
+	gpio_set_level(GPIO_EN_PWR_A, 0);
+}
+
+void chipset_reset(enum chipset_shutdown_reason reason)
+{
+	CPRINTS("%s: %d", __func__, reason);
+
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
+		CPRINTS("Can't reset: SOC is off");
+		return;
+	}
+
+	if (IS_ENABLED(CONFIG_PLATFORM_EC_AMD_STB_DUMP) &&
+	    amd_stb_dump_in_progress()) {
+		CPRINTS("STB dump still in progress during reset");
+		amd_stb_dump_finish();
+	}
+
+	report_ap_reset(reason);
+	/*
+	 * Send a pulse to SYS_RST to trigger a warm reset.
+	 */
+	gpio_set_level(GPIO_SYS_RESET_L, 0);
+	usleep(32 * MSEC);
+	gpio_set_level(GPIO_SYS_RESET_L, 1);
+}
+
+void chipset_throttle_cpu(int throttle)
+{
+	CPRINTS("%s(%d)", __func__, throttle);
+	if (IS_ENABLED(CONFIG_CPU_PROCHOT_ACTIVE_LOW))
+		throttle = !throttle;
+
+	if (!chipset_in_state(CHIPSET_STATE_ON))
+		return;
+
+	if (IS_ENABLED(CONFIG_THROTTLE_AP_INTERRUPT_SINGLE)) {
+		if (throttle == IS_ENABLED(CONFIG_CPU_PROCHOT_ACTIVE_LOW)) {
+			/* Enable interrupt if we're not throttling the AP */
+			gpio_set_flags(GPIO_CPU_PROCHOT, GPIO_INPUT);
+			gpio_enable_interrupt(GPIO_CPU_PROCHOT);
+
+			if ((!gpio_get_level(GPIO_CPU_PROCHOT)) ==
+			    IS_ENABLED(CONFIG_CPU_PROCHOT_ACTIVE_LOW)) {
+				CPRINTS("External prochot during throttling");
+			}
+			return;
+		}
+
+		/* Otherwise restore our original GPIO settings */
+		gpio_disable_interrupt(GPIO_CPU_PROCHOT);
+		gpio_set_flags(GPIO_CPU_PROCHOT,
+			       gpio_get_default_flags(GPIO_CPU_PROCHOT));
+	}
+
+	gpio_set_level(GPIO_CPU_PROCHOT, throttle);
+}
+
+void chipset_handle_espi_reset_assert(void)
+{
+	/*
+	 * eSPI_Reset# pin being asserted without RSMRST# being asserted
+	 * means there is an unexpected power loss (global reset event).
+	 * In this case, check if the shutdown is forced by the EC (due
+	 * to battery, thermal, or console command). The forced shutdown
+	 * initiates a power button press that we need to release.
+	 *
+	 * NOTE: S5_PGOOD input is passed through to the RSMRST# output to
+	 * the AP.
+	 */
+	if ((power_get_signals() & IN_S5_PGOOD) && forcing_shutdown) {
+		power_button_pch_release();
+		forcing_shutdown = 0;
+	}
+}
+
+enum power_state power_chipset_init(void)
+{
+	CPRINTS("%s: power_signal=0x%x", __func__, power_get_signals());
+
+	if (!system_jumped_to_this_image())
+		return POWER_G3;
+	/*
+	 * We are here as RW. We need to handle the following cases:
+	 *
+	 * 1. Late sysjump by software sync. AP is in S0.
+	 * 2. Shutting down in recovery mode then sysjump by EFS2. AP is in S5
+	 *    and expected to sequence down.
+	 * 3. Rebooting from recovery mode then sysjump by EFS2. AP is in S5
+	 *    and expected to sequence up.
+	 * 4. RO jumps to RW from main() by EFS2. (a.k.a. power on reset, cold
+	 *    reset). AP is in G3.
+	 */
+	if (gpio_get_level(GPIO_S0_PGOOD)) {
+		/* case #1. Disable idle task deep sleep when in S0. */
+		disable_sleep(SLEEP_MASK_AP_RUN);
+		CPRINTS("already in S0");
+		return POWER_S0;
+	}
+	if (power_get_signals() & IN_S5_PGOOD) {
+		/* case #2 & #3 */
+		CPRINTS("already in S5");
+		return POWER_S5;
+	}
+	/* case #4 */
+	chipset_force_g3();
+	return POWER_G3;
+}
+
+static void handle_pass_through(enum gpio_signal pin_in,
+				enum gpio_signal pin_out)
+{
+	/*
+	 * Pass through asynchronously, as SOC may not react
+	 * immediately to power changes.
+	 */
+	int in_level = gpio_get_level(pin_in);
+	int out_level = gpio_get_level(pin_out);
+
+	/*
+	 * Only pass through high S0_PGOOD (S0 power) when S5_PGOOD (S5 power)
+	 * is also high (S0_PGOOD is pulled high in G3 when S5_PGOOD is low).
+	 */
+	if ((pin_in == GPIO_S0_PGOOD) && !gpio_get_level(GPIO_S5_PGOOD))
+		in_level = 0;
+
+	/* Nothing to do. */
+	if (in_level == out_level)
+		return;
+
+	/*
+	 * SOC requires a delay of 1ms with stable power before
+	 * asserting PWR_GOOD.
+	 */
+	if ((pin_in == GPIO_S0_PGOOD) && in_level)
+		msleep(1);
+
+	if (IS_ENABLED(CONFIG_CHIPSET_X86_RSMRST_DELAY) &&
+	    (pin_out == GPIO_PCH_RSMRST_L) && in_level)
+		msleep(10);
+
+	gpio_set_level(pin_out, in_level);
+
+	CPRINTS("Pass through %s: %d", gpio_get_name(pin_in), in_level);
+}
+
+#ifdef CONFIG_POWER_S0IX
+/*
+ * Backup copies of SCI and SMI mask to preserve across S0ix suspend/resume
+ * cycle. If the host uses S0ix, BIOS is not involved during suspend and resume
+ * operations and hence SCI/SMI masks are programmed only once during boot-up.
+ *
+ * These backup variables are set whenever host expresses its interest to
+ * enter S0ix and then lpc_host_event_mask for SCI and SMI are cleared. When
+ * host resumes from S0ix, masks from backup variables are copied over to
+ * lpc_host_event_mask for SCI and SMI.
+ */
+static host_event_t backup_sci_mask;
+static host_event_t backup_smi_mask;
+
+/*
+ * Clear host event masks for SMI and SCI when host is entering S0ix. This is
+ * done to prevent any SCI/SMI interrupts when the host is in suspend. Since
+ * BIOS is not involved in the suspend path, EC needs to take care of clearing
+ * these masks.
+ */
+static void lpc_s0ix_suspend_clear_masks(void)
+{
+	backup_sci_mask = lpc_get_host_event_mask(LPC_HOST_EVENT_SCI);
+	backup_smi_mask = lpc_get_host_event_mask(LPC_HOST_EVENT_SMI);
+
+	lpc_set_host_event_mask(LPC_HOST_EVENT_SCI, 0);
+	lpc_set_host_event_mask(LPC_HOST_EVENT_SMI, 0);
+}
+
+/*
+ * Restore host event masks for SMI and SCI when host exits S0ix. This is done
+ * because BIOS is not involved in the resume path and so EC needs to restore
+ * the masks from backup variables.
+ */
+static void lpc_s0ix_resume_restore_masks(void)
+{
+	/*
+	 * No need to restore SCI/SMI masks if both backup_sci_mask and
+	 * backup_smi_mask are zero. This indicates that there was a failure to
+	 * enter S0ix(SLP_S0# assertion) and hence SCI/SMI masks were never
+	 * backed up.
+	 */
+	if (!backup_sci_mask && !backup_smi_mask)
+		return;
+
+	lpc_set_host_event_mask(LPC_HOST_EVENT_SCI, backup_sci_mask);
+	lpc_set_host_event_mask(LPC_HOST_EVENT_SMI, backup_smi_mask);
+
+	backup_sci_mask = backup_smi_mask = 0;
+}
+
+__override void power_chipset_handle_sleep_hang(enum sleep_hang_type hang_type)
+{
+	/*
+	 * Wake up the AP so they don't just chill in a non-suspended state and
+	 * burn power. Overload a vaguely related event bit since event bits are
+	 * at a premium. If the system never entered S0ix, then manually set the
+	 * wake mask to pretend it did, so that the hang detect event wakes the
+	 * system.
+	 */
+	if (power_get_state() == POWER_S0) {
+		host_event_t sleep_wake_mask;
+
+		get_lazy_wake_mask(POWER_S0ix, &sleep_wake_mask);
+		lpc_set_host_event_mask(LPC_HOST_EVENT_WAKE, sleep_wake_mask);
+	}
+
+	if (IS_ENABLED(CONFIG_PLATFORM_EC_AMD_STB_DUMP))
+		amd_stb_dump_trigger();
+
+	CPRINTS("Warning: Detected sleep hang! Waking host up!");
+	host_set_single_event(EC_HOST_EVENT_HANG_DETECT);
+}
+
+static void handle_chipset_reset(void)
+{
+	if (chipset_in_state(CHIPSET_STATE_STANDBY)) {
+		CPRINTS("chipset reset: exit s0ix");
+		power_reset_host_sleep_state();
+		task_wake(TASK_ID_CHIPSET);
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESET, handle_chipset_reset, HOOK_PRIO_FIRST);
+
+void power_reset_host_sleep_state(void)
+{
+	power_set_host_sleep_state(HOST_SLEEP_EVENT_DEFAULT_RESET);
+	sleep_reset_tracking();
+	power_chipset_handle_host_sleep_event(HOST_SLEEP_EVENT_DEFAULT_RESET,
+					      NULL);
+}
+
+#endif /* CONFIG_POWER_S0IX */
+
+#ifdef CONFIG_POWER_TRACK_HOST_SLEEP_STATE
+
+__overridable void
+power_board_handle_host_sleep_event(enum host_sleep_event state)
+{
+	/* Default weak implementation -- no action required. */
+}
+
+__override void
+power_chipset_handle_host_sleep_event(enum host_sleep_event state,
+				      struct host_sleep_event_context *ctx)
+{
+	power_board_handle_host_sleep_event(state);
+
+#ifdef CONFIG_POWER_S0IX
+	if (state == HOST_SLEEP_EVENT_S0IX_SUSPEND) {
+		/*
+		 * Clear event mask for SMI and SCI first to avoid host being
+		 * interrupted while suspending.
+		 */
+		lpc_s0ix_suspend_clear_masks();
+		/*
+		 * Indicate to power state machine that a new host event for
+		 * s0ix/s3 suspend has been received and so chipset suspend
+		 * notification needs to be sent to listeners.
+		 */
+		sleep_set_notify(SLEEP_NOTIFY_SUSPEND);
+
+		sleep_start_suspend(ctx);
+	} else if (state == HOST_SLEEP_EVENT_S0IX_RESUME) {
+		/*
+		 * Wake up chipset task and indicate to power state machine that
+		 * listeners need to be notified of chipset resume.
+		 */
+		sleep_set_notify(SLEEP_NOTIFY_RESUME);
+		task_wake(TASK_ID_CHIPSET);
+		lpc_s0ix_resume_restore_masks();
+		sleep_complete_resume(ctx);
+		/*
+		 * If the sleep signal timed out and never transitioned, then
+		 * the wake mask was modified to its suspend state (S0ix), so
+		 * that the event wakes the system. Explicitly restore the wake
+		 * mask to its S0 state now.
+		 */
+		power_update_wake_mask();
+	}
+#endif /* CONFIG_POWER_S0IX */
+}
+#endif /* CONFIG_POWER_TRACK_HOST_SLEEP_STATE */
+
+enum power_state power_handle_state(enum power_state state)
+{
+	handle_pass_through(GPIO_S5_PGOOD, GPIO_PCH_RSMRST_L);
+
+	handle_pass_through(GPIO_S0_PGOOD, GPIO_PCH_SYS_PWROK);
+
+	if (state == POWER_S5 && forcing_shutdown) {
+		power_button_pch_release();
+		forcing_shutdown = 0;
+	}
+
+	switch (state) {
+	case POWER_G3:
+		break;
+
+	case POWER_G3S5:
+		/* Exit SOC G3 */
+		/* Enable system power ("*_A" rails) in S5. */
+		gpio_set_level(GPIO_EN_PWR_A, 1);
+
+		/*
+		 * Callback to do pre-initialization within the context of
+		 * chipset task.
+		 */
+		if (IS_ENABLED(CONFIG_CHIPSET_HAS_PRE_INIT_CALLBACK))
+			chipset_pre_init_callback();
+
+		if (power_wait_signals(IN_S5_PGOOD)) {
+			chipset_force_g3();
+			return POWER_G3;
+		}
+
+		CPRINTS("Exit SOC G3");
+
+		return POWER_S5;
+
+	case POWER_S5:
+		if (!power_has_signals(IN_S5_PGOOD)) {
+			/* Required rail went away */
+			return POWER_S5G3;
+		} else if (gpio_get_level(GPIO_PCH_SLP_S5_L) == 1) {
+			/* Power up to next state */
+			return POWER_S5S3;
+		}
+		break;
+
+	case POWER_S5S3:
+		if (!power_has_signals(IN_S5_PGOOD)) {
+			/* Required rail went away */
+			return POWER_S5G3;
+		}
+
+		/* Call hooks now that rails are up */
+		hook_notify(HOOK_CHIPSET_STARTUP);
+
+#ifdef CONFIG_POWER_S0IX
+		/*
+		 * Clearing the S0ix flag on the path to S0
+		 * to handle any reset conditions.
+		 */
+		power_reset_host_sleep_state();
+#endif
+		return POWER_S3;
+
+	case POWER_S3:
+		if (!power_has_signals(IN_S5_PGOOD)) {
+			/* Required rail went away */
+			return POWER_S5G3;
+		} else if (gpio_get_level(GPIO_PCH_SLP_S3_L) == 1) {
+			/* Power up to next state */
+			return POWER_S3S0;
+		} else if (gpio_get_level(GPIO_PCH_SLP_S5_L) == 0) {
+			/* Power down to next state */
+			return POWER_S3S5;
+		}
+		break;
+
+	case POWER_S3S0:
+		if (!power_has_signals(IN_S5_PGOOD)) {
+			/* Required rail went away */
+			return POWER_S5G3;
+		}
+
+		/* Enable wireless */
+		wireless_set_state(WIRELESS_ON);
+
+		lpc_s3_resume_clear_masks();
+
+		/* Call hooks now that rails are up */
+		hook_notify(HOOK_CHIPSET_RESUME);
+
+		/*
+		 * Disable idle task deep sleep. This means that the low
+		 * power idle task will not go into deep sleep while in S0.
+		 */
+		disable_sleep(SLEEP_MASK_AP_RUN);
+
+		return POWER_S0;
+
+	case POWER_S0:
+		if (!power_has_signals(IN_S5_PGOOD)) {
+			/* Required rail went away */
+			return POWER_S5G3;
+		}
+#ifdef CONFIG_POWER_S0IX
+		/*
+		 * SLP_S0 may assert in system idle scenario without a kernel
+		 * freeze call. This may cause interrupt storm since there is
+		 * no freeze/unfreeze of threads/process in the idle scenario.
+		 * Ignore the SLP_S0 assertions in idle scenario by checking
+		 * the host sleep state.
+		 */
+		else if (power_get_host_sleep_state() ==
+				 HOST_SLEEP_EVENT_S0IX_SUSPEND &&
+			 gpio_get_level(GPIO_PCH_SLP_S0_L) == 0) {
+			return POWER_S0S0ix;
+		}
+#endif
+		else if (gpio_get_level(GPIO_PCH_SLP_S3_L) == 0) {
+			/* Power down to next state */
+			return POWER_S0S3;
+		}
+#ifdef CONFIG_POWER_S0IX
+		/*
+		 * Call hooks only if we haven't notified listeners of S0ix
+		 * resume.
+		 */
+		sleep_notify_transition(SLEEP_NOTIFY_RESUME,
+					HOOK_CHIPSET_RESUME);
+#endif
+		break;
+
+	case POWER_S0S3:
+		/* Call hooks before we remove power rails */
+		hook_notify(HOOK_CHIPSET_SUSPEND);
+
+		/* Suspend wireless */
+		wireless_set_state(WIRELESS_SUSPEND);
+
+		/*
+		 * Enable idle task deep sleep. Allow the low power idle task
+		 * to go into deep sleep in S3 or lower.
+		 */
+		enable_sleep(SLEEP_MASK_AP_RUN);
+
+#ifdef CONFIG_POWER_S0IX
+		/* re-init S0ix flag */
+		power_reset_host_sleep_state();
+#endif
+		return POWER_S3;
+
+	case POWER_S3S5:
+		/* Call hooks before we remove power rails */
+		hook_notify(HOOK_CHIPSET_SHUTDOWN);
+
+		/* Disable wireless */
+		wireless_set_state(WIRELESS_OFF);
+
+		/* Call hooks after we remove power rails */
+		hook_notify(HOOK_CHIPSET_SHUTDOWN_COMPLETE);
+
+		return POWER_S5;
+
+	case POWER_S5G3:
+		chipset_force_g3();
+
+		return POWER_G3;
+
+#ifdef CONFIG_POWER_S0IX
+	case POWER_S0ix:
+		/* System in S0 only if SLP_S0 and SLP_S3 are de-asserted */
+		if ((gpio_get_level(GPIO_PCH_SLP_S0_L) == 1) &&
+		    (gpio_get_level(GPIO_PCH_SLP_S3_L) == 1)) {
+			return POWER_S0ixS0;
+		} else if (!power_has_signals(IN_S5_PGOOD) ||
+			   (gpio_get_level(GPIO_PCH_SLP_S5_L) == 0)) {
+			/* Lost power or AP shutdown, start transition to G3 */
+			power_reset_host_sleep_state();
+			return POWER_S0;
+		}
+		break;
+
+	case POWER_S0S0ix:
+		/*
+		 * Call hooks only if we haven't notified listeners of S0ix
+		 * suspend.
+		 */
+		sleep_notify_transition(SLEEP_NOTIFY_SUSPEND,
+					HOOK_CHIPSET_SUSPEND);
+		sleep_suspend_transition();
+
+		/*
+		 * Enable idle task deep sleep. Allow the low power idle task
+		 * to go into deep sleep in S0ix.
+		 */
+		enable_sleep(SLEEP_MASK_AP_RUN);
+		return POWER_S0ix;
+
+	case POWER_S0ixS0:
+		/*
+		 * Disable idle task deep sleep. This means that the low
+		 * power idle task will not go into deep sleep while in S0.
+		 */
+		disable_sleep(SLEEP_MASK_AP_RUN);
+
+		sleep_resume_transition();
+		return POWER_S0;
+#endif /* CONFIG_POWER_S0IX */
+	default:
+		break;
+	}
+	return state;
+}
diff --git a/power/apollolake.c b/power/apollolake.c
index 36c78c8158..20244abee9 100644
--- a/power/apollolake.c
+++ b/power/apollolake.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,12 +8,12 @@
 #include "chipset.h"
 #include "console.h"
 #include "gpio.h"
-#include "intel_x86.h"
+#include "power/intel_x86.h"
 #include "task.h"
 #include "timer.h"
 
 /* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 /*
  * force_shutdown is used to maintain chipset shutdown request. This request
@@ -51,7 +51,7 @@ const struct power_signal_info power_signal_list[] = {
 		"ALL_SYS_PGOOD",
 	},
 	[X86_RSMRST_N] = {
-		GPIO_RSMRST_L_PGOOD,
+		GPIO_PG_EC_RSMRST_ODL,
 		POWER_SIGNAL_ACTIVE_HIGH,
 		"RSMRST_L",
 	},
@@ -145,7 +145,6 @@ enum power_state power_handle_state(enum power_state state)
 
 		new_state = POWER_S5G3;
 		goto rsmrst_handle;
-
 	}
 
 	/* If force shutdown is requested, perform that. */
@@ -178,6 +177,6 @@ int chipset_pltrst_is_valid(void)
 	 * Invalid PLTRST# from SOC unless RSMRST#
 	 * from PMIC through EC to soc is deasserted.
 	 */
-	return (gpio_get_level(GPIO_RSMRST_L_PGOOD) &&
+	return (gpio_get_level(GPIO_PG_EC_RSMRST_ODL) &&
 		gpio_get_level(GPIO_PCH_RSMRST_L));
 }
diff --git a/power/apollolake.h b/power/apollolake.h
deleted file mode 100644
index cc864f26c3..0000000000
--- a/power/apollolake.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Apollolake chipset power control module for Chrome EC */
-
-#ifndef __CROS_EC_APOLLOLAKE_H
-#define __CROS_EC_APOLLOLAKE_H
-
-/*
- * Input state flags.
- * TODO: Normalize the power signal masks from board defines to SoC headers.
- */
-#define IN_RSMRST_N	POWER_SIGNAL_MASK(X86_RSMRST_N)
-#define IN_ALL_SYS_PG	POWER_SIGNAL_MASK(X86_ALL_SYS_PG)
-#define IN_SLP_S3_N	POWER_SIGNAL_MASK(X86_SLP_S3_N)
-#define IN_SLP_S4_N	POWER_SIGNAL_MASK(X86_SLP_S4_N)
-#define IN_PCH_SLP_S4_DEASSERTED IN_SLP_S4_N
-#define IN_SUSPWRDNACK	POWER_SIGNAL_MASK(X86_SUSPWRDNACK)
-#define IN_SUS_STAT_N	POWER_SIGNAL_MASK(X86_SUS_STAT_N)
-
-#define IN_ALL_PM_SLP_DEASSERTED (IN_SLP_S3_N | \
-				  IN_SLP_S4_N)
-
-#define IN_PGOOD_ALL_CORE (IN_RSMRST_N)
-
-#define IN_ALL_S0 (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED)
-
-#define CHIPSET_G3S5_POWERUP_SIGNAL IN_PGOOD_ALL_CORE
-
-#define CHARGER_INITIALIZED_DELAY_MS 100
-#define CHARGER_INITIALIZED_TRIES 40
-
-enum power_signal {
-#ifdef CONFIG_POWER_S0IX
-	X86_SLP_S0_N,		/* PCH  -> SLP_S0_L */
-#endif
-	X86_SLP_S3_N,		/* PCH  -> SLP_S3_L */
-	X86_SLP_S4_N,		/* PCH  -> SLP_S4_L */
-	X86_SUSPWRDNACK,	/* PCH  -> SUSPWRDNACK */
-
-	X86_ALL_SYS_PG,		/* PMIC -> PMIC_EC_PWROK_OD */
-	X86_RSMRST_N,		/* PMIC -> PMIC_EC_RSMRST_ODL */
-	X86_PGOOD_PP3300,	/* PMIC -> PP3300_PG_OD */
-	X86_PGOOD_PP5000,	/* PMIC -> PP5000_PG_OD */
-
-	/* Number of X86 signals */
-	POWER_SIGNAL_COUNT
-};
-
-#endif /* __CROS_EC_APOLLOLAKE_H */
diff --git a/power/braswell.c b/power/braswell.c
deleted file mode 100644
index 288092c795..0000000000
--- a/power/braswell.c
+++ /dev/null
@@ -1,324 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* X86 braswell chipset power control module for Chrome EC */
-
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "lid_switch.h"
-#include "lpc.h"
-#include "power.h"
-#include "power_button.h"
-#include "system.h"
-#include "timer.h"
-#include "usb_charge.h"
-#include "util.h"
-#include "wireless.h"
-#include "registers.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-/* Input state flags */
-#define IN_RSMRST_L_PWRGD          POWER_SIGNAL_MASK(X86_RSMRST_L_PWRGD)
-#define IN_ALL_SYS_PWRGD           POWER_SIGNAL_MASK(X86_ALL_SYS_PWRGD)
-#define IN_SLP_S3_DEASSERTED       POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
-#define IN_SLP_S4_DEASSERTED       POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED)
-
-/* All always-on supplies */
-#define IN_PGOOD_ALWAYS_ON   (IN_RSMRST_L_PWRGD)
-/* All non-core power rails */
-#define IN_PGOOD_ALL_NONCORE (IN_ALL_SYS_PWRGD)
-/* All core power rails */
-#define IN_PGOOD_ALL_CORE    (IN_ALL_SYS_PWRGD)
-/* Rails required for S5 */
-#define IN_PGOOD_S5          (IN_PGOOD_ALWAYS_ON)
-/* Rails required for S3 */
-#define IN_PGOOD_S3          (IN_PGOOD_ALWAYS_ON)
-/* Rails required for S0 */
-#define IN_PGOOD_S0          (IN_PGOOD_ALWAYS_ON | IN_PGOOD_ALL_NONCORE)
-
-/* All PM_SLP signals from PCH deasserted */
-#define IN_ALL_PM_SLP_DEASSERTED (IN_SLP_S3_DEASSERTED | IN_SLP_S4_DEASSERTED)
-/* All inputs in the right state for S0 */
-#define IN_ALL_S0 (IN_PGOOD_S0 | IN_ALL_PM_SLP_DEASSERTED)
-
-static int throttle_cpu;      /* Throttle CPU? */
-static int forcing_shutdown;  /* Forced shutdown in progress? */
-
-void chipset_force_shutdown(enum chipset_shutdown_reason reason)
-{
-	CPRINTS("%s(%d)", __func__, reason);
-	report_ap_reset(reason);
-
-	/*
-	 * Force power off. This condition will reset once the state machine
-	 * transitions to G3.
-	 */
-#ifndef CONFIG_PMIC
-	gpio_set_level(GPIO_PCH_SYS_PWROK, 0);
-#endif
-	gpio_set_level(GPIO_PCH_RSMRST_L, 0);
-	forcing_shutdown = 1;
-}
-
-void chipset_reset(enum chipset_reset_reason reason)
-{
-	CPRINTS("%s: %d", __func__, reason);
-	report_ap_reset(reason);
-
-	/*
-	 * Send a reset pulse to the PCH.  This just causes it to
-	 * assert INIT# to the CPU without dropping power or asserting
-	 * PLTRST# to reset the rest of the system.  The PCH uses a 16
-	 * ms debounce time, so assert the signal for twice that.
-	 */
-	gpio_set_level(GPIO_PCH_RCIN_L, 0);
-	usleep(32 * MSEC);
-	gpio_set_level(GPIO_PCH_RCIN_L, 1);
-}
-
-void chipset_throttle_cpu(int throttle)
-{
-#ifdef CONFIG_CPU_PROCHOT_ACTIVE_LOW
-	throttle = !throttle;
-#endif /* CONFIG_CPU_PROCHOT_ACTIVE_LOW */
-	if (chipset_in_state(CHIPSET_STATE_ON))
-		gpio_set_level(GPIO_CPU_PROCHOT, throttle);
-}
-
-enum power_state power_chipset_init(void)
-{
-	/* Pause in S5 when shutting down. */
-	power_set_pause_in_s5(1);
-
-	/*
-	 * If we're switching between images without rebooting, see if the x86
-	 * is already powered on; if so, leave it there instead of cycling
-	 * through G3.
-	 */
-	if (system_jumped_to_this_image()) {
-		if ((power_get_signals() & IN_PGOOD_S0) == IN_PGOOD_S0) {
-			/* Disable idle task deep sleep when in S0. */
-			disable_sleep(SLEEP_MASK_AP_RUN);
-
-			CPRINTS("already in S0");
-			return POWER_S0;
-		} else {
-			/* Force all signals to their G3 states */
-			CPRINTS("forcing G3");
-			gpio_set_level(GPIO_PCH_SYS_PWROK, 0);
-			gpio_set_level(GPIO_PCH_RSMRST_L, 0);
-
-			/*wireless_set_state(WIRELESS_OFF);*/
-		}
-	}
-
-	return POWER_G3;
-}
-
-enum power_state power_handle_state(enum power_state state)
-{
-	switch (state) {
-	case POWER_G3:
-		break;
-
-	case POWER_G3S5:
-		/* Exit SOC G3 */
-#ifdef CONFIG_PMIC
-		gpio_set_level(GPIO_PCH_SYS_PWROK, 1);
-#else
-		gpio_set_level(GPIO_SUSPWRDNACK_SOC_EC, 0);
-#endif
-		CPRINTS("Exit SOC G3");
-
-		if (power_wait_signals(IN_PGOOD_S5)) {
-			chipset_force_shutdown(CHIPSET_SHUTDOWN_WAIT);
-			return POWER_G3;
-		}
-
-		/* Deassert RSMRST# */
-		gpio_set_level(GPIO_PCH_RSMRST_L, 1);
-		return POWER_S5;
-
-	case POWER_S5:
-		/* Check for SLP S4 */
-		if (gpio_get_level(GPIO_PCH_SLP_S4_L) == 1)
-			return POWER_S5S3; /* Power up to next state */
-		break;
-
-	case POWER_S5S3:
-
-		/* Call hooks now that rails are up */
-		hook_notify(HOOK_CHIPSET_STARTUP);
-
-		return POWER_S3;
-
-
-	case POWER_S3:
-
-		/* Check for state transitions */
-		if (!power_has_signals(IN_PGOOD_S3)) {
-			/* Required rail went away */
-			chipset_force_shutdown(CHIPSET_SHUTDOWN_POWERFAIL);
-			return POWER_S3S5;
-		} else if (gpio_get_level(GPIO_PCH_SLP_S3_L) == 1) {
-			/* Power up to next state */
-			return POWER_S3S0;
-		} else if (gpio_get_level(GPIO_PCH_SLP_S4_L) == 0) {
-			/* Power down to next state */
-			return POWER_S3S5;
-		}
-		break;
-
-	case POWER_S3S0:
-		/* Enable wireless */
-
-		/*wireless_set_state(WIRELESS_ON);*/
-
-		if (!power_has_signals(IN_PGOOD_S3)) {
-			chipset_force_shutdown(CHIPSET_SHUTDOWN_POWERFAIL);
-
-		/*wireless_set_state(WIRELESS_OFF);*/
-			return POWER_S3S5;
-		}
-
-		/* Call hooks now that rails are up */
-		hook_notify(HOOK_CHIPSET_RESUME);
-
-		/*
-		 * Disable idle task deep sleep. This means that the low
-		 * power idle task will not go into deep sleep while in S0.
-		 */
-		disable_sleep(SLEEP_MASK_AP_RUN);
-
-		/*
-		 * Wait 15 ms after all voltages good.  100 ms is only needed
-		 * for PCIe devices; mini-PCIe devices should need only 10 ms.
-		 */
-		msleep(15);
-
-		/*
-		 * Throttle CPU if necessary.  This should only be asserted
-		 * when +VCCP is powered (it is by now).
-		 */
-#ifdef CONFIG_CPU_PROCHOT_ACTIVE_LOW
-		gpio_set_level(GPIO_CPU_PROCHOT, !throttle_cpu);
-#else
-		gpio_set_level(GPIO_CPU_PROCHOT, throttle_cpu);
-#endif /* CONFIG_CPU_PROCHOT_ACTIVE_LOW */
-
-		/* Set SYS and CORE PWROK */
-		gpio_set_level(GPIO_PCH_SYS_PWROK, 1);
-
-		return POWER_S0;
-
-
-	case POWER_S0:
-
-		if (!power_has_signals(IN_PGOOD_ALWAYS_ON)) {
-			chipset_force_shutdown(CHIPSET_SHUTDOWN_POWERFAIL);
-			return POWER_S0S3;
-		}
-
-		if (!power_has_signals(IN_ALL_S0)) {
-			return POWER_S0S3;
-		}
-
-		break;
-	case POWER_S0S3:
-		/* Call hooks before we remove power rails */
-		hook_notify(HOOK_CHIPSET_SUSPEND);
-
-#ifndef CONFIG_PMIC
-		/* Clear SYS and CORE PWROK */
-		gpio_set_level(GPIO_PCH_SYS_PWROK, 0);
-#endif
-		/* Wait 40ns */
-		udelay(1);
-
-		/* Suspend wireless */
-
-		/*wireless_set_state(WIRELESS_SUSPEND);*/
-
-		/*
-		 * Enable idle task deep sleep. Allow the low power idle task
-		 * to go into deep sleep in S3 or lower.
-		 */
-		enable_sleep(SLEEP_MASK_AP_RUN);
-
-		/*
-		 * Deassert prochot since CPU is off and we're about to drop
-		 * +VCCP.
-		 */
-		gpio_set_level(GPIO_CPU_PROCHOT, 0);
-
-		return POWER_S3;
-
-	case POWER_S3S5:
-
-		/* Call hooks before we remove power rails */
-		hook_notify(HOOK_CHIPSET_SHUTDOWN);
-
-		/*wireless_set_state(WIRELESS_OFF);*/
-
-		/* Call hooks after we remove power rails */
-		hook_notify(HOOK_CHIPSET_SHUTDOWN_COMPLETE);
-
-		/* Start shutting down */
-		return power_get_pause_in_s5() ? POWER_S5 : POWER_S5G3;
-
-	case POWER_S5G3:
-		/*
-		 * in case shutdown is already done by apshutdown
-		 * (or chipset_force_shutdown()), SOC already lost
-		 * power and can't assert PMC_SUSPWRDNACK any more.
-		 */
-		if (forcing_shutdown) {
-			/* Config pins for SOC G3 */
-			gpio_config_module(MODULE_GPIO, 1);
-#ifndef CONFIG_PMIC
-			gpio_set_level(GPIO_SUSPWRDNACK_SOC_EC, 1);
-#else
-			gpio_set_level(GPIO_PCH_SYS_PWROK, 0);
-#endif
-
-			forcing_shutdown = 0;
-
-			CPRINTS("Enter SOC G3");
-
-			return POWER_G3;
-		}
-
-		if (gpio_get_level(GPIO_PCH_SUSPWRDNACK) == 1) {
-			/* Assert RSMRST# */
-			gpio_set_level(GPIO_PCH_RSMRST_L, 0);
-
-			/* Config pins for SOC G3 */
-			gpio_config_module(MODULE_GPIO, 1);
-
-			/* Enter SOC G3 */
-#ifdef CONFIG_PMIC
-			gpio_set_level(GPIO_PCH_SYS_PWROK, 0);
-			udelay(1);
-			gpio_set_level(GPIO_PCH_RSMRST_L, 0);
-#else
-			gpio_set_level(GPIO_SUSPWRDNACK_SOC_EC, 1);
-#endif
-			CPRINTS("Enter SOC G3");
-
-			return POWER_G3;
-		} else {
-			CPRINTS("waiting for PMC_SUSPWRDNACK to assert!");
-			return POWER_S5;
-		}
-	}
-	return state;
-}
diff --git a/power/build.mk b/power/build.mk
index b635219d3f..8ef237c154 100644
--- a/power/build.mk
+++ b/power/build.mk
@@ -1,26 +1,32 @@
 # -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
+# Copyright 2013 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
 # Power management for application processor and peripherals
 #
 
+power-$(CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540)+=alderlake_slg4bd44540.o
+power-$(CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540)+=intel_x86.o
 power-$(CONFIG_CHIPSET_APL_GLK)+=apollolake.o intel_x86.o
-power-$(CONFIG_CHIPSET_BRASWELL)+=braswell.o
 power-$(CONFIG_CHIPSET_CANNONLAKE)+=cannonlake.o intel_x86.o
 power-$(CONFIG_CHIPSET_COMETLAKE)+=cometlake.o intel_x86.o
 power-$(CONFIG_CHIPSET_COMETLAKE_DISCRETE)+=cometlake-discrete.o intel_x86.o
 power-$(CONFIG_CHIPSET_ECDRIVEN)+=ec_driven.o
 power-$(CONFIG_CHIPSET_ICELAKE)+=icelake.o intel_x86.o
+power-$(CONFIG_CHIPSET_METEORLAKE)+=meteorlake.o intel_x86.o
 power-$(CONFIG_CHIPSET_MT817X)+=mt817x.o
 power-$(CONFIG_CHIPSET_MT8183)+=mt8183.o
+power-$(CONFIG_CHIPSET_MT8186)+=mt8186.o
 power-$(CONFIG_CHIPSET_MT8192)+=mt8192.o
+power-$(CONFIG_CHIPSET_CEZANNE)+=amd_x86.o
 power-$(CONFIG_CHIPSET_RK3288)+=rk3288.o
 power-$(CONFIG_CHIPSET_RK3399)+=rk3399.o
-power-$(CONFIG_CHIPSET_SC7180)+=sc7180.o
+power-$(CONFIG_CHIPSET_SC7180)+=qcom.o
+power-$(CONFIG_CHIPSET_SC7280)+=qcom.o
 power-$(CONFIG_CHIPSET_SDM845)+=sdm845.o
 power-$(CONFIG_CHIPSET_SKYLAKE)+=skylake.o intel_x86.o
-power-$(CONFIG_CHIPSET_STONEY)+=stoney.o
+power-$(CONFIG_CHIPSET_STONEY)+=amd_x86.o
+power-$(CONFIG_CHIPSET_FALCONLITE)+=falconlite.o
 power-$(CONFIG_POWER_COMMON)+=common.o
 power-$(CONFIG_POWER_TRACK_HOST_SLEEP_STATE)+=host_sleep.o
diff --git a/power/cannonlake.c b/power/cannonlake.c
index 1822b1d3c2..b6f8d91e69 100644
--- a/power/cannonlake.c
+++ b/power/cannonlake.c
@@ -1,24 +1,24 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Cannonlake chipset power control module for Chrome EC */
 
-#include "cannonlake.h"
 #include "chipset.h"
 #include "console.h"
 #include "gpio.h"
-#include "intel_x86.h"
 #include "power.h"
+#include "power/cannonlake.h"
+#include "power/intel_x86.h"
 #include "power_button.h"
 #include "task.h"
 #include "timer.h"
 
 /* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
-static int forcing_shutdown;  /* Forced shutdown in progress? */
+static int forcing_shutdown; /* Forced shutdown in progress? */
 
 void chipset_force_shutdown(enum chipset_shutdown_reason reason)
 {
@@ -47,7 +47,7 @@ void chipset_handle_espi_reset_assert(void)
 	 * power button. If yes, release power button.
 	 */
 	if ((power_get_signals() & IN_PCH_SLP_SUS_DEASSERTED) &&
-		forcing_shutdown) {
+	    forcing_shutdown) {
 		power_button_pch_release();
 		forcing_shutdown = 0;
 	}
diff --git a/power/cannonlake.h b/power/cannonlake.h
deleted file mode 100644
index a056a96ec8..0000000000
--- a/power/cannonlake.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Cannonlake chipset power control module for Chrome EC */
-
-#ifndef __CROS_EC_CANNONLAKE_H
-#define __CROS_EC_CANNONLAKE_H
-
-/* Input state flags. */
-#define IN_PCH_SLP_S3_DEASSERTED  POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
-#define IN_PCH_SLP_S4_DEASSERTED  POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED)
-#define IN_PCH_SLP_SUS_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_SUS_DEASSERTED)
-
-#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3_DEASSERTED | \
-				  IN_PCH_SLP_S4_DEASSERTED | \
-				  IN_PCH_SLP_SUS_DEASSERTED)
-
-#define IN_PGOOD_ALL_CORE POWER_SIGNAL_MASK(X86_PMIC_DPWROK)
-
-#define IN_ALL_S0 (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED | \
-		   PP5000_PGOOD_POWER_SIGNAL_MASK)
-
-#define CHIPSET_G3S5_POWERUP_SIGNAL IN_PCH_SLP_SUS_DEASSERTED
-
-#define CHARGER_INITIALIZED_DELAY_MS 100
-#define CHARGER_INITIALIZED_TRIES 40
-
-#endif /* __CROS_EC_CANNONLAKE_H */
diff --git a/power/cometlake-discrete.c b/power/cometlake-discrete.c
index 0cdf8b2d5f..85a08da2d2 100644
--- a/power/cometlake-discrete.c
+++ b/power/cometlake-discrete.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,8 +12,8 @@
 #include "chipset.h"
 #include "console.h"
 #include "gpio.h"
-#include "intel_x86.h"
 #include "power.h"
+#include "power/intel_x86.h"
 #include "power_button.h"
 #include "task.h"
 #include "timer.h"
@@ -217,7 +217,9 @@ void chipset_force_shutdown(enum chipset_shutdown_reason reason)
 	shutdown_s5_rails();
 }
 
-void chipset_handle_espi_reset_assert(void) {}
+void chipset_handle_espi_reset_assert(void)
+{
+}
 
 enum power_state chipset_force_g3(void)
 {
@@ -303,7 +305,7 @@ enum power_state power_handle_state(enum power_state state)
 		if (power_wait_signals(POWER_SIGNAL_MASK(PP1800_A_PGOOD) |
 				       POWER_SIGNAL_MASK(PP1050_A_PGOOD)))
 			return pgood_timeout(POWER_S5G3);
-		msleep(10);	/* tPCH03: VCCPRIM good -> RSMRST >10ms */
+		msleep(10); /* tPCH03: VCCPRIM good -> RSMRST >10ms */
 		gpio_set_level(GPIO_PCH_RSMRST_L, 1);
 		break;
 
@@ -383,7 +385,9 @@ enum power_state power_handle_state(enum power_state state)
  * implies power sequencing is all-off and we don't have any external
  * PMIC to synchronize state with.
  */
-void chipset_handle_reboot(void) {}
+void chipset_handle_reboot(void)
+{
+}
 #endif /* CONFIG_VBOOT_EFS */
 
 void c10_gate_interrupt(enum gpio_signal signal)
@@ -406,8 +410,8 @@ void c10_gate_interrupt(enum gpio_signal signal)
 
 void slp_s3_interrupt(enum gpio_signal signal)
 {
-	if (!gpio_get_level(GPIO_SLP_S3_L)
-	    && chipset_in_state(CHIPSET_STATE_ON)) {
+	if (!gpio_get_level(GPIO_SLP_S3_L) &&
+	    chipset_in_state(CHIPSET_STATE_ON)) {
 		/* Falling edge on SLP_S3_L means dropping to S3 from S0 */
 		shutdown_s0_rails();
 	}
diff --git a/power/cometlake.c b/power/cometlake.c
index 8328696751..508ad22df4 100644
--- a/power/cometlake.c
+++ b/power/cometlake.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,14 +8,14 @@
 #include "chipset.h"
 #include "console.h"
 #include "gpio.h"
-#include "intel_x86.h"
 #include "power.h"
+#include "power/intel_x86.h"
 #include "power_button.h"
 #include "task.h"
 #include "timer.h"
 
 /* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 /* Power signals list. Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
@@ -36,7 +36,7 @@ const struct power_signal_info power_signal_list[] = {
 		.name = "SLP_S4_DEASSERTED",
 	},
 	[X86_RSMRST_L_PGOOD] = {
-		.gpio = GPIO_RSMRST_L_PGOOD,
+		.gpio = GPIO_PG_EC_RSMRST_ODL,
 		.flags = POWER_SIGNAL_ACTIVE_HIGH,
 		.name = "RSMRST_L_PGOOD",
 	},
@@ -53,12 +53,12 @@ const struct power_signal_info power_signal_list[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
-static int forcing_shutdown;  /* Forced shutdown in progress? */
+static int forcing_shutdown; /* Forced shutdown in progress? */
 
 /* Default no action, overwrite it in board.c if necessary*/
 __overridable void board_chipset_forced_shutdown(void)
 {
-        return;
+	return;
 }
 
 void chipset_force_shutdown(enum chipset_shutdown_reason reason)
@@ -84,7 +84,7 @@ void chipset_force_shutdown(enum chipset_shutdown_reason reason)
 
 	/* For b:143440730, stop checking GPIO_ALL_SYS_PGOOD if system is
 	 * already force to G3.
-         */
+	 */
 	board_chipset_forced_shutdown();
 
 	/* Need to wait a min of 10 msec before check for power good */
@@ -92,7 +92,8 @@ void chipset_force_shutdown(enum chipset_shutdown_reason reason)
 
 	/* Now wait for PP5000_A and RSMRST_L to go low */
 	while ((gpio_get_level(GPIO_PP5000_A_PG_OD) ||
-		power_has_signals(IN_PGOOD_ALL_CORE)) && (timeout_ms > 0)) {
+		power_has_signals(IN_PGOOD_ALL_CORE)) &&
+	       (timeout_ms > 0)) {
 		msleep(1);
 		timeout_ms--;
 	};
@@ -155,7 +156,6 @@ void chipset_pre_init_callback(void)
 
 enum power_state power_handle_state(enum power_state state)
 {
-
 	int all_sys_pwrgd_in;
 	int all_sys_pwrgd_out;
 
@@ -176,7 +176,6 @@ enum power_state power_handle_state(enum power_state state)
 		common_intel_x86_handle_rsmrst(state);
 
 	switch (state) {
-
 	case POWER_S5:
 		if (forcing_shutdown) {
 			power_button_pch_release();
diff --git a/power/cometlake.h b/power/cometlake.h
deleted file mode 100644
index 8e0aab6982..0000000000
--- a/power/cometlake.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Cometlake chipset power control module for Chrome EC */
-
-#ifndef __CROS_EC_COMETLAKE_H
-#define __CROS_EC_COMETLATE_H
-
-/* Input state flags. */
-#define IN_PCH_SLP_S3_DEASSERTED  POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
-#define IN_PCH_SLP_S4_DEASSERTED  POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED)
-
-#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3_DEASSERTED | \
-				  IN_PCH_SLP_S4_DEASSERTED)
-
-#define IN_PGOOD_ALL_CORE POWER_SIGNAL_MASK(X86_RSMRST_L_PGOOD)
-
-#define IN_ALL_S0 (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED | \
-		   PP5000_PGOOD_POWER_SIGNAL_MASK)
-
-#define CHIPSET_G3S5_POWERUP_SIGNAL (POWER_SIGNAL_MASK(X86_RSMRST_L_PGOOD) | \
-	POWER_SIGNAL_MASK(X86_PP5000_A_PGOOD))
-
-#define CHARGER_INITIALIZED_DELAY_MS 100
-#define CHARGER_INITIALIZED_TRIES 40
-
-/* Power signals list */
-enum power_signal {
-	X86_SLP_S0_DEASSERTED,
-	X86_SLP_S3_DEASSERTED,
-	X86_SLP_S4_DEASSERTED,
-	X86_RSMRST_L_PGOOD,
-	X86_PP5000_A_PGOOD,
-	X86_ALL_SYS_PGOOD,
-
-	/* Number of X86 signals */
-	POWER_SIGNAL_COUNT
-};
-
-void all_sys_pgood_check_reboot(void);
-__override_proto void board_chipset_forced_shutdown(void);
-
-#endif /* __CROS_EC_COMETLAKE_H */
diff --git a/power/common.c b/power/common.c
index 8806c9a3b6..7a1de54de1 100644
--- a/power/common.c
+++ b/power/common.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,9 +16,11 @@
 #include "gpio.h"
 #include "hooks.h"
 #include "host_command.h"
-#include "intel_x86.h"
 #include "lpc.h"
 #include "power.h"
+#include "power/amd_x86.h"
+#include "power/intel_x86.h"
+#include "power/qcom.h"
 #include "system.h"
 #include "task.h"
 #include "timer.h"
@@ -26,8 +28,8 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ##args)
 
 /*
  * Default timeout in us; if we've been waiting this long for an input
@@ -35,35 +37,34 @@
  */
 #define DEFAULT_TIMEOUT SECOND
 
-/* Timeout for dropping back from S5 to G3 */
-#define S5_INACTIVITY_TIMEOUT (10 * SECOND)
+/* Timeout for dropping back from S5 to G3 in seconds */
+#ifdef CONFIG_CMD_S5_TIMEOUT
+static int s5_inactivity_timeout = 10;
+#else
+static const int s5_inactivity_timeout = 10;
+#endif
 
-static const char * const state_names[] = {
-	"G3",
-	"S5",
-	"S3",
-	"S0",
+static const char *const state_names[] = {
+	"G3",	    "S5",	"S4",	  "S3",	    "S0",
 #ifdef CONFIG_POWER_S0IX
 	"S0ix",
 #endif
-	"G3->S5",
-	"S5->S3",
-	"S3->S0",
-	"S0->S3",
-	"S3->S5",
-	"S5->G3",
+	"G3->S5",   "S5->S3",	"S3->S0", "S0->S3", "S3->S5",
+	"S5->G3",   "S3->S4",	"S4->S3", "S4->S5", "S5->S4",
 #ifdef CONFIG_POWER_S0IX
-	"S0ix->S0",
-	"S0->S0ix",
+	"S0ix->S0", "S0->S0ix",
+#endif
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+	"S0ix->S3", "S3->S0ix",
 #endif
 };
 
-static uint32_t in_signals;   /* Current input signal states (IN_PGOOD_*) */
-static uint32_t in_want;      /* Input signal state we're waiting for */
-static uint32_t in_debug;     /* Signal values which print debug output */
+static uint32_t in_signals; /* Current input signal states (IN_PGOOD_*) */
+static uint32_t in_want; /* Input signal state we're waiting for */
+static uint32_t in_debug; /* Signal values which print debug output */
 
-static enum power_state state = POWER_G3;  /* Current state */
-static int want_g3_exit;      /* Should we exit the G3 state? */
+static enum power_state state = POWER_G3; /* Current state */
+static int want_g3_exit; /* Should we exit the G3 state? */
 static uint64_t last_shutdown_time; /* When did we enter G3? */
 
 #ifdef CONFIG_HIBERNATE
@@ -76,46 +77,69 @@ static uint32_t hibernate_delay = CONFIG_HIBERNATE_DELAY_SEC;
 static int pause_in_s5;
 #endif
 
-static bool want_reboot_ap_at_g3;/* Want to reboot AP from G3? */
+static bool want_reboot_ap_at_g3; /* Want to reboot AP from G3? */
+/* Want to reboot AP from G3 with delay? */
+static uint64_t reboot_ap_at_g3_delay;
 
 static enum ec_status
 host_command_reboot_ap_on_g3(struct host_cmd_handler_args *args)
 {
+	const struct ec_params_reboot_ap_on_g3_v1 *cmd = args->params;
+
 	/* Store request for processing at g3 */
 	want_reboot_ap_at_g3 = true;
 
+	switch (args->version) {
+	case 0:
+		break;
+	case 1:
+		/* Store user specified delay to wait in G3 state */
+		reboot_ap_at_g3_delay = cmd->reboot_ap_at_g3_delay;
+		break;
+	default:
+		return EC_RES_INVALID_PARAM;
+	}
+
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_REBOOT_AP_ON_G3,
-		     host_command_reboot_ap_on_g3,
-		     EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_REBOOT_AP_ON_G3, host_command_reboot_ap_on_g3,
+		     EC_VER_MASK(0) | EC_VER_MASK(1));
+
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+void board_reboot_ap_on_g3(void)
+{
+	want_reboot_ap_at_g3 = true;
+}
+#endif
 
 __overridable int power_signal_get_level(enum gpio_signal signal)
 {
-	if (IS_ENABLED(CONFIG_HOSTCMD_ESPI)) {
+	if (IS_ENABLED(CONFIG_HOST_ESPI_VW_POWER_SIGNAL)) {
 		/* Check signal is from GPIOs or VWs */
 		if (espi_signal_is_vw(signal))
-			return espi_vw_get_wire(signal);
+			return espi_vw_get_wire((enum espi_vw_signal)signal);
 	}
 	return gpio_get_level(signal);
 }
 
 int power_signal_disable_interrupt(enum gpio_signal signal)
 {
-	if (IS_ENABLED(CONFIG_HOSTCMD_ESPI)) {
+	if (IS_ENABLED(CONFIG_HOST_ESPI_VW_POWER_SIGNAL)) {
 		/* Check signal is from GPIOs or VWs */
 		if (espi_signal_is_vw(signal))
-			return espi_vw_disable_wire_int(signal);
+			return espi_vw_disable_wire_int(
+				(enum espi_vw_signal)signal);
 	}
 	return gpio_disable_interrupt(signal);
 }
 
 int power_signal_enable_interrupt(enum gpio_signal signal)
 {
-	if (IS_ENABLED(CONFIG_HOSTCMD_ESPI)) {
+	if (IS_ENABLED(CONFIG_HOST_ESPI_VW_POWER_SIGNAL)) {
 		/* Check signal is from GPIOs or VWs */
 		if (espi_signal_is_vw(signal))
-			return espi_vw_enable_wire_int(signal);
+			return espi_vw_enable_wire_int(
+				(enum espi_vw_signal)signal);
 	}
 	return gpio_enable_interrupt(signal);
 }
@@ -123,16 +147,17 @@ int power_signal_enable_interrupt(enum gpio_signal signal)
 int power_signal_is_asserted(const struct power_signal_info *s)
 {
 	return power_signal_get_level(s->gpio) ==
-		!!(s->flags & POWER_SIGNAL_ACTIVE_STATE);
+	       !!(s->flags & POWER_SIGNAL_ACTIVE_STATE);
 }
 
 #ifdef CONFIG_BRINGUP
 static const char *power_signal_get_name(enum gpio_signal signal)
 {
-	if (IS_ENABLED(CONFIG_HOSTCMD_ESPI)) {
+	if (IS_ENABLED(CONFIG_HOST_INTERFACE_ESPI)) {
 		/* Check signal is from GPIOs or VWs */
 		if (espi_signal_is_vw(signal))
-			return espi_vw_get_wire_name(signal);
+			return espi_vw_get_wire_name(
+				(enum espi_vw_signal)signal);
 	}
 	return gpio_get_name(signal);
 }
@@ -168,8 +193,8 @@ int power_has_signals(uint32_t want)
 	if ((in_signals & want) == want)
 		return 1;
 
-	CPRINTS("power lost input; wanted 0x%04x, got 0x%04x",
-		want, in_signals & want);
+	CPRINTS("power lost input; wanted 0x%04x, got 0x%04x", want,
+		in_signals & want);
 
 	return 0;
 }
@@ -223,11 +248,11 @@ void power_set_state(enum power_state new_state)
 
 	/*
 	 * Reset want_g3_exit flag here to prevent the situation that if the
-	 * error handler in POWER_S5S3 decides to force shutdown the system and
+	 * error handler in POWER_S5S4 decides to force shutdown the system and
 	 * the flag is set, the system will go to G3 and then immediately exit
 	 * G3 again.
 	 */
-	if (state == POWER_S5S3)
+	if ((state == POWER_S5S4) || (state == POWER_S5S3))
 		want_g3_exit = 0;
 }
 
@@ -239,18 +264,19 @@ enum power_state power_get_state(void)
 #ifdef CONFIG_HOSTCMD_X86
 
 /* If host doesn't program s0ix lazy wake mask, use default s0ix mask */
-#define DEFAULT_WAKE_MASK_S0IX  (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \
-				EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
-
- /*
-  * Set the wake mask according to the current power state:
-  * 1. On transition to S0, wake mask is reset.
-  * 2. In non-S0 states, active mask set by host gets a higher preference.
-  * 3. If host has not set any active mask, then check if a lazy mask exists
-  *    for the current power state.
-  * 4. If state is S0ix and no lazy or active wake mask is set, then use default
-  *    S0ix mask to be compatible with older BIOS versions.
-  */
+#define DEFAULT_WAKE_MASK_S0IX                        \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
+
+/*
+ * Set the wake mask according to the current power state:
+ * 1. On transition to S0, wake mask is reset.
+ * 2. In non-S0 states, active mask set by host gets a higher preference.
+ * 3. If host has not set any active mask, then check if a lazy mask exists
+ *    for the current power state.
+ * 4. If state is S0ix and no lazy or active wake mask is set, then use default
+ *    S0ix mask to be compatible with older BIOS versions.
+ */
 
 void power_update_wake_mask(void)
 {
@@ -272,11 +298,11 @@ void power_update_wake_mask(void)
 
 	lpc_set_host_event_mask(LPC_HOST_EVENT_WAKE, wake_mask);
 }
- /*
-  * Set wake mask after power state has stabilized, 5ms after power state
-  * change. The reason for making this a deferred call is to avoid race
-  * conditions occurring from S0ix periodic wakes on the SoC.
-  */
+/*
+ * Set wake mask after power state has stabilized, 5ms after power state
+ * change. The reason for making this a deferred call is to avoid race
+ * conditions occurring from S0ix periodic wakes on the SoC.
+ */
 
 static void power_update_wake_mask_deferred(void);
 DECLARE_DEFERRED(power_update_wake_mask_deferred);
@@ -301,12 +327,13 @@ static void power_set_active_wake_mask(void)
 	 * that it takes ~2msec for the periodic wake cycle to complete on the
 	 * host for KBL.
 	 */
-	hook_call_deferred(&power_update_wake_mask_deferred_data,
-			   5 * MSEC);
+	hook_call_deferred(&power_update_wake_mask_deferred_data, 5 * MSEC);
 }
 
 #else
-static void power_set_active_wake_mask(void) { }
+static void power_set_active_wake_mask(void)
+{
+}
 #endif
 
 #ifdef CONFIG_HIBERNATE
@@ -350,15 +377,15 @@ static enum ec_status hc_smart_discharge(struct host_cmd_handler_args *args)
 		else if (p->drate.cutoff > 0 && p->drate.hibern > 0)
 			drate = p->drate;
 		else if (p->drate.cutoff == 0 && p->drate.hibern == 0)
-			;  /* no-op. use the current drate. */
+			; /* no-op. use the current drate. */
 		else
 			return EC_RES_INVALID_PARAM;
 
 		/* Commit */
 		hours_to_zero = p->hours_to_zero;
 		sdzone.stayup = MIN(hours_to_zero * drate.hibern / 1000, cap);
-		sdzone.cutoff = MIN(hours_to_zero * drate.cutoff / 1000,
-				    sdzone.stayup);
+		sdzone.cutoff =
+			MIN(hours_to_zero * drate.cutoff / 1000, sdzone.stayup);
 	}
 
 	/* Return the effective values. */
@@ -369,12 +396,12 @@ static enum ec_status hc_smart_discharge(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_SMART_DISCHARGE,
-		     hc_smart_discharge,
+DECLARE_HOST_COMMAND(EC_CMD_SMART_DISCHARGE, hc_smart_discharge,
 		     EC_VER_MASK(0));
 
-__overridable enum critical_shutdown board_system_is_idle(
-		uint64_t last_shutdown_time, uint64_t *target, uint64_t now)
+__overridable enum critical_shutdown
+board_system_is_idle(uint64_t last_shutdown_time, uint64_t *target,
+		     uint64_t now)
 {
 	int remain;
 
@@ -399,14 +426,15 @@ __overridable enum critical_shutdown board_system_is_idle(
 }
 #else
 /* Default implementation for battery-less systems */
-__overridable enum critical_shutdown board_system_is_idle(
-		uint64_t last_shutdown_time, uint64_t *target, uint64_t now)
+__overridable enum critical_shutdown
+board_system_is_idle(uint64_t last_shutdown_time, uint64_t *target,
+		     uint64_t now)
 {
-	return now > *target ?
-			CRITICAL_SHUTDOWN_HIBERNATE : CRITICAL_SHUTDOWN_IGNORE;
+	return now > *target ? CRITICAL_SHUTDOWN_HIBERNATE :
+			       CRITICAL_SHUTDOWN_IGNORE;
 }
-#endif	/* CONFIG_BATTERY */
-#endif	/* CONFIG_HIBERNATE */
+#endif /* CONFIG_BATTERY */
+#endif /* CONFIG_HIBERNATE */
 
 /**
  * Common handler for steady states
@@ -414,13 +442,24 @@ __overridable enum critical_shutdown board_system_is_idle(
  * @param state		Current power state
  * @return Updated power state
  */
-static enum power_state power_common_state(enum power_state state)
+static enum power_state power_common_state(void)
 {
 	switch (state) {
 	case POWER_G3:
 		if (want_g3_exit || want_reboot_ap_at_g3) {
+			uint64_t i;
+
 			want_g3_exit = 0;
 			want_reboot_ap_at_g3 = false;
+			reboot_ap_at_g3_delay = reboot_ap_at_g3_delay * MSEC;
+			/*
+			 * G3->S0 transition should happen only after the
+			 * user specified delay. Hence, wait until the
+			 * user specified delay times out.
+			 */
+			for (i = 0; i < reboot_ap_at_g3_delay; i += 100)
+				msleep(100);
+			reboot_ap_at_g3_delay = 0;
 
 			return POWER_G3S5;
 		}
@@ -435,7 +474,8 @@ static enum power_state power_common_state(enum power_state state)
 			}
 
 			now = get_time().val;
-			target = last_shutdown_time + hibernate_delay * SECOND;
+			target = last_shutdown_time +
+				 (uint64_t)hibernate_delay * SECOND;
 			switch (board_system_is_idle(last_shutdown_time,
 						     &target, now)) {
 			case CRITICAL_SHUTDOWN_HIBERNATE:
@@ -476,33 +516,34 @@ static enum power_state power_common_state(enum power_state state)
 		 */
 		want_g3_exit = 0;
 
-		/* Wait for inactivity timeout */
 		power_wait_signals(0);
-		if (task_wait_event(S5_INACTIVITY_TIMEOUT) ==
-		    TASK_EVENT_TIMER) {
+
+		/* Wait for inactivity timeout, if desired */
+		if (s5_inactivity_timeout == 0) {
+			return POWER_S5G3;
+		} else if (s5_inactivity_timeout < 0) {
+			task_wait_event(-1);
+		} else if (task_wait_event(s5_inactivity_timeout * SECOND) ==
+			   TASK_EVENT_TIMER) {
 			/* Prepare to drop to G3; wake not requested yet */
 			return POWER_S5G3;
 		}
 		break;
 
+	case POWER_S4:
+		__fallthrough;
 	case POWER_S3:
-		/* Wait for a message */
-		power_wait_signals(0);
-		task_wait_event(-1);
-		break;
-
+		__fallthrough;
 	case POWER_S0:
-		/* Wait for a message */
-		power_wait_signals(0);
-		task_wait_event(-1);
-		break;
 #ifdef CONFIG_POWER_S0IX
+		__fallthrough;
 	case POWER_S0ix:
+#endif
 		/* Wait for a message */
 		power_wait_signals(0);
 		task_wait_event(-1);
 		break;
-#endif
+
 	default:
 		/* No common functionality for transition states */
 		break;
@@ -536,10 +577,15 @@ int chipset_in_state(int state_mask)
 		need_mask = CHIPSET_STATE_HARD_OFF | CHIPSET_STATE_SOFT_OFF;
 		break;
 	case POWER_S5:
+	case POWER_S5S4:
+	case POWER_S4S5:
+	case POWER_S4:
 		need_mask = CHIPSET_STATE_SOFT_OFF;
 		break;
 	case POWER_S5S3:
 	case POWER_S3S5:
+	case POWER_S4S3:
+	case POWER_S3S4:
 		need_mask = CHIPSET_STATE_SOFT_OFF | CHIPSET_STATE_SUSPEND;
 		break;
 	case POWER_S3:
@@ -553,6 +599,12 @@ int chipset_in_state(int state_mask)
 		need_mask = CHIPSET_STATE_ON;
 		break;
 #ifdef CONFIG_POWER_S0IX
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+	case POWER_S0ixS3:
+	case POWER_S3S0ix:
+		need_mask = CHIPSET_STATE_ON | CHIPSET_STATE_STANDBY;
+		break;
+#endif
 	case POWER_S0ixS0:
 	case POWER_S0S0ix:
 		need_mask = CHIPSET_STATE_ON | CHIPSET_STATE_STANDBY;
@@ -574,14 +626,24 @@ int chipset_in_or_transitioning_to_state(int state_mask)
 	case POWER_S5G3:
 		return state_mask & CHIPSET_STATE_HARD_OFF;
 	case POWER_S5:
-	case POWER_G3S5:
+	case POWER_S4:
 	case POWER_S3S5:
+	case POWER_G3S5:
+	case POWER_S4S5:
+	case POWER_S5S4:
+	case POWER_S3S4:
 		return state_mask & CHIPSET_STATE_SOFT_OFF;
-	case POWER_S3:
 	case POWER_S5S3:
+	case POWER_S3:
+	case POWER_S4S3:
 	case POWER_S0S3:
 		return state_mask & CHIPSET_STATE_SUSPEND;
 #ifdef CONFIG_POWER_S0IX
+#ifdef CONFIG_CUSTOMIZED_DESIGN
+	case POWER_S0ixS3:
+	case POWER_S3S0ix:
+		return state_mask & CHIPSET_STATE_STANDBY;
+#endif
 	case POWER_S0ix:
 	case POWER_S0S0ix:
 		return state_mask & CHIPSET_STATE_STANDBY;
@@ -626,6 +688,18 @@ void chipset_exit_hard_off(void)
 	task_wake(TASK_ID_CHIPSET);
 }
 
+#ifdef CONFIG_ZTEST
+void test_power_common_state(void)
+{
+	enum power_state new_state;
+
+	task_wake(task_get_current());
+	new_state = power_common_state();
+	if (new_state != state)
+		power_set_state(new_state);
+}
+#endif
+
 /*****************************************************************************/
 /* Task function */
 
@@ -645,8 +719,8 @@ void chipset_task(void *u)
 		 */
 		this_in_signals = in_signals;
 		if (this_in_signals != last_in_signals || state != last_state) {
-			CPRINTS("power state %d = %s, in 0x%04x",
-				state, state_names[state], this_in_signals);
+			CPRINTS("power state %d = %s, in 0x%04x", state,
+				state_names[state], this_in_signals);
 			if (IS_ENABLED(CONFIG_SEVEN_SEG_DISPLAY))
 				display_7seg_write(SEVEN_SEG_EC_DISPLAY, state);
 			last_in_signals = this_in_signals;
@@ -661,12 +735,16 @@ void chipset_task(void *u)
 		 * handler.
 		 */
 		if (new_state == state)
-			new_state = power_common_state(state);
+			new_state = power_common_state();
 
 		/* Handle state changes */
 		if (new_state != state) {
 			power_set_state(new_state);
 			power_set_active_wake_mask();
+
+			/* Call hooks before we enter G3 */
+			if (new_state == POWER_G3)
+				hook_notify(HOOK_CHIPSET_HARD_OFF);
 		}
 	}
 }
@@ -682,9 +760,6 @@ static void power_common_init(void)
 	/* Update input state */
 	power_update_signals();
 
-	/* Call chipset-specific init to set initial state */
-	power_set_state(power_chipset_init());
-
 	/* Enable interrupts for input signals */
 	for (i = 0; i < POWER_SIGNAL_COUNT; i++, s++)
 		if (s->flags & POWER_SIGNAL_DISABLE_AT_BOOT)
@@ -692,6 +767,9 @@ static void power_common_init(void)
 		else
 			power_signal_enable_interrupt(s->gpio);
 
+	/* Call chipset-specific init to set initial state */
+	power_set_state(power_chipset_init());
+
 	/*
 	 * Update input state again since there is a small window
 	 * before GPIO is enabled.
@@ -742,7 +820,7 @@ static struct {
 static void siglog_deferred(void)
 {
 	unsigned int i;
-	timestamp_t tdiff = {.val = 0};
+	timestamp_t tdiff = { .val = 0 };
 
 	/* Disable interrupts for input signals while we print stuff.*/
 	for (i = 0; i < POWER_SIGNAL_COUNT; i++)
@@ -751,10 +829,9 @@ static void siglog_deferred(void)
 	CPRINTF("%d signal changes:\n", siglog_entries);
 	for (i = 0; i < siglog_entries; i++) {
 		if (i)
-			tdiff.val = siglog[i].time.val - siglog[i-1].time.val;
-		CPRINTF("  %.6lld  +%.6lld  %s => %d\n",
-			siglog[i].time.val, tdiff.val,
-			power_signal_get_name(siglog[i].signal),
+			tdiff.val = siglog[i].time.val - siglog[i - 1].time.val;
+		CPRINTF("  %.6lld  +%.6lld  %s => %d\n", siglog[i].time.val,
+			tdiff.val, power_signal_get_name(siglog[i].signal),
 			siglog[i].level);
 	}
 	if (siglog_truncated)
@@ -769,6 +846,15 @@ DECLARE_DEFERRED(siglog_deferred);
 
 static void siglog_add(enum gpio_signal signal)
 {
+	const struct power_signal_info *s = power_signal_list;
+	int i;
+
+	for (i = 0; i < POWER_SIGNAL_COUNT; i++, s++) {
+		if (s->gpio == signal && s->flags & POWER_SIGNAL_NO_LOG) {
+			return;
+		}
+	}
+
 	if (siglog_entries >= MAX_SIGLOG_ENTRIES) {
 		siglog_truncated = 1;
 		return;
@@ -786,7 +872,7 @@ static void siglog_add(enum gpio_signal signal)
 
 #else
 #define SIGLOG(S)
-#endif	/* CONFIG_BRINGUP */
+#endif /* CONFIG_BRINGUP */
 
 #ifdef CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD
 /*
@@ -803,8 +889,7 @@ static void reset_power_signal_interrupt_count(void)
 	for (i = 0; i < POWER_SIGNAL_COUNT; ++i)
 		power_signal_interrupt_count[i] = 0;
 }
-DECLARE_HOOK(HOOK_SECOND,
-	     reset_power_signal_interrupt_count,
+DECLARE_HOOK(HOOK_SECOND, reset_power_signal_interrupt_count,
 	     HOOK_PRIO_DEFAULT);
 #endif
 
@@ -817,7 +902,7 @@ void power_signal_interrupt(enum gpio_signal signal)
 	for (i = 0; i < POWER_SIGNAL_COUNT; ++i) {
 		if (power_signal_list[i].gpio == signal) {
 			if (power_signal_interrupt_count[i]++ ==
-			   CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD)
+			    CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD)
 				CPRINTS("Interrupt storm! Signal %d", i);
 			break;
 		}
@@ -848,23 +933,22 @@ inline void power_set_pause_in_s5(int pause)
 /*****************************************************************************/
 /* Console commands */
 
-static int command_powerinfo(int argc, char **argv)
+static int command_powerinfo(int argc, const char **argv)
 {
 	/*
 	 * Print power state in same format as state machine.  This is
 	 * used by FAFT tests, so must match exactly.
 	 */
-	ccprintf("power state %d = %s, in 0x%04x\n",
-		 state, state_names[state], in_signals);
+	ccprintf("power state %d = %s, in 0x%04x\n", state, state_names[state],
+		 in_signals);
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(powerinfo, command_powerinfo,
-			NULL,
+DECLARE_CONSOLE_COMMAND(powerinfo, command_powerinfo, NULL,
 			"Show current power state");
 
 #ifdef CONFIG_CMD_POWERINDEBUG
-static int command_powerindebug(int argc, char **argv)
+static int command_powerindebug(int argc, const char **argv)
 {
 	const struct power_signal_info *s = power_signal_list;
 	int i;
@@ -888,23 +972,46 @@ static int command_powerindebug(int argc, char **argv)
 	ccprintf("bit meanings:\n");
 	for (i = 0; i < POWER_SIGNAL_COUNT; i++, s++) {
 		int mask = 1 << i;
-		ccprintf("  0x%04x %d %s\n",
-			 mask, in_signals & mask ? 1 : 0, s->name);
+		ccprintf("  0x%04x %d %s\n", mask, in_signals & mask ? 1 : 0,
+			 s->name);
 	}
 
 	return EC_SUCCESS;
 };
-DECLARE_CONSOLE_COMMAND(powerindebug, command_powerindebug,
-			"[mask]",
+DECLARE_CONSOLE_COMMAND(powerindebug, command_powerindebug, "[mask]",
 			"Get/set power input debug mask");
 #endif
 
+#ifdef CONFIG_CMD_S5_TIMEOUT
+/* Allow command-line access to configure our S5 delay for power testing */
+static int command_s5_timeout(int argc, const char **argv)
+{
+	char *e;
+
+	if (argc >= 2) {
+		uint32_t s = strtoi(argv[1], &e, 0);
+
+		if (*e)
+			return EC_ERROR_PARAM1;
+
+		s5_inactivity_timeout = s;
+	}
+
+	/* Print the current setting */
+	ccprintf("S5 inactivity timeout: %d s\n", s5_inactivity_timeout);
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(s5_timeout, command_s5_timeout, "[sec]",
+			"Set the timeout from S5 to G3 transition, "
+			"-1 to indicate no transition");
+#endif
+
 #ifdef CONFIG_HIBERNATE
-static int command_hibernation_delay(int argc, char **argv)
+static int command_hibernation_delay(int argc, const char **argv)
 {
 	char *e;
-	uint32_t time_g3 = ((uint32_t)(get_time().val - last_shutdown_time))
-				/ SECOND;
+	uint32_t time_g3 =
+		((uint32_t)(get_time().val - last_shutdown_time)) / SECOND;
 
 	if (argc >= 2) {
 		uint32_t s = strtoi(argv[1], &e, 0);
@@ -922,8 +1029,7 @@ static int command_hibernation_delay(int argc, char **argv)
 	}
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(hibdelay, command_hibernation_delay,
-			"[sec]",
+DECLARE_CONSOLE_COMMAND(hibdelay, command_hibernation_delay, "[sec]",
 			"Set the delay before going into hibernation");
 
 static enum ec_status
@@ -954,10 +1060,9 @@ host_command_hibernation_delay(struct host_cmd_handler_args *args)
 	r->hibernate_delay = hibernate_delay;
 
 	args->response_size = sizeof(struct ec_response_hibernation_delay);
-	return EC_SUCCESS;
+	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_HIBERNATION_DELAY,
-		     host_command_hibernation_delay,
+DECLARE_HOST_COMMAND(EC_CMD_HIBERNATION_DELAY, host_command_hibernation_delay,
 		     EC_VER_MASK(0));
 #endif /* CONFIG_HIBERNATE */
 
@@ -976,11 +1081,10 @@ host_command_pause_in_s5(struct host_cmd_handler_args *args)
 	args->response_size = sizeof(*r);
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_GSV_PAUSE_IN_S5,
-		     host_command_pause_in_s5,
+DECLARE_HOST_COMMAND(EC_CMD_GSV_PAUSE_IN_S5, host_command_pause_in_s5,
 		     EC_VER_MASK(0));
 
-static int command_pause_in_s5(int argc, char **argv)
+static int command_pause_in_s5(int argc, const char **argv)
 {
 	if (argc > 1 && !parse_bool(argv[1], &pause_in_s5))
 		return EC_ERROR_INVAL;
@@ -989,8 +1093,7 @@ static int command_pause_in_s5(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(pause_in_s5, command_pause_in_s5,
-			"[on|off]",
+DECLARE_CONSOLE_COMMAND(pause_in_s5, command_pause_in_s5, "[on|off]",
 			"Should the AP pause in S5 during shutdown?");
 #endif /* CONFIG_POWER_SHUTDOWN_PAUSE_IN_S5 */
 
@@ -1005,7 +1108,7 @@ __overridable void board_power_5v_enable(int enable)
 
 /* 5V enable request bitmask from various tasks. */
 static uint32_t pwr_5v_en_req;
-static struct mutex pwr_5v_ctl_mtx;
+K_MUTEX_DEFINE(pwr_5v_ctl_mtx);
 
 void power_5v_enable(task_id_t tid, int enable)
 {
@@ -1024,14 +1127,13 @@ void power_5v_enable(task_id_t tid, int enable)
 	mutex_unlock(&pwr_5v_ctl_mtx);
 }
 
-#define P5_SYSJUMP_TAG 0x5005  /* "P5" */
+#define P5_SYSJUMP_TAG 0x5005 /* "P5" */
 static void restore_enable_5v_state(void)
 {
 	const uint32_t *state;
 	int size;
 
-	state = (const uint32_t *) system_get_jump_tag(P5_SYSJUMP_TAG, 0,
-						       &size);
+	state = (const uint32_t *)system_get_jump_tag(P5_SYSJUMP_TAG, 0, &size);
 	if (state && size == sizeof(pwr_5v_en_req)) {
 		mutex_lock(&pwr_5v_ctl_mtx);
 		pwr_5v_en_req |= *state;
@@ -1044,8 +1146,39 @@ static void preserve_enable_5v_state(void)
 {
 	mutex_lock(&pwr_5v_ctl_mtx);
 	system_add_jump_tag(P5_SYSJUMP_TAG, 0, sizeof(pwr_5v_en_req),
-	    &pwr_5v_en_req);
+			    &pwr_5v_en_req);
 	mutex_unlock(&pwr_5v_ctl_mtx);
 }
 DECLARE_HOOK(HOOK_SYSJUMP, preserve_enable_5v_state, HOOK_PRIO_DEFAULT);
 #endif /* defined(CONFIG_POWER_PP5000_CONTROL) */
+
+__overridable int chipset_in_low_power_mode(void)
+{
+	return false;
+}
+
+#ifdef CONFIG_POWERSEQ_FAKE_CONTROL
+static int command_power_fake(int argc, const char **argv)
+{
+	if (argc < 2) {
+		ccprints("Error: Argument required");
+		return EC_ERROR_PARAM_COUNT;
+	}
+
+	if (strcasecmp(argv[1], "S0") == 0) {
+		power_fake_s0();
+		if (power_get_state() == POWER_G3)
+			want_g3_exit = 1;
+	} else if (strcasecmp(argv[1], "disable") == 0) {
+		power_fake_disable();
+	} else {
+		ccprints("Error: Unknown param");
+		return EC_ERROR_PARAM1;
+	}
+
+	power_update_signals();
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(powerfake, command_power_fake, "S0|disable",
+			"Force power inputs for early board bringup");
+#endif /* defined(CONFIG_POWERSEQ_FAKE_CONTROL) */
diff --git a/power/ec_driven.c b/power/ec_driven.c
index 282941b941..f0aee46c60 100644
--- a/power/ec_driven.c
+++ b/power/ec_driven.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,7 +11,7 @@
  *
  */
 
-#include "chipset.h"  /* This module implements chipset functions too */
+#include "chipset.h" /* This module implements chipset functions too */
 #include "common.h"
 #include "console.h"
 #include "gpio.h"
@@ -22,7 +22,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 #define IN_SUSPEND POWER_SIGNAL_MASK(ECDRIVEN_SUSPEND_ASSERTED)
 
diff --git a/power/falconlite.c b/power/falconlite.c
new file mode 100644
index 0000000000..04c428f5be
--- /dev/null
+++ b/power/falconlite.c
@@ -0,0 +1,487 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* FalconLite chipset power control module for Chrome EC */
+
+#include "builtin/assert.h"
+#include "charge_state.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "system.h"
+#include "task.h"
+#include "timer.h"
+#include "util.h"
+
+#ifdef CONFIG_BRINGUP
+#define GPIO_SET_LEVEL(signal, value) \
+	gpio_set_level_verbose(CC_CHIPSET, signal, value)
+#else
+#define GPIO_SET_LEVEL(signal, value) gpio_set_level(signal, value)
+#endif
+
+/* Console output macros */
+#define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
+
+/* Long power key press to force shutdown in S0. go/crosdebug */
+#define FORCED_SHUTDOWN_DELAY (8 * SECOND)
+/* Long power key press to boot from S5/G3 state. */
+#define POWERBTN_BOOT_DELAY (10 * MSEC)
+
+#define SYS_RST_PULSE_LENGTH (30 * MSEC)
+
+/* Masks for power signals */
+#define IN_PG_S5 POWER_SIGNAL_MASK(FCL_PG_S5)
+#define IN_PGOOD                                  \
+	(POWER_SIGNAL_MASK(FCL_PG_VDD1_VDD2) |    \
+	 POWER_SIGNAL_MASK(FCL_PG_VDD_MEDIA_ML) | \
+	 POWER_SIGNAL_MASK(FCL_PG_VDD_SOC) |      \
+	 POWER_SIGNAL_MASK(FCL_PG_VDD_DDR_OD) | POWER_SIGNAL_MASK(FCL_PG_S5))
+
+#define IN_ALL_S0 IN_PGOOD
+#define IN_ALL_S3 IN_PGOOD
+
+/* Power signal list. Must match order of enum power_signal. */
+const struct power_signal_info power_signal_list[] = {
+	[FCL_AP_WARM_RST_REQ] = { GPIO_AP_EC_WARM_RST_REQ,
+				  POWER_SIGNAL_ACTIVE_HIGH, "AP_WARM_RST_REQ" },
+	[FCL_AP_SHUTDOWN_REQ] = { GPIO_AP_EC_SHUTDOWN_REQ_L,
+				  POWER_SIGNAL_ACTIVE_LOW, "AP_SHUTDOWN_REQ" },
+	[FCL_AP_WATCHDOG] = { GPIO_AP_EC_WATCHDOG_L, POWER_SIGNAL_ACTIVE_LOW,
+			      "AP_WDT" },
+	[FCL_PG_S5] = { GPIO_PG_S5_PWR_OD, POWER_SIGNAL_ACTIVE_HIGH, "PG_S5" },
+	[FCL_PG_VDD1_VDD2] = { GPIO_PG_VDD1_VDD2_OD, POWER_SIGNAL_ACTIVE_HIGH,
+			       "PG_VDD1_VDD2" },
+	[FCL_PG_VDD_MEDIA_ML] = { GPIO_PG_VDD_MEDIA_ML_OD,
+				  POWER_SIGNAL_ACTIVE_HIGH, "PG_VDD_MEDIA_ML" },
+	[FCL_PG_VDD_SOC] = { GPIO_PG_VDD_SOC_OD, POWER_SIGNAL_ACTIVE_HIGH,
+			     "PG_VDD_SOC" },
+	[FCL_PG_VDD_DDR_OD] = { GPIO_PG_VDD_DDR_OD, POWER_SIGNAL_ACTIVE_HIGH,
+				"PG_VDD_DDR" },
+};
+
+/* Data structure for a GPIO operation for power sequencing */
+struct power_seq_op {
+	enum gpio_signal signal;
+	uint8_t level;
+	/* Number of milliseconds to delay after setting signal to level */
+	uint32_t delay;
+};
+
+/*
+ * The entries in the table are handled sequentially from the top
+ * to the bottom.
+ */
+
+/* The power sequence for POWER_S3S5 */
+static const struct power_seq_op s3s5_power_seq[] = {
+	{ GPIO_EN_VDD_CPU, 0, 0 },	{ GPIO_EN_VDD_GPU, 0, 0 },
+	{ GPIO_EN_VDD_MEDIA_ML, 0, 4 },
+
+	{ GPIO_EN_VDDQ_VR_D, 0, 4 }, /* LPDDR */
+
+	{ GPIO_EN_VDD1_VDD2_VR, 0, 4 }, /* LPDDR */
+
+	{ GPIO_EN_VDD_DDR, 0, 4 },
+
+	{ GPIO_EN_PP3300A_IO_X, 0, 0 }, { GPIO_EN_PP3300_S3, 0, 4 },
+
+	{ GPIO_EN_PP1820A_IO_X, 0, 0 }, { GPIO_EN_PP1800_S3, 0, 0 },
+};
+
+/* The power sequence for POWER_G3S5 */
+static const struct power_seq_op g3s5_power_seq[] = {
+	/* delay 10ms as PP1800_S5 uses PP1800_S5 as alaternative supply */
+	{ GPIO_EN_PP5000_S5, 1, 10 },
+
+	{ GPIO_EN_PP1800_S5, 1, 0 },
+
+	{ GPIO_EN_PP1800_VDDIO_PMC_X, 1, 4 },
+
+	{ GPIO_EN_PP0800_VDD_PMC_X, 1, 0 },   { GPIO_EN_VDD_SOC, 1, 4 },
+
+	{ GPIO_EN_PP1800_VDD33_PMC_X, 1, 0 },
+};
+
+/* This is the power sequence for POWER_S5S3. */
+static const struct power_seq_op s5s3_power_seq[] = {
+	{ GPIO_EN_PP1800_S3, 1, 0 },	{ GPIO_EN_PP1820A_IO_X, 1, 4 },
+
+	{ GPIO_EN_PP3300_S3, 1, 0 },	{ GPIO_EN_PP3300A_IO_X, 1, 4 },
+
+	{ GPIO_EN_VDD_DDR, 1, 4 },
+
+	{ GPIO_EN_VDD1_VDD2_VR, 1, 4 }, /* LPDDR */
+
+	{ GPIO_EN_VDDQ_VR_D, 1, 4 }, /* LPDDR */
+
+	{ GPIO_EN_VDD_MEDIA_ML, 1, 0 }, { GPIO_EN_VDD_GPU, 1, 0 },
+	{ GPIO_EN_VDD_CPU, 1, 0 },
+};
+
+/* The power sequence for POWER_S5G3 */
+static const struct power_seq_op s5g3_power_seq[] = {
+	{ GPIO_EN_PP1800_VDD33_PMC_X, 0, 4 },
+
+	{ GPIO_EN_VDD_SOC, 0, 0 },
+
+	{ GPIO_EN_PP0800_VDD_PMC_X, 0, 4 },
+
+	{ GPIO_EN_PP1800_VDDIO_PMC_X, 0, 4 },
+
+	{ GPIO_EN_PP1800_S5, 0, 4 },
+
+	{ GPIO_EN_PP5000_S5, 0, 4 },
+};
+
+/* most recently received sleep event */
+static enum host_sleep_event ap_sleep_event;
+/* indicator for shutdown AP */
+static char ap_shutdown;
+/* indicator for boot AP from off state */
+static char boot_from_off;
+
+static void reset_request_interrupt_deferred(void)
+{
+	chipset_reset(CHIPSET_RESET_AP_REQ);
+}
+DECLARE_DEFERRED(reset_request_interrupt_deferred);
+
+void chipset_force_shutdown(enum chipset_shutdown_reason reason)
+{
+	CPRINTS("%s(%d)", __func__, reason);
+	report_ap_reset(reason);
+
+	/*
+	 * Force power off. This condition will reset once the state machine
+	 * transitions to G3.
+	 */
+	ap_shutdown = 1;
+	task_wake(TASK_ID_CHIPSET);
+}
+
+void chipset_force_shutdown_button(void)
+{
+	chipset_force_shutdown(CHIPSET_SHUTDOWN_BUTTON);
+}
+DECLARE_DEFERRED(chipset_force_shutdown_button);
+
+void chipset_exit_hard_off_button(void)
+{
+	/* Power up from off */
+	ap_shutdown = 0;
+	boot_from_off = 1;
+	CPRINTS("PWRON:BTN");
+	chipset_exit_hard_off();
+}
+DECLARE_DEFERRED(chipset_exit_hard_off_button);
+
+void chipset_reset_request_interrupt(enum gpio_signal signal)
+{
+	/*
+	 * indicator for the following reset is a reboot or a AP requested
+	 * shutdown.
+	 */
+	static char want_reboot;
+
+	if (signal == GPIO_AP_EC_WARM_RST_REQ) {
+		CPRINTS("AP wants reboot");
+		hook_call_deferred(&reset_request_interrupt_deferred_data, 0);
+		want_reboot = 1;
+	} else if (signal == GPIO_AP_EC_SHUTDOWN_REQ_L) {
+		/*
+		 * When AP_SHUTDOWN_REQ_L is asserted, we have to check if
+		 * there is a AP_EC_WARM_RST_REQ interrupt prior to this one,
+		 * and that would be a reboot request, rather than a
+		 * shutdown. In the meantime, the WDT should not be asserted,
+		 * or this is a WDT reset, which will be handled by AP.
+		 */
+		if (gpio_get_level(GPIO_AP_EC_WATCHDOG_L) &&
+		    !gpio_get_level(signal) && !want_reboot) {
+			CPRINTS("AP wants shutdown");
+			ap_shutdown = 1;
+		}
+		want_reboot = 0;
+	}
+	power_signal_interrupt(signal);
+}
+
+enum power_state power_chipset_init(void)
+{
+	uint32_t reset_flags = system_get_reset_flags();
+	int exit_hard_off = 1;
+
+	/* Enable reboot / sleep control inputs from AP */
+	gpio_enable_interrupt(GPIO_AP_EC_WARM_RST_REQ);
+	gpio_enable_interrupt(GPIO_AP_EC_SHUTDOWN_REQ_L);
+
+	if (reset_flags & EC_RESET_FLAG_SYSJUMP) {
+		if ((power_get_signals() & IN_ALL_S0) == IN_ALL_S0) {
+			disable_sleep(SLEEP_MASK_AP_RUN);
+			CPRINTS("already in S0");
+			return POWER_S0;
+		}
+	} else if (reset_flags & EC_RESET_FLAG_AP_OFF) {
+		exit_hard_off = 0;
+	} else if ((reset_flags & EC_RESET_FLAG_HIBERNATE) &&
+		   gpio_get_level(GPIO_AC_PRESENT)) {
+		/*
+		 * If AC present, assume this is a wake-up by AC insert.
+		 * Boot EC only.
+		 *
+		 * Note that extpower module is not initialized at this point,
+		 * the only way is to ask GPIO_AC_PRESENT directly.
+		 */
+		exit_hard_off = 0;
+	}
+
+	if (battery_is_present() == BP_YES)
+		/*
+		 * (crosbug.com/p/28289): Wait battery stable.
+		 * Some batteries use clock stretching feature, which requires
+		 * more time to be stable.
+		 */
+		battery_wait_for_stable();
+
+	if (exit_hard_off) {
+		CPRINTS("PWRON:0x%x", reset_flags);
+		ap_shutdown = 0;
+		boot_from_off = 1;
+		/* Auto-power on */
+		chipset_exit_hard_off();
+	}
+
+	/* Start from S5 if the rail is already up. */
+	if (power_get_signals() & IN_PG_S5) {
+		/* Force shutdown from S5 if the rails is already up. */
+		if (!exit_hard_off)
+			ap_shutdown = 1;
+		return POWER_S5;
+	}
+
+	return POWER_G3;
+}
+
+void chipset_reset(enum chipset_shutdown_reason reason)
+{
+	CPRINTS("%s: %d", __func__, reason);
+	report_ap_reset(reason);
+
+	GPIO_SET_LEVEL(GPIO_SYS_RST_ODL, 0);
+	usleep(SYS_RST_PULSE_LENGTH);
+	GPIO_SET_LEVEL(GPIO_SYS_RST_ODL, 1);
+}
+/**
+ * Step through the power sequence table and do corresponding GPIO operations.
+ *
+ * @param	power_seq_ops	The pointer to the power sequence table.
+ * @param	op_count	The number of entries of power_seq_ops.
+ */
+static void power_seq_run(const struct power_seq_op *power_seq_ops,
+			  int op_count)
+{
+	int i;
+
+	for (i = 0; i < op_count; i++) {
+		GPIO_SET_LEVEL(power_seq_ops[i].signal, power_seq_ops[i].level);
+		if (!power_seq_ops[i].delay)
+			continue;
+		msleep(power_seq_ops[i].delay);
+	}
+}
+
+enum power_state power_handle_state(enum power_state state)
+{
+	/* Retry S5->S3 transition, if not zero. */
+	static int s5s3_retry;
+
+	switch (state) {
+	case POWER_G3:
+		break;
+
+	case POWER_S5:
+		if (boot_from_off) {
+			s5s3_retry = 1;
+			return POWER_S5S3;
+		}
+
+		/*
+		 * Stay in S5, common code will drop to G3 after timeout
+		 * if the long press does not work.
+		 */
+		return POWER_S5;
+	case POWER_S3:
+		if (!power_has_signals(IN_PGOOD) || ap_shutdown)
+			return POWER_S3S5;
+		else if (ap_sleep_event == HOST_SLEEP_EVENT_S3_RESUME ||
+			 boot_from_off)
+			return POWER_S3S0;
+		break;
+
+	case POWER_S0:
+		if (ap_sleep_event == HOST_SLEEP_EVENT_S3_SUSPEND ||
+		    !power_has_signals(IN_ALL_S0) || ap_shutdown)
+			return POWER_S0S3;
+		break;
+
+	case POWER_G3S5:
+		ap_shutdown = 0;
+		power_seq_run(g3s5_power_seq, ARRAY_SIZE(g3s5_power_seq));
+
+		/* Power up to next state, or go back */
+		if (power_get_signals() & IN_PG_S5)
+			return POWER_S5;
+		else
+			return POWER_G3;
+		break;
+
+	case POWER_S5S3:
+		hook_notify(HOOK_CHIPSET_PRE_INIT);
+
+		power_seq_run(s5s3_power_seq, ARRAY_SIZE(s5s3_power_seq));
+
+		/*
+		 * Wait for rails up. Retry if it fails
+		 * (it may take 2 attempts on restart after we use
+		 * force reset).
+		 */
+		if (!power_has_signals(IN_ALL_S3)) {
+			if (s5s3_retry) {
+				s5s3_retry = 0;
+				return POWER_S5S3;
+			}
+			boot_from_off = 0;
+			/* Give up, go back to G3. */
+			return POWER_S5G3;
+		}
+
+		GPIO_SET_LEVEL(GPIO_SYS_RST_ODL, 1);
+
+		/* Call hooks now that rails are up */
+		hook_notify(HOOK_CHIPSET_STARTUP);
+
+		/* Power up to next state */
+		return POWER_S3;
+
+	case POWER_S3S5:
+		/* Call hooks before we remove power rails */
+		hook_notify(HOOK_CHIPSET_SHUTDOWN);
+
+		GPIO_SET_LEVEL(GPIO_SYS_RST_ODL, 0);
+		power_seq_run(s3s5_power_seq, ARRAY_SIZE(s3s5_power_seq));
+
+		/* Call hooks after we remove power rails */
+		hook_notify(HOOK_CHIPSET_SHUTDOWN_COMPLETE);
+
+		/* Start shutting down */
+		return POWER_S5;
+
+	case POWER_S0S3:
+		/* Call hooks before we remove power rails */
+		hook_notify(HOOK_CHIPSET_SUSPEND);
+
+		/*
+		 * Enable idle task deep sleep. Allow the low power idle task
+		 * to go into deep sleep in S3 or lower.
+		 */
+		enable_sleep(SLEEP_MASK_AP_RUN);
+
+		/*
+		 * In case the power button is held awaiting power-off timeout,
+		 * power off immediately now that we're entering S3.
+		 */
+		if (power_button_is_pressed()) {
+			ap_shutdown = 1;
+			hook_call_deferred(&chipset_force_shutdown_button_data,
+					   -1);
+		}
+
+		return POWER_S3;
+
+	case POWER_S3S0:
+		if (power_wait_signals(IN_ALL_S0)) {
+			chipset_force_shutdown(CHIPSET_SHUTDOWN_WAIT);
+			return POWER_S0S3;
+		}
+		boot_from_off = 0;
+
+		/* Call hooks now that rails are up */
+		hook_notify(HOOK_CHIPSET_RESUME);
+
+		/*
+		 * Disable idle task deep sleep. This means that the low
+		 * power idle task will not go into deep sleep while in S0.
+		 */
+		disable_sleep(SLEEP_MASK_AP_RUN);
+
+		/* Power up to next state */
+		return POWER_S0;
+
+	case POWER_S5G3:
+		power_seq_run(s5g3_power_seq, ARRAY_SIZE(s5g3_power_seq));
+		return POWER_G3;
+
+	default:
+		CPRINTS("Unexpected power state %d", state);
+		ASSERT(0);
+		break;
+	}
+
+	return state;
+}
+
+static void power_button_changed(void)
+{
+	if (power_button_is_pressed()) {
+		if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+			hook_call_deferred(&chipset_exit_hard_off_button_data,
+					   POWERBTN_BOOT_DELAY);
+
+		/* Delayed power down from S0/S3, cancel on PB release */
+		hook_call_deferred(&chipset_force_shutdown_button_data,
+				   FORCED_SHUTDOWN_DELAY);
+	} else {
+		/* Power button released, cancel deferred shutdown/boot */
+		hook_call_deferred(&chipset_exit_hard_off_button_data, -1);
+		hook_call_deferred(&chipset_force_shutdown_button_data, -1);
+	}
+}
+DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, power_button_changed, HOOK_PRIO_DEFAULT);
+
+#ifdef CONFIG_POWER_TRACK_HOST_SLEEP_STATE
+__override void
+power_chipset_handle_host_sleep_event(enum host_sleep_event state,
+				      struct host_sleep_event_context *ctx)
+{
+	CPRINTS("Handle sleep: %d", state);
+
+	ap_sleep_event = state;
+
+	if (state == HOST_SLEEP_EVENT_S3_RESUME ||
+	    state == HOST_SLEEP_EVENT_S3_SUSPEND)
+		task_wake(TASK_ID_CHIPSET);
+}
+#endif /* CONFIG_POWER_TRACK_HOST_SLEEP_STATE */
+
+#ifdef CONFIG_LID_SWITCH
+static void lid_changed(void)
+{
+	/* Power-up from off on lid open */
+	if (lid_is_open() && chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
+		CPRINTS("PWRON:LIDOPEN");
+		ap_shutdown = 0;
+		boot_from_off = 1;
+		chipset_exit_hard_off();
+	}
+}
+DECLARE_HOOK(HOOK_LID_CHANGE, lid_changed, HOOK_PRIO_DEFAULT);
+#endif
diff --git a/power/hibernate.c b/power/hibernate.c
new file mode 100644
index 0000000000..02e4728ad2
--- /dev/null
+++ b/power/hibernate.c
@@ -0,0 +1,181 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "extpower.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "system.h"
+#include "util.h"
+
+#include <zephyr/init.h>
+#include <zephyr/logging/log.h>
+
+#include <ap_power/ap_power.h>
+#include <ap_power/ap_power_interface.h>
+
+LOG_MODULE_DECLARE(ap_pwrseq, CONFIG_AP_PWRSEQ_LOG_LEVEL);
+
+/*
+ * Hibernate processing.
+ *
+ * When enabled, the system will be put into an extreme low
+ * power state after the AP is in G3 for a configurable period of time,
+ * and there is no external power connected (i.e on battery).
+ *
+ * The delay has a configurable default, and may be set dynamically
+ * via a host command, or an EC console command. A typical delay
+ * may be 1 hour (3600 seconds).
+ *
+ * AP events such as AP_POWER_HARD_OFF are listened for, and
+ * a timer is used to detect when the AP has been off for the
+ * selected delay time. If the AP is started again, the timer is canceled.
+ * Once the timer expires, the system_hibernate() function is called,
+ * and this will suspend the EC until a wake signal is received.
+ */
+static uint32_t hibernate_delay = CONFIG_HIBERNATE_DELAY_SEC;
+
+/*
+ * Return true if conditions are right for hibernation.
+ */
+static inline bool ready_to_hibernate(void)
+{
+	return ap_power_in_or_transitioning_to_state(AP_POWER_STATE_HARD_OFF) &&
+	       !extpower_is_present();
+}
+
+/*
+ * The AP has been off for the delay period, so hibernate the system,
+ * if ready.  Called from system work queue.
+ */
+static void hibernate_handler(struct k_work *unused)
+{
+	if (ready_to_hibernate()) {
+		LOG_INF("System hibernating due to %d seconds AP off",
+			hibernate_delay);
+		system_hibernate(0, 0);
+	}
+}
+
+K_WORK_DEFINE(hibernate_work, hibernate_handler);
+
+/*
+ * Hibernate timer handler.
+ * Called when timer has expired.
+ * Schedule hibernate_handler to run via system work queue.
+ */
+static void timer_handler(struct k_timer *timer)
+{
+	k_work_submit(&hibernate_work);
+}
+
+K_TIMER_DEFINE(hibernate_timer, timer_handler, NULL);
+
+/*
+ * A change has been detected in either the AP state or the
+ * external power supply.
+ */
+static void change_detected(void)
+{
+	if (ready_to_hibernate()) {
+		/*
+		 * AP is off, and there is no external power.
+		 * Start the timer if it is not already running.
+		 */
+		if (k_timer_remaining_get(&hibernate_timer) == 0) {
+			k_timer_start(&hibernate_timer,
+				      K_SECONDS(hibernate_delay), K_NO_WAIT);
+		}
+
+	} else {
+		/*
+		 * AP is either on, or external power is on.
+		 * Either way, no hibernation is done.
+		 * Make sure the timer is not running.
+		 */
+		k_timer_stop(&hibernate_timer);
+	}
+}
+
+static void ap_change(struct ap_power_ev_callback *callback,
+		      struct ap_power_ev_data data)
+{
+	change_detected();
+}
+
+/*
+ * Hook to listen for external power supply changes.
+ */
+DECLARE_HOOK(HOOK_AC_CHANGE, change_detected, HOOK_PRIO_DEFAULT);
+
+/*
+ * EC Console command to get/set the hibernation delay
+ */
+static int command_hibernation_delay(int argc, const char **argv)
+{
+	char *e;
+	uint32_t remaining;
+
+	if (argc >= 2) {
+		uint32_t s = strtoi(argv[1], &e, 0);
+
+		if (*e)
+			return EC_ERROR_PARAM1;
+
+		hibernate_delay = s;
+	}
+
+	/* Print the current setting */
+	ccprintf("Hibernation delay: %d s\n", hibernate_delay);
+	remaining = k_timer_remaining_get(&hibernate_timer);
+	if (remaining == 0) {
+		ccprintf("Timer not running\n");
+	} else {
+		ccprintf("Time remaining: %d s\n", remaining / 1000);
+	}
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(hibdelay, command_hibernation_delay, "[sec]",
+			"Set the delay before going into hibernation");
+/*
+ * Host command to set the hibernation delay
+ */
+static enum ec_status
+host_command_hibernation_delay(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_hibernation_delay *p = args->params;
+	struct ec_response_hibernation_delay *r = args->response;
+
+	/* Only change the hibernation delay if seconds is non-zero. */
+	if (p->seconds)
+		hibernate_delay = p->seconds;
+
+	r->hibernate_delay = hibernate_delay;
+	/*
+	 * It makes no sense to try and set these values since
+	 * they are only valid when the AP is in G3 (so this
+	 * host command will never be called at that point).
+	 */
+	r->time_g3 = 0;
+	r->time_remaining = 0;
+
+	args->response_size = sizeof(struct ec_response_hibernation_delay);
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_HIBERNATION_DELAY, host_command_hibernation_delay,
+		     EC_VER_MASK(0));
+
+static int hibernate_init(void)
+{
+	static struct ap_power_ev_callback cb;
+
+	ap_power_ev_init_callback(&cb, ap_change,
+				  AP_POWER_INITIALIZED | AP_POWER_HARD_OFF |
+					  AP_POWER_STARTUP);
+	ap_power_ev_add_callback(&cb);
+	return 0;
+}
+
+SYS_INIT(hibernate_init, APPLICATION, CONFIG_APPLICATION_INIT_PRIORITY);
diff --git a/power/host_sleep.c b/power/host_sleep.c
index 54a308d6c3..d16cb73dc6 100644
--- a/power/host_sleep.c
+++ b/power/host_sleep.c
@@ -1,8 +1,10 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "config.h"
+#include "console.h"
 #include "ec_commands.h"
 #include "hooks.h"
 #include "host_command.h"
@@ -10,18 +12,21 @@
 #include "util.h"
 
 /* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ##args)
 
 /* Track last reported sleep event */
 static enum host_sleep_event host_sleep_state;
 
-__overridable void power_chipset_handle_host_sleep_event(
-		enum host_sleep_event state,
-		struct host_sleep_event_context *ctx)
+/* LCOV_EXCL_START */
+/* Function stub that has no behavior, so ignoring for coverage */
+__overridable void
+power_chipset_handle_host_sleep_event(enum host_sleep_event state,
+				      struct host_sleep_event_context *ctx)
 {
 	/* Default weak implementation -- no action required. */
 }
+/* LCOV_EXCL_STOP */
 
 static enum ec_status
 host_command_host_sleep_event(struct host_cmd_handler_args *args)
@@ -31,6 +36,13 @@ host_command_host_sleep_event(struct host_cmd_handler_args *args)
 	struct host_sleep_event_context ctx;
 	enum host_sleep_event state = p->sleep_event;
 
+	/*
+	 * Treat a reboot after suspend as a resume for notification purposes
+	 * (see b/273327518 for more details)
+	 */
+	if (host_sleep_state == HOST_SLEEP_EVENT_S0IX_SUSPEND && state == 0)
+		state = HOST_SLEEP_EVENT_S0IX_RESUME;
+
 	host_sleep_state = state;
 	ctx.sleep_transitions = 0;
 	switch (state) {
@@ -69,8 +81,7 @@ host_command_host_sleep_event(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_HOST_SLEEP_EVENT,
-		     host_command_host_sleep_event,
+DECLARE_HOST_COMMAND(EC_CMD_HOST_SLEEP_EVENT, host_command_host_sleep_event,
 		     EC_VER_MASK(0) | EC_VER_MASK(1));
 
 enum host_sleep_event power_get_host_sleep_state(void)
@@ -83,9 +94,8 @@ void power_set_host_sleep_state(enum host_sleep_event state)
 	host_sleep_state = state;
 }
 
-#ifdef CONFIG_POWER_SLEEP_FAILURE_DETECTION
 /* Flag to notify listeners about suspend/resume events. */
-enum sleep_notify_type sleep_notify = SLEEP_NOTIFY_NONE;
+static enum sleep_notify_type sleep_notify = SLEEP_NOTIFY_NONE;
 
 /*
  * Note: the following sleep_ functions do not get called in the S3 path on
@@ -96,7 +106,7 @@ void sleep_set_notify(enum sleep_notify_type notify)
 	sleep_notify = notify;
 }
 
-void sleep_notify_transition(int check_state, int hook_id)
+void sleep_notify_transition(enum sleep_notify_type check_state, int hook_id)
 {
 	if (sleep_notify != check_state)
 		return;
@@ -105,13 +115,44 @@ void sleep_notify_transition(int check_state, int hook_id)
 	sleep_set_notify(SLEEP_NOTIFY_NONE);
 }
 
+#ifdef CONFIG_POWERSEQ_S0IX_COUNTER
+atomic_t s0ix_counter;
+
+static void handle_chipset_suspend(void)
+{
+	atomic_inc(&s0ix_counter);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, handle_chipset_suspend, HOOK_PRIO_LAST);
+#endif /* CONFIG_POWERSEQ_S0IX_COUNTER */
+
+#ifdef CONFIG_POWER_SLEEP_FAILURE_DETECTION
+
 static uint16_t sleep_signal_timeout;
+/* Non-const because it may be set by sleeptimeout console cmd */
+static uint16_t host_sleep_timeout_default = CONFIG_SLEEP_TIMEOUT_MS;
 static uint32_t sleep_signal_transitions;
-static void (*sleep_timeout_callback)(void);
+static enum sleep_hang_type timeout_hang_type;
 
 static void sleep_transition_timeout(void);
 DECLARE_DEFERRED(sleep_transition_timeout);
 
+/* LCOV_EXCL_START */
+/* Function stub that has no behavior, so ignoring for coverage */
+__overridable void power_board_handle_sleep_hang(enum sleep_hang_type hang_type)
+{
+	/* Default empty implementation */
+}
+/* LCOV_EXCL_STOP */
+
+/* LCOV_EXCL_START */
+/* Function stub that has no behavior, so ignoring for coverage */
+__overridable void
+power_chipset_handle_sleep_hang(enum sleep_hang_type hang_type)
+{
+	/* Default empty implementation */
+}
+/* LCOV_EXCL_STOP */
+
 static void sleep_increment_transition(void)
 {
 	if ((sleep_signal_transitions & EC_HOST_RESUME_SLEEP_TRANSITIONS_MASK) <
@@ -136,9 +177,11 @@ void sleep_resume_transition(void)
 	 * internal periodic housekeeping code might result in a situation
 	 * like this.
 	 */
-	if (sleep_signal_timeout)
+	if (sleep_signal_timeout) {
+		timeout_hang_type = SLEEP_HANG_S0IX_RESUME;
 		hook_call_deferred(&sleep_transition_timeout_data,
 				   (uint32_t)sleep_signal_timeout * 1000);
+	}
 }
 
 static void sleep_transition_timeout(void)
@@ -147,35 +190,43 @@ static void sleep_transition_timeout(void)
 	sleep_signal_transitions |= EC_HOST_RESUME_SLEEP_TIMEOUT;
 	hook_call_deferred(&sleep_transition_timeout_data, -1);
 
-	/* Call the custom callback */
-	if (sleep_timeout_callback)
-		sleep_timeout_callback();
+	if (timeout_hang_type != SLEEP_HANG_NONE) {
+		power_chipset_handle_sleep_hang(timeout_hang_type);
+		power_board_handle_sleep_hang(timeout_hang_type);
+	}
 }
 
-void sleep_start_suspend(struct host_sleep_event_context *ctx,
-			 void (*callback)(void))
+void sleep_start_suspend(struct host_sleep_event_context *ctx)
 {
 	uint16_t timeout = ctx->sleep_timeout_ms;
 
-	sleep_timeout_callback = callback;
 	sleep_signal_transitions = 0;
 
-	/* Use zero internally to indicate no timeout. */
+	/* Use default to indicate no timeout given. */
 	if (timeout == EC_HOST_SLEEP_TIMEOUT_DEFAULT) {
-		timeout = CONFIG_SLEEP_TIMEOUT_MS;
+		timeout = host_sleep_timeout_default;
+	}
 
-	} else if (timeout == EC_HOST_SLEEP_TIMEOUT_INFINITE) {
+	/* Use 0xFFFF to disable the timeout */
+	if (timeout == EC_HOST_SLEEP_TIMEOUT_INFINITE) {
 		sleep_signal_timeout = 0;
 		return;
 	}
 
 	sleep_signal_timeout = timeout;
+	timeout_hang_type = SLEEP_HANG_S0IX_SUSPEND;
 	hook_call_deferred(&sleep_transition_timeout_data,
 			   (uint32_t)timeout * 1000);
 }
 
 void sleep_complete_resume(struct host_sleep_event_context *ctx)
 {
+	/*
+	 * Ensure we don't schedule another sleep_transition_timeout
+	 * if the the HOST_SLEEP_EVENT_S0IX_RESUME message arrives before
+	 * the CHIPSET task transitions to the POWER_S0ixS0 state.
+	 */
+	sleep_signal_timeout = 0;
 	hook_call_deferred(&sleep_transition_timeout_data, -1);
 	ctx->sleep_transitions = sleep_signal_transitions;
 }
@@ -184,20 +235,54 @@ void sleep_reset_tracking(void)
 {
 	sleep_signal_transitions = 0;
 	sleep_signal_timeout = 0;
-	sleep_timeout_callback = NULL;
+	timeout_hang_type = SLEEP_HANG_NONE;
 }
 
-#else /* !CONFIG_POWER_SLEEP_FAILURE_DETECTION */
-
-/* No action */
-void sleep_set_notify(enum sleep_notify_type notify)
+static int command_sleep_fail_timeout(int argc, const char **argv)
 {
-}
+	if (argc < 2) {
+		/* no arguments - just print the current timeout */
+	} else if (!strcasecmp(argv[1], "default")) {
+		host_sleep_timeout_default = CONFIG_SLEEP_TIMEOUT_MS;
+	} else if (!strcasecmp(argv[1], "infinite")) {
+		host_sleep_timeout_default = EC_HOST_SLEEP_TIMEOUT_INFINITE;
+	} else {
+		char *e;
+		int val;
+
+		val = strtoi(argv[1], &e, 10);
+		if (*e)
+			return EC_ERROR_PARAM1;
+
+		if (val <= 0 || val >= EC_HOST_SLEEP_TIMEOUT_INFINITE) {
+			ccprintf("Error: timeout range is 1..%d [msec]\n",
+				 EC_HOST_SLEEP_TIMEOUT_INFINITE - 1);
+			return EC_ERROR_PARAM1;
+		}
 
-void sleep_notify_transition(int check_state, int hook_id)
-{
+		host_sleep_timeout_default = val;
+	}
+
+	if (host_sleep_timeout_default == EC_HOST_SLEEP_TIMEOUT_INFINITE)
+		ccprintf("Sleep failure detection timeout is disabled\n");
+	else
+		ccprintf("Sleep failure detection timeout is %d [msec]\n",
+			 host_sleep_timeout_default);
+
+	return EC_SUCCESS;
 }
+DECLARE_CONSOLE_COMMAND(sleeptimeout, command_sleep_fail_timeout,
+			"[default | infinite | <msec>]",
+			"Display or set host sleep failure detection timeout.\n"
+			"Valid arguments are:\n"
+			" default\n"
+			" infinite - disables the timeout\n"
+			" <msec> - custom length in milliseconds\n"
+			" <none> - prints the current setting");
+
+#else /* !CONFIG_POWER_SLEEP_FAILURE_DETECTION */
 
+/* No action */
 void sleep_suspend_transition(void)
 {
 }
@@ -206,8 +291,7 @@ void sleep_resume_transition(void)
 {
 }
 
-void sleep_start_suspend(struct host_sleep_event_context *ctx,
-			 void (*callback)(void))
+void sleep_start_suspend(struct host_sleep_event_context *ctx)
 {
 }
 
diff --git a/power/icelake.c b/power/icelake.c
index 7f91e48006..bfa4bff91a 100644
--- a/power/icelake.c
+++ b/power/icelake.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,27 +10,27 @@
 #include "console.h"
 #include "gpio.h"
 #include "hooks.h"
-#include "intel_x86.h"
 #include "power.h"
+#include "power/intel_x86.h"
 #include "power_button.h"
+#include "system_boot_time.h"
 #include "task.h"
 #include "timer.h"
 
 /* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 #ifdef CONFIG_BRINGUP
 #define GPIO_SET_LEVEL(signal, value) \
 	gpio_set_level_verbose(CC_CHIPSET, signal, value)
 #else
-#define GPIO_SET_LEVEL(signal, value) \
-	gpio_set_level(signal, value)
+#define GPIO_SET_LEVEL(signal, value) gpio_set_level(signal, value)
 #endif
 
 /* The wait time is ~150 msec, allow for safety margin. */
-#define IN_PCH_SLP_SUS_WAIT_TIME_USEC	(250 * MSEC)
+#define IN_PCH_SLP_SUS_WAIT_TIME_USEC (250 * MSEC)
 
-static int forcing_shutdown;  /* Forced shutdown in progress? */
+static int forcing_shutdown; /* Forced shutdown in progress? */
 
 /* Power signals list. Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
@@ -41,15 +41,20 @@ const struct power_signal_info power_signal_list[] = {
 		.name = "SLP_S0_DEASSERTED",
 	},
 	[X86_SLP_S3_DEASSERTED] = {
-		.gpio = SLP_S3_SIGNAL_L,
+		.gpio = (enum gpio_signal)SLP_S3_SIGNAL_L,
 		.flags = POWER_SIGNAL_ACTIVE_HIGH,
 		.name = "SLP_S3_DEASSERTED",
 	},
 	[X86_SLP_S4_DEASSERTED] = {
-		.gpio = SLP_S4_SIGNAL_L,
+		.gpio = (enum gpio_signal)SLP_S4_SIGNAL_L,
 		.flags = POWER_SIGNAL_ACTIVE_HIGH,
 		.name = "SLP_S4_DEASSERTED",
 	},
+	[X86_SLP_S5_DEASSERTED] = {
+		.gpio = (enum gpio_signal)SLP_S5_SIGNAL_L,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "SLP_S5_DEASSERTED",
+	},
 	[X86_SLP_SUS_DEASSERTED] = {
 		.gpio = GPIO_SLP_SUS_L,
 		.flags = POWER_SIGNAL_ACTIVE_HIGH,
@@ -114,6 +119,15 @@ void chipset_force_shutdown(enum chipset_shutdown_reason reason)
 	else
 		GPIO_SET_LEVEL(GPIO_EN_PP5000, 0);
 
+	/*
+	 * For JSL, we may not catch the DSW power good transitioning if this
+	 * occurs in suspend as our ADC interrupts are disabled for power
+	 * reasons. Therefore, kick the chipset state machine in order to catch
+	 * up with the current state of affairs.
+	 */
+	if (IS_ENABLED(CONFIG_CHIPSET_JASPERLAKE))
+		power_signal_interrupt(GPIO_PG_EC_DSW_PWROK);
+
 	/*
 	 * TODO(b/111810925): Replace this wait with
 	 * power_wait_signals_timeout()
@@ -138,7 +152,7 @@ void chipset_handle_espi_reset_assert(void)
 	 * power button. If yes, release power button.
 	 */
 	if ((power_get_signals() & IN_PCH_SLP_SUS_DEASSERTED) &&
-		forcing_shutdown) {
+	    forcing_shutdown) {
 		power_button_pch_release();
 		forcing_shutdown = 0;
 	}
@@ -157,7 +171,6 @@ static void enable_pp5000_rail(void)
 		power_5v_enable(task_get_current(), 1);
 	else
 		GPIO_SET_LEVEL(GPIO_EN_PP5000, 1);
-
 }
 
 static void dsw_pwrok_pass_thru(void)
@@ -166,8 +179,8 @@ static void dsw_pwrok_pass_thru(void)
 
 	/* Pass-through DSW_PWROK to ICL. */
 	if (dswpwrok_in != gpio_get_level(GPIO_PCH_DSW_PWROK)) {
-		if (IS_ENABLED(CONFIG_CHIPSET_SLP_S3_L_OVERRIDE)
-			&& dswpwrok_in) {
+#if defined(CONFIG_CHIPSET_SLP_S3_L_OVERRIDE)
+		if (dswpwrok_in) {
 			/*
 			 * Once DSW_PWROK is high, reconfigure SLP_S3_L back to
 			 * an input after a short delay.
@@ -177,6 +190,7 @@ static void dsw_pwrok_pass_thru(void)
 			gpio_reset(SLP_S3_SIGNAL_L);
 			power_signal_enable_interrupt(SLP_S3_SIGNAL_L);
 		}
+#endif
 
 		CPRINTS("Pass thru GPIO_DSW_PWROK: %d", dswpwrok_in);
 		/*
@@ -188,26 +202,13 @@ static void dsw_pwrok_pass_thru(void)
 	}
 }
 
-/*
- * Return 0 if PWROK signal is deasserted, non-zero if asserted
- */
-static int pwrok_signal_get(const struct intel_x86_pwrok_signal *signal)
-{
-	int level = gpio_get_level(signal->gpio);
-
-	if (signal->active_low)
-		level = !level;
-
-	return level;
-}
-
 /*
  * Set the PWROK signal state
  *
  * &param level		0 deasserts the signal, other values assert the signal
  */
 static void pwrok_signal_set(const struct intel_x86_pwrok_signal *signal,
-	int level)
+			     int level)
 {
 	GPIO_SET_LEVEL(signal->gpio, signal->active_low ? !level : level);
 }
@@ -236,10 +237,6 @@ static void all_sys_pwrgd_pass_thru(void)
 	 * to match the current ALL_SYS_PWRGD input.
 	 */
 	for (i = 0; i < signal_count; i++, pwrok_signal++) {
-		if ((!all_sys_pwrgd_in && !pwrok_signal_get(pwrok_signal))
-			|| (all_sys_pwrgd_in && pwrok_signal_get(pwrok_signal)))
-			continue;
-
 		if (pwrok_signal->delay_ms > 0)
 			msleep(pwrok_signal->delay_ms);
 
@@ -260,18 +257,22 @@ enum power_state power_handle_state(enum power_state state)
 	common_intel_x86_handle_rsmrst(state);
 
 	switch (state) {
-
 	case POWER_G3S5:
-		if (IS_ENABLED(CONFIG_CHIPSET_SLP_S3_L_OVERRIDE)) {
-			/*
-			 * Prevent glitches on the SLP_S3_L and PCH_PWROK
-			 * signals while when the PP3300_A rail is turned on.
-			 * Drive SLP_S3_L from the EC until DSW_PWROK is high.
-			 */
-			CPRINTS("Drive SLP_S3_L low during PP3300_A rampup");
-			power_signal_disable_interrupt(SLP_S3_SIGNAL_L);
-			gpio_set_flags(SLP_S3_SIGNAL_L, GPIO_ODR_LOW);
+		if (intel_x86_wait_power_up_ok() != EC_SUCCESS) {
+			chipset_force_shutdown(
+				CHIPSET_SHUTDOWN_BATTERY_INHIBIT);
+			return POWER_G3;
 		}
+#if defined(CONFIG_CHIPSET_SLP_S3_L_OVERRIDE)
+		/*
+		 * Prevent glitches on the SLP_S3_L and PCH_PWROK
+		 * signals while when the PP3300_A rail is turned on.
+		 * Drive SLP_S3_L from the EC until DSW_PWROK is high.
+		 */
+		CPRINTS("Drive SLP_S3_L low during PP3300_A rampup");
+		power_signal_disable_interrupt(SLP_S3_SIGNAL_L);
+		gpio_set_flags(SLP_S3_SIGNAL_L, GPIO_ODR_LOW);
+#endif
 
 		/* Default behavior - turn on PP5000 rail first */
 		if (!IS_ENABLED(CONFIG_CHIPSET_PP3300_RAIL_FIRST))
@@ -285,6 +286,9 @@ enum power_state power_handle_state(enum power_state state)
 		 */
 		/* Turn on the PP3300_DSW rail. */
 		GPIO_SET_LEVEL(GPIO_EN_PP3300_A, 1);
+
+		update_ap_boot_time(ARAIL);
+
 		if (power_wait_signals(IN_PGOOD_ALL_CORE))
 			break;
 
@@ -300,7 +304,8 @@ enum power_state power_handle_state(enum power_state state)
 		 * signal doesn't go high within 250 msec then go back to G3.
 		 */
 		if (power_wait_signals_timeout(IN_PCH_SLP_SUS_DEASSERTED,
-				IN_PCH_SLP_SUS_WAIT_TIME_USEC) != EC_SUCCESS) {
+					       IN_PCH_SLP_SUS_WAIT_TIME_USEC) !=
+		    EC_SUCCESS) {
 			CPRINTS("SLP_SUS_L didn't go high!  Going back to G3.");
 			return POWER_S5G3;
 		}
@@ -321,7 +326,7 @@ enum power_state power_handle_state(enum power_state state)
 		GPIO_SET_LEVEL(GPIO_EN_VCCIO_EXT, 1);
 		/* Now wait for ALL_SYS_PWRGD. */
 		while (!intel_x86_get_pg_ec_all_sys_pwrgd() &&
-			(timeout_ms > 0)) {
+		       (timeout_ms > 0)) {
 			msleep(1);
 			timeout_ms--;
 		};
diff --git a/power/intel_x86.c b/power/intel_x86.c
index 1fdf1b96ea..5efdf20ce4 100644
--- a/power/intel_x86.c
+++ b/power/intel_x86.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,23 +12,25 @@
 #include "ec_commands.h"
 #include "gpio.h"
 #include "hooks.h"
-#include "intel_x86.h"
 #include "lpc.h"
 #include "power.h"
+#include "power/intel_x86.h"
 #include "power_button.h"
 #include "system.h"
+#include "system_boot_time.h"
 #include "task.h"
 #include "util.h"
 #include "vboot.h"
 #include "wireless.h"
 
 /* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ##args)
 
 enum sys_sleep_state {
 	SYS_SLEEP_S3,
 	SYS_SLEEP_S4,
+	SYS_SLEEP_S5,
 #ifdef CONFIG_POWER_S0IX
 	SYS_SLEEP_S0IX,
 #endif
@@ -37,12 +39,13 @@ enum sys_sleep_state {
 static const int sleep_sig[] = {
 	[SYS_SLEEP_S3] = SLP_S3_SIGNAL_L,
 	[SYS_SLEEP_S4] = SLP_S4_SIGNAL_L,
+	[SYS_SLEEP_S5] = SLP_S5_SIGNAL_L,
 #ifdef CONFIG_POWER_S0IX
 	[SYS_SLEEP_S0IX] = GPIO_PCH_SLP_S0_L,
 #endif
 };
 
-static int power_s5_up;       /* Chipset is sequencing up or down */
+static int power_s5_up; /* Chipset is sequencing up or down */
 
 #ifdef CONFIG_CHARGER
 /* Flag to indicate if power up was inhibited due to low battery SOC level. */
@@ -59,7 +62,7 @@ static int is_power_up_inhibited(void)
 	const int power_button_pressed = 0;
 
 	return charge_prevent_power_on(power_button_pressed) ||
-		charge_want_shutdown();
+	       charge_want_shutdown();
 }
 
 static void power_up_inhibited_cb(void)
@@ -103,7 +106,8 @@ static enum power_state power_wait_s5_rtc_reset(void)
 	while ((power_get_signals() & IN_PCH_SLP_S4_DEASSERTED) == 0) {
 		/* Handle RSMRST passthru event while waiting */
 		common_intel_x86_handle_rsmrst(POWER_S5);
-		if (task_wait_event(SECOND*4) == TASK_EVENT_TIMER) {
+		if (task_wait_event(SECOND * CONFIG_S5_EXIT_WAIT) ==
+		    TASK_EVENT_TIMER) {
 			CPRINTS("timeout waiting for S5 exit");
 			chipset_force_g3();
 
@@ -121,7 +125,7 @@ static enum power_state power_wait_s5_rtc_reset(void)
 	}
 
 	s5_exit_tries = 0;
-	return POWER_S5S3; /* Power up to next state */
+	return POWER_S5S4; /* Power up to next state */
 }
 #endif
 
@@ -176,7 +180,7 @@ static void lpc_s0ix_resume_restore_masks(void)
 	backup_sci_mask = backup_smi_mask = 0;
 }
 
-static void lpc_s0ix_hang_detected(void)
+__override void power_chipset_handle_sleep_hang(enum sleep_hang_type hang_type)
 {
 	/*
 	 * Wake up the AP so they don't just chill in a non-suspended state and
@@ -255,8 +259,8 @@ enum power_state power_chipset_init(void)
 		CPRINTS("already in S0");
 		return POWER_S0;
 	}
-	if ((power_get_signals() & CHIPSET_G3S5_POWERUP_SIGNAL)
-			== CHIPSET_G3S5_POWERUP_SIGNAL) {
+	if ((power_get_signals() & CHIPSET_G3S5_POWERUP_SIGNAL) ==
+	    CHIPSET_G3S5_POWERUP_SIGNAL) {
 		/* case #2 & #3 */
 		CPRINTS("already in S5");
 		return POWER_S5;
@@ -279,22 +283,34 @@ enum power_state common_intel_x86_power_handle_state(enum power_state state)
 			return power_wait_s5_rtc_reset();
 #endif
 
-		if (chipset_get_sleep_signal(SYS_SLEEP_S4) == 1)
-			return POWER_S5S3; /* Power up to next state */
+		if (chipset_get_sleep_signal(SYS_SLEEP_S5) == 1)
+			return POWER_S5S4; /* Power up to next state */
+		break;
+
+	case POWER_S4:
+		if (chipset_get_sleep_signal(SYS_SLEEP_S5) == 0) {
+			/* Power down to next state */
+			return POWER_S4S5;
+		} else if (chipset_get_sleep_signal(SYS_SLEEP_S4) == 1) {
+			/* Power up to the next level */
+			return POWER_S4S3;
+		}
+
 		break;
 
 	case POWER_S3:
 		if (!power_has_signals(IN_PGOOD_ALL_CORE)) {
-			/* Required rail went away */
+			/* Required rail went away, go straight to S5 */
 			chipset_force_shutdown(CHIPSET_SHUTDOWN_POWERFAIL);
 			return POWER_S3S5;
 		} else if (chipset_get_sleep_signal(SYS_SLEEP_S3) == 1) {
 			/* Power up to next state */
 			return POWER_S3S0;
 		} else if (chipset_get_sleep_signal(SYS_SLEEP_S4) == 0) {
-			/* Power down to next state */
-			return POWER_S3S5;
+			/* Power down to the next state */
+			return POWER_S3S4;
 		}
+
 		break;
 
 	case POWER_S0:
@@ -305,16 +321,16 @@ enum power_state common_intel_x86_power_handle_state(enum power_state state)
 			/* Power down to next state */
 			return POWER_S0S3;
 #ifdef CONFIG_POWER_S0IX
-		/*
-		 * SLP_S0 may assert in system idle scenario without a kernel
-		 * freeze call. This may cause interrupt storm since there is
-		 * no freeze/unfreeze of threads/process in the idle scenario.
-		 * Ignore the SLP_S0 assertions in idle scenario by checking
-		 * the host sleep state.
-		 */
-		} else if (power_get_host_sleep_state()
-					== HOST_SLEEP_EVENT_S0IX_SUSPEND &&
-				chipset_get_sleep_signal(SYS_SLEEP_S0IX) == 0) {
+			/*
+			 * SLP_S0 may assert in system idle scenario without a
+			 * kernel freeze call. This may cause interrupt storm
+			 * since there is no freeze/unfreeze of threads/process
+			 * in the idle scenario. Ignore the SLP_S0 assertions in
+			 * idle scenario by checking the host sleep state.
+			 */
+		} else if (power_get_host_sleep_state() ==
+				   HOST_SLEEP_EVENT_S0IX_SUSPEND &&
+			   chipset_get_sleep_signal(SYS_SLEEP_S0IX) == 0) {
 			return POWER_S0S0ix;
 		} else {
 			sleep_notify_transition(SLEEP_NOTIFY_RESUME,
@@ -328,7 +344,7 @@ enum power_state common_intel_x86_power_handle_state(enum power_state state)
 	case POWER_S0ix:
 		/* System in S0 only if SLP_S0 and SLP_S3 are de-asserted */
 		if ((chipset_get_sleep_signal(SYS_SLEEP_S0IX) == 1) &&
-		   (chipset_get_sleep_signal(SYS_SLEEP_S3) == 1)) {
+		    (chipset_get_sleep_signal(SYS_SLEEP_S3) == 1)) {
 			return POWER_S0ixS0;
 		} else if (!power_has_signals(IN_PGOOD_ALL_CORE)) {
 			return POWER_S0;
@@ -359,7 +375,15 @@ enum power_state common_intel_x86_power_handle_state(enum power_state state)
 		power_s5_up = 1;
 		return POWER_S5;
 
+	case POWER_S5S4:
+		return POWER_S4; /* Power up to next state */
+
+	case POWER_S3S4:
+		return POWER_S4; /* Power down to the next state */
+
 	case POWER_S5S3:
+		__fallthrough;
+	case POWER_S4S3:
 		if (!power_has_signals(IN_PGOOD_ALL_CORE)) {
 			/* Required rail went away */
 			chipset_force_shutdown(CHIPSET_SHUTDOWN_POWERFAIL);
@@ -380,7 +404,7 @@ enum power_state common_intel_x86_power_handle_state(enum power_state state)
 
 	case POWER_S3S0:
 		if (!power_has_signals(IN_PGOOD_ALL_CORE)) {
-			/* Required rail went away */
+			/* Required rail went away, go straight back to S5 */
 			chipset_force_shutdown(CHIPSET_SHUTDOWN_POWERFAIL);
 			return POWER_S3S5;
 		}
@@ -390,6 +414,10 @@ enum power_state common_intel_x86_power_handle_state(enum power_state state)
 
 		lpc_s3_resume_clear_masks();
 
+#ifdef CONFIG_CHIPSET_RESUME_INIT_HOOK
+		/* Call hooks prior to chipset resume */
+		hook_notify(HOOK_CHIPSET_RESUME_INIT);
+#endif
 		/* Call hooks now that rails are up */
 		hook_notify(HOOK_CHIPSET_RESUME);
 
@@ -412,8 +440,13 @@ enum power_state common_intel_x86_power_handle_state(enum power_state state)
 		return POWER_S0;
 
 	case POWER_S0S3:
+
 		/* Call hooks before we remove power rails */
 		hook_notify(HOOK_CHIPSET_SUSPEND);
+#ifdef CONFIG_CHIPSET_RESUME_INIT_HOOK
+		/* Call hooks after chipset suspend */
+		hook_notify(HOOK_CHIPSET_SUSPEND_COMPLETE);
+#endif
 
 		/* Suspend wireless */
 		wireless_set_state(WIRELESS_SUSPEND);
@@ -445,6 +478,11 @@ enum power_state common_intel_x86_power_handle_state(enum power_state state)
 		 * to go into deep sleep in S0ix.
 		 */
 		enable_sleep(SLEEP_MASK_AP_RUN);
+
+#ifdef CONFIG_CHIPSET_RESUME_INIT_HOOK
+		hook_notify(HOOK_CHIPSET_SUSPEND_COMPLETE);
+#endif
+
 		return POWER_S0ix;
 
 	case POWER_S0ixS0:
@@ -454,11 +492,17 @@ enum power_state common_intel_x86_power_handle_state(enum power_state state)
 		 */
 		disable_sleep(SLEEP_MASK_AP_RUN);
 
+#ifdef CONFIG_CHIPSET_RESUME_INIT_HOOK
+		hook_notify(HOOK_CHIPSET_RESUME_INIT);
+#endif
+
 		sleep_resume_transition();
 		return POWER_S0;
 #endif
 
 	case POWER_S3S5:
+		/* fallthrough */
+	case POWER_S4S5:
 		/* Call hooks before we remove power rails */
 		hook_notify(HOOK_CHIPSET_SHUTDOWN);
 
@@ -485,9 +529,30 @@ enum power_state common_intel_x86_power_handle_state(enum power_state state)
 	return state;
 }
 
+#ifdef GPIO_PCH_DSW_PWROK
+void intel_x86_pwrok_signal_interrupt(enum gpio_signal signal)
+{
+	int in = gpio_get_level(GPIO_PG_EC_DSW_PWROK);
+	int out = gpio_get_level(GPIO_PCH_DSW_PWROK);
+
+	/*
+	 * This function is called when pwrok changes state. If pwrok
+	 * has been asserted (high -> low) then pass this new state to PCH.
+	 */
+	if (!in && (in != out))
+		gpio_set_level(GPIO_PCH_DSW_PWROK, in);
+
+	/*
+	 * Call the main power signal interrupt handler to wake up the chipset
+	 * task which handles low->high pwrok pass through.
+	 */
+	power_signal_interrupt(signal);
+}
+#endif
+
 void intel_x86_rsmrst_signal_interrupt(enum gpio_signal signal)
 {
-	int rsmrst_in = gpio_get_level(GPIO_RSMRST_L_PGOOD);
+	int rsmrst_in = gpio_get_level(GPIO_PG_EC_RSMRST_ODL);
 	int rsmrst_out = gpio_get_level(GPIO_PCH_RSMRST_L);
 
 	/*
@@ -518,7 +583,7 @@ void common_intel_x86_handle_rsmrst(enum power_state state)
 	 * Pass through RSMRST asynchronously, as PCH may not react
 	 * immediately to power changes.
 	 */
-	int rsmrst_in = gpio_get_level(GPIO_RSMRST_L_PGOOD);
+	int rsmrst_in = gpio_get_level(GPIO_PG_EC_RSMRST_ODL);
 	int rsmrst_out = gpio_get_level(GPIO_PCH_RSMRST_L);
 
 	/* Nothing to do. */
@@ -527,37 +592,37 @@ void common_intel_x86_handle_rsmrst(enum power_state state)
 
 	board_before_rsmrst(rsmrst_in);
 
-#ifdef CONFIG_CHIPSET_APL_GLK
 	/* Only passthrough RSMRST_L de-assertion on power up */
-	if (rsmrst_in && !power_s5_up)
+	if (IS_ENABLED(CONFIG_CHIPSET_X86_RSMRST_AFTER_S5) && rsmrst_in &&
+	    !power_s5_up)
 		return;
-#elif defined(CONFIG_CHIPSET_X86_RSMRST_DELAY)
 	/*
 	 * Wait at least 10ms between power signals going high
 	 * and deasserting RSMRST to PCH.
 	 */
-	if (rsmrst_in)
+	if (IS_ENABLED(CONFIG_CHIPSET_X86_RSMRST_DELAY) && rsmrst_in)
 		msleep(10);
-#endif
 
 	gpio_set_level(GPIO_PCH_RSMRST_L, rsmrst_in);
 
-	CPRINTS("Pass through GPIO_RSMRST_L_PGOOD: %d", rsmrst_in);
+	update_ap_boot_time(RSMRST);
+
+	CPRINTS("Pass through GPIO_PG_EC_RSMRST_ODL: %d", rsmrst_in);
 
 	board_after_rsmrst(rsmrst_in);
 }
 
 #ifdef CONFIG_POWER_TRACK_HOST_SLEEP_STATE
 
-__overridable void power_board_handle_host_sleep_event(
-		enum host_sleep_event state)
+__overridable void
+power_board_handle_host_sleep_event(enum host_sleep_event state)
 {
 	/* Default weak implementation -- no action required. */
 }
 
-__override void power_chipset_handle_host_sleep_event(
-		enum host_sleep_event state,
-		struct host_sleep_event_context *ctx)
+__override void
+power_chipset_handle_host_sleep_event(enum host_sleep_event state,
+				      struct host_sleep_event_context *ctx)
 {
 	power_board_handle_host_sleep_event(state);
 
@@ -570,7 +635,7 @@ __override void power_chipset_handle_host_sleep_event(
 		 */
 		sleep_set_notify(SLEEP_NOTIFY_SUSPEND);
 
-		sleep_start_suspend(ctx, lpc_s0ix_hang_detected);
+		sleep_start_suspend(ctx);
 		power_signal_enable_interrupt(sleep_sig[SYS_SLEEP_S0IX]);
 	} else if (state == HOST_SLEEP_EVENT_S0IX_RESUME) {
 		/*
@@ -593,7 +658,6 @@ __override void power_chipset_handle_host_sleep_event(
 		power_signal_disable_interrupt(sleep_sig[SYS_SLEEP_S0IX]);
 	}
 #endif
-
 }
 
 #endif
@@ -607,7 +671,7 @@ __overridable void intel_x86_sys_reset_delay(void)
 	udelay(32 * MSEC);
 }
 
-void chipset_reset(enum chipset_reset_reason reason)
+void chipset_reset(enum chipset_shutdown_reason reason)
 {
 	/*
 	 * Irrespective of cold_reset value, always toggle SYS_RESET_L to
@@ -645,8 +709,7 @@ enum ec_error_list intel_x86_wait_power_up_ok(void)
 	 * Allow charger to be initialized for up to defined tries,
 	 * in case we're trying to boot the AP with no battery.
 	 */
-	while ((tries < CHARGER_INITIALIZED_TRIES) &&
-	       is_power_up_inhibited()) {
+	while ((tries < CHARGER_INITIALIZED_TRIES) && is_power_up_inhibited()) {
 		msleep(CHARGER_INITIALIZED_DELAY_MS);
 		tries++;
 	}
diff --git a/power/meteorlake.c b/power/meteorlake.c
new file mode 100644
index 0000000000..c13ed1694d
--- /dev/null
+++ b/power/meteorlake.c
@@ -0,0 +1,213 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Meteorlake chipset power control module for Chrome EC
+ * TODO(b/223985632): Use native Zephyr power sequencing once implemented.
+ */
+
+#include "board_config.h"
+#include "chipset.h"
+#include "console.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "power.h"
+#include "power/intel_x86.h"
+#include "power_button.h"
+#include "task.h"
+#include "timer.h"
+
+/* Console output macros */
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
+
+#ifdef CONFIG_BRINGUP
+#define GPIO_SET_LEVEL(signal, value) \
+	gpio_set_level_verbose(CC_CHIPSET, signal, value)
+#else
+#define GPIO_SET_LEVEL(signal, value) gpio_set_level(signal, value)
+#endif
+
+/* Power signals list. Must match order of enum power_signal. */
+const struct power_signal_info power_signal_list[] = {
+	[X86_SLP_S0_DEASSERTED] = {
+		.gpio = GPIO_PCH_SLP_S0_L,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH |
+			POWER_SIGNAL_DISABLE_AT_BOOT,
+		.name = "SLP_S0_DEASSERTED",
+	},
+	[X86_SLP_S3_DEASSERTED] = {
+		.gpio = SLP_S3_SIGNAL_L,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "SLP_S3_DEASSERTED",
+	},
+	[X86_SLP_S4_DEASSERTED] = {
+		.gpio = SLP_S4_SIGNAL_L,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "SLP_S4_DEASSERTED",
+	},
+	[X86_SLP_S5_DEASSERTED] = {
+		.gpio = SLP_S5_SIGNAL_L,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "SLP_S5_DEASSERTED",
+	},
+	[X86_RSMRST_L_PGOOD] = {
+		.gpio = GPIO_PG_EC_RSMRST_ODL,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "RSMRST_L_PGOOD",
+	},
+	[X86_ALL_SYS_PGOOD] = {
+		.gpio = GPIO_PG_EC_ALL_SYS_PWRGD,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "ALL_SYS_PWRGD",
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
+
+void chipset_force_shutdown(enum chipset_shutdown_reason reason)
+{
+	int timeout_ms = 50;
+
+	CPRINTS("%s() %d", __func__, reason);
+	report_ap_reset(reason);
+
+	gpio_set_level(GPIO_PCH_PWROK, 0);
+
+	/* Turn off RMSRST_L  to meet tPCH12 */
+	board_before_rsmrst(0);
+	GPIO_SET_LEVEL(GPIO_PCH_RSMRST_L, 0);
+	board_after_rsmrst(0);
+
+	/* Turn off PRIM load switch. */
+	GPIO_SET_LEVEL(GPIO_EN_PP3300_A, 0);
+
+	/* Turn off PP5000 rail */
+	if (IS_ENABLED(CONFIG_POWER_PP5000_CONTROL))
+		power_5v_enable(task_get_current(), 0);
+	else
+		GPIO_SET_LEVEL(GPIO_EN_PP5000, 0);
+
+	/* RSMRST_ODL to go away. */
+	while (gpio_get_level(GPIO_PG_EC_RSMRST_ODL) && (timeout_ms > 0)) {
+		msleep(1);
+		timeout_ms--;
+	};
+
+	if (!timeout_ms)
+		CPRINTS("RSMRST_ODL didn't go low!  Assuming G3.");
+}
+
+void chipset_handle_espi_reset_assert(void)
+{
+	/* Nothing to do */
+}
+
+enum power_state chipset_force_g3(void)
+{
+	chipset_force_shutdown(CHIPSET_SHUTDOWN_G3);
+
+	return POWER_G3;
+}
+
+static void enable_pp5000_rail(void)
+{
+	if (IS_ENABLED(CONFIG_POWER_PP5000_CONTROL))
+		power_5v_enable(task_get_current(), 1);
+	else
+		GPIO_SET_LEVEL(GPIO_EN_PP5000, 1);
+}
+
+/*
+ * Set the PWROK signal state
+ *
+ * &param level		0 deasserts the signal, other values assert the signal
+ */
+static void pwrok_signal_set(const struct intel_x86_pwrok_signal *signal,
+			     int level)
+{
+	GPIO_SET_LEVEL(signal->gpio, signal->active_low ? !level : level);
+}
+
+__overridable int intel_x86_get_pg_ec_all_sys_pwrgd(void)
+{
+	return gpio_get_level(GPIO_PG_EC_ALL_SYS_PWRGD);
+}
+
+/*
+ * Pass through the state of the ALL_SYS_PWRGD input to all the PWROK outputs
+ * defined by the board.
+ */
+static void all_sys_pwrgd_pass_thru(void)
+{
+	int all_sys_pwrgd_in = intel_x86_get_pg_ec_all_sys_pwrgd();
+	const struct intel_x86_pwrok_signal *pwrok_signal;
+	int signal_count;
+	int i;
+
+	if (all_sys_pwrgd_in) {
+		pwrok_signal = pwrok_signal_assert_list;
+		signal_count = pwrok_signal_assert_count;
+	} else {
+		pwrok_signal = pwrok_signal_deassert_list;
+		signal_count = pwrok_signal_deassert_count;
+	}
+
+	/*
+	 * Loop through all PWROK signals defined by the board and set
+	 * to match the current ALL_SYS_PWRGD input.
+	 */
+	for (i = 0; i < signal_count; i++, pwrok_signal++) {
+		if (pwrok_signal->delay_ms > 0)
+			msleep(pwrok_signal->delay_ms);
+
+		pwrok_signal_set(pwrok_signal, all_sys_pwrgd_in);
+	}
+
+	/* PCH_PWROK is combination of ALL_SYS_PWRGD and SLP_S3 */
+	gpio_set_level(GPIO_PCH_PWROK,
+		       all_sys_pwrgd_in &&
+			       power_signal_get_level(SLP_S3_SIGNAL_L));
+}
+
+enum power_state power_handle_state(enum power_state state)
+{
+	all_sys_pwrgd_pass_thru();
+
+	common_intel_x86_handle_rsmrst(state);
+
+	switch (state) {
+	case POWER_G3S5:
+		if (IS_ENABLED(CONFIG_CHIPSET_SLP_S3_L_OVERRIDE)) {
+			/*
+			 * Prevent glitches on the SLP_S3_L and PCH_PWROK
+			 * signals while when the PP3300_A rail is turned on.
+			 * Drive SLP_S3_L from the EC until PRIM rail is high.
+			 */
+			CPRINTS("Drive SLP_S3_L low during PP3300_A rampup");
+			power_signal_disable_interrupt(SLP_S3_SIGNAL_L);
+			gpio_set_flags(SLP_S3_SIGNAL_L, GPIO_ODR_LOW);
+		}
+
+		/* Default behavior - turn on PP5000 rail first */
+		if (!IS_ENABLED(CONFIG_CHIPSET_PP3300_RAIL_FIRST))
+			enable_pp5000_rail();
+
+		/* Turn on the PP3300_PRIM rail. */
+		GPIO_SET_LEVEL(GPIO_EN_PP3300_A, 1);
+
+		if (power_wait_signals(IN_PGOOD_ALL_CORE))
+			break;
+
+		/* Turn on PP5000 after PP3300 enabled */
+		if (IS_ENABLED(CONFIG_CHIPSET_PP3300_RAIL_FIRST))
+			enable_pp5000_rail();
+
+		break;
+
+	default:
+		break;
+	}
+
+	return common_intel_x86_power_handle_state(state);
+}
diff --git a/power/mt817x.c b/power/mt817x.c
index e7e23605f2..a50e66b156 100644
--- a/power/mt817x.c
+++ b/power/mt817x.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,6 +26,7 @@
  */
 
 #include "battery.h"
+#include "builtin/assert.h"
 #include "chipset.h" /* ./common/chipset.c implements chipset functions too */
 #include "common.h"
 #include "gpio.h"
@@ -40,38 +41,38 @@
 #include "test_util.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
-#define INT_BOTH_PULL_UP	(GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH)
+#define INT_BOTH_PULL_UP (GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH)
 
 /* masks for power signals */
 #define IN_POWER_GOOD POWER_SIGNAL_MASK(MTK_POWER_GOOD)
 #define IN_SUSPEND POWER_SIGNAL_MASK(MTK_SUSPEND_ASSERTED)
 
 /* Long power key press to force shutdown */
-#define DELAY_FORCE_SHUTDOWN  (8000 * MSEC)	/* 8 seconds */
+#define DELAY_FORCE_SHUTDOWN (8000 * MSEC) /* 8 seconds */
 
 /*
  * The power signal from SoC should be kept at least 50ms.
  */
-#define POWER_DEBOUNCE_TIME     (50 * MSEC)
+#define POWER_DEBOUNCE_TIME (50 * MSEC)
 
 /*
  * The suspend signal from SoC should be kept at least 50ms.
  */
-#define SUSPEND_DEBOUNCE_TIME   (50 * MSEC)
+#define SUSPEND_DEBOUNCE_TIME (50 * MSEC)
 
 /*
  * The time to bootup the PMIC from power-off to power-on.
  */
-#define PMIC_PWRON_PRESS_TIME   (5000 * MSEC)
+#define PMIC_PWRON_PRESS_TIME (5000 * MSEC)
 
 /*
  * The minimum time to assert the PMIC THERM pin is 32us. However,
  * it needs to be extended to about 50ms to let the 5V rail
  * dissipate fully.
  */
-#define PMIC_THERM_HOLD_TIME  (50 * MSEC)
+#define PMIC_THERM_HOLD_TIME (50 * MSEC)
 
 /*
  * If the power key is pressed to turn on, then held for this long, we
@@ -81,7 +82,7 @@
  *    into the inner loop, waiting for next event to occur (power button
  *    press or POWER_GOOD == 0).
  */
-#define DELAY_SHUTDOWN_ON_POWER_HOLD	(8000 * MSEC)	/* 8 seconds */
+#define DELAY_SHUTDOWN_ON_POWER_HOLD (8000 * MSEC) /* 8 seconds */
 
 /*
  * The hold time for pulling down the PMIC_WARM_RESET_H pin so that
@@ -387,9 +388,8 @@ static void mtk_lid_event(void)
 	/* Override the panel backlight enable signal from SoC,
 	 * force the backlight off on lid close.
 	 */
-	bl_override = lid_is_open() ?
-		MTK_BACKLIGHT_CONTROL_BY_SOC :
-		MTK_BACKLIGHT_FORCE_OFF;
+	bl_override = lid_is_open() ? MTK_BACKLIGHT_CONTROL_BY_SOC :
+				      MTK_BACKLIGHT_FORCE_OFF;
 	mtk_backlight_override(bl_override);
 
 	/* Power task only cares about lid-open events */
@@ -539,7 +539,8 @@ static int check_for_power_on_event(void)
 			CPRINTS("system is on, but EC_RESET_FLAG_AP_OFF is on");
 			return POWER_ON_CANCEL;
 		} else {
-			CPRINTS("system is on, thus clear " "auto_power_on");
+			CPRINTS("system is on, thus clear "
+				"auto_power_on");
 			/* no need to arrange another power on */
 			auto_power_on = 0;
 			return POWER_ON_BY_IN_POWER_GOOD;
@@ -644,7 +645,7 @@ static void power_on(void)
 	CPRINTS("AP running ...");
 }
 
-void chipset_reset(enum chipset_reset_reason reason)
+void chipset_reset(enum chipset_shutdown_reason reason)
 {
 	CPRINTS("%s: %d", __func__, reason);
 	report_ap_reset(reason);
@@ -748,6 +749,12 @@ enum power_state power_handle_state(enum power_state state)
 
 	case POWER_S5G3:
 		return POWER_G3;
+
+	default:
+		/* Elm does not have space for such an extravagant print. */
+		/* CPRINTS("Unexpected power state %d", state); */
+		ASSERT(0);
+		break;
 	}
 
 	return state;
@@ -778,14 +785,14 @@ enum power_state_t {
 	PSTATE_COUNT,
 };
 
-static const char * const state_name[] = {
+static const char *const state_name[] = {
 	"unknown",
 	"off",
 	"suspend",
 	"on",
 };
 
-static int command_power(int argc, char **argv)
+static int command_power(int argc, const char **argv)
 {
 	int v;
 
@@ -813,6 +820,4 @@ static int command_power(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(power, command_power,
-			"on/off",
-			"Turn AP power on/off");
+DECLARE_CONSOLE_COMMAND(power, command_power, "on/off", "Turn AP power on/off");
diff --git a/power/mt8183.c b/power/mt8183.c
index 56aeaadb7a..eec8796427 100644
--- a/power/mt8183.c
+++ b/power/mt8183.c
@@ -1,10 +1,11 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* mt8183 chipset power control module for Chrome EC */
 
+#include "builtin/assert.h"
 #include "charge_state.h"
 #include "chipset.h"
 #include "common.h"
@@ -30,29 +31,29 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 /* Input state flags */
-#define IN_PGOOD_PMIC		POWER_SIGNAL_MASK(PMIC_PWR_GOOD)
-#define IN_SUSPEND_ASSERTED	POWER_SIGNAL_MASK(AP_IN_S3_L)
+#define IN_PGOOD_PMIC POWER_SIGNAL_MASK(PMIC_PWR_GOOD)
+#define IN_SUSPEND_ASSERTED POWER_SIGNAL_MASK(AP_IN_S3_L)
 
 /* Rails required for S3 and S0 */
-#define IN_PGOOD_S0		(IN_PGOOD_PMIC)
-#define IN_PGOOD_S3		(IN_PGOOD_PMIC)
+#define IN_PGOOD_S0 (IN_PGOOD_PMIC)
+#define IN_PGOOD_S3 (IN_PGOOD_PMIC)
 
 /* All inputs in the right state for S0 */
-#define IN_ALL_S0		(IN_PGOOD_S0 & ~IN_SUSPEND_ASSERTED)
+#define IN_ALL_S0 (IN_PGOOD_S0 & ~IN_SUSPEND_ASSERTED)
 
 /* Long power key press to force shutdown in S0. go/crosdebug */
 #ifdef VARIANT_KUKUI_JACUZZI
-#define FORCED_SHUTDOWN_DELAY	(8 * SECOND)
+#define FORCED_SHUTDOWN_DELAY (8 * SECOND)
 #else
-#define FORCED_SHUTDOWN_DELAY	(10 * SECOND)
+#define FORCED_SHUTDOWN_DELAY (10 * SECOND)
 #endif
 
 /* Long power key press to boot from S5/G3 state. */
 #ifndef POWERBTN_BOOT_DELAY
-#define POWERBTN_BOOT_DELAY	(1 * SECOND)
+#define POWERBTN_BOOT_DELAY (1 * SECOND)
 #endif
 
 #define CHARGER_INITIALIZED_DELAY_MS 100
@@ -96,12 +97,10 @@ static const struct power_seq_op s5s3_power_seq[] = {
 };
 
 /* The power sequence for POWER_S3S0 */
-static const struct power_seq_op s3s0_power_seq[] = {
-};
+static const struct power_seq_op s3s0_power_seq[] = {};
 
 /* The power sequence for POWER_S0S3 */
-static const struct power_seq_op s0s3_power_seq[] = {
-};
+static const struct power_seq_op s0s3_power_seq[] = {};
 
 /* The power sequence for POWER_S3S5 */
 static const struct power_seq_op s3s5_power_seq[] = {
@@ -109,9 +108,6 @@ static const struct power_seq_op s3s5_power_seq[] = {
 	{ GPIO_AP_SYS_RST_L, 0, 0 },
 	/* Assert watchdog to PMIC (there may be a 1.6ms debounce) */
 	{ GPIO_PMIC_WATCHDOG_L, 0, 3 },
-#ifdef BOARD_KAKADU
-        { GPIO_USB_C0_VCONN_EN_OD, 0, 0 },
-#endif
 };
 
 static int forcing_shutdown;
@@ -168,8 +164,28 @@ void chipset_exit_hard_off_button(void)
 }
 DECLARE_DEFERRED(chipset_exit_hard_off_button);
 
+#ifdef CONFIG_POWER_TRACK_HOST_SLEEP_STATE
+static void power_reset_host_sleep_state(void)
+{
+	power_set_host_sleep_state(HOST_SLEEP_EVENT_DEFAULT_RESET);
+	sleep_reset_tracking();
+	power_chipset_handle_host_sleep_event(HOST_SLEEP_EVENT_DEFAULT_RESET,
+					      NULL);
+}
+
+static void handle_chipset_reset(void)
+{
+	if (chipset_in_state(CHIPSET_STATE_SUSPEND)) {
+		CPRINTS("Chipset reset: exit s3");
+		power_reset_host_sleep_state();
+		task_wake(TASK_ID_CHIPSET);
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESET, handle_chipset_reset, HOOK_PRIO_FIRST);
+#endif /* CONFIG_POWER_TRACK_HOST_SLEEP_STATE */
+
 /* If chipset needs to be reset, EC also reboots to RO. */
-void chipset_reset(enum chipset_reset_reason reason)
+void chipset_reset(enum chipset_shutdown_reason reason)
 {
 	int flags = SYSTEM_RESET_HARD;
 
@@ -244,8 +260,7 @@ static void power_seq_run(const struct power_seq_op *power_seq_ops,
 	int i;
 
 	for (i = 0; i < op_count; i++) {
-		gpio_set_level(power_seq_ops[i].signal,
-			       power_seq_ops[i].level);
+		gpio_set_level(power_seq_ops[i].signal, power_seq_ops[i].level);
 		if (!power_seq_ops[i].delay)
 			continue;
 		msleep(power_seq_ops[i].delay);
@@ -276,6 +291,7 @@ enum power_state power_handle_state(enum power_state state)
 	 * transition to S5, G3.
 	 */
 	static int ap_shutdown;
+	uint16_t tries = 0;
 
 	switch (state) {
 	case POWER_G3:
@@ -333,8 +349,7 @@ enum power_state power_handle_state(enum power_state state)
 		break;
 
 	case POWER_S0:
-		if (!power_has_signals(IN_PGOOD_S0) ||
-		    forcing_shutdown ||
+		if (!power_has_signals(IN_PGOOD_S0) || forcing_shutdown ||
 		    power_get_signals() & IN_SUSPEND_ASSERTED)
 			return POWER_S0S3;
 
@@ -362,6 +377,24 @@ enum power_state power_handle_state(enum power_state state)
 		}
 #endif
 
+		/*
+		 * Allow time for charger to be initialized, in case we're
+		 * trying to boot the AP with no battery.
+		 */
+		while (charge_prevent_power_on(0) &&
+		       tries++ < CHARGER_INITIALIZED_TRIES) {
+			msleep(CHARGER_INITIALIZED_DELAY_MS);
+		}
+
+		/* Return to G3 if battery level is too low. */
+		if (charge_want_shutdown() ||
+		    tries > CHARGER_INITIALIZED_TRIES) {
+			CPRINTS("power-up inhibited");
+			chipset_force_shutdown(
+				CHIPSET_SHUTDOWN_BATTERY_INHIBIT);
+			return POWER_G3;
+		}
+
 #if CONFIG_CHIPSET_POWER_SEQ_VERSION == 1
 		hook_call_deferred(&deassert_en_pp1800_s5_l_data, -1);
 #endif
@@ -426,6 +459,14 @@ enum power_state power_handle_state(enum power_state state)
 		/* Call hooks now that rails are up */
 		hook_notify(HOOK_CHIPSET_STARTUP);
 
+		/*
+		 * Clearing the sleep failure detection tracking on the path
+		 * to S0 to handle any reset conditions.
+		 */
+#ifdef CONFIG_POWER_SLEEP_FAILURE_DETECTION
+		power_reset_host_sleep_state();
+#endif /* CONFIG_POWER_SLEEP_FAILURE_DETECTION */
+
 		/* Power up to next state */
 		return POWER_S3;
 
@@ -440,6 +481,10 @@ enum power_state power_handle_state(enum power_state state)
 		/* Call hooks now that rails are up */
 		hook_notify(HOOK_CHIPSET_RESUME);
 
+#ifdef CONFIG_POWER_SLEEP_FAILURE_DETECTION
+		sleep_resume_transition();
+#endif /* CONFIG_POWER_SLEEP_FAILURE_DETECTION */
+
 		/*
 		 * Disable idle task deep sleep. This means that the low
 		 * power idle task will not go into deep sleep while in S0.
@@ -453,6 +498,10 @@ enum power_state power_handle_state(enum power_state state)
 		/* Call hooks before we remove power rails */
 		hook_notify(HOOK_CHIPSET_SUSPEND);
 
+#ifdef CONFIG_POWER_SLEEP_FAILURE_DETECTION
+		sleep_suspend_transition();
+#endif /* CONFIG_POWER_SLEEP_FAILURE_DETECTION */
+
 		/*
 		 * TODO(b:109850749): Check if we need some delay here to
 		 * "debounce" entering suspend (rk3399 uses 20ms delay).
@@ -473,7 +522,7 @@ enum power_state power_handle_state(enum power_state state)
 		if (power_button_is_pressed()) {
 			forcing_shutdown = 1;
 			hook_call_deferred(&chipset_force_shutdown_button_data,
-					-1);
+					   -1);
 		}
 
 		return POWER_S3;
@@ -512,17 +561,56 @@ enum power_state power_handle_state(enum power_state state)
 			gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 0);
 			msleep(5);
 			hook_call_deferred(&release_pmic_force_reset_data,
-				PMIC_FORCE_RESET_TIME);
+					   PMIC_FORCE_RESET_TIME);
 
 			return POWER_S5G3;
 		}
 
 		return POWER_G3;
+
+	default:
+		CPRINTS("Unexpected power state %d", state);
+		ASSERT(0);
+		break;
 	}
 
 	return state;
 }
 
+#ifdef CONFIG_POWER_TRACK_HOST_SLEEP_STATE
+__override void power_chipset_handle_sleep_hang(enum sleep_hang_type hang_type)
+{
+	CPRINTS("Warning: Detected sleep hang! Waking host up!");
+	host_set_single_event(EC_HOST_EVENT_HANG_DETECT);
+}
+
+__override void
+power_chipset_handle_host_sleep_event(enum host_sleep_event state,
+				      struct host_sleep_event_context *ctx)
+{
+	CPRINTS("Handle sleep: %d", state);
+
+	if (state == HOST_SLEEP_EVENT_S3_SUSPEND) {
+		/*
+		 * Indicate to power state machine that a new host event for
+		 * S3 suspend has been received and so chipset suspend
+		 * notification needs to be sent to listeners.
+		 */
+		sleep_set_notify(SLEEP_NOTIFY_SUSPEND);
+		sleep_start_suspend(ctx);
+
+	} else if (state == HOST_SLEEP_EVENT_S3_RESUME) {
+		/*
+		 * Wake up chipset task and indicate to power state machine that
+		 * listeners need to be notified of chipset resume.
+		 */
+		sleep_set_notify(SLEEP_NOTIFY_RESUME);
+		task_wake(TASK_ID_CHIPSET);
+		sleep_complete_resume(ctx);
+	}
+}
+#endif /* CONFIG_POWER_TRACK_HOST_SLEEP_STATE */
+
 static void power_button_changed(void)
 {
 	if (power_button_is_pressed()) {
diff --git a/power/mt8186.c b/power/mt8186.c
new file mode 100644
index 0000000000..6e4c0b4945
--- /dev/null
+++ b/power/mt8186.c
@@ -0,0 +1,577 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * MT8186/MT8188 SoC power sequencing module for Chrome EC
+ *
+ * This implements the following features:
+ *
+ * - Cold reset powers on the AP
+ *
+ * When powered off:
+ *  - Press power button turns on the AP
+ *  - Hold power button turns on the AP, and then 8s later turns it off and
+ *    leaves it off until pwron is released and press again.
+ *  - Lid open turns on the AP
+ *
+ *  When powered on:
+ *  - Holding power button for 8s powers off the AP
+ *  - Pressing and releaseing power within that 8s is ignored
+ */
+
+#include "battery.h"
+#include "chipset.h"
+#include "common.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "system.h"
+#include "task.h"
+#include "timer.h"
+
+#ifdef CONFIG_BRINGUP
+#define GPIO_SET_LEVEL(signal, value) \
+	gpio_set_level_verbose(CC_CHIPSET, signal, value)
+#else
+#define GPIO_SET_LEVEL(signal, value) gpio_set_level(signal, value)
+#endif
+
+/* Console output macros */
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
+
+/* Input state flags */
+#define IN_SUSPEND_ASSERTED POWER_SIGNAL_MASK(AP_IN_S3)
+#define IN_AP_RST POWER_SIGNAL_MASK(AP_IN_RST)
+#define IN_PG_PP4200_S5 POWER_SIGNAL_MASK(PG_PP4200_S5)
+#define IN_PMIC_AP_RST POWER_SIGNAL_MASK(PMIC_AP_RST)
+
+/* Long power key press to force shutdown in S0. go/crosdebug */
+#define FORCED_SHUTDOWN_DELAY (8 * SECOND)
+
+/* PG4200 S5 ready delay */
+#define PG_PP4200_S5_DELAY (100 * MSEC)
+
+/* Maximum time it should for PMIC to turn on after toggling PMIC_EN_ODL. */
+#define PMIC_EN_TIMEOUT (300 * MSEC)
+#define PMIC_EN_PULSE_MS 50
+/* PMIC hard off delay with 20% tolerance. */
+#define PMIC_HARD_OFF_DELAY (8 * SECOND / 100 * 120)
+/* Timeout for PMIC resetting AP after hard off. */
+#define PMIC_AP_RESET_TIMEOUT (1 * SECOND)
+
+/* 30 ms for hard reset, we hold it longer to prevent TPM false alarm. */
+#define SYS_RST_PULSE_LENGTH (50 * MSEC)
+
+/*
+ * A delay for distinguish a WDT reset or a normal shutdown. It usually takes
+ * 90ms to pull AP_IN_SLEEP_L low in a normal shutdown.
+ */
+#define NORMAL_SHUTDOWN_DELAY (150 * MSEC)
+#define RESET_FLAG_TIMEOUT (2 * SECOND)
+
+#if defined(CONFIG_PLATFORM_EC_POWERSEQ_MT8188) && \
+	!DT_NODE_EXISTS(DT_NODELABEL(en_pp4200_s5))
+#error Must have dt node en_pp4200_s5 for MT8188 power sequence
+#endif
+
+/* indicate MT8186 is processing a chipset reset. */
+static bool is_resetting;
+/* indicate MT8186 is AP reset is held by servo or GSC. */
+test_export_static bool is_held;
+/* indicate MT8186 is processing a AP forcing shutdown. */
+test_export_static bool is_shutdown;
+/* indicate MT8186 has been dropped to S5G3 from the last IN_AP_RST state . */
+static bool is_s5g3_passed;
+/*
+ * indicate exiting off state, and don't respect the power signals until chipset
+ * on.
+ */
+static bool is_exiting_off;
+
+/* forward declaration */
+static enum power_state power_get_signal_state(void);
+
+/* Turn on the PMIC power source to AP, this also boots AP. */
+static void set_pmic_pwron(void)
+{
+	GPIO_SET_LEVEL(GPIO_EC_PMIC_EN_ODL, 1);
+	msleep(PMIC_EN_PULSE_MS);
+	GPIO_SET_LEVEL(GPIO_EC_PMIC_EN_ODL, 0);
+	msleep(PMIC_EN_PULSE_MS);
+	GPIO_SET_LEVEL(GPIO_EC_PMIC_EN_ODL, 1);
+}
+
+/* Turn off the PMIC power source to AP (forcely), this could take up to 8
+ * seconds
+ */
+static void set_pmic_pwroff(void)
+{
+	timestamp_t pmic_off_timeout;
+
+	/* We don't have a PMIC PG signal, so we can only blindly assert
+	 * the PMIC EN for a long delay time that the spec requiring.
+	 */
+	GPIO_SET_LEVEL(GPIO_EC_PMIC_EN_ODL, 0);
+
+	pmic_off_timeout = get_time();
+	pmic_off_timeout.val += PMIC_HARD_OFF_DELAY;
+
+	while (!timestamp_expired(pmic_off_timeout, NULL)) {
+		msleep(100);
+	};
+
+	GPIO_SET_LEVEL(GPIO_EC_PMIC_EN_ODL, 1);
+}
+
+void chipset_warm_reset_interrupt(enum gpio_signal signal)
+{
+	/* If this is not a chipset_reset, the ap_rst must be held by gsc or
+	 * servo.
+	 */
+	if (!is_resetting && !gpio_get_level(GPIO_SYS_RST_ODL) &&
+	    !gpio_get_level(signal))
+		is_held = true;
+	else
+		is_held = false;
+
+	power_signal_interrupt(signal);
+}
+
+static void reset_request_interrupt_deferred(void)
+{
+	chipset_reset(CHIPSET_RESET_AP_REQ);
+}
+DECLARE_DEFERRED(reset_request_interrupt_deferred);
+
+void chipset_reset_request_interrupt(enum gpio_signal signal)
+{
+	power_signal_interrupt(signal);
+	hook_call_deferred(&reset_request_interrupt_deferred_data, 0);
+}
+
+static void watchdog_interrupt_deferred(void)
+{
+	/* If it's a real WDT, it must be in S0. */
+	if (!(power_get_signals() & (IN_AP_RST | IN_SUSPEND_ASSERTED)))
+		chipset_reset(CHIPSET_RESET_AP_WATCHDOG);
+}
+DECLARE_DEFERRED(watchdog_interrupt_deferred);
+
+void chipset_watchdog_interrupt(enum gpio_signal signal)
+{
+	power_signal_interrupt(signal);
+
+	/*
+	 * We need this guard in that:
+	 * 1. AP_EC_WDTRST_L will recursively toggle until the AP is reset.
+	 * 2. If a warm reset request or AP shutdown is processing, then this
+	 *    interrupt tirgger is a fake WDT interrupt, we should skip it.
+	 */
+	if (!is_resetting && !is_shutdown)
+		hook_call_deferred(&watchdog_interrupt_deferred_data,
+				   NORMAL_SHUTDOWN_DELAY);
+}
+
+void chipset_force_shutdown(enum chipset_shutdown_reason reason)
+{
+	int state = power_get_signal_state();
+	/* use the signal state instead of the chipset_in_state because the
+	 * power_state is not initaialized when chipset_force_shutdown is called
+	 * from power_chipset_init.
+	 */
+	bool chipset_off = (state != POWER_S0 && state != POWER_S3);
+
+	CPRINTS("%s: 0x%x%s", __func__, reason, chipset_off ? "(skipped)" : "");
+
+	if (chipset_off)
+		return;
+
+	report_ap_reset(reason);
+
+	is_shutdown = true;
+
+	task_wake(TASK_ID_CHIPSET);
+}
+
+void chipset_force_shutdown_button(void)
+{
+	chipset_force_shutdown(CHIPSET_SHUTDOWN_BUTTON);
+}
+DECLARE_DEFERRED(chipset_force_shutdown_button);
+
+static void mt8186_exit_off(void)
+{
+	is_exiting_off = true;
+	chipset_exit_hard_off();
+}
+
+static void reset_flag_deferred(void)
+{
+	if (!is_resetting)
+		return;
+
+	CPRINTS("chipset_reset failed");
+	is_resetting = false;
+	task_wake(TASK_ID_CHIPSET);
+}
+DECLARE_DEFERRED(reset_flag_deferred);
+
+void chipset_reset(enum chipset_shutdown_reason reason)
+{
+	CPRINTS("%s: 0x%x", __func__, reason);
+	report_ap_reset(reason);
+
+	is_resetting = true;
+	hook_call_deferred(&reset_flag_deferred_data, RESET_FLAG_TIMEOUT);
+	GPIO_SET_LEVEL(GPIO_SYS_RST_ODL, 0);
+	usleep(SYS_RST_PULSE_LENGTH);
+	GPIO_SET_LEVEL(GPIO_SYS_RST_ODL, 1);
+}
+
+#ifdef CONFIG_POWER_TRACK_HOST_SLEEP_STATE
+static void power_reset_host_sleep_state(void)
+{
+	power_set_host_sleep_state(HOST_SLEEP_EVENT_DEFAULT_RESET);
+	sleep_reset_tracking();
+	power_chipset_handle_host_sleep_event(HOST_SLEEP_EVENT_DEFAULT_RESET,
+					      NULL);
+}
+#endif /* CONFIG_POWER_TRACK_HOST_SLEEP_STATE */
+
+/*
+ * Power state is determined from the following table:
+ *
+ *     | IN_AP_RST | IN_SUSPEND_ASSERTED | is_s5g3_passed |
+ * --------------------------------------------------------
+ *  S0 |         0 |                   0 |               x|
+ *  S3 |         0 |                   1 |               x|
+ *  S5 |         1 |                   x |               0|
+ *  G3 |         1 |                   x |               1|
+ *
+ * S5 is a temp stage, which will be put into G3 after s5_inactivity_timeout.
+ * is_resetting flag indicates it's resetting chipset, and always S0.
+ * is_held flag indicates the AP reset is held by servo or GSC, and always S0.
+ * is_shutdown flag indicates it's shutting down the AP, it goes for S5.
+ * is_s5g3_passed flag indicates it has shutdown from S5 to G3 since last
+ * shutdown.
+ */
+static enum power_state power_get_signal_state(void)
+{
+	if (is_shutdown)
+		return POWER_S5;
+	/*
+	 * - We are processing a chipset reset(S0->S0), so we don't check the
+	 * power signals until the reset is finished. This is because
+	 * while the chipset is resetting, the intermediate power signal state
+	 * is not reflecting the current power state.
+	 *
+	 * - GSC or Servo is holding the SYS_RST, in this case, we should stay
+	 * at S0.
+	 */
+	if (is_resetting || is_held)
+		return POWER_S0;
+	if (power_get_signals() & IN_AP_RST) {
+		/* If it has been put to G3 from S5 idle, then stay at G3.*/
+		if (is_s5g3_passed)
+			return POWER_G3;
+		return POWER_S5;
+	}
+	if (power_get_signals() & IN_SUSPEND_ASSERTED)
+		return POWER_S3;
+	return POWER_S0;
+}
+
+enum power_state power_chipset_init(void)
+{
+	int exit_hard_off = 1;
+	enum power_state init_state = power_get_signal_state();
+
+	if (system_get_reset_flags() & EC_RESET_FLAG_AP_IDLE) {
+		if (init_state == POWER_S0) {
+			disable_sleep(SLEEP_MASK_AP_RUN);
+		}
+
+		return init_state;
+	}
+
+	if (system_jumped_late()) {
+		if (init_state == POWER_S0) {
+			disable_sleep(SLEEP_MASK_AP_RUN);
+			CPRINTS("already in S0");
+		}
+	} else if (system_get_reset_flags() & EC_RESET_FLAG_AP_OFF) {
+		exit_hard_off = 0;
+	} else if ((system_get_reset_flags() & EC_RESET_FLAG_HIBERNATE) &&
+		   gpio_get_level(GPIO_AC_PRESENT)) {
+		/*
+		 * If AC present, assume this is a wake-up by AC insert.
+		 * Boot EC only.
+		 *
+		 * Note that extpower module is not initialized at this point,
+		 * the only way is to ask GPIO_AC_PRESENT directly.
+		 */
+		exit_hard_off = 0;
+	}
+
+	/* If the init signal state is at S5, assigns it to G3 to match the
+	 * default GPIO and PP4200_S5 rail states.
+	 */
+	if (init_state == POWER_S5) {
+		init_state = POWER_G3;
+		is_s5g3_passed = true;
+	}
+
+	if (battery_is_present() == BP_YES)
+		/*
+		 * (crosbug.com/p/28289): Wait battery stable.
+		 * Some batteries use clock stretching feature, which requires
+		 * more time to be stable.
+		 */
+		battery_wait_for_stable();
+
+	if (exit_hard_off && init_state == POWER_G3)
+		/* Auto-power on */
+		mt8186_exit_off();
+
+	if (init_state != POWER_G3 && !exit_hard_off) {
+		/* Force shutdown from S5 if the PMIC is already up. */
+		chipset_force_shutdown(CHIPSET_SHUTDOWN_INIT);
+	}
+
+	return init_state;
+}
+
+enum power_state power_handle_state(enum power_state state)
+{
+	enum power_state next_state = power_get_signal_state();
+
+	switch (state) {
+	case POWER_G3:
+		if (next_state != POWER_G3)
+			return POWER_G3S5;
+		break;
+
+	case POWER_S5:
+		if (is_exiting_off)
+			return POWER_S5S3;
+		else if (next_state == POWER_G3)
+			return POWER_S5G3;
+		else if (next_state == POWER_S5)
+			return POWER_S5;
+		else
+			return POWER_S5S3;
+
+	case POWER_S3:
+		if (next_state == POWER_G3 || next_state == POWER_S5)
+			return POWER_S3S5;
+		else if (next_state == POWER_S0)
+			return POWER_S3S0;
+		break;
+
+	case POWER_S0:
+		if (next_state != POWER_S0)
+			return POWER_S0S3;
+		is_resetting = false;
+
+		break;
+
+	case POWER_G3S5:
+#if DT_NODE_EXISTS(DT_NODELABEL(en_pp4200_s5))
+		power_signal_enable_interrupt(GPIO_PMIC_EC_RESETB);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(en_pp4200_s5), 1);
+		if (power_wait_mask_signals_timeout(IN_PG_PP4200_S5,
+						    IN_PG_PP4200_S5,
+						    PG_PP4200_S5_DELAY))
+			return POWER_S5G3;
+#endif
+		return POWER_S5;
+
+	case POWER_S5S3:
+		/* Off state exited. */
+		is_exiting_off = false;
+		is_s5g3_passed = false;
+		hook_notify(HOOK_CHIPSET_PRE_INIT);
+
+		power_signal_enable_interrupt(GPIO_AP_IN_SLEEP_L);
+		power_signal_enable_interrupt(GPIO_AP_EC_WDTRST_L);
+		power_signal_enable_interrupt(GPIO_AP_EC_WARM_RST_REQ);
+
+		set_pmic_pwron();
+
+		GPIO_SET_LEVEL(GPIO_SYS_RST_ODL, 1);
+
+		if (power_wait_mask_signals_timeout(0, IN_AP_RST,
+						    PMIC_EN_TIMEOUT))
+			/* Give up, go back to G3. */
+			return POWER_S5G3;
+
+		/* Call hooks now that rails are up */
+		hook_notify(HOOK_CHIPSET_STARTUP);
+		/*
+		 * Clearing the sleep failure detection tracking on the path
+		 * to S0 to handle any reset conditions.
+		 */
+#ifdef CONFIG_POWER_SLEEP_FAILURE_DETECTION
+		power_reset_host_sleep_state();
+#endif /* CONFIG_POWER_SLEEP_FAILURE_DETECTION */
+		/* Power up to next state */
+		return POWER_S3;
+
+	case POWER_S3S0:
+		hook_notify(HOOK_CHIPSET_RESUME_INIT);
+
+		if (power_wait_mask_signals_timeout(0, IN_AP_RST, SECOND)) {
+			chipset_force_shutdown(CHIPSET_SHUTDOWN_WAIT);
+			return POWER_S0S3;
+		}
+
+		/* Call hooks now that rails are up */
+		hook_notify(HOOK_CHIPSET_RESUME);
+
+#ifdef CONFIG_POWER_SLEEP_FAILURE_DETECTION
+		sleep_resume_transition();
+#endif /* CONFIG_POWER_SLEEP_FAILURE_DETECTION */
+
+		/*
+		 * Disable idle task deep sleep. This means that the low
+		 * power idle task will not go into deep sleep while in S0.
+		 */
+		disable_sleep(SLEEP_MASK_AP_RUN);
+
+		/* Power up to next state */
+		return POWER_S0;
+
+	case POWER_S0S3:
+		/* Call hooks before we remove power rails */
+		hook_notify(HOOK_CHIPSET_SUSPEND);
+
+#ifdef CONFIG_POWER_SLEEP_FAILURE_DETECTION
+		sleep_suspend_transition();
+#endif /* CONFIG_POWER_SLEEP_FAILURE_DETECTION */
+
+		/*
+		 * Enable idle task deep sleep. Allow the low power idle task
+		 * to go into deep sleep in S3 or lower.
+		 */
+		enable_sleep(SLEEP_MASK_AP_RUN);
+
+		hook_notify(HOOK_CHIPSET_SUSPEND_COMPLETE);
+
+		return POWER_S3;
+
+	case POWER_S3S5:
+		/* Stop the power key shutdown deferred in case the power key
+		 * is still pressed.
+		 */
+		hook_call_deferred(&chipset_force_shutdown_button_data, -1);
+
+		power_signal_disable_interrupt(GPIO_AP_IN_SLEEP_L);
+		power_signal_disable_interrupt(GPIO_AP_EC_WDTRST_L);
+		power_signal_disable_interrupt(GPIO_AP_EC_WARM_RST_REQ);
+
+		/* Only actively reset AP with hard shutdown.
+		 * For AP initiated shutdown, the AP has been reset by PMIC.
+		 * For servo, gsc initiaed warm reset, EC doesn't need to hold
+		 * it.
+		 */
+		if (is_shutdown)
+			GPIO_SET_LEVEL(GPIO_SYS_RST_ODL, 0);
+
+		/* Call hooks before we remove power rails */
+		hook_notify(HOOK_CHIPSET_SHUTDOWN);
+
+		/* If this is a forcing shutdown, power off the PMIC now,
+		 * and can wait at most up to 8 seconds.
+		 */
+		if (is_shutdown)
+			set_pmic_pwroff();
+
+		hook_notify(HOOK_CHIPSET_SHUTDOWN_COMPLETE);
+
+		is_shutdown = false;
+		/* AP down and PMIC off, the servo and GSC is unable to hold the
+		 * AP for S0.
+		 */
+		is_held = false;
+		return POWER_S5;
+
+	case POWER_S5G3:
+		is_s5g3_passed = true;
+#if DT_NODE_EXISTS(DT_NODELABEL(en_pp4200_s5))
+		if (power_wait_mask_signals_timeout(IN_PMIC_AP_RST,
+						    IN_PMIC_AP_RST,
+						    PMIC_AP_RESET_TIMEOUT))
+			CPRINTS("PMIC reset AP timeout. Forcing PMIC off");
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(en_pp4200_s5), 0);
+		power_signal_disable_interrupt(GPIO_PMIC_EC_RESETB);
+#endif
+		return POWER_G3;
+	default:
+		CPRINTS("Unexpected power state %d", state);
+		break;
+	}
+
+	return state;
+}
+
+static void power_button_changed(void)
+{
+	if (power_button_is_pressed()) {
+		if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+			mt8186_exit_off();
+		/* Delayed power down from S0/S3, cancel on PB release */
+		hook_call_deferred(&chipset_force_shutdown_button_data,
+				   FORCED_SHUTDOWN_DELAY);
+	} else {
+		hook_call_deferred(&chipset_force_shutdown_button_data, -1);
+	}
+}
+DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, power_button_changed, HOOK_PRIO_DEFAULT);
+
+#ifdef CONFIG_POWER_TRACK_HOST_SLEEP_STATE
+__override void power_chipset_handle_sleep_hang(enum sleep_hang_type hang_type)
+{
+	CPRINTS("Warning: Detected sleep hang! Waking host up!");
+	host_set_single_event(EC_HOST_EVENT_HANG_DETECT);
+}
+
+__override void
+power_chipset_handle_host_sleep_event(enum host_sleep_event state,
+				      struct host_sleep_event_context *ctx)
+{
+	CPRINTS("Handle sleep: %d", state);
+
+	if (state == HOST_SLEEP_EVENT_S3_SUSPEND) {
+		/*
+		 * Indicate to power state machine that a new host event for
+		 * S3 suspend has been received and so chipset suspend
+		 * notification needs to be sent to listeners.
+		 */
+		sleep_set_notify(SLEEP_NOTIFY_SUSPEND);
+		sleep_start_suspend(ctx);
+
+	} else if (state == HOST_SLEEP_EVENT_S3_RESUME) {
+		/*
+		 * Wake up chipset task and indicate to power state machine that
+		 * listeners need to be notified of chipset resume.
+		 */
+		sleep_set_notify(SLEEP_NOTIFY_RESUME);
+		task_wake(TASK_ID_CHIPSET);
+		sleep_complete_resume(ctx);
+	}
+}
+#endif /* CONFIG_POWER_TRACK_HOST_SLEEP_STATE */
+
+#ifdef CONFIG_LID_SWITCH
+static void lid_changed(void)
+{
+	/* Power-up from off on lid open */
+	if (lid_is_open() && chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		mt8186_exit_off();
+}
+DECLARE_HOOK(HOOK_LID_CHANGE, lid_changed, HOOK_PRIO_DEFAULT);
+#endif
diff --git a/power/mt8192.c b/power/mt8192.c
index c1d545fc86..67dcc2fec6 100644
--- a/power/mt8192.c
+++ b/power/mt8192.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,8 +22,10 @@
  */
 
 #include "battery.h"
+#include "builtin/assert.h"
 #include "chipset.h"
 #include "common.h"
+#include "gpio.h"
 #include "hooks.h"
 #include "lid_switch.h"
 #include "power.h"
@@ -31,6 +33,7 @@
 #include "system.h"
 #include "task.h"
 #include "timer.h"
+#include "util.h"
 
 #ifdef CONFIG_BRINGUP
 #define GPIO_SET_LEVEL(signal, value) \
@@ -66,9 +69,6 @@
 /* Maximum time it should for PMIC to turn on after toggling PMIC_EN_ODL. */
 #define PMIC_EN_TIMEOUT (300 * MSEC)
 
-/* Time delay in G3 to deassert EN_PP1800_S5_L */
-#define EN_PP1800_S5_L_DEASSERT_TIME (20 * MSEC)
-
 /*
  * Time delay for AP on/off the AP_EC_WDT when received SYS_RST_ODL.
  * Generally it can be done within 3 ms.
@@ -78,6 +78,18 @@
 /* 30 ms for hard reset, we hold it longer to prevent TPM false alarm. */
 #define SYS_RST_PULSE_LENGTH (50 * MSEC)
 
+#ifndef CONFIG_ZEPHYR
+
+/* power signal list.  Must match order of enum power_signal. */
+const struct power_signal_info power_signal_list[] = {
+	{ GPIO_PMIC_EC_PWRGD, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" },
+	{ GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" },
+	{ GPIO_AP_EC_WATCHDOG_L, POWER_SIGNAL_ACTIVE_LOW, "AP_WDT_ASSERTED" },
+};
+BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
+
+#endif /* !CONFIG_ZEPHYR */
+
 static int forcing_shutdown;
 
 static void watchdog_interrupt_deferred(void)
@@ -160,7 +172,7 @@ void chipset_exit_hard_off_button(void)
 }
 DECLARE_DEFERRED(chipset_exit_hard_off_button);
 
-void chipset_reset(enum chipset_reset_reason reason)
+void chipset_reset(enum chipset_shutdown_reason reason)
 {
 	CPRINTS("%s: %d", __func__, reason);
 	report_ap_reset(reason);
@@ -170,25 +182,47 @@ void chipset_reset(enum chipset_reset_reason reason)
 	GPIO_SET_LEVEL(GPIO_SYS_RST_ODL, 1);
 }
 
+#ifdef CONFIG_POWER_TRACK_HOST_SLEEP_STATE
+static void power_reset_host_sleep_state(void)
+{
+	power_set_host_sleep_state(HOST_SLEEP_EVENT_DEFAULT_RESET);
+	sleep_reset_tracking();
+	power_chipset_handle_host_sleep_event(HOST_SLEEP_EVENT_DEFAULT_RESET,
+					      NULL);
+}
+
+static void handle_chipset_reset(void)
+{
+	if (chipset_in_state(CHIPSET_STATE_SUSPEND)) {
+		CPRINTS("Chipset reset: exit s3");
+		power_reset_host_sleep_state();
+		task_wake(TASK_ID_CHIPSET);
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESET, handle_chipset_reset, HOOK_PRIO_FIRST);
+#endif /* CONFIG_POWER_TRACK_HOST_SLEEP_STATE */
+
 enum power_state power_chipset_init(void)
 {
 	int exit_hard_off = 1;
+	uint32_t reset_flags = system_get_reset_flags();
 
 	/* Enable reboot / sleep control inputs from AP */
 	gpio_enable_interrupt(GPIO_AP_EC_WARM_RST_REQ);
 	gpio_enable_interrupt(GPIO_AP_IN_SLEEP_L);
 
-	if (system_get_reset_flags() & EC_RESET_FLAG_SYSJUMP) {
+	if (system_jumped_late()) {
 		if ((power_get_signals() & IN_ALL_S0) == IN_ALL_S0) {
 			disable_sleep(SLEEP_MASK_AP_RUN);
 			power_signal_enable_interrupt(GPIO_AP_EC_WATCHDOG_L);
 			CPRINTS("already in S0");
 			return POWER_S0;
 		}
-	} else if (system_get_reset_flags() & EC_RESET_FLAG_AP_OFF) {
+	} else if ((reset_flags & EC_RESET_FLAG_AP_OFF) ||
+		   (reset_flags & EC_RESET_FLAG_AP_IDLE)) {
 		exit_hard_off = 0;
-	} else if ((system_get_reset_flags() & EC_RESET_FLAG_HIBERNATE) &&
-			gpio_get_level(GPIO_AC_PRESENT)) {
+	} else if ((reset_flags & EC_RESET_FLAG_HIBERNATE) &&
+		   gpio_get_level(GPIO_AC_PRESENT)) {
 		/*
 		 * If AC present, assume this is a wake-up by AC insert.
 		 * Boot EC only.
@@ -350,10 +384,22 @@ enum power_state power_handle_state(enum power_state state)
 		/* Call hooks now that rails are up */
 		hook_notify(HOOK_CHIPSET_STARTUP);
 
+		/*
+		 * Clearing the sleep failure detection tracking on the path
+		 * to S0 to handle any reset conditions.
+		 */
+#ifdef CONFIG_POWER_SLEEP_FAILURE_DETECTION
+		power_reset_host_sleep_state();
+#endif /* CONFIG_POWER_SLEEP_FAILURE_DETECTION */
 		/* Power up to next state */
 		return POWER_S3;
 
 	case POWER_S3S0:
+#ifdef CONFIG_CHIPSET_RESUME_INIT_HOOK
+		/* Call hooks prior to chipset resume */
+		hook_notify(HOOK_CHIPSET_RESUME_INIT);
+#endif
+
 		if (power_wait_signals(IN_PGOOD_S0)) {
 			chipset_force_shutdown(CHIPSET_SHUTDOWN_WAIT);
 			return POWER_S0S3;
@@ -362,6 +408,10 @@ enum power_state power_handle_state(enum power_state state)
 		/* Call hooks now that rails are up */
 		hook_notify(HOOK_CHIPSET_RESUME);
 
+#ifdef CONFIG_POWER_SLEEP_FAILURE_DETECTION
+		sleep_resume_transition();
+#endif /* CONFIG_POWER_SLEEP_FAILURE_DETECTION */
+
 		/*
 		 * Disable idle task deep sleep. This means that the low
 		 * power idle task will not go into deep sleep while in S0.
@@ -374,6 +424,14 @@ enum power_state power_handle_state(enum power_state state)
 	case POWER_S0S3:
 		/* Call hooks before we remove power rails */
 		hook_notify(HOOK_CHIPSET_SUSPEND);
+#ifdef CONFIG_CHIPSET_RESUME_INIT_HOOK
+		/* Call hooks after chipset suspend */
+		hook_notify(HOOK_CHIPSET_SUSPEND_COMPLETE);
+#endif
+
+#ifdef CONFIG_POWER_SLEEP_FAILURE_DETECTION
+		sleep_suspend_transition();
+#endif /* CONFIG_POWER_SLEEP_FAILURE_DETECTION */
 
 		/*
 		 * Enable idle task deep sleep. Allow the low power idle task
@@ -425,7 +483,16 @@ enum power_state power_handle_state(enum power_state state)
 		if (forcing_shutdown)
 			GPIO_SET_LEVEL(GPIO_EC_PMIC_EN_ODL, 1);
 
+		/* If PMIC is not off, go back to S5 and try again. */
+		if (power_get_signals() & IN_PGOOD_PMIC)
+			return POWER_S5;
+
 		return POWER_G3;
+
+	default:
+		CPRINTS("Unexpected power state %d", state);
+		ASSERT(0);
+		break;
 	}
 
 	return state;
@@ -449,6 +516,41 @@ static void power_button_changed(void)
 }
 DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, power_button_changed, HOOK_PRIO_DEFAULT);
 
+#ifdef CONFIG_POWER_TRACK_HOST_SLEEP_STATE
+__overridable void
+power_chipset_handle_sleep_hang(enum sleep_hang_type hang_type)
+{
+	CPRINTS("Warning: Detected sleep hang! Waking host up!");
+	host_set_single_event(EC_HOST_EVENT_HANG_DETECT);
+}
+
+__override void
+power_chipset_handle_host_sleep_event(enum host_sleep_event state,
+				      struct host_sleep_event_context *ctx)
+{
+	CPRINTS("Handle sleep: %d", state);
+
+	if (state == HOST_SLEEP_EVENT_S3_SUSPEND) {
+		/*
+		 * Indicate to power state machine that a new host event for
+		 * S3 suspend has been received and so chipset suspend
+		 * notification needs to be sent to listeners.
+		 */
+		sleep_set_notify(SLEEP_NOTIFY_SUSPEND);
+		sleep_start_suspend(ctx);
+
+	} else if (state == HOST_SLEEP_EVENT_S3_RESUME) {
+		/*
+		 * Wake up chipset task and indicate to power state machine that
+		 * listeners need to be notified of chipset resume.
+		 */
+		sleep_set_notify(SLEEP_NOTIFY_RESUME);
+		task_wake(TASK_ID_CHIPSET);
+		sleep_complete_resume(ctx);
+	}
+}
+#endif /* CONFIG_POWER_TRACK_HOST_SLEEP_STATE */
+
 #ifdef CONFIG_LID_SWITCH
 static void lid_changed(void)
 {
diff --git a/power/qcom.c b/power/qcom.c
new file mode 100644
index 0000000000..074dc1407f
--- /dev/null
+++ b/power/qcom.c
@@ -0,0 +1,1196 @@
+/* Copyright 2019 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * SC7X80 SoC power sequencing module for Chrome EC
+ *
+ * This implements the following features:
+ *
+ * - Cold reset powers on the AP
+ *
+ *  When powered off:
+ *  - Press power button turns on the AP
+ *  - Hold power button turns on the AP, and then 8s later turns it off and
+ *    leaves it off until pwron is released and pressed again
+ *  - Lid open turns on the AP
+ *
+ *  When powered on:
+ *  - Holding power button for 8s powers off the AP
+ *  - Pressing and releasing pwron within that 8s is ignored
+ *  - If POWER_GOOD is dropped by the AP, then we power the AP off
+ */
+
+#include "builtin/assert.h"
+#include "charge_state.h"
+#include "chipset.h"
+#include "common.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power/qcom.h"
+#include "power_button.h"
+#include "system.h"
+#include "task.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
+
+/* Power signal list. Must match order of enum power_signal. */
+const struct power_signal_info power_signal_list[] = {
+	[SC7X80_AP_RST_ASSERTED] = {
+		GPIO_AP_RST_L,
+		POWER_SIGNAL_ACTIVE_LOW | POWER_SIGNAL_DISABLE_AT_BOOT,
+		"AP_RST_ASSERTED",
+	},
+	[SC7X80_PS_HOLD] = {
+		GPIO_PS_HOLD,
+		POWER_SIGNAL_ACTIVE_HIGH,
+		"PS_HOLD",
+	},
+	[SC7X80_POWER_GOOD] = {
+		GPIO_POWER_GOOD,
+		POWER_SIGNAL_ACTIVE_HIGH,
+		"POWER_GOOD",
+	},
+	[SC7X80_AP_SUSPEND] = {
+		GPIO_AP_SUSPEND,
+		POWER_SIGNAL_ACTIVE_HIGH | POWER_SIGNAL_NO_LOG,
+		"AP_SUSPEND",
+	},
+#ifdef CONFIG_CHIPSET_SC7180
+	[SC7X80_WARM_RESET] = {
+		GPIO_WARM_RESET_L,
+		POWER_SIGNAL_ACTIVE_HIGH,
+		"WARM_RESET_L",
+	},
+	[SC7X80_DEPRECATED_AP_RST_REQ] = {
+		GPIO_DEPRECATED_AP_RST_REQ,
+		POWER_SIGNAL_ACTIVE_HIGH,
+		"DEPRECATED_AP_RST_REQ",
+	},
+#endif /* defined(CONFIG_CHIPSET_SC7180) */
+};
+BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
+
+/* Masks for power signals */
+#define IN_POWER_GOOD POWER_SIGNAL_MASK(SC7X80_POWER_GOOD)
+#define IN_AP_RST_ASSERTED POWER_SIGNAL_MASK(SC7X80_AP_RST_ASSERTED)
+#define IN_SUSPEND POWER_SIGNAL_MASK(SC7X80_AP_SUSPEND)
+
+/* Long power key press to force shutdown */
+#define DELAY_FORCE_SHUTDOWN (8 * SECOND)
+
+/*
+ * If the power button is pressed to turn on, then held for this long, we
+ * power off.
+ *
+ * Normal case: User releases power button and chipset_task() goes
+ *    into the inner loop, waiting for next event to occur (power button
+ *    press or POWER_GOOD == 0).
+ */
+#define DELAY_SHUTDOWN_ON_POWER_HOLD (8 * SECOND)
+
+/*
+ * After trigger PMIC power sequence, how long it triggers AP to turn on
+ * or off. Observed that the worst case is ~150ms. Pick a safe vale.
+ */
+#define PMIC_POWER_AP_RESPONSE_TIMEOUT (350 * MSEC)
+
+/*
+ * After force off the switch cap, how long the PMIC/AP totally off.
+ * Observed that the worst case is 2s. Pick a safe vale.
+ */
+#define FORCE_OFF_RESPONSE_TIMEOUT (4 * SECOND)
+
+/* Wait for polling the AP on signal */
+#define PMIC_POWER_AP_WAIT (1 * MSEC)
+
+/* The length of an issued low pulse to the PMIC_RESIN_L signal */
+#define PMIC_RESIN_PULSE_LENGTH (20 * MSEC)
+
+/* The timeout of the check if the system can boot AP */
+#define CAN_BOOT_AP_CHECK_TIMEOUT (1500 * MSEC)
+
+/* Wait for polling if the system can boot AP */
+#define CAN_BOOT_AP_CHECK_WAIT (200 * MSEC)
+
+/* The timeout of the check if the switchcap outputs good voltage */
+#define SWITCHCAP_PG_CHECK_TIMEOUT (100 * MSEC)
+
+/* Wait for polling if the switchcap outputs good voltage */
+#define SWITCHCAP_PG_CHECK_WAIT (6 * MSEC)
+
+/*
+ * Delay between power-on the system and power-on the PMIC.
+ * Some latest PMIC firmware needs this delay longer, for doing a cold
+ * reboot.
+ *
+ * Measured on Herobrine IOB + Trogdor MLB, the delay takes ~200ms. Set
+ * it with margin.
+ */
+#define SYSTEM_POWER_ON_DELAY (300 * MSEC)
+
+/*
+ * Delay between the PMIC power drop and power-off the system.
+ * Qualcomm measured the entire POFF duration is around 70ms. Setting
+ * this delay to the same value as the above power-on sequence, which
+ * has much safer margin.
+ */
+#define PMIC_POWER_OFF_DELAY (150 * MSEC)
+
+/* The AP_RST_L transition count of a normal AP warm reset */
+#define EXPECTED_AP_RST_TRANSITIONS 3
+
+/*
+ * The timeout of waiting the next AP_RST_L transition. We measured
+ * the interval between AP_RST_L transitions is 130ms ~ 150ms. Pick
+ * a safer value.
+ */
+#define AP_RST_TRANSITION_TIMEOUT (450 * MSEC)
+
+/* TODO(crosbug.com/p/25047): move to HOOK_POWER_BUTTON_CHANGE */
+/* 1 if the power button was pressed last time we checked */
+static char power_button_was_pressed;
+
+/* 1 if lid-open event has been detected */
+static char lid_opened;
+
+/* Time where we will power off, if power button still held down */
+static timestamp_t power_off_deadline;
+
+/* Force AP power on (used for recovery keypress) */
+static int auto_power_on;
+
+enum power_request_t {
+	POWER_REQ_NONE,
+	POWER_REQ_OFF,
+	POWER_REQ_ON,
+	POWER_REQ_COLD_RESET,
+	POWER_REQ_WARM_RESET,
+
+	POWER_REQ_COUNT,
+};
+
+static enum power_request_t power_request;
+
+/**
+ * Return values for check_for_power_off_event().
+ */
+enum power_off_event_t {
+	POWER_OFF_CANCEL,
+	POWER_OFF_BY_POWER_BUTTON_PRESSED,
+	POWER_OFF_BY_LONG_PRESS,
+	POWER_OFF_BY_POWER_GOOD_LOST,
+	POWER_OFF_BY_POWER_REQ_OFF,
+	POWER_OFF_BY_POWER_REQ_RESET,
+
+	POWER_OFF_EVENT_COUNT,
+};
+
+/**
+ * Return values for check_for_power_on_event().
+ */
+enum power_on_event_t {
+	POWER_ON_CANCEL,
+	POWER_ON_BY_AUTO_POWER_ON,
+	POWER_ON_BY_LID_OPEN,
+	POWER_ON_BY_POWER_BUTTON_PRESSED,
+	POWER_ON_BY_POWER_REQ_ON,
+	POWER_ON_BY_POWER_REQ_RESET,
+
+	POWER_ON_EVENT_COUNT,
+};
+
+#ifdef CONFIG_CHIPSET_RESET_HOOK
+static int ap_rst_transitions;
+
+static void notify_chipset_reset(void)
+{
+	if (ap_rst_transitions != EXPECTED_AP_RST_TRANSITIONS)
+		CPRINTS("AP_RST_L transitions not expected: %d",
+			ap_rst_transitions);
+
+	ap_rst_transitions = 0;
+	hook_notify(HOOK_CHIPSET_RESET);
+}
+DECLARE_DEFERRED(notify_chipset_reset);
+#endif
+
+void chipset_ap_rst_interrupt(enum gpio_signal signal)
+{
+#ifdef CONFIG_CHIPSET_RESET_HOOK
+	int delay;
+
+	/*
+	 * Only care the raising edge and AP in S0/S3. The single raising edge
+	 * of AP power-on during S5S3 is ignored.
+	 */
+	if (gpio_get_level(GPIO_AP_RST_L) &&
+	    chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_SUSPEND)) {
+		ap_rst_transitions++;
+		if (ap_rst_transitions >= EXPECTED_AP_RST_TRANSITIONS) {
+			/*
+			 * Reach the expected transition count. AP is booting
+			 * up. Notify HOOK_CHIPSET_RESET immediately.
+			 */
+			delay = 0;
+		} else {
+			/*
+			 * Should have more transitions of the AP_RST_L signal.
+			 * In case the AP_RST_L signal is not toggled, still
+			 * notify HOOK_CHIPSET_RESET.
+			 */
+			delay = AP_RST_TRANSITION_TIMEOUT;
+		}
+		hook_call_deferred(&notify_chipset_reset_data, delay);
+	}
+#endif
+	power_signal_interrupt(signal);
+}
+
+#ifdef CONFIG_CHIPSET_SC7180
+
+/* 1 if AP_RST_L and PS_HOLD is overdriven by EC */
+static char ap_rst_overdriven;
+
+/* Issue a request to initiate a reset sequence */
+static void request_cold_reset(void)
+{
+	power_request = POWER_REQ_COLD_RESET;
+	task_wake(TASK_ID_CHIPSET);
+}
+
+void chipset_warm_reset_interrupt(enum gpio_signal signal)
+{
+	/*
+	 * The warm_reset signal is pulled-up by a rail from PMIC. If the
+	 * warm_reset drops, it means:
+	 *  * Servo or Cr50 holds the signal, or
+	 *  * its pull-up rail POWER_GOOD drops.
+	 */
+	if (!gpio_get_level(GPIO_WARM_RESET_L)) {
+		if (gpio_get_level(GPIO_POWER_GOOD)) {
+			/*
+			 * Servo or Cr50 holds the WARM_RESET_L signal.
+			 *
+			 * Overdrive AP_RST_L to hold AP. Overdrive PS_HOLD to
+			 * emulate AP being up to trick the PMIC into thinking
+			 * there’s nothing weird going on.
+			 */
+			ap_rst_overdriven = 1;
+			gpio_set_flags(GPIO_PS_HOLD, GPIO_INT_BOTH |
+							     GPIO_SEL_1P8V |
+							     GPIO_OUT_HIGH);
+			gpio_set_flags(GPIO_AP_RST_L, GPIO_INT_BOTH |
+							      GPIO_SEL_1P8V |
+							      GPIO_OUT_LOW);
+		}
+		/* Ignore the else clause, the pull-up rail drops. */
+	} else {
+		if (ap_rst_overdriven) {
+			/*
+			 * Servo or Cr50 releases the WARM_RESET_L signal.
+			 *
+			 * Cold reset the PMIC, doing S0->S5->S0 transition,
+			 * by issuing a request to initiate a reset sequence,
+			 * to recover the system. The transition to S5 makes
+			 * POWER_GOOD drop that triggers an interrupt to
+			 * high-Z both AP_RST_L and PS_HOLD.
+			 */
+			CPRINTS("Long warm reset ended, "
+				"cold resetting to restore confidence.");
+			request_cold_reset();
+		}
+		/* If not overdriven, just a normal power-up, do nothing. */
+	}
+	power_signal_interrupt(signal);
+}
+
+void chipset_power_good_interrupt(enum gpio_signal signal)
+{
+	if (!gpio_get_level(GPIO_POWER_GOOD) && ap_rst_overdriven) {
+		/*
+		 * POWER_GOOD is the pull-up rail of WARM_RESET_L.
+		 * When POWER_GOOD drops, high-Z both AP_RST_L and PS_HOLD
+		 * to restore their states.
+		 */
+		gpio_set_flags(GPIO_AP_RST_L, GPIO_INT_BOTH | GPIO_SEL_1P8V);
+		gpio_set_flags(GPIO_PS_HOLD, GPIO_INT_BOTH | GPIO_SEL_1P8V);
+		ap_rst_overdriven = 0;
+	}
+	power_signal_interrupt(signal);
+}
+#endif /* defined(CONFIG_CHIPSET_SC7180) */
+
+static void sc7x80_lid_event(void)
+{
+	/* Power task only cares about lid-open events */
+	if (!lid_is_open())
+		return;
+
+	lid_opened = 1;
+	task_wake(TASK_ID_CHIPSET);
+}
+DECLARE_HOOK(HOOK_LID_CHANGE, sc7x80_lid_event, HOOK_PRIO_DEFAULT);
+
+static void sc7x80_powerbtn_changed(void)
+{
+	task_wake(TASK_ID_CHIPSET);
+}
+DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, sc7x80_powerbtn_changed,
+	     HOOK_PRIO_DEFAULT);
+
+/**
+ * Wait the switchcap GPIO0 PVC_PG signal asserted.
+ *
+ * When the output voltage is over the threshold PVC_PG_ADJ,
+ * the PVC_PG is asserted.
+ *
+ * PVG_PG_ADJ is configured to 3.0V.
+ * GPIO0 is configured as PVC_PG.
+ *
+ * @param enable	1 to wait the PMIC/AP on.
+ *			0 to wait the PMIC/AP off.
+ *
+ * @return EC_SUCCESS or error
+ */
+static int wait_switchcap_power_good(int enable)
+{
+	timestamp_t poll_deadline;
+
+	poll_deadline = get_time();
+	poll_deadline.val += SWITCHCAP_PG_CHECK_TIMEOUT;
+	while (enable != board_is_switchcap_power_good() &&
+	       get_time().val < poll_deadline.val) {
+		usleep(SWITCHCAP_PG_CHECK_WAIT);
+	}
+
+	/*
+	 * Check the timeout case. Just show a message. More check later
+	 * will switch the power state.
+	 */
+	if (enable != board_is_switchcap_power_good()) {
+		if (enable)
+			CPRINTS("SWITCHCAP NO POWER GOOD!");
+		else
+			CPRINTS("SWITCHCAP STILL POWER GOOD!");
+		return EC_ERROR_UNKNOWN;
+	}
+	return EC_SUCCESS;
+}
+
+/**
+ * Get the state of the system power signals.
+ *
+ * @return 1 if the system is powered, 0 if not
+ */
+static int is_system_powered(void)
+{
+	return board_is_switchcap_enabled();
+}
+
+/**
+ * Get the PMIC/AP power signal.
+ *
+ * We treat the PMIC chips and the AP as a whole here. Don't deal with
+ * the individual chip.
+ *
+ * @return 1 if the PMIC/AP is powered, 0 if not
+ */
+static int is_pmic_pwron(void)
+{
+	/* Use POWER_GOOD to indicate PMIC/AP is on/off */
+	return gpio_get_level(GPIO_POWER_GOOD);
+}
+
+/**
+ * Wait the PMIC/AP power-on state.
+ *
+ * @param enable	1 to wait the PMIC/AP on.
+ *			0 to wait the PMIC/AP off.
+ * @param timeout	Number of microsecond of timeout.
+ *
+ * @return EC_SUCCESS or error
+ */
+static int wait_pmic_pwron(int enable, unsigned int timeout)
+{
+	timestamp_t poll_deadline;
+
+	/* Check the AP power status */
+	if (enable == is_pmic_pwron())
+		return EC_SUCCESS;
+
+	poll_deadline = get_time();
+	poll_deadline.val += timeout;
+	while (enable != is_pmic_pwron() &&
+	       get_time().val < poll_deadline.val) {
+		usleep(PMIC_POWER_AP_WAIT);
+	}
+
+	/* Check the timeout case */
+	if (enable != is_pmic_pwron()) {
+		if (enable)
+			CPRINTS("AP POWER NOT READY!");
+		else
+			CPRINTS("AP POWER STILL UP!");
+
+		return EC_ERROR_UNKNOWN;
+	}
+	return EC_SUCCESS;
+}
+
+/**
+ * Set the state of the system power signals but without any check.
+ *
+ * The system power signals are the enable pins of SwitchCap.
+ * They control the power of the set of PMIC chips and the AP.
+ *
+ * @param enable	1 to enable or 0 to disable
+ */
+static void set_system_power_no_check(int enable)
+{
+	board_set_switchcap_power(enable);
+}
+
+/**
+ * Set the state of the system power signals.
+ *
+ * The system power signals are the enable pins of SwitchCap.
+ * They control the power of the set of PMIC chips and the AP.
+ *
+ * @param enable	1 to enable or 0 to disable
+ *
+ * @return EC_SUCCESS or error
+ */
+static int set_system_power(int enable)
+{
+	int ret;
+
+	CPRINTS("%s(%d)", __func__, enable);
+	set_system_power_no_check(enable);
+
+	ret = wait_switchcap_power_good(enable);
+
+	if (!enable) {
+		/* Ensure POWER_GOOD drop to low if it is a forced shutdown */
+		ret |= wait_pmic_pwron(0, FORCE_OFF_RESPONSE_TIMEOUT);
+	}
+	usleep(SYSTEM_POWER_ON_DELAY);
+
+	return ret;
+}
+
+/**
+ * Set the PMIC/AP power-on state.
+ *
+ * It triggers the PMIC/AP power-on and power-off sequence.
+ *
+ * @param enable	1 to power the PMIC/AP on.
+ *			0 to power the PMIC/AP off.
+ *
+ * @return EC_SUCCESS or error
+ */
+static int set_pmic_pwron(int enable)
+{
+	int ret;
+
+	CPRINTS("%s(%d)", __func__, enable);
+
+	/* Check the PMIC/AP power state */
+	if (enable == is_pmic_pwron())
+		return EC_SUCCESS;
+
+	if (!gpio_get_level(GPIO_PMIC_RESIN_L)) {
+		CPRINTS("PMIC_RESIN_L not pulled up by PMIC; cancel pwron");
+		return EC_ERROR_UNKNOWN;
+	}
+
+	/*
+	 * Power-on sequence:
+	 * 1. Hold down PMIC_KPD_PWR_ODL, which is a power-on trigger
+	 * 2. PMIC supplies power to POWER_GOOD
+	 * 3. Release PMIC_KPD_PWR_ODL
+	 *
+	 * Power-off sequence:
+	 * 1. Hold down PMIC_KPD_PWR_ODL and PMIC_RESIN_L, which is a power-off
+	 *    trigger (requiring reprogramming PMIC registers to make
+	 *    PMIC_KPD_PWR_ODL + PMIC_RESIN_L as a shutdown trigger)
+	 * 2. PMIC stops supplying power to POWER_GOOD (requiring
+	 *    reprogramming PMIC to set the stage-1 and stage-2 reset timers to
+	 *    0 such that the pull down happens just after the deboucing time
+	 *    of the trigger, like 2ms)
+	 * 3. Release PMIC_KPD_PWR_ODL and PMIC_RESIN_L
+	 *
+	 * If the above PMIC registers not programmed or programmed wrong, it
+	 * falls back to the next functions, which cuts off the system power.
+	 */
+
+	gpio_set_level(GPIO_PMIC_KPD_PWR_ODL, 0);
+	if (!enable)
+		gpio_set_level(GPIO_PMIC_RESIN_L, 0);
+	ret = wait_pmic_pwron(enable, PMIC_POWER_AP_RESPONSE_TIMEOUT);
+	gpio_set_level(GPIO_PMIC_KPD_PWR_ODL, 1);
+	if (!enable)
+		gpio_set_level(GPIO_PMIC_RESIN_L, 1);
+
+	return ret;
+}
+
+enum power_state power_chipset_init(void)
+{
+	int init_power_state;
+	uint32_t reset_flags = system_get_reset_flags();
+
+	/* Enable interrupts */
+	if (IS_ENABLED(CONFIG_CHIPSET_SC7180)) {
+		gpio_enable_interrupt(GPIO_WARM_RESET_L);
+		gpio_enable_interrupt(GPIO_POWER_GOOD);
+	}
+
+	/*
+	 * Force the AP shutdown unless we are doing SYSJUMP. Otherwise,
+	 * the AP could stay in strange state.
+	 */
+	if (!(reset_flags & EC_RESET_FLAG_SYSJUMP)) {
+		CPRINTS("not sysjump; forcing system shutdown");
+		set_system_power_no_check(0);
+		init_power_state = POWER_G3;
+	} else {
+		/* In the SYSJUMP case, we check if the AP is on */
+		if (power_get_signals() & IN_POWER_GOOD) {
+			CPRINTS("SOC ON");
+			init_power_state = POWER_S0;
+
+			/*
+			 * Reenable the power signal AP_RST_L interrupt, which
+			 * should be enabled during S5->S3 but sysjump makes
+			 * it back to default, disabled.
+			 */
+			power_signal_enable_interrupt(GPIO_AP_RST_L);
+
+			/* Disable idle task deep sleep when in S0 */
+			disable_sleep(SLEEP_MASK_AP_RUN);
+		} else {
+			CPRINTS("SOC OFF");
+			init_power_state = POWER_G3;
+		}
+	}
+
+	auto_power_on = 1;
+
+	/*
+	 * Leave power off only if requested by reset flags
+	 *
+	 * TODO(b/201099749): EC bootloader: Give RO chance to run EFS after
+	 * shutdown from recovery screen
+	 */
+	if (reset_flags & EC_RESET_FLAG_AP_OFF)
+		auto_power_on = 0;
+	else if (!(reset_flags & EC_RESET_FLAG_EFS) &&
+		 (reset_flags & EC_RESET_FLAG_SYSJUMP))
+		auto_power_on = 0;
+
+	if (battery_is_present() == BP_YES) {
+		/*
+		 * (crosbug.com/p/28289): Wait battery stable.
+		 * Some batteries use clock stretching feature, which requires
+		 * more time to be stable.
+		 */
+		battery_wait_for_stable();
+	}
+
+	if (auto_power_on)
+		CPRINTS("auto_power_on set due to reset flags");
+
+	return init_power_state;
+}
+
+/*****************************************************************************/
+
+/**
+ * Power off the AP
+ *
+ * @param shutdown_event	reason of shutdown, which is a return value of
+ *				check_for_power_off_event()
+ */
+static void power_off_seq(uint8_t shutdown_event)
+{
+	/* Check PMIC POWER_GOOD */
+	if (is_pmic_pwron()) {
+		if (shutdown_event == POWER_OFF_BY_POWER_GOOD_LOST) {
+			/*
+			 * The POWER_GOOD was lost previously, which sets the
+			 * shutdown_event flag. But now it is up again. This
+			 * is unexpected. Show the warning message. Then go
+			 * straight to turn off the switchcap.
+			 */
+			CPRINTS("Warning: POWER_GOOD up again after lost");
+		} else {
+			/* Do a graceful way to shutdown PMIC/AP first */
+			set_pmic_pwron(0);
+			usleep(PMIC_POWER_OFF_DELAY);
+		}
+	}
+
+	/*
+	 * Disable signal interrupts, as they are floating when
+	 * switchcap off.
+	 */
+	power_signal_disable_interrupt(GPIO_AP_RST_L);
+
+	/* Check the switchcap status */
+	if (is_system_powered()) {
+		/* Force to switch off all rails */
+		set_system_power(0);
+	}
+
+	lid_opened = 0;
+}
+
+/**
+ * Check if the power is enough to boot the AP.
+ */
+static int power_is_enough(void)
+{
+	timestamp_t poll_deadline;
+
+	/* If powered by adapter only, wait a while for PD negoiation. */
+	poll_deadline = get_time();
+	poll_deadline.val += CAN_BOOT_AP_CHECK_TIMEOUT;
+
+	/*
+	 * Wait for PD negotiation. If a system with drained battery, don't
+	 * waste the time and exit the loop.
+	 */
+	while (!system_can_boot_ap() && !charge_want_shutdown() &&
+	       get_time().val < poll_deadline.val) {
+		usleep(CAN_BOOT_AP_CHECK_WAIT);
+	}
+
+	return system_can_boot_ap() && !charge_want_shutdown();
+}
+
+/**
+ * Power on the AP
+ *
+ * @return EC_SUCCESS or error
+ */
+static int power_on_seq(void)
+{
+	int ret;
+
+	ret = set_system_power(1);
+	if (ret != EC_SUCCESS)
+		return ret;
+
+	/* Enable signal interrupts */
+	power_signal_enable_interrupt(GPIO_AP_RST_L);
+
+	ret = set_pmic_pwron(1);
+	if (ret != EC_SUCCESS) {
+		CPRINTS("POWER_GOOD not seen in time");
+		return ret;
+	}
+
+	CPRINTS("POWER_GOOD seen");
+	return EC_SUCCESS;
+}
+
+/**
+ * Check if there has been a power-on event
+ *
+ * This checks all power-on event signals and returns non-zero if any have been
+ * triggered (with debounce taken into account).
+ *
+ * @return non-zero if there has been a power-on event, 0 if not.
+ */
+static uint8_t check_for_power_on_event(void)
+{
+	uint8_t ret;
+
+	if (power_request == POWER_REQ_ON) {
+		ret = POWER_ON_BY_POWER_REQ_ON;
+	} else if (power_request == POWER_REQ_COLD_RESET) {
+		ret = POWER_ON_BY_POWER_REQ_RESET;
+	} else if (auto_power_on) {
+		/* power on requested at EC startup for recovery */
+		ret = POWER_ON_BY_AUTO_POWER_ON;
+	} else if (lid_opened) {
+		/* check lid open */
+		ret = POWER_ON_BY_LID_OPEN;
+	} else if (power_button_is_pressed()) {
+		/* check for power button press */
+		ret = POWER_ON_BY_POWER_BUTTON_PRESSED;
+	} else {
+		ret = POWER_OFF_CANCEL;
+	}
+
+	/* The flags are handled above. Clear them all. */
+	power_request = POWER_REQ_NONE;
+	auto_power_on = 0;
+	lid_opened = 0;
+
+	return ret;
+}
+
+/**
+ * Check for some event triggering the shutdown.
+ *
+ * It can be either a long power button press or a shutdown triggered from the
+ * AP and detected by reading POWER_GOOD.
+ *
+ * @return non-zero if a shutdown should happen, 0 if not
+ */
+static uint8_t check_for_power_off_event(void)
+{
+	timestamp_t now;
+	int pressed = 0;
+
+	if (power_request == POWER_REQ_OFF) {
+		power_request = POWER_REQ_NONE;
+		return POWER_OFF_BY_POWER_REQ_OFF;
+	} else if (power_request == POWER_REQ_COLD_RESET) {
+		/*
+		 * The power_request flag will be cleared later
+		 * in check_for_power_on_event() in S5.
+		 */
+		return POWER_OFF_BY_POWER_REQ_RESET;
+	}
+	/* Clear invalid request */
+	power_request = POWER_REQ_NONE;
+
+	/*
+	 * Check for power button press.
+	 */
+	if (power_button_is_pressed())
+		pressed = POWER_OFF_BY_POWER_BUTTON_PRESSED;
+
+	now = get_time();
+	if (pressed) {
+		if (!power_button_was_pressed) {
+			power_off_deadline.val = now.val + DELAY_FORCE_SHUTDOWN;
+			CPRINTS("power waiting for long press %u",
+				power_off_deadline.le.lo);
+			/* Ensure we will wake up to check the power key */
+			timer_arm(power_off_deadline, TASK_ID_CHIPSET);
+		} else if (timestamp_expired(power_off_deadline, &now)) {
+			power_off_deadline.val = 0;
+			CPRINTS("power off after long press now=%u, %u",
+				now.le.lo, power_off_deadline.le.lo);
+			return POWER_OFF_BY_LONG_PRESS;
+		}
+	} else if (power_button_was_pressed) {
+		CPRINTS("power off cancel");
+		timer_cancel(TASK_ID_CHIPSET);
+	}
+
+	power_button_was_pressed = pressed;
+
+	/* POWER_GOOD released by AP : shutdown immediately */
+	if (!power_has_signals(IN_POWER_GOOD)) {
+		CPRINTS("POWER_GOOD is lost");
+		return POWER_OFF_BY_POWER_GOOD_LOST;
+	}
+
+	return POWER_OFF_CANCEL;
+}
+
+/**
+ * Cancel the power button timer.
+ *
+ * The timer was previously created in the check_for_power_off_event(),
+ * which waited for the power button long press. Should cancel the timer
+ * during the power state transition; otherwise, EC will crash.
+ */
+static inline void cancel_power_button_timer(void)
+{
+	if (power_button_was_pressed)
+		timer_cancel(TASK_ID_CHIPSET);
+}
+
+/*****************************************************************************/
+/* Chipset interface */
+
+test_mockable void chipset_force_shutdown(enum chipset_shutdown_reason reason)
+{
+	CPRINTS("%s(%d)", __func__, reason);
+	report_ap_reset(reason);
+
+	/* Issue a request to initiate a power-off sequence */
+	power_request = POWER_REQ_OFF;
+	task_wake(TASK_ID_CHIPSET);
+}
+
+test_mockable void chipset_power_on(void)
+{
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
+		power_request = POWER_REQ_ON;
+		task_wake(TASK_ID_CHIPSET);
+	}
+}
+
+/**
+ * Warm reset the AP
+ *
+ * @return EC_SUCCESS or error
+ */
+static int warm_reset_seq(void)
+{
+	int rv;
+
+	/*
+	 * Warm reset sequence:
+	 * 1. Issue a low pulse to PMIC_RESIN_L, which triggers PMIC
+	 *    to do a warm reset (requiring reprogramming PMIC registers
+	 *    to make PMIC_RESIN_L as a warm reset trigger).
+	 * 2. PMIC then issues a low pulse to AP_RST_L to reset AP.
+	 *    EC monitors the signal to see any low pulse.
+	 *    2.1. If a low pulse found, done.
+	 *    2.2. If a low pulse not found (the above PMIC registers
+	 *         not programmed or programmed wrong), issue a request
+	 *         to initiate a cold reset power sequence.
+	 */
+
+	gpio_set_level(GPIO_PMIC_RESIN_L, 0);
+	usleep(PMIC_RESIN_PULSE_LENGTH);
+	gpio_set_level(GPIO_PMIC_RESIN_L, 1);
+
+	rv = power_wait_signals_timeout(IN_AP_RST_ASSERTED,
+					PMIC_POWER_AP_RESPONSE_TIMEOUT);
+
+	/* Exception case: PMIC not work as expected, request a cold reset */
+	if (rv != EC_SUCCESS)
+		return rv;
+
+	return EC_SUCCESS;
+}
+
+/**
+ * Check for some event triggering the warm reset.
+ *
+ * The only event is a request by the console command `apreset`.
+ */
+static void check_for_warm_reset_event(void)
+{
+	int rv;
+
+	if (power_request == POWER_REQ_WARM_RESET) {
+		power_request = POWER_REQ_NONE;
+		rv = warm_reset_seq();
+		if (rv != EC_SUCCESS) {
+			CPRINTS("AP refuses to warm reset. Cold resetting.");
+			power_request = POWER_REQ_COLD_RESET;
+		}
+	}
+}
+
+test_mockable void chipset_reset(enum chipset_shutdown_reason reason)
+{
+	CPRINTS("%s(%d)", __func__, reason);
+	report_ap_reset(reason);
+
+	power_request = POWER_REQ_WARM_RESET;
+	task_wake(TASK_ID_CHIPSET);
+}
+
+/* Get system sleep state through GPIOs */
+static inline int chipset_get_sleep_signal(void)
+{
+	return (power_get_signals() & IN_SUSPEND) == IN_SUSPEND;
+}
+
+__override void power_chipset_handle_sleep_hang(enum sleep_hang_type hang_type)
+{
+	CPRINTS("Warning: Detected sleep hang! Waking host up!");
+	host_set_single_event(EC_HOST_EVENT_HANG_DETECT);
+}
+
+static void power_reset_host_sleep_state(void)
+{
+	power_set_host_sleep_state(HOST_SLEEP_EVENT_DEFAULT_RESET);
+	sleep_reset_tracking();
+	power_chipset_handle_host_sleep_event(HOST_SLEEP_EVENT_DEFAULT_RESET,
+					      NULL);
+}
+
+static void handle_chipset_reset(void)
+{
+	if (chipset_in_state(CHIPSET_STATE_SUSPEND)) {
+		CPRINTS("Chipset reset: exit s3");
+		power_reset_host_sleep_state();
+		task_wake(TASK_ID_CHIPSET);
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESET, handle_chipset_reset, HOOK_PRIO_FIRST);
+
+__override void
+power_chipset_handle_host_sleep_event(enum host_sleep_event state,
+				      struct host_sleep_event_context *ctx)
+{
+	CPRINTS("Handle sleep: %d", state);
+
+	if (state == HOST_SLEEP_EVENT_S3_SUSPEND) {
+		/*
+		 * Indicate to power state machine that a new host event for
+		 * S3 suspend has been received and so chipset suspend
+		 * notification needs to be sent to listeners.
+		 */
+		sleep_set_notify(SLEEP_NOTIFY_SUSPEND);
+		sleep_start_suspend(ctx);
+		power_signal_enable_interrupt(GPIO_AP_SUSPEND);
+
+	} else if (state == HOST_SLEEP_EVENT_S3_RESUME) {
+		/*
+		 * Wake up chipset task and indicate to power state machine that
+		 * listeners need to be notified of chipset resume.
+		 */
+		sleep_set_notify(SLEEP_NOTIFY_RESUME);
+		task_wake(TASK_ID_CHIPSET);
+		power_signal_disable_interrupt(GPIO_AP_SUSPEND);
+		sleep_complete_resume(ctx);
+
+	} else if (state == HOST_SLEEP_EVENT_DEFAULT_RESET) {
+		power_signal_disable_interrupt(GPIO_AP_SUSPEND);
+	}
+}
+
+/**
+ * Power handler for steady states
+ *
+ * @param state		Current power state
+ * @return Updated power state
+ */
+test_mockable enum power_state power_handle_state(enum power_state state)
+{
+	static uint8_t boot_from_off, shutdown_from_on;
+
+	switch (state) {
+	case POWER_G3:
+		boot_from_off = check_for_power_on_event();
+		if (boot_from_off)
+			return POWER_G3S5;
+		break;
+
+	case POWER_G3S5:
+		return POWER_S5;
+
+	case POWER_S5:
+		if (!boot_from_off)
+			boot_from_off = check_for_power_on_event();
+
+		if (boot_from_off) {
+			CPRINTS("power on %d", boot_from_off);
+			return POWER_S5S3;
+		}
+		break;
+
+	case POWER_S5S3:
+		/*
+		 * Wait for power button release before actually boot AP.
+		 * It may be a long-hold power button with volume buttons
+		 * to trigger the recovery button. We don't want AP up
+		 * during the long-hold.
+		 */
+		power_button_wait_for_release(-1);
+
+		/* If no enough power, return back to S5. */
+		if (!power_is_enough()) {
+			boot_from_off = 0;
+			return POWER_S5;
+		}
+
+		/* Initialize components to ready state before AP is up. */
+		hook_notify(HOOK_CHIPSET_PRE_INIT);
+
+		if (power_on_seq() != EC_SUCCESS) {
+			power_off_seq(shutdown_from_on);
+			boot_from_off = 0;
+			return POWER_S5;
+		}
+		CPRINTS("AP running ...");
+
+		/* Call hooks now that AP is running */
+		hook_notify(HOOK_CHIPSET_STARTUP);
+
+		/*
+		 * Clearing the sleep failure detection tracking on the path
+		 * to S0 to handle any reset conditions.
+		 */
+		power_reset_host_sleep_state();
+		return POWER_S3;
+
+	case POWER_S3:
+		if (!shutdown_from_on)
+			shutdown_from_on = check_for_power_off_event();
+
+		if (shutdown_from_on) {
+			CPRINTS("power off %d", shutdown_from_on);
+			return POWER_S3S5;
+		}
+
+		/*
+		 * AP has woken up and it deasserts the suspend signal;
+		 * go to S0.
+		 *
+		 * In S0, it will wait for a host event and then trigger the
+		 * RESUME hook.
+		 */
+		if (!chipset_get_sleep_signal())
+			return POWER_S3S0;
+		break;
+
+	case POWER_S3S0:
+		cancel_power_button_timer();
+
+#ifdef CONFIG_CHIPSET_RESUME_INIT_HOOK
+		/*
+		 * Notify the RESUME_INIT hooks, i.e. enabling SPI driver
+		 * to receive host commands/events.
+		 *
+		 * If boot from an off state, notify the RESUME hooks too;
+		 * otherwise (resume from S3), the normal RESUME hooks will
+		 * be notified later, after receive a host resume event.
+		 */
+		hook_notify(HOOK_CHIPSET_RESUME_INIT);
+		if (boot_from_off)
+			hook_notify(HOOK_CHIPSET_RESUME);
+#else
+		hook_notify(HOOK_CHIPSET_RESUME);
+#endif
+		sleep_resume_transition();
+
+		boot_from_off = 0;
+		disable_sleep(SLEEP_MASK_AP_RUN);
+		return POWER_S0;
+
+	case POWER_S0:
+		check_for_warm_reset_event();
+
+		shutdown_from_on = check_for_power_off_event();
+		if (shutdown_from_on) {
+			return POWER_S0S3;
+		} else if (power_get_host_sleep_state() ==
+				   HOST_SLEEP_EVENT_S3_SUSPEND &&
+			   chipset_get_sleep_signal()) {
+			return POWER_S0S3;
+		}
+		/* When receive the host event, trigger the RESUME hook. */
+		sleep_notify_transition(SLEEP_NOTIFY_RESUME,
+					HOOK_CHIPSET_RESUME);
+		break;
+
+	case POWER_S0S3:
+		cancel_power_button_timer();
+
+		/*
+		 * Call SUSPEND hooks only if we haven't notified listeners of
+		 * S3 suspend.
+		 */
+		sleep_notify_transition(SLEEP_NOTIFY_SUSPEND,
+					HOOK_CHIPSET_SUSPEND);
+#ifdef CONFIG_CHIPSET_RESUME_INIT_HOOK
+		/*
+		 * Pair with the HOOK_CHIPSET_RESUME_INIT, i.e. disabling SPI
+		 * driver, by notifying the SUSPEND_COMPLETE hooks.
+		 *
+		 * If shutdown from an on state, notify the SUSPEND hooks too;
+		 * otherwise (suspend from S0), the normal SUSPEND hooks have
+		 * been notified in the above sleep_notify_transition() call.
+		 */
+		if (shutdown_from_on)
+			hook_notify(HOOK_CHIPSET_SUSPEND);
+		hook_notify(HOOK_CHIPSET_SUSPEND_COMPLETE);
+#else
+		hook_notify(HOOK_CHIPSET_SUSPEND);
+#endif
+		sleep_suspend_transition();
+
+		enable_sleep(SLEEP_MASK_AP_RUN);
+		return POWER_S3;
+
+	case POWER_S3S5:
+		cancel_power_button_timer();
+
+		/* Call hooks before we drop power rails */
+		hook_notify(HOOK_CHIPSET_SHUTDOWN);
+
+		power_off_seq(shutdown_from_on);
+		CPRINTS("power shutdown complete");
+
+		/* Call hooks after we drop power rails */
+		hook_notify(HOOK_CHIPSET_SHUTDOWN_COMPLETE);
+
+		shutdown_from_on = 0;
+
+		/*
+		 * Wait forever for the release of the power button; otherwise,
+		 * this power button press will then trigger a power-on in S5.
+		 */
+		power_button_wait_for_release(-1);
+		power_button_was_pressed = 0;
+		return POWER_S5;
+
+	case POWER_S5G3:
+		return POWER_G3;
+
+	default:
+		CPRINTS("Unexpected power state %d", state);
+		ASSERT(0);
+	}
+
+	return state;
+}
+
+/*****************************************************************************/
+/* Console debug command */
+
+static const char *power_req_name[POWER_REQ_COUNT] = {
+	"none",
+	"off",
+	"on",
+};
+
+/* Power states that we can report */
+enum power_state_t {
+	PSTATE_UNKNOWN,
+	PSTATE_OFF,
+	PSTATE_ON,
+	PSTATE_COUNT,
+};
+
+static const char *const state_name[] = {
+	"unknown",
+	"off",
+	"on",
+};
+
+test_mockable_static int command_power(int argc, const char **argv)
+{
+	int v;
+
+	if (argc < 2) {
+		enum power_state_t state;
+
+		state = PSTATE_UNKNOWN;
+		if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+			state = PSTATE_OFF;
+		if (chipset_in_state(CHIPSET_STATE_ON))
+			state = PSTATE_ON;
+		ccprintf("%s\n", state_name[state]);
+
+		return EC_SUCCESS;
+	}
+
+	if (!parse_bool(argv[1], &v))
+		return EC_ERROR_PARAM1;
+
+	power_request = v ? POWER_REQ_ON : POWER_REQ_OFF;
+	ccprintf("Requesting power %s\n", power_req_name[power_request]);
+	task_wake(TASK_ID_CHIPSET);
+
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(power, command_power, "on/off", "Turn AP power on/off");
diff --git a/power/rk3288.c b/power/rk3288.c
index c647ab97b2..8aea147391 100644
--- a/power/rk3288.c
+++ b/power/rk3288.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,15 +24,16 @@
  */
 
 #include "battery.h"
+#include "builtin/assert.h"
 #include "charge_state.h"
-#include "chipset.h"  /* This module implements chipset functions too */
+#include "chipset.h" /* This module implements chipset functions too */
 #include "clock.h"
 #include "common.h"
 #include "console.h"
 #include "gpio.h"
 #include "hooks.h"
-#include "lid_switch.h"
 #include "keyboard_scan.h"
+#include "lid_switch.h"
 #include "power.h"
 #include "power_button.h"
 #include "power_led.h"
@@ -43,14 +44,14 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 /* masks for power signals */
 #define IN_POWER_GOOD POWER_SIGNAL_MASK(RK_POWER_GOOD)
 #define IN_SUSPEND POWER_SIGNAL_MASK(RK_SUSPEND_ASSERTED)
 
 /* Long power key press to force shutdown */
-#define DELAY_FORCE_SHUTDOWN  (8 * SECOND)
+#define DELAY_FORCE_SHUTDOWN (8 * SECOND)
 
 /*
  * If the power key is pressed to turn on, then held for this long, we
@@ -60,7 +61,7 @@
  *    into the inner loop, waiting for next event to occur (power button
  *    press or power good == 0).
  */
-#define DELAY_SHUTDOWN_ON_POWER_HOLD	(8 * SECOND)
+#define DELAY_SHUTDOWN_ON_POWER_HOLD (8 * SECOND)
 
 /*
  * The hold time for pulling down the PMIC_WARM_RESET_L pin so that
@@ -101,11 +102,9 @@ enum power_request_t {
 
 static enum power_request_t power_request;
 
-
 /* Forward declaration */
 static void chipset_turn_off_power_rails(void);
 
-
 /**
  * Set the PMIC WARM RESET signal.
  *
@@ -117,7 +116,6 @@ static void set_pmic_warm_reset(int asserted)
 	gpio_set_level(GPIO_PMIC_WARM_RESET_L, asserted ? 0 : 1);
 }
 
-
 /**
  * Set the PMIC PWRON signal.
  *
@@ -161,7 +159,7 @@ static int check_for_power_off_event(void)
 		pressed = 1;
 	} else if (power_request == POWER_REQ_OFF) {
 		power_request = POWER_REQ_NONE;
-		return 4;  /* return non-zero for shudown down */
+		return 4; /* return non-zero for shudown down */
 	}
 
 	now = get_time();
@@ -294,13 +292,11 @@ static int check_for_power_on_event(void)
 	/* check if system is already ON */
 	if (power_get_signals() & IN_POWER_GOOD) {
 		if (ap_off_flag) {
-			CPRINTS(
-				"system is on, but "
+			CPRINTS("system is on, but "
 				"EC_RESET_FLAG_AP_OFF is on");
 			return 0;
 		} else {
-			CPRINTS(
-				"system is on, thus clear "
+			CPRINTS("system is on, thus clear "
 				"auto_power_on");
 			/* no need to arrange another power on */
 			auto_power_on = 0;
@@ -385,13 +381,13 @@ static void power_off(void)
 	hook_notify(HOOK_CHIPSET_SHUTDOWN_COMPLETE);
 }
 
-void chipset_reset(enum chipset_reset_reason reason)
+void chipset_reset(enum chipset_shutdown_reason reason)
 {
 	CPRINTS("%s(%d)", __func__, reason);
 	report_ap_reset(reason);
 
 	CPRINTS("assert GPIO_PMIC_WARM_RESET_L for %d ms",
-			PMIC_WARM_RESET_L_HOLD_TIME / MSEC);
+		PMIC_WARM_RESET_L_HOLD_TIME / MSEC);
 	set_pmic_warm_reset(1);
 	usleep(PMIC_WARM_RESET_L_HOLD_TIME);
 	set_pmic_warm_reset(0);
@@ -437,16 +433,17 @@ enum power_state power_handle_state(enum power_state state)
 		if (power_wait_signals(IN_POWER_GOOD) == EC_SUCCESS) {
 			CPRINTS("POWER_GOOD seen");
 			if (power_button_wait_for_release(
-					DELAY_SHUTDOWN_ON_POWER_HOLD) ==
-					EC_SUCCESS) {
+				    DELAY_SHUTDOWN_ON_POWER_HOLD) ==
+			    EC_SUCCESS) {
 				power_button_was_pressed = 0;
 				set_pmic_pwron(0);
 
 				/* setup misc gpio for S3/S0 functionality */
-				gpio_set_flags(GPIO_SUSPEND_L, GPIO_INPUT
-					| GPIO_INT_BOTH | GPIO_PULL_DOWN);
-				gpio_set_flags(GPIO_EC_INT_L, GPIO_OUTPUT
-						| GPIO_OUT_HIGH);
+				gpio_set_flags(GPIO_SUSPEND_L,
+					       GPIO_INPUT | GPIO_INT_BOTH |
+						       GPIO_PULL_DOWN);
+				gpio_set_flags(GPIO_EC_INT_L,
+					       GPIO_OUTPUT | GPIO_OUT_HIGH);
 
 				/* Call hooks now that AP is running */
 				hook_notify(HOOK_CHIPSET_STARTUP);
@@ -506,6 +503,11 @@ enum power_state power_handle_state(enum power_state state)
 
 	case POWER_S5G3:
 		return POWER_G3;
+
+	default:
+		CPRINTS("Unexpected power state %d", state);
+		ASSERT(0);
+		break;
 	}
 
 	return state;
@@ -516,7 +518,7 @@ static void powerbtn_rockchip_changed(void)
 	task_wake(TASK_ID_CHIPSET);
 }
 DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, powerbtn_rockchip_changed,
-		HOOK_PRIO_DEFAULT);
+	     HOOK_PRIO_DEFAULT);
 
 /*****************************************************************************/
 /* Console debug command */
@@ -537,14 +539,14 @@ enum power_state_t {
 	PSTATE_COUNT,
 };
 
-static const char * const state_name[] = {
+static const char *const state_name[] = {
 	"unknown",
 	"off",
 	"suspend",
 	"on",
 };
 
-static int command_power(int argc, char **argv)
+static int command_power(int argc, const char **argv)
 {
 	int v;
 
@@ -572,6 +574,4 @@ static int command_power(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(power, command_power,
-			"on/off",
-			"Turn AP power on/off");
+DECLARE_CONSOLE_COMMAND(power, command_power, "on/off", "Turn AP power on/off");
diff --git a/power/rk3399.c b/power/rk3399.c
index 9db25f0b28..ef4c0407b8 100644
--- a/power/rk3399.c
+++ b/power/rk3399.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,6 +12,7 @@
  * Version 1: Simplified power tree for tablet / detachable.
  */
 
+#include "builtin/assert.h"
 #include "charge_state.h"
 #include "chipset.h"
 #include "common.h"
@@ -30,46 +31,46 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 /* Input state flags */
 #if CONFIG_CHIPSET_POWER_SEQ_VERSION == 1
-	#define IN_PGOOD_PP1250_S3   POWER_SIGNAL_MASK(PP1250_S3_PWR_GOOD)
-	#define IN_PGOOD_PP900_S0    POWER_SIGNAL_MASK(PP900_S0_PWR_GOOD)
+#define IN_PGOOD_PP1250_S3 POWER_SIGNAL_MASK(PP1250_S3_PWR_GOOD)
+#define IN_PGOOD_PP900_S0 POWER_SIGNAL_MASK(PP900_S0_PWR_GOOD)
 #else
-	#define IN_PGOOD_PP5000      POWER_SIGNAL_MASK(PP5000_PWR_GOOD)
-	#define IN_PGOOD_SYS         POWER_SIGNAL_MASK(SYS_PWR_GOOD)
+#define IN_PGOOD_PP5000 POWER_SIGNAL_MASK(PP5000_PWR_GOOD)
+#define IN_PGOOD_SYS POWER_SIGNAL_MASK(SYS_PWR_GOOD)
 #endif
 
-#define IN_PGOOD_AP            POWER_SIGNAL_MASK(AP_PWR_GOOD)
-#define IN_SUSPEND_DEASSERTED  POWER_SIGNAL_MASK(SUSPEND_DEASSERTED)
+#define IN_PGOOD_AP POWER_SIGNAL_MASK(AP_PWR_GOOD)
+#define IN_SUSPEND_DEASSERTED POWER_SIGNAL_MASK(SUSPEND_DEASSERTED)
 
 /* Rails requires for S3 and S0 */
 #if CONFIG_CHIPSET_POWER_SEQ_VERSION == 1
-	#define IN_PGOOD_S3    (IN_PGOOD_PP1250_S3)
-	#define IN_PGOOD_S0    (IN_PGOOD_S3 | IN_PGOOD_PP900_S0 | IN_PGOOD_AP)
-	/* This board can optionally wake-on-USB in S3 */
-	#define S3_USB_WAKE
-	/* This board has non-INT power signal pins */
-	#define POWER_SIGNAL_POLLING
-	/* This board supports CR50 deep sleep mode */
-	#define CR50_DEEP_SLEEP
-	/*
-	 * If AP_PWR_GOOD assertion does not trigger an interrupt, poll the
-	 * signal every 5ms, up to 200 times (~ 1 second timeout).
-	 */
-	#define PGOOD_S0_POLL_TIMEOUT  (5 * MSEC)
-	#define PGOOD_S0_POLL_TRIES    200
+#define IN_PGOOD_S3 (IN_PGOOD_PP1250_S3)
+#define IN_PGOOD_S0 (IN_PGOOD_S3 | IN_PGOOD_PP900_S0 | IN_PGOOD_AP)
+/* This board can optionally wake-on-USB in S3 */
+#define S3_USB_WAKE
+/* This board has non-INT power signal pins */
+#define POWER_SIGNAL_POLLING
+/* This board supports CR50 deep sleep mode */
+#define CR50_DEEP_SLEEP
+/*
+ * If AP_PWR_GOOD assertion does not trigger an interrupt, poll the
+ * signal every 5ms, up to 200 times (~ 1 second timeout).
+ */
+#define PGOOD_S0_POLL_TIMEOUT (5 * MSEC)
+#define PGOOD_S0_POLL_TRIES 200
 #else
-	#define IN_PGOOD_S3    (IN_PGOOD_PP5000)
-	#define IN_PGOOD_S0    (IN_PGOOD_S3 | IN_PGOOD_AP | IN_PGOOD_SYS)
+#define IN_PGOOD_S3 (IN_PGOOD_PP5000)
+#define IN_PGOOD_S0 (IN_PGOOD_S3 | IN_PGOOD_AP | IN_PGOOD_SYS)
 #endif
 
 /* All inputs in the right state for S0 */
-#define IN_ALL_S0              (IN_PGOOD_S0 | IN_SUSPEND_DEASSERTED)
+#define IN_ALL_S0 (IN_PGOOD_S0 | IN_SUSPEND_DEASSERTED)
 
 /* Long power key press to force shutdown in S0 */
-#define FORCED_SHUTDOWN_DELAY  (8 * SECOND)
+#define FORCED_SHUTDOWN_DELAY (8 * SECOND)
 
 #define CHARGER_INITIALIZED_DELAY_MS 100
 #define CHARGER_INITIALIZED_TRIES 40
@@ -126,12 +127,9 @@ static const struct power_seq_op s3s0_power_seq[] = {
 };
 #else
 static const struct power_seq_op s3s0_power_seq[] = {
-	{ GPIO_PPVAR_CLOGIC_EN, 1, 2 },
-	{ GPIO_PP900_DDRPLL_EN, 1, 2 },
-	{ GPIO_PP1800_AP_AVDD_EN_L, 0, 2 },
-	{ GPIO_AP_CORE_EN, 1, 2 },
-	{ GPIO_PP1800_S0_EN_L, 0, 2 },
-	{ GPIO_PP3300_S0_EN_L, 0, 0 },
+	{ GPIO_PPVAR_CLOGIC_EN, 1, 2 },	    { GPIO_PP900_DDRPLL_EN, 1, 2 },
+	{ GPIO_PP1800_AP_AVDD_EN_L, 0, 2 }, { GPIO_AP_CORE_EN, 1, 2 },
+	{ GPIO_PP1800_S0_EN_L, 0, 2 },	    { GPIO_PP3300_S0_EN_L, 0, 0 },
 };
 #endif
 
@@ -151,12 +149,9 @@ static const struct power_seq_op s0s3_power_seq[] = {
 };
 #else
 static const struct power_seq_op s0s3_power_seq[] = {
-	{ GPIO_PP3300_S0_EN_L, 1, 20 },
-	{ GPIO_PP1800_S0_EN_L, 1, 1 },
-	{ GPIO_AP_CORE_EN, 0, 20 },
-	{ GPIO_PP1800_AP_AVDD_EN_L, 1, 1 },
-	{ GPIO_PP900_DDRPLL_EN, 0, 1 },
-	{ GPIO_PPVAR_CLOGIC_EN, 0, 0 },
+	{ GPIO_PP3300_S0_EN_L, 1, 20 }, { GPIO_PP1800_S0_EN_L, 1, 1 },
+	{ GPIO_AP_CORE_EN, 0, 20 },	{ GPIO_PP1800_AP_AVDD_EN_L, 1, 1 },
+	{ GPIO_PP900_DDRPLL_EN, 0, 1 }, { GPIO_PPVAR_CLOGIC_EN, 0, 0 },
 };
 #endif
 
@@ -173,28 +168,19 @@ static const struct power_seq_op s0s3_usb_wake_power_seq[] = {
 /* The power sequence for POWER_S3S5 */
 #if CONFIG_CHIPSET_POWER_SEQ_VERSION == 1
 static const struct power_seq_op s3s5_power_seq[] = {
-	{ GPIO_SYS_RST_L, 0, 0 },
-	{ GPIO_PP1250_S3_EN, 0, 2 },
-	{ GPIO_PP1800_S3_EN, 0, 2 },
-	{ GPIO_PP3300_S3_EN, 0, 2 },
+	{ GPIO_SYS_RST_L, 0, 0 },    { GPIO_PP1250_S3_EN, 0, 2 },
+	{ GPIO_PP1800_S3_EN, 0, 2 }, { GPIO_PP3300_S3_EN, 0, 2 },
 	{ GPIO_PP900_S3_EN, 0, 0 },
 };
 #else
 static const struct power_seq_op s3s5_power_seq[] = {
-	{ GPIO_PP1800_SENSOR_EN_L, 1, 0},
-	{ GPIO_PP1800_SIXAXIS_EN_L, 1, 0},
-	{ GPIO_PP1800_LID_EN_L, 1, 0 },
-	{ GPIO_PP3300_TRACKPAD_EN_L, 1, 0 },
-	{ GPIO_PP5000_EN, 0, 0 },
-	{ GPIO_PP3300_USB_EN_L, 1, 20 },
-	{ GPIO_PP1800_USB_EN_L, 1, 10 },
-	{ GPIO_LPDDR_PWR_EN, 0, 20 },
-	{ GPIO_PP1800_PMU_EN_L, 1, 2 },
-	{ GPIO_PP900_PLL_EN, 0, 0 },
-	{ GPIO_PP900_PMU_EN, 0, 0 },
-	{ GPIO_PP900_USB_EN, 0, 6 },
-	{ GPIO_PP900_PCIE_EN, 0, 0 },
-	{ GPIO_PP900_AP_EN, 0, 0 },
+	{ GPIO_PP1800_SENSOR_EN_L, 1, 0 }, { GPIO_PP1800_SIXAXIS_EN_L, 1, 0 },
+	{ GPIO_PP1800_LID_EN_L, 1, 0 },	   { GPIO_PP3300_TRACKPAD_EN_L, 1, 0 },
+	{ GPIO_PP5000_EN, 0, 0 },	   { GPIO_PP3300_USB_EN_L, 1, 20 },
+	{ GPIO_PP1800_USB_EN_L, 1, 10 },   { GPIO_LPDDR_PWR_EN, 0, 20 },
+	{ GPIO_PP1800_PMU_EN_L, 1, 2 },	   { GPIO_PP900_PLL_EN, 0, 0 },
+	{ GPIO_PP900_PMU_EN, 0, 0 },	   { GPIO_PP900_USB_EN, 0, 6 },
+	{ GPIO_PP900_PCIE_EN, 0, 0 },	   { GPIO_PP900_AP_EN, 0, 0 },
 	{ GPIO_PPVAR_LOGIC_EN, 0, 0 },
 };
 #endif
@@ -215,7 +201,7 @@ void chipset_force_shutdown(enum chipset_shutdown_reason reason)
 }
 
 #define SYS_RST_HOLD_US (1 * MSEC)
-void chipset_reset(enum chipset_reset_reason reason)
+void chipset_reset(enum chipset_shutdown_reason reason)
 {
 #ifdef CONFIG_CMD_RTC
 	/* Print out the RTC to help correlate resets in logs. */
@@ -268,18 +254,18 @@ DECLARE_DEFERRED(force_shutdown);
  * power sequencing, and immediately transition out of suspend if necessary.
  */
 #define SLEEP_INTERVAL_MS 5
-#define MSLEEP_CHECK_ABORTED_SUSPEND(msec) \
-	do { \
-		int sleep_remain = msec; \
-		do { \
-			msleep(MIN(sleep_remain, SLEEP_INTERVAL_MS)); \
-			sleep_remain -= SLEEP_INTERVAL_MS; \
-			if (!forcing_shutdown && \
-			    power_get_signals() & IN_SUSPEND_DEASSERTED)  { \
-				CPRINTS("suspend aborted"); \
-				return POWER_S3S0; \
-			} \
-		} while (sleep_remain > 0); \
+#define MSLEEP_CHECK_ABORTED_SUSPEND(msec)                                 \
+	do {                                                               \
+		int sleep_remain = msec;                                   \
+		do {                                                       \
+			msleep(MIN(sleep_remain, SLEEP_INTERVAL_MS));      \
+			sleep_remain -= SLEEP_INTERVAL_MS;                 \
+			if (!forcing_shutdown &&                           \
+			    power_get_signals() & IN_SUSPEND_DEASSERTED) { \
+				CPRINTS("suspend aborted");                \
+				return POWER_S3S0;                         \
+			}                                                  \
+		} while (sleep_remain > 0);                                \
 	} while (0)
 BUILD_ASSERT(POWER_S3S0 != 0);
 
@@ -295,15 +281,14 @@ static int power_seq_run(const struct power_seq_op *power_seq_ops, int op_count)
 	int i;
 
 	for (i = 0; i < op_count; i++) {
-		gpio_set_level(power_seq_ops[i].signal,
-			       power_seq_ops[i].level);
+		gpio_set_level(power_seq_ops[i].signal, power_seq_ops[i].level);
 		if (!power_seq_ops[i].delay)
 			continue;
 		if ((power_seq_ops == s0s3_power_seq)
 #ifdef S3_USB_WAKE
 		    || (power_seq_ops == s0s3_usb_wake_power_seq)
 #endif
-		   )
+		)
 			MSLEEP_CHECK_ABORTED_SUSPEND(power_seq_ops[i].delay);
 		else
 			msleep(power_seq_ops[i].delay);
@@ -340,8 +325,7 @@ enum power_state power_handle_state(enum power_state state)
 		break;
 
 	case POWER_S0:
-		if (!power_has_signals(IN_PGOOD_S3) ||
-		    forcing_shutdown ||
+		if (!power_has_signals(IN_PGOOD_S3) || forcing_shutdown ||
 		    !(power_get_signals() & IN_SUSPEND_DEASSERTED))
 			return POWER_S0S3;
 
@@ -353,16 +337,15 @@ enum power_state power_handle_state(enum power_state state)
 		 * it here as well.
 		 */
 		if (power_wait_signals_timeout(IN_PGOOD_AP | IN_PGOOD_SYS,
-					       PGOOD_AP_DEBOUNCE_TIMEOUT)
-					       == EC_ERROR_TIMEOUT)
+					       PGOOD_AP_DEBOUNCE_TIMEOUT) ==
+		    EC_ERROR_TIMEOUT)
 			return POWER_S0S3;
 
 		/*
 		 * power_wait_signals_timeout() can block and consume task
 		 * wake events, so re-verify the state of the world.
 		 */
-		if (!power_has_signals(IN_PGOOD_S3) ||
-		    forcing_shutdown ||
+		if (!power_has_signals(IN_PGOOD_S3) || forcing_shutdown ||
 		    !(power_get_signals() & IN_SUSPEND_DEASSERTED))
 			return POWER_S0S3;
 #endif
@@ -444,7 +427,8 @@ enum power_state power_handle_state(enum power_state state)
 		 * interrupt.
 		 */
 		while (power_wait_signals_timeout(IN_PGOOD_S0,
-		       PGOOD_S0_POLL_TIMEOUT) == EC_ERROR_TIMEOUT &&
+						  PGOOD_S0_POLL_TIMEOUT) ==
+			       EC_ERROR_TIMEOUT &&
 		       ++tries < PGOOD_S0_POLL_TRIES)
 			;
 
@@ -529,6 +513,11 @@ enum power_state power_handle_state(enum power_state state)
 
 	case POWER_S5G3:
 		return POWER_G3;
+
+	default:
+		CPRINTS("Unexpected power state %d", state);
+		ASSERT(0);
+		break;
 	}
 
 	return state;
@@ -548,8 +537,7 @@ static void power_button_changed(void)
 #endif
 		}
 		/* Delayed power down from S0/S3, cancel on PB release */
-		hook_call_deferred(&force_shutdown_data,
-				   FORCED_SHUTDOWN_DELAY);
+		hook_call_deferred(&force_shutdown_data, FORCED_SHUTDOWN_DELAY);
 	} else {
 #if CONFIG_CHIPSET_POWER_SEQ_VERSION == 1
 		if (tablet_boot_on_button_release) {
@@ -602,7 +590,7 @@ static void power_signal_changed(void)
 		 * Pass a fake power gpio_signal to power_signal_interrupt().
 		 * Note that here we make power_signal_interrupt() reentrant.
 		 */
-		power_signal_interrupt(POWER_SIGNAL_COUNT);
+		power_signal_interrupt(GPIO_COUNT);
 		in_signals = inew;
 	}
 }
diff --git a/power/sc7180.c b/power/sc7180.c
deleted file mode 100644
index f80703f740..0000000000
--- a/power/sc7180.c
+++ /dev/null
@@ -1,1134 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * SC7180 SoC power sequencing module for Chrome EC
- *
- * This implements the following features:
- *
- * - Cold reset powers on the AP
- *
- *  When powered off:
- *  - Press power button turns on the AP
- *  - Hold power button turns on the AP, and then 8s later turns it off and
- *    leaves it off until pwron is released and pressed again
- *  - Lid open turns on the AP
- *
- *  When powered on:
- *  - Holding power button for 8s powers off the AP
- *  - Pressing and releasing pwron within that 8s is ignored
- *  - If POWER_GOOD is dropped by the AP, then we power the AP off
- */
-
-#include "charge_state.h"
-#include "chipset.h"
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-/* Masks for power signals */
-#define IN_POWER_GOOD		POWER_SIGNAL_MASK(SC7180_POWER_GOOD)
-#define IN_AP_RST_ASSERTED	POWER_SIGNAL_MASK(SC7180_AP_RST_ASSERTED)
-#define IN_SUSPEND		POWER_SIGNAL_MASK(SC7180_AP_SUSPEND)
-
-
-/* Long power key press to force shutdown */
-#define DELAY_FORCE_SHUTDOWN		(8 * SECOND)
-
-/*
- * If the power button is pressed to turn on, then held for this long, we
- * power off.
- *
- * Normal case: User releases power button and chipset_task() goes
- *    into the inner loop, waiting for next event to occur (power button
- *    press or POWER_GOOD == 0).
- */
-#define DELAY_SHUTDOWN_ON_POWER_HOLD	(8 * SECOND)
-
-/*
- * After trigger PMIC power sequence, how long it triggers AP to turn on
- * or off. Observed that the worst case is ~150ms. Pick a safe vale.
- */
-#define PMIC_POWER_AP_RESPONSE_TIMEOUT	(350 * MSEC)
-
-/*
- * After force off the switch cap, how long the PMIC/AP totally off.
- * Observed that the worst case is 2s. Pick a safe vale.
- */
-#define FORCE_OFF_RESPONSE_TIMEOUT	(4 * SECOND)
-
-/* Wait for polling the AP on signal */
-#define PMIC_POWER_AP_WAIT		(1 * MSEC)
-
-/* The length of an issued low pulse to the PMIC_RESIN_L signal */
-#define PMIC_RESIN_PULSE_LENGTH		(20 * MSEC)
-
-/* The timeout of the check if the system can boot AP */
-#define CAN_BOOT_AP_CHECK_TIMEOUT	(1500 * MSEC)
-
-/* Wait for polling if the system can boot AP */
-#define CAN_BOOT_AP_CHECK_WAIT		(100 * MSEC)
-
-/* The timeout of the check if the switchcap outputs good voltage */
-#define SWITCHCAP_PG_CHECK_TIMEOUT	(50 * MSEC)
-
-/* Wait for polling if the switchcap outputs good voltage */
-#define SWITCHCAP_PG_CHECK_WAIT		(5 * MSEC)
-
-/*
- * Delay between power-on the system and power-on the PMIC.
- * Some latest PMIC firmware needs this delay longer, for doing a cold
- * reboot. Did an experiment; it should be 100ms+. Set it with margin.
- */
-#define SYSTEM_POWER_ON_DELAY		(110 * MSEC)
-
-/*
- * Delay between the PMIC power drop and power-off the system.
- * Qualcomm measured the entire POFF duration is around 70ms. Setting
- * this delay to 70ms is more than enough, as the PMIC power drop is in
- * the middle of POFF duration.
- */
-#define PMIC_POWER_OFF_DELAY		(70 * MSEC)
-
-/* The AP_RST_L transition count of a normal AP warm reset */
-#define EXPECTED_AP_RST_TRANSITIONS	3
-
-/*
- * The timeout of waiting the next AP_RST_L transition. We measured
- * the interval between AP_RST_L transitions is 130ms ~ 150ms. Pick
- * a safer value.
- */
-#define AP_RST_TRANSITION_TIMEOUT	(450 * MSEC)
-
-/* TODO(crosbug.com/p/25047): move to HOOK_POWER_BUTTON_CHANGE */
-/* 1 if the power button was pressed last time we checked */
-static char power_button_was_pressed;
-
-/* 1 if lid-open event has been detected */
-static char lid_opened;
-
-/* 1 if AP_RST_L and PS_HOLD is overdriven by EC */
-static char ap_rst_overdriven;
-
-/* Time where we will power off, if power button still held down */
-static timestamp_t power_off_deadline;
-
-/* Force AP power on (used for recovery keypress) */
-static int auto_power_on;
-
-enum power_request_t {
-	POWER_REQ_NONE,
-	POWER_REQ_OFF,
-	POWER_REQ_ON,
-	POWER_REQ_RESET,
-
-	POWER_REQ_COUNT,
-};
-
-static enum power_request_t power_request;
-
-/**
- * Return values for check_for_power_off_event().
- */
-enum power_off_event_t {
-	POWER_OFF_CANCEL,
-	POWER_OFF_BY_POWER_BUTTON_PRESSED,
-	POWER_OFF_BY_LONG_PRESS,
-	POWER_OFF_BY_POWER_GOOD_LOST,
-	POWER_OFF_BY_POWER_REQ_OFF,
-	POWER_OFF_BY_POWER_REQ_RESET,
-
-	POWER_OFF_EVENT_COUNT,
-};
-
-/**
- * Return values for check_for_power_on_event().
- */
-enum power_on_event_t {
-	POWER_ON_CANCEL,
-	POWER_ON_BY_AUTO_POWER_ON,
-	POWER_ON_BY_LID_OPEN,
-	POWER_ON_BY_POWER_BUTTON_PRESSED,
-	POWER_ON_BY_POWER_REQ_ON,
-	POWER_ON_BY_POWER_REQ_RESET,
-
-	POWER_ON_EVENT_COUNT,
-};
-
-#ifdef CONFIG_CHIPSET_RESET_HOOK
-static int ap_rst_transitions;
-
-static void notify_chipset_reset(void)
-{
-	if (ap_rst_transitions != EXPECTED_AP_RST_TRANSITIONS)
-		CPRINTS("AP_RST_L transitions not expected: %d",
-			ap_rst_transitions);
-
-	ap_rst_transitions = 0;
-	hook_notify(HOOK_CHIPSET_RESET);
-}
-DECLARE_DEFERRED(notify_chipset_reset);
-#endif
-
-void chipset_ap_rst_interrupt(enum gpio_signal signal)
-{
-#ifdef CONFIG_CHIPSET_RESET_HOOK
-	int delay;
-
-	/*
-	 * Only care the raising edge and AP in S0/S3. The single raising edge
-	 * of AP power-on during S5S3 is ignored.
-	 */
-	if (gpio_get_level(GPIO_AP_RST_L) &&
-	    chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_SUSPEND)) {
-		ap_rst_transitions++;
-		if (ap_rst_transitions >= EXPECTED_AP_RST_TRANSITIONS) {
-			/*
-			 * Reach the expected transition count. AP is booting
-			 * up. Notify HOOK_CHIPSET_RESET immediately.
-			 */
-			delay = 0;
-		} else {
-			/*
-			 * Should have more transitions of the AP_RST_L signal.
-			 * In case the AP_RST_L signal is not toggled, still
-			 * notify HOOK_CHIPSET_RESET.
-			 */
-			delay = AP_RST_TRANSITION_TIMEOUT;
-		}
-		hook_call_deferred(&notify_chipset_reset_data, delay);
-	}
-#endif
-	power_signal_interrupt(signal);
-}
-
-/* Issue a request to initiate a reset sequence */
-static void request_cold_reset(void)
-{
-	power_request = POWER_REQ_RESET;
-	task_wake(TASK_ID_CHIPSET);
-}
-
-void chipset_warm_reset_interrupt(enum gpio_signal signal)
-{
-	/*
-	 * The warm_reset signal is pulled-up by a rail from PMIC. If the
-	 * warm_reset drops, it means:
-	 *  * Servo or Cr50 holds the signal, or
-	 *  * its pull-up rail POWER_GOOD drops.
-	 */
-	if (!gpio_get_level(GPIO_WARM_RESET_L)) {
-		if (gpio_get_level(GPIO_POWER_GOOD)) {
-			/*
-			 * Servo or Cr50 holds the WARM_RESET_L signal.
-			 *
-			 * Overdrive AP_RST_L to hold AP. Overdrive PS_HOLD to
-			 * emulate AP being up to trick the PMIC into thinking
-			 * there’s nothing weird going on.
-			 */
-			ap_rst_overdriven = 1;
-			gpio_set_flags(GPIO_PS_HOLD, GPIO_INT_BOTH |
-				       GPIO_SEL_1P8V | GPIO_OUT_HIGH);
-			gpio_set_flags(GPIO_AP_RST_L, GPIO_INT_BOTH |
-				       GPIO_SEL_1P8V | GPIO_OUT_LOW);
-		}
-		/* Ignore the else clause, the pull-up rail drops. */
-	} else {
-		if (ap_rst_overdriven) {
-			/*
-			 * Servo or Cr50 releases the WARM_RESET_L signal.
-			 *
-			 * Cold reset the PMIC, doing S0->S5->S0 transition,
-			 * by issuing a request to initiate a reset sequence,
-			 * to recover the system. The transition to S5 makes
-			 * POWER_GOOD drop that triggers an interrupt to
-			 * high-Z both AP_RST_L and PS_HOLD.
-			 */
-			CPRINTS("Long warm reset ended, "
-				"cold resetting to restore confidence.");
-			request_cold_reset();
-		}
-		/* If not overdriven, just a normal power-up, do nothing. */
-	}
-	power_signal_interrupt(signal);
-}
-
-void chipset_power_good_interrupt(enum gpio_signal signal)
-{
-	if (!gpio_get_level(GPIO_POWER_GOOD) && ap_rst_overdriven) {
-		/*
-		 * POWER_GOOD is the pull-up rail of WARM_RESET_L.
-		 * When POWER_GOOD drops, high-Z both AP_RST_L and PS_HOLD
-		 * to restore their states.
-		 */
-		gpio_set_flags(GPIO_AP_RST_L, GPIO_INT_BOTH |
-			       GPIO_SEL_1P8V);
-		gpio_set_flags(GPIO_PS_HOLD, GPIO_INT_BOTH |
-			       GPIO_SEL_1P8V);
-		ap_rst_overdriven = 0;
-	}
-	power_signal_interrupt(signal);
-}
-
-static void sc7180_lid_event(void)
-{
-	/* Power task only cares about lid-open events */
-	if (!lid_is_open())
-		return;
-
-	lid_opened = 1;
-	task_wake(TASK_ID_CHIPSET);
-}
-DECLARE_HOOK(HOOK_LID_CHANGE, sc7180_lid_event, HOOK_PRIO_DEFAULT);
-
-static void sc7180_powerbtn_changed(void)
-{
-	task_wake(TASK_ID_CHIPSET);
-}
-DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, sc7180_powerbtn_changed,
-	     HOOK_PRIO_DEFAULT);
-
-/**
- * Wait the switchcap GPIO0 PVC_PG signal asserted.
- *
- * When the output voltage is over the threshold PVC_PG_ADJ,
- * the PVC_PG is asserted.
- *
- * PVG_PG_ADJ is configured to 3.0V.
- * GPIO0 is configured as PVC_PG.
- *
- * @param enable	1 to wait the PMIC/AP on.
- *			0 to wait the PMIC/AP off.
- *
- * @return EC_SUCCESS or error
- */
-static int wait_switchcap_power_good(int enable)
-{
-	timestamp_t poll_deadline;
-
-	poll_deadline = get_time();
-	poll_deadline.val += SWITCHCAP_PG_CHECK_TIMEOUT;
-	while (enable != board_is_switchcap_power_good() &&
-	       get_time().val < poll_deadline.val) {
-		usleep(SWITCHCAP_PG_CHECK_WAIT);
-	}
-
-	/*
-	 * Check the timeout case. Just show a message. More check later
-	 * will switch the power state.
-	 */
-	if (enable != board_is_switchcap_power_good()) {
-		if (enable)
-			CPRINTS("SWITCHCAP NO POWER GOOD!");
-		else
-			CPRINTS("SWITCHCAP STILL POWER GOOD!");
-		return EC_ERROR_UNKNOWN;
-	}
-	return EC_SUCCESS;
-}
-
-/**
- * Get the state of the system power signals.
- *
- * @return 1 if the system is powered, 0 if not
- */
-static int is_system_powered(void)
-{
-	return board_is_switchcap_enabled();
-}
-
-/**
- * Get the PMIC/AP power signal.
- *
- * We treat the PMIC chips and the AP as a whole here. Don't deal with
- * the individual chip.
- *
- * @return 1 if the PMIC/AP is powered, 0 if not
- */
-static int is_pmic_pwron(void)
-{
-	/* Use POWER_GOOD to indicate PMIC/AP is on/off */
-	return gpio_get_level(GPIO_POWER_GOOD);
-}
-
-/**
- * Wait the PMIC/AP power-on state.
- *
- * @param enable	1 to wait the PMIC/AP on.
- *			0 to wait the PMIC/AP off.
- * @param timeout	Number of microsecond of timeout.
- *
- * @return EC_SUCCESS or error
- */
-static int wait_pmic_pwron(int enable, unsigned int timeout)
-{
-	timestamp_t poll_deadline;
-
-	/* Check the AP power status */
-	if (enable == is_pmic_pwron())
-		return EC_SUCCESS;
-
-	poll_deadline = get_time();
-	poll_deadline.val += timeout;
-	while (enable != is_pmic_pwron() &&
-	       get_time().val < poll_deadline.val) {
-		usleep(PMIC_POWER_AP_WAIT);
-	}
-
-	/* Check the timeout case */
-	if (enable != is_pmic_pwron()) {
-		if (enable)
-			CPRINTS("AP POWER NOT READY!");
-		else
-			CPRINTS("AP POWER STILL UP!");
-
-		return EC_ERROR_UNKNOWN;
-	}
-	return EC_SUCCESS;
-}
-
-/**
- * Set the state of the system power signals but without any check.
- *
- * The system power signals are the enable pins of SwitchCap.
- * They control the power of the set of PMIC chips and the AP.
- *
- * @param enable	1 to enable or 0 to disable
- */
-static void set_system_power_no_check(int enable)
-{
-	board_set_switchcap_power(enable);
-}
-
-/**
- * Set the state of the system power signals.
- *
- * The system power signals are the enable pins of SwitchCap.
- * They control the power of the set of PMIC chips and the AP.
- *
- * @param enable	1 to enable or 0 to disable
- *
- * @return EC_SUCCESS or error
- */
-static int set_system_power(int enable)
-{
-	int ret;
-
-	CPRINTS("%s(%d)", __func__, enable);
-	set_system_power_no_check(enable);
-
-	ret = wait_switchcap_power_good(enable);
-
-	if (!enable) {
-		/* Ensure POWER_GOOD drop to low if it is a forced shutdown */
-		ret |= wait_pmic_pwron(0, FORCE_OFF_RESPONSE_TIMEOUT);
-	}
-	usleep(SYSTEM_POWER_ON_DELAY);
-
-	return ret;
-}
-
-/**
- * Set the PMIC/AP power-on state.
- *
- * It triggers the PMIC/AP power-on and power-off sequence.
- *
- * @param enable	1 to power the PMIC/AP on.
- *			0 to power the PMIC/AP off.
- *
- * @return EC_SUCCESS or error
- */
-static int set_pmic_pwron(int enable)
-{
-	int ret;
-
-	CPRINTS("%s(%d)", __func__, enable);
-
-	/* Check the PMIC/AP power state */
-	if (enable == is_pmic_pwron())
-		return EC_SUCCESS;
-
-	if (!gpio_get_level(GPIO_PMIC_KPD_PWR_ODL)) {
-		CPRINTS("PMIC_KPD_PWR_ODL not pulled up by PMIC; cancel pwron");
-		return EC_ERROR_UNKNOWN;
-	}
-
-	/*
-	 * Power-on sequence:
-	 * 1. Hold down PMIC_KPD_PWR_ODL, which is a power-on trigger
-	 * 2. PMIC supplies power to POWER_GOOD
-	 * 3. Release PMIC_KPD_PWR_ODL
-	 *
-	 * Power-off sequence:
-	 * 1. Hold down PMIC_KPD_PWR_ODL and PMIC_RESIN_L, which is a power-off
-	 *    trigger (requiring reprogramming PMIC registers to make
-	 *    PMIC_KPD_PWR_ODL + PMIC_RESIN_L as a shutdown trigger)
-	 * 2. PMIC stops supplying power to POWER_GOOD (requiring
-	 *    reprogramming PMIC to set the stage-1 and stage-2 reset timers to
-	 *    0 such that the pull down happens just after the deboucing time
-	 *    of the trigger, like 2ms)
-	 * 3. Release PMIC_KPD_PWR_ODL and PMIC_RESIN_L
-	 *
-	 * If the above PMIC registers not programmed or programmed wrong, it
-	 * falls back to the next functions, which cuts off the system power.
-	 */
-
-	gpio_set_level(GPIO_PMIC_KPD_PWR_ODL, 0);
-	if (!enable)
-		gpio_set_level(GPIO_PMIC_RESIN_L, 0);
-	ret = wait_pmic_pwron(enable, PMIC_POWER_AP_RESPONSE_TIMEOUT);
-	gpio_set_level(GPIO_PMIC_KPD_PWR_ODL, 1);
-	if (!enable)
-		gpio_set_level(GPIO_PMIC_RESIN_L, 1);
-
-	return ret;
-}
-
-enum power_state power_chipset_init(void)
-{
-	int init_power_state;
-	uint32_t reset_flags = system_get_reset_flags();
-
-	/* Enable interrupts */
-	gpio_enable_interrupt(GPIO_WARM_RESET_L);
-	gpio_enable_interrupt(GPIO_POWER_GOOD);
-
-	/*
-	 * Force the AP shutdown unless we are doing SYSJUMP. Otherwise,
-	 * the AP could stay in strange state.
-	 */
-	if (!(reset_flags & EC_RESET_FLAG_SYSJUMP)) {
-		CPRINTS("not sysjump; forcing system shutdown");
-		set_system_power_no_check(0);
-		init_power_state = POWER_G3;
-	} else {
-		/* In the SYSJUMP case, we check if the AP is on */
-		if (power_get_signals() & IN_POWER_GOOD) {
-			CPRINTS("SOC ON");
-			init_power_state = POWER_S0;
-			/* Disable idle task deep sleep when in S0 */
-			disable_sleep(SLEEP_MASK_AP_RUN);
-		} else {
-			CPRINTS("SOC OFF");
-			init_power_state = POWER_G3;
-		}
-	}
-
-	/* Leave power off only if requested by reset flags */
-	if (!(reset_flags & EC_RESET_FLAG_AP_OFF) &&
-	    !(reset_flags & EC_RESET_FLAG_SYSJUMP)) {
-		CPRINTS("auto_power_on set due to reset_flag 0x%x",
-			system_get_reset_flags());
-		auto_power_on = 1;
-	}
-
-	if (battery_is_present() == BP_YES) {
-		/*
-		 * (crosbug.com/p/28289): Wait battery stable.
-		 * Some batteries use clock stretching feature, which requires
-		 * more time to be stable.
-		 */
-		battery_wait_for_stable();
-	}
-
-	return init_power_state;
-}
-
-/*****************************************************************************/
-
-/**
- * Power off the AP
- */
-static void power_off(void)
-{
-	/* Check PMIC POWER_GOOD */
-	if (is_pmic_pwron()) {
-		/* Do a graceful way to shutdown PMIC/AP first */
-		set_pmic_pwron(0);
-		usleep(PMIC_POWER_OFF_DELAY);
-
-		/*
-		 * Disable signal interrupts, as they are floating when
-		 * switchcap off.
-		 */
-		power_signal_disable_interrupt(GPIO_AP_RST_L);
-		power_signal_disable_interrupt(GPIO_PMIC_FAULT_L);
-	}
-
-	/* Check the switchcap status */
-	if (is_system_powered()) {
-		/* Force to switch off all rails */
-		set_system_power(0);
-	}
-
-	/* Turn off the load switch */
-	gpio_set_level(GPIO_QSIP_ON, 0);
-
-	/* Turn off the 3.3V and 5V rails. */
-	gpio_set_level(GPIO_EN_PP3300_A, 0);
-#ifdef CONFIG_POWER_PP5000_CONTROL
-	power_5v_enable(task_get_current(), 0);
-#else /* !defined(CONFIG_POWER_PP5000_CONTROL) */
-	gpio_set_level(GPIO_EN_PP5000, 0);
-#endif /* defined(CONFIG_POWER_PP5000_CONTROL) */
-
-	lid_opened = 0;
-}
-
-/**
- * Check if the power is enough to boot the AP.
- */
-static int power_is_enough(void)
-{
-	timestamp_t poll_deadline;
-
-	/* If powered by adapter only, wait a while for PD negoiation. */
-	poll_deadline = get_time();
-	poll_deadline.val += CAN_BOOT_AP_CHECK_TIMEOUT;
-
-	/*
-	 * Wait for PD negotiation. If a system with drained battery, don't
-	 * waste the time and exit the loop.
-	 */
-	while (!system_can_boot_ap() && !charge_want_shutdown() &&
-		get_time().val < poll_deadline.val) {
-		usleep(CAN_BOOT_AP_CHECK_WAIT);
-	}
-
-	return system_can_boot_ap() && !charge_want_shutdown();
-}
-
-/**
- * Power on the AP
- *
- * @return EC_SUCCESS or error
- */
-static int power_on(void)
-{
-	int ret;
-
-	/* Enable the 3.3V and 5V rail. */
-	gpio_set_level(GPIO_EN_PP3300_A, 1);
-#ifdef CONFIG_POWER_PP5000_CONTROL
-	power_5v_enable(task_get_current(), 1);
-#else /* !defined(CONFIG_POWER_PP5000_CONTROL) */
-	gpio_set_level(GPIO_EN_PP5000, 1);
-#endif /* defined(CONFIG_POWER_PP5000_CONTROL) */
-
-	/*
-	 * Enable the load switch. The load switch is redundant.
-	 * But leaving it off consumes power.
-	 */
-	gpio_set_level(GPIO_QSIP_ON, 1);
-
-	ret = set_system_power(1);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	/* Enable signal interrupts */
-	power_signal_enable_interrupt(GPIO_AP_RST_L);
-	power_signal_enable_interrupt(GPIO_PMIC_FAULT_L);
-
-	ret = set_pmic_pwron(1);
-	if (ret != EC_SUCCESS) {
-		CPRINTS("POWER_GOOD not seen in time");
-		return ret;
-	}
-
-	CPRINTS("POWER_GOOD seen");
-	return EC_SUCCESS;
-}
-
-/**
- * Check if there has been a power-on event
- *
- * This checks all power-on event signals and returns non-zero if any have been
- * triggered (with debounce taken into account).
- *
- * @return non-zero if there has been a power-on event, 0 if not.
- */
-static uint8_t check_for_power_on_event(void)
-{
-	if (power_request == POWER_REQ_ON) {
-		power_request = POWER_REQ_NONE;
-		return POWER_ON_BY_POWER_REQ_ON;
-	} else if (power_request == POWER_REQ_RESET) {
-		power_request = POWER_REQ_NONE;
-		return POWER_ON_BY_POWER_REQ_RESET;
-	}
-	/* Clear invalid request */
-	power_request = POWER_REQ_NONE;
-
-	/* power on requested at EC startup for recovery */
-	if (auto_power_on) {
-		auto_power_on = 0;
-		return POWER_ON_BY_AUTO_POWER_ON;
-	}
-
-	/* Check lid open */
-	if (lid_opened) {
-		lid_opened = 0;
-		return POWER_ON_BY_LID_OPEN;
-	}
-
-	/* check for power button press */
-	if (power_button_is_pressed())
-		return POWER_ON_BY_POWER_BUTTON_PRESSED;
-
-	return POWER_OFF_CANCEL;
-}
-
-/**
- * Check for some event triggering the shutdown.
- *
- * It can be either a long power button press or a shutdown triggered from the
- * AP and detected by reading POWER_GOOD.
- *
- * @return non-zero if a shutdown should happen, 0 if not
- */
-static uint8_t check_for_power_off_event(void)
-{
-	timestamp_t now;
-	int pressed = 0;
-
-	if (power_request == POWER_REQ_OFF) {
-		power_request = POWER_REQ_NONE;
-		return POWER_OFF_BY_POWER_REQ_OFF;
-	} else if (power_request == POWER_REQ_RESET) {
-		/*
-		 * The power_request flag will be cleared later
-		 * in check_for_power_on_event() in S5.
-		 */
-		return POWER_OFF_BY_POWER_REQ_RESET;
-	}
-	/* Clear invalid request */
-	power_request = POWER_REQ_NONE;
-
-	/*
-	 * Check for power button press.
-	 */
-	if (power_button_is_pressed())
-		pressed = POWER_OFF_BY_POWER_BUTTON_PRESSED;
-
-	now = get_time();
-	if (pressed) {
-		if (!power_button_was_pressed) {
-			power_off_deadline.val = now.val + DELAY_FORCE_SHUTDOWN;
-			CPRINTS("power waiting for long press %u",
-				power_off_deadline.le.lo);
-			/* Ensure we will wake up to check the power key */
-			timer_arm(power_off_deadline, TASK_ID_CHIPSET);
-		} else if (timestamp_expired(power_off_deadline, &now)) {
-			power_off_deadline.val = 0;
-			CPRINTS("power off after long press now=%u, %u",
-				now.le.lo, power_off_deadline.le.lo);
-			return POWER_OFF_BY_LONG_PRESS;
-		}
-	} else if (power_button_was_pressed) {
-		CPRINTS("power off cancel");
-		timer_cancel(TASK_ID_CHIPSET);
-	}
-
-	power_button_was_pressed = pressed;
-
-	/* POWER_GOOD released by AP : shutdown immediately */
-	if (!power_has_signals(IN_POWER_GOOD)) {
-		CPRINTS("POWER_GOOD is lost");
-		return POWER_OFF_BY_POWER_GOOD_LOST;
-	}
-
-	return POWER_OFF_CANCEL;
-}
-
-/**
- * Cancel the power button timer.
- *
- * The timer was previously created in the check_for_power_off_event(),
- * which waited for the power button long press. Should cancel the timer
- * during the power state transition; otherwise, EC will crash.
- */
-static inline void cancel_power_button_timer(void)
-{
-	if (power_button_was_pressed)
-		timer_cancel(TASK_ID_CHIPSET);
-}
-
-/*****************************************************************************/
-/* Chipset interface */
-
-void chipset_force_shutdown(enum chipset_shutdown_reason reason)
-{
-	CPRINTS("%s(%d)", __func__, reason);
-	report_ap_reset(reason);
-
-	/* Issue a request to initiate a power-off sequence */
-	power_request = POWER_REQ_OFF;
-	task_wake(TASK_ID_CHIPSET);
-}
-
-void chipset_reset(enum chipset_reset_reason reason)
-{
-	int rv;
-
-	CPRINTS("%s(%d)", __func__, reason);
-	report_ap_reset(reason);
-
-	/*
-	 * Warm reset sequence:
-	 * 1. Issue a low pulse to PMIC_RESIN_L, which triggers PMIC
-	 *    to do a warm reset (requiring reprogramming PMIC registers
-	 *    to make PMIC_RESIN_L as a warm reset trigger).
-	 * 2. PMIC then issues a low pulse to AP_RST_L to reset AP.
-	 *    EC monitors the signal to see any low pulse.
-	 *    2.1. If a low pulse found, done.
-	 *    2.2. If a low pulse not found (the above PMIC registers
-	 *         not programmed or programmed wrong), issue a request
-	 *         to initiate a cold reset power sequence.
-	 */
-
-	gpio_set_level(GPIO_PMIC_RESIN_L, 0);
-	usleep(PMIC_RESIN_PULSE_LENGTH);
-	gpio_set_level(GPIO_PMIC_RESIN_L, 1);
-
-	rv = power_wait_signals_timeout(IN_AP_RST_ASSERTED,
-					PMIC_POWER_AP_RESPONSE_TIMEOUT);
-	/* Exception case: PMIC not work as expected, request a cold reset */
-	if (rv != EC_SUCCESS) {
-		CPRINTS("AP refuses to warm reset. Cold resetting.");
-		request_cold_reset();
-	}
-}
-
-/*
- * Flag to fake the suspend signal to 1 or 0, or -1 means not fake it.
- *
- * TODO(waihong): Remove this flag and debug command when the AP_SUSPEND
- * signal is working.
- */
-static int fake_suspend = -1;
-
-static int command_fake_suspend(int argc, char **argv)
-{
-	int v;
-
-	if (argc < 2) {
-		ccprintf("fake_suspend: %s\n",
-			 fake_suspend == -1 ? "reset"
-					    : (fake_suspend ? "on" : "off"));
-		return EC_SUCCESS;
-	}
-
-	if (!strcasecmp(argv[1], "reset"))
-		fake_suspend = -1;
-	else if (parse_bool(argv[1], &v))
-		fake_suspend = v;
-	else
-		return EC_ERROR_PARAM1;
-
-	task_wake(TASK_ID_CHIPSET);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(fakesuspend, command_fake_suspend,
-			"on/off/reset",
-			"Fake the AP_SUSPEND signal");
-
-/* Get system sleep state through GPIOs */
-static inline int chipset_get_sleep_signal(void)
-{
-	if (fake_suspend == -1)
-		return (power_get_signals() & IN_SUSPEND) == IN_SUSPEND;
-	else
-		return fake_suspend;
-}
-
-static void suspend_hang_detected(void)
-{
-	CPRINTS("Warning: Detected sleep hang! Waking host up!");
-	host_set_single_event(EC_HOST_EVENT_HANG_DETECT);
-}
-
-static void power_reset_host_sleep_state(void)
-{
-	power_set_host_sleep_state(HOST_SLEEP_EVENT_DEFAULT_RESET);
-	sleep_reset_tracking();
-	power_chipset_handle_host_sleep_event(HOST_SLEEP_EVENT_DEFAULT_RESET,
-					      NULL);
-}
-
-static void handle_chipset_reset(void)
-{
-	if (chipset_in_state(CHIPSET_STATE_SUSPEND)) {
-		CPRINTS("Chipset reset: exit s3");
-		power_reset_host_sleep_state();
-		task_wake(TASK_ID_CHIPSET);
-	}
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESET, handle_chipset_reset, HOOK_PRIO_FIRST);
-
-__override void power_chipset_handle_host_sleep_event(
-		enum host_sleep_event state,
-		struct host_sleep_event_context *ctx)
-{
-	CPRINTS("Handle sleep: %d", state);
-
-	if (state == HOST_SLEEP_EVENT_S3_SUSPEND) {
-		/*
-		 * Indicate to power state machine that a new host event for
-		 * S3 suspend has been received and so chipset suspend
-		 * notification needs to be sent to listeners.
-		 */
-		sleep_set_notify(SLEEP_NOTIFY_SUSPEND);
-		sleep_start_suspend(ctx, suspend_hang_detected);
-		power_signal_enable_interrupt(GPIO_AP_SUSPEND);
-
-	} else if (state == HOST_SLEEP_EVENT_S3_RESUME) {
-		/*
-		 * Wake up chipset task and indicate to power state machine that
-		 * listeners need to be notified of chipset resume.
-		 */
-		sleep_set_notify(SLEEP_NOTIFY_RESUME);
-		task_wake(TASK_ID_CHIPSET);
-		power_signal_disable_interrupt(GPIO_AP_SUSPEND);
-		sleep_complete_resume(ctx);
-
-	} else if (state == HOST_SLEEP_EVENT_DEFAULT_RESET) {
-		power_signal_disable_interrupt(GPIO_AP_SUSPEND);
-	}
-}
-
-/**
- * Power handler for steady states
- *
- * @param state		Current power state
- * @return Updated power state
- */
-enum power_state power_handle_state(enum power_state state)
-{
-	static uint8_t boot_from_off, shutdown_from_on;
-
-	switch (state) {
-	case POWER_G3:
-		boot_from_off = check_for_power_on_event();
-		if (boot_from_off)
-			return POWER_G3S5;
-		break;
-
-	case POWER_G3S5:
-		return POWER_S5;
-
-	case POWER_S5:
-		if (!boot_from_off)
-			boot_from_off = check_for_power_on_event();
-
-		if (boot_from_off) {
-			CPRINTS("power on %d", boot_from_off);
-			return POWER_S5S3;
-		}
-		break;
-
-	case POWER_S5S3:
-		/*
-		 * Wait for power button release before actually boot AP.
-		 * It may be a long-hold power button with volume buttons
-		 * to trigger the recovery button. We don't want AP up
-		 * during the long-hold.
-		 */
-		power_button_wait_for_release(-1);
-
-		/* If no enough power, return back to S5. */
-		if (!power_is_enough())
-			return POWER_S5;
-
-		/* Initialize components to ready state before AP is up. */
-		hook_notify(HOOK_CHIPSET_PRE_INIT);
-
-		if (power_on() != EC_SUCCESS) {
-			power_off();
-			return POWER_S5;
-		}
-		CPRINTS("AP running ...");
-
-		/* Call hooks now that AP is running */
-		hook_notify(HOOK_CHIPSET_STARTUP);
-
-		/*
-		 * Clearing the sleep failure detection tracking on the path
-		 * to S0 to handle any reset conditions.
-		 */
-		power_reset_host_sleep_state();
-		return POWER_S3;
-
-	case POWER_S3:
-		if (!shutdown_from_on)
-			shutdown_from_on = check_for_power_off_event();
-
-		if (shutdown_from_on) {
-			CPRINTS("power off %d", shutdown_from_on);
-			return POWER_S3S5;
-		}
-
-		/*
-		 * AP has woken up and it deasserts the suspend signal;
-		 * go to S0.
-		 *
-		 * In S0, it will wait for a host event and then trigger the
-		 * RESUME hook.
-		 */
-		if (!chipset_get_sleep_signal())
-			return POWER_S3S0;
-		break;
-
-	case POWER_S3S0:
-		cancel_power_button_timer();
-
-#ifdef CONFIG_CHIPSET_RESUME_INIT_HOOK
-		/*
-		 * Notify the RESUME_INIT hooks, i.e. enabling SPI driver
-		 * to receive host commands/events.
-		 *
-		 * If boot from an off state, notify the RESUME hooks too;
-		 * otherwise (resume from S3), the normal RESUME hooks will
-		 * be notified later, after receive a host resume event.
-		 */
-		hook_notify(HOOK_CHIPSET_RESUME_INIT);
-		if (boot_from_off)
-			hook_notify(HOOK_CHIPSET_RESUME);
-#else
-		hook_notify(HOOK_CHIPSET_RESUME);
-#endif
-		sleep_resume_transition();
-
-		boot_from_off = 0;
-		disable_sleep(SLEEP_MASK_AP_RUN);
-		return POWER_S0;
-
-	case POWER_S0:
-		shutdown_from_on = check_for_power_off_event();
-		if (shutdown_from_on) {
-			return POWER_S0S3;
-		} else if (power_get_host_sleep_state()
-					== HOST_SLEEP_EVENT_S3_SUSPEND &&
-				chipset_get_sleep_signal()) {
-			return POWER_S0S3;
-		}
-		/* When receive the host event, trigger the RESUME hook. */
-		sleep_notify_transition(SLEEP_NOTIFY_RESUME,
-					HOOK_CHIPSET_RESUME);
-		break;
-
-	case POWER_S0S3:
-		cancel_power_button_timer();
-
-#ifdef CONFIG_CHIPSET_RESUME_INIT_HOOK
-		/*
-		 * Pair with the HOOK_CHIPSET_RESUME_INIT, i.e. disabling SPI
-		 * driver, by notifying the SUSPEND_COMPLETE hook. The normal
-		 * SUSPEND hook will be notified afterward.
-		 */
-		hook_notify(HOOK_CHIPSET_SUSPEND_COMPLETE);
-#else
-		hook_notify(HOOK_CHIPSET_SUSPEND);
-#endif
-		/*
-		 * Call SUSPEND hooks only if we haven't notified listeners of
-		 * S3 suspend.
-		 */
-		sleep_notify_transition(SLEEP_NOTIFY_SUSPEND,
-					HOOK_CHIPSET_SUSPEND);
-		sleep_suspend_transition();
-
-		enable_sleep(SLEEP_MASK_AP_RUN);
-		return POWER_S3;
-
-	case POWER_S3S5:
-		cancel_power_button_timer();
-
-		/* Call hooks before we drop power rails */
-		hook_notify(HOOK_CHIPSET_SHUTDOWN);
-
-		power_off();
-		CPRINTS("power shutdown complete");
-
-		/* Call hooks after we drop power rails */
-		hook_notify(HOOK_CHIPSET_SHUTDOWN_COMPLETE);
-
-		shutdown_from_on = 0;
-
-		/*
-		 * Wait forever for the release of the power button; otherwise,
-		 * this power button press will then trigger a power-on in S5.
-		 */
-		power_button_wait_for_release(-1);
-		power_button_was_pressed = 0;
-		return POWER_S5;
-
-	case POWER_S5G3:
-		return POWER_G3;
-	}
-
-	return state;
-}
-
-/*****************************************************************************/
-/* Console debug command */
-
-static const char *power_req_name[POWER_REQ_COUNT] = {
-	"none",
-	"off",
-	"on",
-};
-
-/* Power states that we can report */
-enum power_state_t {
-	PSTATE_UNKNOWN,
-	PSTATE_OFF,
-	PSTATE_ON,
-	PSTATE_COUNT,
-};
-
-static const char * const state_name[] = {
-	"unknown",
-	"off",
-	"on",
-};
-
-static int command_power(int argc, char **argv)
-{
-	int v;
-
-	if (argc < 2) {
-		enum power_state_t state;
-
-		state = PSTATE_UNKNOWN;
-		if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-			state = PSTATE_OFF;
-		if (chipset_in_state(CHIPSET_STATE_ON))
-			state = PSTATE_ON;
-		ccprintf("%s\n", state_name[state]);
-
-		return EC_SUCCESS;
-	}
-
-	if (!parse_bool(argv[1], &v))
-		return EC_ERROR_PARAM1;
-
-	power_request = v ? POWER_REQ_ON : POWER_REQ_OFF;
-	ccprintf("Requesting power %s\n", power_req_name[power_request]);
-	task_wake(TASK_ID_CHIPSET);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(power, command_power,
-			"on/off",
-			"Turn AP power on/off");
diff --git a/power/sdm845.c b/power/sdm845.c
index a8cc70b8ea..aeed0d13d2 100644
--- a/power/sdm845.c
+++ b/power/sdm845.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,6 +22,7 @@
  *  - If POWER_GOOD is dropped by the AP, then we power the AP off
  */
 
+#include "builtin/assert.h"
 #include "charge_state.h"
 #include "chipset.h"
 #include "common.h"
@@ -34,15 +35,14 @@
 #include "task.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 /* Masks for power signals */
-#define IN_POWER_GOOD		POWER_SIGNAL_MASK(SDM845_POWER_GOOD)
-#define IN_AP_RST_ASSERTED	POWER_SIGNAL_MASK(SDM845_AP_RST_ASSERTED)
-
+#define IN_POWER_GOOD POWER_SIGNAL_MASK(SDM845_POWER_GOOD)
+#define IN_AP_RST_ASSERTED POWER_SIGNAL_MASK(SDM845_AP_RST_ASSERTED)
 
 /* Long power key press to force shutdown */
-#define DELAY_FORCE_SHUTDOWN		(8 * SECOND)
+#define DELAY_FORCE_SHUTDOWN (8 * SECOND)
 
 /*
  * If the power button is pressed to turn on, then held for this long, we
@@ -52,40 +52,40 @@
  *    into the inner loop, waiting for next event to occur (power button
  *    press or POWER_GOOD == 0).
  */
-#define DELAY_SHUTDOWN_ON_POWER_HOLD	(8 * SECOND)
+#define DELAY_SHUTDOWN_ON_POWER_HOLD (8 * SECOND)
 
 /*
  * After trigger PMIC power sequence, how long it triggers AP to turn on
  * or off. Observed that the worst case is ~150ms. Pick a safe vale.
  */
-#define PMIC_POWER_AP_RESPONSE_TIMEOUT	(350 * MSEC)
+#define PMIC_POWER_AP_RESPONSE_TIMEOUT (350 * MSEC)
 
 /*
  * After force off the switch cap, how long the PMIC/AP totally off.
  * Observed that the worst case is 2s. Pick a safe vale.
  */
-#define FORCE_OFF_RESPONSE_TIMEOUT	(4 * SECOND)
+#define FORCE_OFF_RESPONSE_TIMEOUT (4 * SECOND)
 
 /* Wait for polling the AP on signal */
-#define PMIC_POWER_AP_WAIT		(1 * MSEC)
+#define PMIC_POWER_AP_WAIT (1 * MSEC)
 
 /* The length of an issued low pulse to the PMIC_RESIN_L signal */
-#define PMIC_RESIN_PULSE_LENGTH		(20 * MSEC)
+#define PMIC_RESIN_PULSE_LENGTH (20 * MSEC)
 
 /* The timeout of the check if the system can boot AP */
-#define CAN_BOOT_AP_CHECK_TIMEOUT	(500 * MSEC)
+#define CAN_BOOT_AP_CHECK_TIMEOUT (500 * MSEC)
 
 /* Wait for polling if the system can boot AP */
-#define CAN_BOOT_AP_CHECK_WAIT		(100 * MSEC)
+#define CAN_BOOT_AP_CHECK_WAIT (100 * MSEC)
 
 /* The timeout of the check if the switchcap outputs good voltage */
-#define SWITCHCAP_PG_CHECK_TIMEOUT	(50 * MSEC)
+#define SWITCHCAP_PG_CHECK_TIMEOUT (50 * MSEC)
 
 /* Wait for polling if the switchcap outputs good voltage */
-#define SWITCHCAP_PG_CHECK_WAIT		(5 * MSEC)
+#define SWITCHCAP_PG_CHECK_WAIT (5 * MSEC)
 
 /* Delay between power-on the system and power-on the PMIC */
-#define SYSTEM_POWER_ON_DELAY		(10 * MSEC)
+#define SYSTEM_POWER_ON_DELAY (10 * MSEC)
 
 /* TODO(crosbug.com/p/25047): move to HOOK_POWER_BUTTON_CHANGE */
 /* 1 if the power button was pressed last time we checked */
@@ -182,9 +182,11 @@ void chipset_warm_reset_interrupt(enum gpio_signal signal)
 			 */
 			ap_rst_overdriven = 1;
 			gpio_set_flags(GPIO_PS_HOLD, GPIO_INT_BOTH |
-				       GPIO_SEL_1P8V | GPIO_OUT_HIGH);
+							     GPIO_SEL_1P8V |
+							     GPIO_OUT_HIGH);
 			gpio_set_flags(GPIO_AP_RST_L, GPIO_INT_BOTH |
-				       GPIO_SEL_1P8V | GPIO_OUT_LOW);
+							      GPIO_SEL_1P8V |
+							      GPIO_OUT_LOW);
 		} else {
 			/*
 			 * The pull-up rail POWER_GOOD drops.
@@ -192,10 +194,10 @@ void chipset_warm_reset_interrupt(enum gpio_signal signal)
 			 * High-Z both AP_RST_L and PS_HOLD to restore their
 			 * states.
 			 */
-			gpio_set_flags(GPIO_AP_RST_L, GPIO_INT_BOTH |
-				       GPIO_SEL_1P8V);
-			gpio_set_flags(GPIO_PS_HOLD, GPIO_INT_BOTH |
-				       GPIO_SEL_1P8V);
+			gpio_set_flags(GPIO_AP_RST_L,
+				       GPIO_INT_BOTH | GPIO_SEL_1P8V);
+			gpio_set_flags(GPIO_PS_HOLD,
+				       GPIO_INT_BOTH | GPIO_SEL_1P8V);
 			ap_rst_overdriven = 0;
 		}
 	} else {
@@ -268,7 +270,6 @@ static void wait_switchcap_power_good(int enable)
 		else
 			CPRINTS("SWITCHCAP STILL POWER GOOD!");
 	}
-
 }
 
 /**
@@ -500,7 +501,7 @@ static int power_is_enough(void)
 	 * waste the time and exit the loop.
 	 */
 	while (!system_can_boot_ap() && !charge_want_shutdown() &&
-		get_time().val < poll_deadline.val) {
+	       get_time().val < poll_deadline.val) {
 		usleep(CAN_BOOT_AP_CHECK_WAIT);
 	}
 
@@ -687,7 +688,7 @@ void chipset_force_shutdown(enum chipset_shutdown_reason reason)
 	task_wake(TASK_ID_CHIPSET);
 }
 
-void chipset_reset(enum chipset_reset_reason reason)
+void chipset_reset(enum chipset_shutdown_reason reason)
 {
 	int rv;
 
@@ -823,6 +824,11 @@ enum power_state power_handle_state(enum power_state state)
 
 	case POWER_S5G3:
 		return POWER_G3;
+
+	default:
+		CPRINTS("Unexpected power state %d", state);
+		ASSERT(0);
+		break;
 	}
 
 	return state;
@@ -845,13 +851,13 @@ enum power_state_t {
 	PSTATE_COUNT,
 };
 
-static const char * const state_name[] = {
+static const char *const state_name[] = {
 	"unknown",
 	"off",
 	"on",
 };
 
-static int command_power(int argc, char **argv)
+static int command_power(int argc, const char **argv)
 {
 	int v;
 
@@ -877,6 +883,4 @@ static int command_power(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(power, command_power,
-			"on/off",
-			"Turn AP power on/off");
+DECLARE_CONSOLE_COMMAND(power, command_power, "on/off", "Turn AP power on/off");
diff --git a/power/skylake.c b/power/skylake.c
index 829a0fa370..24adb56f86 100644
--- a/power/skylake.c
+++ b/power/skylake.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,17 +9,17 @@
 #include "console.h"
 #include "gpio.h"
 #include "hooks.h"
-#include "intel_x86.h"
 #include "lpc.h"
 #include "panic.h"
+#include "power/intel_x86.h"
 #include "power_button.h"
 #include "system.h"
 #include "timer.h"
 
 /* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
-static int forcing_shutdown;  /* Forced shutdown in progress? */
+static int forcing_shutdown; /* Forced shutdown in progress? */
 
 /* Power signals list. Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
@@ -31,12 +31,12 @@ const struct power_signal_info power_signal_list[] = {
 	},
 #endif
 	[X86_SLP_S3_DEASSERTED] = {
-		SLP_S3_SIGNAL_L,
+		(enum gpio_signal)SLP_S3_SIGNAL_L,
 		POWER_SIGNAL_ACTIVE_HIGH,
 		"SLP_S3_DEASSERTED",
 	},
 	[X86_SLP_S4_DEASSERTED] = {
-		SLP_S4_SIGNAL_L,
+		(enum gpio_signal)SLP_S4_SIGNAL_L,
 		POWER_SIGNAL_ACTIVE_HIGH,
 		"SLP_S4_DEASSERTED",
 	},
@@ -46,7 +46,7 @@ const struct power_signal_info power_signal_list[] = {
 		"SLP_SUS_DEASSERTED",
 	},
 	[X86_RSMRST_L_PWRGD] = {
-		GPIO_RSMRST_L_PGOOD,
+		GPIO_PG_EC_RSMRST_ODL,
 		POWER_SIGNAL_ACTIVE_HIGH,
 		"RSMRST_N_PWRGD",
 	},
@@ -58,7 +58,6 @@ const struct power_signal_info power_signal_list[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
-
 void chipset_force_shutdown(enum chipset_shutdown_reason reason)
 {
 	CPRINTS("%s()", __func__);
@@ -110,7 +109,7 @@ void chipset_handle_espi_reset_assert(void)
 	 * power button. If yes, release power button.
 	 */
 	if ((power_get_signals() & IN_PCH_SLP_SUS_DEASSERTED) &&
-		forcing_shutdown) {
+	    forcing_shutdown) {
 		power_button_pch_release();
 		forcing_shutdown = 0;
 	}
@@ -157,9 +156,8 @@ void chipset_handle_reboot(void)
 	 * Do not make PMIC re-sequence the power rails if the following reset
 	 * conditions are not met.
 	 */
-	if (!(flags &
-		(EC_RESET_FLAG_WATCHDOG | EC_RESET_FLAG_SOFT |
-		 EC_RESET_FLAG_HARD)))
+	if (!(flags & (EC_RESET_FLAG_WATCHDOG | EC_RESET_FLAG_SOFT |
+		       EC_RESET_FLAG_HARD)))
 		return;
 
 	/* Preserve AP off request. */
diff --git a/power/stoney.c b/power/stoney.c
deleted file mode 100644
index a889cc9102..0000000000
--- a/power/stoney.c
+++ /dev/null
@@ -1,300 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Stoney power sequencing module for Chrome EC */
-
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "system.h"
-#include "timer.h"
-#include "usb_charge.h"
-#include "util.h"
-#include "wireless.h"
-#include "registers.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
-
-#define IN_S5_PGOOD POWER_SIGNAL_MASK(X86_S5_PGOOD)
-
-static int forcing_shutdown; /* Forced shutdown in progress? */
-
-void chipset_force_shutdown(enum chipset_shutdown_reason reason)
-{
-	CPRINTS("%s()", __func__);
-
-	if (!chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
-		forcing_shutdown = 1;
-		power_button_pch_press();
-		report_ap_reset(reason);
-	}
-}
-
-static void chipset_force_g3(void)
-{
-	/* Disable system power ("*_A" rails) in G3. */
-	gpio_set_level(GPIO_EN_PWR_A, 0);
-}
-
-void chipset_reset(enum chipset_reset_reason reason)
-{
-	CPRINTS("%s: %d", __func__, reason);
-
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
-		CPRINTS("Can't reset: SOC is off");
-		return;
-	}
-
-	report_ap_reset(reason);
-	/*
-	 * Send a pulse to SYS_RST to trigger a warm reset.
-	 */
-	gpio_set_level(GPIO_SYS_RESET_L, 0);
-	usleep(32 * MSEC);
-	gpio_set_level(GPIO_SYS_RESET_L, 1);
-}
-
-void chipset_throttle_cpu(int throttle)
-{
-	CPRINTS("%s(%d)", __func__, throttle);
-	if (IS_ENABLED(CONFIG_CPU_PROCHOT_ACTIVE_LOW))
-		throttle = !throttle;
-
-	if (chipset_in_state(CHIPSET_STATE_ON))
-		gpio_set_level(GPIO_CPU_PROCHOT, throttle);
-}
-
-void chipset_handle_espi_reset_assert(void)
-{
-	/*
-	 * eSPI_Reset# pin being asserted without RSMRST# being asserted
-	 * means there is an unexpected power loss (global reset event).
-	 * In this case, check if the shutdown is forced by the EC (due
-	 * to battery, thermal, or console command). The forced shutdown
-	 * initiates a power button press that we need to release.
-	 *
-	 * NOTE: S5_PGOOD input is passed through to the RSMRST# output to
-	 * the AP.
-	 */
-	if ((power_get_signals() & IN_S5_PGOOD) && forcing_shutdown) {
-		power_button_pch_release();
-		forcing_shutdown = 0;
-	}
-}
-
-enum power_state power_chipset_init(void)
-{
-	CPRINTS("%s: power_signal=0x%x", __func__, power_get_signals());
-
-	/* Pause in S5 when shutting down. */
-	power_set_pause_in_s5(1);
-
-	if (!system_jumped_to_this_image())
-		return POWER_G3;
-	/*
-	 * We are here as RW. We need to handle the following cases:
-	 *
-	 * 1. Late sysjump by software sync. AP is in S0.
-	 * 2. Shutting down in recovery mode then sysjump by EFS2. AP is in S5
-	 *    and expected to sequence down.
-	 * 3. Rebooting from recovery mode then sysjump by EFS2. AP is in S5
-	 *    and expected to sequence up.
-	 * 4. RO jumps to RW from main() by EFS2. (a.k.a. power on reset, cold
-	 *    reset). AP is in G3.
-	 */
-	if (gpio_get_level(GPIO_S0_PGOOD)) {
-		/* case #1. Disable idle task deep sleep when in S0. */
-		disable_sleep(SLEEP_MASK_AP_RUN);
-		CPRINTS("already in S0");
-		return POWER_S0;
-	}
-	if (power_get_signals() & IN_S5_PGOOD) {
-		/* case #2 & #3 */
-		CPRINTS("already in S5");
-		return POWER_S5;
-	}
-	/* case #4 */
-	chipset_force_g3();
-	return POWER_G3;
-}
-
-static void handle_pass_through(enum gpio_signal pin_in,
-				enum gpio_signal pin_out)
-{
-	/*
-	 * Pass through asynchronously, as SOC may not react
-	 * immediately to power changes.
-	 */
-	int in_level = gpio_get_level(pin_in);
-	int out_level = gpio_get_level(pin_out);
-
-	/*
-	 * Only pass through high S0_PGOOD (S0 power) when S5_PGOOD (S5 power)
-	 * is also high (S0_PGOOD is pulled high in G3 when S5_PGOOD is low).
-	 */
-	if ((pin_in == GPIO_S0_PGOOD) && !gpio_get_level(GPIO_S5_PGOOD))
-		in_level = 0;
-
-	/* Nothing to do. */
-	if (in_level == out_level)
-		return;
-
-	/*
-	 * SOC requires a delay of 1ms with stable power before
-	 * asserting PWR_GOOD.
-	 */
-	if ((pin_in == GPIO_S0_PGOOD) && in_level)
-		msleep(1);
-
-	gpio_set_level(pin_out, in_level);
-
-	CPRINTS("Pass through %s: %d", gpio_get_name(pin_in), in_level);
-}
-
-enum power_state power_handle_state(enum power_state state)
-{
-	handle_pass_through(GPIO_S5_PGOOD, GPIO_PCH_RSMRST_L);
-
-	handle_pass_through(GPIO_S0_PGOOD, GPIO_PCH_SYS_PWROK);
-
-	if (state == POWER_S5 && forcing_shutdown) {
-		power_button_pch_release();
-		forcing_shutdown = 0;
-	}
-
-	switch (state) {
-	case POWER_G3:
-		break;
-
-	case POWER_G3S5:
-		/* Exit SOC G3 */
-		/* Enable system power ("*_A" rails) in S5. */
-		gpio_set_level(GPIO_EN_PWR_A, 1);
-
-		/*
-		 * Callback to do pre-initialization within the context of
-		 * chipset task.
-		 */
-		if (IS_ENABLED(CONFIG_CHIPSET_HAS_PRE_INIT_CALLBACK))
-			chipset_pre_init_callback();
-
-		if (power_wait_signals(IN_S5_PGOOD)) {
-			chipset_force_g3();
-			return POWER_G3;
-		}
-
-		CPRINTS("Exit SOC G3");
-
-		return POWER_S5;
-
-	case POWER_S5:
-		if (!power_has_signals(IN_S5_PGOOD)) {
-			/* Required rail went away */
-			return POWER_S5G3;
-		} else if (gpio_get_level(GPIO_PCH_SLP_S5_L) == 1) {
-			/* Power up to next state */
-			return POWER_S5S3;
-		}
-		break;
-
-	case POWER_S5S3:
-		if (!power_has_signals(IN_S5_PGOOD)) {
-			/* Required rail went away */
-			return POWER_S5G3;
-		}
-
-		/* Call hooks now that rails are up */
-		hook_notify(HOOK_CHIPSET_STARTUP);
-
-		return POWER_S3;
-
-	case POWER_S3:
-		if (!power_has_signals(IN_S5_PGOOD)) {
-			/* Required rail went away */
-			return POWER_S5G3;
-		} else if (gpio_get_level(GPIO_PCH_SLP_S3_L) == 1) {
-			/* Power up to next state */
-			return POWER_S3S0;
-		} else if (gpio_get_level(GPIO_PCH_SLP_S5_L) == 0) {
-			/* Power down to next state */
-			return POWER_S3S5;
-		}
-		break;
-
-	case POWER_S3S0:
-		if (!power_has_signals(IN_S5_PGOOD)) {
-			/* Required rail went away */
-			return POWER_S5G3;
-		}
-
-		/* Enable wireless */
-		wireless_set_state(WIRELESS_ON);
-
-		/* Call hooks now that rails are up */
-		hook_notify(HOOK_CHIPSET_RESUME);
-
-		/*
-		 * Disable idle task deep sleep. This means that the low
-		 * power idle task will not go into deep sleep while in S0.
-		 */
-		disable_sleep(SLEEP_MASK_AP_RUN);
-
-		return POWER_S0;
-
-	case POWER_S0:
-		if (!power_has_signals(IN_S5_PGOOD)) {
-			/* Required rail went away */
-			return POWER_S5G3;
-		} else if (gpio_get_level(GPIO_PCH_SLP_S3_L) == 0) {
-			/* Power down to next state */
-			return POWER_S0S3;
-		}
-		break;
-
-	case POWER_S0S3:
-		/* Call hooks before we remove power rails */
-		hook_notify(HOOK_CHIPSET_SUSPEND);
-
-		/* Suspend wireless */
-		wireless_set_state(WIRELESS_SUSPEND);
-
-		/*
-		 * Enable idle task deep sleep. Allow the low power idle task
-		 * to go into deep sleep in S3 or lower.
-		 */
-		enable_sleep(SLEEP_MASK_AP_RUN);
-
-		return POWER_S3;
-
-	case POWER_S3S5:
-		/* Call hooks before we remove power rails */
-		hook_notify(HOOK_CHIPSET_SHUTDOWN);
-
-		/* Disable wireless */
-		wireless_set_state(WIRELESS_OFF);
-
-		/* Call hooks after we remove power rails */
-		hook_notify(HOOK_CHIPSET_SHUTDOWN_COMPLETE);
-
-		return POWER_S5;
-
-	case POWER_S5G3:
-		chipset_force_g3();
-
-		return POWER_G3;
-
-	default:
-		break;
-	}
-	return state;
-}
diff --git a/pylintrc b/pylintrc
new file mode 100644
index 0000000000..9de16177e8
--- /dev/null
+++ b/pylintrc
@@ -0,0 +1,24 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Changes to make pylint and black agree on the formatting.
+
+[MESSAGES CONTROL]
+
+disable=
+    bad-continuation,
+    bad-whitespace,
+    line-too-long,
+    # These have nothing to do with black, they are just annoying
+    fixme,
+    too-few-public-methods,
+    too-many-arguments,
+    too-many-branches,
+    too-many-locals,
+    too-many-nested-blocks,
+    too-many-statements
+
+[format]
+
+string-quote=double
diff --git a/pyproject.toml b/pyproject.toml
new file mode 100644
index 0000000000..83c116eb5f
--- /dev/null
+++ b/pyproject.toml
@@ -0,0 +1,2 @@
+[tool.black]
+line-length = 80
diff --git a/setup.py b/setup.py
index fc6c5d396b..031894cfe0 100644
--- a/setup.py
+++ b/setup.py
@@ -1,16 +1,17 @@
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 from setuptools import setup
 
+
 setup(
     name="ec3po",
     version="1.0.0rc1",
     author="Aseda Aboagye",
     author_email="aaboagye@chromium.org",
     url="https://www.chromium.org/chromium-os/ec-development",
-    package_dir={"" : "util"},
+    package_dir={"": "util"},
     packages=["ec3po"],
     py_modules=["ec3po.console", "ec3po.interpreter"],
     description="EC console interpreter.",
@@ -22,7 +23,7 @@
     author="Nick Sanders",
     author_email="nsanders@chromium.org",
     url="https://www.chromium.org/chromium-os/ec-development",
-    package_dir={"" : "extra/tigertool"},
+    package_dir={"": "extra/tigertool"},
     packages=["ecusb"],
     description="Tiny implementation of servod.",
 )
@@ -33,17 +34,23 @@
     author="Nick Sanders",
     author_email="nsanders@chromium.org",
     url="https://www.chromium.org/chromium-os/ec-development",
-    package_dir={"" : "extra/usb_updater"},
+    package_dir={"": "extra/usb_updater"},
     py_modules=["servo_updater", "fw_update"],
-    entry_points = {
+    entry_points={
         "console_scripts": ["servo_updater=servo_updater:main"],
     },
-    data_files=[("share/servo_updater/configs",
-                    ["extra/usb_updater/c2d2.json",
-                     "extra/usb_updater/servo_v4.json",
-                     "extra/usb_updater/servo_v4p1.json",
-                     "extra/usb_updater/servo_micro.json",
-                     "extra/usb_updater/sweetberry.json"])],
+    data_files=[
+        (
+            "share/servo_updater/configs",
+            [
+                "extra/usb_updater/c2d2.json",
+                "extra/usb_updater/servo_v4.json",
+                "extra/usb_updater/servo_v4p1.json",
+                "extra/usb_updater/servo_micro.json",
+                "extra/usb_updater/sweetberry.json",
+            ],
+        )
+    ],
     description="Servo usb updater.",
 )
 
@@ -53,9 +60,9 @@
     author="Nick Sanders",
     author_email="nsanders@chromium.org",
     url="https://www.chromium.org/chromium-os/ec-development",
-    package_dir={"" : "extra/usb_power"},
+    package_dir={"": "extra/usb_power"},
     py_modules=["powerlog", "stats_manager"],
-    entry_points = {
+    entry_points={
         "console_scripts": ["powerlog=powerlog:main"],
     },
     description="Sweetberry power logger.",
@@ -67,9 +74,9 @@
     author="Nick Sanders",
     author_email="nsanders@chromium.org",
     url="https://www.chromium.org/chromium-os/ec-development",
-    package_dir={"" : "extra/usb_serial"},
+    package_dir={"": "extra/usb_serial"},
     py_modules=["console"],
-    entry_points = {
+    entry_points={
         "console_scripts": ["usb_console=console:main"],
     },
     description="Tool to open the usb console on servo, cr50.",
@@ -81,11 +88,10 @@
     author="Wei-Han Chen",
     author_email="stimim@chromium.org",
     url="https://www.chromium.org/chromium-os/ec-development",
-    package_dir={"" : "util"},
+    package_dir={"": "util"},
     py_modules=["unpack_ftb"],
-    entry_points = {
+    entry_points={
         "console_scripts": ["unpack_ftb=unpack_ftb:main"],
     },
     description="Tool to convert ST touchpad .ftb file to .bin",
 )
-
diff --git a/test/abort.c b/test/abort.c
new file mode 100644
index 0000000000..dcc798861e
--- /dev/null
+++ b/test/abort.c
@@ -0,0 +1,80 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "panic.h"
+#include "system.h"
+#include "task.h"
+#include "test_util.h"
+
+#include <stdlib.h>
+
+test_static int test_abort(void)
+{
+	ccprintf("Calling abort\n");
+	cflush();
+	abort();
+	/* Should never reach this. */
+	return EC_ERROR_UNKNOWN;
+}
+
+test_static int test_panic_data(void)
+{
+	const uint32_t expected_reason = PANIC_SW_EXIT;
+	/* Note: The task_id can be found with the "taskinfo" command. */
+	const uint32_t expected_task_id = 5;
+	const uint8_t expected_exception = 0;
+
+	uint32_t reason = 0;
+	uint32_t info = 0;
+	uint8_t exception = UINT8_MAX;
+
+	panic_get_reason(&reason, &info, &exception);
+
+	TEST_EQ(reason, expected_reason, "%08x");
+	TEST_EQ(info, expected_task_id, "%d");
+	TEST_EQ(exception, expected_exception, "%d");
+
+	return EC_SUCCESS;
+}
+
+test_static void run_test_step1(void)
+{
+	test_set_next_step(TEST_STATE_STEP_2);
+	RUN_TEST(test_abort);
+}
+
+test_static void run_test_step2(void)
+{
+	RUN_TEST(test_panic_data);
+
+	if (test_get_error_count())
+		test_reboot_to_next_step(TEST_STATE_FAILED);
+	else
+		test_reboot_to_next_step(TEST_STATE_PASSED);
+}
+
+void test_run_step(uint32_t state)
+{
+	if (state & TEST_STATE_MASK(TEST_STATE_STEP_1)) {
+		run_test_step1();
+	} else if (state & TEST_STATE_MASK(TEST_STATE_STEP_2)) {
+		run_test_step2();
+	}
+}
+
+int task_test(void *unused)
+{
+	if (IS_ENABLED(SECTION_IS_RW))
+		test_run_multistep();
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
+{
+	test_reset();
+	msleep(30); /* Wait for TASK_ID_TEST to initialize */
+	task_wake(TASK_ID_TEST);
+}
diff --git a/test/abort.tasklist b/test/abort.tasklist
new file mode 100644
index 0000000000..273a9664c0
--- /dev/null
+++ b/test/abort.tasklist
@@ -0,0 +1,10 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST \
+  TASK_TEST(TEST, task_test, NULL, TASK_STACK_SIZE)
diff --git a/test/accel_cal.c b/test/accel_cal.c
index 1fa657b36c..5c50211bd5 100644
--- a/test/accel_cal.c
+++ b/test/accel_cal.c
@@ -1,12 +1,13 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include "common.h"
 #include "accel_cal.h"
-#include "test_util.h"
+#include "common.h"
 #include "motion_sense.h"
+#include "test_util.h"
+
 #include <math.h>
 
 struct motion_sensor_t motion_sensors[] = {};
@@ -29,15 +30,15 @@ struct accel_cal cal = {
 
 static bool accumulate(float x, float y, float z, float temperature)
 {
-	return accel_cal_accumulate(&cal, 0, x, y, z, temperature)
-		| accel_cal_accumulate(&cal, 200 * MSEC, x, y, z, temperature)
-		| accel_cal_accumulate(&cal, 400 * MSEC, x, y, z, temperature)
-		| accel_cal_accumulate(&cal, 600 * MSEC, x, y, z, temperature)
-		| accel_cal_accumulate(&cal, 800 * MSEC, x, y, z, temperature)
-		| accel_cal_accumulate(&cal, 1000 * MSEC, x, y, z, temperature);
+	return accel_cal_accumulate(&cal, 0, x, y, z, temperature) ||
+	       accel_cal_accumulate(&cal, 200 * MSEC, x, y, z, temperature) ||
+	       accel_cal_accumulate(&cal, 400 * MSEC, x, y, z, temperature) ||
+	       accel_cal_accumulate(&cal, 600 * MSEC, x, y, z, temperature) ||
+	       accel_cal_accumulate(&cal, 800 * MSEC, x, y, z, temperature) ||
+	       accel_cal_accumulate(&cal, 1000 * MSEC, x, y, z, temperature);
 }
 
-static int test_calibrated_correctly_with_kasa(void)
+DECLARE_EC_TEST(test_calibrated_correctly_with_kasa)
 {
 	bool has_bias;
 
@@ -50,15 +51,15 @@ static int test_calibrated_correctly_with_kasa(void)
 	accumulate(0.7171f, 0.7171f, 0.7171f, 21.0f);
 	has_bias = accumulate(-0.6971f, -0.6971f, -0.6971f, 21.0f);
 
-	TEST_EQ(has_bias, true, "%d");
-	TEST_NEAR(cal.bias[X], 0.01f, 0.0001f, "%f");
-	TEST_NEAR(cal.bias[Y], 0.01f, 0.0001f, "%f");
-	TEST_NEAR(cal.bias[Z], 0.01f, 0.0001f, "%f");
+	zassert_true(has_bias);
+	zassert_within(cal.bias[X], 0.01f, 0.0001f, "%f", cal.bias[X]);
+	zassert_within(cal.bias[Y], 0.01f, 0.0001f, "%f", cal.bias[Y]);
+	zassert_within(cal.bias[Z], 0.01f, 0.0001f, "%f", cal.bias[Z]);
 
 	return EC_SUCCESS;
 }
 
-static int test_calibrated_correctly_with_newton(void)
+DECLARE_EC_TEST(test_calibrated_correctly_with_newton)
 {
 	bool has_bias = false;
 	struct kasa_fit kasa;
@@ -66,42 +67,38 @@ static int test_calibrated_correctly_with_newton(void)
 	float kasa_radius;
 	int i;
 	float data[] = {
-		1.00290f, 0.09170f, 0.09649f,
-		0.95183f, 0.23626f, 0.25853f,
-		0.95023f, 0.15387f, 0.31865f,
-		0.97374f, 0.01639f, 0.27675f,
-		0.88521f, 0.30212f, 0.39558f,
-		0.92787f, 0.35157f, 0.21209f,
-		0.95162f, 0.33173f, 0.10924f,
-		0.98397f, 0.22644f, 0.07737f,
+		1.00290f, 0.09170f, 0.09649f, 0.95183f, 0.23626f, 0.25853f,
+		0.95023f, 0.15387f, 0.31865f, 0.97374f, 0.01639f, 0.27675f,
+		0.88521f, 0.30212f, 0.39558f, 0.92787f, 0.35157f, 0.21209f,
+		0.95162f, 0.33173f, 0.10924f, 0.98397f, 0.22644f, 0.07737f,
 	};
 
 	kasa_reset(&kasa);
 	for (i = 0; i < ARRAY_SIZE(data); i += 3) {
-		TEST_EQ(has_bias, false, "%d");
-		kasa_accumulate(&kasa,  data[i], data[i + 1], data[i + 2]);
+		zassert_false(has_bias);
+		kasa_accumulate(&kasa, data[i], data[i + 1], data[i + 2]);
 		has_bias = accumulate(data[i], data[i + 1], data[i + 2], 21.0f);
 	}
 
 	kasa_compute(&kasa, kasa_bias, &kasa_radius);
-	TEST_EQ(has_bias, true, "%d");
+	zassert_true(has_bias);
 	/* Check that the bias is right */
-	TEST_NEAR(cal.bias[X], 0.01f, 0.001f, "%f");
-	TEST_NEAR(cal.bias[Y], 0.01f, 0.001f, "%f");
-	TEST_NEAR(cal.bias[Z], 0.01f, 0.001f, "%f");
+	zassert_within(cal.bias[X], 0.01f, 0.001f, "%f", cal.bias[X]);
+	zassert_within(cal.bias[Y], 0.01f, 0.001f, "%f", cal.bias[Y]);
+	zassert_within(cal.bias[Z], 0.01f, 0.001f, "%f", cal.bias[Z]);
 	/* Demonstrate that we got a better bias compared to kasa */
-	TEST_LT(sqrtf(powf(cal.bias[X] - 0.01f, 2.0f) +
-		      powf(cal.bias[Y] - 0.01f, 2.0f) +
-		      powf(cal.bias[Z] - 0.01f, 2.0f)),
-		sqrtf(powf(kasa_bias[X] - 0.01f, 2.0f) +
-		      powf(kasa_bias[Y] - 0.01f, 2.0f) +
-		      powf(kasa_bias[Z] - 0.01f, 2.0f)),
-		"%f");
+	zassert_true(sqrtf(powf(cal.bias[X] - 0.01f, 2.0f) +
+			   powf(cal.bias[Y] - 0.01f, 2.0f) +
+			   powf(cal.bias[Z] - 0.01f, 2.0f)) <
+			     sqrtf(powf(kasa_bias[X] - 0.01f, 2.0f) +
+				   powf(kasa_bias[Y] - 0.01f, 2.0f) +
+				   powf(kasa_bias[Z] - 0.01f, 2.0f)),
+		     NULL);
 
 	return EC_SUCCESS;
 }
 
-static int test_temperature_gates(void)
+DECLARE_EC_TEST(test_temperature_gates)
 {
 	bool has_bias;
 
@@ -114,7 +111,7 @@ static int test_temperature_gates(void)
 	accumulate(0.7171f, 0.7171f, 0.7171f, 21.0f);
 	has_bias = accumulate(-0.6971f, -0.6971f, -0.6971f, 31.0f);
 
-	TEST_EQ(has_bias, false, "%d");
+	zassert_false(has_bias);
 
 	return EC_SUCCESS;
 }
@@ -125,13 +122,21 @@ void before_test(void)
 	accel_cal_reset(&cal);
 }
 
-void run_test(int argc, char **argv)
+void after_test(void)
 {
-	test_reset();
-
-	RUN_TEST(test_calibrated_correctly_with_kasa);
-	RUN_TEST(test_calibrated_correctly_with_newton);
-	RUN_TEST(test_temperature_gates);
+}
 
-	test_print_result();
+TEST_MAIN()
+{
+	ztest_test_suite(test_accel_cal,
+			 ztest_unit_test_setup_teardown(
+				 test_calibrated_correctly_with_kasa,
+				 before_test, after_test),
+			 ztest_unit_test_setup_teardown(
+				 test_calibrated_correctly_with_newton,
+				 before_test, after_test),
+			 ztest_unit_test_setup_teardown(test_temperature_gates,
+							before_test,
+							after_test));
+	ztest_run_test_suite(test_accel_cal);
 }
diff --git a/test/accel_cal.tasklist b/test/accel_cal.tasklist
index 0e3696c3f0..d3fcf83121 100644
--- a/test/accel_cal.tasklist
+++ b/test/accel_cal.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/aes.c b/test/aes.c
deleted file mode 100644
index 1c71e2874e..0000000000
--- a/test/aes.c
+++ /dev/null
@@ -1,664 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */
-
-#include "aes.h"
-#include "aes-gcm.h"
-#include "console.h"
-#include "common.h"
-#include "test_util.h"
-#include "timer.h"
-#include "util.h"
-#include "watchdog.h"
-
-/* Temporary buffer, to avoid using too much stack space. */
-static uint8_t tmp[512];
-
-/*
- * Do encryption, put result in |result|, and compare with |ciphertext|.
- */
-static int test_aes_gcm_encrypt(uint8_t *result,
-				const uint8_t *key,
-				int key_size,
-				const uint8_t *plaintext,
-				const uint8_t *ciphertext,
-				int plaintext_size,
-				const uint8_t *nonce,
-				int nonce_size,
-				const uint8_t *tag,
-				int tag_size)
-{
-	static AES_KEY aes_key;
-	static GCM128_CONTEXT ctx;
-
-	TEST_ASSERT(AES_set_encrypt_key(key, 8 * key_size, &aes_key) == 0);
-
-	CRYPTO_gcm128_init(&ctx, &aes_key, (block128_f) AES_encrypt, 0);
-	CRYPTO_gcm128_setiv(&ctx, &aes_key, nonce, nonce_size);
-	TEST_ASSERT(CRYPTO_gcm128_encrypt(&ctx, &aes_key, plaintext, result,
-					  plaintext_size));
-	TEST_ASSERT(CRYPTO_gcm128_finish(&ctx, tag, tag_size));
-	TEST_ASSERT_ARRAY_EQ(ciphertext, result, plaintext_size);
-
-	return EC_SUCCESS;
-}
-
-/*
- * Do decryption, put result in |result|, and compare with |plaintext|.
- */
-static int test_aes_gcm_decrypt(uint8_t *result,
-				const uint8_t *key,
-				int key_size,
-				const uint8_t *plaintext,
-				const uint8_t *ciphertext,
-				int plaintext_size,
-				const uint8_t *nonce,
-				int nonce_size,
-				const uint8_t *tag,
-				int tag_size)
-{
-	static AES_KEY aes_key;
-	static GCM128_CONTEXT ctx;
-
-	TEST_ASSERT(AES_set_encrypt_key(key, 8 * key_size, &aes_key) == 0);
-
-	CRYPTO_gcm128_init(&ctx, &aes_key, (block128_f) AES_encrypt, 0);
-	CRYPTO_gcm128_setiv(&ctx, &aes_key, nonce, nonce_size);
-	TEST_ASSERT(CRYPTO_gcm128_decrypt(&ctx, &aes_key, ciphertext, result,
-					  plaintext_size));
-	TEST_ASSERT(CRYPTO_gcm128_finish(&ctx, tag, tag_size));
-	TEST_ASSERT_ARRAY_EQ(plaintext, result, plaintext_size);
-
-	return EC_SUCCESS;
-}
-
-static int test_aes_gcm_raw_inplace(const uint8_t *key,
-				    int key_size,
-				    const uint8_t *plaintext,
-				    const uint8_t *ciphertext,
-				    int plaintext_size,
-				    const uint8_t *nonce,
-				    int nonce_size,
-				    const uint8_t *tag,
-				    int tag_size)
-{
-
-	/*
-	 * Make copies that will be clobbered during in-place encryption or
-	 * decryption.
-	 */
-	uint8_t plaintext_copy[plaintext_size];
-	uint8_t ciphertext_copy[plaintext_size];
-
-	memcpy(plaintext_copy, plaintext, plaintext_size);
-	memcpy(ciphertext_copy, ciphertext, plaintext_size);
-
-	TEST_ASSERT(test_aes_gcm_encrypt(plaintext_copy,
-					 key,
-					 key_size,
-					 plaintext_copy,
-					 ciphertext,
-					 plaintext_size,
-					 nonce,
-					 nonce_size,
-					 tag,
-					 tag_size) == EC_SUCCESS);
-
-	TEST_ASSERT(test_aes_gcm_decrypt(ciphertext_copy,
-					 key,
-					 key_size,
-					 plaintext,
-					 ciphertext_copy,
-					 plaintext_size,
-					 nonce,
-					 nonce_size,
-					 tag,
-					 tag_size) == EC_SUCCESS);
-
-	return EC_SUCCESS;
-}
-
-static int test_aes_gcm_raw_non_inplace(const uint8_t *key,
-					int key_size,
-					const uint8_t *plaintext,
-					const uint8_t *ciphertext,
-					int plaintext_size,
-					const uint8_t *nonce,
-					int nonce_size,
-					const uint8_t *tag,
-					int tag_size)
-{
-	TEST_ASSERT(test_aes_gcm_encrypt(tmp,
-					 key,
-					 key_size,
-					 plaintext,
-					 ciphertext,
-					 plaintext_size,
-					 nonce,
-					 nonce_size,
-					 tag,
-					 tag_size) == EC_SUCCESS);
-
-	TEST_ASSERT(test_aes_gcm_decrypt(tmp,
-					 key,
-					 key_size,
-					 plaintext,
-					 ciphertext,
-					 plaintext_size,
-					 nonce,
-					 nonce_size,
-					 tag,
-					 tag_size) == EC_SUCCESS);
-
-	return EC_SUCCESS;
-}
-
-static int test_aes_gcm_raw(const uint8_t *key,
-			    int key_size,
-			    const uint8_t *plaintext,
-			    const uint8_t *ciphertext,
-			    int plaintext_size,
-			    const uint8_t *nonce,
-			    int nonce_size,
-			    const uint8_t *tag,
-			    int tag_size)
-{
-	TEST_ASSERT(plaintext_size <= sizeof(tmp));
-
-	TEST_ASSERT(test_aes_gcm_raw_non_inplace(key,
-						 key_size,
-						 plaintext,
-						 ciphertext,
-						 plaintext_size,
-						 nonce,
-						 nonce_size,
-						 tag,
-						 tag_size) == EC_SUCCESS);
-	TEST_ASSERT(test_aes_gcm_raw_inplace(key,
-					     key_size,
-					     plaintext,
-					     ciphertext,
-					     plaintext_size,
-					     nonce,
-					     nonce_size,
-					     tag,
-					     tag_size) == EC_SUCCESS);
-
-	return EC_SUCCESS;
-}
-
-static int test_aes_gcm(void)
-{
-	/*
-	 * Test vectors from BoringSSL crypto/fipsmodule/modes/gcm_tests.txt
-	 * (only the ones with actual data, and no additional data).
-	 */
-	static const uint8_t key1[] = {
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	};
-	static const uint8_t plain1[] = {
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	};
-	static const uint8_t nonce1[] = {
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00,
-	};
-	static const uint8_t cipher1[] = {
-		0x03, 0x88, 0xda, 0xce, 0x60, 0xb6, 0xa3, 0x92,
-		0xf3, 0x28, 0xc2, 0xb9, 0x71, 0xb2, 0xfe, 0x78,
-	};
-	static const uint8_t tag1[] = {
-		0xab, 0x6e, 0x47, 0xd4, 0x2c, 0xec, 0x13, 0xbd,
-		0xf5, 0x3a, 0x67, 0xb2, 0x12, 0x57, 0xbd, 0xdf,
-	};
-
-	static const uint8_t key2[] = {
-		0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c,
-		0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08,
-	};
-	static const uint8_t plain2[] = {
-		0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5,
-		0xa5, 0x59, 0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a,
-		0x86, 0xa7, 0xa9, 0x53, 0x15, 0x34, 0xf7, 0xda,
-		0x2e, 0x4c, 0x30, 0x3d, 0x8a, 0x31, 0x8a, 0x72,
-		0x1c, 0x3c, 0x0c, 0x95, 0x95, 0x68, 0x09, 0x53,
-		0x2f, 0xcf, 0x0e, 0x24, 0x49, 0xa6, 0xb5, 0x25,
-		0xb1, 0x6a, 0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57,
-		0xba, 0x63, 0x7b, 0x39, 0x1a, 0xaf, 0xd2, 0x55,
-	};
-	static const uint8_t nonce2[] = {
-		0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce, 0xdb, 0xad,
-		0xde, 0xca, 0xf8, 0x88,
-	};
-	static const uint8_t cipher2[] = {
-		0x42, 0x83, 0x1e, 0xc2, 0x21, 0x77, 0x74, 0x24,
-		0x4b, 0x72, 0x21, 0xb7, 0x84, 0xd0, 0xd4, 0x9c,
-		0xe3, 0xaa, 0x21, 0x2f, 0x2c, 0x02, 0xa4, 0xe0,
-		0x35, 0xc1, 0x7e, 0x23, 0x29, 0xac, 0xa1, 0x2e,
-		0x21, 0xd5, 0x14, 0xb2, 0x54, 0x66, 0x93, 0x1c,
-		0x7d, 0x8f, 0x6a, 0x5a, 0xac, 0x84, 0xaa, 0x05,
-		0x1b, 0xa3, 0x0b, 0x39, 0x6a, 0x0a, 0xac, 0x97,
-		0x3d, 0x58, 0xe0, 0x91, 0x47, 0x3f, 0x59, 0x85,
-	};
-	static const uint8_t tag2[] = {
-		0x4d, 0x5c, 0x2a, 0xf3, 0x27, 0xcd, 0x64, 0xa6,
-		0x2c, 0xf3, 0x5a, 0xbd, 0x2b, 0xa6, 0xfa, 0xb4,
-	};
-
-	static const uint8_t key3[] = {
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	};
-	static const uint8_t plain3[] = {
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	};
-	static const uint8_t nonce3[] = {
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00,
-	};
-	static const uint8_t cipher3[] = {
-		0x98, 0xe7, 0x24, 0x7c, 0x07, 0xf0, 0xfe, 0x41,
-		0x1c, 0x26, 0x7e, 0x43, 0x84, 0xb0, 0xf6, 0x00,
-	};
-	static const uint8_t tag3[] = {
-		0x2f, 0xf5, 0x8d, 0x80, 0x03, 0x39, 0x27, 0xab,
-		0x8e, 0xf4, 0xd4, 0x58, 0x75, 0x14, 0xf0, 0xfb,
-	};
-
-	static const uint8_t key4[] = {
-		0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c,
-		0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08,
-		0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c,
-	};
-	static const uint8_t plain4[] = {
-		0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5,
-		0xa5, 0x59, 0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a,
-		0x86, 0xa7, 0xa9, 0x53, 0x15, 0x34, 0xf7, 0xda,
-		0x2e, 0x4c, 0x30, 0x3d, 0x8a, 0x31, 0x8a, 0x72,
-		0x1c, 0x3c, 0x0c, 0x95, 0x95, 0x68, 0x09, 0x53,
-		0x2f, 0xcf, 0x0e, 0x24, 0x49, 0xa6, 0xb5, 0x25,
-		0xb1, 0x6a, 0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57,
-		0xba, 0x63, 0x7b, 0x39, 0x1a, 0xaf, 0xd2, 0x55,
-	};
-	static const uint8_t nonce4[] = {
-		0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce, 0xdb, 0xad,
-		0xde, 0xca, 0xf8, 0x88,
-	};
-	static const uint8_t cipher4[] = {
-		0x39, 0x80, 0xca, 0x0b, 0x3c, 0x00, 0xe8, 0x41,
-		0xeb, 0x06, 0xfa, 0xc4, 0x87, 0x2a, 0x27, 0x57,
-		0x85, 0x9e, 0x1c, 0xea, 0xa6, 0xef, 0xd9, 0x84,
-		0x62, 0x85, 0x93, 0xb4, 0x0c, 0xa1, 0xe1, 0x9c,
-		0x7d, 0x77, 0x3d, 0x00, 0xc1, 0x44, 0xc5, 0x25,
-		0xac, 0x61, 0x9d, 0x18, 0xc8, 0x4a, 0x3f, 0x47,
-		0x18, 0xe2, 0x44, 0x8b, 0x2f, 0xe3, 0x24, 0xd9,
-		0xcc, 0xda, 0x27, 0x10, 0xac, 0xad, 0xe2, 0x56,
-	};
-	static const uint8_t tag4[] = {
-		0x99, 0x24, 0xa7, 0xc8, 0x58, 0x73, 0x36, 0xbf,
-		0xb1, 0x18, 0x02, 0x4d, 0xb8, 0x67, 0x4a, 0x14,
-	};
-
-	static const uint8_t key5[] = {
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	};
-	static const uint8_t plain5[] = {
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	};
-	static const uint8_t nonce5[] = {
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00,
-	};
-	static const uint8_t cipher5[] = {
-		0xce, 0xa7, 0x40, 0x3d, 0x4d, 0x60, 0x6b, 0x6e,
-		0x07, 0x4e, 0xc5, 0xd3, 0xba, 0xf3, 0x9d, 0x18,
-	};
-	static const uint8_t tag5[] = {
-		0xd0, 0xd1, 0xc8, 0xa7, 0x99, 0x99, 0x6b, 0xf0,
-		0x26, 0x5b, 0x98, 0xb5, 0xd4, 0x8a, 0xb9, 0x19,
-	};
-
-	static const uint8_t key6[] = {
-		0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c,
-		0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08,
-		0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c,
-		0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08,
-	};
-	static const uint8_t plain6[] = {
-		0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5,
-		0xa5, 0x59, 0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a,
-		0x86, 0xa7, 0xa9, 0x53, 0x15, 0x34, 0xf7, 0xda,
-		0x2e, 0x4c, 0x30, 0x3d, 0x8a, 0x31, 0x8a, 0x72,
-		0x1c, 0x3c, 0x0c, 0x95, 0x95, 0x68, 0x09, 0x53,
-		0x2f, 0xcf, 0x0e, 0x24, 0x49, 0xa6, 0xb5, 0x25,
-		0xb1, 0x6a, 0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57,
-		0xba, 0x63, 0x7b, 0x39, 0x1a, 0xaf, 0xd2, 0x55,
-	};
-	static const uint8_t nonce6[] = {
-		0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce, 0xdb, 0xad,
-		0xde, 0xca, 0xf8, 0x88,
-	};
-	static const uint8_t cipher6[] = {
-		0x52, 0x2d, 0xc1, 0xf0, 0x99, 0x56, 0x7d, 0x07,
-		0xf4, 0x7f, 0x37, 0xa3, 0x2a, 0x84, 0x42, 0x7d,
-		0x64, 0x3a, 0x8c, 0xdc, 0xbf, 0xe5, 0xc0, 0xc9,
-		0x75, 0x98, 0xa2, 0xbd, 0x25, 0x55, 0xd1, 0xaa,
-		0x8c, 0xb0, 0x8e, 0x48, 0x59, 0x0d, 0xbb, 0x3d,
-		0xa7, 0xb0, 0x8b, 0x10, 0x56, 0x82, 0x88, 0x38,
-		0xc5, 0xf6, 0x1e, 0x63, 0x93, 0xba, 0x7a, 0x0a,
-		0xbc, 0xc9, 0xf6, 0x62, 0x89, 0x80, 0x15, 0xad,
-	};
-	static const uint8_t tag6[] = {
-		0xb0, 0x94, 0xda, 0xc5, 0xd9, 0x34, 0x71, 0xbd,
-		0xec, 0x1a, 0x50, 0x22, 0x70, 0xe3, 0xcc, 0x6c,
-	};
-
-	static const uint8_t key7[] = {
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	};
-	static const uint8_t plain7[] = {
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	};
-	/* This nonce results in 0xfff in counter LSB. */
-	static const uint8_t nonce7[] = {
-		0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	};
-	static const uint8_t cipher7[] = {
-		0x56, 0xb3, 0x37, 0x3c, 0xa9, 0xef, 0x6e, 0x4a,
-		0x2b, 0x64, 0xfe, 0x1e, 0x9a, 0x17, 0xb6, 0x14,
-		0x25, 0xf1, 0x0d, 0x47, 0xa7, 0x5a, 0x5f, 0xce,
-		0x13, 0xef, 0xc6, 0xbc, 0x78, 0x4a, 0xf2, 0x4f,
-		0x41, 0x41, 0xbd, 0xd4, 0x8c, 0xf7, 0xc7, 0x70,
-		0x88, 0x7a, 0xfd, 0x57, 0x3c, 0xca, 0x54, 0x18,
-		0xa9, 0xae, 0xff, 0xcd, 0x7c, 0x5c, 0xed, 0xdf,
-		0xc6, 0xa7, 0x83, 0x97, 0xb9, 0xa8, 0x5b, 0x49,
-		0x9d, 0xa5, 0x58, 0x25, 0x72, 0x67, 0xca, 0xab,
-		0x2a, 0xd0, 0xb2, 0x3c, 0xa4, 0x76, 0xa5, 0x3c,
-		0xb1, 0x7f, 0xb4, 0x1c, 0x4b, 0x8b, 0x47, 0x5c,
-		0xb4, 0xf3, 0xf7, 0x16, 0x50, 0x94, 0xc2, 0x29,
-		0xc9, 0xe8, 0xc4, 0xdc, 0x0a, 0x2a, 0x5f, 0xf1,
-		0x90, 0x3e, 0x50, 0x15, 0x11, 0x22, 0x13, 0x76,
-		0xa1, 0xcd, 0xb8, 0x36, 0x4c, 0x50, 0x61, 0xa2,
-		0x0c, 0xae, 0x74, 0xbc, 0x4a, 0xcd, 0x76, 0xce,
-		0xb0, 0xab, 0xc9, 0xfd, 0x32, 0x17, 0xef, 0x9f,
-		0x8c, 0x90, 0xbe, 0x40, 0x2d, 0xdf, 0x6d, 0x86,
-		0x97, 0xf4, 0xf8, 0x80, 0xdf, 0xf1, 0x5b, 0xfb,
-		0x7a, 0x6b, 0x28, 0x24, 0x1e, 0xc8, 0xfe, 0x18,
-		0x3c, 0x2d, 0x59, 0xe3, 0xf9, 0xdf, 0xff, 0x65,
-		0x3c, 0x71, 0x26, 0xf0, 0xac, 0xb9, 0xe6, 0x42,
-		0x11, 0xf4, 0x2b, 0xae, 0x12, 0xaf, 0x46, 0x2b,
-		0x10, 0x70, 0xbe, 0xf1, 0xab, 0x5e, 0x36, 0x06,
-		0x87, 0x2c, 0xa1, 0x0d, 0xee, 0x15, 0xb3, 0x24,
-		0x9b, 0x1a, 0x1b, 0x95, 0x8f, 0x23, 0x13, 0x4c,
-		0x4b, 0xcc, 0xb7, 0xd0, 0x32, 0x00, 0xbc, 0xe4,
-		0x20, 0xa2, 0xf8, 0xeb, 0x66, 0xdc, 0xf3, 0x64,
-		0x4d, 0x14, 0x23, 0xc1, 0xb5, 0x69, 0x90, 0x03,
-		0xc1, 0x3e, 0xce, 0xf4, 0xbf, 0x38, 0xa3, 0xb6,
-		0x0e, 0xed, 0xc3, 0x40, 0x33, 0xba, 0xc1, 0x90,
-		0x27, 0x83, 0xdc, 0x6d, 0x89, 0xe2, 0xe7, 0x74,
-		0x18, 0x8a, 0x43, 0x9c, 0x7e, 0xbc, 0xc0, 0x67,
-		0x2d, 0xbd, 0xa4, 0xdd, 0xcf, 0xb2, 0x79, 0x46,
-		0x13, 0xb0, 0xbe, 0x41, 0x31, 0x5e, 0xf7, 0x78,
-		0x70, 0x8a, 0x70, 0xee, 0x7d, 0x75, 0x16, 0x5c,
-	};
-	static const uint8_t tag7[] = {
-		0x8b, 0x30, 0x7f, 0x6b, 0x33, 0x28, 0x6d, 0x0a,
-		0xb0, 0x26, 0xa9, 0xed, 0x3f, 0xe1, 0xe8, 0x5f,
-	};
-
-	TEST_ASSERT(!test_aes_gcm_raw(key1, sizeof(key1),
-			plain1, cipher1, sizeof(plain1),
-			nonce1, sizeof(nonce1), tag1, sizeof(tag1)));
-	TEST_ASSERT(!test_aes_gcm_raw(key2, sizeof(key2),
-			plain2, cipher2, sizeof(plain2),
-			nonce2, sizeof(nonce2), tag2, sizeof(tag2)));
-	TEST_ASSERT(!test_aes_gcm_raw(key3, sizeof(key3),
-			plain3, cipher3, sizeof(plain3),
-			nonce3, sizeof(nonce3), tag3, sizeof(tag3)));
-	TEST_ASSERT(!test_aes_gcm_raw(key4, sizeof(key4),
-			plain4, cipher4, sizeof(plain4),
-			nonce4, sizeof(nonce4), tag4, sizeof(tag4)));
-	TEST_ASSERT(!test_aes_gcm_raw(key5, sizeof(key5),
-			plain5, cipher5, sizeof(plain5),
-			nonce5, sizeof(nonce5), tag5, sizeof(tag5)));
-	TEST_ASSERT(!test_aes_gcm_raw(key6, sizeof(key6),
-			plain6, cipher6, sizeof(plain6),
-			nonce6, sizeof(nonce6), tag6, sizeof(tag6)));
-	TEST_ASSERT(!test_aes_gcm_raw(key7, sizeof(key7),
-			plain7, cipher7, sizeof(plain7),
-			nonce7, sizeof(nonce7), tag7, sizeof(tag7)));
-
-	return EC_SUCCESS;
-}
-
-static void test_aes_gcm_speed(void)
-{
-	int i;
-	static const uint8_t key[] = {
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	};
-	const int key_size = sizeof(key);
-	static const uint8_t plaintext[512] = { 0 };
-	const int plaintext_size = sizeof(plaintext);
-	static const uint8_t nonce[] = {
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00,
-	};
-	const int nonce_size = sizeof(nonce);
-	uint8_t tag[16] = {0};
-	const int tag_size = sizeof(tag);
-
-	uint8_t *out = tmp;
-	static AES_KEY aes_key;
-	static GCM128_CONTEXT ctx;
-	timestamp_t t0, t1;
-
-	assert(plaintext_size <= sizeof(tmp));
-
-	t0 = get_time();
-	for (i = 0; i < 1000; i++) {
-		AES_set_encrypt_key(key, 8 * key_size, &aes_key);
-		CRYPTO_gcm128_init(&ctx, &aes_key, (block128_f)AES_encrypt, 0);
-		CRYPTO_gcm128_setiv(&ctx, &aes_key, nonce, nonce_size);
-		CRYPTO_gcm128_encrypt(&ctx, &aes_key, plaintext, out,
-				plaintext_size);
-		CRYPTO_gcm128_tag(&ctx, tag, tag_size);
-	}
-	t1 = get_time();
-	ccprintf("AES-GCM duration %lld us\n", (long long)(t1.val - t0.val));
-}
-
-static int test_aes_raw(const uint8_t *key, int key_size,
-			const uint8_t *plaintext, const uint8_t *ciphertext)
-{
-	AES_KEY aes_key;
-	uint8_t *block = tmp;
-
-	TEST_ASSERT(AES_BLOCK_SIZE <= sizeof(tmp));
-
-	TEST_ASSERT(AES_set_encrypt_key(key, 8 * key_size, &aes_key) == 0);
-
-	/* Test encryption. */
-	AES_encrypt(plaintext, block, &aes_key);
-	TEST_ASSERT_ARRAY_EQ(ciphertext, block, AES_BLOCK_SIZE);
-
-	/* Test in-place encryption. */
-	memcpy(block, plaintext, AES_BLOCK_SIZE);
-	AES_encrypt(block, block, &aes_key);
-	TEST_ASSERT_ARRAY_EQ(ciphertext, block, AES_BLOCK_SIZE);
-
-	TEST_ASSERT(AES_set_decrypt_key(key, 8 * key_size, &aes_key) == 0);
-
-	/* Test decryption. */
-	AES_decrypt(ciphertext, block, &aes_key);
-	TEST_ASSERT_ARRAY_EQ(plaintext, block, AES_BLOCK_SIZE);
-
-	/* Test in-place decryption. */
-	memcpy(block, ciphertext, AES_BLOCK_SIZE);
-	AES_decrypt(block, block, &aes_key);
-	TEST_ASSERT_ARRAY_EQ(plaintext, block, AES_BLOCK_SIZE);
-
-	return EC_SUCCESS;
-}
-
-static int test_aes(void)
-{
-	/* Test vectors from FIPS-197, Appendix C. */
-	static const uint8_t key1[] = {
-		0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
-		0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
-	};
-	static const uint8_t plain1[] = {
-		0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
-		0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
-	};
-	static const uint8_t cipher1[] = {
-		0x69, 0xc4, 0xe0, 0xd8, 0x6a, 0x7b, 0x04, 0x30,
-		0xd8, 0xcd, 0xb7, 0x80, 0x70, 0xb4, 0xc5, 0x5a,
-	};
-
-	static const uint8_t key2[] = {
-		0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
-		0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
-		0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
-	};
-	static const uint8_t plain2[] = {
-		0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
-		0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
-	};
-	static const uint8_t cipher2[] = {
-		0xdd, 0xa9, 0x7c, 0xa4, 0x86, 0x4c, 0xdf, 0xe0,
-		0x6e, 0xaf, 0x70, 0xa0, 0xec, 0x0d, 0x71, 0x91,
-	};
-
-	static const uint8_t key3[] = {
-		0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
-		0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
-		0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
-		0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
-	};
-	static const uint8_t plain3[] = {
-		0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
-		0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
-	};
-	static const uint8_t cipher3[] = {
-		0x8e, 0xa2, 0xb7, 0xca, 0x51, 0x67, 0x45, 0xbf,
-		0xea, 0xfc, 0x49, 0x90, 0x4b, 0x49, 0x60, 0x89,
-	};
-
-	TEST_ASSERT(!test_aes_raw(key1, sizeof(key1), plain1, cipher1));
-	TEST_ASSERT(!test_aes_raw(key2, sizeof(key2), plain2, cipher2));
-	TEST_ASSERT(!test_aes_raw(key3, sizeof(key3), plain3, cipher3));
-
-	return EC_SUCCESS;
-}
-
-static void test_aes_speed(void)
-{
-	int i;
-	/* Test vectors from FIPS-197, Appendix C. */
-	static const uint8_t key[] __aligned(4) = {
-		0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
-		0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
-	};
-	const int key_size = sizeof(key);
-	static const uint8_t plaintext[] __aligned(4) = {
-		0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
-		0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
-	};
-
-	AES_KEY aes_key;
-	uint8_t block[AES_BLOCK_SIZE];
-	timestamp_t t0, t1;
-
-	AES_set_encrypt_key(key, 8 * key_size, &aes_key);
-	AES_encrypt(plaintext, block, &aes_key);
-	t0 = get_time();
-	for (i = 0; i < 1000; i++)
-		AES_encrypt(block, block, &aes_key);
-	t1 = get_time();
-	ccprintf("AES duration %lld us\n", (long long)(t1.val - t0.val));
-}
-
-void run_test(int argc, char **argv)
-{
-	watchdog_reload();
-
-	/* do not check result, just as a benchmark */
-	test_aes_speed();
-
-	watchdog_reload();
-	RUN_TEST(test_aes);
-
-	/* do not check result, just as a benchmark */
-	test_aes_gcm_speed();
-
-	watchdog_reload();
-	RUN_TEST(test_aes_gcm);
-
-	test_print_result();
-}
diff --git a/test/aes.cc b/test/aes.cc
new file mode 100644
index 0000000000..98d79b4b03
--- /dev/null
+++ b/test/aes.cc
@@ -0,0 +1,606 @@
+/* Copyright 2018 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */
+
+#include "benchmark.h"
+#include "common.h"
+#include "test_util.h"
+
+extern "C" {
+#include "builtin/assert.h"
+#include "console.h"
+#include "timer.h"
+#include "util.h"
+#include "watchdog.h"
+}
+
+#include "aes_gcm_helpers.h"
+#include "openssl/aes.h"
+
+/* These must be included after the "openssl/aes.h" */
+#include "crypto/fipsmodule/aes/internal.h"
+#include "crypto/fipsmodule/modes/internal.h"
+
+/* Temporary buffer, to avoid using too much stack space. */
+static uint8_t tmp[512];
+
+/*
+ * Do encryption, put result in |result|, and compare with |ciphertext|.
+ */
+static int test_aes_gcm_encrypt(uint8_t *result, const uint8_t *key,
+				int key_size, const uint8_t *plaintext,
+				const uint8_t *ciphertext, int plaintext_size,
+				const uint8_t *nonce, int nonce_size,
+				const uint8_t *tag, int tag_size)
+{
+	static AES_KEY aes_key;
+	static GCM128_CONTEXT ctx;
+
+	TEST_ASSERT(AES_set_encrypt_key(key, 8 * key_size, &aes_key) == 0);
+
+	CRYPTO_gcm128_init(&ctx, &aes_key, (block128_f)AES_encrypt, 0);
+	CRYPTO_gcm128_setiv(&ctx, &aes_key, nonce, nonce_size);
+	TEST_ASSERT(CRYPTO_gcm128_encrypt(&ctx, &aes_key, plaintext, result,
+					  plaintext_size));
+	TEST_ASSERT(CRYPTO_gcm128_finish(&ctx, tag, tag_size));
+	TEST_ASSERT_ARRAY_EQ(ciphertext, result, plaintext_size);
+
+	return EC_SUCCESS;
+}
+
+/*
+ * Do decryption, put result in |result|, and compare with |plaintext|.
+ */
+static int test_aes_gcm_decrypt(uint8_t *result, const uint8_t *key,
+				int key_size, const uint8_t *plaintext,
+				const uint8_t *ciphertext, int plaintext_size,
+				const uint8_t *nonce, int nonce_size,
+				const uint8_t *tag, int tag_size)
+{
+	static AES_KEY aes_key;
+	static GCM128_CONTEXT ctx;
+
+	TEST_ASSERT(AES_set_encrypt_key(key, 8 * key_size, &aes_key) == 0);
+
+	CRYPTO_gcm128_init(&ctx, &aes_key, (block128_f)AES_encrypt, 0);
+	CRYPTO_gcm128_setiv(&ctx, &aes_key, nonce, nonce_size);
+	TEST_ASSERT(CRYPTO_gcm128_decrypt(&ctx, &aes_key, ciphertext, result,
+					  plaintext_size));
+	TEST_ASSERT(CRYPTO_gcm128_finish(&ctx, tag, tag_size));
+	TEST_ASSERT_ARRAY_EQ(plaintext, result, plaintext_size);
+
+	return EC_SUCCESS;
+}
+
+static int test_aes_gcm_raw_inplace(const uint8_t *key, int key_size,
+				    const uint8_t *plaintext,
+				    const uint8_t *ciphertext,
+				    int plaintext_size, const uint8_t *nonce,
+				    int nonce_size, const uint8_t *tag,
+				    int tag_size)
+{
+	/*
+	 * Make copies that will be clobbered during in-place encryption or
+	 * decryption.
+	 */
+	uint8_t plaintext_copy[plaintext_size];
+	uint8_t ciphertext_copy[plaintext_size];
+
+	memcpy(plaintext_copy, plaintext, plaintext_size);
+	memcpy(ciphertext_copy, ciphertext, plaintext_size);
+
+	TEST_ASSERT(test_aes_gcm_encrypt(plaintext_copy, key, key_size,
+					 plaintext_copy, ciphertext,
+					 plaintext_size, nonce, nonce_size, tag,
+					 tag_size) == EC_SUCCESS);
+
+	TEST_ASSERT(test_aes_gcm_decrypt(ciphertext_copy, key, key_size,
+					 plaintext, ciphertext_copy,
+					 plaintext_size, nonce, nonce_size, tag,
+					 tag_size) == EC_SUCCESS);
+
+	return EC_SUCCESS;
+}
+
+static int test_aes_gcm_raw_non_inplace(const uint8_t *key, int key_size,
+					const uint8_t *plaintext,
+					const uint8_t *ciphertext,
+					int plaintext_size,
+					const uint8_t *nonce, int nonce_size,
+					const uint8_t *tag, int tag_size)
+{
+	TEST_ASSERT(test_aes_gcm_encrypt(tmp, key, key_size, plaintext,
+					 ciphertext, plaintext_size, nonce,
+					 nonce_size, tag,
+					 tag_size) == EC_SUCCESS);
+
+	TEST_ASSERT(test_aes_gcm_decrypt(tmp, key, key_size, plaintext,
+					 ciphertext, plaintext_size, nonce,
+					 nonce_size, tag,
+					 tag_size) == EC_SUCCESS);
+
+	return EC_SUCCESS;
+}
+
+static int test_aes_gcm_raw(const uint8_t *key, int key_size,
+			    const uint8_t *plaintext, const uint8_t *ciphertext,
+			    std::size_t plaintext_size, const uint8_t *nonce,
+			    std::size_t nonce_size, const uint8_t *tag,
+			    std::size_t tag_size)
+{
+	TEST_ASSERT(plaintext_size <= sizeof(tmp));
+
+	TEST_ASSERT(test_aes_gcm_raw_non_inplace(key, key_size, plaintext,
+						 ciphertext, plaintext_size,
+						 nonce, nonce_size, tag,
+						 tag_size) == EC_SUCCESS);
+	TEST_ASSERT(test_aes_gcm_raw_inplace(key, key_size, plaintext,
+					     ciphertext, plaintext_size, nonce,
+					     nonce_size, tag,
+					     tag_size) == EC_SUCCESS);
+
+	return EC_SUCCESS;
+}
+
+static int test_aes_gcm(void)
+{
+	/*
+	 * Test vectors from BoringSSL crypto/fipsmodule/modes/gcm_tests.txt
+	 * (only the ones with actual data, and no additional data).
+	 */
+	static const uint8_t key1[] = {
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	};
+	static const uint8_t plain1[] = {
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	};
+	static const uint8_t nonce1[] = {
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	};
+	static const uint8_t cipher1[] = {
+		0x03, 0x88, 0xda, 0xce, 0x60, 0xb6, 0xa3, 0x92,
+		0xf3, 0x28, 0xc2, 0xb9, 0x71, 0xb2, 0xfe, 0x78,
+	};
+	static const uint8_t tag1[] = {
+		0xab, 0x6e, 0x47, 0xd4, 0x2c, 0xec, 0x13, 0xbd,
+		0xf5, 0x3a, 0x67, 0xb2, 0x12, 0x57, 0xbd, 0xdf,
+	};
+
+	static const uint8_t key2[] = {
+		0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c,
+		0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08,
+	};
+	static const uint8_t plain2[] = {
+		0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5, 0xa5, 0x59,
+		0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a, 0x86, 0xa7, 0xa9, 0x53,
+		0x15, 0x34, 0xf7, 0xda, 0x2e, 0x4c, 0x30, 0x3d, 0x8a, 0x31,
+		0x8a, 0x72, 0x1c, 0x3c, 0x0c, 0x95, 0x95, 0x68, 0x09, 0x53,
+		0x2f, 0xcf, 0x0e, 0x24, 0x49, 0xa6, 0xb5, 0x25, 0xb1, 0x6a,
+		0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57, 0xba, 0x63, 0x7b, 0x39,
+		0x1a, 0xaf, 0xd2, 0x55,
+	};
+	static const uint8_t nonce2[] = {
+		0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce,
+		0xdb, 0xad, 0xde, 0xca, 0xf8, 0x88,
+	};
+	static const uint8_t cipher2[] = {
+		0x42, 0x83, 0x1e, 0xc2, 0x21, 0x77, 0x74, 0x24, 0x4b, 0x72,
+		0x21, 0xb7, 0x84, 0xd0, 0xd4, 0x9c, 0xe3, 0xaa, 0x21, 0x2f,
+		0x2c, 0x02, 0xa4, 0xe0, 0x35, 0xc1, 0x7e, 0x23, 0x29, 0xac,
+		0xa1, 0x2e, 0x21, 0xd5, 0x14, 0xb2, 0x54, 0x66, 0x93, 0x1c,
+		0x7d, 0x8f, 0x6a, 0x5a, 0xac, 0x84, 0xaa, 0x05, 0x1b, 0xa3,
+		0x0b, 0x39, 0x6a, 0x0a, 0xac, 0x97, 0x3d, 0x58, 0xe0, 0x91,
+		0x47, 0x3f, 0x59, 0x85,
+	};
+	static const uint8_t tag2[] = {
+		0x4d, 0x5c, 0x2a, 0xf3, 0x27, 0xcd, 0x64, 0xa6,
+		0x2c, 0xf3, 0x5a, 0xbd, 0x2b, 0xa6, 0xfa, 0xb4,
+	};
+
+	static const uint8_t key3[] = {
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	};
+	static const uint8_t plain3[] = {
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	};
+	static const uint8_t nonce3[] = {
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	};
+	static const uint8_t cipher3[] = {
+		0x98, 0xe7, 0x24, 0x7c, 0x07, 0xf0, 0xfe, 0x41,
+		0x1c, 0x26, 0x7e, 0x43, 0x84, 0xb0, 0xf6, 0x00,
+	};
+	static const uint8_t tag3[] = {
+		0x2f, 0xf5, 0x8d, 0x80, 0x03, 0x39, 0x27, 0xab,
+		0x8e, 0xf4, 0xd4, 0x58, 0x75, 0x14, 0xf0, 0xfb,
+	};
+
+	static const uint8_t key4[] = {
+		0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c,
+		0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08,
+		0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c,
+	};
+	static const uint8_t plain4[] = {
+		0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5, 0xa5, 0x59,
+		0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a, 0x86, 0xa7, 0xa9, 0x53,
+		0x15, 0x34, 0xf7, 0xda, 0x2e, 0x4c, 0x30, 0x3d, 0x8a, 0x31,
+		0x8a, 0x72, 0x1c, 0x3c, 0x0c, 0x95, 0x95, 0x68, 0x09, 0x53,
+		0x2f, 0xcf, 0x0e, 0x24, 0x49, 0xa6, 0xb5, 0x25, 0xb1, 0x6a,
+		0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57, 0xba, 0x63, 0x7b, 0x39,
+		0x1a, 0xaf, 0xd2, 0x55,
+	};
+	static const uint8_t nonce4[] = {
+		0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce,
+		0xdb, 0xad, 0xde, 0xca, 0xf8, 0x88,
+	};
+	static const uint8_t cipher4[] = {
+		0x39, 0x80, 0xca, 0x0b, 0x3c, 0x00, 0xe8, 0x41, 0xeb, 0x06,
+		0xfa, 0xc4, 0x87, 0x2a, 0x27, 0x57, 0x85, 0x9e, 0x1c, 0xea,
+		0xa6, 0xef, 0xd9, 0x84, 0x62, 0x85, 0x93, 0xb4, 0x0c, 0xa1,
+		0xe1, 0x9c, 0x7d, 0x77, 0x3d, 0x00, 0xc1, 0x44, 0xc5, 0x25,
+		0xac, 0x61, 0x9d, 0x18, 0xc8, 0x4a, 0x3f, 0x47, 0x18, 0xe2,
+		0x44, 0x8b, 0x2f, 0xe3, 0x24, 0xd9, 0xcc, 0xda, 0x27, 0x10,
+		0xac, 0xad, 0xe2, 0x56,
+	};
+	static const uint8_t tag4[] = {
+		0x99, 0x24, 0xa7, 0xc8, 0x58, 0x73, 0x36, 0xbf,
+		0xb1, 0x18, 0x02, 0x4d, 0xb8, 0x67, 0x4a, 0x14,
+	};
+
+	static const uint8_t key5[] = {
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	};
+	static const uint8_t plain5[] = {
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	};
+	static const uint8_t nonce5[] = {
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	};
+	static const uint8_t cipher5[] = {
+		0xce, 0xa7, 0x40, 0x3d, 0x4d, 0x60, 0x6b, 0x6e,
+		0x07, 0x4e, 0xc5, 0xd3, 0xba, 0xf3, 0x9d, 0x18,
+	};
+	static const uint8_t tag5[] = {
+		0xd0, 0xd1, 0xc8, 0xa7, 0x99, 0x99, 0x6b, 0xf0,
+		0x26, 0x5b, 0x98, 0xb5, 0xd4, 0x8a, 0xb9, 0x19,
+	};
+
+	static const uint8_t key6[] = {
+		0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c,
+		0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08,
+		0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c,
+		0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08,
+	};
+	static const uint8_t plain6[] = {
+		0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5, 0xa5, 0x59,
+		0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a, 0x86, 0xa7, 0xa9, 0x53,
+		0x15, 0x34, 0xf7, 0xda, 0x2e, 0x4c, 0x30, 0x3d, 0x8a, 0x31,
+		0x8a, 0x72, 0x1c, 0x3c, 0x0c, 0x95, 0x95, 0x68, 0x09, 0x53,
+		0x2f, 0xcf, 0x0e, 0x24, 0x49, 0xa6, 0xb5, 0x25, 0xb1, 0x6a,
+		0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57, 0xba, 0x63, 0x7b, 0x39,
+		0x1a, 0xaf, 0xd2, 0x55,
+	};
+	static const uint8_t nonce6[] = {
+		0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce,
+		0xdb, 0xad, 0xde, 0xca, 0xf8, 0x88,
+	};
+	static const uint8_t cipher6[] = {
+		0x52, 0x2d, 0xc1, 0xf0, 0x99, 0x56, 0x7d, 0x07, 0xf4, 0x7f,
+		0x37, 0xa3, 0x2a, 0x84, 0x42, 0x7d, 0x64, 0x3a, 0x8c, 0xdc,
+		0xbf, 0xe5, 0xc0, 0xc9, 0x75, 0x98, 0xa2, 0xbd, 0x25, 0x55,
+		0xd1, 0xaa, 0x8c, 0xb0, 0x8e, 0x48, 0x59, 0x0d, 0xbb, 0x3d,
+		0xa7, 0xb0, 0x8b, 0x10, 0x56, 0x82, 0x88, 0x38, 0xc5, 0xf6,
+		0x1e, 0x63, 0x93, 0xba, 0x7a, 0x0a, 0xbc, 0xc9, 0xf6, 0x62,
+		0x89, 0x80, 0x15, 0xad,
+	};
+	static const uint8_t tag6[] = {
+		0xb0, 0x94, 0xda, 0xc5, 0xd9, 0x34, 0x71, 0xbd,
+		0xec, 0x1a, 0x50, 0x22, 0x70, 0xe3, 0xcc, 0x6c,
+	};
+
+	static const uint8_t key7[] = {
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	};
+	static const uint8_t plain7[] = {
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	};
+	/* This nonce results in 0xfff in counter LSB. */
+	static const uint8_t nonce7[] = {
+		0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00,
+	};
+	static const uint8_t cipher7[] = {
+		0x56, 0xb3, 0x37, 0x3c, 0xa9, 0xef, 0x6e, 0x4a, 0x2b, 0x64,
+		0xfe, 0x1e, 0x9a, 0x17, 0xb6, 0x14, 0x25, 0xf1, 0x0d, 0x47,
+		0xa7, 0x5a, 0x5f, 0xce, 0x13, 0xef, 0xc6, 0xbc, 0x78, 0x4a,
+		0xf2, 0x4f, 0x41, 0x41, 0xbd, 0xd4, 0x8c, 0xf7, 0xc7, 0x70,
+		0x88, 0x7a, 0xfd, 0x57, 0x3c, 0xca, 0x54, 0x18, 0xa9, 0xae,
+		0xff, 0xcd, 0x7c, 0x5c, 0xed, 0xdf, 0xc6, 0xa7, 0x83, 0x97,
+		0xb9, 0xa8, 0x5b, 0x49, 0x9d, 0xa5, 0x58, 0x25, 0x72, 0x67,
+		0xca, 0xab, 0x2a, 0xd0, 0xb2, 0x3c, 0xa4, 0x76, 0xa5, 0x3c,
+		0xb1, 0x7f, 0xb4, 0x1c, 0x4b, 0x8b, 0x47, 0x5c, 0xb4, 0xf3,
+		0xf7, 0x16, 0x50, 0x94, 0xc2, 0x29, 0xc9, 0xe8, 0xc4, 0xdc,
+		0x0a, 0x2a, 0x5f, 0xf1, 0x90, 0x3e, 0x50, 0x15, 0x11, 0x22,
+		0x13, 0x76, 0xa1, 0xcd, 0xb8, 0x36, 0x4c, 0x50, 0x61, 0xa2,
+		0x0c, 0xae, 0x74, 0xbc, 0x4a, 0xcd, 0x76, 0xce, 0xb0, 0xab,
+		0xc9, 0xfd, 0x32, 0x17, 0xef, 0x9f, 0x8c, 0x90, 0xbe, 0x40,
+		0x2d, 0xdf, 0x6d, 0x86, 0x97, 0xf4, 0xf8, 0x80, 0xdf, 0xf1,
+		0x5b, 0xfb, 0x7a, 0x6b, 0x28, 0x24, 0x1e, 0xc8, 0xfe, 0x18,
+		0x3c, 0x2d, 0x59, 0xe3, 0xf9, 0xdf, 0xff, 0x65, 0x3c, 0x71,
+		0x26, 0xf0, 0xac, 0xb9, 0xe6, 0x42, 0x11, 0xf4, 0x2b, 0xae,
+		0x12, 0xaf, 0x46, 0x2b, 0x10, 0x70, 0xbe, 0xf1, 0xab, 0x5e,
+		0x36, 0x06, 0x87, 0x2c, 0xa1, 0x0d, 0xee, 0x15, 0xb3, 0x24,
+		0x9b, 0x1a, 0x1b, 0x95, 0x8f, 0x23, 0x13, 0x4c, 0x4b, 0xcc,
+		0xb7, 0xd0, 0x32, 0x00, 0xbc, 0xe4, 0x20, 0xa2, 0xf8, 0xeb,
+		0x66, 0xdc, 0xf3, 0x64, 0x4d, 0x14, 0x23, 0xc1, 0xb5, 0x69,
+		0x90, 0x03, 0xc1, 0x3e, 0xce, 0xf4, 0xbf, 0x38, 0xa3, 0xb6,
+		0x0e, 0xed, 0xc3, 0x40, 0x33, 0xba, 0xc1, 0x90, 0x27, 0x83,
+		0xdc, 0x6d, 0x89, 0xe2, 0xe7, 0x74, 0x18, 0x8a, 0x43, 0x9c,
+		0x7e, 0xbc, 0xc0, 0x67, 0x2d, 0xbd, 0xa4, 0xdd, 0xcf, 0xb2,
+		0x79, 0x46, 0x13, 0xb0, 0xbe, 0x41, 0x31, 0x5e, 0xf7, 0x78,
+		0x70, 0x8a, 0x70, 0xee, 0x7d, 0x75, 0x16, 0x5c,
+	};
+	static const uint8_t tag7[] = {
+		0x8b, 0x30, 0x7f, 0x6b, 0x33, 0x28, 0x6d, 0x0a,
+		0xb0, 0x26, 0xa9, 0xed, 0x3f, 0xe1, 0xe8, 0x5f,
+	};
+
+	TEST_ASSERT(!test_aes_gcm_raw(key1, sizeof(key1), plain1, cipher1,
+				      sizeof(plain1), nonce1, sizeof(nonce1),
+				      tag1, sizeof(tag1)));
+	TEST_ASSERT(!test_aes_gcm_raw(key2, sizeof(key2), plain2, cipher2,
+				      sizeof(plain2), nonce2, sizeof(nonce2),
+				      tag2, sizeof(tag2)));
+	TEST_ASSERT(!test_aes_gcm_raw(key3, sizeof(key3), plain3, cipher3,
+				      sizeof(plain3), nonce3, sizeof(nonce3),
+				      tag3, sizeof(tag3)));
+	TEST_ASSERT(!test_aes_gcm_raw(key4, sizeof(key4), plain4, cipher4,
+				      sizeof(plain4), nonce4, sizeof(nonce4),
+				      tag4, sizeof(tag4)));
+	TEST_ASSERT(!test_aes_gcm_raw(key5, sizeof(key5), plain5, cipher5,
+				      sizeof(plain5), nonce5, sizeof(nonce5),
+				      tag5, sizeof(tag5)));
+	TEST_ASSERT(!test_aes_gcm_raw(key6, sizeof(key6), plain6, cipher6,
+				      sizeof(plain6), nonce6, sizeof(nonce6),
+				      tag6, sizeof(tag6)));
+	TEST_ASSERT(!test_aes_gcm_raw(key7, sizeof(key7), plain7, cipher7,
+				      sizeof(plain7), nonce7, sizeof(nonce7),
+				      tag7, sizeof(tag7)));
+
+	return EC_SUCCESS;
+}
+
+static void test_aes_gcm_speed(void)
+{
+	Benchmark benchmark({ .num_iterations = 1000 });
+	static const uint8_t key[] = {
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	};
+	const int key_size = sizeof(key);
+	static uint8_t plaintext[512] = { 0 };
+	const auto plaintext_size = sizeof(plaintext);
+	static const uint8_t nonce[] = {
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	};
+	const int nonce_size = sizeof(nonce);
+	uint8_t tag[16] = { 0 };
+	const int tag_size = sizeof(tag);
+
+	uint8_t *encrypted_data = tmp;
+	static AES_KEY aes_key;
+	static GCM128_CONTEXT ctx;
+
+	assert(plaintext_size <= sizeof(tmp));
+
+	benchmark.run("AES-GCM encrypt", [&]() {
+		AES_set_encrypt_key(key, 8 * key_size, &aes_key);
+		CRYPTO_gcm128_init(&ctx, &aes_key, (block128_f)AES_encrypt, 0);
+		CRYPTO_gcm128_setiv(&ctx, &aes_key, nonce, nonce_size);
+		CRYPTO_gcm128_encrypt(&ctx, &aes_key, plaintext, encrypted_data,
+				      plaintext_size);
+		CRYPTO_gcm128_tag(&ctx, tag, tag_size);
+	});
+
+	benchmark.run("AES-GCM decrypt", [&]() {
+		AES_set_encrypt_key(key, 8 * key_size, &aes_key);
+		CRYPTO_gcm128_init(&ctx, &aes_key, (block128_f)AES_encrypt, 0);
+		CRYPTO_gcm128_setiv(&ctx, &aes_key, nonce, nonce_size);
+		auto decrypt_res =
+			CRYPTO_gcm128_decrypt(&ctx, &aes_key, encrypted_data,
+					      plaintext, plaintext_size);
+
+		auto finish_res = CRYPTO_gcm128_finish(&ctx, tag, tag_size);
+		assert(decrypt_res);
+		assert(finish_res);
+	});
+	benchmark.print_results();
+}
+
+static int test_aes_raw(const uint8_t *key, int key_size,
+			const uint8_t *plaintext, const uint8_t *ciphertext)
+{
+	AES_KEY aes_key;
+	uint8_t *block = tmp;
+
+	TEST_ASSERT(AES_BLOCK_SIZE <= sizeof(tmp));
+
+	TEST_ASSERT(AES_set_encrypt_key(key, 8 * key_size, &aes_key) == 0);
+
+	/* Test encryption. */
+	AES_encrypt(plaintext, block, &aes_key);
+	TEST_ASSERT_ARRAY_EQ(ciphertext, block, AES_BLOCK_SIZE);
+
+	/* Test in-place encryption. */
+	memcpy(block, plaintext, AES_BLOCK_SIZE);
+	AES_encrypt(block, block, &aes_key);
+	TEST_ASSERT_ARRAY_EQ(ciphertext, block, AES_BLOCK_SIZE);
+
+	TEST_ASSERT(AES_set_decrypt_key(key, 8 * key_size, &aes_key) == 0);
+
+	/* Test decryption. */
+	AES_decrypt(ciphertext, block, &aes_key);
+	TEST_ASSERT_ARRAY_EQ(plaintext, block, AES_BLOCK_SIZE);
+
+	/* Test in-place decryption. */
+	memcpy(block, ciphertext, AES_BLOCK_SIZE);
+	AES_decrypt(block, block, &aes_key);
+	TEST_ASSERT_ARRAY_EQ(plaintext, block, AES_BLOCK_SIZE);
+
+	return EC_SUCCESS;
+}
+
+static int test_aes(void)
+{
+	/* Test vectors from FIPS-197, Appendix C. */
+	static const uint8_t key1[] = {
+		0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+		0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
+	};
+	static const uint8_t plain1[] = {
+		0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
+		0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
+	};
+	static const uint8_t cipher1[] = {
+		0x69, 0xc4, 0xe0, 0xd8, 0x6a, 0x7b, 0x04, 0x30,
+		0xd8, 0xcd, 0xb7, 0x80, 0x70, 0xb4, 0xc5, 0x5a,
+	};
+
+	static const uint8_t key2[] = {
+		0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+		0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
+		0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
+	};
+	static const uint8_t plain2[] = {
+		0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
+		0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
+	};
+	static const uint8_t cipher2[] = {
+		0xdd, 0xa9, 0x7c, 0xa4, 0x86, 0x4c, 0xdf, 0xe0,
+		0x6e, 0xaf, 0x70, 0xa0, 0xec, 0x0d, 0x71, 0x91,
+	};
+
+	static const uint8_t key3[] = {
+		0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+		0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
+		0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
+		0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
+	};
+	static const uint8_t plain3[] = {
+		0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
+		0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
+	};
+	static const uint8_t cipher3[] = {
+		0x8e, 0xa2, 0xb7, 0xca, 0x51, 0x67, 0x45, 0xbf,
+		0xea, 0xfc, 0x49, 0x90, 0x4b, 0x49, 0x60, 0x89,
+	};
+
+	TEST_ASSERT(!test_aes_raw(key1, sizeof(key1), plain1, cipher1));
+	TEST_ASSERT(!test_aes_raw(key2, sizeof(key2), plain2, cipher2));
+	TEST_ASSERT(!test_aes_raw(key3, sizeof(key3), plain3, cipher3));
+
+	return EC_SUCCESS;
+}
+
+static void test_aes_speed(void)
+{
+	Benchmark benchmark({ .num_iterations = 1000 });
+	/* Test vectors from FIPS-197, Appendix C. */
+	static const uint8_t key[] __aligned(4) = {
+		0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+		0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
+	};
+	const int key_size = sizeof(key);
+	static const uint8_t plaintext[] __aligned(4) = {
+		0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
+		0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
+	};
+
+	AES_KEY aes_key;
+	uint8_t block[AES_BLOCK_SIZE];
+
+	AES_set_encrypt_key(key, 8 * key_size, &aes_key);
+	AES_encrypt(plaintext, block, &aes_key);
+	benchmark.run("AES", [&block, &aes_key]() {
+		AES_encrypt(block, block, &aes_key);
+	});
+	benchmark.print_results();
+}
+
+void run_test(int argc, const char **argv)
+{
+	watchdog_reload();
+
+	/* do not check result, just as a benchmark */
+	test_aes_speed();
+
+	watchdog_reload();
+	RUN_TEST(test_aes);
+
+	/* do not check result, just as a benchmark */
+	test_aes_gcm_speed();
+
+	watchdog_reload();
+	RUN_TEST(test_aes_gcm);
+
+	test_print_result();
+}
diff --git a/test/aes.tasklist b/test/aes.tasklist
index 24870f2abb..86bc8aa2d5 100644
--- a/test/aes.tasklist
+++ b/test/aes.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/always_memset.c b/test/always_memset.c
new file mode 100644
index 0000000000..8a022ef8ef
--- /dev/null
+++ b/test/always_memset.c
@@ -0,0 +1,202 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * We enable optimization level 3 in the test/build.mk.
+ * Running these tests without optimization is pointless, since the primary
+ * purpose of the always_memset function is to evade compiler optimizations.
+ * If optimization is disabled, the test_optimization_working test will fail.
+ */
+
+#include "common.h"
+#include "cryptoc/util.h"
+#include "test_util.h"
+
+#include <string.h>
+
+/* 256 bytes of stack is only safe enough for a memcpy. */
+#define EXTRA_STACK_SIZE 256
+#define UNIQUE_STRING "Hello World!"
+
+/**
+ * @brief Check basic memset behavior of always_memset.
+ */
+test_static int test_basic_functionality(void)
+{
+	char buf[256];
+
+	for (size_t i = 0; i < sizeof(buf); i++) {
+		buf[i] = (char)i;
+	}
+
+	always_memset(buf, 1, sizeof(buf));
+
+	TEST_ASSERT_MEMSET(buf, 1, sizeof(buf));
+
+	return EC_SUCCESS;
+}
+
+/**
+ * @brief Builtin memset stand-in.
+ *
+ * The compiler doesn't see our EC memset as a function that can be optimized
+ * out "with no side effect", so we present one here.
+ */
+test_static inline __attribute__((always_inline)) void
+fake_builtin_memset(char *dest, char c, size_t len)
+{
+	for (size_t i = 0; i < len; i++)
+		dest[i] = c;
+}
+
+/**
+ * This function creates a contrived scenario where the compiler would choose
+ * to optimize out the last memset due to no side effect.
+ *
+ * This methodology/setup has also been manually tested using the real builtin
+ * memset with -O3 in a GNU/Linux environment using GCC-12.2.0 and clang-14.0.6.
+ *
+ * Notes for manually verifying:
+ * - Run outright with normal memset. Ensure that you can still read the
+ *   UNIQUE_STRING from p.
+ * - Use GDB.
+ * - Set break point at |exercise_memset| and run.
+ * - Run "info locals" to check the state of |space| and |buf|.
+ * - Run "p &space" and "p &buf". Ensure both are real stack addresses and
+ *   that buf's address is lower than space's address.
+ *   Ensure the size of |space|.
+ * - Save the address of |space| for later by doing "set $addr = &space".
+ * - Set a mem watch on |buf| by running "watch buf".
+ * - Run "c" to continue the function. Ensure that the only part of the function
+ *   that touches this variable is the initialization.
+ * - If there seems to be something odd happening, open "layout split" and
+ *   step instruction-by-instruction using "si".
+ *   Note that memset will not be a function call and will not always
+ *   look the same. It will probably be tightly integrated with other
+ *   functionality.
+ * - To check how much of the stack |space| was used by the caller,
+ *   run "x/256xb $adr" or "x/64xw $adr" after the memcpy.
+ *
+ * Disable ASAN with the attribute because this function returns a pointer to
+ * stack memory, which is normally very naughty, but is what we want to test
+ * here.
+ */
+__attribute__((no_sanitize("address"))) test_static void
+exercise_memset(char **p)
+{
+	/*
+	 * Add extra stack space so that |buf| doesn't get trampled while the
+	 * caller is processing the |p| we set (ex. printing and testing p).
+	 *
+	 * Without volatile, space will be optimized out.
+	 */
+	volatile char __unused space[EXTRA_STACK_SIZE] = {
+		[0 ... EXTRA_STACK_SIZE - 1] = 's'
+	};
+
+	char buf[] = UNIQUE_STRING;
+	*p = buf;
+
+	/*
+	 * Force access to |buf| to ensure that it is allocated and seen as
+	 * used. Without casting to volatile, the access would be optimized out.
+	 * We don't want to make |buf| itself volatile, since
+	 * we want the compiler to optimize out the final memset.
+	 */
+	for (size_t i = 0; i < sizeof(buf); i++)
+		(void)((volatile char *)buf)[i];
+
+	/* Expect the following memset to be omitted during optimization. */
+	fake_builtin_memset(buf, 0, sizeof(buf));
+}
+
+/**
+ * Ensure that optimization is removing a trailing memset that it deems to have
+ * no side-effect.
+ */
+test_static int test_optimization_working(void)
+{
+	char buf[sizeof(UNIQUE_STRING)];
+	char *p;
+
+	exercise_memset(&p);
+	memcpy(buf, p, sizeof(buf));
+
+	/*
+	 * We expect that the compiler would have optimized out the final
+	 * memset, thus we should still be able to see the UNIQUE_STRING in
+	 * memory.
+	 */
+	TEST_ASSERT_ARRAY_EQ(buf, UNIQUE_STRING, sizeof(buf));
+
+	return EC_SUCCESS;
+}
+
+/**
+ * This function creates a contrived scenario where the compiler would choose
+ * to optimize out the last memset due to no side effect.
+ *
+ * This function layout must remain identical to exercise_memset.
+ *
+ * Disable ASAN with the attribute because this function returns a pointer to
+ * stack memory, which is normally very naughty, but is what we want to test
+ * here.
+ */
+__attribute__((no_sanitize("address"))) test_static void
+exercise_always_memset(char **p)
+{
+	/*
+	 * Add extra stack space so that |buf| doesn't get trampled while the
+	 * caller is processing the |p| we set (ex. printing and testing p).
+	 *
+	 * Without volatile, space will be optimized out.
+	 */
+	volatile char __unused space[EXTRA_STACK_SIZE] = {
+		[0 ... EXTRA_STACK_SIZE - 1] = 's'
+	};
+
+	char buf[] = UNIQUE_STRING;
+	*p = buf;
+
+	/*
+	 * Force access to |buf| to ensure that it is allocated and seen as
+	 * used. Without casting to volatile, the access would be optimized out.
+	 * We don't want to make |buf| itself volatile, since
+	 * we want the compiler to optimize out the final memset.
+	 */
+	for (size_t i = 0; i < sizeof(buf); i++)
+		(void)((volatile char *)buf)[i];
+
+	/* Expect the following memset to NOT be omitted during optimization. */
+	always_memset(buf, 0, sizeof(buf));
+}
+
+/**
+ * Ensure that always_memset works when used in a scenario where a normal
+ * memset would be removed.
+ */
+test_static int test_always_memset(void)
+{
+	char buf[sizeof(UNIQUE_STRING)];
+	char *p;
+
+	exercise_always_memset(&p);
+	memcpy(buf, p, sizeof(buf));
+
+	TEST_ASSERT_MEMSET(buf, 0, sizeof(buf));
+
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
+{
+	test_reset();
+
+	RUN_TEST(test_basic_functionality);
+	RUN_TEST(test_optimization_working);
+	RUN_TEST(test_always_memset);
+
+	test_print_result();
+}
diff --git a/test/always_memset.tasklist b/test/always_memset.tasklist
new file mode 100644
index 0000000000..959f62ef79
--- /dev/null
+++ b/test/always_memset.tasklist
@@ -0,0 +1,9 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST
diff --git a/test/base32.c b/test/base32.c
index 433c874cba..50b9d994c1 100644
--- a/test/base32.c
+++ b/test/base32.c
@@ -1,17 +1,18 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Test Base-32 encoding/decoding
  */
 
-#include <stdio.h>
-#include "common.h"
 #include "base32.h"
+#include "common.h"
 #include "test_util.h"
 #include "util.h"
 
-static int test_crc5(void)
+#include <stdio.h>
+
+DECLARE_EC_TEST(test_crc5)
 {
 	uint32_t seen;
 	int i, j, c;
@@ -25,7 +26,7 @@ static int test_crc5(void)
 		seen = 0;
 		for (j = 0; j < 32; j++)
 			seen |= 1 << crc5_sym(j, i);
-		TEST_ASSERT(seen == 0xffffffff);
+		zassert_equal(seen, 0xffffffff);
 	}
 
 	/*
@@ -36,7 +37,7 @@ static int test_crc5(void)
 		seen = 0;
 		for (j = 0; j < 32; j++)
 			seen |= 1 << crc5_sym(i, j);
-		TEST_ASSERT(seen == 0xffffffff);
+		zassert_equal(seen, 0xffffffff);
 	}
 
 	/* Transposing different symbols generates distinct CRCs */
@@ -49,13 +50,12 @@ static int test_crc5(void)
 			}
 		}
 	}
-	TEST_ASSERT(errors == 0);
+	zassert_equal(errors, 0);
 
 	return EC_SUCCESS;
 }
 
-static int enctest(const void *src, int srcbits, int crc_every,
-		   const char *enc)
+static int enctest(const void *src, int srcbits, int crc_every, const char *enc)
 {
 	char dest[32];
 
@@ -69,17 +69,17 @@ static int enctest(const void *src, int srcbits, int crc_every,
 	return 0;
 }
 
-#define ENCTEST(a, b, c, d) TEST_ASSERT(enctest(a, b, c, d) == 0)
+#define ENCTEST(a, b, c, d) zassert_equal(enctest(a, b, c, d), 0, NULL)
 
-static int test_encode(void)
+DECLARE_EC_TEST(test_encode)
 {
-	const uint8_t src1[5] = {0xff, 0x00, 0xff, 0x00, 0xff};
+	const uint8_t src1[5] = { 0xff, 0x00, 0xff, 0x00, 0xff };
 	char enc[32];
 
 	/* Test for enough space; error produces null string */
 	*enc = 1;
-	TEST_ASSERT(base32_encode(enc, 3, src1, 15, 0) == EC_ERROR_INVAL);
-	TEST_ASSERT(*enc == 0);
+	zassert_equal(base32_encode(enc, 3, src1, 15, 0), EC_ERROR_INVAL);
+	zassert_equal(*enc, 0);
 
 	/* Empty source */
 	ENCTEST("\x00", 0, 0, "");
@@ -104,9 +104,9 @@ static int test_encode(void)
 	/* CRC requires exact multiple of symbol count */
 	ENCTEST("\xff\x00\xff\x00\xff", 40, 4, "96ARU8AH9D");
 	ENCTEST("\xff\x00\xff\x00\xff", 40, 8, "96AR8AH9L");
-	TEST_ASSERT(
-	    base32_encode(enc, 16, (uint8_t *)"\xff\x00\xff\x00\xff", 40, 6)
-	    == EC_ERROR_INVAL);
+	zassert_equal(base32_encode(enc, 16, (uint8_t *)"\xff\x00\xff\x00\xff",
+				    40, 6),
+		      EC_ERROR_INVAL, NULL);
 	/* But what matters is symbol count, not bit count */
 	ENCTEST("\xff\x00\xff\x00\xfe", 39, 4, "96ARU8AH8P");
 
@@ -139,15 +139,15 @@ static int dectest(const void *dec, int decbits, int crc_every, const char *enc)
 	int wantbits = decbits > 0 ? decbits : 5 * strlen(enc);
 	int gotbits = base32_decode(dest, destbits, enc, crc_every);
 
-	TEST_ASSERT(gotbits == wantbits);
+	zassert_equal(gotbits, wantbits);
 	if (gotbits != wantbits)
 		return -1;
 	return cmpbytes(dec, dest, (decbits + 7) / 8, "decode");
 }
 
-#define DECTEST(a, b, c, d) TEST_ASSERT(dectest(a, b, c, d) == 0)
+#define DECTEST(a, b, c, d) zassert_equal(dectest(a, b, c, d), 0, NULL)
 
-static int test_decode(void)
+DECLARE_EC_TEST(test_decode)
 {
 	uint8_t dec[32];
 
@@ -165,7 +165,7 @@ static int test_decode(void)
 	DECTEST("\xff\x00\xff\x00\xff", 40, 0, " 96\tA-R\r8A H9\n");
 
 	/* Invalid symbol fails */
-	TEST_ASSERT(base32_decode(dec, 16, "AI", 0) == -1);
+	zassert_equal(base32_decode(dec, 16, "AI", 0), -1);
 
 	/* If dest buffer is big, use all the source bits */
 	DECTEST("", 0, 0, "");
@@ -186,25 +186,25 @@ static int test_decode(void)
 	DECTEST("\xff\x00\xff\x00\xff", 40, 8, "96AR8AH9L");
 
 	/* CRC requires exact multiple of symbol count */
-	TEST_ASSERT(base32_decode(dec, 40, "96ARL8AH9", 4) == -1);
+	zassert_equal(base32_decode(dec, 40, "96ARL8AH9", 4), -1);
 	/* But what matters is symbol count, not bit count */
 	DECTEST("\xff\x00\xff\x00\xfe", 39, 4, "96ARU8AH8P");
 
 	/* Detect errors in data, CRC, and transposition */
-	TEST_ASSERT(base32_decode(dec, 40, "96AQL", 4) == -1);
-	TEST_ASSERT(base32_decode(dec, 40, "96ARM", 4) == -1);
-	TEST_ASSERT(base32_decode(dec, 40, "96RAL", 4) == -1);
+	zassert_equal(base32_decode(dec, 40, "96AQL", 4), -1);
+	zassert_equal(base32_decode(dec, 40, "96ARM", 4), -1);
+	zassert_equal(base32_decode(dec, 40, "96RAL", 4), -1);
+
+	/* Detect error when not enough data is given */
+	zassert_equal(base32_decode(dec, 40, "AA", 4), -1, NULL);
 
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+TEST_MAIN()
 {
-	test_reset();
-
-	RUN_TEST(test_crc5);
-	RUN_TEST(test_encode);
-	RUN_TEST(test_decode);
-
-	test_print_result();
+	ztest_test_suite(test_base32_lib, ztest_unit_test(test_crc5),
+			 ztest_unit_test(test_encode),
+			 ztest_unit_test(test_decode));
+	ztest_run_test_suite(test_base32_lib);
 }
diff --git a/test/base32.tasklist b/test/base32.tasklist
index 7150f17cbd..6373a70ab1 100644
--- a/test/base32.tasklist
+++ b/test/base32.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/battery_config.c b/test/battery_config.c
new file mode 100644
index 0000000000..2e25f391ad
--- /dev/null
+++ b/test/battery_config.c
@@ -0,0 +1,406 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Test battery info in CBI
+ */
+
+#include "battery_fuel_gauge.h"
+#include "common.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "ec_commands.h"
+#include "test_util.h"
+#include "util.h"
+#include "write_protect.h"
+
+int batt_conf_read(enum cbi_data_tag tag, uint8_t *data, uint8_t size);
+int batt_conf_read_ship_mode(struct board_batt_params *info);
+int batt_conf_read_sleep_mode(struct board_batt_params *info);
+int batt_conf_read_fet_info(struct board_batt_params *info);
+int batt_conf_read_fuel_gauge_info(struct board_batt_params *info);
+int batt_conf_read_battery_info(struct board_batt_params *info);
+void batt_conf_main(void);
+
+struct board_batt_params default_battery_conf = {};
+
+static bool init_battery_type_called;
+static bool board_batt_conf_enabled_return = true;
+
+void init_battery_type(void)
+{
+	init_battery_type_called = true;
+}
+
+__override bool board_batt_conf_enabled(void)
+{
+	return board_batt_conf_enabled_return;
+}
+
+static struct board_batt_params conf_in_cbi = {
+	.fuel_gauge = {
+		.manuf_name = "abc",
+		.device_name = "xyz",
+		.ship_mode = {
+			.reg_addr = 0xaa,
+			.reg_data = {
+				[0] = 0x89ab,
+				[1] = 0xcdef,
+			},
+		},
+	},
+	.batt_info = {
+		.voltage_max = 8400,
+		.voltage_normal = 7400,
+		.voltage_min = 6000,
+		.precharge_current = 64, /* mA */
+		.start_charging_min_c = 0,
+		.start_charging_max_c = 50,
+		.charging_min_c = 0,
+		.charging_max_c = 50,
+		.discharging_min_c = -20,
+		.discharging_max_c = 60,
+	},
+};
+
+static void test_setup(void)
+{
+	/* Make sure that write protect is disabled */
+	write_protect_set(0);
+
+	cbi_create();
+	cbi_write();
+
+	memset(&default_battery_conf, 0, sizeof(default_battery_conf));
+}
+
+static void test_teardown(void)
+{
+}
+
+DECLARE_EC_TEST(test_batt_conf_read)
+{
+	struct ship_mode_info *info = &conf_in_cbi.fuel_gauge.ship_mode;
+	struct ship_mode_info *dflt =
+		&default_battery_conf.fuel_gauge.ship_mode;
+	enum cbi_data_tag tag;
+
+	/* Program data in invalid size. */
+	tag = CBI_TAG_BATT_SHIP_MODE_REG_ADDR;
+	zassert_equal(cbi_set_board_info(tag, &info->reg_addr,
+					 sizeof(info->reg_addr) + 1),
+		      EC_SUCCESS);
+
+	/* Read */
+	zassert_equal(batt_conf_read(tag, &dflt->reg_addr,
+				     sizeof(dflt->reg_addr)),
+		      EC_ERROR_INVAL);
+
+	return EC_SUCCESS;
+}
+
+DECLARE_EC_TEST(test_read_ship_mode)
+{
+	struct ship_mode_info *info = &conf_in_cbi.fuel_gauge.ship_mode;
+	struct ship_mode_info *dflt =
+		&default_battery_conf.fuel_gauge.ship_mode;
+	enum cbi_data_tag tag;
+	uint8_t d8;
+
+	/* Read without data in CBI. Test ERROR_UNKNOWN is correctly ignored. */
+	zassert_equal(batt_conf_read_ship_mode(&default_battery_conf),
+		      EC_SUCCESS);
+
+	/* Validate default info remains unchanged. */
+	zassert_equal(dflt->reg_addr, 0);
+	zassert_equal(dflt->reg_data[0], 0);
+	zassert_equal(dflt->reg_data[1], 0);
+	zassert_equal(dflt->wb_support, 0);
+
+	tag = CBI_TAG_BATT_SHIP_MODE_FLAGS;
+	d8 = BIT(0);
+	zassert_equal(cbi_set_board_info(tag, &d8, sizeof(d8)), EC_SUCCESS);
+	tag = CBI_TAG_BATT_SHIP_MODE_REG_ADDR;
+	zassert_equal(cbi_set_board_info(tag, &info->reg_addr,
+					 sizeof(info->reg_addr)),
+		      EC_SUCCESS);
+	tag = CBI_TAG_BATT_SHIP_MODE_REG_DATA;
+	zassert_equal(cbi_set_board_info(tag, (uint8_t *)&info->reg_data,
+					 sizeof(info->reg_data)),
+		      EC_SUCCESS);
+
+	/* Read */
+	zassert_equal(batt_conf_read_ship_mode(&default_battery_conf),
+		      EC_SUCCESS);
+
+	/* Validate default info == info in cbi. */
+	zassert_equal(dflt->reg_addr, info->reg_addr);
+	zassert_equal(dflt->reg_data[0], info->reg_data[0]);
+	zassert_equal(dflt->reg_data[1], info->reg_data[1]);
+	zassert_equal(dflt->wb_support, 1);
+
+	return EC_SUCCESS;
+}
+
+DECLARE_EC_TEST(test_read_sleep_mode)
+{
+	struct sleep_mode_info *info = &conf_in_cbi.fuel_gauge.sleep_mode;
+	struct sleep_mode_info *dflt =
+		&default_battery_conf.fuel_gauge.sleep_mode;
+	enum cbi_data_tag tag;
+	uint8_t d8;
+
+	/* Read without data in CBI. Test ERROR_UNKNOWN is correctly ignored. */
+	zassert_equal(batt_conf_read_sleep_mode(&default_battery_conf),
+		      EC_SUCCESS);
+
+	/* Validate default info remains unchanged. */
+	zassert_equal(dflt->reg_addr, 0);
+	zassert_equal(dflt->reg_data, 0);
+	zassert_equal(dflt->sleep_supported, 0);
+
+	tag = CBI_TAG_BATT_SLEEP_MODE_FLAGS;
+	d8 = BIT(0);
+	zassert_equal(cbi_set_board_info(tag, &d8, sizeof(d8)), EC_SUCCESS);
+	tag = CBI_TAG_BATT_SLEEP_MODE_REG_ADDR;
+	zassert_equal(cbi_set_board_info(tag, &info->reg_addr,
+					 sizeof(info->reg_addr)),
+		      EC_SUCCESS);
+	tag = CBI_TAG_BATT_SLEEP_MODE_REG_DATA;
+	zassert_equal(cbi_set_board_info(tag, (uint8_t *)&info->reg_data,
+					 sizeof(info->reg_data)),
+		      EC_SUCCESS);
+
+	/* Read */
+	zassert_equal(batt_conf_read_sleep_mode(&default_battery_conf),
+		      EC_SUCCESS);
+
+	/* Validate default info == info in cbi. */
+	zassert_equal(dflt->reg_addr, info->reg_addr);
+	zassert_equal(dflt->reg_data, info->reg_data);
+	zassert_equal(dflt->sleep_supported, 1);
+
+	return EC_SUCCESS;
+}
+
+DECLARE_EC_TEST(test_read_fet_info)
+{
+	struct fet_info *info = &conf_in_cbi.fuel_gauge.fet;
+	struct fet_info *dflt = &default_battery_conf.fuel_gauge.fet;
+	enum cbi_data_tag tag;
+	uint8_t d8;
+
+	/* Read without data in CBI. Test ERROR_UNKNOWN is correctly ignored. */
+	zassert_equal(batt_conf_read_fet_info(&default_battery_conf),
+		      EC_SUCCESS);
+
+	/* Validate default info remains unchanged. */
+	zassert_equal(dflt->reg_addr, 0);
+	zassert_equal(dflt->reg_mask, 0);
+	zassert_equal(dflt->mfgacc_support, 0);
+
+	tag = CBI_TAG_BATT_FET_FLAGS;
+	d8 = BIT(0);
+	zassert_equal(cbi_set_board_info(tag, &d8, sizeof(d8)), EC_SUCCESS);
+	tag = CBI_TAG_BATT_FET_REG_ADDR;
+	zassert_equal(cbi_set_board_info(tag, &info->reg_addr,
+					 sizeof(info->reg_addr)),
+		      EC_SUCCESS);
+	tag = CBI_TAG_BATT_FET_REG_MASK;
+	zassert_equal(cbi_set_board_info(tag, (uint8_t *)&info->reg_mask,
+					 sizeof(info->reg_mask)),
+		      EC_SUCCESS);
+	tag = CBI_TAG_BATT_FET_DISCONNECT_VAL;
+	zassert_equal(cbi_set_board_info(tag, (uint8_t *)&info->disconnect_val,
+					 sizeof(info->disconnect_val)),
+		      EC_SUCCESS);
+	tag = CBI_TAG_BATT_FET_CFET_MASK;
+	zassert_equal(cbi_set_board_info(tag, (uint8_t *)&info->cfet_mask,
+					 sizeof(info->cfet_mask)),
+		      EC_SUCCESS);
+	tag = CBI_TAG_BATT_FET_CFET_OFF_VAL;
+	zassert_equal(cbi_set_board_info(tag, (uint8_t *)&info->cfet_off_val,
+					 sizeof(info->cfet_off_val)),
+		      EC_SUCCESS);
+
+	/* Read */
+	zassert_equal(batt_conf_read_fet_info(&default_battery_conf),
+		      EC_SUCCESS);
+
+	zassert_equal(dflt->reg_addr, info->reg_addr);
+	zassert_equal(dflt->reg_mask, info->reg_mask);
+	zassert_equal(dflt->mfgacc_support, 1);
+
+	return EC_SUCCESS;
+}
+
+DECLARE_EC_TEST(test_read_fuel_gauge_info)
+{
+	struct fuel_gauge_info *info = &conf_in_cbi.fuel_gauge;
+	struct fuel_gauge_info *dflt = &default_battery_conf.fuel_gauge;
+	enum cbi_data_tag tag;
+	uint8_t d8;
+
+	/* Read without data in CBI. Test ERROR_UNKNOWN is correctly ignored. */
+	zassert_equal(batt_conf_read_fuel_gauge_info(&default_battery_conf),
+		      EC_SUCCESS);
+
+	/* Validate default info remains unchanged. */
+	zassert_is_null(dflt->manuf_name);
+	zassert_is_null(dflt->device_name);
+	zassert_equal(dflt->override_nil, 0);
+
+	tag = CBI_TAG_FUEL_GAUGE_MANUF_NAME;
+	zassert_equal(cbi_set_board_info(tag, (uint8_t *)info->manuf_name,
+					 strlen(info->manuf_name)),
+		      EC_SUCCESS);
+	tag = CBI_TAG_FUEL_GAUGE_DEVICE_NAME;
+	zassert_equal(cbi_set_board_info(tag, (uint8_t *)info->device_name,
+					 strlen(info->device_name)),
+		      EC_SUCCESS);
+	tag = CBI_TAG_FUEL_GAUGE_FLAGS;
+	d8 = BIT(0);
+	zassert_equal(cbi_set_board_info(tag, &d8, sizeof(d8)), EC_SUCCESS);
+
+	/* Read */
+	zassert_equal(batt_conf_read_fuel_gauge_info(&default_battery_conf),
+		      EC_SUCCESS);
+
+	/* Validate default info == info in cbi. */
+	zassert_equal(strncmp(dflt->manuf_name, info->manuf_name,
+			      strlen(info->manuf_name)),
+		      0);
+	zassert_equal(strncmp(dflt->device_name, info->device_name,
+			      strlen(info->device_name)),
+		      0);
+	zassert_equal(dflt->override_nil, 1);
+
+	return EC_SUCCESS;
+}
+
+DECLARE_EC_TEST(test_read_battery_info)
+{
+	struct battery_info *info = &conf_in_cbi.batt_info;
+	struct battery_info *dflt = &default_battery_conf.batt_info;
+	enum cbi_data_tag tag;
+
+	/* Read without data in CBI. Test ERROR_UNKNOWN is correctly ignored. */
+	zassert_equal(batt_conf_read_battery_info(&default_battery_conf),
+		      EC_SUCCESS);
+
+	/* Validate default info remains unchanged. */
+	zassert_equal(dflt->voltage_min, 0);
+	zassert_equal(dflt->voltage_normal, 0);
+	zassert_equal(dflt->voltage_max, 0);
+	zassert_equal(dflt->precharge_voltage, 0);
+	zassert_equal(dflt->precharge_current, 0);
+	zassert_equal(dflt->start_charging_min_c, 0);
+	zassert_equal(dflt->start_charging_max_c, 0);
+	zassert_equal(dflt->charging_min_c, 0);
+	zassert_equal(dflt->charging_max_c, 0);
+	zassert_equal(dflt->discharging_min_c, 0);
+	zassert_equal(dflt->discharging_max_c, 0);
+
+	tag = CBI_TAG_BATT_VOLTAGE_MIN;
+	zassert_equal(cbi_set_board_info(tag, (uint8_t *)&info->voltage_min,
+					 sizeof(info->voltage_min)),
+		      EC_SUCCESS);
+	tag = CBI_TAG_BATT_VOLTAGE_NORMAL;
+	zassert_equal(cbi_set_board_info(tag, (uint8_t *)&info->voltage_normal,
+					 sizeof(info->voltage_normal)),
+		      EC_SUCCESS);
+	tag = CBI_TAG_BATT_VOLTAGE_MAX;
+	zassert_equal(cbi_set_board_info(tag, (uint8_t *)&info->voltage_max,
+					 sizeof(info->voltage_max)),
+		      EC_SUCCESS);
+	tag = CBI_TAG_BATT_PRECHARGE_VOLTAGE;
+	zassert_equal(cbi_set_board_info(tag,
+					 (uint8_t *)&info->precharge_voltage,
+					 sizeof(info->precharge_voltage)),
+		      EC_SUCCESS);
+	tag = CBI_TAG_BATT_PRECHARGE_CURRENT;
+	zassert_equal(cbi_set_board_info(tag,
+					 (uint8_t *)&info->precharge_current,
+					 sizeof(info->precharge_current)),
+		      EC_SUCCESS);
+	tag = CBI_TAG_BATT_START_CHARGING_MIN_C;
+	zassert_equal(cbi_set_board_info(tag,
+					 (uint8_t *)&info->start_charging_min_c,
+					 sizeof(info->start_charging_min_c)),
+		      EC_SUCCESS);
+	tag = CBI_TAG_BATT_START_CHARGING_MAX_C;
+	zassert_equal(cbi_set_board_info(tag,
+					 (uint8_t *)&info->start_charging_max_c,
+					 sizeof(info->start_charging_max_c)),
+		      EC_SUCCESS);
+	tag = CBI_TAG_BATT_CHARGING_MIN_C;
+	zassert_equal(cbi_set_board_info(tag, (uint8_t *)&info->charging_min_c,
+					 sizeof(info->charging_min_c)),
+		      EC_SUCCESS);
+	tag = CBI_TAG_BATT_CHARGING_MAX_C;
+	zassert_equal(cbi_set_board_info(tag, (uint8_t *)&info->charging_max_c,
+					 sizeof(info->charging_max_c)),
+		      EC_SUCCESS);
+	tag = CBI_TAG_BATT_DISCHARGING_MIN_C;
+	zassert_equal(cbi_set_board_info(tag,
+					 (uint8_t *)&info->discharging_min_c,
+					 sizeof(info->discharging_min_c)),
+		      EC_SUCCESS);
+	tag = CBI_TAG_BATT_DISCHARGING_MAX_C;
+	zassert_equal(cbi_set_board_info(tag,
+					 (uint8_t *)&info->discharging_max_c,
+					 sizeof(info->discharging_max_c)),
+		      EC_SUCCESS);
+
+	/* Read */
+	zassert_equal(batt_conf_read_battery_info(&default_battery_conf),
+		      EC_SUCCESS);
+
+	/* Validate default info == info in cbi. */
+	zassert_equal(dflt->voltage_min, info->voltage_min);
+	zassert_equal(dflt->voltage_normal, info->voltage_normal);
+	zassert_equal(dflt->voltage_max, info->voltage_max);
+	zassert_equal(dflt->precharge_voltage, info->precharge_voltage);
+	zassert_equal(dflt->precharge_current, info->precharge_current);
+	zassert_equal(dflt->start_charging_min_c, info->start_charging_min_c);
+	zassert_equal(dflt->start_charging_max_c, info->start_charging_max_c);
+	zassert_equal(dflt->charging_min_c, info->charging_min_c);
+	zassert_equal(dflt->charging_max_c, info->charging_max_c);
+	zassert_equal(dflt->discharging_min_c, info->discharging_min_c);
+	zassert_equal(dflt->discharging_max_c, info->discharging_max_c);
+
+	return EC_SUCCESS;
+}
+
+DECLARE_EC_TEST(test_batt_conf_main)
+{
+	board_batt_conf_enabled_return = false;
+
+	/* Rerun main. */
+	batt_conf_main();
+
+	zassert_equal(init_battery_type_called, true);
+
+	return EC_SUCCESS;
+}
+
+TEST_SUITE(test_suite_battery_config)
+{
+	ztest_test_suite(
+		test_battery_config,
+		ztest_unit_test_setup_teardown(test_batt_conf_read, test_setup,
+					       test_teardown),
+		ztest_unit_test_setup_teardown(test_read_ship_mode, test_setup,
+					       test_teardown),
+		ztest_unit_test_setup_teardown(test_read_sleep_mode, test_setup,
+					       test_teardown),
+		ztest_unit_test_setup_teardown(test_read_fet_info, test_setup,
+					       test_teardown),
+		ztest_unit_test_setup_teardown(test_read_fuel_gauge_info,
+					       test_setup, test_teardown),
+		ztest_unit_test_setup_teardown(test_read_battery_info,
+					       test_setup, test_teardown),
+		ztest_unit_test_setup_teardown(test_batt_conf_main, test_setup,
+					       test_teardown));
+	ztest_run_test_suite(test_battery_config);
+}
diff --git a/test/battery_config.tasklist b/test/battery_config.tasklist
new file mode 100644
index 0000000000..f1132f8819
--- /dev/null
+++ b/test/battery_config.tasklist
@@ -0,0 +1,9 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST  /* No test task */
diff --git a/test/battery_get_params_smart.c b/test/battery_get_params_smart.c
index 3163fb587e..f63003d8d9 100644
--- a/test/battery_get_params_smart.c
+++ b/test/battery_get_params_smart.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -18,7 +18,7 @@
 static int fail_on_first, fail_on_last;
 static int read_count, write_count;
 struct batt_params batt;
-
+static int cmd_to_fail;
 
 void battery_compensate_params(struct batt_params *batt)
 {
@@ -28,15 +28,21 @@ void board_battery_compensate_params(struct batt_params *batt)
 {
 }
 
-static void reset_and_fail_on(int first, int last)
+static void reset_counters(int first, int last)
 {
-	/* We're not initializing the fake battery, so everything reads zero */
-	memset(&batt, 0, sizeof(typeof(batt)));
 	read_count = write_count = 0;
 	fail_on_first = first;
 	fail_on_last = last;
 }
 
+static void reset_and_fail_on(int first, int last, int cmd)
+{
+	/* We're not initializing the fake battery, so everything reads zero */
+	memset(&batt, 0, sizeof(typeof(batt)));
+	cmd_to_fail = cmd;
+	reset_counters(first, last);
+}
+
 /* Mocked functions */
 int sb_read(int cmd, int *param)
 {
@@ -44,32 +50,35 @@ int sb_read(int cmd, int *param)
 	if (read_count >= fail_on_first && read_count <= fail_on_last)
 		return EC_ERROR_UNKNOWN;
 
-	return i2c_read16(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS,
-			  cmd, param);
+	if (cmd == cmd_to_fail)
+		return EC_ERROR_UNKNOWN;
+
+	return i2c_read16(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS, cmd, param);
 }
+
 int sb_write(int cmd, int param)
 {
 	write_count++;
-	return i2c_write16(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS,
-			   cmd, param);
+	return i2c_write16(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS, cmd, param);
 }
 
-
 /* Tests */
 static int test_param_failures(void)
 {
 	int i, num_reads;
 
 	/* No failures */
-	reset_and_fail_on(0, 0);
+	reset_and_fail_on(0, 0, -1);
 	battery_get_params(&batt);
 	TEST_ASSERT(batt.flags & BATT_FLAG_RESPONSIVE);
 	TEST_ASSERT(!(batt.flags & BATT_FLAG_BAD_ANY));
+
+	/* Save the max number of reads. */
 	num_reads = read_count;
 
 	/* Just a single failure */
 	for (i = 1; i <= num_reads; i++) {
-		reset_and_fail_on(i, i);
+		reset_and_fail_on(i, i, -1);
 		battery_get_params(&batt);
 		TEST_ASSERT(batt.flags & BATT_FLAG_BAD_ANY);
 		TEST_ASSERT(batt.flags & BATT_FLAG_RESPONSIVE);
@@ -77,7 +86,7 @@ static int test_param_failures(void)
 
 	/* Once it fails, it keeps failing */
 	for (i = 1; i <= num_reads; i++) {
-		reset_and_fail_on(i, num_reads);
+		reset_and_fail_on(i, num_reads, -1);
 		battery_get_params(&batt);
 		TEST_ASSERT(batt.flags & BATT_FLAG_BAD_ANY);
 		if (i == 1)
@@ -90,9 +99,155 @@ static int test_param_failures(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+/**
+ * Test if battery_get_params sets a flag properly for a SB command.
+ *
+ * @param cmd   SB command to fail.
+ * @param flag  Flag expected to be set when <cmd> fails.
+ * @return  EC_SUCCESS
+ */
+static int test_flag(int cmd, int flag)
+{
+	reset_and_fail_on(0, 0, cmd);
+	battery_get_params(&batt);
+	TEST_ASSERT(batt.flags & flag);
+	TEST_ASSERT(!((batt.flags & ~flag) & BATT_FLAG_BAD_ANY));
+	TEST_ASSERT(batt.flags & BATT_FLAG_RESPONSIVE);
+
+	/*
+	 * When SB_CHARGING_VOLTAGE, SB_CHARGING_CURRENT, or
+	 * SB_RELATIVE_STATE_OF_CHARGE fails, WANT_CHARGE should be cleared.
+	 */
+	switch (cmd) {
+	case SB_RELATIVE_STATE_OF_CHARGE:
+	case SB_CHARGING_VOLTAGE:
+	case SB_CHARGING_CURRENT:
+		TEST_ASSERT(!(batt.flags & BATT_FLAG_WANT_CHARGE));
+		TEST_ASSERT(batt.desired_voltage == 0);
+		TEST_ASSERT(batt.desired_current == 0);
+		break;
+	default:
+		TEST_ASSERT(batt.flags & BATT_FLAG_WANT_CHARGE);
+		TEST_ASSERT(batt.desired_voltage == 100);
+		TEST_ASSERT(batt.desired_current == 100);
+	}
+
+	/*
+	 * Failure is recovered. <flag> should be cleared. WANT_CHARGE should be
+	 * set.
+	 */
+	cmd_to_fail = -1;
+	battery_get_params(&batt);
+	TEST_ASSERT(!(batt.flags & flag));
+	TEST_ASSERT(batt.flags & BATT_FLAG_WANT_CHARGE);
+
+	return EC_SUCCESS;
+}
+
+static int test_flags(void)
+{
+	sb_write(SB_CHARGING_VOLTAGE, 100);
+	sb_write(SB_CHARGING_CURRENT, 100);
+	sb_write(SB_RELATIVE_STATE_OF_CHARGE, 50);
+
+	/* Test each command-flag pair. */
+	test_flag(SB_TEMPERATURE, BATT_FLAG_BAD_TEMPERATURE);
+	test_flag(SB_RELATIVE_STATE_OF_CHARGE, BATT_FLAG_BAD_STATE_OF_CHARGE);
+	test_flag(SB_VOLTAGE, BATT_FLAG_BAD_VOLTAGE);
+	test_flag(SB_CURRENT, BATT_FLAG_BAD_CURRENT);
+	test_flag(SB_AVERAGE_CURRENT, BATT_FLAG_BAD_AVERAGE_CURRENT);
+	test_flag(SB_CHARGING_VOLTAGE, BATT_FLAG_BAD_DESIRED_VOLTAGE);
+	test_flag(SB_CHARGING_CURRENT, BATT_FLAG_BAD_DESIRED_CURRENT);
+	test_flag(SB_REMAINING_CAPACITY, BATT_FLAG_BAD_REMAINING_CAPACITY);
+	test_flag(SB_FULL_CHARGE_CAPACITY, BATT_FLAG_BAD_FULL_CAPACITY);
+	test_flag(SB_BATTERY_STATUS, BATT_FLAG_BAD_STATUS);
+
+	/*
+	 * Volatile flags should be cleared and other flags should be preserved.
+	 */
+	reset_and_fail_on(0, 0, -1);
+	batt.flags |= BATT_FLAG_BAD_TEMPERATURE;
+	batt.flags |= BATT_FLAG_DEEP_CHARGE;
+	battery_get_params(&batt);
+	TEST_ASSERT(batt.flags & BATT_FLAG_DEEP_CHARGE);
+	TEST_ASSERT(!(batt.flags & BATT_FLAG_BAD_ANY));
+
+	/*
+	 * All reads succeed. BATT_FLAG_RESPONSIVE should be set. Then, all
+	 * reads fail. BATT_FLAG_RESPONSIVE should be cleared.
+	 */
+	reset_and_fail_on(0, 0, -1);
+	battery_get_params(&batt);
+	TEST_ASSERT(batt.flags & BATT_FLAG_RESPONSIVE);
+
+	reset_counters(1, read_count);
+	battery_get_params(&batt);
+	TEST_ASSERT(!(batt.flags & BATT_FLAG_RESPONSIVE));
+
+	/* Test WANT_CHARGE is explicitly cleared. */
+	reset_and_fail_on(0, 0, SB_RELATIVE_STATE_OF_CHARGE);
+	batt.flags |= BATT_FLAG_WANT_CHARGE;
+	battery_get_params(&batt);
+	TEST_ASSERT(!(batt.flags & BATT_FLAG_WANT_CHARGE));
+
+	return EC_SUCCESS;
+}
+
+static int test_full_state_of_charge(void)
+{
+	/*
+	 * When SoC is full, BATT_FLAG_WANT_CHARGE should be cleared and
+	 * desired voltage and current are also cleared.
+	 */
+	sb_write(SB_CHARGING_VOLTAGE, 100);
+	sb_write(SB_CHARGING_CURRENT, 100);
+	sb_write(SB_RELATIVE_STATE_OF_CHARGE, 100);
+
+	reset_and_fail_on(0, 0, -1);
+	battery_get_params(&batt);
+	TEST_ASSERT(!(batt.flags & BATT_FLAG_WANT_CHARGE));
+	TEST_ASSERT(batt.desired_voltage == 0);
+	TEST_ASSERT(batt.desired_current == 0);
+	TEST_ASSERT(batt.state_of_charge == 100);
+
+	return EC_SUCCESS;
+}
+
+static int test_voltage(void)
+{
+	sb_write(SB_VOLTAGE, 100);
+	reset_and_fail_on(0, 0, -1);
+
+	battery_get_params(&batt);
+	TEST_ASSERT(batt.voltage == 100);
+
+	return EC_SUCCESS;
+}
+
+static int test_current(void)
+{
+	/* Test positive (charge) current. */
+	sb_write(SB_CURRENT, 100);
+	reset_and_fail_on(0, 0, -1);
+	battery_get_params(&batt);
+	TEST_ASSERT(batt.current == 100);
+
+	/* Test negative (discharge) current. */
+	sb_write(SB_CURRENT, -100);
+	reset_and_fail_on(0, 0, -1);
+	battery_get_params(&batt);
+	TEST_ASSERT(batt.current == -100);
+
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
 {
 	RUN_TEST(test_param_failures);
+	RUN_TEST(test_flags);
+	RUN_TEST(test_full_state_of_charge);
+	RUN_TEST(test_voltage);
+	RUN_TEST(test_current);
 
 	test_print_result();
 }
diff --git a/test/battery_get_params_smart.tasklist b/test/battery_get_params_smart.tasklist
index c2eb8159a9..efcc6883a5 100644
--- a/test/battery_get_params_smart.tasklist
+++ b/test/battery_get_params_smart.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/benchmark.cc b/test/benchmark.cc
new file mode 100644
index 0000000000..9b4017db3a
--- /dev/null
+++ b/test/benchmark.cc
@@ -0,0 +1,162 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Simple test to validate the benchmark library.
+ */
+
+#include "benchmark.h"
+
+extern "C" {
+#include "test_util.h"
+}
+
+/* Sample function for the benchmark */
+static void float_mult()
+{
+	float a = 1.1;
+	float b = 1.1;
+	int i;
+
+	for (i = 0; i < 1000; ++i)
+		a *= b;
+}
+
+test_static int test_valid_benchmark()
+{
+	Benchmark benchmark;
+
+	auto result = benchmark.run("float_mult", float_mult);
+	TEST_ASSERT(result.has_value());
+
+	benchmark.print_results();
+	return EC_SUCCESS;
+}
+
+test_static int test_num_iterations()
+{
+	Benchmark benchmark({ .num_iterations = 5 });
+	int num_calls = 0;
+
+	auto result = benchmark.run("call_counter", [&] { ++num_calls; });
+	TEST_ASSERT(result.has_value());
+	TEST_EQ(num_calls, 5, "%d");
+
+	benchmark.print_results();
+	return EC_SUCCESS;
+}
+
+test_static int test_multiple_benchmarks()
+{
+	// Use two separate instances with different settings
+	Benchmark benchmark1({ .num_iterations = 5 });
+	Benchmark benchmark2({ .num_iterations = 3 });
+	int num_calls = 0;
+
+	auto result1 = benchmark1.run("call_counter1", [&] { ++num_calls; });
+	TEST_ASSERT(result1.has_value());
+	TEST_EQ(num_calls, 5, "%d");
+
+	num_calls = 0;
+	auto result2 = benchmark2.run("call_counter2", [&] { ++num_calls; });
+	TEST_ASSERT(result2.has_value());
+	TEST_EQ(num_calls, 3, "%d");
+
+	benchmark1.print_results();
+	benchmark2.print_results();
+	return EC_SUCCESS;
+}
+
+test_static int test_long_benchmark()
+{
+	Benchmark benchmark({ .num_iterations = 100 });
+	int num_calls = 0;
+
+	auto result = benchmark.run("call_counter", [&] {
+		++num_calls;
+		udelay(10000);
+	});
+	TEST_ASSERT(result.has_value());
+	TEST_EQ(num_calls, 100, "%d");
+
+	benchmark.print_results();
+	return EC_SUCCESS;
+}
+
+test_static int test_result_comparison()
+{
+	constexpr auto result1 = BenchmarkResult{
+		.name = "implementation1",
+		.elapsed_time = 10000,
+		.average_time = 100,
+		.min_time = 10,
+		.max_time = 200,
+	};
+
+	constexpr auto result2 = BenchmarkResult{
+		.name = "implementation2",
+		.elapsed_time = 8000,
+		.average_time = 80,
+		.min_time = 13,
+		.max_time = 150,
+	};
+
+	BenchmarkResult::compare(result1, result2);
+	return EC_SUCCESS;
+}
+
+test_static int test_empty_benchmark_name()
+{
+	Benchmark benchmark;
+	TEST_ASSERT(!benchmark.run("", [] {}).has_value());
+	return EC_SUCCESS;
+}
+
+test_static int test_too_many_runs()
+{
+	auto benchmark = Benchmark<3>();
+	TEST_ASSERT(benchmark.run("call_1", [] {}).has_value());
+	TEST_ASSERT(benchmark.run("call_2", [] {}).has_value());
+	TEST_ASSERT(benchmark.run("call_3", [] {}).has_value());
+	TEST_ASSERT(!benchmark.run("call_4", [] {}).has_value());
+
+	return EC_SUCCESS;
+}
+
+test_static int test_min_max_time()
+{
+	// Run test 3 times with increasing delay of 1ms, 2ms, and 4ms
+	Benchmark benchmark({ .num_iterations = 3 });
+	int delay_us = 1000;
+
+	auto result = benchmark.run("delay", [&delay_us] {
+		udelay(delay_us);
+		delay_us *= 2;
+	});
+	TEST_ASSERT(result.has_value());
+
+	auto min_time = result.value().min_time;
+	auto max_time = result.value().max_time;
+
+	TEST_GE(min_time, 995U, "%u");
+	TEST_LE(min_time, 1005U, "%u");
+	TEST_GE(max_time, 3995U, "%u");
+	TEST_LE(max_time, 4005U, "%u");
+
+	benchmark.print_results();
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
+{
+	test_reset();
+	RUN_TEST(test_valid_benchmark);
+	RUN_TEST(test_num_iterations);
+	RUN_TEST(test_multiple_benchmarks);
+	RUN_TEST(test_long_benchmark);
+	RUN_TEST(test_result_comparison);
+	RUN_TEST(test_too_many_runs);
+	RUN_TEST(test_empty_benchmark_name);
+	RUN_TEST(test_min_max_time);
+	test_print_result();
+}
diff --git a/test/benchmark.tasklist b/test/benchmark.tasklist
new file mode 100644
index 0000000000..6d43377af5
--- /dev/null
+++ b/test/benchmark.tasklist
@@ -0,0 +1,9 @@
+/* Copyright 2022 The ChromiumOS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST
diff --git a/test/bklight_lid.c b/test/bklight_lid.c
index 99167a71a6..52fc91f677 100644
--- a/test/bklight_lid.c
+++ b/test/bklight_lid.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -95,7 +95,7 @@ static int test_hostcommand(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/bklight_lid.tasklist b/test/bklight_lid.tasklist
index da0ab6211a..100cb6b5bd 100644
--- a/test/bklight_lid.tasklist
+++ b/test/bklight_lid.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/bklight_passthru.c b/test/bklight_passthru.c
index 170cc734cd..2bba2fe713 100644
--- a/test/bklight_passthru.c
+++ b/test/bklight_passthru.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -129,7 +129,7 @@ static int test_hostcommand(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/bklight_passthru.tasklist b/test/bklight_passthru.tasklist
index da0ab6211a..100cb6b5bd 100644
--- a/test/bklight_passthru.tasklist
+++ b/test/bklight_passthru.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/body_detection.c b/test/body_detection.c
index 48fefce249..e1015f5a72 100644
--- a/test/body_detection.c
+++ b/test/body_detection.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,11 +19,9 @@ static const int window_size = 50; /* sensor data rate (Hz) */
 
 static int filler(const struct motion_sensor_t *s, const float v)
 {
-	int resolution = s->drv->get_resolution(s);
-	int range = s->drv->get_range(s);
-	int data_1g = BIT(resolution - 1) / range;
+	int data_1g = MOTION_SCALING_FACTOR / s->current_range;
 
-	return (int)(v * data_1g / 9.8);
+	return (int)(v * data_1g / MOTION_ONE_G);
 }
 
 static void feed_body_detect_data(const struct body_detect_test_data *array,
@@ -46,7 +44,7 @@ static int get_trigger_time(const struct body_detect_test_data *data,
 	 * that we do not need to wait for 15 second if the testcase
 	 * is in off-body initially.
 	 */
-	body_detect_change_state(BODY_DETECTION_OFF_BODY);
+	body_detect_change_state(BODY_DETECTION_OFF_BODY, false);
 	for (i = 0; i < size; ++i) {
 		enum body_detect_states motion_state;
 
@@ -106,8 +104,7 @@ static int test_body_detect(void)
 	return EC_SUCCESS;
 }
 
-
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/body_detection.tasklist b/test/body_detection.tasklist
index 95a30e9973..7926640d53 100644
--- a/test/body_detection.tasklist
+++ b/test/body_detection.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/body_detection_data_literals.c b/test/body_detection_data_literals.c
index 96a0cc2f8f..cafe1d6ade 100644
--- a/test/body_detection_data_literals.c
+++ b/test/body_detection_data_literals.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,6208 +6,6208 @@
 
 const struct body_detect_test_data kBodyDetectOnBodyTestData[] = {
 	/*       x,		y,		z, action*/
-	{3.233367f,	1.968032f,	8.875299f,	0},
-	{3.190272f,	2.127247f,	9.054865f,	0},
-	{3.361457f,	2.057815f,	9.054865f,	0},
-	{3.377019f,	1.917754f,	9.093172f,	0},
-	{3.460816f,	1.817198f,	9.058456f,	0},
-	{3.500320f,	1.726218f,	8.900438f,	0},
-	{3.715799f,	1.363497f,	8.836992f,	0},
-	{3.883393f,	0.884657f,	8.832204f,	0},
-	{3.948036f,	0.577002f,	9.016558f,	0},
-	{3.600877f,	0.717063f,	9.200911f,	0},
-	{3.318361f,	0.854729f,	9.166195f,	0},
-	{3.272871f,	0.731428f,	9.149436f,	0},
-	{3.452436f,	0.250194f,	9.297876f,	0},
-	{3.817552f,	-0.353144f,	9.424768f,	0},
-	{3.828326f,	-0.495599f,	9.284708f,	0},
-	{3.312376f,	-0.040701f,	9.204502f,	0},
-	{3.049014f,	0.515950f,	9.223656f,	0},
-	{3.099292f,	0.980425f,	8.882483f,	0},
-	{3.153162f,	1.443703f,	8.154645f,	0},
-	{3.501518f,	1.487995f,	8.054089f,	0},
-	{4.235340f,	1.292868f,	8.480257f,	0},
-	{4.284421f,	1.511937f,	8.848964f,	0},
-	{3.988737f,	1.928528f,	9.149436f,	0},
-	{3.825932f,	2.076969f,	9.576800f,	0},
-	{3.903743f,	1.991974f,	10.133451f,	0},
-	{3.841494f,	2.000354f,	10.165773f,	0},
-	{3.706222f,	1.930922f,	9.649823f,	0},
-	{3.949233f,	1.614888f,	9.054865f,	0},
-	{4.237734f,	1.272517f,	8.625106f,	0},
-	{4.188653f,	1.134851f,	8.268370f,	0},
-	{4.242523f,	0.991199f,	8.091199f,	0},
-	{4.157528f,	0.970848f,	8.135491f,	0},
-	{3.951627f,	0.967257f,	8.353364f,	0},
-	{4.073731f,	0.994790f,	8.854949f,	0},
-	{3.840297f,	1.124077f,	9.249992f,	0},
-	{3.736149f,	1.142033f,	9.491806f,	0},
-	{3.809172f,	1.126471f,	9.651020f,	0},
-	{3.987540f,	1.173158f,	9.633064f,	0},
-	{4.237734f,	1.005564f,	9.467864f,	0},
-	{4.308363f,	0.939724f,	9.190137f,	0},
-	{4.367021f,	0.986410f,	9.021346f,	0},
-	{4.406525f,	1.033097f,	9.074018f,	0},
-	{4.185062f,	1.276109f,	9.235627f,	0},
-	{3.971978f,	1.363497f,	9.525325f,	0},
-	{4.031833f,	1.318007f,	10.833755f,	0},
-	{4.214989f,	1.144428f,	10.241191f,	0},
-	{4.808751f,	0.590170f,	9.690525f,	0},
-	{4.697421f,	0.372298f,	10.245979f,	0},
-	{4.490322f,	0.207098f,	9.682145f,	0},
-	{4.353853f,	0.494402f,	8.651442f,	0},
-	{3.981555f,	1.094149f,	8.230062f,	0},
-	{3.933671f,	1.310825f,	8.426387f,	0},
-	{4.107250f,	1.189917f,	9.068033f,	0},
-	{4.529827f,	0.888248f,	9.501383f,	0},
-	{4.699815f,	0.720654f,	9.765942f,	0},
-	{4.661508f,	0.647631f,	9.916777f,	0},
-	{4.627989f,	0.587776f,	9.925157f,	0},
-	{4.413708f,	0.587776f,	9.791081f,	0},
-	{4.369415f,	0.466869f,	9.840162f,	0},
-	{4.412511f,	0.335188f,	9.932339f,	0},
-	{4.234143f,	0.452504f,	9.502580f,	0},
-	{3.817552f,	1.055842f,	8.638274f,	0},
-	{3.130417f,	1.842337f,	7.748828f,	0},
-	{2.511516f,	2.430113f,	7.059299f,	0},
-	{2.267308f,	2.840718f,	6.742067f,	0},
-	{2.082954f,	3.129220f,	6.706154f,	0},
-	{1.653195f,	3.483561f,	6.813893f,	0},
-	{1.053448f,	3.797201f,	7.132322f,	0},
-	{0.333991f,	4.125207f,	7.364560f,	0},
-	{-0.039504f,	4.228158f,	8.018176f,	0},
-	{0.403423f,	3.726573f,	8.789108f,	0},
-	{1.179144f,	3.120840f,	9.289496f,	0},
-	{1.683123f,	2.905362f,	9.911988f,	0},
-	{1.442506f,	3.038240f,	10.551240f,	0},
-	{1.403001f,	2.936486f,	12.229574f,	0},
-	{1.601720f,	2.541443f,	14.815310f,	0},
-	{2.233789f,	2.037464f,	14.715951f,	0},
-	{2.664745f,	1.736992f,	12.216406f,	0},
-	{3.331529f,	1.385045f,	10.475822f,	0},
-	{3.337515f,	1.235407f,	9.133873f,	0},
-	{3.173512f,	1.292868f,	8.406036f,	0},
-	{3.201046f,	1.462856f,	8.306677f,	0},
-	{3.157950f,	1.595734f,	9.011769f,	0},
-	{2.759315f,	1.777694f,	10.049655f,	0},
-	{2.315192f,	2.105699f,	10.682920f,	0},
-	{2.063801f,	2.375046f,	10.832559f,	0},
-	{2.310403f,	2.485180f,	10.688907f,	0},
-	{2.553414f,	2.606087f,	10.153803f,	0},
-	{2.475603f,	2.731782f,	9.356534f,	0},
-	{2.710234f,	2.529472f,	9.297876f,	0},
-	{2.777272f,	2.193087f,	9.394841f,	0},
-	{2.938881f,	1.920148f,	9.531310f,	0},
-	{3.108869f,	1.635239f,	10.534480f,	0},
-	{3.187877f,	1.425746f,	10.899596f,	0},
-	{3.448845f,	1.331175f,	10.508144f,	0},
-	{3.606862f,	1.470039f,	9.440331f,	0},
-	{3.700236f,	1.162384f,	8.781926f,	0},
-	{3.713404f,	0.864306f,	8.845372f,	0},
-	{3.575738f,	0.404620f,	9.610319f,	0},
-	{3.495532f,	-0.130484f,	9.526522f,	0},
-	{3.403355f,	-0.411802f,	8.833401f,	0},
-	{3.203440f,	-0.380678f,	8.850161f,	0},
-	{2.822762f,	-0.191536f,	9.560040f,	0},
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+	{ 0.033519f, 1.243787f, 8.768758f, 0 },
+	{ 0.373495f, 1.514332f, 8.633486f, 0 },
+	{ 0.353144f, 1.561018f, 8.446738f, 0 },
+	{ 0.129287f, 1.313219f, 8.616726f, 0 },
+	{ -0.028730f, 0.976834f, 9.123099f, 0 },
+	{ -0.076614f, 0.966060f, 9.351746f, 0 },
+	{ -0.161609f, 1.165975f, 8.965082f, 0 },
+	{ -0.343568f, 1.641224f, 8.194150f, 0 },
+	{ -0.442927f, 1.661575f, 8.437161f, 0 },
+	{ -0.363918f, 1.365891f, 9.854527f, 0 },
+	{ -0.282516f, 1.326387f, 10.666162f, 0 },
+	{ -0.314837f, 1.443703f, 10.433924f, 0 },
+	{ -0.644040f, 1.332372f, 9.327804f, 0 },
+	{ -0.999579f, 1.479616f, 8.036133f, 0 },
+	{ -0.799663f, 1.452082f, 8.346182f, 0 },
+	{ -0.858321f, 1.567004f, 9.868893f, 0 },
+	{ -0.938526f, 1.495178f, 11.599899f, 0 },
+	{ -1.193509f, 1.498769f, 11.905160f, 0 },
+	{ -1.556230f, 1.338358f, 10.947480f, 0 },
+	{ -1.557427f, 1.256955f, 11.003743f, 0 },
+	{ -1.413775f, 1.060631f, 11.848896f, 0 },
+	{ -1.280897f, 0.922964f, 12.215209f, 0 },
+	{ -1.132457f, 0.927753f, 11.399983f, 0 },
+	{ -1.037886f, 0.881066f, 10.413573f, 0 },
+	{ -0.605733f, 0.897825f, 10.074794f, 0 },
+	{ -0.149638f, 0.872686f, 10.181335f, 0 },
+	{ 0.278924f, 0.933738f, 10.765521f, 0 },
+	{ 0.741005f, 1.137245f, 10.898398f, 0 },
+	{ 1.114500f, 1.398213f, 10.672147f, 0 },
+	{ 1.337161f, 1.841140f, 11.609476f, 0 },
+	{ 1.916557f, 1.922543f, 13.679262f, 0 },
+	{ 2.594116f, 1.768117f, 13.814534f, 0 },
+	{ 3.088518f, 2.280476f, 12.144580f, 0 },
+	{ 3.426100f, 2.173934f, 11.726792f, 0 },
+	{ 3.564964f, 1.717839f, 11.662148f, 0 },
+	{ 3.779245f, 1.653195f, 11.219221f, 0 },
+	{ 3.823538f, 1.709459f, 10.377660f, 0 },
 };
 
 const size_t kBodyDetectOnBodyTestDataLength =
 	ARRAY_SIZE(kBodyDetectOnBodyTestData);
 
 const struct body_detect_test_data kBodyDetectOffOnTestData[] = {
-	{-0.269348,	0.220266,	10.030501,	0},
-	{-0.259771,	0.216675,	10.113101,	0},
-	{-0.253785,	0.213084,	10.096342,	0},
-	{-0.262165,	0.201113,	10.098736,	0},
-	{-0.257377,	0.210690,	10.093947,	0},
-	{-0.253785,	0.202310,	10.096342,	0},
-	{-0.257377,	0.213084,	10.113101,	0},
-	{-0.257377,	0.221464,	10.096342,	0},
-	{-0.262165,	0.217872,	10.115496,	0},
-	{-0.258574,	0.219069,	10.102327,	0},
-	{-0.275333,	0.205901,	10.123875,	0},
-	{-0.262165,	0.209493,	10.085567,	0},
-	{-0.271742,	0.209493,	10.110707,	0},
-	{-0.275333,	0.220266,	10.096342,	0},
-	{-0.251391,	0.210690,	10.097539,	0},
-	{-0.262165,	0.210690,	10.090356,	0},
-	{-0.268150,	0.208295,	10.108313,	0},
-	{-0.258574,	0.210690,	10.098736,	0},
-	{-0.270545,	0.219069,	10.097539,	0},
-	{-0.263362,	0.211887,	10.102327,	0},
-	{-0.264559,	0.211887,	10.097539,	0},
-	{-0.262165,	0.204704,	10.090356,	0},
-	{-0.246603,	0.203507,	10.089159,	0},
-	{-0.250194,	0.215478,	10.099933,	0},
-	{-0.270545,	0.225055,	10.109509,	0},
-	{-0.256179,	0.213084,	10.097539,	0},
-	{-0.248997,	0.207098,	10.086765,	0},
-	{-0.248997,	0.210690,	10.087962,	0},
-	{-0.256179,	0.201113,	10.089159,	0},
-	{-0.258574,	0.203507,	10.104721,	0},
-	{-0.262165,	0.208295,	10.093947,	0},
-	{-0.246603,	0.204704,	10.086765,	0},
-	{-0.247800,	0.208295,	10.108313,	0},
-	{-0.252588,	0.220266,	10.099933,	0},
-	{-0.264559,	0.210690,	10.098736,	0},
-	{-0.266953,	0.185551,	10.084371,	0},
-	{-0.253785,	0.213084,	10.109509,	0},
-	{-0.256179,	0.231040,	10.099933,	0},
-	{-0.252588,	0.205901,	10.091554,	0},
-	{-0.259771,	0.207098,	10.095144,	0},
-	{-0.260968,	0.203507,	10.096342,	0},
-	{-0.253785,	0.205901,	10.095144,	0},
-	{-0.256179,	0.217872,	10.093947,	0},
-	{-0.265756,	0.209493,	10.083174,	0},
-	{-0.263362,	0.204704,	10.103524,	0},
-	{-0.253785,	0.198719,	10.095144,	0},
-	{-0.252588,	0.209493,	10.103524,	0},
-	{-0.260968,	0.205901,	10.098736,	0},
-	{-0.259771,	0.205901,	10.083174,	0},
-	{-0.266953,	0.216675,	10.090356,	0},
-	{-0.265756,	0.207098,	10.101130,	0},
-	{-0.262165,	0.204704,	10.111904,	0},
-	{-0.248997,	0.199916,	10.101130,	0},
-	{-0.263362,	0.207098,	10.096342,	0},
-	{-0.281319,	0.227449,	10.108313,	0},
-	{-0.259771,	0.219069,	10.087962,	0},
-	{-0.258574,	0.214281,	10.079582,	0},
-	{-0.268150,	0.204704,	10.108313,	0},
-	{-0.277727,	0.204704,	10.114298,	0},
-	{-0.257377,	0.208295,	10.115496,	0},
-	{-0.260968,	0.222661,	10.104721,	0},
-	{-0.265756,	0.213084,	10.102327,	0},
-	{-0.256179,	0.210690,	10.099933,	0},
-	{-0.253785,	0.203507,	10.109509,	0},
-	{-0.270545,	0.201113,	10.103524,	0},
-	{-0.259771,	0.209493,	10.115496,	0},
-	{-0.264559,	0.207098,	10.103524,	0},
-	{-0.263362,	0.202310,	10.105919,	0},
-	{-0.260968,	0.220266,	10.110707,	0},
-	{-0.257377,	0.216675,	10.110707,	0},
-	{-0.259771,	0.195127,	10.093947,	0},
-	{-0.271742,	0.209493,	10.104721,	0},
-	{-0.257377,	0.223858,	10.108313,	0},
-	{-0.265756,	0.205901,	10.101130,	0},
-	{-0.270545,	0.196324,	10.101130,	0},
-	{-0.254982,	0.202310,	10.115496,	0},
-	{-0.248997,	0.214281,	10.116693,	0},
-	{-0.268150,	0.207098,	10.111904,	0},
-	{-0.263362,	0.204704,	10.091554,	0},
-	{-0.270545,	0.210690,	10.091554,	0},
-	{-0.268150,	0.215478,	10.102327,	0},
-	{-0.264559,	0.223858,	10.096342,	0},
-	{-0.262165,	0.203507,	10.099933,	0},
-	{-0.259771,	0.203507,	10.103524,	0},
-	{-0.269348,	0.204704,	10.119086,	0},
-	{-0.265756,	0.202310,	10.091554,	0},
-	{-0.260968,	0.201113,	10.092751,	0},
-	{-0.260968,	0.210690,	10.092751,	0},
-	{-0.266953,	0.205901,	10.109509,	0},
-	{-0.269348,	0.203507,	10.105919,	0},
-	{-0.264559,	0.193930,	10.114298,	0},
-	{-0.263362,	0.216675,	10.093947,	0},
-	{-0.256179,	0.208295,	10.095144,	0},
-	{-0.271742,	0.203507,	10.103524,	0},
-	{-0.259771,	0.208295,	10.089159,	0},
-	{-0.257377,	0.220266,	10.108313,	0},
-	{-0.266953,	0.207098,	10.101130,	0},
-	{-0.268150,	0.198719,	10.117889,	0},
-	{-0.258574,	0.204704,	10.091554,	0},
-	{-0.266953,	0.201113,	10.104721,	0},
-	{-0.265756,	0.205901,	10.091554,	0},
-	{-0.277727,	0.203507,	10.102327,	0},
-	{-0.266953,	0.204704,	10.093947,	0},
-	{-0.265756,	0.215478,	10.107116,	0},
-	{-0.254982,	0.215478,	10.110707,	0},
-	{-0.269348,	0.217872,	10.095144,	0},
-	{-0.265756,	0.229843,	10.109509,	0},
-	{-0.260968,	0.226252,	10.098736,	0},
-	{-0.253785,	0.208295,	10.095144,	0},
-	{-0.253785,	0.211887,	10.085567,	0},
-	{-0.268150,	0.214281,	10.109509,	0},
-	{-0.258574,	0.201113,	10.107116,	0},
-	{-0.265756,	0.211887,	10.103524,	0},
-	{-0.256179,	0.215478,	10.093947,	0},
-	{-0.263362,	0.204704,	10.107116,	0},
-	{-0.260968,	0.214281,	10.098736,	0},
-	{-0.259771,	0.213084,	10.110707,	0},
-	{-0.276530,	0.215478,	10.095144,	0},
-	{-0.263362,	0.211887,	10.084371,	0},
-	{-0.245406,	0.217872,	10.110707,	0},
-	{-0.251391,	0.209493,	10.105919,	0},
-	{-0.269348,	0.205901,	10.093947,	0},
-	{-0.271742,	0.201113,	10.099933,	0},
-	{-0.270545,	0.228646,	10.099933,	0},
-	{-0.262165,	0.217872,	10.096342,	0},
-	{-0.259771,	0.209493,	10.099933,	0},
-	{-0.260968,	0.210690,	10.105919,	0},
-	{-0.252588,	0.203507,	10.099933,	0},
-	{-0.263362,	0.197522,	10.095144,	0},
-	{-0.271742,	0.213084,	10.101130,	0},
-	{-0.268150,	0.196324,	10.110707,	0},
-	{-0.248997,	0.213084,	10.108313,	0},
-	{-0.254982,	0.215478,	10.095144,	0},
-	{-0.260968,	0.208295,	10.107116,	0},
-	{-0.259771,	0.219069,	10.108313,	0},
-	{-0.266953,	0.214281,	10.098736,	0},
-	{-0.269348,	0.202310,	10.090356,	0},
-	{-0.258574,	0.204704,	10.113101,	0},
-	{-0.263362,	0.226252,	10.086765,	0},
-	{-0.264559,	0.204704,	10.096342,	0},
-	{-0.271742,	0.219069,	10.096342,	0},
-	{-0.252588,	0.210690,	10.104721,	0},
-	{-0.258574,	0.211887,	10.113101,	0},
-	{-0.264559,	0.210690,	10.104721,	0},
-	{-0.269348,	0.214281,	10.103524,	0},
-	{-0.253785,	0.211887,	10.093947,	0},
-	{-0.256179,	0.223858,	10.110707,	0},
-	{-0.274136,	0.207098,	10.098736,	0},
-	{-0.274136,	0.207098,	10.092751,	0},
-	{-0.254982,	0.210690,	10.091554,	0},
-	{-0.257377,	0.204704,	10.098736,	0},
-	{-0.257377,	0.209493,	10.108313,	0},
-	{-0.257377,	0.211887,	10.095144,	0},
-	{-0.259771,	0.199916,	10.095144,	0},
-	{-0.257377,	0.214281,	10.101130,	0},
-	{-0.270545,	0.217872,	10.103524,	0},
-	{-0.281319,	0.204704,	10.104721,	0},
-	{-0.271742,	0.208295,	10.103524,	0},
-	{-0.258574,	0.211887,	10.104721,	0},
-	{-0.264559,	0.204704,	10.126269,	0},
-	{-0.262165,	0.201113,	10.101130,	0},
-	{-0.258574,	0.219069,	10.096342,	0},
-	{-0.263362,	0.211887,	10.107116,	0},
-	{-0.265756,	0.203507,	10.091554,	0},
-	{-0.264559,	0.205901,	10.107116,	0},
-	{-0.256179,	0.214281,	10.095144,	0},
-	{-0.263362,	0.202310,	10.097539,	0},
-	{-0.271742,	0.207098,	10.104721,	0},
-	{-0.272939,	0.210690,	10.101130,	0},
-	{-0.262165,	0.205901,	10.096342,	0},
-	{-0.260968,	0.209493,	10.107116,	0},
-	{-0.269348,	0.217872,	10.093947,	0},
-	{-0.256179,	0.220266,	10.087962,	0},
-	{-0.264559,	0.208295,	10.092751,	0},
-	{-0.265756,	0.208295,	10.095144,	0},
-	{-0.262165,	0.199916,	10.098736,	0},
-	{-0.259771,	0.215478,	10.101130,	0},
-	{-0.263362,	0.217872,	10.097539,	0},
-	{-0.263362,	0.204704,	10.095144,	0},
-	{-0.248997,	0.202310,	10.096342,	0},
-	{-0.260968,	0.226252,	10.097539,	0},
-	{-0.259771,	0.216675,	10.103524,	0},
-	{-0.270545,	0.205901,	10.090356,	0},
-	{-0.250194,	0.219069,	10.089159,	0},
-	{-0.254982,	0.213084,	10.098736,	0},
-	{-0.268150,	0.204704,	10.102327,	0},
-	{-0.258574,	0.215478,	10.104721,	0},
-	{-0.250194,	0.217872,	10.102327,	0},
-	{-0.250194,	0.215478,	10.097539,	0},
-	{-0.251391,	0.213084,	10.086765,	0},
-	{-0.266953,	0.204704,	10.108313,	0},
-	{-0.270545,	0.199916,	10.099933,	0},
-	{-0.271742,	0.208295,	10.092751,	0},
-	{-0.268150,	0.222661,	10.098736,	0},
-	{-0.252588,	0.213084,	10.096342,	0},
-	{-0.266953,	0.213084,	10.092751,	0},
-	{-0.265756,	0.205901,	10.105919,	0},
-	{-0.258574,	0.209493,	10.103524,	0},
-	{-0.263362,	0.203507,	10.103524,	0},
-	{-0.265756,	0.213084,	10.092751,	0},
-	{-0.266953,	0.209493,	10.097539,	0},
-	{-0.272939,	0.193930,	10.110707,	0},
-	{-0.258574,	0.209493,	10.109509,	0},
-	{-0.259771,	0.213084,	10.101130,	0},
-	{-0.274136,	0.215478,	10.101130,	0},
-	{-0.259771,	0.207098,	10.091554,	0},
-	{-0.265756,	0.208295,	10.101130,	0},
-	{-0.263362,	0.210690,	10.109509,	0},
-	{-0.264559,	0.216675,	10.110707,	0},
-	{-0.266953,	0.211887,	10.099933,	0},
-	{-0.268150,	0.199916,	10.093947,	0},
-	{-0.265756,	0.216675,	10.105919,	0},
-	{-0.262165,	0.204704,	10.081977,	0},
-	{-0.263362,	0.214281,	10.086765,	0},
-	{-0.263362,	0.210690,	10.084371,	0},
-	{-0.257377,	0.201113,	10.104721,	0},
-	{-0.262165,	0.203507,	10.109509,	0},
-	{-0.266953,	0.217872,	10.113101,	0},
-	{-0.252588,	0.209493,	10.102327,	0},
-	{-0.257377,	0.213084,	10.096342,	0},
-	{-0.260968,	0.211887,	10.101130,	0},
-	{-0.263362,	0.197522,	10.114298,	0},
-	{-0.272939,	0.192733,	10.103524,	0},
-	{-0.250194,	0.207098,	10.079582,	0},
-	{-0.253785,	0.214281,	10.107116,	0},
-	{-0.254982,	0.205901,	10.095144,	0},
-	{-0.256179,	0.209493,	10.103524,	0},
-	{-0.265756,	0.222661,	10.111904,	0},
-	{-0.259771,	0.211887,	10.101130,	0},
-	{-0.256179,	0.202310,	10.115496,	0},
-	{-0.260968,	0.209493,	10.109509,	0},
-	{-0.243011,	0.203507,	10.101130,	0},
-	{-0.252588,	0.205901,	10.096342,	0},
-	{-0.253785,	0.225055,	10.095144,	0},
-	{-0.258574,	0.225055,	10.096342,	0},
-	{-0.264559,	0.215478,	10.092751,	0},
-	{-0.265756,	0.205901,	10.114298,	0},
-	{-0.266953,	0.220266,	10.108313,	0},
-	{-0.268150,	0.208295,	10.109509,	0},
-	{-0.259771,	0.210690,	10.103524,	0},
-	{-0.253785,	0.210690,	10.109509,	0},
-	{-0.268150,	0.213084,	10.097539,	0},
-	{-0.268150,	0.215478,	10.102327,	0},
-	{-0.269348,	0.201113,	10.103524,	0},
-	{-0.262165,	0.199916,	10.107116,	0},
-	{-0.260968,	0.205901,	10.120284,	0},
-	{-0.257377,	0.193930,	10.102327,	0},
-	{-0.264559,	0.203507,	10.104721,	0},
-	{-0.265756,	0.210690,	10.093947,	0},
-	{-0.256179,	0.209493,	10.097539,	0},
-	{-0.257377,	0.204704,	10.107116,	0},
-	{-0.260968,	0.208295,	10.093947,	0},
-	{-0.258574,	0.204704,	10.102327,	0},
-	{-0.263362,	0.211887,	10.107116,	0},
-	{-0.263362,	0.191536,	10.097539,	0},
-	{-0.253785,	0.209493,	10.107116,	0},
-	{-0.254982,	0.217872,	10.105919,	0},
-	{-0.259771,	0.207098,	10.096342,	0},
-	{-0.265756,	0.204704,	10.114298,	0},
-	{-0.270545,	0.208295,	10.099933,	0},
-	{-0.262165,	0.214281,	10.104721,	0},
-	{-0.257377,	0.205901,	10.095144,	0},
-	{-0.266953,	0.214281,	10.096342,	0},
-	{-0.274136,	0.225055,	10.093947,	0},
-	{-0.266953,	0.216675,	10.099933,	0},
-	{-0.269348,	0.208295,	10.099933,	0},
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+	{ 5.887338, 0.451307, 7.697353, 0 },
+	{ 5.850228, 0.456095, 7.779953, 0 },
+	{ 5.858608, 0.477643, 7.884101, 0 },
+	{ 5.749671, 0.506373, 7.787136, 0 },
+	{ 5.683831, 0.507570, 7.660243, 0 },
+	{ 5.740095, 0.469263, 7.811078, 0 },
+	{ 5.766431, 0.405817, 8.002614, 0 },
+	{ 5.714955, 0.442927, 8.042118, 0 },
+	{ 5.723335, 0.399831, 8.002614, 0 },
+	{ 5.712561, 0.343568, 7.995431, 0 },
+	{ 5.741292, 0.323217, 8.110353, 0 },
+	{ 5.766431, 0.349553, 8.237246, 0 },
+	{ 5.704182, 0.367510, 8.276750, 0 },
+	{ 5.651509, 0.348356, 8.161828, 0 },
+	{ 5.655100, 0.367510, 7.977475, 0 },
+	{ 5.770022, 0.269348, 8.037330, 0 },
+	{ 5.765234, 0.149638, 8.125915, 0 },
+	{ 5.671860, 0.073023, 7.973883, 0 },
+	{ 5.667071, 0.105345, 7.836217, 0 },
+	{ 5.662283, 0.092177, 7.824246, 0 },
+	{ 5.702984, 0.031125, 7.970292, 0 },
+	{ 5.731715, -0.005986, 8.169010, 0 },
+	{ 5.705379, -0.038307, 8.178588, 0 },
+	{ 5.635947, -0.082600, 8.060075, 0 },
+	{ 5.614399, -0.087388, 7.846991, 0 },
+	{ 5.607216, -0.051475, 7.807487, 0 },
+	{ 5.610808, -0.033519, 7.864947, 0 },
+	{ 5.594049, 0.014365, 7.959518, 0 },
+	{ 5.595245, 0.070629, 8.085214, 0 },
+	{ 5.577289, 0.046687, 8.267173, 0 },
+	{ 5.512646, -0.061052, 8.195347, 0 },
+	{ 5.414484, -0.068235, 7.988248, 0 },
+	{ 5.358220, 0.023942, 7.862553, 0 },
+	{ 5.412089, 0.094571, 7.925999, 0 },
+	{ 5.420469, 0.159214, 8.106761, 0 },
+	{ 5.276817, 0.208295, 8.341393, 0 },
+	{ 5.264846, 0.239420, 8.215697, 0 },
+	{ 5.281605, 0.105345, 8.564054, 0 },
+	{ 5.311533, -0.020351, 8.683764, 0 },
+	{ 5.209779, 0.087388, 8.489834, 0 },
+	{ 5.149924, 0.135272, 8.765166, 0 },
+	{ 5.169078, 0.017957, 9.282313, 0 },
+	{ 5.274423, -0.105345, 9.628276, 0 },
+	{ 5.270832, -0.059855, 9.247598, 0 },
+	{ 5.166684, 0.098162, 8.629894, 0 },
+	{ 5.128376, 0.126893, 8.294706, 0 },
+	{ 5.119997, 0.088585, 8.373714, 0 },
+	{ 5.146333, 0.090980, 8.540112, 0 },
+	{ 5.112814, 0.226252, 8.293509, 0 },
+	{ 5.086478, 0.238223, 8.079228, 0 },
+	{ 5.076901, 0.137667, 8.086411, 0 },
+	{ 5.064930, 0.064643, 8.396460, 0 },
+	{ 5.090069, 0.101754, 8.791503, 0 },
+	{ 5.090069, 0.272939, 9.018951, 0 },
+	{ 5.106829, 0.399831, 8.947125, 0 },
+	{ 5.129574, 0.401029, 8.738831, 0 },
+	{ 5.143939, 0.233435, 8.713691, 0 },
+	{ 5.165487, 0.124498, 8.570039, 0 },
+	{ 5.170275, 0.147243, 8.276750, 0 },
+	{ 5.114011, 0.207098, 7.818260, 0 },
+	{ 5.033806, 0.308852, 7.491452, 0 },
+	{ 5.043383, 0.314837, 7.789530, 0 },
+	{ 5.061339, 0.219069, 8.386883, 0 },
+	{ 5.069719, 0.137667, 8.644259, 0 },
+	{ 5.058945, 0.147243, 8.481454, 0 },
+	{ 5.007470, 0.186748, 8.107959, 0 },
+	{ 4.957191, 0.214281, 8.024161, 0 },
+	{ 5.048171, 0.130484, 8.451527, 0 },
+	{ 5.088872, 0.058658, 8.924380, 0 },
+	{ 5.104434, -0.016759, 9.154224, 0 },
+	{ 5.117603, -0.027533, 8.935155, 0 },
+	{ 5.018243, 0.071826, 8.637076, 0 },
+	{ 4.983528, 0.090980, 8.604755, 0 },
+	{ 5.019441, 0.026336, 8.650245, 0 },
+	{ 5.030214, -0.013168, 8.646653, 0 },
+	{ 4.939235, -0.026336, 8.565250, 0 },
+	{ 4.879380, -0.089783, 8.562857, 0 },
+	{ 4.832693, -0.186748, 8.906425, 0 },
+	{ 4.851846, -0.294487, 9.361322, 0 },
+	{ 4.910504, -0.284910, 9.572012, 0 },
+	{ 4.920081, -0.166397, 9.233232, 0 },
+	{ 4.865015, -0.051475, 8.621514, 0 },
+	{ 4.821919, -0.007183, 8.482651, 0 },
+	{ 4.851846, -0.021548, 8.792700, 0 },
+	{ 4.916490, -0.056264, 9.081201, 0 },
+	{ 4.939235, -0.034716, 8.680172, 0 },
+	{ 4.878182, 0.039504, 8.130703, 0 },
+	{ 4.825510, 0.070629, 8.079228, 0 },
+	{ 4.854240, 0.033519, 8.445540, 0 },
+	{ 4.932052, -0.016759, 8.767561, 0 },
+	{ 4.988316, -0.080206, 8.864526, 0 },
+	{ 5.024229, -0.152032, 8.710100, 0 },
+	{ 5.026623, -0.175974, 8.593981, 0 },
+	{ 5.011061, -0.119710, 8.465892, 0 },
+	{ 5.051762, -0.058658, 8.503001, 0 },
+	{ 5.104434, 0.028730, 8.389277, 0 },
+	{ 5.108026, 0.174777, 8.304283, 0 },
+	{ 5.121194, 0.207098, 8.368926, 0 },
+	{ 5.137953, 0.177171, 8.186967, 0 },
+	{ 5.123588, 0.141258, 8.036133, 0 },
+	{ 5.098449, 0.186748, 8.031344, 0 },
+	{ 5.036200, 0.240617, 8.049300, 0 },
+	{ 4.977542, 0.316034, 8.190558, 0 },
+	{ 4.978739, 0.294487, 8.428782, 0 },
+	{ 5.046974, 0.195127, 8.704114, 0 },
+	{ 5.042185, 0.211887, 8.719677, 0 },
+	{ 4.927264, 0.299275, 8.538915, 0 },
+	{ 4.918884, 0.241814, 8.495819, 0 },
+	{ 4.897336, 0.189142, 8.492228, 0 },
+	{ 4.878182, 0.237026, 8.601164, 0 },
+	{ 4.818327, 0.262165, 8.705312, 0 },
+	{ 4.871000, 0.172382, 8.791503, 0 },
+	{ 4.924870, 0.119710, 8.872906, 0 },
+	{ 4.873394, 0.243011, 8.825022, 0 },
+	{ 4.832693, 0.408211, 8.659822, 0 },
+	{ 4.838678, 0.367510, 8.619121, 0 },
+	{ 4.904519, 0.169988, 8.809459, 0 },
+	{ 4.926067, 0.071826, 9.058456, 0 },
+	{ 4.940432, 0.058658, 8.823824, 0 },
+	{ 4.930855, 0.167594, 8.331817, 0 },
+	{ 4.918884, 0.266953, 8.265976, 0 },
+	{ 4.941629, 0.207098, 8.900438, 0 },
+	{ 4.957191, 0.129287, 9.339774, 0 },
+	{ 4.915293, 0.180762, 9.089581, 0 },
+	{ 4.930855, 0.190339, 8.826219, 0 },
+	{ 5.080492, 0.038307, 8.766363, 0 },
+	{ 5.204991, -0.108936, 8.631091, 0 },
+	{ 5.202597, -0.047884, 8.157040, 0 },
+	{ 5.157107, 0.095768, 7.870933, 0 },
+	{ 5.164289, 0.168791, 8.019373, 0 },
+	{ 5.199006, 0.167594, 8.428782, 0 },
+	{ 5.215765, 0.180762, 8.804670, 0 },
+	{ 5.201400, 0.278924, 8.614332, 0 },
+	{ 5.171472, 0.433350, 8.225274, 0 },
+	{ 5.199006, 0.466869, 8.068454, 0 },
+	{ 5.245692, 0.434547, 8.081622, 0 },
+	{ 5.252875, 0.493205, 8.092396, 0 },
+	{ 5.194217, 0.633266, 8.359349, 0 },
+	{ 5.155910, 0.772130, 8.494622, 0 },
+	{ 5.196611, 0.809240, 8.324634, 0 },
+	{ 5.245692, 0.724246, 8.206120, 0 },
+	{ 5.252875, 0.677559, 8.295903, 0 },
+	{ 5.234919, 0.689530, 8.449132, 0 },
+	{ 5.256466, 0.666785, 8.635880, 0 },
+	{ 5.276817, 0.672770, 8.653836, 0 },
+	{ 5.300759, 0.682347, 8.694537, 0 },
+	{ 5.352234, 0.640449, 8.677778, 0 },
+	{ 5.373782, 0.659602, 8.445540, 0 },
+	{ 5.371388, 0.752976, 8.093594, 0 },
+	{ 5.348643, 0.889445, 7.916422, 0 },
+	{ 5.337869, 0.974439, 8.097184, 0 },
+	{ 5.346249, 0.991199, 8.227669, 0 },
+	{ 5.382162, 0.978031, 8.289918, 0 },
+	{ 5.436031, 0.922964, 8.264779, 0 },
+	{ 5.408498, 0.940921, 8.136689, 0 },
+	{ 5.376176, 0.939724, 8.165420, 0 },
+	{ 5.364205, 0.924161, 8.331817, 0 },
+	{ 5.351037, 0.873883, 8.446738, 0 },
+	{ 5.334278, 0.855927, 8.334210, 0 },
+	{ 5.292379, 0.861912, 8.178588, 0 },
+	{ 5.298365, 0.858321, 8.146266, 0 },
+	{ 5.319912, 0.841561, 8.136689, 0 },
+	{ 5.353431, 0.793677, 8.121126, 0 },
+	{ 5.378571, 0.736217, 8.218092, 0 },
+	{ 5.397724, 0.694318, 8.354561, 0 },
+	{ 5.367796, 0.709880, 8.420402, 0 },
+	{ 5.335475, 0.749385, 8.528141, 0 },
+	{ 5.313927, 0.818816, 8.493424, 0 },
+	{ 5.306745, 0.889445, 8.315057, 0 },
+	{ 5.333081, 0.893037, 8.216895, 0 },
+	{ 5.345052, 0.899022, 8.208515, 0 },
+	{ 5.348643, 0.920570, 8.322240, 0 },
+	{ 5.346249, 0.955286, 8.494622, 0 },
+	{ 5.325898, 0.984016, 8.801080, 0 },
+	{ 5.355825, 0.998381, 9.132676, 0 },
+	{ 5.388147, 0.967257, 9.349351, 0 },
+	{ 5.489901, 0.889445, 9.421177, 0 },
+	{ 5.553347, 0.900219, 9.010572, 0 },
+	{ 5.532996, 1.004367, 8.176193, 0 },
+	{ 5.509054, 1.109712, 7.471101, 0 },
+	{ 5.504266, 1.175552, 7.400473, 0 },
+	{ 5.482718, 1.159990, 7.684185, 0 },
+	{ 5.443214, 1.177946, 8.027753, 0 },
+	{ 5.426455, 1.201888, 8.292312, 0 },
+	{ 5.492295, 1.139639, 8.359349, 0 },
+	{ 5.532996, 1.092952, 8.263581, 0 },
+	{ 5.522223, 1.072602, 7.959518, 0 },
+	{ 5.504266, 1.033097, 7.606374, 0 },
+	{ 5.524617, 0.958877, 7.461524, 0 },
+	{ 5.505463, 0.876277, 7.580038, 0 },
+	{ 5.458776, 0.823605, 7.835020, 0 },
+	{ 5.432440, 0.756567, 8.016979, 0 },
+	{ 5.386950, 0.760159, 8.174996, 0 },
+	{ 5.400118, 0.748188, 8.362941, 0 },
+	{ 5.449199, 0.687135, 8.324634, 0 },
+	{ 5.426455, 0.701501, 7.993037, 0 },
+	{ 5.407301, 0.751779, 7.637498, 0 },
+	{ 5.455185, 0.737414, 7.868538, 0 },
+	{ 5.456382, 0.735019, 8.342590, 0 },
+	{ 5.409695, 0.805648, 8.420402, 0 },
+	{ 5.379767, 0.878671, 8.323437, 0 },
+	{ 5.433637, 0.877474, 8.230062, 0 },
+	{ 5.477930, 0.864306, 8.248019, 0 },
+	{ 5.511448, 0.831985, 8.370124, 0 },
+	{ 5.525814, 0.817619, 8.439555, 0 },
+	{ 5.498281, 0.797269, 8.486242, 0 },
+	{ 5.485112, 0.806845, 8.465892, 0 },
+	{ 5.480324, 0.830787, 8.364138, 0 },
+	{ 5.485112, 0.831985, 8.337802, 0 },
+	{ 5.487506, 0.854729, 8.340196, 0 },
+	{ 5.434834, 0.873883, 8.372518, 0 },
+	{ 5.397724, 0.854729, 8.346182, 0 },
+	{ 5.392936, 0.869095, 8.216895, 0 },
+	{ 5.373782, 0.891840, 8.018176, 0 },
+	{ 5.401315, 0.872686, 7.902057, 0 },
+	{ 5.448002, 0.833182, 7.929591, 0 },
+	{ 5.425257, 0.835576, 8.146266, 0 },
+	{ 5.413286, 0.849941, 8.409628, 0 },
+	{ 5.421666, 0.837970, 8.495819, 0 },
+	{ 5.434834, 0.802057, 8.402445, 0 },
+	{ 5.456382, 0.772130, 8.238442, 0 },
+	{ 5.482718, 0.749385, 8.231260, 0 },
+	{ 5.497083, 0.744596, 8.304283, 0 },
+	{ 5.479127, 0.781706, 8.298298, 0 },
+	{ 5.432440, 0.882263, 8.295903, 0 },
+	{ 5.404907, 0.958877, 8.201332, 0 },
+	{ 5.397724, 0.944512, 8.110353, 0 },
+	{ 5.394133, 0.920570, 8.216895, 0 },
+	{ 5.437228, 0.899022, 8.328225, 0 },
+	{ 5.474339, 0.902613, 8.413219, 0 },
+	{ 5.529405, 0.889445, 8.447935, 0 },
+	{ 5.590457, 0.873883, 8.355759, 0 },
+	{ 5.612005, 0.877474, 8.292312, 0 },
+	{ 5.613202, 0.870292, 8.209712, 0 },
+	{ 5.585669, 0.913387, 8.025358, 0 },
+	{ 5.511448, 0.933738, 7.991840, 0 },
+	{ 5.475535, 0.949300, 8.026556, 0 },
+	{ 5.463564, 0.999579, 8.031344, 0 },
+	{ 5.469550, 0.994790, 7.918817, 0 },
+	{ 5.504266, 0.974439, 7.881707, 0 },
+	{ 5.546165, 0.991199, 7.955927, 0 },
+	{ 5.553347, 0.997184, 8.128309, 0 },
+	{ 5.567712, 1.010352, 8.230062, 0 },
+	{ 5.553347, 1.048660, 8.279144, 0 },
+	{ 5.578486, 1.033097, 8.268370, 0 },
+	{ 5.571303, 1.016338, 8.101973, 0 },
+	{ 5.543770, 0.985213, 7.933182, 0 },
+	{ 5.550953, 0.909796, 7.971489, 0 },
+	{ 5.547361, 0.855927, 7.951138, 0 },
+	{ 5.540179, 0.840364, 7.978672, 0 },
+	{ 5.523419, 0.848744, 8.152251, 0 },
+	{ 5.491098, 0.853532, 8.298298, 0 },
+	{ 5.420469, 0.901416, 8.333014, 0 },
+	{ 5.403709, 0.937329, 8.419205, 0 },
+	{ 5.440820, 0.964863, 8.601164, 0 },
+	{ 5.465959, 0.991199, 8.426387, 0 },
+	{ 5.457579, 1.051054, 8.109156, 0 },
+	{ 5.437228, 1.104923, 7.977475, 0 },
+	{ 5.428849, 1.102529, 8.027753, 0 },
+	{ 5.433637, 1.090558, 8.195347, 0 },
+	{ 5.432440, 1.100135, 8.276750, 0 },
+	{ 5.461170, 1.134851, 8.309072, 0 },
+	{ 5.511448, 1.119289, 8.292312, 0 },
+	{ 5.540179, 1.089361, 8.316254, 0 },
+	{ 5.518631, 1.103726, 8.358152, 0 },
+	{ 5.528208, 1.112106, 8.343787, 0 },
+	{ 5.527011, 1.094149, 8.257596, 0 },
+	{ 5.495886, 1.116894, 8.154645, 0 },
+	{ 5.510252, 1.092952, 8.208515, 0 },
+	{ 5.538982, 1.058236, 8.158237, 0 },
+	{ 5.511448, 1.088164, 7.948744, 0 },
+	{ 5.515040, 1.084573, 7.852976, 0 },
+	{ 5.507857, 1.104923, 7.959518, 0 },
+	{ 5.468353, 1.138442, 8.188165, 0 },
+	{ 5.468353, 1.148019, 8.327028, 0 },
+	{ 5.481521, 1.133654, 8.289918, 0 },
+	{ 5.511448, 1.120486, 8.226472, 0 },
+	{ 5.530602, 1.086967, 8.198938, 0 },
+	{ 5.529405, 1.065419, 8.166616, 0 },
+	{ 5.469550, 1.060631, 8.221684, 0 },
+	{ 5.440820, 1.053448, 8.240837, 0 },
+	{ 5.396527, 1.053448, 8.213304, 0 },
+	{ 5.386950, 1.055842, 8.234851, 0 },
+	{ 5.421666, 1.046265, 8.246822, 0 },
+	{ 5.431243, 1.029506, 8.155843, 0 },
+	{ 5.298365, 1.292868, 5.756854, 0 },
+	{ 5.191823, 1.255758, 8.088805, 0 },
+	{ 5.204991, 1.169567, 10.260345, 0 }
 };
 
 const size_t kBodyDetectOffOnTestDataLength =
 	ARRAY_SIZE(kBodyDetectOffOnTestData);
 
 const struct body_detect_test_data kBodyDetectOnOffTestData[] = {
-	{-6.536166,	0.264559,	7.560884,	0},
-	{-6.253651,	0.108936,	8.167813,	0},
-	{-5.890929,	-0.029928,	8.061272,	0},
-	{-5.833468,	-0.045490,	8.250414,	0},
-	{-5.932828,	0.038307,	8.573630,	0},
-	{-5.995077,	0.104148,	8.634683,	0},
-	{-6.080071,	0.181959,	8.317451,	0},
-	{-6.069297,	0.177171,	8.151054,	0},
-	{-5.978318,	0.113724,	8.407233,	0},
-	{-5.895718,	0.033519,	8.592784,	0},
-	{-5.828680,	-0.022745,	8.299495,	0},
-	{-5.768825,	-0.070629,	7.958321,	0},
-	{-5.770022,	-0.089783,	8.028950,	0},
-	{-5.832272,	-0.074220,	8.360547,	0},
-	{-5.880156,	-0.067038,	8.488636,	0},
-	{-5.987895,	-0.017957,	8.342590,	0},
-	{-6.148306,	0.014365,	8.317451,	0},
-	{-6.337448,	0.102951,	8.492228,	0},
-	{-6.411668,	0.148440,	8.571237,	0},
-	{-6.341039,	0.099359,	8.250414,	0},
-	{-6.232103,	0.067038,	7.899663,	0},
-	{-6.172248,	0.100556,	8.152251,	0},
-	{-6.095634,	0.111330,	8.632288,	0},
-	{-6.033384,	0.126893,	8.614332,	0},
-	{-5.936419,	0.131681,	8.136689,	0},
-	{-5.931631,	0.205901,	7.739252,	0},
-	{-5.986697,	0.271742,	7.870933,	0},
-	{-6.040567,	0.250194,	8.099579,	0},
-	{-6.077677,	0.244208,	8.191755,	0},
-	{-6.071692,	0.277727,	8.146266,	0},
-	{-5.953178,	0.292092,	8.025358,	0},
-	{-5.847834,	0.330400,	7.942759,	0},
-	{-5.776008,	0.392649,	8.036133,	0},
-	{-5.680240,	0.417788,	7.892480,	0},
-	{-5.617990,	0.458489,	7.609965,	0},
-	{-5.550953,	0.496797,	7.418429,	0},
-	{-5.301956,	0.369904,	8.050498,	0},
-	{-5.276817,	0.290895,	9.167392,	0},
-	{-5.890929,	0.215478,	9.044091,	0},
-	{-6.495465,	0.108936,	9.111129,	0},
-	{-6.545743,	-0.049081,	9.390053,	0},
-	{-5.966347,	-0.161609,	9.362519,	0},
-	{-5.325898,	-0.117316,	8.969871,	0},
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+	{ -0.252588, 0.071826, 10.099933, 0 },
+	{ -0.245406, 0.082600, 10.132255, 0 },
+	{ -0.246603, 0.086191, 10.129861, 0 },
+	{ -0.227449, 0.067038, 10.151408, 0 },
+	{ -0.235829, 0.079009, 10.109509, 0 },
+	{ -0.239420, 0.080206, 10.137043, 0 },
+	{ -0.241814, 0.084994, 10.121481, 0 },
+	{ -0.251391, 0.081403, 10.116693, 0 },
+	{ -0.260968, 0.073023, 10.141831, 0 },
+	{ -0.245406, 0.073023, 10.122678, 0 },
+	{ -0.252588, 0.083797, 10.139438, 0 },
+	{ -0.243011, 0.080206, 10.122678, 0 },
+	{ -0.239420, 0.077812, 10.138240, 0 },
+	{ -0.241814, 0.068235, 10.113101, 0 },
+	{ -0.244208, 0.074220, 10.133451, 0 },
+	{ -0.257377, 0.079009, 10.128663, 0 },
+	{ -0.253785, 0.074220, 10.125072, 0 },
+	{ -0.238223, 0.062249, 10.132255, 0 },
+	{ -0.243011, 0.068235, 10.119086, 0 },
+	{ -0.240617, 0.074220, 10.132255, 0 },
+	{ -0.272939, 0.076614, 10.116693, 0 },
+	{ -0.234632, 0.075417, 10.138240, 0 },
+	{ -0.241814, 0.073023, 10.085567, 0 },
+	{ -0.246603, 0.075417, 10.163380, 0 },
+	{ -0.248997, 0.058658, 10.093947, 0 },
+	{ -0.243011, 0.070629, 10.146620, 0 },
+	{ -0.238223, 0.074220, 10.110707, 0 },
+	{ -0.252588, 0.065841, 10.141831, 0 },
+	{ -0.229843, 0.074220, 10.137043, 0 },
+	{ -0.248997, 0.076614, 10.099933, 0 },
+	{ -0.229843, 0.081403, 10.157393, 0 },
+	{ -0.243011, 0.082600, 10.074794, 0 },
+	{ -0.250194, 0.071826, 10.164577, 0 },
+	{ -0.263362, 0.076614, 10.103524, 0 },
+	{ -0.260968, 0.094571, 10.138240, 0 },
+	{ -0.240617, 0.077812, 10.116693, 0 },
+	{ -0.239420, 0.081403, 10.109509, 0 },
+	{ -0.253785, 0.086191, 10.135846, 0 },
+	{ -0.247800, 0.076614, 10.093947, 0 },
+	{ -0.256179, 0.068235, 10.158591, 0 },
+	{ -0.253785, 0.079009, 10.090356, 0 },
+	{ -0.239420, 0.076614, 10.151408, 0 },
+	{ -0.244208, 0.082600, 10.115496, 0 },
+	{ -0.244208, 0.081403, 10.134649, 0 },
+	{ -0.254982, 0.088585, 10.122678, 0 },
+	{ -0.252588, 0.069432, 10.120284, 0 },
+	{ -0.247800, 0.077812, 10.137043, 0 },
+	{ -0.250194, 0.076614, 10.117889, 0 },
+	{ -0.238223, 0.077812, 10.121481, 0 },
+	{ -0.245406, 0.065841, 10.186124, 0 },
+	{ -0.233435, 0.065841, 10.046063, 0 },
+	{ -0.237026, 0.094571, 10.243585, 0 },
+	{ -0.231040, 0.093374, 10.014939, 0 },
+	{ -0.243011, 0.084994, 10.223234, 0 },
+	{ -0.256179, 0.064643, 9.987406, 0 },
+	{ -0.250194, 0.098162, 10.247176, 0 },
+	{ -0.229843, 0.073023, 9.891638, 0 },
+	{ -0.268150, 0.062249, 10.406390, 0 },
+	{ -0.247800, 0.073023, 9.883258, 0 },
+	{ -0.237026, 0.076614, 10.360901, 0 },
+	{ -0.247800, 0.081403, 9.975434, 0 },
+	{ -0.225055, 0.080206, 10.178942, 0 },
+	{ -0.263362, 0.071826, 10.163380, 0 },
+	{ -0.237026, 0.076614, 10.062823, 0 },
+	{ -0.265756, 0.075417, 10.214854, 0 },
+	{ -0.234632, 0.083797, 10.053246, 0 },
+	{ -0.254982, 0.071826, 10.210066, 0 },
+	{ -0.241814, 0.076614, 10.001771, 0 },
+	{ -0.221464, 0.117316, 10.239994, 0 },
+	{ -0.269348, 0.076614, 10.064020, 0 },
+	{ -0.220266, 0.092177, 10.166970, 0 },
+	{ -0.252588, 0.075417, 10.111904, 0 },
+	{ -0.232237, 0.068235, 10.122678, 0 },
+	{ -0.259771, 0.075417, 10.110707, 0 },
+	{ -0.246603, 0.095768, 10.137043, 0 },
+	{ -0.235829, 0.076614, 10.138240, 0 },
+	{ -0.256179, 0.071826, 10.102327, 0 },
+	{ -0.229843, 0.089783, 10.175350, 0 },
+	{ -0.260968, 0.082600, 10.089159, 0 },
+	{ -0.225055, 0.086191, 10.169365, 0 },
+	{ -0.262165, 0.087388, 10.103524, 0 },
+	{ -0.234632, 0.077812, 10.149014, 0 },
+	{ -0.241814, 0.070629, 10.079582, 0 },
+	{ -0.256179, 0.077812, 10.163380, 0 },
+	{ -0.226252, 0.068235, 10.096342, 0 },
+	{ -0.253785, 0.080206, 10.117889, 0 },
+	{ -0.244208, 0.077812, 10.163380, 0 },
+	{ -0.269348, 0.076614, 10.097539, 0 },
+	{ -0.238223, 0.069432, 10.169365, 0 },
+	{ -0.254982, 0.068235, 10.096342, 0 },
+	{ -0.231040, 0.061052, 10.159788, 0 },
+	{ -0.248997, 0.075417, 10.079582, 0 },
+	{ -0.258574, 0.071826, 10.162182, 0 },
+	{ -0.232237, 0.079009, 10.102327, 0 },
+	{ -0.256179, 0.100556, 10.138240, 0 },
+	{ -0.232237, 0.084994, 10.116693, 0 },
+	{ -0.235829, 0.080206, 10.110707, 0 },
+	{ -0.225055, 0.065841, 10.129861, 0 },
+	{ -0.217872, 0.082600, 10.090356, 0 },
+	{ -0.244208, 0.081403, 10.157393, 0 },
 };
 
 const size_t kBodyDetectOnOffTestDataLength =
diff --git a/test/body_detection_test_data.h b/test/body_detection_test_data.h
index 4c22c3236f..913701455b 100644
--- a/test/body_detection_test_data.h
+++ b/test/body_detection_test_data.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/boringssl_crypto.cc b/test/boringssl_crypto.cc
new file mode 100644
index 0000000000..a138f3f61a
--- /dev/null
+++ b/test/boringssl_crypto.cc
@@ -0,0 +1,221 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "crypto/cleanse_wrapper.h"
+#include "crypto/elliptic_curve_key.h"
+#include "openssl/bn.h"
+#include "openssl/ec.h"
+#include "openssl/mem.h"
+#include "openssl/obj_mac.h"
+#include "openssl/rand.h"
+#include "test_util.h"
+#include "util.h"
+
+extern "C" {
+#include "sha256.h"
+}
+
+#include <array>
+#include <memory>
+
+test_static enum ec_error_list test_rand(void)
+{
+	constexpr uint8_t zero[256] = { 0 };
+	uint8_t buf1[256];
+	uint8_t buf2[256];
+
+	RAND_bytes(buf1, sizeof(buf1));
+	RAND_bytes(buf2, sizeof(buf2));
+
+	TEST_ASSERT_ARRAY_NE(buf1, zero, sizeof(zero));
+	TEST_ASSERT_ARRAY_NE(buf2, zero, sizeof(zero));
+	TEST_ASSERT_ARRAY_NE(buf1, buf2, sizeof(buf1));
+
+	return EC_SUCCESS;
+}
+
+test_static enum ec_error_list test_ecc_keygen(void)
+{
+	bssl::UniquePtr<EC_KEY> key1 = generate_elliptic_curve_key();
+
+	TEST_NE(key1.get(), nullptr, "%p");
+
+	/* The generated key should be valid.*/
+	TEST_EQ(EC_KEY_check_key(key1.get()), 1, "%d");
+
+	bssl::UniquePtr<EC_KEY> key2 = generate_elliptic_curve_key();
+
+	TEST_NE(key2.get(), nullptr, "%p");
+
+	/* The generated key should be valid. */
+	TEST_EQ(EC_KEY_check_key(key2.get()), 1, "%d");
+
+	const BIGNUM *priv1 = EC_KEY_get0_private_key(key1.get());
+	const BIGNUM *priv2 = EC_KEY_get0_private_key(key2.get());
+
+	/* The generated keys should not be the same. */
+	TEST_NE(BN_cmp(priv1, priv2), 0, "%d");
+
+	/* The generated keys should not be zero. */
+	TEST_EQ(BN_is_zero(priv1), 0, "%d");
+	TEST_EQ(BN_is_zero(priv2), 0, "%d");
+
+	return EC_SUCCESS;
+}
+
+test_static enum ec_error_list test_cleanse_wrapper_std_array(void)
+{
+	using TypeToCheck = std::array<uint8_t, 6>;
+	using Wrapped = CleanseWrapper<TypeToCheck>;
+
+	/* Preserve a space for it. */
+	uint8_t *buffer = static_cast<uint8_t *>(malloc(sizeof(Wrapped)));
+	Wrapped *data = reinterpret_cast<Wrapped *>(buffer);
+
+	/* Call the constructor. */
+	new (data) Wrapped({ 1, 1, 1, 1, 1, 1 });
+
+	TEST_ASSERT_MEMSET(data->data(), 1, data->size());
+
+	/* Call the destructor. */
+	data->~Wrapped();
+
+	TEST_ASSERT_MEMSET(buffer, 0, sizeof(Wrapped));
+
+	/* Free the space. */
+	free(buffer);
+
+	return EC_SUCCESS;
+}
+
+test_static enum ec_error_list test_cleanse_wrapper_sha256(void)
+{
+	using TypeToCheck = struct sha256_ctx;
+	using Wrapped = CleanseWrapper<TypeToCheck>;
+
+	/* Preserve a space for it. */
+	uint8_t *buffer = static_cast<uint8_t *>(malloc(sizeof(Wrapped)));
+	Wrapped *data = reinterpret_cast<Wrapped *>(buffer);
+
+	/* Call the constructor. */
+	new (data) Wrapped();
+
+	std::array<uint8_t, 5> data_to_sha = { 1, 2, 3, 4, 5 };
+	SHA256_init(data);
+	SHA256_update(data, data_to_sha.data(), data_to_sha.size());
+	uint8_t *result = SHA256_final(data);
+
+	std::array<uint8_t, 32> expected_result = {
+		0X74, 0XF8, 0X1F, 0XE1, 0X67, 0XD9, 0X9B, 0X4C,
+		0XB4, 0X1D, 0X6D, 0X0C, 0XCD, 0XA8, 0X22, 0X78,
+		0XCA, 0XEE, 0X9F, 0X3E, 0X2F, 0X25, 0XD5, 0XE5,
+		0XA3, 0X93, 0X6F, 0XF3, 0XDC, 0XEC, 0X60, 0XD0,
+	};
+
+	TEST_ASSERT_ARRAY_EQ(result, expected_result, expected_result.size());
+
+	/* Call the destructor. */
+	data->~Wrapped();
+
+	TEST_ASSERT_MEMSET(buffer, 0, sizeof(Wrapped));
+
+	/* Free the space. */
+	free(buffer);
+
+	return EC_SUCCESS;
+}
+
+test_static enum ec_error_list test_cleanse_wrapper_custom_struct(void)
+{
+	struct TestingStruct {
+		bool used;
+		std::array<uint32_t, 4> data;
+	};
+
+	using TypeToCheck = TestingStruct;
+	using Wrapped = CleanseWrapper<TypeToCheck>;
+
+	/* Preserve a space for it. */
+	uint8_t *buffer = static_cast<uint8_t *>(malloc(sizeof(Wrapped)));
+	Wrapped *data = reinterpret_cast<Wrapped *>(buffer);
+
+	/* Call the constructor. */
+	new (data) Wrapped({
+		.used = true,
+		.data = { 0x7fffffffu, 0x12345678u, 0x0u, 0x42u },
+	});
+
+	TEST_EQ(data->used, true, "%d");
+	TEST_EQ(data->data[0], 0x7fffffffu, "%d");
+	TEST_EQ(data->data[1], 0x12345678u, "%d");
+	TEST_EQ(data->data[2], 0x0u, "%d");
+	TEST_EQ(data->data[3], 0x42u, "%d");
+
+	/* Call the destructor. */
+	data->~Wrapped();
+
+	TEST_ASSERT_MEMSET(buffer, 0, sizeof(Wrapped));
+
+	/* Free the space. */
+	free(buffer);
+
+	return EC_SUCCESS;
+}
+
+test_static enum ec_error_list test_cleanse_wrapper_normal_usage(void)
+{
+	struct TestingStruct {
+		bool used;
+		std::array<uint32_t, 4> data;
+	};
+
+	CleanseWrapper<std::array<uint8_t, 6> > array({ 1, 1, 1, 1, 1, 1 });
+
+	TEST_ASSERT_MEMSET(array.data(), 1, array.size());
+
+	CleanseWrapper<TestingStruct> data({
+		.used = true,
+		.data = { 0x7fffffffu, 0x12345678u, 0x0u, 0x42u },
+	});
+
+	TEST_EQ(data.used, true, "%d");
+	TEST_EQ(data.data[0], 0x7fffffffu, "%d");
+	TEST_EQ(data.data[1], 0x12345678u, "%d");
+	TEST_EQ(data.data[2], 0x0u, "%d");
+	TEST_EQ(data.data[3], 0x42u, "%d");
+
+	CleanseWrapper<struct sha256_ctx> ctx;
+
+	std::array<uint8_t, 5> data_to_sha = { 1, 2, 3, 4, 5 };
+	SHA256_init(&ctx);
+	SHA256_update(&ctx, data_to_sha.data(), data_to_sha.size());
+	uint8_t *result = SHA256_final(&ctx);
+
+	std::array<uint8_t, 32> expected_result = {
+		0X74, 0XF8, 0X1F, 0XE1, 0X67, 0XD9, 0X9B, 0X4C,
+		0XB4, 0X1D, 0X6D, 0X0C, 0XCD, 0XA8, 0X22, 0X78,
+		0XCA, 0XEE, 0X9F, 0X3E, 0X2F, 0X25, 0XD5, 0XE5,
+		0XA3, 0X93, 0X6F, 0XF3, 0XDC, 0XEC, 0X60, 0XD0,
+	};
+
+	TEST_ASSERT_ARRAY_EQ(result, expected_result, expected_result.size());
+
+	/* There is no way to check the context is cleared without undefined
+	 * behavior. */
+
+	return EC_SUCCESS;
+}
+
+extern "C" void run_test(int argc, const char **argv)
+{
+	RUN_TEST(test_rand);
+	RUN_TEST(test_ecc_keygen);
+	RUN_TEST(test_cleanse_wrapper_std_array);
+	RUN_TEST(test_cleanse_wrapper_sha256);
+	RUN_TEST(test_cleanse_wrapper_custom_struct);
+	RUN_TEST(test_cleanse_wrapper_normal_usage);
+	test_print_result();
+}
diff --git a/test/boringssl_crypto.tasklist b/test/boringssl_crypto.tasklist
new file mode 100644
index 0000000000..d1920322a9
--- /dev/null
+++ b/test/boringssl_crypto.tasklist
@@ -0,0 +1,9 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST
diff --git a/test/build.mk b/test/build.mk
index 0dd01347ed..f96c500983 100644
--- a/test/build.mk
+++ b/test/build.mk
@@ -1,10 +1,18 @@
 # -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
+# Copyright 2013 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 # Device test binaries
-test-list-y ?= flash_write_protect pingpong timer_calib timer_dos timer_jump mutex utils utils_str
+test-list-y ?= flash_write_protect \
+	pingpong \
+	stdlib \
+	timer_calib \
+	timer_dos \
+	timer_jump \
+	mutex \
+	utils \
+	utils_str
 #disable: powerdemo
 
 # Emulator tests
@@ -13,20 +21,26 @@ test-list-host=$(TEST_LIST_HOST)
 else
 test-list-host = accel_cal
 test-list-host += aes
+test-list-host += always_memset
 test-list-host += base32
+test-list-host += battery_config
 test-list-host += battery_get_params_smart
+test-list-host += benchmark
 test-list-host += bklight_lid
 test-list-host += bklight_passthru
 test-list-host += body_detection
+test-list-host += boringssl_crypto
 test-list-host += button
 test-list-host += cbi
+test-list-host += cbi_wp
 test-list-host += cec
 test-list-host += charge_manager
 test-list-host += charge_manager_drp_charging
 test-list-host += charge_ramp
+test-list-host += chipset
 test-list-host += compile_time_macros
 test-list-host += console_edit
-test-list-host += crc32
+test-list-host += crc
 test-list-host += entropy
 test-list-host += extpwr_gpio
 test-list-host += fan
@@ -34,23 +48,35 @@ test-list-host += flash
 test-list-host += float
 test-list-host += fp
 test-list-host += fpsensor
+test-list-host += fpsensor_auth_commands
+test-list-host += fpsensor_auth_crypto_stateful
+test-list-host += fpsensor_auth_crypto_stateless
 test-list-host += fpsensor_crypto
 test-list-host += fpsensor_state
+test-list-host += gettimeofday
 test-list-host += gyro_cal
 test-list-host += hooks
 test-list-host += host_command
 test-list-host += i2c_bitbang
 test-list-host += inductive_charging
-test-list-host += interrupt
+# This test times out in the CQ, and generally doesn't seem useful.
+# It is verifying the host test scheduler, which is never used in real boards.
+# test-list-host += interrupt
+test-list-host += irq_locking
 test-list-host += is_enabled
+ifeq ($(TEST_ASAN),)
+# is_enabled_error fails with TEST_ASAN
 test-list-host += is_enabled_error
+endif
 test-list-host += kasa
 test-list-host += kb_8042
 test-list-host += kb_mkbp
-#test-list-host += kb_scan	# crbug.com/976974
+test-list-host += kb_scan
+test-list-host += kb_scan_strict
 test-list-host += lid_sw
 test-list-host += lightbar
 test-list-host += mag_cal
+test-list-host += malloc
 test-list-host += math_util
 test-list-host += motion_angle
 test-list-host += motion_angle_tablet
@@ -58,29 +84,46 @@ test-list-host += motion_lid
 test-list-host += motion_sense_fifo
 test-list-host += mutex
 test-list-host += newton_fit
+test-list-host += nvidia_gpu
 test-list-host += online_calibration
+test-list-host += online_calibration_spoof
 test-list-host += pingpong
 test-list-host += power_button
 test-list-host += printf
 test-list-host += queue
+test-list-host += rgb_keyboard
+test-list-host += rollback_secret
 test-list-host += rsa
 test-list-host += rsa3
 test-list-host += rtc
-test-list-host += sbs_charging_v2
+test-list-host += sbrk
+test-list-host += sbs_charging
+test-list-host += scoped_fast_cpu
 test-list-host += sha256
 test-list-host += sha256_unrolled
 test-list-host += shmalloc
 test-list-host += static_if
 test-list-host += static_if_error
+# TODO(b/237823627): When building for the host, we're linking against the
+# toolchain's C standard library, so these tests are actually testing the
+# toolchain's C standard library.
+test-list-host += stdlib
+test-list-host += std_vector
 test-list-host += system
+test-list-host += tablet_broken_sensor
+test-list-host += tablet_no_sensor
 test-list-host += thermal
+test-list-host += timer
 test-list-host += timer_dos
 test-list-host += uptime
 test-list-host += usb_common
 test-list-host += usb_pd_int
 test-list-host += usb_pd
+test-list-host += usb_pd_console
 test-list-host += usb_pd_giveback
 test-list-host += usb_pd_rev30
+test-list-host += usb_pd_pdo_fixed
+test-list-host += usb_pd_timer
 test-list-host += usb_ppc
 test-list-host += usb_sm_framework_h3
 test-list-host += usb_sm_framework_h2
@@ -90,7 +133,7 @@ test-list-host += usb_typec_vpd
 test-list-host += usb_typec_ctvpd
 test-list-host += usb_typec_drp_acc_trysrc
 test-list-host += usb_prl_old
-test-list-host += usb_tcpmv2_tcpci
+test-list-host += usb_tcpmv2_compliance
 test-list-host += usb_prl
 test-list-host += usb_prl_noextended
 test-list-host += usb_pe_drp_old
@@ -100,8 +143,10 @@ test-list-host += usb_pe_drp_noextended
 test-list-host += utils
 test-list-host += utils_str
 test-list-host += vboot
+test-list-host += version
 test-list-host += x25519
 test-list-host += stillness_detector
+-include private/test/build.mk
 endif
 
 # Build up the list of coverage test targets based on test-list-host, but
@@ -117,85 +162,139 @@ cov-dont-test += fpsensor
 cov-dont-test += fpsensor_crypto
 # fpsensor_state: genhtml looks for build/host/fpsensor_state/cryptoc/util.c
 cov-dont-test += fpsensor_state
+# version: Only works in a chroot.
+cov-dont-test += version
+# interrupt: The test often times out if enabled for coverage.
+cov-dont-test += interrupt
+# Flaky tests. The number of covered lines changes from run to run
+# b/213374060
+cov-dont-test += accel_cal entropy flash float kb_mkbp kb_scan kb_scan_strict
+cov-dont-test += rsa
+
 cov-test-list-host = $(filter-out $(cov-dont-test), $(test-list-host))
 
+abort-y=abort.o
 accel_cal-y=accel_cal.o
 aes-y=aes.o
+# The purpose of the always_memset test is to ensure the functionality of
+# always_memset during high levels of optimization.
+%/test/always_memset.o: CFLAGS += -O3
+always_memset-y=always_memset.o
 base32-y=base32.o
+battery_config-y=battery_config.o
 battery_get_params_smart-y=battery_get_params_smart.o
+benchmark-y=benchmark.o
 bklight_lid-y=bklight_lid.o
 bklight_passthru-y=bklight_passthru.o
 body_detection-y=body_detection.o body_detection_data_literals.o motion_common.o
+boringssl_crypto-y=boringssl_crypto.o
 button-y=button.o
 cbi-y=cbi.o
+cbi_wp-y=cbi_wp.o
 cec-y=cec.o
-charge_manager-y=charge_manager.o
-charge_manager_drp_charging-y=charge_manager.o
+charge_manager-y=charge_manager.o fake_usbc.o
+charge_manager_drp_charging-y=charge_manager.o fake_usbc.o
 charge_ramp-y+=charge_ramp.o
+chipset-y+=chipset.o
 compile_time_macros-y=compile_time_macros.o
 console_edit-y=console_edit.o
-crc32-y=crc32.o
+cortexm_fpu-y=cortexm_fpu.o
+crc-y=crc.o
+debug-y=debug.o
 entropy-y=entropy.o
+exception-y=exception.o
 extpwr_gpio-y=extpwr_gpio.o
 fan-y=fan.o
 flash-y=flash.o
 flash_physical-y=flash_physical.o
 flash_write_protect-y=flash_write_protect.o
 fpsensor-y=fpsensor.o
+fpsensor_auth_commands-y=fpsensor_auth_commands.o
+fpsensor_auth_crypto_stateful-y=fpsensor_auth_crypto_stateful.o
+fpsensor_auth_crypto_stateless-y=fpsensor_auth_crypto_stateless.o
 fpsensor_crypto-y=fpsensor_crypto.o
+fpsensor_hw-y=fpsensor_hw.o
 fpsensor_state-y=fpsensor_state.o
-gyro_cal-y=gyro_cal.o
+ftrapv-y=ftrapv.o
+gettimeofday-y=gettimeofday.o
+global_initialization-y=global_initialization.o
+gyro_cal-y=gyro_cal.o gyro_cal_init_for_test.o
 hooks-y=hooks.o
 host_command-y=host_command.o
 i2c_bitbang-y=i2c_bitbang.o
 inductive_charging-y=inductive_charging.o
 interrupt-y=interrupt.o
+irq_locking-y=irq_locking.o
 is_enabled-y=is_enabled.o
 kb_8042-y=kb_8042.o
 kb_mkbp-y=kb_mkbp.o
 kb_scan-y=kb_scan.o
+kb_scan_strict-y=kb_scan.o
 lid_sw-y=lid_sw.o
 lightbar-y=lightbar.o
 mag_cal-y=mag_cal.o
+malloc-y=malloc.o
 math_util-y=math_util.o
 motion_angle-y=motion_angle.o motion_angle_data_literals.o motion_common.o
 motion_angle_tablet-y=motion_angle_tablet.o motion_angle_data_literals_tablet.o motion_common.o
 motion_lid-y=motion_lid.o
 motion_sense_fifo-y=motion_sense_fifo.o
+nvidia_gpu-y=nvidia_gpu.o
 online_calibration-y=online_calibration.o
+online_calibration_spoof-y=online_calibration_spoof.o gyro_cal_init_for_test.o
+rgb_keyboard-y=rgb_keyboard.o
 kasa-y=kasa.o
+ifeq ($(USE_BUILTIN_STDLIB), 0)
+libc_printf-y=libc_printf.o
+endif
+libcxx-y=libcxx.o
 mpu-y=mpu.o
 mutex-y=mutex.o
 newton_fit-y=newton_fit.o
+panic-y=panic.o
+panic_data-y=panic_data.o
 pingpong-y=pingpong.o
 power_button-y=power_button.o
 powerdemo-y=powerdemo.o
 printf-y=printf.o
 queue-y=queue.o
+rng_benchmark-y=rng_benchmark.o
 rollback-y=rollback.o
 rollback_entropy-y=rollback_entropy.o
+rollback_secret-y=rollback_secret.o
 rsa-y=rsa.o
 rsa3-y=rsa.o
 rtc-y=rtc.o
 scratchpad-y=scratchpad.o
+sbrk-y=sbrk.o
 sbs_charging-y=sbs_charging.o
-sbs_charging_v2-y=sbs_charging_v2.o
+scoped_fast_cpu-y=scoped_fast_cpu.o
 sha256-y=sha256.o
 sha256_unrolled-y=sha256.o
 shmalloc-y=shmalloc.o
 static_if-y=static_if.o
+stdlib-y=stdlib.o
+std_vector-y=std_vector.o
 stm32f_rtc-y=stm32f_rtc.o
 stress-y=stress.o
 system-y=system.o
+system_is_locked-y=system_is_locked.o
+tablet_broken_sensor-y=tablet_broken_sensor.o
+tablet_no_sensor-y=tablet_no_sensor.o
 thermal-y=thermal.o
 timer_calib-y=timer_calib.o
 timer_dos-y=timer_dos.o
+timer-y=timer.o
+tpm_seed_clear-y=tpm_seed_clear.o
 uptime-y=uptime.o
 usb_common-y=usb_common_test.o fake_battery.o
 usb_pd_int-y=usb_pd_int.o
 usb_pd-y=usb_pd.o
+usb_pd_console-y=usb_pd_console.o
 usb_pd_giveback-y=usb_pd.o
 usb_pd_rev30-y=usb_pd.o
+usb_pd_pdo_fixed-y=usb_pd_pdo_fixed_test.o
+usb_pd_timer-y=usb_pd_timer.o
 usb_ppc-y=usb_ppc.o
 usb_sm_framework_h3-y=usb_sm_framework_h3.o
 usb_sm_framework_h2-y=usb_sm_framework_h3.o
@@ -212,10 +311,26 @@ usb_pe_drp_old-y=usb_pe_drp_old.o usb_sm_checks.o fake_usbc.o
 usb_pe_drp_old_noextended-y=usb_pe_drp_old.o usb_sm_checks.o fake_usbc.o
 usb_pe_drp-y=usb_pe_drp.o usb_sm_checks.o
 usb_pe_drp_noextended-y=usb_pe_drp_noextended.o usb_sm_checks.o
-usb_tcpmv2_tcpci-y=usb_tcpmv2_tcpci.o vpd_api.o usb_sm_checks.o
+usb_tcpmv2_compliance-y=usb_tcpmv2_compliance.o usb_tcpmv2_compliance_common.o \
+	usb_tcpmv2_td_pd_ll_e3.o \
+	usb_tcpmv2_td_pd_ll_e4.o \
+	usb_tcpmv2_td_pd_ll_e5.o \
+	usb_tcpmv2_td_pd_src_e1.o \
+	usb_tcpmv2_td_pd_src_e2.o \
+	usb_tcpmv2_td_pd_src_e5.o \
+	usb_tcpmv2_td_pd_src3_e1.o \
+	usb_tcpmv2_td_pd_src3_e7.o \
+	usb_tcpmv2_td_pd_src3_e8.o \
+	usb_tcpmv2_td_pd_src3_e9.o \
+	usb_tcpmv2_td_pd_src3_e26.o \
+	usb_tcpmv2_td_pd_src3_e32.o \
+	usb_tcpmv2_td_pd_snk3_e12.o \
+	usb_tcpmv2_td_pd_vndi3_e3.o \
+	usb_tcpmv2_td_pd_other.o
 utils-y=utils.o
 utils_str-y=utils_str.o
 vboot-y=vboot.o
+version-y += version.o
 float-y=fp.o
 fp-y=fp.o
 x25519-y=x25519.o
@@ -226,3 +341,11 @@ is_enabled_error-y=is_enabled_error.o.cmd
 
 host-static_if_error: TEST_SCRIPT=static_if_error.sh
 static_if_error-y=static_if_error.o.cmd
+
+run-genvif_test:
+	@echo "  TEST    genvif_test"
+	@test/genvif/genvif.sh
+
+# This test requires C++ exceptions to be enabled.
+$(out)/RW/test/exception.o: CXXFLAGS+=-fexceptions
+$(out)/RO/test/exception.o: CXXFLAGS+=-fexceptions
diff --git a/test/button.c b/test/button.c
index e457eaa786..3a46625660 100644
--- a/test/button.c
+++ b/test/button.c
@@ -1,9 +1,9 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Test non-keyboard buttons.
-*
+ *
  * Using GPIOS and buttons[] defined in board/host/board.c
  * Volume down is active low with a debounce time of 30 mSec.
  * Volume up is active high with a debounce time of 60 mSec.
@@ -15,10 +15,10 @@
 #include "console.h"
 #include "gpio.h"
 #include "host_command.h"
-#include "test_util.h"
-#include "timer.h"
 #include "keyboard_config.h"
 #include "keyboard_protocol.h"
+#include "test_util.h"
+#include "timer.h"
 #include "util.h"
 
 #define UNCHANGED -1
@@ -272,7 +272,7 @@ static void button_test_init(void)
 		button_state[i] = UNCHANGED;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/button.tasklist b/test/button.tasklist
index 5a8fb1bfbe..e2f8671c60 100644
--- a/test/button.tasklist
+++ b/test/button.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/cbi.c b/test/cbi.c
index f0fe68f162..b0f2943bcf 100644
--- a/test/cbi.c
+++ b/test/cbi.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -13,14 +13,22 @@
 #include "i2c.h"
 #include "test_util.h"
 #include "util.h"
+#include "write_protect.h"
 
-void before_test(void)
+static void test_setup(void)
 {
+	/* Make sure that write protect is disabled */
+	write_protect_set(0);
+
 	cbi_create();
 	cbi_write();
 }
 
-static int test_uint8(void)
+static void test_teardown(void)
+{
+}
+
+DECLARE_EC_TEST(test_uint8)
 {
 	uint8_t d8;
 	uint32_t d32;
@@ -29,25 +37,27 @@ static int test_uint8(void)
 
 	/* Set & get uint8_t */
 	d8 = 0xa5;
-	TEST_ASSERT(cbi_set_board_info(tag, &d8, sizeof(d8)) == EC_SUCCESS);
+	zassert_equal(cbi_set_board_info(tag, &d8, sizeof(d8)), EC_SUCCESS,
+		      NULL);
 	size = 1;
-	TEST_ASSERT(cbi_get_board_info(tag, &d8, &size) == EC_SUCCESS);
-	TEST_EQ(d8, 0xa5, "0x%x");
-	TEST_EQ(size, 1, "%x");
+	zassert_equal(cbi_get_board_info(tag, &d8, &size), EC_SUCCESS);
+	zassert_equal(d8, 0xa5, "0x%x, 0x%x", d8, 0xa5);
+	zassert_equal(size, 1, "%x, %x", size, 1);
 
 	/* Size-up */
 	d32 = 0x1234abcd;
-	TEST_ASSERT(cbi_set_board_info(tag, (void *)&d32, sizeof(d32))
-		    == EC_SUCCESS);
+	zassert_equal(cbi_set_board_info(tag, (void *)&d32, sizeof(d32)),
+		      EC_SUCCESS, NULL);
 	size = 4;
-	TEST_ASSERT(cbi_get_board_info(tag, (void *)&d32, &size) == EC_SUCCESS);
-	TEST_EQ(d32, 0x1234abcd, "0x%x");
-	TEST_EQ(size, 4, "%u");
+	zassert_equal(cbi_get_board_info(tag, (void *)&d32, &size), EC_SUCCESS,
+		      NULL);
+	zassert_equal(d32, 0x1234abcd, "0x%x, 0x%x", d32, 0x1234abcd);
+	zassert_equal(size, 4, "%u, %u", size, 4);
 
 	return EC_SUCCESS;
 }
 
-static int test_uint32(void)
+DECLARE_EC_TEST(test_uint32)
 {
 	uint8_t d8;
 	uint32_t d32;
@@ -56,25 +66,27 @@ static int test_uint32(void)
 
 	/* Set & get uint32_t */
 	d32 = 0x1234abcd;
-	TEST_ASSERT(cbi_set_board_info(tag, (void *)&d32, sizeof(d32))
-			== EC_SUCCESS);
+	zassert_equal(cbi_set_board_info(tag, (void *)&d32, sizeof(d32)),
+		      EC_SUCCESS, NULL);
 	size = 4;
-	TEST_ASSERT(cbi_get_board_info(tag, (void *)&d32, &size) == EC_SUCCESS);
-	TEST_EQ(d32, 0x1234abcd, "0x%x");
-	TEST_EQ(size, 4, "%u");
+	zassert_equal(cbi_get_board_info(tag, (void *)&d32, &size), EC_SUCCESS,
+		      NULL);
+	zassert_equal(d32, 0x1234abcd, "0x%x, 0x%x", d32, 0x1234abcd);
+	zassert_equal(size, 4, "%u, %u", size, 4);
 
 	/* Size-down */
 	d8 = 0xa5;
-	TEST_ASSERT(cbi_set_board_info(tag, &d8, sizeof(d8)) == EC_SUCCESS);
+	zassert_equal(cbi_set_board_info(tag, &d8, sizeof(d8)), EC_SUCCESS,
+		      NULL);
 	size = 1;
-	TEST_ASSERT(cbi_get_board_info(tag, &d8, &size) == EC_SUCCESS);
-	TEST_EQ(d8, 0xa5, "0x%x");
-	TEST_EQ(size, 1, "%u");
+	zassert_equal(cbi_get_board_info(tag, &d8, &size), EC_SUCCESS);
+	zassert_equal(d8, 0xa5, "0x%x, 0x%x", d8, 0xa5);
+	zassert_equal(size, 1, "%u, %u", size, 1);
 
 	return EC_SUCCESS;
 }
 
-static int test_string(void)
+DECLARE_EC_TEST(test_string)
 {
 	const uint8_t string[] = "abcdefghijklmn";
 	uint8_t buf[32];
@@ -82,50 +94,57 @@ static int test_string(void)
 	const int tag = 0xff;
 
 	/* Set & get string */
-	TEST_ASSERT(cbi_set_board_info(tag, string, sizeof(string))
-		    == EC_SUCCESS);
+	zassert_equal(cbi_set_board_info(tag, string, sizeof(string)),
+		      EC_SUCCESS, NULL);
 	size = sizeof(buf);
-	TEST_ASSERT(cbi_get_board_info(tag, buf, &size) == EC_SUCCESS);
-	TEST_ASSERT(strncmp(buf, string, sizeof(string)) == 0);
+	zassert_equal(cbi_get_board_info(tag, buf, &size), EC_SUCCESS);
+	zassert_equal(strncmp(buf, string, sizeof(string)), 0);
 	/* Size contains null byte */
-	TEST_EQ((size_t)size - 1, strlen(buf), "%zu");
+	/* This should be zassert_equal, but for EC test fmt is always "0x%x"
+	 * which will generate compilation error.
+	 */
+	zassert_true((size_t)size - 1 == strlen(buf), "%zu, %zu",
+		     (size_t)size - 1, strlen(buf));
 
 	/* Read buffer too small */
 	size = 4;
-	TEST_ASSERT(cbi_get_board_info(tag, buf, &size) == EC_ERROR_INVAL);
+	zassert_equal(cbi_get_board_info(tag, buf, &size), EC_ERROR_INVAL,
+		      NULL);
 
 	return EC_SUCCESS;
 }
 
-static int test_not_found(void)
+DECLARE_EC_TEST(test_not_found)
 {
 	uint8_t d8;
 	const int tag = 0xff;
 	uint8_t size;
 
 	size = 1;
-	TEST_ASSERT(cbi_get_board_info(tag, &d8, &size) == EC_ERROR_UNKNOWN);
+	zassert_equal(cbi_get_board_info(tag, &d8, &size), EC_ERROR_UNKNOWN,
+		      NULL);
 
 	return EC_SUCCESS;
 }
 
-static int test_too_large(void)
+DECLARE_EC_TEST(test_too_large)
 {
-	uint8_t buf[CBI_EEPROM_SIZE-1];
+	uint8_t buf[CBI_IMAGE_SIZE - 1];
 	const int tag = 0xff;
 
 	/* Data too large */
 	memset(buf, 0xa5, sizeof(buf));
-	TEST_ASSERT(cbi_set_board_info(tag, buf, sizeof(buf))
-		    == EC_ERROR_OVERFLOW);
+	zassert_equal(cbi_set_board_info(tag, buf, sizeof(buf)),
+		      EC_ERROR_OVERFLOW, NULL);
 
 	return EC_SUCCESS;
 }
 
-static int test_all_tags(void)
+DECLARE_EC_TEST(test_all_tags)
 {
 	uint8_t d8;
 	uint32_t d32;
+	uint64_t d64;
 	const char string[] = "abc";
 	uint8_t buf[32];
 	uint8_t size;
@@ -133,73 +152,104 @@ static int test_all_tags(void)
 
 	/* Populate all data and read out */
 	d8 = 0x12;
-	TEST_ASSERT(cbi_set_board_info(CBI_TAG_BOARD_VERSION, &d8, sizeof(d8))
-		    == EC_SUCCESS);
+	zassert_equal(cbi_set_board_info(CBI_TAG_BOARD_VERSION, &d8,
+					 sizeof(d8)),
+		      EC_SUCCESS, NULL);
 	count++;
-	TEST_ASSERT(cbi_set_board_info(CBI_TAG_OEM_ID, &d8, sizeof(d8))
-		    == EC_SUCCESS);
+	zassert_equal(cbi_set_board_info(CBI_TAG_OEM_ID, &d8, sizeof(d8)),
+		      EC_SUCCESS, NULL);
 	count++;
-	TEST_ASSERT(cbi_set_board_info(CBI_TAG_SKU_ID, &d8, sizeof(d8))
-		    == EC_SUCCESS);
+	zassert_equal(cbi_set_board_info(CBI_TAG_SKU_ID, &d8, sizeof(d8)),
+		      EC_SUCCESS, NULL);
 	count++;
-	TEST_ASSERT(cbi_set_board_info(CBI_TAG_DRAM_PART_NUM,
-				       string, sizeof(string))
-		    == EC_SUCCESS);
+	zassert_equal(cbi_set_board_info(CBI_TAG_DRAM_PART_NUM, string,
+					 sizeof(string)),
+		      EC_SUCCESS, NULL);
 	count++;
-	TEST_ASSERT(cbi_set_board_info(CBI_TAG_OEM_NAME,
-				       string, sizeof(string))
-		    == EC_SUCCESS);
+	zassert_equal(cbi_set_board_info(CBI_TAG_OEM_NAME, string,
+					 sizeof(string)),
+		      EC_SUCCESS, NULL);
 	count++;
-	TEST_ASSERT(cbi_set_board_info(CBI_TAG_MODEL_ID, &d8, sizeof(d8))
-		    == EC_SUCCESS);
+	zassert_equal(cbi_set_board_info(CBI_TAG_MODEL_ID, &d8, sizeof(d8)),
+		      EC_SUCCESS, NULL);
 	count++;
-	TEST_ASSERT(cbi_set_board_info(CBI_TAG_FW_CONFIG, &d8, sizeof(d8))
-		    == EC_SUCCESS);
+	zassert_equal(cbi_set_board_info(CBI_TAG_FW_CONFIG, &d8, sizeof(d8)),
+		      EC_SUCCESS, NULL);
 	count++;
-	TEST_ASSERT(cbi_set_board_info(CBI_TAG_PCB_SUPPLIER, &d8, sizeof(d8))
-		    == EC_SUCCESS);
+	zassert_equal(cbi_set_board_info(CBI_TAG_PCB_SUPPLIER, &d8, sizeof(d8)),
+		      EC_SUCCESS, NULL);
 	count++;
-	TEST_ASSERT(cbi_set_board_info(CBI_TAG_SSFC, &d8, sizeof(d8))
-		    == EC_SUCCESS);
+	zassert_equal(cbi_set_board_info(CBI_TAG_SSFC, &d8, sizeof(d8)),
+		      EC_SUCCESS, NULL);
+	count++;
+	zassert_equal(cbi_set_board_info(CBI_TAG_REWORK_ID, &d8, sizeof(d8)),
+		      EC_SUCCESS, NULL);
+	count++;
+	zassert_equal(cbi_set_board_info(CBI_TAG_FACTORY_CALIBRATION_DATA, &d8,
+					 sizeof(d8)),
+		      EC_SUCCESS, NULL);
 	count++;
 
 	/* Read out all */
-	TEST_ASSERT(cbi_get_board_version(&d32) == EC_SUCCESS);
-	TEST_EQ(d32, d8, "0x%x");
-	TEST_ASSERT(cbi_get_oem_id(&d32) == EC_SUCCESS);
-	TEST_EQ(d32, d8, "0x%x");
-	TEST_ASSERT(cbi_get_sku_id(&d32) == EC_SUCCESS);
-	TEST_EQ(d32, d8, "0x%x");
+	zassert_equal(cbi_get_board_version(&d32), EC_SUCCESS);
+	zassert_equal(d32, d8, "0x%x, 0x%x", d32, d8);
+	zassert_equal(cbi_get_oem_id(&d32), EC_SUCCESS);
+	zassert_equal(d32, d8, "0x%x, 0x%x", d32, d8);
+	zassert_equal(cbi_get_sku_id(&d32), EC_SUCCESS);
+	zassert_equal(d32, d8, "0x%x, 0x%x", d32, d8);
 	size = sizeof(buf);
-	TEST_ASSERT(cbi_get_board_info(CBI_TAG_DRAM_PART_NUM, buf, &size)
-		    == EC_SUCCESS);
-	TEST_ASSERT(strncmp(buf, string, sizeof(string)) == 0);
-	TEST_EQ((size_t)size - 1, strlen(buf), "%zu");
+	zassert_equal(cbi_get_board_info(CBI_TAG_DRAM_PART_NUM, buf, &size),
+		      EC_SUCCESS, NULL);
+	zassert_equal(strncmp(buf, string, sizeof(string)), 0);
+	/* This should be zassert_equal, but for EC test fmt is always "0x%x"
+	 * which will generate compilation error.
+	 */
+	zassert_true((size_t)size - 1 == strlen(buf), "%zu, %zu",
+		     (size_t)size - 1, strlen(buf));
 	size = sizeof(buf);
-	TEST_ASSERT(cbi_get_board_info(CBI_TAG_OEM_NAME, buf, &size)
-		    == EC_SUCCESS);
-	TEST_ASSERT(strncmp(buf, string, sizeof(string)) == 0);
-	TEST_EQ((size_t)size - 1, strlen(buf), "%zu");
-	TEST_ASSERT(cbi_get_model_id(&d32) == EC_SUCCESS);
-	TEST_EQ(d32, d8, "0x%x");
-	TEST_ASSERT(cbi_get_fw_config(&d32) == EC_SUCCESS);
-	TEST_EQ(d32, d8, "0x%x");
-	TEST_ASSERT(cbi_get_pcb_supplier(&d32) == EC_SUCCESS);
-	TEST_EQ(d32, d8, "0x%x");
-	TEST_ASSERT(cbi_get_ssfc(&d32) == EC_SUCCESS);
-	TEST_EQ(d32, d8, "0x%x");
-
-	/* Fail if a (new) tag is missing from the unit test. */
-	TEST_EQ(count, CBI_TAG_COUNT, "%d");
+	zassert_equal(cbi_get_board_info(CBI_TAG_OEM_NAME, buf, &size),
+		      EC_SUCCESS, NULL);
+	zassert_equal(strncmp(buf, string, sizeof(string)), 0);
+	/* This should be zassert_equal, but for EC test fmt is always "0x%x"
+	 * which will generate compilation error.
+	 */
+	zassert_true((size_t)size - 1 == strlen(buf), "%zu, %zu",
+		     (size_t)size - 1, strlen(buf));
+	zassert_equal(cbi_get_model_id(&d32), EC_SUCCESS);
+	zassert_equal(d32, d8, "0x%x, 0x%x", d32, d8);
+	zassert_equal(cbi_get_fw_config(&d32), EC_SUCCESS);
+	zassert_equal(d32, d8, "0x%x, 0x%x", d32, d8);
+	zassert_equal(cbi_get_pcb_supplier(&d32), EC_SUCCESS);
+	zassert_equal(d32, d8, "0x%x, 0x%x", d32, d8);
+	zassert_equal(cbi_get_ssfc(&d32), EC_SUCCESS);
+	zassert_equal(d32, d8, "0x%x, 0x%x", d32, d8);
+	zassert_equal(cbi_get_factory_calibration_data(&d32), EC_SUCCESS);
+	zassert_equal(d32, d8, "0x%x, 0x%x", d32, d8);
+	zassert_equal(cbi_get_rework_id(&d64), EC_SUCCESS);
+	/* This should be zassert_equal, but for EC test fmt is always "0x%x"
+	 * which will generate compilation error.
+	 */
+	zassert_true((unsigned long long)d64 == (unsigned long long)d8,
+		     "0x%llx, 0x%llx", (unsigned long long)d64,
+		     (unsigned long long)d8);
+
+	/*
+	 * Fail if a (new) tag is missing from the unit test.
+	 *
+	 * Tags after FUEL_GAUGE_MANUF_NAME are tested in test/battery_config.c.
+	 * Since they don't have dedicated accessors, adding them here do not
+	 * exercise any new lines.
+	 */
+	zassert_equal(count, CBI_TAG_FUEL_GAUGE_MANUF_NAME);
 
 	/* Write protect */
-	gpio_set_level(GPIO_WP, 1);
-	TEST_ASSERT(cbi_write() == EC_ERROR_ACCESS_DENIED);
+	write_protect_set(1);
+	zassert_equal(cbi_write(), EC_ERROR_ACCESS_DENIED);
 
 	return EC_SUCCESS;
 }
 
-static int test_bad_crc(void)
+DECLARE_EC_TEST(test_bad_crc)
 {
 	uint8_t d8;
 	const int tag = 0xff;
@@ -208,27 +258,37 @@ static int test_bad_crc(void)
 
 	/* Bad CRC */
 	d8 = 0xa5;
-	TEST_ASSERT(cbi_set_board_info(tag, &d8, sizeof(d8)) == EC_SUCCESS);
+	zassert_equal(cbi_set_board_info(tag, &d8, sizeof(d8)), EC_SUCCESS,
+		      NULL);
 	i2c_read8(I2C_PORT_EEPROM, I2C_ADDR_EEPROM_FLAGS,
-		   offsetof(struct cbi_header, crc), &crc);
+		  offsetof(struct cbi_header, crc), &crc);
 	i2c_write8(I2C_PORT_EEPROM, I2C_ADDR_EEPROM_FLAGS,
 		   offsetof(struct cbi_header, crc), ++crc);
 	cbi_invalidate_cache();
 	size = sizeof(d8);
-	TEST_ASSERT(cbi_get_board_info(tag, &d8, &size) == EC_ERROR_UNKNOWN);
+	zassert_equal(cbi_get_board_info(tag, &d8, &size), EC_ERROR_UNKNOWN,
+		      NULL);
 
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+TEST_SUITE(test_suite_cbi)
 {
-	RUN_TEST(test_uint8);
-	RUN_TEST(test_uint32);
-	RUN_TEST(test_string);
-	RUN_TEST(test_not_found);
-	RUN_TEST(test_too_large);
-	RUN_TEST(test_all_tags);
-	RUN_TEST(test_bad_crc);
-
-	test_print_result();
+	ztest_test_suite(
+		test_cbi,
+		ztest_unit_test_setup_teardown(test_uint8, test_setup,
+					       test_teardown),
+		ztest_unit_test_setup_teardown(test_uint32, test_setup,
+					       test_teardown),
+		ztest_unit_test_setup_teardown(test_string, test_setup,
+					       test_teardown),
+		ztest_unit_test_setup_teardown(test_not_found, test_setup,
+					       test_teardown),
+		ztest_unit_test_setup_teardown(test_too_large, test_setup,
+					       test_teardown),
+		ztest_unit_test_setup_teardown(test_all_tags, test_setup,
+					       test_teardown),
+		ztest_unit_test_setup_teardown(test_bad_crc, test_setup,
+					       test_teardown));
+	ztest_run_test_suite(test_cbi);
 }
diff --git a/test/cbi.tasklist b/test/cbi.tasklist
index 52c0d390ef..08d31e0102 100644
--- a/test/cbi.tasklist
+++ b/test/cbi.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/cbi_wp.c b/test/cbi_wp.c
new file mode 100644
index 0000000000..705d860eeb
--- /dev/null
+++ b/test/cbi_wp.c
@@ -0,0 +1,55 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Test CBI EEPROM WP
+ */
+
+#include "common.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "gpio.h"
+#include "system.h"
+#include "test_util.h"
+#include "util.h"
+
+static int system_locked;
+
+static void test_setup(void)
+{
+	/* Make sure that write protect is disabled */
+	gpio_set_level(GPIO_WP, 0);
+	gpio_set_level(GPIO_EC_CBI_WP, 0);
+	system_locked = 0;
+}
+
+static void test_teardown(void)
+{
+}
+
+int system_is_locked(void)
+{
+	return system_locked;
+}
+
+DECLARE_EC_TEST(test_wp)
+{
+	int cbi_wp;
+
+	cbi_wp = gpio_get_level(GPIO_EC_CBI_WP);
+	zassert_equal(cbi_wp, 0);
+
+	cbi_latch_eeprom_wp();
+	cbi_wp = gpio_get_level(GPIO_EC_CBI_WP);
+	zassert_equal(cbi_wp, 1);
+
+	return EC_SUCCESS;
+}
+
+TEST_SUITE(test_suite_cbi_wp)
+{
+	ztest_test_suite(test_cbi_wp,
+			 ztest_unit_test_setup_teardown(test_wp, test_setup,
+							test_teardown));
+	ztest_run_test_suite(test_cbi_wp);
+}
diff --git a/test/cbi_wp.tasklist b/test/cbi_wp.tasklist
new file mode 100644
index 0000000000..cd866d90e1
--- /dev/null
+++ b/test/cbi_wp.tasklist
@@ -0,0 +1,9 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST  /* No test task */
diff --git a/test/cec.c b/test/cec.c
index 9377e4fcd3..6d385665a8 100644
--- a/test/cec.c
+++ b/test/cec.c
@@ -1,15 +1,15 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Test the buffer handling of HDMI CEC
  */
 
-#include <string.h>
-
 #include "cec.h"
 #include "test_util.h"
 
+#include <string.h>
+
 struct overflow_msg {
 	struct cec_msg_transfer transfer;
 	uint8_t overflow_detector;
@@ -18,7 +18,6 @@ struct overflow_msg {
 BUILD_ASSERT(offsetof(struct overflow_msg, overflow_detector) ==
 	     offsetof(struct cec_msg_transfer, buf) + MAX_CEC_MSG_LEN);
 
-
 struct overflow_queue {
 	struct cec_rx_queue queue;
 	uint8_t overflow_detector[CEC_RX_BUFFER_SIZE];
@@ -35,7 +34,7 @@ static int test_msg_overflow(void)
 	int i;
 
 	/* Overwrite the buffer by 1 byte */
-	for (i = 0; i < (MAX_CEC_MSG_LEN+1)*8; i++) {
+	for (i = 0; i < (MAX_CEC_MSG_LEN + 1) * 8; i++) {
 		cec_transfer_set_bit(&overflow_msg.transfer, 1);
 		cec_transfer_inc_bit(&overflow_msg.transfer);
 	}
@@ -60,8 +59,6 @@ static int test_msg_overflow(void)
 	return EC_SUCCESS;
 }
 
-
-
 static int verify_no_queue_overflow(void)
 {
 	int i;
@@ -73,11 +70,9 @@ static int verify_no_queue_overflow(void)
 	return EC_SUCCESS;
 }
 
-
 static void clear_queue(void)
 {
 	memset(queue, 0, sizeof(struct cec_rx_queue));
-
 }
 
 static int fill_queue(uint8_t *msg, int msg_size)
@@ -92,12 +87,12 @@ static int fill_queue(uint8_t *msg, int msg_size)
 	 */
 	clear_queue();
 
-	for (i = 0; i < (CEC_RX_BUFFER_SIZE - 1)/(msg_size + 1); i++)
+	for (i = 0; i < (CEC_RX_BUFFER_SIZE - 1) / (msg_size + 1); i++)
 		TEST_ASSERT(cec_rx_queue_push(queue, msg, msg_size) == 0);
 
 	/* Now the queue should be full */
 	TEST_ASSERT(cec_rx_queue_push(queue, msg, msg_size) ==
-							EC_ERROR_OVERFLOW);
+		    EC_ERROR_OVERFLOW);
 
 	/* Verify nothing was written outside of the queue */
 	TEST_ASSERT(verify_no_queue_overflow() == EC_SUCCESS);
@@ -119,7 +114,7 @@ static int test_queue_overflow(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	queue = &overflow_queue.queue;
 
diff --git a/test/cec.tasklist b/test/cec.tasklist
index e7634958a9..df71bfc0f9 100644
--- a/test/cec.tasklist
+++ b/test/cec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/test/charge_manager.c b/test/charge_manager.c
index 2a64ca3e98..9d1c888e9d 100644
--- a/test/charge_manager.c
+++ b/test/charge_manager.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -18,16 +18,11 @@
 
 /* Charge supplier priority: lower number indicates higher priority. */
 const int supplier_priority[] = {
-	[CHARGE_SUPPLIER_TEST1] = 0,
-	[CHARGE_SUPPLIER_TEST2] = 1,
-	[CHARGE_SUPPLIER_TEST3] = 1,
-	[CHARGE_SUPPLIER_TEST4] = 1,
-	[CHARGE_SUPPLIER_TEST5] = 3,
-	[CHARGE_SUPPLIER_TEST6] = 3,
-	[CHARGE_SUPPLIER_TEST7] = 5,
-	[CHARGE_SUPPLIER_TEST8] = 6,
-	[CHARGE_SUPPLIER_TEST9] = 6,
-	[CHARGE_SUPPLIER_TEST10] = 7,
+	[CHARGE_SUPPLIER_TEST1] = 0, [CHARGE_SUPPLIER_TEST2] = 1,
+	[CHARGE_SUPPLIER_TEST3] = 1, [CHARGE_SUPPLIER_TEST4] = 1,
+	[CHARGE_SUPPLIER_TEST5] = 3, [CHARGE_SUPPLIER_TEST6] = 3,
+	[CHARGE_SUPPLIER_TEST7] = 5, [CHARGE_SUPPLIER_TEST8] = 6,
+	[CHARGE_SUPPLIER_TEST9] = 6, [CHARGE_SUPPLIER_TEST10] = 7,
 };
 BUILD_ASSERT((int)CHARGE_SUPPLIER_COUNT == (int)CHARGE_SUPPLIER_TEST_COUNT);
 BUILD_ASSERT(ARRAY_SIZE(supplier_priority) == CHARGE_SUPPLIER_COUNT);
@@ -39,8 +34,8 @@ static int new_power_request[CONFIG_USB_PD_PORT_MAX_COUNT];
 static enum pd_power_role power_role[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 /* Callback functions called by CM on state change */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
 {
 	active_charge_limit = charge_ma;
 }
@@ -156,8 +151,8 @@ static int test_initialization(void)
 	TEST_ASSERT(active_charge_port == CHARGE_PORT_NONE);
 
 	/* Update last pair and verify a charge port has been selected */
-	charge_manager_update_charge(CHARGE_SUPPLIER_COUNT-1,
-				     board_get_usb_pd_port_count()-1,
+	charge_manager_update_charge(CHARGE_SUPPLIER_COUNT - 1,
+				     board_get_usb_pd_port_count() - 1,
 				     &charge);
 	wait_for_charge_manager_refresh();
 	TEST_ASSERT(active_charge_port != CHARGE_PORT_NONE);
@@ -787,7 +782,7 @@ static int test_unknown_dualrole_capability(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
@@ -801,5 +796,8 @@ void run_test(int argc, char **argv)
 	RUN_TEST(test_rejected_port);
 	RUN_TEST(test_unknown_dualrole_capability);
 
+	/* Some handlers are still running after the test ends. */
+	sleep(2);
+
 	test_print_result();
 }
diff --git a/test/charge_manager.mocklist b/test/charge_manager.mocklist
new file mode 100644
index 0000000000..69c74e9bcd
--- /dev/null
+++ b/test/charge_manager.mocklist
@@ -0,0 +1,6 @@
+#ifdef BOARD_HOST
+#define CONFIG_TEST_MOCK_LIST \
+	MOCK(ADC)             \
+	MOCK(BATTERY)         \
+
+#endif
diff --git a/test/charge_manager.tasklist b/test/charge_manager.tasklist
index 1f6f139a63..8c05d700ee 100644
--- a/test/charge_manager.tasklist
+++ b/test/charge_manager.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/charge_manager_drp_charging.mocklist b/test/charge_manager_drp_charging.mocklist
new file mode 120000
index 0000000000..0df9e2fdb0
--- /dev/null
+++ b/test/charge_manager_drp_charging.mocklist
@@ -0,0 +1 @@
+charge_manager.mocklist
\ No newline at end of file
diff --git a/test/charge_manager_drp_charging.tasklist b/test/charge_manager_drp_charging.tasklist
index e39c934e44..7b9e5153c4 100644
--- a/test/charge_manager_drp_charging.tasklist
+++ b/test/charge_manager_drp_charging.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/charge_ramp.c b/test/charge_ramp.c
index acffdadbf8..056fa67c21 100644
--- a/test/charge_ramp.c
+++ b/test/charge_ramp.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,7 +19,7 @@
 
 #define TASK_EVENT_OVERCURRENT (1 << 0)
 
-#define RAMP_STABLE_DELAY (120*SECOND)
+#define RAMP_STABLE_DELAY (120 * SECOND)
 
 /*
  * Time to delay for detecting the charger type. This value follows
@@ -27,7 +27,7 @@
  * CHARGE_DETECT_DELAY so we guarantee we wake up before the ramp
  * has started.
  */
-#define CHARGE_DETECT_DELAY_TEST (CHARGE_DETECT_DELAY - 100*MSEC)
+#define CHARGE_DETECT_DELAY_TEST (CHARGE_DETECT_DELAY - 100 * MSEC)
 
 static int system_load_current_ma;
 static int vbus_low_current_ma = 500;
@@ -73,12 +73,12 @@ int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
 	       vbus_low_current_ma;
 }
 
-void board_set_charge_limit(int port, int supplier, int limit_ma,
-			    int max_ma, int max_mv)
+__override void board_set_charge_limit(int port, int supplier, int limit_ma,
+				       int max_ma, int max_mv)
 {
 	charge_limit_ma = limit_ma;
 	if (charge_limit_ma > overcurrent_current_ma)
-		task_set_event(TASK_ID_TEST_RUNNER, TASK_EVENT_OVERCURRENT, 0);
+		task_set_event(TASK_ID_TEST_RUNNER, TASK_EVENT_OVERCURRENT);
 }
 
 /* Test utilities */
@@ -96,9 +96,8 @@ static void plug_charger_with_ts(int supplier_type, int port, int min_current,
 static void plug_charger(int supplier_type, int port, int min_current,
 			 int vbus_low_current, int overcurrent_current)
 {
-	plug_charger_with_ts(supplier_type, port, min_current,
-			     vbus_low_current, overcurrent_current,
-			     get_time());
+	plug_charger_with_ts(supplier_type, port, min_current, vbus_low_current,
+			     overcurrent_current, get_time());
 }
 
 static void unplug_charger(void)
@@ -137,7 +136,7 @@ static int test_no_ramp(void)
 	 * the charge limit.  This just needs at least transition to the
 	 * CHG_RAMP_OVERCURRENT_DETECT state.
 	 */
-	usleep(CHARGE_DETECT_DELAY_TEST + 200*MSEC);
+	usleep(CHARGE_DETECT_DELAY_TEST + 200 * MSEC);
 	/* That's right. Start at 500 mA */
 	TEST_ASSERT(charge_limit_ma == 500);
 	TEST_ASSERT(wait_stable_no_overcurrent());
@@ -442,14 +441,14 @@ static int test_equal_priority_overcurrent(void)
 	 * switches to the other one.
 	 */
 	while (1) {
-		plug_charger_with_ts(CHARGE_SUPPLIER_TEST4, 0, 500, 3000,
-				     2000, oc_time);
+		plug_charger_with_ts(CHARGE_SUPPLIER_TEST4, 0, 500, 3000, 2000,
+				     oc_time);
 		oc_time = get_time();
 		oc_time.val += 600 * MSEC;
 		if (wait_stable_no_overcurrent())
 			break;
-		plug_charger_with_ts(CHARGE_SUPPLIER_TEST4, 1, 500, 3000,
-				     2000, oc_time);
+		plug_charger_with_ts(CHARGE_SUPPLIER_TEST4, 1, 500, 3000, 2000,
+				     oc_time);
 		oc_time = get_time();
 		oc_time.val += 600 * MSEC;
 		if (wait_stable_no_overcurrent())
@@ -497,7 +496,7 @@ static int test_ramp_limit(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/charge_ramp.tasklist b/test/charge_ramp.tasklist
index 1e18846c75..ff0b0b7fd0 100644
--- a/test/charge_ramp.tasklist
+++ b/test/charge_ramp.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/chipset.c b/test/chipset.c
new file mode 100644
index 0000000000..6c9031e3f0
--- /dev/null
+++ b/test/chipset.c
@@ -0,0 +1,32 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Test chipset
+ */
+
+#define CONFIG_CMD_AP_RESET_LOG
+
+#include "chipset.h"
+#include "test_util.h"
+
+static int test_get_shutdown_reason(void)
+{
+	enum chipset_shutdown_reason reason = chipset_get_shutdown_reason();
+
+	TEST_ASSERT(reason == 0);
+	report_ap_reset(CHIPSET_SHUTDOWN_POWERFAIL);
+	reason = chipset_get_shutdown_reason();
+	TEST_ASSERT(reason == CHIPSET_SHUTDOWN_POWERFAIL);
+
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
+{
+	test_reset();
+
+	RUN_TEST(test_get_shutdown_reason);
+
+	test_print_result();
+}
diff --git a/test/chipset.tasklist b/test/chipset.tasklist
new file mode 100644
index 0000000000..45964224fe
--- /dev/null
+++ b/test/chipset.tasklist
@@ -0,0 +1,10 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST  \
+        TASK_TEST(CHIPSET, chipset_task, NULL, TASK_STACK_SIZE)
diff --git a/test/compile_time_macros.c b/test/compile_time_macros.c
index 40e962e101..2a22f0f276 100644
--- a/test/compile_time_macros.c
+++ b/test/compile_time_macros.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -6,12 +6,12 @@
  */
 
 #include "common.h"
+#include "stdbool.h"
 #include "test_util.h"
 
-
 static int test_BIT(void)
 {
-	TEST_EQ(BIT(0),  0x00000001U, "%u");
+	TEST_EQ(BIT(0), 0x00000001U, "%u");
 	TEST_EQ(BIT(25), 0x02000000U, "%u");
 	TEST_EQ(BIT(31), 0x80000000U, "%u");
 
@@ -20,7 +20,7 @@ static int test_BIT(void)
 
 static int test_BIT_ULL(void)
 {
-	TEST_EQ(BIT_ULL(0),  0x0000000000000001ULL, "%Lu");
+	TEST_EQ(BIT_ULL(0), 0x0000000000000001ULL, "%Lu");
 	TEST_EQ(BIT_ULL(25), 0x0000000002000000ULL, "%Lu");
 	TEST_EQ(BIT_ULL(50), 0x0004000000000000ULL, "%Lu");
 	TEST_EQ(BIT_ULL(63), 0x8000000000000000ULL, "%Lu");
@@ -28,12 +28,78 @@ static int test_BIT_ULL(void)
 	return EC_SUCCESS;
 }
 
+static int test_WRITE_MASK(void)
+{
+	uint8_t r8 __maybe_unused;
+	uint16_t r16 __maybe_unused;
+	uint32_t r32 __maybe_unused;
+
+	r8 = 0;
+	WRITE_MASK(r8, BIT(0) | BIT(1) | BIT(5), true);
+	TEST_EQ(r8, 0x23, "%u");
+	WRITE_MASK(r8, BIT(0), false);
+	TEST_EQ(r8, 0x22, "%u");
+
+	r16 = 0;
+	WRITE_MASK(r16, BIT(0) | BIT(9) | BIT(15), true);
+	TEST_EQ(r16, 0x8201, "%u");
+	WRITE_MASK(r16, BIT(0), false);
+	TEST_EQ(r16, 0x8200, "%u");
+
+	r32 = 0;
+	WRITE_MASK(r32, BIT(0) | BIT(25) | BIT(31), true);
+	TEST_EQ(r32, 0x82000001, "%u");
+	WRITE_MASK(r32, BIT(0), false);
+	TEST_EQ(r32, 0x82000000, "%u");
+
+	return EC_SUCCESS;
+}
+
+static int test_WRITE_BIT(void)
+{
+	uint8_t r8 __maybe_unused;
+	uint16_t r16 __maybe_unused;
+	uint32_t r32 __maybe_unused;
+
+	r8 = 0;
+	WRITE_BIT(r8, 0, true);
+	TEST_EQ(r8, 0x01, "%u");
+	WRITE_BIT(r8, 1, true);
+	TEST_EQ(r8, 0x03, "%u");
+	WRITE_BIT(r8, 5, true);
+	TEST_EQ(r8, 0x23, "%u");
+	WRITE_BIT(r8, 0, false);
+	TEST_EQ(r8, 0x22, "%u");
+
+	r16 = 0;
+	WRITE_BIT(r16, 0, true);
+	TEST_EQ(r16, 0x0001, "%u");
+	WRITE_BIT(r16, 9, true);
+	TEST_EQ(r16, 0x0201, "%u");
+	WRITE_BIT(r16, 15, true);
+	TEST_EQ(r16, 0x8201, "%u");
+	WRITE_BIT(r16, 0, false);
+	TEST_EQ(r16, 0x8200, "%u");
+
+	r32 = 0;
+	WRITE_BIT(r32, 0, true);
+	TEST_EQ(r32, 0x00000001, "%u");
+	WRITE_BIT(r32, 25, true);
+	TEST_EQ(r32, 0x02000001, "%u");
+	WRITE_BIT(r32, 31, true);
+	TEST_EQ(r32, 0x82000001, "%u");
+	WRITE_BIT(r32, 0, false);
+	TEST_EQ(r32, 0x82000000, "%u");
+
+	return EC_SUCCESS;
+}
+
 static int test_GENMASK(void)
 {
-	TEST_EQ(GENMASK(0, 0),   0x00000001U, "%u");
-	TEST_EQ(GENMASK(31, 0),  0xFFFFFFFFU, "%u");
-	TEST_EQ(GENMASK(4, 4),   0x00000010U, "%u");
-	TEST_EQ(GENMASK(4, 0),   0x0000001FU, "%u");
+	TEST_EQ(GENMASK(0, 0), 0x00000001U, "%u");
+	TEST_EQ(GENMASK(31, 0), 0xFFFFFFFFU, "%u");
+	TEST_EQ(GENMASK(4, 4), 0x00000010U, "%u");
+	TEST_EQ(GENMASK(4, 0), 0x0000001FU, "%u");
 	TEST_EQ(GENMASK(21, 21), 0x00200000U, "%u");
 	TEST_EQ(GENMASK(31, 31), 0x80000000U, "%u");
 
@@ -42,11 +108,11 @@ static int test_GENMASK(void)
 
 static int test_GENMASK_ULL(void)
 {
-	TEST_EQ(GENMASK_ULL(0, 0),   0x0000000000000001ULL, "%Lu");
-	TEST_EQ(GENMASK_ULL(31, 0),  0x00000000FFFFFFFFULL, "%Lu");
-	TEST_EQ(GENMASK_ULL(63, 0),  0xFFFFFFFFFFFFFFFFULL, "%Lu");
-	TEST_EQ(GENMASK_ULL(4, 4),   0x0000000000000010ULL, "%Lu");
-	TEST_EQ(GENMASK_ULL(4, 0),   0x000000000000001FULL, "%Lu");
+	TEST_EQ(GENMASK_ULL(0, 0), 0x0000000000000001ULL, "%Lu");
+	TEST_EQ(GENMASK_ULL(31, 0), 0x00000000FFFFFFFFULL, "%Lu");
+	TEST_EQ(GENMASK_ULL(63, 0), 0xFFFFFFFFFFFFFFFFULL, "%Lu");
+	TEST_EQ(GENMASK_ULL(4, 4), 0x0000000000000010ULL, "%Lu");
+	TEST_EQ(GENMASK_ULL(4, 0), 0x000000000000001FULL, "%Lu");
 	TEST_EQ(GENMASK_ULL(21, 21), 0x0000000000200000ULL, "%Lu");
 	TEST_EQ(GENMASK_ULL(31, 31), 0x0000000080000000ULL, "%Lu");
 	TEST_EQ(GENMASK_ULL(63, 63), 0x8000000000000000ULL, "%Lu");
@@ -55,14 +121,28 @@ static int test_GENMASK_ULL(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+test_static int test_IS_ARRAY(void)
+{
+	int array[5];
+	int *pointer = array;
+
+	TEST_EQ(_IS_ARRAY(array), true, "%d");
+	TEST_EQ(_IS_ARRAY(pointer), false, "%d");
+
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
 	RUN_TEST(test_BIT);
 	RUN_TEST(test_BIT_ULL);
+	RUN_TEST(test_WRITE_MASK);
+	RUN_TEST(test_WRITE_BIT);
 	RUN_TEST(test_GENMASK);
 	RUN_TEST(test_GENMASK_ULL);
+	RUN_TEST(test_IS_ARRAY);
 
 	test_print_result();
 }
diff --git a/test/compile_time_macros.tasklist b/test/compile_time_macros.tasklist
index 5ffe662d01..2d4595f76a 100644
--- a/test/compile_time_macros.tasklist
+++ b/test/compile_time_macros.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/console_edit.c b/test/console_edit.c
index 8d0721c14e..5ec649be5f 100644
--- a/test/console_edit.c
+++ b/test/console_edit.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -7,21 +7,23 @@
 
 #include "common.h"
 #include "console.h"
+#include "ec_commands.h"
 #include "test_util.h"
 #include "timer.h"
+#include "uart.h"
 #include "util.h"
 
 static int cmd_1_call_cnt;
 static int cmd_2_call_cnt;
 
-static int command_test_1(int argc, char **argv)
+static int command_test_1(int argc, const char **argv)
 {
 	cmd_1_call_cnt++;
 	return EC_SUCCESS;
 }
 DECLARE_CONSOLE_COMMAND(test1, command_test_1, NULL, NULL);
 
-static int command_test_2(int argc, char **argv)
+static int command_test_2(int argc, const char **argv)
 {
 	cmd_2_call_cnt++;
 	return EC_SUCCESS;
@@ -40,7 +42,7 @@ enum arrow_key_t {
 
 static void arrow_key(enum arrow_key_t k, int repeat)
 {
-	static char seq[4] = {0x1B, '[', 0, 0};
+	static char seq[4] = { 0x1B, '[', 0, 0 };
 	seq[2] = 'A' + k;
 	while (repeat--)
 		UART_INJECT(seq);
@@ -63,7 +65,7 @@ static void end_key(void)
 
 static void ctrl_key(char c)
 {
-	static char seq[2] = {0, 0};
+	static char seq[2] = { 0, 0 };
 	seq[0] = c - '@';
 	UART_INJECT(seq);
 }
@@ -98,7 +100,8 @@ static int test_backspace(void)
 	cmd_1_call_cnt = 0;
 	UART_INJECT("testx\b1\n");
 	msleep(30);
-	TEST_CHECK(cmd_1_call_cnt == 1);
+	TEST_ASSERT(cmd_1_call_cnt == 1);
+	return EC_SUCCESS;
 }
 
 static int test_insert_char(void)
@@ -108,7 +111,8 @@ static int test_insert_char(void)
 	arrow_key(ARROW_LEFT, 2);
 	UART_INJECT("s\n");
 	msleep(30);
-	TEST_CHECK(cmd_1_call_cnt == 1);
+	TEST_ASSERT(cmd_1_call_cnt == 1);
+	return EC_SUCCESS;
 }
 
 static int test_delete_char(void)
@@ -118,7 +122,8 @@ static int test_delete_char(void)
 	arrow_key(ARROW_LEFT, 1);
 	UART_INJECT("\b\n");
 	msleep(30);
-	TEST_CHECK(cmd_1_call_cnt == 1);
+	TEST_ASSERT(cmd_1_call_cnt == 1);
+	return EC_SUCCESS;
 }
 
 static int test_insert_delete_char(void)
@@ -130,7 +135,8 @@ static int test_insert_delete_char(void)
 	arrow_key(ARROW_RIGHT, 1);
 	UART_INJECT("s\n");
 	msleep(30);
-	TEST_CHECK(cmd_1_call_cnt == 1);
+	TEST_ASSERT(cmd_1_call_cnt == 1);
+	return EC_SUCCESS;
 }
 
 static int test_home_end_key(void)
@@ -142,7 +148,8 @@ static int test_home_end_key(void)
 	end_key();
 	UART_INJECT("1\n");
 	msleep(30);
-	TEST_CHECK(cmd_1_call_cnt == 1);
+	TEST_ASSERT(cmd_1_call_cnt == 1);
+	return EC_SUCCESS;
 }
 
 static int test_ctrl_k(void)
@@ -153,7 +160,8 @@ static int test_ctrl_k(void)
 	ctrl_key('K');
 	UART_INJECT("\n");
 	msleep(30);
-	TEST_CHECK(cmd_1_call_cnt == 1);
+	TEST_ASSERT(cmd_1_call_cnt == 1);
+	return EC_SUCCESS;
 }
 
 static int test_history_up(void)
@@ -164,7 +172,8 @@ static int test_history_up(void)
 	arrow_key(ARROW_UP, 1);
 	UART_INJECT("\n");
 	msleep(30);
-	TEST_CHECK(cmd_1_call_cnt == 2);
+	TEST_ASSERT(cmd_1_call_cnt == 2);
+	return EC_SUCCESS;
 }
 
 static int test_history_up_up(void)
@@ -178,7 +187,8 @@ static int test_history_up_up(void)
 	arrow_key(ARROW_UP, 2);
 	UART_INJECT("\n");
 	msleep(30);
-	TEST_CHECK(cmd_1_call_cnt == 2 && cmd_2_call_cnt == 1);
+	TEST_ASSERT(cmd_1_call_cnt == 2 && cmd_2_call_cnt == 1);
+	return EC_SUCCESS;
 }
 
 static int test_history_up_up_down(void)
@@ -193,7 +203,8 @@ static int test_history_up_up_down(void)
 	arrow_key(ARROW_DOWN, 1);
 	UART_INJECT("\n");
 	msleep(30);
-	TEST_CHECK(cmd_1_call_cnt == 1 && cmd_2_call_cnt == 2);
+	TEST_ASSERT(cmd_1_call_cnt == 1 && cmd_2_call_cnt == 2);
+	return EC_SUCCESS;
 }
 
 static int test_history_edit(void)
@@ -205,7 +216,8 @@ static int test_history_edit(void)
 	arrow_key(ARROW_UP, 1);
 	UART_INJECT("\b2\n");
 	msleep(30);
-	TEST_CHECK(cmd_1_call_cnt == 1 && cmd_2_call_cnt == 1);
+	TEST_ASSERT(cmd_1_call_cnt == 1 && cmd_2_call_cnt == 1);
+	return EC_SUCCESS;
 }
 
 static int test_history_stash(void)
@@ -219,13 +231,14 @@ static int test_history_stash(void)
 	arrow_key(ARROW_DOWN, 1);
 	UART_INJECT("2\n");
 	msleep(30);
-	TEST_CHECK(cmd_1_call_cnt == 1 && cmd_2_call_cnt == 1);
+	TEST_ASSERT(cmd_1_call_cnt == 1 && cmd_2_call_cnt == 1);
+	return EC_SUCCESS;
 }
 
 static int test_history_list(void)
 {
 	const char *exp_output = "history\n" /* Input command */
-				 "test3\n"   /* Output 4 last commands */
+				 "test3\n" /* Output 4 last commands */
 				 "test4\n"
 				 "test5\n"
 				 "history\n"
@@ -258,8 +271,8 @@ static int test_output_channel(void)
 	cputs(CC_TASK, "shouldn't see this either\n");
 	cflush();
 	test_capture_console(0);
-	TEST_ASSERT(compare_multiline_string(test_get_captured_console(),
-					     "") == 0);
+	TEST_ASSERT(compare_multiline_string(test_get_captured_console(), "") ==
+		    0);
 	UART_INJECT("chan restore\n");
 	msleep(30);
 	test_capture_console(1);
@@ -273,7 +286,54 @@ static int test_output_channel(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+/* This test is identical to console::buf_notify_null in
+ * zephyr/test/drivers/default/src/console.c. Please keep them in sync to
+ * verify that uart_console_read_buffer works identically in legacy EC and
+ * zephyr.
+ */
+static int test_buf_notify_null(void)
+{
+	char buffer[100];
+	uint16_t write_count;
+
+	/* Flush the console buffer before we start. */
+	TEST_ASSERT(uart_console_read_buffer_init() == 0);
+
+	/* Write a nul char to the buffer. */
+	cprintf(CC_SYSTEM, "ab%cc", 0);
+	cflush();
+
+	/* Check if the nul is present in the buffer. */
+	TEST_ASSERT(uart_console_read_buffer_init() == 0);
+	TEST_ASSERT(uart_console_read_buffer(CONSOLE_READ_RECENT, buffer,
+					     sizeof(buffer),
+					     &write_count) == 0);
+	TEST_ASSERT(strncmp(buffer, "abc", 4) == 0);
+	TEST_EQ(write_count, 4, "%d");
+
+	return EC_SUCCESS;
+}
+
+static const char *large_string =
+	"This is a very long string, it will cause a buffer flush at "
+	"some point while printing to the shell. Long long text. Blah "
+	"blah. Long long text. Blah blah. Long long text. Blah blah."
+	"This is a very long string, it will cause a buffer flush at "
+	"some point while printing to the shell. Long long text. Blah "
+	"blah. Long long text. Blah blah. Long long text. Blah blah."
+	"This is a very long string, it will cause a buffer flush at "
+	"some point while printing to the shell. Long long text. Blah "
+	"blah. Long long text. Blah blah. Long long text. Blah blah.";
+static int test_cprints_overflow(void)
+{
+	TEST_GE(strlen(large_string), (size_t)CONFIG_UART_TX_BUF_SIZE, "%ld");
+
+	TEST_NE(cprints(CC_SYSTEM, large_string), 0, "%d");
+
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
@@ -290,6 +350,8 @@ void run_test(int argc, char **argv)
 	RUN_TEST(test_history_stash);
 	RUN_TEST(test_history_list);
 	RUN_TEST(test_output_channel);
+	RUN_TEST(test_buf_notify_null);
+	RUN_TEST(test_cprints_overflow);
 
 	test_print_result();
 }
diff --git a/test/console_edit.tasklist b/test/console_edit.tasklist
index da0ab6211a..100cb6b5bd 100644
--- a/test/console_edit.tasklist
+++ b/test/console_edit.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/cortexm_fpu.c b/test/cortexm_fpu.c
new file mode 100644
index 0000000000..04e9c442c6
--- /dev/null
+++ b/test/cortexm_fpu.c
@@ -0,0 +1,206 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cpu.h"
+#include "math.h"
+#include "registers.h"
+#include "task.h"
+#include "test_util.h"
+#include "time.h"
+
+static volatile uint32_t fpscr;
+static volatile bool fpu_irq_handled;
+
+/* Override default FPU interrupt handler. */
+void __keep fpu_irq(uint32_t excep_lr, uint32_t excep_sp)
+{
+	/*
+	 * Get address of exception FPU exception frame. FPCAR register points
+	 * to the beginning of allocated FPU exception frame on the stack.
+	 */
+	uint32_t *fpu_state = (uint32_t *)CPU_FPU_FPCAR;
+
+	fpscr = fpu_state[FPU_IDX_REG_FPSCR];
+
+	/* Clear FPSCR on stack. */
+	fpu_state[FPU_IDX_REG_FPSCR] &= ~FPU_FPSCR_EXC_FLAGS;
+
+	fpu_irq_handled = true;
+}
+
+/* Performs division without casting to double. */
+static float divf(float a, float b)
+{
+	float result;
+
+	asm volatile("fdivs %0, %1, %2" : "=w"(result) : "w"(a), "w"(b));
+
+	return result;
+}
+
+/*
+ * Expect underflow when dividing the smallest number that can be represented
+ * using floats.
+ */
+test_static int test_cortexm_fpu_underflow(void)
+{
+	float result;
+
+	fpscr = 0;
+	fpu_irq_handled = false;
+
+	result = divf(1.40130e-45f, 2.0f);
+
+	/*
+	 * On STM32H7 FPU interrupt is not triggered (see errata ES0392 Rev 8,
+	 * 2.1.2 Cortex-M7 FPU interrupt not present on NVIC line 81), so
+	 * trigger it from software.
+	 */
+	if (IS_ENABLED(CHIP_FAMILY_STM32H7))
+		task_trigger_irq(STM32_IRQ_FPU);
+
+	TEST_ASSERT(result == 0.0f);
+
+	/* Wait for asynchronous FPU interrupt. */
+	while (!fpu_irq_handled) {
+	}
+
+	TEST_ASSERT(fpscr & FPU_FPSCR_UFC);
+
+	return EC_SUCCESS;
+}
+
+/*
+ * Expect overflow when dividing the highest number that can be represented
+ * using floats by number smaller than < 1.0f.
+ */
+test_static int test_cortexm_fpu_overflow(void)
+{
+	float result;
+
+	fpscr = 0;
+	fpu_irq_handled = false;
+
+	result = divf(3.40282e38f, 0.5f);
+
+	/*
+	 * On STM32H7 FPU interrupt is not triggered (see errata ES0392 Rev 8,
+	 * 2.1.2 Cortex-M7 FPU interrupt not present on NVIC line 81), so
+	 * trigger it from software.
+	 */
+	if (IS_ENABLED(CHIP_FAMILY_STM32H7))
+		task_trigger_irq(STM32_IRQ_FPU);
+
+	TEST_ASSERT(isinf(result));
+
+	/* Wait for asynchronous FPU interrupt. */
+	while (!fpu_irq_handled) {
+	}
+
+	TEST_ASSERT(fpscr & FPU_FPSCR_OFC);
+
+	return EC_SUCCESS;
+}
+
+/* Expect Division By Zero exception when 1.0f/0.0f. */
+test_static int test_cortexm_fpu_division_by_zero(void)
+{
+	float result;
+
+	fpscr = 0;
+	fpu_irq_handled = false;
+
+	result = divf(1.0f, 0.0f);
+
+	/*
+	 * On STM32H7 FPU interrupt is not triggered (see errata ES0392 Rev 8,
+	 * 2.1.2 Cortex-M7 FPU interrupt not present on NVIC line 81), so
+	 * trigger it from software.
+	 */
+	if (IS_ENABLED(CHIP_FAMILY_STM32H7))
+		task_trigger_irq(STM32_IRQ_FPU);
+
+	TEST_ASSERT(isinf(result));
+
+	/* Wait for asynchronous FPU interrupt. */
+	while (!fpu_irq_handled) {
+	}
+
+	TEST_ASSERT(fpscr & FPU_FPSCR_DZC);
+
+	return EC_SUCCESS;
+}
+
+/* Expect Invalid Operation when trying to get square root of -1.0f. */
+test_static int test_cortexm_fpu_invalid_operation(void)
+{
+	float result;
+
+	fpscr = 0;
+	fpu_irq_handled = false;
+
+	result = sqrtf(-1.0f);
+
+	/*
+	 * On STM32H7 FPU interrupt is not triggered (see errata ES0392 Rev 8,
+	 * 2.1.2 Cortex-M7 FPU interrupt not present on NVIC line 81), so
+	 * trigger it from software.
+	 */
+	if (IS_ENABLED(CHIP_FAMILY_STM32H7))
+		task_trigger_irq(STM32_IRQ_FPU);
+
+	TEST_ASSERT(isnan(result));
+
+	/* Wait for asynchronous FPU interrupt. */
+	while (!fpu_irq_handled) {
+	}
+
+	TEST_ASSERT(fpscr & FPU_FPSCR_IOC);
+
+	return EC_SUCCESS;
+}
+
+/* Expect Inexact bit to be set when performing 2.0f/3.0f. */
+test_static int test_cortexm_fpu_inexact(void)
+{
+	float result;
+
+	fpscr = 0;
+	fpu_irq_handled = false;
+
+	result = divf(2.0f, 3.0f);
+
+	/*
+	 * Inexact bit doesn't generate interrupt, so we will trigger it from
+	 * software.
+	 */
+	task_trigger_irq(STM32_IRQ_FPU);
+
+	/* Check if result is not NaN nor infinity. */
+	TEST_ASSERT(!isnan(result) && !isinf(result));
+
+	/* Wait for asynchronous FPU interrupt. */
+	while (!fpu_irq_handled) {
+	}
+
+	TEST_ASSERT(fpscr & FPU_FPSCR_IXC);
+
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
+{
+	test_reset();
+
+	if (IS_ENABLED(CONFIG_FPU)) {
+		RUN_TEST(test_cortexm_fpu_underflow);
+		RUN_TEST(test_cortexm_fpu_overflow);
+		RUN_TEST(test_cortexm_fpu_division_by_zero);
+		RUN_TEST(test_cortexm_fpu_invalid_operation);
+		RUN_TEST(test_cortexm_fpu_inexact);
+	}
+
+	test_print_result();
+}
diff --git a/test/cortexm_fpu.tasklist b/test/cortexm_fpu.tasklist
new file mode 100644
index 0000000000..16313e9055
--- /dev/null
+++ b/test/cortexm_fpu.tasklist
@@ -0,0 +1,9 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST  /* no tasks */
diff --git a/test/crc.c b/test/crc.c
new file mode 100644
index 0000000000..cd0ad0f1cc
--- /dev/null
+++ b/test/crc.c
@@ -0,0 +1,112 @@
+/* Copyright 2016 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Tests crc32 sw implementation.
+ */
+
+#include "common.h"
+#include "console.h"
+#include "crc.h"
+#include "crc8.h"
+#include "test_util.h"
+#include "util.h"
+
+// test that static version matches context version
+static int test_static_version(void)
+{
+	uint32_t crc;
+	const uint32_t input = 0xdeadbeef;
+
+	crc32_ctx_init(&crc);
+	crc32_ctx_hash32(&crc, input);
+
+	crc32_init();
+	crc32_hash32(input);
+	TEST_ASSERT(crc32_result() == crc32_ctx_result(&crc));
+
+	crc32_init();
+	crc32_hash(&input, sizeof(input));
+	TEST_ASSERT(crc32_result() == crc32_ctx_result(&crc));
+
+	return EC_SUCCESS;
+}
+
+// test that context bytes at a time matches static word at time
+static int test_8(void)
+{
+	uint32_t crc;
+	const uint32_t input = 0xdeadbeef;
+	const uint8_t *p = (const uint8_t *)&input;
+	int i;
+
+	crc32_init();
+	crc32_hash32(input);
+
+	crc32_ctx_init(&crc);
+	for (i = 0; i < sizeof(input); ++i)
+		crc32_ctx_hash8(&crc, p[i]);
+
+	TEST_ASSERT(crc32_result() == crc32_ctx_result(&crc));
+
+	return EC_SUCCESS;
+}
+
+// http://www.febooti.com/products/filetweak/members/hash-and-crc/test-vectors/
+static int test_kat0(void)
+{
+	uint32_t crc;
+	int i;
+	const char input[] = "The quick brown fox jumps over the lazy dog";
+
+	crc32_ctx_init(&crc);
+	for (i = 0; i < strlen(input); ++i)
+		crc32_ctx_hash8(&crc, input[i]);
+	TEST_ASSERT(crc32_ctx_result(&crc) == 0x414fa339);
+
+	crc32_ctx_init(&crc);
+	crc32_ctx_hash(&crc, input, strlen(input));
+	TEST_ASSERT(crc32_ctx_result(&crc) == 0x414fa339);
+
+	return EC_SUCCESS;
+}
+
+static int test_cros_crc8(void)
+{
+	uint8_t buffer[10] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 8 };
+
+	int crc = cros_crc8(buffer, 10);
+
+	/* Verifies polynomial values of 0x07 representing x^8 + x^2 + x + 1 */
+	TEST_EQ(crc, 170, "%d");
+
+	return EC_SUCCESS;
+}
+
+static int test_crc16(void)
+{
+	uint8_t buffer[10] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 8 };
+
+	int crc = cros_crc16(buffer, 10, 0);
+
+	/*
+	 * Verifies polynomial values of 0x1021 representing X^16 + X^15 + X^2 +
+	 * 1
+	 */
+	TEST_EQ(crc, 60681, "%d");
+
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
+{
+	test_reset();
+
+	RUN_TEST(test_static_version);
+	RUN_TEST(test_8);
+	RUN_TEST(test_kat0);
+	RUN_TEST(test_cros_crc8);
+	RUN_TEST(test_crc16);
+
+	test_print_result();
+}
diff --git a/test/crc.tasklist b/test/crc.tasklist
new file mode 100644
index 0000000000..bf2309064a
--- /dev/null
+++ b/test/crc.tasklist
@@ -0,0 +1,9 @@
+/* Copyright 2016 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST
diff --git a/test/crc32.c b/test/crc32.c
deleted file mode 100644
index 3521bce4a9..0000000000
--- a/test/crc32.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Tests crc32 sw implementation.
- */
-
-#include "common.h"
-#include "console.h"
-#include "crc.h"
-#include "test_util.h"
-#include "util.h"
-
-// test that static version matches context version
-static int test_static_version(void)
-{
-	uint32_t crc;
-	const uint32_t input = 0xdeadbeef;
-
-	crc32_init();
-	crc32_hash32(input);
-
-	crc32_ctx_init(&crc);
-	crc32_ctx_hash32(&crc, input);
-
-	TEST_ASSERT(crc32_result() == crc32_ctx_result(&crc));
-
-	return EC_SUCCESS;
-}
-
-// test that context bytes at a time matches static word at time
-static int test_8(void)
-{
-	uint32_t crc;
-	const uint32_t input = 0xdeadbeef;
-	const uint8_t *p = (const uint8_t *) &input;
-	int i;
-
-	crc32_init();
-	crc32_hash32(input);
-
-	crc32_ctx_init(&crc);
-	for (i = 0; i < sizeof(input); ++i)
-		crc32_ctx_hash8(&crc, p[i]);
-
-	TEST_ASSERT(crc32_result() == crc32_ctx_result(&crc));
-
-	return EC_SUCCESS;
-}
-
-// http://www.febooti.com/products/filetweak/members/hash-and-crc/test-vectors/
-static int test_kat0(void)
-{
-	uint32_t crc;
-	int i;
-	const char input[] = "The quick brown fox jumps over the lazy dog";
-
-	crc32_ctx_init(&crc);
-	for (i = 0; i < strlen(input); ++i)
-		crc32_ctx_hash8(&crc, input[i]);
-	TEST_ASSERT(crc32_ctx_result(&crc) == 0x414fa339);
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_static_version);
-	RUN_TEST(test_8);
-	RUN_TEST(test_kat0);
-
-	test_print_result();
-}
diff --git a/test/crc32.tasklist b/test/crc32.tasklist
deleted file mode 100644
index f46a2eaa1d..0000000000
--- a/test/crc32.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST
diff --git a/test/debug.c b/test/debug.c
new file mode 100644
index 0000000000..2c637ab725
--- /dev/null
+++ b/test/debug.c
@@ -0,0 +1,47 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "debug.h"
+#include "string.h"
+#include "test_util.h"
+
+static bool debugger_connected;
+
+static void print_usage(void)
+{
+	ccprintf("usage: runtest [debugger|no_debugger]\n");
+}
+
+test_static int test_debugger_is_connected(void)
+{
+	ccprintf("debugger_is_connected: %d\n", debugger_connected);
+	TEST_EQ(debugger_is_connected(), debugger_connected, "%d");
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
+{
+	test_reset();
+
+	if (argc < 2) {
+		print_usage();
+		test_fail();
+		return;
+	}
+
+	if (strncmp(argv[1], "debugger", sizeof("debugger")) == 0)
+		debugger_connected = true;
+	else if (strncmp(argv[1], "no_debugger", sizeof("no_debugger")) == 0) {
+		debugger_connected = false;
+	} else {
+		print_usage();
+		test_fail();
+		return;
+	}
+
+	RUN_TEST(test_debugger_is_connected);
+	test_print_result();
+}
diff --git a/test/debug.tasklist b/test/debug.tasklist
new file mode 100644
index 0000000000..959f62ef79
--- /dev/null
+++ b/test/debug.tasklist
@@ -0,0 +1,9 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST
diff --git a/test/ec_gtest.h b/test/ec_gtest.h
new file mode 100644
index 0000000000..bf30a35724
--- /dev/null
+++ b/test/ec_gtest.h
@@ -0,0 +1,35 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ * @brief Tests that want to utilize googletest should include this header file.
+ *
+ * There's no need to include the googletest header files directly.
+ */
+
+#ifndef __CROS_EC_TEST_EC_GTEST_H
+#define __CROS_EC_TEST_EC_GTEST_H
+
+#include <gtest/gtest.h>
+
+static inline void run_all_googletest_tests()
+{
+	testing::InitGoogleTest();
+
+	int ret = RUN_ALL_TESTS();
+
+	if (ret == 0)
+		printf("Pass!\n");
+	else
+		printf("Fail!\n");
+}
+
+extern "C" void run_test(int, const char **)
+{
+	run_all_googletest_tests();
+}
+
+#endif /* __CROS_EC_TEST_EC_GTEST_H */
diff --git a/test/entropy.c b/test/entropy.c
index fb066a6c5b..abac349d76 100644
--- a/test/entropy.c
+++ b/test/entropy.c
@@ -1,12 +1,12 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Tests entropy source.
  */
 
-#include "console.h"
 #include "common.h"
+#include "console.h"
 #include "rollback.h"
 #include "test_util.h"
 #include "timer.h"
@@ -26,10 +26,10 @@ uint32_t log2(int32_t val)
 	int val1 = 31 - __builtin_clz(val);
 	int val2 = 32 - __builtin_clz(val - 1);
 
-	return log2_mult * (val1 + val2)/2;
+	return log2_mult * (val1 + val2) / 2;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	const int loopcount = 512;
 
@@ -52,7 +52,7 @@ void run_test(int argc, char **argv)
 		t1 = get_time();
 		if (i == 0)
 			ccprintf("Got %zd bytes in %" PRId64 " us\n",
-				sizeof(buffer), t1.val - t0.val);
+				 sizeof(buffer), t1.val - t0.val);
 
 		for (j = 0; j < sizeof(buffer); j++)
 			buckets[buffer[j]]++;
@@ -82,7 +82,7 @@ void run_test(int argc, char **argv)
 	ccprintf("\n");
 
 	ccprintf("Entropy: %u/1000 bits\n",
-		entropy * 1000 / (log2_mult * totalcount));
+		 entropy * 1000 / (log2_mult * totalcount));
 
 	/* We want at least 2 bits of entropy (out of a maximum of 8) */
 	if ((entropy / (log2_mult * totalcount)) >= 2)
diff --git a/test/entropy.tasklist b/test/entropy.tasklist
index 80072bb620..329f9a3d28 100644
--- a/test/entropy.tasklist
+++ b/test/entropy.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/exception.cc b/test/exception.cc
new file mode 100644
index 0000000000..bedc1c6f14
--- /dev/null
+++ b/test/exception.cc
@@ -0,0 +1,89 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <exception>
+
+extern "C" {
+#include "common.h"
+#include "panic.h"
+#include "system.h"
+#include "task.h"
+#include "test_util.h"
+}
+
+test_static int test_exception()
+{
+	try {
+		ccprintf("Throwing an exception\n");
+		throw std::exception();
+	} catch (std::exception &e) {
+		/*
+		 * Since we have exceptions disabled, we should not reach this.
+		 * Instead, the exception should cause a reboot.
+		 */
+		ccprintf("Caught exception\n");
+		return EC_ERROR_UNKNOWN;
+	}
+	return EC_ERROR_UNKNOWN;
+}
+
+test_static int test_panic_data()
+{
+	const uint32_t expected_reason = PANIC_SW_EXIT;
+	/* Note: The task_id can be found with the "taskinfo" command. */
+	const uint32_t expected_task_id = 5;
+	const uint8_t expected_exception = 0;
+
+	uint32_t reason = 0;
+	uint32_t info = 0;
+	uint8_t exception = UINT8_MAX;
+
+	panic_get_reason(&reason, &info, &exception);
+
+	TEST_EQ(reason, expected_reason, "%08x");
+	TEST_EQ(info, expected_task_id, "%d");
+	TEST_EQ(exception, expected_exception, "%d");
+
+	return EC_SUCCESS;
+}
+
+test_static void run_test_step1()
+{
+	test_set_next_step(TEST_STATE_STEP_2);
+	RUN_TEST(test_exception);
+}
+
+test_static void run_test_step2()
+{
+	RUN_TEST(test_panic_data);
+
+	if (test_get_error_count())
+		test_reboot_to_next_step(TEST_STATE_FAILED);
+	else
+		test_reboot_to_next_step(TEST_STATE_PASSED);
+}
+
+void test_run_step(uint32_t state)
+{
+	if (state & TEST_STATE_MASK(TEST_STATE_STEP_1)) {
+		run_test_step1();
+	} else if (state & TEST_STATE_MASK(TEST_STATE_STEP_2)) {
+		run_test_step2();
+	}
+}
+
+extern "C" int task_test(void *unused)
+{
+	if (IS_ENABLED(SECTION_IS_RW))
+		test_run_multistep();
+	return EC_SUCCESS;
+}
+
+extern "C" void run_test(int argc, const char **argv)
+{
+	test_reset();
+	msleep(30); /* Wait for TASK_ID_TEST to initialize */
+	task_wake(TASK_ID_TEST);
+}
diff --git a/test/exception.tasklist b/test/exception.tasklist
new file mode 100644
index 0000000000..273a9664c0
--- /dev/null
+++ b/test/exception.tasklist
@@ -0,0 +1,10 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST \
+  TASK_TEST(TEST, task_test, NULL, TASK_STACK_SIZE)
diff --git a/test/extpwr_gpio.c b/test/extpwr_gpio.c
index d1f77c9167..8a17a9580c 100644
--- a/test/extpwr_gpio.c
+++ b/test/extpwr_gpio.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -51,7 +51,7 @@ static int test_hook(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/extpwr_gpio.tasklist b/test/extpwr_gpio.tasklist
index da0ab6211a..100cb6b5bd 100644
--- a/test/extpwr_gpio.tasklist
+++ b/test/extpwr_gpio.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/fake_battery.c b/test/fake_battery.c
index 4442300572..9dabbb31d9 100644
--- a/test/fake_battery.c
+++ b/test/fake_battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/test/fake_usbc.c b/test/fake_usbc.c
index 0f92379b38..faaed19503 100644
--- a/test/fake_usbc.c
+++ b/test/fake_usbc.c
@@ -1,12 +1,13 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Test USB Type-C module.
  */
 #include "common.h"
-#include "usb_tc_sm.h"
 #include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usb_tc_sm.h"
 
 __overridable int pd_is_vbus_present(int port)
 {
@@ -14,17 +15,20 @@ __overridable int pd_is_vbus_present(int port)
 }
 
 __overridable void pd_request_data_swap(int port)
-{}
+{
+}
 
 __overridable void pd_request_power_swap(int port)
-{}
+{
+}
 
 void pd_request_vconn_swap_off(int port)
-{}
+{
+}
 
 void pd_request_vconn_swap_on(int port)
-{}
-
+{
+}
 
 static enum pd_data_role data_role;
 __overridable enum pd_data_role pd_get_data_role(int port)
@@ -56,16 +60,23 @@ __overridable enum pd_cable_plug tc_get_cable_plug(int port)
 	return PD_PLUG_FROM_DFP_UFP;
 }
 
+__overridable int pd_get_rev(int port, enum tcpci_msg_type type)
+{
+	return IS_ENABLED(CONFIG_USB_PD_REV30) ? PD_REV30 : PD_REV20;
+}
+
 int tc_check_vconn_swap(int port)
 {
 	return 0;
 }
 
 void tc_ctvpd_detected(int port)
-{}
+{
+}
 
 void tc_disc_ident_complete(int port)
-{}
+{
+}
 
 static int attached_snk;
 int tc_is_attached_snk(int port)
@@ -85,28 +96,36 @@ int tc_is_vconn_src(int port)
 }
 
 void tc_hard_reset_request(int port)
-{}
+{
+}
 
 void tc_hard_reset_complete(int port)
-{}
+{
+}
 
 void tc_partner_dr_data(int port, int en)
-{}
+{
+}
 
 void tc_partner_dr_power(int port, int en)
-{}
+{
+}
 
 void tc_partner_unconstrainedpower(int port, int en)
-{}
+{
+}
 
 void tc_partner_usb_comm(int port, int en)
-{}
+{
+}
 
 void tc_pd_connection(int port, int en)
-{}
+{
+}
 
 void tc_pr_swap_complete(int port, bool success)
-{}
+{
+}
 
 void tc_prs_snk_src_assert_rp(int port)
 {
@@ -121,16 +140,20 @@ void tc_prs_src_snk_assert_rd(int port)
 }
 
 void tc_src_power_off(int port)
-{}
+{
+}
 
 void tc_set_timeout(int port, uint64_t timeout)
-{}
+{
+}
 
 __overridable void tc_start_error_recovery(int port)
-{}
+{
+}
 
 __overridable void tc_snk_power_off(int port)
-{}
+{
+}
 
 __overridable void pe_invalidate_explicit_contract(int port)
 {
@@ -142,10 +165,17 @@ __overridable enum pd_dual_role_states pd_get_dual_role(int port)
 }
 
 __overridable void pd_dev_get_rw_hash(int port, uint16_t *dev_id,
-		uint8_t *rw_hash, uint32_t *current_image)
+				      uint8_t *rw_hash, uint32_t *current_image)
 {
 }
 
+__overridable int pd_dev_store_rw_hash(int port, uint16_t dev_id,
+				       uint32_t *rw_hash,
+				       uint32_t current_image)
+{
+	return 0;
+}
+
 __overridable int pd_comm_is_enabled(int port)
 {
 	return 0;
@@ -161,13 +191,18 @@ bool pd_capable(int port)
 	return true;
 }
 
+bool pd_waiting_on_partner_src_caps(int port)
+{
+	return false;
+}
+
 #ifndef CONFIG_TEST_USB_PE_SM
 enum idh_ptype get_usb_pd_mux_cable_type(int port)
 {
 	return IDH_PTYPE_UNDEF;
 }
 
-const uint32_t * const pd_get_src_caps(int port)
+const uint32_t *const pd_get_src_caps(int port)
 {
 	return NULL;
 }
@@ -182,8 +217,7 @@ uint8_t pd_get_src_cap_cnt(int port)
 }
 #endif
 
-#if !defined(CONFIG_USB_DRP_ACC_TRYSRC) && \
-	!defined(CONFIG_USB_CTVPD)
+#if !defined(CONFIG_USB_DRP_ACC_TRYSRC) && !defined(CONFIG_USB_CTVPD)
 int pd_is_connected(int port)
 {
 	return true;
@@ -236,11 +270,11 @@ const char *pd_get_task_state_name(int port)
 }
 #endif /* CONFIG_USB_DRP_ACC_TRYSRC */
 
-void dp_init(int port)
+void dfp_consume_attention(int port, uint32_t *payload)
 {
 }
 
-void dp_vdm_acked(int port, int cmd)
+void pd_prepare_sysjump(void)
 {
 }
 
@@ -248,17 +282,17 @@ void dpm_init(int port)
 {
 }
 
-void dpm_vdm_acked(int port, enum tcpm_transmit_type type, int vdo_count,
-		uint32_t *vdm)
+void dpm_mode_exit_complete(int port)
 {
 }
 
-void dp_teardown(int port)
+void dpm_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count,
+		   uint32_t *vdm)
 {
 }
 
-void dpm_vdm_naked(int port, enum tcpm_transmit_type type, uint16_t svid,
-		uint8_t vdm_cmd)
+void dpm_vdm_naked(int port, enum tcpci_msg_type type, uint16_t svid,
+		   uint8_t vdm_cmd, uint32_t vdm_header)
 {
 }
 
@@ -270,13 +304,64 @@ void dpm_set_mode_exit_request(int port)
 {
 }
 
-void dpm_run(int port)
+void dpm_notify_attention(int port, size_t vdo_objects, uint32_t *buf)
+{
+}
+
+void dpm_run(int port, int evt, int enable)
+{
+}
+
+void dpm_evaluate_sink_fixed_pdo(int port, uint32_t vsafe5v_pdo)
+{
+}
+
+void dpm_add_non_pd_sink(int port)
+{
+}
+
+void dpm_evaluate_request_rdo(int port, uint32_t rdo)
+{
+}
+
+void dpm_remove_sink(int port)
+{
+}
+
+void dpm_remove_source(int port)
+{
+}
+
+void dpm_bist_shared_mode_enter(int port)
+{
+}
+
+void dpm_bist_shared_mode_exit(int port)
+{
+}
+
+int dpm_get_source_pdo(const uint32_t **src_pdo, const int port)
+{
+	*src_pdo = pd_src_pdo;
+	return pd_src_pdo_cnt;
+}
+
+int dpm_get_status_msg(int port, uint8_t *msg, uint32_t *len)
+{
+	return EC_SUCCESS;
+}
+
+void dpm_handle_alert(int port, uint32_t ado)
+{
+}
+
+void dpm_set_pe_ready(int port, bool enable)
 {
 }
 
 static enum tcpc_rp_value lcl_rp;
 __overridable void typec_select_src_current_limit_rp(int port,
-						  enum tcpc_rp_value rp)
+						     enum tcpc_rp_value rp)
 {
 	lcl_rp = rp;
 }
diff --git a/test/fan.c b/test/fan.c
index d03aa0213c..48a019382b 100644
--- a/test/fan.c
+++ b/test/fan.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,14 +10,13 @@
 #include "fan.h"
 #include "hooks.h"
 #include "host_command.h"
-#include "printf.h"
 #include "temp_sensor.h"
 #include "test_util.h"
 #include "thermal.h"
 #include "timer.h"
 #include "util.h"
 
-#define FAN_RPM(fan)	fans[fan].rpm
+#define FAN_RPM(fan) fans[fan].rpm
 
 /*****************************************************************************/
 /* Tests */
@@ -105,9 +104,128 @@ static int test_fan(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+/* Provide a test driver to make test easier to read. */
+int temp_to_rpm(int temperature_c)
+{
+	const int temp_fan_off = C_TO_K(35);
+	const int temp_fan_max = C_TO_K(55);
+	const struct fan_step_1_1 fan_table[] = {
+		{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(35),
+		  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(41),
+		  .rpm = 2500 },
+		{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(37),
+		  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(43),
+		  .rpm = 3200 },
+		{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(42),
+		  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(45),
+		  .rpm = 3500 },
+		{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(44),
+		  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(47),
+		  .rpm = 3900 },
+		{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(46),
+		  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(49),
+		  .rpm = 4500 },
+		{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(48),
+		  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(52),
+		  .rpm = 5100 },
+		{ .decreasing_temp_ratio_threshold = TEMP_TO_RATIO(51),
+		  .increasing_temp_ratio_threshold = TEMP_TO_RATIO(55),
+		  .rpm = 5400 },
+	};
+	const int num_fan_levels = ARRAY_SIZE(fan_table);
+	int temp_ratio = TEMP_TO_RATIO(temperature_c);
+
+	int rpm = temp_ratio_to_rpm_hysteresis(fan_table, num_fan_levels, 0,
+					       temp_ratio, NULL);
+
+	fan_set_rpm_target(FAN_CH(0), rpm);
+	return rpm;
+}
+
+static int test_temp_ratio_to_rpm_hysteresis(void)
+{
+	const int ZERO = 0;
+	/* set initial value to be different so that a log message appears */
+	fan_set_rpm_target(FAN_CH(0), 5400);
+	/* initial turn-on behavior, ramp up. @ represents fan speed; + temp */
+	TEST_ASSERT(temp_to_rpm(30) == ZERO); /* @+. .   40    .   50    .60 */
+	TEST_ASSERT(temp_to_rpm(30) == ZERO); /* @+. .    .    .    .    .   */
+	TEST_ASSERT(temp_to_rpm(35) == ZERO); /* @   +    .    .    .    .   */
+	TEST_ASSERT(temp_to_rpm(37) == ZERO); /* @   . +  .    .    .    .   */
+	TEST_ASSERT(temp_to_rpm(39) == ZERO); /* @   .   +.    .    .    .   */
+	TEST_ASSERT(temp_to_rpm(40) == ZERO); /* @   .    +    .    .    .   */
+	TEST_ASSERT(temp_to_rpm(41) == 2500); /*    @.    .+   .    .    .   */
+	TEST_ASSERT(temp_to_rpm(36) == 2500); /*    @.+   .    .    .    .   */
+	TEST_ASSERT(temp_to_rpm(42) == 2500); /*    @.    . +  .    .    .   */
+	TEST_ASSERT(temp_to_rpm(43) == 3200); /*     @    .  + .    .    .   */
+	TEST_ASSERT(temp_to_rpm(38) == 3200); /*     @  + .    .    .    .   */
+	TEST_ASSERT(temp_to_rpm(44) == 3200); /*     @    .   +.    .    .   */
+	TEST_ASSERT(temp_to_rpm(45) == 3500); /*     .@   .    +    .    .   */
+	TEST_ASSERT(temp_to_rpm(43) == 3500); /*     .@   .  + .    .    .   */
+	TEST_ASSERT(temp_to_rpm(46) == 3500); /*     .@   .    .+   .    .   */
+	TEST_ASSERT(temp_to_rpm(47) == 3900); /*     . @  .    . +  .    .   */
+	TEST_ASSERT(temp_to_rpm(45) == 3900); /*     . @  .    +    .    .   */
+	TEST_ASSERT(temp_to_rpm(48) == 3900); /*     . @  .    .  + .    .   */
+	TEST_ASSERT(temp_to_rpm(49) == 4500); /*     .  @ .    .   +.    .   */
+	TEST_ASSERT(temp_to_rpm(47) == 4500); /*     .  @ .    . +  .    .   */
+	TEST_ASSERT(temp_to_rpm(51) == 4500); /*     .  @ .    .    .+   .   */
+	TEST_ASSERT(temp_to_rpm(52) == 5100); /*     .   @.    .    . +  .   */
+	TEST_ASSERT(temp_to_rpm(49) == 5100); /*     .   @.    .   +.    .   */
+	TEST_ASSERT(temp_to_rpm(54) == 5100); /*     .   @.    .    .   +.   */
+	TEST_ASSERT(temp_to_rpm(55) == 5400); /*     .    @    .    .    +   */
+	TEST_ASSERT(temp_to_rpm(52) == 5400); /*     .    @    .    . +  .   */
+	TEST_ASSERT(temp_to_rpm(60) == 5400); /*     .    @    .   50    ..+ */
+	/* cool-down */
+	TEST_ASSERT(temp_to_rpm(55) == 5400); /*     .    @    .    .    +   */
+	TEST_ASSERT(temp_to_rpm(52) == 5400); /*     .    @    .    . +  .   */
+	TEST_ASSERT(temp_to_rpm(51) == 5100); /*     .   @.    .    .+   .   */
+	TEST_ASSERT(temp_to_rpm(54) == 5100); /*     .   @.    .    .   +.   */
+	TEST_ASSERT(temp_to_rpm(49) == 5100); /*     .   @.    .   +.    .   */
+	TEST_ASSERT(temp_to_rpm(48) == 4500); /*     .  @ .    .  + .    .   */
+	TEST_ASSERT(temp_to_rpm(51) == 4500); /*     .  @ .    .    .+   .   */
+	TEST_ASSERT(temp_to_rpm(47) == 4500); /*     .  @ .    . +  .    .   */
+	TEST_ASSERT(temp_to_rpm(46) == 3900); /*     . @  .    .+   .    .   */
+	TEST_ASSERT(temp_to_rpm(48) == 3900); /*     . @  .    .  + .    .   */
+	TEST_ASSERT(temp_to_rpm(45) == 3900); /*     . @  .    +    .    .   */
+	TEST_ASSERT(temp_to_rpm(44) == 3500); /*     .@   .   +.    .    .   */
+	TEST_ASSERT(temp_to_rpm(46) == 3500); /*     .@   .    .+   .    .   */
+	TEST_ASSERT(temp_to_rpm(43) == 3500); /*     .@   .  + .    .    .   */
+	TEST_ASSERT(temp_to_rpm(42) == 3200); /*     @    . +  .    .    .   */
+	TEST_ASSERT(temp_to_rpm(44) == 3200); /*     @    .   +.    .    .   */
+	TEST_ASSERT(temp_to_rpm(38) == 3200); /*     @  + .    .    .    .   */
+	TEST_ASSERT(temp_to_rpm(37) == 2500); /*    @. +  .    .    .    .   */
+	TEST_ASSERT(temp_to_rpm(42) == 2500); /*    @.    . +  .    .    .   */
+	TEST_ASSERT(temp_to_rpm(36) == 2500); /*    @.+   .    .    .    .   */
+	TEST_ASSERT(temp_to_rpm(35) == ZERO); /* @   +   40    .   50    .   */
+	/* warm up again */
+	TEST_ASSERT(temp_to_rpm(38) == ZERO); /* @   .  + .    .    .    .   */
+	/* jumping */
+	TEST_ASSERT(temp_to_rpm(46) == 3500); /*     .@   .    .+   .    .   */
+	TEST_ASSERT(temp_to_rpm(36) == 2500); /*    @.+   .    .    .    .   */
+	TEST_ASSERT(temp_to_rpm(35) == ZERO); /* @   +    .    .    .    .   */
+	TEST_ASSERT(temp_to_rpm(37) == ZERO); /* @   . +  .    .    .    .   */
+	TEST_ASSERT(temp_to_rpm(46) == 3500); /*     .@   .    .+   .    .   */
+	TEST_ASSERT(temp_to_rpm(54) == 5100); /*     .   @.    .    .   +.   */
+	TEST_ASSERT(temp_to_rpm(55) == 5400); /*     .    @    .    .    +   */
+	TEST_ASSERT(temp_to_rpm(60) == 5400); /*     .    @    .    .    ..+ */
+	TEST_ASSERT(temp_to_rpm(53) == 5400); /*     .    @    .    .  + .   */
+	TEST_ASSERT(temp_to_rpm(46) == 3900); /*     . @  .    .+   .    .   */
+	TEST_ASSERT(temp_to_rpm(30) == ZERO); /* @+. .   40    .   50    .   */
+
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
 {
 	RUN_TEST(test_fan);
+	RUN_TEST(test_temp_ratio_to_rpm_hysteresis);
 
 	test_print_result();
 }
+
+/* Doesn't do anything, but it makes this test stop intermittently covering
+ * some code in core/host/task.c:fast_forward().
+ */
+void interrupt_generator(void)
+{
+}
diff --git a/test/fan.tasklist b/test/fan.tasklist
index 25dcf124db..836bdd08ed 100644
--- a/test/fan.tasklist
+++ b/test/fan.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/flash.c b/test/flash.c
index 401e2bd6f4..bd1b646f1f 100644
--- a/test/flash.c
+++ b/test/flash.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -103,60 +103,59 @@ static int verify_erase(int offset, int size)
 	return EC_SUCCESS;
 }
 
-
-#define VERIFY_NO_WRITE(off, sz, d) \
-	do { \
-		record_flash(off, sz); \
+#define VERIFY_NO_WRITE(off, sz, d)                                        \
+	do {                                                               \
+		record_flash(off, sz);                                     \
 		TEST_ASSERT(host_command_write(off, sz, d) != EC_SUCCESS); \
-		TEST_ASSERT(verify_flash(off, sz) == EC_SUCCESS); \
+		TEST_ASSERT(verify_flash(off, sz) == EC_SUCCESS);          \
 	} while (0)
 
-#define VERIFY_NO_ERASE(off, sz) \
-	do { \
-		record_flash(off, sz); \
+#define VERIFY_NO_ERASE(off, sz)                                        \
+	do {                                                            \
+		record_flash(off, sz);                                  \
 		TEST_ASSERT(host_command_erase(off, sz) != EC_SUCCESS); \
-		TEST_ASSERT(verify_flash(off, sz) == EC_SUCCESS); \
+		TEST_ASSERT(verify_flash(off, sz) == EC_SUCCESS);       \
 	} while (0)
 
-#define VERIFY_WRITE(off, sz, d) \
-	do { \
+#define VERIFY_WRITE(off, sz, d)                                           \
+	do {                                                               \
 		TEST_ASSERT(host_command_write(off, sz, d) == EC_SUCCESS); \
-		TEST_ASSERT(verify_write(off, sz, d) == EC_SUCCESS); \
+		TEST_ASSERT(verify_write(off, sz, d) == EC_SUCCESS);       \
 	} while (0)
 
-#define VERIFY_ERASE(off, sz) \
-	do { \
+#define VERIFY_ERASE(off, sz)                                           \
+	do {                                                            \
 		TEST_ASSERT(host_command_erase(off, sz) == EC_SUCCESS); \
-		TEST_ASSERT(verify_erase(off, sz) == EC_SUCCESS); \
+		TEST_ASSERT(verify_erase(off, sz) == EC_SUCCESS);       \
 	} while (0)
 
-#define SET_WP_FLAGS(m, f) \
-	TEST_ASSERT(host_command_protect(m, ((f) ? m : 0), \
-				NULL, NULL, NULL) == EC_RES_SUCCESS)
+#define SET_WP_FLAGS(m, f)                                             \
+	TEST_ASSERT(host_command_protect(m, ((f) ? m : 0), NULL, NULL, \
+					 NULL) == EC_RES_SUCCESS)
 
-#define ASSERT_WP_FLAGS(f) \
-	do { \
-		uint32_t flags; \
+#define ASSERT_WP_FLAGS(f)                                                    \
+	do {                                                                  \
+		uint32_t flags;                                               \
 		TEST_ASSERT(host_command_protect(0, 0, &flags, NULL, NULL) == \
-			    EC_RES_SUCCESS); \
-		TEST_ASSERT(flags & (f)); \
+			    EC_RES_SUCCESS);                                  \
+		TEST_ASSERT(flags &(f));                                      \
 	} while (0)
 
-#define ASSERT_WP_NO_FLAGS(f) \
-	do { \
-		uint32_t flags; \
+#define ASSERT_WP_NO_FLAGS(f)                                                 \
+	do {                                                                  \
+		uint32_t flags;                                               \
 		TEST_ASSERT(host_command_protect(0, 0, &flags, NULL, NULL) == \
-			    EC_RES_SUCCESS); \
-		TEST_ASSERT((flags & (f)) == 0); \
+			    EC_RES_SUCCESS);                                  \
+		TEST_ASSERT((flags & (f)) == 0);                              \
 	} while (0)
 
-#define VERIFY_REGION_INFO(r, o, s) \
-	do { \
-		uint32_t offset, size; \
+#define VERIFY_REGION_INFO(r, o, s)                                        \
+	do {                                                               \
+		uint32_t offset, size;                                     \
 		TEST_ASSERT(host_command_region_info(r, &offset, &size) == \
-			    EC_RES_SUCCESS); \
-		TEST_ASSERT(offset == (o)); \
-		TEST_ASSERT(size == (s)); \
+			    EC_RES_SUCCESS);                               \
+		TEST_ASSERT(offset == (o));                                \
+		TEST_ASSERT(size == (s));                                  \
 	} while (0)
 
 int host_command_read(int offset, int size, char *out)
@@ -195,9 +194,8 @@ int host_command_erase(int offset, int size)
 				      sizeof(params), NULL, 0);
 }
 
-int host_command_protect(uint32_t mask, uint32_t flags,
-			 uint32_t *flags_out, uint32_t *valid_out,
-			 uint32_t *writable_out)
+int host_command_protect(uint32_t mask, uint32_t flags, uint32_t *flags_out,
+			 uint32_t *valid_out, uint32_t *writable_out)
 {
 	struct ec_params_flash_protect params;
 	struct ec_response_flash_protect resp;
@@ -222,7 +220,7 @@ int host_command_protect(uint32_t mask, uint32_t flags,
 }
 
 int host_command_region_info(enum ec_flash_region reg, uint32_t *offset,
-				 uint32_t *size)
+			     uint32_t *size)
 {
 	struct ec_params_flash_region_info params;
 	struct ec_response_flash_region_info resp;
@@ -253,7 +251,7 @@ static int test_read(void)
 #endif
 
 	/* The first few bytes in the flash should always contain some code */
-	TEST_ASSERT(!flash_is_erased(0, sizeof(buf)));
+	TEST_ASSERT(!crec_flash_is_erased(0, sizeof(buf)));
 
 	TEST_ASSERT(host_command_read(0, sizeof(buf), buf) == EC_RES_SUCCESS);
 	TEST_ASSERT_ARRAY_EQ(buf, (char *)CONFIG_PROGRAM_MEMORY_BASE,
@@ -268,11 +266,11 @@ static int test_is_erased(void)
 
 #ifdef EMU_BUILD
 	memset(__host_flash, 0xff, 1024);
-	TEST_ASSERT(flash_is_erased(0, 1024));
+	TEST_ASSERT(crec_flash_is_erased(0, 1024));
 
 	for (i = 0; i < 1024; ++i) {
 		__host_flash[i] = 0xec;
-		TEST_ASSERT(!flash_is_erased(0, 1024));
+		TEST_ASSERT(!crec_flash_is_erased(0, 1024));
 		__host_flash[i] = 0xff;
 	}
 #else
@@ -350,29 +348,31 @@ static int test_flash_info(void)
 {
 	struct ec_response_flash_info_1 resp;
 
-	TEST_ASSERT(test_send_host_command(EC_CMD_FLASH_INFO, 1, NULL, 0,
-		    &resp, sizeof(resp)) == EC_RES_SUCCESS);
+	TEST_ASSERT(test_send_host_command(EC_CMD_FLASH_INFO, 1, NULL, 0, &resp,
+					   sizeof(resp)) == EC_RES_SUCCESS);
 
-	TEST_CHECK((resp.flash_size == CONFIG_FLASH_SIZE) &&
-		   (resp.write_block_size == CONFIG_FLASH_WRITE_SIZE) &&
-		   (resp.erase_block_size == CONFIG_FLASH_ERASE_SIZE) &&
-		   (resp.protect_block_size == CONFIG_FLASH_BANK_SIZE));
+	TEST_ASSERT(resp.flash_size == CONFIG_FLASH_SIZE_BYTES);
+	TEST_ASSERT(resp.write_block_size == CONFIG_FLASH_WRITE_SIZE);
+	TEST_ASSERT(resp.erase_block_size == CONFIG_FLASH_ERASE_SIZE);
+	TEST_ASSERT(resp.protect_block_size == CONFIG_FLASH_BANK_SIZE);
+	return EC_SUCCESS;
 }
 
 static int test_region_info(void)
 {
 	VERIFY_REGION_INFO(EC_FLASH_REGION_RO,
 			   CONFIG_EC_PROTECTED_STORAGE_OFF +
-			   CONFIG_RO_STORAGE_OFF, EC_FLASH_REGION_RO_SIZE);
+				   CONFIG_RO_STORAGE_OFF,
+			   EC_FLASH_REGION_RO_SIZE);
 	VERIFY_REGION_INFO(EC_FLASH_REGION_ACTIVE,
 			   CONFIG_EC_WRITABLE_STORAGE_OFF +
-			   CONFIG_RW_STORAGE_OFF,
+				   CONFIG_RW_STORAGE_OFF,
 			   CONFIG_EC_WRITABLE_STORAGE_SIZE);
-	VERIFY_REGION_INFO(EC_FLASH_REGION_WP_RO,
-			   CONFIG_WP_STORAGE_OFF, CONFIG_WP_STORAGE_SIZE);
+	VERIFY_REGION_INFO(EC_FLASH_REGION_WP_RO, CONFIG_WP_STORAGE_OFF,
+			   CONFIG_WP_STORAGE_SIZE);
 	VERIFY_REGION_INFO(EC_FLASH_REGION_UPDATE,
 			   CONFIG_EC_WRITABLE_STORAGE_OFF +
-			   CONFIG_RW_STORAGE_OFF,
+				   CONFIG_RW_STORAGE_OFF,
 			   CONFIG_EC_WRITABLE_STORAGE_SIZE);
 
 	return EC_SUCCESS;
@@ -400,10 +400,12 @@ static int test_write_protect(void)
 	ASSERT_WP_FLAGS(EC_FLASH_PROTECT_ALL_NOW | EC_FLASH_PROTECT_RO_AT_BOOT);
 
 	/* Check we cannot erase anything */
-	TEST_ASSERT(flash_physical_erase(CONFIG_RO_STORAGE_OFF,
-			CONFIG_FLASH_ERASE_SIZE) != EC_SUCCESS);
-	TEST_ASSERT(flash_physical_erase(CONFIG_RW_STORAGE_OFF,
-			CONFIG_FLASH_ERASE_SIZE) != EC_SUCCESS);
+	TEST_ASSERT(crec_flash_physical_erase(CONFIG_RO_STORAGE_OFF,
+					      CONFIG_FLASH_ERASE_SIZE) !=
+		    EC_SUCCESS);
+	TEST_ASSERT(crec_flash_physical_erase(CONFIG_RW_STORAGE_OFF,
+					      CONFIG_FLASH_ERASE_SIZE) !=
+		    EC_SUCCESS);
 
 	/* We should not even try to write/erase */
 	VERIFY_NO_ERASE(CONFIG_RO_STORAGE_OFF, CONFIG_FLASH_ERASE_SIZE);
@@ -418,8 +420,9 @@ static int test_boot_write_protect(void)
 {
 	/* Check write protect state persists through reboot */
 	ASSERT_WP_FLAGS(EC_FLASH_PROTECT_RO_NOW | EC_FLASH_PROTECT_RO_AT_BOOT);
-	TEST_ASSERT(flash_physical_erase(CONFIG_RO_STORAGE_OFF,
-			CONFIG_FLASH_ERASE_SIZE) != EC_SUCCESS);
+	TEST_ASSERT(crec_flash_physical_erase(CONFIG_RO_STORAGE_OFF,
+					      CONFIG_FLASH_ERASE_SIZE) !=
+		    EC_SUCCESS);
 
 	return EC_SUCCESS;
 }
@@ -500,7 +503,7 @@ int task_test(void *data)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	msleep(30); /* Wait for TASK_ID_TEST to initialize */
 	task_wake(TASK_ID_TEST);
diff --git a/test/flash.tasklist b/test/flash.tasklist
index dae84c1635..dbebe0dabb 100644
--- a/test/flash.tasklist
+++ b/test/flash.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/flash_physical.c b/test/flash_physical.c
index e5430f4bd0..6e8f9ef883 100644
--- a/test/flash_physical.c
+++ b/test/flash_physical.c
@@ -1,9 +1,9 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include "chip/stm32/flash-f.h"
+#include "chip/stm32/flash-regs.h"
 #include "flash.h"
 #include "panic.h"
 #include "test_util.h"
@@ -30,7 +30,6 @@ struct flash_info flash_info = {
 #error "Flash info not defined for this chip. Please add it."
 #endif
 
-
 test_static int test_lock_option_bytes(void)
 {
 	TEST_EQ(flash_option_bytes_locked(), true, "%d");
@@ -113,25 +112,20 @@ test_static int test_disable_flash_control_register(void)
 
 test_static int test_flash_config(void)
 {
-	TEST_EQ(PHYSICAL_BANKS, flash_info.num_flash_banks, "%d");
+	TEST_EQ(crec_flash_total_banks(), flash_info.num_flash_banks, "%d");
 	TEST_EQ(WP_BANK_OFFSET, flash_info.write_protect_bank_offset, "%d");
 	TEST_EQ(WP_BANK_COUNT, flash_info.write_protect_bank_count, "%d");
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	ccprintf("Running flash physical test\n");
 	RUN_TEST(test_flash_config);
-	/*
-	 * TODO(b/157692395): These should be implemented for the STM32H743 as
-	 * well.
-	 */
-#if defined(CHIP_VARIANT_STM32F412)
+
 	RUN_TEST(test_lock_option_bytes);
 	RUN_TEST(test_disable_option_bytes);
 	RUN_TEST(test_lock_flash_control_register);
 	RUN_TEST(test_disable_flash_control_register);
-#endif
 	test_print_result();
 }
diff --git a/test/flash_physical.tasklist b/test/flash_physical.tasklist
index 51734f058d..a1f1a94e2d 100644
--- a/test/flash_physical.tasklist
+++ b/test/flash_physical.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/flash_write_protect.c b/test/flash_write_protect.c
index 2b69484e93..138aab24ff 100644
--- a/test/flash_write_protect.c
+++ b/test/flash_write_protect.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,23 +9,18 @@
 #include "system.h"
 #include "task.h"
 #include "test_util.h"
+#include "write_protect.h"
 
 test_static int check_image_and_hardware_write_protect(void)
 {
-	int wp;
+	bool wp;
 
 	if (system_get_image_copy() != EC_IMAGE_RO) {
 		ccprintf("This test is only works when running RO\n");
 		return EC_ERROR_UNKNOWN;
 	}
 
-#ifdef CONFIG_WP_ALWAYS
-        wp = 1;
-#elif defined(CONFIG_WP_ACTIVE_HIGH)
-        wp = gpio_get_level(GPIO_WP);
-#else
-	wp = !gpio_get_level(GPIO_WP_L);
-#endif
+	wp = write_protect_is_asserted();
 
 	if (!wp) {
 		ccprintf("Hardware write protect (GPIO_WP) must be enabled\n");
@@ -42,8 +37,8 @@ test_static int test_flash_write_protect_enable(void)
 	TEST_EQ(check_image_and_hardware_write_protect(), EC_SUCCESS, "%d");
 
 	/* Equivalent of ectool --name=cros_fp flashprotect enable */
-	rv = flash_set_protect(EC_FLASH_PROTECT_RO_AT_BOOT,
-			       EC_FLASH_PROTECT_RO_AT_BOOT);
+	rv = crec_flash_set_protect(EC_FLASH_PROTECT_RO_AT_BOOT,
+				    EC_FLASH_PROTECT_RO_AT_BOOT);
 
 	return rv;
 }
@@ -55,7 +50,7 @@ test_static int test_flash_write_protect_disable(void)
 	TEST_EQ(check_image_and_hardware_write_protect(), EC_SUCCESS, "%d");
 
 	/* Equivalent of ectool --name=cros_fp flashprotect disable */
-	rv = flash_set_protect(EC_FLASH_PROTECT_RO_AT_BOOT, 0);
+	rv = crec_flash_set_protect(EC_FLASH_PROTECT_RO_AT_BOOT, 0);
 	TEST_NE(rv, EC_SUCCESS, "%d");
 
 	return EC_SUCCESS;
@@ -79,16 +74,54 @@ test_static void run_test_step2(void)
 
 	if (test_get_error_count())
 		test_reboot_to_next_step(TEST_STATE_FAILED);
+	else if (IS_ENABLED(CONFIG_EEPROM_CBI_WP))
+		test_reboot_to_next_step(TEST_STATE_STEP_3);
 	else
 		test_reboot_to_next_step(TEST_STATE_PASSED);
 }
 
+#ifdef CONFIG_EEPROM_CBI_WP
+test_static int test_cbi_wb_asserted_immediately(void)
+{
+	int rv;
+
+	TEST_EQ(check_image_and_hardware_write_protect(), EC_SUCCESS, "%d");
+
+	/* Ensure that EC_CBI_WP is not asserted. */
+	TEST_EQ(gpio_get_level(GPIO_EC_CBI_WP), 0, "%d");
+
+	/* Equivalent of ectool --name=cros_fp flashprotect disable */
+	rv = crec_flash_set_protect(EC_FLASH_PROTECT_RO_NOW, 0);
+	TEST_EQ(rv, EC_SUCCESS, "%d");
+
+	/* Now make sure EC_CBI_WP is asserted immediately. */
+	TEST_EQ(gpio_get_level(GPIO_EC_CBI_WP), 1, "%d");
+
+	return EC_SUCCESS;
+}
+
+test_static void run_test_step3(void)
+{
+	ccprintf("Step 3: Flash write protect test\n");
+	RUN_TEST(test_cbi_wb_asserted_immediately);
+
+	if (test_get_error_count())
+		test_reboot_to_next_step(TEST_STATE_FAILED);
+	else
+		test_reboot_to_next_step(TEST_STATE_PASSED);
+}
+#endif /* CONFIG_EEPROM_CBI_WP */
+
 void test_run_step(uint32_t state)
 {
 	if (state & TEST_STATE_MASK(TEST_STATE_STEP_1))
 		run_test_step1();
 	else if (state & TEST_STATE_MASK(TEST_STATE_STEP_2))
 		run_test_step2();
+#ifdef CONFIG_EEPROM_CBI_WP
+	else if (state & TEST_STATE_MASK(TEST_STATE_STEP_3))
+		run_test_step3();
+#endif /* CONFIG_EEPROM_CBI_WP */
 }
 
 int task_test(void *unused)
@@ -97,7 +130,7 @@ int task_test(void *unused)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	msleep(30); /* Wait for TASK_ID_TEST to initialize */
 	task_wake(TASK_ID_TEST);
diff --git a/test/flash_write_protect.tasklist b/test/flash_write_protect.tasklist
index 21619decc3..974106d6c2 100644
--- a/test/flash_write_protect.tasklist
+++ b/test/flash_write_protect.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/float.tasklist b/test/float.tasklist
index 9ad0114d8a..5216cd488c 100644
--- a/test/float.tasklist
+++ b/test/float.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/fp.c b/test/fp.c
index 1945c09189..135670f47a 100644
--- a/test/fp.c
+++ b/test/fp.c
@@ -1,16 +1,16 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /*
  * Explicitly include common.h to populate predefined macros in test_config.h
- * early. e.g. CONFIG_FPU, which is needed in math_util.h
+ * early. e.g. CONFIG_FPU, which is needed in math_util.h.
  */
 #include "common.h"
-
 #include "mat33.h"
 #include "mat44.h"
+#include "math.h"
 #include "math_util.h"
 #include "test_util.h"
 #include "vec3.h"
@@ -24,20 +24,20 @@
 #define LUP_TOLERANCE FLOAT_TO_FP(0.0005f)
 #define SOLVE_TOLERANCE FLOAT_TO_FP(0.0005f)
 #elif defined(TEST_FLOAT) && defined(CONFIG_FPU)
-#define NORM_TOLERANCE FLOAT_TO_FP(0.0f)
+#define NORM_TOLERANCE FLOAT_TO_FP(0.00001f)
 #define NORM_SQUARED_TOLERANCE FLOAT_TO_FP(0.0f)
 #define DOT_TOLERANCE FLOAT_TO_FP(0.0f)
 #define SCALAR_MUL_TOLERANCE FLOAT_TO_FP(0.005f)
 #define EIGENBASIS_TOLERANCE FLOAT_TO_FP(0.02f)
-#define LUP_TOLERANCE FLOAT_TO_FP(0.0f)
-#define SOLVE_TOLERANCE FLOAT_TO_FP(0.0f)
+#define LUP_TOLERANCE FLOAT_TO_FP(0.00001f)
+#define SOLVE_TOLERANCE FLOAT_TO_FP(0.00001f)
 #else
 #error "No such test configuration."
 #endif
 
-#define IS_FPV3_VECTOR_EQUAL(a, b, diff)                                       \
-	(IS_FP_EQUAL((a)[0], (b)[0], (diff)) &&                                \
-	 IS_FP_EQUAL((a)[1], (b)[1], (diff)) &&                                \
+#define IS_FPV3_VECTOR_EQUAL(a, b, diff)        \
+	(IS_FP_EQUAL((a)[0], (b)[0], (diff)) && \
+	 IS_FP_EQUAL((a)[1], (b)[1], (diff)) && \
 	 IS_FP_EQUAL((a)[2], (b)[2], (diff)))
 #define IS_FP_EQUAL(a, b, diff) ((a) >= ((b)-diff) && (a) <= ((b) + diff))
 #define IS_FLOAT_EQUAL(a, b, diff) IS_FP_EQUAL(a, b, diff)
@@ -46,9 +46,9 @@ static int test_fpv3_scalar_mul(void)
 {
 	const int N = 3;
 	const float s = 2.0f;
-	floatv3_t r = {1.0f, 2.0f, 4.0f};
+	floatv3_t r = { 1.0f, 2.0f, 4.0f };
 	/* Golden result g = s * r; */
-	const floatv3_t g = {2.0f, 4.0f, 8.0f};
+	const floatv3_t g = { 2.0f, 4.0f, 8.0f };
 	int i;
 	fpv3_t a;
 
@@ -67,19 +67,20 @@ static int test_fpv3_dot(void)
 {
 	const int N = 3;
 	int i;
-	floatv3_t a = {1.8f, 2.12f, 4.12f};
-	floatv3_t b = {3.1f, 4.3f, 5.8f};
-	/* Golden result g = dot(a, b) */
+	floatv3_t a = { 1.8f, 2.12f, 4.12f };
+	floatv3_t b = { 3.1f, 4.3f, 5.8f };
+	/* Golden result g = dot(a, b). */
 	float g = 38.592f;
 	fpv3_t fpa, fpb;
+	volatile fp_t result;
 
 	for (i = 0; i < N; ++i) {
 		fpa[i] = FLOAT_TO_FP(a[i]);
 		fpb[i] = FLOAT_TO_FP(b[i]);
 	}
 
-	TEST_ASSERT(IS_FP_EQUAL(fpv3_dot(fpa, fpb), FLOAT_TO_FP(g),
-				DOT_TOLERANCE));
+	result = fpv3_dot(fpa, fpb);
+	TEST_ASSERT(IS_FP_EQUAL(result, FLOAT_TO_FP(g), DOT_TOLERANCE));
 
 	return EC_SUCCESS;
 }
@@ -88,8 +89,8 @@ static int test_fpv3_norm_squared(void)
 {
 	const int N = 3;
 	int i;
-	floatv3_t a = {3.0f, 4.0f, 5.0f};
-	/* Golden result g = norm_squared(a) */
+	floatv3_t a = { 3.0f, 4.0f, 5.0f };
+	/* Golden result g = norm_squared(a). */
 	float g = 50.0f;
 	fpv3_t fpa;
 
@@ -105,17 +106,35 @@ static int test_fpv3_norm_squared(void)
 static int test_fpv3_norm(void)
 {
 	const int N = 3;
-	floatv3_t a = {3.1f, 4.2f, 5.3f};
-	/* Golden result g = norm(a) */
-	float g = 7.439085483551025390625f;
+	floatv3_t a = { 3.1f, 4.2f, 5.3f };
+	/* Golden result g = norm(a). */
+	float g = 7.439086f;
 	int i;
 	fpv3_t fpa;
+	volatile fp_t result;
 
 	for (i = 0; i < N; ++i)
 		fpa[i] = FLOAT_TO_FP(a[i]);
 
-	TEST_ASSERT(
-		IS_FP_EQUAL(fpv3_norm(fpa), FLOAT_TO_FP(g), NORM_TOLERANCE));
+	result = fpv3_norm(fpa);
+	TEST_ASSERT(IS_FP_EQUAL(result, FLOAT_TO_FP(g), NORM_TOLERANCE));
+	return EC_SUCCESS;
+}
+
+static int test_int_sqrtf(void)
+{
+#ifndef CONFIG_FPU
+	TEST_ASSERT(int_sqrtf(0) == 0);
+	TEST_ASSERT(int_sqrtf(15) == 3);
+	TEST_ASSERT(int_sqrtf(25) == 5);
+	TEST_ASSERT(int_sqrtf(1111088889) == 33333);
+	TEST_ASSERT(int_sqrtf(123456789) == 11111);
+	TEST_ASSERT(int_sqrtf(1000000000000000005) == 1000000000);
+	/* Return zero for imaginary numbers. */
+	TEST_ASSERT(int_sqrtf(-100) == 0);
+	/* Return INT32_MAX for input greater than INT32_MAX ^ 2. */
+	TEST_ASSERT(int_sqrtf(INT64_MAX) == INT32_MAX);
+#endif
 
 	return EC_SUCCESS;
 }
@@ -167,17 +186,14 @@ static int test_mat33_fp_scalar_mul(void)
 {
 	const int N = 3;
 	float scale = 3.11f;
-	mat33_float_t a = {
-		{1.0f, 2.0f, 3.0f},
-		{1.1f, 2.2f, 3.3f},
-		{0.38f, 13.2f, 88.3f}
-	};
-	/* Golden result g = scalar_mul(a, scale) */
-	mat33_float_t g = {{3.11f, 6.22f, 9.33f},
-			   {3.421f, 6.842f, 10.263f},
-			   {1.18179988861083984375f, 41.051998138427734375f,
-			    274.613006591796875f}
-	};
+	mat33_float_t a = { { 1.0f, 2.0f, 3.0f },
+			    { 1.1f, 2.2f, 3.3f },
+			    { 0.38f, 13.2f, 88.3f } };
+	/* Golden result g = scalar_mul(a, scale). */
+	mat33_float_t g = { { 3.11f, 6.22f, 9.33f },
+			    { 3.421f, 6.842f, 10.263f },
+			    { 1.18179988861083984375f, 41.051998138427734375f,
+			      274.613006591796875f } };
 	int i, j;
 	mat33_fp_t fpa;
 
@@ -198,9 +214,9 @@ static int test_mat33_fp_scalar_mul(void)
 static int test_mat33_fp_get_eigenbasis(void)
 {
 	mat33_fp_t s = {
-		{FLOAT_TO_FP(4.0f), FLOAT_TO_FP(2.0f), FLOAT_TO_FP(2.0f)},
-		{FLOAT_TO_FP(2.0f), FLOAT_TO_FP(4.0f), FLOAT_TO_FP(2.0f)},
-		{FLOAT_TO_FP(2.0f), FLOAT_TO_FP(2.0f), FLOAT_TO_FP(4.0f)}
+		{ FLOAT_TO_FP(4.0f), FLOAT_TO_FP(2.0f), FLOAT_TO_FP(2.0f) },
+		{ FLOAT_TO_FP(2.0f), FLOAT_TO_FP(4.0f), FLOAT_TO_FP(2.0f) },
+		{ FLOAT_TO_FP(2.0f), FLOAT_TO_FP(2.0f), FLOAT_TO_FP(4.0f) }
 	};
 	fpv3_t e_vals;
 	mat33_fp_t e_vecs;
@@ -208,15 +224,15 @@ static int test_mat33_fp_get_eigenbasis(void)
 
 	/* Golden result from float version. */
 	mat33_fp_t gold_vecs = {
-		{FLOAT_TO_FP(0.55735206f), FLOAT_TO_FP(0.55735206f),
-		 FLOAT_TO_FP(0.55735206f)},
-		{FLOAT_TO_FP(0.70710677f), FLOAT_TO_FP(-0.70710677f),
-		 FLOAT_TO_FP(0.0f)},
-		{FLOAT_TO_FP(-0.40824828f), FLOAT_TO_FP(-0.40824828f),
-		 FLOAT_TO_FP(0.81649655f)}
+		{ FLOAT_TO_FP(0.55735206f), FLOAT_TO_FP(0.55735206f),
+		  FLOAT_TO_FP(0.55735206f) },
+		{ FLOAT_TO_FP(0.70710677f), FLOAT_TO_FP(-0.70710677f),
+		  FLOAT_TO_FP(0.0f) },
+		{ FLOAT_TO_FP(-0.40824828f), FLOAT_TO_FP(-0.40824828f),
+		  FLOAT_TO_FP(0.81649655f) }
 	};
-	fpv3_t gold_vals = {FLOAT_TO_FP(8.0f), FLOAT_TO_FP(2.0f),
-			    FLOAT_TO_FP(2.0f)};
+	fpv3_t gold_vals = { FLOAT_TO_FP(8.0f), FLOAT_TO_FP(2.0f),
+			     FLOAT_TO_FP(2.0f) };
 
 	mat33_fp_get_eigenbasis(s, e_vals, e_vecs);
 
@@ -236,28 +252,26 @@ static int test_mat44_fp_decompose_lup(void)
 {
 	int i, j;
 	sizev4_t pivot;
-	mat44_fp_t fpa = {
-		{FLOAT_TO_FP(11.0f), FLOAT_TO_FP(9.0f),
-		 FLOAT_TO_FP(24.0f), FLOAT_TO_FP(2.0f)},
-		{FLOAT_TO_FP(1.0f), FLOAT_TO_FP(5.0f),
-		 FLOAT_TO_FP(2.0f), FLOAT_TO_FP(6.0f)},
-		{FLOAT_TO_FP(3.0f), FLOAT_TO_FP(17.0f),
-		 FLOAT_TO_FP(18.0f), FLOAT_TO_FP(1.0f)},
-		{FLOAT_TO_FP(2.0f), FLOAT_TO_FP(5.0f),
-		 FLOAT_TO_FP(7.0f), FLOAT_TO_FP(1.0f)}
-	};
+	mat44_fp_t fpa = { { FLOAT_TO_FP(11.0f), FLOAT_TO_FP(9.0f),
+			     FLOAT_TO_FP(24.0f), FLOAT_TO_FP(2.0f) },
+			   { FLOAT_TO_FP(1.0f), FLOAT_TO_FP(5.0f),
+			     FLOAT_TO_FP(2.0f), FLOAT_TO_FP(6.0f) },
+			   { FLOAT_TO_FP(3.0f), FLOAT_TO_FP(17.0f),
+			     FLOAT_TO_FP(18.0f), FLOAT_TO_FP(1.0f) },
+			   { FLOAT_TO_FP(2.0f), FLOAT_TO_FP(5.0f),
+			     FLOAT_TO_FP(7.0f), FLOAT_TO_FP(1.0f) } };
 	/* Golden result from float version. */
 	mat44_fp_t gold_lu = {
-		{FLOAT_TO_FP(11.0f), FLOAT_TO_FP(0.8181818f),
-		 FLOAT_TO_FP(2.1818182f), FLOAT_TO_FP(0.18181819f)},
-		{FLOAT_TO_FP(3.0f), FLOAT_TO_FP(14.545454),
-		 FLOAT_TO_FP(0.7875f), FLOAT_TO_FP(0.03125f)},
-		{FLOAT_TO_FP(1.0f), FLOAT_TO_FP(4.181818f),
-		 FLOAT_TO_FP(-3.4750001f), FLOAT_TO_FP(-1.6366906f)},
-		{FLOAT_TO_FP(2.0f), FLOAT_TO_FP(3.3636365f),
-		 FLOAT_TO_FP(-0.012500286f), FLOAT_TO_FP(0.5107909f)}
+		{ FLOAT_TO_FP(11.0f), FLOAT_TO_FP(0.8181818f),
+		  FLOAT_TO_FP(2.1818182f), FLOAT_TO_FP(0.18181819f) },
+		{ FLOAT_TO_FP(3.0f), FLOAT_TO_FP(14.545455f),
+		  FLOAT_TO_FP(0.78749999f), FLOAT_TO_FP(0.031249999f) },
+		{ FLOAT_TO_FP(1.0f), FLOAT_TO_FP(4.181818f),
+		  FLOAT_TO_FP(-3.4749996f), FLOAT_TO_FP(-1.6366909f) },
+		{ FLOAT_TO_FP(2.0f), FLOAT_TO_FP(3.3636365f),
+		  FLOAT_TO_FP(-0.012500112f), FLOAT_TO_FP(0.5107912f) }
 	};
-	sizev4_t gold_pivot = {0, 2, 2, 3};
+	sizev4_t gold_pivot = { 0, 2, 2, 3 };
 
 	mat44_fp_decompose_lup(fpa, pivot);
 
@@ -275,22 +289,21 @@ static int test_mat44_fp_solve(void)
 {
 	int i;
 	fpv4_t x;
-	mat44_fp_t A = {
-		{FLOAT_TO_FP(11.0f), FLOAT_TO_FP(0.8181818f),
-		 FLOAT_TO_FP(2.1818182f), FLOAT_TO_FP(0.18181819f)},
-		{FLOAT_TO_FP(3.0f), FLOAT_TO_FP(14.545454),
-		 FLOAT_TO_FP(0.7875f), FLOAT_TO_FP(0.03125f)},
-		{FLOAT_TO_FP(1.0f), FLOAT_TO_FP(4.181818f),
-		 FLOAT_TO_FP(-3.4750001f), FLOAT_TO_FP(-1.6366906f)},
-		{FLOAT_TO_FP(2.0f), FLOAT_TO_FP(3.3636365f),
-		 FLOAT_TO_FP(-0.012500286f), FLOAT_TO_FP(0.5107909f)}
-	};
-	sizev4_t pivot = {0, 2, 2, 3};
-	fpv4_t b = {FLOAT_TO_FP(1.0f), FLOAT_TO_FP(3.3f), FLOAT_TO_FP(0.8f),
-		    FLOAT_TO_FP(8.9f)};
+	mat44_fp_t A = { { FLOAT_TO_FP(11.0f), FLOAT_TO_FP(0.8181818f),
+			   FLOAT_TO_FP(2.1818182f), FLOAT_TO_FP(0.18181819f) },
+			 { FLOAT_TO_FP(3.0f), FLOAT_TO_FP(14.545454),
+			   FLOAT_TO_FP(0.7875f), FLOAT_TO_FP(0.03125f) },
+			 { FLOAT_TO_FP(1.0f), FLOAT_TO_FP(4.181818f),
+			   FLOAT_TO_FP(-3.4750001f), FLOAT_TO_FP(-1.6366906f) },
+			 { FLOAT_TO_FP(2.0f), FLOAT_TO_FP(3.3636365f),
+			   FLOAT_TO_FP(-0.012500286f),
+			   FLOAT_TO_FP(0.5107909f) } };
+	sizev4_t pivot = { 0, 2, 2, 3 };
+	fpv4_t b = { FLOAT_TO_FP(1.0f), FLOAT_TO_FP(3.3f), FLOAT_TO_FP(0.8f),
+		     FLOAT_TO_FP(8.9f) };
 	/* Golden result from float version. */
-	fpv4_t gold_x = {FLOAT_TO_FP(-43.50743f), FLOAT_TO_FP(-21.459526f),
-			 FLOAT_TO_FP(26.629248f), FLOAT_TO_FP(16.80776f)};
+	fpv4_t gold_x = { FLOAT_TO_FP(-43.507435f), FLOAT_TO_FP(-21.459525f),
+			  FLOAT_TO_FP(26.629248f), FLOAT_TO_FP(16.80776f) };
 
 	mat44_fp_solve(A, x, b, pivot);
 
@@ -300,7 +313,61 @@ static int test_mat44_fp_solve(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+test_static int test_isnan(void)
+{
+	float zero = 0.0f;
+	float smallest = 1.40130e-45f;
+	float highest = 3.40282e38f;
+
+	/* 0.0/0.0 results in NaN. */
+	TEST_ASSERT(isnan(zero / zero));
+	TEST_ASSERT(isnan(-zero / zero));
+	TEST_ASSERT(isnan(zero / -zero));
+	TEST_ASSERT(isnan(-zero / -zero));
+
+	/*
+	 * Make sure the smallest number (which is also denormalized) won't be
+	 * recognized as NaN.
+	 */
+	TEST_ASSERT(!isnan(smallest));
+
+	/* Make sure highest number won't be recognized as NaN. */
+	TEST_ASSERT(!isnan(highest));
+
+	/* Make sure that 0.0 is not recognized as NaN. */
+	TEST_ASSERT(!isnan(zero));
+	TEST_ASSERT(!isnan(-zero));
+
+	return EC_SUCCESS;
+}
+
+test_static int test_isinf(void)
+{
+	float one = 1.0f;
+	float zero = 0.0f;
+	float smallest = 1.40130e-45f;
+	float highest = 3.40282e38f;
+
+	TEST_ASSERT(isinf(one / zero));
+	TEST_ASSERT(isinf(-one / zero));
+
+	/*
+	 * Make sure the smallest number (which is also denormalized) won't be
+	 * recognized as infinity.
+	 */
+	TEST_ASSERT(!isinf(smallest));
+
+	/* Make sure highest number won't be recognized as infinity. */
+	TEST_ASSERT(!isinf(highest));
+
+	/* Make sure that 0.0 is not recognized as infinity. */
+	TEST_ASSERT(!isinf(zero));
+	TEST_ASSERT(!isinf(-zero));
+
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
@@ -308,12 +375,15 @@ void run_test(int argc, char **argv)
 	RUN_TEST(test_fpv3_dot);
 	RUN_TEST(test_fpv3_norm_squared);
 	RUN_TEST(test_fpv3_norm);
+	RUN_TEST(test_int_sqrtf);
 	RUN_TEST(test_mat33_fp_init_zero);
 	RUN_TEST(test_mat33_fp_init_diagonal);
 	RUN_TEST(test_mat33_fp_scalar_mul);
 	RUN_TEST(test_mat33_fp_get_eigenbasis);
 	RUN_TEST(test_mat44_fp_decompose_lup);
 	RUN_TEST(test_mat44_fp_solve);
+	RUN_TEST(test_isnan);
+	RUN_TEST(test_isinf);
 
 	test_print_result();
 }
diff --git a/test/fp.tasklist b/test/fp.tasklist
index 9ad0114d8a..5216cd488c 100644
--- a/test/fp.tasklist
+++ b/test/fp.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/fpsensor.c b/test/fpsensor.c
index ff5a9a6c51..a1947f7844 100644
--- a/test/fpsensor.c
+++ b/test/fpsensor.c
@@ -1,10 +1,31 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "ec_commands.h"
+#include "fpsensor_utils.h"
+#include "mock/fpsensor_detect_mock.h"
+#include "string.h"
 #include "test_util.h"
-#include "common/fpsensor/fpsensor_private.h"
+
+#include <stdbool.h>
+#include <stddef.h>
+
+static const struct ec_response_get_protocol_info expected_info[] = {
+	[FP_TRANSPORT_TYPE_SPI] = {
+		.flags = 1,
+		.max_response_packet_size = 544,
+		.max_request_packet_size = 544,
+		.protocol_versions = 8,
+	},
+	[FP_TRANSPORT_TYPE_UART] = {
+		.flags = 1,
+		.max_response_packet_size = 256,
+		.max_request_packet_size = 544,
+		.protocol_versions = 8,
+	}
+};
 
 test_static int test_validate_fp_buffer_offset_success(void)
 {
@@ -25,10 +46,75 @@ test_static int test_validate_fp_buffer_offset_failure_overflow(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+test_static int test_host_command_protocol_info(
+	enum fp_transport_type transport_type,
+	const struct ec_response_get_protocol_info *expected)
+{
+	struct ec_response_get_protocol_info info;
+	int rv;
+
+	mock_ctrl_fpsensor_detect.fpsensor_detect_get_type_return =
+		FP_SENSOR_TYPE_FPC;
+	mock_ctrl_fpsensor_detect.get_fp_transport_type_return = transport_type;
+
+	rv = test_send_host_command(EC_CMD_GET_PROTOCOL_INFO, 0, NULL, 0, &info,
+				    sizeof(info));
+
+	TEST_EQ(rv, EC_RES_SUCCESS, "%d");
+
+	TEST_EQ(info.flags, expected->flags, "%d");
+	TEST_EQ(info.max_request_packet_size, expected->max_request_packet_size,
+		"%d");
+	TEST_EQ(info.max_response_packet_size,
+		expected->max_response_packet_size, "%d");
+	TEST_EQ(info.protocol_versions, expected->protocol_versions, "%d");
+
+	return EC_SUCCESS;
+}
+
+test_static int test_host_command_protocol_info_uart(void)
+{
+	return test_host_command_protocol_info(
+		FP_TRANSPORT_TYPE_UART, &expected_info[FP_TRANSPORT_TYPE_UART]);
+}
+
+test_static int test_host_command_protocol_info_spi(void)
 {
-	test_validate_fp_buffer_offset_success();
-	test_validate_fp_buffer_offset_failure_no_overflow();
-	test_validate_fp_buffer_offset_failure_overflow();
+	return test_host_command_protocol_info(
+		FP_TRANSPORT_TYPE_SPI, &expected_info[FP_TRANSPORT_TYPE_SPI]);
+}
+
+void run_test(int argc, const char **argv)
+{
+	if (IS_ENABLED(HAS_TASK_FPSENSOR)) {
+		/* TODO(b/171924356): The "emulator" build only builds RO and
+		 *  the functions used in the tests are only in RW, so these
+		 *  tests are not run on the emulator.
+		 */
+		RUN_TEST(test_validate_fp_buffer_offset_success);
+		RUN_TEST(test_validate_fp_buffer_offset_failure_no_overflow);
+		RUN_TEST(test_validate_fp_buffer_offset_failure_overflow);
+	}
+
+	/* The tests after this only work on device right now. */
+	if (IS_ENABLED(EMU_BUILD)) {
+		test_print_result();
+		return;
+	}
+
+	if (argc < 2) {
+		ccprintf("usage: runtest [uart|spi]\n");
+		test_fail();
+		return;
+	}
+
+	/* The transport type is cached in a static variable, so the tests
+	 * cannot be run back to back (without reboot).
+	 */
+	if (strncmp(argv[1], "uart", 4) == 0 && IS_ENABLED(BOARD_BLOONCHIPPER))
+		RUN_TEST(test_host_command_protocol_info_uart);
+	else if (strncmp(argv[1], "spi", 3) == 0)
+		RUN_TEST(test_host_command_protocol_info_spi);
+
 	test_print_result();
 }
diff --git a/test/fpsensor.mocklist b/test/fpsensor.mocklist
index 990dd92c45..84972487c9 100644
--- a/test/fpsensor.mocklist
+++ b/test/fpsensor.mocklist
@@ -1,12 +1,21 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
- #define CONFIG_TEST_MOCK_LIST \
-        MOCK(FP_SENSOR)        \
-        MOCK(FPSENSOR_DETECT)  \
-	MOCK(FPSENSOR_STATE)   \
-        MOCK(MKBP_EVENTS)      \
-        MOCK(ROLLBACK)         \
+#ifdef BOARD_HOST
+#define CONFIG_TEST_MOCK_LIST \
+	MOCK(FPSENSOR)       \
+	MOCK(FPSENSOR_CRYPTO) \
+	MOCK(FPSENSOR_DETECT) \
+	MOCK(FPSENSOR_STATE)  \
+	MOCK(MKBP_EVENTS)     \
+	MOCK(ROLLBACK)        \
 	MOCK(TIMER)
+#elif defined(TEST_BUILD)
+/* Mock the sensor detection on dragonclaw v0.2 dev boards since we can't
+ * otherwise change the detected version in hardware without a rework. See
+ * https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/docs/schematics/dragonclaw
+ */
+#define CONFIG_TEST_MOCK_LIST MOCK(FPSENSOR_DETECT)
+#endif /* BOARD_HOST */
diff --git a/test/fpsensor.tasklist b/test/fpsensor.tasklist
index bee999ff6b..6c3ec6d65e 100644
--- a/test/fpsensor.tasklist
+++ b/test/fpsensor.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,6 +6,10 @@
 /**
  * See CONFIG_TASK_LIST in config.h for details.
  */
-#define CONFIG_TEST_TASK_LIST \
-        TASK_TEST(FPSENSOR, fp_task_simulate, NULL, TASK_STACK_SIZE)
+#define CONFIG_TEST_TASK_LIST
 
+#ifdef BOARD_HOST
+#undef CONFIG_TEST_TASK_LIST
+#define CONFIG_TEST_TASK_LIST \
+	TASK_TEST(FPSENSOR, fp_task_simulate, NULL, TASK_STACK_SIZE)
+#endif
diff --git a/test/fpsensor_auth_commands.cc b/test/fpsensor_auth_commands.cc
new file mode 100644
index 0000000000..f57d011715
--- /dev/null
+++ b/test/fpsensor_auth_commands.cc
@@ -0,0 +1,247 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "ec_commands.h"
+#include "fpsensor_auth_commands.h"
+#include "fpsensor_auth_crypto.h"
+#include "fpsensor_state.h"
+#include "mock/fpsensor_state_mock.h"
+#include "openssl/bn.h"
+#include "openssl/ec.h"
+#include "openssl/obj_mac.h"
+#include "test_util.h"
+#include "util.h"
+
+#include <stdbool.h>
+
+#include <array>
+
+namespace
+{
+
+enum ec_error_list
+check_seed_set_result(const enum ec_status rv, const uint32_t expected,
+		      const struct ec_response_fp_encryption_status *resp)
+{
+	const uint32_t actual = resp->status & FP_ENC_STATUS_SEED_SET;
+
+	if (rv != EC_RES_SUCCESS || expected != actual) {
+		ccprintf("%s:%s(): rv = %d, seed is set: %d\n", __FILE__,
+			 __func__, rv, actual);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+test_static enum ec_error_list test_set_fp_tpm_seed(void)
+{
+	enum ec_status rv;
+	struct ec_params_fp_seed params;
+	struct ec_response_fp_encryption_status resp = { 0 };
+
+	params.struct_version = FP_TEMPLATE_FORMAT_VERSION;
+	memcpy(params.seed, default_fake_tpm_seed,
+	       sizeof(default_fake_tpm_seed));
+
+	rv = test_send_host_command(EC_CMD_FP_SEED, 0, &params, sizeof(params),
+				    NULL, 0);
+	if (rv != EC_RES_SUCCESS) {
+		ccprintf("%s:%s(): rv = %d, set seed failed\n", __FILE__,
+			 __func__, rv);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	/* Now seed should have been set. */
+	rv = test_send_host_command(EC_CMD_FP_ENC_STATUS, 0, NULL, 0, &resp,
+				    sizeof(resp));
+
+	return check_seed_set_result(rv, FP_ENC_STATUS_SEED_SET, &resp);
+}
+
+test_static enum ec_error_list test_fp_command_check_context_cleared(void)
+{
+	fp_reset_and_clear_context();
+	TEST_EQ(check_context_cleared(), EC_SUCCESS, "%d");
+
+	struct ec_params_fp_context_v1 params = {
+		.action = FP_CONTEXT_GET_RESULT,
+		.userid = { 0, 1, 2, 3, 4, 5, 6, 7 },
+	};
+	TEST_EQ(test_send_host_command(EC_CMD_FP_CONTEXT, 1, &params,
+				       sizeof(params), NULL, 0),
+		EC_RES_SUCCESS, "%d");
+	TEST_EQ(check_context_cleared(), EC_ERROR_ACCESS_DENIED, "%d");
+
+	fp_reset_and_clear_context();
+	TEST_EQ(check_context_cleared(), EC_SUCCESS, "%d");
+
+	templ_valid++;
+	TEST_EQ(check_context_cleared(), EC_ERROR_ACCESS_DENIED, "%d");
+
+	fp_reset_and_clear_context();
+	TEST_EQ(check_context_cleared(), EC_SUCCESS, "%d");
+
+	templ_dirty |= BIT(0);
+	TEST_EQ(check_context_cleared(), EC_ERROR_ACCESS_DENIED, "%d");
+
+	fp_reset_and_clear_context();
+	TEST_EQ(check_context_cleared(), EC_SUCCESS, "%d");
+
+	positive_match_secret_state.template_matched = 0;
+	TEST_EQ(check_context_cleared(), EC_ERROR_ACCESS_DENIED, "%d");
+
+	return EC_SUCCESS;
+}
+
+test_static enum ec_error_list
+test_fp_command_establish_pairing_key_without_seed(void)
+{
+	enum ec_status rv;
+	struct ec_response_fp_encryption_status resp = { 0 };
+	struct ec_response_fp_establish_pairing_key_keygen keygen_response;
+
+	/* Seed shouldn't have been set. */
+	rv = test_send_host_command(EC_CMD_FP_ENC_STATUS, 0, NULL, 0, &resp,
+				    sizeof(resp));
+
+	TEST_EQ(check_seed_set_result(rv, 0, &resp), EC_SUCCESS, "%d");
+
+	rv = test_send_host_command(EC_CMD_FP_ESTABLISH_PAIRING_KEY_KEYGEN, 0,
+				    NULL, 0, &keygen_response,
+				    sizeof(keygen_response));
+
+	TEST_NE(rv, EC_RES_SUCCESS, "%d");
+
+	return EC_SUCCESS;
+}
+
+test_static enum ec_error_list
+test_fp_command_establish_pairing_key_keygen(void)
+{
+	enum ec_status rv;
+	struct ec_response_fp_establish_pairing_key_keygen keygen_response;
+
+	rv = test_send_host_command(EC_CMD_FP_ESTABLISH_PAIRING_KEY_KEYGEN, 0,
+				    NULL, 0, &keygen_response,
+				    sizeof(keygen_response));
+
+	TEST_EQ(rv, EC_RES_SUCCESS, "%d");
+
+	bssl::UniquePtr<EC_KEY> pubkey =
+		create_ec_key_from_pubkey(keygen_response.pubkey);
+
+	TEST_NE(pubkey.get(), nullptr, "%p");
+	TEST_EQ(EC_KEY_check_key(pubkey.get()), 1, "%d");
+
+	return EC_SUCCESS;
+}
+
+test_static enum ec_error_list test_fp_command_establish_pairing_key(void)
+{
+	enum ec_status rv;
+	struct ec_response_fp_establish_pairing_key_keygen keygen_response;
+	struct ec_params_fp_establish_pairing_key_wrap wrap_params {
+		.peers_pubkey = {
+			.x = {
+				0x85, 0xAD, 0x35, 0x23, 0x05, 0x1E, 0x33, 0x3F,
+				0xCA, 0xA7, 0xEA, 0xA5, 0x88, 0x33, 0x12, 0x95,
+				0xA7, 0xB5, 0x98, 0x9F, 0x32, 0xEF, 0x7D, 0xE9,
+				0xF8, 0x70, 0x14, 0x5E, 0x89, 0xCB, 0xDE, 0x1F,
+			},
+			.y = {
+				0xD1, 0xDC, 0x91, 0xC6, 0xE6, 0x5B, 0x1E, 0x3C,
+				0x01, 0x6C, 0xE6, 0x50, 0x25, 0x5D, 0x89, 0xCF,
+				0xB7, 0x8D, 0x88, 0xB9, 0x0D, 0x09, 0x41, 0xF1,
+				0x09, 0x4F, 0x61, 0x55, 0x6C, 0xC4, 0x96, 0x6B,
+			},
+		},
+	};
+	struct ec_response_fp_establish_pairing_key_wrap wrap_response;
+
+	rv = test_send_host_command(EC_CMD_FP_ESTABLISH_PAIRING_KEY_KEYGEN, 0,
+				    NULL, 0, &keygen_response,
+				    sizeof(keygen_response));
+
+	TEST_EQ(rv, EC_RES_SUCCESS, "%d");
+
+	memcpy(&wrap_params.encrypted_private_key.info,
+	       &keygen_response.encrypted_private_key.info,
+	       sizeof(keygen_response.encrypted_private_key.info));
+
+	memcpy(wrap_params.encrypted_private_key.data,
+	       keygen_response.encrypted_private_key.data,
+	       sizeof(keygen_response.encrypted_private_key.data));
+
+	rv = test_send_host_command(EC_CMD_FP_ESTABLISH_PAIRING_KEY_WRAP, 0,
+				    &wrap_params, sizeof(wrap_params),
+				    &wrap_response, sizeof(wrap_response));
+
+	TEST_EQ(rv, EC_RES_SUCCESS, "%d");
+
+	return EC_SUCCESS;
+}
+
+test_static enum ec_error_list test_fp_command_establish_pairing_key_fail(void)
+{
+	enum ec_status rv;
+	struct ec_response_fp_establish_pairing_key_keygen keygen_response;
+	struct ec_params_fp_establish_pairing_key_wrap wrap_params {
+		.peers_pubkey = {
+			.x = {
+				0x85, 0xAD, 0x35, 0x23, 0x05, 0x1E, 0x33, 0x3F,
+				0xCA, 0xA7, 0xEA, 0xA5, 0x88, 0x33, 0x12, 0x95,
+				0xA7, 0xB5, 0x98, 0x9F, 0x32, 0xEF, 0x7D, 0xE9,
+				0xF8, 0x70, 0x14, 0x5E, 0x89, 0xCB, 0xDE, 0x1F,
+			},
+			.y = {
+				0xD1, 0xDC, 0x91, 0xC6, 0xE6, 0x5B, 0x1E, 0x3C,
+				0x01, 0x6C, 0xE6, 0x50, 0x25, 0x5D, 0x89, 0xCF,
+				0xB7, 0x8D, 0x88, 0xB9, 0x0D, 0x09, 0x41, 0xF1,
+				0x09, 0x4F, 0x61, 0x55, 0x6C, 0xC4, 0x96, 0x6B,
+			},
+		},
+	};
+	struct ec_response_fp_establish_pairing_key_wrap wrap_response;
+
+	rv = test_send_host_command(EC_CMD_FP_ESTABLISH_PAIRING_KEY_KEYGEN, 0,
+				    NULL, 0, &keygen_response,
+				    sizeof(keygen_response));
+
+	TEST_EQ(rv, EC_RES_SUCCESS, "%d");
+
+	/* No encryption info. */
+	memset(&wrap_params.encrypted_private_key.info, 0,
+	       sizeof(wrap_params.encrypted_private_key.info));
+
+	memcpy(wrap_params.encrypted_private_key.data,
+	       keygen_response.encrypted_private_key.data,
+	       sizeof(keygen_response.encrypted_private_key.data));
+
+	rv = test_send_host_command(EC_CMD_FP_ESTABLISH_PAIRING_KEY_WRAP, 0,
+				    &wrap_params, sizeof(wrap_params),
+				    &wrap_response, sizeof(wrap_response));
+
+	TEST_NE(rv, EC_RES_SUCCESS, "%d");
+
+	return EC_SUCCESS;
+}
+
+} // namespace
+
+extern "C" void run_test(int argc, const char **argv)
+{
+	RUN_TEST(test_fp_command_establish_pairing_key_without_seed);
+	RUN_TEST(test_fp_command_check_context_cleared);
+
+	// All tests after this require the TPM seed to be set.
+	RUN_TEST(test_set_fp_tpm_seed);
+
+	RUN_TEST(test_fp_command_establish_pairing_key_keygen);
+	RUN_TEST(test_fp_command_establish_pairing_key);
+	RUN_TEST(test_fp_command_establish_pairing_key_fail);
+	test_print_result();
+}
diff --git a/test/fpsensor_auth_commands.mocklist b/test/fpsensor_auth_commands.mocklist
new file mode 120000
index 0000000000..3ab27169be
--- /dev/null
+++ b/test/fpsensor_auth_commands.mocklist
@@ -0,0 +1 @@
+fpsensor.mocklist
\ No newline at end of file
diff --git a/test/fpsensor_auth_commands.tasklist b/test/fpsensor_auth_commands.tasklist
new file mode 120000
index 0000000000..69b4562a97
--- /dev/null
+++ b/test/fpsensor_auth_commands.tasklist
@@ -0,0 +1 @@
+./fpsensor.tasklist
\ No newline at end of file
diff --git a/test/fpsensor_auth_crypto_stateful.cc b/test/fpsensor_auth_crypto_stateful.cc
new file mode 100644
index 0000000000..ad4eb87cbb
--- /dev/null
+++ b/test/fpsensor_auth_crypto_stateful.cc
@@ -0,0 +1,304 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "crypto/elliptic_curve_key.h"
+#include "ec_commands.h"
+#include "fpsensor_auth_crypto.h"
+#include "fpsensor_state_without_driver_info.h"
+#include "openssl/aes.h"
+#include "openssl/bn.h"
+#include "openssl/ec.h"
+#include "openssl/obj_mac.h"
+#include "test_util.h"
+#include "util.h"
+
+#include <assert.h>
+#include <stdbool.h>
+
+#include <array>
+
+namespace
+{
+
+void init_tpm_seed(void)
+{
+	std::array<uint8_t, 32> fake_tpm_seed = {
+		0xd9, 0x71, 0xaf, 0xc4, 0xcd, 0x36, 0xe3, 0x60,
+		0xf8, 0x5a, 0xa0, 0xa6, 0x2c, 0xb3, 0xf5, 0xe2,
+		0xeb, 0xb9, 0xd8, 0x2f, 0xb5, 0x78, 0x5c, 0x79,
+		0x82, 0xce, 0x06, 0x3f, 0xcc, 0x23, 0xb9, 0xe7,
+	};
+
+	static_assert(fake_tpm_seed.size() == sizeof(tpm_seed));
+
+	std::copy(fake_tpm_seed.begin(), fake_tpm_seed.end(), tpm_seed);
+
+	fp_encryption_status |= FP_ENC_STATUS_SEED_SET;
+}
+
+test_static enum ec_error_list test_fp_encrypt_decrypt_data(void)
+{
+	struct fp_auth_command_encryption_metadata info;
+	const std::array<uint8_t, 32> input = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0,
+						1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1,
+						2, 3, 4, 5, 6, 7, 8, 9, 1, 2 };
+	uint16_t version = 1;
+	std::array<uint8_t, 32> data;
+
+	std::copy(input.begin(), input.end(), data.begin());
+
+	TEST_EQ(encrypt_data_in_place(version, info, data.data(), data.size()),
+		EC_SUCCESS, "%d");
+
+	TEST_EQ(info.struct_version, version, "%d");
+
+	/* The encrypted data should not be the same as the input. */
+	TEST_ASSERT_ARRAY_NE(data, input, data.size());
+
+	std::array<uint8_t, 32> output;
+	TEST_EQ(decrypt_data(info, data.data(), data.size(), output.data(),
+			     output.size()),
+		EC_SUCCESS, "%d");
+
+	TEST_ASSERT_ARRAY_EQ(input, output, sizeof(input));
+
+	return EC_SUCCESS;
+}
+
+test_static enum ec_error_list test_fp_encrypt_decrypt_key(void)
+{
+	uint16_t version = 1;
+	std::array<uint8_t, 32> privkey = { 1, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0,
+					    1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1,
+					    2, 3, 4, 5, 6, 7, 8, 9, 1, 2 };
+
+	bssl::UniquePtr<EC_KEY> key =
+		create_ec_key_from_privkey(privkey.data(), privkey.size());
+
+	TEST_NE(key.get(), nullptr, "%p");
+
+	auto enc_key = create_encrypted_private_key(*key, version);
+	TEST_ASSERT(enc_key.has_value());
+
+	TEST_EQ(enc_key->info.struct_version, version, "%d");
+
+	bssl::UniquePtr<EC_KEY> out_key = decrypt_private_key(*enc_key);
+
+	TEST_NE(key.get(), nullptr, "%p");
+
+	std::array<uint8_t, 32> output_privkey;
+	EC_KEY_priv2oct(out_key.get(), output_privkey.data(),
+			output_privkey.size());
+
+	TEST_ASSERT_ARRAY_EQ(privkey, output_privkey, sizeof(privkey));
+
+	return EC_SUCCESS;
+}
+
+test_static enum ec_error_list test_fp_generate_gsc_session_key(void)
+{
+	std::array<uint8_t, 32> auth_nonce = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0,
+					       1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1,
+					       2, 3, 4, 5, 6, 7, 8, 9, 1, 2 };
+	std::array<uint8_t, 32> gsc_nonce = { 1, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0,
+					      1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1,
+					      2, 3, 4, 5, 6, 7, 8, 9, 1, 2 };
+	std::array<uint8_t, 32> pairing_key = { 2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0,
+						1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1,
+						2, 3, 4, 5, 6, 7, 8, 9, 1, 2 };
+
+	std::array<uint8_t, 32> gsc_session_key;
+
+	TEST_EQ(generate_gsc_session_key(auth_nonce.data(), auth_nonce.size(),
+					 gsc_nonce.data(), gsc_nonce.size(),
+					 pairing_key.data(), pairing_key.size(),
+					 gsc_session_key.data(),
+					 gsc_session_key.size()),
+		EC_SUCCESS, "%d");
+
+	std::array<uint8_t, 32> expected_gsc_session_key = {
+		0X1A, 0X1A, 0X3C, 0X33, 0X7F, 0XAE, 0XF9, 0X3E,
+		0XA8, 0X7C, 0XE4, 0XEC, 0XD9, 0XFF, 0X45, 0X8A,
+		0XB6, 0X2F, 0X75, 0XD5, 0XEA, 0X25, 0X93, 0X36,
+		0X60, 0XF1, 0XAB, 0XD2, 0XF4, 0X9F, 0X22, 0X89,
+	};
+
+	TEST_ASSERT_ARRAY_EQ(gsc_session_key, expected_gsc_session_key,
+			     gsc_session_key.size());
+
+	return EC_SUCCESS;
+}
+
+test_static enum ec_error_list test_fp_generate_gsc_session_key_fail(void)
+{
+	std::array<uint8_t, 32> auth_nonce = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0,
+					       1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1,
+					       2, 3, 4, 5, 6, 7, 8, 9, 1, 2 };
+	std::array<uint8_t, 32> gsc_nonce = { 1, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0,
+					      1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1,
+					      2, 3, 4, 5, 6, 7, 8, 9, 1, 2 };
+	std::array<uint8_t, 32> pairing_key = { 2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0,
+						1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1,
+						2, 3, 4, 5, 6, 7, 8, 9, 1, 2 };
+
+	/* Wrong gsc_session_key size. */
+	std::array<uint8_t, 30> gsc_session_key;
+
+	TEST_NE(generate_gsc_session_key(auth_nonce.data(), auth_nonce.size(),
+					 gsc_nonce.data(), gsc_nonce.size(),
+					 pairing_key.data(), pairing_key.size(),
+					 gsc_session_key.data(),
+					 gsc_session_key.size()),
+		EC_SUCCESS, "%d");
+
+	return EC_SUCCESS;
+}
+
+test_static enum ec_error_list
+test_fp_decrypt_data_with_gsc_session_key_in_place(void)
+{
+	std::array<uint8_t, 32> gsc_session_key = {
+		0X1A, 0X1A, 0X3C, 0X33, 0X7F, 0XAE, 0XF9, 0X3E,
+		0XA8, 0X7C, 0XE4, 0XEC, 0XD9, 0XFF, 0X45, 0X8A,
+		0XB6, 0X2F, 0X75, 0XD5, 0XEA, 0X25, 0X93, 0X36,
+		0X60, 0XF1, 0XAB, 0XD2, 0XF4, 0X9F, 0X22, 0X89,
+	};
+
+	std::array<uint8_t, 16> iv = {
+		0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1, 2, 3, 4, 5,
+	};
+
+	std::array<uint8_t, 32> data = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0,
+					 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1,
+					 2, 3, 4, 5, 6, 7, 8, 9, 1, 2 };
+
+	TEST_EQ(decrypt_data_with_gsc_session_key_in_place(
+			gsc_session_key.data(), gsc_session_key.size(),
+			iv.data(), iv.size(), data.data(), data.size()),
+		EC_SUCCESS, "%d");
+
+	std::array<uint8_t, 32> expected_data = {
+		0X6D, 0XED, 0XAD, 0X04, 0XF8, 0XDB, 0XAE, 0X51,
+		0XF8, 0XEE, 0X94, 0X7E, 0XDB, 0X12, 0X14, 0X22,
+		0X38, 0X32, 0X27, 0XC5, 0X19, 0X72, 0XA3, 0X60,
+		0X67, 0X71, 0X25, 0XE8, 0X27, 0X56, 0XC6, 0X35,
+	};
+
+	TEST_ASSERT_ARRAY_EQ(data, expected_data, data.size());
+
+	return EC_SUCCESS;
+}
+
+test_static enum ec_error_list
+test_fp_decrypt_data_with_gsc_session_key_in_place_fail(void)
+{
+	std::array<uint8_t, 32> gsc_session_key = {
+		0X1A, 0X1A, 0X3C, 0X33, 0X7F, 0XAE, 0XF9, 0X3E,
+		0XA8, 0X7C, 0XE4, 0XEC, 0XD9, 0XFF, 0X45, 0X8A,
+		0XB6, 0X2F, 0X75, 0XD5, 0XEA, 0X25, 0X93, 0X36,
+		0X60, 0XF1, 0XAB, 0XD2, 0XF4, 0X9F, 0X22, 0X89,
+	};
+
+	/* Wrong IV size. */
+	std::array<uint8_t, 32> iv = {
+		0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1, 2, 3, 4, 5,
+		0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1, 2, 3, 4, 5,
+	};
+
+	std::array<uint8_t, 32> data = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0,
+					 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1,
+					 2, 3, 4, 5, 6, 7, 8, 9, 1, 2 };
+
+	TEST_NE(decrypt_data_with_gsc_session_key_in_place(
+			gsc_session_key.data(), gsc_session_key.size(),
+			iv.data(), iv.size(), data.data(), data.size()),
+		EC_SUCCESS, "%d");
+
+	return EC_SUCCESS;
+}
+
+test_static enum ec_error_list test_fp_encrypt_data_with_ecdh_key_in_place(void)
+{
+	constexpr std::array<uint8_t, FP_ELLIPTIC_CURVE_PUBLIC_KEY_IV_LEN>
+		zero_iv = { 0 };
+
+	bssl::UniquePtr<EC_KEY> ecdh_key = generate_elliptic_curve_key();
+
+	std::optional<fp_elliptic_curve_public_key> pubkey =
+		create_pubkey_from_ec_key(*ecdh_key);
+
+	TEST_ASSERT(pubkey.has_value());
+
+	TEST_NE(ecdh_key.get(), nullptr, "%p");
+
+	struct fp_elliptic_curve_public_key response_pubkey;
+
+	std::array<uint8_t, FP_POSITIVE_MATCH_SECRET_BYTES> secret = {
+		0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1, 2, 3, 4, 5,
+		6, 7, 8, 9, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 1, 2
+	};
+
+	std::array<uint8_t, FP_POSITIVE_MATCH_SECRET_BYTES> enc_secret = secret;
+
+	std::array<uint8_t, FP_ELLIPTIC_CURVE_PUBLIC_KEY_IV_LEN> iv = {};
+
+	TEST_ASSERT_ARRAY_EQ(iv, zero_iv, iv.size());
+
+	TEST_EQ(encrypt_data_with_ecdh_key_in_place(
+			*pubkey, enc_secret.data(), enc_secret.size(),
+			iv.data(), iv.size(), response_pubkey),
+		EC_SUCCESS, "%d");
+
+	/* The encrypted data should not be the same as the input. */
+	TEST_ASSERT_ARRAY_NE(enc_secret, secret, secret.size());
+
+	/* The IV should not be zero. */
+	TEST_ASSERT_ARRAY_NE(iv, zero_iv, iv.size());
+
+	bssl::UniquePtr<EC_KEY> output_key =
+		create_ec_key_from_pubkey(response_pubkey);
+
+	TEST_NE(output_key.get(), nullptr, "%p");
+
+	std::array<uint8_t, 32> share_secret;
+	TEST_EQ(generate_ecdh_shared_secret(*ecdh_key, *output_key,
+					    share_secret.data(),
+					    share_secret.size()),
+		EC_SUCCESS, "%d");
+
+	AES_KEY aes_key;
+	TEST_EQ(AES_set_encrypt_key(share_secret.data(), 256, &aes_key), 0,
+		"%d");
+
+	unsigned int block_num = 0;
+	std::array<uint8_t, AES_BLOCK_SIZE> ecount_buf;
+
+	/* The AES CTR uses the same function for encryption & decryption. */
+	AES_ctr128_encrypt(enc_secret.data(), enc_secret.data(),
+			   enc_secret.size(), &aes_key, iv.data(),
+			   ecount_buf.data(), &block_num);
+
+	/* The secret should be the same after decrypt. */
+	TEST_ASSERT_ARRAY_EQ(enc_secret, secret, secret.size());
+
+	return EC_SUCCESS;
+}
+
+} // namespace
+
+extern "C" void run_test(int argc, const char **argv)
+{
+	init_tpm_seed();
+
+	RUN_TEST(test_fp_encrypt_decrypt_data);
+	RUN_TEST(test_fp_encrypt_decrypt_key);
+	RUN_TEST(test_fp_generate_gsc_session_key);
+	RUN_TEST(test_fp_generate_gsc_session_key_fail);
+	RUN_TEST(test_fp_decrypt_data_with_gsc_session_key_in_place);
+	RUN_TEST(test_fp_decrypt_data_with_gsc_session_key_in_place_fail);
+	RUN_TEST(test_fp_encrypt_data_with_ecdh_key_in_place);
+	test_print_result();
+}
diff --git a/test/fpsensor_auth_crypto_stateful.mocklist b/test/fpsensor_auth_crypto_stateful.mocklist
new file mode 100644
index 0000000000..c28558df85
--- /dev/null
+++ b/test/fpsensor_auth_crypto_stateful.mocklist
@@ -0,0 +1,7 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define CONFIG_TEST_MOCK_LIST \
+	MOCK(ROLLBACK)
diff --git a/test/fpsensor_auth_crypto_stateful.tasklist b/test/fpsensor_auth_crypto_stateful.tasklist
new file mode 100644
index 0000000000..d1920322a9
--- /dev/null
+++ b/test/fpsensor_auth_crypto_stateful.tasklist
@@ -0,0 +1,9 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST
diff --git a/test/fpsensor_auth_crypto_stateless.cc b/test/fpsensor_auth_crypto_stateless.cc
new file mode 100644
index 0000000000..a6e6bd633d
--- /dev/null
+++ b/test/fpsensor_auth_crypto_stateless.cc
@@ -0,0 +1,184 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "ec_commands.h"
+#include "fpsensor_auth_crypto.h"
+#include "openssl/bn.h"
+#include "openssl/ec.h"
+#include "openssl/obj_mac.h"
+#include "test_util.h"
+#include "util.h"
+
+#include <assert.h>
+#include <stdbool.h>
+
+#include <array>
+
+extern "C" enum ec_error_list rollback_get_secret(uint8_t *secret)
+{
+	// We should not call this function in the test.
+	TEST_ASSERT(false);
+}
+
+namespace
+{
+
+test_static enum ec_error_list test_fp_create_ec_key_from_pubkey(void)
+{
+	fp_elliptic_curve_public_key pubkey = {
+		.x = {
+			0x85, 0xAD, 0x35, 0x23, 0x05, 0x1E, 0x33, 0x3F,
+			0xCA, 0xA7, 0xEA, 0xA5, 0x88, 0x33, 0x12, 0x95,
+			0xA7, 0xB5, 0x98, 0x9F, 0x32, 0xEF, 0x7D, 0xE9,
+			0xF8, 0x70, 0x14, 0x5E, 0x89, 0xCB, 0xDE, 0x1F,
+		},
+		.y = {
+			0xD1, 0xDC, 0x91, 0xC6, 0xE6, 0x5B, 0x1E, 0x3C,
+			0x01, 0x6C, 0xE6, 0x50, 0x25, 0x5D, 0x89, 0xCF,
+			0xB7, 0x8D, 0x88, 0xB9, 0x0D, 0x09, 0x41, 0xF1,
+			0x09, 0x4F, 0x61, 0x55, 0x6C, 0xC4, 0x96, 0x6B,
+		},
+	};
+
+	bssl::UniquePtr<EC_KEY> key = create_ec_key_from_pubkey(pubkey);
+
+	TEST_NE(key.get(), nullptr, "%p");
+	TEST_EQ(EC_KEY_check_key(key.get()), 1, "%d");
+
+	return EC_SUCCESS;
+}
+
+test_static enum ec_error_list test_fp_create_ec_key_from_pubkey_fail(void)
+{
+	fp_elliptic_curve_public_key pubkey = {
+		.x = {},
+		.y = {},
+	};
+
+	bssl::UniquePtr<EC_KEY> key = create_ec_key_from_pubkey(pubkey);
+
+	TEST_EQ(key.get(), nullptr, "%p");
+
+	return EC_SUCCESS;
+}
+
+test_static enum ec_error_list test_fp_create_pubkey_from_ec_key(void)
+{
+	fp_elliptic_curve_public_key pubkey = {
+		.x = {
+			0x85, 0xAD, 0x35, 0x23, 0x05, 0x1E, 0x33, 0x3F,
+			0xCA, 0xA7, 0xEA, 0xA5, 0x88, 0x33, 0x12, 0x95,
+			0xA7, 0xB5, 0x98, 0x9F, 0x32, 0xEF, 0x7D, 0xE9,
+			0xF8, 0x70, 0x14, 0x5E, 0x89, 0xCB, 0xDE, 0x1F,
+		},
+		.y = {
+			0xD1, 0xDC, 0x91, 0xC6, 0xE6, 0x5B, 0x1E, 0x3C,
+			0x01, 0x6C, 0xE6, 0x50, 0x25, 0x5D, 0x89, 0xCF,
+			0xB7, 0x8D, 0x88, 0xB9, 0x0D, 0x09, 0x41, 0xF1,
+			0x09, 0x4F, 0x61, 0x55, 0x6C, 0xC4, 0x96, 0x6B,
+		},
+	};
+
+	bssl::UniquePtr<EC_KEY> key = create_ec_key_from_pubkey(pubkey);
+
+	TEST_NE(key.get(), nullptr, "%p");
+	TEST_EQ(EC_KEY_check_key(key.get()), 1, "%d");
+
+	auto result = create_pubkey_from_ec_key(*key);
+	TEST_ASSERT(result.has_value());
+
+	TEST_ASSERT_ARRAY_EQ(result->x, pubkey.x, sizeof(pubkey.x));
+	TEST_ASSERT_ARRAY_EQ(result->y, pubkey.y, sizeof(pubkey.y));
+
+	return EC_SUCCESS;
+}
+
+test_static enum ec_error_list test_fp_create_ec_key_from_privkey(void)
+{
+	std::array<uint8_t, 32> data = {};
+
+	bssl::UniquePtr<EC_KEY> key =
+		create_ec_key_from_privkey(data.data(), data.size());
+
+	TEST_NE(key.get(), nullptr, "%p");
+
+	/* There is nothing to check for the private key. */
+
+	return EC_SUCCESS;
+}
+
+test_static enum ec_error_list test_fp_create_ec_key_from_privkey_fail(void)
+{
+	std::array<uint8_t, 1> data = {};
+
+	bssl::UniquePtr<EC_KEY> key =
+		create_ec_key_from_privkey(data.data(), data.size());
+
+	TEST_EQ(key.get(), nullptr, "%p");
+
+	return EC_SUCCESS;
+}
+
+test_static enum ec_error_list test_fp_generate_ecdh_shared_secret(void)
+{
+	struct fp_elliptic_curve_public_key pubkey = {
+		.x = {
+			0x85, 0xAD, 0x35, 0x23, 0x05, 0x1E, 0x33, 0x3F,
+			0xCA, 0xA7, 0xEA, 0xA5, 0x88, 0x33, 0x12, 0x95,
+			0xA7, 0xB5, 0x98, 0x9F, 0x32, 0xEF, 0x7D, 0xE9,
+			0xF8, 0x70, 0x14, 0x5E, 0x89, 0xCB, 0xDE, 0x1F,
+		},
+		.y = {
+			0xD1, 0xDC, 0x91, 0xC6, 0xE6, 0x5B, 0x1E, 0x3C,
+			0x01, 0x6C, 0xE6, 0x50, 0x25, 0x5D, 0x89, 0xCF,
+			0xB7, 0x8D, 0x88, 0xB9, 0x0D, 0x09, 0x41, 0xF1,
+			0x09, 0x4F, 0x61, 0x55, 0x6C, 0xC4, 0x96, 0x6B,
+		},
+	};
+
+	bssl::UniquePtr<EC_KEY> public_key = create_ec_key_from_pubkey(pubkey);
+
+	TEST_NE(public_key.get(), nullptr, "%p");
+
+	std::array<uint8_t, 32> privkey = { 1, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0,
+					    1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1,
+					    2, 3, 4, 5, 6, 7, 8, 9, 1, 2 };
+
+	bssl::UniquePtr<EC_KEY> private_key =
+		create_ec_key_from_privkey(privkey.data(), privkey.size());
+
+	TEST_NE(private_key.get(), nullptr, "%p");
+
+	std::array<uint8_t, 32> shared_secret;
+	TEST_EQ(generate_ecdh_shared_secret(*private_key, *public_key,
+					    shared_secret.data(),
+					    shared_secret.size()),
+		EC_SUCCESS, "%d");
+
+	std::array<uint8_t, 32> expected_result = {
+		0x46, 0x86, 0xca, 0x75, 0xce, 0xa1, 0xde, 0x23,
+		0x48, 0xb3, 0x0b, 0xfc, 0xd7, 0xbe, 0x7a, 0xa0,
+		0x33, 0x17, 0x6c, 0x97, 0xc6, 0xa7, 0x70, 0x7c,
+		0xd4, 0x2c, 0xfd, 0xc0, 0xba, 0xc1, 0x47, 0x01,
+	};
+
+	TEST_ASSERT_ARRAY_EQ(shared_secret, expected_result,
+			     shared_secret.size());
+	return EC_SUCCESS;
+}
+
+} // namespace
+
+extern "C" void run_test(int argc, const char **argv)
+{
+	RUN_TEST(test_fp_create_ec_key_from_pubkey);
+	RUN_TEST(test_fp_create_ec_key_from_pubkey_fail);
+	RUN_TEST(test_fp_create_ec_key_from_privkey);
+	RUN_TEST(test_fp_create_ec_key_from_privkey_fail);
+	RUN_TEST(test_fp_create_pubkey_from_ec_key);
+	RUN_TEST(test_fp_generate_ecdh_shared_secret);
+	test_print_result();
+}
diff --git a/test/fpsensor_auth_crypto_stateless.tasklist b/test/fpsensor_auth_crypto_stateless.tasklist
new file mode 100644
index 0000000000..d1920322a9
--- /dev/null
+++ b/test/fpsensor_auth_crypto_stateless.tasklist
@@ -0,0 +1,9 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST
diff --git a/test/fpsensor_crypto.c b/test/fpsensor_crypto.c
deleted file mode 100644
index d0fd92cf7c..0000000000
--- a/test/fpsensor_crypto.c
+++ /dev/null
@@ -1,643 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <stdbool.h>
-
-#include "common.h"
-#include "ec_commands.h"
-#include "fpsensor_crypto.h"
-#include "fpsensor_state.h"
-#include "mock/fpsensor_state_mock.h"
-#include "mock/rollback_mock.h"
-#include "mock/timer_mock.h"
-#include "test_util.h"
-#include "util.h"
-
-static const uint8_t fake_positive_match_salt[] = {
-	0x04, 0x1f, 0x5a, 0xac, 0x5f, 0x79, 0x10, 0xaf,
-	0x04, 0x1d, 0x46, 0x3a, 0x5f, 0x08, 0xee, 0xcb,
-};
-
-static const uint8_t fake_user_id[] = {
-	0x28, 0xb5, 0x5a, 0x55, 0x57, 0x1b, 0x26, 0x88,
-	0xce, 0xc5, 0xd1, 0xfe, 0x1d, 0x58, 0x5b, 0x94,
-	0x51, 0xa2, 0x60, 0x49, 0x9f, 0xea, 0xb1, 0xea,
-	0xf7, 0x04, 0x2f, 0x0b, 0x20, 0xa5, 0x93, 0x64,
-};
-
-/*
- * |expected_positive_match_secret_for_empty_user_id| is obtained by running
- * BoringSSL locally.
- * From https://boringssl.googlesource.com/boringssl
- * commit 365b7a0fcbf273b1fa704d151059e419abd6cfb8
- *
- * Steps to reproduce:
- *
- * Open boringssl/crypto/hkdf/hkdf_test.cc
- * Add the following case to static const HKDFTestVector kTests[]
- *
- * // test positive match secret
- * {
- *   EVP_sha256,
- *   {
- *     // IKM:
- *     // fake_rollback_secret
- *     [ ***Copy 32 octets of fake_rollback_secret here*** ]
- *     // fake_tpm_seed
- *     [ ***Copy 32 octets of fake_tpm_seed here*** ]
- *   }, 64,
- *   {
- *     // fake_positive_match_salt
- *     [ ***Copy 16 octets of fake_positive_match_salt here*** ]
- *   }, 16,
- *   {
- *     // Info:
- *     // "positive_match_secret for user "
- *     0x70, 0x6f, 0x73, 0x69, 0x74, 0x69, 0x76, 0x65,
- *     0x5f, 0x6d, 0x61, 0x74, 0x63, 0x68, 0x5f, 0x73,
- *     0x65, 0x63, 0x72, 0x65, 0x74, 0x20, 0x66, 0x6f,
- *     0x72, 0x20, 0x75, 0x73, 0x65, 0x72, 0x20,
- *     // user_id
- *     [ ***Type 32 octets of 0x00 here*** ]
- *   }, 63,
- *   {  // Expected PRK:
- *     0xc2, 0xff, 0x50, 0x2d, 0xb1, 0x7e, 0x87, 0xb1,
- *     0x25, 0x36, 0x3a, 0x88, 0xe1, 0xdb, 0x4f, 0x98,
- *     0x22, 0xb5, 0x66, 0x8c, 0xab, 0xb7, 0xc7, 0x5e,
- *     0xd7, 0x56, 0xbe, 0xde, 0x82, 0x3f, 0xd0, 0x62,
- *   }, 32,
- *   32, { // 32 = L = FP_POSITIVE_MATCH_SECRET_BYTES
- *     // Expected positive match secret:
- *     [ ***Copy 32 octets of expected positive_match_secret here*** ]
- *   }
- * },
- *
- * Then from boringssl/ execute:
- * mkdir build
- * cd build
- * cmake ..
- * make
- * cd ..
- * go run util/all_tests.go
- */
-static const uint8_t expected_positive_match_secret_for_empty_user_id[] = {
-	0x8d, 0xc4, 0x5b, 0xdf, 0x55, 0x1e, 0xa8, 0x72,
-	0xd6, 0xdd, 0xa1, 0x4c, 0xb8, 0xa1, 0x76, 0x2b,
-	0xde, 0x38, 0xd5, 0x03, 0xce, 0xe4, 0x74, 0x51,
-	0x63, 0x6c, 0x6a, 0x26, 0xa9, 0xb7, 0xfa, 0x68,
-};
-
-/*
- * Same as |expected_positive_match_secret_for_empty_user_id| but use
- * |fake_user_id| instead of all-zero user_id.
- */
-static const uint8_t expected_positive_match_secret_for_fake_user_id[] = {
-	0x0d, 0xf5, 0xac, 0x7c, 0xad, 0x37, 0x0a, 0x66,
-	0x2f, 0x71, 0xf6, 0xc6, 0xca, 0x8a, 0x41, 0x69,
-	0x8a, 0xd3, 0xcf, 0x0b, 0xc4, 0x5a, 0x5f, 0x4d,
-	0x54, 0xeb, 0x7b, 0xad, 0x5d, 0x1b, 0xbe, 0x30,
-};
-
-static int test_hkdf_expand_raw(const uint8_t *prk, size_t prk_size,
-				const uint8_t *info, size_t info_size,
-				const uint8_t *expected_okm, size_t okm_size)
-{
-	uint8_t actual_okm[okm_size];
-
-	TEST_ASSERT(hkdf_expand(actual_okm, okm_size, prk, prk_size,
-				info, info_size) == EC_SUCCESS);
-	TEST_ASSERT_ARRAY_EQ(expected_okm, actual_okm, okm_size);
-	return EC_SUCCESS;
-}
-
-test_static int test_hkdf_expand(void)
-{
-	/* Test vectors in https://tools.ietf.org/html/rfc5869#appendix-A */
-	static const uint8_t prk1[] = {
-		0x07, 0x77, 0x09, 0x36, 0x2c, 0x2e, 0x32, 0xdf,
-		0x0d, 0xdc, 0x3f, 0x0d, 0xc4, 0x7b, 0xba, 0x63,
-		0x90, 0xb6, 0xc7, 0x3b, 0xb5, 0x0f, 0x9c, 0x31,
-		0x22, 0xec, 0x84, 0x4a, 0xd7, 0xc2, 0xb3, 0xe5,
-	};
-	static const uint8_t info1[] = {
-		0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
-		0xf8, 0xf9,
-	};
-	static const uint8_t expected_okm1[] = {
-		0x3c, 0xb2, 0x5f, 0x25, 0xfa, 0xac, 0xd5, 0x7a,
-		0x90, 0x43, 0x4f, 0x64, 0xd0, 0x36, 0x2f, 0x2a,
-		0x2d, 0x2d, 0x0a, 0x90, 0xcf, 0x1a, 0x5a, 0x4c,
-		0x5d, 0xb0, 0x2d, 0x56, 0xec, 0xc4, 0xc5, 0xbf,
-		0x34, 0x00, 0x72, 0x08, 0xd5, 0xb8, 0x87, 0x18,
-		0x58, 0x65,
-	};
-	static const uint8_t prk2[] = {
-		0x06, 0xa6, 0xb8, 0x8c, 0x58, 0x53, 0x36, 0x1a,
-		0x06, 0x10, 0x4c, 0x9c, 0xeb, 0x35, 0xb4, 0x5c,
-		0xef, 0x76, 0x00, 0x14, 0x90, 0x46, 0x71, 0x01,
-		0x4a, 0x19, 0x3f, 0x40, 0xc1, 0x5f, 0xc2, 0x44,
-	};
-	static const uint8_t info2[] = {
-		0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7,
-		0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf,
-		0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
-		0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf,
-		0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
-		0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf,
-		0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
-		0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef,
-		0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
-		0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff,
-	};
-	static const uint8_t expected_okm2[] = {
-		0xb1, 0x1e, 0x39, 0x8d, 0xc8, 0x03, 0x27, 0xa1,
-		0xc8, 0xe7, 0xf7, 0x8c, 0x59, 0x6a, 0x49, 0x34,
-		0x4f, 0x01, 0x2e, 0xda, 0x2d, 0x4e, 0xfa, 0xd8,
-		0xa0, 0x50, 0xcc, 0x4c, 0x19, 0xaf, 0xa9, 0x7c,
-		0x59, 0x04, 0x5a, 0x99, 0xca, 0xc7, 0x82, 0x72,
-		0x71, 0xcb, 0x41, 0xc6, 0x5e, 0x59, 0x0e, 0x09,
-		0xda, 0x32, 0x75, 0x60, 0x0c, 0x2f, 0x09, 0xb8,
-		0x36, 0x77, 0x93, 0xa9, 0xac, 0xa3, 0xdb, 0x71,
-		0xcc, 0x30, 0xc5, 0x81, 0x79, 0xec, 0x3e, 0x87,
-		0xc1, 0x4c, 0x01, 0xd5, 0xc1, 0xf3, 0x43, 0x4f,
-		0x1d, 0x87,
-	};
-	static const uint8_t prk3[] = {
-		0x19, 0xef, 0x24, 0xa3, 0x2c, 0x71, 0x7b, 0x16,
-		0x7f, 0x33, 0xa9, 0x1d, 0x6f, 0x64, 0x8b, 0xdf,
-		0x96, 0x59, 0x67, 0x76, 0xaf, 0xdb, 0x63, 0x77,
-		0xac, 0x43, 0x4c, 0x1c, 0x29, 0x3c, 0xcb, 0x04,
-	};
-	static const uint8_t expected_okm3[] = {
-		0x8d, 0xa4, 0xe7, 0x75, 0xa5, 0x63, 0xc1, 0x8f,
-		0x71, 0x5f, 0x80, 0x2a, 0x06, 0x3c, 0x5a, 0x31,
-		0xb8, 0xa1, 0x1f, 0x5c, 0x5e, 0xe1, 0x87, 0x9e,
-		0xc3, 0x45, 0x4e, 0x5f, 0x3c, 0x73, 0x8d, 0x2d,
-		0x9d, 0x20, 0x13, 0x95, 0xfa, 0xa4, 0xb6, 0x1a,
-		0x96, 0xc8,
-	};
-	static uint8_t unused_output[SHA256_DIGEST_SIZE] = { 0 };
-
-	TEST_ASSERT(test_hkdf_expand_raw(prk1, sizeof(prk1), info1,
-					 sizeof(info1), expected_okm1,
-					 sizeof(expected_okm1))
-			    == EC_SUCCESS);
-	TEST_ASSERT(test_hkdf_expand_raw(prk2, sizeof(prk2), info2,
-					 sizeof(info2), expected_okm2,
-					 sizeof(expected_okm2))
-			    == EC_SUCCESS);
-	TEST_ASSERT(test_hkdf_expand_raw(prk3, sizeof(prk3), NULL, 0,
-					 expected_okm3, sizeof(expected_okm3))
-			    == EC_SUCCESS);
-
-	TEST_ASSERT(hkdf_expand(NULL, sizeof(unused_output), prk1,
-				sizeof(prk1), info1, sizeof(info1))
-			    == EC_ERROR_INVAL);
-	TEST_ASSERT(hkdf_expand(unused_output, sizeof(unused_output),
-				NULL, sizeof(prk1), info1, sizeof(info1))
-			    == EC_ERROR_INVAL);
-	TEST_ASSERT(hkdf_expand(unused_output, sizeof(unused_output),
-				prk1, sizeof(prk1), NULL, sizeof(info1))
-			    == EC_ERROR_INVAL);
-	/* Info size too long. */
-	TEST_ASSERT(hkdf_expand(unused_output, sizeof(unused_output),
-				prk1, sizeof(prk1), info1, 1024)
-			    == EC_ERROR_INVAL);
-	/* OKM size too big. */
-	TEST_ASSERT(hkdf_expand(unused_output, 256 * SHA256_DIGEST_SIZE,
-				prk1, sizeof(prk1), info1, sizeof(info1))
-			    == EC_ERROR_INVAL);
-	return EC_SUCCESS;
-}
-
-test_static int test_derive_encryption_key_failure_seed_not_set(void)
-{
-	static uint8_t unused_key[SBP_ENC_KEY_LEN];
-	static const uint8_t unused_salt[FP_CONTEXT_ENCRYPTION_SALT_BYTES]
-		= { 0 };
-
-	/* GIVEN that the TPM seed is not set. */
-	if (fp_tpm_seed_is_set()) {
-		ccprintf("%s:%s(): this test should be executed before setting"
-			 " TPM seed.\n",
-			 __FILE__, __func__);
-		return -1;
-	}
-
-	/* THEN derivation will fail. */
-	TEST_ASSERT(derive_encryption_key(unused_key, unused_salt) ==
-		    EC_ERROR_ACCESS_DENIED);
-
-	return EC_SUCCESS;
-}
-
-static int test_derive_encryption_key_raw(const uint32_t *user_id_,
-					  const uint8_t *salt,
-					  const uint8_t *expected_key)
-{
-	uint8_t key[SBP_ENC_KEY_LEN];
-	int rv;
-
-	/*
-	 * |user_id| is a global variable used as "info" in HKDF expand
-	 * in derive_encryption_key().
-	 */
-	memcpy(user_id, user_id_, sizeof(user_id));
-	rv = derive_encryption_key(key, salt);
-
-	TEST_ASSERT(rv == EC_SUCCESS);
-	TEST_ASSERT_ARRAY_EQ(key, expected_key, sizeof(key));
-
-	memset(user_id, 0, sizeof(user_id));
-
-	return EC_SUCCESS;
-}
-
-test_static int test_derive_encryption_key(void)
-{
-	/*
-	 * These vectors are obtained by choosing the salt and the user_id
-	 * (used as "info" in HKDF), and running boringSSL's HKDF
-	 * (https://boringssl.googlesource.com/boringssl/+/c0b4c72b6d4c6f4828a373ec454bd646390017d4/crypto/hkdf/)
-	 * locally to get the output key. The IKM used in the run is the
-	 * concatenation of |fake_rollback_secret| and |fake_tpm_seed|.
-	 */
-	static const uint32_t user_id1[] = {
-		0x608b1b0b, 0xe10d3d24, 0x0bbbe4e6, 0x807b36d9,
-		0x2a1f8abc, 0xea38104a, 0x562d9431, 0x64d721c5,
-	};
-
-	static const uint8_t salt1[] = {
-		0xd0, 0x88, 0x34, 0x15, 0xc0, 0xfa, 0x8e, 0x22,
-		0x9f, 0xb4, 0xd5, 0xa9, 0xee, 0xd3, 0x15, 0x19,
-	};
-
-	static const uint8_t key1[] = {
-		0xdb, 0x49, 0x6e, 0x1b, 0x67, 0x8a, 0x35, 0xc6,
-		0xa0, 0x9d, 0xb6, 0xa0, 0x13, 0xf4, 0x21, 0xb3,
-	};
-
-	static const uint32_t user_id2[] = {
-		0x2546a2ca, 0xf1891f7a, 0x44aad8b8, 0x0d6aac74,
-		0x6a4ab846, 0x9c279796, 0x5a72eae1, 0x8276d2a3,
-	};
-
-	static const uint8_t salt2[] = {
-		0x72, 0x6b, 0xc1, 0xe4, 0x64, 0xd4, 0xff, 0xa2,
-		0x5a, 0xac, 0x5b, 0x0b, 0x06, 0x67, 0xe1, 0x53,
-	};
-
-	static const uint8_t key2[] = {
-		0x8d, 0x53, 0xaf, 0x4c, 0x96, 0xa2, 0xee, 0x46,
-		0x9c, 0xe2, 0xe2, 0x6f, 0xe6, 0x66, 0x3d, 0x3a,
-	};
-
-	/*
-	 * GIVEN that the TPM seed is set, and reading the rollback secret will
-	 * succeed.
-	 */
-	TEST_ASSERT(fp_tpm_seed_is_set() &&
-		    !mock_ctrl_rollback.get_secret_fail);
-
-	/* THEN the derivation will succeed. */
-	TEST_ASSERT(test_derive_encryption_key_raw(user_id1, salt1, key1) ==
-		    EC_SUCCESS);
-
-	TEST_ASSERT(test_derive_encryption_key_raw(user_id2, salt2, key2) ==
-		    EC_SUCCESS);
-
-	return EC_SUCCESS;
-}
-
-test_static int test_derive_encryption_key_failure_rollback_fail(void)
-{
-	static uint8_t unused_key[SBP_ENC_KEY_LEN];
-	static const uint8_t unused_salt[FP_CONTEXT_ENCRYPTION_SALT_BYTES]
-		= { 0 };
-
-	/* GIVEN that reading the rollback secret will fail. */
-	mock_ctrl_rollback.get_secret_fail = true;
-	/* THEN the derivation will fail. */
-	TEST_ASSERT(derive_encryption_key(unused_key, unused_salt) ==
-		    EC_ERROR_HW_INTERNAL);
-
-	/* GIVEN that reading the rollback secret will succeed. */
-	mock_ctrl_rollback.get_secret_fail = false;
-	/* GIVEN that the TPM seed has been set. */
-	TEST_ASSERT(fp_tpm_seed_is_set());
-	/* THEN the derivation will succeed. */
-	TEST_ASSERT(derive_encryption_key(unused_key, unused_salt) ==
-		    EC_SUCCESS);
-
-	return EC_SUCCESS;
-}
-
-test_static int test_derive_positive_match_secret_fail_seed_not_set(void)
-{
-	static uint8_t output[FP_POSITIVE_MATCH_SECRET_BYTES];
-
-	/* GIVEN that seed is not set. */
-	TEST_ASSERT(!fp_tpm_seed_is_set());
-	/* THEN EVEN IF the encryption salt is not trivial. */
-	TEST_ASSERT(!bytes_are_trivial(fake_positive_match_salt,
-				       sizeof(fake_positive_match_salt)));
-
-	/* Deriving positive match secret will fail. */
-	TEST_ASSERT(derive_positive_match_secret(output,
-						 fake_positive_match_salt)
-		== EC_ERROR_ACCESS_DENIED);
-
-	return EC_SUCCESS;
-
-}
-
-test_static int test_derive_new_pos_match_secret(void)
-{
-	static uint8_t output[FP_POSITIVE_MATCH_SECRET_BYTES];
-
-	/* First, for empty user_id. */
-	memset(user_id, 0, sizeof(user_id));
-
-	/* GIVEN that the encryption salt is not trivial. */
-	TEST_ASSERT(!bytes_are_trivial(fake_positive_match_salt,
-				       sizeof(fake_positive_match_salt)));
-	/*
-	 * GIVEN that the TPM seed is set, and reading the rollback secret will
-	 * succeed.
-	 */
-	TEST_ASSERT(
-		fp_tpm_seed_is_set() && !mock_ctrl_rollback.get_secret_fail);
-
-	/* GIVEN that the salt is not trivial. */
-	TEST_ASSERT(!bytes_are_trivial(fake_positive_match_salt,
-				       sizeof(fake_positive_match_salt)));
-
-	/* THEN the derivation will succeed. */
-	TEST_ASSERT(derive_positive_match_secret(output,
-						 fake_positive_match_salt)
-		== EC_SUCCESS);
-	TEST_ASSERT_ARRAY_EQ(
-		output,
-		expected_positive_match_secret_for_empty_user_id,
-		sizeof(expected_positive_match_secret_for_empty_user_id));
-
-	/* Now change the user_id to be non-trivial. */
-	memcpy(user_id, fake_user_id, sizeof(fake_user_id));
-	TEST_ASSERT(derive_positive_match_secret(output,
-						 fake_positive_match_salt)
-		== EC_SUCCESS);
-	TEST_ASSERT_ARRAY_EQ(
-		output,
-		expected_positive_match_secret_for_fake_user_id,
-		sizeof(expected_positive_match_secret_for_fake_user_id));
-	memset(user_id, 0, sizeof(user_id));
-
-	return EC_SUCCESS;
-}
-
-test_static int test_derive_positive_match_secret_fail_rollback_fail(void)
-{
-	static uint8_t output[FP_POSITIVE_MATCH_SECRET_BYTES];
-
-	/* GIVEN that reading secret from anti-rollback block will fail. */
-	mock_ctrl_rollback.get_secret_fail = true;
-	/* THEN EVEN IF the encryption salt is not trivial. */
-	TEST_ASSERT(!bytes_are_trivial(fake_positive_match_salt,
-				       sizeof(fake_positive_match_salt)));
-
-	/* Deriving positive match secret will fail. */
-	TEST_ASSERT(derive_positive_match_secret(output,
-						 fake_positive_match_salt)
-		== EC_ERROR_HW_INTERNAL);
-	mock_ctrl_rollback.get_secret_fail = false;
-
-	return EC_SUCCESS;
-}
-
-test_static int test_derive_positive_match_secret_fail_salt_trivial(void)
-{
-	static uint8_t output[FP_POSITIVE_MATCH_SECRET_BYTES];
-
-	/* GIVEN that the salt is trivial. */
-	static const uint8_t salt[FP_CONTEXT_ENCRYPTION_SALT_BYTES] = { 0 };
-
-	/* THEN deriving positive match secret will fail. */
-	TEST_ASSERT(derive_positive_match_secret(output, salt)
-		== EC_ERROR_INVAL);
-	return EC_SUCCESS;
-}
-
-static int test_enable_positive_match_secret_once(
-	struct positive_match_secret_state *dumb_state)
-{
-	const int8_t kIndexToEnable = 0;
-	timestamp_t now = get_time();
-
-	TEST_ASSERT(fp_enable_positive_match_secret(
-		kIndexToEnable, dumb_state) == EC_SUCCESS);
-	TEST_ASSERT(dumb_state->template_matched == kIndexToEnable);
-	TEST_ASSERT(dumb_state->readable);
-	TEST_ASSERT(dumb_state->deadline.val == now.val + (5 * SECOND));
-
-	return EC_SUCCESS;
-}
-
-test_static int test_enable_positive_match_secret(void)
-{
-	struct positive_match_secret_state dumb_state = {
-		.template_matched = FP_NO_SUCH_TEMPLATE,
-		.readable = false,
-		.deadline.val = 0,
-	};
-
-	TEST_ASSERT(test_enable_positive_match_secret_once(&dumb_state)
-		== EC_SUCCESS);
-
-	/* Trying to enable again before reading secret should fail. */
-	TEST_ASSERT(fp_enable_positive_match_secret(0, &dumb_state) ==
-		EC_ERROR_UNKNOWN);
-	TEST_ASSERT(dumb_state.template_matched == FP_NO_SUCH_TEMPLATE);
-	TEST_ASSERT(!dumb_state.readable);
-	TEST_ASSERT(dumb_state.deadline.val == 0);
-
-	return EC_SUCCESS;
-}
-
-test_static int test_disable_positive_match_secret(void)
-{
-	struct positive_match_secret_state dumb_state = {
-		.template_matched = FP_NO_SUCH_TEMPLATE,
-		.readable = false,
-		.deadline.val = 0,
-	};
-
-	TEST_ASSERT(test_enable_positive_match_secret_once(&dumb_state)
-		== EC_SUCCESS);
-
-	fp_disable_positive_match_secret(&dumb_state);
-	TEST_ASSERT(dumb_state.template_matched == FP_NO_SUCH_TEMPLATE);
-	TEST_ASSERT(!dumb_state.readable);
-	TEST_ASSERT(dumb_state.deadline.val == 0);
-
-	return EC_SUCCESS;
-}
-
-test_static int test_command_read_match_secret(void)
-{
-	int rv;
-	struct ec_params_fp_read_match_secret params;
-	struct ec_response_fp_read_match_secret resp;
-	timestamp_t now = get_time();
-
-	/* For empty user_id. */
-	memset(user_id, 0, sizeof(user_id));
-
-	/* Invalid finger index should be rejected. */
-	params.fgr = FP_NO_SUCH_TEMPLATE;
-	rv = test_send_host_command(EC_CMD_FP_READ_MATCH_SECRET, 0, &params,
-				    sizeof(params), NULL, 0);
-	TEST_ASSERT(rv == EC_RES_INVALID_PARAM);
-	params.fgr = FP_MAX_FINGER_COUNT;
-	rv = test_send_host_command(EC_CMD_FP_READ_MATCH_SECRET, 0, &params,
-				    sizeof(params), NULL, 0);
-	TEST_ASSERT(rv == EC_RES_INVALID_PARAM);
-
-	memset(&resp, 0, sizeof(resp));
-	/* GIVEN that finger index is valid. */
-	params.fgr = 0;
-
-	/* GIVEN that positive match secret is enabled. */
-	fp_enable_positive_match_secret(params.fgr,
-					&positive_match_secret_state);
-
-	/* GIVEN that salt is non-trivial. */
-	memcpy(fp_positive_match_salt[0], fake_positive_match_salt,
-	       sizeof(fp_positive_match_salt[0]));
-	/* THEN reading positive match secret should succeed. */
-	rv = test_send_host_command(EC_CMD_FP_READ_MATCH_SECRET, 0, &params,
-				    sizeof(params), &resp, sizeof(resp));
-	if (rv != EC_RES_SUCCESS) {
-		ccprintf("%s:%s(): rv = %d\n", __FILE__, __func__, rv);
-		return -1;
-	}
-	/* AND the readable bit should be cleared after the read. */
-	TEST_ASSERT(positive_match_secret_state.readable == false);
-
-	TEST_ASSERT_ARRAY_EQ(
-		resp.positive_match_secret,
-		expected_positive_match_secret_for_empty_user_id,
-		sizeof(expected_positive_match_secret_for_empty_user_id));
-
-	/*
-	 * Now try reading secret again.
-	 * EVEN IF the deadline has not passed.
-	 */
-	positive_match_secret_state.deadline.val = now.val + 1 * SECOND;
-	rv = test_send_host_command(EC_CMD_FP_READ_MATCH_SECRET, 0, &params,
-				    sizeof(params), NULL, 0);
-	/*
-	 * This time the command should fail because the
-	 * fp_pos_match_secret_readable bit is cleared when the secret was read
-	 * the first time.
-	 */
-	TEST_ASSERT(rv == EC_RES_ACCESS_DENIED);
-
-	return EC_SUCCESS;
-}
-
-test_static int test_command_read_match_secret_wrong_finger(void)
-{
-	int rv;
-	struct ec_params_fp_read_match_secret params;
-
-	/* GIVEN that the finger is not the matched or enrolled finger. */
-	params.fgr = 0;
-	/*
-	 * GIVEN that positive match secret is enabled for a different
-	 * finger.
-	 */
-	fp_enable_positive_match_secret(params.fgr + 1,
-					&positive_match_secret_state);
-
-	/* Reading secret will fail. */
-	rv = test_send_host_command(EC_CMD_FP_READ_MATCH_SECRET, 0, &params,
-				    sizeof(params), NULL, 0);
-	TEST_ASSERT(rv == EC_RES_ACCESS_DENIED);
-	return EC_SUCCESS;
-}
-
-test_static int test_command_read_match_secret_timeout(void)
-{
-	int rv;
-	struct ec_params_fp_read_match_secret params;
-
-	params.fgr = 0;
-	/* GIVEN that the read is too late. */
-	fp_enable_positive_match_secret(params.fgr,
-					&positive_match_secret_state);
-	set_time(positive_match_secret_state.deadline);
-
-	/* EVEN IF encryption salt is non-trivial. */
-	memcpy(fp_positive_match_salt[0], fake_positive_match_salt,
-	       sizeof(fp_positive_match_salt[0]));
-	/* Reading secret will fail. */
-	rv = test_send_host_command(EC_CMD_FP_READ_MATCH_SECRET, 0, &params,
-				    sizeof(params), NULL, 0);
-	TEST_ASSERT(rv == EC_RES_TIMEOUT);
-	return EC_SUCCESS;
-}
-
-test_static int test_command_read_match_secret_unreadable(void)
-{
-	int rv;
-	struct ec_params_fp_read_match_secret params;
-
-	params.fgr = 0;
-	/* GIVEN that the readable bit is not set. */
-	fp_enable_positive_match_secret(params.fgr,
-					&positive_match_secret_state);
-	positive_match_secret_state.readable = false;
-
-	/* EVEN IF the finger is just matched. */
-	TEST_ASSERT(positive_match_secret_state.template_matched
-		== params.fgr);
-
-	/* EVEN IF encryption salt is non-trivial. */
-	memcpy(fp_positive_match_salt[0], fake_positive_match_salt,
-	       sizeof(fp_positive_match_salt[0]));
-	/* Reading secret will fail. */
-	rv = test_send_host_command(EC_CMD_FP_READ_MATCH_SECRET, 0, &params,
-				    sizeof(params), NULL, 0);
-	TEST_ASSERT(rv == EC_RES_ACCESS_DENIED);
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	RUN_TEST(test_hkdf_expand);
-	RUN_TEST(test_derive_encryption_key_failure_seed_not_set);
-	RUN_TEST(test_derive_positive_match_secret_fail_seed_not_set);
-
-	/*
-	 * Set the TPM seed here because it can only be set once and cannot be
-	 * cleared.
-	 */
-	ASSERT(fpsensor_state_mock_set_tpm_seed(default_fake_tpm_seed) ==
-		    EC_SUCCESS);
-
-	/* The following test requires TPM seed to be already set. */
-	RUN_TEST(test_derive_encryption_key);
-	RUN_TEST(test_derive_encryption_key_failure_rollback_fail);
-	RUN_TEST(test_derive_new_pos_match_secret);
-	RUN_TEST(test_derive_positive_match_secret_fail_rollback_fail);
-	RUN_TEST(test_derive_positive_match_secret_fail_salt_trivial);
-	RUN_TEST(test_enable_positive_match_secret);
-	RUN_TEST(test_disable_positive_match_secret);
-	RUN_TEST(test_command_read_match_secret);
-	RUN_TEST(test_command_read_match_secret_wrong_finger);
-	RUN_TEST(test_command_read_match_secret_timeout);
-	RUN_TEST(test_command_read_match_secret_unreadable);
-	test_print_result();
-}
diff --git a/test/fpsensor_crypto.cc b/test/fpsensor_crypto.cc
new file mode 100644
index 0000000000..dca44a2697
--- /dev/null
+++ b/test/fpsensor_crypto.cc
@@ -0,0 +1,788 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "compile_time_macros.h"
+#include "fpsensor_crypto.h"
+#include "fpsensor_state.h"
+
+extern "C" {
+#include "builtin/assert.h"
+#include "common.h"
+#include "ec_commands.h"
+#include "mock/fpsensor_crypto_mock.h"
+#include "mock/fpsensor_state_mock.h"
+#include "mock/rollback_mock.h"
+#include "mock/timer_mock.h"
+#include "test_util.h"
+#include "util.h"
+}
+
+extern int get_ikm(uint8_t *ikm);
+
+#include <stdbool.h>
+
+static const uint8_t fake_positive_match_salt[] = {
+	0x04, 0x1f, 0x5a, 0xac, 0x5f, 0x79, 0x10, 0xaf,
+	0x04, 0x1d, 0x46, 0x3a, 0x5f, 0x08, 0xee, 0xcb,
+};
+
+static const uint8_t fake_user_id[] = {
+	0x28, 0xb5, 0x5a, 0x55, 0x57, 0x1b, 0x26, 0x88, 0xce, 0xc5, 0xd1,
+	0xfe, 0x1d, 0x58, 0x5b, 0x94, 0x51, 0xa2, 0x60, 0x49, 0x9f, 0xea,
+	0xb1, 0xea, 0xf7, 0x04, 0x2f, 0x0b, 0x20, 0xa5, 0x93, 0x64,
+};
+
+/*
+ * |expected_positive_match_secret_for_empty_user_id| is obtained by running
+ * BoringSSL locally.
+ * From https://boringssl.googlesource.com/boringssl
+ * commit 365b7a0fcbf273b1fa704d151059e419abd6cfb8
+ *
+ * Steps to reproduce:
+ *
+ * Open boringssl/crypto/hkdf/hkdf_test.cc
+ * Add the following case to static const HKDFTestVector kTests[]
+ *
+ * // test positive match secret
+ * {
+ *   EVP_sha256,
+ *   {
+ *     // IKM:
+ *     // fake_rollback_secret
+ *     [ ***Copy 32 octets of fake_rollback_secret here*** ]
+ *     // fake_tpm_seed
+ *     [ ***Copy 32 octets of fake_tpm_seed here*** ]
+ *   }, 64,
+ *   {
+ *     // fake_positive_match_salt
+ *     [ ***Copy 16 octets of fake_positive_match_salt here*** ]
+ *   }, 16,
+ *   {
+ *     // Info:
+ *     // "positive_match_secret for user "
+ *     0x70, 0x6f, 0x73, 0x69, 0x74, 0x69, 0x76, 0x65,
+ *     0x5f, 0x6d, 0x61, 0x74, 0x63, 0x68, 0x5f, 0x73,
+ *     0x65, 0x63, 0x72, 0x65, 0x74, 0x20, 0x66, 0x6f,
+ *     0x72, 0x20, 0x75, 0x73, 0x65, 0x72, 0x20,
+ *     // user_id
+ *     [ ***Type 32 octets of 0x00 here*** ]
+ *   }, 63,
+ *   {  // Expected PRK:
+ *     0xc2, 0xff, 0x50, 0x2d, 0xb1, 0x7e, 0x87, 0xb1,
+ *     0x25, 0x36, 0x3a, 0x88, 0xe1, 0xdb, 0x4f, 0x98,
+ *     0x22, 0xb5, 0x66, 0x8c, 0xab, 0xb7, 0xc7, 0x5e,
+ *     0xd7, 0x56, 0xbe, 0xde, 0x82, 0x3f, 0xd0, 0x62,
+ *   }, 32,
+ *   32, { // 32 = L = FP_POSITIVE_MATCH_SECRET_BYTES
+ *     // Expected positive match secret:
+ *     [ ***Copy 32 octets of expected positive_match_secret here*** ]
+ *   }
+ * },
+ *
+ * Then from boringssl/ execute:
+ * mkdir build
+ * cd build
+ * cmake ..
+ * make
+ * cd ..
+ * go run util/all_tests.go
+ */
+static const uint8_t expected_positive_match_secret_for_empty_user_id[] = {
+	0x8d, 0xc4, 0x5b, 0xdf, 0x55, 0x1e, 0xa8, 0x72, 0xd6, 0xdd, 0xa1,
+	0x4c, 0xb8, 0xa1, 0x76, 0x2b, 0xde, 0x38, 0xd5, 0x03, 0xce, 0xe4,
+	0x74, 0x51, 0x63, 0x6c, 0x6a, 0x26, 0xa9, 0xb7, 0xfa, 0x68,
+};
+
+/*
+ * Same as |expected_positive_match_secret_for_empty_user_id| but use
+ * |fake_user_id| instead of all-zero user_id.
+ */
+static const uint8_t expected_positive_match_secret_for_fake_user_id[] = {
+	0x0d, 0xf5, 0xac, 0x7c, 0xad, 0x37, 0x0a, 0x66, 0x2f, 0x71, 0xf6,
+	0xc6, 0xca, 0x8a, 0x41, 0x69, 0x8a, 0xd3, 0xcf, 0x0b, 0xc4, 0x5a,
+	0x5f, 0x4d, 0x54, 0xeb, 0x7b, 0xad, 0x5d, 0x1b, 0xbe, 0x30,
+};
+
+test_static int test_get_ikm_failure_seed_not_set(void)
+{
+	uint8_t ikm;
+
+	TEST_ASSERT(fp_tpm_seed_is_set() == 0);
+	TEST_ASSERT(get_ikm(&ikm) == EC_ERROR_ACCESS_DENIED);
+	return EC_SUCCESS;
+}
+
+test_static int test_get_ikm_failure_cannot_get_rollback_secret(void)
+{
+	uint8_t ikm[CONFIG_ROLLBACK_SECRET_SIZE + FP_CONTEXT_TPM_BYTES];
+
+	/* Given that the tmp seed has been set. */
+	TEST_ASSERT(fp_tpm_seed_is_set());
+
+	/* GIVEN that reading the rollback secret will fail. */
+	mock_ctrl_rollback.get_secret_fail = true;
+
+	/* THEN get_ikm should fail. */
+	TEST_ASSERT(get_ikm(ikm) == EC_ERROR_HW_INTERNAL);
+
+	/*
+	 * Enable get_rollback_secret to succeed before returning from this
+	 * test function.
+	 */
+	mock_ctrl_rollback.get_secret_fail = false;
+
+	return EC_SUCCESS;
+}
+
+test_static int test_get_ikm_success(void)
+{
+	/*
+	 * Expected ikm is the concatenation of the rollback secret and the
+	 * seed from the TPM.
+	 */
+	uint8_t ikm[CONFIG_ROLLBACK_SECRET_SIZE + FP_CONTEXT_TPM_BYTES];
+	static const uint8_t expected_ikm[] = {
+		0xcf, 0xe3, 0x23, 0x76, 0x35, 0x04, 0xc2, 0x0f, 0x0d, 0xb6,
+		0x02, 0xa9, 0x68, 0xba, 0x2a, 0x61, 0x86, 0x2a, 0x85, 0xd1,
+		0xca, 0x09, 0x54, 0x8a, 0x6b, 0xe2, 0xe3, 0x38, 0xde, 0x5d,
+		0x59, 0x14, 0xd9, 0x71, 0xaf, 0xc4, 0xcd, 0x36, 0xe3, 0x60,
+		0xf8, 0x5a, 0xa0, 0xa6, 0x2c, 0xb3, 0xf5, 0xe2, 0xeb, 0xb9,
+		0xd8, 0x2f, 0xb5, 0x78, 0x5c, 0x79, 0x82, 0xce, 0x06, 0x3f,
+		0xcc, 0x23, 0xb9, 0xe7
+	};
+
+	/* GIVEN that the TPM seed has been set. */
+	TEST_ASSERT(fp_tpm_seed_is_set());
+
+	/* GIVEN that reading the rollback secret will succeed. */
+	mock_ctrl_rollback.get_secret_fail = false;
+
+	/* THEN get_ikm will succeed. */
+	TEST_ASSERT(get_ikm(ikm) == EC_SUCCESS);
+	TEST_ASSERT_ARRAY_EQ(ikm, expected_ikm,
+			     CONFIG_ROLLBACK_SECRET_SIZE +
+				     FP_CONTEXT_TPM_BYTES);
+
+	return EC_SUCCESS;
+}
+
+static int test_hkdf_expand_raw(const uint8_t *prk, size_t prk_size,
+				const uint8_t *info, size_t info_size,
+				const uint8_t *expected_okm, size_t okm_size)
+{
+	uint8_t actual_okm[okm_size];
+
+	TEST_ASSERT(hkdf_expand(actual_okm, okm_size, prk, prk_size, info,
+				info_size) == EC_SUCCESS);
+	TEST_ASSERT_ARRAY_EQ(expected_okm, actual_okm, okm_size);
+	return EC_SUCCESS;
+}
+
+test_static int test_hkdf_expand(void)
+{
+	/* Test vectors in https://tools.ietf.org/html/rfc5869#appendix-A */
+	static const uint8_t prk1[] = {
+		0x07, 0x77, 0x09, 0x36, 0x2c, 0x2e, 0x32, 0xdf,
+		0x0d, 0xdc, 0x3f, 0x0d, 0xc4, 0x7b, 0xba, 0x63,
+		0x90, 0xb6, 0xc7, 0x3b, 0xb5, 0x0f, 0x9c, 0x31,
+		0x22, 0xec, 0x84, 0x4a, 0xd7, 0xc2, 0xb3, 0xe5,
+	};
+	static const uint8_t info1[] = {
+		0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9,
+	};
+	static const uint8_t expected_okm1[] = {
+		0x3c, 0xb2, 0x5f, 0x25, 0xfa, 0xac, 0xd5, 0x7a, 0x90,
+		0x43, 0x4f, 0x64, 0xd0, 0x36, 0x2f, 0x2a, 0x2d, 0x2d,
+		0x0a, 0x90, 0xcf, 0x1a, 0x5a, 0x4c, 0x5d, 0xb0, 0x2d,
+		0x56, 0xec, 0xc4, 0xc5, 0xbf, 0x34, 0x00, 0x72, 0x08,
+		0xd5, 0xb8, 0x87, 0x18, 0x58, 0x65,
+	};
+	static const uint8_t prk2[] = {
+		0x06, 0xa6, 0xb8, 0x8c, 0x58, 0x53, 0x36, 0x1a,
+		0x06, 0x10, 0x4c, 0x9c, 0xeb, 0x35, 0xb4, 0x5c,
+		0xef, 0x76, 0x00, 0x14, 0x90, 0x46, 0x71, 0x01,
+		0x4a, 0x19, 0x3f, 0x40, 0xc1, 0x5f, 0xc2, 0x44,
+	};
+	static const uint8_t info2[] = {
+		0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, 0xb8, 0xb9,
+		0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, 0xc0, 0xc1, 0xc2, 0xc3,
+		0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd,
+		0xce, 0xcf, 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
+		0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, 0xe0, 0xe1,
+		0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xea, 0xeb,
+		0xec, 0xed, 0xee, 0xef, 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5,
+		0xf6, 0xf7, 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff,
+	};
+	static const uint8_t expected_okm2[] = {
+		0xb1, 0x1e, 0x39, 0x8d, 0xc8, 0x03, 0x27, 0xa1, 0xc8, 0xe7,
+		0xf7, 0x8c, 0x59, 0x6a, 0x49, 0x34, 0x4f, 0x01, 0x2e, 0xda,
+		0x2d, 0x4e, 0xfa, 0xd8, 0xa0, 0x50, 0xcc, 0x4c, 0x19, 0xaf,
+		0xa9, 0x7c, 0x59, 0x04, 0x5a, 0x99, 0xca, 0xc7, 0x82, 0x72,
+		0x71, 0xcb, 0x41, 0xc6, 0x5e, 0x59, 0x0e, 0x09, 0xda, 0x32,
+		0x75, 0x60, 0x0c, 0x2f, 0x09, 0xb8, 0x36, 0x77, 0x93, 0xa9,
+		0xac, 0xa3, 0xdb, 0x71, 0xcc, 0x30, 0xc5, 0x81, 0x79, 0xec,
+		0x3e, 0x87, 0xc1, 0x4c, 0x01, 0xd5, 0xc1, 0xf3, 0x43, 0x4f,
+		0x1d, 0x87,
+	};
+	static const uint8_t prk3[] = {
+		0x19, 0xef, 0x24, 0xa3, 0x2c, 0x71, 0x7b, 0x16,
+		0x7f, 0x33, 0xa9, 0x1d, 0x6f, 0x64, 0x8b, 0xdf,
+		0x96, 0x59, 0x67, 0x76, 0xaf, 0xdb, 0x63, 0x77,
+		0xac, 0x43, 0x4c, 0x1c, 0x29, 0x3c, 0xcb, 0x04,
+	};
+	static const uint8_t expected_okm3[] = {
+		0x8d, 0xa4, 0xe7, 0x75, 0xa5, 0x63, 0xc1, 0x8f, 0x71,
+		0x5f, 0x80, 0x2a, 0x06, 0x3c, 0x5a, 0x31, 0xb8, 0xa1,
+		0x1f, 0x5c, 0x5e, 0xe1, 0x87, 0x9e, 0xc3, 0x45, 0x4e,
+		0x5f, 0x3c, 0x73, 0x8d, 0x2d, 0x9d, 0x20, 0x13, 0x95,
+		0xfa, 0xa4, 0xb6, 0x1a, 0x96, 0xc8,
+	};
+	static uint8_t unused_output[SHA256_DIGEST_SIZE] = { 0 };
+
+	TEST_ASSERT(test_hkdf_expand_raw(prk1, sizeof(prk1), info1,
+					 sizeof(info1), expected_okm1,
+					 sizeof(expected_okm1)) == EC_SUCCESS);
+	TEST_ASSERT(test_hkdf_expand_raw(prk2, sizeof(prk2), info2,
+					 sizeof(info2), expected_okm2,
+					 sizeof(expected_okm2)) == EC_SUCCESS);
+	TEST_ASSERT(test_hkdf_expand_raw(prk3, sizeof(prk3), NULL, 0,
+					 expected_okm3,
+					 sizeof(expected_okm3)) == EC_SUCCESS);
+
+	TEST_ASSERT(hkdf_expand(NULL, sizeof(unused_output), prk1, sizeof(prk1),
+				info1, sizeof(info1)) == EC_ERROR_INVAL);
+	TEST_ASSERT(hkdf_expand(unused_output, sizeof(unused_output), NULL,
+				sizeof(prk1), info1,
+				sizeof(info1)) == EC_ERROR_INVAL);
+	TEST_ASSERT(hkdf_expand(unused_output, sizeof(unused_output), prk1,
+				sizeof(prk1), NULL,
+				sizeof(info1)) == EC_ERROR_INVAL);
+	/* Info size too long. */
+	TEST_ASSERT(hkdf_expand(unused_output, sizeof(unused_output), prk1,
+				sizeof(prk1), info1, 1024) == EC_ERROR_INVAL);
+	/* OKM size too big. */
+	TEST_ASSERT(hkdf_expand(unused_output, 256 * SHA256_DIGEST_SIZE, prk1,
+				sizeof(prk1), info1,
+				sizeof(info1)) == EC_ERROR_INVAL);
+	return EC_SUCCESS;
+}
+
+test_static int test_derive_encryption_key_failure_seed_not_set(void)
+{
+	static uint8_t unused_key[SBP_ENC_KEY_LEN];
+	static const uint8_t unused_salt[FP_CONTEXT_ENCRYPTION_SALT_BYTES] = {
+		0
+	};
+
+	/* GIVEN that the TPM seed is not set. */
+	if (fp_tpm_seed_is_set()) {
+		ccprintf("%s:%s(): this test should be executed before setting"
+			 " TPM seed.\n",
+			 __FILE__, __func__);
+		return -1;
+	}
+
+	/* THEN derivation will fail. */
+	TEST_ASSERT(derive_encryption_key(unused_key, unused_salt) ==
+		    EC_ERROR_ACCESS_DENIED);
+
+	return EC_SUCCESS;
+}
+
+static int test_derive_encryption_key_raw(const uint32_t *user_id_,
+					  const uint8_t *salt,
+					  const uint8_t *expected_key)
+{
+	uint8_t key[SBP_ENC_KEY_LEN];
+	enum ec_error_list rv;
+
+	/*
+	 * |user_id| is a global variable used as "info" in HKDF expand
+	 * in derive_encryption_key().
+	 */
+	memcpy(user_id, user_id_, sizeof(user_id));
+	rv = derive_encryption_key(key, salt);
+
+	TEST_ASSERT(rv == EC_SUCCESS);
+	TEST_ASSERT_ARRAY_EQ(key, expected_key, sizeof(key));
+
+	memset(user_id, 0, sizeof(user_id));
+
+	return EC_SUCCESS;
+}
+
+test_static int test_derive_encryption_key(void)
+{
+	/*
+	 * These vectors are obtained by choosing the salt and the user_id
+	 * (used as "info" in HKDF), and running boringSSL's HKDF
+	 * (https://boringssl.googlesource.com/boringssl/+/c0b4c72b6d4c6f4828a373ec454bd646390017d4/crypto/hkdf/)
+	 * locally to get the output key. The IKM used in the run is the
+	 * concatenation of |fake_rollback_secret| and |fake_tpm_seed|.
+	 */
+	static const uint32_t user_id1[] = {
+		0x608b1b0b, 0xe10d3d24, 0x0bbbe4e6, 0x807b36d9,
+		0x2a1f8abc, 0xea38104a, 0x562d9431, 0x64d721c5,
+	};
+
+	static const uint8_t salt1[] = {
+		0xd0, 0x88, 0x34, 0x15, 0xc0, 0xfa, 0x8e, 0x22,
+		0x9f, 0xb4, 0xd5, 0xa9, 0xee, 0xd3, 0x15, 0x19,
+	};
+
+	static const uint8_t key1[] = {
+		0xdb, 0x49, 0x6e, 0x1b, 0x67, 0x8a, 0x35, 0xc6,
+		0xa0, 0x9d, 0xb6, 0xa0, 0x13, 0xf4, 0x21, 0xb3,
+	};
+
+	static const uint32_t user_id2[] = {
+		0x2546a2ca, 0xf1891f7a, 0x44aad8b8, 0x0d6aac74,
+		0x6a4ab846, 0x9c279796, 0x5a72eae1, 0x8276d2a3,
+	};
+
+	static const uint8_t salt2[] = {
+		0x72, 0x6b, 0xc1, 0xe4, 0x64, 0xd4, 0xff, 0xa2,
+		0x5a, 0xac, 0x5b, 0x0b, 0x06, 0x67, 0xe1, 0x53,
+	};
+
+	static const uint8_t key2[] = {
+		0x8d, 0x53, 0xaf, 0x4c, 0x96, 0xa2, 0xee, 0x46,
+		0x9c, 0xe2, 0xe2, 0x6f, 0xe6, 0x66, 0x3d, 0x3a,
+	};
+
+	/*
+	 * GIVEN that the TPM seed is set, and reading the rollback secret will
+	 * succeed.
+	 */
+	TEST_ASSERT(fp_tpm_seed_is_set() &&
+		    !mock_ctrl_rollback.get_secret_fail);
+
+	/* THEN the derivation will succeed. */
+	TEST_ASSERT(test_derive_encryption_key_raw(user_id1, salt1, key1) ==
+		    EC_SUCCESS);
+
+	TEST_ASSERT(test_derive_encryption_key_raw(user_id2, salt2, key2) ==
+		    EC_SUCCESS);
+
+	return EC_SUCCESS;
+}
+
+test_static int test_derive_encryption_key_failure_rollback_fail(void)
+{
+	static uint8_t unused_key[SBP_ENC_KEY_LEN];
+	static const uint8_t unused_salt[FP_CONTEXT_ENCRYPTION_SALT_BYTES] = {
+		0
+	};
+
+	/* GIVEN that reading the rollback secret will fail. */
+	mock_ctrl_rollback.get_secret_fail = true;
+	/* THEN the derivation will fail. */
+	TEST_ASSERT(derive_encryption_key(unused_key, unused_salt) ==
+		    EC_ERROR_HW_INTERNAL);
+
+	/* GIVEN that reading the rollback secret will succeed. */
+	mock_ctrl_rollback.get_secret_fail = false;
+	/* GIVEN that the TPM seed has been set. */
+	TEST_ASSERT(fp_tpm_seed_is_set());
+	/* THEN the derivation will succeed. */
+	TEST_ASSERT(derive_encryption_key(unused_key, unused_salt) ==
+		    EC_SUCCESS);
+
+	return EC_SUCCESS;
+}
+
+test_static int test_derive_positive_match_secret_fail_seed_not_set(void)
+{
+	static uint8_t output[FP_POSITIVE_MATCH_SECRET_BYTES];
+
+	/* GIVEN that seed is not set. */
+	TEST_ASSERT(!fp_tpm_seed_is_set());
+	/* THEN EVEN IF the encryption salt is not trivial. */
+	TEST_ASSERT(!bytes_are_trivial(fake_positive_match_salt,
+				       sizeof(fake_positive_match_salt)));
+
+	/* Deriving positive match secret will fail. */
+	TEST_ASSERT(derive_positive_match_secret(output,
+						 fake_positive_match_salt) ==
+		    EC_ERROR_ACCESS_DENIED);
+
+	return EC_SUCCESS;
+}
+
+test_static int test_derive_new_pos_match_secret(void)
+{
+	static uint8_t output[FP_POSITIVE_MATCH_SECRET_BYTES];
+
+	/* First, for empty user_id. */
+	memset(user_id, 0, sizeof(user_id));
+
+	/* GIVEN that the encryption salt is not trivial. */
+	TEST_ASSERT(!bytes_are_trivial(fake_positive_match_salt,
+				       sizeof(fake_positive_match_salt)));
+	/*
+	 * GIVEN that the TPM seed is set, and reading the rollback secret will
+	 * succeed.
+	 */
+	TEST_ASSERT(fp_tpm_seed_is_set() &&
+		    !mock_ctrl_rollback.get_secret_fail);
+
+	/* GIVEN that the salt is not trivial. */
+	TEST_ASSERT(!bytes_are_trivial(fake_positive_match_salt,
+				       sizeof(fake_positive_match_salt)));
+
+	/* THEN the derivation will succeed. */
+	TEST_ASSERT(derive_positive_match_secret(
+			    output, fake_positive_match_salt) == EC_SUCCESS);
+	TEST_ASSERT_ARRAY_EQ(
+		output, expected_positive_match_secret_for_empty_user_id,
+		sizeof(expected_positive_match_secret_for_empty_user_id));
+
+	/* Now change the user_id to be non-trivial. */
+	memcpy(user_id, fake_user_id, sizeof(fake_user_id));
+	TEST_ASSERT(derive_positive_match_secret(
+			    output, fake_positive_match_salt) == EC_SUCCESS);
+	TEST_ASSERT_ARRAY_EQ(
+		output, expected_positive_match_secret_for_fake_user_id,
+		sizeof(expected_positive_match_secret_for_fake_user_id));
+	memset(user_id, 0, sizeof(user_id));
+
+	return EC_SUCCESS;
+}
+
+test_static int test_derive_positive_match_secret_fail_rollback_fail(void)
+{
+	static uint8_t output[FP_POSITIVE_MATCH_SECRET_BYTES];
+
+	/* GIVEN that reading secret from anti-rollback block will fail. */
+	mock_ctrl_rollback.get_secret_fail = true;
+	/* THEN EVEN IF the encryption salt is not trivial. */
+	TEST_ASSERT(!bytes_are_trivial(fake_positive_match_salt,
+				       sizeof(fake_positive_match_salt)));
+
+	/* Deriving positive match secret will fail. */
+	TEST_ASSERT(derive_positive_match_secret(output,
+						 fake_positive_match_salt) ==
+		    EC_ERROR_HW_INTERNAL);
+	mock_ctrl_rollback.get_secret_fail = false;
+
+	return EC_SUCCESS;
+}
+
+test_static int test_derive_positive_match_secret_fail_salt_trivial(void)
+{
+	static uint8_t output[FP_POSITIVE_MATCH_SECRET_BYTES];
+
+	/* GIVEN that the salt is trivial. */
+	static const uint8_t salt[FP_CONTEXT_ENCRYPTION_SALT_BYTES] = { 0 };
+
+	/* THEN deriving positive match secret will fail. */
+	TEST_ASSERT(derive_positive_match_secret(output, salt) ==
+		    EC_ERROR_INVAL);
+	return EC_SUCCESS;
+}
+
+test_static int test_derive_positive_match_secret_fail_trivial_key_0x00(void)
+{
+	static uint8_t output[FP_POSITIVE_MATCH_SECRET_BYTES];
+
+	/* GIVEN that the user ID is set to a known value. */
+	memcpy(user_id, fake_user_id, sizeof(fake_user_id));
+
+	/*
+	 * GIVEN that the TPM seed is set, and reading the rollback secret will
+	 * succeed.
+	 */
+	TEST_ASSERT(fp_tpm_seed_is_set() &&
+		    !mock_ctrl_rollback.get_secret_fail);
+
+	/* GIVEN that the salt is not trivial. */
+	TEST_ASSERT(!bytes_are_trivial(fake_positive_match_salt,
+				       sizeof(fake_positive_match_salt)));
+
+	/* GIVEN that the sha256 output is trivial (0x00) */
+	mock_ctrl_fpsensor_crypto.output_type =
+		MOCK_CTRL_FPSENSOR_CRYPTO_SHA256_TYPE_ZEROS;
+
+	/* THEN the derivation will fail with EC_ERROR_HW_INTERNAL. */
+	TEST_ASSERT(derive_positive_match_secret(output,
+						 fake_positive_match_salt) ==
+		    EC_ERROR_HW_INTERNAL);
+
+	/* Now verify success is possible after reverting */
+
+	/* GIVEN that the sha256 output is non-trivial */
+	mock_ctrl_fpsensor_crypto.output_type =
+		MOCK_CTRL_FPSENSOR_CRYPTO_SHA256_TYPE_REAL;
+
+	/* THEN the derivation will succeed */
+	TEST_ASSERT(derive_positive_match_secret(
+			    output, fake_positive_match_salt) == EC_SUCCESS);
+
+	/* Clean up any mock changes */
+	mock_ctrl_fpsensor_crypto = MOCK_CTRL_DEFAULT_FPSENSOR_CRYPTO;
+
+	return EC_SUCCESS;
+}
+
+test_static int test_derive_positive_match_secret_fail_trivial_key_0xff(void)
+{
+	static uint8_t output[FP_POSITIVE_MATCH_SECRET_BYTES];
+
+	/* GIVEN that the user ID is set to a known value. */
+	memcpy(user_id, fake_user_id, sizeof(fake_user_id));
+
+	/*
+	 * GIVEN that the TPM seed is set, and reading the rollback secret will
+	 * succeed.
+	 */
+	TEST_ASSERT(fp_tpm_seed_is_set() &&
+		    !mock_ctrl_rollback.get_secret_fail);
+
+	/* GIVEN that the salt is not trivial. */
+	TEST_ASSERT(!bytes_are_trivial(fake_positive_match_salt,
+				       sizeof(fake_positive_match_salt)));
+
+	/* GIVEN that the sha256 output is trivial (0xFF) */
+	mock_ctrl_fpsensor_crypto.output_type =
+		MOCK_CTRL_FPSENSOR_CRYPTO_SHA256_TYPE_FF;
+
+	/* THEN the derivation will fail with EC_ERROR_HW_INTERNAL. */
+	TEST_ASSERT(derive_positive_match_secret(output,
+						 fake_positive_match_salt) ==
+		    EC_ERROR_HW_INTERNAL);
+
+	/* Now verify success is possible after reverting */
+
+	/* GIVEN that the sha256 output is non-trivial */
+	mock_ctrl_fpsensor_crypto.output_type =
+		MOCK_CTRL_FPSENSOR_CRYPTO_SHA256_TYPE_REAL;
+
+	/* THEN the derivation will succeed */
+	TEST_ASSERT(derive_positive_match_secret(
+			    output, fake_positive_match_salt) == EC_SUCCESS);
+
+	/* Clean up any mock changes */
+	mock_ctrl_fpsensor_crypto = MOCK_CTRL_DEFAULT_FPSENSOR_CRYPTO;
+
+	return EC_SUCCESS;
+}
+
+static int test_enable_positive_match_secret_once(
+	struct positive_match_secret_state *dumb_state)
+{
+	const int8_t kIndexToEnable = 0;
+	timestamp_t now = get_time();
+
+	TEST_ASSERT(fp_enable_positive_match_secret(kIndexToEnable,
+						    dumb_state) == EC_SUCCESS);
+	TEST_ASSERT(dumb_state->template_matched == kIndexToEnable);
+	TEST_ASSERT(dumb_state->readable);
+	TEST_ASSERT(dumb_state->deadline.val == now.val + (5 * SECOND));
+
+	return EC_SUCCESS;
+}
+
+test_static int test_enable_positive_match_secret(void)
+{
+	struct positive_match_secret_state
+		dumb_state = { .template_matched = FP_NO_SUCH_TEMPLATE,
+			       .readable = false,
+			       .deadline = {
+				       .val = 0,
+			       } };
+
+	TEST_ASSERT(test_enable_positive_match_secret_once(&dumb_state) ==
+		    EC_SUCCESS);
+
+	/* Trying to enable again before reading secret should fail. */
+	TEST_ASSERT(fp_enable_positive_match_secret(0, &dumb_state) ==
+		    EC_ERROR_UNKNOWN);
+	TEST_ASSERT(dumb_state.template_matched == FP_NO_SUCH_TEMPLATE);
+	TEST_ASSERT(!dumb_state.readable);
+	TEST_ASSERT(dumb_state.deadline.val == 0);
+
+	return EC_SUCCESS;
+}
+
+test_static int test_disable_positive_match_secret(void)
+{
+	struct positive_match_secret_state
+		dumb_state = { .template_matched = FP_NO_SUCH_TEMPLATE,
+			       .readable = false,
+			       .deadline = {
+				       .val = 0,
+			       } };
+
+	TEST_ASSERT(test_enable_positive_match_secret_once(&dumb_state) ==
+		    EC_SUCCESS);
+
+	fp_disable_positive_match_secret(&dumb_state);
+	TEST_ASSERT(dumb_state.template_matched == FP_NO_SUCH_TEMPLATE);
+	TEST_ASSERT(!dumb_state.readable);
+	TEST_ASSERT(dumb_state.deadline.val == 0);
+
+	return EC_SUCCESS;
+}
+
+test_static int test_command_read_match_secret(void)
+{
+	enum ec_status rv;
+	struct ec_params_fp_read_match_secret params;
+	struct ec_response_fp_read_match_secret resp;
+	timestamp_t now = get_time();
+
+	/* For empty user_id. */
+	memset(user_id, 0, sizeof(user_id));
+
+	/* Invalid finger index should be rejected. */
+	params.fgr = FP_NO_SUCH_TEMPLATE;
+	rv = test_send_host_command(EC_CMD_FP_READ_MATCH_SECRET, 0, &params,
+				    sizeof(params), NULL, 0);
+	TEST_ASSERT(rv == EC_RES_INVALID_PARAM);
+	params.fgr = FP_MAX_FINGER_COUNT;
+	rv = test_send_host_command(EC_CMD_FP_READ_MATCH_SECRET, 0, &params,
+				    sizeof(params), NULL, 0);
+	TEST_ASSERT(rv == EC_RES_INVALID_PARAM);
+
+	memset(&resp, 0, sizeof(resp));
+	/* GIVEN that finger index is valid. */
+	params.fgr = 0;
+
+	/* GIVEN that positive match secret is enabled. */
+	fp_enable_positive_match_secret(params.fgr,
+					&positive_match_secret_state);
+
+	/* GIVEN that salt is non-trivial. */
+	memcpy(fp_positive_match_salt[0], fake_positive_match_salt,
+	       sizeof(fp_positive_match_salt[0]));
+	/* THEN reading positive match secret should succeed. */
+	rv = test_send_host_command(EC_CMD_FP_READ_MATCH_SECRET, 0, &params,
+				    sizeof(params), &resp, sizeof(resp));
+	if (rv != EC_RES_SUCCESS) {
+		ccprintf("%s:%s(): rv = %d\n", __FILE__, __func__, rv);
+		return -1;
+	}
+	/* AND the readable bit should be cleared after the read. */
+	TEST_ASSERT(positive_match_secret_state.readable == false);
+
+	TEST_ASSERT_ARRAY_EQ(
+		resp.positive_match_secret,
+		expected_positive_match_secret_for_empty_user_id,
+		sizeof(expected_positive_match_secret_for_empty_user_id));
+
+	/*
+	 * Now try reading secret again.
+	 * EVEN IF the deadline has not passed.
+	 */
+	positive_match_secret_state.deadline.val = now.val + 1 * SECOND;
+	rv = test_send_host_command(EC_CMD_FP_READ_MATCH_SECRET, 0, &params,
+				    sizeof(params), NULL, 0);
+	/*
+	 * This time the command should fail because the
+	 * fp_pos_match_secret_readable bit is cleared when the secret was read
+	 * the first time.
+	 */
+	TEST_ASSERT(rv == EC_RES_ACCESS_DENIED);
+
+	return EC_SUCCESS;
+}
+
+test_static int test_command_read_match_secret_wrong_finger(void)
+{
+	enum ec_status rv;
+	struct ec_params_fp_read_match_secret params;
+
+	/* GIVEN that the finger is not the matched or enrolled finger. */
+	params.fgr = 0;
+	/*
+	 * GIVEN that positive match secret is enabled for a different
+	 * finger.
+	 */
+	fp_enable_positive_match_secret(params.fgr + 1,
+					&positive_match_secret_state);
+
+	/* Reading secret will fail. */
+	rv = test_send_host_command(EC_CMD_FP_READ_MATCH_SECRET, 0, &params,
+				    sizeof(params), NULL, 0);
+	TEST_ASSERT(rv == EC_RES_ACCESS_DENIED);
+	return EC_SUCCESS;
+}
+
+test_static int test_command_read_match_secret_timeout(void)
+{
+	enum ec_status rv;
+	struct ec_params_fp_read_match_secret params;
+
+	params.fgr = 0;
+	/* GIVEN that the read is too late. */
+	fp_enable_positive_match_secret(params.fgr,
+					&positive_match_secret_state);
+	set_time(positive_match_secret_state.deadline);
+
+	/* EVEN IF encryption salt is non-trivial. */
+	memcpy(fp_positive_match_salt[0], fake_positive_match_salt,
+	       sizeof(fp_positive_match_salt[0]));
+	/* Reading secret will fail. */
+	rv = test_send_host_command(EC_CMD_FP_READ_MATCH_SECRET, 0, &params,
+				    sizeof(params), NULL, 0);
+	TEST_ASSERT(rv == EC_RES_TIMEOUT);
+	return EC_SUCCESS;
+}
+
+test_static int test_command_read_match_secret_unreadable(void)
+{
+	enum ec_status rv;
+	struct ec_params_fp_read_match_secret params;
+
+	params.fgr = 0;
+	/* GIVEN that the readable bit is not set. */
+	fp_enable_positive_match_secret(params.fgr,
+					&positive_match_secret_state);
+	positive_match_secret_state.readable = false;
+
+	/* EVEN IF the finger is just matched. */
+	TEST_ASSERT(positive_match_secret_state.template_matched == params.fgr);
+
+	/* EVEN IF encryption salt is non-trivial. */
+	memcpy(fp_positive_match_salt[0], fake_positive_match_salt,
+	       sizeof(fp_positive_match_salt[0]));
+	/* Reading secret will fail. */
+	rv = test_send_host_command(EC_CMD_FP_READ_MATCH_SECRET, 0, &params,
+				    sizeof(params), NULL, 0);
+	TEST_ASSERT(rv == EC_RES_ACCESS_DENIED);
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
+{
+	RUN_TEST(test_hkdf_expand);
+	RUN_TEST(test_derive_encryption_key_failure_seed_not_set);
+	RUN_TEST(test_derive_positive_match_secret_fail_seed_not_set);
+	RUN_TEST(test_get_ikm_failure_seed_not_set);
+	/*
+	 * Set the TPM seed here because it can only be set once and cannot be
+	 * cleared.
+	 */
+	ASSERT(fpsensor_state_mock_set_tpm_seed(default_fake_tpm_seed) ==
+	       EC_SUCCESS);
+
+	/* The following test requires TPM seed to be already set. */
+	RUN_TEST(test_get_ikm_failure_cannot_get_rollback_secret);
+	RUN_TEST(test_get_ikm_success);
+	RUN_TEST(test_derive_encryption_key);
+	RUN_TEST(test_derive_encryption_key_failure_rollback_fail);
+	RUN_TEST(test_derive_new_pos_match_secret);
+	RUN_TEST(test_derive_positive_match_secret_fail_rollback_fail);
+	RUN_TEST(test_derive_positive_match_secret_fail_salt_trivial);
+	RUN_TEST(test_derive_positive_match_secret_fail_trivial_key_0x00);
+	RUN_TEST(test_derive_positive_match_secret_fail_trivial_key_0xff);
+	RUN_TEST(test_enable_positive_match_secret);
+	RUN_TEST(test_disable_positive_match_secret);
+	RUN_TEST(test_command_read_match_secret);
+	RUN_TEST(test_command_read_match_secret_wrong_finger);
+	RUN_TEST(test_command_read_match_secret_timeout);
+	RUN_TEST(test_command_read_match_secret_unreadable);
+	test_print_result();
+}
diff --git a/test/fpsensor_hw.cc b/test/fpsensor_hw.cc
new file mode 100644
index 0000000000..559af6f939
--- /dev/null
+++ b/test/fpsensor_hw.cc
@@ -0,0 +1,39 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "config.h"
+#include "fpc_private.h"
+#include "test_util.h"
+
+#ifdef SECTION_IS_RW
+#include "fpc/fpc_sensor.h"
+static const uint32_t fp_sensor_hwid = FP_SENSOR_HWID_FPC;
+#else
+static const uint32_t fp_sensor_hwid = UINT32_MAX;
+#endif
+
+/* Hardware-dependent smoke test that makes a SPI transaction with the
+ * fingerprint sensor.
+ */
+test_static int test_fp_check_hwid(void)
+{
+	uint16_t id = 0;
+
+	if (IS_ENABLED(SECTION_IS_RW)) {
+		TEST_EQ(fpc_get_hwid(&id), EC_SUCCESS, "%d");
+		/* The lower 4-bits of the sensor hardware id are a
+		 * manufacturing ID that is ok to vary.
+		 */
+		TEST_EQ(fp_sensor_hwid, id >> 4, "%d");
+	};
+	return EC_SUCCESS;
+}
+
+extern "C" void run_test(int argc, const char **argv)
+{
+	RUN_TEST(test_fp_check_hwid);
+	test_print_result();
+}
diff --git a/test/fpsensor_hw.tasklist b/test/fpsensor_hw.tasklist
new file mode 100644
index 0000000000..35fa6f24bd
--- /dev/null
+++ b/test/fpsensor_hw.tasklist
@@ -0,0 +1,9 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST
diff --git a/test/fpsensor_state.c b/test/fpsensor_state.c
deleted file mode 100644
index 3822fe49ab..0000000000
--- a/test/fpsensor_state.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <stdbool.h>
-
-#include "common.h"
-#include "ec_commands.h"
-#include "fpsensor_state.h"
-#include "mock/fpsensor_state_mock.h"
-#include "test_util.h"
-#include "util.h"
-
-test_static int test_fp_enc_status_valid_flags(void)
-{
-	/* Putting expected value here because test_static should take void */
-	const uint32_t expected = FP_ENC_STATUS_SEED_SET;
-	int rv;
-	struct ec_response_fp_encryption_status resp = { 0 };
-
-	rv = test_send_host_command(EC_CMD_FP_ENC_STATUS, 0, NULL, 0, &resp,
-				    sizeof(resp));
-	if (rv != EC_RES_SUCCESS) {
-		ccprintf("%s:%s(): failed to get encryption status. rv = %d\n",
-			 __FILE__, __func__, rv);
-		return -1;
-	}
-
-	if (resp.valid_flags != expected) {
-		ccprintf("%s:%s(): expected valid flags 0x%08x, got 0x%08x\n",
-			 __FILE__, __func__, expected, resp.valid_flags);
-		return -1;
-	}
-
-	return EC_RES_SUCCESS;
-}
-
-static int
-check_seed_set_result(const int rv, const uint32_t expected,
-		      const struct ec_response_fp_encryption_status *resp)
-{
-	const uint32_t actual = resp->status & FP_ENC_STATUS_SEED_SET;
-
-	if (rv != EC_RES_SUCCESS || expected != actual) {
-		ccprintf("%s:%s(): rv = %d, seed is set: %d\n", __FILE__,
-			 __func__, rv, actual);
-		return -1;
-	}
-
-	return EC_SUCCESS;
-}
-
-test_static int test_fp_tpm_seed_not_set(void)
-{
-	int rv;
-	struct ec_response_fp_encryption_status resp = { 0 };
-
-	/* Initially the seed should not have been set. */
-	rv = test_send_host_command(EC_CMD_FP_ENC_STATUS, 0, NULL, 0, &resp,
-				    sizeof(resp));
-
-	return check_seed_set_result(rv, 0, &resp);
-}
-
-test_static int test_set_fp_tpm_seed(void)
-{
-	int rv;
-	struct ec_params_fp_seed params;
-	struct ec_response_fp_encryption_status resp = { 0 };
-
-	params.struct_version = FP_TEMPLATE_FORMAT_VERSION;
-	memcpy(params.seed, default_fake_tpm_seed,
-	       sizeof(default_fake_tpm_seed));
-
-	rv = test_send_host_command(EC_CMD_FP_SEED, 0, &params, sizeof(params),
-				    NULL, 0);
-	if (rv != EC_RES_SUCCESS) {
-		ccprintf("%s:%s(): rv = %d, set seed failed\n", __FILE__,
-			 __func__, rv);
-		return -1;
-	}
-
-	/* Now seed should have been set. */
-	rv = test_send_host_command(EC_CMD_FP_ENC_STATUS, 0, NULL, 0, &resp,
-				    sizeof(resp));
-
-	return check_seed_set_result(rv, FP_ENC_STATUS_SEED_SET, &resp);
-}
-
-test_static int test_set_fp_tpm_seed_again(void)
-{
-	int rv;
-	struct ec_params_fp_seed params;
-	struct ec_response_fp_encryption_status resp = { 0 };
-
-	TEST_ASSERT(fp_tpm_seed_is_set());
-
-	params.struct_version = FP_TEMPLATE_FORMAT_VERSION;
-	memcpy(params.seed, default_fake_tpm_seed,
-	       sizeof(default_fake_tpm_seed));
-
-	rv = test_send_host_command(EC_CMD_FP_SEED, 0, &params, sizeof(params),
-				    NULL, 0);
-	if (rv != EC_RES_ACCESS_DENIED) {
-		ccprintf("%s:%s(): rv = %d, setting seed the second time "
-			 "should result in EC_RES_ACCESS_DENIED but did not.\n",
-			 __FILE__, __func__, rv);
-		return -1;
-	}
-
-	/* Now seed should still be set. */
-	rv = test_send_host_command(EC_CMD_FP_ENC_STATUS, 0, NULL, 0, &resp,
-				    sizeof(resp));
-
-	return check_seed_set_result(rv, FP_ENC_STATUS_SEED_SET, &resp);
-}
-
-test_static int test_fp_set_sensor_mode(void)
-{
-	uint32_t requested_mode = 0;
-	uint32_t output_mode = 0;
-
-	/* Validate initial conditions */
-	TEST_ASSERT(FP_MAX_FINGER_COUNT == 5);
-	TEST_ASSERT(templ_valid == 0);
-	TEST_ASSERT(sensor_mode == 0);
-
-	/* GIVEN missing output parameter, THEN get error */
-	TEST_ASSERT(fp_set_sensor_mode(0, NULL) == EC_RES_INVALID_PARAM);
-	/* THEN sensor_mode is unchanged */
-	TEST_ASSERT(sensor_mode == 0);
-
-	/* GIVEN requested mode includes FP_MODE_DONT_CHANGE, THEN succeed */
-	TEST_ASSERT(sensor_mode == 0);
-	TEST_ASSERT(output_mode == 0);
-	requested_mode = FP_MODE_DONT_CHANGE;
-	TEST_ASSERT(fp_set_sensor_mode(requested_mode, &output_mode) ==
-		    EC_RES_SUCCESS);
-	/* THEN sensor_mode is unchanged */
-	TEST_ASSERT(sensor_mode == 0);
-	/* THEN output_mode matches sensor_mode */
-	TEST_ASSERT(output_mode == sensor_mode);
-
-	/* GIVEN request to change to valid sensor mode */
-	TEST_ASSERT(sensor_mode == 0);
-	requested_mode = FP_MODE_ENROLL_SESSION;
-	/* THEN succeed */
-	TEST_ASSERT(fp_set_sensor_mode(requested_mode, &output_mode) ==
-		    EC_RES_SUCCESS);
-	/* THEN requested mode is returned */
-	TEST_ASSERT(requested_mode == output_mode);
-	/* THEN sensor_mode is updated */
-	TEST_ASSERT(sensor_mode == requested_mode);
-
-	/* GIVEN max number of fingers already enrolled */
-	sensor_mode = 0;
-	output_mode = 0xdeadbeef;
-	templ_valid = FP_MAX_FINGER_COUNT;
-	requested_mode = FP_MODE_ENROLL_SESSION;
-	/* THEN additional enroll attempt will fail */
-	TEST_ASSERT(fp_set_sensor_mode(requested_mode, &output_mode) ==
-		    EC_RES_INVALID_PARAM);
-	/* THEN output parameters is unchanged */
-	TEST_ASSERT(output_mode = 0xdeadbeef);
-	/* THEN sensor_mode is unchanged */
-	TEST_ASSERT(sensor_mode == 0);
-
-	return EC_SUCCESS;
-}
-
-test_static int test_fp_set_maintenance_mode(void)
-{
-	uint32_t output_mode = 0;
-
-	/* GIVEN request to change to maintenance sensor mode */
-	TEST_ASSERT(sensor_mode == 0);
-	/* THEN succeed */
-	TEST_ASSERT(fp_set_sensor_mode(FP_MODE_SENSOR_MAINTENANCE,
-				       &output_mode) == EC_RES_SUCCESS);
-	/* THEN requested mode is returned */
-	TEST_ASSERT(output_mode == FP_MODE_SENSOR_MAINTENANCE);
-	/* THEN sensor_mode is updated */
-	TEST_ASSERT(sensor_mode == FP_MODE_SENSOR_MAINTENANCE);
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	RUN_TEST(test_fp_enc_status_valid_flags);
-	RUN_TEST(test_fp_tpm_seed_not_set);
-	RUN_TEST(test_set_fp_tpm_seed);
-	RUN_TEST(test_set_fp_tpm_seed_again);
-	RUN_TEST(test_fp_set_sensor_mode);
-	RUN_TEST(test_fp_set_maintenance_mode);
-	test_print_result();
-}
diff --git a/test/fpsensor_state.cc b/test/fpsensor_state.cc
new file mode 100644
index 0000000000..f1b74446ea
--- /dev/null
+++ b/test/fpsensor_state.cc
@@ -0,0 +1,403 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "ec_commands.h"
+#include "fpsensor_state.h"
+#include "mock/fpsensor_state_mock.h"
+#include "test_util.h"
+#include "util.h"
+
+#include <stdbool.h>
+
+test_static enum ec_error_list test_fp_enc_status_valid_flags(void)
+{
+	/* Putting expected value here because test_static should take void */
+	const uint32_t expected = FP_ENC_STATUS_SEED_SET;
+	enum ec_status rv;
+	struct ec_response_fp_encryption_status resp = { 0 };
+
+	rv = test_send_host_command(EC_CMD_FP_ENC_STATUS, 0, NULL, 0, &resp,
+				    sizeof(resp));
+	if (rv != EC_RES_SUCCESS) {
+		ccprintf("%s:%s(): failed to get encryption status. rv = %d\n",
+			 __FILE__, __func__, rv);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	if (resp.valid_flags != expected) {
+		ccprintf("%s:%s(): expected valid flags 0x%08x, got 0x%08x\n",
+			 __FILE__, __func__, expected, resp.valid_flags);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+static enum ec_error_list
+check_seed_set_result(const enum ec_status rv, const uint32_t expected,
+		      const struct ec_response_fp_encryption_status *resp)
+{
+	const uint32_t actual = resp->status & FP_ENC_STATUS_SEED_SET;
+
+	if (rv != EC_RES_SUCCESS || expected != actual) {
+		ccprintf("%s:%s(): rv = %d, seed is set: %d\n", __FILE__,
+			 __func__, rv, actual);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+test_static enum ec_error_list test_fp_tpm_seed_not_set(void)
+{
+	enum ec_status rv;
+	struct ec_response_fp_encryption_status resp = { 0 };
+
+	/* Initially the seed should not have been set. */
+	rv = test_send_host_command(EC_CMD_FP_ENC_STATUS, 0, NULL, 0, &resp,
+				    sizeof(resp));
+
+	return check_seed_set_result(rv, 0, &resp);
+}
+
+test_static enum ec_error_list test_set_fp_tpm_seed(void)
+{
+	enum ec_status rv;
+	struct ec_params_fp_seed params;
+	struct ec_response_fp_encryption_status resp = { 0 };
+
+	params.struct_version = FP_TEMPLATE_FORMAT_VERSION;
+	memcpy(params.seed, default_fake_tpm_seed,
+	       sizeof(default_fake_tpm_seed));
+
+	rv = test_send_host_command(EC_CMD_FP_SEED, 0, &params, sizeof(params),
+				    NULL, 0);
+	if (rv != EC_RES_SUCCESS) {
+		ccprintf("%s:%s(): rv = %d, set seed failed\n", __FILE__,
+			 __func__, rv);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	/* Now seed should have been set. */
+	rv = test_send_host_command(EC_CMD_FP_ENC_STATUS, 0, NULL, 0, &resp,
+				    sizeof(resp));
+
+	return check_seed_set_result(rv, FP_ENC_STATUS_SEED_SET, &resp);
+}
+
+test_static enum ec_error_list test_set_fp_tpm_seed_again(void)
+{
+	enum ec_status rv;
+	struct ec_params_fp_seed params;
+	struct ec_response_fp_encryption_status resp = { 0 };
+
+	TEST_ASSERT(fp_tpm_seed_is_set());
+
+	params.struct_version = FP_TEMPLATE_FORMAT_VERSION;
+	memcpy(params.seed, default_fake_tpm_seed,
+	       sizeof(default_fake_tpm_seed));
+
+	rv = test_send_host_command(EC_CMD_FP_SEED, 0, &params, sizeof(params),
+				    NULL, 0);
+	if (rv != EC_RES_ACCESS_DENIED) {
+		ccprintf("%s:%s(): rv = %d, setting seed the second time "
+			 "should result in EC_RES_ACCESS_DENIED but did not.\n",
+			 __FILE__, __func__, rv);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	/* Now seed should still be set. */
+	rv = test_send_host_command(EC_CMD_FP_ENC_STATUS, 0, NULL, 0, &resp,
+				    sizeof(resp));
+
+	return check_seed_set_result(rv, FP_ENC_STATUS_SEED_SET, &resp);
+}
+
+test_static enum ec_error_list test_fp_set_sensor_mode(void)
+{
+	uint32_t requested_mode = 0;
+	uint32_t output_mode = 0;
+
+	/* Validate initial conditions */
+	TEST_ASSERT(FP_MAX_FINGER_COUNT == 5);
+	TEST_ASSERT(templ_valid == 0);
+	TEST_ASSERT(sensor_mode == 0);
+
+	/* GIVEN missing output parameter, THEN get error */
+	TEST_ASSERT(fp_set_sensor_mode(0, NULL) == EC_RES_INVALID_PARAM);
+	/* THEN sensor_mode is unchanged */
+	TEST_ASSERT(sensor_mode == 0);
+
+	/* GIVEN requested mode includes FP_MODE_DONT_CHANGE, THEN succeed */
+	TEST_ASSERT(sensor_mode == 0);
+	TEST_ASSERT(output_mode == 0);
+	requested_mode = FP_MODE_DONT_CHANGE;
+	TEST_ASSERT(fp_set_sensor_mode(requested_mode, &output_mode) ==
+		    EC_RES_SUCCESS);
+	/* THEN sensor_mode is unchanged */
+	TEST_ASSERT(sensor_mode == 0);
+	/* THEN output_mode matches sensor_mode */
+	TEST_ASSERT(output_mode == sensor_mode);
+
+	/* GIVEN request to change to valid sensor mode */
+	TEST_ASSERT(sensor_mode == 0);
+	requested_mode = FP_MODE_ENROLL_SESSION;
+	/* THEN succeed */
+	TEST_ASSERT(fp_set_sensor_mode(requested_mode, &output_mode) ==
+		    EC_RES_SUCCESS);
+	/* THEN requested mode is returned */
+	TEST_ASSERT(requested_mode == output_mode);
+	/* THEN sensor_mode is updated */
+	TEST_ASSERT(sensor_mode == requested_mode);
+
+	/* GIVEN max number of fingers already enrolled */
+	sensor_mode = 0;
+	output_mode = 0xdeadbeef;
+	templ_valid = FP_MAX_FINGER_COUNT;
+	requested_mode = FP_MODE_ENROLL_SESSION;
+	/* THEN additional enroll attempt will fail */
+	TEST_ASSERT(fp_set_sensor_mode(requested_mode, &output_mode) ==
+		    EC_RES_INVALID_PARAM);
+	/* THEN output parameters is unchanged */
+	TEST_ASSERT(output_mode = 0xdeadbeef);
+	/* THEN sensor_mode is unchanged */
+	TEST_ASSERT(sensor_mode == 0);
+
+	return EC_SUCCESS;
+}
+
+test_static enum ec_error_list test_fp_set_maintenance_mode(void)
+{
+	uint32_t output_mode = 0;
+
+	/* GIVEN request to change to maintenance sensor mode */
+	TEST_ASSERT(sensor_mode == 0);
+	/* THEN succeed */
+	TEST_ASSERT(fp_set_sensor_mode(FP_MODE_SENSOR_MAINTENANCE,
+				       &output_mode) == EC_RES_SUCCESS);
+	/* THEN requested mode is returned */
+	TEST_ASSERT(output_mode == FP_MODE_SENSOR_MAINTENANCE);
+	/* THEN sensor_mode is updated */
+	TEST_ASSERT(sensor_mode == FP_MODE_SENSOR_MAINTENANCE);
+
+	return EC_SUCCESS;
+}
+
+test_static enum ec_error_list
+test_fp_command_read_match_secret_fail_fgr_less_than_zero(void)
+{
+	/* Create invalid param with fgr < 0 */
+	struct ec_params_fp_read_match_secret test_match_secret = {
+		.fgr = static_cast<uint16_t>(-1),
+	};
+
+	TEST_ASSERT(test_send_host_command(EC_CMD_FP_READ_MATCH_SECRET, 0,
+					   &test_match_secret,
+					   sizeof(test_match_secret), NULL,
+					   0) == EC_RES_INVALID_PARAM);
+
+	return EC_SUCCESS;
+}
+
+test_static enum ec_error_list
+test_fp_command_read_match_secret_fail_fgr_large_than_max(void)
+{
+	/* Create invalid param with fgr = FP_MAX_FINGER_COUNT */
+	struct ec_params_fp_read_match_secret test_match_secret = {
+		.fgr = FP_MAX_FINGER_COUNT,
+	};
+
+	TEST_ASSERT(test_send_host_command(EC_CMD_FP_READ_MATCH_SECRET, 0,
+					   &test_match_secret,
+					   sizeof(test_match_secret), NULL,
+					   0) == EC_RES_INVALID_PARAM);
+	return EC_SUCCESS;
+}
+
+test_static enum ec_error_list
+test_fp_command_read_match_secret_fail_timeout(void)
+{
+	/* Create valid param with 0 <= fgr < 5 */
+	struct ec_params_fp_read_match_secret test_match_secret_1 = {
+		.fgr = 1,
+	};
+
+	/* Disable positive secret match to create 0 deadline val */
+	fp_disable_positive_match_secret(&positive_match_secret_state);
+
+	TEST_ASSERT(positive_match_secret_state.deadline.val == 0);
+
+	TEST_ASSERT(test_send_host_command(EC_CMD_FP_READ_MATCH_SECRET, 0,
+					   &test_match_secret_1,
+					   sizeof(test_match_secret_1), NULL,
+					   0) == EC_RES_TIMEOUT);
+
+	return EC_SUCCESS;
+}
+
+test_static enum ec_error_list
+test_fp_command_read_match_secret_unmatched_fgr(void)
+{
+	/* Create valid param with 0 <= fgr < 5 */
+	uint16_t matched_fgr = 1;
+	uint16_t unmatched_fgr = 2;
+	struct ec_params_fp_read_match_secret test_match_secret_1 = {
+		.fgr = matched_fgr,
+	};
+	/* Create positive secret match state with valid deadline value,
+	 * readable state, and wrong template matched
+	 */
+	struct positive_match_secret_state test_state = {
+		.template_matched = unmatched_fgr,
+		.readable = true,
+		.deadline = { .val = 5000000 },
+	};
+
+	/* Test for the wrong matched finger state */
+	positive_match_secret_state = test_state;
+
+	TEST_ASSERT(test_send_host_command(EC_CMD_FP_READ_MATCH_SECRET, 0,
+					   &test_match_secret_1,
+					   sizeof(test_match_secret_1), NULL,
+					   0) == EC_RES_ACCESS_DENIED);
+
+	return EC_SUCCESS;
+}
+
+test_static enum ec_error_list
+test_fp_command_read_match_secret_unreadable_state(void)
+{
+	/* Create valid param with 0 <= fgr < 5 */
+	uint16_t matched_fgr = 1;
+	struct ec_params_fp_read_match_secret test_match_secret_1 = {
+		.fgr = matched_fgr,
+	};
+	/*
+	 * Create positive secret match state with valid deadline value ,
+	 * unreadable state, and correct matched template
+	 */
+	struct positive_match_secret_state test_state = {
+		.template_matched = matched_fgr,
+		.readable = false,
+		.deadline = { .val = 5000000 },
+	};
+
+	/* Test for the unreadable state */
+	positive_match_secret_state = test_state;
+
+	TEST_ASSERT(test_send_host_command(EC_CMD_FP_READ_MATCH_SECRET, 0,
+					   &test_match_secret_1,
+					   sizeof(test_match_secret_1), NULL,
+					   0) == EC_RES_ACCESS_DENIED);
+
+	return EC_SUCCESS;
+}
+
+test_static enum ec_error_list
+test_fp_command_read_match_secret_derive_fail(void)
+{
+	struct ec_response_fp_read_match_secret response = { 0 };
+	/* Create valid param with 0 <= fgr < 5 */
+	uint16_t matched_fgr = 1;
+	struct ec_params_fp_read_match_secret test_match_secret_1 = {
+		.fgr = matched_fgr,
+	};
+	/* Create positive secret match state with valid deadline value,
+	 * readable state, and correct template matched
+	 */
+	struct positive_match_secret_state test_state_1 = {
+		.template_matched = matched_fgr,
+		.readable = true,
+		.deadline = { .val = 5000000 },
+	};
+	positive_match_secret_state = test_state_1;
+	/* Set fp_positive_match_salt to the trivial value */
+	memcpy(fp_positive_match_salt, trivial_fp_positive_match_salt,
+	       sizeof(trivial_fp_positive_match_salt));
+
+	/* Test with the correct matched finger state and a trivial
+	 * fp_positive_match_salt
+	 */
+	TEST_ASSERT(test_send_host_command(
+			    EC_CMD_FP_READ_MATCH_SECRET, 0,
+			    &test_match_secret_1, sizeof(test_match_secret_1),
+			    &response, sizeof(response)) == EC_RES_ERROR);
+	return EC_SUCCESS;
+}
+
+test_static enum ec_error_list
+test_fp_command_read_match_secret_derive_succeed(void)
+{
+	struct ec_response_fp_read_match_secret response = { 0 };
+	/* Create valid param with 0 <= fgr < 5 */
+	uint16_t matched_fgr = 1;
+	struct ec_params_fp_read_match_secret test_match_secret_1 = {
+		.fgr = matched_fgr,
+	};
+
+	/* Expected positive_match_secret same as  in test/fpsensor_crypto.c*/
+	static const uint8_t
+		expected_positive_match_secret_for_empty_user_id[] = {
+			0x8d, 0xc4, 0x5b, 0xdf, 0x55, 0x1e, 0xa8, 0x72,
+			0xd6, 0xdd, 0xa1, 0x4c, 0xb8, 0xa1, 0x76, 0x2b,
+			0xde, 0x38, 0xd5, 0x03, 0xce, 0xe4, 0x74, 0x51,
+			0x63, 0x6c, 0x6a, 0x26, 0xa9, 0xb7, 0xfa, 0x68,
+		};
+	/* Create positive secret match state with valid deadline value,
+	 * readable state, and correct template matched
+	 */
+	struct positive_match_secret_state test_state_1 = {
+		.template_matched = matched_fgr,
+		.readable = true,
+		.deadline = { .val = 5000000 },
+	};
+	positive_match_secret_state = test_state_1;
+	/* Set fp_positive_match_salt to the trivial value */
+	memcpy(fp_positive_match_salt, default_fake_fp_positive_match_salt,
+	       sizeof(default_fake_fp_positive_match_salt));
+
+	TEST_ASSERT_ARRAY_EQ(
+		(uint8_t const *)fp_positive_match_salt,
+		(uint8_t const *)default_fake_fp_positive_match_salt,
+		sizeof(default_fake_fp_positive_match_salt));
+
+	/* Initialize an empty user_id to compare positive_match_secret */
+	memset(user_id, 0, sizeof(user_id));
+
+	TEST_ASSERT(fp_tpm_seed_is_set());
+	/* Test with the correct matched finger state and the default fake
+	 * fp_positive_match_salt
+	 */
+	TEST_ASSERT(test_send_host_command(
+			    EC_CMD_FP_READ_MATCH_SECRET, 0,
+			    &test_match_secret_1, sizeof(test_match_secret_1),
+			    &response, sizeof(response)) == EC_RES_SUCCESS);
+
+	TEST_ASSERT_ARRAY_EQ(
+		response.positive_match_secret,
+		expected_positive_match_secret_for_empty_user_id,
+		sizeof(expected_positive_match_secret_for_empty_user_id));
+
+	return EC_SUCCESS;
+}
+
+extern "C" void run_test(int argc, const char **argv)
+{
+	RUN_TEST(test_fp_enc_status_valid_flags);
+	RUN_TEST(test_fp_tpm_seed_not_set);
+	RUN_TEST(test_set_fp_tpm_seed);
+	RUN_TEST(test_set_fp_tpm_seed_again);
+	RUN_TEST(test_fp_set_sensor_mode);
+	RUN_TEST(test_fp_set_maintenance_mode);
+	RUN_TEST(test_fp_command_read_match_secret_fail_fgr_less_than_zero);
+	RUN_TEST(test_fp_command_read_match_secret_fail_fgr_large_than_max);
+	RUN_TEST(test_fp_command_read_match_secret_fail_timeout);
+	RUN_TEST(test_fp_command_read_match_secret_unmatched_fgr);
+	RUN_TEST(test_fp_command_read_match_secret_unreadable_state);
+	RUN_TEST(test_fp_command_read_match_secret_derive_fail);
+	RUN_TEST(test_fp_command_read_match_secret_derive_succeed);
+	test_print_result();
+}
diff --git a/test/ftrapv.c b/test/ftrapv.c
new file mode 100644
index 0000000000..1aefb8404f
--- /dev/null
+++ b/test/ftrapv.c
@@ -0,0 +1,265 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "panic.h"
+#include "system.h"
+#include "task.h"
+#include "test_util.h"
+
+#include <stdlib.h>
+
+/*
+ * trapping addition: __addvsi3.
+ */
+test_static int test_ftrapv_addition(void)
+{
+	int32_t test_overflow = INT32_MAX;
+	int32_t ret;
+
+	ccprintf("Testing signed integer addition overflow\n");
+	cflush();
+	ret = test_overflow + 1;
+
+	/* Should never reach this. */
+	ccprintf("ret: %d\n", ret);
+	cflush();
+
+	return EC_ERROR_UNKNOWN;
+}
+
+/*
+ * trapping subtraction: __subvsi3.
+ */
+test_static int test_ftrapv_subtraction(void)
+{
+	int32_t test_overflow = INT32_MIN;
+	int32_t ret;
+
+	ccprintf("Testing signed integer subtraction overflow\n");
+	cflush();
+	ret = test_overflow - 1;
+
+	/* Should never reach this. */
+	ccprintf("ret: %d\n", ret);
+	cflush();
+
+	return EC_ERROR_UNKNOWN;
+}
+
+/*
+ * trapping multiplication: __mulvsi3.
+ */
+test_static int test_ftrapv_multiplication(void)
+{
+	int32_t test_overflow = INT32_MAX;
+	int32_t ret;
+
+	ccprintf("Testing signed integer multiplication overflow\n");
+	cflush();
+	ret = test_overflow * 2;
+
+	/* Should never reach this. */
+	ccprintf("ret: %d\n", ret);
+	cflush();
+
+	return EC_ERROR_UNKNOWN;
+}
+
+/*
+ * trapping negation: __negvsi2.
+ */
+test_static int test_ftrapv_negation(void)
+{
+	int32_t test_overflow = INT32_MIN;
+	int32_t ret;
+
+	ccprintf("Testing signed integer negation overflow\n");
+	cflush();
+	ret = -test_overflow;
+
+	/* Should never reach this. */
+	ccprintf("ret: %d\n", ret);
+	cflush();
+
+	return EC_ERROR_UNKNOWN;
+}
+
+/*
+ * trapping absolute value: __absvsi2.
+ *
+ * TODO(b/258074414): Trapping on absolute value overflow is broken in clang.
+ */
+test_static int test_ftrapv_absolute_value(void)
+{
+	int32_t test_overflow = INT32_MIN;
+	int32_t ret;
+
+	ccprintf("Testing signed integer absolute value overflow\n");
+	cflush();
+
+	ret = abs(test_overflow);
+
+	/* Should never reach this. */
+	ccprintf("ret: %d\n", ret);
+	cflush();
+
+	return EC_ERROR_UNKNOWN;
+}
+
+test_static int test_panic_data(void)
+{
+	const uint32_t expected_reason = 0;
+	const uint32_t expected_info = 0;
+	/*
+	 * https://developer.arm.com/documentation/dui0552/a/the-cortex-m3-processor/exception-model/exception-types
+	 */
+	const uint8_t expected_exception = 6; /* usage fault */
+
+	uint32_t reason = UINT32_MAX;
+	uint32_t info = UINT32_MAX;
+	uint8_t exception = UINT8_MAX;
+
+	panic_get_reason(&reason, &info, &exception);
+
+	TEST_EQ(reason, expected_reason, "%08x");
+	TEST_EQ(info, expected_info, "%d");
+	TEST_EQ(exception, expected_exception, "%d");
+
+	return EC_SUCCESS;
+}
+
+test_static void run_test_step1(void)
+{
+	test_set_next_step(TEST_STATE_STEP_2);
+	RUN_TEST(test_ftrapv_addition);
+}
+
+test_static void run_test_step2(void)
+{
+	RUN_TEST(test_panic_data);
+
+	if (test_get_error_count())
+		test_reboot_to_next_step(TEST_STATE_FAILED);
+	else
+		test_reboot_to_next_step(TEST_STATE_STEP_3);
+}
+
+test_static void run_test_step3(void)
+{
+	test_set_next_step(TEST_STATE_STEP_4);
+	RUN_TEST(test_ftrapv_subtraction);
+}
+
+test_static void run_test_step4(void)
+{
+	RUN_TEST(test_panic_data);
+
+	if (test_get_error_count())
+		test_reboot_to_next_step(TEST_STATE_FAILED);
+	else
+		test_reboot_to_next_step(TEST_STATE_STEP_5);
+}
+
+test_static void run_test_step5(void)
+{
+	test_set_next_step(TEST_STATE_STEP_6);
+	RUN_TEST(test_ftrapv_multiplication);
+}
+
+test_static void run_test_step6(void)
+{
+	RUN_TEST(test_panic_data);
+
+	if (test_get_error_count())
+		test_reboot_to_next_step(TEST_STATE_FAILED);
+	else
+		test_reboot_to_next_step(TEST_STATE_STEP_7);
+}
+
+test_static void run_test_step7(void)
+{
+	test_set_next_step(TEST_STATE_STEP_8);
+	RUN_TEST(test_ftrapv_negation);
+}
+
+test_static void run_test_step8(void)
+{
+	RUN_TEST(test_panic_data);
+
+	if (test_get_error_count())
+		test_reboot_to_next_step(TEST_STATE_FAILED);
+	else
+		test_reboot_to_next_step(TEST_STATE_STEP_9);
+}
+
+test_static void run_test_step9(void)
+{
+	/*
+	 * TODO(b/258074414): Trapping on absolute value overflow is broken in
+	 * clang, so skip the check.
+	 */
+#if 0
+	test_set_next_step(TEST_STATE_STEP_10);
+	RUN_TEST(test_ftrapv_absolute_value);
+#else
+	test_reboot_to_next_step(TEST_STATE_STEP_10);
+#endif
+}
+
+test_static void run_test_step10(void)
+{
+	/*
+	 * TODO(b/258074414): Trapping on absolute value overflow is broken in
+	 * clang, so skip the check.
+	 */
+#if 0
+	RUN_TEST(test_panic_data);
+#endif
+
+	if (test_get_error_count())
+		test_reboot_to_next_step(TEST_STATE_FAILED);
+	else
+		test_reboot_to_next_step(TEST_STATE_PASSED);
+}
+
+void test_run_step(uint32_t state)
+{
+	if (state & TEST_STATE_MASK(TEST_STATE_STEP_1)) {
+		run_test_step1();
+	} else if (state & TEST_STATE_MASK(TEST_STATE_STEP_2)) {
+		run_test_step2();
+	} else if (state & TEST_STATE_MASK(TEST_STATE_STEP_3)) {
+		run_test_step3();
+	} else if (state & TEST_STATE_MASK(TEST_STATE_STEP_4)) {
+		run_test_step4();
+	} else if (state & TEST_STATE_MASK(TEST_STATE_STEP_5)) {
+		run_test_step5();
+	} else if (state & TEST_STATE_MASK(TEST_STATE_STEP_6)) {
+		run_test_step6();
+	} else if (state & TEST_STATE_MASK(TEST_STATE_STEP_7)) {
+		run_test_step7();
+	} else if (state & TEST_STATE_MASK(TEST_STATE_STEP_8)) {
+		run_test_step8();
+	} else if (state & TEST_STATE_MASK(TEST_STATE_STEP_9)) {
+		run_test_step9();
+	} else if (state & TEST_STATE_MASK(TEST_STATE_STEP_10)) {
+		run_test_step10();
+	}
+}
+
+int task_test(void *unused)
+{
+	if (IS_ENABLED(SECTION_IS_RW))
+		test_run_multistep();
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
+{
+	test_reset();
+	msleep(30); /* Wait for TASK_ID_TEST to initialize */
+	task_wake(TASK_ID_TEST);
+}
diff --git a/test/ftrapv.tasklist b/test/ftrapv.tasklist
new file mode 100644
index 0000000000..273a9664c0
--- /dev/null
+++ b/test/ftrapv.tasklist
@@ -0,0 +1,10 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST \
+  TASK_TEST(TEST, task_test, NULL, TASK_STACK_SIZE)
diff --git a/test/genvif/.gitignore b/test/genvif/.gitignore
new file mode 100644
index 0000000000..eabdcbd17f
--- /dev/null
+++ b/test/genvif/.gitignore
@@ -0,0 +1,2 @@
+genvif
+vif_output
diff --git a/test/genvif/Makefile b/test/genvif/Makefile
new file mode 100644
index 0000000000..a41e8308cc
--- /dev/null
+++ b/test/genvif/Makefile
@@ -0,0 +1,24 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+
+CC=gcc
+CFLAGS=-O2 -Isrc -I../../include
+
+genvif: ../../util/genvif.c src/helper.c
+	@$(CC) -o $@ $^ $(CFLAGS)
+
+test: genvif
+	@mkdir vif_output 2>/dev/null
+	@./genvif -b test -o vif_output
+	@./genvif -b exp_test -o vif_output -n -v vif/exp_test_vif.xml
+	@diff vif_output/test_vif.xml vif_output/exp_test_vif.xml
+	@./genvif -b test_over -o vif_output -v vif/over_test_vif.xml
+	@./genvif -b exp_test_over -o vif_output -n -v vif/exp_test_over_vif.xml
+	@diff vif_output/test_over_vif.xml vif_output/exp_test_over_vif.xml
+
+.PHONY: clean
+clean:
+	@rm -f genvif
+	@rm -rf vif_output
diff --git a/test/genvif/genvif.sh b/test/genvif/genvif.sh
new file mode 100755
index 0000000000..b54d1de9eb
--- /dev/null
+++ b/test/genvif/genvif.sh
@@ -0,0 +1,8 @@
+#!/bin/bash -e
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cd test/genvif
+make clean
+make test
diff --git a/test/genvif/src/atomic.h b/test/genvif/src/atomic.h
new file mode 100644
index 0000000000..d58e57a1c2
--- /dev/null
+++ b/test/genvif/src/atomic.h
@@ -0,0 +1,8 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Blank shell to avoid including the real file
+ */
diff --git a/test/genvif/src/board.h b/test/genvif/src/board.h
new file mode 100644
index 0000000000..c596b833e0
--- /dev/null
+++ b/test/genvif/src/board.h
@@ -0,0 +1,13 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 65000
+#define PD_MAX_CURRENT_MA 3250
+#define PD_MAX_VOLTAGE_MV 20000
+
+/* Stubs required by the shared code */
+#define GPIO_PIN(port, index) (GPIO_##port, BIT(index))
+#define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m)
diff --git a/test/genvif/src/config_chip.h b/test/genvif/src/config_chip.h
new file mode 100644
index 0000000000..d58e57a1c2
--- /dev/null
+++ b/test/genvif/src/config_chip.h
@@ -0,0 +1,8 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Blank shell to avoid including the real file
+ */
diff --git a/test/genvif/src/fuzz_config.h b/test/genvif/src/fuzz_config.h
new file mode 100644
index 0000000000..d58e57a1c2
--- /dev/null
+++ b/test/genvif/src/fuzz_config.h
@@ -0,0 +1,8 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Blank shell to avoid including the real file
+ */
diff --git a/test/genvif/src/gpio.inc b/test/genvif/src/gpio.inc
new file mode 100644
index 0000000000..65e3066695
--- /dev/null
+++ b/test/genvif/src/gpio.inc
@@ -0,0 +1,8 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Stub file only */
\ No newline at end of file
diff --git a/test/genvif/src/helper.c b/test/genvif/src/helper.c
new file mode 100644
index 0000000000..f3b5d97317
--- /dev/null
+++ b/test/genvif/src/helper.c
@@ -0,0 +1,33 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "usb_pd.h"
+
+#ifndef CONFIG_USB_PD_CUSTOM_PDO
+#define PDO_FIXED_FLAGS \
+	(PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP | PDO_FIXED_COMM_CAP)
+
+const uint32_t pd_src_pdo[] = {
+	PDO_FIXED(5000, 1500, PDO_FIXED_FLAGS),
+};
+const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
+const uint32_t pd_src_pdo_max[] = {
+	PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS),
+};
+const int pd_src_pdo_max_cnt = ARRAY_SIZE(pd_src_pdo_max);
+
+const uint32_t pd_snk_pdo[] = {
+	PDO_FIXED(5000, 500, PDO_FIXED_FLAGS),
+	PDO_BATT(4750, PD_MAX_VOLTAGE_MV, PD_OPERATING_POWER_MW),
+	PDO_VAR(4750, PD_MAX_VOLTAGE_MV, PD_MAX_CURRENT_MA),
+};
+const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
+#endif /* CONFIG_USB_PD_CUSTOM_PDO */
+
+uint8_t board_get_usb_pd_port_count(void)
+{
+	return 1;
+}
diff --git a/test/genvif/src/test_config.h b/test/genvif/src/test_config.h
new file mode 100644
index 0000000000..d58e57a1c2
--- /dev/null
+++ b/test/genvif/src/test_config.h
@@ -0,0 +1,8 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Blank shell to avoid including the real file
+ */
diff --git a/test/genvif/src/timer.h b/test/genvif/src/timer.h
new file mode 100644
index 0000000000..d58e57a1c2
--- /dev/null
+++ b/test/genvif/src/timer.h
@@ -0,0 +1,8 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Blank shell to avoid including the real file
+ */
diff --git a/test/genvif/vif/exp_test_over_vif.xml b/test/genvif/vif/exp_test_over_vif.xml
new file mode 100644
index 0000000000..c81f36faac
--- /dev/null
+++ b/test/genvif/vif/exp_test_over_vif.xml
@@ -0,0 +1,89 @@
+<?xml version="1.0" encoding="utf-8"?>
+<vif:VIF>
+  <vif:VIF_Specification>3.18</VIF_Specification>
+  <vif:Vendor_Name>Google</Vendor_Name>
+  <vif:Model_Part_Number>SuperTestWithOverride</Model_Part_Number>
+  <vif:Product_Revision>Final</Product_Revision>
+  <vif:TID>12345</TID>
+  <vif:VIF_Product_Type value="0">Port Product</VIF_Product_Type>
+  <vif:Certification_Type value="0">End Product</Certification_Type>
+  <vif:Component>
+    <vif:Port_Label>0</Port_Label>
+    <vif:Connector_Type value="2">Type-C®</Connector_Type>
+    <vif:USB4_Supported value="false" />
+    <vif:USB_PD_Support value="true" />
+    <vif:PD_Port_Type value="4">DRP</PD_Port_Type>
+    <vif:Type_C_State_Machine value="2">DRP</Type_C_State_Machine>
+    <vif:Captive_Cable value="false" />
+    <vif:Port_Battery_Powered value="false" />
+    <vif:BC_1_2_Support value="0">None</BC_1_2_Support>
+    <vif:PD_Spec_Revision_Major value="3" />
+    <vif:PD_Spec_Revision_Minor value="1" />
+    <vif:PD_Spec_Version_Major value="1" />
+    <vif:PD_Spec_Version_Minor value="3" />
+    <vif:PD_Specification_Revision value="2">Revision 3</PD_Specification_Revision>
+    <vif:USB_Comms_Capable value="true" />
+    <vif:DR_Swap_To_DFP_Supported value="true" />
+    <vif:DR_Swap_To_UFP_Supported value="false" />
+    <vif:Unconstrained_Power value="false" />
+    <vif:VCONN_Swap_To_On_Supported value="false" />
+    <vif:VCONN_Swap_To_Off_Supported value="false" />
+    <vif:Responds_To_Discov_SOP_UFP value="false" />
+    <vif:Responds_To_Discov_SOP_DFP value="false" />
+    <vif:Attempts_Discov_SOP value="true" />
+    <vif:Chunking_Implemented_SOP value="false" />
+    <vif:Unchunked_Extended_Messages_Supported value="false" />
+    <vif:Manufacturer_Info_Supported_Port value="false" />
+    <vif:Security_Msgs_Supported_SOP value="false" />
+    <vif:Num_Fixed_Batteries value="1" />
+    <vif:Num_Swappable_Battery_Slots value="0" />
+    <vif:ID_Header_Connector_Type_SOP value="2">USB Type-C® Receptacle</ID_Header_Connector_Type_SOP>
+    <vif:SOP_Capable value="true" />
+    <vif:SOP_P_Capable value="false" />
+    <vif:SOP_PP_Capable value="false" />
+    <vif:SOP_P_Debug_Capable value="false" />
+    <vif:SOP_PP_Debug_Capable value="false" />
+    <vif:Type_C_Implements_Try_SRC value="false" />
+    <vif:Type_C_Implements_Try_SNK value="false" />
+    <vif:RP_Value value="1">1.5A</RP_Value>
+    <vif:Power_Interruption_Available value="0">No Interruption Possible</Power_Interruption_Available>
+    <vif:Data_Reset_Supported value="false" />
+    <vif:Enter_USB_Supported value="false" />
+    <vif:Type_C_Is_VCONN_Powered_Accessory value="false" />
+    <vif:Type_C_Is_Debug_Target_SRC value="true" />
+    <vif:Type_C_Is_Debug_Target_SNK value="true" />
+    <vif:Type_C_Can_Act_As_Host value="true" />
+    <vif:Type_C_Is_Alt_Mode_Controller value="false" />
+    <vif:Type_C_Is_Alt_Mode_Adapter value="false" />
+    <vif:Type_C_Can_Act_As_Device value="false" />
+    <vif:Type_C_Power_Source value="1">UFP-powered</Type_C_Power_Source>
+    <vif:Type_C_Port_On_Hub value="false" />
+    <vif:Type_C_Supports_Audio_Accessory value="false" />
+    <vif:Type_C_Sources_VCONN value="false" />
+    <vif:PD_Power_As_Source value="15000">15000 mW</PD_Power_As_Source>
+    <vif:USB_Suspend_May_Be_Cleared value="false" />
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="0">FR_Swap not supported</FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <vif:Master_Port value="false" />
+    <vif:Num_Src_PDOs value="1" />
+    <vif:Host_Supports_USB_Data value="true" />
+    <vif:Host_Speed value="1">USB 3.2 Gen 1x1</Host_Speed>
+    <vif:Is_DFP_On_Hub value="false" />
+    <vif:Host_Contains_Captive_Retimer value="false" />
+    <vif:Host_Is_Embedded value="false" />
+    <vif:PD_OC_Protection value="false" />
+    <vif:Product_Total_Source_Power_mW value="15000">15000 mW</Product_Total_Source_Power_mW>
+    <vif:Port_Source_Power_Type value="0">Assured</Port_Source_Power_Type>
+    <vif:EPR_Supported_As_Src value="false" />
+    <vif:Modal_Operation_Supported_SOP value="false" />
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <vif:Src_PDO_Supply_Type value="0">Fixed</Src_PDO_Supply_Type>
+        <vif:Src_PDO_Peak_Current value="0">100% IOC</Src_PDO_Peak_Current>
+        <vif:Src_PDO_Voltage value="100">5000 mV</Src_PDO_Voltage>
+        <vif:Src_PDO_Max_Current value="300">3000 mA</Src_PDO_Max_Current>
+        <vif:Src_PD_OCP_OC_Debounce value="50">50 msec</Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="360">3600 mA</Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+  </vif:Component>
+</vif:VIF>
diff --git a/test/genvif/vif/exp_test_vif.xml b/test/genvif/vif/exp_test_vif.xml
new file mode 100644
index 0000000000..7aade79006
--- /dev/null
+++ b/test/genvif/vif/exp_test_vif.xml
@@ -0,0 +1,87 @@
+<vif:VIF>
+  <vif:VIF_Specification>3.18</vif:VIF_Specification>
+  <vif:Vendor_Name>Google</vif:Vendor_Name>
+  <vif:Model_Part_Number>test</vif:Model_Part_Number>
+  <vif:Product_Revision>FIX-ME</vif:Product_Revision>
+  <vif:TID>65535</vif:TID>
+  <vif:VIF_Product_Type value="0">Port Product</vif:VIF_Product_Type>
+  <vif:Certification_Type value="0">End Product</vif:Certification_Type>
+  <vif:Component>
+    <vif:Port_Label>0</vif:Port_Label>
+    <vif:Connector_Type value="2">Type-C®</vif:Connector_Type>
+    <vif:USB4_Supported value="false" />
+    <vif:USB_PD_Support value="true" />
+    <vif:PD_Port_Type value="4">DRP</vif:PD_Port_Type>
+    <vif:Type_C_State_Machine value="2">DRP</vif:Type_C_State_Machine>
+    <vif:Captive_Cable value="false" />
+    <vif:Port_Battery_Powered value="false" />
+    <vif:BC_1_2_Support value="0">None</vif:BC_1_2_Support>
+    <vif:PD_Spec_Revision_Major value="3" />
+    <vif:PD_Spec_Revision_Minor value="1" />
+    <vif:PD_Spec_Version_Major value="1" />
+    <vif:PD_Spec_Version_Minor value="3" />
+    <vif:PD_Specification_Revision value="2">Revision 3</vif:PD_Specification_Revision>
+    <vif:USB_Comms_Capable value="true" />
+    <vif:DR_Swap_To_DFP_Supported value="true" />
+    <vif:DR_Swap_To_UFP_Supported value="false" />
+    <vif:Unconstrained_Power value="false" />
+    <vif:VCONN_Swap_To_On_Supported value="false" />
+    <vif:VCONN_Swap_To_Off_Supported value="false" />
+    <vif:Responds_To_Discov_SOP_UFP value="false" />
+    <vif:Responds_To_Discov_SOP_DFP value="false" />
+    <vif:Attempts_Discov_SOP value="true" />
+    <vif:Chunking_Implemented_SOP value="false" />
+    <vif:Unchunked_Extended_Messages_Supported value="false" />
+    <vif:Manufacturer_Info_Supported_Port value="false" />
+    <vif:Security_Msgs_Supported_SOP value="false" />
+    <vif:Num_Fixed_Batteries value="1" />
+    <vif:Num_Swappable_Battery_Slots value="0" />
+    <vif:ID_Header_Connector_Type_SOP value="2">USB Type-C® Receptacle</vif:ID_Header_Connector_Type_SOP>
+    <vif:SOP_Capable value="true" />
+    <vif:SOP_P_Capable value="false" />
+    <vif:SOP_PP_Capable value="false" />
+    <vif:SOP_P_Debug_Capable value="false" />
+    <vif:SOP_PP_Debug_Capable value="false" />
+    <vif:Type_C_Implements_Try_SRC value="false" />
+    <vif:Type_C_Implements_Try_SNK value="false" />
+    <vif:RP_Value value="1">1.5A</vif:RP_Value>
+    <vif:Type_C_Is_VCONN_Powered_Accessory value="false" />
+    <vif:Type_C_Is_Debug_Target_SRC value="true" />
+    <vif:Type_C_Is_Debug_Target_SNK value="true" />
+    <vif:Power_Interruption_Available value="0">No Interruption Possible</vif:Power_Interruption_Available>
+    <vif:Data_Reset_Supported value="false" />
+    <vif:Enter_USB_Supported value="false" />
+    <vif:Type_C_Can_Act_As_Host value="true" />
+    <vif:Type_C_Is_Alt_Mode_Controller value="false" />
+    <vif:Type_C_Is_Alt_Mode_Adapter value="false" />
+    <vif:Type_C_Can_Act_As_Device value="false" />
+    <vif:Type_C_Power_Source value="1">UFP-powered</vif:Type_C_Power_Source>
+    <vif:Type_C_Port_On_Hub value="false" />
+    <vif:Type_C_Supports_Audio_Accessory value="false" />
+    <vif:Type_C_Sources_VCONN value="false" />
+    <vif:PD_Power_As_Source value="15000">15000 mW</vif:PD_Power_As_Source>
+    <vif:USB_Suspend_May_Be_Cleared value="false" />
+    <vif:Sends_Pings value="false" />
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="0">FR_Swap not supported</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <vif:Master_Port value="false" />
+    <vif:Num_Src_PDOs value="1" />
+    <vif:Host_Supports_USB_Data value="true" />
+    <vif:Host_Speed value="1">USB 3.2 Gen 1x1</vif:Host_Speed>
+    <vif:Is_DFP_On_Hub value="false" />
+    <vif:Host_Contains_Captive_Retimer value="false" />
+    <vif:Host_Is_Embedded value="false" />
+    <vif:PD_OC_Protection value="false" />
+    <vif:Product_Total_Source_Power_mW value="15000">15000 mW</vif:Product_Total_Source_Power_mW>
+    <vif:Port_Source_Power_Type value="0">Assured</vif:Port_Source_Power_Type>
+    <vif:EPR_Supported_As_Src value="false" />
+    <vif:Modal_Operation_Supported_SOP value="false" />
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <vif:Src_PDO_Supply_Type value="0">Fixed</vif:Src_PDO_Supply_Type>
+        <vif:Src_PDO_Peak_Current value="0">100% IOC</vif:Src_PDO_Peak_Current>
+        <vif:Src_PDO_Voltage value="100">5000 mV</vif:Src_PDO_Voltage>
+        <vif:Src_PDO_Max_Current value="300">3000 mA</vif:Src_PDO_Max_Current>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+  </vif:Component>
+</vif:VIF>
diff --git a/test/genvif/vif/over_test_vif.xml b/test/genvif/vif/over_test_vif.xml
new file mode 100644
index 0000000000..a8d1b8f08e
--- /dev/null
+++ b/test/genvif/vif/over_test_vif.xml
@@ -0,0 +1,19 @@
+<vif:VIF>
+  <!-- Override the following fields -->
+  <vif:Model_Part_Number>SuperTestWithOverride</vif:Model_Part_Number>
+  <vif:Product_Revision>Final</vif:Product_Revision>
+  <vif:TID>12345</vif:TID>
+
+  <vif:Component>
+    <!-- Remove Sends_Pings -->
+    <vif:Sends_Pings />
+
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!-- Add in missing fields for SrcPdo0 -->
+        <vif:Src_PD_OCP_OC_Debounce value="50">50 msec</vif:Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="360">3600 mA</vif:Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+  </vif:Component>
+</vif:VIF>
diff --git a/test/gettimeofday.c b/test/gettimeofday.c
new file mode 100644
index 0000000000..3e6d33602a
--- /dev/null
+++ b/test/gettimeofday.c
@@ -0,0 +1,92 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "gettimeofday.h"
+#include "mock/timer_mock.h"
+#include "test_util.h"
+
+#include <stddef.h>
+
+static int test_gettimeofday_zero(void)
+{
+	struct timeval tv;
+	timestamp_t now;
+
+	now.val = 0;
+	set_time(now);
+
+	TEST_EQ(ec_gettimeofday(&tv, NULL), EC_SUCCESS, "%d");
+	TEST_EQ(tv.tv_sec, 0L, "%ld");
+	TEST_EQ(tv.tv_usec, 0L, "%ld");
+
+	return EC_SUCCESS;
+}
+
+static int test_gettimeofday_zero_seconds(void)
+{
+	struct timeval tv;
+	timestamp_t now;
+
+	now.val = 100;
+	set_time(now);
+
+	TEST_EQ(ec_gettimeofday(&tv, NULL), EC_SUCCESS, "%d");
+	TEST_EQ(tv.tv_sec, 0L, "%ld");
+	TEST_EQ(tv.tv_usec, 100L, "%ld");
+
+	return EC_SUCCESS;
+}
+
+static int test_gettimeofday_nonzero_seconds(void)
+{
+	struct timeval tv;
+	timestamp_t now;
+
+	now.val = 1000001;
+	set_time(now);
+
+	TEST_EQ(ec_gettimeofday(&tv, NULL), EC_SUCCESS, "%d");
+	TEST_EQ(tv.tv_sec, 1L, "%ld");
+	TEST_EQ(tv.tv_usec, 1L, "%ld");
+
+	return EC_SUCCESS;
+}
+
+static int test_gettimeofday_max(void)
+{
+	struct timeval tv;
+	timestamp_t now;
+
+	now.val = UINT64_MAX;
+	set_time(now);
+
+	TEST_EQ(ec_gettimeofday(&tv, NULL), EC_SUCCESS, "%d");
+	TEST_EQ(tv.tv_sec, 18446744073709L, "%ld");
+	TEST_EQ(tv.tv_usec, 551615L, "%ld");
+
+	return EC_SUCCESS;
+}
+
+static int test_gettimeofday_null_arg(void)
+{
+	TEST_EQ(ec_gettimeofday(NULL, NULL), EC_ERROR_INVAL, "%d");
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
+{
+	/*
+	 * Right now these tests only work on the host since they use a mock
+	 * timer. Using a mock timer on device prevents the device from booting.
+	 */
+	test_reset();
+	RUN_TEST(test_gettimeofday_zero);
+	RUN_TEST(test_gettimeofday_zero_seconds);
+	RUN_TEST(test_gettimeofday_nonzero_seconds);
+	RUN_TEST(test_gettimeofday_max);
+	RUN_TEST(test_gettimeofday_null_arg);
+	test_print_result();
+}
diff --git a/test/gettimeofday.mocklist b/test/gettimeofday.mocklist
new file mode 100644
index 0000000000..fd1425faf1
--- /dev/null
+++ b/test/gettimeofday.mocklist
@@ -0,0 +1,8 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifdef TEST_BUILD
+#define CONFIG_TEST_MOCK_LIST MOCK(TIMER)
+#endif /* TEST_BUILD */
diff --git a/test/gettimeofday.tasklist b/test/gettimeofday.tasklist
new file mode 100644
index 0000000000..1154b1ae8b
--- /dev/null
+++ b/test/gettimeofday.tasklist
@@ -0,0 +1,9 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST  /* No test task */
diff --git a/test/global_initialization.cc b/test/global_initialization.cc
new file mode 100644
index 0000000000..5168494ab4
--- /dev/null
+++ b/test/global_initialization.cc
@@ -0,0 +1,50 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @brief Tests initialization of global/static objects.
+ */
+
+#include "test_util.h"
+
+#include <cstdio>
+#include <cstring>
+
+struct TestObj {
+	TestObj()
+	{
+		/*
+		 * In order to make sure the compiler can't perform the
+		 * initialization at compile time (e.g., initialization of a
+		 * POD value), we make a function call.
+		 *
+		 * In order to keep the test focused on initialization only
+		 * and not the behavior of the heap, we avoid objects that
+		 * would use dynamic allocation (such as std::vector).
+		 *
+		 * When making changes to this test, make sure to disable the
+		 * call to call constructors of global objects
+		 * (__libc_init_array) and make sure the test fails.
+		 */
+		snprintf(val, sizeof(val), "test %d", 42);
+	}
+
+	char val[8];
+};
+
+static TestObj global_obj;
+
+static int test_global_init()
+{
+	TEST_EQ(strcmp(global_obj.val, "test 42"), 0, "%d");
+	return EC_SUCCESS;
+}
+
+extern "C" void run_test(int, const char **)
+{
+	test_reset();
+	RUN_TEST(test_global_init);
+	test_print_result();
+}
diff --git a/test/global_initialization.tasklist b/test/global_initialization.tasklist
new file mode 100644
index 0000000000..35fa6f24bd
--- /dev/null
+++ b/test/global_initialization.tasklist
@@ -0,0 +1,9 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST
diff --git a/test/gyro_cal.c b/test/gyro_cal.c
index 85d53789ef..cf9af0fdbc 100644
--- a/test/gyro_cal.c
+++ b/test/gyro_cal.c
@@ -1,17 +1,19 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "common.h"
 #include "gyro_cal.h"
+#include "gyro_cal_init_for_test.h"
 #include "gyro_still_det.h"
 #include "motion_sense.h"
 #include "test_util.h"
-#include <string.h>
-#include <stdlib.h>
+
 #include <math.h>
 #include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
 
 float kToleranceGyroRps = 1e-6f;
 float kDefaultGravityMps2 = 9.81f;
@@ -69,107 +71,6 @@ static float normal_random2(float mean, float stddev)
 	return normal_random() * stddev + mean;
 }
 
-/**
- *
- * @param det              Pointer to the stillness detector
- * @param var_threshold    The variance threshold in units^2
- * @param confidence_delta The confidence delta in units^2
- */
-static void gyro_still_det_initialization_for_test(struct gyro_still_det *det,
-						   float var_threshold,
-						   float confidence_delta)
-{
-	/* Clear all data structure variables to 0. */
-	memset(det, 0, sizeof(struct gyro_still_det));
-
-	/*
-	 * Set the delta about the variance threshold for calculation
-	 * of the stillness confidence score.
-	 */
-	if (confidence_delta < var_threshold)
-		det->confidence_delta = confidence_delta;
-	else
-		det->confidence_delta = var_threshold;
-
-	/*
-	 * Set the variance threshold parameter for the stillness
-	 * confidence score.
-	 */
-	det->var_threshold = var_threshold;
-
-	/* Signal to start capture of next stillness data window. */
-	det->start_new_window = true;
-}
-
-static void gyro_cal_initialization_for_test(struct gyro_cal *gyro_cal)
-{
-	/* GyroCal initialization. */
-	memset(gyro_cal, 0, sizeof(struct gyro_cal));
-
-	/*
-	 * Initialize the stillness detectors.
-	 * Gyro parameter input units are [rad/sec].
-	 * Accel parameter input units are [m/sec^2].
-	 * Magnetometer parameter input units are [uT].
-	 */
-	gyro_still_det_initialization_for_test(&gyro_cal->gyro_stillness_detect,
-					       /* var_threshold */ 5e-5f,
-					       /* confidence_delta */ 1e-5f);
-	gyro_still_det_initialization_for_test(
-		&gyro_cal->accel_stillness_detect,
-		/* var_threshold */ 8e-3f,
-		/* confidence_delta */ 1.6e-3f);
-	gyro_still_det_initialization_for_test(&gyro_cal->mag_stillness_detect,
-					       /* var_threshold */ 1.4f,
-					       /* confidence_delta */ 0.25f);
-
-	/* Reset stillness flag and start timestamp. */
-	gyro_cal->prev_still = false;
-	gyro_cal->start_still_time_us = 0;
-
-	/* Set the min and max window stillness duration. */
-	gyro_cal->min_still_duration_us = 5 * SECOND;
-	gyro_cal->max_still_duration_us = 6 * SECOND;
-
-	/* Sets the duration of the stillness processing windows. */
-	gyro_cal->window_time_duration_us = 1500000;
-
-	/* Set the window timeout duration. */
-	gyro_cal->gyro_window_timeout_duration_us = 5 * SECOND;
-
-	/* Load the last valid cal from system memory. */
-	gyro_cal->bias_x = 0.0f; /* [rad/sec] */
-	gyro_cal->bias_y = 0.0f; /* [rad/sec] */
-	gyro_cal->bias_z = 0.0f; /* [rad/sec] */
-	gyro_cal->calibration_time_us = 0;
-
-	/* Set the stillness threshold required for gyro bias calibration. */
-	gyro_cal->stillness_threshold = 0.95f;
-
-	/*
-	 * Current window end-time used to assist in keeping sensor data
-	 * collection in sync. Setting this to zero signals that sensor data
-	 * will be dropped until a valid end-time is set from the first gyro
-	 * timestamp received.
-	 */
-	gyro_cal->stillness_win_endtime_us = 0;
-
-	/* Gyro calibrations will be applied (see, gyro_cal_remove_bias()). */
-	gyro_cal->gyro_calibration_enable = true;
-
-	/*
-	 * Sets the stability limit for the stillness window mean acceptable
-	 * delta.
-	 */
-	gyro_cal->stillness_mean_delta_limit = 50.0f * MDEG_TO_RAD;
-
-	/* Sets the min/max temperature delta limit for the stillness period. */
-	gyro_cal->temperature_delta_limit_kelvin = 1.5f;
-
-	/* Ensures that the data tracking functionality is reset. */
-	init_gyro_cal(gyro_cal);
-}
-
 /**
  * Tests that a calibration is updated after a period where the IMU device is
  * stationary. Accelerometer and gyroscope measurements are simulated with data
@@ -595,7 +496,7 @@ static int test_gyro_cal_remove_bias(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
@@ -609,3 +510,11 @@ void run_test(int argc, char **argv)
 
 	test_print_result();
 }
+
+/* Mock out mkbp_send_event. Rarely, but occasionally, mkbp_send_event gets
+ * called and the coverage is thrown off.
+ */
+int mkbp_send_event(uint8_t event_type)
+{
+	return 1;
+}
diff --git a/test/gyro_cal.tasklist b/test/gyro_cal.tasklist
index 7d28eb5b64..7209a7441e 100644
--- a/test/gyro_cal.tasklist
+++ b/test/gyro_cal.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/gyro_cal_init_for_test.c b/test/gyro_cal_init_for_test.c
new file mode 100644
index 0000000000..ebb1dd8799
--- /dev/null
+++ b/test/gyro_cal_init_for_test.c
@@ -0,0 +1,115 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "gyro_cal_init_for_test.h"
+#include "timer.h"
+
+#include <string.h>
+
+#define NANO_PI (3.14159265359f)
+/** Unit conversion: milli-degrees to radians. */
+#define MDEG_TO_RAD (NANO_PI / 180.0e3f)
+
+/**
+ *
+ * @param det              Pointer to the stillness detector
+ * @param var_threshold    The variance threshold in units^2
+ * @param confidence_delta The confidence delta in units^2
+ */
+static void gyro_still_det_initialization_for_test(struct gyro_still_det *det,
+						   float var_threshold,
+						   float confidence_delta)
+{
+	/* Clear all data structure variables to 0. */
+	memset(det, 0, sizeof(struct gyro_still_det));
+
+	/*
+	 * Set the delta about the variance threshold for calculation
+	 * of the stillness confidence score.
+	 */
+	if (confidence_delta < var_threshold)
+		det->confidence_delta = confidence_delta;
+	else
+		det->confidence_delta = var_threshold;
+
+	/*
+	 * Set the variance threshold parameter for the stillness
+	 * confidence score.
+	 */
+	det->var_threshold = var_threshold;
+
+	/* Signal to start capture of next stillness data window. */
+	det->start_new_window = true;
+}
+
+void gyro_cal_initialization_for_test(struct gyro_cal *gyro_cal)
+{
+	/* GyroCal initialization. */
+	memset(gyro_cal, 0, sizeof(struct gyro_cal));
+
+	/*
+	 * Initialize the stillness detectors.
+	 * Gyro parameter input units are [rad/sec].
+	 * Accel parameter input units are [m/sec^2].
+	 * Magnetometer parameter input units are [uT].
+	 */
+	gyro_still_det_initialization_for_test(&gyro_cal->gyro_stillness_detect,
+					       /* var_threshold */ 5e-5f,
+					       /* confidence_delta */ 1e-5f);
+	gyro_still_det_initialization_for_test(
+		&gyro_cal->accel_stillness_detect,
+		/* var_threshold */ 8e-3f,
+		/* confidence_delta */ 1.6e-3f);
+	gyro_still_det_initialization_for_test(&gyro_cal->mag_stillness_detect,
+					       /* var_threshold */ 1.4f,
+					       /* confidence_delta */ 0.25f);
+
+	/* Reset stillness flag and start timestamp. */
+	gyro_cal->prev_still = false;
+	gyro_cal->start_still_time_us = 0;
+
+	/* Set the min and max window stillness duration. */
+	gyro_cal->min_still_duration_us = 5 * SECOND;
+	gyro_cal->max_still_duration_us = 6 * SECOND;
+
+	/* Sets the duration of the stillness processing windows. */
+	gyro_cal->window_time_duration_us = 1500000;
+
+	/* Set the window timeout duration. */
+	gyro_cal->gyro_window_timeout_duration_us = 5 * SECOND;
+
+	/* Load the last valid cal from system memory. */
+	gyro_cal->bias_x = 0.0f; /* [rad/sec] */
+	gyro_cal->bias_y = 0.0f; /* [rad/sec] */
+	gyro_cal->bias_z = 0.0f; /* [rad/sec] */
+	gyro_cal->calibration_time_us = 0;
+
+	/* Set the stillness threshold required for gyro bias calibration. */
+	gyro_cal->stillness_threshold = 0.95f;
+
+	/*
+	 * Current window end-time used to assist in keeping sensor data
+	 * collection in sync. Setting this to zero signals that sensor data
+	 * will be dropped until a valid end-time is set from the first gyro
+	 * timestamp received.
+	 */
+	gyro_cal->stillness_win_endtime_us = 0;
+
+	/* Gyro calibrations will be applied (see, gyro_cal_remove_bias()). */
+	gyro_cal->gyro_calibration_enable = true;
+
+	/*
+	 * Sets the stability limit for the stillness window mean acceptable
+	 * delta.
+	 */
+	gyro_cal->stillness_mean_delta_limit = 50.0f * MDEG_TO_RAD;
+
+	/* Sets the min/max temperature delta limit for the stillness period. */
+	gyro_cal->temperature_delta_limit_kelvin = 1.5f;
+
+	/* Ensures that the data tracking functionality is reset. */
+	init_gyro_cal(gyro_cal);
+}
diff --git a/test/gyro_cal_init_for_test.h b/test/gyro_cal_init_for_test.h
new file mode 100644
index 0000000000..8af51b8e10
--- /dev/null
+++ b/test/gyro_cal_init_for_test.h
@@ -0,0 +1,39 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_GYRO_CAL_INIT_FOR_TEST
+#define __CROS_EC_GYRO_CAL_INIT_FOR_TEST
+
+#include "gyro_cal.h"
+#include "gyro_still_det.h"
+
+/**
+ * Initialization function used for testing the gyroscope calibration.
+ * This function will initialize to the following values:
+ * - Gyrscope stillness detector
+ *   - variance threshold:		5e-5
+ *   - confidence delta:		1e-5
+ * - Accelerometer stillness detector
+ *   - variance threshold:		8e-3
+ *   - confidence delta:		1.6e-3
+ * - Magnetometer stillness detector
+ *   - variance threshold:		1.4
+ *   - confidence delta:		2.5e-1
+ * - Minimum stillness duration:	5 seconds
+ * - Maximum stillness duration:	6 seconds
+ * - Window duration:			1.5 seconds
+ * - Window timeout duration:		5 seconds
+ * - Stillness threshold:		0.95
+ * - Stillness mean delta limit:	50 millidegrees
+ * - Temperature delta limit:		1.5K
+ *
+ * Once all the values are set, this function will call init_gyro_cal()
+ * to finish initializing/resetting the struct data.
+ *
+ * @param gyro_cal Pointer to the calibration data structure to initialize.
+ */
+void gyro_cal_initialization_for_test(struct gyro_cal *gyro_cal);
+
+#endif /* __CROS_EC_GYRO_CAL_INIT_FOR_TEST */
diff --git a/test/hooks.c b/test/hooks.c
index 8d12494688..0913f257b3 100644
--- a/test/hooks.c
+++ b/test/hooks.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -41,7 +41,7 @@ static void tick2_hook(void)
 	tick_count_seen_by_tick2 = tick_hook_count;
 }
 /* tick2_hook() prio means it should be called after tick_hook() */
-DECLARE_HOOK(HOOK_TICK, tick2_hook, HOOK_PRIO_DEFAULT+1);
+DECLARE_HOOK(HOOK_TICK, tick2_hook, HOOK_PRIO_DEFAULT + 1);
 
 static void second_hook(void)
 {
@@ -62,9 +62,7 @@ static void non_deferred_func(void)
 	deferred_call_count++;
 }
 
-static const struct deferred_data non_deferred_func_data = {
-	non_deferred_func
-};
+static const struct deferred_data non_deferred_func_data = { non_deferred_func };
 
 static int test_init_hook(void)
 {
@@ -85,8 +83,7 @@ static int test_ticks(void)
 	usleep(1300 * MSEC);
 
 	interval = tick_time[1].val - tick_time[0].val;
-	error_pct = (interval - HOOK_TICK_INTERVAL) * 100 /
-		    HOOK_TICK_INTERVAL;
+	error_pct = (interval - HOOK_TICK_INTERVAL) * 100 / HOOK_TICK_INTERVAL;
 	TEST_ASSERT_ABS_LESS(error_pct, 10);
 
 	interval = second_time[1].val - second_time[0].val;
@@ -159,7 +156,7 @@ static int test_repeating_deferred(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/hooks.tasklist b/test/hooks.tasklist
index da0ab6211a..100cb6b5bd 100644
--- a/test/hooks.tasklist
+++ b/test/hooks.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/host_command.c b/test/host_command.c
index ba1d4dcd96..e88ddc852c 100644
--- a/test/host_command.c
+++ b/test/host_command.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,6 +8,7 @@
 #include "common.h"
 #include "console.h"
 #include "host_command.h"
+#include "printf.h"
 #include "task.h"
 #include "test_util.h"
 #include "timer.h"
@@ -177,6 +178,7 @@ static int test_hostcmd_reuse_response_buffer(void)
 	struct ec_host_request *h = (struct ec_host_request *)resp_buf;
 	struct ec_params_hello *d =
 		(struct ec_params_hello *)(resp_buf + sizeof(*h));
+	char str_buf[hex_str_buf_size(BUFFER_SIZE)];
 
 	h->struct_version = 3;
 	h->checksum = 0;
@@ -201,16 +203,18 @@ static int test_hostcmd_reuse_response_buffer(void)
 
 	h->checksum = calculate_checksum(resp_buf, pkt.request_size);
 
-	ccprintf("\nBuffer contents before process 0x%ph\n",
-			HEX_BUF(resp_buf, BUFFER_SIZE));
+	snprintf_hex_buffer(str_buf, sizeof(str_buf),
+			    HEX_BUF(resp_buf, BUFFER_SIZE));
+	ccprintf("\nBuffer contents before process 0x%s\n", str_buf);
 	host_packet_receive(&pkt);
 	task_wait_event(-1);
 
-	ccprintf("\nBuffer contents after process 0x%ph\n",
-			HEX_BUF(resp_buf, BUFFER_SIZE));
+	snprintf_hex_buffer(str_buf, sizeof(str_buf),
+			    HEX_BUF(resp_buf, BUFFER_SIZE));
+	ccprintf("\nBuffer contents after process 0x%s\n", str_buf);
 
-	TEST_EQ(calculate_checksum(resp_buf,
-				sizeof(*resp) + resp->data_len), 0, "%d");
+	TEST_EQ(calculate_checksum(resp_buf, sizeof(*resp) + resp->data_len), 0,
+		"%d");
 	TEST_EQ(resp->result, EC_RES_SUCCESS, "%d");
 	TEST_EQ(r->out_data, 0x12243648, "0x%x");
 
@@ -239,6 +243,7 @@ static void hostcmd_fill_chip_info(void)
 static int test_hostcmd_clears_unused_data(void)
 {
 	int i, found_null;
+	char str_buf[hex_str_buf_size(BUFFER_SIZE)];
 
 	/* Set the buffer to junk and ensure that is gets cleared */
 	memset(resp_buf, 0xAA, BUFFER_SIZE);
@@ -246,11 +251,12 @@ static int test_hostcmd_clears_unused_data(void)
 
 	hostcmd_send();
 
-	ccprintf("\nBuffer contents 0x%ph\n",
-			HEX_BUF(resp_buf, BUFFER_SIZE));
+	snprintf_hex_buffer(str_buf, sizeof(str_buf),
+			    HEX_BUF(resp_buf, BUFFER_SIZE));
+	ccprintf("\nBuffer contents 0x%s\n", str_buf);
 
-	TEST_EQ(calculate_checksum(resp_buf,
-				sizeof(*resp) + resp->data_len), 0, "%d");
+	TEST_EQ(calculate_checksum(resp_buf, sizeof(*resp) + resp->data_len), 0,
+		"%d");
 	TEST_EQ(resp->result, EC_RES_SUCCESS, "%d");
 
 	/* Ensure partial strings have 0s after the NULL byte */
@@ -300,7 +306,7 @@ static int test_hostcmd_clears_unused_data(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	wait_for_task_started();
 	test_reset();
diff --git a/test/host_command.tasklist b/test/host_command.tasklist
index da0ab6211a..100cb6b5bd 100644
--- a/test/host_command.tasklist
+++ b/test/host_command.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/i2c_bitbang.c b/test/i2c_bitbang.c
index ab1136a922..6916110b5c 100644
--- a/test/i2c_bitbang.c
+++ b/test/i2c_bitbang.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,9 +10,11 @@
 #include "test_util.h"
 #include "util.h"
 
-const struct i2c_port_t i2c_bitbang_ports[] = {
-	{"", 0, 100, GPIO_I2C_SCL, GPIO_I2C_SDA}
-};
+const struct i2c_port_t i2c_bitbang_ports[] = { { .name = "",
+						  .port = 0,
+						  .kbps = 100,
+						  .scl = GPIO_I2C_SCL,
+						  .sda = GPIO_I2C_SDA } };
 const unsigned int i2c_bitbang_ports_used = 1;
 
 struct pin_state {
@@ -23,7 +25,7 @@ int history_count;
 
 void reset_state(void)
 {
-	history[0] = (struct pin_state) {1, 1};
+	history[0] = (struct pin_state){ 1, 1 };
 	history_count = 1;
 	bitbang_set_started(0);
 }
@@ -42,7 +44,7 @@ void gpio_set_level(enum gpio_signal signal, int level)
 		new.scl = level;
 
 	if (new.scl != history[history_count - 1].scl ||
-			new.sda != history[history_count - 1].sda)
+	    new.sda != history[history_count - 1].sda)
 		history[history_count++] = new;
 }
 
@@ -60,12 +62,12 @@ static int test_i2c_start_stop(void)
 {
 	struct pin_state expected[] = {
 		/* start */
-		{1, 1},
-		{1, 0},
-		{0, 0},
+		{ 1, 1 },
+		{ 1, 0 },
+		{ 0, 0 },
 		/* stop */
-		{1, 0},
-		{1, 1},
+		{ 1, 0 },
+		{ 1, 1 },
 	};
 	int i;
 
@@ -88,14 +90,14 @@ static int test_i2c_repeated_start(void)
 {
 	struct pin_state expected[] = {
 		/* start */
-		{1, 1},
-		{1, 0},
-		{0, 0},
+		{ 1, 1 },
+		{ 1, 0 },
+		{ 0, 0 },
 		/* repeated start */
-		{0, 1},
-		{1, 1},
-		{1, 0},
-		{0, 0},
+		{ 0, 1 },
+		{ 1, 1 },
+		{ 1, 0 },
+		{ 0, 0 },
 	};
 	int i;
 
@@ -118,47 +120,47 @@ static int test_i2c_write(void)
 {
 	struct pin_state expected[] = {
 		/* start */
-		{1, 1},
-		{1, 0},
-		{0, 0},
+		{ 1, 1 },
+		{ 1, 0 },
+		{ 0, 0 },
 		/* bit 7: 0 */
-		{1, 0},
-		{0, 0},
+		{ 1, 0 },
+		{ 0, 0 },
 		/* bit 6: 1 */
-		{0, 1},
-		{1, 1},
-		{0, 1},
+		{ 0, 1 },
+		{ 1, 1 },
+		{ 0, 1 },
 		/* bit 5: 0 */
-		{0, 0},
-		{1, 0},
-		{0, 0},
+		{ 0, 0 },
+		{ 1, 0 },
+		{ 0, 0 },
 		/* bit 4: 1 */
-		{0, 1},
-		{1, 1},
-		{0, 1},
+		{ 0, 1 },
+		{ 1, 1 },
+		{ 0, 1 },
 		/* bit 3: 0 */
-		{0, 0},
-		{1, 0},
-		{0, 0},
+		{ 0, 0 },
+		{ 1, 0 },
+		{ 0, 0 },
 		/* bit 2: 1 */
-		{0, 1},
-		{1, 1},
-		{0, 1},
+		{ 0, 1 },
+		{ 1, 1 },
+		{ 0, 1 },
 		/* bit 1: 1 */
-		{1, 1},
-		{0, 1},
+		{ 1, 1 },
+		{ 0, 1 },
 		/* bit 0: 0 */
-		{0, 0},
-		{1, 0},
-		{0, 0},
+		{ 0, 0 },
+		{ 1, 0 },
+		{ 0, 0 },
 		/* read bit */
-		{0, 1},
-		{1, 1},
-		{0, 1},
+		{ 0, 1 },
+		{ 1, 1 },
+		{ 0, 1 },
 		/* stop */
-		{0, 0},
-		{1, 0},
-		{1, 1},
+		{ 0, 0 },
+		{ 1, 0 },
+		{ 1, 1 },
 	};
 	int i, ret;
 
@@ -180,7 +182,7 @@ static int test_i2c_write(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/i2c_bitbang.tasklist b/test/i2c_bitbang.tasklist
index 9fc1a80f4d..844ddb6c10 100644
--- a/test/i2c_bitbang.tasklist
+++ b/test/i2c_bitbang.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/inductive_charging.c b/test/inductive_charging.c
index d487e171fd..a5b23d1d8c 100644
--- a/test/inductive_charging.c
+++ b/test/inductive_charging.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -17,8 +17,8 @@
 
 #define START_CHARGE_DELAY 5000 /* ms */
 #define MONITOR_CHARGE_DONE_DELAY 1000 /* ms */
-#define TEST_CHECK_CHARGE_DELAY (START_CHARGE_DELAY + \
-				 MONITOR_CHARGE_DONE_DELAY + 500) /* ms */
+#define TEST_CHECK_CHARGE_DELAY \
+	(START_CHARGE_DELAY + MONITOR_CHARGE_DONE_DELAY + 500) /* ms */
 
 static void wait_for_lid_debounce(void)
 {
@@ -157,7 +157,7 @@ static int test_debounce_charge_done(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/inductive_charging.tasklist b/test/inductive_charging.tasklist
index f5c894ccaf..dbe560d4aa 100644
--- a/test/inductive_charging.tasklist
+++ b/test/inductive_charging.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/interrupt.c b/test/interrupt.c
index ca98309e1f..fbd35253e8 100644
--- a/test/interrupt.c
+++ b/test/interrupt.c
@@ -1,11 +1,9 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Test interrupt support of EC emulator.
  */
-#include <stdio.h>
-
 #include "common.h"
 #include "console.h"
 #include "task.h"
@@ -13,6 +11,8 @@
 #include "timer.h"
 #include "util.h"
 
+#include <stdio.h>
+
 static int main_count;
 static int has_error;
 static int interrupt_count;
@@ -88,7 +88,7 @@ static int test_wait_for_ready(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/interrupt.tasklist b/test/interrupt.tasklist
index da0ab6211a..100cb6b5bd 100644
--- a/test/interrupt.tasklist
+++ b/test/interrupt.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/irq_locking.c b/test/irq_locking.c
new file mode 100644
index 0000000000..c46b94e8c5
--- /dev/null
+++ b/test/irq_locking.c
@@ -0,0 +1,83 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "task.h"
+#include "test_util.h"
+
+static uint32_t interrupt_disable_count;
+static uint32_t interrupt_enable_count;
+
+/** Mock implementation of interrupt_disable. */
+void interrupt_disable(void)
+{
+	++interrupt_disable_count;
+}
+
+/** Mock implementation of interrupt_enable. */
+void interrupt_enable(void)
+{
+	++interrupt_enable_count;
+}
+
+static int test_simple_lock_unlock(void)
+{
+	uint32_t key = irq_lock();
+
+	irq_unlock(key);
+
+	TEST_EQ(interrupt_disable_count, 1, "%u");
+	TEST_EQ(interrupt_enable_count, 1, "%u");
+
+	return EC_SUCCESS;
+}
+
+static int test_unlock_when_all_keys_removed(void)
+{
+	uint32_t key0 = irq_lock();
+	uint32_t key1 = irq_lock();
+
+	TEST_EQ(interrupt_disable_count, 2, "%u");
+
+	irq_unlock(key1);
+
+	TEST_EQ(interrupt_enable_count, 0, "%u");
+
+	irq_unlock(key0);
+
+	TEST_EQ(interrupt_enable_count, 1, "%u");
+
+	return EC_SUCCESS;
+}
+
+static int test_unlock_from_root_key(void)
+{
+	uint32_t key0 = irq_lock();
+	uint32_t key1 = irq_lock();
+
+	TEST_NE(key0, key1, "%u");
+	TEST_EQ(interrupt_disable_count, 2, "%u");
+
+	irq_unlock(key0);
+	TEST_EQ(interrupt_enable_count, 1, "%u");
+
+	return EC_SUCCESS;
+}
+
+void before_test(void)
+{
+	interrupt_disable_count = 0;
+	interrupt_enable_count = 0;
+}
+
+void run_test(int argc, const char **argv)
+{
+	test_reset();
+
+	RUN_TEST(test_simple_lock_unlock);
+	RUN_TEST(test_unlock_when_all_keys_removed);
+	RUN_TEST(test_unlock_from_root_key);
+
+	test_print_result();
+}
diff --git a/test/irq_locking.tasklist b/test/irq_locking.tasklist
new file mode 100644
index 0000000000..5659b9033d
--- /dev/null
+++ b/test/irq_locking.tasklist
@@ -0,0 +1,9 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST /* No test task. */
diff --git a/test/is_enabled.c b/test/is_enabled.c
index fe93bafc31..d54f709bf9 100644
--- a/test/is_enabled.c
+++ b/test/is_enabled.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -7,8 +7,8 @@
 #include "common.h"
 #include "test_util.h"
 
-#undef	CONFIG_UNDEFINED
-#define	CONFIG_BLANK
+#undef CONFIG_UNDEFINED
+#define CONFIG_BLANK
 
 static int test_undef(void)
 {
@@ -24,7 +24,7 @@ static int test_blank(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/is_enabled.tasklist b/test/is_enabled.tasklist
index 5ffe662d01..2d4595f76a 100644
--- a/test/is_enabled.tasklist
+++ b/test/is_enabled.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/is_enabled_error.c b/test/is_enabled_error.c
index 3fcd80afe0..b5d6994c4d 100644
--- a/test/is_enabled_error.c
+++ b/test/is_enabled_error.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -7,7 +7,7 @@
 #include "common.h"
 #include "test_util.h"
 
-#define	CONFIG_VALUE		TEST_VALUE
+#define CONFIG_VALUE TEST_VALUE
 
 static int test_invalid_value(void)
 {
@@ -17,7 +17,7 @@ static int test_invalid_value(void)
 	return EC_ERROR_UNKNOWN;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/is_enabled_error.sh b/test/is_enabled_error.sh
index 1e5407f31f..c99c4f0e26 100644
--- a/test/is_enabled_error.sh
+++ b/test/is_enabled_error.sh
@@ -1,5 +1,5 @@
 #!/bin/bash -e
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/test/is_enabled_error.tasklist b/test/is_enabled_error.tasklist
index 5ffe662d01..2d4595f76a 100644
--- a/test/is_enabled_error.tasklist
+++ b/test/is_enabled_error.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/kasa.c b/test/kasa.c
index 3ecd32a556..222fb2a0cf 100644
--- a/test/kasa.c
+++ b/test/kasa.c
@@ -1,12 +1,13 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "common.h"
 #include "kasa.h"
-#include "test_util.h"
 #include "motion_sense.h"
+#include "test_util.h"
+
 #include <stdio.h>
 
 struct motion_sensor_t motion_sensors[] = {};
@@ -62,7 +63,7 @@ static int test_kasa_calculate(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
@@ -71,3 +72,11 @@ void run_test(int argc, char **argv)
 
 	test_print_result();
 }
+
+/* Mock out mkbp_send_event. Rarely, but occasionally, mkbp_send_event gets
+ * called and the coverage is thrown off.
+ */
+int mkbp_send_event(uint8_t event_type)
+{
+	return 1;
+}
diff --git a/test/kasa.tasklist b/test/kasa.tasklist
index 0e3696c3f0..d3fcf83121 100644
--- a/test/kasa.tasklist
+++ b/test/kasa.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/kb_8042.c b/test/kb_8042.c
index 9705b506fe..00b70cdea6 100644
--- a/test/kb_8042.c
+++ b/test/kb_8042.c
@@ -1,10 +1,11 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Tests for keyboard MKBP protocol
  */
 
+#include "atkbd_protocol.h"
 #include "common.h"
 #include "console.h"
 #include "ec_commands.h"
@@ -15,16 +16,30 @@
 #include "keyboard_scan.h"
 #include "lpc.h"
 #include "power_button.h"
+#include "queue.h"
 #include "system.h"
+#include "task.h"
 #include "test_util.h"
 #include "timer.h"
 #include "util.h"
 
-static const char *action[2] = {"release", "press"};
+#include <stdbool.h>
 
-#define BUF_SIZE 16
-static char lpc_char_buf[BUF_SIZE];
-static unsigned int lpc_char_cnt;
+static const char *action[2] = { "release", "press" };
+
+/*
+ * This simulates the hardware output buffer. The x86 will read the output
+ * buffer from IOx60. Since we don't have actual hardware, we emulate the
+ * output buffer.
+ */
+static volatile struct {
+	bool full;
+	uint8_t data;
+	bool irq;
+	bool from_aux;
+} output_buffer;
+
+static struct queue const aux_to_device = QUEUE_NULL(16, uint8_t);
 
 /*****************************************************************************/
 /* Mock functions */
@@ -34,97 +49,519 @@ int lid_is_open(void)
 	return 1;
 }
 
+int lpc_keyboard_has_char(void)
+{
+	return output_buffer.full;
+}
+
 void lpc_keyboard_put_char(uint8_t chr, int send_irq)
 {
-	lpc_char_buf[lpc_char_cnt++] = chr;
+	if (lpc_keyboard_has_char()) {
+		ccprintf("%s:%s ERROR: output buffer is full!\n", __FILE__,
+			 __func__);
+		/* We can't fail the test, but we can abort!. */
+		exit(1);
+	}
+
+	output_buffer.data = chr;
+	output_buffer.irq = send_irq;
+	output_buffer.from_aux = false;
+	output_buffer.full = true;
 }
 
+void send_aux_data_to_device(uint8_t data)
+{
+	if (queue_add_unit(&aux_to_device, &data) == 0) {
+		ccprintf("%s: ERROR: aux_to_device queue is full!\n", __FILE__);
+		/* We can't fail the test, but we can abort!. */
+		exit(1);
+	}
+}
+
+void lpc_aux_put_char(uint8_t chr, int send_irq)
+{
+	if (lpc_keyboard_has_char()) {
+		ccprintf("%s:%s ERROR: output buffer is full!\n", __FILE__,
+			 __func__);
+		/* We can't fail the test, but we can abort!. */
+		exit(1);
+	}
+
+	output_buffer.data = chr;
+	output_buffer.irq = send_irq;
+	output_buffer.from_aux = true;
+	output_buffer.full = true;
+}
 /*****************************************************************************/
 /* Test utilities */
 
+/*
+ * This is a bit tricky, the second parameter to _Static_assert must be a string
+ * literal, so we use that property to assert x is a string literal.
+ */
+#define ASSERT_IS_STRING_LITERAL(x) _Static_assert(true, x)
+
+int _wait_for_data(int delay_ms)
+{
+	while (!output_buffer.full) {
+		if (delay_ms <= 0)
+			break;
+		delay_ms -= 1;
+
+		msleep(1);
+	}
+	TEST_ASSERT(output_buffer.full);
+
+	return EC_SUCCESS;
+}
+
+#define WAIT_FOR_DATA(d) TEST_EQ(_wait_for_data(d), EC_SUCCESS, "%d")
+
+#define VERIFY_LPC_CHAR_ALL(s, d, aux, _irq)                               \
+	do {                                                               \
+		const uint8_t *expected = s;                               \
+		ASSERT_IS_STRING_LITERAL(s);                               \
+		for (int _i = 0; _i < sizeof(s) - 1; ++_i) {               \
+			WAIT_FOR_DATA(d);                                  \
+			TEST_EQ(output_buffer.from_aux, aux, "%d");        \
+			if (_irq >= 0)                                     \
+				TEST_EQ(output_buffer.irq,                 \
+					_irq > 0 ? true : false, "%d");    \
+			TEST_EQ(output_buffer.data, expected[_i], "0x%x"); \
+			output_buffer.full = false;                        \
+			task_wake(TASK_ID_KEYPROTO);                       \
+		}                                                          \
+	} while (0)
+
+#define VERIFY_LPC_CHAR_DELAY(s, d)                    \
+	do {                                           \
+		msleep(d);                             \
+		VERIFY_LPC_CHAR_ALL(s, 10, false, -1); \
+	} while (0)
+#define VERIFY_LPC_CHAR(s) VERIFY_LPC_CHAR_ALL(s, 30, false, -1)
+#define VERIFY_ATKBD_ACK(s) VERIFY_LPC_CHAR("\xfa") /* ATKBD_RET_ACK */
+
+#define VERIFY_NO_CHAR()                              \
+	do {                                          \
+		msleep(30);                           \
+		TEST_EQ(output_buffer.full, 0, "%d"); \
+	} while (0)
+
+#define VERIFY_AUX_TO_HOST(expected_data, expected_irq) \
+	VERIFY_LPC_CHAR_ALL(expected_data, 30, true, expected_irq)
+
+#define VERIFY_AUX_TO_HOST_EMPTY VERIFY_NO_CHAR
+
+#define VERIFY_AUX_TO_DEVICE(expected_data)                                   \
+	do {                                                                  \
+		uint8_t _data;                                                \
+		msleep(30);                                                   \
+		TEST_EQ(queue_remove_unit(&aux_to_device, &_data), (size_t)1, \
+			"%zd");                                               \
+		TEST_EQ(_data, expected_data, "%#x");                         \
+	} while (0)
+
+#define VERIFY_AUX_TO_DEVICE_EMPTY()                         \
+	do {                                                 \
+		msleep(30);                                  \
+		TEST_ASSERT(queue_is_empty(&aux_to_device)); \
+	} while (0)
+
 static void press_key(int c, int r, int pressed)
 {
 	ccprintf("Input %s (%d, %d)\n", action[pressed], c, r);
 	keyboard_state_changed(r, c, pressed);
 }
 
-static void enable_keystroke(int enabled)
+static int _enable_keystroke(int enabled)
 {
-	uint8_t data = enabled ? I8042_CMD_ENABLE : I8042_CMD_RESET_DIS;
+	uint8_t data = enabled ? ATKBD_CMD_ENABLE : ATKBD_CMD_RESET_DIS;
 	keyboard_host_write(data, 0);
-	msleep(30);
+	VERIFY_ATKBD_ACK();
+
+	return EC_SUCCESS;
 }
+#define ENABLE_KEYSTROKE(enabled) \
+	TEST_EQ(_enable_keystroke(enabled), EC_SUCCESS, "%d")
 
-static void reset_8042(void)
+static int _reset_8042_def(void)
 {
-	keyboard_host_write(I8042_CMD_RESET_DEF, 0);
-	msleep(30);
+	keyboard_host_write(ATKBD_CMD_RESET_DEF, 0);
+	VERIFY_ATKBD_ACK();
+
+	return EC_SUCCESS;
 }
+#define RESET_8042_DEF() TEST_EQ(_reset_8042_def(), EC_SUCCESS, "%d")
 
-static void set_typematic(uint8_t val)
+static int _set_typematic(uint8_t val)
 {
-	keyboard_host_write(I8042_CMD_SETREP, 0);
-	msleep(30);
+	keyboard_host_write(ATKBD_CMD_SETREP, 0);
+	VERIFY_ATKBD_ACK();
+
 	keyboard_host_write(val, 0);
-	msleep(30);
+	VERIFY_ATKBD_ACK();
+
+	return EC_SUCCESS;
 }
+#define SET_TYPEMATIC(val) TEST_EQ(_set_typematic(val), EC_SUCCESS, "%d")
 
-static void set_scancode(uint8_t s)
+static int _set_scancode(uint8_t s)
 {
-	keyboard_host_write(I8042_CMD_SSCANSET, 0);
-	msleep(30);
+	keyboard_host_write(ATKBD_CMD_SSCANSET, 0);
+	VERIFY_ATKBD_ACK();
+
 	keyboard_host_write(s, 0);
-	msleep(30);
+	VERIFY_ATKBD_ACK();
+
+	return EC_SUCCESS;
 }
+#define SET_SCANCODE(s) TEST_EQ(_set_scancode(s), EC_SUCCESS, "%d")
 
-static void write_cmd_byte(uint8_t val)
+static int _write_cmd_byte(uint8_t val)
 {
 	keyboard_host_write(I8042_WRITE_CMD_BYTE, 1);
-	msleep(30);
+	VERIFY_NO_CHAR();
+
 	keyboard_host_write(val, 0);
-	msleep(30);
+	VERIFY_NO_CHAR();
+
+	return EC_SUCCESS;
 }
+#define WRITE_CMD_BYTE(val) TEST_EQ(_write_cmd_byte(val), EC_SUCCESS, "%d")
 
-static uint8_t read_cmd_byte(void)
+static int _read_cmd_byte(uint8_t *cmd)
 {
-	lpc_char_cnt = 0;
 	keyboard_host_write(I8042_READ_CMD_BYTE, 1);
-	msleep(30);
-	return lpc_char_buf[0];
+	WAIT_FOR_DATA(30);
+	TEST_EQ(output_buffer.from_aux, 0, "%d");
+
+	*cmd = output_buffer.data;
+	output_buffer.full = false;
+	task_wake(TASK_ID_KEYPROTO);
+
+	return EC_SUCCESS;
 }
+#define READ_CMD_BYTE()                                          \
+	({                                                       \
+		uint8_t cmd;                                     \
+		TEST_EQ(_read_cmd_byte(&cmd), EC_SUCCESS, "%d"); \
+		cmd;                                             \
+	})
+
+/*
+ * We unfortunately don't have an Input Buffer Full (IBF). Instead we
+ * directly write to the task's input queue. Ideally we would have an
+ * emulator that emulates the 8042 input/output buffers.
+ */
+#define i8042_write_cmd(cmd) keyboard_host_write(cmd, 1)
+#define i8042_write_data(data) keyboard_host_write(data, 0)
+
+/*****************************************************************************/
+/* Tests */
 
-static int __verify_lpc_char(char *arr, unsigned int sz, int delay_ms)
+void before_test(void)
 {
-	int i;
+	/* Make sure all tests start with the controller in the same state */
+	keyboard_clear_buffer();
+	_write_cmd_byte(I8042_XLATE | I8042_AUX_DIS | I8042_KBD_DIS);
+}
+
+void after_test(void)
+{
+	if (output_buffer.full) {
+		ccprintf("%s:%s ERROR: output buffer is not empty!\n", __FILE__,
+			 __func__);
+		/* We can't fail the test, but we can abort!. */
+		exit(1);
+	}
+}
+
+test_static int test_8042_aux_loopback(void)
+{
+	/* Disable all IRQs */
+	WRITE_CMD_BYTE(0);
+
+	i8042_write_cmd(I8042_ECHO_MOUSE);
+	i8042_write_data(0x01);
+	VERIFY_AUX_TO_HOST("\x01", 0);
+
+	/* Enable AUX IRQ */
+	WRITE_CMD_BYTE(I8042_ENIRQ12);
+
+	i8042_write_cmd(I8042_ECHO_MOUSE);
+	i8042_write_data(0x02);
+	VERIFY_AUX_TO_HOST("\x02", 1);
 
-	lpc_char_cnt = 0;
-	for (i = 0; i < sz; ++i)
-		lpc_char_buf[i] = 0;
-	msleep(delay_ms);
-	TEST_ASSERT_ARRAY_EQ(arr, lpc_char_buf, sz);
 	return EC_SUCCESS;
 }
 
-#define VERIFY_LPC_CHAR(s) \
-	TEST_ASSERT(__verify_lpc_char(s, strlen(s), 30) == EC_SUCCESS)
-#define VERIFY_LPC_CHAR_DELAY(s, t) \
-	TEST_ASSERT(__verify_lpc_char(s, strlen(s), t) == EC_SUCCESS)
+test_static int test_8042_aux_two_way_communication(void)
+{
+	/* Enable AUX IRQ */
+	WRITE_CMD_BYTE(I8042_ENIRQ12);
+
+	i8042_write_cmd(I8042_SEND_TO_MOUSE);
+	i8042_write_data(0x01);
+	/* No response expected from the 8042 controller*/
+	VERIFY_AUX_TO_HOST_EMPTY();
+	VERIFY_AUX_TO_DEVICE(0x01);
+
+	/* Simulate the AUX device sending a response to the host */
+	send_aux_data_to_host_interrupt(0x02);
+	VERIFY_AUX_TO_HOST("\x02", 1);
+
+	return EC_SUCCESS;
+}
 
-static int __verify_no_char(void)
+test_static int test_8042_aux_inhibit(void)
 {
-	lpc_char_cnt = 0;
-	msleep(30);
-	TEST_CHECK(lpc_char_cnt == 0);
+	/* Enable AUX IRQ, but inhibit the AUX device from sending data. */
+	WRITE_CMD_BYTE(I8042_ENIRQ12 | I8042_AUX_DIS);
+
+	/* Simulate the AUX device sending a response to the host */
+	send_aux_data_to_host_interrupt(0x02);
+	VERIFY_AUX_TO_HOST_EMPTY();
+
+	/* Stop inhibiting the AUX device */
+	WRITE_CMD_BYTE(I8042_ENIRQ12);
+	/*
+	 * This is wrong. When the CLK is inhibited the device will queue up
+	 * events/scan codes in it's internal buffer. Once the inhibit is
+	 * released, the device will start clocking out the data. So in this
+	 * test we should be receiving a 0x02 byte, but we don't.
+	 *
+	 * In order to fix this we either need to plumb an inhibit function
+	 * to the AUX PS/2 controller so it can hold the CLK line low, and thus
+	 * tell the AUX device to buffer. Or, we can have the 8042 controller
+	 * buffer the data internally and start replying it when the device is
+	 * no longer inhibited.
+	 */
+	VERIFY_AUX_TO_HOST_EMPTY();
+
+	return EC_SUCCESS;
 }
 
-#define VERIFY_NO_CHAR() TEST_ASSERT(__verify_no_char() == EC_SUCCESS)
+test_static int test_8042_aux_controller_commands(void)
+{
+	uint8_t ctrl;
 
-/*****************************************************************************/
-/* Tests */
+	/* Start with empty controller flags. i.e., AUX Enabled */
+	WRITE_CMD_BYTE(0);
+
+	/* Send the AUX DISABLE command and verify the ctrl got updated */
+	i8042_write_cmd(I8042_DIS_MOUSE);
+	ctrl = READ_CMD_BYTE();
+	TEST_ASSERT(ctrl & I8042_AUX_DIS);
+
+	/* Send the AUX ENABLE command and verify the ctrl got updated */
+	i8042_write_cmd(I8042_ENA_MOUSE);
+	ctrl = READ_CMD_BYTE();
+	TEST_ASSERT(!(ctrl & I8042_AUX_DIS));
+
+	return EC_SUCCESS;
+}
+
+test_static int test_8042_aux_test_command(void)
+{
+	i8042_write_cmd(I8042_TEST_MOUSE);
+
+	VERIFY_LPC_CHAR("\x00");
+
+	return EC_SUCCESS;
+}
+
+test_static int test_8042_self_test(void)
+{
+	i8042_write_cmd(I8042_RESET_SELF_TEST);
+	VERIFY_LPC_CHAR("\x55");
+
+	return EC_SUCCESS;
+}
+
+test_static int test_8042_keyboard_test_command(void)
+{
+	i8042_write_cmd(I8042_TEST_KB_PORT);
+	VERIFY_LPC_CHAR("\x00"); /* Data and Clock are not stuck */
+
+	return EC_SUCCESS;
+}
+
+test_static int test_8042_keyboard_controller_commands(void)
+{
+	uint8_t ctrl;
+
+	/* Start with empty controller flags. i.e., Keyboard Enabled */
+	WRITE_CMD_BYTE(0);
+
+	/* Send the Keyboard DISABLE command and verify the ctrl got updated */
+	i8042_write_cmd(I8042_DIS_KB);
+	ctrl = READ_CMD_BYTE();
+	TEST_ASSERT(ctrl & I8042_KBD_DIS);
+
+	/* Send the Keyboard ENABLE command and verify the ctrl got updated */
+	i8042_write_cmd(I8042_ENA_KB);
+	ctrl = READ_CMD_BYTE();
+	TEST_ASSERT(!(ctrl & I8042_KBD_DIS));
+
+	return EC_SUCCESS;
+}
 
-static int test_single_key_press(void)
+test_static int test_8042_keyboard_key_pressed_while_inhibited(void)
 {
-	enable_keystroke(1);
+	ENABLE_KEYSTROKE(1);
+
+	/* Inhibit the keyboard device from sending data. */
+	WRITE_CMD_BYTE(I8042_XLATE | I8042_KBD_DIS);
+
+	/* Simulate a keypress on the keyboard */
+	press_key(1, 1, 1);
+
+	/*
+	 * FIXME: This is wrong! We shouldn't be sending scan codes to the
+	 * host while the keyboard channel is inhibited. This should be
+	 * VERIFY_NO_CHAR();
+	 */
+	VERIFY_LPC_CHAR("\x01");
+
+	/* FIXME: This is also wrong for the same reason as above! */
+	press_key(1, 1, 0);
+	VERIFY_LPC_CHAR("\x81");
+
+	/* Stop inhibiting the keyboard */
+	WRITE_CMD_BYTE(0);
+
+	/*
+	 * FIXME: This is wrong. When the CLK is inhibited the device will queue
+	 * up events/scan codes in it's internal buffer. Once the inhibit is
+	 * released, the device will start clocking out the data. So in this
+	 * test we should be receiving the 0x01, and x81 here, but we received
+	 * them above.
+	 */
+	VERIFY_NO_CHAR();
+
+	return EC_SUCCESS;
+}
+
+test_static int
+test_8042_keyboard_key_pressed_before_inhibit_using_cmd_byte(void)
+{
+	ENABLE_KEYSTROKE(1);
+	/* Simulate a keypress on the keyboard */
+	press_key(1, 1, 1);
+	press_key(1, 1, 0);
+
+	/*
+	 * We should have a press scan code in the output buffer, and a
+	 * release scan code queued up in the keyboard queue.
+	 */
+	WAIT_FOR_DATA(30);
+
+	/* Inhibit the keyboard device from sending data. */
+	keyboard_host_write(I8042_WRITE_CMD_BYTE, 1);
+	keyboard_host_write(I8042_XLATE | I8042_KBD_DIS, 0);
+	/* Wait for controller to processes the command */
+	msleep(10);
+
+	/* Stop inhibiting the keyboard */
+	keyboard_host_write(I8042_WRITE_CMD_BYTE, 1);
+	keyboard_host_write(I8042_XLATE, 0);
+	/* Wait for controller to processes the command */
+	msleep(10);
+
+	/* Verify the scan codes from above */
+	VERIFY_LPC_CHAR("\x01");
+	VERIFY_LPC_CHAR("\x81");
+
+	return EC_SUCCESS;
+}
+
+test_static int
+test_8042_keyboard_key_pressed_before_inhibit_using_cmd_byte_with_read(void)
+{
+	uint8_t cmd;
+
+	ENABLE_KEYSTROKE(1);
+	/* Simulate a keypress on the keyboard */
+	press_key(1, 1, 1);
+	press_key(1, 1, 0);
+
+	/*
+	 * We should have a press scan code in the output buffer, and a
+	 * release scan code queued up in the keyboard queue.
+	 */
+	WAIT_FOR_DATA(30);
+
+	/* Inhibit the keyboard device from sending data. */
+	keyboard_host_write(I8042_WRITE_CMD_BYTE, 1);
+	keyboard_host_write(I8042_XLATE | I8042_KBD_DIS, 0);
+	/* Wait for controller to processes the command */
+	msleep(10);
+
+	/* Read the key press scan code from the output buffer. */
+	VERIFY_LPC_CHAR("\x01");
+
+	/*
+	 * With the keyboard output suppressed, we should be able to read from
+	 * the 8042 controller.
+	 */
+	cmd = READ_CMD_BYTE();
+
+	/* Verify we got the cmd byte we set above */
+	TEST_EQ(cmd, I8042_XLATE | I8042_KBD_DIS, "%d");
+
+	/* Stop inhibiting the keyboard */
+	keyboard_host_write(I8042_WRITE_CMD_BYTE, 1);
+	keyboard_host_write(I8042_XLATE, 0);
+	/* Wait for controller to processes the command */
+	msleep(10);
+
+	/* Verify the key release scan code from above */
+	/*
+	 * FIXME: This is wrong. We should receive the key release scan code
+	 * 0x81. Instead the `I8042_READ_CMD_BYTE` above cleared the keyboard's
+	 * output queue. It did this because the 8042 and keyboard output queues
+	 * are implemented as the same thing.
+	 */
+	VERIFY_NO_CHAR();
+
+	return EC_SUCCESS;
+}
+
+test_static int test_8042_keyboard_key_pressed_before_inhibit_using_cmd(void)
+{
+	ENABLE_KEYSTROKE(1);
+	/* Simulate a keypress on the keyboard */
+	press_key(1, 1, 1);
+	press_key(1, 1, 0);
+
+	/*
+	 * We should have a press scan code in the output buffer, and a
+	 * release scan code queued up in the keyboard queue.
+	 */
+	WAIT_FOR_DATA(30);
+
+	/* Inhibit the keyboard device from sending data. */
+	keyboard_host_write(I8042_DIS_KB, 1);
+
+	/* Stop inhibiting the keyboard */
+	keyboard_host_write(I8042_ENA_KB, 1);
+
+	/* Verify the scan codes from above */
+	VERIFY_LPC_CHAR("\x01");
+	/*
+	 * FIXME: This is wrong. When the keyboard CLK is inhibited the keyboard
+	 * will queue up events/scan codes in it's internal buffer. Once the
+	 * inhibit is released, the keyboard will start clocking out the data.
+	 * So in this test we should be receiving 0x81, but the keyboard buffer
+	 * was cleared by the I8042_DIS_KB above.
+	 */
+	VERIFY_NO_CHAR();
+	return EC_SUCCESS;
+}
+
+test_static int test_single_key_press(void)
+{
+	ENABLE_KEYSTROKE(1);
 	press_key(1, 1, 1);
 	VERIFY_LPC_CHAR("\x01");
 	press_key(1, 1, 0);
@@ -138,9 +575,9 @@ static int test_single_key_press(void)
 	return EC_SUCCESS;
 }
 
-static int test_disable_keystroke(void)
+test_static int test_disable_keystroke(void)
 {
-	enable_keystroke(0);
+	ENABLE_KEYSTROKE(0);
 	press_key(1, 1, 1);
 	VERIFY_NO_CHAR();
 	press_key(1, 1, 0);
@@ -149,14 +586,14 @@ static int test_disable_keystroke(void)
 	return EC_SUCCESS;
 }
 
-static int test_typematic(void)
+test_static int test_typematic(void)
 {
-	enable_keystroke(1);
+	ENABLE_KEYSTROKE(1);
 
 	/*
 	 * 250ms delay, 8 chars / sec.
 	 */
-	set_typematic(0xf);
+	SET_TYPEMATIC(0xf);
 
 	press_key(1, 1, 1);
 	VERIFY_LPC_CHAR_DELAY("\x01\x01\x01\x01\x01", 650);
@@ -166,7 +603,7 @@ static int test_typematic(void)
 	/*
 	 * 500ms delay, 10.9 chars / sec.
 	 */
-	reset_8042();
+	RESET_8042_DEF();
 
 	press_key(1, 1, 1);
 	VERIFY_LPC_CHAR_DELAY("\x01\x01\x01", 650);
@@ -176,17 +613,243 @@ static int test_typematic(void)
 	return EC_SUCCESS;
 }
 
-static int test_scancode_set2(void)
+test_static int test_atkbd_get_scancode(void)
+{
+	SET_SCANCODE(1);
+
+	keyboard_host_write(ATKBD_CMD_GSCANSET, 0);
+	VERIFY_ATKBD_ACK();
+
+	/* Writing a 0 scan code will return the current scan code. */
+	keyboard_host_write(0, 0);
+	VERIFY_ATKBD_ACK();
+	VERIFY_LPC_CHAR("\x01");
+
+	SET_SCANCODE(2);
+
+	keyboard_host_write(ATKBD_CMD_GSCANSET, 0);
+	VERIFY_ATKBD_ACK();
+
+	/* Writing a 0 scan code will return the current scan code. */
+	keyboard_host_write(0, 0);
+	VERIFY_ATKBD_ACK();
+	VERIFY_LPC_CHAR("\x02");
+
+	return EC_SUCCESS;
+}
+
+test_static int test_atkbd_set_scancode_with_keystroke_disabled(void)
+{
+	ENABLE_KEYSTROKE(0);
+
+	SET_SCANCODE(1);
+
+	press_key(1, 1, 1);
+	VERIFY_NO_CHAR();
+
+	return EC_SUCCESS;
+}
+
+test_static int test_atkbd_set_scancode_with_key_press_before_set(void)
+{
+	ENABLE_KEYSTROKE(0);
+	ENABLE_KEYSTROKE(1);
+
+	/* Push data into the output buffer and keyboard queue */
+	press_key(1, 1, 1);
+	press_key(1, 1, 0);
+
+	/*
+	 * ATKBD_CMD_SSCANSET should cause the keyboard to stop scanning, flush
+	 * the keyboards output queue, and reset the typematic key.
+	 */
+	i8042_write_data(ATKBD_CMD_SSCANSET);
+	VERIFY_ATKBD_ACK();
+
+	/*
+	 * FIXME: This is wrong. The keyboard's output queue should have been
+	 * flushed when it received the `ATKBD_CMD_SSCANSET` command.
+	 */
+	VERIFY_LPC_CHAR("\x01\x81");
+
+	/* Finish setting scan code 1 */
+	i8042_write_data(1);
+	VERIFY_ATKBD_ACK();
+
+	/* Key scanning should be restored. */
+	press_key(1, 1, 1);
+	press_key(1, 1, 0);
+	VERIFY_LPC_CHAR("\x01\x81");
+
+	return EC_SUCCESS;
+}
+
+test_static int test_atkbd_set_scancode_with_key_press_during_set(void)
 {
-	set_scancode(2);
+	ENABLE_KEYSTROKE(1);
 
-	write_cmd_byte(read_cmd_byte() | I8042_XLATE);
+	/*
+	 * ATKBD_CMD_SSCANSET should cause the keyboard to stop scanning, flush
+	 * the keyboards output queue, and reset the typematic key.
+	 */
+	i8042_write_data(ATKBD_CMD_SSCANSET);
+	VERIFY_ATKBD_ACK();
+
+	/* These keypresses should be dropped. */
+	press_key(1, 1, 1);
+	press_key(1, 1, 0);
+	/*
+	 * FIXME: So this is wrong. scanning should be stopped while waiting
+	 * for the scan code to be sent.
+	 */
+	VERIFY_LPC_CHAR("\x01\x81");
+
+	/* Finish setting scan code 1 */
+	i8042_write_data(1);
+	VERIFY_ATKBD_ACK();
+
+	/* Key scanning should be restored. */
+	press_key(1, 1, 1);
+	press_key(1, 1, 0);
+	VERIFY_LPC_CHAR("\x01\x81");
+
+	return EC_SUCCESS;
+}
+
+test_static int test_atkbd_echo(void)
+{
+	i8042_write_data(ATKBD_CMD_DIAG_ECHO);
+	VERIFY_ATKBD_ACK();
+
+	VERIFY_LPC_CHAR("\xee");
+
+	return EC_SUCCESS;
+}
+
+test_static int test_atkbd_get_id(void)
+{
+	i8042_write_data(ATKBD_CMD_GETID);
+	VERIFY_ATKBD_ACK();
+
+	VERIFY_LPC_CHAR("\xab\x83");
+
+	i8042_write_data(ATKBD_CMD_OK_GETID);
+	VERIFY_ATKBD_ACK();
+
+	VERIFY_LPC_CHAR("\xab\x83");
+
+	return EC_SUCCESS;
+}
+
+test_static int test_atkbd_set_leds_keypress_during(void)
+{
+	ENABLE_KEYSTROKE(1);
+
+	/* This should pause scanning. */
+	i8042_write_data(ATKBD_CMD_SETLEDS);
+	VERIFY_ATKBD_ACK();
+
+	/* Simulate keypress while keyboard is waiting for option byte */
+	press_key(1, 1, 1);
+	press_key(1, 1, 0);
+
+	/* Scancode is kept in queue during SETLEDS. */
+	msleep(15);
+	TEST_EQ(output_buffer.full, 0, "%d");
+
+	/* 2nd byte arrives (before timer expires) */
+	i8042_write_data(0x01);
+	VERIFY_ATKBD_ACK();
+
+	/* Scancode previously queued should be sent now. */
+	VERIFY_LPC_CHAR("\x01\x81");
+
+	return EC_SUCCESS;
+}
+
+test_static int test_atkbd_set_leds_keypress_timeout(void)
+{
+	ENABLE_KEYSTROKE(1);
+
+	/* This should pause scanning. */
+	i8042_write_data(ATKBD_CMD_SETLEDS);
+	VERIFY_ATKBD_ACK();
+
+	/* Simulate keypress while keyboard is waiting for option byte */
+	press_key(1, 1, 1);
+	press_key(1, 1, 0);
+
+	/* Scancode is kept in queue during SETLEDS. */
+	msleep(15);
+	TEST_EQ(output_buffer.full, 0, "%d");
+
+	/* Further wait until timer expires. */
+	msleep(15);
+
+	/* Scancode previously queued should be sent now. */
+	VERIFY_LPC_CHAR("\x01\x81");
+
+	return EC_SUCCESS;
+}
+
+test_static int test_atkbd_set_leds_abort_set(void)
+{
+	i8042_write_data(ATKBD_CMD_SETLEDS);
+	VERIFY_ATKBD_ACK();
+
+	/*
+	 * The spec says if we send a command instead of the option byte, the
+	 * keyboard will abort the SETLEDS command and processes the new
+	 * command. The way we can differentiate between a command and the
+	 * option byte is the option byte must have the top 5 bits set to 0.
+	 */
+	i8042_write_data(ATKBD_CMD_DIAG_ECHO);
+	VERIFY_ATKBD_ACK();
+
+	/* FIXME: This is wrong. We are expecting the 0xee echo byte. */
+	VERIFY_NO_CHAR();
+
+	return EC_SUCCESS;
+}
+
+test_static int test_atkbd_set_ex_leds(void)
+{
+	i8042_write_data(ATKBD_CMD_EX_SETLEDS);
+	VERIFY_ATKBD_ACK();
+
+	/* The extra set led command expects two option bytes. */
+
+	i8042_write_data(0x1);
+	VERIFY_ATKBD_ACK();
+
+	i8042_write_data(0x2);
+	VERIFY_ATKBD_ACK();
+
+	return EC_SUCCESS;
+}
+
+test_static int test_atkbd_reset(void)
+{
+	i8042_write_data(ATKBD_CMD_RESET);
+	VERIFY_ATKBD_ACK();
+	/* Successful BAT self-test */
+	VERIFY_LPC_CHAR("\xAA");
+
+	return EC_SUCCESS;
+}
+
+test_static int test_scancode_set2(void)
+{
+	SET_SCANCODE(2);
+	ENABLE_KEYSTROKE(1);
+
+	WRITE_CMD_BYTE(READ_CMD_BYTE() | I8042_XLATE);
 	press_key(1, 1, 1);
 	VERIFY_LPC_CHAR("\x01");
 	press_key(1, 1, 0);
 	VERIFY_LPC_CHAR("\x81");
 
-	write_cmd_byte(read_cmd_byte() & ~I8042_XLATE);
+	WRITE_CMD_BYTE(READ_CMD_BYTE() & ~I8042_XLATE);
 	press_key(1, 1, 1);
 	VERIFY_LPC_CHAR("\x76");
 	press_key(1, 1, 0);
@@ -195,10 +858,15 @@ static int test_scancode_set2(void)
 	return EC_SUCCESS;
 }
 
-static int test_power_button(void)
+test_static int test_power_button(void)
 {
+	ENABLE_KEYSTROKE(0);
+
 	gpio_set_level(GPIO_POWER_BUTTON_L, 1);
-	set_scancode(1);
+	msleep(100);
+
+	SET_SCANCODE(1);
+	ENABLE_KEYSTROKE(1);
 	test_chipset_on();
 
 	gpio_set_level(GPIO_POWER_BUTTON_L, 0);
@@ -207,8 +875,8 @@ static int test_power_button(void)
 	gpio_set_level(GPIO_POWER_BUTTON_L, 1);
 	VERIFY_LPC_CHAR_DELAY("\xe0\xde", 100);
 
-	set_scancode(2);
-	write_cmd_byte(read_cmd_byte() & ~I8042_XLATE);
+	SET_SCANCODE(2);
+	WRITE_CMD_BYTE(READ_CMD_BYTE() & ~I8042_XLATE);
 
 	gpio_set_level(GPIO_POWER_BUTTON_L, 0);
 	VERIFY_LPC_CHAR_DELAY("\xe0\x37", 100);
@@ -227,10 +895,10 @@ static int test_power_button(void)
 	return EC_SUCCESS;
 }
 
-static int test_sysjump(void)
+test_static int test_sysjump(void)
 {
-	set_scancode(2);
-	enable_keystroke(1);
+	SET_SCANCODE(2);
+	ENABLE_KEYSTROKE(1);
 
 	system_run_image_copy(EC_IMAGE_RW);
 
@@ -238,15 +906,17 @@ static int test_sysjump(void)
 	return EC_ERROR_UNKNOWN;
 }
 
-static int test_sysjump_cont(void)
+test_static int test_sysjump_cont(void)
 {
-	write_cmd_byte(read_cmd_byte() | I8042_XLATE);
+	WRITE_CMD_BYTE(READ_CMD_BYTE() | I8042_XLATE);
+
 	press_key(1, 1, 1);
 	VERIFY_LPC_CHAR("\x01");
 	press_key(1, 1, 0);
 	VERIFY_LPC_CHAR("\x81");
 
-	write_cmd_byte(read_cmd_byte() & ~I8042_XLATE);
+	WRITE_CMD_BYTE(READ_CMD_BYTE() & ~I8042_XLATE);
+
 	press_key(1, 1, 1);
 	VERIFY_LPC_CHAR("\x76");
 	press_key(1, 1, 0);
@@ -255,7 +925,7 @@ static int test_sysjump_cont(void)
 	return EC_SUCCESS;
 }
 
-static const struct ec_response_keybd_config keybd_config = {
+test_static const struct ec_response_keybd_config keybd_config = {
 	.num_top_row_keys = 13,
 	.action_keys = {
 		TK_BACK,		/* T1 */
@@ -274,19 +944,19 @@ static const struct ec_response_keybd_config keybd_config = {
 	},
 };
 
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	return &keybd_config;
 }
 
-static int test_ec_cmd_get_keybd_config(void)
+test_static int test_ec_cmd_get_keybd_config(void)
 {
 	struct ec_response_keybd_config resp;
 	int rv;
 
-	rv = test_send_host_command(EC_CMD_GET_KEYBD_CONFIG, 0, NULL, 0,
-				    &resp, sizeof(resp));
+	rv = test_send_host_command(EC_CMD_GET_KEYBD_CONFIG, 0, NULL, 0, &resp,
+				    sizeof(resp));
 	if (rv != EC_RES_SUCCESS) {
 		ccprintf("Error: EC_CMD_GET_KEYBD_CONFIG cmd returns %d\n", rv);
 		return EC_ERROR_INVAL;
@@ -301,34 +971,63 @@ static int test_ec_cmd_get_keybd_config(void)
 	return EC_SUCCESS;
 }
 
-static int test_vivaldi_top_keys(void)
+test_static int test_vivaldi_top_keys(void)
 {
-	set_scancode(2);
+	SET_SCANCODE(2);
 
 	/* Test REFRESH key */
-	write_cmd_byte(read_cmd_byte() | I8042_XLATE);
-	press_key(2, 3, 1);		/* Press T2 */
-	VERIFY_LPC_CHAR("\xe0\x67");	/* Check REFRESH scancode in set-1 */
+	WRITE_CMD_BYTE(READ_CMD_BYTE() | I8042_XLATE);
+
+	press_key(2, 3, 1); /* Press T2 */
+	VERIFY_LPC_CHAR("\xe0\x67"); /* Check REFRESH scancode in set-1 */
 
 	/* Test SNAPSHOT key */
-	write_cmd_byte(read_cmd_byte() | I8042_XLATE);
-	press_key(4, 3, 1);		/* Press T2 */
-	VERIFY_LPC_CHAR("\xe0\x13");	/* Check SNAPSHOT scancode in set-1 */
+	WRITE_CMD_BYTE(READ_CMD_BYTE() | I8042_XLATE);
+
+	press_key(4, 3, 1); /* Press T2 */
+	VERIFY_LPC_CHAR("\xe0\x13"); /* Check SNAPSHOT scancode in set-1 */
 
 	/* Test VOL_UP key */
-	write_cmd_byte(read_cmd_byte() | I8042_XLATE);
-	press_key(5, 3, 1);		/* Press T2 */
-	VERIFY_LPC_CHAR("\xe0\x30");	/* Check VOL_UP scancode in set-1 */
+	WRITE_CMD_BYTE(READ_CMD_BYTE() | I8042_XLATE);
+
+	press_key(5, 3, 1); /* Press T2 */
+	VERIFY_LPC_CHAR("\xe0\x30"); /* Check VOL_UP scancode in set-1 */
 
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 	wait_for_task_started();
 
 	if (system_get_image_copy() == EC_IMAGE_RO) {
+		RUN_TEST(test_8042_aux_loopback);
+		RUN_TEST(test_8042_aux_two_way_communication);
+		RUN_TEST(test_8042_aux_inhibit);
+		RUN_TEST(test_8042_aux_controller_commands);
+		RUN_TEST(test_8042_aux_test_command);
+		RUN_TEST(test_8042_self_test);
+		RUN_TEST(test_8042_keyboard_test_command);
+		RUN_TEST(test_8042_keyboard_controller_commands);
+		RUN_TEST(test_8042_keyboard_key_pressed_while_inhibited);
+		RUN_TEST(
+			test_8042_keyboard_key_pressed_before_inhibit_using_cmd_byte);
+		RUN_TEST(
+			test_8042_keyboard_key_pressed_before_inhibit_using_cmd_byte_with_read);
+		RUN_TEST(
+			test_8042_keyboard_key_pressed_before_inhibit_using_cmd);
+		RUN_TEST(test_atkbd_get_scancode);
+		RUN_TEST(test_atkbd_set_scancode_with_keystroke_disabled);
+		RUN_TEST(test_atkbd_set_scancode_with_key_press_before_set);
+		RUN_TEST(test_atkbd_set_scancode_with_key_press_during_set);
+		RUN_TEST(test_atkbd_echo);
+		RUN_TEST(test_atkbd_get_id);
+		RUN_TEST(test_atkbd_set_leds_keypress_during);
+		RUN_TEST(test_atkbd_set_leds_keypress_timeout);
+		RUN_TEST(test_atkbd_set_leds_abort_set);
+		RUN_TEST(test_atkbd_set_ex_leds);
+		RUN_TEST(test_atkbd_reset);
 		RUN_TEST(test_single_key_press);
 		RUN_TEST(test_disable_keystroke);
 		RUN_TEST(test_typematic);
diff --git a/test/kb_8042.tasklist b/test/kb_8042.tasklist
index 8cd35e6145..4d74e3c269 100644
--- a/test/kb_8042.tasklist
+++ b/test/kb_8042.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/kb_mkbp.c b/test/kb_mkbp.c
index 6ab010807d..0bfd1e5a15 100644
--- a/test/kb_mkbp.c
+++ b/test/kb_mkbp.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,7 +19,7 @@
 static uint8_t state[KEYBOARD_COLS_MAX];
 static int ec_int_level;
 
-static const char *action[2] = {"release", "press"};
+static const char *action[2] = { "release", "press" };
 
 /*****************************************************************************/
 /* Mock functions */
@@ -43,7 +43,7 @@ int lid_is_open(void)
 /*****************************************************************************/
 /* Test utilities */
 
-#define FIFO_EMPTY()     (ec_int_level == 1)
+#define FIFO_EMPTY() (ec_int_level == 1)
 #define FIFO_NOT_EMPTY() (ec_int_level == 0)
 
 void clear_state(void)
@@ -65,13 +65,13 @@ int press_key(int c, int r, int pressed)
 {
 	ccprintf("Input %s (%d, %d)\n", action[pressed], c, r);
 	set_state(c, r, pressed);
-	return keyboard_fifo_add(state);
+	return mkbp_keyboard_add(state);
 }
 
 int verify_key(int c, int r, int pressed)
 {
 	struct host_cmd_handler_args args;
-	struct  ec_response_get_next_event event;
+	struct ec_response_get_next_event event;
 	int i;
 
 	args.version = 0;
@@ -104,7 +104,7 @@ int verify_key(int c, int r, int pressed)
 int verify_key_v2(int c, int r, int pressed, int expect_more)
 {
 	struct host_cmd_handler_args args;
-	struct  ec_response_get_next_event_v1 event;
+	struct ec_response_get_next_event_v1 event;
 	int i;
 
 	args.version = 2;
@@ -286,7 +286,7 @@ int fifo_underrun(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	ec_int_level = 1;
 	test_reset();
diff --git a/test/kb_mkbp.tasklist b/test/kb_mkbp.tasklist
index d84996c71c..a255779878 100644
--- a/test/kb_mkbp.tasklist
+++ b/test/kb_mkbp.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/kb_scan.c b/test/kb_scan.c
index e0ba11137d..031c972d0e 100644
--- a/test/kb_scan.c
+++ b/test/kb_scan.c
@@ -1,7 +1,7 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
- * Copyright 2013 Google Inc.
+ * Copyright 2013 Google LLC
  *
  * Tests for keyboard scan deghosting and debouncing.
  */
@@ -20,18 +20,27 @@
 #include "timer.h"
 #include "util.h"
 
-#define KEYDOWN_DELAY_MS     10
-#define KEYDOWN_RETRY        10
-#define NO_KEYDOWN_DELAY_MS  100
+#define KEYDOWN_DELAY_MS 10
+#define KEYDOWN_RETRY 10
+#define NO_KEYDOWN_DELAY_MS 100
 
-#define CHECK_KEY_COUNT(old, expected) \
-	do { \
+#define CHECK_KEY_COUNT(old, expected)                               \
+	do {                                                         \
 		if (verify_key_presses(old, expected) != EC_SUCCESS) \
-			return EC_ERROR_UNKNOWN; \
-		old = fifo_add_count; \
+			return EC_ERROR_UNKNOWN;                     \
+		old = fifo_add_count;                                \
 	} while (0)
 
+/* Emulated physical key state */
 static uint8_t mock_state[KEYBOARD_COLS_MAX];
+
+/* Snapshot of last known key state */
+static uint8_t key_state[KEYBOARD_COLS_MAX];
+
+/* Counters for key state changes (UP/DOWN) */
+static int key_state_change[KEYBOARD_COLS_MAX][KEYBOARD_ROWS];
+static int total_key_state_change;
+
 static int column_driven;
 static int fifo_add_count;
 static int lid_open;
@@ -77,9 +86,26 @@ int keyboard_raw_read_rows(void)
 	}
 }
 
-int keyboard_fifo_add(const uint8_t *buffp)
+int mkbp_keyboard_add(const uint8_t *buffp)
 {
+	int c, r;
+
 	fifo_add_count++;
+
+	for (c = 0; c < KEYBOARD_COLS_MAX; c++) {
+		uint8_t diff = key_state[c] ^ buffp[c];
+
+		for (r = 0; r < KEYBOARD_ROWS; r++) {
+			if (diff & BIT(r)) {
+				key_state_change[c][r]++;
+				total_key_state_change++;
+			}
+		}
+	}
+
+	/* Save a snapshot. */
+	memcpy(key_state, buffp, sizeof(key_state));
+
 	return EC_SUCCESS;
 }
 
@@ -95,19 +121,30 @@ void chipset_reset(void)
 }
 #endif
 
-#define mock_defined_key(k, p) mock_key(KEYBOARD_ROW_ ## k, \
-					KEYBOARD_COL_ ## k, \
-					p)
+#define mock_defined_key(k, p) mock_key(KEYBOARD_ROW_##k, KEYBOARD_COL_##k, p)
+
+#define mock_default_key(k, p) \
+	mock_key(KEYBOARD_DEFAULT_ROW_##k, KEYBOARD_DEFAULT_COL_##k, p)
 
 static void mock_key(int r, int c, int keydown)
 {
-	ccprintf("%s (%d, %d)\n", keydown ? "Pressing" : "Releasing", r, c);
+	ccprintf("  %s (%d, %d)\n", keydown ? "Pressing" : "Releasing", r, c);
 	if (keydown)
 		mock_state[c] |= (1 << r);
 	else
 		mock_state[c] &= ~(1 << r);
 }
 
+static void reset_key_state(void)
+{
+	memset(mock_state, 0, sizeof(mock_state));
+	memset(key_state, 0, sizeof(key_state));
+	memset(key_state_change, 0, sizeof(key_state_change));
+	task_wake(TASK_ID_KEYSCAN);
+	msleep(NO_KEYDOWN_DELAY_MS);
+	total_key_state_change = 0;
+}
+
 static int expect_keychange(void)
 {
 	int old_count = fifo_add_count;
@@ -160,6 +197,8 @@ static int verify_key_presses(int old, int expected)
 
 static int deghost_test(void)
 {
+	reset_key_state();
+
 	/* Test we can detect a keypress */
 	mock_key(1, 1, 1);
 	TEST_ASSERT(expect_keychange() == EC_SUCCESS);
@@ -201,11 +240,118 @@ static int deghost_test(void)
 	return EC_SUCCESS;
 }
 
+static int strict_debounce_test(void)
+{
+	reset_key_state();
+
+	ccprintf("Test key press & hold.\n");
+	mock_key(1, 1, 1);
+	TEST_EQ(expect_keychange(), EC_SUCCESS, "%d");
+	TEST_EQ(key_state_change[1][1], 1, "%d");
+	TEST_EQ(total_key_state_change, 1, "%d");
+	ccprintf("Pass.\n");
+
+	reset_key_state();
+
+	ccprintf("Test a short stroke.\n");
+	mock_key(1, 1, 1);
+	task_wake_then_sleep_1ms(TASK_ID_KEYSCAN);
+	mock_key(1, 1, 0);
+	task_wake_then_sleep_1ms(TASK_ID_KEYSCAN);
+	TEST_EQ(expect_no_keychange(), EC_SUCCESS, "%d");
+	TEST_EQ(key_state_change[1][1], 0, "%d");
+	ccprintf("Pass.\n");
+
+	reset_key_state();
+
+	ccprintf("Test ripples being suppressed.\n");
+	/* DOWN */
+	mock_key(1, 1, 1);
+	task_wake_then_sleep_1ms(TASK_ID_KEYSCAN);
+	mock_key(1, 1, 0);
+	task_wake_then_sleep_1ms(TASK_ID_KEYSCAN);
+	mock_key(1, 1, 1);
+	task_wake_then_sleep_1ms(TASK_ID_KEYSCAN);
+	TEST_EQ(expect_keychange(), EC_SUCCESS, "%d");
+	TEST_EQ(key_state_change[1][1], 1, "%d");
+	TEST_EQ(total_key_state_change, 1, "%d");
+	/* UP */
+	mock_key(1, 1, 0);
+	task_wake_then_sleep_1ms(TASK_ID_KEYSCAN);
+	mock_key(1, 1, 1);
+	task_wake_then_sleep_1ms(TASK_ID_KEYSCAN);
+	mock_key(1, 1, 0);
+	task_wake_then_sleep_1ms(TASK_ID_KEYSCAN);
+	TEST_EQ(expect_keychange(), EC_SUCCESS, "%d");
+	TEST_EQ(key_state_change[1][1], 2, "%d");
+	TEST_EQ(total_key_state_change, 2, "%d");
+	ccprintf("Pass.\n");
+
+	reset_key_state();
+
+	ccprintf("Test simultaneous strokes.\n");
+	mock_key(1, 1, 1);
+	mock_key(2, 1, 1);
+	task_wake_then_sleep_1ms(TASK_ID_KEYSCAN);
+	TEST_EQ(expect_keychange(), EC_SUCCESS, "%d");
+	TEST_EQ(key_state_change[1][1], 1, "%d");
+	TEST_EQ(key_state_change[1][2], 1, "%d");
+	TEST_EQ(total_key_state_change, 2, "%d");
+	ccprintf("Pass.\n");
+
+	reset_key_state();
+
+	ccprintf("Test simultaneous strokes in two columns.\n");
+	mock_key(1, 1, 1);
+	mock_key(1, 2, 1);
+	task_wake_then_sleep_1ms(TASK_ID_KEYSCAN);
+	TEST_EQ(expect_keychange(), EC_SUCCESS, "%d");
+	TEST_EQ(key_state_change[1][1], 1, "%d");
+	TEST_EQ(key_state_change[2][1], 1, "%d");
+	TEST_EQ(total_key_state_change, 2, "%d");
+	ccprintf("Pass.\n");
+
+	reset_key_state();
+
+	ccprintf("Test normal & short simultaneous strokes.\n");
+	mock_key(1, 1, 1);
+	task_wake_then_sleep_1ms(TASK_ID_KEYSCAN);
+	mock_key(2, 1, 1);
+	task_wake_then_sleep_1ms(TASK_ID_KEYSCAN);
+	mock_key(1, 1, 0);
+	task_wake_then_sleep_1ms(TASK_ID_KEYSCAN);
+	TEST_EQ(expect_keychange(), EC_SUCCESS, "%d");
+	TEST_EQ(key_state_change[1][1], 0, "%d");
+	TEST_EQ(key_state_change[1][2], 1, "%d");
+	TEST_EQ(total_key_state_change, 1, "%d");
+	ccprintf("Pass.\n");
+
+	reset_key_state();
+
+	ccprintf("Test normal & short simultaneous strokes in two columns.\n");
+	reset_key_state();
+	mock_key(1, 1, 1);
+	task_wake(TASK_ID_KEYSCAN);
+	mock_key(1, 2, 1);
+	task_wake(TASK_ID_KEYSCAN);
+	mock_key(1, 1, 0);
+	task_wake(TASK_ID_KEYSCAN);
+	TEST_EQ(expect_keychange(), EC_SUCCESS, "%d");
+	TEST_EQ(key_state_change[1][1], 0, "%d");
+	TEST_EQ(key_state_change[2][1], 1, "%d");
+	TEST_EQ(total_key_state_change, 1, "%d");
+	ccprintf("Pass.\n");
+
+	return EC_SUCCESS;
+}
+
 static int debounce_test(void)
 {
 	int old_count = fifo_add_count;
 	int i;
 
+	reset_key_state();
+
 	/* One brief keypress is detected. */
 	msleep(40);
 	mock_key(1, 1, 1);
@@ -254,7 +400,7 @@ static int debounce_test(void)
 	 * Push down each subsequent key, until all 8 are pressed, each
 	 * time bouncing the former one once.
 	 */
-	for (i = 1 ; i < 8; i++) {
+	for (i = 1; i < 8; i++) {
 		mock_key(i, 1, 1);
 		task_wake(TASK_ID_KEYSCAN);
 		msleep(3);
@@ -289,6 +435,8 @@ static int simulate_key_test(void)
 {
 	int old_count;
 
+	reset_key_state();
+
 	task_wake(TASK_ID_KEYSCAN);
 	msleep(40); /* Wait for debouncing to settle */
 
@@ -328,23 +476,25 @@ static int verify_variable_not_set(int *var)
 
 static int runtime_key_test(void)
 {
+	reset_key_state();
+
 	/* Alt-VolUp-H triggers system hibernation */
 	mock_defined_key(LEFT_ALT, 1);
-	mock_defined_key(VOL_UP, 1);
+	mock_default_key(VOL_UP, 1);
 	mock_defined_key(KEY_H, 1);
 	TEST_ASSERT(wait_variable_set(&hibernated) == EC_SUCCESS);
 	mock_defined_key(LEFT_ALT, 0);
-	mock_defined_key(VOL_UP, 0);
+	mock_default_key(VOL_UP, 0);
 	mock_defined_key(KEY_H, 0);
 	TEST_ASSERT(expect_keychange() == EC_SUCCESS);
 
 	/* Alt-VolUp-R triggers chipset reset */
 	mock_defined_key(RIGHT_ALT, 1);
-	mock_defined_key(VOL_UP, 1);
+	mock_default_key(VOL_UP, 1);
 	mock_defined_key(KEY_R, 1);
 	TEST_ASSERT(wait_variable_set(&reset_called) == EC_SUCCESS);
 	mock_defined_key(RIGHT_ALT, 0);
-	mock_defined_key(VOL_UP, 0);
+	mock_default_key(VOL_UP, 0);
 	mock_defined_key(KEY_R, 0);
 	TEST_ASSERT(expect_keychange() == EC_SUCCESS);
 
@@ -352,10 +502,10 @@ static int runtime_key_test(void)
 	mock_defined_key(LEFT_ALT, 1);
 	mock_defined_key(KEY_H, 1);
 	mock_defined_key(KEY_R, 1);
-	mock_defined_key(VOL_UP, 1);
+	mock_default_key(VOL_UP, 1);
 	TEST_ASSERT(verify_variable_not_set(&hibernated) == EC_SUCCESS);
 	TEST_ASSERT(verify_variable_not_set(&reset_called) == EC_SUCCESS);
-	mock_defined_key(VOL_UP, 0);
+	mock_default_key(VOL_UP, 0);
 	mock_defined_key(KEY_R, 0);
 	mock_defined_key(KEY_H, 0);
 	mock_defined_key(LEFT_ALT, 0);
@@ -368,6 +518,8 @@ static int runtime_key_test(void)
 #ifdef CONFIG_LID_SWITCH
 static int lid_test(void)
 {
+	reset_key_state();
+
 	msleep(40); /* Allow debounce to settle */
 
 	lid_open = 0;
@@ -392,23 +544,27 @@ static int lid_test(void)
 
 static int test_check_boot_esc(void)
 {
-	TEST_CHECK(keyboard_scan_get_boot_keys() == BOOT_KEY_ESC);
+	TEST_ASSERT(keyboard_scan_get_boot_keys() == BOOT_KEY_ESC);
+	return EC_SUCCESS;
 }
 
 static int test_check_boot_down(void)
 {
-	TEST_CHECK(keyboard_scan_get_boot_keys() == BOOT_KEY_DOWN_ARROW);
+	TEST_ASSERT(keyboard_scan_get_boot_keys() == BOOT_KEY_DOWN_ARROW);
+	return EC_SUCCESS;
 }
 
 void test_init(void)
 {
-	uint32_t state = system_get_scratchpad();
+	uint32_t state;
+
+	system_get_scratchpad(&state);
 
 	if (state & TEST_STATE_MASK(TEST_STATE_STEP_2)) {
 		/* Power-F3-ESC */
 		system_set_reset_flags(system_get_reset_flags() |
 				       EC_RESET_FLAG_RESET_PIN);
-		mock_key(1, 1, 1);
+		mock_key(KEYBOARD_ROW_ESC, KEYBOARD_COL_ESC, 1);
 	} else if (state & TEST_STATE_MASK(TEST_STATE_STEP_3)) {
 		/* Power-F3-Down */
 		system_set_reset_flags(system_get_reset_flags() |
@@ -422,10 +578,17 @@ static void run_test_step1(void)
 	lid_open = 1;
 	hook_notify(HOOK_LID_CHANGE);
 	test_reset();
+	msleep(1);
 
 	RUN_TEST(deghost_test);
-	RUN_TEST(debounce_test);
-	RUN_TEST(simulate_key_test);
+
+	if (IS_ENABLED(CONFIG_KEYBOARD_STRICT_DEBOUNCE))
+		RUN_TEST(strict_debounce_test);
+	else
+		RUN_TEST(debounce_test);
+
+	if (0) /* crbug.com/976974 */
+		RUN_TEST(simulate_key_test);
 #ifdef EMU_BUILD
 	RUN_TEST(runtime_key_test);
 #endif
@@ -444,6 +607,7 @@ static void run_test_step2(void)
 	lid_open = 1;
 	hook_notify(HOOK_LID_CHANGE);
 	test_reset();
+	msleep(1);
 
 	RUN_TEST(test_check_boot_esc);
 
@@ -458,6 +622,7 @@ static void run_test_step3(void)
 	lid_open = 1;
 	hook_notify(HOOK_LID_CHANGE);
 	test_reset();
+	msleep(1);
 
 	RUN_TEST(test_check_boot_down);
 
@@ -483,7 +648,7 @@ int test_task(void *data)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	msleep(30); /* Wait for TASK_ID_TEST to initialize */
 	task_wake(TASK_ID_TEST);
diff --git a/test/kb_scan.tasklist b/test/kb_scan.tasklist
index ded03b1112..3cac36bb23 100644
--- a/test/kb_scan.tasklist
+++ b/test/kb_scan.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/kb_scan_strict.tasklist b/test/kb_scan_strict.tasklist
new file mode 120000
index 0000000000..d4d4fa1efb
--- /dev/null
+++ b/test/kb_scan_strict.tasklist
@@ -0,0 +1 @@
+kb_scan.tasklist
\ No newline at end of file
diff --git a/test/legacy_nvmem_dump.h b/test/legacy_nvmem_dump.h
index 6816673c23..401694d9d6 100644
--- a/test/legacy_nvmem_dump.h
+++ b/test/legacy_nvmem_dump.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,10 +12,10 @@
  * This binary dump is placed in a separate file not to free up the test file
  * using it.
  */
-	0x00, 0x65, 0x8e, 0x10, 0x80, 0xca, 0x52, 0x1e, 0x95, 0x81, 0x12, 0x4f,
-	0x36, 0x78, 0x9a, 0x34, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x10, 0xff, 0xff,
-	0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00,
+0x00, 0x65, 0x8e, 0x10, 0x80, 0xca, 0x52, 0x1e, 0x95, 0x81, 0x12, 0x4f, 0x36,
+	0x78, 0x9a, 0x34, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x10, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -32,12 +32,12 @@
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x63, 0x72, 0x6f, 0x73, 0x2d, 0x70,
-	0x61, 0x73, 0x73, 0x77, 0x6f, 0x72, 0x64, 0x00, 0xe1, 0xac, 0x01, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6b, 0x37, 0x01, 0x00,
-	0x03, 0x00, 0x00, 0x00, 0xbd, 0xfe, 0xff, 0xff, 0x85, 0xfc, 0x05, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0xb0, 0xde, 0x01, 0x00, 0xb4, 0xde, 0x01, 0x00,
-	0x9b, 0x0f, 0x06, 0x00, 0xbc, 0xde, 0x01, 0x00, 0x40, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x0d, 0x00, 0x63, 0x72, 0x6f, 0x73, 0x2d, 0x70, 0x61,
+	0x73, 0x73, 0x77, 0x6f, 0x72, 0x64, 0x00, 0xe1, 0xac, 0x01, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6b, 0x37, 0x01, 0x00, 0x03,
+	0x00, 0x00, 0x00, 0xbd, 0xfe, 0xff, 0xff, 0x85, 0xfc, 0x05, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0xb0, 0xde, 0x01, 0x00, 0xb4, 0xde, 0x01, 0x00, 0x9b,
+	0x0f, 0x06, 0x00, 0xbc, 0xde, 0x01, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -48,34 +48,33 @@
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
-	0x5b, 0x15, 0xa1, 0x0a, 0x05, 0x12, 0x58, 0x84, 0xbf, 0xf6, 0xc9, 0xf3,
-	0xdd, 0xb7, 0x26, 0xce, 0x56, 0x9e, 0x5f, 0x7a, 0xa8, 0xd4, 0x8a, 0x67,
-	0x5c, 0x26, 0x35, 0x0e, 0xb2, 0x13, 0x2c, 0x79, 0x20, 0x00, 0x26, 0xca,
-	0x7d, 0xb8, 0x1a, 0x1f, 0x0b, 0x5c, 0x0a, 0xf3, 0xb5, 0xe2, 0x6a, 0xec,
-	0x1a, 0x0d, 0x90, 0x8b, 0x92, 0x3c, 0x07, 0xb0, 0x41, 0xb0, 0x27, 0x20,
-	0x88, 0x33, 0xfe, 0x5c, 0xf2, 0x7b, 0x20, 0x00, 0x9e, 0xb7, 0xa2, 0x4c,
-	0xad, 0x6c, 0xc0, 0x92, 0x92, 0xef, 0xbc, 0x56, 0x65, 0x47, 0xf9, 0x09,
-	0xd1, 0xc4, 0xbc, 0x36, 0xe8, 0x3a, 0xc2, 0x8a, 0x11, 0x3a, 0xca, 0xe1,
-	0x66, 0xd7, 0x85, 0x57, 0x20, 0x00, 0x0c, 0x6d, 0xc7, 0x61, 0x92, 0xfc,
-	0x1b, 0x24, 0x02, 0xc1, 0x92, 0x0e, 0xf4, 0xa1, 0x75, 0xbe, 0xb1, 0x3d,
-	0x29, 0xfe, 0x1e, 0xe2, 0x65, 0xf5, 0x25, 0xae, 0xaf, 0xfe, 0x73, 0x32,
-	0x35, 0x75, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x5b,
+	0x15, 0xa1, 0x0a, 0x05, 0x12, 0x58, 0x84, 0xbf, 0xf6, 0xc9, 0xf3, 0xdd,
+	0xb7, 0x26, 0xce, 0x56, 0x9e, 0x5f, 0x7a, 0xa8, 0xd4, 0x8a, 0x67, 0x5c,
+	0x26, 0x35, 0x0e, 0xb2, 0x13, 0x2c, 0x79, 0x20, 0x00, 0x26, 0xca, 0x7d,
+	0xb8, 0x1a, 0x1f, 0x0b, 0x5c, 0x0a, 0xf3, 0xb5, 0xe2, 0x6a, 0xec, 0x1a,
+	0x0d, 0x90, 0x8b, 0x92, 0x3c, 0x07, 0xb0, 0x41, 0xb0, 0x27, 0x20, 0x88,
+	0x33, 0xfe, 0x5c, 0xf2, 0x7b, 0x20, 0x00, 0x9e, 0xb7, 0xa2, 0x4c, 0xad,
+	0x6c, 0xc0, 0x92, 0x92, 0xef, 0xbc, 0x56, 0x65, 0x47, 0xf9, 0x09, 0xd1,
+	0xc4, 0xbc, 0x36, 0xe8, 0x3a, 0xc2, 0x8a, 0x11, 0x3a, 0xca, 0xe1, 0x66,
+	0xd7, 0x85, 0x57, 0x20, 0x00, 0x0c, 0x6d, 0xc7, 0x61, 0x92, 0xfc, 0x1b,
+	0x24, 0x02, 0xc1, 0x92, 0x0e, 0xf4, 0xa1, 0x75, 0xbe, 0xb1, 0x3d, 0x29,
+	0xfe, 0x1e, 0xe2, 0x65, 0xf5, 0x25, 0xae, 0xaf, 0xfe, 0x73, 0x32, 0x35,
+	0x75, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
-	0x52, 0x01, 0x7b, 0x53, 0xc5, 0x95, 0xa0, 0x3a, 0x07, 0xd5, 0x62, 0x7f,
-	0xd3, 0x9c, 0x85, 0xaa, 0xfc, 0x56, 0xa0, 0xfa, 0x3a, 0xe8, 0x17, 0x38,
-	0xc3, 0x59, 0x65, 0xbe, 0x75, 0x1b, 0xdc, 0xdc, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x52,
+	0x01, 0x7b, 0x53, 0xc5, 0x95, 0xa0, 0x3a, 0x07, 0xd5, 0x62, 0x7f, 0xd3,
+	0x9c, 0x85, 0xaa, 0xfc, 0x56, 0xa0, 0xfa, 0x3a, 0xe8, 0x17, 0x38, 0xc3,
+	0x59, 0x65, 0xbe, 0x75, 0x1b, 0xdc, 0xdc, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x84, 0xe7, 0x7e, 0x46, 0xfe, 0xbd,
-	0x10, 0xdd, 0x5b, 0x09, 0xb2, 0xe2, 0xb1, 0x3f, 0xbf, 0x9a, 0xf3, 0xd7,
-	0xfb, 0xf7, 0x28, 0xbb, 0x24, 0x10, 0xa3, 0xf3, 0x18, 0xa4, 0xa2, 0x16,
-	0xd5, 0xea, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00,
+	0x00, 0x00, 0x00, 0x20, 0x00, 0x84, 0xe7, 0x7e, 0x46, 0xfe, 0xbd, 0x10,
+	0xdd, 0x5b, 0x09, 0xb2, 0xe2, 0xb1, 0x3f, 0xbf, 0x9a, 0xf3, 0xd7, 0xfb,
+	0xf7, 0x28, 0xbb, 0x24, 0x10, 0xa3, 0xf3, 0x18, 0xa4, 0xa2, 0x16, 0xd5,
+	0xea, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -86,15 +85,16 @@
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x04, 0x00, 0x00, 0x00, 0x04, 0x00, 0x03, 0xff, 0xff, 0xff, 0x0b, 0x00,
-	0x03, 0xff, 0xff, 0xff, 0x0c, 0x00, 0x03, 0xff, 0xff, 0xff, 0x0d, 0x00,
-	0x03, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8,
-	0x00, 0x00, 0x00, 0xe8, 0x03, 0x00, 0x00, 0xe8, 0x03, 0x00, 0x00, 0x01,
-	0x00, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
+	0x00, 0x00, 0x00, 0x04, 0x00, 0x03, 0xff, 0xff, 0xff, 0x0b, 0x00, 0x03,
+	0xff, 0xff, 0xff, 0x0c, 0x00, 0x03, 0xff, 0xff, 0xff, 0x0d, 0x00, 0x03,
+	0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x00,
+	0x00, 0x00, 0xe8, 0x03, 0x00, 0x00, 0xe8, 0x03, 0x00, 0x00, 0x01, 0x00,
+	0x00, 0x00, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
@@ -113,7 +113,7 @@
 	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff,
 	/* Manually added nonempty pcr. Array 0, index 0 */
 	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01, 0x02, 0x03, 0x04, 0x05, 0xff,
 	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
diff --git a/test/libc_printf.c b/test/libc_printf.c
new file mode 100644
index 0000000000..8900d9ea04
--- /dev/null
+++ b/test/libc_printf.c
@@ -0,0 +1,28 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "test_util.h"
+
+#include <stdio.h>
+
+test_static int test_printf(void)
+{
+	/*
+	 * The test itself is not verifying that printing works (according to
+	 * the test framework, this will always pass).
+	 *
+	 * Instead, the test runner (test/run_device_tests.py) looks for the
+	 * printed string in the test output to determine if the test passed.
+	 */
+	printf("printf called\n");
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
+{
+	test_reset();
+	RUN_TEST(test_printf);
+	test_print_result();
+}
diff --git a/test/libc_printf.tasklist b/test/libc_printf.tasklist
new file mode 100644
index 0000000000..959f62ef79
--- /dev/null
+++ b/test/libc_printf.tasklist
@@ -0,0 +1,9 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST
diff --git a/test/libcxx.cc b/test/libcxx.cc
new file mode 100644
index 0000000000..a88bd2fb85
--- /dev/null
+++ b/test/libcxx.cc
@@ -0,0 +1,36 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @brief Tests for functions in libc++ (libcxx).
+ */
+
+#include "test_util.h"
+
+extern "C" {
+#include "timer.h"
+}
+
+#include <chrono>
+
+static int test_system_clock()
+{
+	auto start = std::chrono::system_clock::now();
+	udelay(0.5 * SECOND);
+	auto end = std::chrono::system_clock::now();
+	auto elapsed_ms = std::chrono::duration_cast<std::chrono::milliseconds>(
+				  end - start)
+				  .count();
+	TEST_NEAR(elapsed_ms, 500ULL, 5ULL, "%llu");
+
+	return EC_SUCCESS;
+}
+
+extern "C" void run_test(int, const char **)
+{
+	test_reset();
+	RUN_TEST(test_system_clock);
+	test_print_result();
+}
diff --git a/test/libcxx.tasklist b/test/libcxx.tasklist
new file mode 100644
index 0000000000..35fa6f24bd
--- /dev/null
+++ b/test/libcxx.tasklist
@@ -0,0 +1,9 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST
diff --git a/test/lid_sw.c b/test/lid_sw.c
index 8163f74716..123676a1fa 100644
--- a/test/lid_sw.c
+++ b/test/lid_sw.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -83,7 +83,7 @@ static int test_debounce(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/lid_sw.tasklist b/test/lid_sw.tasklist
index da0ab6211a..100cb6b5bd 100644
--- a/test/lid_sw.tasklist
+++ b/test/lid_sw.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/lightbar.c b/test/lightbar.c
index 363d73a36b..d51b61779e 100644
--- a/test/lightbar.c
+++ b/test/lightbar.c
@@ -1,12 +1,12 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "console.h"
 #include "ec_commands.h"
-#include "lightbar.h"
 #include "host_command.h"
+#include "lightbar.h"
 #include "test_util.h"
 #include "timer.h"
 #include "util.h"
@@ -20,9 +20,8 @@ static int get_seq(void)
 	/* Get the state */
 	memset(&resp, 0, sizeof(resp));
 	params.cmd = LIGHTBAR_CMD_GET_SEQ;
-	rv = test_send_host_command(EC_CMD_LIGHTBAR_CMD, 0,
-				    &params, sizeof(params),
-				    &resp, sizeof(resp));
+	rv = test_send_host_command(EC_CMD_LIGHTBAR_CMD, 0, &params,
+				    sizeof(params), &resp, sizeof(resp));
 	if (rv != EC_RES_SUCCESS) {
 		ccprintf("%s:%s(): rv = %d\n", __FILE__, __func__, rv);
 		return -1;
@@ -41,9 +40,8 @@ static int set_seq(int s)
 	memset(&resp, 0, sizeof(resp));
 	params.cmd = LIGHTBAR_CMD_SEQ;
 	params.seq.num = s;
-	rv = test_send_host_command(EC_CMD_LIGHTBAR_CMD, 0,
-				    &params, sizeof(params),
-				    &resp, sizeof(resp));
+	rv = test_send_host_command(EC_CMD_LIGHTBAR_CMD, 0, &params,
+				    sizeof(params), &resp, sizeof(resp));
 	if (rv != EC_RES_SUCCESS) {
 		ccprintf("%s:%s(): rv = %d\n", __FILE__, __func__, rv);
 		return -1;
@@ -169,9 +167,8 @@ test_static int test_stop_timeout(void)
 		TEST_ASSERT(set_seq(i) == EC_RES_SUCCESS);
 		usleep(SECOND);
 		/* What happened? */
-		if (i == LIGHTBAR_RUN ||
-		    i == LIGHTBAR_S0S3 || i ==  LIGHTBAR_S3 ||
-		    i ==  LIGHTBAR_S3S5 || i ==  LIGHTBAR_S5)
+		if (i == LIGHTBAR_RUN || i == LIGHTBAR_S0S3 ||
+		    i == LIGHTBAR_S3 || i == LIGHTBAR_S3S5 || i == LIGHTBAR_S5)
 			/* RUN or shutdown sequences should stop it */
 			TEST_ASSERT(get_seq() == LIGHTBAR_S0);
 		else
@@ -290,7 +287,7 @@ const struct lb_brightness_def lb_brightness_levels[] = {
 	},
 };
 const unsigned int lb_brightness_levels_count =
-		ARRAY_SIZE(lb_brightness_levels);
+	ARRAY_SIZE(lb_brightness_levels);
 
 int lux_level_to_google_color(const int lux);
 extern int google_color_id;
@@ -303,8 +300,8 @@ int lid_is_open(void)
 test_static int test_als_lightbar(void)
 {
 	int lux_data[] = { 500, 100, 35, 15, 30, 35, 55, 70, 55, 100 };
-	int exp_gcid[] = {   0,   0,  1,  2,  2,  2,  1,  0,  0,   0 };
-	int exp_chg[]  = {   0,   0,  1,  1,  0,  0,  1,  1,  0,   0 };
+	int exp_gcid[] = { 0, 0, 1, 2, 2, 2, 1, 0, 0, 0 };
+	int exp_chg[] = { 0, 0, 1, 1, 0, 0, 1, 1, 0, 0 };
 	int i;
 
 	BUILD_ASSERT(ARRAY_SIZE(lux_data) == ARRAY_SIZE(exp_gcid));
@@ -319,7 +316,7 @@ test_static int test_als_lightbar(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	/* Ensure tasks are started before running tests */
 	usleep(SECOND);
diff --git a/test/lightbar.tasklist b/test/lightbar.tasklist
index b5e714765d..78c08cc652 100644
--- a/test/lightbar.tasklist
+++ b/test/lightbar.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/mag_cal.c b/test/mag_cal.c
index 8ee3b41480..fe98318258 100644
--- a/test/mag_cal.c
+++ b/test/mag_cal.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,6 +6,7 @@
 #include "common.h"
 #include "mag_cal.h"
 #include "test_util.h"
+
 #include <stdio.h>
 
 /**
@@ -17,35 +18,17 @@
  * the high values and [-5,5] (+- 1.53 uT) for the low values.
  */
 static intv3_t samples[] = {
-	{ -522, 5, -5 },
-	{ -528, -3, 1 },
-	{ -531, -2, 0 },
-	{ -525, -1, 3 },
-
-	{ 527, 3, -2 },
-	{ 523, -5, 1 },
-	{ 520, -3, 2 },
-	{ 522, 0, -4 },
-
-	{ -3, -519, -2 },
-	{ 1, -521, 5 },
-	{ 2, -526, 4 },
-	{ 0, -532, -5 },
-
-	{ -5, 528, 4 },
-	{ -2, 531, -4 },
-	{ 1, 522, 2 },
-	{ 5, 532, 3 },
-
-	{ -5, 0, -524 },
-	{ -1, -2, -527 },
-	{ -3, 4, -532 },
-	{ 5, 3, -531 },
-
-	{ 4, -2, 524 },
-	{ 1, 3, 520 },
-	{ 5, -5, 528 },
-	{ 0, 2, 521 },
+	{ -522, 5, -5 },  { -528, -3, 1 },  { -531, -2, 0 }, { -525, -1, 3 },
+
+	{ 527, 3, -2 },	  { 523, -5, 1 },   { 520, -3, 2 },  { 522, 0, -4 },
+
+	{ -3, -519, -2 }, { 1, -521, 5 },   { 2, -526, 4 },  { 0, -532, -5 },
+
+	{ -5, 528, 4 },	  { -2, 531, -4 },  { 1, 522, 2 },   { 5, 532, 3 },
+
+	{ -5, 0, -524 },  { -1, -2, -527 }, { -3, 4, -532 }, { 5, 3, -531 },
+
+	{ 4, -2, 524 },	  { 1, 3, 520 },    { 5, -5, 528 },  { 0, 2, 521 },
 };
 
 static int test_mag_cal_computes_bias(void)
@@ -81,7 +64,7 @@ static int test_mag_cal_computes_bias(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/mag_cal.tasklist b/test/mag_cal.tasklist
index ff715f69cd..a8b04538aa 100644
--- a/test/mag_cal.tasklist
+++ b/test/mag_cal.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/malloc.c b/test/malloc.c
new file mode 100644
index 0000000000..0a498acb82
--- /dev/null
+++ b/test/malloc.c
@@ -0,0 +1,119 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "shared_mem.h"
+#include "stdlib.h"
+#include "test_util.h"
+
+#include <malloc.h>
+
+struct malloc_data {
+	uint32_t size;
+	uint8_t val;
+	uint8_t *data;
+};
+
+static struct malloc_data test_data[] = {
+	{ .size = 15, .val = 1, .data = NULL },
+	{ .size = 1024, .val = 2, .data = NULL },
+	{ .size = 86096, .val = 3, .data = NULL }
+};
+
+test_static int test_malloc_different_sizes(void)
+{
+	/* Trim to make sure that previous tests haven't fragmented the heap. */
+	malloc_trim(0);
+
+	for (int i = 0; i < ARRAY_SIZE(test_data); i++) {
+		uint8_t *volatile ptr = malloc(test_data[i].size);
+		TEST_NE(ptr, NULL, "%p");
+		test_data[i].data = ptr;
+		for (int j = 0; j < test_data[i].size; j++) {
+			ptr[j] = test_data[i].val;
+		}
+	}
+
+	for (int i = 0; i < ARRAY_SIZE(test_data); i++) {
+		uint8_t *ptr = test_data[i].data;
+		/* Using TEST_EQ results in too much logging. */
+		for (int j = 0; j < test_data[i].size; j++) {
+			if (ptr[j] != test_data[i].val) {
+				TEST_ASSERT(false);
+			}
+		}
+	}
+
+	for (int i = 0; i < ARRAY_SIZE(test_data); i++) {
+		free(test_data[i].data);
+	}
+
+	return EC_SUCCESS;
+}
+
+test_static int test_free_null(void)
+{
+	free(NULL);
+	return EC_SUCCESS;
+}
+
+test_static int test_malloc_large(void)
+{
+	/* Trim to make sure that previous tests haven't fragmented the heap. */
+	malloc_trim(0);
+	uint8_t *volatile ptr = malloc(shared_mem_size() * 0.8);
+	TEST_NE(ptr, NULL, "%p");
+	free(ptr);
+	return EC_SUCCESS;
+}
+
+test_static int test_malloc_too_large(void)
+{
+	/* Trim to make sure that previous tests haven't fragmented the heap. */
+	malloc_trim(0);
+	uint8_t *volatile ptr = malloc(shared_mem_size() + 1);
+	TEST_EQ(ptr, NULL, "%p");
+	free(ptr);
+	return EC_SUCCESS;
+}
+
+/**
+ * Useful for manually testing the behavior of double frees.
+ *
+ * For example, if you compile the malloc implementation provided by newlib
+ * with the patch in https://crrev.com/c/4406822, you'll get something like:
+ *
+ * assertion "inuse(p)" failed: file "newlib/libc/stdlib/mallocr.c",
+ * line 1841, function: do_check_inuse_chunk
+ * _exit called with rc: 1
+ *
+ * If you run the host tests you'll get something like:
+ *
+ * free(): double free detected in tcache 2
+ * Aborted
+ */
+test_static int test_malloc_double_free(void)
+{
+	uint8_t *volatile ptr = malloc(10);
+	TEST_NE(ptr, NULL, "%p");
+	free(ptr);
+	free(ptr);
+
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
+{
+	test_reset();
+
+	RUN_TEST(test_free_null);
+	RUN_TEST(test_malloc_different_sizes);
+	RUN_TEST(test_malloc_large);
+
+	if (!IS_ENABLED(BOARD_HOST))
+		RUN_TEST(test_malloc_too_large);
+
+	test_print_result();
+}
diff --git a/test/malloc.tasklist b/test/malloc.tasklist
new file mode 100644
index 0000000000..d1920322a9
--- /dev/null
+++ b/test/malloc.tasklist
@@ -0,0 +1,9 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST
diff --git a/test/math_util.c b/test/math_util.c
index b45de1a29d..c08bd0c561 100644
--- a/test/math_util.c
+++ b/test/math_util.c
@@ -1,18 +1,19 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Test motion sense code.
  */
 
-#include <math.h>
-#include <stdio.h>
 #include "common.h"
 #include "math_util.h"
 #include "motion_sense.h"
 #include "test_util.h"
 #include "util.h"
 
+#include <math.h>
+#include <stdio.h>
+
 /*****************************************************************************/
 /*
  * Need to define motion sensor globals just to compile.
@@ -25,7 +26,7 @@ const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 /* Test utilities */
 
 /* Macro to compare two floats and check if they are equal within diff. */
-#define IS_FLOAT_EQUAL(a, b, diff) ((a) >= ((b) - diff) && (a) <= ((b) + diff))
+#define IS_FLOAT_EQUAL(a, b, diff) ((a) >= ((b)-diff) && (a) <= ((b) + diff))
 
 #define ACOS_TOLERANCE_DEG 0.5f
 #define RAD_TO_DEG (180.0f / 3.1415926f)
@@ -45,21 +46,19 @@ static int test_acos(void)
 	return EC_SUCCESS;
 }
 
-
 const mat33_fp_t test_matrices[] = {
-	{{ 0, FLOAT_TO_FP(-1), 0},
-	 {FLOAT_TO_FP(-1), 0, 0},
-	 { 0, 0, FLOAT_TO_FP(1)} },
-	{{ FLOAT_TO_FP(1), 0, FLOAT_TO_FP(5)},
-	 { FLOAT_TO_FP(2), FLOAT_TO_FP(1), FLOAT_TO_FP(6)},
-	 { FLOAT_TO_FP(3), FLOAT_TO_FP(4), 0} }
+	{ { 0, FLOAT_TO_FP(-1), 0 },
+	  { FLOAT_TO_FP(-1), 0, 0 },
+	  { 0, 0, FLOAT_TO_FP(1) } },
+	{ { FLOAT_TO_FP(1), 0, FLOAT_TO_FP(5) },
+	  { FLOAT_TO_FP(2), FLOAT_TO_FP(1), FLOAT_TO_FP(6) },
+	  { FLOAT_TO_FP(3), FLOAT_TO_FP(4), 0 } }
 };
 
-
 static int test_rotate(void)
 {
 	int i, j, k;
-	intv3_t v = {1, 2, 3};
+	intv3_t v = { 1, 2, 3 };
 	intv3_t w;
 
 	for (i = 0; i < ARRAY_SIZE(test_matrices); i++) {
@@ -78,12 +77,58 @@ static int test_rotate(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+test_static int test_round_divide(void)
+{
+	/* Check function version */
+	TEST_EQ(round_divide(10, 1), 10, "%d");
+	TEST_EQ(round_divide(10, 2), 5, "%d");
+	TEST_EQ(round_divide(10, 3), 3, "%d");
+	TEST_EQ(round_divide(10, 4), 3, "%d");
+	TEST_EQ(round_divide(10, 5), 2, "%d");
+	TEST_EQ(round_divide(10, 6), 2, "%d");
+	TEST_EQ(round_divide(10, 7), 1, "%d");
+	TEST_EQ(round_divide(10, 9), 1, "%d");
+	TEST_EQ(round_divide(10, 10), 1, "%d");
+	TEST_EQ(round_divide(10, 11), 1, "%d");
+	TEST_EQ(round_divide(10, 20), 1, "%d");
+	TEST_EQ(round_divide(10, 21), 0, "%d");
+
+	/* Check negative conditions */
+	TEST_EQ(round_divide(-10, 6), -2, "%d");
+	TEST_EQ(round_divide(10, -6), -2, "%d");
+	TEST_EQ(round_divide(-10, -6), 2, "%d");
+
+	return EC_SUCCESS;
+}
+
+test_static int test_temp_conversion(void)
+{
+	TEST_EQ(C_TO_K(100), 373, "%d");
+	TEST_EQ(K_TO_C(100), -173, "%d");
+
+	TEST_EQ((int)CELSIUS_TO_DECI_KELVIN(100), 3732, "%d");
+	TEST_EQ(DECI_KELVIN_TO_CELSIUS(100), -263, "%d");
+
+	TEST_EQ(MILLI_KELVIN_TO_MILLI_CELSIUS(100), -273050, "%d");
+	TEST_EQ(MILLI_CELSIUS_TO_MILLI_KELVIN(100), 273250, "%d");
+
+	TEST_EQ(MILLI_KELVIN_TO_KELVIN(5000), 5, "%d");
+	TEST_EQ(KELVIN_TO_MILLI_KELVIN(100), 100000, "%d");
+
+	TEST_EQ(CELSIUS_TO_MILLI_KELVIN(100), 373150, "%d");
+	TEST_EQ(MILLI_KELVIN_TO_CELSIUS(100), -273, "%d");
+
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
 	RUN_TEST(test_acos);
 	RUN_TEST(test_rotate);
+	RUN_TEST(test_round_divide);
+	RUN_TEST(test_temp_conversion);
 
 	test_print_result();
 }
diff --git a/test/math_util.tasklist b/test/math_util.tasklist
index f5c894ccaf..dbe560d4aa 100644
--- a/test/math_util.tasklist
+++ b/test/math_util.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/motion_angle.c b/test/motion_angle.c
index 06872a7a41..8eb1a775e4 100644
--- a/test/motion_angle.c
+++ b/test/motion_angle.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -6,9 +6,6 @@
  * transition.
  */
 
-#include <math.h>
-#include <stdio.h>
-
 #include "accelgyro.h"
 #include "common.h"
 #include "gpio.h"
@@ -20,22 +17,25 @@
 #include "test_util.h"
 #include "util.h"
 
+#include <math.h>
+#include <stdio.h>
+
 /*****************************************************************************/
 /* Test utilities */
 
 /* Array units is in m/s^2 - old matrix format. */
 int filler(const struct motion_sensor_t *s, const float v)
 {
-	return (v * MOTION_SCALING_FACTOR) / s->drv->get_range(s);
+	return (v * MOTION_SCALING_FACTOR) / s->current_range;
 }
 
 static int test_lid_angle_less180(void)
 {
 	int index = 0, lid_angle;
-	struct motion_sensor_t *lid = &motion_sensors[
-		CONFIG_LID_ANGLE_SENSOR_LID];
-	struct motion_sensor_t *base = &motion_sensors[
-		CONFIG_LID_ANGLE_SENSOR_BASE];
+	struct motion_sensor_t *lid =
+		&motion_sensors[CONFIG_LID_ANGLE_SENSOR_LID];
+	struct motion_sensor_t *base =
+		&motion_sensors[CONFIG_LID_ANGLE_SENSOR_BASE];
 
 	/* We don't have TASK_CHIP so simulate init ourselves */
 	hook_notify(HOOK_CHIPSET_SHUTDOWN);
@@ -56,42 +56,39 @@ static int test_lid_angle_less180(void)
 	cprints(CC_ACCEL, "start loop");
 	/* Check we will never enter tablet mode. */
 	while (index < kAccelerometerLaptopModeTestDataLength) {
-		feed_accel_data(kAccelerometerLaptopModeTestData,
-				&index, filler);
+		feed_accel_data(kAccelerometerLaptopModeTestData, &index,
+				filler);
 		wait_for_valid_sample();
 		lid_angle = motion_lid_get_angle();
 		cprints(CC_ACCEL, "%d : LID(%d, %d, %d)/BASE(%d, %d, %d): %d",
-				index / TEST_LID_SAMPLE_SIZE,
-				lid->xyz[X], lid->xyz[Y], lid->xyz[Z],
-				base->xyz[X], base->xyz[Y], base->xyz[Z],
-				lid_angle);
+			index / TEST_LID_SAMPLE_SIZE, lid->xyz[X], lid->xyz[Y],
+			lid->xyz[Z], base->xyz[X], base->xyz[Y], base->xyz[Z],
+			lid_angle);
 		/* We need few sample to debounce and enter laptop mode. */
 		TEST_ASSERT(index < TEST_LID_SAMPLE_SIZE *
-				(TABLET_MODE_DEBOUNCE_COUNT + 2) ||
+					    (TABLET_MODE_DEBOUNCE_COUNT + 2) ||
 			    !tablet_get_mode());
 	}
 
 	/* Check we will never exit tablet mode. */
 	index = 0;
 	while (index < kAccelerometerFullyOpenTestDataLength) {
-		feed_accel_data(kAccelerometerFullyOpenTestData,
-				&index, filler);
+		feed_accel_data(kAccelerometerFullyOpenTestData, &index,
+				filler);
 		wait_for_valid_sample();
 		lid_angle = motion_lid_get_angle();
 		cprints(CC_ACCEL, "%d : LID(%d, %d, %d)/BASE(%d, %d, %d): %d",
-				index / TEST_LID_SAMPLE_SIZE,
-				lid->xyz[X], lid->xyz[Y], lid->xyz[Z],
-				base->xyz[X], base->xyz[Y], base->xyz[Z],
-				lid_angle);
+			index / TEST_LID_SAMPLE_SIZE, lid->xyz[X], lid->xyz[Y],
+			lid->xyz[Z], base->xyz[X], base->xyz[Y], base->xyz[Z],
+			lid_angle);
 		TEST_ASSERT(index < TEST_LID_SAMPLE_SIZE *
-				(TABLET_MODE_DEBOUNCE_COUNT + 2) ||
+					    (TABLET_MODE_DEBOUNCE_COUNT + 2) ||
 			    tablet_get_mode());
 	}
 	return EC_SUCCESS;
 }
 
-
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/motion_angle.tasklist b/test/motion_angle.tasklist
index 0b774ebb4a..6c99c23eea 100644
--- a/test/motion_angle.tasklist
+++ b/test/motion_angle.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/motion_angle_data_literals.c b/test/motion_angle_data_literals.c
index 6c0fcb35c2..d22a8230a2 100644
--- a/test/motion_angle_data_literals.c
+++ b/test/motion_angle_data_literals.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,992 +12,993 @@
  * [ CONFIG_ACCEL_STD_REF_FRAME_OLD must be defined to used this array. ]
  */
 const float kAccelerometerLaptopModeTestData[] = {
-    -0.166016f,   -0.00488281f,  0.924805f,     -0.770508f,    -0.0488281f,
-    -0.510742f,   -0.199219f,    -0.0078125f,   0.953125f,     -0.782227f,
-    -0.0244141f,  -0.652344f,    -0.177734f,    -0.0136719f,   0.936523f,
-    -0.772461f,   -0.0527344f,   -0.59375f,     -0.176758f,    -0.00878906f,
-    0.9375f,      -0.777344f,    -0.0419922f,   -0.637695f,    -0.165039f,
-    -0.00878906f, 0.942383f,     -0.782227f,    -0.046875f,    -0.613281f,
-    -0.180664f,   -0.00976562f,  0.943359f,     -0.777344f,    -0.0419922f,
-    -0.601562f,   -0.189453f,    -0.00488281f,  0.943359f,     -0.776367f,
-    -0.0263672f,  -0.613281f,    -0.166992f,    -0.00488281f,  0.935547f,
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+	0.457031f,    -0.682617f,    -0.500977f,    0.210938f,	   0.391602f,
+	-0.303711f,   0.725586f,     -0.80957f,	    -0.391602f,	   0.0976562f,
+	0.958984f,    0.0185547f,    1.69922f,	    -1.36035f,	   1.98242f,
+	-0.392578f,   -0.461914f,    -0.37793f,	    -0.0712891f,   0.928711f,
+	-1.60254f,    0.133789f,     -0.0419922f,   -1.12109f,	   -0.201172f,
+	0.0732422f,   -1.99902f,     0.629883f,	    -0.174805f,	   -0.894531f,
+	0.0742188f,   -0.147461f,    -1.23633f,	    -0.259766f,	   0.0410156f,
+	-1.00879f,    -0.0166016f,   -0.0205078f,   -1.99902f,	   0.267578f,
+	-0.0664062f,  -0.164062f,    0.511719f,	    0.825195f,	   -1.21191f,
+	-0.515625f,   0.46875f,	     0.0898438f,    1.09766f,	   -0.144531f,
+	1.59375f,     0.166016f,     0.428711f,	    0.294922f,	   0.8125f,
+	-0.770508f,   0.535156f,     0.280273f,	    0.231445f,	   0.504883f,
+	0.864258f,    -0.884766f,    0.524414f,	    -0.183594f,	   0.0820312f,
+	0.713867f,    0.405273f,     -0.520508f,    -0.326172f,	   0.0126953f,
+	-0.310547f,   1.38086f,	     0.831055f,	    0.380859f,	   1.3125f,
+	-1.60645f,    0.151367f,     1.01953f,	    0.580078f,	   -0.0283203f,
+	2.0f,	      1.03516f,	     -0.0634766f,   1.03418f,	   0.332031f,
+	-0.0859375f,  1.32129f,	     -0.234375f,    0.0917969f,	   1.49219f,
+	0.30957f,     -0.118164f,    1.76953f,	    -0.717773f,	   0.174805f,
+	1.59863f,     0.0947266f,    1.1875f,	    0.429688f,	   0.442383f,
+	0.00976562f,  0.435547f,     0.345703f,	    -0.114258f,	   0.238281f,
+	-0.689453f,   0.30957f,	     0.0732422f,    0.606445f,	   -0.650391f,
+	-0.0947266f,  -0.03125f,     0.183594f,	    -0.144531f,	   0.746094f,
+	-0.793945f,   -0.574219f,    -0.0742188f,   0.196289f,	   -0.199219f,
+	1.13867f,     -1.11816f,     -0.227539f,    -0.462891f,	   0.0517578f,
+	-0.0341797f,  1.18945f,	     -1.1084f,	    -0.0283203f,   -0.342773f,
+	0.174805f,    -0.0078125f,   1.05176f,	    -1.03906f,	   0.0253906f,
+	-0.375977f,   -0.169922f,    0.00292969f,   0.837891f,	   -0.716797f,
+	-0.0205078f,  -0.373047f,    0.293945f,	    0.0175781f,	   0.833984f,
+	-0.916016f,   -0.0996094f,   -0.149414f,    0.200195f,	   -0.00195312f,
+	0.865234f,    -0.916016f,    -0.0117188f,   -0.390625f,	   0.290039f,
+	0.0234375f,   0.985352f,     -0.987305f,    0.0439453f,	   -0.214844f,
+	0.0917969f,   0.0615234f,    1.02832f,	    -1.00684f,	   0.152344f,
+	-0.452148f,   0.0615234f,    -0.00585938f,  1.02148f,	   -0.976562f,
+	-0.0927734f,  -0.286133f,    0.189453f,	    -0.0644531f,   1.02539f,
+	-1.02246f,    0.0166016f,    -0.243164f,    0.109375f,	   -0.09375f,
+	0.981445f,    -0.931641f,    0.0458984f,    -0.460938f,	   0.0537109f,
+	-0.0429688f,  1.05859f,	     -0.850586f,    0.0771484f,	   -0.0507812f,
+	0.108398f,    -0.177734f,    0.779297f,	    -0.74707f,	   -0.378906f,
+	-0.413086f,   -0.205078f,    -0.0488281f,   0.946289f,	   -0.760742f,
+	-0.180664f,   -0.228516f,    -0.208008f,    -0.0615234f,   1.05371f,
+	-0.953125f,   -0.34668f,     -1.16797f,	    -0.0322266f,   -0.276367f,
+	1.06641f,     -0.863281f,    -0.0244141f,   -0.290039f,	   -0.0429688f,
+	0.0439453f,   1.28223f,	     -1.06348f,	    0.181641f,	   -0.514648f,
+	-0.0214844f,  0.0f,	     0.861328f,	    -0.738281f,	   -0.0449219f,
+	0.0722656f,   0.125f,	     0.193359f,	    1.15039f,	   -1.0957f,
+	0.225586f,    -0.137695f,    0.12207f,	    -0.0400391f,   0.732422f,
+	-0.818359f,   -0.40918f,     -0.672852f,    -0.425781f,	   0.839844f,
+	0.856445f,    0.198242f,     -0.363281f,    0.206055f,	   -0.214844f,
+	1.20215f,     0.943359f,     0.0195312f,    2.0f,	   0.874023f,
+	0.0839844f,   0.827148f,     0.587891f,	    -0.384766f,	   1.57715f,
+	0.108398f,    -0.116211f,    0.952148f,	    0.246094f,	   -0.336914f,
+	0.463867f,    -0.740234f,    0.0185547f,    0.950195f,	   0.55957f,
+	-0.442383f,   1.09668f,	     0.0585938f,    0.132812f,	   1.37695f,
+	2.0f,	      -0.59375f,     2.0f,	    -0.676758f,	   -0.199219f,
+	-0.0205078f,  0.268555f,     -0.5f,	    -1.94629f,	   1.2832f,
+	0.0078125f,   -0.201172f,    0.674805f,	    -0.708984f,	   -0.490234f,
+	-0.515625f,   0.0439453f,    -0.0830078f,   1.14355f,	   -1.01953f,
+	-0.0224609f,  -0.282227f,    0.0214844f,    -0.078125f,	   1.09668f,
+	-0.961914f,   0.0253906f,    -0.56543f,	    0.30957f,	   0.964844f,
+	1.56836f,     -0.272461f,    1.91309f,	    -0.53418f,	   -0.695312f,
+	-0.878906f,   -0.0146484f,   0.277344f,	    -1.6416f,	   0.0244141f,
+	0.0898438f,   -0.785156f,    0.229492f,	    -0.259766f,	   -1.06055f,
+	-0.241211f,   0.0224609f,    -0.769531f,    0.748047f,	   -0.680664f,
+	-0.629883f,   -0.549805f,    -0.195312f,    -0.796875f,	   -0.399414f,
+	0.0859375f,   -1.99902f,     0.24707f,	    0.208984f,	   0.563477f,
+	1.91797f,     0.0585938f,    2.0f,	    -0.990234f,	   0.327148f,
+	-0.0917969f,  1.16797f,	     -0.94043f,	    0.623047f,	   -1.1748f,
+	-0.0205078f,  -0.0449219f,   0.883789f,	    -0.905273f,	   -0.370117f,
+	-0.601562f,   0.0332031f,    -0.0527344f,   0.928711f,	   -0.833984f,
+	-0.180664f,   -0.267578f,    0.0351562f,    -0.0175781f,   0.998047f,
+	-0.922852f,   -0.000976562f, -0.371094f,    0.0341797f,	   -0.0166016f,
+	0.977539f,    -0.900391f,    -0.00292969f,  -0.37207f,	   0.0449219f,
+	-0.0439453f,  0.989258f,     -0.904297f,    -0.0576172f,   -0.37207f,
+	0.270508f,    -0.368164f,    0.0576172f,    -0.607422f,	   -1.95508f,
+	-0.182617f,   -0.390625f,    1.62598f,	    1.52734f,	   1.2793f,
+	2.0f,	      -1.99902f,     0.226562f,	    1.01465f,	   0.669922f,
+	-0.373047f,   1.71484f,	     1.99707f,	    -0.0654297f,   1.00391f,
+	0.330078f,    -0.432617f,    0.704102f,	    -0.96875f,	   0.0800781f,
+	0.964844f,    0.702148f,     -0.5625f,	    1.39746f,	   -0.203125f,
+	0.255859f,    1.74512f,	     1.52539f,	    0.417969f,	   2.0f,
+	-0.0976562f,  -0.482422f,    0.09375f,	    0.151367f,	   -0.328125f,
+	-1.88867f,    -0.0595703f,   0.117188f,	    0.0751953f,	   0.870117f,
+	-0.870117f,   0.046875f,     -0.280273f,    0.125f,	   0.124023f,
+	1.0791f,      -0.964844f,    0.338867f,	    -0.0791016f,   0.0751953f,
+	0.12207f,     0.920898f,     -0.888672f,    0.0273438f,	   -0.250977f,
+	0.00488281f,  0.165039f,     1.01074f,	    -0.944336f,	   0.137695f,
+	-0.387695f,   -0.142578f,    0.238281f,	    1.77246f,	   -1.42285f,
+	0.90625f,     -0.856445f,    0.0556641f,    -0.219727f,	   -0.785156f,
+	1.47266f,     -1.99902f,     1.27246f,	    -0.132812f,	   -0.746094f,
+	0.172852f,    -0.0830078f,   -1.3584f,	    0.638672f,	   0.0175781f,
+	-0.786133f,   0.754883f,     -0.729492f,    -0.808594f,	   -0.291992f,
+	0.170898f,    -0.746094f,    0.623047f,	    -0.667969f,	   -0.743164f,
+	-0.241211f,   0.0693359f,    -0.725586f,    0.495117f,	   -0.545898f,
+	-0.969727f,   -0.131836f,    0.0234375f,    -0.52832f,	   0.280273f,
+	-0.327148f,   -1.0498f,	     -0.210938f,    -0.253906f,	   0.234375f,
+	0.661133f,    -0.0332031f,   -0.708008f,    -0.458984f,	   0.31543f,
+	0.480469f,    1.59082f,	     -1.22266f,	    1.41602f,	   -0.270508f,
+	0.263672f,    0.318359f,     1.21289f,	    -1.12207f,	   0.853516f,
+	-0.272461f,   0.158203f,     1.84766f,	    2.0f,	   0.341797f,
+	2.0f,	      -0.788086f,    -0.264648f,    -0.326172f,	   -1.25977f,
+	0.842773f,    -1.99902f,     -0.947266f,    0.249023f,	   -0.642578f,
+	0.745117f,    -0.744141f,    -0.404297f,    -0.266602f,	   0.0898438f,
+	-0.568359f,   0.501953f,     -0.494141f,    -0.858398f,	   0.0722656f,
+	-0.543945f,   1.16895f,	     1.12012f,	    1.47461f,	   -1.12988f,
+	-0.27832f,    0.53125f,	     0.875f,	    0.845703f,	   -0.318359f,
+	1.68555f,     1.29199f,	     -0.00195312f,  0.861328f,	   0.601562f,
+	-0.519531f,   1.16211f,	     -1.05957f,	    0.0507812f,	   0.904297f,
+	0.625977f,    -0.525391f,    1.16797f,	    -0.163086f,	   0.125977f,
+	1.99902f,     2.0f,	     2.0f,	    2.0f,	   -0.00195312f,
+	-1.11719f,    -0.3125f,	     -0.320312f,    0.585938f,	   -1.99902f,
+	0.647461f,    0.198242f,     -0.538086f,    0.993164f,	   -0.897461f,
+	-0.227539f,   -0.354492f,    0.0976562f,    -0.416016f,	   0.623047f,
+	-0.682617f,   -0.832031f,    -0.223633f,    -0.160156f,	   0.0751953f,
+	-0.791992f,   1.13379f,	     -1.99902f,	    -0.755859f,	   0.669922f,
+	1.02637f,     1.26758f,	     -0.293945f,    2.0f,	   1.93457f,
+	-0.0126953f,  0.773438f,     0.475586f,	    -0.59375f,	   0.329102f,
+	-0.588867f,   0.113281f,     0.740234f,	    0.749023f,	   -0.716797f,
+	0.941406f,    -0.0878906f,   0.71875f,	    1.8125f,	   2.0f,
+	-0.289062f,   2.0f,	     -1.01074f,	    0.0117188f,	   -0.183594f,
+	-0.969727f,   0.893555f,     -1.99902f,	    0.333008f,	   0.188477f,
+	-0.643555f,   0.504883f,     -0.511719f,    -0.804688f,	   -0.957031f,
+	0.0546875f,   -0.305664f,    -0.0449219f,   -0.145508f,	   -1.875f,
+	0.0996094f,   -0.155273f,    1.59668f,	    1.5293f,	   1.46973f,
+	2.0f,	      -1.9834f,	     0.375f,	    1.20508f,	   0.736328f,
+	-0.399414f,   2.0f,	     2.0f,	    0.123047f,	   0.834961f,
+	1.04004f,     -0.808594f,    1.31934f,	    -0.634766f,	   0.548828f,
+	0.129883f,    -1.64746f,     2.0f,	    -1.99902f,	   0.819336f,
+	0.0273438f,   -0.254883f,    0.722656f,	    -0.691406f,	   -0.464844f,
+	-1.05566f,    0.0634766f,    -0.206055f,    1.02148f,	   -0.90332f,
+	0.0595703f,   -0.03125f,     0.129883f,	    -0.177734f,	   0.697266f,
+	-0.713867f,   -0.351562f,    -0.169922f,    -0.119141f,	   -0.172852f,
+	1.01855f,     -0.989258f,    -0.12793f,	    -0.670898f,	   -0.146484f,
+	-0.261719f,   1.16602f,	     -1.05664f,	    -0.302734f,	   -0.25293f,
+	-0.0458984f,  -0.198242f,    0.90625f,	    -0.876953f,	   -0.144531f,
+	-0.424805f,   -0.151367f,    -0.147461f,    0.926758f,	   -0.835938f,
+	-0.191406f,   -0.326172f,    -0.128906f,    -0.216797f,	   0.910156f,
+	-0.851562f,   -0.291992f,    -0.549805f,    -0.0517578f,   -0.0869141f,
+	1.07715f,     -0.977539f,    -0.0361328f,   -0.418945f,	   -0.148438f,
+	-0.133789f,   0.907227f,     -0.836914f,    -0.213867f,	   -0.768555f,
+	-0.0664062f,  0.182617f,     1.0498f,	    -0.915039f,	   0.400391f,
+	-0.523438f,   0.015625f,     0.0f,	    1.13184f,	   -1.09961f,
+	-0.244141f,   -0.330078f,    -0.115234f,    0.0166016f,	   0.944336f,
+	-0.868164f,   -0.430664f,    -0.246094f,    -0.0185547f,   -0.00976562f,
+	0.819336f,    -0.822266f,    -0.380859f,    -1.1709f,	   0.0605469f,
+	-0.0498047f,  0.777344f,     -0.703125f,    0.0800781f,	   -0.451172f,
+	0.304688f,    0.0517578f,    0.825195f,	    -0.771484f,	   0.145508f,
+	0.495117f,    -0.0888672f,   -0.243164f,    1.48145f,	   -1.22168f,
+	0.0615234f,   -0.192383f,    -0.0537109f,   0.0195312f,	   1.21582f,
+	-1.06836f,    0.175781f,     -0.394531f,    0.237305f,	   -0.0126953f,
+	0.800781f,    -0.920898f,    -0.12207f,	    -0.391602f,	   -0.0917969f,
+	-0.0791016f,  1.08008f,	     -1.03613f,	    -0.0654297f,   -0.423828f,
+	0.0478516f,   -0.0253906f,   0.873047f,	    -0.884766f,	   -0.0722656f,
+	-0.579102f,   0.0136719f,    -0.0917969f,   0.954102f,	   -0.922852f,
+	-0.172852f,   -0.244141f,    0.0f,	    -0.141602f,	   0.929688f,
+	-0.894531f,   -0.179688f,    -0.291992f,    0.0283203f,	   -0.0947266f,
+	0.961914f,    -0.926758f,    -0.135742f,    -0.329102f,	   0.0576172f,
+	-0.0351562f,  0.999023f,     -0.958984f,    -0.0498047f,   -0.248047f,
+	0.0869141f,   -0.078125f,    1.01074f,	    -0.954102f,	   0.00976562f,
+	-0.217773f,   0.0986328f,    -0.0556641f,   0.916992f,	   -0.914062f,
+	-0.136719f,   -0.219727f,    0.0488281f,    -0.139648f,	   0.985352f,
+	-0.952148f,   -0.152344f,    -0.286133f,    0.0166016f,	   -0.0917969f,
+	1.0459f,      -0.972656f,    -0.0605469f,   -0.228516f,	   0.0507812f,
+	-0.0810547f,  0.956055f,     -0.9375f,	    -0.18457f,	   -0.275391f,
+	0.0703125f,   -0.0986328f,   0.948242f,	    -0.928711f,	   -0.162109f,
+	-0.333008f
+};
 const size_t kAccelerometerLaptopModeTestDataLength =
-    ARRAY_SIZE(kAccelerometerLaptopModeTestData);
+	ARRAY_SIZE(kAccelerometerLaptopModeTestData);
 
 const float kAccelerometerFullyOpenTestData[] = {
-    0.892578f,    -0.0810547f,  0.0146484f,    0.929688f,     -0.0644531f,
-    -0.0234375f,  0.996094f,    -0.0136719f,   0.0185547f,    1.02344f,
-    -0.0615234f,  -0.0449219f,  0.978516f,     0.125977f,     0.0400391f,
-    0.996094f,    0.0332031f,   -0.0117188f,   0.963867f,     0.107422f,
-    0.0214844f,   0.980469f,    0.0185547f,    -0.00683594f,  0.952148f,
-    0.0361328f,   0.0253906f,   0.976562f,     -0.00390625f,  -0.0126953f,
-    0.97168f,     0.0205078f,   0.0517578f,    1.01074f,      0.015625f,
-    -0.0234375f,  0.953125f,    -0.000976562f, 0.0390625f,    0.977539f,
-    -0.0224609f,  -0.00976562f, 0.954102f,     0.0244141f,    0.0439453f,
-    0.986328f,    0.00292969f,  -0.000976562f, 0.967773f,     0.0537109f,
-    0.046875f,    0.99707f,     0.0175781f,    -0.000976562f, 0.951172f,
-    0.0390625f,   0.0341797f,   0.974609f,     -0.00878906f,  -0.000976562f,
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+	-0.981445f,   -0.447266f,   -0.0107422f,   -0.823242f,	  -0.303711f,
+	0.0986328f,   -1.00684f,    -0.366211f,	   0.0986328f,	  -1.14551f,
+	-0.239258f,   0.140625f,    -0.894531f,	   -0.297852f,	  0.0849609f,
+	-0.949219f,   -0.341797f,   0.131836f,	   -0.966797f,	  -0.380859f,
+	0.0947266f,   -0.75293f,    -0.391602f,	   0.0839844f,	  -0.908203f,
+	-0.40625f,    0.161133f,    -0.860352f,	   -0.452148f,	  0.1875f,
+	-0.950195f,   -0.496094f,   0.200195f,	   -0.828125f,	  -0.581055f,
+	0.0771484f,   -0.93457f,    -0.607422f,	   0.0996094f,	  -0.863281f,
+	-0.59375f,    0.0927734f,   -0.802734f,	   -0.604492f,	  0.0947266f,
+	-0.807617f,   -0.722656f,   0.101562f,	   -0.844727f,	  -0.711914f,
+	0.149414f,    -1.03125f,    -0.77832f,	   0.125977f,	  -0.78418f,
+	-0.740234f,   0.121094f,    -0.891602f,	   -0.808594f,	  0.164062f,
+	-0.650391f,   -0.80957f,    0.0888672f,	   -0.416992f,	  -0.866211f,
+	0.155273f,    -0.382812f,   -0.880859f,	   0.0849609f,	  -0.264648f,
+	-0.775391f,   0.229492f,    -0.389648f,	   -0.814453f,	  0.0664062f,
+	-0.226562f,   -0.625f,	    0.414062f,	   -0.274414f,	  -0.681641f,
+	0.0292969f,   -0.0478516f,  -0.711914f,	   0.794922f,	  -0.388672f,
+	-0.584961f,   0.368164f,    -0.257812f,	   -0.545898f,	  1.09277f,
+	-0.277344f,   -0.125977f,   0.822266f,	   -0.365234f,	  -0.467773f,
+	0.714844f,    -0.413086f,   -0.136719f,	   1.57227f,	  -0.0947266f,
+	-0.223633f,   0.817383f,    -0.0556641f,   -0.0322266f,	  1.18945f,
+	-0.191406f,   -0.498047f,   0.991211f,	   -0.231445f,	  -0.246094f,
+	0.8125f,      -0.239258f,   -0.755859f,	   0.853516f,	  -0.228516f,
+	-0.821289f,   0.503906f,    -0.121094f,	   -0.795898f,	  0.523438f,
+	-0.220703f,   -0.773438f,   0.517578f,	   -0.274414f,	  -0.757812f,
+	0.539062f,    -0.222656f,   -0.770508f,	   0.396484f,	  -0.115234f,
+	-1.2334f,     0.485352f,    -0.217773f,	   -0.94043f,	  1.01758f,
+	-0.202148f,   -0.605469f,   0.0546875f,	   0.0957031f,	  -0.639648f,
+	-0.661133f,   0.245117f,    -0.750977f,	   0.0615234f,	  -0.726562f,
+	-0.879883f,   -0.432617f,   -1.05859f,	   -1.29688f,	  0.00488281f,
+	0.193359f,    -0.939453f,   0.209961f,	   -0.209961f,	  -0.793945f,
+	0.251953f,    0.722656f,    -0.447266f,	   0.0615234f,	  0.855469f,
+	-0.454102f,   -0.0126953f,  0.0527344f,	   -0.342773f,	  0.154297f,
+	1.3877f,      -0.65918f,    0.133789f,	   0.0576172f,	  -0.233398f,
+	-0.12207f,    0.46582f,	    -1.09961f,	   0.438477f,	  -0.641602f,
+	-0.861328f,   0.197266f,    -1.99902f,	   -0.932617f,	  0.234375f,
+	0.389648f,    -0.792969f,   -0.0908203f,   1.66797f,	  -1.0459f,
+	0.0107422f,   -0.543945f,   -0.80957f,	   0.206055f,	  -0.27832f,
+	-0.915039f,   0.104492f,    -0.301758f,	   -0.891602f,	  0.0556641f,
+	-0.681641f,   -0.901367f,   0.0498047f,	   -0.461914f,	  -0.927734f,
+	-0.0390625f,  -0.229492f,   -1.04004f,	   0.0869141f,	  -0.435547f,
+	-1.02148f,    0.0947266f,   -0.527344f,	   -0.979492f,	  0.0751953f,
+	0.266602f,    -0.786133f,   -0.0224609f,   -0.0947266f,	  -0.702148f,
+	-0.00683594f, -0.316406f,   -0.698242f,	   -0.317383f,	  1.92578f,
+	-1.0498f,     0.0273438f,   -1.14258f,	   -0.226562f,	  0.233398f,
+	-0.995117f,   -0.9375f,	    0.0146484f,	   -0.223633f,	  -0.49707f,
+	-0.0078125f,  -1.95703f,    -0.847656f,	   0.157227f,	  0.129883f,
+	-0.459961f,   -0.114258f,   2.0f,	   -1.13574f,	  -0.0839844f,
+	-0.0878906f,  -0.783203f,   0.131836f,	   -0.803711f,	  -0.90332f,
+	0.208984f,    -0.365234f,   -0.97168f,	   -0.0322266f,	  0.186523f,
+	-0.924805f,   0.00292969f,  -0.272461f,	   -0.890625f,	  0.015625f,
+	-0.333008f,   -0.932617f,   0.180664f,	   -0.459961f,	  -0.90918f,
+	0.240234f,    -0.625977f,   -1.1582f,	   0.0996094f,	  -0.170898f,
+	-1.08887f,    -0.00976562f, -0.849609f,	   -0.430664f,	  0.139648f,
+	-0.308594f,   -0.572266f,   -0.722656f,	   1.83496f,	  -1.00977f,
+	0.387695f,    0.487305f,    -0.268555f,	   0.0712891f,	  -0.0136719f,
+	-1.5332f,     0.290039f,    -0.0351562f,   -0.861328f,	  1.98535f,
+	-1.16602f,    -0.602539f,   0.441406f,	   0.175781f,	  -0.605469f,
+	-0.831055f,   0.686523f,    -0.984375f,	   0.494141f,	  -0.489258f,
+	-0.895508f,   0.371094f,    -0.665039f,	   -1.14258f,	  -0.214844f,
+	-0.140625f,   -1.06348f,    -0.0996094f,   0.255859f,	  -0.874023f,
+	0.193359f,    -0.0947266f,  -0.959961f,	   -0.0966797f,	  0.00195312f,
+	-0.996094f,   -0.0117188f,  -0.174805f,	   -0.962891f,	  0.106445f,
+	-0.162109f,   -1.04297f,    -0.0283203f,   -0.306641f,	  -1.06738f,
+	-0.0224609f,  -0.129883f,   -1.03223f,	   0.129883f,	  0.195312f,
+	-1.08789f,    -0.130859f,   0.649414f,	   -0.572266f,	  -0.0136719f,
+	-0.793945f,   -0.382812f,   0.0f,	   -1.08301f,	  -0.78125f,
+	-0.0224609f,  -0.339844f,   -0.629883f,	   -0.0947266f,	  -1.83789f,
+	-1.01562f,    0.046875f,    0.223633f,	   -0.808594f,	  0.0957031f,
+	1.09766f,     -0.756836f,   -0.0488281f,   0.157227f,	  -0.59082f,
+	-0.103516f,   0.929688f,    -0.816406f,	   -0.0322266f,	  -0.426758f,
+	-0.868164f,   -0.209961f,   -1.99902f,	   -0.986328f,	  -0.00878906f,
+	-0.365234f,   -0.980469f,   0.0439453f,	   0.59375f,	  -0.994141f,
+	0.0253906f,   0.0371094f,   -0.970703f,	   -0.0273438f,	  -0.120117f,
+	-0.935547f,   0.00195312f,  -0.235352f,	   -0.952148f,	  -0.0263672f,
+	-0.194336f,   -0.917969f,   -0.0195312f,   -0.261719f,	  -0.928711f,
+	-0.0234375f,  -0.219727f,   -0.945312f,	   0.0107422f,	  -0.228516f,
+	-0.938477f,   0.00683594f,  -0.178711f,	   -0.791016f,	  0.03125f,
+	-0.255859f,   -0.789062f,   0.0f,	   -0.141602f,	  -0.789062f,
+	0.232422f,    -0.285156f,   -0.788086f,	   0.228516f,	  -0.28125f,
+	-1.0f,	      0.258789f,    -0.277344f,	   -0.999023f,	  0.28125f,
+	-0.25293f,    -1.06152f,    0.046875f,	   -0.421875f,	  -1.07715f,
+	0.0390625f,   -0.224609f,   -0.923828f,	   -0.0205078f,	  -0.335938f,
+	-0.984375f,   -0.0966797f,  -0.34668f,	   -0.990234f,	  -0.191406f,
+	-0.301758f,   -1.03613f,    -0.241211f,	   -0.37207f,	  -0.975586f,
+	-0.267578f,   -0.460938f,   -1.00977f,	   -0.320312f,	  -0.382812f,
+	-0.913086f,   -0.257812f,   -0.457031f,	   -0.925781f,	  -0.256836f,
+	-0.34668f,    -0.889648f,   -0.237305f,	   -0.393555f,	  -0.897461f,
+	-0.239258f,   -0.429688f,   -0.844727f,	   -0.21875f,	  -0.428711f,
+	-0.87207f,    -0.203125f,   -0.368164f,	   -0.84668f,	  -0.101562f,
+	-0.423828f,   -0.875977f,   -0.165039f,	   -0.363281f,	  -0.884766f,
+	-0.0625f,     -0.473633f,   -0.90332f,	   -0.078125f,	  -0.138672f,
+	-0.918945f,   -0.198242f,   -0.25f,	   -0.928711f,	  -0.138672f,
+	-0.267578f,   -1.08203f,    0.00488281f,   -0.575195f,	  -1.125f,
+	-0.0332031f,  -0.4375f,	    -0.924805f,	   0.078125f,	  -0.305664f,
+	-0.93457f,    -0.0166016f,  -0.475586f,	   -0.94043f,	  -0.00488281f,
+	-0.533203f,   -0.956055f,   0.00292969f,   -0.391602f,	  -1.00293f,
+	0.0361328f,   -0.711914f,   -1.0166f,	   0.0332031f,	  -0.448242f,
+	-0.806641f,   -0.21582f,    -0.556641f,	   -0.759766f,	  -0.0214844f,
+	-0.626953f,   -0.700195f,   -0.263672f,	   -0.308594f,	  -0.608398f,
+	-0.236328f,   -0.253906f,   -0.616211f,	   -0.378906f,	  0.224609f,
+	-0.498047f,   -0.399414f,   0.206055f,	   -0.516602f,	  -0.228516f,
+	0.743164f,    -0.174805f,   -0.125f,	   0.760742f,	  -0.0214844f,
+	-0.135742f,   0.966797f,    0.240234f,	   0.0332031f,	  1.01855f,
+	0.105469f,    0.15332f,	    0.950195f,	   0.240234f,	  0.0732422f,
+	1.16895f,     0.245117f,    0.206055f,	   0.952148f,	  0.273438f,
+	-0.0390625f,  1.2793f,	    0.404297f,	   0.303711f,	  0.720703f,
+	0.369141f,    0.0966797f,   0.918945f,	   0.329102f,	  0.0390625f,
+	0.991211f,    0.397461f,    -0.124023f,	   0.866211f,	  0.210938f,
+	0.130859f,    1.08789f,	    0.317383f,	   0.0537109f,	  0.858398f,
+	0.245117f,    0.0732422f,   0.741211f,	   0.419922f,	  0.0302734f,
+	0.681641f,    0.485352f,    -0.0214844f,   0.641602f,	  0.520508f,
+	-0.129883f,   0.839844f,    0.490234f,	   0.00390625f,	  0.676758f,
+	0.581055f,    -0.0146484f,  0.692383f,	   0.432617f,	  -0.0371094f,
+	0.807617f,    0.664062f,    0.255859f,	   0.216797f,	  1.22559f,
+	0.0195312f,   1.22168f,	    1.2793f,	   -0.405273f,	  1.72559f,
+	0.708984f,    -0.209961f,   0.579102f,	   0.821289f,	  0.0380859f,
+	0.605469f,    0.80957f,	    0.147461f,	   0.419922f,	  0.869141f,
+	0.0390625f,   0.5625f,	    0.786133f,	   0.0654297f,	  0.594727f,
+	0.879883f,    0.0166016f,   0.480469f,	   0.835938f,	  0.00195312f,
+	0.414062f,    0.899414f,    -0.03125f,	   0.344727f,	  0.889648f,
+	0.0185547f,   0.236328f,    0.932617f,	   -0.00585938f,  0.255859f,
+	0.910156f,    0.0898438f,   0.262695f,	   0.945312f,	  0.0126953f,
+	0.279297f,    0.860352f,    0.0507812f,	   0.322266f,	  0.913086f,
+	0.00195312f,  0.296875f,    0.875977f,	   0.0078125f,	  0.373047f,
+	0.922852f,    -0.0244141f,  0.267578f,	   0.884766f,	  0.0117188f,
+	0.347656f,    0.926758f,    -0.0371094f,   0.266602f,	  0.894531f,
+	-0.00683594f, 0.345703f,    0.926758f,	   -0.0478516f,	  0.269531f,
+	0.887695f,    0.0146484f,   0.360352f,	   0.927734f,	  -0.03125f,
+	0.272461f
+};
 const size_t kAccelerometerFullyOpenTestDataLength =
-    ARRAY_SIZE(kAccelerometerFullyOpenTestData);
-
+	ARRAY_SIZE(kAccelerometerFullyOpenTestData);
diff --git a/test/motion_angle_data_literals_tablet.c b/test/motion_angle_data_literals_tablet.c
index 456779f457..f5b00f5fba 100644
--- a/test/motion_angle_data_literals_tablet.c
+++ b/test/motion_angle_data_literals_tablet.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,1030 +11,1030 @@
  * The arrays contain actual accelerator readings.
  */
 const float kAccelerometerVerticalHingeTestData[] = {
-    -0.0766145f,  6.02381f,     7.85298f,     -0.268151f,   -8.84897f,
-    -1.3216f,     -0.402226f,   5.11401f,     8.77236f,     -1.10133f,
-    -10.1706f,    1.24498f,     -1.18752f,    6.40688f,     8.0924f,
-    -2.60489f,    -8.99262f,    2.58574f,     0.632069f,    9.05008f,
-    3.61046f,     1.50356f,     -9.67257f,    1.93451f,     0.411803f,
-    8.81066f,     0.268151f,    -0.00957681f, -8.7532f,     2.15478f,
-    -0.0191536f,  9.49062f,     -0.68953f,    0.0383072f,   -8.94474f,
-    2.99754f,     -0.871489f,   9.80665f,     1.53229f,     -0.92895f,
-    -9.88326f,    0.957681f,    0.507571f,    9.19373f,     1.71425f,
-    0.287304f,    -9.03093f,    0.651223f,    0.363919f,    9.71088f,
-    1.18752f,     1.10133f,     -10.0556f,    2.98796f,     0.23942f,
-    9.39485f,     1.0343f,      0.842759f,    -9.73961f,    -1.12049f,
-    0.172383f,    9.50977f,     1.18752f,     0.0383072f,   -9.9503f,
-    0.957681f,    -0.373495f,   9.96946f,     1.01514f,     0.794875f,
-    -10.1897f,    -1.38864f,    -9.50977f,    -1.04387f,    0.325611f,
-    -9.76834f,    1.05345f,     -0.679953f,   -9.76834f,    -0.641646f,
-    0.488417f,    -9.2895f,     0.316035f,    0.258574f,    -9.29908f,
-    -0.890643f,   0.469264f,    -9.33739f,    0.823605f,    -0.45011f,
-    -9.69173f,    -1.02472f,    0.536301f,    -9.52892f,    0.90022f,
-    -0.411803f,   -9.34696f,    -0.890643f,   0.430956f,    -9.48104f,
-    0.823605f,    -0.603339f,   -9.7875f,     -0.565032f,   0.574608f,
-    -9.96946f,    0.536301f,    -0.699107f,   -9.57681f,    -0.823605f,
-    0.641646f,    -9.43316f,    0.593762f,    -0.775721f,   -9.35654f,
-    -1.04387f,    0.440533f,    -9.77792f,    1.01514f,     -0.881066f,
-    -9.32781f,    -1.10133f,    0.306458f,    -9.414f,      0.995988f,
-    0.0287304f,   -9.26077f,    -1.01514f,    0.268151f,    -9.29908f,
-    0.881066f,    0.00957681f,  -9.42358f,    -0.679953f,   0.201113f,
-    -9.49062f,    0.488417f,    -0.00957681f, -9.47146f,    -0.363919f,
-    0.191536f,    -9.32781f,    0.124498f,    0.124498f,    -9.5385f,
-    -0.0766145f,  0.268151f,    -9.32781f,    -0.172383f,   0.0574608f,
-    -9.69173f,    0.21069f,     0.354342f,    -9.50019f,    -0.306458f,
-    0.0383072f,   -9.54808f,    0.507571f,    0.363919f,    -9.20331f,
-    -0.775721f,   0.0574608f,   -9.59596f,    0.651223f,    0.679953f,
-    -9.56723f,    -0.794875f,   -0.0287304f,  -9.49062f,    0.794875f,
-    0.612916f,    -9.06924f,    -1.10133f,    -0.201113f,   -9.20331f,
-    1.90578f,     1.46525f,     -9.29908f,    -2.17394f,    0.603339f,
-    -0.995988f,   0.0766145f,   9.58638f,     -0.344765f,   -0.92895f,
-    -9.1267f,     -2.03986f,    -0.497994f,   10.477f,      -2.49955f,
-    -0.0957681f,  -10.4866f,    -1.5706f,     -0.23942f,    9.13627f,
-    -1.92494f,    -0.325611f,   -9.05008f,    -1.5706f,     -0.0383072f,
-    10.1323f,     -1.87705f,    -0.632069f,   -9.52892f,    -1.20668f,
-    0.105345f,    9.14585f,     -1.13964f,    -0.718261f,   -9.02135f,
-    -1.58975f,    0.296881f,    9.50019f,     -1.74298f,    -1.00556f,
-    -9.27993f,    -1.09176f,    0.23942f,     9.87369f,     -1.04387f,
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+	0.258574f,    -10.0844f,    0.23942f,	  0.0766145f,	-10.1131f,
+	0.794875f,    0.0f,	    -9.86411f,	  -0.593762f,	0.909797f,
+	-9.29908f,    -2.09732f,    1.72383f,	  -9.17458f,	1.89621f,
+	-1.58975f,    -8.91601f,    -2.16436f,	  1.94409f,	-9.1267f,
+	2.03986f,     -1.96325f,    -9.30866f,	  -2.42293f,	2.02071f,
+	-9.43316f,    2.26013f,	    -1.38864f,	  -9.8258f,	-2.2697f,
+	1.16837f,     -9.44273f,    2.16436f,	  -1.09176f,	-9.14585f,
+	-2.03986f,    1.26414f,	    -9.01178f,	  1.82917f,	-1.28329f,
+	-8.89685f,    -2.09732f,    1.64721f,	  -8.95431f,	1.93451f,
+	-1.69509f,    -8.8777f,	    -2.19309f,	  1.28329f,	-9.03093f,
+	2.11647f,     -1.40779f,    -9.31823f,	  -2.2697f,	1.09176f,
+	-9.11712f,    2.06859f,	    -1.3216f,	  -9.2895f,	-2.21224f,
+	1.4461f,      -9.165f,	    2.00155f,	  -1.48441f,	-8.98304f,
+	-2.20267f,    1.46525f,	    -8.83939f,	  2.00155f,	-1.24498f,
+	-9.14585f,    -2.26013f,    1.43652f,	  -9.01178f,	2.1069f,
+	-1.45567f,    -9.1267f,	    -2.29843f,	  1.63763f,	-9.04051f,
+	2.12605f,     -1.76213f,    -9.18416f,	  -2.27928f,	1.9824f,
+	-9.09797f,    2.07817f,	    -1.79086f,	  -9.08839f,	-2.00155f,
+	1.79086f,     -9.44273f,    1.87705f,	  -1.62806f,	-9.14585f,
+	-2.31759f,    1.84832f,	    -8.86812f,	  2.06859f,	1.61848f,
+	-9.165f,      -2.24097f,    2.05901f,	  -9.0022f,	2.02071f,
+	-1.7334f,     -9.04051f,    -2.1452f,	  2.04944f,	-9.2895f,
+	2.06859f,     -1.70467f,    -9.20331f,	  -2.22182f,	2.06859f,
+	-9.33739f,    2.09732f,	    -1.76213f,	  -9.34696f,	-2.13563f,
+	1.99198f,     -9.1267f,	    1.9824f,	  -1.84832f,	-8.88728f,
+	-1.79086f,    1.55144f,	    -9.03093f,	  1.62806f,	-1.61848f,
+	-9.1267f,     -1.58975f,    1.47483f,	  -9.19373f,	1.49398f,
+	-1.47483f,    -8.92558f,    -1.48441f,	  1.76213f,	-8.69574f,
+	1.18752f,     -1.76213f,    -9.24162f,	  -1.35991f,	1.49398f,
+	-9.48104f,    1.23541f,	    -1.61848f,	  -9.51935f,	1.86748f,
+	2.00155f,     -8.71489f,    -1.24498f,	  -2.11647f,	-5.6982f,
+	8.15944f,     1.27372f,	    -4.52983f,	  -7.99663f,	-0.775721f,
+	-4.00311f,    8.31267f,	    0.632069f,	  -3.68707f,	-8.03494f,
+	0.344765f,    -2.16436f,    7.79552f,	  3.7158f,	-1.7334f,
+	-7.74764f,    -4.22337f,    -1.56102f,	  8.78193f,	4.39575f,
+	-1.58017f,    -8.76278f,    -4.5011f,	  -1.72383f,	9.05008f,
+	5.25767f,     -1.93451f,    -9.11712f,	  -3.9648f,	-0.995988f,
+	7.97748f,     5.34386f,	    -1.33118f,	  -7.92002f,	-4.03184f,
+	-0.670376f,   9.17458f,	    4.3766f,	  0.220267f,	-9.60554f,
+	-4.13718f,    -0.746991f,   7.33583f,	  5.34386f,	-1.1971f,
+	-7.28795f,    -5.14275f,    0.871489f,	  7.90087f,	5.80354f,
+	0.584185f,    -8.33182f,    -3.04542f,	  0.986411f,	7.59441f,
+	6.49307f,     -0.0670376f,  -7.85298f,	  -5.92804f,	2.07817f,
+	8.83939f,     5.4109f,	    0.325611f,	  -9.59596f,	-3.83072f,
+	0.718261f,    7.38372f,	    5.99508f,	  0.248997f,	-8.29351f,
+	-5.10444f,    1.72383f,	    7.83383f,	  5.85143f,	2.12605f,
+	-9.15543f,    -4.03184f,    2.05901f,	  7.37414f,	5.79397f,
+	2.19309f,     -8.49463f,    -4.95121f,	  2.13563f,	7.91044f,
+	4.29999f,     2.1452f,	    -8.76278f,	  -2.24097f,	1.31202f,
+	8.59997f,     5.72693f,	    0.746991f,	  -9.55765f,	-3.54342f,
+	1.36948f,     8.5042f,	    5.09486f,	  1.17795f,	-9.62469f,
+	-4.1276f,     1.77171f,	    8.69574f,	  5.46836f,	1.63763f,
+	-9.40442f,    -2.32716f,    1.91536f,	  7.75721f,	5.25767f,
+	2.04944f,     -8.81066f,    -2.40378f,	  0.392649f,	7.73806f,
+	5.63116f,     1.45567f,	    -9.24162f,	  -1.49398f,	-0.258574f,
+	6.82826f,     7.34541f,	    -0.42138f,	  -9.07881f,	-1.30245f,
+	-0.517148f,   6.97192f,	    7.6806f,	  -0.890643f,	-9.58638f,
+	-4.81713f,    -0.21069f,    3.13162f,	  9.20331f,	-0.967257f,
+	-10.0748f,    0.181959f,    -0.948104f,	  -5.9855f,	7.4316f,
+	-1.00556f,    -9.5385f,	    0.497994f,	  0.162806f,	-8.47547f,
+	4.32872f,     0.248997f,    -9.165f,	  -2.27928f,	0.143652f,
+	-8.6287f,     4.47237f,	    0.354342f,	  -9.51935f,	0.986411f,
 };
 
 const size_t kAccelerometerVerticalHingeTestDataLength =
-    ARRAY_SIZE(kAccelerometerVerticalHingeTestData);
+	ARRAY_SIZE(kAccelerometerVerticalHingeTestData);
 
 const float kAccelerometerVerticalHingeUnstableTestData[] = {
-    8.5904f,   -1.36948f,  -3.74453f,   8.72447f,  1.1971f,    4.00311f,
-    8.80109f,  -3.08373f,  2.27928f,    8.95431f,  -1.90578f,  -1.10133f,
-    8.93516f,  -2.03986f,  0.248997f,   9.05008f,  1.53229f,   -0.708684f,
-    -8.78193f, 1.43652f,   -2.63362f,   -8.66701f, 0.220267f,  2.79643f,
-    -8.66701f, -2.06859f,  2.42293f,    -8.79151f, -2.88262f,  -1.16837f,
-    8.74362f,  -1.9824f,   3.53384f,    9.04051f,  0.0574608f, -1.36948f,
-    8.78193f,  -4.1276f,   2.58574f,    8.8777f,   0.201113f,  -1.80044f,
-    8.70532f,  -0.296881f, 1.52271f,    9.02135f,  -0.871489f, -2.43251f,
-    -9.09797f, -1.3216f,   -3.60088f,   -8.97347f, 2.52828f,   2.6432f,
-    -8.82024f, 1.87705f,   0.354342f,   -7.93917f, -4.38618f,  0.258574f,
-    -8.81066f, 1.91536f,   -2.92093f,   -8.04452f, -5.4492f,   3.28484f,
-    -8.86812f, 2.05901f,   0.890643f,   -8.01579f, -5.65989f,  -2.20267f,
-    -9.0022f,  2.18351f,   -2.9305f,    -8.80109f, -4.01268f,  3.055f,
-    -9.37569f, -1.04387f,  0.277727f,   -6.80911f, 2.806f,     -6.0717f,
-    -8.79151f, -8.79151f,  -2.11647f,   -8.6287f,  -1.53229f,  3.58173f,
-    -8.97347f, -0.335188f, 1.26414f,    8.5042f,   1.51314f,   -2.20267f,
-    -9.19373f, -1.37906f,  1.41737f,    -7.67102f, 2.8922f,    -5.09486f,
-    -8.81066f, 0.986411f,  2.30801f,    -8.53294f, 3.26569f,   -3.11246f,
-    -9.03093f, 1.06303f,   1.39821f,    -8.8777f,  -4.47237f,  -0.632069f,
-    -8.74362f, -1.83875f,  -0.0957681f, -7.92002f, 1.0343f,    -3.84988f,
-    -8.92558f, 0.440533f,  1.26414f,    -8.71489f, -0.153229f, -3.64876f,
+	8.5904f,   -1.36948f,  -3.74453f,   8.72447f,  1.1971f,	   4.00311f,
+	8.80109f,  -3.08373f,  2.27928f,    8.95431f,  -1.90578f,  -1.10133f,
+	8.93516f,  -2.03986f,  0.248997f,   9.05008f,  1.53229f,   -0.708684f,
+	-8.78193f, 1.43652f,   -2.63362f,   -8.66701f, 0.220267f,  2.79643f,
+	-8.66701f, -2.06859f,  2.42293f,    -8.79151f, -2.88262f,  -1.16837f,
+	8.74362f,  -1.9824f,   3.53384f,    9.04051f,  0.0574608f, -1.36948f,
+	8.78193f,  -4.1276f,   2.58574f,    8.8777f,   0.201113f,  -1.80044f,
+	8.70532f,  -0.296881f, 1.52271f,    9.02135f,  -0.871489f, -2.43251f,
+	-9.09797f, -1.3216f,   -3.60088f,   -8.97347f, 2.52828f,   2.6432f,
+	-8.82024f, 1.87705f,   0.354342f,   -7.93917f, -4.38618f,  0.258574f,
+	-8.81066f, 1.91536f,   -2.92093f,   -8.04452f, -5.4492f,   3.28484f,
+	-8.86812f, 2.05901f,   0.890643f,   -8.01579f, -5.65989f,  -2.20267f,
+	-9.0022f,  2.18351f,   -2.9305f,    -8.80109f, -4.01268f,  3.055f,
+	-9.37569f, -1.04387f,  0.277727f,   -6.80911f, 2.806f,	   -6.0717f,
+	-8.79151f, -8.79151f,  -2.11647f,   -8.6287f,  -1.53229f,  3.58173f,
+	-8.97347f, -0.335188f, 1.26414f,    8.5042f,   1.51314f,   -2.20267f,
+	-9.19373f, -1.37906f,  1.41737f,    -7.67102f, 2.8922f,	   -5.09486f,
+	-8.81066f, 0.986411f,  2.30801f,    -8.53294f, 3.26569f,   -3.11246f,
+	-9.03093f, 1.06303f,   1.39821f,    -8.8777f,  -4.47237f,  -0.632069f,
+	-8.74362f, -1.83875f,  -0.0957681f, -7.92002f, 1.0343f,	   -3.84988f,
+	-8.92558f, 0.440533f,  1.26414f,    -8.71489f, -0.153229f, -3.64876f,
 };
 
 const size_t kAccelerometerVerticalHingeUnstableTestDataLength =
-    ARRAY_SIZE(kAccelerometerVerticalHingeUnstableTestData);
+	ARRAY_SIZE(kAccelerometerVerticalHingeUnstableTestData);
diff --git a/test/motion_angle_tablet.c b/test/motion_angle_tablet.c
index 0829d9bb31..2f458381b3 100644
--- a/test/motion_angle_tablet.c
+++ b/test/motion_angle_tablet.c
@@ -1,13 +1,10 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Test motion sense code, when in tablet mode.
  */
 
-#include <math.h>
-#include <stdio.h>
-
 #include "accelgyro.h"
 #include "common.h"
 #include "gpio.h"
@@ -19,6 +16,8 @@
 #include "test_util.h"
 #include "util.h"
 
+#include <math.h>
+#include <stdio.h>
 
 /*****************************************************************************/
 /* Test utilities */
@@ -26,18 +25,18 @@
 /* convert array value from g to m.s^2. */
 int filler(const struct motion_sensor_t *s, const float v)
 {
-	return FP_TO_INT( fp_div(
-		FLOAT_TO_FP(v) * MOTION_SCALING_FACTOR,
-		fp_mul(INT_TO_FP(s->drv->get_range(s)), MOTION_ONE_G)));
+	return FP_TO_INT(
+		fp_div(FLOAT_TO_FP(v) * MOTION_SCALING_FACTOR,
+		       fp_mul(INT_TO_FP(s->current_range), MOTION_ONE_G)));
 }
 
 static int test_lid_angle_less180(void)
 {
 	int index = 0, lid_angle;
-	struct motion_sensor_t *lid = &motion_sensors[
-		CONFIG_LID_ANGLE_SENSOR_LID];
-	struct motion_sensor_t *base = &motion_sensors[
-		CONFIG_LID_ANGLE_SENSOR_BASE];
+	struct motion_sensor_t *lid =
+		&motion_sensors[CONFIG_LID_ANGLE_SENSOR_LID];
+	struct motion_sensor_t *base =
+		&motion_sensors[CONFIG_LID_ANGLE_SENSOR_BASE];
 
 	/* We don't have TASK_CHIP so simulate init ourselves */
 	hook_notify(HOOK_CHIPSET_SHUTDOWN);
@@ -57,49 +56,46 @@ static int test_lid_angle_less180(void)
 
 	cprints(CC_ACCEL, "start loop");
 	/* Force clamshell mode, to be sure we go in tablet mode ASAP. */
-	tablet_set_mode(0);
+	tablet_set_mode(0, TABLET_TRIGGER_LID);
 
 	/* Check we stay in tablet mode, even when hinge is vertical. */
 	while (index < kAccelerometerVerticalHingeTestDataLength) {
-		feed_accel_data(kAccelerometerVerticalHingeTestData,
-				&index, filler);
+		feed_accel_data(kAccelerometerVerticalHingeTestData, &index,
+				filler);
 		wait_for_valid_sample();
 		lid_angle = motion_lid_get_angle();
 		cprints(CC_ACCEL, "%d : LID(%d, %d, %d)/BASE(%d, %d, %d): %d",
-				index / TEST_LID_SAMPLE_SIZE,
-				lid->xyz[X], lid->xyz[Y], lid->xyz[Z],
-				base->xyz[X], base->xyz[Y], base->xyz[Z],
-				lid_angle);
+			index / TEST_LID_SAMPLE_SIZE, lid->xyz[X], lid->xyz[Y],
+			lid->xyz[Z], base->xyz[X], base->xyz[Y], base->xyz[Z],
+			lid_angle);
 		/* We need few sample to debounce and enter laptop mode. */
-		TEST_ASSERT(index < 2 * TEST_LID_SAMPLE_SIZE * \
-				(TABLET_MODE_DEBOUNCE_COUNT + 2) ||
+		TEST_ASSERT(index < 2 * TEST_LID_SAMPLE_SIZE *
+					    (TABLET_MODE_DEBOUNCE_COUNT + 2) ||
 			    tablet_get_mode());
 	}
 	/*
 	 * Check we stay in tablet mode, even when hinge is vertical and
 	 * shaked.
 	 */
-	tablet_set_mode(0);
+	tablet_set_mode(0, TABLET_TRIGGER_LID);
 	while (index < kAccelerometerVerticalHingeUnstableTestDataLength) {
 		feed_accel_data(kAccelerometerVerticalHingeUnstableTestData,
 				&index, filler);
 		wait_for_valid_sample();
 		lid_angle = motion_lid_get_angle();
 		cprints(CC_ACCEL, "%d : LID(%d, %d, %d)/BASE(%d, %d, %d): %d",
-				index / TEST_LID_SAMPLE_SIZE,
-				lid->xyz[X], lid->xyz[Y], lid->xyz[Z],
-				base->xyz[X], base->xyz[Y], base->xyz[Z],
-				lid_angle);
+			index / TEST_LID_SAMPLE_SIZE, lid->xyz[X], lid->xyz[Y],
+			lid->xyz[Z], base->xyz[X], base->xyz[Y], base->xyz[Z],
+			lid_angle);
 		/* We need few sample to debounce and enter laptop mode. */
 		TEST_ASSERT(index < TEST_LID_SAMPLE_SIZE *
-				(TABLET_MODE_DEBOUNCE_COUNT + 2) ||
+					    (TABLET_MODE_DEBOUNCE_COUNT + 2) ||
 			    tablet_get_mode());
 	}
 	return EC_SUCCESS;
 }
 
-
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/motion_angle_tablet.tasklist b/test/motion_angle_tablet.tasklist
index 0b774ebb4a..6c99c23eea 100644
--- a/test/motion_angle_tablet.tasklist
+++ b/test/motion_angle_tablet.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/motion_common.c b/test/motion_common.c
index 2cacae0eb1..b1e0a8cd7d 100644
--- a/test/motion_common.c
+++ b/test/motion_common.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -15,9 +15,9 @@
 
 /*****************************************************************************/
 /* Mock functions */
-static int accel_init(const struct motion_sensor_t *s)
+static int accel_init(struct motion_sensor_t *s)
 {
-	return EC_SUCCESS;
+	return sensor_init_done(s);
 }
 
 static int accel_read(const struct motion_sensor_t *s, intv3_t v)
@@ -26,25 +26,16 @@ static int accel_read(const struct motion_sensor_t *s, intv3_t v)
 	return EC_SUCCESS;
 }
 
-static int accel_get_range(const struct motion_sensor_t *s)
+static int accel_set_range(struct motion_sensor_t *s, int range, int rnd)
 {
-	return s->default_range;
-}
-
-static int accel_get_resolution(const struct motion_sensor_t *s)
-{
-#ifdef TEST_BODY_DETECTION
-	/* Assume we are using BMI160 */
-	return BMI_RESOLUTION;
-#endif
-	return 0;
+	s->current_range = range;
+	return EC_SUCCESS;
 }
 
 int test_data_rate[2] = { 0 };
 
-static int accel_set_data_rate(const struct motion_sensor_t *s,
-			      const int rate,
-			      const int rnd)
+static int accel_set_data_rate(const struct motion_sensor_t *s, const int rate,
+			       const int rnd)
 {
 	test_data_rate[s - motion_sensors] = rate | (rnd ? ROUND_UP_FLAG : 0);
 	return EC_SUCCESS;
@@ -61,8 +52,8 @@ static int accel_get_rms_noise(const struct motion_sensor_t *s)
 	/* Assume we are using BMI160 */
 	fp_t rate = INT_TO_FP(accel_get_data_rate(s) / 1000);
 	fp_t noise_100hz = INT_TO_FP(BMI160_ACCEL_RMS_NOISE_100HZ);
-	fp_t sqrt_rate_ratio = fp_sqrtf(fp_div(rate,
-					       INT_TO_FP(BMI_ACCEL_100HZ)));
+	fp_t sqrt_rate_ratio =
+		fp_sqrtf(fp_div(rate, INT_TO_FP(BMI_ACCEL_100HZ)));
 	return FP_TO_INT(fp_mul(noise_100hz, sqrt_rate_ratio));
 }
 #endif
@@ -70,8 +61,7 @@ static int accel_get_rms_noise(const struct motion_sensor_t *s)
 const struct accelgyro_drv test_motion_sense = {
 	.init = accel_init,
 	.read = accel_read,
-	.get_range = accel_get_range,
-	.get_resolution = accel_get_resolution,
+	.set_range = accel_set_range,
 	.set_data_rate = accel_set_data_rate,
 	.get_data_rate = accel_get_data_rate,
 #ifdef CONFIG_BODY_DETECTION
@@ -117,7 +107,7 @@ const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
 /* Read 6 samples from array to sensor vectors, convert units if necessary. */
 void feed_accel_data(const float *array, int *idx,
-		int (filler)(const struct motion_sensor_t*, const float))
+		     int(filler)(const struct motion_sensor_t *, const float))
 {
 	int i, j;
 
@@ -137,9 +127,6 @@ void wait_for_valid_sample(void)
 
 	sample = *lpc_status & EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK;
 	usleep(TEST_LID_EC_RATE);
-	task_wake(TASK_ID_MOTIONSENSE);
 	while ((*lpc_status & EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK) == sample)
 		usleep(TEST_LID_SLEEP_RATE);
 }
-
-
diff --git a/test/motion_common.h b/test/motion_common.h
index 45d856d9ef..2c87e7bc6e 100644
--- a/test/motion_common.h
+++ b/test/motion_common.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -13,7 +13,7 @@
  * The task will read the vectors at that interval
  */
 #define TEST_LID_EC_RATE (1 * MSEC)
-#define TEST_LID_FREQUENCY (1e9 / TEST_LID_EC_RATE)   /* mHz */
+#define TEST_LID_FREQUENCY (1e9 / TEST_LID_EC_RATE) /* mHz */
 
 /*
  * Time in ms to wait for the task to read the vectors.
@@ -26,11 +26,11 @@
 extern enum chipset_state_mask sensor_active;
 
 extern struct motion_sensor_t motion_sensors[];
-extern const unsigned int motion_sensor_count;
 
 void wait_for_valid_sample(void);
 void feed_accel_data(const float *array, int *idx,
-		int (filler)(const struct motion_sensor_t *s, const float f));
+		     int(filler)(const struct motion_sensor_t *s,
+				 const float f));
 
 /*
  * External data - from
@@ -65,4 +65,4 @@ extern const float kAccelerometerVerticalHingeTestData[];
 extern const size_t kAccelerometerVerticalHingeTestDataLength;
 extern const float kAccelerometerVerticalHingeUnstableTestData[];
 extern const size_t kAccelerometerVerticalHingeUnstableTestDataLength;
-#endif  /* __CROS_EC_MOTION_COMMON_H */
+#endif /* __CROS_EC_MOTION_COMMON_H */
diff --git a/test/motion_lid.c b/test/motion_lid.c
index a9ede3a651..d734959fbe 100644
--- a/test/motion_lid.c
+++ b/test/motion_lid.c
@@ -1,13 +1,10 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Test motion sense code.
  */
 
-#include <math.h>
-#include <stdio.h>
-
 #include "accelgyro.h"
 #include "common.h"
 #include "gpio.h"
@@ -15,12 +12,17 @@
 #include "host_command.h"
 #include "motion_lid.h"
 #include "motion_sense.h"
+#include "tablet_mode.h"
 #include "task.h"
 #include "test_util.h"
 #include "timer.h"
 #include "util.h"
 
+#include <math.h>
+#include <stdio.h>
+
 extern enum chipset_state_mask sensor_active;
+extern int wait_us;
 
 /*
  * Period in us for the motion task period.
@@ -29,14 +31,14 @@ extern enum chipset_state_mask sensor_active;
 #define TEST_LID_EC_RATE (10 * MSEC)
 
 /*
- * Time in ms to wait for the task to read the vectors.
+ * Time in us to wait for the task to read the vectors.
  */
 #define TEST_LID_SLEEP_RATE (TEST_LID_EC_RATE / 5)
 #define ONE_G_MEASURED (1 << 14)
 
 /*****************************************************************************/
 /* Mock functions */
-static int accel_init(const struct motion_sensor_t *s)
+static int accel_init(struct motion_sensor_t *s)
 {
 	return EC_SUCCESS;
 }
@@ -47,18 +49,13 @@ static int accel_read(const struct motion_sensor_t *s, intv3_t v)
 	return EC_SUCCESS;
 }
 
-static int accel_set_range(const struct motion_sensor_t *s,
-			   const int range,
+static int accel_set_range(struct motion_sensor_t *s, const int range,
 			   const int rnd)
 {
+	s->current_range = range;
 	return EC_SUCCESS;
 }
 
-static int accel_get_range(const struct motion_sensor_t *s)
-{
-	return s->default_range;
-}
-
 static int accel_get_resolution(const struct motion_sensor_t *s)
 {
 	return 0;
@@ -66,9 +63,8 @@ static int accel_get_resolution(const struct motion_sensor_t *s)
 
 int test_data_rate[2] = { 0 };
 
-static int accel_set_data_rate(const struct motion_sensor_t *s,
-			      const int rate,
-			      const int rnd)
+static int accel_set_data_rate(const struct motion_sensor_t *s, const int rate,
+			       const int rnd)
 {
 	test_data_rate[s - motion_sensors] = rate;
 	return EC_SUCCESS;
@@ -83,7 +79,6 @@ const struct accelgyro_drv test_motion_sense = {
 	.init = accel_init,
 	.read = accel_read,
 	.set_range = accel_set_range,
-	.get_range = accel_get_range,
 	.get_resolution = accel_get_resolution,
 	.set_data_rate = accel_set_data_rate,
 	.get_data_rate = accel_get_data_rate,
@@ -100,11 +95,6 @@ struct motion_sensor_t motion_sensors[] = {
 		.rot_standard_ref = NULL,
 		.default_range = MOTION_SCALING_FACTOR / ONE_G_MEASURED,
 		.config = {
-			/* AP: by default shutdown all sensors */
-			[SENSOR_CONFIG_AP] = {
-				.odr = 0,
-				.ec_rate = 0,
-			},
 			/* EC use accel for angle detection */
 			[SENSOR_CONFIG_EC_S0] = {
 				.odr = 119000 | ROUND_UP_FLAG,
@@ -115,15 +105,11 @@ struct motion_sensor_t motion_sensors[] = {
 				.odr = 119000 | ROUND_UP_FLAG,
 				.ec_rate = TEST_LID_EC_RATE * 100,
 			},
-			[SENSOR_CONFIG_EC_S5] = {
-				.odr = 0,
-				.ec_rate = 0,
-			},
 		},
 	},
 	[LID] = {
 		.name = "lid",
-		.active_mask = SENSOR_ACTIVE_S0,
+		.active_mask = SENSOR_ACTIVE_S0_S3,
 		.chip = MOTIONSENSE_CHIP_KXCJ9,
 		.type = MOTIONSENSE_TYPE_ACCEL,
 		.location = MOTIONSENSE_LOC_LID,
@@ -131,11 +117,6 @@ struct motion_sensor_t motion_sensors[] = {
 		.rot_standard_ref = NULL,
 		.default_range = MOTION_SCALING_FACTOR / ONE_G_MEASURED,
 		.config = {
-			/* AP: by default shutdown all sensors */
-			[SENSOR_CONFIG_AP] = {
-				.odr = 0,
-				.ec_rate = 0,
-			},
 			/* EC use accel for angle detection */
 			[SENSOR_CONFIG_EC_S0] = {
 				.odr = 119000 | ROUND_UP_FLAG,
@@ -146,10 +127,6 @@ struct motion_sensor_t motion_sensors[] = {
 				.odr = 200000 | ROUND_UP_FLAG,
 				.ec_rate = TEST_LID_EC_RATE * 100,
 			},
-			[SENSOR_CONFIG_EC_S5] = {
-				.odr = 0,
-				.ec_rate = 0,
-			},
 		},
 	},
 };
@@ -159,36 +136,76 @@ const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 /* Test utilities */
 static void wait_for_valid_sample(void)
 {
-	uint8_t sample;
 	uint8_t *lpc_status = host_get_memmap(EC_MEMMAP_ACC_STATUS);
+	uint8_t sample;
+	int i;
+
+	for (i = 0; i < 2 * TABLET_MODE_DEBOUNCE_COUNT; i++) {
+		sample = *lpc_status & EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK;
+		usleep(TEST_LID_EC_RATE);
+		while ((*lpc_status & EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK) ==
+		       sample)
+			usleep(TEST_LID_SLEEP_RATE);
+	}
+}
 
-	sample = *lpc_status & EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK;
-	usleep(TEST_LID_EC_RATE);
-	task_wake(TASK_ID_MOTIONSENSE);
-	while ((*lpc_status & EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK) == sample)
-		usleep(TEST_LID_SLEEP_RATE);
+static int tablet_hook_count;
+
+static void tablet_mode_change_hook(void)
+{
+	tablet_hook_count++;
 }
+DECLARE_HOOK(HOOK_TABLET_MODE_CHANGE, tablet_mode_change_hook,
+	     HOOK_PRIO_DEFAULT);
 
-static int test_lid_angle(void)
+void before_test(void)
 {
+	/* Make sure the device lid is in a consistent state (close). */
+	gpio_set_level(GPIO_TABLET_MODE_L, 1);
+	msleep(50);
+	gpio_set_level(GPIO_LID_OPEN, 0);
+	msleep(50);
+	tablet_hook_count = 1;
+}
 
-	struct motion_sensor_t *base = &motion_sensors[
-		CONFIG_LID_ANGLE_SENSOR_BASE];
-	struct motion_sensor_t *lid = &motion_sensors[
-		CONFIG_LID_ANGLE_SENSOR_LID];
+/*
+ * The device lid is closed from before_test,
+ * Initialize the EC, set the sensors to match the lid angle (0 degree)
+ * and go through several lid angles.
+ * When lid angle are close to 0 or 360, activate the GMRs GPIO or not
+ * and observe their on lid angle data quality and the tablet mode state.
+ */
+static int test_lid_angle(void)
+{
+	struct motion_sensor_t *base =
+		&motion_sensors[CONFIG_LID_ANGLE_SENSOR_BASE];
+	struct motion_sensor_t *lid =
+		&motion_sensors[CONFIG_LID_ANGLE_SENSOR_LID];
 	int lid_angle;
 
 	/* We don't have TASK_CHIP so simulate init ourselves */
 	hook_notify(HOOK_CHIPSET_SHUTDOWN);
+	/* Wait for the sensor task to start */
+	msleep(50);
 	TEST_ASSERT(sensor_active == SENSOR_ACTIVE_S5);
 	TEST_ASSERT(accel_get_data_rate(lid) == 0);
+	TEST_ASSERT(base->collection_rate == 0);
+	TEST_ASSERT(lid->collection_rate == 0);
+	TEST_ASSERT(wait_us == -1);
 
 	/* Go to S0 state */
 	hook_notify(HOOK_CHIPSET_SUSPEND);
 	hook_notify(HOOK_CHIPSET_RESUME);
-	msleep(1000);
+	msleep(50);
 	TEST_ASSERT(sensor_active == SENSOR_ACTIVE_S0);
 	TEST_ASSERT(accel_get_data_rate(lid) == 119000);
+	TEST_ASSERT(base->collection_rate != 0);
+	TEST_ASSERT(lid->collection_rate != 0);
+	TEST_ASSERT(wait_us > 0);
+
+	/* Check we are in clamshell mode initially. */
+	TEST_ASSERT(tablet_hook_count == 1);
+	TEST_ASSERT(!tablet_get_mode());
 
 	/*
 	 * Set the base accelerometer as if it were sitting flat on a desk
@@ -200,20 +217,16 @@ static int test_lid_angle(void)
 	lid->xyz[X] = 0;
 	lid->xyz[Y] = 0;
 	lid->xyz[Z] = -ONE_G_MEASURED;
-	gpio_set_level(GPIO_LID_OPEN, 0);
-	/* Initial wake up, like init does */
-	task_wake(TASK_ID_MOTIONSENSE);
 
-	/* wait for the EC sampling period to expire   */
-	msleep(TEST_LID_EC_RATE);
-	task_wake(TASK_ID_MOTIONSENSE);
+	/* Check we are still in clamshell mode, no event */
+	TEST_ASSERT(tablet_hook_count == 1);
+	TEST_ASSERT(!tablet_get_mode());
 
 	wait_for_valid_sample();
 	lid_angle = motion_lid_get_angle();
-	cprints(CC_ACCEL, "LID(%d, %d, %d)/BASE(%d, %d, %d): %d",
-			lid->xyz[X], lid->xyz[Y], lid->xyz[Z],
-			base->xyz[X], base->xyz[Y], base->xyz[Z],
-			lid_angle);
+	cprints(CC_ACCEL, "LID(%d, %d, %d)/BASE(%d, %d, %d): %d", lid->xyz[X],
+		lid->xyz[Y], lid->xyz[Z], base->xyz[X], base->xyz[Y],
+		base->xyz[Z], lid_angle);
 	TEST_ASSERT(lid_angle == 0);
 
 	/* Set lid open to 90 degrees. */
@@ -225,6 +238,8 @@ static int test_lid_angle(void)
 	wait_for_valid_sample();
 
 	TEST_ASSERT(motion_lid_get_angle() == 90);
+	TEST_ASSERT(tablet_hook_count == 1);
+	TEST_ASSERT(!tablet_get_mode());
 
 	/* Set lid open to 225. */
 	lid->xyz[X] = 0;
@@ -233,6 +248,10 @@ static int test_lid_angle(void)
 	wait_for_valid_sample();
 	TEST_ASSERT(motion_lid_get_angle() == 225);
 
+	/* We are now in tablet mode */
+	TEST_ASSERT(tablet_hook_count == 2);
+	TEST_ASSERT(tablet_get_mode());
+
 	/* Set lid open to 350 */
 	lid->xyz[X] = 0;
 	lid->xyz[Y] = -1 * ONE_G_MEASURED * 0.1736;
@@ -240,15 +259,28 @@ static int test_lid_angle(void)
 	wait_for_valid_sample();
 	TEST_ASSERT(motion_lid_get_angle() == 350);
 
+	TEST_ASSERT(tablet_hook_count == 2);
+	TEST_ASSERT(tablet_get_mode());
+
+	/* Assert tablet GMT sensor, no change. */
+	gpio_set_level(GPIO_TABLET_MODE_L, 0);
+	msleep(50);
+	TEST_ASSERT(tablet_hook_count == 2);
+	TEST_ASSERT(tablet_get_mode());
+
 	/*
 	 * Set lid open to 10.  Since the lid switch still indicates that it's
 	 * open, we should be getting an unreliable reading.
+	 * We are still in tablet mode.
 	 */
+	gpio_set_level(GPIO_TABLET_MODE_L, 1);
 	lid->xyz[X] = 0;
 	lid->xyz[Y] = ONE_G_MEASURED * 0.1736;
 	lid->xyz[Z] = -1 * ONE_G_MEASURED * 0.9848;
 	wait_for_valid_sample();
 	TEST_ASSERT(motion_lid_get_angle() == LID_ANGLE_UNRELIABLE);
+	TEST_ASSERT(tablet_hook_count == 2);
+	TEST_ASSERT(tablet_get_mode());
 
 	/* Rotate back to 180 and then 10 */
 	lid->xyz[X] = 0;
@@ -256,6 +288,8 @@ static int test_lid_angle(void)
 	lid->xyz[Z] = ONE_G_MEASURED;
 	wait_for_valid_sample();
 	TEST_ASSERT(motion_lid_get_angle() == 180);
+	TEST_ASSERT(tablet_hook_count == 2);
+	TEST_ASSERT(tablet_get_mode());
 
 	/*
 	 * Again, since the lid isn't closed, the angle should be unreliable.
@@ -266,6 +300,8 @@ static int test_lid_angle(void)
 	lid->xyz[Z] = -1 * ONE_G_MEASURED * 0.9848;
 	wait_for_valid_sample();
 	TEST_ASSERT(motion_lid_get_angle() == LID_ANGLE_UNRELIABLE);
+	TEST_ASSERT(tablet_hook_count == 2);
+	TEST_ASSERT(tablet_get_mode());
 
 	/*
 	 * Align base with hinge and make sure it returns unreliable for angle.
@@ -276,6 +312,8 @@ static int test_lid_angle(void)
 	base->xyz[Z] = 0;
 	wait_for_valid_sample();
 	TEST_ASSERT(motion_lid_get_angle() == LID_ANGLE_UNRELIABLE);
+	TEST_ASSERT(tablet_hook_count == 2);
+	TEST_ASSERT(tablet_get_mode());
 
 	/*
 	 * Use all three axes and set lid to negative base and make sure
@@ -289,6 +327,9 @@ static int test_lid_angle(void)
 	lid->xyz[Z] = 13712;
 	wait_for_valid_sample();
 	TEST_ASSERT(motion_lid_get_angle() == 180);
+	/* Still in tablet mode */
+	TEST_ASSERT(tablet_hook_count == 2);
+	TEST_ASSERT(tablet_get_mode());
 
 	/*
 	 * Close the lid and set the angle to 0.
@@ -303,6 +344,8 @@ static int test_lid_angle(void)
 	msleep(100);
 	wait_for_valid_sample();
 	TEST_ASSERT(motion_lid_get_angle() == 0);
+	TEST_ASSERT(tablet_hook_count == 3);
+	TEST_ASSERT(!tablet_get_mode());
 
 	/*
 	 * Make the angle large, but since the lid is closed, the angle should
@@ -313,12 +356,20 @@ static int test_lid_angle(void)
 	lid->xyz[Z] = -1 * ONE_G_MEASURED * 0.9848;
 	wait_for_valid_sample();
 	TEST_ASSERT(motion_lid_get_angle() == LID_ANGLE_UNRELIABLE);
+	TEST_ASSERT(tablet_hook_count == 3);
+	TEST_ASSERT(!tablet_get_mode());
+
+	/* Open the lid, the large angle is now valid */
+	gpio_set_level(GPIO_LID_OPEN, 1);
+	msleep(100);
+	TEST_ASSERT(motion_lid_get_angle() == 350);
+	TEST_ASSERT(tablet_hook_count == 4);
+	TEST_ASSERT(tablet_get_mode());
 
 	/*
-	 * Open the lid to 350, and then close the lid and set the angle
+	 * Close the lid and set the angle
 	 * to 10. The reading of small angle shouldn't be corrected.
 	 */
-	gpio_set_level(GPIO_LID_OPEN, 1);
 	msleep(100);
 	gpio_set_level(GPIO_LID_OPEN, 0);
 	msleep(100);
@@ -327,12 +378,25 @@ static int test_lid_angle(void)
 	lid->xyz[Z] = -1 * ONE_G_MEASURED * 0.9848;
 	wait_for_valid_sample();
 	TEST_ASSERT(motion_lid_get_angle() == 10);
+	TEST_ASSERT(tablet_hook_count == 5);
+	TEST_ASSERT(!tablet_get_mode());
+
+	/* Shutdown in place, same mode. */
+	hook_notify(HOOK_CHIPSET_SHUTDOWN);
+	msleep(1000);
+	TEST_ASSERT(sensor_active == SENSOR_ACTIVE_S5);
+	/* Base ODR is 0, collection rate is 0. */
+	TEST_ASSERT(base->collection_rate == 0);
+	/* Lid is powered off, collection rate is 0. */
+	TEST_ASSERT(lid->collection_rate == 0);
+	TEST_ASSERT(wait_us == -1);
+	TEST_ASSERT(tablet_hook_count == 5);
+	TEST_ASSERT(!tablet_get_mode());
 
 	return EC_SUCCESS;
 }
 
-
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/motion_lid.tasklist b/test/motion_lid.tasklist
index 0b774ebb4a..6c99c23eea 100644
--- a/test/motion_lid.tasklist
+++ b/test/motion_lid.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/motion_sense_fifo.c b/test/motion_sense_fifo.c
index 09d3404032..3cea279bda 100644
--- a/test/motion_sense_fifo.c
+++ b/test/motion_sense_fifo.c
@@ -1,19 +1,24 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Test motion_sense_fifo.
  */
 
-#include "stdio.h"
+#include "accelgyro.h"
+#include "ec_commands.h"
+#include "hwtimer.h"
 #include "motion_sense_fifo.h"
+#include "stdio.h"
+#include "task.h"
 #include "test_util.h"
-#include "util.h"
-#include "hwtimer.h"
 #include "timer.h"
-#include "accelgyro.h"
+#include "util.h"
+
 #include <sys/types.h>
 
+mutex_t g_sensor_mutex;
+
 struct motion_sensor_t motion_sensors[] = {
 	[BASE] = {},
 	[LID] = {},
@@ -149,6 +154,11 @@ static int test_stage_data_removed_oversample(void)
 
 static int test_stage_data_remove_all_oversampling(void)
 {
+	uint8_t fifo_info_buffer
+		[sizeof(struct ec_response_motion_sense_fifo_info) +
+		 sizeof(uint16_t) * MAX_MOTION_SENSORS];
+	struct ec_response_motion_sense_fifo_info *fifo_info =
+		(void *)fifo_info_buffer;
 	int read_count;
 
 	motion_sensors->oversampling_ratio = 0;
@@ -162,6 +172,15 @@ static int test_stage_data_remove_all_oversampling(void)
 	data->data[1] = 5;
 	data->data[2] = 6;
 	motion_sense_fifo_stage_data(data, motion_sensors, 3, 110);
+
+	/*
+	 * Check that count is 0 and total_lost is 0, oversampling should be
+	 * removing the data before it touches the FIFO.
+	 */
+	motion_sense_fifo_get_info(fifo_info, /*reset=*/false);
+	TEST_EQ(fifo_info->count, 0, "%d");
+	TEST_EQ(fifo_info->total_lost, 0, "%d");
+
 	motion_sense_fifo_commit_data();
 
 	read_count = motion_sense_fifo_read(
@@ -177,6 +196,11 @@ static int test_stage_data_remove_all_oversampling(void)
 
 static int test_stage_data_evicts_data_with_timestamp(void)
 {
+	uint8_t fifo_info_buffer
+		[sizeof(struct ec_response_motion_sense_fifo_info) +
+		 sizeof(uint16_t) * MAX_MOTION_SENSORS];
+	struct ec_response_motion_sense_fifo_info *fifo_info =
+		(void *)fifo_info_buffer;
 	int i, read_count;
 
 	/* Fill the fifo */
@@ -186,6 +210,15 @@ static int test_stage_data_evicts_data_with_timestamp(void)
 
 	/* Add a single entry (should evict 2) */
 	motion_sense_fifo_add_timestamp(CONFIG_ACCEL_FIFO_SIZE * 100);
+
+	/*
+	 * Check that count is 1 smaller than the total size and total_lost is 2
+	 * because 2 entries were evicted together.
+	 */
+	motion_sense_fifo_get_info(fifo_info, /*reset=*/false);
+	TEST_EQ(fifo_info->count, CONFIG_ACCEL_FIFO_SIZE - 1, "%d");
+	TEST_EQ(fifo_info->total_lost, 2, "%d");
+
 	read_count = motion_sense_fifo_read(
 		sizeof(data), CONFIG_ACCEL_FIFO_SIZE, data, &data_bytes_read);
 	TEST_EQ(read_count, CONFIG_ACCEL_FIFO_SIZE - 1, "%d");
@@ -249,17 +282,17 @@ static int test_spread_data_in_window(void)
 	int read_count;
 
 	motion_sensors[0].oversampling_ratio = 1;
-	motion_sensors[0].collection_rate = 20000; /* ns */
+	motion_sense_set_data_period(0, 20 /* us */);
 	now = __hw_clock_source_read();
 
-	motion_sense_fifo_stage_data(data, motion_sensors, 3, now - 18000);
-	motion_sense_fifo_stage_data(data, motion_sensors, 3, now - 18000);
+	motion_sense_fifo_stage_data(data, motion_sensors, 3, now - 18);
+	motion_sense_fifo_stage_data(data, motion_sensors, 3, now - 18);
 	motion_sense_fifo_commit_data();
 	read_count = motion_sense_fifo_read(
 		sizeof(data), CONFIG_ACCEL_FIFO_SIZE, data, &data_bytes_read);
 	TEST_EQ(read_count, 4, "%d");
 	TEST_BITS_SET(data[0].flags, MOTIONSENSE_SENSOR_FLAG_TIMESTAMP);
-	TEST_EQ(data[0].timestamp, now - 18000, "%u");
+	TEST_EQ(data[0].timestamp, now - 18, "%u");
 	TEST_BITS_SET(data[2].flags, MOTIONSENSE_SENSOR_FLAG_TIMESTAMP);
 	/* TODO(b/142892004): mock __hw_clock_source_read so we can check for
 	 * exact TS.
@@ -269,47 +302,75 @@ static int test_spread_data_in_window(void)
 	return EC_SUCCESS;
 }
 
-static int test_spread_data_by_collection_rate(void)
+static int test_spread_data_on_overflow(void)
 {
 	const uint32_t now = __hw_clock_source_read();
-	int read_count;
+	const int fill_count = (CONFIG_ACCEL_FIFO_SIZE / 2) - 1;
+	int i, read_count;
 
+	/* Set up the sensors */
 	motion_sensors[0].oversampling_ratio = 1;
-	motion_sensors[0].collection_rate = 20000; /* ns */
-	motion_sense_fifo_stage_data(data, motion_sensors, 3, now - 20500);
-	motion_sense_fifo_stage_data(data, motion_sensors, 3, now - 20500);
-	motion_sense_fifo_commit_data();
-	read_count = motion_sense_fifo_read(
-		sizeof(data), CONFIG_ACCEL_FIFO_SIZE, data, &data_bytes_read);
+	motion_sensors[1].oversampling_ratio = 1;
+	motion_sense_set_data_period(0, 20 /* us */);
+
+	/* Add 1 sample for sensor [1]. This will be evicted. */
+	data->sensor_num = 1;
+	motion_sense_fifo_stage_data(data, motion_sensors + 1, 3, 0);
+
+	/*
+	 * Fill the rest of the fifo, every 2 entries will have the same
+	 * timestamp simulating have 2 entries on the hardware FIFO per read.
+	 */
+	data->sensor_num = 0;
+	for (i = 0; i < fill_count; i++) {
+		int ts = now - ((fill_count - i) / 2) * 10;
+
+		motion_sense_fifo_stage_data(data, motion_sensors, 3, ts);
+	}
+
+	/* Insert an async event which also causes a commit */
+	motion_sense_fifo_insert_async_event(motion_sensors, ASYNC_EVENT_FLUSH);
+
+	read_count =
+		motion_sense_fifo_read(sizeof(data), 4, data, &data_bytes_read);
+
+	/* Verify that we read 4 entries */
 	TEST_EQ(read_count, 4, "%d");
+
+	/* Verify that entries 0 and 2 are timestamps (1 and 3 are data) */
 	TEST_BITS_SET(data[0].flags, MOTIONSENSE_SENSOR_FLAG_TIMESTAMP);
-	TEST_EQ(data[0].timestamp, now - 20500, "%u");
 	TEST_BITS_SET(data[2].flags, MOTIONSENSE_SENSOR_FLAG_TIMESTAMP);
-	TEST_EQ(data[2].timestamp, now - 500, "%u");
+
+	/*
+	 * Verify that the first read entry is the first one added in the for
+	 * loop above.
+	 */
+	TEST_EQ(data[0].sensor_num, 0, "%u");
+	TEST_EQ(data[0].timestamp, now - ((fill_count - 1) / 2) * 10, "%u");
+
+	/* Verify that the timestamp was spread */
+	TEST_NE(data[0].timestamp, data[2].timestamp, "%u");
 
 	return EC_SUCCESS;
 }
 
-static int test_spread_double_commit_same_timestamp(void)
+static int test_spread_data_by_collection_rate(void)
 {
 	const uint32_t now = __hw_clock_source_read();
 	int read_count;
 
 	motion_sensors[0].oversampling_ratio = 1;
-	motion_sensors[0].collection_rate = 20000; /* ns */
-	motion_sense_fifo_stage_data(data, motion_sensors, 3, now - 20500);
-	motion_sense_fifo_commit_data();
-	motion_sense_fifo_stage_data(data, motion_sensors, 3, now - 20500);
+	motion_sense_set_data_period(0, 20 /* us */);
+	motion_sense_fifo_stage_data(data, motion_sensors, 3, now - 25);
+	motion_sense_fifo_stage_data(data, motion_sensors, 3, now - 25);
 	motion_sense_fifo_commit_data();
-
 	read_count = motion_sense_fifo_read(
 		sizeof(data), CONFIG_ACCEL_FIFO_SIZE, data, &data_bytes_read);
 	TEST_EQ(read_count, 4, "%d");
 	TEST_BITS_SET(data[0].flags, MOTIONSENSE_SENSOR_FLAG_TIMESTAMP);
-	TEST_EQ(data[0].timestamp, now - 20500, "%u");
+	TEST_EQ(data[0].timestamp, now - 25, "%u");
 	TEST_BITS_SET(data[2].flags, MOTIONSENSE_SENSOR_FLAG_TIMESTAMP);
-	TEST_GT(time_until(now - 20500, data[2].timestamp), 10000, "%u");
-	TEST_LE(time_until(now - 20500, data[2].timestamp), 20000, "%u");
+	TEST_EQ(data[2].timestamp, now - 5, "%u");
 
 	return EC_SUCCESS;
 }
@@ -320,25 +381,112 @@ static int test_commit_non_data_or_timestamp_entries(void)
 	int read_count;
 
 	motion_sensors[0].oversampling_ratio = 1;
-	motion_sensors[0].collection_rate = 20000; /* ns */
+	motion_sense_set_data_period(0, 20 /* us */);
 
 	/* Insert non-data entry */
 	data[0].flags = MOTIONSENSE_SENSOR_FLAG_ODR;
-	motion_sense_fifo_stage_data(data, motion_sensors, 3, now - 20500);
+	motion_sense_fifo_stage_data(data, motion_sensors, 3, now - 25);
 
 	/* Insert data entry */
 	data[0].flags = 0;
-	motion_sense_fifo_stage_data(data, motion_sensors, 3, now - 20500);
+	motion_sense_fifo_stage_data(data, motion_sensors, 3, now - 25);
 
 	motion_sense_fifo_commit_data();
 	read_count = motion_sense_fifo_read(
 		sizeof(data), CONFIG_ACCEL_FIFO_SIZE, data, &data_bytes_read);
 	TEST_EQ(read_count, 4, "%d");
 	TEST_BITS_SET(data[0].flags, MOTIONSENSE_SENSOR_FLAG_TIMESTAMP);
-	TEST_EQ(data[0].timestamp, now - 20500, "%u");
+	TEST_EQ(data[0].timestamp, now - 25, "%u");
 	TEST_BITS_SET(data[1].flags, MOTIONSENSE_SENSOR_FLAG_ODR);
 	TEST_BITS_SET(data[2].flags, MOTIONSENSE_SENSOR_FLAG_TIMESTAMP);
-	TEST_EQ(data[2].timestamp, now - 20500, "%u");
+	TEST_EQ(data[2].timestamp, now - 25, "%u");
+
+	return EC_SUCCESS;
+}
+
+static int test_get_info_size(void)
+{
+	uint8_t fifo_info_buffer
+		[sizeof(struct ec_response_motion_sense_fifo_info) +
+		 sizeof(uint16_t) * MAX_MOTION_SENSORS];
+	struct ec_response_motion_sense_fifo_info *fifo_info =
+		(void *)fifo_info_buffer;
+
+	motion_sense_fifo_get_info(fifo_info, /*reset=*/false);
+	TEST_EQ(fifo_info->size, CONFIG_ACCEL_FIFO_SIZE, "%d");
+
+	return EC_SUCCESS;
+}
+
+static int test_check_ap_interval_set_one_sample(void)
+{
+	uint32_t now;
+	int read_count;
+
+	/* The AP needs data every sample (200 Hz). */
+	motion_sensors[0].config[SENSOR_CONFIG_AP].ec_rate = 5000; /* us */
+	motion_sensors[0].oversampling_ratio = 1;
+	motion_sense_set_data_period(0, 5000 /* us */);
+	msleep(5);
+	now = __hw_clock_source_read();
+
+	motion_sense_fifo_stage_data(data, motion_sensors, 3, now);
+	motion_sense_fifo_commit_data();
+	read_count = motion_sense_fifo_read(
+		sizeof(data), CONFIG_ACCEL_FIFO_SIZE, data, &data_bytes_read);
+	TEST_EQ(read_count, 2, "%d");
+	TEST_BITS_SET(data[0].flags, MOTIONSENSE_SENSOR_FLAG_TIMESTAMP);
+	TEST_EQ(data[0].timestamp, now, "%u");
+	TEST_EQ(motion_sense_fifo_interrupt_needed(), 1, "%d");
+
+	/* Simulate interrupt processing. */
+	motion_sense_fifo_reset_needed_flags();
+
+	msleep(5);
+	now = __hw_clock_source_read();
+	motion_sense_fifo_stage_data(data, motion_sensors, 3, now);
+	motion_sense_fifo_commit_data();
+	read_count = motion_sense_fifo_read(
+		sizeof(data), CONFIG_ACCEL_FIFO_SIZE, data, &data_bytes_read);
+	TEST_EQ(read_count, 2, "%d");
+	TEST_BITS_SET(data[0].flags, MOTIONSENSE_SENSOR_FLAG_TIMESTAMP);
+	TEST_EQ(data[0].timestamp, now, "%u");
+	TEST_EQ(motion_sense_fifo_interrupt_needed(), 1, "%d");
+
+	return EC_SUCCESS;
+}
+
+static int test_check_ap_interval_set_multiple_sample(void)
+{
+	uint32_t now;
+	int read_count;
+
+	/* The AP needs data every 2 samples. */
+	motion_sensors[0].config[SENSOR_CONFIG_AP].ec_rate = 10000; /* us */
+	motion_sensors[0].oversampling_ratio = 1;
+	motion_sense_set_data_period(0, 5000 /* us */);
+	msleep(5);
+	now = __hw_clock_source_read();
+
+	motion_sense_fifo_stage_data(data, motion_sensors, 3, now);
+	motion_sense_fifo_commit_data();
+	read_count = motion_sense_fifo_read(
+		sizeof(data), CONFIG_ACCEL_FIFO_SIZE, data, &data_bytes_read);
+	TEST_EQ(read_count, 2, "%d");
+	TEST_BITS_SET(data[0].flags, MOTIONSENSE_SENSOR_FLAG_TIMESTAMP);
+	TEST_EQ(data[0].timestamp, now, "%u");
+	TEST_EQ(motion_sense_fifo_interrupt_needed(), 0, "%d");
+
+	msleep(5);
+	now = __hw_clock_source_read();
+	motion_sense_fifo_stage_data(data, motion_sensors, 3, now);
+	motion_sense_fifo_commit_data();
+	read_count = motion_sense_fifo_read(
+		sizeof(data), CONFIG_ACCEL_FIFO_SIZE, data, &data_bytes_read);
+	TEST_EQ(read_count, 2, "%d");
+	TEST_BITS_SET(data[0].flags, MOTIONSENSE_SENSOR_FLAG_TIMESTAMP);
+	TEST_EQ(data[0].timestamp, now, "%u");
+	TEST_EQ(motion_sense_fifo_interrupt_needed(), 1, "%d");
 
 	return EC_SUCCESS;
 }
@@ -348,12 +496,12 @@ void before_test(void)
 	motion_sense_fifo_commit_data();
 	motion_sense_fifo_read(sizeof(data), CONFIG_ACCEL_FIFO_SIZE, &data,
 			       &data_bytes_read);
-	motion_sense_fifo_reset_wake_up_needed();
+	motion_sense_fifo_reset_needed_flags();
 	memset(data, 0, sizeof(data));
 	motion_sense_fifo_reset();
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 	motion_sense_fifo_init();
@@ -369,9 +517,12 @@ void run_test(int argc, char **argv)
 	RUN_TEST(test_add_data_no_spreading_when_different_sensors);
 	RUN_TEST(test_add_data_no_spreading_different_timestamps);
 	RUN_TEST(test_spread_data_in_window);
+	RUN_TEST(test_spread_data_on_overflow);
 	RUN_TEST(test_spread_data_by_collection_rate);
-	RUN_TEST(test_spread_double_commit_same_timestamp);
 	RUN_TEST(test_commit_non_data_or_timestamp_entries);
+	RUN_TEST(test_get_info_size);
+	RUN_TEST(test_check_ap_interval_set_one_sample);
+	RUN_TEST(test_check_ap_interval_set_multiple_sample);
 
 	test_print_result();
 }
diff --git a/test/motion_sense_fifo.tasklist b/test/motion_sense_fifo.tasklist
index 0e3696c3f0..844ddb6c10 100644
--- a/test/motion_sense_fifo.tasklist
+++ b/test/motion_sense_fifo.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,5 +6,4 @@
 /**
  * See CONFIG_TASK_LIST in config.h for details.
  */
-#define CONFIG_TEST_TASK_LIST \
-	TASK_TEST(MOTIONSENSE, motion_sense_task, NULL, TASK_STACK_SIZE)
+#define CONFIG_TEST_TASK_LIST
diff --git a/test/mpu.c b/test/mpu.c
index 25b2c58903..dfc5877d5a 100644
--- a/test/mpu.c
+++ b/test/mpu.c
@@ -1,15 +1,24 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <stdbool.h>
+/* This test file meant to be executed on a real device. Example:
+ * 1. make tests BOARD=bloonchipper
+ * 2. servod --board=bloonchipper
+ * 3. flash_ec --board bloonchipper --image build/bloonchipper/test-mpu.bin
+ * 4. Open console via dut-control raw_fpmcu_console_uart_pty
+ * 5. runtest on console
+ */
+
 #include "mpu.h"
 #include "mpu_private.h"
 #include "string.h"
 #include "system.h"
 #include "test_util.h"
 
+#include <stdbool.h>
+
 struct mpu_info {
 	bool has_mpu;
 	int num_mpu_regions;
@@ -17,22 +26,18 @@ struct mpu_info {
 };
 
 #if defined(CHIP_VARIANT_STM32F412)
-struct mpu_info mpu_info = {
-	.has_mpu = true,
-	.num_mpu_regions = 8,
-	.mpu_is_unified = true
-};
+struct mpu_info mpu_info = { .has_mpu = true,
+			     .num_mpu_regions = 8,
+			     .mpu_is_unified = true };
 
 struct mpu_rw_regions expected_rw_regions = { .num_regions = 2,
 					      .addr = { 0x08060000,
 							0x08080000 },
 					      .size = { 0x20000, 0x80000 } };
 #elif defined(CHIP_VARIANT_STM32H7X3)
-struct mpu_info mpu_info = {
-	.has_mpu = true,
-	.num_mpu_regions = 16,
-	.mpu_is_unified = true
-};
+struct mpu_info mpu_info = { .has_mpu = true,
+			     .num_mpu_regions = 16,
+			     .mpu_is_unified = true };
 
 struct mpu_rw_regions expected_rw_regions = { .num_regions = 1,
 					      .addr = { 0x08100000,
@@ -75,7 +80,7 @@ test_static int test_mpu_update_region_valid_region(void)
 {
 	volatile char data __maybe_unused;
 
-	char * const ram_base = (char * const)CONFIG_RAM_BASE;
+	char *const ram_base = (char *const)CONFIG_RAM_BASE;
 	const uint8_t size_bit = 5;
 	uint16_t mpu_attr = MPU_ATTR_NO_NO;
 
@@ -176,7 +181,20 @@ test_static int test_mpu_get_rw_regions(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+test_static int test_align_down_to_bits(void)
+{
+	uint32_t addr = 0x87654321;
+
+	TEST_EQ(align_down_to_bits(addr, 0), addr, "%d");
+	TEST_EQ(align_down_to_bits(addr, 1), 0x87654320, "%d");
+	TEST_EQ(align_down_to_bits(addr, 30), 0x80000000, "%d");
+	TEST_EQ(align_down_to_bits(addr, 31), 0x80000000, "%d");
+	TEST_EQ(align_down_to_bits(addr, 32), addr, "%d");
+	TEST_EQ(align_down_to_bits(addr, 33), addr, "%d");
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
 {
 	enum ec_image cur_image = system_get_image_copy();
 
@@ -215,6 +233,8 @@ void run_test(int argc, char **argv)
 	RUN_TEST(reset_mpu);
 	RUN_TEST(test_mpu_get_rw_regions);
 	RUN_TEST(reset_mpu);
+	RUN_TEST(test_align_down_to_bits);
+	RUN_TEST(reset_mpu);
 	/* This test must be last because it generates a panic */
 	RUN_TEST(test_mpu_update_region_valid_region);
 	RUN_TEST(reset_mpu);
diff --git a/test/mpu.tasklist b/test/mpu.tasklist
index 51734f058d..a1f1a94e2d 100644
--- a/test/mpu.tasklist
+++ b/test/mpu.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/mutex.c b/test/mutex.c
index d5e7e09c51..b4066c8c4f 100644
--- a/test/mutex.c
+++ b/test/mutex.c
@@ -1,13 +1,13 @@
-/* Copyright 2011 The Chromium OS Authors. All rights reserved.
+/* Copyright 2011 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
- * Copyright 2011 Google Inc.
+ * Copyright 2011 Google LLC
  *
  * Tasks for mutexes basic tests.
  */
 
-#include "console.h"
 #include "common.h"
+#include "console.h"
 #include "task.h"
 #include "test_util.h"
 #include "timer.h"
@@ -22,7 +22,7 @@ static struct mutex mtx;
 
 int mutex_random_task(void *unused)
 {
-	char letter = 'A'+(TASK_ID_MTX3A - task_get_current());
+	char letter = 'A' + (TASK_ID_MTX3A - task_get_current());
 	/* wait to be activated */
 
 	while (1) {
@@ -83,7 +83,8 @@ int mutex_main_task(void *unused)
 	/* --- Serialization to test simple contention --- */
 	ccprintf("Simple contention :\n");
 	/* lock the mutex from the other task */
-	task_set_event(TASK_ID_MTX2, TASK_EVENT_WAKE, 1);
+	task_set_event(TASK_ID_MTX2, TASK_EVENT_WAKE);
+	task_wait_event(0);
 	/* block on the mutex */
 	ccprintf("MTX1: blocking...\n");
 	mutex_lock(&mtx);
@@ -109,7 +110,7 @@ int mutex_main_task(void *unused)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	wait_for_task_started();
 	task_wake(TASK_ID_MTX1);
diff --git a/test/mutex.tasklist b/test/mutex.tasklist
index 8e3d08ddc2..46cdad7fa1 100644
--- a/test/mutex.tasklist
+++ b/test/mutex.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/newton_fit.c b/test/newton_fit.c
index 9648fbfd9a..62f4710f0c 100644
--- a/test/newton_fit.c
+++ b/test/newton_fit.c
@@ -1,12 +1,13 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "common.h"
-#include "newton_fit.h"
 #include "motion_sense.h"
+#include "newton_fit.h"
 #include "test_util.h"
+
 #include <stdio.h>
 
 /*
@@ -126,7 +127,7 @@ static int test_newton_fit_calculate(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/newton_fit.tasklist b/test/newton_fit.tasklist
index 5ffe662d01..2d4595f76a 100644
--- a/test/newton_fit.tasklist
+++ b/test/newton_fit.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/nvidia_gpu.c b/test/nvidia_gpu.c
new file mode 100644
index 0000000000..3e03197e50
--- /dev/null
+++ b/test/nvidia_gpu.c
@@ -0,0 +1,214 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Tests for Nvidia GPU.
+ */
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "common.h"
+#include "console.h"
+#include "driver/nvidia_gpu.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "task.h"
+#include "test_util.h"
+#include "throttle_ap.h"
+#include "timer.h"
+#include "util.h"
+
+#include <stdio.h>
+
+struct d_notify_policy d_notify_policies[] = {
+	AC_ATLEAST_W(100), AC_ATLEAST_W(65), AC_DC,
+	DC_ATMOST_SOC(20), DC_ATMOST_SOC(5),
+};
+
+extern enum d_notify_level d_notify_level;
+extern bool policy_initialized;
+extern const struct d_notify_policy *d_notify_policy;
+static int extpower_presence = 1;
+static int nvidia_gpu_acoff_odl = 1;
+static int charge_percent = 100;
+static int charge_power = 100;
+static uint8_t *memmap_gpu;
+
+__override int charge_get_percent(void)
+{
+	return charge_percent;
+}
+
+__override int charge_manager_get_power_limit_uw(void)
+{
+	return charge_power * 1000000;
+}
+
+__override int extpower_is_present(void)
+{
+	return extpower_presence;
+}
+
+__override int gpio_get_level(enum gpio_signal signal)
+{
+	if (signal == GPIO_NVIDIA_GPU_ACOFF_ODL)
+		return nvidia_gpu_acoff_odl;
+	return 0;
+}
+
+__override void gpio_set_level(enum gpio_signal signal, int value)
+{
+	if (signal == GPIO_NVIDIA_GPU_ACOFF_ODL)
+		nvidia_gpu_acoff_odl = value;
+}
+
+static void setup(int extpower, int gpio_acoff, int percent, int power,
+		  enum d_notify_level level)
+{
+	extpower_presence = extpower;
+	nvidia_gpu_acoff_odl = gpio_acoff;
+	charge_percent = percent;
+	charge_power = power;
+	d_notify_level = level;
+	*memmap_gpu = level;
+}
+
+static void plug_ac(int plug)
+{
+	extpower_presence = plug;
+	hook_notify(HOOK_AC_CHANGE);
+}
+
+static int check_d_notify_level(enum d_notify_level expected_level)
+{
+	TEST_EQ(d_notify_level, expected_level, "%d");
+	TEST_EQ(*memmap_gpu, expected_level, "%d");
+
+	return EC_SUCCESS;
+}
+
+static int test_startup(void)
+{
+	/* Test initial values after HOOK_INIT. Don't call setup(). */
+
+	TEST_ASSERT(IS_ENABLED(HAS_GPU_DRIVER));
+	TEST_ASSERT(policy_initialized);
+	TEST_NE(d_notify_policy, NULL, "%p");
+	TEST_EQ(check_d_notify_level(D_NOTIFY_1), EC_SUCCESS, "%d");
+
+	return EC_SUCCESS;
+}
+
+static int test_ac_unplug(void)
+{
+	setup(1, 1, 100, 100, D_NOTIFY_1);
+
+	/* Unplug AC. D1 -> D5 */
+	plug_ac(0);
+	throttle_gpu(THROTTLE_ON, THROTTLE_HARD, THROTTLE_SRC_AC);
+	TEST_EQ(nvidia_gpu_acoff_odl, 0, "%d");
+	TEST_EQ(check_d_notify_level(D_NOTIFY_5), EC_SUCCESS, "%d");
+	TEST_ASSERT(host_is_event_set(EC_HOST_EVENT_GPU));
+	host_clear_events(EC_HOST_EVENT_MASK(EC_HOST_EVENT_GPU));
+
+	/* Wait half of NVIDIA_GPU_ACOFF_DURATION. D5 -> D5. */
+	usleep(NVIDIA_GPU_ACOFF_DURATION / 2);
+	TEST_EQ(nvidia_gpu_acoff_odl, 0, "%d");
+	TEST_EQ(check_d_notify_level(D_NOTIFY_5), EC_SUCCESS, "%d");
+	TEST_ASSERT(!host_is_event_set(EC_HOST_EVENT_GPU));
+
+	/* Wait another half of NVIDIA_GPU_ACOFF_DURATION. D5 -> D3. */
+	usleep(NVIDIA_GPU_ACOFF_DURATION / 2);
+	TEST_EQ(nvidia_gpu_acoff_odl, 1, "%d");
+	TEST_EQ(check_d_notify_level(D_NOTIFY_3), EC_SUCCESS, "%d");
+	TEST_ASSERT(host_is_event_set(EC_HOST_EVENT_GPU));
+	host_clear_events(EC_HOST_EVENT_MASK(EC_HOST_EVENT_GPU));
+
+	/* Discharge to 60%. D3 -> D3. */
+	charge_percent = 60;
+	hook_notify(HOOK_BATTERY_SOC_CHANGE);
+	TEST_EQ(nvidia_gpu_acoff_odl, 1, "%d");
+	TEST_EQ(check_d_notify_level(D_NOTIFY_3), EC_SUCCESS, "%d");
+	TEST_ASSERT(!host_is_event_set(EC_HOST_EVENT_GPU));
+
+	/* Discharge to 20%. D3 -> D4 */
+	charge_percent = 20;
+	hook_notify(HOOK_BATTERY_SOC_CHANGE);
+	TEST_EQ(nvidia_gpu_acoff_odl, 1, "%d");
+	TEST_EQ(check_d_notify_level(D_NOTIFY_4), EC_SUCCESS, "%d");
+	TEST_ASSERT(host_is_event_set(EC_HOST_EVENT_GPU));
+	host_clear_events(EC_HOST_EVENT_MASK(EC_HOST_EVENT_GPU));
+
+	/* Discharge to 5%. D4 -> D5 */
+	charge_percent = 5;
+	hook_notify(HOOK_BATTERY_SOC_CHANGE);
+	TEST_EQ(nvidia_gpu_acoff_odl, 1, "%d");
+	TEST_EQ(check_d_notify_level(D_NOTIFY_5), EC_SUCCESS, "%d");
+	TEST_ASSERT(host_is_event_set(EC_HOST_EVENT_GPU));
+	host_clear_events(EC_HOST_EVENT_MASK(EC_HOST_EVENT_GPU));
+
+	return EC_SUCCESS;
+}
+
+static int test_ac_plug(void)
+{
+	/* Plug 100W AC. D5 -> D1. */
+	setup(0, 1, 5, 100, D_NOTIFY_5);
+	plug_ac(1);
+	throttle_gpu(THROTTLE_OFF, THROTTLE_HARD, THROTTLE_SRC_AC);
+	TEST_EQ(nvidia_gpu_acoff_odl, 1, "%d");
+	TEST_EQ(check_d_notify_level(D_NOTIFY_1), EC_SUCCESS, "%d");
+	TEST_ASSERT(host_is_event_set(EC_HOST_EVENT_GPU));
+	host_clear_events(EC_HOST_EVENT_MASK(EC_HOST_EVENT_GPU));
+
+	/* Plug 65W AC. D5 -> D2. */
+	setup(0, 1, 5, 65, D_NOTIFY_5);
+	plug_ac(1);
+	throttle_gpu(THROTTLE_OFF, THROTTLE_HARD, THROTTLE_SRC_AC);
+	TEST_EQ(nvidia_gpu_acoff_odl, 1, "%d");
+	TEST_EQ(check_d_notify_level(D_NOTIFY_2), EC_SUCCESS, "%d");
+	TEST_ASSERT(host_is_event_set(EC_HOST_EVENT_GPU));
+	host_clear_events(EC_HOST_EVENT_MASK(EC_HOST_EVENT_GPU));
+
+	/* Plug 35W AC. D5 -> D3. */
+	setup(0, 1, 5, 35, D_NOTIFY_5);
+	plug_ac(1);
+	throttle_gpu(THROTTLE_OFF, THROTTLE_HARD, THROTTLE_SRC_AC);
+	TEST_EQ(nvidia_gpu_acoff_odl, 1, "%d");
+	TEST_EQ(check_d_notify_level(D_NOTIFY_3), EC_SUCCESS, "%d");
+	TEST_ASSERT(host_is_event_set(EC_HOST_EVENT_GPU));
+	host_clear_events(EC_HOST_EVENT_MASK(EC_HOST_EVENT_GPU));
+
+	return EC_SUCCESS;
+}
+
+static int test_overt(void)
+{
+	nvidia_gpu_over_temp(1);
+	TEST_ASSERT(*memmap_gpu & EC_MEMMAP_GPU_OVERT_BIT);
+	TEST_ASSERT(host_is_event_set(EC_HOST_EVENT_GPU));
+
+	nvidia_gpu_over_temp(0);
+	TEST_ASSERT(!(*memmap_gpu & EC_MEMMAP_GPU_OVERT_BIT));
+	TEST_ASSERT(host_is_event_set(EC_HOST_EVENT_GPU));
+
+	return EC_SUCCESS;
+}
+
+static void board_gpu_init(void)
+{
+	nvidia_gpu_init_policy(d_notify_policies);
+}
+DECLARE_HOOK(HOOK_INIT, board_gpu_init, HOOK_PRIO_DEFAULT);
+
+void run_test(int argc, const char **argv)
+{
+	memmap_gpu = (uint8_t *)host_get_memmap(EC_MEMMAP_GPU);
+
+	test_chipset_on();
+
+	RUN_TEST(test_startup);
+	RUN_TEST(test_ac_unplug);
+	RUN_TEST(test_ac_plug);
+	RUN_TEST(test_overt);
+	test_print_result();
+}
diff --git a/test/nvidia_gpu.tasklist b/test/nvidia_gpu.tasklist
new file mode 100644
index 0000000000..8918b4ee2f
--- /dev/null
+++ b/test/nvidia_gpu.tasklist
@@ -0,0 +1,10 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST \
+	TASK_TEST(CHIPSET, chipset_task, NULL, TASK_STACK_SIZE)
diff --git a/test/online_calibration.c b/test/online_calibration.c
index e9fff2430e..c845378012 100644
--- a/test/online_calibration.c
+++ b/test/online_calibration.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,6 +10,7 @@
 #include "online_calibration.h"
 #include "test_util.h"
 #include "timer.h"
+
 #include <stdio.h>
 
 int mkbp_send_event(uint8_t event_type)
@@ -44,43 +45,18 @@ static int mock_read_temp(const struct motion_sensor_t *s, int *temp)
 	return EC_ERROR_UNKNOWN;
 }
 
-struct mock_get_range_result {
-	struct motion_sensor_t *s;
-	int ret;
-	struct mock_get_range_result *next;
-};
-
-static struct mock_get_range_result *mock_get_range_results;
-
-static int mock_get_range(const struct motion_sensor_t *s)
-{
-	struct mock_get_range_result *ptr = mock_get_range_results;
-
-	while (ptr) {
-		if (ptr->s == s)
-			return ptr->ret;
-		ptr = ptr->next;
-	}
-
-	return 4;
-}
-
 static struct accelgyro_drv mock_sensor_driver = {
 	.read_temp = mock_read_temp,
-	.get_range = mock_get_range,
 };
 
-static struct accel_cal_algo base_accel_cal_algos[] = {
-	{
-		.newton_fit = NEWTON_FIT(4, 15, FLOAT_TO_FP(0.01f),
-					 FLOAT_TO_FP(0.25f),
-					 FLOAT_TO_FP(1.0e-8f), 100),
-	}
-};
+static struct accel_cal_algo base_accel_cal_algos[] = { {
+	.newton_fit = NEWTON_FIT(4, 15, FLOAT_TO_FP(0.01f), FLOAT_TO_FP(0.25f),
+				 FLOAT_TO_FP(1.0e-8f), 100),
+} };
 
 static struct accel_cal base_accel_cal_data = {
-	.still_det = STILL_DET(FLOAT_TO_FP(0.00025f), 800 * MSEC, 1200 * MSEC,
-			       5),
+	.still_det =
+		STILL_DET(FLOAT_TO_FP(0.00025f), 800 * MSEC, 1200 * MSEC, 5),
 	.algos = base_accel_cal_algos,
 	.num_temp_windows = ARRAY_SIZE(base_accel_cal_algos),
 };
@@ -90,9 +66,8 @@ static struct mag_cal_t lid_mag_cal_data;
 static bool next_accel_cal_accumulate_result;
 static fpv3_t next_accel_cal_bias;
 
-bool accel_cal_accumulate(
-	struct accel_cal *cal, uint32_t sample_time, fp_t x, fp_t y, fp_t z,
-	fp_t temp)
+bool accel_cal_accumulate(struct accel_cal *cal, uint32_t sample_time, fp_t x,
+			  fp_t y, fp_t z, fp_t temp)
 {
 	if (next_accel_cal_accumulate_result) {
 		cal->bias[X] = next_accel_cal_bias[X];
@@ -105,6 +80,7 @@ bool accel_cal_accumulate(
 struct motion_sensor_t motion_sensors[] = {
 	[BASE] = {
 		.type = MOTIONSENSE_TYPE_ACCEL,
+		.default_range = 4,
 		.drv = &mock_sensor_driver,
 		.online_calib_data[0] = {
 			.type_specific_data = &base_accel_cal_data,
@@ -112,6 +88,7 @@ struct motion_sensor_t motion_sensors[] = {
 	},
 	[LID] = {
 		.type = MOTIONSENSE_TYPE_MAG,
+		.default_range = 4,
 		.drv = &mock_sensor_driver,
 		.online_calib_data[0] = {
 			.type_specific_data = &lid_mag_cal_data,
@@ -130,8 +107,8 @@ static int test_read_temp_on_stage(void)
 
 	mock_read_temp_results = &expected;
 	data.sensor_num = BASE;
-	rc = online_calibration_process_data(
-		&data, &motion_sensors[0], __hw_clock_source_read());
+	rc = online_calibration_process_data(&data, &motion_sensors[0],
+					     __hw_clock_source_read());
 
 	TEST_EQ(rc, EC_SUCCESS, "%d");
 	TEST_EQ(expected.used_count, 1, "%d");
@@ -148,12 +125,12 @@ static int test_read_temp_from_cache_on_stage(void)
 
 	mock_read_temp_results = &expected;
 	data.sensor_num = BASE;
-	rc = online_calibration_process_data(
-		&data, &motion_sensors[0], __hw_clock_source_read());
+	rc = online_calibration_process_data(&data, &motion_sensors[0],
+					     __hw_clock_source_read());
 	TEST_EQ(rc, EC_SUCCESS, "%d");
 
-	rc = online_calibration_process_data(
-		&data, &motion_sensors[0], __hw_clock_source_read());
+	rc = online_calibration_process_data(&data, &motion_sensors[0],
+					     __hw_clock_source_read());
 	TEST_EQ(rc, EC_SUCCESS, "%d");
 
 	TEST_EQ(expected.used_count, 1, "%d");
@@ -170,13 +147,13 @@ static int test_read_temp_twice_after_cache_stale(void)
 
 	mock_read_temp_results = &expected;
 	data.sensor_num = BASE;
-	rc = online_calibration_process_data(
-		&data, &motion_sensors[0], __hw_clock_source_read());
+	rc = online_calibration_process_data(&data, &motion_sensors[0],
+					     __hw_clock_source_read());
 	TEST_EQ(rc, EC_SUCCESS, "%d");
 
 	sleep(2);
-	rc = online_calibration_process_data(
-		&data, &motion_sensors[0], __hw_clock_source_read());
+	rc = online_calibration_process_data(&data, &motion_sensors[0],
+					     __hw_clock_source_read());
 	TEST_EQ(rc, EC_SUCCESS, "%d");
 
 	TEST_EQ(expected.used_count, 2, "%d");
@@ -196,21 +173,21 @@ static int test_new_calibration_value(void)
 	next_accel_cal_accumulate_result = false;
 	data.sensor_num = BASE;
 
-	rc = online_calibration_process_data(
-		&data, &motion_sensors[BASE], __hw_clock_source_read());
+	rc = online_calibration_process_data(&data, &motion_sensors[BASE],
+					     __hw_clock_source_read());
 	TEST_EQ(rc, EC_SUCCESS, "%d");
 	TEST_EQ(online_calibration_has_new_values(), false, "%d");
 
 	next_accel_cal_accumulate_result = true;
-	next_accel_cal_bias[X] = 0.01f;		/* expect:  81  */
-	next_accel_cal_bias[Y] = -0.02f;	/* expect: -163 */
-	next_accel_cal_bias[Z] = 0;		/* expect:    0 */
-	rc = online_calibration_process_data(
-		&data, &motion_sensors[BASE], __hw_clock_source_read());
+	next_accel_cal_bias[X] = 0.01f; /* expect:  81  */
+	next_accel_cal_bias[Y] = -0.02f; /* expect: -163 */
+	next_accel_cal_bias[Z] = 0; /* expect:    0 */
+	rc = online_calibration_process_data(&data, &motion_sensors[BASE],
+					     __hw_clock_source_read());
 	TEST_EQ(rc, EC_SUCCESS, "%d");
 	TEST_EQ(online_calibration_has_new_values(), true, "%d");
 
-	rc = online_calibration_read(BASE, cal_data.data);
+	rc = online_calibration_read(&motion_sensors[BASE], &cal_data);
 	TEST_EQ(rc, true, "%d");
 	TEST_EQ(cal_data.data[X], 81, "%d");
 	TEST_EQ(cal_data.data[Y], -163, "%d");
@@ -236,8 +213,8 @@ int test_mag_reading_updated_cal(void)
 	init_mag_cal(&expected_results);
 	mag_cal_update(&expected_results, test_values);
 
-	rc = online_calibration_process_data(
-		&data, &motion_sensors[LID], __hw_clock_source_read());
+	rc = online_calibration_process_data(&data, &motion_sensors[LID],
+					     __hw_clock_source_read());
 	TEST_EQ(rc, EC_SUCCESS, "%d");
 	TEST_EQ(expected_results.kasa_fit.nsamples,
 		lid_mag_cal_data.kasa_fit.nsamples, "%d");
@@ -251,7 +228,7 @@ void before_test(void)
 	online_calibration_init();
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/online_calibration.tasklist b/test/online_calibration.tasklist
index 5b67239ff8..a9ba96907d 100644
--- a/test/online_calibration.tasklist
+++ b/test/online_calibration.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/online_calibration_spoof.c b/test/online_calibration_spoof.c
new file mode 100644
index 0000000000..31c17bb8dd
--- /dev/null
+++ b/test/online_calibration_spoof.c
@@ -0,0 +1,197 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "accel_cal.h"
+#include "accelgyro.h"
+#include "gyro_cal.h"
+#include "gyro_cal_init_for_test.h"
+#include "hwtimer.h"
+#include "mag_cal.h"
+#include "online_calibration.h"
+#include "test_util.h"
+#include "timer.h"
+
+#include <stdio.h>
+
+int mkbp_send_event(uint8_t event_type)
+{
+	return 1;
+}
+
+/*
+ * Mocked driver (can be re-used for all sensors).
+ */
+
+static int mock_read_temp(const struct motion_sensor_t *s, int *temp)
+{
+	if (temp)
+		*temp = 200;
+	return EC_SUCCESS;
+}
+
+static struct accelgyro_drv mock_sensor_driver = {
+	.read_temp = mock_read_temp,
+};
+
+/*
+ * Accelerometer, magnetometer, and gyroscope data structs.
+ */
+
+static struct accel_cal_algo accel_cal_algos[] = { {
+	.newton_fit = NEWTON_FIT(4, 15, FLOAT_TO_FP(0.01f), FLOAT_TO_FP(0.25f),
+				 FLOAT_TO_FP(1.0e-8f), 100),
+} };
+
+static struct accel_cal accel_cal_data = {
+	.still_det =
+		STILL_DET(FLOAT_TO_FP(0.00025f), 800 * MSEC, 1200 * MSEC, 5),
+	.algos = accel_cal_algos,
+	.num_temp_windows = ARRAY_SIZE(accel_cal_algos),
+};
+
+static struct mag_cal_t mag_cal_data;
+
+static struct gyro_cal gyro_cal_data;
+
+/*
+ * Motion sensor array and count.
+ */
+
+struct motion_sensor_t motion_sensors[] = {
+	{
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.default_range = 4,
+		.drv = &mock_sensor_driver,
+		.online_calib_data[0] = {
+			.type_specific_data = &accel_cal_data,
+		},
+	},
+	{
+		.type = MOTIONSENSE_TYPE_MAG,
+		.default_range = 4,
+		.drv = &mock_sensor_driver,
+		.online_calib_data[0] = {
+			.type_specific_data = &mag_cal_data,
+		},
+	},
+	{
+		.type = MOTIONSENSE_TYPE_GYRO,
+		.default_range = 4,
+		.drv = &mock_sensor_driver,
+		.online_calib_data[0] = {
+			.type_specific_data = &gyro_cal_data,
+		},
+	},
+};
+
+const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+static void spoof_sensor_data(struct motion_sensor_t *s, int x, int y, int z)
+{
+	struct ec_response_motion_sensor_data data;
+	uint32_t timestamp = 0;
+
+	/* Set the data and flags. */
+	data.data[X] = x;
+	data.data[Y] = y;
+	data.data[Z] = z;
+	s->flags |= MOTIONSENSE_FLAG_IN_SPOOF_MODE;
+
+	/* Pass the data to online_calibdation. */
+	online_calibration_process_data(&data, s, timestamp);
+}
+
+/*
+ * Begin testing.
+ */
+
+static int test_accel_calibration_on_spoof(void)
+{
+	struct ec_response_online_calibration_data out;
+
+	/* Send spoof data (1, 2, 3). */
+	spoof_sensor_data(&motion_sensors[0], 1, 2, 3);
+
+	/* Check that we have new values. */
+	TEST_ASSERT(online_calibration_has_new_values());
+
+	/* Get the new values for sensor 0. */
+	TEST_ASSERT(online_calibration_read(&motion_sensors[0], &out));
+
+	/* Validate the new values. */
+	TEST_EQ(out.data[X], 1, "%d");
+	TEST_EQ(out.data[Y], 2, "%d");
+	TEST_EQ(out.data[Z], 3, "%d");
+
+	/* Validate that no other sensors have data. */
+	TEST_ASSERT(!online_calibration_has_new_values());
+
+	return EC_SUCCESS;
+}
+
+static int test_mag_calibration_on_spoof(void)
+{
+	struct ec_response_online_calibration_data out;
+
+	/* Send spoof data (4, 5, 6). */
+	spoof_sensor_data(&motion_sensors[1], 4, 5, 6);
+
+	/* Check that we have new values. */
+	TEST_ASSERT(online_calibration_has_new_values());
+
+	/* Get the new values for sensor 0. */
+	TEST_ASSERT(online_calibration_read(&motion_sensors[1], &out));
+
+	/* Validate the new values. */
+	TEST_EQ(out.data[X], 4, "%d");
+	TEST_EQ(out.data[Y], 5, "%d");
+	TEST_EQ(out.data[Z], 6, "%d");
+
+	/* Validate that no other sensors have data. */
+	TEST_ASSERT(!online_calibration_has_new_values());
+
+	return EC_SUCCESS;
+}
+
+static int test_gyro_calibration_on_spoof(void)
+{
+	struct ec_response_online_calibration_data out;
+
+	/* Send spoof data (7, 8, 9). */
+	spoof_sensor_data(&motion_sensors[2], 7, 8, 9);
+
+	/* Check that we have new values. */
+	TEST_ASSERT(online_calibration_has_new_values());
+
+	/* Get the new values for sensor 0. */
+	TEST_ASSERT(online_calibration_read(&motion_sensors[2], &out));
+
+	/* Validate the new values. */
+	TEST_EQ(out.data[X], 7, "%d");
+	TEST_EQ(out.data[Y], 8, "%d");
+	TEST_EQ(out.data[Z], 9, "%d");
+
+	/* Validate that no other sensors have data. */
+	TEST_ASSERT(!online_calibration_has_new_values());
+
+	return EC_SUCCESS;
+}
+
+void before_test(void)
+{
+	online_calibration_init();
+	gyro_cal_initialization_for_test(&gyro_cal_data);
+}
+
+void run_test(int argc, const char **argv)
+{
+	test_reset();
+
+	RUN_TEST(test_accel_calibration_on_spoof);
+	RUN_TEST(test_mag_calibration_on_spoof);
+	RUN_TEST(test_gyro_calibration_on_spoof);
+
+	test_print_result();
+}
diff --git a/test/online_calibration_spoof.tasklist b/test/online_calibration_spoof.tasklist
new file mode 100644
index 0000000000..7209a7441e
--- /dev/null
+++ b/test/online_calibration_spoof.tasklist
@@ -0,0 +1,10 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST \
+	TASK_TEST(MOTIONSENSE, motion_sense_task, NULL, TASK_STACK_SIZE)
diff --git a/test/panic.c b/test/panic.c
new file mode 100644
index 0000000000..a7333eda98
--- /dev/null
+++ b/test/panic.c
@@ -0,0 +1,121 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "assert.h"
+#include "panic.h"
+#include "system.h"
+#include "task.h"
+#include "test_util.h"
+
+#if !(defined(CORE_CORTEX_M) || defined(CORE_CORTEX_M0))
+#error "Architecture not supported"
+#endif
+
+struct reg_vals {
+	int index;
+	uint32_t val;
+};
+
+static const struct reg_vals EXPECTED[] = {
+	{ .index = CORTEX_PANIC_REGISTER_R4, .val = 0xecec0004 },
+	{ .index = CORTEX_PANIC_REGISTER_R5, .val = 0xecec0005 },
+	{ .index = CORTEX_PANIC_REGISTER_R6, .val = 0xecec0006 },
+	{ .index = CORTEX_PANIC_REGISTER_R7, .val = 0xecec0007 },
+	{ .index = CORTEX_PANIC_REGISTER_R8, .val = 0xecec0008 },
+	{ .index = CORTEX_PANIC_REGISTER_R9, .val = 0xecec0009 },
+	{ .index = CORTEX_PANIC_REGISTER_R10, .val = 0xecec000a },
+	{ .index = CORTEX_PANIC_REGISTER_R11, .val = 0xecec000b },
+};
+
+test_static int test_exception_panic_registers(void)
+{
+	if (IS_ENABLED(CORE_CORTEX_M)) {
+		asm volatile("ldr r0, =0xecec0000\n"
+			     "ldr r1, =0xecec0001\n"
+			     "ldr r2, =0xecec0002\n"
+			     "ldr r3, =0xecec0003\n"
+			     "ldr r4, =0xecec0004\n"
+			     "ldr r5, =0xecec0005\n"
+			     "ldr r6, =0xecec0006\n"
+			     "ldr r7, =0xecec0007\n"
+			     "ldr r8, =0xecec0008\n"
+			     "ldr r9, =0xecec0009\n"
+			     "ldr r10, =0xecec000a\n"
+			     "ldr r11, =0xecec000b\n"
+			     "ldr r14, =0xecec000e\n"
+			     /* Undefined instruction. */
+			     "udf #0\n");
+	} else if (IS_ENABLED(CORE_CORTEX_M0)) {
+		asm volatile("ldr r1, =0xecec0001\n"
+			     "ldr r2, =0xecec0002\n"
+			     "ldr r3, =0xecec0003\n"
+			     "ldr r4, =0xecec0004\n"
+			     "ldr r5, =0xecec0005\n"
+			     "ldr r6, =0xecec0006\n"
+			     "ldr r7, =0xecec0007\n"
+			     "ldr r0, =0xecec0008\n"
+			     "mov r8, r0\n"
+			     "ldr r0, =0xecec0009\n"
+			     "mov r9, r0\n"
+			     "ldr r0, =0xecec000a\n"
+			     "mov r10, r0\n"
+			     "ldr r0, =0xecec000b\n"
+			     "mov r11, r0\n"
+			     "ldr r0, =0xecec000e\n"
+			     "mov r14, r0\n"
+			     /* Undefined instruction. */
+			     "udf #0\n");
+	}
+	__builtin_unreachable();
+}
+
+test_static void run_test_step1(void)
+{
+	ccprintf("Step 1: Panic\n");
+	system_set_scratchpad(TEST_STATE_MASK(TEST_STATE_STEP_2));
+	RUN_TEST(test_exception_panic_registers);
+}
+
+test_static int run_test_step2(void)
+{
+	struct panic_data *data;
+	int i;
+
+	ccprintf("Step 2: Read panic data\n");
+	data = panic_get_data();
+	for (i = 0; i < ARRAY_SIZE(EXPECTED); i++) {
+		TEST_EQ(EXPECTED[i].val, data->cm.regs[EXPECTED[i].index],
+			"%04x");
+		cflush();
+	}
+	return EC_SUCCESS;
+}
+
+void test_run_step(uint32_t state)
+{
+	int ret;
+
+	if (state & TEST_STATE_MASK(TEST_STATE_STEP_1))
+		run_test_step1();
+	else if (state & TEST_STATE_MASK(TEST_STATE_STEP_2)) {
+		ret = run_test_step2();
+		if (ret == EC_SUCCESS)
+			test_reboot_to_next_step(TEST_STATE_PASSED);
+		else
+			test_reboot_to_next_step(TEST_STATE_FAILED);
+	}
+}
+
+int task_test(void *unused)
+{
+	test_run_multistep();
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
+{
+	msleep(30); /* Wait for TASK_ID_TEST to initialize */
+	task_wake(TASK_ID_TEST);
+}
diff --git a/test/panic.tasklist b/test/panic.tasklist
new file mode 100644
index 0000000000..35a6edd545
--- /dev/null
+++ b/test/panic.tasklist
@@ -0,0 +1,9 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST TASK_TEST(TEST, task_test, NULL, TASK_STACK_SIZE)
diff --git a/test/panic_data.c b/test/panic_data.c
new file mode 100644
index 0000000000..8892c17ece
--- /dev/null
+++ b/test/panic_data.c
@@ -0,0 +1,139 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "builtin/assert.h"
+#include "panic.h"
+#include "system.h"
+#include "task.h"
+#include "test_util.h"
+
+static int get_assert_line(void)
+{
+	/* Returned number should point to ASSERT(0) line below */
+	return __LINE__ + 5;
+}
+
+static void crash_system(void)
+{
+	ASSERT(0);
+}
+
+test_static int test_panic_data(void)
+{
+	struct panic_data *pdata = panic_get_data();
+
+	/* Check panic reason. */
+	TEST_EQ(pdata->cm.regs[CORTEX_PANIC_REGISTER_R4], PANIC_SW_ASSERT,
+		"%08x");
+
+	/* Check panic info. */
+	TEST_EQ(pdata->cm.regs[CORTEX_PANIC_REGISTER_R5], get_assert_line(),
+		"%d");
+
+	/*
+	 * Check panic exception - it should be always 0 because panic didn't
+	 * happen during interrupt processing.
+	 */
+	TEST_EQ(pdata->cm.regs[CORTEX_PANIC_REGISTER_IPSR], 0, "%d");
+
+	/* Check panic flags. */
+	TEST_EQ(pdata->flags,
+		PANIC_DATA_FLAG_FRAME_VALID | PANIC_DATA_FLAG_OLD_HOSTEVENT,
+		"%02x");
+
+	return EC_SUCCESS;
+}
+
+/*
+ * After hard reboot we expect to have panic flags, panic exception and lower
+ * 16 bits of panic reason and info (upper 16 bits should be zero). This
+ * information is saved in backup RAM because hard reboot clears memory. The
+ * backup RAM only has 16 bits available for this information. Check if lower
+ * 16 bits of reason and info are present and upper 16 bits are zero.
+ */
+test_static int test_panic_data_half(void)
+{
+	struct panic_data *pdata = panic_get_data();
+
+	/* Check panic reason. */
+	TEST_EQ(pdata->cm.regs[CORTEX_PANIC_REGISTER_R4],
+		(PANIC_SW_ASSERT & 0xffff), "%08x");
+
+	/* Check panic info. */
+	TEST_EQ(pdata->cm.regs[CORTEX_PANIC_REGISTER_R5],
+		(get_assert_line() & 0xffff), "%d");
+
+	/*
+	 * Check panic exception - it should be always 0 because panic didn't
+	 * happen during interrupt processing.
+	 */
+	TEST_EQ(pdata->cm.regs[CORTEX_PANIC_REGISTER_IPSR], 0, "%d");
+
+	/* Check panic flags. */
+	TEST_EQ(pdata->flags,
+		PANIC_DATA_FLAG_FRAME_VALID | PANIC_DATA_FLAG_OLD_HOSTEVENT,
+		"%02x");
+
+	return EC_SUCCESS;
+}
+
+void test_run_step(uint32_t state)
+{
+	/* Step 1: Crash system to get panic data. */
+	if (state & TEST_STATE_MASK(TEST_STATE_STEP_1)) {
+		test_set_next_step(TEST_STATE_STEP_2);
+		/* Crash the system */
+		ccprintf("Crash the system!\n");
+		cflush();
+		crash_system();
+	}
+	/* Step 2: Check panic data after crash and do soft reboot. */
+	else if (state & TEST_STATE_MASK(TEST_STATE_STEP_2)) {
+		RUN_TEST(test_panic_data);
+		if (!test_get_error_count()) {
+			test_set_next_step(TEST_STATE_STEP_3);
+			/* Do a soft system reset */
+			ccprintf("Perform soft reboot\n");
+			cflush();
+			system_reset(0);
+		} else
+			test_reboot_to_next_step(TEST_STATE_FAILED);
+	}
+	/* Step 3: Check panic data after soft reboot and do hard reboot. */
+	else if (state & TEST_STATE_MASK(TEST_STATE_STEP_3)) {
+		RUN_TEST(test_panic_data);
+		if (!test_get_error_count()) {
+			test_set_next_step(TEST_STATE_STEP_4);
+			/* Do a hard system reset */
+			ccprintf("Perform hard reboot\n");
+			cflush();
+			system_reset(SYSTEM_RESET_HARD);
+		} else
+			test_reboot_to_next_step(TEST_STATE_FAILED);
+	}
+	/* Step 4: Check panic data after hard reboot */
+	else if (state & TEST_STATE_MASK(TEST_STATE_STEP_4)) {
+		RUN_TEST(test_panic_data_half);
+		if (!test_get_error_count())
+			test_reboot_to_next_step(TEST_STATE_PASSED);
+		else
+			test_reboot_to_next_step(TEST_STATE_FAILED);
+	}
+}
+
+int task_test(void *unused)
+{
+	if (IS_ENABLED(SECTION_IS_RW))
+		test_run_multistep();
+
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
+{
+	test_reset();
+	msleep(30); /* Wait for TASK_ID_TEST to initialize */
+	task_wake(TASK_ID_TEST);
+}
diff --git a/test/panic_data.tasklist b/test/panic_data.tasklist
new file mode 100644
index 0000000000..273a9664c0
--- /dev/null
+++ b/test/panic_data.tasklist
@@ -0,0 +1,10 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST \
+  TASK_TEST(TEST, task_test, NULL, TASK_STACK_SIZE)
diff --git a/test/pingpong.c b/test/pingpong.c
index f3ff89341f..cb8c5af8c9 100644
--- a/test/pingpong.c
+++ b/test/pingpong.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -38,7 +38,8 @@ int task_abc(void *data)
 			wake_count[0] = wake_count[1] = wake_count[2] = 0;
 			task_wait_event(-1);
 		} else {
-			task_set_event(next, TASK_EVENT_WAKE, 1);
+			task_set_event(next, TASK_EVENT_WAKE);
+			task_wait_event(-1);
 		}
 	}
 
@@ -59,7 +60,7 @@ int task_tick(void *data)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	wait_for_task_started();
 	task_wake(TASK_ID_TICK);
diff --git a/test/pingpong.tasklist b/test/pingpong.tasklist
index 760d204b67..7db2ce33a6 100644
--- a/test/pingpong.tasklist
+++ b/test/pingpong.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/power_button.c b/test/power_button.c
index 5fe9136105..dc64e607fa 100644
--- a/test/power_button.c
+++ b/test/power_button.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -89,7 +89,7 @@ static int test_debounce(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/power_button.tasklist b/test/power_button.tasklist
index da0ab6211a..100cb6b5bd 100644
--- a/test/power_button.tasklist
+++ b/test/power_button.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/powerdemo.c b/test/powerdemo.c
index e695bb8e5e..2900401370 100644
--- a/test/powerdemo.c
+++ b/test/powerdemo.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,22 +8,21 @@
 #include "clock.h"
 #include "common.h"
 #include "powerdemo.h"
+#include "registers.h"
 #include "task.h"
 #include "timer.h"
-#include "registers.h"
 
 static volatile enum {
-	POWER_STATE_IDLE = 0,    /* Idle */
-	POWER_STATE_DOWN1,       /* Assert output for 1ms */
-	POWER_STATE_UP1,         /* Deassert output for 1ms */
-	POWER_STATE_DOWN10,      /* Assert output for 10ms */
-	POWER_STATE_UP5,         /* Deassert output for 5ms */
-	POWER_STATE_DOWN15,      /* Assert output for 15ms */
-	POWER_STATE_WAIT,        /* Wait for button to be released */
-	POWER_STATE_DOWN2        /* Assert output for 2ms */
+	POWER_STATE_IDLE = 0, /* Idle */
+	POWER_STATE_DOWN1, /* Assert output for 1ms */
+	POWER_STATE_UP1, /* Deassert output for 1ms */
+	POWER_STATE_DOWN10, /* Assert output for 10ms */
+	POWER_STATE_UP5, /* Deassert output for 5ms */
+	POWER_STATE_DOWN15, /* Assert output for 15ms */
+	POWER_STATE_WAIT, /* Wait for button to be released */
+	POWER_STATE_DOWN2 /* Assert output for 2ms */
 } state = POWER_STATE_IDLE;
 
-
 /* Stops the timer. */
 static void __stop_timer(void)
 {
@@ -33,7 +32,6 @@ static void __stop_timer(void)
 	LM4_TIMER_ICR(7) = LM4_TIMER_RIS(7);
 }
 
-
 /* Starts the timer with the specified delay.  If the timer is already
  * started, resets it. */
 static void __start_timer(int usec)
@@ -46,7 +44,6 @@ static void __start_timer(int usec)
 	LM4_TIMER_CTL(7) |= 0x01;
 }
 
-
 static void __set_state(int new_state, int pin_value, int timeout)
 {
 	LM4_GPIO_DATA(LM4_GPIO_D, 0x08) = (pin_value ? 0x08 : 0);
@@ -57,7 +54,6 @@ static void __set_state(int new_state, int pin_value, int timeout)
 	state = new_state;
 }
 
-
 int power_demo_init(void)
 {
 	volatile uint32_t scratch __attribute__((unused));
@@ -102,7 +98,6 @@ int power_demo_init(void)
 	return EC_SUCCESS;
 }
 
-
 /* GPIO interrupt handler */
 static void __gpio_d_interrupt(void)
 {
@@ -125,7 +120,6 @@ static void __gpio_d_interrupt(void)
 
 DECLARE_IRQ(LM4_IRQ_GPIOD, __gpio_d_interrupt, 1);
 
-
 /* Timer interrupt handler */
 static void __timer_w1_interrupt(void)
 {
diff --git a/test/powerdemo.h b/test/powerdemo.h
index 17ed482042..a8ee854acb 100644
--- a/test/powerdemo.h
+++ b/test/powerdemo.h
@@ -1,4 +1,4 @@
-/* Copyright 2011 The Chromium OS Authors. All rights reserved.
+/* Copyright 2011 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,4 +13,4 @@
 /* Initializes the module. */
 int power_demo_init(void);
 
-#endif  /* __TEST_POWERDEMO_H */
+#endif /* __TEST_POWERDEMO_H */
diff --git a/test/powerdemo.tasklist b/test/powerdemo.tasklist
index a4fff562e3..3824306072 100644
--- a/test/powerdemo.tasklist
+++ b/test/powerdemo.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/printf.c b/test/printf.c
index ae85837cd5..4906e25404 100644
--- a/test/printf.c
+++ b/test/printf.c
@@ -1,25 +1,43 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <stdarg.h>
-#include <stdbool.h>
-#include <stddef.h>
-
 #include "common.h"
+#include "compiler.h"
 #include "printf.h"
 #include "test_util.h"
 #include "util.h"
 
+#include <stdarg.h>
+#include <stdbool.h>
+#include <stddef.h>
+
+#ifdef USE_BUILTIN_STDLIB
+/*
+ * When USE_BUILTIN_STDLIB is defined, we want to test the EC printf
+ * implementation. We need to include the builtin header file directly so
+ * that we can call the EC version (crec_vsnprintf) when linking with the
+ * standard library on the host.
+ */
+#include "builtin/stdio.h"
+#define VSNPRINTF crec_vsnprintf
+#define SNPRINTF crec_snprintf
+static const bool use_builtin_stdlib = true;
+#else
+#include <stdio.h>
+#define VSNPRINTF vsnprintf
+#define SNPRINTF snprintf
+static const bool use_builtin_stdlib = false;
+#endif
+
 #define INIT_VALUE 0x5E
 #define NO_BYTES_TOUCHED NULL
 
 static const char err_str[] = "ERROR";
 static char output[1024];
 
-int run(int expect_ret, const char *expect,
-	bool output_null, size_t size_limit,
+int run(int expect_ret, const char *expect, bool output_null, size_t size_limit,
 	const char *format, va_list args)
 {
 	size_t expect_size = expect ? strlen(expect) + 1 : 0;
@@ -34,10 +52,8 @@ int run(int expect_ret, const char *expect,
 	TEST_ASSERT(expect_size <= size_limit);
 	memset(output, INIT_VALUE, sizeof(output));
 
-	rv = vsnprintf(output_null ? NULL : output, size_limit,
-		       format, args);
-	ccprintf("received='%.*s'   | ret          =%d\n",
-		 30, output, rv);
+	rv = VSNPRINTF(output_null ? NULL : output, size_limit, format, args);
+	ccprintf("received='%.*s'   | ret          =%d\n", 30, output, rv);
 
 	TEST_ASSERT_ARRAY_EQ(output, expect, expect_size);
 	TEST_ASSERT_MEMSET(&output[expect_size], INIT_VALUE,
@@ -59,256 +75,623 @@ int expect_success(const char *expect, const char *format, ...)
 	int rv;
 
 	va_start(args, format);
-	rv = run(EC_SUCCESS, expect,
-		 false, sizeof(output),
-		 format, args);
+	rv = run(EC_SUCCESS, expect, false, sizeof(output), format, args);
 	va_end(args);
 
 	return rv;
 }
 
-int expect(int expect_ret, const char *expect,
-	   bool output_null, size_t size_limit,
-	   const char *format, ...)
+int expect(int expect_ret, const char *expect, bool output_null,
+	   size_t size_limit, const char *format, ...)
 {
 	va_list args;
 	int rv;
 
 	va_start(args, format);
-	rv = run(expect_ret, expect,
-		 output_null, size_limit,
-		 format, args);
+	rv = run(expect_ret, expect, output_null, size_limit, format, args);
 	va_end(args);
 
 	return rv;
 }
 
-#define T(n)                                                                  \
-	do {                                                                  \
-		int rv = (n);                                                 \
-		if (rv != EC_SUCCESS)                                         \
-			return rv;                                            \
+#define T(n)                          \
+	do {                          \
+		int rv = (n);         \
+		if (rv != EC_SUCCESS) \
+			return rv;    \
 	} while (0)
 
 test_static int test_vsnprintf_args(void)
 {
-	T(expect_success("",          ""));
-	T(expect_success("a",         "a"));
-
-	T(expect(/* expect an invalid args error */
-		 EC_ERROR_INVAL, NO_BYTES_TOUCHED,
-		 /* given -1 as output size limit */
-		 false, -1, ""));
-	T(expect(/* expect an invalid args error */
-		 EC_ERROR_INVAL, NO_BYTES_TOUCHED,
-		 /* given 0 as output size limit */
-		 false, 0, ""));
+	T(expect_success("", ""));
+	T(expect_success("a", "a"));
+
+	if (use_builtin_stdlib) {
+		/*
+		 * TODO(b/239233116): This differs from the C standard library
+		 * behavior and should probably be changed.
+		 */
+		T(expect(/* expect an invalid args error */
+			 EC_ERROR_INVAL, NO_BYTES_TOUCHED,
+			 /* given 0 as output size limit */
+			 false, 0, ""));
+		T(expect(/* expect an overflow error */
+			 EC_ERROR_OVERFLOW, "",
+			 /* given 1 as output size limit with a non-blank format
+			  */
+			 false, 1, "a"));
+		T(expect(/* expect an invalid args error */
+			 EC_ERROR_INVAL, NO_BYTES_TOUCHED,
+			 /* given NULL as the output buffer */
+			 true, sizeof(output), ""));
+		T(expect(/* expect an invalid args error */
+			 EC_ERROR_INVAL, NO_BYTES_TOUCHED,
+			 /* given a NULL format string */
+			 false, sizeof(output), NULL));
+	}
 	T(expect(/* expect SUCCESS */
 		 EC_SUCCESS, "",
 		 /* given 1 as output size limit and a blank format */
 		 false, 1, ""));
-	T(expect(/* expect an overflow error */
-		 EC_ERROR_OVERFLOW, "",
-		 /* given 1 as output size limit with a non-blank format */
-		 false, 1, "a"));
-
-	T(expect(/* expect an invalid args error */
-		 EC_ERROR_INVAL, NO_BYTES_TOUCHED,
-		 /* given NULL as the output buffer */
-		 true, sizeof(output), ""));
-	T(expect(/* expect an invalid args error */
-		 EC_ERROR_INVAL, NO_BYTES_TOUCHED,
-		 /* given a NULL format string */
-		 false, sizeof(output), NULL));
 
 	return EC_SUCCESS;
 }
 
 test_static int test_vsnprintf_int(void)
 {
-	T(expect_success("123",       "%d",      123));
-	T(expect_success("-123",      "%d",     -123));
-	T(expect_success("+123",      "%+d",     123));
-	T(expect_success("-123",      "%+d",    -123));
-	T(expect_success("123",       "%-d",     123));
-	T(expect_success("-123",      "%-d",    -123));
-
-	T(expect_success("  123",     "%5d",     123));
-	T(expect_success(" +123",     "%+5d",    123));
-	T(expect_success("00123",     "%05d",    123));
-	T(expect_success("00123",     "%005d",   123));
-	/*
-	 * TODO(crbug.com/974084): This odd behavior should be fixed.
-	 * T(expect_success("+0123",     "%+05d",   123));
-	 * Actual: "0+123"
-	 * T(expect_success("+0123",     "%+005d",  123));
-	 * Actual: "0+123"
-	 */
+	T(expect_success("123", "%d", 123));
+	T(expect_success("-123", "%d", -123));
+	T(expect_success("+123", "%+d", 123));
+	T(expect_success("-123", "%+d", -123));
+	T(expect_success("123", "%-d", 123));
+	T(expect_success("-123", "%-d", -123));
+
+	T(expect_success("  123", "%5d", 123));
+	T(expect_success(" +123", "%+5d", 123));
+	T(expect_success("00123", "%05d", 123));
+	T(expect_success("00123", "%005d", 123));
+
+	if (use_builtin_stdlib) {
+		/*
+		 * TODO(b/239233116): These are incorrect and should be fixed.
+		 */
+		/* Fixed point. */
+		T(expect_success("0.00123", "%.5d", 123));
+		T(expect_success("12.3", "%2.1d", 123));
+		/* Precision or width larger than buffer should fail. */
+		T(expect(EC_ERROR_OVERFLOW, "  1", false, 4, "%5d", 123));
+		T(expect(EC_ERROR_OVERFLOW, "   ", false, 4, "%10d", 123));
+		T(expect(EC_ERROR_OVERFLOW, "123", false, 4, "%-10d", 123));
+		T(expect(EC_ERROR_OVERFLOW, "0.0", false, 4, "%.10d", 123));
+	} else {
+		int ret;
+
+		T(expect_success("00123", "%.5d", 123));
+		T(expect_success("123", "%2.1d", 123));
+
+		/*
+		 * From the man page: The functions  snprintf() and vsnprintf()
+		 * do not write more than size bytes (including the
+		 * terminating null byte ('\0')). If the output was truncated
+		 * due to this limit, then the return value is the number of
+		 * characters (excluding the terminating null byte) which
+		 * would have been written to the final string if enough
+		 * space had been available. Thus, a return value of size or
+		 * more means that the output was truncated.
+		 */
+		DISABLE_COMPILER_WARNING("-Wformat-truncation");
+
+		ret = SNPRINTF(output, 4, "%5d", 123);
+		TEST_ASSERT_ARRAY_EQ(output, "  1", 4);
+		TEST_EQ(ret, 5, "%d");
+
+		ret = SNPRINTF(output, 4, "%10d", 123);
+		TEST_ASSERT_ARRAY_EQ(output, "   ", 4);
+		TEST_EQ(ret, 10, "%d");
+
+		ret = SNPRINTF(output, 4, "%-10d", 123);
+		TEST_ASSERT_ARRAY_EQ(output, "123", 4);
+		TEST_EQ(ret, 10, "%d");
+
+		ret = SNPRINTF(output, 4, "%.10d", 123);
+		TEST_ASSERT_ARRAY_EQ(output, "000", 4);
+		TEST_EQ(ret, 10, "%d");
+
+		ENABLE_COMPILER_WARNING("-Wformat-truncation");
+	}
 
-	T(expect_success("  123",     "%*d",     5, 123));
-	T(expect_success(" +123",     "%+*d",    5, 123));
-	T(expect_success("00123",     "%0*d",    5, 123));
-	/*
-	 * TODO(crbug.com/974084): This odd behavior should be fixed.
-	 * T(expect_success("00123",     "%00*d",   5, 123));
-	 * Actual: "ERROR"
-	 */
-	T(expect_success("0+123",     "%+0*d",   5, 123));
-	/*
-	 * TODO(crbug.com/974084): This odd behavior should be fixed.
-	 * T(expect_success("0+123",     "%+00*d",  5, 123));
-	 * Actual: "ERROR"
-	 */
+	if (use_builtin_stdlib) {
+		/*
+		 * TODO(b/239233116): These are incorrect and should be fixed.
+		 */
+		T(expect_success("0+123", "%+05d", 123));
+		T(expect_success("0+123", "%+005d", 123));
+	} else {
+		T(expect_success("+0123", "%+05d", 123));
+		T(expect_success("+0123", "%+005d", 123));
+	}
+
+	T(expect_success("  123", "%*d", 5, 123));
+	T(expect_success(" +123", "%+*d", 5, 123));
+	T(expect_success("00123", "%0*d", 5, 123));
 
-	T(expect_success("123  ",     "%-5d",    123));
-	T(expect_success("+123 ",     "%-+5d",   123));
-	T(expect_success(err_str,     "%+-5d",   123));
-	T(expect_success("123  ",     "%-05d",   123));
-	T(expect_success("123  ",     "%-005d",  123));
-	T(expect_success("+123 ",     "%-+05d",  123));
-	T(expect_success("+123 ",     "%-+005d", 123));
-
-	T(expect_success("0.00123",   "%.5d",    123));
-	T(expect_success("+0.00123",  "%+.5d",   123));
-	T(expect_success("0.00123",   "%7.5d",   123));
-	T(expect_success("  0.00123", "%9.5d",   123));
-	T(expect_success(" +0.00123", "%+9.5d",  123));
-
-	T(expect_success("123",        "%u",    123));
-	T(expect_success("4294967295", "%u",   -1));
+	if (use_builtin_stdlib) {
+		/*
+		 * TODO(b/239233116): This incorrect and should be fixed.
+		 */
+		T(expect_success(err_str, "%00*d", 5, 123));
+	} else {
+		T(expect_success("00123", "%00*d", 5, 123));
+	}
+
+	if (use_builtin_stdlib) {
+		/*
+		 * TODO(b/239233116): This is incorrect and should be fixed.
+		 */
+		T(expect_success("0+123", "%+0*d", 5, 123));
+	} else {
+		T(expect_success("+0123", "%+0*d", 5, 123));
+	}
+
+	if (use_builtin_stdlib) {
+		/*
+		 * TODO(b/239233116): This is incorrect and should be fixed.
+		 */
+		T(expect_success(err_str, "%+00*d", 5, 123));
+	} else {
+		T(expect_success("+0123", "%+00*d", 5, 123));
+	}
+
+	T(expect_success("123  ", "%-5d", 123));
+	T(expect_success("+123 ", "%-+5d", 123));
+	if (use_builtin_stdlib) {
+		/*
+		 * TODO(b/239233116): This incorrect and should be fixed.
+		 */
+		T(expect_success(err_str, "%+-5d", 123));
+	} else {
+		T(expect_success("+123 ", "%+-5d", 123));
+	}
+	T(expect_success("123  ", "%-05d", 123));
+	T(expect_success("123  ", "%-005d", 123));
+	T(expect_success("+123 ", "%-+05d", 123));
+	T(expect_success("+123 ", "%-+005d", 123));
+
+	if (use_builtin_stdlib) {
+		/*
+		 * TODO(b/239233116): These are incorrect and should be fixed.
+		 */
+		T(expect_success("0.00123", "%.5d", 123));
+		T(expect_success("+0.00123", "%+.5d", 123));
+		T(expect_success("0.00123", "%7.5d", 123));
+		T(expect_success("  0.00123", "%9.5d", 123));
+		T(expect_success(" +0.00123", "%+9.5d", 123));
+	} else {
+		T(expect_success("00123", "%.5d", 123));
+		T(expect_success("+00123", "%+.5d", 123));
+		T(expect_success("  00123", "%7.5d", 123));
+		T(expect_success("    00123", "%9.5d", 123));
+		T(expect_success("   +00123", "%+9.5d", 123));
+	}
+
+	T(expect_success("123", "%u", 123));
+	T(expect_success("4294967295", "%u", -1));
 	T(expect_success("18446744073709551615", "%llu", (uint64_t)-1));
 
-	T(expect_success("0",         "%x",     0));
-	T(expect_success("0",         "%X",     0));
-	T(expect_success("5e",        "%x",     0X5E));
-	T(expect_success("5E",        "%X",     0X5E));
+	T(expect_success("0", "%x", 0));
+	T(expect_success("0", "%X", 0));
+	T(expect_success("5e", "%x", 0X5E));
+	T(expect_success("5E", "%X", 0X5E));
+
+	return EC_SUCCESS;
+}
+
+test_static int test_printf_long32_enabled(void)
+{
+	bool use_l32 = IS_ENABLED(CONFIG_PRINTF_LONG_IS_32BITS);
+
+	if (IS_ENABLED(BOARD_BLOONCHIPPER) || IS_ENABLED(BOARD_DARTMONKEY) ||
+	    IS_ENABLED(BOARD_HELIPILOT))
+		TEST_ASSERT(use_l32);
+	else
+		TEST_ASSERT(!use_l32);
+	return EC_SUCCESS;
+}
+
+test_static int test_vsnprintf_32bit_long_supported(void)
+{
+	long long_min = INT32_MIN;
+	long long_max = INT32_MAX;
+	unsigned long ulong_max = UINT32_MAX;
+	char const *long_min_str = "-2147483648";
+	char const *long_max_str = "2147483647";
+	char const *ulong_max_str = "4294967295";
+	char const *long_min_hexstr = "80000000";
+	char const *long_max_hexstr = "7fffffff";
+	char const *ulong_max_hexstr = "ffffffff";
+
+	T(expect_success(long_min_str, "%ld", long_min));
+	T(expect_success(long_min_hexstr, "%lx", long_min));
+	T(expect_success(long_max_str, "%ld", long_max));
+	T(expect_success(long_max_hexstr, "%lx", long_max));
+	T(expect_success(ulong_max_str, "%lu", ulong_max));
+	T(expect_success(ulong_max_hexstr, "%lx", ulong_max));
+	T(expect_success(long_max_str, "%ld", long_max));
+
+	T(expect_success(" +123", "%+*ld", 5, 123));
+	T(expect_success("00000123", "%08lu", 123));
+	T(expect_success("131415", "%d%lu%d", 13, 14L, 15));
 
 	/*
-	 * %l is deprecated on 32-bit systems (see crbug.com/984041), but is
-	 * is still functional on 64-bit systems.
+	 * %i and %li are only supported via the CONFIG_PRINTF_LONG_IS_32BITS
+	 * configuration (see https://issuetracker.google.com/issues/172210614).
 	 */
-	if (sizeof(long) == sizeof(uint32_t)) {
-		T(expect_success(err_str,     "%lx",    0x7b));
-		T(expect_success(err_str,     "%08lu",  0x7b));
-		T(expect_success("13ERROR",   "%d%lu", 13, 14));
+	T(expect_success("123", "%i", 123));
+	T(expect_success("123", "%li", 123));
+
+	return EC_SUCCESS;
+}
+
+test_static int test_vsnprintf_64bit_long_supported(void)
+{
+	/* These lines are only executed when sizeof(long) is 64-bits but are
+	 * still compiled by systems with 32-bit longs, so the casts are needed
+	 * to avoid compilation errors.
+	 */
+	long long_min = (long)INT64_MIN;
+	long long_max = (long)INT64_MAX;
+	unsigned long ulong_max = (unsigned long)UINT64_MAX;
+	char const *long_min_str = "-9223372036854775808";
+	char const *long_max_str = "9223372036854775807";
+	char const *ulong_max_str = "18446744073709551615";
+	char const *long_min_hexstr = "8000000000000000";
+	char const *long_max_hexstr = "7fffffffffffffff";
+	char const *ulong_max_hexstr = "ffffffffffffffff";
+
+	T(expect_success(long_min_str, "%ld", long_min));
+	T(expect_success(long_min_hexstr, "%lx", long_min));
+	T(expect_success(long_max_str, "%ld", long_max));
+	T(expect_success(long_max_hexstr, "%lx", long_max));
+	T(expect_success(ulong_max_str, "%lu", ulong_max));
+	T(expect_success(ulong_max_hexstr, "%lx", ulong_max));
+	T(expect_success(long_max_str, "%ld", long_max));
+
+	T(expect_success(" +123", "%+*ld", 5, 123));
+	T(expect_success("00000123", "%08lu", 123));
+	T(expect_success("131415", "%d%lu%d", 13, 14L, 15));
+
+	if (use_builtin_stdlib) {
+		/*
+		 * TODO(b/239233116): These are incorrect and should be fixed.
+		 */
+		T(expect_success(err_str, "%i", 123));
+		T(expect_success(err_str, "%li", 123));
 	} else {
-		T(expect_success("7b",        "%lx",    0x7b));
-		T(expect_success("00000123",  "%08lu",  123));
-		T(expect_success("131415",    "%d%lu%d", 13, 14L, 15));
+		T(expect_success("123", "%i", 123));
+		T(expect_success("123", "%li", 123));
 	}
 
 	return EC_SUCCESS;
 }
 
+test_static int test_vsnprintf_long_not_supported(void)
+{
+	T(expect_success(err_str, "%ld", 0x7b));
+	T(expect_success(err_str, "%li", 0x7b));
+	T(expect_success(err_str, "%lu", 0x7b));
+	T(expect_success(err_str, "%lx", 0x7b));
+	T(expect_success(err_str, "%08lu", 123));
+	T(expect_success("13ERROR", "%d%lu%d", 13, 14L, 15));
+
+	T(expect_success(err_str, "%i", 123));
+	T(expect_success(err_str, "%li", 123));
+
+	return EC_SUCCESS;
+}
+
+test_static int test_vsnprintf_long(void)
+{
+	/*
+	 * %l is functional on 64-bit systems but is not supported on 32-bit
+	 * systems (see https://issuetracker.google.com/issues/172210614) unless
+	 * explicitly enabled via configuration.
+	 */
+	if (IS_ENABLED(CONFIG_PRINTF_LONG_IS_32BITS))
+		return test_vsnprintf_32bit_long_supported();
+	else if (sizeof(long) == sizeof(uint64_t))
+		return test_vsnprintf_64bit_long_supported();
+	else
+		return test_vsnprintf_long_not_supported();
+}
+
 test_static int test_vsnprintf_pointers(void)
 {
 	void *ptr = (void *)0x55005E00;
-	unsigned int val = 0;
-
-	T(expect_success("55005e00",  "%pP",     ptr));
-	T(expect_success(err_str,     "%P",      ptr));
-	/* %p by itself is invalid */
-	T(expect(EC_ERROR_INVAL, NO_BYTES_TOUCHED,
-		 false, -1, "%p"));
-	/* %p with an unknown suffix is invalid */
-	T(expect(EC_ERROR_INVAL, NO_BYTES_TOUCHED,
-		 false, -1, "%p "));
-	/* %p with an unknown suffix is invalid */
-	T(expect(EC_ERROR_INVAL, NO_BYTES_TOUCHED,
-		 false, -1, "%pQ"));
-
-	/* Test %pb, binary format */
-	T(expect_success("0",         "%pb",     BINARY_VALUE(val, 0)));
-	val = 0x5E;
-	T(expect_success("1011110",   "%pb",     BINARY_VALUE(val, 0)));
-	T(expect_success("0000000001011110", "%pb", BINARY_VALUE(val, 16)));
-	val = 0x12345678;
-	T(expect_success("10010001101000101011001111000", "%pb",
-			 BINARY_VALUE(val, 0)));
-	val = 0xFEDCBA90;
-	/* Test a number that makes the longest string possible */
-	T(expect_success("11111110110111001011101010010000", "%pb",
-			 BINARY_VALUE(val, 0)));
+
+	if (use_builtin_stdlib) {
+		/*
+		 * TODO(b/239233116): This incorrect and should be fixed.
+		 */
+		T(expect_success("55005e00", "%p", ptr));
+	} else {
+		T(expect_success("0x55005e00", "%p", ptr));
+	}
+
 	return EC_SUCCESS;
 }
 
 test_static int test_vsnprintf_chars(void)
 {
-	T(expect_success("a",         "%c",      'a'));
-	T(expect_success("*",         "%c",      '*'));
+	T(expect_success("a", "%c", 'a'));
+	T(expect_success("*", "%c", '*'));
 	return EC_SUCCESS;
 }
 
 test_static int test_vsnprintf_strings(void)
 {
-	T(expect_success("abc",       "%s",      "abc"));
-	T(expect_success("  abc",     "%5s",     "abc"));
-	T(expect_success("abc",       "%0s",     "abc"));
-	T(expect_success("abc  ",     "%-5s",    "abc"));
-	T(expect_success("abc",       "%*s",     0, "abc"));
-	T(expect_success("a",         "%.1s",    "abc"));
-	T(expect_success("a",         "%.*s",    1, "abc"));
-	T(expect_success("",          "%.0s",    "abc"));
-	T(expect_success("",          "%.*s",    0, "abc"));
-	/*
-	 * TODO(crbug.com/974084):
-	 * Ignoring the padding parameter is slightly
-	 * odd behavior and could use a review.
-	 */
-	T(expect_success("ab",        "%5.2s",   "abc"));
-	T(expect_success("abc",        "%.4s",   "abc"));
+	T(expect_success("abc", "%s", "abc"));
+	T(expect_success("  abc", "%5s", "abc"));
+	T(expect_success("abc", "%0s", "abc"));
+	T(expect_success("abc  ", "%-5s", "abc"));
+	T(expect_success("abc", "%*s", 0, "abc"));
+	T(expect_success("a", "%.1s", "abc"));
+	T(expect_success("a", "%.*s", 1, "abc"));
+	T(expect_success("", "%.0s", "abc"));
+	T(expect_success("", "%.*s", 0, "abc"));
+	if (use_builtin_stdlib) {
+		/*
+		 * TODO(b/239233116): This incorrect and should be fixed.
+		 */
+		T(expect_success("ab", "%5.2s", "abc"));
+	} else {
+		T(expect_success("   ab", "%5.2s", "abc"));
+	}
+	T(expect_success("abc", "%.4s", "abc"));
 
 	/*
 	 * Given a malformed string (address 0x1 is a good example),
 	 * if we ask for zero precision, expect no bytes to be read
 	 * from the malformed address and a blank output string.
 	 */
-	T(expect_success("",          "%.0s",    (char *)1));
+	T(expect_success("", "%.0s", (char *)1));
 
 	return EC_SUCCESS;
 }
 
-test_static int test_vsnprintf_timestamps(void)
+test_static int test_snprintf_timestamp(void)
 {
+	char str[PRINTF_TIMESTAMP_BUF_SIZE];
+	int size;
+	int ret;
 	uint64_t ts = 0;
 
-	T(expect_success("0.000000",       "%pT",      &ts));
+	/* Success cases. */
+
+	ret = snprintf_timestamp(str, sizeof(str), ts);
+	TEST_EQ(ret, 8, "%d");
+	TEST_ASSERT_ARRAY_EQ(str, "0.000000", sizeof("0.000000"));
+
 	ts = 123456;
-	T(expect_success("0.123456",       "%pT",      &ts));
+	ret = snprintf_timestamp(str, sizeof(str), ts);
+	TEST_EQ(ret, 8, "%d");
+	TEST_ASSERT_ARRAY_EQ(str, "0.123456", sizeof("0.123456"));
+
 	ts = 9999999000000;
-	T(expect_success("9999999.000000", "%pT",      &ts));
+	ret = snprintf_timestamp(str, sizeof(str), ts);
+	TEST_EQ(ret, 14, "%d");
+	TEST_ASSERT_ARRAY_EQ(str, "9999999.000000", sizeof("9999999.000000"));
+
+	ts = UINT64_MAX;
+	ret = snprintf_timestamp(str, sizeof(str), ts);
+	TEST_EQ(ret, 21, "%d");
+	TEST_ASSERT_ARRAY_EQ(str, "18446744073709.551615",
+			     sizeof("18446744073709.551615"));
+
+	/* Error cases. */
+
+	/* Buffer is too small by one. */
+	size = 21;
+	ts = UINT64_MAX;
+	str[0] = 'f';
+	ret = snprintf_timestamp(str, size, ts);
+	TEST_EQ(ret, -EC_ERROR_OVERFLOW, "%d");
+	TEST_EQ(str[0], '\0', "%d");
+
+	/* Size is zero. */
+	size = 0;
+	ts = UINT64_MAX;
+	str[0] = 'f';
+	ret = snprintf_timestamp(str, size, ts);
+	TEST_EQ(ret, -EC_ERROR_INVAL, "%d");
+	TEST_EQ(str[0], 'f', "%d");
+
+	/* Size is one. */
+	size = 1;
+	ts = UINT64_MAX;
+	str[0] = 'f';
+	ret = snprintf_timestamp(str, size, ts);
+	TEST_EQ(ret, -EC_ERROR_OVERFLOW, "%d");
+	TEST_EQ(str[0], '\0', "%d");
+
 	return EC_SUCCESS;
 }
 
-test_static int test_vsnprintf_hexdump(void)
+test_static int test_snprintf_hex_buffer(void)
 {
-	const char bytes[] = {0x00, 0x5E};
+	const uint8_t bytes[] = { 0xAB, 0x5E };
+	char str_buf[5];
+	int rv;
+
+	/* Success cases. */
+
+	memset(str_buf, 0xff, sizeof(str_buf));
+	rv = snprintf_hex_buffer(str_buf, sizeof(str_buf), HEX_BUF(bytes, 2));
+	TEST_ASSERT_ARRAY_EQ(str_buf, "ab5e", sizeof("ab5e"));
+	TEST_EQ(rv, 4, "%d");
+
+	memset(str_buf, 0xff, sizeof(str_buf));
+	rv = snprintf_hex_buffer(str_buf, sizeof(str_buf), HEX_BUF(bytes, 0));
+	TEST_ASSERT_ARRAY_EQ(str_buf, "", sizeof(""));
+	TEST_EQ(rv, 0, "%d");
+
+	memset(str_buf, 0xff, sizeof(str_buf));
+	rv = snprintf_hex_buffer(str_buf, sizeof(str_buf), HEX_BUF(bytes, 1));
+	TEST_ASSERT_ARRAY_EQ(str_buf, "ab", sizeof("ab"));
+	TEST_EQ(rv, 2, "%d");
+
+	/* Error cases. */
+
+	/* Zero for buffer size argument is an error. */
+	memset(str_buf, 0xff, sizeof(str_buf));
+	TEST_ASSERT_MEMSET(str_buf, (char)0xff, sizeof(str_buf));
+	rv = snprintf_hex_buffer(str_buf, 0, HEX_BUF(bytes, 2));
+	TEST_EQ(rv, -EC_ERROR_INVAL, "%d");
+	TEST_ASSERT_MEMSET(str_buf, (char)0xff, sizeof(str_buf));
+
+	/* Buffer only has space for terminating '\0'. */
+	memset(str_buf, 0xff, sizeof(str_buf));
+	TEST_ASSERT_MEMSET(str_buf, (char)0xff, sizeof(str_buf));
+	rv = snprintf_hex_buffer(str_buf, 1, HEX_BUF(bytes, 1));
+	TEST_ASSERT_ARRAY_EQ(str_buf, "", sizeof(""));
+	TEST_EQ(rv, -EC_ERROR_OVERFLOW, "%d");
+
+	/* Buffer only has space for one character and '\0'. */
+	memset(str_buf, 0xff, sizeof(str_buf));
+	TEST_ASSERT_MEMSET(str_buf, (char)0xff, sizeof(str_buf));
+	rv = snprintf_hex_buffer(str_buf, 2, HEX_BUF(bytes, 1));
+	TEST_ASSERT_ARRAY_EQ(str_buf, "a", sizeof("a"));
+	TEST_EQ(rv, -EC_ERROR_OVERFLOW, "%d");
 
-	T(expect_success("005e",      "%ph",      HEX_BUF(bytes, 2)));
-	T(expect_success("",          "%ph",      HEX_BUF(bytes, 0)));
-	T(expect_success("00",        "%ph",      HEX_BUF(bytes, 1)));
 	return EC_SUCCESS;
 }
 
 test_static int test_vsnprintf_combined(void)
 {
-	T(expect_success("abc",       "%c%s",    'a', "bc"));
-	T(expect_success("12\tbc",    "%d\t%s",  12, "bc"));
+	T(expect_success("abc", "%c%s", 'a', "bc"));
+	T(expect_success("12\tbc", "%d\t%s", 12, "bc"));
+	return EC_SUCCESS;
+}
+
+test_static int test_uint64_to_str(void)
+{
+	/* Longest uin64 in decimal = 20, plus terminating NUL. */
+	char buf[21];
+	char *str;
+
+	str = uint64_to_str(buf, sizeof(buf), /*val=*/0, /*precision=*/-1,
+			    /*base=*/10, /*uppercase=*/false);
+	TEST_ASSERT_ARRAY_EQ(str, "0", sizeof("0"));
+
+	str = uint64_to_str(buf, sizeof(buf), /*val=*/UINT64_MAX,
+			    /*precision=*/-1, /*base=*/10,
+			    /*uppercase=*/false);
+	TEST_ASSERT_ARRAY_EQ(str, "18446744073709551615",
+			     sizeof("18446744073709551615"));
+
+	/* Buffer too small by 1. */
+	str = uint64_to_str(buf, /*buf_len=*/20, /*val=*/UINT64_MAX,
+			    /*precision=*/-1, /*base=*/10, /*uppercase=*/false);
+	TEST_ASSERT(str == NULL);
+
+	/* lower case hex */
+	str = uint64_to_str(buf, sizeof(buf), /*val=*/0, /*precision=*/-1,
+			    /*base=*/16, /*uppercase=*/false);
+	TEST_ASSERT_ARRAY_EQ(str, "0", sizeof("0"));
+
+	/* lower case hex */
+	str = uint64_to_str(buf, sizeof(buf), /*val=*/UINT64_MAX,
+			    /*precision=*/-1, /*base=*/16,
+			    /*uppercase=*/false);
+	TEST_ASSERT_ARRAY_EQ(str, "ffffffffffffffff",
+			     sizeof("fffffffffffffff"));
+
+	/* upper case hex */
+	str = uint64_to_str(buf, sizeof(buf), /*val=*/0, /*precision=*/-1,
+			    /*base=*/16, /*uppercase=*/true);
+	TEST_ASSERT_ARRAY_EQ(str, "0", sizeof("0"));
+
+	str = uint64_to_str(buf, sizeof(buf), /*val=*/UINT64_MAX,
+			    /*precision=*/-1, /*base=*/16,
+			    /*uppercase=*/true);
+	TEST_ASSERT_ARRAY_EQ(str, "FFFFFFFFFFFFFFFF",
+			     sizeof("FFFFFFFFFFFFFFF"));
+
+	/* precision 0 */
+	str = uint64_to_str(buf, sizeof(buf), /*val=*/1, /*precision=*/0,
+			    /*base=*/10, /*uppercase=*/false);
+	TEST_ASSERT_ARRAY_EQ(str, "1.", sizeof("1."));
+
+	/* precision 6 */
+	str = uint64_to_str(buf, sizeof(buf), /*val=*/1, /*precision=*/6,
+			    /*base=*/10, /*uppercase=*/false);
+	TEST_ASSERT_ARRAY_EQ(str, "0.000001", sizeof("0.000001"));
+
+	/* Reduced precision due to buffer that is too small. */
+	str = uint64_to_str(buf, /*buf_len=*/8, /*val=*/1, /*precision=*/6,
+			    /*base=*/10, /*uppercase=*/false);
+	TEST_ASSERT_ARRAY_EQ(str, "0.00001", sizeof("0.00001"));
+
+	/*
+	 * Reduced precision due to buffer that is too small, so precision
+	 * gets changed to 0.
+	 */
+	str = uint64_to_str(buf, /*buf_len=*/3, /*val=*/1, /*precision=*/6,
+			    /*base=*/10, /*uppercase=*/false);
+	TEST_ASSERT_ARRAY_EQ(str, "1.", sizeof("1."));
+
+	/* Precision is unable to fit in provided buffer. */
+	str = uint64_to_str(buf, /*buf_len=*/2, /*val=*/1, /*precision=*/6,
+			    /*base=*/10, /*uppercase=*/false);
+	TEST_ASSERT(str == NULL);
+
+	/* Negative base. */
+	str = uint64_to_str(buf, sizeof(buf), /*val=*/0, /*precision=*/-1,
+			    /*base=*/-1, /*uppercase=*/false);
+	TEST_ASSERT(str == NULL);
+
+	/* Base zero. */
+	str = uint64_to_str(buf, sizeof(buf), /*val=*/1, /*precision=*/-1,
+			    /*base=*/0, /*uppercase=*/false);
+	TEST_ASSERT(str == NULL);
+
+	/* Base one. */
+	str = uint64_to_str(buf, sizeof(buf), /*val=*/1, /*precision=*/-1,
+			    /*base=*/1, /*uppercase=*/false);
+	TEST_ASSERT(str == NULL);
+
+	/* Buffer size 1. */
+	str = uint64_to_str(buf, /*buf_len=*/1, /*val=*/0, /*precision=*/-1,
+			    /*base=*/10, /*uppercase=*/false);
+	TEST_ASSERT(str == NULL);
+
+	/* Buffer size 0. */
+	str = uint64_to_str(buf, /*buf_len=*/0, /*val=*/0, /*precision=*/-1,
+			    /*base=*/10, /*uppercase=*/false);
+	TEST_ASSERT(str == NULL);
+
+	/* Buffer size -1. */
+	str = uint64_to_str(buf, /*buf_len=*/-1, /*val=*/0, /*precision=*/-1,
+			    /*base=*/10, /*uppercase=*/false);
+	TEST_ASSERT(str == NULL);
+
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
 	RUN_TEST(test_vsnprintf_args);
 	RUN_TEST(test_vsnprintf_int);
+	RUN_TEST(test_printf_long32_enabled);
+	RUN_TEST(test_vsnprintf_long);
 	RUN_TEST(test_vsnprintf_pointers);
 	RUN_TEST(test_vsnprintf_chars);
 	RUN_TEST(test_vsnprintf_strings);
-	RUN_TEST(test_vsnprintf_timestamps);
-	RUN_TEST(test_vsnprintf_hexdump);
 	RUN_TEST(test_vsnprintf_combined);
+	RUN_TEST(test_uint64_to_str);
+	RUN_TEST(test_snprintf_timestamp);
+	RUN_TEST(test_snprintf_hex_buffer);
 
 	test_print_result();
 }
diff --git a/test/printf.tasklist b/test/printf.tasklist
index 9fc1a80f4d..844ddb6c10 100644
--- a/test/printf.tasklist
+++ b/test/printf.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/queue.c b/test/queue.c
index 4e12fb147b..24e56230ff 100644
--- a/test/queue.c
+++ b/test/queue.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,7 +11,6 @@
 #include "test_util.h"
 #include "timer.h"
 #include "util.h"
-#include <stdio.h>
 
 static struct queue const test_queue8 = QUEUE_NULL(8, char);
 static struct queue const test_queue2 = QUEUE_NULL(2, int16_t);
@@ -35,13 +34,14 @@ static int test_queue8_init(void)
 	TEST_ASSERT(queue_add_units(&test_queue8, &tmp, 1) == 1);
 	queue_init(&test_queue8);
 	TEST_ASSERT(queue_is_empty(&test_queue8));
+	TEST_ASSERT(queue_remove_unit(&test_queue8, &tmp) == 0);
 
 	return EC_SUCCESS;
 }
 
 static int test_queue8_fifo(void)
 {
-	char buf1[3] = {1, 2, 3};
+	char buf1[3] = { 1, 2, 3 };
 	char buf2[3];
 
 	TEST_ASSERT(queue_add_units(&test_queue8, buf1 + 0, 1) == 1);
@@ -56,7 +56,7 @@ static int test_queue8_fifo(void)
 
 static int test_queue8_multiple_units_add(void)
 {
-	char buf1[5] = {1, 2, 3, 4, 5};
+	char buf1[] = { 1, 2, 3, 4, 5, 6, 7, 8, 9 };
 	char buf2[5];
 
 	TEST_ASSERT(queue_space(&test_queue8) >= 5);
@@ -64,12 +64,15 @@ static int test_queue8_multiple_units_add(void)
 	TEST_ASSERT(queue_remove_units(&test_queue8, buf2, 5) == 5);
 	TEST_ASSERT_ARRAY_EQ(buf1, buf2, 5);
 
+	TEST_ASSERT(queue_add_units(&test_queue8, buf1, 8) == 8);
+	TEST_ASSERT(queue_add_unit(&test_queue8, &buf1[8]) == 0);
+
 	return EC_SUCCESS;
 }
 
 static int test_queue8_removal(void)
 {
-	char buf1[5] = {1, 2, 3, 4, 5};
+	char buf1[5] = { 1, 2, 3, 4, 5 };
 	char buf2[5];
 
 	TEST_ASSERT(queue_add_units(&test_queue8, buf1, 5) == 5);
@@ -106,7 +109,7 @@ static int test_queue8_removal(void)
 
 static int test_queue8_peek(void)
 {
-	char buf1[5] = {1, 2, 3, 4, 5};
+	char buf1[5] = { 1, 2, 3, 4, 5 };
 	char buf2[5];
 
 	TEST_ASSERT(queue_add_units(&test_queue8, buf1, 5) == 5);
@@ -123,7 +126,7 @@ static int test_queue8_peek(void)
 
 static int test_queue2_odd_even(void)
 {
-	uint16_t buf1[3] = {1, 2, 3};
+	uint16_t buf1[3] = { 1, 2, 3 };
 	uint16_t buf2[3];
 
 	TEST_ASSERT(queue_add_units(&test_queue2, buf1, 1) == 1);
@@ -148,7 +151,7 @@ static int test_queue2_odd_even(void)
 
 static int test_queue8_chunks(void)
 {
-	static uint8_t const data[3] = {1, 2, 3};
+	static uint8_t const data[3] = { 1, 2, 3 };
 	struct queue_chunk chunk;
 
 	chunk = queue_get_write_chunk(&test_queue8, 0);
@@ -162,7 +165,7 @@ static int test_queue8_chunks(void)
 	chunk = queue_get_read_chunk(&test_queue8);
 
 	TEST_ASSERT(chunk.count == 3);
-	TEST_ASSERT_ARRAY_EQ((uint8_t *) chunk.buffer, data, 3);
+	TEST_ASSERT_ARRAY_EQ((uint8_t *)chunk.buffer, data, 3);
 
 	TEST_ASSERT(queue_advance_head(&test_queue8, 3) == 3);
 	TEST_ASSERT(queue_is_empty(&test_queue8));
@@ -172,7 +175,7 @@ static int test_queue8_chunks(void)
 
 static int test_queue8_chunks_wrapped(void)
 {
-	static uint8_t const data[3] = {1, 2, 3};
+	static uint8_t const data[3] = { 1, 2, 3 };
 
 	/* Move near the end of the queue */
 	TEST_ASSERT(queue_advance_tail(&test_queue8, 6) == 6);
@@ -214,7 +217,7 @@ static int test_queue8_chunks_wrapped(void)
 
 static int test_queue8_chunks_full(void)
 {
-	static uint8_t const data[8] = {1, 2, 3, 4, 5, 6, 7, 8};
+	static uint8_t const data[8] = { 1, 2, 3, 4, 5, 6, 7, 8 };
 	struct queue_chunk chunk;
 
 	/* Move near the end of the queue */
@@ -231,7 +234,7 @@ static int test_queue8_chunks_full(void)
 	chunk = queue_get_read_chunk(&test_queue8);
 
 	TEST_ASSERT(chunk.count == 2);
-	TEST_ASSERT_ARRAY_EQ((uint8_t *) chunk.buffer, data, 2);
+	TEST_ASSERT_ARRAY_EQ((uint8_t *)chunk.buffer, data, 2);
 
 	/* Signal that we have read both units */
 	TEST_ASSERT(queue_advance_head(&test_queue8, 2) == 2);
@@ -240,8 +243,7 @@ static int test_queue8_chunks_full(void)
 	chunk = queue_get_read_chunk(&test_queue8);
 
 	TEST_ASSERT(chunk.count == 6);
-	TEST_ASSERT_ARRAY_EQ((uint8_t *) chunk.buffer, data + 2, 6);
-
+	TEST_ASSERT_ARRAY_EQ((uint8_t *)chunk.buffer, data + 2, 6);
 
 	return EC_SUCCESS;
 }
@@ -288,12 +290,12 @@ static int test_queue8_chunks_offset(void)
 	/* Check offsetting by 1 */
 	TEST_ASSERT(queue_get_write_chunk(&test_queue8, 1).count == 7);
 	TEST_ASSERT(queue_get_write_chunk(&test_queue8, 1).buffer ==
-			test_queue8.buffer + 1);
+		    test_queue8.buffer + 1);
 
 	/* Check offsetting by 4 */
 	TEST_ASSERT(queue_get_write_chunk(&test_queue8, 4).count == 4);
 	TEST_ASSERT(queue_get_write_chunk(&test_queue8, 4).buffer ==
-			test_queue8.buffer + 4);
+		    test_queue8.buffer + 4);
 
 	/* Check offset wrapping around */
 	TEST_ASSERT(queue_get_write_chunk(&test_queue8, 10).count == 0);
@@ -310,12 +312,12 @@ static int test_queue8_chunks_offset(void)
 	/* Get writable chunk to right of tail. */
 	TEST_ASSERT(queue_get_write_chunk(&test_queue8, 2).count == 2);
 	TEST_ASSERT(queue_get_write_chunk(&test_queue8, 2).buffer ==
-			test_queue8.buffer + 6);
+		    test_queue8.buffer + 6);
 
 	/* Get writable chunk wrapped and before head. */
 	TEST_ASSERT(queue_get_write_chunk(&test_queue8, 4).count == 2);
 	TEST_ASSERT(queue_get_write_chunk(&test_queue8, 4).buffer ==
-			test_queue8.buffer);
+		    test_queue8.buffer);
 
 	/* Check offsetting into non-writable memory. */
 	TEST_ASSERT(queue_get_write_chunk(&test_queue8, 6).count == 0);
@@ -385,6 +387,9 @@ static int test_queue2_iterate_next_full(void)
 	queue_next(q, &it);
 	TEST_EQ(it.ptr, NULL, "%p");
 
+	queue_next(q, &it);
+	TEST_EQ(it.ptr, NULL, "%p");
+
 	return EC_SUCCESS;
 }
 
@@ -416,7 +421,7 @@ void before_test(void)
 	queue_init(&test_queue8);
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/queue.tasklist b/test/queue.tasklist
index da0ab6211a..100cb6b5bd 100644
--- a/test/queue.tasklist
+++ b/test/queue.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/rgb_keyboard.c b/test/rgb_keyboard.c
new file mode 100644
index 0000000000..1b6ea1bf95
--- /dev/null
+++ b/test/rgb_keyboard.c
@@ -0,0 +1,398 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Tests for RGB keyboard.
+ */
+#include "common.h"
+#include "console.h"
+#include "keyboard_backlight.h"
+#include "rgb_keyboard.h"
+#include "task.h"
+#include "test_util.h"
+#include "timer.h"
+#include "util.h"
+
+#include <stdio.h>
+
+#define RGB_GRID0_COL 11
+#define RGB_GRID0_ROW 6
+#define RGB_GRID1_COL 11
+#define RGB_GRID1_ROW 6
+#define SPI_RGB0_DEVICE_ID 0
+#define SPI_RGB1_DEVICE_ID 1
+
+static struct rgb_s grid0[RGB_GRID0_COL * RGB_GRID0_ROW];
+static struct rgb_s grid1[RGB_GRID1_COL * RGB_GRID1_ROW];
+
+const struct rgbkbd_drv test_drv;
+
+struct rgbkbd rgbkbds[] = {
+	[0] = {
+		.cfg = &(const struct rgbkbd_cfg) {
+			.drv = &test_drv,
+			.spi = SPI_RGB0_DEVICE_ID,
+			.col_len = RGB_GRID0_COL,
+			.row_len = RGB_GRID0_ROW,
+		},
+		.buf = grid0,
+	},
+	[1] = {
+		.cfg = &(const struct rgbkbd_cfg) {
+			.drv = &test_drv,
+			.spi = SPI_RGB1_DEVICE_ID,
+			.col_len = RGB_GRID1_COL,
+			.row_len = RGB_GRID1_ROW,
+		},
+		.buf = grid1,
+	},
+};
+const uint8_t rgbkbd_count = ARRAY_SIZE(rgbkbds);
+const uint8_t rgbkbd_hsize = RGB_GRID0_COL + RGB_GRID1_COL;
+const uint8_t rgbkbd_vsize = RGB_GRID0_ROW;
+
+enum ec_rgbkbd_type rgbkbd_type = EC_RGBKBD_TYPE_UNKNOWN;
+
+const uint8_t rgbkbd_map[] = {
+	RGBKBD_DELM,	    RGBKBD_COORD(1, 2), RGBKBD_DELM, RGBKBD_COORD(3, 4),
+	RGBKBD_COORD(5, 6), RGBKBD_DELM,	RGBKBD_DELM, RGBKBD_DELM,
+};
+const size_t rgbkbd_map_size = ARRAY_SIZE(rgbkbd_map);
+
+extern const uint8_t rgbkbd_table[EC_RGBKBD_MAX_KEY_COUNT];
+
+static struct rgbkbd_mock {
+	uint32_t count_drv_reset;
+	uint32_t count_drv_init;
+	uint32_t count_drv_enable;
+	uint32_t count_drv_set_color;
+	uint32_t count_drv_set_scale;
+	uint32_t count_drv_set_gcc;
+	uint32_t gcc_level;
+} mock_state;
+
+__override void board_kblight_init(void)
+{
+}
+
+__override void board_kblight_shutdown(void)
+{
+}
+
+void before_test(void)
+{
+	memset(&mock_state, 0, sizeof(mock_state));
+}
+
+static int test_drv_reset(struct rgbkbd *ctx)
+{
+	mock_state.count_drv_reset++;
+	return EC_SUCCESS;
+}
+
+static int test_drv_init(struct rgbkbd *ctx)
+{
+	mock_state.count_drv_init++;
+	return EC_SUCCESS;
+}
+
+static int test_drv_enable(struct rgbkbd *ctx, bool enable)
+{
+	mock_state.count_drv_enable++;
+	return EC_SUCCESS;
+}
+
+static int test_drv_set_color(struct rgbkbd *ctx, uint8_t offset,
+			      struct rgb_s *color, uint8_t len)
+{
+	mock_state.count_drv_set_color++;
+	return EC_SUCCESS;
+}
+
+static int test_drv_set_scale(struct rgbkbd *ctx, uint8_t offset,
+			      struct rgb_s scale, uint8_t len)
+{
+	mock_state.count_drv_set_scale++;
+	return EC_SUCCESS;
+}
+
+static int test_drv_set_gcc(struct rgbkbd *ctx, uint8_t level)
+{
+	mock_state.count_drv_set_gcc++;
+	mock_state.gcc_level = level;
+	return EC_SUCCESS;
+}
+
+void rgbkbd_init_lookup_table(void);
+
+static int test_rgbkbd_map(void)
+{
+	union rgbkbd_coord_u8 led;
+
+	rgbkbd_init_lookup_table();
+
+	led.u8 = rgbkbd_map[rgbkbd_table[0]];
+	zassert_equal(RGBKBD_COORD(led.coord.x, led.coord.y), RGBKBD_DELM,
+		      "key[0] -> None");
+
+	led.u8 = rgbkbd_map[rgbkbd_table[1]];
+	zassert_equal(RGBKBD_COORD(led.coord.x, led.coord.y),
+		      RGBKBD_COORD(1, 2), "key[1] -> LED(1,2)");
+
+	led.u8 = rgbkbd_map[rgbkbd_table[2]];
+	zassert_equal(RGBKBD_COORD(led.coord.x, led.coord.y),
+		      RGBKBD_COORD(3, 4), "key[2] -> LED(3,4)");
+	led.u8 = rgbkbd_map[rgbkbd_table[2] + 1];
+	zassert_equal(RGBKBD_COORD(led.coord.x, led.coord.y),
+		      RGBKBD_COORD(5, 6), "key[2] -> LED(5,6)");
+
+	led.u8 = rgbkbd_map[rgbkbd_table[3]];
+	zassert_equal(RGBKBD_COORD(led.coord.x, led.coord.y), RGBKBD_DELM,
+		      "key[3] -> None");
+
+	led.u8 = rgbkbd_map[rgbkbd_table[4]];
+	zassert_equal(RGBKBD_COORD(led.coord.x, led.coord.y), RGBKBD_DELM,
+		      "key[4] -> None");
+
+	return EC_SUCCESS;
+}
+
+const struct rgbkbd_drv test_drv = {
+	.reset = test_drv_reset,
+	.init = test_drv_init,
+	.enable = test_drv_enable,
+	.set_color = test_drv_set_color,
+	.set_scale = test_drv_set_scale,
+	.set_gcc = test_drv_set_gcc,
+};
+
+extern int demo_interval_ms;
+
+static int test_rgbkbd_startup(void)
+{
+	struct rgbkbd *ctx;
+	struct rgb_s color;
+	int g, x, y, c, r;
+
+	demo_interval_ms = 1;
+
+	/* Let RGBKBD task run. */
+	task_wait_event(-1);
+
+	/* Check 'DOT' demo. */
+	for (x = 0; x < rgbkbd_hsize; x++) {
+		g = x / rgbkbds[0].cfg->col_len;
+		c = x % rgbkbds[0].cfg->col_len;
+		ctx = &rgbkbds[g];
+		for (y = 0; y < ctx->cfg->row_len; y++) {
+			r = y;
+			color = ctx->buf[ctx->cfg->row_len * c + r];
+			zassert_equal(color.r, 0, "R = 0");
+			zassert_equal(color.g, 0, "G = 0");
+			zassert_equal(color.b, 0, "B = 0");
+
+			r++;
+			if (r >= ctx->cfg->row_len) {
+				r = 0;
+				c++;
+				if (c >= rgbkbds[0].cfg->col_len) {
+					task_wait_event(-1);
+					break;
+				}
+			}
+			color = ctx->buf[ctx->cfg->row_len * c + r];
+			zassert_equal(color.r, 0x80, "R = 0x80");
+			zassert_equal(color.g, 0, "G = 0");
+			zassert_equal(color.b, 0, "B = 0");
+
+			task_wait_event(-1);
+		}
+	}
+
+	return EC_SUCCESS;
+}
+
+int cc_rgb(int argc, const char **argv);
+extern enum ec_rgbkbd_demo demo;
+
+static int test_rgbkbd_console_command(void)
+{
+	struct rgbkbd *ctx;
+	int argc;
+	char buf[8];
+	int i, x, y, r, c;
+	uint8_t offset;
+	const char *argv_demo[] = { "rgbk", "demo", "0" };
+	const char *argv_gcc[] = { "rgbk", "100" };
+	const char *argv_color[] = { "rgbk", buf, "0x010203" };
+	const char *argv_all[] = { "rgbk", "all", "0x010203" };
+
+	/* Test 'rgbk demo 0'. */
+	before_test();
+	argc = ARRAY_SIZE(argv_demo);
+	zassert_equal(demo, 2, "demo == 2");
+	zassert_equal(cc_rgb(argc, argv_demo), EC_SUCCESS, "rgbk demo 0");
+	zassert_equal(demo, 0, "demo == 0");
+
+	/* Test 'rgbk 100'. */
+	before_test();
+	argc = ARRAY_SIZE(argv_gcc);
+	zassert_equal(cc_rgb(argc, argv_gcc), EC_SUCCESS, "rgbk 100");
+	zassert_equal(mock_state.count_drv_set_gcc, rgbkbd_count,
+		      "set_gcc() called");
+	zassert_equal(mock_state.gcc_level, 100, "gcc == 100");
+
+	/* Test 'rgbk 1,1 1 2 3'. */
+	before_test();
+	ctx = &rgbkbds[0];
+	x = 1;
+	y = 1;
+	offset = rgbkbd_vsize * x + y;
+	sprintf(buf, "%d,%d", x, y);
+	argc = ARRAY_SIZE(argv_color);
+	zassert_equal(cc_rgb(argc, argv_color), EC_SUCCESS, "rgbk %s 0x010203",
+		      buf);
+	zassert_equal(ctx->buf[offset].r, 1, "R = 1");
+	zassert_equal(ctx->buf[offset].g, 2, "G = 2");
+	zassert_equal(ctx->buf[offset].b, 3, "B = 3");
+
+	/* Test 'rgbk 1,-1 1 2 3'. */
+	before_test();
+	ctx = &rgbkbds[0];
+	x = 1;
+	y = -1;
+	sprintf(buf, "%d,%d", x, y);
+	argc = ARRAY_SIZE(argv_color);
+	zassert_equal(cc_rgb(argc, argv_color), EC_SUCCESS, "rgbk %s 1 2 3",
+		      buf);
+	for (r = 0; r < rgbkbd_vsize; r++) {
+		offset = rgbkbd_vsize * x + r;
+		zassert_equal(ctx->buf[offset].r, 1, "R = 1");
+		zassert_equal(ctx->buf[offset].g, 2, "G = 2");
+		zassert_equal(ctx->buf[offset].b, 3, "B = 3");
+	}
+
+	/* Test 'rgbk -1,1 1 2 3'. */
+	before_test();
+	x = -1;
+	y = 1;
+	sprintf(buf, "%d,%d", x, y);
+	argc = ARRAY_SIZE(argv_color);
+	zassert_equal(cc_rgb(argc, argv_color), EC_SUCCESS, "rgbk %s 1 2 3",
+		      buf);
+	for (c = 0; c < rgbkbd_hsize; c++) {
+		ctx = &rgbkbds[c / rgbkbds[0].cfg->col_len];
+		offset = rgbkbd_vsize * (c % ctx->cfg->col_len) + y;
+		zassert_equal(ctx->buf[offset].r, 1, "R = 1");
+		zassert_equal(ctx->buf[offset].g, 2, "G = 2");
+		zassert_equal(ctx->buf[offset].b, 3, "B = 3");
+	}
+
+	/* Test 'rgbk all 1 2 3'. */
+	before_test();
+	argc = ARRAY_SIZE(argv_all);
+	zassert_equal(cc_rgb(argc, argv_all), EC_SUCCESS, "rgbk all 1 2 3");
+	for (i = 0; i < rgbkbd_count; i++) {
+		ctx = &rgbkbds[i];
+		for (c = 0; c < ctx->cfg->col_len; c++) {
+			for (r = 0; r < ctx->cfg->row_len; r++) {
+				offset = rgbkbd_vsize * c + r;
+				zassert_equal(ctx->buf[offset].r, 1, "R = 1");
+				zassert_equal(ctx->buf[offset].g, 2, "G = 2");
+				zassert_equal(ctx->buf[offset].b, 3, "B = 3");
+			}
+		}
+	}
+
+	return EC_SUCCESS;
+}
+
+struct rgb_s rotate_color(struct rgb_s color, int step);
+uint8_t get_grid_size(const struct rgbkbd *ctx);
+
+static int test_rgbkbd_rotate_color(void)
+{
+	struct rgb_s color = {};
+	const int step = 32;
+	int r, g, b;
+
+	for (b = 0; b < 0x100 / step; b++) {
+		zassert_equal(color.r, 0, "R = 0");
+		zassert_equal(color.g, 0, "G = 0");
+		zassert_equal(color.b, b * step, "B += 32");
+		for (g = 0; g < 0x100 / step; g++) {
+			zassert_equal(color.r, 0, "R = 0");
+			zassert_equal(color.g, g * step, "G += 32");
+			zassert_equal(color.b, b * step, "B = B");
+			for (r = 0; r < 0x100 / step; r++) {
+				zassert_equal(color.r, r * step, "R += 32");
+				zassert_equal(color.g, g * step, "G = G");
+				zassert_equal(color.b, b * step, "B = B");
+				color = rotate_color(color, step);
+			}
+		}
+	}
+	zassert_equal(color.r, 0, "R = 0");
+	zassert_equal(color.g, 0, "G = 0");
+	zassert_equal(color.b, 0, "B = 0");
+
+	return EC_SUCCESS;
+}
+
+static int test_rgbkbd_demo_flow(void)
+{
+	struct rgb_s copy[ARRAY_SIZE(rgbkbds)][RGB_GRID0_COL * RGB_GRID0_ROW];
+	const char *argv_demo[] = { "rgbk", "demo", "1" };
+	struct rgb_s *p;
+	int argc;
+	struct rgbkbd *ctx;
+	struct rgb_s color = {};
+	const int step = 32;
+	uint8_t len;
+	int i, j, g;
+
+	argc = ARRAY_SIZE(argv_demo);
+	zassert_equal(cc_rgb(argc, argv_demo), EC_SUCCESS, "rgbk demo flow");
+
+	for (j = 0; j < 0x100 / step; j++) {
+		/* Take a snapshot. */
+		memcpy(&copy[0], rgbkbds[0].buf, sizeof(copy[0]));
+		memcpy(&copy[1], rgbkbds[1].buf, sizeof(copy[1]));
+
+		/* Let demo run one iteration. */
+		task_wait_event(-1);
+
+		/* Compare with the snapshot. */
+		for (g = rgbkbd_count - 1; g >= 0; g--) {
+			ctx = &rgbkbds[g];
+			p = copy[g];
+			len = get_grid_size(ctx);
+			for (i = len - 1; i > 0; i--) {
+				zassert_equal(ctx->buf[i].r, p[i - 1].r,
+					      "i <- i-1");
+			}
+			if (g > 0) {
+				len = get_grid_size(&rgbkbds[g - 1]);
+				p = copy[g - 1];
+				zassert_equal(ctx->buf[0].r, p[len - 1].r,
+					      "grid1[0] <- grid0[last]");
+			}
+		}
+
+		/* After one run, a new color will be injected to (0,0). */
+		color = rotate_color(color, step);
+		zassert_equal(ctx->buf[0].r, color.r, "(0,0) <- new color");
+	}
+
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
+{
+	RUN_TEST(test_rgbkbd_startup);
+	RUN_TEST(test_rgbkbd_console_command);
+	RUN_TEST(test_rgbkbd_rotate_color);
+	RUN_TEST(test_rgbkbd_demo_flow);
+	RUN_TEST(test_rgbkbd_map);
+	test_print_result();
+}
diff --git a/test/rgb_keyboard.tasklist b/test/rgb_keyboard.tasklist
new file mode 100644
index 0000000000..9b25deacfb
--- /dev/null
+++ b/test/rgb_keyboard.tasklist
@@ -0,0 +1,10 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST \
+	TASK_TEST(RGBKBD, rgbkbd_task, NULL, 2048)
diff --git a/test/rng_benchmark.cc b/test/rng_benchmark.cc
new file mode 100644
index 0000000000..10716f863d
--- /dev/null
+++ b/test/rng_benchmark.cc
@@ -0,0 +1,81 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Measure performance of the hardware True Random Number Generator (TRNG)
+ * compared to the std::rand().
+ */
+
+#include "benchmark.h"
+#include "console.h"
+
+#include <array>
+#include <cstdint>
+#include <cstdlib>
+
+extern "C" {
+#include "test_util.h"
+#include "trng.h"
+}
+
+test_static int test_rng()
+{
+	constexpr int num_iterations = 100;
+	Benchmark benchmark({ .num_iterations = num_iterations });
+	std::array<uint32_t, num_iterations> trng_out;
+	std::array<int, num_iterations> rand_out;
+
+	// Try the hardware true random number generator
+	trng_out.fill(0);
+
+	trng_init();
+	auto result = benchmark.run("trng", [&trng_out]() {
+		static int i = 0;
+		trng_rand_bytes(&trng_out[i++], sizeof(uint32_t));
+	});
+	trng_exit();
+
+	TEST_ASSERT(result.has_value());
+	for (int i = 0; i < trng_out.size() - 1; ++i) {
+		TEST_NE(trng_out[i], trng_out[i + 1], "%d");
+		cflush();
+	}
+
+	// Repeat the test by turning the TNRG on and off at each iteration
+	trng_out.fill(0);
+	result = benchmark.run("trng_on_off", [&trng_out]() {
+		trng_init();
+		static int i = 0;
+		trng_rand_bytes(&trng_out[i++], sizeof(uint32_t));
+		trng_exit();
+	});
+
+	TEST_ASSERT(result.has_value());
+	for (int i = 0; i < trng_out.size() - 1; ++i) {
+		TEST_NE(trng_out[i], trng_out[i + 1], "%d");
+		cflush();
+	}
+
+	// Repeat the test using std::rand() for comparison
+	rand_out.fill(0);
+	result = benchmark.run("std::rand", [&rand_out]() {
+		static int i = 0;
+		rand_out[i++] = std::rand();
+	});
+
+	TEST_ASSERT(result.has_value());
+	for (int i = 0; i < rand_out.size() - 1; ++i) {
+		TEST_NE(rand_out[i], rand_out[i + 1], "%d");
+		cflush();
+	}
+
+	benchmark.print_results();
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
+{
+	test_reset();
+	RUN_TEST(test_rng);
+	test_print_result();
+}
\ No newline at end of file
diff --git a/test/rng_benchmark.tasklist b/test/rng_benchmark.tasklist
new file mode 100644
index 0000000000..19615b9ea8
--- /dev/null
+++ b/test/rng_benchmark.tasklist
@@ -0,0 +1,9 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST
\ No newline at end of file
diff --git a/test/rollback.c b/test/rollback.c
index 50c65e876d..5d16c4509e 100644
--- a/test/rollback.c
+++ b/test/rollback.c
@@ -1,14 +1,15 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <stdbool.h>
 #include "flash.h"
 #include "mpu.h"
 #include "string.h"
 #include "test_util.h"
 
+#include <stdbool.h>
+
 struct rollback_info {
 	int region_0_offset;
 	int region_1_offset;
@@ -19,7 +20,7 @@ struct rollback_info {
  * config headers, so that if the headers are accidentally changed we can catch
  * it.
  */
-#if defined(CHIP_VARIANT_STM32F412)
+#if defined(CHIP_VARIANT_STM32F412) || defined(CHIP_VARIANT_NPCX9M8S)
 struct rollback_info rollback_info = {
 	.region_0_offset = 0x20000,
 	.region_1_offset = 0x40000,
@@ -46,7 +47,8 @@ test_static int read_rollback_region(const struct rollback_info *info,
 				   info->region_1_offset;
 
 	for (i = 0; i < info->region_size_bytes; i++) {
-		if (flash_read(offset + i, sizeof(data), &data) == EC_SUCCESS)
+		if (crec_flash_read(offset + i, sizeof(data), &data) ==
+		    EC_SUCCESS)
 			bytes_read++;
 	}
 
@@ -104,7 +106,7 @@ test_static int test_lock_rollback_region_1(void)
 	return _test_lock_rollback(&rollback_info, 1);
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	if (argc < 2) {
 		ccprintf("usage: runtest [region0|region1]\n");
diff --git a/test/rollback.tasklist b/test/rollback.tasklist
index 51734f058d..a1f1a94e2d 100644
--- a/test/rollback.tasklist
+++ b/test/rollback.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/rollback_entropy.c b/test/rollback_entropy.c
index 8b9ace2f31..50a8cb4701 100644
--- a/test/rollback_entropy.c
+++ b/test/rollback_entropy.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,9 +12,7 @@
 static const uint32_t VALID_ROLLBACK_COOKIE = 0x0b112233;
 static const uint32_t UNINITIALIZED_ROLLBACK_COOKIE = 0xffffffff;
 
-static const uint8_t FAKE_ENTROPY[] = {
-	0xff, 0xff, 0xff, 0xff
-};
+static const uint8_t FAKE_ENTROPY[] = { 0xff, 0xff, 0xff, 0xff };
 
 /*
  * Generated by concatenating 32-bytes (256-bits) of zeros with the 4 bytes
@@ -26,13 +24,12 @@ static const uint8_t FAKE_ENTROPY[] = {
  *
  * 890ed82cf09f22243bdc4252e4d79c8a9810c1391f455dce37a7b732eb0a0e4f
  */
-#define EXPECTED_SECRET \
-	0x89, 0x0e, 0xd8, 0x2c, 0xf0, 0x9f, 0x22, 0x24, 0x3b, 0xdc, 0x42, \
-	0x52, 0xe4, 0xd7, 0x9c, 0x8a, 0x98, 0x10, 0xc1, 0x39, 0x1f, 0x45, \
-	0x5d, 0xce, 0x37, 0xa7, 0xb7, 0x32, 0xeb, 0x0a, 0x0e, 0x4f
-static const uint8_t _EXPECTED_SECRET[] = {
-	EXPECTED_SECRET
-};
+#define EXPECTED_SECRET                                                     \
+	0x89, 0x0e, 0xd8, 0x2c, 0xf0, 0x9f, 0x22, 0x24, 0x3b, 0xdc, 0x42,   \
+		0x52, 0xe4, 0xd7, 0x9c, 0x8a, 0x98, 0x10, 0xc1, 0x39, 0x1f, \
+		0x45, 0x5d, 0xce, 0x37, 0xa7, 0xb7, 0x32, 0xeb, 0x0a, 0x0e, \
+		0x4f
+__maybe_unused static const uint8_t _EXPECTED_SECRET[] = { EXPECTED_SECRET };
 BUILD_ASSERT(sizeof(_EXPECTED_SECRET) == CONFIG_ROLLBACK_SECRET_SIZE);
 
 /*
@@ -45,21 +42,20 @@ BUILD_ASSERT(sizeof(_EXPECTED_SECRET) == CONFIG_ROLLBACK_SECRET_SIZE);
  *
  * b5d2c08b1f9109ac5c67de15486f0ac267ef9501bd9f646f4ea80085cb08284c
  */
-#define EXPECTED_SECRET2 \
-	0xb5, 0xd2, 0xc0, 0x8b, 0x1f, 0x91, 0x09, 0xac, 0x5c, 0x67, 0xde, \
-	0x15, 0x48, 0x6f, 0x0a, 0xc2, 0x67, 0xef, 0x95, 0x01, 0xbd, 0x9f, \
-	0x64, 0x6f, 0x4e, 0xa8, 0x00, 0x85, 0xcb, 0x08, 0x28, 0x4c
-static const uint8_t _EXPECTED_SECRET2[] = {
-	EXPECTED_SECRET2
-};
+#define EXPECTED_SECRET2                                                    \
+	0xb5, 0xd2, 0xc0, 0x8b, 0x1f, 0x91, 0x09, 0xac, 0x5c, 0x67, 0xde,   \
+		0x15, 0x48, 0x6f, 0x0a, 0xc2, 0x67, 0xef, 0x95, 0x01, 0xbd, \
+		0x9f, 0x64, 0x6f, 0x4e, 0xa8, 0x00, 0x85, 0xcb, 0x08, 0x28, \
+		0x4c
+__maybe_unused static const uint8_t _EXPECTED_SECRET2[] = { EXPECTED_SECRET2 };
 BUILD_ASSERT(sizeof(_EXPECTED_SECRET2) == CONFIG_ROLLBACK_SECRET_SIZE);
 
-#define EXPECTED_UNINITIALIZED_ROLLBACK_SECRET \
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, \
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, \
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, \
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-static const uint8_t _EXPECTED_UNINITIALIZED_ROLLBACK_SECRET[] = {
+#define EXPECTED_UNINITIALIZED_ROLLBACK_SECRET                              \
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,   \
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, \
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, \
+		0xff,
+__maybe_unused static const uint8_t _EXPECTED_UNINITIALIZED_ROLLBACK_SECRET[] = {
 	EXPECTED_UNINITIALIZED_ROLLBACK_SECRET
 };
 BUILD_ASSERT(sizeof(_EXPECTED_UNINITIALIZED_ROLLBACK_SECRET) ==
@@ -142,7 +138,8 @@ test_static int test_add_entropy(void)
 	/* Immediately after boot region 1 should not yet be initialized. */
 	rv = read_rollback(1, &rb_data);
 	TEST_EQ(rv, EC_SUCCESS, "%d");
-	TEST_EQ(check_equal(&rb_data, &expected_uninitialized), EC_SUCCESS, "%d");
+	TEST_EQ(check_equal(&rb_data, &expected_uninitialized), EC_SUCCESS,
+		"%d");
 
 	/*
 	 * Add entropy. The result should end up being written to the unused
@@ -185,7 +182,7 @@ test_static int test_add_entropy(void)
 	return rv;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	ccprintf("Running rollback_entropy test\n");
 	RUN_TEST(test_add_entropy);
diff --git a/test/rollback_entropy.tasklist b/test/rollback_entropy.tasklist
index 51734f058d..a1f1a94e2d 100644
--- a/test/rollback_entropy.tasklist
+++ b/test/rollback_entropy.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/rollback_secret.c b/test/rollback_secret.c
new file mode 100644
index 0000000000..46ecfa587b
--- /dev/null
+++ b/test/rollback_secret.c
@@ -0,0 +1,68 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "mock/rollback_latest_mock.h"
+#include "rollback.h"
+#include "rollback_private.h"
+#include "string.h"
+#include "system.h"
+#include "test_util.h"
+
+#include <stdint.h>
+
+extern int get_latest_rollback(struct rollback_data *data);
+
+test_static int test_get_rollback_secret_latest_rollback_fail(void)
+{
+	struct rollback_data test_data;
+	uint8_t secret[32] = { 0 };
+
+	mock_ctrl_latest_rollback.output_type = GET_LATEST_ROLLBACK_FAIL;
+	TEST_ASSERT(get_latest_rollback(&test_data) == -5);
+
+	TEST_ASSERT(rollback_get_secret(secret) == EC_ERROR_UNKNOWN);
+
+	return EC_SUCCESS;
+}
+
+test_static int test_get_rollback_secret_latest_rollback_secret_zeros(void)
+{
+	struct rollback_data test_data;
+	uint8_t secret[32];
+
+	mock_ctrl_latest_rollback.output_type = GET_LATEST_ROLLBACK_ZEROS;
+	TEST_ASSERT(get_latest_rollback(&test_data) == EC_SUCCESS);
+	TEST_ASSERT_ARRAY_EQ(test_data.secret,
+			     fake_latest_rollback_zeros.secret,
+			     sizeof(fake_latest_rollback_zeros.secret));
+
+	TEST_ASSERT(rollback_get_secret(secret) == EC_ERROR_UNKNOWN);
+
+	return EC_SUCCESS;
+}
+
+test_static int test_get_rollback_secret_latest_rollback_secret_succeed(void)
+{
+	struct rollback_data test_data;
+	uint8_t secret[32];
+
+	mock_ctrl_latest_rollback.output_type = GET_LATEST_ROLLBACK_REAL;
+	TEST_ASSERT(get_latest_rollback(&test_data) == EC_SUCCESS);
+	TEST_ASSERT_ARRAY_EQ(test_data.secret, fake_latest_rollback_real.secret,
+			     sizeof(fake_latest_rollback_real.secret));
+
+	TEST_ASSERT(rollback_get_secret(secret) == EC_SUCCESS);
+	TEST_ASSERT_ARRAY_EQ(secret, test_data.secret, sizeof(secret));
+
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
+{
+	RUN_TEST(test_get_rollback_secret_latest_rollback_fail);
+	RUN_TEST(test_get_rollback_secret_latest_rollback_secret_zeros);
+	RUN_TEST(test_get_rollback_secret_latest_rollback_secret_succeed);
+	test_print_result();
+}
diff --git a/test/rollback_secret.mocklist b/test/rollback_secret.mocklist
new file mode 100644
index 0000000000..1a22d1d4b2
--- /dev/null
+++ b/test/rollback_secret.mocklist
@@ -0,0 +1,7 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define CONFIG_TEST_MOCK_LIST \
+  MOCK(ROLLBACK_LATEST)
diff --git a/test/rollback_secret.tasklist b/test/rollback_secret.tasklist
new file mode 100644
index 0000000000..844ddb6c10
--- /dev/null
+++ b/test/rollback_secret.tasklist
@@ -0,0 +1,9 @@
+/* Copyright 2019 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST
diff --git a/test/rsa.c b/test/rsa.c
index cd9530c4ad..a63b274711 100644
--- a/test/rsa.c
+++ b/test/rsa.c
@@ -1,25 +1,29 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Tests RSA implementation.
  */
 
-#include "console.h"
 #include "common.h"
+#include "console.h"
 #include "rsa.h"
 #include "test_util.h"
 #include "util.h"
 
 #ifdef TEST_RSA3
+#if CONFIG_RSA_KEY_SIZE == 3072
+#include "rsa3072-3.h"
+#else
 #include "rsa2048-3.h"
+#endif
 #else
 #include "rsa2048-F4.h"
 #endif
 
-static uint32_t rsa_workbuf[3 * RSANUMBYTES/4];
+static uint32_t rsa_workbuf[3 * RSANUMBYTES / 4];
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	int good;
 
@@ -41,7 +45,7 @@ void run_test(int argc, char **argv)
 	ccprintf("RSA verify FAILED (as expected)\n");
 
 	/* Test with a wrong signature */
-	good = rsa_verify(rsa_key, sig+1, hash, rsa_workbuf);
+	good = rsa_verify(rsa_key, sig + 1, hash, rsa_workbuf);
 	if (good) {
 		ccprintf("RSA verify OK (expected fail)\n");
 		test_fail();
@@ -51,4 +55,3 @@ void run_test(int argc, char **argv)
 
 	test_pass();
 }
-
diff --git a/test/rsa.tasklist b/test/rsa.tasklist
index f46a2eaa1d..bf2309064a 100644
--- a/test/rsa.tasklist
+++ b/test/rsa.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/rsa2048-3.h b/test/rsa2048-3.h
index d1b15c15a4..17b3c8989a 100644
--- a/test/rsa2048-3.h
+++ b/test/rsa2048-3.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -13,7 +13,7 @@
  * # dumpRSAPublicKey -pub key.pub | xxd -i
  */
 const uint8_t rsa_data[] = {
-	0x40, 0x00, 0x00, 0x00, 0x0f, 0x46, 0xe8, 0x2c,	0x11, 0x17, 0x38, 0xfd,
+	0x40, 0x00, 0x00, 0x00, 0x0f, 0x46, 0xe8, 0x2c, 0x11, 0x17, 0x38, 0xfd,
 	0xef, 0xa2, 0xb5, 0x2d, 0x6d, 0x76, 0xe1, 0x70, 0x7d, 0x67, 0xb1, 0x9a,
 	0x18, 0x78, 0x90, 0xe2, 0xce, 0xa6, 0x81, 0xa0, 0x13, 0x37, 0xf2, 0x71,
 	0xf0, 0x44, 0x96, 0xaf, 0x52, 0x53, 0xd4, 0x23, 0x51, 0x19, 0xe5, 0xb0,
@@ -65,18 +65,16 @@ BUILD_ASSERT(sizeof(*rsa_key) == sizeof(rsa_data));
 /* SHA-256 sum to verify:
  * # sha256sum README | sed -e 's/\(..\)/0x\1, /mg'
  */
-const uint8_t hash[] = {
-	0x6c, 0x5f, 0xef, 0x7f, 0x63, 0x1d, 0xb4, 0x35, 0x6c, 0xae, 0x8b, 0x2a,
-	0x4e, 0xde, 0xc5, 0xeb, 0x11, 0xba, 0x1f, 0x44, 0x40, 0xb6, 0x3a, 0x52,
-	0xf2, 0x70, 0xef, 0xee, 0x44, 0x4b, 0x57, 0x62
-};
+const uint8_t hash[] = { 0x6c, 0x5f, 0xef, 0x7f, 0x63, 0x1d, 0xb4, 0x35,
+			 0x6c, 0xae, 0x8b, 0x2a, 0x4e, 0xde, 0xc5, 0xeb,
+			 0x11, 0xba, 0x1f, 0x44, 0x40, 0xb6, 0x3a, 0x52,
+			 0xf2, 0x70, 0xef, 0xee, 0x44, 0x4b, 0x57, 0x62 };
 
 /* Incorrect hash to test the negative case */
-const uint8_t hash_wrong[] = {
-	0x61, 0x1b, 0xd2, 0x44, 0xc7, 0x18, 0xa7, 0x2d, 0x0f, 0x2d, 0x3d, 0x0f,
-	0xe3, 0xb3, 0xc5, 0xe4, 0x12, 0xc2, 0x7b, 0x1e, 0x05, 0x2c, 0x6f, 0xad,
-	0xc4, 0xac, 0x71, 0x55, 0xe8, 0x80, 0x5c, 0x38
-};
+const uint8_t hash_wrong[] = { 0x61, 0x1b, 0xd2, 0x44, 0xc7, 0x18, 0xa7, 0x2d,
+			       0x0f, 0x2d, 0x3d, 0x0f, 0xe3, 0xb3, 0xc5, 0xe4,
+			       0x12, 0xc2, 0x7b, 0x1e, 0x05, 0x2c, 0x6f, 0xad,
+			       0xc4, 0xac, 0x71, 0x55, 0xe8, 0x80, 0x5c, 0x38 };
 
 /* Generate signature using futility:
  * # futility create key.pem
diff --git a/test/rsa2048-F4.h b/test/rsa2048-F4.h
index afe66a198f..08b8f70155 100644
--- a/test/rsa2048-F4.h
+++ b/test/rsa2048-F4.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -65,18 +65,16 @@ BUILD_ASSERT(sizeof(*rsa_key) == sizeof(rsa_data));
 /* SHA-256 sum to verify:
  * # sha256sum README | sed -e 's/\(..\)/0x\1, /mg'
  */
-const uint8_t hash[] = {
-	0x6c, 0x5f, 0xef, 0x7f, 0x63, 0x1d, 0xb4, 0x35, 0x6c, 0xae, 0x8b, 0x2a,
-	0x4e, 0xde, 0xc5, 0xeb, 0x11, 0xba, 0x1f, 0x44, 0x40, 0xb6, 0x3a, 0x52,
-	0xf2, 0x70, 0xef, 0xee, 0x44, 0x4b, 0x57, 0x62
-};
+const uint8_t hash[] = { 0x6c, 0x5f, 0xef, 0x7f, 0x63, 0x1d, 0xb4, 0x35,
+			 0x6c, 0xae, 0x8b, 0x2a, 0x4e, 0xde, 0xc5, 0xeb,
+			 0x11, 0xba, 0x1f, 0x44, 0x40, 0xb6, 0x3a, 0x52,
+			 0xf2, 0x70, 0xef, 0xee, 0x44, 0x4b, 0x57, 0x62 };
 
 /* Incorrect hash to test the negative case */
-const uint8_t hash_wrong[] = {
-	0x61, 0x1b, 0xd2, 0x44, 0xc7, 0x18, 0xa7, 0x2d, 0x0f, 0x2d, 0x3d, 0x0f,
-	0xe3, 0xb3, 0xc5, 0xe4, 0x12, 0xc2, 0x7b, 0x1e, 0x05, 0x2c, 0x6f, 0xad,
-	0xc4, 0xac, 0x71, 0x55, 0xe8, 0x80, 0x5c, 0x38
-};
+const uint8_t hash_wrong[] = { 0x61, 0x1b, 0xd2, 0x44, 0xc7, 0x18, 0xa7, 0x2d,
+			       0x0f, 0x2d, 0x3d, 0x0f, 0xe3, 0xb3, 0xc5, 0xe4,
+			       0x12, 0xc2, 0x7b, 0x1e, 0x05, 0x2c, 0x6f, 0xad,
+			       0xc4, 0xac, 0x71, 0x55, 0xe8, 0x80, 0x5c, 0x38 };
 
 /* Generate signature using futility:
  * # futility create key.pem
diff --git a/test/rsa3072-3.h b/test/rsa3072-3.h
new file mode 100644
index 0000000000..3ad93fafe8
--- /dev/null
+++ b/test/rsa3072-3.h
@@ -0,0 +1,138 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * RSA 3072 with 3 exponent public key and verification.
+ * Private key in rsa3072-3.pem.
+ */
+
+/* First generate a key:
+ * # openssl genrsa -3 -out key.pem 3072
+ * # openssl rsa -in key.pem -pubout > key.pub
+ * Then dump the key: sudo emerge vboot_reference
+ * # /usr/bin/dumpRSAPublicKey -pub key.pub | xxd -i
+ */
+const uint8_t rsa_data[] = {
+	0x60, 0x00, 0x00, 0x00, 0xdd, 0x54, 0xe6, 0xe2, 0x8b, 0xdc, 0xea, 0xd2,
+	0x58, 0x10, 0x72, 0xf1, 0x39, 0x2d, 0x10, 0x6e, 0x37, 0x4b, 0x19, 0x0d,
+	0x0a, 0x02, 0x80, 0xdc, 0xb9, 0xee, 0xb4, 0x6b, 0xb6, 0x19, 0x73, 0x22,
+	0x43, 0x09, 0x22, 0x7e, 0xf1, 0x48, 0xdd, 0xf2, 0x66, 0x12, 0x90, 0xb9,
+	0x58, 0x54, 0x4b, 0xc4, 0xce, 0xf0, 0xb3, 0xbf, 0xad, 0x86, 0x1a, 0x6a,
+	0x23, 0x66, 0x08, 0x10, 0x83, 0xda, 0xa3, 0xec, 0x8e, 0x36, 0x2d, 0xb2,
+	0x91, 0x2c, 0xbd, 0x11, 0x2f, 0xa8, 0xdc, 0x8f, 0x52, 0x7a, 0x23, 0x58,
+	0xad, 0x36, 0x9b, 0xde, 0xd6, 0x0d, 0x21, 0x1b, 0x5d, 0x7b, 0x1d, 0x51,
+	0x6d, 0x7e, 0xa1, 0xca, 0x13, 0x0a, 0x11, 0x29, 0x63, 0xaa, 0x6e, 0x64,
+	0x7a, 0x15, 0xa3, 0xf6, 0xed, 0xfd, 0xce, 0x5d, 0x17, 0xfb, 0x16, 0x38,
+	0x55, 0x0b, 0xed, 0x6b, 0x12, 0xf9, 0xcf, 0x8b, 0xa7, 0xeb, 0x92, 0xd0,
+	0x5e, 0x91, 0x91, 0x4e, 0x6e, 0x41, 0xa2, 0x88, 0x51, 0xf9, 0xf9, 0x0b,
+	0x99, 0x72, 0x2e, 0xab, 0x50, 0xbb, 0xc6, 0xc0, 0x64, 0x88, 0x26, 0x7f,
+	0xc1, 0x91, 0x8d, 0xe8, 0xea, 0x5a, 0x15, 0x1c, 0x0a, 0xac, 0xa3, 0x8a,
+	0x8f, 0x42, 0x68, 0xc6, 0x7d, 0x3a, 0x53, 0xf6, 0x6a, 0x65, 0x7a, 0xb4,
+	0x51, 0xf0, 0xce, 0xe3, 0x49, 0xd8, 0x38, 0x1a, 0x30, 0x1a, 0xd3, 0xa2,
+	0x98, 0xf8, 0x53, 0x6d, 0xa2, 0x35, 0x22, 0x92, 0xd8, 0x46, 0x7b, 0x9d,
+	0xc7, 0x25, 0xb6, 0xc6, 0x28, 0x12, 0x0d, 0x0d, 0x91, 0xbf, 0x9b, 0x58,
+	0x73, 0xc1, 0x78, 0x39, 0xed, 0x16, 0x61, 0x90, 0x25, 0x14, 0xba, 0x9b,
+	0x17, 0x4f, 0xaa, 0xf9, 0x5c, 0xfd, 0xc7, 0x18, 0xf3, 0x1d, 0xd7, 0xaa,
+	0xea, 0x11, 0x18, 0xbb, 0x24, 0x3d, 0xf0, 0x57, 0x33, 0x9c, 0x23, 0x04,
+	0x33, 0x81, 0xa0, 0x10, 0xc3, 0x6d, 0x12, 0xb6, 0xd0, 0xdc, 0xad, 0xd2,
+	0x9c, 0x76, 0x01, 0x7a, 0x70, 0x04, 0x72, 0x29, 0xeb, 0x82, 0x60, 0x1b,
+	0xea, 0x19, 0xe6, 0xdc, 0xeb, 0xec, 0xaf, 0xad, 0xce, 0xfa, 0x5b, 0xbc,
+	0x81, 0x0c, 0x82, 0x19, 0xde, 0xbd, 0x65, 0xe6, 0x69, 0x1b, 0x8e, 0x38,
+	0x93, 0xf3, 0x3f, 0x9f, 0x75, 0x69, 0xa9, 0x0f, 0xb7, 0x94, 0xca, 0xfd,
+	0x30, 0xa9, 0x09, 0x59, 0x77, 0xd3, 0xef, 0x8d, 0x0a, 0x11, 0xfa, 0x07,
+	0xd8, 0xe5, 0x35, 0x59, 0x23, 0xb5, 0x20, 0x28, 0xa7, 0x9f, 0x6d, 0xb6,
+	0x18, 0x72, 0x51, 0x06, 0x02, 0xe7, 0x2b, 0xfb, 0xa5, 0x96, 0xf8, 0x8b,
+	0x2d, 0xb4, 0x01, 0xd8, 0x66, 0xd0, 0x12, 0xa3, 0xd3, 0x67, 0x94, 0x37,
+	0x21, 0xb4, 0xfc, 0xc5, 0x73, 0xd7, 0x77, 0x39, 0x75, 0xdd, 0xb2, 0x57,
+	0x62, 0x83, 0xcd, 0x2d, 0xca, 0x8a, 0xf9, 0xd8, 0xc3, 0x00, 0xc2, 0x64,
+	0x45, 0xaa, 0xaa, 0xe7, 0xf8, 0xdb, 0x9c, 0xd4, 0x33, 0x77, 0x5b, 0x55,
+	0x57, 0x12, 0xcd, 0x33, 0xbe, 0x70, 0xa5, 0x78, 0x26, 0x3c, 0x56, 0xee,
+	0xe3, 0xac, 0x23, 0xfe, 0x54, 0x98, 0xd6, 0x2e, 0xfe, 0xdd, 0xc4, 0x5a,
+	0x23, 0xca, 0x5a, 0x22, 0xec, 0x8e, 0x36, 0x3b, 0xfb, 0x9f, 0x97, 0x7d,
+	0x75, 0x37, 0xf7, 0x59, 0xef, 0x1d, 0x96, 0xad, 0x2b, 0x82, 0x19, 0x67,
+	0x46, 0x7f, 0x92, 0x1f, 0xcb, 0xf0, 0xf7, 0x31, 0x72, 0x34, 0x4d, 0xdd,
+	0x8b, 0x5b, 0x90, 0xe2, 0xeb, 0xdd, 0x04, 0x00, 0xde, 0x28, 0x15, 0x03,
+	0x6b, 0x4e, 0x4e, 0x6b, 0x03, 0xd0, 0x54, 0x81, 0xea, 0xe4, 0x26, 0xbb,
+	0x4c, 0x6f, 0x65, 0x70, 0x12, 0x6d, 0x84, 0x1d, 0x71, 0xfe, 0xc1, 0x63,
+	0x1c, 0x33, 0x43, 0xcd, 0x8a, 0x92, 0xa6, 0x2d, 0xa3, 0xbd, 0xef, 0x93,
+	0x39, 0x2f, 0x9b, 0xa9, 0x5c, 0x0d, 0xb9, 0x61, 0x23, 0xcf, 0x12, 0x1f,
+	0x98, 0x85, 0x19, 0xa7, 0x08, 0xfc, 0xee, 0x8e, 0x79, 0x25, 0x0b, 0xed,
+	0xb3, 0x72, 0xf4, 0x27, 0x9f, 0xee, 0x7b, 0x22, 0xd0, 0x6e, 0xdf, 0x4b,
+	0x05, 0xef, 0xbd, 0x13, 0xb6, 0x22, 0xeb, 0x9e, 0xc5, 0x7d, 0xb6, 0x1c,
+	0xfd, 0xf8, 0xc6, 0x82, 0x89, 0xd2, 0xc4, 0x01, 0xac, 0xec, 0xd5, 0xbd,
+	0x2d, 0xbb, 0x09, 0x17, 0x0f, 0xd6, 0xc1, 0xb9, 0x07, 0xf0, 0xce, 0x23,
+	0x81, 0x0c, 0xa9, 0x60, 0x58, 0x17, 0xbf, 0xf5, 0x14, 0xd0, 0x68, 0x33,
+	0xf6, 0xc6, 0xae, 0xc3, 0xc3, 0x1f, 0x01, 0xd6, 0xae, 0xc8, 0x94, 0xba,
+	0x35, 0x47, 0xa9, 0x77, 0x2b, 0x68, 0xd2, 0x75, 0x19, 0x75, 0x40, 0xce,
+	0x11, 0x93, 0xaa, 0xb9, 0x09, 0x37, 0x91, 0xca, 0x83, 0x3d, 0x7a, 0xb1,
+	0x03, 0x57, 0x34, 0x06, 0x37, 0x86, 0xf9, 0x64, 0xe4, 0xcf, 0x49, 0x0b,
+	0x20, 0x21, 0xda, 0x0a, 0x25, 0xd4, 0x17, 0x21, 0x73, 0x39, 0xf9, 0x2f,
+	0xeb, 0x81, 0x6f, 0x90, 0xea, 0x83, 0xfc, 0xc7, 0xe9, 0x44, 0xd1, 0xd2,
+	0x8b, 0xc5, 0xf3, 0x1f, 0x35, 0x1c, 0xc5, 0xa3, 0x75, 0x36, 0xb7, 0x84,
+	0xed, 0x67, 0xa0, 0xbd, 0xaf, 0x6b, 0x00, 0x15, 0x5a, 0x7c, 0x5c, 0xc7,
+	0x95, 0x22, 0x76, 0xd9, 0x9c, 0x1f, 0xf0, 0xb2, 0x6e, 0x5b, 0xcb, 0x32,
+	0x88, 0xa4, 0xc6, 0x7f, 0xfa, 0x2e, 0xc6, 0x40, 0x40, 0xa3, 0xe2, 0x57,
+	0xb7, 0x08, 0xe0, 0xe9, 0x93, 0x10, 0x95, 0x70, 0x2d, 0x90, 0x0c, 0xeb,
+	0x44, 0x50, 0xbc, 0xd9, 0xc7, 0xd5, 0x2b, 0x74, 0xac, 0x6e, 0x7f, 0xcf,
+	0xfa, 0x8c, 0xf6, 0x76, 0x77, 0x79, 0xf8, 0xf4, 0x11, 0x8e, 0x5a, 0xe4,
+	0x2c, 0xa2, 0x84, 0x56, 0xdb, 0x39, 0x54, 0x82, 0x8e, 0x85, 0x31, 0xc0,
+	0x51, 0xf7, 0x6c, 0x2c, 0x5f, 0xbc, 0x63, 0x5c, 0xf3, 0x68, 0x4e, 0xa4,
+	0x52, 0xc9, 0xe8, 0x06, 0xff, 0x94, 0xd3, 0xa1,
+};
+
+const struct rsa_public_key *rsa_key = (struct rsa_public_key *)rsa_data;
+BUILD_ASSERT(sizeof(*rsa_key) == sizeof(rsa_data));
+
+/* SHA-256 sum to verify:
+ * # sha256sum README.md | sed -e 's/\(..\)/0x\1, /mg'
+ */
+const uint8_t hash[] = { 0xc7, 0xc3, 0xd0, 0xa3, 0x7e, 0xbd, 0x50, 0xe8,
+			 0x3c, 0xb3, 0x5b, 0xed, 0x02, 0xf9, 0x8f, 0x97,
+			 0xf8, 0xb5, 0x23, 0x43, 0x74, 0xda, 0x0a, 0x24,
+			 0xdb, 0x04, 0xe4, 0x1e, 0xbd, 0x43, 0x02, 0xdc };
+
+/* Incorrect hash to test the negative case */
+const uint8_t hash_wrong[] = { 0x61, 0x1b, 0xd2, 0x44, 0xc7, 0x18, 0xa7, 0x2d,
+			       0x0f, 0x2d, 0x3d, 0x0f, 0xe3, 0xb3, 0xc5, 0xe4,
+			       0x12, 0xc2, 0x7b, 0x1e, 0x05, 0x2c, 0x6f, 0xad,
+			       0xc4, 0xac, 0x71, 0x55, 0xe8, 0x80, 0x5c, 0x38 };
+
+/* Generate signature using openssl:
+ * openssl dgst -sha256 -sign test/rsa3072-3.pem README.md | xxd -i
+ */
+const uint8_t sig[] = {
+	0xb3, 0xac, 0xcb, 0x5c, 0xbc, 0x82, 0x74, 0x14, 0xce, 0x7d, 0xbd, 0x3b,
+	0xc6, 0x6e, 0x2d, 0x3e, 0xfd, 0xdb, 0x76, 0xb3, 0xfe, 0xed, 0x29, 0xd6,
+	0xb8, 0x20, 0x8a, 0x79, 0xf8, 0xe4, 0x1b, 0xc1, 0x99, 0x21, 0x77, 0xb0,
+	0xa7, 0x49, 0xfc, 0x31, 0x70, 0xe2, 0x5c, 0xc9, 0xc4, 0xc8, 0x5b, 0xbd,
+	0xf9, 0xc9, 0x81, 0x43, 0x7e, 0x16, 0x23, 0xc7, 0xb3, 0x8f, 0x95, 0xca,
+	0xb2, 0x56, 0x96, 0xfc, 0x53, 0xba, 0xf3, 0x77, 0x31, 0xde, 0x69, 0x9f,
+	0x2e, 0xb1, 0xc0, 0xe1, 0xb9, 0x05, 0x7a, 0xf2, 0x92, 0x9c, 0xf2, 0x0b,
+	0x54, 0xa1, 0x93, 0x58, 0x52, 0x2e, 0x9b, 0x02, 0x59, 0x05, 0x67, 0xc2,
+	0x8c, 0x27, 0x1d, 0xc2, 0x70, 0x2f, 0x5c, 0x4f, 0xb2, 0xb4, 0x87, 0x71,
+	0x75, 0x33, 0x2d, 0x96, 0x02, 0x81, 0x80, 0x13, 0xb1, 0xff, 0x8a, 0x73,
+	0x1c, 0x66, 0x54, 0xec, 0x97, 0x08, 0x4f, 0x98, 0xec, 0x01, 0xa6, 0x93,
+	0x59, 0xa9, 0x16, 0x28, 0x41, 0x60, 0x83, 0xb2, 0xe1, 0xe8, 0x42, 0xf7,
+	0x92, 0x96, 0x5c, 0x91, 0x06, 0xf8, 0xde, 0x45, 0x67, 0x4e, 0xef, 0xde,
+	0xb5, 0x87, 0x72, 0x02, 0x5e, 0x39, 0x7a, 0xa7, 0xf2, 0x22, 0xbc, 0x10,
+	0x59, 0x13, 0xfb, 0x53, 0x98, 0x99, 0x2a, 0x51, 0xc5, 0x46, 0x7e, 0xdf,
+	0x6f, 0xd8, 0xbd, 0xcd, 0x0e, 0xd7, 0x00, 0x2f, 0x76, 0x17, 0x8b, 0xce,
+	0x05, 0x56, 0xc2, 0xe1, 0xcd, 0x37, 0xa1, 0x2f, 0xa6, 0xc4, 0xcd, 0xd5,
+	0xaf, 0x10, 0x9b, 0x1f, 0x72, 0x28, 0x14, 0x3f, 0xa1, 0x9d, 0x08, 0x7f,
+	0x3d, 0x0a, 0xac, 0x80, 0x7b, 0xe3, 0x31, 0x4f, 0x9c, 0x79, 0x7c, 0x4b,
+	0xd7, 0x01, 0xcc, 0x9f, 0xbd, 0x9d, 0x52, 0x84, 0xd7, 0xea, 0xf8, 0xc8,
+	0xf5, 0xf3, 0x0c, 0x83, 0x5c, 0x30, 0x0c, 0x50, 0x66, 0x5f, 0xee, 0x4d,
+	0x23, 0x8a, 0x32, 0x07, 0x55, 0xb1, 0xfa, 0x5e, 0x89, 0x57, 0x18, 0x24,
+	0xcc, 0x20, 0x30, 0x79, 0xf0, 0x4c, 0x09, 0xe2, 0x9a, 0x34, 0xc7, 0x07,
+	0xf7, 0x29, 0x3a, 0xcf, 0x38, 0x18, 0x2c, 0x53, 0x2f, 0x33, 0xca, 0x95,
+	0xfc, 0x3b, 0x23, 0x75, 0xbc, 0x15, 0xac, 0x1a, 0xbd, 0xf1, 0xa5, 0x6c,
+	0x3e, 0x4b, 0xc3, 0x39, 0xb2, 0x1e, 0x18, 0xf1, 0xb9, 0x28, 0xcd, 0x13,
+	0x05, 0x32, 0xd5, 0x46, 0x3e, 0x9b, 0x55, 0x9f, 0x13, 0xe3, 0x5d, 0x53,
+	0x6a, 0xa8, 0x93, 0x33, 0xbb, 0x78, 0x1d, 0x3a, 0xeb, 0xbd, 0x3d, 0x2e,
+	0xd1, 0xdc, 0x1c, 0xb6, 0x76, 0x6f, 0x29, 0x9f, 0x9f, 0x59, 0x23, 0x45,
+	0xcc, 0x80, 0x23, 0xd7, 0x51, 0x06, 0xc8, 0x72, 0x94, 0x3a, 0xf8, 0x14,
+	0x4d, 0x76, 0x2d, 0x59, 0x3c, 0xd7, 0x4e, 0x17, 0x52, 0xad, 0x1a, 0xe4,
+	0xa9, 0xfb, 0x09, 0xc8, 0xb4, 0x28, 0x0b, 0x7d, 0xa8, 0x0a, 0x71, 0x81,
+	/* Padding */
+	0x00
+};
diff --git a/test/rsa3072-3.pem b/test/rsa3072-3.pem
new file mode 100644
index 0000000000..78fbce265e
--- /dev/null
+++ b/test/rsa3072-3.pem
@@ -0,0 +1,39 @@
+-----BEGIN RSA PRIVATE KEY-----
+MIIG4wIBAAKCAYEA1Jzb+OeqqkVkwgDD2PmKyi3Ng2JXst11OXfXc8X8tCE3lGfT
+oxLQZtgBtC2L+Jal+yvnAgZRchi2bZ+nKCC1I1k15dgH+hEKje/Td1kJqTD9ypS3
+D6lpdZ8/85M4jhtp5mW93hmCDIG8W/rOra/s69zmGeobYILrKXIEcHoBdpzSrdzQ
+thJtwxCggTMEI5wzV/A9JLsYEeqq1x3zGMf9XPmqTxebuhQlkGEW7Tl4wXNYm7+R
+DQ0SKMa2Jcede0bYkiI1om1T+Jii0xowGjjYSePO8FG0emVq9lM6fcZoQo+Ko6wK
+HBVa6uiNkcF/JohkwMa7UKsucpkL+flRiKJBbk6RkV7Qkuuni8/5EmvtC1U4FvsX
+Xc797fajFXpkbqpjKREKE8qhfm1RHXtdGyEN1t6bNq1YI3pSj9yoLxG9LJGyLTaO
+7KPagxAIZiNqGoatv7PwzsRLVFi5kBJm8t1I8X4iCUMicxm2a7TuudyAAgoNGUs3
+bhAtOfFyEFjS6tyLAgEDAoIBgQCNvef7RRxxg5iBVdfl+7HcHokCQY/Mk6N7pTpN
+Lqh4FiUNmo0XYeBEkAEiyQf7DxlSHUSsBDZMEHmeam9wFc4XkM6ZOq/8C1xen+JP
+kLEbdf6HDc9fxkZOaiqiYiW0EkaZmSk+u6wIVn2SpzRzyp3yk0QRRrzrAfIboVhK
+/AD5veHJPeB5YZ6CCxWrd1gXvXeP9X4YfLq2nHHkvqIQhVOTURw0umfRYsO1lg9I
+0PsrojsSf7YIs2FwhHluhROnhI8qFy2Va0j/5ypoKtWitNOUb2K//I/E5a8s7N86
+GhG0Vn0iolTxgJfj5kI0/5B5jXRYrLCvOJvnmOL6rbR1HPOmSC62VorgvsF3ExXh
+Z+9mpjMjDdHZAZRLpr8Toj7nZabbIGZMfLFFutSvVXSvhNPezKeREJ3uS65E0oeK
+Vl3qi5IZA02X7WrlYJYop7HGH/ZSqR+iIIJEHhYhLt5oST3XZ3cSEUTupyWE1cxm
+2HBkuUULO8eIo9CmLEnLxUUjZlsCgcEA8yLuYy3pfAdUOJulycDHuTjN4BAsqXLV
+lpO/6Cq+jeNzChobcpWWUsx0E3gjaUfRTEEuSoHo/oHUIFjOGdv1VdsZjXIh0RS+
+3ltf2zMHoTwnsHIDrAIdyLMEylDQXefpKsievPj8YJx180/ZUcmaCV2s0YL//vxg
+moL3ynXkQQhHSbwz+TSEOkdU5r6G1TNiJnup3W3+elB7zmyU4yFboNC5P1clLiVM
+9InAq1mLn2CP9GCqtJTnU1ij55929C8NAoHBAN/cgt8efPy2jv4+Sdxo0zID7PBG
+sCmaDpxcK750jyYqW+Webz8+4MJCti7KAwbsZO+Cg/9UW5ix42Gb9L8a3p8HMfJq
+3nC4xnrX+GUc/lAfw7H0WOxKgbPJf622NbWp/7WX0eQWmzU4nCMrVMIQNf9N8wuR
+az8MbI4d5RUaTAu4D731Zo+LNfC30kJpWJwjWh06l34liXPbHI/fhHNOEI2SNi7S
+Fd75sS/qe3Q+S8uTlZQQ4WyFjO1WX3cRdEGT9wKBwQCiF0mXc/D9WjglvRkxKy/Q
+0IlACshw9zkPDSqaxymz7PdcEWehuQ7h3aK3pWzw2ouIK3Qxq/Cpq+LAOzQRPU45
+PLuzoWvguH8+55U8zK/A0sUgTAJyrBPbIgMxizWT7/DHMGnTUKhAaE6iNTuL27wG
+PnM2V1VUqEBnAfqG+ULWBYTb0s1Qza18L43vKa84zOwZp8aTnqmm4FKJnbiXa5Jr
+NdDU5MN0GN34W9XHkQe/lbVNlccjDe+M5cKaak9NdLMCgcEAlT2slL79/c8J/tQx
+PZs3dq1IoC8gG7wJvZLH1E20xBw9Q7701NSV1tckHzFXWfLt9QGtVOLnuyFCQRKj
+KhHpv1ohTEc+9dCEUeVQQ2ipir/Xy/g7SDGrzTD/ySQjznFVI7qL7WRneNBoF3I4
+gWAj/4lMsmDyKghIXr6YuLwysnq1KU5EX7Ij9c/hgZuQaBeRaNG6VBkGTTy9tT+t
+ojQLCQwkHza5P1EgypxSTX7dMmJjuAtA8wOzSOQ/pLZNgQ1PAoHAbZMZo5yF+yzC
+Ofu/Wq38ftt3KGzaiN+xwPu8MG8jFLNnQXCpI+qiszBK0lkS3W/yPlouUYJXfbec
+LCp/z+lfUe5glm7AUxvuSZ63ZBTx8q/Vgl7490mzFzOSoL5iBtnq3qzwGHWfM0au
+h3hlTdBpYnuIGqcU910JsJ3tdzcLoJe9OaihQrgBudGftAr9nm3uuvLtVRuHSAP1
+m6u+qq5Ae/0ejhJWnyPcYE4Gnv4JWLRYywBT0WpdSNiV/3aAPoq3
+-----END RSA PRIVATE KEY-----
diff --git a/test/rtc.c b/test/rtc.c
index 3e53f85611..3a006498f2 100644
--- a/test/rtc.c
+++ b/test/rtc.c
@@ -1,12 +1,12 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Tests for rtc time conversions
  */
 
-#include "console.h"
 #include "common.h"
+#include "console.h"
 #include "rtc.h"
 #include "test_util.h"
 #include "util.h"
@@ -16,15 +16,14 @@ static struct {
 	struct calendar_date time;
 	uint32_t sec;
 } test_case[] = {
-	{{8, 3, 1}, 1204329600},
-	{{17, 10, 1}, 1506816000},
+	{ { 8, 3, 1 }, 1204329600 },
+	{ { 17, 10, 1 }, 1506816000 },
 };
 
 static int calendar_time_comp(struct calendar_date time_1,
-			   struct calendar_date time_2)
+			      struct calendar_date time_2)
 {
-	return (time_1.year == time_2.year &&
-		time_1.month == time_2.month &&
+	return (time_1.year == time_2.year && time_1.month == time_2.month &&
 		time_1.day == time_2.day);
 }
 
@@ -96,7 +95,7 @@ static int test_time_conversion(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	RUN_TEST(test_time_conversion);
 
diff --git a/test/rtc.tasklist b/test/rtc.tasklist
index 80072bb620..329f9a3d28 100644
--- a/test/rtc.tasklist
+++ b/test/rtc.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/run_device_tests.py b/test/run_device_tests.py
index e6861824e9..f2e9e8dab9 100755
--- a/test/run_device_tests.py
+++ b/test/run_device_tests.py
@@ -1,406 +1,1000 @@
 #!/usr/bin/env python3
-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
+# pylint: disable=line-too-long
+
 """Runs unit tests on device and displays the results.
 
 This script assumes you have a ~/.servodrc config file with a line that
 corresponds to the board being tested.
 
 See https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/HEAD/docs/servo.md#servodrc
+
+In addition to running this script locally, you can also run it from a remote
+machine against a board connected to a local machine. For example:
+
+Start servod and JLink locally:
+
+(local chroot) $ sudo servod --board dragonclaw
+(local chroot) $ sudo JLinkRemoteServerCLExe -select USB
+
+Forward the FPMCU console on a TCP port:
+
+(local chroot) $ socat $(dut-control raw_fpmcu_console_uart_pty | cut -d: -f2) \
+                 tcp4-listen:10000,fork
+
+Forward all the ports to the remote machine:
+
+(local outside) $ ssh -R 9999:localhost:9999 <remote> -N
+(local outside) $ ssh -R 10000:localhost:10000 <remote> -N
+(local outside) $ ssh -R 19020:localhost:19020 <remote> -N
+
+Run the script on the remote machine:
+
+(remote chroot) ./test/run_device_tests.py --remote 127.0.0.1 \
+                --jlink_port 19020 --console_port 10000
 """
+# pylint: enable=line-too-long
+# TODO(b/267800058): refactor into multiple modules
+# pylint: disable=too-many-lines
+
 import argparse
 import concurrent
+from concurrent.futures.thread import ThreadPoolExecutor
+from dataclasses import dataclass
+from dataclasses import field
+from enum import Enum
 import io
 import logging
 import os
+from pathlib import Path
 import re
+import socket
 import subprocess
 import sys
 import time
-from concurrent.futures.thread import ThreadPoolExecutor
-from enum import Enum
-from pathlib import Path
-from typing import Optional, BinaryIO, List
+from typing import BinaryIO, Dict, List, Optional, Tuple
 
+# pylint: disable=import-error
 import colorama  # type: ignore[import]
+from contextlib2 import ExitStack
+import fmap
+
+
+# pylint: enable=import-error
 
 EC_DIR = Path(os.path.dirname(os.path.realpath(__file__))).parent
-FLASH_SCRIPT = os.path.join(EC_DIR, 'util/flash_jlink.py')
+JTRACE_FLASH_SCRIPT = os.path.join(EC_DIR, "util/flash_jlink.py")
+SERVO_MICRO_FLASH_SCRIPT = os.path.join(EC_DIR, "util/flash_ec")
+
+ALL_TESTS_PASSED_REGEX = re.compile(r"Pass!\r\n")
+ALL_TESTS_FAILED_REGEX = re.compile(r"Fail! \(\d+ tests\)\r\n")
+
+SINGLE_CHECK_PASSED_REGEX = re.compile(r"Pass: .*")
+SINGLE_CHECK_FAILED_REGEX = re.compile(r".*failed:.*")
 
-ALL_TESTS_PASSED_REGEX = re.compile(r'Pass!\r\n')
-ALL_TESTS_FAILED_REGEX = re.compile(r'Fail! \(\d+ tests\)\r\n')
+RW_IMAGE_BOOTED_REGEX = re.compile(r"^\[Image: RW.*")
 
-SINGLE_CHECK_PASSED_REGEX = re.compile(r'Pass: .*')
-SINGLE_CHECK_FAILED_REGEX = re.compile(r'.*failed:.*')
+ASSERTION_FAILURE_REGEX = re.compile(r"ASSERTION FAILURE.*")
 
 DATA_ACCESS_VIOLATION_8020000_REGEX = re.compile(
-    r'Data access violation, mfar = 8020000\r\n')
+    r"Data access violation, mfar = 8020000\r\n"
+)
 DATA_ACCESS_VIOLATION_8040000_REGEX = re.compile(
-    r'Data access violation, mfar = 8040000\r\n')
+    r"Data access violation, mfar = 8040000\r\n"
+)
+DATA_ACCESS_VIOLATION_80C0000_REGEX = re.compile(
+    r"Data access violation, mfar = 80c0000\r\n"
+)
+DATA_ACCESS_VIOLATION_80E0000_REGEX = re.compile(
+    r"Data access violation, mfar = 80e0000\r\n"
+)
 DATA_ACCESS_VIOLATION_20000000_REGEX = re.compile(
-    r'Data access violation, mfar = 20000000\r\n')
+    r"Data access violation, mfar = 20000000\r\n"
+)
+DATA_ACCESS_VIOLATION_24000000_REGEX = re.compile(
+    r"Data access violation, mfar = 24000000\r\n"
+)
+DATA_ACCESS_VIOLATION_64020000_REGEX = re.compile(
+    r"Data access violation, mfar = 64020000\r\n"
+)
+DATA_ACCESS_VIOLATION_64040000_REGEX = re.compile(
+    r"Data access violation, mfar = 64040000\r\n"
+)
+
+PRINTF_CALLED_REGEX = re.compile(r"printf called\r\n")
+
+BLOONCHIPPER = "bloonchipper"
+DARTMONKEY = "dartmonkey"
+HELIPILOT = "helipilot"
+
+JTRACE = "jtrace"
+SERVO_MICRO = "servo_micro"
+
+GCC = "gcc"
+CLANG = "clang"
+
+PRIVATE_YES = "yes"
+PRIVATE_NO = "no"
+PRIVATE_ONLY = "only"
+
+TEST_ASSETS_BUCKET = "gs://chromiumos-test-assets-public/fpmcu/RO"
+DARTMONKEY_IMAGE_PATH = os.path.join(
+    TEST_ASSETS_BUCKET, "dartmonkey_v2.0.2887-311310808.bin"
+)
+NOCTURNE_FP_IMAGE_PATH = os.path.join(
+    TEST_ASSETS_BUCKET, "nocturne_fp_v2.2.64-58cf5974e.bin"
+)
+NAMI_FP_IMAGE_PATH = os.path.join(
+    TEST_ASSETS_BUCKET, "nami_fp_v2.2.144-7a08e07eb.bin"
+)
+BLOONCHIPPER_V4277_IMAGE_PATH = os.path.join(
+    TEST_ASSETS_BUCKET, "bloonchipper_v2.0.4277-9f652bb3.bin"
+)
+BLOONCHIPPER_V5938_IMAGE_PATH = os.path.join(
+    TEST_ASSETS_BUCKET, "bloonchipper_v2.0.5938-197506c1.bin"
+)
 
 
 class ImageType(Enum):
     """EC Image type to use for the test."""
+
     RO = 1
     RW = 2
 
 
+class ApplicationType(Enum):
+    """
+    Select the application type to use (test or production)
+    """
+
+    TEST = 1
+    PRODUCTION = 2
+
+
+@dataclass
 class BoardConfig:
     """Board-specific configuration."""
-    def __init__(self, test_list, servo_uart_name, servo_power_enable):
-        self.test_list = test_list
-        self.servo_uart_name = servo_uart_name
-        self.servo_power_enable = servo_power_enable
+
+    name: str
+    servo_uart_name: str
+    servo_power_enable: str
+    rollback_region0_regex: object
+    rollback_region1_regex: object
+    mpu_regex: object
+    variants: Dict
 
 
+@dataclass
 class TestConfig:
     """Configuration for a given test."""
 
-    def __init__(self, name, image_to_use=ImageType.RW, finish_regexes=None,
-                 toggle_power=False, test_args=None, num_flash_attempts=2,
-                 timeout_secs=10, enable_hw_write_protect=False):
-        if test_args is None:
-            test_args = []
-        if finish_regexes is None:
-            finish_regexes = [ALL_TESTS_PASSED_REGEX, ALL_TESTS_FAILED_REGEX]
-
-        self.name = name
-        self.image_to_use = image_to_use
-        self.finish_regexes = finish_regexes
-        self.test_args = test_args
-        self.toggle_power = toggle_power
-        self.num_flash_attempts = num_flash_attempts
-        self.timeout_secs = timeout_secs
-        self.enable_hw_write_protect = enable_hw_write_protect
-        self.logs = []
-        self.passed = False
-        self.num_fails = 0
-        self.num_passes = 0
+    # pylint: disable=too-many-instance-attributes
+    test_name: str
+    imagetype_to_use: ImageType = ImageType.RW
+    apptype_to_use: ApplicationType = ApplicationType.TEST
+    finish_regexes: List = None
+    fail_regexes: List = None
+    toggle_power: bool = False
+    test_args: List[str] = field(default_factory=list)
+    num_flash_attempts: int = 2
+    timeout_secs: int = 10
+    enable_hw_write_protect: bool = False
+    ro_image: str = None
+    build_board: str = None
+    config_name: str = None
+    exclude_boards: List = field(default_factory=list)
+    logs: List = field(init=False, default_factory=list)
+    passed: bool = field(init=False, default=False)
+    num_passes: int = field(init=False, default=0)
+    num_fails: int = field(init=False, default=0)
+
+    def __post_init__(self):
+        if self.finish_regexes is None:
+            self.finish_regexes = [
+                ALL_TESTS_PASSED_REGEX,
+                ALL_TESTS_FAILED_REGEX,
+            ]
+        if self.fail_regexes is None:
+            self.fail_regexes = [
+                SINGLE_CHECK_FAILED_REGEX,
+                ALL_TESTS_FAILED_REGEX,
+                ASSERTION_FAILURE_REGEX,
+            ]
+        if self.config_name is None:
+            self.config_name = self.test_name
 
 
 # All possible tests.
-ALL_TESTS = {
-    'aes':
-        TestConfig(name='aes'),
-    'crc32':
-        TestConfig(name='crc32'),
-    'flash_physical':
-        TestConfig(name='flash_physical', image_to_use=ImageType.RO,
-                   toggle_power=True),
-    'flash_write_protect':
-        TestConfig(name='flash_write_protect', image_to_use=ImageType.RO,
-                   toggle_power=True, enable_hw_write_protect=True),
-    'mpu_ro':
-        TestConfig(name='mpu',
-                   image_to_use=ImageType.RO,
-                   finish_regexes=[DATA_ACCESS_VIOLATION_20000000_REGEX]),
-    'mpu_rw':
-        TestConfig(name='mpu',
-                   finish_regexes=[DATA_ACCESS_VIOLATION_20000000_REGEX]),
-    'mutex':
-        TestConfig(name='mutex'),
-    'pingpong':
-        TestConfig(name='pingpong'),
-    'rollback_region0':
-        TestConfig(name='rollback', finish_regexes=[
-            DATA_ACCESS_VIOLATION_8020000_REGEX],
-                   test_args=['region0']),
-    'rollback_region1':
-        TestConfig(name='rollback', finish_regexes=[
-            DATA_ACCESS_VIOLATION_8040000_REGEX],
-                   test_args=['region1']),
-    'rollback_entropy':
-        TestConfig(name='rollback_entropy', image_to_use=ImageType.RO),
-    'rtc':
-        TestConfig(name='rtc'),
-    'sha256':
-        TestConfig(name='sha256'),
-    'sha256_unrolled':
-        TestConfig(name='sha256_unrolled'),
-    'stm32f_rtc':
-        TestConfig(name='stm32f_rtc'),
-    'utils':
-        TestConfig(name='utils', timeout_secs=20),
-}
+class AllTests:
+    """All possible tests."""
+
+    @staticmethod
+    def get(board_config: BoardConfig, with_private: str) -> List[TestConfig]:
+        """Return public and private test configs for the specified board."""
+        public_tests = (
+            []
+            if with_private == PRIVATE_ONLY
+            else AllTests.get_public_tests(board_config)
+        )
+        private_tests = (
+            [] if with_private == PRIVATE_NO else AllTests.get_private_tests()
+        )
+
+        all_tests = public_tests + private_tests
+        board_tests = list(
+            filter(
+                lambda e: (board_config.name not in e.exclude_boards), all_tests
+            )
+        )
+        return board_tests
+
+    @staticmethod
+    def get_public_tests(board_config: BoardConfig) -> List[TestConfig]:
+        """Return public test configs for the specified board."""
+        tests = [
+            TestConfig(
+                test_name="production_app_test",
+                finish_regexes=[RW_IMAGE_BOOTED_REGEX],
+                imagetype_to_use=ImageType.RW,
+                apptype_to_use=ApplicationType.PRODUCTION,
+            ),
+            TestConfig(test_name="abort"),
+            TestConfig(test_name="aes"),
+            TestConfig(test_name="always_memset"),
+            TestConfig(test_name="benchmark"),
+            TestConfig(test_name="boringssl_crypto"),
+            TestConfig(test_name="cortexm_fpu"),
+            TestConfig(test_name="crc"),
+            TestConfig(test_name="exception"),
+            TestConfig(
+                test_name="flash_physical",
+                imagetype_to_use=ImageType.RO,
+                toggle_power=True,
+            ),
+            TestConfig(
+                test_name="flash_write_protect",
+                imagetype_to_use=ImageType.RO,
+                toggle_power=True,
+                enable_hw_write_protect=True,
+            ),
+            # TODO(b/274162810): Re-enable test on bloonchipper when LTO is re-enabled.
+            TestConfig(
+                test_name="fpsensor_auth_crypto_stateful",
+                exclude_boards=[BLOONCHIPPER],
+            ),
+            TestConfig(test_name="fpsensor_auth_crypto_stateless"),
+            TestConfig(test_name="fpsensor_hw"),
+            TestConfig(
+                config_name="fpsensor_spi_ro",
+                test_name="fpsensor",
+                imagetype_to_use=ImageType.RO,
+                test_args=["spi"],
+            ),
+            TestConfig(
+                config_name="fpsensor_spi_rw",
+                test_name="fpsensor",
+                test_args=["spi"],
+            ),
+            TestConfig(
+                config_name="fpsensor_uart_ro",
+                test_name="fpsensor",
+                imagetype_to_use=ImageType.RO,
+                test_args=["uart"],
+            ),
+            TestConfig(
+                config_name="fpsensor_uart_rw",
+                test_name="fpsensor",
+                test_args=["uart"],
+            ),
+            TestConfig(test_name="ftrapv"),
+            TestConfig(
+                test_name="libc_printf",
+                finish_regexes=[PRINTF_CALLED_REGEX],
+            ),
+            TestConfig(test_name="global_initialization"),
+            TestConfig(test_name="libcxx"),
+            TestConfig(test_name="malloc", imagetype_to_use=ImageType.RO),
+            TestConfig(
+                config_name="mpu_ro",
+                test_name="mpu",
+                imagetype_to_use=ImageType.RO,
+                finish_regexes=[board_config.mpu_regex],
+            ),
+            TestConfig(
+                config_name="mpu_rw",
+                test_name="mpu",
+                finish_regexes=[board_config.mpu_regex],
+            ),
+            TestConfig(test_name="mutex"),
+            TestConfig(test_name="panic"),
+            TestConfig(test_name="pingpong"),
+            TestConfig(test_name="printf"),
+            TestConfig(test_name="queue"),
+            TestConfig(test_name="rng_benchmark"),
+            TestConfig(
+                config_name="rollback_region0",
+                test_name="rollback",
+                finish_regexes=[board_config.rollback_region0_regex],
+                test_args=["region0"],
+            ),
+            TestConfig(
+                config_name="rollback_region1",
+                test_name="rollback",
+                finish_regexes=[board_config.rollback_region1_regex],
+                test_args=["region1"],
+            ),
+            TestConfig(
+                test_name="rollback_entropy", imagetype_to_use=ImageType.RO
+            ),
+            TestConfig(test_name="rtc"),
+            TestConfig(test_name="sbrk", imagetype_to_use=ImageType.RO),
+            TestConfig(test_name="sha256"),
+            TestConfig(test_name="sha256_unrolled"),
+            TestConfig(test_name="static_if"),
+            TestConfig(test_name="stdlib"),
+            TestConfig(test_name="std_vector"),
+            TestConfig(test_name="stm32f_rtc", exclude_boards=[DARTMONKEY]),
+            TestConfig(
+                config_name="system_is_locked_wp_on",
+                test_name="system_is_locked",
+                test_args=["wp_on"],
+                toggle_power=True,
+                enable_hw_write_protect=True,
+            ),
+            TestConfig(
+                config_name="system_is_locked_wp_off",
+                test_name="system_is_locked",
+                test_args=["wp_off"],
+                toggle_power=True,
+                enable_hw_write_protect=False,
+            ),
+            TestConfig(test_name="timer"),
+            TestConfig(test_name="timer_dos"),
+            TestConfig(test_name="tpm_seed_clear"),
+            TestConfig(test_name="utils", timeout_secs=20),
+            TestConfig(test_name="utils_str"),
+        ]
+
+        # Run panic data tests for all boards and RO versions.
+        for variant_name, variant_info in board_config.variants.items():
+            tests.append(
+                TestConfig(
+                    config_name="panic_data_" + variant_name,
+                    test_name="panic_data",
+                    fail_regexes=[
+                        SINGLE_CHECK_FAILED_REGEX,
+                        ALL_TESTS_FAILED_REGEX,
+                    ],
+                    ro_image=variant_info.get("ro_image_path"),
+                    build_board=variant_info.get("build_board"),
+                )
+            )
+
+        return tests
+
+    @staticmethod
+    def get_private_tests() -> List[TestConfig]:
+        """Return private test configs for the specified board, if available."""
+        tests = []
+        try:
+            current_dir = os.path.dirname(__file__)
+            private_dir = os.path.join(current_dir, os.pardir, "private/test")
+            have_private = os.path.isdir(private_dir)
+            if not have_private:
+                return []
+            sys.path.append(private_dir)
+            import private_tests  # pylint: disable=import-error,import-outside-toplevel
+
+            for test_args in private_tests.tests:
+                tests.append(TestConfig(**test_args))
+        # Catch all exceptions to avoid disruptions in public repo
+        except BaseException as exception:  # pylint: disable=broad-except
+            logging.debug(
+                "Failed to get list of private tests: %s", str(exception)
+            )
+            logging.debug("Ignore error and continue.")
+            return []
+        return tests
+
 
 BLOONCHIPPER_CONFIG = BoardConfig(
-    test_list=ALL_TESTS.values(),
-    servo_uart_name='raw_fpmcu_uart_pty',
-    servo_power_enable='spi1_vref'
+    name=BLOONCHIPPER,
+    servo_uart_name="raw_fpmcu_console_uart_pty",
+    servo_power_enable="fpmcu_pp3300",
+    rollback_region0_regex=DATA_ACCESS_VIOLATION_8020000_REGEX,
+    rollback_region1_regex=DATA_ACCESS_VIOLATION_8040000_REGEX,
+    mpu_regex=DATA_ACCESS_VIOLATION_20000000_REGEX,
+    variants={
+        "bloonchipper_v2.0.4277": {
+            "ro_image_path": BLOONCHIPPER_V4277_IMAGE_PATH
+        },
+        "bloonchipper_v2.0.5938": {
+            "ro_image_path": BLOONCHIPPER_V5938_IMAGE_PATH
+        },
+    },
+)
+
+DARTMONKEY_CONFIG = BoardConfig(
+    name=DARTMONKEY,
+    servo_uart_name="raw_fpmcu_console_uart_pty",
+    servo_power_enable="fpmcu_pp3300",
+    rollback_region0_regex=DATA_ACCESS_VIOLATION_80C0000_REGEX,
+    rollback_region1_regex=DATA_ACCESS_VIOLATION_80E0000_REGEX,
+    mpu_regex=DATA_ACCESS_VIOLATION_24000000_REGEX,
+    # For dartmonkey board, run panic data test also on nocturne_fp and
+    # nami_fp boards with appropriate RO image.
+    variants={
+        "dartmonkey_v2.0.2887": {"ro_image_path": DARTMONKEY_IMAGE_PATH},
+        "nocturne_fp_v2.2.64": {
+            "ro_image_path": NOCTURNE_FP_IMAGE_PATH,
+            "build_board": "nocturne_fp",
+        },
+        "nami_fp_v2.2.144": {
+            "ro_image_path": NAMI_FP_IMAGE_PATH,
+            "build_board": "nami_fp",
+        },
+    },
+)
+
+HELIPILOT_CONFIG = BoardConfig(
+    name=HELIPILOT,
+    servo_uart_name="raw_fpmcu_console_uart_pty",
+    servo_power_enable="fpmcu_pp3300",
+    # TODO(b/286537264): Double check these values and ensure rollback tests pass
+    rollback_region0_regex=DATA_ACCESS_VIOLATION_64020000_REGEX,
+    rollback_region1_regex=DATA_ACCESS_VIOLATION_64040000_REGEX,
+    mpu_regex=DATA_ACCESS_VIOLATION_20000000_REGEX,
+    variants={},
 )
-DARTMONKEY_CONFIG = BLOONCHIPPER_CONFIG
 
 BOARD_CONFIGS = {
-    'bloonchipper': BLOONCHIPPER_CONFIG,
-    'dartmonkey': DARTMONKEY_CONFIG,
+    "bloonchipper": BLOONCHIPPER_CONFIG,
+    "dartmonkey": DARTMONKEY_CONFIG,
+    "helipilot": HELIPILOT_CONFIG,
 }
 
 
-def get_console(board_name: str, board_config: BoardConfig) -> Optional[str]:
+def read_file_gsutil(path: str) -> bytes:
+    """Get data from bucket, using gsutil tool"""
+    cmd = ["gsutil", "cat", path]
+
+    logging.debug('Running command: "%s"', " ".join(cmd))
+    gsutil = subprocess.run(cmd, stdout=subprocess.PIPE, check=False)
+    gsutil.check_returncode()
+
+    return gsutil.stdout
+
+
+def find_section_offset_size(section: str, image: bytes) -> Tuple[int, int]:
+    """Get offset and size of the section in image"""
+    areas = fmap.fmap_decode(image)["areas"]
+    area = next(area for area in areas if area["name"] == section)
+    return area["offset"], area["size"]
+
+
+def read_section(src: bytes, section: str) -> bytes:
+    """Read FMAP section content into byte array"""
+    (src_start, src_size) = find_section_offset_size(section, src)
+    src_end = src_start + src_size
+    return src[src_start:src_end]
+
+
+def write_section(data: bytes, image: bytearray, section: str):
+    """Replace the specified section in image with the contents of data"""
+    (section_start, section_size) = find_section_offset_size(section, image)
+
+    if section_size < len(data):
+        raise ValueError(section + " section size is not enough to store data")
+
+    section_end = section_start + section_size
+    filling = bytes([0xFF for _ in range(section_size - len(data))])
+
+    image[section_start:section_end] = data + filling
+
+
+def copy_section(src: bytes, dst: bytearray, section: str):
+    """Copy section from src image to dst image"""
+    (src_start, src_size) = find_section_offset_size(section, src)
+    (dst_start, dst_size) = find_section_offset_size(section, dst)
+
+    if dst_size < src_size:
+        raise ValueError(
+            "Section " + section + " from source image has "
+            "greater size than the section in destination image"
+        )
+
+    src_end = src_start + src_size
+    dst_end = dst_start + dst_size
+    filling = bytes([0xFF for _ in range(dst_size - src_size)])
+
+    dst[dst_start:dst_end] = src[src_start:src_end] + filling
+
+
+def replace_ro(image: bytearray, ro_section: bytes):
+    """Replace RO in image with provided one"""
+    # Backup RO public key since its private part was used to sign RW.
+    ro_pubkey = read_section(image, "KEY_RO")
+
+    # Copy RO part of the firmware to the image. Please note that RO public key
+    # is copied too since EC_RO area includes KEY_RO area.
+    copy_section(ro_section, image, "EC_RO")
+
+    # Restore RO public key.
+    write_section(ro_pubkey, image, "KEY_RO")
+
+
+def get_console(board_config: BoardConfig) -> Optional[str]:
     """Get the name of the console for a given board."""
     cmd = [
-        'dut-control',
-        '-n', board_name,
+        "dut-control",
         board_config.servo_uart_name,
     ]
-    logging.debug('Running command: "%s"', ' '.join(cmd))
+    logging.debug('Running command: "%s"', " ".join(cmd))
 
     with subprocess.Popen(cmd, stdout=subprocess.PIPE) as proc:
         for line in io.TextIOWrapper(proc.stdout):  # type: ignore[arg-type]
             logging.debug(line)
-            pty = line.split(':')
+            pty = line.split(":")
             if len(pty) == 2 and pty[0] == board_config.servo_uart_name:
                 return pty[1].strip()
 
     return None
 
 
-def power(board_name: str, board_config: BoardConfig, on: bool) -> None:
+def power(board_config: BoardConfig, power_on: bool) -> None:
     """Turn power to board on/off."""
-    if on:
-        state = 'pp3300'
+    if power_on:
+        state = "pp3300"
     else:
-        state = 'off'
+        state = "off"
 
     cmd = [
-        'dut-control',
-        '-n', board_name,
-        board_config.servo_power_enable + ':' + state,
+        "dut-control",
+        board_config.servo_power_enable + ":" + state,
     ]
-    logging.debug('Running command: "%s"', ' '.join(cmd))
-    subprocess.run(cmd).check_returncode()
+    logging.debug('Running command: "%s"', " ".join(cmd))
+    subprocess.run(cmd, check=False).check_returncode()
+
+
+def power_cycle(board_config: BoardConfig) -> None:
+    """power_cycle the boards."""
+    logging.debug("power_cycling board")
+    power(board_config, power_on=False)
+    time.sleep(1)
+    power(board_config, power_on=True)
 
 
-def hw_write_protect(board_name: str, enable: bool) -> None:
+def hw_write_protect(enable: bool) -> None:
     """Enable/disable hardware write protect."""
     if enable:
-        state = 'on'
+        state = "force_on"
     else:
-        state = 'off'
+        state = "force_off"
 
     cmd = [
-        'dut-control',
-        '-n', board_name,
-        'fw_wp_en' + ':' + state,
-        ]
-    logging.debug('Running command: "%s"', ' '.join(cmd))
-    subprocess.run(cmd).check_returncode()
+        "dut-control",
+        "fw_wp_state:" + state,
+    ]
+    logging.debug('Running command: "%s"', " ".join(cmd))
+    subprocess.run(cmd, check=False).check_returncode()
 
 
-def build(test_name: str, board_name: str) -> None:
+def build(
+    test_name: str, board_name: str, compiler: str, app_type: ApplicationType
+) -> None:
     """Build specified test for specified board."""
-    cmd = [
-        'make',
-        'BOARD=' + board_name,
-        'test-' + test_name,
-        '-j',
+    cmd = ["make"]
+
+    if compiler == CLANG:
+        cmd = cmd + ["CC=arm-none-eabi-clang"]
+
+    cmd = cmd + [
+        "BOARD=" + board_name,
+        "-j",
     ]
 
-    logging.debug('Running command: "%s"', ' '.join(cmd))
-    subprocess.run(cmd).check_returncode()
+    # If the image type is a test image, then apply test- prefix to the target name
+    if app_type == ApplicationType.TEST:
+        cmd = cmd + [
+            "test-" + test_name,
+        ]
+
+    logging.debug('Running command: "%s"', " ".join(cmd))
+    subprocess.run(cmd, check=False).check_returncode()
 
 
-def flash(test_name: str, board: str) -> bool:
+def flash(
+    image_path: str, board: str, flasher: str, remote_ip: str, remote_port: int
+) -> bool:
     """Flash specified test to specified board."""
     logging.info("Flashing test")
 
-    # TODO(b/151105339): Support ./util/flash_ec as well. It's slower, but only
-    # requires servo micro.
-    cmd = [
-        FLASH_SCRIPT,
-        '--board', board,
-        '--image', os.path.join(EC_DIR, 'build', board, test_name,
-                                test_name + '.bin'),
-    ]
-    logging.debug('Running command: "%s"', ' '.join(cmd))
-    completed_process = subprocess.run(cmd)
+    cmd = []
+    if flasher == JTRACE:
+        cmd.append(JTRACE_FLASH_SCRIPT)
+        if remote_ip:
+            cmd.extend(["--remote", remote_ip + ":" + str(remote_port)])
+    elif flasher == SERVO_MICRO:
+        cmd.append(SERVO_MICRO_FLASH_SCRIPT)
+    else:
+        logging.error('Unknown flasher: "%s"', flasher)
+        return False
+    cmd.extend(
+        [
+            "--board",
+            board,
+            "--image",
+            image_path,
+        ]
+    )
+    logging.debug('Running command: "%s"', " ".join(cmd))
+    completed_process = subprocess.run(cmd, check=False)
     return completed_process.returncode == 0
 
 
-def readline(executor: ThreadPoolExecutor, f: BinaryIO, timeout_secs: int) -> \
-             Optional[bytes]:
+def patch_image(test: TestConfig, image_path: str):
+    """Replace RO part of the firmware with provided one."""
+    with open(image_path, "rb+") as image_file:
+        image = bytearray(image_file.read())
+        ro_section = read_file_gsutil(test.ro_image)
+        replace_ro(image, ro_section)
+        image_file.seek(0)
+        image_file.write(image)
+        image_file.truncate()
+
+
+def readline(
+    executor: ThreadPoolExecutor, file: BinaryIO, timeout_secs: int
+) -> Optional[bytes]:
     """Read a line with timeout."""
-    a = executor.submit(f.readline)
+    future = executor.submit(file.readline)
     try:
-        return a.result(timeout_secs)
+        return future.result(timeout_secs)
     except concurrent.futures.TimeoutError:
         return None
 
 
-def readlines_until_timeout(executor, f: BinaryIO, timeout_secs: int) -> \
-                            List[bytes]:
+def readlines_until_timeout(
+    executor, file: BinaryIO, timeout_secs: int
+) -> List[bytes]:
     """Continuously read lines for timeout_secs."""
     lines: List[bytes] = []
     while True:
-        line = readline(executor, f, timeout_secs)
+        line = readline(executor, file, timeout_secs)
         if not line:
             return lines
         lines.append(line)
 
 
-def run_test(test: TestConfig, console: str, executor: ThreadPoolExecutor) ->\
-             bool:
+def process_console_output_line(line: bytes, test: TestConfig):
+    """Parse console output line and update test pass/fail counters."""
+    try:
+        line_str = line.decode()
+
+        if SINGLE_CHECK_PASSED_REGEX.match(line_str):
+            test.num_passes += 1
+
+        for regex in test.fail_regexes:
+            if regex.match(line_str):
+                test.num_fails += 1
+                break
+
+        return line_str
+    except UnicodeDecodeError:
+        # Sometimes we get non-unicode from the console (e.g., when the
+        # board reboots.) Not much we can do in this case, so we'll just
+        # ignore it.
+        return None
+
+
+def run_test(
+    test: TestConfig, console: io.FileIO, executor: ThreadPoolExecutor
+) -> bool:
     """Run specified test."""
     start = time.time()
-    with open(console, "wb+", buffering=0) as c:
-        # Wait for boot to finish
+
+    # Wait for boot to finish
+    time.sleep(1)
+    console.write("\n".encode())
+    if test.imagetype_to_use == ImageType.RO:
+        console.write("reboot ro\n".encode())
         time.sleep(1)
-        c.write('\n'.encode())
-        if test.image_to_use == ImageType.RO:
-            c.write('reboot ro\n'.encode())
-            time.sleep(1)
-
-        test_cmd = 'runtest ' + ' '.join(test.test_args) + '\n'
-        c.write(test_cmd.encode())
-
-        while True:
-            c.flush()
-            line = readline(executor, c, 1)
-            if not line:
-                now = time.time()
-                if now - start > test.timeout_secs:
-                    logging.debug("Test timed out")
-                    return False
-                continue
 
-            logging.debug(line)
-            test.logs.append(line)
-            # Look for test_print_result() output (success or failure)
-            try:
-                line_str = line.decode()
+    # Skip runtest if using standard app type
+    if test.apptype_to_use != ApplicationType.PRODUCTION:
+        test_cmd = "runtest " + " ".join(test.test_args) + "\n"
+        console.write(test_cmd.encode())
+
+    while True:
+        console.flush()
+        line = readline(executor, console, 1)
+        if not line:
+            now = time.time()
+            if now - start > test.timeout_secs:
+                logging.debug("Test timed out")
+                return False
+            continue
 
-                if SINGLE_CHECK_PASSED_REGEX.match(line_str):
-                    test.num_passes += 1
+        test.logs.append(line)
+        # Look for test_print_result() output (success or failure)
+        line_str = process_console_output_line(line, test)
+        if line_str is None:
+            # Sometimes we get non-unicode from the console (e.g., when the
+            # board reboots.) Not much we can do in this case, so we'll just
+            # ignore it and print log the line as is.
+            logging.debug(line)
+            continue
 
-                if SINGLE_CHECK_FAILED_REGEX.match(line_str):
-                    test.num_fails += 1
+        logging.debug(line_str.rstrip())
 
-                if ALL_TESTS_FAILED_REGEX.match(line_str):
-                    test.num_fails += 1
+        for finish_re in test.finish_regexes:
+            if finish_re.match(line_str):
+                # flush read the remaining
+                lines = readlines_until_timeout(executor, console, 1)
+                logging.debug(lines)
+                test.logs.append(lines)
 
-                for r in test.finish_regexes:
-                    if r.match(line_str):
-                        # flush read the remaining
-                        lines = readlines_until_timeout(executor, c, 1)
-                        logging.debug(lines)
-                        test.logs.append(lines)
-                        return test.num_fails == 0
+                for line in lines:
+                    process_console_output_line(line, test)
 
-            except UnicodeDecodeError:
-                # Sometimes we get non-unicode from the console (e.g., when the
-                # board reboots.) Not much we can do in this case, so we'll just
-                # ignore it.
-                pass
+                return test.num_fails == 0
 
 
-def get_test_list(config: BoardConfig, test_args) -> List[TestConfig]:
+def get_test_list(
+    config: BoardConfig, test_args, with_private: str
+) -> List[TestConfig]:
     """Get a list of tests to run."""
-    if test_args == 'all':
-        return config.test_list
+    if test_args == "all":
+        return AllTests.get(config, with_private)
 
     test_list = []
-    for t in test_args:
-        logging.debug('test: %s', t)
-        test_config = ALL_TESTS.get(t)
-        if test_config is None:
-            logging.error('Unable to find test config for "%s"', t)
+    for test in test_args:
+        logging.debug("test: %s", test)
+        test_regex = re.compile(test)
+        tests = [
+            test
+            for test in AllTests.get(config, with_private)
+            if test_regex.fullmatch(test.config_name)
+        ]
+        if not tests:
+            logging.error(
+                'Test "%s" is either not configured or not supported on board "%s"',
+                test,
+                config.name,
+            )
             sys.exit(1)
-        test_list.append(test_config)
+        test_list += tests
 
     return test_list
 
 
-def main():
-    parser = argparse.ArgumentParser()
+def flash_and_run_test(
+    test: TestConfig,
+    board_config: BoardConfig,
+    args: argparse.Namespace,
+    executor,
+) -> bool:
+    """Run a single test using the test and board configuration specified"""
+    build_board = args.board
+    # If test provides this information, build image for board specified
+    # by test.
+    if test.build_board is not None:
+        build_board = test.build_board
+
+    # attempt to build test binary, reporting a test failure on error
+    try:
+        build(test.test_name, build_board, args.compiler, test.apptype_to_use)
+    except Exception as exception:  # pylint: disable=broad-except
+        logging.error("failed to build %s: %s", test.test_name, exception)
+        return False
 
-    default_board = 'bloonchipper'
-    parser.add_argument(
-        '--board', '-b',
-        help='Board (default: ' + default_board + ')',
-        default=default_board)
+    if test.apptype_to_use == ApplicationType.PRODUCTION:
+        image_path = os.path.join(EC_DIR, "build", build_board, "ec.bin")
+    else:
+        image_path = os.path.join(
+            EC_DIR,
+            "build",
+            build_board,
+            test.test_name,
+            test.test_name + ".bin",
+        )
+    logging.debug("image_path: %s", image_path)
+
+    if test.ro_image is not None:
+        try:
+            patch_image(test, image_path)
+        except Exception as exception:  # pylint: disable=broad-except
+            logging.warning(
+                "An exception occurred while patching image: %s", exception
+            )
+            return False
+
+    # flash test binary
+    # TODO(b/158327221): First attempt to flash fails after
+    #  flash_write_protect test is run; works after second attempt.
+    flash_succeeded = False
+    for i in range(0, test.num_flash_attempts):
+        logging.debug("Flash attempt %d", i + 1)
+        if flash(
+            image_path, args.board, args.flasher, args.remote, args.jlink_port
+        ):
+            flash_succeeded = True
+            break
+        time.sleep(1)
 
-    default_tests = 'all'
-    parser.add_argument(
-        '--tests', '-t',
-        nargs='+',
-        help='Tests (default: ' + default_tests + ')',
-        default=default_tests)
+    if not flash_succeeded:
+        logging.debug(
+            "Flashing failed after max attempts: %d", test.num_flash_attempts
+        )
+        return False
 
-    log_level_choices = ['DEBUG', 'INFO', 'WARNING', 'ERROR', 'CRITICAL']
-    parser.add_argument(
-        '--log_level', '-l',
-        choices=log_level_choices,
-        default='DEBUG'
-    )
+    if test.toggle_power:
+        power_cycle(board_config)
 
-    args = parser.parse_args()
-    logging.basicConfig(level=args.log_level)
+    hw_write_protect(test.enable_hw_write_protect)
+
+    # run the test
+    logging.info('Running test: "%s"', test.config_name)
+
+    with ExitStack() as stack:
+        if args.remote and args.console_port:
+            console_socket = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
+            console_socket.connect((args.remote, args.console_port))
+            console = stack.enter_context(
+                console_socket.makefile(mode="rwb", buffering=0)
+            )
+        else:
+            # pylint: disable-next=consider-using-with
+            console_file = open(get_console(board_config), "wb+", buffering=0)
+            console = stack.enter_context(console_file)
+
+        return run_test(test, console, executor=executor)
+
+
+def parse_remote_arg(remote: str) -> str:
+    """Convert the 'remote' input argument to IP address, if available."""
+    if not remote:
+        return ""
+
+    try:
+        ip_addr = socket.gethostbyname(remote)
+        return ip_addr
+    except socket.gaierror:
+        logging.error('Failed to resolve host "%s".', remote)
+        sys.exit(1)
+
+
+def validate_args_combination(args: argparse.Namespace):
+    """Check that the current combination of arguments is supported.
+
+    Not all combinations of command line arguments are valid or currently
+    supported. If tests can't be executed, print and error message and exit.
+    """
+    if args.jlink_port and not args.flasher == JTRACE:
+        logging.error("jlink_port specified, but flasher is not set to J-Link.")
+        sys.exit(1)
+
+    if args.remote and not (args.jlink_port or args.console_port):
+        logging.error(
+            "jlink_port or console_port must be specified when using "
+            "the remote option."
+        )
+        sys.exit(1)
+
+    if (args.jlink_port or args.console_port) and not args.remote:
+        logging.error(
+            "The remote option must be specified when using the "
+            "jlink_port or console_port options."
+        )
+        sys.exit(1)
+
+    if args.remote and args.flasher == SERVO_MICRO:
+        logging.error(
+            "The remote option is not supported when flashing with servo "
+            "micro. Use J-Link instead or flash with a local servo micro."
+        )
+        sys.exit(1)
 
     if args.board not in BOARD_CONFIGS:
         logging.error('Unable to find a config for board: "%s"', args.board)
         sys.exit(1)
 
-    board_config = BOARD_CONFIGS[args.board]
 
-    e = ThreadPoolExecutor(max_workers=1)
+def main():
+    """Run unit tests on device and displays the results."""
+    parser = argparse.ArgumentParser()
 
-    test_list = get_test_list(board_config, args.tests)
-    logging.debug('Running tests: %s', [t.name for t in test_list])
+    default_board = "bloonchipper"
+    parser.add_argument(
+        "--board",
+        "-b",
+        help="Board (default: " + default_board + ")",
+        default=default_board,
+    )
 
-    for test in test_list:
-        # build test binary
-        build(test.name, args.board)
+    default_tests = "all"
+    parser.add_argument(
+        "--tests",
+        "-t",
+        nargs="+",
+        help="Tests (default: " + default_tests + ")",
+        default=default_tests,
+    )
 
-        # flash test binary
-        # TODO(b/158327221): First attempt to flash fails after
-        #  flash_write_protect test is run; works after second attempt.
-        flash_succeeded = False
-        for i in range(0, test.num_flash_attempts):
-            logging.debug('Flash attempt %d', i + 1)
-            if flash(test.name, args.board):
-                flash_succeeded = True
-                break
-            time.sleep(1)
+    log_level_choices = ["DEBUG", "INFO", "WARNING", "ERROR", "CRITICAL"]
+    parser.add_argument(
+        "--log_level", "-l", choices=log_level_choices, default="DEBUG"
+    )
 
-        if not flash_succeeded:
-            logging.debug('Flashing failed after max attempts: %d',
-                          test.num_flash_attempts)
-            test.passed = False
-            continue
+    flasher_choices = [SERVO_MICRO, JTRACE]
+    parser.add_argument(
+        "--flasher", "-f", choices=flasher_choices, default=JTRACE
+    )
 
-        if test.toggle_power:
-            power(args.board, board_config, on=False)
-            time.sleep(1)
-            power(args.board, board_config, on=True)
-
-        hw_write_protect(args.board, test.enable_hw_write_protect)
-
-        # run the test
-        logging.info('Running test: "%s"', test.name)
-        console = get_console(args.board, board_config)
-        test.passed = run_test(test, console, executor=e)
-
-    colorama.init()
-    exit_code = 0
-    for test in test_list:
-        # print results
-        print('Test "' + test.name + '": ', end='')
-        if test.passed:
-            print(colorama.Fore.GREEN + 'PASSED')
-        else:
-            print(colorama.Fore.RED + 'FAILED')
-            exit_code = 1
+    compiler_options = [GCC, CLANG]
+    parser.add_argument(
+        "--compiler", "-c", choices=compiler_options, default=GCC
+    )
 
-        print(colorama.Style.RESET_ALL)
+    # This might be expanded to serve as a "remote" for flash_ec also, so
+    # we will leave it generic.
+    parser.add_argument(
+        "--remote",
+        "-n",
+        help="The remote host connected to one or both of: J-Link and Servo.",
+        type=parse_remote_arg,
+    )
+
+    parser.add_argument(
+        "--jlink_port",
+        "-j",
+        type=int,
+        help="The port to use when connecting to JLink.",
+    )
+    parser.add_argument(
+        "--console_port",
+        "-p",
+        type=int,
+        help="The port connected to the FPMCU console.",
+    )
+
+    with_private_choices = [PRIVATE_YES, PRIVATE_NO, PRIVATE_ONLY]
+    parser.add_argument(
+        "--with_private", choices=with_private_choices, default=PRIVATE_YES
+    )
+
+    args = parser.parse_args()
+    logging.basicConfig(
+        format="%(levelname)s:%(message)s", level=args.log_level
+    )
+    validate_args_combination(args)
+
+    board_config = BOARD_CONFIGS[args.board]
+    test_list = get_test_list(board_config, args.tests, args.with_private)
+    logging.debug("Running tests: %s", [test.config_name for test in test_list])
+
+    with ThreadPoolExecutor(max_workers=1) as executor:
+        for test in test_list:
+            test.passed = flash_and_run_test(test, board_config, args, executor)
+
+        colorama.init()
+        exit_code = 0
+        for test in test_list:
+            # print results
+            print('Test "' + test.config_name + '": ', end="")
+            if test.passed:
+                print(colorama.Fore.GREEN + "PASSED")
+            else:
+                print(colorama.Fore.RED + "FAILED")
+                exit_code = 1
+
+            print(colorama.Style.RESET_ALL)
 
-    e.shutdown(wait=False)
     sys.exit(exit_code)
 
 
-if __name__ == '__main__':
-  sys.exit(main())
+if __name__ == "__main__":
+    sys.exit(main())
diff --git a/test/sbrk.c b/test/sbrk.c
new file mode 100644
index 0000000000..a5cbd2e41b
--- /dev/null
+++ b/test/sbrk.c
@@ -0,0 +1,86 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "link_defs.h"
+#include "shared_mem.h"
+#include "test_util.h"
+
+#include <errno.h>
+
+#include <unistd.h>
+
+test_static int test_sbrk_overflow(void)
+{
+	/* Requesting the maximum possible amount should succeed. */
+	uint8_t *ptr = sbrk(shared_mem_size());
+	TEST_NE(ptr, (void *)-1, "%p");
+
+	/* Requesting any more should fail. */
+	ptr = sbrk(1);
+	TEST_EQ(ptr, (void *)-1, "%p");
+	TEST_EQ(errno, ENOMEM, "%d");
+
+	return EC_SUCCESS;
+}
+
+test_static int test_sbrk_underflow(void)
+{
+	uint8_t *const start = sbrk(0);
+	TEST_EQ(start, (uint8_t *)__shared_mem_buf, "%p");
+
+	/*
+	 * We're already at the start of the shared mem buffer, so requesting
+	 * less should fail.
+	 */
+	uint8_t *ptr = sbrk(-1);
+	TEST_EQ(ptr, (void *)-1, "%p");
+	TEST_EQ(errno, ENOMEM, "%d");
+
+	ptr = sbrk(0);
+	TEST_EQ(ptr, (uint8_t *)__shared_mem_buf, "%p");
+
+	return EC_SUCCESS;
+}
+
+test_static int test_sbrk(void)
+{
+	uint8_t *const start = sbrk(0);
+	if (!IS_ENABLED(BOARD_HOST))
+		TEST_EQ(start, (uint8_t *)__shared_mem_buf, "%p");
+
+	uint8_t *prev = sbrk(100);
+	TEST_EQ(prev, start, "%p");
+
+	uint8_t *cur = sbrk(0);
+	TEST_EQ(cur, prev + 100, "%p");
+
+	prev = sbrk(-100);
+	TEST_EQ(prev, cur, "%p");
+
+	cur = sbrk(0);
+	TEST_EQ(cur, start, "%p");
+
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
+{
+	test_reset();
+
+	RUN_TEST(test_sbrk);
+	if (!IS_ENABLED(BOARD_HOST)) {
+		if (IS_ENABLED(SECTION_IS_RW)) {
+			ccprintf("The following tests only work in RO, since "
+				 "RW performs dynamic memory allocation "
+				 "before the test starts.\n");
+			test_fail();
+			return;
+		}
+		RUN_TEST(test_sbrk_underflow);
+		RUN_TEST(test_sbrk_overflow);
+	}
+
+	test_print_result();
+}
diff --git a/test/sbrk.tasklist b/test/sbrk.tasklist
new file mode 100644
index 0000000000..d1920322a9
--- /dev/null
+++ b/test/sbrk.tasklist
@@ -0,0 +1,9 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST
diff --git a/test/sbs_charging.c b/test/sbs_charging.c
new file mode 100644
index 0000000000..5921b377da
--- /dev/null
+++ b/test/sbs_charging.c
@@ -0,0 +1,1143 @@
+/* Copyright 2014 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Test charge_state behavior
+ */
+
+#include "battery_smart.h"
+#include "charge_state.h"
+#include "chipset.h"
+#include "common.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "math_util.h"
+#include "power.h"
+#include "task.h"
+#include "test_util.h"
+#include "util.h"
+
+#define WAIT_CHARGER_TASK 600
+#define BATTERY_DETACH_DELAY 35000
+
+enum ec_charge_control_mode get_chg_ctrl_mode(void);
+
+test_static int mock_chipset_state = CHIPSET_STATE_ON;
+test_static int is_shutdown;
+test_static int is_force_discharge;
+test_static int is_hibernated;
+test_static int override_voltage, override_current, override_usec;
+test_static int display_soc;
+test_static int is_full;
+
+/* The simulation doesn't really hibernate, so we must reset this ourselves */
+extern timestamp_t shutdown_target_time;
+bool battery_sustainer_enabled(void);
+
+test_static void reset_mocks(void)
+{
+	mock_chipset_state = CHIPSET_STATE_ON;
+	is_shutdown = is_force_discharge = is_hibernated = 0;
+	override_voltage = override_current = override_usec = 0;
+	shutdown_target_time.val = 0ULL;
+	is_full = 0;
+}
+
+int board_cut_off_battery(void)
+{
+	return EC_SUCCESS;
+}
+
+void chipset_force_shutdown(enum chipset_shutdown_reason reason)
+{
+	is_shutdown = 1;
+	mock_chipset_state = CHIPSET_STATE_HARD_OFF;
+}
+
+int chipset_in_state(int state_mask)
+{
+	return state_mask & mock_chipset_state;
+}
+
+int chipset_in_or_transitioning_to_state(int state_mask)
+{
+	return state_mask & mock_chipset_state;
+}
+
+enum power_state power_get_state(void)
+{
+	if (is_shutdown)
+		return POWER_S5;
+	else if (is_hibernated)
+		return POWER_G3;
+	else
+		return POWER_S0;
+}
+
+int board_discharge_on_ac(int enabled)
+{
+	is_force_discharge = enabled;
+	return EC_SUCCESS;
+}
+
+void system_hibernate(int sec, int usec)
+{
+	is_hibernated = 1;
+}
+
+int charger_profile_override(struct charge_state_data *curr)
+{
+	if (override_voltage)
+		curr->requested_voltage = override_voltage;
+	if (override_current)
+		curr->requested_current = override_current;
+
+	if (override_usec)
+		return override_usec;
+
+	/* Don't let it sleep a whole minute when the AP is off */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return CHARGE_POLL_PERIOD_LONG;
+
+	return 0;
+}
+
+test_static uint32_t meh;
+enum ec_status charger_profile_override_get_param(uint32_t param,
+						  uint32_t *value)
+{
+	if (param == CS_PARAM_CUSTOM_PROFILE_MIN) {
+		*value = meh;
+		return EC_RES_SUCCESS;
+	}
+	return EC_RES_INVALID_PARAM;
+}
+enum ec_status charger_profile_override_set_param(uint32_t param,
+						  uint32_t value)
+{
+	if (param == CS_PARAM_CUSTOM_PROFILE_MIN) {
+		meh = value;
+		return EC_RES_SUCCESS;
+	}
+	return EC_RES_INVALID_PARAM;
+}
+
+test_static int wait_charging_state(void)
+{
+	enum led_pwr_state state;
+	task_wake(TASK_ID_CHARGER);
+	msleep(WAIT_CHARGER_TASK);
+	state = led_pwr_get_state();
+	ccprintf("[CHARGING TEST] state = %d\n", state);
+	return state;
+}
+
+test_static int charge_control(enum ec_charge_control_mode mode)
+{
+	struct ec_params_charge_control p;
+
+	p.cmd = EC_CHARGE_CONTROL_CMD_SET;
+	p.mode = mode;
+	p.sustain_soc.lower = -1;
+	p.sustain_soc.upper = -1;
+	return test_send_host_command(EC_CMD_CHARGE_CONTROL, 2, &p, sizeof(p),
+				      NULL, 0);
+}
+
+__override int charge_get_display_charge(void)
+{
+	return display_soc;
+}
+
+__override int calc_is_full(void)
+{
+	return is_full;
+}
+
+/* Setup init condition */
+test_static void test_setup(int on_ac)
+{
+	const struct battery_info *bat_info = battery_get_info();
+
+	reset_mocks();
+
+	/* 50% of charge */
+	sb_write(SB_RELATIVE_STATE_OF_CHARGE, 50);
+	sb_write(SB_ABSOLUTE_STATE_OF_CHARGE, 50);
+	/* full charge capacity in mAh */
+	sb_write(SB_FULL_CHARGE_CAPACITY, 0xf000);
+	/* 25 degree Celsius */
+	sb_write(SB_TEMPERATURE, CELSIUS_TO_DECI_KELVIN(25));
+	/* battery pack voltage */
+	sb_write(SB_VOLTAGE, bat_info->voltage_normal);
+	/* desired charging voltage/current */
+	sb_write(SB_CHARGING_VOLTAGE, bat_info->voltage_max);
+	sb_write(SB_CHARGING_CURRENT, 4000);
+
+	/* battery pack current is positive when charging */
+	if (on_ac) {
+		sb_write(SB_CURRENT, 1000);
+		gpio_set_level(GPIO_AC_PRESENT, 1);
+	} else {
+		sb_write(SB_CURRENT, -100);
+		gpio_set_level(GPIO_AC_PRESENT, 0);
+	}
+
+	/* Reset the charger state to initial state */
+	charge_control(CHARGE_CONTROL_NORMAL);
+
+	/* Let things stabilize */
+	wait_charging_state();
+}
+
+/* Host Event helpers */
+test_static int ev_is_set(int event)
+{
+	return host_get_events() & EC_HOST_EVENT_MASK(event);
+}
+test_static int ev_is_clear(int event)
+{
+	return !ev_is_set(event);
+}
+test_static void ev_clear(int event)
+{
+	host_clear_events(EC_HOST_EVENT_MASK(event));
+}
+
+test_static int test_charge_state(void)
+{
+	enum led_pwr_state state;
+	uint32_t flags;
+
+	/* On AC */
+	test_setup(1);
+
+	ccprintf("[CHARGING TEST] AC on\n");
+
+	/* Detach battery, charging error */
+	ccprintf("[CHARGING TEST] Detach battery\n");
+	TEST_ASSERT(test_detach_i2c(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS) ==
+		    EC_SUCCESS);
+	msleep(BATTERY_DETACH_DELAY);
+	state = wait_charging_state();
+	TEST_ASSERT(state == LED_PWRS_ERROR);
+
+	/* Attach battery again, charging */
+	ccprintf("[CHARGING TEST] Attach battery\n");
+	test_attach_i2c(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS);
+	/* And changing full capacity should trigger a host event */
+	ev_clear(EC_HOST_EVENT_BATTERY);
+	sb_write(SB_FULL_CHARGE_CAPACITY, 0xeff0);
+	state = wait_charging_state();
+	TEST_ASSERT(state == LED_PWRS_CHARGE);
+	TEST_ASSERT(ev_is_set(EC_HOST_EVENT_BATTERY));
+
+	/* Unplug AC, discharging at 1000mAh */
+	ccprintf("[CHARGING TEST] AC off\n");
+	gpio_set_level(GPIO_AC_PRESENT, 0);
+	sb_write(SB_CURRENT, -1000);
+	state = wait_charging_state();
+	TEST_ASSERT(state == LED_PWRS_DISCHARGE);
+	flags = charge_get_flags();
+	TEST_ASSERT(!(flags & CHARGE_FLAG_EXTERNAL_POWER));
+	TEST_ASSERT(!(flags & CHARGE_FLAG_FORCE_IDLE));
+
+	/* Discharging waaaay overtemp is ignored */
+	ccprintf("[CHARGING TEST] AC off, batt temp = 0xffff\n");
+	gpio_set_level(GPIO_AC_PRESENT, 0);
+	sb_write(SB_CURRENT, -1000);
+	state = wait_charging_state();
+	TEST_ASSERT(state == LED_PWRS_DISCHARGE);
+	sb_write(SB_TEMPERATURE, 0xffff);
+	state = wait_charging_state();
+	TEST_ASSERT(!is_shutdown);
+	TEST_ASSERT(state == LED_PWRS_DISCHARGE);
+	sb_write(SB_TEMPERATURE, CELSIUS_TO_DECI_KELVIN(40));
+
+	/* Discharging overtemp */
+	ccprintf("[CHARGING TEST] AC off, batt temp = 90 C\n");
+	gpio_set_level(GPIO_AC_PRESENT, 0);
+	sb_write(SB_CURRENT, -1000);
+
+	state = wait_charging_state();
+	TEST_ASSERT(state == LED_PWRS_DISCHARGE);
+	sb_write(SB_TEMPERATURE, CELSIUS_TO_DECI_KELVIN(90));
+	state = wait_charging_state();
+	sleep(CONFIG_BATTERY_CRITICAL_SHUTDOWN_TIMEOUT);
+	TEST_ASSERT(is_shutdown);
+	TEST_ASSERT(state == LED_PWRS_DISCHARGE);
+	sb_write(SB_TEMPERATURE, CELSIUS_TO_DECI_KELVIN(40));
+
+	/* Force idle */
+	ccprintf("[CHARGING TEST] AC on, force idle\n");
+	gpio_set_level(GPIO_AC_PRESENT, 1);
+	sb_write(SB_CURRENT, 1000);
+	state = wait_charging_state();
+	TEST_ASSERT(state == LED_PWRS_CHARGE);
+	flags = charge_get_flags();
+	TEST_ASSERT(flags & CHARGE_FLAG_EXTERNAL_POWER);
+	TEST_ASSERT(!(flags & CHARGE_FLAG_FORCE_IDLE));
+	charge_control(CHARGE_CONTROL_IDLE);
+	state = wait_charging_state();
+	TEST_ASSERT(state == LED_PWRS_FORCED_IDLE);
+	flags = charge_get_flags();
+	TEST_ASSERT(flags & CHARGE_FLAG_EXTERNAL_POWER);
+	TEST_ASSERT(flags & CHARGE_FLAG_FORCE_IDLE);
+	charge_control(CHARGE_CONTROL_NORMAL);
+	state = wait_charging_state();
+	TEST_ASSERT(state == LED_PWRS_CHARGE);
+
+	/* Force discharge */
+	ccprintf("[CHARGING TEST] AC on, force discharge\n");
+	gpio_set_level(GPIO_AC_PRESENT, 1);
+	sb_write(SB_CURRENT, 1000);
+	charge_control(CHARGE_CONTROL_DISCHARGE);
+	state = wait_charging_state();
+	TEST_ASSERT(state == LED_PWRS_FORCED_IDLE);
+	TEST_ASSERT(is_force_discharge);
+	charge_control(CHARGE_CONTROL_NORMAL);
+	state = wait_charging_state();
+	TEST_ASSERT(state == LED_PWRS_CHARGE);
+	TEST_ASSERT(!is_force_discharge);
+
+	return EC_SUCCESS;
+}
+
+test_static int test_low_battery(void)
+{
+	test_setup(1);
+
+	ccprintf("[CHARGING TEST] Low battery with AC and positive current\n");
+	sb_write(SB_RELATIVE_STATE_OF_CHARGE, 2);
+	sb_write(SB_CURRENT, 1000);
+	wait_charging_state();
+	mock_chipset_state = CHIPSET_STATE_SOFT_OFF;
+	hook_notify(HOOK_CHIPSET_SHUTDOWN);
+	TEST_ASSERT(!is_hibernated);
+
+	ccprintf("[CHARGING TEST] Low battery with AC and negative current\n");
+	sb_write(SB_CURRENT, -1000);
+	wait_charging_state();
+	sleep(CONFIG_BATTERY_CRITICAL_SHUTDOWN_TIMEOUT);
+	TEST_ASSERT(is_hibernated);
+
+	ccprintf("[CHARGING TEST] Low battery shutdown S0->S5\n");
+	mock_chipset_state = CHIPSET_STATE_ON;
+	hook_notify(HOOK_CHIPSET_PRE_INIT);
+	hook_notify(HOOK_CHIPSET_STARTUP);
+	gpio_set_level(GPIO_AC_PRESENT, 0);
+	is_hibernated = 0;
+	sb_write(SB_CURRENT, -1000);
+	sb_write(SB_RELATIVE_STATE_OF_CHARGE, 2);
+	wait_charging_state();
+	mock_chipset_state = CHIPSET_STATE_SOFT_OFF;
+	hook_notify(HOOK_CHIPSET_SHUTDOWN);
+	wait_charging_state();
+	/* after a while, the EC should hibernate */
+	sleep(CONFIG_BATTERY_CRITICAL_SHUTDOWN_TIMEOUT);
+	TEST_ASSERT(is_hibernated);
+
+	ccprintf("[CHARGING TEST] Low battery shutdown S5\n");
+	is_hibernated = 0;
+	sb_write(SB_RELATIVE_STATE_OF_CHARGE, 10);
+	wait_charging_state();
+	sb_write(SB_RELATIVE_STATE_OF_CHARGE, 2);
+	wait_charging_state();
+	/* after a while, the EC should hibernate */
+	sleep(CONFIG_BATTERY_CRITICAL_SHUTDOWN_TIMEOUT);
+	TEST_ASSERT(is_hibernated);
+
+	ccprintf("[CHARGING TEST] Low battery AP shutdown\n");
+	is_shutdown = 0;
+	mock_chipset_state = CHIPSET_STATE_ON;
+	sb_write(SB_RELATIVE_STATE_OF_CHARGE, 10);
+	gpio_set_level(GPIO_AC_PRESENT, 1);
+	sb_write(SB_CURRENT, 1000);
+	wait_charging_state();
+	gpio_set_level(GPIO_AC_PRESENT, 0);
+	sb_write(SB_CURRENT, -1000);
+	sb_write(SB_RELATIVE_STATE_OF_CHARGE, 2);
+	wait_charging_state();
+	usleep(32 * SECOND);
+	wait_charging_state();
+	TEST_ASSERT(is_shutdown);
+
+	return EC_SUCCESS;
+}
+
+test_static int test_deep_charge_battery(void)
+{
+	enum charge_state state;
+	const struct battery_info *bat_info = battery_get_info();
+
+	test_setup(1);
+
+	/* battery pack voltage bellow voltage_min */
+	sb_write(SB_VOLTAGE, (bat_info->voltage_min - 200));
+	wait_charging_state();
+	state = charge_get_state();
+	TEST_ASSERT(state == ST_PRECHARGE);
+
+	/*
+	 * Battery voltage keep bellow voltage_min,
+	 * precharge over time CONFIG_BATTERY_LOW_VOLTAGE_TIMEOUT
+	 */
+	usleep(CONFIG_BATTERY_LOW_VOLTAGE_TIMEOUT);
+	state = charge_get_state();
+	TEST_ASSERT(state == ST_IDLE);
+
+	/* recovery from a low voltage. */
+	sb_write(SB_VOLTAGE, (bat_info->voltage_normal));
+	wait_charging_state();
+	state = charge_get_state();
+	TEST_ASSERT(state == ST_CHARGE);
+
+	return EC_SUCCESS;
+}
+test_static int test_high_temp_battery(void)
+{
+	test_setup(1);
+
+	ccprintf("[CHARGING TEST] High battery temperature shutdown\n");
+	ev_clear(EC_HOST_EVENT_BATTERY_SHUTDOWN);
+	sb_write(SB_TEMPERATURE, CELSIUS_TO_DECI_KELVIN(90));
+	wait_charging_state();
+	TEST_ASSERT(ev_is_set(EC_HOST_EVENT_BATTERY_SHUTDOWN));
+	TEST_ASSERT(!is_shutdown);
+	sleep(CONFIG_BATTERY_CRITICAL_SHUTDOWN_TIMEOUT);
+	TEST_ASSERT(is_shutdown);
+
+	ccprintf("[CHARGING TEST] High battery temp S0->S5 hibernate\n");
+	mock_chipset_state = CHIPSET_STATE_SOFT_OFF;
+	wait_charging_state();
+	TEST_ASSERT(is_hibernated);
+
+	return EC_SUCCESS;
+}
+
+test_static int test_cold_battery_with_ac(void)
+{
+	test_setup(1);
+
+	ccprintf("[CHARGING TEST] Cold battery no shutdown with AC\n");
+	ev_clear(EC_HOST_EVENT_BATTERY_SHUTDOWN);
+	sb_write(SB_TEMPERATURE, CELSIUS_TO_DECI_KELVIN(-90));
+	wait_charging_state();
+	sleep(CONFIG_BATTERY_CRITICAL_SHUTDOWN_TIMEOUT);
+	TEST_ASSERT(!is_shutdown);
+
+	return EC_SUCCESS;
+}
+
+test_static int test_cold_battery_no_ac(void)
+{
+	test_setup(0);
+
+	ccprintf("[CHARGING TEST] Cold battery shutdown when discharging\n");
+	ev_clear(EC_HOST_EVENT_BATTERY_SHUTDOWN);
+	sb_write(SB_TEMPERATURE, CELSIUS_TO_DECI_KELVIN(-90));
+	wait_charging_state();
+	TEST_ASSERT(ev_is_set(EC_HOST_EVENT_BATTERY_SHUTDOWN));
+	TEST_ASSERT(!is_shutdown);
+	sleep(CONFIG_BATTERY_CRITICAL_SHUTDOWN_TIMEOUT);
+	TEST_ASSERT(is_shutdown);
+
+	return EC_SUCCESS;
+}
+
+test_static int test_external_funcs(void)
+{
+	int rv, temp;
+	uint32_t flags;
+	int state;
+
+	/* Connect the AC */
+	test_setup(1);
+
+	flags = charge_get_flags();
+	TEST_ASSERT(flags & CHARGE_FLAG_EXTERNAL_POWER);
+	TEST_ASSERT(!(flags & CHARGE_FLAG_FORCE_IDLE));
+
+	/* Invalid or do-nothing commands first */
+	UART_INJECT("chg\n");
+	state = wait_charging_state();
+	TEST_ASSERT(state == LED_PWRS_CHARGE);
+	flags = charge_get_flags();
+	TEST_ASSERT(flags & CHARGE_FLAG_EXTERNAL_POWER);
+	TEST_ASSERT(!(flags & CHARGE_FLAG_FORCE_IDLE));
+
+	UART_INJECT("chg blahblah\n");
+	state = wait_charging_state();
+	TEST_ASSERT(state == LED_PWRS_CHARGE);
+	flags = charge_get_flags();
+	TEST_ASSERT(flags & CHARGE_FLAG_EXTERNAL_POWER);
+	TEST_ASSERT(!(flags & CHARGE_FLAG_FORCE_IDLE));
+
+	UART_INJECT("chg idle\n");
+	state = wait_charging_state();
+	TEST_ASSERT(state == LED_PWRS_CHARGE);
+	flags = charge_get_flags();
+	TEST_ASSERT(flags & CHARGE_FLAG_EXTERNAL_POWER);
+	TEST_ASSERT(!(flags & CHARGE_FLAG_FORCE_IDLE));
+
+	UART_INJECT("chg idle blargh\n");
+	state = wait_charging_state();
+	TEST_ASSERT(state == LED_PWRS_CHARGE);
+	flags = charge_get_flags();
+	TEST_ASSERT(flags & CHARGE_FLAG_EXTERNAL_POWER);
+	TEST_ASSERT(!(flags & CHARGE_FLAG_FORCE_IDLE));
+
+	/* Now let's force idle on and off */
+	UART_INJECT("chg idle on\n");
+	state = wait_charging_state();
+	TEST_ASSERT(state == LED_PWRS_FORCED_IDLE);
+	flags = charge_get_flags();
+	TEST_ASSERT(flags & CHARGE_FLAG_EXTERNAL_POWER);
+	TEST_ASSERT(flags & CHARGE_FLAG_FORCE_IDLE);
+
+	UART_INJECT("chg idle off\n");
+	wait_charging_state();
+	state = wait_charging_state();
+	TEST_ASSERT(state == LED_PWRS_CHARGE);
+	flags = charge_get_flags();
+	TEST_ASSERT(flags & CHARGE_FLAG_EXTERNAL_POWER);
+	TEST_ASSERT(!(flags & CHARGE_FLAG_FORCE_IDLE));
+
+	/* and the rest */
+	TEST_ASSERT(led_pwr_get_state() == LED_PWRS_CHARGE);
+	TEST_ASSERT(!charge_want_shutdown());
+	TEST_ASSERT(charge_get_percent() == 50);
+	temp = 0;
+	rv = charge_get_battery_temp(0, &temp);
+	TEST_ASSERT(rv == EC_SUCCESS);
+	TEST_ASSERT(K_TO_C(temp) == 25);
+
+	return EC_SUCCESS;
+}
+
+#define CHG_OPT1 0x2000
+#define CHG_OPT2 0x4000
+test_static int test_hc_charge_state(void)
+{
+	enum led_pwr_state state;
+	int i, rv, tmp;
+	struct ec_params_charge_state params;
+	struct ec_response_charge_state resp;
+
+	/* Let's connect the AC again. */
+	test_setup(1);
+
+	/* Initialize the charger options with some nonzero value */
+	TEST_ASSERT(charger_set_option(CHG_OPT1) == EC_SUCCESS);
+
+	/* Get the state */
+	memset(&resp, 0, sizeof(resp));
+	params.cmd = CHARGE_STATE_CMD_GET_STATE;
+	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, &params,
+				    sizeof(params), &resp, sizeof(resp));
+	TEST_ASSERT(rv == EC_RES_SUCCESS);
+	TEST_ASSERT(resp.get_state.ac);
+	TEST_ASSERT(resp.get_state.chg_voltage);
+	TEST_ASSERT(resp.get_state.chg_current);
+	TEST_ASSERT(resp.get_state.chg_input_current);
+	TEST_ASSERT(resp.get_state.batt_state_of_charge);
+
+	/* Check all the params */
+	for (i = 0; i < CS_NUM_BASE_PARAMS; i++) {
+		/* Read it */
+		memset(&resp, 0, sizeof(resp));
+		params.cmd = CHARGE_STATE_CMD_GET_PARAM;
+		params.get_param.param = i;
+		rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, &params,
+					    sizeof(params), &resp,
+					    sizeof(resp));
+		TEST_ASSERT(rv == EC_RES_SUCCESS);
+		if (i != CS_PARAM_LIMIT_POWER)
+			TEST_ASSERT(resp.get_param.value);
+		else
+			TEST_ASSERT(!resp.get_param.value);
+
+		/* Bump it up a bit */
+		tmp = resp.get_param.value;
+		switch (i) {
+		case CS_PARAM_CHG_VOLTAGE:
+		case CS_PARAM_CHG_CURRENT:
+		case CS_PARAM_CHG_INPUT_CURRENT:
+			tmp -= 128; /* Should be valid delta */
+			break;
+		case CS_PARAM_CHG_STATUS:
+		case CS_PARAM_LIMIT_POWER:
+			/* These ones can't be set */
+			break;
+		case CS_PARAM_CHG_OPTION:
+			tmp = CHG_OPT2;
+			break;
+		}
+		params.cmd = CHARGE_STATE_CMD_SET_PARAM;
+		params.set_param.param = i;
+		params.set_param.value = tmp;
+		rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, &params,
+					    sizeof(params), &resp,
+					    sizeof(resp));
+		if (i == CS_PARAM_CHG_STATUS || i == CS_PARAM_LIMIT_POWER)
+			TEST_ASSERT(rv == EC_RES_ACCESS_DENIED);
+		else
+			TEST_ASSERT(rv == EC_RES_SUCCESS);
+		/* Allow the change to take effect */
+		state = wait_charging_state();
+		TEST_ASSERT(state == LED_PWRS_CHARGE);
+
+		/* Read it back again*/
+		memset(&resp, 0, sizeof(resp));
+		params.cmd = CHARGE_STATE_CMD_GET_PARAM;
+		params.get_param.param = i;
+		rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, &params,
+					    sizeof(params), &resp,
+					    sizeof(resp));
+		TEST_ASSERT(rv == EC_RES_SUCCESS);
+		TEST_ASSERT(resp.get_param.value == tmp);
+	}
+
+	/* And a custom profile param */
+	meh = 0xdeadbeef;
+	memset(&resp, 0, sizeof(resp));
+	params.cmd = CHARGE_STATE_CMD_GET_PARAM;
+	params.get_param.param = CS_PARAM_CUSTOM_PROFILE_MIN;
+	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, &params,
+				    sizeof(params), &resp, sizeof(resp));
+	TEST_ASSERT(rv == EC_RES_SUCCESS);
+	TEST_ASSERT(resp.get_param.value == meh);
+	params.cmd = CHARGE_STATE_CMD_SET_PARAM;
+	params.set_param.param = CS_PARAM_CUSTOM_PROFILE_MIN;
+	params.set_param.value = 0xc0def00d;
+	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, &params,
+				    sizeof(params), &resp, sizeof(resp));
+	TEST_ASSERT(rv == EC_RES_SUCCESS);
+	/* Allow the change to take effect */
+	state = wait_charging_state();
+	TEST_ASSERT(meh == params.set_param.value);
+
+	/* param out of range */
+	params.cmd = CHARGE_STATE_CMD_GET_PARAM;
+	params.get_param.param = CS_NUM_BASE_PARAMS;
+	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, &params,
+				    sizeof(params), &resp, sizeof(resp));
+	TEST_ASSERT(rv == EC_RES_INVALID_PARAM);
+	params.cmd = CHARGE_STATE_CMD_SET_PARAM;
+	params.set_param.param = CS_NUM_BASE_PARAMS;
+	params.set_param.value = 0x1000; /* random value */
+	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, &params,
+				    sizeof(params), &resp, sizeof(resp));
+	TEST_ASSERT(rv == EC_RES_INVALID_PARAM);
+
+	/* command out of range */
+	params.cmd = CHARGE_STATE_NUM_CMDS;
+	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, &params,
+				    sizeof(params), &resp, sizeof(resp));
+	TEST_ASSERT(rv == EC_RES_INVALID_PARAM);
+
+	/*
+	 * We've screwed with the charger settings, so let the state machine
+	 * reset itself before we stop.
+	 */
+	test_setup(0);
+	test_setup(1);
+
+	return EC_SUCCESS;
+}
+
+test_static int test_hc_current_limit(void)
+{
+	int rv, norm_current, lower_current;
+	struct ec_params_charge_state cs_params;
+	struct ec_response_charge_state cs_resp;
+	struct ec_params_current_limit cl_params;
+
+	/* On AC */
+	test_setup(1);
+
+	/* See what current the charger is delivering */
+	cs_params.cmd = CHARGE_STATE_CMD_GET_STATE;
+	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, &cs_params,
+				    sizeof(cs_params), &cs_resp,
+				    sizeof(cs_resp));
+	TEST_ASSERT(rv == EC_RES_SUCCESS);
+	norm_current = cs_resp.get_state.chg_current;
+
+	/* Lower it a bit */
+	lower_current = norm_current - 256;
+	cl_params.limit = lower_current;
+	rv = test_send_host_command(EC_CMD_CHARGE_CURRENT_LIMIT, 0, &cl_params,
+				    sizeof(cl_params), 0, 0);
+	TEST_ASSERT(rv == EC_RES_SUCCESS);
+	wait_charging_state();
+
+	/* See that it's changed */
+	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, &cs_params,
+				    sizeof(cs_params), &cs_resp,
+				    sizeof(cs_resp));
+	TEST_ASSERT(rv == EC_RES_SUCCESS);
+	TEST_ASSERT(lower_current == cs_resp.get_state.chg_current);
+
+	/* Remove the limit */
+	cl_params.limit = -1U;
+	rv = test_send_host_command(EC_CMD_CHARGE_CURRENT_LIMIT, 0, &cl_params,
+				    sizeof(cl_params), 0, 0);
+	TEST_ASSERT(rv == EC_RES_SUCCESS);
+	wait_charging_state();
+
+	/* See that it's back */
+	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, &cs_params,
+				    sizeof(cs_params), &cs_resp,
+				    sizeof(cs_resp));
+	TEST_ASSERT(rv == EC_RES_SUCCESS);
+	TEST_ASSERT(norm_current == cs_resp.get_state.chg_current);
+
+	return EC_SUCCESS;
+}
+
+test_static int test_hc_current_limit_v1(void)
+{
+	int rv, norm_current, lower_current, current;
+	struct ec_params_current_limit_v1 params;
+
+	/* On AC */
+	test_setup(1);
+	display_soc = 700;
+	wait_charging_state();
+
+	/* See what current the charger is delivering */
+	rv = charger_get_current(0, &norm_current);
+	TEST_ASSERT(rv == EC_RES_SUCCESS);
+
+	/* Lower it a bit */
+	lower_current = norm_current - 256;
+	params.limit = lower_current;
+	params.battery_soc = 80;
+	rv = test_send_host_command(EC_CMD_CHARGE_CURRENT_LIMIT, 1, &params,
+				    sizeof(params), 0, 0);
+	TEST_ASSERT(rv == EC_RES_SUCCESS);
+	wait_charging_state();
+
+	/* Check current limit is not applied. */
+	rv = charger_get_current(0, &current);
+	TEST_ASSERT(rv == EC_RES_SUCCESS);
+	TEST_ASSERT(norm_current == current);
+
+	/* Increase the soc above the slow charge trigger point. */
+	display_soc = 900;
+	wait_charging_state();
+
+	/* Check current limit is applied. */
+	rv = charger_get_current(0, &current);
+	TEST_ASSERT(rv == EC_RES_SUCCESS);
+	TEST_ASSERT(current == lower_current);
+
+	/* Remove the limit */
+	params.limit = -1U;
+	params.battery_soc = 0;
+	rv = test_send_host_command(EC_CMD_CHARGE_CURRENT_LIMIT, 1, &params,
+				    sizeof(params), 0, 0);
+	TEST_ASSERT(rv == EC_RES_SUCCESS);
+	wait_charging_state();
+
+	/* Check current limit is removed. */
+	rv = charger_get_current(0, &current);
+	TEST_ASSERT(rv == EC_RES_SUCCESS);
+	TEST_ASSERT(norm_current == current);
+
+	/* Test invalid value. */
+	params.battery_soc = 101;
+	rv = test_send_host_command(EC_CMD_CHARGE_CURRENT_LIMIT, 1, &params,
+				    sizeof(params), 0, 0);
+	TEST_ASSERT(rv = EC_RES_INVALID_PARAM);
+
+	return EC_SUCCESS;
+}
+
+test_static int test_low_battery_hostevents(void)
+{
+	int state;
+
+	test_setup(0);
+
+	ccprintf("[CHARGING TEST] Low battery host events\n");
+
+	/* You know you make me wanna */
+	sb_write(SB_RELATIVE_STATE_OF_CHARGE, BATTERY_LEVEL_LOW + 1);
+	ev_clear(EC_HOST_EVENT_BATTERY_LOW);
+	ev_clear(EC_HOST_EVENT_BATTERY_CRITICAL);
+	ev_clear(EC_HOST_EVENT_BATTERY_SHUTDOWN);
+	state = wait_charging_state();
+	TEST_ASSERT(state == LED_PWRS_DISCHARGE);
+	TEST_ASSERT(ev_is_clear(EC_HOST_EVENT_BATTERY_LOW));
+	TEST_ASSERT(ev_is_clear(EC_HOST_EVENT_BATTERY_CRITICAL));
+	TEST_ASSERT(ev_is_clear(EC_HOST_EVENT_BATTERY_SHUTDOWN));
+
+	/* (Shout) a little bit louder now */
+	sb_write(SB_RELATIVE_STATE_OF_CHARGE, BATTERY_LEVEL_LOW - 1);
+	state = wait_charging_state();
+	TEST_ASSERT(state == LED_PWRS_DISCHARGE);
+	TEST_ASSERT(ev_is_set(EC_HOST_EVENT_BATTERY_LOW));
+	TEST_ASSERT(ev_is_clear(EC_HOST_EVENT_BATTERY_CRITICAL));
+	TEST_ASSERT(ev_is_clear(EC_HOST_EVENT_BATTERY_SHUTDOWN));
+	TEST_ASSERT(!is_shutdown);
+
+	/* (Shout) a little bit louder now */
+	sb_write(SB_RELATIVE_STATE_OF_CHARGE,
+		 CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE + 1);
+	state = wait_charging_state();
+	TEST_ASSERT(state == LED_PWRS_DISCHARGE);
+	TEST_ASSERT(ev_is_set(EC_HOST_EVENT_BATTERY_LOW));
+	TEST_ASSERT(ev_is_clear(EC_HOST_EVENT_BATTERY_CRITICAL));
+	TEST_ASSERT(ev_is_clear(EC_HOST_EVENT_BATTERY_SHUTDOWN));
+	TEST_ASSERT(!is_shutdown);
+
+	/* (Shout) a little bit louder now */
+	sb_write(SB_RELATIVE_STATE_OF_CHARGE,
+		 CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE - 1);
+	state = wait_charging_state();
+	TEST_ASSERT(state == LED_PWRS_DISCHARGE);
+	TEST_ASSERT(ev_is_set(EC_HOST_EVENT_BATTERY_LOW));
+	TEST_ASSERT(ev_is_set(EC_HOST_EVENT_BATTERY_CRITICAL));
+	TEST_ASSERT(ev_is_clear(EC_HOST_EVENT_BATTERY_SHUTDOWN));
+	TEST_ASSERT(!is_shutdown);
+
+	/* (Shout) a little bit louder now */
+	sb_write(SB_RELATIVE_STATE_OF_CHARGE, BATTERY_LEVEL_SHUTDOWN + 1);
+	state = wait_charging_state();
+	TEST_ASSERT(state == LED_PWRS_DISCHARGE);
+	TEST_ASSERT(ev_is_set(EC_HOST_EVENT_BATTERY_LOW));
+	TEST_ASSERT(ev_is_set(EC_HOST_EVENT_BATTERY_CRITICAL));
+	TEST_ASSERT(ev_is_clear(EC_HOST_EVENT_BATTERY_SHUTDOWN));
+	TEST_ASSERT(!is_shutdown);
+
+	/* (Shout) a little bit louder now */
+	sb_write(SB_RELATIVE_STATE_OF_CHARGE, BATTERY_LEVEL_SHUTDOWN - 1);
+	state = wait_charging_state();
+	TEST_ASSERT(state == LED_PWRS_DISCHARGE);
+	TEST_ASSERT(ev_is_set(EC_HOST_EVENT_BATTERY_LOW));
+	TEST_ASSERT(ev_is_set(EC_HOST_EVENT_BATTERY_CRITICAL));
+	/* hey-hey-HEY-hey. Doesn't immediately shut down */
+	TEST_ASSERT(ev_is_set(EC_HOST_EVENT_BATTERY_SHUTDOWN));
+	TEST_ASSERT(!is_shutdown);
+	/* after a while, the AP should shut down */
+	sleep(CONFIG_BATTERY_CRITICAL_SHUTDOWN_TIMEOUT);
+	TEST_ASSERT(is_shutdown);
+
+	return EC_SUCCESS;
+}
+
+test_static int battery_sustainer_set(int version, int8_t lower, int8_t upper,
+				      enum ec_charge_control_flag flags)
+{
+	struct ec_params_charge_control p;
+
+	p.cmd = EC_CHARGE_CONTROL_CMD_SET;
+	p.mode = CHARGE_CONTROL_NORMAL;
+	p.sustain_soc.lower = lower;
+	p.sustain_soc.upper = upper;
+	p.flags = flags;
+	return test_send_host_command(EC_CMD_CHARGE_CONTROL, version, &p,
+				      sizeof(p), NULL, 0);
+}
+
+test_static int battery_sustainer_get(int version,
+				      struct ec_response_charge_control *r)
+{
+	struct ec_params_charge_control p;
+
+	p.cmd = EC_CHARGE_CONTROL_CMD_GET;
+	return test_send_host_command(EC_CMD_CHARGE_CONTROL, version, &p,
+				      sizeof(p), r, sizeof(*r));
+}
+
+test_static int test_hc_charge_control_v2(void)
+{
+	struct ec_response_charge_control r;
+	int rv;
+
+	test_setup(1);
+
+	ccprintf("Test v2 command\n");
+	rv = battery_sustainer_set(2, 79, 80, 0);
+	TEST_ASSERT(rv == EC_RES_SUCCESS);
+	rv = battery_sustainer_get(2, &r);
+	TEST_ASSERT(r.sustain_soc.lower == 79);
+	TEST_ASSERT(r.sustain_soc.upper == 80);
+	TEST_ASSERT(r.flags == 0);
+
+	ccprintf("Test v2 lower > upper\n");
+	rv = battery_sustainer_set(2, 80, 79, 0);
+	TEST_ASSERT(rv == EC_RES_INVALID_PARAM);
+
+	ccprintf("Test v2 lower < 0\n");
+	rv = battery_sustainer_set(2, -100, 80, 0);
+	TEST_ASSERT(rv == EC_RES_INVALID_PARAM);
+
+	ccprintf("Test v2 100 < upper\n");
+	rv = battery_sustainer_set(2, -100, 80, 0);
+	TEST_ASSERT(rv == EC_RES_INVALID_PARAM);
+
+	return EC_SUCCESS;
+}
+
+test_static int test_hc_charge_control_v3(void)
+{
+	struct ec_params_charge_control p;
+	struct ec_response_charge_control r;
+	int rv;
+
+	test_setup(1);
+
+	ccprintf("Test v3 command\n");
+	rv = battery_sustainer_set(3, 79, 80, 0);
+	TEST_ASSERT(rv == EC_RES_SUCCESS);
+	rv = battery_sustainer_get(3, &r);
+	TEST_ASSERT(r.sustain_soc.lower == 79);
+	TEST_ASSERT(r.sustain_soc.upper == 80);
+	TEST_ASSERT(r.flags == 0);
+
+	ccprintf("Test v3 command with flags\n");
+	rv = battery_sustainer_set(3, 79, 80, EC_CHARGE_CONTROL_FLAG_NO_IDLE);
+	TEST_ASSERT(rv == EC_RES_SUCCESS);
+	rv = battery_sustainer_get(3, &r);
+	TEST_ASSERT(r.sustain_soc.lower == 79);
+	TEST_ASSERT(r.sustain_soc.upper == 80);
+	TEST_ASSERT(r.flags == EC_CHARGE_CONTROL_FLAG_NO_IDLE);
+
+	ccprintf("Test v3 lower > upper\n");
+	rv = battery_sustainer_set(3, 80, 79, 0);
+	TEST_ASSERT(rv == EC_RES_INVALID_PARAM);
+
+	ccprintf("Test v3 lower < 0\n");
+	rv = battery_sustainer_set(3, -100, 80, 0);
+	TEST_ASSERT(rv == EC_RES_INVALID_PARAM);
+
+	ccprintf("Test v3 100 < upper\n");
+	rv = battery_sustainer_set(3, 79, 101, 0);
+	TEST_ASSERT(rv == EC_RES_INVALID_PARAM);
+
+	/* Test illegal command */
+	p.cmd = UINT8_MAX;
+	rv = test_send_host_command(EC_CMD_CHARGE_CONTROL, 3, &p, sizeof(p), &r,
+				    sizeof(r));
+	TEST_ASSERT(rv == EC_RES_INVALID_PARAM);
+
+	/* Test illegal control mode */
+	p.cmd = EC_CHARGE_CONTROL_CMD_SET;
+	p.mode = CHARGE_CONTROL_COUNT;
+	rv = test_send_host_command(EC_CMD_CHARGE_CONTROL, 3, &p, sizeof(p), &r,
+				    sizeof(r));
+	TEST_ASSERT(rv == EC_RES_ERROR);
+
+	return EC_SUCCESS;
+}
+
+test_static int run_battery_sustainer_no_idle(int version)
+{
+	const enum ec_charge_control_flag flags =
+		version > 2 ? EC_CHARGE_CONTROL_FLAG_NO_IDLE : 0;
+	int rv;
+
+	test_setup(1);
+
+	/* Enable sustainer */
+	rv = battery_sustainer_set(version, 79, 80, flags);
+	TEST_ASSERT(rv == EC_RES_SUCCESS);
+
+	/* Check mode transition as the SoC changes. */
+
+	ccprintf("Test SoC < lower < upper.\n");
+	display_soc = 780;
+	wait_charging_state();
+	TEST_ASSERT(get_chg_ctrl_mode() == CHARGE_CONTROL_NORMAL);
+	ccprintf("Pass.\n");
+
+	ccprintf("Test lower < upper < SoC.\n");
+	display_soc = 810;
+	wait_charging_state();
+	TEST_ASSERT(get_chg_ctrl_mode() == CHARGE_CONTROL_DISCHARGE);
+	ccprintf("Pass.\n");
+
+	ccprintf("Test unplug AC.\n");
+	gpio_set_level(GPIO_AC_PRESENT, 0);
+	wait_charging_state();
+	TEST_ASSERT(get_chg_ctrl_mode() == CHARGE_CONTROL_NORMAL);
+	ccprintf("Pass.\n");
+
+	ccprintf("Test replug AC.\n");
+	gpio_set_level(GPIO_AC_PRESENT, 1);
+	wait_charging_state();
+	TEST_ASSERT(get_chg_ctrl_mode() == CHARGE_CONTROL_DISCHARGE);
+	ccprintf("Pass.\n");
+
+	ccprintf("Test lower < SoC < upper.\n");
+	display_soc = 799;
+	wait_charging_state();
+	TEST_ASSERT(get_chg_ctrl_mode() == CHARGE_CONTROL_DISCHARGE);
+	ccprintf("Pass.\n");
+
+	ccprintf("Test SoC < lower < upper.\n");
+	display_soc = 789;
+	wait_charging_state();
+	TEST_ASSERT(get_chg_ctrl_mode() == CHARGE_CONTROL_NORMAL);
+	ccprintf("Pass.\n");
+
+	ccprintf("Test disable sustainer.\n");
+	charge_control(CHARGE_CONTROL_NORMAL);
+	display_soc = 810;
+	wait_charging_state();
+	TEST_ASSERT(get_chg_ctrl_mode() == CHARGE_CONTROL_NORMAL);
+	ccprintf("Pass.\n");
+
+	ccprintf("Test enable sustainer when battery is full.\n");
+	display_soc = 1000;
+	is_full = 1;
+	wait_charging_state();
+	/* Enable sustainer. */
+	rv = battery_sustainer_set(version, 79, 80, flags);
+	TEST_ASSERT(rv == EC_RES_SUCCESS);
+	wait_charging_state();
+	TEST_ASSERT(get_chg_ctrl_mode() == CHARGE_CONTROL_DISCHARGE);
+	ccprintf("Pass.\n");
+
+	/* Disable sustainer, unplug AC, upper < SoC < 100. */
+	charge_control(CHARGE_CONTROL_NORMAL);
+	display_soc = 810;
+	is_full = 0;
+	gpio_set_level(GPIO_AC_PRESENT, 0);
+	wait_charging_state();
+
+	ccprintf("Test enable sustainer when AC is present.\n");
+	gpio_set_level(GPIO_AC_PRESENT, 1);
+	wait_charging_state();
+	/* Enable sustainer. */
+	rv = battery_sustainer_set(version, 79, 80, flags);
+	TEST_ASSERT(rv == EC_RES_SUCCESS);
+	wait_charging_state();
+	TEST_ASSERT(get_chg_ctrl_mode() == CHARGE_CONTROL_DISCHARGE);
+	ccprintf("Pass.\n");
+
+	return EC_SUCCESS;
+}
+
+test_static int test_battery_sustainer_without_idle(void)
+{
+	ccprintf("Test v2 without idle\n");
+	run_battery_sustainer_no_idle(2);
+
+	ccprintf("Test v3 without idle\n");
+	run_battery_sustainer_no_idle(3);
+
+	return EC_SUCCESS;
+}
+
+test_static int run_battery_sustainer_with_idle(int version)
+{
+	int rv;
+
+	test_setup(1);
+
+	/* Enable sustainer */
+	if (version > 2)
+		rv = battery_sustainer_set(version, 79, 80, 0);
+	else
+		/* V2 needs lower == upper to enable IDLE. */
+		rv = battery_sustainer_set(version, 80, 80, 0);
+	TEST_ASSERT(rv == EC_RES_SUCCESS);
+	TEST_ASSERT(battery_sustainer_enabled());
+
+	/* Check mode transition as the SoC changes. */
+
+	/* SoC < lower (= upper) */
+	display_soc = 780;
+	wait_charging_state();
+	TEST_ASSERT(get_chg_ctrl_mode() == CHARGE_CONTROL_NORMAL);
+
+	/* (lower =) upper < SoC */
+	display_soc = 810;
+	wait_charging_state();
+	TEST_ASSERT(get_chg_ctrl_mode() == CHARGE_CONTROL_DISCHARGE);
+
+	/* Full */
+	display_soc = 1000;
+	wait_charging_state();
+	TEST_ASSERT(get_chg_ctrl_mode() == CHARGE_CONTROL_DISCHARGE);
+	TEST_ASSERT(battery_sustainer_enabled());
+
+	/* Unplug AC. Sustainer gets deactivated. */
+	gpio_set_level(GPIO_AC_PRESENT, 0);
+	wait_charging_state();
+	TEST_ASSERT(get_chg_ctrl_mode() == CHARGE_CONTROL_NORMAL);
+
+	/* Replug AC. Sustainer gets re-activated. */
+	gpio_set_level(GPIO_AC_PRESENT, 1);
+	wait_charging_state();
+	TEST_ASSERT(get_chg_ctrl_mode() == CHARGE_CONTROL_DISCHARGE);
+
+	/* lower = SoC = upper */
+	display_soc = 800;
+	wait_charging_state();
+	TEST_ASSERT(get_chg_ctrl_mode() == CHARGE_CONTROL_IDLE);
+
+	/* Emulate restarting with upper smaller than the previous. */
+	display_soc = 810;
+	wait_charging_state();
+	TEST_ASSERT(get_chg_ctrl_mode() == CHARGE_CONTROL_DISCHARGE);
+
+	/* SoC < lower (= upper) */
+	display_soc = 789;
+	wait_charging_state();
+	TEST_ASSERT(get_chg_ctrl_mode() == CHARGE_CONTROL_NORMAL);
+
+	/* Re-enable sustainer when it's already running */
+	rv = battery_sustainer_set(version, 89, 90, 0);
+	TEST_ASSERT(rv == EC_RES_SUCCESS);
+	TEST_ASSERT(battery_sustainer_enabled());
+
+	/* Disable sustainer */
+	rv = battery_sustainer_set(version, -1, -1, 0);
+	TEST_ASSERT(rv == EC_RES_SUCCESS);
+	TEST_ASSERT(!battery_sustainer_enabled());
+
+	/* This time, mode will stay in NORMAL even when upper < SoC. */
+	display_soc = 810;
+	wait_charging_state();
+	TEST_ASSERT(get_chg_ctrl_mode() == CHARGE_CONTROL_NORMAL);
+
+	return EC_SUCCESS;
+}
+
+test_static int test_battery_sustainer_with_idle(void)
+{
+	ccprintf("Test v2 with idle\n");
+	run_battery_sustainer_with_idle(2);
+
+	ccprintf("Test v3 with idle\n");
+	run_battery_sustainer_with_idle(3);
+
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
+{
+	RUN_TEST(test_charge_state);
+	RUN_TEST(test_low_battery);
+	RUN_TEST(test_high_temp_battery);
+	RUN_TEST(test_cold_battery_with_ac);
+	RUN_TEST(test_cold_battery_no_ac);
+	RUN_TEST(test_external_funcs);
+	RUN_TEST(test_hc_charge_state);
+	RUN_TEST(test_hc_current_limit);
+	RUN_TEST(test_hc_current_limit_v1);
+	RUN_TEST(test_hc_charge_control_v2);
+	RUN_TEST(test_hc_charge_control_v3);
+	RUN_TEST(test_low_battery_hostevents);
+	RUN_TEST(test_battery_sustainer_without_idle);
+	RUN_TEST(test_battery_sustainer_with_idle);
+	RUN_TEST(test_deep_charge_battery);
+
+	test_print_result();
+}
diff --git a/test/sbs_charging.tasklist b/test/sbs_charging.tasklist
new file mode 100644
index 0000000000..202541188f
--- /dev/null
+++ b/test/sbs_charging.tasklist
@@ -0,0 +1,11 @@
+/* Copyright 2014 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST \
+	TASK_TEST(CHARGER, charger_task, NULL, TASK_STACK_SIZE) \
+	TASK_TEST(CHIPSET, chipset_task, NULL, TASK_STACK_SIZE)
diff --git a/test/sbs_charging_v2.c b/test/sbs_charging_v2.c
deleted file mode 100644
index 7477c9d290..0000000000
--- a/test/sbs_charging_v2.c
+++ /dev/null
@@ -1,729 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test charge_state_v2 behavior
- */
-
-#include "battery_smart.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "task.h"
-#include "test_util.h"
-#include "util.h"
-
-#define WAIT_CHARGER_TASK 600
-#define BATTERY_DETACH_DELAY 35000
-
-static int mock_chipset_state = CHIPSET_STATE_ON;
-static int is_shutdown;
-static int is_force_discharge;
-static int is_hibernated;
-static int override_voltage, override_current, override_usec;
-
-/* The simulation doesn't really hibernate, so we must reset this ourselves */
-extern timestamp_t shutdown_target_time;
-
-static void reset_mocks(void)
-{
-	mock_chipset_state = CHIPSET_STATE_ON;
-	is_shutdown = is_force_discharge = is_hibernated = 0;
-	override_voltage = override_current = override_usec = 0;
-	shutdown_target_time.val = 0ULL;
-}
-
-int board_cut_off_battery(void)
-{
-	return EC_SUCCESS;
-}
-
-void chipset_force_shutdown(enum chipset_shutdown_reason reason)
-{
-	is_shutdown = 1;
-	mock_chipset_state = CHIPSET_STATE_HARD_OFF;
-}
-
-int chipset_in_state(int state_mask)
-{
-	return state_mask & mock_chipset_state;
-}
-
-int board_discharge_on_ac(int enabled)
-{
-	is_force_discharge = enabled;
-	return EC_SUCCESS;
-}
-
-void system_hibernate(int sec, int usec)
-{
-	is_hibernated = 1;
-}
-
-int charger_profile_override(struct charge_state_data *curr)
-{
-	if (override_voltage)
-		curr->requested_voltage = override_voltage;
-	if (override_current)
-		curr->requested_current = override_current;
-
-	if (override_usec)
-		return override_usec;
-
-	/* Don't let it sleep a whole minute when the AP is off */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return CHARGE_POLL_PERIOD_LONG;
-
-	return 0;
-}
-
-static uint32_t meh;
-enum ec_status charger_profile_override_get_param(uint32_t param,
-						  uint32_t *value)
-{
-	if (param == CS_PARAM_CUSTOM_PROFILE_MIN) {
-		*value = meh;
-		return EC_RES_SUCCESS;
-	}
-	return EC_RES_INVALID_PARAM;
-}
-enum ec_status charger_profile_override_set_param(uint32_t param,
-						  uint32_t value)
-{
-	if (param == CS_PARAM_CUSTOM_PROFILE_MIN) {
-		meh = value;
-		return EC_RES_SUCCESS;
-	}
-	return EC_RES_INVALID_PARAM;
-}
-
-static int wait_charging_state(void)
-{
-	enum charge_state state;
-	task_wake(TASK_ID_CHARGER);
-	msleep(WAIT_CHARGER_TASK);
-	state = charge_get_state();
-	ccprintf("[CHARGING TEST] state = %d\n", state);
-	return state;
-}
-
-static int charge_control(enum ec_charge_control_mode mode)
-{
-	struct ec_params_charge_control params;
-	params.mode = mode;
-	return test_send_host_command(EC_CMD_CHARGE_CONTROL, 1, &params,
-				      sizeof(params), NULL, 0);
-}
-
-/* Setup init condition */
-static void test_setup(int on_ac)
-{
-	const struct battery_info *bat_info = battery_get_info();
-
-	reset_mocks();
-
-	/* 50% of charge */
-	sb_write(SB_RELATIVE_STATE_OF_CHARGE, 50);
-	sb_write(SB_ABSOLUTE_STATE_OF_CHARGE, 50);
-	/* full charge capacity in mAh */
-	sb_write(SB_FULL_CHARGE_CAPACITY, 0xf000);
-	/* 25 degree Celsius */
-	sb_write(SB_TEMPERATURE, CELSIUS_TO_DECI_KELVIN(25));
-	/* battery pack voltage */
-	sb_write(SB_VOLTAGE, bat_info->voltage_normal);
-	/* desired charging voltage/current */
-	sb_write(SB_CHARGING_VOLTAGE, bat_info->voltage_max);
-	sb_write(SB_CHARGING_CURRENT, 4000);
-
-	/* battery pack current is positive when charging */
-	if (on_ac) {
-		sb_write(SB_CURRENT, 1000);
-		gpio_set_level(GPIO_AC_PRESENT, 1);
-	} else {
-		sb_write(SB_CURRENT, -100);
-		gpio_set_level(GPIO_AC_PRESENT, 0);
-	}
-
-	/* Reset the charger state to initial state */
-	charge_control(CHARGE_CONTROL_NORMAL);
-
-	/* Let things stabilize */
-	wait_charging_state();
-}
-
-/* Host Event helpers */
-static int ev_is_set(int event)
-{
-	return host_get_events() & EC_HOST_EVENT_MASK(event);
-}
-static int ev_is_clear(int event)
-{
-	return !ev_is_set(event);
-}
-static void ev_clear(int event)
-{
-	host_clear_events(EC_HOST_EVENT_MASK(event));
-}
-
-static int test_charge_state(void)
-{
-	enum charge_state state;
-	uint32_t flags;
-
-	/* On AC */
-	test_setup(1);
-
-	ccprintf("[CHARGING TEST] AC on\n");
-
-	/* Detach battery, charging error */
-	ccprintf("[CHARGING TEST] Detach battery\n");
-	TEST_ASSERT(test_detach_i2c(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS) ==
-		    EC_SUCCESS);
-	msleep(BATTERY_DETACH_DELAY);
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_ERROR);
-
-	/* Attach battery again, charging */
-	ccprintf("[CHARGING TEST] Attach battery\n");
-	test_attach_i2c(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS);
-	/* And changing full capacity should trigger a host event */
-	ev_clear(EC_HOST_EVENT_BATTERY);
-	sb_write(SB_FULL_CHARGE_CAPACITY, 0xeff0);
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_CHARGE);
-	TEST_ASSERT(ev_is_set(EC_HOST_EVENT_BATTERY));
-
-	/* Unplug AC, discharging at 1000mAh */
-	ccprintf("[CHARGING TEST] AC off\n");
-	gpio_set_level(GPIO_AC_PRESENT, 0);
-	sb_write(SB_CURRENT, -1000);
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_DISCHARGE);
-	flags = charge_get_flags();
-	TEST_ASSERT(!(flags & CHARGE_FLAG_EXTERNAL_POWER));
-	TEST_ASSERT(!(flags & CHARGE_FLAG_FORCE_IDLE));
-
-	/* Discharging waaaay overtemp is ignored */
-	ccprintf("[CHARGING TEST] AC off, batt temp = 0xffff\n");
-	gpio_set_level(GPIO_AC_PRESENT, 0);
-	sb_write(SB_CURRENT, -1000);
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_DISCHARGE);
-	sb_write(SB_TEMPERATURE, 0xffff);
-	state = wait_charging_state();
-	TEST_ASSERT(!is_shutdown);
-	TEST_ASSERT(state == PWR_STATE_DISCHARGE);
-	sb_write(SB_TEMPERATURE, CELSIUS_TO_DECI_KELVIN(40));
-
-	/* Discharging overtemp */
-	ccprintf("[CHARGING TEST] AC off, batt temp = 90 C\n");
-	gpio_set_level(GPIO_AC_PRESENT, 0);
-	sb_write(SB_CURRENT, -1000);
-
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_DISCHARGE);
-	sb_write(SB_TEMPERATURE, CELSIUS_TO_DECI_KELVIN(90));
-	state = wait_charging_state();
-	sleep(CONFIG_BATTERY_CRITICAL_SHUTDOWN_TIMEOUT);
-	TEST_ASSERT(is_shutdown);
-	TEST_ASSERT(state == PWR_STATE_DISCHARGE);
-	sb_write(SB_TEMPERATURE, CELSIUS_TO_DECI_KELVIN(40));
-
-	/* Force idle */
-	ccprintf("[CHARGING TEST] AC on, force idle\n");
-	gpio_set_level(GPIO_AC_PRESENT, 1);
-	sb_write(SB_CURRENT, 1000);
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_CHARGE);
-	flags = charge_get_flags();
-	TEST_ASSERT(flags & CHARGE_FLAG_EXTERNAL_POWER);
-	TEST_ASSERT(!(flags & CHARGE_FLAG_FORCE_IDLE));
-	charge_control(CHARGE_CONTROL_IDLE);
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_IDLE);
-	flags = charge_get_flags();
-	TEST_ASSERT(flags & CHARGE_FLAG_EXTERNAL_POWER);
-	TEST_ASSERT(flags & CHARGE_FLAG_FORCE_IDLE);
-	charge_control(CHARGE_CONTROL_NORMAL);
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_CHARGE);
-
-	/* Force discharge */
-	ccprintf("[CHARGING TEST] AC on, force discharge\n");
-	gpio_set_level(GPIO_AC_PRESENT, 1);
-	sb_write(SB_CURRENT, 1000);
-	charge_control(CHARGE_CONTROL_DISCHARGE);
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_IDLE);
-	TEST_ASSERT(is_force_discharge);
-	charge_control(CHARGE_CONTROL_NORMAL);
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_CHARGE);
-	TEST_ASSERT(!is_force_discharge);
-
-	return EC_SUCCESS;
-}
-
-static int test_low_battery(void)
-{
-	test_setup(1);
-
-	ccprintf("[CHARGING TEST] Low battery with AC and positive current\n");
-	sb_write(SB_RELATIVE_STATE_OF_CHARGE, 2);
-	sb_write(SB_CURRENT, 1000);
-	wait_charging_state();
-	mock_chipset_state = CHIPSET_STATE_SOFT_OFF;
-	hook_notify(HOOK_CHIPSET_SHUTDOWN);
-	TEST_ASSERT(!is_hibernated);
-
-	ccprintf("[CHARGING TEST] Low battery with AC and negative current\n");
-	sb_write(SB_CURRENT, -1000);
-	wait_charging_state();
-	sleep(CONFIG_BATTERY_CRITICAL_SHUTDOWN_TIMEOUT);
-	TEST_ASSERT(is_hibernated);
-
-	ccprintf("[CHARGING TEST] Low battery shutdown S0->S5\n");
-	mock_chipset_state = CHIPSET_STATE_ON;
-	hook_notify(HOOK_CHIPSET_PRE_INIT);
-	hook_notify(HOOK_CHIPSET_STARTUP);
-	gpio_set_level(GPIO_AC_PRESENT, 0);
-	is_hibernated = 0;
-	sb_write(SB_CURRENT, -1000);
-	sb_write(SB_RELATIVE_STATE_OF_CHARGE, 2);
-	wait_charging_state();
-	mock_chipset_state = CHIPSET_STATE_SOFT_OFF;
-	hook_notify(HOOK_CHIPSET_SHUTDOWN);
-	wait_charging_state();
-	/* after a while, the EC should hibernate */
-	sleep(CONFIG_BATTERY_CRITICAL_SHUTDOWN_TIMEOUT);
-	TEST_ASSERT(is_hibernated);
-
-	ccprintf("[CHARGING TEST] Low battery shutdown S5\n");
-	is_hibernated = 0;
-	sb_write(SB_RELATIVE_STATE_OF_CHARGE, 10);
-	wait_charging_state();
-	sb_write(SB_RELATIVE_STATE_OF_CHARGE, 2);
-	wait_charging_state();
-	/* after a while, the EC should hibernate */
-	sleep(CONFIG_BATTERY_CRITICAL_SHUTDOWN_TIMEOUT);
-	TEST_ASSERT(is_hibernated);
-
-	ccprintf("[CHARGING TEST] Low battery AP shutdown\n");
-	is_shutdown = 0;
-	mock_chipset_state = CHIPSET_STATE_ON;
-	sb_write(SB_RELATIVE_STATE_OF_CHARGE, 10);
-	gpio_set_level(GPIO_AC_PRESENT, 1);
-	sb_write(SB_CURRENT, 1000);
-	wait_charging_state();
-	gpio_set_level(GPIO_AC_PRESENT, 0);
-	sb_write(SB_CURRENT, -1000);
-	sb_write(SB_RELATIVE_STATE_OF_CHARGE, 2);
-	wait_charging_state();
-	usleep(32 * SECOND);
-	wait_charging_state();
-	TEST_ASSERT(is_shutdown);
-
-	return EC_SUCCESS;
-}
-
-static int test_high_temp_battery(void)
-{
-	test_setup(1);
-
-	ccprintf("[CHARGING TEST] High battery temperature shutdown\n");
-	ev_clear(EC_HOST_EVENT_BATTERY_SHUTDOWN);
-	sb_write(SB_TEMPERATURE, CELSIUS_TO_DECI_KELVIN(90));
-	wait_charging_state();
-	TEST_ASSERT(ev_is_set(EC_HOST_EVENT_BATTERY_SHUTDOWN));
-	TEST_ASSERT(!is_shutdown);
-	sleep(CONFIG_BATTERY_CRITICAL_SHUTDOWN_TIMEOUT);
-	TEST_ASSERT(is_shutdown);
-
-	ccprintf("[CHARGING TEST] High battery temp S0->S5 hibernate\n");
-	mock_chipset_state = CHIPSET_STATE_SOFT_OFF;
-	wait_charging_state();
-	TEST_ASSERT(is_hibernated);
-
-	return EC_SUCCESS;
-}
-
-static int test_cold_battery_with_ac(void)
-{
-	test_setup(1);
-
-	ccprintf("[CHARGING TEST] Cold battery no shutdown with AC\n");
-	ev_clear(EC_HOST_EVENT_BATTERY_SHUTDOWN);
-	sb_write(SB_TEMPERATURE, CELSIUS_TO_DECI_KELVIN(-90));
-	wait_charging_state();
-	sleep(CONFIG_BATTERY_CRITICAL_SHUTDOWN_TIMEOUT);
-	TEST_ASSERT(!is_shutdown);
-
-	return EC_SUCCESS;
-}
-
-static int test_cold_battery_no_ac(void)
-{
-	test_setup(0);
-
-	ccprintf("[CHARGING TEST] Cold battery shutdown when discharging\n");
-	ev_clear(EC_HOST_EVENT_BATTERY_SHUTDOWN);
-	sb_write(SB_TEMPERATURE, CELSIUS_TO_DECI_KELVIN(-90));
-	wait_charging_state();
-	TEST_ASSERT(ev_is_set(EC_HOST_EVENT_BATTERY_SHUTDOWN));
-	TEST_ASSERT(!is_shutdown);
-	sleep(CONFIG_BATTERY_CRITICAL_SHUTDOWN_TIMEOUT);
-	TEST_ASSERT(is_shutdown);
-
-	return EC_SUCCESS;
-}
-
-static int test_external_funcs(void)
-{
-	int rv, temp;
-	uint32_t flags;
-	int state;
-
-	/* Connect the AC */
-	test_setup(1);
-
-	flags = charge_get_flags();
-	TEST_ASSERT(flags & CHARGE_FLAG_EXTERNAL_POWER);
-	TEST_ASSERT(!(flags & CHARGE_FLAG_FORCE_IDLE));
-
-	/* Invalid or do-nothing commands first */
-	UART_INJECT("chg\n");
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_CHARGE);
-	flags = charge_get_flags();
-	TEST_ASSERT(flags & CHARGE_FLAG_EXTERNAL_POWER);
-	TEST_ASSERT(!(flags & CHARGE_FLAG_FORCE_IDLE));
-
-	UART_INJECT("chg blahblah\n");
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_CHARGE);
-	flags = charge_get_flags();
-	TEST_ASSERT(flags & CHARGE_FLAG_EXTERNAL_POWER);
-	TEST_ASSERT(!(flags & CHARGE_FLAG_FORCE_IDLE));
-
-	UART_INJECT("chg idle\n");
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_CHARGE);
-	flags = charge_get_flags();
-	TEST_ASSERT(flags & CHARGE_FLAG_EXTERNAL_POWER);
-	TEST_ASSERT(!(flags & CHARGE_FLAG_FORCE_IDLE));
-
-	UART_INJECT("chg idle blargh\n");
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_CHARGE);
-	flags = charge_get_flags();
-	TEST_ASSERT(flags & CHARGE_FLAG_EXTERNAL_POWER);
-	TEST_ASSERT(!(flags & CHARGE_FLAG_FORCE_IDLE));
-
-	/* Now let's force idle on and off */
-	UART_INJECT("chg idle on\n");
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_IDLE);
-	flags = charge_get_flags();
-	TEST_ASSERT(flags & CHARGE_FLAG_EXTERNAL_POWER);
-	TEST_ASSERT(flags & CHARGE_FLAG_FORCE_IDLE);
-
-	UART_INJECT("chg idle off\n");
-	wait_charging_state();
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_CHARGE);
-	flags = charge_get_flags();
-	TEST_ASSERT(flags & CHARGE_FLAG_EXTERNAL_POWER);
-	TEST_ASSERT(!(flags & CHARGE_FLAG_FORCE_IDLE));
-
-	/* and the rest */
-	TEST_ASSERT(charge_get_state() == PWR_STATE_CHARGE);
-	TEST_ASSERT(!charge_want_shutdown());
-	TEST_ASSERT(charge_get_percent() == 50);
-	temp = 0;
-	rv = charge_get_battery_temp(0, &temp);
-	TEST_ASSERT(rv == EC_SUCCESS);
-	TEST_ASSERT(K_TO_C(temp) == 25);
-
-	return EC_SUCCESS;
-}
-
-#define CHG_OPT1 0x2000
-#define CHG_OPT2 0x4000
-static int test_hc_charge_state(void)
-{
-	enum charge_state state;
-	int i, rv, tmp;
-	struct ec_params_charge_state params;
-	struct ec_response_charge_state resp;
-
-	/* Let's connect the AC again. */
-	test_setup(1);
-
-	/* Initialize the charger options with some nonzero value */
-	TEST_ASSERT(charger_set_option(CHG_OPT1) == EC_SUCCESS);
-
-	/* Get the state */
-	memset(&resp, 0, sizeof(resp));
-	params.cmd = CHARGE_STATE_CMD_GET_STATE;
-	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0,
-				    &params, sizeof(params),
-				    &resp, sizeof(resp));
-	TEST_ASSERT(rv == EC_RES_SUCCESS);
-	TEST_ASSERT(resp.get_state.ac);
-	TEST_ASSERT(resp.get_state.chg_voltage);
-	TEST_ASSERT(resp.get_state.chg_current);
-	TEST_ASSERT(resp.get_state.chg_input_current);
-	TEST_ASSERT(resp.get_state.batt_state_of_charge);
-
-	/* Check all the params */
-	for (i = 0; i < CS_NUM_BASE_PARAMS; i++) {
-
-		/* Read it */
-		memset(&resp, 0, sizeof(resp));
-		params.cmd = CHARGE_STATE_CMD_GET_PARAM;
-		params.get_param.param = i;
-		rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0,
-					    &params, sizeof(params),
-					    &resp, sizeof(resp));
-		TEST_ASSERT(rv == EC_RES_SUCCESS);
-		if (i != CS_PARAM_LIMIT_POWER)
-			TEST_ASSERT(resp.get_param.value);
-		else
-			TEST_ASSERT(!resp.get_param.value);
-
-		/* Bump it up a bit */
-		tmp = resp.get_param.value;
-		switch (i) {
-		case CS_PARAM_CHG_VOLTAGE:
-		case CS_PARAM_CHG_CURRENT:
-		case CS_PARAM_CHG_INPUT_CURRENT:
-			tmp -= 128;		/* Should be valid delta */
-			break;
-		case CS_PARAM_CHG_STATUS:
-		case CS_PARAM_LIMIT_POWER:
-			/* These ones can't be set */
-			break;
-		case CS_PARAM_CHG_OPTION:
-			tmp = CHG_OPT2;
-			break;
-		}
-		params.cmd = CHARGE_STATE_CMD_SET_PARAM;
-		params.set_param.param = i;
-		params.set_param.value = tmp;
-		rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0,
-					    &params, sizeof(params),
-					    &resp, sizeof(resp));
-		if (i == CS_PARAM_CHG_STATUS || i == CS_PARAM_LIMIT_POWER)
-			TEST_ASSERT(rv == EC_RES_ACCESS_DENIED);
-		else
-			TEST_ASSERT(rv == EC_RES_SUCCESS);
-		/* Allow the change to take effect */
-		state = wait_charging_state();
-		TEST_ASSERT(state == PWR_STATE_CHARGE);
-
-		/* Read it back again*/
-		memset(&resp, 0, sizeof(resp));
-		params.cmd = CHARGE_STATE_CMD_GET_PARAM;
-		params.get_param.param = i;
-		rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0,
-					    &params, sizeof(params),
-					    &resp, sizeof(resp));
-		TEST_ASSERT(rv == EC_RES_SUCCESS);
-		TEST_ASSERT(resp.get_param.value == tmp);
-	}
-
-	/* And a custom profile param */
-	meh = 0xdeadbeef;
-	memset(&resp, 0, sizeof(resp));
-	params.cmd = CHARGE_STATE_CMD_GET_PARAM;
-	params.get_param.param = CS_PARAM_CUSTOM_PROFILE_MIN;
-	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0,
-				    &params, sizeof(params),
-				    &resp, sizeof(resp));
-	TEST_ASSERT(rv == EC_RES_SUCCESS);
-	TEST_ASSERT(resp.get_param.value == meh);
-	params.cmd = CHARGE_STATE_CMD_SET_PARAM;
-	params.set_param.param = CS_PARAM_CUSTOM_PROFILE_MIN;
-	params.set_param.value = 0xc0def00d;
-	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0,
-				    &params, sizeof(params),
-				    &resp, sizeof(resp));
-	TEST_ASSERT(rv == EC_RES_SUCCESS);
-	/* Allow the change to take effect */
-	state = wait_charging_state();
-	TEST_ASSERT(meh == params.set_param.value);
-
-	/* param out of range */
-	params.cmd = CHARGE_STATE_CMD_GET_PARAM;
-	params.get_param.param = CS_NUM_BASE_PARAMS;
-	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0,
-				    &params, sizeof(params),
-				    &resp, sizeof(resp));
-	TEST_ASSERT(rv == EC_RES_INVALID_PARAM);
-	params.cmd = CHARGE_STATE_CMD_SET_PARAM;
-	params.set_param.param = CS_NUM_BASE_PARAMS;
-	params.set_param.value = 0x1000;	/* random value */
-	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0,
-				    &params, sizeof(params),
-				    &resp, sizeof(resp));
-	TEST_ASSERT(rv == EC_RES_INVALID_PARAM);
-
-	/* command out of range */
-	params.cmd = CHARGE_STATE_NUM_CMDS;
-	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0,
-				    &params, sizeof(params),
-				    &resp, sizeof(resp));
-	TEST_ASSERT(rv == EC_RES_INVALID_PARAM);
-
-	/*
-	 * We've screwed with the charger settings, so let the state machine
-	 * reset itself before we stop.
-	 */
-	test_setup(0);
-	test_setup(1);
-
-	return EC_SUCCESS;
-}
-
-static int test_hc_current_limit(void)
-{
-	int rv, norm_current, lower_current;
-	struct ec_params_charge_state cs_params;
-	struct ec_response_charge_state cs_resp;
-	struct ec_params_current_limit cl_params;
-
-	/* On AC */
-	test_setup(1);
-
-	/* See what current the charger is delivering */
-	cs_params.cmd = CHARGE_STATE_CMD_GET_STATE;
-	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0,
-				    &cs_params, sizeof(cs_params),
-				    &cs_resp, sizeof(cs_resp));
-	TEST_ASSERT(rv == EC_RES_SUCCESS);
-	norm_current = cs_resp.get_state.chg_current;
-
-	/* Lower it a bit */
-	lower_current = norm_current - 256;
-	cl_params.limit = lower_current;
-	rv = test_send_host_command(EC_CMD_CHARGE_CURRENT_LIMIT, 0,
-				    &cl_params, sizeof(cl_params),
-				    0, 0);
-	TEST_ASSERT(rv == EC_RES_SUCCESS);
-	wait_charging_state();
-
-	/* See that it's changed */
-	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0,
-				    &cs_params, sizeof(cs_params),
-				    &cs_resp, sizeof(cs_resp));
-	TEST_ASSERT(rv == EC_RES_SUCCESS);
-	TEST_ASSERT(lower_current == cs_resp.get_state.chg_current);
-
-	/* Remove the limit */
-	cl_params.limit = -1U;
-	rv = test_send_host_command(EC_CMD_CHARGE_CURRENT_LIMIT, 0,
-				    &cl_params, sizeof(cl_params),
-				    0, 0);
-	TEST_ASSERT(rv == EC_RES_SUCCESS);
-	wait_charging_state();
-
-	/* See that it's back */
-	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0,
-				    &cs_params, sizeof(cs_params),
-				    &cs_resp, sizeof(cs_resp));
-	TEST_ASSERT(rv == EC_RES_SUCCESS);
-	TEST_ASSERT(norm_current == cs_resp.get_state.chg_current);
-
-	return EC_SUCCESS;
-}
-
-static int test_low_battery_hostevents(void)
-{
-	int state;
-
-	test_setup(0);
-
-	ccprintf("[CHARGING TEST] Low battery host events\n");
-
-	/* You know you make me wanna */
-	sb_write(SB_RELATIVE_STATE_OF_CHARGE, BATTERY_LEVEL_LOW + 1);
-	ev_clear(EC_HOST_EVENT_BATTERY_LOW);
-	ev_clear(EC_HOST_EVENT_BATTERY_CRITICAL);
-	ev_clear(EC_HOST_EVENT_BATTERY_SHUTDOWN);
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_DISCHARGE);
-	TEST_ASSERT(ev_is_clear(EC_HOST_EVENT_BATTERY_LOW));
-	TEST_ASSERT(ev_is_clear(EC_HOST_EVENT_BATTERY_CRITICAL));
-	TEST_ASSERT(ev_is_clear(EC_HOST_EVENT_BATTERY_SHUTDOWN));
-
-	/* (Shout) a little bit louder now */
-	sb_write(SB_RELATIVE_STATE_OF_CHARGE, BATTERY_LEVEL_LOW - 1);
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_DISCHARGE);
-	TEST_ASSERT(ev_is_set(EC_HOST_EVENT_BATTERY_LOW));
-	TEST_ASSERT(ev_is_clear(EC_HOST_EVENT_BATTERY_CRITICAL));
-	TEST_ASSERT(ev_is_clear(EC_HOST_EVENT_BATTERY_SHUTDOWN));
-	TEST_ASSERT(!is_shutdown);
-
-	/* (Shout) a little bit louder now */
-	sb_write(SB_RELATIVE_STATE_OF_CHARGE, BATTERY_LEVEL_CRITICAL + 1);
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_DISCHARGE);
-	TEST_ASSERT(ev_is_set(EC_HOST_EVENT_BATTERY_LOW));
-	TEST_ASSERT(ev_is_clear(EC_HOST_EVENT_BATTERY_CRITICAL));
-	TEST_ASSERT(ev_is_clear(EC_HOST_EVENT_BATTERY_SHUTDOWN));
-	TEST_ASSERT(!is_shutdown);
-
-	/* (Shout) a little bit louder now */
-	sb_write(SB_RELATIVE_STATE_OF_CHARGE, BATTERY_LEVEL_CRITICAL - 1);
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_DISCHARGE);
-	TEST_ASSERT(ev_is_set(EC_HOST_EVENT_BATTERY_LOW));
-	TEST_ASSERT(ev_is_set(EC_HOST_EVENT_BATTERY_CRITICAL));
-	TEST_ASSERT(ev_is_clear(EC_HOST_EVENT_BATTERY_SHUTDOWN));
-	TEST_ASSERT(!is_shutdown);
-
-	/* (Shout) a little bit louder now */
-	sb_write(SB_RELATIVE_STATE_OF_CHARGE, BATTERY_LEVEL_SHUTDOWN + 1);
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_DISCHARGE);
-	TEST_ASSERT(ev_is_set(EC_HOST_EVENT_BATTERY_LOW));
-	TEST_ASSERT(ev_is_set(EC_HOST_EVENT_BATTERY_CRITICAL));
-	TEST_ASSERT(ev_is_clear(EC_HOST_EVENT_BATTERY_SHUTDOWN));
-	TEST_ASSERT(!is_shutdown);
-
-	/* (Shout) a little bit louder now */
-	sb_write(SB_RELATIVE_STATE_OF_CHARGE, BATTERY_LEVEL_SHUTDOWN - 1);
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_DISCHARGE);
-	TEST_ASSERT(ev_is_set(EC_HOST_EVENT_BATTERY_LOW));
-	TEST_ASSERT(ev_is_set(EC_HOST_EVENT_BATTERY_CRITICAL));
-	/* hey-hey-HEY-hey. Doesn't immediately shut down */
-	TEST_ASSERT(ev_is_set(EC_HOST_EVENT_BATTERY_SHUTDOWN));
-	TEST_ASSERT(!is_shutdown);
-	/* after a while, the AP should shut down */
-	sleep(CONFIG_BATTERY_CRITICAL_SHUTDOWN_TIMEOUT);
-	TEST_ASSERT(is_shutdown);
-
-	return EC_SUCCESS;
-}
-
-
-
-void run_test(int argc, char **argv)
-{
-	RUN_TEST(test_charge_state);
-	RUN_TEST(test_low_battery);
-	RUN_TEST(test_high_temp_battery);
-	RUN_TEST(test_cold_battery_with_ac);
-	RUN_TEST(test_cold_battery_no_ac);
-	RUN_TEST(test_external_funcs);
-	RUN_TEST(test_hc_charge_state);
-	RUN_TEST(test_hc_current_limit);
-	RUN_TEST(test_low_battery_hostevents);
-
-	test_print_result();
-}
diff --git a/test/sbs_charging_v2.tasklist b/test/sbs_charging_v2.tasklist
deleted file mode 100644
index 3895762986..0000000000
--- a/test/sbs_charging_v2.tasklist
+++ /dev/null
@@ -1,11 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST \
-	TASK_TEST(CHARGER, charger_task, NULL, TASK_STACK_SIZE) \
-	TASK_TEST(CHIPSET, chipset_task, NULL, TASK_STACK_SIZE)
diff --git a/test/scoped_fast_cpu.cc b/test/scoped_fast_cpu.cc
new file mode 100644
index 0000000000..ec66ae1fdf
--- /dev/null
+++ b/test/scoped_fast_cpu.cc
@@ -0,0 +1,57 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Basic test of ScopedFastCpu.
+ */
+
+#include "common.h"
+
+extern "C" {
+#include "console.h"
+#include "test_util.h"
+}
+
+#include "mock/clock_mock.h"
+#include "scoped_fast_cpu.h"
+
+test_static int fast_cpu_disable_at_start()
+{
+	{
+		TEST_EQ(get_mock_fast_cpu_status(), 0, "%d");
+		{
+			/* instantiate, which calls constructor. */
+			ScopedFastCpu cpu;
+			TEST_EQ(get_mock_fast_cpu_status(), 1, "%d");
+			/* destructed here. */
+		}
+		TEST_EQ(get_mock_fast_cpu_status(), 0, "%d");
+	}
+	return EC_SUCCESS;
+}
+
+test_static int fast_cpu_enable_at_start()
+{
+	{
+		ScopedFastCpu cpu;
+		TEST_EQ(get_mock_fast_cpu_status(), 1, "%d");
+		{
+			/* instantiate, which calls constructor. */
+			ScopedFastCpu cpu;
+			TEST_EQ(get_mock_fast_cpu_status(), 1, "%d");
+			/* destructed here. */
+		}
+		TEST_EQ(get_mock_fast_cpu_status(), 1, "%d");
+	}
+	return EC_SUCCESS;
+}
+
+extern "C" void run_test(int argc, const char **argv)
+{
+	test_reset();
+
+	RUN_TEST(fast_cpu_disable_at_start);
+	RUN_TEST(fast_cpu_enable_at_start);
+
+	test_print_result();
+}
\ No newline at end of file
diff --git a/test/scoped_fast_cpu.mocklist b/test/scoped_fast_cpu.mocklist
new file mode 100644
index 0000000000..c2d5b4a689
--- /dev/null
+++ b/test/scoped_fast_cpu.mocklist
@@ -0,0 +1,8 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifdef TEST_BUILD
+#define CONFIG_TEST_MOCK_LIST MOCK(CLOCK)
+#endif /* TEST_BUILD */
diff --git a/test/scoped_fast_cpu.tasklist b/test/scoped_fast_cpu.tasklist
new file mode 100644
index 0000000000..e85d8b7405
--- /dev/null
+++ b/test/scoped_fast_cpu.tasklist
@@ -0,0 +1,9 @@
+/* Copyright 2023 The ChromiumOS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST
diff --git a/test/scratchpad.c b/test/scratchpad.c
index eeae7fcb93..c023f1dc72 100644
--- a/test/scratchpad.c
+++ b/test/scratchpad.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,19 +15,19 @@ test_static int test_scratchpad(void)
 	int rv;
 	uint32_t scratch;
 
-	scratch = system_get_scratchpad();
+	TEST_EQ(system_get_scratchpad(&scratch), EC_SUCCESS, "%d");
 	TEST_EQ(scratch, 0, "%d");
 
 	rv = system_set_scratchpad(1);
 	TEST_EQ(rv, EC_SUCCESS, "%d");
 
-	scratch = system_get_scratchpad();
+	TEST_EQ(system_get_scratchpad(&scratch), EC_SUCCESS, "%d");
 	TEST_EQ(scratch, 1, "%d");
 
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	RUN_TEST(test_scratchpad);
 	test_print_result();
diff --git a/test/scratchpad.tasklist b/test/scratchpad.tasklist
index 51734f058d..a1f1a94e2d 100644
--- a/test/scratchpad.tasklist
+++ b/test/scratchpad.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/sha256.c b/test/sha256.c
index 105ae8fec5..0387d23175 100644
--- a/test/sha256.c
+++ b/test/sha256.c
@@ -1,34 +1,31 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Tests SHA256 implementation.
  */
 
-#include "console.h"
 #include "common.h"
+#include "console.h"
 #include "sha256.h"
 #include "test_util.h"
 #include "util.h"
 
 /* Short Msg from NIST FIPS 180-4 (Len = 8) */
-static const uint8_t sha256_8_input[] = {
-	0xd3
-};
+static const uint8_t sha256_8_input[] = { 0xd3 };
 static const uint8_t sha256_8_output[SHA256_DIGEST_SIZE] = {
-	0x28, 0x96, 0x9c, 0xdf, 0xa7, 0x4a, 0x12, 0xc8, 0x2f, 0x3b, 0xad, 0x96,
-	0x0b, 0x0b, 0x00, 0x0a, 0xca, 0x2a, 0xc3, 0x29, 0xde, 0xea, 0x5c, 0x23,
-	0x28, 0xeb, 0xc6, 0xf2, 0xba, 0x98, 0x02, 0xc1
+	0x28, 0x96, 0x9c, 0xdf, 0xa7, 0x4a, 0x12, 0xc8, 0x2f, 0x3b, 0xad,
+	0x96, 0x0b, 0x0b, 0x00, 0x0a, 0xca, 0x2a, 0xc3, 0x29, 0xde, 0xea,
+	0x5c, 0x23, 0x28, 0xeb, 0xc6, 0xf2, 0xba, 0x98, 0x02, 0xc1
 };
 
 /* Short Msg from NIST FIPS 180-4 (Len = 72) */
-static const uint8_t sha256_72_input[] = {
-	0x33, 0x34, 0xc5, 0x80, 0x75, 0xd3, 0xf4, 0x13, 0x9e
-};
+static const uint8_t sha256_72_input[] = { 0x33, 0x34, 0xc5, 0x80, 0x75,
+					   0xd3, 0xf4, 0x13, 0x9e };
 static const uint8_t sha256_72_output[SHA256_DIGEST_SIZE] = {
-	0x07, 0x8d, 0xa3, 0xd7, 0x7e, 0xd4, 0x3b, 0xd3, 0x03, 0x7a, 0x43, 0x3f,
-	0xd0, 0x34, 0x18, 0x55, 0x02, 0x37, 0x93, 0xf9, 0xaf, 0xd0, 0x8b, 0x4b,
-	0x08, 0xea, 0x1e, 0x55, 0x97, 0xce, 0xef, 0x20
+	0x07, 0x8d, 0xa3, 0xd7, 0x7e, 0xd4, 0x3b, 0xd3, 0x03, 0x7a, 0x43,
+	0x3f, 0xd0, 0x34, 0x18, 0x55, 0x02, 0x37, 0x93, 0xf9, 0xaf, 0xd0,
+	0x8b, 0x4b, 0x08, 0xea, 0x1e, 0x55, 0x97, 0xce, 0xef, 0x20
 };
 
 /* Long Msg from NIST FIPS 180-4 (Len = 2888) */
@@ -66,9 +63,9 @@ static const uint8_t sha256_2888_input[] = {
 	0x93
 };
 static const uint8_t sha256_2888_output[SHA256_DIGEST_SIZE] = {
-	0x5f, 0x4e, 0x16, 0xa7, 0x2d, 0x6c, 0x98, 0x57, 0xda, 0x0b, 0xa0, 0x09,
-	0xcc, 0xac, 0xd4, 0xf2, 0x6d, 0x7f, 0x6b, 0xf6, 0xc1, 0xb7, 0x8a, 0x2e,
-	0xd3, 0x5e, 0x68, 0xfc, 0xb1, 0x5b, 0x8e, 0x40
+	0x5f, 0x4e, 0x16, 0xa7, 0x2d, 0x6c, 0x98, 0x57, 0xda, 0x0b, 0xa0,
+	0x09, 0xcc, 0xac, 0xd4, 0xf2, 0x6d, 0x7f, 0x6b, 0xf6, 0xc1, 0xb7,
+	0x8a, 0x2e, 0xd3, 0x5e, 0x68, 0xfc, 0xb1, 0x5b, 0x8e, 0x40
 };
 
 /* HMAC short key (40 bytes) from NIST FIPS 198-1 (Count = 34) */
@@ -86,15 +83,15 @@ static const uint8_t hmac_short_msg[] = {
 	0x03, 0x2b, 0x31, 0xd2, 0x41, 0xad, 0x33, 0x71
 };
 static const uint8_t hmac_short_key[] = {
-	0x9d, 0xa0, 0xc1, 0x14, 0x68, 0x2f, 0x82, 0xc1, 0xd1, 0xe9, 0xb5, 0x44,
-	0x30, 0x58, 0x0b, 0x9c, 0x56, 0x94, 0x89, 0xca, 0x16, 0xb9, 0x2e, 0xe1,
-	0x04, 0x98, 0xd5, 0x5d, 0x7c, 0xad, 0x5d, 0xb5, 0xe6, 0x52, 0x06, 0x34,
-	0x39, 0x31, 0x1e, 0x04
+	0x9d, 0xa0, 0xc1, 0x14, 0x68, 0x2f, 0x82, 0xc1, 0xd1, 0xe9,
+	0xb5, 0x44, 0x30, 0x58, 0x0b, 0x9c, 0x56, 0x94, 0x89, 0xca,
+	0x16, 0xb9, 0x2e, 0xe1, 0x04, 0x98, 0xd5, 0x5d, 0x7c, 0xad,
+	0x5d, 0xb5, 0xe6, 0x52, 0x06, 0x34, 0x39, 0x31, 0x1e, 0x04
 };
 static const uint8_t hmac_short_output[] = {
-	0xcd, 0xea, 0xcf, 0xce, 0xbf, 0x46, 0xcc, 0x9d, 0x7e, 0x4d, 0x41, 0x75,
-	0xe5, 0xd8, 0xd2, 0x67, 0xc2, 0x3a, 0x64, 0xcd, 0xe8, 0x3e, 0x86, 0x7e,
-	0x50, 0x01, 0xec, 0xf2, 0x6f, 0xbd, 0x30, 0xd2
+	0xcd, 0xea, 0xcf, 0xce, 0xbf, 0x46, 0xcc, 0x9d, 0x7e, 0x4d, 0x41,
+	0x75, 0xe5, 0xd8, 0xd2, 0x67, 0xc2, 0x3a, 0x64, 0xcd, 0xe8, 0x3e,
+	0x86, 0x7e, 0x50, 0x01, 0xec, 0xf2, 0x6f, 0xbd, 0x30, 0xd2
 };
 
 /* HMAC medium key (64 bytes) from NIST FIPS 198-1 (Count = 120) */
@@ -112,17 +109,17 @@ static const uint8_t hmac_medium_msg[] = {
 	0x85, 0x46, 0x80, 0x4f, 0x9c, 0xf2, 0xec, 0xfe
 };
 static const uint8_t hmac_medium_key[] = {
-	0x99, 0x28, 0x68, 0x50, 0x4d, 0x25, 0x64, 0xc4, 0xfb, 0x47, 0xbc, 0xbd,
-	0x4a, 0xe4, 0x82, 0xd8, 0xfb, 0x0e, 0x8e, 0x56, 0xd7, 0xb8, 0x18, 0x64,
-	0xe6, 0x19, 0x86, 0xa0, 0xe2, 0x56, 0x82, 0xda, 0xeb, 0x5b, 0x50, 0x17,
-	0x7c, 0x09, 0x5e, 0xdc, 0x9e, 0x97, 0x1d, 0xa9, 0x5c, 0x32, 0x10, 0xc3,
-	0x76, 0xe7, 0x23, 0x36, 0x5a, 0xc3, 0x3d, 0x1b, 0x4f, 0x39, 0x18, 0x17,
-	0xf4, 0xc3, 0x51, 0x24
+	0x99, 0x28, 0x68, 0x50, 0x4d, 0x25, 0x64, 0xc4, 0xfb, 0x47, 0xbc,
+	0xbd, 0x4a, 0xe4, 0x82, 0xd8, 0xfb, 0x0e, 0x8e, 0x56, 0xd7, 0xb8,
+	0x18, 0x64, 0xe6, 0x19, 0x86, 0xa0, 0xe2, 0x56, 0x82, 0xda, 0xeb,
+	0x5b, 0x50, 0x17, 0x7c, 0x09, 0x5e, 0xdc, 0x9e, 0x97, 0x1d, 0xa9,
+	0x5c, 0x32, 0x10, 0xc3, 0x76, 0xe7, 0x23, 0x36, 0x5a, 0xc3, 0x3d,
+	0x1b, 0x4f, 0x39, 0x18, 0x17, 0xf4, 0xc3, 0x51, 0x24
 };
 static const uint8_t hmac_medium_output[] = {
-	0x2f, 0x83, 0x21, 0xf4, 0x16, 0xb9, 0xbb, 0x24, 0x9f, 0x11, 0x3b, 0x13,
-	0xfc, 0x12, 0xd7, 0x0e, 0x16, 0x68, 0xdc, 0x33, 0x28, 0x39, 0xc1, 0x0d,
-	0xaa, 0x57, 0x17, 0x89, 0x6c, 0xb7, 0x0d, 0xdf
+	0x2f, 0x83, 0x21, 0xf4, 0x16, 0xb9, 0xbb, 0x24, 0x9f, 0x11, 0x3b,
+	0x13, 0xfc, 0x12, 0xd7, 0x0e, 0x16, 0x68, 0xdc, 0x33, 0x28, 0x39,
+	0xc1, 0x0d, 0xaa, 0x57, 0x17, 0x89, 0x6c, 0xb7, 0x0d, 0xdf
 };
 
 static int test_sha256(const uint8_t *input, int input_len,
@@ -156,9 +153,8 @@ static int test_sha256(const uint8_t *input, int input_len,
 	return 1;
 }
 
-static int test_hmac(const uint8_t *key, int key_len,
-		     const uint8_t *input, int input_len,
-		     const uint8_t *output)
+static int test_hmac(const uint8_t *key, int key_len, const uint8_t *input,
+		     int input_len, const uint8_t *output)
 {
 	uint8_t tmp[SHA256_DIGEST_SIZE];
 
@@ -172,7 +168,7 @@ static int test_hmac(const uint8_t *key, int key_len,
 	return 1;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	ccprintf("Testing short message (8 bytes)\n");
 	if (!test_sha256(sha256_8_input, sizeof(sha256_8_input),
@@ -196,9 +192,8 @@ void run_test(int argc, char **argv)
 	}
 
 	ccprintf("HMAC: Testing short key\n");
-	if (!test_hmac(hmac_short_key, sizeof(hmac_short_key),
-		       hmac_short_msg, sizeof(hmac_short_msg),
-		       hmac_short_output)) {
+	if (!test_hmac(hmac_short_key, sizeof(hmac_short_key), hmac_short_msg,
+		       sizeof(hmac_short_msg), hmac_short_output)) {
 		test_fail();
 		return;
 	}
diff --git a/test/sha256.tasklist b/test/sha256.tasklist
index 80072bb620..329f9a3d28 100644
--- a/test/sha256.tasklist
+++ b/test/sha256.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/shmalloc.c b/test/shmalloc.c
index 70e0fb5aab..f86efd4fa9 100644
--- a/test/shmalloc.c
+++ b/test/shmalloc.c
@@ -1,14 +1,9 @@
 /*
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <stddef.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-
 #include "common.h"
 #include "compile_time_macros.h"
 #include "console.h"
@@ -16,6 +11,11 @@
 #include "shared_mem.h"
 #include "test_util.h"
 
+#include <stddef.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+
 /*
  * Total size of memory in the malloc pool (shared between free and allocated
  * buffers.
@@ -36,14 +36,14 @@ static uint32_t next = 127;
 static uint32_t myrand(void)
 {
 	next = next * 1103515245 + 12345;
-	return ((uint32_t)(next/65536) % 32768);
+	return ((uint32_t)(next / 65536) % 32768);
 }
 
 /* Keep track of buffers allocated by the test function. */
 static struct {
 	void *buf;
 	size_t buffer_size;
-} allocations[12];  /* Up to 12 buffers could be allocated concurrently. */
+} allocations[12]; /* Up to 12 buffers could be allocated concurrently. */
 
 /*
  * Verify that allocated and free buffers do not overlap, and that our and
@@ -77,8 +77,7 @@ static int check_for_overlaps(void)
 		 * multiple times to keep things simple.
 		 */
 		allocated_count = 0;
-		for (allocced_buf = allocced_buf_chain;
-		     allocced_buf;
+		for (allocced_buf = allocced_buf_chain; allocced_buf;
 		     allocced_buf = allocced_buf->next_buffer) {
 			int allocated_size, allocation_size;
 
@@ -112,13 +111,13 @@ static int check_for_overlaps(void)
 			}
 		}
 		if (!allocation_match) {
-			ccprintf("missing match %pP!\n", allocations[i].buf);
+			ccprintf("missing match %p!\n", allocations[i].buf);
 			return 0;
 		}
 	}
 	if (allocations_count != allocated_count) {
-		ccprintf("count mismatch (%d != %d)!\n",
-			 allocations_count, allocated_count);
+		ccprintf("count mismatch (%d != %d)!\n", allocations_count,
+			 allocated_count);
 		return 0;
 	}
 	return 1;
@@ -137,7 +136,7 @@ static int shmem_is_ok(int line)
 	struct shm_buffer *pbuf = free_buf_chain;
 
 	if (pbuf && pbuf->prev_buffer) {
-		ccprintf("Bad free buffer list start %pP\n", pbuf);
+		ccprintf("Bad free buffer list start %p\n", pbuf);
 		goto bailout;
 	}
 
@@ -146,20 +145,20 @@ static int shmem_is_ok(int line)
 
 		running_size += pbuf->buffer_size;
 		if (count++ > 100)
-			goto bailout;  /* Is there a loop? */
+			goto bailout; /* Is there a loop? */
 
 		top = (struct shm_buffer *)((uintptr_t)pbuf +
-					     pbuf->buffer_size);
+					    pbuf->buffer_size);
 		if (pbuf->next_buffer) {
 			if (top >= pbuf->next_buffer) {
 				ccprintf("%s:%d"
-					 " - inconsistent buffer size at %pP\n",
+					 " - inconsistent buffer size at %p\n",
 					 __func__, __LINE__, pbuf);
 				goto bailout;
 			}
 			if (pbuf->next_buffer->prev_buffer != pbuf) {
 				ccprintf("%s:%d"
-					 " - inconsistent next buffer at %pP\n",
+					 " - inconsistent next buffer at %p\n",
 					 __func__, __LINE__, pbuf);
 				goto bailout;
 			}
@@ -193,7 +192,7 @@ static int shmem_is_ok(int line)
 
 	return 1;
 
- bailout:
+bailout:
 	ccprintf("Line %d, counter %d. The list has been corrupted, "
 		 "total size %d, running size %d\n",
 		 line, counter, total_size, running_size);
@@ -207,7 +206,7 @@ static int shmem_is_ok(int line)
  */
 static uint32_t test_map;
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	int index;
 	const int shmem_size = shared_mem_size();
@@ -229,8 +228,7 @@ void run_test(int argc, char **argv)
 			if (test_map & ~ALL_PATHS_MASK) {
 				ccprintf("Unexpected mask bits set: %x"
 					 ", counter %d\n",
-					 test_map & ~ALL_PATHS_MASK,
-					 counter);
+					 test_map & ~ALL_PATHS_MASK, counter);
 				test_fail();
 				return;
 			}
@@ -253,7 +251,7 @@ void run_test(int argc, char **argv)
 				return;
 			}
 		} else {
-			size_t alloc_size = r_data % (shmem_size);
+			size_t alloc_size = r_data % (shmem_size / 2);
 
 			/*
 			 * If the allocation entry is empty - allocate a
@@ -261,7 +259,7 @@ void run_test(int argc, char **argv)
 			 */
 			if (shared_mem_acquire(alloc_size, &shptr) ==
 			    EC_SUCCESS) {
-				allocations[index].buf = (void *) shptr;
+				allocations[index].buf = (void *)shptr;
 				allocations[index].buffer_size = alloc_size;
 
 				/*
@@ -269,8 +267,8 @@ void run_test(int argc, char **argv)
 				 * modified.
 				 */
 				while (alloc_size--)
-					shptr[alloc_size] =
-					shptr[alloc_size] ^ 0xff;
+					shptr[alloc_size] = shptr[alloc_size] ^
+							    0xff;
 
 				if (!shmem_is_ok(__LINE__)) {
 					test_fail();
@@ -294,8 +292,8 @@ void run_test(int argc, char **argv)
 			}
 		}
 
-	ccprintf("Did not pass all paths, map %x != %x\n",
-		 test_map, ALL_PATHS_MASK);
+	ccprintf("Did not pass all paths, map %x != %x\n", test_map,
+		 ALL_PATHS_MASK);
 	test_fail();
 }
 
diff --git a/test/shmalloc.tasklist b/test/shmalloc.tasklist
index a8ef01a489..1413e373b1 100644
--- a/test/shmalloc.tasklist
+++ b/test/shmalloc.tasklist
@@ -1,5 +1,5 @@
 /*
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/static_if.c b/test/static_if.c
index f70f7d30c3..9e8b9db465 100644
--- a/test/static_if.c
+++ b/test/static_if.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -39,7 +39,7 @@ static int test_static_if_unused_no_fail(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/static_if.tasklist b/test/static_if.tasklist
index 5ffe662d01..2d4595f76a 100644
--- a/test/static_if.tasklist
+++ b/test/static_if.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/static_if_error.c b/test/static_if_error.c
index 65882b3bbd..99765ece99 100644
--- a/test/static_if_error.c
+++ b/test/static_if_error.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,7 +24,7 @@
 /* This is intended to cause a compilation error. */
 TEST_MACRO(CONFIG_FOO) __maybe_unused int foo;
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/static_if_error.sh b/test/static_if_error.sh
index efc7cd3e1e..ef17780f4c 100644
--- a/test/static_if_error.sh
+++ b/test/static_if_error.sh
@@ -1,5 +1,5 @@
 #!/bin/bash -e
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/test/static_if_error.tasklist b/test/static_if_error.tasklist
index 5ffe662d01..2d4595f76a 100644
--- a/test/static_if_error.tasklist
+++ b/test/static_if_error.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/std_vector.cc b/test/std_vector.cc
new file mode 100644
index 0000000000..c4ec6108fe
--- /dev/null
+++ b/test/std_vector.cc
@@ -0,0 +1,158 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Basic test of std::vector and dynamic memory allocation.
+ */
+
+#include <array>
+#include <vector>
+
+extern "C" {
+#include "common.h"
+#include "console.h"
+#include "test_util.h"
+}
+
+test_static int stack_init_elements()
+{
+	std::vector<int32_t> vec{ 10, 11, 12, 13, 14 };
+
+	TEST_EQ(static_cast<int32_t>(vec.size()), 5, "%d");
+	TEST_EQ(vec[0], 10, "%d");
+	TEST_EQ(vec[1], 11, "%d");
+	TEST_EQ(vec[2], 12, "%d");
+	TEST_EQ(vec[3], 13, "%d");
+	TEST_EQ(vec[4], 14, "%d");
+
+	return EC_SUCCESS;
+}
+
+test_static int static_init_elements()
+{
+	static std::vector<int32_t> vec{ 20, 21, 22, 23, 24 };
+
+	TEST_EQ(static_cast<int32_t>(vec.size()), 5, "%d");
+	TEST_EQ(vec[0], 20, "%d");
+	TEST_EQ(vec[1], 21, "%d");
+	TEST_EQ(vec[2], 22, "%d");
+	TEST_EQ(vec[3], 23, "%d");
+	TEST_EQ(vec[4], 24, "%d");
+
+	return EC_SUCCESS;
+}
+
+std::vector<int32_t> global_vec{ 30, 31, 32, 33, 34 };
+test_static int global_init_elements()
+{
+	TEST_EQ(static_cast<int32_t>(global_vec.size()), 5, "%d");
+	TEST_EQ(global_vec[0], 30, "%d");
+	TEST_EQ(global_vec[1], 31, "%d");
+	TEST_EQ(global_vec[2], 32, "%d");
+	TEST_EQ(global_vec[3], 33, "%d");
+	TEST_EQ(global_vec[4], 34, "%d");
+
+	return EC_SUCCESS;
+}
+
+test_static int push_back_elements()
+{
+	std::vector<int32_t> vec;
+
+	vec.push_back(0);
+	vec.push_back(1);
+	vec.push_back(2);
+	vec.push_back(3);
+
+	TEST_EQ(static_cast<int32_t>(vec.size()), 4, "%d");
+	TEST_EQ(vec[0], 0, "%d");
+	TEST_EQ(vec[1], 1, "%d");
+	TEST_EQ(vec[2], 2, "%d");
+	TEST_EQ(vec[3], 3, "%d");
+
+	return EC_SUCCESS;
+}
+
+test_static int fill_one_vector()
+{
+	// This test allocates 64kB of memory in total in a single std::vector
+	constexpr int num_elements = 16 * 1024;
+	std::vector<int32_t> vec;
+
+	for (int i = 0; i < num_elements; ++i)
+		vec.push_back(i);
+
+	TEST_EQ(static_cast<int>(vec.size()), num_elements, "%d");
+	for (int i = 0; i < num_elements; ++i) {
+		TEST_ASSERT(vec[i] == i);
+		// Using TEST_EQ floods the console and trigger the watchdog
+		// TEST_EQ(vec[i], i, "%d");
+		// cflush();
+	}
+
+	return EC_SUCCESS;
+}
+
+test_static int fill_multiple_vectors()
+{
+	// This test allocates 64kB of memory in total split in 8 std::vectors
+	constexpr int num_elements = 2 * 1024;
+	std::array<std::vector<int32_t>, 8> vecs;
+
+	for (int i = 0; i < num_elements; ++i)
+		for (auto &vec : vecs)
+			vec.push_back(i);
+
+	for (auto &vec : vecs) {
+		TEST_EQ(static_cast<int>(vec.size()), num_elements, "%d");
+		for (int i = 0; i < num_elements; ++i) {
+			TEST_ASSERT(vec[i] == i);
+		}
+	}
+
+	return EC_SUCCESS;
+}
+
+test_static int create_and_destroy_two_vectors()
+{
+	// This allocates 64kB of memory twice.
+	// The first vector is declared in a local scope and the memory is
+	// free'd at the end of the block.
+	constexpr int num_elements = 16 * 1024;
+	{
+		std::vector<int32_t> vec;
+		for (int i = 0; i < num_elements; ++i)
+			vec.push_back(i);
+
+		TEST_EQ(static_cast<int>(vec.size()), num_elements, "%d");
+		for (int i = 0; i < num_elements; ++i) {
+			TEST_ASSERT(vec[i] == i);
+		}
+	}
+
+	std::vector<int32_t> vec;
+	for (int i = 0; i < num_elements; ++i)
+		vec.push_back(i);
+
+	TEST_EQ(static_cast<int>(vec.size()), num_elements, "%d");
+	for (int i = 0; i < num_elements; ++i) {
+		TEST_ASSERT(vec[i] == i);
+	}
+
+	return EC_SUCCESS;
+}
+
+extern "C" void run_test(int argc, const char **argv)
+{
+	test_reset();
+
+	RUN_TEST(stack_init_elements);
+	RUN_TEST(static_init_elements);
+	RUN_TEST(global_init_elements);
+	RUN_TEST(push_back_elements);
+	RUN_TEST(fill_one_vector);
+	RUN_TEST(fill_multiple_vectors);
+	RUN_TEST(create_and_destroy_two_vectors);
+
+	test_print_result();
+}
diff --git a/test/std_vector.tasklist b/test/std_vector.tasklist
new file mode 100644
index 0000000000..6d43377af5
--- /dev/null
+++ b/test/std_vector.tasklist
@@ -0,0 +1,9 @@
+/* Copyright 2022 The ChromiumOS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST
diff --git a/test/stdlib.c b/test/stdlib.c
new file mode 100644
index 0000000000..3034522c23
--- /dev/null
+++ b/test/stdlib.c
@@ -0,0 +1,518 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Test standard library functions.
+ */
+
+#include "common.h"
+#include "compiler.h"
+#include "console.h"
+#include "printf.h"
+#include "shared_mem.h"
+#include "system.h"
+#include "test_util.h"
+#include "timer.h"
+#include "util.h"
+
+#ifdef USE_BUILTIN_STDLIB
+static const bool use_builtin_stdlib = true;
+#else
+static const bool use_builtin_stdlib = false;
+#endif
+
+static int test_isalpha(void)
+{
+	TEST_ASSERT(isalpha('a'));
+	TEST_ASSERT(isalpha('z'));
+	TEST_ASSERT(isalpha('A'));
+	TEST_ASSERT(isalpha('Z'));
+	TEST_ASSERT(!isalpha('0'));
+	TEST_ASSERT(!isalpha('~'));
+	TEST_ASSERT(!isalpha(' '));
+	TEST_ASSERT(!isalpha('\0'));
+	TEST_ASSERT(!isalpha('\n'));
+	return EC_SUCCESS;
+}
+
+static int test_isprint(void)
+{
+	TEST_ASSERT(isprint('a'));
+	TEST_ASSERT(isprint('z'));
+	TEST_ASSERT(isprint('A'));
+	TEST_ASSERT(isprint('Z'));
+	TEST_ASSERT(isprint('0'));
+	TEST_ASSERT(isprint('~'));
+	TEST_ASSERT(isprint(' '));
+	TEST_ASSERT(!isprint('\0'));
+	TEST_ASSERT(!isprint('\n'));
+	return EC_SUCCESS;
+}
+
+static int test_strstr(void)
+{
+	const char s1[] = "abcde";
+
+	TEST_ASSERT(strstr(s1, "ab") == s1);
+	if (use_builtin_stdlib) {
+		/*
+		 * TODO(http://b/243192369): This is incorrect and should be
+		 * fixed.
+		 */
+		TEST_ASSERT(strstr(s1, "") == NULL);
+	} else {
+		/*
+		 * From the man page: If needle is the empty string, the return
+		 * value is always haystack itself.
+		 */
+		TEST_ASSERT(strstr(s1, "") == s1);
+	}
+	TEST_ASSERT(strstr("", "ab") == NULL);
+	TEST_ASSERT(strstr("", "x") == NULL);
+	TEST_ASSERT(strstr(s1, "de") == &s1[3]);
+	TEST_ASSERT(strstr(s1, "def") == NULL);
+
+	return EC_SUCCESS;
+}
+
+static int test_strtoull(void)
+{
+	char *e;
+
+	TEST_ASSERT(strtoull("10", &e, 0) == 10);
+	TEST_ASSERT(e && (*e == '\0'));
+	TEST_ASSERT(strtoull("010", &e, 0) == 8);
+	TEST_ASSERT(e && (*e == '\0'));
+	TEST_ASSERT(strtoull("+010", &e, 0) == 8);
+	TEST_ASSERT(e && (*e == '\0'));
+
+	if (use_builtin_stdlib) {
+		/*
+		 * TODO(http://b/243192369): This is incorrect and should be
+		 * fixed.
+		 */
+		TEST_ASSERT(strtoull("-010", &e, 0) == 0);
+		TEST_ASSERT(e && (*e == '-'));
+	} else {
+		/*
+		 * From the man page: The strtoull() function returns either
+		 * the result of the conversion or, if there was a leading
+		 * minus sign, the negation of the result of the conversion
+		 * represented as an unsigned value, unless the original
+		 * (nonnegated) value would overflow
+		 */
+		TEST_ASSERT(strtoull("-010", &e, 0) == 0xFFFFFFFFFFFFFFF8);
+	}
+
+	TEST_ASSERT(strtoull("0x1f z", &e, 0) == 31);
+	TEST_ASSERT(e && (*e == ' '));
+	TEST_ASSERT(strtoull("0X1f z", &e, 0) == 31);
+	TEST_ASSERT(e && (*e == ' '));
+	TEST_ASSERT(strtoull("10a", &e, 16) == 266);
+	TEST_ASSERT(e && (*e == '\0'));
+	TEST_ASSERT(strtoull("0x02C", &e, 16) == 44);
+	TEST_ASSERT(e && (*e == '\0'));
+	TEST_ASSERT(strtoull("+0x02C", &e, 16) == 44);
+	TEST_ASSERT(e && (*e == '\0'));
+
+	if (use_builtin_stdlib) {
+		/*
+		 * TODO(http://b/243192369): This is incorrect and should be
+		 * fixed.
+		 */
+		TEST_ASSERT(strtoull("-0x02C", &e, 16) == 0);
+		TEST_ASSERT(e && (*e == '-'));
+	} else {
+		TEST_ASSERT(strtoull("-0x02C", &e, 16) == 0xFFFFFFFFFFFFFFD4);
+	}
+
+	TEST_ASSERT(strtoull("0x02C", &e, 0) == 44);
+	TEST_ASSERT(e && (*e == '\0'));
+	TEST_ASSERT(strtoull("+0x02C", &e, 0) == 44);
+	TEST_ASSERT(e && (*e == '\0'));
+
+	if (use_builtin_stdlib) {
+		/*
+		 * TODO(http://b/243192369): This is incorrect and should be
+		 * fixed.
+		 */
+		TEST_ASSERT(strtoull("-0x02C", &e, 0) == 0);
+		TEST_ASSERT(e && (*e == '-'));
+	} else {
+		TEST_ASSERT(strtoull("-0x02C", &e, 0) == 0xFFFFFFFFFFFFFFD4);
+	}
+
+	TEST_ASSERT(strtoull("0X02C", &e, 16) == 44);
+	TEST_ASSERT(e && (*e == '\0'));
+	TEST_ASSERT(strtoull("+0X02C", &e, 16) == 44);
+	TEST_ASSERT(e && (*e == '\0'));
+
+	if (use_builtin_stdlib) {
+		/*
+		 * TODO(http://b/243192369): This is incorrect and should be
+		 * fixed.
+		 */
+		TEST_ASSERT(strtoull("-0X02C", &e, 16) == 0);
+		TEST_ASSERT(e && (*e == '-'));
+	} else {
+		TEST_ASSERT(strtoull("-0X02C", &e, 16) == 0xFFFFFFFFFFFFFFD4);
+	}
+
+	TEST_ASSERT(strtoull("0X02C", &e, 0) == 44);
+	TEST_ASSERT(e && (*e == '\0'));
+	TEST_ASSERT(strtoull("+0X02C", &e, 0) == 44);
+	TEST_ASSERT(e && (*e == '\0'));
+
+	if (use_builtin_stdlib) {
+		/*
+		 * TODO(http://b/243192369): This is incorrect and should be
+		 * fixed.
+		 */
+		TEST_ASSERT(strtoull("-0X02C", &e, 0) == 0);
+		TEST_ASSERT(e && (*e == '-'));
+	} else {
+		TEST_ASSERT(strtoull("-0X02C", &e, 0) == 0xFFFFFFFFFFFFFFD4);
+	}
+
+	if (use_builtin_stdlib) {
+		/*
+		 * TODO(http://b/243192369): This is incorrect and should be
+		 * fixed.
+		 */
+		TEST_ASSERT(strtoull("   -12", &e, 0) == 0);
+		TEST_ASSERT(e && (*e == '-'));
+	} else {
+		TEST_ASSERT(strtoull("   -12", &e, 0) == 0xFFFFFFFFFFFFFFF4);
+	}
+
+	TEST_ASSERT(strtoull("!", &e, 0) == 0);
+	TEST_ASSERT(e && (*e == '!'));
+
+	TEST_ASSERT(strtoull("+!", &e, 0) == 0);
+	if (use_builtin_stdlib) {
+		/*
+		 * TODO(http://b/243192369): This is incorrect and should be
+		 * fixed.
+		 */
+		TEST_ASSERT(e && (*e == '!'));
+	} else {
+		TEST_ASSERT(e && (*e == '+'));
+	}
+
+	TEST_ASSERT(strtoull("+0!", &e, 0) == 0);
+	TEST_ASSERT(e && (*e == '!'));
+
+	TEST_ASSERT(strtoull("+0x!", &e, 0) == 0);
+	if (use_builtin_stdlib) {
+		TEST_ASSERT(e && (*e == '!'));
+	} else {
+		if (IS_ENABLED(EMU_BUILD))
+			TEST_ASSERT(e && (*e == 'x'));
+		else
+			TEST_ASSERT(e && (*e == '+'));
+	}
+
+	TEST_ASSERT(strtoull("+0X!", &e, 0) == 0);
+	if (use_builtin_stdlib) {
+		TEST_ASSERT(e && (*e == '!'));
+	} else {
+		if (IS_ENABLED(EMU_BUILD))
+			TEST_ASSERT(e && (*e == 'X'));
+		else
+			TEST_ASSERT(e && (*e == '+'));
+	}
+
+	return EC_SUCCESS;
+}
+
+static int test_strncpy(void)
+{
+	char dest[10];
+
+	strncpy(dest, "test", 10);
+	TEST_ASSERT_ARRAY_EQ("test", dest, 5);
+	strncpy(dest, "12345", 6);
+	TEST_ASSERT_ARRAY_EQ("12345", dest, 6);
+	/*
+	 * gcc complains:
+	 * error: ‘__builtin_strncpy’ output truncated copying 10 bytes from a
+	 * string of length 12 [-Werror=stringop-truncation]
+	 */
+	DISABLE_GCC_WARNING("-Wstringop-truncation");
+	strncpy(dest, "testtesttest", 10);
+	ENABLE_GCC_WARNING("-Wstringop-truncation");
+	TEST_ASSERT_ARRAY_EQ("testtestte", dest, 10);
+
+	return EC_SUCCESS;
+}
+
+static int test_strncmp(void)
+{
+	TEST_ASSERT(strncmp("123", "123", 8) == 0);
+	TEST_ASSERT(strncmp("789", "456", 8) > 0);
+	TEST_ASSERT(strncmp("abc", "abd", 4) < 0);
+	TEST_ASSERT(strncmp("abc", "abd", 2) == 0);
+	return EC_SUCCESS;
+}
+
+static int test_strlen(void)
+{
+	TEST_ASSERT(strlen("this is a string") == 16);
+	return EC_SUCCESS;
+}
+
+static int test_strnlen(void)
+{
+	TEST_ASSERT(strnlen("this is a string", 17) == 16);
+	TEST_ASSERT(strnlen("this is a string", 16) == 16);
+	TEST_ASSERT(strnlen("this is a string", 5) == 5);
+
+	return EC_SUCCESS;
+}
+
+static int test_strcasecmp(void)
+{
+	TEST_ASSERT(strcasecmp("test string", "TEST strIng") == 0);
+	TEST_ASSERT(strcasecmp("test123!@#", "TesT123!@#") == 0);
+	TEST_ASSERT(strcasecmp("lower", "UPPER") != 0);
+	return EC_SUCCESS;
+}
+
+static int test_strncasecmp(void)
+{
+	TEST_ASSERT(strncasecmp("test string", "TEST str", 4) == 0);
+	TEST_ASSERT(strncasecmp("test string", "TEST str", 8) == 0);
+	TEST_ASSERT(strncasecmp("test123!@#", "TesT321!@#", 5) != 0);
+	TEST_ASSERT(strncasecmp("test123!@#", "TesT321!@#", 4) == 0);
+	TEST_ASSERT(strncasecmp("1test123!@#", "1TesT321!@#", 5) == 0);
+	TEST_ASSERT(strncasecmp("1test123", "teststr", 0) == 0);
+	return EC_SUCCESS;
+}
+
+static int test_atoi(void)
+{
+	TEST_ASSERT(atoi("  901") == 901);
+	TEST_ASSERT(atoi("-12c") == -12);
+	TEST_ASSERT(atoi("   0  ") == 0);
+	TEST_ASSERT(atoi("\t111") == 111);
+	return EC_SUCCESS;
+}
+
+static int test_snprintf(void)
+{
+	char buffer[32];
+
+	TEST_ASSERT(snprintf(buffer, sizeof(buffer), "%u", 1234) == 4);
+	TEST_ASSERT(strncmp(buffer, "1234", sizeof(buffer)) == 0);
+	return EC_SUCCESS;
+}
+
+static int test_strcspn(void)
+{
+	const char str1[] = "abc";
+	const char str2[] = "This is a string\nwith newlines!";
+
+	TEST_EQ(strcspn(str1, "a"), (size_t)0, "%zu");
+	TEST_EQ(strcspn(str1, "b"), (size_t)1, "%zu");
+	TEST_EQ(strcspn(str1, "c"), (size_t)2, "%zu");
+	TEST_EQ(strcspn(str1, "ccc"), (size_t)2, "%zu");
+	TEST_EQ(strcspn(str1, "cba"), (size_t)0, "%zu");
+	TEST_EQ(strcspn(str1, "cb"), (size_t)1, "%zu");
+	TEST_EQ(strcspn(str1, "bc"), (size_t)1, "%zu");
+	TEST_EQ(strcspn(str1, "cbc"), (size_t)1, "%zu");
+	TEST_EQ(strcspn(str1, "z"), strlen(str1), "%zu");
+	TEST_EQ(strcspn(str1, "xyz"), strlen(str1), "%zu");
+	TEST_EQ(strcspn(str1, ""), strlen(str1), "%zu");
+
+	TEST_EQ(strcspn(str2, " "), (size_t)4, "%zu");
+	TEST_EQ(strcspn(str2, "\n"), (size_t)16, "%zu");
+	TEST_EQ(strcspn(str2, "\n "), (size_t)4, "%zu");
+	TEST_EQ(strcspn(str2, "!"), strlen(str2) - 1, "%zu");
+	TEST_EQ(strcspn(str2, "z"), strlen(str2), "%zu");
+	TEST_EQ(strcspn(str2, "z!"), strlen(str2) - 1, "%zu");
+
+	return EC_SUCCESS;
+}
+
+static int test_memmove(void)
+{
+	int i;
+	timestamp_t t0, t1, t2, t3;
+	char *buf;
+	const int buf_size = 1000;
+	const int len = 400;
+	const int iteration = 1000;
+
+	TEST_ASSERT(shared_mem_acquire(buf_size, &buf) == EC_SUCCESS);
+
+	for (i = 0; i < len; ++i)
+		buf[i] = i & 0x7f;
+	for (i = len; i < buf_size; ++i)
+		buf[i] = 0;
+
+	t0 = get_time();
+	for (i = 0; i < iteration; ++i)
+		memmove(buf + 101, buf, len); /* unaligned */
+	t1 = get_time();
+	TEST_ASSERT_ARRAY_EQ(buf + 101, buf, len);
+	ccprintf(" (speed gain: %" PRId64 " ->", t1.val - t0.val);
+
+	t2 = get_time();
+	for (i = 0; i < iteration; ++i)
+		memmove(buf + 100, buf, len); /* aligned */
+	t3 = get_time();
+	ccprintf(" %" PRId64 " us) ", t3.val - t2.val);
+	TEST_ASSERT_ARRAY_EQ(buf + 100, buf, len);
+
+	if (!IS_ENABLED(EMU_BUILD) && use_builtin_stdlib)
+		TEST_ASSERT((t1.val - t0.val) > (t3.val - t2.val));
+
+	/* Test small moves */
+	memmove(buf + 1, buf, 1);
+	TEST_ASSERT_ARRAY_EQ(buf + 1, buf, 1);
+	memmove(buf + 5, buf, 4);
+	memmove(buf + 1, buf, 4);
+	TEST_ASSERT_ARRAY_EQ(buf + 1, buf + 5, 4);
+
+	shared_mem_release(buf);
+	return EC_SUCCESS;
+}
+
+static int test_memcpy(void)
+{
+	int i;
+	timestamp_t t0, t1, t2, t3;
+	char *buf;
+	const int buf_size = 1000;
+	const int len = 400;
+	const int dest_offset = 500;
+	const int iteration = 1000;
+
+	TEST_ASSERT(shared_mem_acquire(buf_size, &buf) == EC_SUCCESS);
+
+	for (i = 0; i < len; ++i)
+		buf[i] = i & 0x7f;
+	for (i = len; i < buf_size; ++i)
+		buf[i] = 0;
+
+	t0 = get_time();
+	for (i = 0; i < iteration; ++i)
+		memcpy(buf + dest_offset + 1, buf, len); /* unaligned */
+	t1 = get_time();
+	TEST_ASSERT_ARRAY_EQ(buf + dest_offset + 1, buf, len);
+	ccprintf(" (speed gain: %" PRId64 " ->", t1.val - t0.val);
+
+	t2 = get_time();
+	for (i = 0; i < iteration; ++i)
+		memcpy(buf + dest_offset, buf, len); /* aligned */
+	t3 = get_time();
+	ccprintf(" %" PRId64 " us) ", t3.val - t2.val);
+	TEST_ASSERT_ARRAY_EQ(buf + dest_offset, buf, len);
+
+	if (!IS_ENABLED(EMU_BUILD))
+		TEST_ASSERT((t1.val - t0.val) > (t3.val - t2.val));
+
+	memcpy(buf + dest_offset + 1, buf + 1, len - 1);
+	TEST_ASSERT_ARRAY_EQ(buf + dest_offset + 1, buf + 1, len - 1);
+
+	/* Test small copies */
+	memcpy(buf + dest_offset, buf, 1);
+	TEST_ASSERT_ARRAY_EQ(buf + dest_offset, buf, 1);
+	memcpy(buf + dest_offset, buf, 4);
+	TEST_ASSERT_ARRAY_EQ(buf + dest_offset, buf, 4);
+	memcpy(buf + dest_offset + 1, buf, 1);
+	TEST_ASSERT_ARRAY_EQ(buf + dest_offset + 1, buf, 1);
+	memcpy(buf + dest_offset + 1, buf, 4);
+	TEST_ASSERT_ARRAY_EQ(buf + dest_offset + 1, buf, 4);
+
+	shared_mem_release(buf);
+	return EC_SUCCESS;
+}
+
+/* Plain memset, used as a reference to measure speed gain */
+static void *dumb_memset(void *dest, int c, int len)
+{
+	char *d = (char *)dest;
+	while (len > 0) {
+		*(d++) = c;
+		len--;
+	}
+	return dest;
+}
+
+static int test_memset(void)
+{
+	int i;
+	timestamp_t t0, t1, t2, t3;
+	char *buf;
+	const int buf_size = 1000;
+	const int len = 400;
+	const int iteration = 1000;
+
+	TEST_ASSERT(shared_mem_acquire(buf_size, &buf) == EC_SUCCESS);
+
+	t0 = get_time();
+	for (i = 0; i < iteration; ++i)
+		dumb_memset(buf, 1, len);
+	t1 = get_time();
+	TEST_ASSERT_MEMSET(buf, (char)1, len);
+	ccprintf(" (speed gain: %" PRId64 " ->", t1.val - t0.val);
+
+	t2 = get_time();
+	for (i = 0; i < iteration; ++i)
+		memset(buf, 1, len);
+	t3 = get_time();
+	TEST_ASSERT_MEMSET(buf, (char)1, len);
+	ccprintf(" %" PRId64 " us) ", t3.val - t2.val);
+
+	if (!IS_ENABLED(EMU_BUILD))
+		TEST_ASSERT((t1.val - t0.val) > (t3.val - t2.val));
+
+	memset(buf, 128, len);
+	TEST_ASSERT_MEMSET(buf, (char)128, len);
+
+	memset(buf, -2, len);
+	TEST_ASSERT_MEMSET(buf, (char)-2, len);
+
+	memset(buf + 1, 1, len - 2);
+	TEST_ASSERT_MEMSET(buf + 1, (char)1, len - 2);
+
+	shared_mem_release(buf);
+	return EC_SUCCESS;
+}
+
+static int test_memchr(void)
+{
+	char *buf = "1234";
+
+	TEST_ASSERT(memchr("123567890", '4', 8) == NULL);
+	TEST_ASSERT(memchr("123", '3', 2) == NULL);
+	TEST_ASSERT(memchr(buf, '3', 4) == buf + 2);
+	TEST_ASSERT(memchr(buf, '4', 4) == buf + 3);
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
+{
+	test_reset();
+
+	RUN_TEST(test_isalpha);
+	RUN_TEST(test_isprint);
+	RUN_TEST(test_strstr);
+	RUN_TEST(test_strtoull);
+	RUN_TEST(test_strncpy);
+	RUN_TEST(test_strncmp);
+	RUN_TEST(test_strlen);
+	RUN_TEST(test_strnlen);
+	RUN_TEST(test_strcasecmp);
+	RUN_TEST(test_strncasecmp);
+	RUN_TEST(test_atoi);
+	RUN_TEST(test_snprintf);
+	RUN_TEST(test_strcspn);
+	RUN_TEST(test_memmove);
+	RUN_TEST(test_memcpy);
+	RUN_TEST(test_memset);
+	RUN_TEST(test_memchr);
+
+	test_print_result();
+}
diff --git a/test/stdlib.tasklist b/test/stdlib.tasklist
new file mode 100644
index 0000000000..1154b1ae8b
--- /dev/null
+++ b/test/stdlib.tasklist
@@ -0,0 +1,9 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST  /* No test task */
diff --git a/test/stillness_detector.c b/test/stillness_detector.c
index e881525491..2e82075e5e 100644
--- a/test/stillness_detector.c
+++ b/test/stillness_detector.c
@@ -1,12 +1,13 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include "stillness_detector.h"
 #include "motion_sense.h"
+#include "stillness_detector.h"
 #include "test_util.h"
 #include "timer.h"
+
 #include <stdio.h>
 
 /*****************************************************************************/
@@ -35,8 +36,8 @@ static int test_not_still_short_window(void)
 	int i;
 
 	for (i = 0; i < 6; ++i)
-		TEST_ASSERT(!still_det_update(&det, i * 100 * MSEC,
-					      0.0f, 0.0f, 0.0f));
+		TEST_ASSERT(!still_det_update(&det, i * 100 * MSEC, 0.0f, 0.0f,
+					      0.0f));
 
 	return EC_SUCCESS;
 }
@@ -47,8 +48,8 @@ static int test_not_still_long_window(void)
 	int i;
 
 	for (i = 0; i < 5; ++i)
-		TEST_ASSERT(!still_det_update(&det, i * 300 * MSEC,
-					      0.0f, 0.0f, 0.0f));
+		TEST_ASSERT(!still_det_update(&det, i * 300 * MSEC, 0.0f, 0.0f,
+					      0.0f));
 
 	return EC_SUCCESS;
 }
@@ -59,8 +60,8 @@ static int test_not_still_not_enough_samples(void)
 	int i;
 
 	for (i = 0; i < 4; ++i)
-		TEST_ASSERT(!still_det_update(&det, i * 200 * MSEC,
-					      0.0f, 0.0f, 0.0f));
+		TEST_ASSERT(!still_det_update(&det, i * 200 * MSEC, 0.0f, 0.0f,
+					      0.0f));
 
 	return EC_SUCCESS;
 }
@@ -71,9 +72,8 @@ static int test_is_still_all_axes(void)
 	int i;
 
 	for (i = 0; i < 9; ++i) {
-		int result = still_det_update(&det, i * 100 * MSEC,
-					      i * 0.001f, i * 0.001f,
-					      i * 0.001f);
+		int result = still_det_update(&det, i * 100 * MSEC, i * 0.001f,
+					      i * 0.001f, i * 0.001f);
 
 		TEST_EQ(result, i == 8 ? 1 : 0, "%d");
 	}
@@ -90,9 +90,8 @@ static int test_not_still_one_axis(void)
 	int i;
 
 	for (i = 0; i < 9; ++i) {
-		TEST_ASSERT(!still_det_update(&det, i * 100 * MSEC,
-					      i * 0.001f, i * 0.001f,
-					      i * 0.01f));
+		TEST_ASSERT(!still_det_update(&det, i * 100 * MSEC, i * 0.001f,
+					      i * 0.001f, i * 0.01f));
 	}
 
 	return EC_SUCCESS;
@@ -104,15 +103,13 @@ static int test_resets(void)
 	int i;
 
 	for (i = 0; i < 9; ++i) {
-		TEST_ASSERT(!still_det_update(&det, i * 100 * MSEC,
-					      i * 0.001f, i * 0.001f,
-					      i * 0.01f));
+		TEST_ASSERT(!still_det_update(&det, i * 100 * MSEC, i * 0.001f,
+					      i * 0.001f, i * 0.01f));
 	}
 
 	for (i = 0; i < 9; ++i) {
-		int result = still_det_update(&det, i * 100 * MSEC,
-					      i * 0.001f, i * 0.001f,
-					      i * 0.001f);
+		int result = still_det_update(&det, i * 100 * MSEC, i * 0.001f,
+					      i * 0.001f, i * 0.001f);
 
 		TEST_EQ(result, i == 8 ? 1 : 0, "%d");
 	}
@@ -123,7 +120,7 @@ static int test_resets(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
@@ -135,5 +132,7 @@ void run_test(int argc, char **argv)
 	RUN_TEST(test_not_still_one_axis);
 	RUN_TEST(test_resets);
 
+	/* Wait for all background tasks to start. */
+	sleep(4);
 	test_print_result();
 }
diff --git a/test/stillness_detector.tasklist b/test/stillness_detector.tasklist
index 5ffe662d01..2d4595f76a 100644
--- a/test/stillness_detector.tasklist
+++ b/test/stillness_detector.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/stm32f_rtc.c b/test/stm32f_rtc.c
index 7eb1930892..b055398b28 100644
--- a/test/stm32f_rtc.c
+++ b/test/stm32f_rtc.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,14 +6,20 @@
 #include "clock-f.h"
 #include "test_util.h"
 
-static volatile uint32_t rtc_fired;
+static uint32_t rtc_fired;
 static struct rtc_time_reg rtc_irq;
 static const int rtc_delay_ms = 500;
 
+/*
+ * We will be testing that the RTC interrupt timestamp occurs
+ * within +/- delay_tol_us (tolerance) of the above rtc_delay_ms.
+ */
+static const int delay_tol_us = MSEC / 2;
+
 /* Override default RTC interrupt handler */
-void __rtc_alarm_irq(void)
+void rtc_alarm_irq(void)
 {
-	deprecated_atomic_add(&rtc_fired, 1);
+	atomic_add(&rtc_fired, 1);
 	reset_rtc_alarm(&rtc_irq);
 }
 
@@ -21,7 +27,6 @@ test_static int test_rtc_alarm(void)
 {
 	struct rtc_time_reg rtc;
 	uint32_t rtc_diff_us;
-	uint32_t rtc_diff_ms;
 	const int delay_us = rtc_delay_ms * MSEC;
 
 	set_rtc_alarm(0, delay_us, &rtc, 0);
@@ -29,24 +34,54 @@ test_static int test_rtc_alarm(void)
 	msleep(2 * rtc_delay_ms);
 
 	/* Make sure the interrupt fired exactly once. */
-	TEST_EQ(1, deprecated_atomic_read_clear(&rtc_fired), "%d");
+	TEST_EQ(1, atomic_clear(&rtc_fired), "%d");
 
 	rtc_diff_us = get_rtc_diff(&rtc, &rtc_irq);
 
-	ccprintf("rtc_diff_us: %d\n", rtc_diff_us);
+	ccprintf("Target delay was %dus\n", delay_us);
+	ccprintf("Actual delay was %dus\n", rtc_diff_us);
+	ccprintf("The delays are expected to be within +/- %dus\n", MSEC / 2);
 
-	/* Assume we'll always fire within 1 ms. May need to be adjusted if
+	/* Assume we'll always fire within 500us. May need to be adjusted if
 	 * this doesn't hold.
+	 *
+	 * delay_us-delay_tol_us < rtc_diff_us < delay_us+delay_tol_us
 	 */
-	rtc_diff_ms = rtc_diff_us / MSEC;
-	TEST_EQ(rtc_diff_ms, rtc_delay_ms, "%d");
+	TEST_LT(delay_us - delay_tol_us, rtc_diff_us, "%dus");
+	TEST_LT(rtc_diff_us, delay_us + delay_tol_us, "%dus");
 
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+static const int rtc_match_delay_iterations = 5000;
+
+test_static int test_rtc_match_delay(void)
 {
+	struct rtc_time_reg rtc;
+	int i;
+
+	atomic_clear(&rtc_fired);
+	for (i = 0; i < rtc_match_delay_iterations; i++) {
+		set_rtc_alarm(0, SET_RTC_MATCH_DELAY, &rtc, 0);
+		usleep(2 * SET_RTC_MATCH_DELAY);
+	}
+
+	ccprintf("Expected number of RTC alarm interrupts %d\n",
+		 rtc_match_delay_iterations);
+	ccprintf("Actual number of RTC alarm interrupts %d\n", rtc_fired);
+
+	/* Make sure each set_rtc_alarm() generated the interrupt. */
+	TEST_EQ(rtc_match_delay_iterations, atomic_clear(&rtc_fired), "%d");
+
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
+{
+	test_reset();
+
 	RUN_TEST(test_rtc_alarm);
+	RUN_TEST(test_rtc_match_delay);
 
 	test_print_result();
 }
diff --git a/test/stm32f_rtc.tasklist b/test/stm32f_rtc.tasklist
index 51734f058d..a1f1a94e2d 100644
--- a/test/stm32f_rtc.tasklist
+++ b/test/stm32f_rtc.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/stress.c b/test/stress.c
index d975e87a84..f497644602 100644
--- a/test/stress.c
+++ b/test/stress.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -46,8 +46,7 @@ struct i2c_test_param_t {
 /* period between 500us and 32ms */
 #define RAND_US() (((prng_no_seed() % 64) + 1) * 500)
 
-static int stress(const char *name,
-		  int (*test_routine)(void),
+static int stress(const char *name, int (*test_routine)(void),
 		  const int iteration)
 {
 	int i;
@@ -65,42 +64,43 @@ static int stress(const char *name,
 	return EC_SUCCESS;
 }
 
-#define RUN_STRESS_TEST(n, r, iter) \
-	do { \
+#define RUN_STRESS_TEST(n, r, iter)                     \
+	do {                                            \
 		if (stress(n, r, iter) != EC_SUCCESS) { \
-			ccputs("Fail\n"); \
-			error_count++; \
-		} \
+			ccputs("Fail\n");               \
+			error_count++;                  \
+		}                                       \
 	} while (0)
 
 /*****************************************************************************/
 /* Tests */
-#ifdef CONFIG_I2C_MASTER
+#ifdef CONFIG_I2C_CONTROLLER
 static int test_i2c(void)
 {
 	int res = EC_ERROR_UNKNOWN;
 	int mock_data;
 	struct i2c_test_param_t *param;
-	param = i2c_test_params + (prng_no_seed() % (sizeof(i2c_test_params) /
-				   sizeof(struct i2c_test_param_t)));
+	param = i2c_test_params +
+		(prng_no_seed() %
+		 (sizeof(i2c_test_params) / sizeof(struct i2c_test_param_t)));
 	if (param->width == 8 && param->data == -1)
-		res = i2c_read8(param->port, param->addr,
-				param->offset, &mock_data);
+		res = i2c_read8(param->port, param->addr, param->offset,
+				&mock_data);
 	else if (param->width == 8 && param->data >= 0)
-		res = i2c_write8(param->port, param->addr,
-				 param->offset, param->data);
+		res = i2c_write8(param->port, param->addr, param->offset,
+				 param->data);
 	else if (param->width == 16 && param->data == -1)
-		res = i2c_read16(param->port, param->addr,
-				 param->offset, &mock_data);
+		res = i2c_read16(param->port, param->addr, param->offset,
+				 &mock_data);
 	else if (param->width == 16 && param->data >= 0)
-		res = i2c_write16(param->port, param->addr,
-				  param->offset, param->data);
+		res = i2c_write16(param->port, param->addr, param->offset,
+				  param->data);
 	else if (param->width == 32 && param->data == -1)
-		res = i2c_read32(param->port, param->addr,
-				 param->offset, &mock_data);
+		res = i2c_read32(param->port, param->addr, param->offset,
+				 &mock_data);
 	else if (param->width == 32 && param->data >= 0)
-		res = i2c_write32(param->port, param->addr,
-				  param->offset, param->data);
+		res = i2c_write32(param->port, param->addr, param->offset,
+				  param->data);
 
 	return res;
 }
@@ -128,11 +128,11 @@ static int test_adc(void)
 }
 #endif
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
-#ifdef CONFIG_I2C_MASTER
+#ifdef CONFIG_I2C_CONTROLLER
 	RUN_STRESS_TEST("I2C Stress Test", test_i2c, I2C_TEST_ITERATION);
 #endif
 #ifdef CONFIG_ADC
diff --git a/test/stress.tasklist b/test/stress.tasklist
index da0ab6211a..100cb6b5bd 100644
--- a/test/stress.tasklist
+++ b/test/stress.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/system.c b/test/system.c
index 6874708cc7..d123bd5cee 100644
--- a/test/system.c
+++ b/test/system.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -13,8 +13,8 @@
 #include "timer.h"
 #include "util.h"
 
-#define TEST_STATE_STEP_2	(1 << 0)
-#define TEST_STATE_FAIL		(1 << 1)
+#define TEST_STATE_STEP_2 (1 << 0)
+#define TEST_STATE_FAIL (1 << 1)
 
 static int test_reboot_on_shutdown(void)
 {
@@ -29,9 +29,9 @@ static int test_reboot_on_shutdown(void)
 	params.cmd = EC_REBOOT_COLD;
 	params.flags = EC_REBOOT_FLAG_ON_AP_SHUTDOWN;
 
-	TEST_ASSERT(test_send_host_command(
-			EC_CMD_REBOOT_EC, 0, &params,
-			sizeof(params), NULL, 0) == EC_SUCCESS);
+	TEST_EQ(test_send_host_command(EC_CMD_REBOOT_EC, 0, &params,
+				       sizeof(params), NULL, 0),
+		EC_SUCCESS, "%d");
 
 	system_set_scratchpad(TEST_STATE_STEP_2);
 	test_chipset_off();
@@ -54,16 +54,16 @@ static int test_cancel_reboot(void)
 	params.cmd = EC_REBOOT_COLD;
 	params.flags = EC_REBOOT_FLAG_ON_AP_SHUTDOWN;
 
-	TEST_ASSERT(test_send_host_command(
-			EC_CMD_REBOOT_EC, 0, &params,
-			sizeof(params), NULL, 0) == EC_SUCCESS);
+	TEST_EQ(test_send_host_command(EC_CMD_REBOOT_EC, 0, &params,
+				       sizeof(params), NULL, 0),
+		EC_SUCCESS, "%d");
 
 	params.cmd = EC_REBOOT_CANCEL;
 	params.flags = 0;
 
-	TEST_ASSERT(test_send_host_command(
-			EC_CMD_REBOOT_EC, 0, &params,
-			sizeof(params), NULL, 0) == EC_SUCCESS);
+	TEST_EQ(test_send_host_command(EC_CMD_REBOOT_EC, 0, &params,
+				       sizeof(params), NULL, 0),
+		EC_SUCCESS, "%d");
 
 	test_chipset_off();
 	msleep(30);
@@ -92,9 +92,16 @@ static void fail_and_clean_up(void)
 	test_fail();
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
-	uint32_t state = system_get_scratchpad();
+	uint32_t state = 0;
+
+	/* The return value isn't checked here on purpose. The scratchpad file
+	 * may exist from a previous run or it may be in a clean state. A
+	 * previous run of this test should reset the scratchpad value to 0
+	 * regardless of the final result.
+	 */
+	system_get_scratchpad(&state);
 
 	test_reset();
 
diff --git a/test/system.tasklist b/test/system.tasklist
index 4e455a7ea3..6967ec1095 100644
--- a/test/system.tasklist
+++ b/test/system.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/system_is_locked.c b/test/system_is_locked.c
new file mode 100644
index 0000000000..0a517f1509
--- /dev/null
+++ b/test/system_is_locked.c
@@ -0,0 +1,128 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "flash.h"
+#include "string.h"
+#include "system.h"
+#include "task.h"
+#include "test_util.h"
+#include "write_protect.h"
+
+static bool write_protect_enabled;
+
+test_static int test_write_protect(void)
+{
+	TEST_EQ(write_protect_is_asserted(), write_protect_enabled, "%d");
+
+	return EC_SUCCESS;
+}
+
+test_static int test_ro_protection_enabled(void)
+{
+	TEST_BITS_SET(crec_flash_get_protect(), EC_FLASH_PROTECT_RO_NOW);
+
+	return EC_SUCCESS;
+}
+
+test_static int test_system_is_locked(void)
+{
+	if (!write_protect_is_asserted() ||
+	    (~crec_flash_get_protect() & EC_FLASH_PROTECT_RO_NOW))
+		TEST_EQ(system_is_locked(), 0, "%d");
+	else
+		TEST_EQ(system_is_locked(), 1, "%d");
+
+	return EC_SUCCESS;
+}
+
+static void print_usage(void)
+{
+	ccprintf("usage: runtest [wp_on|wp_off]\n");
+}
+
+void test_run_step(uint32_t state)
+{
+	/*
+	 * Step 1: Check if reported write protect and system_is_locked()
+	 * output is correct. Since RO protection is not enabled at this point
+	 * we expect system_is_locked() to return 0. If write protect is
+	 * enabled then attempt to enable RO protection.
+	 */
+	if (state & TEST_STATE_MASK(TEST_STATE_STEP_1)) {
+		RUN_TEST(test_write_protect);
+		RUN_TEST(test_system_is_locked);
+
+		if (test_get_error_count())
+			test_reboot_to_next_step(TEST_STATE_FAILED);
+		else if (write_protect_enabled) {
+			ccprintf("Request RO protection at boot\n");
+			crec_flash_set_protect(EC_FLASH_PROTECT_RO_AT_BOOT,
+					       EC_FLASH_PROTECT_RO_AT_BOOT);
+			test_reboot_to_next_step(TEST_STATE_STEP_2);
+		} else {
+			/* Write protect is disabled, nothing else to do */
+			test_reboot_to_next_step(TEST_STATE_PASSED);
+		}
+	}
+	/*
+	 * Step 2: Check if hardware write protect is enabled, RO protection
+	 * is enabled and system_is_locked() returns 1.
+	 */
+	else if (state & TEST_STATE_MASK(TEST_STATE_STEP_2)) {
+		/* Expect hardware write protect to be enabled */
+		write_protect_enabled = true;
+		RUN_TEST(test_write_protect);
+		RUN_TEST(test_ro_protection_enabled);
+		RUN_TEST(test_system_is_locked);
+		if (test_get_error_count())
+			test_reboot_to_next_step(TEST_STATE_FAILED);
+		else
+			test_reboot_to_next_step(TEST_STATE_PASSED);
+	}
+}
+
+int task_test(void *unused)
+{
+	test_run_multistep();
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
+{
+	test_reset();
+
+	if (IS_ENABLED(CONFIG_SYSTEM_UNLOCKED)) {
+		ccprintf("Please disable CONFIG_SYSTEM_UNLOCKED before "
+			 "running this test\n");
+		test_fail();
+		return;
+	}
+
+	if (argc < 2) {
+		print_usage();
+		test_fail();
+		return;
+	}
+
+	if (strncmp(argv[1], "wp_on", 5) == 0)
+		write_protect_enabled = true;
+	else if (strncmp(argv[1], "wp_off", 6) == 0) {
+		write_protect_enabled = false;
+		if (IS_ENABLED(CONFIG_WP_ALWAYS)) {
+			ccprintf("Hardware write protect always enabled. "
+				 "Please disable CONFIG_WP_ALWAYS before "
+				 "running this test\n");
+			test_fail();
+			return;
+		}
+	} else {
+		print_usage();
+		test_fail();
+		return;
+	}
+
+	msleep(30); /* Wait for TASK_ID_TEST to initialize */
+	task_wake(TASK_ID_TEST);
+}
diff --git a/test/system_is_locked.tasklist b/test/system_is_locked.tasklist
new file mode 100644
index 0000000000..273a9664c0
--- /dev/null
+++ b/test/system_is_locked.tasklist
@@ -0,0 +1,10 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST \
+  TASK_TEST(TEST, task_test, NULL, TASK_STACK_SIZE)
diff --git a/test/tablet_broken_sensor.c b/test/tablet_broken_sensor.c
new file mode 100644
index 0000000000..b98b4f194e
--- /dev/null
+++ b/test/tablet_broken_sensor.c
@@ -0,0 +1,232 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Test clamshell/tablet when the sensors are broken.
+ */
+
+#include "accelgyro.h"
+#include "common.h"
+#include "console.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "motion_common.h"
+#include "motion_sense.h"
+#include "tablet_mode.h"
+#include "test_util.h"
+#include "timer.h"
+#include "util.h"
+
+/*****************************************************************************/
+/* Mock functions */
+static int accel_init(struct motion_sensor_t *s)
+{
+	return EC_ERROR_UNKNOWN;
+}
+
+/* Only populate _init(), sensor stack should not touch the sensors on failure.
+ */
+const struct accelgyro_drv test_motion_sense = {
+	.init = accel_init,
+};
+
+struct motion_sensor_t motion_sensors[] = {
+	[BASE] = {
+		.name = "base",
+		.active_mask = SENSOR_ACTIVE_S0_S3_S5,
+		.chip = MOTIONSENSE_CHIP_LSM6DS0,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &test_motion_sense,
+		.rot_standard_ref = NULL,
+		.default_range = 2,
+	},
+	[LID] = {
+		.name = "lid",
+		.active_mask = SENSOR_ACTIVE_S0_S3_S5,
+		.chip = MOTIONSENSE_CHIP_KXCJ9,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &test_motion_sense,
+		.rot_standard_ref = NULL,
+		.default_range = 2,
+	},
+};
+unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+static int tablet_hook_count;
+/* Store value obtained by caller. */
+static int tablet_hook_value;
+
+static void tablet_mode_change_hook(void)
+{
+	tablet_hook_count++;
+	tablet_hook_value = tablet_get_mode();
+}
+DECLARE_HOOK(HOOK_TABLET_MODE_CHANGE, tablet_mode_change_hook,
+	     HOOK_PRIO_DEFAULT);
+
+void before_test(void)
+{
+	/* Make sure the device lid is in a consistent state (close). */
+	gpio_set_level(GPIO_TABLET_MODE_L, 1);
+	msleep(50);
+	gpio_set_level(GPIO_LID_OPEN, 0);
+	msleep(50);
+	tablet_hook_count = 1;
+}
+
+/*
+ * The device is in clamshell mode from before_test(),
+ * Go through GPIO transitions and observe the table mode state.
+ */
+test_static int test_start_lid_close(void)
+{
+	TEST_ASSERT(!tablet_get_mode());
+
+	/* Opening, No change. */
+	gpio_set_level(GPIO_LID_OPEN, 1);
+	msleep(50);
+	TEST_ASSERT(tablet_hook_count == 1);
+	TEST_ASSERT(!tablet_get_mode());
+
+	/* full 360, tablet mode. */
+	gpio_set_level(GPIO_TABLET_MODE_L, 0);
+	msleep(50);
+	TEST_ASSERT(tablet_hook_count == 2);
+	TEST_ASSERT(tablet_get_mode());
+
+	/* Going out of 360 mode, no change. */
+	gpio_set_level(GPIO_TABLET_MODE_L, 1);
+	msleep(50);
+	TEST_ASSERT(tablet_hook_count == 2);
+	TEST_ASSERT(tablet_get_mode());
+
+	/* Back to close. */
+	gpio_set_level(GPIO_LID_OPEN, 0);
+	msleep(50);
+	TEST_ASSERT(tablet_hook_count == 3);
+	TEST_ASSERT(!tablet_get_mode());
+
+	return EC_SUCCESS;
+}
+
+/*
+ * Put the device in tablet mode first.
+ * Reset the EC, keep the existing GPIO level.
+ * Verify the state is not forgotten when the EC starts in tablet mode after
+ * reset.
+ */
+test_static int test_start_tablet_mode(void)
+{
+	/* Go in tablet mode */
+	gpio_set_level(GPIO_LID_OPEN, 1);
+	gpio_set_level(GPIO_TABLET_MODE_L, 0);
+	msleep(50);
+	TEST_ASSERT(tablet_hook_count == 2);
+
+	/* Shutdown device */
+	hook_notify(HOOK_CHIPSET_SHUTDOWN);
+
+	msleep(50);
+	TEST_ASSERT(sensor_active == SENSOR_ACTIVE_S5);
+	TEST_ASSERT(tablet_hook_count == 2);
+	TEST_ASSERT(tablet_get_mode());
+
+	return EC_SUCCESS;
+}
+
+/*
+ * Put the device in tablet mode first.
+ * Do a fast transition from 0 degree to 360 degree:
+ * Observe the transition happens.
+ * then 360 degree to 0 degree.
+ * Observe the transition happens.
+ */
+test_static int test_fast_transition(void)
+{
+	TEST_ASSERT(!tablet_get_mode());
+
+	/* Go in tablet mode fast.*/
+	gpio_set_level(GPIO_LID_OPEN, 1);
+	gpio_set_level(GPIO_TABLET_MODE_L, 0);
+	msleep(50);
+	TEST_ASSERT(tablet_get_mode());
+	TEST_ASSERT(tablet_hook_count == 2);
+
+	/* Go in clamshell mode fast.*/
+	gpio_set_level(GPIO_LID_OPEN, 0);
+	gpio_set_level(GPIO_TABLET_MODE_L, 1);
+	msleep(50);
+	TEST_ASSERT(!tablet_get_mode());
+	TEST_ASSERT(tablet_hook_count == 3);
+
+	return EC_SUCCESS;
+}
+
+/*
+ * Simulate disabling the sensors from boad_init() - when
+ * the firmware can work for both clamsheel and convertible.
+ */
+test_static int test_disable_sensors_GMR_low(void)
+{
+	/* Assume lid is open */
+	gpio_set_level(GPIO_LID_OPEN, 1);
+	/* GMR is not stuffed, assume low. */
+	gpio_set_level(GPIO_TABLET_MODE_L, 0);
+	msleep(50);
+	TEST_ASSERT(tablet_hook_count == 2);
+	TEST_ASSERT(tablet_get_mode());
+	TEST_ASSERT(tablet_hook_value == tablet_get_mode());
+
+	/* Disable tablet mode deteciton.*/
+	gmr_tablet_switch_disable();
+	motion_sensor_count = 0;
+
+	/* We should not be in tablet mode. */
+	TEST_ASSERT(!tablet_get_mode());
+	TEST_ASSERT(tablet_hook_value == tablet_get_mode());
+
+	return EC_SUCCESS;
+}
+
+/*
+ * Simulate disabling the sensors from boad_init() - when
+ * the firmware can work for both clamsheel and convertible.
+ */
+test_static int test_disable_sensors_GMR_high(void)
+{
+	/* Assume lid is open */
+	gpio_set_level(GPIO_LID_OPEN, 1);
+	/* GMR is not stuffed, assume high. */
+	gpio_set_level(GPIO_TABLET_MODE_L, 1);
+	msleep(50);
+	TEST_ASSERT(tablet_hook_count == 1);
+	TEST_ASSERT(!tablet_get_mode());
+	TEST_ASSERT(tablet_hook_value == tablet_get_mode());
+
+	/* Disable tablet mode deteciton.*/
+	gmr_tablet_switch_disable();
+	motion_sensor_count = 0;
+
+	/* We should not be in tablet mode. */
+	TEST_ASSERT(!tablet_get_mode());
+	TEST_ASSERT(tablet_hook_value == tablet_get_mode());
+
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
+{
+	test_reset();
+
+	RUN_TEST(test_start_lid_close);
+	RUN_TEST(test_start_tablet_mode);
+	RUN_TEST(test_fast_transition);
+
+	RUN_TEST(test_disable_sensors_GMR_low);
+	RUN_TEST(test_disable_sensors_GMR_high);
+
+	test_print_result();
+}
diff --git a/test/tablet_broken_sensor.tasklist b/test/tablet_broken_sensor.tasklist
new file mode 100644
index 0000000000..04f8e3006d
--- /dev/null
+++ b/test/tablet_broken_sensor.tasklist
@@ -0,0 +1,10 @@
+/* Copyright 2013 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST  \
+  TASK_TEST(MOTIONSENSE, motion_sense_task, NULL, TASK_STACK_SIZE)
diff --git a/test/tablet_no_sensor.c b/test/tablet_no_sensor.c
new file mode 100644
index 0000000000..f6a3d16c11
--- /dev/null
+++ b/test/tablet_no_sensor.c
@@ -0,0 +1,105 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Test clamshell/tablet when Only the GMR sensor is driving the tablet mode:
+ * In that mode, tablet mode is entered only when the lid angle is 360 degree.
+ */
+
+#include "common.h"
+#include "console.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "tablet_mode.h"
+#include "test_util.h"
+#include "timer.h"
+#include "util.h"
+
+static int tablet_hook_count;
+
+static void tablet_mode_change_hook(void)
+{
+	tablet_hook_count++;
+}
+DECLARE_HOOK(HOOK_TABLET_MODE_CHANGE, tablet_mode_change_hook,
+	     HOOK_PRIO_DEFAULT);
+
+void before_test(void)
+{
+	/* Make sure the device lid is in a consistent state (close). */
+	gpio_set_level(GPIO_TABLET_MODE_L, 1);
+	msleep(50);
+	gpio_set_level(GPIO_LID_OPEN, 0);
+	msleep(50);
+	tablet_hook_count = 1;
+}
+
+/*
+ * The device is in clamshell mode from before_test,
+ * Go through GPIO transitions and observe the table mode state.
+ */
+test_static int test_start_lid_close(void)
+{
+	TEST_ASSERT(!tablet_get_mode());
+
+	/* Opening, No change. */
+	gpio_set_level(GPIO_LID_OPEN, 1);
+	msleep(50);
+	TEST_ASSERT(tablet_hook_count == 1);
+	TEST_ASSERT(!tablet_get_mode());
+
+	/* full 360, tablet mode. */
+	gpio_set_level(GPIO_TABLET_MODE_L, 0);
+	msleep(50);
+	TEST_ASSERT(tablet_hook_count == 2);
+	TEST_ASSERT(tablet_get_mode());
+
+	/* Get out of full 360 mode, Immediately back to clamshell mode. */
+	gpio_set_level(GPIO_TABLET_MODE_L, 1);
+	msleep(50);
+	TEST_ASSERT(tablet_hook_count == 3);
+	TEST_ASSERT(!tablet_get_mode());
+
+	/* Back to close, no change. */
+	gpio_set_level(GPIO_LID_OPEN, 0);
+	msleep(50);
+	TEST_ASSERT(tablet_hook_count == 3);
+	TEST_ASSERT(!tablet_get_mode());
+
+	return EC_SUCCESS;
+}
+
+/*
+ * Put the device in tablet mode first.
+ * Reset the EC, keep the existing GPIO level.
+ * Verify the state is not forgotten when the EC starts in tablet mode after
+ * reset.
+ */
+test_static int test_start_tablet_mode(void)
+{
+	/* Go in tablet mode */
+	gpio_set_level(GPIO_LID_OPEN, 1);
+	gpio_set_level(GPIO_TABLET_MODE_L, 0);
+	msleep(50);
+	TEST_ASSERT(tablet_hook_count == 2);
+
+	/* Shutdown device */
+	hook_notify(HOOK_CHIPSET_SHUTDOWN);
+
+	/* Check we start in tablet mode */
+	msleep(50);
+	TEST_ASSERT(tablet_get_mode());
+
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
+{
+	test_reset();
+
+	RUN_TEST(test_start_lid_close);
+	RUN_TEST(test_start_tablet_mode);
+
+	test_print_result();
+}
diff --git a/test/tablet_no_sensor.tasklist b/test/tablet_no_sensor.tasklist
new file mode 100644
index 0000000000..47a61cc5a5
--- /dev/null
+++ b/test/tablet_no_sensor.tasklist
@@ -0,0 +1,9 @@
+/* Copyright 2013 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST
diff --git a/test/test_config.h b/test/test_config.h
index 0d473eadad..936d99ba56 100644
--- a/test/test_config.h
+++ b/test/test_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,17 +20,28 @@
 
 /* Don't compile features unless specifically testing for them */
 #undef CONFIG_VBOOT_HASH
+
+/* Only disable this if we didn't explicitly enable it in Kconfig */
+#ifndef CONFIG_PLATFORM_EC_USB_PD_LOGGING
 #undef CONFIG_USB_PD_LOGGING
+#endif
 
-#ifdef TEST_AES
-#define CONFIG_AES
-#define CONFIG_AES_GCM
+#ifdef TEST_ALWAYS_MEMSET
+#define CONFIG_LIBCRYPTOC
+#endif
+
+#if defined(TEST_AES) || defined(TEST_CRYPTO_BENCHMARK)
+#define CONFIG_BORINGSSL_CRYPTO
 #endif
 
 #ifdef TEST_BASE32
 #define CONFIG_BASE32
 #endif
 
+#ifdef TEST_BATTERY_CONFIG
+#define CONFIG_BATTERY_CONFIG_IN_CBI
+#endif
+
 #ifdef TEST_BKLIGHT_LID
 #define CONFIG_BACKLIGHT_LID
 #endif
@@ -40,6 +51,10 @@
 #define CONFIG_BACKLIGHT_REQ_GPIO GPIO_PCH_BKLTEN
 #endif
 
+#ifdef TEST_CBI_WP
+#define CONFIG_EEPROM_CBI_WP
+#endif
+
 #ifdef TEST_FLASH_LOG
 #define CONFIG_CRC8
 #define CONFIG_FLASH_ERASED_VALUE32 (-1U)
@@ -51,6 +66,8 @@
 
 #ifdef TEST_KB_8042
 #define CONFIG_KEYBOARD_PROTOCOL_8042
+#define CONFIG_8042_AUX
+#define CONFIG_KEYBOARD_DEBUG
 #endif
 
 #ifdef TEST_KB_MKBP
@@ -59,10 +76,13 @@
 #define CONFIG_MKBP_USE_GPIO
 #endif
 
-#ifdef TEST_KB_SCAN
+#if defined(TEST_KB_SCAN) || defined(TEST_KB_SCAN_STRICT)
 #define CONFIG_KEYBOARD_PROTOCOL_MKBP
 #define CONFIG_MKBP_EVENT
 #define CONFIG_MKBP_USE_GPIO
+#ifdef TEST_KB_SCAN_STRICT
+#define CONFIG_KEYBOARD_STRICT_DEBOUNCE
+#endif
 #endif
 
 #ifdef TEST_MATH_UTIL
@@ -92,13 +112,28 @@
 #endif
 
 #if defined(TEST_FPSENSOR) || defined(TEST_FPSENSOR_STATE) || \
-	defined(TEST_FPSENSOR_CRYPTO)
-#define CONFIG_AES
-#define CONFIG_AES_GCM
+	defined(TEST_FPSENSOR_CRYPTO) ||                      \
+	defined(TEST_FPSENSOR_AUTH_CRYPTO_STATELESS) ||       \
+	defined(TEST_FPSENSOR_AUTH_CRYPTO_STATEFUL) ||        \
+	defined(TEST_FPSENSOR_AUTH_COMMANDS)
+#define CONFIG_BORINGSSL_CRYPTO
 #define CONFIG_ROLLBACK_SECRET_SIZE 32
 #define CONFIG_SHA256
 #endif
 
+#if defined(TEST_BORINGSSL_CRYPTO)
+#define CONFIG_BORINGSSL_CRYPTO
+#endif
+
+#ifdef TEST_ROLLBACK_SECRET
+#define CONFIG_ROLLBACK
+#define CONFIG_ROLLBACK_SECRET_SIZE 32
+#define CONFIG_ROLLBACK_OFF 1
+#define CONFIG_ROLLBACK_SIZE 2
+#undef CONFIG_ROLLBACK_UPDATE
+#define FP_CONTEXT_TPM_BYTES 32
+#endif
+
 #ifdef TEST_MOTION_SENSE_FIFO
 #define CONFIG_ACCEL_FIFO
 #define CONFIG_ACCEL_FIFO_SIZE 256
@@ -130,6 +165,16 @@
 #define CONFIG_MKBP_USE_GPIO
 #endif
 
+#ifdef TEST_RGB_KEYBOARD
+#define CONFIG_RGB_KEYBOARD
+#define CONFIG_RGBKBD_DEMO_DOT
+#endif
+
+#ifdef TEST_NVIDIA_GPU
+#define CONFIG_GPU_NVIDIA
+#define GPIO_NVIDIA_GPU_ACOFF_ODL 123
+#endif
+
 #ifdef TEST_STILLNESS_DETECTOR
 #define CONFIG_MKBP_EVENT
 #define CONFIG_MKBP_USE_GPIO
@@ -142,6 +187,14 @@
 #define CONFIG_MKBP_USE_GPIO
 #endif
 
+#ifdef TEST_ONLINE_CALIBRATION_SPOOF
+#define CONFIG_FPU
+#define CONFIG_ONLINE_CALIB
+#define CONFIG_MKBP_EVENT
+#define CONFIG_MKBP_USE_GPIO
+#define CONFIG_ONLINE_CALIB_SPOOF_MODE
+#endif /* TEST_ONLINE_CALIBRATION_SPOOF */
+
 #ifdef TEST_GYRO_CAL
 #define CONFIG_FPU
 #define CONFIG_ONLINE_CALIB
@@ -149,44 +202,55 @@
 #define CONFIG_MKBP_USE_GPIO
 #endif
 
-#if defined(CONFIG_ONLINE_CALIB) && \
-	!defined(CONFIG_TEMP_CACHE_STALE_THRES)
+#if defined(CONFIG_ONLINE_CALIB) && !defined(CONFIG_TEMP_CACHE_STALE_THRES)
 #define CONFIG_TEMP_CACHE_STALE_THRES (1 * SECOND)
 #endif /* CONFIG_ONLINE_CALIB && !CONFIG_TEMP_CACHE_STALE_THRES */
 
-#if defined(CONFIG_ONLINE_CALIB) || \
-	defined(TEST_BODY_DETECTION) || \
-	defined(TEST_MOTION_ANGLE) || \
-	defined(TEST_MOTION_ANGLE_TABLET) || \
-	defined(TEST_MOTION_LID) || \
-	defined(TEST_MOTION_SENSE_FIFO)
+#if defined(CONFIG_ONLINE_CALIB) || defined(TEST_BODY_DETECTION) ||        \
+	defined(TEST_MOTION_ANGLE) || defined(TEST_MOTION_ANGLE_TABLET) || \
+	defined(TEST_MOTION_LID) || defined(TEST_MOTION_SENSE_FIFO) ||     \
+	defined(TEST_TABLET_BROKEN_SENSOR)
 enum sensor_id {
 	BASE,
 	LID,
 	SENSOR_COUNT,
 };
 
+#if defined(TEST_MOTION_ANGLE) || defined(TEST_MOTION_ANGLE_TABLET) || \
+	defined(TEST_MOTION_LID) || defined(TEST_TABLET_BROKEN_SENSOR)
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_SENSOR_BASE BASE
 #define CONFIG_LID_ANGLE_SENSOR_LID LID
 #define CONFIG_TABLET_MODE
+#endif /* LID ANGLE needed */
+
 #define CONFIG_MOTION_FILL_LPC_SENSE_DATA
 
-#endif
+#endif /* sensor_id needed */
 
 #if defined(TEST_MOTION_ANGLE)
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
+#define CONFIG_ACCEL_FORCE_MODE_MASK           \
 	((1 << CONFIG_LID_ANGLE_SENSOR_BASE) | \
 	 (1 << CONFIG_LID_ANGLE_SENSOR_LID))
 #define CONFIG_ACCEL_STD_REF_FRAME_OLD
 #endif
 
-#if defined(TEST_MOTION_ANGLE_TABLET)
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
+#if defined(TEST_MOTION_ANGLE_TABLET) || defined(TEST_MOTION_LID)
+#define CONFIG_ACCEL_FORCE_MODE_MASK           \
 	((1 << CONFIG_LID_ANGLE_SENSOR_BASE) | \
 	 (1 << CONFIG_LID_ANGLE_SENSOR_LID))
 #endif
 
+#if defined(TEST_TABLET_BROKEN_SENSOR) || defined(TEST_TABLET_NO_SENSOR) || \
+	defined(TEST_MOTION_LID)
+#define CONFIG_TABLET_MODE
+#define CONFIG_GMR_TABLET_MODE
+#endif
+
+#ifdef TEST_TABLET_BROKEN_SENSOR
+#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
+#endif
+
 #if defined(TEST_BODY_DETECTION)
 #define CONFIG_BODY_DETECTION
 #define CONFIG_BODY_DETECTION_SENSOR BASE
@@ -195,19 +259,21 @@ enum sensor_id {
 #ifdef TEST_RMA_AUTH
 
 /* Test server public and private keys */
-#define RMA_KEY_BLOB	{					\
-		0x03, 0xae, 0x2d, 0x2c, 0x06, 0x23, 0xe0, 0x73, \
-		0x0d, 0xd3, 0xb7, 0x92, 0xac, 0x54, 0xc5, 0xfd,	\
-		0x7e, 0x9c, 0xf0, 0xa8, 0xeb, 0x7e, 0x2a, 0xb5,	\
-		0xdb, 0xf4, 0x79, 0x5f, 0x8a, 0x0f, 0x28, 0x3f, \
-		0x10						\
+#define RMA_KEY_BLOB                                                          \
+	{                                                                     \
+		0x03, 0xae, 0x2d, 0x2c, 0x06, 0x23, 0xe0, 0x73, 0x0d, 0xd3,   \
+			0xb7, 0x92, 0xac, 0x54, 0xc5, 0xfd, 0x7e, 0x9c, 0xf0, \
+			0xa8, 0xeb, 0x7e, 0x2a, 0xb5, 0xdb, 0xf4, 0x79, 0x5f, \
+			0x8a, 0x0f, 0x28, 0x3f, 0x10                          \
 	}
 
-#define RMA_TEST_SERVER_PRIVATE_KEY {				\
-		0x47, 0x3b, 0xa5, 0xdb, 0xc4, 0xbb, 0xd6, 0x77, \
-		0x20, 0xbd, 0xd8, 0xbd, 0xc8, 0x7a, 0xbb, 0x07,	\
-		0x03, 0x79, 0xba, 0x7b, 0x52, 0x8c, 0xec, 0xb3,	\
-		0x4d, 0xaa, 0x69, 0xf5, 0x65, 0xb4, 0x31, 0xad}
+#define RMA_TEST_SERVER_PRIVATE_KEY                                           \
+	{                                                                     \
+		0x47, 0x3b, 0xa5, 0xdb, 0xc4, 0xbb, 0xd6, 0x77, 0x20, 0xbd,   \
+			0xd8, 0xbd, 0xc8, 0x7a, 0xbb, 0x07, 0x03, 0x79, 0xba, \
+			0x7b, 0x52, 0x8c, 0xec, 0xb3, 0x4d, 0xaa, 0x69, 0xf5, \
+			0x65, 0xb4, 0x31, 0xad                                \
+	}
 #define RMA_TEST_SERVER_KEY_ID 0x10
 
 #define CONFIG_BASE32
@@ -219,22 +285,21 @@ enum sensor_id {
 
 #endif
 
-#ifdef TEST_CRC32
+#ifdef TEST_CRC
+#define CONFIG_CRC8
 #define CONFIG_SW_CRC
 #endif
 
 #ifdef TEST_RSA
 #define CONFIG_RSA
-#undef CONFIG_RSA_KEY_SIZE
-#define CONFIG_RSA_KEY_SIZE 2048
-#undef CONFIG_RSA_EXPONENT_3
+#ifdef CONFIG_RSA_EXPONENT_3
+#error Your board uses RSA exponent 3, please build rsa3 test instead!
+#endif
 #define CONFIG_RWSIG_TYPE_RWSIG
 #endif
 
 #ifdef TEST_RSA3
 #define CONFIG_RSA
-#undef CONFIG_RSA_KEY_SIZE
-#define CONFIG_RSA_KEY_SIZE 2048
 #define CONFIG_RSA_EXPONENT_3
 #define CONFIG_RWSIG_TYPE_RWSIG
 #endif
@@ -252,28 +317,33 @@ enum sensor_id {
 #define CONFIG_MALLOC
 #endif
 
-#ifdef TEST_SBS_CHARGING_V2
+#ifdef TEST_SBS_CHARGING
 #define CONFIG_BATTERY
+#define CONFIG_BATTERY_V2
+#define CONFIG_BATTERY_COUNT 1
 #define CONFIG_BATTERY_MOCK
 #define CONFIG_BATTERY_SMART
 #define CONFIG_CHARGER
 #define CONFIG_CHARGER_PROFILE_OVERRIDE
-#define CONFIG_CHARGER_INPUT_CURRENT 4032
+#define CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT 4032
 #define CONFIG_CHARGER_DISCHARGE_ON_AC
 #define CONFIG_CHARGER_DISCHARGE_ON_AC_CUSTOM
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_CONTROLLER
 int board_discharge_on_ac(int enabled);
 #define I2C_PORT_MASTER 0
 #define I2C_PORT_BATTERY 0
 #define I2C_PORT_CHARGER 0
+#define CONFIG_BATTERY_LOW_VOLTAGE_PROTECTION
+#undef CONFIG_BATTERY_LOW_VOLTAGE_TIMEOUT
+#define CONFIG_BATTERY_LOW_VOLTAGE_TIMEOUT (2 * SECOND)
 #endif
 
 #ifdef TEST_THERMAL
 #define CONFIG_CHIPSET_CAN_THROTTLE
 #define CONFIG_FANS 1
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_CONTROLLER
 #define CONFIG_TEMP_SENSOR
 #define CONFIG_THROTTLE_AP
 #define CONFIG_THERMISTOR
@@ -296,9 +366,9 @@ int ncp15wb_calculate_temp(uint16_t adc);
 #ifdef TEST_BATTERY_GET_PARAMS_SMART
 #define CONFIG_BATTERY_MOCK
 #define CONFIG_BATTERY_SMART
-#define CONFIG_CHARGER_INPUT_CURRENT 4032
+#define CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT 4032
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_CONTROLLER
 #define I2C_PORT_MASTER 0
 #define I2C_PORT_BATTERY 0
 #define I2C_PORT_CHARGER 0
@@ -306,11 +376,13 @@ int ncp15wb_calculate_temp(uint16_t adc);
 
 #ifdef TEST_CEC
 #define CONFIG_CEC
+#define CONFIG_MKBP_EVENT
+#define CONFIG_MKBP_USE_GPIO
 #endif
 
 #ifdef TEST_LIGHTBAR
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_CONTROLLER
 #define I2C_PORT_LIGHTBAR 0
 #define CONFIG_ALS_LIGHTBAR_DIMMING 0
 #endif
@@ -325,10 +397,19 @@ int ncp15wb_calculate_temp(uint16_t adc);
 #define CONFIG_SW_CRC
 #endif
 
-#if defined(TEST_USB_SM_FRAMEWORK_H3) || \
-	defined(TEST_USB_SM_FRAMEWORK_H2) || \
-	defined(TEST_USB_SM_FRAMEWORK_H1) || \
-	defined(TEST_USB_SM_FRAMEWORK_H0)
+#ifdef TEST_USB_PD_PDO_FIXED
+#define CONFIG_USB_POWER_DELIVERY
+#define CONFIG_USB_PD_TCPMV1
+#define CONFIG_USB_PD_PORT_MAX_COUNT 1
+#define CONFIG_USB_PD_TCPC
+#define CONFIG_USB_PD_TCPM_STUB
+#define CONFIG_SHA256
+#define CONFIG_SW_CRC
+#define CONFIG_USB_PD_ONLY_FIXED_PDOS
+#endif
+
+#if defined(TEST_USB_SM_FRAMEWORK_H3) || defined(TEST_USB_SM_FRAMEWORK_H2) || \
+	defined(TEST_USB_SM_FRAMEWORK_H1) || defined(TEST_USB_SM_FRAMEWORK_H0)
 #define CONFIG_TEST_SM
 #endif
 
@@ -344,6 +425,7 @@ int ncp15wb_calculate_temp(uint16_t adc);
 #undef CONFIG_USB_PE_SM
 #undef CONFIG_USB_TYPEC_SM
 #undef CONFIG_USB_PD_HOST_CMD
+#undef CONFIG_USB_DPM_SM
 #define CONFIG_USB_PRL_SM
 #define CONFIG_USB_PD_TCPC
 #define CONFIG_USB_PD_TCPM_STUB
@@ -352,12 +434,19 @@ int ncp15wb_calculate_temp(uint16_t adc);
 #define CONFIG_SW_CRC
 #endif
 
+#if defined(TEST_USB_PD_TIMER)
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#define CONFIG_MATH_UTIL
+#define CONFIG_TEST_USB_PD_TIMER
+#endif
+
 #if defined(TEST_USB_PRL)
 #define CONFIG_USB_PD_PORT_MAX_COUNT 1
 #define CONFIG_USB_PD_REV30
 #define CONFIG_USB_PD_EXTENDED_MESSAGES
 #define CONFIG_USB_PD_TCPMV2
 #undef CONFIG_USB_PE_SM
+#undef CONFIG_USB_DPM_SM
 #undef CONFIG_USB_TYPEC_SM
 #undef CONFIG_USB_PD_HOST_CMD
 #define CONFIG_USB_PRL_SM
@@ -381,11 +470,13 @@ int ncp15wb_calculate_temp(uint16_t adc);
 #define CONFIG_USB_PD_DECODE_SOP
 #undef CONFIG_USB_TYPEC_SM
 #define CONFIG_USBC_VCONN
-#define PD_VCONN_SWAP_DELAY 5000 /* us */
 #define CONFIG_USB_PD_DISCHARGE_GPIO
 #undef CONFIG_USB_PD_HOST_CMD
 #define CONFIG_USB_PD_ALT_MODE_DFP
+#define CONFIG_USB_PD_DP_MODE
+#define CONFIG_USB_PD_DISCOVERY
 #define CONFIG_USBC_SS_MUX
+#define CONFIG_USB_PD_3A_PORTS 0 /* Host does not define a 3.0 A PDO */
 #endif
 
 #if defined(TEST_USB_PE_DRP) || defined(TEST_USB_PE_DRP_NOEXTENDED)
@@ -405,21 +496,24 @@ int ncp15wb_calculate_temp(uint16_t adc);
 #define CONFIG_USB_PD_DECODE_SOP
 #undef CONFIG_USB_TYPEC_SM
 #define CONFIG_USBC_VCONN
-#define PD_VCONN_SWAP_DELAY 5000 /* us */
 #define CONFIG_USB_PD_DISCHARGE_GPIO
 #undef CONFIG_USB_PD_HOST_CMD
 #define CONFIG_USB_PD_ALT_MODE_DFP
+#define CONFIG_USB_PD_DP_MODE
+#define CONFIG_USB_PD_DISCOVERY
 #define CONFIG_USBC_SS_MUX
-#endif
+#define I2C_PORT_HOST_TCPC 0
+#define CONFIG_CHARGE_MANAGER
+#define CONFIG_USB_PD_3A_PORTS 0 /* Host does not define a 3.0 A PDO */
+#endif /* TEST_USB_PE_DRP || TEST_USB_PE_DRP_NOEXTENDED */
 
 /* Common TypeC tests defines */
-#if defined(TEST_USB_TYPEC_VPD) || \
-	defined(TEST_USB_TYPEC_CTVPD)
+#if defined(TEST_USB_TYPEC_VPD) || defined(TEST_USB_TYPEC_CTVPD)
 #define CONFIG_USB_PID 0x5036
 #define VPD_HW_VERSION 0x0001
 #define VPD_FW_VERSION 0x0001
 #define USB_BCD_DEVICE 0
-
+#define VPD_CT_CURRENT VPD_CT_CURRENT_3A
 /* Vbus impedance in milliohms */
 #define VPD_VBUS_IMPEDANCE 65
 
@@ -457,14 +551,19 @@ int ncp15wb_calculate_temp(uint16_t adc);
 #define CONFIG_USB_PD_PORT_MAX_COUNT 1
 #define CONFIG_USBC_SS_MUX
 #define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+#define CONFIG_USB_PD_TCPC_LOW_POWER
 #define CONFIG_USB_PD_VBUS_DETECT_TCPC
+/* Since we have no real HW to wait on, use a minimal debounce */
+#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
+#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE 1
 #define CONFIG_USB_POWER_DELIVERY
 #undef CONFIG_USB_PRL_SM
 #undef CONFIG_USB_PE_SM
+#undef CONFIG_USB_DPM_SM
 #undef CONFIG_USB_PD_HOST_CMD
 #endif
 
-#ifdef TEST_USB_TCPMV2_TCPCI
+#ifdef TEST_USB_TCPMV2_COMPLIANCE
 #define CONFIG_USB_DRP_ACC_TRYSRC
 #define CONFIG_USB_PD_DUAL_ROLE
 #define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
@@ -478,17 +577,21 @@ int ncp15wb_calculate_temp(uint16_t adc);
 #define CONFIG_USB_POWER_DELIVERY
 #define CONFIG_TEST_USB_PE_SM
 #define CONFIG_USB_PD_ALT_MODE_DFP
+#define CONFIG_USB_PD_DP_MODE
+#define CONFIG_USB_PD_DISCOVERY
 #define CONFIG_USBC_VCONN
 #define CONFIG_USBC_VCONN_SWAP
 #define CONFIG_USB_PID 0x5036
-#define PD_VCONN_SWAP_DELAY 5000 /* us */
 #define CONFIG_USB_PD_TCPM_TCPCI
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_CONTROLLER
+#define CONFIG_BATTERY
+#define CONFIG_NUM_FIXED_BATTERIES 1
 #define I2C_PORT_HOST_TCPC 0
 #define CONFIG_USB_PD_DEBUG_LEVEL 3
 #define CONFIG_USB_PD_EXTENDED_MESSAGES
 #define CONFIG_USB_PD_DECODE_SOP
+#define CONFIG_USB_PD_3A_PORTS 0 /* Host does not define a 3.0 A PDO */
 #endif
 
 #ifdef TEST_USB_PD_INT
@@ -522,6 +625,10 @@ int ncp15wb_calculate_temp(uint16_t adc);
 #endif
 #endif /* TEST_USB_PD || TEST_USB_PD_GIVEBACK || TEST_USB_PD_REV30 */
 
+#ifdef TEST_USB_PD_CONSOLE
+#define CONFIG_USB_PD_EPR
+#endif
+
 #ifdef TEST_USB_PPC
 #define CONFIG_USB_PD_PORT_MAX_COUNT 1
 #define CONFIG_USB_PD_VBUS_DETECT_PPC
@@ -531,14 +638,31 @@ int ncp15wb_calculate_temp(uint16_t adc);
 #define CONFIG_USBC_PPC_VCONN
 #endif
 
+#ifdef TEST_USB_PD_CONSOLE
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#define CONFIG_USB_PE_SM
+#define CONFIG_CMD_PD
+#define CONFIG_USB_PD_TCPMV2
+#define CONFIG_USB_PD_TRY_SRC
+#define CONFIG_USB_PD_DUAL_ROLE
+#define CONFIG_USBC_VCONN
+#define CONFIG_USBC_VCONN_SWAP
+#define CONFIG_CMD_PD_TIMER
+#undef CONFIG_USB_PD_HOST_CMD
+#undef CONFIG_USB_PRL_SM
+#undef CONFIG_USB_DPM_SM
+#endif
+
 #if defined(TEST_CHARGE_MANAGER) || defined(TEST_CHARGE_MANAGER_DRP_CHARGING)
 #define CONFIG_CHARGE_MANAGER
+#define CONFIG_USB_PD_3A_PORTS 0 /* Host does not define a 3.0 A PDO */
 #define CONFIG_USB_PD_DUAL_ROLE
 #define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#define CONFIG_USB_POWER_DELIVERY
 #define CONFIG_BATTERY
 #define CONFIG_BATTERY_SMART
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_CONTROLLER
 #define I2C_PORT_BATTERY 0
 #endif /* TEST_CHARGE_MANAGER_* */
 
@@ -551,6 +675,7 @@ int ncp15wb_calculate_temp(uint16_t adc);
 #ifdef TEST_CHARGE_RAMP
 #define CONFIG_CHARGE_RAMP_SW
 #define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#undef CONFIG_USB_PD_HOST_CMD
 #endif
 
 #ifdef TEST_RTC
@@ -563,18 +688,17 @@ int ncp15wb_calculate_temp(uint16_t adc);
 #define CONFIG_RSA
 #define CONFIG_RWSIG_TYPE_RWSIG
 #define CONFIG_RW_B
-#define CONFIG_RW_B_MEM_OFF		CONFIG_RO_MEM_OFF
-#undef  CONFIG_RO_SIZE
-#define CONFIG_RO_SIZE			(CONFIG_FLASH_SIZE / 4)
-#undef  CONFIG_RW_SIZE
-#define CONFIG_RW_SIZE			CONFIG_RO_SIZE
-#define CONFIG_RW_A_STORAGE_OFF		CONFIG_RW_STORAGE_OFF
-#define CONFIG_RW_B_STORAGE_OFF		(CONFIG_RW_A_STORAGE_OFF + \
-					 CONFIG_RW_SIZE)
-#define CONFIG_RW_A_SIGN_STORAGE_OFF	(CONFIG_RW_A_STORAGE_OFF + \
-					 CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE)
-#define CONFIG_RW_B_SIGN_STORAGE_OFF	(CONFIG_RW_B_STORAGE_OFF + \
-					 CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE)
+#define CONFIG_RW_B_MEM_OFF CONFIG_RO_MEM_OFF
+#undef CONFIG_RO_SIZE
+#define CONFIG_RO_SIZE (CONFIG_FLASH_SIZE_BYTES / 4)
+#undef CONFIG_RW_SIZE
+#define CONFIG_RW_SIZE CONFIG_RO_SIZE
+#define CONFIG_RW_A_STORAGE_OFF CONFIG_RW_STORAGE_OFF
+#define CONFIG_RW_B_STORAGE_OFF (CONFIG_RW_A_STORAGE_OFF + CONFIG_RW_SIZE)
+#define CONFIG_RW_A_SIGN_STORAGE_OFF \
+	(CONFIG_RW_A_STORAGE_OFF + CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE)
+#define CONFIG_RW_B_SIGN_STORAGE_OFF \
+	(CONFIG_RW_B_STORAGE_OFF + CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE)
 #endif
 
 #ifdef TEST_X25519
@@ -583,10 +707,14 @@ int ncp15wb_calculate_temp(uint16_t adc);
 
 #ifdef TEST_I2C_BITBANG
 #define CONFIG_I2C
-#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_CONTROLLER
 #define CONFIG_I2C_BITBANG
 #define I2C_BITBANG_PORT_COUNT 1
 #endif
 
-#endif  /* TEST_BUILD */
-#endif  /* __TEST_TEST_CONFIG_H */
+#ifdef TEST_PANIC
+#undef CONFIG_PANIC_STRIP_GPR
+#endif
+
+#endif /* TEST_BUILD */
+#endif /* __TEST_TEST_CONFIG_H */
diff --git a/test/thermal.c b/test/thermal.c
index 1161ecbf1b..a70137238d 100644
--- a/test/thermal.c
+++ b/test/thermal.c
@@ -1,10 +1,11 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Test thermal engine.
  */
 
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
 #include "driver/temp_sensor/thermistor.h"
@@ -18,7 +19,6 @@
 #include "timer.h"
 #include "util.h"
 
-
 /*****************************************************************************/
 /* Exported data */
 
@@ -95,7 +95,7 @@ static void reset_mocks(void)
 	memset(thermal_params, 0, sizeof(thermal_params));
 
 	/* All sensors report error anyway */
-	set_temps(-1, -1 , -1, -1);
+	set_temps(-1, -1, -1, -1);
 
 	/* Reset expectations */
 	host_throttled = 0;
@@ -105,7 +105,6 @@ static void reset_mocks(void)
 	no_temps_read = 0;
 }
 
-
 /*****************************************************************************/
 /* Tests */
 
@@ -147,7 +146,6 @@ static int test_sensors_can_be_read(void)
 	return EC_SUCCESS;
 }
 
-
 static int test_one_fan(void)
 {
 	reset_mocks();
@@ -448,42 +446,41 @@ static int test_several_limits(void)
 	TEST_ASSERT(cpu_throttled == 0);
 	TEST_ASSERT(cpu_shutdown == 0);
 
-	set_temps(500, 50, -1, 10);	/* 1=low, 2=X, 3=low */
+	set_temps(500, 50, -1, 10); /* 1=low, 2=X, 3=low */
 	sleep(2);
 	TEST_ASSERT(host_throttled == 0);
 	TEST_ASSERT(cpu_throttled == 0);
 	TEST_ASSERT(cpu_shutdown == 0);
 
-	set_temps(500, 170, 210, 10);	/* 1=warn, 2=high, 3=low */
+	set_temps(500, 170, 210, 10); /* 1=warn, 2=high, 3=low */
 	sleep(2);
 	TEST_ASSERT(host_throttled == 1);
 	TEST_ASSERT(cpu_throttled == 1);
 	TEST_ASSERT(cpu_shutdown == 0);
 
-	set_temps(500, 100, 50, 40);	/* 1=low, 2=low, 3=high */
+	set_temps(500, 100, 50, 40); /* 1=low, 2=low, 3=high */
 	sleep(2);
 	TEST_ASSERT(host_throttled == 1);
 	TEST_ASSERT(cpu_throttled == 1);
 	TEST_ASSERT(cpu_shutdown == 0);
 
-	set_temps(500, 100, 50, 41);	/* 1=low, 2=low, 3=shutdown */
+	set_temps(500, 100, 50, 41); /* 1=low, 2=low, 3=shutdown */
 	sleep(2);
 	TEST_ASSERT(host_throttled == 1);
 	TEST_ASSERT(cpu_throttled == 1);
 	TEST_ASSERT(cpu_shutdown == 1);
 
-	all_temps(0);			/* reset from shutdown */
+	all_temps(0); /* reset from shutdown */
 	sleep(2);
 	TEST_ASSERT(host_throttled == 0);
 	TEST_ASSERT(cpu_throttled == 0);
 
-
 	return EC_SUCCESS;
 }
 
 /* Tests for ncp15wb thermistor ADC-to-temp calculation */
-#define LOW_ADC_TEST_VALUE	887 /* 0 C */
-#define HIGH_ADC_TEST_VALUE	100 /* > 100C */
+#define LOW_ADC_TEST_VALUE 887 /* 0 C */
+#define HIGH_ADC_TEST_VALUE 100 /* > 100C */
 
 static int test_ncp15wb_adc_to_temp(void)
 {
@@ -496,18 +493,11 @@ static int test_ncp15wb_adc_to_temp(void)
 		int adc;
 		int temp;
 	} adc_temp_datapoints[] = {
-		{ 615, 30 },
-		{ 561, 35 },
-		{ 508, 40 },
-		{ 407, 50 },
-		{ 315, 60 },
-		{ 243, 70 },
-		{ 186, 80 },
-		{ 140, 90 },
-		{ 107, 100 },
+		{ 615, 30 }, { 561, 35 }, { 508, 40 },
+		{ 407, 50 }, { 315, 60 }, { 243, 70 },
+		{ 186, 80 }, { 140, 90 }, { 107, 100 },
 	};
 
-
 	/*
 	 * Verify that calculated temp is decreasing for entire ADC range,
 	 * and that a tick down in ADC value results in no more than 1C
@@ -518,8 +508,7 @@ static int test_ncp15wb_adc_to_temp(void)
 
 	while (--i > HIGH_ADC_TEST_VALUE) {
 		new_temp = ncp15wb_calculate_temp(i);
-		TEST_ASSERT(new_temp == temp ||
-			    new_temp == temp + 1);
+		TEST_ASSERT(new_temp == temp || new_temp == temp + 1);
 		temp = new_temp;
 	}
 
@@ -539,9 +528,7 @@ static int test_thermistor_linear_interpolate(void)
 	int i, t, t0;
 	uint16_t mv;
 	/* Simple test case - a straight line. */
-	struct thermistor_data_pair line_data[] = {
-		{ 100, 0 }, { 0, 100 }
-	};
+	struct thermistor_data_pair line_data[] = { { 100, 0 }, { 0, 100 } };
 	struct thermistor_info line_info = {
 		.scaling_factor = 1,
 		.num_pairs = ARRAY_SIZE(line_data),
@@ -576,19 +563,17 @@ static int test_thermistor_linear_interpolate(void)
 	 * of derived values but at temp - 1, temp + 1, and in between.
 	 */
 	struct {
-		uint16_t mv;	/* not scaled */
+		uint16_t mv; /* not scaled */
 		int temp;
 	} cmp[] = {
-		{ 3030, 1 },  { 2341, 5 }, { 2195, 9 },
-		{ 2120, 11 }, { 1966, 15 }, { 1811, 19 },
-		{ 1733, 21 }, { 1581, 25 }, { 1434, 29 },
-		{ 1363, 31 }, { 1227, 35 }, { 1100, 39 },
-		{ 1040, 41 }, { 929, 45 }, { 827, 49 },
-		{ 780, 51 }, { 693, 55 }, { 615, 59 },
-		{ 579, 61 }, { 514, 65 }, { 460, 69 },
-		{ 430, 71 }, { 382, 75 }, { 339, 79 },
-		{ 320, 81 }, { 285, 85 }, { 254, 89 },
-		{ 240, 91 }, { 214, 95 }, { 192, 99 },
+		{ 3030, 1 },  { 2341, 5 },  { 2195, 9 },  { 2120, 11 },
+		{ 1966, 15 }, { 1811, 19 }, { 1733, 21 }, { 1581, 25 },
+		{ 1434, 29 }, { 1363, 31 }, { 1227, 35 }, { 1100, 39 },
+		{ 1040, 41 }, { 929, 45 },  { 827, 49 },  { 780, 51 },
+		{ 693, 55 },  { 615, 59 },  { 579, 61 },  { 514, 65 },
+		{ 460, 69 },  { 430, 71 },  { 382, 75 },  { 339, 79 },
+		{ 320, 81 },  { 285, 85 },  { 254, 89 },  { 240, 91 },
+		{ 214, 95 },  { 192, 99 },
 	};
 
 	/* Return lowest temperature in data set if voltage is too high. */
@@ -602,9 +587,8 @@ static int test_thermistor_linear_interpolate(void)
 	TEST_ASSERT(t == data[info.num_pairs - 1].temp);
 
 	/* Simple line test */
-	for (mv = line_data[0].mv;
-		mv > line_data[line_info.num_pairs - 1].mv;
-		mv--) {
+	for (mv = line_data[0].mv; mv > line_data[line_info.num_pairs - 1].mv;
+	     mv--) {
 		t = thermistor_linear_interpolate(mv, &line_info);
 		TEST_ASSERT(mv == line_data[line_info.num_pairs - 1].temp - t);
 	}
@@ -614,8 +598,7 @@ static int test_thermistor_linear_interpolate(void)
 	 * decreases with increase in voltage (0-5V, 10mV steps).
 	 */
 	for (mv = data[0].mv * info.scaling_factor, t0 = data[0].temp;
-		mv > data[info.num_pairs - 1].mv;
-		mv -= 10) {
+	     mv > data[info.num_pairs - 1].mv; mv -= 10) {
 		int t1 = thermistor_linear_interpolate(mv, &info);
 
 		TEST_ASSERT(t1 >= t0);
@@ -642,7 +625,7 @@ static int test_thermistor_linear_interpolate(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	RUN_TEST(test_init_val);
 	RUN_TEST(test_sensors_can_be_read);
diff --git a/test/thermal.tasklist b/test/thermal.tasklist
index d22719d1fb..7494e757cf 100644
--- a/test/thermal.tasklist
+++ b/test/thermal.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/timer.cc b/test/timer.cc
new file mode 100644
index 0000000000..bac49f8498
--- /dev/null
+++ b/test/timer.cc
@@ -0,0 +1,42 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/** @brief Test functions defined in timer.h, like usleep().
+ *
+ * This test only validates the functionality of code in timer.h and is not
+ * expected to accurately measure/check the timing.
+ */
+
+#include "common.h"
+#include "math_util.h"
+#include "test_util.h"
+
+extern "C" {
+#include "timer.h"
+#include "watchdog.h"
+}
+
+test_static int test_usleep(void)
+{
+	constexpr int expected_duration = 12345;
+
+	timestamp_t start_time = get_time();
+	usleep(expected_duration);
+	int sleep_duration = time_since32(start_time);
+
+	TEST_NEAR(expected_duration, sleep_duration, 100, "%d");
+
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
+{
+	test_reset();
+	watchdog_reload();
+
+	RUN_TEST(test_usleep);
+
+	test_print_result();
+}
diff --git a/test/timer.tasklist b/test/timer.tasklist
new file mode 100644
index 0000000000..959f62ef79
--- /dev/null
+++ b/test/timer.tasklist
@@ -0,0 +1,9 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST
diff --git a/test/timer_calib.c b/test/timer_calib.c
index 68603762fe..115bbc4841 100644
--- a/test/timer_calib.c
+++ b/test/timer_calib.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -13,13 +13,13 @@
 
 uint32_t difftime(timestamp_t t0, timestamp_t t1)
 {
-	return (uint32_t)(t1.val-t0.val);
+	return (uint32_t)(t1.val - t0.val);
 }
 
 int timer_calib_task(void *data)
 {
 	timestamp_t t0, t1;
-	unsigned d;
+	unsigned int d;
 
 	while (1) {
 		task_wait_event(-1);
@@ -56,7 +56,7 @@ int timer_calib_task(void *data)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	task_wake(TASK_ID_TESTTMR);
 }
diff --git a/test/timer_calib.py b/test/timer_calib.py
index 2a625d80c7..2b7c33060e 100644
--- a/test/timer_calib.py
+++ b/test/timer_calib.py
@@ -1,4 +1,4 @@
-# Copyright 2011 The Chromium OS Authors. All rights reserved.
+# Copyright 2011 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -7,48 +7,54 @@
 
 import time
 
-def one_pass(helper):
-      helper.wait_output("=== Timer calibration ===")
-      res = helper.wait_output("back-to-back get_time : (?P<lat>[0-9]+) us",
-                               use_re=True)["lat"]
-      minlat = int(res)
-      helper.trace("get_time latency %d us\n" % minlat)
-
-      helper.wait_output("sleep 1s")
-      t0 = time.time()
-      second = helper.wait_output("done. delay = (?P<second>[0-9]+) us",
-                               use_re=True)["second"]
-      t1 = time.time()
-      secondreal = t1 - t0
-      secondlat = int(second) - 1000000
-      helper.trace("1s timer latency %d us / real time %f s\n" % (secondlat,
-                                                                  secondreal))
-
 
-      us = {}
-      for pow2 in range(7):
-          delay = 1 << (7-pow2)
-          us[delay] = helper.wait_output("%d us => (?P<us>[0-9]+) us" % delay,
-                                  use_re=True)["us"]
-      helper.wait_output("Done.")
-
-      return minlat, secondlat, secondreal
+def one_pass(helper):
+    helper.wait_output("=== Timer calibration ===")
+    res = helper.wait_output(
+        "back-to-back get_time : (?P<lat>[0-9]+) us", use_re=True
+    )["lat"]
+    minlat = int(res)
+    helper.trace("get_time latency %d us\n" % minlat)
+
+    helper.wait_output("sleep 1s")
+    t0 = time.time()
+    second = helper.wait_output(
+        "done. delay = (?P<second>[0-9]+) us", use_re=True
+    )["second"]
+    t1 = time.time()
+    secondreal = t1 - t0
+    secondlat = int(second) - 1000000
+    helper.trace(
+        "1s timer latency %d us / real time %f s\n" % (secondlat, secondreal)
+    )
+
+    us = {}
+    for pow2 in range(7):
+        delay = 1 << (7 - pow2)
+        us[delay] = helper.wait_output(
+            "%d us => (?P<us>[0-9]+) us" % delay, use_re=True
+        )["us"]
+    helper.wait_output("Done.")
+
+    return minlat, secondlat, secondreal
 
 
 def test(helper):
-      one_pass(helper)
+    one_pass(helper)
 
-      helper.ec_command("reboot")
-      helper.wait_output("--- UART initialized")
+    helper.ec_command("reboot")
+    helper.wait_output("--- UART initialized")
 
-      # get the timing results on the second pass
-      # to avoid binary translation overhead
-      minlat, secondlat, secondreal = one_pass(helper)
+    # get the timing results on the second pass
+    # to avoid binary translation overhead
+    minlat, secondlat, secondreal = one_pass(helper)
 
-      # check that the timings somewhat make sense
-      if minlat > 220 or secondlat > 500 or abs(secondreal-1.0) > 0.200:
-           helper.fail("imprecise timings " +
-                       "(get_time %d us sleep %d us / real time %.3f s)" %
-                       (minlat, secondlat, secondreal))
+    # check that the timings somewhat make sense
+    if minlat > 220 or secondlat > 500 or abs(secondreal - 1.0) > 0.200:
+        helper.fail(
+            "imprecise timings "
+            + "(get_time %d us sleep %d us / real time %.3f s)"
+            % (minlat, secondlat, secondreal)
+        )
 
-      return True # PASS !
+    return True  # PASS !
diff --git a/test/timer_calib.tasklist b/test/timer_calib.tasklist
index 51f5beb6c1..22a63c247e 100644
--- a/test/timer_calib.tasklist
+++ b/test/timer_calib.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/timer_dos.c b/test/timer_dos.c
index c681300102..ef9cc3ef0c 100644
--- a/test/timer_dos.c
+++ b/test/timer_dos.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -68,7 +68,7 @@ int task_timer(void *seed)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	wait_for_task_started();
 	task_wake(TASK_ID_TMRD);
diff --git a/test/timer_dos.tasklist b/test/timer_dos.tasklist
index 4da3419f77..5bd77b0580 100644
--- a/test/timer_dos.tasklist
+++ b/test/timer_dos.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/timer_jump.py b/test/timer_jump.py
index f506a69fcf..bd2310f3d7 100644
--- a/test/timer_jump.py
+++ b/test/timer_jump.py
@@ -1,4 +1,4 @@
-# Copyright 2012 The Chromium OS Authors. All rights reserved.
+# Copyright 2012 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -7,25 +7,29 @@
 
 import time
 
+
 DELAY = 5
 ERROR_MARGIN = 0.5
 
+
 def test(helper):
-      helper.wait_output("idle task started")
-      helper.ec_command("sysinfo")
-      copy = helper.wait_output("Copy:\s+(?P<c>\S+)", use_re=True)["c"]
-      if copy != "RO":
-          helper.ec_command("sysjump ro")
-          helper.wait_output("idle task started")
-      helper.ec_command("gettime")
-      ec_start_time = helper.wait_output("Time: 0x[0-9a-f]* = (?P<t>[\d\.]+) s",
-                                         use_re=True)["t"]
-      time.sleep(DELAY)
-      helper.ec_command("sysjump a")
-      helper.wait_output("idle task started")
-      helper.ec_command("gettime")
-      ec_end_time = helper.wait_output("Time: 0x[0-9a-f]* = (?P<t>[\d\.]+) s",
-                                       use_re=True)["t"]
+    helper.wait_output("idle task started")
+    helper.ec_command("sysinfo")
+    copy = helper.wait_output("Copy:\s+(?P<c>\S+)", use_re=True)["c"]
+    if copy != "RO":
+        helper.ec_command("sysjump ro")
+        helper.wait_output("idle task started")
+    helper.ec_command("gettime")
+    ec_start_time = helper.wait_output(
+        "Time: 0x[0-9a-f]* = (?P<t>[\d\.]+) s", use_re=True
+    )["t"]
+    time.sleep(DELAY)
+    helper.ec_command("sysjump a")
+    helper.wait_output("idle task started")
+    helper.ec_command("gettime")
+    ec_end_time = helper.wait_output(
+        "Time: 0x[0-9a-f]* = (?P<t>[\d\.]+) s", use_re=True
+    )["t"]
 
-      time_diff = float(ec_end_time) - float(ec_start_time)
-      return time_diff >= DELAY and time_diff <= DELAY + ERROR_MARGIN
+    time_diff = float(ec_end_time) - float(ec_start_time)
+    return time_diff >= DELAY and time_diff <= DELAY + ERROR_MARGIN
diff --git a/test/timer_jump.tasklist b/test/timer_jump.tasklist
index da0ab6211a..100cb6b5bd 100644
--- a/test/timer_jump.tasklist
+++ b/test/timer_jump.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/tpm_seed_clear.c b/test/tpm_seed_clear.c
new file mode 100644
index 0000000000..2077c82e01
--- /dev/null
+++ b/test/tpm_seed_clear.c
@@ -0,0 +1,104 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "ec_commands.h"
+#include "system.h"
+#include "task.h"
+#include "test_util.h"
+
+#ifdef SECTION_IS_RW
+#include "fpsensor_state.h"
+#endif
+
+#include <stdint.h>
+#include <string.h>
+
+test_static const uint8_t default_fake_tpm_seed[] = {
+	0xd9, 0x71, 0xaf, 0xc4, 0xcd, 0x36, 0xe3, 0x60, 0xf8, 0x5a, 0xa0,
+	0xa6, 0x2c, 0xb3, 0xf5, 0xe2, 0xeb, 0xb9, 0xd8, 0x2f, 0xb5, 0x78,
+	0x5c, 0x79, 0x82, 0xce, 0x06, 0x3f, 0xcc, 0x23, 0xb9, 0xe7,
+};
+
+test_static const uint8_t zero_fake_tpm_seed[] = {
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+};
+
+#ifdef SECTION_IS_RO
+test_static uint8_t tpm_seed[FP_CONTEXT_TPM_BYTES];
+#endif
+
+test_static int test_tpm_seed_before_reboot(void)
+{
+	if (IS_ENABLED(SECTION_IS_RW)) {
+		TEST_ASSERT_ARRAY_EQ(tpm_seed, zero_fake_tpm_seed,
+				     FP_CONTEXT_TPM_BYTES);
+		memcpy(tpm_seed, default_fake_tpm_seed, FP_CONTEXT_TPM_BYTES);
+		TEST_ASSERT_ARRAY_EQ(tpm_seed, default_fake_tpm_seed,
+				     FP_CONTEXT_TPM_BYTES);
+	}
+	return EC_SUCCESS;
+}
+
+test_static int test_tpm_seed_after_reboot(void)
+{
+	if (IS_ENABLED(SECTION_IS_RW)) {
+		TEST_ASSERT_ARRAY_EQ(tpm_seed, zero_fake_tpm_seed,
+				     FP_CONTEXT_TPM_BYTES);
+	}
+	return EC_SUCCESS;
+}
+
+test_static void run_test_step1(void)
+{
+	ccprints("Step 1: tpm_seed_clear\n");
+	cflush();
+
+	RUN_TEST(test_tpm_seed_before_reboot);
+
+	if (test_get_error_count()) {
+		test_reboot_to_next_step(TEST_STATE_FAILED);
+	} else {
+		test_reboot_to_next_step(TEST_STATE_STEP_2);
+	}
+}
+
+test_static void run_test_step2(void)
+{
+	ccprints("Step 2: tpm_seed_clear\n");
+	cflush();
+
+	RUN_TEST(test_tpm_seed_after_reboot);
+
+	if (test_get_error_count()) {
+		test_reboot_to_next_step(TEST_STATE_FAILED);
+	} else {
+		test_reboot_to_next_step(TEST_STATE_PASSED);
+	}
+}
+
+void test_run_step(uint32_t state)
+{
+	if (state & TEST_STATE_MASK(TEST_STATE_STEP_1)) {
+		run_test_step1();
+	} else if (state & TEST_STATE_MASK(TEST_STATE_STEP_2)) {
+		run_test_step2();
+	}
+}
+int task_test(void *unused)
+{
+	if (IS_ENABLED(SECTION_IS_RW))
+		test_run_multistep();
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
+{
+	test_reset();
+	msleep(100); /* Wait for TASK_ID_TEST to initialize */
+	task_wake(TASK_ID_TEST);
+}
diff --git a/test/tpm_seed_clear.tasklist b/test/tpm_seed_clear.tasklist
new file mode 100644
index 0000000000..59918a1ab0
--- /dev/null
+++ b/test/tpm_seed_clear.tasklist
@@ -0,0 +1,10 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST \
+  TASK_TEST(TEST, task_test, NULL, TASK_STACK_SIZE)
diff --git a/test/uptime.c b/test/uptime.c
index 651628ab7b..ab65820c18 100644
--- a/test/uptime.c
+++ b/test/uptime.c
@@ -1,10 +1,8 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <stdbool.h>
-
 #include "common.h"
 #include "ec_commands.h"
 #include "host_command.h"
@@ -12,6 +10,8 @@
 #include "timer.h"
 #include "util.h"
 
+#include <stdbool.h>
+
 static bool get_ap_reset_stats_should_succeed = true;
 
 /* Mocks */
@@ -62,7 +62,7 @@ test_static int test_host_uptime_info_command_failure(void)
 	return EC_RES_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/uptime.tasklist b/test/uptime.tasklist
index 9bf1c80c20..b5c09fb4c3 100644
--- a/test/uptime.tasklist
+++ b/test/uptime.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/usb_common.tasklist b/test/usb_common.tasklist
index 9bf1c80c20..b5c09fb4c3 100644
--- a/test/usb_common.tasklist
+++ b/test/usb_common.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/usb_common_test.c b/test/usb_common_test.c
index c7cec27640..e385b57c16 100644
--- a/test/usb_common_test.c
+++ b/test/usb_common_test.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -66,9 +66,138 @@ int test_pd_get_cc_state(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+/*
+ * From USB Power Delivery Specification Revision 3.0, Version 2.0
+ * Table 6-7 Power Data Object
+ */
+#define MAKE_FIXED(v, c) (0 << 30 | (v / 50) << 10 | (c / 10))
+#define MAKE_BATT(v_max, v_min, p) \
+	(1 << 30 | (v_max / 50) << 20 | (v_min / 50) << 10 | (p / 250))
+#define MAKE_VAR(v_max, v_min, c) \
+	(2 << 30 | (v_max / 50) << 20 | (v_min / 50) << 10 | (c / 10))
+#define MAKE_AUG(v_max, v_min, c) \
+	(3 << 30 | (v_max / 100) << 17 | (v_min / 100) << 8 | (c / 50))
+
+/*
+ * Tests various cases for pd_extract_pdo_power. It takes a very high voltage to
+ * exceed PD_MAX_POWER_MW without also exceeding PD_MAX_CURRENT_MA, so those
+ * tests are not particularly realistic.
+ */
+int test_pd_extract_pdo_power(void)
+{
+	uint32_t ma;
+	uint32_t max_mv;
+	uint32_t min_mv;
+
+	pd_extract_pdo_power(MAKE_FIXED(/*v=*/5000, /*c=*/3000), &ma, &max_mv,
+			     &min_mv);
+	TEST_EQ(max_mv, 5000, "%d");
+	TEST_EQ(min_mv, 5000, "%d");
+	TEST_EQ(ma, 3000, "%d");
+	pd_extract_pdo_power(MAKE_FIXED(/*v=*/20000, /*c=*/2600), &ma, &max_mv,
+			     &min_mv);
+	TEST_EQ(max_mv, 20000, "%d");
+	TEST_EQ(min_mv, 20000, "%d");
+	TEST_EQ(ma, 2600, "%d");
+	pd_extract_pdo_power(MAKE_FIXED(/*v=*/20000, /*c=*/4000), &ma, &max_mv,
+			     &min_mv);
+	TEST_EQ(max_mv, 20000, "%d");
+	TEST_EQ(min_mv, 20000, "%d");
+	TEST_EQ(ma, 3000, "%d"); /* Capped at PD_MAX_CURRENT_MA */
+	pd_extract_pdo_power(MAKE_FIXED(/*v=*/10000, /*c=*/4000), &ma, &max_mv,
+			     &min_mv);
+	TEST_EQ(max_mv, 10000, "%d");
+	TEST_EQ(min_mv, 10000, "%d");
+	TEST_EQ(ma, 3000, "%d"); /* Capped at PD_MAX_CURRENT_MA */
+	pd_extract_pdo_power(MAKE_FIXED(/*v=*/21000, /*c=*/4000), &ma, &max_mv,
+			     &min_mv);
+	TEST_EQ(max_mv, 21000, "%d");
+	TEST_EQ(min_mv, 21000, "%d");
+	TEST_EQ(ma, 2857, "%d"); /* Capped at PD_MAX_POWER_MW */
+
+	pd_extract_pdo_power(MAKE_BATT(/*v_max=*/5700, /*v_min=*/3300,
+				       /*p=*/7000),
+			     &ma, &max_mv, &min_mv);
+	TEST_EQ(max_mv, 5700, "%d");
+	TEST_EQ(min_mv, 3300, "%d");
+	TEST_EQ(ma, 2121, "%d"); /* 3300mV * 2121mA ~= 7000mW */
+	pd_extract_pdo_power(MAKE_BATT(/*v_max=*/3300, /*v_min=*/2700,
+				       /*p=*/12000),
+			     &ma, &max_mv, &min_mv);
+	TEST_EQ(max_mv, 3300, "%d");
+	TEST_EQ(min_mv, 2700, "%d");
+	TEST_EQ(ma, 3000, "%d"); /* Capped at PD_MAX_CURRENT_MA */
+
+	pd_extract_pdo_power(MAKE_BATT(/*v_max=*/25000, /*v_min=*/21000,
+				       /*p=*/61000),
+			     &ma, &max_mv, &min_mv);
+	TEST_EQ(max_mv, 25000, "%d");
+	TEST_EQ(min_mv, 21000, "%d");
+	TEST_EQ(ma, 2857, "%d"); /* Capped at PD_MAX_POWER_MW */
+
+	pd_extract_pdo_power(MAKE_VAR(/*v_max=*/5000, /*v_min=*/3300,
+				      /*c=*/3000),
+			     &ma, &max_mv, &min_mv);
+	TEST_EQ(max_mv, 5000, "%d");
+	TEST_EQ(min_mv, 3300, "%d");
+	TEST_EQ(ma, 3000, "%d");
+	pd_extract_pdo_power(MAKE_VAR(/*v_max=*/20000, /*v_min=*/5000,
+				      /*c=*/2600),
+			     &ma, &max_mv, &min_mv);
+	TEST_EQ(max_mv, 20000, "%d");
+	TEST_EQ(min_mv, 5000, "%d");
+	TEST_EQ(ma, 2600, "%d");
+	pd_extract_pdo_power(MAKE_VAR(/*v_max=*/20000, /*v_min=*/5000,
+				      /*c=*/4000),
+			     &ma, &max_mv, &min_mv);
+	TEST_EQ(max_mv, 20000, "%d");
+	TEST_EQ(min_mv, 5000, "%d");
+	TEST_EQ(ma, 3000, "%d"); /* Capped at PD_MAX_CURRENT_MA */
+	pd_extract_pdo_power(MAKE_VAR(/*v_max=*/10000, /*v_min=*/3300,
+				      /*c=*/4000),
+			     &ma, &max_mv, &min_mv);
+	TEST_EQ(max_mv, 10000, "%d");
+	TEST_EQ(min_mv, 3300, "%d");
+	TEST_EQ(ma, 3000, "%d"); /* Capped at PD_MAX_CURRENT_MA */
+	pd_extract_pdo_power(MAKE_VAR(/*v_max=*/22000, /*v_min=*/21000,
+				      /*c=*/4000),
+			     &ma, &max_mv, &min_mv);
+	TEST_EQ(max_mv, 22000, "%d");
+	TEST_EQ(min_mv, 21000, "%d");
+	TEST_EQ(ma, 2857, "%d"); /* Capped at PD_MAX_POWER_MW */
+
+	pd_extract_pdo_power(MAKE_AUG(/*v_max=*/5000, /*v_min=*/3300,
+				      /*c=*/3000),
+			     &ma, &max_mv, &min_mv);
+	TEST_EQ(max_mv, 5000, "%d");
+	TEST_EQ(min_mv, 3300, "%d");
+	TEST_EQ(ma, 3000, "%d");
+	pd_extract_pdo_power(MAKE_AUG(/*v_max=*/20000, /*v_min=*/3300,
+				      /*c=*/2600),
+			     &ma, &max_mv, &min_mv);
+	TEST_EQ(max_mv, 20000, "%d");
+	TEST_EQ(min_mv, 3300, "%d");
+	TEST_EQ(ma, 2600, "%d");
+	pd_extract_pdo_power(MAKE_AUG(/*v_max=*/10000, /*v_min=*/3300,
+				      /*c=*/4000),
+			     &ma, &max_mv, &min_mv);
+	TEST_EQ(max_mv, 10000, "%d");
+	TEST_EQ(min_mv, 3300, "%d");
+	TEST_EQ(ma, 3000, "%d"); /* Capped at PD_MAX_CURRENT_MA */
+	pd_extract_pdo_power(MAKE_AUG(/*v_max=*/22000, /*v_min=*/21000,
+				      /*c=*/4000),
+			     &ma, &max_mv, &min_mv);
+	TEST_EQ(max_mv, 22000, "%d");
+	TEST_EQ(min_mv, 21000, "%d");
+	TEST_EQ(ma, 2857, "%d"); /* Capped at PD_MAX_POWER_MW */
+
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
 {
 	RUN_TEST(test_pd_get_cc_state);
+	RUN_TEST(test_pd_extract_pdo_power);
 
 	test_print_result();
 }
diff --git a/test/usb_pd.c b/test/usb_pd.c
index f572b5bb21..505b80e830 100644
--- a/test/usb_pd.c
+++ b/test/usb_pd.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -14,8 +14,8 @@
 #include "usb_pd_test_util.h"
 #include "util.h"
 
-#define PORT0	0
-#define PORT1	1
+#define PORT0 0
+#define PORT1 1
 
 #define BATTERY_DESIGN_VOLTAGE 7600
 #define BATTERY_DESIGN_CAPACITY 5131
@@ -87,7 +87,7 @@ int pd_adc_read(int port, int cc)
 		/* we are source connected to sink, return Rd/Open */
 		return (pd_port[port].partner_polarity == cc) ? 400 : 3000;
 	else if (!pd_port[port].host_mode &&
-		  pd_port[port].partner_role == PD_ROLE_SOURCE)
+		 pd_port[port].partner_role == PD_ROLE_SOURCE)
 		/* we are sink connected to source, return Rp/Open */
 		return (pd_port[port].partner_polarity == cc) ? 1700 : 0;
 	else if (pd_port[port].host_mode)
@@ -179,39 +179,38 @@ static void simulate_rx_msg(int port, uint16_t header, int cnt,
 
 static void simulate_wait(int port)
 {
-	uint16_t header = PD_HEADER(PD_CTRL_WAIT, PD_ROLE_SOURCE,
-				    PD_ROLE_DFP, pd_port[port].msg_rx_id,
-				    0, pd_port[port].rev, 0);
+	uint16_t header = PD_HEADER(PD_CTRL_WAIT, PD_ROLE_SOURCE, PD_ROLE_DFP,
+				    pd_port[port].msg_rx_id, 0,
+				    pd_port[port].rev, 0);
 
 	simulate_rx_msg(port, header, 0, NULL);
 }
 
 static void simulate_accept(int port)
 {
-	uint16_t header = PD_HEADER(PD_CTRL_ACCEPT, PD_ROLE_SOURCE,
-				PD_ROLE_DFP, pd_port[port].msg_rx_id,
-				0, pd_port[port].rev, 0);
+	uint16_t header = PD_HEADER(PD_CTRL_ACCEPT, PD_ROLE_SOURCE, PD_ROLE_DFP,
+				    pd_port[port].msg_rx_id, 0,
+				    pd_port[port].rev, 0);
 
 	simulate_rx_msg(port, header, 0, NULL);
 }
 
 static void simulate_reject(int port)
 {
-	uint16_t header = PD_HEADER(PD_CTRL_REJECT, PD_ROLE_SOURCE,
-				PD_ROLE_DFP, pd_port[port].msg_rx_id,
-				0, pd_port[port].rev, 0);
+	uint16_t header = PD_HEADER(PD_CTRL_REJECT, PD_ROLE_SOURCE, PD_ROLE_DFP,
+				    pd_port[port].msg_rx_id, 0,
+				    pd_port[port].rev, 0);
 
 	simulate_rx_msg(port, header, 0, NULL);
 }
 
-
 #ifdef CONFIG_USB_PD_REV30
 static void simulate_get_bat_cap(int port)
 {
 	uint16_t msg[2];
 	uint16_t header = PD_HEADER(PD_EXT_GET_BATTERY_CAP, PD_ROLE_SOURCE,
-			PD_ROLE_DFP, pd_port[port].msg_rx_id,
-			1, pd_port[port].rev, 1);
+				    PD_ROLE_DFP, pd_port[port].msg_rx_id, 1,
+				    pd_port[port].rev, 1);
 
 	/* set extended header */
 	msg[0] = PD_EXT_HEADER(0, 0, 1);
@@ -226,8 +225,8 @@ static void simulate_get_bat_status(int port)
 {
 	uint16_t msg[2];
 	uint16_t header = PD_HEADER(PD_EXT_GET_BATTERY_STATUS, PD_ROLE_SOURCE,
-			PD_ROLE_DFP, pd_port[port].msg_rx_id,
-			1, pd_port[port].rev, 1);
+				    PD_ROLE_DFP, pd_port[port].msg_rx_id, 1,
+				    pd_port[port].rev, 1);
 
 	/* set extended header */
 	msg[0] = PD_EXT_HEADER(0, 0, 1);
@@ -252,18 +251,20 @@ static void simulate_source_cap(int port, uint32_t cnt)
 
 static void simulate_goodcrc(int port, int role, int id)
 {
-	simulate_rx_msg(port, PD_HEADER(PD_CTRL_GOOD_CRC, role, role, id, 0,
-					pd_port[port].rev, 0), 0, NULL);
+	simulate_rx_msg(port,
+			PD_HEADER(PD_CTRL_GOOD_CRC, role, role, id, 0,
+				  pd_port[port].rev, 0),
+			0, NULL);
 }
 
 static int verify_goodcrc(int port, int role, int id)
 {
-
 	return pd_test_tx_msg_verify_sop(port) &&
-		pd_test_tx_msg_verify_short(port, PD_HEADER(PD_CTRL_GOOD_CRC,
-					role, role, id, 0, 0, 0)) &&
-		pd_test_tx_msg_verify_crc(port) &&
-		pd_test_tx_msg_verify_eop(port);
+	       pd_test_tx_msg_verify_short(port,
+					   PD_HEADER(PD_CTRL_GOOD_CRC, role,
+						     role, id, 0, 0, 0)) &&
+	       pd_test_tx_msg_verify_crc(port) &&
+	       pd_test_tx_msg_verify_eop(port);
 }
 
 static void plug_in_source(int port, int polarity)
@@ -272,7 +273,7 @@ static void plug_in_source(int port, int polarity)
 	pd_port[port].partner_role = PD_ROLE_SOURCE;
 	pd_port[port].partner_polarity = polarity;
 	/* Indicate that the CC lines have changed. */
-	task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_CC, 0);
+	task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_CC);
 }
 
 static void plug_in_sink(int port, int polarity)
@@ -281,7 +282,7 @@ static void plug_in_sink(int port, int polarity)
 	pd_port[port].partner_role = PD_ROLE_SINK;
 	pd_port[port].partner_polarity = polarity;
 	/* Indicate that the CC lines have changed. */
-	task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_CC, 0);
+	task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_CC);
 }
 
 static void unplug(int port)
@@ -291,12 +292,12 @@ static void unplug(int port)
 	pd_port[port].has_vbus = 0;
 	pd_port[port].partner_role = -1;
 	/* Indicate that the CC lines have changed. */
-	task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_CC, 0);
+	task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_CC);
 	task_wake(PD_PORT_TO_TASK_ID(port));
 	usleep(30 * MSEC);
 }
 
-void pd_snk_give_back(int port, uint32_t * const ma, uint32_t * const mv)
+void pd_snk_give_back(int port, uint32_t *const ma, uint32_t *const mv)
 {
 	if (*ma == 3000)
 		give_back_called = 1;
@@ -304,9 +305,9 @@ void pd_snk_give_back(int port, uint32_t * const ma, uint32_t * const mv)
 
 static void simulate_ps_rdy(int port)
 {
-	uint16_t header = PD_HEADER(PD_CTRL_PS_RDY, PD_ROLE_SOURCE,
-				PD_ROLE_DFP, pd_port[port].msg_rx_id,
-				0, pd_port[port].rev, 0);
+	uint16_t header = PD_HEADER(PD_CTRL_PS_RDY, PD_ROLE_SOURCE, PD_ROLE_DFP,
+				    pd_port[port].msg_rx_id, 0,
+				    pd_port[port].rev, 0);
 
 	simulate_rx_msg(port, header, 0, NULL);
 }
@@ -314,7 +315,8 @@ static void simulate_ps_rdy(int port)
 static void simulate_goto_min(int port)
 {
 	uint16_t header = PD_HEADER(PD_CTRL_GOTO_MIN, PD_ROLE_SOURCE,
-		PD_ROLE_DFP, pd_port[port].msg_rx_id, 0, pd_port[port].rev, 0);
+				    PD_ROLE_DFP, pd_port[port].msg_rx_id, 0,
+				    pd_port[port].rev, 0);
 
 	simulate_rx_msg(port, header, 0, NULL);
 }
@@ -324,8 +326,9 @@ static int test_request_with_wait_and_contract(void)
 #ifdef CONFIG_USB_PD_REV30
 	uint32_t expected_status_bsdo =
 		BSDO_CAP(DIV_ROUND_NEAREST(BATTERY_REMAINING_CAPACITY *
-					BATTERY_DESIGN_VOLTAGE, 100000)) |
-					BSDO_PRESENT;
+						   BATTERY_DESIGN_VOLTAGE,
+					   100000)) |
+		BSDO_PRESENT;
 	uint16_t expected_cap_hdr = PD_EXT_HEADER(0, 0, 9);
 	uint16_t expected_cap_vid = USB_VID_GOOGLE;
 #ifdef CONFIG_USB_PID
@@ -333,12 +336,10 @@ static int test_request_with_wait_and_contract(void)
 #else
 	uint16_t expected_cap_pid = 0;
 #endif
-	uint16_t expected_cap_des =
-		DIV_ROUND_NEAREST(BATTERY_DESIGN_CAPACITY *
-			BATTERY_DESIGN_VOLTAGE, 100000);
-	uint16_t expected_cap_ful =
-		DIV_ROUND_NEAREST(BATTERY_FULL_CHARGE_CAPACITY *
-			BATTERY_DESIGN_VOLTAGE, 100000);
+	uint16_t expected_cap_des = DIV_ROUND_NEAREST(
+		BATTERY_DESIGN_CAPACITY * BATTERY_DESIGN_VOLTAGE, 100000);
+	uint16_t expected_cap_ful = DIV_ROUND_NEAREST(
+		BATTERY_FULL_CHARGE_CAPACITY * BATTERY_DESIGN_VOLTAGE, 100000);
 	uint16_t expected_cap_type = 0;
 #endif
 
@@ -358,8 +359,8 @@ static int test_request_with_wait_and_contract(void)
 	/* We're in SNK_DISCOVERY now. Let's send the source cap. */
 	simulate_source_cap(port, 1);
 	task_wait_event(30 * MSEC);
-	TEST_ASSERT(verify_goodcrc(port, PD_ROLE_SINK,
-						pd_port[port].msg_rx_id));
+	TEST_ASSERT(
+		verify_goodcrc(port, PD_ROLE_SINK, pd_port[port].msg_rx_id));
 
 	/* Wait for the power request */
 	task_wake(PD_PORT_TO_TASK_ID(port));
@@ -368,9 +369,10 @@ static int test_request_with_wait_and_contract(void)
 
 	/* Process the request */
 	TEST_ASSERT(pd_test_tx_msg_verify_sop(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
-			PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
-			pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
+	TEST_ASSERT(pd_test_tx_msg_verify_short(
+		port,
+		PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
+			  pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
 	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_rdo));
 	TEST_ASSERT(pd_test_tx_msg_verify_crc(port));
 	TEST_ASSERT(pd_test_tx_msg_verify_eop(port));
@@ -399,8 +401,8 @@ static int test_request_with_wait_and_contract(void)
 	 */
 	simulate_source_cap(port, 1);
 	task_wait_event(30 * MSEC);
-	TEST_ASSERT(verify_goodcrc(port, PD_ROLE_SINK,
-					pd_port[port].msg_rx_id));
+	TEST_ASSERT(
+		verify_goodcrc(port, PD_ROLE_SINK, pd_port[port].msg_rx_id));
 
 	/* Wait for the power request */
 	task_wake(PD_PORT_TO_TASK_ID(port));
@@ -409,9 +411,10 @@ static int test_request_with_wait_and_contract(void)
 
 	/* Process the request */
 	TEST_ASSERT(pd_test_tx_msg_verify_sop(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
-			PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
-			pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
+	TEST_ASSERT(pd_test_tx_msg_verify_short(
+		port,
+		PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
+			  pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
 	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_rdo));
 	TEST_ASSERT(pd_test_tx_msg_verify_crc(port));
 	TEST_ASSERT(pd_test_tx_msg_verify_eop(port));
@@ -441,11 +444,10 @@ static int test_request_with_wait_and_contract(void)
 	/* We had an explicit contract. So request should have been resent. */
 	/* Process the request */
 	TEST_ASSERT(pd_test_tx_msg_verify_sop(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
-			PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
-			pd_port[port].msg_tx_id, 1,
-			pd_port[port].rev, 0
-	)));
+	TEST_ASSERT(pd_test_tx_msg_verify_short(
+		port,
+		PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
+			  pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
 	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_rdo));
 	TEST_ASSERT(pd_test_tx_msg_verify_crc(port));
 	TEST_ASSERT(pd_test_tx_msg_verify_eop(port));
@@ -492,9 +494,10 @@ static int test_request_with_wait_and_contract(void)
 
 	/* Process the request */
 	TEST_ASSERT(pd_test_tx_msg_verify_sop(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
+	TEST_ASSERT(pd_test_tx_msg_verify_short(
+		port,
 		PD_HEADER(PD_EXT_BATTERY_CAP, PD_ROLE_SINK, PD_ROLE_UFP,
-		pd_port[port].msg_tx_id, 3, pd_port[port].rev, 1)));
+			  pd_port[port].msg_tx_id, 3, pd_port[port].rev, 1)));
 	TEST_ASSERT(pd_test_tx_msg_verify_short(port, expected_cap_hdr));
 	TEST_ASSERT(pd_test_tx_msg_verify_short(port, expected_cap_vid));
 	TEST_ASSERT(pd_test_tx_msg_verify_short(port, expected_cap_pid));
@@ -524,9 +527,10 @@ static int test_request_with_wait_and_contract(void)
 
 	/* Process the request */
 	TEST_ASSERT(pd_test_tx_msg_verify_sop(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
+	TEST_ASSERT(pd_test_tx_msg_verify_short(
+		port,
 		PD_HEADER(PD_DATA_BATTERY_STATUS, PD_ROLE_SINK, PD_ROLE_UFP,
-		pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
+			  pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
 	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_status_bsdo));
 	TEST_ASSERT(pd_test_tx_msg_verify_crc(port));
 	TEST_ASSERT(pd_test_tx_msg_verify_eop(port));
@@ -564,7 +568,7 @@ static int test_request_with_wait(void)
 {
 #ifdef CONFIG_USB_PD_GIVE_BACK
 	uint32_t expected_rdo = RDO_FIXED(1, 900, PD_MIN_CURRENT_MA,
-					RDO_CAP_MISMATCH | RDO_GIVE_BACK);
+					  RDO_CAP_MISMATCH | RDO_GIVE_BACK);
 #else
 	uint32_t expected_rdo = RDO_FIXED(1, 900, 900, RDO_CAP_MISMATCH);
 #endif
@@ -578,8 +582,8 @@ static int test_request_with_wait(void)
 	/* We're in SNK_DISCOVERY now. Let's send the source cap. */
 	simulate_source_cap(port, 0);
 	task_wait_event(30 * MSEC);
-	TEST_ASSERT(verify_goodcrc(port,
-			PD_ROLE_SINK, pd_port[port].msg_rx_id));
+	TEST_ASSERT(
+		verify_goodcrc(port, PD_ROLE_SINK, pd_port[port].msg_rx_id));
 
 	/* Wait for the power request */
 	task_wake(PD_PORT_TO_TASK_ID(port));
@@ -588,9 +592,10 @@ static int test_request_with_wait(void)
 
 	/* Process the request */
 	TEST_ASSERT(pd_test_tx_msg_verify_sop(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
-			PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
-			pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
+	TEST_ASSERT(pd_test_tx_msg_verify_short(
+		port,
+		PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
+			  pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
 	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_rdo));
 	TEST_ASSERT(pd_test_tx_msg_verify_crc(port));
 	TEST_ASSERT(pd_test_tx_msg_verify_eop(port));
@@ -617,8 +622,8 @@ static int test_request_with_wait(void)
 	/* Resend Source Cap. */
 	simulate_source_cap(port, 0);
 	task_wait_event(30 * MSEC);
-	TEST_ASSERT(verify_goodcrc(port,
-			PD_ROLE_SINK, pd_port[port].msg_rx_id));
+	TEST_ASSERT(
+		verify_goodcrc(port, PD_ROLE_SINK, pd_port[port].msg_rx_id));
 
 	/* Wait for the power request */
 	task_wake(PD_PORT_TO_TASK_ID(port));
@@ -627,9 +632,10 @@ static int test_request_with_wait(void)
 
 	/* Process the request */
 	TEST_ASSERT(pd_test_tx_msg_verify_sop(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
-			PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
-			pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
+	TEST_ASSERT(pd_test_tx_msg_verify_short(
+		port,
+		PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
+			  pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
 	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_rdo));
 	TEST_ASSERT(pd_test_tx_msg_verify_crc(port));
 	TEST_ASSERT(pd_test_tx_msg_verify_eop(port));
@@ -652,7 +658,7 @@ static int test_request_with_wait_no_src_cap(void)
 {
 #ifdef CONFIG_USB_PD_GIVE_BACK
 	uint32_t expected_rdo = RDO_FIXED(1, 900, PD_MIN_CURRENT_MA,
-					RDO_CAP_MISMATCH | RDO_GIVE_BACK);
+					  RDO_CAP_MISMATCH | RDO_GIVE_BACK);
 #else
 	uint32_t expected_rdo = RDO_FIXED(1, 900, 900, RDO_CAP_MISMATCH);
 #endif
@@ -666,8 +672,8 @@ static int test_request_with_wait_no_src_cap(void)
 	/* We're in SNK_DISCOVERY now. Let's send the source cap. */
 	simulate_source_cap(port, 0);
 	task_wait_event(30 * MSEC);
-	TEST_ASSERT(verify_goodcrc(port,
-			PD_ROLE_SINK, pd_port[port].msg_rx_id));
+	TEST_ASSERT(
+		verify_goodcrc(port, PD_ROLE_SINK, pd_port[port].msg_rx_id));
 
 	/* Wait for the power request */
 	task_wake(PD_PORT_TO_TASK_ID(port));
@@ -676,9 +682,10 @@ static int test_request_with_wait_no_src_cap(void)
 
 	/* Process the request */
 	TEST_ASSERT(pd_test_tx_msg_verify_sop(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
-			PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
-			pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
+	TEST_ASSERT(pd_test_tx_msg_verify_short(
+		port,
+		PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
+			  pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
 	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_rdo));
 	TEST_ASSERT(pd_test_tx_msg_verify_crc(port));
 	TEST_ASSERT(pd_test_tx_msg_verify_eop(port));
@@ -711,9 +718,10 @@ static int test_request_with_wait_no_src_cap(void)
 
 	/* Process the request */
 	TEST_ASSERT(pd_test_tx_msg_verify_sop(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
-			PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
-			pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
+	TEST_ASSERT(pd_test_tx_msg_verify_short(
+		port,
+		PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
+			  pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
 	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_rdo));
 	TEST_ASSERT(pd_test_tx_msg_verify_crc(port));
 	TEST_ASSERT(pd_test_tx_msg_verify_eop(port));
@@ -736,7 +744,7 @@ static int test_request_with_reject(void)
 {
 #ifdef CONFIG_USB_PD_GIVE_BACK
 	uint32_t expected_rdo = RDO_FIXED(1, 900, PD_MIN_CURRENT_MA,
-					RDO_CAP_MISMATCH | RDO_GIVE_BACK);
+					  RDO_CAP_MISMATCH | RDO_GIVE_BACK);
 #else
 	uint32_t expected_rdo = RDO_FIXED(1, 900, 900, RDO_CAP_MISMATCH);
 #endif
@@ -750,8 +758,8 @@ static int test_request_with_reject(void)
 	/* We're in SNK_DISCOVERY now. Let's send the source cap. */
 	simulate_source_cap(port, 0);
 	task_wait_event(30 * MSEC);
-	TEST_ASSERT(verify_goodcrc(port,
-			PD_ROLE_SINK, pd_port[port].msg_rx_id));
+	TEST_ASSERT(
+		verify_goodcrc(port, PD_ROLE_SINK, pd_port[port].msg_rx_id));
 
 	/* Wait for the power request */
 	task_wake(PD_PORT_TO_TASK_ID(port));
@@ -760,9 +768,10 @@ static int test_request_with_reject(void)
 
 	/* Process the request */
 	TEST_ASSERT(pd_test_tx_msg_verify_sop(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
-			PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
-			pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
+	TEST_ASSERT(pd_test_tx_msg_verify_short(
+		port,
+		PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
+			  pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
 	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_rdo));
 	TEST_ASSERT(pd_test_tx_msg_verify_crc(port));
 	TEST_ASSERT(pd_test_tx_msg_verify_eop(port));
@@ -788,8 +797,8 @@ static int test_request_with_reject(void)
 	/* We're in SNK_READY. Send source cap. again. */
 	simulate_source_cap(port, 0);
 	task_wait_event(30 * MSEC);
-	TEST_ASSERT(verify_goodcrc(port,
-			PD_ROLE_SINK, pd_port[port].msg_rx_id));
+	TEST_ASSERT(
+		verify_goodcrc(port, PD_ROLE_SINK, pd_port[port].msg_rx_id));
 
 	/* Wait for the power request */
 	task_wake(PD_PORT_TO_TASK_ID(port));
@@ -798,9 +807,10 @@ static int test_request_with_reject(void)
 
 	/* Process the request */
 	TEST_ASSERT(pd_test_tx_msg_verify_sop(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
-			PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
-			pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
+	TEST_ASSERT(pd_test_tx_msg_verify_short(
+		port,
+		PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
+			  pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
 	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_rdo));
 	TEST_ASSERT(pd_test_tx_msg_verify_crc(port));
 	TEST_ASSERT(pd_test_tx_msg_verify_eop(port));
@@ -814,7 +824,7 @@ static int test_request(void)
 {
 #ifdef CONFIG_USB_PD_GIVE_BACK
 	uint32_t expected_rdo = RDO_FIXED(1, 900, PD_MIN_CURRENT_MA,
-					RDO_CAP_MISMATCH | RDO_GIVE_BACK);
+					  RDO_CAP_MISMATCH | RDO_GIVE_BACK);
 #else
 	uint32_t expected_rdo = RDO_FIXED(1, 900, 900, RDO_CAP_MISMATCH);
 #endif
@@ -828,8 +838,8 @@ static int test_request(void)
 	/* We're in SNK_DISCOVERY now. Let's send the source cap. */
 	simulate_source_cap(port, 0);
 	task_wait_event(30 * MSEC);
-	TEST_ASSERT(verify_goodcrc(port,
-				PD_ROLE_SINK, pd_port[port].msg_rx_id));
+	TEST_ASSERT(
+		verify_goodcrc(port, PD_ROLE_SINK, pd_port[port].msg_rx_id));
 
 	/* Wait for the power request */
 	task_wake(PD_PORT_TO_TASK_ID(port));
@@ -838,9 +848,10 @@ static int test_request(void)
 
 	/* Process the request */
 	TEST_ASSERT(pd_test_tx_msg_verify_sop(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
-			PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
-			pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
+	TEST_ASSERT(pd_test_tx_msg_verify_short(
+		port,
+		PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
+			  pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
 	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_rdo));
 	TEST_ASSERT(pd_test_tx_msg_verify_crc(port));
 	TEST_ASSERT(pd_test_tx_msg_verify_eop(port));
@@ -872,10 +883,10 @@ static int test_sink(void)
 
 	/* The source cap should be sent */
 	TEST_ASSERT(pd_test_tx_msg_verify_sop(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
-			PD_HEADER(PD_DATA_SOURCE_CAP, PD_ROLE_SOURCE,
-				  PD_ROLE_DFP, pd_port[port].msg_tx_id,
-				  pd_src_pdo_cnt, pd_port[port].rev, 0)));
+	TEST_ASSERT(pd_test_tx_msg_verify_short(
+		port, PD_HEADER(PD_DATA_SOURCE_CAP, PD_ROLE_SOURCE, PD_ROLE_DFP,
+				pd_port[port].msg_tx_id, pd_src_pdo_cnt,
+				pd_port[port].rev, 0)));
 
 	for (i = 0; i < pd_src_pdo_cnt; ++i)
 		TEST_ASSERT(pd_test_tx_msg_verify_word(port, pd_src_pdo[i]));
@@ -900,7 +911,7 @@ static int test_sink(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 	init_ports();
diff --git a/test/usb_pd.tasklist b/test/usb_pd.tasklist
index fbd319148e..6ba85de1aa 100644
--- a/test/usb_pd.tasklist
+++ b/test/usb_pd.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/usb_pd_console.c b/test/usb_pd_console.c
index 800eae7b3d..119fe7131d 100644
--- a/test/usb_pd_console.c
+++ b/test/usb_pd_console.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,32 +10,165 @@
 #include "stdio.h"
 #include "stdlib.h"
 #include "string.h"
-#include "usb_pe_sm.h"
+#include "test_util.h"
 #include "usb_pd.h"
+#include "usb_pe_sm.h"
 #include "usb_tc_sm.h"
 #include "util.h"
-#include "test_util.h"
 
 /* Defined in implementation */
-int hex8tou32(char *str, uint32_t *val);
-int command_pd(int argc, char **argv);
-int remote_flashing(int argc, char **argv);
+int command_pd(int argc, const char **argv);
+
+static enum debug_level dpm_debug_level;
+static enum debug_level prl_debug_level;
+static enum debug_level pe_debug_level;
+static enum debug_level tc_debug_level;
+
+static bool pd_get_polarity_called;
+static bool pd_comm_is_enabled_called;
+static bool pd_get_power_role_called;
+static bool pd_get_data_role_called;
+static bool tc_is_vconn_src_called;
+static bool tc_get_current_state_called;
+static bool tc_get_flags_called;
+static bool pe_get_current_state_called;
+static bool pe_get_flags_called;
+static bool pe_is_explicit_contract_called;
+static bool pe_snk_in_epr_mode_called;
+static bool pe_snk_epr_explicit_exit_called;
+static bool pd_get_dual_role_called;
+static bool board_get_usb_pd_port_count_called;
+static bool pd_srccaps_dump_called;
+static bool pd_timer_dump_called;
 
 static enum try_src_override_t try_src_override;
 static int test_port;
 static enum pd_dpm_request request;
 static int max_volt;
 static int comm_enable;
+static int pd_suspended;
+static int pd_bistsharemode;
 static int dev_info;
 static int vdm_cmd;
 static int vdm_count;
 static int vdm_vid;
 static uint32_t vdm_data[10];
 static enum pd_dual_role_states dr_state;
+static enum pd_power_role pd_get_power_role_return = PD_ROLE_SINK;
 
 /* Mock functions */
+int tc_is_vconn_src(int port)
+{
+	tc_is_vconn_src_called = true;
+	return 0;
+}
+
+enum pd_power_role pd_get_power_role(int port)
+{
+	pd_get_power_role_called = true;
+	return pd_get_power_role_return;
+}
+
+uint32_t pe_get_flags(int port)
+{
+	pe_get_flags_called = true;
+	return 0;
+}
+
+int pe_is_explicit_contract(int port)
+{
+	pe_is_explicit_contract_called = true;
+	return 1;
+}
+
+bool pe_snk_in_epr_mode(int port)
+{
+	pe_snk_in_epr_mode_called = true;
+	return true;
+}
+
+void pe_snk_epr_explicit_exit(int port)
+{
+	pe_snk_epr_explicit_exit_called = true;
+}
+
+const char *pe_get_current_state(int port)
+{
+	pe_get_current_state_called = true;
+	return "PE_STATE";
+}
+
+enum pd_dual_role_states pd_get_dual_role(int port)
+{
+	pd_get_dual_role_called = true;
+	return 0;
+}
+
+void pd_timer_dump(int port)
+{
+	pd_timer_dump_called = true;
+}
+
+void pd_srccaps_dump(int port)
+{
+	pd_srccaps_dump_called = true;
+}
+
+void dpm_set_debug_level(enum debug_level level)
+{
+	dpm_debug_level = level;
+}
+
+void prl_set_debug_level(enum debug_level level)
+{
+	prl_debug_level = level;
+}
+
+void pe_set_debug_level(enum debug_level level)
+{
+	pe_debug_level = level;
+}
+
+void tc_set_debug_level(enum debug_level level)
+{
+	tc_debug_level = level;
+}
+
+enum pd_data_role pd_get_data_role(int port)
+{
+	pd_get_data_role_called = true;
+	return 0;
+}
+
+void tc_state_init(int port)
+{
+}
+
+void tc_event_check(int port, int evt)
+{
+}
+
+uint8_t tc_get_pd_enabled(int port)
+{
+	return 0;
+}
+
+void pe_run(int port, int evt, int en)
+{
+}
+
+void tc_run(int port)
+{
+}
+
+uint8_t board_get_usb_pd_port_count(void)
+{
+	board_get_usb_pd_port_count_called = true;
+	return CONFIG_USB_PD_PORT_MAX_COUNT;
+}
+
 void pe_send_vdm(int port, uint32_t vid, int cmd, const uint32_t *data,
-					int count)
+		 int count)
 {
 	int i;
 
@@ -75,6 +208,18 @@ void pd_comm_enable(int port, int enable)
 	comm_enable = enable;
 }
 
+void pd_set_suspend(int port, int enable)
+{
+	test_port = port;
+	pd_suspended = enable;
+}
+
+enum ec_status pd_set_bist_share_mode(uint8_t enable)
+{
+	pd_bistsharemode = enable;
+	return EC_RES_SUCCESS;
+}
+
 void tc_print_dev_info(int port)
 {
 	test_port = port;
@@ -90,25 +235,29 @@ void pd_set_dual_role(int port, enum pd_dual_role_states state)
 int pd_comm_is_enabled(int port)
 {
 	test_port = port;
+	pd_comm_is_enabled_called = true;
 	return 0;
 }
 
-int pd_get_polarity(int port)
+enum tcpc_cc_polarity pd_get_polarity(int port)
 {
 	test_port = port;
+	pd_get_polarity_called = true;
 	return 0;
 }
 
 uint32_t tc_get_flags(int port)
 {
 	test_port = port;
+	tc_get_flags_called = true;
 	return 0;
 }
 
 const char *tc_get_current_state(int port)
 {
 	test_port = port;
-	return 0;
+	tc_get_current_state_called = true;
+	return "TC_STATE";
 }
 
 void tc_try_src_override(enum try_src_override_t ov)
@@ -132,48 +281,45 @@ enum try_src_override_t tc_get_try_src_override(void)
 	return try_src_override;
 }
 
-static int test_hex8tou32(void)
+enum pd_cc_states pd_get_task_cc_state(int port)
 {
-	char const *tst_str[] = {"01234567", "89abcdef",
-					"AABBCCDD", "EEFF0011"};
-	uint32_t const tst_int[] = {0x01234567, 0x89abcdef,
-					0xaabbccdd, 0xeeff0011};
-	uint32_t val;
-	int i;
-
-	for (i = 0; i < 4; i++) {
-		hex8tou32(tst_str[i], &val);
-		TEST_ASSERT(val == tst_int[i]);
-	}
-
-	return EC_SUCCESS;
-}
-
-static int test_command_pd_arg_count(void)
-{
-	int argc;
-	char const *argv[] = {"pd", "", 0, 0, 0};
-
-	for (argc = 0; argc < 3; argc++)
-		TEST_ASSERT(command_pd(argc, argv) == EC_ERROR_PARAM_COUNT);
-
-	return EC_SUCCESS;
+	return PD_CC_NONE;
 }
 
-static int test_command_pd_port_num(void)
+static int test_command_pd_dump(void)
 {
 	int argc = 3;
-	char const *argv[10] = {"pd", "5", 0, 0, 0};
+	const char *argv[] = { "pd", "dump", "", 0, 0, 0 };
+	char test[2];
 
+	sprintf(test, "e");
+	argv[2] = test;
 	TEST_ASSERT(command_pd(argc, argv) == EC_ERROR_PARAM2);
 
+	for (int i = DEBUG_DISABLE; i <= DEBUG_LEVEL_MAX; i++) {
+		sprintf(test, "%d", i);
+		argv[2] = test;
+		TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
+		TEST_ASSERT(dpm_debug_level == i);
+		TEST_ASSERT(prl_debug_level == i);
+		TEST_ASSERT(pe_debug_level == i);
+		TEST_ASSERT(tc_debug_level == i);
+	}
+
+	sprintf(test, "%d", DEBUG_LEVEL_MAX + 1);
+	argv[2] = test;
+	TEST_ASSERT(dpm_debug_level == DEBUG_LEVEL_MAX);
+	TEST_ASSERT(prl_debug_level == DEBUG_LEVEL_MAX);
+	TEST_ASSERT(pe_debug_level == DEBUG_LEVEL_MAX);
+	TEST_ASSERT(tc_debug_level == DEBUG_LEVEL_MAX);
+
 	return EC_SUCCESS;
 }
 
 static int test_command_pd_try_src(void)
 {
 	int argc = 3;
-	char const *argv[] = {"pd", "trysrc", "2", 0, 0};
+	const char *argv[] = { "pd", "trysrc", "2", 0, 0 };
 
 	try_src_override = 0;
 	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
@@ -190,10 +336,68 @@ static int test_command_pd_try_src(void)
 	return EC_SUCCESS;
 }
 
+static int test_command_pd_version(void)
+{
+	int argc = 2;
+	const char *argv[] = { "pd", "version", 0, 0, 0 };
+
+	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
+
+	return EC_SUCCESS;
+}
+
+static int test_command_pd_bistsharemode_enable(void)
+{
+	int argc = 3;
+	static const char *argv[10] = { "pd", "bistsharemode", "enable" };
+
+	pd_bistsharemode = -1;
+	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
+	TEST_ASSERT(pd_bistsharemode == 1);
+
+	return EC_SUCCESS;
+}
+
+static int test_command_pd_bistsharemode_disable(void)
+{
+	int argc = 3;
+	static const char *argv[10] = { "pd", "bistsharemode", "disable" };
+
+	pd_bistsharemode = -1;
+	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
+	TEST_ASSERT(pd_bistsharemode == 0);
+
+	return EC_SUCCESS;
+}
+
+static int test_command_pd_arg_count(void)
+{
+	int argc;
+	const char *argv[] = { "pd", "", 0, 0, 0 };
+
+	for (argc = 0; argc < 3; argc++)
+		TEST_ASSERT(command_pd(argc, argv) == EC_ERROR_PARAM_COUNT);
+
+	return EC_SUCCESS;
+}
+
+static int test_command_pd_port_num(void)
+{
+	int argc = 3;
+	const char *argv[10] = { "pd", "0", 0, 0, 0 };
+	char test[2];
+
+	sprintf(test, "%d", CONFIG_USB_PD_PORT_MAX_COUNT);
+	argv[1] = test;
+	TEST_ASSERT(command_pd(argc, argv) == EC_ERROR_PARAM2);
+
+	return EC_SUCCESS;
+}
+
 static int test_command_pd_tx(void)
 {
 	int argc = 3;
-	char const *argv[] = {"pd", "0", "tx", 0, 0};
+	const char *argv[] = { "pd", "0", "tx", 0, 0 };
 
 	request = 0;
 	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
@@ -206,7 +410,7 @@ static int test_command_pd_tx(void)
 static int test_command_pd_charger(void)
 {
 	int argc = 3;
-	char const *argv[] = {"pd", "1", "charger", 0, 0};
+	const char *argv[] = { "pd", "1", "charger", 0, 0 };
 
 	request = 0;
 	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
@@ -219,7 +423,7 @@ static int test_command_pd_charger(void)
 static int test_command_pd_dev1(void)
 {
 	int argc = 4;
-	char const *argv[] = {"pd", "0", "dev", "20", 0};
+	const char *argv[] = { "pd", "0", "dev", "20", 0 };
 
 	request = 0;
 	max_volt = 0;
@@ -234,7 +438,7 @@ static int test_command_pd_dev1(void)
 static int test_command_pd_dev2(void)
 {
 	int argc = 3;
-	char const *argv[] = {"pd", "1", "dev", 0, 0};
+	const char *argv[] = { "pd", "1", "dev", 0, 0 };
 
 	request = 0;
 	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
@@ -248,7 +452,7 @@ static int test_command_pd_dev2(void)
 static int test_command_pd_disable(void)
 {
 	int argc = 3;
-	char const *argv[] = {"pd", "0", "disable", 0, 0};
+	const char *argv[] = { "pd", "0", "disable", 0, 0 };
 
 	comm_enable = 1;
 	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
@@ -261,7 +465,7 @@ static int test_command_pd_disable(void)
 static int test_command_pd_enable(void)
 {
 	int argc = 3;
-	char const *argv[] = {"pd", "1", "enable", 0, 0};
+	const char *argv[] = { "pd", "1", "enable", 0, 0 };
 
 	comm_enable = 0;
 	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
@@ -274,7 +478,7 @@ static int test_command_pd_enable(void)
 static int test_command_pd_hard(void)
 {
 	int argc = 3;
-	char const *argv[] = {"pd", "0", "hard", 0, 0};
+	const char *argv[] = { "pd", "0", "hard", 0, 0 };
 
 	request = 0;
 	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
@@ -287,7 +491,7 @@ static int test_command_pd_hard(void)
 static int test_command_pd_soft(void)
 {
 	int argc = 3;
-	char const *argv[] = {"pd", "0", "soft", 0, 0};
+	const char *argv[] = { "pd", "0", "soft", 0, 0 };
 
 	request = 0;
 	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
@@ -297,10 +501,42 @@ static int test_command_pd_soft(void)
 	return EC_SUCCESS;
 }
 
+static int test_command_pd_suspend(void)
+{
+	int argc = 3;
+	static const char *argv[] = { "pd", "0", "suspend" };
+
+	test_port = -1;
+	comm_enable = -1;
+	pd_suspended = -1;
+	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
+	TEST_ASSERT(test_port == 0);
+	TEST_ASSERT(comm_enable == 0);
+	TEST_ASSERT(pd_suspended == 1);
+
+	return EC_SUCCESS;
+}
+
+static int test_command_pd_resume(void)
+{
+	int argc = 3;
+	static const char *argv[] = { "pd", "1", "resume" };
+
+	test_port = -1;
+	comm_enable = -1;
+	pd_suspended = -1;
+	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
+	TEST_ASSERT(test_port == 1);
+	TEST_ASSERT(comm_enable == 1);
+	TEST_ASSERT(pd_suspended == 0);
+
+	return EC_SUCCESS;
+}
+
 static int test_command_pd_swap1(void)
 {
 	int argc = 3;
-	char const *argv[] = {"pd", "0", "swap", 0, 0};
+	const char *argv[] = { "pd", "0", "swap", 0, 0 };
 
 	TEST_ASSERT(command_pd(argc, argv) == EC_ERROR_PARAM_COUNT);
 
@@ -310,7 +546,7 @@ static int test_command_pd_swap1(void)
 static int test_command_pd_swap2(void)
 {
 	int argc = 4;
-	char const *argv[] = {"pd", "0", "swap", "power", 0};
+	const char *argv[] = { "pd", "0", "swap", "power", 0 };
 
 	request = 0;
 	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
@@ -323,7 +559,7 @@ static int test_command_pd_swap2(void)
 static int test_command_pd_swap3(void)
 {
 	int argc = 4;
-	char const *argv[] = {"pd", "1", "swap", "data", 0};
+	const char *argv[] = { "pd", "1", "swap", "data", 0 };
 
 	request = 0;
 	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
@@ -336,7 +572,7 @@ static int test_command_pd_swap3(void)
 static int test_command_pd_swap4(void)
 {
 	int argc = 4;
-	char const *argv[] = {"pd", "0", "swap", "vconn", 0};
+	const char *argv[] = { "pd", "0", "swap", "vconn", 0 };
 
 	request = 0;
 	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
@@ -349,17 +585,27 @@ static int test_command_pd_swap4(void)
 static int test_command_pd_swap5(void)
 {
 	int argc = 4;
-	char const *argv[] = {"pd", "0", "swap", "xyz", 0};
+	const char *argv[] = { "pd", "0", "swap", "xyz", 0 };
 
 	TEST_ASSERT(command_pd(argc, argv) == EC_ERROR_PARAM3);
 
 	return EC_SUCCESS;
 }
 
+static int test_command_pd_dualrole0(void)
+{
+	int argc = 3;
+	const char *argv[] = { "pd", "0", "dualrole", 0, 0 };
+
+	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
+
+	return EC_SUCCESS;
+}
+
 static int test_command_pd_dualrole1(void)
 {
 	int argc = 4;
-	char const *argv[] = {"pd", "0", "dualrole", "on", 0};
+	const char *argv[] = { "pd", "0", "dualrole", "on", 0 };
 
 	dr_state = 0;
 	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
@@ -372,7 +618,7 @@ static int test_command_pd_dualrole1(void)
 static int test_command_pd_dualrole2(void)
 {
 	int argc = 4;
-	char const *argv[] = {"pd", "0", "dualrole", "off", 0};
+	const char *argv[] = { "pd", "0", "dualrole", "off", 0 };
 
 	dr_state = 0;
 	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
@@ -385,7 +631,7 @@ static int test_command_pd_dualrole2(void)
 static int test_command_pd_dualrole3(void)
 {
 	int argc = 4;
-	char const *argv[] = {"pd", "0", "dualrole", "freeze", 0};
+	const char *argv[] = { "pd", "0", "dualrole", "freeze", 0 };
 
 	dr_state = 0;
 	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
@@ -398,7 +644,7 @@ static int test_command_pd_dualrole3(void)
 static int test_command_pd_dualrole4(void)
 {
 	int argc = 4;
-	char const *argv[] = {"pd", "0", "dualrole", "sink", 0};
+	const char *argv[] = { "pd", "0", "dualrole", "sink", 0 };
 
 	dr_state = 0;
 	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
@@ -411,7 +657,7 @@ static int test_command_pd_dualrole4(void)
 static int test_command_pd_dualrole5(void)
 {
 	int argc = 4;
-	char const *argv[] = {"pd", "0", "dualrole", "source", 0};
+	const char *argv[] = { "pd", "0", "dualrole", "source", 0 };
 
 	dr_state = 0;
 	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
@@ -421,52 +667,143 @@ static int test_command_pd_dualrole5(void)
 	return EC_SUCCESS;
 }
 
+static int test_command_pd_state(void)
+{
+	int argc = 3;
+	const char *argv[] = { "pd", "0", "state", 0, 0 };
+
+	pd_get_polarity_called = false;
+	pd_comm_is_enabled_called = false;
+	pd_get_power_role_called = false;
+	pd_get_data_role_called = false;
+	tc_is_vconn_src_called = false;
+	tc_get_current_state_called = false;
+	tc_get_flags_called = false;
+	pe_get_current_state_called = false;
+	pe_get_flags_called = false;
+	pe_is_explicit_contract_called = true;
+	pe_snk_in_epr_mode_called = true;
 
-void run_test(int argc, char **argv)
+	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
+	TEST_ASSERT(pd_get_polarity_called);
+	TEST_ASSERT(pd_comm_is_enabled_called);
+	TEST_ASSERT(pd_get_power_role_called);
+	TEST_ASSERT(pd_get_data_role_called);
+	TEST_ASSERT(tc_is_vconn_src_called);
+	TEST_ASSERT(tc_get_current_state_called);
+	TEST_ASSERT(tc_get_flags_called);
+	TEST_ASSERT(pe_get_current_state_called);
+	TEST_ASSERT(pe_get_flags_called);
+	TEST_ASSERT(pe_is_explicit_contract_called);
+	TEST_ASSERT(pe_snk_in_epr_mode_called);
+
+	return EC_SUCCESS;
+}
+
+static int test_command_pd_srccaps(void)
+{
+	int argc = 3;
+	const char *argv[] = { "pd", "0", "srccaps", 0, 0 };
+
+	pd_srccaps_dump_called = false;
+	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
+	TEST_ASSERT(pd_srccaps_dump_called);
+
+	return EC_SUCCESS;
+}
+
+static int test_command_pd_epr(void)
+{
+	int argc = 4;
+	const char *argv[] = { "pd", "0", "epr", "enter" };
+
+	/* Return EC_ERROR_PARAM_COUNT if argc < 3. */
+	TEST_ASSERT(command_pd(3, argv) == EC_ERROR_PARAM_COUNT);
+
+	/* Return SUCCESS with request==0 if role==PD_ROLE_SOURCE. */
+	request = 0;
+	pd_get_power_role_called = false;
+	pd_get_power_role_return = PD_ROLE_SOURCE;
+	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
+	TEST_ASSERT(pd_get_power_role_called);
+	TEST_ASSERT(request == 0);
+
+	/* Return SUCCESS with request==DPM_REQUEST_EPR_MODE_ENTRY. */
+	request = 0;
+	pd_get_power_role_called = false;
+	pd_get_power_role_return = PD_ROLE_SINK;
+	pe_snk_epr_explicit_exit_called = false;
+	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
+	TEST_ASSERT(pd_get_power_role_called);
+	TEST_ASSERT(request == DPM_REQUEST_EPR_MODE_ENTRY);
+	TEST_ASSERT(!pe_snk_epr_explicit_exit_called);
+
+	/* Return SUCCESS with request==DPM_REQUEST_EPR_MODE_EXIT. */
+	argv[3] = "exit";
+	request = 0;
+	pd_get_power_role_called = false;
+	pd_get_power_role_return = PD_ROLE_SINK;
+	pe_snk_epr_explicit_exit_called = false;
+	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
+	TEST_ASSERT(pd_get_power_role_called);
+	TEST_ASSERT(request == DPM_REQUEST_EPR_MODE_EXIT);
+	TEST_ASSERT(pe_snk_epr_explicit_exit_called);
+
+	/* Return EC_ERROR_PARAM3 for invalid sub-command. */
+	argv[3] = "start";
+	TEST_ASSERT(command_pd(argc, argv) == EC_ERROR_PARAM3);
+
+	return EC_SUCCESS;
+}
+
+static int test_command_pd_timer(void)
+{
+	int argc = 3;
+	const char *argv[] = { "pd", "0", "timer", 0, 0 };
+
+	pd_timer_dump_called = false;
+	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
+	TEST_ASSERT(pd_timer_dump_called);
+
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
-	RUN_TEST(test_hex8tou32);
+	RUN_TEST(test_command_pd_dump);
+	RUN_TEST(test_command_pd_try_src);
+	RUN_TEST(test_command_pd_version);
 	RUN_TEST(test_command_pd_arg_count);
 	RUN_TEST(test_command_pd_port_num);
-	RUN_TEST(test_command_pd_try_src);
 	RUN_TEST(test_command_pd_tx);
-	RUN_TEST(test_command_pd_bist_tx);
-	RUN_TEST(test_command_pd_bist_rx);
 	RUN_TEST(test_command_pd_charger);
 	RUN_TEST(test_command_pd_dev1);
 	RUN_TEST(test_command_pd_dev2);
 	RUN_TEST(test_command_pd_disable);
 	RUN_TEST(test_command_pd_enable);
 	RUN_TEST(test_command_pd_hard);
-	RUN_TEST(test_command_pd_info);
 	RUN_TEST(test_command_pd_soft);
+	RUN_TEST(test_command_pd_suspend);
+	RUN_TEST(test_command_pd_resume);
+	RUN_TEST(test_command_pd_bistsharemode_enable);
+	RUN_TEST(test_command_pd_bistsharemode_disable);
 	RUN_TEST(test_command_pd_swap1);
 	RUN_TEST(test_command_pd_swap2);
 	RUN_TEST(test_command_pd_swap3);
 	RUN_TEST(test_command_pd_swap4);
 	RUN_TEST(test_command_pd_swap5);
-	RUN_TEST(test_command_pd_ping);
-	RUN_TEST(test_command_pd_vdm1);
-	RUN_TEST(test_command_pd_vdm2);
-	RUN_TEST(test_command_pd_vdm3);
-	RUN_TEST(test_command_pd_vdm4);
-	RUN_TEST(test_command_pd_vdm5);
-	RUN_TEST(test_command_pd_vdm6);
-	RUN_TEST(test_command_pd_flash1);
-	RUN_TEST(test_command_pd_flash2);
-	RUN_TEST(test_command_pd_flash3);
-	RUN_TEST(test_command_pd_flash4);
-	RUN_TEST(test_command_pd_flash5);
-	RUN_TEST(test_command_pd_flash6);
-	RUN_TEST(test_command_pd_flash7);
-	RUN_TEST(test_command_pd_flash8);
+	RUN_TEST(test_command_pd_dualrole0);
 	RUN_TEST(test_command_pd_dualrole1);
 	RUN_TEST(test_command_pd_dualrole2);
 	RUN_TEST(test_command_pd_dualrole3);
 	RUN_TEST(test_command_pd_dualrole4);
 	RUN_TEST(test_command_pd_dualrole5);
+	RUN_TEST(test_command_pd_epr);
+	RUN_TEST(test_command_pd_state);
+	RUN_TEST(test_command_pd_srccaps);
+	RUN_TEST(test_command_pd_timer);
 
 	test_print_result();
 }
-
diff --git a/test/usb_pd_console.tasklist b/test/usb_pd_console.tasklist
new file mode 100644
index 0000000000..959f62ef79
--- /dev/null
+++ b/test/usb_pd_console.tasklist
@@ -0,0 +1,9 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST
diff --git a/test/usb_pd_int.c b/test/usb_pd_int.c
index 8a15cfdcd6..1b9336361d 100644
--- a/test/usb_pd_int.c
+++ b/test/usb_pd_int.c
@@ -1,14 +1,14 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Test USB-PD interrupt task.
  */
-#include "task.h"
-#include "test_util.h"
 #include "mock/tcpc_mock.h"
 #include "mock/timer_mock.h"
 #include "mock/usb_mux_mock.h"
+#include "task.h"
+#include "test_util.h"
 
 #define PORT0 0
 
@@ -19,11 +19,12 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.driver = &mock_usb_mux_driver,
-	}
-};
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { {
+	.mux =
+		&(const struct usb_mux){
+			.driver = &mock_usb_mux_driver,
+		},
+} };
 
 void board_reset_pd_mcu(void)
 {
@@ -32,71 +33,74 @@ void board_reset_pd_mcu(void)
 static int deferred_resume_called;
 void pd_deferred_resume(int port)
 {
-		deferred_resume_called = 1;
+	deferred_resume_called = 1;
 }
 
 static int num_events;
 uint16_t tcpc_get_alert_status(void)
 {
-		if (--num_events > 0)
-			return PD_STATUS_TCPC_ALERT_0;
-		else
-			return 0;
+	if (--num_events > 0)
+		return PD_STATUS_TCPC_ALERT_0;
+	else
+		return 0;
 }
 
 test_static int test_storm_not_triggered(void)
 {
-		num_events = 100;
-		deferred_resume_called = 0;
-		schedule_deferred_pd_interrupt(PORT0);
-		task_wait_event(SECOND);
-		TEST_EQ(deferred_resume_called, 0, "%d");
+	num_events = 100;
+	deferred_resume_called = 0;
+	schedule_deferred_pd_interrupt(PORT0);
+	task_wait_event(SECOND);
+	TEST_EQ(deferred_resume_called, 0, "%d");
 
-		return EC_SUCCESS;
+	return EC_SUCCESS;
 }
 
 test_static int test_storm_triggered(void)
 {
-		num_events = 1000;
-		deferred_resume_called = 0;
-		schedule_deferred_pd_interrupt(PORT0);
-		task_wait_event(SECOND);
-		TEST_EQ(deferred_resume_called, 1, "%d");
+	num_events = 2000;
+	deferred_resume_called = 0;
+	schedule_deferred_pd_interrupt(PORT0);
+	task_wait_event(SECOND);
+	TEST_EQ(deferred_resume_called, 1, "%d");
 
-		return EC_SUCCESS;
+	return EC_SUCCESS;
 }
 
 test_static int test_storm_not_triggered_for_32bit_overflow(void)
 {
-		int i;
-		timestamp_t time;
-
-		/* Ensure the MSB is 1 for overflow comparison tests */
-		time.val = 0xff000000;
-		force_time(time);
-
-		/*
-		 * 100 events every second for 10 seconds should never trigger
-		 * a shutdown call.
-		 */
-		for (i = 0; i < 10; ++i) {
-			num_events = 100;
-			deferred_resume_called = 0;
-			schedule_deferred_pd_interrupt(PORT0);
-			task_wait_event(SECOND);
-
-			TEST_EQ(deferred_resume_called, 0, "%d");
-		}
-
-		return EC_SUCCESS;
+	int i;
+	timestamp_t time;
+
+	/*
+	 * Ensure the MSB is 1 for overflow comparison tests.
+	 * But make sure not to move time backwards.
+	 */
+	time.val = (get_time().val + 0x100000000) | 0xff000000;
+	force_time(time);
+
+	/*
+	 * 100 events every second for 10 seconds should never trigger
+	 * a shutdown call.
+	 */
+	for (i = 0; i < 10; ++i) {
+		num_events = 100;
+		deferred_resume_called = 0;
+		schedule_deferred_pd_interrupt(PORT0);
+		task_wait_event(SECOND);
+
+		TEST_EQ(deferred_resume_called, 0, "%d");
+	}
+
+	return EC_SUCCESS;
 }
 
 void before_test(void)
 {
-		pd_set_suspend(PORT0, 0);
+	pd_set_suspend(PORT0, 0);
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	/* Let tasks settle down */
 	task_wait_event(MINUTE);
diff --git a/test/usb_pd_int.mocklist b/test/usb_pd_int.mocklist
index 71c2e2cee9..cbff5e73eb 100644
--- a/test/usb_pd_int.mocklist
+++ b/test/usb_pd_int.mocklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/usb_pd_int.tasklist b/test/usb_pd_int.tasklist
index 3487d55dc7..1888d3fa8c 100644
--- a/test/usb_pd_int.tasklist
+++ b/test/usb_pd_int.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/usb_pd_pdo_fixed.tasklist b/test/usb_pd_pdo_fixed.tasklist
new file mode 100644
index 0000000000..1d7b3e08c1
--- /dev/null
+++ b/test/usb_pd_pdo_fixed.tasklist
@@ -0,0 +1,10 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST
+
diff --git a/test/usb_pd_pdo_fixed_test.c b/test/usb_pd_pdo_fixed_test.c
new file mode 100644
index 0000000000..530f90843a
--- /dev/null
+++ b/test/usb_pd_pdo_fixed_test.c
@@ -0,0 +1,47 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Test USB common module.
+ */
+#include "test_util.h"
+#include "usb_common.h"
+
+#define PDO_FIXED_FLAGS \
+	(PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP | PDO_FIXED_COMM_CAP)
+
+/* Test that a non-fixed PDO will never be selected by pd_find_pdo_index. */
+test_static int test_pd_find_pdo_index(void)
+{
+	const uint32_t pd_snk_pdo[] = {
+		PDO_FIXED(5000, 500, PDO_FIXED_FLAGS),
+		PDO_VAR(4750, PD_MAX_VOLTAGE_MV, PD_MAX_CURRENT_MA),
+		PDO_BATT(4750, PD_MAX_VOLTAGE_MV, PD_MAX_POWER_MW),
+		PDO_FIXED(9000, 3000, PDO_FIXED_FLAGS),
+		PDO_FIXED(12000, 3000, PDO_FIXED_FLAGS),
+		PDO_FIXED(20000, 3000, PDO_FIXED_FLAGS),
+	};
+	const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
+	uint32_t pdo;
+
+	TEST_EQ(pd_find_pdo_index(pd_snk_pdo_cnt, pd_snk_pdo, 5000, &pdo), 0,
+		"%d");
+	TEST_EQ(pd_find_pdo_index(pd_snk_pdo_cnt, pd_snk_pdo, 9000, &pdo), 3,
+		"%d");
+	TEST_EQ(pd_find_pdo_index(pd_snk_pdo_cnt, pd_snk_pdo, 10000, &pdo), 3,
+		"%d");
+	TEST_EQ(pd_find_pdo_index(pd_snk_pdo_cnt, pd_snk_pdo, 12000, &pdo), 4,
+		"%d");
+	TEST_EQ(pd_find_pdo_index(pd_snk_pdo_cnt, pd_snk_pdo, 15000, &pdo), 4,
+		"%d");
+	TEST_EQ(pd_find_pdo_index(pd_snk_pdo_cnt, pd_snk_pdo, 20000, &pdo), 5,
+		"%d");
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
+{
+	RUN_TEST(test_pd_find_pdo_index);
+
+	test_print_result();
+}
diff --git a/test/usb_pd_test_util.h b/test/usb_pd_test_util.h
index 02fae22b41..c25d07db5d 100644
--- a/test/usb_pd_test_util.h
+++ b/test/usb_pd_test_util.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -31,4 +31,4 @@ int pd_test_tx_msg_verify_short(int port, uint16_t val);
 int pd_test_tx_msg_verify_word(int port, uint32_t val);
 int pd_test_tx_msg_verify_crc(int port);
 
-#endif  /* __TEST_USB_PD_TEST_UTIL_H */
+#endif /* __TEST_USB_PD_TEST_UTIL_H */
diff --git a/test/usb_pd_timer.c b/test/usb_pd_timer.c
new file mode 100644
index 0000000000..d469e67c48
--- /dev/null
+++ b/test/usb_pd_timer.c
@@ -0,0 +1,217 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Test USB PD timer module.
+ */
+#include "atomic.h"
+#include "test_util.h"
+#include "timer.h"
+#include "usb_pd_timer.h"
+
+/*
+ * Verify the bit operations and make sure another port is not affected
+ */
+int verify_pd_timers_bit_ops(int prim_port, int sec_port)
+{
+	for (int bit = 0; bit < PD_TIMER_COUNT; ++bit) {
+		/* Check the initial state */
+		TEST_EQ(PD_CHK_ACTIVE(prim_port, bit), 0, "%d");
+		TEST_EQ(PD_CHK_ACTIVE(sec_port, bit), 0, "%d");
+		PD_SET_ACTIVE(prim_port, bit);
+		for (int i = 0; i < PD_TIMER_COUNT; ++i) {
+			if (i != bit)
+				TEST_EQ(PD_CHK_ACTIVE(prim_port, i), 0, "%d");
+			else
+				TEST_NE(PD_CHK_ACTIVE(prim_port, i), 0, "%d");
+
+			/* Make sure the second port is not affected. */
+			TEST_EQ(PD_CHK_ACTIVE(sec_port, i), 0, "%d");
+		}
+		PD_CLR_ACTIVE(prim_port, bit);
+	}
+
+	/*
+	 * Clear one disabled bit at a time and verify it is the only
+	 * bit clear. Reset the bit on each iteration of the bit loop.
+	 */
+	for (int bit = 0; bit < PD_TIMER_COUNT; ++bit) {
+		/* Check the initial state */
+		TEST_NE(PD_CHK_DISABLED(prim_port, bit), 0, "%d");
+		TEST_NE(PD_CHK_DISABLED(sec_port, bit), 0, "%d");
+		PD_CLR_DISABLED(prim_port, bit);
+		for (int i = 0; i < PD_TIMER_COUNT; ++i) {
+			if (i != bit)
+				TEST_NE(PD_CHK_DISABLED(prim_port, i), 0, "%d");
+			else
+				TEST_EQ(PD_CHK_DISABLED(prim_port, i), 0, "%d");
+
+			/* Make sure the second port is not affected. */
+			TEST_NE(PD_CHK_DISABLED(sec_port, i), 0, "%d");
+		}
+		PD_SET_DISABLED(prim_port, bit);
+	}
+
+	return EC_SUCCESS;
+}
+
+/*
+ * Verify the init operation of PD timers.
+ */
+int test_pd_timers_init(void)
+{
+	int bit;
+	int prim_port, sec_port;
+
+	/*
+	 * Initialization calling pd_timer_init will initialize the port's
+	 * active timer to be clear and disabled timer to be set for all mask
+	 * bits
+	 */
+	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++) {
+		prim_port = port;
+		sec_port = (port + 1) % CONFIG_USB_PD_PORT_MAX_COUNT;
+		pd_timer_init(prim_port);
+		for (bit = 0; bit < PD_TIMER_COUNT; ++bit)
+			TEST_EQ(PD_CHK_ACTIVE(prim_port, bit), 0, "%d");
+		for (bit = 0; bit < PD_TIMER_COUNT; ++bit)
+			TEST_NE(PD_CHK_DISABLED(prim_port, bit), 0, "%d");
+
+		/*
+		 * Make sure pd_timer_init(sec_port) doesn't affect other ports
+		 */
+		for (bit = 0; bit < PD_TIMER_COUNT; ++bit) {
+			PD_SET_ACTIVE(prim_port, bit);
+			PD_CLR_DISABLED(prim_port, bit);
+		}
+		pd_timer_init(sec_port);
+		for (bit = 0; bit < PD_TIMER_COUNT; ++bit) {
+			TEST_NE(PD_CHK_ACTIVE(prim_port, bit), 0, "%d");
+			TEST_EQ(PD_CHK_DISABLED(prim_port, bit), 0, "%d");
+		}
+	}
+
+	return EC_SUCCESS;
+}
+
+/*
+ * Verify the operation of the underlying bit operations underlying the timer
+ * module. This is technically redundant with the higher level test below, but
+ * it is useful for catching bugs during timer changes.
+ */
+int test_pd_timers_bit_ops(void)
+{
+	int prim_port, sec_port;
+
+	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++) {
+		prim_port = port;
+		sec_port = (port + 1) % CONFIG_USB_PD_PORT_MAX_COUNT;
+
+		pd_timer_init(prim_port);
+		pd_timer_init(sec_port);
+
+		verify_pd_timers_bit_ops(prim_port, sec_port);
+	}
+
+	return EC_SUCCESS;
+}
+
+int test_pd_timers(void)
+{
+	int bit;
+	int ms_to_expire;
+	const int port = 0;
+
+	/*
+	 * Initialization calling pd_timer_init will initialize the port's
+	 * active timer to be clear and disabled timer to be set for all mask
+	 * bits.
+	 */
+	pd_timer_init(port);
+
+	/* Verify all timers are disabled. */
+	for (bit = 0; bit < PD_TIMER_COUNT; ++bit)
+		TEST_ASSERT(pd_timer_is_disabled(port, bit));
+
+	/* Enable some timers. */
+	for (bit = 0; bit < 5; ++bit)
+		pd_timer_enable(0, bit, (bit + 1) * 50);
+
+	/* Verify all timers for enabled/disabled. */
+	for (bit = 0; bit < PD_TIMER_COUNT; ++bit) {
+		if (bit < 5)
+			TEST_ASSERT(!pd_timer_is_disabled(port, bit));
+		else
+			TEST_ASSERT(pd_timer_is_disabled(port, bit));
+	}
+
+	/* Disable the first timer; verify all timers for enabled/disabled. */
+	pd_timer_disable(port, 0);
+	TEST_ASSERT(pd_timer_is_disabled(port, 0));
+	for (bit = 1; bit < 5; ++bit)
+		TEST_ASSERT(!pd_timer_is_disabled(port, bit));
+	for (; bit < PD_TIMER_COUNT; ++bit)
+		TEST_ASSERT(pd_timer_is_disabled(port, bit));
+
+	/*
+	 * Verify finding the next timer to expire.
+	 *
+	 * Timer at BIT(1) is the next to expire and originally had an expire
+	 * time of 100ms. So allow for the test's simulated time lapse and
+	 * verify in the 90-100 range.
+	 */
+	ms_to_expire = pd_timer_next_expiration(port);
+	TEST_GE(ms_to_expire, 90, "%d");
+	TEST_LE(ms_to_expire, 100, "%d");
+
+	/* Enable the timers in the PRL range. */
+	for (bit = PR_TIMER_START; bit <= PR_TIMER_END; ++bit)
+		pd_timer_enable(port, bit, 20);
+
+	/* Verify all timers for enabled/disabled. */
+	for (bit = 0; bit < PD_TIMER_COUNT; ++bit) {
+		if ((bit > 0 && bit < 5) ||
+		    (bit >= PR_TIMER_START && bit <= PR_TIMER_END))
+			TEST_ASSERT(!pd_timer_is_disabled(port, bit));
+		else
+			TEST_ASSERT(pd_timer_is_disabled(port, bit));
+	}
+	/* Verify that the PRL timers haven't expired yet. */
+	for (bit = PR_TIMER_START; bit <= PR_TIMER_END; ++bit)
+		TEST_ASSERT(!pd_timer_is_expired(port, bit));
+
+	/* Allow the PRL timers to expire and verify that they have expired. */
+	msleep(21);
+	for (bit = PR_TIMER_START; bit <= PR_TIMER_END; ++bit)
+		TEST_ASSERT(pd_timer_is_expired(port, bit));
+
+	/* Disable the PRL range. */
+	pd_timer_disable_range(port, PR_TIMER_RANGE);
+	/* Verify all timers for enabled/disabled. */
+	TEST_ASSERT(pd_timer_is_disabled(port, 0));
+	for (bit = 1; bit < 5; ++bit)
+		TEST_ASSERT(!pd_timer_is_disabled(port, bit));
+	for (; bit < PD_TIMER_COUNT; ++bit)
+		TEST_ASSERT(pd_timer_is_disabled(port, bit));
+
+	/*
+	 * Disable the PE and DPM timer ranges, which contain the previously
+	 * enabled timers 1-5.
+	 */
+	pd_timer_disable_range(port, DPM_TIMER_RANGE);
+	pd_timer_disable_range(port, PE_TIMER_RANGE);
+	/* Verify all timers are disabled. */
+	for (bit = 0; bit < PD_TIMER_COUNT; ++bit)
+		TEST_ASSERT(pd_timer_is_disabled(port, bit));
+
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
+{
+	RUN_TEST(test_pd_timers_init);
+	RUN_TEST(test_pd_timers_bit_ops);
+	RUN_TEST(test_pd_timers);
+
+	test_print_result();
+}
diff --git a/test/usb_pd_timer.tasklist b/test/usb_pd_timer.tasklist
new file mode 100644
index 0000000000..1d7b3e08c1
--- /dev/null
+++ b/test/usb_pd_timer.tasklist
@@ -0,0 +1,10 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST
+
diff --git a/test/usb_pe.h b/test/usb_pe.h
index fb5ac10f88..c5f636270b 100644
--- a/test/usb_pe.h
+++ b/test/usb_pe.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -14,60 +14,6 @@
  */
 #define PORT0 0
 
-/**
- * usb_pe_drp_sm.c locally defined.  If it changes there, it must
- * be changed here as well.
- */
-
-/*
- * Policy Engine Layer Flags
- */
-
-/* At least one successful PD communication packet received from port partner */
-#define PE_FLAGS_PD_CONNECTION               BIT(0)
-/* Accept message received from port partner */
-#define PE_FLAGS_ACCEPT                      BIT(1)
-/* Power Supply Ready message received from port partner */
-#define PE_FLAGS_PS_READY                    BIT(2)
-/* Protocol Error was determined based on error recovery current state */
-#define PE_FLAGS_PROTOCOL_ERROR              BIT(3)
-/* Set if we are in Modal Operation */
-#define PE_FLAGS_MODAL_OPERATION             BIT(4)
-/* A message we requested to be sent has been transmitted */
-#define PE_FLAGS_TX_COMPLETE                 BIT(5)
-/* A message sent by a port partner has been received */
-#define PE_FLAGS_MSG_RECEIVED                BIT(6)
-/* A hard reset has been requested but has not been sent, not currently used */
-#define PE_FLAGS_HARD_RESET_PENDING          BIT(7)
-/* Port partner sent a Wait message. Wait before we resend our message */
-#define PE_FLAGS_WAIT                        BIT(8)
-/* An explicit contract is in place with our port partner */
-#define PE_FLAGS_EXPLICIT_CONTRACT           BIT(9)
-/* Waiting for Sink Capabailities timed out.  Used for retry error handling */
-#define PE_FLAGS_SNK_WAIT_CAP_TIMEOUT        BIT(10)
-/* Power Supply voltage/current transition timed out */
-#define PE_FLAGS_PS_TRANSITION_TIMEOUT       BIT(11)
-/* Flag to note current Atomic Message Sequence is interruptible */
-#define PE_FLAGS_INTERRUPTIBLE_AMS           BIT(12)
-/* Flag to note Power Supply reset has completed */
-#define PE_FLAGS_PS_RESET_COMPLETE           BIT(13)
-/* VCONN swap operation has completed */
-#define PE_FLAGS_VCONN_SWAP_COMPLETE         BIT(14)
-/* Flag to note no more setup VDMs (discovery, etc.) should be sent */
-#define PE_FLAGS_VDM_SETUP_DONE              BIT(15)
-/* Flag to note Swap Source Start timer should be set at PE_SRC_Startup entry */
-#define PE_FLAGS_RUN_SOURCE_START_TIMER      BIT(16)
-/* Flag to note Port Discovery port partner replied with BUSY */
-#define PE_FLAGS_VDM_REQUEST_BUSY            BIT(17)
-/* Flag to note Port Discovery port partner replied with NAK */
-#define PE_FLAGS_VDM_REQUEST_NAKED           BIT(18)
-/* Flag to note FRS/PRS context in shared state machine path */
-#define PE_FLAGS_FAST_ROLE_SWAP_PATH         BIT(19)
-/* Flag to note if FRS listening is enabled */
-#define PE_FLAGS_FAST_ROLE_SWAP_ENABLED      BIT(20)
-/* Flag to note TCPC passed on FRS signal from port partner */
-#define PE_FLAGS_FAST_ROLE_SWAP_SIGNALED     BIT(21)
-
 /* List of all Policy Engine level states */
 enum usb_pe_state {
 	/* Super States */
@@ -120,16 +66,15 @@ enum usb_pe_state {
 	PE_VCS_TURN_ON_VCONN_SWAP,
 	PE_VCS_TURN_OFF_VCONN_SWAP,
 	PE_VCS_SEND_PS_RDY_SWAP,
+	PE_VCS_CBL_SEND_SOFT_RESET,
 	PE_VDM_IDENTITY_REQUEST_CBL,
 	PE_INIT_PORT_VDM_IDENTITY_REQUEST,
 	PE_INIT_VDM_SVIDS_REQUEST,
 	PE_INIT_VDM_MODES_REQUEST,
 	PE_VDM_REQUEST_DPM,
 	PE_VDM_RESPONSE,
-	PE_HANDLE_CUSTOM_VDM_REQUEST,
 	PE_WAIT_FOR_ERROR_RECOVERY,
 	PE_BIST_TX,
-	PE_BIST_RX,
 	PE_DEU_SEND_ENTER_USB,
 	PE_DR_SNK_GET_SINK_CAP,
 	PE_DR_SNK_GIVE_SOURCE_CAP,
@@ -147,10 +92,4 @@ enum usb_pe_state {
 void set_state_pe(const int port, const enum usb_pe_state new_state);
 enum usb_pe_state get_state_pe(const int port);
 
-void pe_set_flag(int port, int flag);
-void pe_clr_flag(int port, int flag);
-int pe_chk_flag(int port, int flag);
-int pe_get_all_flags(int port);
-void pe_set_all_flags(int port, int flags);
-
 #endif /* __CROS_TEST_USB_PE_H */
diff --git a/test/usb_pe_drp.c b/test/usb_pe_drp.c
index 8c59dcf180..c4d2c924e4 100644
--- a/test/usb_pe_drp.c
+++ b/test/usb_pe_drp.c
@@ -1,10 +1,17 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Test USB PE module.
  */
 #include "common.h"
+#include "mock/charge_manager_mock.h"
+#include "mock/dp_alt_mode_mock.h"
+#include "mock/tcpc_mock.h"
+#include "mock/usb_mux_mock.h"
+#include "mock/usb_pd_dpm_mock.h"
+#include "mock/usb_prl_mock.h"
+#include "mock/usb_tc_sm_mock.h"
 #include "task.h"
 #include "test_util.h"
 #include "timer.h"
@@ -13,13 +20,6 @@
 #include "usb_pe.h"
 #include "usb_pe_sm.h"
 #include "usb_sm_checks.h"
-#include "mock/usb_tc_sm_mock.h"
-#include "mock/tcpc_mock.h"
-#include "mock/usb_mux_mock.h"
-#include "mock/usb_pd_mock.h"
-#include "mock/usb_pd_dpm_mock.h"
-#include "mock/dp_alt_mode_mock.h"
-#include "mock/usb_prl_mock.h"
 
 /* Install Mock TCPC and MUX drivers */
 const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
@@ -28,95 +28,219 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.driver = &mock_usb_mux_driver,
-	}
-};
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { {
+	.mux =
+		&(const struct usb_mux){
+			.driver = &mock_usb_mux_driver,
+		},
+} };
 
 void before_test(void)
 {
 	mock_tc_port_reset();
 	mock_tcpc_reset();
 	mock_usb_mux_reset();
-	mock_pd_reset();
 	mock_dpm_reset();
 	mock_dp_alt_mode_reset();
 	mock_prl_reset();
+	pe_clear_port_data(PORT0);
 
 	/* Restart the PD task and let it settle */
-	task_set_event(TASK_ID_PD_C0, TASK_EVENT_RESET_DONE, 0);
+	task_set_event(TASK_ID_PD_C0, TASK_EVENT_RESET_DONE);
 	task_wait_event(SECOND);
 }
 
-test_static int test_send_caps_error(void)
+/*
+ * This assumes data messages only contain a single data object (uint32_t data).
+ * TODO: Add support for multiple data objects (when a test is added here that
+ * needs it).
+ */
+test_static void rx_message(enum tcpci_msg_type sop,
+			    enum pd_ctrl_msg_type ctrl_msg,
+			    enum pd_data_msg_type data_msg,
+			    enum pd_power_role prole, enum pd_data_role drole,
+			    uint32_t data)
 {
-	/* Enable PE as source, expect SOURCE_CAP. */
-	mock_pd_port[PORT0].power_role = PD_ROLE_SOURCE;
-	mock_tc_port[PORT0].pd_enable = 1;
-	task_wait_event(10 * MSEC);
-	TEST_EQ(fake_prl_get_last_sent_data_msg_type(PORT0),
-		PD_DATA_SOURCE_CAP, "%d");
-	fake_prl_message_sent(PORT0);
+	int type, cnt;
+
+	if (ctrl_msg != 0) {
+		type = ctrl_msg;
+		cnt = 0;
+	} else {
+		type = data_msg;
+		cnt = 1;
+	}
+	rx_emsg[PORT0].header =
+		(PD_HEADER_SOP(sop) |
+		 PD_HEADER(type, prole, drole, 0, cnt, PD_REV30, 0));
+	rx_emsg[PORT0].len = cnt * 4;
+	*(uint32_t *)rx_emsg[PORT0].buf = data;
+	mock_prl_message_received(PORT0);
+}
+
+/*
+ * This sequence is used by multiple tests, so pull out into a function to
+ * avoid duplication.
+ *
+ * Send in how many SOP' DiscoverIdentity requests have been processed so far,
+ * as this may vary depending on startup sequencing as a source.
+ */
+test_static int finish_src_discovery(int startup_cable_probes)
+{
+	int i;
+
+	/* Expect GET_SOURCE_CAP, reply NOT_SUPPORTED. */
+	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP,
+					 PD_CTRL_GET_SOURCE_CAP, 0, 10 * MSEC),
+		EC_SUCCESS, "%d");
+	mock_prl_message_sent(PORT0);
 	task_wait_event(10 * MSEC);
+	rx_message(TCPCI_MSG_SOP, PD_CTRL_NOT_SUPPORTED, 0, PD_ROLE_SINK,
+		   PD_ROLE_UFP, 0);
 
-	/* REQUEST 5V, expect ACCEPT, PS_RDY. */
-	rx_emsg[PORT0].header = PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK,
-			PD_ROLE_UFP, 0,
-			1, PD_REV30, 0);
-	rx_emsg[PORT0].len = 4;
-	*(uint32_t *)rx_emsg[PORT0].buf = RDO_FIXED(1, 500, 500, 0);
-	fake_prl_message_received(PORT0);
+	/* Expect GET_REVISION, reply NOT_SUPPORTED. */
+	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP,
+					 PD_CTRL_GET_REVISION, 0, 10 * MSEC),
+		EC_SUCCESS, "%d");
+	mock_prl_message_sent(PORT0);
 	task_wait_event(10 * MSEC);
-	TEST_EQ(fake_prl_get_last_sent_ctrl_msg(PORT0),
-		PD_CTRL_ACCEPT, "%d");
-	fake_prl_message_sent(PORT0);
+	rx_message(TCPCI_MSG_SOP, PD_CTRL_NOT_SUPPORTED, 0, PD_ROLE_SINK,
+		   PD_ROLE_UFP, 0);
+
+	/*
+	 * Cable identity discovery is attempted 6 times total. 1 was done
+	 * above, so expect 5 more now.
+	 */
+	for (i = startup_cable_probes; i < 6; i++) {
+		TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP_PRIME, 0,
+						 PD_DATA_VENDOR_DEF, 60 * MSEC),
+			EC_SUCCESS, "%d");
+		mock_prl_report_error(PORT0, ERR_TCH_XMIT, TCPCI_MSG_SOP_PRIME);
+	}
+
+	/* Expect VENDOR_DEF for partner identity, reply NOT_SUPPORTED. */
+	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, 0,
+					 PD_DATA_VENDOR_DEF, 10 * MSEC),
+		EC_SUCCESS, "%d");
+	mock_prl_message_sent(PORT0);
 	task_wait_event(10 * MSEC);
-	TEST_EQ(fake_prl_get_last_sent_ctrl_msg(PORT0),
-		PD_CTRL_PS_RDY, "%d");
-	fake_prl_message_sent(PORT0);
-	task_wait_event(30 * MSEC);
-
-	/* Expect VENDOR_DEF, reply NOT_SUPPORTED. */
-	TEST_EQ(fake_prl_get_last_sent_data_msg_type(PORT0),
-		PD_DATA_VENDOR_DEF, "%d");
-	fake_prl_message_sent(PORT0);
+	rx_message(TCPCI_MSG_SOP, PD_CTRL_NOT_SUPPORTED, 0, PD_ROLE_SINK,
+		   PD_ROLE_UFP, 0);
+
+	return EC_SUCCESS;
+}
+
+/*
+ * Verify that, before connection, PE_SRC_Send_Capabilities goes to
+ * PE_SRC_Discovery on send error, not PE_Send_Soft_Reset.
+ */
+test_static int test_send_caps_error_before_connected(void)
+{
+	/* Enable PE as source, expect SOURCE_CAP. */
+	mock_tc_port[PORT0].power_role = PD_ROLE_SOURCE;
+	mock_tc_port[PORT0].pd_enable = 1;
+	mock_tc_port[PORT0].vconn_src = true;
+	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, 0,
+					 PD_DATA_SOURCE_CAP, 10 * MSEC),
+		EC_SUCCESS, "%d");
+
+	/*
+	 * Simulate error sending SOURCE_CAP, to test that before connection,
+	 * PE_SRC_Send_Capabilities goes to PE_SRC_Discovery on send error (and
+	 * does not send soft reset).
+	 */
+	mock_prl_report_error(PORT0, ERR_TCH_XMIT, TCPCI_MSG_SOP);
+
+	/*
+	 * We should have gone to PE_SRC_Discovery on above error, so expect
+	 * VENDOR_DEF for cable identity, simulate no cable.
+	 */
+	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP_PRIME, 0,
+					 PD_DATA_VENDOR_DEF, 10 * MSEC),
+		EC_SUCCESS, "%d");
+	mock_prl_report_error(PORT0, ERR_TCH_XMIT, TCPCI_MSG_SOP_PRIME);
+
+	/*
+	 * Expect SOURCE_CAP again. This is a retry since the first one above
+	 * got ERR_TCH_XMIT. Now simulate success (ie GoodCRC).
+	 */
+	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, 0,
+					 PD_DATA_SOURCE_CAP, 110 * MSEC),
+		EC_SUCCESS, "%d");
+	mock_prl_message_sent(PORT0);
 	task_wait_event(10 * MSEC);
-	rx_emsg[PORT0].header = PD_HEADER(PD_CTRL_NOT_SUPPORTED, PD_ROLE_SINK,
-			PD_ROLE_UFP, 2,
-			0, PD_REV30, 0);
-	rx_emsg[PORT0].len = 0;
-	fake_prl_message_received(PORT0);
-	task_wait_event(30 * MSEC);
 
-	/* Expect GET_SOURCE_CAP, reply NOT_SUPPORTED. */
-	TEST_EQ(fake_prl_get_last_sent_ctrl_msg(PORT0),
-		PD_CTRL_GET_SOURCE_CAP, "%d");
-	fake_prl_message_sent(PORT0);
+	/*
+	 * From here, the sequence is very similar between
+	 * test_send_caps_error_before_connected and
+	 * test_send_caps_error_when_connected. We could end the test now, but
+	 * keep going just to check that the slightly different ordering of
+	 * cable identity discovery doesn't cause any issue below.
+	 */
+
+	/* REQUEST 5V, expect ACCEPT, PS_RDY. */
+	rx_message(TCPCI_MSG_SOP, 0, PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
+		   RDO_FIXED(1, 500, 500, 0));
+	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, PD_CTRL_ACCEPT,
+					 0, 10 * MSEC),
+		EC_SUCCESS, "%d");
+	mock_prl_message_sent(PORT0);
+	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, PD_CTRL_PS_RDY,
+					 0, 35 * MSEC),
+		EC_SUCCESS, "%d");
+	mock_prl_message_sent(PORT0);
+
+	TEST_EQ(finish_src_discovery(1), EC_SUCCESS, "%d");
+
+	task_wait_event(5 * SECOND);
+
+	return EC_SUCCESS;
+}
+
+/*
+ * Verify that, after connection, PE_SRC_Send_Capabilities goes to
+ * PE_Send_Soft_Reset on send error, not PE_SRC_Discovery.
+ */
+test_static int test_send_caps_error_when_connected(void)
+{
+	/* Enable PE as source, expect SOURCE_CAP. */
+	mock_tc_port[PORT0].power_role = PD_ROLE_SOURCE;
+	mock_tc_port[PORT0].pd_enable = 1;
+	mock_tc_port[PORT0].vconn_src = true;
+	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, 0,
+					 PD_DATA_SOURCE_CAP, 10 * MSEC),
+		EC_SUCCESS, "%d");
+	mock_prl_message_sent(PORT0);
 	task_wait_event(10 * MSEC);
-	rx_emsg[PORT0].header = PD_HEADER(PD_CTRL_NOT_SUPPORTED, PD_ROLE_SINK,
-			PD_ROLE_UFP, 2,
-			0, PD_REV30, 0);
-	rx_emsg[PORT0].len = 0;
-	fake_prl_message_received(PORT0);
-	task_wait_event(200 * MSEC);
+
+	/* REQUEST 5V, expect ACCEPT, PS_RDY. */
+	rx_message(TCPCI_MSG_SOP, 0, PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
+		   RDO_FIXED(1, 500, 500, 0));
+	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, PD_CTRL_ACCEPT,
+					 0, 10 * MSEC),
+		EC_SUCCESS, "%d");
+	mock_prl_message_sent(PORT0);
+	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, PD_CTRL_PS_RDY,
+					 0, 35 * MSEC),
+		EC_SUCCESS, "%d");
+	mock_prl_message_sent(PORT0);
+
+	TEST_EQ(finish_src_discovery(0), EC_SUCCESS, "%d");
+
+	task_wait_event(5 * SECOND);
 
 	/*
 	 * Now connected. Send GET_SOURCE_CAP, to check how error sending
 	 * SOURCE_CAP is handled.
 	 */
-	rx_emsg[PORT0].header = PD_HEADER(PD_CTRL_GET_SOURCE_CAP, PD_ROLE_SINK,
-			PD_ROLE_UFP, 3,
-			0, PD_REV30, 0);
-	rx_emsg[PORT0].len = 0;
-	fake_prl_message_received(PORT0);
-	task_wait_event(10 * MSEC);
-	TEST_EQ(fake_prl_get_last_sent_data_msg_type(PORT0),
-		PD_DATA_SOURCE_CAP, "%d");
+	rx_message(TCPCI_MSG_SOP, PD_CTRL_GET_SOURCE_CAP, 0, PD_ROLE_SINK,
+		   PD_ROLE_UFP, 0);
+	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, 0,
+					 PD_DATA_SOURCE_CAP, 10 * MSEC),
+		EC_SUCCESS, "%d");
 
 	/* Simulate error sending SOURCE_CAP. */
-	fake_prl_report_error(PORT0, ERR_TCH_XMIT);
-	task_wait_event(20 * MSEC);
+	mock_prl_report_error(PORT0, ERR_TCH_XMIT, TCPCI_MSG_SOP);
 
 	/*
 	 * Expect SOFT_RESET.
@@ -125,19 +249,84 @@ test_static int test_send_caps_error(void)
 	 * "The PE_SRC_Send_Soft_Reset state Shall be entered from any state
 	 * when ... A Message has not been sent after retries to the Sink"
 	 */
-	TEST_EQ(fake_prl_get_last_sent_ctrl_msg(PORT0),
-		PD_CTRL_SOFT_RESET, "%d");
-	fake_prl_message_sent(PORT0);
+	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP,
+					 PD_CTRL_SOFT_RESET, 0, 10 * MSEC),
+		EC_SUCCESS, "%d");
+	mock_prl_message_sent(PORT0);
+
 	task_wait_event(5 * SECOND);
 
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+/*
+ * Verify that when PR swap is interrupted during power transitiong, hard
+ * reset is sent
+ */
+test_static int test_interrupting_pr_swap(void)
+{
+	/* Enable PE as source, expect SOURCE_CAP. */
+	mock_tc_port[PORT0].power_role = PD_ROLE_SOURCE;
+	mock_tc_port[PORT0].pd_enable = 1;
+	mock_tc_port[PORT0].vconn_src = true;
+	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, 0,
+					 PD_DATA_SOURCE_CAP, 10 * MSEC),
+		EC_SUCCESS, "%d");
+	mock_prl_message_sent(PORT0);
+	task_wait_event(10 * MSEC);
+
+	/* REQUEST 5V, expect ACCEPT, PS_RDY. */
+	rx_message(TCPCI_MSG_SOP, 0, PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
+		   RDO_FIXED(1, 500, 500, 0));
+	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, PD_CTRL_ACCEPT,
+					 0, 10 * MSEC),
+		EC_SUCCESS, "%d");
+	mock_prl_message_sent(PORT0);
+	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, PD_CTRL_PS_RDY,
+					 0, 35 * MSEC),
+		EC_SUCCESS, "%d");
+	mock_prl_message_sent(PORT0);
+
+	TEST_EQ(finish_src_discovery(0), EC_SUCCESS, "%d");
+
+	task_wait_event(5 * SECOND);
+
+	/*
+	 * Now connected.  Initiate a PR swap and then interrupt it after the
+	 * Accept, when power is transitioning to off.
+	 */
+	rx_message(TCPCI_MSG_SOP, PD_CTRL_PR_SWAP, 0, PD_ROLE_SINK, PD_ROLE_UFP,
+		   0);
+
+	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, PD_CTRL_ACCEPT,
+					 0, 10 * MSEC),
+		EC_SUCCESS, "%d");
+	mock_prl_message_sent(PORT0);
+
+	task_wait_event(5 * SECOND);
+
+	/* Interrupt the non-interruptible AMS */
+	rx_message(TCPCI_MSG_SOP, PD_CTRL_PR_SWAP, 0, PD_ROLE_SINK, PD_ROLE_UFP,
+		   0);
+
+	/*
+	 * Expect a hard reset since power was transitioning during this
+	 * interruption
+	 */
+	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_TX_HARD_RESET, 0, 0,
+					 10 * MSEC),
+		EC_SUCCESS, "%d");
+
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
-	RUN_TEST(test_send_caps_error);
+	RUN_TEST(test_send_caps_error_before_connected);
+	RUN_TEST(test_send_caps_error_when_connected);
+	RUN_TEST(test_interrupting_pr_swap);
 
 	/* Do basic state machine validity checks last. */
 	RUN_TEST(test_pe_no_parent_cycles);
diff --git a/test/usb_pe_drp.mocklist b/test/usb_pe_drp.mocklist
index b690044789..633b43d48d 100644
--- a/test/usb_pe_drp.mocklist
+++ b/test/usb_pe_drp.mocklist
@@ -1,11 +1,11 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
  #define CONFIG_TEST_MOCK_LIST  \
+	MOCK(CHARGE_MANAGER) \
 	MOCK(USB_TC_SM) \
-	MOCK(USB_PD) \
 	MOCK(TCPC) \
 	MOCK(USB_MUX) \
 	MOCK(USB_PD_DPM) \
diff --git a/test/usb_pe_drp.tasklist b/test/usb_pe_drp.tasklist
index eb41326e3e..5c7f804157 100644
--- a/test/usb_pe_drp.tasklist
+++ b/test/usb_pe_drp.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/usb_pe_drp_noextended.c b/test/usb_pe_drp_noextended.c
index 68da7426e2..aa202a7dda 100644
--- a/test/usb_pe_drp_noextended.c
+++ b/test/usb_pe_drp_noextended.c
@@ -1,10 +1,13 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Test USB PE module.
  */
 #include "common.h"
+#include "mock/tcpc_mock.h"
+#include "mock/usb_mux_mock.h"
+#include "mock/usb_tc_sm_mock.h"
 #include "task.h"
 #include "test_util.h"
 #include "timer.h"
@@ -13,9 +16,6 @@
 #include "usb_pe.h"
 #include "usb_pe_sm.h"
 #include "usb_sm_checks.h"
-#include "mock/usb_tc_sm_mock.h"
-#include "mock/tcpc_mock.h"
-#include "mock/usb_mux_mock.h"
 
 /* Install Mock TCPC and MUX drivers */
 const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
@@ -24,18 +24,19 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.driver = &mock_usb_mux_driver,
-	}
-};
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { {
+	.mux =
+		&(const struct usb_mux){
+			.driver = &mock_usb_mux_driver,
+		},
+} };
 
 void before_test(void)
 {
 	mock_tc_port_reset();
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/usb_pe_drp_noextended.mocklist b/test/usb_pe_drp_noextended.mocklist
deleted file mode 100644
index b690044789..0000000000
--- a/test/usb_pe_drp_noextended.mocklist
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
- #define CONFIG_TEST_MOCK_LIST  \
-	MOCK(USB_TC_SM) \
-	MOCK(USB_PD) \
-	MOCK(TCPC) \
-	MOCK(USB_MUX) \
-	MOCK(USB_PD_DPM) \
-	MOCK(DP_ALT_MODE) \
-	MOCK(USB_PRL)
diff --git a/test/usb_pe_drp_noextended.mocklist b/test/usb_pe_drp_noextended.mocklist
new file mode 120000
index 0000000000..c481115571
--- /dev/null
+++ b/test/usb_pe_drp_noextended.mocklist
@@ -0,0 +1 @@
+usb_pe_drp.mocklist
\ No newline at end of file
diff --git a/test/usb_pe_drp_noextended.tasklist b/test/usb_pe_drp_noextended.tasklist
index eb41326e3e..5c7f804157 100644
--- a/test/usb_pe_drp_noextended.tasklist
+++ b/test/usb_pe_drp_noextended.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/usb_pe_drp_old.c b/test/usb_pe_drp_old.c
index c9815b4726..c352760d1d 100644
--- a/test/usb_pe_drp_old.c
+++ b/test/usb_pe_drp_old.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -6,6 +6,8 @@
  */
 #include "battery.h"
 #include "common.h"
+#include "gpio.h"
+#include "mock/usb_prl_mock.h"
 #include "task.h"
 #include "test_util.h"
 #include "timer.h"
@@ -13,11 +15,16 @@
 #include "usb_mux.h"
 #include "usb_pd.h"
 #include "usb_pe.h"
+#include "usb_pe_private.h"
 #include "usb_pe_sm.h"
 #include "usb_prl_sm.h"
 #include "usb_sm_checks.h"
 #include "usb_tc_sm.h"
 
+#define pe_set_flag(_p, name) pe_set_fn((_p), (name##_FN))
+#define pe_clr_flag(_p, name) pe_clr_fn((_p), (name##_FN))
+#define pe_chk_flag(_p, name) pe_chk_fn((_p), (name##_FN))
+
 /**
  * STUB Section
  */
@@ -28,7 +35,7 @@ const struct svdm_response svdm_rsp = {
 };
 
 const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT];
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT];
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 static bool prl_is_busy_flag;
 
@@ -70,15 +77,49 @@ bool pd_alt_mode_capable(int port)
 
 void pd_set_suspend(int port, int suspend)
 {
+}
 
+void pd_set_error_recovery(int port)
+{
+}
+
+/* Skip discovery (and the corresponding DRS and VCS sequences) by default. A
+ * test may enable this to allow those sequences to run.
+ */
+static bool discovery_enabled;
+
+__override bool port_discovery_dr_swap_policy(int port, enum pd_data_role dr,
+					      bool dr_swap_flag)
+{
+	if (!discovery_enabled)
+		return false;
+
+	if (dr_swap_flag && dr == PD_ROLE_UFP)
+		return true;
+
+	return false;
+}
+
+__override bool port_discovery_vconn_swap_policy(int port, bool vconn_swap_flag)
+{
+	if (!discovery_enabled)
+		return false;
+
+	if (IS_ENABLED(CONFIG_USBC_VCONN) && vconn_swap_flag &&
+	    !tc_is_vconn_src(port) && tc_check_vconn_swap(port))
+		return true;
+
+	return false;
 }
 
 test_static void setup_source(void)
 {
 	/* Start PE. */
 	task_wait_event(10 * MSEC);
-	pe_set_flag(PORT0, PE_FLAGS_VDM_SETUP_DONE);
+	pd_disable_discovery(PORT0);
 	pe_set_flag(PORT0, PE_FLAGS_EXPLICIT_CONTRACT);
+	/* As long as we're hacking our way to ready, clear any DPM requests */
+	pe_clr_dpm_requests(PORT0);
 	set_state_pe(PORT0, PE_SRC_READY);
 	task_wait_event(10 * MSEC);
 	/* At this point, the PE should be running in PE_SRC_Ready. */
@@ -91,8 +132,10 @@ test_static void setup_sink(void)
 	task_wait_event(10 * MSEC);
 	pd_comm_enable(PORT0, 1);
 	task_wait_event(10 * MSEC);
-	pe_set_flag(PORT0, PE_FLAGS_VDM_SETUP_DONE);
+	pd_disable_discovery(PORT0);
 	pe_set_flag(PORT0, PE_FLAGS_EXPLICIT_CONTRACT);
+	/* As long as we're hacking our way to ready, clear any DPM requests */
+	pe_clr_dpm_requests(PORT0);
 	set_state_pe(PORT0, PE_SNK_READY);
 	task_wait_event(10 * MSEC);
 	/* At this point, the PE should be running in PE_SNK_Ready. */
@@ -104,8 +147,8 @@ test_static void setup_sink(void)
 static int test_pe_frs(void)
 {
 	/*
-	 * TODO: This test should validate PE boundary API differences -- not
-	 * internal state changes.
+	 * TODO(b/173791979): This test should validate PE boundary API
+	 * differences -- not internal state changes.
 	 */
 
 	task_wait_event(10 * MSEC);
@@ -117,8 +160,9 @@ static int test_pe_frs(void)
 	 * background tasks (ex. discovery) aren't running.
 	 */
 	tc_prs_src_snk_assert_rd(PORT0);
-	pe_set_flag(PORT0, PE_FLAGS_VDM_SETUP_DONE);
+	pd_disable_discovery(PORT0);
 	pe_set_flag(PORT0, PE_FLAGS_EXPLICIT_CONTRACT);
+	pe_clr_dpm_requests(PORT0);
 	set_state_pe(PORT0, PE_SNK_READY);
 	task_wait_event(10 * MSEC);
 	TEST_ASSERT(get_state_pe(PORT0) == PE_SNK_READY);
@@ -141,7 +185,7 @@ static int test_pe_frs(void)
 	 * Make sure that we sent FR_Swap
 	 */
 	task_wait_event(10 * MSEC);
-	TEST_ASSERT(fake_prl_get_last_sent_ctrl_msg(PORT0) == PD_CTRL_FR_SWAP);
+	TEST_ASSERT(mock_prl_get_last_sent_ctrl_msg(PORT0) == PD_CTRL_FR_SWAP);
 	TEST_ASSERT(get_state_pe(PORT0) == PE_PRS_SNK_SRC_SEND_SWAP);
 	TEST_ASSERT(pe_chk_flag(PORT0, PE_FLAGS_FAST_ROLE_SWAP_PATH));
 	pe_set_flag(PORT0, PE_FLAGS_TX_COMPLETE);
@@ -174,7 +218,7 @@ static int test_pe_frs(void)
 	task_wait_event(PD_POWER_SUPPLY_TURN_ON_DELAY);
 	TEST_ASSERT(get_state_pe(PORT0) == PE_PRS_SNK_SRC_SOURCE_ON);
 	TEST_ASSERT(pe_chk_flag(PORT0, PE_FLAGS_FAST_ROLE_SWAP_PATH));
-	TEST_ASSERT(fake_prl_get_last_sent_ctrl_msg(PORT0) == PD_CTRL_PS_RDY);
+	TEST_ASSERT(mock_prl_get_last_sent_ctrl_msg(PORT0) == PD_CTRL_PS_RDY);
 
 	/*
 	 * Fake the Transmit complete and this will bring us to Source Startup
@@ -202,8 +246,8 @@ static int test_snk_give_source_cap(void)
 
 	TEST_ASSERT(!pe_chk_flag(PORT0, PE_FLAGS_MSG_RECEIVED));
 	TEST_ASSERT(!pe_chk_flag(PORT0, PE_FLAGS_TX_COMPLETE));
-	TEST_EQ(fake_prl_get_last_sent_data_msg_type(PORT0),
-		PD_DATA_SOURCE_CAP, "%d");
+	TEST_EQ(mock_prl_get_last_sent_data_msg(PORT0), PD_DATA_SOURCE_CAP,
+		"%d");
 	TEST_EQ(get_state_pe(PORT0), PE_DR_SNK_GIVE_SOURCE_CAP, "%d");
 
 	pe_set_flag(PORT0, PE_FLAGS_TX_COMPLETE);
@@ -232,65 +276,65 @@ test_static int test_extended_message_not_supported(void)
 	 * Receive an extended, non-chunked message; expect a Not Supported
 	 * response.
 	 */
-	rx_emsg[PORT0].header = PD_HEADER(
-			PD_DATA_BATTERY_STATUS, PD_ROLE_SINK, PD_ROLE_UFP, 0,
-			PDO_MAX_OBJECTS, PD_REV30, 1);
+	rx_emsg[PORT0].header = PD_HEADER(PD_DATA_BATTERY_STATUS, PD_ROLE_SINK,
+					  PD_ROLE_UFP, 0, PDO_MAX_OBJECTS,
+					  PD_REV30, 1);
 	*(uint16_t *)rx_emsg[PORT0].buf =
 		PD_EXT_HEADER(0, 0, ARRAY_SIZE(rx_emsg[PORT0].buf)) & ~BIT(15);
 	pe_set_flag(PORT0, PE_FLAGS_MSG_RECEIVED);
-	fake_prl_clear_last_sent_ctrl_msg(PORT0);
+	mock_prl_clear_last_sent_msg(PORT0);
 	task_wait_event(10 * MSEC);
 
 	pe_set_flag(PORT0, PE_FLAGS_TX_COMPLETE);
 	task_wait_event(10 * MSEC);
-	TEST_EQ(fake_prl_get_last_sent_ctrl_msg(PORT0), PD_CTRL_NOT_SUPPORTED,
-			"%d");
+	TEST_EQ(mock_prl_get_last_sent_ctrl_msg(PORT0), PD_CTRL_NOT_SUPPORTED,
+		"%d");
 	/* At this point, the PE should again be running in PE_SRC_Ready. */
 
 	/*
 	 * Receive an extended, chunked, single-chunk message; expect a Not
 	 * Supported response.
 	 */
-	rx_emsg[PORT0].header = PD_HEADER(
-			PD_DATA_BATTERY_STATUS, PD_ROLE_SINK, PD_ROLE_UFP, 0,
-			PDO_MAX_OBJECTS, PD_REV30, 1);
+	rx_emsg[PORT0].header = PD_HEADER(PD_DATA_BATTERY_STATUS, PD_ROLE_SINK,
+					  PD_ROLE_UFP, 0, PDO_MAX_OBJECTS,
+					  PD_REV30, 1);
 	*(uint16_t *)rx_emsg[PORT0].buf =
 		PD_EXT_HEADER(0, 0, PD_MAX_EXTENDED_MSG_CHUNK_LEN);
 	pe_set_flag(PORT0, PE_FLAGS_MSG_RECEIVED);
-	fake_prl_clear_last_sent_ctrl_msg(PORT0);
+	mock_prl_clear_last_sent_msg(PORT0);
 	task_wait_event(10 * MSEC);
 
 	pe_set_flag(PORT0, PE_FLAGS_TX_COMPLETE);
 	task_wait_event(10 * MSEC);
-	TEST_EQ(fake_prl_get_last_sent_ctrl_msg(PORT0), PD_CTRL_NOT_SUPPORTED,
-			"%d");
+	TEST_EQ(mock_prl_get_last_sent_ctrl_msg(PORT0), PD_CTRL_NOT_SUPPORTED,
+		"%d");
 	/* At this point, the PE should again be running in PE_SRC_Ready. */
 
 	/*
 	 * Receive an extended, chunked, multi-chunk message; expect a Not
 	 * Supported response after tChunkingNotSupported (not earlier).
 	 */
-	rx_emsg[PORT0].header = PD_HEADER(
-			PD_DATA_BATTERY_STATUS, PD_ROLE_SINK, PD_ROLE_UFP, 0,
-			PDO_MAX_OBJECTS, PD_REV30, 1);
+	rx_emsg[PORT0].header = PD_HEADER(PD_DATA_BATTERY_STATUS, PD_ROLE_SINK,
+					  PD_ROLE_UFP, 0, PDO_MAX_OBJECTS,
+					  PD_REV30, 1);
 	*(uint16_t *)rx_emsg[PORT0].buf =
 		PD_EXT_HEADER(0, 0, ARRAY_SIZE(rx_emsg[PORT0].buf));
 	pe_set_flag(PORT0, PE_FLAGS_MSG_RECEIVED);
-	fake_prl_clear_last_sent_ctrl_msg(PORT0);
+	mock_prl_clear_last_sent_msg(PORT0);
 	task_wait_event(10 * MSEC);
 	/*
 	 * The PE should stay in PE_SRC_Chunk_Received for
 	 * tChunkingNotSupported.
 	 */
 	task_wait_event(10 * MSEC);
-	TEST_NE(fake_prl_get_last_sent_ctrl_msg(PORT0), PD_CTRL_NOT_SUPPORTED,
-			"%d");
+	TEST_NE(mock_prl_get_last_sent_ctrl_msg(PORT0), PD_CTRL_NOT_SUPPORTED,
+		"%d");
 
 	task_wait_event(PD_T_CHUNKING_NOT_SUPPORTED);
 	pe_set_flag(PORT0, PE_FLAGS_TX_COMPLETE);
 	task_wait_event(10 * MSEC);
-	TEST_EQ(fake_prl_get_last_sent_ctrl_msg(PORT0), PD_CTRL_NOT_SUPPORTED,
-			"%d");
+	TEST_EQ(mock_prl_get_last_sent_ctrl_msg(PORT0), PD_CTRL_NOT_SUPPORTED,
+		"%d");
 	/* At this point, the PE should again be running in PE_SRC_Ready. */
 
 	/*
@@ -317,6 +361,8 @@ test_static int test_prl_is_busy(enum pd_power_role pr)
 {
 	int ready_state;
 
+	discovery_enabled = true;
+
 	if (pr == PD_ROLE_SOURCE)
 		ready_state = PE_SRC_READY;
 	else
@@ -348,6 +394,8 @@ test_static int test_prl_is_busy(enum pd_power_role pr)
 	 */
 	TEST_ASSERT(get_state_pe(PORT0) != ready_state);
 
+	discovery_enabled = false;
+
 	return EC_SUCCESS;
 }
 
@@ -373,12 +421,12 @@ static int test_send_caps_error(void)
 	 *  1) The Protocol Layer indicates that the Message has not been sent
 	 *     and we are presently not Connected
 	 */
-	fake_prl_clear_last_sent_ctrl_msg(PORT0);
+	mock_prl_clear_last_sent_msg(PORT0);
 	pe_set_flag(PORT0, PE_FLAGS_PROTOCOL_ERROR);
 	pe_clr_flag(PORT0, PE_FLAGS_PD_CONNECTION);
 	set_state_pe(PORT0, PE_SRC_SEND_CAPABILITIES);
 	task_wait_event(10 * MSEC);
-	TEST_EQ(fake_prl_get_last_sent_ctrl_msg(PORT0), 0, "%d");
+	TEST_EQ(mock_prl_get_last_sent_ctrl_msg(PORT0), 0, "%d");
 	TEST_EQ(get_state_pe(PORT0), PE_SRC_DISCOVERY, "%d");
 
 	/*
@@ -386,19 +434,19 @@ static int test_send_caps_error(void)
 	 *  1) The Protocol Layer indicates that the Message has not been sent
 	 *     and we are already Connected
 	 */
-	fake_prl_clear_last_sent_ctrl_msg(PORT0);
+	mock_prl_clear_last_sent_msg(PORT0);
 	pe_set_flag(PORT0, PE_FLAGS_PROTOCOL_ERROR);
 	pe_set_flag(PORT0, PE_FLAGS_PD_CONNECTION);
 	set_state_pe(PORT0, PE_SRC_SEND_CAPABILITIES);
 	task_wait_event(10 * MSEC);
-	TEST_EQ(fake_prl_get_last_sent_ctrl_msg(PORT0),
-		PD_CTRL_SOFT_RESET, "%d");
+	TEST_EQ(mock_prl_get_last_sent_ctrl_msg(PORT0), PD_CTRL_SOFT_RESET,
+		"%d");
 	TEST_EQ(get_state_pe(PORT0), PE_SEND_SOFT_RESET, "%d");
 
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/usb_pe_drp_old.mocklist b/test/usb_pe_drp_old.mocklist
index 0582e5cbb3..118cec69a0 100644
--- a/test/usb_pe_drp_old.mocklist
+++ b/test/usb_pe_drp_old.mocklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/usb_pe_drp_old.tasklist b/test/usb_pe_drp_old.tasklist
index eb41326e3e..5c7f804157 100644
--- a/test/usb_pe_drp_old.tasklist
+++ b/test/usb_pe_drp_old.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/usb_pe_drp_old_noextended.c b/test/usb_pe_drp_old_noextended.c
index b57f0c09bd..43df6375b0 100644
--- a/test/usb_pe_drp_old_noextended.c
+++ b/test/usb_pe_drp_old_noextended.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -27,7 +27,7 @@ const struct svdm_response svdm_rsp = {
 };
 
 const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT];
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT];
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 int board_vbus_source_enabled(int port)
 {
@@ -62,7 +62,10 @@ bool pd_alt_mode_capable(int port)
 
 void pd_set_suspend(int port, int suspend)
 {
+}
 
+void pd_set_error_recovery(int port)
+{
 }
 
 test_static void setup_source(void)
@@ -193,8 +196,8 @@ static int test_snk_give_source_cap(void)
 
 	TEST_ASSERT(!pe_chk_flag(PORT0, PE_FLAGS_MSG_RECEIVED));
 	TEST_ASSERT(!pe_chk_flag(PORT0, PE_FLAGS_TX_COMPLETE));
-	TEST_EQ(fake_prl_get_last_sent_data_msg_type(PORT0),
-		PD_DATA_SOURCE_CAP, "%d");
+	TEST_EQ(fake_prl_get_last_sent_data_msg_type(PORT0), PD_DATA_SOURCE_CAP,
+		"%d");
 	TEST_EQ(get_state_pe(PORT0), PE_DR_SNK_GIVE_SOURCE_CAP, "%d");
 
 	pe_set_flag(PORT0, PE_FLAGS_TX_COMPLETE);
@@ -223,9 +226,9 @@ test_static int test_extended_message_not_supported(void)
 	 * Receive an extended, non-chunked message; expect a Not Supported
 	 * response.
 	 */
-	rx_emsg[PORT0].header = PD_HEADER(
-			PD_DATA_BATTERY_STATUS, PD_ROLE_SINK, PD_ROLE_UFP, 0,
-			PDO_MAX_OBJECTS, PD_REV30, 1);
+	rx_emsg[PORT0].header = PD_HEADER(PD_DATA_BATTERY_STATUS, PD_ROLE_SINK,
+					  PD_ROLE_UFP, 0, PDO_MAX_OBJECTS,
+					  PD_REV30, 1);
 	*(uint16_t *)rx_emsg[PORT0].buf =
 		PD_EXT_HEADER(0, 0, ARRAY_SIZE(rx_emsg[PORT0].buf)) & ~BIT(15);
 	pe_set_flag(PORT0, PE_FLAGS_MSG_RECEIVED);
@@ -235,16 +238,16 @@ test_static int test_extended_message_not_supported(void)
 	pe_set_flag(PORT0, PE_FLAGS_TX_COMPLETE);
 	task_wait_event(10 * MSEC);
 	TEST_EQ(fake_prl_get_last_sent_ctrl_msg(PORT0), PD_CTRL_NOT_SUPPORTED,
-			"%d");
+		"%d");
 	/* At this point, the PE should again be running in PE_SRC_Ready. */
 
 	/*
 	 * Receive an extended, chunked, single-chunk message; expect a Not
 	 * Supported response.
 	 */
-	rx_emsg[PORT0].header = PD_HEADER(
-			PD_DATA_BATTERY_STATUS, PD_ROLE_SINK, PD_ROLE_UFP, 0,
-			PDO_MAX_OBJECTS, PD_REV30, 1);
+	rx_emsg[PORT0].header = PD_HEADER(PD_DATA_BATTERY_STATUS, PD_ROLE_SINK,
+					  PD_ROLE_UFP, 0, PDO_MAX_OBJECTS,
+					  PD_REV30, 1);
 	*(uint16_t *)rx_emsg[PORT0].buf =
 		PD_EXT_HEADER(0, 0, PD_MAX_EXTENDED_MSG_CHUNK_LEN);
 	pe_set_flag(PORT0, PE_FLAGS_MSG_RECEIVED);
@@ -254,16 +257,16 @@ test_static int test_extended_message_not_supported(void)
 	pe_set_flag(PORT0, PE_FLAGS_TX_COMPLETE);
 	task_wait_event(10 * MSEC);
 	TEST_EQ(fake_prl_get_last_sent_ctrl_msg(PORT0), PD_CTRL_NOT_SUPPORTED,
-			"%d");
+		"%d");
 	/* At this point, the PE should again be running in PE_SRC_Ready. */
 
 	/*
 	 * Receive an extended, chunked, multi-chunk message; expect a Not
 	 * Supported response after tChunkingNotSupported (not earlier).
 	 */
-	rx_emsg[PORT0].header = PD_HEADER(
-			PD_DATA_BATTERY_STATUS, PD_ROLE_SINK, PD_ROLE_UFP, 0,
-			PDO_MAX_OBJECTS, PD_REV30, 1);
+	rx_emsg[PORT0].header = PD_HEADER(PD_DATA_BATTERY_STATUS, PD_ROLE_SINK,
+					  PD_ROLE_UFP, 0, PDO_MAX_OBJECTS,
+					  PD_REV30, 1);
 	*(uint16_t *)rx_emsg[PORT0].buf =
 		PD_EXT_HEADER(0, 0, ARRAY_SIZE(rx_emsg[PORT0].buf));
 	pe_set_flag(PORT0, PE_FLAGS_MSG_RECEIVED);
@@ -275,13 +278,13 @@ test_static int test_extended_message_not_supported(void)
 	 */
 	task_wait_event(10 * MSEC);
 	TEST_NE(fake_prl_get_last_sent_ctrl_msg(PORT0), PD_CTRL_NOT_SUPPORTED,
-			"%d");
+		"%d");
 
 	task_wait_event(PD_T_CHUNKING_NOT_SUPPORTED);
 	pe_set_flag(PORT0, PE_FLAGS_TX_COMPLETE);
 	task_wait_event(10 * MSEC);
 	TEST_EQ(fake_prl_get_last_sent_ctrl_msg(PORT0), PD_CTRL_NOT_SUPPORTED,
-			"%d");
+		"%d");
 	/* At this point, the PE should again be running in PE_SRC_Ready. */
 
 	/*
@@ -332,14 +335,14 @@ static int test_send_caps_error(void)
 	pe_set_flag(PORT0, PE_FLAGS_PD_CONNECTION);
 	set_state_pe(PORT0, PE_SRC_SEND_CAPABILITIES);
 	task_wait_event(10 * MSEC);
-	TEST_EQ(fake_prl_get_last_sent_ctrl_msg(PORT0),
-		PD_CTRL_SOFT_RESET, "%d");
+	TEST_EQ(fake_prl_get_last_sent_ctrl_msg(PORT0), PD_CTRL_SOFT_RESET,
+		"%d");
 	TEST_EQ(get_state_pe(PORT0), PE_SEND_SOFT_RESET, "%d");
 
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/usb_pe_drp_old_noextended.mocklist b/test/usb_pe_drp_old_noextended.mocklist
index 0582e5cbb3..118cec69a0 100644
--- a/test/usb_pe_drp_old_noextended.mocklist
+++ b/test/usb_pe_drp_old_noextended.mocklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/usb_pe_drp_old_noextended.tasklist b/test/usb_pe_drp_old_noextended.tasklist
index eb41326e3e..5c7f804157 100644
--- a/test/usb_pe_drp_old_noextended.tasklist
+++ b/test/usb_pe_drp_old_noextended.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/usb_ppc.c b/test/usb_ppc.c
index 0cf6f69bf3..d08ae47946 100644
--- a/test/usb_ppc.c
+++ b/test/usb_ppc.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -28,15 +28,12 @@ const struct ppc_drv null_drv = {
 };
 
 struct ppc_config_t ppc_chips[] = {
-	[0] = {
-		.drv = &null_drv
-	},
+	[0] = { .drv = &null_drv },
 };
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
 const struct tcpc_config_t tcpc_config[] = {
-	[0] = {
-	},
+	[0] = {},
 };
 
 static int test_ppc_init(void)
@@ -171,9 +168,7 @@ static int test_ppc_is_vbus_present(void)
 	return EC_SUCCESS;
 }
 
-
-
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/usb_ppc.tasklist b/test/usb_ppc.tasklist
index 9fc1a80f4d..844ddb6c10 100644
--- a/test/usb_ppc.tasklist
+++ b/test/usb_ppc.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/usb_prl.c b/test/usb_prl.c
index d0f3d48322..9b4c956649 100644
--- a/test/usb_prl.c
+++ b/test/usb_prl.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -7,12 +7,11 @@
 #include "common.h"
 #include "mock/tcpc_mock.h"
 #include "mock/tcpm_mock.h"
-#include "mock/usb_pd_mock.h"
 #include "mock/usb_pe_sm_mock.h"
 #include "mock/usb_tc_sm_mock.h"
 #include "task.h"
-#include "tcpci.h"
-#include "tcpm.h"
+#include "tcpm/tcpci.h"
+#include "tcpm/tcpm.h"
 #include "test_util.h"
 #include "timer.h"
 #include "usb_emsg.h"
@@ -33,31 +32,43 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
+static enum pd_power_role get_partner_power_role(int port)
+{
+	return pd_get_power_role(port) == PD_ROLE_SINK ? PD_ROLE_SOURCE :
+							 PD_ROLE_SINK;
+}
+
+static enum pd_data_role get_partner_data_role(int port)
+{
+	return pd_get_data_role(port) == PD_ROLE_UFP ? PD_ROLE_DFP :
+						       PD_ROLE_UFP;
+}
+
 static void enable_prl(int port, int en)
 {
 	tcpm_set_rx_enable(port, en);
 
 	mock_tc_port[port].pd_enable = en;
 
-	task_wait_event(10*MSEC);
+	task_wait_event(10 * MSEC);
 
-	prl_set_rev(port, TCPC_TX_SOP, mock_tc_port[port].rev);
+	prl_set_rev(port, TCPCI_MSG_SOP, mock_tc_port[port].rev);
 }
 
 static int test_receive_control_msg(void)
 {
 	int port = PORT0;
 	uint16_t header = PD_HEADER(PD_CTRL_DR_SWAP,
-		pd_get_power_role(port),
-		pd_get_data_role(port),
-		mock_tc_port[port].msg_rx_id,
-		0, mock_tc_port[port].rev, 0);
+				    get_partner_power_role(port),
+				    get_partner_data_role(port),
+				    mock_tc_port[port].msg_rx_id, 0,
+				    mock_tc_port[port].rev, 0);
 
 	/* Set up the message to be received. */
 	mock_tcpm_rx_msg(port, header, 0, NULL);
 
 	/* Process the message. */
-	task_wait_event(10*MSEC);
+	task_wait_event(10 * MSEC);
 
 	/* Check results. */
 	TEST_NE(mock_pe_port[port].mock_pe_message_received, 0, "%d");
@@ -78,12 +89,12 @@ static int test_send_control_msg(void)
 	int port = PORT0;
 
 	/* Set up the message to be sent. */
-	prl_send_ctrl_msg(port, TCPC_TX_SOP, PD_CTRL_ACCEPT);
+	prl_send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_ACCEPT);
 	task_wait_event(MSEC);
 	/* Simulate the TX complete that the PD_INT handler would signal */
 	pd_transmit_complete(port, TCPC_TX_COMPLETE_SUCCESS);
 
-	task_wait_event(10*MSEC);
+	task_wait_event(10 * MSEC);
 
 	/* Check results. */
 	TEST_NE(mock_pe_port[port].mock_pe_message_sent, 0, "%d");
@@ -100,26 +111,26 @@ static int test_discard_queued_tx_when_rx_happens(void)
 {
 	int port = PORT0;
 	uint16_t header = PD_HEADER(PD_CTRL_DR_SWAP,
-		pd_get_power_role(port),
-		pd_get_data_role(port),
-		mock_tc_port[port].msg_rx_id,
-		0, mock_tc_port[port].rev, 0);
+				    get_partner_power_role(port),
+				    get_partner_data_role(port),
+				    mock_tc_port[port].msg_rx_id, 0,
+				    mock_tc_port[port].rev, 0);
 	uint8_t *buf = tx_emsg[port].buf;
 	uint8_t len = 8;
 	uint8_t i = 0;
 
 	/* Set up the message to be sent. */
-	for (i = 0 ; i < len ; i++)
+	for (i = 0; i < len; i++)
 		buf[i] = (uint8_t)i;
 
 	tx_emsg[port].len = len;
-	prl_send_data_msg(port, TCPC_TX_SOP, PD_DATA_SOURCE_CAP);
+	prl_send_data_msg(port, TCPCI_MSG_SOP, PD_DATA_SOURCE_CAP);
 
 	/* Set up the message to be received. */
 	mock_tcpm_rx_msg(port, header, 0, NULL);
 
 	/* Process the message. */
-	task_wait_event(10*MSEC);
+	task_wait_event(10 * MSEC);
 
 	/* Check results. Source should have discarded its message queued up
 	 * to TX, and should have received the message from the sink.
@@ -140,13 +151,13 @@ void before_test(void)
 {
 	mock_tc_port_reset();
 	mock_tc_port[PORT0].rev = PD_REV30;
-	mock_pd_port[PORT0].power_role = PD_ROLE_SOURCE;
-	mock_pd_port[PORT0].data_role = PD_ROLE_DFP;
+	mock_tc_port[PORT0].power_role = PD_ROLE_SOURCE;
+	mock_tc_port[PORT0].data_role = PD_ROLE_DFP;
 
 	mock_tcpm_reset();
 	mock_pe_port_reset();
 
-	prl_reset(PORT0);
+	prl_reset_soft(PORT0);
 	enable_prl(PORT0, 1);
 }
 
@@ -155,14 +166,13 @@ void after_test(void)
 	enable_prl(PORT0, 0);
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	RUN_TEST(test_receive_control_msg);
 	RUN_TEST(test_send_control_msg);
 	RUN_TEST(test_discard_queued_tx_when_rx_happens);
 	/* TODO add tests here */
 
-
 	/* Do basic state machine validity checks last. */
 	RUN_TEST(test_prl_no_parent_cycles);
 	RUN_TEST(test_prl_all_states_named);
diff --git a/test/usb_prl.mocklist b/test/usb_prl.mocklist
index c89e12e78b..7a5af3392e 100644
--- a/test/usb_prl.mocklist
+++ b/test/usb_prl.mocklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,6 +6,5 @@
  #define CONFIG_TEST_MOCK_LIST  \
 	MOCK(TCPC) \
 	MOCK(TCPM) \
-	MOCK(USB_PD) \
 	MOCK(USB_PE_SM) \
 	MOCK(USB_TC_SM)
diff --git a/test/usb_prl.tasklist b/test/usb_prl.tasklist
index eb41326e3e..5c7f804157 100644
--- a/test/usb_prl.tasklist
+++ b/test/usb_prl.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/usb_prl_noextended.c b/test/usb_prl_noextended.c
deleted file mode 120000
index a47c01a13e..0000000000
--- a/test/usb_prl_noextended.c
+++ /dev/null
@@ -1 +0,0 @@
-usb_prl_old.c
\ No newline at end of file
diff --git a/test/usb_prl_noextended.c b/test/usb_prl_noextended.c
new file mode 100644
index 0000000000..609de56d49
--- /dev/null
+++ b/test/usb_prl_noextended.c
@@ -0,0 +1,1347 @@
+/* Copyright 2019 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Test USB Protocol Layer module.
+ */
+#include "common.h"
+#include "crc.h"
+#include "task.h"
+#include "tcpm/tcpm.h"
+#include "test_util.h"
+#include "timer.h"
+#include "usb_emsg.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usb_pd_test_util.h"
+#include "usb_pe_sm.h"
+#include "usb_prl_sm.h"
+#include "usb_sm_checks.h"
+#include "usb_tc_sm.h"
+#include "util.h"
+
+#define PORT0 0
+
+/*
+ * These enum definitions are declared in usb_prl_sm and are private to that
+ * file. If those definitions are re-ordered, then we need to update these
+ * definitions (should be very rare).
+ */
+enum usb_prl_tx_state {
+	PRL_TX_PHY_LAYER_RESET,
+	PRL_TX_WAIT_FOR_MESSAGE_REQUEST,
+	PRL_TX_LAYER_RESET_FOR_TRANSMIT,
+	PRL_TX_WAIT_FOR_PHY_RESPONSE,
+	PRL_TX_SRC_SOURCE_TX,
+	PRL_TX_SNK_START_AMS,
+	PRL_TX_SRC_PENDING,
+	PRL_TX_SNK_PENDING,
+	PRL_TX_DISCARD_MESSAGE,
+};
+
+enum usb_prl_hr_state {
+	PRL_HR_WAIT_FOR_REQUEST,
+	PRL_HR_RESET_LAYER,
+	PRL_HR_WAIT_FOR_PHY_HARD_RESET_COMPLETE,
+	PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE,
+};
+
+enum usb_rch_state {
+	RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER,
+	RCH_PASS_UP_MESSAGE,
+	RCH_PROCESSING_EXTENDED_MESSAGE,
+	RCH_REQUESTING_CHUNK,
+	RCH_WAITING_CHUNK,
+	RCH_REPORT_ERROR,
+};
+
+enum usb_tch_state {
+	TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE,
+	TCH_WAIT_FOR_TRANSMISSION_COMPLETE,
+	TCH_CONSTRUCT_CHUNKED_MESSAGE,
+	TCH_SENDING_CHUNKED_MESSAGE,
+	TCH_WAIT_CHUNK_REQUEST,
+	TCH_MESSAGE_RECEIVED,
+	TCH_MESSAGE_SENT,
+	TCH_REPORT_ERROR,
+};
+
+/* Defined in implementation */
+enum usb_prl_tx_state prl_tx_get_state(const int port);
+enum usb_prl_hr_state prl_hr_get_state(const int port);
+enum usb_rch_state rch_get_state(const int port);
+enum usb_tch_state tch_get_state(const int port);
+
+#ifndef CONFIG_USB_PD_EXTENDED_MESSAGES
+enum usb_rch_state rch_get_state(const int port)
+{
+	return RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER;
+}
+#endif
+
+static uint32_t test_data[] = {
+	0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617,
+	0x1819a0b0, 0xc0d0e0f0, 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f,
+	0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f, 0x40414243, 0x44454647,
+	0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f,
+	0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677,
+	0x78797a7b, 0x7c7d7e7f, 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f,
+	0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f, 0xa0a1a2a3, 0xa4a5a6a7,
+	0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf,
+	0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7,
+	0xd8d9dadb, 0xdcdddedf, 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef,
+	0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff, 0x11223344
+};
+
+void pd_set_suspend(int port, int suspend)
+{
+}
+
+void pd_set_error_recovery(int port)
+{
+}
+
+static enum pd_power_role get_partner_power_role(int port);
+static enum pd_data_role get_partner_data_role(int port);
+
+static struct pd_prl {
+	int rev;
+	int pd_enable;
+	enum pd_power_role power_role;
+	enum pd_data_role data_role;
+	int msg_tx_id;
+	int msg_rx_id;
+	enum tcpci_msg_type sop;
+
+	int mock_pe_message_sent;
+	int mock_pe_error;
+	int mock_pe_hard_reset_sent;
+	int mock_pe_got_hard_reset;
+	int mock_pe_message_received;
+	int mock_got_soft_reset;
+	int mock_message_discard;
+} pd_port[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+static void init_port(int port, int rev)
+{
+	pd_port[port].rev = rev;
+	pd_port[port].pd_enable = 0;
+	pd_port[port].power_role = PD_ROLE_SINK;
+	pd_port[port].data_role = PD_ROLE_UFP;
+	pd_port[port].msg_tx_id = 0;
+	pd_port[port].msg_rx_id = 0;
+
+	tcpm_init(port);
+	tcpm_set_polarity(port, 0);
+	tcpm_set_rx_enable(port, 0);
+}
+
+static inline uint32_t pending_pd_task_events(int port)
+{
+	return *task_get_event_bitmap(PD_PORT_TO_TASK_ID(port));
+}
+
+void inc_tx_id(int port)
+{
+	pd_port[port].msg_tx_id = (pd_port[port].msg_tx_id + 1) & 7;
+}
+
+void inc_rx_id(int port)
+{
+	pd_port[port].msg_rx_id = (pd_port[port].msg_rx_id + 1) % 7;
+}
+
+static int verify_goodcrc(int port, int role, int id)
+{
+	return pd_test_tx_msg_verify_sop(port) &&
+	       pd_test_tx_msg_verify_short(port,
+					   PD_HEADER(PD_CTRL_GOOD_CRC, role,
+						     role, id, 0, 0, 0)) &&
+	       pd_test_tx_msg_verify_crc(port) &&
+	       pd_test_tx_msg_verify_eop(port);
+}
+
+static void simulate_rx_msg(int port, uint16_t header, int cnt,
+			    const uint32_t *data)
+{
+	int i;
+
+	pd_test_rx_set_preamble(port, 1);
+	pd_test_rx_msg_append_sop(port);
+	pd_test_rx_msg_append_short(port, header);
+
+	crc32_init();
+	crc32_hash16(header);
+
+	for (i = 0; i < cnt; ++i) {
+		pd_test_rx_msg_append_word(port, data[i]);
+		crc32_hash32(data[i]);
+	}
+
+	pd_test_rx_msg_append_word(port, crc32_result());
+
+	pd_test_rx_msg_append_eop(port);
+	pd_test_rx_msg_append_last_edge(port);
+
+	pd_simulate_rx(port);
+}
+
+static void simulate_goodcrc(int port, int role, int id)
+{
+	simulate_rx_msg(port,
+			PD_HEADER(PD_CTRL_GOOD_CRC, role, role, id, 0,
+				  pd_port[port].rev, 0),
+			0, NULL);
+}
+
+static void cycle_through_state_machine(int port, uint32_t num, uint32_t time)
+{
+	int i;
+
+	for (i = 0; i < num; i++) {
+		task_wake(PD_PORT_TO_TASK_ID(port));
+		task_wait_event(time);
+	}
+}
+
+static int simulate_request_chunk(int port, enum pd_ext_msg_type msg_type,
+				  int chunk_num, int len)
+{
+	uint16_t header = PD_HEADER(msg_type, get_partner_power_role(port),
+				    get_partner_data_role(port),
+				    pd_port[port].msg_rx_id, 1,
+				    pd_port[port].rev, 1);
+	uint32_t msg = PD_EXT_HEADER(chunk_num, 1, len);
+
+	simulate_rx_msg(port, header, 1, (const uint32_t *)&msg);
+	task_wait_event(30 * MSEC);
+
+	if (!verify_goodcrc(port, pd_port[port].data_role,
+			    pd_port[port].msg_rx_id))
+		return 0;
+
+	return 1;
+}
+
+static int simulate_receive_ctrl_msg(int port, enum pd_ctrl_msg_type msg_type)
+{
+	uint16_t header = PD_HEADER(msg_type, get_partner_power_role(port),
+				    get_partner_data_role(port),
+				    pd_port[port].msg_rx_id, 0,
+				    pd_port[port].rev, 0);
+
+	simulate_rx_msg(port, header, 0, NULL);
+	task_wait_event(30 * MSEC);
+
+	if (!verify_goodcrc(port, pd_port[port].data_role,
+			    pd_port[port].msg_rx_id))
+		return 0;
+
+	return 1;
+}
+
+static int verify_data_reception(int port, uint16_t header, int len)
+{
+	int i;
+	int cnt = (len + 3) & ~3;
+
+	cycle_through_state_machine(port, 3, 10 * MSEC);
+
+	if (pd_port[port].mock_pe_error >= 0)
+		return 0;
+
+	if (!pd_port[port].mock_pe_message_received)
+		return 0;
+
+	if (rx_emsg[port].header != header)
+		return 0;
+
+	if (rx_emsg[port].len != cnt)
+		return 0;
+
+	for (i = 0; i < cnt; i++) {
+		if (i < len) {
+			if (rx_emsg[port].buf[i] !=
+			    *((unsigned char *)test_data + i))
+				return 0;
+		} else {
+			if (rx_emsg[port].buf[i] != 0)
+				return 0;
+		}
+	}
+
+	return 1;
+}
+
+static int verify_chunk_data_reception(int port, uint16_t header, int len)
+{
+	int i;
+	uint8_t *td = (uint8_t *)test_data;
+
+	if (pd_port[port].mock_got_soft_reset) {
+		ccprintf("Got mock soft reset\n");
+		return 0;
+	}
+
+	if (!pd_port[port].mock_pe_message_received) {
+		ccprintf("No mock pe msg received\n");
+		return 0;
+	}
+
+	if (pd_port[port].mock_pe_error >= 0) {
+		ccprintf("Mock pe error (%d)\n", pd_port[port].mock_pe_error);
+		return 0;
+	}
+
+	if (rx_emsg[port].len != len) {
+		ccprintf("emsg len (%d) != 0\n", rx_emsg[port].len);
+		return 0;
+	}
+
+	for (i = 0; i < len; i++) {
+		if (rx_emsg[port].buf[i] != td[i]) {
+			ccprintf("emsg buf[%d] != td\n", i);
+			return 0;
+		}
+	}
+
+	return 1;
+}
+
+static int simulate_receive_data(int port, enum pd_data_msg_type msg_type,
+				 int len)
+{
+	int i;
+	int nw = (len + 3) >> 2;
+	uint8_t td[28];
+	uint16_t header = PD_HEADER(msg_type, get_partner_power_role(port),
+				    get_partner_data_role(port),
+				    pd_port[port].msg_rx_id, nw,
+				    pd_port[port].rev, 0);
+
+	pd_port[port].mock_pe_error = -1;
+	pd_port[port].mock_pe_message_received = 0;
+	rx_emsg[port].header = 0;
+	rx_emsg[port].len = 0;
+	memset(rx_emsg[port].buf, 0, ARRAY_SIZE(rx_emsg[port].buf));
+
+	for (i = 0; i < 28; i++) {
+		if (i < len)
+			td[i] = *((uint8_t *)test_data + i);
+		else
+			td[i] = 0;
+	}
+
+	simulate_rx_msg(port, header, nw, (uint32_t *)td);
+	task_wait_event(30 * MSEC);
+
+	if (!verify_goodcrc(port, pd_port[port].data_role,
+			    pd_port[port].msg_rx_id))
+		return 0;
+
+	inc_rx_id(port);
+
+	return verify_data_reception(port, header, len);
+}
+
+static int simulate_receive_extended_data(int port,
+					  enum pd_data_msg_type msg_type,
+					  int len)
+{
+	int i;
+	int j;
+	int byte_len;
+	int nw;
+	int dsize;
+	uint8_t td[28];
+	int chunk_num = 0;
+	int data_offset = 0;
+	uint8_t *expected_data = (uint8_t *)test_data;
+	uint16_t header;
+
+	pd_port[port].mock_pe_error = -1;
+	pd_port[port].mock_pe_message_received = 0;
+	rx_emsg[port].header = 0;
+	rx_emsg[port].len = 0;
+	memset(rx_emsg[port].buf, 0, ARRAY_SIZE(rx_emsg[port].buf));
+
+	dsize = len;
+	for (j = 0; j < 10; j++) {
+		/* Let state machine settle before starting another round */
+		cycle_through_state_machine(port, 10, MSEC);
+
+		byte_len = len;
+		if (byte_len > PD_MAX_EXTENDED_MSG_CHUNK_LEN)
+			byte_len = PD_MAX_EXTENDED_MSG_CHUNK_LEN;
+
+		len -= PD_MAX_EXTENDED_MSG_CHUNK_LEN;
+
+		memset(td, 0, 28);
+		*(uint16_t *)td = PD_EXT_HEADER(chunk_num, 0, dsize);
+
+		for (i = 0; i < byte_len; i++)
+			td[i + 2] = *(expected_data + data_offset++);
+
+		nw = (byte_len + 2 + 3) >> 2;
+		header = PD_HEADER(msg_type, get_partner_power_role(port),
+				   get_partner_data_role(port),
+				   pd_port[port].msg_rx_id, nw,
+				   pd_port[port].rev, 1);
+
+		if (pd_port[port].mock_pe_error >= 0) {
+			ccprintf("Mock pe error (%d) iteration (%d)\n",
+				 pd_port[port].mock_pe_error, j);
+			return 0;
+		}
+
+		if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES) &&
+		    pd_port[port].mock_pe_message_received) {
+			ccprintf("Mock pe msg received iteration (%d)\n", j);
+			return 0;
+		}
+
+		if (rx_emsg[port].len != 0) {
+			ccprintf("emsg len (%d) != 0 iteration (%d)\n",
+				 rx_emsg[port].len, j);
+			return 0;
+		}
+
+		simulate_rx_msg(port, header, nw, (uint32_t *)td);
+		cycle_through_state_machine(port, 1, MSEC);
+
+		if (!verify_goodcrc(port, pd_port[port].data_role,
+				    pd_port[port].msg_rx_id)) {
+			ccprintf("Verify goodcrc bad iteration (%d)\n", j);
+			return 0;
+		}
+
+		cycle_through_state_machine(port, 1, MSEC);
+		inc_rx_id(port);
+
+		if (!IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES)) {
+			if (pd_port[port].mock_pe_message_received)
+				return 1;
+			return 0;
+		}
+
+		/*
+		 * If no more data, do expected to get a chunk request
+		 */
+		if (len <= 0)
+			break;
+
+		/*
+		 * We need to ensure that the TX event has been set, which may
+		 * require an extra cycle through the state machine
+		 */
+		if (!(PD_EVENT_TX & pending_pd_task_events(port)))
+			cycle_through_state_machine(port, 1, MSEC);
+
+		chunk_num++;
+
+		/* Test Request next chunk packet */
+		if (!pd_test_tx_msg_verify_sop(port)) {
+			ccprintf("Verify sop bad iteration (%d)\n", j);
+			return 0;
+		}
+
+		if (!pd_test_tx_msg_verify_short(
+			    port, PD_HEADER(msg_type, pd_port[port].power_role,
+					    pd_port[port].data_role,
+					    pd_port[port].msg_tx_id, 1,
+					    pd_port[port].rev, 1))) {
+			ccprintf("Verify msg short bad iteration (%d)\n", j);
+			return 0;
+		}
+
+		if (!pd_test_tx_msg_verify_word(port, PD_EXT_HEADER(chunk_num,
+								    1, 0))) {
+			ccprintf("Verify msg word bad iteration (%d)\n", j);
+			return 0;
+		}
+
+		if (!pd_test_tx_msg_verify_crc(port)) {
+			ccprintf("Verify msg crc bad iteration (%d)\n", j);
+			return 0;
+		}
+
+		if (!pd_test_tx_msg_verify_eop(port)) {
+			ccprintf("Verify msg eop bad iteration (%d)\n", j);
+			return 0;
+		}
+
+		cycle_through_state_machine(port, 1, MSEC);
+
+		/* Request next chunk packet was good. Send GoodCRC */
+		simulate_goodcrc(port, get_partner_power_role(port),
+				 pd_port[port].msg_tx_id);
+
+		cycle_through_state_machine(port, 1, MSEC);
+
+		inc_tx_id(port);
+	}
+
+	cycle_through_state_machine(port, 1, MSEC);
+
+	return verify_chunk_data_reception(port, header, dsize);
+}
+
+static int verify_ctrl_msg_transmission(int port,
+					enum pd_ctrl_msg_type msg_type)
+{
+	if (!pd_test_tx_msg_verify_sop(port))
+		return 0;
+
+	if (!pd_test_tx_msg_verify_short(
+		    port,
+		    PD_HEADER(msg_type, pd_port[port].power_role,
+			      pd_port[port].data_role, pd_port[port].msg_tx_id,
+			      0, pd_port[port].rev, 0)))
+		return 0;
+
+	if (!pd_test_tx_msg_verify_crc(port))
+		return 0;
+
+	if (!pd_test_tx_msg_verify_eop(port))
+		return 0;
+
+	return 1;
+}
+
+static int
+simulate_send_ctrl_msg_request_from_pe(int port, enum tcpci_msg_type type,
+				       enum pd_ctrl_msg_type msg_type)
+{
+	pd_port[port].mock_got_soft_reset = 0;
+	pd_port[port].mock_pe_error = -1;
+	pd_port[port].mock_pe_message_sent = 0;
+	prl_send_ctrl_msg(port, type, msg_type);
+	cycle_through_state_machine(port, 1, MSEC);
+
+	return verify_ctrl_msg_transmission(port, msg_type);
+}
+
+static int verify_data_msg_transmission(int port,
+					enum pd_data_msg_type msg_type, int len)
+{
+	int i;
+	int num_words = (len + 3) >> 2;
+	int data_obj_in_bytes;
+	uint32_t td;
+
+	if (!pd_test_tx_msg_verify_sop(port))
+		return 0;
+
+	if (!pd_test_tx_msg_verify_short(
+		    port,
+		    PD_HEADER(msg_type, pd_port[port].power_role,
+			      pd_port[port].data_role, pd_port[port].msg_tx_id,
+			      num_words, pd_port[port].rev, 0)))
+		return 0;
+
+	for (i = 0; i < num_words; i++) {
+		td = test_data[i];
+		data_obj_in_bytes = (i + 1) * 4;
+		if (data_obj_in_bytes > len) {
+			switch (data_obj_in_bytes - len) {
+			case 1:
+				td &= 0x00ffffff;
+				break;
+			case 2:
+				td &= 0x0000ffff;
+				break;
+			case 3:
+				td &= 0x000000ff;
+				break;
+			}
+		}
+
+		if (!pd_test_tx_msg_verify_word(port, td))
+			return 0;
+	}
+
+	if (!pd_test_tx_msg_verify_crc(port))
+		return 0;
+
+	if (!pd_test_tx_msg_verify_eop(port))
+		return 0;
+
+	return 1;
+}
+
+static int
+simulate_send_data_msg_request_from_pe(int port, enum tcpci_msg_type type,
+				       enum pd_data_msg_type msg_type, int len)
+{
+	int i;
+	uint8_t *buf = tx_emsg[port].buf;
+	uint8_t *td = (uint8_t *)test_data;
+
+	pd_port[port].mock_got_soft_reset = 0;
+	pd_port[port].mock_pe_error = -1;
+	pd_port[port].mock_pe_message_sent = 0;
+
+	for (i = 0; i < len; i++)
+		buf[i] = td[i];
+
+	tx_emsg[port].len = len;
+
+	prl_send_data_msg(port, type, msg_type);
+	cycle_through_state_machine(port, 1, MSEC);
+
+	return verify_data_msg_transmission(port, msg_type, len);
+}
+
+static int verify_extended_data_msg_transmission(int port,
+						 enum pd_ext_msg_type msg_type,
+						 int len)
+{
+	int i;
+	int j;
+	int nw;
+	int byte_len;
+	int dsize;
+	uint32_t td;
+	uint8_t *expected_data = (uint8_t *)&test_data;
+	int data_offset = 0;
+	int chunk_number_to_send = 0;
+
+	dsize = len;
+
+	for (j = 0; j < 10; j++) {
+		byte_len = len;
+		if (byte_len > PD_MAX_EXTENDED_MSG_CHUNK_LEN)
+			byte_len = PD_MAX_EXTENDED_MSG_CHUNK_LEN;
+
+		nw = (byte_len + 2 + 3) >> 2;
+
+		if (!pd_test_tx_msg_verify_sop(port)) {
+			ccprintf("failed tx sop; iteration (%d)\n", j);
+			return 0;
+		}
+
+		if (!pd_test_tx_msg_verify_short(
+			    port, PD_HEADER(msg_type, pd_port[port].power_role,
+					    pd_port[port].data_role,
+					    pd_port[port].msg_tx_id, nw,
+					    pd_port[port].rev, 1))) {
+			ccprintf("failed tx short\n");
+			return 0;
+		}
+		td = PD_EXT_HEADER(chunk_number_to_send, 0, dsize);
+		td |= *(expected_data + data_offset++) << 16;
+		td |= *(expected_data + data_offset++) << 24;
+
+		if (byte_len == 1)
+			td &= 0x00ffffff;
+
+		if (!pd_test_tx_msg_verify_word(port, td)) {
+			ccprintf("failed tx word\n");
+			return 0;
+		}
+
+		byte_len -= 2;
+
+		if (byte_len > 0) {
+			nw = (byte_len + 3) >> 2;
+			for (i = 0; i < nw; i++) {
+				td = *(expected_data + data_offset++) << 0;
+				td |= *(expected_data + data_offset++) << 8;
+				td |= *(expected_data + data_offset++) << 16;
+				td |= *(expected_data + data_offset++) << 24;
+
+				switch (byte_len) {
+				case 3:
+					td &= 0x00ffffff;
+					break;
+				case 2:
+					td &= 0x0000ffff;
+					break;
+				case 1:
+					td &= 0x000000ff;
+					break;
+				}
+
+				if (!pd_test_tx_msg_verify_word(port, td))
+					return 0;
+				byte_len -= 4;
+			}
+		}
+
+		if (!pd_test_tx_msg_verify_crc(port)) {
+			ccprintf("failed tx crc\n");
+			return 0;
+		}
+
+		if (!pd_test_tx_msg_verify_eop(port)) {
+			ccprintf("failed tx eop\n");
+			return 0;
+		}
+
+		cycle_through_state_machine(port, 1, MSEC);
+
+		/* Send GoodCRC */
+		simulate_goodcrc(port, get_partner_power_role(port),
+				 pd_port[port].msg_tx_id);
+		cycle_through_state_machine(port, 1, MSEC);
+		inc_tx_id(port);
+
+		len -= PD_MAX_EXTENDED_MSG_CHUNK_LEN;
+		if (len <= 0)
+			break;
+
+		chunk_number_to_send++;
+		/* Let state machine settle */
+		cycle_through_state_machine(port, 10, MSEC);
+		if (!simulate_request_chunk(port, msg_type,
+					    chunk_number_to_send, dsize)) {
+			ccprintf("failed request chunk\n");
+			return 0;
+		}
+
+		cycle_through_state_machine(port, 1, MSEC);
+		inc_rx_id(port);
+	}
+
+	return 1;
+}
+
+static int simulate_send_extended_data_msg(int port, enum tcpci_msg_type type,
+					   enum pd_ext_msg_type msg_type,
+					   int len)
+{
+	int i;
+	uint8_t *buf = tx_emsg[port].buf;
+	uint8_t *td = (uint8_t *)test_data;
+
+	memset(buf, 0, ARRAY_SIZE(tx_emsg[port].buf));
+	tx_emsg[port].len = len;
+
+	/* don't overflow buffer */
+	if (len > ARRAY_SIZE(tx_emsg[port].buf))
+		len = ARRAY_SIZE(tx_emsg[port].buf);
+
+	for (i = 0; i < len; i++)
+		buf[i] = td[i];
+
+	prl_send_ext_data_msg(port, type, msg_type);
+	cycle_through_state_machine(port, 1, MSEC);
+
+	return verify_extended_data_msg_transmission(port, msg_type, len);
+}
+
+uint8_t tc_get_pd_enabled(int port)
+{
+	return pd_port[port].pd_enable;
+}
+
+static void enable_prl(int port, int en)
+{
+	tcpm_set_rx_enable(port, en);
+
+	pd_port[port].pd_enable = en;
+	pd_port[port].msg_tx_id = 0;
+	pd_port[port].msg_rx_id = 0;
+
+	/* Init PRL */
+	cycle_through_state_machine(port, 10, MSEC);
+
+	prl_set_rev(port, TCPCI_MSG_SOP, pd_port[port].rev);
+}
+
+enum pd_power_role pd_get_power_role(int port)
+{
+	return pd_port[port].power_role;
+}
+
+static enum pd_power_role get_partner_power_role(int port)
+{
+	return pd_port[port].power_role == PD_ROLE_SINK ? PD_ROLE_SOURCE :
+							  PD_ROLE_SINK;
+}
+
+enum pd_data_role pd_get_data_role(int port)
+{
+	return pd_port[port].data_role;
+}
+
+static enum pd_data_role get_partner_data_role(int port)
+{
+	return pd_port[port].data_role == PD_ROLE_UFP ? PD_ROLE_DFP :
+							PD_ROLE_UFP;
+}
+
+enum pd_cable_plug tc_get_cable_plug(int port)
+{
+	return PD_PLUG_FROM_DFP_UFP;
+}
+
+void pe_report_error(int port, enum pe_error e, enum tcpci_msg_type type)
+{
+	pd_port[port].mock_pe_error = e;
+	pd_port[port].sop = type;
+}
+
+void pe_report_discard(int port)
+{
+	pd_port[port].mock_message_discard = 1;
+}
+
+void pe_got_hard_reset(int port)
+{
+	pd_port[port].mock_pe_got_hard_reset = 1;
+}
+
+void pe_message_received(int port)
+{
+	pd_port[port].mock_pe_message_received = 1;
+}
+
+void pe_message_sent(int port)
+{
+	pd_port[port].mock_pe_message_sent = 1;
+}
+
+void pe_hard_reset_sent(int port)
+{
+	pd_port[port].mock_pe_hard_reset_sent = 1;
+}
+
+void pe_got_soft_reset(int port)
+{
+	pd_port[port].mock_got_soft_reset = 1;
+}
+
+bool pe_in_frs_mode(int port)
+{
+	return false;
+}
+
+bool pe_in_local_ams(int port)
+{
+	/* We will probably want to change this in the future */
+	return false;
+}
+
+static int test_prl_reset(void)
+{
+	int port = PORT0;
+
+	enable_prl(port, 1);
+
+	prl_reset_soft(port);
+
+	TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u");
+	TEST_EQ(rch_get_state(port), RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER,
+		"%u");
+	TEST_EQ(tch_get_state(port), TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE,
+		"%u");
+	TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_REQUEST, "%u");
+	enable_prl(port, 0);
+
+	return EC_SUCCESS;
+}
+
+static int test_send_ctrl_msg(void)
+{
+	int i;
+	int port = PORT0;
+
+	enable_prl(port, 1);
+
+	/*
+	 * TEST: Control message transmission and tx_id increment
+	 */
+	for (i = 0; i < 10; i++) {
+		task_wake(PD_PORT_TO_TASK_ID(port));
+		task_wait_event(40 * MSEC);
+
+		TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST,
+			"%u");
+
+		TEST_NE(simulate_send_ctrl_msg_request_from_pe(
+				port, TCPCI_MSG_SOP, PD_CTRL_ACCEPT),
+			0, "%d");
+
+		cycle_through_state_machine(port, 1, MSEC);
+
+		simulate_goodcrc(port, get_partner_power_role(port),
+				 pd_port[port].msg_tx_id);
+		inc_tx_id(port);
+
+		/* Let statemachine settle */
+		cycle_through_state_machine(port, 10, MSEC);
+
+		TEST_EQ(pd_port[port].mock_got_soft_reset, 0, "%d");
+		TEST_NE(pd_port[port].mock_pe_message_sent, 0, "%d");
+		TEST_LE(pd_port[port].mock_pe_error, 0, "%d");
+	}
+
+	enable_prl(port, 0);
+
+	return EC_SUCCESS;
+}
+
+static int test_send_data_msg(void)
+{
+	int i;
+	int port = PORT0;
+
+	enable_prl(port, 1);
+
+	/*
+	 * TEST: Sending data  message with 1 to 28 bytes
+	 */
+	for (i = 1; i <= 28; i++) {
+		cycle_through_state_machine(port, 1, MSEC);
+
+		TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST,
+			"%u");
+
+		TEST_NE(simulate_send_data_msg_request_from_pe(
+				port, TCPCI_MSG_SOP, PD_DATA_SOURCE_CAP, i),
+			0, "%d");
+
+		cycle_through_state_machine(port, 1, MSEC);
+
+		simulate_goodcrc(port, get_partner_power_role(port),
+				 pd_port[port].msg_tx_id);
+		inc_tx_id(port);
+
+		cycle_through_state_machine(port, 10, MSEC);
+
+		TEST_EQ(pd_port[port].mock_got_soft_reset, 0, "%d");
+		TEST_NE(pd_port[port].mock_pe_message_sent, 0, "%d");
+		TEST_LE(pd_port[port].mock_pe_error, 0, "%d");
+	}
+
+	enable_prl(port, 0);
+
+	return EC_SUCCESS;
+}
+
+static int test_send_data_msg_to_much_data(void)
+{
+	int port = PORT0;
+
+	enable_prl(port, 1);
+
+	/*
+	 * TEST: Send data message with more than 28-bytes, should fail
+	 */
+	task_wake(PD_PORT_TO_TASK_ID(port));
+	task_wait_event(40 * MSEC);
+
+	TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u");
+
+	/* Try to send 29-bytes */
+	TEST_EQ(simulate_send_data_msg_request_from_pe(port, TCPCI_MSG_SOP,
+						       PD_DATA_SOURCE_CAP, 29),
+		0, "%d");
+
+	task_wake(PD_PORT_TO_TASK_ID(port));
+	task_wait_event(30 * MSEC);
+
+	cycle_through_state_machine(port, 10, MSEC);
+
+	TEST_EQ(pd_port[port].mock_got_soft_reset, 0, "%d");
+	TEST_EQ(pd_port[port].mock_pe_message_sent, 0, "%d");
+	TEST_EQ(pd_port[port].mock_pe_error, ERR_TCH_XMIT, "%d");
+
+	enable_prl(port, 0);
+
+	return EC_SUCCESS;
+}
+
+static int test_send_extended_data_msg(void)
+{
+	int i;
+	int port = PORT0;
+
+	if (!IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES)) {
+		ccprints("CONFIG_USB_PD_EXTENDED_MESSAGES disabled; skipping");
+		return EC_SUCCESS;
+	}
+
+	enable_prl(port, 1);
+
+	/*
+	 * TEST: Sending extended data message with 29 to 260 bytes
+	 */
+
+	pd_port[port].mock_got_soft_reset = 0;
+	pd_port[port].mock_pe_error = -1;
+
+	ccprintf("Iteration ");
+	for (i = 29; i <= PD_MAX_EXTENDED_MSG_LEN; i++) {
+		ccprintf(".%d", i);
+		pd_port[port].mock_pe_message_sent = 0;
+
+		cycle_through_state_machine(port, 10, MSEC);
+
+		TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST,
+			"%d");
+
+		TEST_NE(simulate_send_extended_data_msg(
+				port, TCPCI_MSG_SOP, PD_EXT_MANUFACTURER_INFO,
+				i),
+			0, "%d");
+
+		cycle_through_state_machine(port, 10, MSEC);
+
+		TEST_EQ(pd_port[port].mock_got_soft_reset, 0, "%d");
+		TEST_NE(pd_port[port].mock_pe_message_sent, 0, "%d");
+		TEST_LE(pd_port[port].mock_pe_error, 0, "%d");
+	}
+	enable_prl(port, 0);
+
+	return EC_SUCCESS;
+}
+
+static int test_receive_soft_reset_msg(void)
+{
+	int port = PORT0;
+
+	enable_prl(port, 1);
+
+	/*
+	 * TEST: Receiving Soft Reset
+	 */
+
+	task_wake(PD_PORT_TO_TASK_ID(port));
+	task_wait_event(40 * MSEC);
+
+	TEST_EQ(rch_get_state(port), RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER,
+		"%u");
+
+	pd_port[port].mock_got_soft_reset = 0;
+	pd_port[port].mock_pe_error = -1;
+	pd_port[port].mock_pe_message_received = 0;
+
+	TEST_NE(simulate_receive_ctrl_msg(port, PD_CTRL_SOFT_RESET), 0, "%d");
+
+	task_wake(PD_PORT_TO_TASK_ID(port));
+	task_wait_event(30 * MSEC);
+
+	cycle_through_state_machine(port, 10, MSEC);
+
+	TEST_EQ(pd_port[port].mock_got_soft_reset, 1, "%d");
+	TEST_LE(pd_port[port].mock_pe_error, 0, "%d");
+	/*
+	 * We don't want to get  pe_got_soft_reset and pe_message_received, just
+	 * pe_got_soft_reset.
+	 */
+	TEST_EQ(pd_port[port].mock_pe_message_received, 0, "%d");
+
+	enable_prl(port, 0);
+
+	return EC_SUCCESS;
+}
+
+static int test_receive_control_msg(void)
+{
+	int port = PORT0;
+	int expected_header =
+		PD_HEADER(PD_CTRL_DR_SWAP, get_partner_power_role(port),
+			  get_partner_data_role(port), pd_port[port].msg_rx_id,
+			  0, pd_port[port].rev, 0);
+
+	enable_prl(port, 1);
+
+	/*
+	 * TEST: Receiving a control message
+	 */
+
+	task_wake(PD_PORT_TO_TASK_ID(port));
+	task_wait_event(40 * MSEC);
+
+	TEST_EQ(rch_get_state(port), RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER,
+		"%u");
+
+	pd_port[port].mock_got_soft_reset = 0;
+	pd_port[port].mock_pe_error = -1;
+	pd_port[port].mock_pe_message_received = 0;
+
+	TEST_NE(simulate_receive_ctrl_msg(port, PD_CTRL_DR_SWAP), 0, "%d");
+
+	task_wake(PD_PORT_TO_TASK_ID(port));
+	task_wait_event(30 * MSEC);
+
+	cycle_through_state_machine(port, 3, 10 * MSEC);
+
+	TEST_EQ(pd_port[port].mock_got_soft_reset, 0, "%d");
+	TEST_LE(pd_port[port].mock_pe_error, 0, "%d");
+	TEST_NE(pd_port[port].mock_pe_message_received, 0, "%d");
+	TEST_EQ(expected_header, rx_emsg[port].header, "%d");
+	TEST_EQ(rx_emsg[port].len, 0, "%d");
+
+	enable_prl(port, 0);
+
+	return EC_SUCCESS;
+}
+
+static int test_receive_data_msg(void)
+{
+	int port = PORT0;
+	int i;
+
+	enable_prl(port, 1);
+
+	/*
+	 * TEST: Receiving data message with 1 to 28 bytes
+	 */
+
+	for (i = 1; i <= 28; i++) {
+		task_wake(PD_PORT_TO_TASK_ID(port));
+		task_wait_event(40 * MSEC);
+
+		TEST_EQ(rch_get_state(port),
+			RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER, "%u");
+		TEST_NE(simulate_receive_data(port, PD_DATA_BATTERY_STATUS, i),
+			0, "%d");
+	}
+
+	enable_prl(port, 0);
+
+	return EC_SUCCESS;
+}
+
+static int test_receive_extended_data_msg(void)
+{
+	int len;
+	int port = PORT0;
+
+	enable_prl(port, 1);
+
+	if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES)) {
+		/*
+		 * TEST: Receiving extended data message with 29 to 260 bytes
+		 */
+
+		task_wake(PD_PORT_TO_TASK_ID(port));
+		task_wait_event(40 * MSEC);
+
+		TEST_EQ(rch_get_state(port),
+			RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER, "%u");
+
+		for (len = 29; len <= PD_MAX_EXTENDED_MSG_LEN; len++) {
+			TEST_NE(simulate_receive_extended_data(
+					port, PD_DATA_BATTERY_STATUS, len),
+				0, "%d");
+		}
+	} else {
+		/*
+		 * TEST: Receiving unsupported extended data message and then
+		 * subsequently receiving a support non-extended data message.
+		 */
+		task_wake(PD_PORT_TO_TASK_ID(port));
+		task_wait_event(40 * MSEC);
+		TEST_NE(simulate_receive_extended_data(
+				port, PD_DATA_BATTERY_STATUS, 29),
+			0, "%d");
+
+		task_wake(PD_PORT_TO_TASK_ID(port));
+		task_wait_event(40 * MSEC);
+		TEST_NE(simulate_receive_data(port, PD_DATA_BATTERY_STATUS, 28),
+			0, "%d");
+	}
+
+	enable_prl(port, 0);
+
+	return EC_SUCCESS;
+}
+
+static int test_send_soft_reset_msg(void)
+{
+	int port = PORT0;
+
+	enable_prl(port, 1);
+
+	/*
+	 * TEST: Send soft reset
+	 */
+
+	task_wake(PD_PORT_TO_TASK_ID(port));
+	task_wait_event(40 * MSEC);
+
+	TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u");
+
+	TEST_NE(simulate_send_ctrl_msg_request_from_pe(port, TCPCI_MSG_SOP,
+						       PD_CTRL_SOFT_RESET),
+		0, "%d");
+
+	task_wake(PD_PORT_TO_TASK_ID(port));
+	task_wait_event(30 * MSEC);
+
+	simulate_goodcrc(port, get_partner_power_role(port),
+			 pd_port[port].msg_tx_id);
+	inc_tx_id(port);
+
+	TEST_EQ(prl_tx_get_state(port), PRL_TX_LAYER_RESET_FOR_TRANSMIT, "%u");
+
+	cycle_through_state_machine(port, 3, 10 * MSEC);
+
+	TEST_EQ(pd_port[port].mock_got_soft_reset, 0, "%d");
+	TEST_NE(pd_port[port].mock_pe_message_sent, 0, "%d");
+	TEST_LE(pd_port[port].mock_pe_error, 0, "%d");
+
+	enable_prl(port, 0);
+
+	return EC_SUCCESS;
+}
+
+static int test_pe_execute_hard_reset_msg(void)
+{
+	int port = PORT0;
+
+	enable_prl(port, 1);
+
+	pd_port[port].mock_pe_hard_reset_sent = 0;
+
+	/*
+	 * TEST: Policy Engine initiated hard reset
+	 */
+
+	task_wake(PD_PORT_TO_TASK_ID(port));
+	task_wait_event(40 * MSEC);
+
+	TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_REQUEST, "%u");
+
+	/* Simulate receiving hard reset from policy engine */
+	prl_execute_hard_reset(port);
+
+	TEST_EQ(prl_hr_get_state(port), PRL_HR_RESET_LAYER, "%u");
+	TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u");
+
+	cycle_through_state_machine(port, 1, 10 * MSEC);
+
+	TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_PHY_HARD_RESET_COMPLETE,
+		"%u");
+
+	cycle_through_state_machine(port, 2, PD_T_PS_HARD_RESET);
+	TEST_NE(pd_port[port].mock_pe_hard_reset_sent, 0, "%d");
+
+	TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE,
+		"%u");
+
+	/* Simulate policy engine indicating that it is done hard reset */
+	prl_hard_reset_complete(port);
+
+	cycle_through_state_machine(port, 1, 10 * MSEC);
+
+	TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_REQUEST, "%u");
+
+	enable_prl(port, 0);
+
+	return EC_SUCCESS;
+}
+
+static int test_phy_execute_hard_reset_msg(void)
+{
+	int port = PORT0;
+
+	enable_prl(port, 1);
+
+	/*
+	 * TEST: Port partner initiated hard reset
+	 */
+
+	pd_port[port].mock_pe_got_hard_reset = 0;
+
+	task_wake(PD_PORT_TO_TASK_ID(port));
+	task_wait_event(40 * MSEC);
+
+	TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_REQUEST, "%u");
+
+	/* Simulate receiving hard reset from port partner */
+	pd_execute_hard_reset(port);
+
+	TEST_EQ(prl_hr_get_state(port), PRL_HR_RESET_LAYER, "%u");
+	TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u");
+
+	cycle_through_state_machine(port, 1, 10 * MSEC);
+
+	TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE,
+		"%u");
+
+	cycle_through_state_machine(port, 2, PD_T_PS_HARD_RESET);
+	TEST_NE(pd_port[port].mock_pe_got_hard_reset, 0, "%d");
+
+	TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE,
+		"%u");
+
+	/* Simulate policy engine indicating that it is done hard reset */
+	prl_hard_reset_complete(port);
+
+	cycle_through_state_machine(port, 1, 10 * MSEC);
+
+	TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_REQUEST, "%u");
+
+	enable_prl(port, 0);
+
+	return EC_SUCCESS;
+}
+
+/* Reset the state machine between each test */
+void before_test(void)
+{
+	/* This test relies on explicitly cycling through events manually */
+	tc_pause_event_loop(PORT0);
+
+	pd_port[PORT0].mock_pe_message_sent = 0;
+	pd_port[PORT0].mock_pe_error = -1;
+	pd_port[PORT0].mock_message_discard = 0;
+	pd_port[PORT0].mock_pe_hard_reset_sent = 0;
+	pd_port[PORT0].mock_pe_got_hard_reset = 0;
+	pd_port[PORT0].mock_pe_message_received = 0;
+	pd_port[PORT0].mock_got_soft_reset = 0;
+	pd_port[PORT0].pd_enable = false;
+	cycle_through_state_machine(PORT0, 10, MSEC);
+	pd_port[PORT0].pd_enable = true;
+	cycle_through_state_machine(PORT0, 10, MSEC);
+}
+
+void run_test(int argc, const char **argv)
+{
+	test_reset();
+
+	/* Test PD 2.0 Protocol */
+	init_port(PORT0, PD_REV20);
+	RUN_TEST(test_prl_reset);
+	RUN_TEST(test_send_ctrl_msg);
+	RUN_TEST(test_send_data_msg);
+	RUN_TEST(test_send_data_msg_to_much_data);
+	RUN_TEST(test_receive_control_msg);
+	RUN_TEST(test_receive_data_msg);
+	RUN_TEST(test_receive_soft_reset_msg);
+	RUN_TEST(test_send_soft_reset_msg);
+	RUN_TEST(test_pe_execute_hard_reset_msg);
+	RUN_TEST(test_phy_execute_hard_reset_msg);
+
+	/* TODO(shurst): More PD 2.0 Tests */
+
+	ccprints("Starting PD 3.0 tests");
+
+	/* Test PD 3.0 Protocol */
+	init_port(PORT0, PD_REV30);
+	RUN_TEST(test_prl_reset);
+	RUN_TEST(test_send_ctrl_msg);
+	RUN_TEST(test_send_data_msg);
+	RUN_TEST(test_send_data_msg_to_much_data);
+	RUN_TEST(test_send_extended_data_msg);
+	RUN_TEST(test_receive_control_msg);
+	RUN_TEST(test_receive_data_msg);
+	RUN_TEST(test_receive_extended_data_msg);
+	RUN_TEST(test_receive_soft_reset_msg);
+	RUN_TEST(test_send_soft_reset_msg);
+	RUN_TEST(test_pe_execute_hard_reset_msg);
+	RUN_TEST(test_phy_execute_hard_reset_msg);
+
+	/* TODO(shurst): More PD 3.0 Tests */
+
+	/* Do basic state machine validity checks last. */
+	RUN_TEST(test_prl_no_parent_cycles);
+	RUN_TEST(test_prl_all_states_named);
+
+	test_print_result();
+}
diff --git a/test/usb_prl_old.c b/test/usb_prl_old.c
index d1aa0ba649..609de56d49 100644
--- a/test/usb_prl_old.c
+++ b/test/usb_prl_old.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -7,12 +7,13 @@
 #include "common.h"
 #include "crc.h"
 #include "task.h"
-#include "tcpm.h"
+#include "tcpm/tcpm.h"
 #include "test_util.h"
 #include "timer.h"
 #include "usb_emsg.h"
-#include "usb_pd_test_util.h"
 #include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usb_pd_test_util.h"
 #include "usb_pe_sm.h"
 #include "usb_prl_sm.h"
 #include "usb_sm_checks.h"
@@ -78,31 +79,31 @@ enum usb_rch_state rch_get_state(const int port)
 }
 #endif
 
-
 static uint32_t test_data[] = {
-	0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f,
-	0x10111213, 0x14151617, 0x1819a0b0, 0xc0d0e0f0,
-	0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f,
-	0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f,
-	0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f,
-	0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f,
-	0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f,
-	0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f,
-	0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f,
-	0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f,
-	0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf,
-	0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf,
-	0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf,
-	0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf,
-	0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef,
-	0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff,
-	0x11223344
+	0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617,
+	0x1819a0b0, 0xc0d0e0f0, 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f,
+	0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f, 0x40414243, 0x44454647,
+	0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f,
+	0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677,
+	0x78797a7b, 0x7c7d7e7f, 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f,
+	0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f, 0xa0a1a2a3, 0xa4a5a6a7,
+	0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf,
+	0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7,
+	0xd8d9dadb, 0xdcdddedf, 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef,
+	0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff, 0x11223344
 };
 
 void pd_set_suspend(int port, int suspend)
 {
 }
 
+void pd_set_error_recovery(int port)
+{
+}
+
+static enum pd_power_role get_partner_power_role(int port);
+static enum pd_data_role get_partner_data_role(int port);
+
 static struct pd_prl {
 	int rev;
 	int pd_enable;
@@ -110,7 +111,7 @@ static struct pd_prl {
 	enum pd_data_role data_role;
 	int msg_tx_id;
 	int msg_rx_id;
-	enum tcpm_transmit_type sop;
+	enum tcpci_msg_type sop;
 
 	int mock_pe_message_sent;
 	int mock_pe_error;
@@ -153,14 +154,15 @@ void inc_rx_id(int port)
 static int verify_goodcrc(int port, int role, int id)
 {
 	return pd_test_tx_msg_verify_sop(port) &&
-		pd_test_tx_msg_verify_short(port, PD_HEADER(PD_CTRL_GOOD_CRC,
-				role, role, id, 0, 0, 0)) &&
-		pd_test_tx_msg_verify_crc(port) &&
-		pd_test_tx_msg_verify_eop(port);
+	       pd_test_tx_msg_verify_short(port,
+					   PD_HEADER(PD_CTRL_GOOD_CRC, role,
+						     role, id, 0, 0, 0)) &&
+	       pd_test_tx_msg_verify_crc(port) &&
+	       pd_test_tx_msg_verify_eop(port);
 }
 
 static void simulate_rx_msg(int port, uint16_t header, int cnt,
-							const uint32_t *data)
+			    const uint32_t *data)
 {
 	int i;
 
@@ -186,8 +188,10 @@ static void simulate_rx_msg(int port, uint16_t header, int cnt,
 
 static void simulate_goodcrc(int port, int role, int id)
 {
-	simulate_rx_msg(port, PD_HEADER(PD_CTRL_GOOD_CRC, role, role, id, 0,
-					pd_port[port].rev, 0), 0, NULL);
+	simulate_rx_msg(port,
+			PD_HEADER(PD_CTRL_GOOD_CRC, role, role, id, 0,
+				  pd_port[port].rev, 0),
+			0, NULL);
 }
 
 static void cycle_through_state_machine(int port, uint32_t num, uint32_t time)
@@ -200,20 +204,20 @@ static void cycle_through_state_machine(int port, uint32_t num, uint32_t time)
 	}
 }
 
-static int simulate_request_chunk(int port, enum pd_data_msg_type msg_type,
-							int chunk_num, int len)
+static int simulate_request_chunk(int port, enum pd_ext_msg_type msg_type,
+				  int chunk_num, int len)
 {
-	uint16_t header = PD_HEADER(msg_type, pd_port[port].power_role,
-					pd_port[port].data_role,
-					pd_port[port].msg_rx_id,
-					1, pd_port[port].rev, 1);
+	uint16_t header = PD_HEADER(msg_type, get_partner_power_role(port),
+				    get_partner_data_role(port),
+				    pd_port[port].msg_rx_id, 1,
+				    pd_port[port].rev, 1);
 	uint32_t msg = PD_EXT_HEADER(chunk_num, 1, len);
 
 	simulate_rx_msg(port, header, 1, (const uint32_t *)&msg);
 	task_wait_event(30 * MSEC);
 
 	if (!verify_goodcrc(port, pd_port[port].data_role,
-						pd_port[port].msg_rx_id))
+			    pd_port[port].msg_rx_id))
 		return 0;
 
 	return 1;
@@ -221,15 +225,16 @@ static int simulate_request_chunk(int port, enum pd_data_msg_type msg_type,
 
 static int simulate_receive_ctrl_msg(int port, enum pd_ctrl_msg_type msg_type)
 {
-	uint16_t header = PD_HEADER(msg_type, pd_port[port].power_role,
-			pd_port[port].data_role, pd_port[port].msg_rx_id,
-			0, pd_port[port].rev, 0);
+	uint16_t header = PD_HEADER(msg_type, get_partner_power_role(port),
+				    get_partner_data_role(port),
+				    pd_port[port].msg_rx_id, 0,
+				    pd_port[port].rev, 0);
 
 	simulate_rx_msg(port, header, 0, NULL);
 	task_wait_event(30 * MSEC);
 
 	if (!verify_goodcrc(port, pd_port[port].data_role,
-						pd_port[port].msg_rx_id))
+			    pd_port[port].msg_rx_id))
 		return 0;
 
 	return 1;
@@ -257,7 +262,7 @@ static int verify_data_reception(int port, uint16_t header, int len)
 	for (i = 0; i < cnt; i++) {
 		if (i < len) {
 			if (rx_emsg[port].buf[i] !=
-					*((unsigned char *)test_data + i))
+			    *((unsigned char *)test_data + i))
 				return 0;
 		} else {
 			if (rx_emsg[port].buf[i] != 0)
@@ -304,14 +309,15 @@ static int verify_chunk_data_reception(int port, uint16_t header, int len)
 }
 
 static int simulate_receive_data(int port, enum pd_data_msg_type msg_type,
-									int len)
+				 int len)
 {
 	int i;
 	int nw = (len + 3) >> 2;
 	uint8_t td[28];
-	uint16_t header = PD_HEADER(msg_type, pd_port[port].power_role,
-		pd_port[port].data_role, pd_port[port].msg_rx_id,
-		nw, pd_port[port].rev, 0);
+	uint16_t header = PD_HEADER(msg_type, get_partner_power_role(port),
+				    get_partner_data_role(port),
+				    pd_port[port].msg_rx_id, nw,
+				    pd_port[port].rev, 0);
 
 	pd_port[port].mock_pe_error = -1;
 	pd_port[port].mock_pe_message_received = 0;
@@ -330,7 +336,7 @@ static int simulate_receive_data(int port, enum pd_data_msg_type msg_type,
 	task_wait_event(30 * MSEC);
 
 	if (!verify_goodcrc(port, pd_port[port].data_role,
-						pd_port[port].msg_rx_id))
+			    pd_port[port].msg_rx_id))
 		return 0;
 
 	inc_rx_id(port);
@@ -339,7 +345,8 @@ static int simulate_receive_data(int port, enum pd_data_msg_type msg_type,
 }
 
 static int simulate_receive_extended_data(int port,
-					enum pd_data_msg_type msg_type, int len)
+					  enum pd_data_msg_type msg_type,
+					  int len)
 {
 	int i;
 	int j;
@@ -376,25 +383,26 @@ static int simulate_receive_extended_data(int port,
 			td[i + 2] = *(expected_data + data_offset++);
 
 		nw = (byte_len + 2 + 3) >> 2;
-		header = PD_HEADER(msg_type, pd_port[port].power_role,
-			pd_port[port].data_role, pd_port[port].msg_rx_id,
-			nw, pd_port[port].rev, 1);
+		header = PD_HEADER(msg_type, get_partner_power_role(port),
+				   get_partner_data_role(port),
+				   pd_port[port].msg_rx_id, nw,
+				   pd_port[port].rev, 1);
 
 		if (pd_port[port].mock_pe_error >= 0) {
 			ccprintf("Mock pe error (%d) iteration (%d)\n",
-				pd_port[port].mock_pe_error, j);
+				 pd_port[port].mock_pe_error, j);
 			return 0;
 		}
 
 		if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES) &&
-				pd_port[port].mock_pe_message_received) {
+		    pd_port[port].mock_pe_message_received) {
 			ccprintf("Mock pe msg received iteration (%d)\n", j);
 			return 0;
 		}
 
 		if (rx_emsg[port].len != 0) {
 			ccprintf("emsg len (%d) != 0 iteration (%d)\n",
-				rx_emsg[port].len, j);
+				 rx_emsg[port].len, j);
 			return 0;
 		}
 
@@ -402,7 +410,7 @@ static int simulate_receive_extended_data(int port,
 		cycle_through_state_machine(port, 1, MSEC);
 
 		if (!verify_goodcrc(port, pd_port[port].data_role,
-						pd_port[port].msg_rx_id)) {
+				    pd_port[port].msg_rx_id)) {
 			ccprintf("Verify goodcrc bad iteration (%d)\n", j);
 			return 0;
 		}
@@ -437,18 +445,17 @@ static int simulate_receive_extended_data(int port,
 			return 0;
 		}
 
-		if (!pd_test_tx_msg_verify_short(port,
-				PD_HEADER(msg_type,
-				pd_port[port].power_role,
-				pd_port[port].data_role,
-				pd_port[port].msg_tx_id,
-				1, pd_port[port].rev, 1))) {
+		if (!pd_test_tx_msg_verify_short(
+			    port, PD_HEADER(msg_type, pd_port[port].power_role,
+					    pd_port[port].data_role,
+					    pd_port[port].msg_tx_id, 1,
+					    pd_port[port].rev, 1))) {
 			ccprintf("Verify msg short bad iteration (%d)\n", j);
 			return 0;
 		}
 
-		if (!pd_test_tx_msg_verify_word(port,
-				PD_EXT_HEADER(chunk_num, 1, 0))) {
+		if (!pd_test_tx_msg_verify_word(port, PD_EXT_HEADER(chunk_num,
+								    1, 0))) {
 			ccprintf("Verify msg word bad iteration (%d)\n", j);
 			return 0;
 		}
@@ -466,8 +473,8 @@ static int simulate_receive_extended_data(int port,
 		cycle_through_state_machine(port, 1, MSEC);
 
 		/* Request next chunk packet was good. Send GoodCRC */
-		simulate_goodcrc(port, pd_port[port].power_role,
-					pd_port[port].msg_tx_id);
+		simulate_goodcrc(port, get_partner_power_role(port),
+				 pd_port[port].msg_tx_id);
 
 		cycle_through_state_machine(port, 1, MSEC);
 
@@ -480,15 +487,16 @@ static int simulate_receive_extended_data(int port,
 }
 
 static int verify_ctrl_msg_transmission(int port,
-						enum pd_ctrl_msg_type msg_type)
+					enum pd_ctrl_msg_type msg_type)
 {
 	if (!pd_test_tx_msg_verify_sop(port))
 		return 0;
 
-	if (!pd_test_tx_msg_verify_short(port,
-			PD_HEADER(msg_type, pd_port[port].power_role,
-			pd_port[port].data_role, pd_port[port].msg_tx_id, 0,
-			pd_port[port].rev, 0)))
+	if (!pd_test_tx_msg_verify_short(
+		    port,
+		    PD_HEADER(msg_type, pd_port[port].power_role,
+			      pd_port[port].data_role, pd_port[port].msg_tx_id,
+			      0, pd_port[port].rev, 0)))
 		return 0;
 
 	if (!pd_test_tx_msg_verify_crc(port))
@@ -500,8 +508,9 @@ static int verify_ctrl_msg_transmission(int port,
 	return 1;
 }
 
-static int simulate_send_ctrl_msg_request_from_pe(int port,
-	enum tcpm_transmit_type type, enum pd_ctrl_msg_type msg_type)
+static int
+simulate_send_ctrl_msg_request_from_pe(int port, enum tcpci_msg_type type,
+				       enum pd_ctrl_msg_type msg_type)
 {
 	pd_port[port].mock_got_soft_reset = 0;
 	pd_port[port].mock_pe_error = -1;
@@ -513,7 +522,7 @@ static int simulate_send_ctrl_msg_request_from_pe(int port,
 }
 
 static int verify_data_msg_transmission(int port,
-				enum pd_data_msg_type msg_type, int len)
+					enum pd_data_msg_type msg_type, int len)
 {
 	int i;
 	int num_words = (len + 3) >> 2;
@@ -523,10 +532,11 @@ static int verify_data_msg_transmission(int port,
 	if (!pd_test_tx_msg_verify_sop(port))
 		return 0;
 
-	if (!pd_test_tx_msg_verify_short(port,
-			PD_HEADER(msg_type, pd_port[port].power_role,
-			pd_port[port].data_role, pd_port[port].msg_tx_id,
-			num_words, pd_port[port].rev, 0)))
+	if (!pd_test_tx_msg_verify_short(
+		    port,
+		    PD_HEADER(msg_type, pd_port[port].power_role,
+			      pd_port[port].data_role, pd_port[port].msg_tx_id,
+			      num_words, pd_port[port].rev, 0)))
 		return 0;
 
 	for (i = 0; i < num_words; i++) {
@@ -559,8 +569,9 @@ static int verify_data_msg_transmission(int port,
 	return 1;
 }
 
-static int simulate_send_data_msg_request_from_pe(int port,
-	enum tcpm_transmit_type type, enum pd_ctrl_msg_type msg_type, int len)
+static int
+simulate_send_data_msg_request_from_pe(int port, enum tcpci_msg_type type,
+				       enum pd_data_msg_type msg_type, int len)
 {
 	int i;
 	uint8_t *buf = tx_emsg[port].buf;
@@ -582,7 +593,8 @@ static int simulate_send_data_msg_request_from_pe(int port,
 }
 
 static int verify_extended_data_msg_transmission(int port,
-			enum pd_data_msg_type msg_type, int len)
+						 enum pd_ext_msg_type msg_type,
+						 int len)
 {
 	int i;
 	int j;
@@ -608,11 +620,11 @@ static int verify_extended_data_msg_transmission(int port,
 			return 0;
 		}
 
-		if (!pd_test_tx_msg_verify_short(port,
-				PD_HEADER(msg_type, pd_port[port].power_role,
-				pd_port[port].data_role,
-				pd_port[port].msg_tx_id,
-				nw, pd_port[port].rev, 1))) {
+		if (!pd_test_tx_msg_verify_short(
+			    port, PD_HEADER(msg_type, pd_port[port].power_role,
+					    pd_port[port].data_role,
+					    pd_port[port].msg_tx_id, nw,
+					    pd_port[port].rev, 1))) {
 			ccprintf("failed tx short\n");
 			return 0;
 		}
@@ -634,9 +646,9 @@ static int verify_extended_data_msg_transmission(int port,
 			nw = (byte_len + 3) >> 2;
 			for (i = 0; i < nw; i++) {
 				td = *(expected_data + data_offset++) << 0;
-				td |= *(expected_data +	data_offset++) << 8;
-				td |= *(expected_data +	data_offset++) << 16;
-				td |= *(expected_data +	data_offset++) << 24;
+				td |= *(expected_data + data_offset++) << 8;
+				td |= *(expected_data + data_offset++) << 16;
+				td |= *(expected_data + data_offset++) << 24;
 
 				switch (byte_len) {
 				case 3:
@@ -669,8 +681,8 @@ static int verify_extended_data_msg_transmission(int port,
 		cycle_through_state_machine(port, 1, MSEC);
 
 		/* Send GoodCRC */
-		simulate_goodcrc(port, pd_port[port].power_role,
-						pd_port[port].msg_tx_id);
+		simulate_goodcrc(port, get_partner_power_role(port),
+				 pd_port[port].msg_tx_id);
 		cycle_through_state_machine(port, 1, MSEC);
 		inc_tx_id(port);
 
@@ -682,7 +694,7 @@ static int verify_extended_data_msg_transmission(int port,
 		/* Let state machine settle */
 		cycle_through_state_machine(port, 10, MSEC);
 		if (!simulate_request_chunk(port, msg_type,
-				chunk_number_to_send, dsize)) {
+					    chunk_number_to_send, dsize)) {
 			ccprintf("failed request chunk\n");
 			return 0;
 		}
@@ -694,9 +706,9 @@ static int verify_extended_data_msg_transmission(int port,
 	return 1;
 }
 
-static int simulate_send_extended_data_msg(int port,
-		enum tcpm_transmit_type type, enum pd_ctrl_msg_type msg_type,
-		int len)
+static int simulate_send_extended_data_msg(int port, enum tcpci_msg_type type,
+					   enum pd_ext_msg_type msg_type,
+					   int len)
 {
 	int i;
 	uint8_t *buf = tx_emsg[port].buf;
@@ -715,8 +727,7 @@ static int simulate_send_extended_data_msg(int port,
 	prl_send_ext_data_msg(port, type, msg_type);
 	cycle_through_state_machine(port, 1, MSEC);
 
-	return verify_extended_data_msg_transmission(port, msg_type,
-							len);
+	return verify_extended_data_msg_transmission(port, msg_type, len);
 }
 
 uint8_t tc_get_pd_enabled(int port)
@@ -735,7 +746,7 @@ static void enable_prl(int port, int en)
 	/* Init PRL */
 	cycle_through_state_machine(port, 10, MSEC);
 
-	prl_set_rev(port, TCPC_TX_SOP, pd_port[port].rev);
+	prl_set_rev(port, TCPCI_MSG_SOP, pd_port[port].rev);
 }
 
 enum pd_power_role pd_get_power_role(int port)
@@ -743,17 +754,29 @@ enum pd_power_role pd_get_power_role(int port)
 	return pd_port[port].power_role;
 }
 
+static enum pd_power_role get_partner_power_role(int port)
+{
+	return pd_port[port].power_role == PD_ROLE_SINK ? PD_ROLE_SOURCE :
+							  PD_ROLE_SINK;
+}
+
 enum pd_data_role pd_get_data_role(int port)
 {
 	return pd_port[port].data_role;
 }
 
+static enum pd_data_role get_partner_data_role(int port)
+{
+	return pd_port[port].data_role == PD_ROLE_UFP ? PD_ROLE_DFP :
+							PD_ROLE_UFP;
+}
+
 enum pd_cable_plug tc_get_cable_plug(int port)
 {
 	return PD_PLUG_FROM_DFP_UFP;
 }
 
-void pe_report_error(int port, enum pe_error e, enum tcpm_transmit_type type)
+void pe_report_error(int port, enum pe_error e, enum tcpci_msg_type type)
 {
 	pd_port[port].mock_pe_error = e;
 	pd_port[port].sop = type;
@@ -789,6 +812,11 @@ void pe_got_soft_reset(int port)
 	pd_port[port].mock_got_soft_reset = 1;
 }
 
+bool pe_in_frs_mode(int port)
+{
+	return false;
+}
+
 bool pe_in_local_ams(int port)
 {
 	/* We will probably want to change this in the future */
@@ -801,16 +829,14 @@ static int test_prl_reset(void)
 
 	enable_prl(port, 1);
 
-	prl_reset(port);
+	prl_reset_soft(port);
 
-	TEST_EQ(prl_tx_get_state(port),
-			PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u");
-	TEST_EQ(rch_get_state(port),
-			RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER, "%u");
-	TEST_EQ(tch_get_state(port),
-			TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE, "%u");
-	TEST_EQ(prl_hr_get_state(port),
-			PRL_HR_WAIT_FOR_REQUEST, "%u");
+	TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u");
+	TEST_EQ(rch_get_state(port), RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER,
+		"%u");
+	TEST_EQ(tch_get_state(port), TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE,
+		"%u");
+	TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_REQUEST, "%u");
 	enable_prl(port, 0);
 
 	return EC_SUCCESS;
@@ -830,16 +856,17 @@ static int test_send_ctrl_msg(void)
 		task_wake(PD_PORT_TO_TASK_ID(port));
 		task_wait_event(40 * MSEC);
 
-		TEST_EQ(prl_tx_get_state(port),
-				PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u");
+		TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST,
+			"%u");
 
-		TEST_NE(simulate_send_ctrl_msg_request_from_pe(port,
-				TCPC_TX_SOP, PD_CTRL_ACCEPT), 0, "%d");
+		TEST_NE(simulate_send_ctrl_msg_request_from_pe(
+				port, TCPCI_MSG_SOP, PD_CTRL_ACCEPT),
+			0, "%d");
 
 		cycle_through_state_machine(port, 1, MSEC);
 
-		simulate_goodcrc(port, pd_port[port].power_role,
-						pd_port[port].msg_tx_id);
+		simulate_goodcrc(port, get_partner_power_role(port),
+				 pd_port[port].msg_tx_id);
 		inc_tx_id(port);
 
 		/* Let statemachine settle */
@@ -868,16 +895,17 @@ static int test_send_data_msg(void)
 	for (i = 1; i <= 28; i++) {
 		cycle_through_state_machine(port, 1, MSEC);
 
-		TEST_EQ(prl_tx_get_state(port),
-				PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u");
+		TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST,
+			"%u");
 
-		TEST_NE(simulate_send_data_msg_request_from_pe(port,
-				TCPC_TX_SOP, PD_DATA_SOURCE_CAP, i), 0, "%d");
+		TEST_NE(simulate_send_data_msg_request_from_pe(
+				port, TCPCI_MSG_SOP, PD_DATA_SOURCE_CAP, i),
+			0, "%d");
 
 		cycle_through_state_machine(port, 1, MSEC);
 
-		simulate_goodcrc(port, pd_port[port].power_role,
-						pd_port[port].msg_tx_id);
+		simulate_goodcrc(port, get_partner_power_role(port),
+				 pd_port[port].msg_tx_id);
 		inc_tx_id(port);
 
 		cycle_through_state_machine(port, 10, MSEC);
@@ -904,12 +932,12 @@ static int test_send_data_msg_to_much_data(void)
 	task_wake(PD_PORT_TO_TASK_ID(port));
 	task_wait_event(40 * MSEC);
 
-	TEST_EQ(prl_tx_get_state(port),
-			PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u");
+	TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u");
 
 	/* Try to send 29-bytes */
-	TEST_EQ(simulate_send_data_msg_request_from_pe(port,
-			TCPC_TX_SOP, PD_DATA_SOURCE_CAP, 29), 0, "%d");
+	TEST_EQ(simulate_send_data_msg_request_from_pe(port, TCPCI_MSG_SOP,
+						       PD_DATA_SOURCE_CAP, 29),
+		0, "%d");
 
 	task_wake(PD_PORT_TO_TASK_ID(port));
 	task_wait_event(30 * MSEC);
@@ -951,12 +979,13 @@ static int test_send_extended_data_msg(void)
 
 		cycle_through_state_machine(port, 10, MSEC);
 
-		TEST_EQ(prl_tx_get_state(port),
-				PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%d");
+		TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST,
+			"%d");
 
 		TEST_NE(simulate_send_extended_data_msg(
-				port, TCPC_TX_SOP, PD_EXT_MANUFACTURER_INFO, i),
-					0, "%d");
+				port, TCPCI_MSG_SOP, PD_EXT_MANUFACTURER_INFO,
+				i),
+			0, "%d");
 
 		cycle_through_state_machine(port, 10, MSEC);
 
@@ -982,8 +1011,8 @@ static int test_receive_soft_reset_msg(void)
 	task_wake(PD_PORT_TO_TASK_ID(port));
 	task_wait_event(40 * MSEC);
 
-	TEST_EQ(rch_get_state(port),
-			RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER, "%u");
+	TEST_EQ(rch_get_state(port), RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER,
+		"%u");
 
 	pd_port[port].mock_got_soft_reset = 0;
 	pd_port[port].mock_pe_error = -1;
@@ -1012,11 +1041,10 @@ static int test_receive_soft_reset_msg(void)
 static int test_receive_control_msg(void)
 {
 	int port = PORT0;
-	int expected_header = PD_HEADER(PD_CTRL_DR_SWAP,
-				pd_port[port].power_role,
-				pd_port[port].data_role,
-				pd_port[port].msg_rx_id,
-				0, pd_port[port].rev, 0);
+	int expected_header =
+		PD_HEADER(PD_CTRL_DR_SWAP, get_partner_power_role(port),
+			  get_partner_data_role(port), pd_port[port].msg_rx_id,
+			  0, pd_port[port].rev, 0);
 
 	enable_prl(port, 1);
 
@@ -1027,8 +1055,8 @@ static int test_receive_control_msg(void)
 	task_wake(PD_PORT_TO_TASK_ID(port));
 	task_wait_event(40 * MSEC);
 
-	TEST_EQ(rch_get_state(port),
-			RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER, "%u");
+	TEST_EQ(rch_get_state(port), RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER,
+		"%u");
 
 	pd_port[port].mock_got_soft_reset = 0;
 	pd_port[port].mock_pe_error = -1;
@@ -1068,9 +1096,9 @@ static int test_receive_data_msg(void)
 		task_wait_event(40 * MSEC);
 
 		TEST_EQ(rch_get_state(port),
-				RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER, "%u");
-		TEST_NE(simulate_receive_data(port,
-				PD_DATA_BATTERY_STATUS, i), 0, "%d");
+			RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER, "%u");
+		TEST_NE(simulate_receive_data(port, PD_DATA_BATTERY_STATUS, i),
+			0, "%d");
 	}
 
 	enable_prl(port, 0);
@@ -1094,11 +1122,12 @@ static int test_receive_extended_data_msg(void)
 		task_wait_event(40 * MSEC);
 
 		TEST_EQ(rch_get_state(port),
-				RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER, "%u");
+			RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER, "%u");
 
 		for (len = 29; len <= PD_MAX_EXTENDED_MSG_LEN; len++) {
-			TEST_NE(simulate_receive_extended_data(port,
-					PD_DATA_BATTERY_STATUS, len), 0, "%d");
+			TEST_NE(simulate_receive_extended_data(
+					port, PD_DATA_BATTERY_STATUS, len),
+				0, "%d");
 		}
 	} else {
 		/*
@@ -1107,13 +1136,14 @@ static int test_receive_extended_data_msg(void)
 		 */
 		task_wake(PD_PORT_TO_TASK_ID(port));
 		task_wait_event(40 * MSEC);
-		TEST_NE(simulate_receive_extended_data(port,
-					PD_DATA_BATTERY_STATUS, 29), 0, "%d");
+		TEST_NE(simulate_receive_extended_data(
+				port, PD_DATA_BATTERY_STATUS, 29),
+			0, "%d");
 
 		task_wake(PD_PORT_TO_TASK_ID(port));
 		task_wait_event(40 * MSEC);
-		TEST_NE(simulate_receive_data(port,
-				PD_DATA_BATTERY_STATUS, 28), 0, "%d");
+		TEST_NE(simulate_receive_data(port, PD_DATA_BATTERY_STATUS, 28),
+			0, "%d");
 	}
 
 	enable_prl(port, 0);
@@ -1134,21 +1164,20 @@ static int test_send_soft_reset_msg(void)
 	task_wake(PD_PORT_TO_TASK_ID(port));
 	task_wait_event(40 * MSEC);
 
-	TEST_EQ(prl_tx_get_state(port),
-				PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u");
+	TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u");
 
-	TEST_NE(simulate_send_ctrl_msg_request_from_pe(port,
-			TCPC_TX_SOP, PD_CTRL_SOFT_RESET), 0, "%d");
+	TEST_NE(simulate_send_ctrl_msg_request_from_pe(port, TCPCI_MSG_SOP,
+						       PD_CTRL_SOFT_RESET),
+		0, "%d");
 
 	task_wake(PD_PORT_TO_TASK_ID(port));
 	task_wait_event(30 * MSEC);
 
-	simulate_goodcrc(port, pd_port[port].power_role,
-						pd_port[port].msg_tx_id);
+	simulate_goodcrc(port, get_partner_power_role(port),
+			 pd_port[port].msg_tx_id);
 	inc_tx_id(port);
 
-	TEST_EQ(prl_tx_get_state(port),
-			PRL_TX_LAYER_RESET_FOR_TRANSMIT, "%u");
+	TEST_EQ(prl_tx_get_state(port), PRL_TX_LAYER_RESET_FOR_TRANSMIT, "%u");
 
 	cycle_through_state_machine(port, 3, 10 * MSEC);
 
@@ -1182,19 +1211,18 @@ static int test_pe_execute_hard_reset_msg(void)
 	prl_execute_hard_reset(port);
 
 	TEST_EQ(prl_hr_get_state(port), PRL_HR_RESET_LAYER, "%u");
-	TEST_EQ(prl_tx_get_state(port),
-			PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u");
+	TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u");
 
 	cycle_through_state_machine(port, 1, 10 * MSEC);
 
-	TEST_EQ(prl_hr_get_state(port),
-			PRL_HR_WAIT_FOR_PHY_HARD_RESET_COMPLETE, "%u");
+	TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_PHY_HARD_RESET_COMPLETE,
+		"%u");
 
 	cycle_through_state_machine(port, 2, PD_T_PS_HARD_RESET);
 	TEST_NE(pd_port[port].mock_pe_hard_reset_sent, 0, "%d");
 
-	TEST_EQ(prl_hr_get_state(port),
-			PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE, "%u");
+	TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE,
+		"%u");
 
 	/* Simulate policy engine indicating that it is done hard reset */
 	prl_hard_reset_complete(port);
@@ -1229,19 +1257,18 @@ static int test_phy_execute_hard_reset_msg(void)
 	pd_execute_hard_reset(port);
 
 	TEST_EQ(prl_hr_get_state(port), PRL_HR_RESET_LAYER, "%u");
-	TEST_EQ(prl_tx_get_state(port),
-			PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u");
+	TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u");
 
 	cycle_through_state_machine(port, 1, 10 * MSEC);
 
-	TEST_EQ(prl_hr_get_state(port),
-			PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE, "%u");
+	TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE,
+		"%u");
 
 	cycle_through_state_machine(port, 2, PD_T_PS_HARD_RESET);
 	TEST_NE(pd_port[port].mock_pe_got_hard_reset, 0, "%d");
 
-	TEST_EQ(prl_hr_get_state(port),
-			PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE, "%u");
+	TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE,
+		"%u");
 
 	/* Simulate policy engine indicating that it is done hard reset */
 	prl_hard_reset_complete(port);
@@ -1274,7 +1301,7 @@ void before_test(void)
 	cycle_through_state_machine(PORT0, 10, MSEC);
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/usb_prl_old.tasklist b/test/usb_prl_old.tasklist
index eb41326e3e..5c7f804157 100644
--- a/test/usb_prl_old.tasklist
+++ b/test/usb_prl_old.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/usb_sm_checks.c b/test/usb_sm_checks.c
index 03e5aa23c2..2204326d97 100644
--- a/test/usb_sm_checks.c
+++ b/test/usb_sm_checks.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -9,10 +9,10 @@
 #include "test_util.h"
 #include "timer.h"
 #include "usb_pd.h"
+#include "usb_pd_test_util.h"
 #include "usb_sm.h"
 #include "usb_tc_sm.h"
 #include "util.h"
-#include "usb_pd_test_util.h"
 #include "vpd_api.h"
 
 #ifdef CONFIG_USB_TYPEC_SM
@@ -39,7 +39,7 @@ const struct test_sm_data test_pe_sm_data[] = {};
 const int test_pe_sm_data_size;
 #endif
 
-test_static int test_no_parent_cycles(const struct test_sm_data * const sm_data)
+test_static int test_no_parent_cycles(const struct test_sm_data *const sm_data)
 {
 	int i;
 
@@ -116,7 +116,7 @@ __override void print_current_state(const int port)
 	state_printed = 1;
 }
 
-static int test_all_states_named(const struct test_sm_data * const sm_data)
+static int test_all_states_named(const struct test_sm_data *const sm_data)
 {
 	int i;
 
@@ -125,12 +125,10 @@ static int test_all_states_named(const struct test_sm_data * const sm_data)
 
 		state_printed = 0;
 
-		if (current->entry)
+		if (current->entry &&
+		    (i >= sm_data->names_size || sm_data->names[i] == NULL)) {
 			current->entry(0);
-
-		if (state_printed) {
-			if (i >= sm_data->names_size ||
-			    sm_data->names[i] == NULL) {
+			if (state_printed) {
 				ccprintf("State %d does not have a name!\n", i);
 				TEST_ASSERT(0);
 			}
@@ -187,4 +185,3 @@ int test_pe_all_states_named(void)
 
 	return EC_SUCCESS;
 }
-
diff --git a/test/usb_sm_checks.h b/test/usb_sm_checks.h
index 92529ac385..1041afbaa4 100644
--- a/test/usb_sm_checks.h
+++ b/test/usb_sm_checks.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,12 +11,10 @@
 int test_tc_no_parent_cycles(void);
 int test_tc_all_states_named(void);
 
-
 int test_prl_no_parent_cycles(void);
 int test_prl_all_states_named(void);
 
-
 int test_pe_no_parent_cycles(void);
 int test_pe_all_states_named(void);
 
-#endif /* __CROS_EC_USB_SM_CHECKS_H */
\ No newline at end of file
+#endif /* __CROS_EC_USB_SM_CHECKS_H */
diff --git a/test/usb_sm_framework_h3.c b/test/usb_sm_framework_h3.c
index ba544a749a..704bae8f9b 100644
--- a/test/usb_sm_framework_h3.c
+++ b/test/usb_sm_framework_h3.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -9,10 +9,10 @@
 #include "test_util.h"
 #include "timer.h"
 #include "usb_pd.h"
+#include "usb_pd_test_util.h"
 #include "usb_sm.h"
 #include "usb_tc_sm.h"
 #include "util.h"
-#include "usb_pd_test_util.h"
 #include "vpd_api.h"
 
 /*
@@ -112,7 +112,7 @@ enum state_id {
 	EXIT_C,
 };
 
-#define PORT0   0
+#define PORT0 0
 
 struct sm_ {
 	/* struct sm_obj must be first */
@@ -198,7 +198,6 @@ static void sm_test_super_A2_exit(const int port)
 	sm[port].seq[sm[port].idx++] = EXIT_A2;
 }
 
-
 static void sm_test_super_B2_entry(const int port)
 {
 	sm[port].seq[sm[port].idx++] = ENTER_B2;
@@ -269,7 +268,6 @@ static void sm_test_A4_exit(const int port)
 	sm[port].seq[sm[port].idx++] = EXIT_A4;
 }
 
-
 static void sm_test_A5_entry(const int port)
 {
 	sm[port].sv_tmp = 0;
@@ -291,7 +289,6 @@ static void sm_test_A5_exit(const int port)
 	sm[port].seq[sm[port].idx++] = EXIT_A5;
 }
 
-
 static void sm_test_A6_entry(const int port)
 {
 	sm[port].sv_tmp = 0;
@@ -355,7 +352,6 @@ static void sm_test_B4_exit(const int port)
 	sm[port].seq[sm[port].idx++] = EXIT_B4;
 }
 
-
 static void sm_test_B5_entry(const int port)
 {
 	sm[port].sv_tmp = 0;
@@ -377,7 +373,6 @@ static void sm_test_B5_exit(const int port)
 	sm[port].seq[sm[port].idx++] = EXIT_B5;
 }
 
-
 static void sm_test_B6_entry(const int port)
 {
 	sm[port].sv_tmp = 0;
@@ -440,63 +435,88 @@ test_static int test_hierarchy_0(void)
 	set_state_sm(port, SM_TEST_A4);
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], ENTER_A4, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A4, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A4, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_A4, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B4, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A4, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B4, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_B4, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_B4, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_B4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B5, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_B4, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B5, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_B5, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_B5, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_B5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B6, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_B5, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B6, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_B6, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_B6, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_B6, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_C, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_B6, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_C, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_C, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_C, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_C, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A7, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_C, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A7, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A7, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_A7, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A7, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A6, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A7, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A6, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A6, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_A6, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A6, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A5, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A6, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A5, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A5, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_A5, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A4, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A5, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A4, "%d");
+	++i;
 
 	for (; i < SEQUENCE_SIZE; i++)
 		TEST_EQ(sm[port].seq[i], 0, "%d");
@@ -512,71 +532,104 @@ test_static int test_hierarchy_1(void)
 	set_state_sm(port, SM_TEST_A4);
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], ENTER_A3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A4, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A4, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A3, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_A4, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_A3, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_A3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B4, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A4, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B4, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_B4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_B3, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_B4, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_B3, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_B4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_B3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B5, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_B4, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], EXIT_B3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B5, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_B5, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_B5, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_B5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B6, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_B5, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B6, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_B6, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_B6, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_B6, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_C, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_B6, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_C, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_C, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_C, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_C, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A7, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_C, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A7, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A7, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_A7, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A7, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A6, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A7, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A6, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A6, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_A6, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A6, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A5, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A6, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A5, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A3, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_A5, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_A3, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A4, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A5, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A4, "%d");
+	++i;
 
 	for (i = 33; i < SEQUENCE_SIZE; i++)
 		TEST_EQ(sm[port].seq[i], 0, "%d");
@@ -586,88 +639,130 @@ test_static int test_hierarchy_1(void)
 
 test_static int test_hierarchy_2(void)
 {
-
 	int port = PORT0;
 	int i = 0;
 
 	set_state_sm(port, SM_TEST_A4);
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], ENTER_A2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A4, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A2, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A4, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A2, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_A4, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_A3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_A2, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_A3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_A2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B4, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A4, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A2, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B2, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B4, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_B4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_B3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_B2, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_B4, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_B3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_B2, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_B4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_B3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B5, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_B4, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], EXIT_B3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B5, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_B5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_B2, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_B5, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_B2, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_B5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_B2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B6, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_B5, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], EXIT_B2, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B6, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_B6, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_B6, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_B6, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_C, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_B6, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_C, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_C, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_C, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_C, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A7, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_C, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A7, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A7, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_A7, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A7, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A6, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A7, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A2, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A6, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A6, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A2, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_A6, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_A2, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A6, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A5, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A6, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A5, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A2, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_A5, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_A3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_A2, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A4, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A5, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A4, "%d");
+	++i;
 
 	for (; i < SEQUENCE_SIZE; i++)
 		TEST_EQ(sm[port].seq[i], 0, "%d");
@@ -677,100 +772,154 @@ test_static int test_hierarchy_2(void)
 
 test_static int test_hierarchy_3(void)
 {
-
 	int port = PORT0;
 	int i = 0;
 
 	set_state_sm(port, SM_TEST_A4);
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], ENTER_A1, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A4, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A1, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_A3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_A2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_A1, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B1, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B4, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_B4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_B3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_B2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_B1, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_B4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_B3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B5, "%d"); ++i;
-
+	TEST_EQ(sm[port].seq[i], ENTER_A1, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A2, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A4, "%d");
+	++i;
+
+	run_sm();
+	TEST_EQ(sm[port].seq[i], RUN_A4, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_A3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_A2, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_A1, "%d");
+	++i;
+
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_B5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_B2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_B1, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A4, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A2, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A1, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B1, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B2, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B4, "%d");
+	++i;
+
+	run_sm();
+	TEST_EQ(sm[port].seq[i], RUN_B4, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_B3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_B2, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_B1, "%d");
+	++i;
+
+	run_sm();
+	TEST_EQ(sm[port].seq[i], EXIT_B4, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], EXIT_B3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B5, "%d");
+	++i;
+
+	run_sm();
+	TEST_EQ(sm[port].seq[i], RUN_B5, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_B2, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_B1, "%d");
+	++i;
+
+	run_sm();
+	TEST_EQ(sm[port].seq[i], EXIT_B5, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], EXIT_B2, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B6, "%d");
+	++i;
+
+	run_sm();
+	TEST_EQ(sm[port].seq[i], RUN_B6, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_B1, "%d");
+	++i;
+
+	run_sm();
+	TEST_EQ(sm[port].seq[i], EXIT_B6, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], EXIT_B1, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_C, "%d");
+	++i;
+
+	run_sm();
+	TEST_EQ(sm[port].seq[i], RUN_C, "%d");
+	++i;
+
+	run_sm();
+	TEST_EQ(sm[port].seq[i], EXIT_C, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A1, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A7, "%d");
+	++i;
+
+	run_sm();
+	TEST_EQ(sm[port].seq[i], RUN_A7, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_A1, "%d");
+	++i;
+
+	run_sm();
+	TEST_EQ(sm[port].seq[i], EXIT_A7, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A2, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A6, "%d");
+	++i;
+
+	run_sm();
+	TEST_EQ(sm[port].seq[i], RUN_A6, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_A2, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_A1, "%d");
+	++i;
 
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_B5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_B2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B6, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_B6, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_B1, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_B6, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_B1, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_C, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_C, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_C, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A1, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A7, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A7, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A1, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A7, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A6, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A6, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A1, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A6, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A5, "%d"); ++i;
+	run_sm();
+	TEST_EQ(sm[port].seq[i], EXIT_A6, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A5, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A1, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_A5, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_A3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_A2, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_A1, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A4, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A5, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A4, "%d");
+	++i;
 
 	for (; i < SEQUENCE_SIZE; i++)
 		TEST_EQ(sm[port].seq[i], 0, "%d");
@@ -787,35 +936,53 @@ test_static int test_set_state_from_parents(void)
 	test_control.a3_entry_to = &states[SM_TEST_B4];
 	run_sm();
 	set_state_sm(port, SM_TEST_A4);
-	TEST_EQ(sm[port].seq[i], ENTER_A1, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A3, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A1, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A2, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A3, "%d");
+	++i;
 	/* Does not enter or exit A4 */
-	TEST_EQ(sm[port].seq[i], EXIT_A3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_A2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_A1, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B1, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B4, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A2, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A1, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B1, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B2, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B4, "%d");
+	++i;
 	/* Ensure we didn't go further than above statements */
 	TEST_EQ(sm[port].seq[i], 0, "%d");
 
 	test_control.b3_run_to = &states[SM_TEST_B5];
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_B4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_B3, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_B4, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_B3, "%d");
+	++i;
 	/* Does not run b2 or b1 */
-	TEST_EQ(sm[port].seq[i], EXIT_B4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_B3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B5, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_B4, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], EXIT_B3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B5, "%d");
+	++i;
 	/* Ensure we didn't go further than above statements */
 	TEST_EQ(sm[port].seq[i], 0, "%d");
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_B5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_B2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_B1, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_B5, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_B2, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_B1, "%d");
+	++i;
 	/* Ensure we didn't go further than above statements */
 	TEST_EQ(sm[port].seq[i], 0, "%d");
 
@@ -827,15 +994,24 @@ test_static int test_set_state_from_parents(void)
 	test_control.c_entry_to = &states[SM_TEST_A7];
 	test_control.c_exit_to = &states[SM_TEST_A4];
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_B5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_B2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B6, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_B6, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_B1, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_C, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_C, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A1, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A7, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_B5, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], EXIT_B2, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B6, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], EXIT_B6, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], EXIT_B1, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_C, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], EXIT_C, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A1, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A7, "%d");
+	++i;
 	/* Ensure we didn't go further than above statements */
 	TEST_EQ(sm[port].seq[i], 0, "%d");
 
@@ -985,7 +1161,7 @@ int test_task(void *u)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 #if defined(TEST_USB_SM_FRAMEWORK_H3)
diff --git a/test/usb_sm_framework_h3.tasklist b/test/usb_sm_framework_h3.tasklist
index 998998fd6c..9db4e49e5e 100644
--- a/test/usb_sm_framework_h3.tasklist
+++ b/test/usb_sm_framework_h3.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/usb_tcpmv2_compliance.c b/test/usb_tcpmv2_compliance.c
new file mode 100644
index 0000000000..2acd2c1660
--- /dev/null
+++ b/test/usb_tcpmv2_compliance.c
@@ -0,0 +1,63 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "mock/tcpci_i2c_mock.h"
+#include "mock/usb_mux_mock.h"
+#include "task.h"
+#include "test_util.h"
+#include "timer.h"
+#include "usb_tc_sm.h"
+#include "usb_tcpmv2_compliance.h"
+
+void before_test(void)
+{
+	partner_set_pd_rev(PD_REV30);
+	partner_tx_msg_id_reset(TCPCI_MSG_SOP_ALL);
+
+	mock_usb_mux_reset();
+	mock_tcpci_reset();
+
+	/* Restart the PD task and let it settle */
+	task_set_event(TASK_ID_PD_C0, TASK_EVENT_RESET_DONE);
+	task_wait_event(SECOND);
+
+	/*
+	 * Default to not allowing DUT to TRY.SRC and set it to be allowed
+	 * specifically in the TRY.SRC tests
+	 */
+	tc_try_src_override(TRY_SRC_OVERRIDE_OFF);
+}
+
+void run_test(int argc, const char **argv)
+{
+	test_reset();
+
+	RUN_TEST(test_td_pd_ll_e3_dfp);
+	RUN_TEST(test_td_pd_ll_e3_ufp);
+	RUN_TEST(test_td_pd_ll_e4_dfp);
+	RUN_TEST(test_td_pd_ll_e4_ufp);
+	RUN_TEST(test_td_pd_ll_e5_dfp);
+	RUN_TEST(test_td_pd_ll_e5_ufp);
+	RUN_TEST(test_td_pd_src_e1);
+	RUN_TEST(test_td_pd_src_e2);
+	RUN_TEST(test_td_pd_src_e5);
+
+	RUN_TEST(test_td_pd_src3_e1);
+	RUN_TEST(test_td_pd_src3_e7);
+	RUN_TEST(test_td_pd_src3_e8);
+	RUN_TEST(test_td_pd_src3_e9);
+	RUN_TEST(test_td_pd_src3_e26);
+	RUN_TEST(test_td_pd_src3_e32);
+	RUN_TEST(test_td_pd_snk3_e12);
+
+	RUN_TEST(test_td_pd_vndi3_e3_dfp);
+	RUN_TEST(test_td_pd_vndi3_e3_ufp);
+
+	RUN_TEST(test_connect_as_nonpd_sink);
+	RUN_TEST(test_retry_count_sop);
+	RUN_TEST(test_retry_count_hard_reset);
+
+	test_print_result();
+}
diff --git a/test/usb_tcpmv2_compliance.h b/test/usb_tcpmv2_compliance.h
new file mode 100644
index 0000000000..0ca4717173
--- /dev/null
+++ b/test/usb_tcpmv2_compliance.h
@@ -0,0 +1,95 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef USB_TCPMV2_COMPLIANCE_H
+#define USB_TCPMV2_COMPLIANCE_H
+
+#define PORT0 0
+
+enum mock_cc_state {
+	MOCK_CC_SRC_OPEN = 0,
+	MOCK_CC_SNK_OPEN = 0,
+	MOCK_CC_SRC_RA = 1,
+	MOCK_CC_SNK_RP_DEF = 1,
+	MOCK_CC_SRC_RD = 2,
+	MOCK_CC_SNK_RP_1_5 = 2,
+	MOCK_CC_SNK_RP_3_0 = 3,
+};
+enum mock_connect_result {
+	MOCK_CC_DUT_IS_SRC = 0,
+	MOCK_CC_DUT_IS_SNK = 1,
+};
+
+extern uint32_t rdo;
+extern uint32_t pdo;
+
+extern const struct tcpc_config_t tcpc_config[];
+extern const struct usb_mux_chain usb_muxes[];
+
+void mock_set_cc(enum mock_connect_result cr, enum mock_cc_state cc1,
+		 enum mock_cc_state cc2);
+void mock_set_role(int drp, enum tcpc_rp_value rp, enum tcpc_cc_pull cc1,
+		   enum tcpc_cc_pull cc2);
+void mock_set_alert(int alert);
+uint16_t tcpc_get_alert_status(void);
+bool vboot_allow_usb_pd(void);
+int pd_check_vconn_swap(int port);
+void board_reset_pd_mcu(void);
+
+int tcpci_startup(void);
+
+void partner_set_data_role(enum pd_data_role data_role);
+enum pd_data_role partner_get_data_role(void);
+
+void partner_set_power_role(enum pd_power_role power_role);
+enum pd_power_role partner_get_power_role(void);
+
+void partner_set_pd_rev(enum pd_rev_type pd_rev);
+enum pd_rev_type partner_get_pd_rev(void);
+
+#define TCPCI_MSG_SOP_ALL -1
+void partner_tx_msg_id_reset(int sop);
+
+void partner_send_msg(enum tcpci_msg_type sop, uint16_t type, uint16_t cnt,
+		      uint16_t ext, uint32_t *payload);
+
+int handle_attach_expected_msgs(enum pd_data_role data_role);
+
+enum proc_pd_e1_attach {
+	INITIAL_ATTACH = BIT(0),
+	ALREADY_ATTACHED = BIT(1),
+	INITIAL_AND_ALREADY_ATTACHED = INITIAL_ATTACH | ALREADY_ATTACHED
+};
+int proc_pd_e1(enum pd_data_role data_role, enum proc_pd_e1_attach attach);
+int proc_pd_e3(void);
+
+int test_td_pd_ll_e3_dfp(void);
+int test_td_pd_ll_e3_ufp(void);
+int test_td_pd_ll_e4_dfp(void);
+int test_td_pd_ll_e4_ufp(void);
+int test_td_pd_ll_e5_dfp(void);
+int test_td_pd_ll_e5_ufp(void);
+
+int test_td_pd_src_e1(void);
+int test_td_pd_src_e2(void);
+int test_td_pd_src_e5(void);
+
+int test_td_pd_src3_e1(void);
+int test_td_pd_src3_e7(void);
+int test_td_pd_src3_e8(void);
+int test_td_pd_src3_e9(void);
+int test_td_pd_src3_e26(void);
+int test_td_pd_src3_e32(void);
+
+int test_td_pd_snk3_e12(void);
+
+int test_td_pd_vndi3_e3_dfp(void);
+int test_td_pd_vndi3_e3_ufp(void);
+
+int test_connect_as_nonpd_sink(void);
+int test_retry_count_sop(void);
+int test_retry_count_hard_reset(void);
+
+#endif /* USB_TCPMV2_COMPLIANCE_H */
diff --git a/test/usb_tcpmv2_compliance.mocklist b/test/usb_tcpmv2_compliance.mocklist
new file mode 100644
index 0000000000..311397fe43
--- /dev/null
+++ b/test/usb_tcpmv2_compliance.mocklist
@@ -0,0 +1,9 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+ #define CONFIG_TEST_MOCK_LIST  \
+	MOCK(USB_MUX)           \
+	MOCK(TCPCI_I2C)         \
+	MOCK(BATTERY)
diff --git a/test/usb_tcpmv2_compliance.tasklist b/test/usb_tcpmv2_compliance.tasklist
new file mode 100644
index 0000000000..794669adbe
--- /dev/null
+++ b/test/usb_tcpmv2_compliance.tasklist
@@ -0,0 +1,11 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TEST_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST \
+	TASK_TEST(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_TEST(PD_INT_C0, pd_interrupt_handler_task, 0, LARGER_TASK_STACK_SIZE)
diff --git a/test/usb_tcpmv2_compliance_common.c b/test/usb_tcpmv2_compliance_common.c
new file mode 100644
index 0000000000..ed46d7baa0
--- /dev/null
+++ b/test/usb_tcpmv2_compliance_common.c
@@ -0,0 +1,489 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "hooks.h"
+#include "mock/tcpci_i2c_mock.h"
+#include "mock/usb_mux_mock.h"
+#include "task.h"
+#include "tcpm/tcpci.h"
+#include "test_util.h"
+#include "timer.h"
+#include "usb_tc_sm.h"
+#include "usb_tcpmv2_compliance.h"
+
+uint32_t rdo = RDO_FIXED(1, 500, 500, 0);
+uint32_t pdo = PDO_FIXED(5000, 3000,
+			 PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |
+				 PDO_FIXED_COMM_CAP);
+
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_HOST_TCPC,
+			.addr_flags = MOCK_TCPCI_I2C_ADDR_FLAGS,
+		},
+		.drv = &tcpci_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+	},
+};
+
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { {
+	.mux =
+		&(const struct usb_mux){
+			.driver = &mock_usb_mux_driver,
+		},
+} };
+
+void mock_set_cc(enum mock_connect_result cr, enum mock_cc_state cc1,
+		 enum mock_cc_state cc2)
+{
+	mock_tcpci_set_reg(TCPC_REG_CC_STATUS,
+			   TCPC_REG_CC_STATUS_SET(cr, cc1, cc2));
+}
+
+void mock_set_role(int drp, enum tcpc_rp_value rp, enum tcpc_cc_pull cc1,
+		   enum tcpc_cc_pull cc2)
+{
+	mock_tcpci_set_reg(TCPC_REG_ROLE_CTRL,
+			   TCPC_REG_ROLE_CTRL_SET(drp, rp, cc1, cc2));
+}
+
+static int mock_alert_count;
+void mock_set_alert(int alert)
+{
+	mock_tcpci_set_reg_bits(TCPC_REG_ALERT, alert);
+	mock_alert_count = 1;
+	schedule_deferred_pd_interrupt(PORT0);
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	ccprints("mock_alert_count %d", mock_alert_count);
+	if (mock_alert_count > 0) {
+		mock_alert_count--;
+		return PD_STATUS_TCPC_ALERT_0;
+	}
+	return 0;
+}
+
+bool vboot_allow_usb_pd(void)
+{
+	return 1;
+}
+
+int pd_check_vconn_swap(int port)
+{
+	return 1;
+}
+
+void board_reset_pd_mcu(void)
+{
+}
+
+/*****************************************************************************
+ * Partner utility functions
+ */
+static enum pd_data_role partner_data_role;
+void partner_set_data_role(enum pd_data_role data_role)
+{
+	partner_data_role = data_role;
+}
+enum pd_data_role partner_get_data_role(void)
+{
+	return partner_data_role;
+}
+
+static enum pd_power_role partner_power_role;
+void partner_set_power_role(enum pd_power_role power_role)
+{
+	partner_power_role = power_role;
+}
+enum pd_power_role partner_get_power_role(void)
+{
+	return partner_power_role;
+}
+
+static enum pd_rev_type partner_pd_rev;
+void partner_set_pd_rev(enum pd_rev_type pd_rev)
+{
+	partner_pd_rev = pd_rev;
+}
+enum pd_rev_type partner_get_pd_rev(void)
+{
+	return partner_pd_rev;
+}
+
+static int partner_tx_id[NUM_SOP_STAR_TYPES];
+void partner_tx_msg_id_reset(int sop)
+{
+	if (sop == TCPCI_MSG_SOP_ALL)
+		for (sop = 0; sop < NUM_SOP_STAR_TYPES; ++sop)
+			partner_tx_id[sop] = 0;
+	else
+		partner_tx_id[sop] = 0;
+}
+
+void partner_send_msg(enum tcpci_msg_type sop, uint16_t type, uint16_t cnt,
+		      uint16_t ext, uint32_t *payload)
+{
+	uint16_t header;
+
+	partner_tx_id[sop] &= 7;
+	header = PD_HEADER(type,
+			   sop == TCPCI_MSG_SOP ? partner_get_power_role() :
+						  PD_PLUG_FROM_CABLE,
+			   partner_get_data_role(), partner_tx_id[sop], cnt,
+			   partner_get_pd_rev(), ext);
+
+	mock_tcpci_receive(sop, header, payload);
+	++partner_tx_id[sop];
+	mock_set_alert(TCPC_REG_ALERT_RX_STATUS);
+}
+
+/*****************************************************************************
+ * TCPCI clean power up
+ */
+int tcpci_startup(void)
+{
+	/* Should be in low power mode before AP boots. */
+	TEST_EQ(mock_tcpci_get_reg(TCPC_REG_COMMAND), TCPC_REG_COMMAND_I2CIDLE,
+		"%d");
+	task_wait_event(10 * SECOND);
+
+	hook_notify(HOOK_CHIPSET_STARTUP);
+	task_wait_event(5 * MSEC);
+	hook_notify(HOOK_CHIPSET_RESUME);
+
+	task_wait_event(10 * SECOND);
+	/* Should be in low power mode and DRP auto-toggling with AP in S0. */
+	TEST_EQ((mock_tcpci_get_reg(TCPC_REG_ROLE_CTRL) &
+		 TCPC_REG_ROLE_CTRL_DRP_MASK),
+		TCPC_REG_ROLE_CTRL_DRP_MASK, "%d");
+	/* TODO: check previous command was TCPC_REG_COMMAND_LOOK4CONNECTION */
+	TEST_EQ(mock_tcpci_get_reg(TCPC_REG_COMMAND), TCPC_REG_COMMAND_I2CIDLE,
+		"%d");
+
+	/* TODO: this should be performed in TCPCI mock on startup but needs
+	 * more TCPCI functionality added before that can happen.  So until
+	 * that time, if the FAULT register is set, send the alert here.
+	 */
+	if (mock_tcpci_get_reg(TCPC_REG_FAULT_STATUS))
+		mock_set_alert(TCPC_REG_ALERT_FAULT);
+
+	return EC_SUCCESS;
+}
+
+/*****************************************************************************
+ * PROC.PD.E1. Bring-up procedure
+ */
+int proc_pd_e1(enum pd_data_role data_role, enum proc_pd_e1_attach attach)
+{
+	if (attach & INITIAL_ATTACH) {
+		/*
+		 * a) The test starts in a disconnected state.
+		 */
+		mock_tcpci_set_reg(TCPC_REG_EXT_STATUS,
+				   TCPC_REG_EXT_STATUS_SAFE0V);
+		mock_set_alert(TCPC_REG_ALERT_EXT_STATUS);
+		task_wait_event(10 * SECOND);
+		TEST_EQ(pd_get_data_role(I2C_PORT_HOST_TCPC),
+			PD_ROLE_DISCONNECTED, "%d");
+
+		partner_set_data_role((data_role == PD_ROLE_UFP) ? PD_ROLE_DFP :
+								   PD_ROLE_UFP);
+
+		partner_set_power_role((data_role == PD_ROLE_UFP) ?
+					       PD_ROLE_SOURCE :
+					       PD_ROLE_SINK);
+
+		switch (partner_get_power_role()) {
+		case PD_ROLE_SOURCE:
+			/*
+			 * b) The tester applies Rp (PD3=1.5A, PD2=3A) and
+			 *    waits for the UUT attachment.
+			 */
+			mock_set_cc(MOCK_CC_DUT_IS_SNK, MOCK_CC_SNK_OPEN,
+				    (partner_get_pd_rev() == PD_REV30 ?
+					     MOCK_CC_SNK_RP_1_5 :
+					     MOCK_CC_SNK_RP_3_0));
+			mock_set_alert(TCPC_REG_ALERT_CC_STATUS);
+			task_wait_event(5 * MSEC);
+
+			/*
+			 * c) If Ra is detected, the tester applies Vconn.
+			 */
+
+			/*
+			 * d) The tester applies Vbus and waits 50 ms.
+			 */
+			mock_tcpci_set_reg_bits(
+				TCPC_REG_POWER_STATUS,
+				TCPC_REG_POWER_STATUS_VBUS_PRES);
+
+			mock_tcpci_clr_reg_bits(TCPC_REG_EXT_STATUS,
+						TCPC_REG_EXT_STATUS_SAFE0V);
+			mock_set_alert(TCPC_REG_ALERT_EXT_STATUS |
+				       TCPC_REG_ALERT_POWER_STATUS);
+			task_wait_event(50 * MSEC);
+			break;
+
+		case PD_ROLE_SINK:
+			/*
+			 * b) The tester applies Rd and waits for Vbus for
+			 *    tNoResponse max (5.5 s).
+			 */
+			mock_set_cc(MOCK_CC_DUT_IS_SRC, MOCK_CC_SRC_OPEN,
+				    MOCK_CC_SRC_RD);
+			mock_set_alert(TCPC_REG_ALERT_CC_STATUS);
+			break;
+		}
+	}
+
+	if (attach & ALREADY_ATTACHED) {
+		switch (partner_get_power_role()) {
+		case PD_ROLE_SOURCE:
+			/*
+			 * e) The tester transmits Source Capabilities until
+			 *    reception of GoodCrc for tNoResponse max (5.5s).
+			 *    The Source Capabilities includes Fixed 5V 3A PDO.
+			 */
+			task_wait_event(1 * MSEC);
+			partner_send_msg(TCPCI_MSG_SOP, PD_DATA_SOURCE_CAP, 1,
+					 0, &pdo);
+
+			/*
+			 * f) The tester waits for the Request from the UUT for
+			 *    tSenderResponse max (30 ms).
+			 */
+			TEST_EQ(verify_tcpci_transmit(TCPCI_MSG_SOP, 0,
+						      PD_DATA_REQUEST),
+				EC_SUCCESS, "%d");
+			mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
+
+			/*
+			 * g) The tester sends Accept, and when Vbus is stable
+			 *    at the target voltage, sends PS_RDY.
+			 */
+			partner_send_msg(TCPCI_MSG_SOP, PD_CTRL_ACCEPT, 0, 0,
+					 NULL);
+			task_wait_event(10 * MSEC);
+			partner_send_msg(TCPCI_MSG_SOP, PD_CTRL_PS_RDY, 0, 0,
+					 NULL);
+			task_wait_event(1 * MSEC);
+
+			TEST_EQ(tc_is_attached_snk(PORT0), true, "%d");
+			break;
+
+		case PD_ROLE_SINK:
+			/*
+			 * c) The tester waits Source Capabilities for for
+			 *    tNoResponse max (5.5 s).
+			 */
+			TEST_EQ(verify_tcpci_transmit(TCPCI_MSG_SOP, 0,
+						      PD_DATA_SOURCE_CAP),
+				EC_SUCCESS, "%d");
+
+			/*
+			 * d) The tester replies GoodCrc on reception of the
+			 *    Source Capabilities.
+			 */
+			mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
+			task_wait_event(10 * MSEC);
+
+			/*
+			 * e) The tester requests 5V 0.5A.
+			 */
+			partner_send_msg(TCPCI_MSG_SOP, PD_DATA_REQUEST, 1, 0,
+					 &rdo);
+
+			TEST_EQ(verify_tcpci_transmit(TCPCI_MSG_SOP,
+						      PD_CTRL_ACCEPT, 0),
+				EC_SUCCESS, "%d");
+			mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
+
+			/*
+			 * f) The tester waits PS_RDY for tPSSourceOn max
+			 *    (480 ms).
+			 */
+			TEST_EQ(verify_tcpci_transmit(TCPCI_MSG_SOP,
+						      PD_CTRL_PS_RDY, 0),
+				EC_SUCCESS, "%d");
+			mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
+
+			TEST_EQ(tc_is_attached_src(PORT0), true, "%d");
+			break;
+		}
+		TEST_EQ(pd_get_data_role(I2C_PORT_HOST_TCPC), data_role, "%d");
+	}
+
+	return EC_SUCCESS;
+}
+
+/*****************************************************************************
+ * PROC.PD.E3. Wait to Start AMS for DFP(Source) UUT
+ */
+int proc_pd_e3(void)
+{
+	/*
+	 * Make sure we are idle. Reject everything that is pending
+	 */
+	TEST_EQ(handle_attach_expected_msgs(PD_ROLE_DFP), EC_SUCCESS, "%d");
+
+	/*
+	 * PROC.PD.E3. Wait to Start AMS for DFP(Source) UUT:
+	 * a) The Tester keeps monitoring the Rp value and if the UUT doesn't
+	 * set the value to SinkTXOK if it doesn't have anything to send in 1s,
+	 * the test fails. During this period, the Tester replies any message
+	 * sent from the UUT with a proper response.
+	 */
+	TEST_EQ(tc_is_attached_src(PORT0), true, "%d");
+	TEST_EQ(TCPC_REG_ROLE_CTRL_RP(mock_tcpci_get_reg(TCPC_REG_ROLE_CTRL)),
+		SINK_TX_OK, "%d");
+
+	task_wait_event(10 * SECOND);
+	return EC_SUCCESS;
+}
+
+/*****************************************************************************
+ * handle_attach_expected_msgs
+ *
+ * Depending on the data role, the DUT will send a sequence of messages on
+ * attach. Most of these can be rejected.
+ */
+int handle_attach_expected_msgs(enum pd_data_role data_role)
+{
+	int rv;
+	int found_index;
+	struct possible_tx possible[5];
+
+	if (data_role == PD_ROLE_DFP) {
+		possible[0].tx_type = TCPCI_MSG_SOP;
+		possible[0].ctrl_msg = PD_CTRL_GET_SOURCE_CAP;
+		possible[0].data_msg = 0;
+
+		possible[1].tx_type = TCPCI_MSG_SOP;
+		possible[1].ctrl_msg = PD_CTRL_GET_SINK_CAP;
+		possible[1].data_msg = 0;
+
+		possible[2].tx_type = TCPCI_MSG_SOP_PRIME;
+		possible[2].ctrl_msg = 0;
+		possible[2].data_msg = PD_DATA_VENDOR_DEF;
+
+		possible[3].tx_type = TCPCI_MSG_SOP;
+		possible[3].ctrl_msg = 0;
+		possible[3].data_msg = PD_DATA_VENDOR_DEF;
+
+		possible[4].tx_type = TCPCI_MSG_SOP;
+		possible[4].ctrl_msg = PD_CTRL_GET_REVISION;
+		possible[4].data_msg = 0;
+
+		do {
+			rv = verify_tcpci_possible_tx(possible, 5, &found_index,
+						      NULL, 0, NULL, -1);
+
+			TEST_NE(rv, EC_ERROR_UNKNOWN, "%d");
+			if (rv == EC_ERROR_TIMEOUT)
+				break;
+
+			mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
+			task_wait_event(10 * MSEC);
+
+			switch (found_index) {
+			case 0: /* TCPCI_MSG_SOP PD_CTRL_GET_SOURCE_CAP */
+				partner_send_msg(TCPCI_MSG_SOP,
+						 PD_DATA_SOURCE_CAP, 1, 0,
+						 &pdo);
+				break;
+			case 1: /* TCPCI_MSG_SOP PD_CTRL_GET_SINK_CAP */
+				partner_send_msg(TCPCI_MSG_SOP,
+						 PD_DATA_SINK_CAP, 1, 0, &pdo);
+				break;
+			case 2: /* TCPCI_MSG_SOP_PRIME PD_DATA_VENDOR_DEF */
+				partner_send_msg(TCPCI_MSG_SOP_PRIME,
+						 PD_CTRL_NOT_SUPPORTED, 0, 0,
+						 NULL);
+				break;
+			case 3: /* TCPCI_MSG_SOP PD_DATA_VENDOR_DEF */
+				partner_send_msg(TCPCI_MSG_SOP,
+						 PD_CTRL_NOT_SUPPORTED, 0, 0,
+						 NULL);
+				break;
+			case 4: /* TCPCI_MSG_SOP PD_CTRL_GET_REVISION */
+				partner_send_msg(TCPCI_MSG_SOP,
+						 PD_CTRL_NOT_SUPPORTED, 0, 0,
+						 NULL);
+				break;
+			default:
+				TEST_ASSERT(0);
+				break;
+			}
+		} while (rv != EC_ERROR_TIMEOUT);
+	} else if (data_role == PD_ROLE_UFP) {
+		int vcs = 0;
+
+		possible[0].tx_type = TCPCI_MSG_SOP;
+		possible[0].ctrl_msg = PD_CTRL_GET_SINK_CAP;
+		possible[0].data_msg = 0;
+
+		possible[1].tx_type = TCPCI_MSG_SOP;
+		possible[1].ctrl_msg = PD_CTRL_DR_SWAP;
+		possible[1].data_msg = 0;
+
+		possible[2].tx_type = TCPCI_MSG_SOP;
+		possible[2].ctrl_msg = PD_CTRL_PR_SWAP;
+		possible[2].data_msg = 0;
+
+		possible[3].tx_type = TCPCI_MSG_SOP;
+		possible[3].ctrl_msg = PD_CTRL_VCONN_SWAP;
+		possible[3].data_msg = 0;
+
+		possible[4].tx_type = TCPCI_MSG_SOP;
+		possible[4].ctrl_msg = PD_CTRL_GET_REVISION;
+		possible[4].data_msg = 0;
+
+		do {
+			rv = verify_tcpci_possible_tx(possible, 5, &found_index,
+						      NULL, 0, NULL, -1);
+
+			TEST_NE(rv, EC_ERROR_UNKNOWN, "%d");
+			if (rv == EC_ERROR_TIMEOUT)
+				break;
+
+			mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
+			task_wait_event(10 * MSEC);
+
+			switch (found_index) {
+			case 0: /* TCPCI_MSG_SOP PD_CTRL_GET_SINK_CAP */
+				partner_send_msg(TCPCI_MSG_SOP,
+						 PD_DATA_SINK_CAP, 1, 0, &pdo);
+				break;
+			case 1: /* TCPCI_MSG_SOP PD_CTRL_DR_SWAP */
+				partner_send_msg(TCPCI_MSG_SOP, PD_CTRL_REJECT,
+						 0, 0, NULL);
+				break;
+			case 2: /* TCPCI_MSG_SOP PD_CTRL_PR_SWAP */
+				partner_send_msg(TCPCI_MSG_SOP, PD_CTRL_REJECT,
+						 0, 0, NULL);
+				break;
+			case 3: /* TCPCI_MSG_SOP PD_CTRL_VCONN_SWAP */
+				TEST_LT(vcs++, 4, "%d");
+				partner_send_msg(TCPCI_MSG_SOP, PD_CTRL_REJECT,
+						 0, 0, NULL);
+				break;
+			case 4: /* TCPCI_MSG_SOP PD_CTRL_GET_REVISION */
+				partner_send_msg(TCPCI_MSG_SOP,
+						 PD_CTRL_NOT_SUPPORTED, 0, 0,
+						 NULL);
+				break;
+			default:
+				TEST_ASSERT(0);
+				break;
+			}
+		} while (rv != EC_ERROR_TIMEOUT);
+	}
+	task_wait_event(1 * SECOND);
+	return EC_SUCCESS;
+}
diff --git a/test/usb_tcpmv2_tcpci.c b/test/usb_tcpmv2_tcpci.c
deleted file mode 100644
index 960cb9ff0f..0000000000
--- a/test/usb_tcpmv2_tcpci.c
+++ /dev/null
@@ -1,392 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "hooks.h"
-#include "mock/tcpci_i2c_mock.h"
-#include "mock/usb_mux_mock.h"
-#include "task.h"
-#include "tcpci.h"
-#include "test_util.h"
-#include "timer.h"
-#include "usb_mux.h"
-#include "usb_tc_sm.h"
-#include "usb_prl_sm.h"
-
-#define PORT0 0
-
-enum mock_cc_state {
-	MOCK_CC_SRC_OPEN = 0,
-	MOCK_CC_SNK_OPEN = 0,
-	MOCK_CC_SRC_RA = 1,
-	MOCK_CC_SNK_RP_DEF = 1,
-	MOCK_CC_SRC_RD = 2,
-	MOCK_CC_SNK_RP_1_5 = 2,
-	MOCK_CC_SNK_RP_3_0 = 3,
-};
-enum mock_connect_result {
-	MOCK_CC_WE_ARE_SRC = 0,
-	MOCK_CC_WE_ARE_SNK = 1,
-};
-
-__maybe_unused static void mock_set_cc(enum mock_connect_result cr,
-	enum mock_cc_state cc1, enum mock_cc_state cc2)
-{
-	mock_tcpci_set_reg(TCPC_REG_CC_STATUS,
-		TCPC_REG_CC_STATUS_SET(cr, cc1, cc2));
-}
-
-__maybe_unused static void mock_set_role(int drp, enum tcpc_rp_value rp,
-	enum tcpc_cc_pull cc1, enum tcpc_cc_pull cc2)
-{
-	mock_tcpci_set_reg(TCPC_REG_ROLE_CTRL,
-		TCPC_REG_ROLE_CTRL_SET(drp, rp, cc1, cc2));
-}
-
-static int mock_alert_count;
-
-__maybe_unused static void mock_set_alert(int alert)
-{
-	mock_tcpci_set_reg(TCPC_REG_ALERT, alert);
-	mock_alert_count = 1;
-	schedule_deferred_pd_interrupt(PORT0);
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	ccprints("mock_alert_count %d", mock_alert_count);
-	if (mock_alert_count > 0) {
-		mock_alert_count--;
-		return PD_STATUS_TCPC_ALERT_0;
-	}
-	return 0;
-}
-
-static int rx_id;
-
-const struct svdm_response svdm_rsp = {
-	.identity = NULL,
-	.svids = NULL,
-	.modes = NULL,
-};
-
-bool vboot_allow_usb_pd(void)
-{
-	return 1;
-}
-
-int pd_check_vconn_swap(int port)
-{
-	return 1;
-}
-
-void board_reset_pd_mcu(void) {}
-
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_HOST_TCPC,
-			.addr_flags = MOCK_TCPCI_I2C_ADDR_FLAGS,
-		},
-		.drv = &tcpci_tcpm_drv,
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-	},
-};
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.driver = &mock_usb_mux_driver,
-	}
-};
-
-__maybe_unused static int test_connect_as_nonpd_sink(void)
-{
-	task_wait_event(10 * SECOND);
-
-	/* Simulate a non-PD power supply being plugged in. */
-	mock_set_cc(MOCK_CC_WE_ARE_SNK, MOCK_CC_SNK_OPEN, MOCK_CC_SNK_RP_3_0);
-	mock_set_alert(TCPC_REG_ALERT_CC_STATUS);
-
-	task_wait_event(50 * MSEC);
-
-	mock_tcpci_set_reg(TCPC_REG_POWER_STATUS,
-			   TCPC_REG_POWER_STATUS_VBUS_PRES);
-	mock_set_alert(TCPC_REG_ALERT_POWER_STATUS);
-
-	task_wait_event(10 * SECOND);
-	TEST_EQ(tc_is_attached_snk(PORT0), true, "%d");
-
-	return EC_SUCCESS;
-}
-
-__maybe_unused static int test_startup_and_resume(void)
-{
-	/* Should be in low power mode before AP boots. */
-	TEST_EQ(mock_tcpci_get_reg(TCPC_REG_COMMAND),
-		TCPC_REG_COMMAND_I2CIDLE, "%d");
-	task_wait_event(10 * SECOND);
-
-	hook_notify(HOOK_CHIPSET_STARTUP);
-	task_wait_event(5 * MSEC);
-	hook_notify(HOOK_CHIPSET_RESUME);
-
-	task_wait_event(10 * SECOND);
-	/* Should be in low power mode and DRP auto-toggling with AP in S0. */
-	TEST_EQ((mock_tcpci_get_reg(TCPC_REG_ROLE_CTRL)
-		 & TCPC_REG_ROLE_CTRL_DRP_MASK),
-		TCPC_REG_ROLE_CTRL_DRP_MASK, "%d");
-	/* TODO: check previous command was TCPC_REG_COMMAND_LOOK4CONNECTION */
-	TEST_EQ(mock_tcpci_get_reg(TCPC_REG_COMMAND),
-		TCPC_REG_COMMAND_I2CIDLE, "%d");
-
-	return EC_SUCCESS;
-}
-
-
-__maybe_unused static int test_connect_as_pd3_source(void)
-{
-	uint32_t rdo = RDO_FIXED(1, 500, 500, 0);
-	uint32_t pdo = PDO_FIXED(5000, 500,
-				 PDO_FIXED_DUAL_ROLE |
-				 PDO_FIXED_DATA_SWAP |
-				 PDO_FIXED_COMM_CAP);
-
-	/* DRP auto-toggling with AP in S0, source enabled. */
-	TEST_EQ(test_startup_and_resume(), EC_SUCCESS, "%d");
-
-	/*
-	 * PROC.PD.E1. Bring-up procedure for DFP(Source) UUT:
-	 * a) The test starts in a disconnected state.
-	 */
-	mock_tcpci_set_reg(TCPC_REG_EXT_STATUS, TCPC_REG_EXT_STATUS_SAFE0V);
-	mock_set_alert(TCPC_REG_ALERT_EXT_STATUS);
-	task_wait_event(10 * SECOND);
-
-	/*
-	 * b) The Tester applies Rd and waits for Vbus for tNoResponse max.
-	 */
-	mock_set_cc(MOCK_CC_WE_ARE_SRC, MOCK_CC_SRC_OPEN, MOCK_CC_SRC_RD);
-	mock_set_alert(TCPC_REG_ALERT_CC_STATUS);
-
-	/*
-	 * c) The Tester waits for Source_Capabilities for tNoResponse max.
-	 */
-	TEST_EQ(verify_tcpci_transmit(TCPC_TX_SOP, 0, PD_DATA_SOURCE_CAP),
-		EC_SUCCESS, "%d");
-	/*
-	 * d) The Tester replies GoodCrc on reception of the
-	 * Source_Capabilities.
-	 */
-	mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
-	task_wait_event(10 * MSEC);
-	/*
-	 * e) The Tester requests 5V 0.5A.
-	 */
-	mock_tcpci_receive(PD_MSG_SOP,
-		PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK,
-			PD_ROLE_UFP, rx_id,
-			1, PD_REV30, 0),
-		&rdo);
-	rx_id++;
-	mock_set_alert(TCPC_REG_ALERT_RX_STATUS);
-	TEST_EQ(verify_tcpci_transmit(TCPC_TX_SOP, PD_CTRL_ACCEPT, 0),
-		EC_SUCCESS, "%d");
-	mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
-	/*
-	 * f) The Tester waits for PS_RDY for tPSSourceOn max.
-	 */
-	TEST_EQ(verify_tcpci_transmit(TCPC_TX_SOP, PD_CTRL_PS_RDY, 0),
-		EC_SUCCESS, "%d");
-	mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
-
-	/*
-	 * PROC.PD.E3. Wait to Start AMS for DFP(Source) UUT:
-	 * a) The Tester keeps monitoring the Rp value and if the UUT doesn't
-	 * set the value to SinkTXOK if it doesn't have anything to send in 1s,
-	 * the test fails. During this period, the Tester replies any message
-	 * sent from the UUT with a proper response.
-	 */
-	TEST_EQ(verify_tcpci_transmit(TCPC_TX_SOP_PRIME, 0, PD_DATA_VENDOR_DEF),
-		EC_SUCCESS, "%d");
-	mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
-	task_wait_event(10 * MSEC);
-	mock_tcpci_receive(PD_MSG_SOP_PRIME,
-		PD_HEADER(PD_CTRL_NOT_SUPPORTED, PD_PLUG_FROM_CABLE,
-			PD_ROLE_UFP, rx_id,
-			0, PD_REV30, 0),
-		NULL);
-	rx_id++;
-	mock_set_alert(TCPC_REG_ALERT_RX_STATUS);
-
-	TEST_EQ(verify_tcpci_transmit(TCPC_TX_SOP, 0, PD_DATA_VENDOR_DEF),
-		EC_SUCCESS, "%d");
-	mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
-	task_wait_event(10 * MSEC);
-	mock_tcpci_receive(PD_MSG_SOP,
-		PD_HEADER(PD_CTRL_NOT_SUPPORTED, PD_ROLE_SINK,
-			PD_ROLE_UFP, rx_id,
-			0, PD_REV30, 0),
-		NULL);
-	rx_id++;
-	mock_set_alert(TCPC_REG_ALERT_RX_STATUS);
-
-	TEST_EQ(verify_tcpci_transmit(TCPC_TX_SOP, PD_CTRL_GET_SOURCE_CAP, 0),
-		EC_SUCCESS, "%d");
-	mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
-	task_wait_event(10 * MSEC);
-	mock_tcpci_receive(PD_MSG_SOP,
-		PD_HEADER(PD_DATA_SOURCE_CAP, PD_ROLE_SINK,
-			PD_ROLE_UFP, rx_id,
-			1, PD_REV30, 0),
-		&pdo);
-	rx_id++;
-	mock_set_alert(TCPC_REG_ALERT_RX_STATUS);
-
-	task_wait_event(1 * SECOND);
-	TEST_EQ(tc_is_attached_src(PORT0), true, "%d");
-	TEST_EQ(TCPC_REG_ROLE_CTRL_RP(mock_tcpci_get_reg(TCPC_REG_ROLE_CTRL)),
-		SINK_TX_OK, "%d");
-
-	task_wait_event(10 * SECOND);
-	return EC_SUCCESS;
-}
-
-__maybe_unused static int test_retry_count_sop(void)
-{
-	/* DRP auto-toggling with AP in S0, source enabled. */
-	TEST_EQ(test_startup_and_resume(), EC_SUCCESS, "%d");
-
-	/*
-	 * The test starts in a disconnected state.
-	 */
-	mock_tcpci_set_reg(TCPC_REG_EXT_STATUS, TCPC_REG_EXT_STATUS_SAFE0V);
-	mock_set_alert(TCPC_REG_ALERT_EXT_STATUS);
-	task_wait_event(10 * SECOND);
-
-	/*
-	 * The Tester applies Rd and waits for Vbus for tNoResponse max.
-	 */
-	mock_set_cc(MOCK_CC_WE_ARE_SRC, MOCK_CC_SRC_OPEN, MOCK_CC_SRC_RD);
-	mock_set_alert(TCPC_REG_ALERT_CC_STATUS);
-
-	/*
-	 * The Tester waits for Source_Capabilities for tNoResponse max.
-	 *
-	 * Source Caps is SOP message which should be retried at TCPC layer
-	 */
-	TEST_EQ(verify_tcpci_tx_retry_count(TCPC_TX_SOP, CONFIG_PD_RETRY_COUNT),
-		EC_SUCCESS, "%d");
-	return EC_SUCCESS;
-}
-
-__maybe_unused static int test_retry_count_hard_reset(void)
-{
-	/* DRP auto-toggling with AP in S0, source enabled. */
-	TEST_EQ(test_startup_and_resume(), EC_SUCCESS, "%d");
-
-	/*
-	 * The test starts in a disconnected state.
-	 */
-	mock_tcpci_set_reg(TCPC_REG_EXT_STATUS, TCPC_REG_EXT_STATUS_SAFE0V);
-	mock_set_alert(TCPC_REG_ALERT_EXT_STATUS);
-	task_wait_event(10 * SECOND);
-
-	/*
-	 * The Tester applies Rd and waits for Vbus for tNoResponse max.
-	 */
-	mock_set_cc(MOCK_CC_WE_ARE_SRC, MOCK_CC_SRC_OPEN, MOCK_CC_SRC_RD);
-	mock_set_alert(TCPC_REG_ALERT_CC_STATUS);
-
-	/*
-	 * The Tester waits for Source_Capabilities for tNoResponse max.
-	 */
-	TEST_EQ(verify_tcpci_transmit(TCPC_TX_SOP, 0, PD_DATA_SOURCE_CAP),
-		EC_SUCCESS, "%d");
-	/*
-	 * The Tester replies GoodCrc on reception of the Source_Capabilities.
-	 */
-	mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
-	task_wait_event(10 * MSEC);
-
-	/*
-	 * Now that PRL is running since we are connected, we can send a hard
-	 * reset.
-	 */
-
-	/* Request that DUT send hard reset */
-	prl_execute_hard_reset(PORT0);
-
-	/* The retry count for hard resets should be 0 */
-	TEST_EQ(verify_tcpci_tx_retry_count(TCPC_TX_HARD_RESET, 0),
-		EC_SUCCESS, "%d");
-
-	return EC_SUCCESS;
-}
-
-__maybe_unused static int test_pd3_source_send_soft_reset(void)
-{
-	/*
-	 * TD.PD.SRC3.E26.Soft_Reset sent regardless of Rp value
-	 * a) Run PROC.PD.E1 Bring-up according to the UUT role.
-	 * b) The Tester waits until it can start an AMS (Run PROC.PD.E3)...
-	 */
-	TEST_EQ(test_connect_as_pd3_source(), EC_SUCCESS, "%d");
-
-	/*
-	 * ...and sends a Get_Source_Cap message to the UUT.
-	 */
-	mock_tcpci_receive(PD_MSG_SOP,
-		PD_HEADER(PD_CTRL_GET_SOURCE_CAP, PD_ROLE_SINK,
-			PD_ROLE_UFP, rx_id,
-			0, PD_REV30, 0),
-		NULL);
-	rx_id++;
-	mock_set_alert(TCPC_REG_ALERT_RX_STATUS);
-
-	/*
-	 * c) Upon receipt of the Source_Capabilities Message, the Tester
-	 * doesn’t reply with GoodCRC.
-	 */
-	TEST_EQ(verify_tcpci_transmit(TCPC_TX_SOP, 0, PD_DATA_SOURCE_CAP),
-		EC_SUCCESS, "%d");
-	mock_set_alert(TCPC_REG_ALERT_TX_FAILED);
-
-	/*
-	 * d) The Tester verifies that a Soft_Reset message is sent by the UUT
-	 * within tReceive max (1.1 ms) + tSoftReset max (15 ms).
-	 */
-	TEST_EQ(verify_tcpci_tx_timeout(
-			TCPC_TX_SOP, PD_CTRL_SOFT_RESET, 0, 15 * MSEC),
-		EC_SUCCESS, "%d");
-	mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
-
-	return EC_SUCCESS;
-}
-
-void before_test(void)
-{
-	rx_id = 0;
-
-	mock_usb_mux_reset();
-	mock_tcpci_reset();
-
-	/* Restart the PD task and let it settle */
-	task_set_event(TASK_ID_PD_C0, TASK_EVENT_RESET_DONE, 0);
-	task_wait_event(SECOND);
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_connect_as_nonpd_sink);
-	RUN_TEST(test_startup_and_resume);
-	RUN_TEST(test_connect_as_pd3_source);
-	RUN_TEST(test_retry_count_sop);
-	RUN_TEST(test_retry_count_hard_reset);
-	RUN_TEST(test_pd3_source_send_soft_reset);
-
-	test_print_result();
-}
diff --git a/test/usb_tcpmv2_tcpci.mocklist b/test/usb_tcpmv2_tcpci.mocklist
deleted file mode 100644
index 58a3541412..0000000000
--- a/test/usb_tcpmv2_tcpci.mocklist
+++ /dev/null
@@ -1,8 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
- #define CONFIG_TEST_MOCK_LIST  \
-	MOCK(USB_MUX)           \
-	MOCK(TCPCI_I2C)
diff --git a/test/usb_tcpmv2_tcpci.tasklist b/test/usb_tcpmv2_tcpci.tasklist
deleted file mode 100644
index 654e4eca2b..0000000000
--- a/test/usb_tcpmv2_tcpci.tasklist
+++ /dev/null
@@ -1,11 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TEST_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST \
-	TASK_TEST(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_TEST(PD_INT_C0, pd_interrupt_handler_task, 0, LARGER_TASK_STACK_SIZE)
diff --git a/test/usb_tcpmv2_td_pd_ll_e3.c b/test/usb_tcpmv2_td_pd_ll_e3.c
new file mode 100644
index 0000000000..8e1d46c15e
--- /dev/null
+++ b/test/usb_tcpmv2_td_pd_ll_e3.c
@@ -0,0 +1,81 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "mock/tcpci_i2c_mock.h"
+#include "task.h"
+#include "tcpm/tcpci.h"
+#include "test_util.h"
+#include "timer.h"
+#include "usb_tc_sm.h"
+#include "usb_tcpmv2_compliance.h"
+
+/*****************************************************************************
+ * TD.PD.LL.E3. Soft Reset Usage
+ *
+ * Description:
+ *	Check that the UUT will issue a Soft Reset after unsuccessful retries,
+ *	and that the link can be successfully recovered after that.
+ */
+static int td_pd_ll_e3(enum pd_data_role data_role)
+{
+	int retries;
+
+	partner_set_pd_rev(PD_REV20);
+
+	TEST_EQ(tcpci_startup(), EC_SUCCESS, "%d");
+
+	/*
+	 * a) Run PROC.PD.E1 Bring-up according to the UUT role.
+	 */
+	TEST_EQ(proc_pd_e1(data_role, INITIAL_AND_ALREADY_ATTACHED), EC_SUCCESS,
+		"%d");
+
+	/*
+	 * Make sure we are idle. Reject everything that is pending
+	 */
+	TEST_EQ(handle_attach_expected_msgs(data_role), EC_SUCCESS, "%d");
+
+	/*
+	 * b) Send a Get_Sink_Cap message to the UUT, wait for a reply
+	 *    and do not send GoodCrc for nRetryCount + 1 times
+	 *    (nRetryCount equals 3 since PD 2.1).
+	 */
+	partner_send_msg(TCPCI_MSG_SOP, PD_CTRL_GET_SINK_CAP, 0, 0, NULL);
+
+	retries = (partner_get_pd_rev() == PD_REV30) ? 2 : 3;
+	TEST_EQ(verify_tcpci_tx_retry_count(TCPCI_MSG_SOP, 0, PD_DATA_SINK_CAP,
+					    retries),
+		EC_SUCCESS, "%d");
+	mock_set_alert(TCPC_REG_ALERT_TX_FAILED);
+
+	/*
+	 * c) Check that the UUT issues a Soft Reset.
+	 */
+	TEST_EQ(verify_tcpci_transmit(TCPCI_MSG_SOP, PD_CTRL_SOFT_RESET, 0),
+		EC_SUCCESS, "%d");
+	mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
+	task_wait_event(10 * MSEC);
+
+	/*
+	 * d) Handle correctly the Soft Reset procedure.
+	 */
+	partner_send_msg(TCPCI_MSG_SOP, PD_CTRL_ACCEPT, 0, 0, NULL);
+
+	/*
+	 * e) Continue the bring-up procedure and check that the link is
+	 *    successfully established.
+	 */
+	TEST_EQ(proc_pd_e1(data_role, ALREADY_ATTACHED), EC_SUCCESS, "%d");
+
+	return EC_SUCCESS;
+}
+int test_td_pd_ll_e3_dfp(void)
+{
+	return td_pd_ll_e3(PD_ROLE_DFP);
+}
+int test_td_pd_ll_e3_ufp(void)
+{
+	return td_pd_ll_e3(PD_ROLE_UFP);
+}
diff --git a/test/usb_tcpmv2_td_pd_ll_e4.c b/test/usb_tcpmv2_td_pd_ll_e4.c
new file mode 100644
index 0000000000..fea5e3dc81
--- /dev/null
+++ b/test/usb_tcpmv2_td_pd_ll_e4.c
@@ -0,0 +1,90 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "mock/tcpci_i2c_mock.h"
+#include "task.h"
+#include "tcpm/tcpci.h"
+#include "test_util.h"
+#include "timer.h"
+#include "usb_tc_sm.h"
+#include "usb_tcpmv2_compliance.h"
+
+/*****************************************************************************
+ * TD.PD.LL.E4. Hard Reset Usage
+ *
+ * Description:
+ *	Check that the UUT will issue a Soft Reset after unsuccessful retries,
+ *	and that the link can be successfully recovered after that.
+ *	Check that the UUT will issue a Hard Reset if the Soft Reset fails,
+ *	and that the link can be successfully recovered after that.
+ */
+static int td_pd_ll_e4(enum pd_data_role data_role)
+{
+	int retries;
+
+	partner_set_pd_rev(PD_REV20);
+
+	TEST_EQ(tcpci_startup(), EC_SUCCESS, "%d");
+
+	/*
+	 * a) Run PROC.PD.E1 Bring-up according to the UUT role.
+	 */
+	TEST_EQ(proc_pd_e1(data_role, INITIAL_AND_ALREADY_ATTACHED), EC_SUCCESS,
+		"%d");
+
+	/*
+	 * Make sure we are idle. Reject everything that is pending
+	 */
+	TEST_EQ(handle_attach_expected_msgs(data_role), EC_SUCCESS, "%d");
+
+	/*
+	 * b) Send a Get_Sink_Cap message to the UUT, wait for a reply
+	 *    and do not send GoodCrc for nRetryCount + 1 times
+	 *    (nRetryCount equals 3 since PD 2.1).
+	 */
+	partner_send_msg(TCPCI_MSG_SOP, PD_CTRL_GET_SINK_CAP, 0, 0, NULL);
+
+	retries = 3;
+	TEST_EQ(verify_tcpci_tx_retry_count(TCPCI_MSG_SOP, 0, PD_DATA_SINK_CAP,
+					    retries),
+		EC_SUCCESS, "%d");
+	mock_set_alert(TCPC_REG_ALERT_TX_FAILED);
+
+	/*
+	 * c) Wait the nRetryCount + 1 (four) Soft Resets from the UUT and do
+	 *    not reply GoodCrc.
+	 */
+	retries = 3;
+	TEST_EQ(verify_tcpci_tx_retry_count(TCPCI_MSG_SOP, PD_CTRL_SOFT_RESET,
+					    0, retries),
+		EC_SUCCESS, "%d");
+	mock_set_alert(TCPC_REG_ALERT_TX_FAILED);
+	task_wait_event(1 * MSEC);
+
+	/*
+	 * d) Check that the UUT issues a Hard Reset.
+	 */
+	TEST_EQ(mock_tcpci_get_reg(TCPC_REG_TRANSMIT), TCPCI_MSG_TX_HARD_RESET,
+		"%d");
+	mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS | TCPC_REG_ALERT_TX_FAILED);
+	mock_tcpci_set_reg(TCPC_REG_TRANSMIT, 0);
+	task_wait_event(1 * MSEC);
+
+	/*
+	 * e) Do the bring-up procedure for Link tests and check that the link
+	 *    is successfully established.
+	 */
+	TEST_EQ(proc_pd_e1(data_role, ALREADY_ATTACHED), EC_SUCCESS, "%d");
+
+	return EC_SUCCESS;
+}
+int test_td_pd_ll_e4_dfp(void)
+{
+	return td_pd_ll_e4(PD_ROLE_DFP);
+}
+int test_td_pd_ll_e4_ufp(void)
+{
+	return td_pd_ll_e4(PD_ROLE_UFP);
+}
diff --git a/test/usb_tcpmv2_td_pd_ll_e5.c b/test/usb_tcpmv2_td_pd_ll_e5.c
new file mode 100644
index 0000000000..49b76fd44e
--- /dev/null
+++ b/test/usb_tcpmv2_td_pd_ll_e5.c
@@ -0,0 +1,58 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "mock/tcpci_i2c_mock.h"
+#include "task.h"
+#include "tcpm/tcpci.h"
+#include "test_util.h"
+#include "timer.h"
+#include "usb_tc_sm.h"
+#include "usb_tcpmv2_compliance.h"
+
+/*****************************************************************************
+ * TD.PD.LL.E5. Soft Reset
+ *
+ * Description:
+ *	Check that the UUT will correctly complete the Soft Reset procedure.
+ */
+static int td_pd_ll_e5(enum pd_data_role data_role)
+{
+	partner_set_pd_rev(PD_REV20);
+
+	TEST_EQ(tcpci_startup(), EC_SUCCESS, "%d");
+
+	/*
+	 * a) Run PROC.PD.E1 Bring-up according to the UUT role.
+	 */
+	TEST_EQ(proc_pd_e1(data_role, INITIAL_AND_ALREADY_ATTACHED), EC_SUCCESS,
+		"%d");
+
+	/*
+	 * Make sure we are idle. Reject everything that is pending
+	 */
+	TEST_EQ(handle_attach_expected_msgs(data_role), EC_SUCCESS, "%d");
+
+	/*
+	 * b) Initiate a Soft Reset and check that the procedure is completed
+	 *    successfully.
+	 */
+	partner_send_msg(TCPCI_MSG_SOP, PD_CTRL_SOFT_RESET, 0, 0, NULL);
+
+	TEST_EQ(verify_tcpci_transmit(TCPCI_MSG_SOP, PD_CTRL_ACCEPT, 0),
+		EC_SUCCESS, "%d");
+	mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
+
+	TEST_EQ(proc_pd_e1(data_role, ALREADY_ATTACHED), EC_SUCCESS, "%d");
+
+	return EC_SUCCESS;
+}
+int test_td_pd_ll_e5_dfp(void)
+{
+	return td_pd_ll_e5(PD_ROLE_DFP);
+}
+int test_td_pd_ll_e5_ufp(void)
+{
+	return td_pd_ll_e5(PD_ROLE_UFP);
+}
diff --git a/test/usb_tcpmv2_td_pd_other.c b/test/usb_tcpmv2_td_pd_other.c
new file mode 100644
index 0000000000..62e051a7a9
--- /dev/null
+++ b/test/usb_tcpmv2_td_pd_other.c
@@ -0,0 +1,107 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "mock/tcpci_i2c_mock.h"
+#include "task.h"
+#include "tcpm/tcpci.h"
+#include "test_util.h"
+#include "timer.h"
+#include "usb_prl_sm.h"
+#include "usb_tc_sm.h"
+#include "usb_tcpmv2_compliance.h"
+
+int test_connect_as_nonpd_sink(void)
+{
+	task_wait_event(10 * SECOND);
+
+	/* Simulate a non-PD power supply being plugged in. */
+	mock_set_cc(MOCK_CC_DUT_IS_SNK, MOCK_CC_SNK_OPEN, MOCK_CC_SNK_RP_3_0);
+	mock_set_alert(TCPC_REG_ALERT_CC_STATUS);
+
+	task_wait_event(50 * MSEC);
+
+	mock_tcpci_set_reg(TCPC_REG_POWER_STATUS,
+			   TCPC_REG_POWER_STATUS_VBUS_PRES);
+	mock_set_alert(TCPC_REG_ALERT_POWER_STATUS);
+
+	task_wait_event(10 * SECOND);
+	TEST_EQ(tc_is_attached_snk(PORT0), true, "%d");
+
+	return EC_SUCCESS;
+}
+
+int test_retry_count_sop(void)
+{
+	/* DRP auto-toggling with AP in S0, source enabled. */
+	TEST_EQ(tcpci_startup(), EC_SUCCESS, "%d");
+
+	/*
+	 * The test starts in a disconnected state.
+	 */
+	mock_tcpci_set_reg(TCPC_REG_EXT_STATUS, TCPC_REG_EXT_STATUS_SAFE0V);
+	mock_set_alert(TCPC_REG_ALERT_EXT_STATUS);
+	task_wait_event(10 * SECOND);
+
+	/*
+	 * The Tester applies Rd and waits for Vbus for tNoResponse max.
+	 */
+	mock_set_cc(MOCK_CC_DUT_IS_SRC, MOCK_CC_SRC_OPEN, MOCK_CC_SRC_RD);
+	mock_set_alert(TCPC_REG_ALERT_CC_STATUS);
+
+	/*
+	 * The Tester waits for Source_Capabilities for tNoResponse max.
+	 *
+	 * Source Caps is SOP message which should be retried at TCPC layer.
+	 * The retry count for PD3 should be 2.
+	 */
+	TEST_EQ(verify_tcpci_tx_retry_count(TCPCI_MSG_SOP, 0,
+					    PD_DATA_SOURCE_CAP, 2),
+		EC_SUCCESS, "%d");
+	return EC_SUCCESS;
+}
+
+int test_retry_count_hard_reset(void)
+{
+	/* DRP auto-toggling with AP in S0, source enabled. */
+	TEST_EQ(tcpci_startup(), EC_SUCCESS, "%d");
+
+	/*
+	 * The test starts in a disconnected state.
+	 */
+	mock_tcpci_set_reg(TCPC_REG_EXT_STATUS, TCPC_REG_EXT_STATUS_SAFE0V);
+	mock_set_alert(TCPC_REG_ALERT_EXT_STATUS);
+	task_wait_event(10 * SECOND);
+
+	/*
+	 * The Tester applies Rd and waits for Vbus for tNoResponse max.
+	 */
+	mock_set_cc(MOCK_CC_DUT_IS_SRC, MOCK_CC_SRC_OPEN, MOCK_CC_SRC_RD);
+	mock_set_alert(TCPC_REG_ALERT_CC_STATUS);
+
+	/*
+	 * The Tester waits for Source_Capabilities for tNoResponse max.
+	 */
+	TEST_EQ(verify_tcpci_transmit(TCPCI_MSG_SOP, 0, PD_DATA_SOURCE_CAP),
+		EC_SUCCESS, "%d");
+	/*
+	 * The Tester replies GoodCrc on reception of the Source_Capabilities.
+	 */
+	mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
+	task_wait_event(10 * MSEC);
+
+	/*
+	 * Now that PRL is running since we are connected, we can send a hard
+	 * reset.
+	 */
+
+	/* Request that DUT send hard reset */
+	prl_execute_hard_reset(PORT0);
+
+	/* The retry count for hard resets should be 0 */
+	TEST_EQ(verify_tcpci_tx_retry_count(TCPCI_MSG_TX_HARD_RESET, 0, 0, 0),
+		EC_SUCCESS, "%d");
+
+	return EC_SUCCESS;
+}
diff --git a/test/usb_tcpmv2_td_pd_snk3_e12.c b/test/usb_tcpmv2_td_pd_snk3_e12.c
new file mode 100644
index 0000000000..11aa51016e
--- /dev/null
+++ b/test/usb_tcpmv2_td_pd_snk3_e12.c
@@ -0,0 +1,55 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "mock/tcpci_i2c_mock.h"
+#include "task.h"
+#include "tcpm/tcpci.h"
+#include "test_util.h"
+#include "timer.h"
+#include "usb_tcpmv2_compliance.h"
+
+/*****************************************************************************
+ * TD.PD.SNK3.E12.Soft_Reset sent regardless of Rp value
+ *
+ * Description:
+ *	As Provider (DFP), the Tester forces the UUT to send Soft_Reset and
+ *	verifies Soft_Reset is sent regardless even though the Rp value is
+ *	SinkTxNG.
+ */
+int test_td_pd_snk3_e12(void)
+{
+	/*
+	 * TD.PD.SNK3.E12.Soft_Reset sent regardless of Rp value
+	 * a) Run PROC.PD.E1 Bring-up according to the UUT role.
+	 */
+	TEST_EQ(tcpci_startup(), EC_SUCCESS, "%d");
+	TEST_EQ(proc_pd_e1(PD_ROLE_UFP, INITIAL_AND_ALREADY_ATTACHED),
+		EC_SUCCESS, "%d");
+
+	/*
+	 * b) The Tester keeps the Rp value as SinkTXNG and sends a
+	 * Get_Sink_Cap message to the UUT.
+	 */
+	partner_send_msg(TCPCI_MSG_SOP, PD_CTRL_GET_SINK_CAP, 0, 0, NULL);
+
+	/*
+	 * c) Upon receipt of the Sink_Capabilities Message, the Tester doesn't
+	 * reply with GoodCRC.
+	 */
+	TEST_EQ(verify_tcpci_transmit(TCPCI_MSG_SOP, 0, PD_DATA_SINK_CAP),
+		EC_SUCCESS, "%d");
+	mock_set_alert(TCPC_REG_ALERT_TX_FAILED);
+
+	/*
+	 * d) The Tester verifies that a Soft_Reset message is sent by the UUT
+	 * within tReceive max + tSoftReset max
+	 */
+	TEST_EQ(verify_tcpci_tx_timeout(TCPCI_MSG_SOP, PD_CTRL_SOFT_RESET, 0,
+					16 * MSEC),
+		EC_SUCCESS, "%d");
+	mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
+
+	return EC_SUCCESS;
+}
diff --git a/test/usb_tcpmv2_td_pd_src3_e1.c b/test/usb_tcpmv2_td_pd_src3_e1.c
new file mode 100644
index 0000000000..9c79ea741a
--- /dev/null
+++ b/test/usb_tcpmv2_td_pd_src3_e1.c
@@ -0,0 +1,171 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "mock/tcpci_i2c_mock.h"
+#include "task.h"
+#include "tcpm/tcpci.h"
+#include "test_util.h"
+#include "timer.h"
+#include "usb_tc_sm.h"
+#include "usb_tcpmv2_compliance.h"
+
+#define BUFFER_SIZE 100
+
+#define HEADER_BYTE_OFFSET 1
+#define HEADER_BYTE_CNT 2
+#define PDO_BYTE_CNT 4
+
+enum pd_revision {
+	REVISION_1 = 0,
+	REVISION_2 = 1,
+	REVISION_3 = 2,
+	REVISION_RESERVED = 3
+};
+
+/*****************************************************************************
+ * TD.PD.SRC3.E1 Source Capabilities Fields Checks
+ *
+ * Description:
+ *	As Consumer (UFP), the Tester waits for a Source_Capabilities message
+ *	from the Provider (DFP,UUT) and verifies correct field values.
+ */
+int test_td_pd_src3_e1(void)
+{
+	int i;
+	int msg_len;
+	uint8_t data[BUFFER_SIZE];
+	uint16_t header;
+	uint16_t pd_cnt;
+	uint32_t pdo;
+	uint32_t type;
+	uint32_t last_fixed_voltage = 0;
+	uint32_t last_battery_voltage = 0;
+	uint32_t last_variable_voltage = 0;
+	uint32_t last_programmable_voltage = 0;
+
+	partner_set_pd_rev(PD_REV30);
+
+	TEST_EQ(tcpci_startup(), EC_SUCCESS, "%d");
+
+	/*
+	 * a) Run PROC.PD.E1 Bring-up For DFP UUT steps a and b.
+	 *
+	 * NOTE: Calling PROC.PD.E1 with INITIAL_ATTACH will stop just before
+	 * the PD_DATA_SOURCE_CAP is verified.  We need to stop the process
+	 * there to gather the actual message data.
+	 */
+	TEST_EQ(proc_pd_e1(PD_ROLE_DFP, INITIAL_ATTACH), EC_SUCCESS, "%d");
+
+	/*
+	 * b) Upon receipt of the Source_Capabilities message from the
+	 *    Provider, the Tester verifies:
+	 *    1. Number of Data Objects field equals the number of Src_PDOs in
+	 *       the message and is not 000b.
+	 *    2. Port Power Role field = 1b (Source)
+	 *    3. Specification Revision field = 10b (Rev 3.0)
+	 *    4. Port Data Role field = 1b (DFP)
+	 *    5. Message Type field = 00001b (Source Capabilities)
+	 *    6. Extended field = 0b
+	 */
+	TEST_EQ(verify_tcpci_tx_with_data(TCPCI_MSG_SOP, PD_DATA_SOURCE_CAP,
+					  data, sizeof(data), &msg_len, 0),
+		EC_SUCCESS, "%d");
+	TEST_GE(msg_len, HEADER_BYTE_CNT, "%d");
+
+	header = UINT16_FROM_BYTE_ARRAY_LE(data, HEADER_BYTE_OFFSET);
+	pd_cnt = PD_HEADER_CNT(header);
+	TEST_NE(pd_cnt, 0, "%d");
+	TEST_EQ(msg_len,
+		HEADER_BYTE_OFFSET + HEADER_BYTE_CNT + (pd_cnt * PDO_BYTE_CNT),
+		"%d");
+	TEST_EQ(PD_HEADER_PROLE(header), PD_ROLE_SOURCE, "%d");
+	TEST_EQ(PD_HEADER_REV(header), REVISION_3, "%d");
+	TEST_EQ(PD_HEADER_DROLE(header), PD_ROLE_DFP, "%d");
+	TEST_EQ(PD_HEADER_TYPE(header), PD_DATA_SOURCE_CAP, "%d");
+	TEST_EQ(PD_HEADER_EXT(header), 0, "%d");
+
+	/*
+	 * c) For the first PDO, the Tester verifies:
+	 *    1. Bits 31..30 (PDO type) are 00b (Fixed Supply).
+	 *    2. Voltage field = 100 (5 V)
+	 *    3. Bits 23..22 = 000b (Reserved)
+	 */
+	pdo = UINT32_FROM_BYTE_ARRAY_LE(data,
+					HEADER_BYTE_OFFSET + HEADER_BYTE_CNT);
+
+	type = pdo & PDO_TYPE_MASK;
+	TEST_EQ(type, PDO_TYPE_FIXED, "%d");
+
+	last_fixed_voltage = PDO_FIXED_VOLTAGE(pdo);
+	TEST_EQ(last_fixed_voltage, 5000, "%d");
+	TEST_EQ(pdo & GENMASK(23, 22), 0, "%d");
+
+	/*
+	 * d) For the other PDOs (if any), the Tester verifies:
+	 *    1. If Bits 31..30 are 00b
+	 *       -- Bits 29..22 are set to 0.
+	 *       NOTE: Bit 29 is Dual Role Power and looks correct for this
+	 *             to not be 0.  Bit 25 is Dual Role Data and looks
+	 *             correct for this to not be 0.
+	 *    2. If Bits 31..30 are 11b
+	 *       --  Bits 29..28 are 00b (Programmable Power Supply)
+	 *       --  Bits 26..25 are 00b (Reserved)
+	 *       --  Bit 16 is 0b (Reserved)
+	 *       --  Bit 7 is 0b (Reserved)
+	 *    3. PDOs are in the order of Fixed Supply Objects (if present),
+	 *       Battery Supply Objects (if present), Variable Supply Objects
+	 *       (if present) and then Programmable Power Supply Objects (if
+	 *       present).
+	 *    4. Fixed Supply Objects (if present) are in voltage order; lowest
+	 *       to highest.
+	 *    5. Battery Supply Objects (if present) are in Minimum Voltage
+	 *       order; lowest to highest.
+	 *    6. Variable Supply Objects (if present) are in Minimum Voltage
+	 *       order; lowest to highest.
+	 *    7. Programmable Power Supply Objects (if present) are in Maximum
+	 *       Voltage order; lowest to highest.
+	 */
+	for (i = 1; i < pd_cnt; ++i) {
+		int offset;
+		uint32_t voltage;
+
+		offset = HEADER_BYTE_OFFSET + HEADER_BYTE_CNT +
+			 (i * PDO_BYTE_CNT);
+		pdo = UINT32_FROM_BYTE_ARRAY_LE(data, offset);
+
+		type = pdo & PDO_TYPE_MASK;
+		if (type == PDO_TYPE_FIXED) {
+			TEST_EQ(pdo & (GENMASK(28, 26) | GENMASK(24, 22)), 0,
+				"%d");
+			TEST_EQ(last_battery_voltage, 0, "%d");
+			TEST_EQ(last_variable_voltage, 0, "%d");
+			TEST_EQ(last_programmable_voltage, 0, "%d");
+			voltage = PDO_FIXED_VOLTAGE(pdo);
+			TEST_GE(voltage, last_fixed_voltage, "%d");
+			last_fixed_voltage = voltage;
+		} else if (type == PDO_TYPE_BATTERY) {
+			TEST_EQ(last_variable_voltage, 0, "%d");
+			TEST_EQ(last_programmable_voltage, 0, "%d");
+			voltage = PDO_BATT_MIN_VOLTAGE(pdo);
+			TEST_GE(voltage, last_battery_voltage, "%d");
+			last_battery_voltage = voltage;
+		} else if (type == PDO_TYPE_VARIABLE) {
+			TEST_EQ(last_programmable_voltage, 0, "%d");
+			voltage = PDO_VAR_MIN_VOLTAGE(pdo);
+			TEST_GE(voltage, last_variable_voltage, "%d");
+			last_variable_voltage = voltage;
+		} else {
+			TEST_EQ(pdo & GENMASK(29, 28), 0, "%d");
+			TEST_EQ(pdo & GENMASK(26, 25), 0, "%d");
+			TEST_EQ(pdo & BIT(16), 0, "%d");
+			TEST_EQ(pdo & BIT(7), 0, "%d");
+			voltage = PDO_AUG_MAX_VOLTAGE(pdo);
+			TEST_GE(voltage, last_programmable_voltage, "%d");
+			last_programmable_voltage = voltage;
+		}
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/test/usb_tcpmv2_td_pd_src3_e26.c b/test/usb_tcpmv2_td_pd_src3_e26.c
new file mode 100644
index 0000000000..aef472884b
--- /dev/null
+++ b/test/usb_tcpmv2_td_pd_src3_e26.c
@@ -0,0 +1,56 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "mock/tcpci_i2c_mock.h"
+#include "task.h"
+#include "tcpm/tcpci.h"
+#include "test_util.h"
+#include "timer.h"
+#include "usb_tcpmv2_compliance.h"
+
+/*****************************************************************************
+ * TD.PD.SRC3.E26.Soft_Reset sent regardless of Rp value
+ *
+ * Description:
+ *	As Consumer (UFP), the Tester forces the UUT to send Soft_Reset and
+ *	verifies Soft_Reset is sent regardless of the Rp value is SinkTxOK or
+ *	SinkTxNG.
+ */
+int test_td_pd_src3_e26(void)
+{
+	/*
+	 * TD.PD.SRC3.E26.Soft_Reset sent regardless of Rp value
+	 * a) Run PROC.PD.E1 Bring-up according to the UUT role.
+	 * b) The Tester waits until it can start an AMS (Run PROC.PD.E3)...
+	 */
+	TEST_EQ(tcpci_startup(), EC_SUCCESS, "%d");
+	TEST_EQ(proc_pd_e1(PD_ROLE_DFP, INITIAL_AND_ALREADY_ATTACHED),
+		EC_SUCCESS, "%d");
+	TEST_EQ(proc_pd_e3(), EC_SUCCESS, "%d");
+
+	/*
+	 * ...and sends a Get_Source_Cap message to the UUT.
+	 */
+	partner_send_msg(TCPCI_MSG_SOP, PD_CTRL_GET_SOURCE_CAP, 0, 0, NULL);
+
+	/*
+	 * c) Upon receipt of the Source_Capabilities Message, the Tester
+	 * doesn’t reply with GoodCRC.
+	 */
+	TEST_EQ(verify_tcpci_transmit(TCPCI_MSG_SOP, 0, PD_DATA_SOURCE_CAP),
+		EC_SUCCESS, "%d");
+	mock_set_alert(TCPC_REG_ALERT_TX_FAILED);
+
+	/*
+	 * d) The Tester verifies that a Soft_Reset message is sent by the UUT
+	 * within tReceive max (1.1 ms) + tSoftReset max (15 ms).
+	 */
+	TEST_EQ(verify_tcpci_tx_timeout(TCPCI_MSG_SOP, PD_CTRL_SOFT_RESET, 0,
+					15 * MSEC),
+		EC_SUCCESS, "%d");
+	mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
+
+	return EC_SUCCESS;
+}
diff --git a/test/usb_tcpmv2_td_pd_src3_e32.c b/test/usb_tcpmv2_td_pd_src3_e32.c
new file mode 100644
index 0000000000..395a251b22
--- /dev/null
+++ b/test/usb_tcpmv2_td_pd_src3_e32.c
@@ -0,0 +1,208 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "mock/tcpci_i2c_mock.h"
+#include "task.h"
+#include "tcpm/tcpci.h"
+#include "test_util.h"
+#include "timer.h"
+#include "usb_tcpmv2_compliance.h"
+
+#define PD_T_CHUNK_RECEIVER_REQUEST_MAX (15 * MSEC)
+#define PD_T_CHUNK_SENDER_RSP_MAX (30 * MSEC)
+#define PD_T_CHUNKING_NOT_SUPPORTED_MIN (40 * MSEC)
+#define PD_T_CHUNKING_NOT_SUPPORTED_MAX (50 * MSEC)
+
+static void setup_chunk_msg(int chunk, char *data)
+{
+	int i;
+	int base_msg_byte = chunk * PD_MAX_EXTENDED_MSG_CHUNK_LEN;
+
+	*(uint16_t *)data = PD_EXT_HEADER(chunk, 0, PD_MAX_EXTENDED_MSG_LEN);
+
+	for (i = 0; i < PD_MAX_EXTENDED_MSG_CHUNK_LEN; ++i) {
+		int val = (i + base_msg_byte) % 256;
+
+		data[i + sizeof(uint16_t)] = val;
+	}
+}
+
+/*****************************************************************************
+ * TD.PD.SRC3.E32 ChunkSenderResponseTimer Timeout
+ *
+ * Description:
+ *	As Consumer (UFP), the Tester verifies that the UUT recovers correctly
+ *	after the Tester stops sending chunked messages in the middle.
+ */
+int test_td_pd_src3_e32(void)
+{
+	int chunk = 0;
+	int msg_len;
+	uint32_t header;
+	char data[PD_MAX_EXTENDED_MSG_CHUNK_LEN + sizeof(uint16_t)];
+
+	int found_index;
+	struct possible_tx possible[2];
+
+	uint64_t start_time;
+
+	/*
+	 * a) Run PROC.PD.E1 Bring-up according to the UUT role. The Tester
+	 * sets Unchunked Extended Messages Supported set to 0 in Request
+	 * message during this process.
+	 * b) The Tester waits until it can start an AMS (Run PROC.PD.E3)
+	 */
+	TEST_EQ(tcpci_startup(), EC_SUCCESS, "%d");
+	TEST_EQ(proc_pd_e1(PD_ROLE_DFP, INITIAL_AND_ALREADY_ATTACHED),
+		EC_SUCCESS, "%d");
+	TEST_EQ(proc_pd_e3(), EC_SUCCESS, "%d");
+
+	/*
+	 * ...and sends the first chunk of a chunked extended message
+	 * to the UUT, with Data Size set to 260 and Message Type set
+	 * to 11111b.  Bytes 0 to 259 of data block contain
+	 * incrementing values (mod 256) starting at 0x00.
+	 */
+	setup_chunk_msg(0, data);
+	partner_send_msg(TCPCI_MSG_SOP, 0x1F, 7, 1, (uint32_t *)data);
+	start_time = get_time().val;
+
+	/*
+	 * c) If a message is not received within tChunkingNotSupported
+	 * max (50ms), this test fails. The delay is messaged from the
+	 * time the last bit of the EOP of the chunk has been
+	 * transmitted until the first bit of the response Message
+	 * Preamble has been received.
+	 */
+	possible[0].tx_type = TCPCI_MSG_SOP;
+	possible[0].ctrl_msg = PD_CTRL_NOT_SUPPORTED;
+	possible[0].data_msg = 0;
+
+	possible[1].tx_type = TCPCI_MSG_SOP;
+	possible[1].ctrl_msg = 0;
+	possible[1].data_msg = 0x1F;
+
+	TEST_EQ(verify_tcpci_possible_tx(possible, 2, &found_index, data,
+					 sizeof(data), &msg_len,
+					 PD_T_CHUNKING_NOT_SUPPORTED_MAX),
+		EC_SUCCESS, "%d");
+	mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
+
+	/*
+	 * d) If the received message is Not_Supported, the Tester verifies
+	 * the message is received after tChunkingNotSupported min (40ms)
+	 * and stops here.
+	 */
+	if (found_index == 0) {
+		TEST_ASSERT((get_time().val - start_time) >=
+			    PD_T_CHUNKING_NOT_SUPPORTED_MIN);
+		return EC_SUCCESS;
+	}
+	TEST_EQ(found_index, 1, "%d");
+
+	/*
+	 * e) If the message is not received within
+	 * tChunkReceiverRequest max (15ms), the test fails.
+	 */
+	TEST_ASSERT((get_time().val - start_time) <=
+		    PD_T_CHUNK_RECEIVER_REQUEST_MAX);
+
+	while (chunk < 4) {
+		int next_chunk;
+
+		/*
+		 * f) Upon receipt of the message from the UUT to request for
+		 * the next chunk, the Tester sends the requested chunk to the
+		 * UUT.
+		 */
+		header = *(uint16_t *)&data[3];
+		next_chunk = PD_EXT_HEADER_CHUNK_NUM(header);
+		TEST_EQ(chunk + 1, next_chunk, "%d");
+		chunk = next_chunk;
+
+		setup_chunk_msg(chunk, data);
+		partner_send_msg(TCPCI_MSG_SOP, 0x1F, 7, 1, (uint32_t *)data);
+
+		TEST_EQ(verify_tcpci_tx_with_data(
+				TCPCI_MSG_SOP, 0x1F, data, sizeof(data),
+				&msg_len, PD_T_CHUNK_RECEIVER_REQUEST_MAX),
+			EC_SUCCESS, "%d");
+		mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
+
+		/*
+		 * g) Repeat f) until the Tester has finished sending 4 chunks
+		 * and intentionally does not send the 5th chunk to the UUT.
+		 */
+	}
+
+	/*
+	 * h) The Tester waits for tChunkSenderResponse max + 5 ms, waits until
+	 * it can start an AMS (Run PROC.PD.E3) and sends the first chunk to
+	 * the UUT.
+	 */
+	task_wait_event(PD_T_CHUNK_SENDER_RSP_MAX + (5 * MSEC));
+
+	setup_chunk_msg(0, data);
+	partner_send_msg(TCPCI_MSG_SOP, 0x1F, 7, 1, (uint32_t *)data);
+
+	/*
+	 * i) If a message is not received within tChunkReceiverRequest max,
+	 * the test fails.
+	 */
+	TEST_EQ(verify_tcpci_tx_with_data(TCPCI_MSG_SOP, 0x1F, data,
+					  sizeof(data), &msg_len,
+					  PD_T_CHUNK_RECEIVER_REQUEST_MAX),
+		EC_SUCCESS, "%d");
+	mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
+
+	/*
+	 * j) Upon receipt of the message, the Tester verifies the following:
+	 *	1. For Message Header
+	 *	  Extended = 1
+	 *	   Number of Data Objects = 1
+	 *	  Port Power Role field = 1b (Source)
+	 *	  Port Data Role field = 1b (DFP)
+	 *	  Specification Revision = 10b (Rev 3.0)
+	 *	  Message Type = 11111b
+	 */
+	TEST_EQ(msg_len, 7, "%d");
+	header = *(uint32_t *)&data[1];
+	TEST_EQ(PD_HEADER_EXT(header), 1, "%d");
+	TEST_EQ(PD_HEADER_CNT(header), 1, "%d");
+	TEST_EQ(PD_HEADER_PROLE(header), 1, "%d");
+	TEST_EQ(PD_HEADER_DROLE(header), 1, "%d");
+	TEST_EQ(PD_HEADER_REV(header), PD_REV30, "%d");
+	TEST_EQ(PD_HEADER_TYPE(header), 0x1F, "%d");
+
+	/*
+	 *	2. For Extended Message Header
+	 *	  Chunked = 1
+	 *	  Chunk Number = 1
+	 *	  Request Chunk = 1
+	 *	  Bit 9 = 0 (Reserved)
+	 *	  Data Size = 0
+	 */
+	header = *(uint16_t *)&data[3];
+	TEST_EQ(PD_EXT_HEADER_CHUNKED(header), 1, "%d");
+	TEST_EQ(PD_EXT_HEADER_CHUNK_NUM(header), 1, "%d");
+	TEST_EQ(PD_EXT_HEADER_REQ_CHUNK(header), 1, "%d");
+	TEST_EQ(header & BIT(9), 0, "%d");
+	TEST_EQ(PD_EXT_HEADER_DATA_SIZE(header), 0, "%d");
+
+	/*
+	 *	3. The total number of data bytes is consistent with the
+	 *	   Number of Data Objects field
+	 */
+	header = *(uint32_t *)&data[1];
+	TEST_EQ(msg_len - 3, PD_HEADER_CNT(header) * 4, "%d");
+
+	/*
+	 *	4. The last 2 bytes of the Data Object are 0
+	 */
+	TEST_EQ(data[5], 0, "%d");
+	TEST_EQ(data[6], 0, "%d");
+
+	return EC_SUCCESS;
+}
diff --git a/test/usb_tcpmv2_td_pd_src3_e7.c b/test/usb_tcpmv2_td_pd_src3_e7.c
new file mode 100644
index 0000000000..e94b017cc6
--- /dev/null
+++ b/test/usb_tcpmv2_td_pd_src3_e7.c
@@ -0,0 +1,128 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "driver/tcpm/tcpci.h"
+#include "mock/tcpci_i2c_mock.h"
+#include "task.h"
+#include "test_util.h"
+#include "timer.h"
+#include "usb_tc_sm.h"
+#include "usb_tcpmv2_compliance.h"
+
+#define BUFFER_SIZE 100
+
+#define HEADER_BYTE_OFFSET 1
+#define HEADER_BYTE_CNT 2
+#define SRC_CAP_EXT_NUM_BATTERY_OFFSET 22
+
+#define EXT_MSG_CHUNKED BIT(15)
+#define EXT_MSG_DATA_SIZE_1 1
+#define GBSDB_FIXED_BATTERY_0 (0 << 16)
+
+static int number_of_fixed_batteries(void)
+{
+	return CONFIG_NUM_FIXED_BATTERIES;
+}
+
+static int number_of_swappable_batteries(void)
+{
+	return 0;
+}
+
+/*****************************************************************************
+ * TD.PD.SRC3.E7 Battery Status sent timely
+ *
+ * Description:
+ *	As Consumer (UFP), the Tester verifies that the UUT replies
+ *	Get_Battery_Status message with a Battery_Status message timely.
+ */
+int test_td_pd_src3_e7(void)
+{
+	int msg_len;
+	uint8_t data[BUFFER_SIZE];
+	uint32_t ext_msg;
+
+	int found_index;
+	struct possible_tx possible[2];
+
+	TEST_EQ(tcpci_startup(), EC_SUCCESS, "%d");
+
+	/*
+	 * a) Run PROC.PD.E1 Bring-up according to the UUT role.
+	 */
+	TEST_EQ(proc_pd_e1(PD_ROLE_DFP, INITIAL_AND_ALREADY_ATTACHED),
+		EC_SUCCESS, "%d");
+
+	/*
+	 * b) The Tester waits until it can start an AMS (Run PROC.PD.E3) and
+	 *    sends a Get_Source_Cap_Extended message to the UUT.
+	 */
+	TEST_EQ(proc_pd_e3(), EC_SUCCESS, "%d");
+
+	partner_send_msg(TCPCI_MSG_SOP, PD_CTRL_GET_SOURCE_CAP_EXT, 0, 0, NULL);
+
+	/*
+	 * c) If a Not_Supported message is received, and Num_Fixed_Batteries
+	 *    and Num_Swappable_Battery_Slots in the VIF are 0, the test
+	 *    passes and stops here.
+	 */
+	possible[0].tx_type = TCPCI_MSG_SOP;
+	possible[0].ctrl_msg = PD_CTRL_NOT_SUPPORTED;
+	possible[0].data_msg = 0;
+
+	possible[1].tx_type = TCPCI_MSG_SOP;
+	possible[1].ctrl_msg = 0;
+	possible[1].data_msg = PD_DATA_SOURCE_CAP;
+
+	TEST_EQ(verify_tcpci_possible_tx(possible, 2, &found_index, data,
+					 sizeof(data), &msg_len, 0),
+		EC_SUCCESS, "%d");
+	if (found_index == 0) {
+		mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
+		task_wait_event(10 * MSEC);
+
+		if (number_of_fixed_batteries() == 0 &&
+		    number_of_swappable_batteries() == 0)
+			return EC_SUCCESS;
+	}
+	/*
+	 * d) If the Number of Batteries/Battery Slots field in the returned
+	 *    Source_Capabilities_Extended message is 0, the test passes and
+	 *    stops here.
+	 */
+	else {
+		TEST_EQ(found_index, 1, "%d");
+		mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
+		task_wait_event(10 * MSEC);
+
+		if (data[HEADER_BYTE_OFFSET + HEADER_BYTE_CNT +
+			 SRC_CAP_EXT_NUM_BATTERY_OFFSET] == 0)
+			return EC_SUCCESS;
+	}
+
+	/*
+	 * e) The Tester waits until it can start an AMS (Run PROC.PD.E3) and
+	 *    sends a Get_Battery_Status message to the UUT
+	 */
+	ext_msg = EXT_MSG_CHUNKED | EXT_MSG_DATA_SIZE_1 | GBSDB_FIXED_BATTERY_0;
+	partner_send_msg(TCPCI_MSG_SOP, PD_EXT_GET_BATTERY_STATUS, 1, 1,
+			 &ext_msg);
+
+	/*
+	 * f) If a Battery_Status message is not received within
+	 *    tReceiverResponse max, the test fails. This delay is measured
+	 *    from the time the last bit of Get_Battery_Status message EOP has
+	 *    been transmitted to the time the first bit of the Battery_Status
+	 *    message preamble has been received.
+	 */
+	TEST_EQ(verify_tcpci_tx_timeout(TCPCI_MSG_SOP, 0,
+					PD_DATA_BATTERY_STATUS, (15 * MSEC)),
+		EC_SUCCESS, "%d");
+	mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
+	task_wait_event(10 * MSEC);
+
+	return EC_SUCCESS;
+}
diff --git a/test/usb_tcpmv2_td_pd_src3_e8.c b/test/usb_tcpmv2_td_pd_src3_e8.c
new file mode 100644
index 0000000000..a19f6c8c82
--- /dev/null
+++ b/test/usb_tcpmv2_td_pd_src3_e8.c
@@ -0,0 +1,232 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "driver/tcpm/tcpci.h"
+#include "mock/tcpci_i2c_mock.h"
+#include "task.h"
+#include "test_util.h"
+#include "timer.h"
+#include "usb_tc_sm.h"
+#include "usb_tcpmv2_compliance.h"
+
+#define BUFFER_SIZE 100
+
+#define EXT_MSG_CHUNKED BIT(15)
+#define EXT_MSG_DATA_SIZE_1 1
+
+#define HEADER_BYTE_OFFSET 1
+#define HEADER_NUM_BYTES 2
+
+#define SCEDB_NUM_BATTERY_OFFSET 22
+#define SCEDB_NUM_BYTES 24
+
+#define BSDO_NUM_BYTES 4
+#define BSDO_INV_BATTERY_REF(bsdo) (((bsdo) >> 8) & 1)
+#define BSDO_BATTERY_PRESENT(bsdo) (((bsdo) >> 9) & 1)
+#define BSDO_BATTERY_CHRG_STS(bsdo) (((bsdo) >> 10) & 3)
+#define BSDO_BATTERY_INFO(bsdo) (((bsdo) >> 8) & 0xFF)
+
+static int number_of_fixed_batteries(void)
+{
+	return CONFIG_NUM_FIXED_BATTERIES;
+}
+
+static int number_of_swappable_batteries(void)
+{
+	return 0;
+}
+
+/*****************************************************************************
+ * TD.PD.SRC3.E8 Battery Status Field Checks
+ *
+ * Description:
+ *	As Consumer (UFP), the Tester sends a Get_Battery_Status message to
+ *	the UUT, verifies the UUT respond with a Battery_Status or
+ *	Not_Supported message. If a Battery_Status message is received, the
+ *	Tester verifies correct field values.
+ */
+int test_td_pd_src3_e8(void)
+{
+	int msg_len;
+	uint8_t data[BUFFER_SIZE];
+	uint32_t ext_msg;
+	int num_fixed_batteries;
+	int num_swappable_battery_slots;
+
+	int ref;
+	int found_index;
+	struct possible_tx possible[2];
+
+	TEST_EQ(tcpci_startup(), EC_SUCCESS, "%d");
+
+	/*
+	 * a) Run PROC.PD.E1 Bring-up according to the UUT role.
+	 */
+	TEST_EQ(proc_pd_e1(PD_ROLE_DFP, INITIAL_AND_ALREADY_ATTACHED),
+		EC_SUCCESS, "%d");
+
+	/*
+	 * b) The Tester waits until it can start an AMS (Run PROC.PD.E3) and
+	 *    sends a Get_Source_Cap_Extended message to the UUT.
+	 */
+	TEST_EQ(proc_pd_e3(), EC_SUCCESS, "%d");
+
+	partner_send_msg(TCPCI_MSG_SOP, PD_CTRL_GET_SOURCE_CAP_EXT, 0, 0, NULL);
+
+	/*
+	 * c) If a Source_Capabilities_Extended message is received, the
+	 *    Tester record the Number of Batteries/Battery Slots field.
+	 */
+	possible[0].tx_type = TCPCI_MSG_SOP;
+	possible[0].ctrl_msg = PD_CTRL_NOT_SUPPORTED;
+	possible[0].data_msg = 0;
+
+	possible[1].tx_type = TCPCI_MSG_SOP;
+	possible[1].ctrl_msg = 0;
+	possible[1].data_msg = PD_DATA_SOURCE_CAP;
+
+	TEST_EQ(verify_tcpci_possible_tx(possible, 2, &found_index, data,
+					 sizeof(data), &msg_len, 0),
+		EC_SUCCESS, "%d");
+	if (found_index == 1) {
+		mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
+		task_wait_event(10 * MSEC);
+
+		TEST_EQ(msg_len,
+			HEADER_BYTE_OFFSET + HEADER_NUM_BYTES + SCEDB_NUM_BYTES,
+			"%d");
+
+		num_fixed_batteries =
+			data[HEADER_BYTE_OFFSET + HEADER_NUM_BYTES +
+			     SCEDB_NUM_BATTERY_OFFSET] &
+			0x0F;
+		num_swappable_battery_slots =
+			(data[HEADER_BYTE_OFFSET + HEADER_NUM_BYTES +
+			      SCEDB_NUM_BATTERY_OFFSET] >>
+			 4) &
+			0x0F;
+	}
+	/*
+	 *    If a Not_Supported message is received, the Tester reads the
+	 *    Number of Batteries/Battery Slots field (combine
+	 *    Num_Fixed_Batteries and Num_Swappable_Battery_Slots) from the
+	 *    VIF.
+	 */
+	else {
+		TEST_EQ(found_index, 0, "%d");
+		mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
+		task_wait_event(10 * MSEC);
+
+		num_fixed_batteries = number_of_fixed_batteries();
+		num_swappable_battery_slots = number_of_swappable_batteries();
+	}
+
+	/*
+	 * d) The Tester waits until it can start an AMS (Run PROC.PD.E3) and
+	 *    sends a Get_Battery_Status message to the UUT, with Battery
+	 *    Status Ref set to 0 (step g includes doing d-f with Battery
+	 *    Status Ref set to 1 - 7).
+	 */
+	for (ref = 0; ref <= 7; ++ref) {
+		uint16_t header;
+		uint32_t bsdo;
+
+		ext_msg = EXT_MSG_CHUNKED | EXT_MSG_DATA_SIZE_1 | (ref << 16);
+		partner_send_msg(TCPCI_MSG_SOP, PD_EXT_GET_BATTERY_STATUS, 1, 1,
+				 &ext_msg);
+
+		/*
+		 * e) If a Battery_Status message is received, the Tester
+		 *    verifies:
+		 */
+		TEST_EQ(verify_tcpci_tx_with_data(TCPCI_MSG_SOP,
+						  PD_DATA_BATTERY_STATUS, data,
+						  sizeof(data), &msg_len, 0),
+			EC_SUCCESS, "%d");
+		mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
+		task_wait_event(10 * MSEC);
+		TEST_EQ(msg_len,
+			HEADER_BYTE_OFFSET + HEADER_NUM_BYTES + BSDO_NUM_BYTES,
+			"%d");
+
+		/*
+		 *    1. Number of Data Objects field = 001b
+		 */
+		header = UINT16_FROM_BYTE_ARRAY_LE(data, HEADER_BYTE_OFFSET);
+		TEST_EQ(PD_HEADER_CNT(header), 1, "%d");
+
+		/*
+		 *    2. Port Power Role field = 1b (Source)
+		 */
+		TEST_EQ(PD_HEADER_PROLE(header), 1, "%d");
+
+		/*
+		 *    3. Specification Revision field = 10b (Rev 3.0)
+		 */
+		TEST_EQ(PD_HEADER_REV(header), PD_REV30, "%d");
+
+		/*
+		 *    4. Port Data Role field = 1b (DFP)
+		 */
+		TEST_EQ(PD_HEADER_DROLE(header), PD_ROLE_DFP, "%d");
+
+		/*
+		 *    5. Extended = 0b
+		 */
+		TEST_EQ(PD_HEADER_EXT(header), 0, "%d");
+
+		/*
+		 *    6. Invalid Battery Reference field (Bit 0) of the
+		 *       Battery Info field in the BSDO matches with the
+		 *       recorded Number of Batteries/Battery Slots field
+		 *    7. If Battery Status Ref referred to a fixed battery
+		 *       and Invalid Battery Reference field is 0, the Battery
+		 *       is present field (Bit 1) shall be 1
+		 *    8. If Invalid Battery Reference field is 1, Battery is
+		 *       present field shall be 0
+		 */
+		bsdo = UINT32_FROM_BYTE_ARRAY_LE(
+			data, HEADER_BYTE_OFFSET + HEADER_NUM_BYTES);
+
+		/* FIXED BATTERY */
+		if (ref < 4) {
+			if (ref < num_fixed_batteries) {
+				TEST_EQ(BSDO_INV_BATTERY_REF(bsdo), 0, "%d");
+				TEST_EQ(BSDO_BATTERY_PRESENT(bsdo), 1, "%d");
+			} else {
+				TEST_EQ(BSDO_INV_BATTERY_REF(bsdo), 1, "%d");
+				TEST_EQ(BSDO_BATTERY_PRESENT(bsdo), 0, "%d");
+			}
+		}
+		/* BATTERY SLOT */
+		else {
+			if ((ref - 4) < num_swappable_battery_slots) {
+				TEST_EQ(BSDO_INV_BATTERY_REF(bsdo), 0, "%d");
+			} else {
+				TEST_EQ(BSDO_INV_BATTERY_REF(bsdo), 1, "%d");
+				TEST_EQ(BSDO_BATTERY_PRESENT(bsdo), 0, "%d");
+			}
+		}
+
+		/*
+		 *    9. If Battery is present, Battery charging status
+		 *       (Bits 3..2) of Battery Info field is not 11b
+		 *   10. If Battery is not present, Bits 3..2 of Battery Info
+		 *       field is 00b
+		 *   11. Bits 7..4 of Battery Info field are 0
+		 *   12. Bits 7..0 of the BSDO are 0
+		 */
+		if (BSDO_BATTERY_PRESENT(bsdo))
+			TEST_NE(BSDO_BATTERY_CHRG_STS(bsdo), 3, "%d");
+		else
+			TEST_EQ(BSDO_BATTERY_CHRG_STS(bsdo), 0, "%d");
+
+		TEST_EQ(BSDO_BATTERY_INFO(bsdo) & GENMASK(7, 4), 0, "%d");
+		TEST_EQ(bsdo & GENMASK(7, 0), 0, "%d");
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/test/usb_tcpmv2_td_pd_src3_e9.c b/test/usb_tcpmv2_td_pd_src3_e9.c
new file mode 100644
index 0000000000..833a9c056f
--- /dev/null
+++ b/test/usb_tcpmv2_td_pd_src3_e9.c
@@ -0,0 +1,213 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "driver/tcpm/tcpci.h"
+#include "mock/tcpci_i2c_mock.h"
+#include "task.h"
+#include "test_util.h"
+#include "timer.h"
+#include "usb_tc_sm.h"
+#include "usb_tcpmv2_compliance.h"
+
+#define BUFFER_SIZE 100
+
+#define EXT_MSG_CHUNKED BIT(15)
+#define EXT_MSG_DATA_SIZE_1 1
+
+#define HEADER_BYTE_OFFSET 1
+#define HEADER_NUM_BYTES 2
+
+#define SCEDB_NUM_BATTERY_OFFSET 22
+#define SCEDB_NUM_BYTES 24
+
+#define BSDO_INV_BATTERY_REF(bsdo) (((bsdo) >> 8) & 1)
+#define BSDO_BATTERY_INFO(bsdo) (((bsdo) >> 8) & 0xFF)
+
+static int number_of_fixed_batteries(void)
+{
+	return CONFIG_NUM_FIXED_BATTERIES;
+}
+
+static int number_of_swappable_batteries(void)
+{
+	return 0;
+}
+
+/*****************************************************************************
+ * TD.PD.SRC3.E9 Battery Status Fields Checks - Invalid Battery reference
+ *
+ * Description:
+ *	As Consumer (UFP), the Tester sends a Get_Battery_Status message with
+ *	an invalid battery reference to the UUT, waits for a Battery_Status
+ *	message from the Provider (DFP, UUT) and verifies correct field values.
+ */
+int test_td_pd_src3_e9(void)
+{
+	int msg_len;
+	uint8_t data[BUFFER_SIZE];
+	uint32_t ext_msg;
+	int num_fixed_batteries;
+	int num_swappable_battery_slots;
+
+	int ref;
+	int found_index;
+	struct possible_tx possible[2];
+
+	TEST_EQ(tcpci_startup(), EC_SUCCESS, "%d");
+
+	/*
+	 * a) Run PROC.PD.E1 Bring-up according to the UUT role.
+	 */
+	TEST_EQ(proc_pd_e1(PD_ROLE_DFP, INITIAL_AND_ALREADY_ATTACHED),
+		EC_SUCCESS, "%d");
+
+	/*
+	 * b) The Tester waits until it can start an AMS (Run PROC.PD.E3) and
+	 *    sends a Get_Source_Cap_Extended message to the UUT.
+	 */
+	TEST_EQ(proc_pd_e3(), EC_SUCCESS, "%d");
+
+	partner_send_msg(TCPCI_MSG_SOP, PD_CTRL_GET_SOURCE_CAP_EXT, 0, 0, NULL);
+
+	/*
+	 * c) If a Source_Capabilities_Extended message is received, the
+	 *    Tester record the Number of Batteries/Battery Slots field.
+	 */
+	possible[0].tx_type = TCPCI_MSG_SOP;
+	possible[0].ctrl_msg = PD_CTRL_NOT_SUPPORTED;
+	possible[0].data_msg = 0;
+
+	possible[1].tx_type = TCPCI_MSG_SOP;
+	possible[1].ctrl_msg = 0;
+	possible[1].data_msg = PD_DATA_SOURCE_CAP;
+
+	TEST_EQ(verify_tcpci_possible_tx(possible, 2, &found_index, data,
+					 sizeof(data), &msg_len, 0),
+		EC_SUCCESS, "%d");
+	if (found_index == 1) {
+		mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
+		task_wait_event(10 * MSEC);
+
+		TEST_EQ(msg_len,
+			HEADER_BYTE_OFFSET + HEADER_NUM_BYTES + SCEDB_NUM_BYTES,
+			"%d");
+
+		num_fixed_batteries =
+			data[HEADER_BYTE_OFFSET + HEADER_NUM_BYTES +
+			     SCEDB_NUM_BATTERY_OFFSET] &
+			0x0F;
+		num_swappable_battery_slots =
+			(data[HEADER_BYTE_OFFSET + HEADER_NUM_BYTES +
+			      SCEDB_NUM_BATTERY_OFFSET] >>
+			 4) &
+			0x0F;
+	}
+	/*
+	 *    If a Not_Supported message is received, the Tester reads the
+	 *    Number of Batteries/Battery Slots field (combine
+	 *    Num_Fixed_Batteries and Num_Swappable_Battery_Slots) from the
+	 *    VIF.
+	 */
+	else {
+		TEST_EQ(found_index, 0, "%d");
+		mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
+		task_wait_event(10 * MSEC);
+
+		num_fixed_batteries = number_of_fixed_batteries();
+		num_swappable_battery_slots = number_of_swappable_batteries();
+	}
+
+	/*
+	 * d) The Tester waits until it can start an AMS (Run PROC.PD.E3) and
+	 *    sends a Get_Battery_Status message, with Battery Status Ref set
+	 *    to 8, to the UUT.
+	 */
+	ref = 8;
+	ext_msg = EXT_MSG_CHUNKED | EXT_MSG_DATA_SIZE_1 | (ref << 16);
+	partner_send_msg(TCPCI_MSG_SOP, PD_EXT_GET_BATTERY_STATUS, 1, 1,
+			 &ext_msg);
+
+	/*
+	 * e) If a Not_Supported message is received, and
+	 *    1. If the recorded Number of Batteries/Battery Slots field is 0,
+	 *       the test passes and stops here.
+	 *    2. If the recorded Number of Batteries/Battery Slots field is
+	 *       not 0, the test fails.
+	 */
+	possible[0].tx_type = TCPCI_MSG_SOP;
+	possible[0].ctrl_msg = PD_CTRL_NOT_SUPPORTED;
+	possible[0].data_msg = 0;
+
+	possible[1].tx_type = TCPCI_MSG_SOP;
+	possible[1].ctrl_msg = 0;
+	possible[1].data_msg = PD_DATA_BATTERY_STATUS;
+
+	TEST_EQ(verify_tcpci_possible_tx(possible, 2, &found_index, data,
+					 sizeof(data), &msg_len, 0),
+		EC_SUCCESS, "%d");
+	if (found_index == 0) {
+		mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
+		task_wait_event(10 * MSEC);
+
+		TEST_EQ(num_fixed_batteries, 0, "%d");
+		TEST_EQ(num_swappable_battery_slots, 0, "%d");
+		return EC_SUCCESS;
+	}
+	/*
+	 * f) Upon receipt of the Battery_Status message, the Tester verifies:
+	 */
+	else {
+		uint16_t header;
+		uint32_t bsdo;
+
+		TEST_EQ(found_index, 1, "%d");
+		mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
+		task_wait_event(10 * MSEC);
+
+		/*
+		 *    1. Number of Data Objects field = 001b
+		 */
+		header = UINT16_FROM_BYTE_ARRAY_LE(data, HEADER_BYTE_OFFSET);
+		TEST_EQ(PD_HEADER_CNT(header), 1, "%d");
+
+		/*
+		 *    2. Port Power Role field = 1b (Source)
+		 */
+		TEST_EQ(PD_HEADER_PROLE(header), 1, "%d");
+
+		/*
+		 *    3. Specification Revision field = 10b (Rev 3.0)
+		 */
+		TEST_EQ(PD_HEADER_REV(header), PD_REV30, "%d");
+
+		/*
+		 *    4. Port Data Role field = 1b (DFP)
+		 */
+		TEST_EQ(PD_HEADER_DROLE(header), PD_ROLE_DFP, "%d");
+
+		/*
+		 *    5. Extended = 0b
+		 */
+		TEST_EQ(PD_HEADER_EXT(header), 0, "%d");
+
+		/*
+		 *    6. Invalid Battery Reference field (Bit 0) of the
+		 *       Battery Info field in the BSDO is 1
+		 */
+		bsdo = UINT32_FROM_BYTE_ARRAY_LE(
+			data, HEADER_BYTE_OFFSET + HEADER_NUM_BYTES);
+		TEST_EQ(BSDO_INV_BATTERY_REF(bsdo), 1, "%d");
+
+		/*
+		 *    7. Bits 7..1 of Battery Info field in the BSDO are 0
+		 *    8. Bits 7..0 of the BSDO are 0
+		 */
+		TEST_EQ(BSDO_BATTERY_INFO(bsdo) & GENMASK(7, 1), 0, "%d");
+		TEST_EQ(bsdo & GENMASK(7, 0), 0, "%d");
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/test/usb_tcpmv2_td_pd_src_e1.c b/test/usb_tcpmv2_td_pd_src_e1.c
new file mode 100644
index 0000000000..10166c4b65
--- /dev/null
+++ b/test/usb_tcpmv2_td_pd_src_e1.c
@@ -0,0 +1,46 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "mock/tcpci_i2c_mock.h"
+#include "task.h"
+#include "tcpm/tcpci.h"
+#include "test_util.h"
+#include "timer.h"
+#include "usb_tc_sm.h"
+#include "usb_tcpmv2_compliance.h"
+
+/*****************************************************************************
+ * TD.PD.SRC.E1 Source Capabilities sent timely
+ *
+ * Description:
+ *	As Consumer (UFP), the Tester verifies a Source Capabilities message
+ *	from the Provider (DFP, UUT) is received timely
+ */
+int test_td_pd_src_e1(void)
+{
+	partner_set_pd_rev(PD_REV20);
+
+	TEST_EQ(tcpci_startup(), EC_SUCCESS, "%d");
+
+	/*
+	 * a) Run PROC.PD.E1 Bring-up according to the UUT role.
+	 *
+	 * NOTE: Calling PROC.PD.E1 with INITIAL_ATTACH will stop just before
+	 * the PD_DATA_SOURCE_CAP is verified.  We need to stop the process
+	 * there to use the timeout verify.
+	 */
+	TEST_EQ(proc_pd_e1(PD_ROLE_DFP, INITIAL_ATTACH), EC_SUCCESS, "%d");
+
+	/*
+	 * b) The test fails if the first bit of a Source Capabilities message
+	 *    is not received from the Provider within 250 ms (tFirstSourceCap
+	 *    max) after VBus present.
+	 */
+	TEST_EQ(verify_tcpci_tx_timeout(TCPCI_MSG_SOP, 0, PD_DATA_SOURCE_CAP,
+					250 * MSEC),
+		EC_SUCCESS, "%d");
+
+	return EC_SUCCESS;
+}
diff --git a/test/usb_tcpmv2_td_pd_src_e2.c b/test/usb_tcpmv2_td_pd_src_e2.c
new file mode 100644
index 0000000000..fbe3e4bce7
--- /dev/null
+++ b/test/usb_tcpmv2_td_pd_src_e2.c
@@ -0,0 +1,158 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "mock/tcpci_i2c_mock.h"
+#include "task.h"
+#include "tcpm/tcpci.h"
+#include "test_util.h"
+#include "timer.h"
+#include "usb_tc_sm.h"
+#include "usb_tcpmv2_compliance.h"
+
+#define BUFFER_SIZE 100
+
+#define HEADER_BYTE_OFFSET 1
+#define HEADER_BYTE_CNT 2
+#define PDO_BYTE_CNT 4
+
+enum pd_revision {
+	REVISION_1 = 0,
+	REVISION_2 = 1,
+	REVISION_3 = 2,
+	REVISION_RESERVED = 3
+};
+
+/*****************************************************************************
+ * TD.PD.SRC.E2 Source Capabilities Fields Checks
+ *
+ * Description:
+ *	As Consumer (UFP), the Tester waits for a Source Capabilities message
+ *	from the Provider (DFP,UUT) and verifies correct field values.
+ */
+int test_td_pd_src_e2(void)
+{
+	int i;
+	int msg_len;
+	uint8_t data[BUFFER_SIZE];
+	uint16_t header;
+	uint16_t revision;
+	uint16_t pd_cnt;
+	uint32_t pdo;
+	uint32_t type;
+	uint32_t last_fixed_voltage = 0;
+	uint32_t last_battery_voltage = 0;
+	uint32_t last_variable_voltage = 0;
+
+	partner_set_pd_rev(PD_REV20);
+
+	TEST_EQ(tcpci_startup(), EC_SUCCESS, "%d");
+
+	/*
+	 * a) Run PROC.PD.E1 Bring-up according to the UUT role.
+	 *
+	 * NOTE: Calling PROC.PD.E1 with INITIAL_ATTACH will stop just before
+	 * the PD_DATA_SOURCE_CAP is verified.  We need to stop the process
+	 * there to gather the actual message data.
+	 */
+	TEST_EQ(proc_pd_e1(PD_ROLE_DFP, INITIAL_ATTACH), EC_SUCCESS, "%d");
+
+	/*
+	 * b) Upon receipt of the Source Capabilities message from the
+	 *    Provider, if the Specification Revision field is 10b
+	 *    (Rev 3.0), the test passes and stops here,
+	 */
+	TEST_EQ(verify_tcpci_tx_with_data(TCPCI_MSG_SOP, PD_DATA_SOURCE_CAP,
+					  data, sizeof(data), &msg_len, 0),
+		EC_SUCCESS, "%d");
+	TEST_GE(msg_len, HEADER_BYTE_CNT, "%d");
+
+	header = UINT16_FROM_BYTE_ARRAY_LE(data, HEADER_BYTE_OFFSET);
+	revision = PD_HEADER_REV(header);
+	if (revision == REVISION_3)
+		return EC_SUCCESS;
+
+	/*
+	 *    otherwise the Tester verifies:
+	 *    1. Number of Data Objects field equals the number of Src_PDOs
+	 *       in the message and is not 000b.
+	 *    2. Port Power Role field = 1b (Source)
+	 *    3. Specification Revision field = 01b (Rev 2.0)
+	 *    4. Port Data Role field = 1b (DFP)
+	 *    5. Message Type field = 0001b (Source Capabilities)
+	 *    6. Bit 15 = 0b (Reserved)
+	 *    7. Bit 4 = 0b (Reserved)
+	 */
+	pd_cnt = PD_HEADER_CNT(header);
+	TEST_NE(pd_cnt, 0, "%d");
+	TEST_EQ(msg_len, HEADER_BYTE_CNT + (pd_cnt * PDO_BYTE_CNT) + 1, "%d");
+	TEST_EQ(PD_HEADER_PROLE(header), PD_ROLE_SOURCE, "%d");
+	TEST_EQ(revision, REVISION_2, "%d");
+	TEST_EQ(PD_HEADER_DROLE(header), PD_ROLE_DFP, "%d");
+	TEST_EQ(PD_HEADER_TYPE(header), PD_DATA_SOURCE_CAP, "%d");
+	TEST_EQ(header & (BIT(4) | BIT(15)), 0, "%d");
+
+	/*
+	 * c) For the first PDO, the Tester verifies:
+	 *    1. Bits 31..30 (PDO type) are 00b (Fixed Supply).
+	 *    2. Voltage field = 100 (5 V)
+	 *    3. Bits 24..22 = 000b (Reserved)
+	 */
+	pdo = UINT32_FROM_BYTE_ARRAY_LE(data,
+					HEADER_BYTE_OFFSET + HEADER_BYTE_CNT);
+
+	type = pdo & PDO_TYPE_MASK;
+	TEST_EQ(type, PDO_TYPE_FIXED, "%d");
+
+	last_fixed_voltage = PDO_FIXED_VOLTAGE(pdo);
+	TEST_EQ(last_fixed_voltage, 5000, "%d");
+	TEST_EQ(pdo & GENMASK(24, 22), 0, "%d");
+
+	/*
+	 * d) For the other PDOs (if any), the Tester verifies:
+	 *    1. Bits 31..30 (PDO type) are 00b (Fixed Supply), 01b (Battery),
+	 *       or 10b (Variable Supply).
+	 *    2. If Bits 31..30 are 00b, Bits 29..22 are set to 0.
+	 *    3. PDOs are in the order of Fixed Supply Objects (if present),
+	 *       Battery Supply Objects (if present) and then Variable Supply
+	 *       Objects (if present).
+	 *    4. Fixed Supply Objects (if present) are in voltage order; lowest
+	 *       to highest.
+	 *    5. Battery Supply Objects (if present) are in Minimum Voltage
+	 *       order; lowest to highest.
+	 *    6. Variable Supply Objects (if present) are in Minimum Voltage
+	 *       order; lowest to highest.
+	 */
+	for (i = 1; i < pd_cnt; ++i) {
+		int offset;
+		uint32_t voltage;
+
+		offset = HEADER_BYTE_OFFSET + HEADER_BYTE_CNT +
+			 (i * PDO_BYTE_CNT);
+		pdo = UINT32_FROM_BYTE_ARRAY_LE(data, offset);
+
+		type = pdo & PDO_TYPE_MASK;
+		TEST_NE(type, PDO_TYPE_AUGMENTED, "%d");
+
+		if (type == PDO_TYPE_FIXED) {
+			TEST_EQ(pdo & GENMASK(29, 22), 0, "%d");
+			TEST_EQ(last_battery_voltage, 0, "%d");
+			TEST_EQ(last_variable_voltage, 0, "%d");
+			voltage = PDO_FIXED_VOLTAGE(pdo);
+			TEST_GE(voltage, last_fixed_voltage, "%d");
+			last_fixed_voltage = voltage;
+		} else if (type == PDO_TYPE_BATTERY) {
+			TEST_EQ(last_variable_voltage, 0, "%d");
+			voltage = PDO_BATT_MIN_VOLTAGE(pdo);
+			TEST_GE(voltage, last_battery_voltage, "%d");
+			last_battery_voltage = voltage;
+		} else {
+			voltage = PDO_VAR_MIN_VOLTAGE(pdo);
+			TEST_GE(voltage, last_variable_voltage, "%d");
+			last_variable_voltage = voltage;
+		}
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/test/usb_tcpmv2_td_pd_src_e5.c b/test/usb_tcpmv2_td_pd_src_e5.c
new file mode 100644
index 0000000000..bc391104ab
--- /dev/null
+++ b/test/usb_tcpmv2_td_pd_src_e5.c
@@ -0,0 +1,85 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "mock/tcpci_i2c_mock.h"
+#include "task.h"
+#include "tcpm/tcpci.h"
+#include "test_util.h"
+#include "timer.h"
+#include "usb_tc_sm.h"
+#include "usb_tcpmv2_compliance.h"
+
+/*****************************************************************************
+ * TD.PD.SRC.E5 SenderResponseTimer Timeout - Request
+ *
+ * Description:
+ *	As Consumer (UFP), the Tester intentionally does not send the Request
+ *	message, which is intended to cause a SenderResponseTimer timeout on
+ *	the Provider (DFP, UUT). The Tester verifies correct implementation
+ *	of this timer
+ */
+int test_td_pd_src_e5(void)
+{
+	uint64_t end_time;
+
+	partner_set_pd_rev(PD_REV20);
+
+	TEST_EQ(tcpci_startup(), EC_SUCCESS, "%d");
+
+	/*
+	 * a) Run PROC.PD.E1 Bring-up according to the UUT role.
+	 *
+	 * NOTE: Calling PROC.PD.E1 with INITIAL_ATTACH will stop just before
+	 * the PD_DATA_SOURCE_CAP is verified.  We need to stop the process
+	 * there to stop the REQUEST message.
+	 */
+	TEST_EQ(proc_pd_e1(PD_ROLE_DFP, INITIAL_ATTACH), EC_SUCCESS, "%d");
+
+	/*
+	 * b) Upon receipt of the Source Capabilities message from the
+	 *    Provider, the Tester replies with a GoodCRC message.
+	 */
+	TEST_EQ(verify_tcpci_transmit(TCPCI_MSG_SOP, 0, PD_DATA_SOURCE_CAP),
+		EC_SUCCESS, "%d");
+	mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
+
+	/* Save time GoodCRC was sent */
+	end_time = get_time().val;
+
+	/*
+	 * c) The Tester intentionally does not send a Request message and
+	 *    waits for a Hard Reset.
+	 */
+
+	/*
+	 * d) If a Hard Reset is not detected within 30 ms from the time the
+	 *    last bit of the GoodCRC message EOP has been sent, the test
+	 *    fails.
+	 * e) If a Hard Reset is detected before 24 ms from the time the
+	 *    last bit of the GoodCRC message EOP has been sent, the test
+	 *    fails.
+	 */
+	end_time += 24 * MSEC;
+	while (get_time().val < end_time) {
+		TEST_NE(mock_tcpci_get_reg(TCPC_REG_TRANSMIT),
+			TCPCI_MSG_TX_HARD_RESET, "%d");
+		task_wait_event(1 * MSEC);
+	}
+
+	end_time += 6 * MSEC;
+	while (get_time().val < end_time) {
+		if (mock_tcpci_get_reg(TCPC_REG_TRANSMIT) ==
+		    TCPCI_MSG_TX_HARD_RESET)
+			break;
+		task_wait_event(1 * MSEC);
+	}
+	TEST_EQ(mock_tcpci_get_reg(TCPC_REG_TRANSMIT), TCPCI_MSG_TX_HARD_RESET,
+		"%d");
+	mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS | TCPC_REG_ALERT_TX_FAILED);
+	mock_tcpci_set_reg(TCPC_REG_TRANSMIT, 0);
+	task_wait_event(1 * MSEC);
+
+	return EC_SUCCESS;
+}
diff --git a/test/usb_tcpmv2_td_pd_vndi3_e3.c b/test/usb_tcpmv2_td_pd_vndi3_e3.c
new file mode 100644
index 0000000000..590c02a0e8
--- /dev/null
+++ b/test/usb_tcpmv2_td_pd_vndi3_e3.c
@@ -0,0 +1,111 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "mock/tcpci_i2c_mock.h"
+#include "task.h"
+#include "tcpm/tcpci.h"
+#include "test_util.h"
+#include "timer.h"
+#include "usb_tc_sm.h"
+#include "usb_tcpmv2_compliance.h"
+
+uint32_t vdo =
+	VDO(USB_SID_PD, 1, VDO_SVDM_VERS(VDM_VER20) | CMD_DISCOVER_IDENT);
+
+/*****************************************************************************
+ * TD.PD.VNDI3.E3.VDM Identity
+ *
+ * Description:
+ *	This test verifies that the VDM Information is as specified in the
+ *	vendor-supplied information.
+ */
+static int td_pd_vndi3_e3(enum pd_data_role data_role)
+{
+	partner_set_pd_rev(PD_REV30);
+
+	TEST_EQ(tcpci_startup(), EC_SUCCESS, "%d");
+
+	/*
+	 * a) Run PROC.PD.E1 Bring-up according to the UUT role.
+	 */
+	TEST_EQ(proc_pd_e1(data_role, INITIAL_AND_ALREADY_ATTACHED), EC_SUCCESS,
+		"%d");
+
+	/*
+	 * Make sure we are idle. Reject everything that is pending
+	 */
+	TEST_EQ(handle_attach_expected_msgs(data_role), EC_SUCCESS, "%d");
+
+	/*
+	 * b) Tester executes a Discover Identity exchange
+	 */
+	partner_send_msg(TCPCI_MSG_SOP, PD_DATA_VENDOR_DEF, 1, 0, &vdo);
+
+	/*
+	 * c) If the UUT is not a cable and if Responds_To_Discov_SOP is set to
+	 * No, the tester checks that the UUT replies Not_Supported.  The test
+	 * stops here in this case.
+	 */
+	TEST_EQ(verify_tcpci_transmit(TCPCI_MSG_SOP, PD_CTRL_NOT_SUPPORTED, 0),
+		EC_SUCCESS, "%d");
+	mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
+
+	/*
+	 * TODO: Items d)-i) could be verified if the unit tests are configured
+	 * to reply to Identity messages.
+	 *
+	 * d) For Cables, the Tester checks the consistency of
+	 * Specification_Revision
+	 *
+	 * e) For all devices, the Tester checks in the ID Header consistency
+	 * of:
+	 *	1. Product_Type(UFP)
+	 *	2. Product Type(Cable Plug)
+	 *	3. Product Type (DFP)
+	 *	4. USB_VID(_SOP)
+	 *	5. Modal_Operation_Supported(_SOP)
+	 *	6. Data_Capable_as_USB_Host(_SOP)
+	 *	7. Data_Capable_as_USB_Device(_SOP)
+	 *
+	 * f) For all devices, the Tester checks in the Cert Stat VDO
+	 * consistency of:
+	 *	1. XID(_SOP)
+	 *
+	 * g) For all devices, the Tester checks in the Product VDO consistency
+	 * of:
+	 *	1. PID(_SOP)
+	 *	2. bcdDevice(_SOP)
+	 *
+	 * h) For Cables, the Tester checks in the Cable VDO consistency of:
+	 *	1. Cable_HW_Vers
+	 *	2. Cable_FW_Vers
+	 *	3. Type_C_to_Type_C_Capt_Vdm_V2
+	 *	4. Cable_Latency
+	 *	5. Cable_Termination_Type
+	 *	6. Max_VBUS_Voltage_Vdm_V2
+	 *	7. Cable_VBUS_Current
+	 *	8. VBUS_through_cable
+	 *	9. Cable_SOP''_controller
+	 *	10. Cable_Superspeed_Support
+	 *
+	 * i) For Alt Mode Adapters, the Tester checks in the AMA VDO
+	 * consistency of:
+	 *	1. AMA_HW_Vers
+	 *	2. AMA_FW_Vers
+	 *	3. AMA_VCONN_power
+	 *	4. AMA_VCONN_reqd
+	 *	5. AMA_VBUS_reqd
+	 *	6. AMA_Superspeed_Support
+	 */
+	return EC_SUCCESS;
+}
+int test_td_pd_vndi3_e3_dfp(void)
+{
+	return td_pd_vndi3_e3(PD_ROLE_DFP);
+}
+int test_td_pd_vndi3_e3_ufp(void)
+{
+	return td_pd_vndi3_e3(PD_ROLE_UFP);
+}
diff --git a/test/usb_test/Makefile b/test/usb_test/Makefile
index e18e4a7c3b..df21c7d331 100644
--- a/test/usb_test/Makefile
+++ b/test/usb_test/Makefile
@@ -1,4 +1,4 @@
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/test/usb_test/device_configuration.c b/test/usb_test/device_configuration.c
index 69f889c2d3..94496fa0fc 100644
--- a/test/usb_test/device_configuration.c
+++ b/test/usb_test/device_configuration.c
@@ -1,20 +1,21 @@
 /*
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include <errno.h>
-#include <getopt.h>
-#include <libusb.h>
 #include <stdarg.h>
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
 
+#include <getopt.h>
+#include <libusb.h>
+
 /* Options */
-static uint16_t vid = 0x18d1;			/* Google */
-static uint16_t pid = 0x5014;			/* Cr50 */
+static uint16_t vid = 0x18d1; /* Google */
+static uint16_t pid = 0x5014; /* Cr50 */
 
 static char *progname;
 
@@ -25,7 +26,8 @@ static void usage(int errs)
 	       "Set/Get the USB Device Configuration value\n"
 	       "\n"
 	       "The default vid:pid is %04x:%04x\n"
-	       "\n", progname, vid, pid);
+	       "\n",
+	       progname, vid, pid);
 
 	exit(!!errs);
 }
@@ -49,14 +51,13 @@ static void stupid_usb(const char *format, ...)
 	exit(1);
 }
 
-
 int main(int argc, char *argv[])
 {
 	int r = 1;
 	int errorcnt = 0;
 	int do_set = 0;
 	uint16_t setval = 0;
-	uint8_t buf[80];			/* Arbitrary size */
+	uint8_t buf[80]; /* Arbitrary size */
 	int i;
 
 	progname = strrchr(argv[0], '/');
@@ -65,13 +66,13 @@ int main(int argc, char *argv[])
 	else
 		progname = argv[0];
 
-	opterr = 0;				/* quiet, you */
+	opterr = 0; /* quiet, you */
 	while ((i = getopt(argc, argv, "")) != -1) {
 		switch (i) {
 		case 'h':
 			usage(errorcnt);
 			break;
-		case 0:				/* auto-handled option */
+		case 0: /* auto-handled option */
 			break;
 		case '?':
 			if (optopt)
@@ -111,8 +112,8 @@ int main(int argc, char *argv[])
 
 	r = libusb_init(NULL);
 	if (r) {
-		printf("libusb_init() returned 0x%x: %s\n",
-		       r, libusb_error_name(r));
+		printf("libusb_init() returned 0x%x: %s\n", r,
+		       libusb_error_name(r));
 		return 1;
 	}
 
@@ -122,41 +123,36 @@ int main(int argc, char *argv[])
 		stupid_usb("Can't open device %04x:%04x\n", vid, pid);
 	}
 
-
 	/* Set config*/
 	if (do_set) {
 		printf("SetCfg %d\n", setval);
-		r = libusb_control_transfer(
-			devh,
-			0x00,			/* bmRequestType */
-			0x09,			/* bRequest */
-			setval,			/* wValue */
-			0x0000,			/* wIndex */
-			NULL,			/* data */
-			0x0000,			/* wLength */
-			1000);			/* timeout (ms) */
+		r = libusb_control_transfer(devh, 0x00, /* bmRequestType */
+					    0x09, /* bRequest */
+					    setval, /* wValue */
+					    0x0000, /* wIndex */
+					    NULL, /* data */
+					    0x0000, /* wLength */
+					    1000); /* timeout (ms) */
 
 		if (r < 0)
-			printf("transfer returned 0x%x %s\n",
-			       r, libusb_error_name(r));
+			printf("transfer returned 0x%x %s\n", r,
+			       libusb_error_name(r));
 	}
 
 	/* Get config */
 	memset(buf, 0, sizeof(buf));
 
-	r = libusb_control_transfer(
-		devh,
-		0x80,				/* bmRequestType */
-		0x08,				/* bRequest */
-		0x0000,				/* wValue */
-		0x0000,				/* wIndex */
-		buf,				/* data */
-		0x0001,				/* wLength */
-		1000);				/* timeout (ms) */
+	r = libusb_control_transfer(devh, 0x80, /* bmRequestType */
+				    0x08, /* bRequest */
+				    0x0000, /* wValue */
+				    0x0000, /* wIndex */
+				    buf, /* data */
+				    0x0001, /* wLength */
+				    1000); /* timeout (ms) */
 
 	if (r <= 0)
-		stupid_usb("GetCfg transfer() returned 0x%x %s\n",
-			   r, libusb_error_name(r));
+		stupid_usb("GetCfg transfer() returned 0x%x %s\n", r,
+			   libusb_error_name(r));
 
 	printf("GetCfg returned %d bytes:", r);
 	for (i = 0; i < r; i++)
diff --git a/test/usb_typec_ctvpd.c b/test/usb_typec_ctvpd.c
index d46e68e40d..17c3452a62 100644
--- a/test/usb_typec_ctvpd.c
+++ b/test/usb_typec_ctvpd.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,20 +10,20 @@
 #include "test_util.h"
 #include "timer.h"
 #include "usb_pd.h"
-#include "usb_sm.h"
-#include "usb_tc_sm.h"
-#include "util.h"
 #include "usb_pd_tcpm.h"
 #include "usb_pd_test_util.h"
+#include "usb_sm.h"
 #include "usb_sm_checks.h"
+#include "usb_tc_sm.h"
+#include "util.h"
 #include "vpd_api.h"
 
-#define PORT0	0
+#define PORT0 0
 
-enum cc_type {CC1, CC2};
-enum vbus_type {VBUS_0 = 0, VBUS_5 = 5000};
-enum vconn_type {VCONN_0 = 0, VCONN_3 = 3000, VCONN_5 = 5000};
-enum snk_con_voltage_type {SRC_CON_DEF, SRC_CON_1_5, SRC_CON_3_0};
+enum cc_type { CC1, CC2 };
+enum vbus_type { VBUS_0 = 0, VBUS_5 = 5000 };
+enum vconn_type { VCONN_0 = 0, VCONN_3 = 3000, VCONN_5 = 5000 };
+enum snk_con_voltage_type { SRC_CON_DEF, SRC_CON_1_5, SRC_CON_3_0 };
 
 /*
  * These enum definitions are declared in usb_tc_*_sm and are private to that
@@ -92,15 +92,15 @@ static int ct_connect_sink(enum cc_type cc, enum snk_con_voltage_type v)
 	switch (v) {
 	case SRC_CON_DEF:
 		ret = (cc) ? mock_set_cc2_rp3a0_rd_l(PD_SRC_DEF_RD_THRESH_MV) :
-			mock_set_cc1_rp3a0_rd_l(PD_SRC_DEF_RD_THRESH_MV);
+			     mock_set_cc1_rp3a0_rd_l(PD_SRC_DEF_RD_THRESH_MV);
 		break;
 	case SRC_CON_1_5:
 		ret = (cc) ? mock_set_cc2_rp3a0_rd_l(PD_SRC_1_5_RD_THRESH_MV) :
-			mock_set_cc1_rp3a0_rd_l(PD_SRC_1_5_RD_THRESH_MV);
+			     mock_set_cc1_rp3a0_rd_l(PD_SRC_1_5_RD_THRESH_MV);
 		break;
 	case SRC_CON_3_0:
 		ret = (cc) ? mock_set_cc2_rp3a0_rd_l(PD_SRC_3_0_RD_THRESH_MV) :
-			mock_set_cc1_rp3a0_rd_l(PD_SRC_3_0_RD_THRESH_MV);
+			     mock_set_cc1_rp3a0_rd_l(PD_SRC_3_0_RD_THRESH_MV);
 		break;
 	default:
 		ret = 0;
@@ -124,7 +124,7 @@ static int ct_connect_source(enum cc_type cc, enum vbus_type vbus)
 {
 	mock_set_ct_vbus(vbus);
 	return (cc) ? mock_set_cc2_rpusb_odh(PD_SNK_VA_MV) :
-				mock_set_cc1_rpusb_odh(PD_SNK_VA_MV);
+		      mock_set_cc1_rpusb_odh(PD_SNK_VA_MV);
 }
 
 static int ct_disconnect_source(void)
@@ -297,14 +297,15 @@ void inc_rx_id(int port)
 static int verify_goodcrc(int port, int role, int id)
 {
 	return pd_test_tx_msg_verify_sop_prime(port) &&
-		pd_test_tx_msg_verify_short(port, PD_HEADER(PD_CTRL_GOOD_CRC,
-					role, role, id, 0, 0, 0)) &&
-		pd_test_tx_msg_verify_crc(port) &&
-		pd_test_tx_msg_verify_eop(port);
+	       pd_test_tx_msg_verify_short(port,
+					   PD_HEADER(PD_CTRL_GOOD_CRC, role,
+						     role, id, 0, 0, 0)) &&
+	       pd_test_tx_msg_verify_crc(port) &&
+	       pd_test_tx_msg_verify_eop(port);
 }
 
 static void simulate_rx_msg(int port, uint16_t header, int cnt,
-							const uint32_t *data)
+			    const uint32_t *data)
 {
 	int i;
 
@@ -330,20 +331,20 @@ static void simulate_rx_msg(int port, uint16_t header, int cnt,
 
 static void simulate_goodcrc(int port, int role, int id)
 {
-	simulate_rx_msg(port, PD_HEADER(PD_CTRL_GOOD_CRC, role, role, id, 0,
-						pd_port[port].rev, 0), 0, NULL);
+	simulate_rx_msg(port,
+			PD_HEADER(PD_CTRL_GOOD_CRC, role, role, id, 0,
+				  pd_port[port].rev, 0),
+			0, NULL);
 }
 
 static void simulate_discovery_identity(int port)
 {
-	uint16_t header = PD_HEADER(PD_DATA_VENDOR_DEF, PD_ROLE_SOURCE,
-					0, pd_port[port].msg_rx_id,
-					1, pd_port[port].rev, 0);
-	uint32_t msg = VDO(USB_SID_PD,
-			1, /* Structured VDM */
-			VDO_SVDM_VERS(1) |
-			VDO_CMDT(CMDT_INIT) |
-			CMD_DISCOVER_IDENT);
+	uint16_t header = PD_HEADER(PD_DATA_VENDOR_DEF, PD_ROLE_SOURCE, 1,
+				    pd_port[port].msg_rx_id, 1,
+				    pd_port[port].rev, 0);
+	uint32_t msg = VDO(USB_SID_PD, 1, /* Structured VDM */
+			   VDO_SVDM_VERS(1) | VDO_CMDT(CMDT_INIT) |
+				   CMD_DISCOVER_IDENT);
 
 	simulate_rx_msg(port, header, 1, (const uint32_t *)&msg);
 }
@@ -538,33 +539,27 @@ static int test_vpd_host_src_detection_vconn(void)
 static int test_vpd_host_src_detection_message_reception(void)
 {
 	int port = PORT0;
-	uint32_t expected_vdm_header = VDO(USB_VID_GOOGLE,
-			1, /* Structured VDM */
-			VDO_SVDM_VERS(1) |
-			VDO_CMDT(CMDT_RSP_ACK) |
-			CMD_DISCOVER_IDENT);
-	uint32_t expected_vdo_id_header = VDO_IDH(
-			0, /* Not a USB Host */
+	uint32_t expected_vdm_header = VDO(
+		USB_VID_GOOGLE, 1, /* Structured VDM */
+		VDO_SVDM_VERS(1) | VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_IDENT);
+	uint32_t expected_vdo_id_header =
+		VDO_IDH(0, /* Not a USB Host */
 			1, /* Capable of being enumerated as USB Device */
-			IDH_PTYPE_VPD,
-			0, /* Modal Operation Not Supported */
+			IDH_PTYPE_VPD, 0, /* Modal Operation Not Supported */
 			USB_VID_GOOGLE);
 	uint32_t expected_vdo_cert = 0;
-	uint32_t expected_vdo_product = VDO_PRODUCT(
-			CONFIG_USB_PID,
-			USB_BCD_DEVICE);
+	uint32_t expected_vdo_product =
+		VDO_PRODUCT(CONFIG_USB_PID, USB_BCD_DEVICE);
 	uint32_t expected_vdo_vpd = VDO_VPD(
-			VPD_HW_VERSION,
-			VPD_FW_VERSION,
-			VPD_MAX_VBUS_20V,
-			VPD_VBUS_IMP(VPD_VBUS_IMPEDANCE),
-			VPD_GND_IMP(VPD_GND_IMPEDANCE),
-#ifdef CONFIG_USB_CTVPD
-			VPD_CTS_SUPPORTED
-#else
-			VPD_CTS_NOT_SUPPORTED
-#endif
-			);
+		VPD_HW_VERSION, VPD_FW_VERSION, VPD_MAX_VBUS_20V,
+		IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_CT_CURRENT : 0,
+		IS_ENABLED(CONFIG_USB_CTVPD) ?
+			VPD_VBUS_IMP(VPD_VBUS_IMPEDANCE) :
+			0,
+		IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_GND_IMP(VPD_GND_IMPEDANCE) :
+					       0,
+		IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_CTS_SUPPORTED :
+					       VPD_CTS_NOT_SUPPORTED);
 
 	mock_set_vconn(VCONN_0);
 	host_disconnect_source();
@@ -606,8 +601,8 @@ static int test_vpd_host_src_detection_message_reception(void)
 	simulate_discovery_identity(port);
 	task_wait_event(30 * MSEC);
 
-	TEST_ASSERT(verify_goodcrc(port,
-				PD_ROLE_SINK, pd_port[port].msg_rx_id));
+	TEST_ASSERT(
+		verify_goodcrc(port, PD_ROLE_SINK, pd_port[port].msg_rx_id));
 
 	task_wake(PD_PORT_TO_TASK_ID(port));
 	task_wait_event(30 * MSEC);
@@ -615,9 +610,10 @@ static int test_vpd_host_src_detection_message_reception(void)
 
 	/* Test Discover Identity Ack */
 	TEST_ASSERT(pd_test_tx_msg_verify_sop_prime(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
-			PD_HEADER(PD_DATA_VENDOR_DEF, PD_PLUG_FROM_CABLE, 0,
-			pd_port[port].msg_tx_id, 5, pd_port[port].rev, 0)));
+	TEST_ASSERT(pd_test_tx_msg_verify_short(
+		port,
+		PD_HEADER(PD_DATA_VENDOR_DEF, PD_PLUG_FROM_CABLE, 0,
+			  pd_port[port].msg_tx_id, 5, pd_port[port].rev, 0)));
 	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_vdm_header));
 	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_vdo_id_header));
 	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_vdo_cert));
@@ -646,7 +642,6 @@ static int test_vpd_host_src_detection_message_reception(void)
 
 	TEST_EQ(get_state_tc(port), TC_UNATTACHED_SNK, "%d");
 
-
 	return EC_SUCCESS;
 }
 
@@ -990,29 +985,27 @@ static int test_ctvpd_behavior_case3(void)
 static int test_ctvpd_behavior_case4(void)
 {
 	int port = PORT0;
-	uint32_t expected_vdm_header = VDO(USB_VID_GOOGLE,
-			1, /* Structured VDM */
-			VDO_SVDM_VERS(1) |
-			VDO_CMDT(CMDT_RSP_ACK) |
-			CMD_DISCOVER_IDENT);
-	uint32_t expected_vdo_id_header = VDO_IDH(
-			0, /* Not a USB Host */
+	uint32_t expected_vdm_header = VDO(
+		USB_VID_GOOGLE, 1, /* Structured VDM */
+		VDO_SVDM_VERS(1) | VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_IDENT);
+	uint32_t expected_vdo_id_header =
+		VDO_IDH(0, /* Not a USB Host */
 			1, /* Capable of being enumerated as USB Device */
-			IDH_PTYPE_VPD,
-			0, /* Modal Operation Not Supported */
+			IDH_PTYPE_VPD, 0, /* Modal Operation Not Supported */
 			USB_VID_GOOGLE);
 	uint32_t expected_vdo_cert = 0;
-	uint32_t expected_vdo_product = VDO_PRODUCT(
-			CONFIG_USB_PID,
-			USB_BCD_DEVICE);
+	uint32_t expected_vdo_product =
+		VDO_PRODUCT(CONFIG_USB_PID, USB_BCD_DEVICE);
 	uint32_t expected_vdo_vpd = VDO_VPD(
-			VPD_HW_VERSION,
-			VPD_FW_VERSION,
-			VPD_MAX_VBUS_20V,
-			VPD_VBUS_IMP(VPD_VBUS_IMPEDANCE),
-			VPD_GND_IMP(VPD_GND_IMPEDANCE),
-			VPD_CTS_SUPPORTED
-			);
+		VPD_HW_VERSION, VPD_FW_VERSION, VPD_MAX_VBUS_20V,
+		IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_CT_CURRENT : 0,
+		IS_ENABLED(CONFIG_USB_CTVPD) ?
+			VPD_VBUS_IMP(VPD_VBUS_IMPEDANCE) :
+			0,
+		IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_GND_IMP(VPD_GND_IMPEDANCE) :
+					       0,
+		IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_CTS_SUPPORTED :
+					       VPD_CTS_NOT_SUPPORTED);
 
 	init_port(port);
 	mock_set_vconn(VCONN_0);
@@ -1099,8 +1092,8 @@ static int test_ctvpd_behavior_case4(void)
 	simulate_discovery_identity(port);
 	task_wait_event(40 * MSEC);
 
-	TEST_ASSERT(verify_goodcrc(port,
-				PD_ROLE_SINK, pd_port[port].msg_rx_id));
+	TEST_ASSERT(
+		verify_goodcrc(port, PD_ROLE_SINK, pd_port[port].msg_rx_id));
 
 	task_wake(PD_PORT_TO_TASK_ID(port));
 	task_wait_event(40 * MSEC);
@@ -1108,9 +1101,10 @@ static int test_ctvpd_behavior_case4(void)
 
 	/* Test Discover Identity Ack */
 	TEST_ASSERT(pd_test_tx_msg_verify_sop_prime(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
-			PD_HEADER(PD_DATA_VENDOR_DEF, PD_PLUG_FROM_CABLE, 0,
-			pd_port[port].msg_tx_id, 5, pd_port[port].rev, 0)));
+	TEST_ASSERT(pd_test_tx_msg_verify_short(
+		port,
+		PD_HEADER(PD_DATA_VENDOR_DEF, PD_PLUG_FROM_CABLE, 0,
+			  pd_port[port].msg_tx_id, 5, pd_port[port].rev, 0)));
 	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_vdm_header));
 	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_vdo_id_header));
 	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_vdo_cert));
@@ -1260,8 +1254,8 @@ static int test_ctvpd_behavior_case5(void)
 	 *    e. CTVPD connects VBUS from the Charge-Through side to the Host
 	 *       side
 	 */
-	wait_for_state_change(port, PD_T_TRY_CC_DEBOUNCE +
-						PD_T_DRP_TRY + 40 * MSEC);
+	wait_for_state_change(port,
+			      PD_T_TRY_CC_DEBOUNCE + PD_T_DRP_TRY + 40 * MSEC);
 
 	TEST_ASSERT(get_state_tc(port) == TC_TRY_WAIT_SRC);
 	TEST_ASSERT(check_host_rpusb());
@@ -1494,7 +1488,7 @@ static int test_ctvpd_behavior_case6(void)
 }
 #endif
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
@@ -1529,6 +1523,8 @@ void run_test(int argc, char **argv)
 	RUN_TEST(test_pe_no_parent_cycles);
 	RUN_TEST(test_pe_all_states_named);
 
+	/* Some handlers are still running after the test ends. */
+	sleep(1);
+
 	test_print_result();
 }
-
diff --git a/test/usb_typec_ctvpd.tasklist b/test/usb_typec_ctvpd.tasklist
index eb41326e3e..5c7f804157 100644
--- a/test/usb_typec_ctvpd.tasklist
+++ b/test/usb_typec_ctvpd.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/usb_typec_drp_acc_trysrc.c b/test/usb_typec_drp_acc_trysrc.c
index 52793bb92f..637db36d80 100644
--- a/test/usb_typec_drp_acc_trysrc.c
+++ b/test/usb_typec_drp_acc_trysrc.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -27,45 +27,65 @@
 /* Unreachable time in future */
 #define TIMER_DISABLED 0xffffffffffffffff
 
-/* TODO(b/153071799): Move these pd_* and pe_* function into mock */
-__overridable void pd_request_power_swap(int port)
-{}
+/* Install Mock TCPC and MUX drivers */
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.drv = &mock_tcpc_driver,
+	},
+};
+
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { {
+	.mux =
+		&(const struct usb_mux){
+			.driver = &mock_usb_mux_driver,
+		},
+} };
 
-uint8_t pd_get_src_cap_cnt(int port)
+uint8_t pd_get_bist_share_mode(void)
 {
 	return 0;
 }
 
-const uint32_t * const pd_get_src_caps(int port)
+void charge_manager_set_ceil(int port, enum ceil_requestor requestor, int ceil)
 {
-	return NULL;
+	/* Do Nothing, but needed for linking */
 }
 
-void pd_set_src_caps(int port, int cnt, uint32_t *src_caps)
+void pd_resume_check_pr_swap_needed(int port)
 {
+	/* Do Nothing, but needed for linking */
 }
 
-__overridable void pe_invalidate_explicit_contract(int port)
+/* Vbus is turned on at the board level, so mock it here for our purposes */
+static bool board_vbus_enabled[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+static bool mock_get_vbus_enabled(int port)
 {
+	return board_vbus_enabled[port];
 }
-/* End pd_ mock section */
 
-/* Install Mock TCPC and MUX drivers */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.drv = &mock_tcpc_driver,
-	},
-};
+static void mock_set_vbus_enabled(int port, bool enabled)
+{
+	board_vbus_enabled[port] = enabled;
+}
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.driver = &mock_usb_mux_driver,
-	}
-};
+static void mock_reset_vbus_enabled(void)
+{
+	int i;
 
-void charge_manager_set_ceil(int port, enum ceil_requestor requestor, int ceil)
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
+		mock_set_vbus_enabled(i, false);
+}
+
+int pd_set_power_supply_ready(int port)
 {
-	/* Do Nothing, but needed for linking */
+	mock_set_vbus_enabled(port, true);
+	return EC_SUCCESS;
+}
+
+void pd_power_supply_reset(int port)
+{
+	mock_set_vbus_enabled(port, false);
 }
 
 __maybe_unused static int test_mux_con_dis_as_src(void)
@@ -76,7 +96,7 @@ __maybe_unused static int test_mux_con_dis_as_src(void)
 	/* Update CC lines send state machine event to process */
 	mock_tcpc.cc1 = TYPEC_CC_VOLT_RD;
 	mock_tcpc.cc2 = TYPEC_CC_VOLT_OPEN;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC, 0);
+	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
 	pd_set_dual_role(0, PD_DRP_TOGGLE_ON);
 
 	/* This wait trainsitions through AttachWait.SRC then Attached.SRC */
@@ -88,7 +108,7 @@ __maybe_unused static int test_mux_con_dis_as_src(void)
 
 	mock_tcpc.cc1 = TYPEC_CC_VOLT_OPEN;
 	mock_tcpc.cc2 = TYPEC_CC_VOLT_OPEN;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC, 0);
+	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
 
 	/* This wait will go through TryWait.SNK then to Unattached.SNK */
 	task_wait_event(10 * SECOND);
@@ -105,11 +125,17 @@ __maybe_unused static int test_mux_con_dis_as_snk(void)
 	mock_tcpc.should_print_call = false;
 	mock_usb_mux.num_set_calls = 0;
 
+	/*
+	 * we expect a PD-capable partner to be able to check below
+	 * whether it is data capable.
+	 */
+	tc_pd_connection(0, 1);
+
 	/* Update CC lines send state machine event to process */
 	mock_tcpc.cc1 = TYPEC_CC_VOLT_RP_3_0;
 	mock_tcpc.cc2 = TYPEC_CC_VOLT_OPEN;
 	mock_tcpc.vbus_level = 1;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC, 0);
+	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
 
 	/* This wait will go through AttachWait.SNK to Attached.SNK */
 	task_wait_event(5 * SECOND);
@@ -123,7 +149,7 @@ __maybe_unused static int test_mux_con_dis_as_snk(void)
 	mock_tcpc.cc1 = TYPEC_CC_VOLT_OPEN;
 	mock_tcpc.cc2 = TYPEC_CC_VOLT_OPEN;
 	mock_tcpc.vbus_level = 0;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC, 0);
+	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
 
 	/* This wait will go through TryWait.SNK then to Unattached.SNK */
 	task_wait_event(10 * SECOND);
@@ -148,7 +174,7 @@ __maybe_unused static int test_power_role_set(void)
 	/* Update CC lines send state machine event to process */
 	mock_tcpc.cc1 = TYPEC_CC_VOLT_OPEN;
 	mock_tcpc.cc2 = TYPEC_CC_VOLT_RD;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC, 0);
+	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
 	task_wait_event(10 * SECOND);
 
 	/* We are in Attached.SRC now */
@@ -180,7 +206,7 @@ __maybe_unused static int test_polarity_cc1_default(void)
 	 */
 	mock_tcpc.last.polarity = POLARITY_COUNT;
 
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC, 0);
+	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
 
 	/* Before tCCDebounce elapses, we should SRC */
 	task_wait_event(PD_T_CC_DEBOUNCE + FUDGE);
@@ -196,7 +222,7 @@ __maybe_unused static int test_polarity_cc1_1A5(void)
 	mock_tcpc.cc1 = TYPEC_CC_VOLT_RP_1_5;
 	mock_tcpc.cc2 = TYPEC_CC_VOLT_OPEN;
 	mock_tcpc.vbus_level = 1;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC, 0);
+	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
 
 	/* Before tCCDebounce elapses, we should SRC */
 	task_wait_event(PD_T_CC_DEBOUNCE + FUDGE);
@@ -212,7 +238,7 @@ __maybe_unused static int test_polarity_cc1_3A0(void)
 	mock_tcpc.cc1 = TYPEC_CC_VOLT_RP_3_0;
 	mock_tcpc.cc2 = TYPEC_CC_VOLT_OPEN;
 	mock_tcpc.vbus_level = 1;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC, 0);
+	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
 
 	/* Before tCCDebounce elapses, we should SRC */
 	task_wait_event(PD_T_CC_DEBOUNCE + FUDGE);
@@ -228,7 +254,7 @@ __maybe_unused static int test_polarity_cc2_default(void)
 	mock_tcpc.cc1 = TYPEC_CC_VOLT_OPEN;
 	mock_tcpc.cc2 = TYPEC_CC_VOLT_RP_DEF;
 	mock_tcpc.vbus_level = 1;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC, 0);
+	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
 
 	/* Before tCCDebounce elapses, we should SRC */
 	task_wait_event(PD_T_CC_DEBOUNCE + FUDGE);
@@ -244,7 +270,7 @@ __maybe_unused static int test_polarity_cc2_1A5(void)
 	mock_tcpc.cc1 = TYPEC_CC_VOLT_OPEN;
 	mock_tcpc.cc2 = TYPEC_CC_VOLT_RP_1_5;
 	mock_tcpc.vbus_level = 1;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC, 0);
+	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
 
 	/* Before tCCDebounce elapses, we should SRC */
 	task_wait_event(PD_T_CC_DEBOUNCE + FUDGE);
@@ -260,7 +286,7 @@ __maybe_unused static int test_polarity_cc2_3A0(void)
 	mock_tcpc.cc1 = TYPEC_CC_VOLT_OPEN;
 	mock_tcpc.cc2 = TYPEC_CC_VOLT_RP_3_0;
 	mock_tcpc.vbus_level = 1;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC, 0);
+	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
 
 	/* Before tCCDebounce elapses, we should SRC */
 	task_wait_event(PD_T_CC_DEBOUNCE + FUDGE);
@@ -276,7 +302,7 @@ __maybe_unused static int test_polarity_dts_cc1_default(void)
 	mock_tcpc.cc1 = TYPEC_CC_VOLT_RP_3_0;
 	mock_tcpc.cc2 = TYPEC_CC_VOLT_RP_1_5;
 	mock_tcpc.vbus_level = 1;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC, 0);
+	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
 
 	/* Before tCCDebounce elapses, we should SRC */
 	task_wait_event(PD_T_CC_DEBOUNCE + FUDGE);
@@ -292,7 +318,7 @@ __maybe_unused static int test_polarity_dts_cc1_1A5(void)
 	mock_tcpc.cc1 = TYPEC_CC_VOLT_RP_1_5;
 	mock_tcpc.cc2 = TYPEC_CC_VOLT_RP_DEF;
 	mock_tcpc.vbus_level = 1;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC, 0);
+	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
 
 	/* Before tCCDebounce elapses, we should SRC */
 	task_wait_event(PD_T_CC_DEBOUNCE + FUDGE);
@@ -308,7 +334,7 @@ __maybe_unused static int test_polarity_dts_cc1_3A0(void)
 	mock_tcpc.cc1 = TYPEC_CC_VOLT_RP_3_0;
 	mock_tcpc.cc2 = TYPEC_CC_VOLT_RP_DEF;
 	mock_tcpc.vbus_level = 1;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC, 0);
+	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
 
 	/* Before tCCDebounce elapses, we should SRC */
 	task_wait_event(PD_T_CC_DEBOUNCE + FUDGE);
@@ -324,7 +350,7 @@ __maybe_unused static int test_polarity_dts_cc2_default(void)
 	mock_tcpc.cc1 = TYPEC_CC_VOLT_RP_1_5;
 	mock_tcpc.cc2 = TYPEC_CC_VOLT_RP_3_0;
 	mock_tcpc.vbus_level = 1;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC, 0);
+	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
 
 	/* Before tCCDebounce elapses, we should SRC */
 	task_wait_event(PD_T_CC_DEBOUNCE + FUDGE);
@@ -340,7 +366,7 @@ __maybe_unused static int test_polarity_dts_cc2_1A5(void)
 	mock_tcpc.cc1 = TYPEC_CC_VOLT_RP_DEF;
 	mock_tcpc.cc2 = TYPEC_CC_VOLT_RP_1_5;
 	mock_tcpc.vbus_level = 1;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC, 0);
+	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
 
 	/* Before tCCDebounce elapses, we should SRC */
 	task_wait_event(PD_T_CC_DEBOUNCE + FUDGE);
@@ -356,7 +382,7 @@ __maybe_unused static int test_polarity_dts_cc2_3A0(void)
 	mock_tcpc.cc1 = TYPEC_CC_VOLT_RP_DEF;
 	mock_tcpc.cc2 = TYPEC_CC_VOLT_RP_3_0;
 	mock_tcpc.vbus_level = 1;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC, 0);
+	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
 
 	/* Before tCCDebounce elapses, we should SRC */
 	task_wait_event(PD_T_CC_DEBOUNCE + FUDGE);
@@ -386,7 +412,7 @@ __maybe_unused static int test_try_src_disabled(void)
 	mock_tcpc.cc1 = TYPEC_CC_VOLT_OPEN;
 	mock_tcpc.cc2 = TYPEC_CC_VOLT_RP_3_0;
 	mock_tcpc.vbus_level = 1;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC, 0);
+	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
 
 	/* Wait a long time past many potential transitions */
 	task_wait_event(10 * SECOND);
@@ -425,7 +451,7 @@ static int switch_to_opposite_role(int port, int pull)
 		ccprints("[Test] Partner presents SRC with Vbus ON");
 	}
 
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC, 0);
+	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
 
 	return EC_SUCCESS;
 };
@@ -440,7 +466,7 @@ __maybe_unused static int test_try_src_partner_switches(void)
 	mock_tcpc.cc1 = TYPEC_CC_VOLT_OPEN;
 	mock_tcpc.cc2 = TYPEC_CC_VOLT_RP_3_0;
 	mock_tcpc.vbus_level = 1;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC, 0);
+	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
 
 	/* We are in AttachWait.SNK now */
 	/* Before tCCDebounce elapses, we should still be a SNK */
@@ -486,7 +512,7 @@ static int dumb_src_charger_cc_response(int port, int pull)
 
 	ccprints("[Test] Partner presents SRC with Vbus ON");
 
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC, 0);
+	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
 
 	return EC_SUCCESS;
 };
@@ -501,7 +527,7 @@ __maybe_unused static int test_try_src_partner_does_not_switch_vbus(void)
 	mock_tcpc.cc1 = TYPEC_CC_VOLT_OPEN;
 	mock_tcpc.cc2 = TYPEC_CC_VOLT_RP_3_0;
 	mock_tcpc.vbus_level = 1;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC, 0);
+	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
 
 	/* We are in AttachWait.SNK now */
 	/* Before tCCDebounce elapses, we should still be a SNK */
@@ -557,7 +583,7 @@ static int src_charger_drops_vbus_cc_response(int port, int pull)
 		ccprints("[Test] Partner presents SRC with Vbus ON");
 	}
 
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC, 0);
+	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
 
 	return EC_SUCCESS;
 };
@@ -572,7 +598,7 @@ __maybe_unused static int test_try_src_partner_does_not_switch_no_vbus(void)
 	mock_tcpc.cc1 = TYPEC_CC_VOLT_OPEN;
 	mock_tcpc.cc2 = TYPEC_CC_VOLT_RP_3_0;
 	mock_tcpc.vbus_level = 1;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC, 0);
+	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
 
 	/* We are in AttachWait.SNK now */
 	/* Before tCCDebounce elapses, we should still be a SNK */
@@ -624,7 +650,7 @@ __maybe_unused static int test_cc_open_on_normal_reset(void)
 
 	system_clear_reset_flags(EC_RESET_FLAG_POWER_ON);
 
-	task_set_event(TASK_ID_PD_C0, TASK_EVENT_RESET_DONE, 0);
+	task_set_event(TASK_ID_PD_C0, TASK_EVENT_RESET_DONE);
 	task_wait_event(SECOND * 10);
 
 	/* Ensure that the first CC set call was to open (error recovery). */
@@ -650,7 +676,7 @@ __maybe_unused static int test_cc_rd_on_por_reset(void)
 
 	system_set_reset_flags(EC_RESET_FLAG_POWER_ON);
 
-	task_set_event(TASK_ID_PD_C0, TASK_EVENT_RESET_DONE, 0);
+	task_set_event(TASK_ID_PD_C0, TASK_EVENT_RESET_DONE);
 	task_wait_event(SECOND * 10);
 
 	/* Ensure that the first CC set call was to Rd (sink) */
@@ -683,7 +709,7 @@ __maybe_unused static int test_auto_toggle_delay(void)
 	 */
 	task_wait_event(SECOND);
 	TEST_GT(mock_tcpc.first_call_to_enable_auto_toggle - time,
-		15ul * MSEC, "%lu");
+		(uint64_t)15 * MSEC, "%" PRIu64);
 
 	return EC_SUCCESS;
 }
@@ -708,12 +734,12 @@ __maybe_unused static int test_auto_toggle_delay_early_connect(void)
 	mock_tcpc.cc1 = TYPEC_CC_VOLT_OPEN;
 	mock_tcpc.cc2 = TYPEC_CC_VOLT_RP_3_0;
 	mock_tcpc.vbus_level = 1;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC, 0);
+	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
 
 	/* Ensure the auto toggle enable was never called */
 	task_wait_event(SECOND);
-	TEST_EQ(mock_tcpc.first_call_to_enable_auto_toggle,
-		TIMER_DISABLED, "%lu");
+	TEST_EQ(mock_tcpc.first_call_to_enable_auto_toggle, TIMER_DISABLED,
+		"%" PRIu64);
 
 	/* Ensure that the first CC set call was to Rd. */
 	TEST_GT(cc_pull_count, 0, "%d");
@@ -723,23 +749,80 @@ __maybe_unused static int test_auto_toggle_delay_early_connect(void)
 }
 
 /* TODO(b/153071799): test as SNK monitor for Vbus disconnect (not CC line) */
-/* TODO(b/153071799): test as SRC monitor for CC line state change */
+__maybe_unused static int test_typec_dis_as_src(void)
+{
+	mock_tcpc.should_print_call = false;
+
+	/* Update CC lines send state machine event to process */
+	mock_tcpc.cc1 = TYPEC_CC_VOLT_RD;
+	mock_tcpc.cc2 = TYPEC_CC_VOLT_OPEN;
+	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
+	pd_set_dual_role(0, PD_DRP_TOGGLE_ON);
+
+	/* This wait trainsitions through AttachWait.SRC then Attached.SRC */
+	task_wait_event(SECOND);
+
+	/*
+	 * We are in Attached.SRC now, verify:
+	 * - Vbus was turned on
+	 * - Rp is set
+	 * - polarity is detected as CC1
+	 * - Rp was set to default configured level
+	 */
+	TEST_EQ(mock_tcpc.last.cc, TYPEC_CC_RP, "%d");
+	TEST_EQ(mock_tcpc.last.polarity, POLARITY_CC1, "%d");
+	TEST_EQ(mock_tcpc.last.rp, CONFIG_USB_PD_PULLUP, "%d");
+	TEST_EQ(mock_get_vbus_enabled(0), true, "%d");
+
+	/* Force a detach through CC open */
+	mock_tcpc.cc1 = TYPEC_CC_VOLT_OPEN;
+	mock_tcpc.cc2 = TYPEC_CC_VOLT_OPEN;
+	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
+
+	/* This wait will go through TryWait.SNK then to Unattached.SNK */
+	task_wait_event(10 * SECOND);
+
+	/* We are in Unattached.SNK. Verify Vbus has been removed */
+	TEST_EQ(mock_get_vbus_enabled(0), false, "%d");
+
+	return EC_SUCCESS;
+}
+
+__maybe_unused static int test_wake_tcpc_toggle_change(void)
+{
+	/* Start with auto toggle disabled */
+	pd_set_dual_role(PORT0, PD_DRP_TOGGLE_OFF);
+	task_wait_event(SECOND);
+
+	/* TCPC should be asleep */
+	TEST_EQ(mock_tcpc.lpm_wake_requested, false, "%d");
+
+	/* Enabled auto toggle */
+	pd_set_dual_role(PORT0, PD_DRP_TOGGLE_ON);
+	task_wait_event(FUDGE);
+
+	/* Ensure TCPC was woken */
+	TEST_EQ(mock_tcpc.lpm_wake_requested, true, "%d");
+
+	return EC_SUCCESS;
+}
 
 /* Reset the mocks before each test */
 void before_test(void)
 {
 	mock_usb_mux_reset();
 	mock_tcpc_reset();
+	mock_reset_vbus_enabled();
 
 	/* Restart the PD task and let it settle */
-	task_set_event(TASK_ID_PD_C0, TASK_EVENT_RESET_DONE, 0);
+	task_set_event(TASK_ID_PD_C0, TASK_EVENT_RESET_DONE);
 	task_wait_event(SECOND);
 
 	/* Print out TCPC calls for easier debugging */
 	mock_tcpc.should_print_call = true;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
@@ -763,6 +846,8 @@ void run_test(int argc, char **argv)
 	RUN_TEST(test_mux_con_dis_as_snk);
 	RUN_TEST(test_power_role_set);
 
+	RUN_TEST(test_typec_dis_as_src);
+
 	RUN_TEST(test_try_src_disabled);
 	RUN_TEST(test_try_src_partner_switches);
 	RUN_TEST(test_try_src_partner_does_not_switch_vbus);
@@ -773,6 +858,8 @@ void run_test(int argc, char **argv)
 	RUN_TEST(test_auto_toggle_delay);
 	RUN_TEST(test_auto_toggle_delay_early_connect);
 
+	RUN_TEST(test_wake_tcpc_toggle_change);
+
 	/* Do basic state machine validity checks last. */
 	RUN_TEST(test_tc_no_parent_cycles);
 	RUN_TEST(test_tc_all_states_named);
diff --git a/test/usb_typec_drp_acc_trysrc.mocklist b/test/usb_typec_drp_acc_trysrc.mocklist
index 71c2e2cee9..cbff5e73eb 100644
--- a/test/usb_typec_drp_acc_trysrc.mocklist
+++ b/test/usb_typec_drp_acc_trysrc.mocklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/usb_typec_drp_acc_trysrc.tasklist b/test/usb_typec_drp_acc_trysrc.tasklist
index eb41326e3e..5c7f804157 100644
--- a/test/usb_typec_drp_acc_trysrc.tasklist
+++ b/test/usb_typec_drp_acc_trysrc.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/utils.c b/test/utils.c
index 92643980d5..775f8582f4 100644
--- a/test/utils.c
+++ b/test/utils.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -14,198 +14,18 @@
 #include "util.h"
 #include "watchdog.h"
 
-static int test_memmove(void)
-{
-	int i;
-	timestamp_t t0, t1, t2, t3;
-	char *buf;
-	const int buf_size = 1000;
-	const int len = 400;
-	const int iteration = 1000;
-
-	TEST_ASSERT(shared_mem_acquire(buf_size, &buf) == EC_SUCCESS);
-
-	for (i = 0; i < len; ++i)
-		buf[i] = i & 0x7f;
-	for (i = len; i < buf_size; ++i)
-		buf[i] = 0;
-
-	t0 = get_time();
-	for (i = 0; i < iteration; ++i)
-		memmove(buf + 101, buf, len);  /* unaligned */
-	t1 = get_time();
-	TEST_ASSERT_ARRAY_EQ(buf + 101, buf, len);
-	ccprintf(" (speed gain: %" PRId64 " ->", t1.val-t0.val);
-
-	t2 = get_time();
-	for (i = 0; i < iteration; ++i)
-		memmove(buf + 100, buf, len);	  /* aligned */
-	t3 = get_time();
-	ccprintf(" %" PRId64 " us) ", t3.val-t2.val);
-	TEST_ASSERT_ARRAY_EQ(buf + 100, buf, len);
-
-	/* Expected about 4x speed gain. Use 3x because it fluctuates */
-#ifndef EMU_BUILD
-	/*
-	 * The speed gain is too unpredictable on host, especially on
-	 * buildbots. Skip it if we are running in the emulator.
-	 */
-	TEST_ASSERT((t1.val-t0.val) > (unsigned)(t3.val-t2.val) * 3);
+#ifndef USE_BUILTIN_STDLIB
+#include <malloc.h>
 #endif
 
-	/* Test small moves */
-	memmove(buf + 1, buf, 1);
-	TEST_ASSERT_ARRAY_EQ(buf + 1, buf, 1);
-	memmove(buf + 5, buf, 4);
-	memmove(buf + 1, buf, 4);
-	TEST_ASSERT_ARRAY_EQ(buf + 1, buf + 5, 4);
-
-	shared_mem_release(buf);
-	return EC_SUCCESS;
-}
-
-static int test_memcpy(void)
-{
-	int i;
-	timestamp_t t0, t1, t2, t3;
-	char *buf;
-	const int buf_size = 1000;
-	const int len = 400;
-	const int dest_offset = 500;
-	const int iteration = 1000;
-
-	TEST_ASSERT(shared_mem_acquire(buf_size, &buf) == EC_SUCCESS);
-
-	for (i = 0; i < len; ++i)
-		buf[i] = i & 0x7f;
-	for (i = len; i < buf_size; ++i)
-		buf[i] = 0;
-
-	t0 = get_time();
-	for (i = 0; i < iteration; ++i)
-		memcpy(buf + dest_offset + 1, buf, len);  /* unaligned */
-	t1 = get_time();
-	TEST_ASSERT_ARRAY_EQ(buf + dest_offset + 1, buf, len);
-	ccprintf(" (speed gain: %" PRId64 " ->", t1.val-t0.val);
-
-	t2 = get_time();
-	for (i = 0; i < iteration; ++i)
-		memcpy(buf + dest_offset, buf, len);	  /* aligned */
-	t3 = get_time();
-	ccprintf(" %" PRId64 " us) ", t3.val-t2.val);
-	TEST_ASSERT_ARRAY_EQ(buf + dest_offset, buf, len);
-
-	/* Expected about 4x speed gain. Use 3x because it fluctuates */
-#ifndef EMU_BUILD
-	/*
-	 * The speed gain is too unpredictable on host, especially on
-	 * buildbots. Skip it if we are running in the emulator.
-	 */
-	TEST_ASSERT((t1.val-t0.val) > (unsigned)(t3.val-t2.val) * 3);
-#endif
-
-	memcpy(buf + dest_offset + 1, buf + 1, len - 1);
-	TEST_ASSERT_ARRAY_EQ(buf + dest_offset + 1, buf + 1, len - 1);
-
-	/* Test small copies */
-	memcpy(buf + dest_offset, buf, 1);
-	TEST_ASSERT_ARRAY_EQ(buf + dest_offset, buf, 1);
-	memcpy(buf + dest_offset, buf, 4);
-	TEST_ASSERT_ARRAY_EQ(buf + dest_offset, buf, 4);
-	memcpy(buf + dest_offset + 1, buf, 1);
-	TEST_ASSERT_ARRAY_EQ(buf + dest_offset + 1, buf, 1);
-	memcpy(buf + dest_offset + 1, buf, 4);
-	TEST_ASSERT_ARRAY_EQ(buf + dest_offset + 1, buf, 4);
-
-	shared_mem_release(buf);
-	return EC_SUCCESS;
-}
-
-/* Plain memset, used as a reference to measure speed gain */
-static void *dumb_memset(void *dest, int c, int len)
-{
-	char *d = (char *)dest;
-	while (len > 0) {
-		*(d++) = c;
-		len--;
-	}
-	return dest;
-}
-
-static int test_memset(void)
-{
-	int i;
-	timestamp_t t0, t1, t2, t3;
-	char *buf;
-	const int buf_size = 1000;
-	const int len = 400;
-	const int iteration = 1000;
-
-	TEST_ASSERT(shared_mem_acquire(buf_size, &buf) == EC_SUCCESS);
-
-	t0 = get_time();
-	for (i = 0; i < iteration; ++i)
-		dumb_memset(buf, 1, len);
-	t1 = get_time();
-	TEST_ASSERT_MEMSET(buf, (char)1, len);
-	ccprintf(" (speed gain: %" PRId64 " ->", t1.val-t0.val);
-
-	t2 = get_time();
-	for (i = 0; i < iteration; ++i)
-		memset(buf, 1, len);
-	t3 = get_time();
-	TEST_ASSERT_MEMSET(buf, (char)1, len);
-	ccprintf(" %" PRId64 " us) ", t3.val-t2.val);
-
-	/*
-	 * Expected about 4x speed gain. Use smaller value since it
-	 * fluctuates.
-	 */
-	if (!IS_ENABLED(EMU_BUILD)) {
-		/*
-		 * The speed gain is too unpredictable on host, especially on
-		 * buildbots. Skip it if we are running in the emulator.
-		 */
-		int expected_speedup = 3;
-
-		if (IS_ENABLED(CHIP_FAMILY_STM32F4))
-			expected_speedup = 2;
-
-		TEST_ASSERT((t1.val - t0.val) >
-			    (unsigned int)(t3.val - t2.val) * expected_speedup);
-	}
-
-	memset(buf, 128, len);
-	TEST_ASSERT_MEMSET(buf, (char)128, len);
-
-	memset(buf, -2, len);
-	TEST_ASSERT_MEMSET(buf, (char)-2, len);
-
-	memset(buf + 1, 1, len - 2);
-	TEST_ASSERT_MEMSET(buf + 1, (char)1, len - 2);
-
-	shared_mem_release(buf);
-	return EC_SUCCESS;
-}
-
-static int test_memchr(void)
-{
-	char *buf = "1234";
-
-	TEST_ASSERT(memchr("123567890", '4', 8) == NULL);
-	TEST_ASSERT(memchr("123", '3', 2) == NULL);
-	TEST_ASSERT(memchr(buf, '3', 4) == buf + 2);
-	TEST_ASSERT(memchr(buf, '4', 4) == buf + 3);
-	return EC_SUCCESS;
-}
-
 static int test_uint64divmod_0(void)
 {
 	uint64_t n = 8567106442584750ULL;
 	int d = 54870071;
 	int r = uint64divmod(&n, d);
 
-	TEST_CHECK(r == 5991285 && n == 156134415ULL);
+	TEST_ASSERT(r == 5991285 && n == 156134415ULL);
+	return EC_SUCCESS;
 }
 
 static int test_uint64divmod_1(void)
@@ -214,7 +34,8 @@ static int test_uint64divmod_1(void)
 	int d = 2;
 	int r = uint64divmod(&n, d);
 
-	TEST_CHECK(r == 0 && n == 4283553221292375ULL);
+	TEST_ASSERT(r == 0 && n == 4283553221292375ULL);
+	return EC_SUCCESS;
 }
 
 static int test_uint64divmod_2(void)
@@ -223,7 +44,8 @@ static int test_uint64divmod_2(void)
 	int d = 0;
 	int r = uint64divmod(&n, d);
 
-	TEST_CHECK(r == 0 && n == 0ULL);
+	TEST_ASSERT(r == 0 && n == 0ULL);
+	return EC_SUCCESS;
 }
 
 static int test_get_next_bit(void)
@@ -246,6 +68,17 @@ static int test_shared_mem(void)
 	int sz = shared_mem_size();
 	char *mem1, *mem2;
 
+#ifndef USE_BUILTIN_STDLIB
+	/* Trim to make sure that other tests haven't fragmented the heap. */
+	malloc_trim(0);
+
+	/*
+	 * When using malloc() we can't allocate the full shared_mem_size() due
+	 * to the overhead of malloc's memory tracking. See test/malloc.c.
+	 */
+	sz *= 0.8;
+#endif
+
 	TEST_ASSERT(shared_mem_acquire(sz, &mem1) == EC_SUCCESS);
 	TEST_ASSERT(shared_mem_acquire(sz, &mem2) == EC_ERROR_BUSY);
 
@@ -261,10 +94,21 @@ static int test_shared_mem(void)
 	return EC_SUCCESS;
 }
 
+test_static int test_shared_mem_release_null(void)
+{
+	/* This should be a no-op. We can't do much to test it directly. */
+	shared_mem_release(NULL);
+
+	return EC_SUCCESS;
+}
+
 static int test_scratchpad(void)
 {
+	uint32_t scratchpad_value;
+
 	system_set_scratchpad(0xfeed);
-	TEST_ASSERT(system_get_scratchpad() == 0xfeed);
+	TEST_EQ(system_get_scratchpad(&scratchpad_value), EC_SUCCESS, "%d");
+	TEST_EQ(scratchpad_value, 0xfeed, "%d");
 
 	return EC_SUCCESS;
 }
@@ -385,35 +229,16 @@ static int test_mula32(void)
 	}
 	t1 = get_time();
 
-	ccprintf("After %d iterations, r=%08x%08x, r2=%08x%08x (time: %d)\n",
-		i, (uint32_t)(r >> 32), (uint32_t)r,
-		(uint32_t)(r2 >> 32), (uint32_t)r2, t1.le.lo-t0.le.lo);
-	TEST_ASSERT(r  == 0x9df59b9fb0ab9d96L);
+	ccprintf("After %d iterations, r=%08x%08x, r2=%08x%08x (time: %d)\n", i,
+		 (uint32_t)(r >> 32), (uint32_t)r, (uint32_t)(r2 >> 32),
+		 (uint32_t)r2, t1.le.lo - t0.le.lo);
+	TEST_ASSERT(r == 0x9df59b9fb0ab9d96L);
 	TEST_ASSERT(r2 == 0x9df59b9fb0beabd6L);
 
 	/* well okay then */
 	return EC_SUCCESS;
 }
 
-#define SWAP_TEST_HARNESS(t, x, y) \
-	do { \
-		t a = x, b = y; \
-		swap(a, b); \
-		TEST_ASSERT(a == y); \
-		TEST_ASSERT(b == x); \
-	} while (0)
-
-
-static int test_swap(void)
-{
-	SWAP_TEST_HARNESS(uint8_t, UINT8_MAX, 0);
-	SWAP_TEST_HARNESS(uint16_t, UINT16_MAX, 0);
-	SWAP_TEST_HARNESS(uint32_t, UINT32_MAX, 0);
-	SWAP_TEST_HARNESS(float, 1, 0);
-	SWAP_TEST_HARNESS(double, 1, 0);
-	return EC_SUCCESS;
-}
-
 static int test_bytes_are_trivial(void)
 {
 	static const uint8_t all0x00[] = { 0x00, 0x00, 0x00 };
@@ -456,7 +281,10 @@ test_static int test_safe_memcmp(void)
 	const char str2[] = "def";
 	const char str3[] = "abc";
 
-	BUILD_ASSERT(str1 != str3);
+	/* Verify that the compiler hasn't optimized str1 and str3 to point
+	 * to the same underlying memory.
+	 */
+	TEST_NE(str1, str3, "%p");
 
 	TEST_EQ(safe_memcmp(NULL, NULL, 0), 0, "%d");
 	TEST_EQ(safe_memcmp(str1, str2, sizeof(str1)), 1, "%d");
@@ -464,26 +292,117 @@ test_static int test_safe_memcmp(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+test_static int test_alignment_log2(void)
+{
+	TEST_EQ(alignment_log2(1), 0, "%d");
+	TEST_EQ(alignment_log2(2), 1, "%d");
+	TEST_EQ(alignment_log2(5), 0, "%d");
+	TEST_EQ(alignment_log2(0x10070000), 16, "%d");
+	TEST_EQ(alignment_log2(0x80000000), 31, "%d");
+	return EC_SUCCESS;
+}
+
+test_static int test_binary_first_base3_from_bits(void)
+{
+	int n0[] = { 0, 0, 0 }; /* LSB first */
+	int n7[] = { 1, 1, 1 };
+	int n8[] = { 2, 0, 0 };
+	int n9[] = { 2, 1, 0 };
+	int n10[] = { 0, 2, 0 };
+	int n11[] = { 1, 2, 0 };
+	int n18[] = { 0, 0, 2 };
+	int n26[] = { 2, 2, 2 };
+	int n38[] = { 1, 2, 0, 1 };
+
+	TEST_EQ(binary_first_base3_from_bits(n0, ARRAY_SIZE(n0)), 0, "%d");
+	TEST_EQ(binary_first_base3_from_bits(n7, ARRAY_SIZE(n7)), 7, "%d");
+	TEST_EQ(binary_first_base3_from_bits(n8, ARRAY_SIZE(n8)), 8, "%d");
+	TEST_EQ(binary_first_base3_from_bits(n9, ARRAY_SIZE(n9)), 9, "%d");
+	TEST_EQ(binary_first_base3_from_bits(n10, ARRAY_SIZE(n10)), 10, "%d");
+	TEST_EQ(binary_first_base3_from_bits(n11, ARRAY_SIZE(n11)), 11, "%d");
+	TEST_EQ(binary_first_base3_from_bits(n18, ARRAY_SIZE(n18)), 18, "%d");
+	TEST_EQ(binary_first_base3_from_bits(n26, ARRAY_SIZE(n26)), 26, "%d");
+	TEST_EQ(binary_first_base3_from_bits(n38, ARRAY_SIZE(n38)), 38, "%d");
+	return EC_SUCCESS;
+}
+
+test_static int test_parse_bool(void)
+{
+	int bool_val;
+	int rv;
+
+	/* False cases. */
+
+	bool_val = 1;
+	rv = parse_bool("off", &bool_val);
+	TEST_EQ(rv, 1, "%d");
+	TEST_EQ(bool_val, 0, "%d");
+
+	bool_val = 1;
+	rv = parse_bool("dis", &bool_val);
+	TEST_EQ(rv, 1, "%d");
+	TEST_EQ(bool_val, 0, "%d");
+
+	bool_val = 1;
+	rv = parse_bool("f", &bool_val);
+	TEST_EQ(rv, 1, "%d");
+	TEST_EQ(bool_val, 0, "%d");
+
+	bool_val = 1;
+	rv = parse_bool("n", &bool_val);
+	TEST_EQ(rv, 1, "%d");
+	TEST_EQ(bool_val, 0, "%d");
+
+	/* True cases. */
+
+	bool_val = 0;
+	rv = parse_bool("on", &bool_val);
+	TEST_EQ(rv, 1, "%d");
+	TEST_EQ(bool_val, 1, "%d");
+
+	bool_val = 0;
+	rv = parse_bool("ena", &bool_val);
+	TEST_EQ(rv, 1, "%d");
+	TEST_EQ(bool_val, 1, "%d");
+
+	bool_val = 0;
+	rv = parse_bool("t", &bool_val);
+	TEST_EQ(rv, 1, "%d");
+	TEST_EQ(bool_val, 1, "%d");
+
+	bool_val = 0;
+	rv = parse_bool("y", &bool_val);
+	TEST_EQ(rv, 1, "%d");
+	TEST_EQ(bool_val, 1, "%d");
+
+	/* Error case. */
+	bool_val = -1;
+	rv = parse_bool("a", &bool_val);
+	TEST_EQ(rv, 0, "%d");
+	TEST_EQ(bool_val, -1, "%d");
+
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
-	RUN_TEST(test_memmove);
-	RUN_TEST(test_memcpy);
-	RUN_TEST(test_memset);
-	RUN_TEST(test_memchr);
 	RUN_TEST(test_uint64divmod_0);
 	RUN_TEST(test_uint64divmod_1);
 	RUN_TEST(test_uint64divmod_2);
 	RUN_TEST(test_get_next_bit);
+	RUN_TEST(test_shared_mem_release_null);
 	RUN_TEST(test_shared_mem);
 	RUN_TEST(test_scratchpad);
 	RUN_TEST(test_cond_t);
 	RUN_TEST(test_mula32);
-	RUN_TEST(test_swap);
 	RUN_TEST(test_bytes_are_trivial);
 	RUN_TEST(test_is_aligned);
 	RUN_TEST(test_safe_memcmp);
+	RUN_TEST(test_alignment_log2);
+	RUN_TEST(test_binary_first_base3_from_bits);
+	RUN_TEST(test_parse_bool);
 
 	test_print_result();
 }
diff --git a/test/utils.tasklist b/test/utils.tasklist
index da0ab6211a..100cb6b5bd 100644
--- a/test/utils.tasklist
+++ b/test/utils.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/utils_str.c b/test/utils_str.c
index 2a68f6c35f..4b2e3d4427 100644
--- a/test/utils_str.c
+++ b/test/utils_str.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -7,40 +7,12 @@
 
 #include "common.h"
 #include "console.h"
-#include "system.h"
 #include "printf.h"
+#include "system.h"
 #include "test_util.h"
 #include "timer.h"
 #include "util.h"
 
-static int test_isalpha(void)
-{
-	TEST_CHECK(isalpha('a') && isalpha('z') && isalpha('A') &&
-		   isalpha('Z') && !isalpha('0') && !isalpha('~') &&
-		   !isalpha(' ') && !isalpha('\0') && !isalpha('\n'));
-}
-
-static int test_isprint(void)
-{
-	TEST_CHECK(isprint('a') && isprint('z') && isprint('A') &&
-		   isprint('Z') && isprint('0') && isprint('~') &&
-		   isprint(' ') && !isprint('\0') && !isprint('\n'));
-}
-
-static int test_strstr(void)
-{
-	const char s1[] = "abcde";
-
-	TEST_ASSERT(strstr(s1, "ab") == s1);
-	TEST_ASSERT(strstr(s1, "") == NULL);
-	TEST_ASSERT(strstr("", "ab") == NULL);
-	TEST_ASSERT(strstr("", "x") == NULL);
-	TEST_ASSERT(strstr(s1, "de") == &s1[3]);
-	TEST_ASSERT(strstr(s1, "def") == NULL);
-
-	return EC_SUCCESS;
-}
-
 static int test_strtoi(void)
 {
 	char *e;
@@ -99,64 +71,6 @@ static int test_strtoi(void)
 	return EC_SUCCESS;
 }
 
-static int test_strtoul(void)
-{
-	char *e;
-
-	TEST_ASSERT(strtoul("10", &e, 0) == 10);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoul("010", &e, 0) == 8);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoul("+010", &e, 0) == 8);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoul("-010", &e, 0) == 0);
-	TEST_ASSERT(e && (*e == '-'));
-	TEST_ASSERT(strtoul("0x1f z", &e, 0) == 31);
-	TEST_ASSERT(e && (*e == ' '));
-	TEST_ASSERT(strtoul("0X1f z", &e, 0) == 31);
-	TEST_ASSERT(e && (*e == ' '));
-	TEST_ASSERT(strtoul("10a", &e, 16) == 266);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoul("0x02C", &e, 16) == 44);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoul("+0x02C", &e, 16) == 44);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoul("-0x02C", &e, 16) == 0);
-	TEST_ASSERT(e && (*e == '-'));
-	TEST_ASSERT(strtoul("0x02C", &e, 0) == 44);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoul("+0x02C", &e, 0) == 44);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoul("-0x02C", &e, 0) == 0);
-	TEST_ASSERT(e && (*e == '-'));
-	TEST_ASSERT(strtoul("0X02C", &e, 16) == 44);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoul("+0X02C", &e, 16) == 44);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoul("-0X02C", &e, 16) == 0);
-	TEST_ASSERT(e && (*e == '-'));
-	TEST_ASSERT(strtoul("0X02C", &e, 0) == 44);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoul("+0X02C", &e, 0) == 44);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoul("-0X02C", &e, 0) == 0);
-	TEST_ASSERT(e && (*e == '-'));
-	TEST_ASSERT(strtoul("   -12", &e, 0) == 0);
-	TEST_ASSERT(e && (*e == '-'));
-	TEST_ASSERT(strtoul("!", &e, 0) == 0);
-	TEST_ASSERT(e && (*e == '!'));
-	TEST_ASSERT(strtoul("+!", &e, 0) == 0);
-	TEST_ASSERT(e && (*e == '!'));
-	TEST_ASSERT(strtoul("+0!", &e, 0) == 0);
-	TEST_ASSERT(e && (*e == '!'));
-	TEST_ASSERT(strtoul("+0x!", &e, 0) == 0);
-	TEST_ASSERT(e && (*e == '!'));
-	TEST_ASSERT(strtoul("+0X!", &e, 0) == 0);
-	TEST_ASSERT(e && (*e == '!'));
-
-	return EC_SUCCESS;
-}
-
 static int test_parse_bool(void)
 {
 	int v;
@@ -190,95 +104,13 @@ static int test_strzcpy(void)
 	return EC_SUCCESS;
 }
 
-static int test_strncpy(void)
-{
-	char dest[10];
-
-	strncpy(dest, "test", 10);
-	TEST_ASSERT_ARRAY_EQ("test", dest, 5);
-	strncpy(dest, "12345", 6);
-	TEST_ASSERT_ARRAY_EQ("12345", dest, 6);
-	strncpy(dest, "testtesttest", 10);
-	TEST_ASSERT_ARRAY_EQ("testtestte", dest, 10);
-
-	return EC_SUCCESS;
-}
-
-static int test_strncmp(void)
-{
-	TEST_ASSERT(strncmp("123", "123", 8) == 0);
-	TEST_ASSERT(strncmp("789", "456", 8) > 0);
-	TEST_ASSERT(strncmp("abc", "abd", 4) < 0);
-	TEST_ASSERT(strncmp("abc", "abd", 2) == 0);
-	return EC_SUCCESS;
-}
-
-static int test_strlen(void)
-{
-	TEST_CHECK(strlen("this is a string") == 16);
-}
-
-static int test_strnlen(void)
-{
-	TEST_ASSERT(strnlen("this is a string", 17) == 16);
-	TEST_ASSERT(strnlen("this is a string", 16) == 16);
-	TEST_ASSERT(strnlen("this is a string", 5) == 5);
-
-	return EC_SUCCESS;
-}
-
-static int test_strcasecmp(void)
-{
-	TEST_CHECK((strcasecmp("test string", "TEST strIng") == 0) &&
-		   (strcasecmp("test123!@#", "TesT123!@#") == 0) &&
-		   (strcasecmp("lower", "UPPER") != 0));
-}
-
-static int test_strncasecmp(void)
-{
-	TEST_CHECK((strncasecmp("test string", "TEST str", 4) == 0) &&
-		   (strncasecmp("test string", "TEST str", 8) == 0) &&
-		   (strncasecmp("test123!@#", "TesT321!@#", 5) != 0) &&
-		   (strncasecmp("test123!@#", "TesT321!@#", 4) == 0) &&
-		   (strncasecmp("1test123!@#", "1TesT321!@#", 5) == 0) &&
-		   (strncasecmp("1test123", "teststr", 0) == 0));
-}
-
-static int test_atoi(void)
-{
-	TEST_CHECK((atoi("  901") == 901) &&
-		   (atoi("-12c") == -12) &&
-		   (atoi("   0  ") == 0) &&
-		   (atoi("\t111") == 111));
-}
-
-static int test_snprintf(void)
-{
-	char buffer[32];
-
-	TEST_CHECK(snprintf(buffer, sizeof(buffer), "%u", 1234) == 4);
-	TEST_CHECK(strncmp(buffer, "1234", sizeof(buffer)));
-}
-
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
-	RUN_TEST(test_isalpha);
-	RUN_TEST(test_isprint);
-	RUN_TEST(test_strstr);
 	RUN_TEST(test_strtoi);
-	RUN_TEST(test_strtoul);
 	RUN_TEST(test_parse_bool);
 	RUN_TEST(test_strzcpy);
-	RUN_TEST(test_strncpy);
-	RUN_TEST(test_strncmp);
-	RUN_TEST(test_strlen);
-	RUN_TEST(test_strnlen);
-	RUN_TEST(test_strcasecmp);
-	RUN_TEST(test_strncasecmp);
-	RUN_TEST(test_atoi);
-	RUN_TEST(test_snprintf);
 
 	test_print_result();
 }
diff --git a/test/utils_str.tasklist b/test/utils_str.tasklist
index 7150f17cbd..6373a70ab1 100644
--- a/test/utils_str.tasklist
+++ b/test/utils_str.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/vboot.c b/test/vboot.c
index 7dab08ac05..caa3d2d7cb 100644
--- a/test/vboot.c
+++ b/test/vboot.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -7,10 +7,10 @@
 
 #include "common.h"
 #include "rsa.h"
-#include "test_util.h"
-#include "vboot.h"
 #include "rsa2048-3.h"
 #include "rwsig.h"
+#include "test_util.h"
+#include "vboot.h"
 
 struct vboot_key {
 	struct vb21_packed_key vb21_key;
@@ -131,7 +131,7 @@ static int test_vboot(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/vboot.tasklist b/test/vboot.tasklist
index 7150f17cbd..6373a70ab1 100644
--- a/test/vboot.tasklist
+++ b/test/vboot.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/version.c b/test/version.c
new file mode 100644
index 0000000000..fea691eef7
--- /dev/null
+++ b/test/version.c
@@ -0,0 +1,149 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Test ec version
+ */
+
+#include "common.h"
+#include "ec_commands.h"
+#include "stddef.h"
+#include "system.h"
+#include "test_util.h"
+#include "util.h"
+
+/*
+ * Tests that fw version adheres to the expected format.
+ * Example fw version: host_v2.0.10135+b3e38e380c
+ */
+static int test_version(void)
+{
+	const char *fw_version;
+	size_t board_name_length, major_version_length, minor_version_length,
+		sub_minor_version_length, hash_length;
+	const char *major_version_ptr, *minor_version_ptr,
+		*sub_minor_version_ptr, *hash_ptr;
+
+	fw_version = system_get_version(EC_IMAGE_RO);
+
+	TEST_ASSERT(fw_version != NULL);
+
+	ccprintf("fw_version: %s\n", fw_version);
+
+	TEST_LE(strlen(fw_version), (size_t)32, "%zu");
+
+	board_name_length = strcspn(fw_version, "_");
+
+	TEST_GE(board_name_length, (size_t)3, "%zu");
+
+	major_version_ptr = fw_version + board_name_length + 1;
+	major_version_length = strcspn(major_version_ptr, ".");
+
+	TEST_GE(major_version_length, (size_t)2, "%zu");
+	TEST_EQ(major_version_ptr[0], 'v', "%c");
+	for (int i = 1; i < major_version_length; i++)
+		TEST_ASSERT(isdigit(major_version_ptr[i]));
+
+	minor_version_ptr = major_version_ptr + major_version_length + 1;
+	minor_version_length = strcspn(minor_version_ptr, ".");
+
+	TEST_GE(minor_version_length, (size_t)1, "%zu");
+	for (int i = 0; i < minor_version_length; i++)
+		TEST_ASSERT(isdigit(minor_version_ptr[i]));
+
+	sub_minor_version_ptr = minor_version_ptr + minor_version_length + 1;
+	sub_minor_version_length = strcspn(sub_minor_version_ptr, "-+");
+
+	TEST_GE(sub_minor_version_length, (size_t)1, "%zu");
+	for (int i = 0; i < sub_minor_version_length; i++)
+		TEST_ASSERT(isdigit(sub_minor_version_ptr[i]));
+
+	hash_ptr = sub_minor_version_ptr + sub_minor_version_length + 1;
+	hash_length = strlen(hash_ptr);
+
+	TEST_GE(hash_length, (size_t)8, "%zu");
+	for (int i = 0; i < hash_length; i++)
+		TEST_ASSERT(isdigit(hash_ptr[i]) ||
+			    (hash_ptr[i] >= 'a' && hash_ptr[i] <= 'f'));
+
+	return EC_SUCCESS;
+}
+
+/*
+ * Tests that cros fwid adheres to the expected format.
+ * Example cros fwid: host_14175.0.21_08_24
+ */
+static int test_fwid(void)
+{
+	const char *cros_fwid;
+	size_t board_name_length, major_version_length, minor_version_length,
+		sub_minor_version_length;
+	const char *major_version_ptr, *minor_version_ptr,
+		*sub_minor_version_ptr;
+
+	cros_fwid = system_get_cros_fwid(EC_IMAGE_RO);
+
+	TEST_ASSERT(cros_fwid != NULL);
+
+	ccprintf("cros_fwid: %s\n", cros_fwid);
+
+	TEST_LE(strlen(cros_fwid), (size_t)32, "%zu");
+
+	board_name_length = strcspn(cros_fwid, "_");
+	TEST_GE(board_name_length, (size_t)3, "%zu");
+
+	major_version_ptr = cros_fwid + board_name_length + 1;
+	major_version_length = strcspn(major_version_ptr, ".");
+	TEST_GE(major_version_length, (size_t)5, "%zu");
+
+	for (int i = 0; i < major_version_length; i++)
+		TEST_ASSERT(isdigit(major_version_ptr[i]));
+
+	minor_version_ptr = major_version_ptr + major_version_length + 1;
+	minor_version_length = strcspn(minor_version_ptr, ".");
+	TEST_GE(minor_version_length, (size_t)1, "%zu");
+
+	for (int i = 0; i < minor_version_length; i++)
+		TEST_ASSERT(isdigit(minor_version_ptr[i]));
+
+	sub_minor_version_ptr = minor_version_ptr + minor_version_length + 1;
+	sub_minor_version_length = strlen(sub_minor_version_ptr);
+	TEST_GE(sub_minor_version_length, (size_t)1, "%zu");
+
+	for (int i = 0; i < sub_minor_version_length; i++)
+		TEST_ASSERT(isdigit(sub_minor_version_ptr[i]) ||
+			    sub_minor_version_ptr[i] == '_');
+
+	return EC_SUCCESS;
+}
+
+/*
+ * Tests requesting TEST.
+ * Example fw version: host_v2.0.10135+b3e38e380c
+ */
+static int test_image_unknown(void)
+{
+	const char *fw_version;
+	const char *cros_fwid;
+
+	fw_version = system_get_version(EC_IMAGE_UNKNOWN);
+
+	TEST_ASSERT(fw_version != NULL);
+	TEST_LE(strlen(fw_version), (size_t)32, "%zu");
+
+	cros_fwid = system_get_cros_fwid(EC_IMAGE_UNKNOWN);
+
+	TEST_ASSERT(cros_fwid != NULL);
+	TEST_LE(strlen(cros_fwid), (size_t)32, "%zu");
+
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
+{
+	RUN_TEST(test_version);
+	RUN_TEST(test_fwid);
+	RUN_TEST(test_image_unknown);
+
+	test_print_result();
+}
diff --git a/test/version.tasklist b/test/version.tasklist
new file mode 100644
index 0000000000..cd866d90e1
--- /dev/null
+++ b/test/version.tasklist
@@ -0,0 +1,9 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST  /* No test task */
diff --git a/test/vpd_api.c b/test/vpd_api.c
index 960c0c664b..e159dcb066 100644
--- a/test/vpd_api.c
+++ b/test/vpd_api.c
@@ -1,12 +1,12 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "console.h"
+#include "driver/tcpm/tcpm.h"
 #include "registers.h"
 #include "vpd_api.h"
-#include "driver/tcpm/tcpm.h"
-#include "console.h"
 /*
  * Polarity based on 'DFP Perspective' (see table USB Type-C Cable and Connector
  * Specification)
@@ -33,11 +33,11 @@
 #endif
 
 #ifndef CC_RA
-#define CC_RA(port, cc, sel)  (cc < pd_src_rd_threshold[ct_cc_rp_value])
+#define CC_RA(port, cc, sel) (cc < pd_src_rd_threshold[ct_cc_rp_value])
 #endif
 #define CC_RD(cc) ((cc >= PD_SRC_RD_THRESHOLD) && (cc < PD_SRC_VNC))
 #ifndef CC_NC
-#define CC_NC(port, cc, sel)  (cc >= PD_SRC_VNC)
+#define CC_NC(port, cc, sel) (cc >= PD_SRC_VNC)
 #endif
 
 /*
@@ -54,7 +54,7 @@
 #define PD_SNK_VA PD_SNK_VA_MV
 #endif
 
-#define CC_RP(cc)  (cc >= PD_SNK_VA)
+#define CC_RP(cc) (cc >= PD_SNK_VA)
 
 /* Mock Board State */
 static enum vpd_pwr mock_vconn_pwr_sel_odl;
@@ -266,7 +266,7 @@ static int vpd_cc_voltage_to_status(int cc_volt, int cc_pull)
 			return TYPEC_CC_VOLT_RA;
 		else
 			return TYPEC_CC_VOLT_RD;
-	/* If we have a pull-down, then we are sink, check for Rp. */
+		/* If we have a pull-down, then we are sink, check for Rp. */
 	} else if (cc_pull == TYPEC_CC_RD || cc_pull == TYPEC_CC_RA_RD) {
 		if (cc_volt >= TYPE_C_SRC_3000_THRESHOLD)
 			return TYPEC_CC_VOLT_RP_3_0;
@@ -324,8 +324,8 @@ void vpd_ct_set_pull(int pull, int rp_value)
 
 void vpd_ct_get_cc(int *cc1, int *cc2)
 {
-	int cc1_v;
-	int cc2_v;
+	int cc1_v = 0;
+	int cc2_v = 0;
 
 	switch (ct_cc_pull) {
 	case TYPEC_CC_RP:
diff --git a/test/vpd_api.h b/test/vpd_api.h
index 3db4803288..62dab34377 100644
--- a/test/vpd_api.h
+++ b/test/vpd_api.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,7 +8,6 @@
 #ifndef __CROS_EC_VPD_API_H
 #define __CROS_EC_VPD_API_H
 
-#include "adc.h"
 #include "gpio.h"
 #include "usb_pd.h"
 
@@ -17,39 +16,22 @@
  * voltage (set by selecting the proper Rd resistor). Any voltage below
  * TYPE_C_SRC_DEFAULT_THRESHOLD will not be identified as a type C charger.
  */
-#define TYPE_C_SRC_DEFAULT_THRESHOLD    200  /* mV */
-#define TYPE_C_SRC_1500_THRESHOLD       660  /* mV */
-#define TYPE_C_SRC_3000_THRESHOLD       1230 /* mV */
+#define TYPE_C_SRC_DEFAULT_THRESHOLD 200 /* mV */
+#define TYPE_C_SRC_1500_THRESHOLD 660 /* mV */
+#define TYPE_C_SRC_3000_THRESHOLD 1230 /* mV */
 
+enum vpd_pin { PIN_ADC, PIN_CMP, PIN_GPO };
 
-enum vpd_pin {
-	PIN_ADC,
-	PIN_CMP,
-	PIN_GPO
-};
-
-enum vpd_gpo {
-	GPO_HZ,
-	GPO_HIGH,
-	GPO_LOW
-};
+enum vpd_gpo { GPO_HZ, GPO_HIGH, GPO_LOW };
 
 enum vpd_pwr {
 	PWR_VCONN,
 	PWR_VBUS,
 };
 
-enum vpd_cc {
-	CT_OPEN,
-	CT_CC1,
-	CT_CC2
-};
+enum vpd_cc { CT_OPEN, CT_CC1, CT_CC2 };
 
-enum vpd_billboard {
-	BB_NONE,
-	BB_SRC,
-	BB_SNK
-};
+enum vpd_billboard { BB_NONE, BB_SRC, BB_SNK };
 
 struct mock_pin {
 	enum vpd_pin cfg;
diff --git a/test/x25519.tasklist b/test/x25519.tasklist
index 80072bb620..329f9a3d28 100644
--- a/test/x25519.tasklist
+++ b/test/x25519.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/third_party/bmi220/LICENSE b/third_party/bmi220/LICENSE
new file mode 100644
index 0000000000..11a00c4a64
--- /dev/null
+++ b/third_party/bmi220/LICENSE
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2020 Bosch Sensortec GmbH. All rights reserved.
+ *
+ * BSD-3-Clause
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
diff --git a/third_party/bmi220/METADATA b/third_party/bmi220/METADATA
new file mode 100644
index 0000000000..272a490378
--- /dev/null
+++ b/third_party/bmi220/METADATA
@@ -0,0 +1,15 @@
+name: "BMI220 implementation"
+description:
+    "Hex encoded binary for BMI220 driver initial configuration"
+
+third_party {
+  url {
+    type: HOMEPAGE
+    value: "https://www.bosch-sensortec.com/"
+  }
+  version: "v2.47.1"
+  last_upgrade_date { year: 2021 month: 06 day: 23 }
+  license_type: NOTICE
+  local_modifications: "Created LICENSE file."
+    "Adapted code to work with EC codebase."
+}
diff --git a/third_party/bmi220/accelgyro_bmi220_config_tbin.h b/third_party/bmi220/accelgyro_bmi220_config_tbin.h
new file mode 100644
index 0000000000..88b4b08e08
--- /dev/null
+++ b/third_party/bmi220/accelgyro_bmi220_config_tbin.h
@@ -0,0 +1,702 @@
+/*
+ * Copyright (c) 2020 Bosch Sensortec GmbH. All rights reserved.
+ *
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * @file accelgyro_bmi220_config_tbin.c
+ * @date 2021-06-23
+ * @version v2.47.1
+ *
+ */
+
+#include "common.h"
+
+const unsigned char __init_rom g_bmi220_config_tbin[] = {
+0xc8, 0x2e, 0x00, 0x2e, 0x80, 0x2e, 0xb6, 0xb0, 0xc8, 0x2e, 0x00, 0x2e,
+0x80, 0x2e, 0xee, 0x00, 0x80, 0x2e, 0x6a, 0x01, 0x80, 0x2e, 0xad, 0x01,
+0xc8, 0x2e, 0x00, 0x2e, 0x80, 0x2e, 0x01, 0xb0, 0x50, 0x32, 0x21, 0x2e,
+0x59, 0xf5, 0x10, 0x30, 0x21, 0x2e, 0x6a, 0xf5, 0x80, 0x2e, 0xea, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x3e, 0x21, 0x01, 0x00, 0x22, 0x00, 0x7f, 0x00,
+0x00, 0x0c, 0xff, 0x0f, 0xbc, 0x00, 0x85, 0x33, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0xac, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x32, 0x01, 0xe6, 0x78,
+0x84, 0x00, 0x9c, 0x6c, 0x07, 0x00, 0x64, 0x75, 0xaa, 0x7e, 0x5f, 0x05,
+0xbe, 0x0a, 0x5f, 0x05, 0x96, 0xe8, 0xef, 0x41, 0x01, 0x00, 0x0c, 0x00,
+0x0c, 0x00, 0x4a, 0x00, 0xa0, 0x00, 0x00, 0x00, 0x0c, 0x00, 0xf0, 0x3c,
+0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x02,
+0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0xc1, 0x4a, 0x00, 0x00, 0x6d, 0x57, 0x00, 0x00, 0x77, 0x8e, 0x00, 0x00,
+0xe0, 0xff, 0xff, 0xff, 0xd3, 0xff, 0xff, 0xff, 0xe5, 0xff, 0xff, 0xff,
+0xee, 0xe1, 0xff, 0xff, 0x7c, 0x13, 0x00, 0x00, 0x46, 0xe6, 0xff, 0xff,
+0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x1a, 0x24, 0x22, 0x00, 0x80, 0x2e, 0x48, 0x02, 0x10, 0x50, 0xf7, 0x7f,
+0x00, 0x2e, 0x0f, 0x2e, 0x69, 0xf5, 0xff, 0xbf, 0xff, 0xbb, 0xc0, 0x91,
+0x02, 0x2f, 0x37, 0x30, 0x2f, 0x2e, 0x69, 0xf5, 0xf7, 0x6f, 0xf0, 0x5f,
+0xc8, 0x2e, 0x80, 0x2e, 0x00, 0xc1, 0xfd, 0x2d, 0xc2, 0x00, 0xaa, 0xaa,
+0xd0, 0x07, 0xc0, 0xf5, 0xdc, 0x00, 0x1e, 0xf2, 0x69, 0xf5, 0x19, 0xf4,
+0x66, 0xf5, 0x00, 0x04, 0xff, 0x00, 0x64, 0xf5, 0xc6, 0x00, 0x08, 0x02,
+0xc9, 0x00, 0xa2, 0x00, 0xa4, 0x00, 0x87, 0x00, 0xda, 0x00, 0xff, 0x3f,
+0xff, 0xfb, 0x00, 0x18, 0x00, 0x10, 0xfd, 0xf5, 0xe2, 0x00, 0xac, 0x00,
+0xe2, 0x00, 0xe5, 0x00, 0x34, 0x43, 0x34, 0x4b, 0xff, 0xfd, 0x9a, 0xf1,
+0x99, 0x51, 0x9a, 0xf9, 0xc1, 0xf5, 0x8d, 0xf1, 0x80, 0x00, 0x00, 0x40,
+0x4d, 0x01, 0xeb, 0x00, 0x7f, 0xff, 0xc2, 0xf5, 0x68, 0xf7, 0xba, 0x00,
+0xae, 0x00, 0xb4, 0x00, 0xc0, 0x00, 0x60, 0x01, 0x61, 0xf7, 0x5b, 0xf7,
+0x63, 0x01, 0x78, 0xf7, 0x77, 0xf7, 0x00, 0x80, 0xff, 0x7f, 0x86, 0x00,
+0x52, 0x01, 0x65, 0x01, 0xb3, 0xf1, 0x5f, 0x01, 0x6c, 0xf7, 0xb9, 0xf1,
+0xc6, 0xf1, 0x00, 0xe0, 0x00, 0xff, 0xd1, 0xf5, 0x67, 0x01, 0x6a, 0x01,
+0xff, 0x03, 0x00, 0xfc, 0xf0, 0x3f, 0x0d, 0x02, 0x10, 0x02, 0x12, 0x02,
+0xb9, 0x00, 0x2d, 0xf5, 0xca, 0xf5, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0xa0, 0x50, 0x80, 0x7f, 0x91, 0x7f, 0xd7, 0x7f,
+0xc5, 0x7f, 0xb3, 0x7f, 0xa2, 0x7f, 0xe4, 0x7f, 0xf6, 0x7f, 0x7b, 0x7f,
+0x00, 0x2e, 0x0d, 0x50, 0x00, 0x2e, 0x01, 0x40, 0x9f, 0xbc, 0x9f, 0xb8,
+0x40, 0x90, 0x02, 0x2f, 0x31, 0x30, 0x23, 0x2e, 0x69, 0xf5, 0x37, 0x80,
+0x00, 0x2e, 0x00, 0x40, 0x60, 0x7f, 0x98, 0x2e, 0xdc, 0x01, 0x62, 0x6f,
+0x01, 0x32, 0x91, 0x08, 0x80, 0xb2, 0x0d, 0x2f, 0x00, 0xb2, 0x03, 0x2f,
+0x05, 0x2e, 0x18, 0x00, 0x80, 0x90, 0x05, 0x2f, 0x17, 0x56, 0x02, 0x30,
+0xc1, 0x42, 0xc2, 0x86, 0x00, 0x2e, 0xc2, 0x42, 0x23, 0x2e, 0x60, 0xf5,
+0x00, 0x90, 0x00, 0x30, 0x06, 0x2f, 0x21, 0x2e, 0x81, 0x00, 0x15, 0x50,
+0x21, 0x2e, 0x5a, 0xf2, 0x98, 0x2e, 0xf0, 0x01, 0xf6, 0x6f, 0xe4, 0x6f,
+0x80, 0x6f, 0x91, 0x6f, 0xa2, 0x6f, 0xb3, 0x6f, 0xc5, 0x6f, 0xd7, 0x6f,
+0x7b, 0x6f, 0x60, 0x5f, 0xc8, 0x2e, 0x30, 0x50, 0xe5, 0x7f, 0xf6, 0x7f,
+0xd7, 0x7f, 0x00, 0x2e, 0x0d, 0x5a, 0x00, 0x2e, 0x46, 0x41, 0x6f, 0xbf,
+0x6f, 0xbb, 0x80, 0x91, 0x02, 0x2f, 0x36, 0x30, 0x2d, 0x2e, 0x69, 0xf5,
+0x46, 0x30, 0x0f, 0x2e, 0xa4, 0xf1, 0xbe, 0x09, 0x77, 0x8b, 0x80, 0xb3,
+0x06, 0x2f, 0x0d, 0x2e, 0xa8, 0x00, 0x84, 0xaf, 0x02, 0x2f, 0x16, 0x30,
+0x2d, 0x2e, 0x84, 0x00, 0x86, 0x30, 0x46, 0x43, 0x00, 0x2e, 0xf6, 0x6f,
+0xe5, 0x6f, 0xd7, 0x6f, 0xd0, 0x5f, 0xc8, 0x2e, 0x03, 0x2e, 0xa7, 0x00,
+0x16, 0xb8, 0x02, 0x34, 0x4a, 0x0c, 0x21, 0x2e, 0x2d, 0xf5, 0xc0, 0x2e,
+0x23, 0x2e, 0xa7, 0x00, 0x2f, 0x52, 0x00, 0x2e, 0x60, 0x40, 0x41, 0x40,
+0x0d, 0xbc, 0x98, 0xbc, 0xc0, 0x2e, 0x01, 0x0a, 0x0f, 0xb8, 0x43, 0x86,
+0x25, 0x40, 0x04, 0x40, 0xd8, 0xbe, 0x2c, 0x0b, 0x22, 0x11, 0x54, 0x42,
+0x03, 0x80, 0x4b, 0x0e, 0xf6, 0x2f, 0xb8, 0x2e, 0x10, 0x50, 0xfb, 0x7f,
+0x98, 0x2e, 0x56, 0xc7, 0xfb, 0x6f, 0xf0, 0x5f, 0x80, 0x2e, 0x49, 0xc3,
+0x21, 0x2e, 0x59, 0xf5, 0x10, 0x30, 0xc0, 0x2e, 0x21, 0x2e, 0x4a, 0xf1,
+0x80, 0x2e, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x07,
+0x3e, 0x21, 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x05, 0xe0, 0xaa, 0x38, 0x05, 0xe0, 0x90, 0x30, 0x1e, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x25, 0x50, 0x10, 0x50,
+0x31, 0x52, 0x05, 0x2e, 0xa7, 0x00, 0xfb, 0x7f, 0x00, 0x2e, 0x13, 0x40,
+0x93, 0x42, 0x41, 0x0e, 0xfb, 0x2f, 0x98, 0x2e, 0xd2, 0x01, 0x98, 0x2e,
+0x87, 0xcf, 0x01, 0x2e, 0xad, 0x00, 0x00, 0xb2, 0x08, 0x2f, 0x01, 0x2e,
+0x69, 0xf7, 0xb1, 0x3f, 0x01, 0x08, 0x01, 0x30, 0x23, 0x2e, 0xad, 0x00,
+0x21, 0x2e, 0x69, 0xf7, 0xfb, 0x6f, 0xf0, 0x5f, 0xb8, 0x2e, 0x44, 0x47,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x40, 0x50, 0x98, 0x2e, 0xf5, 0xb5, 0x00, 0x30,
+0xf0, 0x7f, 0xe0, 0x7f, 0x21, 0x2e, 0x69, 0xf5, 0x00, 0x2e, 0x00, 0x2e,
+0xd0, 0x2e, 0x00, 0x2e, 0x01, 0x80, 0x08, 0xa2, 0xfb, 0x2f, 0x01, 0x2e,
+0xc5, 0x00, 0x00, 0xb2, 0x1a, 0x2f, 0x05, 0x2e, 0x0c, 0x02, 0x01, 0x52,
+0x98, 0x2e, 0xc7, 0xc1, 0x03, 0x2e, 0x18, 0x00, 0x40, 0xb2, 0xf0, 0x7f,
+0x10, 0x2f, 0x01, 0x2e, 0x0c, 0x02, 0x06, 0xbc, 0x0f, 0xb8, 0x00, 0x90,
+0x0a, 0x2f, 0x01, 0x50, 0x98, 0x2e, 0x4d, 0xc3, 0x01, 0x50, 0x98, 0x2e,
+0x5a, 0xc7, 0x98, 0x2e, 0x3e, 0xb1, 0x10, 0x30, 0x21, 0x2e, 0x19, 0x00,
+0x01, 0x2e, 0x0c, 0x02, 0x06, 0xbc, 0x0f, 0xb8, 0x00, 0xb2, 0x0e, 0x2f,
+0xe0, 0x6f, 0x00, 0x90, 0x0b, 0x2f, 0x07, 0x52, 0x00, 0x2e, 0x50, 0x40,
+0x41, 0x40, 0x21, 0x2e, 0xe8, 0x00, 0x23, 0x2e, 0xe9, 0x00, 0x98, 0x2e,
+0x91, 0x03, 0x10, 0x30, 0xe0, 0x7f, 0x98, 0x2e, 0xd7, 0xb1, 0x01, 0x2e,
+0xa8, 0x00, 0x04, 0xae, 0x0b, 0x2f, 0x01, 0x2e, 0xc5, 0x00, 0x00, 0xb2,
+0x07, 0x2f, 0x01, 0x52, 0x98, 0x2e, 0xa9, 0xb5, 0x00, 0xb2, 0x02, 0x2f,
+0x10, 0x30, 0x21, 0x2e, 0x86, 0x00, 0x01, 0x2e, 0x86, 0x00, 0x00, 0x90,
+0x36, 0x2f, 0x01, 0x2e, 0xab, 0x00, 0x00, 0xb2, 0x04, 0x2f, 0x98, 0x2e,
+0xf2, 0x03, 0x00, 0x30, 0x21, 0x2e, 0x84, 0x00, 0x01, 0x2e, 0x84, 0x00,
+0x00, 0xb2, 0x0b, 0x2f, 0x01, 0x2e, 0xa8, 0x00, 0x00, 0x90, 0x02, 0x2f,
+0x98, 0x2e, 0x43, 0xb5, 0x02, 0x2d, 0x98, 0x2e, 0x9b, 0xb4, 0x00, 0x30,
+0x21, 0x2e, 0x84, 0x00, 0x01, 0x2e, 0x85, 0x00, 0x00, 0xb2, 0x31, 0x2f,
+0x01, 0x2e, 0x85, 0x00, 0x01, 0x31, 0x01, 0x08, 0x00, 0xb2, 0x04, 0x2f,
+0x98, 0x2e, 0x47, 0xcb, 0x10, 0x30, 0x21, 0x2e, 0x19, 0x00, 0x81, 0x30,
+0x01, 0x2e, 0x85, 0x00, 0x01, 0x08, 0x00, 0xb2, 0x04, 0x2f, 0x98, 0x2e,
+0x53, 0xb5, 0x00, 0x30, 0x21, 0x2e, 0xa8, 0x00, 0x00, 0x30, 0x21, 0x2e,
+0x85, 0x00, 0x18, 0x2d, 0x01, 0x2e, 0xa8, 0x00, 0x03, 0xaa, 0x01, 0x2f,
+0x98, 0x2e, 0x60, 0xb5, 0x01, 0x2e, 0xa8, 0x00, 0x3f, 0x80, 0x03, 0xa2,
+0x01, 0x2f, 0x00, 0x2e, 0x02, 0x2d, 0x98, 0x2e, 0x76, 0xb5, 0x30, 0x30,
+0x98, 0x2e, 0xbf, 0x03, 0x00, 0x30, 0x21, 0x2e, 0x86, 0x00, 0x50, 0x32,
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+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
+0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1
+};
+
+BUILD_ASSERT(ARRAY_SIZE(g_bmi220_config_tbin) == 8192);
+const unsigned int g_bmi220_config_tbin_len = ARRAY_SIZE(g_bmi220_config_tbin);
diff --git a/third_party/bmi260/accelgyro_bmi260_config_tbin.h b/third_party/bmi260/accelgyro_bmi260_config_tbin.h
index 11a4a90be5..c38411abff 100644
--- a/third_party/bmi260/accelgyro_bmi260_config_tbin.h
+++ b/third_party/bmi260/accelgyro_bmi260_config_tbin.h
@@ -700,4 +700,3 @@ const unsigned char __init_rom g_bmi260_config_tbin[] = {
 
 BUILD_ASSERT(ARRAY_SIZE(g_bmi260_config_tbin) == 8192);
 const unsigned int g_bmi260_config_tbin_len = ARRAY_SIZE(g_bmi260_config_tbin);
-
diff --git a/third_party/boringssl/LICENSE b/third_party/boringssl/LICENSE
index 49c41fa7af..e9667cb9c2 100644
--- a/third_party/boringssl/LICENSE
+++ b/third_party/boringssl/LICENSE
@@ -142,7 +142,7 @@ record keeping.)
 
 ISC license used for completely new code in BoringSSL:
 
-/* Copyright (c) 2015, Google Inc.
+/* Copyright 2015 Google LLC
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -200,7 +200,7 @@ notice, this list of conditions and the following disclaimer.
 copyright notice, this list of conditions and the following disclaimer
 in the documentation and/or other materials provided with the
 distribution.
-   * Neither the name of Google Inc. nor the names of its
+   * Neither the name of Google LLC nor the names of its
 contributors may be used to endorse or promote products derived from
 this software without specific prior written permission.
 
@@ -222,7 +222,7 @@ trybots etc. The scripts which manage this, and the script for generating build
 metadata, are under the Chromium license. Distributing code linked against
 BoringSSL does not trigger this license.
 
-Copyright 2015 The Chromium Authors. All rights reserved.
+Copyright 2015 The Chromium Authors
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions are
@@ -234,7 +234,7 @@ notice, this list of conditions and the following disclaimer.
 copyright notice, this list of conditions and the following disclaimer
 in the documentation and/or other materials provided with the
 distribution.
-   * Neither the name of Google Inc. nor the names of its
+   * Neither the name of Google LLC nor the names of its
 contributors may be used to endorse or promote products derived from
 this software without specific prior written permission.
 
diff --git a/third_party/boringssl/boringssl-toolchain.cmake b/third_party/boringssl/boringssl-toolchain.cmake
new file mode 100644
index 0000000000..655856fe62
--- /dev/null
+++ b/third_party/boringssl/boringssl-toolchain.cmake
@@ -0,0 +1,24 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+set(CMAKE_BUILD_TYPE Release)
+
+# TODO(b/273639386): Remove these workarounds when the upstream supports
+# better way to disable the filesystem, threads and locks usages.
+set(CMAKE_SYSTEM_NAME Linux)
+
+set(CMAKE_TRY_COMPILE_PLATFORM_VARIABLES CROS_EC_REPO CROSS_COMPILE CC_NAME CXX_NAME)
+include("${CROS_EC_REPO}/cmake/toolchain-common.cmake")
+
+# Pretend as "Trusty", an embedded platform.
+# TODO(b/273639386): Remove these workarounds when the upstream supports
+# better way to disable the filesystem, threads and locks usages.
+add_definitions(-D__TRUSTY__)
+set(ANDROID TRUE)
+
+# TODO(b/287661706): This can be removed once https://crrev.com/c/4610318 lands.
+if (CMAKE_SYSTEM_PROCESSOR STREQUAL armv7)
+    add_compile_options(-mcpu=cortex-m4)
+    add_compile_options(-mfloat-abi=hard)
+endif ()
diff --git a/third_party/boringssl/common/aes-gcm.c b/third_party/boringssl/common/aes-gcm.c
deleted file mode 100644
index edb98b88b3..0000000000
--- a/third_party/boringssl/common/aes-gcm.c
+++ /dev/null
@@ -1,883 +0,0 @@
-/* ====================================================================
- * Copyright (c) 2008 The OpenSSL Project.  All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * 3. All advertising materials mentioning features or use of this
- *    software must display the following acknowledgment:
- *    "This product includes software developed by the OpenSSL Project
- *    for use in the OpenSSL Toolkit. (http://www.openssl.org/)"
- *
- * 4. The names "OpenSSL Toolkit" and "OpenSSL Project" must not be used to
- *    endorse or promote products derived from this software without
- *    prior written permission. For written permission, please contact
- *    openssl-core@openssl.org.
- *
- * 5. Products derived from this software may not be called "OpenSSL"
- *    nor may "OpenSSL" appear in their names without prior written
- *    permission of the OpenSSL Project.
- *
- * 6. Redistributions of any form whatsoever must retain the following
- *    acknowledgment:
- *    "This product includes software developed by the OpenSSL Project
- *    for use in the OpenSSL Toolkit (http://www.openssl.org/)"
- *
- * THIS SOFTWARE IS PROVIDED BY THE OpenSSL PROJECT ``AS IS'' AND ANY
- * EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE OpenSSL PROJECT OR
- * ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
- * OF THE POSSIBILITY OF SUCH DAMAGE.
- * ==================================================================== */
-
-#include "aes-gcm.h"
-#include "common.h"
-#include "endian.h"
-#include "util.h"
-
-#define STRICT_ALIGNMENT 1
-
-#define OPENSSL_memcpy memcpy
-#define OPENSSL_memset memset
-#define CRYPTO_memcmp safe_memcmp
-
-#ifdef CORE_CORTEX_M
-#define GHASH_ASM
-#define OPENSSL_ARM
-#define __ARM_ARCH__ 7
-#endif
-
-static inline uint32_t CRYPTO_bswap4(uint32_t x) {
-  return __builtin_bswap32(x);
-}
-
-static inline uint64_t CRYPTO_bswap8(uint64_t x) {
-  return __builtin_bswap64(x);
-}
-
-static inline size_t load_word_le(const void *in) {
-  size_t v;
-  OPENSSL_memcpy(&v, in, sizeof(v));
-  return v;
-}
-
-static inline void store_word_le(void *out, size_t v) {
-  OPENSSL_memcpy(out, &v, sizeof(v));
-}
-
-#define PACK(s) ((size_t)(s) << (sizeof(size_t) * 8 - 16))
-#define REDUCE1BIT(V)                                                 \
-  do {                                                                \
-    if (sizeof(size_t) == 8) {                                        \
-      uint64_t T = UINT64_C(0xe100000000000000) & (0 - ((V).lo & 1)); \
-      (V).lo = ((V).hi << 63) | ((V).lo >> 1);                        \
-      (V).hi = ((V).hi >> 1) ^ T;                                     \
-    } else {                                                          \
-      uint32_t T = 0xe1000000U & (0 - (uint32_t)((V).lo & 1));        \
-      (V).lo = ((V).hi << 63) | ((V).lo >> 1);                        \
-      (V).hi = ((V).hi >> 1) ^ ((uint64_t)T << 32);                   \
-    }                                                                 \
-  } while (0)
-
-static void gcm_init_4bit(u128 Htable[16], uint64_t H[2]) {
-  u128 V;
-
-  Htable[0].hi = 0;
-  Htable[0].lo = 0;
-  V.hi = H[0];
-  V.lo = H[1];
-
-  Htable[8] = V;
-  REDUCE1BIT(V);
-  Htable[4] = V;
-  REDUCE1BIT(V);
-  Htable[2] = V;
-  REDUCE1BIT(V);
-  Htable[1] = V;
-  Htable[3].hi = V.hi ^ Htable[2].hi, Htable[3].lo = V.lo ^ Htable[2].lo;
-  V = Htable[4];
-  Htable[5].hi = V.hi ^ Htable[1].hi, Htable[5].lo = V.lo ^ Htable[1].lo;
-  Htable[6].hi = V.hi ^ Htable[2].hi, Htable[6].lo = V.lo ^ Htable[2].lo;
-  Htable[7].hi = V.hi ^ Htable[3].hi, Htable[7].lo = V.lo ^ Htable[3].lo;
-  V = Htable[8];
-  Htable[9].hi = V.hi ^ Htable[1].hi, Htable[9].lo = V.lo ^ Htable[1].lo;
-  Htable[10].hi = V.hi ^ Htable[2].hi, Htable[10].lo = V.lo ^ Htable[2].lo;
-  Htable[11].hi = V.hi ^ Htable[3].hi, Htable[11].lo = V.lo ^ Htable[3].lo;
-  Htable[12].hi = V.hi ^ Htable[4].hi, Htable[12].lo = V.lo ^ Htable[4].lo;
-  Htable[13].hi = V.hi ^ Htable[5].hi, Htable[13].lo = V.lo ^ Htable[5].lo;
-  Htable[14].hi = V.hi ^ Htable[6].hi, Htable[14].lo = V.lo ^ Htable[6].lo;
-  Htable[15].hi = V.hi ^ Htable[7].hi, Htable[15].lo = V.lo ^ Htable[7].lo;
-
-#if defined(GHASH_ASM) && defined(OPENSSL_ARM)
-  for (int j = 0; j < 16; ++j) {
-    V = Htable[j];
-    Htable[j].hi = V.lo;
-    Htable[j].lo = V.hi;
-  }
-#endif
-}
-
-#if !defined(GHASH_ASM) || defined(OPENSSL_AARCH64) || defined(OPENSSL_PPC64LE)
-static const size_t rem_4bit[16] = {
-    PACK(0x0000), PACK(0x1C20), PACK(0x3840), PACK(0x2460),
-    PACK(0x7080), PACK(0x6CA0), PACK(0x48C0), PACK(0x54E0),
-    PACK(0xE100), PACK(0xFD20), PACK(0xD940), PACK(0xC560),
-    PACK(0x9180), PACK(0x8DA0), PACK(0xA9C0), PACK(0xB5E0)};
-
-static void gcm_gmult_4bit(uint64_t Xi[2], const u128 Htable[16]) {
-  u128 Z;
-  int cnt = 15;
-  size_t rem, nlo, nhi;
-
-  nlo = ((const uint8_t *)Xi)[15];
-  nhi = nlo >> 4;
-  nlo &= 0xf;
-
-  Z.hi = Htable[nlo].hi;
-  Z.lo = Htable[nlo].lo;
-
-  while (1) {
-    rem = (size_t)Z.lo & 0xf;
-    Z.lo = (Z.hi << 60) | (Z.lo >> 4);
-    Z.hi = (Z.hi >> 4);
-    if (sizeof(size_t) == 8) {
-      Z.hi ^= rem_4bit[rem];
-    } else {
-      Z.hi ^= (uint64_t)rem_4bit[rem] << 32;
-    }
-
-    Z.hi ^= Htable[nhi].hi;
-    Z.lo ^= Htable[nhi].lo;
-
-    if (--cnt < 0) {
-      break;
-    }
-
-    nlo = ((const uint8_t *)Xi)[cnt];
-    nhi = nlo >> 4;
-    nlo &= 0xf;
-
-    rem = (size_t)Z.lo & 0xf;
-    Z.lo = (Z.hi << 60) | (Z.lo >> 4);
-    Z.hi = (Z.hi >> 4);
-    if (sizeof(size_t) == 8) {
-      Z.hi ^= rem_4bit[rem];
-    } else {
-      Z.hi ^= (uint64_t)rem_4bit[rem] << 32;
-    }
-
-    Z.hi ^= Htable[nlo].hi;
-    Z.lo ^= Htable[nlo].lo;
-  }
-
-  Xi[0] = CRYPTO_bswap8(Z.hi);
-  Xi[1] = CRYPTO_bswap8(Z.lo);
-}
-
-// Streamed gcm_mult_4bit, see CRYPTO_gcm128_[en|de]crypt for
-// details... Compiler-generated code doesn't seem to give any
-// performance improvement, at least not on x86[_64]. It's here
-// mostly as reference and a placeholder for possible future
-// non-trivial optimization[s]...
-static void gcm_ghash_4bit(uint64_t Xi[2], const u128 Htable[16],
-                           const uint8_t *inp, size_t len) {
-  u128 Z;
-  int cnt;
-  size_t rem, nlo, nhi;
-
-  do {
-    cnt = 15;
-    nlo = ((const uint8_t *)Xi)[15];
-    nlo ^= inp[15];
-    nhi = nlo >> 4;
-    nlo &= 0xf;
-
-    Z.hi = Htable[nlo].hi;
-    Z.lo = Htable[nlo].lo;
-
-    while (1) {
-      rem = (size_t)Z.lo & 0xf;
-      Z.lo = (Z.hi << 60) | (Z.lo >> 4);
-      Z.hi = (Z.hi >> 4);
-      if (sizeof(size_t) == 8) {
-        Z.hi ^= rem_4bit[rem];
-      } else {
-        Z.hi ^= (uint64_t)rem_4bit[rem] << 32;
-      }
-
-      Z.hi ^= Htable[nhi].hi;
-      Z.lo ^= Htable[nhi].lo;
-
-      if (--cnt < 0) {
-        break;
-      }
-
-      nlo = ((const uint8_t *)Xi)[cnt];
-      nlo ^= inp[cnt];
-      nhi = nlo >> 4;
-      nlo &= 0xf;
-
-      rem = (size_t)Z.lo & 0xf;
-      Z.lo = (Z.hi << 60) | (Z.lo >> 4);
-      Z.hi = (Z.hi >> 4);
-      if (sizeof(size_t) == 8) {
-        Z.hi ^= rem_4bit[rem];
-      } else {
-        Z.hi ^= (uint64_t)rem_4bit[rem] << 32;
-      }
-
-      Z.hi ^= Htable[nlo].hi;
-      Z.lo ^= Htable[nlo].lo;
-    }
-
-    Xi[0] = CRYPTO_bswap8(Z.hi);
-    Xi[1] = CRYPTO_bswap8(Z.lo);
-  } while (inp += 16, len -= 16);
-}
-#else  // GHASH_ASM
-void gcm_gmult_4bit(uint64_t Xi[2], const u128 Htable[16]);
-void gcm_ghash_4bit(uint64_t Xi[2], const u128 Htable[16], const uint8_t *inp,
-                    size_t len);
-#endif
-
-#define GCM_MUL(ctx, Xi) gcm_gmult_4bit((ctx)->Xi.u, (ctx)->Htable)
-#if defined(GHASH_ASM)
-#define GHASH(ctx, in, len) gcm_ghash_4bit((ctx)->Xi.u, (ctx)->Htable, in, len)
-// GHASH_CHUNK is "stride parameter" missioned to mitigate cache
-// trashing effect. In other words idea is to hash data while it's
-// still in L1 cache after encryption pass...
-#define GHASH_CHUNK (3 * 1024)
-#endif
-
-
-#if defined(GHASH_ASM)
-
-#if defined(OPENSSL_X86) || defined(OPENSSL_X86_64)
-#define GCM_FUNCREF_4BIT
-void gcm_init_clmul(u128 Htable[16], const uint64_t Xi[2]);
-void gcm_gmult_clmul(uint64_t Xi[2], const u128 Htable[16]);
-void gcm_ghash_clmul(uint64_t Xi[2], const u128 Htable[16], const uint8_t *inp,
-                     size_t len);
-
-#if defined(OPENSSL_X86_64)
-#define GHASH_ASM_X86_64
-void gcm_init_avx(u128 Htable[16], const uint64_t Xi[2]);
-void gcm_gmult_avx(uint64_t Xi[2], const u128 Htable[16]);
-void gcm_ghash_avx(uint64_t Xi[2], const u128 Htable[16], const uint8_t *in,
-                   size_t len);
-#define AESNI_GCM
-size_t aesni_gcm_encrypt(const uint8_t *in, uint8_t *out, size_t len,
-                         const void *key, uint8_t ivec[16], uint64_t *Xi);
-size_t aesni_gcm_decrypt(const uint8_t *in, uint8_t *out, size_t len,
-                         const void *key, uint8_t ivec[16], uint64_t *Xi);
-#endif
-
-#if defined(OPENSSL_X86)
-#define GHASH_ASM_X86
-void gcm_gmult_4bit_mmx(uint64_t Xi[2], const u128 Htable[16]);
-void gcm_ghash_4bit_mmx(uint64_t Xi[2], const u128 Htable[16], const uint8_t *inp,
-                        size_t len);
-#endif
-
-#elif defined(OPENSSL_ARM) || defined(OPENSSL_AARCH64)
-#if __ARM_ARCH__ >= 7
-#define GHASH_ASM_ARM
-#define GCM_FUNCREF_4BIT
-
-#if defined(OPENSSL_ARM_PMULL)
-static int pmull_capable(void) {
-  return CRYPTO_is_ARMv8_PMULL_capable();
-}
-
-void gcm_init_v8(u128 Htable[16], const uint64_t Xi[2]);
-void gcm_gmult_v8(uint64_t Xi[2], const u128 Htable[16]);
-void gcm_ghash_v8(uint64_t Xi[2], const u128 Htable[16], const uint8_t *inp,
-                  size_t len);
-#else
-static int pmull_capable(void) {
-  return 0;
-}
-static void gcm_init_v8(u128 Htable[16], const uint64_t Xi[2]) {
-
-}
-static void gcm_gmult_v8(uint64_t Xi[2], const u128 Htable[16]) {
-
-}
-static void gcm_ghash_v8(uint64_t Xi[2], const u128 Htable[16],
-                         const uint8_t *inp, size_t len) {
-
-}
-#endif
-
-#if defined(OPENSSL_ARM_NEON)
-// 32-bit ARM also has support for doing GCM with NEON instructions.
-static int neon_capable(void) {
-  return CRYPTO_is_NEON_capable();
-}
-
-void gcm_init_neon(u128 Htable[16], const uint64_t Xi[2]);
-void gcm_gmult_neon(uint64_t Xi[2], const u128 Htable[16]);
-void gcm_ghash_neon(uint64_t Xi[2], const u128 Htable[16], const uint8_t *inp,
-                    size_t len);
-#else
-// AArch64 only has the ARMv8 versions of functions.
-static int neon_capable(void) {
-  return 0;
-}
-static void gcm_init_neon(u128 Htable[16], const uint64_t Xi[2]) {
-
-}
-static void gcm_gmult_neon(uint64_t Xi[2], const u128 Htable[16]) {
-
-}
-static void gcm_ghash_neon(uint64_t Xi[2], const u128 Htable[16],
-                           const uint8_t *inp, size_t len) {
-
-}
-#endif
-
-#endif
-#elif defined(OPENSSL_PPC64LE)
-#define GHASH_ASM_PPC64LE
-#define GCM_FUNCREF_4BIT
-void gcm_init_p8(u128 Htable[16], const uint64_t Xi[2]);
-void gcm_gmult_p8(uint64_t Xi[2], const u128 Htable[16]);
-void gcm_ghash_p8(uint64_t Xi[2], const u128 Htable[16], const uint8_t *inp,
-                  size_t len);
-#endif
-#endif
-
-#ifdef GCM_FUNCREF_4BIT
-#undef GCM_MUL
-#define GCM_MUL(ctx, Xi) (*gcm_gmult_p)((ctx)->Xi.u, (ctx)->Htable)
-#ifdef GHASH
-#undef GHASH
-#define GHASH(ctx, in, len) (*gcm_ghash_p)((ctx)->Xi.u, (ctx)->Htable, in, len)
-#endif
-#endif
-
-#ifdef GHASH
-// kSizeTWithoutLower4Bits is a mask that can be used to zero the lower four
-// bits of a |size_t|.
-static const size_t kSizeTWithoutLower4Bits = (size_t) -16;
-#endif
-
-static void CRYPTO_ghash_init(gmult_func *out_mult, ghash_func *out_hash,
-                              u128 *out_key, u128 out_table[16],
-                              const uint8_t *gcm_key) {
-
-  union {
-    uint64_t u[2];
-    uint8_t c[16];
-  } H;
-
-  OPENSSL_memcpy(H.c, gcm_key, 16);
-
-  // H is stored in host byte order
-  H.u[0] = CRYPTO_bswap8(H.u[0]);
-  H.u[1] = CRYPTO_bswap8(H.u[1]);
-
-  OPENSSL_memcpy(out_key, H.c, 16);
-
-#if defined(GHASH_ASM_X86_64)
-  if (crypto_gcm_clmul_enabled()) {
-    if (((OPENSSL_ia32cap_get()[1] >> 22) & 0x41) == 0x41) {  // AVX+MOVBE
-      gcm_init_avx(out_table, H.u);
-      *out_mult = gcm_gmult_avx;
-      *out_hash = gcm_ghash_avx;
-      *out_is_avx = 1;
-      return;
-    }
-    gcm_init_clmul(out_table, H.u);
-    *out_mult = gcm_gmult_clmul;
-    *out_hash = gcm_ghash_clmul;
-    return;
-  }
-#elif defined(GHASH_ASM_X86)
-  if (crypto_gcm_clmul_enabled()) {
-    gcm_init_clmul(out_table, H.u);
-    *out_mult = gcm_gmult_clmul;
-    *out_hash = gcm_ghash_clmul;
-    return;
-  }
-#elif defined(GHASH_ASM_ARM)
-  if (pmull_capable()) {
-    gcm_init_v8(out_table, H.u);
-    *out_mult = gcm_gmult_v8;
-    *out_hash = gcm_ghash_v8;
-    return;
-  }
-
-  if (neon_capable()) {
-    gcm_init_neon(out_table, H.u);
-    *out_mult = gcm_gmult_neon;
-    *out_hash = gcm_ghash_neon;
-    return;
-  }
-#elif defined(GHASH_ASM_PPC64LE)
-  if (CRYPTO_is_PPC64LE_vcrypto_capable()) {
-    gcm_init_p8(out_table, H.u);
-    *out_mult = gcm_gmult_p8;
-    *out_hash = gcm_ghash_p8;
-    return;
-  }
-#endif
-
-  gcm_init_4bit(out_table, H.u);
-#if defined(GHASH_ASM_X86)
-  *out_mult = gcm_gmult_4bit_mmx;
-  *out_hash = gcm_ghash_4bit_mmx;
-#else
-  *out_mult = gcm_gmult_4bit;
-  *out_hash = gcm_ghash_4bit;
-#endif
-}
-
-void CRYPTO_gcm128_init(GCM128_CONTEXT *ctx, const void *aes_key,
-                        block128_f block, int block_is_hwaes) {
-  OPENSSL_memset(ctx, 0, sizeof(*ctx));
-  ctx->block = block;
-
-  uint8_t gcm_key[16];
-  OPENSSL_memset(gcm_key, 0, sizeof(gcm_key));
-  (*block)(gcm_key, gcm_key, aes_key);
-
-  CRYPTO_ghash_init(&ctx->gmult, &ctx->ghash, &ctx->H, ctx->Htable,
-                    gcm_key);
-}
-
-void CRYPTO_gcm128_setiv(GCM128_CONTEXT *ctx, const void *key,
-                         const uint8_t *iv, size_t len) {
-  unsigned int ctr;
-#ifdef GCM_FUNCREF_4BIT
-  void (*gcm_gmult_p)(uint64_t Xi[2], const u128 Htable[16]) = ctx->gmult;
-#endif
-
-  ctx->Yi.u[0] = 0;
-  ctx->Yi.u[1] = 0;
-  ctx->Xi.u[0] = 0;
-  ctx->Xi.u[1] = 0;
-  ctx->len.u[0] = 0;  // AAD length
-  ctx->len.u[1] = 0;  // message length
-  ctx->ares = 0;
-  ctx->mres = 0;
-
-  if (len == 12) {
-    OPENSSL_memcpy(ctx->Yi.c, iv, 12);
-    ctx->Yi.c[15] = 1;
-    ctr = 1;
-  } else {
-    uint64_t len0 = len;
-
-    while (len >= 16) {
-      for (size_t i = 0; i < 16; ++i) {
-        ctx->Yi.c[i] ^= iv[i];
-      }
-      GCM_MUL(ctx, Yi);
-      iv += 16;
-      len -= 16;
-    }
-    if (len) {
-      for (size_t i = 0; i < len; ++i) {
-        ctx->Yi.c[i] ^= iv[i];
-      }
-      GCM_MUL(ctx, Yi);
-    }
-    len0 <<= 3;
-    ctx->Yi.u[1] ^= CRYPTO_bswap8(len0);
-
-    GCM_MUL(ctx, Yi);
-    ctr = CRYPTO_bswap4(ctx->Yi.d[3]);
-  }
-
-  (*ctx->block)(ctx->Yi.c, ctx->EK0.c, key);
-  ++ctr;
-  ctx->Yi.d[3] = CRYPTO_bswap4(ctr);
-}
-
-int CRYPTO_gcm128_aad(GCM128_CONTEXT *ctx, const uint8_t *aad, size_t len) {
-  unsigned int n;
-  uint64_t alen = ctx->len.u[0];
-#ifdef GCM_FUNCREF_4BIT
-  void (*gcm_gmult_p)(uint64_t Xi[2], const u128 Htable[16]) = ctx->gmult;
-#ifdef GHASH
-  void (*gcm_ghash_p)(uint64_t Xi[2], const u128 Htable[16], const uint8_t *inp,
-                      size_t len) = ctx->ghash;
-#endif
-#endif
-
-  if (ctx->len.u[1]) {
-    return 0;
-  }
-
-  alen += len;
-  if (alen > (UINT64_C(1) << 61) || (sizeof(len) == 8 && alen < len)) {
-    return 0;
-  }
-  ctx->len.u[0] = alen;
-
-  n = ctx->ares;
-  if (n) {
-    while (n && len) {
-      ctx->Xi.c[n] ^= *(aad++);
-      --len;
-      n = (n + 1) % 16;
-    }
-    if (n == 0) {
-      GCM_MUL(ctx, Xi);
-    } else {
-      ctx->ares = n;
-      return 1;
-    }
-  }
-
-  // Process a whole number of blocks.
-#ifdef GHASH
-  size_t len_blocks = len & kSizeTWithoutLower4Bits;
-  if (len_blocks != 0) {
-    GHASH(ctx, aad, len_blocks);
-    aad += len_blocks;
-    len -= len_blocks;
-  }
-#else
-  while (len >= 16) {
-    for (size_t i = 0; i < 16; ++i) {
-      ctx->Xi.c[i] ^= aad[i];
-    }
-    GCM_MUL(ctx, Xi);
-    aad += 16;
-    len -= 16;
-  }
-#endif
-
-  // Process the remainder.
-  if (len != 0) {
-    n = (unsigned int)len;
-    for (size_t i = 0; i < len; ++i) {
-      ctx->Xi.c[i] ^= aad[i];
-    }
-  }
-
-  ctx->ares = n;
-  return 1;
-}
-
-int CRYPTO_gcm128_encrypt(GCM128_CONTEXT *ctx, const void *key,
-                          const uint8_t *in, uint8_t *out, size_t len) {
-  unsigned int n, ctr;
-  uint64_t mlen = ctx->len.u[1];
-  block128_f block = ctx->block;
-#ifdef GCM_FUNCREF_4BIT
-  void (*gcm_gmult_p)(uint64_t Xi[2], const u128 Htable[16]) = ctx->gmult;
-#ifdef GHASH
-  void (*gcm_ghash_p)(uint64_t Xi[2], const u128 Htable[16], const uint8_t *inp,
-                      size_t len) = ctx->ghash;
-#endif
-#endif
-
-  mlen += len;
-  if (mlen > ((UINT64_C(1) << 36) - 32) ||
-      (sizeof(len) == 8 && mlen < len)) {
-    return 0;
-  }
-  ctx->len.u[1] = mlen;
-
-  if (ctx->ares) {
-    // First call to encrypt finalizes GHASH(AAD)
-    GCM_MUL(ctx, Xi);
-    ctx->ares = 0;
-  }
-
-  ctr = CRYPTO_bswap4(ctx->Yi.d[3]);
-
-  n = ctx->mres;
-  if (n) {
-    while (n && len) {
-      ctx->Xi.c[n] ^= *(out++) = *(in++) ^ ctx->EKi.c[n];
-      --len;
-      n = (n + 1) % 16;
-    }
-    if (n == 0) {
-      GCM_MUL(ctx, Xi);
-    } else {
-      ctx->mres = n;
-      return 1;
-    }
-  }
-  if (STRICT_ALIGNMENT &&
-      ((uintptr_t)in | (uintptr_t)out) % sizeof(size_t) != 0) {
-    for (size_t i = 0; i < len; ++i) {
-      if (n == 0) {
-        (*block)(ctx->Yi.c, ctx->EKi.c, key);
-        ++ctr;
-        ctx->Yi.d[3] = CRYPTO_bswap4(ctr);
-      }
-      ctx->Xi.c[n] ^= out[i] = in[i] ^ ctx->EKi.c[n];
-      n = (n + 1) % 16;
-      if (n == 0) {
-        GCM_MUL(ctx, Xi);
-      }
-    }
-
-    ctx->mres = n;
-    return 1;
-  }
-#if defined(GHASH) && defined(GHASH_CHUNK)
-  while (len >= GHASH_CHUNK) {
-    size_t j = GHASH_CHUNK;
-
-    while (j) {
-      (*block)(ctx->Yi.c, ctx->EKi.c, key);
-      ++ctr;
-      ctx->Yi.d[3] = CRYPTO_bswap4(ctr);
-      for (size_t i = 0; i < 16; i += sizeof(size_t)) {
-        store_word_le(out + i,
-                      load_word_le(in + i) ^ ctx->EKi.t[i / sizeof(size_t)]);
-      }
-      out += 16;
-      in += 16;
-      j -= 16;
-    }
-    GHASH(ctx, out - GHASH_CHUNK, GHASH_CHUNK);
-    len -= GHASH_CHUNK;
-  }
-  size_t len_blocks = len & kSizeTWithoutLower4Bits;
-  if (len_blocks != 0) {
-    while (len >= 16) {
-      (*block)(ctx->Yi.c, ctx->EKi.c, key);
-      ++ctr;
-      ctx->Yi.d[3] = CRYPTO_bswap4(ctr);
-      for (size_t i = 0; i < 16; i += sizeof(size_t)) {
-        store_word_le(out + i,
-                      load_word_le(in + i) ^ ctx->EKi.t[i / sizeof(size_t)]);
-      }
-      out += 16;
-      in += 16;
-      len -= 16;
-    }
-    GHASH(ctx, out - len_blocks, len_blocks);
-  }
-#else
-  while (len >= 16) {
-    (*block)(ctx->Yi.c, ctx->EKi.c, key);
-    ++ctr;
-    ctx->Yi.d[3] = CRYPTO_bswap4(ctr);
-    for (size_t i = 0; i < 16; i += sizeof(size_t)) {
-      size_t tmp = load_word_le(in + i) ^ ctx->EKi.t[i / sizeof(size_t)];
-      store_word_le(out + i, tmp);
-      ctx->Xi.t[i / sizeof(size_t)] ^= tmp;
-    }
-    GCM_MUL(ctx, Xi);
-    out += 16;
-    in += 16;
-    len -= 16;
-  }
-#endif
-  if (len) {
-    (*block)(ctx->Yi.c, ctx->EKi.c, key);
-    ++ctr;
-    ctx->Yi.d[3] = CRYPTO_bswap4(ctr);
-    while (len--) {
-      ctx->Xi.c[n] ^= out[n] = in[n] ^ ctx->EKi.c[n];
-      ++n;
-    }
-  }
-
-  ctx->mres = n;
-  return 1;
-}
-
-int CRYPTO_gcm128_decrypt(GCM128_CONTEXT *ctx, const void *key,
-                          const unsigned char *in, unsigned char *out,
-                          size_t len) {
-  unsigned int n, ctr;
-  uint64_t mlen = ctx->len.u[1];
-  block128_f block = ctx->block;
-#ifdef GCM_FUNCREF_4BIT
-  void (*gcm_gmult_p)(uint64_t Xi[2], const u128 Htable[16]) = ctx->gmult;
-#ifdef GHASH
-  void (*gcm_ghash_p)(uint64_t Xi[2], const u128 Htable[16], const uint8_t *inp,
-                      size_t len) = ctx->ghash;
-#endif
-#endif
-
-  mlen += len;
-  if (mlen > ((UINT64_C(1) << 36) - 32) ||
-      (sizeof(len) == 8 && mlen < len)) {
-    return 0;
-  }
-  ctx->len.u[1] = mlen;
-
-  if (ctx->ares) {
-    // First call to decrypt finalizes GHASH(AAD)
-    GCM_MUL(ctx, Xi);
-    ctx->ares = 0;
-  }
-
-  ctr = CRYPTO_bswap4(ctx->Yi.d[3]);
-
-  n = ctx->mres;
-  if (n) {
-    while (n && len) {
-      uint8_t c = *(in++);
-      *(out++) = c ^ ctx->EKi.c[n];
-      ctx->Xi.c[n] ^= c;
-      --len;
-      n = (n + 1) % 16;
-    }
-    if (n == 0) {
-      GCM_MUL(ctx, Xi);
-    } else {
-      ctx->mres = n;
-      return 1;
-    }
-  }
-  if (STRICT_ALIGNMENT &&
-      ((uintptr_t)in | (uintptr_t)out) % sizeof(size_t) != 0) {
-    for (size_t i = 0; i < len; ++i) {
-      uint8_t c;
-      if (n == 0) {
-        (*block)(ctx->Yi.c, ctx->EKi.c, key);
-        ++ctr;
-        ctx->Yi.d[3] = CRYPTO_bswap4(ctr);
-      }
-      c = in[i];
-      out[i] = c ^ ctx->EKi.c[n];
-      ctx->Xi.c[n] ^= c;
-      n = (n + 1) % 16;
-      if (n == 0) {
-        GCM_MUL(ctx, Xi);
-      }
-    }
-
-    ctx->mres = n;
-    return 1;
-  }
-#if defined(GHASH) && defined(GHASH_CHUNK)
-  while (len >= GHASH_CHUNK) {
-    size_t j = GHASH_CHUNK;
-
-    GHASH(ctx, in, GHASH_CHUNK);
-    while (j) {
-      (*block)(ctx->Yi.c, ctx->EKi.c, key);
-      ++ctr;
-      ctx->Yi.d[3] = CRYPTO_bswap4(ctr);
-      for (size_t i = 0; i < 16; i += sizeof(size_t)) {
-        store_word_le(out + i,
-                      load_word_le(in + i) ^ ctx->EKi.t[i / sizeof(size_t)]);
-      }
-      out += 16;
-      in += 16;
-      j -= 16;
-    }
-    len -= GHASH_CHUNK;
-  }
-  size_t len_blocks = len & kSizeTWithoutLower4Bits;
-  if (len_blocks != 0) {
-    GHASH(ctx, in, len_blocks);
-    while (len >= 16) {
-      (*block)(ctx->Yi.c, ctx->EKi.c, key);
-      ++ctr;
-      ctx->Yi.d[3] = CRYPTO_bswap4(ctr);
-      for (size_t i = 0; i < 16; i += sizeof(size_t)) {
-        store_word_le(out + i,
-                      load_word_le(in + i) ^ ctx->EKi.t[i / sizeof(size_t)]);
-      }
-      out += 16;
-      in += 16;
-      len -= 16;
-    }
-  }
-#else
-  while (len >= 16) {
-    (*block)(ctx->Yi.c, ctx->EKi.c, key);
-    ++ctr;
-    ctx->Yi.d[3] = CRYPTO_bswap4(ctr);
-    for (size_t i = 0; i < 16; i += sizeof(size_t)) {
-      size_t c = load_word_le(in + i);
-      store_word_le(out + i, c ^ ctx->EKi.t[i / sizeof(size_t)]);
-      ctx->Xi.t[i / sizeof(size_t)] ^= c;
-    }
-    GCM_MUL(ctx, Xi);
-    out += 16;
-    in += 16;
-    len -= 16;
-  }
-#endif
-  if (len) {
-    (*block)(ctx->Yi.c, ctx->EKi.c, key);
-    ++ctr;
-    ctx->Yi.d[3] = CRYPTO_bswap4(ctr);
-    while (len--) {
-      uint8_t c = in[n];
-      ctx->Xi.c[n] ^= c;
-      out[n] = c ^ ctx->EKi.c[n];
-      ++n;
-    }
-  }
-
-  ctx->mres = n;
-  return 1;
-}
-
-int CRYPTO_gcm128_finish(GCM128_CONTEXT *ctx, const uint8_t *tag, size_t len) {
-  uint64_t alen = ctx->len.u[0] << 3;
-  uint64_t clen = ctx->len.u[1] << 3;
-#ifdef GCM_FUNCREF_4BIT
-  void (*gcm_gmult_p)(uint64_t Xi[2], const u128 Htable[16]) = ctx->gmult;
-#endif
-
-  if (ctx->mres || ctx->ares) {
-    GCM_MUL(ctx, Xi);
-  }
-
-  alen = CRYPTO_bswap8(alen);
-  clen = CRYPTO_bswap8(clen);
-
-  ctx->Xi.u[0] ^= alen;
-  ctx->Xi.u[1] ^= clen;
-  GCM_MUL(ctx, Xi);
-
-  ctx->Xi.u[0] ^= ctx->EK0.u[0];
-  ctx->Xi.u[1] ^= ctx->EK0.u[1];
-
-  if (tag && len <= sizeof(ctx->Xi)) {
-    return CRYPTO_memcmp(ctx->Xi.c, tag, len) == 0;
-  } else {
-    return 0;
-  }
-}
-
-void CRYPTO_gcm128_tag(GCM128_CONTEXT *ctx, unsigned char *tag, size_t len) {
-  CRYPTO_gcm128_finish(ctx, NULL, 0);
-  OPENSSL_memcpy(tag, ctx->Xi.c,
-                 len <= sizeof(ctx->Xi.c) ? len : sizeof(ctx->Xi.c));
-}
-
-#if defined(OPENSSL_X86) || defined(OPENSSL_X86_64)
-int crypto_gcm_clmul_enabled(void) {
-#ifdef GHASH_ASM
-  const uint32_t *ia32cap = OPENSSL_ia32cap_get();
-  return (ia32cap[0] & (1 << 24)) &&  // check FXSR bit
-         (ia32cap[1] & (1 << 1));     // check PCLMULQDQ bit
-#else
-  return 0;
-#endif
-}
-#endif
diff --git a/third_party/boringssl/common/aes.c b/third_party/boringssl/common/aes.c
deleted file mode 100644
index aa213eb907..0000000000
--- a/third_party/boringssl/common/aes.c
+++ /dev/null
@@ -1,806 +0,0 @@
-/* ====================================================================
- * Copyright (c) 2002-2006 The OpenSSL Project.  All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * 3. All advertising materials mentioning features or use of this
- *    software must display the following acknowledgment:
- *    "This product includes software developed by the OpenSSL Project
- *    for use in the OpenSSL Toolkit. (http://www.openssl.org/)"
- *
- * 4. The names "OpenSSL Toolkit" and "OpenSSL Project" must not be used to
- *    endorse or promote products derived from this software without
- *    prior written permission. For written permission, please contact
- *    openssl-core@openssl.org.
- *
- * 5. Products derived from this software may not be called "OpenSSL"
- *    nor may "OpenSSL" appear in their names without prior written
- *    permission of the OpenSSL Project.
- *
- * 6. Redistributions of any form whatsoever must retain the following
- *    acknowledgment:
- *    "This product includes software developed by the OpenSSL Project
- *    for use in the OpenSSL Toolkit (http://www.openssl.org/)"
- *
- * THIS SOFTWARE IS PROVIDED BY THE OpenSSL PROJECT ``AS IS'' AND ANY
- * EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE OpenSSL PROJECT OR
- * ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
- * OF THE POSSIBILITY OF SUCH DAMAGE.
- * ==================================================================== */
-
-#include "aes.h"
-#include "common.h"
-#include "endian.h"
-
-static inline uint32_t GETU32(const void *in) {
-  return be32toh(*(uint32_t *)in);
-}
-
-static inline void PUTU32(void *out, uint32_t v) {
-  *(uint32_t *)out = htobe32(v);
-}
-
-// Te0[x] = S [x].[02, 01, 01, 03];
-// Te1[x] = S [x].[03, 02, 01, 01];
-// Te2[x] = S [x].[01, 03, 02, 01];
-// Te3[x] = S [x].[01, 01, 03, 02];
-//
-// Td0[x] = Si[x].[0e, 09, 0d, 0b];
-// Td1[x] = Si[x].[0b, 0e, 09, 0d];
-// Td2[x] = Si[x].[0d, 0b, 0e, 09];
-// Td3[x] = Si[x].[09, 0d, 0b, 0e];
-// Td4[x] = Si[x].[01];
-
-static const uint32_t Te0[256] = {
-    0xc66363a5U, 0xf87c7c84U, 0xee777799U, 0xf67b7b8dU, 0xfff2f20dU,
-    0xd66b6bbdU, 0xde6f6fb1U, 0x91c5c554U, 0x60303050U, 0x02010103U,
-    0xce6767a9U, 0x562b2b7dU, 0xe7fefe19U, 0xb5d7d762U, 0x4dababe6U,
-    0xec76769aU, 0x8fcaca45U, 0x1f82829dU, 0x89c9c940U, 0xfa7d7d87U,
-    0xeffafa15U, 0xb25959ebU, 0x8e4747c9U, 0xfbf0f00bU, 0x41adadecU,
-    0xb3d4d467U, 0x5fa2a2fdU, 0x45afafeaU, 0x239c9cbfU, 0x53a4a4f7U,
-    0xe4727296U, 0x9bc0c05bU, 0x75b7b7c2U, 0xe1fdfd1cU, 0x3d9393aeU,
-    0x4c26266aU, 0x6c36365aU, 0x7e3f3f41U, 0xf5f7f702U, 0x83cccc4fU,
-    0x6834345cU, 0x51a5a5f4U, 0xd1e5e534U, 0xf9f1f108U, 0xe2717193U,
-    0xabd8d873U, 0x62313153U, 0x2a15153fU, 0x0804040cU, 0x95c7c752U,
-    0x46232365U, 0x9dc3c35eU, 0x30181828U, 0x379696a1U, 0x0a05050fU,
-    0x2f9a9ab5U, 0x0e070709U, 0x24121236U, 0x1b80809bU, 0xdfe2e23dU,
-    0xcdebeb26U, 0x4e272769U, 0x7fb2b2cdU, 0xea75759fU, 0x1209091bU,
-    0x1d83839eU, 0x582c2c74U, 0x341a1a2eU, 0x361b1b2dU, 0xdc6e6eb2U,
-    0xb45a5aeeU, 0x5ba0a0fbU, 0xa45252f6U, 0x763b3b4dU, 0xb7d6d661U,
-    0x7db3b3ceU, 0x5229297bU, 0xdde3e33eU, 0x5e2f2f71U, 0x13848497U,
-    0xa65353f5U, 0xb9d1d168U, 0x00000000U, 0xc1eded2cU, 0x40202060U,
-    0xe3fcfc1fU, 0x79b1b1c8U, 0xb65b5bedU, 0xd46a6abeU, 0x8dcbcb46U,
-    0x67bebed9U, 0x7239394bU, 0x944a4adeU, 0x984c4cd4U, 0xb05858e8U,
-    0x85cfcf4aU, 0xbbd0d06bU, 0xc5efef2aU, 0x4faaaae5U, 0xedfbfb16U,
-    0x864343c5U, 0x9a4d4dd7U, 0x66333355U, 0x11858594U, 0x8a4545cfU,
-    0xe9f9f910U, 0x04020206U, 0xfe7f7f81U, 0xa05050f0U, 0x783c3c44U,
-    0x259f9fbaU, 0x4ba8a8e3U, 0xa25151f3U, 0x5da3a3feU, 0x804040c0U,
-    0x058f8f8aU, 0x3f9292adU, 0x219d9dbcU, 0x70383848U, 0xf1f5f504U,
-    0x63bcbcdfU, 0x77b6b6c1U, 0xafdada75U, 0x42212163U, 0x20101030U,
-    0xe5ffff1aU, 0xfdf3f30eU, 0xbfd2d26dU, 0x81cdcd4cU, 0x180c0c14U,
-    0x26131335U, 0xc3ecec2fU, 0xbe5f5fe1U, 0x359797a2U, 0x884444ccU,
-    0x2e171739U, 0x93c4c457U, 0x55a7a7f2U, 0xfc7e7e82U, 0x7a3d3d47U,
-    0xc86464acU, 0xba5d5de7U, 0x3219192bU, 0xe6737395U, 0xc06060a0U,
-    0x19818198U, 0x9e4f4fd1U, 0xa3dcdc7fU, 0x44222266U, 0x542a2a7eU,
-    0x3b9090abU, 0x0b888883U, 0x8c4646caU, 0xc7eeee29U, 0x6bb8b8d3U,
-    0x2814143cU, 0xa7dede79U, 0xbc5e5ee2U, 0x160b0b1dU, 0xaddbdb76U,
-    0xdbe0e03bU, 0x64323256U, 0x743a3a4eU, 0x140a0a1eU, 0x924949dbU,
-    0x0c06060aU, 0x4824246cU, 0xb85c5ce4U, 0x9fc2c25dU, 0xbdd3d36eU,
-    0x43acacefU, 0xc46262a6U, 0x399191a8U, 0x319595a4U, 0xd3e4e437U,
-    0xf279798bU, 0xd5e7e732U, 0x8bc8c843U, 0x6e373759U, 0xda6d6db7U,
-    0x018d8d8cU, 0xb1d5d564U, 0x9c4e4ed2U, 0x49a9a9e0U, 0xd86c6cb4U,
-    0xac5656faU, 0xf3f4f407U, 0xcfeaea25U, 0xca6565afU, 0xf47a7a8eU,
-    0x47aeaee9U, 0x10080818U, 0x6fbabad5U, 0xf0787888U, 0x4a25256fU,
-    0x5c2e2e72U, 0x381c1c24U, 0x57a6a6f1U, 0x73b4b4c7U, 0x97c6c651U,
-    0xcbe8e823U, 0xa1dddd7cU, 0xe874749cU, 0x3e1f1f21U, 0x964b4bddU,
-    0x61bdbddcU, 0x0d8b8b86U, 0x0f8a8a85U, 0xe0707090U, 0x7c3e3e42U,
-    0x71b5b5c4U, 0xcc6666aaU, 0x904848d8U, 0x06030305U, 0xf7f6f601U,
-    0x1c0e0e12U, 0xc26161a3U, 0x6a35355fU, 0xae5757f9U, 0x69b9b9d0U,
-    0x17868691U, 0x99c1c158U, 0x3a1d1d27U, 0x279e9eb9U, 0xd9e1e138U,
-    0xebf8f813U, 0x2b9898b3U, 0x22111133U, 0xd26969bbU, 0xa9d9d970U,
-    0x078e8e89U, 0x339494a7U, 0x2d9b9bb6U, 0x3c1e1e22U, 0x15878792U,
-    0xc9e9e920U, 0x87cece49U, 0xaa5555ffU, 0x50282878U, 0xa5dfdf7aU,
-    0x038c8c8fU, 0x59a1a1f8U, 0x09898980U, 0x1a0d0d17U, 0x65bfbfdaU,
-    0xd7e6e631U, 0x844242c6U, 0xd06868b8U, 0x824141c3U, 0x299999b0U,
-    0x5a2d2d77U, 0x1e0f0f11U, 0x7bb0b0cbU, 0xa85454fcU, 0x6dbbbbd6U,
-    0x2c16163aU, };
-
-static const uint32_t Te1[256] = {
-    0xa5c66363U, 0x84f87c7cU, 0x99ee7777U, 0x8df67b7bU, 0x0dfff2f2U,
-    0xbdd66b6bU, 0xb1de6f6fU, 0x5491c5c5U, 0x50603030U, 0x03020101U,
-    0xa9ce6767U, 0x7d562b2bU, 0x19e7fefeU, 0x62b5d7d7U, 0xe64dababU,
-    0x9aec7676U, 0x458fcacaU, 0x9d1f8282U, 0x4089c9c9U, 0x87fa7d7dU,
-    0x15effafaU, 0xebb25959U, 0xc98e4747U, 0x0bfbf0f0U, 0xec41adadU,
-    0x67b3d4d4U, 0xfd5fa2a2U, 0xea45afafU, 0xbf239c9cU, 0xf753a4a4U,
-    0x96e47272U, 0x5b9bc0c0U, 0xc275b7b7U, 0x1ce1fdfdU, 0xae3d9393U,
-    0x6a4c2626U, 0x5a6c3636U, 0x417e3f3fU, 0x02f5f7f7U, 0x4f83ccccU,
-    0x5c683434U, 0xf451a5a5U, 0x34d1e5e5U, 0x08f9f1f1U, 0x93e27171U,
-    0x73abd8d8U, 0x53623131U, 0x3f2a1515U, 0x0c080404U, 0x5295c7c7U,
-    0x65462323U, 0x5e9dc3c3U, 0x28301818U, 0xa1379696U, 0x0f0a0505U,
-    0xb52f9a9aU, 0x090e0707U, 0x36241212U, 0x9b1b8080U, 0x3ddfe2e2U,
-    0x26cdebebU, 0x694e2727U, 0xcd7fb2b2U, 0x9fea7575U, 0x1b120909U,
-    0x9e1d8383U, 0x74582c2cU, 0x2e341a1aU, 0x2d361b1bU, 0xb2dc6e6eU,
-    0xeeb45a5aU, 0xfb5ba0a0U, 0xf6a45252U, 0x4d763b3bU, 0x61b7d6d6U,
-    0xce7db3b3U, 0x7b522929U, 0x3edde3e3U, 0x715e2f2fU, 0x97138484U,
-    0xf5a65353U, 0x68b9d1d1U, 0x00000000U, 0x2cc1ededU, 0x60402020U,
-    0x1fe3fcfcU, 0xc879b1b1U, 0xedb65b5bU, 0xbed46a6aU, 0x468dcbcbU,
-    0xd967bebeU, 0x4b723939U, 0xde944a4aU, 0xd4984c4cU, 0xe8b05858U,
-    0x4a85cfcfU, 0x6bbbd0d0U, 0x2ac5efefU, 0xe54faaaaU, 0x16edfbfbU,
-    0xc5864343U, 0xd79a4d4dU, 0x55663333U, 0x94118585U, 0xcf8a4545U,
-    0x10e9f9f9U, 0x06040202U, 0x81fe7f7fU, 0xf0a05050U, 0x44783c3cU,
-    0xba259f9fU, 0xe34ba8a8U, 0xf3a25151U, 0xfe5da3a3U, 0xc0804040U,
-    0x8a058f8fU, 0xad3f9292U, 0xbc219d9dU, 0x48703838U, 0x04f1f5f5U,
-    0xdf63bcbcU, 0xc177b6b6U, 0x75afdadaU, 0x63422121U, 0x30201010U,
-    0x1ae5ffffU, 0x0efdf3f3U, 0x6dbfd2d2U, 0x4c81cdcdU, 0x14180c0cU,
-    0x35261313U, 0x2fc3ececU, 0xe1be5f5fU, 0xa2359797U, 0xcc884444U,
-    0x392e1717U, 0x5793c4c4U, 0xf255a7a7U, 0x82fc7e7eU, 0x477a3d3dU,
-    0xacc86464U, 0xe7ba5d5dU, 0x2b321919U, 0x95e67373U, 0xa0c06060U,
-    0x98198181U, 0xd19e4f4fU, 0x7fa3dcdcU, 0x66442222U, 0x7e542a2aU,
-    0xab3b9090U, 0x830b8888U, 0xca8c4646U, 0x29c7eeeeU, 0xd36bb8b8U,
-    0x3c281414U, 0x79a7dedeU, 0xe2bc5e5eU, 0x1d160b0bU, 0x76addbdbU,
-    0x3bdbe0e0U, 0x56643232U, 0x4e743a3aU, 0x1e140a0aU, 0xdb924949U,
-    0x0a0c0606U, 0x6c482424U, 0xe4b85c5cU, 0x5d9fc2c2U, 0x6ebdd3d3U,
-    0xef43acacU, 0xa6c46262U, 0xa8399191U, 0xa4319595U, 0x37d3e4e4U,
-    0x8bf27979U, 0x32d5e7e7U, 0x438bc8c8U, 0x596e3737U, 0xb7da6d6dU,
-    0x8c018d8dU, 0x64b1d5d5U, 0xd29c4e4eU, 0xe049a9a9U, 0xb4d86c6cU,
-    0xfaac5656U, 0x07f3f4f4U, 0x25cfeaeaU, 0xafca6565U, 0x8ef47a7aU,
-    0xe947aeaeU, 0x18100808U, 0xd56fbabaU, 0x88f07878U, 0x6f4a2525U,
-    0x725c2e2eU, 0x24381c1cU, 0xf157a6a6U, 0xc773b4b4U, 0x5197c6c6U,
-    0x23cbe8e8U, 0x7ca1ddddU, 0x9ce87474U, 0x213e1f1fU, 0xdd964b4bU,
-    0xdc61bdbdU, 0x860d8b8bU, 0x850f8a8aU, 0x90e07070U, 0x427c3e3eU,
-    0xc471b5b5U, 0xaacc6666U, 0xd8904848U, 0x05060303U, 0x01f7f6f6U,
-    0x121c0e0eU, 0xa3c26161U, 0x5f6a3535U, 0xf9ae5757U, 0xd069b9b9U,
-    0x91178686U, 0x5899c1c1U, 0x273a1d1dU, 0xb9279e9eU, 0x38d9e1e1U,
-    0x13ebf8f8U, 0xb32b9898U, 0x33221111U, 0xbbd26969U, 0x70a9d9d9U,
-    0x89078e8eU, 0xa7339494U, 0xb62d9b9bU, 0x223c1e1eU, 0x92158787U,
-    0x20c9e9e9U, 0x4987ceceU, 0xffaa5555U, 0x78502828U, 0x7aa5dfdfU,
-    0x8f038c8cU, 0xf859a1a1U, 0x80098989U, 0x171a0d0dU, 0xda65bfbfU,
-    0x31d7e6e6U, 0xc6844242U, 0xb8d06868U, 0xc3824141U, 0xb0299999U,
-    0x775a2d2dU, 0x111e0f0fU, 0xcb7bb0b0U, 0xfca85454U, 0xd66dbbbbU,
-    0x3a2c1616U, };
-
-static const uint32_t Te2[256] = {
-    0x63a5c663U, 0x7c84f87cU, 0x7799ee77U, 0x7b8df67bU, 0xf20dfff2U,
-    0x6bbdd66bU, 0x6fb1de6fU, 0xc55491c5U, 0x30506030U, 0x01030201U,
-    0x67a9ce67U, 0x2b7d562bU, 0xfe19e7feU, 0xd762b5d7U, 0xabe64dabU,
-    0x769aec76U, 0xca458fcaU, 0x829d1f82U, 0xc94089c9U, 0x7d87fa7dU,
-    0xfa15effaU, 0x59ebb259U, 0x47c98e47U, 0xf00bfbf0U, 0xadec41adU,
-    0xd467b3d4U, 0xa2fd5fa2U, 0xafea45afU, 0x9cbf239cU, 0xa4f753a4U,
-    0x7296e472U, 0xc05b9bc0U, 0xb7c275b7U, 0xfd1ce1fdU, 0x93ae3d93U,
-    0x266a4c26U, 0x365a6c36U, 0x3f417e3fU, 0xf702f5f7U, 0xcc4f83ccU,
-    0x345c6834U, 0xa5f451a5U, 0xe534d1e5U, 0xf108f9f1U, 0x7193e271U,
-    0xd873abd8U, 0x31536231U, 0x153f2a15U, 0x040c0804U, 0xc75295c7U,
-    0x23654623U, 0xc35e9dc3U, 0x18283018U, 0x96a13796U, 0x050f0a05U,
-    0x9ab52f9aU, 0x07090e07U, 0x12362412U, 0x809b1b80U, 0xe23ddfe2U,
-    0xeb26cdebU, 0x27694e27U, 0xb2cd7fb2U, 0x759fea75U, 0x091b1209U,
-    0x839e1d83U, 0x2c74582cU, 0x1a2e341aU, 0x1b2d361bU, 0x6eb2dc6eU,
-    0x5aeeb45aU, 0xa0fb5ba0U, 0x52f6a452U, 0x3b4d763bU, 0xd661b7d6U,
-    0xb3ce7db3U, 0x297b5229U, 0xe33edde3U, 0x2f715e2fU, 0x84971384U,
-    0x53f5a653U, 0xd168b9d1U, 0x00000000U, 0xed2cc1edU, 0x20604020U,
-    0xfc1fe3fcU, 0xb1c879b1U, 0x5bedb65bU, 0x6abed46aU, 0xcb468dcbU,
-    0xbed967beU, 0x394b7239U, 0x4ade944aU, 0x4cd4984cU, 0x58e8b058U,
-    0xcf4a85cfU, 0xd06bbbd0U, 0xef2ac5efU, 0xaae54faaU, 0xfb16edfbU,
-    0x43c58643U, 0x4dd79a4dU, 0x33556633U, 0x85941185U, 0x45cf8a45U,
-    0xf910e9f9U, 0x02060402U, 0x7f81fe7fU, 0x50f0a050U, 0x3c44783cU,
-    0x9fba259fU, 0xa8e34ba8U, 0x51f3a251U, 0xa3fe5da3U, 0x40c08040U,
-    0x8f8a058fU, 0x92ad3f92U, 0x9dbc219dU, 0x38487038U, 0xf504f1f5U,
-    0xbcdf63bcU, 0xb6c177b6U, 0xda75afdaU, 0x21634221U, 0x10302010U,
-    0xff1ae5ffU, 0xf30efdf3U, 0xd26dbfd2U, 0xcd4c81cdU, 0x0c14180cU,
-    0x13352613U, 0xec2fc3ecU, 0x5fe1be5fU, 0x97a23597U, 0x44cc8844U,
-    0x17392e17U, 0xc45793c4U, 0xa7f255a7U, 0x7e82fc7eU, 0x3d477a3dU,
-    0x64acc864U, 0x5de7ba5dU, 0x192b3219U, 0x7395e673U, 0x60a0c060U,
-    0x81981981U, 0x4fd19e4fU, 0xdc7fa3dcU, 0x22664422U, 0x2a7e542aU,
-    0x90ab3b90U, 0x88830b88U, 0x46ca8c46U, 0xee29c7eeU, 0xb8d36bb8U,
-    0x143c2814U, 0xde79a7deU, 0x5ee2bc5eU, 0x0b1d160bU, 0xdb76addbU,
-    0xe03bdbe0U, 0x32566432U, 0x3a4e743aU, 0x0a1e140aU, 0x49db9249U,
-    0x060a0c06U, 0x246c4824U, 0x5ce4b85cU, 0xc25d9fc2U, 0xd36ebdd3U,
-    0xacef43acU, 0x62a6c462U, 0x91a83991U, 0x95a43195U, 0xe437d3e4U,
-    0x798bf279U, 0xe732d5e7U, 0xc8438bc8U, 0x37596e37U, 0x6db7da6dU,
-    0x8d8c018dU, 0xd564b1d5U, 0x4ed29c4eU, 0xa9e049a9U, 0x6cb4d86cU,
-    0x56faac56U, 0xf407f3f4U, 0xea25cfeaU, 0x65afca65U, 0x7a8ef47aU,
-    0xaee947aeU, 0x08181008U, 0xbad56fbaU, 0x7888f078U, 0x256f4a25U,
-    0x2e725c2eU, 0x1c24381cU, 0xa6f157a6U, 0xb4c773b4U, 0xc65197c6U,
-    0xe823cbe8U, 0xdd7ca1ddU, 0x749ce874U, 0x1f213e1fU, 0x4bdd964bU,
-    0xbddc61bdU, 0x8b860d8bU, 0x8a850f8aU, 0x7090e070U, 0x3e427c3eU,
-    0xb5c471b5U, 0x66aacc66U, 0x48d89048U, 0x03050603U, 0xf601f7f6U,
-    0x0e121c0eU, 0x61a3c261U, 0x355f6a35U, 0x57f9ae57U, 0xb9d069b9U,
-    0x86911786U, 0xc15899c1U, 0x1d273a1dU, 0x9eb9279eU, 0xe138d9e1U,
-    0xf813ebf8U, 0x98b32b98U, 0x11332211U, 0x69bbd269U, 0xd970a9d9U,
-    0x8e89078eU, 0x94a73394U, 0x9bb62d9bU, 0x1e223c1eU, 0x87921587U,
-    0xe920c9e9U, 0xce4987ceU, 0x55ffaa55U, 0x28785028U, 0xdf7aa5dfU,
-    0x8c8f038cU, 0xa1f859a1U, 0x89800989U, 0x0d171a0dU, 0xbfda65bfU,
-    0xe631d7e6U, 0x42c68442U, 0x68b8d068U, 0x41c38241U, 0x99b02999U,
-    0x2d775a2dU, 0x0f111e0fU, 0xb0cb7bb0U, 0x54fca854U, 0xbbd66dbbU,
-    0x163a2c16U, };
-
-static const uint32_t Te3[256] = {
-    0x6363a5c6U, 0x7c7c84f8U, 0x777799eeU, 0x7b7b8df6U, 0xf2f20dffU,
-    0x6b6bbdd6U, 0x6f6fb1deU, 0xc5c55491U, 0x30305060U, 0x01010302U,
-    0x6767a9ceU, 0x2b2b7d56U, 0xfefe19e7U, 0xd7d762b5U, 0xababe64dU,
-    0x76769aecU, 0xcaca458fU, 0x82829d1fU, 0xc9c94089U, 0x7d7d87faU,
-    0xfafa15efU, 0x5959ebb2U, 0x4747c98eU, 0xf0f00bfbU, 0xadadec41U,
-    0xd4d467b3U, 0xa2a2fd5fU, 0xafafea45U, 0x9c9cbf23U, 0xa4a4f753U,
-    0x727296e4U, 0xc0c05b9bU, 0xb7b7c275U, 0xfdfd1ce1U, 0x9393ae3dU,
-    0x26266a4cU, 0x36365a6cU, 0x3f3f417eU, 0xf7f702f5U, 0xcccc4f83U,
-    0x34345c68U, 0xa5a5f451U, 0xe5e534d1U, 0xf1f108f9U, 0x717193e2U,
-    0xd8d873abU, 0x31315362U, 0x15153f2aU, 0x04040c08U, 0xc7c75295U,
-    0x23236546U, 0xc3c35e9dU, 0x18182830U, 0x9696a137U, 0x05050f0aU,
-    0x9a9ab52fU, 0x0707090eU, 0x12123624U, 0x80809b1bU, 0xe2e23ddfU,
-    0xebeb26cdU, 0x2727694eU, 0xb2b2cd7fU, 0x75759feaU, 0x09091b12U,
-    0x83839e1dU, 0x2c2c7458U, 0x1a1a2e34U, 0x1b1b2d36U, 0x6e6eb2dcU,
-    0x5a5aeeb4U, 0xa0a0fb5bU, 0x5252f6a4U, 0x3b3b4d76U, 0xd6d661b7U,
-    0xb3b3ce7dU, 0x29297b52U, 0xe3e33eddU, 0x2f2f715eU, 0x84849713U,
-    0x5353f5a6U, 0xd1d168b9U, 0x00000000U, 0xeded2cc1U, 0x20206040U,
-    0xfcfc1fe3U, 0xb1b1c879U, 0x5b5bedb6U, 0x6a6abed4U, 0xcbcb468dU,
-    0xbebed967U, 0x39394b72U, 0x4a4ade94U, 0x4c4cd498U, 0x5858e8b0U,
-    0xcfcf4a85U, 0xd0d06bbbU, 0xefef2ac5U, 0xaaaae54fU, 0xfbfb16edU,
-    0x4343c586U, 0x4d4dd79aU, 0x33335566U, 0x85859411U, 0x4545cf8aU,
-    0xf9f910e9U, 0x02020604U, 0x7f7f81feU, 0x5050f0a0U, 0x3c3c4478U,
-    0x9f9fba25U, 0xa8a8e34bU, 0x5151f3a2U, 0xa3a3fe5dU, 0x4040c080U,
-    0x8f8f8a05U, 0x9292ad3fU, 0x9d9dbc21U, 0x38384870U, 0xf5f504f1U,
-    0xbcbcdf63U, 0xb6b6c177U, 0xdada75afU, 0x21216342U, 0x10103020U,
-    0xffff1ae5U, 0xf3f30efdU, 0xd2d26dbfU, 0xcdcd4c81U, 0x0c0c1418U,
-    0x13133526U, 0xecec2fc3U, 0x5f5fe1beU, 0x9797a235U, 0x4444cc88U,
-    0x1717392eU, 0xc4c45793U, 0xa7a7f255U, 0x7e7e82fcU, 0x3d3d477aU,
-    0x6464acc8U, 0x5d5de7baU, 0x19192b32U, 0x737395e6U, 0x6060a0c0U,
-    0x81819819U, 0x4f4fd19eU, 0xdcdc7fa3U, 0x22226644U, 0x2a2a7e54U,
-    0x9090ab3bU, 0x8888830bU, 0x4646ca8cU, 0xeeee29c7U, 0xb8b8d36bU,
-    0x14143c28U, 0xdede79a7U, 0x5e5ee2bcU, 0x0b0b1d16U, 0xdbdb76adU,
-    0xe0e03bdbU, 0x32325664U, 0x3a3a4e74U, 0x0a0a1e14U, 0x4949db92U,
-    0x06060a0cU, 0x24246c48U, 0x5c5ce4b8U, 0xc2c25d9fU, 0xd3d36ebdU,
-    0xacacef43U, 0x6262a6c4U, 0x9191a839U, 0x9595a431U, 0xe4e437d3U,
-    0x79798bf2U, 0xe7e732d5U, 0xc8c8438bU, 0x3737596eU, 0x6d6db7daU,
-    0x8d8d8c01U, 0xd5d564b1U, 0x4e4ed29cU, 0xa9a9e049U, 0x6c6cb4d8U,
-    0x5656faacU, 0xf4f407f3U, 0xeaea25cfU, 0x6565afcaU, 0x7a7a8ef4U,
-    0xaeaee947U, 0x08081810U, 0xbabad56fU, 0x787888f0U, 0x25256f4aU,
-    0x2e2e725cU, 0x1c1c2438U, 0xa6a6f157U, 0xb4b4c773U, 0xc6c65197U,
-    0xe8e823cbU, 0xdddd7ca1U, 0x74749ce8U, 0x1f1f213eU, 0x4b4bdd96U,
-    0xbdbddc61U, 0x8b8b860dU, 0x8a8a850fU, 0x707090e0U, 0x3e3e427cU,
-    0xb5b5c471U, 0x6666aaccU, 0x4848d890U, 0x03030506U, 0xf6f601f7U,
-    0x0e0e121cU, 0x6161a3c2U, 0x35355f6aU, 0x5757f9aeU, 0xb9b9d069U,
-    0x86869117U, 0xc1c15899U, 0x1d1d273aU, 0x9e9eb927U, 0xe1e138d9U,
-    0xf8f813ebU, 0x9898b32bU, 0x11113322U, 0x6969bbd2U, 0xd9d970a9U,
-    0x8e8e8907U, 0x9494a733U, 0x9b9bb62dU, 0x1e1e223cU, 0x87879215U,
-    0xe9e920c9U, 0xcece4987U, 0x5555ffaaU, 0x28287850U, 0xdfdf7aa5U,
-    0x8c8c8f03U, 0xa1a1f859U, 0x89898009U, 0x0d0d171aU, 0xbfbfda65U,
-    0xe6e631d7U, 0x4242c684U, 0x6868b8d0U, 0x4141c382U, 0x9999b029U,
-    0x2d2d775aU, 0x0f0f111eU, 0xb0b0cb7bU, 0x5454fca8U, 0xbbbbd66dU,
-    0x16163a2cU, };
-
-static const uint32_t Td0[256] = {
-    0x51f4a750U, 0x7e416553U, 0x1a17a4c3U, 0x3a275e96U, 0x3bab6bcbU,
-    0x1f9d45f1U, 0xacfa58abU, 0x4be30393U, 0x2030fa55U, 0xad766df6U,
-    0x88cc7691U, 0xf5024c25U, 0x4fe5d7fcU, 0xc52acbd7U, 0x26354480U,
-    0xb562a38fU, 0xdeb15a49U, 0x25ba1b67U, 0x45ea0e98U, 0x5dfec0e1U,
-    0xc32f7502U, 0x814cf012U, 0x8d4697a3U, 0x6bd3f9c6U, 0x038f5fe7U,
-    0x15929c95U, 0xbf6d7aebU, 0x955259daU, 0xd4be832dU, 0x587421d3U,
-    0x49e06929U, 0x8ec9c844U, 0x75c2896aU, 0xf48e7978U, 0x99583e6bU,
-    0x27b971ddU, 0xbee14fb6U, 0xf088ad17U, 0xc920ac66U, 0x7dce3ab4U,
-    0x63df4a18U, 0xe51a3182U, 0x97513360U, 0x62537f45U, 0xb16477e0U,
-    0xbb6bae84U, 0xfe81a01cU, 0xf9082b94U, 0x70486858U, 0x8f45fd19U,
-    0x94de6c87U, 0x527bf8b7U, 0xab73d323U, 0x724b02e2U, 0xe31f8f57U,
-    0x6655ab2aU, 0xb2eb2807U, 0x2fb5c203U, 0x86c57b9aU, 0xd33708a5U,
-    0x302887f2U, 0x23bfa5b2U, 0x02036abaU, 0xed16825cU, 0x8acf1c2bU,
-    0xa779b492U, 0xf307f2f0U, 0x4e69e2a1U, 0x65daf4cdU, 0x0605bed5U,
-    0xd134621fU, 0xc4a6fe8aU, 0x342e539dU, 0xa2f355a0U, 0x058ae132U,
-    0xa4f6eb75U, 0x0b83ec39U, 0x4060efaaU, 0x5e719f06U, 0xbd6e1051U,
-    0x3e218af9U, 0x96dd063dU, 0xdd3e05aeU, 0x4de6bd46U, 0x91548db5U,
-    0x71c45d05U, 0x0406d46fU, 0x605015ffU, 0x1998fb24U, 0xd6bde997U,
-    0x894043ccU, 0x67d99e77U, 0xb0e842bdU, 0x07898b88U, 0xe7195b38U,
-    0x79c8eedbU, 0xa17c0a47U, 0x7c420fe9U, 0xf8841ec9U, 0x00000000U,
-    0x09808683U, 0x322bed48U, 0x1e1170acU, 0x6c5a724eU, 0xfd0efffbU,
-    0x0f853856U, 0x3daed51eU, 0x362d3927U, 0x0a0fd964U, 0x685ca621U,
-    0x9b5b54d1U, 0x24362e3aU, 0x0c0a67b1U, 0x9357e70fU, 0xb4ee96d2U,
-    0x1b9b919eU, 0x80c0c54fU, 0x61dc20a2U, 0x5a774b69U, 0x1c121a16U,
-    0xe293ba0aU, 0xc0a02ae5U, 0x3c22e043U, 0x121b171dU, 0x0e090d0bU,
-    0xf28bc7adU, 0x2db6a8b9U, 0x141ea9c8U, 0x57f11985U, 0xaf75074cU,
-    0xee99ddbbU, 0xa37f60fdU, 0xf701269fU, 0x5c72f5bcU, 0x44663bc5U,
-    0x5bfb7e34U, 0x8b432976U, 0xcb23c6dcU, 0xb6edfc68U, 0xb8e4f163U,
-    0xd731dccaU, 0x42638510U, 0x13972240U, 0x84c61120U, 0x854a247dU,
-    0xd2bb3df8U, 0xaef93211U, 0xc729a16dU, 0x1d9e2f4bU, 0xdcb230f3U,
-    0x0d8652ecU, 0x77c1e3d0U, 0x2bb3166cU, 0xa970b999U, 0x119448faU,
-    0x47e96422U, 0xa8fc8cc4U, 0xa0f03f1aU, 0x567d2cd8U, 0x223390efU,
-    0x87494ec7U, 0xd938d1c1U, 0x8ccaa2feU, 0x98d40b36U, 0xa6f581cfU,
-    0xa57ade28U, 0xdab78e26U, 0x3fadbfa4U, 0x2c3a9de4U, 0x5078920dU,
-    0x6a5fcc9bU, 0x547e4662U, 0xf68d13c2U, 0x90d8b8e8U, 0x2e39f75eU,
-    0x82c3aff5U, 0x9f5d80beU, 0x69d0937cU, 0x6fd52da9U, 0xcf2512b3U,
-    0xc8ac993bU, 0x10187da7U, 0xe89c636eU, 0xdb3bbb7bU, 0xcd267809U,
-    0x6e5918f4U, 0xec9ab701U, 0x834f9aa8U, 0xe6956e65U, 0xaaffe67eU,
-    0x21bccf08U, 0xef15e8e6U, 0xbae79bd9U, 0x4a6f36ceU, 0xea9f09d4U,
-    0x29b07cd6U, 0x31a4b2afU, 0x2a3f2331U, 0xc6a59430U, 0x35a266c0U,
-    0x744ebc37U, 0xfc82caa6U, 0xe090d0b0U, 0x33a7d815U, 0xf104984aU,
-    0x41ecdaf7U, 0x7fcd500eU, 0x1791f62fU, 0x764dd68dU, 0x43efb04dU,
-    0xccaa4d54U, 0xe49604dfU, 0x9ed1b5e3U, 0x4c6a881bU, 0xc12c1fb8U,
-    0x4665517fU, 0x9d5eea04U, 0x018c355dU, 0xfa877473U, 0xfb0b412eU,
-    0xb3671d5aU, 0x92dbd252U, 0xe9105633U, 0x6dd64713U, 0x9ad7618cU,
-    0x37a10c7aU, 0x59f8148eU, 0xeb133c89U, 0xcea927eeU, 0xb761c935U,
-    0xe11ce5edU, 0x7a47b13cU, 0x9cd2df59U, 0x55f2733fU, 0x1814ce79U,
-    0x73c737bfU, 0x53f7cdeaU, 0x5ffdaa5bU, 0xdf3d6f14U, 0x7844db86U,
-    0xcaaff381U, 0xb968c43eU, 0x3824342cU, 0xc2a3405fU, 0x161dc372U,
-    0xbce2250cU, 0x283c498bU, 0xff0d9541U, 0x39a80171U, 0x080cb3deU,
-    0xd8b4e49cU, 0x6456c190U, 0x7bcb8461U, 0xd532b670U, 0x486c5c74U,
-    0xd0b85742U, };
-
-static const uint32_t Td1[256] = {
-    0x5051f4a7U, 0x537e4165U, 0xc31a17a4U, 0x963a275eU, 0xcb3bab6bU,
-    0xf11f9d45U, 0xabacfa58U, 0x934be303U, 0x552030faU, 0xf6ad766dU,
-    0x9188cc76U, 0x25f5024cU, 0xfc4fe5d7U, 0xd7c52acbU, 0x80263544U,
-    0x8fb562a3U, 0x49deb15aU, 0x6725ba1bU, 0x9845ea0eU, 0xe15dfec0U,
-    0x02c32f75U, 0x12814cf0U, 0xa38d4697U, 0xc66bd3f9U, 0xe7038f5fU,
-    0x9515929cU, 0xebbf6d7aU, 0xda955259U, 0x2dd4be83U, 0xd3587421U,
-    0x2949e069U, 0x448ec9c8U, 0x6a75c289U, 0x78f48e79U, 0x6b99583eU,
-    0xdd27b971U, 0xb6bee14fU, 0x17f088adU, 0x66c920acU, 0xb47dce3aU,
-    0x1863df4aU, 0x82e51a31U, 0x60975133U, 0x4562537fU, 0xe0b16477U,
-    0x84bb6baeU, 0x1cfe81a0U, 0x94f9082bU, 0x58704868U, 0x198f45fdU,
-    0x8794de6cU, 0xb7527bf8U, 0x23ab73d3U, 0xe2724b02U, 0x57e31f8fU,
-    0x2a6655abU, 0x07b2eb28U, 0x032fb5c2U, 0x9a86c57bU, 0xa5d33708U,
-    0xf2302887U, 0xb223bfa5U, 0xba02036aU, 0x5ced1682U, 0x2b8acf1cU,
-    0x92a779b4U, 0xf0f307f2U, 0xa14e69e2U, 0xcd65daf4U, 0xd50605beU,
-    0x1fd13462U, 0x8ac4a6feU, 0x9d342e53U, 0xa0a2f355U, 0x32058ae1U,
-    0x75a4f6ebU, 0x390b83ecU, 0xaa4060efU, 0x065e719fU, 0x51bd6e10U,
-    0xf93e218aU, 0x3d96dd06U, 0xaedd3e05U, 0x464de6bdU, 0xb591548dU,
-    0x0571c45dU, 0x6f0406d4U, 0xff605015U, 0x241998fbU, 0x97d6bde9U,
-    0xcc894043U, 0x7767d99eU, 0xbdb0e842U, 0x8807898bU, 0x38e7195bU,
-    0xdb79c8eeU, 0x47a17c0aU, 0xe97c420fU, 0xc9f8841eU, 0x00000000U,
-    0x83098086U, 0x48322bedU, 0xac1e1170U, 0x4e6c5a72U, 0xfbfd0effU,
-    0x560f8538U, 0x1e3daed5U, 0x27362d39U, 0x640a0fd9U, 0x21685ca6U,
-    0xd19b5b54U, 0x3a24362eU, 0xb10c0a67U, 0x0f9357e7U, 0xd2b4ee96U,
-    0x9e1b9b91U, 0x4f80c0c5U, 0xa261dc20U, 0x695a774bU, 0x161c121aU,
-    0x0ae293baU, 0xe5c0a02aU, 0x433c22e0U, 0x1d121b17U, 0x0b0e090dU,
-    0xadf28bc7U, 0xb92db6a8U, 0xc8141ea9U, 0x8557f119U, 0x4caf7507U,
-    0xbbee99ddU, 0xfda37f60U, 0x9ff70126U, 0xbc5c72f5U, 0xc544663bU,
-    0x345bfb7eU, 0x768b4329U, 0xdccb23c6U, 0x68b6edfcU, 0x63b8e4f1U,
-    0xcad731dcU, 0x10426385U, 0x40139722U, 0x2084c611U, 0x7d854a24U,
-    0xf8d2bb3dU, 0x11aef932U, 0x6dc729a1U, 0x4b1d9e2fU, 0xf3dcb230U,
-    0xec0d8652U, 0xd077c1e3U, 0x6c2bb316U, 0x99a970b9U, 0xfa119448U,
-    0x2247e964U, 0xc4a8fc8cU, 0x1aa0f03fU, 0xd8567d2cU, 0xef223390U,
-    0xc787494eU, 0xc1d938d1U, 0xfe8ccaa2U, 0x3698d40bU, 0xcfa6f581U,
-    0x28a57adeU, 0x26dab78eU, 0xa43fadbfU, 0xe42c3a9dU, 0x0d507892U,
-    0x9b6a5fccU, 0x62547e46U, 0xc2f68d13U, 0xe890d8b8U, 0x5e2e39f7U,
-    0xf582c3afU, 0xbe9f5d80U, 0x7c69d093U, 0xa96fd52dU, 0xb3cf2512U,
-    0x3bc8ac99U, 0xa710187dU, 0x6ee89c63U, 0x7bdb3bbbU, 0x09cd2678U,
-    0xf46e5918U, 0x01ec9ab7U, 0xa8834f9aU, 0x65e6956eU, 0x7eaaffe6U,
-    0x0821bccfU, 0xe6ef15e8U, 0xd9bae79bU, 0xce4a6f36U, 0xd4ea9f09U,
-    0xd629b07cU, 0xaf31a4b2U, 0x312a3f23U, 0x30c6a594U, 0xc035a266U,
-    0x37744ebcU, 0xa6fc82caU, 0xb0e090d0U, 0x1533a7d8U, 0x4af10498U,
-    0xf741ecdaU, 0x0e7fcd50U, 0x2f1791f6U, 0x8d764dd6U, 0x4d43efb0U,
-    0x54ccaa4dU, 0xdfe49604U, 0xe39ed1b5U, 0x1b4c6a88U, 0xb8c12c1fU,
-    0x7f466551U, 0x049d5eeaU, 0x5d018c35U, 0x73fa8774U, 0x2efb0b41U,
-    0x5ab3671dU, 0x5292dbd2U, 0x33e91056U, 0x136dd647U, 0x8c9ad761U,
-    0x7a37a10cU, 0x8e59f814U, 0x89eb133cU, 0xeecea927U, 0x35b761c9U,
-    0xede11ce5U, 0x3c7a47b1U, 0x599cd2dfU, 0x3f55f273U, 0x791814ceU,
-    0xbf73c737U, 0xea53f7cdU, 0x5b5ffdaaU, 0x14df3d6fU, 0x867844dbU,
-    0x81caaff3U, 0x3eb968c4U, 0x2c382434U, 0x5fc2a340U, 0x72161dc3U,
-    0x0cbce225U, 0x8b283c49U, 0x41ff0d95U, 0x7139a801U, 0xde080cb3U,
-    0x9cd8b4e4U, 0x906456c1U, 0x617bcb84U, 0x70d532b6U, 0x74486c5cU,
-    0x42d0b857U, };
-
-static const uint32_t Td2[256] = {
-    0xa75051f4U, 0x65537e41U, 0xa4c31a17U, 0x5e963a27U, 0x6bcb3babU,
-    0x45f11f9dU, 0x58abacfaU, 0x03934be3U, 0xfa552030U, 0x6df6ad76U,
-    0x769188ccU, 0x4c25f502U, 0xd7fc4fe5U, 0xcbd7c52aU, 0x44802635U,
-    0xa38fb562U, 0x5a49deb1U, 0x1b6725baU, 0x0e9845eaU, 0xc0e15dfeU,
-    0x7502c32fU, 0xf012814cU, 0x97a38d46U, 0xf9c66bd3U, 0x5fe7038fU,
-    0x9c951592U, 0x7aebbf6dU, 0x59da9552U, 0x832dd4beU, 0x21d35874U,
-    0x692949e0U, 0xc8448ec9U, 0x896a75c2U, 0x7978f48eU, 0x3e6b9958U,
-    0x71dd27b9U, 0x4fb6bee1U, 0xad17f088U, 0xac66c920U, 0x3ab47dceU,
-    0x4a1863dfU, 0x3182e51aU, 0x33609751U, 0x7f456253U, 0x77e0b164U,
-    0xae84bb6bU, 0xa01cfe81U, 0x2b94f908U, 0x68587048U, 0xfd198f45U,
-    0x6c8794deU, 0xf8b7527bU, 0xd323ab73U, 0x02e2724bU, 0x8f57e31fU,
-    0xab2a6655U, 0x2807b2ebU, 0xc2032fb5U, 0x7b9a86c5U, 0x08a5d337U,
-    0x87f23028U, 0xa5b223bfU, 0x6aba0203U, 0x825ced16U, 0x1c2b8acfU,
-    0xb492a779U, 0xf2f0f307U, 0xe2a14e69U, 0xf4cd65daU, 0xbed50605U,
-    0x621fd134U, 0xfe8ac4a6U, 0x539d342eU, 0x55a0a2f3U, 0xe132058aU,
-    0xeb75a4f6U, 0xec390b83U, 0xefaa4060U, 0x9f065e71U, 0x1051bd6eU,
-    0x8af93e21U, 0x063d96ddU, 0x05aedd3eU, 0xbd464de6U, 0x8db59154U,
-    0x5d0571c4U, 0xd46f0406U, 0x15ff6050U, 0xfb241998U, 0xe997d6bdU,
-    0x43cc8940U, 0x9e7767d9U, 0x42bdb0e8U, 0x8b880789U, 0x5b38e719U,
-    0xeedb79c8U, 0x0a47a17cU, 0x0fe97c42U, 0x1ec9f884U, 0x00000000U,
-    0x86830980U, 0xed48322bU, 0x70ac1e11U, 0x724e6c5aU, 0xfffbfd0eU,
-    0x38560f85U, 0xd51e3daeU, 0x3927362dU, 0xd9640a0fU, 0xa621685cU,
-    0x54d19b5bU, 0x2e3a2436U, 0x67b10c0aU, 0xe70f9357U, 0x96d2b4eeU,
-    0x919e1b9bU, 0xc54f80c0U, 0x20a261dcU, 0x4b695a77U, 0x1a161c12U,
-    0xba0ae293U, 0x2ae5c0a0U, 0xe0433c22U, 0x171d121bU, 0x0d0b0e09U,
-    0xc7adf28bU, 0xa8b92db6U, 0xa9c8141eU, 0x198557f1U, 0x074caf75U,
-    0xddbbee99U, 0x60fda37fU, 0x269ff701U, 0xf5bc5c72U, 0x3bc54466U,
-    0x7e345bfbU, 0x29768b43U, 0xc6dccb23U, 0xfc68b6edU, 0xf163b8e4U,
-    0xdccad731U, 0x85104263U, 0x22401397U, 0x112084c6U, 0x247d854aU,
-    0x3df8d2bbU, 0x3211aef9U, 0xa16dc729U, 0x2f4b1d9eU, 0x30f3dcb2U,
-    0x52ec0d86U, 0xe3d077c1U, 0x166c2bb3U, 0xb999a970U, 0x48fa1194U,
-    0x642247e9U, 0x8cc4a8fcU, 0x3f1aa0f0U, 0x2cd8567dU, 0x90ef2233U,
-    0x4ec78749U, 0xd1c1d938U, 0xa2fe8ccaU, 0x0b3698d4U, 0x81cfa6f5U,
-    0xde28a57aU, 0x8e26dab7U, 0xbfa43fadU, 0x9de42c3aU, 0x920d5078U,
-    0xcc9b6a5fU, 0x4662547eU, 0x13c2f68dU, 0xb8e890d8U, 0xf75e2e39U,
-    0xaff582c3U, 0x80be9f5dU, 0x937c69d0U, 0x2da96fd5U, 0x12b3cf25U,
-    0x993bc8acU, 0x7da71018U, 0x636ee89cU, 0xbb7bdb3bU, 0x7809cd26U,
-    0x18f46e59U, 0xb701ec9aU, 0x9aa8834fU, 0x6e65e695U, 0xe67eaaffU,
-    0xcf0821bcU, 0xe8e6ef15U, 0x9bd9bae7U, 0x36ce4a6fU, 0x09d4ea9fU,
-    0x7cd629b0U, 0xb2af31a4U, 0x23312a3fU, 0x9430c6a5U, 0x66c035a2U,
-    0xbc37744eU, 0xcaa6fc82U, 0xd0b0e090U, 0xd81533a7U, 0x984af104U,
-    0xdaf741ecU, 0x500e7fcdU, 0xf62f1791U, 0xd68d764dU, 0xb04d43efU,
-    0x4d54ccaaU, 0x04dfe496U, 0xb5e39ed1U, 0x881b4c6aU, 0x1fb8c12cU,
-    0x517f4665U, 0xea049d5eU, 0x355d018cU, 0x7473fa87U, 0x412efb0bU,
-    0x1d5ab367U, 0xd25292dbU, 0x5633e910U, 0x47136dd6U, 0x618c9ad7U,
-    0x0c7a37a1U, 0x148e59f8U, 0x3c89eb13U, 0x27eecea9U, 0xc935b761U,
-    0xe5ede11cU, 0xb13c7a47U, 0xdf599cd2U, 0x733f55f2U, 0xce791814U,
-    0x37bf73c7U, 0xcdea53f7U, 0xaa5b5ffdU, 0x6f14df3dU, 0xdb867844U,
-    0xf381caafU, 0xc43eb968U, 0x342c3824U, 0x405fc2a3U, 0xc372161dU,
-    0x250cbce2U, 0x498b283cU, 0x9541ff0dU, 0x017139a8U, 0xb3de080cU,
-    0xe49cd8b4U, 0xc1906456U, 0x84617bcbU, 0xb670d532U, 0x5c74486cU,
-    0x5742d0b8U, };
-
-static const uint32_t Td3[256] = {
-    0xf4a75051U, 0x4165537eU, 0x17a4c31aU, 0x275e963aU, 0xab6bcb3bU,
-    0x9d45f11fU, 0xfa58abacU, 0xe303934bU, 0x30fa5520U, 0x766df6adU,
-    0xcc769188U, 0x024c25f5U, 0xe5d7fc4fU, 0x2acbd7c5U, 0x35448026U,
-    0x62a38fb5U, 0xb15a49deU, 0xba1b6725U, 0xea0e9845U, 0xfec0e15dU,
-    0x2f7502c3U, 0x4cf01281U, 0x4697a38dU, 0xd3f9c66bU, 0x8f5fe703U,
-    0x929c9515U, 0x6d7aebbfU, 0x5259da95U, 0xbe832dd4U, 0x7421d358U,
-    0xe0692949U, 0xc9c8448eU, 0xc2896a75U, 0x8e7978f4U, 0x583e6b99U,
-    0xb971dd27U, 0xe14fb6beU, 0x88ad17f0U, 0x20ac66c9U, 0xce3ab47dU,
-    0xdf4a1863U, 0x1a3182e5U, 0x51336097U, 0x537f4562U, 0x6477e0b1U,
-    0x6bae84bbU, 0x81a01cfeU, 0x082b94f9U, 0x48685870U, 0x45fd198fU,
-    0xde6c8794U, 0x7bf8b752U, 0x73d323abU, 0x4b02e272U, 0x1f8f57e3U,
-    0x55ab2a66U, 0xeb2807b2U, 0xb5c2032fU, 0xc57b9a86U, 0x3708a5d3U,
-    0x2887f230U, 0xbfa5b223U, 0x036aba02U, 0x16825cedU, 0xcf1c2b8aU,
-    0x79b492a7U, 0x07f2f0f3U, 0x69e2a14eU, 0xdaf4cd65U, 0x05bed506U,
-    0x34621fd1U, 0xa6fe8ac4U, 0x2e539d34U, 0xf355a0a2U, 0x8ae13205U,
-    0xf6eb75a4U, 0x83ec390bU, 0x60efaa40U, 0x719f065eU, 0x6e1051bdU,
-    0x218af93eU, 0xdd063d96U, 0x3e05aeddU, 0xe6bd464dU, 0x548db591U,
-    0xc45d0571U, 0x06d46f04U, 0x5015ff60U, 0x98fb2419U, 0xbde997d6U,
-    0x4043cc89U, 0xd99e7767U, 0xe842bdb0U, 0x898b8807U, 0x195b38e7U,
-    0xc8eedb79U, 0x7c0a47a1U, 0x420fe97cU, 0x841ec9f8U, 0x00000000U,
-    0x80868309U, 0x2bed4832U, 0x1170ac1eU, 0x5a724e6cU, 0x0efffbfdU,
-    0x8538560fU, 0xaed51e3dU, 0x2d392736U, 0x0fd9640aU, 0x5ca62168U,
-    0x5b54d19bU, 0x362e3a24U, 0x0a67b10cU, 0x57e70f93U, 0xee96d2b4U,
-    0x9b919e1bU, 0xc0c54f80U, 0xdc20a261U, 0x774b695aU, 0x121a161cU,
-    0x93ba0ae2U, 0xa02ae5c0U, 0x22e0433cU, 0x1b171d12U, 0x090d0b0eU,
-    0x8bc7adf2U, 0xb6a8b92dU, 0x1ea9c814U, 0xf1198557U, 0x75074cafU,
-    0x99ddbbeeU, 0x7f60fda3U, 0x01269ff7U, 0x72f5bc5cU, 0x663bc544U,
-    0xfb7e345bU, 0x4329768bU, 0x23c6dccbU, 0xedfc68b6U, 0xe4f163b8U,
-    0x31dccad7U, 0x63851042U, 0x97224013U, 0xc6112084U, 0x4a247d85U,
-    0xbb3df8d2U, 0xf93211aeU, 0x29a16dc7U, 0x9e2f4b1dU, 0xb230f3dcU,
-    0x8652ec0dU, 0xc1e3d077U, 0xb3166c2bU, 0x70b999a9U, 0x9448fa11U,
-    0xe9642247U, 0xfc8cc4a8U, 0xf03f1aa0U, 0x7d2cd856U, 0x3390ef22U,
-    0x494ec787U, 0x38d1c1d9U, 0xcaa2fe8cU, 0xd40b3698U, 0xf581cfa6U,
-    0x7ade28a5U, 0xb78e26daU, 0xadbfa43fU, 0x3a9de42cU, 0x78920d50U,
-    0x5fcc9b6aU, 0x7e466254U, 0x8d13c2f6U, 0xd8b8e890U, 0x39f75e2eU,
-    0xc3aff582U, 0x5d80be9fU, 0xd0937c69U, 0xd52da96fU, 0x2512b3cfU,
-    0xac993bc8U, 0x187da710U, 0x9c636ee8U, 0x3bbb7bdbU, 0x267809cdU,
-    0x5918f46eU, 0x9ab701ecU, 0x4f9aa883U, 0x956e65e6U, 0xffe67eaaU,
-    0xbccf0821U, 0x15e8e6efU, 0xe79bd9baU, 0x6f36ce4aU, 0x9f09d4eaU,
-    0xb07cd629U, 0xa4b2af31U, 0x3f23312aU, 0xa59430c6U, 0xa266c035U,
-    0x4ebc3774U, 0x82caa6fcU, 0x90d0b0e0U, 0xa7d81533U, 0x04984af1U,
-    0xecdaf741U, 0xcd500e7fU, 0x91f62f17U, 0x4dd68d76U, 0xefb04d43U,
-    0xaa4d54ccU, 0x9604dfe4U, 0xd1b5e39eU, 0x6a881b4cU, 0x2c1fb8c1U,
-    0x65517f46U, 0x5eea049dU, 0x8c355d01U, 0x877473faU, 0x0b412efbU,
-    0x671d5ab3U, 0xdbd25292U, 0x105633e9U, 0xd647136dU, 0xd7618c9aU,
-    0xa10c7a37U, 0xf8148e59U, 0x133c89ebU, 0xa927eeceU, 0x61c935b7U,
-    0x1ce5ede1U, 0x47b13c7aU, 0xd2df599cU, 0xf2733f55U, 0x14ce7918U,
-    0xc737bf73U, 0xf7cdea53U, 0xfdaa5b5fU, 0x3d6f14dfU, 0x44db8678U,
-    0xaff381caU, 0x68c43eb9U, 0x24342c38U, 0xa3405fc2U, 0x1dc37216U,
-    0xe2250cbcU, 0x3c498b28U, 0x0d9541ffU, 0xa8017139U, 0x0cb3de08U,
-    0xb4e49cd8U, 0x56c19064U, 0xcb84617bU, 0x32b670d5U, 0x6c5c7448U,
-    0xb85742d0U, };
-
-static const uint8_t Td4[256] = {
-    0x52U, 0x09U, 0x6aU, 0xd5U, 0x30U, 0x36U, 0xa5U, 0x38U, 0xbfU, 0x40U, 0xa3U,
-    0x9eU, 0x81U, 0xf3U, 0xd7U, 0xfbU, 0x7cU, 0xe3U, 0x39U, 0x82U, 0x9bU, 0x2fU,
-    0xffU, 0x87U, 0x34U, 0x8eU, 0x43U, 0x44U, 0xc4U, 0xdeU, 0xe9U, 0xcbU, 0x54U,
-    0x7bU, 0x94U, 0x32U, 0xa6U, 0xc2U, 0x23U, 0x3dU, 0xeeU, 0x4cU, 0x95U, 0x0bU,
-    0x42U, 0xfaU, 0xc3U, 0x4eU, 0x08U, 0x2eU, 0xa1U, 0x66U, 0x28U, 0xd9U, 0x24U,
-    0xb2U, 0x76U, 0x5bU, 0xa2U, 0x49U, 0x6dU, 0x8bU, 0xd1U, 0x25U, 0x72U, 0xf8U,
-    0xf6U, 0x64U, 0x86U, 0x68U, 0x98U, 0x16U, 0xd4U, 0xa4U, 0x5cU, 0xccU, 0x5dU,
-    0x65U, 0xb6U, 0x92U, 0x6cU, 0x70U, 0x48U, 0x50U, 0xfdU, 0xedU, 0xb9U, 0xdaU,
-    0x5eU, 0x15U, 0x46U, 0x57U, 0xa7U, 0x8dU, 0x9dU, 0x84U, 0x90U, 0xd8U, 0xabU,
-    0x00U, 0x8cU, 0xbcU, 0xd3U, 0x0aU, 0xf7U, 0xe4U, 0x58U, 0x05U, 0xb8U, 0xb3U,
-    0x45U, 0x06U, 0xd0U, 0x2cU, 0x1eU, 0x8fU, 0xcaU, 0x3fU, 0x0fU, 0x02U, 0xc1U,
-    0xafU, 0xbdU, 0x03U, 0x01U, 0x13U, 0x8aU, 0x6bU, 0x3aU, 0x91U, 0x11U, 0x41U,
-    0x4fU, 0x67U, 0xdcU, 0xeaU, 0x97U, 0xf2U, 0xcfU, 0xceU, 0xf0U, 0xb4U, 0xe6U,
-    0x73U, 0x96U, 0xacU, 0x74U, 0x22U, 0xe7U, 0xadU, 0x35U, 0x85U, 0xe2U, 0xf9U,
-    0x37U, 0xe8U, 0x1cU, 0x75U, 0xdfU, 0x6eU, 0x47U, 0xf1U, 0x1aU, 0x71U, 0x1dU,
-    0x29U, 0xc5U, 0x89U, 0x6fU, 0xb7U, 0x62U, 0x0eU, 0xaaU, 0x18U, 0xbeU, 0x1bU,
-    0xfcU, 0x56U, 0x3eU, 0x4bU, 0xc6U, 0xd2U, 0x79U, 0x20U, 0x9aU, 0xdbU, 0xc0U,
-    0xfeU, 0x78U, 0xcdU, 0x5aU, 0xf4U, 0x1fU, 0xddU, 0xa8U, 0x33U, 0x88U, 0x07U,
-    0xc7U, 0x31U, 0xb1U, 0x12U, 0x10U, 0x59U, 0x27U, 0x80U, 0xecU, 0x5fU, 0x60U,
-    0x51U, 0x7fU, 0xa9U, 0x19U, 0xb5U, 0x4aU, 0x0dU, 0x2dU, 0xe5U, 0x7aU, 0x9fU,
-    0x93U, 0xc9U, 0x9cU, 0xefU, 0xa0U, 0xe0U, 0x3bU, 0x4dU, 0xaeU, 0x2aU, 0xf5U,
-    0xb0U, 0xc8U, 0xebU, 0xbbU, 0x3cU, 0x83U, 0x53U, 0x99U, 0x61U, 0x17U, 0x2bU,
-    0x04U, 0x7eU, 0xbaU, 0x77U, 0xd6U, 0x26U, 0xe1U, 0x69U, 0x14U, 0x63U, 0x55U,
-    0x21U, 0x0cU, 0x7dU, };
-
-static const uint32_t rcon[] = {
-    0x01000000, 0x02000000, 0x04000000, 0x08000000, 0x10000000,
-    0x20000000, 0x40000000, 0x80000000, 0x1B000000, 0x36000000,
-    // for 128-bit blocks, Rijndael never uses more than 10 rcon values
-};
-
-int aes_nohw_set_encrypt_key(const uint8_t *key, unsigned bits,
-			     AES_KEY *aeskey) {
-  uint32_t *rk;
-  int i = 0;
-  uint32_t temp;
-
-  if (!key || !aeskey) {
-    return -1;
-  }
-
-  switch (bits) {
-    case 128:
-      aeskey->rounds = 10;
-      break;
-    case 192:
-      aeskey->rounds = 12;
-      break;
-    case 256:
-      aeskey->rounds = 14;
-      break;
-    default:
-      return -2;
-  }
-
-  rk = aeskey->rd_key;
-
-  rk[0] = GETU32(key);
-  rk[1] = GETU32(key + 4);
-  rk[2] = GETU32(key + 8);
-  rk[3] = GETU32(key + 12);
-  if (bits == 128) {
-    while (1) {
-      temp = rk[3];
-      rk[4] = rk[0] ^ (Te2[(temp >> 16) & 0xff] & 0xff000000) ^
-              (Te3[(temp >> 8) & 0xff] & 0x00ff0000) ^
-              (Te0[(temp) & 0xff] & 0x0000ff00) ^
-              (Te1[(temp >> 24)] & 0x000000ff) ^ rcon[i];
-      rk[5] = rk[1] ^ rk[4];
-      rk[6] = rk[2] ^ rk[5];
-      rk[7] = rk[3] ^ rk[6];
-      if (++i == 10) {
-        return 0;
-      }
-      rk += 4;
-    }
-  }
-  rk[4] = GETU32(key + 16);
-  rk[5] = GETU32(key + 20);
-  if (bits == 192) {
-    while (1) {
-      temp = rk[5];
-      rk[6] = rk[0] ^ (Te2[(temp >> 16) & 0xff] & 0xff000000) ^
-              (Te3[(temp >> 8) & 0xff] & 0x00ff0000) ^
-              (Te0[(temp) & 0xff] & 0x0000ff00) ^
-              (Te1[(temp >> 24)] & 0x000000ff) ^ rcon[i];
-      rk[7] = rk[1] ^ rk[6];
-      rk[8] = rk[2] ^ rk[7];
-      rk[9] = rk[3] ^ rk[8];
-      if (++i == 8) {
-        return 0;
-      }
-      rk[10] = rk[4] ^ rk[9];
-      rk[11] = rk[5] ^ rk[10];
-      rk += 6;
-    }
-  }
-  rk[6] = GETU32(key + 24);
-  rk[7] = GETU32(key + 28);
-  if (bits == 256) {
-    while (1) {
-      temp = rk[7];
-      rk[8] = rk[0] ^ (Te2[(temp >> 16) & 0xff] & 0xff000000) ^
-              (Te3[(temp >> 8) & 0xff] & 0x00ff0000) ^
-              (Te0[(temp) & 0xff] & 0x0000ff00) ^
-              (Te1[(temp >> 24)] & 0x000000ff) ^ rcon[i];
-      rk[9] = rk[1] ^ rk[8];
-      rk[10] = rk[2] ^ rk[9];
-      rk[11] = rk[3] ^ rk[10];
-      if (++i == 7) {
-        return 0;
-      }
-      temp = rk[11];
-      rk[12] = rk[4] ^ (Te2[(temp >> 24)] & 0xff000000) ^
-               (Te3[(temp >> 16) & 0xff] & 0x00ff0000) ^
-               (Te0[(temp >> 8) & 0xff] & 0x0000ff00) ^
-               (Te1[(temp) & 0xff] & 0x000000ff);
-      rk[13] = rk[5] ^ rk[12];
-      rk[14] = rk[6] ^ rk[13];
-      rk[15] = rk[7] ^ rk[14];
-
-      rk += 8;
-    }
-  }
-  return 0;
-}
-
-int aes_nohw_set_decrypt_key(const uint8_t *key, unsigned bits,
-			     AES_KEY *aeskey) {
-  uint32_t *rk;
-  int i, j, status;
-  uint32_t temp;
-
-  // first, start with an encryption schedule
-  status = AES_set_encrypt_key(key, bits, aeskey);
-  if (status < 0) {
-    return status;
-  }
-
-  rk = aeskey->rd_key;
-
-  // invert the order of the round keys:
-  for (i = 0, j = 4 * aeskey->rounds; i < j; i += 4, j -= 4) {
-    temp = rk[i];
-    rk[i] = rk[j];
-    rk[j] = temp;
-    temp = rk[i + 1];
-    rk[i + 1] = rk[j + 1];
-    rk[j + 1] = temp;
-    temp = rk[i + 2];
-    rk[i + 2] = rk[j + 2];
-    rk[j + 2] = temp;
-    temp = rk[i + 3];
-    rk[i + 3] = rk[j + 3];
-    rk[j + 3] = temp;
-  }
-  // apply the inverse MixColumn transform to all round keys but the first and
-  // the last:
-  for (i = 1; i < (int)aeskey->rounds; i++) {
-    rk += 4;
-    rk[0] =
-        Td0[Te1[(rk[0] >> 24)] & 0xff] ^ Td1[Te1[(rk[0] >> 16) & 0xff] & 0xff] ^
-        Td2[Te1[(rk[0] >> 8) & 0xff] & 0xff] ^ Td3[Te1[(rk[0]) & 0xff] & 0xff];
-    rk[1] =
-        Td0[Te1[(rk[1] >> 24)] & 0xff] ^ Td1[Te1[(rk[1] >> 16) & 0xff] & 0xff] ^
-        Td2[Te1[(rk[1] >> 8) & 0xff] & 0xff] ^ Td3[Te1[(rk[1]) & 0xff] & 0xff];
-    rk[2] =
-        Td0[Te1[(rk[2] >> 24)] & 0xff] ^ Td1[Te1[(rk[2] >> 16) & 0xff] & 0xff] ^
-        Td2[Te1[(rk[2] >> 8) & 0xff] & 0xff] ^ Td3[Te1[(rk[2]) & 0xff] & 0xff];
-    rk[3] =
-        Td0[Te1[(rk[3] >> 24)] & 0xff] ^ Td1[Te1[(rk[3] >> 16) & 0xff] & 0xff] ^
-        Td2[Te1[(rk[3] >> 8) & 0xff] & 0xff] ^ Td3[Te1[(rk[3]) & 0xff] & 0xff];
-  }
-  return 0;
-}
-
-void aes_nohw_encrypt(const uint8_t *in, uint8_t *out,
-		      const AES_KEY *key) {
-  const uint32_t *rk;
-  uint32_t s0, s1, s2, s3, t0, t1, t2, t3;
-  int r;
-
-  rk = key->rd_key;
-
-  // map byte array block to cipher state
-  // and add initial round key:
-  s0 = GETU32(in) ^ rk[0];
-  s1 = GETU32(in + 4) ^ rk[1];
-  s2 = GETU32(in + 8) ^ rk[2];
-  s3 = GETU32(in + 12) ^ rk[3];
-
-  // Nr - 1 full rounds:
-  r = key->rounds >> 1;
-  for (;;) {
-    t0 = Te0[(s0 >> 24)] ^ Te1[(s1 >> 16) & 0xff] ^ Te2[(s2 >> 8) & 0xff] ^
-         Te3[(s3) & 0xff] ^ rk[4];
-    t1 = Te0[(s1 >> 24)] ^ Te1[(s2 >> 16) & 0xff] ^ Te2[(s3 >> 8) & 0xff] ^
-         Te3[(s0) & 0xff] ^ rk[5];
-    t2 = Te0[(s2 >> 24)] ^ Te1[(s3 >> 16) & 0xff] ^ Te2[(s0 >> 8) & 0xff] ^
-         Te3[(s1) & 0xff] ^ rk[6];
-    t3 = Te0[(s3 >> 24)] ^ Te1[(s0 >> 16) & 0xff] ^ Te2[(s1 >> 8) & 0xff] ^
-         Te3[(s2) & 0xff] ^ rk[7];
-
-    rk += 8;
-    if (--r == 0) {
-      break;
-    }
-
-    s0 = Te0[(t0 >> 24)] ^ Te1[(t1 >> 16) & 0xff] ^ Te2[(t2 >> 8) & 0xff] ^
-         Te3[(t3) & 0xff] ^ rk[0];
-    s1 = Te0[(t1 >> 24)] ^ Te1[(t2 >> 16) & 0xff] ^ Te2[(t3 >> 8) & 0xff] ^
-         Te3[(t0) & 0xff] ^ rk[1];
-    s2 = Te0[(t2 >> 24)] ^ Te1[(t3 >> 16) & 0xff] ^ Te2[(t0 >> 8) & 0xff] ^
-         Te3[(t1) & 0xff] ^ rk[2];
-    s3 = Te0[(t3 >> 24)] ^ Te1[(t0 >> 16) & 0xff] ^ Te2[(t1 >> 8) & 0xff] ^
-         Te3[(t2) & 0xff] ^ rk[3];
-  }
-
-  //  apply last round and map cipher state to byte array block:
-  s0 = (Te2[(t0 >> 24)] & 0xff000000) ^ (Te3[(t1 >> 16) & 0xff] & 0x00ff0000) ^
-       (Te0[(t2 >> 8) & 0xff] & 0x0000ff00) ^ (Te1[(t3) & 0xff] & 0x000000ff) ^
-       rk[0];
-  PUTU32(out, s0);
-  s1 = (Te2[(t1 >> 24)] & 0xff000000) ^ (Te3[(t2 >> 16) & 0xff] & 0x00ff0000) ^
-       (Te0[(t3 >> 8) & 0xff] & 0x0000ff00) ^ (Te1[(t0) & 0xff] & 0x000000ff) ^
-       rk[1];
-  PUTU32(out + 4, s1);
-  s2 = (Te2[(t2 >> 24)] & 0xff000000) ^ (Te3[(t3 >> 16) & 0xff] & 0x00ff0000) ^
-       (Te0[(t0 >> 8) & 0xff] & 0x0000ff00) ^ (Te1[(t1) & 0xff] & 0x000000ff) ^
-       rk[2];
-  PUTU32(out + 8, s2);
-  s3 = (Te2[(t3 >> 24)] & 0xff000000) ^ (Te3[(t0 >> 16) & 0xff] & 0x00ff0000) ^
-       (Te0[(t1 >> 8) & 0xff] & 0x0000ff00) ^ (Te1[(t2) & 0xff] & 0x000000ff) ^
-       rk[3];
-  PUTU32(out + 12, s3);
-}
-
-void aes_nohw_decrypt(const uint8_t *in, uint8_t *out,
-		      const AES_KEY *key) {
-  const uint32_t *rk;
-  uint32_t s0, s1, s2, s3, t0, t1, t2, t3;
-  int r;
-
-  rk = key->rd_key;
-
-  // map byte array block to cipher state
-  // and add initial round key:
-  s0 = GETU32(in) ^ rk[0];
-  s1 = GETU32(in + 4) ^ rk[1];
-  s2 = GETU32(in + 8) ^ rk[2];
-  s3 = GETU32(in + 12) ^ rk[3];
-
-  // Nr - 1 full rounds:
-  r = key->rounds >> 1;
-  for (;;) {
-    t0 = Td0[(s0 >> 24)] ^ Td1[(s3 >> 16) & 0xff] ^ Td2[(s2 >> 8) & 0xff] ^
-         Td3[(s1) & 0xff] ^ rk[4];
-    t1 = Td0[(s1 >> 24)] ^ Td1[(s0 >> 16) & 0xff] ^ Td2[(s3 >> 8) & 0xff] ^
-         Td3[(s2) & 0xff] ^ rk[5];
-    t2 = Td0[(s2 >> 24)] ^ Td1[(s1 >> 16) & 0xff] ^ Td2[(s0 >> 8) & 0xff] ^
-         Td3[(s3) & 0xff] ^ rk[6];
-    t3 = Td0[(s3 >> 24)] ^ Td1[(s2 >> 16) & 0xff] ^ Td2[(s1 >> 8) & 0xff] ^
-         Td3[(s0) & 0xff] ^ rk[7];
-
-    rk += 8;
-    if (--r == 0) {
-      break;
-    }
-
-    s0 = Td0[(t0 >> 24)] ^ Td1[(t3 >> 16) & 0xff] ^ Td2[(t2 >> 8) & 0xff] ^
-         Td3[(t1) & 0xff] ^ rk[0];
-    s1 = Td0[(t1 >> 24)] ^ Td1[(t0 >> 16) & 0xff] ^ Td2[(t3 >> 8) & 0xff] ^
-         Td3[(t2) & 0xff] ^ rk[1];
-    s2 = Td0[(t2 >> 24)] ^ Td1[(t1 >> 16) & 0xff] ^ Td2[(t0 >> 8) & 0xff] ^
-         Td3[(t3) & 0xff] ^ rk[2];
-    s3 = Td0[(t3 >> 24)] ^ Td1[(t2 >> 16) & 0xff] ^ Td2[(t1 >> 8) & 0xff] ^
-         Td3[(t0) & 0xff] ^ rk[3];
-  }
-
-  // apply last round and
-  // map cipher state to byte array block:
-  s0 = ((uint32_t)Td4[(t0 >> 24)] << 24) ^
-       ((uint32_t)Td4[(t3 >> 16) & 0xff] << 16) ^
-       ((uint32_t)Td4[(t2 >> 8) & 0xff] << 8) ^
-       ((uint32_t)Td4[(t1) & 0xff]) ^ rk[0];
-  PUTU32(out, s0);
-  s1 = ((uint32_t)Td4[(t1 >> 24)] << 24) ^
-       ((uint32_t)Td4[(t0 >> 16) & 0xff] << 16) ^
-       ((uint32_t)Td4[(t3 >> 8) & 0xff] << 8) ^
-       ((uint32_t)Td4[(t2) & 0xff]) ^ rk[1];
-  PUTU32(out + 4, s1);
-  s2 = ((uint32_t)Td4[(t2 >> 24)] << 24) ^
-       ((uint32_t)Td4[(t1 >> 16) & 0xff] << 16) ^
-       ((uint32_t)Td4[(t0 >> 8) & 0xff] << 8) ^
-       ((uint32_t)Td4[(t3) & 0xff]) ^ rk[2];
-  PUTU32(out + 8, s2);
-  s3 = ((uint32_t)Td4[(t3 >> 24)] << 24) ^
-       ((uint32_t)Td4[(t2 >> 16) & 0xff] << 16) ^
-       ((uint32_t)Td4[(t1 >> 8) & 0xff] << 8) ^
-       ((uint32_t)Td4[(t0) & 0xff]) ^ rk[3];
-  PUTU32(out + 12, s3);
-}
diff --git a/third_party/boringssl/common/build.mk b/third_party/boringssl/common/build.mk
new file mode 100644
index 0000000000..b7848d121b
--- /dev/null
+++ b/third_party/boringssl/common/build.mk
@@ -0,0 +1,8 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# EC OS Support Files for BoringSSL
+#
+
+boringssl-y+=sysrand.o
diff --git a/third_party/boringssl/common/curve25519-generic.c b/third_party/boringssl/common/curve25519-generic.c
index e0d09b2acb..16e0668071 100644
--- a/third_party/boringssl/common/curve25519-generic.c
+++ b/third_party/boringssl/common/curve25519-generic.c
@@ -1,4 +1,4 @@
-/* Copyright 2015, Google Inc.
+/* Copyright 2015 Google LLC
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
diff --git a/third_party/boringssl/common/curve25519.c b/third_party/boringssl/common/curve25519.c
index 2a7fad6509..1c902e424c 100644
--- a/third_party/boringssl/common/curve25519.c
+++ b/third_party/boringssl/common/curve25519.c
@@ -1,4 +1,4 @@
-/* Copyright 2015, Google Inc.
+/* Copyright 2015 Google LLC
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -27,7 +27,7 @@
 
 #ifdef CONFIG_RNG
 void X25519_keypair(uint8_t out_public_value[32], uint8_t out_private_key[32]) {
-  rand_bytes(out_private_key, 32);
+  trng_rand_bytes(out_private_key, 32);
 
   /* All X25519 implementations should decode scalars correctly (see
    * https://tools.ietf.org/html/rfc7748#section-5). However, if an
diff --git a/third_party/boringssl/common/sysrand.c b/third_party/boringssl/common/sysrand.c
new file mode 100644
index 0000000000..74e058f892
--- /dev/null
+++ b/third_party/boringssl/common/sysrand.c
@@ -0,0 +1,20 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Implement the boringssl sysrand from EC TRNG. */
+
+#include "trng.h"
+
+void CRYPTO_sysrand(uint8_t *out, size_t requested)
+{
+	trng_init();
+	trng_rand_bytes(out, requested);
+	trng_exit();
+}
+
+void CRYPTO_sysrand_for_seed(uint8_t *out, size_t requested)
+{
+	return CRYPTO_sysrand(out, requested);
+}
diff --git a/third_party/boringssl/core/cortex-m/aes.S b/third_party/boringssl/core/cortex-m/aes.S
deleted file mode 100644
index 10d3cdabba..0000000000
--- a/third_party/boringssl/core/cortex-m/aes.S
+++ /dev/null
@@ -1,1189 +0,0 @@
-@ Copyright 2007-2016 The OpenSSL Project Authors. All Rights Reserved.
-@
-@ Licensed under the OpenSSL license (the "License").  You may not use
-@ this file except in compliance with the License.  You can obtain a copy
-@ in the file LICENSE in the source distribution or at
-@ https://www.openssl.org/source/license.html
-
-
-@ ====================================================================
-@ Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
-@ project. The module is, however, dual licensed under OpenSSL and
-@ CRYPTOGAMS licenses depending on where you obtain it. For further
-@ details see http://www.openssl.org/~appro/cryptogams/.
-@ ====================================================================
-
-@ AES for ARMv4
-
-@ January 2007.
-@
-@ Code uses single 1K S-box and is >2 times faster than code generated
-@ by gcc-3.4.1. This is thanks to unique feature of ARMv4 ISA, which
-@ allows to merge logical or arithmetic operation with shift or rotate
-@ in one instruction and emit combined result every cycle. The module
-@ is endian-neutral. The performance is ~42 cycles/byte for 128-bit
-@ key [on single-issue Xscale PXA250 core].
-
-@ May 2007.
-@
-@ AES_set_[en|de]crypt_key is added.
-
-@ July 2010.
-@
-@ Rescheduling for dual-issue pipeline resulted in 12% improvement on
-@ Cortex A8 core and ~25 cycles per byte processed with 128-bit key.
-
-@ February 2011.
-@
-@ Profiler-assisted and platform-specific optimization resulted in 16%
-@ improvement on Cortex A8 core and ~21.5 cycles per byte.
-
-#define __ARM_ARCH__ 7
-
-.text
-#if defined(__thumb2__) && !defined(__APPLE__)
-.syntax	unified
-.thumb
-#else
-.code	32
-#undef __thumb2__
-#endif
-
-.type	AES_Te,%object
-.align	5
-AES_Te:
-.word	0xc66363a5, 0xf87c7c84, 0xee777799, 0xf67b7b8d
-.word	0xfff2f20d, 0xd66b6bbd, 0xde6f6fb1, 0x91c5c554
-.word	0x60303050, 0x02010103, 0xce6767a9, 0x562b2b7d
-.word	0xe7fefe19, 0xb5d7d762, 0x4dababe6, 0xec76769a
-.word	0x8fcaca45, 0x1f82829d, 0x89c9c940, 0xfa7d7d87
-.word	0xeffafa15, 0xb25959eb, 0x8e4747c9, 0xfbf0f00b
-.word	0x41adadec, 0xb3d4d467, 0x5fa2a2fd, 0x45afafea
-.word	0x239c9cbf, 0x53a4a4f7, 0xe4727296, 0x9bc0c05b
-.word	0x75b7b7c2, 0xe1fdfd1c, 0x3d9393ae, 0x4c26266a
-.word	0x6c36365a, 0x7e3f3f41, 0xf5f7f702, 0x83cccc4f
-.word	0x6834345c, 0x51a5a5f4, 0xd1e5e534, 0xf9f1f108
-.word	0xe2717193, 0xabd8d873, 0x62313153, 0x2a15153f
-.word	0x0804040c, 0x95c7c752, 0x46232365, 0x9dc3c35e
-.word	0x30181828, 0x379696a1, 0x0a05050f, 0x2f9a9ab5
-.word	0x0e070709, 0x24121236, 0x1b80809b, 0xdfe2e23d
-.word	0xcdebeb26, 0x4e272769, 0x7fb2b2cd, 0xea75759f
-.word	0x1209091b, 0x1d83839e, 0x582c2c74, 0x341a1a2e
-.word	0x361b1b2d, 0xdc6e6eb2, 0xb45a5aee, 0x5ba0a0fb
-.word	0xa45252f6, 0x763b3b4d, 0xb7d6d661, 0x7db3b3ce
-.word	0x5229297b, 0xdde3e33e, 0x5e2f2f71, 0x13848497
-.word	0xa65353f5, 0xb9d1d168, 0x00000000, 0xc1eded2c
-.word	0x40202060, 0xe3fcfc1f, 0x79b1b1c8, 0xb65b5bed
-.word	0xd46a6abe, 0x8dcbcb46, 0x67bebed9, 0x7239394b
-.word	0x944a4ade, 0x984c4cd4, 0xb05858e8, 0x85cfcf4a
-.word	0xbbd0d06b, 0xc5efef2a, 0x4faaaae5, 0xedfbfb16
-.word	0x864343c5, 0x9a4d4dd7, 0x66333355, 0x11858594
-.word	0x8a4545cf, 0xe9f9f910, 0x04020206, 0xfe7f7f81
-.word	0xa05050f0, 0x783c3c44, 0x259f9fba, 0x4ba8a8e3
-.word	0xa25151f3, 0x5da3a3fe, 0x804040c0, 0x058f8f8a
-.word	0x3f9292ad, 0x219d9dbc, 0x70383848, 0xf1f5f504
-.word	0x63bcbcdf, 0x77b6b6c1, 0xafdada75, 0x42212163
-.word	0x20101030, 0xe5ffff1a, 0xfdf3f30e, 0xbfd2d26d
-.word	0x81cdcd4c, 0x180c0c14, 0x26131335, 0xc3ecec2f
-.word	0xbe5f5fe1, 0x359797a2, 0x884444cc, 0x2e171739
-.word	0x93c4c457, 0x55a7a7f2, 0xfc7e7e82, 0x7a3d3d47
-.word	0xc86464ac, 0xba5d5de7, 0x3219192b, 0xe6737395
-.word	0xc06060a0, 0x19818198, 0x9e4f4fd1, 0xa3dcdc7f
-.word	0x44222266, 0x542a2a7e, 0x3b9090ab, 0x0b888883
-.word	0x8c4646ca, 0xc7eeee29, 0x6bb8b8d3, 0x2814143c
-.word	0xa7dede79, 0xbc5e5ee2, 0x160b0b1d, 0xaddbdb76
-.word	0xdbe0e03b, 0x64323256, 0x743a3a4e, 0x140a0a1e
-.word	0x924949db, 0x0c06060a, 0x4824246c, 0xb85c5ce4
-.word	0x9fc2c25d, 0xbdd3d36e, 0x43acacef, 0xc46262a6
-.word	0x399191a8, 0x319595a4, 0xd3e4e437, 0xf279798b
-.word	0xd5e7e732, 0x8bc8c843, 0x6e373759, 0xda6d6db7
-.word	0x018d8d8c, 0xb1d5d564, 0x9c4e4ed2, 0x49a9a9e0
-.word	0xd86c6cb4, 0xac5656fa, 0xf3f4f407, 0xcfeaea25
-.word	0xca6565af, 0xf47a7a8e, 0x47aeaee9, 0x10080818
-.word	0x6fbabad5, 0xf0787888, 0x4a25256f, 0x5c2e2e72
-.word	0x381c1c24, 0x57a6a6f1, 0x73b4b4c7, 0x97c6c651
-.word	0xcbe8e823, 0xa1dddd7c, 0xe874749c, 0x3e1f1f21
-.word	0x964b4bdd, 0x61bdbddc, 0x0d8b8b86, 0x0f8a8a85
-.word	0xe0707090, 0x7c3e3e42, 0x71b5b5c4, 0xcc6666aa
-.word	0x904848d8, 0x06030305, 0xf7f6f601, 0x1c0e0e12
-.word	0xc26161a3, 0x6a35355f, 0xae5757f9, 0x69b9b9d0
-.word	0x17868691, 0x99c1c158, 0x3a1d1d27, 0x279e9eb9
-.word	0xd9e1e138, 0xebf8f813, 0x2b9898b3, 0x22111133
-.word	0xd26969bb, 0xa9d9d970, 0x078e8e89, 0x339494a7
-.word	0x2d9b9bb6, 0x3c1e1e22, 0x15878792, 0xc9e9e920
-.word	0x87cece49, 0xaa5555ff, 0x50282878, 0xa5dfdf7a
-.word	0x038c8c8f, 0x59a1a1f8, 0x09898980, 0x1a0d0d17
-.word	0x65bfbfda, 0xd7e6e631, 0x844242c6, 0xd06868b8
-.word	0x824141c3, 0x299999b0, 0x5a2d2d77, 0x1e0f0f11
-.word	0x7bb0b0cb, 0xa85454fc, 0x6dbbbbd6, 0x2c16163a
-@ Te4[256]
-.byte	0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5
-.byte	0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76
-.byte	0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0
-.byte	0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0
-.byte	0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc
-.byte	0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15
-.byte	0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a
-.byte	0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75
-.byte	0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0
-.byte	0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84
-.byte	0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b
-.byte	0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf
-.byte	0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85
-.byte	0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8
-.byte	0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5
-.byte	0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2
-.byte	0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17
-.byte	0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73
-.byte	0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88
-.byte	0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb
-.byte	0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c
-.byte	0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79
-.byte	0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9
-.byte	0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08
-.byte	0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6
-.byte	0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a
-.byte	0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e
-.byte	0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e
-.byte	0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94
-.byte	0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf
-.byte	0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68
-.byte	0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16
-@ rcon[]
-.word	0x01000000, 0x02000000, 0x04000000, 0x08000000
-.word	0x10000000, 0x20000000, 0x40000000, 0x80000000
-.word	0x1B000000, 0x36000000, 0, 0, 0, 0, 0, 0
-.size	AES_Te,.-AES_Te
-
-@ void aes_nohw_encrypt(const unsigned char *in, unsigned char *out,
-@ 		                  const AES_KEY *key) {
-.global aes_nohw_encrypt
-.type   aes_nohw_encrypt,%function
-.align	5
-aes_nohw_encrypt:
-#ifndef	__thumb2__
-	sub	r3,pc,#8		@ aes_nohw_encrypt
-#else
-	adr	r3,.
-#endif
-	stmdb   sp!,{r1,r4-r12,lr}
-#if defined(__thumb2__) || defined(__APPLE__)
-	adr	r10,AES_Te
-#else
-	sub	r10,r3,#aes_nohw_encrypt-AES_Te	@ Te
-#endif
-	mov	r12,r0		@ inp
-	mov	r11,r2
-#if __ARM_ARCH__<7
-	ldrb	r0,[r12,#3]	@ load input data in endian-neutral
-	ldrb	r4,[r12,#2]	@ manner...
-	ldrb	r5,[r12,#1]
-	ldrb	r6,[r12,#0]
-	orr	r0,r0,r4,lsl#8
-	ldrb	r1,[r12,#7]
-	orr	r0,r0,r5,lsl#16
-	ldrb	r4,[r12,#6]
-	orr	r0,r0,r6,lsl#24
-	ldrb	r5,[r12,#5]
-	ldrb	r6,[r12,#4]
-	orr	r1,r1,r4,lsl#8
-	ldrb	r2,[r12,#11]
-	orr	r1,r1,r5,lsl#16
-	ldrb	r4,[r12,#10]
-	orr	r1,r1,r6,lsl#24
-	ldrb	r5,[r12,#9]
-	ldrb	r6,[r12,#8]
-	orr	r2,r2,r4,lsl#8
-	ldrb	r3,[r12,#15]
-	orr	r2,r2,r5,lsl#16
-	ldrb	r4,[r12,#14]
-	orr	r2,r2,r6,lsl#24
-	ldrb	r5,[r12,#13]
-	ldrb	r6,[r12,#12]
-	orr	r3,r3,r4,lsl#8
-	orr	r3,r3,r5,lsl#16
-	orr	r3,r3,r6,lsl#24
-#else
-	ldr	r0,[r12,#0]
-	ldr	r1,[r12,#4]
-	ldr	r2,[r12,#8]
-	ldr	r3,[r12,#12]
-#ifdef __ARMEL__
-	rev	r0,r0
-	rev	r1,r1
-	rev	r2,r2
-	rev	r3,r3
-#endif
-#endif
-	bl	_armv4_AES_encrypt
-
-	ldr	r12,[sp],#4		@ pop out
-#if __ARM_ARCH__>=7
-#ifdef __ARMEL__
-	rev	r0,r0
-	rev	r1,r1
-	rev	r2,r2
-	rev	r3,r3
-#endif
-	str	r0,[r12,#0]
-	str	r1,[r12,#4]
-	str	r2,[r12,#8]
-	str	r3,[r12,#12]
-#else
-	mov	r4,r0,lsr#24		@ write output in endian-neutral
-	mov	r5,r0,lsr#16		@ manner...
-	mov	r6,r0,lsr#8
-	strb	r4,[r12,#0]
-	strb	r5,[r12,#1]
-	mov	r4,r1,lsr#24
-	strb	r6,[r12,#2]
-	mov	r5,r1,lsr#16
-	strb	r0,[r12,#3]
-	mov	r6,r1,lsr#8
-	strb	r4,[r12,#4]
-	strb	r5,[r12,#5]
-	mov	r4,r2,lsr#24
-	strb	r6,[r12,#6]
-	mov	r5,r2,lsr#16
-	strb	r1,[r12,#7]
-	mov	r6,r2,lsr#8
-	strb	r4,[r12,#8]
-	strb	r5,[r12,#9]
-	mov	r4,r3,lsr#24
-	strb	r6,[r12,#10]
-	mov	r5,r3,lsr#16
-	strb	r2,[r12,#11]
-	mov	r6,r3,lsr#8
-	strb	r4,[r12,#12]
-	strb	r5,[r12,#13]
-	strb	r6,[r12,#14]
-	strb	r3,[r12,#15]
-#endif
-#if __ARM_ARCH__>=5
-	ldmia	sp!,{r4-r12,pc}
-#else
-	ldmia   sp!,{r4-r12,lr}
-	tst	lr,#1
-	moveq	pc,lr			@ be binary compatible with V4, yet
-	.word	0xe12fff1e			@ interoperable with Thumb ISA:-)
-#endif
-.size	aes_nohw_encrypt,.-aes_nohw_encrypt
-
-.type   _armv4_AES_encrypt,%function
-.align	2
-_armv4_AES_encrypt:
-	str	lr,[sp,#-4]!		@ push lr
-	ldmia	r11!,{r4-r7}
-	eor	r0,r0,r4
-	ldr	r12,[r11,#240-16]
-	eor	r1,r1,r5
-	eor	r2,r2,r6
-	eor	r3,r3,r7
-	sub	r12,r12,#1
-	mov	lr,#255
-
-	and	r7,lr,r0
-	and	r8,lr,r0,lsr#8
-	and	r9,lr,r0,lsr#16
-	mov	r0,r0,lsr#24
-.Lenc_loop:
-	ldr	r4,[r10,r7,lsl#2]	@ Te3[s0>>0]
-	and	r7,lr,r1,lsr#16	@ i0
-	ldr	r5,[r10,r8,lsl#2]	@ Te2[s0>>8]
-	and	r8,lr,r1
-	ldr	r6,[r10,r9,lsl#2]	@ Te1[s0>>16]
-	and	r9,lr,r1,lsr#8
-	ldr	r0,[r10,r0,lsl#2]	@ Te0[s0>>24]
-	mov	r1,r1,lsr#24
-
-	ldr	r7,[r10,r7,lsl#2]	@ Te1[s1>>16]
-	ldr	r8,[r10,r8,lsl#2]	@ Te3[s1>>0]
-	ldr	r9,[r10,r9,lsl#2]	@ Te2[s1>>8]
-	eor	r0,r0,r7,ror#8
-	ldr	r1,[r10,r1,lsl#2]	@ Te0[s1>>24]
-	and	r7,lr,r2,lsr#8	@ i0
-	eor	r5,r5,r8,ror#8
-	and	r8,lr,r2,lsr#16	@ i1
-	eor	r6,r6,r9,ror#8
-	and	r9,lr,r2
-	ldr	r7,[r10,r7,lsl#2]	@ Te2[s2>>8]
-	eor	r1,r1,r4,ror#24
-	ldr	r8,[r10,r8,lsl#2]	@ Te1[s2>>16]
-	mov	r2,r2,lsr#24
-
-	ldr	r9,[r10,r9,lsl#2]	@ Te3[s2>>0]
-	eor	r0,r0,r7,ror#16
-	ldr	r2,[r10,r2,lsl#2]	@ Te0[s2>>24]
-	and	r7,lr,r3		@ i0
-	eor	r1,r1,r8,ror#8
-	and	r8,lr,r3,lsr#8	@ i1
-	eor	r6,r6,r9,ror#16
-	and	r9,lr,r3,lsr#16	@ i2
-	ldr	r7,[r10,r7,lsl#2]	@ Te3[s3>>0]
-	eor	r2,r2,r5,ror#16
-	ldr	r8,[r10,r8,lsl#2]	@ Te2[s3>>8]
-	mov	r3,r3,lsr#24
-
-	ldr	r9,[r10,r9,lsl#2]	@ Te1[s3>>16]
-	eor	r0,r0,r7,ror#24
-	ldr	r7,[r11],#16
-	eor	r1,r1,r8,ror#16
-	ldr	r3,[r10,r3,lsl#2]	@ Te0[s3>>24]
-	eor	r2,r2,r9,ror#8
-	ldr	r4,[r11,#-12]
-	eor	r3,r3,r6,ror#8
-
-	ldr	r5,[r11,#-8]
-	eor	r0,r0,r7
-	ldr	r6,[r11,#-4]
-	and	r7,lr,r0
-	eor	r1,r1,r4
-	and	r8,lr,r0,lsr#8
-	eor	r2,r2,r5
-	and	r9,lr,r0,lsr#16
-	eor	r3,r3,r6
-	mov	r0,r0,lsr#24
-
-	subs	r12,r12,#1
-	bne	.Lenc_loop
-
-	add	r10,r10,#2
-
-	ldrb	r4,[r10,r7,lsl#2]	@ Te4[s0>>0]
-	and	r7,lr,r1,lsr#16	@ i0
-	ldrb	r5,[r10,r8,lsl#2]	@ Te4[s0>>8]
-	and	r8,lr,r1
-	ldrb	r6,[r10,r9,lsl#2]	@ Te4[s0>>16]
-	and	r9,lr,r1,lsr#8
-	ldrb	r0,[r10,r0,lsl#2]	@ Te4[s0>>24]
-	mov	r1,r1,lsr#24
-
-	ldrb	r7,[r10,r7,lsl#2]	@ Te4[s1>>16]
-	ldrb	r8,[r10,r8,lsl#2]	@ Te4[s1>>0]
-	ldrb	r9,[r10,r9,lsl#2]	@ Te4[s1>>8]
-	eor	r0,r7,r0,lsl#8
-	ldrb	r1,[r10,r1,lsl#2]	@ Te4[s1>>24]
-	and	r7,lr,r2,lsr#8	@ i0
-	eor	r5,r8,r5,lsl#8
-	and	r8,lr,r2,lsr#16	@ i1
-	eor	r6,r9,r6,lsl#8
-	and	r9,lr,r2
-	ldrb	r7,[r10,r7,lsl#2]	@ Te4[s2>>8]
-	eor	r1,r4,r1,lsl#24
-	ldrb	r8,[r10,r8,lsl#2]	@ Te4[s2>>16]
-	mov	r2,r2,lsr#24
-
-	ldrb	r9,[r10,r9,lsl#2]	@ Te4[s2>>0]
-	eor	r0,r7,r0,lsl#8
-	ldrb	r2,[r10,r2,lsl#2]	@ Te4[s2>>24]
-	and	r7,lr,r3		@ i0
-	eor	r1,r1,r8,lsl#16
-	and	r8,lr,r3,lsr#8	@ i1
-	eor	r6,r9,r6,lsl#8
-	and	r9,lr,r3,lsr#16	@ i2
-	ldrb	r7,[r10,r7,lsl#2]	@ Te4[s3>>0]
-	eor	r2,r5,r2,lsl#24
-	ldrb	r8,[r10,r8,lsl#2]	@ Te4[s3>>8]
-	mov	r3,r3,lsr#24
-
-	ldrb	r9,[r10,r9,lsl#2]	@ Te4[s3>>16]
-	eor	r0,r7,r0,lsl#8
-	ldr	r7,[r11,#0]
-	ldrb	r3,[r10,r3,lsl#2]	@ Te4[s3>>24]
-	eor	r1,r1,r8,lsl#8
-	ldr	r4,[r11,#4]
-	eor	r2,r2,r9,lsl#16
-	ldr	r5,[r11,#8]
-	eor	r3,r6,r3,lsl#24
-	ldr	r6,[r11,#12]
-
-	eor	r0,r0,r7
-	eor	r1,r1,r4
-	eor	r2,r2,r5
-	eor	r3,r3,r6
-
-	sub	r10,r10,#2
-	ldr	pc,[sp],#4		@ pop and return
-.size	_armv4_AES_encrypt,.-_armv4_AES_encrypt
-
-.global aes_nohw_set_encrypt_key
-.type   aes_nohw_set_encrypt_key,%function
-.align	5
-aes_nohw_set_encrypt_key:
-_armv4_AES_set_encrypt_key:
-#ifndef	__thumb2__
-	sub	r3,pc,#8		@ aes_nohw_set_encrypt_key
-#else
-	adr	r3,.
-#endif
-	teq	r0,#0
-#ifdef	__thumb2__
-	itt	eq			@ Thumb2 thing, validity check in ARM
-#endif
-	moveq	r0,#-1
-	beq	.Labrt
-	teq	r2,#0
-#ifdef	__thumb2__
-	itt	eq			@ Thumb2 thing, validity check in ARM
-#endif
-	moveq	r0,#-1
-	beq	.Labrt
-
-	teq	r1,#128
-	beq	.Lok
-	teq	r1,#192
-	beq	.Lok
-	teq	r1,#256
-#ifdef	__thumb2__
-	itt	ne			@ Thumb2 thing, validity check in ARM
-#endif
-	movne	r0,#-1
-	bne	.Labrt
-
-.Lok:	stmdb   sp!,{r4-r12,lr}
-	mov	r12,r0		@ inp
-	mov	lr,r1			@ bits
-	mov	r11,r2			@ key
-
-#if defined(__thumb2__) || defined(__APPLE__)
-	adr	r10,AES_Te+1024				@ Te4
-#else
-	sub	r10,r3,#_armv4_AES_set_encrypt_key-AES_Te-1024	@ Te4
-#endif
-
-#if __ARM_ARCH__<7
-	ldrb	r0,[r12,#3]	@ load input data in endian-neutral
-	ldrb	r4,[r12,#2]	@ manner...
-	ldrb	r5,[r12,#1]
-	ldrb	r6,[r12,#0]
-	orr	r0,r0,r4,lsl#8
-	ldrb	r1,[r12,#7]
-	orr	r0,r0,r5,lsl#16
-	ldrb	r4,[r12,#6]
-	orr	r0,r0,r6,lsl#24
-	ldrb	r5,[r12,#5]
-	ldrb	r6,[r12,#4]
-	orr	r1,r1,r4,lsl#8
-	ldrb	r2,[r12,#11]
-	orr	r1,r1,r5,lsl#16
-	ldrb	r4,[r12,#10]
-	orr	r1,r1,r6,lsl#24
-	ldrb	r5,[r12,#9]
-	ldrb	r6,[r12,#8]
-	orr	r2,r2,r4,lsl#8
-	ldrb	r3,[r12,#15]
-	orr	r2,r2,r5,lsl#16
-	ldrb	r4,[r12,#14]
-	orr	r2,r2,r6,lsl#24
-	ldrb	r5,[r12,#13]
-	ldrb	r6,[r12,#12]
-	orr	r3,r3,r4,lsl#8
-	str	r0,[r11],#16
-	orr	r3,r3,r5,lsl#16
-	str	r1,[r11,#-12]
-	orr	r3,r3,r6,lsl#24
-	str	r2,[r11,#-8]
-	str	r3,[r11,#-4]
-#else
-	ldr	r0,[r12,#0]
-	ldr	r1,[r12,#4]
-	ldr	r2,[r12,#8]
-	ldr	r3,[r12,#12]
-#ifdef __ARMEL__
-	rev	r0,r0
-	rev	r1,r1
-	rev	r2,r2
-	rev	r3,r3
-#endif
-	str	r0,[r11],#16
-	str	r1,[r11,#-12]
-	str	r2,[r11,#-8]
-	str	r3,[r11,#-4]
-#endif
-
-	teq	lr,#128
-	bne	.Lnot128
-	mov	r12,#10
-	str	r12,[r11,#240-16]
-	add	r6,r10,#256			@ rcon
-	mov	lr,#255
-
-.L128_loop:
-	and	r5,lr,r3,lsr#24
-	and	r7,lr,r3,lsr#16
-	ldrb	r5,[r10,r5]
-	and	r8,lr,r3,lsr#8
-	ldrb	r7,[r10,r7]
-	and	r9,lr,r3
-	ldrb	r8,[r10,r8]
-	orr	r5,r5,r7,lsl#24
-	ldrb	r9,[r10,r9]
-	orr	r5,r5,r8,lsl#16
-	ldr	r4,[r6],#4			@ rcon[i++]
-	orr	r5,r5,r9,lsl#8
-	eor	r5,r5,r4
-	eor	r0,r0,r5			@ rk[4]=rk[0]^...
-	eor	r1,r1,r0			@ rk[5]=rk[1]^rk[4]
-	str	r0,[r11],#16
-	eor	r2,r2,r1			@ rk[6]=rk[2]^rk[5]
-	str	r1,[r11,#-12]
-	eor	r3,r3,r2			@ rk[7]=rk[3]^rk[6]
-	str	r2,[r11,#-8]
-	subs	r12,r12,#1
-	str	r3,[r11,#-4]
-	bne	.L128_loop
-	sub	r2,r11,#176
-	b	.Ldone
-
-.Lnot128:
-#if __ARM_ARCH__<7
-	ldrb	r8,[r12,#19]
-	ldrb	r4,[r12,#18]
-	ldrb	r5,[r12,#17]
-	ldrb	r6,[r12,#16]
-	orr	r8,r8,r4,lsl#8
-	ldrb	r9,[r12,#23]
-	orr	r8,r8,r5,lsl#16
-	ldrb	r4,[r12,#22]
-	orr	r8,r8,r6,lsl#24
-	ldrb	r5,[r12,#21]
-	ldrb	r6,[r12,#20]
-	orr	r9,r9,r4,lsl#8
-	orr	r9,r9,r5,lsl#16
-	str	r8,[r11],#8
-	orr	r9,r9,r6,lsl#24
-	str	r9,[r11,#-4]
-#else
-	ldr	r8,[r12,#16]
-	ldr	r9,[r12,#20]
-#ifdef __ARMEL__
-	rev	r8,r8
-	rev	r9,r9
-#endif
-	str	r8,[r11],#8
-	str	r9,[r11,#-4]
-#endif
-
-	teq	lr,#192
-	bne	.Lnot192
-	mov	r12,#12
-	str	r12,[r11,#240-24]
-	add	r6,r10,#256			@ rcon
-	mov	lr,#255
-	mov	r12,#8
-
-.L192_loop:
-	and	r5,lr,r9,lsr#24
-	and	r7,lr,r9,lsr#16
-	ldrb	r5,[r10,r5]
-	and	r8,lr,r9,lsr#8
-	ldrb	r7,[r10,r7]
-	and	r9,lr,r9
-	ldrb	r8,[r10,r8]
-	orr	r5,r5,r7,lsl#24
-	ldrb	r9,[r10,r9]
-	orr	r5,r5,r8,lsl#16
-	ldr	r4,[r6],#4			@ rcon[i++]
-	orr	r5,r5,r9,lsl#8
-	eor	r9,r5,r4
-	eor	r0,r0,r9			@ rk[6]=rk[0]^...
-	eor	r1,r1,r0			@ rk[7]=rk[1]^rk[6]
-	str	r0,[r11],#24
-	eor	r2,r2,r1			@ rk[8]=rk[2]^rk[7]
-	str	r1,[r11,#-20]
-	eor	r3,r3,r2			@ rk[9]=rk[3]^rk[8]
-	str	r2,[r11,#-16]
-	subs	r12,r12,#1
-	str	r3,[r11,#-12]
-#ifdef	__thumb2__
-	itt	eq			@ Thumb2 thing, validity check in ARM
-#endif
-	subeq	r2,r11,#216
-	beq	.Ldone
-
-	ldr	r7,[r11,#-32]
-	ldr	r8,[r11,#-28]
-	eor	r7,r7,r3			@ rk[10]=rk[4]^rk[9]
-	eor	r9,r8,r7			@ rk[11]=rk[5]^rk[10]
-	str	r7,[r11,#-8]
-	str	r9,[r11,#-4]
-	b	.L192_loop
-
-.Lnot192:
-#if __ARM_ARCH__<7
-	ldrb	r8,[r12,#27]
-	ldrb	r4,[r12,#26]
-	ldrb	r5,[r12,#25]
-	ldrb	r6,[r12,#24]
-	orr	r8,r8,r4,lsl#8
-	ldrb	r9,[r12,#31]
-	orr	r8,r8,r5,lsl#16
-	ldrb	r4,[r12,#30]
-	orr	r8,r8,r6,lsl#24
-	ldrb	r5,[r12,#29]
-	ldrb	r6,[r12,#28]
-	orr	r9,r9,r4,lsl#8
-	orr	r9,r9,r5,lsl#16
-	str	r8,[r11],#8
-	orr	r9,r9,r6,lsl#24
-	str	r9,[r11,#-4]
-#else
-	ldr	r8,[r12,#24]
-	ldr	r9,[r12,#28]
-#ifdef __ARMEL__
-	rev	r8,r8
-	rev	r9,r9
-#endif
-	str	r8,[r11],#8
-	str	r9,[r11,#-4]
-#endif
-
-	mov	r12,#14
-	str	r12,[r11,#240-32]
-	add	r6,r10,#256			@ rcon
-	mov	lr,#255
-	mov	r12,#7
-
-.L256_loop:
-	and	r5,lr,r9,lsr#24
-	and	r7,lr,r9,lsr#16
-	ldrb	r5,[r10,r5]
-	and	r8,lr,r9,lsr#8
-	ldrb	r7,[r10,r7]
-	and	r9,lr,r9
-	ldrb	r8,[r10,r8]
-	orr	r5,r5,r7,lsl#24
-	ldrb	r9,[r10,r9]
-	orr	r5,r5,r8,lsl#16
-	ldr	r4,[r6],#4			@ rcon[i++]
-	orr	r5,r5,r9,lsl#8
-	eor	r9,r5,r4
-	eor	r0,r0,r9			@ rk[8]=rk[0]^...
-	eor	r1,r1,r0			@ rk[9]=rk[1]^rk[8]
-	str	r0,[r11],#32
-	eor	r2,r2,r1			@ rk[10]=rk[2]^rk[9]
-	str	r1,[r11,#-28]
-	eor	r3,r3,r2			@ rk[11]=rk[3]^rk[10]
-	str	r2,[r11,#-24]
-	subs	r12,r12,#1
-	str	r3,[r11,#-20]
-#ifdef	__thumb2__
-	itt	eq			@ Thumb2 thing, validity check in ARM
-#endif
-	subeq	r2,r11,#256
-	beq	.Ldone
-
-	and	r5,lr,r3
-	and	r7,lr,r3,lsr#8
-	ldrb	r5,[r10,r5]
-	and	r8,lr,r3,lsr#16
-	ldrb	r7,[r10,r7]
-	and	r9,lr,r3,lsr#24
-	ldrb	r8,[r10,r8]
-	orr	r5,r5,r7,lsl#8
-	ldrb	r9,[r10,r9]
-	orr	r5,r5,r8,lsl#16
-	ldr	r4,[r11,#-48]
-	orr	r5,r5,r9,lsl#24
-
-	ldr	r7,[r11,#-44]
-	ldr	r8,[r11,#-40]
-	eor	r4,r4,r5			@ rk[12]=rk[4]^...
-	ldr	r9,[r11,#-36]
-	eor	r7,r7,r4			@ rk[13]=rk[5]^rk[12]
-	str	r4,[r11,#-16]
-	eor	r8,r8,r7			@ rk[14]=rk[6]^rk[13]
-	str	r7,[r11,#-12]
-	eor	r9,r9,r8			@ rk[15]=rk[7]^rk[14]
-	str	r8,[r11,#-8]
-	str	r9,[r11,#-4]
-	b	.L256_loop
-
-.align	2
-.Ldone:	mov	r0,#0
-	ldmia   sp!,{r4-r12,lr}
-.Labrt:
-#if __ARM_ARCH__>=5
-	bx	lr				@ .word	0xe12fff1e
-#else
-	tst	lr,#1
-	moveq	pc,lr			@ be binary compatible with V4, yet
-	.word	0xe12fff1e			@ interoperable with Thumb ISA:-)
-#endif
-.size	aes_nohw_set_encrypt_key,.-aes_nohw_set_encrypt_key
-
-.global aes_nohw_set_decrypt_key
-.type   aes_nohw_set_decrypt_key,%function
-.align	5
-aes_nohw_set_decrypt_key:
-	str	lr,[sp,#-4]!            @ push lr
-	bl	_armv4_AES_set_encrypt_key
-	teq	r0,#0
-	ldr	lr,[sp],#4              @ pop lr
-	bne	.Labrt
-
-	mov	r0,r2			@ aes_nohw_set_encrypt_key preserves r2,
-	mov	r1,r2			@ which is AES_KEY *key
-	b	_armv4_AES_set_enc2dec_key
-.size	aes_nohw_set_decrypt_key,.-aes_nohw_set_decrypt_key
-
-@ void AES_set_enc2dec_key(const AES_KEY *inp,AES_KEY *out)
-.global	AES_set_enc2dec_key
-.type	AES_set_enc2dec_key,%function
-.align	5
-AES_set_enc2dec_key:
-_armv4_AES_set_enc2dec_key:
-	stmdb   sp!,{r4-r12,lr}
-
-	ldr	r12,[r0,#240]
-	mov	r7,r0			@ input
-	add	r8,r0,r12,lsl#4
-	mov	r11,r1			@ output
-	add	r10,r1,r12,lsl#4
-	str	r12,[r1,#240]
-
-.Linv:	ldr	r0,[r7],#16
-	ldr	r1,[r7,#-12]
-	ldr	r2,[r7,#-8]
-	ldr	r3,[r7,#-4]
-	ldr	r4,[r8],#-16
-	ldr	r5,[r8,#16+4]
-	ldr	r6,[r8,#16+8]
-	ldr	r9,[r8,#16+12]
-	str	r0,[r10],#-16
-	str	r1,[r10,#16+4]
-	str	r2,[r10,#16+8]
-	str	r3,[r10,#16+12]
-	str	r4,[r11],#16
-	str	r5,[r11,#-12]
-	str	r6,[r11,#-8]
-	str	r9,[r11,#-4]
-	teq	r7,r8
-	bne	.Linv
-
-	ldr	r0,[r7]
-	ldr	r1,[r7,#4]
-	ldr	r2,[r7,#8]
-	ldr	r3,[r7,#12]
-	str	r0,[r11]
-	str	r1,[r11,#4]
-	str	r2,[r11,#8]
-	str	r3,[r11,#12]
-	sub	r11,r11,r12,lsl#3
-	ldr	r0,[r11,#16]!		@ prefetch tp1
-	mov	r7,#0x80
-	mov	r8,#0x1b
-	orr	r7,r7,#0x8000
-	orr	r8,r8,#0x1b00
-	orr	r7,r7,r7,lsl#16
-	orr	r8,r8,r8,lsl#16
-	sub	r12,r12,#1
-	mvn	r9,r7
-	mov	r12,r12,lsl#2	@ (rounds-1)*4
-
-.Lmix:	and	r4,r0,r7
-	and	r1,r0,r9
-	sub	r4,r4,r4,lsr#7
-	and	r4,r4,r8
-	eor	r1,r4,r1,lsl#1	@ tp2
-
-	and	r4,r1,r7
-	and	r2,r1,r9
-	sub	r4,r4,r4,lsr#7
-	and	r4,r4,r8
-	eor	r2,r4,r2,lsl#1	@ tp4
-
-	and	r4,r2,r7
-	and	r3,r2,r9
-	sub	r4,r4,r4,lsr#7
-	and	r4,r4,r8
-	eor	r3,r4,r3,lsl#1	@ tp8
-
-	eor	r4,r1,r2
-	eor	r5,r0,r3		@ tp9
-	eor	r4,r4,r3		@ tpe
-	eor	r4,r4,r1,ror#24
-	eor	r4,r4,r5,ror#24	@ ^= ROTATE(tpb=tp9^tp2,8)
-	eor	r4,r4,r2,ror#16
-	eor	r4,r4,r5,ror#16	@ ^= ROTATE(tpd=tp9^tp4,16)
-	eor	r4,r4,r5,ror#8	@ ^= ROTATE(tp9,24)
-
-	ldr	r0,[r11,#4]		@ prefetch tp1
-	str	r4,[r11],#4
-	subs	r12,r12,#1
-	bne	.Lmix
-
-	mov	r0,#0
-#if __ARM_ARCH__>=5
-	ldmia	sp!,{r4-r12,pc}
-#else
-	ldmia   sp!,{r4-r12,lr}
-	tst	lr,#1
-	moveq	pc,lr			@ be binary compatible with V4, yet
-	.word	0xe12fff1e			@ interoperable with Thumb ISA:-)
-#endif
-.size	AES_set_enc2dec_key,.-AES_set_enc2dec_key
-
-.type	AES_Td,%object
-.align	5
-AES_Td:
-.word	0x51f4a750, 0x7e416553, 0x1a17a4c3, 0x3a275e96
-.word	0x3bab6bcb, 0x1f9d45f1, 0xacfa58ab, 0x4be30393
-.word	0x2030fa55, 0xad766df6, 0x88cc7691, 0xf5024c25
-.word	0x4fe5d7fc, 0xc52acbd7, 0x26354480, 0xb562a38f
-.word	0xdeb15a49, 0x25ba1b67, 0x45ea0e98, 0x5dfec0e1
-.word	0xc32f7502, 0x814cf012, 0x8d4697a3, 0x6bd3f9c6
-.word	0x038f5fe7, 0x15929c95, 0xbf6d7aeb, 0x955259da
-.word	0xd4be832d, 0x587421d3, 0x49e06929, 0x8ec9c844
-.word	0x75c2896a, 0xf48e7978, 0x99583e6b, 0x27b971dd
-.word	0xbee14fb6, 0xf088ad17, 0xc920ac66, 0x7dce3ab4
-.word	0x63df4a18, 0xe51a3182, 0x97513360, 0x62537f45
-.word	0xb16477e0, 0xbb6bae84, 0xfe81a01c, 0xf9082b94
-.word	0x70486858, 0x8f45fd19, 0x94de6c87, 0x527bf8b7
-.word	0xab73d323, 0x724b02e2, 0xe31f8f57, 0x6655ab2a
-.word	0xb2eb2807, 0x2fb5c203, 0x86c57b9a, 0xd33708a5
-.word	0x302887f2, 0x23bfa5b2, 0x02036aba, 0xed16825c
-.word	0x8acf1c2b, 0xa779b492, 0xf307f2f0, 0x4e69e2a1
-.word	0x65daf4cd, 0x0605bed5, 0xd134621f, 0xc4a6fe8a
-.word	0x342e539d, 0xa2f355a0, 0x058ae132, 0xa4f6eb75
-.word	0x0b83ec39, 0x4060efaa, 0x5e719f06, 0xbd6e1051
-.word	0x3e218af9, 0x96dd063d, 0xdd3e05ae, 0x4de6bd46
-.word	0x91548db5, 0x71c45d05, 0x0406d46f, 0x605015ff
-.word	0x1998fb24, 0xd6bde997, 0x894043cc, 0x67d99e77
-.word	0xb0e842bd, 0x07898b88, 0xe7195b38, 0x79c8eedb
-.word	0xa17c0a47, 0x7c420fe9, 0xf8841ec9, 0x00000000
-.word	0x09808683, 0x322bed48, 0x1e1170ac, 0x6c5a724e
-.word	0xfd0efffb, 0x0f853856, 0x3daed51e, 0x362d3927
-.word	0x0a0fd964, 0x685ca621, 0x9b5b54d1, 0x24362e3a
-.word	0x0c0a67b1, 0x9357e70f, 0xb4ee96d2, 0x1b9b919e
-.word	0x80c0c54f, 0x61dc20a2, 0x5a774b69, 0x1c121a16
-.word	0xe293ba0a, 0xc0a02ae5, 0x3c22e043, 0x121b171d
-.word	0x0e090d0b, 0xf28bc7ad, 0x2db6a8b9, 0x141ea9c8
-.word	0x57f11985, 0xaf75074c, 0xee99ddbb, 0xa37f60fd
-.word	0xf701269f, 0x5c72f5bc, 0x44663bc5, 0x5bfb7e34
-.word	0x8b432976, 0xcb23c6dc, 0xb6edfc68, 0xb8e4f163
-.word	0xd731dcca, 0x42638510, 0x13972240, 0x84c61120
-.word	0x854a247d, 0xd2bb3df8, 0xaef93211, 0xc729a16d
-.word	0x1d9e2f4b, 0xdcb230f3, 0x0d8652ec, 0x77c1e3d0
-.word	0x2bb3166c, 0xa970b999, 0x119448fa, 0x47e96422
-.word	0xa8fc8cc4, 0xa0f03f1a, 0x567d2cd8, 0x223390ef
-.word	0x87494ec7, 0xd938d1c1, 0x8ccaa2fe, 0x98d40b36
-.word	0xa6f581cf, 0xa57ade28, 0xdab78e26, 0x3fadbfa4
-.word	0x2c3a9de4, 0x5078920d, 0x6a5fcc9b, 0x547e4662
-.word	0xf68d13c2, 0x90d8b8e8, 0x2e39f75e, 0x82c3aff5
-.word	0x9f5d80be, 0x69d0937c, 0x6fd52da9, 0xcf2512b3
-.word	0xc8ac993b, 0x10187da7, 0xe89c636e, 0xdb3bbb7b
-.word	0xcd267809, 0x6e5918f4, 0xec9ab701, 0x834f9aa8
-.word	0xe6956e65, 0xaaffe67e, 0x21bccf08, 0xef15e8e6
-.word	0xbae79bd9, 0x4a6f36ce, 0xea9f09d4, 0x29b07cd6
-.word	0x31a4b2af, 0x2a3f2331, 0xc6a59430, 0x35a266c0
-.word	0x744ebc37, 0xfc82caa6, 0xe090d0b0, 0x33a7d815
-.word	0xf104984a, 0x41ecdaf7, 0x7fcd500e, 0x1791f62f
-.word	0x764dd68d, 0x43efb04d, 0xccaa4d54, 0xe49604df
-.word	0x9ed1b5e3, 0x4c6a881b, 0xc12c1fb8, 0x4665517f
-.word	0x9d5eea04, 0x018c355d, 0xfa877473, 0xfb0b412e
-.word	0xb3671d5a, 0x92dbd252, 0xe9105633, 0x6dd64713
-.word	0x9ad7618c, 0x37a10c7a, 0x59f8148e, 0xeb133c89
-.word	0xcea927ee, 0xb761c935, 0xe11ce5ed, 0x7a47b13c
-.word	0x9cd2df59, 0x55f2733f, 0x1814ce79, 0x73c737bf
-.word	0x53f7cdea, 0x5ffdaa5b, 0xdf3d6f14, 0x7844db86
-.word	0xcaaff381, 0xb968c43e, 0x3824342c, 0xc2a3405f
-.word	0x161dc372, 0xbce2250c, 0x283c498b, 0xff0d9541
-.word	0x39a80171, 0x080cb3de, 0xd8b4e49c, 0x6456c190
-.word	0x7bcb8461, 0xd532b670, 0x486c5c74, 0xd0b85742
-@ Td4[256]
-.byte	0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38
-.byte	0xbf, 0x40, 0xa3, 0x9e, 0x81, 0xf3, 0xd7, 0xfb
-.byte	0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87
-.byte	0x34, 0x8e, 0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb
-.byte	0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23, 0x3d
-.byte	0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e
-.byte	0x08, 0x2e, 0xa1, 0x66, 0x28, 0xd9, 0x24, 0xb2
-.byte	0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25
-.byte	0x72, 0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16
-.byte	0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65, 0xb6, 0x92
-.byte	0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda
-.byte	0x5e, 0x15, 0x46, 0x57, 0xa7, 0x8d, 0x9d, 0x84
-.byte	0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a
-.byte	0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06
-.byte	0xd0, 0x2c, 0x1e, 0x8f, 0xca, 0x3f, 0x0f, 0x02
-.byte	0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b
-.byte	0x3a, 0x91, 0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea
-.byte	0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6, 0x73
-.byte	0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85
-.byte	0xe2, 0xf9, 0x37, 0xe8, 0x1c, 0x75, 0xdf, 0x6e
-.byte	0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89
-.byte	0x6f, 0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b
-.byte	0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2, 0x79, 0x20
-.byte	0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4
-.byte	0x1f, 0xdd, 0xa8, 0x33, 0x88, 0x07, 0xc7, 0x31
-.byte	0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f
-.byte	0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d
-.byte	0x2d, 0xe5, 0x7a, 0x9f, 0x93, 0xc9, 0x9c, 0xef
-.byte	0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0
-.byte	0xc8, 0xeb, 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61
-.byte	0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26
-.byte	0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d
-.size	AES_Td,.-AES_Td
-
-@ void aes_nohw_decrypt(const unsigned char *in, unsigned char *out,
-@ 		                  const AES_KEY *key) {
-.global aes_nohw_decrypt
-.type   aes_nohw_decrypt,%function
-.align	5
-aes_nohw_decrypt:
-#ifndef	__thumb2__
-	sub	r3,pc,#8		@ aes_nohw_decrypt
-#else
-	adr	r3,.
-#endif
-	stmdb   sp!,{r1,r4-r12,lr}
-#if defined(__thumb2__) || defined(__APPLE__)
-	adr	r10,AES_Td
-#else
-	sub	r10,r3,#aes_nohw_decrypt-AES_Td	@ Td
-#endif
-	mov	r12,r0		@ inp
-	mov	r11,r2
-#if __ARM_ARCH__<7
-	ldrb	r0,[r12,#3]	@ load input data in endian-neutral
-	ldrb	r4,[r12,#2]	@ manner...
-	ldrb	r5,[r12,#1]
-	ldrb	r6,[r12,#0]
-	orr	r0,r0,r4,lsl#8
-	ldrb	r1,[r12,#7]
-	orr	r0,r0,r5,lsl#16
-	ldrb	r4,[r12,#6]
-	orr	r0,r0,r6,lsl#24
-	ldrb	r5,[r12,#5]
-	ldrb	r6,[r12,#4]
-	orr	r1,r1,r4,lsl#8
-	ldrb	r2,[r12,#11]
-	orr	r1,r1,r5,lsl#16
-	ldrb	r4,[r12,#10]
-	orr	r1,r1,r6,lsl#24
-	ldrb	r5,[r12,#9]
-	ldrb	r6,[r12,#8]
-	orr	r2,r2,r4,lsl#8
-	ldrb	r3,[r12,#15]
-	orr	r2,r2,r5,lsl#16
-	ldrb	r4,[r12,#14]
-	orr	r2,r2,r6,lsl#24
-	ldrb	r5,[r12,#13]
-	ldrb	r6,[r12,#12]
-	orr	r3,r3,r4,lsl#8
-	orr	r3,r3,r5,lsl#16
-	orr	r3,r3,r6,lsl#24
-#else
-	ldr	r0,[r12,#0]
-	ldr	r1,[r12,#4]
-	ldr	r2,[r12,#8]
-	ldr	r3,[r12,#12]
-#ifdef __ARMEL__
-	rev	r0,r0
-	rev	r1,r1
-	rev	r2,r2
-	rev	r3,r3
-#endif
-#endif
-	bl	_armv4_AES_decrypt
-
-	ldr	r12,[sp],#4		@ pop out
-#if __ARM_ARCH__>=7
-#ifdef __ARMEL__
-	rev	r0,r0
-	rev	r1,r1
-	rev	r2,r2
-	rev	r3,r3
-#endif
-	str	r0,[r12,#0]
-	str	r1,[r12,#4]
-	str	r2,[r12,#8]
-	str	r3,[r12,#12]
-#else
-	mov	r4,r0,lsr#24		@ write output in endian-neutral
-	mov	r5,r0,lsr#16		@ manner...
-	mov	r6,r0,lsr#8
-	strb	r4,[r12,#0]
-	strb	r5,[r12,#1]
-	mov	r4,r1,lsr#24
-	strb	r6,[r12,#2]
-	mov	r5,r1,lsr#16
-	strb	r0,[r12,#3]
-	mov	r6,r1,lsr#8
-	strb	r4,[r12,#4]
-	strb	r5,[r12,#5]
-	mov	r4,r2,lsr#24
-	strb	r6,[r12,#6]
-	mov	r5,r2,lsr#16
-	strb	r1,[r12,#7]
-	mov	r6,r2,lsr#8
-	strb	r4,[r12,#8]
-	strb	r5,[r12,#9]
-	mov	r4,r3,lsr#24
-	strb	r6,[r12,#10]
-	mov	r5,r3,lsr#16
-	strb	r2,[r12,#11]
-	mov	r6,r3,lsr#8
-	strb	r4,[r12,#12]
-	strb	r5,[r12,#13]
-	strb	r6,[r12,#14]
-	strb	r3,[r12,#15]
-#endif
-#if __ARM_ARCH__>=5
-	ldmia	sp!,{r4-r12,pc}
-#else
-	ldmia   sp!,{r4-r12,lr}
-	tst	lr,#1
-	moveq	pc,lr			@ be binary compatible with V4, yet
-	.word	0xe12fff1e			@ interoperable with Thumb ISA:-)
-#endif
-.size	aes_nohw_decrypt,.-aes_nohw_decrypt
-
-.type   _armv4_AES_decrypt,%function
-.align	2
-_armv4_AES_decrypt:
-	str	lr,[sp,#-4]!		@ push lr
-	ldmia	r11!,{r4-r7}
-	eor	r0,r0,r4
-	ldr	r12,[r11,#240-16]
-	eor	r1,r1,r5
-	eor	r2,r2,r6
-	eor	r3,r3,r7
-	sub	r12,r12,#1
-	mov	lr,#255
-
-	and	r7,lr,r0,lsr#16
-	and	r8,lr,r0,lsr#8
-	and	r9,lr,r0
-	mov	r0,r0,lsr#24
-.Ldec_loop:
-	ldr	r4,[r10,r7,lsl#2]	@ Td1[s0>>16]
-	and	r7,lr,r1		@ i0
-	ldr	r5,[r10,r8,lsl#2]	@ Td2[s0>>8]
-	and	r8,lr,r1,lsr#16
-	ldr	r6,[r10,r9,lsl#2]	@ Td3[s0>>0]
-	and	r9,lr,r1,lsr#8
-	ldr	r0,[r10,r0,lsl#2]	@ Td0[s0>>24]
-	mov	r1,r1,lsr#24
-
-	ldr	r7,[r10,r7,lsl#2]	@ Td3[s1>>0]
-	ldr	r8,[r10,r8,lsl#2]	@ Td1[s1>>16]
-	ldr	r9,[r10,r9,lsl#2]	@ Td2[s1>>8]
-	eor	r0,r0,r7,ror#24
-	ldr	r1,[r10,r1,lsl#2]	@ Td0[s1>>24]
-	and	r7,lr,r2,lsr#8	@ i0
-	eor	r5,r8,r5,ror#8
-	and	r8,lr,r2		@ i1
-	eor	r6,r9,r6,ror#8
-	and	r9,lr,r2,lsr#16
-	ldr	r7,[r10,r7,lsl#2]	@ Td2[s2>>8]
-	eor	r1,r1,r4,ror#8
-	ldr	r8,[r10,r8,lsl#2]	@ Td3[s2>>0]
-	mov	r2,r2,lsr#24
-
-	ldr	r9,[r10,r9,lsl#2]	@ Td1[s2>>16]
-	eor	r0,r0,r7,ror#16
-	ldr	r2,[r10,r2,lsl#2]	@ Td0[s2>>24]
-	and	r7,lr,r3,lsr#16	@ i0
-	eor	r1,r1,r8,ror#24
-	and	r8,lr,r3,lsr#8	@ i1
-	eor	r6,r9,r6,ror#8
-	and	r9,lr,r3		@ i2
-	ldr	r7,[r10,r7,lsl#2]	@ Td1[s3>>16]
-	eor	r2,r2,r5,ror#8
-	ldr	r8,[r10,r8,lsl#2]	@ Td2[s3>>8]
-	mov	r3,r3,lsr#24
-
-	ldr	r9,[r10,r9,lsl#2]	@ Td3[s3>>0]
-	eor	r0,r0,r7,ror#8
-	ldr	r7,[r11],#16
-	eor	r1,r1,r8,ror#16
-	ldr	r3,[r10,r3,lsl#2]	@ Td0[s3>>24]
-	eor	r2,r2,r9,ror#24
-
-	ldr	r4,[r11,#-12]
-	eor	r0,r0,r7
-	ldr	r5,[r11,#-8]
-	eor	r3,r3,r6,ror#8
-	ldr	r6,[r11,#-4]
-	and	r7,lr,r0,lsr#16
-	eor	r1,r1,r4
-	and	r8,lr,r0,lsr#8
-	eor	r2,r2,r5
-	and	r9,lr,r0
-	eor	r3,r3,r6
-	mov	r0,r0,lsr#24
-
-	subs	r12,r12,#1
-	bne	.Ldec_loop
-
-	add	r10,r10,#1024
-
-	ldr	r5,[r10,#0]		@ prefetch Td4
-	ldr	r6,[r10,#32]
-	ldr	r4,[r10,#64]
-	ldr	r5,[r10,#96]
-	ldr	r6,[r10,#128]
-	ldr	r4,[r10,#160]
-	ldr	r5,[r10,#192]
-	ldr	r6,[r10,#224]
-
-	ldrb	r0,[r10,r0]		@ Td4[s0>>24]
-	ldrb	r4,[r10,r7]		@ Td4[s0>>16]
-	and	r7,lr,r1		@ i0
-	ldrb	r5,[r10,r8]		@ Td4[s0>>8]
-	and	r8,lr,r1,lsr#16
-	ldrb	r6,[r10,r9]		@ Td4[s0>>0]
-	and	r9,lr,r1,lsr#8
-
-	add	r1,r10,r1,lsr#24
-	ldrb	r7,[r10,r7]		@ Td4[s1>>0]
-	ldrb	r1,[r1]		@ Td4[s1>>24]
-	ldrb	r8,[r10,r8]		@ Td4[s1>>16]
-	eor	r0,r7,r0,lsl#24
-	ldrb	r9,[r10,r9]		@ Td4[s1>>8]
-	eor	r1,r4,r1,lsl#8
-	and	r7,lr,r2,lsr#8	@ i0
-	eor	r5,r5,r8,lsl#8
-	and	r8,lr,r2		@ i1
-	ldrb	r7,[r10,r7]		@ Td4[s2>>8]
-	eor	r6,r6,r9,lsl#8
-	ldrb	r8,[r10,r8]		@ Td4[s2>>0]
-	and	r9,lr,r2,lsr#16
-
-	add	r2,r10,r2,lsr#24
-	ldrb	r2,[r2]		@ Td4[s2>>24]
-	eor	r0,r0,r7,lsl#8
-	ldrb	r9,[r10,r9]		@ Td4[s2>>16]
-	eor	r1,r8,r1,lsl#16
-	and	r7,lr,r3,lsr#16	@ i0
-	eor	r2,r5,r2,lsl#16
-	and	r8,lr,r3,lsr#8	@ i1
-	ldrb	r7,[r10,r7]		@ Td4[s3>>16]
-	eor	r6,r6,r9,lsl#16
-	ldrb	r8,[r10,r8]		@ Td4[s3>>8]
-	and	r9,lr,r3		@ i2
-
-	add	r3,r10,r3,lsr#24
-	ldrb	r9,[r10,r9]		@ Td4[s3>>0]
-	ldrb	r3,[r3]		@ Td4[s3>>24]
-	eor	r0,r0,r7,lsl#16
-	ldr	r7,[r11,#0]
-	eor	r1,r1,r8,lsl#8
-	ldr	r4,[r11,#4]
-	eor	r2,r9,r2,lsl#8
-	ldr	r5,[r11,#8]
-	eor	r3,r6,r3,lsl#24
-	ldr	r6,[r11,#12]
-
-	eor	r0,r0,r7
-	eor	r1,r1,r4
-	eor	r2,r2,r5
-	eor	r3,r3,r6
-
-	sub	r10,r10,#1024
-	ldr	pc,[sp],#4		@ pop and return
-.size	_armv4_AES_decrypt,.-_armv4_AES_decrypt
-.asciz	"AES for ARMv4, CRYPTOGAMS by <appro@openssl.org>"
-.align	2
diff --git a/third_party/boringssl/core/cortex-m/ghash.S b/third_party/boringssl/core/cortex-m/ghash.S
deleted file mode 100644
index a1eb97b9c5..0000000000
--- a/third_party/boringssl/core/cortex-m/ghash.S
+++ /dev/null
@@ -1,575 +0,0 @@
-@ Generated by crypto/fipsmodule/modes/asm/ghash-armv4.pl, which carries
-@ this license:
-@
-@ Copyright 2010-2016 The OpenSSL Project Authors. All Rights Reserved.
-@
-@ Licensed under the OpenSSL license (the "License").  You may not use
-@ this file except in compliance with the License.  You can obtain a copy
-@ in the file LICENSE in the source distribution or at
-@ https://www.openssl.org/source/license.html
-
-#define __ARM_ARCH__ 7
-
-.text
-#if defined(__thumb2__) || defined(__clang__)
-.syntax	unified
-#endif
-#if defined(__thumb2__)
-.thumb
-#else
-.code	32
-#endif
-
-#ifdef  __clang__
-#define ldrplb  ldrbpl
-#define ldrneb  ldrbne
-#endif
-
-.type	rem_4bit,%object
-.align	5
-rem_4bit:
-.short	0x0000,0x1C20,0x3840,0x2460
-.short	0x7080,0x6CA0,0x48C0,0x54E0
-.short	0xE100,0xFD20,0xD940,0xC560
-.short	0x9180,0x8DA0,0xA9C0,0xB5E0
-.size	rem_4bit,.-rem_4bit
-
-.type	rem_4bit_get,%function
-rem_4bit_get:
-#if defined(__thumb2__)
-	adr	r2,rem_4bit
-#else
-	sub	r2,pc,#8+32	@ &rem_4bit
-#endif
-	b	.Lrem_4bit_got
-	nop
-	nop
-.size	rem_4bit_get,.-rem_4bit_get
-
-.global	gcm_ghash_4bit
-.type	gcm_ghash_4bit,%function
-.align	4
-gcm_ghash_4bit:
-#if defined(__thumb2__)
-	adr	r12,rem_4bit
-#else
-	sub	r12,pc,#8+48		@ &rem_4bit
-#endif
-	add	r3,r2,r3		@ r3 to point at the end
-	stmdb	sp!,{r3-r11,lr}		@ save r3/end too
-
-	ldmia	r12,{r4-r11}		@ copy rem_4bit ...
-	stmdb	sp!,{r4-r11}		@ ... to stack
-
-	ldrb	r12,[r2,#15]
-	ldrb	r14,[r0,#15]
-.Louter:
-	eor	r12,r12,r14
-	and	r14,r12,#0xf0
-	and	r12,r12,#0x0f
-	mov	r3,#14
-
-	add	r7,r1,r12,lsl#4
-	ldmia	r7,{r4-r7}	@ load Htbl[nlo]
-	add	r11,r1,r14
-	ldrb	r12,[r2,#14]
-
-	and	r14,r4,#0xf		@ rem
-	ldmia	r11,{r8-r11}	@ load Htbl[nhi]
-	add	r14,r14,r14
-	eor	r4,r8,r4,lsr#4
-	ldrh	r8,[sp,r14]		@ rem_4bit[rem]
-	eor	r4,r4,r5,lsl#28
-	ldrb	r14,[r0,#14]
-	eor	r5,r9,r5,lsr#4
-	eor	r5,r5,r6,lsl#28
-	eor	r6,r10,r6,lsr#4
-	eor	r6,r6,r7,lsl#28
-	eor	r7,r11,r7,lsr#4
-	eor	r12,r12,r14
-	and	r14,r12,#0xf0
-	and	r12,r12,#0x0f
-	eor	r7,r7,r8,lsl#16
-
-.Linner:
-	add	r11,r1,r12,lsl#4
-	and	r12,r4,#0xf		@ rem
-	subs	r3,r3,#1
-	add	r12,r12,r12
-	ldmia	r11,{r8-r11}	@ load Htbl[nlo]
-	eor	r4,r8,r4,lsr#4
-	eor	r4,r4,r5,lsl#28
-	eor	r5,r9,r5,lsr#4
-	eor	r5,r5,r6,lsl#28
-	ldrh	r8,[sp,r12]		@ rem_4bit[rem]
-	eor	r6,r10,r6,lsr#4
-#ifdef	__thumb2__
-	it	pl
-#endif
-	ldrbpl	r12,[r2,r3]
-	eor	r6,r6,r7,lsl#28
-	eor	r7,r11,r7,lsr#4
-
-	add	r11,r1,r14
-	and	r14,r4,#0xf		@ rem
-	eor	r7,r7,r8,lsl#16	@ ^= rem_4bit[rem]
-	add	r14,r14,r14
-	ldmia	r11,{r8-r11}	@ load Htbl[nhi]
-	eor	r4,r8,r4,lsr#4
-#ifdef	__thumb2__
-	it	pl
-#endif
-	ldrbpl	r8,[r0,r3]
-	eor	r4,r4,r5,lsl#28
-	eor	r5,r9,r5,lsr#4
-	ldrh	r9,[sp,r14]
-	eor	r5,r5,r6,lsl#28
-	eor	r6,r10,r6,lsr#4
-	eor	r6,r6,r7,lsl#28
-#ifdef	__thumb2__
-	it	pl
-#endif
-	eorpl	r12,r12,r8
-	eor	r7,r11,r7,lsr#4
-#ifdef	__thumb2__
-	itt	pl
-#endif
-	andpl	r14,r12,#0xf0
-	andpl	r12,r12,#0x0f
-	eor	r7,r7,r9,lsl#16	@ ^= rem_4bit[rem]
-	bpl	.Linner
-
-	ldr	r3,[sp,#32]		@ re-load r3/end
-	add	r2,r2,#16
-	mov	r14,r4
-#if __ARM_ARCH__>=7 && defined(__ARMEL__)
-	rev	r4,r4
-	str	r4,[r0,#12]
-#elif defined(__ARMEB__)
-	str	r4,[r0,#12]
-#else
-	mov	r9,r4,lsr#8
-	strb	r4,[r0,#12+3]
-	mov	r10,r4,lsr#16
-	strb	r9,[r0,#12+2]
-	mov	r11,r4,lsr#24
-	strb	r10,[r0,#12+1]
-	strb	r11,[r0,#12]
-#endif
-	cmp	r2,r3
-#if __ARM_ARCH__>=7 && defined(__ARMEL__)
-	rev	r5,r5
-	str	r5,[r0,#8]
-#elif defined(__ARMEB__)
-	str	r5,[r0,#8]
-#else
-	mov	r9,r5,lsr#8
-	strb	r5,[r0,#8+3]
-	mov	r10,r5,lsr#16
-	strb	r9,[r0,#8+2]
-	mov	r11,r5,lsr#24
-	strb	r10,[r0,#8+1]
-	strb	r11,[r0,#8]
-#endif
-	
-#ifdef __thumb2__
-	it	ne
-#endif
-	ldrbne	r12,[r2,#15]
-#if __ARM_ARCH__>=7 && defined(__ARMEL__)
-	rev	r6,r6
-	str	r6,[r0,#4]
-#elif defined(__ARMEB__)
-	str	r6,[r0,#4]
-#else
-	mov	r9,r6,lsr#8
-	strb	r6,[r0,#4+3]
-	mov	r10,r6,lsr#16
-	strb	r9,[r0,#4+2]
-	mov	r11,r6,lsr#24
-	strb	r10,[r0,#4+1]
-	strb	r11,[r0,#4]
-#endif
-	
-#if __ARM_ARCH__>=7 && defined(__ARMEL__)
-	rev	r7,r7
-	str	r7,[r0,#0]
-#elif defined(__ARMEB__)
-	str	r7,[r0,#0]
-#else
-	mov	r9,r7,lsr#8
-	strb	r7,[r0,#0+3]
-	mov	r10,r7,lsr#16
-	strb	r9,[r0,#0+2]
-	mov	r11,r7,lsr#24
-	strb	r10,[r0,#0+1]
-	strb	r11,[r0,#0]
-#endif
-	
-	bne	.Louter
-
-	add	sp,sp,#36
-#if __ARM_ARCH__>=5
-	ldmia	sp!,{r4-r11,pc}
-#else
-	ldmia	sp!,{r4-r11,lr}
-	tst	lr,#1
-	moveq	pc,lr			@ be binary compatible with V4, yet
-	.word	0xe12fff1e			@ interoperable with Thumb ISA:-)
-#endif
-.size	gcm_ghash_4bit,.-gcm_ghash_4bit
-
-.global	gcm_gmult_4bit
-.type	gcm_gmult_4bit,%function
-gcm_gmult_4bit:
-	stmdb	sp!,{r4-r11,lr}
-	ldrb	r12,[r0,#15]
-	b	rem_4bit_get
-.Lrem_4bit_got:
-	and	r14,r12,#0xf0
-	and	r12,r12,#0x0f
-	mov	r3,#14
-
-	add	r7,r1,r12,lsl#4
-	ldmia	r7,{r4-r7}	@ load Htbl[nlo]
-	ldrb	r12,[r0,#14]
-
-	add	r11,r1,r14
-	and	r14,r4,#0xf		@ rem
-	ldmia	r11,{r8-r11}	@ load Htbl[nhi]
-	add	r14,r14,r14
-	eor	r4,r8,r4,lsr#4
-	ldrh	r8,[r2,r14]	@ rem_4bit[rem]
-	eor	r4,r4,r5,lsl#28
-	eor	r5,r9,r5,lsr#4
-	eor	r5,r5,r6,lsl#28
-	eor	r6,r10,r6,lsr#4
-	eor	r6,r6,r7,lsl#28
-	eor	r7,r11,r7,lsr#4
-	and	r14,r12,#0xf0
-	eor	r7,r7,r8,lsl#16
-	and	r12,r12,#0x0f
-
-.Loop:
-	add	r11,r1,r12,lsl#4
-	and	r12,r4,#0xf		@ rem
-	subs	r3,r3,#1
-	add	r12,r12,r12
-	ldmia	r11,{r8-r11}	@ load Htbl[nlo]
-	eor	r4,r8,r4,lsr#4
-	eor	r4,r4,r5,lsl#28
-	eor	r5,r9,r5,lsr#4
-	eor	r5,r5,r6,lsl#28
-	ldrh	r8,[r2,r12]	@ rem_4bit[rem]
-	eor	r6,r10,r6,lsr#4
-#ifdef	__thumb2__
-	it	pl
-#endif
-	ldrbpl	r12,[r0,r3]
-	eor	r6,r6,r7,lsl#28
-	eor	r7,r11,r7,lsr#4
-
-	add	r11,r1,r14
-	and	r14,r4,#0xf		@ rem
-	eor	r7,r7,r8,lsl#16	@ ^= rem_4bit[rem]
-	add	r14,r14,r14
-	ldmia	r11,{r8-r11}	@ load Htbl[nhi]
-	eor	r4,r8,r4,lsr#4
-	eor	r4,r4,r5,lsl#28
-	eor	r5,r9,r5,lsr#4
-	ldrh	r8,[r2,r14]	@ rem_4bit[rem]
-	eor	r5,r5,r6,lsl#28
-	eor	r6,r10,r6,lsr#4
-	eor	r6,r6,r7,lsl#28
-	eor	r7,r11,r7,lsr#4
-#ifdef	__thumb2__
-	itt	pl
-#endif
-	andpl	r14,r12,#0xf0
-	andpl	r12,r12,#0x0f
-	eor	r7,r7,r8,lsl#16	@ ^= rem_4bit[rem]
-	bpl	.Loop
-#if __ARM_ARCH__>=7 && defined(__ARMEL__)
-	rev	r4,r4
-	str	r4,[r0,#12]
-#elif defined(__ARMEB__)
-	str	r4,[r0,#12]
-#else
-	mov	r9,r4,lsr#8
-	strb	r4,[r0,#12+3]
-	mov	r10,r4,lsr#16
-	strb	r9,[r0,#12+2]
-	mov	r11,r4,lsr#24
-	strb	r10,[r0,#12+1]
-	strb	r11,[r0,#12]
-#endif
-	
-#if __ARM_ARCH__>=7 && defined(__ARMEL__)
-	rev	r5,r5
-	str	r5,[r0,#8]
-#elif defined(__ARMEB__)
-	str	r5,[r0,#8]
-#else
-	mov	r9,r5,lsr#8
-	strb	r5,[r0,#8+3]
-	mov	r10,r5,lsr#16
-	strb	r9,[r0,#8+2]
-	mov	r11,r5,lsr#24
-	strb	r10,[r0,#8+1]
-	strb	r11,[r0,#8]
-#endif
-	
-#if __ARM_ARCH__>=7 && defined(__ARMEL__)
-	rev	r6,r6
-	str	r6,[r0,#4]
-#elif defined(__ARMEB__)
-	str	r6,[r0,#4]
-#else
-	mov	r9,r6,lsr#8
-	strb	r6,[r0,#4+3]
-	mov	r10,r6,lsr#16
-	strb	r9,[r0,#4+2]
-	mov	r11,r6,lsr#24
-	strb	r10,[r0,#4+1]
-	strb	r11,[r0,#4]
-#endif
-	
-#if __ARM_ARCH__>=7 && defined(__ARMEL__)
-	rev	r7,r7
-	str	r7,[r0,#0]
-#elif defined(__ARMEB__)
-	str	r7,[r0,#0]
-#else
-	mov	r9,r7,lsr#8
-	strb	r7,[r0,#0+3]
-	mov	r10,r7,lsr#16
-	strb	r9,[r0,#0+2]
-	mov	r11,r7,lsr#24
-	strb	r10,[r0,#0+1]
-	strb	r11,[r0,#0]
-#endif
-	
-#if __ARM_ARCH__>=5
-	ldmia	sp!,{r4-r11,pc}
-#else
-	ldmia	sp!,{r4-r11,lr}
-	tst	lr,#1
-	moveq	pc,lr			@ be binary compatible with V4, yet
-	.word	0xe12fff1e			@ interoperable with Thumb ISA:-)
-#endif
-.size	gcm_gmult_4bit,.-gcm_gmult_4bit
-#ifdef __ARM_NEON__
-.arch	armv7-a
-.fpu	neon
-
-.global	gcm_init_neon
-.type	gcm_init_neon,%function
-.align	4
-gcm_init_neon:
-	vld1.64		d7,[r1]!		@ load H
-	vmov.i8		q8,#0xe1
-	vld1.64		d6,[r1]
-	vshl.i64	d17,#57
-	vshr.u64	d16,#63		@ t0=0xc2....01
-	vdup.8		q9,d7[7]
-	vshr.u64	d26,d6,#63
-	vshr.s8		q9,#7			@ broadcast carry bit
-	vshl.i64	q3,q3,#1
-	vand		q8,q8,q9
-	vorr		d7,d26		@ H<<<=1
-	veor		q3,q3,q8		@ twisted H
-	vstmia		r0,{q3}
-
-	bx	lr					@ bx lr
-.size	gcm_init_neon,.-gcm_init_neon
-
-.global	gcm_gmult_neon
-.type	gcm_gmult_neon,%function
-.align	4
-gcm_gmult_neon:
-	vld1.64		d7,[r0]!		@ load Xi
-	vld1.64		d6,[r0]!
-	vmov.i64	d29,#0x0000ffffffffffff
-	vldmia		r1,{d26-d27}	@ load twisted H
-	vmov.i64	d30,#0x00000000ffffffff
-#ifdef __ARMEL__
-	vrev64.8	q3,q3
-#endif
-	vmov.i64	d31,#0x000000000000ffff
-	veor		d28,d26,d27		@ Karatsuba pre-processing
-	mov		r3,#16
-	b		.Lgmult_neon
-.size	gcm_gmult_neon,.-gcm_gmult_neon
-
-.global	gcm_ghash_neon
-.type	gcm_ghash_neon,%function
-.align	4
-gcm_ghash_neon:
-	vld1.64		d1,[r0]!		@ load Xi
-	vld1.64		d0,[r0]!
-	vmov.i64	d29,#0x0000ffffffffffff
-	vldmia		r1,{d26-d27}	@ load twisted H
-	vmov.i64	d30,#0x00000000ffffffff
-#ifdef __ARMEL__
-	vrev64.8	q0,q0
-#endif
-	vmov.i64	d31,#0x000000000000ffff
-	veor		d28,d26,d27		@ Karatsuba pre-processing
-
-.Loop_neon:
-	vld1.64		d7,[r2]!		@ load inp
-	vld1.64		d6,[r2]!
-#ifdef __ARMEL__
-	vrev64.8	q3,q3
-#endif
-	veor		q3,q0			@ inp^=Xi
-.Lgmult_neon:
-	vext.8		d16, d26, d26, #1	@ A1
-	vmull.p8	q8, d16, d6		@ F = A1*B
-	vext.8		d0, d6, d6, #1	@ B1
-	vmull.p8	q0, d26, d0		@ E = A*B1
-	vext.8		d18, d26, d26, #2	@ A2
-	vmull.p8	q9, d18, d6		@ H = A2*B
-	vext.8		d22, d6, d6, #2	@ B2
-	vmull.p8	q11, d26, d22		@ G = A*B2
-	vext.8		d20, d26, d26, #3	@ A3
-	veor		q8, q8, q0		@ L = E + F
-	vmull.p8	q10, d20, d6		@ J = A3*B
-	vext.8		d0, d6, d6, #3	@ B3
-	veor		q9, q9, q11		@ M = G + H
-	vmull.p8	q0, d26, d0		@ I = A*B3
-	veor		d16, d16, d17	@ t0 = (L) (P0 + P1) << 8
-	vand		d17, d17, d29
-	vext.8		d22, d6, d6, #4	@ B4
-	veor		d18, d18, d19	@ t1 = (M) (P2 + P3) << 16
-	vand		d19, d19, d30
-	vmull.p8	q11, d26, d22		@ K = A*B4
-	veor		q10, q10, q0		@ N = I + J
-	veor		d16, d16, d17
-	veor		d18, d18, d19
-	veor		d20, d20, d21	@ t2 = (N) (P4 + P5) << 24
-	vand		d21, d21, d31
-	vext.8		q8, q8, q8, #15
-	veor		d22, d22, d23	@ t3 = (K) (P6 + P7) << 32
-	vmov.i64	d23, #0
-	vext.8		q9, q9, q9, #14
-	veor		d20, d20, d21
-	vmull.p8	q0, d26, d6		@ D = A*B
-	vext.8		q11, q11, q11, #12
-	vext.8		q10, q10, q10, #13
-	veor		q8, q8, q9
-	veor		q10, q10, q11
-	veor		q0, q0, q8
-	veor		q0, q0, q10
-	veor		d6,d6,d7	@ Karatsuba pre-processing
-	vext.8		d16, d28, d28, #1	@ A1
-	vmull.p8	q8, d16, d6		@ F = A1*B
-	vext.8		d2, d6, d6, #1	@ B1
-	vmull.p8	q1, d28, d2		@ E = A*B1
-	vext.8		d18, d28, d28, #2	@ A2
-	vmull.p8	q9, d18, d6		@ H = A2*B
-	vext.8		d22, d6, d6, #2	@ B2
-	vmull.p8	q11, d28, d22		@ G = A*B2
-	vext.8		d20, d28, d28, #3	@ A3
-	veor		q8, q8, q1		@ L = E + F
-	vmull.p8	q10, d20, d6		@ J = A3*B
-	vext.8		d2, d6, d6, #3	@ B3
-	veor		q9, q9, q11		@ M = G + H
-	vmull.p8	q1, d28, d2		@ I = A*B3
-	veor		d16, d16, d17	@ t0 = (L) (P0 + P1) << 8
-	vand		d17, d17, d29
-	vext.8		d22, d6, d6, #4	@ B4
-	veor		d18, d18, d19	@ t1 = (M) (P2 + P3) << 16
-	vand		d19, d19, d30
-	vmull.p8	q11, d28, d22		@ K = A*B4
-	veor		q10, q10, q1		@ N = I + J
-	veor		d16, d16, d17
-	veor		d18, d18, d19
-	veor		d20, d20, d21	@ t2 = (N) (P4 + P5) << 24
-	vand		d21, d21, d31
-	vext.8		q8, q8, q8, #15
-	veor		d22, d22, d23	@ t3 = (K) (P6 + P7) << 32
-	vmov.i64	d23, #0
-	vext.8		q9, q9, q9, #14
-	veor		d20, d20, d21
-	vmull.p8	q1, d28, d6		@ D = A*B
-	vext.8		q11, q11, q11, #12
-	vext.8		q10, q10, q10, #13
-	veor		q8, q8, q9
-	veor		q10, q10, q11
-	veor		q1, q1, q8
-	veor		q1, q1, q10
-	vext.8		d16, d27, d27, #1	@ A1
-	vmull.p8	q8, d16, d7		@ F = A1*B
-	vext.8		d4, d7, d7, #1	@ B1
-	vmull.p8	q2, d27, d4		@ E = A*B1
-	vext.8		d18, d27, d27, #2	@ A2
-	vmull.p8	q9, d18, d7		@ H = A2*B
-	vext.8		d22, d7, d7, #2	@ B2
-	vmull.p8	q11, d27, d22		@ G = A*B2
-	vext.8		d20, d27, d27, #3	@ A3
-	veor		q8, q8, q2		@ L = E + F
-	vmull.p8	q10, d20, d7		@ J = A3*B
-	vext.8		d4, d7, d7, #3	@ B3
-	veor		q9, q9, q11		@ M = G + H
-	vmull.p8	q2, d27, d4		@ I = A*B3
-	veor		d16, d16, d17	@ t0 = (L) (P0 + P1) << 8
-	vand		d17, d17, d29
-	vext.8		d22, d7, d7, #4	@ B4
-	veor		d18, d18, d19	@ t1 = (M) (P2 + P3) << 16
-	vand		d19, d19, d30
-	vmull.p8	q11, d27, d22		@ K = A*B4
-	veor		q10, q10, q2		@ N = I + J
-	veor		d16, d16, d17
-	veor		d18, d18, d19
-	veor		d20, d20, d21	@ t2 = (N) (P4 + P5) << 24
-	vand		d21, d21, d31
-	vext.8		q8, q8, q8, #15
-	veor		d22, d22, d23	@ t3 = (K) (P6 + P7) << 32
-	vmov.i64	d23, #0
-	vext.8		q9, q9, q9, #14
-	veor		d20, d20, d21
-	vmull.p8	q2, d27, d7		@ D = A*B
-	vext.8		q11, q11, q11, #12
-	vext.8		q10, q10, q10, #13
-	veor		q8, q8, q9
-	veor		q10, q10, q11
-	veor		q2, q2, q8
-	veor		q2, q2, q10
-	veor		q1,q1,q0		@ Karatsuba post-processing
-	veor		q1,q1,q2
-	veor		d1,d1,d2
-	veor		d4,d4,d3	@ Xh|Xl - 256-bit result
-
-	@ equivalent of reduction_avx from ghash-x86_64.pl
-	vshl.i64	q9,q0,#57		@ 1st phase
-	vshl.i64	q10,q0,#62
-	veor		q10,q10,q9		@
-	vshl.i64	q9,q0,#63
-	veor		q10, q10, q9		@
- 	veor		d1,d1,d20	@
-	veor		d4,d4,d21
-
-	vshr.u64	q10,q0,#1		@ 2nd phase
-	veor		q2,q2,q0
-	veor		q0,q0,q10		@
-	vshr.u64	q10,q10,#6
-	vshr.u64	q0,q0,#1		@
-	veor		q0,q0,q2		@
-	veor		q0,q0,q10		@
-
-	subs		r3,#16
-	bne		.Loop_neon
-
-#ifdef __ARMEL__
-	vrev64.8	q0,q0
-#endif
-	sub		r0,#16
-	vst1.64		d1,[r0]!		@ write out Xi
-	vst1.64		d0,[r0]
-
-	bx	lr					@ bx lr
-.size	gcm_ghash_neon,.-gcm_ghash_neon
-#endif
-.asciz  "GHASH for ARMv4/NEON, CRYPTOGAMS by <appro@openssl.org>"
-.align  2
diff --git a/third_party/boringssl/include/aes-gcm.h b/third_party/boringssl/include/aes-gcm.h
deleted file mode 100644
index e3ef457224..0000000000
--- a/third_party/boringssl/include/aes-gcm.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/* ====================================================================
- * Copyright (c) 2008 The OpenSSL Project.  All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * 3. All advertising materials mentioning features or use of this
- *    software must display the following acknowledgment:
- *    "This product includes software developed by the OpenSSL Project
- *    for use in the OpenSSL Toolkit. (http://www.openssl.org/)"
- *
- * 4. The names "OpenSSL Toolkit" and "OpenSSL Project" must not be used to
- *    endorse or promote products derived from this software without
- *    prior written permission. For written permission, please contact
- *    openssl-core@openssl.org.
- *
- * 5. Products derived from this software may not be called "OpenSSL"
- *    nor may "OpenSSL" appear in their names without prior written
- *    permission of the OpenSSL Project.
- *
- * 6. Redistributions of any form whatsoever must retain the following
- *    acknowledgment:
- *    "This product includes software developed by the OpenSSL Project
- *    for use in the OpenSSL Toolkit (http://www.openssl.org/)"
- *
- * THIS SOFTWARE IS PROVIDED BY THE OpenSSL PROJECT ``AS IS'' AND ANY
- * EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE OpenSSL PROJECT OR
- * ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
- * OF THE POSSIBILITY OF SUCH DAMAGE.
- * ==================================================================== */
-
-#ifndef __CROS_EC_AES_GCM_H
-#define __CROS_EC_AES_GCM_H
-
-#include "common.h"
-#include "endian.h"
-#include "util.h"
-
-// block128_f is the type of a 128-bit, block cipher.
-typedef void (*block128_f)(const uint8_t in[16], uint8_t out[16],
-                           const void *key);
-
-// GCM definitions
-typedef struct { uint64_t hi,lo; } u128;
-
-// gmult_func multiplies |Xi| by the GCM key and writes the result back to
-// |Xi|.
-typedef void (*gmult_func)(uint64_t Xi[2], const u128 Htable[16]);
-
-// ghash_func repeatedly multiplies |Xi| by the GCM key and adds in blocks from
-// |inp|. The result is written back to |Xi| and the |len| argument must be a
-// multiple of 16.
-typedef void (*ghash_func)(uint64_t Xi[2], const u128 Htable[16],
-                           const uint8_t *inp, size_t len);
-
-// This differs from upstream's |gcm128_context| in that it does not have the
-// |key| pointer, in order to make it |memcpy|-friendly. Rather the key is
-// passed into each call that needs it.
-struct gcm128_context {
-  // Following 6 names follow names in GCM specification
-  union {
-    uint64_t u[2];
-    uint32_t d[4];
-    uint8_t c[16];
-    size_t t[16 / sizeof(size_t)];
-  } Yi, EKi, EK0, len, Xi;
-
-  // Note that the order of |Xi|, |H| and |Htable| is fixed by the MOVBE-based,
-  // x86-64, GHASH assembly.
-  u128 H;
-  u128 Htable[16];
-  gmult_func gmult;
-  ghash_func ghash;
-
-  unsigned int mres, ares;
-  block128_f block;
-};
-
-
-// GCM.
-//
-// This API differs from the upstream API slightly. The |GCM128_CONTEXT| does
-// not have a |key| pointer that points to the key as upstream's version does.
-// Instead, every function takes a |key| parameter. This way |GCM128_CONTEXT|
-// can be safely copied.
-
-typedef struct gcm128_context GCM128_CONTEXT;
-
-// CRYPTO_gcm128_init initialises |ctx| to use |block| (typically AES) with
-// the given key. |block_is_hwaes| is one if |block| is |aes_hw_encrypt|.
-void CRYPTO_gcm128_init(GCM128_CONTEXT *ctx, const void *key,
-                                       block128_f block, int block_is_hwaes);
-
-// CRYPTO_gcm128_setiv sets the IV (nonce) for |ctx|. The |key| must be the
-// same key that was passed to |CRYPTO_gcm128_init|.
-void CRYPTO_gcm128_setiv(GCM128_CONTEXT *ctx, const void *key,
-                                        const uint8_t *iv, size_t iv_len);
-
-// CRYPTO_gcm128_aad sets the authenticated data for an instance of GCM.
-// This must be called before and data is encrypted. It returns one on success
-// and zero otherwise.
-int CRYPTO_gcm128_aad(GCM128_CONTEXT *ctx, const uint8_t *aad,
-                                     size_t len);
-
-// CRYPTO_gcm128_encrypt encrypts |len| bytes from |in| to |out|. The |key|
-// must be the same key that was passed to |CRYPTO_gcm128_init|. It returns one
-// on success and zero otherwise.
-int CRYPTO_gcm128_encrypt(GCM128_CONTEXT *ctx, const void *key,
-                                         const uint8_t *in, uint8_t *out,
-                                         size_t len);
-
-// CRYPTO_gcm128_decrypt decrypts |len| bytes from |in| to |out|. The |key|
-// must be the same key that was passed to |CRYPTO_gcm128_init|. It returns one
-// on success and zero otherwise.
-int CRYPTO_gcm128_decrypt(GCM128_CONTEXT *ctx, const void *key,
-                                         const uint8_t *in, uint8_t *out,
-                                         size_t len);
-
-// CRYPTO_gcm128_finish calculates the authenticator and compares it against
-// |len| bytes of |tag|. It returns one on success and zero otherwise.
-int CRYPTO_gcm128_finish(GCM128_CONTEXT *ctx, const uint8_t *tag,
-                                        size_t len);
-
-// CRYPTO_gcm128_tag calculates the authenticator and copies it into |tag|.
-// The minimum of |len| and 16 bytes are copied into |tag|.
-void CRYPTO_gcm128_tag(GCM128_CONTEXT *ctx, uint8_t *tag,
-                                      size_t len);
-
-
-#endif  // __CROS_EC_AES_GCM_H
diff --git a/third_party/boringssl/include/aes.h b/third_party/boringssl/include/aes.h
deleted file mode 100644
index 6418a350eb..0000000000
--- a/third_party/boringssl/include/aes.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/* ====================================================================
- * Copyright (c) 2002-2006 The OpenSSL Project.  All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer. 
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * 3. All advertising materials mentioning features or use of this
- *    software must display the following acknowledgment:
- *    "This product includes software developed by the OpenSSL Project
- *    for use in the OpenSSL Toolkit. (http://www.openssl.org/)"
- *
- * 4. The names "OpenSSL Toolkit" and "OpenSSL Project" must not be used to
- *    endorse or promote products derived from this software without
- *    prior written permission. For written permission, please contact
- *    openssl-core@openssl.org.
- *
- * 5. Products derived from this software may not be called "OpenSSL"
- *    nor may "OpenSSL" appear in their names without prior written
- *    permission of the OpenSSL Project.
- *
- * 6. Redistributions of any form whatsoever must retain the following
- *    acknowledgment:
- *    "This product includes software developed by the OpenSSL Project
- *    for use in the OpenSSL Toolkit (http://www.openssl.org/)"
- *
- * THIS SOFTWARE IS PROVIDED BY THE OpenSSL PROJECT ``AS IS'' AND ANY
- * EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE OpenSSL PROJECT OR
- * ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
- * OF THE POSSIBILITY OF SUCH DAMAGE.
- * ==================================================================== */
-
-#ifndef __CROS_EC_AES_H
-#define __CROS_EC_AES_H
-
-#include <stdint.h>
-
-#define AES_ENCRYPT 1
-#define AES_DECRYPT 0
-
-/* AES_MAXNR is the maximum number of AES rounds. */
-#define AES_MAXNR 14
-
-#define AES_BLOCK_SIZE 16
-
-/*
- * aes_key_st should be an opaque type, but EVP requires that the size be
- * known.
- */
-struct aes_key_st {
-  uint32_t rd_key[4 * (AES_MAXNR + 1)];
-  unsigned rounds;
-};
-typedef struct aes_key_st AES_KEY;
-
-/*
- * These functions are provided by either common/aes.c, or assembly code,
- * and should not be called directly.
- */
-void aes_nohw_encrypt(const uint8_t *in, uint8_t *out, const AES_KEY *key);
-void aes_nohw_decrypt(const uint8_t *in, uint8_t *out, const AES_KEY *key);
-int aes_nohw_set_encrypt_key(const uint8_t *key, unsigned bits,
-                             AES_KEY *aeskey);
-int aes_nohw_set_decrypt_key(const uint8_t *key, unsigned bits,
-                             AES_KEY *aeskey);
-
-/**
- * AES_set_encrypt_key configures |aeskey| to encrypt with the |bits|-bit key,
- * |key|.
- *
- * WARNING: unlike other OpenSSL functions, this returns zero on success and a
- * negative number on error.
- */
-static inline int AES_set_encrypt_key(const uint8_t *key, unsigned int bits,
-				      AES_KEY *aeskey)
-{
-	return aes_nohw_set_encrypt_key(key, bits, aeskey);
-}
-
-/**
- * AES_set_decrypt_key configures |aeskey| to decrypt with the |bits|-bit key,
- * |key|.
- *
- * WARNING: unlike other OpenSSL functions, this returns zero on success and a
- * negative number on error.
- */
-static inline int AES_set_decrypt_key(const uint8_t *key, unsigned int bits,
-				      AES_KEY *aeskey)
-{
-	return aes_nohw_set_decrypt_key(key, bits, aeskey);
-}
-
-/**
- * AES_encrypt encrypts a single block from |in| to |out| with |key|. The |in|
- * and |out| pointers may overlap.
- */
-static inline void AES_encrypt(const uint8_t *in, uint8_t *out,
-			       const AES_KEY *key)
-{
-	aes_nohw_encrypt(in, out, key);
-}
-
-/**
- * AES_decrypt decrypts a single block from |in| to |out| with |key|. The |in|
- * and |out| pointers may overlap.
- */
-static inline void AES_decrypt(const uint8_t *in, uint8_t *out,
-			const AES_KEY *key)
-{
-	aes_nohw_decrypt(in, out, key);
-}
-
-#endif  /* __CROS_EC_AES_H */
diff --git a/third_party/boringssl/include/aes_gcm_helpers.h b/third_party/boringssl/include/aes_gcm_helpers.h
new file mode 100644
index 0000000000..7c902169b7
--- /dev/null
+++ b/third_party/boringssl/include/aes_gcm_helpers.h
@@ -0,0 +1,35 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Helpers for the boringssl AEC GCM interface. */
+
+#ifndef __CROS_EC_AES_GCM_HELPERS_H
+#define __CROS_EC_AES_GCM_HELPERS_H
+
+#include "openssl/aes.h"
+#include "string.h"
+
+/* These must be included after the "openssl/aes.h" */
+#include "crypto/fipsmodule/aes/internal.h"
+#include "crypto/fipsmodule/modes/internal.h"
+
+/* CRYPTO_gcm128_init initialises |ctx| to use |block| (typically AES) with
+ * the given key. |block_is_hwaes| is one if |block| is |aes_hw_encrypt|.
+ *
+ * This API was removed in upstream:
+ * https://boringssl-review.googlesource.com/c/boringssl/+/32004
+ *
+ * Note: The content of GCM128_CONTEXT must be initialized by this function.
+ * Passing the context that remain uninitialized parts into the other
+ * CRYPTO_gcm128_ functions will result undefined behavior.
+ */
+static inline void CRYPTO_gcm128_init(GCM128_CONTEXT *ctx, const AES_KEY *key,
+				      block128_f block, int block_is_hwaes)
+{
+	memset(ctx, 0, sizeof(*ctx));
+	CRYPTO_gcm128_init_key(&ctx->gcm_key, key, block, block_is_hwaes);
+}
+
+#endif /* __CROS_EC_AES_GCM_HELPERS_H */
diff --git a/third_party/boringssl/include/curve25519.h b/third_party/boringssl/include/curve25519.h
index 8287c94466..05cebeed99 100644
--- a/third_party/boringssl/include/curve25519.h
+++ b/third_party/boringssl/include/curve25519.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/third_party/boringssl/test/x25519.c b/third_party/boringssl/test/x25519.c
index dac8795b63..cd773653e5 100644
--- a/third_party/boringssl/test/x25519.c
+++ b/third_party/boringssl/test/x25519.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2015, Google Inc.
+/* Copyright 2015 Google LLC
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -180,7 +180,7 @@ static void test_x25519_speed(void)
 	ccprintf("X25519 duration %lld us\n", (long long)(t1.val - t0.val));
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	watchdog_reload();
 	/* do not check speed, just as a benchmark */
diff --git a/third_party/incbin/README.md b/third_party/incbin/README.md
index cada41fa16..da32103e9e 100644
--- a/third_party/incbin/README.md
+++ b/third_party/incbin/README.md
@@ -4,7 +4,7 @@ Include binary files in your C/C++ applications with ease
 
 ## Example
 
-``` c
+```c
     #include "incbin.h"
 
     INCBIN(Icon, "icon.png");
@@ -28,52 +28,56 @@ Include binary files in your C/C++ applications with ease
 
 Known to work on the following compilers
 
-* GCC
-* Clang
-* PathScale
-* Intel
-* Solaris & Sun Studio
-* Green Hills
-* SNC (ProDG)
-* Diab C++ (WindRiver)
-* XCode
-* ArmCC
-* RealView
-* ImageCraft
-* Stratus VOS C
-* TinyCC
-* cparser & libfirm
-* LCC
-* MSVC _See MSVC below_
-
-If your compiler is not listed, as long as it supports GCC inline assembler, this
-should work.
+*   GCC
+*   Clang
+*   PathScale
+*   Intel
+*   Solaris & Sun Studio
+*   Green Hills
+*   SNC (ProDG)
+*   Diab C++ (WindRiver)
+*   XCode
+*   ArmCC
+*   RealView
+*   ImageCraft
+*   Stratus VOS C
+*   TinyCC
+*   cparser & libfirm
+*   LCC
+*   MSVC _See MSVC below_
+
+If your compiler is not listed, as long as it supports GCC inline assembler,
+this should work.
 
 ## MISRA
-INCBIN can be used in MISRA C setting. However it should be independently checked
-due to its use of inline assembly to achieve what it does. Independent verification
-of the header has been done several times based on commit: 7e327a28ba5467c4202ec37874beca7084e4b08c
+
+INCBIN can be used in MISRA C setting. However it should be independently
+checked due to its use of inline assembly to achieve what it does. Independent
+verification of the header has been done several times based on commit:
+7e327a28ba5467c4202ec37874beca7084e4b08c
 
 ## Alignment
 
-The data included by this tool will be aligned on the architectures word boundary
-unless some variant of SIMD is detected, then it's aligned on a byte boundary that
-respects SIMD convention just incase your binary data may be used in vectorized
-code. The table of the alignments for SIMD this header recognizes is as follows:
+The data included by this tool will be aligned on the architectures word
+boundary unless some variant of SIMD is detected, then it's aligned on a byte
+boundary that respects SIMD convention just in case your binary data may be used
+in vectorized code. The table of the alignments for SIMD this header recognizes
+is as follows:
 
-| SIMD                                    | Alignment |
-|-----------------------------------------|-----------|
-| SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2  | 16        |
-| Neon                                    | 16        |
-| AVX, AVX2                               | 32        |
-| AVX512                                  | 64        |
+SIMD                                   | Alignment
+-------------------------------------- | ---------
+SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 | 16
+Neon                                   | 16
+AVX, AVX2                              | 32
+AVX512                                 | 64
 
 ## Prefix
+
 By default, `incbin.h` emits symbols with a `g` prefix. This can be adjusted by
 defining `INCBIN_PREFIX` before including `incbin.h` with a desired prefix. For
 instance
 
-``` c
+```c
     #define INCBIN_PREFIX g_
     #include "incbin.h"
     INCBIN(test, "test.txt");
@@ -84,9 +88,10 @@ instance
     // const unsigned int g_testSize;
 ```
 
-You can also choose to have no prefix by defining the prefix with nothing, for example:
+You can also choose to have no prefix by defining the prefix with nothing, for
+example:
 
-``` c
+```c
     #define INCBIN_PREFIX
     #include "incbin.h"
     INCBIN(test, "test.txt");
@@ -98,16 +103,17 @@ You can also choose to have no prefix by defining the prefix with nothing, for e
 ```
 
 ## Style
-By default, `incbin.h` emits symbols with `CamelCase` style. This can be adjusted
-by defining `INCBIN_STYLE` before including `incbin.h` to change the style. There
-are two possible styles to choose from
 
-* INCBIN_STYLE_CAMEL (CamelCase)
-* INCBIN_STYLE_SNAKE (snake_case)
+By default, `incbin.h` emits symbols with `CamelCase` style. This can be
+adjusted by defining `INCBIN_STYLE` before including `incbin.h` to change the
+style. There are two possible styles to choose from
+
+*   INCBIN_STYLE_CAMEL (CamelCase)
+*   INCBIN_STYLE_SNAKE (snake_case)
 
 For instance:
 
-``` c
+```c
     #define INCBIN_STYLE INCBIN_STYLE_SNAKE
     #include "incbin.h"
     INCBIN(test, "test.txt");
@@ -122,14 +128,15 @@ Combining both the style and prefix allows for you to adjust `incbin.h` to suite
 your existing style and practices.
 
 ## Overriding Linker Output section
+
 By default, `incbin.h` emits into the read-only linker output section used on
-the detected platform. If you need to override this for whatever reason, you
-can manually specify the linker output section.
+the detected platform. If you need to override this for whatever reason, you can
+manually specify the linker output section.
 
 For example, to emit data into program memory for
 [esp8266/Arduino](github.com/esp8266/Arduino):
 
-``` c
+```c
 #define INCBIN_OUTPUT_SECTION ".irom.text"
 #include "incbin.h"
 INCBIN(Foo, "foo.txt");
@@ -141,27 +148,27 @@ INCBIN(Foo, "foo.txt");
 `INCBIN` is a macro which uses the inline assembler provided by almost all
 compilers to include binary files. It achieves this by utilizing the `.incbin`
 directive of the inline assembler. It then uses the assembler to calculate the
-size of the included binary and exports two global symbols that can be externally
-referenced in other translation units which contain the data and size of the
-included binary data respectively.
+size of the included binary and exports two global symbols that can be
+externally referenced in other translation units which contain the data and size
+of the included binary data respectively.
 
 ## MSVC
 
 Supporting MSVC is slightly harder as MSVC lacks an inline assembler which can
 include data. To support this we ship a tool which can process source files
 containing `INCBIN` macro usage and generate an external source file containing
-the data of all of them combined. This file is named `data.c` by default.
-Just include it into your build and use the `incbin.h` to reference data as
-needed. It's suggested you integrate this tool as part of your projects's
-pre-build events so that this can be automated. A more comprehensive list of
-options for this tool can be viewed by invoking the tool with `-help`
+the data of all of them combined. This file is named `data.c` by default. Just
+include it into your build and use the `incbin.h` to reference data as needed.
+It's suggested you integrate this tool as part of your projects's pre-build
+events so that this can be automated. A more comprehensive list of options for
+this tool can be viewed by invoking the tool with `-help`
 
 If you're using a custom prefix, be sure to specify the prefix on the command
 line with `-p <prefix>` so that everything matches up; similarly, if you're
-using a custom style, be sure to specify the style on the command line with
-`-S <style>` as well.
+using a custom style, be sure to specify the style on the command line with `-S
+<style>` as well.
 
 ## Miscellaneous
 
-Documentation for the API is provided by the header using Doxygen notation.
-For licensing information see UNLICENSE.
+Documentation for the API is provided by the header using Doxygen notation. For
+licensing information see UNLICENSE.
diff --git a/third_party/libaeabi-cortexm0/core/cortex-m/uldivmod.S b/third_party/libaeabi-cortexm0/core/cortex-m/uldivmod.S
index da60793e67..63f060891b 100644
--- a/third_party/libaeabi-cortexm0/core/cortex-m/uldivmod.S
+++ b/third_party/libaeabi-cortexm0/core/cortex-m/uldivmod.S
@@ -176,4 +176,5 @@ L_done_sub4:
 
 __aeabi_ldiv0:
 	ldr	SOFTWARE_PANIC_REASON_REG, =PANIC_SW_DIV_ZERO
+	mov	SOFTWARE_PANIC_INFO_REG, r14
 	bl	exception_panic
diff --git a/third_party/libaeabi-cortexm0/core/cortex-m0/div.S b/third_party/libaeabi-cortexm0/core/cortex-m0/div.S
index 898ecafe83..b3f61df632 100644
--- a/third_party/libaeabi-cortexm0/core/cortex-m0/div.S
+++ b/third_party/libaeabi-cortexm0/core/cortex-m0/div.S
@@ -49,7 +49,7 @@ __aeabi_idiv:
 
 L_num_pos:
 	cmp	r1, #0
-	bge	__aeabi_uidivmod
+	bge	Luidivmod
 
 	rsbs	r1, r1, #0		@ den = -den
 
@@ -94,7 +94,7 @@ L_neg_both:
 
 L_num_pos_bis:
 	cmp	r1, #0
-	bge	__aeabi_uidivmod
+	bge	Luidivmod
 
 	rsbs	r1, r1, #0		@ den = -den
 	push	{lr}
@@ -125,6 +125,7 @@ __aeabi_uidiv:
 __aeabi_uidivmod:
 
 
+Luidivmod:
 	cmp	r1, #0
 	bne	L_no_div0
 	b	__aeabi_idiv0
@@ -163,4 +164,5 @@ L_dont_sub0:
 
 __aeabi_idiv0:
 	ldr	SOFTWARE_PANIC_REASON_REG, =PANIC_SW_DIV_ZERO
+	mov	SOFTWARE_PANIC_INFO_REG, r14
 	bl	exception_panic
diff --git a/third_party/libaeabi-cortexm0/core/cortex-m0/uldivmod.S b/third_party/libaeabi-cortexm0/core/cortex-m0/uldivmod.S
index 269645268b..6c0a469d65 100644
--- a/third_party/libaeabi-cortexm0/core/cortex-m0/uldivmod.S
+++ b/third_party/libaeabi-cortexm0/core/cortex-m0/uldivmod.S
@@ -174,4 +174,5 @@ L_dont_sub4:
 
 __aeabi_ldiv0:
 	ldr	SOFTWARE_PANIC_REASON_REG, =PANIC_SW_DIV_ZERO
+	mov	SOFTWARE_PANIC_INFO_REG, r14
 	bl	exception_panic
diff --git a/third_party/rules.mk b/third_party/rules.mk
new file mode 100644
index 0000000000..93097c9b5c
--- /dev/null
+++ b/third_party/rules.mk
@@ -0,0 +1,161 @@
+# -*- makefile -*-
+# vim: set filetype=make :
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Embedded Controller firmware build system - third_party rules/targets
+#
+
+# Build and link against libcryptoc.
+# See https://chromium.googlesource.com/chromiumos/third_party/cryptoc .
+ifeq ($(CONFIG_LIBCRYPTOC),y)
+
+# The cryptoc path can be overridden on invocation, as in the following example:
+# $ make CRYPTOC_DIR=~/src/cryptoc BOARD=bloonchipper
+CRYPTOC_DIR ?= ../../third_party/cryptoc
+
+# SUPPORT_UNALIGNED indicates to libcryptoc that provided data buffers
+# may be unaligned and please handle them safely.
+cmd_libcryptoc = $(MAKE) -C $(CRYPTOC_DIR) \
+	obj=$(realpath $(out))/cryptoc \
+	SUPPORT_UNALIGNED=1
+cmd_libcryptoc_clean = $(cmd_libcryptoc) -q && echo clean
+
+CPPFLAGS += -I$(CRYPTOC_DIR)/include
+CRYPTOC_LDFLAGS := -L$(out)/cryptoc -lcryptoc
+
+# Conditionally force the rebuilding of libcryptoc.a only if it would be
+# changed.
+# Note, we use ifndef to ensure the likelyhood of rebuilding is much higher.
+# For example, if variable cmd_libcryptoc_clean is modified or blank,
+# we will rebuild.
+ifneq ($(shell $(cmd_libcryptoc_clean)),clean)
+.PHONY: $(out)/cryptoc/libcryptoc.a
+endif
+# Rewrite the CFLAGS include paths to be absolute, since cryptoc is built
+# using a different working directory. This is only relevant because
+# cryptoc makes use of stdlibs, which EC provides from the builtin/ directory.
+$(out)/cryptoc/libcryptoc.a: CFLAGS := $(patsubst -I%,-I$(abspath %),$(CFLAGS))
+$(out)/cryptoc/libcryptoc.a:
+	+$(call quiet,libcryptoc,MAKE   )
+
+# Link RO and RW against cryptoc.
+$(out)/RO/ec.RO.elf $(out)/RO/ec.RO_B.elf: LDFLAGS_EXTRA += $(CRYPTOC_LDFLAGS)
+$(out)/RO/ec.RO.elf $(out)/RO/ec.RO_B.elf: $(out)/cryptoc/libcryptoc.a
+$(out)/RW/ec.RW.elf $(out)/RW/ec.RW_B.elf: LDFLAGS_EXTRA += $(CRYPTOC_LDFLAGS)
+$(out)/RW/ec.RW.elf $(out)/RW/ec.RW_B.elf: $(out)/cryptoc/libcryptoc.a
+
+# Host test executables (including fuzz tests).
+$(out)/$(PROJECT).exe: LDFLAGS_EXTRA += $(CRYPTOC_LDFLAGS)
+$(out)/$(PROJECT).exe: $(out)/cryptoc/libcryptoc.a
+
+# On-device tests.
+third-party-test-targets=$(foreach test,$(test-list-y),\
+	$(out)/RW/$(test).RW.elf $(out)/RO/$(test).RO.elf)
+$(third-party-test-targets): LDFLAGS_EXTRA += $(CRYPTOC_LDFLAGS)
+$(third-party-test-targets): $(out)/cryptoc/libcryptoc.a
+
+endif # CONFIG_LIBCRYPTOC
+
+ifeq ($(CONFIG_BORINGSSL_CRYPTO), y)
+ifndef CMAKE_SYSTEM_PROCESSOR
+$(error ERROR: Set CMAKE_SYSTEM_PROCESSOR in core/$(CORE)/toolchain.mk)
+endif
+ifndef OPENSSL_NO_ASM
+$(error ERROR: Set OPENSSL_NO_ASM in core/$(CORE)/toolchain.mk)
+endif
+
+# The boringssl path can be overridden on invocation, as in the following
+# example: $ make BORINGSSL_DIR=~/src/boringssl BOARD=bloonchipper
+BORINGSSL_DIR ?= ../../third_party/boringssl
+
+BORINGSSL_OUTDIR := $(out)/third_party/boringssl/crypto
+BORINGSSL_TOOLCHAIN := \
+	$(shell pwd)/third_party/boringssl/boringssl-toolchain.cmake
+
+$(BORINGSSL_OUTDIR)/libcrypto.a:
+	mkdir -p $(out)/third_party/boringssl/
+	cmake \
+		-DCC_NAME=$(cc-name) \
+		-DCXX_NAME=$(cxx-name) \
+		-DCROSS_COMPILE=$(CROSS_COMPILE) \
+		-DCMAKE_SYSTEM_PROCESSOR=$(CMAKE_SYSTEM_PROCESSOR) \
+		-DCMAKE_SYSROOT=$(SYSROOT) \
+		-DOPENSSL_NO_ASM=$(OPENSSL_NO_ASM) \
+		-DCROS_EC_REPO=$(CURDIR) \
+		-DCMAKE_TOOLCHAIN_FILE=$(BORINGSSL_TOOLCHAIN) \
+		-DCMAKE_VERBOSE_MAKEFILE=$(V) \
+		-B $(out)/third_party/boringssl/ \
+		-S $(BORINGSSL_DIR) \
+		-GNinja
+	cmake --build $(out)/third_party/boringssl/ -- crypto
+
+# Make sure the EC/FPMCU code can link to the boringssl library.
+CPPFLAGS += -I$(BORINGSSL_DIR) -I$(BORINGSSL_DIR)/include
+BORINGSSL_LDFLAGS := -L$(BORINGSSL_OUTDIR) -lcrypto
+
+# And the custom helpers.
+CPPFLAGS += -I$(shell pwd)/third_party/boringssl/include
+
+# Disable the unsupported features to prevent the usage of pthread & socket
+# related types in headers.
+# TODO(b/273639386): Remove these workarounds when the upstream supports
+# better way to disable the filesystem, threads and locks usages.
+CPPFLAGS += -D__TRUSTY__
+
+$(out)/RO/ec.RO.elf $(out)/RO/ec.RO_B.elf: LDFLAGS_EXTRA += $(BORINGSSL_LDFLAGS)
+$(out)/RO/ec.RO.elf $(out)/RO/ec.RO_B.elf: $(BORINGSSL_OUTDIR)/libcrypto.a
+$(out)/RW/ec.RW.elf $(out)/RW/ec.RW_B.elf: LDFLAGS_EXTRA += $(BORINGSSL_LDFLAGS)
+$(out)/RW/ec.RW.elf $(out)/RW/ec.RW_B.elf: $(BORINGSSL_OUTDIR)/libcrypto.a
+
+$(out)/$(PROJECT).exe: LDFLAGS_EXTRA += $(BORINGSSL_LDFLAGS)
+$(out)/$(PROJECT).exe: $(BORINGSSL_OUTDIR)/libcrypto.a
+
+# On-device tests.
+third-party-test-targets=$(foreach test,$(test-list-y),\
+	$(out)/RW/$(test).RW.elf $(out)/RO/$(test).RO.elf)
+$(third-party-test-targets): LDFLAGS_EXTRA += $(BORINGSSL_LDFLAGS)
+$(third-party-test-targets): $(BORINGSSL_OUTDIR)/libcrypto.a
+endif # CONFIG_BORINGSSL_CRYPTO
+
+# Build and link against googletest in *test* builds if configured.
+ifeq ($(TEST_BUILD),y)
+ifeq ($(CONFIG_GOOGLETEST),y)
+
+# The googletest path can be overridden on invocation. For example:
+# $ make GOOGLETEST_DIR=~/src/googletest BOARD=bloonchipper
+GOOGLETEST_DIR ?= $(realpath ../../third_party/googletest)
+GOOGLETEST_INSTALL_DIR := $(realpath $(out))/googletest/install
+CMAKE_TOOLCHAIN_FILE := $(CURDIR)/cmake/toolchain-armv7m.cmake
+
+GOOGLETEST_CFLAGS := -I$(GOOGLETEST_INSTALL_DIR)/include
+GOOGLETEST_LDFLAGS := -L$(GOOGLETEST_INSTALL_DIR)/lib -lgtest
+GOOGLETEST_LIB := $(GOOGLETEST_INSTALL_DIR)/lib/libgtest.a
+
+$(GOOGLETEST_LIB):
+	mkdir -p $(out)/googletest && \
+	cd $(out)/googletest && \
+	cmake -Dgtest_disable_pthreads=ON \
+		-GNinja \
+		-DCMAKE_TOOLCHAIN_FILE=$(CMAKE_TOOLCHAIN_FILE) \
+		-DCMAKE_INSTALL_PREFIX=$(GOOGLETEST_INSTALL_DIR) \
+		-DCMAKE_VERBOSE_MAKEFILE=$(V) \
+		$(GOOGLETEST_DIR) && \
+	cmake --build . && \
+	cmake --install .
+
+# On-device tests.
+third-party-test-targets=$(foreach test,$(test-list-y),\
+	$(out)/RW/$(test).RW.elf $(out)/RO/$(test).RO.elf)
+$(third-party-test-targets): LDFLAGS_EXTRA += $(GOOGLETEST_LDFLAGS)
+$(third-party-test-targets): CFLAGS += $(GOOGLETEST_CFLAGS)
+$(third-party-test-targets): $(GOOGLETEST_LIB)
+
+# Test files can include googletest headers, so the headers need to be
+# installed first.
+$(ro-objs): $(GOOGLETEST_LIB)
+$(rw-objs): $(GOOGLETEST_LIB)
+
+endif # CONFIG_GOOGLETEST
+endif # TEST_BUILD
diff --git a/third_party/sha2/sha256.c b/third_party/sha2/sha256.c
index 2d6eaa43f2..475092b1fd 100644
--- a/third_party/sha2/sha256.c
+++ b/third_party/sha2/sha256.c
@@ -35,6 +35,7 @@
  * SUCH DAMAGE.
  */
 
+#include "builtin/assert.h"
 #include "sha256.h"
 #include "util.h"
 
diff --git a/third_party/unacl-curve25519/core/cortex-m0/curve25519/mpy121666.S b/third_party/unacl-curve25519/core/cortex-m0/curve25519/mpy121666.S
index d2a467459b..5236dff64c 100644
--- a/third_party/unacl-curve25519/core/cortex-m0/curve25519/mpy121666.S
+++ b/third_party/unacl-curve25519/core/cortex-m0/curve25519/mpy121666.S
@@ -10,7 +10,7 @@
 // ATTENTION:
 // Not yet tested on target hardware.
 
-
+	.syntax unified
 	.code	16
 	.text
 	.align	2
@@ -24,158 +24,157 @@ fe25519_mpyWith121666_asm:
     push {r4,r5,r6,r7,r14}
     ldr r7,=56130
     ldr r2,[r1,#28]
-    lsl r5,r2,#16
-    lsr r6,r2,#16
-    lsr r3,r2,#16
+    lsls r5,r2,#16
+    lsrs r6,r2,#16
+    lsrs r3,r2,#16
     uxth r2,r2
-    mul r2,r7
-    mul r3,r7
-    add r5,r2
-    mov r2,#0
-    adc r6,r2
-    lsl r2,r3,#16
-    lsr r3,r3,#16
-    add r5,r2
-    adc r6,r3
-    lsl r2,r5,#1
-    lsr r2,r2,#1
+    muls r2,r7
+    muls r3,r7
+    adds r5,r5,r2
+    movs r2,#0
+    adcs r6,r2
+    lsls r2,r3,#16
+    lsrs r3,r3,#16
+    adds r5,r5,r2
+    adcs r6,r3
+    lsls r2,r5,#1
+    lsrs r2,r2,#1
     str r2,[r0,#28]
-    lsr r5,r5,#31
-    lsl r6,r6,#1
-    orr r5,r6
-    mov r6,#19
-    mul r5,r6
-    mov r6,#0
+    lsrs r5,r5,#31
+    lsls r6,r6,#1
+    orrs r5,r6
+    movs r6,#19
+    muls r5,r6
+    movs r6,#0
     ldr r2,[r1,#0]
-    lsl r3,r2,#16
-    lsr r4,r2,#16
-    add r5,r3
-    adc r6,r4
-    lsr r3,r2,#16
+    lsls r3,r2,#16
+    lsrs r4,r2,#16
+    adds r5,r5,r3
+    adcs r6,r4
+    lsrs r3,r2,#16
     uxth r2,r2
-    mul r2,r7
-    mul r3,r7
-    add r5,r2
-    mov r2,#0
-    adc r6,r2
-    lsl r2,r3,#16
-    lsr r3,r3,#16
-    add r5,r2
-    adc r6,r3
+    muls r2,r7
+    muls r3,r7
+    adds r5,r5,r2
+    movs r2,#0
+    adcs r6,r2
+    lsls r2,r3,#16
+    lsrs r3,r3,#16
+    adds r5,r5,r2
+    adcs r6,r3
     str r5,[r0,#0]
-    mov r5,#0
+    movs r5,#0
     ldr r2,[r1,#4]
-    lsl r3,r2,#16
-    lsr r4,r2,#16
-    add r6,r3
-    adc r5,r4
-    lsr r3,r2,#16
+    lsls r3,r2,#16
+    lsrs r4,r2,#16
+    adds r6,r6,r3
+    adcs r5,r4
+    lsrs r3,r2,#16
     uxth r2,r2
-    mul r2,r7
-    mul r3,r7
-    add r6,r2
-    mov r2,#0
-    adc r5,r2
-    lsl r2,r3,#16
-    lsr r3,r3,#16
-    add r6,r2
-    adc r5,r3
+    muls r2,r7
+    muls r3,r7
+    adds r6,r6,r2
+    movs r2,#0
+    adcs r5,r2
+    lsls r2,r3,#16
+    lsrs r3,r3,#16
+    adds r6,r6,r2
+    adcs r5,r3
     str r6,[r0,#4]
-    mov r6,#0
+    movs r6,#0
     ldr r2,[r1,#8]
-    lsl r3,r2,#16
-    lsr r4,r2,#16
-    add r5,r3
-    adc r6,r4
-    lsr r3,r2,#16
+    lsls r3,r2,#16
+    lsrs r4,r2,#16
+    adds r5,r5,r3
+    adcs r6,r4
+    lsrs r3,r2,#16
     uxth r2,r2
-    mul r2,r7
-    mul r3,r7
-    add r5,r2
-    mov r2,#0
-    adc r6,r2
-    lsl r2,r3,#16
-    lsr r3,r3,#16
-    add r5,r2
-    adc r6,r3
+    muls r2,r7
+    muls r3,r7
+    adds r5,r5,r2
+    movs r2,#0
+    adcs r6,r2
+    lsls r2,r3,#16
+    lsrs r3,r3,#16
+    adds r5,r5,r2
+    adcs r6,r3
     str r5,[r0,#8]
-    mov r5,#0
+    movs r5,#0
     ldr r2,[r1,#12]
-    lsl r3,r2,#16
-    lsr r4,r2,#16
-    add r6,r3
-    adc r5,r4
-    lsr r3,r2,#16
+    lsls r3,r2,#16
+    lsrs r4,r2,#16
+    adds r6,r6,r3
+    adcs r5,r4
+    lsrs r3,r2,#16
     uxth r2,r2
-    mul r2,r7
-    mul r3,r7
-    add r6,r2
-    mov r2,#0
-    adc r5,r2
-    lsl r2,r3,#16
-    lsr r3,r3,#16
-    add r6,r2
-    adc r5,r3
+    muls r2,r7
+    muls r3,r7
+    adds r6,r6,r2
+    movs r2,#0
+    adcs r5,r2
+    lsls r2,r3,#16
+    lsrs r3,r3,#16
+    adds r6,r6,r2
+    adcs r5,r3
     str r6,[r0,#12]
-    mov r6,#0
+    movs r6,#0
     ldr r2,[r1,#16]
-    lsl r3,r2,#16
-    lsr r4,r2,#16
-    add r5,r3
-    adc r6,r4
-    lsr r3,r2,#16
+    lsls r3,r2,#16
+    lsrs r4,r2,#16
+    adds r5,r5,r3
+    adcs r6,r4
+    lsrs r3,r2,#16
     uxth r2,r2
-    mul r2,r7
-    mul r3,r7
-    add r5,r2
-    mov r2,#0
-    adc r6,r2
-    lsl r2,r3,#16
-    lsr r3,r3,#16
-    add r5,r2
-    adc r6,r3
+    muls r2,r7
+    muls r3,r7
+    adds r5,r5,r2
+    movs r2,#0
+    adcs r6,r2
+    lsls r2,r3,#16
+    lsrs r3,r3,#16
+    adds r5,r5,r2
+    adcs r6,r3
     str r5,[r0,#16]
-    mov r5,#0
+    movs r5,#0
     ldr r2,[r1,#20]
-    lsl r3,r2,#16
-    lsr r4,r2,#16
-    add r6,r3
-    adc r5,r4
-    lsr r3,r2,#16
+    lsls r3,r2,#16
+    lsrs r4,r2,#16
+    adds r6,r6,r3
+    adcs r5,r4
+    lsrs r3,r2,#16
     uxth r2,r2
-    mul r2,r7
-    mul r3,r7
-    add r6,r2
-    mov r2,#0
-    adc r5,r2
-    lsl r2,r3,#16
-    lsr r3,r3,#16
-    add r6,r2
-    adc r5,r3
+    muls r2,r7
+    muls r3,r7
+    adds r6,r6,r2
+    movs r2,#0
+    adcs r5,r2
+    lsls r2,r3,#16
+    lsrs r3,r3,#16
+    adds r6,r6,r2
+    adcs r5,r3
     str r6,[r0,#20]
-    mov r6,#0
+    movs r6,#0
     ldr r2,[r1,#24]
-    lsl r3,r2,#16
-    lsr r4,r2,#16
-    add r5,r3
-    adc r6,r4
-    lsr r3,r2,#16
+    lsls r3,r2,#16
+    lsrs r4,r2,#16
+    adds r5,r5,r3
+    adcs r6,r4
+    lsrs r3,r2,#16
     uxth r2,r2
-    mul r2,r7
-    mul r3,r7
-    add r5,r2
-    mov r2,#0
-    adc r6,r2
-    lsl r2,r3,#16
-    lsr r3,r3,#16
-    add r5,r2
-    adc r6,r3
+    muls r2,r7
+    muls r3,r7
+    adds r5,r5,r2
+    movs r2,#0
+    adcs r6,r2
+    lsls r2,r3,#16
+    lsrs r3,r3,#16
+    adds r5,r5,r2
+    adcs r6,r3
     str r5,[r0,#24]
-    mov r5,#0
+    movs r5,#0
     ldr r2,[r0,#28]
-    add r6,r2
+    adds r6,r6,r2
     str r6,[r0,#28]
     pop {r4,r5,r6,r7,r15}
 
 	.size	fe25519_mpyWith121666_asm, .-fe25519_mpyWith121666_asm
-
diff --git a/third_party/unacl-curve25519/core/cortex-m0/curve25519/mul.S b/third_party/unacl-curve25519/core/cortex-m0/curve25519/mul.S
index 366713a7a3..2980e03364 100644
--- a/third_party/unacl-curve25519/core/cortex-m0/curve25519/mul.S
+++ b/third_party/unacl-curve25519/core/cortex-m0/curve25519/mul.S
@@ -1,3 +1,4 @@
+ .syntax unified
  .align	2
 	.global	multiply256x256_asm
 	.type	multiply256x256_asm, %function
@@ -11,96 +12,96 @@ multiply256x256_asm:
 	mov r12, r0
 	mov r10, r2
 	mov r11, r1
-	mov r0,r2
+	adds r0, r2, #0
 	//ldm r0!, {r4,r5,r6,r7}
 	ldm r0!, {r4,r5}
-  add r0,#8
+  adds r0,#8
 	ldm r1!, {r2,r3,r6,r7}
 	push {r0,r1}
 	/////////BEGIN LOW PART //////////////////////
 		/////////MUL128/////////////
 			//MUL64
-			mov r6, r5
-			mov r1, r2
-			sub r5, r4
-			sbc r0, r0
-			eor r5, r0
-			sub r5, r0
-			sub r1, r3
-			sbc r7, r7
-			eor r1, r7
-			sub r1, r7
-			eor r7, r0
+			adds r6, r5, #0
+			adds r1, r2, #0
+			subs r5, r4
+			sbcs r0, r0
+			eors r5, r0
+			subs r5, r0
+			subs r1, r3
+			sbcs r7, r7
+			eors r1, r7
+			subs r1, r7
+			eors r7, r0
 			mov r9, r1
 			mov r8, r5
-			lsr r1,r4,#16
+			lsrs r1,r4,#16
 			uxth r4,r4
-			mov r0,r4
+			adds r0, r4, #0
 			uxth r5,r2
-			lsr r2,#16
-			mul r0,r5//00
-			mul r5,r1//10
-			mul r4,r2//01
-			mul r1,r2//11
-			lsl r2,r4,#16
-			lsr r4,r4,#16
-			add r0,r2
-			adc r1,r4
-			lsl r2,r5,#16
-			lsr r4,r5,#16
-			add r0,r2
-			adc r1,r4
-			lsr r4, r6,#16
+			lsrs r2,#16
+			muls r0,r5//00
+			muls r5,r1//10
+			muls r4,r2//01
+			muls r1,r2//11
+			lsls r2,r4,#16
+			lsrs r4,r4,#16
+			adds r0, r0, r2
+			adcs r1,r4
+			lsls r2,r5,#16
+			lsrs r4,r5,#16
+			adds r0, r0, r2
+			adcs r1,r4
+			lsrs r4, r6,#16
 			uxth r6, r6
 			uxth r5, r3
-			lsr r3, r3, #16
-			mov r2, r6
-			mul r2, r5
-			mul r5, r4
-			mul r6, r3
-			mul r3, r4
-			lsl r4,r5,#16
-			lsr r5,r5,#16
-			add r2,r4
-			adc r3,r5
-			lsl r4,r6,#16
-			lsr r5,r6,#16
-			add r2,r4
-			adc r3,r5
-			eor r6, r6
-			add r2, r1
-			adc r3, r6
+			lsrs r3, r3, #16
+			adds r2, r6, #0
+			muls r2, r5
+			muls r5, r4
+			muls r6, r3
+			muls r3, r4
+			lsls r4,r5,#16
+			lsrs r5,r5,#16
+			adds r2, r2, r4
+			adcs r3,r5
+			lsls r4,r6,#16
+			lsrs r5,r6,#16
+			adds r2, r2, r4
+			adcs r3,r5
+			eors r6, r6
+			adds r2, r2, r1
+			adcs r3, r6
 			mov r1, r9
 			mov r5, r8
 			mov r8, r0
-			lsr r0, r1,#16
+			lsrs r0, r1,#16
 			uxth r1,r1
-			mov r4,r1
-			lsr r6,r5,#16
+			adds r4, r1, #0
+			lsrs r6,r5,#16
 			uxth r5,r5
-			mul r1,r5
-			mul r4,r6
-			mul r5,r0
-			mul r0,r6
-			lsl r6,r4,#16
-			lsr r4,#16
-			add r1,r6
-			adc r0,r4
-			lsl r6,r5,#16
-			lsr r5,#16
-			add r1,r6
-			adc r0,r5
-			eor r1,r7
-			eor r0,r7
-			eor r4, r4
-			asr r7, r7, #1
-			adc r1, r2
-			adc r2, r0
-			adc r7, r4
+			muls r1,r5
+			muls r4,r6
+			muls r5,r0
+			muls r0,r6
+			lsls r6,r4,#16
+			lsrs r4,#16
+			adds r1, r1, r6
+			adcs r0,r4
+			lsls r6,r5,#16
+			lsrs r5,#16
+			adds r1, r1, r6
+			adcs r0,r5
+			eors r1,r7
+			eors r0,r7
+			eors r4, r4
+			asrs r7, r7, #1
+			adcs r1, r2
+			adcs r2, r0
+			adcs r7, r4
 			mov r0, r8
-			add r1, r0
-			adc r2, r3
-			adc r3, r7
+			adds r1, r1, r0
+			adcs r2, r3
+			adcs r3, r7
 		//////////////////////////
 	mov r4, r12
 	stm r4!, {r0,r1}
@@ -109,229 +110,229 @@ multiply256x256_asm:
 		mov r1, r10
 		mov r10, r2
 		ldm r1, {r0, r1, r4, r5}
-		mov r2, r4
-		mov r7, r5
-		sub r2, r0
-		sbc r7, r1
-		sbc r6, r6
-		eor r2, r6
-		eor r7, r6
-		sub r2, r6
-		sbc r7, r6
+		adds r2, r4, #0
+		adds r7, r5, #0
+		subs r2, r0
+		sbcs r7, r1
+		sbcs r6, r6
+		eors r2, r6
+		eors r7, r6
+		subs r2, r6
+		sbcs r7, r6
 		push {r2, r7}
 		mov r2, r11
 		mov r11, r3
 		ldm r2, {r0, r1, r2, r3}
-		sub r0, r2
-		sbc r1, r3
-		sbc r7, r7
-		eor r0, r7
-		eor r1, r7
-		sub r0, r7
-		sbc r1, r7
-		eor r7, r6
+		subs r0, r2
+		sbcs r1, r3
+		sbcs r7, r7
+		eors r0, r7
+		eors r1, r7
+		subs r0, r7
+		sbcs r1, r7
+		eors r7, r6
 		mov r12, r7
 		push {r0, r1}
 			//MUL64
-			mov r6, r5
-			mov r1, r2
-			sub r5, r4
-			sbc r0, r0
-			eor r5, r0
-			sub r5, r0
-			sub r1, r3
-			sbc r7, r7
-			eor r1, r7
-			sub r1, r7
-			eor r7, r0
+			adds r6, r5, #0
+			adds r1, r2, #0
+			subs r5, r4
+			sbcs r0, r0
+			eors r5, r0
+			subs r5, r0
+			subs r1, r3
+			sbcs r7, r7
+			eors r1, r7
+			subs r1, r7
+			eors r7, r0
 			mov r9, r1
 			mov r8, r5
-			lsr r1,r4,#16
+			lsrs r1,r4,#16
 			uxth r4,r4
-			mov r0,r4
+			adds r0, r4, #0
 			uxth r5,r2
-			lsr r2,#16
-			mul r0,r5//00
-			mul r5,r1//10
-			mul r4,r2//01
-			mul r1,r2//11
-			lsl r2,r4,#16
-			lsr r4,r4,#16
-			add r0,r2
-			adc r1,r4
-			lsl r2,r5,#16
-			lsr r4,r5,#16
-			add r0,r2
-			adc r1,r4
-			lsr r4, r6,#16
+			lsrs r2,#16
+			muls r0,r5//00
+			muls r5,r1//10
+			muls r4,r2//01
+			muls r1,r2//11
+			lsls r2,r4,#16
+			lsrs r4,r4,#16
+			adds r0, r0, r2
+			adcs r1,r4
+			lsls r2,r5,#16
+			lsrs r4,r5,#16
+			adds r0, r0, r2
+			adcs r1,r4
+			lsrs r4, r6,#16
 			uxth r6, r6
 			uxth r5, r3
-			lsr r3, r3, #16
-			mov r2, r6
-			mul r2, r5
-			mul r5, r4
-			mul r6, r3
-			mul r3, r4
-			lsl r4,r5,#16
-			lsr r5,r5,#16
-			add r2,r4
-			adc r3,r5
-			lsl r4,r6,#16
-			lsr r5,r6,#16
-			add r2,r4
-			adc r3,r5
-			eor r6, r6
-			add r2, r1
-			adc r3, r6
+			lsrs r3, r3, #16
+			adds r2, r6, #0
+			muls r2, r5
+			muls r5, r4
+			muls r6, r3
+			muls r3, r4
+			lsls r4,r5,#16
+			lsrs r5,r5,#16
+			adds r2, r2, r4
+			adcs r3,r5
+			lsls r4,r6,#16
+			lsrs r5,r6,#16
+			adds r2, r2, r4
+			adcs r3,r5
+			eors r6, r6
+			adds r2, r2, r1
+			adcs r3, r6
 			mov r1, r9
 			mov r5, r8
 			mov r8, r0
-			lsr r0, r1,#16
+			lsrs r0, r1,#16
 			uxth r1,r1
-			mov r4,r1
-			lsr r6,r5,#16
+			adds r4, r1, #0
+			lsrs r6,r5,#16
 			uxth r5,r5
-			mul r1,r5
-			mul r4,r6
-			mul r5,r0
-			mul r0,r6
-			lsl r6,r4,#16
-			lsr r4,#16
-			add r1,r6
-			adc r0,r4
-			lsl r6,r5,#16
-			lsr r5,#16
-			add r1,r6
-			adc r0,r5
-			eor r1,r7
-			eor r0,r7
-			eor r4, r4
-			asr r7, r7, #1
-			adc r1, r2
-			adc r2, r0
-			adc r7, r4
+			muls r1,r5
+			muls r4,r6
+			muls r5,r0
+			muls r0,r6
+			lsls r6,r4,#16
+			lsrs r4,#16
+			adds r1, r1, r6
+			adcs r0,r4
+			lsls r6,r5,#16
+			lsrs r5,#16
+			adds r1, r1, r6
+			adcs r0,r5
+			eors r1,r7
+			eors r0,r7
+			eors r4, r4
+			asrs r7, r7, #1
+			adcs r1, r2
+			adcs r2, r0
+			adcs r7, r4
 			mov r0, r8
-			add r1, r0
-			adc r2, r3
-			adc r3, r7
+			adds r1, r1, r0
+			adcs r2, r3
+			adcs r3, r7
 		mov r4, r10
 		mov r5, r11
-		eor r6, r6
-		add r0, r4
-		adc r1, r5
-		adc r2, r6
-		adc r3, r6
+		eors r6, r6
+		adds r0, r0, r4
+		adcs r1, r5
+		adcs r2, r6
+		adcs r3, r6
 		mov r10, r2
 		mov r11, r3
 		pop {r2-r5}
 		push {r0, r1}
-			mov r6, r5
-			mov r1, r2
-			sub r5, r4
-			sbc r0, r0
-			eor r5, r0
-			sub r5, r0
-			sub r1, r3
-			sbc r7, r7
-			eor r1, r7
-			sub r1, r7
-			eor r7, r0
+			adds r6, r5, #0
+			adds r1, r2, #0
+			subs r5, r4
+			sbcs r0, r0
+			eors r5, r0
+			subs r5, r0
+			subs r1, r3
+			sbcs r7, r7
+			eors r1, r7
+			subs r1, r7
+			eors r7, r0
 			mov r9, r1
 			mov r8, r5
-			lsr r1,r4,#16
+			lsrs r1,r4,#16
 			uxth r4,r4
-			mov r0,r4
+			adds r0, r4, #0
 			uxth r5,r2
-			lsr r2,#16
-			mul r0,r5//00
-			mul r5,r1//10
-			mul r4,r2//01
-			mul r1,r2//11
-			lsl r2,r4,#16
-			lsr r4,r4,#16
-			add r0,r2
-			adc r1,r4
-			lsl r2,r5,#16
-			lsr r4,r5,#16
-			add r0,r2
-			adc r1,r4
-			lsr r4, r6,#16
+			lsrs r2,#16
+			muls r0,r5//00
+			muls r5,r1//10
+			muls r4,r2//01
+			muls r1,r2//11
+			lsls r2,r4,#16
+			lsrs r4,r4,#16
+			adds r0, r0, r2
+			adcs r1,r4
+			lsls r2,r5,#16
+			lsrs r4,r5,#16
+			adds r0, r0, r2
+			adcs r1,r4
+			lsrs r4, r6,#16
 			uxth r6, r6
 			uxth r5, r3
-			lsr r3, r3, #16
-			mov r2, r6
-			mul r2, r5
-			mul r5, r4
-			mul r6, r3
-			mul r3, r4
-			lsl r4,r5,#16
-			lsr r5,r5,#16
-			add r2,r4
-			adc r3,r5
-			lsl r4,r6,#16
-			lsr r5,r6,#16
-			add r2,r4
-			adc r3,r5
-			eor r6, r6
-			add r2, r1
-			adc r3, r6
+			lsrs r3, r3, #16
+			adds r2, r6, #0
+			muls r2, r5
+			muls r5, r4
+			muls r6, r3
+			muls r3, r4
+			lsls r4,r5,#16
+			lsrs r5,r5,#16
+			adds r2, r2, r4
+			adcs r3,r5
+			lsls r4,r6,#16
+			lsrs r5,r6,#16
+			adds r2, r2, r4
+			adcs r3,r5
+			eors r6, r6
+			adds r2, r2, r1
+			adcs r3, r6
 			mov r1, r9
 			mov r5, r8
 			mov r8, r0
-			lsr r0, r1,#16
+			lsrs r0, r1,#16
 			uxth r1,r1
-			mov r4,r1
-			lsr r6,r5,#16
+			adds r4, r1, #0
+			lsrs r6,r5,#16
 			uxth r5,r5
-			mul r1,r5
-			mul r4,r6
-			mul r5,r0
-			mul r0,r6
-			lsl r6,r4,#16
-			lsr r4,#16
-			add r1,r6
-			adc r0,r4
-			lsl r6,r5,#16
-			lsr r5,#16
-			add r1,r6
-			adc r0,r5
-			eor r1,r7
-			eor r0,r7
-			eor r4, r4
-			asr r7, r7, #1
-			adc r1, r2
-			adc r2, r0
-			adc r7, r4
+			muls r1,r5
+			muls r4,r6
+			muls r5,r0
+			muls r0,r6
+			lsls r6,r4,#16
+			lsrs r4,#16
+			adds r1, r1, r6
+			adcs r0,r4
+			lsls r6,r5,#16
+			lsrs r5,#16
+			adds r1, r1, r6
+			adcs r0,r5
+			eors r1,r7
+			eors r0,r7
+			eors r4, r4
+			asrs r7, r7, #1
+			adcs r1, r2
+			adcs r2, r0
+			adcs r7, r4
 			mov r0, r8
-			add r1, r0
-			adc r2, r3
-			adc r3, r7
+			adds r1, r1, r0
+			adcs r2, r3
+			adcs r3, r7
 		pop {r4, r5}
 		mov r6, r12
 		mov r7, r12
-		eor r0, r6
-		eor r1, r6
-		eor r2, r6
-		eor r3, r6
-		asr r6, r6, #1
-		adc r0, r4
-		adc r1, r5
-		adc r4, r2
-		adc r5, r3
-		eor r2, r2
-		adc r6,r2
-		adc r7,r2
+		eors r0, r6
+		eors r1, r6
+		eors r2, r6
+		eors r3, r6
+		asrs r6, r6, #1
+		adcs r0, r4
+		adcs r1, r5
+		adcs r4, r2
+		adcs r5, r3
+		eors r2, r2
+		adcs r6,r2
+		adcs r7,r2
 		pop {r2, r3}
 		mov r8, r2
 		mov r9, r3
-		add r2, r0
-		adc r3, r1
+		adds r2, r2, r0
+		adcs r3, r1
 		mov r0, r10
 		mov r1, r11
-		adc r4, r0
-		adc r5, r1
-		adc r6, r0
-		adc r7, r1
+		adcs r4, r0
+		adcs r5, r1
+		adcs r6, r0
+		adcs r7, r1
 	////////END LOW PART/////////////////////
 	pop {r0}
 	stm r0!, {r2,r3}
@@ -345,353 +346,353 @@ multiply256x256_asm:
 	/////////BEGIN HIGH PART////////////////
 		/////////MUL128/////////////
 			//MUL64
-			mov r6, r5
-			mov r1, r2
-			sub r5, r4
-			sbc r0, r0
-			eor r5, r0
-			sub r5, r0
-			sub r1, r3
-			sbc r7, r7
-			eor r1, r7
-			sub r1, r7
-			eor r7, r0
+			adds r6, r5, #0
+			adds r1, r2, #0
+			subs r5, r4
+			sbcs r0, r0
+			eors r5, r0
+			subs r5, r0
+			subs r1, r3
+			sbcs r7, r7
+			eors r1, r7
+			subs r1, r7
+			eors r7, r0
 			mov r9, r1
 			mov r8, r5
-			lsr r1,r4,#16
+			lsrs r1,r4,#16
 			uxth r4,r4
-			mov r0,r4
+			adds r0, r4, #0
 			uxth r5,r2
-			lsr r2,#16
-			mul r0,r5//00
-			mul r5,r1//10
-			mul r4,r2//01
-			mul r1,r2//11
-			lsl r2,r4,#16
-			lsr r4,r4,#16
-			add r0,r2
-			adc r1,r4
-			lsl r2,r5,#16
-			lsr r4,r5,#16
-			add r0,r2
-			adc r1,r4
-			lsr r4, r6,#16
+			lsrs r2,#16
+			muls r0,r5//00
+			muls r5,r1//10
+			muls r4,r2//01
+			muls r1,r2//11
+			lsls r2,r4,#16
+			lsrs r4,r4,#16
+			adds r0, r0, r2
+			adcs r1,r4
+			lsls r2,r5,#16
+			lsrs r4,r5,#16
+			adds r0, r0, r2
+			adcs r1,r4
+			lsrs r4, r6,#16
 			uxth r6, r6
 			uxth r5, r3
-			lsr r3, r3, #16
-			mov r2, r6
-			mul r2, r5
-			mul r5, r4
-			mul r6, r3
-			mul r3, r4
-			lsl r4,r5,#16
-			lsr r5,r5,#16
-			add r2,r4
-			adc r3,r5
-			lsl r4,r6,#16
-			lsr r5,r6,#16
-			add r2,r4
-			adc r3,r5
-			eor r6, r6
-			add r2, r1
-			adc r3, r6
+			lsrs r3, r3, #16
+			adds r2, r6, #0
+			muls r2, r5
+			muls r5, r4
+			muls r6, r3
+			muls r3, r4
+			lsls r4,r5,#16
+			lsrs r5,r5,#16
+			adds r2, r2, r4
+			adcs r3,r5
+			lsls r4,r6,#16
+			lsrs r5,r6,#16
+			adds r2, r2, r4
+			adcs r3,r5
+			eors r6, r6
+			adds r2, r2, r1
+			adcs r3, r6
 			mov r1, r9
 			mov r5, r8
 			mov r8, r0
-			lsr r0, r1,#16
+			lsrs r0, r1,#16
 			uxth r1,r1
-			mov r4,r1
-			lsr r6,r5,#16
+			adds r4, r1, #0
+			lsrs r6,r5,#16
 			uxth r5,r5
-			mul r1,r5
-			mul r4,r6
-			mul r5,r0
-			mul r0,r6
-			lsl r6,r4,#16
-			lsr r4,#16
-			add r1,r6
-			adc r0,r4
-			lsl r6,r5,#16
-			lsr r5,#16
-			add r1,r6
-			adc r0,r5
-			eor r1,r7
-			eor r0,r7
-			eor r4, r4
-			asr r7, r7, #1
-			adc r1, r2
-			adc r2, r0
-			adc r7, r4
+			muls r1,r5
+			muls r4,r6
+			muls r5,r0
+			muls r0,r6
+			lsls r6,r4,#16
+			lsrs r4,#16
+			adds r1, r1, r6
+			adcs r0,r4
+			lsls r6,r5,#16
+			lsrs r5,#16
+			adds r1, r1, r6
+			adcs r0,r5
+			eors r1,r7
+			eors r0,r7
+			eors r4, r4
+			asrs r7, r7, #1
+			adcs r1, r2
+			adcs r2, r0
+			adcs r7, r4
 			mov r0, r8
-			add r1, r0
-			adc r2, r3
-			adc r3, r7
+			adds r1, r1, r0
+			adcs r2, r3
+			adcs r3, r7
 		push {r0,r1}
 		mov r1, r10
 		mov r10, r2
 		ldm r1, {r0, r1, r4, r5}
-		mov r2, r4
-		mov r7, r5
-		sub r2, r0
-		sbc r7, r1
-		sbc r6, r6
-		eor r2, r6
-		eor r7, r6
-		sub r2, r6
-		sbc r7, r6
+		adds r2, r4, #0
+		adds r7, r5, #0
+		subs r2, r0
+		sbcs r7, r1
+		sbcs r6, r6
+		eors r2, r6
+		eors r7, r6
+		subs r2, r6
+		sbcs r7, r6
 		push {r2, r7}
 		mov r2, r11
 		mov r11, r3
 		ldm r2, {r0, r1, r2, r3}
-		sub r0, r2
-		sbc r1, r3
-		sbc r7, r7
-		eor r0, r7
-		eor r1, r7
-		sub r0, r7
-		sbc r1, r7
-		eor r7, r6
+		subs r0, r2
+		sbcs r1, r3
+		sbcs r7, r7
+		eors r0, r7
+		eors r1, r7
+		subs r0, r7
+		sbcs r1, r7
+		eors r7, r6
 		mov r12, r7
 		push {r0, r1}
 			//MUL64
-			mov r6, r5
-			mov r1, r2
-			sub r5, r4
-			sbc r0, r0
-			eor r5, r0
-			sub r5, r0
-			sub r1, r3
-			sbc r7, r7
-			eor r1, r7
-			sub r1, r7
-			eor r7, r0
+			adds r6, r5, #0
+			adds r1, r2, #0
+			subs r5, r4
+			sbcs r0, r0
+			eors r5, r0
+			subs r5, r0
+			subs r1, r3
+			sbcs r7, r7
+			eors r1, r7
+			subs r1, r7
+			eors r7, r0
 			mov r9, r1
 			mov r8, r5
-			lsr r1,r4,#16
+			lsrs r1,r4,#16
 			uxth r4,r4
-			mov r0,r4
+			adds r0, r4, #0
 			uxth r5,r2
-			lsr r2,#16
-			mul r0,r5//00
-			mul r5,r1//10
-			mul r4,r2//01
-			mul r1,r2//11
-			lsl r2,r4,#16
-			lsr r4,r4,#16
-			add r0,r2
-			adc r1,r4
-			lsl r2,r5,#16
-			lsr r4,r5,#16
-			add r0,r2
-			adc r1,r4
-			lsr r4, r6,#16
+			lsrs r2,#16
+			muls r0,r5//00
+			muls r5,r1//10
+			muls r4,r2//01
+			muls r1,r2//11
+			lsls r2,r4,#16
+			lsrs r4,r4,#16
+			adds r0, r0, r2
+			adcs r1,r4
+			lsls r2,r5,#16
+			lsrs r4,r5,#16
+			adds r0, r0, r2
+			adcs r1,r4
+			lsrs r4, r6,#16
 			uxth r6, r6
 			uxth r5, r3
-			lsr r3, r3, #16
-			mov r2, r6
-			mul r2, r5
-			mul r5, r4
-			mul r6, r3
-			mul r3, r4
-			lsl r4,r5,#16
-			lsr r5,r5,#16
-			add r2,r4
-			adc r3,r5
-			lsl r4,r6,#16
-			lsr r5,r6,#16
-			add r2,r4
-			adc r3,r5
-			eor r6, r6
-			add r2, r1
-			adc r3, r6
+			lsrs r3, r3, #16
+			adds r2, r6, #0
+			muls r2, r5
+			muls r5, r4
+			muls r6, r3
+			muls r3, r4
+			lsls r4,r5,#16
+			lsrs r5,r5,#16
+			adds r2, r2, r4
+			adcs r3,r5
+			lsls r4,r6,#16
+			lsrs r5,r6,#16
+			adds r2, r2, r4
+			adcs r3,r5
+			eors r6, r6
+			adds r2, r2, r1
+			adcs r3, r6
 			mov r1, r9
 			mov r5, r8
 			mov r8, r0
-			lsr r0, r1,#16
+			lsrs r0, r1,#16
 			uxth r1,r1
-			mov r4,r1
-			lsr r6,r5,#16
+			adds r4, r1, #0
+			lsrs r6,r5,#16
 			uxth r5,r5
-			mul r1,r5
-			mul r4,r6
-			mul r5,r0
-			mul r0,r6
-			lsl r6,r4,#16
-			lsr r4,#16
-			add r1,r6
-			adc r0,r4
-			lsl r6,r5,#16
-			lsr r5,#16
-			add r1,r6
-			adc r0,r5
-			eor r1,r7
-			eor r0,r7
-			eor r4, r4
-			asr r7, r7, #1
-			adc r1, r2
-			adc r2, r0
-			adc r7, r4
+			muls r1,r5
+			muls r4,r6
+			muls r5,r0
+			muls r0,r6
+			lsls r6,r4,#16
+			lsrs r4,#16
+			adds r1, r1, r6
+			adcs r0,r4
+			lsls r6,r5,#16
+			lsrs r5,#16
+			adds r1, r1, r6
+			adcs r0,r5
+			eors r1,r7
+			eors r0,r7
+			eors r4, r4
+			asrs r7, r7, #1
+			adcs r1, r2
+			adcs r2, r0
+			adcs r7, r4
 			mov r0, r8
-			add r1, r0
-			adc r2, r3
-			adc r3, r7
+			adds r1, r1, r0
+			adcs r2, r3
+			adcs r3, r7
 		mov r4, r10
 		mov r5, r11
-		eor r6, r6
-		add r0, r4
-		adc r1, r5
-		adc r2, r6
-		adc r3, r6
+		eors r6, r6
+		adds r0, r0, r4
+		adcs r1, r5
+		adcs r2, r6
+		adcs r3, r6
 		mov r10, r2
 		mov r11, r3
 		pop {r2-r5}
 		push {r0, r1}
-			mov r6, r5
-			mov r1, r2
-			sub r5, r4
-			sbc r0, r0
-			eor r5, r0
-			sub r5, r0
-			sub r1, r3
-			sbc r7, r7
-			eor r1, r7
-			sub r1, r7
-			eor r7, r0
+			adds r6, r5, #0
+			adds r1, r2, #0
+			subs r5, r4
+			sbcs r0, r0
+			eors r5, r0
+			subs r5, r0
+			subs r1, r3
+			sbcs r7, r7
+			eors r1, r7
+			subs r1, r7
+			eors r7, r0
 			mov r9, r1
 			mov r8, r5
-			lsr r1,r4,#16
+			lsrs r1,r4,#16
 			uxth r4,r4
-			mov r0,r4
+			adds r0, r4, #0
 			uxth r5,r2
-			lsr r2,#16
-			mul r0,r5//00
-			mul r5,r1//10
-			mul r4,r2//01
-			mul r1,r2//11
-			lsl r2,r4,#16
-			lsr r4,r4,#16
-			add r0,r2
-			adc r1,r4
-			lsl r2,r5,#16
-			lsr r4,r5,#16
-			add r0,r2
-			adc r1,r4
-			lsr r4, r6,#16
+			lsrs r2,#16
+			muls r0,r5//00
+			muls r5,r1//10
+			muls r4,r2//01
+			muls r1,r2//11
+			lsls r2,r4,#16
+			lsrs r4,r4,#16
+			adds r0, r0, r2
+			adcs r1,r4
+			lsls r2,r5,#16
+			lsrs r4,r5,#16
+			adds r0, r0, r2
+			adcs r1,r4
+			lsrs r4, r6,#16
 			uxth r6, r6
 			uxth r5, r3
-			lsr r3, r3, #16
-			mov r2, r6
-			mul r2, r5
-			mul r5, r4
-			mul r6, r3
-			mul r3, r4
-			lsl r4,r5,#16
-			lsr r5,r5,#16
-			add r2,r4
-			adc r3,r5
-			lsl r4,r6,#16
-			lsr r5,r6,#16
-			add r2,r4
-			adc r3,r5
-			eor r6, r6
-			add r2, r1
-			adc r3, r6
+			lsrs r3, r3, #16
+			adds r2, r6, #0
+			muls r2, r5
+			muls r5, r4
+			muls r6, r3
+			muls r3, r4
+			lsls r4,r5,#16
+			lsrs r5,r5,#16
+			adds r2, r2, r4
+			adcs r3,r5
+			lsls r4,r6,#16
+			lsrs r5,r6,#16
+			adds r2, r2, r4
+			adcs r3,r5
+			eors r6, r6
+			adds r2, r2, r1
+			adcs r3, r6
 			mov r1, r9
 			mov r5, r8
 			mov r8, r0
-			lsr r0, r1,#16
+			lsrs r0, r1,#16
 			uxth r1,r1
-			mov r4,r1
-			lsr r6,r5,#16
+			adds r4, r1, #0
+			lsrs r6,r5,#16
 			uxth r5,r5
-			mul r1,r5
-			mul r4,r6
-			mul r5,r0
-			mul r0,r6
-			lsl r6,r4,#16
-			lsr r4,#16
-			add r1,r6
-			adc r0,r4
-			lsl r6,r5,#16
-			lsr r5,#16
-			add r1,r6
-			adc r0,r5
-			eor r1,r7
-			eor r0,r7
-			eor r4, r4
-			asr r7, r7, #1
-			adc r1, r2
-			adc r2, r0
-			adc r7, r4
+			muls r1,r5
+			muls r4,r6
+			muls r5,r0
+			muls r0,r6
+			lsls r6,r4,#16
+			lsrs r4,#16
+			adds r1, r1, r6
+			adcs r0,r4
+			lsls r6,r5,#16
+			lsrs r5,#16
+			adds r1, r1, r6
+			adcs r0,r5
+			eors r1,r7
+			eors r0,r7
+			eors r4, r4
+			asrs r7, r7, #1
+			adcs r1, r2
+			adcs r2, r0
+			adcs r7, r4
 			mov r0, r8
-			add r1, r0
-			adc r2, r3
-			adc r3, r7
+			adds r1, r1, r0
+			adcs r2, r3
+			adcs r3, r7
 		pop {r4, r5}
 		mov r6, r12
 		mov r7, r12
-		eor r0, r6
-		eor r1, r6
-		eor r2, r6
-		eor r3, r6
-		asr r6, r6, #1
-		adc r0, r4
-		adc r1, r5
-		adc r4, r2
-		adc r5, r3
-		eor r2, r2
-		adc r6,r2 //0,1
-		adc r7,r2
+		eors r0, r6
+		eors r1, r6
+		eors r2, r6
+		eors r3, r6
+		asrs r6, r6, #1
+		adcs r0, r4
+		adcs r1, r5
+		adcs r4, r2
+		adcs r5, r3
+		eors r2, r2
+		adcs r6,r2 //0,1
+		adcs r7,r2
 		pop {r2, r3}
 		mov r8, r2
 		mov r9, r3
-		add r2, r0
-		adc r3, r1
+		adds r2, r2, r0
+		adcs r3, r1
 		mov r0, r10
 		mov r1, r11
-		adc r4, r0
-		adc r5, r1
-		adc r6, r0
-		adc r7, r1
+		adcs r4, r0
+		adcs r5, r1
+		adcs r6, r0
+		adcs r7, r1
 	////////END HIGH PART/////////////////////
 	mov r0, r8
 	mov r1, r9
 	mov r8, r6
 	mov r9, r7
 	pop {r6, r7}
-	add r0, r6
-	adc r1, r7
+	adds r0, r0, r6
+	adcs r1, r7
 	pop {r6, r7}
-	adc r2, r6
-	adc r3, r7
+	adcs r2, r6
+	adcs r3, r7
 	pop {r7}
 	stm r7!, {r0-r3}
 	mov r10, r7
-	eor r0,r0
+	eors r0,r0
 	mov r6, r8
 	mov r7, r9
-	adc r4, r0
-	adc r5, r0
-	adc r6, r0
-	adc r7, r0
+	adcs r4, r0
+	adcs r5, r0
+	adcs r6, r0
+	adcs r7, r0
 	pop {r0,r1,r2}
 	mov r12, r2
 	push {r0, r4-r7}
 	ldm r1, {r0-r7}
-	sub r0, r4
-	sbc r1, r5
-	sbc r2, r6
-	sbc r3, r7
-	eor r4, r4
-	sbc r4, r4
-	eor r0, r4
-	eor r1, r4
-	eor r2, r4
-	eor r3, r4
-	sub r0, r4
-	sbc r1, r4
-	sbc r2, r4
-	sbc r3, r4
+	subs r0, r4
+	sbcs r1, r5
+	sbcs r2, r6
+	sbcs r3, r7
+	eors r4, r4
+	sbcs r4, r4
+	eors r0, r4
+	eors r1, r4
+	eors r2, r4
+	eors r3, r4
+	subs r0, r4
+	sbcs r1, r4
+	sbcs r2, r4
+	sbcs r3, r4
 	mov r6, r12
 	mov r12, r4 //carry
 	mov r5, r10
@@ -700,22 +701,22 @@ multiply256x256_asm:
 	mov r8, r0
 	mov r9, r1
 	ldm r6, {r0-r7}
-	sub r4, r0
-	sbc r5, r1
-	sbc r6, r2
-	sbc r7, r3
-	eor r0, r0
-	sbc r0, r0
-	eor r4, r0
-	eor r5, r0
-	eor r6, r0
-	eor r7, r0
-	sub r4, r0
-	sbc r5, r0
-	sbc r6, r0
-	sbc r7, r0
+	subs r4, r0
+	sbcs r5, r1
+	sbcs r6, r2
+	sbcs r7, r3
+	eors r0, r0
+	sbcs r0, r0
+	eors r4, r0
+	eors r5, r0
+	eors r6, r0
+	eors r7, r0
+	subs r4, r0
+	sbcs r5, r0
+	sbcs r6, r0
+	sbcs r7, r0
 	mov r1, r12
-	eor r0, r1
+	eors r0, r1
 	mov r1, r11
 	stm r1!, {r4-r7}
 	push {r0}
@@ -724,366 +725,366 @@ multiply256x256_asm:
 	/////////BEGIN MIDDLE PART////////////////
 		/////////MUL128/////////////
 			//MUL64
-			mov r6, r5
-			mov r1, r2
-			sub r5, r4
-			sbc r0, r0
-			eor r5, r0
-			sub r5, r0
-			sub r1, r3
-			sbc r7, r7
-			eor r1, r7
-			sub r1, r7
-			eor r7, r0
+			adds r6, r5, #0
+			adds r1, r2, #0
+			subs r5, r4
+			sbcs r0, r0
+			eors r5, r0
+			subs r5, r0
+			subs r1, r3
+			sbcs r7, r7
+			eors r1, r7
+			subs r1, r7
+			eors r7, r0
 			mov r9, r1
 			mov r8, r5
-			lsr r1,r4,#16
+			lsrs r1,r4,#16
 			uxth r4,r4
-			mov r0,r4
+			adds r0, r4, #0
 			uxth r5,r2
-			lsr r2,#16
-			mul r0,r5//00
-			mul r5,r1//10
-			mul r4,r2//01
-			mul r1,r2//11
-			lsl r2,r4,#16
-			lsr r4,r4,#16
-			add r0,r2
-			adc r1,r4
-			lsl r2,r5,#16
-			lsr r4,r5,#16
-			add r0,r2
-			adc r1,r4
-			lsr r4, r6,#16
+			lsrs r2,#16
+			muls r0,r5//00
+			muls r5,r1//10
+			muls r4,r2//01
+			muls r1,r2//11
+			lsls r2,r4,#16
+			lsrs r4,r4,#16
+			adds r0, r0, r2
+			adcs r1,r4
+			lsls r2,r5,#16
+			lsrs r4,r5,#16
+			adds r0, r0, r2
+			adcs r1,r4
+			lsrs r4, r6,#16
 			uxth r6, r6
 			uxth r5, r3
-			lsr r3, r3, #16
-			mov r2, r6
-			mul r2, r5
-			mul r5, r4
-			mul r6, r3
-			mul r3, r4
-			lsl r4,r5,#16
-			lsr r5,r5,#16
-			add r2,r4
-			adc r3,r5
-			lsl r4,r6,#16
-			lsr r5,r6,#16
-			add r2,r4
-			adc r3,r5
-			eor r6, r6
-			add r2, r1
-			adc r3, r6
+			lsrs r3, r3, #16
+			adds r2, r6, #0
+			muls r2, r5
+			muls r5, r4
+			muls r6, r3
+			muls r3, r4
+			lsls r4,r5,#16
+			lsrs r5,r5,#16
+			adds r2, r2, r4
+			adcs r3,r5
+			lsls r4,r6,#16
+			lsrs r5,r6,#16
+			adds r2, r2, r4
+			adcs r3,r5
+			eors r6, r6
+			adds r2, r2, r1
+			adcs r3, r6
 			mov r1, r9
 			mov r5, r8
 			mov r8, r0
-			lsr r0, r1,#16
+			lsrs r0, r1,#16
 			uxth r1,r1
-			mov r4,r1
-			lsr r6,r5,#16
+			adds r4, r1, #0
+			lsrs r6,r5,#16
 			uxth r5,r5
-			mul r1,r5
-			mul r4,r6
-			mul r5,r0
-			mul r0,r6
-			lsl r6,r4,#16
-			lsr r4,#16
-			add r1,r6
-			adc r0,r4
-			lsl r6,r5,#16
-			lsr r5,#16
-			add r1,r6
-			adc r0,r5
-			eor r1,r7
-			eor r0,r7
-			eor r4, r4
-			asr r7, r7, #1
-			adc r1, r2
-			adc r2, r0
-			adc r7, r4
+			muls r1,r5
+			muls r4,r6
+			muls r5,r0
+			muls r0,r6
+			lsls r6,r4,#16
+			lsrs r4,#16
+			adds r1, r1, r6
+			adcs r0,r4
+			lsls r6,r5,#16
+			lsrs r5,#16
+			adds r1, r1, r6
+			adcs r0,r5
+			eors r1,r7
+			eors r0,r7
+			eors r4, r4
+			asrs r7, r7, #1
+			adcs r1, r2
+			adcs r2, r0
+			adcs r7, r4
 			mov r0, r8
-			add r1, r0
-			adc r2, r3
-			adc r3, r7
+			adds r1, r1, r0
+			adcs r2, r3
+			adcs r3, r7
 		push {r0,r1}
 		mov r1, r10
 		mov r10, r2
 		ldm r1, {r0, r1, r4, r5}
-		mov r2, r4
-		mov r7, r5
-		sub r2, r0
-		sbc r7, r1
-		sbc r6, r6
-		eor r2, r6
-		eor r7, r6
-		sub r2, r6
-		sbc r7, r6
+		adds r2, r4, #0
+		adds r7, r5, #0
+		subs r2, r0
+		sbcs r7, r1
+		sbcs r6, r6
+		eors r2, r6
+		eors r7, r6
+		subs r2, r6
+		sbcs r7, r6
 		push {r2, r7}
 		mov r2, r11
 		mov r11, r3
 		ldm r2, {r0, r1, r2, r3}
-		sub r0, r2
-		sbc r1, r3
-		sbc r7, r7
-		eor r0, r7
-		eor r1, r7
-		sub r0, r7
-		sbc r1, r7
-		eor r7, r6
+		subs r0, r2
+		sbcs r1, r3
+		sbcs r7, r7
+		eors r0, r7
+		eors r1, r7
+		subs r0, r7
+		sbcs r1, r7
+		eors r7, r6
 		mov r12, r7
 		push {r0, r1}
 			//MUL64
-			mov r6, r5
-			mov r1, r2
-			sub r5, r4
-			sbc r0, r0
-			eor r5, r0
-			sub r5, r0
-			sub r1, r3
-			sbc r7, r7
-			eor r1, r7
-			sub r1, r7
-			eor r7, r0
+			adds r6, r5, #0
+			adds r1, r2, #0
+			subs r5, r4
+			sbcs r0, r0
+			eors r5, r0
+			subs r5, r0
+			subs r1, r3
+			sbcs r7, r7
+			eors r1, r7
+			subs r1, r7
+			eors r7, r0
 			mov r9, r1
 			mov r8, r5
-			lsr r1,r4,#16
+			lsrs r1,r4,#16
 			uxth r4,r4
-			mov r0,r4
+			adds r0, r4, #0
 			uxth r5,r2
-			lsr r2,#16
-			mul r0,r5//00
-			mul r5,r1//10
-			mul r4,r2//01
-			mul r1,r2//11
-			lsl r2,r4,#16
-			lsr r4,r4,#16
-			add r0,r2
-			adc r1,r4
-			lsl r2,r5,#16
-			lsr r4,r5,#16
-			add r0,r2
-			adc r1,r4
-			lsr r4, r6,#16
+			lsrs r2,#16
+			muls r0,r5//00
+			muls r5,r1//10
+			muls r4,r2//01
+			muls r1,r2//11
+			lsls r2,r4,#16
+			lsrs r4,r4,#16
+			adds r0, r0, r2
+			adcs r1,r4
+			lsls r2,r5,#16
+			lsrs r4,r5,#16
+			adds r0, r0, r2
+			adcs r1,r4
+			lsrs r4, r6,#16
 			uxth r6, r6
 			uxth r5, r3
-			lsr r3, r3, #16
-			mov r2, r6
-			mul r2, r5
-			mul r5, r4
-			mul r6, r3
-			mul r3, r4
-			lsl r4,r5,#16
-			lsr r5,r5,#16
-			add r2,r4
-			adc r3,r5
-			lsl r4,r6,#16
-			lsr r5,r6,#16
-			add r2,r4
-			adc r3,r5
-			eor r6, r6
-			add r2, r1
-			adc r3, r6
+			lsrs r3, r3, #16
+			adds r2, r6, #0
+			muls r2, r5
+			muls r5, r4
+			muls r6, r3
+			muls r3, r4
+			lsls r4,r5,#16
+			lsrs r5,r5,#16
+			adds r2, r2, r4
+			adcs r3,r5
+			lsls r4,r6,#16
+			lsrs r5,r6,#16
+			adds r2, r2, r4
+			adcs r3,r5
+			eors r6, r6
+			adds r2, r2, r1
+			adcs r3, r6
 			mov r1, r9
 			mov r5, r8
 			mov r8, r0
-			lsr r0, r1,#16
+			lsrs r0, r1,#16
 			uxth r1,r1
-			mov r4,r1
-			lsr r6,r5,#16
+			adds r4, r1, #0
+			lsrs r6,r5,#16
 			uxth r5,r5
-			mul r1,r5
-			mul r4,r6
-			mul r5,r0
-			mul r0,r6
-			lsl r6,r4,#16
-			lsr r4,#16
-			add r1,r6
-			adc r0,r4
-			lsl r6,r5,#16
-			lsr r5,#16
-			add r1,r6
-			adc r0,r5
-			eor r1,r7
-			eor r0,r7
-			eor r4, r4
-			asr r7, r7, #1
-			adc r1, r2
-			adc r2, r0
-			adc r7, r4
+			muls r1,r5
+			muls r4,r6
+			muls r5,r0
+			muls r0,r6
+			lsls r6,r4,#16
+			lsrs r4,#16
+			adds r1, r1, r6
+			adcs r0,r4
+			lsls r6,r5,#16
+			lsrs r5,#16
+			adds r1, r1, r6
+			adcs r0,r5
+			eors r1,r7
+			eors r0,r7
+			eors r4, r4
+			asrs r7, r7, #1
+			adcs r1, r2
+			adcs r2, r0
+			adcs r7, r4
 			mov r0, r8
-			add r1, r0
-			adc r2, r3
-			adc r3, r7
+			adds r1, r1, r0
+			adcs r2, r3
+			adcs r3, r7
 		mov r4, r10
 		mov r5, r11
-		eor r6, r6
-		add r0, r4
-		adc r1, r5
-		adc r2, r6
-		adc r3, r6
+		eors r6, r6
+		adds r0, r0, r4
+		adcs r1, r5
+		adcs r2, r6
+		adcs r3, r6
 		mov r10, r2
 		mov r11, r3
 		pop {r2-r5}
 		push {r0, r1}
-			mov r6, r5
-			mov r1, r2
-			sub r5, r4
-			sbc r0, r0
-			eor r5, r0
-			sub r5, r0
-			sub r1, r3
-			sbc r7, r7
-			eor r1, r7
-			sub r1, r7
-			eor r7, r0
+			adds r6, r5, #0
+			adds r1, r2, #0
+			subs r5, r4
+			sbcs r0, r0
+			eors r5, r0
+			subs r5, r0
+			subs r1, r3
+			sbcs r7, r7
+			eors r1, r7
+			subs r1, r7
+			eors r7, r0
 			mov r9, r1
 			mov r8, r5
-			lsr r1,r4,#16
+			lsrs r1,r4,#16
 			uxth r4,r4
-			mov r0,r4
+			adds r0, r4, #0
 			uxth r5,r2
-			lsr r2,#16
-			mul r0,r5//00
-			mul r5,r1//10
-			mul r4,r2//01
-			mul r1,r2//11
-			lsl r2,r4,#16
-			lsr r4,r4,#16
-			add r0,r2
-			adc r1,r4
-			lsl r2,r5,#16
-			lsr r4,r5,#16
-			add r0,r2
-			adc r1,r4
-			lsr r4, r6,#16
+			lsrs r2,#16
+			muls r0,r5//00
+			muls r5,r1//10
+			muls r4,r2//01
+			muls r1,r2//11
+			lsls r2,r4,#16
+			lsrs r4,r4,#16
+			adds r0, r0, r2
+			adcs r1,r4
+			lsls r2,r5,#16
+			lsrs r4,r5,#16
+			adds r0, r0, r2
+			adcs r1,r4
+			lsrs r4, r6,#16
 			uxth r6, r6
 			uxth r5, r3
-			lsr r3, r3, #16
-			mov r2, r6
-			mul r2, r5
-			mul r5, r4
-			mul r6, r3
-			mul r3, r4
-			lsl r4,r5,#16
-			lsr r5,r5,#16
-			add r2,r4
-			adc r3,r5
-			lsl r4,r6,#16
-			lsr r5,r6,#16
-			add r2,r4
-			adc r3,r5
-			eor r6, r6
-			add r2, r1
-			adc r3, r6
+			lsrs r3, r3, #16
+			adds r2, r6, #0
+			muls r2, r5
+			muls r5, r4
+			muls r6, r3
+			muls r3, r4
+			lsls r4,r5,#16
+			lsrs r5,r5,#16
+			adds r2, r2, r4
+			adcs r3,r5
+			lsls r4,r6,#16
+			lsrs r5,r6,#16
+			adds r2, r2, r4
+			adcs r3,r5
+			eors r6, r6
+			adds r2, r2, r1
+			adcs r3, r6
 			mov r1, r9
 			mov r5, r8
 			mov r8, r0
-			lsr r0, r1,#16
+			lsrs r0, r1,#16
 			uxth r1,r1
-			mov r4,r1
-			lsr r6,r5,#16
+			adds r4, r1, #0
+			lsrs r6,r5,#16
 			uxth r5,r5
-			mul r1,r5
-			mul r4,r6
-			mul r5,r0
-			mul r0,r6
-			lsl r6,r4,#16
-			lsr r4,#16
-			add r1,r6
-			adc r0,r4
-			lsl r6,r5,#16
-			lsr r5,#16
-			add r1,r6
-			adc r0,r5
-			eor r1,r7
-			eor r0,r7
-			eor r4, r4
-			asr r7, r7, #1
-			adc r1, r2
-			adc r2, r0
-			adc r7, r4
+			muls r1,r5
+			muls r4,r6
+			muls r5,r0
+			muls r0,r6
+			lsls r6,r4,#16
+			lsrs r4,#16
+			adds r1, r1, r6
+			adcs r0,r4
+			lsls r6,r5,#16
+			lsrs r5,#16
+			adds r1, r1, r6
+			adcs r0,r5
+			eors r1,r7
+			eors r0,r7
+			eors r4, r4
+			asrs r7, r7, #1
+			adcs r1, r2
+			adcs r2, r0
+			adcs r7, r4
 			mov r0, r8
-			add r1, r0
-			adc r2, r3
-			adc r3, r7
+			adds r1, r1, r0
+			adcs r2, r3
+			adcs r3, r7
 		pop {r4, r5}
 		mov r6, r12
 		mov r7, r12
-		eor r0, r6
-		eor r1, r6
-		eor r2, r6
-		eor r3, r6
-		asr r6, r6, #1
-		adc r0, r4
-		adc r1, r5
-		adc r4, r2
-		adc r5, r3
-		eor r2, r2
-		adc r6,r2 //0,1
-		adc r7,r2
+		eors r0, r6
+		eors r1, r6
+		eors r2, r6
+		eors r3, r6
+		asrs r6, r6, #1
+		adcs r0, r4
+		adcs r1, r5
+		adcs r4, r2
+		adcs r5, r3
+		eors r2, r2
+		adcs r6,r2 //0,1
+		adcs r7,r2
 		pop {r2, r3}
 		mov r8, r2
 		mov r9, r3
-		add r2, r0
-		adc r3, r1
+		adds r2, r2, r0
+		adcs r3, r1
 		mov r0, r10
 		mov r1, r11
-		adc r4, r0
-		adc r5, r1
-		adc r6, r0
-		adc r7, r1
+		adcs r4, r0
+		adcs r5, r1
+		adcs r6, r0
+		adcs r7, r1
 	//////////END MIDDLE PART////////////////
 	pop {r0,r1} //r0,r1
 	mov r12, r0 //negative
-	eor r2, r0
-	eor r3, r0
-	eor r4, r0
-	eor r5, r0
-	eor r6, r0
-	eor r7, r0
+	eors r2, r0
+	eors r3, r0
+	eors r4, r0
+	eors r5, r0
+	eors r6, r0
+	eors r7, r0
 	push {r4-r7}
 	ldm r1!, {r4-r7}
 	mov r11, r1 //reference
 	mov r1, r9
-	eor r1, r0
+	eors r1, r0
 	mov r10, r4
 	mov r4, r8
-	asr r0, #1
-	eor r0, r4
+	asrs r0, #1
+	eors r0, r4
 	mov r4, r10
-	adc r0, r4
-	adc r1, r5
-	adc r2, r6
-	adc r3, r7
-	eor r4, r4
-	adc r4, r4
+	adcs r0, r4
+	adcs r1, r5
+	adcs r2, r6
+	adcs r3, r7
+	eors r4, r4
+	adcs r4, r4
 	mov r10, r4 //carry
 	mov r4, r11
 	ldm r4, {r4-r7}
-	add r0, r4
-	adc r1, r5
-	adc r2, r6
-	adc r3, r7
+	adds r0, r0, r4
+	adcs r1, r5
+	adcs r2, r6
+	adcs r3, r7
 	mov r9, r4
 	mov r4, r11
 	stm r4!, {r0-r3}
 	mov r11, r4
 	pop {r0-r3}
 	mov r4, r9
-	adc r4, r0
-	adc r5, r1
-	adc r6, r2
-	adc r7, r3
-	mov r1, #0
-	adc r1, r1
+	adcs r4, r0
+	adcs r5, r1
+	adcs r6, r2
+	adcs r7, r3
+	movs r1, #0
+	adcs r1, r1
 	mov r0, r10
 	mov r10, r1 //carry
-	asr r0, #1
+	asrs r0, #1
 	pop {r0-r3}
-	adc r4, r0
-	adc r5, r1
-	adc r6, r2
-	adc r7, r3
+	adcs r4, r0
+	adcs r5, r1
+	adcs r6, r2
+	adcs r7, r3
 	mov r8, r0
 	mov r0, r11
 	stm r0!, {r4-r7}
@@ -1091,13 +1092,13 @@ multiply256x256_asm:
 	mov r0, r8
 	mov r6, r12
 	mov r5, r10
-	eor r4, r4
-	adc r5, r6
-	adc r6, r4
-	add r0, r5
-	adc r1, r6
-	adc r2, r6
-	adc r3, r6
+	eors r4, r4
+	adcs r5, r6
+	adcs r6, r4
+	adds r0, r0, r5
+	adcs r1, r6
+	adcs r2, r6
+	adcs r3, r6
 	mov r7, r11
 	stm r7!, {r0-r3}
 	pop {r3-r6}
@@ -1108,4 +1109,3 @@ multiply256x256_asm:
 	pop {r4-r7,pc}
 	bx	lr
 .size	multiply256x256_asm, .-multiply256x256_asm
-
diff --git a/third_party/unacl-curve25519/core/cortex-m0/curve25519/reduce25519.S b/third_party/unacl-curve25519/core/cortex-m0/curve25519/reduce25519.S
index 9a3c29a0f6..15e68373ea 100644
--- a/third_party/unacl-curve25519/core/cortex-m0/curve25519/reduce25519.S
+++ b/third_party/unacl-curve25519/core/cortex-m0/curve25519/reduce25519.S
@@ -8,6 +8,7 @@
 // Generated and tested with C++ functions in the test subdirectory and on the target.
 //
 
+	.syntax unified
 	.code	16
 
 	.text
@@ -21,143 +22,142 @@
 fe25519_reduceTo256Bits_asm:
     push {r4,r5,r6,r7,r14}
     ldr r2,[r1,#60]
-    lsr r3,r2,#16
+    lsrs r3,r2,#16
     uxth r2,r2
-    mov r7,#38
-    mul r2,r7
-    mul r3,r7
+    movs r7,#38
+    muls r2,r7
+    muls r3,r7
     ldr r4,[r1,#28]
-    lsr r5,r3,#16
-    lsl r3,r3,#16
-    mov r6,#0
-    add r4,r2
-    adc r5,r6
-    add r4,r3
-    adc r5,r6
-    lsl r2,r4,#1
-    lsr r2,r2,#1
+    lsrs r5,r3,#16
+    lsls r3,r3,#16
+    movs r6,#0
+    adds r4,r4,r2
+    adcs r5,r6
+    adds r4,r4,r3
+    adcs r5,r6
+    lsls r2,r4,#1
+    lsrs r2,r2,#1
     str r2,[r0,#28]
-    lsr r4,r4,#31
-    lsl r5,r5,#1
-    orr r4,r5
-    mov r2,#19
-    mul r2,r4
+    lsrs r4,r4,#31
+    lsls r5,r5,#1
+    orrs r4,r5
+    movs r2,#19
+    muls r2,r4
     ldr r4,[r1,#0]
-    add r2,r4
-    mov r3,#0
-    adc r3,r6
+    adds r2,r2,r4
+    movs r3,#0
+    adcs r3,r6
     ldr r4,[r1,#32]
-    lsr r5,r4,#16
+    lsrs r5,r4,#16
     uxth r4,r4
-    mul r5,r7
-    mul r4,r7
-    add r2,r4
-    adc r3,r6
-    lsl r4,r5,#16
-    lsr r5,r5,#16
-    add r2,r4
-    adc r3,r5
+    muls r5,r7
+    muls r4,r7
+    adds r2,r2,r4
+    adcs r3,r6
+    lsls r4,r5,#16
+    lsrs r5,r5,#16
+    adds r2,r2,r4
+    adcs r3,r5
     str r2,[r0,#0]
     ldr r4,[r1,#4]
-    add r3,r4
-    mov r2,#0
-    adc r2,r6
+    adds r3,r3,r4
+    movs r2,#0
+    adcs r2,r6
     ldr r4,[r1,#36]
-    lsr r5,r4,#16
+    lsrs r5,r4,#16
     uxth r4,r4
-    mul r5,r7
-    mul r4,r7
-    add r3,r4
-    adc r2,r6
-    lsl r4,r5,#16
-    lsr r5,r5,#16
-    add r3,r4
-    adc r2,r5
+    muls r5,r7
+    muls r4,r7
+    adds r3,r3,r4
+    adcs r2,r6
+    lsls r4,r5,#16
+    lsrs r5,r5,#16
+    adds r3,r3,r4
+    adcs r2,r5
     str r3,[r0,#4]
     ldr r4,[r1,#8]
-    add r2,r4
-    mov r3,#0
-    adc r3,r6
+    adds r2,r2,r4
+    movs r3,#0
+    adcs r3,r6
     ldr r4,[r1,#40]
-    lsr r5,r4,#16
+    lsrs r5,r4,#16
     uxth r4,r4
-    mul r5,r7
-    mul r4,r7
-    add r2,r4
-    adc r3,r6
-    lsl r4,r5,#16
-    lsr r5,r5,#16
-    add r2,r4
-    adc r3,r5
+    muls r5,r7
+    muls r4,r7
+    adds r2,r2,r4
+    adcs r3,r6
+    lsls r4,r5,#16
+    lsrs r5,r5,#16
+    adds r2,r2,r4
+    adcs r3,r5
     str r2,[r0,#8]
     ldr r4,[r1,#12]
-    add r3,r4
-    mov r2,#0
-    adc r2,r6
+    adds r3,r3,r4
+    movs r2,#0
+    adcs r2,r6
     ldr r4,[r1,#44]
-    lsr r5,r4,#16
+    lsrs r5,r4,#16
     uxth r4,r4
-    mul r5,r7
-    mul r4,r7
-    add r3,r4
-    adc r2,r6
-    lsl r4,r5,#16
-    lsr r5,r5,#16
-    add r3,r4
-    adc r2,r5
+    muls r5,r7
+    muls r4,r7
+    adds r3,r3,r4
+    adcs r2,r6
+    lsls r4,r5,#16
+    lsrs r5,r5,#16
+    adds r3,r3,r4
+    adcs r2,r5
     str r3,[r0,#12]
     ldr r4,[r1,#16]
-    add r2,r4
-    mov r3,#0
-    adc r3,r6
+    adds r2,r2,r4
+    movs r3,#0
+    adcs r3,r6
     ldr r4,[r1,#48]
-    lsr r5,r4,#16
+    lsrs r5,r4,#16
     uxth r4,r4
-    mul r5,r7
-    mul r4,r7
-    add r2,r4
-    adc r3,r6
-    lsl r4,r5,#16
-    lsr r5,r5,#16
-    add r2,r4
-    adc r3,r5
+    muls r5,r7
+    muls r4,r7
+    adds r2,r2,r4
+    adcs r3,r6
+    lsls r4,r5,#16
+    lsrs r5,r5,#16
+    adds r2,r2,r4
+    adcs r3,r5
     str r2,[r0,#16]
     ldr r4,[r1,#20]
-    add r3,r4
-    mov r2,#0
-    adc r2,r6
+    adds r3,r3,r4
+    movs r2,#0
+    adcs r2,r6
     ldr r4,[r1,#52]
-    lsr r5,r4,#16
+    lsrs r5,r4,#16
     uxth r4,r4
-    mul r5,r7
-    mul r4,r7
-    add r3,r4
-    adc r2,r6
-    lsl r4,r5,#16
-    lsr r5,r5,#16
-    add r3,r4
-    adc r2,r5
+    muls r5,r7
+    muls r4,r7
+    adds r3,r3,r4
+    adcs r2,r6
+    lsls r4,r5,#16
+    lsrs r5,r5,#16
+    adds r3,r3,r4
+    adcs r2,r5
     str r3,[r0,#20]
     ldr r4,[r1,#24]
-    add r2,r4
-    mov r3,#0
-    adc r3,r6
+    adds r2,r2,r4
+    movs r3,#0
+    adcs r3,r6
     ldr r4,[r1,#56]
-    lsr r5,r4,#16
+    lsrs r5,r4,#16
     uxth r4,r4
-    mul r5,r7
-    mul r4,r7
-    add r2,r4
-    adc r3,r6
-    lsl r4,r5,#16
-    lsr r5,r5,#16
-    add r2,r4
-    adc r3,r5
+    muls r5,r7
+    muls r4,r7
+    adds r2,r2,r4
+    adcs r3,r6
+    lsls r4,r5,#16
+    lsrs r5,r5,#16
+    adds r2,r2,r4
+    adcs r3,r5
     str r2,[r0,#24]
     ldr r4,[r0,#28]
-    add r4,r3
+    adds r4,r4,r3
     str r4,[r0,#28]
     pop {r4,r5,r6,r7,r15}
 
 	.size	fe25519_reduceTo256Bits_asm, .-fe25519_reduceTo256Bits_asm
-
diff --git a/third_party/unacl-curve25519/core/cortex-m0/curve25519/sqr.S b/third_party/unacl-curve25519/core/cortex-m0/curve25519/sqr.S
index b62121adb7..340564e87b 100644
--- a/third_party/unacl-curve25519/core/cortex-m0/curve25519/sqr.S
+++ b/third_party/unacl-curve25519/core/cortex-m0/curve25519/sqr.S
@@ -3,6 +3,7 @@
 // public domain
 //
 
+ .syntax unified
  .align	2
 	.global	square256_asm
 	.type	square256_asm, %function
@@ -15,38 +16,30 @@ square256_asm:
  // pResult in r0
  // adheres to arm eabi calling convention.
     push {r1,r4,r5,r6,r7,r14}
-    .syntax unified
     mov r3,r8
     mov r4,r9
     mov r5,r10
     mov r6,r11
     mov r7,r12
-    .syntax divided
     push {r3,r4,r5,r6,r7}
-    .syntax unified
     mov r14,r0
-    .syntax divided
-    ldm r1!,{r4,r5,r6,r7}
+    ldmia r1!,{r4,r5,r6,r7}
  // sqr 128 Refined Karatsuba
  // Input in r4 ... r7
  // Result in r0 ... r7
  // clobbers all registers except for r14
-    .syntax unified
     mov r0,r4
     mov r1,r5
-    .syntax divided
-    sub r0,r6
-    sbc r1,r7
-    sbc r2,r2
-    eor r0,r2
-    eor r1,r2
-    sub r0,r2
-    sbc r1,r2
-    .syntax unified
+    subs r0,r6
+    sbcs r1,r7
+    sbcs r2,r2
+    eors r0,r2
+    eors r1,r2
+    subs r0,r2
+    sbcs r1,r2
     mov r8,r0
     mov r9,r1
     mov r10,r6
-    .syntax divided
  // START: sqr 64 Refined Karatsuba
  // Input operands in r4,r5
  // Result in r0,r1,r2,r3
@@ -56,85 +49,73 @@ square256_asm:
  // Result in r0 ,r1
  // Clobbers: r2, r3
     uxth r0,r4
-    lsr r1,r4,#16
-    .syntax unified
+    lsrs r1,r4,#16
     mov r2,r0
-    .syntax divided
-    mul r2,r1
-    mul r0,r0
-    mul r1,r1
-    lsr r3,r2,#15
-    lsl r2,r2,#17
-    add r0,r2
-    adc r1,r3
+    muls r2,r1
+    muls r0,r0
+    muls r1,r1
+    lsrs r3,r2,#15
+    lsls r2,r2,#17
+    adds r0,r0,r2
+    adcs r1,r3
  // End: sqr 32
  // Result in r0 ,r1
-    sub r4,r5
-    sbc r6,r6
-    eor r4,r6
-    sub r4,r6
+    subs r4,r5
+    sbcs r6,r6
+    eors r4,r6
+    subs r4,r6
  // START: sqr 32
  // Input operand in r5
  // Result in r2 ,r3
  // Clobbers: r5, r6
     uxth r2,r5
-    lsr r3,r5,#16
-    .syntax unified
+    lsrs r3,r5,#16
     mov r5,r2
-    .syntax divided
-    mul r5,r3
-    mul r2,r2
-    mul r3,r3
-    lsr r6,r5,#15
-    lsl r5,r5,#17
-    add r2,r5
-    adc r3,r6
+    muls r5,r3
+    muls r2,r2
+    muls r3,r3
+    lsrs r6,r5,#15
+    lsls r5,r5,#17
+    adds r2,r2,r5
+    adcs r3,r6
  // End: sqr 32
  // Result in r2 ,r3
-    mov r6,#0
-    add r2,r1
-    adc r3,r6
+    movs r6,#0
+    adds r2,r2,r1
+    adcs r3,r6
  // START: sqr 32
  // Input operand in r4
  // Result in r4 ,r5
  // Clobbers: r1, r6
-    lsr r5,r4,#16
+    lsrs r5,r4,#16
     uxth r4,r4
-    .syntax unified
     mov r1,r4
-    .syntax divided
-    mul r1,r5
-    mul r4,r4
-    mul r5,r5
-    lsr r6,r1,#15
-    lsl r1,r1,#17
-    add r4,r1
-    adc r5,r6
+    muls r1,r5
+    muls r4,r4
+    muls r5,r5
+    lsrs r6,r1,#15
+    lsls r1,r1,#17
+    adds r4,r4,r1
+    adcs r5,r6
  // End: sqr 32
  // Result in r4 ,r5
-    .syntax unified
     mov r1,r2
-    .syntax divided
-    sub r1,r4
-    sbc r2,r5
-    .syntax unified
+    subs r1,r4
+    sbcs r2,r5
     mov r5,r3
-    .syntax divided
-    mov r6,#0
-    sbc r3,r6
-    add r1,r0
-    adc r2,r5
-    adc r3,r6
+    movs r6,#0
+    sbcs r3,r6
+    adds r1,r1,r0
+    adcs r2,r5
+    adcs r3,r6
  // END: sqr 64 Refined Karatsuba
  // Result in r0,r1,r2,r3
  // Leaves r6 zero.
-    .syntax unified
     mov r6,r10
     mov r10,r0
     mov r11,r1
     mov r12,r2
     mov r1,r3
-    .syntax divided
  // START: sqr 64 Refined Karatsuba
  // Input operands in r6,r7
  // Result in r2,r3,r4,r5
@@ -144,92 +125,78 @@ square256_asm:
  // Result in r2 ,r3
  // Clobbers: r4, r5
     uxth r2,r6
-    lsr r3,r6,#16
-    .syntax unified
+    lsrs r3,r6,#16
     mov r4,r2
-    .syntax divided
-    mul r4,r3
-    mul r2,r2
-    mul r3,r3
-    lsr r5,r4,#15
-    lsl r4,r4,#17
-    add r2,r4
-    adc r3,r5
+    muls r4,r3
+    muls r2,r2
+    muls r3,r3
+    lsrs r5,r4,#15
+    lsls r4,r4,#17
+    adds r2,r2,r4
+    adcs r3,r5
  // End: sqr 32
  // Result in r2 ,r3
-    sub r6,r7
-    sbc r4,r4
-    eor r6,r4
-    sub r6,r4
+    subs r6,r7
+    sbcs r4,r4
+    eors r6,r4
+    subs r6,r4
  // START: sqr 32
  // Input operand in r7
  // Result in r4 ,r5
  // Clobbers: r0, r7
     uxth r4,r7
-    lsr r5,r7,#16
-    .syntax unified
+    lsrs r5,r7,#16
     mov r0,r4
-    .syntax divided
-    mul r0,r5
-    mul r4,r4
-    mul r5,r5
-    lsr r7,r0,#15
-    lsl r0,r0,#17
-    add r4,r0
-    adc r5,r7
+    muls r0,r5
+    muls r4,r4
+    muls r5,r5
+    lsrs r7,r0,#15
+    lsls r0,r0,#17
+    adds r4,r4,r0
+    adcs r5,r7
  // End: sqr 32
  // Result in r4 ,r5
-    mov r7,#0
-    add r4,r3
-    adc r5,r7
+    movs r7,#0
+    adds r4,r4,r3
+    adcs r5,r7
  // START: sqr 32
  // Input operand in r6
  // Result in r7 ,r0
  // Clobbers: r6, r3
     uxth r7,r6
-    lsr r0,r6,#16
-    .syntax unified
+    lsrs r0,r6,#16
     mov r6,r7
-    .syntax divided
-    mul r6,r0
-    mul r7,r7
-    mul r0,r0
-    lsr r3,r6,#15
-    lsl r6,r6,#17
-    add r7,r6
-    adc r0,r3
+    muls r6,r0
+    muls r7,r7
+    muls r0,r0
+    lsrs r3,r6,#15
+    lsls r6,r6,#17
+    adds r7,r7,r6
+    adcs r0,r3
  // End: sqr 32
  // Result in r7 ,r0
-    .syntax unified
     mov r3,r4
-    .syntax divided
-    sub r3,r7
-    sbc r4,r0
-    .syntax unified
+    subs r3,r7
+    sbcs r4,r0
     mov r0,r5
-    .syntax divided
-    mov r6,#0
-    sbc r5,r6
-    add r3,r2
-    adc r4,r0
-    adc r5,r6
+    movs r6,#0
+    sbcs r5,r6
+    adds r3,r3,r2
+    adcs r4,r0
+    adcs r5,r6
  // END: sqr 64 Refined Karatsuba
  // Result in r2,r3,r4,r5
  // Leaves r6 zero.
-    .syntax unified
     mov r0,r12
-    .syntax divided
-    add r2,r0
-    adc r3,r1
-    adc r4,r6
-    adc r5,r6
-    .syntax unified
+    adds r2,r2,r0
+    adcs r3,r1
+    adcs r4,r6
+    adcs r5,r6
     mov r12,r2
     mov r2,r8
     mov r8,r3
     mov r3,r9
     mov r9,r4
-    .syntax divided
  // START: sqr 64 Refined Karatsuba
  // Input operands in r2,r3
  // Result in r6,r7,r0,r1
@@ -239,146 +206,116 @@ square256_asm:
  // Result in r6 ,r7
  // Clobbers: r0, r1
     uxth r6,r2
-    lsr r7,r2,#16
-    .syntax unified
+    lsrs r7,r2,#16
     mov r0,r6
-    .syntax divided
-    mul r0,r7
-    mul r6,r6
-    mul r7,r7
-    lsr r1,r0,#15
-    lsl r0,r0,#17
-    add r6,r0
-    adc r7,r1
+    muls r0,r7
+    muls r6,r6
+    muls r7,r7
+    lsrs r1,r0,#15
+    lsls r0,r0,#17
+    adds r6,r6,r0
+    adcs r7,r1
  // End: sqr 32
  // Result in r6 ,r7
-    sub r2,r3
-    sbc r4,r4
-    eor r2,r4
-    sub r2,r4
+    subs r2,r3
+    sbcs r4,r4
+    eors r2,r4
+    subs r2,r4
  // START: sqr 32
  // Input operand in r3
  // Result in r0 ,r1
  // Clobbers: r3, r4
     uxth r0,r3
-    lsr r1,r3,#16
-    .syntax unified
+    lsrs r1,r3,#16
     mov r3,r0
-    .syntax divided
-    mul r3,r1
-    mul r0,r0
-    mul r1,r1
-    lsr r4,r3,#15
-    lsl r3,r3,#17
-    add r0,r3
-    adc r1,r4
+    muls r3,r1
+    muls r0,r0
+    muls r1,r1
+    lsrs r4,r3,#15
+    lsls r3,r3,#17
+    adds r0,r0,r3
+    adcs r1,r4
  // End: sqr 32
  // Result in r0 ,r1
-    mov r4,#0
-    add r0,r7
-    adc r1,r4
+    movs r4,#0
+    adds r0,r0,r7
+    adcs r1,r4
  // START: sqr 32
  // Input operand in r2
  // Result in r3 ,r4
  // Clobbers: r2, r7
     uxth r3,r2
-    lsr r4,r2,#16
-    .syntax unified
+    lsrs r4,r2,#16
     mov r2,r3
-    .syntax divided
-    mul r2,r4
-    mul r3,r3
-    mul r4,r4
-    lsr r7,r2,#15
-    lsl r2,r2,#17
-    add r3,r2
-    adc r4,r7
+    muls r2,r4
+    muls r3,r3
+    muls r4,r4
+    lsrs r7,r2,#15
+    lsls r2,r2,#17
+    adds r3,r3,r2
+    adcs r4,r7
  // End: sqr 32
  // Result in r3 ,r4
-    .syntax unified
     mov r7,r0
-    .syntax divided
-    sub r7,r3
-    sbc r0,r4
-    .syntax unified
+    subs r7,r3
+    sbcs r0,r4
     mov r2,r1
-    .syntax divided
-    mov r4,#0
-    sbc r1,r4
-    add r7,r6
-    adc r0,r2
-    adc r1,r4
+    movs r4,#0
+    sbcs r1,r4
+    adds r7,r7,r6
+    adcs r0,r2
+    adcs r1,r4
  // END: sqr 64 Refined Karatsuba
  // Result in r6,r7,r0,r1
  // Returns r4 as zero.
-    .syntax unified
     mov r2,r12
     mov r3,r8
     mov r4,r9
-    .syntax divided
-    sub r2,r6
-    sbc r3,r7
-    .syntax unified
+    subs r2,r6
+    sbcs r3,r7
     mov r6,r4
     mov r7,r5
-    .syntax divided
-    sbc r4,r0
-    sbc r5,r1
-    mov r0,#0
-    sbc r6,r0
-    sbc r7,r0
-    .syntax unified
+    sbcs r4,r0
+    sbcs r5,r1
+    movs r0,#0
+    sbcs r6,r0
+    sbcs r7,r0
     mov r0,r10
-    .syntax divided
-    add r2,r0
-    .syntax unified
+    adds r2,r2,r0
     mov r1,r11
-    .syntax divided
-    adc r3,r1
-    .syntax unified
+    adcs r3,r1
     mov r0,r12
-    .syntax divided
-    adc r4,r0
-    .syntax unified
+    adcs r4,r0
     mov r0,r8
-    .syntax divided
-    adc r5,r0
-    mov r0,#0
-    adc r6,r0
-    adc r7,r0
-    .syntax unified
+    adcs r5,r0
+    movs r0,#0
+    adcs r6,r0
+    adcs r7,r0
     mov r0,r10
-    .syntax divided
  // END: sqr 128 Refined Karatsuba
  // Result in r0 ... r7
     push {r4,r5,r6,r7}
-    .syntax unified
     mov r4,r14
-    .syntax divided
     stm r4!,{r0,r1,r2,r3}
     ldr r4,[SP,#36]
-    add r4,#16
+    adds r4,#16
     ldm r4,{r4,r5,r6,r7}
  // sqr 128 Refined Karatsuba
  // Input in r4 ... r7
  // Result in r0 ... r7
  // clobbers all registers except for r14
-    .syntax unified
     mov r0,r4
     mov r1,r5
-    .syntax divided
-    sub r0,r6
-    sbc r1,r7
-    sbc r2,r2
-    eor r0,r2
-    eor r1,r2
-    sub r0,r2
-    sbc r1,r2
-    .syntax unified
+    subs r0,r6
+    sbcs r1,r7
+    sbcs r2,r2
+    eors r0,r2
+    eors r1,r2
+    subs r0,r2
+    sbcs r1,r2
     mov r8,r0
     mov r9,r1
     mov r10,r6
-    .syntax divided
  // START: sqr 64 Refined Karatsuba
  // Input operands in r4,r5
  // Result in r0,r1,r2,r3
@@ -388,85 +325,73 @@ square256_asm:
  // Result in r0 ,r1
  // Clobbers: r2, r3
     uxth r0,r4
-    lsr r1,r4,#16
-    .syntax unified
+    lsrs r1,r4,#16
     mov r2,r0
-    .syntax divided
-    mul r2,r1
-    mul r0,r0
-    mul r1,r1
-    lsr r3,r2,#15
-    lsl r2,r2,#17
-    add r0,r2
-    adc r1,r3
+    muls r2,r1
+    muls r0,r0
+    muls r1,r1
+    lsrs r3,r2,#15
+    lsls r2,r2,#17
+    adds r0,r0,r2
+    adcs r1,r3
  // End: sqr 32
  // Result in r0 ,r1
-    sub r4,r5
-    sbc r6,r6
-    eor r4,r6
-    sub r4,r6
+    subs r4,r5
+    sbcs r6,r6
+    eors r4,r6
+    subs r4,r6
  // START: sqr 32
  // Input operand in r5
  // Result in r2 ,r3
  // Clobbers: r5, r6
     uxth r2,r5
-    lsr r3,r5,#16
-    .syntax unified
+    lsrs r3,r5,#16
     mov r5,r2
-    .syntax divided
-    mul r5,r3
-    mul r2,r2
-    mul r3,r3
-    lsr r6,r5,#15
-    lsl r5,r5,#17
-    add r2,r5
-    adc r3,r6
+    muls r5,r3
+    muls r2,r2
+    muls r3,r3
+    lsrs r6,r5,#15
+    lsls r5,r5,#17
+    adds r2,r2,r5
+    adcs r3,r6
  // End: sqr 32
  // Result in r2 ,r3
-    mov r6,#0
-    add r2,r1
-    adc r3,r6
+    movs r6,#0
+    adds r2,r2,r1
+    adcs r3,r6
  // START: sqr 32
  // Input operand in r4
  // Result in r4 ,r5
  // Clobbers: r1, r6
-    lsr r5,r4,#16
+    lsrs r5,r4,#16
     uxth r4,r4
-    .syntax unified
     mov r1,r4
-    .syntax divided
-    mul r1,r5
-    mul r4,r4
-    mul r5,r5
-    lsr r6,r1,#15
-    lsl r1,r1,#17
-    add r4,r1
-    adc r5,r6
+    muls r1,r5
+    muls r4,r4
+    muls r5,r5
+    lsrs r6,r1,#15
+    lsls r1,r1,#17
+    adds r4,r4,r1
+    adcs r5,r6
  // End: sqr 32
  // Result in r4 ,r5
-    .syntax unified
     mov r1,r2
-    .syntax divided
-    sub r1,r4
-    sbc r2,r5
-    .syntax unified
+    subs r1,r4
+    sbcs r2,r5
     mov r5,r3
-    .syntax divided
-    mov r6,#0
-    sbc r3,r6
-    add r1,r0
-    adc r2,r5
-    adc r3,r6
+    movs r6,#0
+    sbcs r3,r6
+    adds r1,r1,r0
+    adcs r2,r5
+    adcs r3,r6
  // END: sqr 64 Refined Karatsuba
  // Result in r0,r1,r2,r3
  // Leaves r6 zero.
-    .syntax unified
     mov r6,r10
     mov r10,r0
     mov r11,r1
     mov r12,r2
     mov r1,r3
-    .syntax divided
  // START: sqr 64 Refined Karatsuba
  // Input operands in r6,r7
  // Result in r2,r3,r4,r5
@@ -476,92 +401,78 @@ square256_asm:
  // Result in r2 ,r3
  // Clobbers: r4, r5
     uxth r2,r6
-    lsr r3,r6,#16
-    .syntax unified
+    lsrs r3,r6,#16
     mov r4,r2
-    .syntax divided
-    mul r4,r3
-    mul r2,r2
-    mul r3,r3
-    lsr r5,r4,#15
-    lsl r4,r4,#17
-    add r2,r4
-    adc r3,r5
+    muls r4,r3
+    muls r2,r2
+    muls r3,r3
+    lsrs r5,r4,#15
+    lsls r4,r4,#17
+    adds r2,r2,r4
+    adcs r3,r5
  // End: sqr 32
  // Result in r2 ,r3
-    sub r6,r7
-    sbc r4,r4
-    eor r6,r4
-    sub r6,r4
+    subs r6,r7
+    sbcs r4,r4
+    eors r6,r4
+    subs r6,r4
  // START: sqr 32
  // Input operand in r7
  // Result in r4 ,r5
  // Clobbers: r0, r7
     uxth r4,r7
-    lsr r5,r7,#16
-    .syntax unified
+    lsrs r5,r7,#16
     mov r0,r4
-    .syntax divided
-    mul r0,r5
-    mul r4,r4
-    mul r5,r5
-    lsr r7,r0,#15
-    lsl r0,r0,#17
-    add r4,r0
-    adc r5,r7
+    muls r0,r5
+    muls r4,r4
+    muls r5,r5
+    lsrs r7,r0,#15
+    lsls r0,r0,#17
+    adds r4,r4,r0
+    adcs r5,r7
  // End: sqr 32
  // Result in r4 ,r5
-    mov r7,#0
-    add r4,r3
-    adc r5,r7
+    movs r7,#0
+    adds r4,r4,r3
+    adcs r5,r7
  // START: sqr 32
  // Input operand in r6
  // Result in r7 ,r0
  // Clobbers: r6, r3
     uxth r7,r6
-    lsr r0,r6,#16
-    .syntax unified
+    lsrs r0,r6,#16
     mov r6,r7
-    .syntax divided
-    mul r6,r0
-    mul r7,r7
-    mul r0,r0
-    lsr r3,r6,#15
-    lsl r6,r6,#17
-    add r7,r6
-    adc r0,r3
+    muls r6,r0
+    muls r7,r7
+    muls r0,r0
+    lsrs r3,r6,#15
+    lsls r6,r6,#17
+    adds r7,r7,r6
+    adcs r0,r3
  // End: sqr 32
  // Result in r7 ,r0
-    .syntax unified
     mov r3,r4
-    .syntax divided
-    sub r3,r7
-    sbc r4,r0
-    .syntax unified
+    subs r3,r7
+    sbcs r4,r0
     mov r0,r5
-    .syntax divided
-    mov r6,#0
-    sbc r5,r6
-    add r3,r2
-    adc r4,r0
-    adc r5,r6
+    movs r6,#0
+    sbcs r5,r6
+    adds r3,r3,r2
+    adcs r4,r0
+    adcs r5,r6
  // END: sqr 64 Refined Karatsuba
  // Result in r2,r3,r4,r5
  // Leaves r6 zero.
-    .syntax unified
     mov r0,r12
-    .syntax divided
-    add r2,r0
-    adc r3,r1
-    adc r4,r6
-    adc r5,r6
-    .syntax unified
+    adds r2,r2,r0
+    adcs r3,r1
+    adcs r4,r6
+    adcs r5,r6
     mov r12,r2
     mov r2,r8
     mov r8,r3
     mov r3,r9
     mov r9,r4
-    .syntax divided
  // START: sqr 64 Refined Karatsuba
  // Input operands in r2,r3
  // Result in r6,r7,r0,r1
@@ -571,180 +482,146 @@ square256_asm:
  // Result in r6 ,r7
  // Clobbers: r0, r1
     uxth r6,r2
-    lsr r7,r2,#16
-    .syntax unified
+    lsrs r7,r2,#16
     mov r0,r6
-    .syntax divided
-    mul r0,r7
-    mul r6,r6
-    mul r7,r7
-    lsr r1,r0,#15
-    lsl r0,r0,#17
-    add r6,r0
-    adc r7,r1
+    muls r0,r7
+    muls r6,r6
+    muls r7,r7
+    lsrs r1,r0,#15
+    lsls r0,r0,#17
+    adds r6,r6,r0
+    adcs r7,r1
  // End: sqr 32
  // Result in r6 ,r7
-    sub r2,r3
-    sbc r4,r4
-    eor r2,r4
-    sub r2,r4
+    subs r2,r3
+    sbcs r4,r4
+    eors r2,r4
+    subs r2,r4
  // START: sqr 32
  // Input operand in r3
  // Result in r0 ,r1
  // Clobbers: r3, r4
     uxth r0,r3
-    lsr r1,r3,#16
-    .syntax unified
+    lsrs r1,r3,#16
     mov r3,r0
-    .syntax divided
-    mul r3,r1
-    mul r0,r0
-    mul r1,r1
-    lsr r4,r3,#15
-    lsl r3,r3,#17
-    add r0,r3
-    adc r1,r4
+    muls r3,r1
+    muls r0,r0
+    muls r1,r1
+    lsrs r4,r3,#15
+    lsls r3,r3,#17
+    adds r0,r0,r3
+    adcs r1,r4
  // End: sqr 32
  // Result in r0 ,r1
-    mov r4,#0
-    add r0,r7
-    adc r1,r4
+    movs r4,#0
+    adds r0,r0,r7
+    adcs r1,r4
  // START: sqr 32
  // Input operand in r2
  // Result in r3 ,r4
  // Clobbers: r2, r7
     uxth r3,r2
-    lsr r4,r2,#16
-    .syntax unified
+    lsrs r4,r2,#16
     mov r2,r3
-    .syntax divided
-    mul r2,r4
-    mul r3,r3
-    mul r4,r4
-    lsr r7,r2,#15
-    lsl r2,r2,#17
-    add r3,r2
-    adc r4,r7
+    muls r2,r4
+    muls r3,r3
+    muls r4,r4
+    lsrs r7,r2,#15
+    lsls r2,r2,#17
+    adds r3,r3,r2
+    adcs r4,r7
  // End: sqr 32
  // Result in r3 ,r4
-    .syntax unified
     mov r7,r0
-    .syntax divided
-    sub r7,r3
-    sbc r0,r4
-    .syntax unified
+    subs r7,r3
+    sbcs r0,r4
     mov r2,r1
-    .syntax divided
-    mov r4,#0
-    sbc r1,r4
-    add r7,r6
-    adc r0,r2
-    adc r1,r4
+    movs r4,#0
+    sbcs r1,r4
+    adds r7,r7,r6
+    adcs r0,r2
+    adcs r1,r4
  // END: sqr 64 Refined Karatsuba
  // Result in r6,r7,r0,r1
  // Returns r4 as zero.
-    .syntax unified
     mov r2,r12
     mov r3,r8
     mov r4,r9
-    .syntax divided
-    sub r2,r6
-    sbc r3,r7
-    .syntax unified
+    subs r2,r6
+    sbcs r3,r7
     mov r6,r4
     mov r7,r5
-    .syntax divided
-    sbc r4,r0
-    sbc r5,r1
-    mov r0,#0
-    sbc r6,r0
-    sbc r7,r0
-    .syntax unified
+    sbcs r4,r0
+    sbcs r5,r1
+    movs r0,#0
+    sbcs r6,r0
+    sbcs r7,r0
     mov r0,r10
-    .syntax divided
-    add r2,r0
-    .syntax unified
+    adds r2,r2,r0
     mov r1,r11
-    .syntax divided
-    adc r3,r1
-    .syntax unified
+    adcs r3,r1
     mov r0,r12
-    .syntax divided
-    adc r4,r0
-    .syntax unified
+    adcs r4,r0
     mov r0,r8
-    .syntax divided
-    adc r5,r0
-    mov r0,#0
-    adc r6,r0
-    adc r7,r0
-    .syntax unified
+    adcs r5,r0
+    movs r0,#0
+    adcs r6,r0
+    adcs r7,r0
     mov r0,r10
-    .syntax divided
  // END: sqr 128 Refined Karatsuba
  // Result in r0 ... r7
-    .syntax unified
     mov r8,r4
     mov r9,r5
     mov r10,r6
     mov r11,r7
-    .syntax divided
     pop {r4,r5,r6,r7}
-    add r0,r4
-    adc r1,r5
-    adc r2,r6
-    adc r3,r7
-    .syntax unified
+    adds r0,r0,r4
+    adcs r1,r5
+    adcs r2,r6
+    adcs r3,r7
     mov r4,r8
     mov r5,r9
     mov r6,r10
     mov r7,r11
     mov r8,r0
-    .syntax divided
-    mov r0,#0
-    adc r4,r0
-    adc r5,r0
-    adc r6,r0
-    adc r7,r0
-    .syntax unified
+    movs r0,#0
+    adcs r4,r0
+    adcs r5,r0
+    adcs r6,r0
+    adcs r7,r0
     mov r0,r8
-    .syntax divided
     push {r0,r1,r2,r3,r4,r5,r6,r7}
     ldr r4,[SP,#52]
     ldm r4,{r0,r1,r2,r3,r4,r5,r6,r7}
-    sub r4,r0
-    sbc r5,r1
-    sbc r6,r2
-    sbc r7,r3
-    sbc r0,r0
-    eor r4,r0
-    eor r5,r0
-    eor r6,r0
-    eor r7,r0
-    sub r4,r0
-    sbc r5,r0
-    sbc r6,r0
-    sbc r7,r0
+    subs r4,r0
+    sbcs r5,r1
+    sbcs r6,r2
+    sbcs r7,r3
+    sbcs r0,r0
+    eors r4,r0
+    eors r5,r0
+    eors r6,r0
+    eors r7,r0
+    subs r4,r0
+    sbcs r5,r0
+    sbcs r6,r0
+    sbcs r7,r0
  // sqr 128 Refined Karatsuba
  // Input in r4 ... r7
  // Result in r0 ... r7
  // clobbers all registers except for r14
-    .syntax unified
     mov r0,r4
     mov r1,r5
-    .syntax divided
-    sub r0,r6
-    sbc r1,r7
-    sbc r2,r2
-    eor r0,r2
-    eor r1,r2
-    sub r0,r2
-    sbc r1,r2
-    .syntax unified
+    subs r0,r6
+    sbcs r1,r7
+    sbcs r2,r2
+    eors r0,r2
+    eors r1,r2
+    subs r0,r2
+    sbcs r1,r2
     mov r8,r0
     mov r9,r1
     mov r10,r6
-    .syntax divided
  // START: sqr 64 Refined Karatsuba
  // Input operands in r4,r5
  // Result in r0,r1,r2,r3
@@ -754,85 +631,73 @@ square256_asm:
  // Result in r0 ,r1
  // Clobbers: r2, r3
     uxth r0,r4
-    lsr r1,r4,#16
-    .syntax unified
+    lsrs r1,r4,#16
     mov r2,r0
-    .syntax divided
-    mul r2,r1
-    mul r0,r0
-    mul r1,r1
-    lsr r3,r2,#15
-    lsl r2,r2,#17
-    add r0,r2
-    adc r1,r3
+    muls r2,r1
+    muls r0,r0
+    muls r1,r1
+    lsrs r3,r2,#15
+    lsls r2,r2,#17
+    adds r0,r0,r2
+    adcs r1,r3
  // End: sqr 32
  // Result in r0 ,r1
-    sub r4,r5
-    sbc r6,r6
-    eor r4,r6
-    sub r4,r6
+    subs r4,r5
+    sbcs r6,r6
+    eors r4,r6
+    subs r4,r6
  // START: sqr 32
  // Input operand in r5
  // Result in r2 ,r3
  // Clobbers: r5, r6
     uxth r2,r5
-    lsr r3,r5,#16
-    .syntax unified
+    lsrs r3,r5,#16
     mov r5,r2
-    .syntax divided
-    mul r5,r3
-    mul r2,r2
-    mul r3,r3
-    lsr r6,r5,#15
-    lsl r5,r5,#17
-    add r2,r5
-    adc r3,r6
+    muls r5,r3
+    muls r2,r2
+    muls r3,r3
+    lsrs r6,r5,#15
+    lsls r5,r5,#17
+    adds r2,r2,r5
+    adcs r3,r6
  // End: sqr 32
  // Result in r2 ,r3
-    mov r6,#0
-    add r2,r1
-    adc r3,r6
+    movs r6,#0
+    adds r2,r2,r1
+    adcs r3,r6
  // START: sqr 32
  // Input operand in r4
  // Result in r4 ,r5
  // Clobbers: r1, r6
-    lsr r5,r4,#16
+    lsrs r5,r4,#16
     uxth r4,r4
-    .syntax unified
     mov r1,r4
-    .syntax divided
-    mul r1,r5
-    mul r4,r4
-    mul r5,r5
-    lsr r6,r1,#15
-    lsl r1,r1,#17
-    add r4,r1
-    adc r5,r6
+    muls r1,r5
+    muls r4,r4
+    muls r5,r5
+    lsrs r6,r1,#15
+    lsls r1,r1,#17
+    adds r4,r4,r1
+    adcs r5,r6
  // End: sqr 32
  // Result in r4 ,r5
-    .syntax unified
     mov r1,r2
-    .syntax divided
-    sub r1,r4
-    sbc r2,r5
-    .syntax unified
+    subs r1,r4
+    sbcs r2,r5
     mov r5,r3
-    .syntax divided
-    mov r6,#0
-    sbc r3,r6
-    add r1,r0
-    adc r2,r5
-    adc r3,r6
+    movs r6,#0
+    sbcs r3,r6
+    adds r1,r1,r0
+    adcs r2,r5
+    adcs r3,r6
  // END: sqr 64 Refined Karatsuba
  // Result in r0,r1,r2,r3
  // Leaves r6 zero.
-    .syntax unified
     mov r6,r10
     mov r10,r0
     mov r11,r1
     mov r12,r2
     mov r1,r3
-    .syntax divided
  // START: sqr 64 Refined Karatsuba
  // Input operands in r6,r7
  // Result in r2,r3,r4,r5
@@ -842,92 +707,78 @@ square256_asm:
  // Result in r2 ,r3
  // Clobbers: r4, r5
     uxth r2,r6
-    lsr r3,r6,#16
-    .syntax unified
+    lsrs r3,r6,#16
     mov r4,r2
-    .syntax divided
-    mul r4,r3
-    mul r2,r2
-    mul r3,r3
-    lsr r5,r4,#15
-    lsl r4,r4,#17
-    add r2,r4
-    adc r3,r5
+    muls r4,r3
+    muls r2,r2
+    muls r3,r3
+    lsrs r5,r4,#15
+    lsls r4,r4,#17
+    adds r2,r2,r4
+    adcs r3,r5
  // End: sqr 32
  // Result in r2 ,r3
-    sub r6,r7
-    sbc r4,r4
-    eor r6,r4
-    sub r6,r4
+    subs r6,r7
+    sbcs r4,r4
+    eors r6,r4
+    subs r6,r4
  // START: sqr 32
  // Input operand in r7
  // Result in r4 ,r5
  // Clobbers: r0, r7
     uxth r4,r7
-    lsr r5,r7,#16
-    .syntax unified
+    lsrs r5,r7,#16
     mov r0,r4
-    .syntax divided
-    mul r0,r5
-    mul r4,r4
-    mul r5,r5
-    lsr r7,r0,#15
-    lsl r0,r0,#17
-    add r4,r0
-    adc r5,r7
+    muls r0,r5
+    muls r4,r4
+    muls r5,r5
+    lsrs r7,r0,#15
+    lsls r0,r0,#17
+    adds r4,r4,r0
+    adcs r5,r7
  // End: sqr 32
  // Result in r4 ,r5
-    mov r7,#0
-    add r4,r3
-    adc r5,r7
+    movs r7,#0
+    adds r4,r4,r3
+    adcs r5,r7
  // START: sqr 32
  // Input operand in r6
  // Result in r7 ,r0
  // Clobbers: r6, r3
     uxth r7,r6
-    lsr r0,r6,#16
-    .syntax unified
+    lsrs r0,r6,#16
     mov r6,r7
-    .syntax divided
-    mul r6,r0
-    mul r7,r7
-    mul r0,r0
-    lsr r3,r6,#15
-    lsl r6,r6,#17
-    add r7,r6
-    adc r0,r3
+    muls r6,r0
+    muls r7,r7
+    muls r0,r0
+    lsrs r3,r6,#15
+    lsls r6,r6,#17
+    adds r7,r7,r6
+    adcs r0,r3
  // End: sqr 32
  // Result in r7 ,r0
-    .syntax unified
     mov r3,r4
-    .syntax divided
-    sub r3,r7
-    sbc r4,r0
-    .syntax unified
+    subs r3,r7
+    sbcs r4,r0
     mov r0,r5
-    .syntax divided
-    mov r6,#0
-    sbc r5,r6
-    add r3,r2
-    adc r4,r0
-    adc r5,r6
+    movs r6,#0
+    sbcs r5,r6
+    adds r3,r3,r2
+    adcs r4,r0
+    adcs r5,r6
  // END: sqr 64 Refined Karatsuba
  // Result in r2,r3,r4,r5
  // Leaves r6 zero.
-    .syntax unified
     mov r0,r12
-    .syntax divided
-    add r2,r0
-    adc r3,r1
-    adc r4,r6
-    adc r5,r6
-    .syntax unified
+    adds r2,r2,r0
+    adcs r3,r1
+    adcs r4,r6
+    adcs r5,r6
     mov r12,r2
     mov r2,r8
     mov r8,r3
     mov r3,r9
     mov r9,r4
-    .syntax divided
  // START: sqr 64 Refined Karatsuba
  // Input operands in r2,r3
  // Result in r6,r7,r0,r1
@@ -937,228 +788,172 @@ square256_asm:
  // Result in r6 ,r7
  // Clobbers: r0, r1
     uxth r6,r2
-    lsr r7,r2,#16
-    .syntax unified
+    lsrs r7,r2,#16
     mov r0,r6
-    .syntax divided
-    mul r0,r7
-    mul r6,r6
-    mul r7,r7
-    lsr r1,r0,#15
-    lsl r0,r0,#17
-    add r6,r0
-    adc r7,r1
+    muls r0,r7
+    muls r6,r6
+    muls r7,r7
+    lsrs r1,r0,#15
+    lsls r0,r0,#17
+    adds r6,r6,r0
+    adcs r7,r1
  // End: sqr 32
  // Result in r6 ,r7
-    sub r2,r3
-    sbc r4,r4
-    eor r2,r4
-    sub r2,r4
+    subs r2,r3
+    sbcs r4,r4
+    eors r2,r4
+    subs r2,r4
  // START: sqr 32
  // Input operand in r3
  // Result in r0 ,r1
  // Clobbers: r3, r4
     uxth r0,r3
-    lsr r1,r3,#16
-    .syntax unified
+    lsrs r1,r3,#16
     mov r3,r0
-    .syntax divided
-    mul r3,r1
-    mul r0,r0
-    mul r1,r1
-    lsr r4,r3,#15
-    lsl r3,r3,#17
-    add r0,r3
-    adc r1,r4
+    muls r3,r1
+    muls r0,r0
+    muls r1,r1
+    lsrs r4,r3,#15
+    lsls r3,r3,#17
+    adds r0,r0,r3
+    adcs r1,r4
  // End: sqr 32
  // Result in r0 ,r1
-    mov r4,#0
-    add r0,r7
-    adc r1,r4
+    movs r4,#0
+    adds r0,r0,r7
+    adcs r1,r4
  // START: sqr 32
  // Input operand in r2
  // Result in r3 ,r4
  // Clobbers: r2, r7
     uxth r3,r2
-    lsr r4,r2,#16
-    .syntax unified
+    lsrs r4,r2,#16
     mov r2,r3
-    .syntax divided
-    mul r2,r4
-    mul r3,r3
-    mul r4,r4
-    lsr r7,r2,#15
-    lsl r2,r2,#17
-    add r3,r2
-    adc r4,r7
+    muls r2,r4
+    muls r3,r3
+    muls r4,r4
+    lsrs r7,r2,#15
+    lsls r2,r2,#17
+    adds r3,r3,r2
+    adcs r4,r7
  // End: sqr 32
  // Result in r3 ,r4
-    .syntax unified
     mov r7,r0
-    .syntax divided
-    sub r7,r3
-    sbc r0,r4
-    .syntax unified
+    subs r7,r3
+    sbcs r0,r4
     mov r2,r1
-    .syntax divided
-    mov r4,#0
-    sbc r1,r4
-    add r7,r6
-    adc r0,r2
-    adc r1,r4
+    movs r4,#0
+    sbcs r1,r4
+    adds r7,r7,r6
+    adcs r0,r2
+    adcs r1,r4
  // END: sqr 64 Refined Karatsuba
  // Result in r6,r7,r0,r1
  // Returns r4 as zero.
-    .syntax unified
     mov r2,r12
     mov r3,r8
     mov r4,r9
-    .syntax divided
-    sub r2,r6
-    sbc r3,r7
-    .syntax unified
+    subs r2,r6
+    sbcs r3,r7
     mov r6,r4
     mov r7,r5
-    .syntax divided
-    sbc r4,r0
-    sbc r5,r1
-    mov r0,#0
-    sbc r6,r0
-    sbc r7,r0
-    .syntax unified
+    sbcs r4,r0
+    sbcs r5,r1
+    movs r0,#0
+    sbcs r6,r0
+    sbcs r7,r0
     mov r0,r10
-    .syntax divided
-    add r2,r0
-    .syntax unified
+    adds r2,r2,r0
     mov r1,r11
-    .syntax divided
-    adc r3,r1
-    .syntax unified
+    adcs r3,r1
     mov r0,r12
-    .syntax divided
-    adc r4,r0
-    .syntax unified
+    adcs r4,r0
     mov r0,r8
-    .syntax divided
-    adc r5,r0
-    mov r0,#0
-    adc r6,r0
-    adc r7,r0
-    .syntax unified
+    adcs r5,r0
+    movs r0,#0
+    adcs r6,r0
+    adcs r7,r0
     mov r0,r10
-    .syntax divided
  // END: sqr 128 Refined Karatsuba
  // Result in r0 ... r7
-    mvn r0,r0
-    mvn r1,r1
-    mvn r2,r2
-    mvn r3,r3
-    mvn r4,r4
-    mvn r5,r5
-    mvn r6,r6
-    mvn r7,r7
-    .syntax unified
+    mvns r0,r0
+    mvns r1,r1
+    mvns r2,r2
+    mvns r3,r3
+    mvns r4,r4
+    mvns r5,r5
+    mvns r6,r6
+    mvns r7,r7
     mov r8,r4
     mov r9,r5
     mov r10,r6
     mov r11,r7
-    .syntax divided
-    mov r4,#143
-    asr r4,r4,#1
+    movs r4,#143
+    asrs r4,r4,#1
     pop {r4,r5,r6,r7}
-    adc r0,r4
-    adc r1,r5
-    adc r2,r6
-    adc r3,r7
-    .syntax unified
+    adcs r0,r4
+    adcs r1,r5
+    adcs r2,r6
+    adcs r3,r7
     mov r12,r4
-    .syntax divided
-    mov r4,#16
+    movs r4,#16
     add r4,r14
     stm r4!,{r0,r1,r2,r3}
-    .syntax unified
     mov r4,r12
     mov r0,r8
-    .syntax divided
-    adc r0,r4
-    .syntax unified
+    adcs r0,r4
     mov r8,r0
     mov r1,r9
-    .syntax divided
-    adc r1,r5
-    .syntax unified
+    adcs r1,r5
     mov r9,r1
     mov r2,r10
-    .syntax divided
-    adc r2,r6
-    .syntax unified
+    adcs r2,r6
     mov r10,r2
     mov r3,r11
-    .syntax divided
-    adc r3,r7
-    .syntax unified
+    adcs r3,r7
     mov r11,r3
-    .syntax divided
-    mov r0,#0
-    adc r0,r0
-    .syntax unified
+    movs r0,#0
+    adcs r0,r0
     mov r12,r0
     mov r0,r14
-    .syntax divided
     ldm r0,{r0,r1,r2,r3,r4,r5,r6,r7}
-    add r0,r4
-    adc r1,r5
-    adc r2,r6
-    adc r3,r7
-    mov r4,#16
+    adds r0,r0,r4
+    adcs r1,r5
+    adcs r2,r6
+    adcs r3,r7
+    movs r4,#16
     add r4,r14
     stm r4!,{r0,r1,r2,r3}
-    .syntax unified
     mov r14,r4
     mov r0,r13
-    .syntax divided
     ldm r0!,{r4,r5,r6,r7}
-    .syntax unified
     mov r1,r8
-    .syntax divided
-    adc r4,r1
-    .syntax unified
+    adcs r4,r1
     mov r1,r9
-    .syntax divided
-    adc r5,r1
-    .syntax unified
+    adcs r5,r1
     mov r1,r10
-    .syntax divided
-    adc r6,r1
-    .syntax unified
+    adcs r6,r1
     mov r1,r11
-    .syntax divided
-    adc r7,r1
-    .syntax unified
+    adcs r7,r1
     mov r0,r14
-    .syntax divided
     stm r0!,{r4,r5,r6,r7}
     pop {r4,r5,r6,r7}
-    .syntax unified
     mov r1,r12
-    .syntax divided
-    mov r2,#0
-    mvn r2,r2
-    adc r1,r2
-    asr r2,r1,#4
-    add r4,r1
-    adc r5,r2
-    adc r6,r2
-    adc r7,r2
+    movs r2,#0
+    mvns r2,r2
+    adcs r1,r2
+    asrs r2,r1,#4
+    adds r4,r4,r1
+    adcs r5,r2
+    adcs r6,r2
+    adcs r7,r2
     stm r0!,{r4,r5,r6,r7}
     pop {r3,r4,r5,r6,r7}
-    .syntax unified
     mov r8,r3
     mov r9,r4
     mov r10,r5
     mov r11,r6
     mov r12,r7
-    .syntax divided
     pop {r0,r4,r5,r6,r7,r15}
 //Cycle Count ASM-Version of 256 sqr (Refined Karatsuba) (Cortex M0): 793 (697 instructions).
 	.size	square256_asm, .-square256_asm
diff --git a/third_party/zephyr/LICENSE b/third_party/zephyr/LICENSE
new file mode 100644
index 0000000000..8f71f43fee
--- /dev/null
+++ b/third_party/zephyr/LICENSE
@@ -0,0 +1,202 @@
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diff --git a/third_party/zephyr/METADATA b/third_party/zephyr/METADATA
new file mode 100644
index 0000000000..36580c0784
--- /dev/null
+++ b/third_party/zephyr/METADATA
@@ -0,0 +1,13 @@
+name: "Zephyr RTOS atomic functions"
+description:
+    "atomic functions for bit manipulating"
+
+third_party {
+  url {
+    type: GIT
+    value: "https://github.com/zephyrproject-rtos/zephyr"
+  }
+  version: "8b4a3e23287f88dc270e1fe9400acd7be2963db2"
+  last_upgrade_date { year: 2022 month: 3 day: 4 }
+  license_type: NOTICE
+}
diff --git a/third_party/zephyr/atomic.h b/third_party/zephyr/atomic.h
new file mode 100644
index 0000000000..7b08018723
--- /dev/null
+++ b/third_party/zephyr/atomic.h
@@ -0,0 +1,225 @@
+/*
+ * Copyright (c) 1997-2015, Wind River Systems, Inc.
+ * Copyright (c) 2021 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_SYS_ATOMIC_H_
+#define ZEPHYR_INCLUDE_SYS_ATOMIC_H_
+
+/*
+ * EC adaptation
+ * Remove unnecessary includes.
+ */
+#include <stdbool.h>
+#include <stddef.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * EC adaptation
+ * Remove redefinition of atomic types.
+ */
+
+/*
+ * EC adaptation
+ * Remove including basic atomic operations.
+ */
+
+
+/* Portable higher-level utilities: */
+
+/**
+ * @defgroup atomic_apis Atomic Services APIs
+ * @ingroup kernel_apis
+ * @{
+ */
+
+/**
+ * @brief Initialize an atomic variable.
+ *
+ * This macro can be used to initialize an atomic variable. For example,
+ * @code atomic_t my_var = ATOMIC_INIT(75); @endcode
+ *
+ * @param i Value to assign to atomic variable.
+ */
+#define ATOMIC_INIT(i) (i)
+
+/**
+ * @brief Initialize an atomic pointer variable.
+ *
+ * This macro can be used to initialize an atomic pointer variable. For
+ * example,
+ * @code atomic_ptr_t my_ptr = ATOMIC_PTR_INIT(&data); @endcode
+ *
+ * @param p Pointer value to assign to atomic pointer variable.
+ */
+#define ATOMIC_PTR_INIT(p) (p)
+
+/**
+ * @cond INTERNAL_HIDDEN
+ */
+
+#define ATOMIC_BITS (sizeof(atomic_val_t) * 8)
+#define ATOMIC_MASK(bit) BIT((unsigned long)(bit) & (ATOMIC_BITS - 1U))
+#define ATOMIC_ELEM(addr, bit) ((addr) + ((bit) / ATOMIC_BITS))
+
+/**
+ * INTERNAL_HIDDEN @endcond
+ */
+
+/**
+ * @brief This macro computes the number of atomic variables necessary to
+ * represent a bitmap with @a num_bits.
+ *
+ * @param num_bits Number of bits.
+ */
+#define ATOMIC_BITMAP_SIZE(num_bits) (1 + ((num_bits) - 1) / ATOMIC_BITS)
+
+/**
+ * @brief Define an array of atomic variables.
+ *
+ * This macro defines an array of atomic variables containing at least
+ * @a num_bits bits.
+ *
+ * @note
+ * If used from file scope, the bits of the array are initialized to zero;
+ * if used from within a function, the bits are left uninitialized.
+ *
+ * @cond INTERNAL_HIDDEN
+ * @note
+ * This macro should be replicated in the PREDEFINED field of the documentation
+ * Doxyfile.
+ * @endcond
+ *
+ * @param name Name of array of atomic variables.
+ * @param num_bits Number of bits needed.
+ */
+#define ATOMIC_DEFINE(name, num_bits) \
+	atomic_t name[ATOMIC_BITMAP_SIZE(num_bits)]
+
+/**
+ * @brief Atomically test a bit.
+ *
+ * This routine tests whether bit number @a bit of @a target is set or not.
+ * The target may be a single atomic variable or an array of them.
+ *
+ * @param target Address of atomic variable or array.
+ * @param bit Bit number (starting from 0).
+ *
+ * @return true if the bit was set, false if it wasn't.
+ */
+static inline bool atomic_test_bit(const atomic_t *target, int bit)
+{
+	atomic_val_t val = atomic_get(ATOMIC_ELEM(target, bit));
+
+	return (1 & (val >> (bit & (ATOMIC_BITS - 1)))) != 0;
+}
+
+/**
+ * @brief Atomically test and clear a bit.
+ *
+ * Atomically clear bit number @a bit of @a target and return its old value.
+ * The target may be a single atomic variable or an array of them.
+ *
+ * @param target Address of atomic variable or array.
+ * @param bit Bit number (starting from 0).
+ *
+ * @return true if the bit was set, false if it wasn't.
+ */
+static inline bool atomic_test_and_clear_bit(atomic_t *target, int bit)
+{
+	atomic_val_t mask = ATOMIC_MASK(bit);
+	atomic_val_t old;
+
+	old = atomic_and(ATOMIC_ELEM(target, bit), ~mask);
+
+	return (old & mask) != 0;
+}
+
+/**
+ * @brief Atomically set a bit.
+ *
+ * Atomically set bit number @a bit of @a target and return its old value.
+ * The target may be a single atomic variable or an array of them.
+ *
+ * @param target Address of atomic variable or array.
+ * @param bit Bit number (starting from 0).
+ *
+ * @return true if the bit was set, false if it wasn't.
+ */
+static inline bool atomic_test_and_set_bit(atomic_t *target, int bit)
+{
+	atomic_val_t mask = ATOMIC_MASK(bit);
+	atomic_val_t old;
+
+	old = atomic_or(ATOMIC_ELEM(target, bit), mask);
+
+	return (old & mask) != 0;
+}
+
+/**
+ * @brief Atomically clear a bit.
+ *
+ * Atomically clear bit number @a bit of @a target.
+ * The target may be a single atomic variable or an array of them.
+ *
+ * @param target Address of atomic variable or array.
+ * @param bit Bit number (starting from 0).
+ */
+static inline void atomic_clear_bit(atomic_t *target, int bit)
+{
+	atomic_val_t mask = ATOMIC_MASK(bit);
+
+	(void)atomic_and(ATOMIC_ELEM(target, bit), ~mask);
+}
+
+/**
+ * @brief Atomically set a bit.
+ *
+ * Atomically set bit number @a bit of @a target.
+ * The target may be a single atomic variable or an array of them.
+ *
+ * @param target Address of atomic variable or array.
+ * @param bit Bit number (starting from 0).
+ */
+static inline void atomic_set_bit(atomic_t *target, int bit)
+{
+	atomic_val_t mask = ATOMIC_MASK(bit);
+
+	(void)atomic_or(ATOMIC_ELEM(target, bit), mask);
+}
+
+/**
+ * @brief Atomically set a bit to a given value.
+ *
+ * Atomically set bit number @a bit of @a target to value @a val.
+ * The target may be a single atomic variable or an array of them.
+ *
+ * @param target Address of atomic variable or array.
+ * @param bit Bit number (starting from 0).
+ * @param val true for 1, false for 0.
+ */
+static inline void atomic_set_bit_to(atomic_t *target, int bit, bool val)
+{
+	atomic_val_t mask = ATOMIC_MASK(bit);
+
+	if (val) {
+		(void)atomic_or(ATOMIC_ELEM(target, bit), mask);
+	} else {
+		(void)atomic_and(ATOMIC_ELEM(target, bit), ~mask);
+	}
+}
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /* ZEPHYR_INCLUDE_SYS_ATOMIC_H_ */
diff --git a/twister b/twister
new file mode 120000
index 0000000000..7b6dd74c5c
--- /dev/null
+++ b/twister
@@ -0,0 +1 @@
+util/twister_launcher.py
\ No newline at end of file
diff --git a/unblocked_terms.txt b/unblocked_terms.txt
index edfa587f9b..2ad0dc0a56 100644
--- a/unblocked_terms.txt
+++ b/unblocked_terms.txt
@@ -1,2 +1,5 @@
 master
-slave
\ No newline at end of file
+slave
+# The Zephyr RTOS uses "native_posix" as a build target, so unblock
+# just that specific usage.
+native_posix
diff --git a/util/battery_temp b/util/battery_temp
index c69e3d4778..01f4002b99 100755
--- a/util/battery_temp
+++ b/util/battery_temp
@@ -1,5 +1,5 @@
 #!/bin/bash
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/util/bin2h.sh b/util/bin2h.sh
index 1507bc4004..276d89f0cf 100755
--- a/util/bin2h.sh
+++ b/util/bin2h.sh
@@ -1,6 +1,6 @@
 #!/bin/bash
 #
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/util/build.mk b/util/build.mk
index f21a71b39f..1b692ccb9f 100644
--- a/util/build.mk
+++ b/util/build.mk
@@ -1,60 +1,58 @@
 # -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
+# Copyright 2014 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
 # Host tools build
 #
 
-host-util-bin=ectool lbplay stm32mon ec_sb_firmware_update lbcc \
-	ec_parse_panicinfo cbi-util iteflash
-build-util-bin=ec_uartd
-build-util-art+=util/export_taskinfo.so
-ifeq ($(CHIP),npcx)
-build-util-bin+=ecst
-endif
-host-util-bin+=uartupdatetool
+# See Makefile for description.
+host-util-bin-y += cbi-util iteflash
+host-util-bin-cxx-y += ectool ec_parse_panicinfo lbplay stm32mon lbcc
+build-util-art-y += util/export_taskinfo.so
+
+build-util-bin-$(CHIP_NPCX) += ecst
+host-util-bin-cxx-$(BOARD_NOCTURNE_FP) += ectool_servo
+
+host-util-bin-cxx-y += uartupdatetool
 uartupdatetool-objs=uut/main.o uut/cmd.o uut/opr.o uut/l_com_port.o \
 	uut/lib_crc.o
 $(out)/util/uartupdatetool: HOST_CFLAGS+=-Iutil/
-# Build on a limited subset of boards to save build time
-ifeq ($(BOARD),nocturne_fp)
-build-util-bin+=ectool_servo
-endif
 
 # If the util/ directory in the private repo is symlinked into util/private,
 # we want to build host-side tools from it, too.
 ifneq ("$(wildcard util/private/build.mk)","")
 include util/private/build.mk
 endif
+-include private/util_flags.mk
 
 comm-objs=$(util-lock-objs:%=lock/%) comm-host.o comm-dev.o
-comm-objs+=comm-lpc.o comm-i2c.o misc_util.o
+comm-objs+=comm-lpc.o comm-i2c.o misc_util.o comm-usb.o
 
 iteflash-objs = iteflash.o usb_if.o
-ectool-objs=ectool.o ectool_keyscan.o ec_flash.o ec_panicinfo.o $(comm-objs)
+ectool-objs=ectool.o ectool_keyscan.o ec_flash.o $(comm-objs)
+ectool-objs+=ectool_i2c.o
+ectool-objs+=../common/crc.o
 ectool_servo-objs=$(ectool-objs) comm-servo-spi.o
-ec_sb_firmware_update-objs=ec_sb_firmware_update.o $(comm-objs) misc_util.o
-ec_sb_firmware_update-objs+=powerd_lock.o
 lbplay-objs=lbplay.o $(comm-objs)
 
-util/ectool.c: $(out)/ec_version.h
+util/ectool.cc: $(out)/ec_version.h
 
-ec_parse_panicinfo-objs=ec_parse_panicinfo.o ec_panicinfo.o
+ec_parse_panicinfo-objs=ec_parse_panicinfo.o
 
 # USB type-C Vendor Information File generation
 ifeq ($(CONFIG_USB_POWER_DELIVERY),y)
-build-util-bin+=genvif
-build-util-art+=$(BOARD)_vif.txt
+build-util-bin-y+=genvif
+build-util-art-y+=$(BOARD)_vif.xml
 
 # usb_pd_policy.c can be in baseboard, or board, or both.
-genvif-pd-srcs=$(sort $(wildcard $(BASEDIR)/usb_pd_policy.c \
-			board/$(BOARD)/usb_pd_policy.c))
+genvif-pd-srcs=$(sort $(wildcard $(BASEDIR)/usb_pd_pdo.c \
+			board/$(BOARD)/usb_pd_pdo.c))
 genvif-pd-objs=$(genvif-pd-srcs:%.c=$(out)/util/%.o)
-genvif-pd-objs += $(out)/common/usb_common.o
+genvif-pd-objs += $(out)/common/usb_common.o $(out)/common/usb_pd_pdo.o
 deps-$(CONFIG_USB_POWER_DELIVERY) += $(genvif-pd-objs:%.o=%.o.d)
 
-$(out)/util/genvif: $(genvif-pd-objs) board/$(BOARD)/board.h \
+$(out)/util/genvif: $(genvif-pd-objs) util/genvif.h board/$(BOARD)/board.h \
 			include/usb_pd.h include/usb_pd_tcpm.h
 $(out)/util/genvif: BUILD_LDFLAGS+=$(genvif-pd-objs) -flto
 
@@ -64,20 +62,26 @@ STANDALONE_FLAGS=-ffreestanding -fno-builtin -nostdinc \
 $(out)/util/%/usb_pd_policy.o: %/usb_pd_policy.c
 	-@ mkdir -p $(@D)
 	$(call quiet,c_to_vif,BUILDCC)
+$(out)/util/%/usb_pd_pdo.o: %/usb_pd_pdo.c
+	-@ mkdir -p $(@D)
+	$(call quiet,c_to_vif,BUILDCC)
 $(out)/common/usb_common.o: common/usb_common.c
 	-@ mkdir -p $(@D)
 	$(call quiet,c_to_vif,BUILDCC)
+$(out)/common/usb_pd_pdo.o: common/usb_pd_pdo.c
+	-@ mkdir -p $(@D)
+	$(call quiet,c_to_vif,BUILDCC)
 endif # CONFIG_USB_POWER_DELIVERY
 
 ifneq ($(CONFIG_BOOTBLOCK),)
-build-util-bin += gen_emmc_transfer_data
+build-util-bin-y += gen_emmc_transfer_data
 
 # Bootblock is only packed in RO image.
 $(out)/util/gen_emmc_transfer_data: BUILD_LDFLAGS += -DSECTION_IS_RO=$(EMPTY)
 endif # CONFIG_BOOTBLOCK
 
 ifneq ($(CONFIG_IPI),)
-build-util-bin += gen_ipi_table
+build-util-bin-y += gen_ipi_table
 
 $(out)/util/gen_ipi_table: board/$(BOARD)/board.h
 $(out)/ipi_table_gen.inc: $(out)/util/gen_ipi_table
@@ -85,16 +89,16 @@ $(out)/ipi_table_gen.inc: $(out)/util/gen_ipi_table
 endif
 
 ifneq ($(CONFIG_TOUCHPAD_HASH_FW),)
-build-util-bin += gen_touchpad_hash
+build-util-bin-y += gen_touchpad_hash
 
 # Assume RW section (touchpad FW must be identical for both RO+RW)
 $(out)/util/gen_touchpad_hash: BUILD_LDFLAGS += -DSECTION_IS_RW=$(EMPTY)
 
-OPENSSL_CFLAGS := $(shell $(PKG_CONFIG) --libs openssl)
-OPENSSL_LDFLAGS := $(shell $(PKG_CONFIG) --libs openssl)
+BUILD_OPENSSL_CFLAGS := $(shell $(BUILD_PKG_CONFIG) --cflags openssl)
+BUILD_OPENSSL_LDFLAGS := $(shell $(BUILD_PKG_CONFIG) --libs openssl)
 
-$(out)/util/gen_touchpad_hash: BUILD_CFLAGS += $(OPENSSL_CFLAGS)
-$(out)/util/gen_touchpad_hash: BUILD_LDFLAGS += $(OPENSSL_LDFLAGS)
+$(out)/util/gen_touchpad_hash: BUILD_CFLAGS += $(BUILD_OPENSSL_CFLAGS)
+$(out)/util/gen_touchpad_hash: BUILD_LDFLAGS += $(BUILD_OPENSSL_LDFLAGS)
 
 deps-y += $(out)/util/gen_touchpad_hash.d
 endif # CONFIG_TOUCHPAD_VIRTUAL_OFF
diff --git a/util/build_with_clang.py b/util/build_with_clang.py
new file mode 100755
index 0000000000..48af44472d
--- /dev/null
+++ b/util/build_with_clang.py
@@ -0,0 +1,424 @@
+#!/usr/bin/env python3
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Build firmware with clang instead of gcc."""
+import argparse
+import concurrent
+from concurrent.futures import ThreadPoolExecutor
+import logging
+import multiprocessing
+import os
+import shutil
+import subprocess
+import sys
+import typing
+
+
+# Add to this list as compilation errors are fixed for boards.
+BOARDS_THAT_COMPILE_SUCCESSFULLY_WITH_CLANG = [
+    # Fingerprint boards
+    "dartmonkey",
+    "bloonchipper",
+    "helipilot",
+    "nami_fp",
+    "nucleo-dartmonkey",
+    "nucleo-f412zg",
+    "nucleo-h743zi",
+    # Boards that use CHIP:=stm32 and *not* CHIP_FAMILY:=stm32f0
+    # git grep  --name-only 'CHIP:=stm32' | xargs grep -L 'CHIP_FAMILY:=stm32f0' | sed 's#board/\(.*\)/build.mk#"\1",#'
+    "baklava",
+    "bellis",
+    "discovery",
+    "gingerbread",
+    "hatch_fp",
+    "hyperdebug",
+    "munna",
+    "nocturne_fp",
+    "nucleo-f411re",
+    "nucleo-g431rb",
+    "panqueque",
+    "polyberry",
+    "quiche",
+    "stm32f446e-eval",
+    "stm32l476g-eval",
+    "sweetberry",
+    # Boards that use CHIP:=stm32 *and* CHIP_FAMILY:=stm32f0
+    # git grep  --name-only 'CHIP:=stm32' | xargs grep -L 'CHIP_FAMILY:=stm32f0' | sed 's#board/\(.*\)/build.mk#"\1",#'
+    "bland",
+    "burnet",
+    "c2d2",
+    "cerise",
+    "coffeecake",
+    "damu",
+    "dingdong",
+    "discovery-stm32f072",
+    "don",
+    "duck",
+    "eel",
+    "elm",
+    "fennel",
+    "fluffy",
+    "fusb307bgevb",
+    "gelatin",
+    "hammer",
+    "hoho",
+    "jacuzzi",
+    "jewel",
+    "juniper",
+    "kakadu",
+    "kappa",
+    "katsu",
+    "kodama",
+    "krane",
+    "kukui",
+    "magnemite",
+    "makomo",
+    "masterball",
+    "minimuffin",
+    "moonball",
+    "nucleo-f072rb",
+    "oak",
+    "pdeval-stm32f072",
+    "plankton",
+    "prism",
+    "rainier",
+    "scarlet",
+    "servo_micro",
+    "servo_v4",
+    "servo_v4p1",
+    "staff",
+    "star",
+    "stern",
+    "tigertail",
+    "twinkie",
+    "wand",
+    "willow",
+    "zed",
+    "zinger",
+    # Boards that use CHIP:=mchp
+    # git grep --name-only 'CHIP:=mchp' | sed 's#board/\(.*\)/build.mk#"\1",#'
+    "adlrvpp_mchp1521",
+    "adlrvpp_mchp1727",
+    "mchpevb1",
+    "reef_mchp",
+    # Boards that use CHIP:=max32660
+    # git grep --name-only 'CHIP:=max32660' | sed 's#board/\(.*\)/build.mk#"\1",#'
+    "max32660-eval",
+    # Boards that use CHIP:=npcx
+    # git grep --name-only 'CHIP:=npcx' | sed 's#^board/\(.*\)/build.mk#"\1",#'
+    "adlrvpp_npcx",
+    "agah",
+    "akemi",
+    "aleena",
+    "ambassador",
+    "anahera",
+    "atlas",
+    "aurash",
+    "banshee",
+    "berknip",
+    "bloog",
+    "bobba",
+    "boldar",
+    "brask",
+    "brya",
+    "bugzzy",
+    "cappy2",
+    "careena",
+    "casta",
+    "chronicler",
+    "coachz",
+    "collis",
+    "constitution",
+    "copano",
+    "coral",
+    "corori",
+    "corori2",
+    "cret",
+    "crota",
+    "dalboz",
+    "delbin",
+    "dewatt",
+    "dirinboz",
+    "dood",
+    "dooly",
+    "dratini",
+    "driblee",
+    "drobit",
+    "drobit_ecmodeentry",
+    "eldrid",
+    "elemi",
+    "endeavour",
+    "eve",
+    "ezkinil",
+    "felwinter",
+    "fizz",
+    "fleex",
+    "foob",
+    "gaelin",
+    "garg",
+    "gelarshie",
+    "genesis",
+    "gimble",
+    "gladios",
+    "grunt",
+    "gumboz",
+    "guybrush",
+    "hades",
+    "hatch",
+    "helios",
+    "herobrine",
+    "homestar",
+    "jinlon",
+    "kano",
+    "karma",
+    "kindred",
+    "kingoftown",
+    "kinox",
+    "kohaku",
+    "kuldax",
+    "lalala",
+    "lazor",
+    "liara",
+    "lick",
+    "lindar",
+    "lisbon",
+    "lux",
+    "madoo",
+    "magolor",
+    "marasov",
+    "marzipan",
+    "meep",
+    "metaknight",
+    "mithrax",
+    "moli",
+    "moonbuggy",
+    "morphius",
+    "mrbland",
+    "mushu",
+    "nami",
+    "nautilus",
+    "nightfury",
+    "nipperkin",
+    "nocturne",
+    "npcx7_evb",
+    "npcx9_evb",
+    "npcx_evb",
+    "npcx_evb_arm",
+    "nuwani",
+    "omnigul",
+    "osiris",
+    "palkia",
+    "pazquel",
+    "phaser",
+    "pompom",
+    "poppy",
+    "primus",
+    "puff",
+    "quackingstick",
+    "rammus",
+    "redrix",
+    "reef",
+    "sasuke",
+    "scout",
+    "shuboz",
+    "soraka",
+    "stryke",
+    "taeko",
+    "taniks",
+    "terrador",
+    "treeya",
+    "trembyle",
+    "trogdor",
+    "vell",
+    "vilboz",
+    "voema",
+    "volet",
+    "volmar",
+    "volteer",
+    "volteer_npcx797fc",
+    "voxel",
+    "voxel_ecmodeentry",
+    "voxel_npcx797fc",
+    "waddledoo",
+    "waddledoo2",
+    "whiskers",
+    "woomax",
+    "wormdingler",
+    "yorp",
+    # CHIP=mt_scp *and* CHIP_VARIANT=mt818x
+    # git grep --name-only 'CHIP:=mt_scp' | xargs grep -L 'CHIP_VARIANT:=mt818' | sed 's#board/\(.*\)/build.mk#"\1",#'
+    "corsola_scp",
+    "kukui_scp",
+    # Boards that use CORE:=minute-ia
+    "adl_ish_lite",
+    "arcada_ish",
+    "drallion_ish",
+    "tglrvp_ish",
+    "volteer_ish",
+]
+
+NDS32_BOARDS = [
+    "adlrvpm_ite",
+    "adlrvpp_ite",
+    "ampton",
+    "beadrix",
+    "beetley",
+    "blipper",
+    "boten",
+    "boxy",
+    "dibbi",
+    "drawcia",
+    "galtic",
+    "gooey",
+    "haboki",
+    "it83xx_evb",
+    "kracko",
+    "lantis",
+    "pirika",
+    "reef_it8320",
+    "sasukette",
+    "shotzo",
+    "storo",
+    "taranza",
+    "waddledee",
+    "wheelie",
+]
+
+RISCV_BOARDS = [
+    "asurada",
+    "asurada_scp",
+    "cherry",
+    "cherry_scp",
+    "cozmo",
+    "dojo",
+    "drawcia_riscv",
+    "goroh",
+    "hayato",
+    "icarus",
+    "it8xxx2_evb",
+    "it8xxx2_pdevb",
+    "pico",
+    "spherion",
+    "tomato",
+]
+
+BOARDS_THAT_FAIL_WITH_CLANG = [
+    # Boards that use CHIP:=stm32 *and* CHIP_FAMILY:=stm32f0
+    "chocodile_vpdmcu",  # compilation error: b/254710459
+]
+
+# TODO(b/201311714): NDS32 is not supported by LLVM.
+BOARDS_THAT_FAIL_WITH_CLANG += NDS32_BOARDS
+# TODO(b/201310017): RISC-V is not supported in our LLVM toolchain.
+BOARDS_THAT_FAIL_WITH_CLANG += RISCV_BOARDS
+
+
+def build(board_name: str) -> None:
+    """Build with clang for specified board."""
+    logging.debug('Building board: "%s"', board_name)
+
+    cmd = [
+        "make",
+        "BOARD=" + board_name,
+        "-j",
+    ]
+
+    logging.debug('Running command: "%s"', " ".join(cmd))
+    subprocess.run(cmd, env=dict(os.environ, CC="clang"), check=True)
+
+
+def get_all_boards() -> typing.List[str]:
+    cmd = [
+        "make",
+        "print-boards",
+    ]
+
+    logging.debug('Running command: "%s"', " ".join(cmd))
+    ret = subprocess.run(cmd, stdout=subprocess.PIPE, check=True)
+    all_boards = ret.stdout.decode("utf-8").splitlines()
+    return all_boards
+
+
+def check_boards() -> None:
+    all_boards = get_all_boards()
+    diff = set(all_boards) ^ set(
+        BOARDS_THAT_COMPILE_SUCCESSFULLY_WITH_CLANG
+        + BOARDS_THAT_FAIL_WITH_CLANG
+    )
+    if len(diff) > 0:
+        print(
+            "The following boards are missing and must be added to "
+            "BOARDS_THAT_COMPILE_SUCCESSFULLY_WITH_CLANG or "
+            "BOARDS_THAT_FAIL_WITH_CLANG:"
+        )
+        for i in sorted(diff):
+            print(i)
+        sys.exit(1)
+
+
+def main() -> int:
+    parser = argparse.ArgumentParser()
+
+    log_level_choices = ["DEBUG", "INFO", "WARNING", "ERROR", "CRITICAL"]
+    parser.add_argument(
+        "--log_level", "-l", choices=log_level_choices, default="DEBUG"
+    )
+
+    parser.add_argument(
+        "--num_threads", "-j", type=int, default=multiprocessing.cpu_count()
+    )
+
+    group = parser.add_mutually_exclusive_group(required=False)
+    group.add_argument(
+        "--clean",
+        action="store_true",
+        help="Remove build directory before compiling",
+    )
+    group.add_argument(
+        "--no-clean",
+        dest="clean",
+        action="store_false",
+        help="Do not remove build directory before compiling",
+    )
+    parser.set_defaults(clean=True)
+
+    args = parser.parse_args()
+    logging.basicConfig(level=args.log_level)
+
+    if args.clean:
+        logging.debug("Removing build directory")
+        shutil.rmtree("./build", ignore_errors=True)
+
+    check_boards()
+
+    logging.debug("Building with %d threads", args.num_threads)
+
+    failed_boards = []
+    with ThreadPoolExecutor(max_workers=args.num_threads) as executor:
+        future_to_board = {
+            executor.submit(build, board): board
+            for board in BOARDS_THAT_COMPILE_SUCCESSFULLY_WITH_CLANG
+        }
+        for future in concurrent.futures.as_completed(future_to_board):
+            board = future_to_board[future]
+            try:
+                future.result()
+            except Exception:
+                failed_boards.append(board)
+
+    if len(failed_boards) > 0:
+        failed_boards.sort()
+        logging.error(
+            "The following boards failed to compile:\n%s",
+            "\n".join(failed_boards),
+        )
+        return 1
+
+    logging.info("All boards compiled successfully!")
+    return 0
+
+
+if __name__ == "__main__":
+    sys.exit(main())
diff --git a/util/cbi-util.c b/util/cbi-util.c
index 3626b52859..b5bf74669c 100644
--- a/util/cbi-util.c
+++ b/util/cbi-util.c
@@ -1,29 +1,30 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Cros Board Info utility
  */
 
-#include <compile_time_macros.h>
+#include "crc8.h"
+#include "cros_board_info.h"
+
 #include <errno.h>
-#include <dirent.h>
-#include <getopt.h>
 #include <limits.h>
 #include <stdarg.h>
 #include <stdint.h>
 #include <stdio.h>
-#include <string.h>
 #include <stdlib.h>
-#include <unistd.h>
+#include <string.h>
 
-#include "cros_board_info.h"
-#include "crc8.h"
+#include <compile_time_macros.h>
+#include <dirent.h>
+#include <getopt.h>
+#include <unistd.h>
 
-#define ARGS_MASK_BOARD_VERSION		BIT(0)
-#define ARGS_MASK_FILENAME		BIT(1)
-#define ARGS_MASK_SIZE			BIT(2)
-#define ARGS_MASK_SKU_ID		BIT(3)
+#define ARGS_MASK_BOARD_VERSION BIT(0)
+#define ARGS_MASK_FILENAME BIT(1)
+#define ARGS_MASK_SIZE BIT(2)
+#define ARGS_MASK_SKU_ID BIT(3)
 
 /* TODO: Set it by macro */
 const char cmd_name[] = "cbi-util";
@@ -40,6 +41,8 @@ enum {
 	OPT_FW_CONFIG,
 	OPT_PCB_SUPPLIER,
 	OPT_SSFC,
+	OPT_REWORK_ID,
+	OPT_FACTORY_CALIBRATION_DATA,
 	OPT_SIZE,
 	OPT_ERASE_BYTE,
 	OPT_SHOW_ALL,
@@ -47,26 +50,26 @@ enum {
 };
 
 static const struct option opts_create[] = {
-	{"file", 1, 0, OPT_FILENAME},
-	{"board_version", 1, 0, OPT_BOARD_VERSION},
-	{"oem_id", 1, 0, OPT_OEM_ID},
-	{"sku_id", 1, 0, OPT_SKU_ID},
-	{"dram_part_num", 1, 0, OPT_DRAM_PART_NUM},
-	{"oem_name", 1, 0, OPT_OEM_NAME},
-	{"model_id", 1, 0, OPT_MODEL_ID},
-	{"fw_config", 1, 0, OPT_FW_CONFIG},
-	{"pcb_supplier", 1, 0, OPT_PCB_SUPPLIER},
-	{"ssfc", 1, 0, OPT_SSFC},
-	{"size", 1, 0, OPT_SIZE},
-	{"erase_byte", 1, 0, OPT_ERASE_BYTE},
-	{NULL, 0, 0, 0}
+	{ "file", 1, 0, OPT_FILENAME },
+	{ "board_version", 1, 0, OPT_BOARD_VERSION },
+	{ "oem_id", 1, 0, OPT_OEM_ID },
+	{ "sku_id", 1, 0, OPT_SKU_ID },
+	{ "dram_part_num", 1, 0, OPT_DRAM_PART_NUM },
+	{ "oem_name", 1, 0, OPT_OEM_NAME },
+	{ "model_id", 1, 0, OPT_MODEL_ID },
+	{ "fw_config", 1, 0, OPT_FW_CONFIG },
+	{ "pcb_supplier", 1, 0, OPT_PCB_SUPPLIER },
+	{ "ssfc", 1, 0, OPT_SSFC },
+	{ "rework_id", 1, 0, OPT_REWORK_ID },
+	{ "factory_calibration_data", 1, 0, OPT_FACTORY_CALIBRATION_DATA },
+	{ "size", 1, 0, OPT_SIZE },
+	{ "erase_byte", 1, 0, OPT_ERASE_BYTE },
+	{ NULL, 0, 0, 0 }
 };
 
-static const struct option opts_show[] = {
-	{"file", 1, 0, OPT_FILENAME},
-	{"all", 0, 0, OPT_SHOW_ALL},
-	{NULL, 0, 0, 0}
-};
+static const struct option opts_show[] = { { "file", 1, 0, OPT_FILENAME },
+					   { "all", 0, 0, OPT_SHOW_ALL },
+					   { NULL, 0, 0, 0 } };
 
 static const char *field_name[] = {
 	/* Same order as enum cbi_data_tag */
@@ -79,6 +82,34 @@ static const char *field_name[] = {
 	"FW_CONFIG",
 	"PCB_SUPPLIER",
 	"SSFC",
+	"REWORK_ID",
+	"FACTORY_CALIBRATION_DATA",
+	"BATT_SHIP_MODE_FLAGS",
+	"BATT_SHIP_MODE_REG_ADDR",
+	"BATT_SHIP_MODE_REG_DATA",
+	"BATT_SLEEP_MODE_FLAGS",
+	"BATT_SLEEP_MODE_REG_ADDR",
+	"BATT_SLEEP_MODE_REG_DATA",
+	"BATT_FET_FLAGS",
+	"BATT_FET_REG_ADDR",
+	"BATT_FET_REG_MASK",
+	"BATT_FET_DISCONNECT_VAL",
+	"BATT_FET_CFET_MASK",
+	"BATT_FET_CFET_OFF_VAL",
+	"FUEL_GAUGE_FLAGS",
+	"FUEL_GAUGE_MANUF_NAME",
+	"FUEL_GAUGE_DEVICE_NAME",
+	"BATT_VOLTAGE_MAX",
+	"BATT_VOLTAGE_NORMAL",
+	"BATT_VOLTAGE_MIN",
+	"BATT_PRECHARGE_VOLTAGE",
+	"BATT_PRECHARGE_CURRENT",
+	"BATT_START_CHARGING_MIN_C",
+	"BATT_START_CHARGING_MAX_C",
+	"BATT_CHARGING_MIN_C",
+	"BATT_CHARGING_MAX_C",
+	"BATT_DISCHARGING_MIN_C",
+	"BATT_DISCHARGING_MAX_C",
 };
 BUILD_ASSERT(ARRAY_SIZE(field_name) == CBI_TAG_COUNT);
 
@@ -101,9 +132,12 @@ const char help_create[] =
 	"  --fw_config <value>        Firmware configuration bit-field\n"
 	"  --pcb_supplier <value>     PCB supplier\n"
 	"  --ssfc <value>             Second Source Factory Cache bit-field\n"
+	"  --rework_id <lvalue>       REWORK_ID\n"
+	"  --factory_calibration_data <value>    Factory calibration data\n"
 	"\n"
-	"<value> must be a positive integer <= 0XFFFFFFFF and field size can\n"
-	"    be optionally specified by <value:size> notation: e.g. 0xabcd:4.\n"
+	"<value> must be a positive integer <= 0XFFFFFFFF, <lvalue> must be a\n"
+	"  positive integer <= 0xFFFFFFFFFFFFFFFF and field size can be\n"
+	"  optionally specified by <value:size> notation: e.g. 0xabcd:4.\n"
 	"<size> must be a positive integer <= 0XFFFF.\n"
 	"<string> is a string\n"
 	"\n";
@@ -124,6 +158,11 @@ struct integer_field {
 	int size;
 };
 
+struct long_integer_field {
+	uint64_t val;
+	int size;
+};
+
 static void print_help_create(void)
 {
 	printf(help_create, cmd_name);
@@ -137,8 +176,9 @@ static void print_help_show(void)
 static void print_help(void)
 {
 	printf("\nUsage: %s <create|show> [ARGS]\n"
-		"\n"
-		"Utility for CBI:Cros Board Info images.\n", cmd_name);
+	       "\n"
+	       "Utility for CBI:Cros Board Info images.\n",
+	       cmd_name);
 	print_help_create();
 	print_help_show();
 }
@@ -221,7 +261,7 @@ static int parse_integer_field(const char *arg, struct integer_field *f)
 	char *e;
 	char *ch;
 
-	val = strtoul(arg, &e, 0);
+	val = strtoull(arg, &e, 0);
 	if (val > UINT32_MAX || !*arg || (e && *e && *e != ':')) {
 		fprintf(stderr, "Invalid integer value\n");
 		return -1;
@@ -231,7 +271,7 @@ static int parse_integer_field(const char *arg, struct integer_field *f)
 	ch = strchr(arg, ':');
 	if (ch) {
 		ch++;
-		val = strtoul(ch, &e , 0);
+		val = strtoull(ch, &e, 0);
 		if (val < 1 || 4 < val || !*ch || (e && *e)) {
 			fprintf(stderr, "Invalid size suffix\n");
 			return -1;
@@ -250,6 +290,48 @@ static int parse_integer_field(const char *arg, struct integer_field *f)
 	return 0;
 }
 
+static int parse_uint64_field(const char *arg, struct long_integer_field *f)
+{
+	uint64_t val;
+	char *e;
+	char *ch;
+
+	val = strtoul(arg, &e, 0);
+	/* strtoul sets an errno for invalid input. If the value read is out of
+	 * range of representable values by an unsigned long int, the function
+	 * returns ULONG_MAX or ULONG_MIN and the errno is set to ERANGE.
+	 */
+	if (errno == ERANGE || !*arg || (e && *e && *e != ':')) {
+		fprintf(stderr, "Invalid integer value\n");
+		return -1;
+	}
+	f->val = val;
+
+	ch = strchr(arg, ':');
+	if (ch) {
+		ch++;
+		val = strtoul(ch, &e, 0);
+		if (val < 1 || 8 < val || !*ch || (e && *e)) {
+			fprintf(stderr, "Invalid size suffix\n");
+			return -1;
+		}
+		f->size = val;
+	} else {
+		if (f->val < UINT32_MAX)
+			f->size = estimate_field_size(f->val);
+		else
+			f->size = 8; /* assign default long int size */
+	}
+
+	if (f->size < 8 && (f->val > (1ull << f->size * 8))) {
+		fprintf(stderr, "Value (0x%llx) exceeds field size (%d)\n",
+			(unsigned long long)f->val, f->size);
+		return -1;
+	}
+
+	return 0;
+}
+
 static int cmd_create(int argc, char **argv)
 {
 	uint8_t *cbi;
@@ -261,6 +343,8 @@ static int cmd_create(int argc, char **argv)
 		struct integer_field fw_config;
 		struct integer_field pcb_supplier;
 		struct integer_field ssfc;
+		struct long_integer_field rework;
+		struct integer_field factory_calibration_data;
 		const char *dram_part_num;
 		const char *oem_name;
 	} bi;
@@ -291,7 +375,7 @@ static int cmd_create(int argc, char **argv)
 			set_mask |= ARGS_MASK_BOARD_VERSION;
 			break;
 		case OPT_ERASE_BYTE:
-			erase = strtoul(optarg, &e, 0);
+			erase = strtoull(optarg, &e, 0);
 			if (!*optarg || (e && *e)) {
 				fprintf(stderr, "Invalid --erase_byte\n");
 				return -1;
@@ -306,7 +390,7 @@ static int cmd_create(int argc, char **argv)
 				return -1;
 			break;
 		case OPT_SIZE:
-			val = strtoul(optarg, &e, 0);
+			val = strtoull(optarg, &e, 0);
 			if (val > UINT16_MAX || !*optarg || (e && *e)) {
 				fprintf(stderr, "Invalid --size\n");
 				return -1;
@@ -341,11 +425,20 @@ static int cmd_create(int argc, char **argv)
 			if (parse_integer_field(optarg, &bi.ssfc))
 				return -1;
 			break;
+		case OPT_REWORK_ID:
+			if (parse_uint64_field(optarg, &bi.rework))
+				return -1;
+			break;
+		case OPT_FACTORY_CALIBRATION_DATA:
+			if (parse_integer_field(optarg,
+						&bi.factory_calibration_data))
+				return -1;
+			break;
 		}
 	}
 
 	if (set_mask != (ARGS_MASK_BOARD_VERSION | ARGS_MASK_FILENAME |
-			ARGS_MASK_SIZE | ARGS_MASK_SKU_ID)) {
+			 ARGS_MASK_SIZE | ARGS_MASK_SKU_ID)) {
 		fprintf(stderr, "Missing required arguments\n");
 		print_help_create();
 		return -1;
@@ -370,8 +463,12 @@ static int cmd_create(int argc, char **argv)
 	p = cbi_set_data(p, CBI_TAG_FW_CONFIG, &bi.fw_config.val,
 			 bi.fw_config.size);
 	p = cbi_set_data(p, CBI_TAG_PCB_SUPPLIER, &bi.pcb_supplier.val,
-			bi.pcb_supplier.size);
+			 bi.pcb_supplier.size);
 	p = cbi_set_data(p, CBI_TAG_SSFC, &bi.ssfc.val, bi.ssfc.size);
+	p = cbi_set_data(p, CBI_TAG_REWORK_ID, &bi.rework.val, bi.rework.size);
+	p = cbi_set_data(p, CBI_TAG_FACTORY_CALIBRATION_DATA,
+			 &bi.factory_calibration_data.val,
+			 bi.factory_calibration_data.size);
 	p = cbi_set_string(p, CBI_TAG_DRAM_PART_NUM, bi.dram_part_num);
 	p = cbi_set_string(p, CBI_TAG_OEM_NAME, bi.oem_name);
 
@@ -402,12 +499,13 @@ static void print_string(const uint8_t *buf, enum cbi_data_tag tag)
 	name = d->tag < CBI_TAG_COUNT ? field_name[d->tag] : "???";
 
 	printf("    %s: %.*s (%u, %u)\n", name, d->size, (const char *)d->value,
-		d->tag, d->size);
+	       d->tag, d->size);
 }
 
 static void print_integer(const uint8_t *buf, enum cbi_data_tag tag)
 {
-	uint32_t v;
+	uint64_t v;
+
 	struct cbi_data *d = cbi_find_tag(buf, tag);
 	const char *name;
 
@@ -426,12 +524,16 @@ static void print_integer(const uint8_t *buf, enum cbi_data_tag tag)
 	case 4:
 		v = *(uint32_t *)d->value;
 		break;
+	case 8:
+		v = *(uint64_t *)d->value;
+		break;
 	default:
-		printf("    %s: Integer of size %d not supported\n",
-		       name, d->size);
+		printf("    %s: Integer of size %d not supported\n", name,
+		       d->size);
 		return;
 	}
-	printf("    %s: %u (0x%x, %u, %u)\n", name, v, v, d->tag, d->size);
+	printf("    %s: %llu (0x%llx, %u, %u)\n", name, (unsigned long long)v,
+	       (unsigned long long)v, d->tag, d->size);
 }
 
 static int cmd_show(int argc, char **argv)
@@ -500,6 +602,8 @@ static int cmd_show(int argc, char **argv)
 	print_integer(buf, CBI_TAG_FW_CONFIG);
 	print_integer(buf, CBI_TAG_PCB_SUPPLIER);
 	print_integer(buf, CBI_TAG_SSFC);
+	print_integer(buf, CBI_TAG_REWORK_ID);
+	print_integer(buf, CBI_TAG_FACTORY_CALIBRATION_DATA);
 	print_string(buf, CBI_TAG_DRAM_PART_NUM);
 	print_string(buf, CBI_TAG_OEM_NAME);
 
diff --git a/util/chargen b/util/chargen
index 9ba14d3d6a..fd9e73cbda 100644
--- a/util/chargen
+++ b/util/chargen
@@ -1,10 +1,11 @@
 #!/usr/bin/env python3
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 import sys
 
+
 def chargen(modulo, max_chars):
     """Generate a stream of characters on the console.
 
@@ -18,7 +19,7 @@ def chargen(modulo, max_chars):
                  zero, if zero - print indefinitely
     """
 
-    base = '0'
+    base = "0"
     c = base
     counter = 0
     while True:
@@ -26,25 +27,25 @@ def chargen(modulo, max_chars):
         counter = counter + 1
 
         if (max_chars != 0) and (counter == max_chars):
-            sys.stdout.write('\n')
+            sys.stdout.write("\n")
             return
 
         if modulo and ((counter % modulo) == 0):
             c = base
             continue
 
-        if c == 'z':
+        if c == "z":
             c = base
-        elif c == 'Z':
-            c = 'a'
-        elif c == '9':
-            c = 'A'
+        elif c == "Z":
+            c = "a"
+        elif c == "9":
+            c = "A"
         else:
-            c = '%c' % (ord(c) + 1)
+            c = "%c" % (ord(c) + 1)
 
 
 def main(args):
-    '''Process command line arguments and invoke chargen if args are valid'''
+    """Process command line arguments and invoke chargen if args are valid"""
 
     modulo = 0
     max_chars = 0
@@ -55,8 +56,7 @@ def main(args):
             if len(args) > 1:
                 max_chars = int(args[1])
     except ValueError:
-        sys.stderr.write('usage %s:'
-                         "['seq_length' ['max_chars']]\n")
+        sys.stderr.write("usage %s:" "['seq_length' ['max_chars']]\n")
         sys.exit(1)
 
     try:
@@ -64,6 +64,7 @@ def main(args):
     except KeyboardInterrupt:
         print()
 
-if __name__ == '__main__':
+
+if __name__ == "__main__":
     main(sys.argv[1:])
     sys.exit(0)
diff --git a/util/check_clang_format.py b/util/check_clang_format.py
new file mode 100755
index 0000000000..529a37302d
--- /dev/null
+++ b/util/check_clang_format.py
@@ -0,0 +1,92 @@
+#!/usr/bin/env python3
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Validate all C/C++ source is formatted with clang-format.
+
+This isn't very useful to users to call directly, but it is run it the
+CQ.  Most users will likely find out they forgot to clang-format by
+the pre-upload checks.
+"""
+
+import logging
+import pathlib
+import shlex
+import subprocess
+import sys
+from typing import List
+
+from chromite.lib import commandline
+
+
+def main(argv=None):
+    """Find all C/C++ files and runs clang-format on them."""
+    parser = commandline.ArgumentParser()
+    parser.add_argument(
+        "--fix",
+        action="store_true",
+        help="Fix any formatting errors automatically.",
+    )
+    parser.add_argument(
+        "file",
+        nargs="*",
+        help="File or directory to clang-format.",
+    )
+    opts = parser.parse_args(argv)
+
+    logging.info("Validating all code is formatted with clang-format.")
+    ec_dir = pathlib.Path(__file__).resolve().parent.parent
+    all_files = [
+        ec_dir / path
+        for path in subprocess.run(
+            ["git", "ls-files", "-z"] + opts.file,
+            check=True,
+            cwd=ec_dir,
+            stdout=subprocess.PIPE,
+            encoding="utf-8",
+        ).stdout.split("\0")
+        if path
+    ]
+
+    cmd: List[str | pathlib.Path] = ["clang-format"]
+    if opts.fix:
+        cmd.append("-i")
+    else:
+        cmd.append("--dry-run")
+    for path in all_files:
+        if not path.is_file() or path.is_symlink():
+            continue
+        if "third_party" in path.parts:
+            continue
+        if (
+            path.name.endswith(".c")
+            or path.name.endswith(".cc")
+            or path.name.endswith(".h")
+        ):
+            cmd.append(path)
+
+    logging.debug("Running %s", " ".join(shlex.quote(str(x)) for x in cmd))
+    result = subprocess.run(
+        cmd,
+        check=False,
+        cwd=ec_dir,
+        stderr=subprocess.PIPE,
+        encoding="utf-8",
+        stdin=subprocess.DEVNULL,
+    )
+    if result.stderr:
+        logging.error("All C/C++ source must be formatted with clang-format!")
+        for line in result.stderr.splitlines():
+            logging.error("%s", line)
+        return 1
+    if result.returncode != 0:
+        logging.error("clang-format failed with no output!")
+        return result.returncode
+
+    logging.info("No clang-format issues found!")
+    return 0
+
+
+if __name__ == "__main__":
+    sys.exit(main(sys.argv[1:]))
diff --git a/util/check_cprints.py b/util/check_cprints.py
new file mode 100755
index 0000000000..38de40c5c7
--- /dev/null
+++ b/util/check_cprints.py
@@ -0,0 +1,39 @@
+#!/usr/bin/env vpython3
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Checks files for invalid CPRINTS calls."""
+
+import re
+import sys
+from typing import List, Optional
+
+import preupload.lib
+
+
+CPRINTS_RE = re.compile(r'(CPRINTS|cprints)[^"]*"[^"]*\\n"')
+
+
+def main(argv: Optional[List[str]] = None) -> Optional[int]:
+    """Look at all files passed in on commandline for invalid CPRINTS calls."""
+    return_code = 0
+    parser = preupload.lib.argument_parser()
+
+    args = parser.parse_args(argv)
+    for filename in args.filename:
+        lines = preupload.lib.cat_file(args, filename).splitlines()
+        for linenum, line in enumerate(lines, start=1):
+            if CPRINTS_RE.search(line):
+                print(
+                    "error: CPRINTS strings should not include newline "
+                    f"characters\n{filename}:{linenum}: {line}",
+                    file=sys.stderr,
+                )
+                return_code = 1
+
+    return return_code
+
+
+if __name__ == "__main__":
+    sys.exit(main(sys.argv[1:]))
diff --git a/util/check_low_coverage_reason.py b/util/check_low_coverage_reason.py
new file mode 100755
index 0000000000..52138dc180
--- /dev/null
+++ b/util/check_low_coverage_reason.py
@@ -0,0 +1,59 @@
+#!/usr/bin/env python3
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Ensure commit messages using LOW_COVERAGE_REASON include a bug."""
+
+import argparse
+import logging
+import pathlib
+import re
+import subprocess
+import sys
+
+
+# Look for LOW_COVERAGE_REASON and then an optional b{:|/}number bug reference.
+LOW_COV_REGEX = re.compile(
+    r"\s*(LOW_COVERAGE_REASON=)(?:(?!b[/|:][\d]+).)*(b[/|:]([\d]+))?"
+)
+EC_BASE = pathlib.Path(__file__).resolve().parent.parent
+
+
+def main(argv=None):
+    """Check for bug in LOW_COVERAGE_REASON."""
+    parser = argparse.ArgumentParser()
+    parser.add_argument(
+        "commit_id",
+        help="Commit whose message will be checked.",
+    )
+    opts = parser.parse_args(argv)
+
+    if opts.commit_id == "pre-submit":
+        # Only run check if verifying an actual commit.
+        return 0
+
+    try:
+        commit_log = subprocess.check_output(
+            ["git", "log", "--max-count=1", opts.commit_id],
+            cwd=EC_BASE,
+        )
+    except subprocess.CalledProcessError as err:
+        logging.error("Unable to query git log: %s", err)
+        return 1
+
+    # Search commit message for LOW_COVERAGE_REASON and bug
+    matches = LOW_COV_REGEX.findall(commit_log.decode())
+    if matches and not any({m[2] for m in matches}):
+        # We have LOW_COVERAGE_REASON line(s) but none include a bug
+        logging.error(
+            "LOW_COVERAGE_REASON line must include one or more bugs "
+            "tracking the reason for missing coverage"
+        )
+        return 1
+
+    return 0
+
+
+if __name__ == "__main__":
+    sys.exit(main(sys.argv[1:]))
diff --git a/util/check_zephyr_project_config.py b/util/check_zephyr_project_config.py
new file mode 100755
index 0000000000..6ef4200476
--- /dev/null
+++ b/util/check_zephyr_project_config.py
@@ -0,0 +1,294 @@
+#!/usr/bin/env vpython3
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Validate Zephyr project configuration files."""
+
+import argparse
+import logging
+import os
+import pathlib
+import site
+import sys
+import tempfile
+
+
+EC_BASE = pathlib.Path(__file__).parent.parent
+
+if "ZEPHYR_BASE" in os.environ:
+    ZEPHYR_BASE = pathlib.Path(os.environ.get("ZEPHYR_BASE"))
+else:
+    ZEPHYR_BASE = pathlib.Path(
+        EC_BASE.resolve().parent.parent / "third_party" / "zephyr" / "main"
+    )
+
+if not os.path.exists(ZEPHYR_BASE):
+    raise Exception(
+        f"ZEPHYR_BASE path does not exist!\nZEPHYR_BASE={ZEPHYR_BASE}"
+    )
+
+
+site.addsitedir(ZEPHYR_BASE / "scripts")
+site.addsitedir(ZEPHYR_BASE / "scripts" / "kconfig")
+# pylint:disable=import-error,wrong-import-position
+import kconfiglib
+import zephyr_module
+
+
+# pylint:enable=import-error,wrong-import-position
+
+# Known configuration file extensions.
+CONF_FILE_EXT = (".conf", ".overlay", "_defconfig")
+
+
+def _parse_args(argv):
+    parser = argparse.ArgumentParser(description=__doc__)
+
+    parser.add_argument(
+        "-v", "--verbose", action="store_true", help="Verbose Output"
+    )
+    parser.add_argument(
+        "-d",
+        "--dt-has",
+        action="store_true",
+        help="Check for options that depends on a DT_HAS_..._ENABLE symbol.",
+    )
+    parser.add_argument(
+        "CONFIG_FILE",
+        nargs="*",
+        help="List of config files to be checked, non config files are ignored.",
+        type=pathlib.Path,
+    )
+
+    return parser.parse_args(argv)
+
+
+def _init_log(verbose):
+    """Initialize a logger object."""
+    console = logging.StreamHandler()
+    console.setFormatter(logging.Formatter("%(levelname)s: %(message)s"))
+
+    log = logging.getLogger(__file__)
+    log.addHandler(console)
+
+    if verbose:
+        log.setLevel(logging.DEBUG)
+
+    return log
+
+
+def _default_y(defaults):
+    """Return true if the symbol default is 'default y'
+
+    True if the symbol has any 'default y' definition, regardless of other
+    conditions.
+    """
+    for val, _ in defaults:
+        if (
+            isinstance(val, kconfiglib.Symbol)
+            and val.is_constant
+            and val.str_value == "y"
+        ):
+            return True
+    return False
+
+
+def _default_y_if_ztest(defaults):
+    """Return true if the symbol default is 'default y' if ZTEST
+
+
+    True if the symbol has any 'default y if ZTEST' definition.
+    """
+    for val, cond in defaults:
+        if (
+            isinstance(val, kconfiglib.Symbol)
+            and val.is_constant
+            and val.str_value == "y"
+            and isinstance(cond, kconfiglib.Symbol)
+            and cond.name == "ZTEST"
+        ):
+            return True
+    return False
+
+
+class KconfigCheck:
+    """Validate Zephyr project configuration files.
+
+    Attributes:
+        verbose: whether to enable verbose mode logging
+    """
+
+    def __init__(self, verbose):
+        self.log = _init_log(verbose)
+        self.fail_count = 0
+
+        # Preload the upstream Kconfig.
+        self.program_kconf = {None: self._init_kconfig(None)}
+
+    def _init_kconfig(self, filename):
+        """Initialize a kconfiglib object with all boards and arch options.
+
+        Args:
+            filename: the path of the Kconfig file to load.
+
+        Returns:
+            A kconfiglib.Kconfig object.
+        """
+        with tempfile.TemporaryDirectory() as temp_dir:
+            modules = zephyr_module.parse_modules(
+                ZEPHYR_BASE, modules=[EC_BASE]
+            )
+
+            kconfig = ""
+            for module in modules:
+                kconfig += zephyr_module.process_kconfig(
+                    module.project, module.meta
+                )
+
+            # generate Kconfig.modules file
+            with open(
+                pathlib.Path(temp_dir) / "Kconfig.modules",
+                "w",
+                encoding="utf-8",
+            ) as file:
+                file.write(kconfig)
+
+            # generate empty Kconfig.dts file
+            with open(
+                pathlib.Path(temp_dir) / "Kconfig.dts", "w", encoding="utf-8"
+            ) as file:
+                file.write("")
+
+            os.environ["ZEPHYR_BASE"] = str(ZEPHYR_BASE)
+            os.environ["srctree"] = str(ZEPHYR_BASE)
+            os.environ["KCONFIG_BINARY_DIR"] = temp_dir
+            os.environ["ARCH_DIR"] = "arch"
+            os.environ["ARCH"] = "*"
+            os.environ["BOARD_DIR"] = "boards/posix/native_posix"
+
+            if not filename:
+                filename = os.path.join(ZEPHYR_BASE, "Kconfig")
+
+            self.log.info("Loading Kconfig: %s", filename)
+
+            return kconfiglib.Kconfig(filename)
+
+    def _kconf_from_path(self, path):
+        """Return a Kconfig object for the specified path.
+
+        If path resides under zephyr/program, find the name of the program and
+        look for a corresponding program specific Kconfig file. If one is
+        present, return a corresponding Kconfig object for the program.
+
+        Stores a list of per-program Kconfig objects internally, so each
+        program Kconfig is only loaded once.
+
+        Args:
+            path: the path of the Kconfig file to load.
+
+        Returns:
+            A kconfiglib.Kconfig object.
+        """
+        program_path = pathlib.Path(EC_BASE, "zephyr", "program")
+        file_path = pathlib.Path(path).resolve()
+
+        program = None
+        program_kconfig = None
+        if program_path in file_path.parents:
+            idx = file_path.parents.index(program_path)
+            program = file_path.parts[-(idx + 1)]
+            kconfig_path = pathlib.Path(program_path, program, "Kconfig")
+            if kconfig_path.is_file():
+                program_kconfig = kconfig_path
+
+        self.log.info(
+            "Path: %s, program: %s, program_kconfig: %s",
+            path,
+            program,
+            program_kconfig,
+        )
+
+        if program not in self.program_kconf:
+            if not program_kconfig:
+                self.program_kconf[program] = self.program_kconf[None]
+            else:
+                self.program_kconf[program] = self._init_kconfig(
+                    program_kconfig
+                )
+
+        return self.program_kconf[program]
+
+    def _fail(self, *args):
+        """Report a fail in the error log and increment the fail counter."""
+        self.fail_count += 1
+        self.log.error(*args)
+
+    def _filter_config_files(self, files):
+        """Yield files with known config suffixes from the command line."""
+        for file in files:
+            if not file.exists():
+                self.log.info("Ignoring %s: file has been removed", file)
+                continue
+
+            if not file.name.endswith(CONF_FILE_EXT):
+                self.log.info("Ignoring %s: unrecognized suffix", file)
+                continue
+
+            yield file
+
+    def _check_dt_has(self, file_name):
+        """Check file_name for known automatic config options.
+
+        Check file_name for any explicitly enabled option that has a dependency
+        on a devicetree symbol. These are normally enabled automatically so
+        there's no point enabling them explicitly.
+        """
+        kconf = self._kconf_from_path(file_name)
+
+        symbols = {}
+        for name, val in kconf.syms.items():
+            dep = kconfiglib.expr_str(val.direct_dep)
+            if "DT_HAS_" in dep:
+                if _default_y(val.orig_defaults) and not _default_y_if_ztest(
+                    val.orig_defaults
+                ):
+                    symbols[name] = dep
+
+        self.log.info("Checking %s", file_name)
+
+        with open(file_name, "r", encoding="utf-8") as file:
+            for line_num, line in enumerate(file.readlines(), start=1):
+                for name, dep in symbols.items():
+                    match = f"CONFIG_{name}=y"
+                    if line.startswith(match):
+                        self._fail(
+                            "%s:%d: unnecessary config option %s (depends on %s)",
+                            file_name,
+                            line_num,
+                            match,
+                            dep,
+                        )
+
+    def run_checks(self, files, dt_has):
+        """Run all config checks."""
+        config_files = self._filter_config_files(files)
+
+        for file in config_files:
+            if dt_has:
+                self._check_dt_has(file)
+
+        return self.fail_count
+
+
+def main(argv):
+    """Main function"""
+    args = _parse_args(argv)
+
+    kconfig_checker = KconfigCheck(args.verbose)
+
+    return kconfig_checker.run_checks(args.CONFIG_FILE, args.dt_has)
+
+
+if __name__ == "__main__":
+    sys.exit(main(sys.argv[1:]))
diff --git a/util/check_zephyr_project_config.py.vpython3 b/util/check_zephyr_project_config.py.vpython3
new file mode 120000
index 0000000000..d586316989
--- /dev/null
+++ b/util/check_zephyr_project_config.py.vpython3
@@ -0,0 +1 @@
+../../../third_party/zephyr/main/.vpython3
\ No newline at end of file
diff --git a/util/check_zephyr_project_config_unittest.py b/util/check_zephyr_project_config_unittest.py
new file mode 100755
index 0000000000..4a97b9a6c2
--- /dev/null
+++ b/util/check_zephyr_project_config_unittest.py
@@ -0,0 +1,365 @@
+#!/usr/bin/env python3
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Unit tests for check_zephyr_project_config.py"""
+
+import os
+import pathlib
+import site
+import unittest
+
+import check_zephyr_project_config
+import mock  # pylint:disable=import-error
+
+
+site.addsitedir(check_zephyr_project_config.ZEPHYR_BASE / "scripts" / "kconfig")
+# pylint:disable=import-error,wrong-import-position
+import kconfiglib
+
+
+# pylint:disable=protected-access
+
+
+class TestKconfigCheck(unittest.TestCase):
+    """Tests for KconfigCheck."""
+
+    @mock.patch("check_zephyr_project_config.KconfigCheck._init_kconfig")
+    def setUp(self, init_kconfig_mock):  # pylint:disable=arguments-differ
+        mock_kconfig = mock.Mock()
+        init_kconfig_mock.return_value = mock_kconfig
+
+        self.kcheck = check_zephyr_project_config.KconfigCheck(True)
+
+        self.assertEqual(self.kcheck.fail_count, 0)
+        self.assertEqual(self.kcheck.program_kconf, {None: mock_kconfig})
+
+    @mock.patch("zephyr_module.parse_modules")
+    @mock.patch("zephyr_module.process_kconfig")
+    @mock.patch("kconfiglib.Kconfig")
+    def test_init_kconfig(
+        self, kconfig_mock, process_kconfig_mock, parse_modules_mock
+    ):
+        """Initialize a Kconfig with the upstream Kconfig file."""
+        mock_module = mock.Mock()
+        mock_module.project = "project"
+        mock_module.meta = "meta"
+        parse_modules_mock.return_value = [mock_module]
+        process_kconfig_mock.return_value = "fake kconfig"
+
+        os.environ["ZEPHYR_BASE"] = "/totally/not/zephyr/base"
+        os.environ["srctree"] = "/also/not/zephyr/base"
+        os.environ["ARCH_DIR"] = "not_an_arch_dir"
+        os.environ["ARCH"] = "not_a_star"
+        os.environ["BOARD_DIR"] = "something_else"
+
+        self.kcheck._init_kconfig(None)
+
+        parse_modules_mock.assert_called_once_with(
+            check_zephyr_project_config.ZEPHYR_BASE,
+            modules=[check_zephyr_project_config.EC_BASE],
+        )
+        process_kconfig_mock.assert_called_once_with("project", "meta")
+        kconfig_mock.assert_called_once_with(
+            str(check_zephyr_project_config.ZEPHYR_BASE / "Kconfig")
+        )
+
+        self.assertEqual(
+            os.environ["ZEPHYR_BASE"],
+            str(check_zephyr_project_config.ZEPHYR_BASE),
+        )
+        self.assertEqual(
+            os.environ["srctree"], str(check_zephyr_project_config.ZEPHYR_BASE)
+        )
+        self.assertEqual(os.environ["ARCH_DIR"], "arch")
+        self.assertEqual(os.environ["ARCH"], "*")
+        self.assertEqual(os.environ["BOARD_DIR"], "boards/posix/native_posix")
+
+    @mock.patch("zephyr_module.parse_modules")
+    @mock.patch("zephyr_module.process_kconfig")
+    @mock.patch("kconfiglib.Kconfig")
+    def test_init_kconfig_filename(
+        self, kconfig_mock, process_kconfig_mock, parse_modules_mock
+    ):
+        """Initialize a Kconfig with a specific path."""
+        kconfig_path = "my/project/Kconfig"
+
+        self.kcheck._init_kconfig(kconfig_path)
+
+        kconfig_mock.assert_called_once_with(kconfig_path)
+        self.assertEqual(process_kconfig_mock.call_count, 0)
+        parse_modules_mock.assert_called_once_with(mock.ANY, modules=mock.ANY)
+
+    @mock.patch("pathlib.Path.is_file")
+    @mock.patch("check_zephyr_project_config.KconfigCheck._init_kconfig")
+    def test_kconf_from_path(self, kconfig_mock, is_file_mock):
+        """Test the cached Kconfig load from path."""
+        fake_kconfig_upstream = mock.Mock()
+        fake_kconfig_program = mock.Mock()
+        fake_kconfig_program_new = mock.Mock()
+        kconfig_mock.return_value = fake_kconfig_program_new
+        self.kcheck.program_kconf = {
+            None: fake_kconfig_upstream,
+            "cached_program": fake_kconfig_program,
+        }
+
+        # random project
+        out = self.kcheck._kconf_from_path("random/path")
+
+        self.assertEqual(out, fake_kconfig_upstream)
+        self.assertEqual(kconfig_mock.call_count, 0)
+        self.assertEqual(is_file_mock.call_count, 0)
+
+        # already loaded
+        is_file_mock.return_value = True
+        fake_path = pathlib.Path(
+            check_zephyr_project_config.EC_BASE,
+            "zephyr",
+            "program",
+            "cached_program",
+        )
+
+        out = self.kcheck._kconf_from_path(fake_path)
+
+        self.assertEqual(out, fake_kconfig_program)
+        self.assertEqual(kconfig_mock.call_count, 0)
+        is_file_mock.assert_called_once_with()
+        is_file_mock.reset_mock()
+
+        # project with no kconfig
+        is_file_mock.return_value = False
+        fake_path = pathlib.Path(
+            check_zephyr_project_config.EC_BASE,
+            "zephyr",
+            "program",
+            "program_with_no_kconfig",
+        )
+
+        out = self.kcheck._kconf_from_path(fake_path)
+
+        self.assertEqual(out, fake_kconfig_upstream)
+        self.assertEqual(kconfig_mock.call_count, 0)
+        is_file_mock.assert_called_once_with()
+        is_file_mock.reset_mock()
+
+        # project with kconfig
+        is_file_mock.return_value = True
+        fake_path = pathlib.Path(
+            check_zephyr_project_config.EC_BASE,
+            "zephyr",
+            "program",
+            "program_with_kconfig",
+        )
+
+        out = self.kcheck._kconf_from_path(fake_path)
+
+        self.assertEqual(out, fake_kconfig_program_new)
+        kconfig_mock.assert_called_once_with(pathlib.Path(fake_path, "Kconfig"))
+        is_file_mock.assert_called_once_with()
+        is_file_mock.reset_mock()
+
+        # final cache state
+        self.assertEqual(
+            self.kcheck.program_kconf,
+            {
+                None: fake_kconfig_upstream,
+                "cached_program": fake_kconfig_program,
+                "program_with_kconfig": fake_kconfig_program_new,
+                "program_with_no_kconfig": fake_kconfig_upstream,
+            },
+        )
+
+    def test_fail(self):
+        """Test the fail method."""
+        with mock.patch.object(self.kcheck, "log") as log_mock:
+            self.assertEqual(self.kcheck.fail_count, 0)
+
+            self.kcheck._fail("broken")
+
+            self.assertEqual(self.kcheck.fail_count, 1)
+            log_mock.error.assert_called_once_with("broken")
+
+    def test_filter_config_files(self):
+        """Test the config file filter."""
+        file_no_exist = mock.Mock()
+        file_no_exist.exists.return_value = False
+
+        file_exists = mock.Mock()
+        file_exists.exists.return_value = True
+        file_exists.name = "definitely_not_a_conf"
+
+        file_conf = mock.Mock()
+        file_conf.exists.return_value = True
+        file_conf.name = "blah.conf"
+
+        files = [file_no_exist, file_exists, file_conf]
+
+        out = list(self.kcheck._filter_config_files(files))
+
+        self.assertEqual(out, [file_conf])
+
+    @mock.patch("check_zephyr_project_config._default_y_if_ztest")
+    @mock.patch("check_zephyr_project_config._default_y")
+    @mock.patch("kconfiglib.expr_str")
+    @mock.patch("check_zephyr_project_config.KconfigCheck._kconf_from_path")
+    @mock.patch("check_zephyr_project_config.KconfigCheck._fail")
+    def test_check_dt_has(
+        self,
+        fail_mock,
+        kconf_from_path_mock,
+        expr_str_mock,
+        def_y_mock,
+        def_y_if_ztest_mock,
+    ):
+        """Test the DT_HAS_ check."""
+        fake_symbol_no_dt = mock.Mock()
+        fake_symbol_no_dt.direct_dep = "nothing with devicetree"
+
+        fake_symbol_dt = mock.Mock()
+        fake_symbol_dt.direct_dep = (
+            "a bunch of stuff with DT_HAS_something in the middle"
+        )
+
+        fake_symbol_dt_default_n = mock.Mock()
+        fake_symbol_dt_default_n.direct_dep = (
+            "a bunch of stuff with DT_HAS_something in the middle"
+        )
+        fake_symbol_dt_default_n.orig_defaults = mock.Mock()
+
+        fake_symbol_dt_emul = mock.Mock()
+        fake_symbol_dt_emul.direct_dep = (
+            "a bunch of stuff with DT_HAS_something in the middle"
+        )
+        fake_symbol_dt_emul.orig_defaults = mock.Mock()
+
+        fake_kconf = mock.Mock()
+        fake_kconf.syms = {
+            "NO_DT": fake_symbol_no_dt,
+            "DT": fake_symbol_dt,
+            "DT_BUT_DEFAULT_N": fake_symbol_dt_default_n,
+            "DT_BUT_EMUL": fake_symbol_dt_emul,
+        }
+
+        def_y_mock.side_effect = (
+            lambda deps: deps != fake_symbol_dt_default_n.orig_defaults
+        )
+        def_y_if_ztest_mock.side_effect = (
+            lambda deps: deps == fake_symbol_dt_emul.orig_defaults
+        )
+
+        kconf_from_path_mock.return_value = fake_kconf
+        expr_str_mock.side_effect = lambda val: val
+
+        data = """
+# some comment
+CONFIG_NOT_RELATED=n
+CONFIG_NO_DT=y
+CONFIG_NO_DT=n
+CONFIG_DT=y
+CONFIG_DT=y # and a comment
+CONFIG_DT=n
+CONFIG_SOMETHING_ELSE=y
+CONFIG_DT_BUT_DEFAULT_N=y
+CONFIG_DT_BUT_EMUL=y
+"""
+        with mock.patch("builtins.open", mock.mock_open(read_data=data)):
+            self.kcheck._check_dt_has("the_file")
+
+        self.assertListEqual(
+            fail_mock.call_args_list,
+            [
+                mock.call(
+                    mock.ANY,
+                    "the_file",
+                    6,
+                    "CONFIG_DT=y",
+                    fake_symbol_dt.direct_dep,
+                ),
+                mock.call(
+                    mock.ANY,
+                    "the_file",
+                    7,
+                    "CONFIG_DT=y",
+                    fake_symbol_dt.direct_dep,
+                ),
+            ],
+        )
+
+    @mock.patch("check_zephyr_project_config.KconfigCheck._check_dt_has")
+    @mock.patch("check_zephyr_project_config.KconfigCheck._filter_config_files")
+    def test_run_checks_dt_has(
+        self, filter_config_files_mock, check_dt_has_mock
+    ):
+        """Test the run_check method for dt_has."""
+        filter_config_files_mock.return_value = ["a", "b"]
+
+        self.kcheck.run_checks([], True)
+
+        self.assertListEqual(
+            check_dt_has_mock.call_args_list, [mock.call("a"), mock.call("b")]
+        )
+
+
+class TestKconfigSymbolChecks(unittest.TestCase):
+    """Tests for symbol checks."""
+
+    def setUp(self):  # pylint:disable=arguments-differ
+        self.sym_y = kconfiglib.Symbol()
+        self.sym_y.name = "y"
+        self.sym_y.is_constant = True
+
+        self.sym_n = kconfiglib.Symbol()
+        self.sym_n.name = "n"
+        self.sym_n.is_constant = True
+
+        self.sym_ztest = kconfiglib.Symbol()
+        self.sym_ztest.name = "ZTEST"
+
+        self.sym_not_ztest = (kconfiglib.NOT, self.sym_ztest)
+
+    def test_default_y(self):
+        """Test the _default_y function."""
+        self.assertTrue(
+            check_zephyr_project_config._default_y([[self.sym_y, self.sym_y]])
+        )
+        self.assertTrue(
+            check_zephyr_project_config._default_y(
+                [[self.sym_y, self.sym_not_ztest]]
+            )
+        )
+        self.assertTrue(
+            check_zephyr_project_config._default_y(
+                [[self.sym_y, self.sym_ztest]]
+            )
+        )
+        self.assertFalse(
+            check_zephyr_project_config._default_y([[self.sym_n, self.sym_n]])
+        )
+
+    def test_default_y_if_ztest(self):
+        """Test the _default_y_if_ztest function."""
+        self.assertFalse(
+            check_zephyr_project_config._default_y_if_ztest(
+                [[self.sym_y, self.sym_y]]
+            )
+        )
+        self.assertFalse(
+            check_zephyr_project_config._default_y_if_ztest(
+                [[self.sym_y, self.sym_not_ztest]]
+            )
+        )
+        self.assertTrue(
+            check_zephyr_project_config._default_y_if_ztest(
+                [[self.sym_y, self.sym_ztest]]
+            )
+        )
+        self.assertFalse(
+            check_zephyr_project_config._default_y_if_ztest(
+                [[self.sym_n, self.sym_n]]
+            )
+        )
+
+
+if __name__ == "__main__":
+    unittest.main()
diff --git a/util/check_ztest.py b/util/check_ztest.py
new file mode 100755
index 0000000000..69cb6a08df
--- /dev/null
+++ b/util/check_ztest.py
@@ -0,0 +1,50 @@
+#!/usr/bin/env vpython3
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Checks files for invalid ZTEST decls."""
+
+import re
+import sys
+from typing import List, Optional
+
+import preupload.lib
+
+
+ZTEST_RE = re.compile(
+    r"(ZTEST|ZTEST_F|ZTEST_USER|ZTEST_USER_F)\(\w+,\s*($|\w+)"
+)
+
+
+def main(argv: Optional[List[str]] = None) -> Optional[int]:
+    """Look at all files passed in on commandline for ZTEST decls where the
+    test is not named test_.
+    """
+    return_code = 0
+    parser = preupload.lib.argument_parser()
+
+    args = parser.parse_args(argv)
+    for filename in args.filename:
+        lines = preupload.lib.cat_file(args, filename).splitlines()
+        line_iter = iter(enumerate(lines, start=1))
+        for linenum, line in line_iter:
+            line = line.rstrip("\n")
+            match = ZTEST_RE.search(line)
+            if match and match.group(2) == "":
+                linenum, line2 = next(line_iter)
+                line += line2.rstrip("\n")
+                match = ZTEST_RE.search(line)
+            if match and not match.group(2).startswith("test_"):
+                print(
+                    "error: 'test_' prefix missing from test function name"
+                    f"\n{filename}:{linenum}: {match.group(2)}",
+                    file=sys.stderr,
+                )
+                return_code = 1
+
+    return return_code
+
+
+if __name__ == "__main__":
+    sys.exit(main(sys.argv[1:]))
diff --git a/util/clangd_config.py b/util/clangd_config.py
new file mode 100755
index 0000000000..e9b23e3a04
--- /dev/null
+++ b/util/clangd_config.py
@@ -0,0 +1,194 @@
+#!/usr/bin/env python3
+
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Setup clangd for the given board and image"""
+
+import argparse
+import glob
+import multiprocessing
+import os
+from pathlib import Path
+import shutil
+import subprocess
+import sys
+from typing import List, Optional
+
+
+def ec_fetch_boards(ec_root: Path) -> Optional[List[str]]:
+    """Return a list of EC boards seen."""
+
+    base = str(ec_root) + "/board/"
+
+    boards = glob.glob(base + "*")
+    if boards is None:
+        return None
+
+    return [b[len(base) :] for b in boards]
+
+
+def zephyr_fetch_projects(ec_root: Path) -> Optional[List[str]]:
+    """Return a list of Zephyr projects seen."""
+
+    base = str(ec_root) + "/zephyr/program/"
+
+    boards = glob.glob(base + "*")
+    if boards is None:
+        return None
+
+    return [b[len(base) :] for b in boards]
+
+
+# We would use image: Literal["RW", "RO"], but it was only added in Python 3.8.
+def ec_build(ec_root: Path, board: str, image: str) -> Optional[Path]:
+    """Build the correct compile_commands.json for EC board/image."""
+
+    target = Path(f"build/{board}/{image}/compile_commands.json")
+    cmd = [
+        "make",
+        f"-j{multiprocessing.cpu_count()}",
+        "BOARD=" + board,
+        str(target),
+    ]
+
+    print(" ".join(cmd))
+    status = subprocess.run(cmd, check=False, cwd=ec_root)
+
+    if status.returncode != 0:
+        return None
+    return target
+
+
+# We would use image: Literal["RW", "RO"], but it was only added in Python 3.8.
+def zephyr_build(ec_root: Path, board: str, image: str) -> Optional[Path]:
+    """Build the correct compile_commands.json for Zephyr board/image"""
+
+    target = Path(
+        f"build/zephyr/{board}/build-{image.lower()}/compile_commands.json"
+    )
+    cmd = ["zmake", "configure", board]
+
+    print(" ".join(cmd))
+    status = subprocess.run(cmd, check=False, cwd=ec_root)
+
+    if status.returncode != 0:
+        return None
+
+    # Replace /mnt/host/source with path of chromiumos outside chroot
+    default_chromiumos_path_outside_chroot = os.path.join(
+        Path.home(), "chromiumos"
+    )
+    chromiumos_path_outside_chroot = os.environ.get(
+        "EXTERNAL_TRUNK_PATH", default_chromiumos_path_outside_chroot
+    )
+    chromiumos_path_inside_chroot = "/mnt/host/source"
+
+    print(
+        f"Replacing '{chromiumos_path_inside_chroot}' with "
+        + f"'{chromiumos_path_outside_chroot}' in file {target}"
+    )
+
+    target.write_text(
+        target.read_text().replace(
+            chromiumos_path_inside_chroot, chromiumos_path_outside_chroot
+        )
+    )
+
+    return target
+
+
+def copy(ec_root: Path, target: Path) -> None:
+    """Copy the correct compile_commands.json to the EC root."""
+
+    print(f"Copying {target} to EC root.")
+    root_cmds_path = ec_root / "compile_commands.json"
+    if root_cmds_path.exists():
+        root_cmds_path.unlink()
+    shutil.copy(ec_root / target, root_cmds_path)
+
+
+def link(ec_root: Path, target: Path) -> None:
+    """Link the correct compile_commands.json to the EC root."""
+
+    print(f"Linking compile_comands.json to {target}")
+    root_cmds_path = ec_root / "compile_commands.json"
+    if root_cmds_path.exists():
+        root_cmds_path.unlink()
+    root_cmds_path.symlink_to(target)
+
+
+def main(argv: List[str]) -> int:
+    """Build compile_commands.json for the board/image and lnk to it."""
+
+    parser = argparse.ArgumentParser(description=__doc__)
+    # There are far too many boards to show in help message, so we omit the
+    # choice option and manually check the boards below.
+    parser.add_argument("board", help="EC board name")
+    parser.add_argument(
+        "image",
+        help="EC firmware copy",
+        nargs="?",
+        choices=["ro", "rw"],
+        default="rw",
+        type=str.lower,
+    )
+    parser.add_argument(
+        "-s", help="symbolically link instead of copying.", action="store_true"
+    )
+    parser.add_argument(
+        "--os",
+        help="OS used to build board",
+        nargs="?",
+        choices=["auto", "ec", "zephyr"],
+        default="auto",
+        type=str.lower,
+    )
+    args = parser.parse_args(argv)
+
+    ec_root = Path(os.path.relpath(os.path.dirname(__file__) + "/.."))
+
+    ec_boards = ec_fetch_boards(ec_root)
+    if ec_boards is None:
+        parser.error("Can't find EC boards directory.")
+
+    zephyr_projects = zephyr_fetch_projects(ec_root)
+    if zephyr_projects is None:
+        parser.error("Can't find Zephyr projects directory.")
+
+    is_in_ec = args.board in ec_boards
+    is_in_zephyr = args.board in zephyr_projects
+
+    if not is_in_ec and not is_in_zephyr:
+        parser.error(f"Board '{args.board}' does not exist.")
+
+    # When "os" is auto, try Zephyr first, fall back to EC.
+    os_selection = args.os
+    if os_selection == "auto":
+        if is_in_zephyr:
+            os_selection = "zephyr"
+        else:
+            os_selection = "ec"
+
+    print(f"Configuring for {os_selection}.")
+
+    if os_selection == "ec":
+        target = ec_build(ec_root, args.board, args.image.upper())
+    else:
+        target = zephyr_build(ec_root, args.board, args.image.upper())
+
+    if target is None:
+        print("Failed to build compile_commands.json")
+        return 1
+
+    if args.s:
+        link(ec_root, target)
+    else:
+        copy(ec_root, target)
+
+    return 0
+
+
+if __name__ == "__main__":
+    sys.exit(main(sys.argv[1:]))
diff --git a/util/comm-dev.c b/util/comm-dev.c
deleted file mode 100644
index 679f15225f..0000000000
--- a/util/comm-dev.c
+++ /dev/null
@@ -1,293 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <assert.h>
-#include <errno.h>
-#include <fcntl.h>
-#include <poll.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/ioctl.h>
-#include <sys/stat.h>
-#include <sys/types.h>
-#include <unistd.h>
-
-#include "cros_ec_dev.h"
-#include "comm-host.h"
-#include "ec_commands.h"
-#include "misc_util.h"
-
-static int fd = -1;
-
-#ifndef ARRAY_SIZE
-#define ARRAY_SIZE(t) (sizeof(t) / sizeof(t[0]))
-#endif
-
-static const char * const meanings[] = {
-	"SUCCESS",
-	"INVALID_COMMAND",
-	"ERROR",
-	"INVALID_PARAM",
-	"ACCESS_DENIED",
-	"INVALID_RESPONSE",
-	"INVALID_VERSION",
-	"INVALID_CHECKSUM",
-	"IN_PROGRESS",
-	"UNAVAILABLE",
-	"TIMEOUT",
-	"OVERFLOW",
-	"INVALID_HEADER",
-	"REQUEST_TRUNCATED",
-	"RESPONSE_TOO_BIG",
-	"BUS_ERROR",
-	"BUSY",
-	"INVALID_HEADER_VERSION",
-	"INVALID_HEADER_CRC",
-	"INVALID_DATA_CRC",
-	"DUP_UNAVAILABLE",
-};
-
-static const char *strresult(int i)
-{
-	if (i < 0 || i >= ARRAY_SIZE(meanings))
-		return "<unknown>";
-	return meanings[i];
-}
-
-/* Old ioctl format, used by Chrome OS 3.18 and older */
-
-static int ec_command_dev(int command, int version,
-			  const void *outdata, int outsize,
-			  void *indata, int insize)
-{
-	struct cros_ec_command s_cmd;
-	int r;
-
-	s_cmd.command = command;
-	s_cmd.version = version;
-	s_cmd.result = 0xff;
-	s_cmd.outsize = outsize;
-	s_cmd.outdata = (uint8_t *)outdata;
-	s_cmd.insize = insize;
-	s_cmd.indata = indata;
-
-	r = ioctl(fd, CROS_EC_DEV_IOCXCMD, &s_cmd);
-	if (r < 0) {
-		fprintf(stderr, "ioctl %d, errno %d (%s), EC result %d (%s)\n",
-			r, errno, strerror(errno), s_cmd.result,
-			strresult(s_cmd.result));
-		if (errno == EAGAIN && s_cmd.result == EC_RES_IN_PROGRESS) {
-			s_cmd.command = EC_CMD_RESEND_RESPONSE;
-			r = ioctl(fd, CROS_EC_DEV_IOCXCMD, &s_cmd);
-			fprintf(stderr,
-				"ioctl %d, errno %d (%s), EC result %d (%s)\n",
-				r, errno, strerror(errno), s_cmd.result,
-				strresult(s_cmd.result));
-		}
-	} else if (s_cmd.result != EC_RES_SUCCESS) {
-		fprintf(stderr, "EC result %d (%s)\n", s_cmd.result,
-			strresult(s_cmd.result));
-		return -EECRESULT - s_cmd.result;
-	}
-
-	return r;
-}
-
-static int ec_readmem_dev(int offset, int bytes, void *dest)
-{
-	struct cros_ec_readmem s_mem;
-	struct ec_params_read_memmap r_mem;
-	int r;
-	static int fake_it;
-
-	if (!fake_it) {
-		s_mem.offset = offset;
-		s_mem.bytes = bytes;
-		s_mem.buffer = dest;
-		r = ioctl(fd, CROS_EC_DEV_IOCRDMEM, &s_mem);
-		if (r < 0 && errno == ENOTTY)
-			fake_it = 1;
-		else
-			return r;
-	}
-
-	r_mem.offset = offset;
-	r_mem.size = bytes;
-	return ec_command_dev(EC_CMD_READ_MEMMAP, 0,
-			      &r_mem, sizeof(r_mem),
-			      dest, bytes);
-}
-
-/* New ioctl format, used by Chrome OS 4.4 and later as well as upstream 4.0+ */
-
-static int ec_command_dev_v2(int command, int version,
-			     const void *outdata, int outsize,
-			     void *indata, int insize)
-{
-	struct cros_ec_command_v2 *s_cmd;
-	int r;
-
-	assert(outsize == 0 || outdata != NULL);
-	assert(insize == 0 || indata != NULL);
-
-	s_cmd = malloc(sizeof(struct cros_ec_command_v2) +
-		       MAX(outsize, insize));
-	if (s_cmd == NULL)
-		return -EC_RES_ERROR;
-
-	s_cmd->command = command;
-	s_cmd->version = version;
-	s_cmd->result = 0xff;
-	s_cmd->outsize = outsize;
-	s_cmd->insize = insize;
-	memcpy(s_cmd->data, outdata, outsize);
-
-	r = ioctl(fd, CROS_EC_DEV_IOCXCMD_V2, s_cmd);
-	if (r < 0) {
-		fprintf(stderr, "ioctl %d, errno %d (%s), EC result %d (%s)\n",
-			r, errno, strerror(errno), s_cmd->result,
-			strresult(s_cmd->result));
-		if (errno == EAGAIN && s_cmd->result == EC_RES_IN_PROGRESS) {
-			s_cmd->command = EC_CMD_RESEND_RESPONSE;
-			r = ioctl(fd, CROS_EC_DEV_IOCXCMD_V2, &s_cmd);
-			fprintf(stderr,
-				"ioctl %d, errno %d (%s), EC result %d (%s)\n",
-				r, errno, strerror(errno), s_cmd->result,
-				strresult(s_cmd->result));
-		}
-	} else {
-		memcpy(indata, s_cmd->data, MIN(r, insize));
-		if (s_cmd->result != EC_RES_SUCCESS) {
-			fprintf(stderr, "EC result %d (%s)\n", s_cmd->result,
-				strresult(s_cmd->result));
-			r =  -EECRESULT - s_cmd->result;
-		}
-	}
-	free(s_cmd);
-
-	return r;
-}
-
-static int ec_readmem_dev_v2(int offset, int bytes, void *dest)
-{
-	struct cros_ec_readmem_v2 s_mem;
-	struct ec_params_read_memmap r_mem;
-	int r;
-	static int fake_it;
-
-	if (!fake_it) {
-		s_mem.offset = offset;
-		s_mem.bytes = bytes;
-		r = ioctl(fd, CROS_EC_DEV_IOCRDMEM_V2, &s_mem);
-		if (r < 0 && errno == ENOTTY) {
-			fake_it = 1;
-		} else {
-			memcpy(dest, s_mem.buffer, bytes);
-			return r;
-		}
-	}
-
-	r_mem.offset = offset;
-	r_mem.size = bytes;
-	return ec_command_dev_v2(EC_CMD_READ_MEMMAP, 0,
-				 &r_mem, sizeof(r_mem),
-				 dest, bytes);
-}
-
-/*
- * Attempt to communicate with kernel using old ioctl format.
- * If it returns ENOTTY, assume that this kernel uses the new format.
- */
-static int ec_dev_is_v2(void)
-{
-	struct ec_params_hello h_req = {
-		.in_data = 0xa0b0c0d0
-	};
-	struct ec_response_hello h_resp;
-	struct cros_ec_command s_cmd = { };
-	int r;
-
-	s_cmd.command = EC_CMD_HELLO;
-	s_cmd.result = 0xff;
-	s_cmd.outsize = sizeof(h_req);
-	s_cmd.outdata = (uint8_t *)&h_req;
-	s_cmd.insize = sizeof(h_resp);
-	s_cmd.indata = (uint8_t *)&h_resp;
-
-	r = ioctl(fd, CROS_EC_DEV_IOCXCMD, &s_cmd);
-	if (r < 0 && errno == ENOTTY)
-		return 1;
-
-	return 0;
-}
-
-static int ec_pollevent_dev(unsigned long mask, void *buffer, size_t buf_size,
-			    int timeout)
-{
-	int rv;
-	struct pollfd pf = { .fd = fd, .events = POLLIN };
-
-	ioctl(fd, CROS_EC_DEV_IOCEVENTMASK_V2, mask);
-
-	rv = poll(&pf, 1, timeout);
-	if (rv != 1)
-		return rv;
-
-	if (pf.revents != POLLIN)
-		return -pf.revents;
-
-	return read(fd, buffer, buf_size);
-}
-
-int comm_init_dev(const char *device_name)
-{
-	int (*ec_cmd_readmem)(int offset, int bytes, void *dest);
-	char version[80];
-	char device[80] = "/dev/";
-	int r;
-	char *s;
-
-	strncat(device, (device_name ? device_name : CROS_EC_DEV_NAME), 40);
-	fd = open(device, O_RDWR);
-	if (fd < 0)
-		return 1;
-
-	r = read(fd, version, sizeof(version)-1);
-	if (r <= 0) {
-		close(fd);
-		return 2;
-	}
-	version[r] = '\0';
-	s = strchr(version, '\n');
-	if (s)
-		*s = '\0';
-	if (strcmp(version, CROS_EC_DEV_VERSION)) {
-		close(fd);
-		return 3;
-	}
-
-	if (ec_dev_is_v2()) {
-		ec_command_proto = ec_command_dev_v2;
-		ec_cmd_readmem = ec_readmem_dev_v2;
-	} else {
-		ec_command_proto = ec_command_dev;
-		ec_cmd_readmem = ec_readmem_dev;
-	}
-
-	if (ec_cmd_readmem(EC_MEMMAP_ID, 2, version) == 2 &&
-	    version[0] == 'E' && version[1] == 'C')
-		ec_readmem = ec_cmd_readmem;
-	ec_pollevent = ec_pollevent_dev;
-
-	/*
-	 * Set temporary size, will be updated later.
-	 */
-	ec_max_outsize = EC_PROTO2_MAX_PARAM_SIZE - 8;
-	ec_max_insize = EC_PROTO2_MAX_PARAM_SIZE;
-
-	return 0;
-}
diff --git a/util/comm-dev.cc b/util/comm-dev.cc
new file mode 100644
index 0000000000..1c546abe19
--- /dev/null
+++ b/util/comm-dev.cc
@@ -0,0 +1,300 @@
+/* Copyright 2013 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "comm-host.h"
+#include "cros_ec_dev.h"
+#include "ec_commands.h"
+#include "misc_util.h"
+
+#include <assert.h>
+#include <errno.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <fcntl.h>
+#include <poll.h>
+#include <sys/ioctl.h>
+#include <sys/stat.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+static int fd = -1;
+
+#ifndef ARRAY_SIZE
+#define ARRAY_SIZE(t) (sizeof(t) / sizeof(t[0]))
+#endif
+
+static const char *const meanings[] = {
+	"SUCCESS",
+	"INVALID_COMMAND",
+	"ERROR",
+	"INVALID_PARAM",
+	"ACCESS_DENIED",
+	"INVALID_RESPONSE",
+	"INVALID_VERSION",
+	"INVALID_CHECKSUM",
+	"IN_PROGRESS",
+	"UNAVAILABLE",
+	"TIMEOUT",
+	"OVERFLOW",
+	"INVALID_HEADER",
+	"REQUEST_TRUNCATED",
+	"RESPONSE_TOO_BIG",
+	"BUS_ERROR",
+	"BUSY",
+	"INVALID_HEADER_VERSION",
+	"INVALID_HEADER_CRC",
+	"INVALID_DATA_CRC",
+	"DUP_UNAVAILABLE",
+};
+
+static const char *strresult(int i)
+{
+	if (i < 0 || i >= ARRAY_SIZE(meanings))
+		return "<unknown>";
+	return meanings[i];
+}
+
+/* Old ioctl format, used by Chrome OS 3.18 and older */
+
+static int ec_command_dev(int command, int version, const void *outdata,
+			  int outsize, void *indata, int insize)
+{
+	struct cros_ec_command s_cmd;
+	int r;
+
+	s_cmd.command = command;
+	s_cmd.version = version;
+	s_cmd.result = 0xff;
+	s_cmd.outsize = outsize;
+	s_cmd.outdata = (uint8_t *)outdata;
+	s_cmd.insize = insize;
+	s_cmd.indata = (uint8_t *)(indata);
+
+	r = ioctl(fd, CROS_EC_DEV_IOCXCMD, &s_cmd);
+	if (r < 0) {
+		fprintf(stderr, "ioctl %d, errno %d (%s), EC result %d (%s)\n",
+			r, errno, strerror(errno), s_cmd.result,
+			strresult(s_cmd.result));
+		if (errno == EAGAIN && s_cmd.result == EC_RES_IN_PROGRESS) {
+			s_cmd.command = EC_CMD_RESEND_RESPONSE;
+			r = ioctl(fd, CROS_EC_DEV_IOCXCMD, &s_cmd);
+			if (r < 0) {
+				fprintf(stderr,
+					"ioctl %d, errno %d (%s), EC result %d (%s)\n",
+					r, errno, strerror(errno), s_cmd.result,
+					strresult(s_cmd.result));
+			}
+		}
+	}
+	if (r >= 0 && s_cmd.result != EC_RES_SUCCESS) {
+		fprintf(stderr, "EC result %d (%s)\n", s_cmd.result,
+			strresult(s_cmd.result));
+		return -EECRESULT - s_cmd.result;
+	}
+
+	return r;
+}
+
+static int ec_readmem_dev(int offset, int bytes, void *dest)
+{
+	struct cros_ec_readmem s_mem;
+	struct ec_params_read_memmap r_mem;
+	int r;
+	static int fake_it;
+
+	if (!fake_it) {
+		s_mem.offset = offset;
+		s_mem.bytes = bytes;
+		s_mem.buffer = (char *)(dest);
+		r = ioctl(fd, CROS_EC_DEV_IOCRDMEM, &s_mem);
+		if (r < 0 && errno == ENOTTY)
+			fake_it = 1;
+		else
+			return r;
+	}
+
+	r_mem.offset = offset;
+	r_mem.size = bytes;
+	return ec_command_dev(EC_CMD_READ_MEMMAP, 0, &r_mem, sizeof(r_mem),
+			      dest, bytes);
+}
+
+/* New ioctl format, used by Chrome OS 4.4 and later as well as upstream 4.0+ */
+
+static int ec_command_dev_v2(int command, int version, const void *outdata,
+			     int outsize, void *indata, int insize)
+{
+	struct cros_ec_command_v2 *s_cmd;
+	int r;
+
+	assert(outsize == 0 || outdata != NULL);
+	assert(insize == 0 || indata != NULL);
+
+	s_cmd = (struct cros_ec_command_v2 *)(malloc(
+		sizeof(struct cros_ec_command_v2) + MAX(outsize, insize)));
+	if (s_cmd == NULL)
+		return -EC_RES_ERROR;
+
+	s_cmd->command = command;
+	s_cmd->version = version;
+	s_cmd->result = 0xff;
+	s_cmd->outsize = outsize;
+	s_cmd->insize = insize;
+	memcpy(s_cmd->data, outdata, outsize);
+
+	r = ioctl(fd, CROS_EC_DEV_IOCXCMD_V2, s_cmd);
+	if (r < 0) {
+		fprintf(stderr, "ioctl %d, errno %d (%s), EC result %d (%s)\n",
+			r, errno, strerror(errno), s_cmd->result,
+			strresult(s_cmd->result));
+		if (errno == EAGAIN && s_cmd->result == EC_RES_IN_PROGRESS) {
+			s_cmd->command = EC_CMD_RESEND_RESPONSE;
+			r = ioctl(fd, CROS_EC_DEV_IOCXCMD_V2, s_cmd);
+			if (r < 0) {
+				fprintf(stderr,
+					"ioctl %d, errno %d (%s), EC result %d (%s)\n",
+					r, errno, strerror(errno),
+					s_cmd->result,
+					strresult(s_cmd->result));
+			}
+		}
+	}
+	if (r >= 0) {
+		memcpy(indata, s_cmd->data, MIN(r, insize));
+		if (s_cmd->result != EC_RES_SUCCESS) {
+			fprintf(stderr, "EC result %d (%s)\n", s_cmd->result,
+				strresult(s_cmd->result));
+			r = -EECRESULT - s_cmd->result;
+		}
+	}
+	free(s_cmd);
+
+	return r;
+}
+
+static int ec_readmem_dev_v2(int offset, int bytes, void *dest)
+{
+	struct cros_ec_readmem_v2 s_mem;
+	struct ec_params_read_memmap r_mem;
+	int r;
+	static int fake_it;
+
+	if (!fake_it) {
+		s_mem.offset = offset;
+		s_mem.bytes = bytes;
+		r = ioctl(fd, CROS_EC_DEV_IOCRDMEM_V2, &s_mem);
+		if (r < 0 && errno == ENOTTY) {
+			fake_it = 1;
+		} else {
+			memcpy(dest, s_mem.buffer, bytes);
+			return r;
+		}
+	}
+
+	r_mem.offset = offset;
+	r_mem.size = bytes;
+	return ec_command_dev_v2(EC_CMD_READ_MEMMAP, 0, &r_mem, sizeof(r_mem),
+				 dest, bytes);
+}
+
+/*
+ * Attempt to communicate with kernel using old ioctl format.
+ * If it returns ENOTTY, assume that this kernel uses the new format.
+ */
+static int ec_dev_is_v2(void)
+{
+	struct ec_params_hello h_req = { .in_data = 0xa0b0c0d0 };
+	struct ec_response_hello h_resp;
+	struct cros_ec_command s_cmd = {};
+	int r;
+
+	s_cmd.command = EC_CMD_HELLO;
+	s_cmd.result = 0xff;
+	s_cmd.outsize = sizeof(h_req);
+	s_cmd.outdata = (uint8_t *)&h_req;
+	s_cmd.insize = sizeof(h_resp);
+	s_cmd.indata = (uint8_t *)&h_resp;
+
+	r = ioctl(fd, CROS_EC_DEV_IOCXCMD, &s_cmd);
+	if (r < 0 && errno == ENOTTY)
+		return 1;
+
+	return 0;
+}
+
+static int ec_pollevent_dev(unsigned long mask, void *buffer, size_t buf_size,
+			    int timeout)
+{
+	int rv;
+	struct pollfd pf = { .fd = fd, .events = POLLIN };
+
+	ioctl(fd, CROS_EC_DEV_IOCEVENTMASK_V2, mask);
+
+	rv = poll(&pf, 1, timeout);
+	if (rv != 1)
+		return rv;
+
+	if (pf.revents != POLLIN)
+		return -pf.revents;
+
+	return read(fd, buffer, buf_size);
+}
+
+int comm_init_dev(const char *device_name)
+{
+	int (*ec_cmd_readmem)(int offset, int bytes, void *dest);
+	char version[80];
+	char device[80] = "/dev/";
+	int r;
+	char *s;
+
+	strncat(device, (device_name ? device_name : CROS_EC_DEV_NAME), 40);
+	fd = open(device, O_RDWR);
+	if (fd < 0)
+		return 1;
+
+	r = read(fd, version, sizeof(version) - 1);
+	if (r <= 0) {
+		close(fd);
+		return 2;
+	}
+	version[r] = '\0';
+	s = strchr(version, '\n');
+	if (s)
+		*s = '\0';
+	if (strcmp(version, CROS_EC_DEV_VERSION)) {
+		close(fd);
+		return 3;
+	}
+
+	if (ec_dev_is_v2()) {
+		ec_command_proto = ec_command_dev_v2;
+		ec_cmd_readmem = ec_readmem_dev_v2;
+	} else {
+		ec_command_proto = ec_command_dev;
+		ec_cmd_readmem = ec_readmem_dev;
+	}
+
+	if (ec_cmd_readmem(EC_MEMMAP_ID, 2, version) == 2 &&
+	    version[0] == 'E' && version[1] == 'C')
+		ec_readmem = ec_cmd_readmem;
+	ec_pollevent = ec_pollevent_dev;
+
+	/*
+	 * Set temporary size, will be updated later.
+	 */
+	ec_max_outsize = EC_PROTO2_MAX_PARAM_SIZE - 8;
+	ec_max_insize = EC_PROTO2_MAX_PARAM_SIZE;
+
+	return 0;
+}
+
+int comm_get_fd()
+{
+	return fd;
+}
diff --git a/util/comm-host.c b/util/comm-host.c
deleted file mode 100644
index dd42df1aa8..0000000000
--- a/util/comm-host.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <errno.h>
-#include <stdbool.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "comm-host.h"
-#include "cros_ec_dev.h"
-#include "ec_commands.h"
-#include "misc_util.h"
-
-
-int (*ec_command_proto)(int command, int version,
-			const void *outdata, int outsize,
-			void *indata, int insize);
-
-int (*ec_readmem)(int offset, int bytes, void *dest);
-
-int (*ec_pollevent)(unsigned long mask, void *buffer, size_t buf_size,
-		    int timeout);
-
-int ec_max_outsize, ec_max_insize;
-void *ec_outbuf;
-void *ec_inbuf;
-static int command_offset;
-
-int comm_init_dev(const char *device_name) __attribute__((weak));
-int comm_init_lpc(void) __attribute__((weak));
-int comm_init_i2c(int i2c_bus) __attribute__((weak));
-int comm_init_servo_spi(const char *device_name) __attribute__((weak));
-
-static int fake_readmem(int offset, int bytes, void *dest)
-{
-	struct ec_params_read_memmap p;
-	int c;
-	char *buf;
-
-	p.offset = offset;
-
-	if (bytes) {
-		p.size = bytes;
-		c = ec_command(EC_CMD_READ_MEMMAP, 0, &p, sizeof(p),
-			       dest, p.size);
-		if (c < 0)
-			return c;
-		return p.size;
-	}
-
-	p.size = EC_MEMMAP_TEXT_MAX;
-
-	c = ec_command(EC_CMD_READ_MEMMAP, 0, &p, sizeof(p), dest, p.size);
-	if (c < 0)
-		return c;
-
-	buf = dest;
-	for (c = 0; c < EC_MEMMAP_TEXT_MAX; c++) {
-		if (buf[c] == 0)
-			return c;
-	}
-
-	buf[EC_MEMMAP_TEXT_MAX - 1] = 0;
-	return EC_MEMMAP_TEXT_MAX - 1;
-}
-
-void set_command_offset(int offset)
-{
-	command_offset = offset;
-}
-
-int ec_command(int command, int version,
-	       const void *outdata, int outsize,
-	       void *indata, int insize)
-{
-	/* Offset command code to support sub-devices */
-	return ec_command_proto(command_offset + command, version,
-				outdata, outsize,
-				indata, insize);
-}
-
-int comm_init_alt(int interfaces, const char *device_name, int i2c_bus)
-{
-	bool dev_is_cros_ec;
-
-	/* Default memmap access */
-	ec_readmem = fake_readmem;
-
-	if ((interfaces & COMM_SERVO) && comm_init_servo_spi &&
-	    !comm_init_servo_spi(device_name))
-		return 0;
-
-	/* Do not fallback to other communication methods if target is not a
-	 * cros_ec device */
-	dev_is_cros_ec = !strcmp(CROS_EC_DEV_NAME, device_name);
-
-	/* Fallback to direct LPC on x86 */
-	if (dev_is_cros_ec && (interfaces & COMM_LPC) &&
-			comm_init_lpc && !comm_init_lpc())
-		return 0;
-
-	/* Fallback to direct I2C */
-	if ((dev_is_cros_ec || i2c_bus != -1) && (interfaces & COMM_I2C) &&
-			comm_init_i2c && !comm_init_i2c(i2c_bus))
-		return 0;
-
-	/* Give up */
-	fprintf(stderr, "Unable to establish host communication\n");
-	return 1;
-}
-
-int comm_init_buffer(void)
-{
-	int allow_large_buffer;
-	struct ec_response_get_protocol_info info;
-
-	allow_large_buffer = kernel_version_ge(3, 14, 0);
-	if (allow_large_buffer < 0) {
-		fprintf(stderr, "Unable to check linux version\n");
-		return 1;
-	}
-
-	/* Allocate shared I/O buffers */
-	ec_outbuf = malloc(ec_max_outsize);
-	ec_inbuf = malloc(ec_max_insize);
-	if (!ec_outbuf || !ec_inbuf) {
-		fprintf(stderr, "Unable to allocate buffers\n");
-		return 1;
-	}
-
-	/* read max request / response size from ec for protocol v3+ */
-	if (ec_command(EC_CMD_GET_PROTOCOL_INFO, 0, NULL, 0, &info,
-		sizeof(info)) == sizeof(info)) {
-		int outsize = info.max_request_packet_size -
-			sizeof(struct ec_host_request);
-		int insize = info.max_response_packet_size -
-			sizeof(struct ec_host_response);
-		if ((allow_large_buffer) || (outsize < ec_max_outsize))
-			ec_max_outsize = outsize;
-		if ((allow_large_buffer) || (insize < ec_max_insize))
-			ec_max_insize = insize;
-
-		ec_outbuf = realloc(ec_outbuf, ec_max_outsize);
-		ec_inbuf = realloc(ec_inbuf, ec_max_insize);
-
-		if (!ec_outbuf || !ec_inbuf) {
-			fprintf(stderr, "Unable to reallocate buffers\n");
-			return 1;
-		}
-	}
-
-	return 0;
-}
diff --git a/util/comm-host.cc b/util/comm-host.cc
new file mode 100644
index 0000000000..ef8b9f1125
--- /dev/null
+++ b/util/comm-host.cc
@@ -0,0 +1,153 @@
+/* Copyright 2013 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "comm-host.h"
+#include "cros_ec_dev.h"
+#include "ec_commands.h"
+#include "misc_util.h"
+
+#include <errno.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+int (*ec_command_proto)(int command, int version, const void *outdata,
+			int outsize, void *indata, int insize);
+
+int (*ec_readmem)(int offset, int bytes, void *dest);
+
+int (*ec_pollevent)(unsigned long mask, void *buffer, size_t buf_size,
+		    int timeout);
+
+int ec_max_outsize, ec_max_insize;
+void *ec_outbuf;
+void *ec_inbuf;
+static int command_offset;
+
+int comm_init_dev(const char *device_name) __attribute__((weak));
+int comm_init_lpc(void) __attribute__((weak));
+int comm_init_i2c(int i2c_bus) __attribute__((weak));
+int comm_init_servo_spi(const char *device_name) __attribute__((weak));
+
+static int fake_readmem(int offset, int bytes, void *dest)
+{
+	struct ec_params_read_memmap p;
+	int c;
+	char *buf;
+
+	p.offset = offset;
+
+	if (bytes) {
+		p.size = bytes;
+		c = ec_command(EC_CMD_READ_MEMMAP, 0, &p, sizeof(p), dest,
+			       p.size);
+		if (c < 0)
+			return c;
+		return p.size;
+	}
+
+	p.size = EC_MEMMAP_TEXT_MAX;
+
+	c = ec_command(EC_CMD_READ_MEMMAP, 0, &p, sizeof(p), dest, p.size);
+	if (c < 0)
+		return c;
+
+	buf = (char *)(dest);
+	for (c = 0; c < EC_MEMMAP_TEXT_MAX; c++) {
+		if (buf[c] == 0)
+			return c;
+	}
+
+	buf[EC_MEMMAP_TEXT_MAX - 1] = 0;
+	return EC_MEMMAP_TEXT_MAX - 1;
+}
+
+void set_command_offset(int offset)
+{
+	command_offset = offset;
+}
+
+int ec_command(int command, int version, const void *outdata, int outsize,
+	       void *indata, int insize)
+{
+	/* Offset command code to support sub-devices */
+	return ec_command_proto(command_offset + command, version, outdata,
+				outsize, indata, insize);
+}
+
+int comm_init_alt(int interfaces, const char *device_name, int i2c_bus)
+{
+	bool dev_is_cros_ec;
+
+	/* Default memmap access */
+	ec_readmem = fake_readmem;
+
+	if ((interfaces & COMM_SERVO) && comm_init_servo_spi &&
+	    !comm_init_servo_spi(device_name))
+		return 0;
+
+	/* Do not fallback to other communication methods if target is not a
+	 * cros_ec device */
+	dev_is_cros_ec = !strcmp(CROS_EC_DEV_NAME, device_name);
+
+	/* Fallback to direct LPC on x86 */
+	if (dev_is_cros_ec && (interfaces & COMM_LPC) && comm_init_lpc &&
+	    !comm_init_lpc())
+		return 0;
+
+	/* Fallback to direct I2C */
+	if ((dev_is_cros_ec || i2c_bus != -1) && (interfaces & COMM_I2C) &&
+	    comm_init_i2c && !comm_init_i2c(i2c_bus))
+		return 0;
+
+	/* Give up */
+	fprintf(stderr, "Unable to establish host communication\n");
+	return 1;
+}
+
+int comm_init_buffer(void)
+{
+	int allow_large_buffer;
+	struct ec_response_get_protocol_info info;
+
+	allow_large_buffer = kernel_version_ge(3, 14, 0);
+	if (allow_large_buffer < 0) {
+		fprintf(stderr, "Unable to check linux version\n");
+		return 1;
+	}
+
+	/* Allocate shared I/O buffers */
+	ec_outbuf = malloc(ec_max_outsize);
+	ec_inbuf = malloc(ec_max_insize);
+	if (!ec_outbuf || !ec_inbuf) {
+		fprintf(stderr, "Unable to allocate buffers\n");
+		return 1;
+	}
+
+	/* read max request / response size from ec for protocol v3+ */
+	if (ec_command(EC_CMD_GET_PROTOCOL_INFO, 0, NULL, 0, &info,
+		       sizeof(info)) == sizeof(info)) {
+		int outsize = info.max_request_packet_size -
+			      sizeof(struct ec_host_request);
+		int insize = info.max_response_packet_size -
+			     sizeof(struct ec_host_response);
+		if ((allow_large_buffer) || (outsize < ec_max_outsize))
+			ec_max_outsize = outsize;
+		if ((allow_large_buffer) || (insize < ec_max_insize))
+			ec_max_insize = insize;
+
+		ec_outbuf = realloc(ec_outbuf, ec_max_outsize);
+		ec_inbuf = realloc(ec_inbuf, ec_max_insize);
+
+		if (!ec_outbuf || !ec_inbuf) {
+			fprintf(stderr, "Unable to reallocate buffers\n");
+			return 1;
+		}
+	}
+
+	return 0;
+}
diff --git a/util/comm-host.h b/util/comm-host.h
index 309c97eeb5..0f07bb48f3 100644
--- a/util/comm-host.h
+++ b/util/comm-host.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -31,6 +31,7 @@ enum comm_interface {
 	COMM_LPC = BIT(1),
 	COMM_I2C = BIT(2),
 	COMM_SERVO = BIT(3),
+	COMM_USB = BIT(4),
 	COMM_ALL = -1
 };
 
@@ -51,6 +52,14 @@ int comm_init_alt(int interfaces, const char *device_name, int i2c_bus);
  */
 int comm_init_dev(const char *device_name);
 
+/**
+ * Get the file descriptor associated with the dev interface. comm_init_dev
+ * must be called first in order for the file descriptor to be valid.
+ *
+ * @return file descriptor
+ */
+int comm_get_fd(void);
+
 /**
  * Initialize input & output buffers
  *
@@ -62,9 +71,12 @@ int comm_init_buffer(void);
  * Send a command to the EC.  Returns the length of output data returned (0 if
  * none), or negative on error.
  */
-int ec_command(int command, int version,
-	       const void *outdata, int outsize,   /* to the EC */
-	       void *indata, int insize);	   /* from the EC */
+int ec_command(int command, int version, const void *outdata,
+	       int outsize, /* to
+			       the
+			       EC
+			     */
+	       void *indata, int insize); /* from the EC */
 
 /**
  * Set the offset to be applied to the command number when ec_command() calls
@@ -78,9 +90,9 @@ void set_command_offset(int offset);
  * by the protocol-specific driver.  DO NOT call this version directly from
  * anywhere but ec_command(), or the --device option will not work.
  */
-extern int (*ec_command_proto)(int command, int version,
-			       const void *outdata, int outsize, /* to EC */
-			       void *indata, int insize);        /* from EC */
+extern int (*ec_command_proto)(int command, int version, const void *outdata,
+			       int outsize, /* to EC */
+			       void *indata, int insize); /* from EC */
 
 /**
  * Return the content of the EC information area mapped as "memory".
diff --git a/util/comm-i2c.c b/util/comm-i2c.c
deleted file mode 100644
index d88454ee3b..0000000000
--- a/util/comm-i2c.c
+++ /dev/null
@@ -1,255 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#define _GNU_SOURCE /* for asprintf */
-
-#include <errno.h>
-#include <fcntl.h>
-#include <linux/i2c.h>
-#include <linux/i2c-dev.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/ioctl.h>
-#include <sys/stat.h>
-#include <sys/types.h>
-#include <unistd.h>
-
-#include "comm-host.h"
-#include "i2c.h"
-
-#define EC_I2C_ADDR 0x1e
-
-#define I2C_ADAPTER_NODE "/sys/class/i2c-adapter/i2c-%d/%d-%04x/name"
-#define I2C_ADAPTER_NAME "cros-ec-i2c"
-#define I2C_MAX_ADAPTER  32
-#define I2C_NODE "/dev/i2c-%d"
-
-#ifdef DEBUG
-#define debug(format, arg...) printf(format, ##arg)
-#else
-#define debug(...)
-#endif
-
-static int i2c_fd = -1;
-
-static int sum_bytes(const void *data, int length)
-{
-	const uint8_t *bytes = (const uint8_t *)data;
-	int sum = 0;
-	int i;
-
-	for (i = 0; i < length; i++)
-		sum += bytes[i];
-	return sum;
-}
-
-static void dump_buffer(const uint8_t *data, int length)
-{
-	int i;
-
-	for (i = 0; i < length; i++)
-		fprintf(stderr, "%02X ", data[i]);
-	fprintf(stderr, "\n");
-}
-
-/*
- * Sends a command to the EC (protocol v3). Returns the command status code
- * (>= 0), or a negative EC_RES_* value on error.
- */
-static int ec_command_i2c_3(int command, int version,
-			    const void *outdata, int outsize,
-			    void *indata, int insize)
-{
-	int ret = -EC_RES_ERROR;
-	int error;
-	int req_len, resp_len;
-	uint8_t *req_buf = NULL;
-	uint8_t *resp_buf = NULL;
-	struct ec_host_request *req;
-	struct ec_host_response *resp;
-	uint8_t command_return_code;
-	struct i2c_msg i2c_msg;
-	struct i2c_rdwr_ioctl_data data;
-
-	if (outsize > ec_max_outsize) {
-		fprintf(stderr, "Request is too large (%d > %d).\n", outsize,
-			ec_max_outsize);
-		return -EC_RES_ERROR;
-	}
-	if (insize > ec_max_insize) {
-		fprintf(stderr, "Response would be too large (%d > %d).\n",
-			insize, ec_max_insize);
-		return -EC_RES_ERROR;
-	}
-	req_len = I2C_REQUEST_HEADER_SIZE + sizeof(struct ec_host_request)
-		+ outsize;
-	req_buf = calloc(1, req_len);
-	if (!req_buf)
-		goto done;
-
-	req_buf[0] = EC_COMMAND_PROTOCOL_3;
-	req = (struct ec_host_request *)&req_buf[1];
-	req->struct_version = EC_HOST_REQUEST_VERSION;
-	req->checksum = 0;
-	req->command = command;
-	req->command_version = version;
-	req->reserved = 0;
-	req->data_len = outsize;
-
-	memcpy(&req_buf[I2C_REQUEST_HEADER_SIZE
-			+ sizeof(struct ec_host_request)],
-	       outdata, outsize);
-
-	req->checksum =
-		(uint8_t)(-sum_bytes(&req_buf[I2C_REQUEST_HEADER_SIZE],
-				     req_len - I2C_REQUEST_HEADER_SIZE));
-
-	i2c_msg.addr = EC_I2C_ADDR;
-	i2c_msg.flags = 0;
-	i2c_msg.len = req_len;
-	i2c_msg.buf = (char *)req_buf;
-
-	resp_len = I2C_RESPONSE_HEADER_SIZE + sizeof(struct ec_host_response)
-		+ insize;
-	resp_buf = calloc(1, resp_len);
-	if (!resp_buf)
-		goto done;
-	memset(resp_buf, 0, resp_len);
-
-	if (IS_ENABLED(DEBUG)) {
-		fprintf(stderr, "Sending: 0x");
-		dump_buffer(req_buf, req_len);
-	}
-
-	/*
-	 * Combining these two ioctls makes the write-read interval too short
-	 * for some chips (such as the MAX32660) to handle.
-	 */
-	data.msgs = &i2c_msg;
-	data.nmsgs = 1;
-	error = ioctl(i2c_fd, I2C_RDWR, &data);
-	if (error < 0) {
-		fprintf(stderr, "I2C write failed: %d (err: %d, %s)\n",
-			error, errno, strerror(errno));
-		goto done;
-	}
-
-	i2c_msg.addr = EC_I2C_ADDR;
-	i2c_msg.flags = I2C_M_RD;
-	i2c_msg.len = resp_len;
-	i2c_msg.buf = (char *)resp_buf;
-	error = ioctl(i2c_fd, I2C_RDWR, &data);
-	if (error < 0) {
-		fprintf(stderr, "I2C read failed: %d (err: %d, %s)\n",
-			error, errno, strerror(errno));
-		goto done;
-	}
-
-	if (IS_ENABLED(DEBUG)) {
-		fprintf(stderr, "Received: 0x");
-		dump_buffer(resp_buf, resp_len);
-	}
-
-	command_return_code = resp_buf[0];
-	if (command_return_code != EC_RES_SUCCESS) {
-		debug("command 0x%02x returned an error %d\n", command,
-		      command_return_code);
-		ret = -EECRESULT - command_return_code;
-		goto done;
-	}
-
-	if (resp_buf[1] > sizeof(struct ec_host_response) + insize) {
-		debug("EC returned too much data.\n");
-		ret = -EC_RES_RESPONSE_TOO_BIG;
-		goto done;
-	}
-
-	resp = (struct ec_host_response *)(&resp_buf[2]);
-	if (resp->struct_version != EC_HOST_RESPONSE_VERSION) {
-		debug("EC response version mismatch.\n");
-		ret = -EC_RES_INVALID_RESPONSE;
-		goto done;
-	}
-
-	if ((uint8_t)sum_bytes(&resp_buf[I2C_RESPONSE_HEADER_SIZE], resp_buf[1])
-			!= 0) {
-		debug("Bad checksum on EC response.\n");
-		ret = -EC_RES_INVALID_CHECKSUM;
-		goto done;
-	}
-
-	memcpy(indata, &resp_buf[I2C_RESPONSE_HEADER_SIZE
-				 + sizeof(struct ec_host_response)],
-	       insize);
-
-	ret = resp->data_len;
-done:
-	if (req_buf)
-		free(req_buf);
-	if (resp_buf)
-		free(resp_buf);
-
-	return ret;
-}
-
-int comm_init_i2c(int i2c_bus)
-{
-	char *file_path;
-	char buffer[64];
-	int i;
-
-	if (i2c_bus != -1) {
-		i = i2c_bus;
-
-		if (i >= I2C_MAX_ADAPTER) {
-			fprintf(stderr, "Invalid I2C bus number %d. (The highest possible bus number is %d.)\n",
-				i, I2C_MAX_ADAPTER);
-			return -1;
-		}
-	} else {
-		/* find the device number based on the adapter name */
-		for (i = 0; i < I2C_MAX_ADAPTER; i++) {
-			FILE *f;
-
-			if (asprintf(&file_path, I2C_ADAPTER_NODE,
-				     i, i, EC_I2C_ADDR) < 0)
-				return -1;
-			f = fopen(file_path, "r");
-			if (f) {
-				if (fgets(buffer, sizeof(buffer), f) &&
-				    !strncmp(buffer, I2C_ADAPTER_NAME, 6)) {
-					free(file_path);
-					fclose(f);
-					break;
-				}
-				fclose(f);
-			}
-			free(file_path);
-		}
-		if (i == I2C_MAX_ADAPTER) {
-			fprintf(stderr, "Cannot find I2C adapter\n");
-			return -1;
-		}
-	}
-
-	if (asprintf(&file_path, I2C_NODE, i) < 0)
-		return -1;
-	debug("using I2C adapter %s\n", file_path);
-	i2c_fd = open(file_path, O_RDWR);
-	if (i2c_fd < 0)
-		fprintf(stderr, "Cannot open %s : %d\n", file_path, errno);
-
-	free(file_path);
-
-	ec_command_proto = ec_command_i2c_3;
-	ec_max_outsize = I2C_MAX_HOST_PACKET_SIZE - I2C_REQUEST_HEADER_SIZE
-		- sizeof(struct ec_host_request);
-	ec_max_insize = I2C_MAX_HOST_PACKET_SIZE - I2C_RESPONSE_HEADER_SIZE
-		- sizeof(struct ec_host_response);
-
-	return 0;
-}
diff --git a/util/comm-i2c.cc b/util/comm-i2c.cc
new file mode 100644
index 0000000000..9b5d6e958c
--- /dev/null
+++ b/util/comm-i2c.cc
@@ -0,0 +1,259 @@
+/* Copyright 2012 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _GNU_SOURCE
+#define _GNU_SOURCE /* for asprintf */
+#endif
+
+#include "comm-host.h"
+#include "i2c.h"
+
+#include <errno.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <fcntl.h>
+#include <linux/i2c-dev.h>
+#include <linux/i2c.h>
+#include <sys/ioctl.h>
+#include <sys/stat.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+#define EC_I2C_ADDR 0x1e
+
+#define I2C_ADAPTER_NODE "/sys/class/i2c-adapter/i2c-%d/%d-%04x/name"
+#define I2C_ADAPTER_NAME "cros-ec-i2c"
+#define I2C_MAX_ADAPTER 32
+#define I2C_NODE "/dev/i2c-%d"
+
+#ifdef DEBUG
+#define debug(format, arg...) printf(format, ##arg)
+#else
+#define debug(...)
+#endif
+
+static int i2c_fd = -1;
+
+static int sum_bytes(const void *data, int length)
+{
+	const uint8_t *bytes = (const uint8_t *)data;
+	int sum = 0;
+	int i;
+
+	for (i = 0; i < length; i++)
+		sum += bytes[i];
+	return sum;
+}
+
+static void dump_buffer(const uint8_t *data, int length)
+{
+	int i;
+
+	for (i = 0; i < length; i++)
+		fprintf(stderr, "%02X ", data[i]);
+	fprintf(stderr, "\n");
+}
+
+/*
+ * Sends a command to the EC (protocol v3). Returns the command status code
+ * (>= 0), or a negative EC_RES_* value on error.
+ */
+static int ec_command_i2c_3(int command, int version, const void *outdata,
+			    int outsize, void *indata, int insize)
+{
+	int ret = -EC_RES_ERROR;
+	int error;
+	int req_len, resp_len;
+	uint8_t *req_buf = NULL;
+	uint8_t *resp_buf = NULL;
+	struct ec_host_request *req;
+	struct ec_host_response *resp;
+	uint8_t command_return_code;
+	struct i2c_msg i2c_msg;
+	struct i2c_rdwr_ioctl_data data;
+
+	if (outsize > ec_max_outsize) {
+		fprintf(stderr, "Request is too large (%d > %d).\n", outsize,
+			ec_max_outsize);
+		return -EC_RES_ERROR;
+	}
+	if (insize > ec_max_insize) {
+		fprintf(stderr, "Response would be too large (%d > %d).\n",
+			insize, ec_max_insize);
+		return -EC_RES_ERROR;
+	}
+	req_len = I2C_REQUEST_HEADER_SIZE + sizeof(struct ec_host_request) +
+		  outsize;
+	req_buf = (uint8_t *)(calloc(1, req_len));
+	if (!req_buf)
+		goto done;
+
+	req_buf[0] = EC_COMMAND_PROTOCOL_3;
+	req = (struct ec_host_request *)&req_buf[1];
+	req->struct_version = EC_HOST_REQUEST_VERSION;
+	req->checksum = 0;
+	req->command = command;
+	req->command_version = version;
+	req->reserved = 0;
+	req->data_len = outsize;
+
+	memcpy(&req_buf[I2C_REQUEST_HEADER_SIZE +
+			sizeof(struct ec_host_request)],
+	       outdata, outsize);
+
+	req->checksum =
+		(uint8_t)(-sum_bytes(&req_buf[I2C_REQUEST_HEADER_SIZE],
+				     req_len - I2C_REQUEST_HEADER_SIZE));
+
+	i2c_msg.addr = EC_I2C_ADDR;
+	i2c_msg.flags = 0;
+	i2c_msg.len = req_len;
+	i2c_msg.buf = req_buf;
+
+	resp_len = I2C_RESPONSE_HEADER_SIZE + sizeof(struct ec_host_response) +
+		   insize;
+	resp_buf = (uint8_t *)(calloc(1, resp_len));
+	if (!resp_buf)
+		goto done;
+	memset(resp_buf, 0, resp_len);
+
+	if (IS_ENABLED(DEBUG)) {
+		fprintf(stderr, "Sending: 0x");
+		dump_buffer(req_buf, req_len);
+	}
+
+	/*
+	 * Combining these two ioctls makes the write-read interval too short
+	 * for some chips (such as the MAX32660) to handle.
+	 */
+	data.msgs = &i2c_msg;
+	data.nmsgs = 1;
+	error = ioctl(i2c_fd, I2C_RDWR, &data);
+	if (error < 0) {
+		fprintf(stderr, "I2C write failed: %d (err: %d, %s)\n", error,
+			errno, strerror(errno));
+		goto done;
+	}
+
+	i2c_msg.addr = EC_I2C_ADDR;
+	i2c_msg.flags = I2C_M_RD;
+	i2c_msg.len = resp_len;
+	i2c_msg.buf = resp_buf;
+	error = ioctl(i2c_fd, I2C_RDWR, &data);
+	if (error < 0) {
+		fprintf(stderr, "I2C read failed: %d (err: %d, %s)\n", error,
+			errno, strerror(errno));
+		goto done;
+	}
+
+	if (IS_ENABLED(DEBUG)) {
+		fprintf(stderr, "Received: 0x");
+		dump_buffer(resp_buf, resp_len);
+	}
+
+	command_return_code = resp_buf[0];
+	if (command_return_code != EC_RES_SUCCESS) {
+		debug("command 0x%02x returned an error %d\n", command,
+		      command_return_code);
+		ret = -EECRESULT - command_return_code;
+		goto done;
+	}
+
+	if (resp_buf[1] > sizeof(struct ec_host_response) + insize) {
+		debug("EC returned too much data.\n");
+		ret = -EC_RES_RESPONSE_TOO_BIG;
+		goto done;
+	}
+
+	resp = (struct ec_host_response *)(&resp_buf[2]);
+	if (resp->struct_version != EC_HOST_RESPONSE_VERSION) {
+		debug("EC response version mismatch.\n");
+		ret = -EC_RES_INVALID_RESPONSE;
+		goto done;
+	}
+
+	if ((uint8_t)sum_bytes(&resp_buf[I2C_RESPONSE_HEADER_SIZE],
+			       resp_buf[1]) != 0) {
+		debug("Bad checksum on EC response.\n");
+		ret = -EC_RES_INVALID_CHECKSUM;
+		goto done;
+	}
+
+	memcpy(indata,
+	       &resp_buf[I2C_RESPONSE_HEADER_SIZE +
+			 sizeof(struct ec_host_response)],
+	       insize);
+
+	ret = resp->data_len;
+done:
+	if (req_buf)
+		free(req_buf);
+	if (resp_buf)
+		free(resp_buf);
+
+	return ret;
+}
+
+int comm_init_i2c(int i2c_bus)
+{
+	char *file_path;
+	char buffer[64];
+	int i;
+
+	if (i2c_bus != -1) {
+		i = i2c_bus;
+
+		if (i >= I2C_MAX_ADAPTER) {
+			fprintf(stderr,
+				"Invalid I2C bus number %d. (The highest possible bus number is %d.)\n",
+				i, I2C_MAX_ADAPTER);
+			return -1;
+		}
+	} else {
+		/* find the device number based on the adapter name */
+		for (i = 0; i < I2C_MAX_ADAPTER; i++) {
+			FILE *f;
+
+			if (asprintf(&file_path, I2C_ADAPTER_NODE, i, i,
+				     EC_I2C_ADDR) < 0)
+				return -1;
+			f = fopen(file_path, "r");
+			if (f) {
+				if (fgets(buffer, sizeof(buffer), f) &&
+				    !strncmp(buffer, I2C_ADAPTER_NAME, 6)) {
+					free(file_path);
+					fclose(f);
+					break;
+				}
+				fclose(f);
+			}
+			free(file_path);
+		}
+		if (i == I2C_MAX_ADAPTER) {
+			fprintf(stderr, "Cannot find I2C adapter\n");
+			return -1;
+		}
+	}
+
+	if (asprintf(&file_path, I2C_NODE, i) < 0)
+		return -1;
+	debug("using I2C adapter %s\n", file_path);
+	i2c_fd = open(file_path, O_RDWR);
+	if (i2c_fd < 0)
+		fprintf(stderr, "Cannot open %s : %d\n", file_path, errno);
+
+	free(file_path);
+
+	ec_command_proto = ec_command_i2c_3;
+	ec_max_outsize = I2C_MAX_HOST_PACKET_SIZE - I2C_REQUEST_HEADER_SIZE -
+			 sizeof(struct ec_host_request);
+	ec_max_insize = I2C_MAX_HOST_PACKET_SIZE - I2C_RESPONSE_HEADER_SIZE -
+			sizeof(struct ec_host_response);
+
+	return 0;
+}
diff --git a/util/comm-lpc.c b/util/comm-lpc.c
deleted file mode 100644
index a3a8f64ff7..0000000000
--- a/util/comm-lpc.c
+++ /dev/null
@@ -1,316 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* The I/O asm funcs exist only on x86. */
-#if defined(__i386__) || defined(__x86_64__)
-
-#include <stdint.h>
-#include <stdio.h>
-#include <sys/io.h>
-#include <sys/param.h>
-#include <unistd.h>
-
-#include "comm-host.h"
-
-#define INITIAL_UDELAY 5     /* 5 us */
-#define MAXIMUM_UDELAY 10000 /* 10 ms */
-
-/*
- * Wait for the EC to be unbusy.  Returns 0 if unbusy, non-zero if
- * timeout.
- */
-static int wait_for_ec(int status_addr, int timeout_usec)
-{
-	int i;
-	int delay = INITIAL_UDELAY;
-
-	for (i = 0; i < timeout_usec; i += delay) {
-		/*
-		 * Delay first, in case we just sent out a command but the EC
-		 * hasn't raised the busy flag.  However, I think this doesn't
-		 * happen since the LPC commands are executed in order and the
-		 * busy flag is set by hardware.  Minor issue in any case,
-		 * since the initial delay is very short.
-		 */
-		usleep(MIN(delay, timeout_usec - i));
-
-		if (!(inb(status_addr) & EC_LPC_STATUS_BUSY_MASK))
-			return 0;
-
-		/* Increase the delay interval after a few rapid checks */
-		if (i > 20)
-			delay = MIN(delay * 2, MAXIMUM_UDELAY);
-	}
-	return -1;  /* Timeout */
-}
-
-static int ec_command_lpc(int command, int version,
-			  const void *outdata, int outsize,
-			  void *indata, int insize)
-{
-	struct ec_lpc_host_args args;
-	const uint8_t *d;
-	uint8_t *dout;
-	int csum;
-	int i;
-
-	/* Fill in args */
-	args.flags = EC_HOST_ARGS_FLAG_FROM_HOST;
-	args.command_version = version;
-	args.data_size = outsize;
-
-	/* Initialize checksum */
-	csum = command + args.flags + args.command_version + args.data_size;
-
-	/* Write data and update checksum */
-	for (i = 0, d = (uint8_t *)outdata; i < outsize; i++, d++) {
-		outb(*d, EC_LPC_ADDR_HOST_PARAM + i);
-		csum += *d;
-	}
-
-	/* Finalize checksum and write args */
-	args.checksum = (uint8_t)csum;
-	for (i = 0, d = (const uint8_t *)&args; i < sizeof(args); i++, d++)
-		outb(*d, EC_LPC_ADDR_HOST_ARGS + i);
-
-	outb(command, EC_LPC_ADDR_HOST_CMD);
-
-	if (wait_for_ec(EC_LPC_ADDR_HOST_CMD, 1000000)) {
-		fprintf(stderr, "Timeout waiting for EC response\n");
-		return -EC_RES_ERROR;
-	}
-
-	/* Check result */
-	i = inb(EC_LPC_ADDR_HOST_DATA);
-	if (i) {
-		fprintf(stderr, "EC returned error result code %d\n", i);
-		return -EECRESULT - i;
-	}
-
-	/* Read back args */
-	for (i = 0, dout = (uint8_t *)&args; i < sizeof(args); i++, dout++)
-		*dout = inb(EC_LPC_ADDR_HOST_ARGS + i);
-
-	/*
-	 * If EC didn't modify args flags, then somehow we sent a new-style
-	 * command to an old EC, which means it would have read its params
-	 * from the wrong place.
-	 */
-	if (!(args.flags & EC_HOST_ARGS_FLAG_TO_HOST)) {
-		fprintf(stderr, "EC protocol mismatch\n");
-		return -EC_RES_INVALID_RESPONSE;
-	}
-
-	if (args.data_size > insize) {
-		fprintf(stderr, "EC returned too much data\n");
-		return -EC_RES_INVALID_RESPONSE;
-	}
-
-	/* Start calculating response checksum */
-	csum = command + args.flags + args.command_version + args.data_size;
-
-	/* Read response and update checksum */
-	for (i = 0, dout = (uint8_t *)indata; i < args.data_size;
-	     i++, dout++) {
-		*dout = inb(EC_LPC_ADDR_HOST_PARAM + i);
-		csum += *dout;
-	}
-
-	/* Verify checksum */
-	if (args.checksum != (uint8_t)csum) {
-		fprintf(stderr, "EC response has invalid checksum\n");
-		return -EC_RES_INVALID_CHECKSUM;
-	}
-
-	/* Return actual amount of data received */
-	return args.data_size;
-}
-
-static int ec_command_lpc_3(int command, int version,
-			  const void *outdata, int outsize,
-			  void *indata, int insize)
-{
-	struct ec_host_request rq;
-	struct ec_host_response rs;
-	const uint8_t *d;
-	uint8_t *dout;
-	int csum = 0;
-	int i;
-
-	/* Fail if output size is too big */
-	if (outsize + sizeof(rq) > EC_LPC_HOST_PACKET_SIZE)
-		return -EC_RES_REQUEST_TRUNCATED;
-
-	/* Fill in request packet */
-	/* TODO(crosbug.com/p/23825): This should be common to all protocols */
-	rq.struct_version = EC_HOST_REQUEST_VERSION;
-	rq.checksum = 0;
-	rq.command = command;
-	rq.command_version = version;
-	rq.reserved = 0;
-	rq.data_len = outsize;
-
-	/* Copy data and start checksum */
-	for (i = 0, d = (const uint8_t *)outdata; i < outsize; i++, d++) {
-		outb(*d, EC_LPC_ADDR_HOST_PACKET + sizeof(rq) + i);
-		csum += *d;
-	}
-
-	/* Finish checksum */
-	for (i = 0, d = (const uint8_t *)&rq; i < sizeof(rq); i++, d++)
-		csum += *d;
-
-	/* Write checksum field so the entire packet sums to 0 */
-	rq.checksum = (uint8_t)(-csum);
-
-	/* Copy header */
-	for (i = 0, d = (const uint8_t *)&rq; i < sizeof(rq); i++, d++)
-		outb(*d, EC_LPC_ADDR_HOST_PACKET + i);
-
-	/* Start the command */
-	outb(EC_COMMAND_PROTOCOL_3, EC_LPC_ADDR_HOST_CMD);
-
-	if (wait_for_ec(EC_LPC_ADDR_HOST_CMD, 1000000)) {
-		fprintf(stderr, "Timeout waiting for EC response\n");
-		return -EC_RES_ERROR;
-	}
-
-	/* Check result */
-	i = inb(EC_LPC_ADDR_HOST_DATA);
-	if (i) {
-		fprintf(stderr, "EC returned error result code %d\n", i);
-		return -EECRESULT - i;
-	}
-
-	/* Read back response header and start checksum */
-	csum = 0;
-	for (i = 0, dout = (uint8_t *)&rs; i < sizeof(rs); i++, dout++) {
-		*dout = inb(EC_LPC_ADDR_HOST_PACKET + i);
-		csum += *dout;
-	}
-
-	if (rs.struct_version != EC_HOST_RESPONSE_VERSION) {
-		fprintf(stderr, "EC response version mismatch\n");
-		return -EC_RES_INVALID_RESPONSE;
-	}
-
-	if (rs.reserved) {
-		fprintf(stderr, "EC response reserved != 0\n");
-		return -EC_RES_INVALID_RESPONSE;
-	}
-
-	if (rs.data_len > insize) {
-		fprintf(stderr, "EC returned too much data\n");
-		return -EC_RES_RESPONSE_TOO_BIG;
-	}
-
-	/* Read back data and update checksum */
-	for (i = 0, dout = (uint8_t *)indata; i < rs.data_len; i++, dout++) {
-		*dout = inb(EC_LPC_ADDR_HOST_PACKET + sizeof(rs) + i);
-		csum += *dout;
-	}
-
-	/* Verify checksum */
-	if ((uint8_t)csum) {
-		fprintf(stderr, "EC response has invalid checksum\n");
-		return -EC_RES_INVALID_CHECKSUM;
-	}
-
-	/* Return actual amount of data received */
-	return rs.data_len;
-}
-
-static int ec_readmem_lpc(int offset, int bytes, void *dest)
-{
-	int i = offset;
-	char *s = dest;
-	int cnt = 0;
-
-	if (offset >= EC_MEMMAP_SIZE - bytes)
-		return -1;
-
-	if (bytes) {				/* fixed length */
-		for (; cnt < bytes; i++, s++, cnt++)
-			*s = inb(EC_LPC_ADDR_MEMMAP + i);
-	} else {				/* string */
-		for (; i < EC_MEMMAP_SIZE; i++, s++) {
-			*s = inb(EC_LPC_ADDR_MEMMAP + i);
-			cnt++;
-			if (!*s)
-				break;
-		}
-	}
-
-	return cnt;
-}
-
-int comm_init_lpc(void)
-{
-	int i;
-	int byte = 0xff;
-
-	/* Request I/O privilege */
-	if (iopl(3) < 0) {
-		perror("Error getting I/O privilege");
-		return -3;
-	}
-
-	/*
-	 * Test if the I/O port has been configured for Chromium EC LPC
-	 * interface.  Chromium EC guarantees that at least one status bit will
-	 * be 0, so if the command and data bytes are both 0xff, very likely
-	 * that Chromium EC is not present.  See crosbug.com/p/10963.
-	 */
-	byte &= inb(EC_LPC_ADDR_HOST_CMD);
-	byte &= inb(EC_LPC_ADDR_HOST_DATA);
-	if (byte == 0xff) {
-		fprintf(stderr, "Port 0x%x,0x%x are both 0xFF.\n",
-			EC_LPC_ADDR_HOST_CMD, EC_LPC_ADDR_HOST_DATA);
-		fprintf(stderr,
-			"Very likely this board doesn't have a Chromium EC.\n");
-		return -4;
-	}
-
-	/*
-	 * Test if LPC command args are supported.
-	 *
-	 * The cheapest way to do this is by looking for the memory-mapped
-	 * flag.  This is faster than sending a new-style 'hello' command and
-	 * seeing whether the EC sets the EC_HOST_ARGS_FLAG_FROM_HOST flag
-	 * in args when it responds.
-	 */
-	if (inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_ID) != 'E' ||
-	    inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_ID + 1) != 'C') {
-		fprintf(stderr, "Missing Chromium EC memory map.\n");
-		return -5;
-	}
-
-	/* Check which command version we'll use */
-	i = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_HOST_CMD_FLAGS);
-
-	if (i & EC_HOST_CMD_FLAG_VERSION_3) {
-		/* Protocol version 3 */
-		ec_command_proto = ec_command_lpc_3;
-		ec_max_outsize = EC_LPC_HOST_PACKET_SIZE -
-			sizeof(struct ec_host_request);
-		ec_max_insize = EC_LPC_HOST_PACKET_SIZE -
-			sizeof(struct ec_host_response);
-
-	} else if (i & EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED) {
-		/* Protocol version 2 */
-		ec_command_proto = ec_command_lpc;
-		ec_max_outsize = ec_max_insize = EC_PROTO2_MAX_PARAM_SIZE;
-
-	} else {
-		fprintf(stderr, "EC doesn't support protocols we need.\n");
-		return -5;
-	}
-
-	/* Either one supports reading mapped memory directly. */
-	ec_readmem = ec_readmem_lpc;
-	return 0;
-}
-
-#endif
diff --git a/util/comm-lpc.cc b/util/comm-lpc.cc
new file mode 100644
index 0000000000..a7d22d9a21
--- /dev/null
+++ b/util/comm-lpc.cc
@@ -0,0 +1,314 @@
+/* Copyright 2013 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* The I/O asm funcs exist only on x86. */
+#if defined(__i386__) || defined(__x86_64__)
+
+#include "comm-host.h"
+
+#include <stdint.h>
+#include <stdio.h>
+
+#include <sys/io.h>
+#include <sys/param.h>
+#include <unistd.h>
+
+#define INITIAL_UDELAY 5 /* 5 us */
+#define MAXIMUM_UDELAY 10000 /* 10 ms */
+
+/*
+ * Wait for the EC to be unbusy.  Returns 0 if unbusy, non-zero if
+ * timeout.
+ */
+static int wait_for_ec(int status_addr, int timeout_usec)
+{
+	int i;
+	int delay = INITIAL_UDELAY;
+
+	for (i = 0; i < timeout_usec; i += delay) {
+		/*
+		 * Delay first, in case we just sent out a command but the EC
+		 * hasn't raised the busy flag.  However, I think this doesn't
+		 * happen since the LPC commands are executed in order and the
+		 * busy flag is set by hardware.  Minor issue in any case,
+		 * since the initial delay is very short.
+		 */
+		usleep(MIN(delay, timeout_usec - i));
+
+		if (!(inb(status_addr) & EC_LPC_STATUS_BUSY_MASK))
+			return 0;
+
+		/* Increase the delay interval after a few rapid checks */
+		if (i > 20)
+			delay = MIN(delay * 2, MAXIMUM_UDELAY);
+	}
+	return -1; /* Timeout */
+}
+
+static int ec_command_lpc(int command, int version, const void *outdata,
+			  int outsize, void *indata, int insize)
+{
+	struct ec_lpc_host_args args;
+	const uint8_t *d;
+	uint8_t *dout;
+	int csum;
+	int i;
+
+	/* Fill in args */
+	args.flags = EC_HOST_ARGS_FLAG_FROM_HOST;
+	args.command_version = version;
+	args.data_size = outsize;
+
+	/* Initialize checksum */
+	csum = command + args.flags + args.command_version + args.data_size;
+
+	/* Write data and update checksum */
+	for (i = 0, d = (uint8_t *)outdata; i < outsize; i++, d++) {
+		outb(*d, EC_LPC_ADDR_HOST_PARAM + i);
+		csum += *d;
+	}
+
+	/* Finalize checksum and write args */
+	args.checksum = (uint8_t)csum;
+	for (i = 0, d = (const uint8_t *)&args; i < sizeof(args); i++, d++)
+		outb(*d, EC_LPC_ADDR_HOST_ARGS + i);
+
+	outb(command, EC_LPC_ADDR_HOST_CMD);
+
+	if (wait_for_ec(EC_LPC_ADDR_HOST_CMD, 1000000)) {
+		fprintf(stderr, "Timeout waiting for EC response\n");
+		return -EC_RES_ERROR;
+	}
+
+	/* Check result */
+	i = inb(EC_LPC_ADDR_HOST_DATA);
+	if (i) {
+		fprintf(stderr, "EC returned error result code %d\n", i);
+		return -EECRESULT - i;
+	}
+
+	/* Read back args */
+	for (i = 0, dout = (uint8_t *)&args; i < sizeof(args); i++, dout++)
+		*dout = inb(EC_LPC_ADDR_HOST_ARGS + i);
+
+	/*
+	 * If EC didn't modify args flags, then somehow we sent a new-style
+	 * command to an old EC, which means it would have read its params
+	 * from the wrong place.
+	 */
+	if (!(args.flags & EC_HOST_ARGS_FLAG_TO_HOST)) {
+		fprintf(stderr, "EC protocol mismatch\n");
+		return -EC_RES_INVALID_RESPONSE;
+	}
+
+	if (args.data_size > insize) {
+		fprintf(stderr, "EC returned too much data\n");
+		return -EC_RES_INVALID_RESPONSE;
+	}
+
+	/* Start calculating response checksum */
+	csum = command + args.flags + args.command_version + args.data_size;
+
+	/* Read response and update checksum */
+	for (i = 0, dout = (uint8_t *)indata; i < args.data_size; i++, dout++) {
+		*dout = inb(EC_LPC_ADDR_HOST_PARAM + i);
+		csum += *dout;
+	}
+
+	/* Verify checksum */
+	if (args.checksum != (uint8_t)csum) {
+		fprintf(stderr, "EC response has invalid checksum\n");
+		return -EC_RES_INVALID_CHECKSUM;
+	}
+
+	/* Return actual amount of data received */
+	return args.data_size;
+}
+
+static int ec_command_lpc_3(int command, int version, const void *outdata,
+			    int outsize, void *indata, int insize)
+{
+	struct ec_host_request rq;
+	struct ec_host_response rs;
+	const uint8_t *d;
+	uint8_t *dout;
+	int csum = 0;
+	int i;
+
+	/* Fail if output size is too big */
+	if (outsize + sizeof(rq) > EC_LPC_HOST_PACKET_SIZE)
+		return -EC_RES_REQUEST_TRUNCATED;
+
+	/* Fill in request packet */
+	/* TODO(crosbug.com/p/23825): This should be common to all protocols */
+	rq.struct_version = EC_HOST_REQUEST_VERSION;
+	rq.checksum = 0;
+	rq.command = command;
+	rq.command_version = version;
+	rq.reserved = 0;
+	rq.data_len = outsize;
+
+	/* Copy data and start checksum */
+	for (i = 0, d = (const uint8_t *)outdata; i < outsize; i++, d++) {
+		outb(*d, EC_LPC_ADDR_HOST_PACKET + sizeof(rq) + i);
+		csum += *d;
+	}
+
+	/* Finish checksum */
+	for (i = 0, d = (const uint8_t *)&rq; i < sizeof(rq); i++, d++)
+		csum += *d;
+
+	/* Write checksum field so the entire packet sums to 0 */
+	rq.checksum = (uint8_t)(-csum);
+
+	/* Copy header */
+	for (i = 0, d = (const uint8_t *)&rq; i < sizeof(rq); i++, d++)
+		outb(*d, EC_LPC_ADDR_HOST_PACKET + i);
+
+	/* Start the command */
+	outb(EC_COMMAND_PROTOCOL_3, EC_LPC_ADDR_HOST_CMD);
+
+	if (wait_for_ec(EC_LPC_ADDR_HOST_CMD, 1000000)) {
+		fprintf(stderr, "Timeout waiting for EC response\n");
+		return -EC_RES_ERROR;
+	}
+
+	/* Check result */
+	i = inb(EC_LPC_ADDR_HOST_DATA);
+	if (i) {
+		fprintf(stderr, "EC returned error result code %d\n", i);
+		return -EECRESULT - i;
+	}
+
+	/* Read back response header and start checksum */
+	csum = 0;
+	for (i = 0, dout = (uint8_t *)&rs; i < sizeof(rs); i++, dout++) {
+		*dout = inb(EC_LPC_ADDR_HOST_PACKET + i);
+		csum += *dout;
+	}
+
+	if (rs.struct_version != EC_HOST_RESPONSE_VERSION) {
+		fprintf(stderr, "EC response version mismatch\n");
+		return -EC_RES_INVALID_RESPONSE;
+	}
+
+	if (rs.reserved) {
+		fprintf(stderr, "EC response reserved != 0\n");
+		return -EC_RES_INVALID_RESPONSE;
+	}
+
+	if (rs.data_len > insize) {
+		fprintf(stderr, "EC returned too much data\n");
+		return -EC_RES_RESPONSE_TOO_BIG;
+	}
+
+	/* Read back data and update checksum */
+	for (i = 0, dout = (uint8_t *)indata; i < rs.data_len; i++, dout++) {
+		*dout = inb(EC_LPC_ADDR_HOST_PACKET + sizeof(rs) + i);
+		csum += *dout;
+	}
+
+	/* Verify checksum */
+	if ((uint8_t)csum) {
+		fprintf(stderr, "EC response has invalid checksum\n");
+		return -EC_RES_INVALID_CHECKSUM;
+	}
+
+	/* Return actual amount of data received */
+	return rs.data_len;
+}
+
+static int ec_readmem_lpc(int offset, int bytes, void *dest)
+{
+	int i = offset;
+	char *s = (char *)(dest);
+	int cnt = 0;
+
+	if (offset >= EC_MEMMAP_SIZE - bytes)
+		return -1;
+
+	if (bytes) { /* fixed length */
+		for (; cnt < bytes; i++, s++, cnt++)
+			*s = inb(EC_LPC_ADDR_MEMMAP + i);
+	} else { /* string */
+		for (; i < EC_MEMMAP_SIZE; i++, s++) {
+			*s = inb(EC_LPC_ADDR_MEMMAP + i);
+			cnt++;
+			if (!*s)
+				break;
+		}
+	}
+
+	return cnt;
+}
+
+int comm_init_lpc(void)
+{
+	int i;
+	int byte = 0xff;
+
+	/* Request I/O privilege */
+	if (iopl(3) < 0) {
+		perror("Error getting I/O privilege");
+		return -3;
+	}
+
+	/*
+	 * Test if the I/O port has been configured for Chromium EC LPC
+	 * interface.  Chromium EC guarantees that at least one status bit will
+	 * be 0, so if the command and data bytes are both 0xff, very likely
+	 * that Chromium EC is not present.  See crosbug.com/p/10963.
+	 */
+	byte &= inb(EC_LPC_ADDR_HOST_CMD);
+	byte &= inb(EC_LPC_ADDR_HOST_DATA);
+	if (byte == 0xff) {
+		fprintf(stderr, "Port 0x%x,0x%x are both 0xFF.\n",
+			EC_LPC_ADDR_HOST_CMD, EC_LPC_ADDR_HOST_DATA);
+		fprintf(stderr,
+			"Very likely this board doesn't have a Chromium EC.\n");
+		return -4;
+	}
+
+	/*
+	 * Test if LPC command args are supported.
+	 *
+	 * The cheapest way to do this is by looking for the memory-mapped
+	 * flag.  This is faster than sending a new-style 'hello' command and
+	 * seeing whether the EC sets the EC_HOST_ARGS_FLAG_FROM_HOST flag
+	 * in args when it responds.
+	 */
+	if (inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_ID) != 'E' ||
+	    inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_ID + 1) != 'C') {
+		fprintf(stderr, "Missing Chromium EC memory map.\n");
+		return -5;
+	}
+
+	/* Check which command version we'll use */
+	i = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_HOST_CMD_FLAGS);
+
+	if (i & EC_HOST_CMD_FLAG_VERSION_3) {
+		/* Protocol version 3 */
+		ec_command_proto = ec_command_lpc_3;
+		ec_max_outsize = EC_LPC_HOST_PACKET_SIZE -
+				 sizeof(struct ec_host_request);
+		ec_max_insize = EC_LPC_HOST_PACKET_SIZE -
+				sizeof(struct ec_host_response);
+
+	} else if (i & EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED) {
+		/* Protocol version 2 */
+		ec_command_proto = ec_command_lpc;
+		ec_max_outsize = ec_max_insize = EC_PROTO2_MAX_PARAM_SIZE;
+
+	} else {
+		fprintf(stderr, "EC doesn't support protocols we need.\n");
+		return -5;
+	}
+
+	/* Either one supports reading mapped memory directly. */
+	ec_readmem = ec_readmem_lpc;
+	return 0;
+}
+
+#endif
diff --git a/util/comm-servo-spi.c b/util/comm-servo-spi.c
deleted file mode 100644
index 4010d2ec64..0000000000
--- a/util/comm-servo-spi.c
+++ /dev/null
@@ -1,357 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/*
- * Transport using the Servo V2 SPI1 interface through the FT4232 MPSSE
- * hardware engine (driven by libftdi) in order to send host commands V3
- * directly to a MCU slave SPI controller.
- *
- * It allows to drive a MCU with the cros_ec host SPI interface directly from
- * a developer workstation or another test system.
- *
- * The USB serial number of the servo board can be passed in the 'name'
- * parameter, e.g. :
- * sudo ectool_servo --name=905537-00474 version
- */
-
-#include <errno.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <time.h>
-#include <unistd.h>
-
-#include <libftdi1/ftdi.h>
-
-#include "comm-host.h"
-#include "cros_ec_dev.h"
-
-/* Servo V2 SPI1 interface identifiers */
-#define SERVO_V2_USB_VID 0x18d1
-#define SERVO_V2_USB_PID 0x5003
-#define SERVO_V2_USB_SPI1_INTERFACE INTERFACE_B
-
-/* SPI clock frequency in Hz */
-#define SPI_CLOCK_FREQ 1000000
-
-#define FTDI_LATENCY_1MS 2
-
-/* Timeout when waiting for the EC answer to our request */
-#define RESP_TIMEOUT 2 /* second */
-
-#ifdef DEBUG
-#define debug(format, arg...) printf(format, ##arg)
-#else
-#define debug(...)
-#endif
-
-/* Communication context */
-static struct ftdi_context ftdi;
-
-/* Size of a MPSSE command packet */
-#define MPSSE_CMD_SIZE 3
-
-enum mpsse_commands {
-	ENABLE_ADAPTIVE_CLOCK = 0x96,
-	DISABLE_ADAPTIVE_CLOCK = 0x97,
-	TCK_X5 = 0x8A,
-	TCK_D5 = 0x8B,
-	TRISTATE_IO = 0x9E,
-};
-
-enum mpsse_pins {
-	SCLK = 1,
-	MOSI = 2,
-	MISO = 4,
-	CS_L = 8,
-};
-/* SCLK/MOSI/CS_L are outputs, MISO is an input */
-#define PINS_DIR (SCLK | MOSI | CS_L)
-
-/* SPI mode 0:
- * propagates data on the falling edge
- * and reads data on the rising edge of the clock.
- */
-#define SPI_CMD_TX   (MPSSE_DO_WRITE | MPSSE_WRITE_NEG)
-#define SPI_CMD_RX   (MPSSE_DO_READ)
-#define SPI_CMD_TXRX (MPSSE_DO_WRITE | MPSSE_DO_READ | MPSSE_WRITE_NEG)
-
-static int raw_read(uint8_t *buf, int size)
-{
-	int rlen;
-
-	while (size) {
-		rlen = ftdi_read_data(&ftdi, buf, size);
-		if (rlen < 0)
-			break;
-		buf += rlen;
-		size -= rlen;
-	}
-	return !!size;
-}
-
-static int mpsse_set_pins(uint8_t levels)
-{
-	uint8_t buf[MPSSE_CMD_SIZE] = {0};
-
-	buf[0] = SET_BITS_LOW;
-	buf[1] = levels;
-	buf[2] = PINS_DIR;
-
-	return ftdi_write_data(&ftdi, buf, sizeof(buf)) != sizeof(buf);
-}
-
-static int send_request(int cmd, int version,
-			const uint8_t *outdata, size_t outsize)
-{
-	uint8_t *txbuf;
-	struct ec_host_request *request;
-	size_t i;
-	int ret = -EC_RES_ERROR;
-	uint8_t csum = 0;
-	size_t block_size = sizeof(struct ec_host_request) + outsize;
-	size_t total_len = MPSSE_CMD_SIZE + block_size;
-
-	txbuf = calloc(1, total_len);
-	if (!txbuf)
-		return -ENOMEM;
-
-	/* MPSSE block size is the full command minus 1 byte */
-	txbuf[0] = SPI_CMD_TXRX;
-	txbuf[1] = ((block_size - 1) & 0xFF);
-	txbuf[2] = (((block_size - 1) >> 8) & 0xFF);
-
-	/* Command header first */
-	request = (struct ec_host_request *)(txbuf + MPSSE_CMD_SIZE);
-	request->struct_version = EC_HOST_REQUEST_VERSION;
-	request->checksum = 0;
-	request->command = cmd;
-	request->command_version = version;
-	request->reserved = 0;
-	request->data_len = outsize;
-
-	/* copy the data to transmit after the command header */
-	memcpy(txbuf + MPSSE_CMD_SIZE + sizeof(struct ec_host_request),
-	       outdata, outsize);
-
-	/* Compute the checksum */
-	for (i = MPSSE_CMD_SIZE; i < total_len; i++)
-		csum += txbuf[i];
-	request->checksum = -csum;
-
-	if (ftdi_write_data(&ftdi, txbuf, total_len) != total_len)
-		goto free_request;
-
-	if (raw_read(txbuf, block_size) != 0)
-		goto free_request;
-
-	/* Make sure the EC was listening */
-	ret = 0;
-	for (i = 0; i < block_size; i++) {
-		switch (txbuf[i]) {
-		case EC_SPI_PAST_END:
-		case EC_SPI_RX_BAD_DATA:
-		case EC_SPI_NOT_READY:
-			ret = txbuf[i];
-			/* Fall-through */
-		default:
-			break;
-		}
-		if (ret)
-			break;
-	}
-
-free_request:
-	free(txbuf);
-	return ret;
-}
-
-static int spi_read(void *buf, size_t size)
-{
-	uint8_t cmd[MPSSE_CMD_SIZE];
-
-	cmd[0] = SPI_CMD_RX;
-	cmd[1] = ((size - 1) & 0xFF);
-	cmd[2] = (((size - 1) >> 8) & 0xFF);
-
-	if (ftdi_write_data(&ftdi, cmd, sizeof(cmd)) != sizeof(cmd))
-		return -EC_RES_ERROR;
-
-	return raw_read(buf, size) != 0;
-}
-
-static int get_response(uint8_t *bodydest, size_t bodylen)
-{
-	uint8_t sum = 0;
-	size_t i;
-	struct ec_host_response hdr;
-	uint8_t status;
-	time_t deadline = time(NULL) + RESP_TIMEOUT;
-
-	/*
-	 * Read a byte at a time until we see the start of the frame.
-	 * This is slow, but often still faster than the EC.
-	 */
-	while (time(NULL) < deadline) {
-		if (spi_read(&status, sizeof(status)))
-			goto read_error;
-		if (status == EC_SPI_FRAME_START)
-			break;
-	}
-	if (status != EC_SPI_FRAME_START) {
-		fprintf(stderr, "timeout wait for response\n");
-		return -EC_RES_ERROR;
-	}
-
-	/* Now read the response header */
-	if (spi_read(&hdr, sizeof(hdr)))
-		goto read_error;
-
-	/* Check the header */
-	if (hdr.struct_version != EC_HOST_RESPONSE_VERSION) {
-		fprintf(stderr, "response version %d (should be %d)\n",
-			hdr.struct_version,
-			EC_HOST_RESPONSE_VERSION);
-		return -EC_RES_ERROR;
-	}
-	if (hdr.data_len > bodylen) {
-		fprintf(stderr, "response data_len %d is > %zd\n",
-			hdr.data_len, bodylen);
-		return -EC_RES_ERROR;
-	}
-
-	/* Read the data if needed */
-	if (hdr.data_len && spi_read(bodydest, hdr.data_len))
-		goto read_error;
-
-	/* Verify the checksum */
-	for (i = 0; i < sizeof(struct ec_host_response); i++)
-		sum += ((uint8_t *)&hdr)[i];
-	for (i = 0; i < hdr.data_len; i++)
-		sum += bodydest[i];
-	if (sum) {
-		fprintf(stderr, "Checksum invalid\n");
-		return -EC_RES_ERROR;
-	}
-
-	return hdr.result ? -EECRESULT - hdr.result : 0;
-
-read_error:
-	fprintf(stderr, "Read failed: %s\n", ftdi_get_error_string(&ftdi));
-	return -EC_RES_ERROR;
-}
-
-static int ec_command_servo_spi(int cmd, int version,
-				const void *outdata, int outsize,
-				void *indata, int insize)
-{
-	int ret = -EC_RES_ERROR;
-
-	/* Set the chip select low */
-	if (mpsse_set_pins(0) != 0) {
-		fprintf(stderr, "Start failed: %s\n",
-			ftdi_get_error_string(&ftdi));
-		return -EC_RES_ERROR;
-	}
-
-	if (send_request(cmd, version, outdata, outsize) == 0)
-		ret = get_response(indata, insize);
-
-	if (mpsse_set_pins(CS_L) != 0) {
-		fprintf(stderr, "Stop failed: %s\n",
-			ftdi_get_error_string(&ftdi));
-		return -EC_RES_ERROR;
-	}
-	/* SPI protocol gap ... */
-	usleep(10);
-
-	return ret;
-}
-
-static int mpsse_set_clock(uint32_t freq)
-{
-	uint32_t system_clock = 0;
-	uint16_t divisor = 0;
-	uint8_t buf[MPSSE_CMD_SIZE] = {0};
-
-	if (freq > 6000000) {
-		buf[0] = TCK_X5;
-		system_clock = 60000000;
-	} else {
-		buf[0] = TCK_D5;
-		system_clock = 12000000;
-	}
-
-	if (ftdi_write_data(&ftdi, buf, 1) != 1)
-		return -EC_RES_ERROR;
-
-	divisor = (((system_clock / freq) / 2) - 1);
-
-	buf[0] = TCK_DIVISOR;
-	buf[1] = (divisor & 0xFF);
-	buf[2] = ((divisor >> 8) & 0xFF);
-
-	return ftdi_write_data(&ftdi, buf, MPSSE_CMD_SIZE) != MPSSE_CMD_SIZE;
-}
-
-static void servo_spi_close(void)
-{
-	ftdi_set_bitmode(&ftdi, 0, BITMODE_RESET);
-	ftdi_usb_close(&ftdi);
-	ftdi_deinit(&ftdi);
-}
-
-int comm_init_servo_spi(const char *device_name)
-{
-	int status;
-	uint8_t buf[MPSSE_CMD_SIZE] = {0};
-	/* if the user mentioned a device name, use it as serial string */
-	const char *serial = strcmp(CROS_EC_DEV_NAME, device_name) ?
-		device_name : NULL;
-
-	if (ftdi_init(&ftdi))
-		return -EC_RES_ERROR;
-	ftdi_set_interface(&ftdi, SERVO_V2_USB_SPI1_INTERFACE);
-
-	status = ftdi_usb_open_desc(&ftdi, SERVO_V2_USB_VID, SERVO_V2_USB_PID,
-				    NULL, serial);
-	if (status) {
-		debug("Can't find a Servo v2 USB device\n");
-		return -EC_RES_ERROR;
-	}
-
-	status |= ftdi_usb_reset(&ftdi);
-	status |= ftdi_set_latency_timer(&ftdi, FTDI_LATENCY_1MS);
-	status |= ftdi_set_bitmode(&ftdi, 0, BITMODE_RESET);
-	if (status)
-		goto err_close;
-
-	ftdi_set_bitmode(&ftdi, 0, BITMODE_MPSSE);
-	if (mpsse_set_clock(SPI_CLOCK_FREQ))
-		goto err_close;
-
-	/* Disable FTDI internal loopback */
-	buf[0] = LOOPBACK_END;
-	if (ftdi_write_data(&ftdi, buf, 1) != 1)
-		goto err_close;
-	/* Ensure adaptive clock is disabled */
-	buf[0] = DISABLE_ADAPTIVE_CLOCK;
-	if (ftdi_write_data(&ftdi, buf, 1) != 1)
-		goto err_close;
-	/* Set the idle pin states */
-	if (mpsse_set_pins(CS_L) != 0)
-		goto err_close;
-
-	ec_command_proto = ec_command_servo_spi;
-	/* Set temporary size, will be updated later. */
-	ec_max_outsize = EC_PROTO2_MAX_PARAM_SIZE - 8;
-	ec_max_insize = EC_PROTO2_MAX_PARAM_SIZE;
-
-	return 0;
-
-err_close:
-	servo_spi_close();
-	return -EC_RES_ERROR;
-}
diff --git a/util/comm-servo-spi.cc b/util/comm-servo-spi.cc
new file mode 100644
index 0000000000..a476f7d570
--- /dev/null
+++ b/util/comm-servo-spi.cc
@@ -0,0 +1,356 @@
+/* Copyright 2018 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/*
+ * Transport using the Servo V2 SPI1 interface through the FT4232 MPSSE
+ * hardware engine (driven by libftdi) in order to send host commands V3
+ * directly to a MCU slave SPI controller.
+ *
+ * It allows to drive a MCU with the cros_ec host SPI interface directly from
+ * a developer workstation or another test system.
+ *
+ * The USB serial number of the servo board can be passed in the 'name'
+ * parameter, e.g. :
+ * sudo ectool_servo --name=905537-00474 version
+ */
+
+#include "comm-host.h"
+#include "cros_ec_dev.h"
+
+#include <errno.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <time.h>
+
+#include <libftdi1/ftdi.h>
+#include <unistd.h>
+
+/* Servo V2 SPI1 interface identifiers */
+#define SERVO_V2_USB_VID 0x18d1
+#define SERVO_V2_USB_PID 0x5003
+#define SERVO_V2_USB_SPI1_INTERFACE INTERFACE_B
+
+/* SPI clock frequency in Hz */
+#define SPI_CLOCK_FREQ 1000000
+
+#define FTDI_LATENCY_1MS 2
+
+/* Timeout when waiting for the EC answer to our request */
+#define RESP_TIMEOUT 2 /* second */
+
+#ifdef DEBUG
+#define debug(format, arg...) printf(format, ##arg)
+#else
+#define debug(...)
+#endif
+
+/* Communication context */
+static struct ftdi_context ftdi;
+
+/* Size of a MPSSE command packet */
+#define MPSSE_CMD_SIZE 3
+
+enum mpsse_commands {
+	ENABLE_ADAPTIVE_CLOCK = 0x96,
+	DISABLE_ADAPTIVE_CLOCK = 0x97,
+	TCK_X5 = 0x8A,
+	TCK_D5 = 0x8B,
+	TRISTATE_IO = 0x9E,
+};
+
+enum mpsse_pins {
+	SCLK = 1,
+	MOSI = 2,
+	MISO = 4,
+	CS_L = 8,
+};
+/* SCLK/MOSI/CS_L are outputs, MISO is an input */
+#define PINS_DIR (SCLK | MOSI | CS_L)
+
+/* SPI mode 0:
+ * propagates data on the falling edge
+ * and reads data on the rising edge of the clock.
+ */
+#define SPI_CMD_TX (MPSSE_DO_WRITE | MPSSE_WRITE_NEG)
+#define SPI_CMD_RX (MPSSE_DO_READ)
+#define SPI_CMD_TXRX (MPSSE_DO_WRITE | MPSSE_DO_READ | MPSSE_WRITE_NEG)
+
+static int raw_read(uint8_t *buf, int size)
+{
+	int rlen;
+
+	while (size) {
+		rlen = ftdi_read_data(&ftdi, buf, size);
+		if (rlen < 0)
+			break;
+		buf += rlen;
+		size -= rlen;
+	}
+	return !!size;
+}
+
+static int mpsse_set_pins(uint8_t levels)
+{
+	uint8_t buf[MPSSE_CMD_SIZE] = { 0 };
+
+	buf[0] = SET_BITS_LOW;
+	buf[1] = levels;
+	buf[2] = PINS_DIR;
+
+	return ftdi_write_data(&ftdi, buf, sizeof(buf)) != sizeof(buf);
+}
+
+static int send_request(int cmd, int version, const uint8_t *outdata,
+			size_t outsize)
+{
+	uint8_t *txbuf;
+	struct ec_host_request *request;
+	size_t i;
+	int ret = -EC_RES_ERROR;
+	uint8_t csum = 0;
+	size_t block_size = sizeof(struct ec_host_request) + outsize;
+	size_t total_len = MPSSE_CMD_SIZE + block_size;
+
+	txbuf = (uint8_t *)(calloc(1, total_len));
+	if (!txbuf)
+		return -ENOMEM;
+
+	/* MPSSE block size is the full command minus 1 byte */
+	txbuf[0] = SPI_CMD_TXRX;
+	txbuf[1] = ((block_size - 1) & 0xFF);
+	txbuf[2] = (((block_size - 1) >> 8) & 0xFF);
+
+	/* Command header first */
+	request = (struct ec_host_request *)(txbuf + MPSSE_CMD_SIZE);
+	request->struct_version = EC_HOST_REQUEST_VERSION;
+	request->checksum = 0;
+	request->command = cmd;
+	request->command_version = version;
+	request->reserved = 0;
+	request->data_len = outsize;
+
+	/* copy the data to transmit after the command header */
+	memcpy(txbuf + MPSSE_CMD_SIZE + sizeof(struct ec_host_request), outdata,
+	       outsize);
+
+	/* Compute the checksum */
+	for (i = MPSSE_CMD_SIZE; i < total_len; i++)
+		csum += txbuf[i];
+	request->checksum = -csum;
+
+	if (ftdi_write_data(&ftdi, txbuf, total_len) != total_len)
+		goto free_request;
+
+	if (raw_read(txbuf, block_size) != 0)
+		goto free_request;
+
+	/* Make sure the EC was listening */
+	ret = 0;
+	for (i = 0; i < block_size; i++) {
+		switch (txbuf[i]) {
+		case EC_SPI_PAST_END:
+		case EC_SPI_RX_BAD_DATA:
+		case EC_SPI_NOT_READY:
+			ret = txbuf[i];
+			/* Fall-through */
+		default:
+			break;
+		}
+		if (ret)
+			break;
+	}
+
+free_request:
+	free(txbuf);
+	return ret;
+}
+
+static int spi_read(uint8_t *buf, size_t size)
+{
+	uint8_t cmd[MPSSE_CMD_SIZE];
+
+	cmd[0] = SPI_CMD_RX;
+	cmd[1] = ((size - 1) & 0xFF);
+	cmd[2] = (((size - 1) >> 8) & 0xFF);
+
+	if (ftdi_write_data(&ftdi, cmd, sizeof(cmd)) != sizeof(cmd))
+		return -EC_RES_ERROR;
+
+	return raw_read(buf, size) != 0;
+}
+
+static int get_response(uint8_t *bodydest, size_t bodylen)
+{
+	uint8_t sum = 0;
+	size_t i;
+	struct ec_host_response hdr;
+	uint8_t status;
+	time_t deadline = time(NULL) + RESP_TIMEOUT;
+
+	/*
+	 * Read a byte at a time until we see the start of the frame.
+	 * This is slow, but often still faster than the EC.
+	 */
+	while (time(NULL) < deadline) {
+		if (spi_read(&status, sizeof(status)))
+			goto read_error;
+		if (status == EC_SPI_FRAME_START)
+			break;
+	}
+	if (status != EC_SPI_FRAME_START) {
+		fprintf(stderr, "timeout wait for response\n");
+		return -EC_RES_ERROR;
+	}
+
+	/* Now read the response header */
+	if (spi_read((uint8_t *)(&hdr), sizeof(hdr)))
+		goto read_error;
+
+	/* Check the header */
+	if (hdr.struct_version != EC_HOST_RESPONSE_VERSION) {
+		fprintf(stderr, "response version %d (should be %d)\n",
+			hdr.struct_version, EC_HOST_RESPONSE_VERSION);
+		return -EC_RES_ERROR;
+	}
+	if (hdr.data_len > bodylen) {
+		fprintf(stderr, "response data_len %d is > %zd\n", hdr.data_len,
+			bodylen);
+		return -EC_RES_ERROR;
+	}
+
+	/* Read the data if needed */
+	if (hdr.data_len && spi_read(bodydest, hdr.data_len))
+		goto read_error;
+
+	/* Verify the checksum */
+	for (i = 0; i < sizeof(struct ec_host_response); i++)
+		sum += ((uint8_t *)&hdr)[i];
+	for (i = 0; i < hdr.data_len; i++)
+		sum += bodydest[i];
+	if (sum) {
+		fprintf(stderr, "Checksum invalid\n");
+		return -EC_RES_ERROR;
+	}
+
+	return hdr.result ? -EECRESULT - hdr.result : 0;
+
+read_error:
+	fprintf(stderr, "Read failed: %s\n", ftdi_get_error_string(&ftdi));
+	return -EC_RES_ERROR;
+}
+
+static int ec_command_servo_spi(int cmd, int version, const void *outdata,
+				int outsize, void *indata, int insize)
+{
+	int ret = -EC_RES_ERROR;
+
+	/* Set the chip select low */
+	if (mpsse_set_pins(0) != 0) {
+		fprintf(stderr, "Start failed: %s\n",
+			ftdi_get_error_string(&ftdi));
+		return -EC_RES_ERROR;
+	}
+
+	if (send_request(cmd, version, (const uint8_t *)(outdata), outsize) ==
+	    0)
+		ret = get_response((uint8_t *)(indata), insize);
+
+	if (mpsse_set_pins(CS_L) != 0) {
+		fprintf(stderr, "Stop failed: %s\n",
+			ftdi_get_error_string(&ftdi));
+		return -EC_RES_ERROR;
+	}
+	/* SPI protocol gap ... */
+	usleep(10);
+
+	return ret;
+}
+
+static int mpsse_set_clock(uint32_t freq)
+{
+	uint32_t system_clock = 0;
+	uint16_t divisor = 0;
+	uint8_t buf[MPSSE_CMD_SIZE] = { 0 };
+
+	if (freq > 6000000) {
+		buf[0] = TCK_X5;
+		system_clock = 60000000;
+	} else {
+		buf[0] = TCK_D5;
+		system_clock = 12000000;
+	}
+
+	if (ftdi_write_data(&ftdi, buf, 1) != 1)
+		return -EC_RES_ERROR;
+
+	divisor = (((system_clock / freq) / 2) - 1);
+
+	buf[0] = TCK_DIVISOR;
+	buf[1] = (divisor & 0xFF);
+	buf[2] = ((divisor >> 8) & 0xFF);
+
+	return ftdi_write_data(&ftdi, buf, MPSSE_CMD_SIZE) != MPSSE_CMD_SIZE;
+}
+
+static void servo_spi_close(void)
+{
+	ftdi_set_bitmode(&ftdi, 0, BITMODE_RESET);
+	ftdi_usb_close(&ftdi);
+	ftdi_deinit(&ftdi);
+}
+
+int comm_init_servo_spi(const char *device_name)
+{
+	int status;
+	uint8_t buf[MPSSE_CMD_SIZE] = { 0 };
+	/* if the user mentioned a device name, use it as serial string */
+	const char *serial =
+		strcmp(CROS_EC_DEV_NAME, device_name) ? device_name : NULL;
+
+	if (ftdi_init(&ftdi))
+		return -EC_RES_ERROR;
+	ftdi_set_interface(&ftdi, SERVO_V2_USB_SPI1_INTERFACE);
+
+	status = ftdi_usb_open_desc(&ftdi, SERVO_V2_USB_VID, SERVO_V2_USB_PID,
+				    NULL, serial);
+	if (status) {
+		debug("Can't find a Servo v2 USB device\n");
+		return -EC_RES_ERROR;
+	}
+
+	status |= ftdi_usb_reset(&ftdi);
+	status |= ftdi_set_latency_timer(&ftdi, FTDI_LATENCY_1MS);
+	status |= ftdi_set_bitmode(&ftdi, 0, BITMODE_RESET);
+	if (status)
+		goto err_close;
+
+	ftdi_set_bitmode(&ftdi, 0, BITMODE_MPSSE);
+	if (mpsse_set_clock(SPI_CLOCK_FREQ))
+		goto err_close;
+
+	/* Disable FTDI internal loopback */
+	buf[0] = LOOPBACK_END;
+	if (ftdi_write_data(&ftdi, buf, 1) != 1)
+		goto err_close;
+	/* Ensure adaptive clock is disabled */
+	buf[0] = DISABLE_ADAPTIVE_CLOCK;
+	if (ftdi_write_data(&ftdi, buf, 1) != 1)
+		goto err_close;
+	/* Set the idle pin states */
+	if (mpsse_set_pins(CS_L) != 0)
+		goto err_close;
+
+	ec_command_proto = ec_command_servo_spi;
+	/* Set temporary size, will be updated later. */
+	ec_max_outsize = EC_PROTO2_MAX_PARAM_SIZE - 8;
+	ec_max_insize = EC_PROTO2_MAX_PARAM_SIZE;
+
+	return 0;
+
+err_close:
+	servo_spi_close();
+	return -EC_RES_ERROR;
+}
diff --git a/util/comm-usb.cc b/util/comm-usb.cc
new file mode 100644
index 0000000000..64a2507b2e
--- /dev/null
+++ b/util/comm-usb.cc
@@ -0,0 +1,366 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "comm-host.h"
+#include "comm-usb.h"
+#include "ec_commands.h"
+#include "misc_util.h"
+#include "usb_descriptor.h"
+
+#include <assert.h>
+#include <errno.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <endian.h>
+#include <libusb.h>
+
+#define USB_ERROR(m, r) print_libusb_error(__FILE__, __LINE__, m, r)
+
+#ifdef DEBUG
+#define debug(fmt, arg...) \
+	fprintf(stderr, "%s:%d: " fmt, __FILE__, __LINE__, ##arg)
+#else
+#define debug(...)
+#endif
+
+struct usb_endpoint {
+	struct libusb_device_handle *devh;
+	int iface_num;
+	uint8_t ep_num;
+	int chunk_len;
+};
+
+struct usb_endpoint uep;
+
+static void print_libusb_error(const char *file, int line, const char *message,
+			       int error_code)
+{
+	/*
+	 * TODO(b/247573723): Remove cast when libusb is upgraded.
+	 */
+	fprintf(stderr, "%s:%d, %s returned %d (%s)\n", file, line, message,
+		error_code, libusb_strerror((enum libusb_error)error_code));
+}
+
+void comm_usb_exit(void)
+{
+	debug("Exit libusb.\n");
+
+	if (uep.iface_num)
+		libusb_release_interface(uep.devh, uep.iface_num);
+	if (uep.devh)
+		libusb_close(uep.devh);
+	libusb_exit(NULL);
+
+	memset(&uep, 0, sizeof(uep));
+}
+
+/*
+ * Actual USB transfer function, <allow_less> indicates that a valid response
+ * (e.g. EC_CMD_GET_BUILD_INFO) could be shorter than <inlen>.
+ *
+ * Returns enum libusb_error (< 0) or -EECRESULT on error. On success, returns
+ * actually transferred OUT data size or IN data size if read is performed.
+ */
+static int do_xfer(struct usb_endpoint *uep, void *outbuf, int outlen,
+		   void *inbuf, int inlen, int allow_less)
+{
+	int r, actual;
+
+	/* Send data out */
+	if (outbuf && outlen) {
+		actual = 0;
+		r = libusb_bulk_transfer(uep->devh, uep->ep_num,
+					 (uint8_t *)outbuf, outlen, &actual,
+					 2000);
+		if (r != 0) {
+			USB_ERROR("libusb_bulk_transfer", r);
+			return r;
+		}
+		if (actual != outlen) {
+			fprintf(stderr, "%s:%d, only sent %d/%d bytes\n",
+				__FILE__, __LINE__, actual, outlen);
+			return -EECRESULT;
+		}
+	}
+	debug("Sent %d bytes, expecting to receive %d bytes.\n", outlen, inlen);
+
+	/* Read reply back */
+	if (inbuf && inlen) {
+		actual = 0;
+		/*
+		 * libusb_bulk_transfer may time out if actual < inlen and
+		 * actual is a multiple of ep->wMaxPacketSize.
+		 */
+		r = libusb_bulk_transfer(uep->devh, uep->ep_num | USB_DIR_IN,
+					 (uint8_t *)inbuf, inlen, &actual,
+					 5000);
+		if (r != 0) {
+			USB_ERROR("libusb_bulk_transfer", r);
+			return r;
+		}
+		if ((actual != inlen) && !allow_less) {
+			fprintf(stderr, "%s:%d, only received %d/%d bytes\n",
+				__FILE__, __LINE__, actual, inlen);
+			return -EECRESULT;
+		}
+	}
+
+	debug("Received %d bytes.\n", actual);
+
+	/* actual is useful for allow_less. */
+	return actual;
+}
+
+/* Return iface # or -1 if not found. */
+static int find_interface_with_endpoint(struct usb_endpoint *uep)
+{
+	struct libusb_device *dev;
+	struct libusb_config_descriptor *conf = 0;
+	const struct libusb_interface *iface0;
+	const struct libusb_interface_descriptor *iface;
+	const struct libusb_endpoint_descriptor *ep;
+	int r, i, j, k;
+
+	dev = libusb_get_device(uep->devh);
+	r = libusb_get_active_config_descriptor(dev, &conf);
+	if (r < 0) {
+		USB_ERROR("Failed to get_active_config", r);
+		return -1;
+	}
+
+	for (i = 0; i < conf->bNumInterfaces; i++) {
+		iface0 = &conf->interface[i];
+		for (j = 0; j < iface0->num_altsetting; j++) {
+			iface = &iface0->altsetting[j];
+			for (k = 0; k < iface->bNumEndpoints; k++) {
+				ep = &iface->endpoint[k];
+				if (ep->bEndpointAddress == uep->ep_num) {
+					uep->chunk_len = ep->wMaxPacketSize;
+					r = iface->bInterfaceNumber;
+					libusb_free_config_descriptor(conf);
+					return r;
+				}
+			}
+		}
+	}
+
+	libusb_free_config_descriptor(conf);
+	return -1;
+}
+
+int parse_vidpid(const char *input, uint16_t *vid_ptr, uint16_t *pid_ptr)
+{
+	char *copy, *s, *e;
+
+	int ret = 1;
+
+	copy = strdup(input);
+
+	s = strchr(copy, ':');
+	if (!s) {
+		ret = 0;
+		goto cleanup;
+	}
+	*s++ = '\0';
+
+	e = NULL;
+	*vid_ptr = strtoul(copy, &e, 16);
+	if (e && *e) {
+		ret = 0;
+		goto cleanup;
+	}
+
+	e = NULL;
+	*pid_ptr = strtoul(s, &e, 16);
+	if (e && *e) {
+		ret = 0;
+		goto cleanup;
+	}
+cleanup:
+	free(copy);
+	return ret;
+}
+
+static libusb_device_handle *check_device(libusb_device *dev, uint16_t vid,
+					  uint16_t pid, char *serialno)
+{
+	struct libusb_device_descriptor desc;
+	libusb_device_handle *handle = NULL;
+	char sn[256];
+	int snvalid = 0;
+	int r;
+
+	r = libusb_get_device_descriptor(dev, &desc);
+	if (r < 0)
+		return NULL;
+
+	r = libusb_open(dev, &handle);
+	if (r < 0)
+		return NULL;
+
+	if (desc.iSerialNumber) {
+		r = libusb_get_string_descriptor_ascii(handle,
+						       desc.iSerialNumber,
+						       (unsigned char *)sn,
+						       sizeof(sn));
+		if (r > 0)
+			snvalid = 1;
+	}
+
+	if (vid != 0 && vid != desc.idVendor)
+		return NULL;
+	if (pid != 0 && pid != desc.idProduct)
+		return NULL;
+	if (serialno != NULL && (!snvalid || strstr(sn, serialno) == NULL))
+		return NULL;
+
+	return handle;
+}
+
+static int find_endpoint(uint16_t vid, uint16_t pid, char *serialno,
+			 struct usb_endpoint *uep)
+{
+	int iface_num, r, i;
+	libusb_device **devs;
+	libusb_device_handle *devh = NULL;
+
+	r = libusb_init(NULL);
+	if (r < 0) {
+		USB_ERROR("libusb_init", r);
+		return -1;
+	}
+
+	r = libusb_get_device_list(NULL, &devs);
+	if (r < 0) {
+		USB_ERROR("No device is found.\n", r);
+		return -1;
+	}
+
+	for (i = 0; devs[i]; i++) {
+		devh = check_device(devs[i], vid, pid, serialno);
+		if (devh) {
+			debug("Found device.\n");
+			break;
+		}
+	}
+
+	libusb_free_device_list(devs, 1);
+
+	if (!devh) {
+		fprintf(stderr, "Can't find device\n");
+		return -1;
+	}
+
+	uep->devh = devh;
+	uep->ep_num = 2; /* USB_EP_HOSTCMD */
+
+	iface_num = find_interface_with_endpoint(uep);
+	if (iface_num < 0) {
+		fprintf(stderr, "USB HOSTCMD not supported by that device\n");
+		return -1;
+	}
+
+	if (!uep->chunk_len) {
+		fprintf(stderr, "wMaxPacketSize isn't valid\n");
+		return -1;
+	}
+
+	debug("Found interface %d endpoint=%d, chunk_len=%d\n", iface_num,
+	      uep->ep_num, uep->chunk_len);
+
+	libusb_set_auto_detach_kernel_driver(uep->devh, 1);
+	r = libusb_claim_interface(uep->devh, iface_num);
+	if (r < 0) {
+		USB_ERROR("libusb_claim_interface", r);
+		return -1;
+	}
+	uep->iface_num = iface_num;
+
+	debug("READY\n-------\n");
+	return 1;
+}
+
+static int sum_bytes(const void *data, int length)
+{
+	const uint8_t *bytes = (const uint8_t *)data;
+	int sum = 0;
+	int i;
+
+	for (i = 0; i < length; i++)
+		sum += bytes[i];
+	return sum;
+}
+
+static int ec_command_usb(int command, int version, const void *outdata,
+			  int outsize, void *indata, int insize)
+{
+	struct ec_host_request *req;
+	struct ec_host_response *res;
+	size_t req_len, res_len;
+	int rv = -1;
+
+	assert(outsize == 0 || outdata != NULL);
+	assert(insize == 0 || indata != NULL);
+
+	req_len = sizeof(*req) + outsize;
+	req = (struct ec_host_request *)malloc(req_len);
+	res_len = sizeof(*res) + insize;
+	res = (struct ec_host_response *)malloc(res_len);
+	if (req == NULL || res == NULL)
+		goto out;
+
+	req->struct_version = EC_HOST_REQUEST_VERSION; /* 3 */
+	req->checksum = 0;
+	req->command = command;
+	req->command_version = version;
+	req->reserved = 0;
+	req->data_len = outsize;
+	if (outdata)
+		memcpy(&req[1], outdata, outsize);
+	req->checksum = (uint8_t)(-sum_bytes(req, req_len));
+
+	memset(res, 0, res_len);
+
+	debug("Running command 0x%04x\n", command);
+	rv = do_xfer(&uep, req, req_len, res, res_len, 1);
+	if (rv < 0)
+		goto out;
+
+	if (indata)
+		memcpy(indata, &res[1], insize);
+	if (res->result == EC_RES_SUCCESS)
+		rv = res->data_len;
+	else
+		rv = -EECRESULT - res->result;
+
+out:
+	if (req)
+		free(req);
+	if (res)
+		free(res);
+
+	return rv;
+}
+
+int comm_init_usb(uint16_t vid, uint16_t pid)
+{
+	debug("Initializing for %04x:%04x\n", vid, pid);
+
+	memset(&uep, 0, sizeof(uep));
+
+	if (find_endpoint(vid, pid, NULL, &uep) < 0)
+		return -1;
+
+	ec_command_proto = ec_command_usb;
+
+	/* Set large size temporarily, will be updated (reduced) later. */
+	ec_max_outsize = 0x400;
+	ec_max_insize = 0x400;
+
+	return 0;
+}
diff --git a/util/comm-usb.h b/util/comm-usb.h
new file mode 100644
index 0000000000..b43d1bf66f
--- /dev/null
+++ b/util/comm-usb.h
@@ -0,0 +1,37 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Header file for a USB interface.
+ */
+
+#ifndef __UTIL_COMM_USB_H
+#define __UTIL_COMM_USB_H
+
+#include "common.h"
+
+/**
+ * Parse USB vendor ID and product ID pair (e.g. '18d1:5022').
+ *
+ * @param input    Input string to be parsed.
+ * @param vid_ptr  Parsed vendor ID.
+ * @param pid_ptr  Parsed product ID
+ * @return 1 if parsed successfully or 0 on error.
+ */
+int parse_vidpid(const char *input, uint16_t *vid_ptr, uint16_t *pid_ptr);
+
+/**
+ * Initialize USB communication.
+ *
+ * @param vid  Vendor ID of the endpoint device.
+ * @param pid  Product ID of the endpoint device.
+ * @return     Zero if success or non-zero otherwise.
+ */
+int comm_init_usb(uint16_t vid, uint16_t pid);
+
+/**
+ * Clean up USB communication.
+ */
+void comm_usb_exit(void);
+
+#endif /* __UTIL_COMM_USB_H */
diff --git a/util/compare_build.sh b/util/compare_build.sh
index ffe6cab0e5..d1570878ef 100755
--- a/util/compare_build.sh
+++ b/util/compare_build.sh
@@ -1,6 +1,6 @@
 #!/bin/bash
 
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -14,6 +14,7 @@
 # * all       - All boards that are built by the "buildall" target
 # * fp        - All relevant boards for fingerprint
 # * stm32     - All boards that use an STM32 chip
+# * stm32f0   - All boards that use an STM32F0 family of chip
 # * stm32f4   - All boards that use an STM32F4 family of chip
 # * stm32h7   - All boards that use an STM32H7 family of chip
 # * npcx      - "
@@ -21,7 +22,6 @@
 # * ish       - "
 # * it83xx    - "
 # * lm4       - "
-# * mec1322   - "
 # * max32660  - "
 # * mt_scp    - "
 #
@@ -38,6 +38,11 @@
 
 . /usr/share/misc/shflags
 
+FLAGS_PRIVATE_DEFAULT="${FLAGS_FALSE}"
+if [[ -d private ]]; then
+  FLAGS_PRIVATE_DEFAULT="${FLAGS_TRUE}"
+fi
+
 DEFINE_string 'boards' "nocturne_fp" 'Boards to build (all, fp, stm32, hatch)' \
               'b'
 DEFINE_string 'ref1' "HEAD" 'Git reference (commit, branch, etc)'
@@ -45,17 +50,20 @@ DEFINE_string 'ref2' "HEAD^" 'Git reference (commit, branch, etc)'
 DEFINE_boolean 'keep' "${FLAGS_FALSE}" \
                'Remove the temp directory after comparison.' 'k'
 # Integer type can still be passed blank ("")
-DEFINE_integer 'jobs' "-1" 'Number of jobs to pass to make' 'j'
+DEFINE_integer 'jobs' "$(nproc)" 'Number of jobs to pass to make' 'j'
 # When compiling both refs for all boards, mem usage was larger than 32GB.
 # If you don't have more than 32GB, you probably don't want to build both
 # refs at the same time. Use the -o flag.
 DEFINE_boolean 'oneref' "${FLAGS_FALSE}" \
                'Build only one set of boards at a time. This limits mem.' 'o'
-DEFINE_boolean 'private' "${FLAGS_FALSE}" \
-               'Link the private repo/dir into test build source tree.' 'p'
+DEFINE_boolean 'private' "${FLAGS_PRIVATE_DEFAULT}" \
+               'Link the private repo/dir into test build source tree.'
 
 # Usage: assoc-add-keys <associate_array_name> [item1 [item2...]]
 assoc-add-keys() {
+  # Shellcheck doesn't seem to support nameref variables yet.
+  # See https://github.com/koalaman/shellcheck/issues/1544.
+  # shellcheck disable=SC2034,SC2178
   local -n arr="${1}"
   shift
 
@@ -66,11 +74,14 @@ assoc-add-keys() {
 
 # Usage: assoc-rm-keys <associate_array_name> [item1 [item2...]
 assoc-rm-keys() {
+  # Shellcheck doesn't seem to support nameref variables yet.
+  # See https://github.com/koalaman/shellcheck/issues/1544.
+  # shellcheck disable=SC2034,SC2178
   local -n arr="${1}"
   shift
 
   for key in "${@}"; do
-    unset arr["${key}"]
+    unset 'arr[${key}]'
   done
 }
 
@@ -97,6 +108,8 @@ boards-with() {
 
 # Usage: parse-boards <associate_array_name> [board-grp1 [board-grp2...]]
 parse-boards() {
+  # Shellcheck doesn't seem to support nameref variables yet.
+  # See https://github.com/koalaman/shellcheck/issues/1544.
   # shellcheck disable=SC2034
   local -n boards="$1"
   shift
@@ -109,8 +122,9 @@ parse-boards() {
   local -A BOARD_GROUPS=(
     # make-print-boards already filters out the skipped boards
     [all]="$(make-print-boards)"
-    [fp]="dartmonkey bloonchipper nucleo-dartmonkey nucleo-h743zi"
+    [fp]="dartmonkey bloonchipper helipilot nucleo-dartmonkey nucleo-h743zi"
     [stm32]="$(boards-with 'CHIP[[:space:]:=]*stm32')"
+    [stm32f0]="$(boards-with 'CHIP_VARIANT[[:space:]:=]*stm32f0')"
     [stm32f4]="$(boards-with 'CHIP_VARIANT[[:space:]:=]*stm32f4')"
     [stm32h7]="$(boards-with 'CHIP_VARIANT[[:space:]:=]*stm32h7')"
     [npcx]="$(boards-with 'CHIP[[:space:]:=]*npcx')"
@@ -118,7 +132,6 @@ parse-boards() {
     [ish]="$(boards-with 'CHIP[[:space:]:=]*ish')"
     [it83xx]="$(boards-with 'CHIP[[:space:]:=]*it83xx')"
     [lm4]="$(boards-with 'CHIP[[:space:]:=]*lm4')"
-    [mec1322]="$(boards-with 'CHIP[[:space:]:=]*mec1322')"
     [max32660]="$(boards-with 'CHIP[[:space:]:=]*max32660')"
     [mt_scp]="$(boards-with 'CHIP[[:space:]:=]*mt_scp')"
   )
@@ -195,7 +208,8 @@ printf "%s\n" "${BOARDS[@]}" | sort | column
 # Symbolically linked directories
 LINKS=( )
 if [[ "${FLAGS_private}" == "${FLAGS_TRUE}" ]]; then
-	LINKS+=( private )
+  echo "# Requesting private directory link"
+  LINKS+=( private )
 fi
 
 ##########################################################################
@@ -209,7 +223,9 @@ fi
 echo "# Preparing Makefile"
 cat > "${TMP_DIR}/Makefile" <<HEREDOC
 ORIGIN ?= $(realpath .)
+BORINGSSL_DIR ?= $(realpath ../../third_party/boringssl)
 CRYPTOC_DIR ?= $(realpath ../../third_party/cryptoc)
+ZEPHYR_BASE ?= $(realpath ../../../src/third_party/zephyr/main)
 BOARDS ?= ${BOARDS[*]}
 LINKS ?= ${LINKS[*]}
 
@@ -217,7 +233,7 @@ LINKS ?= ${LINKS[*]}
 all: build-${OLD_REF} build-${NEW_REF}
 
 ec-%:
-	git clone --quiet --no-checkout \$(ORIGIN) \$@
+	git clone --quiet --no-checkout --shared \$(ORIGIN) \$@
 	git -C \$@ checkout --quiet \$(@:ec-%=%)
 ifneq (\$(LINKS),)
 	ln -s \$(addprefix \$(ORIGIN)/,\$(LINKS)) \$@
@@ -226,7 +242,9 @@ endif
 build-%: ec-%
 	\$(MAKE) --no-print-directory -C \$(@:build-%=ec-%)                   \\
 		STATIC_VERSION=1                                              \\
-		CRYPTOCLIB=\$(CRYPTOC_DIR)                                    \\
+		BORINGSSL_DIR=\$(BORINGSSL_DIR)                               \\
+		CRYPTOC_DIR=\$(CRYPTOC_DIR)                                   \\
+		ZEPHYR_BASE=\$(ZEPHYR_BASE)                                   \\
 		\$(addprefix proj-,\$(BOARDS))
 	@printf "  MKDIR   %s\n" "\$@"
 	@mkdir -p \$@
diff --git a/util/config_allowed.txt b/util/config_allowed.txt
new file mode 100644
index 0000000000..b7f511ce42
--- /dev/null
+++ b/util/config_allowed.txt
@@ -0,0 +1,1010 @@
+CONFIG_8042_AUX
+CONFIG_ACCELGYRO_BMI160_INT2_OUTPUT
+CONFIG_ACCELGYRO_BMI160_INT_EVENT
+CONFIG_ACCELGYRO_BMI220
+CONFIG_ACCELGYRO_BMI260_INT2_OUTPUT
+CONFIG_ACCELGYRO_BMI260_INT_EVENT
+CONFIG_ACCELGYRO_BMI3XX_INT_EVENT
+CONFIG_ACCELGYRO_BMI_I2C
+CONFIG_ACCELGYRO_ICM42607_INT_EVENT
+CONFIG_ACCELGYRO_ICM426XX_INT_EVENT
+CONFIG_ACCELGYRO_ICM_I2C
+CONFIG_ACCELGYRO_LSM6DS0
+CONFIG_ACCELGYRO_SEC_ADDR_FLAGS
+CONFIG_ACCEL_CAL_KASA_RADIUS_THRES
+CONFIG_ACCEL_CAL_MAX_TEMP
+CONFIG_ACCEL_CAL_MIN_TEMP
+CONFIG_ACCEL_CAL_NEWTON_RADIUS_THRES
+CONFIG_ACCEL_FORCE_MODE_MASK
+CONFIG_ACCEL_KXCJ9
+CONFIG_ACCEL_LIS2DE
+CONFIG_ACCEL_LIS2DH
+CONFIG_ACCEL_LIS2DS
+CONFIG_ACCEL_LIS2DS_INT_EVENT
+CONFIG_ACCEL_LIS2DW12_INT_EVENT
+CONFIG_ACCEL_LIS2DWL
+CONFIG_ACCEL_LIS2DW_AS_BASE
+CONFIG_ACCEL_LIS2DW_COMMON
+CONFIG_ACCEL_LIS2D_COMMON
+CONFIG_ACCEL_LNG2DM
+CONFIG_ACCEL_LSM6DSM_INT_EVENT
+CONFIG_ACCEL_LSM6DSO_INT_EVENT
+CONFIG_ACCEL_STD_REF_FRAME_OLD
+CONFIG_ADC_BUTTONS
+CONFIG_ADC_PROFILE
+CONFIG_ADC_PROFILE_FAST_CONTINUOUS
+CONFIG_ADC_PROFILE_SINGLE
+CONFIG_ADC_SAMPLE_TIME
+CONFIG_ADC_VOLTAGE_COMPARATOR
+CONFIG_ADC_WATCHDOG
+CONFIG_ALS_AL3010
+CONFIG_ALS_BH1730
+CONFIG_ALS_BH1730_LUXTH_PARAMS
+CONFIG_ALS_ISL29035
+CONFIG_ALS_LIGHTBAR_DIMMING
+CONFIG_ALS_OPT3001
+CONFIG_ALS_SI114X
+CONFIG_ALS_SI114X_CHECK_REVISION
+CONFIG_ALS_SI114X_INT_EVENT
+CONFIG_ALS_SI114X_POLLING
+CONFIG_ALS_TCS3400_INT_EVENT
+CONFIG_AON_PERSISTENT_BASE
+CONFIG_AON_PERSISTENT_SIZE
+CONFIG_AON_RAM_BASE
+CONFIG_AON_RAM_SIZE
+CONFIG_AP_HANG_DETECT
+CONFIG_AP_WARM_RESET_INTERRUPT
+CONFIG_ARMV7M_CACHE
+CONFIG_ASSEMBLY_MULA32
+CONFIG_AUDIO_CODEC_
+CONFIG_AUDIO_CODEC_CAP_WOV_AUDIO_SHM
+CONFIG_AUDIO_CODEC_CAP_WOV_LANG_SHM
+CONFIG_AUDIO_CODEC_DMIC
+CONFIG_AUDIO_CODEC_DMIC_MAX_SOFTWARE_GAIN
+CONFIG_AUDIO_CODEC_DMIC_SOFTWARE_GAIN
+CONFIG_AUDIO_CODEC_I2S_RX
+CONFIG_AUDIO_CODEC_WOV
+CONFIG_AUDIO_CODEC_WOV_AUDIO_BUF_LEN
+CONFIG_AUDIO_CODEC_WOV_AUDIO_BUF_TYPE
+CONFIG_AUDIO_CODEC_WOV_LANG_BUF_LEN
+CONFIG_AUDIO_CODEC_WOV_LANG_BUF_TYPE
+CONFIG_AUX_TIMER_PERIOD_MS
+CONFIG_BACKLIGHT_REQ_GPIO
+CONFIG_BARO_BMP280
+CONFIG_BASE32
+CONFIG_BATTERY_
+CONFIG_BATTERY_BQ20Z453
+CONFIG_BATTERY_BQ27541
+CONFIG_BATTERY_BQ27621
+CONFIG_BATTERY_BQ4050
+CONFIG_BATTERY_CRITICAL_SHUTDOWN_TIMEOUT
+CONFIG_BATTERY_CUTOFF_DELAY_US
+CONFIG_BATTERY_LOW_VOLTAGE_PROTECTION
+CONFIG_BATTERY_LOW_VOLTAGE_TIMEOUT
+CONFIG_BATTERY_MAX17055
+CONFIG_BATTERY_MAX17055_ALERT
+CONFIG_BATTERY_MAX17055_FULL_MODEL
+CONFIG_BATTERY_MM8013
+CONFIG_BATTERY_MOCK
+CONFIG_BATTERY_PRECHARGE_TIMEOUT
+CONFIG_BATTERY_PRESENT_
+CONFIG_BATTERY_REQUESTS_NIL_WHEN_DEAD
+CONFIG_BATTERY_RETRY_NACK
+CONFIG_BATTERY_VENDOR_PARAM
+CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE
+CONFIG_BC12_DETECT_MAX14637
+CONFIG_BC12_DETECT_PI3USB9281
+CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT
+CONFIG_BC12_MAX14637_DELAY_FROM_OFF_TO_ON_MS
+CONFIG_BD9995X_DELAY_INPUT_PORT_SELECT
+CONFIG_BD9995X_POWER_SAVE_MODE
+CONFIG_BLANK
+CONFIG_BLINK
+CONFIG_BLINK_LEDS
+CONFIG_BLUETOOTH_HCI_DEBUG
+CONFIG_BLUETOOTH_LE
+CONFIG_BLUETOOTH_LE_RADIO_TEST
+CONFIG_BLUETOOTH_LE_STACK
+CONFIG_BLUETOOTH_LL_DEBUG
+CONFIG_BMI_ORIENTATION_SENSOR
+CONFIG_BMI_SEC_I2C
+CONFIG_BOARD_DEEP_SLEEP
+CONFIG_BOARD_EC_HANDLES_ALL_SYS_PWRGD
+CONFIG_BOARD_FORCE_RESET_PIN
+CONFIG_BOARD_HAS_ALL_SYS_PWRGD
+CONFIG_BOARD_HAS_RTC_RESET
+CONFIG_BOARD_I2C_ADDR_FLAGS
+CONFIG_BOARD_ID_CMD_ACPI_EC1
+CONFIG_BOARD_POST_GPIO_INIT
+CONFIG_BOARD_PRE_INIT
+CONFIG_BODY_DETECTION_SENSOR
+CONFIG_BOOTBLOCK
+CONFIG_BOOTCFG_VALUE
+CONFIG_BOOT_HEADER_STORAGE_OFF
+CONFIG_BOOT_HEADER_STORAGE_SIZE
+CONFIG_BORINGSSL_CRYPTO
+CONFIG_BUTTON_COUNT
+CONFIG_CAPSENSE
+CONFIG_CASE_CLOSED_DEBUG_EXTERNAL
+CONFIG_CHARGER_BATTERY_TSENSE
+CONFIG_CHARGER_BD9995X
+CONFIG_CHARGER_BD9995X_CHGEN
+CONFIG_CHARGER_BQ24715
+CONFIG_CHARGER_BQ24770
+CONFIG_CHARGER_BQ24773
+CONFIG_CHARGER_BQ25703
+CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA
+CONFIG_CHARGER_CURRENT_LIMIT
+CONFIG_CHARGER_EN_ACTIVE_LOW
+CONFIG_CHARGER_EN_GPIO
+CONFIG_CHARGER_ILIM_PIN_DISABLED
+CONFIG_CHARGER_LIMIT_
+CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT
+CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW
+CONFIG_CHARGER_MAX_INPUT_CURRENT
+CONFIG_CHARGER_MT6370
+CONFIG_CHARGER_MT6370_BACKLIGHT
+CONFIG_CHARGER_MT6370_BC12_GPIO
+CONFIG_CHARGER_PROFILE_OVERRIDE_COMMON
+CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES
+CONFIG_CHARGER_RT9466
+CONFIG_CHARGER_RT9467
+CONFIG_CHARGER_SENSE_RESISTOR_AC_ISL9238
+CONFIG_CHARGER_SY21612
+CONFIG_CHARGE_MANAGER_BAT_PCT_SAFE_MODE_EXIT
+CONFIG_CHARGE_MANAGER_DRP_CHARGING
+CONFIG_CHARGE_MANAGER_EXTERNAL_POWER_LIMIT
+CONFIG_CHARGE_MANAGER_SAFE_MODE
+CONFIG_CHIPSET_ALDERLAKE
+CONFIG_CHIPSET_APL_GLK
+CONFIG_CHIPSET_APOLLOLAKE
+CONFIG_CHIPSET_CANNONLAKE
+CONFIG_CHIPSET_CEZANNE
+CONFIG_CHIPSET_COMETLAKE
+CONFIG_CHIPSET_COMETLAKE_DISCRETE
+CONFIG_CHIPSET_DEBUG
+CONFIG_CHIPSET_ECDRIVEN
+CONFIG_CHIPSET_FALCONLITE
+CONFIG_CHIPSET_GEMINILAKE
+CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET
+CONFIG_CHIPSET_HAS_PLATFORM_RESET
+CONFIG_CHIPSET_HAS_PRE_INIT_CALLBACK
+CONFIG_CHIPSET_ICELAKE
+CONFIG_CHIPSET_JASPERLAKE
+CONFIG_CHIPSET_MT817X
+CONFIG_CHIPSET_MT8183
+CONFIG_CHIPSET_MT8192
+CONFIG_CHIPSET_POWER_SEQ_VERSION
+CONFIG_CHIPSET_PP3300_RAIL_FIRST
+CONFIG_CHIPSET_RK3288
+CONFIG_CHIPSET_RK3399
+CONFIG_CHIPSET_SC7180
+CONFIG_CHIPSET_SC7280
+CONFIG_CHIPSET_SDM845
+CONFIG_CHIPSET_SKYLAKE
+CONFIG_CHIPSET_SLP_S3_L_OVERRIDE
+CONFIG_CHIPSET_STONEY
+CONFIG_CHIPSET_TIGERLAKE
+CONFIG_CHIPSET_X86_RSMRST_AFTER_S5
+CONFIG_CHIPSET_X86_RSMRST_DELAY
+CONFIG_CHIP_DATA_IN_INIT_ROM
+CONFIG_CHIP_LFW_USE_ROM_SPI
+CONFIG_CHIP_MEMORY_REGIONS
+CONFIG_CHIP_PANIC_BACKUP
+CONFIG_CHIP_PRE_INIT
+CONFIG_CHIP_UNCACHED_REGION
+CONFIG_CLOCK_CRYSTAL
+CONFIG_CLOCK_SRC_EXTERNAL
+CONFIG_CMD_
+CONFIG_CMD_ACCELS
+CONFIG_CMD_ACCELSPOOF
+CONFIG_CMD_ACCEL_FIFO
+CONFIG_CMD_ACCEL_INFO
+CONFIG_CMD_ACCEL_SPOOF
+CONFIG_CMD_ADC
+CONFIG_CMD_ALS
+CONFIG_CMD_APTHROTTLE
+CONFIG_CMD_AP_RESET_LOG
+CONFIG_CMD_BATDEBUG
+CONFIG_CMD_BATTFAKE
+CONFIG_CMD_BATT_MFG_ACCESS
+CONFIG_CMD_CBI
+CONFIG_CMD_CHARGEN
+CONFIG_CMD_CHARGER
+CONFIG_CMD_CHARGER_ADC_AMON_BMON
+CONFIG_CMD_CHARGER_DUMP
+CONFIG_CMD_CHARGER_PROFILE_OVERRIDE
+CONFIG_CMD_CHARGER_PROFILE_OVERRIDE_TEST
+CONFIG_CMD_CHARGE_SUPPLIER_INFO
+CONFIG_CMD_CHGRAMP
+CONFIG_CMD_CLOCKGATES
+CONFIG_CMD_COMXTEST
+CONFIG_CMD_CRASH
+CONFIG_CMD_DEVICE_EVENT
+CONFIG_CMD_DLOG
+CONFIG_CMD_ECTEMP
+CONFIG_CMD_FASTCHARGE
+CONFIG_CMD_FLASH
+CONFIG_CMD_FLASHINFO
+CONFIG_CMD_FLASH_TRISTATE
+CONFIG_CMD_FLASH_WP
+CONFIG_CMD_FORCETIME
+CONFIG_CMD_FPSENSOR_DEBUG
+CONFIG_CMD_GETTIME
+CONFIG_CMD_GL3590
+CONFIG_CMD_GPIO_POWER_DOWN
+CONFIG_CMD_GT7288
+CONFIG_CMD_HASH
+CONFIG_CMD_HCDEBUG
+CONFIG_CMD_HOSTCMD
+CONFIG_CMD_I2CWEDGE
+CONFIG_CMD_I2C_PROTECT
+CONFIG_CMD_I2C_SCAN
+CONFIG_CMD_I2C_SPEED
+CONFIG_CMD_I2C_STRESS_TEST
+CONFIG_CMD_I2C_STRESS_TEST_ACCEL
+CONFIG_CMD_I2C_STRESS_TEST_ALS
+CONFIG_CMD_I2C_STRESS_TEST_BATTERY
+CONFIG_CMD_I2C_STRESS_TEST_CHARGER
+CONFIG_CMD_I2C_STRESS_TEST_TCPC
+CONFIG_CMD_I2C_XFER
+CONFIG_CMD_I2C_XFER_RAW
+CONFIG_CMD_IDLE_STATS
+CONFIG_CMD_INA
+CONFIG_CMD_JUMPTAGS
+CONFIG_CMD_KEYBOARD
+CONFIG_CMD_LEDTEST
+CONFIG_CMD_MCDP
+CONFIG_CMD_MD
+CONFIG_CMD_MEM
+CONFIG_CMD_MFALLOW
+CONFIG_CMD_MMAPINFO
+CONFIG_CMD_PD
+CONFIG_CMD_PD_DEV_DUMP_INFO
+CONFIG_CMD_PD_FLASH
+CONFIG_CMD_PD_SRCCAPS_REDUCED_SIZE
+CONFIG_CMD_PD_TIMER
+CONFIG_CMD_PECI
+CONFIG_CMD_PLL
+CONFIG_CMD_POWERLED
+CONFIG_CMD_POWER_AP
+CONFIG_CMD_PPC_DUMP
+CONFIG_CMD_PS2
+CONFIG_CMD_RAND
+CONFIG_CMD_REGULATOR
+CONFIG_CMD_RESET_FLAGS
+CONFIG_CMD_RETIMER
+CONFIG_CMD_RTC
+CONFIG_CMD_RTC_ALARM
+CONFIG_CMD_RW
+CONFIG_CMD_S5_TIMEOUT
+CONFIG_CMD_SCRATCHPAD
+CONFIG_CMD_SEVEN_SEG_DISPLAY
+CONFIG_CMD_SHA256_TEST
+CONFIG_CMD_SHMEM
+CONFIG_CMD_SLEEP
+CONFIG_CMD_SLEEPMASK
+CONFIG_CMD_SLEEPMASK_SET
+CONFIG_CMD_SPI_FLASH
+CONFIG_CMD_SPI_NOR
+CONFIG_CMD_SPI_XFER
+CONFIG_CMD_SYSINFO
+CONFIG_CMD_SYSJUMP
+CONFIG_CMD_SYSLOCK
+CONFIG_CMD_TASKREADY
+CONFIG_CMD_TASK_RESET
+CONFIG_CMD_TCPC_DUMP
+CONFIG_CMD_TEMP_SENSOR
+CONFIG_CMD_TIMERINFO
+CONFIG_CMD_TYPEC
+CONFIG_CMD_USART_INFO
+CONFIG_CMD_USB_PD_CABLE
+CONFIG_CMD_USB_PD_PE
+CONFIG_CMD_WAITMS
+CONFIG_CODE_RAM_SIZE
+CONFIG_COMMON_GPIO
+CONFIG_COMMON_GPIO_SHORTNAMES
+CONFIG_COMMON_PANIC_OUTPUT
+CONFIG_COMMON_RUNTIME
+CONFIG_COMMON_TIMER
+CONFIG_CONSOLE_CMDHELP
+CONFIG_CONSOLE_COMMAND_FLAGS
+CONFIG_CONSOLE_COMMAND_FLAGS_DEFAULT
+CONFIG_CONSOLE_ENABLE_READ_V1
+CONFIG_CONSOLE_HISTORY
+CONFIG_CONSOLE_INPUT_LINE_SIZE
+CONFIG_CONSOLE_UART
+CONFIG_CONSOLE_VERBOSE
+CONFIG_CPU_PROCHOT_ACTIVE_LOW
+CONFIG_CPU_PROCHOT_GATE_ON_C10
+CONFIG_CRC8
+CONFIG_CROS_EC_RO_MEM_SIZE
+CONFIG_CROS_EC_RW_MEM_SIZE
+CONFIG_CTN730
+CONFIG_CTS_TASK_LIST
+CONFIG_CURVE25519
+CONFIG_DATA_RAM_SIZE
+CONFIG_DEBUG_BRINGUP
+CONFIG_DEBUG_DISABLE_WRITE_BUFFER
+CONFIG_DEBUG_EXCEPTIONS
+CONFIG_DEBUG_ORIENTATION
+CONFIG_DEBUG_PRINTF
+CONFIG_DEBUG_STACK_OVERFLOW
+CONFIG_DEDICATED_CHARGE_PORT_COUNT
+CONFIG_DEDICATED_RECOVERY_BUTTON
+CONFIG_DEDICATED_RECOVERY_BUTTON_2
+CONFIG_DEDICATED_RECOVERY_BUTTON_2_FLAGS
+CONFIG_DEDICATED_RECOVERY_BUTTON_FLAGS
+CONFIG_DELAY_DSW_PWROK_TO_PWRBTN
+CONFIG_DEVICE_EVENT
+CONFIG_DEVICE_STATE
+CONFIG_DFU_BOOTMANAGER_MAIN
+CONFIG_DFU_BOOTMANAGER_MAX_REBOOT_COUNT
+CONFIG_DFU_BOOTMANAGER_SHARED
+CONFIG_DFU_RUNTIME
+CONFIG_DMA_CROS
+CONFIG_DMA_DEFAULT_HANDLERS
+CONFIG_DMA_HELP
+CONFIG_DMA_PAGING
+CONFIG_DO_NOT_INCLUDE_RV32I_PANIC_DATA
+CONFIG_DPTF_MOTION_LID_NO_GMR_SENSOR
+CONFIG_DPTF_MULTI_PROFILE
+CONFIG_DRAM_BASE
+CONFIG_DRAM_BASE_LOAD
+CONFIG_DRAM_SIZE
+CONFIG_DSW_PWROK_TO_PWRBTN_US
+CONFIG_EC_CMD_PD_CHIP_INFO
+CONFIG_EC_EC_COMM_BATTERY
+CONFIG_EC_EC_COMM_BATTERY_CLIENT
+CONFIG_EC_EC_COMM_BATTERY_SERVER
+CONFIG_EC_EC_COMM_CLIENT
+CONFIG_EC_EC_COMM_SERVER
+CONFIG_EC_MAX_SENSOR_FREQ_DEFAULT_MILLIHZ
+CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ
+CONFIG_EC_PROTECTED_STORAGE_OFF
+CONFIG_EC_PROTECTED_STORAGE_SIZE
+CONFIG_EC_WRITABLE_STORAGE_OFF
+CONFIG_EC_WRITABLE_STORAGE_SIZE
+CONFIG_ENABLE_JTAG_SELECTION
+CONFIG_EVENT_LOG_SIZE
+CONFIG_EXPERIMENTAL_CONSOLE
+CONFIG_EXTENDED_VERSION_INFO
+CONFIG_FAKE_SHMEM
+CONFIG_FANS
+CONFIG_FAN_DSLEEP
+CONFIG_FAN_DYNAMIC
+CONFIG_FAN_UPDATE_PERIOD
+CONFIG_FINGERPRINT_MCU
+CONFIG_FLASH_BANK_SIZE
+CONFIG_FLASH_DBANK_MODE
+CONFIG_FLASH_DEFERRED_ERASE
+CONFIG_FLASH_ERASED_VALUE32
+CONFIG_FLASH_ERASE_SIZE
+CONFIG_FLASH_LOG
+CONFIG_FLASH_LOG_BASE
+CONFIG_FLASH_LOG_SPACE
+CONFIG_FLASH_MULTIPLE_REGION
+CONFIG_FLASH_PHYSICAL
+CONFIG_FLASH_PROTECT_NEXT_BOOT
+CONFIG_FLASH_PROTECT_RW
+CONFIG_FLASH_READOUT_PROTECTION
+CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE
+CONFIG_FLASH_REGION_TYPE_COUNT
+CONFIG_FLASH_SELECT_REQUIRED
+CONFIG_FLASH_WRITE_IDEAL_SIZE
+CONFIG_FLASH_WRITE_SIZE
+CONFIG_FMAP
+CONFIG_FOO
+CONFIG_FORCE_CONSOLE_RESUME
+CONFIG_FPU_WARNINGS
+CONFIG_FP_SENSOR_ELAN515
+CONFIG_FP_SENSOR_ELAN80
+CONFIG_FP_SENSOR_FPC1025
+CONFIG_FP_SENSOR_FPC1035
+CONFIG_FP_SENSOR_FPC1145
+CONFIG_FRONT_PROXIMITY_SWITCH
+CONFIG_FW_INCLUDE_RO
+CONFIG_FW_LIMITED_IMAGE
+CONFIG_FW_PSTATE_OFF
+CONFIG_FW_PSTATE_SIZE
+CONFIG_GESTURE_DETECTION_MASK
+CONFIG_GESTURE_ORIENTATION
+CONFIG_GESTURE_SAMPLING_INTERVAL_MS
+CONFIG_GESTURE_SENSOR_DOUBLE_TAP
+CONFIG_GESTURE_SENSOR_DOUBLE_TAP_FOR_HOST
+CONFIG_GESTURE_SIGMO
+CONFIG_GESTURE_SIGMO_PROOF_MS
+CONFIG_GESTURE_SIGMO_SENSOR
+CONFIG_GESTURE_SIGMO_SKIP_MS
+CONFIG_GESTURE_SIGMO_THRES_MG
+CONFIG_GESTURE_SW_DETECTION
+CONFIG_GESTURE_TAP_FOR_HOST
+CONFIG_GESTURE_TAP_INNER_WINDOW_T
+CONFIG_GESTURE_TAP_MAX_INTERSTICE_T
+CONFIG_GESTURE_TAP_MIN_INTERSTICE_T
+CONFIG_GESTURE_TAP_OUTER_WINDOW_T
+CONFIG_GESTURE_TAP_SENSOR
+CONFIG_GESTURE_TAP_THRES_MG
+CONFIG_GMR_TABLET_MODE_CUSTOM
+CONFIG_GOOGLETEST
+CONFIG_GPIO_GET_EXTENDED
+CONFIG_GPIO_POWER_DOWN
+CONFIG_GPOI_EXTENDED
+CONFIG_GYRO_L3GD20H
+CONFIG_H2RAM_BASE
+CONFIG_H2RAM_HOST_LPC_IO_BASE
+CONFIG_H2RAM_SIZE
+CONFIG_HAS_TASK_PD_INT
+CONFIG_HIBERNATE_BATT_PCT
+CONFIG_HIBERNATE_BATT_SEC
+CONFIG_HIBERNATE_PSL_COMPENSATE_RTC
+CONFIG_HIBERNATE_PSL_OUT_FLAGS
+CONFIG_HIBERNATE_PSL_VCC1_RST_WAKEUP
+CONFIG_HIBERNATE_WAKEUP_PINS
+CONFIG_HIBERNATE_WAKE_PINS_DYNAMIC
+CONFIG_HID_HECI
+CONFIG_HOOK_DEBUG
+CONFIG_HOSTCMD_ALIGNED
+CONFIG_HOSTCMD_AP_SET_SKUID
+CONFIG_HOSTCMD_BUTTON
+CONFIG_HOSTCMD_EVENTS
+CONFIG_HOSTCMD_FLASHPD
+CONFIG_HOSTCMD_FLASH_SPI_INFO
+CONFIG_HOSTCMD_I2C_ADDR_FLAGS
+CONFIG_HOSTCMD_I2C_SLAVE_ADDR
+CONFIG_HOSTCMD_LOCATE_CHIP
+CONFIG_HOSTCMD_PD
+CONFIG_HOSTCMD_PD_CHG_CTRL
+CONFIG_HOSTCMD_PD_PANIC
+CONFIG_HOSTCMD_RATE_LIMITING_MIN_REST
+CONFIG_HOSTCMD_RATE_LIMITING_PERIOD
+CONFIG_HOSTCMD_RATE_LIMITING_RECESS
+CONFIG_HOSTCMD_RWHASHPD
+CONFIG_HOSTCMD_SECTION_SORTED
+CONFIG_HOSTCMD_SKUID
+CONFIG_HOSTCMD_X86
+CONFIG_HOST_ESPI_VW_POWER_SIGNAL
+CONFIG_HOST_EVENT_REPORT_MASK
+CONFIG_HOST_INTERFACE_ESPI_EC_CHAN_BITMAP
+CONFIG_HOST_INTERFACE_ESPI_EC_MAX_FREQ
+CONFIG_HOST_INTERFACE_ESPI_EC_MODE
+CONFIG_HOSYCMD_BATTERY_V2
+CONFIG_HWTIMER_64BIT
+CONFIG_HW_CRC
+CONFIG_HW_MRIDER
+CONFIG_HW_QUINCY
+CONFIG_HW_SPECIFIC_UDELAY
+CONFIG_I2C_BUS_MAY_BE_UNPOWERED
+CONFIG_I2C_CHIP_MAX_TRANSFER_SIZE
+CONFIG_I2C_CONTROLLER
+CONFIG_I2C_EXTRA_PACKET_SIZE
+CONFIG_I2C_HID_TOUCHPAD
+CONFIG_I2C_MULTI_PORT_CONTROLLER
+CONFIG_I2C_PERIPHERAL
+CONFIG_I2C_SCL_GATE_ADDR
+CONFIG_I2C_SCL_GATE_ADDR_FLAGS
+CONFIG_I2C_SCL_GATE_GPIO
+CONFIG_I2C_SCL_GATE_PORT
+CONFIG_I2C_UPDATE_IF_CHANGED
+CONFIG_I2C_XFER_BOARD_CALLBACK
+CONFIG_I2C_XFER_LARGE_TRANSFER
+CONFIG_IMAGE_PADDING
+CONFIG_INA231
+CONFIG_INDUCTIVE_CHARGING
+CONFIG_INTEL_RVP_MECC_VERSION_1_0
+CONFIG_INTEL_RVP_MECC_VERSION_1_1
+CONFIG_IO_EXPANDER
+CONFIG_IO_EXPANDER_IT8801
+CONFIG_IO_EXPANDER_IT8801_PWM
+CONFIG_IO_EXPANDER_NCT38XX
+CONFIG_IO_EXPANDER_PCA9534
+CONFIG_IO_EXPANDER_PCA9675
+CONFIG_IO_EXPANDER_PCAL6408
+CONFIG_IO_EXPANDER_PORT_COUNT
+CONFIG_IO_EXPANDER_SUPPORT_GET_PORT
+CONFIG_IO_EXPANDER_TCA64XXA
+CONFIG_IPC_SHARED_OBJ_ADDR
+CONFIG_IPC_SHARED_OBJ_BUF_SIZE
+CONFIG_IPI
+CONFIG_IRQ_COUNT
+CONFIG_ISH_BOOT_START
+CONFIG_ISH_CLEAR_FABRIC_ERRORS
+CONFIG_ISH_D0I2_MIN_USEC
+CONFIG_ISH_D0I3_MIN_USEC
+CONFIG_ISH_DW_UART
+CONFIG_ISH_HOST2ISH_COMBINED_ISR
+CONFIG_ISH_IPAPG
+CONFIG_ISH_NEW_PM
+CONFIG_ISH_PM_AONTASK
+CONFIG_ISH_PM_D0I1
+CONFIG_ISH_PM_D0I2
+CONFIG_ISH_PM_D0I3
+CONFIG_ISH_PM_D3
+CONFIG_ISH_PM_RESET_PREP
+CONFIG_ISH_UART_0
+CONFIG_IT83XX_ENABLE_MOUSE_DEVICE
+CONFIG_IT83XX_FLASH_CLOCK_48MHZ
+CONFIG_IT83XX_HARD_RESET_BY_GPG1
+CONFIG_IT83XX_I2C_CMD_QUEUE
+CONFIG_IT83XX_RESET_PD_CONTRACT_IN_BRAM
+CONFIG_IT83XX_SMCLK2_ON_GPC7
+CONFIG_IT83XX_VCC_1P8V
+CONFIG_IT83XX_VCC_3P3V
+CONFIG_IT8XXX2_MUL_WORKAROUND
+CONFIG_ITE_FLASH_SUPPORT
+CONFIG_KEYBOARD_ASSISTANT_KEY
+CONFIG_KEYBOARD_BOOT_KEYS
+CONFIG_KEYBOARD_IRQ_GPIO
+CONFIG_KEYBOARD_KSO_BASE
+CONFIG_KEYBOARD_KSO_HIGH_DRIVE
+CONFIG_KEYBOARD_MULTIPLE
+CONFIG_KEYBOARD_POST_SCAN_CLOCKS
+CONFIG_KEYBOARD_PRINT_SCAN_TIMES
+CONFIG_KEYBOARD_RUNTIME_KEYS
+CONFIG_KEYBOARD_SCANCODE_CALLBACK
+CONFIG_KEYBOARD_TABLET_MODE_SWITCH
+CONFIG_KEYBOARD_TEST
+CONFIG_KX022_ORIENTATION_SENSOR
+CONFIG_LED_BAT_ACTIVE_LOW
+CONFIG_LED_DRIVER_DS2413
+CONFIG_LED_DRIVER_LM3509
+CONFIG_LED_DRIVER_LM3630A
+CONFIG_LED_DRIVER_LP5562
+CONFIG_LED_DRIVER_MP3385
+CONFIG_LED_DRIVER_OZ554
+CONFIG_LED_POLICY_STD
+CONFIG_LED_POWER_ACTIVE_LOW
+CONFIG_LED_POWER_LED
+CONFIG_LED_PWM_ACTIVE_CHARGE_PORT_ONLY
+CONFIG_LED_PWM_CHARGE_STATE_ONLY
+CONFIG_LED_PWM_COUNT
+CONFIG_LFW_OFFSET
+CONFIG_LIBCRYPTOC
+CONFIG_LID_ANGLE_INVALID_CHECK
+CONFIG_LID_ANGLE_SENSOR_BASE
+CONFIG_LID_ANGLE_SENSOR_LID
+CONFIG_LID_ANGLE_TABLET_MODE
+CONFIG_LID_SWITCH_GPIO_LIST
+CONFIG_LIGHTBAR_POWER_RAILS
+CONFIG_LIGHTBAR_TAP_DIM_LAST_SEGMENT
+CONFIG_LLSR_TEST
+CONFIG_LN9310
+CONFIG_LOADER_MEM_OFF
+CONFIG_LOADER_SIZE
+CONFIG_LOADER_STORAGE_OFF
+CONFIG_LOW_POWER_IDLE_LIMITED
+CONFIG_LOW_POWER_USE_LFIOSC
+CONFIG_LPRAM_BASE
+CONFIG_LPRAM_SIZE
+CONFIG_LSM6DSM_SEC_I2C
+CONFIG_MAC_ADDR
+CONFIG_MAC_ADDR_LEN
+CONFIG_MAG_BMI_BMM150
+CONFIG_MAG_BMI_LIS2MDL
+CONFIG_MAG_BMM150
+CONFIG_MAG_CALIBRATE
+CONFIG_MAG_LIS2MDL
+CONFIG_MAG_LSM6DSM_BMM150
+CONFIG_MAG_LSM6DSM_LIS2MDL
+CONFIG_MALLOC
+CONFIG_MCDP28X0
+CONFIG_MCHP_48MHZ_OUT
+CONFIG_MCHP_DEBUG_LPC
+CONFIG_MCHP_DEEP_SLP_DEBUG
+CONFIG_MCHP_DEEP_SLP_GPIO_PWR_DOWN
+CONFIG_MCHP_ESPI_DEBUG
+CONFIG_MCHP_ESPI_EC_CMD
+CONFIG_MCHP_ESPI_RESET_DEASSERT_INIT
+CONFIG_MCHP_ESPI_VW_SAVE_ON_SLEEP
+CONFIG_MCHP_GPSPI
+CONFIG_MCHP_GPSPI_TX_DMA
+CONFIG_MCHP_I2C0_SLAVE_ADDRS
+CONFIG_MCHP_I2C1_SLAVE_ADDRS
+CONFIG_MCHP_I2C2_SLAVE_ADDRS
+CONFIG_MCHP_I2C3_SLAVE_ADDRS
+CONFIG_MCHP_I2C4_SLAVE_ADDRS
+CONFIG_MCHP_I2C5_SLAVE_ADDRS
+CONFIG_MCHP_I2C6_SLAVE_ADDRS
+CONFIG_MCHP_I2C7_SLAVE_ADDRS
+CONFIG_MCHP_JTAG_MODE
+CONFIG_MCHP_LFW_DEBUG
+CONFIG_MCHP_QMSPI_TX_DMA
+CONFIG_MCHP_TFDP
+CONFIG_MEC1701_TFDP
+CONFIG_MEC_GPIO_EC_CMDS
+CONFIG_MEC_SRAM_BASE_END
+CONFIG_MEC_SRAM_BASE_START
+CONFIG_MEC_SRAM_SIZE
+CONFIG_MEC_TEST_EC_RORW_CRC
+CONFIG_MEMORY_REGIONS
+CONFIG_MIA_WDT_VEC
+CONFIG_MKBP_
+CONFIG_MKBP_USE_
+CONFIG_MOTION_FILL_LPC_SENSE_DATA
+CONFIG_MOTION_MIN_SENSE_WAIT_TIME
+CONFIG_MOTION_SENSE_RESUME_DELAY_US
+CONFIG_MOTION_SENSE_SUSPEND_DELAY_US
+CONFIG_MP4245
+CONFIG_NAME
+CONFIG_NB7V904M_LPM_OVERRIDE
+CONFIG_NO_PINHOLD
+CONFIG_NUM_FIXED_BATTERIES
+CONFIG_ONEWIRE
+CONFIG_ONLINE_CALIB
+CONFIG_ONLINE_CALIB_SPOOF_MODE
+CONFIG_ORIENTATION_SENSOR
+CONFIG_OTP
+CONFIG_PANIC_BASE_OFFSET
+CONFIG_PANIC_CONSOLE_OUTPUT
+CONFIG_PANIC_DATA_BASE
+CONFIG_PANIC_DATA_SIZE
+CONFIG_PANIC_DRAM_BASE
+CONFIG_PANIC_DRAM_SIZE
+CONFIG_PANIC_STRIP_GPR
+CONFIG_PD_RETRY_COUNT
+CONFIG_PD_USE_DAC_AS_REF
+CONFIG_PECI_COMMON
+CONFIG_PECI_TJMAX
+CONFIG_PLATFORM_EC_
+CONFIG_PMIC_FW_LONG_PRESS_TIMER
+CONFIG_PMU_HARD_RESET
+CONFIG_POLLING_UART
+CONFIG_PORT80_HISTORY_LEN
+CONFIG_PORT80_PRINT_IN_INT
+CONFIG_POWER_BUTTON_FLAGS
+CONFIG_POWER_BUTTON_INIT_IDLE
+CONFIG_POWER_BUTTON_X86
+CONFIG_POWER_PP5000_CONTROL
+CONFIG_POWER_S0IX
+CONFIG_POWER_S0IX_FAILURE_DETECTION
+CONFIG_POWER_S4_RESIDENCY
+CONFIG_POWER_SHUTDOWN_PAUSE_IN_S5
+CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD
+CONFIG_POWER_SIGNAL_RUNTIME_CONFIG
+CONFIG_POWER_TRACK_HOST_SLEEP_STATE
+CONFIG_PRESERVE_LOGS
+CONFIG_PRINTF_LONG_IS_32BITS
+CONFIG_PRINT_IN_INT
+CONFIG_PROGRAM_MEMORY_BASE
+CONFIG_PROGRAM_MEMORY_BASE_LOAD
+CONFIG_PSTORE
+CONFIG_PVD
+CONFIG_PWM_INPUT_LFCLK
+CONFIG_PWR_STATE_DISCHARGE_FULL
+CONFIG_RAM_BANKS
+CONFIG_RAM_BANK_SIZE
+CONFIG_RAM_BASE
+CONFIG_RAM_SIZE
+CONFIG_REGULATOR_IR357X
+CONFIG_RESTRICTED_CONSOLE_COMMANDS
+CONFIG_RISCV_EXTENSION_M
+CONFIG_RMA_AUTH
+CONFIG_RMA_AUTH_USE_P256
+CONFIG_RNG
+CONFIG_ROLLBACK
+CONFIG_ROLLBACK_MPU_PROTECT
+CONFIG_ROLLBACK_OFF
+CONFIG_ROLLBACK_SECRET_LOCAL_ENTROPY_SIZE
+CONFIG_ROLLBACK_SECRET_SIZE
+CONFIG_ROLLBACK_SIZE
+CONFIG_ROLLBACK_UPDATE
+CONFIG_ROLLBACK_VERSION
+CONFIG_ROM_BASE
+CONFIG_ROM_SIZE
+CONFIG_RO_HDR_MEM_OFF
+CONFIG_RO_HDR_SIZE
+CONFIG_RO_MEM_OFF
+CONFIG_RO_MEM_SIZE
+CONFIG_RO_PANIC_DATA_SIZE
+CONFIG_RO_PUBKEY_ADDR
+CONFIG_RO_PUBKEY_READ_ADDR
+CONFIG_RO_PUBKEY_SIZE
+CONFIG_RO_PUBKEY_STORAGE_OFF
+CONFIG_RO_ROM_RESIDENT_MEM_OFF
+CONFIG_RO_ROM_RESIDENT_SIZE
+CONFIG_RO_SIZE
+CONFIG_RO_STORAGE_OFF
+CONFIG_RPMSG_NAME_SERVICE
+CONFIG_RSA_OPTIMIZED
+CONFIG_RWSIG_DONT_CHECK_ON_PIN_RESET
+CONFIG_RWSIG_JUMP_TIMEOUT
+CONFIG_RWSIG_READ_ADDR
+CONFIG_RW_A_SIGN_STORAGE_OFF
+CONFIG_RW_A_STORAGE_OFF
+CONFIG_RW_B
+CONFIG_RW_BOOT_HEADER_STORAGE_OFF
+CONFIG_RW_BOOT_HEADER_STORAGE_SIZE
+CONFIG_RW_B_MEM_OFF
+CONFIG_RW_B_SIGN_STORAGE_OFF
+CONFIG_RW_B_SIG_ADDR
+CONFIG_RW_B_STORAGE_OFF
+CONFIG_RW_MEM_OFF
+CONFIG_RW_MEM_SIZE
+CONFIG_RW_ROM_RESIDENT_MEM_OFF
+CONFIG_RW_ROM_RESIDENT_SIZE
+CONFIG_RW_SIG_ADDR
+CONFIG_RW_SIG_SIZE
+CONFIG_RW_SIZE
+CONFIG_RW_STORAGE_OFF
+CONFIG_SCI_GPIO
+CONFIG_SENSORHUB_LSM6DSM
+CONFIG_SENSOR_ORIENTATION
+CONFIG_SERIALNO_LEN
+CONFIG_SEVEN_SEG_DISPLAY
+CONFIG_SHA256
+CONFIG_SHA256_HW
+CONFIG_SHAREDLIB
+CONFIG_SHAREDLIB_MEM_OFF
+CONFIG_SHAREDLIB_SIZE
+CONFIG_SHAREDLIB_STORAGE_OFF
+CONFIG_SHAREDMEM_MINIMUM_SIZE
+CONFIG_SHAREDMEM_MINIMUM_SIZE_RWSIG
+CONFIG_SIMULATED_BUTTON
+CONFIG_SLEEP_TIMEOUT_MS
+CONFIG_SMBUS
+CONFIG_SOFTWARE_CLZ
+CONFIG_SOFTWARE_CTZ
+CONFIG_SOMETHING
+CONFIG_SPI_ACCEL_PORT
+CONFIG_SPI_CONTROLLER
+CONFIG_SPI_CS_GPIO
+CONFIG_SPI_FLASH
+CONFIG_SPI_FLASH_GD25LQ40
+CONFIG_SPI_FLASH_GD25Q41B
+CONFIG_SPI_FLASH_HAS_SR2
+CONFIG_SPI_FLASH_PORT
+CONFIG_SPI_FLASH_READ_WAIT_MS
+CONFIG_SPI_FLASH_W25Q128
+CONFIG_SPI_FLASH_W25Q40
+CONFIG_SPI_FLASH_W25Q64
+CONFIG_SPI_FLASH_W25Q80
+CONFIG_SPI_FLASH_W25X40
+CONFIG_SPI_FP_PORT
+CONFIG_SPI_HALFDUPLEX
+CONFIG_SPI_MUTABLE_DEVICE_LIST
+CONFIG_SPI_NOR_BLOCK_ERASE
+CONFIG_SPI_NOR_DEBUG
+CONFIG_SPI_NOR_MAX_MESSAGE_SIZE
+CONFIG_SPI_NOR_MAX_READ_SIZE
+CONFIG_SPI_NOR_MAX_WRITE_SIZE
+CONFIG_SPI_NOR_SMART_ERASE
+CONFIG_SPI_PROTOCOL_V2
+CONFIG_SPI_RX_BUF_SIZE
+CONFIG_SPI_TOUCHPAD_PORT
+CONFIG_SPI_TX_BUF_SIZE
+CONFIG_STACK_SIZE
+CONFIG_STANDARD_OUTPUT
+CONFIG_STEINHART_HART_3V0_22K6_47K_4050B
+CONFIG_STEINHART_HART_3V3_13K7_47K_4050B
+CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
+CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
+CONFIG_STEINHART_HART_6V0_51K1_47K_4050B
+CONFIG_STM32G4_UCPD_DEBUG
+CONFIG_STM32L_FAKE_HIBERNATE
+CONFIG_STM32_CHARGER_DETECT
+CONFIG_STM32_CLOCK_HSE_HZ
+CONFIG_STM32_CLOCK_LSE
+CONFIG_STM32_EXTENDED_RESET_FLAGS
+CONFIG_STM32_SPI1_CONTROLLER
+CONFIG_STREAM_SIGNATURE
+CONFIG_STREAM_USART
+CONFIG_STREAM_USART1
+CONFIG_STREAM_USART2
+CONFIG_STREAM_USART3
+CONFIG_STREAM_USART4
+CONFIG_STREAM_USART5
+CONFIG_STREAM_USART9
+CONFIG_STREAM_USB
+CONFIG_SUPPORT_CHIP_HIBERNATION
+CONFIG_SUPPRESSED_HOST_COMMANDS
+CONFIG_SWITCH_DEDICATED_RECOVERY
+CONFIG_SW_CRC
+CONFIG_SYNC
+CONFIG_SYNC_COMMAND
+CONFIG_SYNC_INT_EVENT
+CONFIG_SYNC_QUEUE_SIZE
+CONFIG_SYSTEM_UNLOCK
+CONFIG_SYV682X_HV_ILIM
+CONFIG_TASK_LIST
+CONFIG_TASK_PROFILING
+CONFIG_TASK_RESET_LIST
+CONFIG_TCPC_I2C_BASE_ADDR
+CONFIG_TCPC_I2C_BASE_ADDR_FLAGS
+CONFIG_TEMP_CACHE_STALE_THRES
+CONFIG_TEMP_SENSOR_ADT7481
+CONFIG_TEMP_SENSOR_AMD_R19ME4070
+CONFIG_TEMP_SENSOR_BD99992GW
+CONFIG_TEMP_SENSOR_EC_ADC
+CONFIG_TEMP_SENSOR_G753
+CONFIG_TEMP_SENSOR_G781
+CONFIG_TEMP_SENSOR_G782
+CONFIG_TEMP_SENSOR_OTI502
+CONFIG_TEMP_SENSOR_POWER_GPIO
+CONFIG_TEMP_SENSOR_TMP006
+CONFIG_TEMP_SENSOR_TMP411
+CONFIG_TEMP_SENSOR_TMP432
+CONFIG_TEMP_SENSOR_TMP468
+CONFIG_TEST_1P8V
+CONFIG_TEST_MOCK_LIST
+CONFIG_TEST_SM
+CONFIG_TEST_TASK_LIST
+CONFIG_TEST_USB_PD_TIMER
+CONFIG_TEST_USB_PE_SM
+CONFIG_THERMISTOR_NCP15WB
+CONFIG_THROTTLE_AP_ON_BAT_OLTAGE
+CONFIG_THROTTLE_AP_ON_BAT_VOLTAGE
+CONFIG_TICK
+CONFIG_TOUCHPAD_FW_CHUNKS
+CONFIG_TOUCHPAD_GT7288
+CONFIG_TOUCHPAD_HASH_FW
+CONFIG_TOUCHPAD_ST
+CONFIG_TOUCHPAD_VIRTUAL_OFF
+CONFIG_TOUCHPAD_VIRTUAL_SIZE
+CONFIG_TRICKLE_CHARGING
+CONFIG_TUSB544_EQ_BY_REGISTER
+CONFIG_UART_BAUD_RATE
+CONFIG_UART_HOST
+CONFIG_UART_HOST_COMMAND_BAUD_RATE
+CONFIG_UART_HOST_COMMAND_HW
+CONFIG_UART_INPUT_FILTER
+CONFIG_UART_PAD_SWITCH
+CONFIG_UART_RX_BUF_SIZE
+CONFIG_UART_RX_DMA
+CONFIG_UART_RX_DMA_CH
+CONFIG_UART_RX_DMA_RECHECKS
+CONFIG_UART_RX_REQ_CH
+CONFIG_UART_TX_BUF_SIZE
+CONFIG_UART_TX_DMA
+CONFIG_UART_TX_DMA_CH
+CONFIG_UART_TX_DMA_PH
+CONFIG_UART_TX_REQ_CH
+CONFIG_UNDEFINED
+CONFIG_UPDATE_PDU_SIZE
+CONFIG_USART_HOST_COMMAND
+CONFIG_USB
+CONFIG_USBC_BACKWARDS_COMPATIBLE_DFP
+CONFIG_USBC_DISABLE_CHARGE_FROM_RP_DEF
+CONFIG_USBC_RETIMER_NB7V904M
+CONFIG_USBC_RETIMER_PI3DPX1207
+CONFIG_USBC_RETIMER_PI3HDX1204
+CONFIG_USBC_RETIMER_PS8802
+CONFIG_USBC_RETIMER_TUSB544
+CONFIG_USBC_SS_MUX_UFP_ONLY
+CONFIG_USBC_VCONN_SWAP_DELAY_US
+CONFIG_USB_
+CONFIG_USB_ALT_MODE_ADAPTER
+CONFIG_USB_BOS
+CONFIG_USB_CONSOLE
+CONFIG_USB_CONSOLE_CRC
+CONFIG_USB_CONSOLE_READ
+CONFIG_USB_CONSOLE_STREAM
+CONFIG_USB_CONSOLE_TX_BUF_SIZE
+CONFIG_USB_DWC_FS
+CONFIG_USB_FRS
+CONFIG_USB_GPIO
+CONFIG_USB_HID
+CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS
+CONFIG_USB_HID_KEYBOARD
+CONFIG_USB_HID_KEYBOARD_BACKLIGHT
+CONFIG_USB_HID_KEYBOARD_VIVALDI
+CONFIG_USB_HID_TOUCHPAD
+CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE
+CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X
+CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y
+CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X
+CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y
+CONFIG_USB_HUB_GL3590
+CONFIG_USB_I2C
+CONFIG_USB_I2C_MAX_READ_COUNT
+CONFIG_USB_I2C_MAX_WRITE_COUNT
+CONFIG_USB_INHIBIT_CONNECT
+CONFIG_USB_INHIBIT_INIT
+CONFIG_USB_ISOCHRONOUS
+CONFIG_USB_MAXPOWER_MA
+CONFIG_USB_MUX_AMD_FP5
+CONFIG_USB_MUX_ANX3443
+CONFIG_USB_MUX_ANX7440
+CONFIG_USB_MUX_ANX7451
+CONFIG_USB_MUX_AP_ACK_REQUEST
+CONFIG_USB_MUX_IT5205H_SBU_OVP
+CONFIG_USB_MUX_PI3USB30532
+CONFIG_USB_MUX_PI3USB31532
+CONFIG_USB_MUX_PS8740
+CONFIG_USB_MUX_PS8742
+CONFIG_USB_MUX_PS8822
+CONFIG_USB_PAIRING
+CONFIG_USB_PD_3A_PORTS
+CONFIG_USB_PD_5V_EN_ACTIVE_LOW
+CONFIG_USB_PD_ALT_MODE_UFP_DP
+CONFIG_USB_PD_ANX7688
+CONFIG_USB_PD_CHECK_MAX_REQUEST_ALLOWED
+CONFIG_USB_PD_COMM_DISABLED
+CONFIG_USB_PD_COMM_LOCKED
+CONFIG_USB_PD_CUSTOM_PDO
+CONFIG_USB_PD_DEBUG_DR
+CONFIG_USB_PD_DYNAMIC_SRC_CAP
+CONFIG_USB_PD_FLASH
+CONFIG_USB_PD_FLASH_ERASE_CHECK
+CONFIG_USB_PD_GIVE_BACK
+CONFIG_USB_PD_HW_DEV_ID_BOARD_MAJOR
+CONFIG_USB_PD_HW_DEV_ID_BOARD_MINOR
+CONFIG_USB_PD_I2C_ADDR_FLAGS
+CONFIG_USB_PD_IDENTITY_HW_VERS
+CONFIG_USB_PD_IDENTITY_SW_VERS
+CONFIG_USB_PD_INITIAL_DRP_STATE
+CONFIG_USB_PD_INTERNAL_COMP
+CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT
+CONFIG_USB_PD_LOW_POWER
+CONFIG_USB_PD_LOW_POWER_IDLE_WHEN_CONNECTED
+CONFIG_USB_PD_MANUFACTURER_INFO
+CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
+CONFIG_USB_PD_MAX_TOTAL_SOURCE_CURRENT
+CONFIG_USB_PD_MODEL_PART_NUMBER
+CONFIG_USB_PD_PCIE_TUNNELING
+CONFIG_USB_PD_PORT_LABEL
+CONFIG_USB_PD_PORT_MAX_COUNT
+CONFIG_USB_PD_PREFER_MV
+CONFIG_USB_PD_PRODUCT_REVISION
+CONFIG_USB_PD_RESET_MIN_BATT_SOC
+CONFIG_USB_PD_RX_COMP_IRQ
+CONFIG_USB_PD_SECURITY_MSGS
+CONFIG_USB_PD_SIMPLE_DFP
+CONFIG_USB_PD_TBT_GEN3_CAPABLE
+CONFIG_USB_PD_TCPC
+CONFIG_USB_PD_TCPC_BOARD_INIT
+CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
+CONFIG_USB_PD_TCPC_ON_CHIP
+CONFIG_USB_PD_TCPC_TRACK_VBUS
+CONFIG_USB_PD_TCPMV1
+CONFIG_USB_PD_TCPMV1_DEBUG
+CONFIG_USB_PD_TCPMV2
+CONFIG_USB_PD_TCPM_ANX3429
+CONFIG_USB_PD_TCPM_ANX740X
+CONFIG_USB_PD_TCPM_ANX741X
+CONFIG_USB_PD_TCPM_ANX74XX
+CONFIG_USB_PD_TCPM_ANX7688
+CONFIG_USB_PD_TCPM_FUSB307
+CONFIG_USB_PD_TCPM_MT6370
+CONFIG_USB_PD_TCPM_PS8
+CONFIG_USB_PD_TCPM_PS8705
+CONFIG_USB_PD_TCPM_PS875
+CONFIG_USB_PD_TCPM_PS8751_CUSTOM_MUX_DRIVER
+CONFIG_USB_PD_TCPM_PS8755
+CONFIG_USB_PD_TCPM_STM32GX
+CONFIG_USB_PD_TCPM_STUB
+CONFIG_USB_PD_TID
+CONFIG_USB_PD_TRY_SRC_MIN_BATT_SOC
+CONFIG_USB_PD_TX_PHY_ONLY
+CONFIG_USB_PD_USB4_DRD
+CONFIG_USB_PD_VBUS_DETECT_GPIO
+CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE
+CONFIG_USB_PORT_POWER_SMART_PORT_COUNT
+CONFIG_USB_POWER
+CONFIG_USB_RAM_ACCESS_SIZE
+CONFIG_USB_RAM_ACCESS_TYPE
+CONFIG_USB_RAM_BASE
+CONFIG_USB_RAM_SIZE
+CONFIG_USB_REMOTE_WAKEUP
+CONFIG_USB_SERIALNO
+CONFIG_USB_SPI
+CONFIG_USB_SPI_BUFFER_SIZE
+CONFIG_USB_SPI_FLASH_EXTENSIONS
+CONFIG_USB_SPI_IGNORE_HOST_SIDE_ENABLE
+CONFIG_USB_SUSPEND
+CONFIG_USB_UPDATE
+CONFIG_VALUE
+CONFIG_VBOOT_EFS
+CONFIG_WATCHDOG_HELP
+CONFIG_WATCHDOG_MAX_RETRIES
+CONFIG_WEBUSB_URL
+CONFIG_WIRELESS
+CONFIG_WIRELESS_SUSPEND
+CONFIG_WLAN_POWER_ACTIVE_LOW
+CONFIG_WOV_FIFO_THRESH_WORDS
+CONFIG_WOV_THRESHOLD_WORDS
+CONFIG_WP_ACTIVE_HIGH
+CONFIG_WP_ALWAYS
+CONFIG_WP_STORAGE_OFF
+CONFIG_WP_STORAGE_SIZE
+CONFIG_ZEPHYR
+CONFIG_xxx
diff --git a/util/config_option_check.py b/util/config_option_check.py
index f4262430aa..a3e92306d3 100755
--- a/util/config_option_check.py
+++ b/util/config_option_check.py
@@ -1,13 +1,15 @@
 #!/usr/bin/env python3
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
+
 """Configuration Option Checker.
 
 Script to ensure that all configuration options for the Chrome EC are defined
 in config.h.
 """
 from __future__ import print_function
+
 import enum
 import os
 import re
@@ -15,362 +17,407 @@
 import sys
 
 
-class Line(object):
-  """Class for each changed line in diff output.
+class Line:
+    """Class for each changed line in diff output.
 
-  Attributes:
-    line_num: The integer line number that this line appears in the file.
-    string: The literal string of this line.
-    line_type: '+' or '-' indicating if this line was an addition or
-      deletion.
-  """
+    Attributes:
+      line_num: The integer line number that this line appears in the file.
+      string: The literal string of this line.
+      line_type: '+' or '-' indicating if this line was an addition or
+        deletion.
+    """
 
-  def __init__(self, line_num, string, line_type):
-    """Inits Line with the line number and the actual string."""
-    self.line_num = line_num
-    self.string = string
-    self.line_type = line_type
+    def __init__(self, line_num, string, line_type):
+        """Inits Line with the line number and the actual string."""
+        self.line_num = line_num
+        self.string = string
+        self.line_type = line_type
 
 
-class Hunk(object):
-  """Class for a git diff hunk.
+class Hunk:
+    """Class for a git diff hunk.
 
-  Attributes:
-    filename: The name of the file that this hunk belongs to.
-    lines: A list of Line objects that are a part of this hunk.
-  """
+    Attributes:
+      filename: The name of the file that this hunk belongs to.
+      lines: A list of Line objects that are a part of this hunk.
+    """
 
-  def __init__(self, filename, lines):
-    """Inits Hunk with the filename and the list of lines of the hunk."""
-    self.filename = filename
-    self.lines = lines
+    def __init__(self, filename, lines):
+        """Inits Hunk with the filename and the list of lines of the hunk."""
+        self.filename = filename
+        self.lines = lines
 
 
 # Master file which is supposed to include all CONFIG_xxxx descriptions.
-CONFIG_FILE = 'include/config.h'
+CONFIG_FILE = "include/config.h"
 
 # Specific files which the checker should ignore.
-ALLOWLIST = [CONFIG_FILE, 'util/config_option_check.py']
+ALLOWLIST = [CONFIG_FILE, "util/config_option_check.py"]
+
+# Specific directories which the checker should ignore.
+ALLOW_PATTERN = re.compile("zephyr/.*")
+
+# Specific CONFIG_* flags which the checker should ignore.
+ALLOWLIST_CONFIGS = ["CONFIG_ZTEST"]
+
 
 def obtain_current_config_options():
-  """Obtains current config options from include/config.h.
-
-  Scans through the master config file defined in CONFIG_FILE for all CONFIG_*
-  options.
-
-  Returns:
-    config_options: A list of all the config options in the master CONFIG_FILE.
-  """
-
-  config_options = []
-  config_option_re = re.compile(r'^#(define|undef)\s+(CONFIG_[A-Z0-9_]+)')
-  with open(CONFIG_FILE, 'r') as config_file:
-    for line in config_file:
-      result = config_option_re.search(line)
-      if not result:
-        continue
-      word = result.groups()[1]
-      if word not in config_options:
-        config_options.append(word)
-  return config_options
+    """Obtains current config options from include/config.h.
+
+    Scans through the main config file defined in CONFIG_FILE for all CONFIG_*
+    options.
+
+    Returns:
+      config_options: A list of all the config options in the main CONFIG_FILE.
+    """
+
+    config_options = []
+    config_option_re = re.compile(r"^#(define|undef)\s+(CONFIG_[A-Z0-9_]+)")
+    with open(CONFIG_FILE, "r") as config_file:
+        for line in config_file:
+            result = config_option_re.search(line)
+            if not result:
+                continue
+            word = result.groups()[1]
+            if word not in config_options:
+                config_options.append(word)
+    return config_options
+
 
 def obtain_config_options_in_use():
-  """Obtains all the config options in use in the repo.
-
-  Scans through the entire repo looking for all CONFIG_* options actively used.
-
-  Returns:
-   options_in_use: A set of all the config options in use in the repo.
-  """
-  file_list = []
-  cwd = os.getcwd()
-  config_option_re = re.compile(r'\b(CONFIG_[a-zA-Z0-9_]+)')
-  config_debug_option_re = re.compile(r'\b(CONFIG_DEBUG_[a-zA-Z0-9_]+)')
-  options_in_use = set()
-  for (dirpath, dirnames, filenames) in os.walk(cwd, topdown=True):
-    # Ignore the build and private directories (taken from .gitignore)
-    if 'build' in dirnames:
-      dirnames.remove('build')
-    if 'private' in dirnames:
-      dirnames.remove('private')
-    for f in filenames:
-      # Ignore hidden files.
-      if f.startswith('.'):
-        continue
-      # Only consider C source, assembler, and Make-style files.
-      if (os.path.splitext(f)[1] in ('.c', '.h', '.inc', '.S', '.mk') or
-          'Makefile' in f):
-        file_list.append(os.path.join(dirpath, f))
-
-  # Search through each file and build a set of the CONFIG_* options being
-  # used.
-
-  for f in file_list:
-    if CONFIG_FILE in f:
-      continue
-    with open(f, 'r') as cur_file:
-      for line in cur_file:
-        match = config_option_re.findall(line)
-        if match:
-          for option in match:
-            if not in_comment(f, line, option):
-              if option not in options_in_use:
-                options_in_use.add(option)
-
-  # Since debug options can be turned on at any time, assume that they are
-  # always in use in case any aren't being used.
-
-  with open(CONFIG_FILE, 'r') as config_file:
-    for line in config_file:
-      match = config_debug_option_re.findall(line)
-      if match:
-        for option in match:
-          if not in_comment(CONFIG_FILE, line, option):
-            if option not in options_in_use:
-              options_in_use.add(option)
-
-  return options_in_use
+    """Obtains all the config options in use in the repo.
+
+    Scans through the entire repo looking for all CONFIG_* options actively used.
+
+    Returns:
+     options_in_use: A set of all the config options in use in the repo.
+    """
+    file_list = []
+    cwd = os.getcwd()
+    config_option_re = re.compile(r"\b(CONFIG_[a-zA-Z0-9_]+)")
+    config_debug_option_re = re.compile(r"\b(CONFIG_DEBUG_[a-zA-Z0-9_]+)")
+    options_in_use = set()
+    for (dirpath, dirnames, filenames) in os.walk(cwd, topdown=True):
+        # Ignore the build and private directories (taken from .gitignore)
+        for i in range(len(dirnames) - 1, -1, -1):
+            if (
+                dirnames[i] == "build"
+                or dirnames[i] == "private"
+                or dirnames[i].startswith("twister-out")
+            ):
+                del dirnames[i]
+        for file in filenames:
+            # Ignore hidden files.
+            if file.startswith("."):
+                continue
+            # Only consider C source, assembler, and Make-style files.
+            if (
+                os.path.splitext(file)[1] in (".c", ".h", ".inc", ".S", ".mk")
+                or "Makefile" in file
+            ):
+                file_list.append(os.path.join(dirpath, file))
+
+    # Search through each file and build a set of the CONFIG_* options being
+    # used.
+
+    for file in file_list:
+        if CONFIG_FILE in file:
+            continue
+        with open(file, "r") as cur_file:
+            for line in cur_file:
+                match = config_option_re.findall(line)
+                if match:
+                    for option in match:
+                        if not in_comment(file, line, option):
+                            if option not in options_in_use:
+                                options_in_use.add(option)
+
+    # Since debug options can be turned on at any time, assume that they are
+    # always in use in case any aren't being used.
+
+    with open(CONFIG_FILE, "r") as config_file:
+        for line in config_file:
+            match = config_debug_option_re.findall(line)
+            if match:
+                for option in match:
+                    if not in_comment(CONFIG_FILE, line, option):
+                        if option not in options_in_use:
+                            options_in_use.add(option)
+
+    return options_in_use
+
 
 def print_missing_config_options(hunks, config_options):
-  """Searches thru all the changes in hunks for missing options and prints them.
-
-  Args:
-    hunks: A list of Hunk objects which represent the hunks from the git
-      diff output.
-    config_options: A list of all the config options in the master CONFIG_FILE.
-
-  Returns:
-    missing_config_option: A boolean indicating if any CONFIG_* options
-      are missing from the master CONFIG_FILE in this commit or if any CONFIG_*
-      options removed are no longer being used in the repo.
-  """
-  missing_config_option = False
-  print_banner = True
-  deprecated_options = set()
-  # Determine longest CONFIG_* length to be used for formatting.
-  max_option_length = max(len(option) for option in config_options)
-  config_option_re = re.compile(r'\b(CONFIG_[a-zA-Z0-9_]+)')
-
-  # Search for all CONFIG_* options in use in the repo.
-  options_in_use = obtain_config_options_in_use()
-
-  # Check each hunk's line for a missing config option.
-  for h in hunks:
-    for l in h.lines:
-      # Check for the existence of a CONFIG_* in the line.
-      match = config_option_re.findall(l.string)
-      if not match:
-        continue
-
-      # At this point, an option was found in the line.  However, we need to
-      # verify that it is not within a comment.
-      violations = set()
-
-      for option in match:
-        if not in_comment(h.filename, l.string, option):
-          # Since the CONFIG_* option is not within a comment, we've found a
-          # violation.  We now need to determine if this line is a deletion or
-          # not.  For deletions, we will need to verify if this CONFIG_* option
-          # is no longer being used in the entire repo.
-
-          if l.line_type == '-':
-            if option not in options_in_use and option in config_options:
-              deprecated_options.add(option)
-          else:
-            violations.add(option)
-
-      # Check to see if the CONFIG_* option is in the config file and print the
-      # violations.
-      for option in match:
-        if option not in config_options and option in violations:
-          # Print the banner once.
-          if print_banner:
-            print('The following config options were found to be missing '
-                  'from %s.\n'
-                  'Please add new config options there along with '
-                  'descriptions.\n\n' % CONFIG_FILE)
-            print_banner = False
+    """Searches thru all the changes in hunks for missing options and prints them.
+
+    Args:
+      hunks: A list of Hunk objects which represent the hunks from the git
+        diff output.
+      config_options: A list of all the config options in the main CONFIG_FILE.
+
+    Returns:
+      missing_config_option: A boolean indicating if any CONFIG_* options
+        are missing from the main CONFIG_FILE in this commit or if any CONFIG_*
+        options removed are no longer being used in the repo.
+    """
+    missing_config_option = False
+    print_banner = True
+    deprecated_options = set()
+    # Determine longest CONFIG_* length to be used for formatting.
+    max_option_length = max(len(option) for option in config_options)
+    config_option_re = re.compile(r"\b(CONFIG_[a-zA-Z0-9_]+)")
+
+    # Search for all CONFIG_* options in use in the repo.
+    options_in_use = obtain_config_options_in_use()
+
+    # Check each hunk's line for a missing config option.
+    for hunk in hunks:
+        for line in hunk.lines:
+            # Check for the existence of a CONFIG_* in the line.
+            match = filter(
+                lambda opt: opt in ALLOWLIST_CONFIGS,
+                config_option_re.findall(line.string),
+            )
+            if not match:
+                continue
+
+            # At this point, an option was found in the line.  However, we need to
+            # verify that it is not within a comment.
+            violations = set()
+
+            for option in match:
+                if not in_comment(hunk.filename, line.string, option):
+                    # Since the CONFIG_* option is not within a comment, we've found a
+                    # violation.  We now need to determine if this line is a deletion or
+                    # not.  For deletions, we will need to verify if this CONFIG_* option
+                    # is no longer being used in the entire repo.
+
+                    if line.line_type == "-":
+                        if (
+                            option not in options_in_use
+                            and option in config_options
+                        ):
+                            deprecated_options.add(option)
+                    else:
+                        violations.add(option)
+
+            # Check to see if the CONFIG_* option is in the config file and print the
+            # violations.
+            for option in match:
+                if option not in config_options and option in violations:
+                    # Print the banner once.
+                    if print_banner:
+                        print(
+                            "The following config options were found to be missing "
+                            "from %s.\n"
+                            "Please add new config options there along with "
+                            "descriptions.\n\n" % CONFIG_FILE
+                        )
+                        print_banner = False
+                        missing_config_option = True
+                    # Print the misssing config option.
+                    print(
+                        "> %-*s %s:%s"
+                        % (
+                            max_option_length,
+                            option,
+                            hunk.filename,
+                            line.line_num,
+                        )
+                    )
+
+    if deprecated_options:
+        print(
+            "\n\nThe following config options are being removed and also appear"
+            " to be the last uses\nof that option.  Please remove these "
+            "options from %s.\n\n" % CONFIG_FILE
+        )
+        for option in deprecated_options:
+            print("> %s" % option)
             missing_config_option = True
-          # Print the misssing config option.
-          print('> %-*s %s:%s' % (max_option_length, option,
-                                  h.filename,
-                                  l.line_num))
 
-  if deprecated_options:
-    print('\n\nThe following config options are being removed and also appear'
-          ' to be the last uses\nof that option.  Please remove these '
-          'options from %s.\n\n' % CONFIG_FILE)
-    for option in deprecated_options:
-      print('> %s' % option)
-      missing_config_option = True
+    return missing_config_option
 
-  return missing_config_option
 
 def in_comment(filename, line, substr):
-  """Checks if given substring appears in a comment.
-
-  Args:
-    filename: The filename where this line is from.  This is used to determine
-      what kind of comments to look for.
-    line: String of line to search in.
-    substr: Substring to search for in the line.
-
-  Returns:
-    is_in_comment: Boolean indicating if substr was in a comment.
-  """
-
-  c_style_ext = ('.c', '.h', '.inc', '.S')
-  make_style_ext = ('.mk')
-  is_in_comment = False
-
-  extension = os.path.splitext(filename)[1]
-  substr_idx = line.find(substr)
-
-  # Different files have different comment syntax;  Handle appropriately.
-  if extension in c_style_ext:
-    beg_comment_idx = line.find('/*')
-    end_comment_idx = line.find('*/')
-    if end_comment_idx == -1:
-      end_comment_idx = len(line)
-
-    if beg_comment_idx == -1:
-      # Check to see if this line is from a multi-line comment.
-      if line.lstrip().startswith('* '):
-        # It _seems_ like it is.
-        is_in_comment = True
-    else:
-      # Check to see if its actually inside the comment.
-      if beg_comment_idx < substr_idx < end_comment_idx:
-        is_in_comment = True
-  elif extension in make_style_ext or 'Makefile' in filename:
-    beg_comment_idx = line.find('#')
-    # Ignore everything to the right of the hash.
-    if beg_comment_idx < substr_idx and beg_comment_idx != -1:
-      is_in_comment = True
-  return is_in_comment
+    """Checks if given substring appears in a comment.
+
+    Args:
+      filename: The filename where this line is from.  This is used to determine
+        what kind of comments to look for.
+      line: String of line to search in.
+      substr: Substring to search for in the line.
+
+    Returns:
+      is_in_comment: Boolean indicating if substr was in a comment.
+    """
+
+    c_style_ext = (".c", ".h", ".inc", ".S")
+    make_style_ext = ".mk"
+    is_in_comment = False
+
+    extension = os.path.splitext(filename)[1]
+    substr_idx = line.find(substr)
+
+    # Different files have different comment syntax;  Handle appropriately.
+    if extension in c_style_ext:
+        beg_comment_idx = line.find("/*")
+        end_comment_idx = line.find("*/")
+        if end_comment_idx == -1:
+            end_comment_idx = len(line)
+
+        if beg_comment_idx == -1:
+            # Check to see if this line is from a multi-line comment.
+            if line.lstrip().startswith("* "):
+                # It _seems_ like it is.
+                is_in_comment = True
+        else:
+            # Check to see if its actually inside the comment.
+            if beg_comment_idx < substr_idx < end_comment_idx:
+                is_in_comment = True
+    elif extension in make_style_ext or "Makefile" in filename:
+        beg_comment_idx = line.find("#")
+        # Ignore everything to the right of the hash.
+        if beg_comment_idx < substr_idx and beg_comment_idx != -1:
+            is_in_comment = True
+    return is_in_comment
+
 
 def get_hunks():
-  """Gets the hunks of the most recent commit.
-
-  States:
-    new_file: Searching for a new file in the git diff.
-    filename_search: Searching for the filename of this hunk.
-    hunk: Searching for the beginning of a new hunk.
-    lines: Counting line numbers and searching for changes.
-
-  Returns:
-    hunks: A list of Hunk objects which represent the hunks in the git diff
-      output.
-  """
-
-  diff = []
-  hunks = []
-  hunk_lines = []
-  line = ''
-  filename = ''
-  i = 0
-  line_num = 0
-
-  # Regex patterns
-  new_file_re = re.compile(r'^diff --git')
-  filename_re = re.compile(r'^[+]{3} (.*)')
-  hunk_line_num_re = re.compile(r'^@@ -[0-9]+,[0-9]+ \+([0-9]+),[0-9]+ @@.*')
-  line_re = re.compile(r'^([+| |-])(.*)')
-
-  # Get the diff output.
-  proc = subprocess.run(['git', 'diff', '--cached', '-GCONFIG_*', '--no-prefix',
-                         '--no-ext-diff', 'HEAD~1'],
-                        stdout=subprocess.PIPE,
-                        encoding='utf-8',
-                        check=True)
-  diff = proc.stdout.splitlines()
-  if not diff:
-    return []
-  line = diff[0]
-
-  state = enum.Enum('state', 'NEW_FILE FILENAME_SEARCH HUNK LINES')
-  current_state = state.NEW_FILE
-
-  while True:
-    # Search for the beginning of a new file.
-    if current_state is state.NEW_FILE:
-      match = new_file_re.search(line)
-      if match:
-        current_state = state.FILENAME_SEARCH
-
-    # Search the diff output for a file name.
-    elif current_state is state.FILENAME_SEARCH:
-      # Search for a file name.
-      match = filename_re.search(line)
-      if match:
-        filename = match.groups(1)[0]
-        if filename in ALLOWLIST:
-          # Skip the file if it's allowlisted.
-          current_state = state.NEW_FILE
-        else:
-          current_state = state.HUNK
-
-    # Search for a hunk.  Each hunk starts with a line describing the line
-    # numbers in the file.
-    elif current_state is state.HUNK:
-      hunk_lines = []
-      match = hunk_line_num_re.search(line)
-      if match:
-        # Extract the line number offset.
-        line_num = int(match.groups(1)[0])
-        current_state = state.LINES
-
-    # Start looking for changes.
-    elif current_state is state.LINES:
-      # Check if state needs updating.
-      new_hunk = hunk_line_num_re.search(line)
-      new_file = new_file_re.search(line)
-      if new_hunk:
-        current_state = state.HUNK
-        hunks.append(Hunk(filename, hunk_lines))
-        continue
-      elif new_file:
-        current_state = state.NEW_FILE
-        hunks.append(Hunk(filename, hunk_lines))
-        continue
-
-      match = line_re.search(line)
-      if match:
-        line_type = match.groups(1)[0]
-        # We only care about modifications.
-        if line_type != ' ':
-          hunk_lines.append(Line(line_num, match.groups(2)[1], line_type))
-        # Deletions don't count towards the line numbers.
-        if line_type != '-':
-          line_num += 1
-
-    # Advance to the next line
-    try:
-      i += 1
-      line = diff[i]
-    except IndexError:
-      # We've reached the end of the diff.  Return what we have.
-      if hunk_lines:
-        hunks.append(Hunk(filename, hunk_lines))
-      return hunks
+    """Gets the hunks of the most recent commit.
+
+    States:
+      new_file: Searching for a new file in the git diff.
+      filename_search: Searching for the filename of this hunk.
+      hunk: Searching for the beginning of a new hunk.
+      lines: Counting line numbers and searching for changes.
+
+    Returns:
+      hunks: A list of Hunk objects which represent the hunks in the git diff
+        output.
+    """
+
+    diff = []
+    hunks = []
+    hunk_lines = []
+    line = ""
+    filename = ""
+    i = 0
+    line_num = 0
+
+    # Regex patterns
+    new_file_re = re.compile(r"^diff --git")
+    filename_re = re.compile(r"^[+]{3} (.*)")
+    hunk_line_num_re = re.compile(r"^@@ -[0-9]+,[0-9]+ \+([0-9]+),[0-9]+ @@.*")
+    line_re = re.compile(r"^([+| |-])(.*)")
+
+    # Get the diff output.
+    proc = subprocess.run(
+        [
+            "git",
+            "diff",
+            "--cached",
+            "-GCONFIG_*",
+            "--no-prefix",
+            "--no-ext-diff",
+            "HEAD~1",
+        ],
+        stdout=subprocess.PIPE,
+        encoding="utf-8",
+        check=True,
+    )
+    diff = proc.stdout.splitlines()
+    if not diff:
+        return []
+    line = diff[0]
+
+    state = enum.Enum("state", "NEW_FILE FILENAME_SEARCH HUNK LINES")
+    current_state = state.NEW_FILE
+
+    while True:
+        # Search for the beginning of a new file.
+        if current_state is state.NEW_FILE:
+            match = new_file_re.search(line)
+            if match:
+                current_state = state.FILENAME_SEARCH
+
+        # Search the diff output for a file name.
+        elif current_state is state.FILENAME_SEARCH:
+            # Search for a file name.
+            match = filename_re.search(line)
+            if match:
+                filename = match.groups(1)[0]
+                if filename in ALLOWLIST or ALLOW_PATTERN.match(filename):
+                    # Skip the file if it's allowlisted.
+                    current_state = state.NEW_FILE
+                else:
+                    current_state = state.HUNK
+
+        # Search for a hunk.  Each hunk starts with a line describing the line
+        # numbers in the file.
+        elif current_state is state.HUNK:
+            hunk_lines = []
+            match = hunk_line_num_re.search(line)
+            if match:
+                # Extract the line number offset.
+                line_num = int(match.groups(1)[0])
+                current_state = state.LINES
+
+        # Start looking for changes.
+        elif current_state is state.LINES:
+            # Check if state needs updating.
+            new_hunk = hunk_line_num_re.search(line)
+            new_file = new_file_re.search(line)
+            if new_hunk:
+                current_state = state.HUNK
+                hunks.append(Hunk(filename, hunk_lines))
+                continue
+            if new_file:
+                current_state = state.NEW_FILE
+                hunks.append(Hunk(filename, hunk_lines))
+                continue
+
+            match = line_re.search(line)
+            if match:
+                line_type = match.groups(1)[0]
+                # We only care about modifications.
+                if line_type != " ":
+                    hunk_lines.append(
+                        Line(line_num, match.groups(2)[1], line_type)
+                    )
+                # Deletions don't count towards the line numbers.
+                if line_type != "-":
+                    line_num += 1
+
+        # Advance to the next line
+        try:
+            i += 1
+            line = diff[i]
+        except IndexError:
+            # We've reached the end of the diff.  Return what we have.
+            if hunk_lines:
+                hunks.append(Hunk(filename, hunk_lines))
+            return hunks
+
 
 def main():
-  """Searches through committed changes for missing config options.
-
-  Checks through committed changes for CONFIG_* options.  Then checks to make
-  sure that all CONFIG_* options used are defined in include/config.h.  Finally,
-  reports any missing config options.
-  """
-  # Obtain the hunks of the commit to search through.
-  hunks = get_hunks()
-  # Obtain config options from include/config.h.
-  config_options = obtain_current_config_options()
-  # Find any missing config options from the hunks and print them.
-  missing_opts = print_missing_config_options(hunks, config_options)
-
-  if missing_opts:
-    print('\nIt may also be possible that you have a typo.')
-    sys.exit(1)
-
-if __name__ == '__main__':
-  main()
+    """Searches through committed changes for missing config options.
+
+    Checks through committed changes for CONFIG_* options.  Then checks to make
+    sure that all CONFIG_* options used are defined in include/config.h.  Finally,
+    reports any missing config options.
+    """
+    # Obtain the hunks of the commit to search through.
+    hunks = get_hunks()
+    # Obtain config options from include/config.h.
+    config_options = obtain_current_config_options()
+    # Find any missing config options from the hunks and print them.
+    missing_opts = print_missing_config_options(hunks, config_options)
+
+    if missing_opts:
+        print("\nIt may also be possible that you have a typo.")
+        sys.exit(1)
+
+
+if __name__ == "__main__":
+    main()
diff --git a/util/corsola-relevant-paths.txt b/util/corsola-relevant-paths.txt
new file mode 100644
index 0000000000..311ac06780
--- /dev/null
+++ b/util/corsola-relevant-paths.txt
@@ -0,0 +1,31 @@
+# Here you can place files of interest to be included in the commit message for
+# merge commits to cros/firmware-corsola-15194.B
+common/charge_state.c
+common/dps.c
+common/mkbp_*
+common/usb_charger.c
+common/usb_common.c
+common/usbc/*_pd_*
+common/usbc/dp_alt_mode.c
+common/usbc/usb_pe_drp_sm.c
+common/usbc/usb_prl_sm.c
+common/usbc/usb_sm.c
+common/usbc/usb_tc_drp_acc_trysrc_sm.c
+driver/battery/smart.c
+driver/bc12/pi3usb9201.*
+driver/charger/isl923x.*
+driver/charger/rt949*
+driver/ppc/nx20p348x.*
+driver/ppc/rt1718s.*
+driver/ppc/syv682x.*
+driver/tcpm/anx7447.*
+driver/tcpm/rt1718s.*
+driver/tcpm/tcpci.*
+driver/usb_mux/it5205.*
+driver/usb_mux/ps8743.*
+power/mt8186.c
+zephyr/boards/arm/npcx9/*
+zephyr/boards/riscv/it8xxx2/*
+zephyr/drivers/*
+zephyr/program/corsola/*
+zephyr/shim/*
diff --git a/util/crash_analyzer.py b/util/crash_analyzer.py
new file mode 100755
index 0000000000..1839c01b28
--- /dev/null
+++ b/util/crash_analyzer.py
@@ -0,0 +1,461 @@
+#!/usr/bin/env python3
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""EC Crash report analyzer"""
+
+import argparse
+import pathlib
+import re
+import sys
+
+
+# TODO(b/253492108): Add regexp for missing architectures.
+# Regex tested here: https://regex101.com/r/K5S8cB/1
+_REGEX_CORTEX_M0 = (
+    r"^Saved.*$\n=== .* EXCEPTION: (.*) ====== xPSR: (.*) ===$\n"
+    r"r0 :(.*) r1 :(.*) r2 :(.*) r3 :(.*)$\n"
+    r"r4 :(.*) r5 :(.*) r6 :(.*) r7 :(.*)$\n"
+    r"r8 :(.*) r9 :(.*) r10:(.*) r11:(.*)$\n"
+    r"r12:(.*) sp :(.*) lr :(.*) pc :(.*)$\n"
+    r"\n"
+    r"^.*cfsr=(.*), shcsr=(.*), hfsr=(.*), dfsr=(.*), ipsr=(.*)$"
+)
+
+# Regex tested here: https://regex101.com/r/FL7T0n/1
+_REGEX_NDS32 = (
+    r"^Saved.*$\n===.*ITYPE=(.*) ===$\n"
+    r"R0  (.*) R1  (.*) R2  (.*) R3  (.*)$\n"
+    r"R4  (.*) R5  (.*) R6  (.*) R7  (.*)$\n"
+    r"R8  (.*) R9  (.*) R10 (.*) R15 (.*)$\n"
+    r"FP  (.*) GP  (.*) LP  (.*) SP  (.*)$\n"
+    r"IPC (.*) IPSW (.*)$\n"
+)
+
+
+# List of symbols. Each entry is tuple: address, name
+_symbols = []
+# List of crashes. Each entry is dictionary.
+# Contains all crashes found.
+_entries = []
+
+
+# This is function, and not a global dictionary, so that
+# we can reference the different functions without placing
+# the functions above the dictionary.
+def get_architectures() -> list:
+    """Returns a dictionary with the supported architectures"""
+
+    archs = {
+        "cm0": {
+            "regex": _REGEX_CORTEX_M0,
+            "parser": cm0_parse,
+            "extra_regs": [
+                "sp",
+                "lr",
+                "pc",
+                "cfsr",
+                "chcsr",
+                "hfsr",
+                "dfsr",
+                "ipsr",
+            ],
+        },
+        "nds32": {
+            "regex": _REGEX_NDS32,
+            "parser": nds32_parse,
+            "extra_regs": ["fp", "gp", "lp", "sp", "ipc", "ipsw"],
+        },
+    }
+    return archs
+
+
+def get_crash_cause(cause: int) -> str:
+    """Returns the cause of crash in human-readable format"""
+    causes = {
+        0xDEAD6660: "div-by-0",
+        0xDEAD6661: "stack-overflow",
+        0xDEAD6662: "pd-crash",
+        0xDEAD6663: "assert",
+        0xDEAD6664: "watchdog",
+        0xDEAD6665: "bad-rng",
+        0xDEAD6666: "pmic-fault",
+        0xDEAD6667: "exit",
+    }
+
+    if cause in causes:
+        return causes[cause]
+    return f"unknown-cause-{format(cause, '#x')}"
+
+
+def cm0_parse(match) -> dict:
+    """Regex parser for Cortex-M0+ architecture"""
+
+    # Expecting something like:
+    # Saved panic data: (NEW)
+    # === PROCESS EXCEPTION: ff ====== xPSR: ffffffff ===
+    # r0 :         r1 :         r2 :         r3 :
+    # r4 :dead6664 r5 :10092632 r6 :00000000 r7 :00000000
+    # r8 :00000000 r9 :00000000 r10:00000000 r11:00000000
+    # r12:         sp :00000000 lr :         pc :
+    #
+    # cfsr=00000000, shcsr=00000000, hfsr=00000000, dfsr=00000000, ipsr=000000ff
+    regs = {}
+    values = []
+
+    for i in match.groups():
+        try:
+            val = int(i, 16)
+        except ValueError:
+            # Value might be empty, so we must handle the exception
+            val = -1
+        values.append(val)
+
+    regs["task"] = values[0]
+    regs["xPSR"] = values[1]
+    regs["regs"] = values[3:15]
+    regs["sp"] = values[15]
+    regs["lr"] = values[16]
+    regs["pc"] = values[17]
+    regs["cfsr"] = values[18]
+    regs["chcsr"] = values[19]
+    regs["hfsr"] = values[20]
+    regs["dfsr"] = values[21]
+    regs["ipsr"] = values[22]
+
+    regs["cause"] = get_crash_cause(values[6])  # r4
+
+    # When CONFIG_DEBUG_STACK_OVERFLOW is enabled, the task number for a stack
+    # overflow is saved in R5.
+    if regs["cause"] == "stack-overflow":
+        regs["task"] = values[7]  # r5
+
+    # based on crash reports in case of asserrt the PC is in R3
+    if regs["cause"] == "assert":
+        regs["symbol"] = get_symbol(values[5])  # r3
+        return regs
+
+    # Heuristics: try link register, then PC, then what is believed to be PC.
+    # When analyzing watchdogs, we try to be as close as possible to the caller
+    # function that caused the watchdog.
+    # That's why we prioritize LR (return address) over PC.
+    if regs["lr"] != -1:
+        regs["symbol"] = get_symbol(regs["lr"])
+    elif regs["pc"] != -1:
+        regs["symbol"] = get_symbol(regs["pc"])
+    else:
+        # Otherwise, if both LR and PC are empty, most probably
+        # PC is in R5.
+        regs["symbol"] = get_symbol(values[7])  # r5
+
+    return regs
+
+
+def nds32_parse(match) -> dict:
+    """Regex parser for Andes (NDS32) architecture"""
+
+    # Expecting something like:
+    # Saved panic data: (NEW)
+    # === EXCEP: ITYPE=0 ===
+    # R0  00000000 R1  00000000 R2  00000000 R3  00000000
+    # R4  00000000 R5  00000000 R6  dead6664 R7  00000000
+    # R8  00000000 R9  00000000 R10 00000000 R15 00000000
+    # FP  00000000 GP  00000000 LP  00000000 SP  00000000
+    # IPC 00050d5e IPSW   00000
+    # SWID of ITYPE: 0
+    regs = {}
+    values = []
+
+    for i in match.groups():
+        try:
+            val = int(i, 16)
+        except ValueError:
+            # Value might be empty, so we must handle the exception
+            val = -1
+        values.append(val)
+
+    # NDS32 is not reporting task info.
+    regs["task"] = -1
+    regs["regs"] = values[1:13]
+    regs["fp"] = values[13]
+    regs["gp"] = values[14]
+    regs["lp"] = values[15]
+    regs["sp"] = values[16]
+    regs["ipc"] = values[17]
+    regs["ipsw"] = values[18]
+
+    regs["cause"] = get_crash_cause(values[7])  # r6
+    regs["symbol"] = get_symbol(regs["ipc"])
+    return regs
+
+
+def read_map_file(map_file):
+    """Reads the map file, and populates the _symbols list with the tuple address/name"""
+    lines = map_file.readlines()
+    for line in lines:
+        addr_str, _, name = line.split(" ")
+        addr = int(addr_str, 16)
+        _symbols.append((addr, name.strip()))
+
+
+def get_symbol_bisec(addr: int, low: int, high: int) -> str:
+    """Finds the symbol using binary search"""
+    # Element not found.
+    if low > high:
+        return f"invalid address: {format(addr, '#x')}"
+
+    mid = (high + low) // 2
+
+    # Corner case for last element.
+    if mid == len(_symbols) - 1:
+        if addr > _symbols[mid][0]:
+            return f"invalid address: {format(addr, '#x')}"
+        return _symbols[mid][1]
+
+    if _symbols[mid][0] <= addr < _symbols[mid + 1][0]:
+        symbol = _symbols[mid][1]
+        # Start of a sequence of Thumb instructions. When this happens, return
+        # the next address.
+        if symbol == "$t":
+            symbol = _symbols[mid + 1][1]
+        return symbol
+
+    if addr > _symbols[mid][0]:
+        return get_symbol_bisec(addr, mid + 1, high)
+    return get_symbol_bisec(addr, low, mid - 1)
+
+
+def get_symbol(addr: int) -> str:
+    """Returns the function name that corresponds to the given address"""
+    symbol = get_symbol_bisec(addr, 0, len(_symbols) - 1)
+
+    # Symbols generated by the compiler to identify transitions in the
+    # code. If so, just append the address.
+    if symbol in ("$a", "$d", "$c", "$t"):
+        symbol = f"{symbol}:{format(addr,'#x')}"
+    return symbol
+
+
+def process_log_file(file_name: str) -> tuple:
+    """Reads a .log file and extracts the EC and BIOS versions"""
+    ec_ver = None
+    bios_ver = None
+    try:
+        with open(file_name, "r", encoding="ascii") as log_file:
+            lines = log_file.readlines()
+            for line in lines:
+                # Searching for something like:
+                # ===ec_info===
+                # vendor               | Nuvoton
+                # name                 | NPCX586G
+                # fw_version           | rammus_v2.0.460-d1d2aeb01f
+                # ...
+                # ===bios_info===
+                # fwid       =   Google_Rammus.11275.193.0    #   [RO/str] ...
+                # ro_fwid    =   Google_Rammus.11275.28.0     #   [RO/str] ...
+
+                # Get EC version.
+                # There could be more than one "fw_version". Only the first one
+                # corresponds to the EC version.
+                if line.startswith("fw_version") and ec_ver is None:
+                    _, ec_ver = line.split("|")
+                    ec_ver = ec_ver.strip(" \n")
+
+                # Get BIOS version.
+                if line.startswith("fwid"):
+                    _, value = line.split("=")
+                    # Only get the first element.
+                    bios_ver, _ = value.split("#")
+                    bios_ver = bios_ver.strip()
+
+                if ec_ver is not None and bios_ver is not None:
+                    return ec_ver, bios_ver
+
+    except FileNotFoundError:
+        return ".log file not found", "not found"
+    return (
+        "unknown fw version" if ec_ver is None else ec_ver,
+        "unknown BIOS version" if bios_ver is None else bios_ver,
+    )
+
+
+def process_crash_file(filename: str) -> dict:
+    """Process a single crash report, and convert it to a dictionary"""
+
+    with open(filename, "r", encoding="ascii") as crash_file:
+        content = crash_file.read()
+
+        for key, arch in get_architectures().items():
+            regex = arch["regex"]
+            match = re.match(regex, content, re.MULTILINE)
+            if match is None:
+                continue
+            entry = arch["parser"](match)
+
+            # Add "arch" entry since it is needed to process
+            # the "extra_regs", among other things.
+            entry["arch"] = key
+            return entry
+    return {}
+
+
+def process_crash_files(crash_folder: pathlib.Path) -> None:
+    """Process the crash reports that are in the crash_folder"""
+
+    total = 0
+    failed = 0
+    good = 0
+    for file in crash_folder.iterdir():
+        # .log and .upload_file_eccrash might not be in order.
+        # To avoid processing it more than once, only process the
+        # ones with extension ".upload_file_eccrash" and then read the ".log".
+        if file.suffix != ".upload_file_eccrash":
+            continue
+        entry = process_crash_file(file)
+        if len(entry) != 0:
+            ec_ver, bios_ver = process_log_file(
+                file.parent.joinpath(file.stem + ".log")
+            )
+            entry["ec_version"] = ec_ver
+            entry["bios_version"] = bios_ver
+            entry["filename"] = file.stem
+
+        if len(entry) != 0:
+            _entries.append(entry)
+            good += 1
+        else:
+            failed += 1
+        total += 1
+    print(f"Total: {total}, OK: {good}, Failed: {failed}", file=sys.stderr)
+
+
+def cmd_report_lite(crash_folder: pathlib.Path, with_filename: bool) -> None:
+    """Generates a 'lite' report that only contains a few fields"""
+
+    process_crash_files(crash_folder)
+    for entry in _entries:
+        print(
+            f"Task: {format(entry['task'],'#04x')} - "
+            f"cause: {entry['cause']} - "
+            f"PC: {entry['symbol']} - "
+            f"{entry['ec_version']} - "
+            f"{entry['bios_version']}",
+            end="",
+        )
+
+        if with_filename:
+            print(f" - {entry['filename']}", end="")
+
+        print()
+
+
+def cmd_report_full(crash_folder: pathlib.Path, with_filename: bool) -> None:
+    """Generates a full report in .cvs format"""
+
+    process_crash_files(crash_folder)
+    # Print header
+    for entry in _entries:
+        print(
+            f"Task: {format(entry['task'],'#04x')} - "
+            f"cause: {entry['cause']} - "
+            f"PC: {entry['symbol']} - ",
+            end="",
+        )
+        # Print registers
+        hex_regs = [hex(x) for x in entry["regs"]]
+        print(f"{hex_regs} - ", end="")
+
+        # Print extra registers. Varies from architecture to architecture.
+        arch = get_architectures()[entry["arch"]]
+        for reg in arch["extra_regs"]:
+            print(f"{reg}: {format(entry[reg], '#x')} ", end="")
+
+        # Print EC & BIOS info
+        print(
+            f"{entry['ec_version']} - {entry['bios_version']}",
+            end="",
+        )
+
+        # Finally the filename. Useful for debugging.
+        if with_filename:
+            print(f" - {entry['filename']}", end="")
+
+        print()
+
+
+def main(argv):
+    """Main entry point"""
+    example_text = """Example:
+# For further details see: go/cros-ec-crash-analyzer
+#
+# Summary:
+# 1st:
+# Collect the crash reports using this script:
+# https://source.corp.google.com/piper///depot/google3/experimental/users/ricardoq/ec_crash_report_fetcher
+# MUST be run within a Google3 Workspace. E.g:
+(google3) blaze run //experimental/users/ricardoq/ec_crash_report_fetcher:main -- --outdir=/tmp/dumps/ --limit=3000 --offset=15000 --hwclass=shyvana --milestone=105
+
+# 2nd:
+# Assuming that you don't have the .map file of the EC image,  you can download the EC image from LUCI
+# and then parse the .elf file by doing:
+nm -n ec.RW.elf | grep " [tT] " > /tmp/rammus_193.map
+
+# 3rd:
+# Run this script
+crash_analyzer.py full -m /tmp/rammus_193.map -f /tmp/dumps
+
+# Combine it with 'sort' and 'uniq' for better reports. E.g:
+crash_analyzer.py lite -m /tmp/rammus_193.map -f /tmp/dumps | sort | uniq -c | less
+
+# Tip:
+# Start by analyzing the "lite" report. If there is a function that calls your
+# attention, generate the "full" report and analyze with Ghidra and/or
+# IDA Pro the different "PC" that belong to the suspicious function.
+"""
+
+    parser = argparse.ArgumentParser(
+        prog="crash_analyzer",
+        epilog=example_text,
+        description="Process crash reports and converts them to human-friendly format.",
+        formatter_class=argparse.RawDescriptionHelpFormatter,
+    )
+    parser.add_argument(
+        "-m",
+        "--map-file",
+        type=argparse.FileType("r"),
+        required=True,
+        metavar="ec_map_file",
+        help="/path/to/ec_image_map_file",
+    )
+    parser.add_argument(
+        "-f",
+        "--crash-folder",
+        type=pathlib.Path,
+        required=True,
+        help="Folder with the EC crash report files",
+    )
+    parser.add_argument(
+        "-n",
+        "--with-filename",
+        action="store_true",
+        help="Includes the filename in the report. Useful for debugging.",
+    )
+    parser.add_argument(
+        "command", choices=["lite", "full"], help="Command to run."
+    )
+    args = parser.parse_args(argv)
+
+    # Needed for all commands
+    read_map_file(args.map_file)
+
+    if args.command == "lite":
+        cmd_report_lite(args.crash_folder, args.with_filename)
+    elif args.command == "full":
+        cmd_report_full(args.crash_folder, args.with_filename)
+    else:
+        print(f"Unsupported command: {args.command}")
+
+
+if __name__ == "__main__":
+    main(sys.argv[1:])
diff --git a/util/cros_ec_dev.h b/util/cros_ec_dev.h
index 41930f97dd..6421afc601 100644
--- a/util/cros_ec_dev.h
+++ b/util/cros_ec_dev.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,9 +6,10 @@
 #ifndef __UTIL_CROS_EC_DEV_H
 #define __UTIL_CROS_EC_DEV_H
 
+#include "ec_commands.h"
+
 #include <linux/ioctl.h>
 #include <linux/types.h>
-#include "ec_commands.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -50,9 +51,9 @@ struct cros_ec_readmem {
 	char *buffer;
 };
 
-#define CROS_EC_DEV_IOC              ':'
-#define CROS_EC_DEV_IOCXCMD    _IOWR(':', 0, struct cros_ec_command)
-#define CROS_EC_DEV_IOCRDMEM   _IOWR(':', 1, struct cros_ec_readmem)
+#define CROS_EC_DEV_IOC ':'
+#define CROS_EC_DEV_IOCXCMD _IOWR(':', 0, struct cros_ec_command)
+#define CROS_EC_DEV_IOCRDMEM _IOWR(':', 1, struct cros_ec_readmem)
 
 /*
  * @version: Command version number (often 0)
@@ -84,12 +85,12 @@ struct cros_ec_readmem_v2 {
 	uint8_t buffer[EC_MEMMAP_SIZE];
 };
 
-#define CROS_EC_DEV_IOC_V2	0xEC
-#define CROS_EC_DEV_IOCXCMD_V2	_IOWR(CROS_EC_DEV_IOC_V2, 0, \
-				      struct cros_ec_command_v2)
-#define CROS_EC_DEV_IOCRDMEM_V2	_IOWR(CROS_EC_DEV_IOC_V2, 1, \
-				      struct cros_ec_readmem_v2)
-#define CROS_EC_DEV_IOCEVENTMASK_V2	_IO(CROS_EC_DEV_IOC_V2, 2)
+#define CROS_EC_DEV_IOC_V2 0xEC
+#define CROS_EC_DEV_IOCXCMD_V2 \
+	_IOWR(CROS_EC_DEV_IOC_V2, 0, struct cros_ec_command_v2)
+#define CROS_EC_DEV_IOCRDMEM_V2 \
+	_IOWR(CROS_EC_DEV_IOC_V2, 1, struct cros_ec_readmem_v2)
+#define CROS_EC_DEV_IOCEVENTMASK_V2 _IO(CROS_EC_DEV_IOC_V2, 2)
 
 #ifdef __cplusplus
 }
diff --git a/util/dedede-relevant-paths.txt b/util/dedede-relevant-paths.txt
new file mode 100644
index 0000000000..d7194c4e3b
--- /dev/null
+++ b/util/dedede-relevant-paths.txt
@@ -0,0 +1,24 @@
+# Here you can place files of interest to be included in the commit message for
+# merge commits to firmware-dedede-13606.B
+chip/it83xx
+common/charge_state.c
+common/fpsensor/build.mk
+common/mkbp_*
+common/ocpc.c
+common/usbc/usb_tc_drp_acc_trysrc_sm.c
+common/usbc/usb_sm.c
+common/usbc/*_pd_*
+common/usbc/dp_alt_mode.c
+common/usbc/usb_prl_sm.c
+common/usbc/usb_pe_drp_sm.c
+common/usb_charger.c
+common/usb_common.c
+common/usbc_ocp.c
+driver/charger/sm5803.*
+driver/charger/isl923x.*
+driver/tcpm/raa489000.*
+driver/tcpm/it83*
+include/power/icelake.h
+include/intel_x86.h
+power/icelake.c
+power/intel_x86.c
diff --git a/util/dt-gpionames/README.md b/util/dt-gpionames/README.md
new file mode 100644
index 0000000000..405b963220
--- /dev/null
+++ b/util/dt-gpionames/README.md
@@ -0,0 +1,124 @@
+# dt-gpionames
+
+## Overview
+
+This program reads a compiled device tree file (DTB), and creates
+a device tree source (DTS) fragment that initialises the `gpio-line-names`
+for each GPIO controller.
+
+The `named-gpios` compatible node is used as the source of the names. Each child node
+of the `named-gpios` node is named from a EC pin name, has a `gpios` property
+referencing the GPIO pin.
+
+The program matches the GPIO controller and pin for each of the
+`named-gpios` entries, and creates overlay DTS fragments for each of
+the GPIO controllers setting the `gpio-line-names`.
+
+The purpose of this program is to help upstream the EC GPIO support,
+specifically to enable a Zephyr based console command equivalent
+to `gpioget` and `gpioset`.
+
+Currently these commands rely on the existence of the
+`named-gpios` child nodes to specify the engineer-friendly name of
+the GPIO pins. However, core Zephyr does not use `named-gpios`,
+and any command upstreamed to Zephyr should only rely on
+the core Zephyr API and interfaces (and the `gpio-line-names`
+property is a standard attribute of the Zephyr GPIO definition).
+
+Using this program, a DTS fragment can be generated from an existing
+DTS with a `named-gpios` node that will allow an upstreamed
+`gpioget`/`gpioset` command to operate.
+
+## Building
+
+```
+cd platform/ec/util/dt-gpionames
+go build
+
+```
+
+This builds the `dt-gpionames` binary in this directory.
+
+## Executing
+
+The program input expects a compiled, flattened device tree binary (DTB)
+file.
+
+The source file for the compiler can be obtained from a device tree
+source file generated as part of a project build.
+
+So the complete process is (using the nivviks project target as an example):
+
+```
+[within the SDK]
+cd ../src/platform/ec/zephyr
+zmake configure -b nivviks
+cd ../util/dt-gpionames
+dtc --out /tmp/dt.dtb ../../build/zephyr/nivviks/build-ro/zephyr/zephyr.dts
+./dt-gpionames --output gpionames.dts --input /tmp/dt.dtb
+```
+
+This `gpionames.dts` can then be copied and added to the project's
+device tree source files.
+
+A shell script is available that runs these commands as a
+single step:
+
+
+```
+gpionames.sh <project>
+```
+
+Where `project` is the project target e.g `nivviks`, `lazor` etc.
+The script will place the output file in `/tmp/gpionames-`<project>`.dts`.
+
+## Examples
+
+If the `named-gpios` node contained:
+```
+	named-gpios {
+		compatible = "named-gpios";
+
+		gpio_slp_s4_l: slp_s4_l {
+			#gpio-cells = < 0x0 >;
+			gpios = < &gpio7 0x0 0x100 >;
+		};
+		gpio_ec_soc_pch_pwrok_od: ec_soc_pch_pwrok_od {
+			#gpio-cells = < 0x0 >;
+			gpios = < &gpio7 0x2 0xa06 >;
+		};
+		gpio_ec_gsc_packet_mode: ec_gsc_packet_mode {
+			#gpio-cells = < 0x0 >;
+			gpios = < &gpio7 0x5 0x100 >;
+			enum-name = "GPIO_PACKET_MODE_EN";
+		};
+		gpio_ec_soc_rtcrst: ec_soc_rtcrst {
+			#gpio-cells = < 0x0 >;
+			gpios = < &gpio7 0x6 0x200 >;
+		};
+...
+	};
+```
+
+The GPIO controllers DTS fragment would be:
+
+```
+/ {
+        soc {
+                gpio@4008f000 {
+                        gpio-line-names =
+                                "slp_s4_l",
+                                "",
+                                "ec_soc_pch_pwrok_od",
+                                "",
+                                "",
+                                "ec_gsc_packet_mode",
+                                "ec_soc_rtcrst";
+                };
+	};
+};
+```
+
+## Testing
+
+Since this is considered a one-off utility, there are no unit tests yet.
diff --git a/util/dt-gpionames/dt.go b/util/dt-gpionames/dt.go
new file mode 100644
index 0000000000..9e95aeb946
--- /dev/null
+++ b/util/dt-gpionames/dt.go
@@ -0,0 +1,203 @@
+// Copyright 2022 The ChromiumOS Authors
+// Use of this source code is governed by a BSD-style license that can be
+// found in the LICENSE file.
+
+// Utility to read a flattened device tree file (DTB) and create a
+// DTS fragment initialising the GPIO controller gpio-line-names
+// property.
+// The input DTB can be generated from device tree source (DTS) using
+// the standard device tree compiler (dtc) e.g
+//
+//   dtc --out zephyr.dtb zephyr.dts
+//   gt-gpionames --output gpio_names.dts --input zephyr.dtb
+//
+
+package main
+
+import (
+	"encoding/binary"
+	"flag"
+	"fmt"
+	"io"
+	"log"
+	"os"
+
+	"github.com/u-root/u-root/pkg/dt"
+)
+
+var input = flag.String("input", "", "Input DTB file")
+var output = flag.String("output", "", "Output file")
+
+type Gpio struct {
+	node *dt.Node // Device tree node
+	pins []string // Slice of pin names
+	max  int      // Last slice entry containing a name
+}
+
+func main() {
+	flag.Parse()
+	f, err := os.Open(*input)
+	if err != nil {
+		log.Fatal(err)
+	}
+	defer f.Close()
+	fdt, err := dt.ReadFDT(f)
+	if err != nil {
+		log.Fatal(err)
+	}
+
+	gm := findGpioControllers(fdt)
+	ng := findNamedGpios(fdt)
+	setLineNames(gm, ng)
+
+	of, err := os.Create(*output)
+	if err != nil {
+		log.Fatal(err)
+	}
+	defer of.Close()
+	writeLineNames(of, gm)
+}
+
+// writeLineNames generates DTS to set the gpio-line-names
+// string array property for each of the GPIO controllers
+// TODO: It may be cleaner to use a template rather than
+// generating each line separately.
+func writeLineNames(of io.Writer, gm map[dt.PHandle]*Gpio) {
+	fmt.Fprintf(of, "/ {\n")
+	fmt.Fprintf(of, "\tsoc {\n")
+	for _, g := range gm {
+		if g.max < 0 {
+			continue
+		}
+		first := true
+		fmt.Fprintf(of, "\t\t%s {\n", g.node.Name)
+		fmt.Fprintf(of, "\t\t\tgpio-line-names =")
+		for i := 0; i <= g.max; i++ {
+			if !first {
+				fmt.Fprintf(of, ",")
+			}
+			fmt.Fprintf(of, "\n\t\t\t\t\"%s\"", g.pins[i])
+			first = false
+		}
+		fmt.Fprintf(of, ";\n")
+		fmt.Fprintf(of, "\t\t};\n")
+	}
+	fmt.Fprintf(of, "\t};\n")
+	fmt.Fprintf(of, "};\n")
+}
+
+// findGpioControllers walks the nodes of the
+// flattened device tree, detecting the
+// GPIO controller nodes (which should have the 'gpio-controller'
+// property on them), and adds them to the map.
+func findGpioControllers(fdt *dt.FDT) map[dt.PHandle]*Gpio {
+	gm := make(map[dt.PHandle]*Gpio)
+	// Walk the tree and find all the GPIO controllers
+	gpios, err := fdt.Root().FindAll(func(n *dt.Node) bool {
+		_, ok := n.LookProperty("gpio-controller")
+		return ok
+	})
+	if err != nil {
+		log.Fatal(err)
+	}
+	// For each of the controllers, create a structure containing
+	// the slice of pin names, and add it to the map using
+	// the phandle as the key.
+	for _, n := range gpios {
+		// Default of 32 pins per controller.
+		var npins uint32 = 32
+		pinsProp, ok := n.LookProperty("ngpios")
+		if ok {
+			npins, err = pinsProp.AsU32()
+			if err != nil {
+				log.Printf("%s illegal number of pins (%v), ignored\n", n.Name, err)
+				continue
+			}
+		}
+		p, ok := n.LookProperty("phandle")
+		if !ok {
+			// No phandle, so not referenced.
+			log.Printf("%s not referenced, ignored\n", n.Name)
+			continue
+		}
+		ph, err := p.AsPHandle()
+		if err != nil {
+			log.Printf("%s illegal phandle (%v), ignored\n", n.Name, err)
+			continue
+		}
+		gpio := new(Gpio)
+		gpio.node = n
+		gpio.pins = make([]string, npins)
+		gpio.max = -1
+		gm[ph] = gpio
+	}
+	return gm
+}
+
+// findNamesGpios will walk the device tree and extract all the
+// child nodes of the nodes with compatible = "named-gpio",
+// and return the slice containing these nodes.
+func findNamedGpios(fdt *dt.FDT) []*dt.Node {
+	ng := make([]*dt.Node, 0)
+	err := fdt.RootNode.Walk(func(n *dt.Node) error {
+		p, ok := n.LookProperty("compatible")
+		if ok {
+			s, err := p.AsType(dt.StringType)
+			if err == nil && s == "named-gpios" {
+				ng = append(ng, n.Children...)
+			}
+		}
+		return nil
+	})
+	if err != nil {
+		log.Fatal(err)
+	}
+	return ng
+}
+
+// setLineNames will add the named-gpio node names to the GPIO controller
+// line names for the associated pin.
+func setLineNames(gm map[dt.PHandle]*Gpio, ngList []*dt.Node) {
+	for _, ng := range ngList {
+		gp, ok := ng.LookProperty("gpios")
+		if !ok {
+			log.Printf("No valid gpios on %s\n", ng.Name)
+			continue
+		}
+		// Get the flattened byte string representing
+		// the GPIO. The array contains:
+		//   32 bit PHandle referencing the GPIO controller
+		//   32 bit pin number
+		//   32 bit flags
+		blk, err := gp.AsPropEncodedArray()
+		if err != nil {
+			log.Printf("%s: %v\n", ng.Name, err)
+			continue
+		}
+		if len(blk) != 12 {
+			log.Printf("%s: Wrong size on gpios PHA(%d)\n", ng.Name, len(blk))
+			continue
+		}
+		ph := binary.BigEndian.Uint32(blk[0:])
+		pin := binary.BigEndian.Uint32(blk[4:])
+		gpio, ok := gm[dt.PHandle(ph)]
+		if !ok {
+			log.Printf("No GPIO controller for %s (PH %d)\n", ng.Name, ph)
+			continue
+		}
+		if int(pin) >= len(gpio.pins) {
+			log.Printf("GPIO %s pin %d out of range for %s (max %d)\n",
+				ng.Name, pin, gpio.node.Name, len(gpio.pins))
+			continue
+		}
+		if gpio.pins[pin] != "" {
+			log.Printf("GPIO %s pin %d already has name (%s)\n",
+				ng.Name, pin, gpio.pins[pin])
+			continue
+		}
+		gpio.pins[pin] = ng.Name
+		if int(pin) > gpio.max {
+			gpio.max = int(pin)
+		}
+	}
+}
diff --git a/util/dt-gpionames/go.mod b/util/dt-gpionames/go.mod
new file mode 100644
index 0000000000..2a83ecdd03
--- /dev/null
+++ b/util/dt-gpionames/go.mod
@@ -0,0 +1,5 @@
+module dt-gpionames
+
+go 1.15
+
+require github.com/u-root/u-root v1.0.1
diff --git a/util/dt-gpionames/go.sum b/util/dt-gpionames/go.sum
new file mode 100644
index 0000000000..e982990133
--- /dev/null
+++ b/util/dt-gpionames/go.sum
@@ -0,0 +1,238 @@
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+gopkg.in/yaml.v2 v2.2.2/go.mod h1:hI93XBmqTisBFMUTm0b8Fm+jr3Dg1NNxqwp+5A1VGuI=
+gopkg.in/yaml.v3 v3.0.0-20200313102051-9f266ea9e77c/go.mod h1:K4uyk7z7BCEPqu6E+C64Yfv1cQ7kz7rIZviUmN+EgEM=
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diff --git a/util/dt-gpionames/gpionames.sh b/util/dt-gpionames/gpionames.sh
new file mode 100755
index 0000000000..972dbbacd9
--- /dev/null
+++ b/util/dt-gpionames/gpionames.sh
@@ -0,0 +1,34 @@
+#!/bin/bash
+#
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+set -e
+
+if [ $# != 1 ]; then
+	echo "Usage $0 <project>"
+	exit
+fi
+
+basedir=$(pwd)
+dtprog="${basedir}/dt-gpionames"
+proj=$1
+dtb="/tmp/dt-${proj}.dtb"
+names="/tmp/gpionames-${proj}.dts"
+dts="../../build/zephyr/${proj}/build-ro/zephyr/zephyr.dts"
+
+# Remove dt-gpionames binary
+trap 'rm -f ${dtprog}' EXIT
+
+proj=$1
+echo "Using ${proj} project"
+echo "Building ${dtprog}"
+go build
+echo "Building project ${proj}"
+(cd ../../zephyr; zmake configure -b "${proj}")
+echo "Compiling device tree ${dts} to ${dtb}"
+dtc --out "${dtb}" "${dts}"
+echo "Generating ${names} from ${dtb}"
+${dtprog} --output "${names}" --input "${dtb}"
+echo "Successfully generated ${names}"
diff --git a/util/ec3po/__init__.py b/util/ec3po/__init__.py
index 9bebfa5842..b3534114ac 100644
--- a/util/ec3po/__init__.py
+++ b/util/ec3po/__init__.py
@@ -1,4 +1,4 @@
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -19,7 +19,3 @@
 automatic command retrying if the EC drops a character in a command.  This is a
 stopgap until all commands are communicated via host commands.
 """
-
-import console
-import interpreter
-import threadproc_shim
diff --git a/util/ec3po/console.py b/util/ec3po/console.py
index aec237ac16..cc822a7073 100755
--- a/util/ec3po/console.py
+++ b/util/ec3po/console.py
@@ -1,5 +1,5 @@
 #!/usr/bin/env python
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -18,7 +18,6 @@
 import binascii
 import ctypes
 from datetime import datetime
-# pylint: disable=cros-logging-import
 import logging
 import os
 import pty
@@ -28,25 +27,25 @@
 import sys
 import traceback
 
+from ec3po import interpreter
+from ec3po import threadproc_shim
 import six
 
-import interpreter
-import threadproc_shim
 
-
-PROMPT = b'> '
+PROMPT = b"> "
 CONSOLE_INPUT_LINE_SIZE = 80  # Taken from the CONFIG_* with the same name.
 CONSOLE_MAX_READ = 100  # Max bytes to read at a time from the user.
 LOOK_BUFFER_SIZE = 256  # Size of search window when looking for the enhanced EC
-                        # image string.
+# image string.
 
 # In console_init(), the EC will print a string saying that the EC console is
 # enabled.  Enhanced images will print a slightly different string.  These
 # regular expressions are used to determine at reboot whether the EC image is
 # enhanced or not.
-ENHANCED_IMAGE_RE = re.compile(br'Enhanced Console is enabled '
-                               br'\(v([0-9]+\.[0-9]+\.[0-9]+)\)')
-NON_ENHANCED_IMAGE_RE = re.compile(br'Console is enabled; ')
+ENHANCED_IMAGE_RE = re.compile(
+    rb"Enhanced Console is enabled " rb"\(v([0-9]+\.[0-9]+\.[0-9]+)\)"
+)
+NON_ENHANCED_IMAGE_RE = re.compile(rb"Console is enabled; ")
 
 # The timeouts are really only useful for enhanced EC images, but otherwise just
 # serve as a delay for non-enhanced EC images.  Therefore, we can keep this
@@ -55,1108 +54,1225 @@
 # EC image, we can increase the timeout for stability just in case it takes a
 # bit longer to receive an ACK for some reason.
 NON_ENHANCED_EC_INTERROGATION_TIMEOUT = 0.3  # Maximum number of seconds to wait
-                                             # for a response to an
-                                             # interrogation of a non-enhanced
-                                             # EC image.
+# for a response to an
+# interrogation of a non-enhanced
+# EC image.
 ENHANCED_EC_INTERROGATION_TIMEOUT = 1.0  # Maximum number of seconds to wait for
-                                         # a response to an interrogation of an
-                                         # enhanced EC image.
+# a response to an interrogation of an
+# enhanced EC image.
 # List of modes which control when interrogations are performed with the EC.
-INTERROGATION_MODES = [b'never', b'always', b'auto']
+INTERROGATION_MODES = [b"never", b"always", b"auto"]
 # Format for printing host timestamp
-HOST_STRFTIME="%y-%m-%d %H:%M:%S.%f"
+HOST_STRFTIME = "%y-%m-%d %H:%M:%S.%f"
 
 
 class EscState(object):
-  """Class which contains an enumeration for states of ESC sequences."""
-  ESC_START = 1
-  ESC_BRACKET = 2
-  ESC_BRACKET_1 = 3
-  ESC_BRACKET_3 = 4
-  ESC_BRACKET_8 = 5
+    """Class which contains an enumeration for states of ESC sequences."""
+
+    ESC_START = 1
+    ESC_BRACKET = 2
+    ESC_BRACKET_1 = 3
+    ESC_BRACKET_3 = 4
+    ESC_BRACKET_8 = 5
 
 
 class ControlKey(object):
-  """Class which contains codes for various control keys."""
-  BACKSPACE = 0x08
-  CTRL_A = 0x01
-  CTRL_B = 0x02
-  CTRL_D = 0x04
-  CTRL_E = 0x05
-  CTRL_F = 0x06
-  CTRL_K = 0x0b
-  CTRL_N = 0xe
-  CTRL_P = 0x10
-  CARRIAGE_RETURN = 0x0d
-  ESC = 0x1b
+    """Class which contains codes for various control keys."""
 
+    BACKSPACE = 0x08
+    CTRL_A = 0x01
+    CTRL_B = 0x02
+    CTRL_D = 0x04
+    CTRL_E = 0x05
+    CTRL_F = 0x06
+    CTRL_K = 0x0B
+    CTRL_N = 0xE
+    CTRL_P = 0x10
+    CARRIAGE_RETURN = 0x0D
+    ESC = 0x1B
 
-class Console(object):
-  """Class which provides the console interface between the EC and the user.
-
-  This class essentially represents the console interface between the user and
-  the EC.  It handles all of the console editing behaviour
-
-  Attributes:
-    logger: A logger for this module.
-    master_pty: File descriptor to the master side of the PTY.  Used for driving
-      output to the user and receiving user input.
-    user_pty: A string representing the PTY name of the served console.
-    cmd_pipe: A socket.socket or multiprocessing.Connection object which
-      represents the console side of the command pipe.  This must be a
-      bidirectional pipe.  Console commands and responses utilize this pipe.
-    dbg_pipe: A socket.socket or multiprocessing.Connection object which
-      represents the console's read-only side of the debug pipe.  This must be a
-      unidirectional pipe attached to the intepreter.  EC debug messages use
-      this pipe.
-    oobm_queue: A queue.Queue or multiprocessing.Queue which is used for out of
-      band management for the interactive console.
-    input_buffer: A string representing the current input command.
-    input_buffer_pos: An integer representing the current position in the buffer
-      to insert a char.
-    partial_cmd: A string representing the command entered on a line before
-      pressing the up arrow keys.
-    esc_state: An integer represeting the current state within an escape
-      sequence.
-    line_limit: An integer representing the maximum number of characters on a
-      line.
-    history: A list of strings containing the past entered console commands.
-    history_pos: An integer representing the current history buffer position.
-      This index is used to show previous commands.
-    prompt: A string representing the console prompt displayed to the user.
-    enhanced_ec: A boolean indicating if the EC image that we are currently
-      communicating with is enhanced or not.  Enhanced EC images will support
-      packed commands and host commands over the UART.  This defaults to False
-      until we perform some handshaking.
-    interrogation_timeout: A float representing the current maximum seconds to
-      wait for a response to an interrogation.
-    receiving_oobm_cmd: A boolean indicating whether or not the console is in
-      the middle of receiving an out of band command.
-    pending_oobm_cmd: A string containing the pending OOBM command.
-    interrogation_mode: A string containing the current mode of whether
-      interrogations are performed with the EC or not and how often.
-    raw_debug: Flag to indicate whether per interrupt data should be logged to
-      debug
-    output_line_log_buffer: buffer for lines coming from the EC to log to debug
-  """
-
-  def __init__(self, master_pty, user_pty, interface_pty, cmd_pipe, dbg_pipe,
-               name=None):
-    """Initalises a Console object with the provided arguments.
-
-    Args:
-    master_pty: File descriptor to the master side of the PTY.  Used for driving
-      output to the user and receiving user input.
-    user_pty: A string representing the PTY name of the served console.
-    interface_pty: A string representing the PTY name of the served command
-      interface.
-    cmd_pipe: A socket.socket or multiprocessing.Connection object which
-      represents the console side of the command pipe.  This must be a
-      bidirectional pipe.  Console commands and responses utilize this pipe.
-    dbg_pipe: A socket.socket or multiprocessing.Connection object which
-      represents the console's read-only side of the debug pipe.  This must be a
-      unidirectional pipe attached to the intepreter.  EC debug messages use
-      this pipe.
-    name: the console source name
-    """
-    # Create a unique logger based on the console name
-    console_prefix = ('%s - ' % name) if name else ''
-    logger = logging.getLogger('%sEC3PO.Console' % console_prefix)
-    self.logger = interpreter.LoggerAdapter(logger, {'pty': user_pty})
-    self.master_pty = master_pty
-    self.user_pty = user_pty
-    self.interface_pty = interface_pty
-    self.cmd_pipe = cmd_pipe
-    self.dbg_pipe = dbg_pipe
-    self.oobm_queue = threadproc_shim.Queue()
-    self.input_buffer = b''
-    self.input_buffer_pos = 0
-    self.partial_cmd = b''
-    self.esc_state = 0
-    self.line_limit = CONSOLE_INPUT_LINE_SIZE
-    self.history = []
-    self.history_pos = 0
-    self.prompt = PROMPT
-    self.enhanced_ec = False
-    self.interrogation_timeout = NON_ENHANCED_EC_INTERROGATION_TIMEOUT
-    self.receiving_oobm_cmd = False
-    self.pending_oobm_cmd = b''
-    self.interrogation_mode = b'auto'
-    self.timestamp_enabled = True
-    self.look_buffer = b''
-    self.raw_debug = False
-    self.output_line_log_buffer = []
-
-  def __str__(self):
-    """Show internal state of Console object as a string."""
-    string = []
-    string.append('master_pty: %s' % self.master_pty)
-    string.append('user_pty: %s' % self.user_pty)
-    string.append('interface_pty: %s' % self.interface_pty)
-    string.append('cmd_pipe: %s' % self.cmd_pipe)
-    string.append('dbg_pipe: %s' % self.dbg_pipe)
-    string.append('oobm_queue: %s' % self.oobm_queue)
-    string.append('input_buffer: %s' % self.input_buffer)
-    string.append('input_buffer_pos: %d' % self.input_buffer_pos)
-    string.append('esc_state: %d' % self.esc_state)
-    string.append('line_limit: %d' % self.line_limit)
-    string.append('history: [\'' + '%s' % repr(self.history) + '\']')
-    string.append('history_pos: %d' % self.history_pos)
-    string.append('prompt: \'%s\'' % self.prompt)
-    string.append('partial_cmd: \'%s\''% self.partial_cmd)
-    string.append('interrogation_mode: \'%s\'' % self.interrogation_mode)
-    string.append('look_buffer: \'%s\'' % self.look_buffer)
-    return '\n'.join(string)
-
-  def LogConsoleOutput(self, data):
-    """Log to debug user MCU output to master_pty when line is filled.
-
-    The logging also suppresses the Cr50 spinner lines by removing characters
-    when it sees backspaces.
-
-    Args:
-      data: binary string received from MCU
-    """
-    data = list(data)
-
-    # This is a list of already filtered characters (or placeholders).
-    line = self.output_line_log_buffer
-
-    symbols = {
-            b'\n': u'\\n',
-            b'\r': u'\\r',
-            b'\t': u'\\t'
-    }
-    # self.logger.debug(u'%s + %r', u''.join(line), ''.join(data))
-    while data:
-      byte = data.pop(0)
-      if byte == '\n':
-        line.append(symbols[byte])
-        if line:
-          self.logger.debug(u'%s', ''.join(line))
-        line = []
-      elif byte == b'\b':
-        # Backspace: trim the last character off the buffer
-        if line:
-          line.pop(-1)
-      elif byte in symbols:
-        line.append(symbols[byte])
-      elif byte < b' ' or byte > b'~':
-        # Turn any character that isn't printable ASCII into escaped hex.
-        # ' ' is chr(20), and 0-19 are unprintable control characters.
-        # '~' is chr(126), and 127 is DELETE.  128-255 are control and Latin-1.
-        line.append(u'\\x%02x' % ord(byte))
-      else:
-        line.append(u'%s' % byte)
-    self.output_line_log_buffer = line
-
-  def PrintHistory(self):
-    """Print the history of entered commands."""
-    fd = self.master_pty
-    # Make it pretty by figuring out how wide to pad the numbers.
-    wide = (len(self.history) // 10) + 1
-    for i in range(len(self.history)):
-      line = b' %*d %s\r\n' % (wide, i, self.history[i])
-      os.write(fd, line)
-
-  def ShowPreviousCommand(self):
-    """Shows the previous command from the history list."""
-    # There's nothing to do if there's no history at all.
-    if not self.history:
-      self.logger.debug('No history to print.')
-      return
-
-    # Don't do anything if there's no more history to show.
-    if self.history_pos == 0:
-      self.logger.debug('No more history to show.')
-      return
-
-    self.logger.debug('current history position: %d.', self.history_pos)
-
-    # Decrement the history buffer position.
-    self.history_pos -= 1
-    self.logger.debug('new history position.: %d', self.history_pos)
-
-    # Save the text entered on the console if any.
-    if self.history_pos == len(self.history)-1:
-      self.logger.debug('saving partial_cmd: \'%s\'', self.input_buffer)
-      self.partial_cmd = self.input_buffer
-
-    # Backspace the line.
-    for _ in range(self.input_buffer_pos):
-      self.SendBackspace()
-
-    # Print the last entry in the history buffer.
-    self.logger.debug('printing previous entry %d - %s', self.history_pos,
-                      self.history[self.history_pos])
-    fd = self.master_pty
-    prev_cmd = self.history[self.history_pos]
-    os.write(fd, prev_cmd)
-    # Update the input buffer.
-    self.input_buffer = prev_cmd
-    self.input_buffer_pos = len(prev_cmd)
-
-  def ShowNextCommand(self):
-    """Shows the next command from the history list."""
-    # Don't do anything if there's no history at all.
-    if not self.history:
-      self.logger.debug('History buffer is empty.')
-      return
-
-    fd = self.master_pty
-
-    self.logger.debug('current history position: %d', self.history_pos)
-    # Increment the history position.
-    self.history_pos += 1
-
-    # Restore the partial cmd.
-    if self.history_pos == len(self.history):
-      self.logger.debug('Restoring partial command of \'%s\'', self.partial_cmd)
-      # Backspace the line.
-      for _ in range(self.input_buffer_pos):
-        self.SendBackspace()
-      # Print the partially entered command if any.
-      os.write(fd, self.partial_cmd)
-      self.input_buffer = self.partial_cmd
-      self.input_buffer_pos = len(self.input_buffer)
-      # Now that we've printed it, clear the partial cmd storage.
-      self.partial_cmd = b''
-      # Reset history position.
-      self.history_pos = len(self.history)
-      return
-
-    self.logger.debug('new history position: %d', self.history_pos)
-    if self.history_pos > len(self.history)-1:
-      self.logger.debug('No more history to show.')
-      self.history_pos -= 1
-      self.logger.debug('Reset history position to %d', self.history_pos)
-      return
-
-    # Backspace the line.
-    for _ in range(self.input_buffer_pos):
-      self.SendBackspace()
-
-    # Print the newer entry from the history buffer.
-    self.logger.debug('printing next entry %d - %s', self.history_pos,
-                      self.history[self.history_pos])
-    next_cmd = self.history[self.history_pos]
-    os.write(fd, next_cmd)
-    # Update the input buffer.
-    self.input_buffer = next_cmd
-    self.input_buffer_pos = len(next_cmd)
-    self.logger.debug('new history position: %d.', self.history_pos)
-
-  def SliceOutChar(self):
-    """Remove a char from the line and shift everything over 1 column."""
-    fd = self.master_pty
-    # Remove the character at the input_buffer_pos by slicing it out.
-    self.input_buffer = self.input_buffer[0:self.input_buffer_pos] + \
-                        self.input_buffer[self.input_buffer_pos+1:]
-    # Write the rest of the line
-    moved_col = os.write(fd, self.input_buffer[self.input_buffer_pos:])
-    # Write a space to clear out the last char
-    moved_col += os.write(fd, b' ')
-    # Update the input buffer position.
-    self.input_buffer_pos += moved_col
-    # Reset the cursor
-    self.MoveCursor('left', moved_col)
-
-  def HandleEsc(self, byte):
-    """HandleEsc processes escape sequences.
 
-    Args:
-      byte: An integer representing the current byte in the sequence.
+class Console(object):
+    """Class which provides the console interface between the EC and the user.
+
+    This class essentially represents the console interface between the user and
+    the EC.  It handles all of the console editing behaviour
+
+    Attributes:
+      logger: A logger for this module.
+      controller_pty: File descriptor to the controller side of the PTY. Used for
+        driving output to the user and receiving user input.
+      user_pty: A string representing the PTY name of the served console.
+      cmd_pipe: A socket.socket or multiprocessing.Connection object which
+        represents the console side of the command pipe.  This must be a
+        bidirectional pipe.  Console commands and responses utilize this pipe.
+      dbg_pipe: A socket.socket or multiprocessing.Connection object which
+        represents the console's read-only side of the debug pipe.  This must be a
+        unidirectional pipe attached to the intepreter.  EC debug messages use
+        this pipe.
+      oobm_queue: A queue.Queue or multiprocessing.Queue which is used for out of
+        band management for the interactive console.
+      input_buffer: A string representing the current input command.
+      input_buffer_pos: An integer representing the current position in the buffer
+        to insert a char.
+      partial_cmd: A string representing the command entered on a line before
+        pressing the up arrow keys.
+      esc_state: An integer represeting the current state within an escape
+        sequence.
+      line_limit: An integer representing the maximum number of characters on a
+        line.
+      history: A list of strings containing the past entered console commands.
+      history_pos: An integer representing the current history buffer position.
+        This index is used to show previous commands.
+      prompt: A string representing the console prompt displayed to the user.
+      enhanced_ec: A boolean indicating if the EC image that we are currently
+        communicating with is enhanced or not.  Enhanced EC images will support
+        packed commands and host commands over the UART.  This defaults to False
+        until we perform some handshaking.
+      interrogation_timeout: A float representing the current maximum seconds to
+        wait for a response to an interrogation.
+      receiving_oobm_cmd: A boolean indicating whether or not the console is in
+        the middle of receiving an out of band command.
+      pending_oobm_cmd: A string containing the pending OOBM command.
+      interrogation_mode: A string containing the current mode of whether
+        interrogations are performed with the EC or not and how often.
+      raw_debug: Flag to indicate whether per interrupt data should be logged to
+        debug
+      output_line_log_buffer: buffer for lines coming from the EC to log to debug
     """
-    # We shouldn't be handling an escape sequence if we haven't seen one.
-    assert self.esc_state != 0
-
-    if self.esc_state is EscState.ESC_START:
-      self.logger.debug('ESC_START')
-      if byte == ord('['):
-        self.esc_state = EscState.ESC_BRACKET
-        return
-
-      else:
-        self.logger.error('Unexpected sequence. %c', byte)
-        self.esc_state = 0
 
-    elif self.esc_state is EscState.ESC_BRACKET:
-      self.logger.debug('ESC_BRACKET')
-      # Left Arrow key was pressed.
-      if byte == ord('D'):
-        self.logger.debug('Left arrow key pressed.')
-        self.MoveCursor('left', 1)
-        self.esc_state = 0 # Reset the state.
-        return
-
-      # Right Arrow key.
-      elif byte == ord('C'):
-        self.logger.debug('Right arrow key pressed.')
-        self.MoveCursor('right', 1)
-        self.esc_state = 0 # Reset the state.
-        return
-
-      # Up Arrow key.
-      elif byte == ord('A'):
-        self.logger.debug('Up arrow key pressed.')
-        self.ShowPreviousCommand()
-        # Reset the state.
-        self.esc_state = 0 # Reset the state.
-        return
-
-      # Down Arrow key.
-      elif byte == ord('B'):
-        self.logger.debug('Down arrow key pressed.')
-        self.ShowNextCommand()
-        # Reset the state.
-        self.esc_state = 0 # Reset the state.
-        return
-
-      # For some reason, minicom sends a 1 instead of 7. /shrug
-      # TODO(aaboagye): Figure out why this happens.
-      elif byte == ord('1') or byte == ord('7'):
-        self.esc_state = EscState.ESC_BRACKET_1
-
-      elif byte == ord('3'):
-        self.esc_state = EscState.ESC_BRACKET_3
-
-      elif byte == ord('8'):
-        self.esc_state = EscState.ESC_BRACKET_8
-
-      else:
-        self.logger.error(r'Bad or unhandled escape sequence. got ^[%c\(%d)',
-                          chr(byte), byte)
-        self.esc_state = 0
-        return
-
-    elif self.esc_state is EscState.ESC_BRACKET_1:
-      self.logger.debug('ESC_BRACKET_1')
-      # HOME key.
-      if byte == ord('~'):
-        self.logger.debug('Home key pressed.')
-        self.MoveCursor('left', self.input_buffer_pos)
-        self.esc_state = 0 # Reset the state.
-        self.logger.debug('ESC sequence complete.')
-        return
-
-    elif self.esc_state is EscState.ESC_BRACKET_3:
-      self.logger.debug('ESC_BRACKET_3')
-      # DEL key.
-      if byte == ord('~'):
-        self.logger.debug('Delete key pressed.')
-        if self.input_buffer_pos != len(self.input_buffer):
-          self.SliceOutChar()
-        self.esc_state = 0 # Reset the state.
-
-    elif self.esc_state is EscState.ESC_BRACKET_8:
-      self.logger.debug('ESC_BRACKET_8')
-      # END key.
-      if byte == ord('~'):
-        self.logger.debug('End key pressed.')
-        self.MoveCursor('right',
-                        len(self.input_buffer) - self.input_buffer_pos)
-        self.esc_state = 0 # Reset the state.
-        self.logger.debug('ESC sequence complete.')
-        return
-
-      else:
-        self.logger.error('Unexpected sequence. %c', byte)
+    def __init__(
+        self,
+        controller_pty,
+        user_pty,
+        interface_pty,
+        cmd_pipe,
+        dbg_pipe,
+        name=None,
+    ):
+        """Initalises a Console object with the provided arguments.
+
+        Args:
+        controller_pty: File descriptor to the controller side of the PTY. Used for
+          driving output to the user and receiving user input.
+        user_pty: A string representing the PTY name of the served console.
+        interface_pty: A string representing the PTY name of the served command
+          interface.
+        cmd_pipe: A socket.socket or multiprocessing.Connection object which
+          represents the console side of the command pipe.  This must be a
+          bidirectional pipe.  Console commands and responses utilize this pipe.
+        dbg_pipe: A socket.socket or multiprocessing.Connection object which
+          represents the console's read-only side of the debug pipe.  This must be a
+          unidirectional pipe attached to the intepreter.  EC debug messages use
+          this pipe.
+        name: the console source name
+        """
+        # Create a unique logger based on the console name
+        console_prefix = ("%s - " % name) if name else ""
+        logger = logging.getLogger("%sEC3PO.Console" % console_prefix)
+        self.logger = interpreter.LoggerAdapter(logger, {"pty": user_pty})
+        self.controller_pty = controller_pty
+        self.user_pty = user_pty
+        self.interface_pty = interface_pty
+        self.cmd_pipe = cmd_pipe
+        self.dbg_pipe = dbg_pipe
+        self.oobm_queue = threadproc_shim.Queue()
+        self.input_buffer = b""
+        self.input_buffer_pos = 0
+        self.partial_cmd = b""
         self.esc_state = 0
+        self.line_limit = CONSOLE_INPUT_LINE_SIZE
+        self.history = []
+        self.history_pos = 0
+        self.prompt = PROMPT
+        self.enhanced_ec = False
+        self.interrogation_timeout = NON_ENHANCED_EC_INTERROGATION_TIMEOUT
+        self.receiving_oobm_cmd = False
+        self.pending_oobm_cmd = b""
+        self.interrogation_mode = b"auto"
+        self.timestamp_enabled = True
+        self.look_buffer = b""
+        self.raw_debug = False
+        self.output_line_log_buffer = []
+
+    def __str__(self):
+        """Show internal state of Console object as a string."""
+        string = []
+        string.append("controller_pty: %s" % self.controller_pty)
+        string.append("user_pty: %s" % self.user_pty)
+        string.append("interface_pty: %s" % self.interface_pty)
+        string.append("cmd_pipe: %s" % self.cmd_pipe)
+        string.append("dbg_pipe: %s" % self.dbg_pipe)
+        string.append("oobm_queue: %s" % self.oobm_queue)
+        string.append("input_buffer: %s" % self.input_buffer)
+        string.append("input_buffer_pos: %d" % self.input_buffer_pos)
+        string.append("esc_state: %d" % self.esc_state)
+        string.append("line_limit: %d" % self.line_limit)
+        string.append("history: %r" % self.history)
+        string.append("history_pos: %d" % self.history_pos)
+        string.append("prompt: %r" % self.prompt)
+        string.append("partial_cmd: %r" % self.partial_cmd)
+        string.append("interrogation_mode: %r" % self.interrogation_mode)
+        string.append("look_buffer: %r" % self.look_buffer)
+        return "\n".join(string)
+
+    def LogConsoleOutput(self, data):
+        """Log to debug user MCU output to controller_pty when line is filled.
+
+        The logging also suppresses the Cr50 spinner lines by removing characters
+        when it sees backspaces.
+
+        Args:
+          data: bytes - string received from MCU
+        """
+        data = list(data)
+        # For compatibility with python2 and python3, standardize on the data
+        # being a list of integers. This requires one more transformation in py2
+        if not isinstance(data[0], int):
+            data = [ord(c) for c in data]
+
+        # This is a list of already filtered characters (or placeholders).
+        line = self.output_line_log_buffer
+
+        # TODO(b/177480273): use raw strings here
+        symbols = {ord(b"\n"): "\\n", ord(b"\r"): "\\r", ord(b"\t"): "\\t"}
+        # self.logger.debug(u'%s + %r', u''.join(line), ''.join(data))
+        while data:
+            # Recall, data is a list of integers, namely the byte values sent by
+            # the MCU.
+            byte = data.pop(0)
+            # This means that |byte| is an int.
+            if byte == ord("\n"):
+                line.append(symbols[byte])
+                if line:
+                    self.logger.debug("%s", "".join(line))
+                line = []
+            elif byte == ord("\b"):
+                # Backspace: trim the last character off the buffer
+                if line:
+                    line.pop(-1)
+            elif byte in symbols:
+                line.append(symbols[byte])
+            elif byte < ord(" ") or byte > ord("~"):
+                # Turn any character that isn't printable ASCII into escaped hex.
+                # ' ' is chr(20), and 0-19 are unprintable control characters.
+                # '~' is chr(126), and 127 is DELETE.  128-255 are control and Latin-1.
+                line.append("\\x%02x" % byte)
+            else:
+                # byte is printable. Thus it is safe to use chr() to get the printable
+                # character out of it again.
+                line.append("%s" % chr(byte))
+        self.output_line_log_buffer = line
+
+    def PrintHistory(self):
+        """Print the history of entered commands."""
+        fd = self.controller_pty
+        # Make it pretty by figuring out how wide to pad the numbers.
+        wide = (len(self.history) // 10) + 1
+        for i in range(len(self.history)):
+            line = b" %*d %s\r\n" % (wide, i, self.history[i])
+            os.write(fd, line)
+
+    def ShowPreviousCommand(self):
+        """Shows the previous command from the history list."""
+        # There's nothing to do if there's no history at all.
+        if not self.history:
+            self.logger.debug("No history to print.")
+            return
+
+        # Don't do anything if there's no more history to show.
+        if self.history_pos == 0:
+            self.logger.debug("No more history to show.")
+            return
+
+        self.logger.debug("current history position: %d.", self.history_pos)
+
+        # Decrement the history buffer position.
+        self.history_pos -= 1
+        self.logger.debug("new history position.: %d", self.history_pos)
+
+        # Save the text entered on the console if any.
+        if self.history_pos == len(self.history) - 1:
+            self.logger.debug("saving partial_cmd: %r", self.input_buffer)
+            self.partial_cmd = self.input_buffer
+
+        # Backspace the line.
+        for _ in range(self.input_buffer_pos):
+            self.SendBackspace()
+
+        # Print the last entry in the history buffer.
+        self.logger.debug(
+            "printing previous entry %d - %s",
+            self.history_pos,
+            self.history[self.history_pos],
+        )
+        fd = self.controller_pty
+        prev_cmd = self.history[self.history_pos]
+        os.write(fd, prev_cmd)
+        # Update the input buffer.
+        self.input_buffer = prev_cmd
+        self.input_buffer_pos = len(prev_cmd)
+
+    def ShowNextCommand(self):
+        """Shows the next command from the history list."""
+        # Don't do anything if there's no history at all.
+        if not self.history:
+            self.logger.debug("History buffer is empty.")
+            return
+
+        fd = self.controller_pty
+
+        self.logger.debug("current history position: %d", self.history_pos)
+        # Increment the history position.
+        self.history_pos += 1
+
+        # Restore the partial cmd.
+        if self.history_pos == len(self.history):
+            self.logger.debug(
+                "Restoring partial command of %r", self.partial_cmd
+            )
+            # Backspace the line.
+            for _ in range(self.input_buffer_pos):
+                self.SendBackspace()
+            # Print the partially entered command if any.
+            os.write(fd, self.partial_cmd)
+            self.input_buffer = self.partial_cmd
+            self.input_buffer_pos = len(self.input_buffer)
+            # Now that we've printed it, clear the partial cmd storage.
+            self.partial_cmd = b""
+            # Reset history position.
+            self.history_pos = len(self.history)
+            return
+
+        self.logger.debug("new history position: %d", self.history_pos)
+        if self.history_pos > len(self.history) - 1:
+            self.logger.debug("No more history to show.")
+            self.history_pos -= 1
+            self.logger.debug("Reset history position to %d", self.history_pos)
+            return
+
+        # Backspace the line.
+        for _ in range(self.input_buffer_pos):
+            self.SendBackspace()
+
+        # Print the newer entry from the history buffer.
+        self.logger.debug(
+            "printing next entry %d - %s",
+            self.history_pos,
+            self.history[self.history_pos],
+        )
+        next_cmd = self.history[self.history_pos]
+        os.write(fd, next_cmd)
+        # Update the input buffer.
+        self.input_buffer = next_cmd
+        self.input_buffer_pos = len(next_cmd)
+        self.logger.debug("new history position: %d.", self.history_pos)
+
+    def SliceOutChar(self):
+        """Remove a char from the line and shift everything over 1 column."""
+        fd = self.controller_pty
+        # Remove the character at the input_buffer_pos by slicing it out.
+        self.input_buffer = (
+            self.input_buffer[0 : self.input_buffer_pos]
+            + self.input_buffer[self.input_buffer_pos + 1 :]
+        )
+        # Write the rest of the line
+        moved_col = os.write(fd, self.input_buffer[self.input_buffer_pos :])
+        # Write a space to clear out the last char
+        moved_col += os.write(fd, b" ")
+        # Update the input buffer position.
+        self.input_buffer_pos += moved_col
+        # Reset the cursor
+        self.MoveCursor("left", moved_col)
+
+    def HandleEsc(self, byte):
+        """HandleEsc processes escape sequences.
+
+        Args:
+          byte: An integer representing the current byte in the sequence.
+        """
+        # We shouldn't be handling an escape sequence if we haven't seen one.
+        assert self.esc_state != 0
+
+        if self.esc_state is EscState.ESC_START:
+            self.logger.debug("ESC_START")
+            if byte == ord("["):
+                self.esc_state = EscState.ESC_BRACKET
+                return
+
+            else:
+                self.logger.error("Unexpected sequence. %c", byte)
+                self.esc_state = 0
+
+        elif self.esc_state is EscState.ESC_BRACKET:
+            self.logger.debug("ESC_BRACKET")
+            # Left Arrow key was pressed.
+            if byte == ord("D"):
+                self.logger.debug("Left arrow key pressed.")
+                self.MoveCursor("left", 1)
+                self.esc_state = 0  # Reset the state.
+                return
+
+            # Right Arrow key.
+            elif byte == ord("C"):
+                self.logger.debug("Right arrow key pressed.")
+                self.MoveCursor("right", 1)
+                self.esc_state = 0  # Reset the state.
+                return
+
+            # Up Arrow key.
+            elif byte == ord("A"):
+                self.logger.debug("Up arrow key pressed.")
+                self.ShowPreviousCommand()
+                # Reset the state.
+                self.esc_state = 0  # Reset the state.
+                return
+
+            # Down Arrow key.
+            elif byte == ord("B"):
+                self.logger.debug("Down arrow key pressed.")
+                self.ShowNextCommand()
+                # Reset the state.
+                self.esc_state = 0  # Reset the state.
+                return
+
+            # For some reason, minicom sends a 1 instead of 7. /shrug
+            # TODO(aaboagye): Figure out why this happens.
+            elif byte == ord("1") or byte == ord("7"):
+                self.esc_state = EscState.ESC_BRACKET_1
+
+            elif byte == ord("3"):
+                self.esc_state = EscState.ESC_BRACKET_3
+
+            elif byte == ord("8"):
+                self.esc_state = EscState.ESC_BRACKET_8
+
+            else:
+                self.logger.error(
+                    r"Bad or unhandled escape sequence. got ^[%c\(%d)",
+                    chr(byte),
+                    byte,
+                )
+                self.esc_state = 0
+                return
+
+        elif self.esc_state is EscState.ESC_BRACKET_1:
+            self.logger.debug("ESC_BRACKET_1")
+            # HOME key.
+            if byte == ord("~"):
+                self.logger.debug("Home key pressed.")
+                self.MoveCursor("left", self.input_buffer_pos)
+                self.esc_state = 0  # Reset the state.
+                self.logger.debug("ESC sequence complete.")
+                return
+
+        elif self.esc_state is EscState.ESC_BRACKET_3:
+            self.logger.debug("ESC_BRACKET_3")
+            # DEL key.
+            if byte == ord("~"):
+                self.logger.debug("Delete key pressed.")
+                if self.input_buffer_pos != len(self.input_buffer):
+                    self.SliceOutChar()
+                self.esc_state = 0  # Reset the state.
+
+        elif self.esc_state is EscState.ESC_BRACKET_8:
+            self.logger.debug("ESC_BRACKET_8")
+            # END key.
+            if byte == ord("~"):
+                self.logger.debug("End key pressed.")
+                self.MoveCursor(
+                    "right", len(self.input_buffer) - self.input_buffer_pos
+                )
+                self.esc_state = 0  # Reset the state.
+                self.logger.debug("ESC sequence complete.")
+                return
+
+            else:
+                self.logger.error("Unexpected sequence. %c", byte)
+                self.esc_state = 0
+
+        else:
+            self.logger.error("Unexpected sequence. %c", byte)
+            self.esc_state = 0
+
+    def ProcessInput(self):
+        """Captures the input determines what actions to take."""
+        # There's nothing to do if the input buffer is empty.
+        if len(self.input_buffer) == 0:
+            return
+
+        # Don't store 2 consecutive identical commands in the history.
+        if (
+            self.history
+            and self.history[-1] != self.input_buffer
+            or not self.history
+        ):
+            self.history.append(self.input_buffer)
+
+        # Split the command up by spaces.
+        line = self.input_buffer.split(b" ")
+        self.logger.debug("cmd: %s", self.input_buffer)
+        cmd = line[0].lower()
+
+        # The 'history' command is a special case that we handle locally.
+        if cmd == "history":
+            self.PrintHistory()
+            return
+
+        # Send the command to the interpreter.
+        self.logger.debug("Sending command to interpreter.")
+        self.cmd_pipe.send(self.input_buffer)
+
+    def CheckForEnhancedECImage(self):
+        """Performs an interrogation of the EC image.
+
+        Send a SYN and expect an ACK.  If no ACK or the response is incorrect, then
+        assume that the current EC image that we are talking to is not enhanced.
+
+        Returns:
+          is_enhanced: A boolean indicating whether the EC responded to the
+            interrogation correctly.
+
+        Raises:
+          EOFError: Allowed to propagate through from self.dbg_pipe.recv().
+        """
+        # Send interrogation byte and wait for the response.
+        self.logger.debug("Performing interrogation.")
+        self.cmd_pipe.send(interpreter.EC_SYN)
+
+        response = ""
+        if self.dbg_pipe.poll(self.interrogation_timeout):
+            response = self.dbg_pipe.recv()
+            self.logger.debug("response: %r", binascii.hexlify(response))
+        else:
+            self.logger.debug("Timed out waiting for EC_ACK")
+
+        # Verify the acknowledgment.
+        is_enhanced = response == interpreter.EC_ACK
+
+        if is_enhanced:
+            # Increase the interrogation timeout for stability purposes.
+            self.interrogation_timeout = ENHANCED_EC_INTERROGATION_TIMEOUT
+            self.logger.debug(
+                "Increasing interrogation timeout to %rs.",
+                self.interrogation_timeout,
+            )
+        else:
+            # Reduce the timeout in order to reduce the perceivable delay.
+            self.interrogation_timeout = NON_ENHANCED_EC_INTERROGATION_TIMEOUT
+            self.logger.debug(
+                "Reducing interrogation timeout to %rs.",
+                self.interrogation_timeout,
+            )
+
+        return is_enhanced
+
+    def HandleChar(self, byte):
+        """HandleChar does a certain action when it receives a character.
+
+        Args:
+          byte: An integer representing the character received from the user.
+
+        Raises:
+          EOFError: Allowed to propagate through from self.CheckForEnhancedECImage()
+              i.e. from self.dbg_pipe.recv().
+        """
+        fd = self.controller_pty
+
+        # Enter the OOBM prompt mode if the user presses '%'.
+        if byte == ord("%"):
+            self.logger.debug("Begin OOBM command.")
+            self.receiving_oobm_cmd = True
+            # Print a "prompt".
+            os.write(self.controller_pty, b"\r\n% ")
+            return
+
+        # Add chars to the pending OOBM command if we're currently receiving one.
+        if self.receiving_oobm_cmd and byte != ControlKey.CARRIAGE_RETURN:
+            tmp_bytes = six.int2byte(byte)
+            self.pending_oobm_cmd += tmp_bytes
+            self.logger.debug("%s", tmp_bytes)
+            os.write(self.controller_pty, tmp_bytes)
+            return
+
+        if byte == ControlKey.CARRIAGE_RETURN:
+            if self.receiving_oobm_cmd:
+                # Terminate the command and place it in the OOBM queue.
+                self.logger.debug("End OOBM command.")
+                if self.pending_oobm_cmd:
+                    self.oobm_queue.put(self.pending_oobm_cmd)
+                    self.logger.debug(
+                        "Placed %r into OOBM command queue.",
+                        self.pending_oobm_cmd,
+                    )
+
+                # Reset the state.
+                os.write(self.controller_pty, b"\r\n" + self.prompt)
+                self.input_buffer = b""
+                self.input_buffer_pos = 0
+                self.receiving_oobm_cmd = False
+                self.pending_oobm_cmd = b""
+                return
+
+            if self.interrogation_mode == b"never":
+                self.logger.debug(
+                    "Skipping interrogation because interrogation mode"
+                    " is set to never."
+                )
+            elif self.interrogation_mode == b"always":
+                # Only interrogate the EC if the interrogation mode is set to 'always'.
+                self.enhanced_ec = self.CheckForEnhancedECImage()
+                self.logger.debug("Enhanced EC image? %r", self.enhanced_ec)
+
+        if not self.enhanced_ec:
+            # Send everything straight to the EC to handle.
+            self.cmd_pipe.send(six.int2byte(byte))
+            # Reset the input buffer.
+            self.input_buffer = b""
+            self.input_buffer_pos = 0
+            self.logger.log(1, "Reset input buffer.")
+            return
+
+        # Keep handling the ESC sequence if we're in the middle of it.
+        if self.esc_state != 0:
+            self.HandleEsc(byte)
+            return
+
+        # When we're at the end of the line, we should only allow going backwards,
+        # backspace, carriage return, up, or down.  The arrow keys are escape
+        # sequences, so we let the escape...escape.
+        if self.input_buffer_pos >= self.line_limit and byte not in [
+            ControlKey.CTRL_B,
+            ControlKey.ESC,
+            ControlKey.BACKSPACE,
+            ControlKey.CTRL_A,
+            ControlKey.CARRIAGE_RETURN,
+            ControlKey.CTRL_P,
+            ControlKey.CTRL_N,
+        ]:
+            return
+
+        # If the input buffer is full we can't accept new chars.
+        buffer_full = len(self.input_buffer) >= self.line_limit
+
+        # Carriage_Return/Enter
+        if byte == ControlKey.CARRIAGE_RETURN:
+            self.logger.debug("Enter key pressed.")
+            # Put a carriage return/newline and the print the prompt.
+            os.write(fd, b"\r\n")
+
+            # TODO(aaboagye): When we control the printing of all output, print the
+            # prompt AFTER printing all the output.  We can't do it yet because we
+            # don't know how much is coming from the EC.
+
+            # Print the prompt.
+            os.write(fd, self.prompt)
+            # Process the input.
+            self.ProcessInput()
+            # Now, clear the buffer.
+            self.input_buffer = b""
+            self.input_buffer_pos = 0
+            # Reset history buffer pos.
+            self.history_pos = len(self.history)
+            # Clear partial command.
+            self.partial_cmd = b""
+
+        # Backspace
+        elif byte == ControlKey.BACKSPACE:
+            self.logger.debug("Backspace pressed.")
+            if self.input_buffer_pos > 0:
+                # Move left 1 column.
+                self.MoveCursor("left", 1)
+                # Remove the character at the input_buffer_pos by slicing it out.
+                self.SliceOutChar()
+
+            self.logger.debug("input_buffer_pos: %d", self.input_buffer_pos)
+
+        # Ctrl+A. Move cursor to beginning of the line
+        elif byte == ControlKey.CTRL_A:
+            self.logger.debug("Control+A pressed.")
+            self.MoveCursor("left", self.input_buffer_pos)
+
+        # Ctrl+B. Move cursor left 1 column.
+        elif byte == ControlKey.CTRL_B:
+            self.logger.debug("Control+B pressed.")
+            self.MoveCursor("left", 1)
+
+        # Ctrl+D. Delete a character.
+        elif byte == ControlKey.CTRL_D:
+            self.logger.debug("Control+D pressed.")
+            if self.input_buffer_pos != len(self.input_buffer):
+                # Remove the character by slicing it out.
+                self.SliceOutChar()
+
+        # Ctrl+E. Move cursor to end of the line.
+        elif byte == ControlKey.CTRL_E:
+            self.logger.debug("Control+E pressed.")
+            self.MoveCursor(
+                "right", len(self.input_buffer) - self.input_buffer_pos
+            )
+
+        # Ctrl+F. Move cursor right 1 column.
+        elif byte == ControlKey.CTRL_F:
+            self.logger.debug("Control+F pressed.")
+            self.MoveCursor("right", 1)
+
+        # Ctrl+K. Kill line.
+        elif byte == ControlKey.CTRL_K:
+            self.logger.debug("Control+K pressed.")
+            self.KillLine()
+
+        # Ctrl+N. Next line.
+        elif byte == ControlKey.CTRL_N:
+            self.logger.debug("Control+N pressed.")
+            self.ShowNextCommand()
+
+        # Ctrl+P. Previous line.
+        elif byte == ControlKey.CTRL_P:
+            self.logger.debug("Control+P pressed.")
+            self.ShowPreviousCommand()
+
+        # ESC sequence
+        elif byte == ControlKey.ESC:
+            # Starting an ESC sequence
+            self.esc_state = EscState.ESC_START
+
+        # Only print printable chars.
+        elif IsPrintable(byte):
+            # Drop the character if we're full.
+            if buffer_full:
+                self.logger.debug("Dropped char: %c(%d)", byte, byte)
+                return
+            # Print the character.
+            os.write(fd, six.int2byte(byte))
+            # Print the rest of the line (if any).
+            extra_bytes_written = os.write(
+                fd, self.input_buffer[self.input_buffer_pos :]
+            )
+
+            # Recreate the input buffer.
+            self.input_buffer = (
+                self.input_buffer[0 : self.input_buffer_pos]
+                + six.int2byte(byte)
+                + self.input_buffer[self.input_buffer_pos :]
+            )
+            # Update the input buffer position.
+            self.input_buffer_pos += 1 + extra_bytes_written
+
+            # Reset the cursor if we wrote any extra bytes.
+            if extra_bytes_written:
+                self.MoveCursor("left", extra_bytes_written)
+
+            self.logger.debug("input_buffer_pos: %d", self.input_buffer_pos)
+
+    def MoveCursor(self, direction, count):
+        """MoveCursor moves the cursor left or right by count columns.
+
+        Args:
+          direction: A string that should be either 'left' or 'right' representing
+            the direction to move the cursor on the console.
+          count: An integer representing how many columns the cursor should be
+            moved.
+
+        Raises:
+          AssertionError: If the direction is not equal to 'left' or 'right'.
+        """
+        # If there's nothing to move, we're done.
+        if not count:
+            return
+        fd = self.controller_pty
+        seq = b"\033[" + str(count).encode("ascii")
+        if direction == "left":
+            # Bind the movement.
+            if count > self.input_buffer_pos:
+                count = self.input_buffer_pos
+            seq += b"D"
+            self.logger.debug("move cursor left %d", count)
+            self.input_buffer_pos -= count
+
+        elif direction == "right":
+            # Bind the movement.
+            if (count + self.input_buffer_pos) > len(self.input_buffer):
+                count = 0
+            seq += b"C"
+            self.logger.debug("move cursor right %d", count)
+            self.input_buffer_pos += count
+
+        else:
+            raise AssertionError(
+                ("The only valid directions are 'left' and 'right'")
+            )
+
+        self.logger.debug("input_buffer_pos: %d", self.input_buffer_pos)
+        # Move the cursor.
+        if count != 0:
+            os.write(fd, seq)
+
+    def KillLine(self):
+        """Kill the rest of the line based on the input buffer position."""
+        # Killing the line is killing all the text to the right.
+        diff = len(self.input_buffer) - self.input_buffer_pos
+        self.logger.debug("diff: %d", diff)
+        # Diff shouldn't be negative, but if it is for some reason, let's try to
+        # correct the cursor.
+        if diff < 0:
+            self.logger.warning(
+                "Resetting input buffer position to %d...",
+                len(self.input_buffer),
+            )
+            self.MoveCursor("left", -diff)
+            return
+        if diff:
+            self.MoveCursor("right", diff)
+            for _ in range(diff):
+                self.SendBackspace()
+            self.input_buffer_pos -= diff
+            self.input_buffer = self.input_buffer[0 : self.input_buffer_pos]
+
+    def SendBackspace(self):
+        """Backspace a character on the console."""
+        os.write(self.controller_pty, b"\033[1D \033[1D")
+
+    def ProcessOOBMQueue(self):
+        """Retrieve an item from the OOBM queue and process it."""
+        item = self.oobm_queue.get()
+        self.logger.debug("OOBM cmd: %r", item)
+        cmd = item.split(b" ")
+
+        if cmd[0] == b"loglevel":
+            # An integer is required in order to set the log level.
+            if len(cmd) < 2:
+                self.logger.debug("Insufficient args")
+                self.PrintOOBMHelp()
+                return
+            try:
+                self.logger.debug("Log level change request.")
+                new_log_level = int(cmd[1])
+                self.logger.logger.setLevel(new_log_level)
+                self.logger.info("Log level changed to %d.", new_log_level)
+
+                # Forward the request to the interpreter as well.
+                self.cmd_pipe.send(item)
+            except ValueError:
+                # Ignoring the request if an integer was not provided.
+                self.PrintOOBMHelp()
+
+        elif cmd[0] == b"timestamp":
+            mode = cmd[1].lower()
+            self.timestamp_enabled = mode == b"on"
+            self.logger.info(
+                "%sabling uart timestamps.",
+                "En" if self.timestamp_enabled else "Dis",
+            )
+
+        elif cmd[0] == b"rawdebug":
+            mode = cmd[1].lower()
+            self.raw_debug = mode == b"on"
+            self.logger.info(
+                "%sabling per interrupt debug logs.",
+                "En" if self.raw_debug else "Dis",
+            )
+
+        elif cmd[0] == b"interrogate" and len(cmd) >= 2:
+            enhanced = False
+            mode = cmd[1]
+            if len(cmd) >= 3 and cmd[2] == b"enhanced":
+                enhanced = True
+
+            # Set the mode if correct.
+            if mode in INTERROGATION_MODES:
+                self.interrogation_mode = mode
+                self.logger.debug("Updated interrogation mode to %s.", mode)
+
+                # Update the assumptions of the EC image.
+                self.enhanced_ec = enhanced
+                self.logger.debug(
+                    "Enhanced EC image is now %r", self.enhanced_ec
+                )
+
+                # Send command to interpreter as well.
+                self.cmd_pipe.send(
+                    b"enhanced " + str(self.enhanced_ec).encode("ascii")
+                )
+            else:
+                self.PrintOOBMHelp()
+
+        else:
+            self.PrintOOBMHelp()
+
+    def PrintOOBMHelp(self):
+        """Prints out the OOBM help."""
+        # Print help syntax.
+        os.write(self.controller_pty, b"\r\n" + b"Known OOBM commands:\r\n")
+        os.write(
+            self.controller_pty,
+            b"  interrogate <never | always | auto> " b"[enhanced]\r\n",
+        )
+        os.write(self.controller_pty, b"  loglevel <int>\r\n")
+
+    def CheckBufferForEnhancedImage(self, data):
+        """Adds data to a look buffer and checks to see for enhanced EC image.
+
+        The EC's console task prints a string upon initialization which says that
+        "Console is enabled; type HELP for help.".  The enhanced EC images print a
+        different string as a part of their init.  This function searches through a
+        "look" buffer, scanning for the presence of either of those strings and
+        updating the enhanced_ec state accordingly.
+
+        Args:
+          data: A string containing the data sent from the interpreter.
+        """
+        self.look_buffer += data
+
+        # Search the buffer for any of the EC image strings.
+        enhanced_match = re.search(ENHANCED_IMAGE_RE, self.look_buffer)
+        non_enhanced_match = re.search(NON_ENHANCED_IMAGE_RE, self.look_buffer)
+
+        # Update the state if any matches were found.
+        if enhanced_match or non_enhanced_match:
+            if enhanced_match:
+                self.enhanced_ec = True
+            elif non_enhanced_match:
+                self.enhanced_ec = False
+
+            # Inform the interpreter of the result.
+            self.cmd_pipe.send(
+                b"enhanced " + str(self.enhanced_ec).encode("ascii")
+            )
+            self.logger.debug("Enhanced EC image? %r", self.enhanced_ec)
+
+            # Clear look buffer since a match was found.
+            self.look_buffer = b""
+
+        # Move the sliding window.
+        self.look_buffer = self.look_buffer[-LOOK_BUFFER_SIZE:]
 
-    else:
-      self.logger.error('Unexpected sequence. %c', byte)
-      self.esc_state = 0
-
-  def ProcessInput(self):
-    """Captures the input determines what actions to take."""
-    # There's nothing to do if the input buffer is empty.
-    if len(self.input_buffer) == 0:
-      return
-
-    # Don't store 2 consecutive identical commands in the history.
-    if (self.history and self.history[-1] != self.input_buffer
-        or not self.history):
-      self.history.append(self.input_buffer)
-
-    # Split the command up by spaces.
-    line = self.input_buffer.split(b' ')
-    self.logger.debug('cmd: %s', self.input_buffer)
-    cmd = line[0].lower()
-
-    # The 'history' command is a special case that we handle locally.
-    if cmd == 'history':
-      self.PrintHistory()
-      return
-
-    # Send the command to the interpreter.
-    self.logger.debug('Sending command to interpreter.')
-    self.cmd_pipe.send(self.input_buffer)
 
-  def CheckForEnhancedECImage(self):
-    """Performs an interrogation of the EC image.
+def CanonicalizeTimeString(timestr):
+    """Canonicalize the timestamp string.
 
-    Send a SYN and expect an ACK.  If no ACK or the response is incorrect, then
-    assume that the current EC image that we are talking to is not enhanced.
+    Args:
+      timestr: A timestamp string ended with 6 digits msec.
 
     Returns:
-      is_enhanced: A boolean indicating whether the EC responded to the
-        interrogation correctly.
-
-    Raises:
-      EOFError: Allowed to propagate through from self.dbg_pipe.recv().
+      A string with 3 digits msec and an extra space.
     """
-    # Send interrogation byte and wait for the response.
-    self.logger.debug('Performing interrogation.')
-    self.cmd_pipe.send(interpreter.EC_SYN)
-
-    response = ''
-    if self.dbg_pipe.poll(self.interrogation_timeout):
-      response = self.dbg_pipe.recv()
-      self.logger.debug('response: \'%s\'', binascii.hexlify(response))
-    else:
-      self.logger.debug('Timed out waiting for EC_ACK')
+    return timestr[:-3].encode("ascii") + b" "
 
-    # Verify the acknowledgment.
-    is_enhanced = response == interpreter.EC_ACK
-
-    if is_enhanced:
-      # Increase the interrogation timeout for stability purposes.
-      self.interrogation_timeout = ENHANCED_EC_INTERROGATION_TIMEOUT
-      self.logger.debug('Increasing interrogation timeout to %rs.',
-                        self.interrogation_timeout)
-    else:
-      # Reduce the timeout in order to reduce the perceivable delay.
-      self.interrogation_timeout = NON_ENHANCED_EC_INTERROGATION_TIMEOUT
-      self.logger.debug('Reducing interrogation timeout to %rs.',
-                        self.interrogation_timeout)
-
-    return is_enhanced
-
-  def HandleChar(self, byte):
-    """HandleChar does a certain action when it receives a character.
-
-    Args:
-      byte: An integer representing the character received from the user.
 
-    Raises:
-      EOFError: Allowed to propagate through from self.CheckForEnhancedECImage()
-          i.e. from self.dbg_pipe.recv().
-    """
-    fd = self.master_pty
-
-    # Enter the OOBM prompt mode if the user presses '%'.
-    if byte == ord('%'):
-      self.logger.debug('Begin OOBM command.')
-      self.receiving_oobm_cmd = True
-      # Print a "prompt".
-      os.write(self.master_pty, b'\r\n% ')
-      return
-
-    # Add chars to the pending OOBM command if we're currently receiving one.
-    if self.receiving_oobm_cmd and byte != ControlKey.CARRIAGE_RETURN:
-      tmp_bytes = six.int2byte(byte)
-      self.pending_oobm_cmd += tmp_bytes
-      self.logger.debug('%s', tmp_bytes)
-      os.write(self.master_pty, tmp_bytes)
-      return
-
-    if byte == ControlKey.CARRIAGE_RETURN:
-      if self.receiving_oobm_cmd:
-        # Terminate the command and place it in the OOBM queue.
-        self.logger.debug('End OOBM command.')
-        if self.pending_oobm_cmd:
-          self.oobm_queue.put(self.pending_oobm_cmd)
-          self.logger.debug('Placed \'%s\' into OOBM command queue.',
-                            self.pending_oobm_cmd)
-
-        # Reset the state.
-        os.write(self.master_pty, b'\r\n' + self.prompt)
-        self.input_buffer = b''
-        self.input_buffer_pos = 0
-        self.receiving_oobm_cmd = False
-        self.pending_oobm_cmd = b''
-        return
-
-      if self.interrogation_mode == b'never':
-        self.logger.debug('Skipping interrogation because interrogation mode'
-                          ' is set to never.')
-      elif self.interrogation_mode == b'always':
-        # Only interrogate the EC if the interrogation mode is set to 'always'.
-        self.enhanced_ec = self.CheckForEnhancedECImage()
-        self.logger.debug('Enhanced EC image? %r', self.enhanced_ec)
-
-    if not self.enhanced_ec:
-      # Send everything straight to the EC to handle.
-      self.cmd_pipe.send(six.int2byte(byte))
-      # Reset the input buffer.
-      self.input_buffer = b''
-      self.input_buffer_pos = 0
-      self.logger.log(1, 'Reset input buffer.')
-      return
-
-    # Keep handling the ESC sequence if we're in the middle of it.
-    if self.esc_state != 0:
-      self.HandleEsc(byte)
-      return
-
-    # When we're at the end of the line, we should only allow going backwards,
-    # backspace, carriage return, up, or down.  The arrow keys are escape
-    # sequences, so we let the escape...escape.
-    if (self.input_buffer_pos >= self.line_limit and
-        byte not in [ControlKey.CTRL_B, ControlKey.ESC, ControlKey.BACKSPACE,
-                     ControlKey.CTRL_A, ControlKey.CARRIAGE_RETURN,
-                     ControlKey.CTRL_P, ControlKey.CTRL_N]):
-      return
-
-    # If the input buffer is full we can't accept new chars.
-    buffer_full = len(self.input_buffer) >= self.line_limit
-
-
-    # Carriage_Return/Enter
-    if byte == ControlKey.CARRIAGE_RETURN:
-      self.logger.debug('Enter key pressed.')
-      # Put a carriage return/newline and the print the prompt.
-      os.write(fd, b'\r\n')
-
-      # TODO(aaboagye): When we control the printing of all output, print the
-      # prompt AFTER printing all the output.  We can't do it yet because we
-      # don't know how much is coming from the EC.
-
-      # Print the prompt.
-      os.write(fd, self.prompt)
-      # Process the input.
-      self.ProcessInput()
-      # Now, clear the buffer.
-      self.input_buffer = b''
-      self.input_buffer_pos = 0
-      # Reset history buffer pos.
-      self.history_pos = len(self.history)
-      # Clear partial command.
-      self.partial_cmd = b''
-
-    # Backspace
-    elif byte == ControlKey.BACKSPACE:
-      self.logger.debug('Backspace pressed.')
-      if self.input_buffer_pos > 0:
-        # Move left 1 column.
-        self.MoveCursor('left', 1)
-        # Remove the character at the input_buffer_pos by slicing it out.
-        self.SliceOutChar()
-
-      self.logger.debug('input_buffer_pos: %d', self.input_buffer_pos)
-
-    # Ctrl+A. Move cursor to beginning of the line
-    elif byte == ControlKey.CTRL_A:
-      self.logger.debug('Control+A pressed.')
-      self.MoveCursor('left', self.input_buffer_pos)
-
-    # Ctrl+B. Move cursor left 1 column.
-    elif byte == ControlKey.CTRL_B:
-      self.logger.debug('Control+B pressed.')
-      self.MoveCursor('left', 1)
-
-    # Ctrl+D. Delete a character.
-    elif byte == ControlKey.CTRL_D:
-      self.logger.debug('Control+D pressed.')
-      if self.input_buffer_pos != len(self.input_buffer):
-        # Remove the character by slicing it out.
-        self.SliceOutChar()
-
-    # Ctrl+E. Move cursor to end of the line.
-    elif byte == ControlKey.CTRL_E:
-      self.logger.debug('Control+E pressed.')
-      self.MoveCursor('right',
-                      len(self.input_buffer) - self.input_buffer_pos)
-
-    # Ctrl+F. Move cursor right 1 column.
-    elif byte == ControlKey.CTRL_F:
-      self.logger.debug('Control+F pressed.')
-      self.MoveCursor('right', 1)
-
-    # Ctrl+K. Kill line.
-    elif byte == ControlKey.CTRL_K:
-      self.logger.debug('Control+K pressed.')
-      self.KillLine()
-
-    # Ctrl+N. Next line.
-    elif byte == ControlKey.CTRL_N:
-      self.logger.debug('Control+N pressed.')
-      self.ShowNextCommand()
-
-    # Ctrl+P. Previous line.
-    elif byte == ControlKey.CTRL_P:
-      self.logger.debug('Control+P pressed.')
-      self.ShowPreviousCommand()
-
-    # ESC sequence
-    elif byte == ControlKey.ESC:
-      # Starting an ESC sequence
-      self.esc_state = EscState.ESC_START
-
-    # Only print printable chars.
-    elif IsPrintable(byte):
-      # Drop the character if we're full.
-      if buffer_full:
-        self.logger.debug('Dropped char: %c(%d)', byte, byte)
-        return
-      # Print the character.
-      os.write(fd, six.int2byte(byte))
-      # Print the rest of the line (if any).
-      extra_bytes_written = os.write(fd,
-                                     self.input_buffer[self.input_buffer_pos:])
-
-      # Recreate the input buffer.
-      self.input_buffer = (self.input_buffer[0:self.input_buffer_pos] +
-                           six.int2byte(byte) +
-                           self.input_buffer[self.input_buffer_pos:])
-      # Update the input buffer position.
-      self.input_buffer_pos += 1 + extra_bytes_written
-
-      # Reset the cursor if we wrote any extra bytes.
-      if extra_bytes_written:
-        self.MoveCursor('left', extra_bytes_written)
-
-      self.logger.debug('input_buffer_pos: %d', self.input_buffer_pos)
-
-  def MoveCursor(self, direction, count):
-    """MoveCursor moves the cursor left or right by count columns.
+def IsPrintable(byte):
+    """Determines if a byte is printable.
 
     Args:
-      direction: A string that should be either 'left' or 'right' representing
-        the direction to move the cursor on the console.
-      count: An integer representing how many columns the cursor should be
-        moved.
+      byte: An integer potentially representing a printable character.
 
-    Raises:
-      AssertionError: If the direction is not equal to 'left' or 'right'.
+    Returns:
+      A boolean indicating whether the byte is a printable character.
     """
-    # If there's nothing to move, we're done.
-    if not count:
-      return
-    fd = self.master_pty
-    seq = b'\033[' + str(count).encode('ascii')
-    if direction == 'left':
-      # Bind the movement.
-      if count > self.input_buffer_pos:
-        count = self.input_buffer_pos
-      seq += b'D'
-      self.logger.debug('move cursor left %d', count)
-      self.input_buffer_pos -= count
-
-    elif direction == 'right':
-      # Bind the movement.
-      if (count + self.input_buffer_pos) > len(self.input_buffer):
-        count = 0
-      seq += b'C'
-      self.logger.debug('move cursor right %d', count)
-      self.input_buffer_pos += count
-
-    else:
-      raise AssertionError(('The only valid directions are \'left\' and '
-                            '\'right\''))
-
-    self.logger.debug('input_buffer_pos: %d', self.input_buffer_pos)
-    # Move the cursor.
-    if count != 0:
-      os.write(fd, seq)
-
-  def KillLine(self):
-    """Kill the rest of the line based on the input buffer position."""
-    # Killing the line is killing all the text to the right.
-    diff = len(self.input_buffer) - self.input_buffer_pos
-    self.logger.debug('diff: %d', diff)
-    # Diff shouldn't be negative, but if it is for some reason, let's try to
-    # correct the cursor.
-    if diff < 0:
-      self.logger.warning('Resetting input buffer position to %d...',
-                          len(self.input_buffer))
-      self.MoveCursor('left', -diff)
-      return
-    if diff:
-      self.MoveCursor('right', diff)
-      for _ in range(diff):
-        self.SendBackspace()
-      self.input_buffer_pos -= diff
-      self.input_buffer = self.input_buffer[0:self.input_buffer_pos]
-
-  def SendBackspace(self):
-    """Backspace a character on the console."""
-    os.write(self.master_pty, b'\033[1D \033[1D')
-
-  def ProcessOOBMQueue(self):
-    """Retrieve an item from the OOBM queue and process it."""
-    item = self.oobm_queue.get()
-    self.logger.debug('OOBM cmd: %s', item)
-    cmd = item.split(b' ')
-
-    if cmd[0] == b'loglevel':
-      # An integer is required in order to set the log level.
-      if len(cmd) < 2:
-        self.logger.debug('Insufficient args')
-        self.PrintOOBMHelp()
-        return
-      try:
-        self.logger.debug('Log level change request.')
-        new_log_level = int(cmd[1])
-        self.logger.logger.setLevel(new_log_level)
-        self.logger.info('Log level changed to %d.', new_log_level)
-
-        # Forward the request to the interpreter as well.
-        self.cmd_pipe.send(item)
-      except ValueError:
-        # Ignoring the request if an integer was not provided.
-        self.PrintOOBMHelp()
-
-    elif cmd[0] == b'timestamp':
-      mode = cmd[1].lower()
-      self.timestamp_enabled = mode == 'on'
-      self.logger.info('%sabling uart timestamps.',
-                       'En' if self.timestamp_enabled else 'Dis')
-
-    elif cmd[0] == b'rawdebug':
-      mode = cmd[1].lower()
-      self.raw_debug = mode == 'on'
-      self.logger.info('%sabling per interrupt debug logs.',
-                       'En' if self.raw_debug else 'Dis')
-
-    elif cmd[0] == b'interrogate' and len(cmd) >= 2:
-      enhanced = False
-      mode = cmd[1]
-      if len(cmd) >= 3 and cmd[2] == b'enhanced':
-        enhanced = True
-
-      # Set the mode if correct.
-      if mode in INTERROGATION_MODES:
-        self.interrogation_mode = mode
-        self.logger.debug('Updated interrogation mode to %s.', mode)
-
-        # Update the assumptions of the EC image.
-        self.enhanced_ec = enhanced
-        self.logger.debug('Enhanced EC image is now %r', self.enhanced_ec)
-
-        # Send command to interpreter as well.
-        self.cmd_pipe.send(b'enhanced ' + str(self.enhanced_ec).encode('ascii'))
-      else:
-        self.PrintOOBMHelp()
-
-    else:
-      self.PrintOOBMHelp()
-
-  def PrintOOBMHelp(self):
-    """Prints out the OOBM help."""
-    # Print help syntax.
-    os.write(self.master_pty, b'\r\n' + b'Known OOBM commands:\r\n')
-    os.write(self.master_pty, b'  interrogate <never | always | auto> '
-             b'[enhanced]\r\n')
-    os.write(self.master_pty, b'  loglevel <int>\r\n')
+    return byte >= ord(" ") and byte <= ord("~")
 
-  def CheckBufferForEnhancedImage(self, data):
-    """Adds data to a look buffer and checks to see for enhanced EC image.
 
-    The EC's console task prints a string upon initialization which says that
-    "Console is enabled; type HELP for help.".  The enhanced EC images print a
-    different string as a part of their init.  This function searches through a
-    "look" buffer, scanning for the presence of either of those strings and
-    updating the enhanced_ec state accordingly.
+def StartLoop(console, command_active, shutdown_pipe=None):
+    """Starts the infinite loop of console processing.
 
     Args:
-      data: A string containing the data sent from the interpreter.
+      console: A Console object that has been properly initialzed.
+      command_active: ctypes data object or multiprocessing.Value indicating if
+        servod owns the console, or user owns the console. This prevents input
+        collisions.
+      shutdown_pipe: A file object for a pipe or equivalent that becomes readable
+        (not blocked) to indicate that the loop should exit.  Can be None to never
+        exit the loop.
     """
-    self.look_buffer += data
-
-    # Search the buffer for any of the EC image strings.
-    enhanced_match = re.search(ENHANCED_IMAGE_RE, self.look_buffer)
-    non_enhanced_match = re.search(NON_ENHANCED_IMAGE_RE, self.look_buffer)
-
-    # Update the state if any matches were found.
-    if enhanced_match or non_enhanced_match:
-      if enhanced_match:
-        self.enhanced_ec = True
-      elif non_enhanced_match:
-        self.enhanced_ec = False
-
-      # Inform the interpreter of the result.
-      self.cmd_pipe.send(b'enhanced ' + str(self.enhanced_ec).encode('ascii'))
-      self.logger.debug('Enhanced EC image? %r', self.enhanced_ec)
-
-      # Clear look buffer since a match was found.
-      self.look_buffer = b''
-
-    # Move the sliding window.
-    self.look_buffer = self.look_buffer[-LOOK_BUFFER_SIZE:]
+    try:
+        console.logger.debug("Console is being served on %s.", console.user_pty)
+        console.logger.debug(
+            "Console controller is on %s.", console.controller_pty
+        )
+        console.logger.debug(
+            "Command interface is being served on %s.", console.interface_pty
+        )
+        console.logger.debug(console)
+
+        # This checks for HUP to indicate if the user has connected to the pty.
+        ep = select.epoll()
+        ep.register(console.controller_pty, select.EPOLLHUP)
+
+        # This is used instead of "break" to avoid exiting the loop in the middle of
+        # an iteration.
+        continue_looping = True
+
+        # Used for determining when to print host timestamps
+        tm_req = True
+
+        while continue_looping:
+            # Check to see if pts is connected to anything
+            events = ep.poll(0)
+            controller_connected = not events
+
+            # Check to see if pipes or the console are ready for reading.
+            read_list = [
+                console.interface_pty,
+                console.cmd_pipe,
+                console.dbg_pipe,
+            ]
+            if controller_connected:
+                read_list.append(console.controller_pty)
+            if shutdown_pipe is not None:
+                read_list.append(shutdown_pipe)
+
+            # Check if any input is ready, or wait for .1 sec and re-poll if
+            # a user has connected to the pts.
+            select_output = select.select(read_list, [], [], 0.1)
+            if not select_output:
+                continue
+            ready_for_reading = select_output[0]
+
+            for obj in ready_for_reading:
+                if obj is console.controller_pty:
+                    if not command_active.value:
+                        # Convert to bytes so we can look for non-printable chars such as
+                        # Ctrl+A, Ctrl+E, etc.
+                        try:
+                            line = bytearray(
+                                os.read(
+                                    console.controller_pty, CONSOLE_MAX_READ
+                                )
+                            )
+                            console.logger.debug(
+                                "Input from user: %s, locked:%s",
+                                str(line).strip(),
+                                command_active.value,
+                            )
+                            for i in line:
+                                try:
+                                    # Handle each character as it arrives.
+                                    console.HandleChar(i)
+                                except EOFError:
+                                    console.logger.debug(
+                                        "ec3po console received EOF from dbg_pipe in HandleChar()"
+                                        " while reading console.controller_pty"
+                                    )
+                                    continue_looping = False
+                                    break
+                        except OSError:
+                            console.logger.debug(
+                                "Ptm read failed, probably user disconnect."
+                            )
+
+                elif obj is console.interface_pty:
+                    if command_active.value:
+                        # Convert to bytes so we can look for non-printable chars such as
+                        # Ctrl+A, Ctrl+E, etc.
+                        line = bytearray(
+                            os.read(console.interface_pty, CONSOLE_MAX_READ)
+                        )
+                        console.logger.debug(
+                            "Input from interface: %s, locked:%s",
+                            str(line).strip(),
+                            command_active.value,
+                        )
+                        for i in line:
+                            try:
+                                # Handle each character as it arrives.
+                                console.HandleChar(i)
+                            except EOFError:
+                                console.logger.debug(
+                                    "ec3po console received EOF from dbg_pipe in HandleChar()"
+                                    " while reading console.interface_pty"
+                                )
+                                continue_looping = False
+                                break
+
+                elif obj is console.cmd_pipe:
+                    try:
+                        data = console.cmd_pipe.recv()
+                    except EOFError:
+                        console.logger.debug(
+                            "ec3po console received EOF from cmd_pipe"
+                        )
+                        continue_looping = False
+                    else:
+                        # Write it to the user console.
+                        if console.raw_debug:
+                            console.logger.debug(
+                                "|CMD|-%s->%r",
+                                ("u" if controller_connected else "")
+                                + ("i" if command_active.value else ""),
+                                data.strip(),
+                            )
+                        if controller_connected:
+                            os.write(console.controller_pty, data)
+                        if command_active.value:
+                            os.write(console.interface_pty, data)
+
+                elif obj is console.dbg_pipe:
+                    try:
+                        data = console.dbg_pipe.recv()
+                    except EOFError:
+                        console.logger.debug(
+                            "ec3po console received EOF from dbg_pipe"
+                        )
+                        continue_looping = False
+                    else:
+                        if console.interrogation_mode == b"auto":
+                            # Search look buffer for enhanced EC image string.
+                            console.CheckBufferForEnhancedImage(data)
+                        # Write it to the user console.
+                        if len(data) > 1 and console.raw_debug:
+                            console.logger.debug(
+                                "|DBG|-%s->%r",
+                                ("u" if controller_connected else "")
+                                + ("i" if command_active.value else ""),
+                                data.strip(),
+                            )
+                        console.LogConsoleOutput(data)
+                        if controller_connected:
+                            end = len(data) - 1
+                            if console.timestamp_enabled:
+                                # A timestamp is required at the beginning of this line
+                                if tm_req is True:
+                                    now = datetime.now()
+                                    tm = CanonicalizeTimeString(
+                                        now.strftime(HOST_STRFTIME)
+                                    )
+                                    os.write(console.controller_pty, tm)
+                                    tm_req = False
+
+                                # Insert timestamps into the middle where appropriate
+                                # except if the last character is a newline
+                                nls_found = data.count(b"\n", 0, end)
+                                now = datetime.now()
+                                tm = CanonicalizeTimeString(
+                                    now.strftime("\n" + HOST_STRFTIME)
+                                )
+                                data_tm = data.replace(b"\n", tm, nls_found)
+                            else:
+                                data_tm = data
+
+                            # timestamp required on next input
+                            if data[end] == b"\n"[0]:
+                                tm_req = True
+                            os.write(console.controller_pty, data_tm)
+                        if command_active.value:
+                            os.write(console.interface_pty, data)
+
+                elif obj is shutdown_pipe:
+                    console.logger.debug(
+                        "ec3po console received shutdown pipe unblocked notification"
+                    )
+                    continue_looping = False
+
+            while not console.oobm_queue.empty():
+                console.logger.debug("OOBM queue ready for reading.")
+                console.ProcessOOBMQueue()
+
+    except KeyboardInterrupt:
+        pass
+
+    finally:
+        ep.unregister(console.controller_pty)
+        console.dbg_pipe.close()
+        console.cmd_pipe.close()
+        os.close(console.controller_pty)
+        os.close(console.interface_pty)
+        if shutdown_pipe is not None:
+            shutdown_pipe.close()
+        console.logger.debug("Exit ec3po console loop for %s", console.user_pty)
 
 
-def CanonicalizeTimeString(timestr):
-  """Canonicalize the timestamp string.
-
-  Args:
-    timestr: A timestamp string ended with 6 digits msec.
-
-  Returns:
-    A string with 3 digits msec and an extra space.
-  """
-  return timestr[:-3].encode('ascii') + b' '
-
-
-def IsPrintable(byte):
-  """Determines if a byte is printable.
-
-  Args:
-    byte: An integer potentially representing a printable character.
-
-  Returns:
-    A boolean indicating whether the byte is a printable character.
-  """
-  return byte >= ord(' ') and byte <= ord('~')
-
-
-def StartLoop(console, command_active, shutdown_pipe=None):
-  """Starts the infinite loop of console processing.
-
-  Args:
-    console: A Console object that has been properly initialzed.
-    command_active: ctypes data object or multiprocessing.Value indicating if
-      servod owns the console, or user owns the console. This prevents input
-      collisions.
-    shutdown_pipe: A file object for a pipe or equivalent that becomes readable
-      (not blocked) to indicate that the loop should exit.  Can be None to never
-      exit the loop.
-  """
-  try:
-    console.logger.debug('Console is being served on %s.', console.user_pty)
-    console.logger.debug('Console master is on %s.', console.master_pty)
-    console.logger.debug('Command interface is being served on %s.',
-        console.interface_pty)
-    console.logger.debug(console)
-
-    # This checks for HUP to indicate if the user has connected to the pty.
-    ep = select.epoll()
-    ep.register(console.master_pty, select.EPOLLHUP)
-
-    # This is used instead of "break" to avoid exiting the loop in the middle of
-    # an iteration.
-    continue_looping = True
-
-    # Used for determining when to print host timestamps
-    tm_req = True
-
-    while continue_looping:
-      # Check to see if pts is connected to anything
-      events = ep.poll(0)
-      master_connected = not events
-
-      # Check to see if pipes or the console are ready for reading.
-      read_list = [console.interface_pty,
-                   console.cmd_pipe, console.dbg_pipe]
-      if master_connected:
-        read_list.append(console.master_pty)
-      if shutdown_pipe is not None:
-        read_list.append(shutdown_pipe)
-
-      # Check if any input is ready, or wait for .1 sec and re-poll if
-      # a user has connected to the pts.
-      select_output = select.select(read_list, [], [], .1)
-      if not select_output:
-        continue
-      ready_for_reading = select_output[0]
-
-      for obj in ready_for_reading:
-        if obj is console.master_pty:
-          if not command_active.value:
-            # Convert to bytes so we can look for non-printable chars such as
-            # Ctrl+A, Ctrl+E, etc.
-            try:
-              line = bytearray(os.read(console.master_pty, CONSOLE_MAX_READ))
-              console.logger.debug('Input from user: %s, locked:%s',
-                  str(line).strip(), command_active.value)
-              for i in line:
-                try:
-                  # Handle each character as it arrives.
-                  console.HandleChar(i)
-                except EOFError:
-                  console.logger.debug(
-                      'ec3po console received EOF from dbg_pipe in HandleChar()'
-                      ' while reading console.master_pty')
-                  continue_looping = False
-                  break
-            except OSError:
-              console.logger.debug('Ptm read failed, probably user disconnect.')
-
-        elif obj is console.interface_pty:
-          if command_active.value:
-            # Convert to bytes so we can look for non-printable chars such as
-            # Ctrl+A, Ctrl+E, etc.
-            line = bytearray(os.read(console.interface_pty, CONSOLE_MAX_READ))
-            console.logger.debug('Input from interface: %s, locked:%s',
-                str(line).strip(), command_active.value)
-            for i in line:
-              try:
-                # Handle each character as it arrives.
-                console.HandleChar(i)
-              except EOFError:
-                console.logger.debug(
-                    'ec3po console received EOF from dbg_pipe in HandleChar()'
-                    ' while reading console.interface_pty')
-                continue_looping = False
-                break
-
-        elif obj is console.cmd_pipe:
-          try:
-            data = console.cmd_pipe.recv()
-          except EOFError:
-            console.logger.debug('ec3po console received EOF from cmd_pipe')
-            continue_looping = False
-          else:
-            # Write it to the user console.
-            if console.raw_debug:
-              console.logger.debug('|CMD|-%s->\'%s\'',
-                                   ('u' if master_connected else '') +
-                                   ('i' if command_active.value else ''),
-                                   data.strip())
-            if master_connected:
-              os.write(console.master_pty, data)
-            if command_active.value:
-              os.write(console.interface_pty, data)
-
-        elif obj is console.dbg_pipe:
-          try:
-            data = console.dbg_pipe.recv()
-          except EOFError:
-            console.logger.debug('ec3po console received EOF from dbg_pipe')
-            continue_looping = False
-          else:
-            if console.interrogation_mode == b'auto':
-              # Search look buffer for enhanced EC image string.
-              console.CheckBufferForEnhancedImage(data)
-            # Write it to the user console.
-            if len(data) > 1 and console.raw_debug:
-              console.logger.debug('|DBG|-%s->\'%s\'',
-                                   ('u' if master_connected else '') +
-                                   ('i' if command_active.value else ''),
-                                   data.strip())
-            console.LogConsoleOutput(data)
-            if master_connected:
-              end = len(data) - 1
-              if console.timestamp_enabled:
-                # A timestamp is required at the beginning of this line
-                if tm_req is True:
-                  now = datetime.now()
-                  tm = CanonicalizeTimeString(now.strftime(HOST_STRFTIME))
-                  os.write(console.master_pty, tm)
-                  tm_req = False
-
-                # Insert timestamps into the middle where appropriate
-                # except if the last character is a newline
-                nls_found = data.count(b'\n', 0, end)
-                now = datetime.now()
-                tm = CanonicalizeTimeString(now.strftime('\n' + HOST_STRFTIME))
-                data_tm = data.replace(b'\n', tm, nls_found)
-              else:
-                data_tm = data
-
-              # timestamp required on next input
-              if data[end] == b'\n':
-                tm_req = True
-              os.write(console.master_pty, data_tm)
-            if command_active.value:
-              os.write(console.interface_pty, data)
-
-        elif obj is shutdown_pipe:
-          console.logger.debug(
-              'ec3po console received shutdown pipe unblocked notification')
-          continue_looping = False
-
-      while not console.oobm_queue.empty():
-        console.logger.debug('OOBM queue ready for reading.')
-        console.ProcessOOBMQueue()
-
-  except KeyboardInterrupt:
-    pass
-
-  finally:
-    ep.unregister(console.master_pty)
-    console.dbg_pipe.close()
-    console.cmd_pipe.close()
-    os.close(console.master_pty)
-    os.close(console.interface_pty)
-    if shutdown_pipe is not None:
-      shutdown_pipe.close()
-    console.logger.debug('Exit ec3po console loop for %s', console.user_pty)
+def main(argv):
+    """Kicks off the EC-3PO interactive console interface and interpreter.
 
+    We create some pipes to communicate with an interpreter, instantiate an
+    interpreter, create a PTY pair, and begin serving the console interface.
 
-def main(argv):
-  """Kicks off the EC-3PO interactive console interface and interpreter.
-
-  We create some pipes to communicate with an interpreter, instantiate an
-  interpreter, create a PTY pair, and begin serving the console interface.
-
-  Args:
-    argv: A list of strings containing the arguments this module was called
-      with.
-  """
-  # Set up argument parser.
-  parser = argparse.ArgumentParser(description=('Start interactive EC console '
-                                                'and interpreter.'))
-  parser.add_argument('ec_uart_pty',
-                      help=('The full PTY name that the EC UART'
-                            ' is present on. eg: /dev/pts/12'))
-  parser.add_argument('--log-level',
-                      default='info',
-                      help='info, debug, warning, error, or critical')
-
-  # Parse arguments.
-  opts = parser.parse_args(argv)
-
-  # Set logging level.
-  opts.log_level = opts.log_level.lower()
-  if opts.log_level == 'info':
-    log_level = logging.INFO
-  elif opts.log_level == 'debug':
-    log_level = logging.DEBUG
-  elif opts.log_level == 'warning':
-    log_level = logging.WARNING
-  elif opts.log_level == 'error':
-    log_level = logging.ERROR
-  elif opts.log_level == 'critical':
-    log_level = logging.CRITICAL
-  else:
-    parser.error('Invalid log level. (info, debug, warning, error, critical)')
-
-  # Start logging with a timestamp, module, and log level shown in each log
-  # entry.
-  logging.basicConfig(level=log_level, format=('%(asctime)s - %(module)s -'
-                                               ' %(levelname)s - %(message)s'))
-
-  # Create some pipes to communicate between the interpreter and the console.
-  # The command pipe is bidirectional.
-  cmd_pipe_interactive, cmd_pipe_interp = threadproc_shim.Pipe()
-  # The debug pipe is unidirectional from interpreter to console only.
-  dbg_pipe_interactive, dbg_pipe_interp = threadproc_shim.Pipe(duplex=False)
-
-  # Create an interpreter instance.
-  itpr = interpreter.Interpreter(opts.ec_uart_pty, cmd_pipe_interp,
-                                 dbg_pipe_interp, log_level)
-
-  # Spawn an interpreter process.
-  itpr_process = threadproc_shim.ThreadOrProcess(
-      target=interpreter.StartLoop, args=(itpr,))
-  # Make sure to kill the interpreter when we terminate.
-  itpr_process.daemon = True
-  # Start the interpreter.
-  itpr_process.start()
-
-  # Open a new pseudo-terminal pair
-  (master_pty, user_pty) = pty.openpty()
-  # Set the permissions to 660.
-  os.chmod(os.ttyname(user_pty), (stat.S_IRGRP | stat.S_IWGRP |
-                                  stat.S_IRUSR | stat.S_IWUSR))
-  # Create a console.
-  console = Console(master_pty, os.ttyname(user_pty), cmd_pipe_interactive,
-                    dbg_pipe_interactive)
-  # Start serving the console.
-  v = threadproc_shim.Value(ctypes.c_bool, False)
-  StartLoop(console, v)
-
-
-if __name__ == '__main__':
-  main(sys.argv[1:])
+    Args:
+      argv: A list of strings containing the arguments this module was called
+        with.
+    """
+    # Set up argument parser.
+    parser = argparse.ArgumentParser(
+        description=("Start interactive EC console and interpreter.")
+    )
+    parser.add_argument(
+        "ec_uart_pty",
+        help=(
+            "The full PTY name that the EC UART is present on. eg: /dev/pts/12"
+        ),
+    )
+    parser.add_argument(
+        "--log-level",
+        default="info",
+        help="info, debug, warning, error, or critical",
+    )
+
+    # Parse arguments.
+    opts = parser.parse_args(argv)
+
+    # Set logging level.
+    opts.log_level = opts.log_level.lower()
+    if opts.log_level == "info":
+        log_level = logging.INFO
+    elif opts.log_level == "debug":
+        log_level = logging.DEBUG
+    elif opts.log_level == "warning":
+        log_level = logging.WARNING
+    elif opts.log_level == "error":
+        log_level = logging.ERROR
+    elif opts.log_level == "critical":
+        log_level = logging.CRITICAL
+    else:
+        parser.error(
+            "Invalid log level. (info, debug, warning, error, critical)"
+        )
+
+    # Start logging with a timestamp, module, and log level shown in each log
+    # entry.
+    logging.basicConfig(
+        level=log_level,
+        format=("%(asctime)s - %(module)s - %(levelname)s - %(message)s"),
+    )
+
+    # Create some pipes to communicate between the interpreter and the console.
+    # The command pipe is bidirectional.
+    cmd_pipe_interactive, cmd_pipe_interp = threadproc_shim.Pipe()
+    # The debug pipe is unidirectional from interpreter to console only.
+    dbg_pipe_interactive, dbg_pipe_interp = threadproc_shim.Pipe(duplex=False)
+
+    # Create an interpreter instance.
+    itpr = interpreter.Interpreter(
+        opts.ec_uart_pty, cmd_pipe_interp, dbg_pipe_interp, log_level
+    )
+
+    # Spawn an interpreter process.
+    itpr_process = threadproc_shim.ThreadOrProcess(
+        target=interpreter.StartLoop, args=(itpr,)
+    )
+    # Make sure to kill the interpreter when we terminate.
+    itpr_process.daemon = True
+    # Start the interpreter.
+    itpr_process.start()
+
+    # Open a new pseudo-terminal pair
+    (controller_pty, user_pty) = pty.openpty()
+    # Set the permissions to 660.
+    os.chmod(
+        os.ttyname(user_pty),
+        (stat.S_IRGRP | stat.S_IWGRP | stat.S_IRUSR | stat.S_IWUSR),
+    )
+    # Create a console.
+    console = Console(
+        controller_pty,
+        os.ttyname(user_pty),
+        os.ttyname(controller_pty),
+        cmd_pipe_interactive,
+        dbg_pipe_interactive,
+    )
+    # Start serving the console.
+    v = threadproc_shim.Value(ctypes.c_bool, False)
+    StartLoop(console, v)
+
+
+if __name__ == "__main__":
+    main(sys.argv[1:])
diff --git a/util/ec3po/console_unittest.py b/util/ec3po/console_unittest.py
index 66f47be358..dfa411f3c8 100755
--- a/util/ec3po/console_unittest.py
+++ b/util/ec3po/console_unittest.py
@@ -1,5 +1,5 @@
 #!/usr/bin/env python
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -10,1264 +10,1321 @@
 from __future__ import print_function
 
 import binascii
-# pylint: disable=cros-logging-import
 import logging
-import mock
 import tempfile
 import unittest
 
+from ec3po import console
+from ec3po import interpreter
+from ec3po import threadproc_shim
+import mock  # pylint:disable=import-error
 import six
 
-import console
-import interpreter
-import threadproc_shim
 
 ESC_STRING = six.int2byte(console.ControlKey.ESC)
 
+
 class Keys(object):
-  """A class that contains the escape sequences for special keys."""
-  LEFT_ARROW = [console.ControlKey.ESC, ord('['), ord('D')]
-  RIGHT_ARROW = [console.ControlKey.ESC, ord('['), ord('C')]
-  UP_ARROW = [console.ControlKey.ESC, ord('['), ord('A')]
-  DOWN_ARROW = [console.ControlKey.ESC, ord('['), ord('B')]
-  HOME = [console.ControlKey.ESC, ord('['), ord('1'), ord('~')]
-  END = [console.ControlKey.ESC, ord('['), ord('8'), ord('~')]
-  DEL = [console.ControlKey.ESC, ord('['), ord('3'), ord('~')]
+    """A class that contains the escape sequences for special keys."""
+
+    LEFT_ARROW = [console.ControlKey.ESC, ord("["), ord("D")]
+    RIGHT_ARROW = [console.ControlKey.ESC, ord("["), ord("C")]
+    UP_ARROW = [console.ControlKey.ESC, ord("["), ord("A")]
+    DOWN_ARROW = [console.ControlKey.ESC, ord("["), ord("B")]
+    HOME = [console.ControlKey.ESC, ord("["), ord("1"), ord("~")]
+    END = [console.ControlKey.ESC, ord("["), ord("8"), ord("~")]
+    DEL = [console.ControlKey.ESC, ord("["), ord("3"), ord("~")]
+
 
 class OutputStream(object):
-  """A class that has methods which return common console output."""
+    """A class that has methods which return common console output."""
 
-  @staticmethod
-  def MoveCursorLeft(count):
-    """Produces what would be printed to the console if the cursor moved left.
+    @staticmethod
+    def MoveCursorLeft(count):
+        """Produces what would be printed to the console if the cursor moved left.
 
-    Args:
-      count: An integer representing how many columns to move left.
+        Args:
+          count: An integer representing how many columns to move left.
 
-    Returns:
-      string: A string which contains what would be printed to the console if
-        the cursor moved left.
-    """
-    string = ESC_STRING
-    string += b'[' + str(count).encode('ascii') + b'D'
-    return string
+        Returns:
+          string: A string which contains what would be printed to the console if
+            the cursor moved left.
+        """
+        string = ESC_STRING
+        string += b"[" + str(count).encode("ascii") + b"D"
+        return string
 
-  @staticmethod
-  def MoveCursorRight(count):
-    """Produces what would be printed to the console if the cursor moved right.
+    @staticmethod
+    def MoveCursorRight(count):
+        """Produces what would be printed to the console if the cursor moved right.
 
-    Args:
-      count: An integer representing how many columns to move right.
+        Args:
+          count: An integer representing how many columns to move right.
 
-    Returns:
-      string: A string which contains what would be printed to the console if
-        the cursor moved right.
-    """
-    string = ESC_STRING
-    string += b'[' + str(count).encode('ascii') + b'C'
-    return string
+        Returns:
+          string: A string which contains what would be printed to the console if
+            the cursor moved right.
+        """
+        string = ESC_STRING
+        string += b"[" + str(count).encode("ascii") + b"C"
+        return string
 
-BACKSPACE_STRING = b''
+
+BACKSPACE_STRING = b""
 # Move cursor left 1 column.
 BACKSPACE_STRING += OutputStream.MoveCursorLeft(1)
 # Write a space.
-BACKSPACE_STRING += b' '
+BACKSPACE_STRING += b" "
 # Move cursor left 1 column.
 BACKSPACE_STRING += OutputStream.MoveCursorLeft(1)
 
-def BytesToByteList(string):
-  """Converts a bytes string to list of bytes.
-
-  Args:
-    string: A literal bytes to turn into a list of bytes.
 
-  Returns:
-    A list of integers representing the byte value of each character in the
-      string.
-  """
-  if six.PY3:
-    return [c for c in string]
-  return [ord(c) for c in string]
-
-def CheckConsoleOutput(test_case, exp_console_out):
-  """Verify what was sent out the console matches what we expect.
+def BytesToByteList(string):
+    """Converts a bytes string to list of bytes.
 
-  Args:
-    test_case: A unittest.TestCase object representing the current unit test.
-    exp_console_out: A string representing the console output stream.
-  """
-  # Read what was sent out the console.
-  test_case.tempfile.seek(0)
-  console_out = test_case.tempfile.read()
+    Args:
+      string: A literal bytes to turn into a list of bytes.
 
-  test_case.assertEqual(exp_console_out, console_out)
+    Returns:
+      A list of integers representing the byte value of each character in the
+        string.
+    """
+    if six.PY3:
+        return [c for c in string]
+    return [ord(c) for c in string]
 
-def CheckInputBuffer(test_case, exp_input_buffer):
-  """Verify that the input buffer contains what we expect.
-
-  Args:
-    test_case: A unittest.TestCase object representing the current unit test.
-    exp_input_buffer: A string containing the contents of the current input
-      buffer.
-  """
-  test_case.assertEqual(exp_input_buffer, test_case.console.input_buffer,
-                        (b'input buffer does not match expected.\n'
-                         b'expected: |' + exp_input_buffer + b'|\n'
-                         b'got:      |' + test_case.console.input_buffer +
-                         b'|\n' + str(test_case.console).encode('ascii')))
 
-def CheckInputBufferPosition(test_case, exp_pos):
-  """Verify the input buffer position.
+def CheckConsoleOutput(test_case, exp_console_out):
+    """Verify what was sent out the console matches what we expect.
 
-  Args:
-    test_case: A unittest.TestCase object representing the current unit test.
-    exp_pos: An integer representing the expected input buffer position.
-  """
-  test_case.assertEqual(exp_pos, test_case.console.input_buffer_pos,
-                        'input buffer position is incorrect.\ngot: ' +
-                        str(test_case.console.input_buffer_pos) + '\nexp: ' +
-                        str(exp_pos) + '\n' + str(test_case.console))
+    Args:
+      test_case: A unittest.TestCase object representing the current unit test.
+      exp_console_out: A string representing the console output stream.
+    """
+    # Read what was sent out the console.
+    test_case.tempfile.seek(0)
+    console_out = test_case.tempfile.read()
 
-def CheckHistoryBuffer(test_case, exp_history):
-  """Verify that the items in the history buffer are what we expect.
-
-  Args:
-    test_case: A unittest.TestCase object representing the current unit test.
-    exp_history: A list of strings representing the expected contents of the
-      history buffer.
-  """
-  # First, check to see if the length is what we expect.
-  test_case.assertEqual(len(exp_history), len(test_case.console.history),
-                        ('The number of items in the history is unexpected.\n'
-                         'exp: ' + str(len(exp_history)) + '\n'
-                         'got: ' + str(len(test_case.console.history)) + '\n'
-                         'internal state:\n' + str(test_case.console)))
-
-  # Next, check the actual contents of the history buffer.
-  for i in range(len(exp_history)):
-    test_case.assertEqual(exp_history[i], test_case.console.history[i],
-                          (b'history buffer contents are incorrect.\n'
-                           b'exp: ' + exp_history[i] + b'\n'
-                           b'got: ' + test_case.console.history[i] + b'\n'
-                           b'internal state:\n' +
-                           str(test_case.console).encode('ascii')))
+    test_case.assertEqual(exp_console_out, console_out)
 
 
-class TestConsoleEditingMethods(unittest.TestCase):
-  """Test case to verify all console editing methods."""
-
-  def setUp(self):
-    """Setup the test harness."""
-    # Setup logging with a timestamp, the module, and the log level.
-    logging.basicConfig(level=logging.DEBUG,
-                        format=('%(asctime)s - %(module)s -'
-                                ' %(levelname)s - %(message)s'))
-
-    # Create a temp file and set both the master and slave PTYs to the file to
-    # create a loopback.
-    self.tempfile = tempfile.TemporaryFile()
-
-    # Create some mock pipes. These won't be used since we'll mock out sends
-    # to the interpreter.
-    mock_pipe_end_0, mock_pipe_end_1 = threadproc_shim.Pipe()
-    self.console = console.Console(self.tempfile.fileno(), self.tempfile,
-                                   tempfile.TemporaryFile(),
-                                   mock_pipe_end_0, mock_pipe_end_1, "EC")
-
-    # Console editing methods are only valid for enhanced EC images, therefore
-    # we have to assume that the "EC" we're talking to is enhanced.  By default,
-    # the console believes that the EC it's communicating with is NOT enhanced
-    # which is why we have to override it here.
-    self.console.enhanced_ec = True
-    self.console.CheckForEnhancedECImage = mock.MagicMock(return_value=True)
-
-  def test_EnteringChars(self):
-    """Verify that characters are echoed onto the console."""
-    test_str = b'abc'
-    input_stream = BytesToByteList(test_str)
-
-    # Send the characters in.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Check the input position.
-    exp_pos = len(test_str)
-    CheckInputBufferPosition(self, exp_pos)
-
-    # Verify that the input buffer is correct.
-    expected_buffer = test_str
-    CheckInputBuffer(self, expected_buffer)
-
-    # Check console output
-    exp_console_out = test_str
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_EnteringDeletingMoreCharsThanEntered(self):
-    """Verify that we can press backspace more than we have entered chars."""
-    test_str = b'spamspam'
-    input_stream = BytesToByteList(test_str)
-
-    # Send the characters in.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Now backspace 1 more than what we sent.
-    input_stream = []
-    for _ in range(len(test_str) + 1):
-      input_stream.append(console.ControlKey.BACKSPACE)
-
-    # Send that sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # First, verify that input buffer position is 0.
-    CheckInputBufferPosition(self, 0)
-
-    # Next, examine the output stream for the correct sequence.
-    exp_console_out = test_str
-    for _ in range(len(test_str)):
-      exp_console_out += BACKSPACE_STRING
-
-    # Now, verify that we got what we expected.
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_EnteringMoreThanCharLimit(self):
-    """Verify that we drop characters when the line is too long."""
-    test_str = self.console.line_limit * b'o' # All allowed.
-    test_str += 5 * b'x' # All should be dropped.
-    input_stream = BytesToByteList(test_str)
-
-    # Send the characters in.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # First, we expect that input buffer position should be equal to the line
-    # limit.
-    exp_pos = self.console.line_limit
-    CheckInputBufferPosition(self, exp_pos)
-
-    # The input buffer should only hold until the line limit.
-    exp_buffer = test_str[0:self.console.line_limit]
-    CheckInputBuffer(self, exp_buffer)
-
-    # Lastly, check that the extra characters are not printed.
-    exp_console_out = exp_buffer
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_ValidKeysOnLongLine(self):
-    """Verify that we can still press valid keys if the line is too long."""
-    # Fill the line.
-    test_str = self.console.line_limit * b'o'
-    exp_console_out = test_str
-    # Try to fill it even more; these should all be dropped.
-    test_str += 5 * b'x'
-    input_stream = BytesToByteList(test_str)
-
-    # We should be able to press the following keys:
-    # - Backspace
-    # - Arrow Keys/CTRL+B/CTRL+F/CTRL+P/CTRL+N
-    # - Delete
-    # - Home/CTRL+A
-    # - End/CTRL+E
-    # - Carriage Return
-
-    # Backspace 1 character
-    input_stream.append(console.ControlKey.BACKSPACE)
-    exp_console_out += BACKSPACE_STRING
-    # Refill the line.
-    input_stream.extend(BytesToByteList(b'o'))
-    exp_console_out += b'o'
-
-    # Left arrow key.
-    input_stream.extend(Keys.LEFT_ARROW)
-    exp_console_out += OutputStream.MoveCursorLeft(1)
-
-    # Right arrow key.
-    input_stream.extend(Keys.RIGHT_ARROW)
-    exp_console_out += OutputStream.MoveCursorRight(1)
-
-    # CTRL+B
-    input_stream.append(console.ControlKey.CTRL_B)
-    exp_console_out += OutputStream.MoveCursorLeft(1)
-
-    # CTRL+F
-    input_stream.append(console.ControlKey.CTRL_F)
-    exp_console_out += OutputStream.MoveCursorRight(1)
-
-    # Let's press enter now so we can test up and down.
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-    exp_console_out += b'\r\n' + self.console.prompt
-
-    # Up arrow key.
-    input_stream.extend(Keys.UP_ARROW)
-    exp_console_out += test_str[:self.console.line_limit]
-
-    # Down arrow key.
-    input_stream.extend(Keys.DOWN_ARROW)
-    # Since the line was blank, we have to backspace the entire line.
-    exp_console_out += self.console.line_limit * BACKSPACE_STRING
-
-    # CTRL+P
-    input_stream.append(console.ControlKey.CTRL_P)
-    exp_console_out += test_str[:self.console.line_limit]
-
-    # CTRL+N
-    input_stream.append(console.ControlKey.CTRL_N)
-    # Since the line was blank, we have to backspace the entire line.
-    exp_console_out += self.console.line_limit * BACKSPACE_STRING
-
-    # Press the Up arrow key to reprint the long line.
-    input_stream.extend(Keys.UP_ARROW)
-    exp_console_out += test_str[:self.console.line_limit]
-
-    # Press the Home key to jump to the beginning of the line.
-    input_stream.extend(Keys.HOME)
-    exp_console_out += OutputStream.MoveCursorLeft(self.console.line_limit)
-
-    # Press the End key to jump to the end of the line.
-    input_stream.extend(Keys.END)
-    exp_console_out += OutputStream.MoveCursorRight(self.console.line_limit)
-
-    # Press CTRL+A to jump to the beginning of the line.
-    input_stream.append(console.ControlKey.CTRL_A)
-    exp_console_out += OutputStream.MoveCursorLeft(self.console.line_limit)
-
-    # Press CTRL+E to jump to the end of the line.
-    input_stream.extend(Keys.END)
-    exp_console_out += OutputStream.MoveCursorRight(self.console.line_limit)
-
-    # Move left one column so we can delete a character.
-    input_stream.extend(Keys.LEFT_ARROW)
-    exp_console_out += OutputStream.MoveCursorLeft(1)
-
-    # Press the delete key.
-    input_stream.extend(Keys.DEL)
-    # This should look like a space, and then move cursor left 1 column since
-    # we're at the end of line.
-    exp_console_out += b' ' + OutputStream.MoveCursorLeft(1)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Verify everything happened correctly.
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_BackspaceOnEmptyLine(self):
-    """Verify that we can backspace on an empty line with no bad effects."""
-    # Send a single backspace.
-    test_str = [console.ControlKey.BACKSPACE]
-
-    # Send the characters in.
-    for byte in test_str:
-      self.console.HandleChar(byte)
-
-    # Check the input position.
-    exp_pos = 0
-    CheckInputBufferPosition(self, exp_pos)
-
-    # Check that buffer is empty.
-    exp_input_buffer = b''
-    CheckInputBuffer(self, exp_input_buffer)
-
-    # Check that the console output is empty.
-    exp_console_out = b''
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_BackspaceWithinLine(self):
-    """Verify that we shift the chars over when backspacing within a line."""
-    # Misspell 'help'
-    test_str = b'heelp'
-    input_stream = BytesToByteList(test_str)
-    # Use the arrow key to go back to fix it.
-    # Move cursor left 1 column.
-    input_stream.extend(2*Keys.LEFT_ARROW)
-    # Backspace once to remove the extra 'e'.
-    input_stream.append(console.ControlKey.BACKSPACE)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Verify the input buffer
-    exp_input_buffer = b'help'
-    CheckInputBuffer(self, exp_input_buffer)
-
-    # Verify the input buffer position. It should be at 2 (cursor over the 'l')
-    CheckInputBufferPosition(self, 2)
-
-    # We expect the console output to be the test string, with two moves to the
-    # left, another move left, and then the rest of the line followed by a
-    # space.
-    exp_console_out = test_str
-    exp_console_out += 2 * OutputStream.MoveCursorLeft(1)
-
-    # Move cursor left 1 column.
-    exp_console_out += OutputStream.MoveCursorLeft(1)
-    # Rest of the line and a space. (test_str in this case)
-    exp_console_out += b'lp '
-    # Reset the cursor 2 + 1 to the left.
-    exp_console_out += OutputStream.MoveCursorLeft(3)
-
-    # Verify console output.
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_JumpToBeginningOfLineViaCtrlA(self):
-    """Verify that we can jump to the beginning of a line with Ctrl+A."""
-    # Enter some chars and press CTRL+A
-    test_str = b'abc'
-    input_stream = BytesToByteList(test_str) + [console.ControlKey.CTRL_A]
-
-    # Send the characters in.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # We expect to see our test string followed by a move cursor left.
-    exp_console_out = test_str
-    exp_console_out += OutputStream.MoveCursorLeft(len(test_str))
-
-    # Check to see what whas printed on the console.
-    CheckConsoleOutput(self, exp_console_out)
-
-    # Check that the input buffer position is now 0.
-    CheckInputBufferPosition(self, 0)
-
-    # Check input buffer still contains our test string.
-    CheckInputBuffer(self, test_str)
-
-  def test_JumpToBeginningOfLineViaHomeKey(self):
-    """Jump to beginning of line via HOME key."""
-    test_str = b'version'
-    input_stream = BytesToByteList(test_str)
-    input_stream.extend(Keys.HOME)
-
-    # Send out the stream.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # First, verify that input buffer position is now 0.
-    CheckInputBufferPosition(self, 0)
-
-    # Next, verify that the input buffer did not change.
-    CheckInputBuffer(self, test_str)
-
-    # Lastly, check that the cursor moved correctly.
-    exp_console_out = test_str
-    exp_console_out += OutputStream.MoveCursorLeft(len(test_str))
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_JumpToEndOfLineViaEndKey(self):
-    """Jump to the end of the line using the END key."""
-    test_str = b'version'
-    input_stream = BytesToByteList(test_str)
-    input_stream += [console.ControlKey.CTRL_A]
-    # Now, jump to the end of the line.
-    input_stream.extend(Keys.END)
-
-    # Send out the stream.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Verify that the input buffer position is correct.  This should be at the
-    # end of the test string.
-    CheckInputBufferPosition(self, len(test_str))
-
-    # The expected output should be the test string, followed by a jump to the
-    # beginning of the line, and lastly a jump to the end of the line.
-    exp_console_out = test_str
-    exp_console_out += OutputStream.MoveCursorLeft(len(test_str))
-    # Now the jump back to the end of the line.
-    exp_console_out += OutputStream.MoveCursorRight(len(test_str))
-
-    # Verify console output stream.
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_JumpToEndOfLineViaCtrlE(self):
-    """Enter some chars and then try to jump to the end. (Should be a no-op)"""
-    test_str = b'sysinfo'
-    input_stream = BytesToByteList(test_str)
-    input_stream.append(console.ControlKey.CTRL_E)
-
-    # Send out the stream
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Verify that the input buffer position isn't any further than we expect.
-    # At this point, the position should be at the end of the test string.
-    CheckInputBufferPosition(self, len(test_str))
-
-    # Now, let's try to jump to the beginning and then jump back to the end.
-    input_stream = [console.ControlKey.CTRL_A, console.ControlKey.CTRL_E]
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Perform the same verification.
-    CheckInputBufferPosition(self, len(test_str))
-
-    # Lastly try to jump again, beyond the end.
-    input_stream = [console.ControlKey.CTRL_E]
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Perform the same verification.
-    CheckInputBufferPosition(self, len(test_str))
-
-    # We expect to see the test string, a jump to the beginning of the line, and
-    # one jump to the end of the line.
-    exp_console_out = test_str
-    # Jump to beginning.
-    exp_console_out += OutputStream.MoveCursorLeft(len(test_str))
-    # Jump back to end.
-    exp_console_out += OutputStream.MoveCursorRight(len(test_str))
-
-    # Verify the console output.
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_MoveLeftWithArrowKey(self):
-    """Move cursor left one column with arrow key."""
-    test_str = b'tastyspam'
-    input_stream = BytesToByteList(test_str)
-    input_stream.extend(Keys.LEFT_ARROW)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Verify that the input buffer position is 1 less than the length.
-    CheckInputBufferPosition(self, len(test_str) - 1)
-
-    # Also, verify that the input buffer is not modified.
-    CheckInputBuffer(self, test_str)
-
-    # We expect the test string, followed by a one column move left.
-    exp_console_out = test_str + OutputStream.MoveCursorLeft(1)
-
-    # Verify console output.
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_MoveLeftWithCtrlB(self):
-    """Move cursor back one column with Ctrl+B."""
-    test_str = b'tastyspam'
-    input_stream = BytesToByteList(test_str)
-    input_stream.append(console.ControlKey.CTRL_B)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Verify that the input buffer position is 1 less than the length.
-    CheckInputBufferPosition(self, len(test_str) - 1)
+def CheckInputBuffer(test_case, exp_input_buffer):
+    """Verify that the input buffer contains what we expect.
 
-    # Also, verify that the input buffer is not modified.
-    CheckInputBuffer(self, test_str)
+    Args:
+      test_case: A unittest.TestCase object representing the current unit test.
+      exp_input_buffer: A string containing the contents of the current input
+        buffer.
+    """
+    test_case.assertEqual(
+        exp_input_buffer,
+        test_case.console.input_buffer,
+        (
+            b"input buffer does not match expected.\n"
+            b"expected: |" + exp_input_buffer + b"|\n"
+            b"got:      |"
+            + test_case.console.input_buffer
+            + b"|\n"
+            + str(test_case.console).encode("ascii")
+        ),
+    )
 
-    # We expect the test string, followed by a one column move left.
-    exp_console_out = test_str + OutputStream.MoveCursorLeft(1)
 
-    # Verify console output.
-    CheckConsoleOutput(self, exp_console_out)
+def CheckInputBufferPosition(test_case, exp_pos):
+    """Verify the input buffer position.
 
-  def test_MoveRightWithArrowKey(self):
-    """Move cursor one column to the right with the arrow key."""
-    test_str = b'version'
-    input_stream = BytesToByteList(test_str)
-    # Jump to beginning of line.
-    input_stream.append(console.ControlKey.CTRL_A)
-    # Press right arrow key.
-    input_stream.extend(Keys.RIGHT_ARROW)
+    Args:
+      test_case: A unittest.TestCase object representing the current unit test.
+      exp_pos: An integer representing the expected input buffer position.
+    """
+    test_case.assertEqual(
+        exp_pos,
+        test_case.console.input_buffer_pos,
+        "input buffer position is incorrect.\ngot: "
+        + str(test_case.console.input_buffer_pos)
+        + "\nexp: "
+        + str(exp_pos)
+        + "\n"
+        + str(test_case.console),
+    )
 
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
 
-    # Verify that the input buffer position is 1.
-    CheckInputBufferPosition(self, 1)
+def CheckHistoryBuffer(test_case, exp_history):
+    """Verify that the items in the history buffer are what we expect.
 
-    # Also, verify that the input buffer is not modified.
-    CheckInputBuffer(self, test_str)
+    Args:
+      test_case: A unittest.TestCase object representing the current unit test.
+      exp_history: A list of strings representing the expected contents of the
+        history buffer.
+    """
+    # First, check to see if the length is what we expect.
+    test_case.assertEqual(
+        len(exp_history),
+        len(test_case.console.history),
+        (
+            "The number of items in the history is unexpected.\n"
+            "exp: " + str(len(exp_history)) + "\n"
+            "got: " + str(len(test_case.console.history)) + "\n"
+            "internal state:\n" + str(test_case.console)
+        ),
+    )
+
+    # Next, check the actual contents of the history buffer.
+    for i in range(len(exp_history)):
+        test_case.assertEqual(
+            exp_history[i],
+            test_case.console.history[i],
+            (
+                b"history buffer contents are incorrect.\n"
+                b"exp: " + exp_history[i] + b"\n"
+                b"got: " + test_case.console.history[i] + b"\n"
+                b"internal state:\n" + str(test_case.console).encode("ascii")
+            ),
+        )
 
-    # We expect the test string, followed by a jump to the beginning of the
-    # line, and finally a move right 1.
-    exp_console_out = test_str + OutputStream.MoveCursorLeft(len((test_str)))
-
-    # A move right 1 column.
-    exp_console_out += OutputStream.MoveCursorRight(1)
-
-    # Verify console output.
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_MoveRightWithCtrlF(self):
-    """Move cursor forward one column with Ctrl+F."""
-    test_str = b'panicinfo'
-    input_stream = BytesToByteList(test_str)
-    input_stream.append(console.ControlKey.CTRL_A)
-    # Now, move right one column.
-    input_stream.append(console.ControlKey.CTRL_F)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Verify that the input buffer position is 1.
-    CheckInputBufferPosition(self, 1)
-
-    # Also, verify that the input buffer is not modified.
-    CheckInputBuffer(self, test_str)
-
-    # We expect the test string, followed by a jump to the beginning of the
-    # line, and finally a move right 1.
-    exp_console_out = test_str + OutputStream.MoveCursorLeft(len((test_str)))
-
-    # A move right 1 column.
-    exp_console_out += OutputStream.MoveCursorRight(1)
-
-    # Verify console output.
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_ImpossibleMoveLeftWithArrowKey(self):
-    """Verify that we can't move left at the beginning of the line."""
-    # We shouldn't be able to move left if we're at the beginning of the line.
-    input_stream = Keys.LEFT_ARROW
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Nothing should have been output.
-    exp_console_output = b''
-    CheckConsoleOutput(self, exp_console_output)
-
-    # The input buffer position should still be 0.
-    CheckInputBufferPosition(self, 0)
-
-    # The input buffer itself should be empty.
-    CheckInputBuffer(self, b'')
-
-  def test_ImpossibleMoveRightWithArrowKey(self):
-    """Verify that we can't move right at the end of the line."""
-    # We shouldn't be able to move right if we're at the end of the line.
-    input_stream = Keys.RIGHT_ARROW
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Nothing should have been output.
-    exp_console_output = b''
-    CheckConsoleOutput(self, exp_console_output)
-
-    # The input buffer position should still be 0.
-    CheckInputBufferPosition(self, 0)
-
-    # The input buffer itself should be empty.
-    CheckInputBuffer(self, b'')
-
-  def test_KillEntireLine(self):
-    """Verify that we can kill an entire line with Ctrl+K."""
-    test_str = b'accelinfo on'
-    input_stream = BytesToByteList(test_str)
-    # Jump to beginning of line and then kill it with Ctrl+K.
-    input_stream.extend([console.ControlKey.CTRL_A, console.ControlKey.CTRL_K])
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # First, we expect that the input buffer is empty.
-    CheckInputBuffer(self, b'')
-
-    # The buffer position should be 0.
-    CheckInputBufferPosition(self, 0)
-
-    # What we expect to see on the console stream should be the following.  The
-    # test string, a jump to the beginning of the line, then jump back to the
-    # end of the line and replace the line with spaces.
-    exp_console_out = test_str
-    # Jump to beginning of line.
-    exp_console_out += OutputStream.MoveCursorLeft(len(test_str))
-    # Jump to end of line.
-    exp_console_out += OutputStream.MoveCursorRight(len(test_str))
-    # Replace line with spaces, which looks like backspaces.
-    for _ in range(len(test_str)):
-      exp_console_out += BACKSPACE_STRING
-
-    # Verify the console output.
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_KillPartialLine(self):
-    """Verify that we can kill a portion of a line."""
-    test_str = b'accelread 0 1'
-    input_stream = BytesToByteList(test_str)
-    len_to_kill = 5
-    for _ in range(len_to_kill):
-      # Move cursor left
-      input_stream.extend(Keys.LEFT_ARROW)
-    # Now kill
-    input_stream.append(console.ControlKey.CTRL_K)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # First, check that the input buffer was truncated.
-    exp_input_buffer = test_str[:-len_to_kill]
-    CheckInputBuffer(self, exp_input_buffer)
-
-    # Verify the input buffer position.
-    CheckInputBufferPosition(self, len(test_str) - len_to_kill)
-
-    # The console output stream that we expect is the test string followed by a
-    # move left of len_to_kill, then a jump to the end of the line and backspace
-    # of len_to_kill.
-    exp_console_out = test_str
-    for _ in range(len_to_kill):
-      # Move left 1 column.
-      exp_console_out += OutputStream.MoveCursorLeft(1)
-    # Then jump to the end of the line
-    exp_console_out += OutputStream.MoveCursorRight(len_to_kill)
-    # Backspace of len_to_kill
-    for _ in range(len_to_kill):
-      exp_console_out += BACKSPACE_STRING
-
-    # Verify console output.
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_InsertingCharacters(self):
-    """Verify that we can insert characters within the line."""
-    test_str = b'accel 0 1' # Here we forgot the 'read' part in 'accelread'
-    input_stream = BytesToByteList(test_str)
-    # We need to move over to the 'l' and add read.
-    insertion_point = test_str.find(b'l') + 1
-    for i in range(len(test_str) - insertion_point):
-      # Move cursor left.
-      input_stream.extend(Keys.LEFT_ARROW)
-    # Now, add in 'read'
-    added_str = b'read'
-    input_stream.extend(BytesToByteList(added_str))
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # First, verify that the input buffer is correct.
-    exp_input_buffer = test_str[:insertion_point] + added_str
-    exp_input_buffer += test_str[insertion_point:]
-    CheckInputBuffer(self, exp_input_buffer)
-
-    # Verify that the input buffer position is correct.
-    exp_input_buffer_pos = insertion_point + len(added_str)
-    CheckInputBufferPosition(self, exp_input_buffer_pos)
-
-    # The console output stream that we expect is the test string, followed by
-    # move cursor left until the 'l' was found, the added test string while
-    # shifting characters around.
-    exp_console_out = test_str
-    for i in range(len(test_str) - insertion_point):
-      # Move cursor left.
-      exp_console_out += OutputStream.MoveCursorLeft(1)
-
-    # Now for each character, write the rest of the line will be shifted to the
-    # right one column.
-    for i in range(len(added_str)):
-      # Printed character.
-      exp_console_out += added_str[i:i+1]
-      # The rest of the line
-      exp_console_out += test_str[insertion_point:]
-      # Reset the cursor back left
-      reset_dist = len(test_str[insertion_point:])
-      exp_console_out += OutputStream.MoveCursorLeft(reset_dist)
-
-    # Verify the console output.
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_StoreCommandHistory(self):
-    """Verify that entered commands are stored in the history."""
-    test_commands = []
-    test_commands.append(b'help')
-    test_commands.append(b'version')
-    test_commands.append(b'accelread 0 1')
-    input_stream = []
-    for c in test_commands:
-      input_stream.extend(BytesToByteList(c))
-      input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # We expect to have the test commands in the history buffer.
-    exp_history_buf = test_commands
-    CheckHistoryBuffer(self, exp_history_buf)
-
-  def test_CycleUpThruCommandHistory(self):
-    """Verify that the UP arrow key will print itmes in the history buffer."""
-    # Enter some commands.
-    test_commands = [b'version', b'accelrange 0', b'battery', b'gettime']
-    input_stream = []
-    for command in test_commands:
-      input_stream.extend(BytesToByteList(command))
-      input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Now, hit the UP arrow key to print the previous entries.
-    for i in range(len(test_commands)):
-      input_stream.extend(Keys.UP_ARROW)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # The expected output should be test commands with prompts printed in
-    # between, followed by line kills with the previous test commands printed.
-    exp_console_out = b''
-    for i in range(len(test_commands)):
-      exp_console_out += test_commands[i] + b'\r\n' + self.console.prompt
-
-    # When we press up, the line should be cleared and print the previous buffer
-    # entry.
-    for i in range(len(test_commands)-1, 0, -1):
-      exp_console_out += test_commands[i]
-      # Backspace to the beginning.
-      for i in range(len(test_commands[i])):
-        exp_console_out += BACKSPACE_STRING
 
-    # The last command should just be printed out with no backspacing.
-    exp_console_out += test_commands[0]
-
-    # Now, verify.
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_UpArrowOnEmptyHistory(self):
-    """Ensure nothing happens if the history is empty."""
-    # Press the up arrow key twice.
-    input_stream = 2 * Keys.UP_ARROW
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # We expect nothing to have happened.
-    exp_console_out = b''
-    exp_input_buffer = b''
-    exp_input_buffer_pos = 0
-    exp_history_buf = []
-
-    # Verify.
-    CheckConsoleOutput(self, exp_console_out)
-    CheckInputBufferPosition(self, exp_input_buffer_pos)
-    CheckInputBuffer(self, exp_input_buffer)
-    CheckHistoryBuffer(self, exp_history_buf)
-
-  def test_UpArrowDoesNotGoOutOfBounds(self):
-    """Verify that pressing the up arrow many times won't go out of bounds."""
-    # Enter one command.
-    test_str = b'help version'
-    input_stream = BytesToByteList(test_str)
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-    # Then press the up arrow key twice.
-    input_stream.extend(2 * Keys.UP_ARROW)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Verify that the history buffer is correct.
-    exp_history_buf = [test_str]
-    CheckHistoryBuffer(self, exp_history_buf)
-
-    # We expect that the console output should only contain our entered command,
-    # a new prompt, and then our command aggain.
-    exp_console_out = test_str + b'\r\n' + self.console.prompt
-    # Pressing up should reprint the command we entered.
-    exp_console_out += test_str
-
-    # Verify.
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_CycleDownThruCommandHistory(self):
-    """Verify that we can select entries by hitting the down arrow."""
-    # Enter at least 4 commands.
-    test_commands = [b'version', b'accelrange 0', b'battery', b'gettime']
-    input_stream = []
-    for command in test_commands:
-      input_stream.extend(BytesToByteList(command))
-      input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Now, hit the UP arrow key twice to print the previous two entries.
-    for i in range(2):
-      input_stream.extend(Keys.UP_ARROW)
-
-    # Now, hit the DOWN arrow key twice to print the newer entries.
-    input_stream.extend(2*Keys.DOWN_ARROW)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # The expected output should be commands that we entered, followed by
-    # prompts, then followed by our last two commands in reverse.  Then, we
-    # should see the last entry in the list, followed by the saved partial cmd
-    # of a blank line.
-    exp_console_out = b''
-    for i in range(len(test_commands)):
-      exp_console_out += test_commands[i] + b'\r\n' + self.console.prompt
-
-    # When we press up, the line should be cleared and print the previous buffer
-    # entry.
-    for i in range(len(test_commands)-1, 1, -1):
-      exp_console_out += test_commands[i]
-      # Backspace to the beginning.
-      for i in range(len(test_commands[i])):
+class TestConsoleEditingMethods(unittest.TestCase):
+    """Test case to verify all console editing methods."""
+
+    def setUp(self):
+        """Setup the test harness."""
+        # Setup logging with a timestamp, the module, and the log level.
+        logging.basicConfig(
+            level=logging.DEBUG,
+            format=("%(asctime)s - %(module)s - %(levelname)s - %(message)s"),
+        )
+
+        # Create a temp file and set both the controller and peripheral PTYs to the
+        # file to create a loopback.
+        self.tempfile = tempfile.TemporaryFile()
+
+        # Create some mock pipes. These won't be used since we'll mock out sends
+        # to the interpreter.
+        mock_pipe_end_0, mock_pipe_end_1 = threadproc_shim.Pipe()
+        self.console = console.Console(
+            self.tempfile.fileno(),
+            self.tempfile,
+            tempfile.TemporaryFile(),
+            mock_pipe_end_0,
+            mock_pipe_end_1,
+            "EC",
+        )
+
+        # Console editing methods are only valid for enhanced EC images, therefore
+        # we have to assume that the "EC" we're talking to is enhanced.  By default,
+        # the console believes that the EC it's communicating with is NOT enhanced
+        # which is why we have to override it here.
+        self.console.enhanced_ec = True
+        self.console.CheckForEnhancedECImage = mock.MagicMock(return_value=True)
+
+    def test_EnteringChars(self):
+        """Verify that characters are echoed onto the console."""
+        test_str = b"abc"
+        input_stream = BytesToByteList(test_str)
+
+        # Send the characters in.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # Check the input position.
+        exp_pos = len(test_str)
+        CheckInputBufferPosition(self, exp_pos)
+
+        # Verify that the input buffer is correct.
+        expected_buffer = test_str
+        CheckInputBuffer(self, expected_buffer)
+
+        # Check console output
+        exp_console_out = test_str
+        CheckConsoleOutput(self, exp_console_out)
+
+    def test_EnteringDeletingMoreCharsThanEntered(self):
+        """Verify that we can press backspace more than we have entered chars."""
+        test_str = b"spamspam"
+        input_stream = BytesToByteList(test_str)
+
+        # Send the characters in.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # Now backspace 1 more than what we sent.
+        input_stream = []
+        for _ in range(len(test_str) + 1):
+            input_stream.append(console.ControlKey.BACKSPACE)
+
+        # Send that sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # First, verify that input buffer position is 0.
+        CheckInputBufferPosition(self, 0)
+
+        # Next, examine the output stream for the correct sequence.
+        exp_console_out = test_str
+        for _ in range(len(test_str)):
+            exp_console_out += BACKSPACE_STRING
+
+        # Now, verify that we got what we expected.
+        CheckConsoleOutput(self, exp_console_out)
+
+    def test_EnteringMoreThanCharLimit(self):
+        """Verify that we drop characters when the line is too long."""
+        test_str = self.console.line_limit * b"o"  # All allowed.
+        test_str += 5 * b"x"  # All should be dropped.
+        input_stream = BytesToByteList(test_str)
+
+        # Send the characters in.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # First, we expect that input buffer position should be equal to the line
+        # limit.
+        exp_pos = self.console.line_limit
+        CheckInputBufferPosition(self, exp_pos)
+
+        # The input buffer should only hold until the line limit.
+        exp_buffer = test_str[0 : self.console.line_limit]
+        CheckInputBuffer(self, exp_buffer)
+
+        # Lastly, check that the extra characters are not printed.
+        exp_console_out = exp_buffer
+        CheckConsoleOutput(self, exp_console_out)
+
+    def test_ValidKeysOnLongLine(self):
+        """Verify that we can still press valid keys if the line is too long."""
+        # Fill the line.
+        test_str = self.console.line_limit * b"o"
+        exp_console_out = test_str
+        # Try to fill it even more; these should all be dropped.
+        test_str += 5 * b"x"
+        input_stream = BytesToByteList(test_str)
+
+        # We should be able to press the following keys:
+        # - Backspace
+        # - Arrow Keys/CTRL+B/CTRL+F/CTRL+P/CTRL+N
+        # - Delete
+        # - Home/CTRL+A
+        # - End/CTRL+E
+        # - Carriage Return
+
+        # Backspace 1 character
+        input_stream.append(console.ControlKey.BACKSPACE)
         exp_console_out += BACKSPACE_STRING
+        # Refill the line.
+        input_stream.extend(BytesToByteList(b"o"))
+        exp_console_out += b"o"
+
+        # Left arrow key.
+        input_stream.extend(Keys.LEFT_ARROW)
+        exp_console_out += OutputStream.MoveCursorLeft(1)
+
+        # Right arrow key.
+        input_stream.extend(Keys.RIGHT_ARROW)
+        exp_console_out += OutputStream.MoveCursorRight(1)
+
+        # CTRL+B
+        input_stream.append(console.ControlKey.CTRL_B)
+        exp_console_out += OutputStream.MoveCursorLeft(1)
+
+        # CTRL+F
+        input_stream.append(console.ControlKey.CTRL_F)
+        exp_console_out += OutputStream.MoveCursorRight(1)
+
+        # Let's press enter now so we can test up and down.
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+        exp_console_out += b"\r\n" + self.console.prompt
+
+        # Up arrow key.
+        input_stream.extend(Keys.UP_ARROW)
+        exp_console_out += test_str[: self.console.line_limit]
+
+        # Down arrow key.
+        input_stream.extend(Keys.DOWN_ARROW)
+        # Since the line was blank, we have to backspace the entire line.
+        exp_console_out += self.console.line_limit * BACKSPACE_STRING
+
+        # CTRL+P
+        input_stream.append(console.ControlKey.CTRL_P)
+        exp_console_out += test_str[: self.console.line_limit]
+
+        # CTRL+N
+        input_stream.append(console.ControlKey.CTRL_N)
+        # Since the line was blank, we have to backspace the entire line.
+        exp_console_out += self.console.line_limit * BACKSPACE_STRING
+
+        # Press the Up arrow key to reprint the long line.
+        input_stream.extend(Keys.UP_ARROW)
+        exp_console_out += test_str[: self.console.line_limit]
+
+        # Press the Home key to jump to the beginning of the line.
+        input_stream.extend(Keys.HOME)
+        exp_console_out += OutputStream.MoveCursorLeft(self.console.line_limit)
+
+        # Press the End key to jump to the end of the line.
+        input_stream.extend(Keys.END)
+        exp_console_out += OutputStream.MoveCursorRight(self.console.line_limit)
+
+        # Press CTRL+A to jump to the beginning of the line.
+        input_stream.append(console.ControlKey.CTRL_A)
+        exp_console_out += OutputStream.MoveCursorLeft(self.console.line_limit)
+
+        # Press CTRL+E to jump to the end of the line.
+        input_stream.extend(Keys.END)
+        exp_console_out += OutputStream.MoveCursorRight(self.console.line_limit)
+
+        # Move left one column so we can delete a character.
+        input_stream.extend(Keys.LEFT_ARROW)
+        exp_console_out += OutputStream.MoveCursorLeft(1)
+
+        # Press the delete key.
+        input_stream.extend(Keys.DEL)
+        # This should look like a space, and then move cursor left 1 column since
+        # we're at the end of line.
+        exp_console_out += b" " + OutputStream.MoveCursorLeft(1)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # Verify everything happened correctly.
+        CheckConsoleOutput(self, exp_console_out)
+
+    def test_BackspaceOnEmptyLine(self):
+        """Verify that we can backspace on an empty line with no bad effects."""
+        # Send a single backspace.
+        test_str = [console.ControlKey.BACKSPACE]
+
+        # Send the characters in.
+        for byte in test_str:
+            self.console.HandleChar(byte)
+
+        # Check the input position.
+        exp_pos = 0
+        CheckInputBufferPosition(self, exp_pos)
+
+        # Check that buffer is empty.
+        exp_input_buffer = b""
+        CheckInputBuffer(self, exp_input_buffer)
+
+        # Check that the console output is empty.
+        exp_console_out = b""
+        CheckConsoleOutput(self, exp_console_out)
+
+    def test_BackspaceWithinLine(self):
+        """Verify that we shift the chars over when backspacing within a line."""
+        # Misspell 'help'
+        test_str = b"heelp"
+        input_stream = BytesToByteList(test_str)
+        # Use the arrow key to go back to fix it.
+        # Move cursor left 1 column.
+        input_stream.extend(2 * Keys.LEFT_ARROW)
+        # Backspace once to remove the extra 'e'.
+        input_stream.append(console.ControlKey.BACKSPACE)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # Verify the input buffer
+        exp_input_buffer = b"help"
+        CheckInputBuffer(self, exp_input_buffer)
+
+        # Verify the input buffer position. It should be at 2 (cursor over the 'l')
+        CheckInputBufferPosition(self, 2)
+
+        # We expect the console output to be the test string, with two moves to the
+        # left, another move left, and then the rest of the line followed by a
+        # space.
+        exp_console_out = test_str
+        exp_console_out += 2 * OutputStream.MoveCursorLeft(1)
+
+        # Move cursor left 1 column.
+        exp_console_out += OutputStream.MoveCursorLeft(1)
+        # Rest of the line and a space. (test_str in this case)
+        exp_console_out += b"lp "
+        # Reset the cursor 2 + 1 to the left.
+        exp_console_out += OutputStream.MoveCursorLeft(3)
+
+        # Verify console output.
+        CheckConsoleOutput(self, exp_console_out)
+
+    def test_JumpToBeginningOfLineViaCtrlA(self):
+        """Verify that we can jump to the beginning of a line with Ctrl+A."""
+        # Enter some chars and press CTRL+A
+        test_str = b"abc"
+        input_stream = BytesToByteList(test_str) + [console.ControlKey.CTRL_A]
+
+        # Send the characters in.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # We expect to see our test string followed by a move cursor left.
+        exp_console_out = test_str
+        exp_console_out += OutputStream.MoveCursorLeft(len(test_str))
+
+        # Check to see what whas printed on the console.
+        CheckConsoleOutput(self, exp_console_out)
+
+        # Check that the input buffer position is now 0.
+        CheckInputBufferPosition(self, 0)
+
+        # Check input buffer still contains our test string.
+        CheckInputBuffer(self, test_str)
+
+    def test_JumpToBeginningOfLineViaHomeKey(self):
+        """Jump to beginning of line via HOME key."""
+        test_str = b"version"
+        input_stream = BytesToByteList(test_str)
+        input_stream.extend(Keys.HOME)
+
+        # Send out the stream.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # First, verify that input buffer position is now 0.
+        CheckInputBufferPosition(self, 0)
+
+        # Next, verify that the input buffer did not change.
+        CheckInputBuffer(self, test_str)
+
+        # Lastly, check that the cursor moved correctly.
+        exp_console_out = test_str
+        exp_console_out += OutputStream.MoveCursorLeft(len(test_str))
+        CheckConsoleOutput(self, exp_console_out)
+
+    def test_JumpToEndOfLineViaEndKey(self):
+        """Jump to the end of the line using the END key."""
+        test_str = b"version"
+        input_stream = BytesToByteList(test_str)
+        input_stream += [console.ControlKey.CTRL_A]
+        # Now, jump to the end of the line.
+        input_stream.extend(Keys.END)
+
+        # Send out the stream.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # Verify that the input buffer position is correct.  This should be at the
+        # end of the test string.
+        CheckInputBufferPosition(self, len(test_str))
+
+        # The expected output should be the test string, followed by a jump to the
+        # beginning of the line, and lastly a jump to the end of the line.
+        exp_console_out = test_str
+        exp_console_out += OutputStream.MoveCursorLeft(len(test_str))
+        # Now the jump back to the end of the line.
+        exp_console_out += OutputStream.MoveCursorRight(len(test_str))
+
+        # Verify console output stream.
+        CheckConsoleOutput(self, exp_console_out)
+
+    def test_JumpToEndOfLineViaCtrlE(self):
+        """Enter some chars and then try to jump to the end. (Should be a no-op)"""
+        test_str = b"sysinfo"
+        input_stream = BytesToByteList(test_str)
+        input_stream.append(console.ControlKey.CTRL_E)
+
+        # Send out the stream
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # Verify that the input buffer position isn't any further than we expect.
+        # At this point, the position should be at the end of the test string.
+        CheckInputBufferPosition(self, len(test_str))
+
+        # Now, let's try to jump to the beginning and then jump back to the end.
+        input_stream = [console.ControlKey.CTRL_A, console.ControlKey.CTRL_E]
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # Perform the same verification.
+        CheckInputBufferPosition(self, len(test_str))
+
+        # Lastly try to jump again, beyond the end.
+        input_stream = [console.ControlKey.CTRL_E]
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # Perform the same verification.
+        CheckInputBufferPosition(self, len(test_str))
+
+        # We expect to see the test string, a jump to the beginning of the line, and
+        # one jump to the end of the line.
+        exp_console_out = test_str
+        # Jump to beginning.
+        exp_console_out += OutputStream.MoveCursorLeft(len(test_str))
+        # Jump back to end.
+        exp_console_out += OutputStream.MoveCursorRight(len(test_str))
+
+        # Verify the console output.
+        CheckConsoleOutput(self, exp_console_out)
+
+    def test_MoveLeftWithArrowKey(self):
+        """Move cursor left one column with arrow key."""
+        test_str = b"tastyspam"
+        input_stream = BytesToByteList(test_str)
+        input_stream.extend(Keys.LEFT_ARROW)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # Verify that the input buffer position is 1 less than the length.
+        CheckInputBufferPosition(self, len(test_str) - 1)
+
+        # Also, verify that the input buffer is not modified.
+        CheckInputBuffer(self, test_str)
+
+        # We expect the test string, followed by a one column move left.
+        exp_console_out = test_str + OutputStream.MoveCursorLeft(1)
+
+        # Verify console output.
+        CheckConsoleOutput(self, exp_console_out)
+
+    def test_MoveLeftWithCtrlB(self):
+        """Move cursor back one column with Ctrl+B."""
+        test_str = b"tastyspam"
+        input_stream = BytesToByteList(test_str)
+        input_stream.append(console.ControlKey.CTRL_B)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # Verify that the input buffer position is 1 less than the length.
+        CheckInputBufferPosition(self, len(test_str) - 1)
+
+        # Also, verify that the input buffer is not modified.
+        CheckInputBuffer(self, test_str)
+
+        # We expect the test string, followed by a one column move left.
+        exp_console_out = test_str + OutputStream.MoveCursorLeft(1)
 
-    # When we press down, it should have cleared the last command (which we
-    # covered with the previous for loop), and then prints the next command.
-    exp_console_out += test_commands[3]
-    for i in range(len(test_commands[3])):
-      exp_console_out += BACKSPACE_STRING
-
-    # Verify console output.
-    CheckConsoleOutput(self, exp_console_out)
-
-    # Verify input buffer.
-    exp_input_buffer = b'' # Empty because our partial command was empty.
-    exp_input_buffer_pos = len(exp_input_buffer)
-    CheckInputBuffer(self, exp_input_buffer)
-    CheckInputBufferPosition(self, exp_input_buffer_pos)
-
-  def test_SavingPartialCommandWhenNavigatingHistory(self):
-    """Verify that partial commands are saved when navigating history."""
-    # Enter a command.
-    test_str = b'accelinfo'
-    input_stream = BytesToByteList(test_str)
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Enter a partial command.
-    partial_cmd = b'ver'
-    input_stream.extend(BytesToByteList(partial_cmd))
-
-    # Hit the UP arrow key.
-    input_stream.extend(Keys.UP_ARROW)
-    # Then, the DOWN arrow key.
-    input_stream.extend(Keys.DOWN_ARROW)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # The expected output should be the command we entered, a prompt, the
-    # partial command, clearing of the partial command, the command entered,
-    # clearing of the command entered, and then the partial command.
-    exp_console_out = test_str + b'\r\n' + self.console.prompt
-    exp_console_out += partial_cmd
-    for _ in range(len(partial_cmd)):
-      exp_console_out += BACKSPACE_STRING
-    exp_console_out += test_str
-    for _ in range(len(test_str)):
-      exp_console_out += BACKSPACE_STRING
-    exp_console_out += partial_cmd
-
-    # Verify console output.
-    CheckConsoleOutput(self, exp_console_out)
-
-    # Verify input buffer.
-    exp_input_buffer = partial_cmd
-    exp_input_buffer_pos = len(exp_input_buffer)
-    CheckInputBuffer(self, exp_input_buffer)
-    CheckInputBufferPosition(self, exp_input_buffer_pos)
-
-  def test_DownArrowOnEmptyHistory(self):
-    """Ensure nothing happens if the history is empty."""
-    # Then press the up down arrow twice.
-    input_stream = 2 * Keys.DOWN_ARROW
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # We expect nothing to have happened.
-    exp_console_out = b''
-    exp_input_buffer = b''
-    exp_input_buffer_pos = 0
-    exp_history_buf = []
-
-    # Verify.
-    CheckConsoleOutput(self, exp_console_out)
-    CheckInputBufferPosition(self, exp_input_buffer_pos)
-    CheckInputBuffer(self, exp_input_buffer)
-    CheckHistoryBuffer(self, exp_history_buf)
-
-  def test_DeleteCharsUsingDELKey(self):
-    """Verify that we can delete characters using the DEL key."""
-    test_str = b'version'
-    input_stream = BytesToByteList(test_str)
-
-    # Hit the left arrow key 2 times.
-    input_stream.extend(2 * Keys.LEFT_ARROW)
-
-    # Press the DEL key.
-    input_stream.extend(Keys.DEL)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # The expected output should be the command we entered, 2 individual cursor
-    # moves to the left, and then removing a char and shifting everything to the
-    # left one column.
-    exp_console_out = test_str
-    exp_console_out += 2 * OutputStream.MoveCursorLeft(1)
-
-    # Remove the char by shifting everything to the left one, slicing out the
-    # remove char.
-    exp_console_out += test_str[-1:] + b' '
-
-    # Reset the cursor by moving back 2 columns because of the 'n' and space.
-    exp_console_out += OutputStream.MoveCursorLeft(2)
-
-    # Verify console output.
-    CheckConsoleOutput(self, exp_console_out)
-
-    # Verify input buffer.  The input buffer should have the char sliced out and
-    # be positioned where the char was removed.
-    exp_input_buffer = test_str[:-2] + test_str[-1:]
-    exp_input_buffer_pos = len(exp_input_buffer) - 1
-    CheckInputBuffer(self, exp_input_buffer)
-    CheckInputBufferPosition(self, exp_input_buffer_pos)
-
-  def test_RepeatedCommandInHistory(self):
-    """Verify that we don't store 2 consecutive identical commands in history"""
-    # Enter a few commands.
-    test_commands = [b'version', b'accelrange 0', b'battery', b'gettime']
-    # Repeat the last command.
-    test_commands.append(test_commands[len(test_commands)-1])
-
-    input_stream = []
-    for command in test_commands:
-      input_stream.extend(BytesToByteList(command))
-      input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Verify that the history buffer is correct.  The last command, since
-    # it was repeated, should not have been added to the history.
-    exp_history_buf = test_commands[0:len(test_commands)-1]
-    CheckHistoryBuffer(self, exp_history_buf)
+        # Verify console output.
+        CheckConsoleOutput(self, exp_console_out)
 
+    def test_MoveRightWithArrowKey(self):
+        """Move cursor one column to the right with the arrow key."""
+        test_str = b"version"
+        input_stream = BytesToByteList(test_str)
+        # Jump to beginning of line.
+        input_stream.append(console.ControlKey.CTRL_A)
+        # Press right arrow key.
+        input_stream.extend(Keys.RIGHT_ARROW)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # Verify that the input buffer position is 1.
+        CheckInputBufferPosition(self, 1)
 
-class TestConsoleCompatibility(unittest.TestCase):
-  """Verify that console can speak to enhanced and non-enhanced EC images."""
-  def setUp(self):
-    """Setup the test harness."""
-    # Setup logging with a timestamp, the module, and the log level.
-    logging.basicConfig(level=logging.DEBUG,
-                        format=('%(asctime)s - %(module)s -'
-                                ' %(levelname)s - %(message)s'))
-    # Create a temp file and set both the master and slave PTYs to the file to
-    # create a loopback.
-    self.tempfile = tempfile.TemporaryFile()
-
-    # Mock out the pipes.
-    mock_pipe_end_0, mock_pipe_end_1 = mock.MagicMock(), mock.MagicMock()
-    self.console = console.Console(self.tempfile.fileno(), self.tempfile,
-                                   tempfile.TemporaryFile(),
-                                   mock_pipe_end_0, mock_pipe_end_1, "EC")
-
-  @mock.patch('console.Console.CheckForEnhancedECImage')
-  def test_ActAsPassThruInNonEnhancedMode(self, mock_check):
-    """Verify we simply pass everything thru to non-enhanced ECs.
+        # Also, verify that the input buffer is not modified.
+        CheckInputBuffer(self, test_str)
 
-    Args:
-      mock_check: A MagicMock object replacing the CheckForEnhancedECImage()
-        method.
-    """
-    # Set the interrogation mode to always so that we actually interrogate.
-    self.console.interrogation_mode = b'always'
-
-    # Assume EC interrogations indicate that the image is non-enhanced.
-    mock_check.return_value = False
-
-    # Press enter, followed by the command, and another enter.
-    input_stream = []
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-    test_command = b'version'
-    input_stream.extend(BytesToByteList(test_command))
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Expected calls to send down the pipe would be each character of the test
-    # command.
-    expected_calls = []
-    expected_calls.append(mock.call(
-        six.int2byte(console.ControlKey.CARRIAGE_RETURN)))
-    for char in test_command:
-      if six.PY3:
-        expected_calls.append(mock.call(bytes([char])))
-      else:
-        expected_calls.append(mock.call(char))
-    expected_calls.append(mock.call(
-        six.int2byte(console.ControlKey.CARRIAGE_RETURN)))
-
-    # Verify that the calls happened.
-    self.console.cmd_pipe.send.assert_has_calls(expected_calls)
-
-    # Since we're acting as a pass-thru, the input buffer should be empty and
-    # input_buffer_pos is 0.
-    CheckInputBuffer(self, b'')
-    CheckInputBufferPosition(self, 0)
-
-  @mock.patch('console.Console.CheckForEnhancedECImage')
-  def test_TransitionFromNonEnhancedToEnhanced(self, mock_check):
-    """Verify that we transition correctly to enhanced mode.
+        # We expect the test string, followed by a jump to the beginning of the
+        # line, and finally a move right 1.
+        exp_console_out = test_str + OutputStream.MoveCursorLeft(
+            len((test_str))
+        )
+
+        # A move right 1 column.
+        exp_console_out += OutputStream.MoveCursorRight(1)
+
+        # Verify console output.
+        CheckConsoleOutput(self, exp_console_out)
+
+    def test_MoveRightWithCtrlF(self):
+        """Move cursor forward one column with Ctrl+F."""
+        test_str = b"panicinfo"
+        input_stream = BytesToByteList(test_str)
+        input_stream.append(console.ControlKey.CTRL_A)
+        # Now, move right one column.
+        input_stream.append(console.ControlKey.CTRL_F)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # Verify that the input buffer position is 1.
+        CheckInputBufferPosition(self, 1)
+
+        # Also, verify that the input buffer is not modified.
+        CheckInputBuffer(self, test_str)
+
+        # We expect the test string, followed by a jump to the beginning of the
+        # line, and finally a move right 1.
+        exp_console_out = test_str + OutputStream.MoveCursorLeft(
+            len((test_str))
+        )
+
+        # A move right 1 column.
+        exp_console_out += OutputStream.MoveCursorRight(1)
+
+        # Verify console output.
+        CheckConsoleOutput(self, exp_console_out)
+
+    def test_ImpossibleMoveLeftWithArrowKey(self):
+        """Verify that we can't move left at the beginning of the line."""
+        # We shouldn't be able to move left if we're at the beginning of the line.
+        input_stream = Keys.LEFT_ARROW
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # Nothing should have been output.
+        exp_console_output = b""
+        CheckConsoleOutput(self, exp_console_output)
+
+        # The input buffer position should still be 0.
+        CheckInputBufferPosition(self, 0)
+
+        # The input buffer itself should be empty.
+        CheckInputBuffer(self, b"")
+
+    def test_ImpossibleMoveRightWithArrowKey(self):
+        """Verify that we can't move right at the end of the line."""
+        # We shouldn't be able to move right if we're at the end of the line.
+        input_stream = Keys.RIGHT_ARROW
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # Nothing should have been output.
+        exp_console_output = b""
+        CheckConsoleOutput(self, exp_console_output)
+
+        # The input buffer position should still be 0.
+        CheckInputBufferPosition(self, 0)
+
+        # The input buffer itself should be empty.
+        CheckInputBuffer(self, b"")
+
+    def test_KillEntireLine(self):
+        """Verify that we can kill an entire line with Ctrl+K."""
+        test_str = b"accelinfo on"
+        input_stream = BytesToByteList(test_str)
+        # Jump to beginning of line and then kill it with Ctrl+K.
+        input_stream.extend(
+            [console.ControlKey.CTRL_A, console.ControlKey.CTRL_K]
+        )
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # First, we expect that the input buffer is empty.
+        CheckInputBuffer(self, b"")
+
+        # The buffer position should be 0.
+        CheckInputBufferPosition(self, 0)
+
+        # What we expect to see on the console stream should be the following.  The
+        # test string, a jump to the beginning of the line, then jump back to the
+        # end of the line and replace the line with spaces.
+        exp_console_out = test_str
+        # Jump to beginning of line.
+        exp_console_out += OutputStream.MoveCursorLeft(len(test_str))
+        # Jump to end of line.
+        exp_console_out += OutputStream.MoveCursorRight(len(test_str))
+        # Replace line with spaces, which looks like backspaces.
+        for _ in range(len(test_str)):
+            exp_console_out += BACKSPACE_STRING
+
+        # Verify the console output.
+        CheckConsoleOutput(self, exp_console_out)
+
+    def test_KillPartialLine(self):
+        """Verify that we can kill a portion of a line."""
+        test_str = b"accelread 0 1"
+        input_stream = BytesToByteList(test_str)
+        len_to_kill = 5
+        for _ in range(len_to_kill):
+            # Move cursor left
+            input_stream.extend(Keys.LEFT_ARROW)
+        # Now kill
+        input_stream.append(console.ControlKey.CTRL_K)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # First, check that the input buffer was truncated.
+        exp_input_buffer = test_str[:-len_to_kill]
+        CheckInputBuffer(self, exp_input_buffer)
+
+        # Verify the input buffer position.
+        CheckInputBufferPosition(self, len(test_str) - len_to_kill)
+
+        # The console output stream that we expect is the test string followed by a
+        # move left of len_to_kill, then a jump to the end of the line and backspace
+        # of len_to_kill.
+        exp_console_out = test_str
+        for _ in range(len_to_kill):
+            # Move left 1 column.
+            exp_console_out += OutputStream.MoveCursorLeft(1)
+        # Then jump to the end of the line
+        exp_console_out += OutputStream.MoveCursorRight(len_to_kill)
+        # Backspace of len_to_kill
+        for _ in range(len_to_kill):
+            exp_console_out += BACKSPACE_STRING
+
+        # Verify console output.
+        CheckConsoleOutput(self, exp_console_out)
+
+    def test_InsertingCharacters(self):
+        """Verify that we can insert characters within the line."""
+        test_str = b"accel 0 1"  # Here we forgot the 'read' part in 'accelread'
+        input_stream = BytesToByteList(test_str)
+        # We need to move over to the 'l' and add read.
+        insertion_point = test_str.find(b"l") + 1
+        for i in range(len(test_str) - insertion_point):
+            # Move cursor left.
+            input_stream.extend(Keys.LEFT_ARROW)
+        # Now, add in 'read'
+        added_str = b"read"
+        input_stream.extend(BytesToByteList(added_str))
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # First, verify that the input buffer is correct.
+        exp_input_buffer = test_str[:insertion_point] + added_str
+        exp_input_buffer += test_str[insertion_point:]
+        CheckInputBuffer(self, exp_input_buffer)
+
+        # Verify that the input buffer position is correct.
+        exp_input_buffer_pos = insertion_point + len(added_str)
+        CheckInputBufferPosition(self, exp_input_buffer_pos)
+
+        # The console output stream that we expect is the test string, followed by
+        # move cursor left until the 'l' was found, the added test string while
+        # shifting characters around.
+        exp_console_out = test_str
+        for i in range(len(test_str) - insertion_point):
+            # Move cursor left.
+            exp_console_out += OutputStream.MoveCursorLeft(1)
+
+        # Now for each character, write the rest of the line will be shifted to the
+        # right one column.
+        for i in range(len(added_str)):
+            # Printed character.
+            exp_console_out += added_str[i : i + 1]
+            # The rest of the line
+            exp_console_out += test_str[insertion_point:]
+            # Reset the cursor back left
+            reset_dist = len(test_str[insertion_point:])
+            exp_console_out += OutputStream.MoveCursorLeft(reset_dist)
+
+        # Verify the console output.
+        CheckConsoleOutput(self, exp_console_out)
+
+    def test_StoreCommandHistory(self):
+        """Verify that entered commands are stored in the history."""
+        test_commands = []
+        test_commands.append(b"help")
+        test_commands.append(b"version")
+        test_commands.append(b"accelread 0 1")
+        input_stream = []
+        for c in test_commands:
+            input_stream.extend(BytesToByteList(c))
+            input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # We expect to have the test commands in the history buffer.
+        exp_history_buf = test_commands
+        CheckHistoryBuffer(self, exp_history_buf)
+
+    def test_CycleUpThruCommandHistory(self):
+        """Verify that the UP arrow key will print itmes in the history buffer."""
+        # Enter some commands.
+        test_commands = [b"version", b"accelrange 0", b"battery", b"gettime"]
+        input_stream = []
+        for command in test_commands:
+            input_stream.extend(BytesToByteList(command))
+            input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+
+        # Now, hit the UP arrow key to print the previous entries.
+        for i in range(len(test_commands)):
+            input_stream.extend(Keys.UP_ARROW)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # The expected output should be test commands with prompts printed in
+        # between, followed by line kills with the previous test commands printed.
+        exp_console_out = b""
+        for i in range(len(test_commands)):
+            exp_console_out += test_commands[i] + b"\r\n" + self.console.prompt
+
+        # When we press up, the line should be cleared and print the previous buffer
+        # entry.
+        for i in range(len(test_commands) - 1, 0, -1):
+            exp_console_out += test_commands[i]
+            # Backspace to the beginning.
+            for i in range(len(test_commands[i])):
+                exp_console_out += BACKSPACE_STRING
+
+        # The last command should just be printed out with no backspacing.
+        exp_console_out += test_commands[0]
+
+        # Now, verify.
+        CheckConsoleOutput(self, exp_console_out)
+
+    def test_UpArrowOnEmptyHistory(self):
+        """Ensure nothing happens if the history is empty."""
+        # Press the up arrow key twice.
+        input_stream = 2 * Keys.UP_ARROW
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # We expect nothing to have happened.
+        exp_console_out = b""
+        exp_input_buffer = b""
+        exp_input_buffer_pos = 0
+        exp_history_buf = []
+
+        # Verify.
+        CheckConsoleOutput(self, exp_console_out)
+        CheckInputBufferPosition(self, exp_input_buffer_pos)
+        CheckInputBuffer(self, exp_input_buffer)
+        CheckHistoryBuffer(self, exp_history_buf)
+
+    def test_UpArrowDoesNotGoOutOfBounds(self):
+        """Verify that pressing the up arrow many times won't go out of bounds."""
+        # Enter one command.
+        test_str = b"help version"
+        input_stream = BytesToByteList(test_str)
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+        # Then press the up arrow key twice.
+        input_stream.extend(2 * Keys.UP_ARROW)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # Verify that the history buffer is correct.
+        exp_history_buf = [test_str]
+        CheckHistoryBuffer(self, exp_history_buf)
+
+        # We expect that the console output should only contain our entered command,
+        # a new prompt, and then our command aggain.
+        exp_console_out = test_str + b"\r\n" + self.console.prompt
+        # Pressing up should reprint the command we entered.
+        exp_console_out += test_str
+
+        # Verify.
+        CheckConsoleOutput(self, exp_console_out)
+
+    def test_CycleDownThruCommandHistory(self):
+        """Verify that we can select entries by hitting the down arrow."""
+        # Enter at least 4 commands.
+        test_commands = [b"version", b"accelrange 0", b"battery", b"gettime"]
+        input_stream = []
+        for command in test_commands:
+            input_stream.extend(BytesToByteList(command))
+            input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+
+        # Now, hit the UP arrow key twice to print the previous two entries.
+        for i in range(2):
+            input_stream.extend(Keys.UP_ARROW)
+
+        # Now, hit the DOWN arrow key twice to print the newer entries.
+        input_stream.extend(2 * Keys.DOWN_ARROW)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # The expected output should be commands that we entered, followed by
+        # prompts, then followed by our last two commands in reverse.  Then, we
+        # should see the last entry in the list, followed by the saved partial cmd
+        # of a blank line.
+        exp_console_out = b""
+        for i in range(len(test_commands)):
+            exp_console_out += test_commands[i] + b"\r\n" + self.console.prompt
+
+        # When we press up, the line should be cleared and print the previous buffer
+        # entry.
+        for i in range(len(test_commands) - 1, 1, -1):
+            exp_console_out += test_commands[i]
+            # Backspace to the beginning.
+            for i in range(len(test_commands[i])):
+                exp_console_out += BACKSPACE_STRING
+
+        # When we press down, it should have cleared the last command (which we
+        # covered with the previous for loop), and then prints the next command.
+        exp_console_out += test_commands[3]
+        for i in range(len(test_commands[3])):
+            exp_console_out += BACKSPACE_STRING
+
+        # Verify console output.
+        CheckConsoleOutput(self, exp_console_out)
+
+        # Verify input buffer.
+        exp_input_buffer = b""  # Empty because our partial command was empty.
+        exp_input_buffer_pos = len(exp_input_buffer)
+        CheckInputBuffer(self, exp_input_buffer)
+        CheckInputBufferPosition(self, exp_input_buffer_pos)
+
+    def test_SavingPartialCommandWhenNavigatingHistory(self):
+        """Verify that partial commands are saved when navigating history."""
+        # Enter a command.
+        test_str = b"accelinfo"
+        input_stream = BytesToByteList(test_str)
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+
+        # Enter a partial command.
+        partial_cmd = b"ver"
+        input_stream.extend(BytesToByteList(partial_cmd))
+
+        # Hit the UP arrow key.
+        input_stream.extend(Keys.UP_ARROW)
+        # Then, the DOWN arrow key.
+        input_stream.extend(Keys.DOWN_ARROW)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # The expected output should be the command we entered, a prompt, the
+        # partial command, clearing of the partial command, the command entered,
+        # clearing of the command entered, and then the partial command.
+        exp_console_out = test_str + b"\r\n" + self.console.prompt
+        exp_console_out += partial_cmd
+        for _ in range(len(partial_cmd)):
+            exp_console_out += BACKSPACE_STRING
+        exp_console_out += test_str
+        for _ in range(len(test_str)):
+            exp_console_out += BACKSPACE_STRING
+        exp_console_out += partial_cmd
+
+        # Verify console output.
+        CheckConsoleOutput(self, exp_console_out)
+
+        # Verify input buffer.
+        exp_input_buffer = partial_cmd
+        exp_input_buffer_pos = len(exp_input_buffer)
+        CheckInputBuffer(self, exp_input_buffer)
+        CheckInputBufferPosition(self, exp_input_buffer_pos)
+
+    def test_DownArrowOnEmptyHistory(self):
+        """Ensure nothing happens if the history is empty."""
+        # Then press the up down arrow twice.
+        input_stream = 2 * Keys.DOWN_ARROW
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # We expect nothing to have happened.
+        exp_console_out = b""
+        exp_input_buffer = b""
+        exp_input_buffer_pos = 0
+        exp_history_buf = []
+
+        # Verify.
+        CheckConsoleOutput(self, exp_console_out)
+        CheckInputBufferPosition(self, exp_input_buffer_pos)
+        CheckInputBuffer(self, exp_input_buffer)
+        CheckHistoryBuffer(self, exp_history_buf)
+
+    def test_DeleteCharsUsingDELKey(self):
+        """Verify that we can delete characters using the DEL key."""
+        test_str = b"version"
+        input_stream = BytesToByteList(test_str)
+
+        # Hit the left arrow key 2 times.
+        input_stream.extend(2 * Keys.LEFT_ARROW)
+
+        # Press the DEL key.
+        input_stream.extend(Keys.DEL)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # The expected output should be the command we entered, 2 individual cursor
+        # moves to the left, and then removing a char and shifting everything to the
+        # left one column.
+        exp_console_out = test_str
+        exp_console_out += 2 * OutputStream.MoveCursorLeft(1)
+
+        # Remove the char by shifting everything to the left one, slicing out the
+        # remove char.
+        exp_console_out += test_str[-1:] + b" "
+
+        # Reset the cursor by moving back 2 columns because of the 'n' and space.
+        exp_console_out += OutputStream.MoveCursorLeft(2)
+
+        # Verify console output.
+        CheckConsoleOutput(self, exp_console_out)
+
+        # Verify input buffer.  The input buffer should have the char sliced out and
+        # be positioned where the char was removed.
+        exp_input_buffer = test_str[:-2] + test_str[-1:]
+        exp_input_buffer_pos = len(exp_input_buffer) - 1
+        CheckInputBuffer(self, exp_input_buffer)
+        CheckInputBufferPosition(self, exp_input_buffer_pos)
+
+    def test_RepeatedCommandInHistory(self):
+        """Verify that we don't store 2 consecutive identical commands in history"""
+        # Enter a few commands.
+        test_commands = [b"version", b"accelrange 0", b"battery", b"gettime"]
+        # Repeat the last command.
+        test_commands.append(test_commands[len(test_commands) - 1])
+
+        input_stream = []
+        for command in test_commands:
+            input_stream.extend(BytesToByteList(command))
+            input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # Verify that the history buffer is correct.  The last command, since
+        # it was repeated, should not have been added to the history.
+        exp_history_buf = test_commands[0 : len(test_commands) - 1]
+        CheckHistoryBuffer(self, exp_history_buf)
 
-    Args:
-      mock_check: A MagicMock object replacing the CheckForEnhancedECImage()
-        method.
-    """
-    # Set the interrogation mode to always so that we actually interrogate.
-    self.console.interrogation_mode = b'always'
-
-    # First, assume that the EC interrogations indicate an enhanced EC image.
-    mock_check.return_value = True
-    # But our current knowledge of the EC image (which was actually the
-    # 'previous' EC) was a non-enhanced image.
-    self.console.enhanced_ec = False
-
-    test_command = b'sysinfo'
-    input_stream = []
-    input_stream.extend(BytesToByteList(test_command))
-
-    expected_calls = []
-    # All keystrokes to the console should be directed straight through to the
-    # EC until we press the enter key.
-    for char in test_command:
-      if six.PY3:
-        expected_calls.append(mock.call(bytes([char])))
-      else:
-        expected_calls.append(mock.call(char))
-
-    # Press the enter key.
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-    # The enter key should not be sent to the pipe since we should negotiate
-    # to an enhanced EC image.
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # At this point, we should have negotiated to enhanced.
-    self.assertTrue(self.console.enhanced_ec, msg=('Did not negotiate to '
-                                                   'enhanced EC image.'))
-
-    # The command would have been dropped however, so verify this...
-    CheckInputBuffer(self, b'')
-    CheckInputBufferPosition(self, 0)
-    # ...and repeat the command.
-    input_stream = BytesToByteList(test_command)
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Since we're enhanced now, we should have sent the entire command as one
-    # string with no trailing carriage return
-    expected_calls.append(mock.call(test_command))
-
-    # Verify all of the calls.
-    self.console.cmd_pipe.send.assert_has_calls(expected_calls)
-
-  @mock.patch('console.Console.CheckForEnhancedECImage')
-  def test_TransitionFromEnhancedToNonEnhanced(self, mock_check):
-    """Verify that we transition correctly to non-enhanced mode.
 
-    Args:
-      mock_check: A MagicMock object replacing the CheckForEnhancedECImage()
-        method.
-    """
-    # Set the interrogation mode to always so that we actually interrogate.
-    self.console.interrogation_mode = b'always'
-
-    # First, assume that the EC interrogations indicate an non-enhanced EC
-    # image.
-    mock_check.return_value = False
-    # But our current knowledge of the EC image (which was actually the
-    # 'previous' EC) was an enhanced image.
-    self.console.enhanced_ec = True
-
-    test_command = b'sysinfo'
-    input_stream = []
-    input_stream.extend(BytesToByteList(test_command))
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # But, we will negotiate to non-enhanced however, dropping this command.
-    # Verify this.
-    self.assertFalse(self.console.enhanced_ec, msg=('Did not negotiate to'
-                                                    'non-enhanced EC image.'))
-    CheckInputBuffer(self, b'')
-    CheckInputBufferPosition(self, 0)
-
-    # The carriage return should have passed through though.
-    expected_calls = []
-    expected_calls.append(mock.call(
-        six.int2byte(console.ControlKey.CARRIAGE_RETURN)))
-
-    # Since the command was dropped, repeat the command.
-    input_stream = BytesToByteList(test_command)
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Since we're not enhanced now, we should have sent each character in the
-    # entire command separately and a carriage return.
-    for char in test_command:
-      if six.PY3:
-        expected_calls.append(mock.call(bytes([char])))
-      else:
-        expected_calls.append(mock.call(char))
-    expected_calls.append(mock.call(
-        six.int2byte(console.ControlKey.CARRIAGE_RETURN)))
-
-    # Verify all of the calls.
-    self.console.cmd_pipe.send.assert_has_calls(expected_calls)
-
-  def test_EnhancedCheckIfTimedOut(self):
-    """Verify that the check returns false if it times out."""
-    # Make the debug pipe "time out".
-    self.console.dbg_pipe.poll.return_value = False
-    self.assertFalse(self.console.CheckForEnhancedECImage())
-
-  def test_EnhancedCheckIfACKReceived(self):
-    """Verify that the check returns true if the ACK is received."""
-    # Make the debug pipe return EC_ACK.
-    self.console.dbg_pipe.poll.return_value = True
-    self.console.dbg_pipe.recv.return_value = interpreter.EC_ACK
-    self.assertTrue(self.console.CheckForEnhancedECImage())
-
-  def test_EnhancedCheckIfWrong(self):
-    """Verify that the check returns false if byte received is wrong."""
-    # Make the debug pipe return the wrong byte.
-    self.console.dbg_pipe.poll.return_value = True
-    self.console.dbg_pipe.recv.return_value = b'\xff'
-    self.assertFalse(self.console.CheckForEnhancedECImage())
-
-  def test_EnhancedCheckUsingBuffer(self):
-    """Verify that given reboot output, enhanced EC images are detected."""
-    enhanced_output_stream = b"""
+class TestConsoleCompatibility(unittest.TestCase):
+    """Verify that console can speak to enhanced and non-enhanced EC images."""
+
+    def setUp(self):
+        """Setup the test harness."""
+        # Setup logging with a timestamp, the module, and the log level.
+        logging.basicConfig(
+            level=logging.DEBUG,
+            format=("%(asctime)s - %(module)s - %(levelname)s - %(message)s"),
+        )
+        # Create a temp file and set both the controller and peripheral PTYs to the
+        # file to create a loopback.
+        self.tempfile = tempfile.TemporaryFile()
+
+        # Mock out the pipes.
+        mock_pipe_end_0, mock_pipe_end_1 = mock.MagicMock(), mock.MagicMock()
+        self.console = console.Console(
+            self.tempfile.fileno(),
+            self.tempfile,
+            tempfile.TemporaryFile(),
+            mock_pipe_end_0,
+            mock_pipe_end_1,
+            "EC",
+        )
+
+    @mock.patch("ec3po.console.Console.CheckForEnhancedECImage")
+    def test_ActAsPassThruInNonEnhancedMode(self, mock_check):
+        """Verify we simply pass everything thru to non-enhanced ECs.
+
+        Args:
+          mock_check: A MagicMock object replacing the CheckForEnhancedECImage()
+            method.
+        """
+        # Set the interrogation mode to always so that we actually interrogate.
+        self.console.interrogation_mode = b"always"
+
+        # Assume EC interrogations indicate that the image is non-enhanced.
+        mock_check.return_value = False
+
+        # Press enter, followed by the command, and another enter.
+        input_stream = []
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+        test_command = b"version"
+        input_stream.extend(BytesToByteList(test_command))
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # Expected calls to send down the pipe would be each character of the test
+        # command.
+        expected_calls = []
+        expected_calls.append(
+            mock.call(six.int2byte(console.ControlKey.CARRIAGE_RETURN))
+        )
+        for char in test_command:
+            if six.PY3:
+                expected_calls.append(mock.call(bytes([char])))
+            else:
+                expected_calls.append(mock.call(char))
+        expected_calls.append(
+            mock.call(six.int2byte(console.ControlKey.CARRIAGE_RETURN))
+        )
+
+        # Verify that the calls happened.
+        self.console.cmd_pipe.send.assert_has_calls(expected_calls)
+
+        # Since we're acting as a pass-thru, the input buffer should be empty and
+        # input_buffer_pos is 0.
+        CheckInputBuffer(self, b"")
+        CheckInputBufferPosition(self, 0)
+
+    @mock.patch("ec3po.console.Console.CheckForEnhancedECImage")
+    def test_TransitionFromNonEnhancedToEnhanced(self, mock_check):
+        """Verify that we transition correctly to enhanced mode.
+
+        Args:
+          mock_check: A MagicMock object replacing the CheckForEnhancedECImage()
+            method.
+        """
+        # Set the interrogation mode to always so that we actually interrogate.
+        self.console.interrogation_mode = b"always"
+
+        # First, assume that the EC interrogations indicate an enhanced EC image.
+        mock_check.return_value = True
+        # But our current knowledge of the EC image (which was actually the
+        # 'previous' EC) was a non-enhanced image.
+        self.console.enhanced_ec = False
+
+        test_command = b"sysinfo"
+        input_stream = []
+        input_stream.extend(BytesToByteList(test_command))
+
+        expected_calls = []
+        # All keystrokes to the console should be directed straight through to the
+        # EC until we press the enter key.
+        for char in test_command:
+            if six.PY3:
+                expected_calls.append(mock.call(bytes([char])))
+            else:
+                expected_calls.append(mock.call(char))
+
+        # Press the enter key.
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+        # The enter key should not be sent to the pipe since we should negotiate
+        # to an enhanced EC image.
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # At this point, we should have negotiated to enhanced.
+        self.assertTrue(
+            self.console.enhanced_ec,
+            msg=("Did not negotiate to enhanced EC image."),
+        )
+
+        # The command would have been dropped however, so verify this...
+        CheckInputBuffer(self, b"")
+        CheckInputBufferPosition(self, 0)
+        # ...and repeat the command.
+        input_stream = BytesToByteList(test_command)
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # Since we're enhanced now, we should have sent the entire command as one
+        # string with no trailing carriage return
+        expected_calls.append(mock.call(test_command))
+
+        # Verify all of the calls.
+        self.console.cmd_pipe.send.assert_has_calls(expected_calls)
+
+    @mock.patch("ec3po.console.Console.CheckForEnhancedECImage")
+    def test_TransitionFromEnhancedToNonEnhanced(self, mock_check):
+        """Verify that we transition correctly to non-enhanced mode.
+
+        Args:
+          mock_check: A MagicMock object replacing the CheckForEnhancedECImage()
+            method.
+        """
+        # Set the interrogation mode to always so that we actually interrogate.
+        self.console.interrogation_mode = b"always"
+
+        # First, assume that the EC interrogations indicate an non-enhanced EC
+        # image.
+        mock_check.return_value = False
+        # But our current knowledge of the EC image (which was actually the
+        # 'previous' EC) was an enhanced image.
+        self.console.enhanced_ec = True
+
+        test_command = b"sysinfo"
+        input_stream = []
+        input_stream.extend(BytesToByteList(test_command))
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # But, we will negotiate to non-enhanced however, dropping this command.
+        # Verify this.
+        self.assertFalse(
+            self.console.enhanced_ec,
+            msg=("Did not negotiate to non-enhanced EC image."),
+        )
+        CheckInputBuffer(self, b"")
+        CheckInputBufferPosition(self, 0)
+
+        # The carriage return should have passed through though.
+        expected_calls = []
+        expected_calls.append(
+            mock.call(six.int2byte(console.ControlKey.CARRIAGE_RETURN))
+        )
+
+        # Since the command was dropped, repeat the command.
+        input_stream = BytesToByteList(test_command)
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # Since we're not enhanced now, we should have sent each character in the
+        # entire command separately and a carriage return.
+        for char in test_command:
+            if six.PY3:
+                expected_calls.append(mock.call(bytes([char])))
+            else:
+                expected_calls.append(mock.call(char))
+        expected_calls.append(
+            mock.call(six.int2byte(console.ControlKey.CARRIAGE_RETURN))
+        )
+
+        # Verify all of the calls.
+        self.console.cmd_pipe.send.assert_has_calls(expected_calls)
+
+    def test_EnhancedCheckIfTimedOut(self):
+        """Verify that the check returns false if it times out."""
+        # Make the debug pipe "time out".
+        self.console.dbg_pipe.poll.return_value = False
+        self.assertFalse(self.console.CheckForEnhancedECImage())
+
+    def test_EnhancedCheckIfACKReceived(self):
+        """Verify that the check returns true if the ACK is received."""
+        # Make the debug pipe return EC_ACK.
+        self.console.dbg_pipe.poll.return_value = True
+        self.console.dbg_pipe.recv.return_value = interpreter.EC_ACK
+        self.assertTrue(self.console.CheckForEnhancedECImage())
+
+    def test_EnhancedCheckIfWrong(self):
+        """Verify that the check returns false if byte received is wrong."""
+        # Make the debug pipe return the wrong byte.
+        self.console.dbg_pipe.poll.return_value = True
+        self.console.dbg_pipe.recv.return_value = b"\xff"
+        self.assertFalse(self.console.CheckForEnhancedECImage())
+
+    def test_EnhancedCheckUsingBuffer(self):
+        """Verify that given reboot output, enhanced EC images are detected."""
+        enhanced_output_stream = b"""
 --- UART initialized after reboot ---
 [Reset cause: reset-pin soft]
 [Image: RO, jerry_v1.1.4363-2af8572-dirty 2016-02-23 13:26:20 aaboagye@lithium.mtv.corp.google.com]
@@ -1296,19 +1353,19 @@ def test_EnhancedCheckUsingBuffer(self):
 [0.224060 hash done 41dac382e3a6e3d2ea5b4d789c1bc46525cae7cc5ff6758f0de8d8369b506f57]
 [0.375150 POWER_GOOD seen]
 """
-    for line in enhanced_output_stream.split(b'\n'):
-      self.console.CheckBufferForEnhancedImage(line)
+        for line in enhanced_output_stream.split(b"\n"):
+            self.console.CheckBufferForEnhancedImage(line)
 
-    # Since the enhanced console string was present in the output, the console
-    # should have caught it.
-    self.assertTrue(self.console.enhanced_ec)
+        # Since the enhanced console string was present in the output, the console
+        # should have caught it.
+        self.assertTrue(self.console.enhanced_ec)
 
-    # Also should check that the command was sent to the interpreter.
-    self.console.cmd_pipe.send.assert_called_once_with(b'enhanced True')
+        # Also should check that the command was sent to the interpreter.
+        self.console.cmd_pipe.send.assert_called_once_with(b"enhanced True")
 
-    # Now test the non-enhanced EC image.
-    self.console.cmd_pipe.reset_mock()
-    non_enhanced_output_stream = b"""
+        # Now test the non-enhanced EC image.
+        self.console.cmd_pipe.reset_mock()
+        non_enhanced_output_stream = b"""
 --- UART initialized after reboot ---
 [Reset cause: reset-pin soft]
 [Image: RO, jerry_v1.1.4363-2af8572-dirty 2016-02-23 13:03:15 aaboagye@lithium.mtv.corp.google.com]
@@ -1332,239 +1389,254 @@ def test_EnhancedCheckUsingBuffer(self):
 [0.010285 power on 2]
 [0.010385 power state 5 = S5->S3, in 0x0000]
 """
-    for line in non_enhanced_output_stream.split(b'\n'):
-      self.console.CheckBufferForEnhancedImage(line)
+        for line in non_enhanced_output_stream.split(b"\n"):
+            self.console.CheckBufferForEnhancedImage(line)
 
-    # Since the default console string is present in the output, it should be
-    # determined to be non enhanced now.
-    self.assertFalse(self.console.enhanced_ec)
+        # Since the default console string is present in the output, it should be
+        # determined to be non enhanced now.
+        self.assertFalse(self.console.enhanced_ec)
 
-    # Check that command was also sent to the interpreter.
-    self.console.cmd_pipe.send.assert_called_once_with(b'enhanced False')
+        # Check that command was also sent to the interpreter.
+        self.console.cmd_pipe.send.assert_called_once_with(b"enhanced False")
 
 
 class TestOOBMConsoleCommands(unittest.TestCase):
-  """Verify that OOBM console commands work correctly."""
-  def setUp(self):
-    """Setup the test harness."""
-    # Setup logging with a timestamp, the module, and the log level.
-    logging.basicConfig(level=logging.DEBUG,
-                        format=('%(asctime)s - %(module)s -'
-                                ' %(levelname)s - %(message)s'))
-    # Create a temp file and set both the master and slave PTYs to the file to
-    # create a loopback.
-    self.tempfile = tempfile.TemporaryFile()
-
-    # Mock out the pipes.
-    mock_pipe_end_0, mock_pipe_end_1 = mock.MagicMock(), mock.MagicMock()
-    self.console = console.Console(self.tempfile.fileno(), self.tempfile,
-                                   tempfile.TemporaryFile(),
-                                   mock_pipe_end_0, mock_pipe_end_1, "EC")
-    self.console.oobm_queue = mock.MagicMock()
-
-  @mock.patch('console.Console.CheckForEnhancedECImage')
-  def test_InterrogateCommand(self, mock_check):
-    """Verify that 'interrogate' command works as expected.
-
-    Args:
-      mock_check: A MagicMock object replacing the CheckForEnhancedECIMage()
-        method.
-    """
-    input_stream = []
-    expected_calls = []
-    mock_check.side_effect = [False]
-
-    # 'interrogate never' should disable the interrogation from happening at
-    # all.
-    cmd = b'interrogate never'
-    # Enter the OOBM prompt.
-    input_stream.extend(BytesToByteList(b'%'))
-    # Type the command
-    input_stream.extend(BytesToByteList(cmd))
-    # Press enter.
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    input_stream = []
-
-    # The OOBM queue should have been called with the command being put.
-    expected_calls.append(mock.call.put(cmd))
-    self.console.oobm_queue.assert_has_calls(expected_calls)
-
-    # Process the OOBM queue.
-    self.console.oobm_queue.get.side_effect = [cmd]
-    self.console.ProcessOOBMQueue()
-
-    # Type out a few commands.
-    input_stream.extend(BytesToByteList(b'version'))
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-    input_stream.extend(BytesToByteList(b'flashinfo'))
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-    input_stream.extend(BytesToByteList(b'sysinfo'))
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # The Check function should NOT have been called at all.
-    mock_check.assert_not_called()
-
-    # The EC image should be assumed to be not enhanced.
-    self.assertFalse(self.console.enhanced_ec, 'The image should be assumed to'
-                     ' be NOT enhanced.')
-
-    # Reset the mocks.
-    mock_check.reset_mock()
-    self.console.oobm_queue.reset_mock()
-
-    # 'interrogate auto' should not interrogate at all.  It should only be
-    # scanning the output stream for the 'console is enabled' strings.
-    cmd = b'interrogate auto'
-    # Enter the OOBM prompt.
-    input_stream.extend(BytesToByteList(b'%'))
-    # Type the command
-    input_stream.extend(BytesToByteList(cmd))
-    # Press enter.
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    input_stream = []
-    expected_calls = []
-
-    # The OOBM queue should have been called with the command being put.
-    expected_calls.append(mock.call.put(cmd))
-    self.console.oobm_queue.assert_has_calls(expected_calls)
-
-    # Process the OOBM queue.
-    self.console.oobm_queue.get.side_effect = [cmd]
-    self.console.ProcessOOBMQueue()
-
-    # Type out a few commands.
-    input_stream.extend(BytesToByteList(b'version'))
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-    input_stream.extend(BytesToByteList(b'flashinfo'))
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-    input_stream.extend(BytesToByteList(b'sysinfo'))
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # The Check function should NOT have been called at all.
-    mock_check.assert_not_called()
-
-    # The EC image should be assumed to be not enhanced.
-    self.assertFalse(self.console.enhanced_ec, 'The image should be assumed to'
-                     ' be NOT enhanced.')
-
-    # Reset the mocks.
-    mock_check.reset_mock()
-    self.console.oobm_queue.reset_mock()
-
-    # 'interrogate always' should, like its name implies, interrogate always
-    # after each press of the enter key.  This was the former way of doing
-    # interrogation.
-    cmd = b'interrogate always'
-    # Enter the OOBM prompt.
-    input_stream.extend(BytesToByteList(b'%'))
-    # Type the command
-    input_stream.extend(BytesToByteList(cmd))
-    # Press enter.
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    input_stream = []
-    expected_calls = []
-
-    # The OOBM queue should have been called with the command being put.
-    expected_calls.append(mock.call.put(cmd))
-    self.console.oobm_queue.assert_has_calls(expected_calls)
-
-    # Process the OOBM queue.
-    self.console.oobm_queue.get.side_effect = [cmd]
-    self.console.ProcessOOBMQueue()
-
-    # The Check method should be called 3 times here.
-    mock_check.side_effect = [False, False, False]
-
-    # Type out a few commands.
-    input_stream.extend(BytesToByteList(b'help list'))
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-    input_stream.extend(BytesToByteList(b'taskinfo'))
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-    input_stream.extend(BytesToByteList(b'hibdelay'))
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # The Check method should have been called 3 times here.
-    expected_calls = [mock.call(), mock.call(), mock.call()]
-    mock_check.assert_has_calls(expected_calls)
-
-    # The EC image should be assumed to be not enhanced.
-    self.assertFalse(self.console.enhanced_ec, 'The image should be assumed to'
-                     ' be NOT enhanced.')
-
-    # Now, let's try to assume that the image is enhanced while still disabling
-    # interrogation.
-    mock_check.reset_mock()
-    self.console.oobm_queue.reset_mock()
-    input_stream = []
-    cmd = b'interrogate never enhanced'
-    # Enter the OOBM prompt.
-    input_stream.extend(BytesToByteList(b'%'))
-    # Type the command
-    input_stream.extend(BytesToByteList(cmd))
-    # Press enter.
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    input_stream = []
-    expected_calls = []
-
-    # The OOBM queue should have been called with the command being put.
-    expected_calls.append(mock.call.put(cmd))
-    self.console.oobm_queue.assert_has_calls(expected_calls)
-
-    # Process the OOBM queue.
-    self.console.oobm_queue.get.side_effect = [cmd]
-    self.console.ProcessOOBMQueue()
-
-    # Type out a few commands.
-    input_stream.extend(BytesToByteList(b'chgstate'))
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-    input_stream.extend(BytesToByteList(b'hash'))
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-    input_stream.extend(BytesToByteList(b'sysjump rw'))
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # The check method should have never been called.
-    mock_check.assert_not_called()
-
-    # The EC image should be assumed to be enhanced.
-    self.assertTrue(self.console.enhanced_ec, 'The image should be'
-                    ' assumed to be enhanced.')
-
-
-if __name__ == '__main__':
-  unittest.main()
+    """Verify that OOBM console commands work correctly."""
+
+    def setUp(self):
+        """Setup the test harness."""
+        # Setup logging with a timestamp, the module, and the log level.
+        logging.basicConfig(
+            level=logging.DEBUG,
+            format=("%(asctime)s - %(module)s - %(levelname)s - %(message)s"),
+        )
+        # Create a temp file and set both the controller and peripheral PTYs to the
+        # file to create a loopback.
+        self.tempfile = tempfile.TemporaryFile()
+
+        # Mock out the pipes.
+        mock_pipe_end_0, mock_pipe_end_1 = mock.MagicMock(), mock.MagicMock()
+        self.console = console.Console(
+            self.tempfile.fileno(),
+            self.tempfile,
+            tempfile.TemporaryFile(),
+            mock_pipe_end_0,
+            mock_pipe_end_1,
+            "EC",
+        )
+        self.console.oobm_queue = mock.MagicMock()
+
+    @mock.patch("ec3po.console.Console.CheckForEnhancedECImage")
+    def test_InterrogateCommand(self, mock_check):
+        """Verify that 'interrogate' command works as expected.
+
+        Args:
+          mock_check: A MagicMock object replacing the CheckForEnhancedECIMage()
+            method.
+        """
+        input_stream = []
+        expected_calls = []
+        mock_check.side_effect = [False]
+
+        # 'interrogate never' should disable the interrogation from happening at
+        # all.
+        cmd = b"interrogate never"
+        # Enter the OOBM prompt.
+        input_stream.extend(BytesToByteList(b"%"))
+        # Type the command
+        input_stream.extend(BytesToByteList(cmd))
+        # Press enter.
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        input_stream = []
+
+        # The OOBM queue should have been called with the command being put.
+        expected_calls.append(mock.call.put(cmd))
+        self.console.oobm_queue.assert_has_calls(expected_calls)
+
+        # Process the OOBM queue.
+        self.console.oobm_queue.get.side_effect = [cmd]
+        self.console.ProcessOOBMQueue()
+
+        # Type out a few commands.
+        input_stream.extend(BytesToByteList(b"version"))
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+        input_stream.extend(BytesToByteList(b"flashinfo"))
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+        input_stream.extend(BytesToByteList(b"sysinfo"))
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # The Check function should NOT have been called at all.
+        mock_check.assert_not_called()
+
+        # The EC image should be assumed to be not enhanced.
+        self.assertFalse(
+            self.console.enhanced_ec,
+            "The image should be assumed to be NOT enhanced.",
+        )
+
+        # Reset the mocks.
+        mock_check.reset_mock()
+        self.console.oobm_queue.reset_mock()
+
+        # 'interrogate auto' should not interrogate at all.  It should only be
+        # scanning the output stream for the 'console is enabled' strings.
+        cmd = b"interrogate auto"
+        # Enter the OOBM prompt.
+        input_stream.extend(BytesToByteList(b"%"))
+        # Type the command
+        input_stream.extend(BytesToByteList(cmd))
+        # Press enter.
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        input_stream = []
+        expected_calls = []
+
+        # The OOBM queue should have been called with the command being put.
+        expected_calls.append(mock.call.put(cmd))
+        self.console.oobm_queue.assert_has_calls(expected_calls)
+
+        # Process the OOBM queue.
+        self.console.oobm_queue.get.side_effect = [cmd]
+        self.console.ProcessOOBMQueue()
+
+        # Type out a few commands.
+        input_stream.extend(BytesToByteList(b"version"))
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+        input_stream.extend(BytesToByteList(b"flashinfo"))
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+        input_stream.extend(BytesToByteList(b"sysinfo"))
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # The Check function should NOT have been called at all.
+        mock_check.assert_not_called()
+
+        # The EC image should be assumed to be not enhanced.
+        self.assertFalse(
+            self.console.enhanced_ec,
+            "The image should be assumed to be NOT enhanced.",
+        )
+
+        # Reset the mocks.
+        mock_check.reset_mock()
+        self.console.oobm_queue.reset_mock()
+
+        # 'interrogate always' should, like its name implies, interrogate always
+        # after each press of the enter key.  This was the former way of doing
+        # interrogation.
+        cmd = b"interrogate always"
+        # Enter the OOBM prompt.
+        input_stream.extend(BytesToByteList(b"%"))
+        # Type the command
+        input_stream.extend(BytesToByteList(cmd))
+        # Press enter.
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        input_stream = []
+        expected_calls = []
+
+        # The OOBM queue should have been called with the command being put.
+        expected_calls.append(mock.call.put(cmd))
+        self.console.oobm_queue.assert_has_calls(expected_calls)
+
+        # Process the OOBM queue.
+        self.console.oobm_queue.get.side_effect = [cmd]
+        self.console.ProcessOOBMQueue()
+
+        # The Check method should be called 3 times here.
+        mock_check.side_effect = [False, False, False]
+
+        # Type out a few commands.
+        input_stream.extend(BytesToByteList(b"help list"))
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+        input_stream.extend(BytesToByteList(b"taskinfo"))
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+        input_stream.extend(BytesToByteList(b"hibdelay"))
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # The Check method should have been called 3 times here.
+        expected_calls = [mock.call(), mock.call(), mock.call()]
+        mock_check.assert_has_calls(expected_calls)
+
+        # The EC image should be assumed to be not enhanced.
+        self.assertFalse(
+            self.console.enhanced_ec,
+            "The image should be assumed to be NOT enhanced.",
+        )
+
+        # Now, let's try to assume that the image is enhanced while still disabling
+        # interrogation.
+        mock_check.reset_mock()
+        self.console.oobm_queue.reset_mock()
+        input_stream = []
+        cmd = b"interrogate never enhanced"
+        # Enter the OOBM prompt.
+        input_stream.extend(BytesToByteList(b"%"))
+        # Type the command
+        input_stream.extend(BytesToByteList(cmd))
+        # Press enter.
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        input_stream = []
+        expected_calls = []
+
+        # The OOBM queue should have been called with the command being put.
+        expected_calls.append(mock.call.put(cmd))
+        self.console.oobm_queue.assert_has_calls(expected_calls)
+
+        # Process the OOBM queue.
+        self.console.oobm_queue.get.side_effect = [cmd]
+        self.console.ProcessOOBMQueue()
+
+        # Type out a few commands.
+        input_stream.extend(BytesToByteList(b"chgstate"))
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+        input_stream.extend(BytesToByteList(b"hash"))
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+        input_stream.extend(BytesToByteList(b"sysjump rw"))
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # The check method should have never been called.
+        mock_check.assert_not_called()
+
+        # The EC image should be assumed to be enhanced.
+        self.assertTrue(
+            self.console.enhanced_ec,
+            "The image should be assumed to be enhanced.",
+        )
+
+
+if __name__ == "__main__":
+    unittest.main()
diff --git a/util/ec3po/interpreter.py b/util/ec3po/interpreter.py
index 66394fe45a..16c047039b 100644
--- a/util/ec3po/interpreter.py
+++ b/util/ec3po/interpreter.py
@@ -1,4 +1,4 @@
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -17,7 +17,6 @@
 from __future__ import print_function
 
 import binascii
-# pylint: disable=cros-logging-import
 import copy
 import logging
 import os
@@ -29,433 +28,455 @@
 
 COMMAND_RETRIES = 3  # Number of attempts to retry a command.
 EC_MAX_READ = 1024  # Max bytes to read at a time from the EC.
-EC_SYN = b'\xec'  # Byte indicating EC interrogation.
-EC_ACK = b'\xc0'  # Byte representing correct EC response to interrogation.
+EC_SYN = b"\xec"  # Byte indicating EC interrogation.
+EC_ACK = b"\xc0"  # Byte representing correct EC response to interrogation.
 
 
 class LoggerAdapter(logging.LoggerAdapter):
-  """Class which provides a small adapter for the logger."""
+    """Class which provides a small adapter for the logger."""
 
-  def process(self, msg, kwargs):
-    """Prepends the served PTY to the beginning of the log message."""
-    return '%s - %s' % (self.extra['pty'], msg), kwargs
+    def process(self, msg, kwargs):
+        """Prepends the served PTY to the beginning of the log message."""
+        return "%s - %s" % (self.extra["pty"], msg), kwargs
 
 
 class Interpreter(object):
-  """Class which provides the interpretation layer between the EC and user.
-
-  This class essentially performs all of the intepretation for the EC and the
-  user.  It handles all of the automatic command retrying as well as the
-  formation of commands for EC images which support that.
-
-  Attributes:
-    logger: A logger for this module.
-    ec_uart_pty: An opened file object to the raw EC UART PTY.
-    ec_uart_pty_name: A string containing the name of the raw EC UART PTY.
-    cmd_pipe: A socket.socket or multiprocessing.Connection object which
-      represents the Interpreter side of the command pipe.  This must be a
-      bidirectional pipe.  Commands and responses will utilize this pipe.
-    dbg_pipe: A socket.socket or multiprocessing.Connection object which
-      represents the Interpreter side of the debug pipe. This must be a
-      unidirectional pipe with write capabilities.  EC debug output will utilize
-      this pipe.
-    cmd_retries: An integer representing the number of attempts the console
-      should retry commands if it receives an error.
-    log_level: An integer representing the numeric value of the log level.
-    inputs: A list of objects that the intpreter selects for reading.
-      Initially, these are the EC UART and the command pipe.
-    outputs: A list of objects that the interpreter selects for writing.
-    ec_cmd_queue: A FIFO queue used for sending commands down to the EC UART.
-    last_cmd: A string that represents the last command sent to the EC.  If an
-      error is encountered, the interpreter will attempt to retry this command
-      up to COMMAND_RETRIES.
-    enhanced_ec: A boolean indicating if the EC image that we are currently
-      communicating with is enhanced or not.  Enhanced EC images will support
-      packed commands and host commands over the UART.  This defaults to False
-      and is changed depending on the result of an interrogation.
-    interrogating: A boolean indicating if we are in the middle of interrogating
-      the EC.
-    connected: A boolean indicating if the interpreter is actually connected to
-      the UART and listening.
-  """
-  def __init__(self, ec_uart_pty, cmd_pipe, dbg_pipe, log_level=logging.INFO,
-               name=None):
-    """Intializes an Interpreter object with the provided args.
+    """Class which provides the interpretation layer between the EC and user.
 
-    Args:
-      ec_uart_pty: A string representing the EC UART to connect to.
+    This class essentially performs all of the intepretation for the EC and the
+    user.  It handles all of the automatic command retrying as well as the
+    formation of commands for EC images which support that.
+
+    Attributes:
+      logger: A logger for this module.
+      ec_uart_pty: An opened file object to the raw EC UART PTY.
+      ec_uart_pty_name: A string containing the name of the raw EC UART PTY.
       cmd_pipe: A socket.socket or multiprocessing.Connection object which
         represents the Interpreter side of the command pipe.  This must be a
         bidirectional pipe.  Commands and responses will utilize this pipe.
       dbg_pipe: A socket.socket or multiprocessing.Connection object which
         represents the Interpreter side of the debug pipe. This must be a
-        unidirectional pipe with write capabilities.  EC debug output will
-        utilize this pipe.
+        unidirectional pipe with write capabilities.  EC debug output will utilize
+        this pipe.
       cmd_retries: An integer representing the number of attempts the console
         should retry commands if it receives an error.
-      log_level: An optional integer representing the numeric value of the log
-        level.  By default, the log level will be logging.INFO (20).
-      name: the console source name
+      log_level: An integer representing the numeric value of the log level.
+      inputs: A list of objects that the intpreter selects for reading.
+        Initially, these are the EC UART and the command pipe.
+      outputs: A list of objects that the interpreter selects for writing.
+      ec_cmd_queue: A FIFO queue used for sending commands down to the EC UART.
+      last_cmd: A string that represents the last command sent to the EC.  If an
+        error is encountered, the interpreter will attempt to retry this command
+        up to COMMAND_RETRIES.
+      enhanced_ec: A boolean indicating if the EC image that we are currently
+        communicating with is enhanced or not.  Enhanced EC images will support
+        packed commands and host commands over the UART.  This defaults to False
+        and is changed depending on the result of an interrogation.
+      interrogating: A boolean indicating if we are in the middle of interrogating
+        the EC.
+      connected: A boolean indicating if the interpreter is actually connected to
+        the UART and listening.
     """
-    # Create a unique logger based on the interpreter name
-    interpreter_prefix = ('%s - ' % name) if name else ''
-    logger = logging.getLogger('%sEC3PO.Interpreter' % interpreter_prefix)
-    self.logger = LoggerAdapter(logger, {'pty': ec_uart_pty})
-    self.ec_uart_pty = open(ec_uart_pty, 'ab+')
-    self.ec_uart_pty_name = ec_uart_pty
-    self.cmd_pipe = cmd_pipe
-    self.dbg_pipe = dbg_pipe
-    self.cmd_retries = COMMAND_RETRIES
-    self.log_level = log_level
-    self.inputs = [self.ec_uart_pty, self.cmd_pipe]
-    self.outputs = []
-    self.ec_cmd_queue = six.moves.queue.Queue()
-    self.last_cmd = b''
-    self.enhanced_ec = False
-    self.interrogating = False
-    self.connected = True
-
-  def __str__(self):
-    """Show internal state of the Interpreter object.
 
-    Returns:
-      A string that shows the values of the attributes.
-    """
-    string = []
-    string.append('%r' % self)
-    string.append('ec_uart_pty: %s' % self.ec_uart_pty)
-    string.append('cmd_pipe: %r' % self.cmd_pipe)
-    string.append('dbg_pipe: %r' % self.dbg_pipe)
-    string.append('cmd_retries: %d' % self.cmd_retries)
-    string.append('log_level: %d' % self.log_level)
-    string.append('inputs: %r' % self.inputs)
-    string.append('outputs: %r' % self.outputs)
-    string.append('ec_cmd_queue: %r' % self.ec_cmd_queue)
-    string.append('last_cmd: \'%s\'' % self.last_cmd)
-    string.append('enhanced_ec: %r' % self.enhanced_ec)
-    string.append('interrogating: %r' % self.interrogating)
-    return '\n'.join(string)
-
-  def EnqueueCmd(self, command):
-    """Enqueue a command to be sent to the EC UART.
-
-    Args:
-      command: A string which contains the command to be sent.
-    """
-    self.ec_cmd_queue.put(command)
-    self.logger.log(1, 'Commands now in queue: %d', self.ec_cmd_queue.qsize())
+    def __init__(
+        self, ec_uart_pty, cmd_pipe, dbg_pipe, log_level=logging.INFO, name=None
+    ):
+        """Intializes an Interpreter object with the provided args.
+
+        Args:
+          ec_uart_pty: A string representing the EC UART to connect to.
+          cmd_pipe: A socket.socket or multiprocessing.Connection object which
+            represents the Interpreter side of the command pipe.  This must be a
+            bidirectional pipe.  Commands and responses will utilize this pipe.
+          dbg_pipe: A socket.socket or multiprocessing.Connection object which
+            represents the Interpreter side of the debug pipe. This must be a
+            unidirectional pipe with write capabilities.  EC debug output will
+            utilize this pipe.
+          cmd_retries: An integer representing the number of attempts the console
+            should retry commands if it receives an error.
+          log_level: An optional integer representing the numeric value of the log
+            level.  By default, the log level will be logging.INFO (20).
+          name: the console source name
+        """
+        # Create a unique logger based on the interpreter name
+        interpreter_prefix = ("%s - " % name) if name else ""
+        logger = logging.getLogger("%sEC3PO.Interpreter" % interpreter_prefix)
+        self.logger = LoggerAdapter(logger, {"pty": ec_uart_pty})
+        # TODO(https://crbug.com/1162189): revist the 2 TODOs below
+        # TODO(https://bugs.python.org/issue27805, python3.7+): revert to ab+
+        # TODO(https://bugs.python.org/issue20074): removing buffering=0 if/when
+        # that gets fixed, or keep two pty: one for reading and one for writing
+        self.ec_uart_pty = open(ec_uart_pty, "r+b", buffering=0)
+        self.ec_uart_pty_name = ec_uart_pty
+        self.cmd_pipe = cmd_pipe
+        self.dbg_pipe = dbg_pipe
+        self.cmd_retries = COMMAND_RETRIES
+        self.log_level = log_level
+        self.inputs = [self.ec_uart_pty, self.cmd_pipe]
+        self.outputs = []
+        self.ec_cmd_queue = six.moves.queue.Queue()
+        self.last_cmd = b""
+        self.enhanced_ec = False
+        self.interrogating = False
+        self.connected = True
 
-    # Add the EC UART as an output to be serviced.
-    if self.connected and self.ec_uart_pty not in self.outputs:
-      self.outputs.append(self.ec_uart_pty)
+    def __str__(self):
+        """Show internal state of the Interpreter object.
+
+        Returns:
+          A string that shows the values of the attributes.
+        """
+        string = []
+        string.append("%r" % self)
+        string.append("ec_uart_pty: %s" % self.ec_uart_pty)
+        string.append("cmd_pipe: %r" % self.cmd_pipe)
+        string.append("dbg_pipe: %r" % self.dbg_pipe)
+        string.append("cmd_retries: %d" % self.cmd_retries)
+        string.append("log_level: %d" % self.log_level)
+        string.append("inputs: %r" % self.inputs)
+        string.append("outputs: %r" % self.outputs)
+        string.append("ec_cmd_queue: %r" % self.ec_cmd_queue)
+        string.append("last_cmd: '%s'" % self.last_cmd)
+        string.append("enhanced_ec: %r" % self.enhanced_ec)
+        string.append("interrogating: %r" % self.interrogating)
+        return "\n".join(string)
+
+    def EnqueueCmd(self, command):
+        """Enqueue a command to be sent to the EC UART.
+
+        Args:
+          command: A string which contains the command to be sent.
+        """
+        self.ec_cmd_queue.put(command)
+        self.logger.log(
+            1, "Commands now in queue: %d", self.ec_cmd_queue.qsize()
+        )
+
+        # Add the EC UART as an output to be serviced.
+        if self.connected and self.ec_uart_pty not in self.outputs:
+            self.outputs.append(self.ec_uart_pty)
+
+    def PackCommand(self, raw_cmd):
+        r"""Packs a command for use with error checking.
+
+        For error checking, we pack console commands in a particular format.  The
+        format is as follows:
+
+          &&[x][x][x][x]&{cmd}\n\n
+          ^ ^    ^^    ^^  ^  ^-- 2 newlines.
+          | |    ||    ||  |-- the raw console command.
+          | |    ||    ||-- 1 ampersand.
+          | |    ||____|--- 2 hex digits representing the CRC8 of cmd.
+          | |____|-- 2 hex digits reprsenting the length of cmd.
+          |-- 2 ampersands
+
+        Args:
+          raw_cmd: A pre-packed string which contains the raw command.
+
+        Returns:
+          A string which contains the packed command.
+        """
+        # Don't pack a single carriage return.
+        if raw_cmd != b"\r":
+            # The command format is as follows.
+            # &&[x][x][x][x]&{cmd}\n\n
+            packed_cmd = []
+            packed_cmd.append(b"&&")
+            # The first pair of hex digits are the length of the command.
+            packed_cmd.append(b"%02x" % len(raw_cmd))
+            # Then the CRC8 of cmd.
+            packed_cmd.append(b"%02x" % Crc8(raw_cmd))
+            packed_cmd.append(b"&")
+            # Now, the raw command followed by 2 newlines.
+            packed_cmd.append(raw_cmd)
+            packed_cmd.append(b"\n\n")
+            return b"".join(packed_cmd)
+        else:
+            return raw_cmd
+
+    def ProcessCommand(self, command):
+        """Captures the input determines what actions to take.
+
+        Args:
+          command: A string representing the command sent by the user.
+        """
+        if command == b"disconnect":
+            if self.connected:
+                self.logger.debug("UART disconnect request.")
+                # Drop all pending commands if any.
+                while not self.ec_cmd_queue.empty():
+                    c = self.ec_cmd_queue.get()
+                    self.logger.debug("dropped: '%s'", c)
+                if self.enhanced_ec:
+                    # Reset retry state.
+                    self.cmd_retries = COMMAND_RETRIES
+                    self.last_cmd = b""
+                # Get the UART that the interpreter is attached to.
+                fileobj = self.ec_uart_pty
+                self.logger.debug("fileobj: %r", fileobj)
+                # Remove the descriptor from the inputs and outputs.
+                self.inputs.remove(fileobj)
+                if fileobj in self.outputs:
+                    self.outputs.remove(fileobj)
+                self.logger.debug(
+                    "Removed fileobj. Remaining inputs: %r", self.inputs
+                )
+                # Close the file.
+                fileobj.close()
+                # Mark the interpreter as disconnected now.
+                self.connected = False
+                self.logger.debug(
+                    "Disconnected from %s.", self.ec_uart_pty_name
+                )
+            return
+
+        elif command == b"reconnect":
+            if not self.connected:
+                self.logger.debug("UART reconnect request.")
+                # Reopen the PTY.
+                # TODO(https://bugs.python.org/issue27805, python3.7+): revert to ab+
+                # TODO(https://bugs.python.org/issue20074): removing buffering=0 if/when
+                # that gets fixed, or keep two pty: one for reading and one for writing
+                fileobj = open(self.ec_uart_pty_name, "r+b", buffering=0)
+                self.logger.debug("fileobj: %r", fileobj)
+                self.ec_uart_pty = fileobj
+                # Add the descriptor to the inputs.
+                self.inputs.append(fileobj)
+                self.logger.debug("fileobj added. curr inputs: %r", self.inputs)
+                # Mark the interpreter as connected now.
+                self.connected = True
+                self.logger.debug("Connected to %s.", self.ec_uart_pty_name)
+            return
+
+        elif command.startswith(b"enhanced"):
+            self.enhanced_ec = command.split(b" ")[1] == b"True"
+            return
+
+        # Ignore any other commands while in the disconnected state.
+        self.logger.log(1, "command: '%s'", command)
+        if not self.connected:
+            self.logger.debug(
+                "Ignoring command because currently disconnected."
+            )
+            return
+
+        # Remove leading and trailing spaces only if this is an enhanced EC image.
+        # For non-enhanced EC images, commands will be single characters at a time
+        # and can be spaces.
+        if self.enhanced_ec:
+            command = command.strip(b" ")
+
+        # There's nothing to do if the command is empty.
+        if len(command) == 0:
+            return
+
+        # Handle log level change requests.
+        if command.startswith(b"loglevel"):
+            self.logger.debug("Log level change request.")
+            new_log_level = int(command.split(b" ")[1])
+            self.logger.logger.setLevel(new_log_level)
+            self.logger.info("Log level changed to %d.", new_log_level)
+            return
+
+        # Check for interrogation command.
+        if command == EC_SYN:
+            # User is requesting interrogation.  Send SYN as is.
+            self.logger.debug("User requesting interrogation.")
+            self.interrogating = True
+            # Assume the EC isn't enhanced until we get a response.
+            self.enhanced_ec = False
+        elif self.enhanced_ec:
+            # Enhanced EC images require the plaintext commands to be packed.
+            command = self.PackCommand(command)
+            # TODO(aaboagye): Make a dict of commands and keys and eventually,
+            # handle partial matching based on unique prefixes.
+
+        self.EnqueueCmd(command)
+
+    def HandleCmdRetries(self):
+        """Attempts to retry commands if possible."""
+        if self.cmd_retries > 0:
+            # The EC encountered an error.  We'll have to retry again.
+            self.logger.warning("Retrying command...")
+            self.cmd_retries -= 1
+            self.logger.warning("Retries remaining: %d", self.cmd_retries)
+            # Retry the command and add the EC UART to the writers again.
+            self.EnqueueCmd(self.last_cmd)
+            self.outputs.append(self.ec_uart_pty)
+        else:
+            # We're out of retries, so just give up.
+            self.logger.error("Command failed.  No retries left.")
+            # Clear the command in progress.
+            self.last_cmd = b""
+            # Reset the retry count.
+            self.cmd_retries = COMMAND_RETRIES
+
+    def SendCmdToEC(self):
+        """Sends a command to the EC."""
+        # If we're retrying a command, just try to send it again.
+        if self.cmd_retries < COMMAND_RETRIES:
+            cmd = self.last_cmd
+        else:
+            # If we're not retrying, we should not be writing to the EC if we have no
+            # items in our command queue.
+            assert not self.ec_cmd_queue.empty()
+            # Get the command to send.
+            cmd = self.ec_cmd_queue.get()
+
+        # Send the command.
+        self.ec_uart_pty.write(cmd)
+        self.ec_uart_pty.flush()
+        self.logger.log(1, "Sent command to EC.")
+
+        if self.enhanced_ec and cmd != EC_SYN:
+            # Now, that we've sent the command, store the current command as the last
+            # command sent.  If we encounter an error string, we will attempt to retry
+            # this command.
+            if cmd != self.last_cmd:
+                self.last_cmd = cmd
+                # Reset the retry count.
+                self.cmd_retries = COMMAND_RETRIES
+
+        # If no command is pending to be sent, then we can remove the EC UART from
+        # writers.  Might need better checking for command retry logic in here.
+        if self.ec_cmd_queue.empty():
+            # Remove the EC UART from the writers while we wait for a response.
+            self.logger.debug("Removing EC UART from writers.")
+            self.outputs.remove(self.ec_uart_pty)
+
+    def HandleECData(self):
+        """Handle any debug prints from the EC."""
+        self.logger.log(1, "EC has data")
+        # Read what the EC sent us.
+        data = os.read(self.ec_uart_pty.fileno(), EC_MAX_READ)
+        self.logger.log(1, "got: '%s'", binascii.hexlify(data))
+        if b"&E" in data and self.enhanced_ec:
+            # We received an error, so we should retry it if possible.
+            self.logger.warning("Error string found in data.")
+            self.HandleCmdRetries()
+            return
+
+        # If we were interrogating, check the response and update our knowledge
+        # of the current EC image.
+        if self.interrogating:
+            self.enhanced_ec = data == EC_ACK
+            if self.enhanced_ec:
+                self.logger.debug("The current EC image seems enhanced.")
+            else:
+                self.logger.debug(
+                    "The current EC image does NOT seem enhanced."
+                )
+            # Done interrogating.
+            self.interrogating = False
+        # For now, just forward everything the EC sends us.
+        self.logger.log(1, "Forwarding to user...")
+        self.dbg_pipe.send(data)
+
+    def HandleUserData(self):
+        """Handle any incoming commands from the user.
+
+        Raises:
+          EOFError: Allowed to propagate through from self.cmd_pipe.recv().
+        """
+        self.logger.log(1, "Command data available.  Begin processing.")
+        data = self.cmd_pipe.recv()
+        # Process the command.
+        self.ProcessCommand(data)
 
-  def PackCommand(self, raw_cmd):
-    r"""Packs a command for use with error checking.
 
-    For error checking, we pack console commands in a particular format.  The
-    format is as follows:
+def Crc8(data):
+    """Calculates the CRC8 of data.
 
-      &&[x][x][x][x]&{cmd}\n\n
-      ^ ^    ^^    ^^  ^  ^-- 2 newlines.
-      | |    ||    ||  |-- the raw console command.
-      | |    ||    ||-- 1 ampersand.
-      | |    ||____|--- 2 hex digits representing the CRC8 of cmd.
-      | |____|-- 2 hex digits reprsenting the length of cmd.
-      |-- 2 ampersands
+    The generator polynomial used is: x^8 + x^2 + x + 1.
+    This is the same implementation that is used in the EC.
 
     Args:
-      raw_cmd: A pre-packed string which contains the raw command.
+      data: A string of data that we wish to calculate the CRC8 on.
 
     Returns:
-      A string which contains the packed command.
-    """
-    # Don't pack a single carriage return.
-    if raw_cmd != b'\r':
-      # The command format is as follows.
-      # &&[x][x][x][x]&{cmd}\n\n
-      packed_cmd = []
-      packed_cmd.append(b'&&')
-      # The first pair of hex digits are the length of the command.
-      packed_cmd.append(b'%02x' % len(raw_cmd))
-      # Then the CRC8 of cmd.
-      packed_cmd.append(b'%02x' % Crc8(raw_cmd))
-      packed_cmd.append(b'&')
-      # Now, the raw command followed by 2 newlines.
-      packed_cmd.append(raw_cmd)
-      packed_cmd.append(b'\n\n')
-      return b''.join(packed_cmd)
-    else:
-      return raw_cmd
-
-  def ProcessCommand(self, command):
-    """Captures the input determines what actions to take.
-
-    Args:
-      command: A string representing the command sent by the user.
+      crc >> 8: An integer representing the CRC8 value.
     """
-    if command == b'disconnect':
-      if self.connected:
-        self.logger.debug('UART disconnect request.')
-        # Drop all pending commands if any.
-        while not self.ec_cmd_queue.empty():
-          c = self.ec_cmd_queue.get()
-          self.logger.debug('dropped: \'%s\'', c)
-        if self.enhanced_ec:
-          # Reset retry state.
-          self.cmd_retries = COMMAND_RETRIES
-          self.last_cmd = b''
-        # Get the UART that the interpreter is attached to.
-        fileobj = self.ec_uart_pty
-        self.logger.debug('fileobj: %r', fileobj)
-        # Remove the descriptor from the inputs and outputs.
-        self.inputs.remove(fileobj)
-        if fileobj in self.outputs:
-          self.outputs.remove(fileobj)
-        self.logger.debug('Removed fileobj. Remaining inputs: %r', self.inputs)
-        # Close the file.
-        fileobj.close()
-        # Mark the interpreter as disconnected now.
-        self.connected = False
-        self.logger.debug('Disconnected from %s.', self.ec_uart_pty_name)
-      return
-
-    elif command == b'reconnect':
-      if not self.connected:
-        self.logger.debug('UART reconnect request.')
-        # Reopen the PTY.
-        fileobj = open(self.ec_uart_pty_name, 'ab+')
-        self.logger.debug('fileobj: %r', fileobj)
-        self.ec_uart_pty = fileobj
-        # Add the descriptor to the inputs.
-        self.inputs.append(fileobj)
-        self.logger.debug('fileobj added. curr inputs: %r', self.inputs)
-        # Mark the interpreter as connected now.
-        self.connected = True
-        self.logger.debug('Connected to %s.', self.ec_uart_pty_name)
-      return
-
-    elif command.startswith(b'enhanced'):
-      self.enhanced_ec = command.split(b' ')[1] == b'True'
-      return
-
-    # Ignore any other commands while in the disconnected state.
-    self.logger.log(1, 'command: \'%s\'', command)
-    if not self.connected:
-      self.logger.debug('Ignoring command because currently disconnected.')
-      return
-
-    # Remove leading and trailing spaces only if this is an enhanced EC image.
-    # For non-enhanced EC images, commands will be single characters at a time
-    # and can be spaces.
-    if self.enhanced_ec:
-      command = command.strip(b' ')
-
-    # There's nothing to do if the command is empty.
-    if len(command) == 0:
-      return
-
-    # Handle log level change requests.
-    if command.startswith(b'loglevel'):
-      self.logger.debug('Log level change request.')
-      new_log_level = int(command.split(b' ')[1])
-      self.logger.logger.setLevel(new_log_level)
-      self.logger.info('Log level changed to %d.', new_log_level)
-      return
-
-    # Check for interrogation command.
-    if command == EC_SYN:
-      # User is requesting interrogation.  Send SYN as is.
-      self.logger.debug('User requesting interrogation.')
-      self.interrogating = True
-      # Assume the EC isn't enhanced until we get a response.
-      self.enhanced_ec = False
-    elif self.enhanced_ec:
-      # Enhanced EC images require the plaintext commands to be packed.
-      command = self.PackCommand(command)
-      # TODO(aaboagye): Make a dict of commands and keys and eventually,
-      # handle partial matching based on unique prefixes.
-
-    self.EnqueueCmd(command)
-
-  def HandleCmdRetries(self):
-    """Attempts to retry commands if possible."""
-    if self.cmd_retries > 0:
-      # The EC encountered an error.  We'll have to retry again.
-      self.logger.warning('Retrying command...')
-      self.cmd_retries -= 1
-      self.logger.warning('Retries remaining: %d', self.cmd_retries)
-      # Retry the command and add the EC UART to the writers again.
-      self.EnqueueCmd(self.last_cmd)
-      self.outputs.append(self.ec_uart_pty)
-    else:
-      # We're out of retries, so just give up.
-      self.logger.error('Command failed.  No retries left.')
-      # Clear the command in progress.
-      self.last_cmd = b''
-      # Reset the retry count.
-      self.cmd_retries = COMMAND_RETRIES
-
-  def SendCmdToEC(self):
-    """Sends a command to the EC."""
-    # If we're retrying a command, just try to send it again.
-    if self.cmd_retries < COMMAND_RETRIES:
-      cmd = self.last_cmd
-    else:
-      # If we're not retrying, we should not be writing to the EC if we have no
-      # items in our command queue.
-      assert not self.ec_cmd_queue.empty()
-      # Get the command to send.
-      cmd = self.ec_cmd_queue.get()
-
-    # Send the command.
-    self.ec_uart_pty.write(cmd)
-    self.ec_uart_pty.flush()
-    self.logger.log(1, 'Sent command to EC.')
-
-    if self.enhanced_ec and cmd != EC_SYN:
-      # Now, that we've sent the command, store the current command as the last
-      # command sent.  If we encounter an error string, we will attempt to retry
-      # this command.
-      if cmd != self.last_cmd:
-        self.last_cmd = cmd
-        # Reset the retry count.
-        self.cmd_retries = COMMAND_RETRIES
-
-    # If no command is pending to be sent, then we can remove the EC UART from
-    # writers.  Might need better checking for command retry logic in here.
-    if self.ec_cmd_queue.empty():
-      # Remove the EC UART from the writers while we wait for a response.
-      self.logger.debug('Removing EC UART from writers.')
-      self.outputs.remove(self.ec_uart_pty)
-
-  def HandleECData(self):
-    """Handle any debug prints from the EC."""
-    self.logger.log(1, 'EC has data')
-    # Read what the EC sent us.
-    data = os.read(self.ec_uart_pty.fileno(), EC_MAX_READ)
-    self.logger.log(1, 'got: \'%s\'', binascii.hexlify(data))
-    if b'&E' in data and self.enhanced_ec:
-      # We received an error, so we should retry it if possible.
-      self.logger.warning('Error string found in data.')
-      self.HandleCmdRetries()
-      return
-
-    # If we were interrogating, check the response and update our knowledge
-    # of the current EC image.
-    if self.interrogating:
-      self.enhanced_ec = data == EC_ACK
-      if self.enhanced_ec:
-        self.logger.debug('The current EC image seems enhanced.')
-      else:
-        self.logger.debug('The current EC image does NOT seem enhanced.')
-      # Done interrogating.
-      self.interrogating = False
-    # For now, just forward everything the EC sends us.
-    self.logger.log(1, 'Forwarding to user...')
-    self.dbg_pipe.send(data)
-
-  def HandleUserData(self):
-    """Handle any incoming commands from the user.
-
-    Raises:
-      EOFError: Allowed to propagate through from self.cmd_pipe.recv().
-    """
-    self.logger.log(1, 'Command data available.  Begin processing.')
-    data = self.cmd_pipe.recv()
-    # Process the command.
-    self.ProcessCommand(data)
+    crc = 0
+    for byte in six.iterbytes(data):
+        crc ^= byte << 8
+        for _ in range(8):
+            if crc & 0x8000:
+                crc ^= 0x1070 << 3
+            crc <<= 1
+    return crc >> 8
 
 
-def Crc8(data):
-  """Calculates the CRC8 of data.
-
-  The generator polynomial used is: x^8 + x^2 + x + 1.
-  This is the same implementation that is used in the EC.
-
-  Args:
-    data: A string of data that we wish to calculate the CRC8 on.
+def StartLoop(interp, shutdown_pipe=None):
+    """Starts an infinite loop of servicing the user and the EC.
 
-  Returns:
-    crc >> 8: An integer representing the CRC8 value.
-  """
-  crc = 0
-  for byte in six.iterbytes(data):
-    crc ^= (byte << 8)
-    for _ in range(8):
-      if crc & 0x8000:
-        crc ^= (0x1070 << 3)
-      crc <<= 1
-  return crc >> 8
+    StartLoop checks to see if there are any commands to process, processing them
+    if any, and forwards EC output to the user.
 
+    When sending a command to the EC, we send the command once and check the
+    response to see if the EC encountered an error when receiving the command.  An
+    error condition is reported to the interpreter by a string with at least one
+    '&' and 'E'.  The full string is actually '&&EE', however it's possible that
+    the leading ampersand or trailing 'E' could be dropped.  If an error is
+    encountered, the interpreter will retry up to the amount configured.
 
-def StartLoop(interp, shutdown_pipe=None):
-  """Starts an infinite loop of servicing the user and the EC.
-
-  StartLoop checks to see if there are any commands to process, processing them
-  if any, and forwards EC output to the user.
-
-  When sending a command to the EC, we send the command once and check the
-  response to see if the EC encountered an error when receiving the command.  An
-  error condition is reported to the interpreter by a string with at least one
-  '&' and 'E'.  The full string is actually '&&EE', however it's possible that
-  the leading ampersand or trailing 'E' could be dropped.  If an error is
-  encountered, the interpreter will retry up to the amount configured.
-
-  Args:
-    interp: An Interpreter object that has been properly initialised.
-    shutdown_pipe: A file object for a pipe or equivalent that becomes readable
-      (not blocked) to indicate that the loop should exit.  Can be None to never
-      exit the loop.
-  """
-  try:
-    # This is used instead of "break" to avoid exiting the loop in the middle of
-    # an iteration.
-    continue_looping = True
-
-    while continue_looping:
-      # The inputs list is created anew in each loop iteration because the
-      # Interpreter class sometimes modifies the interp.inputs list.
-      if shutdown_pipe is None:
-        inputs = interp.inputs
-      else:
-        inputs = list(interp.inputs)
-        inputs.append(shutdown_pipe)
-
-      readable, writeable, _ = select.select(inputs, interp.outputs, [])
-
-      for obj in readable:
-        # Handle any debug prints from the EC.
-        if obj is interp.ec_uart_pty:
-          interp.HandleECData()
-
-        # Handle any commands from the user.
-        elif obj is interp.cmd_pipe:
-          try:
-            interp.HandleUserData()
-          except EOFError:
-            interp.logger.debug(
-                'ec3po interpreter received EOF from cmd_pipe in '
-                'HandleUserData()')
-            continue_looping = False
-
-        elif obj is shutdown_pipe:
-          interp.logger.debug(
-              'ec3po interpreter received shutdown pipe unblocked notification')
-          continue_looping = False
-
-      for obj in writeable:
-        # Send a command to the EC.
-        if obj is interp.ec_uart_pty:
-          interp.SendCmdToEC()
-
-  except KeyboardInterrupt:
-    pass
-
-  finally:
-    interp.cmd_pipe.close()
-    interp.dbg_pipe.close()
-    interp.ec_uart_pty.close()
-    if shutdown_pipe is not None:
-      shutdown_pipe.close()
-    interp.logger.debug('Exit ec3po interpreter loop for %s',
-                        interp.ec_uart_pty_name)
+    Args:
+      interp: An Interpreter object that has been properly initialised.
+      shutdown_pipe: A file object for a pipe or equivalent that becomes readable
+        (not blocked) to indicate that the loop should exit.  Can be None to never
+        exit the loop.
+    """
+    try:
+        # This is used instead of "break" to avoid exiting the loop in the middle of
+        # an iteration.
+        continue_looping = True
+
+        while continue_looping:
+            # The inputs list is created anew in each loop iteration because the
+            # Interpreter class sometimes modifies the interp.inputs list.
+            if shutdown_pipe is None:
+                inputs = interp.inputs
+            else:
+                inputs = list(interp.inputs)
+                inputs.append(shutdown_pipe)
+
+            readable, writeable, _ = select.select(inputs, interp.outputs, [])
+
+            for obj in readable:
+                # Handle any debug prints from the EC.
+                if obj is interp.ec_uart_pty:
+                    interp.HandleECData()
+
+                # Handle any commands from the user.
+                elif obj is interp.cmd_pipe:
+                    try:
+                        interp.HandleUserData()
+                    except EOFError:
+                        interp.logger.debug(
+                            "ec3po interpreter received EOF from cmd_pipe in "
+                            "HandleUserData()"
+                        )
+                        continue_looping = False
+
+                elif obj is shutdown_pipe:
+                    interp.logger.debug(
+                        "ec3po interpreter received shutdown pipe unblocked notification"
+                    )
+                    continue_looping = False
+
+            for obj in writeable:
+                # Send a command to the EC.
+                if obj is interp.ec_uart_pty:
+                    interp.SendCmdToEC()
+
+    except KeyboardInterrupt:
+        pass
+
+    finally:
+        interp.cmd_pipe.close()
+        interp.dbg_pipe.close()
+        interp.ec_uart_pty.close()
+        if shutdown_pipe is not None:
+            shutdown_pipe.close()
+        interp.logger.debug(
+            "Exit ec3po interpreter loop for %s", interp.ec_uart_pty_name
+        )
diff --git a/util/ec3po/interpreter_unittest.py b/util/ec3po/interpreter_unittest.py
index bd328496f9..a6bfd3baec 100755
--- a/util/ec3po/interpreter_unittest.py
+++ b/util/ec3po/interpreter_unittest.py
@@ -1,5 +1,5 @@
 #!/usr/bin/env python
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -9,373 +9,411 @@
 
 from __future__ import print_function
 
-# pylint: disable=cros-logging-import
 import logging
-import mock
 import tempfile
 import unittest
 
+from ec3po import interpreter
+from ec3po import threadproc_shim
+import mock  # pylint:disable=import-error
 import six
 
-import interpreter
-import threadproc_shim
-
 
 def GetBuiltins(func):
-  if six.PY2:
-    return '__builtin__.' + func
-  return 'builtins.' + func
+    if six.PY2:
+        return "__builtin__." + func
+    return "builtins." + func
 
 
 class TestEnhancedECBehaviour(unittest.TestCase):
-  """Test case to verify all enhanced EC interpretation tasks."""
-  def setUp(self):
-    """Setup the test harness."""
-    # Setup logging with a timestamp, the module, and the log level.
-    logging.basicConfig(level=logging.DEBUG,
-                        format=('%(asctime)s - %(module)s -'
-                                ' %(levelname)s - %(message)s'))
-
-    # Create a tempfile that would represent the EC UART PTY.
-    self.tempfile = tempfile.NamedTemporaryFile()
-
-    # Create the pipes that the interpreter will use.
-    self.cmd_pipe_user, self.cmd_pipe_itpr = threadproc_shim.Pipe()
-    self.dbg_pipe_user, self.dbg_pipe_itpr = threadproc_shim.Pipe(duplex=False)
-
-    # Mock the open() function so we can inspect reads/writes to the EC.
-    self.ec_uart_pty = mock.mock_open()
-
-    with mock.patch(GetBuiltins('open'), self.ec_uart_pty):
-      # Create an interpreter.
-      self.itpr = interpreter.Interpreter(self.tempfile.name,
-                                          self.cmd_pipe_itpr,
-                                          self.dbg_pipe_itpr,
-                                          log_level=logging.DEBUG,
-                                          name="EC")
-
-  @mock.patch('interpreter.os')
-  def test_HandlingCommandsThatProduceNoOutput(self, mock_os):
-    """Verify that the Interpreter correctly handles non-output commands.
-
-    Args:
-      mock_os: MagicMock object replacing the 'os' module for this test
-        case.
-    """
-    # The interpreter init should open the EC UART PTY.
-    expected_ec_calls = [mock.call(self.tempfile.name, 'ab+')]
-    # Have a command come in the command pipe.  The first command will be an
-    # interrogation to determine if the EC is enhanced or not.
-    self.cmd_pipe_user.send(interpreter.EC_SYN)
-    self.itpr.HandleUserData()
-    # At this point, the command should be queued up waiting to be sent, so
-    # let's actually send it to the EC.
-    self.itpr.SendCmdToEC()
-    expected_ec_calls.extend([mock.call().write(interpreter.EC_SYN),
-                              mock.call().flush()])
-    # Now, assume that the EC sends only 1 response back of EC_ACK.
-    mock_os.read.side_effect = [interpreter.EC_ACK]
-    # When reading the EC, the interpreter will call file.fileno() to pass to
-    # os.read().
-    expected_ec_calls.append(mock.call().fileno())
-    # Simulate the response.
-    self.itpr.HandleECData()
-
-    # Now that the interrogation was complete, it's time to send down the real
-    # command.
-    test_cmd = b'chan save'
-    # Send the test command down the pipe.
-    self.cmd_pipe_user.send(test_cmd)
-    self.itpr.HandleUserData()
-    self.itpr.SendCmdToEC()
-    # Since the EC image is enhanced, we should have sent a packed command.
-    expected_ec_calls.append(mock.call().write(self.itpr.PackCommand(test_cmd)))
-    expected_ec_calls.append(mock.call().flush())
-
-    # Now that the first command was sent, we should send another command which
-    # produces no output.  The console would send another interrogation.
-    self.cmd_pipe_user.send(interpreter.EC_SYN)
-    self.itpr.HandleUserData()
-    self.itpr.SendCmdToEC()
-    expected_ec_calls.extend([mock.call().write(interpreter.EC_SYN),
-                              mock.call().flush()])
-    # Again, assume that the EC sends only 1 response back of EC_ACK.
-    mock_os.read.side_effect = [interpreter.EC_ACK]
-    # When reading the EC, the interpreter will call file.fileno() to pass to
-    # os.read().
-    expected_ec_calls.append(mock.call().fileno())
-    # Simulate the response.
-    self.itpr.HandleECData()
-
-    # Now send the second test command.
-    test_cmd = b'chan 0'
-    self.cmd_pipe_user.send(test_cmd)
-    self.itpr.HandleUserData()
-    self.itpr.SendCmdToEC()
-    # Since the EC image is enhanced, we should have sent a packed command.
-    expected_ec_calls.append(mock.call().write(self.itpr.PackCommand(test_cmd)))
-    expected_ec_calls.append(mock.call().flush())
-
-    # Finally, verify that the appropriate writes were actually sent to the EC.
-    self.ec_uart_pty.assert_has_calls(expected_ec_calls)
-
-  @mock.patch('interpreter.os')
-  def test_CommandRetryingOnError(self, mock_os):
-    """Verify that commands are retried if an error is encountered.
-
-    Args:
-      mock_os: MagicMock object replacing the 'os' module for this test
-        case.
-    """
-    # The interpreter init should open the EC UART PTY.
-    expected_ec_calls = [mock.call(self.tempfile.name, 'ab+')]
-    # Have a command come in the command pipe.  The first command will be an
-    # interrogation to determine if the EC is enhanced or not.
-    self.cmd_pipe_user.send(interpreter.EC_SYN)
-    self.itpr.HandleUserData()
-    # At this point, the command should be queued up waiting to be sent, so
-    # let's actually send it to the EC.
-    self.itpr.SendCmdToEC()
-    expected_ec_calls.extend([mock.call().write(interpreter.EC_SYN),
-                              mock.call().flush()])
-    # Now, assume that the EC sends only 1 response back of EC_ACK.
-    mock_os.read.side_effect = [interpreter.EC_ACK]
-    # When reading the EC, the interpreter will call file.fileno() to pass to
-    # os.read().
-    expected_ec_calls.append(mock.call().fileno())
-    # Simulate the response.
-    self.itpr.HandleECData()
-
-    # Let's send a command that is received on the EC-side with an error.
-    test_cmd = b'accelinfo'
-    self.cmd_pipe_user.send(test_cmd)
-    self.itpr.HandleUserData()
-    self.itpr.SendCmdToEC()
-    packed_cmd = self.itpr.PackCommand(test_cmd)
-    expected_ec_calls.extend([mock.call().write(packed_cmd),
-                              mock.call().flush()])
-    # Have the EC return the error string twice.
-    mock_os.read.side_effect = [b'&&EE', b'&&EE']
-    for i in range(2):
-      # When reading the EC, the interpreter will call file.fileno() to pass to
-      # os.read().
-      expected_ec_calls.append(mock.call().fileno())
-      # Simulate the response.
-      self.itpr.HandleECData()
-
-      # Since an error was received, the EC should attempt to retry the command.
-      expected_ec_calls.extend([mock.call().write(packed_cmd),
-                                mock.call().flush()])
-      # Verify that the retry count was decremented.
-      self.assertEqual(interpreter.COMMAND_RETRIES-i-1, self.itpr.cmd_retries,
-                       'Unexpected cmd_remaining count.')
-      # Actually retry the command.
-      self.itpr.SendCmdToEC()
-
-    # Now assume that the last one goes through with no trouble.
-    expected_ec_calls.extend([mock.call().write(packed_cmd),
-                              mock.call().flush()])
-    self.itpr.SendCmdToEC()
-
-    # Verify all the calls.
-    self.ec_uart_pty.assert_has_calls(expected_ec_calls)
-
-  def test_PackCommandsForEnhancedEC(self):
-    """Verify that the interpreter packs commands for enhanced EC images."""
-    # Assume current EC image is enhanced.
-    self.itpr.enhanced_ec = True
-    # Receive a command from the user.
-    test_cmd = b'gettime'
-    self.cmd_pipe_user.send(test_cmd)
-    # Mock out PackCommand to see if it was called.
-    self.itpr.PackCommand = mock.MagicMock()
-    # Have the interpreter handle the command.
-    self.itpr.HandleUserData()
-    # Verify that PackCommand() was called.
-    self.itpr.PackCommand.assert_called_once_with(test_cmd)
-
-  def test_DontPackCommandsForNonEnhancedEC(self):
-    """Verify the interpreter doesn't pack commands for non-enhanced images."""
-    # Assume current EC image is not enhanced.
-    self.itpr.enhanced_ec = False
-    # Receive a command from the user.
-    test_cmd = b'gettime'
-    self.cmd_pipe_user.send(test_cmd)
-    # Mock out PackCommand to see if it was called.
-    self.itpr.PackCommand = mock.MagicMock()
-    # Have the interpreter handle the command.
-    self.itpr.HandleUserData()
-    # Verify that PackCommand() was called.
-    self.itpr.PackCommand.assert_not_called()
-
-  @mock.patch('interpreter.os')
-  def test_KeepingTrackOfInterrogation(self, mock_os):
-    """Verify that the interpreter can track the state of the interrogation.
-
-    Args:
-      mock_os: MagicMock object replacing the 'os' module. for this test
-        case.
-    """
-    # Upon init, the interpreter should assume that the current EC image is not
-    # enhanced.
-    self.assertFalse(self.itpr.enhanced_ec, msg=('State of enhanced_ec upon'
-                                                 ' init is not False.'))
-
-    # Assume an interrogation request comes in from the user.
-    self.cmd_pipe_user.send(interpreter.EC_SYN)
-    self.itpr.HandleUserData()
-
-    # Verify the state is now within an interrogation.
-    self.assertTrue(self.itpr.interrogating, 'interrogating should be True')
-    # The state of enhanced_ec should not be changed yet because we haven't
-    # received a valid response yet.
-    self.assertFalse(self.itpr.enhanced_ec, msg=('State of enhanced_ec is '
-                                                 'not False.'))
-
-    # Assume that the EC responds with an EC_ACK.
-    mock_os.read.side_effect = [interpreter.EC_ACK]
-    self.itpr.HandleECData()
-
-    # Now, the interrogation should be complete and we should know that the
-    # current EC image is enhanced.
-    self.assertFalse(self.itpr.interrogating, msg=('interrogating should be '
-                                                   'False'))
-    self.assertTrue(self.itpr.enhanced_ec, msg='enhanced_ec sholud be True')
-
-    # Now let's perform another interrogation, but pretend that the EC ignores
-    # it.
-    self.cmd_pipe_user.send(interpreter.EC_SYN)
-    self.itpr.HandleUserData()
-
-    # Verify interrogating state.
-    self.assertTrue(self.itpr.interrogating, 'interrogating sholud be True')
-    # We should assume that the image is not enhanced until we get the valid
-    # response.
-    self.assertFalse(self.itpr.enhanced_ec, 'enhanced_ec should be False now.')
-
-    # Let's pretend that we get a random debug print.  This should clear the
-    # interrogating flag.
-    mock_os.read.side_effect = [b'[1660.593076 HC 0x103]']
-    self.itpr.HandleECData()
-
-    # Verify that interrogating flag is cleared and enhanced_ec is still False.
-    self.assertFalse(self.itpr.interrogating, 'interrogating should be False.')
-    self.assertFalse(self.itpr.enhanced_ec,
-                     'enhanced_ec should still be False.')
+    """Test case to verify all enhanced EC interpretation tasks."""
+
+    def setUp(self):
+        """Setup the test harness."""
+        # Setup logging with a timestamp, the module, and the log level.
+        logging.basicConfig(
+            level=logging.DEBUG,
+            format=("%(asctime)s - %(module)s - %(levelname)s - %(message)s"),
+        )
+
+        # Create a tempfile that would represent the EC UART PTY.
+        self.tempfile = tempfile.NamedTemporaryFile()
+
+        # Create the pipes that the interpreter will use.
+        self.cmd_pipe_user, self.cmd_pipe_itpr = threadproc_shim.Pipe()
+        self.dbg_pipe_user, self.dbg_pipe_itpr = threadproc_shim.Pipe(
+            duplex=False
+        )
+
+        # Mock the open() function so we can inspect reads/writes to the EC.
+        self.ec_uart_pty = mock.mock_open()
+
+        with mock.patch(GetBuiltins("open"), self.ec_uart_pty):
+            # Create an interpreter.
+            self.itpr = interpreter.Interpreter(
+                self.tempfile.name,
+                self.cmd_pipe_itpr,
+                self.dbg_pipe_itpr,
+                log_level=logging.DEBUG,
+                name="EC",
+            )
+
+    @mock.patch("ec3po.interpreter.os")
+    def test_HandlingCommandsThatProduceNoOutput(self, mock_os):
+        """Verify that the Interpreter correctly handles non-output commands.
+
+        Args:
+          mock_os: MagicMock object replacing the 'os' module for this test
+            case.
+        """
+        # The interpreter init should open the EC UART PTY.
+        expected_ec_calls = [mock.call(self.tempfile.name, "r+b", buffering=0)]
+        # Have a command come in the command pipe.  The first command will be an
+        # interrogation to determine if the EC is enhanced or not.
+        self.cmd_pipe_user.send(interpreter.EC_SYN)
+        self.itpr.HandleUserData()
+        # At this point, the command should be queued up waiting to be sent, so
+        # let's actually send it to the EC.
+        self.itpr.SendCmdToEC()
+        expected_ec_calls.extend(
+            [mock.call().write(interpreter.EC_SYN), mock.call().flush()]
+        )
+        # Now, assume that the EC sends only 1 response back of EC_ACK.
+        mock_os.read.side_effect = [interpreter.EC_ACK]
+        # When reading the EC, the interpreter will call file.fileno() to pass to
+        # os.read().
+        expected_ec_calls.append(mock.call().fileno())
+        # Simulate the response.
+        self.itpr.HandleECData()
+
+        # Now that the interrogation was complete, it's time to send down the real
+        # command.
+        test_cmd = b"chan save"
+        # Send the test command down the pipe.
+        self.cmd_pipe_user.send(test_cmd)
+        self.itpr.HandleUserData()
+        self.itpr.SendCmdToEC()
+        # Since the EC image is enhanced, we should have sent a packed command.
+        expected_ec_calls.append(
+            mock.call().write(self.itpr.PackCommand(test_cmd))
+        )
+        expected_ec_calls.append(mock.call().flush())
+
+        # Now that the first command was sent, we should send another command which
+        # produces no output.  The console would send another interrogation.
+        self.cmd_pipe_user.send(interpreter.EC_SYN)
+        self.itpr.HandleUserData()
+        self.itpr.SendCmdToEC()
+        expected_ec_calls.extend(
+            [mock.call().write(interpreter.EC_SYN), mock.call().flush()]
+        )
+        # Again, assume that the EC sends only 1 response back of EC_ACK.
+        mock_os.read.side_effect = [interpreter.EC_ACK]
+        # When reading the EC, the interpreter will call file.fileno() to pass to
+        # os.read().
+        expected_ec_calls.append(mock.call().fileno())
+        # Simulate the response.
+        self.itpr.HandleECData()
+
+        # Now send the second test command.
+        test_cmd = b"chan 0"
+        self.cmd_pipe_user.send(test_cmd)
+        self.itpr.HandleUserData()
+        self.itpr.SendCmdToEC()
+        # Since the EC image is enhanced, we should have sent a packed command.
+        expected_ec_calls.append(
+            mock.call().write(self.itpr.PackCommand(test_cmd))
+        )
+        expected_ec_calls.append(mock.call().flush())
+
+        # Finally, verify that the appropriate writes were actually sent to the EC.
+        self.ec_uart_pty.assert_has_calls(expected_ec_calls)
+
+    @mock.patch("ec3po.interpreter.os")
+    def test_CommandRetryingOnError(self, mock_os):
+        """Verify that commands are retried if an error is encountered.
+
+        Args:
+          mock_os: MagicMock object replacing the 'os' module for this test
+            case.
+        """
+        # The interpreter init should open the EC UART PTY.
+        expected_ec_calls = [mock.call(self.tempfile.name, "r+b", buffering=0)]
+        # Have a command come in the command pipe.  The first command will be an
+        # interrogation to determine if the EC is enhanced or not.
+        self.cmd_pipe_user.send(interpreter.EC_SYN)
+        self.itpr.HandleUserData()
+        # At this point, the command should be queued up waiting to be sent, so
+        # let's actually send it to the EC.
+        self.itpr.SendCmdToEC()
+        expected_ec_calls.extend(
+            [mock.call().write(interpreter.EC_SYN), mock.call().flush()]
+        )
+        # Now, assume that the EC sends only 1 response back of EC_ACK.
+        mock_os.read.side_effect = [interpreter.EC_ACK]
+        # When reading the EC, the interpreter will call file.fileno() to pass to
+        # os.read().
+        expected_ec_calls.append(mock.call().fileno())
+        # Simulate the response.
+        self.itpr.HandleECData()
+
+        # Let's send a command that is received on the EC-side with an error.
+        test_cmd = b"accelinfo"
+        self.cmd_pipe_user.send(test_cmd)
+        self.itpr.HandleUserData()
+        self.itpr.SendCmdToEC()
+        packed_cmd = self.itpr.PackCommand(test_cmd)
+        expected_ec_calls.extend(
+            [mock.call().write(packed_cmd), mock.call().flush()]
+        )
+        # Have the EC return the error string twice.
+        mock_os.read.side_effect = [b"&&EE", b"&&EE"]
+        for i in range(2):
+            # When reading the EC, the interpreter will call file.fileno() to pass to
+            # os.read().
+            expected_ec_calls.append(mock.call().fileno())
+            # Simulate the response.
+            self.itpr.HandleECData()
+
+            # Since an error was received, the EC should attempt to retry the command.
+            expected_ec_calls.extend(
+                [mock.call().write(packed_cmd), mock.call().flush()]
+            )
+            # Verify that the retry count was decremented.
+            self.assertEqual(
+                interpreter.COMMAND_RETRIES - i - 1,
+                self.itpr.cmd_retries,
+                "Unexpected cmd_remaining count.",
+            )
+            # Actually retry the command.
+            self.itpr.SendCmdToEC()
+
+        # Now assume that the last one goes through with no trouble.
+        expected_ec_calls.extend(
+            [mock.call().write(packed_cmd), mock.call().flush()]
+        )
+        self.itpr.SendCmdToEC()
+
+        # Verify all the calls.
+        self.ec_uart_pty.assert_has_calls(expected_ec_calls)
+
+    def test_PackCommandsForEnhancedEC(self):
+        """Verify that the interpreter packs commands for enhanced EC images."""
+        # Assume current EC image is enhanced.
+        self.itpr.enhanced_ec = True
+        # Receive a command from the user.
+        test_cmd = b"gettime"
+        self.cmd_pipe_user.send(test_cmd)
+        # Mock out PackCommand to see if it was called.
+        self.itpr.PackCommand = mock.MagicMock()
+        # Have the interpreter handle the command.
+        self.itpr.HandleUserData()
+        # Verify that PackCommand() was called.
+        self.itpr.PackCommand.assert_called_once_with(test_cmd)
+
+    def test_DontPackCommandsForNonEnhancedEC(self):
+        """Verify the interpreter doesn't pack commands for non-enhanced images."""
+        # Assume current EC image is not enhanced.
+        self.itpr.enhanced_ec = False
+        # Receive a command from the user.
+        test_cmd = b"gettime"
+        self.cmd_pipe_user.send(test_cmd)
+        # Mock out PackCommand to see if it was called.
+        self.itpr.PackCommand = mock.MagicMock()
+        # Have the interpreter handle the command.
+        self.itpr.HandleUserData()
+        # Verify that PackCommand() was called.
+        self.itpr.PackCommand.assert_not_called()
+
+    @mock.patch("ec3po.interpreter.os")
+    def test_KeepingTrackOfInterrogation(self, mock_os):
+        """Verify that the interpreter can track the state of the interrogation.
+
+        Args:
+          mock_os: MagicMock object replacing the 'os' module. for this test
+            case.
+        """
+        # Upon init, the interpreter should assume that the current EC image is not
+        # enhanced.
+        self.assertFalse(
+            self.itpr.enhanced_ec,
+            msg=("State of enhanced_ec upon init is not False."),
+        )
+
+        # Assume an interrogation request comes in from the user.
+        self.cmd_pipe_user.send(interpreter.EC_SYN)
+        self.itpr.HandleUserData()
+
+        # Verify the state is now within an interrogation.
+        self.assertTrue(self.itpr.interrogating, "interrogating should be True")
+        # The state of enhanced_ec should not be changed yet because we haven't
+        # received a valid response yet.
+        self.assertFalse(
+            self.itpr.enhanced_ec, msg=("State of enhanced_ec is not False.")
+        )
+
+        # Assume that the EC responds with an EC_ACK.
+        mock_os.read.side_effect = [interpreter.EC_ACK]
+        self.itpr.HandleECData()
+
+        # Now, the interrogation should be complete and we should know that the
+        # current EC image is enhanced.
+        self.assertFalse(
+            self.itpr.interrogating, msg=("interrogating should be False")
+        )
+        self.assertTrue(self.itpr.enhanced_ec, msg="enhanced_ec sholud be True")
+
+        # Now let's perform another interrogation, but pretend that the EC ignores
+        # it.
+        self.cmd_pipe_user.send(interpreter.EC_SYN)
+        self.itpr.HandleUserData()
+
+        # Verify interrogating state.
+        self.assertTrue(self.itpr.interrogating, "interrogating sholud be True")
+        # We should assume that the image is not enhanced until we get the valid
+        # response.
+        self.assertFalse(
+            self.itpr.enhanced_ec, "enhanced_ec should be False now."
+        )
+
+        # Let's pretend that we get a random debug print.  This should clear the
+        # interrogating flag.
+        mock_os.read.side_effect = [b"[1660.593076 HC 0x103]"]
+        self.itpr.HandleECData()
+
+        # Verify that interrogating flag is cleared and enhanced_ec is still False.
+        self.assertFalse(
+            self.itpr.interrogating, "interrogating should be False."
+        )
+        self.assertFalse(
+            self.itpr.enhanced_ec, "enhanced_ec should still be False."
+        )
 
 
 class TestUARTDisconnection(unittest.TestCase):
-  """Test case to verify interpreter disconnection/reconnection."""
-  def setUp(self):
-    """Setup the test harness."""
-    # Setup logging with a timestamp, the module, and the log level.
-    logging.basicConfig(level=logging.DEBUG,
-                        format=('%(asctime)s - %(module)s -'
-                                ' %(levelname)s - %(message)s'))
-
-    # Create a tempfile that would represent the EC UART PTY.
-    self.tempfile = tempfile.NamedTemporaryFile()
-
-    # Create the pipes that the interpreter will use.
-    self.cmd_pipe_user, self.cmd_pipe_itpr = threadproc_shim.Pipe()
-    self.dbg_pipe_user, self.dbg_pipe_itpr = threadproc_shim.Pipe(duplex=False)
-
-    # Mock the open() function so we can inspect reads/writes to the EC.
-    self.ec_uart_pty = mock.mock_open()
-
-    with mock.patch(GetBuiltins('open'), self.ec_uart_pty):
-      # Create an interpreter.
-      self.itpr = interpreter.Interpreter(self.tempfile.name,
-                                          self.cmd_pipe_itpr,
-                                          self.dbg_pipe_itpr,
-                                          log_level=logging.DEBUG,
-                                          name="EC")
-
-    # First, check that interpreter is initialized to connected.
-    self.assertTrue(self.itpr.connected, ('The interpreter should be'
-                                          ' initialized in a connected state'))
-
-  def test_DisconnectStopsECTraffic(self):
-    """Verify that when in disconnected state, no debug prints are sent."""
-    # Let's send a disconnect command through the command pipe.
-    self.cmd_pipe_user.send(b'disconnect')
-    self.itpr.HandleUserData()
-
-    # Verify interpreter is disconnected from EC.
-    self.assertFalse(self.itpr.connected, ('The interpreter should be'
-                                           'disconnected.'))
-    # Verify that the EC UART is no longer a member of the inputs.  The
-    # interpreter will never pull data from the EC if it's not a member of the
-    # inputs list.
-    self.assertFalse(self.itpr.ec_uart_pty in self.itpr.inputs)
-
-  def test_CommandsDroppedWhenDisconnected(self):
-    """Verify that when in disconnected state, commands are dropped."""
-    # Send a command, followed by 'disconnect'.
-    self.cmd_pipe_user.send(b'taskinfo')
-    self.itpr.HandleUserData()
-    self.cmd_pipe_user.send(b'disconnect')
-    self.itpr.HandleUserData()
-
-    # Verify interpreter is disconnected from EC.
-    self.assertFalse(self.itpr.connected, ('The interpreter should be'
-                                           'disconnected.'))
-    # Verify that the EC UART is no longer a member of the inputs nor outputs.
-    self.assertFalse(self.itpr.ec_uart_pty in self.itpr.inputs)
-    self.assertFalse(self.itpr.ec_uart_pty in self.itpr.outputs)
-
-    # Have the user send a few more commands in the disconnected state.
-    command = 'help\n'
-    for char in command:
-      self.cmd_pipe_user.send(char.encode('utf-8'))
-      self.itpr.HandleUserData()
-
-    # The command queue should be empty.
-    self.assertEqual(0, self.itpr.ec_cmd_queue.qsize())
-
-    # Now send the reconnect command.
-    self.cmd_pipe_user.send(b'reconnect')
-
-    with mock.patch(GetBuiltins('open'), mock.mock_open()):
-      self.itpr.HandleUserData()
-
-    # Verify interpreter is connected.
-    self.assertTrue(self.itpr.connected)
-    # Verify that EC UART is a member of the inputs.
-    self.assertTrue(self.itpr.ec_uart_pty in self.itpr.inputs)
-    # Since no command was sent after reconnection, verify that the EC UART is
-    # not a member of the outputs.
-    self.assertFalse(self.itpr.ec_uart_pty in self.itpr.outputs)
-
-  def test_ReconnectAllowsECTraffic(self):
-    """Verify that when connected, EC UART traffic is allowed."""
-    # Let's send a disconnect command through the command pipe.
-    self.cmd_pipe_user.send(b'disconnect')
-    self.itpr.HandleUserData()
-
-    # Verify interpreter is disconnected.
-    self.assertFalse(self.itpr.connected, ('The interpreter should be'
-                                           'disconnected.'))
-    # Verify that the EC UART is no longer a member of the inputs nor outputs.
-    self.assertFalse(self.itpr.ec_uart_pty in self.itpr.inputs)
-    self.assertFalse(self.itpr.ec_uart_pty in self.itpr.outputs)
-
-    # Issue reconnect command through the command pipe.
-    self.cmd_pipe_user.send(b'reconnect')
-
-    with mock.patch(GetBuiltins('open'), mock.mock_open()):
-      self.itpr.HandleUserData()
-
-    # Verify interpreter is connected.
-    self.assertTrue(self.itpr.connected, ('The interpreter should be'
-                                          'connected.'))
-    # Verify that the EC UART is now a member of the inputs.
-    self.assertTrue(self.itpr.ec_uart_pty in self.itpr.inputs)
-    # Since we have issued no commands during the disconnected state, no
-    # commands are pending and therefore the PTY should not be added to the
-    # outputs.
-    self.assertFalse(self.itpr.ec_uart_pty in self.itpr.outputs)
-
-
-if __name__ == '__main__':
-  unittest.main()
+    """Test case to verify interpreter disconnection/reconnection."""
+
+    def setUp(self):
+        """Setup the test harness."""
+        # Setup logging with a timestamp, the module, and the log level.
+        logging.basicConfig(
+            level=logging.DEBUG,
+            format=("%(asctime)s - %(module)s - %(levelname)s - %(message)s"),
+        )
+
+        # Create a tempfile that would represent the EC UART PTY.
+        self.tempfile = tempfile.NamedTemporaryFile()
+
+        # Create the pipes that the interpreter will use.
+        self.cmd_pipe_user, self.cmd_pipe_itpr = threadproc_shim.Pipe()
+        self.dbg_pipe_user, self.dbg_pipe_itpr = threadproc_shim.Pipe(
+            duplex=False
+        )
+
+        # Mock the open() function so we can inspect reads/writes to the EC.
+        self.ec_uart_pty = mock.mock_open()
+
+        with mock.patch(GetBuiltins("open"), self.ec_uart_pty):
+            # Create an interpreter.
+            self.itpr = interpreter.Interpreter(
+                self.tempfile.name,
+                self.cmd_pipe_itpr,
+                self.dbg_pipe_itpr,
+                log_level=logging.DEBUG,
+                name="EC",
+            )
+
+        # First, check that interpreter is initialized to connected.
+        self.assertTrue(
+            self.itpr.connected,
+            ("The interpreter should be initialized in a connected state"),
+        )
+
+    def test_DisconnectStopsECTraffic(self):
+        """Verify that when in disconnected state, no debug prints are sent."""
+        # Let's send a disconnect command through the command pipe.
+        self.cmd_pipe_user.send(b"disconnect")
+        self.itpr.HandleUserData()
+
+        # Verify interpreter is disconnected from EC.
+        self.assertFalse(
+            self.itpr.connected, ("The interpreter should be disconnected.")
+        )
+        # Verify that the EC UART is no longer a member of the inputs.  The
+        # interpreter will never pull data from the EC if it's not a member of the
+        # inputs list.
+        self.assertFalse(self.itpr.ec_uart_pty in self.itpr.inputs)
+
+    def test_CommandsDroppedWhenDisconnected(self):
+        """Verify that when in disconnected state, commands are dropped."""
+        # Send a command, followed by 'disconnect'.
+        self.cmd_pipe_user.send(b"taskinfo")
+        self.itpr.HandleUserData()
+        self.cmd_pipe_user.send(b"disconnect")
+        self.itpr.HandleUserData()
+
+        # Verify interpreter is disconnected from EC.
+        self.assertFalse(
+            self.itpr.connected, ("The interpreter should be disconnected.")
+        )
+        # Verify that the EC UART is no longer a member of the inputs nor outputs.
+        self.assertFalse(self.itpr.ec_uart_pty in self.itpr.inputs)
+        self.assertFalse(self.itpr.ec_uart_pty in self.itpr.outputs)
+
+        # Have the user send a few more commands in the disconnected state.
+        command = "help\n"
+        for char in command:
+            self.cmd_pipe_user.send(char.encode("utf-8"))
+            self.itpr.HandleUserData()
+
+        # The command queue should be empty.
+        self.assertEqual(0, self.itpr.ec_cmd_queue.qsize())
+
+        # Now send the reconnect command.
+        self.cmd_pipe_user.send(b"reconnect")
+
+        with mock.patch(GetBuiltins("open"), mock.mock_open()):
+            self.itpr.HandleUserData()
+
+        # Verify interpreter is connected.
+        self.assertTrue(self.itpr.connected)
+        # Verify that EC UART is a member of the inputs.
+        self.assertTrue(self.itpr.ec_uart_pty in self.itpr.inputs)
+        # Since no command was sent after reconnection, verify that the EC UART is
+        # not a member of the outputs.
+        self.assertFalse(self.itpr.ec_uart_pty in self.itpr.outputs)
+
+    def test_ReconnectAllowsECTraffic(self):
+        """Verify that when connected, EC UART traffic is allowed."""
+        # Let's send a disconnect command through the command pipe.
+        self.cmd_pipe_user.send(b"disconnect")
+        self.itpr.HandleUserData()
+
+        # Verify interpreter is disconnected.
+        self.assertFalse(
+            self.itpr.connected, ("The interpreter should be disconnected.")
+        )
+        # Verify that the EC UART is no longer a member of the inputs nor outputs.
+        self.assertFalse(self.itpr.ec_uart_pty in self.itpr.inputs)
+        self.assertFalse(self.itpr.ec_uart_pty in self.itpr.outputs)
+
+        # Issue reconnect command through the command pipe.
+        self.cmd_pipe_user.send(b"reconnect")
+
+        with mock.patch(GetBuiltins("open"), mock.mock_open()):
+            self.itpr.HandleUserData()
+
+        # Verify interpreter is connected.
+        self.assertTrue(
+            self.itpr.connected, ("The interpreter should be connected.")
+        )
+        # Verify that the EC UART is now a member of the inputs.
+        self.assertTrue(self.itpr.ec_uart_pty in self.itpr.inputs)
+        # Since we have issued no commands during the disconnected state, no
+        # commands are pending and therefore the PTY should not be added to the
+        # outputs.
+        self.assertFalse(self.itpr.ec_uart_pty in self.itpr.outputs)
+
+
+if __name__ == "__main__":
+    unittest.main()
diff --git a/util/ec3po/run_tests.sh b/util/ec3po/run_tests.sh
index 09e1a545d0..d61b2b428e 100755
--- a/util/ec3po/run_tests.sh
+++ b/util/ec3po/run_tests.sh
@@ -1,9 +1,15 @@
 #!/bin/bash
 #
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
-# Discover all the unit tests in the ec3po directory and run them.
-python3 -m unittest discover -b -s util/ec3po/ -p "*_unittest.py"  \
-    && touch util/ec3po/.tests-passed
+set -e
+
+my_dir="$(realpath -e -- "$(dirname -- "$0")")"
+parent_dir="$(realpath -e -- "$my_dir/..")"
+
+PYTHONPATH="$parent_dir" python3 -s -m unittest \
+    ec3po.console_unittest \
+    ec3po.interpreter_unittest \
+    && touch -- "$my_dir/.tests-passed"
diff --git a/util/ec3po/threadproc_shim.py b/util/ec3po/threadproc_shim.py
index da5440b1f3..b468de1535 100644
--- a/util/ec3po/threadproc_shim.py
+++ b/util/ec3po/threadproc_shim.py
@@ -1,4 +1,4 @@
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -34,33 +34,35 @@
 
 # Imports to bring objects into this namespace for users of this module.
 from multiprocessing import Pipe
-from six.moves.queue import Queue
 from threading import Thread as ThreadOrProcess
 
+from six.moves.queue import Queue
+
+
 # True if this module has ec3po using subprocesses, False if using threads.
 USING_SUBPROCS = False
 
 
 def _DoNothing():
-  """Do-nothing function for use as a callback with DoIf()."""
+    """Do-nothing function for use as a callback with DoIf()."""
 
 
 def DoIf(subprocs=_DoNothing, threads=_DoNothing):
-  """Return a callback or not based on ec3po use of subprocesses or threads.
+    """Return a callback or not based on ec3po use of subprocesses or threads.
 
-  Args:
-    subprocs: callback that does not require any args - This will be returned
-        (not called!) if and only if ec3po is using subprocesses.  This is
-        OPTIONAL, the default value is a do-nothing callback that returns None.
-    threads: callback that does not require any args - This will be returned
-        (not called!) if and only if ec3po is using threads.  This is OPTIONAL,
-        the default value is a do-nothing callback that returns None.
+    Args:
+      subprocs: callback that does not require any args - This will be returned
+          (not called!) if and only if ec3po is using subprocesses.  This is
+          OPTIONAL, the default value is a do-nothing callback that returns None.
+      threads: callback that does not require any args - This will be returned
+          (not called!) if and only if ec3po is using threads.  This is OPTIONAL,
+          the default value is a do-nothing callback that returns None.
 
-  Returns:
-    Either the subprocs or threads argument will be returned.
-  """
-  return subprocs if USING_SUBPROCS else threads
+    Returns:
+      Either the subprocs or threads argument will be returned.
+    """
+    return subprocs if USING_SUBPROCS else threads
 
 
 def Value(ctype, *args):
-  return ctype(*args)
+    return ctype(*args)
diff --git a/util/ec_flash.c b/util/ec_flash.c
deleted file mode 100644
index 3bae077200..0000000000
--- a/util/ec_flash.c
+++ /dev/null
@@ -1,231 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <errno.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "comm-host.h"
-#include "misc_util.h"
-#include "timer.h"
-
-static const uint32_t ERASE_ASYNC_TIMEOUT = 10 * SECOND;
-static const uint32_t ERASE_ASYNC_WAIT = 500 * MSEC;
-static const int FLASH_ERASE_BUSY_RV = -EECRESULT - EC_RES_BUSY;
-
-int ec_flash_read(uint8_t *buf, int offset, int size)
-{
-	struct ec_params_flash_read p;
-	int rv;
-	int i;
-
-	/* Read data in chunks */
-	for (i = 0; i < size; i += ec_max_insize) {
-		p.offset = offset + i;
-		p.size = MIN(size - i, ec_max_insize);
-		rv = ec_command(EC_CMD_FLASH_READ, 0,
-				&p, sizeof(p), ec_inbuf, p.size);
-		if (rv < 0) {
-			fprintf(stderr, "Read error at offset %d\n", i);
-			return rv;
-		}
-		memcpy(buf + i, ec_inbuf, p.size);
-	}
-
-	return 0;
-}
-
-int ec_flash_verify(const uint8_t *buf, int offset, int size)
-{
-	uint8_t *rbuf = malloc(size);
-	int rv;
-	int i;
-
-	if (!rbuf) {
-		fprintf(stderr, "Unable to allocate buffer.\n");
-		return -1;
-	}
-
-	rv = ec_flash_read(rbuf, offset, size);
-	if (rv < 0) {
-		free(rbuf);
-		return rv;
-	}
-
-	for (i = 0; i < size; i++) {
-		if (buf[i] != rbuf[i]) {
-			fprintf(stderr, "Mismatch at offset 0x%x: "
-				"want 0x%02x, got 0x%02x\n",
-				i, buf[i], rbuf[i]);
-			free(rbuf);
-			return -1;
-		}
-	}
-
-	free(rbuf);
-	return 0;
-}
-
-/**
- * @param info_response  pointer to response that will be filled on success
- * @return Zero or positive on success, negative on failure
- */
-static int get_flash_info_v2(struct ec_response_flash_info_2 *info_response)
-{
-	struct ec_params_flash_info_2 info_params = {
-		/*
-		 * By setting this to zero we indicate that we don't care
-		 * about getting the bank description in the response.
-		 */
-		.num_banks_desc = 0
-	};
-
-	return ec_command(EC_CMD_FLASH_INFO, 2, &info_params,
-			  sizeof(info_params), info_response,
-			  sizeof(*info_response));
-}
-
-/**
- * @param info_response  pointer to response that will be filled on success
- * @return Zero or positive on success, negative on failure
- */
-static int get_flash_info_v0(struct ec_response_flash_info *info_response)
-{
-	return ec_command(EC_CMD_FLASH_INFO, 0, NULL, 0, info_response,
-			  sizeof(*info_response));
-}
-
-/**
- * @return Write size on success, negative on failure
- */
-static int get_flash_write_size(void)
-{
-	int rv = 0;
-	int write_size;
-	int flash_info_version = -1;
-	struct ec_response_flash_info info_response_v0 = { 0 };
-	struct ec_response_flash_info_2 info_response_v2 = { 0 };
-
-	if (ec_cmd_version_supported(EC_CMD_FLASH_INFO, 2))
-		flash_info_version = 2;
-	else if (ec_cmd_version_supported(EC_CMD_FLASH_INFO, 0))
-		flash_info_version = 0;
-
-	if (flash_info_version < 0)
-		return -1;
-
-	if (flash_info_version == 2) {
-		rv = get_flash_info_v2(&info_response_v2);
-		write_size = info_response_v2.write_ideal_size;
-	} else {
-		rv = get_flash_info_v0(&info_response_v0);
-		write_size = info_response_v0.write_block_size;
-	}
-
-	if (rv < 0)
-		return rv;
-
-	return write_size;
-}
-
-int ec_flash_write(const uint8_t *buf, int offset, int size)
-{
-	struct ec_params_flash_write *p =
-		(struct ec_params_flash_write *)ec_outbuf;
-	int write_size;
-	int pdata_max_size = (int)(ec_max_outsize - sizeof(*p));
-	int step;
-	int rv;
-	int i;
-
-	/*
-	 * Determine whether we can use version 1 of the EC_CMD_FLASH_WRITE
-	 * command with more data, or only version 0.
-	 */
-	if (!ec_cmd_version_supported(EC_CMD_FLASH_WRITE, EC_VER_FLASH_WRITE))
-		pdata_max_size = EC_FLASH_WRITE_VER0_SIZE;
-
-	write_size = get_flash_write_size();
-	if (write_size < 0)
-		return write_size;
-
-	/*
-	 * shouldn't ever happen, but report an error rather than a division
-	 * by zero in the next statement.
-	 */
-	if (write_size == 0)
-		return -1;
-
-	step = (pdata_max_size / write_size) * write_size;
-
-	if (!step) {
-		fprintf(stderr, "Write block size %d > max param size %d\n",
-			write_size, pdata_max_size);
-		return -1;
-	}
-
-	/* Write data in chunks */
-	printf("Write size %d...\n", step);
-
-	for (i = 0; i < size; i += step) {
-		p->offset = offset + i;
-		p->size = MIN(size - i, step);
-		memcpy(p + 1, buf + i, p->size);
-		rv = ec_command(EC_CMD_FLASH_WRITE, 0, p, sizeof(*p) + p->size,
-				NULL, 0);
-		if (rv < 0) {
-			fprintf(stderr, "Write error at offset %d\n", i);
-			return rv;
-		}
-	}
-
-	return 0;
-}
-
-int ec_flash_erase(int offset, int size)
-{
-	struct ec_params_flash_erase p;
-
-	p.offset = offset;
-	p.size = size;
-
-	return ec_command(EC_CMD_FLASH_ERASE, 0, &p, sizeof(p), NULL, 0);
-}
-
-int ec_flash_erase_async(int offset, int size)
-{
-	struct ec_params_flash_erase_v1 p = { 0 };
-	uint32_t timeout = 0;
-	int rv = FLASH_ERASE_BUSY_RV;
-
-	p.cmd = FLASH_ERASE_SECTOR_ASYNC;
-	p.params.offset = offset;
-	p.params.size = size;
-
-	rv = ec_command(EC_CMD_FLASH_ERASE, 1, &p, sizeof(p), NULL, 0);
-
-	if (rv < 0)
-		return rv;
-
-	rv = FLASH_ERASE_BUSY_RV;
-
-	while (rv < 0 && timeout < ERASE_ASYNC_TIMEOUT) {
-		/*
-		 * The erase is not complete until FLASH_ERASE_GET_RESULT
-		 * returns success. It's important that we retry even when the
-		 * underlying ioctl returns an error (not just
-		 * FLASH_ERASE_BUSY_RV).
-		 *
-		 * See https://crrev.com/c/511805 for details.
-		 */
-		usleep(ERASE_ASYNC_WAIT);
-		timeout += ERASE_ASYNC_WAIT;
-		p.cmd = FLASH_ERASE_GET_RESULT;
-		rv = ec_command(EC_CMD_FLASH_ERASE, 1, &p, sizeof(p), NULL, 0);
-	}
-	return rv;
-}
diff --git a/util/ec_flash.cc b/util/ec_flash.cc
new file mode 100644
index 0000000000..9bab0a431b
--- /dev/null
+++ b/util/ec_flash.cc
@@ -0,0 +1,238 @@
+/* Copyright 2013 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "comm-host.h"
+#include "misc_util.h"
+#include "timer.h"
+
+#include <errno.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <chrono>
+#include <thread>
+
+static const auto ERASE_ASYNC_TIMEOUT = std::chrono::seconds(10);
+static const auto ERASE_ASYNC_WAIT_MS = std::chrono::milliseconds(500);
+static const int FLASH_ERASE_BUSY_RV = -EECRESULT - EC_RES_BUSY;
+
+int ec_flash_read(uint8_t *buf, int offset, int size)
+{
+	struct ec_params_flash_read p;
+	int rv;
+	int i;
+
+	/* Read data in chunks */
+	for (i = 0; i < size; i += ec_max_insize) {
+		p.offset = offset + i;
+		p.size = MIN(size - i, ec_max_insize);
+		rv = ec_command(EC_CMD_FLASH_READ, 0, &p, sizeof(p), ec_inbuf,
+				p.size);
+		if (rv < 0) {
+			fprintf(stderr, "Read error at offset %d\n", i);
+			return rv;
+		}
+		memcpy(buf + i, ec_inbuf, p.size);
+	}
+
+	return 0;
+}
+
+int ec_flash_verify(const uint8_t *buf, int offset, int size)
+{
+	uint8_t *rbuf = (uint8_t *)(malloc(size));
+	int rv;
+	int i;
+
+	if (!rbuf) {
+		fprintf(stderr, "Unable to allocate buffer.\n");
+		return -1;
+	}
+
+	rv = ec_flash_read(rbuf, offset, size);
+	if (rv < 0) {
+		free(rbuf);
+		return rv;
+	}
+
+	for (i = 0; i < size; i++) {
+		if (buf[i] != rbuf[i]) {
+			fprintf(stderr,
+				"Mismatch at offset 0x%x: "
+				"want 0x%02x, got 0x%02x\n",
+				i, buf[i], rbuf[i]);
+			free(rbuf);
+			return -1;
+		}
+	}
+
+	free(rbuf);
+	return 0;
+}
+
+/**
+ * @param info_response  pointer to response that will be filled on success
+ * @return Zero or positive on success, negative on failure
+ */
+static int get_flash_info_v2(struct ec_response_flash_info_2 *info_response)
+{
+	struct ec_params_flash_info_2 info_params = { /*
+						       * By setting this to zero
+						       * we indicate that we
+						       * don't care about
+						       * getting the bank
+						       * description in the
+						       * response.
+						       */
+						      .num_banks_desc = 0
+	};
+
+	return ec_command(EC_CMD_FLASH_INFO, 2, &info_params,
+			  sizeof(info_params), info_response,
+			  sizeof(*info_response));
+}
+
+/**
+ * @param info_response  pointer to response that will be filled on success
+ * @return Zero or positive on success, negative on failure
+ */
+static int get_flash_info_v0(struct ec_response_flash_info *info_response)
+{
+	return ec_command(EC_CMD_FLASH_INFO, 0, NULL, 0, info_response,
+			  sizeof(*info_response));
+}
+
+/**
+ * @return Write size on success, negative on failure
+ */
+static int get_flash_write_size(void)
+{
+	int rv = 0;
+	int write_size;
+	int flash_info_version = -1;
+	struct ec_response_flash_info info_response_v0 = { 0 };
+	struct ec_response_flash_info_2 info_response_v2 = { 0 };
+
+	if (ec_cmd_version_supported(EC_CMD_FLASH_INFO, 2))
+		flash_info_version = 2;
+	else if (ec_cmd_version_supported(EC_CMD_FLASH_INFO, 0))
+		flash_info_version = 0;
+
+	if (flash_info_version < 0)
+		return -1;
+
+	if (flash_info_version == 2) {
+		rv = get_flash_info_v2(&info_response_v2);
+		write_size = info_response_v2.write_ideal_size;
+	} else {
+		rv = get_flash_info_v0(&info_response_v0);
+		write_size = info_response_v0.write_block_size;
+	}
+
+	if (rv < 0)
+		return rv;
+
+	return write_size;
+}
+
+int ec_flash_write(const uint8_t *buf, int offset, int size)
+{
+	struct ec_params_flash_write *p =
+		(struct ec_params_flash_write *)ec_outbuf;
+	int write_size;
+	int pdata_max_size = (int)(ec_max_outsize - sizeof(*p));
+	int step;
+	int rv;
+	int i;
+
+	/*
+	 * Determine whether we can use version 1 of the EC_CMD_FLASH_WRITE
+	 * command with more data, or only version 0.
+	 */
+	if (!ec_cmd_version_supported(EC_CMD_FLASH_WRITE, EC_VER_FLASH_WRITE))
+		pdata_max_size = EC_FLASH_WRITE_VER0_SIZE;
+
+	write_size = get_flash_write_size();
+	if (write_size < 0)
+		return write_size;
+
+	/*
+	 * shouldn't ever happen, but report an error rather than a division
+	 * by zero in the next statement.
+	 */
+	if (write_size == 0)
+		return -1;
+
+	step = (pdata_max_size / write_size) * write_size;
+
+	if (!step) {
+		fprintf(stderr, "Write block size %d > max param size %d\n",
+			write_size, pdata_max_size);
+		return -1;
+	}
+
+	/* Write data in chunks */
+	printf("Write size %d...\n", step);
+
+	for (i = 0; i < size; i += step) {
+		p->offset = offset + i;
+		p->size = MIN(size - i, step);
+		memcpy(p + 1, buf + i, p->size);
+		rv = ec_command(EC_CMD_FLASH_WRITE, 0, p, sizeof(*p) + p->size,
+				NULL, 0);
+		if (rv < 0) {
+			fprintf(stderr, "Write error at offset %d\n", i);
+			return rv;
+		}
+	}
+
+	return 0;
+}
+
+int ec_flash_erase(int offset, int size)
+{
+	struct ec_params_flash_erase p;
+
+	p.offset = offset;
+	p.size = size;
+
+	return ec_command(EC_CMD_FLASH_ERASE, 0, &p, sizeof(p), NULL, 0);
+}
+
+int ec_flash_erase_async(int offset, int size)
+{
+	struct ec_params_flash_erase_v1 p = { 0 };
+	auto timeout = std::chrono::milliseconds(0);
+	int rv = FLASH_ERASE_BUSY_RV;
+
+	p.cmd = FLASH_ERASE_SECTOR_ASYNC;
+	p.params.offset = offset;
+	p.params.size = size;
+
+	rv = ec_command(EC_CMD_FLASH_ERASE, 1, &p, sizeof(p), NULL, 0);
+
+	if (rv < 0)
+		return rv;
+
+	rv = FLASH_ERASE_BUSY_RV;
+
+	while (rv < 0 && timeout < ERASE_ASYNC_TIMEOUT) {
+		/*
+		 * The erase is not complete until FLASH_ERASE_GET_RESULT
+		 * returns success. It's important that we retry even when the
+		 * underlying ioctl returns an error (not just
+		 * FLASH_ERASE_BUSY_RV).
+		 *
+		 * See https://crrev.com/c/511805 for details.
+		 */
+		std::this_thread::sleep_for(ERASE_ASYNC_WAIT_MS);
+		timeout += ERASE_ASYNC_WAIT_MS;
+		p.cmd = FLASH_ERASE_GET_RESULT;
+		rv = ec_command(EC_CMD_FLASH_ERASE, 1, &p, sizeof(p), NULL, 0);
+	}
+	return rv;
+}
diff --git a/util/ec_flash.h b/util/ec_flash.h
index f4aea3b7a3..179df1979b 100644
--- a/util/ec_flash.h
+++ b/util/ec_flash.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/util/ec_openocd.py b/util/ec_openocd.py
new file mode 100755
index 0000000000..b8c9364bd8
--- /dev/null
+++ b/util/ec_openocd.py
@@ -0,0 +1,308 @@
+#!/usr/bin/env python3
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""
+Flashes and debugs the EC through openocd
+"""
+
+import argparse
+import dataclasses
+import distutils.spawn
+import os
+import pathlib
+import signal
+import socket
+import subprocess
+import sys
+import time
+
+
+EC_BASE = pathlib.Path(__file__).parent.parent
+
+# GDB variant to use if the board specific one is not found
+FALLBACK_GDB_VARIANT = "gdb-multiarch"
+
+
+@dataclasses.dataclass
+class BoardInfo:
+    """Holds the board specific parameters."""
+
+    gdb_variant: str
+    num_breakpoints: int
+    num_watchpoints: int
+
+
+# Debuggers for each board, OpenOCD currently only supports GDB
+boards = {
+    "rex": BoardInfo("arm-none-eabi-gdb", 6, 4),
+    "skyrim": BoardInfo("arm-none-eabi-gdb", 6, 4),
+}
+
+
+def create_openocd_args(interface, board):
+    """Return a list of arguments for initializing OpenOCD."""
+    if not board in boards:
+        raise RuntimeError(f"Unsupported board {board}")
+
+    args = [
+        "openocd",
+        "-f",
+        f"interface/{interface}.cfg",
+        "-c",
+        f"add_script_search_dir {EC_BASE}/util/openocd",
+        "-f",
+        f"board/{board}.cfg",
+    ]
+
+    return args
+
+
+def create_gdb_args(board, port, executable, attach):
+    """Return a list of arguments for initializing GDB."""
+    if not board in boards:
+        raise RuntimeError(f"Unsupported board {board}")
+
+    board_info = boards[board]
+
+    if distutils.spawn.find_executable(board_info.gdb_variant):
+        gdb_path = board_info.gdb_variant
+    elif distutils.spawn.find_executable(FALLBACK_GDB_VARIANT):
+        print(
+            f"GDB executable {board_info.gdb_variant} not found, "
+            f"using {FALLBACK_GDB_VARIANT} instead"
+        )
+        gdb_path = FALLBACK_GDB_VARIANT
+    else:
+        raise RuntimeError("No GDB executable found in the system")
+
+    args = [
+        gdb_path,
+        executable,
+        # GDB can't autodetect these according to OpenOCD
+        "-ex",
+        f"set remote hardware-breakpoint-limit {board_info.num_breakpoints}",
+        "-ex",
+        f"set remote hardware-watchpoint-limit {board_info.num_watchpoints}",
+        # Connect to OpenOCD
+        "-ex",
+        f"target extended-remote localhost:{port}",
+    ]
+
+    if not attach:
+        args.extend(["-ex", "load"])
+
+    return args
+
+
+def flash(interface, board, image, verify):
+    """Run openocd to flash the specified image file."""
+    print(f"Flashing image {image}")
+    # Run OpenOCD and pipe its output to stdout
+    # OpenOCD will shutdown after the flashing is completed
+    args = create_openocd_args(interface, board)
+    args += ["-c", f'init; flash_target "{image}" {int(verify)}; shutdown']
+
+    subprocess.run(
+        args, stdout=sys.stdout, stderr=subprocess.STDOUT, check=True
+    )
+
+
+def debug(interface, board, port, executable, attach):
+    """Start OpenOCD and connect GDB to it."""
+    # Start OpenOCD in the background
+    openocd_args = create_openocd_args(interface, board)
+    openocd_args += ["-c", f"gdb_port {port}"]
+    openocd_out = ""
+
+    with subprocess.Popen(  # pylint: disable=subprocess-popen-preexec-fn
+        openocd_args,
+        encoding="utf-8",
+        stdout=subprocess.PIPE,
+        stderr=subprocess.STDOUT,
+        preexec_fn=os.setsid,
+    ) as openocd:
+        # Wait for OpenOCD to start, it'll open a port for GDB connections
+        sock = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
+        connected = False
+        for _ in range(0, 10):
+            print("Waiting for OpenOCD to start...")
+            connected = sock.connect_ex(("localhost", port))
+            if connected:
+                break
+
+            time.sleep(1000)
+
+        if not connected:
+            print(f"Failed to connect to OpenOCD on port {port}")
+            return
+
+        sock.close()
+
+        old_sigint = signal.signal(signal.SIGINT, signal.SIG_IGN)
+
+        # Start GDB
+        gdb_args = create_gdb_args(board, port, executable, attach)
+        with subprocess.Popen(
+            gdb_args,
+            stdout=sys.stdout,
+            stderr=subprocess.STDOUT,
+            stdin=sys.stdin,
+        ) as gdb:
+            while gdb.poll() is None and openocd.poll() is None:
+                (output, _) = openocd.communicate()
+                openocd_out += output
+
+        signal.signal(signal.SIGINT, old_sigint)
+
+        # Wait for OpenOCD to shutdown
+        print("Waiting for OpenOCD to finish...")
+        if openocd.poll() is None:
+            try:
+                # Read the last bit of stdout
+                (output, _) = openocd.communicate(timeout=3)
+                openocd_out += output
+            except subprocess.TimeoutExpired:
+                # OpenOCD didn't shutdown, kill it
+                openocd.kill()
+
+        if openocd.returncode != 0:
+            print("OpenOCD failed to shutdown cleanly: ")
+    print(openocd_out)
+
+
+def debug_external(board, port, executable, attach):
+    """Run GDB against an external gdbserver."""
+    gdb_args = create_gdb_args(board, port, executable, attach)
+
+    old_sigint = signal.signal(signal.SIGINT, signal.SIG_IGN)
+
+    subprocess.run(
+        gdb_args,
+        stdout=sys.stdout,
+        stderr=subprocess.STDOUT,
+        stdin=sys.stdin,
+        check=True,
+    )
+
+    signal.signal(signal.SIGINT, old_sigint)
+
+
+def get_flash_file(board):
+    """Returns the path of the main output file for the board."""
+    return (
+        EC_BASE / "build" / "zephyr" / board / "output" / "ec.bin"
+    ).resolve()
+
+
+def get_executable_file(board):
+    """Returns the path of the main RO executable file for the board."""
+    return (
+        EC_BASE / "build" / "zephyr" / board / "output" / "zephyr.ro.elf"
+    ).resolve()
+
+
+def main():
+    """Main function."""
+    parser = argparse.ArgumentParser()
+    parser.add_argument(
+        "--board",
+        "-b",
+        choices=boards.keys(),
+        required=True,
+    )
+
+    parser.add_argument(
+        "--interface",
+        "-i",
+        default="jlink",
+        help="The JTAG interface to use",
+    )
+
+    parser.add_argument(
+        "--file",
+        "-f",
+        type=pathlib.Path,
+        default=None,
+        help="The file to use, see each sub-command for what the file is used for",
+    )
+
+    sub_parsers = parser.add_subparsers(help="sub-command -h for specific help")
+    flash_parser = sub_parsers.add_parser(
+        "flash",
+        help="Flashes an image to the target EC, \
+        FILE selects the image to flash, defaults to the zephyr image",
+    )
+    flash_parser.set_defaults(command="flash")
+    flash_parser.add_argument(
+        "--no-verify",
+        "-n",
+        action="store_true",
+        help="Do not verify flash after writing image",
+    )
+
+    debug_parser = sub_parsers.add_parser(
+        "debug",
+        help="Debugs the target EC through GDB, FILE selects the executable to \
+              load debug info from, defaults to using the zephyr RO executable",
+    )
+    debug_parser.set_defaults(command="debug")
+    debug_parser.add_argument(
+        "--port",
+        "-p",
+        help="The port for GDB to connect to",
+        type=int,
+        default=3333,
+    )
+    debug_parser.add_argument(
+        "--external-gdbserver",
+        "-x",
+        help="Do not run openocd, use an already running external gdb server",
+        action="store_true",
+    )
+    debug_parser.add_argument(
+        "--attach",
+        "-a",
+        help="Do not load the binary after starting gdb, attach to the running instance instead",
+        action="store_true",
+    )
+
+    args = parser.parse_args()
+    # Get the image path if we were given one
+    target_file = None
+    if args.file is not None:
+        target_file = args.file.resolve()
+
+    if args.command == "flash":
+        image_file = (
+            get_flash_file(args.board) if target_file is None else target_file
+        )
+        flash(args.interface, args.board, image_file, not args.no_verify)
+    elif args.command == "debug":
+        executable_file = (
+            get_executable_file(args.board)
+            if target_file is None
+            else target_file
+        )
+        if args.external_gdbserver:
+            debug_external(
+                args.board,
+                args.port,
+                executable_file,
+                args.attach,
+            )
+        else:
+            debug(
+                args.interface,
+                args.board,
+                args.port,
+                executable_file,
+                args.attach,
+            )
+    else:
+        parser.print_usage()
+
+
+if __name__ == "__main__":
+    main()
diff --git a/util/ec_panicinfo.c b/util/ec_panicinfo.c
deleted file mode 100644
index f614770619..0000000000
--- a/util/ec_panicinfo.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <stdint.h>
-#include <stdio.h>
-#include "compile_time_macros.h"
-#include "ec_panicinfo.h"
-
-static void print_panic_reg(int regnum, const uint32_t *regs, int index)
-{
-	static const char * const regname[] = {
-		"r0 ", "r1 ", "r2 ", "r3 ", "r4 ",
-		"r5 ", "r6 ", "r7 ", "r8 ", "r9 ",
-		"r10", "r11", "r12", "sp ", "lr ",
-		"pc "};
-
-	printf("%s:", regname[regnum]);
-	if (regs)
-		printf("%08x", regs[index]);
-	else
-		printf("        ");
-	printf((regnum & 3) == 3 ? "\n" : " ");
-}
-
-static int parse_panic_info_cm(const struct panic_data *pdata)
-{
-	const uint32_t *lregs = pdata->cm.regs;
-	const uint32_t *sregs = NULL;
-	enum {
-		ORIG_UNKNOWN = 0,
-		ORIG_PROCESS,
-		ORIG_HANDLER
-	} origin = ORIG_UNKNOWN;
-	int i;
-	const char *panic_origins[3] = {"", "PROCESS", "HANDLER"};
-
-	printf("Saved panic data:%s\n",
-	       (pdata->flags & PANIC_DATA_FLAG_OLD_HOSTCMD ? "" : " (NEW)"));
-
-	if (pdata->struct_version == 2)
-		origin = ((lregs[11] & 0xf) == 1 || (lregs[11] & 0xf) == 9) ?
-			 ORIG_HANDLER : ORIG_PROCESS;
-
-	/*
-	 * In pdata struct, 'regs', which is allocated before 'frame', has
-	 * one less elements in version 1. Therefore, if the data is from
-	 * version 1, shift 'sregs' by one element to align with 'frame' in
-	 * version 1.
-	 */
-	if (pdata->flags & PANIC_DATA_FLAG_FRAME_VALID)
-		sregs = pdata->cm.frame - (pdata->struct_version == 1 ? 1 : 0);
-
-	printf("=== %s EXCEPTION: %02x ====== xPSR: %08x ===\n",
-	       panic_origins[origin],
-	       lregs[1] & 0xff, sregs ? sregs[7] : -1);
-	for (i = 0; i < 4; ++i)
-		print_panic_reg(i, sregs, i);
-	for (i = 4; i < 10; ++i)
-		print_panic_reg(i, lregs, i - 1);
-	print_panic_reg(10, lregs, 9);
-	print_panic_reg(11, lregs, 10);
-	print_panic_reg(12, sregs, 4);
-	print_panic_reg(13, lregs, origin == ORIG_HANDLER ? 2 : 0);
-	print_panic_reg(14, sregs, 5);
-	print_panic_reg(15, sregs, 6);
-
-	return 0;
-}
-
-static int parse_panic_info_nds32(const struct panic_data *pdata)
-{
-	const uint32_t *regs = pdata->nds_n8.regs;
-	uint32_t itype = pdata->nds_n8.itype;
-	uint32_t ipc = pdata->nds_n8.ipc;
-	uint32_t ipsw = pdata->nds_n8.ipsw;
-
-	printf("Saved panic data:%s\n",
-	       (pdata->flags & PANIC_DATA_FLAG_OLD_HOSTCMD ? "" : " (NEW)"));
-
-	printf("=== EXCEP: ITYPE=%x ===\n", itype);
-	printf("R0  %08x R1  %08x R2  %08x R3  %08x\n",
-		     regs[0], regs[1], regs[2], regs[3]);
-	printf("R4  %08x R5  %08x R6  %08x R7  %08x\n",
-		     regs[4], regs[5], regs[6], regs[7]);
-	printf("R8  %08x R9  %08x R10 %08x R15 %08x\n",
-		     regs[8], regs[9], regs[10], regs[11]);
-	printf("FP  %08x GP  %08x LP  %08x SP  %08x\n",
-		     regs[12], regs[13], regs[14], regs[15]);
-	printf("IPC %08x IPSW   %05x\n", ipc, ipsw);
-	printf("SWID of ITYPE: %x\n", ((itype >> 16) & 0x7fff));
-
-	return 0;
-}
-
-int parse_panic_info(const struct panic_data *pdata)
-{
-	/*
-	 * We only understand panic data with version <= 2. Warn the user
-	 * of higher versions.
-	 */
-	if (pdata->struct_version > 2)
-		fprintf(stderr,
-			"Unknown panic data version (%d). "
-			"Following data may be incorrect!\n",
-			pdata->struct_version);
-
-	/* Validate magic number */
-	if (pdata->magic != PANIC_DATA_MAGIC)
-		fprintf(stderr,
-			"Incorrect panic magic (%d). "
-			"Following data may be incorrect!\n",
-			pdata->magic);
-
-	switch (pdata->arch) {
-	case PANIC_ARCH_CORTEX_M:
-		return parse_panic_info_cm(pdata);
-	case PANIC_ARCH_NDS32_N8:
-		return parse_panic_info_nds32(pdata);
-	default:
-		fprintf(stderr, "Unknown architecture (%d).\n", pdata->arch);
-		break;
-	}
-	return -1;
-}
diff --git a/util/ec_panicinfo.h b/util/ec_panicinfo.h
deleted file mode 100644
index f70c58e59f..0000000000
--- a/util/ec_panicinfo.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef EC_PANICINFO_H
-#define EC_PANICINFO_H
-
-#include "panic.h"
-
-/**
- * Prints panic information to stdout.
- *
- * @param pdata  Panic information to print
- * @return 0 if success or non-zero error code if error.
- */
-int parse_panic_info(const struct panic_data *pdata);
-
-#endif /* EC_PANICINFO_H */
diff --git a/util/ec_panicinfo_fuzzer.cc b/util/ec_panicinfo_fuzzer.cc
new file mode 100644
index 0000000000..7767afa2e2
--- /dev/null
+++ b/util/ec_panicinfo_fuzzer.cc
@@ -0,0 +1,22 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <libec/ec_panicinfo.h>
+
+/* Fuzzing Build command:
+ * $ clang++ ec_panicinfo_fuzzer.cc ec_panicinfo.cc -g -fsanitize=address,fuzzer
+ *   -o ec_panicinfo_fuzzer
+ *   -I../include/ -I../chip/host/ -I../board/host/ -I../fuzz -I../test
+ *
+ * Run Fuzzing:
+ *  $ ./ec_panicinfo_fuzzer -runs=5000
+ */
+
+extern "C" int LLVMFuzzerTestOneInput(const uint8_t *data, unsigned int size)
+{
+	parse_panic_info((const char *)data, size);
+
+	return 0;
+}
diff --git a/util/ec_parse_panicinfo.c b/util/ec_parse_panicinfo.c
deleted file mode 100644
index 5db8ed2e05..0000000000
--- a/util/ec_parse_panicinfo.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Standalone utility to parse EC panicinfo.
- */
-
-#include <stdint.h>
-#include <stdio.h>
-#include "ec_panicinfo.h"
-
-int main(int argc, char *argv[])
-{
-	struct panic_data pdata;
-
-	if (fread(&pdata, sizeof(pdata), 1, stdin) != 1) {
-		fprintf(stderr, "Error reading panicinfo from stdin.\n");
-		return 1;
-	}
-
-	return parse_panic_info(&pdata) ? 1 : 0;
-}
diff --git a/util/ec_parse_panicinfo.cc b/util/ec_parse_panicinfo.cc
new file mode 100644
index 0000000000..eb8ab2a24c
--- /dev/null
+++ b/util/ec_parse_panicinfo.cc
@@ -0,0 +1,53 @@
+/* Copyright 2016 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Standalone utility to parse EC panicinfo.
+ */
+
+#include "compile_time_macros.h"
+
+#include <stdint.h>
+#include <stdio.h>
+
+#include <libec/ec_panicinfo.h>
+
+int main(int argc, char *argv[])
+{
+	/*
+	 * panic_data size could change with time, as new architecture are
+	 * added (or, less likely, removed).
+	 */
+	const size_t max_size = 4096;
+
+	BUILD_ASSERT(max_size > sizeof(struct panic_data) * 2);
+
+	/*
+	 * Provide a minimal help message.
+	 */
+	if (argc > 1) {
+		printf("Usage: cat <PANIC_BLOB_PATH> | ec_parse_panicinfo\n");
+		printf("Print the plain text panic info from a raw EC panic "
+		       "data blob.\n\n");
+		printf("Example:\n");
+		printf("ec_parse_panicinfo "
+		       "</sys/kernel/debug/cros_ec/panicinfo\n");
+		return 1;
+	}
+
+	auto data = ec::GetPanicInput(4096);
+	if (!data.has_value()) {
+		fprintf(stderr, "%s", data.error().c_str());
+		return 1;
+	}
+
+	auto result = ec::ParsePanicInfo(data.value());
+
+	if (!result.has_value()) {
+		fprintf(stderr, "%s", result.error().c_str());
+		return 1;
+	}
+	printf("%s", result.value().c_str());
+
+	return 0;
+}
diff --git a/util/ec_sb_firmware_update.c b/util/ec_sb_firmware_update.c
deleted file mode 100644
index 72d3baf175..0000000000
--- a/util/ec_sb_firmware_update.c
+++ /dev/null
@@ -1,843 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <errno.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
-
-#include "comm-host.h"
-#include "compile_time_macros.h"
-#include "ec_sb_firmware_update.h"
-#include "ec_commands.h"
-#include "lock/gec_lock.h"
-#include "misc_util.h"
-#include "powerd_lock.h"
-
-/* Subcommands: [check|update] */
-enum {
-	OP_UNKNOWN = 0,
-	OP_CHECK   = 1,
-	OP_UPDATE  = 2,
-};
-
-struct delay_value {
-	uint32_t steps;
-	uint32_t value;
-};
-
-/* Default retry counter on errors */
-#define SB_FW_UPDATE_DEFAULT_RETRY_CNT 3
-/* Default delay value */
-#define SB_FW_UPDATE_DEFAULT_DELAY  1000
-
-#define DELAY_US_BEGIN  500000
-#define DELAY_US_END   1000000
-#define DELAY_US_BUSY  1000000
-#define DELAY_US_WRITE_END  50000
-
-static struct delay_value sb_delays[] = {
-	{1,             100000},
-	{2,            9000000},
-	{4,             100000},
-	{771,            30000},
-	{2200,           10000},
-	{0xFFFFFF,       50000},
-};
-
-enum fw_update_state {
-	S0_READ_STATUS   = 0,
-	S1_READ_INFO     = 1,
-	S2_WRITE_PREPARE = 2,
-	S3_READ_STATUS   = 3,
-	S4_WRITE_UPDATE  = 4,
-	S5_READ_STATUS   = 5,
-	S6_WRITE_BLOCK   = 6,
-	S7_READ_STATUS   = 7,
-	S8_WRITE_END     = 8,
-	S9_READ_STATUS   = 9,
-	S10_TERMINAL     = 10
-};
-
-#define MAX_FW_IMAGE_NAME_SIZE 80
-
-/* Firmware Update Control Flags */
-enum {
-	F_AC_PRESENT    = 0x1, /* AC Present */
-	F_VERSION_CHECK = 0x2, /* do firmware version check */
-	F_UPDATE        = 0x4, /* do firmware update */
-	F_NEED_UPDATE   = 0x8,  /* need firmware update */
-	F_POWERD_DISABLED = 0x10,  /* powerd is disabled */
-	F_LFCC_ZERO =       0x20,  /* last full charge is zero */
-	F_BATT_DISCHARGE =  0x40   /* battery discharging */
-};
-
-struct fw_update_ctrl {
-	uint32_t flags; /* fw update control flags */
-	int size;    /* size of battery firmware image */
-	char *ptr;   /* current read pointer of the firmware image */
-	int  offset; /* current block write offset */
-	struct sb_fw_header *fw_img_hdr; /*pointer to firmware image header*/
-	struct sb_fw_update_status status;
-	struct sb_fw_update_info info;
-	int err_retry_cnt;
-	int fec_err_retry_cnt;
-	int busy_retry_cnt;
-	int step_size;
-	int rv;
-	char image_name[MAX_FW_IMAGE_NAME_SIZE];
-	char msg[256];
-};
-
-/*
- * Global Firmware Update Control Data Structure
- */
-static struct fw_update_ctrl fw_update;
-
-static uint32_t get_delay_value(uint32_t offset, uint32_t step_size)
-{
-	int sz = ARRAY_SIZE(sb_delays);
-	int i;
-	for (i = 0; i < sz; i++) {
-		if (offset <= sb_delays[i].steps * step_size)
-			return sb_delays[i].value;
-	}
-	return sb_delays[sz-1].value;
-}
-
-static void print_battery_firmware_image_hdr(
-	struct sb_fw_header *hdr)
-{
-	printf("Latest Battery Firmware:\n");
-	printf("\t%c%c%c%c hdr_ver:%04x major_minor:%04x\n",
-		hdr->signature[0],
-		hdr->signature[1],
-		hdr->signature[2],
-		hdr->signature[3],
-		hdr->hdr_version, hdr->pkg_version_major_minor);
-
-	printf("\tmaker:0x%04x hwid:0x%04x fw_ver:0x%04x tbl_ver:0x%04x\n",
-		hdr->vendor_id, hdr->battery_type, hdr->fw_version,
-		hdr->data_table_version);
-
-	printf("\tbinary offset:0x%08x size:0x%08x chk_sum:0x%02x\n",
-		hdr->fw_binary_offset, hdr->fw_binary_size, hdr->checksum);
-}
-
-static void print_info(struct sb_fw_update_info *info)
-{
-	printf("\nCurrent Battery Firmware:\n");
-	printf("\tmaker:0x%04x hwid:0x%04x fw_ver:0x%04x tbl_ver:0x%04x\n",
-		info->maker_id,
-		info->hardware_id,
-		info->fw_version,
-		info->data_version);
-	return;
-}
-
-static void print_status(struct sb_fw_update_status *sts)
-{
-	printf("f_maker_id:%d f_hw_id:%d f_fw_ver:%d f_permnent:%d\n",
-		sts->v_fail_maker_id,
-		sts->v_fail_hw_id,
-		sts->v_fail_fw_version,
-		sts->v_fail_permanent);
-	printf("permanent failure:%d abnormal:%d fw_update:%d\n",
-		sts->permanent_failure,
-		sts->abnormal_condition,
-		sts->fw_update_supported);
-	printf("fw_update_mode:%d fw_corrupted:%d cmd_reject:%d\n",
-		sts->fw_update_mode,
-		sts->fw_corrupted,
-		sts->cmd_reject);
-	printf("invliad data:%d fw_fatal_err:%d fec_err:%d busy:%d\n",
-		sts->invalid_data,
-		sts->fw_fatal_error,
-		sts->fec_error,
-		sts->busy);
-	printf("\n");
-	return;
-}
-
-/* @return 1 (True) if img signature is valid */
-static int check_battery_firmware_image_signature(
-	struct sb_fw_header *hdr)
-{
-	return (hdr->signature[0] == 'B') &&
-		(hdr->signature[1] == 'T') &&
-		(hdr->signature[2] == 'F') &&
-		(hdr->signature[3] == 'W');
-}
-
-/* @return 1 (True) if img checksum is valid. */
-static int check_battery_firmware_image_checksum(
-	struct sb_fw_header *hdr)
-{
-	int i;
-	uint8_t sum = 0;
-	uint8_t *img = (uint8_t *)hdr;
-
-	img += hdr->fw_binary_offset;
-	for (i = 0; i < hdr->fw_binary_size; i++)
-		sum += img[i];
-	sum += hdr->checksum;
-	return sum == 0;
-}
-
-/* @return 1 (True) if img versions are ok to update. */
-static int check_battery_firmware_image_version(
-	struct sb_fw_header *hdr,
-	struct sb_fw_update_info *p)
-{
-	/*
-	 * If the battery firmware has a newer fw version
-	 * or a newer data table version, then it is ok to update.
-	 */
-	return (hdr->fw_version > p->fw_version)
-		|| (hdr->data_table_version > p->data_version);
-}
-
-
-static int check_battery_firmware_ids(
-	struct sb_fw_header *hdr,
-	struct sb_fw_update_info *p)
-{
-	return ((hdr->vendor_id == p->maker_id) &&
-		(hdr->battery_type == p->hardware_id));
-}
-
-/* check_if_need_update_fw
- * @return 1 (true) if need; 0 (false) if not.
- */
-static int check_if_valid_fw(
-		struct sb_fw_header *hdr,
-		struct sb_fw_update_info *info)
-{
-	return check_battery_firmware_image_signature(hdr)
-		&& check_battery_firmware_ids(hdr, info)
-		&& check_battery_firmware_image_checksum(hdr);
-}
-
-/* check_if_need_update_fw
- * @return 1 (true) if need; 0 (false) if not.
- */
-static int check_if_need_update_fw(
-		struct sb_fw_header *hdr,
-		struct sb_fw_update_info *info)
-{
-	return check_battery_firmware_image_version(hdr, info);
-}
-
-static void log_msg(struct fw_update_ctrl *fw_update,
-			enum fw_update_state state, const char *msg)
-{
-	sprintf(fw_update->msg,
-		"Battery Firmware Updater State:%d %s", state, msg);
-}
-
-
-static char *read_fw_image(struct fw_update_ctrl *fw_update)
-{
-	int size;
-	char *buf;
-	fw_update->size = 0;
-	fw_update->ptr = NULL;
-	fw_update->fw_img_hdr = (struct sb_fw_header *)NULL;
-
-	/* Read the input file */
-	buf = read_file(fw_update->image_name, &size);
-	if (!buf)
-		return NULL;
-
-	fw_update->size = size;
-	fw_update->ptr = buf;
-	fw_update->fw_img_hdr = (struct sb_fw_header *)buf;
-	print_battery_firmware_image_hdr(fw_update->fw_img_hdr);
-
-	if (fw_update->fw_img_hdr->fw_binary_offset >= fw_update->size ||
-		fw_update->size < 256) {
-		printf("Load Firmware Image[%s] Error offset:%d size:%d\n",
-			fw_update->image_name,
-			fw_update->fw_img_hdr->fw_binary_offset,
-			fw_update->size);
-		free(buf);
-		return NULL;
-	}
-	return buf;
-}
-
-static int get_status(struct sb_fw_update_status *status)
-{
-	int rv = EC_RES_SUCCESS;
-	int cnt = 0;
-
-	struct ec_params_sb_fw_update *param =
-		(struct ec_params_sb_fw_update *)ec_outbuf;
-
-	struct ec_response_sb_fw_update *resp =
-		(struct ec_response_sb_fw_update *)ec_inbuf;
-
-	param->hdr.subcmd = EC_SB_FW_UPDATE_STATUS;
-	do {
-		usleep(SB_FW_UPDATE_DEFAULT_DELAY);
-		rv = ec_command(EC_CMD_SB_FW_UPDATE, 0,
-			param, sizeof(struct ec_sb_fw_update_header),
-			resp, SB_FW_UPDATE_CMD_STATUS_SIZE);
-	} while ((rv < 0) && (cnt++ < SB_FW_UPDATE_DEFAULT_RETRY_CNT));
-
-	if (rv < 0) {
-		memset(status, 0, SB_FW_UPDATE_CMD_STATUS_SIZE);
-		return -EC_RES_ERROR;
-	}
-
-	memcpy(status, resp->status.data, SB_FW_UPDATE_CMD_STATUS_SIZE);
-	return EC_RES_SUCCESS;
-}
-
-static int get_info(struct sb_fw_update_info *info)
-{
-	int rv = EC_RES_SUCCESS;
-	int cnt = 0;
-
-	struct ec_params_sb_fw_update *param =
-		(struct ec_params_sb_fw_update *)ec_outbuf;
-
-	struct ec_response_sb_fw_update *resp =
-		(struct ec_response_sb_fw_update *)ec_inbuf;
-
-	param->hdr.subcmd = EC_SB_FW_UPDATE_INFO;
-	do {
-		usleep(SB_FW_UPDATE_DEFAULT_DELAY);
-		rv = ec_command(EC_CMD_SB_FW_UPDATE, 0,
-			param, sizeof(struct ec_sb_fw_update_header),
-			resp, SB_FW_UPDATE_CMD_INFO_SIZE);
-	} while ((rv < 0) && (cnt++ < SB_FW_UPDATE_DEFAULT_RETRY_CNT));
-
-	if (rv < 0) {
-		memset(info, 0, SB_FW_UPDATE_CMD_INFO_SIZE);
-		return -EC_RES_ERROR;
-	}
-
-	memcpy(info, resp->info.data, SB_FW_UPDATE_CMD_INFO_SIZE);
-	return EC_RES_SUCCESS;
-}
-
-static int send_subcmd(int subcmd)
-{
-	int rv = EC_RES_SUCCESS;
-
-	struct ec_params_sb_fw_update *param =
-		(struct ec_params_sb_fw_update *)ec_outbuf;
-
-	param->hdr.subcmd = subcmd;
-	rv = ec_command(EC_CMD_SB_FW_UPDATE, 0,
-		param, sizeof(struct ec_sb_fw_update_header), NULL, 0);
-	if (rv < 0) {
-		printf("Firmware Update subcmd:%d Error\n", subcmd);
-		return -EC_RES_ERROR;
-	}
-	return EC_RES_SUCCESS;
-}
-
-static int write_block(struct fw_update_ctrl *fw_update,
-			int offset, int bsize)
-{
-	int rv;
-
-	struct ec_params_sb_fw_update *param =
-		(struct ec_params_sb_fw_update *)ec_outbuf;
-
-	memcpy(param->write.data, fw_update->ptr+offset, bsize);
-
-	param->hdr.subcmd = EC_SB_FW_UPDATE_WRITE;
-	rv = ec_command(EC_CMD_SB_FW_UPDATE, 0,
-		param, sizeof(struct ec_params_sb_fw_update), NULL, 0);
-	if (rv < 0) {
-		printf("Firmware Update Write Error ptr:%p offset@%x\n",
-			fw_update->ptr, offset);
-		return -EC_RES_ERROR;
-	}
-	return EC_RES_SUCCESS;
-}
-
-static void dump_data(uint8_t *data, int offset, int size)
-{
-	int i = 0;
-
-	printf("Offset:0x%X\n", offset);
-	for (i = 0; i < size; i++) {
-		if ((i%16) == 0)
-			printf("\n");
-		printf("%02X ", data[i]);
-	}
-	printf("\n");
-}
-
-static enum fw_update_state s0_read_status(struct fw_update_ctrl *fw_update)
-{
-	if (fw_update->busy_retry_cnt == 0) {
-		fw_update->rv = -1;
-		log_msg(fw_update, S0_READ_STATUS, "Busy");
-		return S10_TERMINAL;
-	}
-
-	fw_update->busy_retry_cnt--;
-
-	fw_update->rv = get_status(&fw_update->status);
-	if (fw_update->rv) {
-		fw_update->rv = -1;
-		log_msg(fw_update, S0_READ_STATUS, "Interface Error");
-		return S10_TERMINAL;
-	}
-
-	if (!((fw_update->status.abnormal_condition == 0)
-		&& (fw_update->status.fw_update_supported == 1))) {
-		return S0_READ_STATUS;
-	}
-
-	if (fw_update->status.busy) {
-		usleep(DELAY_US_BUSY);
-		return S0_READ_STATUS;
-	} else
-		return S1_READ_INFO;
-}
-
-static enum fw_update_state s1_read_battery_info(
-		struct fw_update_ctrl *fw_update)
-{
-	int rv;
-
-	if (fw_update->err_retry_cnt == 0) {
-		fw_update->rv = -1;
-		log_msg(fw_update, S1_READ_INFO, "Retry Error");
-		return S10_TERMINAL;
-	}
-
-	fw_update->err_retry_cnt--;
-
-	rv = get_info(&fw_update->info);
-	if (rv) {
-		fw_update->rv = -1;
-		log_msg(fw_update, S1_READ_INFO, "Interface Error");
-		return S10_TERMINAL;
-	}
-	print_info(&fw_update->info);
-
-	sprintf(fw_update->image_name,
-			"/lib/firmware/battery/maker.%04x.hwid.%04x.bin",
-			fw_update->info.maker_id,
-			fw_update->info.hardware_id);
-
-	if (NULL == read_fw_image(fw_update)) {
-		fw_update->rv = 0;
-		log_msg(fw_update, S1_READ_INFO, "Open Image File");
-		return S10_TERMINAL;
-	}
-
-	rv = get_status(&fw_update->status);
-	if (rv) {
-		fw_update->rv = -1;
-		log_msg(fw_update, S1_READ_INFO, "Interface Error");
-		return S10_TERMINAL;
-	}
-
-	rv = check_if_valid_fw(fw_update->fw_img_hdr, &fw_update->info);
-	if (rv == 0) {
-		fw_update->rv = -EC_RES_INVALID_PARAM;
-		log_msg(fw_update, S1_READ_INFO, "Invalid Firmware");
-		return S10_TERMINAL;
-	}
-
-	rv = check_if_need_update_fw(fw_update->fw_img_hdr, &fw_update->info);
-	if (rv == 0 && (fw_update->flags & F_VERSION_CHECK)) {
-		fw_update->rv = 0;
-		log_msg(fw_update, S1_READ_INFO, "Latest Firmware");
-		return S10_TERMINAL;
-	}
-
-	fw_update->flags |= F_NEED_UPDATE;
-
-	if (!(fw_update->flags & F_UPDATE)) {
-		fw_update->rv = 0;
-		return S10_TERMINAL;
-	}
-
-	if (!(fw_update->flags & F_AC_PRESENT)) {
-		fw_update->rv = 0;
-		log_msg(fw_update, S1_READ_INFO,
-			"Require AC Adapter Connected.");
-		return S10_TERMINAL;
-	}
-
-	if ((fw_update->flags & F_BATT_DISCHARGE) &&
-	    (fw_update->flags & F_AC_PRESENT)) {
-		/*
-		 * If battery discharge due to battery learning mode,
-		 * we can't update battery FW, because device will shutdown
-		 * during FW update.
-		 */
-		fw_update->rv = 0;
-		log_msg(fw_update, S1_READ_INFO,
-			"battery can't update in learning mode");
-		return S10_TERMINAL;
-	}
-
-	return S2_WRITE_PREPARE;
-}
-
-static enum fw_update_state s2_write_prepare(struct fw_update_ctrl *fw_update)
-{
-	int rv;
-
-	rv = disable_power_management();
-	if (0 == rv)
-		fw_update->flags |= F_POWERD_DISABLED;
-
-	rv = send_subcmd(EC_SB_FW_UPDATE_PREPARE);
-	if (rv) {
-		fw_update->rv = -1;
-		log_msg(fw_update, S2_WRITE_PREPARE, "Interface Error");
-		return S10_TERMINAL;
-	}
-	return S3_READ_STATUS;
-}
-
-static enum fw_update_state s3_read_status(struct fw_update_ctrl *fw_update)
-{
-	int rv;
-
-	rv = get_status(&fw_update->status);
-	if (rv) {
-		fw_update->rv = -1;
-		log_msg(fw_update, S3_READ_STATUS, "Interface Error");
-		return S10_TERMINAL;
-	}
-	return S4_WRITE_UPDATE;
-
-}
-
-static enum fw_update_state s4_write_update(struct fw_update_ctrl *fw_update)
-{
-	int rv;
-
-	rv = send_subcmd(EC_SB_FW_UPDATE_BEGIN);
-	if (rv) {
-		fw_update->rv = -1;
-		log_msg(fw_update, S4_WRITE_UPDATE, "Interface Error");
-		return S10_TERMINAL;
-	}
-	usleep(DELAY_US_BEGIN);
-	return S5_READ_STATUS;
-}
-
-static enum fw_update_state s5_read_status(struct fw_update_ctrl *fw_update)
-{
-	int rv = get_status(&fw_update->status);
-
-	if (rv) {
-		fw_update->rv = -1;
-		log_msg(fw_update, S5_READ_STATUS, "Interface Error");
-		return S10_TERMINAL;
-	}
-	if (fw_update->status.fw_update_mode == 0)
-		return S2_WRITE_PREPARE;
-
-	/* Init Write Block Loop Controls */
-	fw_update->ptr += fw_update->fw_img_hdr->fw_binary_offset;
-	fw_update->size -= fw_update->fw_img_hdr->fw_binary_offset;
-	fw_update->offset = 0;
-
-	return S6_WRITE_BLOCK;
-}
-
-static enum fw_update_state s6_write_block(struct fw_update_ctrl *fw_update)
-{
-	int rv;
-	int bsize;
-	int offset = fw_update->offset;
-
-	if (offset >= fw_update->size)
-		return S8_WRITE_END;
-
-	bsize = fw_update->step_size;
-
-	if ((offset & 0xFFFF) == 0x0)
-		printf("\n%X\n", offset);
-
-	if (fw_update->fec_err_retry_cnt == 0) {
-		fw_update->rv = -1;
-		log_msg(fw_update, S6_WRITE_BLOCK, "FEC Retry Error");
-		return S10_TERMINAL;
-	}
-	fw_update->fec_err_retry_cnt--;
-
-	rv = write_block(fw_update, offset, bsize);
-	if (rv) {
-		fw_update->rv = -1;
-		log_msg(fw_update, S6_WRITE_BLOCK, "Interface Error");
-		return S10_TERMINAL;
-	}
-
-	/*
-	 * Add more delays after the last few (3) block writes.
-	 * 3 is chosen based on current test results.
-	 */
-	if ((offset + 3*fw_update->step_size) >= fw_update->size)
-		usleep(DELAY_US_WRITE_END);
-
-	usleep(get_delay_value(offset, fw_update->step_size));
-
-	return S7_READ_STATUS;
-}
-
-static enum fw_update_state s7_read_status(struct fw_update_ctrl *fw_update)
-{
-	int rv;
-	int offset = fw_update->offset;
-	int bsize;
-	int cnt = 0;
-
-	bsize = fw_update->step_size;
-	do {
-		usleep(SB_FW_UPDATE_DEFAULT_DELAY);
-		rv = get_status(&fw_update->status);
-		if (rv) {
-			dump_data(fw_update->ptr+offset, offset, bsize);
-			print_status(&fw_update->status);
-			fw_update->rv = -1;
-			log_msg(fw_update, S7_READ_STATUS, "Interface Error");
-			return S10_TERMINAL;
-		}
-	} while (fw_update->status.busy &&
-			(cnt++ < SB_FW_UPDATE_DEFAULT_RETRY_CNT));
-
-	if (fw_update->status.fec_error) {
-		dump_data(fw_update->ptr+offset, offset, bsize);
-		print_status(&fw_update->status);
-		fw_update->rv = 0;
-		return S6_WRITE_BLOCK;
-	}
-	if (fw_update->status.permanent_failure ||
-		fw_update->status.v_fail_permanent) {
-		dump_data(fw_update->ptr+offset, offset, bsize);
-		print_status(&fw_update->status);
-		fw_update->rv = -1;
-		log_msg(fw_update, S7_READ_STATUS, "Battery Permanent Error");
-		return S8_WRITE_END;
-	}
-	if (fw_update->status.v_fail_maker_id ||
-		fw_update->status.v_fail_hw_id ||
-		fw_update->status.v_fail_fw_version ||
-		fw_update->status.fw_corrupted ||
-		fw_update->status.cmd_reject ||
-		fw_update->status.invalid_data ||
-		fw_update->status.fw_fatal_error) {
-
-		dump_data(fw_update->ptr+offset, offset, bsize);
-		print_status(&fw_update->status);
-		fw_update->rv = 0;
-		return S1_READ_INFO;
-	}
-
-	fw_update->fec_err_retry_cnt = SB_FW_UPDATE_FEC_ERROR_RETRY_CNT;
-	fw_update->offset += fw_update->step_size;
-	return S6_WRITE_BLOCK;
-}
-
-
-static enum fw_update_state s8_write_end(struct fw_update_ctrl *fw_update)
-{
-	int rv;
-
-	rv = send_subcmd(EC_SB_FW_UPDATE_END);
-	if (rv && (0 == fw_update->rv)) {
-		fw_update->rv = -1;
-		log_msg(fw_update, S8_WRITE_END, "Interface Error");
-	}
-
-	if (fw_update->rv)
-		return S10_TERMINAL;
-
-	usleep(DELAY_US_END);
-	fw_update->busy_retry_cnt = SB_FW_UPDATE_BUSY_ERROR_RETRY_CNT;
-	return S9_READ_STATUS;
-}
-
-static enum fw_update_state s9_read_status(struct fw_update_ctrl *fw_update)
-{
-	int rv;
-
-	if (fw_update->busy_retry_cnt == 0) {
-		fw_update->rv = -1;
-		log_msg(fw_update, S9_READ_STATUS, "Busy");
-		return S10_TERMINAL;
-	}
-
-	rv = get_status(&fw_update->status);
-	if (rv) {
-		fw_update->rv = -1;
-		log_msg(fw_update, S9_READ_STATUS, "Interface Error");
-		return S10_TERMINAL;
-	}
-	if ((fw_update->status.fw_update_mode == 1)
-		|| (fw_update->status.busy == 1)) {
-		usleep(SB_FW_UPDATE_DEFAULT_DELAY);
-		fw_update->busy_retry_cnt--;
-		return S9_READ_STATUS;
-	}
-	log_msg(fw_update, S9_READ_STATUS, "Complete");
-	fw_update->flags &= ~F_NEED_UPDATE;
-	return S10_TERMINAL;
-}
-
-
-typedef enum fw_update_state (*fw_state_func)(struct fw_update_ctrl *fw_update);
-
-fw_state_func state_table[] = {
-	s0_read_status,
-	s1_read_battery_info,
-	s2_write_prepare,
-	s3_read_status,
-	s4_write_update,
-	s5_read_status,
-	s6_write_block,
-	s7_read_status,
-	s8_write_end,
-	s9_read_status
-};
-
-
-/**
- * Update Smart Battery Firmware
- *
- * @param fw_update struct fw_update_ctrl
- *
- * @return 0 if success, negative if error.
- */
-static int ec_sb_firmware_update(struct fw_update_ctrl *fw_update)
-{
-	enum fw_update_state state;
-
-	fw_update->err_retry_cnt = SB_FW_UPDATE_ERROR_RETRY_CNT;
-	fw_update->fec_err_retry_cnt = SB_FW_UPDATE_FEC_ERROR_RETRY_CNT;
-	fw_update->busy_retry_cnt = SB_FW_UPDATE_BUSY_ERROR_RETRY_CNT;
-	fw_update->step_size = SB_FW_UPDATE_CMD_WRITE_BLOCK_SIZE;
-
-	state = S0_READ_STATUS;
-	while (state != S10_TERMINAL)
-		state = state_table[state](fw_update);
-
-	if (fw_update->fw_img_hdr)
-		free(fw_update->fw_img_hdr);
-
-	return fw_update->rv;
-}
-
-#define GEC_LOCK_TIMEOUT_SECS   30  /* 30 secs */
-void usage(char *argv[])
-{
-	printf("Usage: %s [check|update]\n"
-		"	check: check if AC Adaptor is connected.\n"
-		"	update: trigger battery firmware update.\n",
-		argv[0]);
-}
-
-int main(int argc, char *argv[])
-{
-	int rv = 0;
-	int op = OP_UNKNOWN;
-	uint8_t val = 0;
-
-	if (argc != 2) {
-		usage(argv);
-		return -1;
-	}
-
-	if (!strcmp(argv[1], "check"))
-		op = OP_CHECK;
-	else if (!strcmp(argv[1], "update"))
-		op = OP_UPDATE;
-	else {
-		op = OP_UNKNOWN;
-		usage(argv);
-		return -1;
-	}
-
-	if (comm_init_dev(NULL)) {
-		printf("Couldn't initialize /dev.\n");
-		return -1;
-	}
-
-	if (comm_init_buffer()) {
-		fprintf(stderr, "Couldn't initialize buffers\n");
-		return -1;
-	}
-
-	fw_update.flags = 0;
-	rv = ec_readmem(EC_MEMMAP_BATT_FLAG, sizeof(val), &val);
-	if (rv <= 0) {
-		printf("EC Memmap read error:%d\n", rv);
-		goto out;
-	}
-
-	rv = get_status(&fw_update.status);
-	if (rv) {
-		fw_update.rv = -1;
-		log_msg(&fw_update, S1_READ_INFO, "Interface Error");
-		return S10_TERMINAL;
-	}
-
-	if (fw_update.status.fw_update_mode) {
-		/*
-		 * Previous battery firmware update was interrupted,
-		 * and we may not detect the presence of AC correctly.
-		 * Therefore, lie about our AC status.
-		 */
-		fw_update.flags |= F_AC_PRESENT;
-		printf("Assuming AC_PRESENT due to interrupted FW update\n");
-	} else {
-		if (val & EC_BATT_FLAG_AC_PRESENT) {
-			fw_update.flags |= F_AC_PRESENT;
-			printf("AC_PRESENT\n");
-		}
-	}
-
-	if (val & EC_BATT_FLAG_DISCHARGING) {
-		fw_update.flags |= F_BATT_DISCHARGE;
-		printf("Battery is in discharge state\n");
-	}
-	rv = ec_readmem(EC_MEMMAP_BATT_LFCC, sizeof(val), &val);
-	if (rv <= 0) {
-		printf("EC Memmap read error:%d\n", rv);
-		goto out;
-	}
-	if (val == 0)
-		fw_update.flags |= F_LFCC_ZERO;
-
-	if (op == OP_UPDATE)
-		fw_update.flags |= F_UPDATE;
-
-	fw_update.flags |= F_VERSION_CHECK;
-
-	rv = ec_sb_firmware_update(&fw_update);
-	printf("Battery Firmware Update:0x%02x %s\n%s\n",
-			fw_update.flags,
-			((rv) ? "FAIL " : " "),
-			fw_update.msg);
-
-	/* Update battery firmware update interface to be protected */
-	if (!(fw_update.flags & F_NEED_UPDATE))
-		rv |= send_subcmd(EC_SB_FW_UPDATE_PROTECT);
-
-	if (fw_update.flags & F_POWERD_DISABLED)
-		rv |= restore_power_management();
-out:
-	if (rv)
-		return -1;
-	else
-		return fw_update.flags & (F_LFCC_ZERO | F_NEED_UPDATE);
-}
diff --git a/util/ec_sb_firmware_update.h b/util/ec_sb_firmware_update.h
deleted file mode 100644
index 5bddebaf4a..0000000000
--- a/util/ec_sb_firmware_update.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Smart battery Firmware Update driver.
- * Ref: Common Smart Battery System Interface Specification v8.0.
- *
- * cmd.0x35, Write Word
- *   0x1000: Prepare to Update
- *   0x2000: End of Update
- *   0xF000: Update Firmware
- *
- * cmd.0x35, Read Word
- *   Firmware Update Status
- *
- * cmd.0x36 Write Block
- *   Send 32 byte firmware image
- *
- * cmd.0x37 Read Word
- *   Get Battery Information
- *   sequence:=b1,b0,b3,b2,b5,b5,b7,b6
- *
- * Command Sequence for Battery FW Update
- *
- *  0. cmd.0x35.read
- *  1. cmd.0x37.read
- *  2. cmd.0x35.write.0x1000
- *  3. cmd.0x35.read.status (optional)
- *  4. cmd.0x35.write.0xF000
- *  5. cmd.0x35.read.status
- *     if bit8-0, go to step 2
- *  6. cmd.0x36.write.32byte
- *  7. cmd.0x35.read.status
- *     if FEC.b13=1, go to step 6
- *     if fatal.b12=1, go to step 2
- *     if b11,b10,b9,b2,b1,b0; go to step 1
- *     if b5,b3; go to step 8
- *    (repeat 6,7)
- *  8. cmd.0x36.write.0x2000
- *  9. cmd.0x35.read.status
- */
-
-#ifndef __UTIL_EC_SB_FIRMWARE_UPDATE_H
-#define __UTIL_EC_SB_FIRMWARE_UPDATE_H
-
-struct sb_fw_header {
-	uint8_t signature[4]; /* "BTFW" */
-	uint16_t hdr_version; /* 0x0100 */
-	uint16_t pkg_version_major_minor;
-
-	uint16_t vendor_id; /* 8,9 */
-	uint16_t battery_type; /* A B */
-
-	uint16_t fw_version; /* C D */
-	uint16_t data_table_version; /* E F */
-	uint32_t fw_binary_offset; /*0x10 0x11 0x12 0x13 */
-	uint32_t fw_binary_size; /* 0x14 0x15 0x16 0x17 */
-	uint8_t  checksum; /* 0x18 */
-};
-
-/**
- * sb.fw.update.cmd.0x35, Read Word
- *    Firmware Update Status
- */
-struct sb_fw_update_status {
-	uint16_t v_fail_maker_id:1; /* b0 */
-	uint16_t v_fail_hw_id:1; /* b1 */
-	uint16_t v_fail_fw_version:1; /* b2 */
-	uint16_t v_fail_permanent:1; /* b3 */
-
-	uint16_t rsvd5:1; /* b4 */
-	uint16_t permanent_failure:1; /* b5 */
-	uint16_t abnormal_condition:1; /* b6 */
-	uint16_t fw_update_supported:1; /* b7 */
-
-	uint16_t fw_update_mode:1; /* b8 */
-	uint16_t fw_corrupted:1; /* b9 */
-	uint16_t cmd_reject:1; /* b10 */
-	uint16_t invalid_data:1; /* b11 */
-
-	uint16_t fw_fatal_error:1; /* b12 */
-	uint16_t fec_error:1; /* b13 */
-	uint16_t busy:1; /* b14 */
-	uint16_t rsvd15:1; /* b15 */
-} __packed;
-
-/**
- * sb.fw.update.cmd.0x37 Read Word
- *     Get Battery Information
- *     sequence:=b1,b0,b3,b2,b5,b5,b7,b6
- */
-struct sb_fw_update_info {
-	uint16_t maker_id;    /* b0, b1 */
-	uint16_t hardware_id; /* b2, b3 */
-	uint16_t fw_version;  /* b4, b5 */
-	uint16_t data_version;/* b6, b7 */
-} __packed;
-
-/**
- * smart.battery.maker.id
- */
-enum sb_maker_id {
-	sb_maker_id_lgc       = 0x0001, /* b0=0; b1=1 */
-	sb_maker_id_panasonic = 0x0002,
-	sb_maker_id_sanyo     = 0x0003,
-	sb_maker_id_sony      = 0x0004,
-	sb_maker_id_simplo    = 0x0005,
-	sb_maker_id_celxpert  = 0x0006,
-};
-
-/*
- * Ref: Common Smart Battery System Interface Specification v8.0 page 21-24.
- * case 1. If permanent error:b5,b3, go to setp8.
- * case 2. If error:b11,b10,b9 b2,b1,b0, go to step1. Retry < 3 times.
- * case 3. If firmware update fatal error:b12, go to step2. Retry < 3 times.
- *         In order to simply the implementation, I merged case 2 and 3.
- *         If firmware update fatal error:b12, go to step1 as well.
- * case 4. If error.FEC.b13=1, go to step6. Retry < 3 times.
- * case 5. If battery interface is busy, retry < 10 times.
- *    Delay 1 second between retries.
- */
-#define SB_FW_UPDATE_ERROR_RETRY_CNT      2
-#define SB_FW_UPDATE_FEC_ERROR_RETRY_CNT  2
-#define SB_FW_UPDATE_BUSY_ERROR_RETRY_CNT 4
-
-#endif
diff --git a/util/ec_uartd.c b/util/ec_uartd.c
deleted file mode 100644
index 4fc0323619..0000000000
--- a/util/ec_uartd.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/* Copyright 2011 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* ec_uartd.c - UART daemon for BD-ICDI-B board for EC debugging
- *
- * based on chromeos_public/src/third_party/hdctools/src/ftdiuart.c
- *
- * compile with:
- *    gcc -o ftdi_uartd ftdi_uartd.c -lftdi
- */
-
-/* Force header files to define grantpt(), posix_openpt(), cfmakeraw() */
-#define _DEFAULT_SOURCE /* Newer glibc */
-#define _BSD_SOURCE     /* Older glibc */
-#define _XOPEN_SOURCE 600
-/* Force header file to declare ptsname_r(), etc. */
-#ifndef _GNU_SOURCE
-#define _GNU_SOURCE
-#endif
-
-#include <errno.h>
-#include <fcntl.h>
-#include <ftdi.h>
-#include <getopt.h>
-#include <limits.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <sys/stat.h>
-#include <termios.h>
-#include <unistd.h>
-
-static const int ftdi_id[][2] = { {0x0403, 0xbcda},
-				  {0x0403, 0xbcd9} };
-
-int main(int argc, char **argv)
-{
-	struct ftdi_context fcontext;
-	struct termios tty_cfg;
-	char ptname[PATH_MAX];
-	char buf[1024];
-	int fd;
-	int rv;
-	int i;
-	int device_opened;
-
-	/* Init */
-	if (ftdi_init(&fcontext) < 0) {
-		fprintf(stderr, "ftdi_init failed\n");
-		return 1;
-	}
-
-	/* Open interface B (UART) in the FTDI device and set 115kbaud */
-	ftdi_set_interface(&fcontext, INTERFACE_B);
-	device_opened = 0;
-	for (i = 0; i < sizeof(ftdi_id) / sizeof(ftdi_id[0]); ++i) {
-		rv = ftdi_usb_open(&fcontext, ftdi_id[i][0], ftdi_id[i][1]);
-		if (rv >= 0) {
-			fprintf(stderr, "Using FTDI device %04x:%04x\n",
-					ftdi_id[i][0], ftdi_id[i][1]);
-			device_opened = 1;
-			break;
-		}
-	}
-	if (!device_opened) {
-		fprintf(stderr, "error opening ftdi device: %d (%s)\n",
-			rv, ftdi_get_error_string(&fcontext));
-		return 2;
-	}
-
-	rv = ftdi_set_baudrate(&fcontext, 115200);
-	if (rv < 0) {
-		fprintf(stderr, "error setting baudrate: %d (%s)\n",
-			rv, ftdi_get_error_string(&fcontext));
-		return 2;
-	}
-
-	/* Set DTR; this muxes RX on the ICDI board */
-	ftdi_setdtr(&fcontext, 1);
-
-	/* Open the pty */
-	fd = posix_openpt(O_RDWR | O_NOCTTY);
-	if (fd == -1) {
-		perror("opening pty master");
-		return 3;
-	}
-	if (grantpt(fd) == -1) {
-		perror("grantpt");
-		return 3;
-	}
-	if (unlockpt(fd) == -1) {
-		perror("unlockpt");
-		return 3;
-	}
-	if (fcntl(fd, F_SETFL, O_NONBLOCK) == -1) {
-		perror("fcntl setfl -> nonblock");
-		return 3;
-	}
-	if (ptsname_r(fd, ptname, PATH_MAX) != 0) {
-		perror("getting name of pty");
-		return 3;
-	}
-	fprintf(stderr, "pty name = %s\n", ptname);
-	if (!isatty(fd)) {
-		perror("not a TTY device\n");
-		return 3;
-	}
-	cfmakeraw(&tty_cfg);
-	tcsetattr(fd, TCSANOW, &tty_cfg);
-	if (chmod(ptname, 0666) == -1) {
-		perror("setting pty attributes");
-		return 3;
-	}
-
-	/* Read and write data forever */
-	while (1) {
-		int bytes = read(fd, buf, sizeof(buf));
-		if (bytes > 0) {
-			rv = ftdi_write_data(&fcontext, buf, bytes);
-			if (rv != bytes) {
-				perror("writing to uart");
-				break;
-			}
-		}
-
-		usleep(1000);
-
-		bytes = ftdi_read_data(&fcontext, buf, sizeof(buf));
-		if (bytes > 0) {
-			int bytes_remaining = bytes;
-			char *buf_ptr = buf;
-
-retry_write:
-			while (bytes_remaining &&
-			       ((bytes = write(fd, buf_ptr,
-					       bytes_remaining)) > 0)) {
-				buf_ptr += bytes;
-				bytes_remaining -= bytes;
-			}
-
-			if ((bytes == -1) &&
-			    ((errno == EAGAIN) || (errno == EWOULDBLOCK)))
-				goto retry_write;
-
-			if (bytes == -1)
-				perror("writing ftdi data to pty");
-
-		} else if (bytes < 0) {
-			perror("failed ftdi_read_data");
-			break;
-		}
-	}
-
-	/* Cleanup */
-	close(fd);
-	ftdi_usb_close(&fcontext);
-	ftdi_deinit(&fcontext);
-	return 0;
-}
diff --git a/util/ecst.c b/util/ecst.c
index 95aee7b73d..03c0ba582c 100644
--- a/util/ecst.c
+++ b/util/ecst.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -39,20 +39,22 @@ int is_mrider15 = FALSE;
 
 /* Chips information, RAM start address and RAM size. */
 struct chip_info chip_info[] = {
-	[NPCX5M5G] = {NPCX5M5G_RAM_ADDR, NPCX5M5G_RAM_SIZE},
-	[NPCX5M6G] = {NPCX5M6G_RAM_ADDR, NPCX5M6G_RAM_SIZE},
-	[NPCX7M5] = {NPCX7M5X_RAM_ADDR, NPCX7M5X_RAM_SIZE},
-	[NPCX7M6] = {NPCX7M6X_RAM_ADDR, NPCX7M6X_RAM_SIZE},
-	[NPCX7M7] = {NPCX7M7X_RAM_ADDR, NPCX7M7X_RAM_SIZE},
-	[NPCX9M3] = {NPCX9M3X_RAM_ADDR, NPCX9M3X_RAM_SIZE},
-	[NPCX9M6] = {NPCX9M6X_RAM_ADDR, NPCX9M6X_RAM_SIZE},
+	[NPCX5M5G] = { NPCX5M5G_RAM_ADDR, NPCX5M5G_RAM_SIZE },
+	[NPCX5M6G] = { NPCX5M6G_RAM_ADDR, NPCX5M6G_RAM_SIZE },
+	[NPCX7M5] = { NPCX7M5X_RAM_ADDR, NPCX7M5X_RAM_SIZE },
+	[NPCX7M6] = { NPCX7M6X_RAM_ADDR, NPCX7M6X_RAM_SIZE },
+	[NPCX7M7] = { NPCX7M7X_RAM_ADDR, NPCX7M7X_RAM_SIZE },
+	[NPCX9M3] = { NPCX9M3X_RAM_ADDR, NPCX9M3X_RAM_SIZE },
+	[NPCX9M6] = { NPCX9M6X_RAM_ADDR, NPCX9M6X_RAM_SIZE },
+	[NPCX9M8] = { NPCX9M8X_RAM_ADDR, NPCX9M8X_RAM_SIZE },
 };
 BUILD_ASSERT(ARRAY_SIZE(chip_info) == NPCX_CHIP_RAM_VAR_NONE);
 
 /* Support chips name strings */
-const char *supported_chips = "npcx5m5g, npcx5m6g, npcx7m5g, npcx7m6g, "
-		"npcx7m6f, npcx7m6fb, npcx7m6fc, npcx7m7fc, npcx7m7wb, "
-		"npcx7m7wc, npcx9m3f or npcx9m6f";
+const char *supported_chips =
+	"npcx5m5g, npcx5m6g, npcx7m5g, npcx7m6g, "
+	"npcx7m6f, npcx7m6fb, npcx7m6fc, npcx7m7fc, npcx7m7wb, "
+	"npcx7m7wc, npcx9m3f, npcx9m6f or npcx9m8s";
 
 static unsigned int calc_api_csum_bin(void);
 static unsigned int initialize_crc_32(void);
@@ -70,16 +72,17 @@ static unsigned int finalize_crc_32(unsigned int crc);
  *    and returns FALSE.
  */
 static int splice_into_path(char *result, const char *path, int resultsz,
-	const char *prefix) {
+			    const char *prefix)
+{
 	char *last_delim, *result_last_delim;
 
 	if (strlen(path) + strlen(prefix) + 1 > resultsz) {
 		my_printf(TERR,
-			"\n\nfilename '%s' with prefix '%s' too long\n\n",
-			path, prefix);
+			  "\n\nfilename '%s' with prefix '%s' too long\n\n",
+			  path, prefix);
 		my_printf(TINF,
-			"\n\n%zu + %zu + 1 needs to fit in %d bytes\n\n",
-			strlen(path), strlen(prefix), resultsz);
+			  "\n\n%zu + %zu + 1 needs to fit in %d bytes\n\n",
+			  strlen(path), strlen(prefix), resultsz);
 		return FALSE;
 	}
 
@@ -111,6 +114,8 @@ static enum npcx_chip_ram_variant chip_to_ram_var(const char *chip_name)
 		return NPCX9M6;
 	else if (str_cmp_no_case(chip_name, "npcx9m3f") == 0)
 		return NPCX9M3;
+	else if (str_cmp_no_case(chip_name, "npcx9m8s") == 0)
+		return NPCX9M8;
 	else if (str_cmp_no_case(chip_name, "npcx7m7wb") == 0)
 		return NPCX7M7;
 	else if (str_cmp_no_case(chip_name, "npcx7m7wc") == 0)
@@ -124,7 +129,7 @@ static enum npcx_chip_ram_variant chip_to_ram_var(const char *chip_name)
 	else if (str_cmp_no_case(chip_name, "npcx7m6fc") == 0)
 		return NPCX7M6;
 	else if (str_cmp_no_case(chip_name, "npcx7m6g") == 0)
-		return  NPCX7M6;
+		return NPCX7M6;
 	else if (str_cmp_no_case(chip_name, "npcx7m5g") == 0)
 		return NPCX7M5;
 	else if (str_cmp_no_case(chip_name, "npcx5m6g") == 0)
@@ -149,7 +154,6 @@ static enum npcx_chip_ram_variant chip_to_ram_var(const char *chip_name)
 int main(int argc, char *argv[])
 
 {
-
 	int mode_choose = FALSE;
 	/* Do we get a bin File? */
 	int main_fw_hdr_flag = FALSE;
@@ -160,7 +164,7 @@ int main(int argc, char *argv[])
 
 	/* Following variables: common to all modes */
 	int main_status = TRUE;
-	unsigned int  main_temp = 0L;
+	unsigned int main_temp = 0L;
 	char main_str_temp[TMP_STR_SIZE];
 	char *end_ptr;
 
@@ -189,17 +193,15 @@ int main(int argc, char *argv[])
 	g_verbose = NO_VERBOSE;
 
 	g_ram_start_address = chip_info[DEFAULT_CHIP].ram_addr;
-	g_ram_size          = chip_info[DEFAULT_CHIP].ram_size;
+	g_ram_size = chip_info[DEFAULT_CHIP].ram_size;
 
 	/* Set default values */
 	g_calc_type = CALC_TYPE_NONE;
 	bin_params.spi_max_clk = SPI_MAX_CLOCK_DEFAULT;
 	bin_params.spi_clk_ratio = 0x00;
 	bin_params.spi_read_mode = SPI_READ_MODE_DEFAULT;
-	bin_params.fw_load_addr =
-				chip_info[DEFAULT_CHIP].ram_addr;
-	bin_params.fw_ep =
-				chip_info[DEFAULT_CHIP].ram_addr;
+	bin_params.fw_load_addr = chip_info[DEFAULT_CHIP].ram_addr;
+	bin_params.fw_ep = chip_info[DEFAULT_CHIP].ram_addr;
 	bin_params.fw_err_detec_s_addr = FW_CRC_START_ADDR;
 	bin_params.fw_err_detec_e_addr = FW_CRC_START_ADDR;
 	bin_params.flash_size = FLASH_SIZE_DEFAULT;
@@ -234,20 +236,18 @@ int main(int argc, char *argv[])
 		else if (str_cmp_no_case(hdr_args[arg_ind], "-vv") == 0)
 			g_verbose = SUPER_VERBOSE;
 
-		else if (str_cmp_no_case(hdr_args[arg_ind],
-							"-mode") == 0) {
+		else if (str_cmp_no_case(hdr_args[arg_ind], "-mode") == 0) {
 			mode_choose = TRUE;
 			arg_ind++;
 			if ((hdr_args[arg_ind] == NULL) ||
-				(sscanf(hdr_args[arg_ind],
-					"%s", main_str_temp) != 1)) {
+			    (sscanf(hdr_args[arg_ind], "%s", main_str_temp) !=
+			     1)) {
 				my_printf(TERR, "\nCannot read operation mode");
 				my_printf(TERR, ", bt, bh or api. !\n");
 				main_status = FALSE;
 			} else {
 				/* bt, bh and api should not coexist */
-				if (main_fw_hdr_flag ||
-				    main_api_flag ||
+				if (main_fw_hdr_flag || main_api_flag ||
 				    main_hdr_flag) {
 					my_printf(TERR, "\nOperation modes bt");
 					my_printf(TERR, ", bh, and api should");
@@ -257,8 +257,8 @@ int main(int argc, char *argv[])
 
 				if (str_cmp_no_case(main_str_temp, "bt") == 0)
 					main_fw_hdr_flag = TRUE;
-				else if (str_cmp_no_case(main_str_temp,
-							 "bh") == 0)
+				else if (str_cmp_no_case(main_str_temp, "bh") ==
+					 0)
 					main_hdr_flag = TRUE;
 				else if (str_cmp_no_case(main_str_temp,
 							 "api") == 0)
@@ -266,8 +266,8 @@ int main(int argc, char *argv[])
 				else {
 					my_printf(TERR,
 						  "\nInvalid operation mode ");
-					my_printf(TERR,
-						  "(%s)\n", main_str_temp);
+					my_printf(TERR, "(%s)\n",
+						  main_str_temp);
 					main_status = FALSE;
 				}
 			}
@@ -276,11 +276,10 @@ int main(int argc, char *argv[])
 		else if (str_cmp_no_case(hdr_args[arg_ind], "-chip") == 0) {
 			arg_ind++;
 			if ((hdr_args[arg_ind] == NULL) ||
-				(sscanf(hdr_args[arg_ind],
-					"%s",
-					main_str_temp) != 1)) {
+			    (sscanf(hdr_args[arg_ind], "%s", main_str_temp) !=
+			     1)) {
 				my_printf(TERR, "\nCannot read chip name %s.\n",
-						supported_chips);
+					  supported_chips);
 				main_status = FALSE;
 			} else {
 				enum npcx_chip_ram_variant ram_variant;
@@ -291,41 +290,38 @@ int main(int argc, char *argv[])
 						  "\nInvalid chip name (%s) ",
 						  main_str_temp);
 					my_printf(TERR, ", it should be %s.\n",
-						supported_chips);
+						  supported_chips);
 					main_status = FALSE;
 					break;
 				}
 
-				if ((bin_params.bin_params
-					& BIN_FW_LOAD_START_ADDR) ==
-					0x00000000)
+				if ((bin_params.bin_params &
+				     BIN_FW_LOAD_START_ADDR) == 0x00000000)
 					bin_params.fw_load_addr =
-					chip_info[ram_variant].ram_addr;
+						chip_info[ram_variant].ram_addr;
 
-				if ((bin_params.bin_params
-					& BIN_FW_ENTRY_POINT) ==
-					0x00000000)
+				if ((bin_params.bin_params &
+				     BIN_FW_ENTRY_POINT) == 0x00000000)
 					bin_params.fw_ep =
-					chip_info[ram_variant].ram_addr;
+						chip_info[ram_variant].ram_addr;
 
 				g_ram_start_address =
 					chip_info[ram_variant].ram_addr;
-				g_ram_size =
-					chip_info[ram_variant].ram_size;
+				g_ram_size = chip_info[ram_variant].ram_size;
 
 				if ((ram_variant == NPCX5M5G) ||
-					(ram_variant == NPCX5M6G)) {
+				    (ram_variant == NPCX5M6G)) {
 					is_mrider15 = TRUE;
 				}
 			}
-		  /* -argfile Read argument file. File name must be after it.*/
-		} else if (str_cmp_no_case(hdr_args[arg_ind],
-					   "-argfile") == 0) {
+			/* -argfile Read argument file. File name must be after
+			 * it.*/
+		} else if (str_cmp_no_case(hdr_args[arg_ind], "-argfile") ==
+			   0) {
 			arg_ind++;
 			if (arg_ind < arg_num) {
-				strncpy(arg_file_name,
-						hdr_args[arg_ind],
-						sizeof(arg_file_name) - 1);
+				strncpy(arg_file_name, hdr_args[arg_ind],
+					sizeof(arg_file_name) - 1);
 				arg_file_pointer = fopen(arg_file_name, "rt");
 				if (arg_file_pointer == NULL) {
 					my_printf(TERR,
@@ -340,16 +336,15 @@ int main(int argc, char *argv[])
 					     (tmp_ind + arg_ind + 1) < arg_num;
 					     tmp_ind++)
 						strncpy(tmp_hdr_args[tmp_ind],
-							hdr_args
-							   [tmp_ind+arg_ind+1],
+							hdr_args[tmp_ind +
+								 arg_ind + 1],
 							ARG_SIZE);
 
 					tmp_arg_num = tmp_ind;
 
 					/* Read arguments from file to array */
 					for (arg_ind++;
-					     fscanf(arg_file_pointer,
-						    "%s",
+					     fscanf(arg_file_pointer, "%s",
 						    hdr_args[arg_ind]) == 1;
 					     arg_ind++)
 						;
@@ -359,9 +354,9 @@ int main(int argc, char *argv[])
 
 					/* Copy back the restored arguments. */
 					for (tmp_ind = 0;
-						 (tmp_ind < tmp_arg_num) &&
-						 (arg_ind < MAX_ARGS);
-						 tmp_ind++) {
+					     (tmp_ind < tmp_arg_num) &&
+					     (arg_ind < MAX_ARGS);
+					     tmp_ind++) {
 						strncpy(hdr_args[arg_ind++],
 							tmp_hdr_args[tmp_ind],
 							ARG_SIZE);
@@ -379,120 +374,113 @@ int main(int argc, char *argv[])
 		} else if (str_cmp_no_case(hdr_args[arg_ind], "-i") == 0) {
 			arg_ind++;
 			if (arg_ind < arg_num) {
-				strncpy(input_file_name,
-				hdr_args[arg_ind],
-				sizeof(input_file_name) - 1);
+				strncpy(input_file_name, hdr_args[arg_ind],
+					sizeof(input_file_name) - 1);
 			} else {
 				my_printf(TERR, "\nMissing Input File Name\n");
 				main_status = FALSE;
 			}
-		  /* -o Get output file name. */
+			/* -o Get output file name. */
 		} else if (str_cmp_no_case(hdr_args[arg_ind], "-o") == 0) {
 			arg_ind++;
 			if (arg_ind < arg_num) {
-				strncpy(output_file_name,
-					hdr_args[arg_ind],
+				strncpy(output_file_name, hdr_args[arg_ind],
 					sizeof(output_file_name) - 1);
 			} else {
 				my_printf(TERR,
 					  "\nMissing Output File Name.\n");
 				main_status = FALSE;
 			}
-		  /* -usearmrst get FW entry point from FW image offset 4.*/
-		} else if (str_cmp_no_case(hdr_args[arg_ind],
-					   "-usearmrst") == 0) {
-			if ((bin_params.bin_params &
-			     BIN_FW_ENTRY_POINT) != 0x00000000) {
+			/* -usearmrst get FW entry point from FW image
+			 * offset 4.*/
+		} else if (str_cmp_no_case(hdr_args[arg_ind], "-usearmrst") ==
+			   0) {
+			if ((bin_params.bin_params & BIN_FW_ENTRY_POINT) !=
+			    0x00000000) {
 				my_printf(TERR, "\n-usearmrst not allowed, ");
 				my_printf(TERR, "FW entry point already set ");
 				my_printf(TERR, "using -fwep !\n");
 				main_status = FALSE;
 			} else
-				bin_params.bin_params |=
-							BIN_FW_USER_ARM_RESET;
-		/* -nohcrs disable header CRC*/
+				bin_params.bin_params |= BIN_FW_USER_ARM_RESET;
+			/* -nohcrs disable header CRC*/
 		} else if (str_cmp_no_case(hdr_args[arg_ind], "-nohcrc") == 0)
-			bin_params.bin_params |=
-							BIN_FW_HDR_CRC_DISABLE;
+			bin_params.bin_params |= BIN_FW_HDR_CRC_DISABLE;
 		/* -ph merg header in BIN file. */
 		else if (str_cmp_no_case(hdr_args[arg_ind], "-ph") == 0) {
-			bin_params.bin_params |=
-							BIN_FW_HDR_OFFSET;
-			if ((strlen(hdr_args[arg_ind+1]) == 0) ||
-				(sscanf(hdr_args[arg_ind+1],
-					"%x",
-					&main_temp) != 1))
+			bin_params.bin_params |= BIN_FW_HDR_OFFSET;
+			if ((strlen(hdr_args[arg_ind + 1]) == 0) ||
+			    (sscanf(hdr_args[arg_ind + 1], "%x", &main_temp) !=
+			     1))
 				bin_params.fw_hdr_offset = 0;
 			else {
 				arg_ind++;
 				bin_params.fw_hdr_offset = main_temp;
 			}
-		/* -spimaxclk  Get SPI flash max clock. */
-		} else if (str_cmp_no_case(hdr_args[arg_ind],
-					   "-spimaxclk") == 0) {
+			/* -spimaxclk  Get SPI flash max clock. */
+		} else if (str_cmp_no_case(hdr_args[arg_ind], "-spimaxclk") ==
+			   0) {
 			arg_ind++;
 			if ((hdr_args[arg_ind] == NULL) ||
-				(sscanf(hdr_args[arg_ind],
-					"%d", &main_temp) != 1)) {
+			    (sscanf(hdr_args[arg_ind], "%d", &main_temp) !=
+			     1)) {
 				my_printf(TERR, "\nCannot read SPI Flash Max");
 				my_printf(TERR, " Clock !\n");
 				main_status = FALSE;
 			} else
 				bin_params.spi_max_clk =
-						(unsigned char) main_temp;
-		/* -spiclkratio  Get SPI flash max clock ratio. */
-		} else if (str_cmp_no_case(hdr_args[arg_ind],
-			"-spiclkratio") == 0) {
+					(unsigned char)main_temp;
+			/* -spiclkratio  Get SPI flash max clock ratio. */
+		} else if (str_cmp_no_case(hdr_args[arg_ind], "-spiclkratio") ==
+			   0) {
 			arg_ind++;
 			if ((hdr_args[arg_ind] == NULL) ||
-				(sscanf(hdr_args[arg_ind],
-				"%d", &main_temp) != 1)) {
+			    (sscanf(hdr_args[arg_ind], "%d", &main_temp) !=
+			     1)) {
 				my_printf(TERR,
 					  "\nCannot read SPI Clock Ratio\n");
 				main_status = FALSE;
 			} else
 				bin_params.spi_clk_ratio =
-						(unsigned char)main_temp;
+					(unsigned char)main_temp;
 
-		/* spireadmode	get SPI read mode. */
-		} else if (str_cmp_no_case(hdr_args[arg_ind],
-					   "-spireadmode") == 0) {
+			/* spireadmode	get SPI read mode. */
+		} else if (str_cmp_no_case(hdr_args[arg_ind], "-spireadmode") ==
+			   0) {
 			arg_ind++;
 			if ((hdr_args[arg_ind] == NULL) ||
-				(sscanf(hdr_args[arg_ind],
-						"%20s",
-						main_str_temp) != 1)) {
+			    (sscanf(hdr_args[arg_ind], "%20s", main_str_temp) !=
+			     1)) {
 				my_printf(TERR, "\nCannot read SPI Flash");
 				my_printf(TERR, " Read Mode !\n");
 				main_status = FALSE;
 			} else {
 				if (str_cmp_no_case(main_str_temp,
-						SPI_NORMAL_MODE_VAL) == 0)
+						    SPI_NORMAL_MODE_VAL) == 0)
 					bin_params.spi_read_mode =
-					(unsigned char) SPI_NORMAL_MODE;
+						(unsigned char)SPI_NORMAL_MODE;
 				else if (str_cmp_no_case(main_str_temp,
-					 SPI_SINGLE_MODE_VAL) == 0)
+							 SPI_SINGLE_MODE_VAL) ==
+					 0)
 					bin_params.spi_read_mode =
-						(unsigned char)
-						SPI_SINGLE_MODE;
+						(unsigned char)SPI_SINGLE_MODE;
 				else if (str_cmp_no_case(main_str_temp,
-					 SPI_DUAL_MODE_VAL) == 0)
+							 SPI_DUAL_MODE_VAL) ==
+					 0)
 					bin_params.spi_read_mode =
-						(unsigned char)
-						SPI_DUAL_MODE;
+						(unsigned char)SPI_DUAL_MODE;
 				else if (str_cmp_no_case(main_str_temp,
-					SPI_QUAD_MODE_VAL) == 0)
+							 SPI_QUAD_MODE_VAL) ==
+					 0)
 					bin_params.spi_read_mode =
-						(unsigned char)
-						SPI_QUAD_MODE;
+						(unsigned char)SPI_QUAD_MODE;
 				else {
 					my_printf(TERR,
 						  "\nInvalid SPI Flash Read ");
 					my_printf(TERR,
 						  "Mode (%s), it should be ",
 						  main_str_temp);
-					my_printf(TERR,
-						  "normal, singleMode, ");
+					my_printf(TERR, "normal, singleMode, ");
 					my_printf(TERR,
 						  "dualMode or quadMode !\n");
 					main_status = FALSE;
@@ -508,95 +496,88 @@ int main(int argc, char *argv[])
 			bin_params.bin_params |= BIN_FW_CRC_DISABLE;
 
 		/* -fwloadaddr,  Get the FW load address. */
-		else if (str_cmp_no_case(hdr_args[arg_ind],
-					 "-fwloadaddr") == 0) {
+		else if (str_cmp_no_case(hdr_args[arg_ind], "-fwloadaddr") ==
+			 0) {
 			arg_ind++;
 			if ((hdr_args[arg_ind] == NULL) ||
-				(sscanf(hdr_args[arg_ind],
-					"%x",
-					&main_temp) != 1)) {
+			    (sscanf(hdr_args[arg_ind], "%x", &main_temp) !=
+			     1)) {
 				my_printf(TERR, "\nCannot read FW Load ");
 				my_printf(TERR, "\nstart address !\n");
 				main_status = FALSE;
 			} else {
 				/* Check that the address is 16-bytes aligned */
-				if ((main_temp &
-					ADDR_16_BYTES_ALIGNED_MASK) != 0) {
+				if ((main_temp & ADDR_16_BYTES_ALIGNED_MASK) !=
+				    0) {
 					my_printf(TERR,
 						  "\nFW load address start ");
 					my_printf(TERR,
 						  "address (0x%08X) is not ",
 						  main_temp);
-					my_printf(TERR,
-						  "16-bytes aligned !\n");
+					my_printf(TERR, "16-bytes aligned !\n");
 					main_status = FALSE;
 				} else {
-					bin_params.fw_load_addr =
-								     main_temp;
+					bin_params.fw_load_addr = main_temp;
 					bin_params.bin_params |=
-							BIN_FW_LOAD_START_ADDR;
+						BIN_FW_LOAD_START_ADDR;
 				}
 			}
-		  /* -fwep, Get the FW entry point. */
+			/* -fwep, Get the FW entry point. */
 		} else if (str_cmp_no_case(hdr_args[arg_ind], "-fwep") == 0) {
-			if ((bin_params.bin_params & BIN_FW_USER_ARM_RESET)
-								!= 0x00000000) {
-				my_printf(TERR,
-					 "\n-fwep not allowed, FW entry point");
+			if ((bin_params.bin_params & BIN_FW_USER_ARM_RESET) !=
+			    0x00000000) {
+				my_printf(
+					TERR,
+					"\n-fwep not allowed, FW entry point");
 				my_printf(TERR,
 					  " already set using -usearmrst!\n");
 				main_status = FALSE;
 			} else {
 				arg_ind++;
 				if ((hdr_args[arg_ind] == NULL) ||
-					(sscanf(hdr_args[arg_ind],
-						"%x",
-						&main_temp) != 1)) {
+				    (sscanf(hdr_args[arg_ind], "%x",
+					    &main_temp) != 1)) {
 					my_printf(TERR,
 						  "\nCan't read FW E-Point\n");
 					main_status = FALSE;
 				} else {
-					bin_params.fw_ep =
-								main_temp;
+					bin_params.fw_ep = main_temp;
 					bin_params.bin_params |=
-							BIN_FW_ENTRY_POINT;
+						BIN_FW_ENTRY_POINT;
 				}
 			}
-		  /*
-		   * -crcstart, Get the address from where to calculate
-		   * the FW CRC.
-		   */
-		} else if (str_cmp_no_case(hdr_args[arg_ind],
-					   "-crcstart") == 0) {
+			/*
+			 * -crcstart, Get the address from where to calculate
+			 * the FW CRC.
+			 */
+		} else if (str_cmp_no_case(hdr_args[arg_ind], "-crcstart") ==
+			   0) {
 			arg_ind++;
 			if ((hdr_args[arg_ind] == NULL) ||
-				(sscanf(hdr_args[arg_ind],
-					"%x",
-					&main_temp) != 1)) {
-						my_printf(TERR,
-						  "\nCannot read FW CRC");
-						my_printf(TERR,
-						  " start address !\n");
+			    (sscanf(hdr_args[arg_ind], "%x", &main_temp) !=
+			     1)) {
+				my_printf(TERR, "\nCannot read FW CRC");
+				my_printf(TERR, " start address !\n");
 				main_status = FALSE;
 			} else {
 				bin_params.fw_err_detec_e_addr =
 					bin_params.fw_err_detec_e_addr -
-					bin_params.fw_err_detec_s_addr
-					+ main_temp;
-				bin_params.fw_err_detec_s_addr =
-								main_temp;
+					bin_params.fw_err_detec_s_addr +
+					main_temp;
+				bin_params.fw_err_detec_s_addr = main_temp;
 				bin_params.bin_params |= BIN_FW_CKS_START;
 			}
-		  /* -crcsize,  Get the area size that need to be CRCed. */
-		} else if (str_cmp_no_case(hdr_args[arg_ind],
-					   "-crcsize") == 0) {
+			/* -crcsize,  Get the area size that need to be CRCed.
+			 */
+		} else if (str_cmp_no_case(hdr_args[arg_ind], "-crcsize") ==
+			   0) {
 			arg_ind++;
 			main_temp = 0x00;
 			if (hdr_args[arg_ind] == NULL)
 				end_ptr = NULL;
 			else
-				main_temp = strtol(hdr_args[arg_ind],
-						   &end_ptr, 16);
+				main_temp =
+					strtol(hdr_args[arg_ind], &end_ptr, 16);
 
 			if (hdr_args[arg_ind] == end_ptr) {
 				my_printf(TERR,
@@ -604,8 +585,8 @@ int main(int argc, char *argv[])
 				main_status = FALSE;
 			} else {
 				bin_params.fw_err_detec_e_addr =
-					bin_params.fw_err_detec_s_addr
-					+ main_temp - 1;
+					bin_params.fw_err_detec_s_addr +
+					main_temp - 1;
 				bin_params.bin_params |= BIN_FW_CKS_SIZE;
 			}
 		}
@@ -613,9 +594,8 @@ int main(int argc, char *argv[])
 		else if (str_cmp_no_case(hdr_args[arg_ind], "-fwlen") == 0) {
 			arg_ind++;
 			if ((hdr_args[arg_ind] == NULL) ||
-				(sscanf(hdr_args[arg_ind],
-					"%x",
-					&main_temp) != 1)) {
+			    (sscanf(hdr_args[arg_ind], "%x", &main_temp) !=
+			     1)) {
 				my_printf(TERR, "\nCannot read FW length !\n");
 				main_status = FALSE;
 			} else {
@@ -624,25 +604,24 @@ int main(int argc, char *argv[])
 			}
 		}
 		/* flashsize, Get the flash size. */
-		else if (str_cmp_no_case(hdr_args[arg_ind],
-					 "-flashsize") == 0) {
+		else if (str_cmp_no_case(hdr_args[arg_ind], "-flashsize") ==
+			 0) {
 			arg_ind++;
 			if ((hdr_args[arg_ind] == NULL) ||
-				(sscanf(hdr_args[arg_ind],
-					"%d",
-					&main_temp) != 1)) {
+			    (sscanf(hdr_args[arg_ind], "%d", &main_temp) !=
+			     1)) {
 				my_printf(TERR, "\nCannot read Flash size !\n");
 				main_status = FALSE;
 			} else
 				bin_params.flash_size = main_temp;
-		  /* -apisign, Get the method for error detect calculation. */
-		} else if (str_cmp_no_case(hdr_args[arg_ind],
-					   "-apisign") == 0) {
+			/* -apisign, Get the method for error detect
+			 * calculation. */
+		} else if (str_cmp_no_case(hdr_args[arg_ind], "-apisign") ==
+			   0) {
 			arg_ind++;
 			if ((hdr_args[arg_ind] == NULL) ||
-				(sscanf(hdr_args[arg_ind],
-					"%s",
-					main_str_temp) != 1)) {
+			    (sscanf(hdr_args[arg_ind], "%s", main_str_temp) !=
+			     1)) {
 				my_printf(TERR, "\nCannot read API sign, CRC,");
 				my_printf(TERR, " CheckSum or None. !\n");
 				main_status = FALSE;
@@ -666,23 +645,21 @@ int main(int argc, char *argv[])
 						  main_str_temp);
 					main_status = FALSE;
 				}
-
 			}
-		  /* -pointer,  Get the FW image address. */
-		} else if (str_cmp_no_case(hdr_args[arg_ind],
-					   "-pointer") == 0) {
+			/* -pointer,  Get the FW image address. */
+		} else if (str_cmp_no_case(hdr_args[arg_ind], "-pointer") ==
+			   0) {
 			arg_ind++;
 			if ((hdr_args[arg_ind] == NULL) ||
-				(sscanf(hdr_args[arg_ind],
-					"%x",
-					&main_temp) != 1)) {
+			    (sscanf(hdr_args[arg_ind], "%x", &main_temp) !=
+			     1)) {
 				my_printf(TERR,
 					  "\nCannot read FW Image address !\n");
 				main_status = FALSE;
 			} else {
 				/* Check that the address is 16-bytes aligned */
-				if ((main_temp & ADDR_16_BYTES_ALIGNED_MASK)
-									!= 0) {
+				if ((main_temp & ADDR_16_BYTES_ALIGNED_MASK) !=
+				    0) {
 					my_printf(TERR,
 						  "\nFW Image address (0x%08X)"
 						  " isn't 16-bytes aligned !\n",
@@ -696,8 +673,7 @@ int main(int argc, char *argv[])
 						  main_temp);
 					my_printf(TERR,
 						  "is higher from flash size");
-					my_printf(TERR,
-						  " (0x%08X) !\n",
+					my_printf(TERR, " (0x%08X) !\n",
 						  MAX_FLASH_SIZE);
 					main_status = FALSE;
 				} else {
@@ -713,8 +689,8 @@ int main(int argc, char *argv[])
 			if (hdr_args[arg_ind] == NULL)
 				end_ptr = NULL;
 			else
-				main_temp = strtol(hdr_args[arg_ind],
-						   &end_ptr, 16);
+				main_temp =
+					strtol(hdr_args[arg_ind], &end_ptr, 16);
 
 			if (hdr_args[arg_ind] == end_ptr) {
 				my_printf(TERR, "\nCannot read BootLoader");
@@ -722,11 +698,12 @@ int main(int argc, char *argv[])
 				main_status = FALSE;
 			} else {
 				/* Check that the address is 16-bytes aligned */
-				if ((main_temp & ADDR_16_BYTES_ALIGNED_MASK)
-									!= 0) {
-					my_printf(TERR,
-						  "\nFW Image address (0x%08X) ",
-						  main_temp);
+				if ((main_temp & ADDR_16_BYTES_ALIGNED_MASK) !=
+				    0) {
+					my_printf(
+						TERR,
+						"\nFW Image address (0x%08X) ",
+						main_temp);
 					my_printf(TERR,
 						  "is not 16-bytes aligned!\n");
 				}
@@ -737,8 +714,7 @@ int main(int argc, char *argv[])
 						  main_temp);
 					my_printf(TERR,
 						  " is higher from flash size");
-					my_printf(TERR,
-						  " (0x%08X) !\n",
+					my_printf(TERR, " (0x%08X) !\n",
 						  MAX_FLASH_SIZE);
 					main_status = FALSE;
 				} else {
@@ -747,27 +723,25 @@ int main(int argc, char *argv[])
 				}
 			}
 		} else {
-			my_printf(TERR,
-				  "\nUnknown flag: %s\n",
+			my_printf(TERR, "\nUnknown flag: %s\n",
 				  hdr_args[arg_ind]);
 			main_status = FALSE;
 		}
 	}
 
 	/*
-	* If the input and output file have the same name then exit with error.
-	*/
+	 * If the input and output file have the same name then exit with error.
+	 */
 	if (strcmp(output_file_name, input_file_name) == 0) {
 		my_printf(TINF,
-			"Input file name (%s) should be differed from\n",
-			input_file_name);
+			  "Input file name (%s) should be differed from\n",
+			  input_file_name);
 		my_printf(TINF, "Output file name (%s).\n", output_file_name);
 		main_status = FALSE;
 	}
 
 	/* No problems reading argv? So go on... */
 	if (main_status) {
-
 		/* if output file already exist, then delete it. */
 		tmp_file = fopen(output_file_name, "w");
 		if (tmp_file != NULL)
@@ -802,18 +776,17 @@ int main(int argc, char *argv[])
 	/* Say Bye Bye */
 	if (main_status) {
 		my_printf(TPAS, "\n\n******************************");
-		my_printf(TPAS,   "\n***    SUCCESS     ***");
-		my_printf(TPAS,   "\n******************************\n");
+		my_printf(TPAS, "\n***    SUCCESS     ***");
+		my_printf(TPAS, "\n******************************\n");
 
 		exit(EXIT_SUCCESS);
 	} else {
 		my_printf(TERR, "\n\n******************************");
-		my_printf(TERR,   "\n***    FAILED      ***");
-		my_printf(TERR,   "\n******************************\n");
+		my_printf(TERR, "\n***    FAILED      ***");
+		my_printf(TERR, "\n******************************\n");
 
 		exit(EXIT_FAILURE);
 	}
-
 }
 
 /*
@@ -930,12 +903,9 @@ void exit_with_usage(void)
  * Description: Copy the source file to the end of the destination file.
  *--------------------------------------------------------------------------
  */
-int copy_file_to_file(char *dst_file_name,
-		      char *src_file_name,
-		      int offset,
-		      int  origin)
+int copy_file_to_file(char *dst_file_name, char *src_file_name, int offset,
+		      int origin)
 {
-
 	int index = 0;
 	int result = 0;
 	unsigned char local_val;
@@ -1030,12 +1000,9 @@ void my_printf(int error_level, char *fmt, ...)
  * Description:	 Writes to ELF or BIN files - whatever is open
  *--------------------------------------------------------------------------
  */
-int write_to_file(unsigned int write_value,
-		  unsigned int offset,
-		  unsigned char num_of_bytes,
-		  char *print_string)
+int write_to_file(unsigned int write_value, unsigned int offset,
+		  unsigned char num_of_bytes, char *print_string)
 {
-
 	int result = 0;
 	int index;
 	unsigned int localValue4;
@@ -1046,32 +1013,23 @@ int write_to_file(unsigned int write_value,
 		return FALSE;
 
 	switch (num_of_bytes) {
-	case(1):
+	case (1):
 		localValue1 = (unsigned char)write_value;
-		result = (int)(fwrite(&localValue1, 1,
-							  1, g_hfd_pointer));
-	break;
-	case(2):
+		result = (int)(fwrite(&localValue1, 1, 1, g_hfd_pointer));
+		break;
+	case (2):
 		localValue2 = (unsigned short)write_value;
-		result = (int)(fwrite(&localValue2,
-				      2,
-				      1,
-				      g_hfd_pointer));
+		result = (int)(fwrite(&localValue2, 2, 1, g_hfd_pointer));
 		break;
-	case(4):
+	case (4):
 		localValue4 = write_value;
-		result = (int)(fwrite(&localValue4,
-				      4,
-				      1,
-				      g_hfd_pointer));
+		result = (int)(fwrite(&localValue4, 4, 1, g_hfd_pointer));
 		break;
 	default:
 		/* Pad the same value N times. */
 		localValue1 = (unsigned char)write_value;
 		for (index = 0; index < num_of_bytes; index++)
-			result = (int)(fwrite(&localValue1,
-					      1,
-					      1,
+			result = (int)(fwrite(&localValue1, 1, 1,
 					      g_hfd_pointer));
 		break;
 	}
@@ -1079,18 +1037,15 @@ int write_to_file(unsigned int write_value,
 	my_printf(TINF, "\nIn write_to_file  - %s", print_string);
 
 	if (result) {
-		my_printf(TINF,
-			" - Offset %2d - value 0x%x",
-			offset, write_value);
+		my_printf(TINF, " - Offset %2d - value 0x%x", offset,
+			  write_value);
 	} else {
-		my_printf(TERR,
-			"\n\nCouldn't write %x to file at %x\n\n",
-			write_value, offset);
+		my_printf(TERR, "\n\nCouldn't write %x to file at %x\n\n",
+			  write_value, offset);
 		return FALSE;
 	}
 
 	return TRUE;
-
 }
 
 /*
@@ -1101,10 +1056,8 @@ int write_to_file(unsigned int write_value,
  * Description : Reads from open BIN file
  *--------------------------------------------------------------------------
  */
-int read_from_file(unsigned int offset,
-				   unsigned char size_to_read,
-				   unsigned int *read_value,
-				   char *print_string)
+int read_from_file(unsigned int offset, unsigned char size_to_read,
+		   unsigned int *read_value, char *print_string)
 {
 	int result;
 	unsigned int localValue4;
@@ -1115,25 +1068,16 @@ int read_from_file(unsigned int offset,
 		return FALSE;
 
 	switch (size_to_read) {
-	case(1):
-		result = (int)(fread(&localValue1,
-				     1,
-				     1,
-				     input_file_pointer));
+	case (1):
+		result = (int)(fread(&localValue1, 1, 1, input_file_pointer));
 		*read_value = localValue1;
 		break;
-	case(2):
-		result = (int)(fread(&localValue2,
-				     2,
-				     1,
-				     input_file_pointer));
+	case (2):
+		result = (int)(fread(&localValue2, 2, 1, input_file_pointer));
 		*read_value = localValue2;
 		break;
-	case(4):
-		result = (int)(fread(&localValue4,
-				     4,
-				     1,
-				     input_file_pointer));
+	case (4):
+		result = (int)(fread(&localValue4, 4, 1, input_file_pointer));
 		*read_value = localValue4;
 		break;
 	default:
@@ -1145,13 +1089,10 @@ int read_from_file(unsigned int offset,
 	my_printf(TINF, "\nIn read_from_file - %s", print_string);
 
 	if (result) {
-		my_printf(TINF,
-			" - Offset %d - value %x",
-			offset, *read_value);
+		my_printf(TINF, " - Offset %d - value %x", offset, *read_value);
 	} else {
-		my_printf(TERR,
-			"\n\nCouldn't read from file at %x\n\n",
-			offset);
+		my_printf(TERR, "\n\nCouldn't read from file at %x\n\n",
+			  offset);
 		return FALSE;
 	}
 
@@ -1210,12 +1151,11 @@ void finalize_calculation(unsigned int *check_sum_crc)
  *		 given the previous checksum\crc
  *--------------------------------------------------------------------------
  */
-void update_calculation(unsigned int *check_sum_crc,
-						unsigned char byte_to_add)
+void update_calculation(unsigned int *check_sum_crc, unsigned char byte_to_add)
 {
 	switch (g_calc_type) {
 	case CALC_TYPE_NONE:
-			/* Do nothing */
+		/* Do nothing */
 		break;
 	case CALC_TYPE_CHECKSUM:
 		*check_sum_crc += byte_to_add;
@@ -1328,25 +1268,22 @@ int main_bin(struct tbinparams binary_params)
 		bin_fw_offset = binary_params.fw_hdr_offset + HEADER_SIZE;
 
 	my_printf(TINF, "\nBIN file:  %s, size: %d (0x%x) bytes\n",
-			  input_file_name,
-			  bin_file_size_bytes,
-			  bin_file_size_bytes);
+		  input_file_name, bin_file_size_bytes, bin_file_size_bytes);
 
 	/* Check validity of FW header offset. */
 	if (((int)binary_params.fw_hdr_offset < 0) ||
-		(binary_params.fw_hdr_offset > bin_file_size_bytes)) {
+	    (binary_params.fw_hdr_offset > bin_file_size_bytes)) {
 		my_printf(TERR,
 			  "\nFW header offset 0x%08x (%d) should be in the"
 			  " range of 0 and file size (%d).\n",
 			  binary_params.fw_hdr_offset,
-			  binary_params.fw_hdr_offset,
-			  bin_file_size_bytes);
+			  binary_params.fw_hdr_offset, bin_file_size_bytes);
 		return FALSE;
 	}
 
 	/* Create the header file in the same directory as the input file. */
 	if (!splice_into_path(g_hdr_input_name, input_file_name,
-		sizeof(g_hdr_input_name), "hdr_"))
+			      sizeof(g_hdr_input_name), "hdr_"))
 		return FALSE;
 	g_hfd_pointer = fopen(g_hdr_input_name, "w+b");
 	if (g_hfd_pointer == NULL) {
@@ -1356,7 +1293,7 @@ int main_bin(struct tbinparams binary_params)
 
 	if (strlen(output_file_name) == 0) {
 		if (!splice_into_path(output_file_name, input_file_name,
-			sizeof(output_file_name), "out_"))
+				      sizeof(output_file_name), "out_"))
 			return FALSE;
 	}
 
@@ -1368,15 +1305,12 @@ int main_bin(struct tbinparams binary_params)
 	 *********************************************************************
 	 */
 	/* Write the ancore. */
-	if (!write_to_file(FW_HDR_ANCHOR,
-			   HDR_ANCHOR_OFFSET,
-			   4,
+	if (!write_to_file(FW_HDR_ANCHOR, HDR_ANCHOR_OFFSET, 4,
 			   "HDR - FW Header ANCHOR		  "))
 		return FALSE;
 
 	/* Write the extended anchor. */
 	if (binary_params.bin_params & BIN_FW_HDR_CRC_DISABLE) {
-
 		/* Write the ancore and the extended anchor. */
 		if (!write_to_file(FW_HDR_EXT_ANCHOR_DISABLE,
 				   HDR_EXTENDED_ANCHOR_OFFSET, 2,
@@ -1409,14 +1343,13 @@ int main_bin(struct tbinparams binary_params)
 		break;
 	default:
 		my_printf(TERR, "\n\nInvalid SPI Flash MAX clock (%d MHz) ",
-				  binary_params.spi_max_clk);
+			  binary_params.spi_max_clk);
 		my_printf(TERR, "- it should be 20, 25, 33, 40 or 50 MHz");
 		return FALSE;
 	}
 
 	/* If SPI clock ratio set for MRIDER15, then it is error. */
 	if ((binary_params.spi_clk_ratio != 0x00) && (is_mrider15 == TRUE)) {
-
 		my_printf(TERR, "\nspiclkratio is not relevant for");
 		my_printf(TERR, " npcx5mng chips family !\n");
 
@@ -1439,13 +1372,13 @@ int main_bin(struct tbinparams binary_params)
 		break;
 	default:
 		my_printf(TERR, "\n\nInvalid SPI Core Clock Ratio (%d) ",
-			binary_params.spi_clk_ratio);
+			  binary_params.spi_clk_ratio);
 		my_printf(TERR, "- it should be 1 or 2");
 		return FALSE;
 	}
 
 	if (!write_to_file(tmp_param, HDR_SPI_MAX_CLK_OFFSET, 1,
-					   "HDR - SPI flash MAX Clock	  "))
+			   "HDR - SPI flash MAX Clock	  "))
 		return FALSE;
 
 	/* Write the SPI flash Read Mode. */
@@ -1453,7 +1386,6 @@ int main_bin(struct tbinparams binary_params)
 	/* If needed, set the unlimited burst bit. */
 	if (binary_params.bin_params & BIN_UNLIM_BURST_ENABLE) {
 		if (is_mrider15 == TRUE) {
-
 			my_printf(TERR, "\nunlimburst is not relevant for");
 			my_printf(TERR, " npcx5mng chips family !\n");
 
@@ -1462,35 +1394,29 @@ int main_bin(struct tbinparams binary_params)
 
 		tmp_param |= SPI_UNLIMITED_BURST_ENABLE;
 	}
-	if (!write_to_file(tmp_param,
-					   HDR_SPI_READ_MODE_OFFSET, 1,
-					   "HDR - SPI flash Read Mode	   "))
+	if (!write_to_file(tmp_param, HDR_SPI_READ_MODE_OFFSET, 1,
+			   "HDR - SPI flash Read Mode	   "))
 		return FALSE;
 
 	/* Write the error detection configuration. */
 	if (binary_params.bin_params & BIN_FW_CRC_DISABLE) {
 		if (!write_to_file(FW_CRC_DISABLE,
-				   HDR_ERR_DETECTION_CONF_OFFSET,
-				   1,
+				   HDR_ERR_DETECTION_CONF_OFFSET, 1,
 				   "HDR - FW CRC Disabled		   "))
 			return FALSE;
 	} else {
 		/* Write the ancore and the extended anchor. */
-		if (!write_to_file(FW_CRC_ENABLE,
-				   HDR_ERR_DETECTION_CONF_OFFSET, 1,
-				   "HDR - FW CRC Enabled		  "))
+		if (!write_to_file(FW_CRC_ENABLE, HDR_ERR_DETECTION_CONF_OFFSET,
+				   1, "HDR - FW CRC Enabled		  "))
 			return FALSE;
 	}
 
 	/* FW entry point should be between the FW load address and RAM size */
-	if ((binary_params.fw_load_addr >
-					(g_ram_start_address + g_ram_size)) ||
-		(binary_params.fw_load_addr < g_ram_start_address)) {
-		my_printf(TERR,
-			  "\nFW load address (0x%08x) should be between ",
+	if ((binary_params.fw_load_addr > (g_ram_start_address + g_ram_size)) ||
+	    (binary_params.fw_load_addr < g_ram_start_address)) {
+		my_printf(TERR, "\nFW load address (0x%08x) should be between ",
 			  binary_params.fw_load_addr);
-		my_printf(TERR,
-			  "start (0x%08x) and end (0x%08x) of RAM ).",
+		my_printf(TERR, "start (0x%08x) and end (0x%08x) of RAM ).",
 			  g_ram_start_address,
 			  (g_ram_start_address + g_ram_size));
 
@@ -1499,8 +1425,8 @@ int main_bin(struct tbinparams binary_params)
 
 	/* Write the FW load start address */
 	if (!write_to_file(binary_params.fw_load_addr,
-					   HDR_FW_LOAD_START_ADDR_OFFSET, 4,
-					   "HDR - FW load start address	 "))
+			   HDR_FW_LOAD_START_ADDR_OFFSET, 4,
+			   "HDR - FW load start address	 "))
 		return FALSE;
 
 	/*
@@ -1512,25 +1438,22 @@ int main_bin(struct tbinparams binary_params)
 		 * size of the binary file minus the offset of the start of the
 		 * FW.
 		 */
-		binary_params.fw_len = bin_file_size_bytes-bin_fw_offset;
+		binary_params.fw_len = bin_file_size_bytes - bin_fw_offset;
 	}
 
 	if ((int)binary_params.fw_len < 0) {
 		my_printf(TERR,
 			  "\nFW length %d (0x%08x) should be greater than 0x0.",
-			  binary_params.fw_len,
-			  binary_params.fw_len);
+			  binary_params.fw_len, binary_params.fw_len);
 		return FALSE;
 	}
 
 	if (((int)binary_params.fw_len >
-				(bin_file_size_bytes - bin_fw_offset)) ||
-		((int)binary_params.fw_len > g_ram_size)) {
-		my_printf(TERR,
-			  "\nFW length %d (0x%08x) should be within the",
+	     (bin_file_size_bytes - bin_fw_offset)) ||
+	    ((int)binary_params.fw_len > g_ram_size)) {
+		my_printf(TERR, "\nFW length %d (0x%08x) should be within the",
 			  binary_params.fw_len, binary_params.fw_len);
-		my_printf(TERR,
-			  " input-file (related to the FW offset)");
+		my_printf(TERR, " input-file (related to the FW offset)");
 		my_printf(TERR,
 			  "\n (0x%08x) and within the RAM (RAM size: 0x%08x).",
 			  (bin_file_size_bytes - bin_fw_offset), g_ram_size);
@@ -1538,61 +1461,48 @@ int main_bin(struct tbinparams binary_params)
 	}
 
 	if ((binary_params.bin_params & BIN_FW_USER_ARM_RESET) != 0x00000000) {
-		read_from_file((bin_fw_offset + ARM_FW_ENTRY_POINT_OFFSET),
-			4,
-			&binary_params.fw_ep,
-			"read FW entry point for FW image ");
-
-		if ((binary_params.fw_ep <
-				binary_params.fw_load_addr) ||
-			(binary_params.fw_ep >
-				(binary_params.fw_load_addr +
-						binary_params.fw_len))) {
+		read_from_file((bin_fw_offset + ARM_FW_ENTRY_POINT_OFFSET), 4,
+			       &binary_params.fw_ep,
+			       "read FW entry point for FW image ");
+
+		if ((binary_params.fw_ep < binary_params.fw_load_addr) ||
+		    (binary_params.fw_ep >
+		     (binary_params.fw_load_addr + binary_params.fw_len))) {
 			my_printf(TERR,
 				  "\nFW entry point (0x%08x) should be between",
 				  binary_params.fw_ep);
-			my_printf(TERR,
-				  " the FW load address (0x%08x) ",
+			my_printf(TERR, " the FW load address (0x%08x) ",
 				  binary_params.fw_load_addr);
-			my_printf(TERR,
-				  "and FW length (0x%08x).\n",
+			my_printf(TERR, "and FW length (0x%08x).\n",
 				  (binary_params.fw_load_addr +
-							binary_params.fw_len));
+				   binary_params.fw_len));
 			return FALSE;
 		}
 	}
 
 	/* FW entry point should be between the FW load address and RAM size */
-	if ((binary_params.fw_ep <
-				binary_params.fw_load_addr) ||
-		(binary_params.fw_ep >
-				(binary_params.fw_load_addr +
-						binary_params.fw_len))) {
+	if ((binary_params.fw_ep < binary_params.fw_load_addr) ||
+	    (binary_params.fw_ep >
+	     (binary_params.fw_load_addr + binary_params.fw_len))) {
 		if (((binary_params.bin_params & BIN_FW_ENTRY_POINT) ==
-								0x00000000) &&
-			((binary_params.bin_params &
-			  BIN_FW_LOAD_START_ADDR) != 0x00000000)) {
-			binary_params.fw_ep =
-					binary_params.fw_load_addr;
+		     0x00000000) &&
+		    ((binary_params.bin_params & BIN_FW_LOAD_START_ADDR) !=
+		     0x00000000)) {
+			binary_params.fw_ep = binary_params.fw_load_addr;
 		} else {
-			my_printf(TERR,
-				  "\nFW entry point (0x%08x) should be ",
+			my_printf(TERR, "\nFW entry point (0x%08x) should be ",
 				  binary_params.fw_ep);
-			my_printf(TERR,
-				  "\between the FW load address (0x%08x)",
+			my_printf(TERR, "\between the FW load address (0x%08x)",
 				  binary_params.fw_load_addr);
-			my_printf(TERR,
-				  " and FW length (0x%08x).\n",
+			my_printf(TERR, " and FW length (0x%08x).\n",
 				  (binary_params.fw_load_addr +
-							binary_params.fw_len));
+				   binary_params.fw_len));
 			return FALSE;
 		}
 	}
 
 	/* Write the FW entry point */
-	if (!write_to_file(binary_params.fw_ep,
-			   HDR_FW_ENTRY_POINT_OFFSET,
-			   4,
+	if (!write_to_file(binary_params.fw_ep, HDR_FW_ENTRY_POINT_OFFSET, 4,
 			   "HDR - FW Entry point		 "))
 		return FALSE;
 
@@ -1602,17 +1512,15 @@ int main_bin(struct tbinparams binary_params)
 		 * In case the size was not set, then CRC end address is
 		 * the size of the binary file.
 		 */
-		binary_params.fw_err_detec_e_addr =
-						binary_params.fw_len - 1;
+		binary_params.fw_err_detec_e_addr = binary_params.fw_len - 1;
 	} else {
 		/* CRC end address should be less than FW length. */
 		if (binary_params.fw_err_detec_e_addr >
-					(binary_params.fw_len - 1)) {
+		    (binary_params.fw_len - 1)) {
 			my_printf(TERR,
 				  "\nCRC end address (0x%08x) should be less ",
 				  binary_params.fw_err_detec_e_addr);
-			my_printf(TERR,
-				  "than the FW length %d (0x%08x)",
+			my_printf(TERR, "than the FW length %d (0x%08x)",
 				  (binary_params.fw_len),
 				  (binary_params.fw_len));
 			return FALSE;
@@ -1621,40 +1529,35 @@ int main_bin(struct tbinparams binary_params)
 
 	/* Check CRC start and end addresses. */
 	if (binary_params.fw_err_detec_s_addr >
-					binary_params.fw_err_detec_e_addr) {
+	    binary_params.fw_err_detec_e_addr) {
 		my_printf(TERR,
 			  "\nCRC start address (0x%08x) should be less or ",
 			  binary_params.fw_err_detec_s_addr);
 		my_printf(TERR,
 			  "equal to CRC end address (0x%08x)\nPlease check ",
 			  binary_params.fw_err_detec_e_addr);
-		my_printf(TERR,
-			  "CRC start address and CRC size arguments.");
+		my_printf(TERR, "CRC start address and CRC size arguments.");
 		return FALSE;
 	}
 
 	/* CRC start addr should be between the FW load address and RAM size */
-	if (binary_params.fw_err_detec_s_addr >
-				binary_params.fw_len) {
+	if (binary_params.fw_err_detec_s_addr > binary_params.fw_len) {
 		my_printf(TERR, "\nCRC start address (0x%08x) should ",
 			  binary_params.fw_err_detec_s_addr);
-		my_printf(TERR, "be FW length (0x%08x).",
-			  binary_params.fw_len);
+		my_printf(TERR, "be FW length (0x%08x).", binary_params.fw_len);
 		return FALSE;
 	}
 
 	/* Write the CRC start address */
 	if (!write_to_file(binary_params.fw_err_detec_s_addr,
-			   HDR_FW_ERR_DETECT_START_ADDR_OFFSET,
-			   4,
+			   HDR_FW_ERR_DETECT_START_ADDR_OFFSET, 4,
 			   "HDR - FW CRC Start			 "))
 		return FALSE;
 
 	/* CRC end addr should be between the CRC start address and RAM size */
 	if ((binary_params.fw_err_detec_e_addr <
-				binary_params.fw_err_detec_s_addr) ||
-		(binary_params.fw_err_detec_e_addr >
-				binary_params.fw_len)) {
+	     binary_params.fw_err_detec_s_addr) ||
+	    (binary_params.fw_err_detec_e_addr > binary_params.fw_len)) {
 		my_printf(TERR,
 			  "\nCRC end address (0x%08x) should be between the ",
 			  binary_params.fw_err_detec_e_addr);
@@ -1667,8 +1570,7 @@ int main_bin(struct tbinparams binary_params)
 
 	/* Write the CRC end address */
 	if (!write_to_file(binary_params.fw_err_detec_e_addr,
-			   HDR_FW_ERR_DETECT_END_ADDR_OFFSET,
-			   4,
+			   HDR_FW_ERR_DETECT_END_ADDR_OFFSET, 4,
 			   "HDR - FW CRC End			 "))
 		return FALSE;
 
@@ -1678,22 +1580,18 @@ int main_bin(struct tbinparams binary_params)
 		binary_params.fw_len += (16 - tmp_param);
 
 	/* FW load address + FW length should be less than the RAM size. */
-	if ((binary_params.fw_load_addr +
-			binary_params.fw_len) >
-					(g_ram_start_address + g_ram_size)) {
+	if ((binary_params.fw_load_addr + binary_params.fw_len) >
+	    (g_ram_start_address + g_ram_size)) {
 		my_printf(TERR,
 			  "\nFW load address + FW length should (0x%08x) be ",
 			  (binary_params.fw_load_addr + binary_params.fw_len));
-		my_printf(TERR,
-			  "less than the RAM size (0x%08x).",
+		my_printf(TERR, "less than the RAM size (0x%08x).",
 			  (g_ram_start_address + g_ram_size));
 		return FALSE;
 	}
 
 	/* Write the FW length */
-	if (!write_to_file(binary_params.fw_len,
-			   HDR_FW_LENGTH_OFFSET,
-			   4,
+	if (!write_to_file(binary_params.fw_len, HDR_FW_LENGTH_OFFSET, 4,
 			   "HDR - FW Length			   "))
 		return FALSE;
 
@@ -1716,30 +1614,26 @@ int main_bin(struct tbinparams binary_params)
 		break;
 	default:
 		my_printf(TERR, "\n\nInvalid Flash size (%d MBytes) -",
-				  binary_params.flash_size);
+			  binary_params.flash_size);
 		my_printf(TERR, " it should be 1, 2, 4, 8 or 16 MBytes\n");
 		return FALSE;
 	}
-	if (!write_to_file(tmp_param,
-			   HDR_FLASH_SIZE_OFFSET,
-			   1,
+	if (!write_to_file(tmp_param, HDR_FLASH_SIZE_OFFSET, 1,
 			   "HDR - Flash size			 "))
 
 		return FALSE;
 
 	/* Write the reserved bytes. */
 	if (!write_to_file(PAD_VALUE, HDR_RESERVED, 26,
-					   "HDR - Reserved (26 bytes)	  "))
+			   "HDR - Reserved (26 bytes)	  "))
 		return FALSE;
 
-
 	/* Refresh the FW header bin file in order to calculate CRC */
 	if (g_hfd_pointer) {
 		fclose(g_hfd_pointer);
 		g_hfd_pointer = fopen(g_hdr_input_name, "r+b");
 		if (g_hfd_pointer == NULL) {
-			my_printf(TERR,
-				  "\n\nCannot open %s\n\n",
+			my_printf(TERR, "\n\nCannot open %s\n\n",
 				  input_file_name);
 			return FALSE;
 		}
@@ -1757,9 +1651,7 @@ int main_bin(struct tbinparams binary_params)
 		binary_params.hdr_crc = 0;
 
 	/* Write FW header CRC to header file */
-	if (!write_to_file(binary_params.hdr_crc,
-			   HDR_FW_HEADER_SIG_OFFSET,
-			   4,
+	if (!write_to_file(binary_params.hdr_crc, HDR_FW_HEADER_SIG_OFFSET, 4,
 			   "HDR - Header CRC				"))
 		return FALSE;
 
@@ -1767,11 +1659,11 @@ int main_bin(struct tbinparams binary_params)
 	if ((binary_params.bin_params & BIN_FW_CRC_DISABLE) == 0) {
 		/* Calculate ... */
 		g_calc_type = CALC_TYPE_CRC;
-		if (!calc_firmware_csum_bin(&binary_params.fw_crc,
-			(bin_fw_offset +
-				binary_params.fw_err_detec_s_addr),
-			(binary_params.fw_err_detec_e_addr -
-				binary_params.fw_err_detec_s_addr+1)))
+		if (!calc_firmware_csum_bin(
+			    &binary_params.fw_crc,
+			    (bin_fw_offset + binary_params.fw_err_detec_s_addr),
+			    (binary_params.fw_err_detec_e_addr -
+			     binary_params.fw_err_detec_s_addr + 1)))
 			return FALSE;
 
 		g_calc_type = CALC_TYPE_NONE;
@@ -1779,9 +1671,7 @@ int main_bin(struct tbinparams binary_params)
 		binary_params.fw_crc = 0;
 
 	/* Write the FW CRC into file header file */
-	if (!write_to_file(binary_params.fw_crc,
-			   HDR_FW_IMAGE_SIG_OFFSET,
-			   4,
+	if (!write_to_file(binary_params.fw_crc, HDR_FW_IMAGE_SIG_OFFSET, 4,
 			   "HDR - FW CRC				   "))
 		return FALSE;
 
@@ -1802,22 +1692,14 @@ int main_bin(struct tbinparams binary_params)
 		fclose(output_file_pointer);
 
 	if ((binary_params.bin_params & BIN_FW_HDR_OFFSET) != 0) {
-		copy_file_to_file(output_file_name,
-				  input_file_name,
-				  0,
-				  SEEK_SET);
-		copy_file_to_file(output_file_name,
-				  g_hdr_input_name,
-				  binary_params.fw_hdr_offset,
+		copy_file_to_file(output_file_name, input_file_name, 0,
 				  SEEK_SET);
+		copy_file_to_file(output_file_name, g_hdr_input_name,
+				  binary_params.fw_hdr_offset, SEEK_SET);
 	} else {
-		copy_file_to_file(output_file_name,
-				  g_hdr_input_name,
-				  0,
+		copy_file_to_file(output_file_name, g_hdr_input_name, 0,
 				  SEEK_END);
-		copy_file_to_file(output_file_name,
-				  input_file_name,
-				  0,
+		copy_file_to_file(output_file_name, input_file_name, 0,
 				  SEEK_END);
 	}
 
@@ -1848,20 +1730,16 @@ int calc_header_crc_bin(unsigned int *p_cksum)
 	if (fseek(g_hfd_pointer, 0x00000000, SEEK_SET) < 0)
 		return FALSE;
 
-	if (fread(g_header_array,
-		  HEADER_SIZE,
-		  1,
-		  g_hfd_pointer) != 1)
+	if (fread(g_header_array, HEADER_SIZE, 1, g_hfd_pointer) != 1)
 		return FALSE;
 
 	for (i = 0; i < (HEADER_SIZE - HEADER_CRC_FIELDS_SIZE); i++) {
-
 		/*
 		 * I had once the Verbose check inside the my_printf, but
 		 * it made ECST run sloooowwwwwly....
 		 */
 		if (g_verbose == SUPER_VERBOSE) {
-			if (i%line_print_size == 0)
+			if (i % line_print_size == 0)
 				my_printf(TDBG, "\n[%.4x]: ", i);
 
 			my_printf(TDBG, "%.2x ", g_header_array[i]);
@@ -1872,10 +1750,8 @@ int calc_header_crc_bin(unsigned int *p_cksum)
 
 		if (g_verbose == SUPER_VERBOSE) {
 			if ((i + 1) % line_print_size == 0)
-				my_printf(TDBG,
-					  "FW Header ChecksumCRC = %.8x",
-					   calc_header_checksum_crc);
-
+				my_printf(TDBG, "FW Header ChecksumCRC = %.8x",
+					  calc_header_checksum_crc);
 		}
 	}
 
@@ -1895,11 +1771,9 @@ int calc_header_crc_bin(unsigned int *p_cksum)
  * Description:	 TBD
  *******************************************************************
  */
-int calc_firmware_csum_bin(unsigned int *p_cksum,
-						   unsigned int fw_offset,
-						   unsigned int fw_length)
+int calc_firmware_csum_bin(unsigned int *p_cksum, unsigned int fw_offset,
+			   unsigned int fw_length)
 {
-
 	unsigned int i;
 	unsigned int calc_read_bytes;
 	unsigned int calc_num_of_bytes_to_read;
@@ -1912,16 +1786,12 @@ int calc_firmware_csum_bin(unsigned int *p_cksum,
 	calc_curr_position = fw_offset;
 
 	if (g_verbose == REGULAR_VERBOSE) {
-		my_printf(TINF,
-			  "\nFW Error Detect Start Dddress: 0x%08x",
+		my_printf(TINF, "\nFW Error Detect Start Dddress: 0x%08x",
 			  calc_curr_position);
-		my_printf(TINF,
-			  "\nFW Error Detect End Dddress: 0x%08x",
+		my_printf(TINF, "\nFW Error Detect End Dddress: 0x%08x",
 			  calc_curr_position + calc_num_of_bytes_to_read - 1);
-		my_printf(TINF,
-			  "\nFW Error Detect Size:  %d (0x%X)",
-			  calc_num_of_bytes_to_read,
-			  calc_num_of_bytes_to_read);
+		my_printf(TINF, "\nFW Error Detect Size:  %d (0x%X)",
+			  calc_num_of_bytes_to_read, calc_num_of_bytes_to_read);
 	}
 
 	init_calculation(&calc_fw_checksum_crc);
@@ -1932,13 +1802,10 @@ int calc_firmware_csum_bin(unsigned int *p_cksum,
 		else
 			calc_read_bytes = calc_num_of_bytes_to_read;
 
-		if (fseek(input_file_pointer,
-			calc_curr_position, SEEK_SET) < 0)
+		if (fseek(input_file_pointer, calc_curr_position, SEEK_SET) < 0)
 			return 0;
-		if (fread(g_fw_array,
-			  calc_read_bytes,
-			  1,
-			  input_file_pointer) != 1)
+		if (fread(g_fw_array, calc_read_bytes, 1, input_file_pointer) !=
+		    1)
 			return 0;
 
 		for (i = 0; i < calc_read_bytes; i++) {
@@ -1947,9 +1814,8 @@ int calc_firmware_csum_bin(unsigned int *p_cksum,
 			 * but it made ECST run sloooowwwwwly....
 			 */
 			if (g_verbose == SUPER_VERBOSE) {
-				if (i%line_print_size == 0)
-					my_printf(TDBG,
-						  "\n[%.4x]: ",
+				if (i % line_print_size == 0)
+					my_printf(TDBG, "\n[%.4x]: ",
 						  calc_curr_position + i);
 
 				my_printf(TDBG, "%.2x ", g_fw_array[i]);
@@ -1960,8 +1826,7 @@ int calc_firmware_csum_bin(unsigned int *p_cksum,
 
 			if (g_verbose == SUPER_VERBOSE) {
 				if ((i + 1) % line_print_size == 0)
-					my_printf(TDBG,
-						  "FW Checksum= %.8x",
+					my_printf(TDBG, "FW Checksum= %.8x",
 						  calc_fw_checksum_crc);
 			}
 		}
@@ -2006,24 +1871,19 @@ int main_hdr(void)
 		}
 
 		if (strlen(output_file_name) == 0)
-			strncpy(tmp_file_name,
-				input_file_name,
+			strncpy(tmp_file_name, input_file_name,
 				sizeof(tmp_file_name) - 1);
 		else {
-			copy_file_to_file(output_file_name,
-					  input_file_name,
-					  0,
+			copy_file_to_file(output_file_name, input_file_name, 0,
 					  SEEK_END);
-			strncpy(tmp_file_name,
-				output_file_name,
+			strncpy(tmp_file_name, output_file_name,
 				sizeof(tmp_file_name) - 1);
 		}
 
 		/* Open Header file */
 		g_hdr_pointer = fopen(tmp_file_name, "r+b");
 		if (g_hdr_pointer == NULL) {
-			my_printf(TERR,
-				  "\n\nCannot open %s file.\n\n",
+			my_printf(TERR, "\n\nCannot open %s file.\n\n",
 				  tmp_file_name);
 			return FALSE;
 		}
@@ -2035,10 +1895,9 @@ int main_hdr(void)
 			my_printf(TERR,
 				  "\n\nFW offset 0x%08x should be less than ",
 				  fw_offset);
-			my_printf(TERR,
-				  "file size 0x%x (%d).\n\n",
+			my_printf(TERR, "file size 0x%x (%d).\n\n",
 				  bin_file_size_bytes, bin_file_size_bytes);
-			 return FALSE;
+			return FALSE;
 		}
 
 		/* FW table should be less than file size. */
@@ -2046,7 +1905,7 @@ int main_hdr(void)
 			my_printf(TERR, "\n\nFW table 0x%08x should be less ",
 				  ptr_fw_addr);
 			my_printf(TERR, "than file size 0x%x (%d).\n\n",
-				bin_file_size_bytes, bin_file_size_bytes);
+				  bin_file_size_bytes, bin_file_size_bytes);
 			return FALSE;
 		}
 
@@ -2054,25 +1913,15 @@ int main_hdr(void)
 			return FALSE;
 
 		tmp_long_val = HDR_PTR_SIGNATURE;
-		result = (int)(fwrite(&tmp_long_val,
-				      4,
-				      1,
-				      g_hdr_pointer));
-		result |= (int)(fwrite(&ptr_fw_addr,
-				       4,
-				       1,
-				       g_hdr_pointer));
+		result = (int)(fwrite(&tmp_long_val, 4, 1, g_hdr_pointer));
+		result |= (int)(fwrite(&ptr_fw_addr, 4, 1, g_hdr_pointer));
 
 		if (result) {
-			my_printf(TINF,
-				  "\nBootLoader Header file: %s\n",
+			my_printf(TINF, "\nBootLoader Header file: %s\n",
 				  tmp_file_name);
-			my_printf(TINF,
-				  " Offset: 0x%08X,  Signature: 0x%08X,",
+			my_printf(TINF, " Offset: 0x%08X,  Signature: 0x%08X,",
 				  fw_offset, HDR_PTR_SIGNATURE);
-			my_printf(TINF,
-				  " Pointer: 0x%08X\n",
-				  ptr_fw_addr);
+			my_printf(TINF, " Pointer: 0x%08X\n", ptr_fw_addr);
 		} else {
 			my_printf(TERR,
 				  "\n\nCouldn't write signature (%x) and "
@@ -2082,7 +1931,6 @@ int main_hdr(void)
 		}
 
 	} else {
-
 		if (strlen(output_file_name) == 0) {
 			my_printf(TERR, "\n\nNo output file selected ");
 			my_printf(TERR, "for BootLoader header file.\n\n");
@@ -2092,8 +1940,7 @@ int main_hdr(void)
 		/* Open Output file */
 		g_hdr_pointer = fopen(output_file_name, "w+b");
 		if (g_hdr_pointer == NULL) {
-			my_printf(TERR,
-				  "\n\nCannot open %s file.\n\n",
+			my_printf(TERR, "\n\nCannot open %s file.\n\n",
 				  output_file_name);
 			return FALSE;
 		}
@@ -2102,23 +1949,15 @@ int main_hdr(void)
 			return FALSE;
 
 		tmp_long_val = HDR_PTR_SIGNATURE;
-		result = (int)(fwrite(&tmp_long_val,
-				      4,
-				      1,
-				      g_hdr_pointer));
-		result |= (int)(fwrite(&ptr_fw_addr,
-				       4,
-				       1,
-				       g_hdr_pointer));
+		result = (int)(fwrite(&tmp_long_val, 4, 1, g_hdr_pointer));
+		result |= (int)(fwrite(&ptr_fw_addr, 4, 1, g_hdr_pointer));
 
 		if (result) {
-			my_printf(TINF,
-				  "\nBootLoader Header file: %s\n",
+			my_printf(TINF, "\nBootLoader Header file: %s\n",
 				  output_file_name);
 			my_printf(TINF,
 				  "     Signature: 0x%08X,   Pointer: 0x%08X\n",
-				  HDR_PTR_SIGNATURE,
-				  ptr_fw_addr);
+				  HDR_PTR_SIGNATURE, ptr_fw_addr);
 		} else {
 			my_printf(TERR,
 				  "\n\nCouldn't write signature (%x) and ",
@@ -2128,7 +1967,6 @@ int main_hdr(void)
 				  output_file_name);
 			return FALSE;
 		}
-
 	}
 
 	/* Close if needed... */
@@ -2166,15 +2004,15 @@ int main_api(void)
 
 	/* If API input file was not declared, then print error message. */
 	if (strlen(input_file_name) == 0) {
-		my_printf(TERR,
+		my_printf(
+			TERR,
 			"\n\nNeed to define API input file, using -i flag\n\n");
 		return FALSE;
-
 	}
 
 	if (strlen(output_file_name) == 0) {
 		if (!splice_into_path(tmp_file_name, input_file_name,
-			sizeof(tmp_file_name), "api_"))
+				      sizeof(tmp_file_name), "api_"))
 			return FALSE;
 	} else
 		strncpy(tmp_file_name, output_file_name,
@@ -2204,27 +2042,20 @@ int main_api(void)
 	api_file_size_bytes = get_file_length(api_file_pointer);
 	if (api_file_size_bytes < 0)
 		return FALSE;
-	my_printf(TINF,
-		  "\nAPI file: %s, size: %d bytes (0x%x)\n",
-		  tmp_file_name,
-		  api_file_size_bytes,
-		  api_file_size_bytes);
+	my_printf(TINF, "\nAPI file: %s, size: %d bytes (0x%x)\n",
+		  tmp_file_name, api_file_size_bytes, api_file_size_bytes);
 
 	crc_checksum = calc_api_csum_bin();
 
 	if (fseek(api_file_pointer, api_file_size_bytes, SEEK_SET) < 0)
 		return FALSE;
 
-	result = (int)(fwrite(&crc_checksum,
-			      4,
-			      1,
-			      api_file_pointer));
+	result = (int)(fwrite(&crc_checksum, 4, 1, api_file_pointer));
 
 	if (result)
 		my_printf(TINF,
 			  "\nIn API BIN file - Offset 0x%08X - value 0x%08X",
-			  api_file_size_bytes,
-			  crc_checksum);
+			  api_file_size_bytes, crc_checksum);
 	else {
 		my_printf(TERR,
 			  "\n\nCouldn't write %x to API BIN file at %08x\n\n",
@@ -2241,7 +2072,6 @@ int main_api(void)
 	return TRUE;
 }
 
-
 /*
  *******************************************************************
  * Function: calc_api_csum_bin
@@ -2250,10 +2080,9 @@ int main_api(void)
  * Return: Return the CRC \ checksum, or "0" in case of fail.
  * Description:	 TBD
  *******************************************************************
-*/
+ */
 unsigned int calc_api_csum_bin(void)
 {
-
 	unsigned int i;
 	unsigned int calc_read_bytes;
 	int calc_num_of_bytes_to_read;
@@ -2269,10 +2098,8 @@ unsigned int calc_api_csum_bin(void)
 		my_printf(TDBG,
 			  "\nAPI CRC \\ Checksum First Byte Address: 0x%08x",
 			  calc_curr_position);
-		my_printf(TDBG,
-			  "\nAPI CRC \\ Checksum Size:  %d (0x%X)",
-			  calc_num_of_bytes_to_read,
-			  calc_num_of_bytes_to_read);
+		my_printf(TDBG, "\nAPI CRC \\ Checksum Size:  %d (0x%X)",
+			  calc_num_of_bytes_to_read, calc_num_of_bytes_to_read);
 	}
 
 	init_calculation(&calc_fw_checksum_crc);
@@ -2283,13 +2110,10 @@ unsigned int calc_api_csum_bin(void)
 		else
 			calc_read_bytes = calc_num_of_bytes_to_read;
 
-		if (fseek(api_file_pointer,
-			calc_curr_position, SEEK_SET) < 0)
+		if (fseek(api_file_pointer, calc_curr_position, SEEK_SET) < 0)
 			return 0;
-		if (fread(g_fw_array,
-			  calc_read_bytes,
-			  1,
-			  api_file_pointer) != 1)
+		if (fread(g_fw_array, calc_read_bytes, 1, api_file_pointer) !=
+		    1)
 			return 0;
 
 		for (i = 0; i < calc_read_bytes; i++) {
@@ -2298,10 +2122,9 @@ unsigned int calc_api_csum_bin(void)
 			 * but it made ecst run sloooowwwwwly....
 			 */
 			if (g_verbose == SUPER_VERBOSE) {
-				if (i%line_print_size == 0)
-					my_printf(TDBG,
-					"\n[%.4x]: ",
-					calc_curr_position + i);
+				if (i % line_print_size == 0)
+					my_printf(TDBG, "\n[%.4x]: ",
+						  calc_curr_position + i);
 
 				my_printf(TDBG, "%.2x ", g_fw_array[i]);
 			}
@@ -2311,8 +2134,7 @@ unsigned int calc_api_csum_bin(void)
 
 			if (g_verbose == SUPER_VERBOSE) {
 				if ((i + 1) % line_print_size == 0)
-					my_printf(TDBG,
-						  "FW Checksum= %.8x",
+					my_printf(TDBG, "FW Checksum= %.8x",
 						  calc_fw_checksum_crc);
 			}
 		}
@@ -2323,14 +2145,13 @@ unsigned int calc_api_csum_bin(void)
 	finalize_calculation(&calc_fw_checksum_crc);
 
 	return calc_fw_checksum_crc;
-
 }
 
 /*
  **************************************************************************
  *			CRC Handler
  **************************************************************************
-*/
+ */
 
 /*
  *******************************************************************
@@ -2343,13 +2164,13 @@ unsigned int calc_api_csum_bin(void)
  *******************************************************************
  */
 
-#define P_32        0xEDB88320L
+#define P_32 0xEDB88320L
 
 /*
  *******************************************************************
  *
  *	static int crc_tab...init
- *	static unsigned ... crc_tab...[]
+ *	static unsigned int ... crc_tab...[]
  *
  *	The algorithms use tables with pre-calculated  values.  This
  *	speeds	up	the calculation dramatically. The first time the
@@ -2394,7 +2215,7 @@ static void init_crc32_tab(void);
 unsigned int initialize_crc_32(void)
 {
 	return 0xffffffffL;
-}  /* initialize_crc_32 */
+} /* initialize_crc_32 */
 
 /*
  *******************************************************************
@@ -2410,7 +2231,6 @@ unsigned int initialize_crc_32(void)
 
 unsigned int update_crc_32(unsigned int crc, char c)
 {
-
 	unsigned int tmp, long_c;
 
 	long_c = 0x000000ffL & (unsigned int)c;
@@ -2423,7 +2243,7 @@ unsigned int update_crc_32(unsigned int crc, char c)
 
 	return crc;
 
-}  /* update_crc_32 */
+} /* update_crc_32 */
 
 /*
  *******************************************************************
@@ -2437,16 +2257,13 @@ unsigned int update_crc_32(unsigned int crc, char c)
  */
 static void init_crc32_tab(void)
 {
-
 	int i, j;
 	unsigned int crc;
 
 	for (i = 0; i < 256; i++) {
-
 		crc = (unsigned int)i;
 
 		for (j = 0; j < 8; j++) {
-
 			if (crc & 0x00000001L)
 				crc = (crc >> 1) ^ P_32;
 			else
@@ -2458,7 +2275,7 @@ static void init_crc32_tab(void)
 
 	crc_tab32_init = TRUE;
 
-}  /* init_crc32_tab */
+} /* init_crc32_tab */
 
 /*
  *******************************************************************
@@ -2473,14 +2290,13 @@ static void init_crc32_tab(void)
 
 unsigned int finalize_crc_32(unsigned int crc)
 {
-
 	int i;
 	unsigned int result = 0;
 
 	for (i = 0; i < NUM_OF_BYTES; i++)
-		SET_VAR_BIT(result, NUM_OF_BYTES - (i+1), READ_VAR_BIT(crc, i));
+		SET_VAR_BIT(result, NUM_OF_BYTES - (i + 1),
+			    READ_VAR_BIT(crc, i));
 
 	return result;
 
-}  /* finalize_crc_32 */
-
+} /* finalize_crc_32 */
diff --git a/util/ecst.h b/util/ecst.h
index 04d696c7c5..49e4b0d55e 100644
--- a/util/ecst.h
+++ b/util/ecst.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,154 +11,152 @@
   Includes
   --------------------------------------------------------------------------*/
 
+#include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
-#include <stdio.h>
-#include <curses.h>
 
+#include <curses.h>
 
 /*---------------------------------------------------------------------------
   Defines
   --------------------------------------------------------------------------*/
 
 /* For the beauty */
-#define TRUE                            1
-#define FALSE                           0
+#define TRUE 1
+#define FALSE 0
 
 /* CHANGEME when the version is updated */
-#define T_VER                           1
-#define T_REV_MAJOR                     0
-#define T_REV_MINOR                     3
+#define T_VER 1
+#define T_REV_MAJOR 0
+#define T_REV_MINOR 3
 
 /* Header starts by default at 0x20000 */
-#define FIRMWARE_OFFSET_FROM_HEADER     0x40
+#define FIRMWARE_OFFSET_FROM_HEADER 0x40
 
-#define ARM_FW_ENTRY_POINT_OFFSET       0x04
+#define ARM_FW_ENTRY_POINT_OFFSET 0x04
 
 /* Some useful offsets inside the header */
-#define	HDR_ANCHOR_OFFSET                    0
-#define	HDR_EXTENDED_ANCHOR_OFFSET           4
-#define	HDR_SPI_MAX_CLK_OFFSET               6
-#define	HDR_SPI_READ_MODE_OFFSET             7
-#define	HDR_ERR_DETECTION_CONF_OFFSET        8
-#define	HDR_FW_LOAD_START_ADDR_OFFSET        9
-#define	HDR_FW_ENTRY_POINT_OFFSET            13
-#define	HDR_FW_ERR_DETECT_START_ADDR_OFFSET  17
-#define	HDR_FW_ERR_DETECT_END_ADDR_OFFSET    21
-#define	HDR_FW_LENGTH_OFFSET                 25
-#define	HDR_FLASH_SIZE_OFFSET                29
-#define HDR_RESERVED                         30
-#define	HDR_FW_HEADER_SIG_OFFSET             56
-#define HDR_FW_IMAGE_SIG_OFFSET              60
-
-
-#define FIRMW_CKSM_OFFSET               0x3C
+#define HDR_ANCHOR_OFFSET 0
+#define HDR_EXTENDED_ANCHOR_OFFSET 4
+#define HDR_SPI_MAX_CLK_OFFSET 6
+#define HDR_SPI_READ_MODE_OFFSET 7
+#define HDR_ERR_DETECTION_CONF_OFFSET 8
+#define HDR_FW_LOAD_START_ADDR_OFFSET 9
+#define HDR_FW_ENTRY_POINT_OFFSET 13
+#define HDR_FW_ERR_DETECT_START_ADDR_OFFSET 17
+#define HDR_FW_ERR_DETECT_END_ADDR_OFFSET 21
+#define HDR_FW_LENGTH_OFFSET 25
+#define HDR_FLASH_SIZE_OFFSET 29
+#define HDR_RESERVED 30
+#define HDR_FW_HEADER_SIG_OFFSET 56
+#define HDR_FW_IMAGE_SIG_OFFSET 60
+
+#define FIRMW_CKSM_OFFSET 0x3C
 
 /* Header field known values */
-#define FW_HDR_ANCHOR                   0x2A3B4D5E
-#define FW_HDR_EXT_ANCHOR_ENABLE        0xAB1E
-#define FW_HDR_EXT_ANCHOR_DISABLE       0x54E1
-#define FW_CRC_DISABLE                  0x00
-#define FW_CRC_ENABLE                   0x02
-#define HEADER_CRC_FIELDS_SIZE          8
+#define FW_HDR_ANCHOR 0x2A3B4D5E
+#define FW_HDR_EXT_ANCHOR_ENABLE 0xAB1E
+#define FW_HDR_EXT_ANCHOR_DISABLE 0x54E1
+#define FW_CRC_DISABLE 0x00
+#define FW_CRC_ENABLE 0x02
+#define HEADER_CRC_FIELDS_SIZE 8
 
-#define HDR_PTR_SIGNATURE               0x55AA650E
+#define HDR_PTR_SIGNATURE 0x55AA650E
 
-#define CKSMCRC_INV_BIT_OFFSET          0x1
+#define CKSMCRC_INV_BIT_OFFSET 0x1
 
 /* Some common Sizes */
-#define STR_SIZE                        200
-#define	ARG_SIZE                        100
-#define NAME_SIZE                       160
-#define BUFF_SIZE                       0x400
-#define HEADER_SIZE                     64
-#define TMP_STR_SIZE                    20
-#define PAD_VALUE                       0x00
+#define STR_SIZE 200
+#define ARG_SIZE 100
+#define NAME_SIZE 160
+#define BUFF_SIZE 0x400
+#define HEADER_SIZE 64
+#define TMP_STR_SIZE 21
+#define PAD_VALUE 0x00
 
-
-#define MAX_ARGS                        100
+#define MAX_ARGS 100
 
 /* Text Colors */
-#define TDBG                            0x02  /* Dark Green     */
-#define TPAS                            0x0A  /* light green    */
-#define TINF                            0x0B  /* light turquise */
-#define TERR                            0x0C  /* light red      */
-#define TUSG                            0x0E  /* light yellow   */
+#define TDBG 0x02 /* Dark Green     */
+#define TPAS 0x0A /* light green    */
+#define TINF 0x0B /* light turquise */
+#define TERR 0x0C /* light red      */
+#define TUSG 0x0E /* light yellow   */
 
 /* Indicates bin Command line parameters */
-#define BIN_FW_HDR_CRC_DISABLE          0x0001
-#define BIN_FW_CRC_DISABLE              0x0002
-#define BIN_FW_START                    0x0004
-#define BIN_FW_SIZE                     0x0008
-#define BIN_CK_FIRMWARE                 0x0010
-#define BIN_FW_CKS_START                0x0020
-#define BIN_FW_CKS_SIZE                 0x0040
-#define BIN_FW_CHANGE_SIG               0x0080
-#define BIN_FW_SPI_MAX_CLK              0x0100
-#define BIN_FW_LOAD_START_ADDR          0x0200
-#define BIN_FW_ENTRY_POINT              0x0400
-#define BIN_FW_LENGTH                   0x0800
-#define BIN_FW_HDR_OFFSET               0x1000
-#define	BIN_FW_USER_ARM_RESET           0x2000
-#define BIN_UNLIM_BURST_ENABLE          0x4000
-
-#define ECRP_OFFSET                     0x01
-#define ECRP_INPUT_FILE                 0x02
-#define ECRP_OUTPUT_FILE                0x04
-
-#define SPI_MAX_CLOCK_20_MHZ_VAL        20
-#define SPI_MAX_CLOCK_25_MHZ_VAL        25
-#define SPI_MAX_CLOCK_33_MHZ_VAL        33
-#define SPI_MAX_CLOCK_40_MHZ_VAL        40
-#define SPI_MAX_CLOCK_50_MHZ_VAL        50
-
-#define SPI_MAX_CLOCK_20_MHZ            0x00
-#define SPI_MAX_CLOCK_25_MHZ            0x01
-#define SPI_MAX_CLOCK_33_MHZ            0x02
-#define SPI_MAX_CLOCK_40_MHZ            0x03
-#define SPI_MAX_CLOCK_50_MHZ            0x04
-#define SPI_MAX_CLOCK_MASK              0xF8
-
-#define SPI_CLOCK_RATIO_1_VAL           1
-#define SPI_CLOCK_RATIO_2_VAL           2
-
-#define SPI_CLOCK_RATIO_1               0x07
-#define SPI_CLOCK_RATIO_2               0x08
-
-#define SPI_NORMAL_MODE_VAL             "normal"
-#define SPI_SINGLE_MODE_VAL             "fast"
-#define SPI_DUAL_MODE_VAL               "dual"
-#define SPI_QUAD_MODE_VAL               "quad"
-
-#define SPI_NORMAL_MODE                 0x00
-#define SPI_SINGLE_MODE                 0x01
-#define SPI_DUAL_MODE                   0x03
-#define SPI_QUAD_MODE                   0x04
-
-#define SPI_UNLIMITED_BURST_ENABLE      0x08
-
-#define FLASH_SIZE_1_MBYTES_VAL         1
-#define FLASH_SIZE_2_MBYTES_VAL         2
-#define FLASH_SIZE_4_MBYTES_VAL         4
-#define FLASH_SIZE_8_MBYTES_VAL         8
-#define FLASH_SIZE_16_MBYTES_VAL        16
-
-#define FLASH_SIZE_1_MBYTES             0x01
-#define FLASH_SIZE_2_MBYTES             0x03
-#define FLASH_SIZE_4_MBYTES             0x07
-#define FLASH_SIZE_8_MBYTES             0x0F
-#define FLASH_SIZE_16_MBYTES            0x1F
+#define BIN_FW_HDR_CRC_DISABLE 0x0001
+#define BIN_FW_CRC_DISABLE 0x0002
+#define BIN_FW_START 0x0004
+#define BIN_FW_SIZE 0x0008
+#define BIN_CK_FIRMWARE 0x0010
+#define BIN_FW_CKS_START 0x0020
+#define BIN_FW_CKS_SIZE 0x0040
+#define BIN_FW_CHANGE_SIG 0x0080
+#define BIN_FW_SPI_MAX_CLK 0x0100
+#define BIN_FW_LOAD_START_ADDR 0x0200
+#define BIN_FW_ENTRY_POINT 0x0400
+#define BIN_FW_LENGTH 0x0800
+#define BIN_FW_HDR_OFFSET 0x1000
+#define BIN_FW_USER_ARM_RESET 0x2000
+#define BIN_UNLIM_BURST_ENABLE 0x4000
+
+#define ECRP_OFFSET 0x01
+#define ECRP_INPUT_FILE 0x02
+#define ECRP_OUTPUT_FILE 0x04
+
+#define SPI_MAX_CLOCK_20_MHZ_VAL 20
+#define SPI_MAX_CLOCK_25_MHZ_VAL 25
+#define SPI_MAX_CLOCK_33_MHZ_VAL 33
+#define SPI_MAX_CLOCK_40_MHZ_VAL 40
+#define SPI_MAX_CLOCK_50_MHZ_VAL 50
+
+#define SPI_MAX_CLOCK_20_MHZ 0x00
+#define SPI_MAX_CLOCK_25_MHZ 0x01
+#define SPI_MAX_CLOCK_33_MHZ 0x02
+#define SPI_MAX_CLOCK_40_MHZ 0x03
+#define SPI_MAX_CLOCK_50_MHZ 0x04
+#define SPI_MAX_CLOCK_MASK 0xF8
+
+#define SPI_CLOCK_RATIO_1_VAL 1
+#define SPI_CLOCK_RATIO_2_VAL 2
+
+#define SPI_CLOCK_RATIO_1 0x07
+#define SPI_CLOCK_RATIO_2 0x08
+
+#define SPI_NORMAL_MODE_VAL "normal"
+#define SPI_SINGLE_MODE_VAL "fast"
+#define SPI_DUAL_MODE_VAL "dual"
+#define SPI_QUAD_MODE_VAL "quad"
+
+#define SPI_NORMAL_MODE 0x00
+#define SPI_SINGLE_MODE 0x01
+#define SPI_DUAL_MODE 0x03
+#define SPI_QUAD_MODE 0x04
+
+#define SPI_UNLIMITED_BURST_ENABLE 0x08
+
+#define FLASH_SIZE_1_MBYTES_VAL 1
+#define FLASH_SIZE_2_MBYTES_VAL 2
+#define FLASH_SIZE_4_MBYTES_VAL 4
+#define FLASH_SIZE_8_MBYTES_VAL 8
+#define FLASH_SIZE_16_MBYTES_VAL 16
+
+#define FLASH_SIZE_1_MBYTES 0x01
+#define FLASH_SIZE_2_MBYTES 0x03
+#define FLASH_SIZE_4_MBYTES 0x07
+#define FLASH_SIZE_8_MBYTES 0x0F
+#define FLASH_SIZE_16_MBYTES 0x1F
 
 /* Header fields default values. */
-#define SPI_MAX_CLOCK_DEFAULT           SPI_MAX_CLOCK_20_MHZ_VAL
-#define SPI_READ_MODE_DEFAULT           SPI_NORMAL_MODE
-#define FLASH_SIZE_DEFAULT              FLASH_SIZE_16_MBYTES_VAL
-#define	FW_CRC_START_ADDR               0x00000000
+#define SPI_MAX_CLOCK_DEFAULT SPI_MAX_CLOCK_20_MHZ_VAL
+#define SPI_READ_MODE_DEFAULT SPI_NORMAL_MODE
+#define FLASH_SIZE_DEFAULT FLASH_SIZE_16_MBYTES_VAL
+#define FW_CRC_START_ADDR 0x00000000
 
-#define ADDR_16_BYTES_ALIGNED_MASK      0x0000000F
-#define ADDR_4_BYTES_ALIGNED_MASK       0x00000003
+#define ADDR_16_BYTES_ALIGNED_MASK 0x0000000F
+#define ADDR_4_BYTES_ALIGNED_MASK 0x00000003
 
-#define MAX_FLASH_SIZE                  0x03ffffff
+#define MAX_FLASH_SIZE 0x03ffffff
 
 /* Chips: convert from name to index. */
 enum npcx_chip_ram_variant {
@@ -169,28 +167,32 @@ enum npcx_chip_ram_variant {
 	NPCX7M7 = 4,
 	NPCX9M3 = 5,
 	NPCX9M6 = 6,
+	NPCX9M7 = 7,
+	NPCX9M8 = 8,
 	NPCX_CHIP_RAM_VAR_NONE
 };
 
-#define DEFAULT_CHIP                    NPCX5M5G
+#define DEFAULT_CHIP NPCX5M5G
 
 /* NPCX5 */
-#define NPCX5M5G_RAM_ADDR               0x100A8000
-#define NPCX5M5G_RAM_SIZE               0x20000
-#define NPCX5M6G_RAM_ADDR               0x10088000
-#define NPCX5M6G_RAM_SIZE               0x40000
+#define NPCX5M5G_RAM_ADDR 0x100A8000
+#define NPCX5M5G_RAM_SIZE 0x20000
+#define NPCX5M6G_RAM_ADDR 0x10088000
+#define NPCX5M6G_RAM_SIZE 0x40000
 /* NPCX7 */
-#define NPCX7M5X_RAM_ADDR               0x100A8000
-#define NPCX7M5X_RAM_SIZE               0x20000
-#define NPCX7M6X_RAM_ADDR               0x10090000
-#define NPCX7M6X_RAM_SIZE               0x40000
-#define NPCX7M7X_RAM_ADDR               0x10070000
-#define NPCX7M7X_RAM_SIZE               0x60000
+#define NPCX7M5X_RAM_ADDR 0x100A8000
+#define NPCX7M5X_RAM_SIZE 0x20000
+#define NPCX7M6X_RAM_ADDR 0x10090000
+#define NPCX7M6X_RAM_SIZE 0x40000
+#define NPCX7M7X_RAM_ADDR 0x10070000
+#define NPCX7M7X_RAM_SIZE 0x60000
 /* NPCX9 */
-#define NPCX9M3X_RAM_ADDR               0x10080000
-#define NPCX9M3X_RAM_SIZE               0x50000
-#define NPCX9M6X_RAM_ADDR               0x10090000
-#define NPCX9M6X_RAM_SIZE               0x40000
+#define NPCX9M3X_RAM_ADDR 0x10080000
+#define NPCX9M3X_RAM_SIZE 0x50000
+#define NPCX9M6X_RAM_ADDR 0x10090000
+#define NPCX9M6X_RAM_SIZE 0x40000
+#define NPCX9M8X_RAM_ADDR 0x10058000
+#define NPCX9M8X_RAM_SIZE 0x80000
 
 /*---------------------------------------------------------------------------
   Typedefs
@@ -198,47 +200,39 @@ enum npcx_chip_ram_variant {
 
 /* Parameters for Binary manipulation */
 struct tbinparams {
-	unsigned int	anchor;
-	unsigned short	ext_anchor;
-	unsigned char	spi_max_clk;
-	unsigned char	spi_clk_ratio;
-	unsigned char	spi_read_mode;
-	unsigned char	err_detec_cnf;
-	unsigned int	fw_load_addr;
-	unsigned int	fw_ep;
-	unsigned int	fw_err_detec_s_addr;
-	unsigned int	fw_err_detec_e_addr;
-	unsigned int	fw_len;
-	unsigned int	flash_size;
-	unsigned int	hdr_crc;
-	unsigned int	fw_crc;
-	unsigned int	fw_hdr_offset;
-	unsigned int	bin_params;
+	unsigned int anchor;
+	unsigned short ext_anchor;
+	unsigned char spi_max_clk;
+	unsigned char spi_clk_ratio;
+	unsigned char spi_read_mode;
+	unsigned char err_detec_cnf;
+	unsigned int fw_load_addr;
+	unsigned int fw_ep;
+	unsigned int fw_err_detec_s_addr;
+	unsigned int fw_err_detec_e_addr;
+	unsigned int fw_len;
+	unsigned int flash_size;
+	unsigned int hdr_crc;
+	unsigned int fw_crc;
+	unsigned int fw_hdr_offset;
+	unsigned int bin_params;
 } bin_params_struct;
 
-enum verbose_level {
-	NO_VERBOSE = 0,
-	REGULAR_VERBOSE,
-	SUPER_VERBOSE
-};
+enum verbose_level { NO_VERBOSE = 0, REGULAR_VERBOSE, SUPER_VERBOSE };
 
-enum calc_type {
-	CALC_TYPE_NONE	= 0,
-	CALC_TYPE_CHECKSUM ,
-	CALC_TYPE_CRC
-};
+enum calc_type { CALC_TYPE_NONE = 0, CALC_TYPE_CHECKSUM, CALC_TYPE_CRC };
 
 struct chip_info {
-	unsigned int	ram_addr;
-	unsigned int   ram_size;
+	unsigned int ram_addr;
+	unsigned int ram_size;
 } chip_info_struct;
 
 /*------------------------------------------------------------------------*/
 /* CRC Variable bit operation macros                                      */
 /*------------------------------------------------------------------------*/
-#define NUM_OF_BYTES					32
-#define READ_VAR_BIT(var, nb)			(((var) >> (nb)) & 0x1)
-#define SET_VAR_BIT(var, nb, val)		((var) |= ((val)<<(nb)))
+#define NUM_OF_BYTES 32
+#define READ_VAR_BIT(var, nb) (((var) >> (nb)) & 0x1)
+#define SET_VAR_BIT(var, nb, val) ((var) |= ((val) << (nb)))
 
 /*---------------------------------------------------------------------------
   Functions Declaration
@@ -254,35 +248,27 @@ void init_calculation(unsigned int *check_sum_crc);
 void finalize_calculation(unsigned int *check_sum_crc);
 void update_calculation_information(unsigned char crc_con_dat);
 
-
 /* Checksum calculation etc. (BIN Specific) */
 int calc_header_crc_bin(unsigned int *pointer_header_checksum);
-int calc_firmware_csum_bin(unsigned int *p_cksum,
-						   unsigned int fw_offset,
-						   unsigned int fw_length);
+int calc_firmware_csum_bin(unsigned int *p_cksum, unsigned int fw_offset,
+			   unsigned int fw_length);
 
 /* Checksum calculation etc. (ERP Specific) */
 int calc_erp_csum_bin(unsigned short *region_pointer_header_checksum,
-					  unsigned int region_pointer_ofs);
+		      unsigned int region_pointer_ofs);
 
 /* No words - General */
 void exit_with_usage(void);
-int copy_file_to_file(char *dst_file_name,
-					  char *src_file_name,
-					  int offset,
-					  int origin);
-int write_to_file(unsigned int write_value,
-				  unsigned int offset,
-				  unsigned char num_of_bytes,
-				  char *print_string);
-int read_from_file(unsigned int offset,
-				   unsigned char size_to_read,
-				   unsigned int *read_value,
-				   char *print_string);
+int copy_file_to_file(char *dst_file_name, char *src_file_name, int offset,
+		      int origin);
+int write_to_file(unsigned int write_value, unsigned int offset,
+		  unsigned char num_of_bytes, char *print_string);
+int read_from_file(unsigned int offset, unsigned char size_to_read,
+		   unsigned int *read_value, char *print_string);
 
 /* Nice Particular Printf - General */
-__attribute__((__format__(__printf__, 2, 3)))
-void my_printf(int error_level, char *fmt, ...);
+__attribute__((__format__(__printf__, 2, 3))) void my_printf(int error_level,
+							     char *fmt, ...);
 
 int str_cmp_no_case(const char *s1, const char *s2);
 int get_file_length(FILE *stream);
diff --git a/util/ectool.c b/util/ectool.c
deleted file mode 100644
index 6d2a74d94e..0000000000
--- a/util/ectool.c
+++ /dev/null
@@ -1,10295 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <ctype.h>
-#include <errno.h>
-#include <getopt.h>
-#include <inttypes.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <time.h>
-#include <unistd.h>
-#include <signal.h>
-#include <stdbool.h>
-
-#include "battery.h"
-#include "comm-host.h"
-#include "chipset.h"
-#include "compile_time_macros.h"
-#include "cros_ec_dev.h"
-#include "ec_panicinfo.h"
-#include "ec_flash.h"
-#include "ec_version.h"
-#include "ectool.h"
-#include "i2c.h"
-#include "lightbar.h"
-#include "lock/gec_lock.h"
-#include "misc_util.h"
-#include "panic.h"
-#include "usb_pd.h"
-
-/* Maximum flash size (16 MB, conservative) */
-#define MAX_FLASH_SIZE 0x1000000
-
-/*
- * Calculate the expected response for a hello ec command.
- */
-#define HELLO_RESP(in_data) ((in_data) + 0x01020304)
-
-/* Command line options */
-enum {
-	OPT_DEV = 1000,
-	OPT_INTERFACE,
-	OPT_NAME,
-	OPT_ASCII,
-	OPT_I2C_BUS,
-};
-
-static struct option long_opts[] = {
-	{"dev", 1, 0, OPT_DEV},
-	{"interface", 1, 0, OPT_INTERFACE},
-	{"name", 1, 0, OPT_NAME},
-	{"ascii", 0, 0, OPT_ASCII},
-	{"i2c_bus", 1, 0, OPT_I2C_BUS},
-	{NULL, 0, 0, 0}
-};
-
-#define GEC_LOCK_TIMEOUT_SECS	30  /* 30 secs */
-
-const char help_str[] =
-	"Commands:\n"
-	"  adcread <channel>\n"
-	"      Read an ADC channel.\n"
-	"  addentropy [reset]\n"
-	"      Add entropy to device secret\n"
-	"  apreset\n"
-	"      Issue AP reset\n"
-	"  autofanctrl <on>\n"
-	"      Turn on automatic fan speed control.\n"
-	"  backlight <enabled>\n"
-	"      Enable/disable LCD backlight\n"
-	"  battery\n"
-	"      Prints battery info\n"
-	"  batterycutoff [at-shutdown]\n"
-	"      Cut off battery output power\n"
-	"  batteryparam\n"
-	"      Read or write board-specific battery parameter\n"
-	"  boardversion\n"
-	"      Prints the board version\n"
-	"  button [vup|vdown|rec] <Delay-ms>\n"
-	"      Simulates button press.\n"
-	"  cbi\n"
-	"      Get/Set/Remove Cros Board Info\n"
-	"  chargecurrentlimit\n"
-	"      Set the maximum battery charging current\n"
-	"  chargecontrol\n"
-	"      Force the battery to stop charging or discharge\n"
-	"  chargeoverride\n"
-	"      Overrides charge port selection logic\n"
-	"  chargestate\n"
-	"      Handle commands related to charge state v2 (and later)\n"
-	"  chipinfo\n"
-	"      Prints chip info\n"
-	"  cmdversions <cmd>\n"
-	"      Prints supported version mask for a command number\n"
-	"  console\n"
-	"      Prints the last output to the EC debug console\n"
-	"  cec\n"
-	"      Read or write CEC messages and settings\n"
-	"  echash [CMDS]\n"
-	"      Various EC hash commands\n"
-	"  eventclear <mask>\n"
-	"      Clears EC host events flags where mask has bits set\n"
-	"  eventclearb <mask>\n"
-	"      Clears EC host events flags copy B where mask has bits set\n"
-	"  eventget\n"
-	"      Prints raw EC host event flags\n"
-	"  eventgetb\n"
-	"      Prints raw EC host event flags copy B\n"
-	"  eventgetscimask\n"
-	"      Prints SCI mask for EC host events\n"
-	"  eventgetsmimask\n"
-	"      Prints SMI mask for EC host events\n"
-	"  eventgetwakemask\n"
-	"      Prints wake mask for EC host events\n"
-	"  eventsetscimask <mask>\n"
-	"      Sets the SCI mask for EC host events\n"
-	"  eventsetsmimask <mask>\n"
-	"      Sets the SMI mask for EC host events\n"
-	"  eventsetwakemask <mask>\n"
-	"      Sets the wake mask for EC host events\n"
-	"  extpwrlimit\n"
-	"      Set the maximum external power limit\n"
-	"  fanduty <percent>\n"
-	"      Forces the fan PWM to a constant duty cycle\n"
-	"  flasherase <offset> <size>\n"
-	"      Erases EC flash\n"
-	"  flasheraseasync <offset> <size>\n"
-	"      Erases EC flash asynchronously\n"
-	"  flashinfo\n"
-	"      Prints information on the EC flash\n"
-	"  flashspiinfo\n"
-	"      Prints information on EC SPI flash, if present\n"
-	"  flashpd <dev_id> <port> <filename>\n"
-	"      Flash commands over PD\n"
-	"  flashprotect [now] [enable | disable]\n"
-	"      Prints or sets EC flash protection state\n"
-	"  flashread <offset> <size> <outfile>\n"
-	"      Reads from EC flash to a file\n"
-	"  flashwrite <offset> <infile>\n"
-	"      Writes to EC flash from a file\n"
-	"  forcelidopen <enable>\n"
-	"      Forces the lid switch to open position\n"
-	"  fpcontext\n"
-	"      Sets the fingerprint sensor context\n"
-	"  fpencstatus\n"
-	"      Prints status of Fingerprint sensor encryption engine\n"
-	"  fpframe\n"
-	"      Retrieve the finger image as a PGM image\n"
-	"  fpinfo\n"
-	"      Prints information about the Fingerprint sensor\n"
-	"  fpmode [capture|deepsleep|fingerdown|fingerup]\n"
-	"      Configure/Read the fingerprint sensor current mode\n"
-	"  fpseed\n"
-	"      Sets the value of the TPM seed.\n"
-	"  fpstats\n"
-	"      Prints timing statisitcs relating to capture and matching\n"
-	"  fptemplate [<infile>|<index 0..2>]\n"
-	"      Add a template if <infile> is provided, else dump it\n"
-	"  gpioget <GPIO name>\n"
-	"      Get the value of GPIO signal\n"
-	"  gpioset <GPIO name>\n"
-	"      Set the value of GPIO signal\n"
-	"  hangdetect <flags> <event_msec> <reboot_msec> | stop | start\n"
-	"      Configure or start/stop the hang detect timer\n"
-	"  hello\n"
-	"      Checks for basic communication with EC\n"
-	"  hibdelay [sec]\n"
-	"      Set the delay before going into hibernation\n"
-	"  hostsleepstate\n"
-	"      Report host sleep state to the EC\n"
-	"  hostevent\n"
-	"      Get & set host event masks.\n"
-	"  i2cprotect <port> [status]\n"
-	"      Protect EC's I2C bus\n"
-	"  i2cread\n"
-	"      Read I2C bus\n"
-	"  i2cwrite\n"
-	"      Write I2C bus\n"
-	"  i2cxfer <port> <slave_addr> <read_count> [write bytes...]\n"
-	"      Perform I2C transfer on EC's I2C bus\n"
-	"  infopddev <port>\n"
-	"      Get info about USB type-C accessory attached to port\n"
-	"  inventory\n"
-	"      Return the list of supported features\n"
-	"  kbfactorytest\n"
-	"      Scan out keyboard if any pins are shorted\n"
-	"  kbid\n"
-	"      Get keyboard ID of supported keyboards\n"
-	"  kbinfo\n"
-	"      Dump keyboard matrix dimensions\n"
-	"  kbpress\n"
-	"      Simulate key press\n"
-	"  keyscan <beat_us> <filename>\n"
-	"      Test low-level key scanning\n"
-	"  led <name> <query | auto | off | <color> | <color>=<value>...>\n"
-	"      Set the color of an LED or query brightness range\n"
-	"  lightbar [CMDS]\n"
-	"      Various lightbar control commands\n"
-	"  mkbpget <buttons|switches>\n"
-	"      Get MKBP buttons/switches supported mask and current state\n"
-	"  mkbpwakemask <get|set> <event|hostevent> [mask]\n"
-	"      Get or Set the MKBP event wake mask, or host event wake mask\n"
-	"  motionsense [CMDS]\n"
-	"      Various motion sense control commands\n"
-	"  panicinfo\n"
-	"      Prints saved panic info\n"
-	"  pause_in_s5 [on|off]\n"
-	"      Whether or not the AP should pause in S5 on shutdown\n"
-	"  pdcontrol [suspend|resume|reset|disable|on]\n"
-	"      Controls the PD chip\n"
-	"  pdchipinfo <port>\n"
-	"      Get PD chip information\n"
-	"  pdlog\n"
-	"      Prints the PD event log entries\n"
-	"  pdwritelog <type> <port>\n"
-	"      Writes a PD event log of the given <type>\n"
-	"  pdgetmode <port>\n"
-	"      Get All USB-PD alternate SVIDs and modes on <port>\n"
-	"  pdsetmode <port> <svid> <opos>\n"
-	"      Set USB-PD alternate SVID and mode on <port>\n"
-	"  port80flood\n"
-	"      Rapidly write bytes to port 80\n"
-	"  port80read\n"
-	"      Print history of port 80 write\n"
-	"  powerinfo\n"
-	"      Prints power-related information\n"
-	"  protoinfo\n"
-	"       Prints EC host protocol information\n"
-	"  pse\n"
-	"      Get and set PoE PSE port power status\n"
-	"  pstoreinfo\n"
-	"      Prints information on the EC host persistent storage\n"
-	"  pstoreread <offset> <size> <outfile>\n"
-	"      Reads from EC host persistent storage to a file\n"
-	"  pstorewrite <offset> <infile>\n"
-	"      Writes to EC host persistent storage from a file\n"
-	"  pwmgetfanrpm [<index> | all]\n"
-	"      Prints current fan RPM\n"
-	"  pwmgetkblight\n"
-	"      Prints current keyboard backlight percent\n"
-	"  pwmgetnumfans\n"
-	"      Prints the number of fans present\n"
-	"  pwmgetduty\n"
-	"      Prints the current 16 bit duty cycle for given PWM\n"
-	"  pwmsetfanrpm <targetrpm>\n"
-	"      Set target fan RPM\n"
-	"  pwmsetkblight <percent>\n"
-	"      Set keyboard backlight in percent\n"
-	"  pwmsetduty\n"
-	"      Set 16 bit duty cycle of given PWM\n"
-	"  rand <num_bytes>\n"
-	"      generate <num_bytes> of random numbers\n"
-	"  readtest <patternoffset> <size>\n"
-	"      Reads a pattern from the EC via LPC\n"
-	"  reboot_ec <RO|RW|cold|hibernate|hibernate-clear-ap-off|disable-jump>"
-			" [at-shutdown|switch-slot]\n"
-	"      Reboot EC to RO or RW\n"
-	"  reboot_ap_on_g3\n"
-	"      Requests that the EC will automatically reboot the AP the next time\n"
-	"      we enter the G3 power state.\n"
-	"  rollbackinfo\n"
-	"      Print rollback block information\n"
-	"  rtcget\n"
-	"      Print real-time clock\n"
-	"  rtcgetalarm\n"
-	"      Print # of seconds before real-time clock alarm goes off.\n"
-	"  rtcset <time>\n"
-	"      Set real-time clock\n"
-	"  rtcsetalarm <sec>\n"
-	"      Set real-time clock alarm to go off in <sec> seconds\n"
-	"  rwhashpd <dev_id> <HASH[0] ... <HASH[4]>\n"
-	"      Set entry in PD MCU's device rw_hash table.\n"
-	"  rwsig <info|dump|action|status> ...\n"
-	"      info: get all info about rwsig\n"
-	"      dump: show individual rwsig field\n"
-	"      action: Control the behavior of RWSIG task.\n"
-	"      status: Run RW signature verification and get status.\n{"
-	"  rwsigaction (DEPRECATED; use \"rwsig action\")\n"
-	"      Control the behavior of RWSIG task.\n"
-	"  rwsigstatus (DEPRECATED; use \"rwsig status\"\n"
-	"      Run RW signature verification and get status.\n"
-	"  sertest\n"
-	"      Serial output test for COM2\n"
-	"  smartdischarge\n"
-	"      Set/Get smart discharge parameters\n"
-	"  stress [reboot] [help]\n"
-	"      Stress test the ec host command interface.\n"
-	"  sysinfo [flags|reset_flags|firmware_copy]\n"
-	"      Display system info.\n"
-	"  switches\n"
-	"      Prints current EC switch positions\n"
-	"  temps <sensorid>\n"
-	"      Print temperature.\n"
-	"  tempsinfo <sensorid>\n"
-	"      Print temperature sensor info.\n"
-	"  thermalget <platform-specific args>\n"
-	"      Get the threshold temperature values from the thermal engine.\n"
-	"  thermalset <platform-specific args>\n"
-	"      Set the threshold temperature values for the thermal engine.\n"
-	"  tpselftest\n"
-	"      Run touchpad self test.\n"
-	"  tpframeget\n"
-	"      Get touchpad frame data.\n"
-	"  tmp006cal <tmp006_index> [params...]\n"
-	"      Get/set TMP006 calibration\n"
-	"  tmp006raw <tmp006_index>\n"
-	"      Get raw TMP006 data\n"
-	"  typeccontrol <port> <command>\n"
-	"      Control USB PD policy\n"
-	"  typecdiscovery <port> <type>\n"
-	"      Get discovery information for port and type\n"
-	"  typecstatus <port>\n"
-	"      Get status information for port\n"
-	"  uptimeinfo\n"
-	"      Get info about how long the EC has been running and the most\n"
-	"      recent AP resets\n"
-	"  usbchargemode <port> <mode> [<inhibit_charge>]\n"
-	"      Set USB charging mode\n"
-	"  usbmux <mux>\n"
-	"      Set USB mux switch state\n"
-	"  usbpd <port> <auto | "
-			"[toggle|toggle-off|sink|source] [none|usb|dp|dock] "
-			"[dr_swap|pr_swap|vconn_swap]>\n"
-	"      Control USB PD/type-C [deprecated]\n"
-	"  usbpdmuxinfo\n"
-	"      Get USB-C SS mux info\n"
-	"  usbpdpower [port]\n"
-	"      Get USB PD power information\n"
-	"  version\n"
-	"      Prints EC version\n"
-	"  waitevent <type> [<timeout>]\n"
-	"      Wait for the MKBP event of type and display it\n"
-	"  wireless <flags> [<mask> [<suspend_flags> <suspend_mask>]]\n"
-	"      Enable/disable WLAN/Bluetooth radio\n"
-	"";
-
-/* Note: depends on enum ec_image */
-static const char * const image_names[] = {"unknown", "RO", "RW"};
-
-/* Note: depends on enum ec_led_colors */
-static const char * const led_color_names[] = {
-	"red", "green", "blue", "yellow", "white", "amber"};
-BUILD_ASSERT(ARRAY_SIZE(led_color_names) == EC_LED_COLOR_COUNT);
-
-/* Note: depends on enum ec_led_id */
-static const char * const led_names[] = {
-	"battery", "power", "adapter", "left", "right", "recovery_hwreinit",
-	"sysrq debug" };
-BUILD_ASSERT(ARRAY_SIZE(led_names) == EC_LED_ID_COUNT);
-
-/* ASCII mode for printing, default off */
-static int ascii_mode = 0;
-
-/* Check SBS numerical value range */
-int is_battery_range(int val)
-{
-	return (val >= 0 && val <= 65535) ? 1 : 0;
-}
-
-int parse_bool(const char *s, int *dest)
-{
-	if (!strcasecmp(s, "off") || !strncasecmp(s, "dis", 3) ||
-	    tolower(*s) == 'f' || tolower(*s) == 'n') {
-		*dest = 0;
-		return 1;
-	} else if (!strcasecmp(s, "on") || !strncasecmp(s, "ena", 3) ||
-	    tolower(*s) == 't' || tolower(*s) == 'y') {
-		*dest = 1;
-		return 1;
-	} else {
-		return 0;
-	}
-}
-
-void print_help(const char *prog, int print_cmds)
-{
-	printf("Usage: %s [--dev=n] [--interface=dev|i2c|lpc] [--i2c_bus=n]",
-	       prog);
-	printf("[--name=cros_ec|cros_fp|cros_pd|cros_scp|cros_ish] [--ascii] ");
-	printf("<command> [params]\n\n");
-	printf("  --i2c_bus=n  Specifies the number of an I2C bus to use. For\n"
-	       "               example, to use /dev/i2c-7, pass --i2c_bus=7.\n"
-	       "               Implies --interface=i2c.\n\n");
-	if (print_cmds)
-		puts(help_str);
-	else
-		printf("Use '%s help' to print a list of commands.\n", prog);
-}
-
-static uint8_t read_mapped_mem8(uint8_t offset)
-{
-	int ret;
-	uint8_t val;
-
-	ret = ec_readmem(offset, sizeof(val), &val);
-	if (ret <= 0) {
-		fprintf(stderr, "failure in %s(): %d\n", __func__, ret);
-		exit(1);
-	}
-	return val;
-}
-
-static uint16_t read_mapped_mem16(uint8_t offset)
-{
-	int ret;
-	uint16_t val;
-
-	ret = ec_readmem(offset, sizeof(val), &val);
-	if (ret <= 0) {
-		fprintf(stderr, "failure in %s(): %d\n", __func__, ret);
-		exit(1);
-	}
-	return val;
-}
-
-static uint32_t read_mapped_mem32(uint8_t offset)
-{
-	int ret;
-	uint32_t val;
-
-	ret = ec_readmem(offset, sizeof(val), &val);
-	if (ret <= 0) {
-		fprintf(stderr, "failure in %s(): %d\n", __func__, ret);
-		exit(1);
-	}
-	return val;
-}
-
-static int read_mapped_string(uint8_t offset, char *buffer, int max_size)
-{
-	int ret;
-
-	ret = ec_readmem(offset, max_size, buffer);
-	if (ret <= 0) {
-		fprintf(stderr, "failure in %s(): %d\n", __func__, ret);
-		exit(1);
-	}
-	return ret;
-}
-
-int cmd_adc_read(int argc, char *argv[])
-{
-	char *e;
-	struct ec_params_adc_read p;
-	struct ec_response_adc_read r;
-	int rv;
-
-	if (argc < 2) {
-		fprintf(stderr, "Usage: %s <adc channel>\n", argv[0]);
-		return -1;
-	}
-
-	p.adc_channel = (uint8_t)strtoul(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "\"%s\": invalid channel!\n", argv[1]);
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_ADC_READ, 0, &p, sizeof(p), &r, sizeof(r));
-	if (rv > 0) {
-		printf("%s: %d\n", argv[1], r.adc_value);
-		return 0;
-	}
-
-	return rv;
-}
-
-int cmd_add_entropy(int argc, char *argv[])
-{
-	struct ec_params_rollback_add_entropy p;
-	int rv;
-	int tries = 100; /* Wait for 10 seconds at most */
-
-	if (argc >= 2 && !strcmp(argv[1], "reset"))
-		p.action = ADD_ENTROPY_RESET_ASYNC;
-	else
-		p.action = ADD_ENTROPY_ASYNC;
-
-	rv = ec_command(EC_CMD_ADD_ENTROPY, 0, &p, sizeof(p), NULL, 0);
-
-	if (rv != EC_RES_SUCCESS)
-		goto out;
-
-	while (tries--) {
-		usleep(100000);
-
-		p.action = ADD_ENTROPY_GET_RESULT;
-		rv = ec_command(EC_CMD_ADD_ENTROPY, 0, &p, sizeof(p), NULL, 0);
-
-		if (rv == EC_RES_SUCCESS) {
-			printf("Entropy added successfully\n");
-			return EC_RES_SUCCESS;
-		}
-
-		/* Abort if EC returns an error other than EC_RES_BUSY. */
-		if (rv <= -EECRESULT && rv != -EECRESULT-EC_RES_BUSY)
-			goto out;
-	}
-
-	rv = -EECRESULT-EC_RES_TIMEOUT;
-out:
-	fprintf(stderr, "Failed to add entropy: %d\n", rv);
-	return rv;
-}
-
-int cmd_hello(int argc, char *argv[])
-{
-	struct ec_params_hello p;
-	struct ec_response_hello r;
-	int rv;
-
-	p.in_data = 0xa0b0c0d0;
-
-	rv = ec_command(EC_CMD_HELLO, 0, &p, sizeof(p), &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	if (r.out_data != 0xa1b2c3d4) {
-		fprintf(stderr, "Expected response 0x%08x, got 0x%08x\n",
-			0xa1b2c3d4, r.out_data);
-		return -1;
-	}
-
-	printf("EC says hello!\n");
-	return 0;
-}
-
-int cmd_hibdelay(int argc, char *argv[])
-{
-	struct ec_params_hibernation_delay p;
-	struct ec_response_hibernation_delay r;
-	char *e;
-	int rv;
-
-	if (argc < 2) {
-		p.seconds = 0; /* Just read the current settings. */
-	} else {
-		p.seconds = strtoul(argv[1], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "invalid number\n");
-			return -1;
-		}
-	}
-
-	rv = ec_command(EC_CMD_HIBERNATION_DELAY, 0, &p, sizeof(p),
-			&r, sizeof(r));
-	if (rv < 0) {
-		fprintf(stderr, "err: rv=%d\n", rv);
-		return -1;
-	}
-
-	printf("Hibernation delay: %u s\n", r.hibernate_delay);
-	printf("Time G3: %u s\n", r.time_g3);
-	printf("Time left: %u s\n", r.time_remaining);
-	return 0;
-}
-
-static void cmd_hostevent_help(char *cmd)
-{
-	fprintf(stderr,
-	"  Usage: %s get <type>\n"
-	"  Usage: %s set <type> <value>\n"
-	"    <type> is one of:\n"
-	"      1: EC_HOST_EVENT_B\n"
-	"      2: EC_HOST_EVENT_SCI_MASK\n"
-	"      3: EC_HOST_EVENT_SMI_MASK\n"
-	"      4: EC_HOST_EVENT_ALWAYS_REPORT_MASK\n"
-	"      5: EC_HOST_EVENT_ACTIVE_WAKE_MASK\n"
-	"      6: EC_HOST_EVENT_LAZY_WAKE_MASK_S0IX\n"
-	"      7: EC_HOST_EVENT_LAZY_WAKE_MASK_S3\n"
-	"      8: EC_HOST_EVENT_LAZY_WAKE_MASK_S5\n"
-		, cmd, cmd);
-}
-
-static int cmd_hostevent(int argc, char *argv[])
-{
-	struct ec_params_host_event p;
-	struct ec_response_host_event r;
-	char *e;
-	int rv;
-
-	if (argc < 2) {
-		fprintf(stderr, "Invalid number of params\n");
-		cmd_hostevent_help(argv[0]);
-		return -1;
-	}
-
-	if (!strcasecmp(argv[1], "get")) {
-		if (argc != 3) {
-			fprintf(stderr, "Invalid number of params\n");
-			cmd_hostevent_help(argv[0]);
-			return -1;
-		}
-		p.action = EC_HOST_EVENT_GET;
-	} else if (!strcasecmp(argv[1], "set")) {
-		if (argc != 4) {
-			fprintf(stderr, "Invalid number of params\n");
-			cmd_hostevent_help(argv[0]);
-			return -1;
-		}
-		p.action = EC_HOST_EVENT_SET;
-		p.value = strtoul(argv[3], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad value\n");
-			return -1;
-		}
-	} else {
-		fprintf(stderr, "Bad subcommand: %s\n", argv[1]);
-		return -1;
-	}
-
-	p.mask_type = strtol(argv[2], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad type\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_HOST_EVENT, 0, &p, sizeof(p), &r, sizeof(r));
-	if (rv == -EC_RES_ACCESS_DENIED - EECRESULT) {
-		fprintf(stderr, "%s isn't permitted for mask %d.\n",
-			p.action == EC_HOST_EVENT_SET ? "Set" : "Get",
-			p.mask_type);
-		return rv;
-	} else if (rv < 0) {
-		return rv;
-	}
-
-	if (p.action == EC_HOST_EVENT_GET)
-		printf("0x%" PRIx64 "\n", r.value);
-
-	return 0;
-}
-
-static int get_latest_cmd_version(uint8_t cmd, int *version)
-{
-	struct ec_params_get_cmd_versions p;
-	struct ec_response_get_cmd_versions r;
-	int rv;
-
-	*version = 0;
-	/* Figure out the latest version of the given command the EC supports */
-	p.cmd = cmd;
-	rv = ec_command(EC_CMD_GET_CMD_VERSIONS, 0, &p, sizeof(p),
-			&r, sizeof(r));
-	if (rv < 0) {
-		if (rv == -EC_RES_INVALID_PARAM)
-			printf("Command 0x%02x not supported by EC.\n",
-					EC_CMD_GET_CMD_VERSIONS);
-		return rv;
-	}
-
-	if (r.version_mask)
-		*version = __fls(r.version_mask);
-
-	return rv;
-}
-
-int cmd_hostsleepstate(int argc, char *argv[])
-{
-	struct ec_params_host_sleep_event p;
-	struct ec_params_host_sleep_event_v1 p1;
-	struct ec_response_host_sleep_event_v1 r;
-	void *pp = &p;
-	size_t psize = sizeof(p), rsize = 0;
-	char *afterscan;
-	int rv;
-	int version = 0, max_version = 0;
-	uint32_t timeout, transitions;
-
-	if (argc < 2) {
-		fprintf(stderr, "Usage: %s "
-			"[suspend|wsuspend|resume|freeze|thaw] [timeout]\n",
-			argv[0]);
-		return -1;
-	}
-
-	rv = get_latest_cmd_version(EC_CMD_HOST_SLEEP_EVENT, &max_version);
-	if (rv < 0)
-		return rv;
-
-	if (!strcmp(argv[1], "suspend"))
-		p.sleep_event = HOST_SLEEP_EVENT_S3_SUSPEND;
-	else if (!strcmp(argv[1], "wsuspend"))
-		p.sleep_event = HOST_SLEEP_EVENT_S3_WAKEABLE_SUSPEND;
-	else if (!strcmp(argv[1], "resume"))
-		p.sleep_event = HOST_SLEEP_EVENT_S3_RESUME;
-	else if (!strcmp(argv[1], "freeze")) {
-		p.sleep_event = HOST_SLEEP_EVENT_S0IX_SUSPEND;
-		if (max_version >= 1) {
-			p1.sleep_event = p.sleep_event;
-			p1.reserved = 0;
-			p1.suspend_params.sleep_timeout_ms =
-				EC_HOST_SLEEP_TIMEOUT_DEFAULT;
-
-			if (argc > 2) {
-				p1.suspend_params.sleep_timeout_ms =
-					strtoul(argv[2], &afterscan, 0);
-
-				if ((*afterscan != '\0') ||
-				    (afterscan == argv[2])) {
-					fprintf(stderr,
-						"Invalid value: %s\n",
-						argv[2]);
-
-					return -1;
-				}
-			}
-
-			pp = &p1;
-			psize = sizeof(p1);
-			version = 1;
-		}
-
-	} else if (!strcmp(argv[1], "thaw")) {
-		p.sleep_event = HOST_SLEEP_EVENT_S0IX_RESUME;
-		if (max_version >= 1) {
-			version = 1;
-			rsize = sizeof(r);
-		}
-	} else {
-		fprintf(stderr, "Unknown command: %s\n", argv[1]);
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_HOST_SLEEP_EVENT, version, pp, psize, &r, rsize);
-	if (rv < 0) {
-		fprintf(stderr, "EC host sleep command failed: %d\n", rv);
-		return rv;
-	}
-
-	if (rsize) {
-		timeout = r.resume_response.sleep_transitions &
-			  EC_HOST_RESUME_SLEEP_TIMEOUT;
-
-		transitions = r.resume_response.sleep_transitions &
-			      EC_HOST_RESUME_SLEEP_TRANSITIONS_MASK;
-
-		printf("%s%d sleep line transitions.\n",
-		       timeout ? "Timeout: " : "",
-		       transitions);
-	}
-
-	return 0;
-}
-
-int cmd_test(int argc, char *argv[])
-{
-	struct ec_params_test_protocol p = {
-		.buf = "0123456789abcdef0123456789ABCDEF"
-	};
-	struct ec_response_test_protocol r;
-	int rv, version = 0;
-	char *e;
-
-	if (argc < 3) {
-		fprintf(stderr, "Usage: %s result length [version]\n",
-			argv[0]);
-		return -1;
-	}
-
-	p.ec_result = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "invalid param (result)\n");
-		return -1;
-	}
-	p.ret_len = strtol(argv[2], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "invalid param (length)\n");
-		return -1;
-	}
-
-	if (argc > 3) {
-		version = strtol(argv[3], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "invalid param (version)\n");
-			return -1;
-		}
-	}
-
-	rv = ec_command(EC_CMD_TEST_PROTOCOL, version,
-			&p, sizeof(p), &r, sizeof(r));
-	printf("rv = %d\n", rv);
-
-	return rv;
-}
-
-int cmd_s5(int argc, char *argv[])
-{
-	struct ec_params_get_set_value p;
-	struct ec_params_get_set_value r;
-	int rv, param;
-
-	p.flags = 0;
-
-	if (argc > 1) {
-		p.flags |= EC_GSV_SET;
-		if (!parse_bool(argv[1], &param)) {
-			fprintf(stderr, "invalid arg \"%s\"\n", argv[1]);
-			return -1;
-		}
-		p.value = param;
-	}
-
-	rv = ec_command(EC_CMD_GSV_PAUSE_IN_S5, 0,
-			&p, sizeof(p), &r, sizeof(r));
-	if (rv > 0)
-		printf("%s\n", r.value ? "on" : "off");
-
-	return rv < 0;
-}
-
-static const char * const ec_feature_names[] = {
-	[EC_FEATURE_LIMITED] = "Limited image, load RW for more",
-	[EC_FEATURE_FLASH] = "Flash",
-	[EC_FEATURE_PWM_FAN] = "Direct Fan power management",
-	[EC_FEATURE_PWM_KEYB] = "Keyboard backlight",
-	[EC_FEATURE_LIGHTBAR] = "Lightbar",
-	[EC_FEATURE_LED] = "LED",
-	[EC_FEATURE_MOTION_SENSE] = "Motion Sensors",
-	[EC_FEATURE_KEYB] = "Keyboard",
-	[EC_FEATURE_PSTORE] = "Host Permanent Storage",
-	[EC_FEATURE_PORT80] = "BIOS Port 80h access",
-	[EC_FEATURE_THERMAL] = "Thermal management",
-	[EC_FEATURE_BKLIGHT_SWITCH] = "Switch backlight on/off",
-	[EC_FEATURE_WIFI_SWITCH] = "Switch wifi on/off",
-	[EC_FEATURE_HOST_EVENTS] = "Host event",
-	[EC_FEATURE_GPIO] = "GPIO",
-	[EC_FEATURE_I2C] = "I2C master",
-	[EC_FEATURE_CHARGER] = "Charger",
-	[EC_FEATURE_BATTERY] = "Simple Battery",
-	[EC_FEATURE_SMART_BATTERY] = "Smart Battery",
-	[EC_FEATURE_HANG_DETECT] = "Host hang detection",
-	[EC_FEATURE_PMU] = "Power Management",
-	[EC_FEATURE_SUB_MCU] = "Control downstream MCU",
-	[EC_FEATURE_USB_PD] = "USB Cros Power Delivery",
-	[EC_FEATURE_USB_MUX] = "USB Multiplexer",
-	[EC_FEATURE_MOTION_SENSE_FIFO] = "FIFO for Motion Sensors events",
-	[EC_FEATURE_VSTORE] = "Temporary secure vstore",
-	[EC_FEATURE_USBC_SS_MUX_VIRTUAL] = "Host-controlled USB-C SS mux",
-	[EC_FEATURE_RTC] = "Real-time clock",
-	[EC_FEATURE_FINGERPRINT] = "Fingerprint",
-	[EC_FEATURE_TOUCHPAD] = "Touchpad",
-	[EC_FEATURE_RWSIG] = "RWSIG task",
-	[EC_FEATURE_DEVICE_EVENT] = "Device events reporting",
-	[EC_FEATURE_UNIFIED_WAKE_MASKS] = "Unified wake masks for LPC/eSPI",
-	[EC_FEATURE_HOST_EVENT64] = "64-bit host events",
-	[EC_FEATURE_EXEC_IN_RAM] = "Execute code in RAM",
-	[EC_FEATURE_CEC] = "Consumer Electronics Control",
-	[EC_FEATURE_MOTION_SENSE_TIGHT_TIMESTAMPS] =
-		"Tight timestamp for sensors events",
-	[EC_FEATURE_REFINED_TABLET_MODE_HYSTERESIS] =
-		"Refined tablet mode hysteresis",
-	[EC_FEATURE_EFS2] = "Early Firmware Selection v2",
-	[EC_FEATURE_ISH] = "Intel Integrated Sensor Hub",
-};
-
-int cmd_inventory(int argc, char *argv[])
-{
-	struct ec_response_get_features r;
-	int rv, i, j, idx;
-
-	rv = ec_command(EC_CMD_GET_FEATURES, 0, NULL, 0, &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	printf("EC supported features:\n");
-	for (i = 0, idx = 0; i < 2; i++) {
-		for (j = 0; j < 32; j++, idx++) {
-			if (r.flags[i] & BIT(j)) {
-				if (idx >= ARRAY_SIZE(ec_feature_names) ||
-				    !ec_feature_names[idx] ||
-				    strlen(ec_feature_names[idx]) == 0)
-					printf("%-4d: Unknown feature\n", idx);
-				else
-					printf("%-4d: %s support\n",
-					       idx, ec_feature_names[idx]);
-			}
-		}
-	}
-	return 0;
-}
-
-
-int cmd_cmdversions(int argc, char *argv[])
-{
-	struct ec_params_get_cmd_versions p;
-	struct ec_response_get_cmd_versions r;
-	char *e;
-	int cmd;
-	int rv;
-
-	if (argc < 2) {
-		fprintf(stderr, "Usage: %s <cmd>\n", argv[0]);
-		return -1;
-	}
-	cmd = strtol(argv[1], &e, 0);
-	if ((e && *e) || cmd < 0 || cmd > 0xff) {
-		fprintf(stderr, "Bad command number.\n");
-		return -1;
-	}
-
-	p.cmd = cmd;
-	rv = ec_command(EC_CMD_GET_CMD_VERSIONS, 0, &p, sizeof(p),
-			&r, sizeof(r));
-	if (rv < 0) {
-		if (rv == -EC_RES_INVALID_PARAM)
-			printf("Command 0x%02x not supported by EC.\n", cmd);
-
-		return rv;
-	}
-
-	printf("Command 0x%02x supports version mask 0x%08x\n",
-	       cmd, r.version_mask);
-	return 0;
-}
-
-/*
- * Convert a reset cause ID to human-readable string, providing total coverage
- * of the 'cause' space.  The returned string points to static storage and must
- * not be free()ed.
- */
-static const char *reset_cause_to_str(uint16_t cause)
-{
-	static const char * const reset_causes[] = {
-		"(reset unknown)",
-		"reset: board custom",
-		"reset: ap hang detected",
-		"reset: console command",
-		"reset: host command",
-		"reset: keyboard sysreset",
-		"reset: keyboard warm reboot",
-		"reset: debug warm reboot",
-		"reset: at AP's request",
-		"reset: during EC initialization",
-		"reset: AP watchdog",
-	};
-	BUILD_ASSERT(ARRAY_SIZE(reset_causes) == CHIPSET_RESET_COUNT);
-
-	static const char * const shutdown_causes[] = {
-		"shutdown: power failure",
-		"shutdown: during EC initialization",
-		"shutdown: board custom",
-		"shutdown: battery voltage startup inhibit",
-		"shutdown: power wait asserted",
-		"shutdown: critical battery",
-		"shutdown: by console command",
-		"shutdown: entering G3",
-		"shutdown: thermal",
-		"shutdown: power button",
-	};
-	BUILD_ASSERT(ARRAY_SIZE(shutdown_causes) ==
-		     CHIPSET_SHUTDOWN_COUNT - CHIPSET_SHUTDOWN_BEGIN);
-
-	if (cause < CHIPSET_RESET_COUNT)
-		return reset_causes[cause];
-
-	if (cause < CHIPSET_SHUTDOWN_BEGIN)
-		return "(reset unknown)";
-
-	if (cause < CHIPSET_SHUTDOWN_COUNT)
-		return shutdown_causes[cause - CHIPSET_SHUTDOWN_BEGIN];
-
-	return "(shutdown unknown)";
-}
-
-int cmd_uptimeinfo(int argc, char *argv[])
-{
-	struct ec_response_uptime_info r;
-	int rv;
-	int i;
-	int flag_count;
-	uint32_t flag;
-	static const char * const reset_flag_descs[] = {
-		#include "reset_flag_desc.inc"
-	};
-
-	if (argc != 1) {
-		fprintf(stderr, "uptimeinfo takes no arguments");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_GET_UPTIME_INFO, 0, NULL, 0, &r, sizeof(r));
-	if (rv < 0) {
-		fprintf(stderr, "ERROR: EC_CMD_GET_UPTIME_INFO failed; %d\n",
-			rv);
-		return rv;
-	}
-
-	printf("EC uptime: %d.%03d seconds\n",
-		r.time_since_ec_boot_ms / 1000,
-		r.time_since_ec_boot_ms % 1000);
-
-	printf("AP resets since EC boot: %d\n", r.ap_resets_since_ec_boot);
-
-	printf("Most recent AP reset causes:\n");
-	for (i = 0; i != ARRAY_SIZE(r.recent_ap_reset); ++i) {
-		if (r.recent_ap_reset[i].reset_time_ms == 0)
-			continue;
-
-		printf("\t%d.%03d: %s\n",
-			r.recent_ap_reset[i].reset_time_ms / 1000,
-			r.recent_ap_reset[i].reset_time_ms % 1000,
-			reset_cause_to_str(r.recent_ap_reset[i].reset_cause));
-	}
-
-	printf("EC reset flags at last EC boot: ");
-
-	if (!r.ec_reset_flags) {
-		printf("unknown\n");
-		return 0;
-	}
-
-	flag_count = 0;
-	for (flag = 0; flag < ARRAY_SIZE(reset_flag_descs); ++flag) {
-		if ((r.ec_reset_flags & BIT(flag)) != 0) {
-			if (flag_count)
-				printf(" | ");
-			printf(reset_flag_descs[flag]);
-			flag_count++;
-		}
-	}
-
-	if (r.ec_reset_flags >= BIT(flag)) {
-		if (flag_count)
-			printf(" | ");
-		printf("no-desc");
-	}
-	printf("\n");
-	return 0;
-}
-
-int cmd_version(int argc, char *argv[])
-{
-	struct ec_response_get_version r;
-	char *build_string = (char *)ec_inbuf;
-	int rv;
-
-	rv = ec_command(EC_CMD_GET_VERSION, 0, NULL, 0, &r, sizeof(r));
-	if (rv < 0) {
-		fprintf(stderr, "ERROR: EC_CMD_GET_VERSION failed: %d\n", rv);
-		goto exit;
-	}
-	rv = ec_command(EC_CMD_GET_BUILD_INFO, 0,
-			NULL, 0, ec_inbuf, ec_max_insize);
-	if (rv < 0) {
-		fprintf(stderr, "ERROR: EC_CMD_GET_BUILD_INFO failed: %d\n",
-				rv);
-		goto exit;
-	}
-	rv = 0;
-
-	/* Ensure versions are null-terminated before we print them */
-	r.version_string_ro[sizeof(r.version_string_ro) - 1] = '\0';
-	r.version_string_rw[sizeof(r.version_string_rw) - 1] = '\0';
-	build_string[ec_max_insize - 1] = '\0';
-
-	/* Print versions */
-	printf("RO version:    %s\n", r.version_string_ro);
-	printf("RW version:    %s\n", r.version_string_rw);
-	printf("Firmware copy: %s\n",
-	       (r.current_image < ARRAY_SIZE(image_names) ?
-		image_names[r.current_image] : "?"));
-	printf("Build info:    %s\n", build_string);
-exit:
-	printf("Tool version:  %s %s %s\n", CROS_ECTOOL_VERSION, DATE, BUILDER);
-
-	return rv;
-}
-
-
-int cmd_read_test(int argc, char *argv[])
-{
-	struct ec_params_read_test p;
-	struct ec_response_read_test r;
-	int offset, size;
-	int errors = 0;
-	int rv;
-	int i;
-	char *e;
-	char *buf;
-	uint32_t *b;
-
-	if (argc < 3) {
-		fprintf(stderr, "Usage: %s <pattern_offset> <size>\n", argv[0]);
-		return -1;
-	}
-	offset = strtol(argv[1], &e, 0);
-	size = strtol(argv[2], &e, 0);
-	if ((e && *e) || size <= 0 || size > MAX_FLASH_SIZE) {
-		fprintf(stderr, "Bad size.\n");
-		return -1;
-	}
-	printf("Reading %d bytes with pattern offset 0x%x...\n", size, offset);
-
-	buf = (char *)malloc(size);
-	if (!buf) {
-		fprintf(stderr, "Unable to allocate buffer.\n");
-		return -1;
-	}
-
-	/* Read data in chunks */
-	for (i = 0; i < size; i += sizeof(r.data)) {
-		p.offset = offset + i / sizeof(uint32_t);
-		p.size = MIN(size - i, sizeof(r.data));
-		rv = ec_command(EC_CMD_READ_TEST, 0, &p, sizeof(p),
-				&r, sizeof(r));
-		if (rv < 0) {
-			fprintf(stderr, "Read error at offset %d\n", i);
-			free(buf);
-			return rv;
-		}
-		memcpy(buf + i, r.data, p.size);
-	}
-
-	/* Check data */
-	for (i = 0, b = (uint32_t *)buf; i < size / 4; i++, b++) {
-		if (*b != i + offset) {
-			printf("Mismatch at byte offset 0x%x: "
-			       "expected 0x%08x, got 0x%08x\n",
-			       (int)(i * sizeof(uint32_t)), i + offset, *b);
-			errors++;
-		}
-	}
-
-	free(buf);
-	if (errors) {
-		printf("Found %d errors\n", errors);
-		return -1;
-	}
-
-	printf("done.\n");
-	return 0;
-}
-
-
-int cmd_reboot_ec(int argc, char *argv[])
-{
-	struct ec_params_reboot_ec p;
-	int rv, i;
-
-	if (argc < 2) {
-		/*
-		 * No params specified so tell the EC to reboot immediately.
-		 * That reboots the AP as well, so unlikely we'll be around
-		 * to see a return code from this...
-		 */
-		rv = ec_command(EC_CMD_REBOOT, 0, NULL, 0, NULL, 0);
-		return (rv < 0 ? rv : 0);
-	}
-
-	/* Parse command */
-	if (!strcmp(argv[1], "cancel"))
-		p.cmd = EC_REBOOT_CANCEL;
-	else if (!strcmp(argv[1], "RO"))
-		p.cmd = EC_REBOOT_JUMP_RO;
-	else if (!strcmp(argv[1], "RW"))
-		p.cmd = EC_REBOOT_JUMP_RW;
-	else if (!strcmp(argv[1], "cold"))
-		p.cmd = EC_REBOOT_COLD;
-	else if (!strcmp(argv[1], "disable-jump"))
-		p.cmd = EC_REBOOT_DISABLE_JUMP;
-	else if (!strcmp(argv[1], "hibernate"))
-		p.cmd = EC_REBOOT_HIBERNATE;
-	else if (!strcmp(argv[1], "hibernate-clear-ap-off"))
-		p.cmd = EC_REBOOT_HIBERNATE_CLEAR_AP_OFF;
-	else {
-		fprintf(stderr, "Unknown command: %s\n", argv[1]);
-		return -1;
-	}
-
-	/* Parse flags, if any */
-	p.flags = 0;
-	for (i = 2; i < argc; i++) {
-		if (!strcmp(argv[i], "at-shutdown")) {
-			p.flags |= EC_REBOOT_FLAG_ON_AP_SHUTDOWN;
-		} else if (!strcmp(argv[i], "switch-slot")) {
-			p.flags |= EC_REBOOT_FLAG_SWITCH_RW_SLOT;
-		} else {
-			fprintf(stderr, "Unknown flag: %s\n", argv[i]);
-			return -1;
-		}
-	}
-
-	rv = ec_command(EC_CMD_REBOOT_EC, 0, &p, sizeof(p), NULL, 0);
-	return (rv < 0 ? rv : 0);
-}
-
-int cmd_reboot_ap_on_g3(int argc, char *argv[])
-{
-	int rv;
-
-	rv = ec_command(EC_CMD_REBOOT_AP_ON_G3, 0, NULL, 0, NULL, 0);
-	return (rv < 0 ? rv : 0);
-}
-
-int cmd_button(int argc, char *argv[])
-{
-	struct ec_params_button p;
-	char *e;
-	int argv_idx;
-	int button = KEYBOARD_BUTTON_COUNT;
-	int rv;
-
-	if (argc < 2) {
-		fprintf(stderr, "Invalid num param %d.\n", argc);
-		return -1;
-	}
-
-	p.press_ms = 50;
-	p.btn_mask = 0;
-
-	for (argv_idx = 1; argv_idx < argc; argv_idx++) {
-		if (!strcasecmp(argv[argv_idx], "vup"))
-			button = KEYBOARD_BUTTON_VOLUME_UP;
-		else if (!strcasecmp(argv[argv_idx], "vdown"))
-			button = KEYBOARD_BUTTON_VOLUME_DOWN;
-		else if (!strcasecmp(argv[argv_idx], "rec"))
-			button = KEYBOARD_BUTTON_RECOVERY;
-		else {
-			/* If last parameter check if it is an integer. */
-			if (argv_idx == argc - 1) {
-				p.press_ms = strtol(argv[argv_idx], &e, 0);
-				/* If integer, break out of the loop. */
-				if (!*e)
-					break;
-			}
-			button = KEYBOARD_BUTTON_COUNT;
-		}
-
-		if (button == KEYBOARD_BUTTON_COUNT) {
-			fprintf(stderr, "Invalid button input.\n");
-			return -1;
-		}
-
-		p.btn_mask |= (1 << button);
-	}
-	if (!p.btn_mask)
-		return 0;
-
-	rv = ec_command(EC_CMD_BUTTON, 0, &p, sizeof(p), NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	printf("Button(s) %d set to %d ms\n", p.btn_mask, p.press_ms);
-	return 0;
-}
-
-int cmd_flash_info(int argc, char *argv[])
-{
-	struct ec_response_flash_info_1 r;
-	int cmdver = 1;
-	int rsize = sizeof(r);
-	int rv;
-
-	memset(&r, 0, sizeof(r));
-
-	if (!ec_cmd_version_supported(EC_CMD_FLASH_INFO, cmdver)) {
-		/* Fall back to version 0 command */
-		cmdver = 0;
-		rsize = sizeof(struct ec_response_flash_info);
-	}
-
-	rv = ec_command(EC_CMD_FLASH_INFO, cmdver, NULL, 0, &r, rsize);
-	if (rv < 0)
-		return rv;
-
-	printf("FlashSize %d\nWriteSize %d\nEraseSize %d\nProtectSize %d\n",
-	       r.flash_size, r.write_block_size, r.erase_block_size,
-	       r.protect_block_size);
-
-	if (cmdver >= 1) {
-		/* Fields added in ver.1 available */
-		printf("WriteIdealSize %d\nFlags 0x%x\n",
-		       r.write_ideal_size, r.flags);
-	}
-
-	return 0;
-}
-
-int cmd_rand(int argc, char *argv[])
-{
-	struct ec_params_rand_num p;
-	struct ec_response_rand_num *r;
-	size_t r_size;
-	int64_t num_bytes;
-	int64_t i;
-	char *e;
-	int rv = 0;
-
-	if (argc < 2) {
-		fprintf(stderr, "Usage: %s <num_bytes>\n", argv[0]);
-		return -1;
-	}
-
-	num_bytes = strtol(argv[1], &e, 0);
-	if ((e && *e) || (errno == ERANGE)) {
-		fprintf(stderr, "Invalid num_bytes argument\n");
-		return -1;
-	}
-
-	r = ec_inbuf;
-
-	for (i = 0; i < num_bytes; i += ec_max_insize) {
-		p.num_rand_bytes = ec_max_insize;
-		if (num_bytes - i < p.num_rand_bytes)
-			p.num_rand_bytes = num_bytes - i;
-
-		r_size = p.num_rand_bytes;
-
-		rv = ec_command(EC_CMD_RAND_NUM, EC_VER_RAND_NUM, &p, sizeof(p),
-				r, r_size);
-		if (rv < 0) {
-			fprintf(stderr, "Random number command failed\n");
-			return -1;
-		}
-
-		rv = write(STDOUT_FILENO, r->rand, r_size);
-		if (rv != r_size) {
-			fprintf(stderr, "Failed to write stdout\n");
-			return -1;
-		}
-	}
-
-	return 0;
-}
-
-int cmd_flash_spi_info(int argc, char *argv[])
-{
-	struct ec_response_flash_spi_info r;
-	int rv;
-
-	memset(&r, 0, sizeof(r));
-
-	/* Print SPI flash info if available */
-	if (!ec_cmd_version_supported(EC_CMD_FLASH_SPI_INFO, 0)) {
-		printf("EC has no info (does not use SPI flash?)\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_FLASH_SPI_INFO, 0, NULL, 0, &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	printf("JEDECManufacturerID 0x%02x\n", r.jedec[0]);
-	printf("JEDECDeviceID 0x%02x 0x%02x\n", r.jedec[1], r.jedec[2]);
-	printf("JEDECCapacity %d\n", 1 << r.jedec[2]);
-	printf("ManufacturerID 0x%02x\n", r.mfr_dev_id[0]);
-	printf("DeviceID 0x%02x\n", r.mfr_dev_id[1]);
-	printf("StatusRegister1 0x%02x\n", r.sr1);
-	printf("StatusRegister2 0x%02x\n", r.sr2);
-	return 0;
-}
-
-int cmd_flash_read(int argc, char *argv[])
-{
-	int offset, size;
-	int rv;
-	char *e;
-	char *buf;
-
-	if (argc < 4) {
-		fprintf(stderr,
-			"Usage: %s <offset> <size> <filename>\n", argv[0]);
-		return -1;
-	}
-	offset = strtol(argv[1], &e, 0);
-	if ((e && *e) || offset < 0 || offset > MAX_FLASH_SIZE) {
-		fprintf(stderr, "Bad offset.\n");
-		return -1;
-	}
-	size = strtol(argv[2], &e, 0);
-	if ((e && *e) || size <= 0 || size > MAX_FLASH_SIZE) {
-		fprintf(stderr, "Bad size.\n");
-		return -1;
-	}
-	printf("Reading %d bytes at offset %d...\n", size, offset);
-
-	buf = (char *)malloc(size);
-	if (!buf) {
-		fprintf(stderr, "Unable to allocate buffer.\n");
-		return -1;
-	}
-
-	/* Read data in chunks */
-	rv = ec_flash_read(buf, offset, size);
-	if (rv < 0) {
-		free(buf);
-		return rv;
-	}
-
-	rv = write_file(argv[3], buf, size);
-	free(buf);
-	if (rv)
-		return rv;
-
-	printf("done.\n");
-	return 0;
-}
-
-int cmd_flash_write(int argc, char *argv[])
-{
-	int offset, size;
-	int rv;
-	char *e;
-	char *buf;
-
-	if (argc < 3) {
-		fprintf(stderr, "Usage: %s <offset> <filename>\n", argv[0]);
-		return -1;
-	}
-
-	offset = strtol(argv[1], &e, 0);
-	if ((e && *e) || offset < 0 || offset > MAX_FLASH_SIZE) {
-		fprintf(stderr, "Bad offset.\n");
-		return -1;
-	}
-
-	/* Read the input file */
-	buf = read_file(argv[2], &size);
-	if (!buf)
-		return -1;
-
-	printf("Writing to offset %d...\n", offset);
-
-	/* Write data in chunks */
-	rv = ec_flash_write(buf, offset, size);
-
-	free(buf);
-
-	if (rv < 0)
-		return rv;
-
-	printf("done.\n");
-	return 0;
-}
-
-int cmd_flash_erase(int argc, char *argv[])
-{
-	int offset, size;
-	char *e;
-	int rv;
-	bool async = false;
-
-	if (argc < 3) {
-		fprintf(stderr, "Usage: %s <offset> <size>\n", argv[0]);
-		return -1;
-	}
-
-	if (strcmp(argv[0], "flasheraseasync") == 0)
-		async = true;
-
-	offset = strtol(argv[1], &e, 0);
-	if ((e && *e) || offset < 0 || offset > MAX_FLASH_SIZE) {
-		fprintf(stderr, "Bad offset.\n");
-		return -1;
-	}
-
-	size = strtol(argv[2], &e, 0);
-	if ((e && *e) || size <= 0 || size > MAX_FLASH_SIZE) {
-		fprintf(stderr, "Bad size.\n");
-		return -1;
-	}
-
-	printf("Erasing %d bytes at offset %d...\n", size, offset);
-	if (async)
-		rv = ec_flash_erase_async(offset, size);
-	else
-		rv = ec_flash_erase(offset, size);
-	if (rv < 0)
-		return rv;
-
-	printf("done.\n");
-	return 0;
-}
-
-
-static void print_flash_protect_flags(const char *desc, uint32_t flags)
-{
-	printf("%s 0x%08x", desc, flags);
-	if (flags & EC_FLASH_PROTECT_GPIO_ASSERTED)
-		printf(" wp_gpio_asserted");
-	if (flags & EC_FLASH_PROTECT_RO_AT_BOOT)
-		printf(" ro_at_boot");
-	if (flags & EC_FLASH_PROTECT_RW_AT_BOOT)
-		printf(" rw_at_boot");
-	if (flags & EC_FLASH_PROTECT_ROLLBACK_AT_BOOT)
-		printf(" rollback_at_boot");
-	if (flags & EC_FLASH_PROTECT_ALL_AT_BOOT)
-		printf(" all_at_boot");
-	if (flags & EC_FLASH_PROTECT_RO_NOW)
-		printf(" ro_now");
-	if (flags & EC_FLASH_PROTECT_RW_NOW)
-		printf(" rw_now");
-	if (flags & EC_FLASH_PROTECT_ROLLBACK_NOW)
-		printf(" rollback_now");
-	if (flags & EC_FLASH_PROTECT_ALL_NOW)
-		printf(" all_now");
-	if (flags & EC_FLASH_PROTECT_ERROR_STUCK)
-		printf(" STUCK");
-	if (flags & EC_FLASH_PROTECT_ERROR_INCONSISTENT)
-		printf(" INCONSISTENT");
-	printf("\n");
-}
-
-
-int cmd_flash_protect(int argc, char *argv[])
-{
-	struct ec_params_flash_protect p;
-	struct ec_response_flash_protect r;
-	int rv, i;
-
-	/*
-	 * Set up requested flags.  If no flags were specified, p.mask will
-	 * be 0 and nothing will change.
-	 */
-	p.mask = p.flags = 0;
-	for (i = 1; i < argc; i++) {
-		if (!strcasecmp(argv[i], "now")) {
-			p.mask |= EC_FLASH_PROTECT_ALL_NOW;
-			p.flags |= EC_FLASH_PROTECT_ALL_NOW;
-		} else if (!strcasecmp(argv[i], "enable")) {
-			p.mask |= EC_FLASH_PROTECT_RO_AT_BOOT;
-			p.flags |= EC_FLASH_PROTECT_RO_AT_BOOT;
-		} else if (!strcasecmp(argv[i], "disable"))
-			p.mask |= EC_FLASH_PROTECT_RO_AT_BOOT;
-	}
-
-	rv = ec_command(EC_CMD_FLASH_PROTECT, EC_VER_FLASH_PROTECT,
-			&p, sizeof(p), &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-	if (rv < sizeof(r)) {
-		fprintf(stderr, "Too little data returned.\n");
-		return -1;
-	}
-
-	/* Print returned flags */
-	print_flash_protect_flags("Flash protect flags:", r.flags);
-	print_flash_protect_flags("Valid flags:        ", r.valid_flags);
-	print_flash_protect_flags("Writable flags:     ", r.writable_flags);
-
-	/* Check if we got all the flags we asked for */
-	if ((r.flags & p.mask) != (p.flags & p.mask)) {
-		fprintf(stderr, "Unable to set requested flags "
-			"(wanted mask 0x%08x flags 0x%08x)\n",
-			p.mask, p.flags);
-		if (p.mask & ~r.writable_flags)
-			fprintf(stderr, "Which is expected, because writable "
-				"mask is 0x%08x.\n", r.writable_flags);
-
-		return -1;
-	}
-
-	return 0;
-}
-
-int cmd_rw_hash_pd(int argc, char *argv[])
-{
-	struct ec_params_usb_pd_rw_hash_entry *p =
-		(struct ec_params_usb_pd_rw_hash_entry *)ec_outbuf;
-	int i, rv;
-	char *e;
-	uint32_t val;
-	uint8_t *rwp;
-
-	if (argc < 7) {
-		fprintf(stderr, "Usage: %s <dev_id> <HASH[0]> ... <HASH[4]>\n",
-			argv[0]);
-		return -1;
-	}
-
-	p->dev_id = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad device ID\n");
-		return -1;
-	}
-
-	rwp = p->dev_rw_hash;
-	for (i = 2; i < 7; i++) {
-		val = strtol(argv[i], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad RW hash\n");
-			return -1;
-		}
-		rwp[0] = (uint8_t)  (val >> 0) & 0xff;
-		rwp[1] = (uint8_t)  (val >> 8) & 0xff;
-		rwp[2] = (uint8_t) (val >> 16) & 0xff;
-		rwp[3] = (uint8_t) (val >> 24) & 0xff;
-		rwp += 4;
-	}
-	rv = ec_command(EC_CMD_USB_PD_RW_HASH_ENTRY, 0, p, sizeof(*p), NULL, 0);
-
-	return rv;
-}
-
-int cmd_rwsig_status(int argc, char *argv[])
-{
-	int rv;
-	struct ec_response_rwsig_check_status resp;
-
-	rv = ec_command(EC_CMD_RWSIG_CHECK_STATUS, 0, NULL, 0,
-			&resp, sizeof(resp));
-	if (rv < 0)
-		return rv;
-
-	printf("RW signature check: %s\n", resp.status ? "OK" : "FAILED");
-
-	return 0;
-}
-
-static int rwsig_action(const char *command)
-{
-	struct ec_params_rwsig_action req;
-
-	if (!strcasecmp(command, "abort"))
-		req.action = RWSIG_ACTION_ABORT;
-	else if (!strcasecmp(command, "continue"))
-		req.action = RWSIG_ACTION_CONTINUE;
-	else
-		return -1;
-
-	return ec_command(EC_CMD_RWSIG_ACTION, 0, &req, sizeof(req), NULL, 0);
-}
-
-int cmd_rwsig_action_legacy(int argc, char *argv[])
-{
-	if (argc < 2) {
-		fprintf(stderr, "Usage: %s [abort | continue]\n", argv[0]);
-		return -1;
-	}
-
-	return rwsig_action(argv[1]);
-}
-
-int cmd_rwsig_action(int argc, char *argv[])
-{
-	if (argc < 2) {
-		fprintf(stderr, "Usage: ectool rwsig action [abort | "
-				"continue]\n");
-		return -1;
-	}
-
-	return rwsig_action(argv[1]);
-}
-
-enum rwsig_info_fields {
-	RWSIG_INFO_FIELD_SIG_ALG = BIT(0),
-	RWSIG_INFO_FIELD_KEY_VERSION = BIT(1),
-	RWSIG_INFO_FIELD_HASH_ALG = BIT(2),
-	RWSIG_INFO_FIELD_KEY_IS_VALID = BIT(3),
-	RWSIG_INFO_FIELD_KEY_ID = BIT(4),
-	RWSIG_INFO_FIELD_ALL = RWSIG_INFO_FIELD_SIG_ALG |
-		RWSIG_INFO_FIELD_KEY_VERSION | RWSIG_INFO_FIELD_HASH_ALG |
-		RWSIG_INFO_FIELD_KEY_IS_VALID | RWSIG_INFO_FIELD_KEY_ID
-};
-
-static int rwsig_info(enum rwsig_info_fields fields)
-{
-	int i;
-	int rv;
-	struct ec_response_rwsig_info r;
-	bool print_prefix = false;
-
-	rv = ec_command(EC_CMD_RWSIG_INFO, EC_VER_RWSIG_INFO, NULL, 0, &r,
-			sizeof(r));
-	if (rv < 0) {
-		fprintf(stderr, "rwsig info command failed\n");
-		return -1;
-	}
-
-	if ((fields & RWSIG_INFO_FIELD_ALL) == RWSIG_INFO_FIELD_ALL)
-		print_prefix = true;
-
-	if (fields & RWSIG_INFO_FIELD_SIG_ALG) {
-		if (print_prefix)
-			printf("sig_alg: ");
-
-		printf("%d\n", r.sig_alg);
-	}
-	if (fields & RWSIG_INFO_FIELD_KEY_VERSION) {
-		if (print_prefix)
-			printf("key_version: ");
-
-		printf("%d\n", r.key_version);
-	}
-	if (fields & RWSIG_INFO_FIELD_HASH_ALG) {
-		if (print_prefix)
-			printf("hash_alg: ");
-
-		printf("%d\n", r.hash_alg);
-	}
-	if (fields & RWSIG_INFO_FIELD_KEY_IS_VALID) {
-		if (print_prefix)
-			printf("key_is_valid: ");
-
-		printf("%d\n", r.key_is_valid);
-	}
-	if (fields & RWSIG_INFO_FIELD_KEY_ID) {
-		if (print_prefix)
-			printf("key_id: ");
-
-		for (i = 0; i < sizeof(r.key_id); i++)
-			printf("%02x", r.key_id[i]);
-		printf("\n");
-	}
-
-	return 0;
-}
-
-static int cmd_rwsig_info(int argc, char *argv[])
-{
-	int i;
-
-	struct rwsig_dump_cmds {
-		const char *cmd;
-		enum rwsig_info_fields field;
-	};
-
-	struct rwsig_dump_cmds cmd_map[] = {
-		{ "sig_alg", RWSIG_INFO_FIELD_SIG_ALG },
-		{ "key_version", RWSIG_INFO_FIELD_KEY_VERSION },
-		{ "hash_alg", RWSIG_INFO_FIELD_HASH_ALG },
-		{ "key_valid", RWSIG_INFO_FIELD_KEY_IS_VALID },
-		{ "key_id", RWSIG_INFO_FIELD_KEY_ID },
-	};
-
-	if (argc == 0)
-		return -1;
-
-	if (strcmp(argv[0], "info") == 0)
-		return rwsig_info(RWSIG_INFO_FIELD_ALL);
-
-	if (strcmp(argv[0], "dump") == 0) {
-		if (argc != 2) {
-			fprintf(stderr,
-				"Usage: rwsig dump "
-				"[sig_alg|key_version|hash_alg|key_valid|key_id]\n");
-			return -1;
-		}
-		for (i = 0; i < ARRAY_SIZE(cmd_map); i++)
-			if (strcmp(argv[1], cmd_map[i].cmd) == 0)
-				return rwsig_info(cmd_map[i].field);
-
-		return -1;
-	}
-
-	return -1;
-}
-
-int cmd_rwsig(int argc, char **argv)
-{
-	struct rwsig_subcommand {
-		const char *subcommand;
-		int (*handler)(int argc, char *argv[]);
-	};
-
-	const struct rwsig_subcommand rwsig_subcommands[] = {
-		{ "info", cmd_rwsig_info },
-		{ "dump", cmd_rwsig_info },
-		{ "action", cmd_rwsig_action },
-		{ "status", cmd_rwsig_status }
-	};
-
-	int i;
-
-	if (argc < 2) {
-		fprintf(stderr, "Usage: %s <info|dump|action|status>\n",
-			argv[0]);
-		return -1;
-	}
-
-	for (i = 0; i < ARRAY_SIZE(rwsig_subcommands); i++)
-		if (strcmp(argv[1], rwsig_subcommands[i].subcommand) == 0)
-			return rwsig_subcommands[i].handler(--argc, &argv[1]);
-
-	return -1;
-}
-
-enum sysinfo_fields {
-	SYSINFO_FIELD_RESET_FLAGS = BIT(0),
-	SYSINFO_FIELD_CURRENT_IMAGE = BIT(1),
-	SYSINFO_FIELD_FLAGS = BIT(2),
-	SYSINFO_INFO_FIELD_ALL = SYSINFO_FIELD_RESET_FLAGS |
-				 SYSINFO_FIELD_CURRENT_IMAGE |
-				 SYSINFO_FIELD_FLAGS
-};
-
-static int sysinfo(struct ec_response_sysinfo *info)
-{
-	struct ec_response_sysinfo r;
-	int rv;
-
-	rv = ec_command(EC_CMD_SYSINFO, 0, NULL, 0, &r, sizeof(r));
-	if (rv < 0) {
-		fprintf(stderr, "ERROR: EC_CMD_SYSINFO failed: %d\n", rv);
-		return rv;
-	}
-
-	return 0;
-}
-
-int cmd_sysinfo(int argc, char **argv)
-{
-	struct ec_response_sysinfo r;
-	enum sysinfo_fields fields = 0;
-	bool print_prefix = false;
-
-	if (argc != 1 && argc != 2)
-		goto sysinfo_error_usage;
-
-	if (argc == 1) {
-		fields = SYSINFO_INFO_FIELD_ALL;
-		print_prefix = true;
-	} else if (argc == 2) {
-		if (strcmp(argv[1], "flags") == 0)
-			fields = SYSINFO_FIELD_FLAGS;
-		else if (strcmp(argv[1], "reset_flags") == 0)
-			fields = SYSINFO_FIELD_RESET_FLAGS;
-		else if (strcmp(argv[1], "firmware_copy") == 0)
-			fields = SYSINFO_FIELD_CURRENT_IMAGE;
-		else
-			goto sysinfo_error_usage;
-	}
-
-	if (sysinfo(&r) != 0)
-		return -1;
-
-	if (fields & SYSINFO_FIELD_RESET_FLAGS) {
-		if (print_prefix)
-			printf("Reset flags: ");
-		printf("0x%08x\n", r.reset_flags);
-	}
-
-	if (fields & SYSINFO_FIELD_FLAGS) {
-		if (print_prefix)
-			printf("Flags: ");
-		printf("0x%08x\n", r.flags);
-
-	}
-
-	if (fields & SYSINFO_FIELD_CURRENT_IMAGE) {
-		if (print_prefix)
-			printf("Firmware copy: ");
-		printf("%d\n", r.current_image);
-	}
-
-	return 0;
-
-sysinfo_error_usage:
-	fprintf(stderr, "Usage: %s "
-			"[flags|reset_flags|firmware_copy]\n",
-		argv[0]);
-	return -1;
-}
-
-int cmd_rollback_info(int argc, char *argv[])
-{
-	struct ec_response_rollback_info r;
-	int rv;
-
-	rv = ec_command(EC_CMD_ROLLBACK_INFO, 0, NULL, 0, &r, sizeof(r));
-	if (rv < 0) {
-		fprintf(stderr, "ERROR: EC_CMD_ROLLBACK_INFO failed: %d\n", rv);
-		return rv;
-	}
-
-	/* Print versions */
-	printf("Rollback block id:    %d\n", r.id);
-	printf("Rollback min version: %d\n", r.rollback_min_version);
-	printf("RW rollback version:  %d\n", r.rw_rollback_version);
-
-	return 0;
-}
-
-int cmd_apreset(int argc, char *argv[])
-{
-	return ec_command(EC_CMD_AP_RESET, 0, NULL, 0, NULL, 0);
-}
-
-#define FP_FRAME_INDEX_SIMPLE_IMAGE -1
-
-/*
- * Download a frame buffer from the FPMCU.
- *
- * Might be either the finger image or a finger template depending on 'index'.
- *
- * @param info a pointer to store the struct ec_response_fp_info retrieved by
- * this command.
- * @param index the specific frame to retrieve, might be:
- *  -1 (aka FP_FRAME_INDEX_SIMPLE_IMAGE) for the a single grayscale image.
- *   0  (aka FP_FRAME_INDEX_RAW_IMAGE) for the full vendor raw finger image.
- *   1..n for a finger template.
- *
- * @returns a pointer to the buffer allocated to contain the frame or NULL
- * if case of error. The caller must call free() once it no longer needs the
- * buffer.
- */
-static void *fp_download_frame(struct ec_response_fp_info *info, int index)
-{
-	struct ec_params_fp_frame p;
-	int rv = 0;
-	size_t stride, size;
-	void *buffer;
-	uint8_t *ptr;
-	int cmdver = ec_cmd_version_supported(EC_CMD_FP_INFO, 1) ? 1 : 0;
-	int rsize = cmdver == 1 ? sizeof(*info)
-				: sizeof(struct ec_response_fp_info_v0);
-
-	/* templates not supported in command v0 */
-	if (index > 0 && cmdver == 0)
-		return NULL;
-
-	rv = ec_command(EC_CMD_FP_INFO, cmdver, NULL, 0, info, rsize);
-	if (rv < 0)
-		return NULL;
-
-	if (index == FP_FRAME_INDEX_SIMPLE_IMAGE) {
-		size = (size_t)info->width * info->bpp/8 * info->height;
-		index = FP_FRAME_INDEX_RAW_IMAGE;
-	} else if (index == FP_FRAME_INDEX_RAW_IMAGE) {
-		size = info->frame_size;
-	} else {
-		size = info->template_size;
-	}
-
-	buffer = malloc(size);
-	if (!buffer) {
-		fprintf(stderr, "Cannot allocate memory for the image\n");
-		return NULL;
-	}
-
-	ptr = buffer;
-	p.offset = index << FP_FRAME_INDEX_SHIFT;
-	while (size) {
-		stride = MIN(ec_max_insize, size);
-		p.size = stride;
-		rv = ec_command(EC_CMD_FP_FRAME, 0, &p, sizeof(p),
-				ptr, stride);
-		if (rv < 0) {
-			free(buffer);
-			return NULL;
-		}
-		p.offset += stride;
-		size -= stride;
-		ptr += stride;
-	}
-
-	return buffer;
-}
-
-int cmd_fp_mode(int argc, char *argv[])
-{
-	struct ec_params_fp_mode p;
-	struct ec_response_fp_mode r;
-	uint32_t mode = 0;
-	uint32_t capture_type = FP_CAPTURE_SIMPLE_IMAGE;
-	int i, rv;
-
-	if (argc == 1)
-		mode = FP_MODE_DONT_CHANGE;
-	for (i = 1; i < argc; i++) {
-		/* modes */
-		if (!strncmp(argv[i], "deepsleep", 9))
-			mode |= FP_MODE_DEEPSLEEP;
-		else if (!strncmp(argv[i], "fingerdown", 10))
-			mode |= FP_MODE_FINGER_DOWN;
-		else if (!strncmp(argv[i], "fingerup", 8))
-			mode |= FP_MODE_FINGER_UP;
-		else if (!strncmp(argv[i], "enroll", 6))
-			mode |= FP_MODE_ENROLL_IMAGE | FP_MODE_ENROLL_SESSION;
-		else if (!strncmp(argv[i], "match", 5))
-			mode |= FP_MODE_MATCH;
-		else if (!strncmp(argv[i], "reset_sensor", 12))
-			mode = FP_MODE_RESET_SENSOR;
-		else if (!strncmp(argv[i], "reset", 5))
-			mode = 0;
-		else if (!strncmp(argv[i], "capture", 7))
-			mode |= FP_MODE_CAPTURE;
-		/* capture types */
-		else if (!strncmp(argv[i], "vendor", 6))
-			capture_type = FP_CAPTURE_VENDOR_FORMAT;
-		else if (!strncmp(argv[i], "pattern0", 8))
-			capture_type = FP_CAPTURE_PATTERN0;
-		else if (!strncmp(argv[i], "pattern1", 8))
-			capture_type = FP_CAPTURE_PATTERN1;
-		else if (!strncmp(argv[i], "qual", 4))
-			capture_type = FP_CAPTURE_QUALITY_TEST;
-		else if (!strncmp(argv[i], "test_reset", 10))
-			capture_type = FP_CAPTURE_RESET_TEST;
-	}
-	if (mode & FP_MODE_CAPTURE)
-		mode |= capture_type << FP_MODE_CAPTURE_TYPE_SHIFT;
-
-	p.mode = mode;
-	rv = ec_command(EC_CMD_FP_MODE, 0, &p, sizeof(p), &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	printf("FP mode: (0x%x) ", r.mode);
-	if (r.mode & FP_MODE_DEEPSLEEP)
-		printf("deepsleep ");
-	if (r.mode & FP_MODE_FINGER_DOWN)
-		printf("finger-down ");
-	if (r.mode & FP_MODE_FINGER_UP)
-		printf("finger-up ");
-	if (r.mode & FP_MODE_ENROLL_SESSION)
-		printf("enroll%s ",
-			r.mode & FP_MODE_ENROLL_IMAGE ? "+image" : "");
-	if (r.mode & FP_MODE_MATCH)
-		printf("match ");
-	if (r.mode & FP_MODE_CAPTURE)
-		printf("capture ");
-	printf("\n");
-	return 0;
-}
-
-int cmd_fp_seed(int argc, char *argv[])
-{
-	struct ec_params_fp_seed p;
-	char *seed;
-
-	if (argc != 2) {
-		fprintf(stderr, "Usage: %s <seed>\n", argv[0]);
-		return 1;
-	}
-	seed = argv[1];
-	if (strlen(seed) != FP_CONTEXT_TPM_BYTES) {
-		printf("Invalid seed '%s' is %zd bytes long instead of %d.\n",
-		       seed, strlen(seed), FP_CONTEXT_TPM_BYTES);
-		return 1;
-	}
-	printf("Setting seed '%s'\n", seed);
-	p.struct_version = FP_TEMPLATE_FORMAT_VERSION;
-	memcpy(p.seed, seed, FP_CONTEXT_TPM_BYTES);
-
-	return ec_command(EC_CMD_FP_SEED, 0, &p, sizeof(p), NULL, 0);
-}
-
-int cmd_fp_stats(int argc, char *argv[])
-{
-	struct ec_response_fp_stats r;
-	int rv;
-	unsigned long long ts;
-
-	rv = ec_command(EC_CMD_FP_STATS, 0, NULL, 0, &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	ts = (uint64_t)r.overall_t0.hi << 32 | r.overall_t0.lo;
-	printf("FP stats (t0=%llu us):\n", ts);
-	printf("Last capture time:  ");
-	if (r.timestamps_invalid & FPSTATS_CAPTURE_INV)
-		printf("Invalid\n");
-	else
-		printf("%d us\n", r.capture_time_us);
-
-	printf("Last matching time: ");
-	if (r.timestamps_invalid & FPSTATS_MATCHING_INV)
-		printf("Invalid\n");
-	else
-		printf("%d us (finger: %d)\n", r.matching_time_us,
-			r.template_matched);
-
-	printf("Last overall time:  ");
-	if (r.timestamps_invalid)
-		printf("Invalid\n");
-	else
-		printf("%d us\n", r.overall_time_us);
-
-	return 0;
-}
-
-int cmd_fp_info(int argc, char *argv[])
-{
-	struct ec_response_fp_info r;
-	int rv;
-	int cmdver = ec_cmd_version_supported(EC_CMD_FP_INFO, 1) ? 1 : 0;
-	int rsize = cmdver == 1 ? sizeof(r)
-				: sizeof(struct ec_response_fp_info_v0);
-	uint16_t dead;
-
-	rv = ec_command(EC_CMD_FP_INFO, cmdver, NULL, 0, &r, rsize);
-	if (rv < 0)
-		return rv;
-
-	printf("Fingerprint sensor: vendor %x product %x model %x version %x\n",
-		r.vendor_id, r.product_id, r.model_id, r.version);
-	printf("Image: size %dx%d %d bpp\n", r.width, r.height, r.bpp);
-	printf("Error flags: %s%s%s%s\n",
-	       r.errors & FP_ERROR_NO_IRQ ? "NO_IRQ " : "",
-	       r.errors & FP_ERROR_SPI_COMM ? "SPI_COMM " : "",
-	       r.errors & FP_ERROR_BAD_HWID ? "BAD_HWID " : "",
-	       r.errors & FP_ERROR_INIT_FAIL ? "INIT_FAIL " : "");
-	dead = FP_ERROR_DEAD_PIXELS(r.errors);
-	if (dead == FP_ERROR_DEAD_PIXELS_UNKNOWN) {
-		printf("Dead pixels: UNKNOWN\n");
-	} else {
-		printf("Dead pixels: %u\n", dead);
-	}
-
-	if (cmdver == 1) {
-		printf("Templates: version %d size %d count %d/%d"
-		       " dirty bitmap %x\n",
-		       r.template_version, r.template_size, r.template_valid,
-		       r.template_max, r.template_dirty);
-	}
-
-	return 0;
-}
-
-static void print_fp_enc_flags(const char *desc, uint32_t flags)
-{
-	printf("%s 0x%08x", desc, flags);
-	if (flags & FP_ENC_STATUS_SEED_SET)
-		printf(" FPTPM_seed_set");
-	printf("\n");
-}
-
-static int cmd_fp_context(int argc, char *argv[])
-{
-	struct ec_params_fp_context_v1 p;
-	int rv;
-	int tries = 20; /* Wait at most two seconds */
-
-	if (argc < 2) {
-		fprintf(stderr, "Usage: %s <context>\n", argv[0]);
-		return -1;
-	}
-
-	/*
-	 * Note that we treat the resulting "userid" as raw byte array, so we
-	 * don't want to copy the NUL from the end of the string.
-	 */
-	if (strlen(argv[1]) != sizeof(p.userid)) {
-		fprintf(stderr, "Context must be exactly %zu bytes\n",
-			sizeof(p.userid));
-		return -1;
-	}
-
-	p.action = FP_CONTEXT_ASYNC;
-	memcpy(p.userid, argv[1], sizeof(p.userid));
-
-	rv = ec_command(EC_CMD_FP_CONTEXT, 1, &p, sizeof(p), NULL, 0);
-
-	if (rv != EC_RES_SUCCESS)
-		goto out;
-
-	while (tries--) {
-		usleep(100000);
-
-		p.action = FP_CONTEXT_GET_RESULT;
-		rv = ec_command(EC_CMD_FP_CONTEXT, 1, &p, sizeof(p), NULL, 0);
-
-		if (rv == EC_RES_SUCCESS) {
-			printf("Set context successfully\n");
-			return EC_RES_SUCCESS;
-		}
-
-		/* Abort if EC returns an error other than EC_RES_BUSY. */
-		if (rv <= -EECRESULT && rv != -EECRESULT - EC_RES_BUSY)
-			goto out;
-	}
-
-	rv = -EECRESULT - EC_RES_TIMEOUT;
-
-out:
-	fprintf(stderr, "Failed to reset context: %d\n", rv);
-	return rv;
-}
-
-int cmd_fp_enc_status(int argc, char *argv[])
-{
-	int rv;
-	struct ec_response_fp_encryption_status resp = { 0 };
-
-	rv = ec_command(EC_CMD_FP_ENC_STATUS, 0, NULL, 0, &resp, sizeof(resp));
-	if (rv < 0) {
-		printf("Get FP sensor encryption status failed.\n");
-	} else {
-		print_fp_enc_flags("FPMCU encryption status:", resp.status);
-		print_fp_enc_flags("Valid flags:            ",
-				   resp.valid_flags);
-		rv = 0;
-	}
-	return rv;
-}
-
-int cmd_fp_frame(int argc, char *argv[])
-{
-	struct ec_response_fp_info r;
-	int idx = (argc == 2 && !strcasecmp(argv[1], "raw")) ?
-		FP_FRAME_INDEX_RAW_IMAGE : FP_FRAME_INDEX_SIMPLE_IMAGE;
-	void *buffer = fp_download_frame(&r, idx);
-	uint8_t *ptr = buffer;
-	int x, y;
-
-	if (!buffer) {
-		fprintf(stderr, "Failed to get FP sensor frame\n");
-		return -1;
-	}
-
-	if (idx == FP_FRAME_INDEX_RAW_IMAGE) {
-		fwrite(buffer, r.frame_size, 1, stdout);
-		goto frame_done;
-	}
-
-	/* Print 8-bpp PGM ASCII header */
-	printf("P2\n%d %d\n%d\n", r.width, r.height, (1 << r.bpp) - 1);
-
-	for (y = 0; y < r.height; y++) {
-		for (x = 0; x < r.width; x++, ptr++)
-			printf("%d ", *ptr);
-		printf("\n");
-	}
-	printf("# END OF FILE\n");
-frame_done:
-	free(buffer);
-	return 0;
-}
-
-int cmd_fp_template(int argc, char *argv[])
-{
-	struct ec_response_fp_info r;
-	struct ec_params_fp_template *p = ec_outbuf;
-	/* TODO(b/78544921): removing 32 bits is a workaround for the MCU bug */
-	int max_chunk = ec_max_outsize
-			- offsetof(struct ec_params_fp_template, data) - 4;
-	int idx = -1;
-	char *e;
-	int size;
-	void *buffer = NULL;
-	uint32_t offset = 0;
-	int rv = 0;
-
-	if (argc < 2) {
-		fprintf(stderr, "Usage: %s [<infile>|<index>]\n", argv[0]);
-		return -1;
-	}
-
-	idx = strtol(argv[1], &e, 0);
-	if (!(e && *e)) {
-		buffer = fp_download_frame(&r, idx + 1);
-		if (!buffer) {
-			fprintf(stderr, "Failed to get FP template %d\n", idx);
-			return -1;
-		}
-		fwrite(buffer, r.template_size, 1, stdout);
-		free(buffer);
-		return 0;
-	}
-	/* not an index, is it a filename ? */
-	buffer = read_file(argv[1], &size);
-	if (!buffer) {
-		fprintf(stderr, "Invalid parameter: %s\n", argv[1]);
-		return -1;
-	}
-	printf("sending template from: %s (%d bytes)\n", argv[1], size);
-	while (size) {
-		uint32_t tlen = MIN(max_chunk, size);
-
-		p->offset = offset;
-		p->size = tlen;
-		size -= tlen;
-		if (!size)
-			p->size |= FP_TEMPLATE_COMMIT;
-		memcpy(p->data, buffer + offset, tlen);
-		rv = ec_command(EC_CMD_FP_TEMPLATE, 0, p, tlen +
-				offsetof(struct ec_params_fp_template, data),
-				NULL, 0);
-		if (rv < 0)
-			break;
-		offset += tlen;
-	}
-	if (rv < 0)
-		fprintf(stderr, "Failed with %d\n", rv);
-	else
-		rv = 0;
-	free(buffer);
-	return rv;
-}
-
-/**
- * determine if in GFU mode or not.
- *
- * NOTE, Sends HOST commands that modify ec_outbuf contents.
- *
- * @opos return value of GFU mode object position or zero if not found
- * @port port number to query
- * @return 1 if in GFU mode, 0 if not, -1 if error
- */
-static int in_gfu_mode(int *opos, int port)
-{
-	int i;
-	struct ec_params_usb_pd_get_mode_request *p =
-		(struct ec_params_usb_pd_get_mode_request *)ec_outbuf;
-	struct ec_params_usb_pd_get_mode_response *r =
-		(struct ec_params_usb_pd_get_mode_response *)ec_inbuf;
-	p->port = port;
-	p->svid_idx = 0;
-	do {
-		ec_command(EC_CMD_USB_PD_GET_AMODE, 0, p, sizeof(*p),
-			   ec_inbuf, ec_max_insize);
-		if (!r->svid || (r->svid == USB_VID_GOOGLE))
-			break;
-		p->svid_idx++;
-	} while (p->svid_idx < SVID_DISCOVERY_MAX);
-
-	if (r->svid != USB_VID_GOOGLE) {
-		fprintf(stderr, "Google VID not returned\n");
-		return -1;
-	}
-
-	*opos = 0; /* invalid ... must be 1 thru 6 */
-	for (i = 0; i < PDO_MODES; i++) {
-		if (r->vdo[i] == MODE_GOOGLE_FU) {
-			*opos = i + 1;
-			break;
-		}
-	}
-
-	return r->opos == *opos;
-}
-
-/**
- * Enter GFU mode.
- *
- * NOTE, Sends HOST commands that modify ec_outbuf contents.
- *
- * @port port number to enter GFU on.
- * @return 1 if entered GFU mode, 0 if not, -1 if error
- */
-static int enter_gfu_mode(int port)
-{
-	int opos;
-	struct ec_params_usb_pd_set_mode_request *p =
-		(struct ec_params_usb_pd_set_mode_request *)ec_outbuf;
-	int gfu_mode = in_gfu_mode(&opos, port);
-
-	if (gfu_mode < 0) {
-		fprintf(stderr, "Failed to query GFU mode support\n");
-		return 0;
-	} else if (!gfu_mode) {
-		if (!opos) {
-			fprintf(stderr, "Invalid object position %d\n", opos);
-			return 0;
-		}
-		p->port = port;
-		p->svid = USB_VID_GOOGLE;
-		p->opos = opos;
-		p->cmd = PD_ENTER_MODE;
-
-		ec_command(EC_CMD_USB_PD_SET_AMODE, 0, p, sizeof(*p),
-			   NULL, 0);
-		usleep(500000); /* sleep to allow time for set mode */
-		gfu_mode = in_gfu_mode(&opos, port);
-	}
-	return gfu_mode;
-}
-
-int cmd_pd_device_info(int argc, char *argv[])
-{
-	int i, rv, port;
-	char *e;
-	struct ec_params_usb_pd_info_request *p =
-		(struct ec_params_usb_pd_info_request *)ec_outbuf;
-	struct ec_params_usb_pd_rw_hash_entry *r0 =
-		(struct ec_params_usb_pd_rw_hash_entry *)ec_inbuf;
-	struct ec_params_usb_pd_discovery_entry *r1;
-
-	if (argc < 2) {
-		fprintf(stderr, "Usage: %s <port>\n", argv[0]);
-		return -1;
-	}
-
-	port = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad port\n");
-		return -1;
-	}
-
-	p->port = port;
-	r1 = (struct ec_params_usb_pd_discovery_entry *)ec_inbuf;
-	rv = ec_command(EC_CMD_USB_PD_DISCOVERY, 0, p, sizeof(*p),
-			ec_inbuf, ec_max_insize);
-	if (rv < 0)
-		return rv;
-
-	if (!r1->vid)
-		printf("Port:%d has no discovered device\n", port);
-	else {
-		printf("Port:%d ptype:%d vid:0x%04x pid:0x%04x\n", port,
-		       r1->ptype, r1->vid, r1->pid);
-	}
-
-	if (enter_gfu_mode(port) != 1) {
-		fprintf(stderr, "Failed to enter GFU mode\n");
-		return -1;
-	}
-
-	p->port = port;
-	rv = ec_command(EC_CMD_USB_PD_DEV_INFO, 0, p, sizeof(*p),
-			ec_inbuf, ec_max_insize);
-	if (rv < 0)
-		return rv;
-
-	if (!r0->dev_id)
-		printf("Port:%d has no valid device\n", port);
-	else {
-		uint8_t *rwp = r0->dev_rw_hash;
-		printf("Port:%d DevId:%d.%d Hash:", port,
-		       HW_DEV_ID_MAJ(r0->dev_id), HW_DEV_ID_MIN(r0->dev_id));
-		for (i = 0; i < 5; i++) {
-			printf(" 0x%02x%02x%02x%02x", rwp[3], rwp[2], rwp[1],
-			       rwp[0]);
-			rwp += 4;
-		}
-		printf(" CurImg:%s\n", image_names[r0->current_image]);
-	}
-
-	return rv;
-}
-
-int cmd_flash_pd(int argc, char *argv[])
-{
-	struct ec_params_usb_pd_fw_update *p =
-		(struct ec_params_usb_pd_fw_update *)ec_outbuf;
-	int i, dev_id, port;
-	int rv, fsize, step = 96;
-	char *e;
-	char *buf;
-	char *data = (char *)p + sizeof(*p);
-
-	if (argc < 4) {
-		fprintf(stderr, "Usage: %s <dev_id> <port> <filename>\n",
-			argv[0]);
-		return -1;
-	}
-
-	dev_id = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad device ID\n");
-		return -1;
-	}
-
-	port = strtol(argv[2], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad port\n");
-		return -1;
-	}
-
-	if (enter_gfu_mode(port) != 1) {
-		fprintf(stderr, "Failed to enter GFU mode\n");
-		return -1;
-	}
-
-	/* Read the input file */
-	buf = read_file(argv[3], &fsize);
-	if (!buf)
-		return -1;
-
-	/* Erase the current RW RSA signature */
-	fprintf(stderr, "Erasing expected RW hash\n");
-	p->dev_id = dev_id;
-	p->port = port;
-	p->cmd = USB_PD_FW_ERASE_SIG;
-	p->size = 0;
-	rv = ec_command(EC_CMD_USB_PD_FW_UPDATE, 0,
-			p, p->size + sizeof(*p), NULL, 0);
-
-	if (rv < 0)
-		goto pd_flash_error;
-
-	/* Reboot */
-	fprintf(stderr, "Rebooting\n");
-	p->dev_id = dev_id;
-	p->port = port;
-	p->cmd = USB_PD_FW_REBOOT;
-	p->size = 0;
-	rv = ec_command(EC_CMD_USB_PD_FW_UPDATE, 0,
-			p, p->size + sizeof(*p), NULL, 0);
-
-	if (rv < 0)
-		goto pd_flash_error;
-
-	usleep(3000000); /* 3sec to reboot and get CC line idle */
-
-	/* re-enter GFU after reboot */
-	if (enter_gfu_mode(port) != 1) {
-		fprintf(stderr, "Failed to enter GFU mode\n");
-		goto pd_flash_error;
-	}
-
-	/* Erase RW flash */
-	fprintf(stderr, "Erasing RW flash\n");
-	p->dev_id = dev_id;
-	p->port = port;
-	p->cmd = USB_PD_FW_FLASH_ERASE;
-	p->size = 0;
-	rv = ec_command(EC_CMD_USB_PD_FW_UPDATE, 0,
-			p, p->size + sizeof(*p), NULL, 0);
-
-	/* 3 secs should allow ample time for 2KB page erases at 40ms */
-	usleep(3000000);
-
-	if (rv < 0)
-		goto pd_flash_error;
-
-	/* Write RW flash */
-	fprintf(stderr, "Writing RW flash\n");
-	p->dev_id = dev_id;
-	p->port = port;
-	p->cmd = USB_PD_FW_FLASH_WRITE;
-	p->size = step;
-
-	for (i = 0; i < fsize; i += step) {
-		p->size = MIN(fsize - i, step);
-		memcpy(data, buf + i, p->size);
-		rv = ec_command(EC_CMD_USB_PD_FW_UPDATE, 0,
-				p, p->size + sizeof(*p), NULL, 0);
-		if (rv < 0)
-			goto pd_flash_error;
-
-		/*
-		 * TODO(crosbug.com/p/33905) throttle so EC doesn't watchdog on
-		 * other tasks.  Remove once issue resolved.
-		 */
-		usleep(10000);
-	}
-
-	/* 100msec to guarantee writes finish */
-	usleep(100000);
-
-	/* Reboot into new RW */
-	fprintf(stderr, "Rebooting PD into new RW\n");
-	p->cmd = USB_PD_FW_REBOOT;
-	p->size = 0;
-	rv = ec_command(EC_CMD_USB_PD_FW_UPDATE, 0,
-			p, p->size + sizeof(*p), NULL, 0);
-
-	if (rv < 0)
-		goto pd_flash_error;
-
-	free(buf);
-	fprintf(stderr, "Complete\n");
-	return 0;
-
-pd_flash_error:
-	free(buf);
-	fprintf(stderr, "PD flash error\n");
-	return -1;
-}
-
-int cmd_pd_set_amode(int argc, char *argv[])
-{
-	char *e;
-	struct ec_params_usb_pd_set_mode_request *p =
-		(struct ec_params_usb_pd_set_mode_request *)ec_outbuf;
-
-	if (argc < 5) {
-		fprintf(stderr, "Usage: %s <port> <svid> <opos> <cmd>\n",
-			argv[0]);
-		return -1;
-	}
-
-	p->port = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad port\n");
-		return -1;
-	}
-
-	p->svid = strtol(argv[2], &e, 0);
-	if ((e && *e) || !p->svid) {
-		fprintf(stderr, "Bad svid\n");
-		return -1;
-	}
-
-	p->opos = strtol(argv[3], &e, 0);
-	if ((e && *e) || !p->opos) {
-		fprintf(stderr, "Bad opos\n");
-		return -1;
-	}
-
-	p->cmd = strtol(argv[4], &e, 0);
-	if ((e && *e) || (p->cmd >= PD_MODE_CMD_COUNT)) {
-		fprintf(stderr, "Bad cmd\n");
-		return -1;
-	}
-	return ec_command(EC_CMD_USB_PD_SET_AMODE, 0, p, sizeof(*p), NULL, 0);
-}
-
-int cmd_pd_get_amode(int argc, char *argv[])
-{
-	int i;
-	char *e;
-	struct ec_params_usb_pd_get_mode_request *p =
-		(struct ec_params_usb_pd_get_mode_request *)ec_outbuf;
-	struct ec_params_usb_pd_get_mode_response *r =
-		(struct ec_params_usb_pd_get_mode_response *)ec_inbuf;
-
-	if (argc < 2) {
-		fprintf(stderr, "Usage: %s <port>\n", argv[0]);
-		return -1;
-	}
-
-	p->port = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad port\n");
-		return -1;
-	}
-
-	p->svid_idx = 0;
-	do {
-		ec_command(EC_CMD_USB_PD_GET_AMODE, 0, p, sizeof(*p),
-			   ec_inbuf, ec_max_insize);
-		if (!r->svid)
-			break;
-		printf("%cSVID:0x%04x ", (r->opos) ? '*' : ' ',
-		       r->svid);
-		for (i = 0; i < PDO_MODES; i++) {
-			printf("%c0x%08x ", (r->opos && (r->opos == i + 1)) ?
-			       '*' : ' ', r->vdo[i]);
-		}
-		printf("\n");
-		p->svid_idx++;
-	} while (p->svid_idx < SVID_DISCOVERY_MAX);
-	return -1;
-}
-
-/* The I/O asm funcs exist only on x86. */
-#if defined(__i386__) || defined(__x86_64__)
-#include <sys/io.h>
-
-int cmd_serial_test(int argc, char *argv[])
-{
-	const char *c = "COM2 sample serial output from host!\r\n";
-
-	printf("Writing sample serial output to COM2\n");
-
-	while (*c) {
-		/* Wait for space in transmit FIFO */
-		while (!(inb(0x2fd) & 0x20))
-			;
-
-		/* Put the next character */
-		outb(*c++, 0x2f8);
-	}
-
-	printf("done.\n");
-	return 0;
-}
-
-
-int cmd_port_80_flood(int argc, char *argv[])
-{
-	int i;
-
-	for (i = 0; i < 256; i++)
-		outb(i, 0x80);
-	return 0;
-}
-#else
-int cmd_serial_test(int argc, char *argv[])
-{
-	printf("x86 specific command\n");
-	return -1;
-}
-
-int cmd_port_80_flood(int argc, char *argv[])
-{
-	printf("x86 specific command\n");
-	return -1;
-}
-#endif
-
-static void cmd_smart_discharge_usage(const char *command)
-{
-	printf("Usage: %s [hours_to_zero [hibern] [cutoff]]\n", command);
-	printf("\n");
-	printf("Set/Get smart discharge parameters\n");
-	printf("hours_to_zero: Desired hours for state of charge to zero\n");
-	printf("hibern: Discharge rate in hibernation (uA)\n");
-	printf("cutoff: Discharge rate in battery cutoff (uA)\n");
-}
-
-int cmd_smart_discharge(int argc, char *argv[])
-{
-	struct ec_params_smart_discharge *p = ec_outbuf;
-	struct ec_response_smart_discharge *r = ec_inbuf;
-	uint32_t cap;
-	char *e;
-	int rv;
-
-	if (argc > 1) {
-		if (strcmp(argv[1], "help") == 0) {
-			cmd_smart_discharge_usage(argv[0]);
-			return 0;
-		}
-		p->flags = EC_SMART_DISCHARGE_FLAGS_SET;
-		p->hours_to_zero = strtol(argv[1], &e, 0);
-		if (p->hours_to_zero < 0 || (e && *e)) {
-			perror("Bad value for [hours_to_zero]");
-			return -1;
-		}
-		if (argc == 4) {
-			p->drate.hibern = strtol(argv[2], &e, 0);
-			if (p->drate.hibern < 0 || (e && *e)) {
-				perror("Bad value for [hibern]");
-				return -1;
-			}
-			p->drate.cutoff = strtol(argv[3], &e, 0);
-			if (p->drate.cutoff < 0 || (e && *e)) {
-				perror("Bad value for [cutoff]");
-				return -1;
-			}
-		} else if (argc != 2) {
-			/* If argc != 4, it has to be 2. */
-			perror("Invalid number of parameters");
-			return -1;
-		}
-	}
-
-	rv = ec_command(EC_CMD_SMART_DISCHARGE, 0, p, sizeof(*p),
-			r, ec_max_insize);
-	if (rv < 0) {
-		perror("ERROR: EC_CMD_SMART_DISCHARGE failed");
-		return rv;
-	}
-
-	cap = read_mapped_mem32(EC_MEMMAP_BATT_LFCC);
-	if (!is_battery_range(cap)) {
-		perror("WARN: Failed to read battery capacity");
-		cap = 0;
-	}
-
-	printf("%-27s %5d h\n", "Hours to zero capacity:", r->hours_to_zero);
-	printf("%-27s %5d mAh (%d %%)\n", "Stay-up threshold:",
-	       r->dzone.stayup, cap > 0 ? r->dzone.stayup * 100 / cap : -1);
-	printf("%-27s %5d mAh (%d %%)\n", "Cutoff threshold:",
-	       r->dzone.cutoff, cap > 0 ? r->dzone.cutoff * 100 / cap : -1);
-	printf("%-27s %5d uA\n", "Hibernate discharge rate:", r->drate.hibern);
-	printf("%-27s %5d uA\n", "Cutoff discharge rate:", r->drate.cutoff);
-
-	return 0;
-}
-
-/*
- * This boolean variable and handler are used for
- * catching signals that translate into a quit/shutdown
- * of a runtime loop.
- * This is used in cmd_stress_test.
- */
-static bool sig_quit;
-static void sig_quit_handler(int sig)
-{
-	sig_quit = true;
-}
-
-int cmd_stress_test(int argc, char *argv[])
-{
-	int i;
-	bool reboot = false;
-	time_t now;
-	time_t start_time, last_update_time;
-	unsigned int rand_seed = 0;
-	uint64_t round = 1, attempt = 1;
-	uint64_t failures = 0;
-
-	const int max_sleep_usec = 1000; /* 1ms */
-	const int loop_update_interval = 10000;
-
-	for (i = 1; i < argc; i++) {
-		if (strcmp(argv[i], "help") == 0) {
-			printf("Usage: %s [reboot] [help]\n", argv[0]);
-			printf("Stress tests the host command interface by"
-			       " repeatedly issuing common host commands.\n");
-			printf("The intent is to expose errors in kernel<->mcu"
-			       " communication, such as exceeding timeouts.\n");
-			printf("\n");
-			printf("reboot - Reboots the target before"
-			       " starting the stress test.\n");
-			printf("         This may force restart the host,"
-			       " if the main ec is the target.\n");
-			return 0;
-		} else if (strcmp(argv[i], "reboot") == 0) {
-			reboot = true;
-		} else {
-			fprintf(stderr, "Error - Unknown argument '%s'\n",
-				argv[i]);
-			return 1;
-		}
-	}
-
-	printf("Stress test tool version: %s %s %s\n",
-	       CROS_ECTOOL_VERSION, DATE, BUILDER);
-
-	start_time = time(NULL);
-	last_update_time = start_time;
-	printf("Start time: %s\n", ctime(&start_time));
-
-	if (reboot) {
-		printf("Issuing ec reboot. Expect a few early failed"
-		       " ioctl messages.\n");
-		ec_command(EC_CMD_REBOOT, 0, NULL, 0, NULL, 0);
-		sleep(2);
-	}
-
-	sig_quit = false;
-	signal(SIGINT, sig_quit_handler);
-	while (!sig_quit) {
-		int rv;
-		struct ec_response_get_version ver_r;
-		char *build_string = (char *)ec_inbuf;
-		struct ec_params_flash_protect flash_p;
-		struct ec_response_flash_protect flash_r;
-		struct ec_params_hello hello_p;
-		struct ec_response_hello hello_r;
-
-		/* Request EC Version Strings */
-		rv = ec_command(EC_CMD_GET_VERSION, 0,
-				NULL, 0, &ver_r, sizeof(ver_r));
-		if (rv < 0) {
-			failures++;
-			perror("ERROR: EC_CMD_GET_VERSION failed");
-		}
-		ver_r.version_string_ro[sizeof(ver_r.version_string_ro) - 1]
-			= '\0';
-		ver_r.version_string_rw[sizeof(ver_r.version_string_rw) - 1]
-			= '\0';
-		if (strlen(ver_r.version_string_ro) == 0) {
-			failures++;
-			fprintf(stderr, "RO version string is empty\n");
-		}
-		if (strlen(ver_r.version_string_rw) == 0) {
-			failures++;
-			fprintf(stderr, "RW version string is empty\n");
-		}
-
-		usleep(rand_r(&rand_seed) % max_sleep_usec);
-
-		/* Request EC Build String */
-		rv = ec_command(EC_CMD_GET_BUILD_INFO, 0,
-				NULL, 0, ec_inbuf, ec_max_insize);
-		if (rv < 0) {
-			failures++;
-			perror("ERROR: EC_CMD_GET_BUILD_INFO failed");
-		}
-		build_string[ec_max_insize - 1] = '\0';
-		if (strlen(build_string) == 0) {
-			failures++;
-			fprintf(stderr, "Build string is empty\n");
-		}
-
-		usleep(rand_r(&rand_seed) % max_sleep_usec);
-
-		/* Request Flash Protect Status */
-		rv = ec_command(EC_CMD_FLASH_PROTECT, EC_VER_FLASH_PROTECT,
-				&flash_p, sizeof(flash_p), &flash_r,
-				sizeof(flash_r));
-		if (rv < 0) {
-			failures++;
-			perror("ERROR: EC_CMD_FLASH_PROTECT failed");
-		}
-
-		usleep(rand_r(&rand_seed) % max_sleep_usec);
-
-		/* Request Hello */
-		hello_p.in_data = 0xa0b0c0d0;
-		rv = ec_command(EC_CMD_HELLO, 0, &hello_p, sizeof(hello_p),
-				&hello_r, sizeof(hello_r));
-		if (rv < 0) {
-			failures++;
-			perror("ERROR: EC_CMD_HELLO failed");
-		}
-		if (hello_r.out_data != HELLO_RESP(hello_p.in_data)) {
-			failures++;
-			fprintf(stderr, "Hello response was invalid.\n");
-		}
-
-		usleep(rand_r(&rand_seed) % max_sleep_usec);
-
-		if ((attempt % loop_update_interval) == 0) {
-			now = time(NULL);
-			printf("Update: attempt %" PRIu64 " round %" PRIu64
-			       " | took %.f seconds\n",
-			       attempt, round,
-			       difftime(now, last_update_time));
-			last_update_time = now;
-		}
-
-		if (attempt++ == UINT64_MAX)
-			round++;
-	}
-	printf("\n");
-
-	now = time(NULL);
-	printf("End time:        %s\n", ctime(&now));
-	printf("Total runtime:   %.f seconds\n",
-		difftime(time(NULL), start_time));
-	printf("Total failures:  %" PRIu64 "\n", failures);
-	return 0;
-}
-
-int read_mapped_temperature(int id)
-{
-	int rv;
-
-	if (!read_mapped_mem8(EC_MEMMAP_THERMAL_VERSION)) {
-		/*
-		 *  The temp_sensor_init() is not called, which implies no
-		 * temp sensor is defined.
-		 */
-		rv = EC_TEMP_SENSOR_NOT_PRESENT;
-	} else if (id < EC_TEMP_SENSOR_ENTRIES)
-		rv = read_mapped_mem8(EC_MEMMAP_TEMP_SENSOR + id);
-	else if (read_mapped_mem8(EC_MEMMAP_THERMAL_VERSION) >= 2)
-		rv = read_mapped_mem8(EC_MEMMAP_TEMP_SENSOR_B +
-				      id - EC_TEMP_SENSOR_ENTRIES);
-	else {
-		/* Sensor in second bank, but second bank isn't supported */
-		rv = EC_TEMP_SENSOR_NOT_PRESENT;
-	}
-	return rv;
-}
-
-
-int cmd_temperature(int argc, char *argv[])
-{
-	int rv;
-	int id;
-	char *e;
-
-	if (argc != 2) {
-		fprintf(stderr, "Usage: %s <sensorid> | all\n", argv[0]);
-		return -1;
-	}
-
-	if (strcmp(argv[1], "all") == 0) {
-		for (id = 0;
-		     id < EC_TEMP_SENSOR_ENTRIES + EC_TEMP_SENSOR_B_ENTRIES;
-		     id++) {
-			rv = read_mapped_temperature(id);
-			switch (rv) {
-			case EC_TEMP_SENSOR_NOT_PRESENT:
-				break;
-			case EC_TEMP_SENSOR_ERROR:
-				fprintf(stderr, "Sensor %d error\n", id);
-				break;
-			case EC_TEMP_SENSOR_NOT_POWERED:
-				fprintf(stderr, "Sensor %d disabled\n", id);
-				break;
-			case EC_TEMP_SENSOR_NOT_CALIBRATED:
-				fprintf(stderr, "Sensor %d not calibrated\n",
-					id);
-				break;
-			default:
-				printf("%d: %d K\n", id,
-				       rv + EC_TEMP_SENSOR_OFFSET);
-			}
-		}
-		return 0;
-	}
-
-	id = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad sensor ID.\n");
-		return -1;
-	}
-
-	if (id < 0 ||
-	    id >= EC_TEMP_SENSOR_ENTRIES + EC_TEMP_SENSOR_B_ENTRIES) {
-		printf("Sensor ID invalid.\n");
-		return -1;
-	}
-
-	printf("Reading temperature...");
-	rv = read_mapped_temperature(id);
-
-	switch (rv) {
-	case EC_TEMP_SENSOR_NOT_PRESENT:
-		printf("Sensor not present\n");
-		return -1;
-	case EC_TEMP_SENSOR_ERROR:
-		printf("Error\n");
-		return -1;
-	case EC_TEMP_SENSOR_NOT_POWERED:
-		printf("Sensor disabled/unpowered\n");
-		return -1;
-	case EC_TEMP_SENSOR_NOT_CALIBRATED:
-		fprintf(stderr, "Sensor not calibrated\n");
-		return -1;
-	default:
-		printf("%d K\n", rv + EC_TEMP_SENSOR_OFFSET);
-		return 0;
-	}
-}
-
-
-int cmd_temp_sensor_info(int argc, char *argv[])
-{
-	struct ec_params_temp_sensor_get_info p;
-	struct ec_response_temp_sensor_get_info r;
-	int rv;
-	char *e;
-
-	if (argc != 2) {
-		fprintf(stderr, "Usage: %s <sensorid> | all\n", argv[0]);
-		return -1;
-	}
-
-	if (strcmp(argv[1], "all") == 0) {
-		for (p.id = 0;
-		     p.id < EC_TEMP_SENSOR_ENTRIES + EC_TEMP_SENSOR_B_ENTRIES;
-		     p.id++) {
-			if (read_mapped_temperature(p.id) ==
-			    EC_TEMP_SENSOR_NOT_PRESENT)
-				continue;
-			rv = ec_command(EC_CMD_TEMP_SENSOR_GET_INFO, 0,
-					&p, sizeof(p), &r, sizeof(r));
-			if (rv < 0)
-				continue;
-			printf("%d: %d %s\n", p.id, r.sensor_type,
-			       r.sensor_name);
-		}
-		return 0;
-	}
-
-	p.id = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad sensor ID.\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_TEMP_SENSOR_GET_INFO, 0,
-			&p, sizeof(p), &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	printf("Sensor name: %s\n", r.sensor_name);
-	printf("Sensor type: %d\n", r.sensor_type);
-
-	return 0;
-}
-
-
-int cmd_thermal_get_threshold_v0(int argc, char *argv[])
-{
-	struct ec_params_thermal_get_threshold p;
-	struct ec_response_thermal_get_threshold r;
-	char *e;
-	int rv;
-
-	if (argc != 3) {
-		fprintf(stderr,
-			"Usage: %s <sensortypeid> <thresholdid>\n", argv[0]);
-		return -1;
-	}
-
-	p.sensor_type = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad sensor type ID.\n");
-		return -1;
-	}
-
-	p.threshold_id = strtol(argv[2], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad threshold ID.\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_THERMAL_GET_THRESHOLD, 0,
-			&p, sizeof(p), &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	printf("Threshold %d for sensor type %d is %d K.\n",
-			p.threshold_id, p.sensor_type, r.value);
-
-	return 0;
-}
-
-
-int cmd_thermal_set_threshold_v0(int argc, char *argv[])
-{
-	struct ec_params_thermal_set_threshold p;
-	char *e;
-	int rv;
-
-	if (argc != 4) {
-		fprintf(stderr,
-			"Usage: %s <sensortypeid> <thresholdid> <value>\n",
-			argv[0]);
-		return -1;
-	}
-
-	p.sensor_type = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad sensor type ID.\n");
-		return -1;
-	}
-
-	p.threshold_id = strtol(argv[2], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad threshold ID.\n");
-		return -1;
-	}
-
-	p.value = strtol(argv[3], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad threshold value.\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_THERMAL_SET_THRESHOLD, 0,
-			&p, sizeof(p), NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	printf("Threshold %d for sensor type %d set to %d.\n",
-			p.threshold_id, p.sensor_type, p.value);
-
-	return 0;
-}
-
-
-int cmd_thermal_get_threshold_v1(int argc, char *argv[])
-{
-	struct ec_params_thermal_get_threshold_v1 p;
-	struct ec_thermal_config r;
-	struct ec_params_temp_sensor_get_info pi;
-	struct ec_response_temp_sensor_get_info ri;
-	int rv;
-	int i;
-
-	printf("sensor  warn  high  halt   fan_off fan_max   name\n");
-	for (i = 0; i < 99; i++) {	/* number of sensors is unknown */
-
-		/* ask for one */
-		p.sensor_num = i;
-		rv = ec_command(EC_CMD_THERMAL_GET_THRESHOLD, 1,
-				&p, sizeof(p), &r, sizeof(r));
-		if (rv <= 0)		/* stop on first failure */
-			break;
-
-		/* ask for its name, too */
-		pi.id = i;
-		rv = ec_command(EC_CMD_TEMP_SENSOR_GET_INFO, 0,
-				&pi, sizeof(pi), &ri, sizeof(ri));
-
-		/* print what we know */
-		printf(" %2d      %3d   %3d    %3d    %3d     %3d     %s\n",
-		       i,
-		       r.temp_host[EC_TEMP_THRESH_WARN],
-		       r.temp_host[EC_TEMP_THRESH_HIGH],
-		       r.temp_host[EC_TEMP_THRESH_HALT],
-		       r.temp_fan_off, r.temp_fan_max,
-		       rv > 0 ? ri.sensor_name : "?");
-	}
-	if (i)
-		printf("(all temps in degrees Kelvin)\n");
-
-	return 0;
-}
-
-int cmd_thermal_set_threshold_v1(int argc, char *argv[])
-{
-	struct ec_params_thermal_get_threshold_v1 p;
-	struct ec_thermal_config r;
-	struct ec_params_thermal_set_threshold_v1 s;
-	int i, n, val, rv;
-	char *e;
-
-	if (argc < 3 || argc > 7) {
-		printf("Usage: %s"
-		       " sensor warn [high [shutdown [fan_off [fan_max]]]]\n",
-		       argv[0]);
-		return 1;
-	}
-
-	n = strtod(argv[1], &e);
-	if (e && *e) {
-		printf("arg %d is invalid\n", 1);
-		return 1;
-	}
-
-	p.sensor_num = n;
-	rv = ec_command(EC_CMD_THERMAL_GET_THRESHOLD, 1,
-			&p, sizeof(p), &r, sizeof(r));
-	if (rv <= 0)
-		return rv;
-
-	s.sensor_num = n;
-	s.cfg = r;
-
-	for (i = 2; i < argc; i++) {
-		val = strtod(argv[i], &e);
-		if (e && *e) {
-			printf("arg %d is invalid\n", i);
-			return 1;
-		}
-
-		if (val < 0)
-			continue;
-		switch (i) {
-		case 2:
-		case 3:
-		case 4:
-			s.cfg.temp_host[i-2] = val;
-			break;
-		case 5:
-			s.cfg.temp_fan_off = val;
-			break;
-		case 6:
-			s.cfg.temp_fan_max = val;
-			break;
-		}
-	}
-
-	rv = ec_command(EC_CMD_THERMAL_SET_THRESHOLD, 1,
-			&s, sizeof(s), NULL, 0);
-
-	return rv;
-}
-
-int cmd_thermal_get_threshold(int argc, char *argv[])
-{
-	if (ec_cmd_version_supported(EC_CMD_THERMAL_GET_THRESHOLD, 1))
-		return cmd_thermal_get_threshold_v1(argc, argv);
-	else if (ec_cmd_version_supported(EC_CMD_THERMAL_GET_THRESHOLD, 0))
-		return cmd_thermal_get_threshold_v0(argc, argv);
-
-	printf("I got nuthin.\n");
-	return -1;
-}
-
-int cmd_thermal_set_threshold(int argc, char *argv[])
-{
-	if (ec_cmd_version_supported(EC_CMD_THERMAL_SET_THRESHOLD, 1))
-		return cmd_thermal_set_threshold_v1(argc, argv);
-	else if (ec_cmd_version_supported(EC_CMD_THERMAL_SET_THRESHOLD, 0))
-		return cmd_thermal_set_threshold_v0(argc, argv);
-
-	printf("I got nuthin.\n");
-	return -1;
-}
-
-
-static int get_num_fans(void)
-{
-	int idx, rv;
-	struct ec_response_get_features r;
-
-	/*
-	 * iff the EC supports the GET_FEATURES,
-	 * check whether it has fan support enabled.
-	 */
-	rv = ec_command(EC_CMD_GET_FEATURES, 0, NULL, 0, &r, sizeof(r));
-	if (rv >= 0 && !(r.flags[0] & BIT(EC_FEATURE_PWM_FAN)))
-		return 0;
-
-	for (idx = 0; idx < EC_FAN_SPEED_ENTRIES; idx++) {
-		rv = read_mapped_mem16(EC_MEMMAP_FAN + 2 * idx);
-		if (rv == EC_FAN_SPEED_NOT_PRESENT)
-			break;
-	}
-
-	return idx;
-}
-
-int cmd_thermal_auto_fan_ctrl(int argc, char *argv[])
-{
-	int rv, num_fans;
-	struct ec_params_auto_fan_ctrl_v1 p_v1;
-	char *e;
-	int cmdver = 1;
-
-	if (!ec_cmd_version_supported(EC_CMD_THERMAL_AUTO_FAN_CTRL, cmdver)
-	    || (argc == 1)) {
-		/* If no argument is provided then enable auto fan ctrl */
-		/* for all fans by using version 0 of the host command */
-
-		rv = ec_command(EC_CMD_THERMAL_AUTO_FAN_CTRL, 0,
-				NULL, 0, NULL, 0);
-		if (rv < 0)
-			return rv;
-
-		printf("Automatic fan control is now on for all fans.\n");
-		return 0;
-	}
-
-	if (argc > 2 || !strcmp(argv[1], "help")) {
-		printf("Usage: %s [idx]\n", argv[0]);
-		return -1;
-	}
-
-	num_fans = get_num_fans();
-	p_v1.fan_idx = strtol(argv[1], &e, 0);
-	if ((e && *e) || (p_v1.fan_idx >= num_fans)) {
-		fprintf(stderr, "Bad fan index.\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_THERMAL_AUTO_FAN_CTRL, cmdver,
-			&p_v1, sizeof(p_v1), NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	printf("Automatic fan control is now on for fan %d\n", p_v1.fan_idx);
-
-	return 0;
-}
-
-static int print_fan(int idx)
-{
-	int rv = read_mapped_mem16(EC_MEMMAP_FAN + 2 * idx);
-
-	switch (rv) {
-	case EC_FAN_SPEED_NOT_PRESENT:
-		return -1;
-	case EC_FAN_SPEED_STALLED:
-		printf("Fan %d stalled!\n", idx);
-		break;
-	default:
-		printf("Fan %d RPM: %d\n", idx, rv);
-		break;
-	}
-
-	return 0;
-}
-
-int cmd_pwm_get_num_fans(int argc, char *argv[])
-{
-	int num_fans;
-
-	num_fans = get_num_fans();
-
-	printf("Number of fans = %d\n", num_fans);
-
-	return 0;
-}
-
-int cmd_pwm_get_fan_rpm(int argc, char *argv[])
-{
-	int i, num_fans;
-
-	num_fans = get_num_fans();
-	if (argc < 2 || !strcasecmp(argv[1], "all")) {
-		/* Print all the fan speeds */
-		for (i = 0; i < num_fans; i++)
-			print_fan(i);
-	} else {
-		char *e;
-		int idx;
-
-		idx = strtol(argv[1], &e, 0);
-		if ((e && *e) || idx < 0 || idx >= num_fans) {
-			fprintf(stderr, "Bad index.\n");
-			return -1;
-		}
-
-		print_fan(idx);
-	}
-
-	return 0;
-}
-
-
-int cmd_pwm_set_fan_rpm(int argc, char *argv[])
-{
-	struct ec_params_pwm_set_fan_target_rpm_v1 p_v1;
-	char *e;
-	int rv, num_fans;
-	int cmdver = 1;
-
-	if (!ec_cmd_version_supported(EC_CMD_PWM_SET_FAN_TARGET_RPM, cmdver)) {
-		struct ec_params_pwm_set_fan_target_rpm_v0 p_v0;
-
-		/* Fall back to command version 0 command */
-		cmdver = 0;
-
-		if (argc != 2) {
-			fprintf(stderr,
-				"Usage: %s <targetrpm>\n", argv[0]);
-			return -1;
-		}
-		p_v0.rpm = strtol(argv[1], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad RPM.\n");
-			return -1;
-		}
-
-		rv = ec_command(EC_CMD_PWM_SET_FAN_TARGET_RPM, cmdver,
-				&p_v0, sizeof(p_v0), NULL, 0);
-		if (rv < 0)
-			return rv;
-
-		printf("Fan target RPM set for all fans.\n");
-		return 0;
-	}
-
-	if (argc > 3 || (argc == 2 && !strcmp(argv[1], "help")) || argc == 1) {
-		printf("Usage: %s [idx] <targetrpm>\n", argv[0]);
-		printf("'%s 0 3000' - Set fan 0 RPM to 3000\n", argv[0]);
-		printf("'%s 3000' - Set all fans RPM to 3000\n", argv[0]);
-		return -1;
-	}
-
-	num_fans = get_num_fans();
-	p_v1.rpm = strtol(argv[argc - 1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad RPM.\n");
-		return -1;
-	}
-
-	if (argc == 2) {
-		/* Reuse version 0 command if we're setting targetrpm
-		 * for all fans */
-		struct ec_params_pwm_set_fan_target_rpm_v0 p_v0;
-
-		cmdver = 0;
-		p_v0.rpm = p_v1.rpm;
-
-		rv = ec_command(EC_CMD_PWM_SET_FAN_TARGET_RPM, cmdver,
-				&p_v0, sizeof(p_v0), NULL, 0);
-		if (rv < 0)
-			return rv;
-
-		printf("Fan target RPM set for all fans.\n");
-	} else {
-		p_v1.fan_idx = strtol(argv[1], &e, 0);
-		if ((e && *e) || (p_v1.fan_idx >= num_fans)) {
-			fprintf(stderr, "Bad fan index.\n");
-			return -1;
-		}
-
-		rv = ec_command(EC_CMD_PWM_SET_FAN_TARGET_RPM, cmdver,
-				&p_v1, sizeof(p_v1), NULL, 0);
-		if (rv < 0)
-			return rv;
-
-		printf("Fan %d target RPM set.\n", p_v1.fan_idx);
-	}
-
-	return 0;
-}
-
-int cmd_pwm_get_keyboard_backlight(int argc, char *argv[])
-{
-	struct ec_response_pwm_get_keyboard_backlight r;
-	int rv;
-
-	rv = ec_command(EC_CMD_PWM_GET_KEYBOARD_BACKLIGHT, 0,
-			NULL, 0, &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	if (r.enabled == 1)
-		printf("Current keyboard backlight percent: %d\n", r.percent);
-	else
-		printf("Keyboard backlight disabled.\n");
-
-	return 0;
-}
-
-
-int cmd_pwm_set_keyboard_backlight(int argc, char *argv[])
-{
-	struct ec_params_pwm_set_keyboard_backlight p;
-	char *e;
-	int rv;
-
-	if (argc != 2) {
-		fprintf(stderr, "Usage: %s <percent>\n", argv[0]);
-		return -1;
-	}
-	p.percent = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad percent.\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT, 0,
-			&p, sizeof(p), NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	printf("Keyboard backlight set.\n");
-	return 0;
-}
-
-int cmd_pwm_get_duty(int argc, char *argv[])
-{
-	struct ec_params_pwm_get_duty p;
-	struct ec_response_pwm_get_duty r;
-	char *e;
-	int rv;
-
-	if (argc != 2) {
-		fprintf(stderr, "Usage: %s <pwm_idx> | kb | disp\n", argv[0]);
-		return -1;
-	}
-
-	if (!strcmp(argv[1], "kb")) {
-		p.pwm_type = EC_PWM_TYPE_KB_LIGHT;
-		p.index = 0;
-	} else if (!strcmp(argv[1], "disp")) {
-		p.pwm_type = EC_PWM_TYPE_DISPLAY_LIGHT;
-		p.index = 0;
-	} else {
-		p.pwm_type = EC_PWM_TYPE_GENERIC;
-		p.index = strtol(argv[1], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad pwm_idx\n");
-			return -1;
-		}
-	}
-
-	rv = ec_command(EC_CMD_PWM_GET_DUTY, 0, &p, sizeof(p), &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	printf("Current PWM duty: %d\n", r.duty);
-	return 0;
-}
-
-
-int cmd_pwm_set_duty(int argc, char *argv[])
-{
-	struct ec_params_pwm_set_duty p;
-	char *e;
-	int rv;
-
-	if (argc != 3) {
-		fprintf(stderr, "Usage: %s <pwm_idx> | kb | disp <duty>\n",
-			argv[0]);
-		return -1;
-	}
-
-	if (!strcmp(argv[1], "kb")) {
-		p.pwm_type = EC_PWM_TYPE_KB_LIGHT;
-		p.index = 0;
-	} else if (!strcmp(argv[1], "disp")) {
-		p.pwm_type = EC_PWM_TYPE_DISPLAY_LIGHT;
-		p.index = 0;
-	} else {
-		p.pwm_type = EC_PWM_TYPE_GENERIC;
-		p.index = strtol(argv[1], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad pwm_idx\n");
-			return -1;
-		}
-	}
-
-	p.duty = strtol(argv[2], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad duty.\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_PWM_SET_DUTY, 0,
-			&p, sizeof(p), NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	printf("PWM set.\n");
-	return 0;
-}
-
-int cmd_fanduty(int argc, char *argv[])
-{
-	struct ec_params_pwm_set_fan_duty_v1 p_v1;
-	char *e;
-	int rv, num_fans;
-	int cmdver = 1;
-
-	if (!ec_cmd_version_supported(EC_CMD_PWM_SET_FAN_DUTY, cmdver)) {
-		struct ec_params_pwm_set_fan_duty_v0 p_v0;
-
-		if (argc != 2) {
-			fprintf(stderr,
-				"Usage: %s <percent>\n", argv[0]);
-			return -1;
-		}
-		p_v0.percent = strtol(argv[1], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad percent arg.\n");
-			return -1;
-		}
-
-		rv = ec_command(EC_CMD_PWM_SET_FAN_DUTY, 0,
-				&p_v0, sizeof(p_v0), NULL, 0);
-		if (rv < 0)
-			return rv;
-
-		printf("Fan duty cycle set.\n");
-		return 0;
-	}
-
-	if (argc > 3 || (argc == 2 && !strcmp(argv[1], "help")) || argc == 1) {
-		printf("Usage: %s [idx] <percent>\n", argv[0]);
-		printf("'%s 0 50' - Set fan 0 duty cycle to 50 percent\n",
-			argv[0]);
-		printf("'%s 30' - Set all fans duty cycle to 30 percent\n",
-			argv[0]);
-		return -1;
-	}
-
-	num_fans = get_num_fans();
-	p_v1.percent = strtol(argv[argc - 1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad percent arg.\n");
-		return -1;
-	}
-
-	if (argc == 2) {
-		/* Reuse version 0 command if we're setting duty cycle
-		 * for all fans */
-		struct ec_params_pwm_set_fan_duty_v0 p_v0;
-
-		cmdver = 0;
-		p_v0.percent = p_v1.percent;
-
-		rv = ec_command(EC_CMD_PWM_SET_FAN_DUTY, cmdver,
-				&p_v0, sizeof(p_v0), NULL, 0);
-		if (rv < 0)
-			return rv;
-
-		printf("Fan duty cycle set for all fans.\n");
-	} else {
-		p_v1.fan_idx = strtol(argv[1], &e, 0);
-		if ((e && *e) || (p_v1.fan_idx >= num_fans)) {
-			fprintf(stderr, "Bad fan index.\n");
-			return -1;
-		}
-
-		rv = ec_command(EC_CMD_PWM_SET_FAN_DUTY, cmdver,
-				&p_v1, sizeof(p_v1), NULL, 0);
-		if (rv < 0)
-			return rv;
-
-		printf("Fan %d duty cycle set.\n", p_v1.fan_idx);
-	}
-
-	return 0;
-}
-
-#define LBMSG(state) #state
-#include "lightbar_msg_list.h"
-static const char * const lightbar_cmds[] = {
-	LIGHTBAR_MSG_LIST
-};
-#undef LBMSG
-
-/* Size of field <FLD> in structure <ST> */
-#define ST_FLD_SIZE(ST, FLD) sizeof(((struct ST *)0)->FLD)
-
-#define ST_CMD_SIZE ST_FLD_SIZE(ec_params_lightbar, cmd)
-#define ST_PRM_SIZE(SUBCMD) \
-	(ST_CMD_SIZE + ST_FLD_SIZE(ec_params_lightbar, SUBCMD))
-#define ST_RSP_SIZE(SUBCMD) ST_FLD_SIZE(ec_response_lightbar, SUBCMD)
-
-static const struct {
-	uint8_t insize;
-	uint8_t outsize;
-} lb_command_paramcount[] = {
-	{ ST_CMD_SIZE, ST_RSP_SIZE(dump) },
-	{ ST_CMD_SIZE, 0 },
-	{ ST_CMD_SIZE, 0 },
-	{ ST_CMD_SIZE, 0 },
-	{ ST_PRM_SIZE(set_brightness), 0},
-	{ ST_PRM_SIZE(seq), 0},
-	{ ST_PRM_SIZE(reg), 0},
-	{ ST_PRM_SIZE(set_rgb), 0},
-	{ ST_CMD_SIZE, ST_RSP_SIZE(get_seq) },
-	{ ST_PRM_SIZE(demo), 0},
-	{ ST_CMD_SIZE, ST_RSP_SIZE(get_params_v0) },
-	{ ST_PRM_SIZE(set_params_v0), 0},
-	{ ST_CMD_SIZE, ST_RSP_SIZE(version) },
-	{ ST_CMD_SIZE, ST_RSP_SIZE(get_brightness) },
-	{ ST_PRM_SIZE(get_rgb), ST_RSP_SIZE(get_rgb) },
-	{ ST_CMD_SIZE, ST_RSP_SIZE(get_demo) },
-	{ ST_CMD_SIZE, ST_RSP_SIZE(get_params_v1) },
-	{ ST_PRM_SIZE(set_params_v1), 0},
-	{ ST_PRM_SIZE(set_program), 0},
-	{ ST_PRM_SIZE(manual_suspend_ctrl), 0},
-	{ ST_CMD_SIZE, 0 },
-	{ ST_CMD_SIZE, 0 },
-	{ ST_CMD_SIZE, ST_RSP_SIZE(get_params_v2_timing) },
-	{ ST_PRM_SIZE(set_v2par_timing), 0},
-	{ ST_CMD_SIZE, ST_RSP_SIZE(get_params_v2_tap) },
-	{ ST_PRM_SIZE(set_v2par_tap), 0},
-	{ ST_CMD_SIZE, ST_RSP_SIZE(get_params_v2_osc) },
-	{ ST_PRM_SIZE(set_v2par_osc), 0},
-	{ ST_CMD_SIZE, ST_RSP_SIZE(get_params_v2_bright) },
-	{ ST_PRM_SIZE(set_v2par_bright), 0},
-	{ ST_CMD_SIZE, ST_RSP_SIZE(get_params_v2_thlds) },
-	{ ST_PRM_SIZE(set_v2par_thlds), 0},
-	{ ST_CMD_SIZE, ST_RSP_SIZE(get_params_v2_colors) },
-	{ ST_PRM_SIZE(set_v2par_colors), 0},
-};
-BUILD_ASSERT(ARRAY_SIZE(lb_command_paramcount) == LIGHTBAR_NUM_CMDS);
-
-#undef ST_CMD_SIZE
-#undef ST_PRM_SIZE
-#undef ST_RSP_SIZE
-
-static int lb_help(const char *cmd)
-{
-	printf("Usage:\n");
-	printf("  %s                         - dump all regs\n", cmd);
-	printf("  %s off                     - enter standby\n", cmd);
-	printf("  %s on                      - leave standby\n", cmd);
-	printf("  %s init                    - load default vals\n", cmd);
-	printf("  %s brightness [NUM]        - get/set intensity(0-ff)\n", cmd);
-	printf("  %s seq [NUM|SEQUENCE]      - run given pattern"
-		 " (no arg for list)\n", cmd);
-	printf("  %s CTRL REG VAL            - set LED controller regs\n", cmd);
-	printf("  %s LED RED GREEN BLUE      - set color manually"
-		 " (LED=4 for all)\n", cmd);
-	printf("  %s LED                     - get current LED color\n", cmd);
-	printf("  %s demo [0|1]              - turn demo mode on & off\n", cmd);
-	printf("  %s params [setfile]        - get params"
-	       " (or set from file)\n", cmd);
-	printf("  %s params2 group [setfile] - get params by group\n"
-	       " (or set from file)\n", cmd);
-	printf("  %s program file            - load program from file\n", cmd);
-	return 0;
-}
-
-static uint8_t lb_find_msg_by_name(const char *str)
-{
-	uint8_t i;
-	for (i = 0; i < LIGHTBAR_NUM_SEQUENCES; i++)
-		if (!strcasecmp(str, lightbar_cmds[i]))
-			return i;
-
-	return LIGHTBAR_NUM_SEQUENCES;
-}
-
-static int lb_do_cmd(enum lightbar_command cmd,
-		     struct ec_params_lightbar *in,
-		     struct ec_response_lightbar *out)
-{
-	int rv;
-	in->cmd = cmd;
-	rv = ec_command(EC_CMD_LIGHTBAR_CMD, 0,
-			in, lb_command_paramcount[cmd].insize,
-			out, lb_command_paramcount[cmd].outsize);
-	return (rv < 0 ? rv : 0);
-}
-
-static int lb_show_msg_names(void)
-{
-	int i, current_state;
-	struct ec_params_lightbar param;
-	struct ec_response_lightbar resp;
-
-	i = lb_do_cmd(LIGHTBAR_CMD_GET_SEQ, &param, &resp);
-	if (i < 0)
-		return i;
-	current_state = resp.get_seq.num;
-
-	printf("sequence names:");
-	for (i = 0; i < LIGHTBAR_NUM_SEQUENCES; i++)
-		printf(" %s", lightbar_cmds[i]);
-	printf("\nCurrent = 0x%x %s\n", current_state,
-	       lightbar_cmds[current_state]);
-
-	return 0;
-}
-
-static int lb_read_params_v0_from_file(const char *filename,
-				       struct lightbar_params_v0 *p)
-{
-	FILE *fp;
-	char buf[80];
-	int val[4];
-	int r = 1;
-	int line = 0;
-	int want, got;
-	int i;
-
-	fp = fopen(filename, "rb");
-	if (!fp) {
-		fprintf(stderr, "Can't open %s: %s\n",
-			filename, strerror(errno));
-		return 1;
-	}
-
-	/* We must read the correct number of params from each line */
-#define READ(N) do {							\
-		line++;							\
-		want = (N);						\
-		got = -1;						\
-		if (!fgets(buf, sizeof(buf), fp))			\
-			goto done;					\
-		got = sscanf(buf, "%i %i %i %i",			\
-			     &val[0], &val[1], &val[2], &val[3]);	\
-		if (want != got)					\
-			goto done;					\
-	} while (0)
-
-
-	/* Do it */
-	READ(1); p->google_ramp_up = val[0];
-	READ(1); p->google_ramp_down = val[0];
-	READ(1); p->s3s0_ramp_up = val[0];
-	READ(1); p->s0_tick_delay[0] = val[0];
-	READ(1); p->s0_tick_delay[1] = val[0];
-	READ(1); p->s0a_tick_delay[0] = val[0];
-	READ(1); p->s0a_tick_delay[1] = val[0];
-	READ(1); p->s0s3_ramp_down = val[0];
-	READ(1); p->s3_sleep_for = val[0];
-	READ(1); p->s3_ramp_up = val[0];
-	READ(1); p->s3_ramp_down = val[0];
-	READ(1); p->new_s0 = val[0];
-
-	READ(2);
-	p->osc_min[0] = val[0];
-	p->osc_min[1] = val[1];
-	READ(2);
-	p->osc_max[0] = val[0];
-	p->osc_max[1] = val[1];
-	READ(2);
-	p->w_ofs[0] = val[0];
-	p->w_ofs[1] = val[1];
-
-	READ(2);
-	p->bright_bl_off_fixed[0] = val[0];
-	p->bright_bl_off_fixed[1] = val[1];
-
-	READ(2);
-	p->bright_bl_on_min[0] = val[0];
-	p->bright_bl_on_min[1] = val[1];
-
-	READ(2);
-	p->bright_bl_on_max[0] = val[0];
-	p->bright_bl_on_max[1] = val[1];
-
-	READ(3);
-	p->battery_threshold[0] = val[0];
-	p->battery_threshold[1] = val[1];
-	p->battery_threshold[2] = val[2];
-
-	READ(4);
-	p->s0_idx[0][0] = val[0];
-	p->s0_idx[0][1] = val[1];
-	p->s0_idx[0][2] = val[2];
-	p->s0_idx[0][3] = val[3];
-
-	READ(4);
-	p->s0_idx[1][0] = val[0];
-	p->s0_idx[1][1] = val[1];
-	p->s0_idx[1][2] = val[2];
-	p->s0_idx[1][3] = val[3];
-
-	READ(4);
-	p->s3_idx[0][0] = val[0];
-	p->s3_idx[0][1] = val[1];
-	p->s3_idx[0][2] = val[2];
-	p->s3_idx[0][3] = val[3];
-
-	READ(4);
-	p->s3_idx[1][0] = val[0];
-	p->s3_idx[1][1] = val[1];
-	p->s3_idx[1][2] = val[2];
-	p->s3_idx[1][3] = val[3];
-
-	for (i = 0; i < ARRAY_SIZE(p->color); i++) {
-		READ(3);
-		p->color[i].r = val[0];
-		p->color[i].g = val[1];
-		p->color[i].b = val[2];
-	}
-
-#undef READ
-
-	/* Yay */
-	r = 0;
-done:
-	if (r)
-		fprintf(stderr, "problem with line %d: wanted %d, got %d\n",
-			line, want, got);
-	fclose(fp);
-	return r;
-}
-
-static void lb_show_params_v0(const struct lightbar_params_v0 *p)
-{
-	int i;
-
-	printf("%d\t\t# .google_ramp_up\n", p->google_ramp_up);
-	printf("%d\t\t# .google_ramp_down\n", p->google_ramp_down);
-	printf("%d\t\t# .s3s0_ramp_up\n", p->s3s0_ramp_up);
-	printf("%d\t\t# .s0_tick_delay (battery)\n", p->s0_tick_delay[0]);
-	printf("%d\t\t# .s0_tick_delay (AC)\n", p->s0_tick_delay[1]);
-	printf("%d\t\t# .s0a_tick_delay (battery)\n", p->s0a_tick_delay[0]);
-	printf("%d\t\t# .s0a_tick_delay (AC)\n", p->s0a_tick_delay[1]);
-	printf("%d\t\t# .s0s3_ramp_down\n", p->s0s3_ramp_down);
-	printf("%d\t# .s3_sleep_for\n", p->s3_sleep_for);
-	printf("%d\t\t# .s3_ramp_up\n", p->s3_ramp_up);
-	printf("%d\t\t# .s3_ramp_down\n", p->s3_ramp_down);
-	printf("%d\t\t# .new_s0\n", p->new_s0);
-	printf("0x%02x 0x%02x\t# .osc_min (battery, AC)\n",
-	       p->osc_min[0], p->osc_min[1]);
-	printf("0x%02x 0x%02x\t# .osc_max (battery, AC)\n",
-	       p->osc_max[0], p->osc_max[1]);
-	printf("%d %d\t\t# .w_ofs (battery, AC)\n",
-	       p->w_ofs[0], p->w_ofs[1]);
-	printf("0x%02x 0x%02x\t# .bright_bl_off_fixed (battery, AC)\n",
-	       p->bright_bl_off_fixed[0], p->bright_bl_off_fixed[1]);
-	printf("0x%02x 0x%02x\t# .bright_bl_on_min (battery, AC)\n",
-	       p->bright_bl_on_min[0], p->bright_bl_on_min[1]);
-	printf("0x%02x 0x%02x\t# .bright_bl_on_max (battery, AC)\n",
-	       p->bright_bl_on_max[0], p->bright_bl_on_max[1]);
-	printf("%d %d %d\t\t# .battery_threshold\n",
-	       p->battery_threshold[0],
-	       p->battery_threshold[1],
-	       p->battery_threshold[2]);
-	printf("%d %d %d %d\t\t# .s0_idx[] (battery)\n",
-	       p->s0_idx[0][0], p->s0_idx[0][1],
-	       p->s0_idx[0][2], p->s0_idx[0][3]);
-	printf("%d %d %d %d\t\t# .s0_idx[] (AC)\n",
-	       p->s0_idx[1][0], p->s0_idx[1][1],
-	       p->s0_idx[1][2], p->s0_idx[1][3]);
-	printf("%d %d %d %d\t# .s3_idx[] (battery)\n",
-	       p->s3_idx[0][0], p->s3_idx[0][1],
-	       p->s3_idx[0][2], p->s3_idx[0][3]);
-	printf("%d %d %d %d\t# .s3_idx[] (AC)\n",
-	       p->s3_idx[1][0], p->s3_idx[1][1],
-	       p->s3_idx[1][2], p->s3_idx[1][3]);
-	for (i = 0; i < ARRAY_SIZE(p->color); i++)
-		printf("0x%02x 0x%02x 0x%02x\t# color[%d]\n",
-		       p->color[i].r,
-		       p->color[i].g,
-		       p->color[i].b, i);
-}
-
-static int lb_read_params_v1_from_file(const char *filename,
-				       struct lightbar_params_v1 *p)
-{
-	FILE *fp;
-	char buf[80];
-	int val[4];
-	int r = 1;
-	int line = 0;
-	int want, got;
-	int i;
-
-	fp = fopen(filename, "rb");
-	if (!fp) {
-		fprintf(stderr, "Can't open %s: %s\n",
-			filename, strerror(errno));
-		return 1;
-	}
-
-	/* We must read the correct number of params from each line */
-#define READ(N) do {							\
-		line++;							\
-		want = (N);						\
-		got = -1;						\
-		if (!fgets(buf, sizeof(buf), fp))			\
-			goto done;					\
-		got = sscanf(buf, "%i %i %i %i",			\
-			     &val[0], &val[1], &val[2], &val[3]);	\
-		if (want != got)					\
-			goto done;					\
-	} while (0)
-
-
-	/* Do it */
-	READ(1); p->google_ramp_up = val[0];
-	READ(1); p->google_ramp_down = val[0];
-	READ(1); p->s3s0_ramp_up = val[0];
-	READ(1); p->s0_tick_delay[0] = val[0];
-	READ(1); p->s0_tick_delay[1] = val[0];
-	READ(1); p->s0a_tick_delay[0] = val[0];
-	READ(1); p->s0a_tick_delay[1] = val[0];
-	READ(1); p->s0s3_ramp_down = val[0];
-	READ(1); p->s3_sleep_for = val[0];
-	READ(1); p->s3_ramp_up = val[0];
-	READ(1); p->s3_ramp_down = val[0];
-	READ(1); p->tap_tick_delay = val[0];
-	READ(1); p->tap_gate_delay = val[0];
-	READ(1); p->tap_display_time = val[0];
-
-	READ(1); p->tap_pct_red = val[0];
-	READ(1); p->tap_pct_green = val[0];
-	READ(1); p->tap_seg_min_on = val[0];
-	READ(1); p->tap_seg_max_on = val[0];
-	READ(1); p->tap_seg_osc = val[0];
-	READ(3);
-	p->tap_idx[0] = val[0];
-	p->tap_idx[1] = val[1];
-	p->tap_idx[2] = val[2];
-
-	READ(2);
-	p->osc_min[0] = val[0];
-	p->osc_min[1] = val[1];
-	READ(2);
-	p->osc_max[0] = val[0];
-	p->osc_max[1] = val[1];
-	READ(2);
-	p->w_ofs[0] = val[0];
-	p->w_ofs[1] = val[1];
-
-	READ(2);
-	p->bright_bl_off_fixed[0] = val[0];
-	p->bright_bl_off_fixed[1] = val[1];
-
-	READ(2);
-	p->bright_bl_on_min[0] = val[0];
-	p->bright_bl_on_min[1] = val[1];
-
-	READ(2);
-	p->bright_bl_on_max[0] = val[0];
-	p->bright_bl_on_max[1] = val[1];
-
-	READ(3);
-	p->battery_threshold[0] = val[0];
-	p->battery_threshold[1] = val[1];
-	p->battery_threshold[2] = val[2];
-
-	READ(4);
-	p->s0_idx[0][0] = val[0];
-	p->s0_idx[0][1] = val[1];
-	p->s0_idx[0][2] = val[2];
-	p->s0_idx[0][3] = val[3];
-
-	READ(4);
-	p->s0_idx[1][0] = val[0];
-	p->s0_idx[1][1] = val[1];
-	p->s0_idx[1][2] = val[2];
-	p->s0_idx[1][3] = val[3];
-
-	READ(4);
-	p->s3_idx[0][0] = val[0];
-	p->s3_idx[0][1] = val[1];
-	p->s3_idx[0][2] = val[2];
-	p->s3_idx[0][3] = val[3];
-
-	READ(4);
-	p->s3_idx[1][0] = val[0];
-	p->s3_idx[1][1] = val[1];
-	p->s3_idx[1][2] = val[2];
-	p->s3_idx[1][3] = val[3];
-
-	for (i = 0; i < ARRAY_SIZE(p->color); i++) {
-		READ(3);
-		p->color[i].r = val[0];
-		p->color[i].g = val[1];
-		p->color[i].b = val[2];
-	}
-
-#undef READ
-
-	/* Yay */
-	r = 0;
-done:
-	if (r)
-		fprintf(stderr, "problem with line %d: wanted %d, got %d\n",
-			line, want, got);
-	fclose(fp);
-	return r;
-}
-
-static void lb_show_params_v1(const struct lightbar_params_v1 *p)
-{
-	int i;
-
-	printf("%d\t\t# .google_ramp_up\n", p->google_ramp_up);
-	printf("%d\t\t# .google_ramp_down\n", p->google_ramp_down);
-	printf("%d\t\t# .s3s0_ramp_up\n", p->s3s0_ramp_up);
-	printf("%d\t\t# .s0_tick_delay (battery)\n", p->s0_tick_delay[0]);
-	printf("%d\t\t# .s0_tick_delay (AC)\n", p->s0_tick_delay[1]);
-	printf("%d\t\t# .s0a_tick_delay (battery)\n", p->s0a_tick_delay[0]);
-	printf("%d\t\t# .s0a_tick_delay (AC)\n", p->s0a_tick_delay[1]);
-	printf("%d\t\t# .s0s3_ramp_down\n", p->s0s3_ramp_down);
-	printf("%d\t\t# .s3_sleep_for\n", p->s3_sleep_for);
-	printf("%d\t\t# .s3_ramp_up\n", p->s3_ramp_up);
-	printf("%d\t\t# .s3_ramp_down\n", p->s3_ramp_down);
-	printf("%d\t\t# .tap_tick_delay\n", p->tap_tick_delay);
-	printf("%d\t\t# .tap_gate_delay\n", p->tap_gate_delay);
-	printf("%d\t\t# .tap_display_time\n", p->tap_display_time);
-	printf("%d\t\t# .tap_pct_red\n", p->tap_pct_red);
-	printf("%d\t\t# .tap_pct_green\n", p->tap_pct_green);
-	printf("%d\t\t# .tap_seg_min_on\n", p->tap_seg_min_on);
-	printf("%d\t\t# .tap_seg_max_on\n", p->tap_seg_max_on);
-	printf("%d\t\t# .tap_seg_osc\n", p->tap_seg_osc);
-	printf("%d %d %d\t\t# .tap_idx\n",
-	       p->tap_idx[0], p->tap_idx[1], p->tap_idx[2]);
-	printf("0x%02x 0x%02x\t# .osc_min (battery, AC)\n",
-	       p->osc_min[0], p->osc_min[1]);
-	printf("0x%02x 0x%02x\t# .osc_max (battery, AC)\n",
-	       p->osc_max[0], p->osc_max[1]);
-	printf("%d %d\t\t# .w_ofs (battery, AC)\n",
-	       p->w_ofs[0], p->w_ofs[1]);
-	printf("0x%02x 0x%02x\t# .bright_bl_off_fixed (battery, AC)\n",
-	       p->bright_bl_off_fixed[0], p->bright_bl_off_fixed[1]);
-	printf("0x%02x 0x%02x\t# .bright_bl_on_min (battery, AC)\n",
-	       p->bright_bl_on_min[0], p->bright_bl_on_min[1]);
-	printf("0x%02x 0x%02x\t# .bright_bl_on_max (battery, AC)\n",
-	       p->bright_bl_on_max[0], p->bright_bl_on_max[1]);
-	printf("%d %d %d\t# .battery_threshold\n",
-	       p->battery_threshold[0],
-	       p->battery_threshold[1],
-	       p->battery_threshold[2]);
-	printf("%d %d %d %d\t\t# .s0_idx[] (battery)\n",
-	       p->s0_idx[0][0], p->s0_idx[0][1],
-	       p->s0_idx[0][2], p->s0_idx[0][3]);
-	printf("%d %d %d %d\t\t# .s0_idx[] (AC)\n",
-	       p->s0_idx[1][0], p->s0_idx[1][1],
-	       p->s0_idx[1][2], p->s0_idx[1][3]);
-	printf("%d %d %d %d\t# .s3_idx[] (battery)\n",
-	       p->s3_idx[0][0], p->s3_idx[0][1],
-	       p->s3_idx[0][2], p->s3_idx[0][3]);
-	printf("%d %d %d %d\t# .s3_idx[] (AC)\n",
-	       p->s3_idx[1][0], p->s3_idx[1][1],
-	       p->s3_idx[1][2], p->s3_idx[1][3]);
-	for (i = 0; i < ARRAY_SIZE(p->color); i++)
-		printf("0x%02x 0x%02x 0x%02x\t# color[%d]\n",
-		       p->color[i].r,
-		       p->color[i].g,
-		       p->color[i].b, i);
-}
-
-static int lb_rd_timing_v2par_from_file(const char *filename,
-					struct lightbar_params_v2_timing *p)
-{
-	FILE *fp;
-	char buf[80];
-	int val[4];
-	int r = 1;
-	int line = 0;
-	int want, got;
-
-	fp = fopen(filename, "rb");
-	if (!fp) {
-		fprintf(stderr, "Can't open %s: %s\n",
-			filename, strerror(errno));
-		return 1;
-	}
-
-	/* We must read the correct number of params from each line */
-#define READ(N) do {							\
-		line++;							\
-		want = (N);						\
-		got = -1;						\
-		if (!fgets(buf, sizeof(buf), fp))			\
-			goto done;					\
-		got = sscanf(buf, "%i %i %i %i",			\
-			     &val[0], &val[1], &val[2], &val[3]);	\
-		if (want != got)					\
-			goto done;					\
-	} while (0)
-
-	READ(1); p->google_ramp_up = val[0];
-	READ(1); p->google_ramp_down = val[0];
-	READ(1); p->s3s0_ramp_up = val[0];
-	READ(1); p->s0_tick_delay[0] = val[0];
-	READ(1); p->s0_tick_delay[1] = val[0];
-	READ(1); p->s0a_tick_delay[0] = val[0];
-	READ(1); p->s0a_tick_delay[1] = val[0];
-	READ(1); p->s0s3_ramp_down = val[0];
-	READ(1); p->s3_sleep_for = val[0];
-	READ(1); p->s3_ramp_up = val[0];
-	READ(1); p->s3_ramp_down = val[0];
-	READ(1); p->tap_tick_delay = val[0];
-	READ(1); p->tap_gate_delay = val[0];
-	READ(1); p->tap_display_time = val[0];
-#undef READ
-
-	/* Yay */
-	r = 0;
-done:
-	if (r)
-		fprintf(stderr, "problem with line %d: wanted %d, got %d\n",
-			line, want, got);
-	fclose(fp);
-	return r;
-}
-
-static int lb_rd_tap_v2par_from_file(const char *filename,
-				     struct lightbar_params_v2_tap *p)
-{
-	FILE *fp;
-	char buf[80];
-	int val[4];
-	int r = 1;
-	int line = 0;
-	int want, got;
-
-	fp = fopen(filename, "rb");
-	if (!fp) {
-		fprintf(stderr, "Can't open %s: %s\n",
-			filename, strerror(errno));
-		return 1;
-	}
-
-	/* We must read the correct number of params from each line */
-#define READ(N) do {							\
-		line++;							\
-		want = (N);						\
-		got = -1;						\
-		if (!fgets(buf, sizeof(buf), fp))			\
-			goto done;					\
-		got = sscanf(buf, "%i %i %i %i",			\
-			     &val[0], &val[1], &val[2], &val[3]);	\
-		if (want != got)					\
-			goto done;					\
-	} while (0)
-
-	READ(1); p->tap_pct_red = val[0];
-	READ(1); p->tap_pct_green = val[0];
-	READ(1); p->tap_seg_min_on = val[0];
-	READ(1); p->tap_seg_max_on = val[0];
-	READ(1); p->tap_seg_osc = val[0];
-	READ(3);
-	p->tap_idx[0] = val[0];
-	p->tap_idx[1] = val[1];
-	p->tap_idx[2] = val[2];
-#undef READ
-
-	/* Yay */
-	r = 0;
-done:
-	if (r)
-		fprintf(stderr, "problem with line %d: wanted %d, got %d\n",
-			line, want, got);
-	fclose(fp);
-	return r;
-}
-
-static int lb_rd_osc_v2par_from_file(const char *filename,
-				     struct lightbar_params_v2_oscillation *p)
-{
-	FILE *fp;
-	char buf[80];
-	int val[4];
-	int r = 1;
-	int line = 0;
-	int want, got;
-
-	fp = fopen(filename, "rb");
-	if (!fp) {
-		fprintf(stderr, "Can't open %s: %s\n",
-			filename, strerror(errno));
-		return 1;
-	}
-
-	/* We must read the correct number of params from each line */
-#define READ(N) do {							\
-		line++;							\
-		want = (N);						\
-		got = -1;						\
-		if (!fgets(buf, sizeof(buf), fp))			\
-			goto done;					\
-		got = sscanf(buf, "%i %i %i %i",			\
-			     &val[0], &val[1], &val[2], &val[3]);	\
-		if (want != got)					\
-			goto done;					\
-	} while (0)
-
-	READ(2);
-	p->osc_min[0] = val[0];
-	p->osc_min[1] = val[1];
-	READ(2);
-	p->osc_max[0] = val[0];
-	p->osc_max[1] = val[1];
-	READ(2);
-	p->w_ofs[0] = val[0];
-	p->w_ofs[1] = val[1];
-#undef READ
-
-	/* Yay */
-	r = 0;
-done:
-	if (r)
-		fprintf(stderr, "problem with line %d: wanted %d, got %d\n",
-			line, want, got);
-	fclose(fp);
-	return r;
-}
-
-static int lb_rd_bright_v2par_from_file(const char *filename,
-					struct lightbar_params_v2_brightness *p)
-{
-	FILE *fp;
-	char buf[80];
-	int val[4];
-	int r = 1;
-	int line = 0;
-	int want, got;
-
-	fp = fopen(filename, "rb");
-	if (!fp) {
-		fprintf(stderr, "Can't open %s: %s\n",
-			filename, strerror(errno));
-		return 1;
-	}
-
-	/* We must read the correct number of params from each line */
-#define READ(N) do {							\
-		line++;							\
-		want = (N);						\
-		got = -1;						\
-		if (!fgets(buf, sizeof(buf), fp))			\
-			goto done;					\
-		got = sscanf(buf, "%i %i %i %i",			\
-			     &val[0], &val[1], &val[2], &val[3]);	\
-		if (want != got)					\
-			goto done;					\
-	} while (0)
-
-	READ(2);
-	p->bright_bl_off_fixed[0] = val[0];
-	p->bright_bl_off_fixed[1] = val[1];
-
-	READ(2);
-	p->bright_bl_on_min[0] = val[0];
-	p->bright_bl_on_min[1] = val[1];
-
-	READ(2);
-	p->bright_bl_on_max[0] = val[0];
-	p->bright_bl_on_max[1] = val[1];
-#undef READ
-
-	/* Yay */
-	r = 0;
-done:
-	if (r)
-		fprintf(stderr, "problem with line %d: wanted %d, got %d\n",
-			line, want, got);
-	fclose(fp);
-	return r;
-}
-
-static int lb_rd_thlds_v2par_from_file(const char *filename,
-				       struct lightbar_params_v2_thresholds *p)
-{
-	FILE *fp;
-	char buf[80];
-	int val[4];
-	int r = 1;
-	int line = 0;
-	int want, got;
-
-	fp = fopen(filename, "rb");
-	if (!fp) {
-		fprintf(stderr, "Can't open %s: %s\n",
-			filename, strerror(errno));
-		return 1;
-	}
-
-	/* We must read the correct number of params from each line */
-#define READ(N) do {							\
-		line++;							\
-		want = (N);						\
-		got = -1;						\
-		if (!fgets(buf, sizeof(buf), fp))			\
-			goto done;					\
-		got = sscanf(buf, "%i %i %i %i",			\
-			     &val[0], &val[1], &val[2], &val[3]);	\
-		if (want != got)					\
-			goto done;					\
-	} while (0)
-
-	READ(3);
-	p->battery_threshold[0] = val[0];
-	p->battery_threshold[1] = val[1];
-	p->battery_threshold[2] = val[2];
-#undef READ
-
-	/* Yay */
-	r = 0;
-done:
-	if (r)
-		fprintf(stderr, "problem with line %d: wanted %d, got %d\n",
-			line, want, got);
-	fclose(fp);
-	return r;
-}
-
-static int lb_rd_colors_v2par_from_file(const char *filename,
-					struct lightbar_params_v2_colors *p)
-{
-	FILE *fp;
-	char buf[80];
-	int val[4];
-	int r = 1;
-	int line = 0;
-	int want, got;
-	int i;
-
-	fp = fopen(filename, "rb");
-	if (!fp) {
-		fprintf(stderr, "Can't open %s: %s\n",
-			filename, strerror(errno));
-		return 1;
-	}
-
-	/* We must read the correct number of params from each line */
-#define READ(N) do {							\
-		line++;							\
-		want = (N);						\
-		got = -1;						\
-		if (!fgets(buf, sizeof(buf), fp))			\
-			goto done;					\
-		got = sscanf(buf, "%i %i %i %i",			\
-			     &val[0], &val[1], &val[2], &val[3]);	\
-		if (want != got)					\
-			goto done;					\
-	} while (0)
-
-	READ(4);
-	p->s0_idx[0][0] = val[0];
-	p->s0_idx[0][1] = val[1];
-	p->s0_idx[0][2] = val[2];
-	p->s0_idx[0][3] = val[3];
-
-	READ(4);
-	p->s0_idx[1][0] = val[0];
-	p->s0_idx[1][1] = val[1];
-	p->s0_idx[1][2] = val[2];
-	p->s0_idx[1][3] = val[3];
-
-	READ(4);
-	p->s3_idx[0][0] = val[0];
-	p->s3_idx[0][1] = val[1];
-	p->s3_idx[0][2] = val[2];
-	p->s3_idx[0][3] = val[3];
-
-	READ(4);
-	p->s3_idx[1][0] = val[0];
-	p->s3_idx[1][1] = val[1];
-	p->s3_idx[1][2] = val[2];
-	p->s3_idx[1][3] = val[3];
-	for (i = 0; i < ARRAY_SIZE(p->color); i++) {
-		READ(3);
-		p->color[i].r = val[0];
-		p->color[i].g = val[1];
-		p->color[i].b = val[2];
-	}
-
-#undef READ
-
-	/* Yay */
-	r = 0;
-done:
-	if (r)
-		fprintf(stderr, "problem with line %d: wanted %d, got %d\n",
-			line, want, got);
-	fclose(fp);
-	return r;
-}
-
-static void lb_show_v2par_timing(const struct lightbar_params_v2_timing *p)
-{
-	printf("%d\t\t# .google_ramp_up\n", p->google_ramp_up);
-	printf("%d\t\t# .google_ramp_down\n", p->google_ramp_down);
-	printf("%d\t\t# .s3s0_ramp_up\n", p->s3s0_ramp_up);
-	printf("%d\t\t# .s0_tick_delay (battery)\n", p->s0_tick_delay[0]);
-	printf("%d\t\t# .s0_tick_delay (AC)\n", p->s0_tick_delay[1]);
-	printf("%d\t\t# .s0a_tick_delay (battery)\n", p->s0a_tick_delay[0]);
-	printf("%d\t\t# .s0a_tick_delay (AC)\n", p->s0a_tick_delay[1]);
-	printf("%d\t\t# .s0s3_ramp_down\n", p->s0s3_ramp_down);
-	printf("%d\t\t# .s3_sleep_for\n", p->s3_sleep_for);
-	printf("%d\t\t# .s3_ramp_up\n", p->s3_ramp_up);
-	printf("%d\t\t# .s3_ramp_down\n", p->s3_ramp_down);
-	printf("%d\t\t# .tap_tick_delay\n", p->tap_tick_delay);
-	printf("%d\t\t# .tap_gate_delay\n", p->tap_gate_delay);
-	printf("%d\t\t# .tap_display_time\n", p->tap_display_time);
-}
-
-static void lb_show_v2par_tap(const struct lightbar_params_v2_tap *p)
-{
-	printf("%d\t\t# .tap_pct_red\n", p->tap_pct_red);
-	printf("%d\t\t# .tap_pct_green\n", p->tap_pct_green);
-	printf("%d\t\t# .tap_seg_min_on\n", p->tap_seg_min_on);
-	printf("%d\t\t# .tap_seg_max_on\n", p->tap_seg_max_on);
-	printf("%d\t\t# .tap_seg_osc\n", p->tap_seg_osc);
-	printf("%d %d %d\t\t# .tap_idx\n",
-	       p->tap_idx[0], p->tap_idx[1], p->tap_idx[2]);
-}
-
-static void lb_show_v2par_osc(const struct lightbar_params_v2_oscillation *p)
-{
-	printf("0x%02x 0x%02x\t# .osc_min (battery, AC)\n",
-	       p->osc_min[0], p->osc_min[1]);
-	printf("0x%02x 0x%02x\t# .osc_max (battery, AC)\n",
-	       p->osc_max[0], p->osc_max[1]);
-	printf("%d %d\t\t# .w_ofs (battery, AC)\n",
-	       p->w_ofs[0], p->w_ofs[1]);
-}
-
-static void lb_show_v2par_bright(const struct lightbar_params_v2_brightness *p)
-{
-	printf("0x%02x 0x%02x\t# .bright_bl_off_fixed (battery, AC)\n",
-	       p->bright_bl_off_fixed[0], p->bright_bl_off_fixed[1]);
-	printf("0x%02x 0x%02x\t# .bright_bl_on_min (battery, AC)\n",
-	       p->bright_bl_on_min[0], p->bright_bl_on_min[1]);
-	printf("0x%02x 0x%02x\t# .bright_bl_on_max (battery, AC)\n",
-	       p->bright_bl_on_max[0], p->bright_bl_on_max[1]);
-}
-
-static void lb_show_v2par_thlds(const struct lightbar_params_v2_thresholds *p)
-{
-	printf("%d %d %d\t# .battery_threshold\n",
-	       p->battery_threshold[0],
-	       p->battery_threshold[1],
-	       p->battery_threshold[2]);
-}
-
-static void lb_show_v2par_colors(const struct lightbar_params_v2_colors *p)
-{
-	int i;
-
-	printf("%d %d %d %d\t\t# .s0_idx[] (battery)\n",
-	       p->s0_idx[0][0], p->s0_idx[0][1],
-	       p->s0_idx[0][2], p->s0_idx[0][3]);
-	printf("%d %d %d %d\t\t# .s0_idx[] (AC)\n",
-	       p->s0_idx[1][0], p->s0_idx[1][1],
-	       p->s0_idx[1][2], p->s0_idx[1][3]);
-	printf("%d %d %d %d\t# .s3_idx[] (battery)\n",
-	       p->s3_idx[0][0], p->s3_idx[0][1],
-	       p->s3_idx[0][2], p->s3_idx[0][3]);
-	printf("%d %d %d %d\t# .s3_idx[] (AC)\n",
-	       p->s3_idx[1][0], p->s3_idx[1][1],
-	       p->s3_idx[1][2], p->s3_idx[1][3]);
-
-	for (i = 0; i < ARRAY_SIZE(p->color); i++)
-		printf("0x%02x 0x%02x 0x%02x\t# color[%d]\n",
-		       p->color[i].r,
-		       p->color[i].g,
-		       p->color[i].b, i);
-}
-
-static int lb_load_program(const char *filename, struct lightbar_program *prog)
-{
-	FILE *fp;
-	size_t got;
-	int rc;
-
-	fp = fopen(filename, "rb");
-	if (!fp) {
-		fprintf(stderr, "Can't open %s: %s\n",
-			filename, strerror(errno));
-		return 1;
-	}
-
-	rc = fseek(fp, 0, SEEK_END);
-	if (rc) {
-		fprintf(stderr, "Couldn't find end of file %s",
-				filename);
-		fclose(fp);
-		return 1;
-	}
-	rc = (int) ftell(fp);
-	if (rc > EC_LB_PROG_LEN) {
-		fprintf(stderr, "File %s is too long, aborting\n", filename);
-		fclose(fp);
-		return 1;
-	}
-	rewind(fp);
-
-	memset(prog->data, 0, EC_LB_PROG_LEN);
-	got = fread(prog->data, 1, EC_LB_PROG_LEN, fp);
-	if (rc != got)
-		fprintf(stderr, "Warning: did not read entire file\n");
-	prog->size = got;
-	fclose(fp);
-	return 0;
-}
-
-static int cmd_lightbar_params_v0(int argc, char **argv)
-{
-	struct ec_params_lightbar param;
-	struct ec_response_lightbar resp;
-	int r;
-
-	if (argc > 2) {
-		r = lb_read_params_v0_from_file(argv[2],
-						&param.set_params_v0);
-		if (r)
-			return r;
-		return lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V0,
-				 &param, &resp);
-	}
-	r = lb_do_cmd(LIGHTBAR_CMD_GET_PARAMS_V0, &param, &resp);
-	if (!r)
-		lb_show_params_v0(&resp.get_params_v0);
-	return r;
-}
-
-static int cmd_lightbar_params_v1(int argc, char **argv)
-{
-	struct ec_params_lightbar param;
-	struct ec_response_lightbar resp;
-	int r;
-
-	if (argc > 2) {
-		r = lb_read_params_v1_from_file(argv[2],
-						&param.set_params_v1);
-		if (r)
-			return r;
-		return lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V1,
-				 &param, &resp);
-	}
-	r = lb_do_cmd(LIGHTBAR_CMD_GET_PARAMS_V1, &param, &resp);
-	if (!r)
-		lb_show_params_v1(&resp.get_params_v1);
-	return r;
-}
-
-static void lb_param_v2_help(void)
-{
-	printf("Usage:\n");
-	printf("lightbar params2 group [setfile]\n");
-	printf("group list:\n");
-	printf("  timing\n");
-	printf("  tap\n");
-	printf("  oscillation\n");
-	printf("  brightness\n");
-	printf("  thresholds\n");
-	printf("  colors\n");
-
-	return;
-}
-
-static int cmd_lightbar_params_v2(int argc, char **argv)
-{
-	struct ec_params_lightbar p;
-	struct ec_response_lightbar resp;
-	int r = 0;
-	int set = 0;
-
-	memset(&p, 0, sizeof(struct ec_params_lightbar));
-	memset(&resp, 0, sizeof(struct ec_response_lightbar));
-
-	if (argc < 3) {
-		lb_param_v2_help();
-		return 1;
-	}
-
-	/* Set new params if provided with a setfile */
-	if (argc > 3)
-		set = 1;
-
-	/* Show selected v2 params */
-	if (!strncasecmp(argv[2], "timing", 6)) {
-		if (set) {
-			r = lb_rd_timing_v2par_from_file(argv[3],
-							 &p.set_v2par_timing);
-			if (r)
-				return r;
-			r = lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V2_TIMING,
-				      &p, &resp);
-			if (r)
-				return r;
-		}
-		r = lb_do_cmd(LIGHTBAR_CMD_GET_PARAMS_V2_TIMING, &p, &resp);
-		if (r)
-			return r;
-		lb_show_v2par_timing(&resp.get_params_v2_timing);
-	} else if (!strcasecmp(argv[2], "tap")) {
-		if (set) {
-			r = lb_rd_tap_v2par_from_file(argv[3],
-						      &p.set_v2par_tap);
-			if (r)
-				return r;
-			r = lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V2_TAP,
-				      &p, &resp);
-			if (r)
-				return r;
-		}
-		r = lb_do_cmd(LIGHTBAR_CMD_GET_PARAMS_V2_TAP, &p, &resp);
-		if (r)
-			return r;
-		lb_show_v2par_tap(&resp.get_params_v2_tap);
-	} else if (!strncasecmp(argv[2], "oscillation", 11)) {
-		if (set) {
-			r = lb_rd_osc_v2par_from_file(argv[3],
-						      &p.set_v2par_osc);
-			if (r)
-				return r;
-			r = lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V2_OSCILLATION,
-				      &p, &resp);
-			if (r)
-				return r;
-		}
-		r = lb_do_cmd(LIGHTBAR_CMD_GET_PARAMS_V2_OSCILLATION, &p,
-			      &resp);
-		if (r)
-			return r;
-		lb_show_v2par_osc(&resp.get_params_v2_osc);
-	} else if (!strncasecmp(argv[2], "brightness", 10)) {
-		if (set) {
-			r = lb_rd_bright_v2par_from_file(argv[3],
-							 &p.set_v2par_bright);
-			if (r)
-				return r;
-			r = lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V2_BRIGHTNESS,
-				      &p, &resp);
-			if (r)
-				return r;
-		}
-		r = lb_do_cmd(LIGHTBAR_CMD_GET_PARAMS_V2_BRIGHTNESS, &p,
-			      &resp);
-		if (r)
-			return r;
-		lb_show_v2par_bright(&resp.get_params_v2_bright);
-	} else if (!strncasecmp(argv[2], "thresholds", 10)) {
-		if (set) {
-			r = lb_rd_thlds_v2par_from_file(argv[3],
-							&p.set_v2par_thlds);
-			if (r)
-				return r;
-			r = lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V2_THRESHOLDS,
-				      &p, &resp);
-			if (r)
-				return r;
-		}
-		r = lb_do_cmd(LIGHTBAR_CMD_GET_PARAMS_V2_THRESHOLDS, &p,
-			      &resp);
-		if (r)
-			return r;
-		lb_show_v2par_thlds(&resp.get_params_v2_thlds);
-	} else if (!strncasecmp(argv[2], "colors", 6)) {
-		if (set) {
-			r = lb_rd_colors_v2par_from_file(argv[3],
-							 &p.set_v2par_colors);
-			if (r)
-				return r;
-			r = lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V2_COLORS,
-				      &p, &resp);
-			if (r)
-				return r;
-		}
-		r = lb_do_cmd(LIGHTBAR_CMD_GET_PARAMS_V2_COLORS, &p, &resp);
-		if (r)
-			return r;
-		lb_show_v2par_colors(&resp.get_params_v2_colors);
-	} else {
-		lb_param_v2_help();
-	}
-
-	return r;
-}
-
-static int cmd_lightbar(int argc, char **argv)
-{
-	int i, r;
-	struct ec_params_lightbar param;
-	struct ec_response_lightbar resp;
-
-	if (1 == argc) {		/* no args = dump 'em all */
-		r = lb_do_cmd(LIGHTBAR_CMD_DUMP, &param, &resp);
-		if (r)
-			return r;
-		for (i = 0; i < ARRAY_SIZE(resp.dump.vals); i++) {
-			printf(" %02x     %02x     %02x\n",
-			       resp.dump.vals[i].reg,
-			       resp.dump.vals[i].ic0,
-			       resp.dump.vals[i].ic1);
-		}
-		return 0;
-	}
-
-	if (argc == 2 && !strcasecmp(argv[1], "init"))
-		return lb_do_cmd(LIGHTBAR_CMD_INIT, &param, &resp);
-
-	if (argc == 2 && !strcasecmp(argv[1], "off"))
-		return lb_do_cmd(LIGHTBAR_CMD_OFF, &param, &resp);
-
-	if (argc == 2 && !strcasecmp(argv[1], "on"))
-		return lb_do_cmd(LIGHTBAR_CMD_ON, &param, &resp);
-
-	if (!strcasecmp(argv[1], "params0"))
-		return cmd_lightbar_params_v0(argc, argv);
-
-	if (!strcasecmp(argv[1], "params1"))
-		return cmd_lightbar_params_v1(argc, argv);
-
-	if (!strcasecmp(argv[1], "params2"))
-		return cmd_lightbar_params_v2(argc, argv);
-
-	if (!strcasecmp(argv[1], "params")) {
-		/* Just try them both */
-		fprintf(stderr, "trying params1 ...\n");
-		if (0 == cmd_lightbar_params_v1(argc, argv))
-			return 0;
-		fprintf(stderr, "trying params0 ...\n");
-		return cmd_lightbar_params_v0(argc, argv);
-	}
-
-	if (!strcasecmp(argv[1], "version")) {
-		r = lb_do_cmd(LIGHTBAR_CMD_VERSION, &param, &resp);
-		if (!r)
-			printf("version %d flags 0x%x\n",
-			       resp.version.num, resp.version.flags);
-		return r;
-	}
-
-	if (argc > 1 && !strcasecmp(argv[1], "brightness")) {
-		char *e;
-		int rv;
-		if (argc > 2) {
-			param.set_brightness.num = 0xff &
-				strtoul(argv[2], &e, 16);
-			return lb_do_cmd(LIGHTBAR_CMD_SET_BRIGHTNESS,
-					 &param, &resp);
-		}
-		rv = lb_do_cmd(LIGHTBAR_CMD_GET_BRIGHTNESS,
-			       &param, &resp);
-		if (rv)
-			return rv;
-		printf("%02x\n", resp.get_brightness.num);
-		return 0;
-	}
-
-	if (argc > 1 && !strcasecmp(argv[1], "demo")) {
-		int rv;
-		if (argc > 2) {
-			if (!strcasecmp(argv[2], "on") || argv[2][0] == '1')
-				param.demo.num = 1;
-			else if (!strcasecmp(argv[2], "off") ||
-				 argv[2][0] == '0')
-				param.demo.num = 0;
-			else {
-				fprintf(stderr, "Invalid arg\n");
-				return -1;
-			}
-			return lb_do_cmd(LIGHTBAR_CMD_DEMO, &param, &resp);
-		}
-
-		rv = lb_do_cmd(LIGHTBAR_CMD_GET_DEMO, &param, &resp);
-		if (rv)
-			return rv;
-		printf("%s\n", resp.get_demo.num ? "on" : "off");
-		return 0;
-	}
-
-	if (argc >= 2 && !strcasecmp(argv[1], "seq")) {
-		char *e;
-		uint8_t num;
-		if (argc == 2)
-			return lb_show_msg_names();
-		num = 0xff & strtoul(argv[2], &e, 16);
-		if (e && *e)
-			num = lb_find_msg_by_name(argv[2]);
-		if (num >= LIGHTBAR_NUM_SEQUENCES) {
-			fprintf(stderr, "Invalid arg\n");
-			return -1;
-		}
-		param.seq.num = num;
-		return lb_do_cmd(LIGHTBAR_CMD_SEQ, &param, &resp);
-	}
-
-	if (argc >= 3 && !strcasecmp(argv[1], "program")) {
-		lb_load_program(argv[2], &param.set_program);
-		return lb_do_cmd(LIGHTBAR_CMD_SET_PROGRAM, &param, &resp);
-	}
-
-	if (argc == 4) {
-		char *e;
-		param.reg.ctrl = 0xff & strtoul(argv[1], &e, 16);
-		param.reg.reg = 0xff & strtoul(argv[2], &e, 16);
-		param.reg.value = 0xff & strtoul(argv[3], &e, 16);
-		return lb_do_cmd(LIGHTBAR_CMD_REG, &param, &resp);
-	}
-
-	if (argc == 5) {
-		char *e;
-		param.set_rgb.led = strtoul(argv[1], &e, 16);
-		param.set_rgb.red = strtoul(argv[2], &e, 16);
-		param.set_rgb.green = strtoul(argv[3], &e, 16);
-		param.set_rgb.blue = strtoul(argv[4], &e, 16);
-		return lb_do_cmd(LIGHTBAR_CMD_SET_RGB, &param, &resp);
-	}
-
-	/* Only thing left is to try to read an LED value */
-	if (argc == 2) {
-		char *e;
-		param.get_rgb.led = strtoul(argv[1], &e, 0);
-		if (!(e && *e)) {
-			r = lb_do_cmd(LIGHTBAR_CMD_GET_RGB, &param, &resp);
-			if (r)
-				return r;
-			printf("%02x %02x %02x\n",
-			       resp.get_rgb.red,
-			       resp.get_rgb.green,
-			       resp.get_rgb.blue);
-			return 0;
-		}
-	}
-
-	return lb_help(argv[0]);
-}
-
-/* Create an array to store sizes of motion sense param and response structs. */
-#define ST_CMD_SIZE ST_FLD_SIZE(ec_params_motion_sense, cmd)
-#define ST_PRM_SIZE(SUBCMD) \
-	(ST_CMD_SIZE + ST_FLD_SIZE(ec_params_motion_sense, SUBCMD))
-#define ST_RSP_SIZE(SUBCMD) ST_FLD_SIZE(ec_response_motion_sense, SUBCMD)
-#define ST_BOTH_SIZES(SUBCMD) { ST_PRM_SIZE(SUBCMD), ST_RSP_SIZE(SUBCMD) }
-
-/*
- * For ectool only, assume no more than 16 sensors.  More advanced
- * implementation would allocate the right amount of memory depending on the
- * number of sensors.
- */
-#define ECTOOL_MAX_SENSOR 16
-
-static const struct {
-	uint8_t outsize;
-	uint8_t insize;
-} ms_command_sizes[] = {
-	{
-		ST_PRM_SIZE(dump),
-		ST_RSP_SIZE(dump) +
-		sizeof(struct ec_response_motion_sensor_data) *
-		ECTOOL_MAX_SENSOR
-	},
-	ST_BOTH_SIZES(info_4),
-	ST_BOTH_SIZES(ec_rate),
-	ST_BOTH_SIZES(sensor_odr),
-	ST_BOTH_SIZES(sensor_range),
-	ST_BOTH_SIZES(kb_wake_angle),
-	ST_BOTH_SIZES(data),
-	{
-		ST_CMD_SIZE,
-		ST_RSP_SIZE(fifo_info) + sizeof(uint16_t) * ECTOOL_MAX_SENSOR
-	},
-	ST_BOTH_SIZES(fifo_flush),
-	ST_BOTH_SIZES(fifo_read),
-	ST_BOTH_SIZES(perform_calib),
-	ST_BOTH_SIZES(sensor_offset),
-	ST_BOTH_SIZES(list_activities),
-	{ ST_PRM_SIZE(set_activity), 0 },
-	{ ST_CMD_SIZE, ST_RSP_SIZE(lid_angle) },
-	ST_BOTH_SIZES(fifo_int_enable),
-	ST_BOTH_SIZES(spoof),
-	ST_BOTH_SIZES(tablet_mode_threshold),
-	ST_BOTH_SIZES(sensor_scale),
-	ST_BOTH_SIZES(online_calib_read),
-	ST_BOTH_SIZES(get_activity),
-};
-BUILD_ASSERT(ARRAY_SIZE(ms_command_sizes) == MOTIONSENSE_NUM_CMDS);
-
-#undef ST_CMD_SIZE
-#undef ST_PRM_SIZE
-#undef ST_RSP_SIZE
-#undef ST_BOTH_SIZES
-
-static int ms_help(const char *cmd)
-{
-	printf("Usage:\n");
-	printf("  %s                              - dump all motion data\n", cmd);
-	printf("  %s active                       - print active flag\n", cmd);
-	printf("  %s info NUM                     - print sensor info\n", cmd);
-	printf("  %s ec_rate [RATE_MS]            - set/get sample rate\n", cmd);
-	printf("  %s odr NUM [ODR [ROUNDUP]]      - set/get sensor ODR\n", cmd);
-	printf("  %s range NUM [RANGE [ROUNDUP]]  - set/get sensor range\n", cmd);
-	printf("  %s offset NUM [-- X Y Z [TEMP]] - set/get sensor offset\n", cmd);
-	printf("  %s kb_wake NUM                  - set/get KB wake ang\n", cmd);
-	printf("  %s fifo_info                    - print fifo info\n", cmd);
-	printf("  %s fifo_int_enable [0/1]        - enable/disable/get fifo interrupt "
-		"status\n", cmd);
-	printf("  %s fifo_read MAX_DATA           - read fifo data\n", cmd);
-	printf("  %s fifo_flush NUM               - trigger fifo interrupt\n", cmd);
-	printf("  %s list_activities NUM          - list supported activities\n", cmd);
-	printf("  %s set_activity NUM ACT EN      - enable/disable activity\n", cmd);
-	printf("  %s lid_angle                    - print lid angle\n", cmd);
-	printf("  %s spoof -- NUM [0/1] [X Y Z]   - enable/disable spoofing\n", cmd);
-	printf("  %s tablet_mode_angle ANG HYS    - set/get tablet mode angle\n", cmd);
-	printf("  %s calibrate NUM                - run sensor calibration\n", cmd);
-
-	return 0;
-}
-
-static void motionsense_display_activities(uint32_t activities)
-{
-	if (activities & BIT(MOTIONSENSE_ACTIVITY_SIG_MOTION))
-		printf("%d: Significant motion\n",
-		       MOTIONSENSE_ACTIVITY_SIG_MOTION);
-	if (activities & BIT(MOTIONSENSE_ACTIVITY_DOUBLE_TAP))
-		printf("%d: Double tap\n",
-		       MOTIONSENSE_ACTIVITY_DOUBLE_TAP);
-	if (activities & BIT(MOTIONSENSE_ACTIVITY_ORIENTATION))
-		printf("%d: Orientation\n",
-		       MOTIONSENSE_ACTIVITY_ORIENTATION);
-	if (activities & BIT(MOTIONSENSE_ACTIVITY_BODY_DETECTION))
-		printf("%d: Body Detection\n",
-		       MOTIONSENSE_ACTIVITY_BODY_DETECTION);
-}
-
-static int cmd_motionsense(int argc, char **argv)
-{
-	int i, rv, status_only = (argc == 2);
-	struct ec_params_motion_sense param;
-	/* The largest size using resp as a response buffer */
-	uint8_t resp_buffer[ms_command_sizes[MOTIONSENSE_CMD_DUMP].insize];
-	struct ec_response_motion_sense *resp =
-		(struct ec_response_motion_sense *)resp_buffer;
-	char *e;
-	/*
-	 * Warning: the following strings printed out are read in an
-	 * autotest. Do not change string without consulting autotest
-	 * for kernel_CrosECSysfsAccel.
-	 */
-	const char *motion_status_string[2][2] = {
-		{ "Motion sensing inactive", "0"},
-		{ "Motion sensing active", "1"},
-	};
-
-	/* No motionsense command has more than 7 args. */
-	if (argc > 7)
-		return ms_help(argv[0]);
-
-	if ((argc == 1) ||
-	    (argc == 2 && !strcasecmp(argv[1], "active"))) {
-		param.cmd = MOTIONSENSE_CMD_DUMP;
-		param.dump.max_sensor_count = ECTOOL_MAX_SENSOR;
-		rv = ec_command(
-			EC_CMD_MOTION_SENSE_CMD, 1,
-			&param, ms_command_sizes[param.cmd].outsize,
-			resp, ms_command_sizes[param.cmd].insize);
-		if (rv > 0) {
-			printf("%s\n", motion_status_string[
-					!!(resp->dump.module_flags &
-					   MOTIONSENSE_MODULE_FLAG_ACTIVE)][
-					status_only]);
-			if (status_only)
-				return 0;
-
-			if (resp->dump.sensor_count > ECTOOL_MAX_SENSOR) {
-				printf("Too many sensors to handle: %d",
-						resp->dump.sensor_count);
-				return -1;
-			}
-			for (i = 0; i < resp->dump.sensor_count; i++) {
-				/*
-				 * Warning: the following string printed out
-				 * is read by an autotest. Do not change string
-				 * without consulting autotest for
-				 * kernel_CrosECSysfsAccel.
-				 */
-				printf("Sensor %d: ", i);
-				if (resp->dump.sensor[i].flags &
-						MOTIONSENSE_SENSOR_FLAG_PRESENT)
-					printf("%d\t%d\t%d\n",
-						resp->dump.sensor[i].data[0],
-						resp->dump.sensor[i].data[1],
-						resp->dump.sensor[i].data[2]);
-				else
-					printf("None\n");
-			}
-			return 0;
-		} else {
-			return rv;
-		}
-	}
-
-	if (argc == 3 && !strcasecmp(argv[1], "info")) {
-		int version = 0;
-
-		rv = get_latest_cmd_version(EC_CMD_MOTION_SENSE_CMD, &version);
-		if (rv < 0)
-			return rv;
-
-		param.cmd = MOTIONSENSE_CMD_INFO;
-		param.sensor_odr.sensor_num = strtol(argv[2], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad %s arg.\n", argv[2]);
-			return -1;
-		}
-
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, version,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
-		if (rv < 0)
-			return rv;
-
-		printf("Type:     ");
-		switch (resp->info.type) {
-		case MOTIONSENSE_TYPE_ACCEL:
-			printf("accel\n");
-			break;
-		case MOTIONSENSE_TYPE_GYRO:
-			printf("gyro\n");
-			break;
-		case MOTIONSENSE_TYPE_MAG:
-			printf("magnetometer\n");
-			break;
-		case MOTIONSENSE_TYPE_LIGHT:
-			printf("light\n");
-			break;
-		case MOTIONSENSE_TYPE_LIGHT_RGB:
-			printf("rgb light\n");
-			break;
-		case MOTIONSENSE_TYPE_PROX:
-			printf("proximity\n");
-			break;
-		case MOTIONSENSE_TYPE_ACTIVITY:
-			printf("activity\n");
-			break;
-		case MOTIONSENSE_TYPE_BARO:
-			printf("barometer\n");
-			break;
-		case MOTIONSENSE_TYPE_SYNC:
-			printf("sync\n");
-			break;
-		default:
-			printf("unknown\n");
-		}
-
-		printf("Location: ");
-		switch (resp->info.location) {
-		case MOTIONSENSE_LOC_BASE:
-			printf("base\n");
-			break;
-		case MOTIONSENSE_LOC_LID:
-			printf("lid\n");
-			break;
-		case MOTIONSENSE_LOC_CAMERA:
-			printf("camera\n");
-			break;
-		default:
-			printf("unknown\n");
-		}
-
-		printf("Chip:     ");
-		switch (resp->info.chip) {
-		case MOTIONSENSE_CHIP_KXCJ9:
-			printf("kxcj9\n");
-			break;
-		case MOTIONSENSE_CHIP_LSM6DS0:
-			printf("lsm6ds0\n");
-			break;
-		case MOTIONSENSE_CHIP_BMI160:
-			printf("bmi160\n");
-			break;
-		case MOTIONSENSE_CHIP_SI1141:
-			printf("si1141\n");
-			break;
-		case MOTIONSENSE_CHIP_KX022:
-			printf("kx022\n");
-			break;
-		case MOTIONSENSE_CHIP_L3GD20H:
-			printf("l3gd20h\n");
-			break;
-		case MOTIONSENSE_CHIP_BMA255:
-			printf("bma255\n");
-			break;
-		case MOTIONSENSE_CHIP_BMP280:
-			printf("bmp280\n");
-			break;
-		case MOTIONSENSE_CHIP_OPT3001:
-			printf("opt3001\n");
-			break;
-		case MOTIONSENSE_CHIP_BH1730:
-			printf("bh1730\n");
-			break;
-		case MOTIONSENSE_CHIP_GPIO:
-			printf("gpio\n");
-			break;
-		case MOTIONSENSE_CHIP_LIS2DH:
-			printf("lis2dh\n");
-			break;
-		case MOTIONSENSE_CHIP_LSM6DSM:
-			printf("lsm6dsm\n");
-			break;
-		case MOTIONSENSE_CHIP_LIS2DE:
-			printf("lis2de\n");
-			break;
-		case MOTIONSENSE_CHIP_LIS2MDL:
-			printf("lis2mdl\n");
-			break;
-		case MOTIONSENSE_CHIP_LSM6DS3:
-			printf("lsm6ds3\n");
-			break;
-		case MOTIONSENSE_CHIP_LSM6DSO:
-			printf("lsm6dso\n");
-			break;
-		case MOTIONSENSE_CHIP_LNG2DM:
-			printf("lng2dm\n");
-			break;
-		case MOTIONSENSE_CHIP_TCS3400:
-			printf("tcs3400\n");
-			break;
-		case MOTIONSENSE_CHIP_LIS2DW12:
-			printf("lis2dw12\n");
-			break;
-		case MOTIONSENSE_CHIP_LIS2DWL:
-			printf("lis2dwl\n");
-			break;
-		case MOTIONSENSE_CHIP_LIS2DS:
-			printf("lis2ds\n");
-			break;
-		case MOTIONSENSE_CHIP_BMI260:
-			printf("bmi260\n");
-			break;
-		case MOTIONSENSE_CHIP_ICM426XX:
-			printf("icm426xx\n");
-			break;
-		default:
-			printf("unknown\n");
-		}
-
-		if (version >= 3) {
-			printf("Min Frequency:              %d mHz\n",
-				resp->info_3.min_frequency);
-			printf("Max Frequency:              %d mHz\n",
-				resp->info_3.max_frequency);
-			printf("FIFO Max Event Count:       %d\n",
-				resp->info_3.fifo_max_event_count);
-		}
-		if (version >= 4) {
-			printf("Flags:                      %d\n",
-			       resp->info_4.flags);
-		}
-		return 0;
-	}
-
-	if (argc < 4 && !strcasecmp(argv[1], "ec_rate")) {
-		param.cmd = MOTIONSENSE_CMD_EC_RATE;
-		param.ec_rate.data = EC_MOTION_SENSE_NO_VALUE;
-
-		if (argc == 3) {
-			param.ec_rate.data = strtol(argv[2], &e, 0);
-			if (e && *e) {
-				fprintf(stderr, "Bad %s arg.\n", argv[2]);
-				return -1;
-			}
-		}
-
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
-
-		if (rv < 0)
-			return rv;
-
-		printf("%d\n", resp->ec_rate.ret);
-		return 0;
-	}
-
-	if (argc > 2 && !strcasecmp(argv[1], "odr")) {
-		param.cmd = MOTIONSENSE_CMD_SENSOR_ODR;
-		param.sensor_odr.data = EC_MOTION_SENSE_NO_VALUE;
-		param.sensor_odr.roundup = 1;
-
-		param.sensor_odr.sensor_num = strtol(argv[2], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad %s arg.\n", argv[2]);
-			return -1;
-		}
-
-		if (argc >= 4) {
-			param.sensor_odr.data = strtol(argv[3], &e, 0);
-			if (e && *e) {
-				fprintf(stderr, "Bad %s arg.\n", argv[3]);
-				return -1;
-			}
-		}
-
-		if (argc == 5) {
-			param.sensor_odr.roundup = strtol(argv[4], &e, 0);
-			if (e && *e) {
-				fprintf(stderr, "Bad %s arg.\n", argv[4]);
-				return -1;
-			}
-		}
-
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
-
-		if (rv < 0)
-			return rv;
-
-		printf("%d\n", resp->sensor_odr.ret);
-		return 0;
-	}
-
-	if (argc > 2 && !strcasecmp(argv[1], "range")) {
-		param.cmd = MOTIONSENSE_CMD_SENSOR_RANGE;
-		param.sensor_range.data = EC_MOTION_SENSE_NO_VALUE;
-		param.sensor_range.roundup = 1;
-
-		param.sensor_range.sensor_num = strtol(argv[2], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad %s arg.\n", argv[2]);
-			return -1;
-		}
-
-		if (argc >= 4) {
-			param.sensor_range.data = strtol(argv[3], &e, 0);
-			if (e && *e) {
-				fprintf(stderr, "Bad %s arg.\n", argv[3]);
-				return -1;
-			}
-		}
-
-		if (argc == 5) {
-			param.sensor_odr.roundup = strtol(argv[4], &e, 0);
-			if (e && *e) {
-				fprintf(stderr, "Bad %s arg.\n", argv[4]);
-				return -1;
-			}
-		}
-
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
-
-		if (rv < 0)
-			return rv;
-
-		printf("%d\n", resp->sensor_range.ret);
-		return 0;
-	}
-
-	if (argc < 4 && !strcasecmp(argv[1], "kb_wake")) {
-		param.cmd = MOTIONSENSE_CMD_KB_WAKE_ANGLE;
-		param.kb_wake_angle.data = EC_MOTION_SENSE_NO_VALUE;
-
-		if (argc == 3) {
-			param.kb_wake_angle.data = strtol(argv[2], &e, 0);
-			if (e && *e) {
-				fprintf(stderr, "Bad %s arg.\n", argv[2]);
-				return -1;
-			}
-		}
-
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
-
-		if (rv < 0)
-			return rv;
-
-		printf("%d\n", resp->kb_wake_angle.ret);
-		return 0;
-	}
-
-	if (argc < 5 && !strcasecmp(argv[1], "tablet_mode_angle")) {
-		param.cmd = MOTIONSENSE_CMD_TABLET_MODE_LID_ANGLE;
-		/*
-		 * EC_MOTION_SENSE_NO_VALUE indicates to the EC that host is
-		 * attempting to only read the current values.
-		 */
-		param.tablet_mode_threshold.lid_angle =
-			EC_MOTION_SENSE_NO_VALUE;
-		param.tablet_mode_threshold.hys_degree =
-			EC_MOTION_SENSE_NO_VALUE;
-
-		if (argc == 4) {
-			param.tablet_mode_threshold.lid_angle = strtol(argv[2],
-								     &e, 0);
-
-			if (e && *e) {
-				fprintf(stderr, "Bad %s arg.\n", argv[2]);
-				return -1;
-			}
-
-			param.tablet_mode_threshold.hys_degree = strtol(argv[3],
-								     &e, 0);
-			if (e && *e) {
-				fprintf(stderr, "Bad %s arg.\n", argv[3]);
-				return -1;
-			}
-		} else if (argc != 2) {
-			return ms_help(argv[0]);
-		}
-
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
-
-		if (rv < 0)
-			return rv;
-
-		printf("tablet_mode_angle=%d hys=%d\n",
-		       resp->tablet_mode_threshold.lid_angle,
-		       resp->tablet_mode_threshold.hys_degree);
-
-		return 0;
-	}
-
-	if (argc == 2 && !strcasecmp(argv[1], "fifo_info")) {
-		int sensor_count;
-
-		param.cmd = MOTIONSENSE_CMD_DUMP;
-		param.dump.max_sensor_count = 0;
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
-		if (rv < 0)
-			return rv;
-		sensor_count = resp->dump.sensor_count;
-
-		param.cmd = MOTIONSENSE_CMD_FIFO_INFO;
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
-		if (rv < 0)
-			return rv;
-
-		printf("Size:     %d\n", resp->fifo_info.size);
-		printf("Count:    %d\n", resp->fifo_info.count);
-		printf("Timestamp:%" PRIx32 "\n", resp->fifo_info.timestamp);
-		printf("Total lost: %d\n", resp->fifo_info.total_lost);
-		for (i = 0; i < sensor_count; i++) {
-			int lost = resp->fifo_info.lost[i];
-			if (lost != 0)
-				printf("Lost %d:     %d\n", i, lost);
-		}
-		return 0;
-	}
-
-	if (argc >= 2 && !strcasecmp(argv[1], "fifo_int_enable")) {
-		param.cmd = MOTIONSENSE_CMD_FIFO_INT_ENABLE;
-		if (argc == 3)
-			param.fifo_int_enable.enable = strtol(argv[2], &e, 0);
-		else
-			param.fifo_int_enable.enable = EC_MOTION_SENSE_NO_VALUE;
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
-		if (rv < 0)
-			return rv;
-
-		printf("%d\n", resp->fifo_int_enable.ret);
-		return 0;
-	}
-
-	if (argc == 3 && !strcasecmp(argv[1], "fifo_read")) {
-		/* large number to test fragmentation */
-		struct {
-			uint32_t number_data;
-			struct ec_response_motion_sensor_data data[512];
-		} fifo_read_buffer = {
-			.number_data = -1,
-		};
-		int print_data = 0,  max_data = strtol(argv[2], &e, 0);
-
-		if (e && *e) {
-			fprintf(stderr, "Bad %s arg.\n", argv[2]);
-			return -1;
-		}
-		while (fifo_read_buffer.number_data != 0 &&
-		       print_data < max_data) {
-			struct ec_response_motion_sensor_data *vector;
-			param.cmd = MOTIONSENSE_CMD_FIFO_READ;
-			param.fifo_read.max_data_vector =
-				MIN(ARRAY_SIZE(fifo_read_buffer.data),
-				    max_data - print_data);
-
-			rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2,
-					&param,
-					ms_command_sizes[param.cmd].outsize,
-					&fifo_read_buffer, ec_max_insize);
-			if (rv < 0)
-				return rv;
-
-			print_data += fifo_read_buffer.number_data;
-			for (i = 0; i < fifo_read_buffer.number_data; i++) {
-				vector = &fifo_read_buffer.data[i];
-				if (vector->flags &
-					(MOTIONSENSE_SENSOR_FLAG_TIMESTAMP |
-					 MOTIONSENSE_SENSOR_FLAG_FLUSH)) {
-					uint32_t timestamp = 0;
-
-					memcpy(&timestamp, vector->data,
-							sizeof(uint32_t));
-					printf("Timestamp:%" PRIx32 "%s\n",
-						timestamp,
-						(vector->flags &
-						 MOTIONSENSE_SENSOR_FLAG_FLUSH ?
-						 " - Flush" : ""));
-				} else {
-					printf("Sensor %d: %d\t%d\t%d "
-					       "(as uint16: %u\t%u\t%u)\n",
-						vector->sensor_num,
-						vector->data[0],
-						vector->data[1],
-						vector->data[2],
-						vector->data[0],
-						vector->data[1],
-						vector->data[2]);
-				}
-			}
-		}
-		return 0;
-	}
-	if (argc == 3 && !strcasecmp(argv[1], "fifo_flush")) {
-		param.cmd = MOTIONSENSE_CMD_FIFO_FLUSH;
-
-		param.sensor_odr.sensor_num = strtol(argv[2], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad %s arg.\n", argv[2]);
-			return -1;
-		}
-
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
-
-		return rv < 0 ? rv : 0;
-	}
-
-	if (argc == 3 && !strcasecmp(argv[1], "calibrate")) {
-		param.cmd = MOTIONSENSE_CMD_PERFORM_CALIB;
-		param.perform_calib.enable = 1;
-		param.perform_calib.sensor_num = strtol(argv[2], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad %s arg.\n", argv[2]);
-			return -1;
-		}
-
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
-
-		if (rv < 0)
-			return rv;
-
-		printf("--- Calibrated well ---\n");
-		printf("New offset vector: X:%d, Y:%d, Z:%d\n",
-			resp->perform_calib.offset[0],
-			resp->perform_calib.offset[1],
-			resp->perform_calib.offset[2]);
-		if ((uint16_t)resp->perform_calib.temp ==
-		    EC_MOTION_SENSE_INVALID_CALIB_TEMP)
-			printf("Temperature at calibration unknown\n");
-		else
-			printf("Temperature at calibration: %d.%02d C\n",
-			       resp->perform_calib.temp / 100,
-			       resp->perform_calib.temp % 100);
-		return 0;
-	}
-
-	if (argc >= 3 && !strcasecmp(argv[1], "offset")) {
-		param.cmd = MOTIONSENSE_CMD_SENSOR_OFFSET;
-		param.sensor_offset.flags = 0;
-		param.sensor_offset.temp = EC_MOTION_SENSE_INVALID_CALIB_TEMP;
-
-		param.sensor_offset.sensor_num = strtol(argv[2], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad %s arg.\n", argv[2]);
-			return -1;
-		}
-
-		if (argc >= 4) {
-			/* Regarded as a command to set offset */
-			if (argc >= 6 && argc < 8) {
-				/* Set offset : X, Y, Z */
-				param.sensor_offset.flags = MOTION_SENSE_SET_OFFSET;
-				for (i = 0; i < 3; i++) {
-					param.sensor_offset.offset[i] = strtol(argv[3+i], &e, 0);
-					if (e && *e) {
-						fprintf(stderr, "Bad %s arg.\n", argv[3+i]);
-						return -1;
-					}
-				}
-				if (argc == 7) {
-					/* Set offset : Temperature */
-					param.sensor_offset.temp = strtol(argv[6], &e, 0);
-					if (e && *e) {
-						fprintf(stderr, "Bad %s arg.\n", argv[6]);
-						return -1;
-					}
-				}
-			} else {
-				return ms_help(argv[0]);
-			}
-		}
-
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
-
-		if (rv < 0)
-			return rv;
-
-		printf("Offset vector: X:%d, Y:%d, Z:%d\n",
-			resp->sensor_offset.offset[0],
-			resp->sensor_offset.offset[1],
-			resp->sensor_offset.offset[2]);
-		if ((uint16_t)resp->sensor_offset.temp ==
-		    EC_MOTION_SENSE_INVALID_CALIB_TEMP)
-			printf("temperature at calibration unknown\n");
-		else
-			printf("temperature at calibration: %d.%02d C\n",
-			       resp->sensor_offset.temp / 100,
-			       resp->sensor_offset.temp % 100);
-		return 0;
-	}
-
-	if (argc == 3 && !strcasecmp(argv[1], "list_activities")) {
-		param.cmd = MOTIONSENSE_CMD_LIST_ACTIVITIES;
-		param.list_activities.sensor_num = strtol(argv[2], &e, 0);
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
-		if (rv < 0)
-			return rv;
-
-		printf("Enabled:\n");
-		motionsense_display_activities(resp->list_activities.enabled);
-		printf("Disabled:\n");
-		motionsense_display_activities(resp->list_activities.disabled);
-		return 0;
-	}
-	if (argc == 5 && !strcasecmp(argv[1], "set_activity")) {
-		param.cmd = MOTIONSENSE_CMD_SET_ACTIVITY;
-		param.set_activity.sensor_num = strtol(argv[2], &e, 0);
-		param.set_activity.activity = strtol(argv[3], &e, 0);
-		param.set_activity.enable = strtol(argv[4], &e, 0);
-
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
-		if (rv < 0)
-			return rv;
-		return 0;
-	}
-	if (argc == 4 && !strcasecmp(argv[1], "get_activity")) {
-		param.cmd = MOTIONSENSE_CMD_GET_ACTIVITY;
-		param.get_activity.sensor_num = strtol(argv[2], &e, 0);
-		param.get_activity.activity = strtol(argv[3], &e, 0);
-
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
-		if (rv < 0)
-			return rv;
-		printf("State: %d\n", resp->get_activity.state);
-		return 0;
-	}
-
-	if (argc == 2 && !strcasecmp(argv[1], "lid_angle")) {
-		param.cmd = MOTIONSENSE_CMD_LID_ANGLE;
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
-		if (rv < 0)
-			return rv;
-
-		printf("Lid angle: ");
-		if (resp->lid_angle.value == LID_ANGLE_UNRELIABLE)
-			printf("unreliable\n");
-		else
-			printf("%d\n", resp->lid_angle.value);
-
-		return 0;
-	}
-
-	if (argc >= 3 && !strcasecmp(argv[1], "spoof")) {
-		param.cmd = MOTIONSENSE_CMD_SPOOF;
-		/* By default, just query the current spoof status. */
-		param.spoof.spoof_enable = MOTIONSENSE_SPOOF_MODE_QUERY;
-		param.spoof.sensor_id = strtol(argv[2], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad %s arg.\n", argv[2]);
-			return -1;
-		}
-
-		if (argc >= 4) {
-			int enable, i;
-			int16_t val;
-
-			enable = strtol(argv[3], &e, 0);
-			if ((e && *e) || (enable != 0 && enable != 1)) {
-				fprintf(stderr, "Bad %s arg.\n", argv[3]);
-				return -1;
-			}
-
-			if ((enable == 1) && (argc == 4)) {
-				/*
-				 * Enable spoofing, but lock to current sensor
-				 * values.
-				 */
-				param.spoof.spoof_enable =
-					MOTIONSENSE_SPOOF_MODE_LOCK_CURRENT;
-			} else if ((enable == 1) && (argc == 7)) {
-				/*
-				 * Enable spoofing, but use provided component
-				 * values.
-				 */
-				param.spoof.spoof_enable =
-					MOTIONSENSE_SPOOF_MODE_CUSTOM;
-				for (i = 0; i < 3; i++) {
-					val = strtol(argv[4+i], &e, 0);
-					if (e && *e) {
-						fprintf(stderr, "Bad %s arg.\n",
-							argv[4+i]);
-						return -1;
-					}
-					param.spoof.components[i] = val;
-				}
-			} else if (enable == 0) {
-				param.spoof.spoof_enable =
-					MOTIONSENSE_SPOOF_MODE_DISABLE;
-			} else {
-				return ms_help(argv[0]);
-			}
-		}
-
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
-		if (rv < 0)
-			return rv;
-
-		if (param.spoof.spoof_enable == MOTIONSENSE_SPOOF_MODE_QUERY)
-			/*
-			 * Response is the current spoof status of the
-			 * sensor.
-			 */
-			printf("Sensor %d spoof mode is %s.\n",
-			       param.spoof.sensor_id,
-			       resp->spoof.ret ? "enabled" : "disabled");
-
-		return 0;
-	}
-
-	return ms_help(argv[0]);
-}
-
-int cmd_next_event(int argc, char *argv[])
-{
-	uint8_t *rdata = (uint8_t *)ec_inbuf;
-	int rv;
-	int i;
-
-	rv = ec_command(EC_CMD_GET_NEXT_EVENT, 0,
-			NULL, 0, rdata, ec_max_insize);
-	if (rv < 0)
-		return rv;
-
-	printf("Next event is 0x%02x\n", rdata[0]);
-	if (rv > 1) {
-		printf("Event data:\n");
-		for (i = 1; i < rv; ++i) {
-			printf("%02x ", rdata[i]);
-			if (!(i & 0xf))
-				printf("\n");
-		}
-		printf("\n");
-	}
-
-	return 0;
-}
-
-static int find_led_color_by_name(const char *color)
-{
-	int i;
-
-	for (i = 0; i < EC_LED_COLOR_COUNT; ++i)
-		if (!strcasecmp(color, led_color_names[i]))
-			return i;
-
-	return -1;
-}
-
-static int find_led_id_by_name(const char *led)
-{
-	int i;
-
-	for (i = 0; i < EC_LED_ID_COUNT; ++i)
-		if (!strcasecmp(led, led_names[i]))
-			return i;
-
-	return -1;
-}
-
-int cmd_led(int argc, char *argv[])
-{
-	struct ec_params_led_control p;
-	struct ec_response_led_control r;
-	char *e, *ptr;
-	int rv, i, j;
-
-	memset(p.brightness, 0, sizeof(p.brightness));
-	p.flags = 0;
-
-	if (argc < 3) {
-		fprintf(stderr,
-			"Usage: %s <name> <query | auto | "
-			"off | <color> | <color>=<value>...>\n", argv[0]);
-		return -1;
-	}
-
-	p.led_id = find_led_id_by_name(argv[1]);
-	if (p.led_id == (uint8_t)-1) {
-		fprintf(stderr, "Bad LED name: %s\n", argv[1]);
-		fprintf(stderr, "Valid LED names: ");
-		for (i = 0; i < EC_LED_ID_COUNT; i++)
-			fprintf(stderr, "%s ", led_names[i]);
-		fprintf(stderr, "\n");
-		return -1;
-	}
-
-	if (!strcasecmp(argv[2], "query")) {
-		p.flags = EC_LED_FLAGS_QUERY;
-		rv = ec_command(EC_CMD_LED_CONTROL, 1, &p, sizeof(p),
-				&r, sizeof(r));
-		printf("Brightness range for LED %d:\n", p.led_id);
-		if (rv < 0) {
-			fprintf(stderr, "Error: Unsupported LED.\n");
-			return rv;
-		}
-		for (i = 0; i < EC_LED_COLOR_COUNT; ++i)
-			printf("\t%s\t: 0x%x\n",
-			       led_color_names[i],
-			       r.brightness_range[i]);
-		return 0;
-	}
-
-	if (!strcasecmp(argv[2], "off")) {
-		/* Brightness initialized to 0 for each color. */
-	} else if (!strcasecmp(argv[2], "auto")) {
-		p.flags = EC_LED_FLAGS_AUTO;
-	} else if ((i = find_led_color_by_name(argv[2])) != -1) {
-		p.brightness[i] = 0xff;
-	} else {
-		for (i = 2; i < argc; ++i) {
-			ptr = strtok(argv[i], "=");
-			j = find_led_color_by_name(ptr);
-			if (j == -1) {
-				fprintf(stderr, "Bad color name: %s\n", ptr);
-				fprintf(stderr, "Valid colors: ");
-				for (j = 0; j < EC_LED_COLOR_COUNT; j++)
-					fprintf(stderr, "%s ",
-						led_color_names[j]);
-				fprintf(stderr, "\n");
-				return -1;
-			}
-			ptr = strtok(NULL, "=");
-			if (ptr == NULL) {
-				fprintf(stderr, "Missing brightness value\n");
-				return -1;
-			}
-			p.brightness[j] = strtol(ptr, &e, 0);
-			if (e && *e) {
-				fprintf(stderr, "Bad brightness: %s\n", ptr);
-				return -1;
-			}
-		}
-	}
-
-	rv = ec_command(EC_CMD_LED_CONTROL, 1, &p, sizeof(p), &r, sizeof(r));
-	return (rv < 0 ? rv : 0);
-}
-
-
-int cmd_usb_charge_set_mode(int argc, char *argv[])
-{
-	struct ec_params_usb_charge_set_mode p;
-	char *e;
-	int rv;
-
-	if (argc != 3 && argc != 4) {
-		fprintf(stderr,
-			"Usage: %s <port_id> <mode_id> [<inhibit_charge>]\n",
-			argv[0]);
-		return -1;
-	}
-	p.usb_port_id = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad port ID.\n");
-		return -1;
-	}
-	p.mode = strtol(argv[2], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad mode ID.\n");
-		return -1;
-	}
-	p.inhibit_charge = 0;
-	if (argc == 4) {
-		p.inhibit_charge = strtol(argv[3], &e, 0);
-		if ((e && *e) || (p.inhibit_charge != 0 &&
-			p.inhibit_charge != 1)) {
-			fprintf(stderr, "Bad value\n");
-			return -1;
-		}
-	}
-
-	printf("Setting port %d to mode %d inhibit_charge %d...\n",
-		p.usb_port_id, p.mode, p.inhibit_charge);
-
-	rv = ec_command(EC_CMD_USB_CHARGE_SET_MODE, 0,
-			&p, sizeof(p), NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	printf("USB charging mode set.\n");
-	return 0;
-}
-
-
-int cmd_usb_mux(int argc, char *argv[])
-{
-	struct ec_params_usb_mux p;
-	char *e;
-	int rv;
-
-	if (argc != 2) {
-		fprintf(stderr, "Usage: %s <mux>\n", argv[0]);
-		return -1;
-	}
-
-	p.mux = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad mux value.\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_USB_MUX, 0,
-			&p, sizeof(p), NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	printf("Set USB mux to 0x%x.\n", p.mux);
-
-	return 0;
-}
-
-
-int cmd_usb_pd(int argc, char *argv[])
-{
-	const char *role_str[] = {"", "toggle", "toggle-off", "sink", "source",
-				  "freeze"};
-	const char *mux_str[] = {"", "none", "usb", "dp", "dock", "auto"};
-	const char *swap_str[] = {"", "dr_swap", "pr_swap", "vconn_swap"};
-	struct ec_params_usb_pd_control p;
-	struct ec_response_usb_pd_control_v2 *r_v2 =
-		(struct ec_response_usb_pd_control_v2 *)ec_inbuf;
-	struct ec_response_usb_pd_control_v1 *r_v1 =
-		(struct ec_response_usb_pd_control_v1 *)ec_inbuf;
-	struct ec_response_usb_pd_control *r =
-		(struct ec_response_usb_pd_control *)ec_inbuf;
-	int rv, i, j;
-	int option_ok;
-	char *e;
-	int cmdver;
-
-	BUILD_ASSERT(ARRAY_SIZE(role_str) == USB_PD_CTRL_ROLE_COUNT);
-	BUILD_ASSERT(ARRAY_SIZE(mux_str) == USB_PD_CTRL_MUX_COUNT);
-	BUILD_ASSERT(ARRAY_SIZE(swap_str) == USB_PD_CTRL_SWAP_COUNT);
-	p.role = USB_PD_CTRL_ROLE_NO_CHANGE;
-	p.mux = USB_PD_CTRL_MUX_NO_CHANGE;
-	p.swap = USB_PD_CTRL_SWAP_NONE;
-
-	if (argc < 2) {
-		fprintf(stderr, "No port specified.\n");
-		return -1;
-	}
-
-	p.port = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Invalid param (port)\n");
-		return -1;
-	}
-
-	for (i = 2; i < argc; ++i) {
-		option_ok = 0;
-		if (!strcmp(argv[i], "auto")) {
-			if (argc != 3) {
-				fprintf(stderr, "\"auto\" may not be used "
-						"with other options.\n");
-				return -1;
-			}
-			p.role = USB_PD_CTRL_ROLE_TOGGLE_ON;
-			p.mux = USB_PD_CTRL_MUX_AUTO;
-			continue;
-		}
-
-		for (j = 0; j < ARRAY_SIZE(role_str); ++j) {
-			if (!strcmp(argv[i], role_str[j])) {
-				if (p.role != USB_PD_CTRL_ROLE_NO_CHANGE) {
-					fprintf(stderr,
-						"Only one role allowed.\n");
-					return -1;
-				}
-				p.role = j;
-				option_ok = 1;
-				break;
-			}
-		}
-		if (option_ok)
-			continue;
-
-		for (j = 0; j < ARRAY_SIZE(mux_str); ++j) {
-			if (!strcmp(argv[i], mux_str[j])) {
-				if (p.mux != USB_PD_CTRL_MUX_NO_CHANGE) {
-					fprintf(stderr,
-						"Only one mux type allowed.\n");
-					return -1;
-				}
-				p.mux = j;
-				option_ok = 1;
-				break;
-			}
-		}
-		if (option_ok)
-			continue;
-
-		for (j = 0; j < ARRAY_SIZE(swap_str); ++j) {
-			if (!strcmp(argv[i], swap_str[j])) {
-				if (p.swap != USB_PD_CTRL_SWAP_NONE) {
-					fprintf(stderr,
-						"Only one swap type allowed.\n");
-					return -1;
-				}
-				p.swap = j;
-				option_ok = 1;
-				break;
-			}
-		}
-
-
-		if (!option_ok) {
-			fprintf(stderr, "Unknown option: %s\n", argv[i]);
-			return -1;
-		}
-	}
-
-	if (ec_cmd_version_supported(EC_CMD_USB_PD_CONTROL, 2))
-		cmdver = 2;
-	else if (ec_cmd_version_supported(EC_CMD_USB_PD_CONTROL, 1))
-		cmdver = 1;
-	else
-		cmdver = 0;
-
-	rv = ec_command(EC_CMD_USB_PD_CONTROL, cmdver, &p, sizeof(p),
-			ec_inbuf, ec_max_insize);
-
-	if (rv < 0 || argc != 2)
-		return (rv < 0) ? rv : 0;
-
-	if (cmdver == 0) {
-		printf("Port C%d is %sabled, Role:%s Polarity:CC%d State:%d\n",
-		       p.port, (r->enabled) ? "en" : "dis",
-		       r->role == PD_ROLE_SOURCE ? "SRC" : "SNK",
-		       r->polarity + 1, r->state);
-	} else {
-		printf("Port C%d: %s, %s  State:%s\n"
-		       "Role:%s %s%s, Polarity:CC%d\n",
-		       p.port,
-		       (r_v1->enabled & PD_CTRL_RESP_ENABLED_COMMS) ?
-				"enabled" : "disabled",
-		       (r_v1->enabled & PD_CTRL_RESP_ENABLED_CONNECTED) ?
-				"connected" : "disconnected",
-		       r_v1->state,
-
-		       (r_v1->role & PD_CTRL_RESP_ROLE_POWER) ? "SRC" : "SNK",
-		       (r_v1->role & PD_CTRL_RESP_ROLE_DATA) ? "DFP" : "UFP",
-		       (r_v1->role & PD_CTRL_RESP_ROLE_VCONN) ? " VCONN" : "",
-		       r_v1->polarity + 1);
-
-		if (cmdver == 2) {
-			printf("CC State:");
-			if (r_v2->cc_state == PD_CC_NONE)
-				printf("None");
-			else if (r_v2->cc_state == PD_CC_UFP_AUDIO_ACC)
-				printf("UFP Audio accessory");
-			else if (r_v2->cc_state == PD_CC_UFP_DEBUG_ACC)
-				printf("UFP Debug accessory");
-			else if (r_v2->cc_state == PD_CC_UFP_ATTACHED)
-				printf("UFP attached");
-			else if (r_v2->cc_state == PD_CC_DFP_DEBUG_ACC)
-				printf("DFP Debug accessory");
-			else if (r_v2->cc_state == PD_CC_DFP_ATTACHED)
-				printf("DFP attached");
-			else
-				printf("UNKNOWN");
-			printf("\n");
-
-			if (r_v2->dp_mode) {
-				printf("DP pin mode:");
-				if (r_v2->dp_mode == MODE_DP_PIN_A)
-					printf("A");
-				else if (r_v2->dp_mode == MODE_DP_PIN_B)
-					printf("B");
-				else if (r_v2->dp_mode == MODE_DP_PIN_C)
-					printf("C");
-				else if (r_v2->dp_mode == MODE_DP_PIN_D)
-					printf("D");
-				else if (r_v2->dp_mode == MODE_DP_PIN_E)
-					printf("E");
-				else if (r_v2->dp_mode == MODE_DP_PIN_F)
-					printf("F");
-				else
-					printf("UNKNOWN");
-				printf("\n");
-			}
-
-			printf("Cable type:%s\n",
-				r_v2->control_flags & USB_PD_CTRL_ACTIVE_CABLE ?
-					"Active" : "Passive");
-
-			printf("TBT Adapter type:%s\n",
-				r_v2->control_flags &
-				USB_PD_CTRL_TBT_LEGACY_ADAPTER ?
-					"Legacy" : "Gen3");
-
-			printf("Optical Cable:%s\n",
-				r_v2->control_flags &
-				USB_PD_CTRL_OPTICAL_CABLE ? "True" : "False");
-
-			printf("Link LSRX Communication:%s-directional\n",
-				r_v2->control_flags &
-				USB_PD_CTRL_ACTIVE_LINK_UNIDIR ? "Uni" : "Bi");
-
-			printf("TBT Cable Speed:");
-			switch (r_v2->cable_speed) {
-			case TBT_SS_U31_GEN1:
-				printf("TBT Gen1");
-				break;
-			case TBT_SS_U32_GEN1_GEN2:
-				printf("TBT Gen1 and TBT Gen2");
-				break;
-			case TBT_SS_TBT_GEN3:
-				printf("TBT Gen3");
-				break;
-			default:
-				printf("UNKNOWN");
-			}
-			printf("\n");
-
-			printf("Rounded support: 3rd Gen %srounded support\n",
-				r_v2->cable_gen ? "and 4th Gen " : "");
-		}
-		/* If connected to a PD device, then print port partner info */
-		if ((r_v1->enabled & PD_CTRL_RESP_ENABLED_CONNECTED) &&
-		    (r_v1->enabled & PD_CTRL_RESP_ENABLED_PD_CAPABLE))
-			printf("PD Partner Capabilities:\n%s%s%s%s",
-				(r_v1->role & PD_CTRL_RESP_ROLE_DR_POWER) ?
-					" DR power\n" : "",
-				(r_v1->role & PD_CTRL_RESP_ROLE_DR_DATA) ?
-					" DR data\n" : "",
-				(r_v1->role & PD_CTRL_RESP_ROLE_USB_COMM) ?
-					" USB capable\n" : "",
-				(r_v1->role & PD_CTRL_RESP_ROLE_UNCONSTRAINED) ?
-					" Unconstrained power\n" : "");
-	}
-	return 0;
-}
-
-static void print_pd_power_info(struct ec_response_usb_pd_power_info *r)
-{
-	switch (r->role) {
-	case USB_PD_PORT_POWER_DISCONNECTED:
-		printf("Disconnected");
-		break;
-	case USB_PD_PORT_POWER_SOURCE:
-		printf("SRC");
-		break;
-	case USB_PD_PORT_POWER_SINK:
-		printf("SNK");
-		break;
-	case USB_PD_PORT_POWER_SINK_NOT_CHARGING:
-		printf("SNK (not charging)");
-		break;
-	default:
-		printf("Unknown");
-	}
-
-	if ((r->role == USB_PD_PORT_POWER_SOURCE) &&
-	    (r->meas.current_max))
-		printf(" %dmA", r->meas.current_max);
-
-	if ((r->role == USB_PD_PORT_POWER_DISCONNECTED) ||
-	    (r->role == USB_PD_PORT_POWER_SOURCE)) {
-		printf("\n");
-		return;
-	}
-
-	printf(r->dualrole ? " DRP" : " Charger");
-	switch (r->type) {
-	case USB_CHG_TYPE_PD:
-		printf(" PD");
-		break;
-	case USB_CHG_TYPE_C:
-		printf(" Type-C");
-		break;
-	case USB_CHG_TYPE_PROPRIETARY:
-		printf(" Proprietary");
-		break;
-	case USB_CHG_TYPE_BC12_DCP:
-		printf(" DCP");
-		break;
-	case USB_CHG_TYPE_BC12_CDP:
-		printf(" CDP");
-		break;
-	case USB_CHG_TYPE_BC12_SDP:
-		printf(" SDP");
-		break;
-	case USB_CHG_TYPE_OTHER:
-		printf(" Other");
-		break;
-	case USB_CHG_TYPE_VBUS:
-		printf(" VBUS");
-		break;
-	case USB_CHG_TYPE_UNKNOWN:
-		printf(" Unknown");
-		break;
-	}
-	printf(" %dmV / %dmA, max %dmV / %dmA",
-		r->meas.voltage_now, r->meas.current_lim, r->meas.voltage_max,
-		r->meas.current_max);
-	if (r->max_power)
-		printf(" / %dmW", r->max_power / 1000);
-	printf("\n");
-}
-
-int cmd_usb_pd_mux_info(int argc, char *argv[])
-{
-	struct ec_params_usb_pd_mux_info p;
-	struct ec_response_usb_pd_mux_info r;
-	int num_ports, rv, i;
-
-	rv = ec_command(EC_CMD_USB_PD_PORTS, 0, NULL, 0,
-			ec_inbuf, ec_max_insize);
-	if (rv < 0)
-		return rv;
-	num_ports = ((struct ec_response_usb_pd_ports *)ec_inbuf)->num_ports;
-
-	for (i = 0; i < num_ports; i++) {
-		p.port = i;
-		rv = ec_command(EC_CMD_USB_PD_MUX_INFO, 0,
-				&p, sizeof(p),
-				&r, sizeof(r));
-		if (rv < 0)
-			return rv;
-
-		printf("Port %d: ", i);
-		printf("USB=%d ", !!(r.flags & USB_PD_MUX_USB_ENABLED));
-		printf("DP=%d ", !!(r.flags & USB_PD_MUX_DP_ENABLED));
-		printf("POLARITY=%s ", r.flags & USB_PD_MUX_POLARITY_INVERTED ?
-					"INVERTED" : "NORMAL");
-		printf("HPD_IRQ=%d ", !!(r.flags & USB_PD_MUX_HPD_IRQ));
-		printf("HPD_LVL=%d ", !!(r.flags & USB_PD_MUX_HPD_LVL));
-		printf("SAFE=%d ", !!(r.flags & USB_PD_MUX_SAFE_MODE));
-		printf("TBT=%d ", !!(r.flags & USB_PD_MUX_TBT_COMPAT_ENABLED));
-		printf("USB4=%d ", !!(r.flags & USB_PD_MUX_USB4_ENABLED));
-		printf("\n");
-	}
-
-	return 0;
-}
-
-int cmd_usb_pd_power(int argc, char *argv[])
-{
-	struct ec_params_usb_pd_power_info p;
-	struct ec_response_usb_pd_power_info *r =
-		(struct ec_response_usb_pd_power_info *)ec_inbuf;
-	int num_ports, i, rv;
-	char *e;
-
-	rv = ec_command(EC_CMD_USB_PD_PORTS, 0, NULL, 0,
-			ec_inbuf, ec_max_insize);
-	if (rv < 0)
-		return rv;
-	num_ports = ((struct ec_response_usb_pd_ports *)r)->num_ports;
-
-	if (argc < 2) {
-		for (i = 0; i < num_ports; i++) {
-			p.port = i;
-			rv = ec_command(EC_CMD_USB_PD_POWER_INFO, 0,
-					&p, sizeof(p),
-					ec_inbuf, ec_max_insize);
-			if (rv < 0)
-				return rv;
-
-			printf("Port %d: ", i);
-			print_pd_power_info(r);
-		}
-	} else {
-		p.port = strtol(argv[1], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad port.\n");
-			return -1;
-		}
-		rv = ec_command(EC_CMD_USB_PD_POWER_INFO, 0,
-				&p, sizeof(p),
-				ec_inbuf, ec_max_insize);
-		if (rv < 0)
-			return rv;
-
-		printf("Port %d: ", p.port);
-		print_pd_power_info(r);
-	}
-
-	return 0;
-}
-
-int cmd_kbpress(int argc, char *argv[])
-{
-	struct ec_params_mkbp_simulate_key p;
-	char *e;
-	int rv;
-
-	if (argc != 4) {
-		fprintf(stderr,
-			"Usage: %s <row> <col> <0|1>\n", argv[0]);
-		return -1;
-	}
-	p.row = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad row.\n");
-		return -1;
-	}
-	p.col = strtol(argv[2], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad column.\n");
-		return -1;
-	}
-	p.pressed = strtol(argv[3], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad pressed flag.\n");
-		return -1;
-	}
-
-	printf("%s row %d col %d.\n", p.pressed ? "Pressing" : "Releasing",
-				      p.row,
-				      p.col);
-
-	rv = ec_command(EC_CMD_MKBP_SIMULATE_KEY, 0,
-			&p, sizeof(p), NULL, 0);
-	if (rv < 0)
-		return rv;
-	printf("Done.\n");
-	return 0;
-}
-
-int cmd_keyboard_factory_test(int argc, char *argv[])
-{
-	struct ec_response_keyboard_factory_test r;
-	int rv;
-
-	rv = ec_command(EC_CMD_KEYBOARD_FACTORY_TEST, 0,
-			NULL, 0, &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	if (r.shorted != 0)
-		printf("Keyboard %d and %d pin are shorted.\n",
-				r.shorted & 0x00ff, r.shorted >> 8);
-	else
-		printf("Keyboard factory test passed.\n");
-
-	return 0;
-}
-
-int cmd_panic_info(int argc, char *argv[])
-{
-	int rv;
-	struct panic_data *pdata = (struct panic_data *)ec_inbuf;
-
-	rv = ec_command(EC_CMD_GET_PANIC_INFO, 0, NULL, 0,
-			ec_inbuf, ec_max_insize);
-	if (rv < 0)
-		return rv;
-
-	if (rv == 0) {
-		printf("No panic data.\n");
-		return 0;
-	}
-
-	return parse_panic_info(pdata);
-}
-
-
-int cmd_power_info(int argc, char *argv[])
-{
-	struct ec_response_power_info_v1 r;
-	int rv;
-
-	rv = ec_command(EC_CMD_POWER_INFO, 1, NULL, 0, &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	printf("Power source:\t");
-	switch (r.system_power_source) {
-	case POWER_SOURCE_UNKNOWN:
-		printf("Unknown\n");
-		break;
-	case POWER_SOURCE_BATTERY:
-		printf("Battery\n");
-		break;
-	case POWER_SOURCE_AC:
-		printf("AC\n");
-		break;
-	case POWER_SOURCE_AC_BATTERY:
-		printf("AC + battery\n");
-		break;
-	}
-
-	printf("Battery state-of-charge: %d%%\n", r.battery_soc);
-	printf("Max AC power: %d Watts\n", r.ac_adapter_100pct);
-	printf("Battery 1Cd rate: %d\n", r.battery_1cd);
-	printf("RoP Avg: %d Watts\n", r.rop_avg);
-	printf("RoP Peak: %d Watts\n", r.rop_peak);
-	printf("Battery DBPT support level: %d\n",
-	       r.intel.batt_dbpt_support_level);
-	printf("Battery DBPT Max Peak Power: %d Watts\n",
-	       r.intel.batt_dbpt_max_peak_power);
-	printf("Battery DBPT Sus Peak Power: %d Watts\n",
-	       r.intel.batt_dbpt_sus_peak_power);
-	return 0;
-}
-
-
-int cmd_pse(int argc, char *argv[])
-{
-	struct ec_params_pse p;
-	struct ec_response_pse_status r;
-	int rsize = 0;
-	char *e;
-	int rv;
-
-	if (argc < 2 || argc > 3 || !strcmp(argv[1], "help")) {
-		printf("Usage: %s <port> [<subcmd>]\n", argv[0]);
-		printf("'pse <port> [status]' - Get port status\n");
-		printf("'pse <port> disable' - Disable port\n");
-		printf("'pse <port> enable' - Enable port\n");
-		return -1;
-	}
-
-	p.port = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad port.\n");
-		return -1;
-	}
-
-	if (argc == 2 || !strcmp(argv[2], "status")) {
-		p.cmd = EC_PSE_STATUS;
-		rsize = sizeof(r);
-	} else if (!strcmp(argv[2], "disable")) {
-		p.cmd = EC_PSE_DISABLE;
-	} else if (!strcmp(argv[2], "enable")) {
-		p.cmd = EC_PSE_ENABLE;
-	} else {
-		fprintf(stderr, "Unknown command: %s\n", argv[2]);
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_PSE, 0, &p, sizeof(p), &r, rsize);
-	if (rv < 0)
-		return rv;
-
-	if (p.cmd == EC_PSE_STATUS) {
-		const char *status;
-
-		switch (r.status) {
-		case EC_PSE_STATUS_DISABLED:
-			status = "disabled";
-			break;
-		case EC_PSE_STATUS_ENABLED:
-			status = "enabled";
-			break;
-		case EC_PSE_STATUS_POWERED:
-			status = "powered";
-			break;
-		default:
-			status = "unknown";
-			break;
-		}
-
-		printf("Port %d: %s\n", p.port, status);
-	}
-
-	return 0;
-}
-
-
-int cmd_pstore_info(int argc, char *argv[])
-{
-	struct ec_response_pstore_info r;
-	int rv;
-
-	rv = ec_command(EC_CMD_PSTORE_INFO, 0, NULL, 0, &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	printf("PstoreSize %d\nAccessSize %d\n", r.pstore_size, r.access_size);
-	return 0;
-}
-
-
-int cmd_pstore_read(int argc, char *argv[])
-{
-	struct ec_params_pstore_read p;
-	uint8_t rdata[EC_PSTORE_SIZE_MAX];
-	int offset, size;
-	int rv;
-	int i;
-	char *e;
-	char *buf;
-
-	if (argc < 4) {
-		fprintf(stderr,
-			"Usage: %s <offset> <size> <filename>\n", argv[0]);
-		return -1;
-	}
-	offset = strtol(argv[1], &e, 0);
-	if ((e && *e) || offset < 0 || offset > 0x10000) {
-		fprintf(stderr, "Bad offset.\n");
-		return -1;
-	}
-	size = strtol(argv[2], &e, 0);
-	if ((e && *e) || size <= 0 || size > 0x10000) {
-		fprintf(stderr, "Bad size.\n");
-		return -1;
-	}
-	printf("Reading %d bytes at offset %d...\n", size, offset);
-
-	buf = (char *)malloc(size);
-	if (!buf) {
-		fprintf(stderr, "Unable to allocate buffer.\n");
-		return -1;
-	}
-
-	/* Read data in chunks */
-	for (i = 0; i < size; i += EC_PSTORE_SIZE_MAX) {
-		p.offset = offset + i;
-		p.size = MIN(size - i, EC_PSTORE_SIZE_MAX);
-		rv = ec_command(EC_CMD_PSTORE_READ, 0,
-				&p, sizeof(p), rdata, sizeof(rdata));
-		if (rv < 0) {
-			fprintf(stderr, "Read error at offset %d\n", i);
-			free(buf);
-			return rv;
-		}
-		memcpy(buf + i, rdata, p.size);
-	}
-
-	rv = write_file(argv[3], buf, size);
-	free(buf);
-	if (rv)
-		return rv;
-
-	printf("done.\n");
-	return 0;
-}
-
-
-int cmd_pstore_write(int argc, char *argv[])
-{
-	struct ec_params_pstore_write p;
-	int offset, size;
-	int rv;
-	int i;
-	char *e;
-	char *buf;
-
-	if (argc < 3) {
-		fprintf(stderr, "Usage: %s <offset> <filename>\n", argv[0]);
-		return -1;
-	}
-	offset = strtol(argv[1], &e, 0);
-	if ((e && *e) || offset < 0 || offset > 0x10000) {
-		fprintf(stderr, "Bad offset.\n");
-		return -1;
-	}
-
-	/* Read the input file */
-	buf = read_file(argv[2], &size);
-	if (!buf)
-		return -1;
-
-	printf("Writing to offset %d...\n", offset);
-
-	/* Write data in chunks */
-	for (i = 0; i < size; i += EC_PSTORE_SIZE_MAX) {
-		p.offset = offset + i;
-		p.size = MIN(size - i, EC_PSTORE_SIZE_MAX);
-		memcpy(p.data, buf + i, p.size);
-		rv = ec_command(EC_CMD_PSTORE_WRITE, 0,
-				&p, sizeof(p), NULL, 0);
-		if (rv < 0) {
-			fprintf(stderr, "Write error at offset %d\n", i);
-			free(buf);
-			return rv;
-		}
-	}
-
-	free(buf);
-	printf("done.\n");
-	return 0;
-}
-
-
-int cmd_host_event_get_raw(int argc, char *argv[])
-{
-	uint32_t events = read_mapped_mem32(EC_MEMMAP_HOST_EVENTS);
-
-	if (events & EC_HOST_EVENT_MASK(EC_HOST_EVENT_INVALID)) {
-		printf("Current host events: invalid\n");
-		return -1;
-	}
-
-	printf("Current host events: 0x%08x\n", events);
-	return 0;
-}
-
-
-int cmd_host_event_get_b(int argc, char *argv[])
-{
-	struct ec_response_host_event_mask r;
-	int rv;
-
-	rv = ec_command(EC_CMD_HOST_EVENT_GET_B, 0,
-			NULL, 0, &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-	if (rv < sizeof(r)) {
-		fprintf(stderr, "Insufficient data received.\n");
-		return -1;
-	}
-
-	if (r.mask & EC_HOST_EVENT_MASK(EC_HOST_EVENT_INVALID)) {
-		printf("Current host events-B: invalid\n");
-		return -1;
-	}
-
-	printf("Current host events-B: 0x%08x\n", r.mask);
-	return 0;
-}
-
-
-int cmd_host_event_get_smi_mask(int argc, char *argv[])
-{
-	struct ec_response_host_event_mask r;
-	int rv;
-
-	rv = ec_command(EC_CMD_HOST_EVENT_GET_SMI_MASK, 0,
-			NULL, 0, &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	printf("Current host event SMI mask: 0x%08x\n", r.mask);
-	return 0;
-}
-
-
-int cmd_host_event_get_sci_mask(int argc, char *argv[])
-{
-	struct ec_response_host_event_mask r;
-	int rv;
-
-	rv = ec_command(EC_CMD_HOST_EVENT_GET_SCI_MASK, 0,
-			NULL, 0, &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	printf("Current host event SCI mask: 0x%08x\n", r.mask);
-	return 0;
-}
-
-
-int cmd_host_event_get_wake_mask(int argc, char *argv[])
-{
-	struct ec_response_host_event_mask r;
-	int rv;
-
-	rv = ec_command(EC_CMD_HOST_EVENT_GET_WAKE_MASK, 0,
-			NULL, 0, &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	printf("Current host event wake mask: 0x%08x\n", r.mask);
-	return 0;
-}
-
-
-int cmd_host_event_set_smi_mask(int argc, char *argv[])
-{
-	struct ec_params_host_event_mask p;
-	char *e;
-	int rv;
-
-	if (argc != 2) {
-		fprintf(stderr, "Usage: %s <mask>\n", argv[0]);
-		return -1;
-	}
-	p.mask = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad mask.\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_HOST_EVENT_SET_SMI_MASK, 0,
-			&p, sizeof(p), NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	printf("Mask set.\n");
-	return 0;
-}
-
-
-int cmd_host_event_set_sci_mask(int argc, char *argv[])
-{
-	struct ec_params_host_event_mask p;
-	char *e;
-	int rv;
-
-	if (argc != 2) {
-		fprintf(stderr, "Usage: %s <mask>\n", argv[0]);
-		return -1;
-	}
-	p.mask = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad mask.\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_HOST_EVENT_SET_SCI_MASK, 0,
-			&p, sizeof(p), NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	printf("Mask set.\n");
-	return 0;
-}
-
-
-int cmd_host_event_set_wake_mask(int argc, char *argv[])
-{
-	struct ec_params_host_event_mask p;
-	char *e;
-	int rv;
-
-	if (argc != 2) {
-		fprintf(stderr, "Usage: %s <mask>\n", argv[0]);
-		return -1;
-	}
-	p.mask = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad mask.\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_HOST_EVENT_SET_WAKE_MASK, 0,
-			&p, sizeof(p), NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	printf("Mask set.\n");
-	return 0;
-}
-
-
-int cmd_host_event_clear(int argc, char *argv[])
-{
-	struct ec_params_host_event_mask p;
-	char *e;
-	int rv;
-
-	if (argc != 2) {
-		fprintf(stderr, "Usage: %s <mask>\n", argv[0]);
-		return -1;
-	}
-	p.mask = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad mask.\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_HOST_EVENT_CLEAR, 0,
-			&p, sizeof(p), NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	printf("Host events cleared.\n");
-	return 0;
-}
-
-
-int cmd_host_event_clear_b(int argc, char *argv[])
-{
-	struct ec_params_host_event_mask p;
-	char *e;
-	int rv;
-
-	if (argc != 2) {
-		fprintf(stderr, "Usage: %s <mask>\n", argv[0]);
-		return -1;
-	}
-	p.mask = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad mask.\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_HOST_EVENT_CLEAR_B, 0,
-			&p, sizeof(p), NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	printf("Host events-B cleared.\n");
-	return 0;
-}
-
-
-int cmd_switches(int argc, char *argv[])
-{
-	uint8_t s = read_mapped_mem8(EC_MEMMAP_SWITCHES);
-	printf("Current switches:   0x%02x\n", s);
-	printf("Lid switch:         %s\n",
-	       (s & EC_SWITCH_LID_OPEN ? "OPEN" : "CLOSED"));
-	printf("Power button:       %s\n",
-	       (s & EC_SWITCH_POWER_BUTTON_PRESSED ? "DOWN" : "UP"));
-	printf("Write protect:      %sABLED\n",
-	       (s & EC_SWITCH_WRITE_PROTECT_DISABLED ? "DIS" : "EN"));
-	printf("Dedicated recovery: %sABLED\n",
-	       (s & EC_SWITCH_DEDICATED_RECOVERY ? "EN" : "DIS"));
-
-	return 0;
-}
-
-
-int cmd_wireless(int argc, char *argv[])
-{
-	char *e;
-	int rv;
-	int now_flags;
-
-	if (argc < 2) {
-		fprintf(stderr,
-			"Usage: %s <flags> [<mask> [<susflags> <susmask>]]\n",
-			argv[0]);
-		fprintf(stderr, "  0x1 = WLAN radio\n"
-				"  0x2 = Bluetooth radio\n"
-				"  0x4 = WWAN power\n"
-				"  0x8 = WLAN power\n");
-		return -1;
-	}
-
-	now_flags = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad flags.\n");
-		return -1;
-	}
-
-	if (argc < 3) {
-		/* Old-style - current flags only */
-		struct ec_params_switch_enable_wireless_v0 p;
-
-		p.enabled = now_flags;
-		rv = ec_command(EC_CMD_SWITCH_ENABLE_WIRELESS, 0,
-				&p, sizeof(p), NULL, 0);
-		if (rv < 0)
-			return rv;
-
-		printf("Success.\n");
-	} else {
-		/* New-style - masks and suspend flags */
-		struct ec_params_switch_enable_wireless_v1 p;
-		struct ec_response_switch_enable_wireless_v1 r;
-
-		memset(&p, 0, sizeof(p));
-
-		p.now_flags = now_flags;
-
-		p.now_mask = strtol(argv[2], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad mask.\n");
-			return -1;
-		}
-
-		if (argc > 4) {
-			p.suspend_flags = strtol(argv[3], &e, 0);
-			if (e && *e) {
-				fprintf(stderr, "Bad suspend flags.\n");
-				return -1;
-			}
-
-			p.suspend_mask = strtol(argv[4], &e, 0);
-			if (e && *e) {
-				fprintf(stderr, "Bad suspend mask.\n");
-				return -1;
-			}
-		}
-
-		rv = ec_command(EC_CMD_SWITCH_ENABLE_WIRELESS,
-				EC_VER_SWITCH_ENABLE_WIRELESS,
-				&p, sizeof(p), &r, sizeof(r));
-		if (rv < 0)
-			return rv;
-
-		printf("Now=0x%x, suspend=0x%x\n",
-		       r.now_flags, r.suspend_flags);
-	}
-
-	return 0;
-}
-
-
-int cmd_i2c_protect(int argc, char *argv[])
-{
-	struct ec_params_i2c_passthru_protect p;
-	char *e;
-	int rv;
-
-	if (argc != 2 && (argc != 3 || strcmp(argv[2], "status"))) {
-		fprintf(stderr, "Usage: %s <port> [status]\n",
-				argv[0]);
-		return -1;
-	}
-
-	p.port = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad port.\n");
-		return -1;
-	}
-
-	if (argc == 3) {
-		struct ec_response_i2c_passthru_protect r;
-
-		p.subcmd = EC_CMD_I2C_PASSTHRU_PROTECT_STATUS;
-
-		rv = ec_command(EC_CMD_I2C_PASSTHRU_PROTECT, 0, &p, sizeof(p),
-				&r, sizeof(r));
-
-		if (rv < 0)
-			return rv;
-
-		printf("I2C port %d: %s (%d)\n", p.port,
-			r.status ? "Protected" : "Unprotected", r.status);
-	} else {
-		p.subcmd = EC_CMD_I2C_PASSTHRU_PROTECT_ENABLE;
-
-		rv = ec_command(EC_CMD_I2C_PASSTHRU_PROTECT, 0, &p, sizeof(p),
-				NULL, 0);
-
-		if (rv < 0)
-			return rv;
-	}
-	return 0;
-}
-
-
-int do_i2c_xfer(unsigned int port, unsigned int addr,
-		uint8_t *write_buf, int write_len,
-		uint8_t **read_buf, int read_len) {
-	struct ec_params_i2c_passthru *p =
-		(struct ec_params_i2c_passthru *)ec_outbuf;
-	struct ec_response_i2c_passthru *r =
-		(struct ec_response_i2c_passthru *)ec_inbuf;
-	struct ec_params_i2c_passthru_msg *msg = p->msg;
-	uint8_t *pdata;
-	int size;
-	int rv;
-
-	p->port = port;
-	p->num_msgs = (read_len != 0) + (write_len != 0);
-
-	size = sizeof(*p) + p->num_msgs * sizeof(*msg);
-	if (size + write_len > ec_max_outsize) {
-		fprintf(stderr, "Params too large for buffer\n");
-		return -1;
-	}
-	if (sizeof(*r) + read_len > ec_max_insize) {
-		fprintf(stderr, "Read length too big for buffer\n");
-		return -1;
-	}
-
-	pdata = (uint8_t *)p + size;
-	if (write_len) {
-		msg->addr_flags = addr;
-		msg->len = write_len;
-
-		memcpy(pdata, write_buf, write_len);
-		msg++;
-	}
-
-	if (read_len) {
-		msg->addr_flags = addr | EC_I2C_FLAG_READ;
-		msg->len = read_len;
-	}
-
-	rv = ec_command(EC_CMD_I2C_PASSTHRU, 0, p, size + write_len,
-			r, sizeof(*r) + read_len);
-	if (rv < 0)
-		return rv;
-
-	/* Parse response */
-	if (r->i2c_status & (EC_I2C_STATUS_NAK | EC_I2C_STATUS_TIMEOUT)) {
-		fprintf(stderr, "Transfer failed with status=0x%x\n",
-			r->i2c_status);
-		return -1;
-	}
-
-	if (rv < sizeof(*r) + read_len) {
-		fprintf(stderr, "Truncated read response\n");
-		return -1;
-	}
-
-	if (read_len)
-		*read_buf = r->data;
-
-	return 0;
-}
-
-static void cmd_i2c_help(void)
-{
-	fprintf(stderr,
-	"  Usage: i2cread <8 | 16> <port> <addr8> <offset>\n"
-	"  Usage: i2cwrite <8 | 16> <port> <addr8> <offset> <data>\n"
-	"  Usage: i2cxfer <port> <addr7> <read_count> [bytes...]\n"
-	"    <port> i2c port number\n"
-	"    <addr8> 8-bit i2c address\n"
-	"    <addr7> 7-bit i2c address\n"
-	"    <offset> offset to read from or write to\n"
-	"    <data> data to write\n"
-	"    <read_count> number of bytes to read\n"
-	"    [bytes ...] data to write\n"
-	);
-
-}
-
-int cmd_i2c_read(int argc, char *argv[])
-{
-	unsigned int port, addr;
-	int read_len, write_len;
-	uint8_t write_buf[1];
-	uint8_t *read_buf = NULL;
-	char *e;
-	int rv;
-
-	if (argc != 5) {
-		cmd_i2c_help();
-		return -1;
-	}
-
-	read_len = strtol(argv[1], &e, 0);
-	if ((e && *e) || (read_len != 8 && read_len != 16)) {
-		fprintf(stderr, "Bad read size.\n");
-		return -1;
-	}
-	read_len = read_len / 8;
-
-	port = strtol(argv[2], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad port.\n");
-		return -1;
-	}
-
-	addr = strtol(argv[3], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad address.\n");
-		return -1;
-	}
-	/* Convert from 8-bit to 7-bit address */
-	addr = addr >> 1;
-
-	write_buf[0] = strtol(argv[4], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad offset.\n");
-		return -1;
-	}
-	write_len = 1;
-
-	rv = do_i2c_xfer(port, addr, write_buf, write_len, &read_buf, read_len);
-
-	if (rv < 0)
-		return rv;
-
-	printf("Read from I2C port %d at 0x%x offset 0x%x = 0x%x\n",
-		port, addr, write_buf[0], *(uint16_t *)read_buf);
-	return 0;
-}
-
-
-int cmd_i2c_write(int argc, char *argv[])
-{
-	unsigned int port, addr;
-	int write_len;
-	uint8_t write_buf[3];
-	char *e;
-	int rv;
-
-	if (argc != 6) {
-		cmd_i2c_help();
-		return -1;
-	}
-
-	write_len = strtol(argv[1], &e, 0);
-	if ((e && *e) || (write_len != 8 && write_len != 16)) {
-		fprintf(stderr, "Bad write size.\n");
-		return -1;
-	}
-	/* Include offset (length 1) */
-	write_len = 1 + write_len / 8;
-
-	port = strtol(argv[2], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad port.\n");
-		return -1;
-	}
-
-	addr = strtol(argv[3], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad address.\n");
-		return -1;
-	}
-	/* Convert from 8-bit to 7-bit address */
-	addr = addr >> 1;
-
-	write_buf[0] = strtol(argv[4], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad offset.\n");
-		return -1;
-	}
-
-	*((uint16_t *)&write_buf[1]) = strtol(argv[5], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad data.\n");
-		return -1;
-	}
-
-	rv = do_i2c_xfer(port, addr, write_buf, write_len, NULL, 0);
-
-	if (rv < 0)
-		return rv;
-
-	printf("Wrote 0x%x to I2C port %d at 0x%x offset 0x%x.\n",
-	       *((uint16_t *)&write_buf[1]), port, addr, write_buf[0]);
-	return 0;
-}
-
-int cmd_i2c_xfer(int argc, char *argv[])
-{
-	unsigned int port, addr;
-	int read_len, write_len;
-	uint8_t *write_buf = NULL;
-	uint8_t *read_buf;
-	char *e;
-	int rv, i;
-
-	if (argc < 4) {
-		cmd_i2c_help();
-		return -1;
-	}
-
-	port = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad port.\n");
-		return -1;
-	}
-
-	addr = strtol(argv[2], &e, 0) & 0x7f;
-	if (e && *e) {
-		fprintf(stderr, "Bad slave address.\n");
-		return -1;
-	}
-
-	read_len = strtol(argv[3], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad read length.\n");
-		return -1;
-	}
-
-	/* Skip over params to bytes to write */
-	argc -= 4;
-	argv += 4;
-	write_len = argc;
-
-	if (write_len) {
-		write_buf = malloc(write_len);
-		if (write_buf == NULL)
-			return -1;
-		for (i = 0; i < write_len; i++) {
-			write_buf[i] = strtol(argv[i], &e, 0);
-			if (e && *e) {
-				fprintf(stderr, "Bad write byte %d\n", i);
-				free(write_buf);
-				return -1;
-			}
-		}
-	}
-
-	rv = do_i2c_xfer(port, addr, write_buf, write_len, &read_buf, read_len);
-
-	if (write_len)
-		free(write_buf);
-
-	if (rv)
-		return rv;
-
-	if (read_len) {
-		if (ascii_mode) {
-			for (i = 0; i < read_len; i++)
-				printf(isprint(read_buf[i]) ? "%c" : "\\x%02x",
-				       read_buf[i]);
-		} else {
-			printf("Read bytes:");
-			for (i = 0; i < read_len; i++)
-				printf(" %#02x", read_buf[i]);
-		}
-		printf("\n");
-	} else {
-		printf("Write successful.\n");
-	}
-
-	return 0;
-}
-
-static void cmd_locate_chip_help(const char *const cmd)
-{
-	fprintf(stderr,
-		"Usage: %s <type> <index>\n"
-		"  <type> is one of:\n"
-		"    0: CBI_EEPROM\n"
-		"    1: TCPCs\n"
-		"  <index> instance # of <type>\n",
-		cmd);
-}
-
-static const char *bus_type[] = {
-	"I2C",
-	"EMBEDDED"
-};
-
-int cmd_locate_chip(int argc, char *argv[])
-{
-	struct ec_params_locate_chip p;
-	struct ec_response_locate_chip r = {0};
-	char *e;
-	int rv;
-
-	if (argc != 3) {
-		cmd_locate_chip_help(argv[0]);
-		return -1;
-	}
-
-	p.type = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad type.\n");
-		cmd_locate_chip_help(argv[0]);
-		return -1;
-	}
-
-	p.index = strtol(argv[2], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad index.\n");
-		cmd_locate_chip_help(argv[0]);
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_LOCATE_CHIP, 0, &p, sizeof(p), &r, sizeof(r));
-
-	if (rv == -EC_RES_INVALID_PARAM - EECRESULT) {
-		fprintf(stderr, "Bus type %d not supported.\n", p.type);
-		return rv;
-	}
-
-	if (rv == -EC_RES_UNAVAILABLE - EECRESULT) {
-		fprintf(stderr, "Chip not found\n");
-		return rv;
-	}
-
-	if (rv == -EC_RES_OVERFLOW - EECRESULT) {
-		fprintf(stderr, "Index too large\n");
-		return rv;
-	}
-
-	if (rv < 0)
-		return rv;
-
-	if (r.bus_type >= EC_BUS_TYPE_COUNT
-			|| r.bus_type >= ARRAY_SIZE(bus_type)) {
-		fprintf(stderr, "Unknown bus type (%d)\n", r.bus_type);
-		return -1;
-	}
-
-	/*
-	 * When changing the format of this print, make sure FAFT
-	 * (firmware_ECCbiEeprom) still passes. It may silently skip the test.
-	 */
-	printf("Bus: %s; Port: %d; Address: 0x%02x (7-bit format)\n",
-	       bus_type[r.bus_type], r.i2c_info.port,
-	       I2C_GET_ADDR(r.i2c_info.addr_flags));
-
-	printf("reserved: 0x%x\n", r.reserved);
-
-	return 0;
-}
-
-int cmd_lcd_backlight(int argc, char *argv[])
-{
-	struct ec_params_switch_enable_backlight p;
-	char *e;
-	int rv;
-
-	if (argc != 2) {
-		fprintf(stderr, "Usage: %s <0|1>\n", argv[0]);
-		return -1;
-	}
-	p.enabled = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad value.\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_SWITCH_ENABLE_BKLIGHT, 0,
-			&p, sizeof(p), NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	printf("Success.\n");
-	return 0;
-}
-
-
-int cmd_ext_power_limit(int argc, char *argv[])
-{
-	/* Version 1 is used, no support for obsolete version 0 */
-	struct ec_params_external_power_limit_v1 p;
-	char *e;
-
-	if (argc != 3) {
-		fprintf(stderr,
-			"Usage: %s <max_current_mA> <max_voltage_mV>\n",
-			argv[0]);
-		return -1;
-	}
-
-	p.current_lim = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad param1.\n");
-		return -1;
-	}
-
-	p.voltage_lim = strtol(argv[2], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad param2.\n");
-		return -1;
-	}
-
-	/* Send version 1 of command */
-	return ec_command(EC_CMD_EXTERNAL_POWER_LIMIT, 1, &p, sizeof(p),
-			  NULL, 0);
-}
-
-
-int cmd_charge_current_limit(int argc, char *argv[])
-{
-	struct ec_params_current_limit p;
-	int rv;
-	char *e;
-
-	if (argc != 2) {
-		fprintf(stderr, "Usage: %s <max_current_mA>\n", argv[0]);
-		return -1;
-	}
-
-	p.limit = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad value.\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_CHARGE_CURRENT_LIMIT, 0, &p, sizeof(p),
-			NULL, 0);
-	return rv;
-}
-
-
-int cmd_charge_control(int argc, char *argv[])
-{
-	struct ec_params_charge_control p;
-	int rv;
-
-	if (argc != 2) {
-		fprintf(stderr, "Usage: %s <normal | idle | discharge>\n",
-			argv[0]);
-		return -1;
-	}
-
-	if (!strcasecmp(argv[1], "normal")) {
-		p.mode = CHARGE_CONTROL_NORMAL;
-	} else if (!strcasecmp(argv[1], "idle")) {
-		p.mode = CHARGE_CONTROL_IDLE;
-	} else if (!strcasecmp(argv[1], "discharge")) {
-		p.mode = CHARGE_CONTROL_DISCHARGE;
-	} else {
-		fprintf(stderr, "Bad value.\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_CHARGE_CONTROL, 1, &p, sizeof(p), NULL, 0);
-	if (rv < 0) {
-		fprintf(stderr, "Is AC connected?\n");
-		return rv;
-	}
-
-	switch (p.mode) {
-	case CHARGE_CONTROL_NORMAL:
-		printf("Charge state machine normal mode.\n");
-		break;
-	case CHARGE_CONTROL_IDLE:
-		printf("Charge state machine force idle.\n");
-		break;
-	case CHARGE_CONTROL_DISCHARGE:
-		printf("Charge state machine force discharge.\n");
-		break;
-	default:
-		break;
-	}
-	return 0;
-}
-
-
-#define ST_CMD_SIZE ST_FLD_SIZE(ec_params_charge_state, cmd)
-#define ST_PRM_SIZE(SUBCMD) \
-	(ST_CMD_SIZE + ST_FLD_SIZE(ec_params_charge_state, SUBCMD))
-#define ST_RSP_SIZE(SUBCMD) ST_FLD_SIZE(ec_response_charge_state, SUBCMD)
-
-/* Table of subcommand sizes for EC_CMD_CHARGE_STATE */
-static const struct {
-	uint8_t to_ec_size;
-	uint8_t from_ec_size;
-} cs_paramcount[] = {
-	/* Order must match enum charge_state_command */
-	{ ST_CMD_SIZE, ST_RSP_SIZE(get_state) },
-	{ ST_PRM_SIZE(get_param), ST_RSP_SIZE(get_param) },
-	{ ST_PRM_SIZE(set_param), 0},
-};
-BUILD_ASSERT(ARRAY_SIZE(cs_paramcount) == CHARGE_STATE_NUM_CMDS);
-
-#undef ST_CMD_SIZE
-#undef ST_PRM_SIZE
-#undef ST_RSP_SIZE
-
-static int cs_do_cmd(struct ec_params_charge_state *to_ec,
-		     struct ec_response_charge_state *from_ec)
-{
-	int rv;
-	int cmd = to_ec->cmd;
-
-	rv = ec_command(EC_CMD_CHARGE_STATE, 0,
-			to_ec, cs_paramcount[cmd].to_ec_size,
-			from_ec, cs_paramcount[cmd].from_ec_size);
-
-	return (rv < 0 ? 1 : 0);
-}
-
-static const char * const base_params[] = {
-	"chg_voltage",
-	"chg_current",
-	"chg_input_current",
-	"chg_status",
-	"chg_option",
-	"limit_power",
-};
-BUILD_ASSERT(ARRAY_SIZE(base_params) == CS_NUM_BASE_PARAMS);
-
-static int cmd_charge_state(int argc, char **argv)
-{
-	struct ec_params_charge_state param;
-	struct ec_response_charge_state resp;
-	uint32_t p, v;
-	int i, r;
-	char *e;
-
-	if (argc > 1 && !strcasecmp(argv[1], "show")) {
-		param.cmd = CHARGE_STATE_CMD_GET_STATE;
-		r = cs_do_cmd(&param, &resp);
-		if (r)
-			return r;
-		printf("ac = %d\n", resp.get_state.ac);
-		printf("chg_voltage = %dmV\n", resp.get_state.chg_voltage);
-		printf("chg_current = %dmA\n", resp.get_state.chg_current);
-		printf("chg_input_current = %dmA\n",
-		       resp.get_state.chg_input_current);
-		printf("batt_state_of_charge = %d%%\n",
-		       resp.get_state.batt_state_of_charge);
-		return 0;
-	}
-
-	if (argc > 1 && !strcasecmp(argv[1], "param")) {
-		switch (argc) {
-		case 3:
-			if (!strcasecmp(argv[2], "help"))
-				break;
-			param.cmd = CHARGE_STATE_CMD_GET_PARAM;
-			p = strtoul(argv[2], &e, 0);
-			if (e && *e) {
-				fprintf(stderr, "Bad param: %s\n", argv[2]);
-				return -1;
-			}
-			param.get_param.param = p;
-			r = cs_do_cmd(&param, &resp);
-			if (r)
-				return r;
-			v = resp.get_param.value;
-			if (p < CS_NUM_BASE_PARAMS)
-				printf("%d (0x%x)       # %s\n", v, v,
-				       base_params[p]);
-			else
-				printf("%d (0x%x)\n", v, v);
-			return 0;
-		case 4:
-			param.cmd = CHARGE_STATE_CMD_SET_PARAM;
-			p = strtoul(argv[2], &e, 0);
-			if (e && *e) {
-				fprintf(stderr, "Bad param: %s\n", argv[2]);
-				return -1;
-			}
-			v = strtoul(argv[3], &e, 0);
-			if (e && *e) {
-				fprintf(stderr, "Bad value: %s\n", argv[3]);
-				return -1;
-			}
-			param.set_param.param = p;
-			param.set_param.value = v;
-			return cs_do_cmd(&param, &resp);
-		}
-
-		printf("base params:\n");
-		for (i = 0; i < CS_NUM_BASE_PARAMS; i++)
-			printf("  %d   %s\n", i, base_params[i]);
-		printf("custom profile params:\n");
-		printf("  0x%x - 0x%x\n", CS_PARAM_CUSTOM_PROFILE_MIN,
-		       CS_PARAM_CUSTOM_PROFILE_MAX);
-
-		return 0;
-	}
-
-	printf("Usage:\n");
-	printf("  %s show                  - show current state\n", argv[0]);
-	printf("  %s param NUM [VALUE]     - get/set param NUM\n", argv[0]);
-	printf("  %s param help            - show known param NUMs\n", argv[0]);
-	return 0;
-}
-
-int cmd_gpio_get(int argc, char *argv[])
-{
-	struct ec_params_gpio_get_v1 p_v1;
-	struct ec_response_gpio_get_v1 r_v1;
-	int i, rv, subcmd, num_gpios;
-	int cmdver = 1;
-
-	if (!ec_cmd_version_supported(EC_CMD_GPIO_GET, cmdver)) {
-		struct ec_params_gpio_get p;
-		struct ec_response_gpio_get r;
-
-		/* Fall back to version 0 command */
-		cmdver = 0;
-		if (argc != 2) {
-			fprintf(stderr, "Usage: %s <GPIO name>\n", argv[0]);
-			return -1;
-		}
-
-		if (strlen(argv[1]) + 1 > sizeof(p.name)) {
-			fprintf(stderr, "GPIO name too long.\n");
-			return -1;
-		}
-		strcpy(p.name, argv[1]);
-
-		rv = ec_command(EC_CMD_GPIO_GET, cmdver, &p,
-				sizeof(p), &r, sizeof(r));
-		if (rv < 0)
-			return rv;
-
-		printf("GPIO %s = %d\n", p.name, r.val);
-		return 0;
-	}
-
-	if (argc > 2 || (argc == 2 && !strcmp(argv[1], "help"))) {
-		printf("Usage: %s [<subcmd> <GPIO name>]\n", argv[0]);
-		printf("'gpioget <GPIO_NAME>' - Get value by name\n");
-		printf("'gpioget count' - Get count of GPIOS\n");
-		printf("'gpioget all' - Get info for all GPIOs\n");
-		return -1;
-	}
-
-	/* Keeping it consistent with console command behavior */
-	if (argc == 1)
-		subcmd = EC_GPIO_GET_INFO;
-	else if (!strcmp(argv[1], "count"))
-		subcmd = EC_GPIO_GET_COUNT;
-	else if (!strcmp(argv[1], "all"))
-		subcmd = EC_GPIO_GET_INFO;
-	else
-		subcmd = EC_GPIO_GET_BY_NAME;
-
-	if (subcmd == EC_GPIO_GET_BY_NAME) {
-		p_v1.subcmd = EC_GPIO_GET_BY_NAME;
-		if (strlen(argv[1]) + 1 > sizeof(p_v1.get_value_by_name.name)) {
-			fprintf(stderr, "GPIO name too long.\n");
-			return -1;
-		}
-		strcpy(p_v1.get_value_by_name.name, argv[1]);
-
-		rv = ec_command(EC_CMD_GPIO_GET, cmdver, &p_v1,
-				sizeof(p_v1), &r_v1, sizeof(r_v1));
-
-		if (rv < 0)
-			return rv;
-
-		printf("GPIO %s = %d\n", p_v1.get_value_by_name.name,
-			r_v1.get_value_by_name.val);
-		return 0;
-	}
-
-	/* Need GPIO count for EC_GPIO_GET_COUNT or EC_GPIO_GET_INFO */
-	p_v1.subcmd = EC_GPIO_GET_COUNT;
-	rv = ec_command(EC_CMD_GPIO_GET, cmdver, &p_v1,
-			sizeof(p_v1), &r_v1, sizeof(r_v1));
-	if (rv < 0)
-		return rv;
-
-	if (subcmd == EC_GPIO_GET_COUNT) {
-		printf("GPIO COUNT = %d\n", r_v1.get_count.val);
-		return 0;
-	}
-
-	/* subcmd EC_GPIO_GET_INFO */
-	num_gpios = r_v1.get_count.val;
-	p_v1.subcmd = EC_GPIO_GET_INFO;
-
-	for (i = 0; i < num_gpios; i++) {
-		p_v1.get_info.index = i;
-
-		rv = ec_command(EC_CMD_GPIO_GET, cmdver, &p_v1,
-				sizeof(p_v1), &r_v1, sizeof(r_v1));
-		if (rv < 0)
-			return rv;
-
-		printf("%2d %-32s 0x%04X\n", r_v1.get_info.val,
-			r_v1.get_info.name, r_v1.get_info.flags);
-	}
-
-	return 0;
-}
-
-
-int cmd_gpio_set(int argc, char *argv[])
-{
-	struct ec_params_gpio_set p;
-	char *e;
-	int rv;
-
-	if (argc != 3) {
-		fprintf(stderr, "Usage: %s <GPIO name> <0 | 1>\n", argv[0]);
-		return -1;
-	}
-
-	if (strlen(argv[1]) + 1 > sizeof(p.name)) {
-		fprintf(stderr, "GPIO name too long.\n");
-		return -1;
-	}
-	strcpy(p.name, argv[1]);
-
-	p.val = strtol(argv[2], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad value.\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_GPIO_SET, 0, &p, sizeof(p), NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	printf("GPIO %s set to %d\n", p.name, p.val);
-	return 0;
-}
-
-void print_battery_flags(int flags)
-{
-	printf("  Flags                   0x%02x", flags);
-	if (flags & EC_BATT_FLAG_AC_PRESENT)
-		printf(" AC_PRESENT");
-	if (flags & EC_BATT_FLAG_BATT_PRESENT)
-		printf(" BATT_PRESENT");
-	if (flags & EC_BATT_FLAG_DISCHARGING)
-		printf(" DISCHARGING");
-	if (flags & EC_BATT_FLAG_CHARGING)
-		printf(" CHARGING");
-	if (flags & EC_BATT_FLAG_LEVEL_CRITICAL)
-		printf(" LEVEL_CRITICAL");
-	printf("\n");
-}
-
-int get_battery_command(int index)
-{
-	struct ec_params_battery_static_info static_p;
-	struct ec_response_battery_static_info static_r;
-	struct ec_params_battery_dynamic_info dynamic_p;
-	struct ec_response_battery_dynamic_info dynamic_r;
-	int rv;
-
-	printf("Battery %d info:\n", index);
-
-	static_p.index = index;
-	rv = ec_command(EC_CMD_BATTERY_GET_STATIC, 0,
-			&static_p, sizeof(static_p),
-			&static_r, sizeof(static_r));
-	if (rv < 0)
-		return -1;
-
-	dynamic_p.index = index;
-	rv = ec_command(EC_CMD_BATTERY_GET_DYNAMIC, 0,
-			&dynamic_p, sizeof(dynamic_p),
-			&dynamic_r, sizeof(dynamic_r));
-	if (rv < 0)
-		return -1;
-
-	if (dynamic_r.flags & EC_BATT_FLAG_INVALID_DATA) {
-		printf("  Invalid data (not present?)\n");
-		return -1;
-	}
-
-	if (!is_string_printable(static_r.manufacturer))
-		goto cmd_error;
-	printf("  OEM name:               %s\n", static_r.manufacturer);
-
-	if (!is_string_printable(static_r.model))
-		goto cmd_error;
-	printf("  Model number:           %s\n", static_r.model);
-
-	if (!is_string_printable(static_r.type))
-		goto cmd_error;
-	printf("  Chemistry   :           %s\n", static_r.type);
-
-	if (!is_string_printable(static_r.serial))
-		goto cmd_error;
-	printf("  Serial number:          %s\n", static_r.serial);
-
-	if (!is_battery_range(static_r.design_capacity))
-		goto cmd_error;
-	printf("  Design capacity:        %u mAh\n", static_r.design_capacity);
-
-	if (!is_battery_range(dynamic_r.full_capacity))
-		goto cmd_error;
-	printf("  Last full charge:       %u mAh\n", dynamic_r.full_capacity);
-
-	if (!is_battery_range(static_r.design_voltage))
-		goto cmd_error;
-	printf("  Design output voltage   %u mV\n", static_r.design_voltage);
-
-	if (!is_battery_range(static_r.cycle_count))
-		goto cmd_error;
-	printf("  Cycle count             %u\n", static_r.cycle_count);
-
-	if (!is_battery_range(dynamic_r.actual_voltage))
-		goto cmd_error;
-	printf("  Present voltage         %u mV\n", dynamic_r.actual_voltage);
-
-	/* current can be negative */
-	printf("  Present current         %d mA\n", dynamic_r.actual_current);
-
-	if (!is_battery_range(dynamic_r.remaining_capacity))
-		goto cmd_error;
-	printf("  Remaining capacity      %u mAh\n",
-						dynamic_r.remaining_capacity);
-
-	if (!is_battery_range(dynamic_r.desired_voltage))
-		goto cmd_error;
-	printf("  Desired voltage         %u mV\n", dynamic_r.desired_voltage);
-
-	if (!is_battery_range(dynamic_r.desired_current))
-		goto cmd_error;
-	printf("  Desired current         %u mA\n", dynamic_r.desired_current);
-
-	print_battery_flags(dynamic_r.flags);
-	return 0;
-
-cmd_error:
-	fprintf(stderr, "Bad battery info value.\n");
-	return -1;
-}
-
-int cmd_battery(int argc, char *argv[])
-{
-	char batt_text[EC_MEMMAP_TEXT_MAX];
-	int rv, val;
-	char *e;
-	int index = 0;
-
-	if (argc > 2) {
-		fprintf(stderr, "Usage: %s [index]\n", argv[0]);
-		return -1;
-	} else if (argc == 2) {
-		index = strtol(argv[1], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad battery index.\n");
-			return -1;
-		}
-
-		if (index > 0)
-			return get_battery_command(index);
-	}
-
-	/*
-	 * TODO(b:65697620): When supported/required, read battery 0 information
-	 * through EC commands as well.
-	 */
-
-	val = read_mapped_mem8(EC_MEMMAP_BATTERY_VERSION);
-	if (val < 1) {
-		fprintf(stderr, "Battery version %d is not supported\n", val);
-		return -1;
-	}
-
-	printf("Battery info:\n");
-
-	rv = read_mapped_string(EC_MEMMAP_BATT_MFGR, batt_text,
-			sizeof(batt_text));
-	if (rv < 0 || !is_string_printable(batt_text))
-		goto cmd_error;
-	printf("  OEM name:               %s\n", batt_text);
-
-	rv = read_mapped_string(EC_MEMMAP_BATT_MODEL, batt_text,
-			sizeof(batt_text));
-	if (rv < 0 || !is_string_printable(batt_text))
-		goto cmd_error;
-	printf("  Model number:           %s\n", batt_text);
-
-	rv = read_mapped_string(EC_MEMMAP_BATT_TYPE, batt_text,
-			sizeof(batt_text));
-	if (rv < 0 || !is_string_printable(batt_text))
-		goto cmd_error;
-	printf("  Chemistry   :           %s\n", batt_text);
-
-	rv = read_mapped_string(EC_MEMMAP_BATT_SERIAL, batt_text,
-			sizeof(batt_text));
-	printf("  Serial number:          %s\n", batt_text);
-
-	val = read_mapped_mem32(EC_MEMMAP_BATT_DCAP);
-	if (!is_battery_range(val))
-		goto cmd_error;
-	printf("  Design capacity:        %u mAh\n", val);
-
-	val = read_mapped_mem32(EC_MEMMAP_BATT_LFCC);
-	if (!is_battery_range(val))
-		goto cmd_error;
-	printf("  Last full charge:       %u mAh\n", val);
-
-	val = read_mapped_mem32(EC_MEMMAP_BATT_DVLT);
-	if (!is_battery_range(val))
-		goto cmd_error;
-	printf("  Design output voltage   %u mV\n", val);
-
-	val = read_mapped_mem32(EC_MEMMAP_BATT_CCNT);
-	if (!is_battery_range(val))
-		goto cmd_error;
-	printf("  Cycle count             %u\n", val);
-
-	val = read_mapped_mem32(EC_MEMMAP_BATT_VOLT);
-	if (!is_battery_range(val))
-		goto cmd_error;
-	printf("  Present voltage         %u mV\n", val);
-
-	val = read_mapped_mem32(EC_MEMMAP_BATT_RATE);
-	if (!is_battery_range(val))
-		goto cmd_error;
-	printf("  Present current         %u mA\n", val);
-
-	val = read_mapped_mem32(EC_MEMMAP_BATT_CAP);
-	if (!is_battery_range(val))
-		goto cmd_error;
-	printf("  Remaining capacity      %u mAh\n", val);
-
-	val = read_mapped_mem8(EC_MEMMAP_BATT_FLAG);
-	print_battery_flags(val);
-
-	return 0;
-cmd_error:
-	fprintf(stderr, "Bad battery info value. Check protocol version.\n");
-	return -1;
-}
-
-int cmd_battery_cut_off(int argc, char *argv[])
-{
-	struct ec_params_battery_cutoff p;
-	int cmd_version;
-	int rv;
-
-	memset(&p, 0, sizeof(p));
-	if (ec_cmd_version_supported(EC_CMD_BATTERY_CUT_OFF, 1)) {
-		cmd_version = 1;
-		if (argc > 1) {
-			if (!strcasecmp(argv[1], "at-shutdown")) {
-				p.flags = EC_BATTERY_CUTOFF_FLAG_AT_SHUTDOWN;
-			} else {
-				fprintf(stderr, "Bad parameter: %s\n", argv[1]);
-				return -1;
-			}
-		}
-	} else {
-		/* Fall back to version 0 command */
-		cmd_version = 0;
-		if (argc > 1) {
-			if (!strcasecmp(argv[1], "at-shutdown")) {
-				fprintf(stderr, "Explicit 'at-shutdown' ");
-				fprintf(stderr, "parameter not supported.\n");
-			} else {
-				fprintf(stderr, "Bad parameter: %s\n", argv[1]);
-			}
-			return -1;
-		}
-	}
-
-	rv = ec_command(EC_CMD_BATTERY_CUT_OFF, cmd_version, &p, sizeof(p),
-			NULL, 0);
-	rv = (rv < 0 ? rv : 0);
-
-	if (rv < 0) {
-		fprintf(stderr, "Failed to cut off battery, rv=%d\n", rv);
-		fprintf(stderr, "It is expected if the rv is -%d "
-				"(EC_RES_INVALID_COMMAND) if the battery "
-				"doesn't support cut-off function.\n",
-				EC_RES_INVALID_COMMAND);
-	} else {
-		printf("\n");
-		printf("SUCCESS. The battery has arranged a cut-off.\n");
-
-		if (cmd_version == 1 &&
-		    (p.flags & EC_BATTERY_CUTOFF_FLAG_AT_SHUTDOWN))
-			printf("The battery will be cut off after shutdown.\n");
-		else
-			printf("The system should be shutdown immediately.\n");
-
-		printf("\n");
-	}
-	return rv;
-}
-
-int cmd_battery_vendor_param(int argc, char *argv[])
-{
-	struct ec_params_battery_vendor_param p;
-	struct ec_response_battery_vendor_param r;
-	char *e;
-	int rv;
-
-	if (argc < 3)
-		goto cmd_battery_vendor_param_usage;
-
-	if (!strcasecmp(argv[1], "get"))
-		p.mode = BATTERY_VENDOR_PARAM_MODE_GET;
-	else if (!strcasecmp(argv[1], "set"))
-		p.mode = BATTERY_VENDOR_PARAM_MODE_SET;
-	else
-		goto cmd_battery_vendor_param_usage;
-
-	p.param = strtol(argv[2], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Invalid param.\n");
-		goto cmd_battery_vendor_param_usage;
-	}
-
-	if (p.mode == BATTERY_VENDOR_PARAM_MODE_SET) {
-		if (argc != 4) {
-			fprintf(stderr, "Missing value.\n");
-			goto cmd_battery_vendor_param_usage;
-		}
-
-		p.value = strtol(argv[3], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Invalid value.\n");
-			goto cmd_battery_vendor_param_usage;
-		}
-	}
-
-	rv = ec_command(EC_CMD_BATTERY_VENDOR_PARAM, 0, &p, sizeof(p),
-			&r, sizeof(r));
-
-	if (rv < 0)
-		return rv;
-
-	printf("0x%08x\n", r.value);
-
-	return 0;
-
-cmd_battery_vendor_param_usage:
-	fprintf(stderr,
-		"Usage:\t %s get <param>\n"
-		"\t %s set <param> <value>\n",
-		argv[0], argv[0]);
-	return -1;
-}
-
-int cmd_board_version(int argc, char *argv[])
-{
-	struct ec_response_board_version response;
-	int rv;
-
-	rv = ec_command(EC_CMD_GET_BOARD_VERSION, 0, NULL, 0, &response,
-			sizeof(response));
-	if (rv < 0)
-		return rv;
-
-	printf("%d\n", response.board_version);
-	return rv;
-}
-
-static void cmd_cbi_help(char *cmd)
-{
-	fprintf(stderr,
-	"  Usage: %s get <tag> [get_flag]\n"
-	"  Usage: %s set <tag> <value/string> <size> [set_flag]\n"
-	"  Usage: %s remove <tag> [set_flag]\n"
-	"    <tag> is one of:\n"
-	"      0: BOARD_VERSION\n"
-	"      1: OEM_ID\n"
-	"      2: SKU_ID\n"
-	"      3: DRAM_PART_NUM (string)\n"
-	"      4: OEM_NAME (string)\n"
-	"      5: MODEL_ID\n"
-	"      6: FW_CONFIG\n"
-	"      7: PCB_VENDOR\n"
-	"      8: SSFC\n"
-	"    <size> is the size of the data in byte. It should be zero for\n"
-	"      string types.\n"
-	"    <value/string> is an integer or a string to be set\n"
-	"    [get_flag] is combination of:\n"
-	"      01b: Invalidate cache and reload data from EEPROM\n"
-	"    [set_flag] is combination of:\n"
-	"      01b: Skip write to EEPROM. Use for back-to-back writes\n"
-	"      10b: Set all fields to defaults first\n", cmd, cmd, cmd);
-}
-
-static int cmd_cbi_is_string_field(enum cbi_data_tag tag)
-{
-	return tag == CBI_TAG_DRAM_PART_NUM || tag == CBI_TAG_OEM_NAME;
-}
-
-/*
- * Write value to CBI
- *
- * TODO: Support asynchronous write
- */
-static int cmd_cbi(int argc, char *argv[])
-{
-	enum cbi_data_tag tag;
-	char *e;
-	int rv;
-
-	if (argc < 3) {
-		fprintf(stderr, "Invalid number of params\n");
-		cmd_cbi_help(argv[0]);
-		return -1;
-	}
-
-	/* Tag */
-	tag = strtol(argv[2], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad tag\n");
-		return -1;
-	}
-
-	if (!strcasecmp(argv[1], "get")) {
-		struct ec_params_get_cbi p = { 0 };
-		int i;
-
-		p.tag = tag;
-		if (argc > 3) {
-			p.flag = strtol(argv[3], &e, 0);
-			if (e && *e) {
-				fprintf(stderr, "Bad flag\n");
-				return -1;
-			}
-		}
-		rv = ec_command(EC_CMD_GET_CROS_BOARD_INFO, 0, &p, sizeof(p),
-				ec_inbuf, ec_max_insize);
-		if (rv < 0) {
-			fprintf(stderr, "Error code: %d\n", rv);
-			return rv;
-		}
-		if (rv < sizeof(uint8_t)) {
-			fprintf(stderr, "Invalid size: %d\n", rv);
-			return -1;
-		}
-		if (cmd_cbi_is_string_field(tag)) {
-			printf("%.*s", rv, (const char *)ec_inbuf);
-		} else {
-			const uint8_t * const buffer = ec_inbuf;
-
-			if (rv <= sizeof(uint32_t)) {
-				uint32_t int_value = 0;
-
-				for (i = 0; i < rv; i++)
-					int_value |= buffer[i] << (i * 8);
-
-				printf("As uint: %u (0x%x)\n", int_value,
-				       int_value);
-			}
-			printf("As binary:");
-			for (i = 0; i < rv; i++) {
-				if (i % 32 == 31)
-					printf("\n");
-				printf(" %02x", buffer[i]);
-			}
-		}
-		printf("\n");
-		return 0;
-	} else if (!strcasecmp(argv[1], "set")) {
-		struct ec_params_set_cbi *p =
-				(struct ec_params_set_cbi *)ec_outbuf;
-		void *val_ptr;
-		uint32_t val;
-		uint8_t size;
-		if (argc < 5) {
-			fprintf(stderr, "Invalid number of params\n");
-			cmd_cbi_help(argv[0]);
-			return -1;
-		}
-		memset(p, 0, ec_max_outsize);
-		p->tag = tag;
-
-		if (cmd_cbi_is_string_field(tag)) {
-			val_ptr = argv[3];
-			size = strlen(val_ptr) + 1;
-		} else {
-			val = strtol(argv[3], &e, 0);
-			if (e && *e) {
-				fprintf(stderr, "Bad value\n");
-				return -1;
-			}
-			size = strtol(argv[4], &e, 0);
-			if ((e && *e) || size < 1 || 4 < size ||
-					val >= (1ull << size*8)) {
-				fprintf(stderr, "Bad size: %d\n", size);
-				return -1;
-			}
-			val_ptr = &val;
-		}
-
-		if (size > ec_max_outsize - sizeof(*p)) {
-			fprintf(stderr, "Size exceeds parameter buffer: %d\n",
-				size);
-			return -1;
-		}
-		/* Little endian */
-		memcpy(p->data, val_ptr, size);
-		p->size = size;
-		if (argc > 5) {
-			p->flag = strtol(argv[5], &e, 0);
-			if (e && *e) {
-				fprintf(stderr, "Bad flag\n");
-				return -1;
-			}
-		}
-		rv = ec_command(EC_CMD_SET_CROS_BOARD_INFO, 0,
-				p, sizeof(*p) + size, NULL, 0);
-		if (rv < 0) {
-			if (rv == -EC_RES_ACCESS_DENIED - EECRESULT)
-				fprintf(stderr, "Write-protect is enabled or "
-					"EC explicitly refused to change the "
-					"requested field.\n");
-			else
-				fprintf(stderr, "Error code: %d\n", rv);
-			return rv;
-		}
-		return 0;
-	} else if (!strcasecmp(argv[1], "remove")) {
-		struct ec_params_set_cbi p = { 0 };
-
-		p.tag = tag;
-		p.size = 0;
-		if (argc > 3) {
-			p.flag = strtol(argv[3], &e, 0);
-			if (e && *e) {
-				fprintf(stderr, "Bad flag\n");
-				return -1;
-			}
-		}
-		rv = ec_command(EC_CMD_SET_CROS_BOARD_INFO, 0,
-				&p, sizeof(p), NULL, 0);
-		if (rv < 0) {
-			if (rv == -EC_RES_ACCESS_DENIED - EECRESULT)
-				fprintf(stderr, "Write-protect is enabled or "
-					"EC explicitly refused to change the "
-					"requested field.\n");
-			else
-				fprintf(stderr, "Error code: %d\n", rv);
-			return rv;
-		}
-		return 0;
-	}
-
-	fprintf(stderr, "Invalid sub command: %s\n", argv[1]);
-	cmd_cbi_help(argv[0]);
-
-	return -1;
-}
-
-int cmd_chipinfo(int argc, char *argv[])
-{
-	struct ec_response_get_chip_info info;
-	int rv;
-
-	printf("Chip info:\n");
-
-	rv = ec_command(EC_CMD_GET_CHIP_INFO, 0, NULL, 0, &info, sizeof(info));
-	if (rv < 0)
-		return rv;
-	printf("  vendor:    %s\n", info.vendor);
-	printf("  name:      %s\n", info.name);
-	printf("  revision:  %s\n", info.revision);
-
-	return 0;
-}
-
-int cmd_proto_info(int argc, char *argv[])
-{
-	struct ec_response_get_protocol_info info;
-	int rv;
-	int i;
-
-	printf("Protocol info:\n");
-
-	rv = ec_command(EC_CMD_GET_PROTOCOL_INFO, 0, NULL, 0,
-			&info, sizeof(info));
-	if (rv < 0) {
-		fprintf(stderr, "Protocol info unavailable.  EC probably only "
-				"supports protocol version 2.\n");
-		return rv;
-	}
-
-	printf("  protocol versions:");
-	for (i = 0; i < 32; i++) {
-		if (info.protocol_versions & BIT(i))
-			printf(" %d", i);
-	}
-	printf("\n");
-
-	printf("  max request:  %4d bytes\n", info.max_request_packet_size);
-	printf("  max response: %4d bytes\n", info.max_response_packet_size);
-	printf("  flags: 0x%08x\n", info.flags);
-	if (info.flags & EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED)
-		printf("    EC_RES_IN_PROGRESS supported\n");
-	return 0;
-}
-
-static int ec_hash_help(const char *cmd)
-{
-	printf("Usage:\n");
-	printf("  %s                        - get last hash\n", cmd);
-	printf("  %s abort                  - abort hashing\n", cmd);
-	printf("  %s start [<offset> <size> [<nonce>]] - start hashing\n", cmd);
-	printf("  %s recalc [<offset> <size> [<nonce>]] - sync rehash\n", cmd);
-	printf("\n"
-	       "If <offset> is RO or RW, offset and size are computed\n"
-	       "automatically for the EC-RO or EC-RW firmware image.\n");
-
-	return 0;
-}
-
-
-static int ec_hash_print(const struct ec_response_vboot_hash *r)
-{
-	int i;
-
-	if (r->status == EC_VBOOT_HASH_STATUS_BUSY) {
-		printf("status:  busy\n");
-		return 0;
-	} else if (r->status == EC_VBOOT_HASH_STATUS_NONE) {
-		printf("status:  unavailable\n");
-		return 0;
-	} else if (r->status != EC_VBOOT_HASH_STATUS_DONE) {
-		printf("status:  %d\n", r->status);
-		return 0;
-	}
-
-	printf("status:  done\n");
-	if (r->hash_type == EC_VBOOT_HASH_TYPE_SHA256)
-		printf("type:    SHA-256\n");
-	else
-		printf("type:    %d\n", r->hash_type);
-
-	printf("offset:  0x%08x\n", r->offset);
-	printf("size:    0x%08x\n", r->size);
-
-	printf("hash:    ");
-	for (i = 0; i < r->digest_size; i++)
-		printf("%02x", r->hash_digest[i]);
-	printf("\n");
-	return 0;
-}
-
-
-int cmd_ec_hash(int argc, char *argv[])
-{
-	struct ec_params_vboot_hash p;
-	struct ec_response_vboot_hash r;
-	char *e;
-	int rv;
-
-	memset(&p, 0, sizeof(p));
-	if (argc < 2) {
-		/* Get hash status */
-		p.cmd = EC_VBOOT_HASH_GET;
-		rv = ec_command(EC_CMD_VBOOT_HASH, 0,
-				&p, sizeof(p), &r, sizeof(r));
-		if (rv < 0)
-			return rv;
-
-		return ec_hash_print(&r);
-	}
-
-	if (argc == 2 && !strcasecmp(argv[1], "abort")) {
-		/* Abort hash calculation */
-		p.cmd = EC_VBOOT_HASH_ABORT;
-		rv = ec_command(EC_CMD_VBOOT_HASH, 0,
-				&p, sizeof(p), &r, sizeof(r));
-		return (rv < 0 ? rv : 0);
-	}
-
-	/* The only other commands are start and recalc */
-	if (!strcasecmp(argv[1], "start"))
-		p.cmd = EC_VBOOT_HASH_START;
-	else if (!strcasecmp(argv[1], "recalc"))
-		p.cmd = EC_VBOOT_HASH_RECALC;
-	else
-		return ec_hash_help(argv[0]);
-
-	p.hash_type = EC_VBOOT_HASH_TYPE_SHA256;
-
-	if (argc < 3) {
-		fprintf(stderr, "Must specify offset\n");
-		return -1;
-	}
-
-	if (!strcasecmp(argv[2], "ro")) {
-		p.offset = EC_VBOOT_HASH_OFFSET_RO;
-		p.size = 0;
-		printf("Hashing EC-RO...\n");
-	} else if (!strcasecmp(argv[2], "rw")) {
-		p.offset = EC_VBOOT_HASH_OFFSET_ACTIVE;
-		p.size = 0;
-		printf("Hashing EC-RW...\n");
-	} else if (argc < 4) {
-		fprintf(stderr, "Must specify size\n");
-		return -1;
-	} else {
-		p.offset = strtol(argv[2], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad offset.\n");
-			return -1;
-		}
-		p.size = strtol(argv[3], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad size.\n");
-			return -1;
-		}
-		printf("Hashing %d bytes at offset %d...\n", p.size, p.offset);
-	}
-
-	if (argc == 5) {
-		/*
-		 * Technically nonce can be any binary data up to 64 bytes,
-		 * but this command only supports a 32-bit value.
-		 */
-		uint32_t nonce = strtol(argv[4], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad nonce integer.\n");
-			return -1;
-		}
-		memcpy(p.nonce_data, &nonce, sizeof(nonce));
-		p.nonce_size = sizeof(nonce);
-	} else
-		p.nonce_size = 0;
-
-	rv = ec_command(EC_CMD_VBOOT_HASH, 0, &p, sizeof(p), &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	/* Start command doesn't wait for hashing to finish */
-	if (p.cmd == EC_VBOOT_HASH_START)
-		return 0;
-
-	/* Recalc command does wait around, so a result is ready now */
-	return ec_hash_print(&r);
-}
-
-
-int cmd_rtc_get(int argc, char *argv[])
-{
-	struct ec_response_rtc r;
-	int rv;
-
-	rv = ec_command(EC_CMD_RTC_GET_VALUE, 0, NULL, 0, &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	printf("Current time: 0x%08x (%d)\n", r.time, r.time);
-	return 0;
-}
-
-
-int cmd_rtc_set(int argc, char *argv[])
-{
-	struct ec_params_rtc p;
-	char *e;
-	int rv;
-
-	if (argc != 2) {
-		fprintf(stderr, "Usage: %s <time>\n", argv[0]);
-		return -1;
-	}
-	p.time = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad time.\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_RTC_SET_VALUE, 0, &p, sizeof(p), NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	printf("Time set.\n");
-	return 0;
-}
-
-int cmd_rtc_set_alarm(int argc, char *argv[])
-{
-	struct ec_params_rtc p;
-	char *e;
-	int rv;
-
-	if (argc != 2) {
-		fprintf(stderr, "Usage: %s <sec>\n", argv[0]);
-		return -1;
-	}
-	p.time = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad time.\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_RTC_SET_ALARM, 0, &p, sizeof(p), NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	if (p.time == 0)
-		printf("Disabling alarm.\n");
-	else
-		printf("Alarm set to go off in %d secs.\n", p.time);
-	return 0;
-}
-
-int cmd_rtc_get_alarm(int argc, char *argv[])
-{
-	struct ec_response_rtc r;
-	int rv;
-
-	rv = ec_command(EC_CMD_RTC_GET_ALARM, 0, NULL, 0, &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	if (r.time == 0)
-		printf("Alarm not set\n");
-	else
-		printf("Alarm to go off in %d secs\n", r.time);
-	return 0;
-}
-
-int cmd_console(int argc, char *argv[])
-{
-	char *out = (char *)ec_inbuf;
-	int rv;
-
-	/* Snapshot the EC console */
-	rv = ec_command(EC_CMD_CONSOLE_SNAPSHOT, 0, NULL, 0, NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	/* Loop and read from the snapshot until it's done */
-	while (1) {
-		rv = ec_command(EC_CMD_CONSOLE_READ, 0,
-				NULL, 0, ec_inbuf, ec_max_insize);
-		if (rv < 0)
-			return rv;
-
-		/* Empty response means done */
-		if (!rv || !*out)
-			break;
-
-		/* Make sure output is null-terminated, then dump it */
-		out[ec_max_insize - 1] = '\0';
-		fputs(out, stdout);
-	}
-	printf("\n");
-	return 0;
-}
-struct param_info {
-	const char *name;	/* name of this parameter */
-	const char *help;	/* help message */
-	int size;		/* size in bytes */
-	int offset;		/* offset within structure */
-};
-
-#define FIELD(fname, field, help_str) \
-	{ \
-		.name = fname, \
-		.help = help_str, \
-		.size = sizeof(((struct ec_mkbp_config *)NULL)->field), \
-		.offset = __builtin_offsetof(struct ec_mkbp_config, field), \
-	}
-
-static const struct param_info keyconfig_params[] = {
-	FIELD("scan_period", scan_period_us, "period between scans"),
-	FIELD("poll_timeout", poll_timeout_us,
-	      "revert to irq mode after no activity for this long"),
-	FIELD("min_post_scan_delay", min_post_scan_delay_us,
-	      "minimum post-scan delay before starting a new scan"),
-	FIELD("output_settle", output_settle_us,
-	      "delay to wait for output to settle"),
-	FIELD("debounce_down", debounce_down_us,
-	      "time for debounce on key down"),
-	FIELD("debounce_up", debounce_up_us, "time for debounce on key up"),
-	FIELD("fifo_max_depth", fifo_max_depth,
-	      "maximum depth to allow for fifo (0 = disable)"),
-	FIELD("flags", flags, "0 to disable scanning, 1 to enable"),
-};
-
-static const struct param_info *find_field(const struct param_info *params,
-		int count, const char *name, unsigned int *nump)
-{
-	const struct param_info *param;
-	int i;
-
-	for (i = 0, param = params; i < count; i++, param++) {
-		if (0 == strcmp(param->name, name)) {
-			if (nump)
-				*nump = i;
-			return param;
-		}
-	}
-
-	fprintf(stderr, "Unknown parameter '%s'\n", name);
-	return NULL;
-}
-
-static int get_value(const struct param_info *param, const char *config)
-{
-	const char *field;
-
-	field = config + param->offset;
-	switch (param->size) {
-	case 1:
-		return *(uint8_t *)field;
-	case 2:
-		return *(uint16_t *)field;
-	case 4:
-		return *(uint32_t *)field;
-	default:
-		fprintf(stderr, "Internal error: unknown size %d\n",
-			param->size);
-	}
-
-	return -1;
-}
-
-static int show_fields(struct ec_mkbp_config *config, int argc, char *argv[])
-{
-	const struct param_info *param;
-	uint32_t mask;
-	int i;
-
-	if (!argc) {
-		mask = -1U;	/* show all fields */
-	} else {
-		mask = 0;
-		while (argc > 0) {
-			unsigned int num;
-
-			param = find_field(keyconfig_params,
-					   ARRAY_SIZE(keyconfig_params),
-					   argv[0], &num);
-			if (!param)
-				return -1;
-			mask |= 1 << num;
-			argc--;
-			argv++;
-		}
-	}
-
-	param = keyconfig_params;
-	for (i = 0; i < ARRAY_SIZE(keyconfig_params); i++, param++) {
-		if (mask & BIT(i)) {
-			fprintf(stderr, "%-12s   %u\n", param->name,
-				get_value(param, (char *)config));
-		}
-	}
-
-	return 0;
-}
-
-static int cmd_kbinfo(int argc, char *argv[])
-{
-	struct ec_params_mkbp_info info = {
-		.info_type = EC_MKBP_INFO_KBD,
-	};
-	struct ec_response_mkbp_info resp;
-	int rv;
-
-	if (argc > 1) {
-		fprintf(stderr, "Too many args\n");
-		return -1;
-	}
-	rv = ec_command(EC_CMD_MKBP_INFO, 0, &info, sizeof(info), &resp,
-			sizeof(resp));
-	if (rv < 0)
-		return rv;
-
-	printf("Matrix rows: %d\n", resp.rows);
-	printf("Matrix columns: %d\n", resp.cols);
-
-	return 0;
-}
-
-static int cmd_kbid(int argc, char *argv[])
-{
-	struct ec_response_keyboard_id response;
-	int rv;
-
-	if (argc > 1) {
-		fprintf(stderr, "Too many args\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_GET_KEYBOARD_ID, 0, NULL, 0, &response,
-			sizeof(response));
-	if (rv < 0)
-		return rv;
-	switch (response.keyboard_id) {
-	case KEYBOARD_ID_UNSUPPORTED:
-		/* Keyboard ID was not supported */
-		printf("Keyboard doesn't support ID\n");
-		break;
-	case KEYBOARD_ID_UNREADABLE:
-		/* Ghosting ID was detected */
-		printf("Reboot and keep hands off the keyboard during"
-		       " next boot-up\n");
-		break;
-	default:
-		/* Valid keyboard ID value was reported*/
-		printf("%x\n", response.keyboard_id);
-	}
-	return rv;
-}
-
-static int cmd_keyconfig(int argc, char *argv[])
-{
-	struct ec_params_mkbp_set_config req;
-	int cmd;
-	int rv;
-
-	if (argc < 2) {
-		const struct param_info *param;
-		int i;
-
-		fprintf(stderr, "Usage: %s get [<param>] - print params\n"
-			"\t%s set [<param>> <value>]\n"
-			"   Available params are: (all time values are in us)",
-			argv[0], argv[0]);
-
-		param = keyconfig_params;
-		for (i = 0; i < ARRAY_SIZE(keyconfig_params); i++, param++) {
-			fprintf(stderr, "%-12s   %s\n", param->name,
-				param->name);
-		}
-		return -1;
-	}
-
-	/* Get the command */
-	if (0 == strcmp(argv[1], "get")) {
-		cmd = EC_CMD_MKBP_GET_CONFIG;
-	} else if (0 == strcmp(argv[1], "set")) {
-		cmd = EC_CMD_MKBP_SET_CONFIG;
-	} else {
-		fprintf(stderr, "Invalid command '%s\n", argv[1]);
-		return -1;
-	}
-
-	switch (cmd) {
-	case EC_CMD_MKBP_GET_CONFIG:
-		/* Read the existing config */
-		rv = ec_command(cmd, 0, NULL, 0, &req, sizeof(req));
-		if (rv < 0)
-			return rv;
-		show_fields(&req.config, argc - 2, argv + 2);
-		break;
-	}
-
-	return 0;
-}
-
-static const char * const mkbp_button_strings[] = {
-	[EC_MKBP_POWER_BUTTON] = "Power",
-	[EC_MKBP_VOL_UP] = "Volume up",
-	[EC_MKBP_VOL_DOWN] = "Volume down",
-	[EC_MKBP_RECOVERY] = "Recovery",
-};
-
-static const char * const mkbp_switch_strings[] = {
-	[EC_MKBP_LID_OPEN] = "Lid open",
-	[EC_MKBP_TABLET_MODE] = "Tablet mode",
-	[EC_MKBP_BASE_ATTACHED] = "Base attached",
-};
-
-static int cmd_mkbp_get(int argc, char *argv[])
-{
-	struct ec_params_mkbp_info p;
-	union ec_response_get_next_data r;
-	int rv;
-	int i;
-	uint32_t supported;
-
-	if (argc < 2) {
-		fprintf(stderr, "Usage: %s <buttons|switches>\n", argv[0]);
-		return -1;
-	}
-
-	if (strncmp(argv[1], "button", 6) == 0) {
-		p.event_type = EC_MKBP_EVENT_BUTTON;
-	} else if (strncmp(argv[1], "switch", 6) == 0) {
-		p.event_type = EC_MKBP_EVENT_SWITCH;
-	} else {
-		fprintf(stderr, "Invalid param: '%s'\n", argv[1]);
-		return -1;
-	}
-
-	p.info_type = EC_MKBP_INFO_SUPPORTED;
-	rv = ec_command(EC_CMD_MKBP_INFO, 0, &p, sizeof(p), &r,
-			sizeof(r));
-	if (rv < 0)
-		return rv;
-	if (p.event_type == EC_MKBP_EVENT_BUTTON)
-		supported = r.buttons;
-	else if (p.event_type == EC_MKBP_EVENT_SWITCH)
-		supported = r.switches;
-	else
-		return -1;
-
-	p.info_type = EC_MKBP_INFO_CURRENT;
-	rv = ec_command(EC_CMD_MKBP_INFO, 0, &p, sizeof(p), &r,
-			sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	if (p.event_type == EC_MKBP_EVENT_BUTTON) {
-		printf("MKBP buttons state: 0x%04x (supported: 0x%04x)\n",
-		       r.buttons, supported);
-		for (i = 0; i < ARRAY_SIZE(mkbp_button_strings); i++) {
-			if (supported & BIT(i) && mkbp_button_strings[i]) {
-				printf("%s: %s\n", mkbp_button_strings[i],
-				       r.buttons & BIT(i) ? "ON" : "OFF");
-				supported &= ~BIT(i);
-			}
-		}
-		if (supported)
-			printf("Unknown buttons: 0x%04x\n", supported);
-	} else if (p.event_type == EC_MKBP_EVENT_SWITCH) {
-		printf("MKBP switches state: 0x%04x (supported: 0x%04x)\n",
-		       r.switches, supported);
-		for (i = 0; i < ARRAY_SIZE(mkbp_switch_strings); i++) {
-			if (supported & BIT(i) && mkbp_switch_strings[i]) {
-				printf("%s: %s\n", mkbp_switch_strings[i],
-				       r.switches & BIT(i) ? "ON" : "OFF");
-				supported &= ~BIT(i);
-			}
-		}
-		if (supported)
-			printf("Unknown switches: 0x%04x\n", supported);
-	}
-
-	return 0;
-}
-
-static int cmd_mkbp_wake_mask(int argc, char *argv[])
-{
-	struct ec_params_mkbp_event_wake_mask p;
-	struct ec_response_mkbp_event_wake_mask r;
-	int rv;
-
-	if (argc < 3) {
-		fprintf(stderr, "Usage: %s get <event|hostevent>\n"
-			"\t%s set <event|hostevent> <mask>\n", argv[0],
-			argv[0]);
-		return -1;
-	}
-
-	/* Determine if the user want to get or set the wake mask. */
-	if (strncmp(argv[1], "get", 3) == 0) {
-		p.action = GET_WAKE_MASK;
-	} else if (strncmp(argv[1], "set", 3) == 0) {
-		p.action = SET_WAKE_MASK;
-	} else {
-		fprintf(stderr, "Invalid param: '%s'\n", argv[1]);
-		return -1;
-	}
-
-	/* Determine which mask is of interest. */
-	if (strncmp(argv[2], "event", 5) == 0) {
-		p.mask_type = EC_MKBP_EVENT_WAKE_MASK;
-	} else if (strncmp(argv[2], "hostevent", 9) == 0) {
-		p.mask_type = EC_MKBP_HOST_EVENT_WAKE_MASK;
-	} else {
-		fprintf(stderr, "Invalid param: '%s'\n", argv[2]);
-		return -1;
-	}
-
-	if (p.action == SET_WAKE_MASK) {
-		char *e;
-
-		if (argc < 4) {
-			fprintf(stderr, "Missing mask value!");
-			return -1;
-		}
-
-		p.new_wake_mask = strtol(argv[3], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad mask: '%s'", argv[1]);
-			return -1;
-		}
-	}
-
-	rv = ec_command(EC_CMD_MKBP_WAKE_MASK, 0, &p, sizeof(p), &r,
-			sizeof(r));
-	if (rv < 0) {
-		if (rv == -EECRESULT-EC_RES_INVALID_PARAM) {
-			fprintf(stderr, "Unknown mask, or mask is not in use.  "
-				"You may need to enable the "
-				"CONFIG_MKBP_%s_WAKEUP_MASK option in the EC.\n"
-				, p.mask_type == EC_MKBP_EVENT_WAKE_MASK ?
-				"EVENT" : "HOSTEVENT");
-		}
-		return rv;
-	}
-
-	if (p.action == GET_WAKE_MASK)
-		printf("MBKP %s wake mask: 0x%08x\n", argv[2], r.wake_mask);
-	else if (p.action == SET_WAKE_MASK)
-		printf("MKBP %s wake mask set.\n", argv[2]);
-
-	return 0;
-}
-
-/* Index is already checked. argv[0] is first param value */
-static int cmd_tmp006cal_v0(int idx, int argc, char *argv[])
-{
-	struct ec_params_tmp006_get_calibration pg;
-	struct ec_response_tmp006_get_calibration_v0 rg;
-	struct ec_params_tmp006_set_calibration_v0 ps;
-	float val;
-	char *e;
-	int i, rv;
-
-	/* Get current values */
-	pg.index = idx;
-	rv = ec_command(EC_CMD_TMP006_GET_CALIBRATION, 0,
-			&pg, sizeof(pg), &rg, sizeof(rg));
-	if (rv < 0)
-		return rv;
-
-	if (!argc) {
-		/* If no new values are given, just print what we have */
-		printf("S0: %e\n", rg.s0);
-		printf("b0: %e\n", rg.b0);
-		printf("b1: %e\n", rg.b1);
-		printf("b2: %e\n", rg.b2);
-		return EC_SUCCESS;
-	}
-
-	/* Prepare to reuse the current values */
-	memset(&ps, 0, sizeof(ps));
-	ps.index = idx;
-	ps.s0 = rg.s0;
-	ps.b0 = rg.b0;
-	ps.b1 = rg.b1;
-	ps.b2 = rg.b2;
-
-	/* Parse up to four args, skipping any that are just "-" */
-	for (i = 0; i < argc && i < 4; i++) {
-		if (!strcmp(argv[i], "-"))
-			continue;
-		val = strtod(argv[i], &e);
-		if (e && *e) {
-			fprintf(stderr,
-				"Bad arg \"%s\". Use \"-\" to skip a param.\n",
-				argv[i]);
-			return -1;
-		}
-		switch (i) {
-		case 0:
-			ps.s0 = val;
-			break;
-		case 1:
-			ps.b0 = val;
-			break;
-		case 2:
-			ps.b1 = val;
-			break;
-		case 3:
-			ps.b2 = val;
-			break;
-		}
-	}
-
-	/* Set 'em */
-	return ec_command(EC_CMD_TMP006_SET_CALIBRATION, 0,
-			  &ps, sizeof(ps), NULL, 0);
-}
-
-/* Index is already checked. argv[0] is first param value */
-static int cmd_tmp006cal_v1(int idx, int argc, char *argv[])
-{
-	struct ec_params_tmp006_get_calibration pg;
-	struct ec_response_tmp006_get_calibration_v1 *rg = ec_inbuf;
-	struct ec_params_tmp006_set_calibration_v1 *ps = ec_outbuf;
-	float val;
-	char *e;
-	int i, rv, cmdsize;
-
-	/* Algorithm 1 parameter names */
-	static const char * const alg1_pname[] = {
-		"s0", "a1", "a2", "b0", "b1", "b2", "c2",
-		"d0", "d1", "ds", "e0", "e1",
-	};
-
-	/* Get current values */
-	pg.index = idx;
-	rv = ec_command(EC_CMD_TMP006_GET_CALIBRATION, 1,
-			&pg, sizeof(pg), rg, ec_max_insize);
-	if (rv < 0)
-		return rv;
-
-	if (!argc) {
-		/* If no new values are given, just print what we have */
-		printf("algorithm:  %d\n", rg->algorithm);
-		printf("params:\n");
-		/* We only know about alg 1 at the moment */
-		if (rg->algorithm == 1)
-			for (i = 0; i < rg->num_params; i++)
-				printf("  %s  %e\n", alg1_pname[i], rg->val[i]);
-		else
-			for (i = 0; i < rg->num_params; i++)
-				printf("  param%d  %e\n", i, rg->val[i]);
-		return EC_SUCCESS;
-	}
-
-	/* Prepare to reuse the current values */
-	memset(ps, 0, ec_max_outsize);
-	ps->index = idx;
-	ps->algorithm = rg->algorithm;
-	ps->num_params = rg->num_params;
-	for (i = 0; i < rg->num_params; i++)
-		ps->val[i] = rg->val[i];
-
-	/* Parse the args, skipping any that are just "-" */
-	for (i = 0; i < argc && i < rg->num_params; i++) {
-		if (!strcmp(argv[i], "-"))
-			continue;
-		val = strtod(argv[i], &e);
-		if (e && *e) {
-			fprintf(stderr,
-				"Bad arg \"%s\". Use \"-\" to skip a param.\n",
-				argv[i]);
-			return -1;
-		}
-		ps->val[i] = val;
-	}
-
-	/* Set 'em */
-	cmdsize = sizeof(*ps) + ps->num_params * sizeof(ps->val[0]);
-	return ec_command(EC_CMD_TMP006_SET_CALIBRATION, 1,
-			  ps, cmdsize, NULL, 0);
-}
-
-int cmd_tmp006cal(int argc, char *argv[])
-{
-	char *e;
-	int idx;
-
-	if (argc < 2) {
-		fprintf(stderr, "Must specify tmp006 index.\n");
-		return -1;
-	}
-
-	idx = strtol(argv[1], &e, 0);
-	if ((e && *e) || idx < 0 || idx > 255) {
-		fprintf(stderr, "Bad index.\n");
-		return -1;
-	}
-
-	/* Pass just the params (if any) to the helper function */
-	argc -= 2;
-	argv += 2;
-
-	if (ec_cmd_version_supported(EC_CMD_TMP006_GET_CALIBRATION, 1))
-		return cmd_tmp006cal_v1(idx, argc, argv);
-
-	if (ec_cmd_version_supported(EC_CMD_TMP006_GET_CALIBRATION, 0))
-		return cmd_tmp006cal_v0(idx, argc, argv);
-
-	printf("The EC is being stupid\n");
-	return -1;
-}
-
-int cmd_tmp006raw(int argc, char *argv[])
-{
-	struct ec_params_tmp006_get_raw p;
-	struct ec_response_tmp006_get_raw r;
-	char *e;
-	int idx;
-	int rv;
-
-	if (argc != 2) {
-		fprintf(stderr, "Must specify tmp006 index.\n");
-		return -1;
-	}
-
-	idx = strtol(argv[1], &e, 0);
-	if ((e && *e) || idx < 0 || idx > 255) {
-		fprintf(stderr, "Bad index.\n");
-		return -1;
-	}
-
-	p.index = idx;
-
-	rv = ec_command(EC_CMD_TMP006_GET_RAW, 0, &p, sizeof(p), &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	printf("T: %d.%02d K\n", r.t / 100, r.t % 100);
-	printf("V: %d nV\n", r.v);
-	return EC_SUCCESS;
-}
-
-static int cmd_hang_detect(int argc, char *argv[])
-{
-	struct ec_params_hang_detect req;
-	char *e;
-
-	memset(&req, 0, sizeof(req));
-
-	if (argc == 2 && !strcasecmp(argv[1], "stop")) {
-		req.flags = EC_HANG_STOP_NOW;
-		return ec_command(EC_CMD_HANG_DETECT, 0, &req, sizeof(req),
-				  NULL, 0);
-	}
-
-	if (argc == 2 && !strcasecmp(argv[1], "start")) {
-		req.flags = EC_HANG_START_NOW;
-		return ec_command(EC_CMD_HANG_DETECT, 0, &req, sizeof(req),
-				  NULL, 0);
-	}
-
-	if (argc == 4) {
-		req.flags = strtol(argv[1], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad flags.\n");
-			return -1;
-		}
-
-		req.host_event_timeout_msec = strtol(argv[2], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad event timeout.\n");
-			return -1;
-		}
-
-		req.warm_reboot_timeout_msec = strtol(argv[3], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad reboot timeout.\n");
-			return -1;
-		}
-
-		printf("hang flags=0x%x\n"
-		       "event_timeout=%d ms\n"
-		       "reboot_timeout=%d ms\n",
-		       req.flags, req.host_event_timeout_msec,
-		       req.warm_reboot_timeout_msec);
-
-		return ec_command(EC_CMD_HANG_DETECT, 0, &req, sizeof(req),
-				  NULL, 0);
-	}
-
-	fprintf(stderr,
-		"Must specify start/stop or <flags> <event_ms> <reboot_ms>\n");
-	return -1;
-}
-
-enum port_80_event {
-	PORT_80_EVENT_RESUME = 0x1001,  /* S3->S0 transition */
-	PORT_80_EVENT_RESET = 0x1002,   /* RESET transition */
-};
-
-int cmd_port80_read(int argc, char *argv[])
-{
-	struct ec_params_port80_read p;
-	int cmdver = 1, rv;
-	int i, head, tail;
-	uint16_t *history;
-	uint32_t writes, history_size;
-	struct ec_response_port80_read rsp;
-	int printed = 0;
-
-	if (!ec_cmd_version_supported(EC_CMD_PORT80_READ, cmdver)) {
-		/* fall back to last boot */
-		struct ec_response_port80_last_boot r;
-		rv = ec_command(EC_CMD_PORT80_LAST_BOOT, 0,
-				NULL, 0, &r, sizeof(r));
-		fprintf(stderr, "Last boot %2x\n", r.code);
-		printf("done.\n");
-		return 0;
-	}
-
-
-	/* read writes and history_size */
-	p.subcmd = EC_PORT80_GET_INFO;
-	rv = ec_command(EC_CMD_PORT80_READ, cmdver,
-			&p, sizeof(p), &rsp, sizeof(rsp));
-	if (rv < 0) {
-		fprintf(stderr, "Read error at writes\n");
-		return rv;
-	}
-	writes = rsp.get_info.writes;
-	history_size = rsp.get_info.history_size;
-
-	history = malloc(history_size*sizeof(uint16_t));
-	if (!history) {
-		fprintf(stderr, "Unable to allocate buffer.\n");
-		return -1;
-	}
-	/* As the history buffer is quite large, we read data in chunks, with
-	    size in bytes of EC_PORT80_SIZE_MAX in each chunk.
-	    Incrementing offset until all history buffer has been read. To
-	    simplify the design, chose HISTORY_LEN is always multiple of
-	    EC_PORT80_SIZE_MAX.
-
-	    offset: entry offset from the beginning of history buffer.
-	    num_entries: number of entries requested.
-	*/
-	p.subcmd = EC_PORT80_READ_BUFFER;
-	for (i = 0; i < history_size; i += EC_PORT80_SIZE_MAX) {
-		p.read_buffer.offset = i;
-		p.read_buffer.num_entries = EC_PORT80_SIZE_MAX;
-		rv = ec_command(EC_CMD_PORT80_READ, cmdver,
-				&p, sizeof(p), &rsp, sizeof(rsp));
-		if (rv < 0) {
-			fprintf(stderr, "Read error at offset %d\n", i);
-			free(history);
-			return rv;
-		}
-		memcpy((void *)(history + i), rsp.data.codes,
-			EC_PORT80_SIZE_MAX*sizeof(uint16_t));
-	}
-
-	head = writes;
-	if (head > history_size)
-		tail = head - history_size;
-	else
-		tail = 0;
-
-	fprintf(stderr, "Port 80 writes");
-	for (i = tail; i < head; i++) {
-		int e = history[i % history_size];
-		switch (e) {
-		case PORT_80_EVENT_RESUME:
-			fprintf(stderr, "\n(S3->S0)");
-			printed = 0;
-			break;
-		case PORT_80_EVENT_RESET:
-			fprintf(stderr, "\n(RESET)");
-			printed = 0;
-			break;
-		default:
-			if (!(printed++ % 20))
-				fprintf(stderr, "\n ");
-			fprintf(stderr, " %02x", e);
-		}
-	}
-	fprintf(stderr, " <--new\n");
-
-	free(history);
-	printf("done.\n");
-	return 0;
-}
-
-int cmd_force_lid_open(int argc, char *argv[])
-{
-	struct ec_params_force_lid_open p;
-	char *e;
-	int rv;
-
-	if (argc != 2) {
-		fprintf(stderr, "Usage: %s <0|1>\n", argv[0]);
-		return -1;
-	}
-	p.enabled = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad value.\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_FORCE_LID_OPEN, 0, &p, sizeof(p), NULL, 0);
-	if (rv < 0)
-		return rv;
-	printf("Success.\n");
-	return 0;
-}
-
-int cmd_charge_port_override(int argc, char *argv[])
-{
-	struct ec_params_charge_port_override p;
-	char *e;
-	int rv;
-
-	if (argc < 2) {
-		fprintf(stderr, "Usage: %s <port# | dontcharge | off>\n",
-			argv[0]);
-		return -1;
-	}
-
-	if (!strcasecmp(argv[1], "dontcharge"))
-		p.override_port = OVERRIDE_DONT_CHARGE;
-	else if (!strcasecmp(argv[1], "off"))
-		p.override_port = OVERRIDE_OFF;
-	else {
-		p.override_port = strtol(argv[1], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad parameter.\n");
-			return -1;
-		}
-	}
-
-	rv = ec_command(EC_CMD_PD_CHARGE_PORT_OVERRIDE, 0, &p, sizeof(p),
-			NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	printf("Override port set to %d\n", p.override_port);
-	return 0;
-}
-
-int cmd_pd_log(int argc, char *argv[])
-{
-	union {
-		struct ec_response_pd_log r;
-		uint32_t words[8]; /* space for the payload */
-	} u;
-	struct mcdp_info minfo;
-	struct ec_response_usb_pd_power_info pinfo;
-	int rv;
-	unsigned long long milliseconds;
-	unsigned seconds;
-	time_t now;
-	struct tm ltime;
-	char time_str[64];
-
-	while (1) {
-		now = time(NULL);
-		rv = ec_command(EC_CMD_PD_GET_LOG_ENTRY, 0,
-				NULL, 0, &u, sizeof(u));
-		if (rv < 0)
-			return rv;
-
-		if (u.r.type == PD_EVENT_NO_ENTRY) {
-			printf("--- END OF LOG ---\n");
-			break;
-		}
-
-		/* the timestamp is in 1024th of seconds */
-		milliseconds = ((uint64_t)u.r.timestamp <<
-					 PD_LOG_TIMESTAMP_SHIFT) / 1000;
-		/* the timestamp is the number of milliseconds in the past */
-		seconds = (milliseconds + 999) / 1000;
-		milliseconds -= seconds * 1000;
-		now -= seconds;
-		localtime_r(&now, &ltime);
-		strftime(time_str, sizeof(time_str), "%F %T", &ltime);
-		printf("%s.%03lld P%d ", time_str, -milliseconds,
-			PD_LOG_PORT(u.r.size_port));
-		if (u.r.type == PD_EVENT_MCU_CHARGE) {
-			if (u.r.data & CHARGE_FLAGS_OVERRIDE)
-				printf("override ");
-			if (u.r.data & CHARGE_FLAGS_DELAYED_OVERRIDE)
-				printf("pending_override ");
-			memcpy(&pinfo.meas, u.r.payload,
-				sizeof(struct usb_chg_measures));
-			pinfo.dualrole = !!(u.r.data & CHARGE_FLAGS_DUAL_ROLE);
-			pinfo.role = u.r.data & CHARGE_FLAGS_ROLE_MASK;
-			pinfo.type = (u.r.data & CHARGE_FLAGS_TYPE_MASK)
-					>> CHARGE_FLAGS_TYPE_SHIFT;
-			pinfo.max_power = 0;
-			print_pd_power_info(&pinfo);
-		} else if (u.r.type == PD_EVENT_MCU_CONNECT) {
-			printf("New connection\n");
-		} else if (u.r.type == PD_EVENT_MCU_BOARD_CUSTOM) {
-			printf("Board-custom event\n");
-		} else if (u.r.type == PD_EVENT_ACC_RW_FAIL) {
-			printf("RW signature check failed\n");
-		} else if (u.r.type == PD_EVENT_PS_FAULT) {
-			static const char * const fault_names[] = {
-				"---", "OCP", "fast OCP", "OVP", "Discharge"
-			};
-			const char *fault = u.r.data < ARRAY_SIZE(fault_names) ?
-					fault_names[u.r.data] : "???";
-			printf("Power supply fault: %s\n", fault);
-		} else if (u.r.type == PD_EVENT_VIDEO_DP_MODE) {
-			printf("DP mode %sabled\n", (u.r.data == 1) ?
-			       "en" : "dis");
-		} else if (u.r.type == PD_EVENT_VIDEO_CODEC) {
-			memcpy(&minfo, u.r.payload,
-			       sizeof(struct mcdp_info));
-			printf("HDMI info: family:%04x chipid:%04x "
-			       "irom:%d.%d.%d fw:%d.%d.%d\n",
-			       MCDP_FAMILY(minfo.family),
-			       MCDP_CHIPID(minfo.chipid),
-			       minfo.irom.major, minfo.irom.minor,
-			       minfo.irom.build, minfo.fw.major,
-			       minfo.fw.minor, minfo.fw.build);
-		} else { /* Unknown type */
-			int i;
-			printf("Event %02x (%04x) [", u.r.type, u.r.data);
-			for (i = 0; i < PD_LOG_SIZE(u.r.size_port); i++)
-				printf("%02x ", u.r.payload[i]);
-			printf("]\n");
-		}
-	}
-
-	return 0;
-}
-
-int cmd_pd_control(int argc, char *argv[])
-{
-	struct ec_params_pd_control p;
-	int rv;
-
-	if (argc < 2) {
-		fprintf(stderr, "Missing parameter\n");
-		return -1;
-	}
-
-	/* Parse command */
-	if (!strcmp(argv[1], "reset"))
-		p.subcmd = PD_RESET;
-	else if (!strcmp(argv[1], "suspend"))
-		p.subcmd = PD_SUSPEND;
-	else if (!strcmp(argv[1], "resume"))
-		p.subcmd = PD_RESUME;
-	else if (!strcmp(argv[1], "disable"))
-		p.subcmd = PD_CONTROL_DISABLE;
-	else if (!strcmp(argv[1], "on") || !strcmp(argv[1], "chip_on"))
-		p.subcmd = PD_CHIP_ON;
-	else {
-		fprintf(stderr, "Unknown command: %s\n", argv[1]);
-		return -1;
-	}
-
-	if (argc == 2) {
-		p.chip = 0;
-	} else {
-		char *e;
-		p.chip = strtol(argv[2], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad port number '%s'.\n", argv[2]);
-			return -1;
-		}
-	}
-
-	rv = ec_command(EC_CMD_PD_CONTROL, 0, &p, sizeof(p), NULL, 0);
-	return (rv < 0 ? rv : 0);
-}
-
-int cmd_pd_chip_info(int argc, char *argv[])
-{
-	struct ec_params_pd_chip_info p;
-	struct ec_response_pd_chip_info_v1 r;
-	char *e;
-	int rv;
-	int cmdver = 1;
-
-	if (argc < 2 || 3 < argc) {
-		fprintf(stderr, "Usage: %s <port> [<live>]\n"
-			"live parameter can take values 0 or 1\n"
-			"0 -> Return hard-coded value for VID/PID and\n"
-			"     cached value for Firmware Version\n"
-			"1 -> Return live chip value for VID/PID/FW Version\n",
-			argv[0]);
-		return -1;
-	}
-
-	p.port = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad port number.\n");
-		return -1;
-	}
-
-	p.live = 0;
-	if (argc == 3) {
-		p.live = strtol(argv[2], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "invalid arg \"%s\"\n", argv[2]);
-			return -1;
-		}
-	}
-
-	if (!ec_cmd_version_supported(EC_CMD_PD_CHIP_INFO, cmdver))
-		cmdver = 0;
-
-	rv = ec_command(EC_CMD_PD_CHIP_INFO, cmdver, &p, sizeof(p), &r,
-			sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	printf("vendor_id: 0x%x\n", r.vendor_id);
-	printf("product_id: 0x%x\n", r.product_id);
-	printf("device_id: 0x%x\n", r.device_id);
-
-	if (r.fw_version_number != -1)
-		printf("fw_version: 0x%" PRIx64 "\n", r.fw_version_number);
-	else
-		printf("fw_version: UNSUPPORTED\n");
-
-	if (cmdver >= 1)
-		printf("min_req_fw_version: 0x%" PRIx64 "\n",
-		       r.min_req_fw_version_number);
-	else
-		printf("min_req_fw_version: UNSUPPORTED\n");
-
-	return 0;
-}
-
-int cmd_pd_write_log(int argc, char *argv[])
-{
-	struct ec_params_pd_write_log_entry p;
-	char *e;
-
-	if (argc < 3) {
-		fprintf(stderr, "Usage: %s <log_type> <port>\n",
-			argv[0]);
-		return -1;
-	}
-
-	if (!strcasecmp(argv[1], "charge"))
-		p.type = PD_EVENT_MCU_CHARGE;
-	else {
-		p.type = strtol(argv[1], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad log_type parameter.\n");
-			return -1;
-		}
-	}
-
-	p.port = strtol(argv[2], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad port parameter.\n");
-		return -1;
-	}
-
-	return ec_command(EC_CMD_PD_WRITE_LOG_ENTRY, 0, &p, sizeof(p), NULL, 0);
-}
-
-int cmd_typec_control(int argc, char *argv[])
-{
-	struct ec_params_typec_control p;
-	char *endptr;
-	int rv;
-
-	if (argc < 3) {
-		fprintf(stderr,
-			"Usage: %s <port> <command> [args]\n"
-			"  <port> is the type-c port to query\n"
-			"  <type> is one of:\n"
-			"    0: Exit modes\n"
-			"    1: Clear events\n", argv[0]);
-		return -1;
-	}
-
-	p.port = strtol(argv[1], &endptr, 0);
-	if (endptr && *endptr) {
-		fprintf(stderr, "Bad port\n");
-		return -1;
-	}
-
-	p.command = strtol(argv[2], &endptr, 0);
-	if (endptr && *endptr) {
-		fprintf(stderr, "Bad command\n");
-		return -1;
-	}
-
-	if (p.command == TYPEC_CONTROL_COMMAND_CLEAR_EVENTS) {
-		if (argc < 4) {
-			fprintf(stderr, "Missing event mask\n");
-			return -1;
-		}
-
-		p.clear_events_mask = strtol(argv[3], &endptr, 0);
-		if (endptr && *endptr) {
-			fprintf(stderr, "Bad event mask\n");
-			return -1;
-		}
-	}
-
-	rv = ec_command(EC_CMD_TYPEC_CONTROL, 0, &p, sizeof(p),
-			ec_inbuf, ec_max_insize);
-	if (rv < 0)
-		return -1;
-
-	return 0;
-}
-
-int cmd_typec_discovery(int argc, char *argv[])
-{
-	struct ec_params_typec_discovery p;
-	struct ec_response_typec_discovery *r =
-				(struct ec_response_typec_discovery *)ec_inbuf;
-	char *e;
-	int rv, i, j;
-
-	if (argc < 3) {
-		fprintf(stderr,
-			"Usage: %s <port> <type>\n"
-			"  <port> is the type-c port to query\n"
-			"  <type> is one of:\n"
-			"    0: SOP\n"
-			"    1: SOP prime\n", argv[0]);
-		return -1;
-	}
-
-	p.port = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad port\n");
-		return -1;
-	}
-
-	p.partner_type = strtol(argv[2], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad type\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_TYPEC_DISCOVERY, 0, &p, sizeof(p),
-			ec_inbuf, ec_max_insize);
-	if (rv < 0)
-		return -1;
-
-	if (r->identity_count == 0) {
-		printf("No identity discovered\n");
-		return 0;
-	}
-
-	printf("Identity VDOs:\n");
-	for (i = 0; i < r->identity_count; i++)
-		printf("0x%08x\n", r->discovery_vdo[i]);
-
-	if (r->svid_count == 0) {
-		printf("No SVIDs discovered\n");
-		return 0;
-	}
-
-	for (i = 0; i < r->svid_count; i++) {
-		printf("SVID 0x%04x Modes:\n", r->svids[i].svid);
-		for (j = 0; j < r->svids[i].mode_count; j++)
-			printf("0x%08x\n", r->svids[i].mode_vdo[j]);
-	}
-
-	return 0;
-}
-
-int cmd_typec_status(int argc, char *argv[])
-{
-	struct ec_params_typec_status p;
-	struct ec_response_typec_status *r =
-				(struct ec_response_typec_status *)ec_inbuf;
-	char *endptr;
-	int rv;
-	char *desc;
-
-	if (argc != 2) {
-		fprintf(stderr,
-			"Usage: %s <port>\n"
-			"  <port> is the type-c port to query\n", argv[0]);
-		return -1;
-	}
-
-	p.port = strtol(argv[1], &endptr, 0);
-	if (endptr && *endptr) {
-		fprintf(stderr, "Bad port\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_TYPEC_STATUS, 0, &p, sizeof(p),
-			ec_inbuf, ec_max_insize);
-	if (rv == -EC_RES_INVALID_COMMAND - EECRESULT)
-		/* Fall back to PD_CONTROL to support older ECs */
-		return cmd_usb_pd(argc, argv);
-	else if (rv < 0)
-		return -1;
-
-	printf("Port C%d: %s, %s  State:%s\n"
-	       "Role:%s %s%s, Polarity:CC%d\n",
-		p.port,
-		r->pd_enabled ? "enabled" : "disabled",
-		r->dev_connected ? "connected" : "disconnected",
-		r->tc_state,
-		(r->power_role == PD_ROLE_SOURCE) ? "SRC" : "SNK",
-		(r->data_role == PD_ROLE_DFP) ? "DFP" :
-			(r->data_role == PD_ROLE_UFP) ? "UFP" : "",
-		(r->vconn_role == PD_ROLE_VCONN_SRC) ? " VCONN" : "",
-		(r->polarity % 2 + 1));
-
-	switch (r->cc_state) {
-	case PD_CC_NONE:
-		desc = "None";
-		break;
-	case PD_CC_UFP_AUDIO_ACC:
-		desc = "UFP Audio accessory";
-		break;
-	case PD_CC_UFP_DEBUG_ACC:
-		desc = "UFP Debug accessory";
-		break;
-	case PD_CC_UFP_ATTACHED:
-		desc = "UFP attached";
-		break;
-	case PD_CC_DFP_DEBUG_ACC:
-		desc = "DFP Debug accessory";
-		break;
-	case PD_CC_DFP_ATTACHED:
-		desc = "DFP attached";
-		break;
-	default:
-		desc = "UNKNOWN";
-		break;
-	}
-	printf("CC State: %s\n", desc);
-
-	if (r->dp_pin) {
-		switch (r->dp_pin) {
-		case MODE_DP_PIN_A:
-			desc = "A";
-			break;
-		case MODE_DP_PIN_B:
-			desc = "B";
-			break;
-		case MODE_DP_PIN_C:
-			desc = "C";
-			break;
-		case MODE_DP_PIN_D:
-			desc = "D";
-			break;
-		case MODE_DP_PIN_E:
-			desc = "E";
-			break;
-		case MODE_DP_PIN_F:
-			desc = "F";
-			break;
-		default:
-			desc = "UNKNOWN";
-			break;
-		}
-		printf("DP pin mode: %s\n", desc);
-	}
-
-	if (r->mux_state) {
-		printf("MUX: USB=%d DP=%d POLARITY=%s HPD_IRQ=%d HPD_LVL=%d\n"
-		       "     SAFE=%d TBT=%d USB4=%d\n",
-		       !!(r->mux_state & USB_PD_MUX_USB_ENABLED),
-		       !!(r->mux_state & USB_PD_MUX_DP_ENABLED),
-			(r->mux_state & USB_PD_MUX_POLARITY_INVERTED) ?
-						"INVERTED" : "NORMAL",
-		       !!(r->mux_state & USB_PD_MUX_HPD_IRQ),
-		       !!(r->mux_state & USB_PD_MUX_HPD_LVL),
-		       !!(r->mux_state & USB_PD_MUX_SAFE_MODE),
-		       !!(r->mux_state & USB_PD_MUX_TBT_COMPAT_ENABLED),
-		       !!(r->mux_state & USB_PD_MUX_USB4_ENABLED));
-	}
-
-	printf("Port events: 0x%08x\n", r->events);
-
-	return 0;
-}
-
-int cmd_tp_self_test(int argc, char* argv[])
-{
-	int rv;
-
-	rv = ec_command(EC_CMD_TP_SELF_TEST, 0, NULL, 0, NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	printf("Touchpad self test: %s\n",
-	       rv == EC_RES_SUCCESS ? "passed" : "failed");
-
-	return rv;
-}
-
-int cmd_tp_frame_get(int argc, char* argv[])
-{
-	int i, j;
-	uint32_t remaining = 0, offset = 0;
-	int rv = EC_SUCCESS;
-	uint8_t *data;
-	struct ec_response_tp_frame_info* r;
-	struct ec_params_tp_frame_get p;
-
-	data = malloc(ec_max_insize);
-	r = malloc(ec_max_insize);
-
-	if (data == NULL || r == NULL) {
-		fprintf(stderr, "Couldn't allocate memory.\n");
-		free(r);
-		free(data);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	rv = ec_command(EC_CMD_TP_FRAME_INFO, 0, NULL, 0, r, ec_max_insize);
-	if (rv < 0) {
-		fprintf(stderr, "Failed to get touchpad frame info.\n");
-		goto err;
-	}
-
-	rv = ec_command(EC_CMD_TP_FRAME_SNAPSHOT, 0, NULL, 0, NULL, 0);
-	if (rv < 0) {
-		fprintf(stderr, "Failed to snapshot frame.\n");
-		goto err;
-	}
-
-	for (i = 0; i < r->n_frames; i++) {
-		p.frame_index = i;
-		offset = 0;
-		remaining = r->frame_sizes[i];
-
-		while (remaining > 0) {
-			p.offset = offset;
-			p.size = MIN(remaining, ec_max_insize);
-
-			rv = ec_command(EC_CMD_TP_FRAME_GET, 0,
-					&p, sizeof(p), data, p.size);
-			if (rv < 0) {
-				fprintf(stderr, "Failed to get frame data "
-						"at offset 0x%x\n", offset);
-				goto err;
-			}
-
-			for (j = 0; j < p.size; j++)
-				printf("%02x ", data[j]);
-
-			offset += p.size;
-			remaining -= p.size;
-		}
-		printf("\n");
-	}
-
-err:
-	free(data);
-	free(r);
-
-	return rv < 0;
-}
-
-static int wait_event(long event_type,
-		      struct ec_response_get_next_event_v1 *buffer,
-		      size_t buffer_size, long timeout)
-{
-	int rv;
-
-	rv = ec_pollevent(1 << event_type, buffer, buffer_size, timeout);
-	if (rv == 0) {
-		fprintf(stderr, "Timeout waiting for MKBP event\n");
-		return -ETIMEDOUT;
-	} else if (rv < 0) {
-		perror("Error polling for MKBP event\n");
-		return -EIO;
-	}
-
-	return rv;
-}
-
-int cmd_wait_event(int argc, char *argv[])
-{
-	int rv, i;
-	struct ec_response_get_next_event_v1 buffer;
-	long timeout = 5000;
-	long event_type;
-	char *e;
-
-	if (!ec_pollevent) {
-		fprintf(stderr, "Polling for MKBP event not supported\n");
-		return -EINVAL;
-	}
-
-	if (argc < 2) {
-		fprintf(stderr, "Usage: %s <type> [<timeout>]\n",
-			argv[0]);
-		return -1;
-	}
-
-	event_type = strtol(argv[1], &e, 0);
-	if ((e && *e) || event_type < 0 || event_type >= EC_MKBP_EVENT_COUNT) {
-		fprintf(stderr, "Bad event type '%s'.\n", argv[1]);
-		return -1;
-	}
-	if (argc >= 3) {
-		timeout = strtol(argv[2], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad timeout value '%s'.\n", argv[2]);
-			return -1;
-		}
-	}
-
-	rv = wait_event(event_type, &buffer, sizeof(buffer), timeout);
-	if (rv < 0)
-		return rv;
-
-	printf("MKBP event %d data: ", buffer.event_type);
-	for (i = 0; i < rv - 1; ++i)
-		printf("%02x ", buffer.data.key_matrix[i]);
-	printf("\n");
-
-	return 0;
-}
-
-static void cmd_cec_help(const char *cmd)
-{
-	fprintf(stderr,
-		"  Usage: %s write [write bytes...]\n"
-		"    Write message on the CEC bus\n"
-		"  Usage: %s read [timeout]\n"
-		"    [timeout] in seconds\n"
-		"  Usage: %s get <param>\n"
-		"  Usage: %s set <param> <val>\n"
-		"    <param> is one of:\n"
-		"      address: CEC receive address\n"
-		"        <val> is the new CEC address\n"
-		"      enable: Enable or disable CEC\n"
-		"        <val> is 1 to enable, 0 to disable\n",
-		cmd, cmd, cmd, cmd);
-
-}
-
-static int cmd_cec_write(int argc, char *argv[])
-{
-	char *e;
-	long val;
-	int rv, i, msg_len;
-	struct ec_params_cec_write p;
-	struct ec_response_get_next_event_v1 buffer;
-
-	if (argc < 3 || argc > 18) {
-		fprintf(stderr, "Invalid number of params\n");
-		cmd_cec_help(argv[0]);
-		return -1;
-	}
-
-	msg_len = argc - 2;
-	for (i = 0; i < msg_len; i++) {
-		val = strtol(argv[i + 2], &e, 16);
-		if (e && *e)
-			return -1;
-		if (val < 0 || val > 0xff)
-			return -1;
-		p.msg[i] = (uint8_t)val;
-	}
-
-	printf("Write to CEC: ");
-	for (i = 0; i < msg_len; i++)
-		printf("0x%02x ", p.msg[i]);
-	printf("\n");
-
-	rv = ec_command(EC_CMD_CEC_WRITE_MSG, 0, &p, msg_len, NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	rv = wait_event(EC_MKBP_EVENT_CEC_EVENT, &buffer, sizeof(buffer), 1000);
-	if (rv < 0)
-		return rv;
-
-	if (buffer.data.cec_events & EC_MKBP_CEC_SEND_OK)
-		return 0;
-
-	if (buffer.data.cec_events & EC_MKBP_CEC_SEND_FAILED) {
-		fprintf(stderr, "Send failed\n");
-		return -1;
-	}
-
-	fprintf(stderr, "No send result received\n");
-
-	return -1;
-}
-
-static int cmd_cec_read(int argc, char *argv[])
-{
-	int i, rv;
-	char *e;
-	struct ec_response_get_next_event_v1 buffer;
-	long timeout = 5000;
-
-	if (!ec_pollevent) {
-		fprintf(stderr, "Polling for MKBP event not supported\n");
-		return -EINVAL;
-	}
-
-	if (argc >= 3) {
-		timeout = strtol(argv[2], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad timeout value '%s'.\n", argv[2]);
-			return -1;
-		}
-	}
-
-	rv = wait_event(EC_MKBP_EVENT_CEC_MESSAGE, &buffer,
-			sizeof(buffer), timeout);
-	if (rv < 0)
-		return rv;
-
-	printf("CEC data: ");
-	for (i = 0; i < rv - 1; i++)
-		printf("0x%02x ", buffer.data.cec_message[i]);
-	printf("\n");
-
-	return 0;
-}
-
-static int cec_cmd_from_str(const char *str)
-{
-	if (!strcmp("address", str))
-		return CEC_CMD_LOGICAL_ADDRESS;
-	if (!strcmp("enable", str))
-		return CEC_CMD_ENABLE;
-	return -1;
-}
-
-static int cmd_cec_set(int argc, char *argv[])
-{
-	char *e;
-	struct ec_params_cec_set p;
-	uint8_t val;
-	int cmd;
-
-	if (argc != 4) {
-		fprintf(stderr, "Invalid number of params\n");
-		cmd_cec_help(argv[0]);
-		return -1;
-	}
-
-	val = (uint8_t)strtol(argv[3], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad parameter '%s'.\n", argv[3]);
-		return -1;
-	}
-
-	cmd = cec_cmd_from_str(argv[2]);
-	if (cmd < 0) {
-		fprintf(stderr, "Invalid command '%s'.\n", argv[2]);
-		return -1;
-	}
-	p.cmd = cmd;
-	p.val = val;
-
-	return ec_command(EC_CMD_CEC_SET,
-			  0, &p, sizeof(p), NULL, 0);
-}
-
-
-static int cmd_cec_get(int argc, char *argv[])
-{
-	int rv, cmd;
-	struct ec_params_cec_get p;
-	struct ec_response_cec_get r;
-
-
-	if (argc != 3) {
-		fprintf(stderr, "Invalid number of params\n");
-		cmd_cec_help(argv[0]);
-		return -1;
-	}
-
-	cmd = cec_cmd_from_str(argv[2]);
-	if (cmd < 0) {
-		fprintf(stderr, "Invalid command '%s'.\n", argv[2]);
-		return -1;
-	}
-	p.cmd = cmd;
-
-
-	rv = ec_command(EC_CMD_CEC_GET, 0, &p, sizeof(p), &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	printf("%d\n", r.val);
-
-	return 0;
-}
-
-int cmd_cec(int argc, char *argv[])
-{
-	if (argc < 2) {
-		fprintf(stderr, "Invalid number of params\n");
-		cmd_cec_help(argv[0]);
-		return -1;
-	}
-	if (!strcmp(argv[1], "write"))
-		return cmd_cec_write(argc, argv);
-	if (!strcmp(argv[1], "read"))
-		return cmd_cec_read(argc, argv);
-	if (!strcmp(argv[1], "get"))
-		return cmd_cec_get(argc, argv);
-	if (!strcmp(argv[1], "set"))
-		return cmd_cec_set(argc, argv);
-
-	fprintf(stderr, "Invalid sub command: %s\n", argv[1]);
-	cmd_cec_help(argv[0]);
-
-	return -1;
-}
-
-/* NULL-terminated list of commands */
-const struct command commands[] = {
-	{"adcread", cmd_adc_read},
-	{"addentropy", cmd_add_entropy},
-	{"apreset", cmd_apreset},
-	{"autofanctrl", cmd_thermal_auto_fan_ctrl},
-	{"backlight", cmd_lcd_backlight},
-	{"battery", cmd_battery},
-	{"batterycutoff", cmd_battery_cut_off},
-	{"batteryparam", cmd_battery_vendor_param},
-	{"boardversion", cmd_board_version},
-	{"button", cmd_button},
-	{"cbi", cmd_cbi},
-	{"chargecurrentlimit", cmd_charge_current_limit},
-	{"chargecontrol", cmd_charge_control},
-	{"chargeoverride", cmd_charge_port_override},
-	{"chargestate", cmd_charge_state},
-	{"chipinfo", cmd_chipinfo},
-	{"cmdversions", cmd_cmdversions},
-	{"console", cmd_console},
-	{"cec", cmd_cec},
-	{"echash", cmd_ec_hash},
-	{"eventclear", cmd_host_event_clear},
-	{"eventclearb", cmd_host_event_clear_b},
-	{"eventget", cmd_host_event_get_raw},
-	{"eventgetb", cmd_host_event_get_b},
-	{"eventgetscimask", cmd_host_event_get_sci_mask},
-	{"eventgetsmimask", cmd_host_event_get_smi_mask},
-	{"eventgetwakemask", cmd_host_event_get_wake_mask},
-	{"eventsetscimask", cmd_host_event_set_sci_mask},
-	{"eventsetsmimask", cmd_host_event_set_smi_mask},
-	{"eventsetwakemask", cmd_host_event_set_wake_mask},
-	{"extpwrlimit", cmd_ext_power_limit},
-	{"fanduty", cmd_fanduty},
-	{"flasherase", cmd_flash_erase},
-	{"flasheraseasync", cmd_flash_erase},
-	{"flashprotect", cmd_flash_protect},
-	{"flashread", cmd_flash_read},
-	{"flashwrite", cmd_flash_write},
-	{"flashinfo", cmd_flash_info},
-	{"flashspiinfo", cmd_flash_spi_info},
-	{"flashpd", cmd_flash_pd},
-	{"forcelidopen", cmd_force_lid_open},
-	{"fpcontext", cmd_fp_context},
-	{"fpencstatus", cmd_fp_enc_status},
-	{"fpframe", cmd_fp_frame},
-	{"fpinfo", cmd_fp_info},
-	{"fpmode", cmd_fp_mode},
-	{"fpseed", cmd_fp_seed},
-	{"fpstats", cmd_fp_stats},
-	{"fptemplate", cmd_fp_template},
-	{"gpioget", cmd_gpio_get},
-	{"gpioset", cmd_gpio_set},
-	{"hangdetect", cmd_hang_detect},
-	{"hello", cmd_hello},
-	{"hibdelay", cmd_hibdelay},
-	{"hostevent", cmd_hostevent},
-	{"hostsleepstate", cmd_hostsleepstate},
-	{"locatechip", cmd_locate_chip},
-	{"i2cprotect", cmd_i2c_protect},
-	{"i2cread", cmd_i2c_read},
-	{"i2cwrite", cmd_i2c_write},
-	{"i2cxfer", cmd_i2c_xfer},
-	{"infopddev", cmd_pd_device_info},
-	{"inventory", cmd_inventory},
-	{"led", cmd_led},
-	{"lightbar", cmd_lightbar},
-	{"kbfactorytest", cmd_keyboard_factory_test},
-	{"kbid", cmd_kbid},
-	{"kbinfo", cmd_kbinfo},
-	{"kbpress", cmd_kbpress},
-	{"keyconfig", cmd_keyconfig},
-	{"keyscan", cmd_keyscan},
-	{"mkbpget", cmd_mkbp_get},
-	{"mkbpwakemask", cmd_mkbp_wake_mask},
-	{"motionsense", cmd_motionsense},
-	{"nextevent", cmd_next_event},
-	{"panicinfo", cmd_panic_info},
-	{"pause_in_s5", cmd_s5},
-	{"pdgetmode", cmd_pd_get_amode},
-	{"pdsetmode", cmd_pd_set_amode},
-	{"port80read", cmd_port80_read},
-	{"pdlog", cmd_pd_log},
-	{"pdcontrol", cmd_pd_control},
-	{"pdchipinfo", cmd_pd_chip_info},
-	{"pdwritelog", cmd_pd_write_log},
-	{"powerinfo", cmd_power_info},
-	{"protoinfo", cmd_proto_info},
-	{"pse", cmd_pse},
-	{"pstoreinfo", cmd_pstore_info},
-	{"pstoreread", cmd_pstore_read},
-	{"pstorewrite", cmd_pstore_write},
-	{"pwmgetfanrpm", cmd_pwm_get_fan_rpm},
-	{"pwmgetkblight", cmd_pwm_get_keyboard_backlight},
-	{"pwmgetnumfans", cmd_pwm_get_num_fans},
-	{"pwmgetduty", cmd_pwm_get_duty},
-	{"pwmsetfanrpm", cmd_pwm_set_fan_rpm},
-	{"pwmsetkblight", cmd_pwm_set_keyboard_backlight},
-	{"pwmsetduty", cmd_pwm_set_duty},
-	{"rand", cmd_rand},
-	{"readtest", cmd_read_test},
-	{"reboot_ec", cmd_reboot_ec},
-	{"rollbackinfo", cmd_rollback_info},
-	{"rtcget", cmd_rtc_get},
-	{"rtcgetalarm", cmd_rtc_get_alarm},
-	{"rtcset", cmd_rtc_set},
-	{"rtcsetalarm", cmd_rtc_set_alarm},
-	{"rwhashpd", cmd_rw_hash_pd},
-	{"rwsig", cmd_rwsig},
-	{"rwsigaction", cmd_rwsig_action_legacy},
-	{"rwsigstatus", cmd_rwsig_status},
-	{"sertest", cmd_serial_test},
-	{"smartdischarge", cmd_smart_discharge},
-	{"stress", cmd_stress_test},
-	{"sysinfo", cmd_sysinfo},
-	{"port80flood", cmd_port_80_flood},
-	{"switches", cmd_switches},
-	{"temps", cmd_temperature},
-	{"tempsinfo", cmd_temp_sensor_info},
-	{"test", cmd_test},
-	{"thermalget", cmd_thermal_get_threshold},
-	{"thermalset", cmd_thermal_set_threshold},
-	{"tpselftest", cmd_tp_self_test},
-	{"tpframeget", cmd_tp_frame_get},
-	{"tmp006cal", cmd_tmp006cal},
-	{"tmp006raw", cmd_tmp006raw},
-	{"typeccontrol", cmd_typec_control},
-	{"typecdiscovery", cmd_typec_discovery},
-	{"typecstatus", cmd_typec_status},
-	{"uptimeinfo", cmd_uptimeinfo},
-	{"usbchargemode", cmd_usb_charge_set_mode},
-	{"usbmux", cmd_usb_mux},
-	{"usbpd", cmd_usb_pd},
-	{"usbpdmuxinfo", cmd_usb_pd_mux_info},
-	{"usbpdpower", cmd_usb_pd_power},
-	{"version", cmd_version},
-	{"waitevent", cmd_wait_event},
-	{"wireless", cmd_wireless},
-	{"reboot_ap_on_g3", cmd_reboot_ap_on_g3},
-	{NULL, NULL}
-};
-
-int main(int argc, char *argv[])
-{
-	const struct command *cmd;
-	int dev = 0;
-	int interfaces = COMM_ALL;
-	int i2c_bus = -1;
-	char device_name[41] = CROS_EC_DEV_NAME;
-	int rv = 1;
-	int parse_error = 0;
-	char *e;
-	int i;
-
-	BUILD_ASSERT(ARRAY_SIZE(lb_command_paramcount) == LIGHTBAR_NUM_CMDS);
-
-	while ((i = getopt_long(argc, argv, "?", long_opts, NULL)) != -1) {
-		switch (i) {
-		case '?':
-			/* Unhandled option */
-			parse_error = 1;
-			break;
-
-		case OPT_DEV:
-			dev = strtoul(optarg, &e, 0);
-			if (!*optarg || (e && *e)) {
-				fprintf(stderr, "Invalid --dev\n");
-				parse_error = 1;
-			}
-			break;
-
-		case OPT_INTERFACE:
-			if (!strcasecmp(optarg, "dev")) {
-				interfaces = COMM_DEV;
-			} else if (!strcasecmp(optarg, "lpc")) {
-				interfaces = COMM_LPC;
-			} else if (!strcasecmp(optarg, "i2c")) {
-				interfaces = COMM_I2C;
-			} else if (!strcasecmp(optarg, "servo")) {
-				interfaces = COMM_SERVO;
-			} else {
-				fprintf(stderr, "Invalid --interface\n");
-				parse_error = 1;
-			}
-			break;
-		case OPT_NAME:
-			strncpy(device_name, optarg, 40);
-			device_name[40] = '\0';
-			break;
-		case OPT_I2C_BUS:
-			i2c_bus = strtoul(optarg, &e, 0);
-			if (*optarg == '\0' || (e && *e != '\0')
-			    || i2c_bus < 0) {
-				fprintf(stderr, "Invalid --i2c_bus\n");
-				parse_error = 1;
-			}
-			break;
-		case OPT_ASCII:
-			ascii_mode = 1;
-			break;
-		}
-	}
-
-	if (i2c_bus != -1)  {
-		if (!(interfaces & COMM_I2C)) {
-			fprintf(stderr, "--i2c_bus is specified, but --interface is set to something other than I2C\n");
-			parse_error = 1;
-		} else {
-			interfaces = COMM_I2C;
-		}
-	}
-
-	/* Must specify a command */
-	if (!parse_error && optind == argc)
-		parse_error = 1;
-
-	/* 'ectool help' prints help with commands */
-	if (!parse_error && !strcasecmp(argv[optind], "help")) {
-		print_help(argv[0], 1);
-		exit(1);
-	}
-
-	/* Handle sub-devices command offset */
-	if (dev > 0 && dev < 4) {
-		set_command_offset(EC_CMD_PASSTHRU_OFFSET(dev));
-	} else if (dev == 8) {
-		/* Special offset for Fingerprint MCU */
-		strcpy(device_name, "cros_fp");
-	} else if (dev != 0) {
-		fprintf(stderr, "Bad device number %d\n", dev);
-		parse_error = 1;
-	}
-
-	if (parse_error) {
-		print_help(argv[0], 0);
-		exit(1);
-	}
-
-	/* Prefer /dev method, which supports built-in mutex */
-	if (!(interfaces & COMM_DEV) || comm_init_dev(device_name)) {
-		/* If dev is excluded or isn't supported, find alternative */
-		if (acquire_gec_lock(GEC_LOCK_TIMEOUT_SECS) < 0) {
-			fprintf(stderr, "Could not acquire GEC lock.\n");
-			exit(1);
-		}
-		if (comm_init_alt(interfaces, device_name, i2c_bus)) {
-			fprintf(stderr, "Couldn't find EC\n");
-			goto out;
-		}
-	}
-
-	if (comm_init_buffer()) {
-		fprintf(stderr, "Couldn't initialize buffers\n");
-		goto out;
-	}
-
-	/* Handle commands */
-	for (cmd = commands; cmd->name; cmd++) {
-		if (!strcasecmp(argv[optind], cmd->name)) {
-			rv = cmd->handler(argc - optind, argv + optind);
-			goto out;
-		}
-	}
-
-	/* If we're still here, command was unknown */
-	fprintf(stderr, "Unknown command '%s'\n\n", argv[optind]);
-	print_help(argv[0], 0);
-
-out:
-	release_gec_lock();
-	return !!rv;
-}
diff --git a/util/ectool.cc b/util/ectool.cc
new file mode 100644
index 0000000000..cd37abc0eb
--- /dev/null
+++ b/util/ectool.cc
@@ -0,0 +1,11758 @@
+/* Copyright 2013 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "chipset.h"
+#include "comm-host.h"
+#include "comm-usb.h"
+#include "compile_time_macros.h"
+#include "crc.h"
+#include "cros_ec_dev.h"
+#include "ec_flash.h"
+#include "ec_version.h"
+#include "ectool.h"
+#include "i2c.h"
+#include "lightbar.h"
+#include "lock/gec_lock.h"
+#include "misc_util.h"
+#include "panic.h"
+#include "tablet_mode.h"
+#include "usb_pd.h"
+
+#include <assert.h>
+#include <ctype.h>
+#include <errno.h>
+#include <inttypes.h>
+#include <signal.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <time.h>
+
+#include <getopt.h>
+#include <libec/add_entropy_command.h>
+#include <libec/ec_panicinfo.h>
+#include <libec/fingerprint/fp_encryption_status_command.h>
+#include <libec/flash_protect_command.h>
+#include <libec/rand_num_command.h>
+#include <unistd.h>
+#include <vector>
+
+/* Maximum flash size (16 MB, conservative) */
+#define MAX_FLASH_SIZE 0x1000000
+
+/*
+ * Calculate the expected response for a hello ec command.
+ */
+#define HELLO_RESP(in_data) ((in_data) + 0x01020304)
+
+#define USB_VID_GOOGLE 0x18d1
+#define USB_PID_HAMMER 0x5022
+
+/* Command line options */
+enum {
+	OPT_DEV = 1000,
+	OPT_INTERFACE,
+	OPT_NAME,
+	OPT_ASCII,
+	OPT_I2C_BUS,
+	OPT_DEVICE,
+};
+
+static struct option long_opts[] = { { "dev", 1, 0, OPT_DEV },
+				     { "interface", 1, 0, OPT_INTERFACE },
+				     { "name", 1, 0, OPT_NAME },
+				     { "ascii", 0, 0, OPT_ASCII },
+				     { "i2c_bus", 1, 0, OPT_I2C_BUS },
+				     { "device", 1, 0, OPT_DEVICE },
+				     { NULL, 0, 0, 0 } };
+
+#define GEC_LOCK_TIMEOUT_SECS 30 /* 30 secs */
+
+const char help_str[] =
+	"Commands:\n"
+	"  adcread <channel>\n"
+	"      Read an ADC channel.\n"
+	"  addentropy [reset]\n"
+	"      Add entropy to device secret\n"
+	"  apreset\n"
+	"      Issue AP reset\n"
+	"  autofanctrl <on>\n"
+	"      Turn on automatic fan speed control.\n"
+	"  backlight <enabled>\n"
+	"      Enable/disable LCD backlight\n"
+	"  basestate [attach | detach | reset]\n"
+	"      Manually force base state to attached, detached or reset.\n"
+	"  battery\n"
+	"      Prints battery info\n"
+	"  batterycutoff [at-shutdown]\n"
+	"      Cut off battery output power\n"
+	"  batteryparam\n"
+	"      Read or write board-specific battery parameter\n"
+	"  boardversion\n"
+	"      Prints the board version\n"
+	"  button [vup|vdown|rec] <Delay-ms>\n"
+	"      Simulates button press.\n"
+	"  cbi\n"
+	"      Get/Set/Remove Cros Board Info\n"
+	"  chargecurrentlimit\n"
+	"    Set the maximum battery charging current and the minimum battery\n"
+	"    SoC at which it will apply.\n"
+	"  chargecontrol\n"
+	"      Force the battery to stop charging or discharge\n"
+	"  chargeoverride\n"
+	"      Overrides charge port selection logic\n"
+	"  chargesplash\n"
+	"      Show and manipulate chargesplash variables\n"
+	"  chargestate\n"
+	"      Handle commands related to charge state v2 (and later)\n"
+	"  chipinfo\n"
+	"      Prints chip info\n"
+	"  cmdversions <cmd>\n"
+	"      Prints supported version mask for a command number\n"
+	"  console\n"
+	"      Prints the last output to the EC debug console\n"
+	"  cec\n"
+	"      Read or write CEC messages and settings\n"
+	"  echash [CMDS]\n"
+	"      Various EC hash commands\n"
+	"  eventclear <mask>\n"
+	"      Clears EC host events flags where mask has bits set\n"
+	"  eventclearb <mask>\n"
+	"      Clears EC host events flags copy B where mask has bits set\n"
+	"  eventget\n"
+	"      Prints raw EC host event flags\n"
+	"  eventgetb\n"
+	"      Prints raw EC host event flags copy B\n"
+	"  eventgetscimask\n"
+	"      Prints SCI mask for EC host events\n"
+	"  eventgetsmimask\n"
+	"      Prints SMI mask for EC host events\n"
+	"  eventgetwakemask\n"
+	"      Prints wake mask for EC host events\n"
+	"  eventsetscimask <mask>\n"
+	"      Sets the SCI mask for EC host events\n"
+	"  eventsetsmimask <mask>\n"
+	"      Sets the SMI mask for EC host events\n"
+	"  eventsetwakemask <mask>\n"
+	"      Sets the wake mask for EC host events\n"
+	"  extpwrlimit\n"
+	"      Set the maximum external power limit\n"
+	"  fanduty <percent>\n"
+	"      Forces the fan PWM to a constant duty cycle\n"
+	"  flasherase <offset> <size>\n"
+	"      Erases EC flash\n"
+	"  flasheraseasync <offset> <size>\n"
+	"      Erases EC flash asynchronously\n"
+	"  flashinfo\n"
+	"      Prints information on the EC flash\n"
+	"  flashspiinfo\n"
+	"      Prints information on EC SPI flash, if present\n"
+	"  flashpd <dev_id> <port> <filename>\n"
+	"      Flash commands over PD\n"
+	"  flashprotect [now] [enable | disable]\n"
+	"      Prints or sets EC flash protection state\n"
+	"  flashread <offset> <size> <outfile>\n"
+	"      Reads from EC flash to a file\n"
+	"  flashwrite <offset> <infile>\n"
+	"      Writes to EC flash from a file\n"
+	"  forcelidopen <enable>\n"
+	"      Forces the lid switch to open position\n"
+	"  fpcontext\n"
+	"      Sets the fingerprint sensor context\n"
+	"  fpencstatus\n"
+	"      Prints status of Fingerprint sensor encryption engine\n"
+	"  fpframe\n"
+	"      Retrieve the finger image as a PGM image\n"
+	"  fpinfo\n"
+	"      Prints information about the Fingerprint sensor\n"
+	"  fpmode [mode... [capture_type]]\n"
+	"      Configure/Read the fingerprint sensor current mode\n"
+	"      mode: capture|deepsleep|fingerdown|fingerup|enroll|match|\n"
+	"            reset|reset_sensor|maintenance\n"
+	"      capture_type: vendor|pattern0|pattern1|qual|test_reset\n"
+	"  fpseed\n"
+	"      Sets the value of the TPM seed.\n"
+	"  fpstats\n"
+	"      Prints timing statisitcs relating to capture and matching\n"
+	"  fptemplate [<infile>|<index 0..2>]\n"
+	"      Add a template if <infile> is provided, else dump it\n"
+	"  gpioget <GPIO name>\n"
+	"      Get the value of GPIO signal\n"
+	"  gpioset <GPIO name>\n"
+	"      Set the value of GPIO signal\n"
+	"  hangdetect <flags> <event_msec> <reboot_msec> | stop | start\n"
+	"      Configure or start/stop the hang detect timer\n"
+	"  hello\n"
+	"      Checks for basic communication with EC\n"
+	"  hibdelay [sec]\n"
+	"      Set the delay before going into hibernation\n"
+	"  hostsleepstate\n"
+	"      Report host sleep state to the EC\n"
+	"  hostevent\n"
+	"      Get & set host event masks.\n"
+	"  i2cprotect <port> [status]\n"
+	"      Protect EC's I2C bus\n"
+	"  i2cread\n"
+	"      Read I2C bus\n"
+	"  i2cspeed <port> [speed]\n"
+	"      Get or set EC's I2C bus speed\n"
+	"  i2cwrite\n"
+	"      Write I2C bus\n"
+	"  i2cxfer <port> <peripheral_addr> <read_count> [write bytes...]\n"
+	"      Perform I2C transfer on EC's I2C bus\n"
+	"  infopddev <port>\n"
+	"      Get info about USB type-C accessory attached to port\n"
+	"  inventory\n"
+	"      Return the list of supported features\n"
+	"  kbfactorytest\n"
+	"      Scan out keyboard if any pins are shorted\n"
+	"  kbid\n"
+	"      Get keyboard ID of supported keyboards\n"
+	"  kbinfo\n"
+	"      Dump keyboard matrix dimensions\n"
+	"  kbpress\n"
+	"      Simulate key press\n"
+	"  keyscan <beat_us> <filename>\n"
+	"      Test low-level key scanning\n"
+	"  led <name> <query | auto | off | <color> | <color>=<value>...>\n"
+	"      Set the color of an LED or query brightness range\n"
+	"  lightbar [CMDS]\n"
+	"      Various lightbar control commands\n"
+	"  locatechip <type> <index>\n"
+	"      Get the addresses and ports of i2c connected and embedded chips\n"
+	"  memory_dump [<address> [<size>]]\n"
+	"      Outputs the memory dump in hexdump canonical format.\n"
+	"  mkbpget <buttons|switches>\n"
+	"      Get MKBP buttons/switches supported mask and current state\n"
+	"  mkbpwakemask <get|set> <event|hostevent> [mask]\n"
+	"      Get or Set the MKBP event wake mask, or host event wake mask\n"
+	"  motionsense [CMDS]\n"
+	"      Various motion sense control commands\n"
+	"  panicinfo\n"
+	"      Prints saved panic info\n"
+	"  pause_in_s5 [on|off]\n"
+	"      Whether or not the AP should pause in S5 on shutdown\n"
+	"  pchg [<port>]\n"
+	"      Get peripheral charge port count and status\n"
+	"  pdcontrol [suspend|resume|reset|disable|on]\n"
+	"      Controls the PD chip\n"
+	"  pdchipinfo <port>\n"
+	"      Get PD chip information\n"
+	"  pdlog\n"
+	"      Prints the PD event log entries\n"
+	"  pdwritelog <type> <port>\n"
+	"      Writes a PD event log of the given <type>\n"
+	"  pdgetmode <port>\n"
+	"      Get All USB-PD alternate SVIDs and modes on <port>\n"
+	"  pdsetmode <port> <svid> <opos>\n"
+	"      Set USB-PD alternate SVID and mode on <port>\n"
+	"  port80flood\n"
+	"      Rapidly write bytes to port 80\n"
+	"  port80read\n"
+	"      Print history of port 80 write\n"
+	"  powerinfo\n"
+	"      Prints power-related information\n"
+	"  protoinfo\n"
+	"       Prints EC host protocol information\n"
+	"  pse\n"
+	"      Get and set PoE PSE port power status\n"
+	"  pstoreinfo\n"
+	"      Prints information on the EC host persistent storage\n"
+	"  pstoreread <offset> <size> <outfile>\n"
+	"      Reads from EC host persistent storage to a file\n"
+	"  pstorewrite <offset> <infile>\n"
+	"      Writes to EC host persistent storage from a file\n"
+	"  pwmgetfanrpm [<index> | all]\n"
+	"      Prints current fan RPM\n"
+	"  pwmgetkblight\n"
+	"      Prints current keyboard backlight percent\n"
+	"  pwmgetnumfans\n"
+	"      Prints the number of fans present\n"
+	"  pwmgetduty\n"
+	"      Prints the current 16 bit duty cycle for given PWM\n"
+	"  pwmsetfanrpm <targetrpm>\n"
+	"      Set target fan RPM\n"
+	"  pwmsetkblight <percent>\n"
+	"      Set keyboard backlight in percent\n"
+	"  pwmsetduty\n"
+	"      Set 16 bit duty cycle of given PWM\n"
+	"  rand <num_bytes>\n"
+	"      generate <num_bytes> of random numbers\n"
+	"  reboot_ec <RO|RW|cold|hibernate|hibernate-clear-ap-off|disable-jump|cold-ap-off>"
+	" [at-shutdown|switch-slot|clear-ap-idle]\n"
+	"      Reboot EC to RO or RW\n"
+	"  reboot_ap_on_g3 [<delay>]\n"
+	"      Requests that the EC will automatically reboot the AP after a\n"
+	"      configurable number of seconds the next time we enter the G3\n"
+	"      power state.\n"
+	"  rgbkbd ...\n"
+	"      Set/get RGB keyboard status, config, etc..\n"
+	"  rollbackinfo\n"
+	"      Print rollback block information\n"
+	"  rtcget\n"
+	"      Print real-time clock\n"
+	"  rtcgetalarm\n"
+	"      Print # of seconds before real-time clock alarm goes off.\n"
+	"  rtcset <time>\n"
+	"      Set real-time clock\n"
+	"  rtcsetalarm <sec>\n"
+	"      Set real-time clock alarm to go off in <sec> seconds\n"
+	"  rwhashpd <dev_id> <HASH[0] ... <HASH[4]>\n"
+	"      Set entry in PD MCU's device rw_hash table.\n"
+	"  rwsig <info|dump|action|status> ...\n"
+	"      info: get all info about rwsig\n"
+	"      dump: show individual rwsig field\n"
+	"      action: Control the behavior of RWSIG task.\n"
+	"      status: Run RW signature verification and get status.\n{"
+	"  rwsigaction (DEPRECATED; use \"rwsig action\")\n"
+	"      Control the behavior of RWSIG task.\n"
+	"  rwsigstatus (DEPRECATED; use \"rwsig status\"\n"
+	"      Run RW signature verification and get status.\n"
+	"  sertest\n"
+	"      Serial output test for COM2\n"
+	"  smartdischarge\n"
+	"      Set/Get smart discharge parameters\n"
+	"  stress [reboot] [help]\n"
+	"      Stress test the ec host command interface.\n"
+	"  sysinfo [flags|reset_flags|firmware_copy]\n"
+	"      Display system info.\n"
+	"  switches\n"
+	"      Prints current EC switch positions\n"
+	"  tabletmode [on | off | reset]\n"
+	"      Manually force tablet mode to on, off or reset.\n"
+	"  temps <sensorid>\n"
+	"      Print temperature and temperature ratio between fan_off and\n"
+	"      fan_max values, which could be a fan speed if it's controlled\n"
+	"      linearly\n"
+	"  tempsinfo <sensorid>\n"
+	"      Print temperature sensor info.\n"
+	"  thermalget <platform-specific args>\n"
+	"      Get the threshold temperature values from the thermal engine.\n"
+	"  thermalset <platform-specific args>\n"
+	"      Set the threshold temperature values for the thermal engine.\n"
+	"  tpselftest\n"
+	"      Run touchpad self test.\n"
+	"  tpframeget\n"
+	"      Get touchpad frame data.\n"
+	"  tmp006cal <tmp006_index> [params...]\n"
+	"      Get/set TMP006 calibration\n"
+	"  tmp006raw <tmp006_index>\n"
+	"      Get raw TMP006 data\n"
+	"  typeccontrol <port> <command>\n"
+	"      Control USB PD policy\n"
+	"  typecdiscovery <port> <type>\n"
+	"      Get discovery information for port and type\n"
+	"  typecstatus <port>\n"
+	"      Get status information for port\n"
+	"  typecvdmresponse <port>\n"
+	"      Get last VDM response for AP-requested VDM\n"
+	"  uptimeinfo\n"
+	"      Get info about how long the EC has been running and the most\n"
+	"      recent AP resets\n"
+	"  usbchargemode <port> <mode> [<inhibit_charge>]\n"
+	"      Set USB charging mode\n"
+	"  usbmux <mux>\n"
+	"      Set USB mux switch state\n"
+	"  usbpd <port> <auto | "
+	"[toggle|toggle-off|sink|source] [none|usb|dp|dock] "
+	"[dr_swap|pr_swap|vconn_swap]>\n"
+	"      Control USB PD/type-C [deprecated]\n"
+	"  usbpddps [enable | disable]\n"
+	"      Enable or disable dynamic pdo selection\n"
+	"  usbpdmuxinfo [tsv]\n"
+	"      Get USB-C SS mux info.\n"
+	"          tsv: Output as tab separated values. Columns are defined "
+	"as:\n"
+	"               Port, USB enabled, DP enabled, Polarity, HPD IRQ, "
+	"HPD LVL\n"
+	"  usbpdpower [port]\n"
+	"      Get USB PD power information\n"
+	"  version\n"
+	"      Prints EC version\n"
+	"  waitevent <type> [<timeout>]\n"
+	"      Wait for the MKBP event of type and display it\n"
+	"  wireless <flags> [<mask> [<suspend_flags> <suspend_mask>]]\n"
+	"      Enable/disable WLAN/Bluetooth radio\n"
+	"";
+
+/* Note: depends on enum ec_image */
+static const char *const image_names[] = { "unknown", "RO", "RW" };
+
+/* Note: depends on enum ec_led_colors */
+static const char *const led_color_names[] = { "red",	 "green", "blue",
+					       "yellow", "white", "amber" };
+BUILD_ASSERT(ARRAY_SIZE(led_color_names) == EC_LED_COLOR_COUNT);
+
+/* Note: depends on enum ec_led_id */
+static const char *const led_names[] = { "battery",    "power",
+					 "adapter",    "left",
+					 "right",      "recovery_hwreinit",
+					 "sysrq debug" };
+BUILD_ASSERT(ARRAY_SIZE(led_names) == EC_LED_ID_COUNT);
+
+/* ASCII mode for printing, default off */
+int ascii_mode;
+
+/* Check SBS numerical value range */
+int is_battery_range(int val)
+{
+	return (val >= 0 && val <= 65535) ? 1 : 0;
+}
+
+int parse_bool(const char *s, int *dest)
+{
+	if (!strcasecmp(s, "off") || !strncasecmp(s, "dis", 3) ||
+	    tolower(*s) == 'f' || tolower(*s) == 'n') {
+		*dest = 0;
+		return 1;
+	} else if (!strcasecmp(s, "on") || !strncasecmp(s, "ena", 3) ||
+		   tolower(*s) == 't' || tolower(*s) == 'y') {
+		*dest = 1;
+		return 1;
+	} else {
+		return 0;
+	}
+}
+
+/**
+ * @brief Find the enum value associated the string of enum text or value.
+ *
+ * @param str The input string to parse an enum from.
+ * @param enum_text_map The array that maps enum value (index) to text.
+ * @param enum_text_map_length The length of the enum_text_map array.
+ * @param enum_value Output parsed enum value.
+ * @return int 0 on success, -1 if result cannot be found
+ */
+static int find_enum_from_text(const char *str,
+			       const char *const enum_text_map[],
+			       long enum_text_map_length, long *enum_value)
+{
+	char *e;
+	long value;
+
+	assert(str);
+	assert(enum_value);
+	assert(enum_text_map);
+	assert(enum_text_map_length >= 0);
+
+	if (*str == '\0')
+		return -1;
+
+	value = strtol(str, &e, 0);
+	if (!e || !*e) {
+		*enum_value = value;
+		return 0;
+	}
+
+	for (value = 0; value < enum_text_map_length; value++) {
+		if (!enum_text_map[value])
+			continue;
+		if (strcasecmp(str, enum_text_map[value]) == 0) {
+			*enum_value = value;
+			return 0;
+		}
+	}
+
+	return -1;
+}
+
+void print_help(const char *prog, int print_cmds)
+{
+	printf("Usage: %s [--dev=n] "
+	       "[--interface=dev|i2c|lpc] [--i2c_bus=n] [--device=vid:pid] ",
+	       prog);
+	printf("[--name=cros_ec|cros_fp|cros_pd|cros_scp|cros_ish] [--ascii] ");
+	printf("<command> [params]\n\n");
+	printf("  --i2c_bus=n  Specifies the number of an I2C bus to use. For\n"
+	       "               example, to use /dev/i2c-7, pass --i2c_bus=7.\n"
+	       "               Implies --interface=i2c.\n\n");
+	printf("  --interface Specifies the interface.\n\n");
+	printf("  --device    Specifies USB endpoint by vendor ID and product\n"
+	       "              ID (e.g. 18d1:5022).\n\n");
+	if (print_cmds)
+		puts(help_str);
+	else
+		printf("Use '%s help' to print a list of commands.\n", prog);
+}
+
+static uint8_t read_mapped_mem8(uint8_t offset)
+{
+	int ret;
+	uint8_t val;
+
+	ret = ec_readmem(offset, sizeof(val), &val);
+	if (ret <= 0) {
+		fprintf(stderr, "failure in %s(): %d\n", __func__, ret);
+		exit(1);
+	}
+	return val;
+}
+
+static uint16_t read_mapped_mem16(uint8_t offset)
+{
+	int ret;
+	uint16_t val;
+
+	ret = ec_readmem(offset, sizeof(val), &val);
+	if (ret <= 0) {
+		fprintf(stderr, "failure in %s(): %d\n", __func__, ret);
+		exit(1);
+	}
+	return val;
+}
+
+static uint32_t read_mapped_mem32(uint8_t offset)
+{
+	int ret;
+	uint32_t val;
+
+	ret = ec_readmem(offset, sizeof(val), &val);
+	if (ret <= 0) {
+		fprintf(stderr, "failure in %s(): %d\n", __func__, ret);
+		exit(1);
+	}
+	return val;
+}
+
+static int read_mapped_string(uint8_t offset, char *buffer, int max_size)
+{
+	int ret;
+
+	ret = ec_readmem(offset, max_size, buffer);
+	if (ret <= 0) {
+		fprintf(stderr, "failure in %s(): %d\n", __func__, ret);
+		exit(1);
+	}
+	return ret;
+}
+
+static int wait_event(long event_type,
+		      struct ec_response_get_next_event_v1 *buffer,
+		      size_t buffer_size, long timeout)
+{
+	int rv;
+
+	rv = ec_pollevent(1 << event_type, buffer, buffer_size, timeout);
+	if (rv == 0) {
+		fprintf(stderr, "Timeout waiting for MKBP event\n");
+		return -ETIMEDOUT;
+	} else if (rv < 0) {
+		perror("Error polling for MKBP event\n");
+		return -EIO;
+	}
+
+	return rv;
+}
+
+int cmd_adc_read(int argc, char *argv[])
+{
+	char *e;
+	struct ec_params_adc_read p;
+	struct ec_response_adc_read r;
+	int rv;
+
+	if (argc < 2) {
+		fprintf(stderr, "Usage: %s <adc channel>\n", argv[0]);
+		return -1;
+	}
+
+	p.adc_channel = (uint8_t)strtoull(argv[1], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "\"%s\": invalid channel!\n", argv[1]);
+		return -1;
+	}
+
+	rv = ec_command(EC_CMD_ADC_READ, 0, &p, sizeof(p), &r, sizeof(r));
+	if (rv > 0) {
+		printf("%s: %d\n", argv[1], r.adc_value);
+		return 0;
+	}
+
+	return rv;
+}
+
+int cmd_add_entropy(int argc, char *argv[])
+{
+	bool reset = false;
+	if (argc >= 2 && !strcmp(argv[1], "reset"))
+		reset = true;
+
+	ec::AddEntropyCommand add_entropy_command(reset);
+	if (!add_entropy_command.Run(comm_get_fd())) {
+		fprintf(stderr, "Failed to run addentropy command\n");
+		return -1;
+	}
+
+	int rv = add_entropy_command.Result();
+	if (rv != EC_RES_SUCCESS) {
+		rv = -EECRESULT - add_entropy_command.Result();
+		fprintf(stderr, "Failed to add entropy: %d\n", rv);
+		return rv;
+	}
+
+	printf("Entropy added successfully\n");
+	return rv;
+}
+
+int cmd_hello(int argc, char *argv[])
+{
+	struct ec_params_hello p;
+	struct ec_response_hello r;
+	int rv;
+
+	p.in_data = 0xa0b0c0d0;
+
+	rv = ec_command(EC_CMD_HELLO, 0, &p, sizeof(p), &r, sizeof(r));
+	if (rv < 0)
+		return rv;
+
+	if (r.out_data != 0xa1b2c3d4) {
+		fprintf(stderr, "Expected response 0x%08x, got 0x%08x\n",
+			0xa1b2c3d4, r.out_data);
+		return -1;
+	}
+
+	printf("EC says hello!\n");
+	return 0;
+}
+
+int cmd_hibdelay(int argc, char *argv[])
+{
+	struct ec_params_hibernation_delay p;
+	struct ec_response_hibernation_delay r;
+	char *e;
+	int rv;
+
+	if (argc < 2) {
+		p.seconds = 0; /* Just read the current settings. */
+	} else {
+		p.seconds = strtoull(argv[1], &e, 0);
+		if (e && *e) {
+			fprintf(stderr, "invalid number\n");
+			return -1;
+		}
+	}
+
+	rv = ec_command(EC_CMD_HIBERNATION_DELAY, 0, &p, sizeof(p), &r,
+			sizeof(r));
+	if (rv < 0) {
+		fprintf(stderr, "err: rv=%d\n", rv);
+		return -1;
+	}
+
+	printf("Hibernation delay: %u s\n", r.hibernate_delay);
+	printf("Time G3: %u s\n", r.time_g3);
+	printf("Time left: %u s\n", r.time_remaining);
+	return 0;
+}
+
+static void cmd_hostevent_help(char *cmd)
+{
+	fprintf(stderr,
+		"  Usage: %s get <type>\n"
+		"  Usage: %s set <type> <value>\n"
+		"    <type> is one of:\n"
+		"      1: EC_HOST_EVENT_B\n"
+		"      2: EC_HOST_EVENT_SCI_MASK\n"
+		"      3: EC_HOST_EVENT_SMI_MASK\n"
+		"      4: EC_HOST_EVENT_ALWAYS_REPORT_MASK\n"
+		"      5: EC_HOST_EVENT_ACTIVE_WAKE_MASK\n"
+		"      6: EC_HOST_EVENT_LAZY_WAKE_MASK_S0IX\n"
+		"      7: EC_HOST_EVENT_LAZY_WAKE_MASK_S3\n"
+		"      8: EC_HOST_EVENT_LAZY_WAKE_MASK_S5\n",
+		cmd, cmd);
+}
+
+static int cmd_hostevent(int argc, char *argv[])
+{
+	struct ec_params_host_event p;
+	struct ec_response_host_event r;
+	char *e;
+	int rv;
+
+	if (argc < 2) {
+		fprintf(stderr, "Invalid number of params\n");
+		cmd_hostevent_help(argv[0]);
+		return -1;
+	}
+
+	if (!strcasecmp(argv[1], "get")) {
+		if (argc != 3) {
+			fprintf(stderr, "Invalid number of params\n");
+			cmd_hostevent_help(argv[0]);
+			return -1;
+		}
+		p.action = EC_HOST_EVENT_GET;
+	} else if (!strcasecmp(argv[1], "set")) {
+		if (argc != 4) {
+			fprintf(stderr, "Invalid number of params\n");
+			cmd_hostevent_help(argv[0]);
+			return -1;
+		}
+		p.action = EC_HOST_EVENT_SET;
+		p.value = strtoull(argv[3], &e, 0);
+		if (e && *e) {
+			fprintf(stderr, "Bad value\n");
+			return -1;
+		}
+	} else {
+		fprintf(stderr, "Bad subcommand: %s\n", argv[1]);
+		return -1;
+	}
+
+	p.mask_type = strtol(argv[2], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad type\n");
+		return -1;
+	}
+
+	rv = ec_command(EC_CMD_HOST_EVENT, 0, &p, sizeof(p), &r, sizeof(r));
+	if (rv == -EC_RES_ACCESS_DENIED - EECRESULT) {
+		fprintf(stderr, "%s isn't permitted for mask %d.\n",
+			p.action == EC_HOST_EVENT_SET ? "Set" : "Get",
+			p.mask_type);
+		return rv;
+	} else if (rv < 0) {
+		return rv;
+	}
+
+	if (p.action == EC_HOST_EVENT_GET)
+		printf("0x%" PRIx64 "\n", r.value);
+
+	return 0;
+}
+
+static int get_latest_cmd_version(uint8_t cmd, int *version)
+{
+	struct ec_params_get_cmd_versions p;
+	struct ec_response_get_cmd_versions r;
+	int rv;
+
+	*version = 0;
+	/* Figure out the latest version of the given command the EC supports */
+	p.cmd = cmd;
+	rv = ec_command(EC_CMD_GET_CMD_VERSIONS, 0, &p, sizeof(p), &r,
+			sizeof(r));
+	if (rv < 0) {
+		if (rv == -EC_RES_INVALID_PARAM)
+			printf("Command 0x%02x not supported by EC.\n",
+			       EC_CMD_GET_CMD_VERSIONS);
+		return rv;
+	}
+
+	if (r.version_mask)
+		*version = __fls(r.version_mask);
+
+	return rv;
+}
+
+int cmd_hostsleepstate(int argc, char *argv[])
+{
+	struct ec_params_host_sleep_event p;
+	struct ec_params_host_sleep_event_v1 p1;
+	struct ec_response_host_sleep_event_v1 r;
+	void *pp = &p;
+	size_t psize = sizeof(p), rsize = 0;
+	char *afterscan;
+	int rv;
+	int version = 0, max_version = 0;
+	uint32_t timeout, transitions;
+
+	if (argc < 2) {
+		fprintf(stderr,
+			"Usage: %s "
+			"[suspend|wsuspend|resume|freeze|thaw] [timeout]\n",
+			argv[0]);
+		return -1;
+	}
+
+	rv = get_latest_cmd_version(EC_CMD_HOST_SLEEP_EVENT, &max_version);
+	if (rv < 0)
+		return rv;
+
+	if (!strcmp(argv[1], "suspend"))
+		p.sleep_event = HOST_SLEEP_EVENT_S3_SUSPEND;
+	else if (!strcmp(argv[1], "wsuspend"))
+		p.sleep_event = HOST_SLEEP_EVENT_S3_WAKEABLE_SUSPEND;
+	else if (!strcmp(argv[1], "resume"))
+		p.sleep_event = HOST_SLEEP_EVENT_S3_RESUME;
+	else if (!strcmp(argv[1], "freeze")) {
+		p.sleep_event = HOST_SLEEP_EVENT_S0IX_SUSPEND;
+		if (max_version >= 1) {
+			p1.sleep_event = p.sleep_event;
+			p1.reserved = 0;
+			p1.suspend_params.sleep_timeout_ms =
+				EC_HOST_SLEEP_TIMEOUT_DEFAULT;
+
+			if (argc > 2) {
+				p1.suspend_params.sleep_timeout_ms =
+					strtoull(argv[2], &afterscan, 0);
+
+				if ((*afterscan != '\0') ||
+				    (afterscan == argv[2])) {
+					fprintf(stderr, "Invalid value: %s\n",
+						argv[2]);
+
+					return -1;
+				}
+			}
+
+			pp = &p1;
+			psize = sizeof(p1);
+			version = 1;
+		}
+
+	} else if (!strcmp(argv[1], "thaw")) {
+		p.sleep_event = HOST_SLEEP_EVENT_S0IX_RESUME;
+		if (max_version >= 1) {
+			version = 1;
+			rsize = sizeof(r);
+		}
+	} else {
+		fprintf(stderr, "Unknown command: %s\n", argv[1]);
+		return -1;
+	}
+
+	rv = ec_command(EC_CMD_HOST_SLEEP_EVENT, version, pp, psize, &r, rsize);
+	if (rv < 0) {
+		fprintf(stderr, "EC host sleep command failed: %d\n", rv);
+		return rv;
+	}
+
+	if (rsize) {
+		timeout = r.resume_response.sleep_transitions &
+			  EC_HOST_RESUME_SLEEP_TIMEOUT;
+
+		transitions = r.resume_response.sleep_transitions &
+			      EC_HOST_RESUME_SLEEP_TRANSITIONS_MASK;
+
+		printf("%s%d sleep line transitions.\n",
+		       timeout ? "Timeout: " : "", transitions);
+	}
+
+	return 0;
+}
+
+int cmd_test(int argc, char *argv[])
+{
+	struct ec_params_test_protocol p = {
+		.buf = { 1,  2,	 3,  4,	 5,  6,	 7,  8,	 9,  10, 11,
+			 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22,
+			 23, 24, 25, 26, 27, 28, 29, 30, 31, 32 }
+	};
+	struct ec_response_test_protocol r;
+	int rv, version = 0;
+	char *e;
+
+	if (argc < 3) {
+		fprintf(stderr, "Usage: %s result length [version]\n", argv[0]);
+		return -1;
+	}
+
+	p.ec_result = strtol(argv[1], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "invalid param (result)\n");
+		return -1;
+	}
+	p.ret_len = strtol(argv[2], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "invalid param (length)\n");
+		return -1;
+	}
+
+	if (argc > 3) {
+		version = strtol(argv[3], &e, 0);
+		if (e && *e) {
+			fprintf(stderr, "invalid param (version)\n");
+			return -1;
+		}
+	}
+
+	rv = ec_command(EC_CMD_TEST_PROTOCOL, version, &p, sizeof(p), &r,
+			sizeof(r));
+	printf("rv = %d\n", rv);
+
+	return rv;
+}
+
+int cmd_s5(int argc, char *argv[])
+{
+	struct ec_params_get_set_value p;
+	struct ec_response_get_set_value r;
+	int rv, param;
+
+	p.flags = 0;
+
+	if (argc > 1) {
+		p.flags |= EC_GSV_SET;
+		if (!parse_bool(argv[1], &param)) {
+			fprintf(stderr, "invalid arg \"%s\"\n", argv[1]);
+			return -1;
+		}
+		p.value = param;
+	}
+
+	rv = ec_command(EC_CMD_GSV_PAUSE_IN_S5, 0, &p, sizeof(p), &r,
+			sizeof(r));
+	if (rv > 0)
+		printf("%s\n", r.value ? "on" : "off");
+
+	return rv < 0;
+}
+
+static const char *const ec_feature_names[] = {
+	[EC_FEATURE_LIMITED] = "Limited image, load RW for more",
+	[EC_FEATURE_FLASH] = "Flash",
+	[EC_FEATURE_PWM_FAN] = "Direct Fan power management",
+	[EC_FEATURE_PWM_KEYB] = "Keyboard backlight",
+	[EC_FEATURE_LIGHTBAR] = "Lightbar",
+	[EC_FEATURE_LED] = "LED",
+	[EC_FEATURE_MOTION_SENSE] = "Motion Sensors",
+	[EC_FEATURE_KEYB] = "Keyboard",
+	[EC_FEATURE_PSTORE] = "Host Permanent Storage",
+	[EC_FEATURE_PORT80] = "BIOS Port 80h access",
+	[EC_FEATURE_THERMAL] = "Thermal management",
+	[EC_FEATURE_BKLIGHT_SWITCH] = "Switch backlight on/off",
+	[EC_FEATURE_WIFI_SWITCH] = "Switch wifi on/off",
+	[EC_FEATURE_HOST_EVENTS] = "Host event",
+	[EC_FEATURE_GPIO] = "GPIO",
+	[EC_FEATURE_I2C] = "I2C controller",
+	[EC_FEATURE_CHARGER] = "Charger",
+	[EC_FEATURE_BATTERY] = "Simple Battery",
+	[EC_FEATURE_SMART_BATTERY] = "Smart Battery",
+	[EC_FEATURE_HANG_DETECT] = "Host hang detection",
+	[EC_FEATURE_PMU] = "Power Management",
+	[EC_FEATURE_SUB_MCU] = "Control downstream MCU",
+	[EC_FEATURE_USB_PD] = "USB Cros Power Delivery",
+	[EC_FEATURE_USB_MUX] = "USB Multiplexer",
+	[EC_FEATURE_MOTION_SENSE_FIFO] = "FIFO for Motion Sensors events",
+	[EC_FEATURE_VSTORE] = "Temporary secure vstore",
+	[EC_FEATURE_USBC_SS_MUX_VIRTUAL] = "Host-controlled USB-C SS mux",
+	[EC_FEATURE_RTC] = "Real-time clock",
+	[EC_FEATURE_FINGERPRINT] = "Fingerprint",
+	[EC_FEATURE_TOUCHPAD] = "Touchpad",
+	[EC_FEATURE_RWSIG] = "RWSIG task",
+	[EC_FEATURE_DEVICE_EVENT] = "Device events reporting",
+	[EC_FEATURE_UNIFIED_WAKE_MASKS] = "Unified wake masks for LPC/eSPI",
+	[EC_FEATURE_HOST_EVENT64] = "64-bit host events",
+	[EC_FEATURE_EXEC_IN_RAM] = "Execute code in RAM",
+	[EC_FEATURE_CEC] = "Consumer Electronics Control",
+	[EC_FEATURE_MOTION_SENSE_TIGHT_TIMESTAMPS] =
+		"Tight timestamp for sensors events",
+	[EC_FEATURE_REFINED_TABLET_MODE_HYSTERESIS] =
+		"Refined tablet mode hysteresis",
+	[EC_FEATURE_EFS2] = "Early Firmware Selection v2",
+	[EC_FEATURE_ISH] = "Intel Integrated Sensor Hub",
+	[EC_FEATURE_TYPEC_CMD] = "TCPMv2 Type-C commands",
+	[EC_FEATURE_TYPEC_REQUIRE_AP_MODE_ENTRY] =
+		"Host-controlled Type-C mode entry",
+	[EC_FEATURE_TYPEC_MUX_REQUIRE_AP_ACK] =
+		"AP ack for Type-C mux configuration",
+	[EC_FEATURE_S4_RESIDENCY] = "S4 residency",
+	[EC_FEATURE_TYPEC_AP_MUX_SET] = "AP directed mux sets",
+	[EC_FEATURE_TYPEC_AP_VDM_SEND] = "AP directed VDM Request messages",
+	[EC_FEATURE_SYSTEM_SAFE_MODE] = "System Safe Mode support",
+	[EC_FEATURE_ASSERT_REBOOTS] = "Assert reboots",
+};
+
+int cmd_inventory(int argc, char *argv[])
+{
+	struct ec_response_get_features r;
+	int rv, i, j, idx;
+
+	rv = ec_command(EC_CMD_GET_FEATURES, 0, NULL, 0, &r, sizeof(r));
+	if (rv < 0)
+		return rv;
+
+	printf("EC supported features:\n");
+	for (i = 0, idx = 0; i < 2; i++) {
+		for (j = 0; j < 32; j++, idx++) {
+			if (r.flags[i] & BIT(j)) {
+				if (idx >= ARRAY_SIZE(ec_feature_names) ||
+				    !ec_feature_names[idx] ||
+				    strlen(ec_feature_names[idx]) == 0)
+					printf("%-4d: Unknown feature\n", idx);
+				else
+					printf("%-4d: %s support\n", idx,
+					       ec_feature_names[idx]);
+			}
+		}
+	}
+	return 0;
+}
+
+static int get_cmdversions_v0(uint8_t cmd, uint32_t *version_mask)
+{
+	struct ec_params_get_cmd_versions p;
+	struct ec_response_get_cmd_versions r;
+	int rv;
+
+	p.cmd = cmd;
+	rv = ec_command(EC_CMD_GET_CMD_VERSIONS, 0, &p, sizeof(p), &r,
+			sizeof(r));
+	if (rv < 0) {
+		if (rv == -EC_RES_INVALID_PARAM)
+			printf("Command 0x%02x not supported by EC.\n", cmd);
+
+		return rv;
+	}
+
+	*version_mask = r.version_mask;
+	return 0;
+}
+
+int cmd_cmdversions(int argc, char *argv[])
+{
+	struct ec_params_get_cmd_versions_v1 p;
+	struct ec_response_get_cmd_versions r;
+	char *e;
+	int cmd;
+	int rv;
+
+	if (argc < 2) {
+		fprintf(stderr, "Usage: %s <cmd>\n", argv[0]);
+		return -1;
+	}
+	cmd = strtol(argv[1], &e, 0);
+	if ((e && *e) || cmd < 0 || cmd > 0xffff) {
+		fprintf(stderr, "Bad command number.\n");
+		return -1;
+	}
+
+	if (cmd > 0xff) {
+		/* Ensure the EC support GET_CMD_VERSIONS v1. */
+		rv = get_cmdversions_v0(EC_CMD_GET_CMD_VERSIONS,
+					&r.version_mask);
+		if (rv < 0)
+			return rv;
+
+		if (!(r.version_mask & EC_VER_MASK(1))) {
+			printf("16 bits cmdversions not supported by EC.\n");
+			return -1;
+		}
+
+		/* Use GET_CMD_VERSIONS v1. */
+		p.cmd = cmd;
+		rv = ec_command(EC_CMD_GET_CMD_VERSIONS, 1, &p, sizeof(p), &r,
+				sizeof(r));
+		if (rv < 0) {
+			if (rv == -EC_RES_INVALID_PARAM)
+				printf("Command 0x%02x not supported by EC.\n",
+				       cmd);
+
+			return rv;
+		}
+	} else {
+		rv = get_cmdversions_v0(cmd, &r.version_mask);
+		if (rv < 0)
+			return rv;
+	}
+
+	printf("Command 0x%02x supports version mask 0x%08x\n", cmd,
+	       r.version_mask);
+	return 0;
+}
+
+/*
+ * Convert a reset cause ID to human-readable string, providing total coverage
+ * of the 'cause' space.  The returned string points to static storage and must
+ * not be free()ed.
+ */
+static const char *reset_cause_to_str(uint16_t cause)
+{
+	static const char *const reset_causes[] = {
+		"(reset unknown)",
+		"reset: board custom",
+		"reset: ap hang detected",
+		"reset: console command",
+		"reset: host command",
+		"reset: keyboard sysreset",
+		"reset: keyboard warm reboot",
+		"reset: debug warm reboot",
+		"reset: at AP's request",
+		"reset: during EC initialization",
+		"reset: AP watchdog",
+	};
+	BUILD_ASSERT(ARRAY_SIZE(reset_causes) == CHIPSET_RESET_COUNT);
+
+	static const char *const shutdown_causes[] = {
+		"shutdown: power failure",
+		"shutdown: during EC initialization",
+		"shutdown: board custom",
+		"shutdown: battery voltage startup inhibit",
+		"shutdown: power wait asserted",
+		"shutdown: critical battery",
+		"shutdown: by console command",
+		"shutdown: entering G3",
+		"shutdown: thermal",
+		"shutdown: power button",
+	};
+	BUILD_ASSERT(ARRAY_SIZE(shutdown_causes) ==
+		     CHIPSET_SHUTDOWN_COUNT - CHIPSET_SHUTDOWN_BEGIN);
+
+	if (cause < CHIPSET_RESET_COUNT)
+		return reset_causes[cause];
+
+	if (cause < CHIPSET_SHUTDOWN_BEGIN)
+		return "(reset unknown)";
+
+	if (cause < CHIPSET_SHUTDOWN_COUNT)
+		return shutdown_causes[cause - CHIPSET_SHUTDOWN_BEGIN];
+
+	return "(shutdown unknown)";
+}
+
+int cmd_uptimeinfo(int argc, char *argv[])
+{
+	struct ec_response_uptime_info r;
+	int rv;
+	int i;
+	int flag_count;
+	uint32_t flag;
+	static const char *const reset_flag_descs[] = {
+#include "reset_flag_desc.inc"
+	};
+
+	if (argc != 1) {
+		fprintf(stderr, "uptimeinfo takes no arguments");
+		return -1;
+	}
+
+	rv = ec_command(EC_CMD_GET_UPTIME_INFO, 0, NULL, 0, &r, sizeof(r));
+	if (rv < 0) {
+		fprintf(stderr, "ERROR: EC_CMD_GET_UPTIME_INFO failed; %d\n",
+			rv);
+		return rv;
+	}
+
+	printf("EC uptime: %d.%03d seconds\n", r.time_since_ec_boot_ms / 1000,
+	       r.time_since_ec_boot_ms % 1000);
+
+	printf("AP resets since EC boot: %d\n", r.ap_resets_since_ec_boot);
+
+	printf("Most recent AP reset causes:\n");
+	for (i = 0; i != ARRAY_SIZE(r.recent_ap_reset); ++i) {
+		if (r.recent_ap_reset[i].reset_time_ms == 0)
+			continue;
+
+		printf("\t%d.%03d: %s\n",
+		       r.recent_ap_reset[i].reset_time_ms / 1000,
+		       r.recent_ap_reset[i].reset_time_ms % 1000,
+		       reset_cause_to_str(r.recent_ap_reset[i].reset_cause));
+	}
+
+	printf("EC reset flags at last EC boot: ");
+
+	if (!r.ec_reset_flags) {
+		printf("unknown\n");
+		return 0;
+	}
+
+	flag_count = 0;
+	for (flag = 0; flag < ARRAY_SIZE(reset_flag_descs); ++flag) {
+		if ((r.ec_reset_flags & BIT(flag)) != 0) {
+			if (flag_count)
+				printf(" | ");
+			printf(reset_flag_descs[flag]);
+			flag_count++;
+		}
+	}
+
+	if (r.ec_reset_flags >= BIT(flag)) {
+		if (flag_count)
+			printf(" | ");
+		printf("no-desc");
+	}
+	printf("\n");
+	return 0;
+}
+
+int cmd_version(int argc, char *argv[])
+{
+	struct ec_response_get_version_v1 r;
+	char *build_string = (char *)ec_inbuf;
+	int rv;
+
+	if (ec_cmd_version_supported(EC_CMD_GET_VERSION, 1)) {
+		rv = ec_command(EC_CMD_GET_VERSION, 1, NULL, 0, &r,
+				sizeof(struct ec_response_get_version_v1));
+	} else {
+		/* Fall-back to version 0 if version 1 is not supported */
+		rv = ec_command(EC_CMD_GET_VERSION, 0, NULL, 0, &r,
+				sizeof(struct ec_response_get_version));
+		/* These fields are not supported in version 0, ensure empty */
+		r.cros_fwid_ro[0] = '\0';
+		r.cros_fwid_rw[0] = '\0';
+	}
+	if (rv < 0) {
+		fprintf(stderr, "ERROR: EC_CMD_GET_VERSION failed: %d\n", rv);
+		goto exit;
+	}
+
+	rv = ec_command(EC_CMD_GET_BUILD_INFO, 0, NULL, 0, ec_inbuf,
+			ec_max_insize);
+	if (rv < 0) {
+		fprintf(stderr, "ERROR: EC_CMD_GET_BUILD_INFO failed: %d\n",
+			rv);
+		goto exit;
+	}
+
+	rv = 0;
+
+	/* Ensure versions are null-terminated before we print them */
+	r.version_string_ro[sizeof(r.version_string_ro) - 1] = '\0';
+	r.version_string_rw[sizeof(r.version_string_rw) - 1] = '\0';
+	build_string[ec_max_insize - 1] = '\0';
+	r.cros_fwid_ro[sizeof(r.cros_fwid_ro) - 1] = '\0';
+	r.cros_fwid_rw[sizeof(r.cros_fwid_rw) - 1] = '\0';
+	/* Print versions */
+	printf("RO version:    %s\n", r.version_string_ro);
+	if (strlen(r.cros_fwid_ro))
+		printf("RO cros fwid:  %s\n", r.cros_fwid_ro);
+	printf("RW version:    %s\n", r.version_string_rw);
+	if (strlen(r.cros_fwid_rw))
+		printf("RW cros fwid:  %s\n", r.cros_fwid_rw);
+	printf("Firmware copy: %s\n",
+	       (r.current_image < ARRAY_SIZE(image_names) ?
+			image_names[r.current_image] :
+			"?"));
+	printf("Build info:    %s\n", build_string);
+exit:
+	printf("Tool version:  %s %s %s\n", CROS_ECTOOL_VERSION, DATE, BUILDER);
+
+	return rv;
+}
+
+int cmd_reboot_ec(int argc, char *argv[])
+{
+	struct ec_params_reboot_ec p;
+	int rv, i;
+
+	if (argc < 2) {
+		/*
+		 * No params specified so tell the EC to reboot immediately.
+		 * That reboots the AP as well, so unlikely we'll be around
+		 * to see a return code from this...
+		 */
+		rv = ec_command(EC_CMD_REBOOT, 0, NULL, 0, NULL, 0);
+		return (rv < 0 ? rv : 0);
+	}
+
+	/* Parse command */
+	if (!strcmp(argv[1], "cancel"))
+		p.cmd = EC_REBOOT_CANCEL;
+	else if (!strcmp(argv[1], "RO"))
+		p.cmd = EC_REBOOT_JUMP_RO;
+	else if (!strcmp(argv[1], "RW"))
+		p.cmd = EC_REBOOT_JUMP_RW;
+	else if (!strcmp(argv[1], "cold"))
+		p.cmd = EC_REBOOT_COLD;
+	else if (!strcmp(argv[1], "disable-jump"))
+		p.cmd = EC_REBOOT_DISABLE_JUMP;
+	else if (!strcmp(argv[1], "hibernate"))
+		p.cmd = EC_REBOOT_HIBERNATE;
+	else if (!strcmp(argv[1], "hibernate-clear-ap-off")) {
+		p.cmd = EC_REBOOT_HIBERNATE_CLEAR_AP_OFF;
+		fprintf(stderr, "hibernate-clear-ap-off is deprecated.\n"
+				"Use hibernate and clear-ap-idle, instead.\n");
+	} else if (!strcmp(argv[1], "cold-ap-off"))
+		p.cmd = EC_REBOOT_COLD_AP_OFF;
+	else {
+		fprintf(stderr, "Unknown command: %s\n", argv[1]);
+		return -1;
+	}
+
+	/* Parse flags, if any */
+	p.flags = 0;
+	for (i = 2; i < argc; i++) {
+		if (!strcmp(argv[i], "at-shutdown")) {
+			p.flags |= EC_REBOOT_FLAG_ON_AP_SHUTDOWN;
+		} else if (!strcmp(argv[i], "switch-slot")) {
+			p.flags |= EC_REBOOT_FLAG_SWITCH_RW_SLOT;
+		} else if (!strcmp(argv[i], "clear-ap-idle")) {
+			p.flags |= EC_REBOOT_FLAG_CLEAR_AP_IDLE;
+		} else {
+			fprintf(stderr, "Unknown flag: %s\n", argv[i]);
+			return -1;
+		}
+	}
+
+	rv = ec_command(EC_CMD_REBOOT_EC, 0, &p, sizeof(p), NULL, 0);
+	return (rv < 0 ? rv : 0);
+}
+
+int cmd_reboot_ap_on_g3(int argc, char *argv[])
+{
+	struct ec_params_reboot_ap_on_g3_v1 p;
+	int rv;
+	char *e;
+	int cmdver;
+
+	if (argc < 2) {
+		p.reboot_ap_at_g3_delay = 0;
+	} else {
+		p.reboot_ap_at_g3_delay = strtol(argv[1], &e, 0);
+		if (e && *e) {
+			fprintf(stderr, "invalid number\n");
+			return -1;
+		}
+	}
+	if (ec_cmd_version_supported(EC_CMD_REBOOT_AP_ON_G3, 1))
+		cmdver = 1;
+	else
+		cmdver = 0;
+
+	rv = ec_command(EC_CMD_REBOOT_AP_ON_G3, cmdver, &p, sizeof(p), NULL, 0);
+	return (rv < 0 ? rv : 0);
+}
+
+static void cmd_rgbkbd_help(char *cmd)
+{
+	fprintf(stderr,
+		"  Usage1: %s <key> <RGB> [<RGB> ...]\n"
+		"          Set the color of <key> to <RGB>. Multiple colors for\n"
+		"          adjacent keys can be set at once.\n"
+		"\n"
+		"  Usage2: %s clear <RGB>\n"
+		"          Set the color of all keys to <RGB>.\n"
+		"\n"
+		"  Usage3: %s demo <num>\n"
+		"          Run demo-<num>. 0: Off, 1: Flow, 2: Dot.\n"
+		"\n"
+		"  Usage4: %s scale <key> <val>\n"
+		"          Set the scale parameter of key_<key> to <val>.\n"
+		"          <val> is a 24-bit integer where scale values are encoded\n"
+		"          as R=23:16, G=15:8, B=7:0.\n"
+		"\n"
+		"  Usage5: %s getconfig\n"
+		"          Get the HW config supported.\n"
+		"\n",
+		cmd, cmd, cmd, cmd, cmd);
+}
+
+static int cmd_rgbkbd_parse_rgb_text(const char *text, struct rgb_s *color)
+{
+	uint32_t rgb;
+	char *e;
+
+	rgb = strtoul(text, &e, 0);
+	if ((e && *e) || rgb > EC_RGBKBD_MAX_RGB_COLOR) {
+		fprintf(stderr, "Invalid color '%s'.\n", text);
+		return -1;
+	}
+	color->r = (rgb >> 16) & 0xff;
+	color->g = (rgb >> 8) & 0xff;
+	color->b = (rgb >> 0) & 0xff;
+
+	return 0;
+}
+
+static int cmd_rgbkbd_set_color(int argc, char *argv[])
+{
+	struct ec_params_rgbkbd_set_color *p;
+	int i, key, outlen;
+	char *e;
+	int rv = -1;
+
+	outlen = sizeof(*p) + sizeof(struct rgb_s) * EC_RGBKBD_MAX_KEY_COUNT;
+	p = (struct ec_params_rgbkbd_set_color *)malloc(outlen);
+	if (p == NULL)
+		return -1;
+	memset(p, 0, outlen);
+
+	key = strtol(argv[1], &e, 0);
+	if ((e && *e) || key >= EC_RGBKBD_MAX_KEY_COUNT) {
+		fprintf(stderr, "Invalid key ID '%s'.\n", argv[1]);
+		goto out;
+	}
+	p->start_key = key;
+
+	if (argc - 2 > EC_RGBKBD_MAX_KEY_COUNT) {
+		fprintf(stderr, "# of colors exceed max key count.\n");
+		goto out;
+	}
+
+	for (i = 2; i < argc; i++) {
+		if (cmd_rgbkbd_parse_rgb_text(argv[i], &p->color[p->length]))
+			goto out;
+		p->length++;
+	}
+
+	outlen = sizeof(*p) + sizeof(struct rgb_s) * p->length;
+	rv = ec_command(EC_CMD_RGBKBD_SET_COLOR, 0, p, outlen, NULL, 0);
+
+out:
+	free(p);
+
+	return rv;
+}
+
+static int cmd_rgbkbd(int argc, char *argv[])
+{
+	int val;
+	char *e;
+	int rv = -1;
+	struct ec_params_rgbkbd p;
+	struct ec_response_rgbkbd r;
+
+	if (argc < 2) {
+		cmd_rgbkbd_help(argv[0]);
+		return -1;
+	}
+
+	if (argc == 3 && !strcasecmp(argv[1], "clear")) {
+		/* Usage 2 */
+		p.subcmd = EC_RGBKBD_SUBCMD_CLEAR;
+		if (cmd_rgbkbd_parse_rgb_text(argv[2], &p.color))
+			return -1;
+
+		rv = ec_command(EC_CMD_RGBKBD, 0, &p, sizeof(p), &r, sizeof(r));
+	} else if (argc == 3 && !strcasecmp(argv[1], "demo")) {
+		/* Usage 3 */
+		val = strtol(argv[2], &e, 0);
+		if ((e && *e) || val >= EC_RGBKBD_DEMO_COUNT) {
+			fprintf(stderr, "Invalid demo id: %s\n", argv[2]);
+			return -1;
+		}
+		p.subcmd = EC_RGBKBD_SUBCMD_DEMO;
+		p.demo = val;
+		rv = ec_command(EC_CMD_RGBKBD, 0, &p, sizeof(p), &r, sizeof(r));
+	} else if (argc == 4 && !strcasecmp(argv[1], "scale")) {
+		/* Usage 4 */
+		val = strtol(argv[2], &e, 0);
+		if ((e && *e) || val > EC_RGBKBD_MAX_KEY_COUNT) {
+			fprintf(stderr, "Invalid key number: %s\n", argv[2]);
+			return -1;
+		}
+		p.set_scale.key = val;
+		if (cmd_rgbkbd_parse_rgb_text(argv[3], &p.set_scale.scale)) {
+			fprintf(stderr, "Invalid scale value: %s\n", argv[3]);
+			return -1;
+		}
+		p.subcmd = EC_RGBKBD_SUBCMD_SET_SCALE;
+		rv = ec_command(EC_CMD_RGBKBD, 0, &p, sizeof(p), &r, sizeof(r));
+	} else if (argc == 2 && !strcasecmp(argv[1], "getconfig")) {
+		/* Usage 5 */
+		const char *type;
+
+		p.subcmd = EC_RGBKBD_SUBCMD_GET_CONFIG;
+		rv = ec_command(EC_CMD_RGBKBD, 0, &p, sizeof(p), &r, sizeof(r));
+
+		if (rv < 0)
+			return rv;
+
+		switch ((enum ec_rgbkbd_type)r.rgbkbd_type) {
+		case EC_RGBKBD_TYPE_PER_KEY:
+			type = "EC_RGBKBD_TYPE_PER_KEY";
+			break;
+		case EC_RGBKBD_TYPE_FOUR_ZONES_40_LEDS:
+			type = "EC_RGBKBD_TYPE_FOUR_ZONES_40_LEDS";
+			break;
+		case EC_RGBKBD_TYPE_FOUR_ZONES_12_LEDS:
+			type = "EC_RGBKBD_TYPE_FOUR_ZONES_12_LEDS";
+			break;
+		case EC_RGBKBD_TYPE_FOUR_ZONES_4_LEDS:
+			type = "EC_RGBKBD_TYPE_FOUR_ZONES_4_LEDS";
+			break;
+		default:
+			type = "EC_RGBKBD_TYPE_UNKNOWN";
+		}
+
+		printf("RGBKBD_TYPE: %s\n", type);
+	} else {
+		/* Usage 1 */
+		rv = cmd_rgbkbd_set_color(argc, argv);
+	}
+
+	return (rv < 0 ? rv : 0);
+}
+
+int cmd_button(int argc, char *argv[])
+{
+	struct ec_params_button p;
+	char *e;
+	int argv_idx;
+	int button = KEYBOARD_BUTTON_COUNT;
+	int rv;
+
+	if (argc < 2) {
+		fprintf(stderr, "Invalid num param %d.\n", argc);
+		return -1;
+	}
+
+	p.press_ms = 50;
+	p.btn_mask = 0;
+
+	for (argv_idx = 1; argv_idx < argc; argv_idx++) {
+		if (!strcasecmp(argv[argv_idx], "vup"))
+			button = KEYBOARD_BUTTON_VOLUME_UP;
+		else if (!strcasecmp(argv[argv_idx], "vdown"))
+			button = KEYBOARD_BUTTON_VOLUME_DOWN;
+		else if (!strcasecmp(argv[argv_idx], "rec"))
+			button = KEYBOARD_BUTTON_RECOVERY;
+		else {
+			/* If last parameter check if it is an integer. */
+			if (argv_idx == argc - 1) {
+				p.press_ms = strtol(argv[argv_idx], &e, 0);
+				/* If integer, break out of the loop. */
+				if (!*e)
+					break;
+			}
+			button = KEYBOARD_BUTTON_COUNT;
+		}
+
+		if (button == KEYBOARD_BUTTON_COUNT) {
+			fprintf(stderr, "Invalid button input.\n");
+			return -1;
+		}
+
+		p.btn_mask |= (1 << button);
+	}
+	if (!p.btn_mask)
+		return 0;
+
+	rv = ec_command(EC_CMD_BUTTON, 0, &p, sizeof(p), NULL, 0);
+	if (rv < 0)
+		return rv;
+
+	printf("Button(s) %d set to %d ms\n", p.btn_mask, p.press_ms);
+	return 0;
+}
+
+int cmd_flash_info(int argc, char *argv[])
+{
+	struct ec_response_flash_info_1 r;
+	int cmdver = 1;
+	int rsize = sizeof(r);
+	int rv;
+
+	memset(&r, 0, sizeof(r));
+
+	if (!ec_cmd_version_supported(EC_CMD_FLASH_INFO, cmdver)) {
+		/* Fall back to version 0 command */
+		cmdver = 0;
+		rsize = sizeof(struct ec_response_flash_info);
+	}
+
+	rv = ec_command(EC_CMD_FLASH_INFO, cmdver, NULL, 0, &r, rsize);
+	if (rv < 0)
+		return rv;
+
+	printf("FlashSize %d\nWriteSize %d\nEraseSize %d\nProtectSize %d\n",
+	       r.flash_size, r.write_block_size, r.erase_block_size,
+	       r.protect_block_size);
+
+	if (cmdver >= 1) {
+		/* Fields added in ver.1 available */
+		printf("WriteIdealSize %d\nFlags 0x%x\n", r.write_ideal_size,
+		       r.flags);
+	}
+
+	return 0;
+}
+
+int cmd_rand(int argc, char *argv[])
+{
+	int64_t num_bytes;
+	int64_t i;
+	char *e;
+	int rv = 0;
+
+	if (argc < 2) {
+		fprintf(stderr, "Usage: %s <num_bytes>\n", argv[0]);
+		return -1;
+	}
+
+	num_bytes = strtol(argv[1], &e, 0);
+	if ((e && *e) || (errno == ERANGE)) {
+		fprintf(stderr, "Invalid num_bytes argument\n");
+		return -1;
+	}
+
+	for (i = 0; i < num_bytes; i += ec_max_insize) {
+		uint16_t num_rand_bytes = ec_max_insize;
+		if (num_bytes - i < num_rand_bytes)
+			num_rand_bytes = num_bytes - i;
+
+		ec::RandNumCommand rand_num_command(num_rand_bytes);
+		if (!rand_num_command.Run(comm_get_fd())) {
+			int rv = -EECRESULT - rand_num_command.Result();
+			fprintf(stderr, "Rand Num returned with errors: %d\n",
+				rv);
+			return rv;
+		}
+
+		rv = write(STDOUT_FILENO,
+			   rand_num_command.GetRandNumData().data(),
+			   num_rand_bytes);
+		if (rv != num_rand_bytes) {
+			fprintf(stderr, "Failed to write stdout\n");
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
+int cmd_flash_spi_info(int argc, char *argv[])
+{
+	struct ec_response_flash_spi_info r;
+	int rv;
+
+	memset(&r, 0, sizeof(r));
+
+	/* Print SPI flash info if available */
+	if (!ec_cmd_version_supported(EC_CMD_FLASH_SPI_INFO, 0)) {
+		printf("EC has no info (does not use SPI flash?)\n");
+		return -1;
+	}
+
+	rv = ec_command(EC_CMD_FLASH_SPI_INFO, 0, NULL, 0, &r, sizeof(r));
+	if (rv < 0)
+		return rv;
+
+	printf("JEDECManufacturerID 0x%02x\n", r.jedec[0]);
+	printf("JEDECDeviceID 0x%02x 0x%02x\n", r.jedec[1], r.jedec[2]);
+	printf("JEDECCapacity %d\n", 1 << r.jedec[2]);
+	printf("ManufacturerID 0x%02x\n", r.mfr_dev_id[0]);
+	printf("DeviceID 0x%02x\n", r.mfr_dev_id[1]);
+	printf("StatusRegister1 0x%02x\n", r.sr1);
+	printf("StatusRegister2 0x%02x\n", r.sr2);
+	return 0;
+}
+
+int cmd_flash_read(int argc, char *argv[])
+{
+	int offset, size;
+	int rv;
+	char *e;
+	uint8_t *buf;
+
+	if (argc < 4) {
+		fprintf(stderr, "Usage: %s <offset> <size> <filename>\n",
+			argv[0]);
+		return -1;
+	}
+	offset = strtol(argv[1], &e, 0);
+	if ((e && *e) || offset < 0 || offset > MAX_FLASH_SIZE) {
+		fprintf(stderr, "Bad offset.\n");
+		return -1;
+	}
+	size = strtol(argv[2], &e, 0);
+	if ((e && *e) || size <= 0 || size > MAX_FLASH_SIZE) {
+		fprintf(stderr, "Bad size.\n");
+		return -1;
+	}
+	printf("Reading %d bytes at offset %d...\n", size, offset);
+
+	buf = (uint8_t *)malloc(size);
+	if (!buf) {
+		fprintf(stderr, "Unable to allocate buffer.\n");
+		return -1;
+	}
+
+	/* Read data in chunks */
+	rv = ec_flash_read(buf, offset, size);
+	if (rv < 0) {
+		free(buf);
+		return rv;
+	}
+
+	rv = write_file(argv[3], (const char *)(buf), size);
+	free(buf);
+	if (rv)
+		return rv;
+
+	printf("done.\n");
+	return 0;
+}
+
+int cmd_flash_write(int argc, char *argv[])
+{
+	int offset, size;
+	int rv;
+	char *e;
+	char *buf;
+
+	if (argc < 3) {
+		fprintf(stderr, "Usage: %s <offset> <filename>\n", argv[0]);
+		return -1;
+	}
+
+	offset = strtol(argv[1], &e, 0);
+	if ((e && *e) || offset < 0 || offset > MAX_FLASH_SIZE) {
+		fprintf(stderr, "Bad offset.\n");
+		return -1;
+	}
+
+	/* Read the input file */
+	buf = read_file(argv[2], &size);
+	if (!buf)
+		return -1;
+
+	printf("Writing to offset %d...\n", offset);
+
+	/* Write data in chunks */
+	rv = ec_flash_write((const uint8_t *)(buf), offset, size);
+
+	free(buf);
+
+	if (rv < 0)
+		return rv;
+
+	printf("done.\n");
+	return 0;
+}
+
+int cmd_flash_erase(int argc, char *argv[])
+{
+	int offset, size;
+	char *e;
+	int rv;
+	bool async = false;
+
+	if (argc < 3) {
+		fprintf(stderr, "Usage: %s <offset> <size>\n", argv[0]);
+		return -1;
+	}
+
+	if (strcmp(argv[0], "flasheraseasync") == 0)
+		async = true;
+
+	offset = strtol(argv[1], &e, 0);
+	if ((e && *e) || offset < 0 || offset > MAX_FLASH_SIZE) {
+		fprintf(stderr, "Bad offset.\n");
+		return -1;
+	}
+
+	size = strtol(argv[2], &e, 0);
+	if ((e && *e) || size <= 0 || size > MAX_FLASH_SIZE) {
+		fprintf(stderr, "Bad size.\n");
+		return -1;
+	}
+
+	printf("Erasing %d bytes at offset %d...\n", size, offset);
+	if (async)
+		rv = ec_flash_erase_async(offset, size);
+	else
+		rv = ec_flash_erase(offset, size);
+	if (rv < 0)
+		return rv;
+
+	printf("done.\n");
+	return 0;
+}
+
+int cmd_flash_protect(int argc, char *argv[])
+{
+	/*
+	 * Set up requested flags.  If no flags were specified, mask will
+	 * be flash_protect::Flags::kNone and nothing will change.
+	 */
+	ec::flash_protect::Flags flags = ec::flash_protect::Flags::kNone;
+	ec::flash_protect::Flags mask = ec::flash_protect::Flags::kNone;
+
+	for (int i = 1; i < argc; i++) {
+		if (!strcasecmp(argv[i], "now")) {
+			mask |= ec::flash_protect::Flags::kAllNow;
+			flags |= ec::flash_protect::Flags::kAllNow;
+		} else if (!strcasecmp(argv[i], "enable")) {
+			mask |= ec::flash_protect::Flags::kRoAtBoot;
+			flags |= ec::flash_protect::Flags::kRoAtBoot;
+		} else if (!strcasecmp(argv[i], "disable"))
+			mask |= ec::flash_protect::Flags::kRoAtBoot;
+	}
+
+	ec::FlashProtectCommand_v1 flash_protect_command(flags, mask);
+	if (!flash_protect_command.Run(comm_get_fd())) {
+		int rv = -EECRESULT - flash_protect_command.Result();
+		fprintf(stderr, "Flash protect returned with errors: %d\n", rv);
+		return rv;
+	}
+
+	/* Print returned flags */
+	printf("Flash protect flags: 0x%08x%s\n",
+	       flash_protect_command.GetFlags(),
+	       (ec::FlashProtectCommand::ParseFlags(
+			flash_protect_command.GetFlags()))
+		       .c_str());
+	printf("Valid flags:         0x%08x%s\n",
+	       flash_protect_command.GetValidFlags(),
+	       (ec::FlashProtectCommand::ParseFlags(
+			flash_protect_command.GetValidFlags()))
+		       .c_str());
+	printf("Writable flags:      0x%08x%s\n",
+	       flash_protect_command.GetWritableFlags(),
+
+	       (ec::FlashProtectCommand::ParseFlags(
+			flash_protect_command.GetWritableFlags()))
+		       .c_str());
+
+	/* Check if we got all the flags we asked for */
+	if ((flash_protect_command.GetFlags() & mask) != (flags & mask)) {
+		fprintf(stderr,
+			"Unable to set requested flags "
+			"(wanted mask 0x%08x flags 0x%08x)\n",
+			mask, flags);
+		if ((mask & ~flash_protect_command.GetWritableFlags()) !=
+		    ec::flash_protect::Flags::kNone)
+			fprintf(stderr,
+				"Which is expected, because writable "
+				"mask is 0x%08x.\n",
+				flash_protect_command.GetWritableFlags());
+
+		return -1;
+	}
+
+	return 0;
+}
+
+int cmd_rw_hash_pd(int argc, char *argv[])
+{
+	struct ec_params_usb_pd_rw_hash_entry *p =
+		(struct ec_params_usb_pd_rw_hash_entry *)ec_outbuf;
+	int i, rv;
+	char *e;
+	uint32_t val;
+	uint8_t *rwp;
+
+	if (argc < 7) {
+		fprintf(stderr, "Usage: %s <dev_id> <HASH[0]> ... <HASH[4]>\n",
+			argv[0]);
+		return -1;
+	}
+
+	p->dev_id = strtol(argv[1], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad device ID\n");
+		return -1;
+	}
+
+	rwp = p->dev_rw_hash;
+	for (i = 2; i < 7; i++) {
+		val = strtol(argv[i], &e, 0);
+		if (e && *e) {
+			fprintf(stderr, "Bad RW hash\n");
+			return -1;
+		}
+		rwp[0] = (uint8_t)(val >> 0) & 0xff;
+		rwp[1] = (uint8_t)(val >> 8) & 0xff;
+		rwp[2] = (uint8_t)(val >> 16) & 0xff;
+		rwp[3] = (uint8_t)(val >> 24) & 0xff;
+		rwp += 4;
+	}
+	rv = ec_command(EC_CMD_USB_PD_RW_HASH_ENTRY, 0, p, sizeof(*p), NULL, 0);
+
+	return rv;
+}
+
+int cmd_rwsig_status(int argc, char *argv[])
+{
+	int rv;
+	struct ec_response_rwsig_check_status resp;
+
+	rv = ec_command(EC_CMD_RWSIG_CHECK_STATUS, 0, NULL, 0, &resp,
+			sizeof(resp));
+	if (rv < 0)
+		return rv;
+
+	printf("RW signature check: %s\n", resp.status ? "OK" : "FAILED");
+
+	return 0;
+}
+
+static int rwsig_action(const char *command)
+{
+	struct ec_params_rwsig_action req;
+
+	if (!strcasecmp(command, "abort"))
+		req.action = RWSIG_ACTION_ABORT;
+	else if (!strcasecmp(command, "continue"))
+		req.action = RWSIG_ACTION_CONTINUE;
+	else
+		return -1;
+
+	return ec_command(EC_CMD_RWSIG_ACTION, 0, &req, sizeof(req), NULL, 0);
+}
+
+int cmd_rwsig_action_legacy(int argc, char *argv[])
+{
+	if (argc < 2) {
+		fprintf(stderr, "Usage: %s [abort | continue]\n", argv[0]);
+		return -1;
+	}
+
+	return rwsig_action(argv[1]);
+}
+
+int cmd_rwsig_action(int argc, char *argv[])
+{
+	if (argc < 2) {
+		fprintf(stderr, "Usage: ectool rwsig action [abort | "
+				"continue]\n");
+		return -1;
+	}
+
+	return rwsig_action(argv[1]);
+}
+
+enum rwsig_info_fields {
+	RWSIG_INFO_FIELD_SIG_ALG = BIT(0),
+	RWSIG_INFO_FIELD_KEY_VERSION = BIT(1),
+	RWSIG_INFO_FIELD_HASH_ALG = BIT(2),
+	RWSIG_INFO_FIELD_KEY_IS_VALID = BIT(3),
+	RWSIG_INFO_FIELD_KEY_ID = BIT(4),
+	RWSIG_INFO_FIELD_ALL =
+		RWSIG_INFO_FIELD_SIG_ALG | RWSIG_INFO_FIELD_KEY_VERSION |
+		RWSIG_INFO_FIELD_HASH_ALG | RWSIG_INFO_FIELD_KEY_IS_VALID |
+		RWSIG_INFO_FIELD_KEY_ID
+};
+
+static int rwsig_info(enum rwsig_info_fields fields)
+{
+	int i;
+	int rv;
+	struct ec_response_rwsig_info r;
+	bool print_prefix = false;
+
+	rv = ec_command(EC_CMD_RWSIG_INFO, EC_VER_RWSIG_INFO, NULL, 0, &r,
+			sizeof(r));
+	if (rv < 0) {
+		fprintf(stderr, "rwsig info command failed\n");
+		return -1;
+	}
+
+	if ((fields & RWSIG_INFO_FIELD_ALL) == RWSIG_INFO_FIELD_ALL)
+		print_prefix = true;
+
+	if (fields & RWSIG_INFO_FIELD_SIG_ALG) {
+		if (print_prefix)
+			printf("sig_alg: ");
+
+		printf("%d\n", r.sig_alg);
+	}
+	if (fields & RWSIG_INFO_FIELD_KEY_VERSION) {
+		if (print_prefix)
+			printf("key_version: ");
+
+		printf("%d\n", r.key_version);
+	}
+	if (fields & RWSIG_INFO_FIELD_HASH_ALG) {
+		if (print_prefix)
+			printf("hash_alg: ");
+
+		printf("%d\n", r.hash_alg);
+	}
+	if (fields & RWSIG_INFO_FIELD_KEY_IS_VALID) {
+		if (print_prefix)
+			printf("key_is_valid: ");
+
+		printf("%d\n", r.key_is_valid);
+	}
+	if (fields & RWSIG_INFO_FIELD_KEY_ID) {
+		if (print_prefix)
+			printf("key_id: ");
+
+		for (i = 0; i < sizeof(r.key_id); i++)
+			printf("%02x", r.key_id[i]);
+		printf("\n");
+	}
+
+	return 0;
+}
+
+static int cmd_rwsig_info(int argc, char *argv[])
+{
+	int i;
+
+	struct rwsig_dump_cmds {
+		const char *cmd;
+		enum rwsig_info_fields field;
+	};
+
+	struct rwsig_dump_cmds cmd_map[] = {
+		{ "sig_alg", RWSIG_INFO_FIELD_SIG_ALG },
+		{ "key_version", RWSIG_INFO_FIELD_KEY_VERSION },
+		{ "hash_alg", RWSIG_INFO_FIELD_HASH_ALG },
+		{ "key_valid", RWSIG_INFO_FIELD_KEY_IS_VALID },
+		{ "key_id", RWSIG_INFO_FIELD_KEY_ID },
+	};
+
+	if (argc == 0)
+		return -1;
+
+	if (strcmp(argv[0], "info") == 0)
+		return rwsig_info(RWSIG_INFO_FIELD_ALL);
+
+	if (strcmp(argv[0], "dump") == 0) {
+		if (argc != 2) {
+			fprintf(stderr,
+				"Usage: rwsig dump "
+				"[sig_alg|key_version|hash_alg|key_valid|key_id]\n");
+			return -1;
+		}
+		for (i = 0; i < ARRAY_SIZE(cmd_map); i++)
+			if (strcmp(argv[1], cmd_map[i].cmd) == 0)
+				return rwsig_info(cmd_map[i].field);
+
+		return -1;
+	}
+
+	return -1;
+}
+
+int cmd_rwsig(int argc, char **argv)
+{
+	struct rwsig_subcommand {
+		const char *subcommand;
+		int (*handler)(int argc, char *argv[]);
+	};
+
+	const struct rwsig_subcommand rwsig_subcommands[] = {
+		{ "info", cmd_rwsig_info },
+		{ "dump", cmd_rwsig_info },
+		{ "action", cmd_rwsig_action },
+		{ "status", cmd_rwsig_status }
+	};
+
+	int i;
+
+	if (argc < 2) {
+		fprintf(stderr, "Usage: %s <info|dump|action|status>\n",
+			argv[0]);
+		return -1;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(rwsig_subcommands); i++)
+		if (strcmp(argv[1], rwsig_subcommands[i].subcommand) == 0)
+			return rwsig_subcommands[i].handler(--argc, &argv[1]);
+
+	return -1;
+}
+
+enum sysinfo_fields {
+	SYSINFO_FIELD_NONE = 0,
+	SYSINFO_FIELD_RESET_FLAGS = BIT(0),
+	SYSINFO_FIELD_CURRENT_IMAGE = BIT(1),
+	SYSINFO_FIELD_FLAGS = BIT(2),
+	SYSINFO_INFO_FIELD_ALL = SYSINFO_FIELD_RESET_FLAGS |
+				 SYSINFO_FIELD_CURRENT_IMAGE |
+				 SYSINFO_FIELD_FLAGS
+};
+
+static int sysinfo(struct ec_response_sysinfo *info)
+{
+	int rv;
+
+	rv = ec_command(EC_CMD_SYSINFO, 0, NULL, 0, info, sizeof(*info));
+	if (rv < 0) {
+		fprintf(stderr, "ERROR: EC_CMD_SYSINFO failed: %d\n", rv);
+		return rv;
+	}
+
+	return 0;
+}
+
+int cmd_sysinfo(int argc, char **argv)
+{
+	struct ec_response_sysinfo r;
+	enum sysinfo_fields fields = SYSINFO_FIELD_NONE;
+	bool print_prefix = false;
+
+	if (argc != 1 && argc != 2)
+		goto sysinfo_error_usage;
+
+	if (argc == 1) {
+		fields = SYSINFO_INFO_FIELD_ALL;
+		print_prefix = true;
+	} else if (argc == 2) {
+		if (strcmp(argv[1], "flags") == 0)
+			fields = SYSINFO_FIELD_FLAGS;
+		else if (strcmp(argv[1], "reset_flags") == 0)
+			fields = SYSINFO_FIELD_RESET_FLAGS;
+		else if (strcmp(argv[1], "firmware_copy") == 0)
+			fields = SYSINFO_FIELD_CURRENT_IMAGE;
+		else
+			goto sysinfo_error_usage;
+	}
+
+	memset(&r, '\0', sizeof(r));
+	if (sysinfo(&r) != 0)
+		return -1;
+
+	if (fields & SYSINFO_FIELD_RESET_FLAGS) {
+		if (print_prefix)
+			printf("Reset flags: ");
+		printf("0x%08x\n", r.reset_flags);
+	}
+
+	if (fields & SYSINFO_FIELD_FLAGS) {
+		if (print_prefix)
+			printf("Flags: ");
+		printf("0x%08x\n", r.flags);
+	}
+
+	if (fields & SYSINFO_FIELD_CURRENT_IMAGE) {
+		if (print_prefix)
+			printf("Firmware copy: ");
+		printf("%d\n", r.current_image);
+	}
+
+	return 0;
+
+sysinfo_error_usage:
+	fprintf(stderr,
+		"Usage: %s "
+		"[flags|reset_flags|firmware_copy]\n",
+		argv[0]);
+	return -1;
+}
+
+int cmd_rollback_info(int argc, char *argv[])
+{
+	struct ec_response_rollback_info r;
+	int rv;
+
+	rv = ec_command(EC_CMD_ROLLBACK_INFO, 0, NULL, 0, &r, sizeof(r));
+	if (rv < 0) {
+		fprintf(stderr, "ERROR: EC_CMD_ROLLBACK_INFO failed: %d\n", rv);
+		return rv;
+	}
+
+	/* Print versions */
+	printf("Rollback block id:    %d\n", r.id);
+	printf("Rollback min version: %d\n", r.rollback_min_version);
+	printf("RW rollback version:  %d\n", r.rw_rollback_version);
+
+	return 0;
+}
+
+int cmd_apreset(int argc, char *argv[])
+{
+	return ec_command(EC_CMD_AP_RESET, 0, NULL, 0, NULL, 0);
+}
+
+#define FP_FRAME_INDEX_SIMPLE_IMAGE -1
+
+/*
+ * Download a frame buffer from the FPMCU.
+ *
+ * Might be either the finger image or a finger template depending on 'index'.
+ *
+ * @param info a pointer to store the struct ec_response_fp_info retrieved by
+ * this command.
+ * @param index the specific frame to retrieve, might be:
+ *  -1 (aka FP_FRAME_INDEX_SIMPLE_IMAGE) for the a single grayscale image.
+ *   0  (aka FP_FRAME_INDEX_RAW_IMAGE) for the full vendor raw finger image.
+ *   1..n for a finger template.
+ *
+ * @returns a pointer to the buffer allocated to contain the frame or NULL
+ * if case of error. The caller must call free() once it no longer needs the
+ * buffer.
+ */
+static void *fp_download_frame(struct ec_response_fp_info *info, int index)
+{
+	struct ec_params_fp_frame p;
+	int rv = 0;
+	size_t stride, size;
+	void *buffer;
+	uint8_t *ptr;
+	int cmdver = ec_cmd_version_supported(EC_CMD_FP_INFO, 1) ? 1 : 0;
+	int rsize = cmdver == 1 ? sizeof(*info) :
+				  sizeof(struct ec_response_fp_info_v0);
+	const int max_attempts = 3;
+	int num_attempts;
+
+	/* templates not supported in command v0 */
+	if (index > 0 && cmdver == 0)
+		return NULL;
+
+	rv = ec_command(EC_CMD_FP_INFO, cmdver, NULL, 0, info, rsize);
+	if (rv < 0)
+		return NULL;
+
+	if (index == FP_FRAME_INDEX_SIMPLE_IMAGE) {
+		size = (size_t)info->width * info->bpp / 8 * info->height;
+		index = FP_FRAME_INDEX_RAW_IMAGE;
+	} else if (index == FP_FRAME_INDEX_RAW_IMAGE) {
+		size = info->frame_size;
+	} else {
+		size = info->template_size;
+	}
+
+	buffer = malloc(size);
+	if (!buffer) {
+		fprintf(stderr, "Cannot allocate memory for the image\n");
+		return NULL;
+	}
+
+	ptr = (uint8_t *)(buffer);
+	p.offset = index << FP_FRAME_INDEX_SHIFT;
+	while (size) {
+		stride = MIN(ec_max_insize, size);
+		p.size = stride;
+		num_attempts = 0;
+		while (num_attempts < max_attempts) {
+			num_attempts++;
+			rv = ec_command(EC_CMD_FP_FRAME, 0, &p, sizeof(p), ptr,
+					stride);
+			if (rv >= 0)
+				break;
+			if (rv == -EECRESULT - EC_RES_ACCESS_DENIED)
+				break;
+			usleep(100000);
+		}
+		if (rv < 0) {
+			free(buffer);
+			return NULL;
+		}
+		p.offset += stride;
+		size -= stride;
+		ptr += stride;
+	}
+
+	return buffer;
+}
+
+int cmd_fp_mode(int argc, char *argv[])
+{
+	struct ec_params_fp_mode p;
+	struct ec_response_fp_mode r;
+	uint32_t mode = 0;
+	uint32_t capture_type = FP_CAPTURE_SIMPLE_IMAGE;
+	int i, rv;
+
+	if (argc == 1)
+		mode = FP_MODE_DONT_CHANGE;
+	for (i = 1; i < argc; i++) {
+		/* modes */
+		if (!strncmp(argv[i], "deepsleep", 9))
+			mode |= FP_MODE_DEEPSLEEP;
+		else if (!strncmp(argv[i], "fingerdown", 10))
+			mode |= FP_MODE_FINGER_DOWN;
+		else if (!strncmp(argv[i], "fingerup", 8))
+			mode |= FP_MODE_FINGER_UP;
+		else if (!strncmp(argv[i], "enroll", 6))
+			mode |= FP_MODE_ENROLL_IMAGE | FP_MODE_ENROLL_SESSION;
+		else if (!strncmp(argv[i], "match", 5))
+			mode |= FP_MODE_MATCH;
+		else if (!strncmp(argv[i], "reset_sensor", 12))
+			mode = FP_MODE_RESET_SENSOR;
+		else if (!strncmp(argv[i], "reset", 5))
+			mode = 0;
+		else if (!strncmp(argv[i], "maintenance", 11))
+			mode |= FP_MODE_SENSOR_MAINTENANCE;
+		else if (!strncmp(argv[i], "capture", 7))
+			mode |= FP_MODE_CAPTURE;
+		/* capture types */
+		else if (!strncmp(argv[i], "vendor", 6))
+			capture_type = FP_CAPTURE_VENDOR_FORMAT;
+		else if (!strncmp(argv[i], "pattern0", 8))
+			capture_type = FP_CAPTURE_PATTERN0;
+		else if (!strncmp(argv[i], "pattern1", 8))
+			capture_type = FP_CAPTURE_PATTERN1;
+		else if (!strncmp(argv[i], "qual", 4))
+			capture_type = FP_CAPTURE_QUALITY_TEST;
+		else if (!strncmp(argv[i], "test_reset", 10))
+			capture_type = FP_CAPTURE_RESET_TEST;
+	}
+	if (mode & FP_MODE_CAPTURE)
+		mode |= capture_type << FP_MODE_CAPTURE_TYPE_SHIFT;
+
+	p.mode = mode;
+	rv = ec_command(EC_CMD_FP_MODE, 0, &p, sizeof(p), &r, sizeof(r));
+	if (rv < 0)
+		return rv;
+
+	printf("FP mode: (0x%x) ", r.mode);
+	if (r.mode & FP_MODE_DEEPSLEEP)
+		printf("deepsleep ");
+	if (r.mode & FP_MODE_FINGER_DOWN)
+		printf("finger-down ");
+	if (r.mode & FP_MODE_FINGER_UP)
+		printf("finger-up ");
+	if (r.mode & FP_MODE_ENROLL_SESSION)
+		printf("enroll%s ",
+		       r.mode & FP_MODE_ENROLL_IMAGE ? "+image" : "");
+	if (r.mode & FP_MODE_MATCH)
+		printf("match ");
+	if (r.mode & FP_MODE_CAPTURE)
+		printf("capture ");
+	printf("\n");
+	return 0;
+}
+
+int cmd_fp_seed(int argc, char *argv[])
+{
+	struct ec_params_fp_seed p;
+	char *seed;
+
+	if (argc != 2) {
+		fprintf(stderr, "Usage: %s <seed>\n", argv[0]);
+		return 1;
+	}
+	seed = argv[1];
+	if (strlen(seed) != FP_CONTEXT_TPM_BYTES) {
+		printf("Invalid seed '%s' is %zd bytes long instead of %d.\n",
+		       seed, strlen(seed), FP_CONTEXT_TPM_BYTES);
+		return 1;
+	}
+	printf("Setting seed '%s'\n", seed);
+	p.struct_version = FP_TEMPLATE_FORMAT_VERSION;
+	memcpy(p.seed, seed, FP_CONTEXT_TPM_BYTES);
+
+	return ec_command(EC_CMD_FP_SEED, 0, &p, sizeof(p), NULL, 0);
+}
+
+int cmd_fp_stats(int argc, char *argv[])
+{
+	struct ec_response_fp_stats r;
+	int rv;
+	unsigned long long ts;
+
+	rv = ec_command(EC_CMD_FP_STATS, 0, NULL, 0, &r, sizeof(r));
+	if (rv < 0)
+		return rv;
+
+	ts = (uint64_t)r.overall_t0.hi << 32 | r.overall_t0.lo;
+	printf("FP stats (t0=%llu us):\n", ts);
+	printf("Last capture time:  ");
+	if (r.timestamps_invalid & FPSTATS_CAPTURE_INV)
+		printf("Invalid\n");
+	else
+		printf("%d us\n", r.capture_time_us);
+
+	printf("Last matching time: ");
+	if (r.timestamps_invalid & FPSTATS_MATCHING_INV)
+		printf("Invalid\n");
+	else
+		printf("%d us (finger: %d)\n", r.matching_time_us,
+		       r.template_matched);
+
+	printf("Last overall time:  ");
+	if (r.timestamps_invalid)
+		printf("Invalid\n");
+	else
+		printf("%d us\n", r.overall_time_us);
+
+	return 0;
+}
+
+int cmd_fp_info(int argc, char *argv[])
+{
+	struct ec_response_fp_info r;
+	int rv;
+	int cmdver = ec_cmd_version_supported(EC_CMD_FP_INFO, 1) ? 1 : 0;
+	int rsize = cmdver == 1 ? sizeof(r) :
+				  sizeof(struct ec_response_fp_info_v0);
+	uint16_t dead;
+
+	rv = ec_command(EC_CMD_FP_INFO, cmdver, NULL, 0, &r, rsize);
+	if (rv < 0)
+		return rv;
+
+	printf("Fingerprint sensor: vendor %x product %x model %x version %x\n",
+	       r.vendor_id, r.product_id, r.model_id, r.version);
+	printf("Image: size %dx%d %d bpp\n", r.width, r.height, r.bpp);
+	printf("Error flags: %s%s%s%s\n",
+	       r.errors & FP_ERROR_NO_IRQ ? "NO_IRQ " : "",
+	       r.errors & FP_ERROR_SPI_COMM ? "SPI_COMM " : "",
+	       r.errors & FP_ERROR_BAD_HWID ? "BAD_HWID " : "",
+	       r.errors & FP_ERROR_INIT_FAIL ? "INIT_FAIL " : "");
+	dead = FP_ERROR_DEAD_PIXELS(r.errors);
+	if (dead == FP_ERROR_DEAD_PIXELS_UNKNOWN) {
+		printf("Dead pixels: UNKNOWN\n");
+	} else {
+		printf("Dead pixels: %u\n", dead);
+	}
+
+	if (cmdver == 1) {
+		printf("Templates: version %d size %d count %d/%d"
+		       " dirty bitmap %x\n",
+		       r.template_version, r.template_size, r.template_valid,
+		       r.template_max, r.template_dirty);
+	}
+
+	return 0;
+}
+
+static int cmd_fp_context(int argc, char *argv[])
+{
+	struct ec_params_fp_context_v1 p;
+	int rv;
+	int tries = 20; /* Wait at most two seconds */
+
+	if (argc < 2) {
+		fprintf(stderr, "Usage: %s <context>\n", argv[0]);
+		return -1;
+	}
+
+	/*
+	 * Note that we treat the resulting "userid" as raw byte array, so we
+	 * don't want to copy the NUL from the end of the string.
+	 */
+	if (strlen(argv[1]) != sizeof(p.userid)) {
+		fprintf(stderr, "Context must be exactly %zu bytes\n",
+			sizeof(p.userid));
+		return -1;
+	}
+
+	p.action = FP_CONTEXT_ASYNC;
+	memcpy(p.userid, argv[1], sizeof(p.userid));
+
+	rv = ec_command(EC_CMD_FP_CONTEXT, 1, &p, sizeof(p), NULL, 0);
+
+	if (rv != EC_RES_SUCCESS)
+		goto out;
+
+	while (tries--) {
+		usleep(100000);
+
+		p.action = FP_CONTEXT_GET_RESULT;
+		rv = ec_command(EC_CMD_FP_CONTEXT, 1, &p, sizeof(p), NULL, 0);
+
+		if (rv == EC_RES_SUCCESS) {
+			printf("Set context successfully\n");
+			return EC_RES_SUCCESS;
+		}
+
+		/* Abort if EC returns an error other than EC_RES_BUSY. */
+		if (rv <= -EECRESULT && rv != -EECRESULT - EC_RES_BUSY)
+			goto out;
+	}
+
+	rv = -EECRESULT - EC_RES_TIMEOUT;
+
+out:
+	fprintf(stderr, "Failed to reset context: %d\n", rv);
+	return rv;
+}
+
+int cmd_fp_enc_status(int argc, char *argv[])
+{
+	int rv;
+
+	ec::FpEncryptionStatusCommand fp_encryptionstatus_command;
+
+	if (!fp_encryptionstatus_command.Run(comm_get_fd())) {
+		int rv = -EECRESULT - fp_encryptionstatus_command.Result();
+		fprintf(stderr,
+			"FP Encryption Status returned with errors: %d\n", rv);
+		return rv;
+	}
+	printf("FPMCU encryption status: 0x%08x%s",
+	       fp_encryptionstatus_command.GetStatus(),
+	       (ec::FpEncryptionStatusCommand::ParseFlags(
+			fp_encryptionstatus_command.GetStatus()))
+		       .c_str());
+	printf("Valid flags:             0x%08x%s",
+	       fp_encryptionstatus_command.GetValidFlags(),
+	       (ec::FpEncryptionStatusCommand::ParseFlags(
+			fp_encryptionstatus_command.GetValidFlags()))
+		       .c_str());
+
+	rv = 0;
+
+	return rv;
+}
+
+int cmd_fp_frame(int argc, char *argv[])
+{
+	struct ec_response_fp_info r;
+	int idx = (argc == 2 && !strcasecmp(argv[1], "raw")) ?
+			  FP_FRAME_INDEX_RAW_IMAGE :
+			  FP_FRAME_INDEX_SIMPLE_IMAGE;
+	uint8_t *buffer = (uint8_t *)(fp_download_frame(&r, idx));
+	uint8_t *ptr = buffer;
+	int x, y;
+
+	if (!buffer) {
+		fprintf(stderr, "Failed to get FP sensor frame\n");
+		return -1;
+	}
+
+	if (idx == FP_FRAME_INDEX_RAW_IMAGE) {
+		fwrite(buffer, r.frame_size, 1, stdout);
+		goto frame_done;
+	}
+
+	/* Print 8-bpp PGM ASCII header */
+	printf("P2\n%d %d\n%d\n", r.width, r.height, (1 << r.bpp) - 1);
+
+	for (y = 0; y < r.height; y++) {
+		for (x = 0; x < r.width; x++, ptr++)
+			printf("%d ", *ptr);
+		printf("\n");
+	}
+	printf("# END OF FILE\n");
+frame_done:
+	free(buffer);
+	return 0;
+}
+
+int cmd_fp_template(int argc, char *argv[])
+{
+	struct ec_response_fp_info r;
+	struct ec_params_fp_template *p =
+		(struct ec_params_fp_template *)(ec_outbuf);
+	/* TODO(b/78544921): removing 32 bits is a workaround for the MCU bug */
+	int max_chunk = ec_max_outsize -
+			offsetof(struct ec_params_fp_template, data) - 4;
+	int idx = -1;
+	char *e;
+	int size;
+	char *buffer = NULL;
+	uint32_t offset = 0;
+	int rv = 0;
+
+	if (argc < 2) {
+		fprintf(stderr, "Usage: %s [<infile>|<index>]\n", argv[0]);
+		return -1;
+	}
+
+	idx = strtol(argv[1], &e, 0);
+	if (!(e && *e)) {
+		buffer = (char *)(fp_download_frame(&r, idx + 1));
+		if (!buffer) {
+			fprintf(stderr, "Failed to get FP template %d\n", idx);
+			return -1;
+		}
+		fwrite(buffer, r.template_size, 1, stdout);
+		free(buffer);
+		return 0;
+	}
+	/* not an index, is it a filename ? */
+	buffer = read_file(argv[1], &size);
+	if (!buffer) {
+		fprintf(stderr, "Invalid parameter: %s\n", argv[1]);
+		return -1;
+	}
+	printf("sending template from: %s (%d bytes)\n", argv[1], size);
+	while (size) {
+		uint32_t tlen = MIN(max_chunk, size);
+
+		p->offset = offset;
+		p->size = tlen;
+		size -= tlen;
+		if (!size)
+			p->size |= FP_TEMPLATE_COMMIT;
+		memcpy(p->data, buffer + offset, tlen);
+		rv = ec_command(EC_CMD_FP_TEMPLATE, 0, p,
+				tlen + offsetof(struct ec_params_fp_template,
+						data),
+				NULL, 0);
+		if (rv < 0)
+			break;
+		offset += tlen;
+	}
+	if (rv < 0)
+		fprintf(stderr, "Failed with %d\n", rv);
+	else
+		rv = 0;
+	free(buffer);
+	return rv;
+}
+
+/**
+ * determine if in GFU mode or not.
+ *
+ * NOTE, Sends HOST commands that modify ec_outbuf contents.
+ *
+ * @opos return value of GFU mode object position or zero if not found
+ * @port port number to query
+ * @return 1 if in GFU mode, 0 if not, -1 if error
+ */
+static int in_gfu_mode(int *opos, int port)
+{
+	int i;
+	struct ec_params_usb_pd_get_mode_request *p =
+		(struct ec_params_usb_pd_get_mode_request *)ec_outbuf;
+	struct ec_params_usb_pd_get_mode_response *r =
+		(struct ec_params_usb_pd_get_mode_response *)ec_inbuf;
+	p->port = port;
+	p->svid_idx = 0;
+	do {
+		ec_command(EC_CMD_USB_PD_GET_AMODE, 0, p, sizeof(*p), ec_inbuf,
+			   ec_max_insize);
+		if (!r->svid || (r->svid == USB_VID_GOOGLE))
+			break;
+		p->svid_idx++;
+	} while (p->svid_idx < SVID_DISCOVERY_MAX);
+
+	if (r->svid != USB_VID_GOOGLE) {
+		fprintf(stderr, "Google VID not returned\n");
+		return -1;
+	}
+
+	*opos = 0; /* invalid ... must be 1 thru 6 */
+	for (i = 0; i < VDO_MAX_OBJECTS; i++) {
+		if (r->vdo[i] == MODE_GOOGLE_FU) {
+			*opos = i + 1;
+			break;
+		}
+	}
+
+	return r->opos == *opos;
+}
+
+/**
+ * Enter GFU mode.
+ *
+ * NOTE, Sends HOST commands that modify ec_outbuf contents.
+ *
+ * @port port number to enter GFU on.
+ * @return 1 if entered GFU mode, 0 if not, -1 if error
+ */
+static int enter_gfu_mode(int port)
+{
+	int opos;
+	struct ec_params_usb_pd_set_mode_request *p =
+		(struct ec_params_usb_pd_set_mode_request *)ec_outbuf;
+	int gfu_mode = in_gfu_mode(&opos, port);
+
+	if (gfu_mode < 0) {
+		fprintf(stderr, "Failed to query GFU mode support\n");
+		return 0;
+	} else if (!gfu_mode) {
+		if (!opos) {
+			fprintf(stderr, "Invalid object position %d\n", opos);
+			return 0;
+		}
+		p->port = port;
+		p->svid = USB_VID_GOOGLE;
+		p->opos = opos;
+		p->cmd = PD_ENTER_MODE;
+
+		ec_command(EC_CMD_USB_PD_SET_AMODE, 0, p, sizeof(*p), NULL, 0);
+		usleep(500000); /* sleep to allow time for set mode */
+		gfu_mode = in_gfu_mode(&opos, port);
+	}
+	return gfu_mode;
+}
+
+int cmd_pd_device_info(int argc, char *argv[])
+{
+	int i, rv, port;
+	char *e;
+	struct ec_params_usb_pd_info_request *p =
+		(struct ec_params_usb_pd_info_request *)ec_outbuf;
+	struct ec_params_usb_pd_rw_hash_entry *r0 =
+		(struct ec_params_usb_pd_rw_hash_entry *)ec_inbuf;
+	struct ec_params_usb_pd_discovery_entry *r1;
+
+	if (argc < 2) {
+		fprintf(stderr, "Usage: %s <port>\n", argv[0]);
+		return -1;
+	}
+
+	port = strtol(argv[1], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad port\n");
+		return -1;
+	}
+
+	p->port = port;
+	r1 = (struct ec_params_usb_pd_discovery_entry *)ec_inbuf;
+	rv = ec_command(EC_CMD_USB_PD_DISCOVERY, 0, p, sizeof(*p), r1,
+			sizeof(*r1));
+	if (rv < 0)
+		return rv;
+
+	if (!r1->vid)
+		printf("Port:%d has no discovered device\n", port);
+	else {
+		printf("Port:%d ptype:%d vid:0x%04x pid:0x%04x\n", port,
+		       r1->ptype, r1->vid, r1->pid);
+	}
+
+	if (enter_gfu_mode(port) != 1) {
+		fprintf(stderr, "Failed to enter GFU mode\n");
+		return -1;
+	}
+
+	p->port = port;
+	rv = ec_command(EC_CMD_USB_PD_DEV_INFO, 0, p, sizeof(*p), r0,
+			sizeof(*r0));
+	if (rv < 0)
+		return rv;
+
+	if (!r0->dev_id)
+		printf("Port:%d has no valid device\n", port);
+	else {
+		uint8_t *rwp = r0->dev_rw_hash;
+		printf("Port:%d DevId:%d.%d Hash:", port,
+		       HW_DEV_ID_MAJ(r0->dev_id), HW_DEV_ID_MIN(r0->dev_id));
+		for (i = 0; i < 5; i++) {
+			printf(" 0x%02x%02x%02x%02x", rwp[3], rwp[2], rwp[1],
+			       rwp[0]);
+			rwp += 4;
+		}
+		printf(" CurImg:%s\n", image_names[r0->current_image]);
+	}
+
+	return rv;
+}
+
+int cmd_flash_pd(int argc, char *argv[])
+{
+	struct ec_params_usb_pd_fw_update *p =
+		(struct ec_params_usb_pd_fw_update *)ec_outbuf;
+	int i, dev_id, port;
+	int rv, fsize, step = 96;
+	char *e;
+	char *buf;
+	char *data = (char *)p + sizeof(*p);
+
+	if (argc < 4) {
+		fprintf(stderr, "Usage: %s <dev_id> <port> <filename>\n",
+			argv[0]);
+		return -1;
+	}
+
+	dev_id = strtol(argv[1], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad device ID\n");
+		return -1;
+	}
+
+	port = strtol(argv[2], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad port\n");
+		return -1;
+	}
+
+	if (enter_gfu_mode(port) != 1) {
+		fprintf(stderr, "Failed to enter GFU mode\n");
+		return -1;
+	}
+
+	/* Read the input file */
+	buf = read_file(argv[3], &fsize);
+	if (!buf)
+		return -1;
+
+	/* Erase the current RW RSA signature */
+	fprintf(stderr, "Erasing expected RW hash\n");
+	p->dev_id = dev_id;
+	p->port = port;
+	p->cmd = USB_PD_FW_ERASE_SIG;
+	p->size = 0;
+	rv = ec_command(EC_CMD_USB_PD_FW_UPDATE, 0, p, p->size + sizeof(*p),
+			NULL, 0);
+
+	if (rv < 0)
+		goto pd_flash_error;
+
+	/* Reboot */
+	fprintf(stderr, "Rebooting\n");
+	p->dev_id = dev_id;
+	p->port = port;
+	p->cmd = USB_PD_FW_REBOOT;
+	p->size = 0;
+	rv = ec_command(EC_CMD_USB_PD_FW_UPDATE, 0, p, p->size + sizeof(*p),
+			NULL, 0);
+
+	if (rv < 0)
+		goto pd_flash_error;
+
+	usleep(3000000); /* 3sec to reboot and get CC line idle */
+
+	/* re-enter GFU after reboot */
+	if (enter_gfu_mode(port) != 1) {
+		fprintf(stderr, "Failed to enter GFU mode\n");
+		goto pd_flash_error;
+	}
+
+	/* Erase RW flash */
+	fprintf(stderr, "Erasing RW flash\n");
+	p->dev_id = dev_id;
+	p->port = port;
+	p->cmd = USB_PD_FW_FLASH_ERASE;
+	p->size = 0;
+	rv = ec_command(EC_CMD_USB_PD_FW_UPDATE, 0, p, p->size + sizeof(*p),
+			NULL, 0);
+
+	/* 3 secs should allow ample time for 2KB page erases at 40ms */
+	usleep(3000000);
+
+	if (rv < 0)
+		goto pd_flash_error;
+
+	/* Write RW flash */
+	fprintf(stderr, "Writing RW flash\n");
+	p->dev_id = dev_id;
+	p->port = port;
+	p->cmd = USB_PD_FW_FLASH_WRITE;
+	p->size = step;
+
+	for (i = 0; i < fsize; i += step) {
+		p->size = MIN(fsize - i, step);
+		memcpy(data, buf + i, p->size);
+		rv = ec_command(EC_CMD_USB_PD_FW_UPDATE, 0, p,
+				p->size + sizeof(*p), NULL, 0);
+		if (rv < 0)
+			goto pd_flash_error;
+
+		/*
+		 * TODO(crosbug.com/p/33905) throttle so EC doesn't watchdog on
+		 * other tasks.  Remove once issue resolved.
+		 */
+		usleep(10000);
+	}
+
+	/* 100msec to guarantee writes finish */
+	usleep(100000);
+
+	/* Reboot into new RW */
+	fprintf(stderr, "Rebooting PD into new RW\n");
+	p->cmd = USB_PD_FW_REBOOT;
+	p->size = 0;
+	rv = ec_command(EC_CMD_USB_PD_FW_UPDATE, 0, p, p->size + sizeof(*p),
+			NULL, 0);
+
+	if (rv < 0)
+		goto pd_flash_error;
+
+	free(buf);
+	fprintf(stderr, "Complete\n");
+	return 0;
+
+pd_flash_error:
+	free(buf);
+	fprintf(stderr, "PD flash error\n");
+	return -1;
+}
+
+int cmd_pd_set_amode(int argc, char *argv[])
+{
+	char *e;
+	struct ec_params_usb_pd_set_mode_request *p =
+		(struct ec_params_usb_pd_set_mode_request *)ec_outbuf;
+
+	if (argc < 5) {
+		fprintf(stderr, "Usage: %s <port> <svid> <opos> <cmd>\n",
+			argv[0]);
+		return -1;
+	}
+
+	p->port = strtol(argv[1], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad port\n");
+		return -1;
+	}
+
+	p->svid = strtol(argv[2], &e, 0);
+	if ((e && *e) || !p->svid) {
+		fprintf(stderr, "Bad svid\n");
+		return -1;
+	}
+
+	p->opos = strtol(argv[3], &e, 0);
+	if ((e && *e) || !p->opos) {
+		fprintf(stderr, "Bad opos\n");
+		return -1;
+	}
+
+	p->cmd = strtol(argv[4], &e, 0);
+	if ((e && *e) || (p->cmd >= PD_MODE_CMD_COUNT)) {
+		fprintf(stderr, "Bad cmd\n");
+		return -1;
+	}
+	return ec_command(EC_CMD_USB_PD_SET_AMODE, 0, p, sizeof(*p), NULL, 0);
+}
+
+int cmd_pd_get_amode(int argc, char *argv[])
+{
+	int i;
+	char *e;
+	struct ec_params_usb_pd_get_mode_request *p =
+		(struct ec_params_usb_pd_get_mode_request *)ec_outbuf;
+	struct ec_params_usb_pd_get_mode_response *r =
+		(struct ec_params_usb_pd_get_mode_response *)ec_inbuf;
+
+	if (argc < 2) {
+		fprintf(stderr, "Usage: %s <port>\n", argv[0]);
+		return -1;
+	}
+
+	p->port = strtol(argv[1], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad port\n");
+		return -1;
+	}
+
+	p->svid_idx = 0;
+	do {
+		ec_command(EC_CMD_USB_PD_GET_AMODE, 0, p, sizeof(*p), ec_inbuf,
+			   ec_max_insize);
+		if (!r->svid)
+			break;
+		printf("%cSVID:0x%04x ", (r->opos) ? '*' : ' ', r->svid);
+		for (i = 0; i < VDO_MAX_OBJECTS; i++) {
+			printf("%c0x%08x ",
+			       (r->opos && (r->opos == i + 1)) ? '*' : ' ',
+			       r->vdo[i]);
+		}
+		printf("\n");
+		p->svid_idx++;
+	} while (p->svid_idx < SVID_DISCOVERY_MAX);
+	return -1;
+}
+
+/* The I/O asm funcs exist only on x86. */
+#if defined(__i386__) || defined(__x86_64__)
+#include <sys/io.h>
+
+int cmd_serial_test(int argc, char *argv[])
+{
+	const char *c = "COM2 sample serial output from host!\r\n";
+
+	printf("Writing sample serial output to COM2\n");
+
+	while (*c) {
+		/* Wait for space in transmit FIFO */
+		while (!(inb(0x2fd) & 0x20))
+			;
+
+		/* Put the next character */
+		outb(*c++, 0x2f8);
+	}
+
+	printf("done.\n");
+	return 0;
+}
+
+int cmd_port_80_flood(int argc, char *argv[])
+{
+	int i;
+
+	for (i = 0; i < 256; i++)
+		outb(i, 0x80);
+	return 0;
+}
+#else
+int cmd_serial_test(int argc, char *argv[])
+{
+	printf("x86 specific command\n");
+	return -1;
+}
+
+int cmd_port_80_flood(int argc, char *argv[])
+{
+	printf("x86 specific command\n");
+	return -1;
+}
+#endif
+
+static void cmd_smart_discharge_usage(const char *command)
+{
+	printf("Usage: %s [hours_to_zero [hibern] [cutoff]]\n", command);
+	printf("\n");
+	printf("Set/Get smart discharge parameters\n");
+	printf("hours_to_zero: Desired hours for state of charge to zero\n");
+	printf("hibern: Discharge rate in hibernation (uA)\n");
+	printf("cutoff: Discharge rate in battery cutoff (uA)\n");
+}
+
+int cmd_smart_discharge(int argc, char *argv[])
+{
+	struct ec_params_smart_discharge *p =
+		(struct ec_params_smart_discharge *)(ec_outbuf);
+	struct ec_response_smart_discharge *r =
+		(struct ec_response_smart_discharge *)(ec_inbuf);
+	uint32_t cap;
+	char *e;
+	int rv;
+
+	if (argc > 1) {
+		if (strcmp(argv[1], "help") == 0) {
+			cmd_smart_discharge_usage(argv[0]);
+			return 0;
+		}
+		p->flags = EC_SMART_DISCHARGE_FLAGS_SET;
+		p->hours_to_zero = strtol(argv[1], &e, 0);
+		if (p->hours_to_zero < 0 || (e && *e)) {
+			perror("Bad value for [hours_to_zero]");
+			return -1;
+		}
+		if (argc == 4) {
+			p->drate.hibern = strtol(argv[2], &e, 0);
+			if (p->drate.hibern < 0 || (e && *e)) {
+				perror("Bad value for [hibern]");
+				return -1;
+			}
+			p->drate.cutoff = strtol(argv[3], &e, 0);
+			if (p->drate.cutoff < 0 || (e && *e)) {
+				perror("Bad value for [cutoff]");
+				return -1;
+			}
+		} else if (argc != 2) {
+			/* If argc != 4, it has to be 2. */
+			perror("Invalid number of parameters");
+			return -1;
+		}
+	}
+
+	rv = ec_command(EC_CMD_SMART_DISCHARGE, 0, p, sizeof(*p), r,
+			sizeof(*r));
+	if (rv < 0) {
+		perror("ERROR: EC_CMD_SMART_DISCHARGE failed");
+		return rv;
+	}
+
+	cap = read_mapped_mem32(EC_MEMMAP_BATT_LFCC);
+	if (!is_battery_range(cap)) {
+		perror("WARN: Failed to read battery capacity");
+		cap = 0;
+	}
+
+	printf("%-27s %5d h\n", "Hours to zero capacity:", r->hours_to_zero);
+	printf("%-27s %5d mAh (%d %%)\n", "Stay-up threshold:", r->dzone.stayup,
+	       cap > 0 ? r->dzone.stayup * 100 / cap : -1);
+	printf("%-27s %5d mAh (%d %%)\n", "Cutoff threshold:", r->dzone.cutoff,
+	       cap > 0 ? r->dzone.cutoff * 100 / cap : -1);
+	printf("%-27s %5d uA\n", "Hibernate discharge rate:", r->drate.hibern);
+	printf("%-27s %5d uA\n", "Cutoff discharge rate:", r->drate.cutoff);
+
+	return 0;
+}
+
+/*
+ * This boolean variable and handler are used for
+ * catching signals that translate into a quit/shutdown
+ * of a runtime loop.
+ * This is used in cmd_stress_test.
+ */
+static bool sig_quit;
+static void sig_quit_handler(int sig)
+{
+	sig_quit = true;
+}
+
+int cmd_stress_test(int argc, char *argv[])
+{
+	int i;
+	bool reboot = false;
+	time_t now;
+	time_t start_time, last_update_time;
+	unsigned int rand_seed = 0;
+	uint64_t round = 1, attempt = 1;
+	uint64_t failures = 0;
+
+	const int max_sleep_usec = 1000; /* 1ms */
+	const int loop_update_interval = 10000;
+
+	for (i = 1; i < argc; i++) {
+		if (strcmp(argv[i], "help") == 0) {
+			printf("Usage: %s [reboot] [help]\n", argv[0]);
+			printf("Stress tests the host command interface by"
+			       " repeatedly issuing common host commands.\n");
+			printf("The intent is to expose errors in kernel<->mcu"
+			       " communication, such as exceeding timeouts.\n");
+			printf("\n");
+			printf("reboot - Reboots the target before"
+			       " starting the stress test.\n");
+			printf("         This may force restart the host,"
+			       " if the main ec is the target.\n");
+			return 0;
+		} else if (strcmp(argv[i], "reboot") == 0) {
+			reboot = true;
+		} else {
+			fprintf(stderr, "Error - Unknown argument '%s'\n",
+				argv[i]);
+			return 1;
+		}
+	}
+
+	printf("Stress test tool version: %s %s %s\n", CROS_ECTOOL_VERSION,
+	       DATE, BUILDER);
+
+	start_time = time(NULL);
+	last_update_time = start_time;
+	printf("Start time: %s\n", ctime(&start_time));
+
+	if (reboot) {
+		printf("Issuing ec reboot. Expect a few early failed"
+		       " ioctl messages.\n");
+		ec_command(EC_CMD_REBOOT, 0, NULL, 0, NULL, 0);
+		sleep(2);
+	}
+
+	sig_quit = false;
+	signal(SIGINT, sig_quit_handler);
+	while (!sig_quit) {
+		int rv;
+		struct ec_response_get_version ver_r;
+		char *build_string = (char *)ec_inbuf;
+		struct ec_params_flash_protect flash_p;
+		struct ec_response_flash_protect flash_r;
+		struct ec_params_hello hello_p;
+		struct ec_response_hello hello_r;
+
+		/* Request EC Version Strings */
+		rv = ec_command(EC_CMD_GET_VERSION, 0, NULL, 0, &ver_r,
+				sizeof(ver_r));
+		if (rv < 0) {
+			failures++;
+			perror("ERROR: EC_CMD_GET_VERSION failed");
+		}
+		ver_r.version_string_ro[sizeof(ver_r.version_string_ro) - 1] =
+			'\0';
+		ver_r.version_string_rw[sizeof(ver_r.version_string_rw) - 1] =
+			'\0';
+		if (strlen(ver_r.version_string_ro) == 0) {
+			failures++;
+			fprintf(stderr, "RO version string is empty\n");
+		}
+		if (strlen(ver_r.version_string_rw) == 0) {
+			failures++;
+			fprintf(stderr, "RW version string is empty\n");
+		}
+
+		usleep(rand_r(&rand_seed) % max_sleep_usec);
+
+		/* Request EC Build String */
+		rv = ec_command(EC_CMD_GET_BUILD_INFO, 0, NULL, 0, ec_inbuf,
+				ec_max_insize);
+		if (rv < 0) {
+			failures++;
+			perror("ERROR: EC_CMD_GET_BUILD_INFO failed");
+		}
+		build_string[ec_max_insize - 1] = '\0';
+		if (strlen(build_string) == 0) {
+			failures++;
+			fprintf(stderr, "Build string is empty\n");
+		}
+
+		usleep(rand_r(&rand_seed) % max_sleep_usec);
+
+		/* Request Flash Protect Status */
+		rv = ec_command(EC_CMD_FLASH_PROTECT, EC_VER_FLASH_PROTECT,
+				&flash_p, sizeof(flash_p), &flash_r,
+				sizeof(flash_r));
+		if (rv < 0) {
+			failures++;
+			perror("ERROR: EC_CMD_FLASH_PROTECT failed");
+		}
+
+		usleep(rand_r(&rand_seed) % max_sleep_usec);
+
+		/* Request Hello */
+		hello_p.in_data = 0xa0b0c0d0;
+		rv = ec_command(EC_CMD_HELLO, 0, &hello_p, sizeof(hello_p),
+				&hello_r, sizeof(hello_r));
+		if (rv < 0) {
+			failures++;
+			perror("ERROR: EC_CMD_HELLO failed");
+		}
+		if (hello_r.out_data != HELLO_RESP(hello_p.in_data)) {
+			failures++;
+			fprintf(stderr, "Hello response was invalid.\n");
+		}
+
+		usleep(rand_r(&rand_seed) % max_sleep_usec);
+
+		if ((attempt % loop_update_interval) == 0) {
+			now = time(NULL);
+			printf("Update: attempt %" PRIu64 " round %" PRIu64
+			       " | took %.f seconds\n",
+			       attempt, round, difftime(now, last_update_time));
+			last_update_time = now;
+		}
+
+		if (attempt++ == UINT64_MAX)
+			round++;
+	}
+	printf("\n");
+
+	now = time(NULL);
+	printf("End time:        %s\n", ctime(&now));
+	printf("Total runtime:   %.f seconds\n",
+	       difftime(time(NULL), start_time));
+	printf("Total failures:  %" PRIu64 "\n", failures);
+	return 0;
+}
+
+int read_mapped_temperature(int id)
+{
+	int rv;
+
+	if (!read_mapped_mem8(EC_MEMMAP_THERMAL_VERSION)) {
+		/*
+		 *  The temp_sensor_init() is not called, which implies no
+		 * temp sensor is defined.
+		 */
+		rv = EC_TEMP_SENSOR_NOT_PRESENT;
+	} else if (id < EC_TEMP_SENSOR_ENTRIES)
+		rv = read_mapped_mem8(EC_MEMMAP_TEMP_SENSOR + id);
+	else if (read_mapped_mem8(EC_MEMMAP_THERMAL_VERSION) >= 2)
+		rv = read_mapped_mem8(EC_MEMMAP_TEMP_SENSOR_B + id -
+				      EC_TEMP_SENSOR_ENTRIES);
+	else {
+		/* Sensor in second bank, but second bank isn't supported */
+		rv = EC_TEMP_SENSOR_NOT_PRESENT;
+	}
+	return rv;
+}
+
+static int get_temp_ratio(int temp, int fan_off, int fan_max)
+{
+	if (temp < fan_off)
+		return 0;
+	if (temp > fan_max)
+		return 100;
+	return 100 * (temp - fan_off) / (fan_max - fan_off);
+}
+
+static int cmd_temperature_print(int id, int mtemp)
+{
+	struct ec_response_temp_sensor_get_info temp_r;
+	struct ec_params_temp_sensor_get_info temp_p;
+	struct ec_params_thermal_get_threshold_v1 p;
+	struct ec_thermal_config r;
+	int rc;
+	int temp = mtemp + EC_TEMP_SENSOR_OFFSET;
+
+	temp_p.id = id;
+	rc = ec_command(EC_CMD_TEMP_SENSOR_GET_INFO, 0, &temp_p, sizeof(temp_p),
+			&temp_r, sizeof(temp_r));
+	if (rc < 0)
+		return rc;
+
+	p.sensor_num = id;
+	rc = ec_command(EC_CMD_THERMAL_GET_THRESHOLD, 1, &p, sizeof(p), &r,
+			sizeof(r));
+
+	printf("%-20s  %d K (= %d C)", temp_r.sensor_name, temp, K_TO_C(temp));
+
+	if (rc >= 0)
+		/*
+		 * Check for fan_off == fan_max when their
+		 * values are either zero or non-zero
+		 */
+		if (r.temp_fan_off == r.temp_fan_max)
+			printf("        N/A (fan_off=%d K, fan_max=%d K)",
+			       r.temp_fan_off, r.temp_fan_max);
+		else
+			printf("  %10d%% (%d K and %d K)",
+			       get_temp_ratio(temp, r.temp_fan_off,
+					      r.temp_fan_max),
+			       r.temp_fan_off, r.temp_fan_max);
+	else
+		printf("%20s(rc=%d)", "error", rc);
+
+	return 0;
+}
+
+int cmd_temperature(int argc, char *argv[])
+{
+	int mtemp;
+	int id;
+	char *e;
+	const char header[] = "--sensor name -------- temperature "
+			      "-------- ratio (fan_off and fan_max) --\n";
+
+	if (argc != 2) {
+		fprintf(stderr, "Usage: %s <sensorid> | all\n", argv[0]);
+		return -1;
+	}
+
+	if (strcmp(argv[1], "all") == 0) {
+		fprintf(stdout, header);
+		for (id = 0; id < EC_MAX_TEMP_SENSOR_ENTRIES; id++) {
+			mtemp = read_mapped_temperature(id);
+			switch (mtemp) {
+			case EC_TEMP_SENSOR_NOT_PRESENT:
+				break;
+			case EC_TEMP_SENSOR_ERROR:
+				fprintf(stderr, "Sensor %d error\n", id);
+				break;
+			case EC_TEMP_SENSOR_NOT_POWERED:
+				fprintf(stderr, "Sensor %d disabled\n", id);
+				break;
+			case EC_TEMP_SENSOR_NOT_CALIBRATED:
+				fprintf(stderr, "Sensor %d not calibrated\n",
+					id);
+				break;
+			default:
+				cmd_temperature_print(id, mtemp);
+				printf("\n");
+			}
+		}
+		return 0;
+	}
+
+	id = strtol(argv[1], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad sensor ID.\n");
+		return -1;
+	}
+
+	if (id < 0 || id >= EC_MAX_TEMP_SENSOR_ENTRIES) {
+		printf("Sensor ID invalid.\n");
+		return -1;
+	}
+
+	printf("Reading temperature...");
+	mtemp = read_mapped_temperature(id);
+
+	switch (mtemp) {
+	case EC_TEMP_SENSOR_NOT_PRESENT:
+		printf("Sensor not present\n");
+		return -1;
+	case EC_TEMP_SENSOR_ERROR:
+		printf("Error\n");
+		return -1;
+	case EC_TEMP_SENSOR_NOT_POWERED:
+		printf("Sensor disabled/unpowered\n");
+		return -1;
+	case EC_TEMP_SENSOR_NOT_CALIBRATED:
+		fprintf(stderr, "Sensor not calibrated\n");
+		return -1;
+	default:
+		fprintf(stdout, "\n");
+		fprintf(stdout, header);
+		return cmd_temperature_print(id, mtemp);
+	}
+}
+
+int cmd_temp_sensor_info(int argc, char *argv[])
+{
+	struct ec_params_temp_sensor_get_info p;
+	struct ec_response_temp_sensor_get_info r;
+	int rv;
+	char *e;
+
+	if (argc != 2) {
+		fprintf(stderr, "Usage: %s <sensorid> | all\n", argv[0]);
+		return -1;
+	}
+
+	if (strcmp(argv[1], "all") == 0) {
+		for (p.id = 0; p.id < EC_MAX_TEMP_SENSOR_ENTRIES; p.id++) {
+			if (read_mapped_temperature(p.id) ==
+			    EC_TEMP_SENSOR_NOT_PRESENT)
+				continue;
+			rv = ec_command(EC_CMD_TEMP_SENSOR_GET_INFO, 0, &p,
+					sizeof(p), &r, sizeof(r));
+			if (rv < 0)
+				continue;
+			printf("%d: %d %s\n", p.id, r.sensor_type,
+			       r.sensor_name);
+		}
+		return 0;
+	}
+
+	p.id = strtol(argv[1], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad sensor ID.\n");
+		return -1;
+	}
+
+	rv = ec_command(EC_CMD_TEMP_SENSOR_GET_INFO, 0, &p, sizeof(p), &r,
+			sizeof(r));
+	if (rv < 0)
+		return rv;
+
+	printf("Sensor name: %s\n", r.sensor_name);
+	printf("Sensor type: %d\n", r.sensor_type);
+
+	return 0;
+}
+
+int cmd_thermal_get_threshold_v0(int argc, char *argv[])
+{
+	struct ec_params_thermal_get_threshold p;
+	struct ec_response_thermal_get_threshold r;
+	char *e;
+	int rv;
+
+	if (argc != 3) {
+		fprintf(stderr, "Usage: %s <sensortypeid> <thresholdid>\n",
+			argv[0]);
+		return -1;
+	}
+
+	p.sensor_type = strtol(argv[1], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad sensor type ID.\n");
+		return -1;
+	}
+
+	p.threshold_id = strtol(argv[2], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad threshold ID.\n");
+		return -1;
+	}
+
+	rv = ec_command(EC_CMD_THERMAL_GET_THRESHOLD, 0, &p, sizeof(p), &r,
+			sizeof(r));
+	if (rv < 0)
+		return rv;
+
+	printf("Threshold %d for sensor type %d is %d K.\n", p.threshold_id,
+	       p.sensor_type, r.value);
+
+	return 0;
+}
+
+int cmd_thermal_set_threshold_v0(int argc, char *argv[])
+{
+	struct ec_params_thermal_set_threshold p;
+	char *e;
+	int rv;
+
+	if (argc != 4) {
+		fprintf(stderr,
+			"Usage: %s <sensortypeid> <thresholdid> <value>\n",
+			argv[0]);
+		return -1;
+	}
+
+	p.sensor_type = strtol(argv[1], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad sensor type ID.\n");
+		return -1;
+	}
+
+	p.threshold_id = strtol(argv[2], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad threshold ID.\n");
+		return -1;
+	}
+
+	p.value = strtol(argv[3], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad threshold value.\n");
+		return -1;
+	}
+
+	rv = ec_command(EC_CMD_THERMAL_SET_THRESHOLD, 0, &p, sizeof(p), NULL,
+			0);
+	if (rv < 0)
+		return rv;
+
+	printf("Threshold %d for sensor type %d set to %d.\n", p.threshold_id,
+	       p.sensor_type, p.value);
+
+	return 0;
+}
+
+int cmd_thermal_get_threshold_v1(int argc, char *argv[])
+{
+	struct ec_params_thermal_get_threshold_v1 p;
+	struct ec_thermal_config r;
+	struct ec_params_temp_sensor_get_info pi;
+	struct ec_response_temp_sensor_get_info ri;
+	int rv;
+	int i;
+
+	printf("sensor  warn  high  halt   fan_off fan_max   name\n");
+	for (i = 0; i < EC_MAX_TEMP_SENSOR_ENTRIES; i++) {
+		if (read_mapped_temperature(i) == EC_TEMP_SENSOR_NOT_PRESENT)
+			continue;
+
+		/* ask for one */
+		p.sensor_num = i;
+		rv = ec_command(EC_CMD_THERMAL_GET_THRESHOLD, 1, &p, sizeof(p),
+				&r, sizeof(r));
+		if (rv <= 0) /* stop on first failure */
+			break;
+
+		/* ask for its name, too */
+		pi.id = i;
+		rv = ec_command(EC_CMD_TEMP_SENSOR_GET_INFO, 0, &pi, sizeof(pi),
+				&ri, sizeof(ri));
+
+		/* print what we know */
+		printf(" %2d      %3d   %3d    %3d    %3d     %3d     %s\n", i,
+		       r.temp_host[EC_TEMP_THRESH_WARN],
+		       r.temp_host[EC_TEMP_THRESH_HIGH],
+		       r.temp_host[EC_TEMP_THRESH_HALT], r.temp_fan_off,
+		       r.temp_fan_max, rv > 0 ? ri.sensor_name : "?");
+	}
+	if (i)
+		printf("(all temps in degrees Kelvin)\n");
+
+	return 0;
+}
+
+int cmd_thermal_set_threshold_v1(int argc, char *argv[])
+{
+	struct ec_params_thermal_get_threshold_v1 p;
+	struct ec_thermal_config r;
+	struct ec_params_thermal_set_threshold_v1 s;
+	int i, n, val, rv;
+	char *e;
+
+	if (argc < 3 || argc > 7) {
+		printf("Usage: %s"
+		       " sensor warn [high [shutdown [fan_off [fan_max]]]]\n",
+		       argv[0]);
+		return 1;
+	}
+
+	n = strtod(argv[1], &e);
+	if (e && *e) {
+		printf("arg %d is invalid\n", 1);
+		return 1;
+	}
+
+	p.sensor_num = n;
+	rv = ec_command(EC_CMD_THERMAL_GET_THRESHOLD, 1, &p, sizeof(p), &r,
+			sizeof(r));
+	if (rv <= 0)
+		return rv;
+
+	s.sensor_num = n;
+	s.cfg = r;
+
+	for (i = 2; i < argc; i++) {
+		val = strtod(argv[i], &e);
+		if (e && *e) {
+			printf("arg %d is invalid\n", i);
+			return 1;
+		}
+
+		if (val < 0)
+			continue;
+		switch (i) {
+		case 2:
+		case 3:
+		case 4:
+			s.cfg.temp_host[i - 2] = val;
+			break;
+		case 5:
+			s.cfg.temp_fan_off = val;
+			break;
+		case 6:
+			s.cfg.temp_fan_max = val;
+			break;
+		}
+	}
+
+	rv = ec_command(EC_CMD_THERMAL_SET_THRESHOLD, 1, &s, sizeof(s), NULL,
+			0);
+
+	return rv;
+}
+
+int cmd_thermal_get_threshold(int argc, char *argv[])
+{
+	if (ec_cmd_version_supported(EC_CMD_THERMAL_GET_THRESHOLD, 1))
+		return cmd_thermal_get_threshold_v1(argc, argv);
+	else if (ec_cmd_version_supported(EC_CMD_THERMAL_GET_THRESHOLD, 0))
+		return cmd_thermal_get_threshold_v0(argc, argv);
+
+	printf("I got nuthin.\n");
+	return -1;
+}
+
+int cmd_thermal_set_threshold(int argc, char *argv[])
+{
+	if (ec_cmd_version_supported(EC_CMD_THERMAL_SET_THRESHOLD, 1))
+		return cmd_thermal_set_threshold_v1(argc, argv);
+	else if (ec_cmd_version_supported(EC_CMD_THERMAL_SET_THRESHOLD, 0))
+		return cmd_thermal_set_threshold_v0(argc, argv);
+
+	printf("I got nuthin.\n");
+	return -1;
+}
+
+static int get_num_fans(void)
+{
+	int idx, rv;
+	struct ec_response_get_features r;
+
+	/*
+	 * iff the EC supports the GET_FEATURES,
+	 * check whether it has fan support enabled.
+	 */
+	rv = ec_command(EC_CMD_GET_FEATURES, 0, NULL, 0, &r, sizeof(r));
+	if (rv >= 0 && !(r.flags[0] & BIT(EC_FEATURE_PWM_FAN)))
+		return 0;
+
+	for (idx = 0; idx < EC_FAN_SPEED_ENTRIES; idx++) {
+		rv = read_mapped_mem16(EC_MEMMAP_FAN + 2 * idx);
+		if (rv == EC_FAN_SPEED_NOT_PRESENT)
+			break;
+	}
+
+	return idx;
+}
+
+int cmd_thermal_auto_fan_ctrl(int argc, char *argv[])
+{
+	int rv, num_fans;
+	struct ec_params_auto_fan_ctrl_v1 p_v1;
+	char *e;
+	int cmdver = 1;
+
+	if (!ec_cmd_version_supported(EC_CMD_THERMAL_AUTO_FAN_CTRL, cmdver) ||
+	    (argc == 1)) {
+		/* If no argument is provided then enable auto fan ctrl */
+		/* for all fans by using version 0 of the host command */
+
+		rv = ec_command(EC_CMD_THERMAL_AUTO_FAN_CTRL, 0, NULL, 0, NULL,
+				0);
+		if (rv < 0)
+			return rv;
+
+		printf("Automatic fan control is now on for all fans.\n");
+		return 0;
+	}
+
+	if (argc > 2 || !strcmp(argv[1], "help")) {
+		printf("Usage: %s [idx]\n", argv[0]);
+		return -1;
+	}
+
+	num_fans = get_num_fans();
+	p_v1.fan_idx = strtol(argv[1], &e, 0);
+	if ((e && *e) || (p_v1.fan_idx >= num_fans)) {
+		fprintf(stderr, "Bad fan index.\n");
+		return -1;
+	}
+
+	rv = ec_command(EC_CMD_THERMAL_AUTO_FAN_CTRL, cmdver, &p_v1,
+			sizeof(p_v1), NULL, 0);
+	if (rv < 0)
+		return rv;
+
+	printf("Automatic fan control is now on for fan %d\n", p_v1.fan_idx);
+
+	return 0;
+}
+
+static int print_fan(int idx)
+{
+	int rv = read_mapped_mem16(EC_MEMMAP_FAN + 2 * idx);
+
+	switch (rv) {
+	case EC_FAN_SPEED_NOT_PRESENT:
+		return -1;
+	case EC_FAN_SPEED_STALLED_DEPRECATED:
+		printf("Fan %d stalled (RPM: %d)\n", idx, rv);
+		break;
+	default:
+		printf("Fan %d RPM: %d\n", idx, rv);
+		break;
+	}
+
+	return 0;
+}
+
+int cmd_pwm_get_num_fans(int argc, char *argv[])
+{
+	int num_fans;
+
+	num_fans = get_num_fans();
+
+	printf("Number of fans = %d\n", num_fans);
+
+	return 0;
+}
+
+int cmd_pwm_get_fan_rpm(int argc, char *argv[])
+{
+	int i, num_fans;
+
+	num_fans = get_num_fans();
+	if (argc < 2 || !strcasecmp(argv[1], "all")) {
+		/* Print all the fan speeds */
+		for (i = 0; i < num_fans; i++)
+			print_fan(i);
+	} else {
+		char *e;
+		int idx;
+
+		idx = strtol(argv[1], &e, 0);
+		if ((e && *e) || idx < 0 || idx >= num_fans) {
+			fprintf(stderr, "Bad index.\n");
+			return -1;
+		}
+
+		print_fan(idx);
+	}
+
+	return 0;
+}
+
+int cmd_pwm_set_fan_rpm(int argc, char *argv[])
+{
+	struct ec_params_pwm_set_fan_target_rpm_v1 p_v1;
+	char *e;
+	int rv, num_fans;
+	int cmdver = 1;
+
+	if (!ec_cmd_version_supported(EC_CMD_PWM_SET_FAN_TARGET_RPM, cmdver)) {
+		struct ec_params_pwm_set_fan_target_rpm_v0 p_v0;
+
+		/* Fall back to command version 0 command */
+		cmdver = 0;
+
+		if (argc != 2) {
+			fprintf(stderr, "Usage: %s <targetrpm>\n", argv[0]);
+			return -1;
+		}
+		p_v0.rpm = strtol(argv[1], &e, 0);
+		if (e && *e) {
+			fprintf(stderr, "Bad RPM.\n");
+			return -1;
+		}
+
+		rv = ec_command(EC_CMD_PWM_SET_FAN_TARGET_RPM, cmdver, &p_v0,
+				sizeof(p_v0), NULL, 0);
+		if (rv < 0)
+			return rv;
+
+		printf("Fan target RPM set for all fans.\n");
+		return 0;
+	}
+
+	if (argc > 3 || (argc == 2 && !strcmp(argv[1], "help")) || argc == 1) {
+		printf("Usage: %s [idx] <targetrpm>\n", argv[0]);
+		printf("'%s 0 3000' - Set fan 0 RPM to 3000\n", argv[0]);
+		printf("'%s 3000' - Set all fans RPM to 3000\n", argv[0]);
+		return -1;
+	}
+
+	num_fans = get_num_fans();
+	p_v1.rpm = strtol(argv[argc - 1], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad RPM.\n");
+		return -1;
+	}
+
+	if (argc == 2) {
+		/* Reuse version 0 command if we're setting targetrpm
+		 * for all fans */
+		struct ec_params_pwm_set_fan_target_rpm_v0 p_v0;
+
+		cmdver = 0;
+		p_v0.rpm = p_v1.rpm;
+
+		rv = ec_command(EC_CMD_PWM_SET_FAN_TARGET_RPM, cmdver, &p_v0,
+				sizeof(p_v0), NULL, 0);
+		if (rv < 0)
+			return rv;
+
+		printf("Fan target RPM set for all fans.\n");
+	} else {
+		p_v1.fan_idx = strtol(argv[1], &e, 0);
+		if ((e && *e) || (p_v1.fan_idx >= num_fans)) {
+			fprintf(stderr, "Bad fan index.\n");
+			return -1;
+		}
+
+		rv = ec_command(EC_CMD_PWM_SET_FAN_TARGET_RPM, cmdver, &p_v1,
+				sizeof(p_v1), NULL, 0);
+		if (rv < 0)
+			return rv;
+
+		printf("Fan %d target RPM set.\n", p_v1.fan_idx);
+	}
+
+	return 0;
+}
+
+int cmd_pwm_get_keyboard_backlight(int argc, char *argv[])
+{
+	struct ec_response_pwm_get_keyboard_backlight r;
+	int rv;
+
+	rv = ec_command(EC_CMD_PWM_GET_KEYBOARD_BACKLIGHT, 0, NULL, 0, &r,
+			sizeof(r));
+	if (rv < 0)
+		return rv;
+
+	if (r.enabled == 1)
+		printf("Current keyboard backlight percent: %d\n", r.percent);
+	else
+		printf("Keyboard backlight disabled.\n");
+
+	return 0;
+}
+
+int cmd_pwm_set_keyboard_backlight(int argc, char *argv[])
+{
+	struct ec_params_pwm_set_keyboard_backlight p;
+	char *e;
+	int rv;
+
+	if (argc != 2) {
+		fprintf(stderr, "Usage: %s <percent>\n", argv[0]);
+		return -1;
+	}
+	p.percent = strtol(argv[1], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad percent.\n");
+		return -1;
+	}
+
+	rv = ec_command(EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT, 0, &p, sizeof(p),
+			NULL, 0);
+	if (rv < 0)
+		return rv;
+
+	printf("Keyboard backlight set.\n");
+	return 0;
+}
+
+int cmd_pwm_get_duty(int argc, char *argv[])
+{
+	struct ec_params_pwm_get_duty p;
+	struct ec_response_pwm_get_duty r;
+	char *e;
+	int rv;
+
+	if (argc != 2) {
+		fprintf(stderr, "Usage: %s <pwm_idx> | kb | disp\n", argv[0]);
+		return -1;
+	}
+
+	if (!strcmp(argv[1], "kb")) {
+		p.pwm_type = EC_PWM_TYPE_KB_LIGHT;
+		p.index = 0;
+	} else if (!strcmp(argv[1], "disp")) {
+		p.pwm_type = EC_PWM_TYPE_DISPLAY_LIGHT;
+		p.index = 0;
+	} else {
+		p.pwm_type = EC_PWM_TYPE_GENERIC;
+		p.index = strtol(argv[1], &e, 0);
+		if (e && *e) {
+			fprintf(stderr, "Bad pwm_idx\n");
+			return -1;
+		}
+	}
+
+	rv = ec_command(EC_CMD_PWM_GET_DUTY, 0, &p, sizeof(p), &r, sizeof(r));
+	if (rv < 0)
+		return rv;
+
+	printf("Current PWM duty: %d\n", r.duty);
+	return 0;
+}
+
+int cmd_pwm_set_duty(int argc, char *argv[])
+{
+	struct ec_params_pwm_set_duty p;
+	char *e;
+	int rv;
+
+	if (argc != 3) {
+		fprintf(stderr, "Usage: %s <pwm_idx> | kb | disp <duty>\n",
+			argv[0]);
+		return -1;
+	}
+
+	if (!strcmp(argv[1], "kb")) {
+		p.pwm_type = EC_PWM_TYPE_KB_LIGHT;
+		p.index = 0;
+	} else if (!strcmp(argv[1], "disp")) {
+		p.pwm_type = EC_PWM_TYPE_DISPLAY_LIGHT;
+		p.index = 0;
+	} else {
+		p.pwm_type = EC_PWM_TYPE_GENERIC;
+		p.index = strtol(argv[1], &e, 0);
+		if (e && *e) {
+			fprintf(stderr, "Bad pwm_idx\n");
+			return -1;
+		}
+	}
+
+	p.duty = strtol(argv[2], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad duty.\n");
+		return -1;
+	}
+
+	rv = ec_command(EC_CMD_PWM_SET_DUTY, 0, &p, sizeof(p), NULL, 0);
+	if (rv < 0)
+		return rv;
+
+	printf("PWM set.\n");
+	return 0;
+}
+
+int cmd_fanduty(int argc, char *argv[])
+{
+	struct ec_params_pwm_set_fan_duty_v1 p_v1;
+	char *e;
+	int rv, num_fans;
+	int cmdver = 1;
+
+	if (!ec_cmd_version_supported(EC_CMD_PWM_SET_FAN_DUTY, cmdver)) {
+		struct ec_params_pwm_set_fan_duty_v0 p_v0;
+
+		if (argc != 2) {
+			fprintf(stderr, "Usage: %s <percent>\n", argv[0]);
+			return -1;
+		}
+		p_v0.percent = strtol(argv[1], &e, 0);
+		if (e && *e) {
+			fprintf(stderr, "Bad percent arg.\n");
+			return -1;
+		}
+
+		rv = ec_command(EC_CMD_PWM_SET_FAN_DUTY, 0, &p_v0, sizeof(p_v0),
+				NULL, 0);
+		if (rv < 0)
+			return rv;
+
+		printf("Fan duty cycle set.\n");
+		return 0;
+	}
+
+	if (argc > 3 || (argc == 2 && !strcmp(argv[1], "help")) || argc == 1) {
+		printf("Usage: %s [idx] <percent>\n", argv[0]);
+		printf("'%s 0 50' - Set fan 0 duty cycle to 50 percent\n",
+		       argv[0]);
+		printf("'%s 30' - Set all fans duty cycle to 30 percent\n",
+		       argv[0]);
+		return -1;
+	}
+
+	num_fans = get_num_fans();
+	p_v1.percent = strtol(argv[argc - 1], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad percent arg.\n");
+		return -1;
+	}
+
+	if (argc == 2) {
+		/* Reuse version 0 command if we're setting duty cycle
+		 * for all fans */
+		struct ec_params_pwm_set_fan_duty_v0 p_v0;
+
+		cmdver = 0;
+		p_v0.percent = p_v1.percent;
+
+		rv = ec_command(EC_CMD_PWM_SET_FAN_DUTY, cmdver, &p_v0,
+				sizeof(p_v0), NULL, 0);
+		if (rv < 0)
+			return rv;
+
+		printf("Fan duty cycle set for all fans.\n");
+	} else {
+		p_v1.fan_idx = strtol(argv[1], &e, 0);
+		if ((e && *e) || (p_v1.fan_idx >= num_fans)) {
+			fprintf(stderr, "Bad fan index.\n");
+			return -1;
+		}
+
+		rv = ec_command(EC_CMD_PWM_SET_FAN_DUTY, cmdver, &p_v1,
+				sizeof(p_v1), NULL, 0);
+		if (rv < 0)
+			return rv;
+
+		printf("Fan %d duty cycle set.\n", p_v1.fan_idx);
+	}
+
+	return 0;
+}
+
+#define LBMSG(state) #state
+#include "lightbar_msg_list.h"
+static const char *const lightbar_cmds[] = { LIGHTBAR_MSG_LIST };
+#undef LBMSG
+
+/* Size of field <FLD> in structure <ST> */
+#define ST_FLD_SIZE(ST, FLD) sizeof(((struct ST *)0)->FLD)
+
+#define ST_CMD_SIZE ST_FLD_SIZE(ec_params_lightbar, cmd)
+#define ST_PRM_SIZE(SUBCMD) \
+	(ST_CMD_SIZE + ST_FLD_SIZE(ec_params_lightbar, SUBCMD))
+#define ST_RSP_SIZE(SUBCMD) ST_FLD_SIZE(ec_response_lightbar, SUBCMD)
+
+static const struct {
+	uint8_t insize;
+	uint8_t outsize;
+} lb_command_paramcount[] = {
+	{ ST_CMD_SIZE, ST_RSP_SIZE(dump) },
+	{ ST_CMD_SIZE, 0 },
+	{ ST_CMD_SIZE, 0 },
+	{ ST_CMD_SIZE, 0 },
+	{ ST_PRM_SIZE(set_brightness), 0 },
+	{ ST_PRM_SIZE(seq), 0 },
+	{ ST_PRM_SIZE(reg), 0 },
+	{ ST_PRM_SIZE(set_rgb), 0 },
+	{ ST_CMD_SIZE, ST_RSP_SIZE(get_seq) },
+	{ ST_PRM_SIZE(demo), 0 },
+	{ ST_CMD_SIZE, ST_RSP_SIZE(get_params_v0) },
+	{ ST_PRM_SIZE(set_params_v0), 0 },
+	{ ST_CMD_SIZE, ST_RSP_SIZE(version) },
+	{ ST_CMD_SIZE, ST_RSP_SIZE(get_brightness) },
+	{ ST_PRM_SIZE(get_rgb), ST_RSP_SIZE(get_rgb) },
+	{ ST_CMD_SIZE, ST_RSP_SIZE(get_demo) },
+	{ ST_CMD_SIZE, ST_RSP_SIZE(get_params_v1) },
+	{ ST_PRM_SIZE(set_params_v1), 0 },
+	{ ST_PRM_SIZE(set_program), 0 },
+	{ ST_PRM_SIZE(manual_suspend_ctrl), 0 },
+	{ ST_CMD_SIZE, 0 },
+	{ ST_CMD_SIZE, 0 },
+	{ ST_CMD_SIZE, ST_RSP_SIZE(get_params_v2_timing) },
+	{ ST_PRM_SIZE(set_v2par_timing), 0 },
+	{ ST_CMD_SIZE, ST_RSP_SIZE(get_params_v2_tap) },
+	{ ST_PRM_SIZE(set_v2par_tap), 0 },
+	{ ST_CMD_SIZE, ST_RSP_SIZE(get_params_v2_osc) },
+	{ ST_PRM_SIZE(set_v2par_osc), 0 },
+	{ ST_CMD_SIZE, ST_RSP_SIZE(get_params_v2_bright) },
+	{ ST_PRM_SIZE(set_v2par_bright), 0 },
+	{ ST_CMD_SIZE, ST_RSP_SIZE(get_params_v2_thlds) },
+	{ ST_PRM_SIZE(set_v2par_thlds), 0 },
+	{ ST_CMD_SIZE, ST_RSP_SIZE(get_params_v2_colors) },
+	{ ST_PRM_SIZE(set_v2par_colors), 0 },
+};
+BUILD_ASSERT(ARRAY_SIZE(lb_command_paramcount) == LIGHTBAR_NUM_CMDS);
+
+#undef ST_CMD_SIZE
+#undef ST_PRM_SIZE
+#undef ST_RSP_SIZE
+
+static int lb_help(const char *cmd)
+{
+	printf("Usage:\n");
+	printf("  %s                         - dump all regs\n", cmd);
+	printf("  %s off                     - enter standby\n", cmd);
+	printf("  %s on                      - leave standby\n", cmd);
+	printf("  %s init                    - load default vals\n", cmd);
+	printf("  %s brightness [NUM]        - get/set intensity(0-ff)\n", cmd);
+	printf("  %s seq [NUM|SEQUENCE]      - run given pattern"
+	       " (no arg for list)\n",
+	       cmd);
+	printf("  %s CTRL REG VAL            - set LED controller regs\n", cmd);
+	printf("  %s LED RED GREEN BLUE      - set color manually"
+	       " (LED=4 for all)\n",
+	       cmd);
+	printf("  %s LED                     - get current LED color\n", cmd);
+	printf("  %s demo [0|1]              - turn demo mode on & off\n", cmd);
+	printf("  %s params [setfile]        - get params"
+	       " (or set from file)\n",
+	       cmd);
+	printf("  %s params2 group [setfile] - get params by group\n"
+	       " (or set from file)\n",
+	       cmd);
+	printf("  %s program file            - load program from file\n", cmd);
+	return 0;
+}
+
+static uint8_t lb_find_msg_by_name(const char *str)
+{
+	uint8_t i;
+	for (i = 0; i < LIGHTBAR_NUM_SEQUENCES; i++)
+		if (!strcasecmp(str, lightbar_cmds[i]))
+			return i;
+
+	return LIGHTBAR_NUM_SEQUENCES;
+}
+
+static int lb_do_cmd(enum lightbar_command cmd, struct ec_params_lightbar *in,
+		     struct ec_response_lightbar *out)
+{
+	int rv;
+	in->cmd = cmd;
+	rv = ec_command(EC_CMD_LIGHTBAR_CMD, 0, in,
+			lb_command_paramcount[cmd].insize, out,
+			lb_command_paramcount[cmd].outsize);
+	return (rv < 0 ? rv : 0);
+}
+
+static int lb_show_msg_names(void)
+{
+	int i, current_state;
+	struct ec_params_lightbar param;
+	struct ec_response_lightbar resp;
+
+	i = lb_do_cmd(LIGHTBAR_CMD_GET_SEQ, &param, &resp);
+	if (i < 0)
+		return i;
+	current_state = resp.get_seq.num;
+
+	printf("sequence names:");
+	for (i = 0; i < LIGHTBAR_NUM_SEQUENCES; i++)
+		printf(" %s", lightbar_cmds[i]);
+	printf("\nCurrent = 0x%x %s\n", current_state,
+	       lightbar_cmds[current_state]);
+
+	return 0;
+}
+
+static int lb_read_params_v0_from_file(const char *filename,
+				       struct lightbar_params_v0 *p)
+{
+	FILE *fp;
+	char buf[80];
+	int val[4];
+	int r = 1;
+	int line = 0;
+	int want, got;
+	int i;
+
+	fp = fopen(filename, "rb");
+	if (!fp) {
+		fprintf(stderr, "Can't open %s: %s\n", filename,
+			strerror(errno));
+		return 1;
+	}
+
+	/* We must read the correct number of params from each line */
+#define READ(N)                                                             \
+	do {                                                                \
+		line++;                                                     \
+		want = (N);                                                 \
+		got = -1;                                                   \
+		if (!fgets(buf, sizeof(buf), fp))                           \
+			goto done;                                          \
+		got = sscanf(buf, "%i %i %i %i", &val[0], &val[1], &val[2], \
+			     &val[3]);                                      \
+		if (want != got)                                            \
+			goto done;                                          \
+	} while (0)
+
+	/* Do it */
+	READ(1);
+	p->google_ramp_up = val[0];
+	READ(1);
+	p->google_ramp_down = val[0];
+	READ(1);
+	p->s3s0_ramp_up = val[0];
+	READ(1);
+	p->s0_tick_delay[0] = val[0];
+	READ(1);
+	p->s0_tick_delay[1] = val[0];
+	READ(1);
+	p->s0a_tick_delay[0] = val[0];
+	READ(1);
+	p->s0a_tick_delay[1] = val[0];
+	READ(1);
+	p->s0s3_ramp_down = val[0];
+	READ(1);
+	p->s3_sleep_for = val[0];
+	READ(1);
+	p->s3_ramp_up = val[0];
+	READ(1);
+	p->s3_ramp_down = val[0];
+	READ(1);
+	p->new_s0 = val[0];
+
+	READ(2);
+	p->osc_min[0] = val[0];
+	p->osc_min[1] = val[1];
+	READ(2);
+	p->osc_max[0] = val[0];
+	p->osc_max[1] = val[1];
+	READ(2);
+	p->w_ofs[0] = val[0];
+	p->w_ofs[1] = val[1];
+
+	READ(2);
+	p->bright_bl_off_fixed[0] = val[0];
+	p->bright_bl_off_fixed[1] = val[1];
+
+	READ(2);
+	p->bright_bl_on_min[0] = val[0];
+	p->bright_bl_on_min[1] = val[1];
+
+	READ(2);
+	p->bright_bl_on_max[0] = val[0];
+	p->bright_bl_on_max[1] = val[1];
+
+	READ(3);
+	p->battery_threshold[0] = val[0];
+	p->battery_threshold[1] = val[1];
+	p->battery_threshold[2] = val[2];
+
+	READ(4);
+	p->s0_idx[0][0] = val[0];
+	p->s0_idx[0][1] = val[1];
+	p->s0_idx[0][2] = val[2];
+	p->s0_idx[0][3] = val[3];
+
+	READ(4);
+	p->s0_idx[1][0] = val[0];
+	p->s0_idx[1][1] = val[1];
+	p->s0_idx[1][2] = val[2];
+	p->s0_idx[1][3] = val[3];
+
+	READ(4);
+	p->s3_idx[0][0] = val[0];
+	p->s3_idx[0][1] = val[1];
+	p->s3_idx[0][2] = val[2];
+	p->s3_idx[0][3] = val[3];
+
+	READ(4);
+	p->s3_idx[1][0] = val[0];
+	p->s3_idx[1][1] = val[1];
+	p->s3_idx[1][2] = val[2];
+	p->s3_idx[1][3] = val[3];
+
+	for (i = 0; i < ARRAY_SIZE(p->color); i++) {
+		READ(3);
+		p->color[i].r = val[0];
+		p->color[i].g = val[1];
+		p->color[i].b = val[2];
+	}
+
+#undef READ
+
+	/* Yay */
+	r = 0;
+done:
+	if (r)
+		fprintf(stderr, "problem with line %d: wanted %d, got %d\n",
+			line, want, got);
+	fclose(fp);
+	return r;
+}
+
+static void lb_show_params_v0(const struct lightbar_params_v0 *p)
+{
+	int i;
+
+	printf("%d\t\t# .google_ramp_up\n", p->google_ramp_up);
+	printf("%d\t\t# .google_ramp_down\n", p->google_ramp_down);
+	printf("%d\t\t# .s3s0_ramp_up\n", p->s3s0_ramp_up);
+	printf("%d\t\t# .s0_tick_delay (battery)\n", p->s0_tick_delay[0]);
+	printf("%d\t\t# .s0_tick_delay (AC)\n", p->s0_tick_delay[1]);
+	printf("%d\t\t# .s0a_tick_delay (battery)\n", p->s0a_tick_delay[0]);
+	printf("%d\t\t# .s0a_tick_delay (AC)\n", p->s0a_tick_delay[1]);
+	printf("%d\t\t# .s0s3_ramp_down\n", p->s0s3_ramp_down);
+	printf("%d\t# .s3_sleep_for\n", p->s3_sleep_for);
+	printf("%d\t\t# .s3_ramp_up\n", p->s3_ramp_up);
+	printf("%d\t\t# .s3_ramp_down\n", p->s3_ramp_down);
+	printf("%d\t\t# .new_s0\n", p->new_s0);
+	printf("0x%02x 0x%02x\t# .osc_min (battery, AC)\n", p->osc_min[0],
+	       p->osc_min[1]);
+	printf("0x%02x 0x%02x\t# .osc_max (battery, AC)\n", p->osc_max[0],
+	       p->osc_max[1]);
+	printf("%d %d\t\t# .w_ofs (battery, AC)\n", p->w_ofs[0], p->w_ofs[1]);
+	printf("0x%02x 0x%02x\t# .bright_bl_off_fixed (battery, AC)\n",
+	       p->bright_bl_off_fixed[0], p->bright_bl_off_fixed[1]);
+	printf("0x%02x 0x%02x\t# .bright_bl_on_min (battery, AC)\n",
+	       p->bright_bl_on_min[0], p->bright_bl_on_min[1]);
+	printf("0x%02x 0x%02x\t# .bright_bl_on_max (battery, AC)\n",
+	       p->bright_bl_on_max[0], p->bright_bl_on_max[1]);
+	printf("%d %d %d\t\t# .battery_threshold\n", p->battery_threshold[0],
+	       p->battery_threshold[1], p->battery_threshold[2]);
+	printf("%d %d %d %d\t\t# .s0_idx[] (battery)\n", p->s0_idx[0][0],
+	       p->s0_idx[0][1], p->s0_idx[0][2], p->s0_idx[0][3]);
+	printf("%d %d %d %d\t\t# .s0_idx[] (AC)\n", p->s0_idx[1][0],
+	       p->s0_idx[1][1], p->s0_idx[1][2], p->s0_idx[1][3]);
+	printf("%d %d %d %d\t# .s3_idx[] (battery)\n", p->s3_idx[0][0],
+	       p->s3_idx[0][1], p->s3_idx[0][2], p->s3_idx[0][3]);
+	printf("%d %d %d %d\t# .s3_idx[] (AC)\n", p->s3_idx[1][0],
+	       p->s3_idx[1][1], p->s3_idx[1][2], p->s3_idx[1][3]);
+	for (i = 0; i < ARRAY_SIZE(p->color); i++)
+		printf("0x%02x 0x%02x 0x%02x\t# color[%d]\n", p->color[i].r,
+		       p->color[i].g, p->color[i].b, i);
+}
+
+static int lb_read_params_v1_from_file(const char *filename,
+				       struct lightbar_params_v1 *p)
+{
+	FILE *fp;
+	char buf[80];
+	int val[4];
+	int r = 1;
+	int line = 0;
+	int want, got;
+	int i;
+
+	fp = fopen(filename, "rb");
+	if (!fp) {
+		fprintf(stderr, "Can't open %s: %s\n", filename,
+			strerror(errno));
+		return 1;
+	}
+
+	/* We must read the correct number of params from each line */
+#define READ(N)                                                             \
+	do {                                                                \
+		line++;                                                     \
+		want = (N);                                                 \
+		got = -1;                                                   \
+		if (!fgets(buf, sizeof(buf), fp))                           \
+			goto done;                                          \
+		got = sscanf(buf, "%i %i %i %i", &val[0], &val[1], &val[2], \
+			     &val[3]);                                      \
+		if (want != got)                                            \
+			goto done;                                          \
+	} while (0)
+
+	/* Do it */
+	READ(1);
+	p->google_ramp_up = val[0];
+	READ(1);
+	p->google_ramp_down = val[0];
+	READ(1);
+	p->s3s0_ramp_up = val[0];
+	READ(1);
+	p->s0_tick_delay[0] = val[0];
+	READ(1);
+	p->s0_tick_delay[1] = val[0];
+	READ(1);
+	p->s0a_tick_delay[0] = val[0];
+	READ(1);
+	p->s0a_tick_delay[1] = val[0];
+	READ(1);
+	p->s0s3_ramp_down = val[0];
+	READ(1);
+	p->s3_sleep_for = val[0];
+	READ(1);
+	p->s3_ramp_up = val[0];
+	READ(1);
+	p->s3_ramp_down = val[0];
+	READ(1);
+	p->tap_tick_delay = val[0];
+	READ(1);
+	p->tap_gate_delay = val[0];
+	READ(1);
+	p->tap_display_time = val[0];
+
+	READ(1);
+	p->tap_pct_red = val[0];
+	READ(1);
+	p->tap_pct_green = val[0];
+	READ(1);
+	p->tap_seg_min_on = val[0];
+	READ(1);
+	p->tap_seg_max_on = val[0];
+	READ(1);
+	p->tap_seg_osc = val[0];
+	READ(3);
+	p->tap_idx[0] = val[0];
+	p->tap_idx[1] = val[1];
+	p->tap_idx[2] = val[2];
+
+	READ(2);
+	p->osc_min[0] = val[0];
+	p->osc_min[1] = val[1];
+	READ(2);
+	p->osc_max[0] = val[0];
+	p->osc_max[1] = val[1];
+	READ(2);
+	p->w_ofs[0] = val[0];
+	p->w_ofs[1] = val[1];
+
+	READ(2);
+	p->bright_bl_off_fixed[0] = val[0];
+	p->bright_bl_off_fixed[1] = val[1];
+
+	READ(2);
+	p->bright_bl_on_min[0] = val[0];
+	p->bright_bl_on_min[1] = val[1];
+
+	READ(2);
+	p->bright_bl_on_max[0] = val[0];
+	p->bright_bl_on_max[1] = val[1];
+
+	READ(3);
+	p->battery_threshold[0] = val[0];
+	p->battery_threshold[1] = val[1];
+	p->battery_threshold[2] = val[2];
+
+	READ(4);
+	p->s0_idx[0][0] = val[0];
+	p->s0_idx[0][1] = val[1];
+	p->s0_idx[0][2] = val[2];
+	p->s0_idx[0][3] = val[3];
+
+	READ(4);
+	p->s0_idx[1][0] = val[0];
+	p->s0_idx[1][1] = val[1];
+	p->s0_idx[1][2] = val[2];
+	p->s0_idx[1][3] = val[3];
+
+	READ(4);
+	p->s3_idx[0][0] = val[0];
+	p->s3_idx[0][1] = val[1];
+	p->s3_idx[0][2] = val[2];
+	p->s3_idx[0][3] = val[3];
+
+	READ(4);
+	p->s3_idx[1][0] = val[0];
+	p->s3_idx[1][1] = val[1];
+	p->s3_idx[1][2] = val[2];
+	p->s3_idx[1][3] = val[3];
+
+	for (i = 0; i < ARRAY_SIZE(p->color); i++) {
+		READ(3);
+		p->color[i].r = val[0];
+		p->color[i].g = val[1];
+		p->color[i].b = val[2];
+	}
+
+#undef READ
+
+	/* Yay */
+	r = 0;
+done:
+	if (r)
+		fprintf(stderr, "problem with line %d: wanted %d, got %d\n",
+			line, want, got);
+	fclose(fp);
+	return r;
+}
+
+static void lb_show_params_v1(const struct lightbar_params_v1 *p)
+{
+	int i;
+
+	printf("%d\t\t# .google_ramp_up\n", p->google_ramp_up);
+	printf("%d\t\t# .google_ramp_down\n", p->google_ramp_down);
+	printf("%d\t\t# .s3s0_ramp_up\n", p->s3s0_ramp_up);
+	printf("%d\t\t# .s0_tick_delay (battery)\n", p->s0_tick_delay[0]);
+	printf("%d\t\t# .s0_tick_delay (AC)\n", p->s0_tick_delay[1]);
+	printf("%d\t\t# .s0a_tick_delay (battery)\n", p->s0a_tick_delay[0]);
+	printf("%d\t\t# .s0a_tick_delay (AC)\n", p->s0a_tick_delay[1]);
+	printf("%d\t\t# .s0s3_ramp_down\n", p->s0s3_ramp_down);
+	printf("%d\t\t# .s3_sleep_for\n", p->s3_sleep_for);
+	printf("%d\t\t# .s3_ramp_up\n", p->s3_ramp_up);
+	printf("%d\t\t# .s3_ramp_down\n", p->s3_ramp_down);
+	printf("%d\t\t# .tap_tick_delay\n", p->tap_tick_delay);
+	printf("%d\t\t# .tap_gate_delay\n", p->tap_gate_delay);
+	printf("%d\t\t# .tap_display_time\n", p->tap_display_time);
+	printf("%d\t\t# .tap_pct_red\n", p->tap_pct_red);
+	printf("%d\t\t# .tap_pct_green\n", p->tap_pct_green);
+	printf("%d\t\t# .tap_seg_min_on\n", p->tap_seg_min_on);
+	printf("%d\t\t# .tap_seg_max_on\n", p->tap_seg_max_on);
+	printf("%d\t\t# .tap_seg_osc\n", p->tap_seg_osc);
+	printf("%d %d %d\t\t# .tap_idx\n", p->tap_idx[0], p->tap_idx[1],
+	       p->tap_idx[2]);
+	printf("0x%02x 0x%02x\t# .osc_min (battery, AC)\n", p->osc_min[0],
+	       p->osc_min[1]);
+	printf("0x%02x 0x%02x\t# .osc_max (battery, AC)\n", p->osc_max[0],
+	       p->osc_max[1]);
+	printf("%d %d\t\t# .w_ofs (battery, AC)\n", p->w_ofs[0], p->w_ofs[1]);
+	printf("0x%02x 0x%02x\t# .bright_bl_off_fixed (battery, AC)\n",
+	       p->bright_bl_off_fixed[0], p->bright_bl_off_fixed[1]);
+	printf("0x%02x 0x%02x\t# .bright_bl_on_min (battery, AC)\n",
+	       p->bright_bl_on_min[0], p->bright_bl_on_min[1]);
+	printf("0x%02x 0x%02x\t# .bright_bl_on_max (battery, AC)\n",
+	       p->bright_bl_on_max[0], p->bright_bl_on_max[1]);
+	printf("%d %d %d\t# .battery_threshold\n", p->battery_threshold[0],
+	       p->battery_threshold[1], p->battery_threshold[2]);
+	printf("%d %d %d %d\t\t# .s0_idx[] (battery)\n", p->s0_idx[0][0],
+	       p->s0_idx[0][1], p->s0_idx[0][2], p->s0_idx[0][3]);
+	printf("%d %d %d %d\t\t# .s0_idx[] (AC)\n", p->s0_idx[1][0],
+	       p->s0_idx[1][1], p->s0_idx[1][2], p->s0_idx[1][3]);
+	printf("%d %d %d %d\t# .s3_idx[] (battery)\n", p->s3_idx[0][0],
+	       p->s3_idx[0][1], p->s3_idx[0][2], p->s3_idx[0][3]);
+	printf("%d %d %d %d\t# .s3_idx[] (AC)\n", p->s3_idx[1][0],
+	       p->s3_idx[1][1], p->s3_idx[1][2], p->s3_idx[1][3]);
+	for (i = 0; i < ARRAY_SIZE(p->color); i++)
+		printf("0x%02x 0x%02x 0x%02x\t# color[%d]\n", p->color[i].r,
+		       p->color[i].g, p->color[i].b, i);
+}
+
+static int lb_rd_timing_v2par_from_file(const char *filename,
+					struct lightbar_params_v2_timing *p)
+{
+	FILE *fp;
+	char buf[80];
+	int val[4];
+	int r = 1;
+	int line = 0;
+	int want, got;
+
+	fp = fopen(filename, "rb");
+	if (!fp) {
+		fprintf(stderr, "Can't open %s: %s\n", filename,
+			strerror(errno));
+		return 1;
+	}
+
+	/* We must read the correct number of params from each line */
+#define READ(N)                                                             \
+	do {                                                                \
+		line++;                                                     \
+		want = (N);                                                 \
+		got = -1;                                                   \
+		if (!fgets(buf, sizeof(buf), fp))                           \
+			goto done;                                          \
+		got = sscanf(buf, "%i %i %i %i", &val[0], &val[1], &val[2], \
+			     &val[3]);                                      \
+		if (want != got)                                            \
+			goto done;                                          \
+	} while (0)
+
+	READ(1);
+	p->google_ramp_up = val[0];
+	READ(1);
+	p->google_ramp_down = val[0];
+	READ(1);
+	p->s3s0_ramp_up = val[0];
+	READ(1);
+	p->s0_tick_delay[0] = val[0];
+	READ(1);
+	p->s0_tick_delay[1] = val[0];
+	READ(1);
+	p->s0a_tick_delay[0] = val[0];
+	READ(1);
+	p->s0a_tick_delay[1] = val[0];
+	READ(1);
+	p->s0s3_ramp_down = val[0];
+	READ(1);
+	p->s3_sleep_for = val[0];
+	READ(1);
+	p->s3_ramp_up = val[0];
+	READ(1);
+	p->s3_ramp_down = val[0];
+	READ(1);
+	p->tap_tick_delay = val[0];
+	READ(1);
+	p->tap_gate_delay = val[0];
+	READ(1);
+	p->tap_display_time = val[0];
+#undef READ
+
+	/* Yay */
+	r = 0;
+done:
+	if (r)
+		fprintf(stderr, "problem with line %d: wanted %d, got %d\n",
+			line, want, got);
+	fclose(fp);
+	return r;
+}
+
+static int lb_rd_tap_v2par_from_file(const char *filename,
+				     struct lightbar_params_v2_tap *p)
+{
+	FILE *fp;
+	char buf[80];
+	int val[4];
+	int r = 1;
+	int line = 0;
+	int want, got;
+
+	fp = fopen(filename, "rb");
+	if (!fp) {
+		fprintf(stderr, "Can't open %s: %s\n", filename,
+			strerror(errno));
+		return 1;
+	}
+
+	/* We must read the correct number of params from each line */
+#define READ(N)                                                             \
+	do {                                                                \
+		line++;                                                     \
+		want = (N);                                                 \
+		got = -1;                                                   \
+		if (!fgets(buf, sizeof(buf), fp))                           \
+			goto done;                                          \
+		got = sscanf(buf, "%i %i %i %i", &val[0], &val[1], &val[2], \
+			     &val[3]);                                      \
+		if (want != got)                                            \
+			goto done;                                          \
+	} while (0)
+
+	READ(1);
+	p->tap_pct_red = val[0];
+	READ(1);
+	p->tap_pct_green = val[0];
+	READ(1);
+	p->tap_seg_min_on = val[0];
+	READ(1);
+	p->tap_seg_max_on = val[0];
+	READ(1);
+	p->tap_seg_osc = val[0];
+	READ(3);
+	p->tap_idx[0] = val[0];
+	p->tap_idx[1] = val[1];
+	p->tap_idx[2] = val[2];
+#undef READ
+
+	/* Yay */
+	r = 0;
+done:
+	if (r)
+		fprintf(stderr, "problem with line %d: wanted %d, got %d\n",
+			line, want, got);
+	fclose(fp);
+	return r;
+}
+
+static int lb_rd_osc_v2par_from_file(const char *filename,
+				     struct lightbar_params_v2_oscillation *p)
+{
+	FILE *fp;
+	char buf[80];
+	int val[4];
+	int r = 1;
+	int line = 0;
+	int want, got;
+
+	fp = fopen(filename, "rb");
+	if (!fp) {
+		fprintf(stderr, "Can't open %s: %s\n", filename,
+			strerror(errno));
+		return 1;
+	}
+
+	/* We must read the correct number of params from each line */
+#define READ(N)                                                             \
+	do {                                                                \
+		line++;                                                     \
+		want = (N);                                                 \
+		got = -1;                                                   \
+		if (!fgets(buf, sizeof(buf), fp))                           \
+			goto done;                                          \
+		got = sscanf(buf, "%i %i %i %i", &val[0], &val[1], &val[2], \
+			     &val[3]);                                      \
+		if (want != got)                                            \
+			goto done;                                          \
+	} while (0)
+
+	READ(2);
+	p->osc_min[0] = val[0];
+	p->osc_min[1] = val[1];
+	READ(2);
+	p->osc_max[0] = val[0];
+	p->osc_max[1] = val[1];
+	READ(2);
+	p->w_ofs[0] = val[0];
+	p->w_ofs[1] = val[1];
+#undef READ
+
+	/* Yay */
+	r = 0;
+done:
+	if (r)
+		fprintf(stderr, "problem with line %d: wanted %d, got %d\n",
+			line, want, got);
+	fclose(fp);
+	return r;
+}
+
+static int lb_rd_bright_v2par_from_file(const char *filename,
+					struct lightbar_params_v2_brightness *p)
+{
+	FILE *fp;
+	char buf[80];
+	int val[4];
+	int r = 1;
+	int line = 0;
+	int want, got;
+
+	fp = fopen(filename, "rb");
+	if (!fp) {
+		fprintf(stderr, "Can't open %s: %s\n", filename,
+			strerror(errno));
+		return 1;
+	}
+
+	/* We must read the correct number of params from each line */
+#define READ(N)                                                             \
+	do {                                                                \
+		line++;                                                     \
+		want = (N);                                                 \
+		got = -1;                                                   \
+		if (!fgets(buf, sizeof(buf), fp))                           \
+			goto done;                                          \
+		got = sscanf(buf, "%i %i %i %i", &val[0], &val[1], &val[2], \
+			     &val[3]);                                      \
+		if (want != got)                                            \
+			goto done;                                          \
+	} while (0)
+
+	READ(2);
+	p->bright_bl_off_fixed[0] = val[0];
+	p->bright_bl_off_fixed[1] = val[1];
+
+	READ(2);
+	p->bright_bl_on_min[0] = val[0];
+	p->bright_bl_on_min[1] = val[1];
+
+	READ(2);
+	p->bright_bl_on_max[0] = val[0];
+	p->bright_bl_on_max[1] = val[1];
+#undef READ
+
+	/* Yay */
+	r = 0;
+done:
+	if (r)
+		fprintf(stderr, "problem with line %d: wanted %d, got %d\n",
+			line, want, got);
+	fclose(fp);
+	return r;
+}
+
+static int lb_rd_thlds_v2par_from_file(const char *filename,
+				       struct lightbar_params_v2_thresholds *p)
+{
+	FILE *fp;
+	char buf[80];
+	int val[4];
+	int r = 1;
+	int line = 0;
+	int want, got;
+
+	fp = fopen(filename, "rb");
+	if (!fp) {
+		fprintf(stderr, "Can't open %s: %s\n", filename,
+			strerror(errno));
+		return 1;
+	}
+
+	/* We must read the correct number of params from each line */
+#define READ(N)                                                             \
+	do {                                                                \
+		line++;                                                     \
+		want = (N);                                                 \
+		got = -1;                                                   \
+		if (!fgets(buf, sizeof(buf), fp))                           \
+			goto done;                                          \
+		got = sscanf(buf, "%i %i %i %i", &val[0], &val[1], &val[2], \
+			     &val[3]);                                      \
+		if (want != got)                                            \
+			goto done;                                          \
+	} while (0)
+
+	READ(3);
+	p->battery_threshold[0] = val[0];
+	p->battery_threshold[1] = val[1];
+	p->battery_threshold[2] = val[2];
+#undef READ
+
+	/* Yay */
+	r = 0;
+done:
+	if (r)
+		fprintf(stderr, "problem with line %d: wanted %d, got %d\n",
+			line, want, got);
+	fclose(fp);
+	return r;
+}
+
+static int lb_rd_colors_v2par_from_file(const char *filename,
+					struct lightbar_params_v2_colors *p)
+{
+	FILE *fp;
+	char buf[80];
+	int val[4];
+	int r = 1;
+	int line = 0;
+	int want, got;
+	int i;
+
+	fp = fopen(filename, "rb");
+	if (!fp) {
+		fprintf(stderr, "Can't open %s: %s\n", filename,
+			strerror(errno));
+		return 1;
+	}
+
+	/* We must read the correct number of params from each line */
+#define READ(N)                                                             \
+	do {                                                                \
+		line++;                                                     \
+		want = (N);                                                 \
+		got = -1;                                                   \
+		if (!fgets(buf, sizeof(buf), fp))                           \
+			goto done;                                          \
+		got = sscanf(buf, "%i %i %i %i", &val[0], &val[1], &val[2], \
+			     &val[3]);                                      \
+		if (want != got)                                            \
+			goto done;                                          \
+	} while (0)
+
+	READ(4);
+	p->s0_idx[0][0] = val[0];
+	p->s0_idx[0][1] = val[1];
+	p->s0_idx[0][2] = val[2];
+	p->s0_idx[0][3] = val[3];
+
+	READ(4);
+	p->s0_idx[1][0] = val[0];
+	p->s0_idx[1][1] = val[1];
+	p->s0_idx[1][2] = val[2];
+	p->s0_idx[1][3] = val[3];
+
+	READ(4);
+	p->s3_idx[0][0] = val[0];
+	p->s3_idx[0][1] = val[1];
+	p->s3_idx[0][2] = val[2];
+	p->s3_idx[0][3] = val[3];
+
+	READ(4);
+	p->s3_idx[1][0] = val[0];
+	p->s3_idx[1][1] = val[1];
+	p->s3_idx[1][2] = val[2];
+	p->s3_idx[1][3] = val[3];
+	for (i = 0; i < ARRAY_SIZE(p->color); i++) {
+		READ(3);
+		p->color[i].r = val[0];
+		p->color[i].g = val[1];
+		p->color[i].b = val[2];
+	}
+
+#undef READ
+
+	/* Yay */
+	r = 0;
+done:
+	if (r)
+		fprintf(stderr, "problem with line %d: wanted %d, got %d\n",
+			line, want, got);
+	fclose(fp);
+	return r;
+}
+
+static void lb_show_v2par_timing(const struct lightbar_params_v2_timing *p)
+{
+	printf("%d\t\t# .google_ramp_up\n", p->google_ramp_up);
+	printf("%d\t\t# .google_ramp_down\n", p->google_ramp_down);
+	printf("%d\t\t# .s3s0_ramp_up\n", p->s3s0_ramp_up);
+	printf("%d\t\t# .s0_tick_delay (battery)\n", p->s0_tick_delay[0]);
+	printf("%d\t\t# .s0_tick_delay (AC)\n", p->s0_tick_delay[1]);
+	printf("%d\t\t# .s0a_tick_delay (battery)\n", p->s0a_tick_delay[0]);
+	printf("%d\t\t# .s0a_tick_delay (AC)\n", p->s0a_tick_delay[1]);
+	printf("%d\t\t# .s0s3_ramp_down\n", p->s0s3_ramp_down);
+	printf("%d\t\t# .s3_sleep_for\n", p->s3_sleep_for);
+	printf("%d\t\t# .s3_ramp_up\n", p->s3_ramp_up);
+	printf("%d\t\t# .s3_ramp_down\n", p->s3_ramp_down);
+	printf("%d\t\t# .tap_tick_delay\n", p->tap_tick_delay);
+	printf("%d\t\t# .tap_gate_delay\n", p->tap_gate_delay);
+	printf("%d\t\t# .tap_display_time\n", p->tap_display_time);
+}
+
+static void lb_show_v2par_tap(const struct lightbar_params_v2_tap *p)
+{
+	printf("%d\t\t# .tap_pct_red\n", p->tap_pct_red);
+	printf("%d\t\t# .tap_pct_green\n", p->tap_pct_green);
+	printf("%d\t\t# .tap_seg_min_on\n", p->tap_seg_min_on);
+	printf("%d\t\t# .tap_seg_max_on\n", p->tap_seg_max_on);
+	printf("%d\t\t# .tap_seg_osc\n", p->tap_seg_osc);
+	printf("%d %d %d\t\t# .tap_idx\n", p->tap_idx[0], p->tap_idx[1],
+	       p->tap_idx[2]);
+}
+
+static void lb_show_v2par_osc(const struct lightbar_params_v2_oscillation *p)
+{
+	printf("0x%02x 0x%02x\t# .osc_min (battery, AC)\n", p->osc_min[0],
+	       p->osc_min[1]);
+	printf("0x%02x 0x%02x\t# .osc_max (battery, AC)\n", p->osc_max[0],
+	       p->osc_max[1]);
+	printf("%d %d\t\t# .w_ofs (battery, AC)\n", p->w_ofs[0], p->w_ofs[1]);
+}
+
+static void lb_show_v2par_bright(const struct lightbar_params_v2_brightness *p)
+{
+	printf("0x%02x 0x%02x\t# .bright_bl_off_fixed (battery, AC)\n",
+	       p->bright_bl_off_fixed[0], p->bright_bl_off_fixed[1]);
+	printf("0x%02x 0x%02x\t# .bright_bl_on_min (battery, AC)\n",
+	       p->bright_bl_on_min[0], p->bright_bl_on_min[1]);
+	printf("0x%02x 0x%02x\t# .bright_bl_on_max (battery, AC)\n",
+	       p->bright_bl_on_max[0], p->bright_bl_on_max[1]);
+}
+
+static void lb_show_v2par_thlds(const struct lightbar_params_v2_thresholds *p)
+{
+	printf("%d %d %d\t# .battery_threshold\n", p->battery_threshold[0],
+	       p->battery_threshold[1], p->battery_threshold[2]);
+}
+
+static void lb_show_v2par_colors(const struct lightbar_params_v2_colors *p)
+{
+	int i;
+
+	printf("%d %d %d %d\t\t# .s0_idx[] (battery)\n", p->s0_idx[0][0],
+	       p->s0_idx[0][1], p->s0_idx[0][2], p->s0_idx[0][3]);
+	printf("%d %d %d %d\t\t# .s0_idx[] (AC)\n", p->s0_idx[1][0],
+	       p->s0_idx[1][1], p->s0_idx[1][2], p->s0_idx[1][3]);
+	printf("%d %d %d %d\t# .s3_idx[] (battery)\n", p->s3_idx[0][0],
+	       p->s3_idx[0][1], p->s3_idx[0][2], p->s3_idx[0][3]);
+	printf("%d %d %d %d\t# .s3_idx[] (AC)\n", p->s3_idx[1][0],
+	       p->s3_idx[1][1], p->s3_idx[1][2], p->s3_idx[1][3]);
+
+	for (i = 0; i < ARRAY_SIZE(p->color); i++)
+		printf("0x%02x 0x%02x 0x%02x\t# color[%d]\n", p->color[i].r,
+		       p->color[i].g, p->color[i].b, i);
+}
+
+static int lb_load_program(const char *filename, struct lightbar_program *prog)
+{
+	FILE *fp;
+	size_t got;
+	int rc;
+
+	fp = fopen(filename, "rb");
+	if (!fp) {
+		fprintf(stderr, "Can't open %s: %s\n", filename,
+			strerror(errno));
+		return 1;
+	}
+
+	rc = fseek(fp, 0, SEEK_END);
+	if (rc) {
+		fprintf(stderr, "Couldn't find end of file %s", filename);
+		fclose(fp);
+		return 1;
+	}
+	rc = (int)ftell(fp);
+	if (rc > EC_LB_PROG_LEN) {
+		fprintf(stderr, "File %s is too long, aborting\n", filename);
+		fclose(fp);
+		return 1;
+	}
+	rewind(fp);
+
+	memset(prog->data, 0, EC_LB_PROG_LEN);
+	got = fread(prog->data, 1, EC_LB_PROG_LEN, fp);
+	if (rc != got)
+		fprintf(stderr, "Warning: did not read entire file\n");
+	prog->size = got;
+	fclose(fp);
+	return 0;
+}
+
+static int cmd_lightbar_params_v0(int argc, char **argv)
+{
+	struct ec_params_lightbar param;
+	struct ec_response_lightbar resp;
+	int r;
+
+	if (argc > 2) {
+		r = lb_read_params_v0_from_file(argv[2], &param.set_params_v0);
+		if (r)
+			return r;
+		return lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V0, &param, &resp);
+	}
+	r = lb_do_cmd(LIGHTBAR_CMD_GET_PARAMS_V0, &param, &resp);
+	if (!r)
+		lb_show_params_v0(&resp.get_params_v0);
+	return r;
+}
+
+static int cmd_lightbar_params_v1(int argc, char **argv)
+{
+	struct ec_params_lightbar param;
+	struct ec_response_lightbar resp;
+	int r;
+
+	if (argc > 2) {
+		r = lb_read_params_v1_from_file(argv[2], &param.set_params_v1);
+		if (r)
+			return r;
+		return lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V1, &param, &resp);
+	}
+	r = lb_do_cmd(LIGHTBAR_CMD_GET_PARAMS_V1, &param, &resp);
+	if (!r)
+		lb_show_params_v1(&resp.get_params_v1);
+	return r;
+}
+
+static void lb_param_v2_help(void)
+{
+	printf("Usage:\n");
+	printf("lightbar params2 group [setfile]\n");
+	printf("group list:\n");
+	printf("  timing\n");
+	printf("  tap\n");
+	printf("  oscillation\n");
+	printf("  brightness\n");
+	printf("  thresholds\n");
+	printf("  colors\n");
+
+	return;
+}
+
+static int cmd_lightbar_params_v2(int argc, char **argv)
+{
+	struct ec_params_lightbar p;
+	struct ec_response_lightbar resp;
+	int r = 0;
+	int set = 0;
+
+	memset(&p, 0, sizeof(struct ec_params_lightbar));
+	memset(&resp, 0, sizeof(struct ec_response_lightbar));
+
+	if (argc < 3) {
+		lb_param_v2_help();
+		return 1;
+	}
+
+	/* Set new params if provided with a setfile */
+	if (argc > 3)
+		set = 1;
+
+	/* Show selected v2 params */
+	if (!strncasecmp(argv[2], "timing", 6)) {
+		if (set) {
+			r = lb_rd_timing_v2par_from_file(argv[3],
+							 &p.set_v2par_timing);
+			if (r)
+				return r;
+			r = lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V2_TIMING, &p,
+				      &resp);
+			if (r)
+				return r;
+		}
+		r = lb_do_cmd(LIGHTBAR_CMD_GET_PARAMS_V2_TIMING, &p, &resp);
+		if (r)
+			return r;
+		lb_show_v2par_timing(&resp.get_params_v2_timing);
+	} else if (!strcasecmp(argv[2], "tap")) {
+		if (set) {
+			r = lb_rd_tap_v2par_from_file(argv[3],
+						      &p.set_v2par_tap);
+			if (r)
+				return r;
+			r = lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V2_TAP, &p,
+				      &resp);
+			if (r)
+				return r;
+		}
+		r = lb_do_cmd(LIGHTBAR_CMD_GET_PARAMS_V2_TAP, &p, &resp);
+		if (r)
+			return r;
+		lb_show_v2par_tap(&resp.get_params_v2_tap);
+	} else if (!strncasecmp(argv[2], "oscillation", 11)) {
+		if (set) {
+			r = lb_rd_osc_v2par_from_file(argv[3],
+						      &p.set_v2par_osc);
+			if (r)
+				return r;
+			r = lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V2_OSCILLATION,
+				      &p, &resp);
+			if (r)
+				return r;
+		}
+		r = lb_do_cmd(LIGHTBAR_CMD_GET_PARAMS_V2_OSCILLATION, &p,
+			      &resp);
+		if (r)
+			return r;
+		lb_show_v2par_osc(&resp.get_params_v2_osc);
+	} else if (!strncasecmp(argv[2], "brightness", 10)) {
+		if (set) {
+			r = lb_rd_bright_v2par_from_file(argv[3],
+							 &p.set_v2par_bright);
+			if (r)
+				return r;
+			r = lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V2_BRIGHTNESS, &p,
+				      &resp);
+			if (r)
+				return r;
+		}
+		r = lb_do_cmd(LIGHTBAR_CMD_GET_PARAMS_V2_BRIGHTNESS, &p, &resp);
+		if (r)
+			return r;
+		lb_show_v2par_bright(&resp.get_params_v2_bright);
+	} else if (!strncasecmp(argv[2], "thresholds", 10)) {
+		if (set) {
+			r = lb_rd_thlds_v2par_from_file(argv[3],
+							&p.set_v2par_thlds);
+			if (r)
+				return r;
+			r = lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V2_THRESHOLDS, &p,
+				      &resp);
+			if (r)
+				return r;
+		}
+		r = lb_do_cmd(LIGHTBAR_CMD_GET_PARAMS_V2_THRESHOLDS, &p, &resp);
+		if (r)
+			return r;
+		lb_show_v2par_thlds(&resp.get_params_v2_thlds);
+	} else if (!strncasecmp(argv[2], "colors", 6)) {
+		if (set) {
+			r = lb_rd_colors_v2par_from_file(argv[3],
+							 &p.set_v2par_colors);
+			if (r)
+				return r;
+			r = lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V2_COLORS, &p,
+				      &resp);
+			if (r)
+				return r;
+		}
+		r = lb_do_cmd(LIGHTBAR_CMD_GET_PARAMS_V2_COLORS, &p, &resp);
+		if (r)
+			return r;
+		lb_show_v2par_colors(&resp.get_params_v2_colors);
+	} else {
+		lb_param_v2_help();
+	}
+
+	return r;
+}
+
+static int cmd_lightbar(int argc, char **argv)
+{
+	int i, r;
+	struct ec_params_lightbar param;
+	struct ec_response_lightbar resp;
+
+	if (1 == argc) { /* no args = dump 'em all */
+		r = lb_do_cmd(LIGHTBAR_CMD_DUMP, &param, &resp);
+		if (r)
+			return r;
+		for (i = 0; i < ARRAY_SIZE(resp.dump.vals); i++) {
+			printf(" %02x     %02x     %02x\n",
+			       resp.dump.vals[i].reg, resp.dump.vals[i].ic0,
+			       resp.dump.vals[i].ic1);
+		}
+		return 0;
+	}
+
+	if (argc == 2 && !strcasecmp(argv[1], "init"))
+		return lb_do_cmd(LIGHTBAR_CMD_INIT, &param, &resp);
+
+	if (argc == 2 && !strcasecmp(argv[1], "off"))
+		return lb_do_cmd(LIGHTBAR_CMD_OFF, &param, &resp);
+
+	if (argc == 2 && !strcasecmp(argv[1], "on"))
+		return lb_do_cmd(LIGHTBAR_CMD_ON, &param, &resp);
+
+	if (!strcasecmp(argv[1], "params0"))
+		return cmd_lightbar_params_v0(argc, argv);
+
+	if (!strcasecmp(argv[1], "params1"))
+		return cmd_lightbar_params_v1(argc, argv);
+
+	if (!strcasecmp(argv[1], "params2"))
+		return cmd_lightbar_params_v2(argc, argv);
+
+	if (!strcasecmp(argv[1], "params")) {
+		/* Just try them both */
+		fprintf(stderr, "trying params1 ...\n");
+		if (0 == cmd_lightbar_params_v1(argc, argv))
+			return 0;
+		fprintf(stderr, "trying params0 ...\n");
+		return cmd_lightbar_params_v0(argc, argv);
+	}
+
+	if (!strcasecmp(argv[1], "version")) {
+		r = lb_do_cmd(LIGHTBAR_CMD_VERSION, &param, &resp);
+		if (!r)
+			printf("version %d flags 0x%x\n", resp.version.num,
+			       resp.version.flags);
+		return r;
+	}
+
+	if (argc > 1 && !strcasecmp(argv[1], "brightness")) {
+		char *e;
+		int rv;
+		if (argc > 2) {
+			param.set_brightness.num = 0xff &
+						   strtoull(argv[2], &e, 16);
+			return lb_do_cmd(LIGHTBAR_CMD_SET_BRIGHTNESS, &param,
+					 &resp);
+		}
+		rv = lb_do_cmd(LIGHTBAR_CMD_GET_BRIGHTNESS, &param, &resp);
+		if (rv)
+			return rv;
+		printf("%02x\n", resp.get_brightness.num);
+		return 0;
+	}
+
+	if (argc > 1 && !strcasecmp(argv[1], "demo")) {
+		int rv;
+		if (argc > 2) {
+			if (!strcasecmp(argv[2], "on") || argv[2][0] == '1')
+				param.demo.num = 1;
+			else if (!strcasecmp(argv[2], "off") ||
+				 argv[2][0] == '0')
+				param.demo.num = 0;
+			else {
+				fprintf(stderr, "Invalid arg\n");
+				return -1;
+			}
+			return lb_do_cmd(LIGHTBAR_CMD_DEMO, &param, &resp);
+		}
+
+		rv = lb_do_cmd(LIGHTBAR_CMD_GET_DEMO, &param, &resp);
+		if (rv)
+			return rv;
+		printf("%s\n", resp.get_demo.num ? "on" : "off");
+		return 0;
+	}
+
+	if (argc >= 2 && !strcasecmp(argv[1], "seq")) {
+		char *e;
+		uint8_t num;
+		if (argc == 2)
+			return lb_show_msg_names();
+		num = 0xff & strtoull(argv[2], &e, 16);
+		if (e && *e)
+			num = lb_find_msg_by_name(argv[2]);
+		if (num >= LIGHTBAR_NUM_SEQUENCES) {
+			fprintf(stderr, "Invalid arg\n");
+			return -1;
+		}
+		param.seq.num = num;
+		return lb_do_cmd(LIGHTBAR_CMD_SEQ, &param, &resp);
+	}
+
+	if (argc >= 3 && !strcasecmp(argv[1], "program")) {
+		lb_load_program(argv[2], &param.set_program);
+		return lb_do_cmd(LIGHTBAR_CMD_SET_PROGRAM, &param, &resp);
+	}
+
+	if (argc == 4) {
+		char *e;
+		param.reg.ctrl = 0xff & strtoull(argv[1], &e, 16);
+		param.reg.reg = 0xff & strtoull(argv[2], &e, 16);
+		param.reg.value = 0xff & strtoull(argv[3], &e, 16);
+		return lb_do_cmd(LIGHTBAR_CMD_REG, &param, &resp);
+	}
+
+	if (argc == 5) {
+		char *e;
+		param.set_rgb.led = strtoull(argv[1], &e, 16);
+		param.set_rgb.red = strtoull(argv[2], &e, 16);
+		param.set_rgb.green = strtoull(argv[3], &e, 16);
+		param.set_rgb.blue = strtoull(argv[4], &e, 16);
+		return lb_do_cmd(LIGHTBAR_CMD_SET_RGB, &param, &resp);
+	}
+
+	/* Only thing left is to try to read an LED value */
+	if (argc == 2) {
+		char *e;
+		param.get_rgb.led = strtoull(argv[1], &e, 0);
+		if (!(e && *e)) {
+			r = lb_do_cmd(LIGHTBAR_CMD_GET_RGB, &param, &resp);
+			if (r)
+				return r;
+			printf("%02x %02x %02x\n", resp.get_rgb.red,
+			       resp.get_rgb.green, resp.get_rgb.blue);
+			return 0;
+		}
+	}
+
+	return lb_help(argv[0]);
+}
+
+/* Create an array to store sizes of motion sense param and response structs. */
+#define ST_CMD_SIZE ST_FLD_SIZE(ec_params_motion_sense, cmd)
+#define ST_PRM_SIZE(SUBCMD) \
+	(ST_CMD_SIZE + ST_FLD_SIZE(ec_params_motion_sense, SUBCMD))
+#define ST_RSP_SIZE(SUBCMD) ST_FLD_SIZE(ec_response_motion_sense, SUBCMD)
+#define ST_BOTH_SIZES(SUBCMD)                            \
+	{                                                \
+		ST_PRM_SIZE(SUBCMD), ST_RSP_SIZE(SUBCMD) \
+	}
+
+/*
+ * For ectool only, assume no more than 16 sensors.  More advanced
+ * implementation would allocate the right amount of memory depending on the
+ * number of sensors.
+ */
+#define ECTOOL_MAX_SENSOR 16
+
+static const struct {
+	uint8_t outsize;
+	uint8_t insize;
+} ms_command_sizes[] = {
+	{ ST_PRM_SIZE(dump),
+	  ST_RSP_SIZE(dump) + sizeof(struct ec_response_motion_sensor_data) *
+				      ECTOOL_MAX_SENSOR },
+	ST_BOTH_SIZES(info_4),
+	ST_BOTH_SIZES(ec_rate),
+	ST_BOTH_SIZES(sensor_odr),
+	ST_BOTH_SIZES(sensor_range),
+	ST_BOTH_SIZES(kb_wake_angle),
+	ST_BOTH_SIZES(data),
+	{ ST_CMD_SIZE,
+	  ST_RSP_SIZE(fifo_info) + sizeof(uint16_t) * ECTOOL_MAX_SENSOR },
+	ST_BOTH_SIZES(fifo_flush),
+	ST_BOTH_SIZES(fifo_read),
+	ST_BOTH_SIZES(perform_calib),
+	ST_BOTH_SIZES(sensor_offset),
+	ST_BOTH_SIZES(list_activities),
+	{ ST_PRM_SIZE(set_activity), 0 },
+	{ ST_CMD_SIZE, ST_RSP_SIZE(lid_angle) },
+	ST_BOTH_SIZES(fifo_int_enable),
+	ST_BOTH_SIZES(spoof),
+	ST_BOTH_SIZES(tablet_mode_threshold),
+	ST_BOTH_SIZES(sensor_scale),
+	ST_BOTH_SIZES(online_calib_read),
+	ST_BOTH_SIZES(get_activity),
+};
+BUILD_ASSERT(ARRAY_SIZE(ms_command_sizes) == MOTIONSENSE_NUM_CMDS);
+
+#undef ST_CMD_SIZE
+#undef ST_PRM_SIZE
+#undef ST_RSP_SIZE
+#undef ST_BOTH_SIZES
+
+static int ms_help(const char *cmd)
+{
+	printf("Usage:\n");
+	printf("  %s                              - dump all motion data\n",
+	       cmd);
+	printf("  %s active                       - print active flag\n", cmd);
+	printf("  %s info [NUM]                   - print sensor info\n", cmd);
+	printf("  %s ec_rate NUM [RATE_MS]        - set/get sample rate\n",
+	       cmd);
+	printf("  %s odr NUM [ODR [ROUNDUP]]      - set/get sensor ODR\n", cmd);
+	printf("  %s range NUM [RANGE [ROUNDUP]]  - set/get sensor range\n",
+	       cmd);
+	printf("  %s offset NUM [-- X Y Z [TEMP]] - set/get sensor offset\n",
+	       cmd);
+	printf("  %s kb_wake NUM                  - set/get KB wake ang\n",
+	       cmd);
+	printf("  %s fifo_info                    - print fifo info\n", cmd);
+	printf("  %s fifo_int_enable [0/1]        - enable/disable/get fifo "
+	       "interrupt status\n",
+	       cmd);
+	printf("  %s fifo_read MAX_DATA           - read fifo data\n", cmd);
+	printf("  %s fifo_flush NUM               - trigger fifo interrupt\n",
+	       cmd);
+	printf("  %s list_activities              - list supported "
+	       "activities\n",
+	       cmd);
+	printf("  %s set_activity ACT EN          - enable/disable activity\n",
+	       cmd);
+	printf("  %s get_activity ACT             - get activity status\n",
+	       cmd);
+	printf("  %s lid_angle                    - print lid angle\n", cmd);
+	printf("  %s spoof -- NUM [0/1] [X Y Z]   - enable/disable spoofing\n",
+	       cmd);
+	printf("  %s spoof -- NUM activity ACT [0/1] [STATE] - enable/disable "
+	       "activity spoofing\n",
+	       cmd);
+	printf("  %s tablet_mode_angle ANG HYS    - set/get tablet mode "
+	       "angle\n",
+	       cmd);
+	printf("  %s calibrate NUM                - run sensor calibration\n",
+	       cmd);
+
+	return 0;
+}
+
+static void motionsense_display_activities(uint32_t activities)
+{
+	if (activities & BIT(MOTIONSENSE_ACTIVITY_SIG_MOTION))
+		printf("%d: Significant motion\n",
+		       MOTIONSENSE_ACTIVITY_SIG_MOTION);
+	if (activities & BIT(MOTIONSENSE_ACTIVITY_DOUBLE_TAP))
+		printf("%d: Double tap\n", MOTIONSENSE_ACTIVITY_DOUBLE_TAP);
+	if (activities & BIT(MOTIONSENSE_ACTIVITY_ORIENTATION))
+		printf("%d: Orientation\n", MOTIONSENSE_ACTIVITY_ORIENTATION);
+	if (activities & BIT(MOTIONSENSE_ACTIVITY_BODY_DETECTION))
+		printf("%d: Body Detection\n",
+		       MOTIONSENSE_ACTIVITY_BODY_DETECTION);
+}
+
+static int cmd_motionsense(int argc, char **argv)
+{
+	int i, rv, status_only = (argc == 2);
+	struct ec_params_motion_sense param;
+	/* The largest size using resp as a response buffer */
+	uint8_t resp_buffer[ms_command_sizes[MOTIONSENSE_CMD_DUMP].insize];
+	struct ec_response_motion_sense *resp =
+		(struct ec_response_motion_sense *)resp_buffer;
+	char *e;
+	/*
+	 * Warning: the following strings printed out are read in an
+	 * autotest. Do not change string without consulting autotest
+	 * for kernel_CrosECSysfsAccel.
+	 */
+	const char *motion_status_string[2][2] = {
+		{ "Motion sensing inactive", "0" },
+		{ "Motion sensing active", "1" },
+	};
+	/* No motionsense command has more than 7 args. */
+	if (argc > 7)
+		return ms_help(argv[0]);
+
+	if ((argc == 1) || (argc == 2 && !strcasecmp(argv[1], "active"))) {
+		param.cmd = MOTIONSENSE_CMD_DUMP;
+		param.dump.max_sensor_count = ECTOOL_MAX_SENSOR;
+		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1, &param,
+				ms_command_sizes[param.cmd].outsize, resp,
+				ms_command_sizes[param.cmd].insize);
+		if (rv > 0) {
+			printf("%s\n", motion_status_string[!!(
+					       resp->dump.module_flags &
+					       MOTIONSENSE_MODULE_FLAG_ACTIVE)]
+							   [status_only]);
+			if (status_only)
+				return 0;
+
+			if (resp->dump.sensor_count > ECTOOL_MAX_SENSOR) {
+				printf("Too many sensors to handle: %d",
+				       resp->dump.sensor_count);
+				return -1;
+			}
+			for (i = 0; i < resp->dump.sensor_count; i++) {
+				/*
+				 * Warning: the following string printed out
+				 * is read by an autotest. Do not change string
+				 * without consulting autotest for
+				 * kernel_CrosECSysfsAccel.
+				 */
+				printf("Sensor %d: ", i);
+				if (resp->dump.sensor[i].flags &
+				    MOTIONSENSE_SENSOR_FLAG_PRESENT)
+					printf("%d\t%d\t%d\n",
+					       resp->dump.sensor[i].data[0],
+					       resp->dump.sensor[i].data[1],
+					       resp->dump.sensor[i].data[2]);
+				else
+					printf("None\n");
+			}
+			return 0;
+		} else {
+			return rv;
+		}
+	}
+
+	if ((argc == 2 || argc == 3) && !strcasecmp(argv[1], "info")) {
+		int version = 0;
+		int loop_start;
+		int loop_end;
+		int i;
+
+		rv = get_latest_cmd_version(EC_CMD_MOTION_SENSE_CMD, &version);
+		if (rv < 0)
+			return rv;
+
+		if (argc == 2) {
+			param.cmd = MOTIONSENSE_CMD_DUMP;
+			param.dump.max_sensor_count = ECTOOL_MAX_SENSOR;
+			rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1, &param,
+					ms_command_sizes[param.cmd].outsize,
+					resp,
+					ms_command_sizes[param.cmd].insize);
+			if (rv < 0)
+				return rv;
+			if (resp->dump.sensor_count > ECTOOL_MAX_SENSOR)
+				return -1;
+
+			loop_start = 0;
+			loop_end = resp->dump.sensor_count;
+		} else {
+			loop_start = strtol(argv[2], &e, 0);
+			if (e && *e) {
+				fprintf(stderr, "Bad %s arg.\n", argv[2]);
+				return -1;
+			}
+			loop_end = loop_start + 1;
+		}
+		param.cmd = MOTIONSENSE_CMD_INFO;
+
+		for (i = loop_start; i < loop_end; i++) {
+			param.sensor_odr.sensor_num = i;
+
+			if (argc == 2) {
+				if (i != loop_start)
+					printf("\n");
+				printf("Index:    %d\n", i);
+			}
+
+			rv = ec_command(EC_CMD_MOTION_SENSE_CMD, version,
+					&param,
+					ms_command_sizes[param.cmd].outsize,
+					resp,
+					ms_command_sizes[param.cmd].insize);
+			if (rv < 0) {
+				/*
+				 * Return the error code to a higher level if
+				 * we're querying about a specific sensor; else
+				 * just print the error.
+				 */
+				if (argc == 3)
+					return rv;
+
+				printf("Error: %d\n", rv);
+				continue;
+			}
+			printf("Type:     ");
+			switch (resp->info.type) {
+			case MOTIONSENSE_TYPE_ACCEL:
+				printf("accel\n");
+				break;
+			case MOTIONSENSE_TYPE_GYRO:
+				printf("gyro\n");
+				break;
+			case MOTIONSENSE_TYPE_MAG:
+				printf("magnetometer\n");
+				break;
+			case MOTIONSENSE_TYPE_LIGHT:
+				printf("light\n");
+				break;
+			case MOTIONSENSE_TYPE_LIGHT_RGB:
+				printf("rgb light\n");
+				break;
+			case MOTIONSENSE_TYPE_PROX:
+				printf("proximity\n");
+				break;
+			case MOTIONSENSE_TYPE_ACTIVITY:
+				printf("activity\n");
+				break;
+			case MOTIONSENSE_TYPE_BARO:
+				printf("barometer\n");
+				break;
+			case MOTIONSENSE_TYPE_SYNC:
+				printf("sync\n");
+				break;
+			default:
+				printf("unknown\n");
+			}
+
+			printf("Location: ");
+			switch (resp->info.location) {
+			case MOTIONSENSE_LOC_BASE:
+				printf("base\n");
+				break;
+			case MOTIONSENSE_LOC_LID:
+				printf("lid\n");
+				break;
+			case MOTIONSENSE_LOC_CAMERA:
+				printf("camera\n");
+				break;
+			default:
+				printf("unknown\n");
+			}
+
+			printf("Chip:     ");
+			switch (resp->info.chip) {
+			case MOTIONSENSE_CHIP_KXCJ9:
+				printf("kxcj9\n");
+				break;
+			case MOTIONSENSE_CHIP_LSM6DS0:
+				printf("lsm6ds0\n");
+				break;
+			case MOTIONSENSE_CHIP_BMI160:
+				printf("bmi160\n");
+				break;
+			case MOTIONSENSE_CHIP_SI1141:
+				printf("si1141\n");
+				break;
+			case MOTIONSENSE_CHIP_KX022:
+				printf("kx022\n");
+				break;
+			case MOTIONSENSE_CHIP_L3GD20H:
+				printf("l3gd20h\n");
+				break;
+			case MOTIONSENSE_CHIP_BMA255:
+				printf("bma255\n");
+				break;
+			case MOTIONSENSE_CHIP_BMP280:
+				printf("bmp280\n");
+				break;
+			case MOTIONSENSE_CHIP_OPT3001:
+				printf("opt3001\n");
+				break;
+			case MOTIONSENSE_CHIP_CM32183:
+				printf("cm32183\n");
+				break;
+			case MOTIONSENSE_CHIP_BH1730:
+				printf("bh1730\n");
+				break;
+			case MOTIONSENSE_CHIP_GPIO:
+				printf("gpio\n");
+				break;
+			case MOTIONSENSE_CHIP_LIS2DH:
+				printf("lis2dh\n");
+				break;
+			case MOTIONSENSE_CHIP_LSM6DSM:
+				printf("lsm6dsm\n");
+				break;
+			case MOTIONSENSE_CHIP_LIS2DE:
+				printf("lis2de\n");
+				break;
+			case MOTIONSENSE_CHIP_LIS2MDL:
+				printf("lis2mdl\n");
+				break;
+			case MOTIONSENSE_CHIP_LSM6DS3:
+				printf("lsm6ds3\n");
+				break;
+			case MOTIONSENSE_CHIP_LSM6DSO:
+				printf("lsm6dso\n");
+				break;
+			case MOTIONSENSE_CHIP_LNG2DM:
+				printf("lng2dm\n");
+				break;
+			case MOTIONSENSE_CHIP_TCS3400:
+				printf("tcs3400\n");
+				break;
+			case MOTIONSENSE_CHIP_LIS2DW12:
+				printf("lis2dw12\n");
+				break;
+			case MOTIONSENSE_CHIP_LIS2DWL:
+				printf("lis2dwl\n");
+				break;
+			case MOTIONSENSE_CHIP_LIS2DS:
+				printf("lis2ds\n");
+				break;
+			case MOTIONSENSE_CHIP_BMI260:
+				printf("bmi260\n");
+				break;
+			case MOTIONSENSE_CHIP_ICM426XX:
+				printf("icm426xx\n");
+				break;
+			case MOTIONSENSE_CHIP_ICM42607:
+				printf("icm42607\n");
+				break;
+			case MOTIONSENSE_CHIP_BMI323:
+				printf("bmi323\n");
+				break;
+			case MOTIONSENSE_CHIP_BMA422:
+				printf("bma422\n");
+				break;
+			case MOTIONSENSE_CHIP_BMI220:
+				printf("bmi220\n");
+				break;
+			default:
+				printf("unknown\n");
+			}
+
+			if (version >= 3) {
+				printf("Min Frequency:              %d mHz\n",
+				       resp->info_3.min_frequency);
+				printf("Max Frequency:              %d mHz\n",
+				       resp->info_3.max_frequency);
+				printf("FIFO Max Event Count:       %d\n",
+				       resp->info_3.fifo_max_event_count);
+			}
+			if (version >= 4) {
+				printf("Flags:                      %d\n",
+				       resp->info_4.flags);
+			}
+		}
+
+		return 0;
+	}
+
+	if (argc > 2 && !strcasecmp(argv[1], "ec_rate")) {
+		param.cmd = MOTIONSENSE_CMD_EC_RATE;
+		param.ec_rate.data = EC_MOTION_SENSE_NO_VALUE;
+		param.sensor_odr.sensor_num = strtol(argv[2], &e, 0);
+		if (e && *e) {
+			fprintf(stderr, "Bad %s arg.\n", argv[2]);
+			return -1;
+		}
+		if (argc == 4) {
+			param.ec_rate.data = strtol(argv[3], &e, 0);
+			if (e && *e) {
+				fprintf(stderr, "Bad %s arg.\n", argv[3]);
+				return -1;
+			}
+		}
+
+		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1, &param,
+				ms_command_sizes[param.cmd].outsize, resp,
+				ms_command_sizes[param.cmd].insize);
+
+		if (rv < 0)
+			return rv;
+
+		printf("%d\n", resp->ec_rate.ret);
+		return 0;
+	}
+
+	if (argc > 2 && !strcasecmp(argv[1], "odr")) {
+		param.cmd = MOTIONSENSE_CMD_SENSOR_ODR;
+		param.sensor_odr.data = EC_MOTION_SENSE_NO_VALUE;
+		param.sensor_odr.roundup = 1;
+
+		param.sensor_odr.sensor_num = strtol(argv[2], &e, 0);
+		if (e && *e) {
+			fprintf(stderr, "Bad %s arg.\n", argv[2]);
+			return -1;
+		}
+
+		if (argc >= 4) {
+			param.sensor_odr.data = strtol(argv[3], &e, 0);
+			if (e && *e) {
+				fprintf(stderr, "Bad %s arg.\n", argv[3]);
+				return -1;
+			}
+		}
+
+		if (argc == 5) {
+			param.sensor_odr.roundup = strtol(argv[4], &e, 0);
+			if (e && *e) {
+				fprintf(stderr, "Bad %s arg.\n", argv[4]);
+				return -1;
+			}
+		}
+
+		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1, &param,
+				ms_command_sizes[param.cmd].outsize, resp,
+				ms_command_sizes[param.cmd].insize);
+
+		if (rv < 0)
+			return rv;
+
+		printf("%d\n", resp->sensor_odr.ret);
+		return 0;
+	}
+
+	if (argc > 2 && !strcasecmp(argv[1], "range")) {
+		param.cmd = MOTIONSENSE_CMD_SENSOR_RANGE;
+		param.sensor_range.data = EC_MOTION_SENSE_NO_VALUE;
+		param.sensor_range.roundup = 1;
+
+		param.sensor_range.sensor_num = strtol(argv[2], &e, 0);
+		if (e && *e) {
+			fprintf(stderr, "Bad %s arg.\n", argv[2]);
+			return -1;
+		}
+
+		if (argc >= 4) {
+			param.sensor_range.data = strtol(argv[3], &e, 0);
+			if (e && *e) {
+				fprintf(stderr, "Bad %s arg.\n", argv[3]);
+				return -1;
+			}
+		}
+
+		if (argc == 5) {
+			param.sensor_odr.roundup = strtol(argv[4], &e, 0);
+			if (e && *e) {
+				fprintf(stderr, "Bad %s arg.\n", argv[4]);
+				return -1;
+			}
+		}
+
+		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1, &param,
+				ms_command_sizes[param.cmd].outsize, resp,
+				ms_command_sizes[param.cmd].insize);
+
+		if (rv < 0)
+			return rv;
+
+		printf("%d\n", resp->sensor_range.ret);
+		return 0;
+	}
+
+	if (argc < 4 && !strcasecmp(argv[1], "kb_wake")) {
+		param.cmd = MOTIONSENSE_CMD_KB_WAKE_ANGLE;
+		param.kb_wake_angle.data = EC_MOTION_SENSE_NO_VALUE;
+
+		if (argc == 3) {
+			param.kb_wake_angle.data = strtol(argv[2], &e, 0);
+			if (e && *e) {
+				fprintf(stderr, "Bad %s arg.\n", argv[2]);
+				return -1;
+			}
+		}
+
+		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1, &param,
+				ms_command_sizes[param.cmd].outsize, resp,
+				ms_command_sizes[param.cmd].insize);
+
+		if (rv < 0)
+			return rv;
+
+		printf("%d\n", resp->kb_wake_angle.ret);
+		return 0;
+	}
+
+	if (argc < 5 && !strcasecmp(argv[1], "tablet_mode_angle")) {
+		param.cmd = MOTIONSENSE_CMD_TABLET_MODE_LID_ANGLE;
+		/*
+		 * EC_MOTION_SENSE_NO_VALUE indicates to the EC that host is
+		 * attempting to only read the current values.
+		 */
+		param.tablet_mode_threshold.lid_angle =
+			EC_MOTION_SENSE_NO_VALUE;
+		param.tablet_mode_threshold.hys_degree =
+			EC_MOTION_SENSE_NO_VALUE;
+
+		if (argc == 4) {
+			param.tablet_mode_threshold.lid_angle =
+				strtol(argv[2], &e, 0);
+
+			if (e && *e) {
+				fprintf(stderr, "Bad %s arg.\n", argv[2]);
+				return -1;
+			}
+
+			param.tablet_mode_threshold.hys_degree =
+				strtol(argv[3], &e, 0);
+			if (e && *e) {
+				fprintf(stderr, "Bad %s arg.\n", argv[3]);
+				return -1;
+			}
+		} else if (argc != 2) {
+			return ms_help(argv[0]);
+		}
+
+		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2, &param,
+				ms_command_sizes[param.cmd].outsize, resp,
+				ms_command_sizes[param.cmd].insize);
+
+		if (rv < 0)
+			return rv;
+
+		printf("tablet_mode_angle=%d hys=%d\n",
+		       resp->tablet_mode_threshold.lid_angle,
+		       resp->tablet_mode_threshold.hys_degree);
+
+		return 0;
+	}
+
+	if (argc == 2 && !strcasecmp(argv[1], "fifo_info")) {
+		int sensor_count;
+
+		param.cmd = MOTIONSENSE_CMD_DUMP;
+		param.dump.max_sensor_count = 0;
+		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1, &param,
+				ms_command_sizes[param.cmd].outsize, resp,
+				ms_command_sizes[param.cmd].insize);
+		if (rv < 0)
+			return rv;
+		sensor_count = resp->dump.sensor_count;
+
+		param.cmd = MOTIONSENSE_CMD_FIFO_INFO;
+		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2, &param,
+				ms_command_sizes[param.cmd].outsize, resp,
+				ms_command_sizes[param.cmd].insize);
+		if (rv < 0)
+			return rv;
+
+		printf("Size:     %d\n", resp->fifo_info.size);
+		printf("Count:    %d\n", resp->fifo_info.count);
+		printf("Timestamp:%" PRIx32 "\n", resp->fifo_info.timestamp);
+		printf("Total lost: %d\n", resp->fifo_info.total_lost);
+		for (i = 0; i < sensor_count; i++) {
+			int lost = resp->fifo_info.lost[i];
+			if (lost != 0)
+				printf("Lost %d:     %d\n", i, lost);
+		}
+		return 0;
+	}
+
+	if (argc >= 2 && !strcasecmp(argv[1], "fifo_int_enable")) {
+		param.cmd = MOTIONSENSE_CMD_FIFO_INT_ENABLE;
+		if (argc == 3)
+			param.fifo_int_enable.enable = strtol(argv[2], &e, 0);
+		else
+			param.fifo_int_enable.enable = EC_MOTION_SENSE_NO_VALUE;
+		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2, &param,
+				ms_command_sizes[param.cmd].outsize, resp,
+				ms_command_sizes[param.cmd].insize);
+		if (rv < 0)
+			return rv;
+
+		printf("%d\n", resp->fifo_int_enable.ret);
+		return 0;
+	}
+
+	if (argc == 3 && !strcasecmp(argv[1], "fifo_read")) {
+		/* large number to test fragmentation */
+		struct {
+			uint32_t number_data;
+			struct ec_response_motion_sensor_data data[512];
+		} fifo_read_buffer = {
+			.number_data = UINT32_MAX,
+		};
+		int print_data = 0, max_data = strtol(argv[2], &e, 0);
+
+		if (e && *e) {
+			fprintf(stderr, "Bad %s arg.\n", argv[2]);
+			return -1;
+		}
+		while (fifo_read_buffer.number_data != 0 &&
+		       print_data < max_data) {
+			struct ec_response_motion_sensor_data *vector;
+			param.cmd = MOTIONSENSE_CMD_FIFO_READ;
+			param.fifo_read.max_data_vector =
+				MIN(ARRAY_SIZE(fifo_read_buffer.data),
+				    max_data - print_data);
+
+			rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2, &param,
+					ms_command_sizes[param.cmd].outsize,
+					&fifo_read_buffer, ec_max_insize);
+			if (rv < 0)
+				return rv;
+
+			print_data += fifo_read_buffer.number_data;
+			for (i = 0; i < fifo_read_buffer.number_data; i++) {
+				vector = &fifo_read_buffer.data[i];
+				if (vector->flags &
+				    (MOTIONSENSE_SENSOR_FLAG_TIMESTAMP |
+				     MOTIONSENSE_SENSOR_FLAG_FLUSH)) {
+					printf("Timestamp:%" PRIx32 "%s\n",
+					       vector->timestamp,
+					       (vector->flags & MOTIONSENSE_SENSOR_FLAG_FLUSH ?
+							" - Flush" :
+							""));
+				} else {
+					printf("Sensor %d: %d\t%d\t%d "
+					       "(as uint16: %u\t%u\t%u)\n",
+					       vector->sensor_num,
+					       vector->data[0], vector->data[1],
+					       vector->data[2], vector->data[0],
+					       vector->data[1],
+					       vector->data[2]);
+				}
+			}
+		}
+		return 0;
+	}
+	if (argc == 3 && !strcasecmp(argv[1], "fifo_flush")) {
+		param.cmd = MOTIONSENSE_CMD_FIFO_FLUSH;
+
+		param.sensor_odr.sensor_num = strtol(argv[2], &e, 0);
+		if (e && *e) {
+			fprintf(stderr, "Bad %s arg.\n", argv[2]);
+			return -1;
+		}
+
+		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1, &param,
+				ms_command_sizes[param.cmd].outsize, resp,
+				ms_command_sizes[param.cmd].insize);
+
+		return rv < 0 ? rv : 0;
+	}
+
+	if (argc == 3 && !strcasecmp(argv[1], "calibrate")) {
+		param.cmd = MOTIONSENSE_CMD_PERFORM_CALIB;
+		param.perform_calib.enable = 1;
+		param.perform_calib.sensor_num = strtol(argv[2], &e, 0);
+		if (e && *e) {
+			fprintf(stderr, "Bad %s arg.\n", argv[2]);
+			return -1;
+		}
+
+		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1, &param,
+				ms_command_sizes[param.cmd].outsize, resp,
+				ms_command_sizes[param.cmd].insize);
+
+		if (rv < 0)
+			return rv;
+
+		printf("--- Calibrated well ---\n");
+		printf("New offset vector: X:%d, Y:%d, Z:%d\n",
+		       resp->perform_calib.offset[0],
+		       resp->perform_calib.offset[1],
+		       resp->perform_calib.offset[2]);
+		if (resp->perform_calib.temp ==
+		    EC_MOTION_SENSE_INVALID_CALIB_TEMP)
+			printf("Temperature at calibration unknown\n");
+		else
+			printf("Temperature at calibration: %d.%02d C\n",
+			       resp->perform_calib.temp / 100,
+			       resp->perform_calib.temp % 100);
+		return 0;
+	}
+
+	if (argc >= 3 && !strcasecmp(argv[1], "offset")) {
+		param.cmd = MOTIONSENSE_CMD_SENSOR_OFFSET;
+		param.sensor_offset.flags = 0;
+		param.sensor_offset.temp = EC_MOTION_SENSE_INVALID_CALIB_TEMP;
+
+		param.sensor_offset.sensor_num = strtol(argv[2], &e, 0);
+		if (e && *e) {
+			fprintf(stderr, "Bad %s arg.\n", argv[2]);
+			return -1;
+		}
+
+		if (argc >= 4) {
+			/* Regarded as a command to set offset */
+			if (argc >= 6 && argc < 8) {
+				/* Set offset : X, Y, Z */
+				param.sensor_offset.flags =
+					MOTION_SENSE_SET_OFFSET;
+				for (i = 0; i < 3; i++) {
+					param.sensor_offset.offset[i] =
+						strtol(argv[3 + i], &e, 0);
+					if (e && *e) {
+						fprintf(stderr, "Bad %s arg.\n",
+							argv[3 + i]);
+						return -1;
+					}
+				}
+				if (argc == 7) {
+					/* Set offset : Temperature */
+					param.sensor_offset.temp =
+						strtol(argv[6], &e, 0);
+					if (e && *e) {
+						fprintf(stderr, "Bad %s arg.\n",
+							argv[6]);
+						return -1;
+					}
+				}
+			} else {
+				return ms_help(argv[0]);
+			}
+		}
+
+		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1, &param,
+				ms_command_sizes[param.cmd].outsize, resp,
+				ms_command_sizes[param.cmd].insize);
+
+		if (rv < 0)
+			return rv;
+
+		printf("Offset vector: X:%d, Y:%d, Z:%d\n",
+		       resp->sensor_offset.offset[0],
+		       resp->sensor_offset.offset[1],
+		       resp->sensor_offset.offset[2]);
+		if (resp->sensor_offset.temp ==
+		    EC_MOTION_SENSE_INVALID_CALIB_TEMP)
+			printf("temperature at calibration unknown\n");
+		else
+			printf("temperature at calibration: %d.%02d C\n",
+			       resp->sensor_offset.temp / 100,
+			       resp->sensor_offset.temp % 100);
+		return 0;
+	}
+
+	if (argc == 2 && !strcasecmp(argv[1], "list_activities")) {
+		param.cmd = MOTIONSENSE_CMD_LIST_ACTIVITIES;
+		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2, &param,
+				ms_command_sizes[param.cmd].outsize, resp,
+				ms_command_sizes[param.cmd].insize);
+		if (rv < 0)
+			return rv;
+
+		printf("Enabled:\n");
+		motionsense_display_activities(resp->list_activities.enabled);
+		printf("Disabled:\n");
+		motionsense_display_activities(resp->list_activities.disabled);
+		return 0;
+	}
+	if (argc == 4 && !strcasecmp(argv[1], "set_activity")) {
+		param.cmd = MOTIONSENSE_CMD_SET_ACTIVITY;
+		param.set_activity.activity = strtol(argv[2], &e, 0);
+		param.set_activity.enable = strtol(argv[3], &e, 0);
+
+		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2, &param,
+				ms_command_sizes[param.cmd].outsize, resp,
+				ms_command_sizes[param.cmd].insize);
+		if (rv < 0)
+			return rv;
+		return 0;
+	}
+	if (argc == 3 && !strcasecmp(argv[1], "get_activity")) {
+		param.cmd = MOTIONSENSE_CMD_GET_ACTIVITY;
+		param.get_activity.activity = strtol(argv[2], &e, 0);
+
+		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2, &param,
+				ms_command_sizes[param.cmd].outsize, resp,
+				ms_command_sizes[param.cmd].insize);
+		if (rv < 0)
+			return rv;
+		printf("State: %d\n", resp->get_activity.state);
+		return 0;
+	}
+	if (argc == 2 && !strcasecmp(argv[1], "lid_angle")) {
+		param.cmd = MOTIONSENSE_CMD_LID_ANGLE;
+		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2, &param,
+				ms_command_sizes[param.cmd].outsize, resp,
+				ms_command_sizes[param.cmd].insize);
+		if (rv < 0)
+			return rv;
+
+		printf("Lid angle: ");
+		if (resp->lid_angle.value == LID_ANGLE_UNRELIABLE)
+			printf("unreliable\n");
+		else
+			printf("%d\n", resp->lid_angle.value);
+
+		return 0;
+	}
+
+	if (argc >= 3 && !strcasecmp(argv[1], "spoof")) {
+		param.cmd = MOTIONSENSE_CMD_SPOOF;
+		/* By default, just query the current spoof status. */
+		param.spoof.spoof_enable = MOTIONSENSE_SPOOF_MODE_QUERY;
+		param.spoof.sensor_id = strtol(argv[2], &e, 0);
+		if (e && *e) {
+			fprintf(stderr, "Bad %s arg.\n", argv[2]);
+			return -1;
+		}
+		/* spoof activity state */
+		if (argc >= 5 && !strcasecmp(argv[3], "activity")) {
+			int enable = 0;
+
+			param.spoof.activity_num = strtol(argv[4], &e, 0);
+			if (e && *e) {
+				fprintf(stderr, "Base %s arg.\n", argv[4]);
+				return -1;
+			}
+			if (argc >= 6) {
+				enable = strtol(argv[5], &e, 0);
+				if ((e && *e) || (enable != 0 && enable != 1)) {
+					fprintf(stderr, "Bad %s arg.\n",
+						argv[5]);
+					return -1;
+				}
+			}
+			if ((enable == 1) && (argc == 6)) {
+				/* Enable spoofing, but lock to current state */
+				param.spoof.spoof_enable =
+					MOTIONSENSE_SPOOF_MODE_LOCK_CURRENT;
+			} else if ((enable == 1) && (argc == 7)) {
+				/* Enable spoofing, but use provided state */
+				int state = strtol(argv[6], &e, 0);
+
+				if ((e && *e) || (state != 0 && state != 1)) {
+					fprintf(stderr, "Bad %s arg.\n",
+						argv[6]);
+					return -1;
+				}
+				param.spoof.activity_state = state;
+				param.spoof.spoof_enable =
+					MOTIONSENSE_SPOOF_MODE_CUSTOM;
+			} else if ((enable == 0) && (argc == 6)) {
+				param.spoof.spoof_enable =
+					MOTIONSENSE_SPOOF_MODE_DISABLE;
+			} else if (argc != 5) {
+				return ms_help(argv[0]);
+			}
+			/* spoof accel data */
+		} else if (argc >= 4) {
+			int enable, i;
+			int16_t val;
+
+			enable = strtol(argv[3], &e, 0);
+			if ((e && *e) || (enable != 0 && enable != 1)) {
+				fprintf(stderr, "Bad %s arg.\n", argv[3]);
+				return -1;
+			}
+
+			if ((enable == 1) && (argc == 4)) {
+				/*
+				 * Enable spoofing, but lock to current sensor
+				 * values.
+				 */
+				param.spoof.spoof_enable =
+					MOTIONSENSE_SPOOF_MODE_LOCK_CURRENT;
+			} else if ((enable == 1) && (argc == 7)) {
+				/*
+				 * Enable spoofing, but use provided component
+				 * values.
+				 */
+				param.spoof.spoof_enable =
+					MOTIONSENSE_SPOOF_MODE_CUSTOM;
+				for (i = 0; i < 3; i++) {
+					val = strtol(argv[4 + i], &e, 0);
+					if (e && *e) {
+						fprintf(stderr, "Bad %s arg.\n",
+							argv[4 + i]);
+						return -1;
+					}
+					param.spoof.components[i] = val;
+				}
+			} else if (enable == 0) {
+				param.spoof.spoof_enable =
+					MOTIONSENSE_SPOOF_MODE_DISABLE;
+			} else {
+				return ms_help(argv[0]);
+			}
+		}
+
+		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2, &param,
+				ms_command_sizes[param.cmd].outsize, resp,
+				ms_command_sizes[param.cmd].insize);
+		if (rv < 0)
+			return rv;
+
+		if (param.spoof.spoof_enable == MOTIONSENSE_SPOOF_MODE_QUERY)
+			/*
+			 * Response is the current spoof status of the
+			 * sensor.
+			 */
+			printf("Sensor %d spoof mode is %s.\n",
+			       param.spoof.sensor_id,
+			       resp->spoof.ret ? "enabled" : "disabled");
+
+		return 0;
+	}
+
+	return ms_help(argv[0]);
+}
+
+int cmd_next_event(int argc, char *argv[])
+{
+	uint8_t *rdata = (uint8_t *)ec_inbuf;
+	int rv;
+	int i;
+
+	rv = ec_command(EC_CMD_GET_NEXT_EVENT, 0, NULL, 0, rdata,
+			ec_max_insize);
+	if (rv < 0)
+		return rv;
+
+	printf("Next event is 0x%02x\n", rdata[0]);
+	if (rv > 1) {
+		printf("Event data:\n");
+		for (i = 1; i < rv; ++i) {
+			printf("%02x ", rdata[i]);
+			if (!(i & 0xf))
+				printf("\n");
+		}
+		printf("\n");
+	}
+
+	return 0;
+}
+
+static int find_led_color_by_name(const char *color)
+{
+	int i;
+
+	for (i = 0; i < EC_LED_COLOR_COUNT; ++i)
+		if (!strcasecmp(color, led_color_names[i]))
+			return i;
+
+	return -1;
+}
+
+static int find_led_id_by_name(const char *led)
+{
+	int i;
+
+	for (i = 0; i < EC_LED_ID_COUNT; ++i)
+		if (!strcasecmp(led, led_names[i]))
+			return i;
+
+	return -1;
+}
+
+int cmd_led(int argc, char *argv[])
+{
+	struct ec_params_led_control p;
+	struct ec_response_led_control r;
+	char *e, *ptr;
+	int rv, i, j;
+
+	memset(p.brightness, 0, sizeof(p.brightness));
+	p.flags = 0;
+
+	if (argc < 3) {
+		fprintf(stderr,
+			"Usage: %s <name> <query | auto | "
+			"off | <color> | <color>=<value>...>\n",
+			argv[0]);
+		return -1;
+	}
+
+	p.led_id = find_led_id_by_name(argv[1]);
+	if (p.led_id == (uint8_t)-1) {
+		fprintf(stderr, "Bad LED name: %s\n", argv[1]);
+		fprintf(stderr, "Valid LED names: ");
+		for (i = 0; i < EC_LED_ID_COUNT; i++)
+			fprintf(stderr, "%s ", led_names[i]);
+		fprintf(stderr, "\n");
+		return -1;
+	}
+
+	if (!strcasecmp(argv[2], "query")) {
+		p.flags = EC_LED_FLAGS_QUERY;
+		rv = ec_command(EC_CMD_LED_CONTROL, 1, &p, sizeof(p), &r,
+				sizeof(r));
+		printf("Brightness range for LED %d:\n", p.led_id);
+		if (rv < 0) {
+			fprintf(stderr, "Error: Unsupported LED.\n");
+			return rv;
+		}
+		for (i = 0; i < EC_LED_COLOR_COUNT; ++i)
+			printf("\t%s\t: 0x%x\n", led_color_names[i],
+			       r.brightness_range[i]);
+		return 0;
+	}
+
+	if (!strcasecmp(argv[2], "off")) {
+		/* Brightness initialized to 0 for each color. */
+	} else if (!strcasecmp(argv[2], "auto")) {
+		p.flags = EC_LED_FLAGS_AUTO;
+	} else if ((i = find_led_color_by_name(argv[2])) != -1) {
+		p.brightness[i] = 0xff;
+	} else {
+		for (i = 2; i < argc; ++i) {
+			ptr = strtok(argv[i], "=");
+			j = find_led_color_by_name(ptr);
+			if (j == -1) {
+				fprintf(stderr, "Bad color name: %s\n", ptr);
+				fprintf(stderr, "Valid colors: ");
+				for (j = 0; j < EC_LED_COLOR_COUNT; j++)
+					fprintf(stderr, "%s ",
+						led_color_names[j]);
+				fprintf(stderr, "\n");
+				return -1;
+			}
+			ptr = strtok(NULL, "=");
+			if (ptr == NULL) {
+				fprintf(stderr, "Missing brightness value\n");
+				return -1;
+			}
+			p.brightness[j] = strtol(ptr, &e, 0);
+			if (e && *e) {
+				fprintf(stderr, "Bad brightness: %s\n", ptr);
+				return -1;
+			}
+		}
+	}
+
+	rv = ec_command(EC_CMD_LED_CONTROL, 1, &p, sizeof(p), &r, sizeof(r));
+	return (rv < 0 ? rv : 0);
+}
+
+int cmd_usb_charge_set_mode(int argc, char *argv[])
+{
+	struct ec_params_usb_charge_set_mode p;
+	char *e;
+	int rv;
+
+	if (argc != 3 && argc != 4) {
+		fprintf(stderr,
+			"Usage: %s <port_id> <mode_id> [<inhibit_charge>]\n",
+			argv[0]);
+		return -1;
+	}
+	p.usb_port_id = strtol(argv[1], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad port ID.\n");
+		return -1;
+	}
+	p.mode = strtol(argv[2], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad mode ID.\n");
+		return -1;
+	}
+	p.inhibit_charge = 0;
+	if (argc == 4) {
+		p.inhibit_charge = strtol(argv[3], &e, 0);
+		if ((e && *e) ||
+		    (p.inhibit_charge != 0 && p.inhibit_charge != 1)) {
+			fprintf(stderr, "Bad value\n");
+			return -1;
+		}
+	}
+
+	printf("Setting port %d to mode %d inhibit_charge %d...\n",
+	       p.usb_port_id, p.mode, p.inhibit_charge);
+
+	rv = ec_command(EC_CMD_USB_CHARGE_SET_MODE, 0, &p, sizeof(p), NULL, 0);
+	if (rv < 0)
+		return rv;
+
+	printf("USB charging mode set.\n");
+	return 0;
+}
+
+int cmd_usb_mux(int argc, char *argv[])
+{
+	struct ec_params_usb_mux p;
+	char *e;
+	int rv;
+
+	if (argc != 2) {
+		fprintf(stderr, "Usage: %s <mux>\n", argv[0]);
+		return -1;
+	}
+
+	p.mux = strtol(argv[1], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad mux value.\n");
+		return -1;
+	}
+
+	rv = ec_command(EC_CMD_USB_MUX, 0, &p, sizeof(p), NULL, 0);
+	if (rv < 0)
+		return rv;
+
+	printf("Set USB mux to 0x%x.\n", p.mux);
+
+	return 0;
+}
+
+int cmd_usb_pd(int argc, char *argv[])
+{
+	const char *role_str[] = { "",	   "toggle", "toggle-off",
+				   "sink", "source", "freeze" };
+	const char *mux_str[] = { "", "none", "usb", "dp", "dock", "auto" };
+	const char *swap_str[] = { "", "dr_swap", "pr_swap", "vconn_swap" };
+	struct ec_params_usb_pd_control p;
+	struct ec_response_usb_pd_control_v2 *r_v2 =
+		(struct ec_response_usb_pd_control_v2 *)ec_inbuf;
+	struct ec_response_usb_pd_control_v1 *r_v1 =
+		(struct ec_response_usb_pd_control_v1 *)ec_inbuf;
+	struct ec_response_usb_pd_control *r =
+		(struct ec_response_usb_pd_control *)ec_inbuf;
+	int rv, i, j;
+	int option_ok;
+	char *e;
+	int cmdver;
+
+	BUILD_ASSERT(ARRAY_SIZE(role_str) == USB_PD_CTRL_ROLE_COUNT);
+	BUILD_ASSERT(ARRAY_SIZE(mux_str) == USB_PD_CTRL_MUX_COUNT);
+	BUILD_ASSERT(ARRAY_SIZE(swap_str) == USB_PD_CTRL_SWAP_COUNT);
+	p.role = USB_PD_CTRL_ROLE_NO_CHANGE;
+	p.mux = USB_PD_CTRL_MUX_NO_CHANGE;
+	p.swap = USB_PD_CTRL_SWAP_NONE;
+
+	if (argc < 2) {
+		fprintf(stderr, "No port specified.\n");
+		return -1;
+	}
+
+	p.port = strtol(argv[1], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Invalid param (port)\n");
+		return -1;
+	}
+
+	for (i = 2; i < argc; ++i) {
+		option_ok = 0;
+		if (!strcmp(argv[i], "auto")) {
+			if (argc != 3) {
+				fprintf(stderr, "\"auto\" may not be used "
+						"with other options.\n");
+				return -1;
+			}
+			p.role = USB_PD_CTRL_ROLE_TOGGLE_ON;
+			p.mux = USB_PD_CTRL_MUX_AUTO;
+			continue;
+		}
+
+		for (j = 0; j < ARRAY_SIZE(role_str); ++j) {
+			if (!strcmp(argv[i], role_str[j])) {
+				if (p.role != USB_PD_CTRL_ROLE_NO_CHANGE) {
+					fprintf(stderr,
+						"Only one role allowed.\n");
+					return -1;
+				}
+				p.role = j;
+				option_ok = 1;
+				break;
+			}
+		}
+		if (option_ok)
+			continue;
+
+		for (j = 0; j < ARRAY_SIZE(mux_str); ++j) {
+			if (!strcmp(argv[i], mux_str[j])) {
+				if (p.mux != USB_PD_CTRL_MUX_NO_CHANGE) {
+					fprintf(stderr,
+						"Only one mux type allowed.\n");
+					return -1;
+				}
+				p.mux = j;
+				option_ok = 1;
+				break;
+			}
+		}
+		if (option_ok)
+			continue;
+
+		for (j = 0; j < ARRAY_SIZE(swap_str); ++j) {
+			if (!strcmp(argv[i], swap_str[j])) {
+				if (p.swap != USB_PD_CTRL_SWAP_NONE) {
+					fprintf(stderr,
+						"Only one swap type allowed.\n");
+					return -1;
+				}
+				p.swap = j;
+				option_ok = 1;
+				break;
+			}
+		}
+
+		if (!option_ok) {
+			fprintf(stderr, "Unknown option: %s\n", argv[i]);
+			return -1;
+		}
+	}
+
+	if (ec_cmd_version_supported(EC_CMD_USB_PD_CONTROL, 2))
+		cmdver = 2;
+	else if (ec_cmd_version_supported(EC_CMD_USB_PD_CONTROL, 1))
+		cmdver = 1;
+	else
+		cmdver = 0;
+
+	rv = ec_command(EC_CMD_USB_PD_CONTROL, cmdver, &p, sizeof(p), ec_inbuf,
+			ec_max_insize);
+
+	if (rv < 0 || argc != 2)
+		return (rv < 0) ? rv : 0;
+
+	if (cmdver == 0) {
+		printf("Port C%d is %sabled, Role:%s Polarity:CC%d State:%d\n",
+		       p.port, (r->enabled) ? "en" : "dis",
+		       r->role == PD_ROLE_SOURCE ? "SRC" : "SNK",
+		       r->polarity + 1, r->state);
+	} else {
+		printf("Port C%d: %s, %s  State:%s\n"
+		       "Role:%s %s%s, Polarity:CC%d\n",
+		       p.port,
+		       (r_v1->enabled & PD_CTRL_RESP_ENABLED_COMMS) ?
+			       "enabled" :
+			       "disabled",
+		       (r_v1->enabled & PD_CTRL_RESP_ENABLED_CONNECTED) ?
+			       "connected" :
+			       "disconnected",
+		       r_v1->state,
+
+		       (r_v1->role & PD_CTRL_RESP_ROLE_POWER) ? "SRC" : "SNK",
+		       (r_v1->role & PD_CTRL_RESP_ROLE_DATA) ? "DFP" : "UFP",
+		       (r_v1->role & PD_CTRL_RESP_ROLE_VCONN) ? " VCONN" : "",
+		       r_v1->polarity + 1);
+
+		if (cmdver == 2) {
+			printf("CC State:");
+			if (r_v2->cc_state == PD_CC_NONE)
+				printf("None");
+			else if (r_v2->cc_state == PD_CC_UFP_AUDIO_ACC)
+				printf("UFP Audio accessory");
+			else if (r_v2->cc_state == PD_CC_UFP_DEBUG_ACC)
+				printf("UFP Debug accessory");
+			else if (r_v2->cc_state == PD_CC_UFP_ATTACHED)
+				printf("UFP attached");
+			else if (r_v2->cc_state == PD_CC_DFP_DEBUG_ACC)
+				printf("DFP Debug accessory");
+			else if (r_v2->cc_state == PD_CC_DFP_ATTACHED)
+				printf("DFP attached");
+			else
+				printf("UNKNOWN");
+			printf("\n");
+
+			if (r_v2->dp_mode) {
+				printf("DP pin mode:");
+				if (r_v2->dp_mode == MODE_DP_PIN_A)
+					printf("A");
+				else if (r_v2->dp_mode == MODE_DP_PIN_B)
+					printf("B");
+				else if (r_v2->dp_mode == MODE_DP_PIN_C)
+					printf("C");
+				else if (r_v2->dp_mode == MODE_DP_PIN_D)
+					printf("D");
+				else if (r_v2->dp_mode == MODE_DP_PIN_E)
+					printf("E");
+				else if (r_v2->dp_mode == MODE_DP_PIN_F)
+					printf("F");
+				else
+					printf("UNKNOWN");
+				printf("\n");
+			}
+
+			printf("Cable type:%s\n",
+			       r_v2->control_flags & USB_PD_CTRL_ACTIVE_CABLE ?
+				       "Active" :
+				       "Passive");
+
+			printf("TBT Adapter type:%s\n",
+			       r_v2->control_flags &
+					       USB_PD_CTRL_TBT_LEGACY_ADAPTER ?
+				       "Legacy" :
+				       "Gen3");
+
+			printf("Optical Cable:%s\n",
+			       r_v2->control_flags & USB_PD_CTRL_OPTICAL_CABLE ?
+				       "True" :
+				       "False");
+
+			printf("Link LSRX Communication:%s-directional\n",
+			       r_v2->control_flags &
+					       USB_PD_CTRL_ACTIVE_LINK_UNIDIR ?
+				       "Uni" :
+				       "Bi");
+
+			printf("TBT Cable Speed:");
+			switch (r_v2->cable_speed) {
+			case TBT_SS_U31_GEN1:
+				printf("TBT Gen1");
+				break;
+			case TBT_SS_U32_GEN1_GEN2:
+				printf("TBT Gen1 and TBT Gen2");
+				break;
+			case TBT_SS_TBT_GEN3:
+				printf("TBT Gen3");
+				break;
+			default:
+				printf("UNKNOWN");
+			}
+			printf("\n");
+
+			printf("Rounded support: 3rd Gen %srounded support\n",
+			       r_v2->cable_gen ? "and 4th Gen " : "");
+		}
+		/* If connected to a PD device, then print port partner info */
+		if ((r_v1->enabled & PD_CTRL_RESP_ENABLED_CONNECTED) &&
+		    (r_v1->enabled & PD_CTRL_RESP_ENABLED_PD_CAPABLE))
+			printf("PD Partner Capabilities:\n%s%s%s%s",
+			       (r_v1->role & PD_CTRL_RESP_ROLE_DR_POWER) ?
+				       " DR power\n" :
+				       "",
+			       (r_v1->role & PD_CTRL_RESP_ROLE_DR_DATA) ?
+				       " DR data\n" :
+				       "",
+			       (r_v1->role & PD_CTRL_RESP_ROLE_USB_COMM) ?
+				       " USB capable\n" :
+				       "",
+			       (r_v1->role & PD_CTRL_RESP_ROLE_UNCONSTRAINED) ?
+				       " Unconstrained power\n" :
+				       "");
+	}
+	return 0;
+}
+
+int cmd_usb_pd_dps(int argc, char *argv[])
+{
+	struct ec_params_usb_pd_dps_control p;
+	int rv;
+
+	/*
+	 * Set up requested flags.  If no flags were specified, p.mask will
+	 * be 0 and nothing will change.
+	 */
+	if (argc < 1) {
+		fprintf(stderr, "Usage: %s [enable|disable]\n", argv[0]);
+		return -1;
+	}
+
+	if (!strcasecmp(argv[1], "enable")) {
+		p.enable = 1;
+	} else if (!strcasecmp(argv[1], "disable")) {
+		p.enable = 0;
+	} else {
+		fprintf(stderr, "Usage: %s [enable|disable]\n", argv[0]);
+		return -1;
+	}
+
+	rv = ec_command(EC_CMD_USB_PD_DPS_CONTROL, 0, &p, sizeof(p), NULL, 0);
+	if (rv < 0)
+		return rv;
+
+	return 0;
+}
+
+static void print_pd_power_info(struct ec_response_usb_pd_power_info *r)
+{
+	switch (r->role) {
+	case USB_PD_PORT_POWER_DISCONNECTED:
+		printf("Disconnected");
+		break;
+	case USB_PD_PORT_POWER_SOURCE:
+		printf("SRC");
+		break;
+	case USB_PD_PORT_POWER_SINK:
+		printf("SNK");
+		break;
+	case USB_PD_PORT_POWER_SINK_NOT_CHARGING:
+		printf("SNK (not charging)");
+		break;
+	default:
+		printf("Unknown");
+	}
+
+	if ((r->role == USB_PD_PORT_POWER_SOURCE) && (r->meas.current_max))
+		printf(" %dmA", r->meas.current_max);
+
+	if ((r->role == USB_PD_PORT_POWER_DISCONNECTED) ||
+	    (r->role == USB_PD_PORT_POWER_SOURCE)) {
+		printf("\n");
+		return;
+	}
+
+	printf(r->dualrole ? " DRP" : " Charger");
+	switch (r->type) {
+	case USB_CHG_TYPE_PD:
+		printf(" PD");
+		break;
+	case USB_CHG_TYPE_C:
+		printf(" Type-C");
+		break;
+	case USB_CHG_TYPE_PROPRIETARY:
+		printf(" Proprietary");
+		break;
+	case USB_CHG_TYPE_BC12_DCP:
+		printf(" DCP");
+		break;
+	case USB_CHG_TYPE_BC12_CDP:
+		printf(" CDP");
+		break;
+	case USB_CHG_TYPE_BC12_SDP:
+		printf(" SDP");
+		break;
+	case USB_CHG_TYPE_OTHER:
+		printf(" Other");
+		break;
+	case USB_CHG_TYPE_VBUS:
+		printf(" VBUS");
+		break;
+	case USB_CHG_TYPE_UNKNOWN:
+		printf(" Unknown");
+		break;
+	}
+	printf(" %dmV / %dmA, max %dmV / %dmA", r->meas.voltage_now,
+	       r->meas.current_lim, r->meas.voltage_max, r->meas.current_max);
+	if (r->max_power)
+		printf(" / %dmW", r->max_power / 1000);
+	printf("\n");
+}
+
+int cmd_usb_pd_mux_info(int argc, char *argv[])
+{
+	struct ec_params_usb_pd_mux_info p;
+	struct ec_response_usb_pd_mux_info r;
+	int num_ports, rv, i;
+	bool tsv = false;
+
+	if (argc == 2 && (strncmp(argv[1], "tsv", 4) == 0)) {
+		tsv = true;
+	} else if (argc >= 2) {
+		fprintf(stderr, "Usage: %s [tsv]\n", argv[0]);
+		return -1;
+	}
+
+	rv = ec_command(EC_CMD_USB_PD_PORTS, 0, NULL, 0, ec_inbuf,
+			ec_max_insize);
+	if (rv < 0)
+		return rv;
+	num_ports = ((struct ec_response_usb_pd_ports *)ec_inbuf)->num_ports;
+
+	for (i = 0; i < num_ports; i++) {
+		p.port = i;
+		rv = ec_command(EC_CMD_USB_PD_MUX_INFO, 0, &p, sizeof(p), &r,
+				sizeof(r));
+		if (rv < 0)
+			return rv;
+
+		if (tsv) {
+			/*
+			 * Machine-readable tab-separated values. This set of
+			 * values is append-only. Columns should not be removed
+			 * or repurposed. Update the documentation above if new
+			 * columns are added.
+			 */
+			printf("%d\t", i);
+			printf("%d\t", !!(r.flags & USB_PD_MUX_USB_ENABLED));
+			printf("%d\t", !!(r.flags & USB_PD_MUX_DP_ENABLED));
+			printf("%s\t", r.flags & USB_PD_MUX_POLARITY_INVERTED ?
+					       "INVERTED" :
+					       "NORMAL");
+			printf("%d\t", !!(r.flags & USB_PD_MUX_HPD_IRQ));
+			printf("%d\n", !!(r.flags & USB_PD_MUX_HPD_LVL));
+		} else {
+			/* Human-readable mux info. */
+			printf("Port %d: ", i);
+			printf("USB=%d ", !!(r.flags & USB_PD_MUX_USB_ENABLED));
+			printf("DP=%d ", !!(r.flags & USB_PD_MUX_DP_ENABLED));
+			printf("POLARITY=%s ",
+			       r.flags & USB_PD_MUX_POLARITY_INVERTED ?
+				       "INVERTED" :
+				       "NORMAL");
+			printf("HPD_IRQ=%d ", !!(r.flags & USB_PD_MUX_HPD_IRQ));
+			printf("HPD_LVL=%d ", !!(r.flags & USB_PD_MUX_HPD_LVL));
+			printf("SAFE=%d ", !!(r.flags & USB_PD_MUX_SAFE_MODE));
+			printf("TBT=%d ",
+			       !!(r.flags & USB_PD_MUX_TBT_COMPAT_ENABLED));
+			printf("USB4=%d ",
+			       !!(r.flags & USB_PD_MUX_USB4_ENABLED));
+			printf("\n");
+		}
+	}
+
+	return 0;
+}
+
+int cmd_usb_pd_power(int argc, char *argv[])
+{
+	struct ec_params_usb_pd_power_info p;
+	struct ec_response_usb_pd_power_info *r =
+		(struct ec_response_usb_pd_power_info *)ec_inbuf;
+	int num_ports, i, rv;
+	char *e;
+
+	rv = ec_command(EC_CMD_USB_PD_PORTS, 0, NULL, 0, ec_inbuf,
+			ec_max_insize);
+	if (rv < 0)
+		return rv;
+	num_ports = ((struct ec_response_usb_pd_ports *)r)->num_ports;
+
+	if (argc < 2) {
+		for (i = 0; i < num_ports; i++) {
+			p.port = i;
+			rv = ec_command(EC_CMD_USB_PD_POWER_INFO, 0, &p,
+					sizeof(p), ec_inbuf, ec_max_insize);
+			if (rv < 0)
+				return rv;
+
+			printf("Port %d: ", i);
+			print_pd_power_info(r);
+		}
+	} else {
+		p.port = strtol(argv[1], &e, 0);
+		if (e && *e) {
+			fprintf(stderr, "Bad port.\n");
+			return -1;
+		}
+		rv = ec_command(EC_CMD_USB_PD_POWER_INFO, 0, &p, sizeof(p),
+				ec_inbuf, ec_max_insize);
+		if (rv < 0)
+			return rv;
+
+		printf("Port %d: ", p.port);
+		print_pd_power_info(r);
+	}
+
+	return 0;
+}
+
+int cmd_kbpress(int argc, char *argv[])
+{
+	struct ec_params_mkbp_simulate_key p;
+	char *e;
+	int rv;
+
+	if (argc != 4) {
+		fprintf(stderr, "Usage: %s <row> <col> <0|1>\n", argv[0]);
+		return -1;
+	}
+	p.row = strtol(argv[1], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad row.\n");
+		return -1;
+	}
+	p.col = strtol(argv[2], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad column.\n");
+		return -1;
+	}
+	p.pressed = strtol(argv[3], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad pressed flag.\n");
+		return -1;
+	}
+
+	printf("%s row %d col %d.\n", p.pressed ? "Pressing" : "Releasing",
+	       p.row, p.col);
+
+	rv = ec_command(EC_CMD_MKBP_SIMULATE_KEY, 0, &p, sizeof(p), NULL, 0);
+	if (rv < 0)
+		return rv;
+	printf("Done.\n");
+	return 0;
+}
+
+int cmd_keyboard_factory_test(int argc, char *argv[])
+{
+	struct ec_response_keyboard_factory_test r;
+	int rv;
+
+	rv = ec_command(EC_CMD_KEYBOARD_FACTORY_TEST, 0, NULL, 0, &r,
+			sizeof(r));
+	if (rv < 0)
+		return rv;
+
+	if (r.shorted != 0)
+		printf("Keyboard %d and %d pin are shorted.\n",
+		       r.shorted & 0x00ff, r.shorted >> 8);
+	else
+		printf("Keyboard factory test passed.\n");
+
+	return 0;
+}
+
+int cmd_panic_info(int argc, char *argv[])
+{
+	int rv;
+
+	rv = ec_command(EC_CMD_GET_PANIC_INFO, 0, NULL, 0, ec_inbuf,
+			ec_max_insize);
+	if (rv < 0)
+		return rv;
+
+	if (rv == 0) {
+		printf("No panic data.\n");
+		return 0;
+	}
+
+	std::vector<uint8_t> data(static_cast<uint8_t *>(ec_inbuf),
+				  static_cast<uint8_t *>(ec_inbuf) + rv);
+	auto result = ec::ParsePanicInfo(data);
+
+	if (!result.has_value()) {
+		fprintf(stderr, "%s", result.error().c_str());
+		return 1;
+	}
+	printf("%s", result.value().c_str());
+
+	return 0;
+}
+
+int cmd_power_info(int argc, char *argv[])
+{
+	struct ec_response_power_info_v1 r;
+	int rv;
+
+	rv = ec_command(EC_CMD_POWER_INFO, 1, NULL, 0, &r, sizeof(r));
+	if (rv < 0)
+		return rv;
+
+	printf("Power source:\t");
+	switch (r.system_power_source) {
+	case POWER_SOURCE_UNKNOWN:
+		printf("Unknown\n");
+		break;
+	case POWER_SOURCE_BATTERY:
+		printf("Battery\n");
+		break;
+	case POWER_SOURCE_AC:
+		printf("AC\n");
+		break;
+	case POWER_SOURCE_AC_BATTERY:
+		printf("AC + battery\n");
+		break;
+	}
+
+	printf("Battery state-of-charge: %d%%\n", r.battery_soc);
+	printf("Max AC power: %d Watts\n", r.ac_adapter_100pct);
+	printf("Battery 1Cd rate: %d\n", r.battery_1cd);
+	printf("RoP Avg: %d Watts\n", r.rop_avg);
+	printf("RoP Peak: %d Watts\n", r.rop_peak);
+	printf("Battery DBPT support level: %d\n",
+	       r.intel.batt_dbpt_support_level);
+	printf("Battery DBPT Max Peak Power: %d Watts\n",
+	       r.intel.batt_dbpt_max_peak_power);
+	printf("Battery DBPT Sus Peak Power: %d Watts\n",
+	       r.intel.batt_dbpt_sus_peak_power);
+	return 0;
+}
+
+int cmd_pse(int argc, char *argv[])
+{
+	struct ec_params_pse p;
+	struct ec_response_pse_status r;
+	int rsize = 0;
+	char *e;
+	int rv;
+
+	if (argc < 2 || argc > 3 || !strcmp(argv[1], "help")) {
+		printf("Usage: %s <port> [<subcmd>]\n", argv[0]);
+		printf("'pse <port> [status]' - Get port status\n");
+		printf("'pse <port> disable' - Disable port\n");
+		printf("'pse <port> enable' - Enable port\n");
+		return -1;
+	}
+
+	p.port = strtol(argv[1], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad port.\n");
+		return -1;
+	}
+
+	if (argc == 2 || !strcmp(argv[2], "status")) {
+		p.cmd = EC_PSE_STATUS;
+		rsize = sizeof(r);
+	} else if (!strcmp(argv[2], "disable")) {
+		p.cmd = EC_PSE_DISABLE;
+	} else if (!strcmp(argv[2], "enable")) {
+		p.cmd = EC_PSE_ENABLE;
+	} else {
+		fprintf(stderr, "Unknown command: %s\n", argv[2]);
+		return -1;
+	}
+
+	rv = ec_command(EC_CMD_PSE, 0, &p, sizeof(p), &r, rsize);
+	if (rv < 0)
+		return rv;
+
+	if (p.cmd == EC_PSE_STATUS) {
+		const char *status;
+
+		switch (r.status) {
+		case EC_PSE_STATUS_DISABLED:
+			status = "disabled";
+			break;
+		case EC_PSE_STATUS_ENABLED:
+			status = "enabled";
+			break;
+		case EC_PSE_STATUS_POWERED:
+			status = "powered";
+			break;
+		default:
+			status = "unknown";
+			break;
+		}
+
+		printf("Port %d: %s\n", p.port, status);
+	}
+
+	return 0;
+}
+
+int cmd_pstore_info(int argc, char *argv[])
+{
+	struct ec_response_pstore_info r;
+	int rv;
+
+	rv = ec_command(EC_CMD_PSTORE_INFO, 0, NULL, 0, &r, sizeof(r));
+	if (rv < 0)
+		return rv;
+
+	printf("PstoreSize %d\nAccessSize %d\n", r.pstore_size, r.access_size);
+	return 0;
+}
+
+int cmd_pstore_read(int argc, char *argv[])
+{
+	struct ec_params_pstore_read p;
+	uint8_t rdata[EC_PSTORE_SIZE_MAX];
+	int offset, size;
+	int rv;
+	int i;
+	char *e;
+	char *buf;
+
+	if (argc < 4) {
+		fprintf(stderr, "Usage: %s <offset> <size> <filename>\n",
+			argv[0]);
+		return -1;
+	}
+	offset = strtol(argv[1], &e, 0);
+	if ((e && *e) || offset < 0 || offset > 0x10000) {
+		fprintf(stderr, "Bad offset.\n");
+		return -1;
+	}
+	size = strtol(argv[2], &e, 0);
+	if ((e && *e) || size <= 0 || size > 0x10000) {
+		fprintf(stderr, "Bad size.\n");
+		return -1;
+	}
+	printf("Reading %d bytes at offset %d...\n", size, offset);
+
+	buf = (char *)malloc(size);
+	if (!buf) {
+		fprintf(stderr, "Unable to allocate buffer.\n");
+		return -1;
+	}
+
+	/* Read data in chunks */
+	for (i = 0; i < size; i += EC_PSTORE_SIZE_MAX) {
+		p.offset = offset + i;
+		p.size = MIN(size - i, EC_PSTORE_SIZE_MAX);
+		rv = ec_command(EC_CMD_PSTORE_READ, 0, &p, sizeof(p), rdata,
+				sizeof(rdata));
+		if (rv < 0) {
+			fprintf(stderr, "Read error at offset %d\n", i);
+			free(buf);
+			return rv;
+		}
+		memcpy(buf + i, rdata, p.size);
+	}
+
+	rv = write_file(argv[3], buf, size);
+	free(buf);
+	if (rv)
+		return rv;
+
+	printf("done.\n");
+	return 0;
+}
+
+int cmd_pstore_write(int argc, char *argv[])
+{
+	struct ec_params_pstore_write p;
+	int offset, size;
+	int rv;
+	int i;
+	char *e;
+	char *buf;
+
+	if (argc < 3) {
+		fprintf(stderr, "Usage: %s <offset> <filename>\n", argv[0]);
+		return -1;
+	}
+	offset = strtol(argv[1], &e, 0);
+	if ((e && *e) || offset < 0 || offset > 0x10000) {
+		fprintf(stderr, "Bad offset.\n");
+		return -1;
+	}
+
+	/* Read the input file */
+	buf = read_file(argv[2], &size);
+	if (!buf)
+		return -1;
+
+	printf("Writing to offset %d...\n", offset);
+
+	/* Write data in chunks */
+	for (i = 0; i < size; i += EC_PSTORE_SIZE_MAX) {
+		p.offset = offset + i;
+		p.size = MIN(size - i, EC_PSTORE_SIZE_MAX);
+		memcpy(p.data, buf + i, p.size);
+		rv = ec_command(EC_CMD_PSTORE_WRITE, 0, &p, sizeof(p), NULL, 0);
+		if (rv < 0) {
+			fprintf(stderr, "Write error at offset %d\n", i);
+			free(buf);
+			return rv;
+		}
+	}
+
+	free(buf);
+	printf("done.\n");
+	return 0;
+}
+
+int cmd_host_event_get_raw(int argc, char *argv[])
+{
+	uint32_t events = read_mapped_mem32(EC_MEMMAP_HOST_EVENTS);
+
+	if (events & EC_HOST_EVENT_MASK(EC_HOST_EVENT_INVALID)) {
+		printf("Current host events: invalid\n");
+		return -1;
+	}
+
+	printf("Current host events: 0x%08x\n", events);
+	return 0;
+}
+
+int cmd_host_event_get_b(int argc, char *argv[])
+{
+	struct ec_response_host_event_mask r;
+	int rv;
+
+	rv = ec_command(EC_CMD_HOST_EVENT_GET_B, 0, NULL, 0, &r, sizeof(r));
+	if (rv < 0)
+		return rv;
+	if (rv < sizeof(r)) {
+		fprintf(stderr, "Insufficient data received.\n");
+		return -1;
+	}
+
+	if (r.mask & EC_HOST_EVENT_MASK(EC_HOST_EVENT_INVALID)) {
+		printf("Current host events-B: invalid\n");
+		return -1;
+	}
+
+	printf("Current host events-B: 0x%08x\n", r.mask);
+	return 0;
+}
+
+int cmd_host_event_get_smi_mask(int argc, char *argv[])
+{
+	struct ec_response_host_event_mask r;
+	int rv;
+
+	rv = ec_command(EC_CMD_HOST_EVENT_GET_SMI_MASK, 0, NULL, 0, &r,
+			sizeof(r));
+	if (rv < 0)
+		return rv;
+
+	printf("Current host event SMI mask: 0x%08x\n", r.mask);
+	return 0;
+}
+
+int cmd_host_event_get_sci_mask(int argc, char *argv[])
+{
+	struct ec_response_host_event_mask r;
+	int rv;
+
+	rv = ec_command(EC_CMD_HOST_EVENT_GET_SCI_MASK, 0, NULL, 0, &r,
+			sizeof(r));
+	if (rv < 0)
+		return rv;
+
+	printf("Current host event SCI mask: 0x%08x\n", r.mask);
+	return 0;
+}
+
+int cmd_host_event_get_wake_mask(int argc, char *argv[])
+{
+	struct ec_response_host_event_mask r;
+	int rv;
+
+	rv = ec_command(EC_CMD_HOST_EVENT_GET_WAKE_MASK, 0, NULL, 0, &r,
+			sizeof(r));
+	if (rv < 0)
+		return rv;
+
+	printf("Current host event wake mask: 0x%08x\n", r.mask);
+	return 0;
+}
+
+int cmd_host_event_set_smi_mask(int argc, char *argv[])
+{
+	struct ec_params_host_event_mask p;
+	char *e;
+	int rv;
+
+	if (argc != 2) {
+		fprintf(stderr, "Usage: %s <mask>\n", argv[0]);
+		return -1;
+	}
+	p.mask = strtol(argv[1], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad mask.\n");
+		return -1;
+	}
+
+	rv = ec_command(EC_CMD_HOST_EVENT_SET_SMI_MASK, 0, &p, sizeof(p), NULL,
+			0);
+	if (rv < 0)
+		return rv;
+
+	printf("Mask set.\n");
+	return 0;
+}
+
+int cmd_host_event_set_sci_mask(int argc, char *argv[])
+{
+	struct ec_params_host_event_mask p;
+	char *e;
+	int rv;
+
+	if (argc != 2) {
+		fprintf(stderr, "Usage: %s <mask>\n", argv[0]);
+		return -1;
+	}
+	p.mask = strtol(argv[1], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad mask.\n");
+		return -1;
+	}
+
+	rv = ec_command(EC_CMD_HOST_EVENT_SET_SCI_MASK, 0, &p, sizeof(p), NULL,
+			0);
+	if (rv < 0)
+		return rv;
+
+	printf("Mask set.\n");
+	return 0;
+}
+
+int cmd_host_event_set_wake_mask(int argc, char *argv[])
+{
+	struct ec_params_host_event_mask p;
+	char *e;
+	int rv;
+
+	if (argc != 2) {
+		fprintf(stderr, "Usage: %s <mask>\n", argv[0]);
+		return -1;
+	}
+	p.mask = strtol(argv[1], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad mask.\n");
+		return -1;
+	}
+
+	rv = ec_command(EC_CMD_HOST_EVENT_SET_WAKE_MASK, 0, &p, sizeof(p), NULL,
+			0);
+	if (rv < 0)
+		return rv;
+
+	printf("Mask set.\n");
+	return 0;
+}
+
+int cmd_host_event_clear(int argc, char *argv[])
+{
+	struct ec_params_host_event_mask p;
+	char *e;
+	int rv;
+
+	if (argc != 2) {
+		fprintf(stderr, "Usage: %s <mask>\n", argv[0]);
+		return -1;
+	}
+	p.mask = strtol(argv[1], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad mask.\n");
+		return -1;
+	}
+
+	rv = ec_command(EC_CMD_HOST_EVENT_CLEAR, 0, &p, sizeof(p), NULL, 0);
+	if (rv < 0)
+		return rv;
+
+	printf("Host events cleared.\n");
+	return 0;
+}
+
+int cmd_host_event_clear_b(int argc, char *argv[])
+{
+	struct ec_params_host_event_mask p;
+	char *e;
+	int rv;
+
+	if (argc != 2) {
+		fprintf(stderr, "Usage: %s <mask>\n", argv[0]);
+		return -1;
+	}
+	p.mask = strtol(argv[1], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad mask.\n");
+		return -1;
+	}
+
+	rv = ec_command(EC_CMD_HOST_EVENT_CLEAR_B, 0, &p, sizeof(p), NULL, 0);
+	if (rv < 0)
+		return rv;
+
+	printf("Host events-B cleared.\n");
+	return 0;
+}
+
+int cmd_switches(int argc, char *argv[])
+{
+	uint8_t s = read_mapped_mem8(EC_MEMMAP_SWITCHES);
+	printf("Current switches:   0x%02x\n", s);
+	printf("Lid switch:         %s\n",
+	       (s & EC_SWITCH_LID_OPEN ? "OPEN" : "CLOSED"));
+	printf("Power button:       %s\n",
+	       (s & EC_SWITCH_POWER_BUTTON_PRESSED ? "DOWN" : "UP"));
+	printf("Write protect:      %sABLED\n",
+	       (s & EC_SWITCH_WRITE_PROTECT_DISABLED ? "DIS" : "EN"));
+	printf("Dedicated recovery: %sABLED\n",
+	       (s & EC_SWITCH_DEDICATED_RECOVERY ? "EN" : "DIS"));
+
+	return 0;
+}
+
+int cmd_tabletmode(int argc, char *argv[])
+{
+	struct ec_params_set_tablet_mode p;
+
+	if (argc != 2)
+		return EC_ERROR_PARAM_COUNT;
+
+	memset(&p, 0, sizeof(p));
+	/* |+1| to also make sure the strings the same length. */
+	if (strncmp(argv[1], "on", strlen("on") + 1) == 0) {
+		p.tablet_mode = TABLET_MODE_FORCE_TABLET;
+	} else if (strncmp(argv[1], "off", strlen("off") + 1) == 0) {
+		p.tablet_mode = TABLET_MODE_FORCE_CLAMSHELL;
+	} else if (strncmp(argv[1], "reset", strlen("reset") + 1) == 0) {
+		// Match tablet mode to the current HW orientation.
+		p.tablet_mode = TABLET_MODE_DEFAULT;
+	} else {
+		return EC_ERROR_PARAM1;
+	}
+
+	int rv = ec_command(EC_CMD_SET_TABLET_MODE, 0, &p, sizeof(p), NULL, 0);
+	rv = (rv < 0 ? rv : 0);
+
+	if (rv < 0) {
+		fprintf(stderr, "Failed to set tablet mode, rv=%d\n", rv);
+	} else {
+		printf("\n");
+		printf("SUCCESS. The tablet mode has been set.\n");
+	}
+	return rv;
+}
+
+int cmd_wireless(int argc, char *argv[])
+{
+	char *e;
+	int rv;
+	int now_flags;
+
+	if (argc < 2) {
+		fprintf(stderr,
+			"Usage: %s <flags> [<mask> [<susflags> <susmask>]]\n",
+			argv[0]);
+		fprintf(stderr, "  0x1 = WLAN radio\n"
+				"  0x2 = Bluetooth radio\n"
+				"  0x4 = WWAN power\n"
+				"  0x8 = WLAN power\n");
+		return -1;
+	}
+
+	now_flags = strtol(argv[1], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad flags.\n");
+		return -1;
+	}
+
+	if (argc < 3) {
+		/* Old-style - current flags only */
+		struct ec_params_switch_enable_wireless_v0 p;
+
+		p.enabled = now_flags;
+		rv = ec_command(EC_CMD_SWITCH_ENABLE_WIRELESS, 0, &p, sizeof(p),
+				NULL, 0);
+		if (rv < 0)
+			return rv;
+
+		printf("Success.\n");
+	} else {
+		/* New-style - masks and suspend flags */
+		struct ec_params_switch_enable_wireless_v1 p;
+		struct ec_response_switch_enable_wireless_v1 r;
+
+		memset(&p, 0, sizeof(p));
+
+		p.now_flags = now_flags;
+
+		p.now_mask = strtol(argv[2], &e, 0);
+		if (e && *e) {
+			fprintf(stderr, "Bad mask.\n");
+			return -1;
+		}
+
+		if (argc > 4) {
+			p.suspend_flags = strtol(argv[3], &e, 0);
+			if (e && *e) {
+				fprintf(stderr, "Bad suspend flags.\n");
+				return -1;
+			}
+
+			p.suspend_mask = strtol(argv[4], &e, 0);
+			if (e && *e) {
+				fprintf(stderr, "Bad suspend mask.\n");
+				return -1;
+			}
+		}
+
+		rv = ec_command(EC_CMD_SWITCH_ENABLE_WIRELESS,
+				EC_VER_SWITCH_ENABLE_WIRELESS, &p, sizeof(p),
+				&r, sizeof(r));
+		if (rv < 0)
+			return rv;
+
+		printf("Now=0x%x, suspend=0x%x\n", r.now_flags,
+		       r.suspend_flags);
+	}
+
+	return 0;
+}
+
+static void cmd_locate_chip_help(const char *const cmd)
+{
+	fprintf(stderr,
+		"Usage: %s <type> <index>\n"
+		"  <type> is one of:\n"
+		"    0: CBI_EEPROM\n"
+		"    1: TCPCs\n"
+		"  <index> instance # of <type>\n",
+		cmd);
+}
+
+static const char *bus_type[] = { "I2C", "EMBEDDED" };
+
+int cmd_locate_chip(int argc, char *argv[])
+{
+	struct ec_params_locate_chip p;
+	struct ec_response_locate_chip r = { 0 };
+	char *e;
+	int rv;
+
+	if (argc != 3) {
+		cmd_locate_chip_help(argv[0]);
+		return -1;
+	}
+
+	p.type = strtol(argv[1], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad type.\n");
+		cmd_locate_chip_help(argv[0]);
+		return -1;
+	}
+
+	p.index = strtol(argv[2], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad index.\n");
+		cmd_locate_chip_help(argv[0]);
+		return -1;
+	}
+
+	rv = ec_command(EC_CMD_LOCATE_CHIP, 0, &p, sizeof(p), &r, sizeof(r));
+
+	if (rv == -EC_RES_INVALID_PARAM - EECRESULT) {
+		fprintf(stderr, "Bus type %d not supported.\n", p.type);
+		return rv;
+	}
+
+	if (rv == -EC_RES_UNAVAILABLE - EECRESULT) {
+		fprintf(stderr, "Chip not found\n");
+		return rv;
+	}
+
+	if (rv == -EC_RES_OVERFLOW - EECRESULT) {
+		fprintf(stderr, "Index too large\n");
+		return rv;
+	}
+
+	if (rv < 0)
+		return rv;
+
+	if (r.bus_type >= EC_BUS_TYPE_COUNT ||
+	    r.bus_type >= ARRAY_SIZE(bus_type)) {
+		fprintf(stderr, "Unknown bus type (%d)\n", r.bus_type);
+		return -1;
+	}
+
+	/*
+	 * When changing the format of this print, make sure FAFT
+	 * (firmware_ECCbiEeprom) still passes. It may silently skip the test.
+	 */
+	printf("Bus: %s; Port: %d; Address: 0x%02x (7-bit format)\n",
+	       bus_type[r.bus_type], r.i2c_info.port,
+	       I2C_STRIP_FLAGS(r.i2c_info.addr_flags));
+
+	return 0;
+}
+
+int cmd_lcd_backlight(int argc, char *argv[])
+{
+	struct ec_params_switch_enable_backlight p;
+	char *e;
+	int rv;
+
+	if (argc != 2) {
+		fprintf(stderr, "Usage: %s <0|1>\n", argv[0]);
+		return -1;
+	}
+	p.enabled = strtol(argv[1], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad value.\n");
+		return -1;
+	}
+
+	rv = ec_command(EC_CMD_SWITCH_ENABLE_BKLIGHT, 0, &p, sizeof(p), NULL,
+			0);
+	if (rv < 0)
+		return rv;
+
+	printf("Success.\n");
+	return 0;
+}
+
+static void cmd_basestate_help(void)
+{
+	fprintf(stderr, "Usage: ectool basestate [attach | detach | reset]\n");
+}
+
+int cmd_basestate(int argc, char *argv[])
+{
+	struct ec_params_set_base_state p;
+
+	if (argc != 2) {
+		cmd_basestate_help();
+		return -1;
+	}
+
+	if (!strncmp(argv[1], "attach", 6)) {
+		p.cmd = EC_SET_BASE_STATE_ATTACH;
+	} else if (!strncmp(argv[1], "detach", 6)) {
+		p.cmd = EC_SET_BASE_STATE_DETACH;
+	} else if (!strncmp(argv[1], "reset", 5)) {
+		p.cmd = EC_SET_BASE_STATE_RESET;
+	} else {
+		cmd_basestate_help();
+		return -1;
+	}
+
+	return ec_command(EC_CMD_SET_BASE_STATE, 0, &p, sizeof(p), NULL, 0);
+}
+
+int cmd_ext_power_limit(int argc, char *argv[])
+{
+	/* Version 1 is used, no support for obsolete version 0 */
+	struct ec_params_external_power_limit_v1 p;
+	char *e;
+
+	if (argc != 3) {
+		fprintf(stderr, "Usage: %s <max_current_mA> <max_voltage_mV>\n",
+			argv[0]);
+		return -1;
+	}
+
+	p.current_lim = strtol(argv[1], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad param1.\n");
+		return -1;
+	}
+
+	p.voltage_lim = strtol(argv[2], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad param2.\n");
+		return -1;
+	}
+
+	/* Send version 1 of command */
+	return ec_command(EC_CMD_EXTERNAL_POWER_LIMIT, 1, &p, sizeof(p), NULL,
+			  0);
+}
+
+static void cmd_charge_current_limit_help(const char *cmd)
+{
+	fprintf(stderr,
+		"\n"
+		"  Usage: %s <max_current_mA>\n"
+		"    Set the maximum battery charging current.\n"
+		"  Usage: %s <max_current_mA> [battery_SoC]\n"
+		"    Set the maximum battery charging current and the minimum battery\n"
+		"    SoC at which it will apply. Setting [battery_SoC] is only \n"
+		"    supported in v1.\n"
+		"\n",
+		cmd, cmd);
+}
+
+int cmd_charge_current_limit(int argc, char *argv[])
+{
+	struct ec_params_current_limit_v1 p1;
+	uint32_t limit;
+	uint8_t battery_soc;
+	char *e;
+
+	/*
+	 * v0: max_current_ma (argc == 2)
+	 * v1: max_current_ma [battery_soc] (argc == 2 or 3)
+	 */
+	if (!ec_cmd_version_supported(EC_CMD_CHARGE_CURRENT_LIMIT, 1)) {
+		if (argc != 2) {
+			cmd_charge_current_limit_help(argv[0]);
+			return -1;
+		}
+	} else {
+		if (argc < 2 || argc > 3) {
+			cmd_charge_current_limit_help(argv[0]);
+			return -1;
+		}
+	}
+
+	/* max_current_ma */
+	limit = strtoull(argv[1], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "ERROR: Bad limit value: %s\n", argv[1]);
+		return -1;
+	}
+
+	if (argc == 2) {
+		struct ec_params_current_limit p0;
+
+		p0.limit = limit;
+		return ec_command(EC_CMD_CHARGE_CURRENT_LIMIT, 0, &p0,
+				  sizeof(p0), NULL, 0);
+	}
+
+	/* argc==3 for battery_soc */
+	battery_soc = strtol(argv[2], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "ERROR: Bad battery SoC value: %s\n", argv[2]);
+		return -1;
+	}
+
+	p1.limit = limit;
+	p1.battery_soc = battery_soc;
+	return ec_command(EC_CMD_CHARGE_CURRENT_LIMIT, 1, &p1, sizeof(p1), NULL,
+			  0);
+}
+
+static void cmd_charge_control_help(const char *cmd, const char *msg)
+{
+	if (msg)
+		fprintf(stderr, "ERROR: %s\n", msg);
+
+	fprintf(stderr,
+		"\n"
+		"  Usage: %s\n"
+		"    Get current settings.\n"
+		"  Usage: %s normal|idle|discharge\n"
+		"    Set charge mode (and disable battery sustainer).\n"
+		"  Usage: %s normal <lower> <upper> [<flags>]\n"
+		"    Enable battery sustainer. <lower> and <upper> are battery SoC\n"
+		"    between which EC tries to keep the battery level.\n"
+		"    <flags> are supported in v3+\n."
+		"\n",
+		cmd, cmd, cmd);
+}
+
+int cmd_charge_control(int argc, char *argv[])
+{
+	struct ec_params_charge_control p = {};
+	struct ec_response_charge_control r;
+	int version;
+	const char *const charge_mode_text[] = EC_CHARGE_MODE_TEXT;
+	char *e;
+	int rv;
+
+	if (ec_cmd_version_supported(EC_CMD_CHARGE_CONTROL, 3)) {
+		version = 3;
+	} else if (ec_cmd_version_supported(EC_CMD_CHARGE_CONTROL, 2)) {
+		if (argc > 4) {
+			cmd_charge_control_help(argv[0],
+						"<flags> not supported by EC");
+			return -1;
+		}
+		version = 2;
+	} else {
+		if (argc != 2) {
+			cmd_charge_control_help(
+				argv[0], "Bad arguments or EC is too old");
+			return -1;
+		}
+		version = 1;
+	}
+
+	if (argc == 1) {
+		p.cmd = EC_CHARGE_CONTROL_CMD_GET;
+		rv = ec_command(EC_CMD_CHARGE_CONTROL, version, &p, sizeof(p),
+				&r, sizeof(r));
+		if (rv < 0) {
+			fprintf(stderr, "Command failed.\n");
+			return rv;
+		}
+		printf("Charge mode = %s (%d)\n",
+		       r.mode < ARRAY_SIZE(charge_mode_text) ?
+			       charge_mode_text[r.mode] :
+			       "UNDEFINED",
+		       r.mode);
+		printf("Battery sustainer = %s (%d%% ~ %d%%)\n",
+		       (r.sustain_soc.lower != -1 &&
+			r.sustain_soc.upper != -1) ?
+			       "on" :
+			       "off",
+		       r.sustain_soc.lower, r.sustain_soc.upper);
+		return 0;
+	}
+
+	p.cmd = EC_CHARGE_CONTROL_CMD_SET;
+	if (!strcasecmp(argv[1], "normal")) {
+		p.mode = CHARGE_CONTROL_NORMAL;
+		if (argc == 2) {
+			p.sustain_soc.lower = -1;
+			p.sustain_soc.upper = -1;
+		} else if (argc > 3) {
+			p.sustain_soc.lower = strtol(argv[2], &e, 0);
+			if (e && *e) {
+				cmd_charge_control_help(
+					argv[0], "Bad character in <lower>");
+				return -1;
+			}
+			p.sustain_soc.upper = strtol(argv[3], &e, 0);
+			if (e && *e) {
+				cmd_charge_control_help(
+					argv[0], "Bad character in <upper>");
+				return -1;
+			}
+			if (argc == 5) {
+				p.flags = strtoul(argv[4], &e, 0);
+				if (e && *e) {
+					cmd_charge_control_help(
+						argv[0],
+						"Bad character in <flags>");
+					return -1;
+				}
+			}
+		} else {
+			cmd_charge_control_help(argv[0], "Bad arguments");
+			return -1;
+		}
+	} else if (!strcasecmp(argv[1], "idle")) {
+		if (argc != 2) {
+			cmd_charge_control_help(argv[0], "Bad arguments");
+			return -1;
+		}
+		p.mode = CHARGE_CONTROL_IDLE;
+	} else if (!strcasecmp(argv[1], "discharge")) {
+		if (argc != 2) {
+			cmd_charge_control_help(argv[0], "Bad arguments");
+			return -1;
+		}
+		p.mode = CHARGE_CONTROL_DISCHARGE;
+	} else {
+		cmd_charge_control_help(argv[0], "Bad sub-command");
+		return -1;
+	}
+
+	rv = ec_command(EC_CMD_CHARGE_CONTROL, version, &p, sizeof(p), NULL, 0);
+	if (rv < 0) {
+		fprintf(stderr, "Is AC connected?\n");
+		return rv;
+	}
+
+	switch (p.mode) {
+	case CHARGE_CONTROL_NORMAL:
+		printf("Charge state machine is in normal mode%s.\n",
+		       (p.sustain_soc.lower == -1 ||
+			p.sustain_soc.upper == -1) ?
+			       "" :
+			       " with sustainer enabled");
+		break;
+	case CHARGE_CONTROL_IDLE:
+		printf("Charge state machine force idle.\n");
+		break;
+	case CHARGE_CONTROL_DISCHARGE:
+		printf("Charge state machine force discharge.\n");
+		break;
+	default:
+		break;
+	}
+	return 0;
+}
+
+static void print_bool(const char *name, bool value)
+{
+	printf("%s = %s\n", name, value ? "true" : "false");
+}
+
+static int cmd_chargesplash(int argc, char **argv)
+{
+	static struct {
+		const char *name;
+		enum ec_chargesplash_cmd cmd;
+	} actions[] = {
+		{ "state", EC_CHARGESPLASH_GET_STATE },
+		{ "request", EC_CHARGESPLASH_REQUEST },
+		{ "lockout", EC_CHARGESPLASH_LOCKOUT },
+		{ "reset", EC_CHARGESPLASH_RESET },
+	};
+	struct ec_params_chargesplash params;
+	struct ec_response_chargesplash resp;
+
+	if (argc != 2) {
+		goto usage;
+	}
+
+	for (int i = 0; i < ARRAY_SIZE(actions); i++) {
+		if (!strcasecmp(actions[i].name, argv[1])) {
+			params.cmd = actions[i].cmd;
+			if (ec_command(EC_CMD_CHARGESPLASH, 0, &params,
+				       sizeof(params), &resp,
+				       sizeof(resp)) < 0) {
+				fprintf(stderr, "Host command failed\n");
+				return -1;
+			}
+
+			print_bool("requested", resp.requested);
+			print_bool("display_initialized",
+				   resp.display_initialized);
+			print_bool("locked_out", resp.locked_out);
+			return 0;
+		}
+	}
+
+usage:
+	fprintf(stderr, "Usage: %s <state|request|lockout|reset>", argv[0]);
+	return -1;
+}
+
+#define ST_CMD_SIZE ST_FLD_SIZE(ec_params_charge_state, cmd)
+#define ST_PRM_SIZE(SUBCMD) \
+	(ST_CMD_SIZE + ST_FLD_SIZE(ec_params_charge_state, SUBCMD))
+#define ST_RSP_SIZE(SUBCMD) ST_FLD_SIZE(ec_response_charge_state, SUBCMD)
+
+/* Table of subcommand sizes for EC_CMD_CHARGE_STATE */
+static const struct {
+	uint8_t to_ec_size;
+	uint8_t from_ec_size;
+} cs_paramcount[] = {
+	/* Order must match enum charge_state_command */
+	{ ST_CMD_SIZE, ST_RSP_SIZE(get_state) },
+	{ ST_PRM_SIZE(get_param), ST_RSP_SIZE(get_param) },
+	{ ST_PRM_SIZE(set_param), 0 },
+};
+BUILD_ASSERT(ARRAY_SIZE(cs_paramcount) == CHARGE_STATE_NUM_CMDS);
+
+#undef ST_CMD_SIZE
+#undef ST_PRM_SIZE
+#undef ST_RSP_SIZE
+
+static int cs_do_cmd(struct ec_params_charge_state *to_ec,
+		     struct ec_response_charge_state *from_ec)
+{
+	int rv;
+	int cmd = to_ec->cmd;
+
+	rv = ec_command(EC_CMD_CHARGE_STATE, 0, to_ec,
+			cs_paramcount[cmd].to_ec_size, from_ec,
+			cs_paramcount[cmd].from_ec_size);
+
+	return (rv < 0 ? 1 : 0);
+}
+
+static const char *const base_params[] = {
+	"chg_voltage", "chg_current", "chg_input_current",
+	"chg_status",  "chg_option",  "limit_power",
+};
+BUILD_ASSERT(ARRAY_SIZE(base_params) == CS_NUM_BASE_PARAMS);
+
+static int cmd_charge_state(int argc, char **argv)
+{
+	struct ec_params_charge_state param;
+	struct ec_response_charge_state resp;
+	uint32_t p, v;
+	int i, r;
+	char *e;
+
+	if (argc > 1 && !strcasecmp(argv[1], "show")) {
+		param.cmd = CHARGE_STATE_CMD_GET_STATE;
+		r = cs_do_cmd(&param, &resp);
+		if (r)
+			return r;
+		printf("ac = %d\n", resp.get_state.ac);
+		printf("chg_voltage = %dmV\n", resp.get_state.chg_voltage);
+		printf("chg_current = %dmA\n", resp.get_state.chg_current);
+		printf("chg_input_current = %dmA\n",
+		       resp.get_state.chg_input_current);
+		printf("batt_state_of_charge = %d%%\n",
+		       resp.get_state.batt_state_of_charge);
+		return 0;
+	}
+
+	if (argc > 1 && !strcasecmp(argv[1], "param")) {
+		switch (argc) {
+		case 3:
+			if (!strcasecmp(argv[2], "help"))
+				break;
+			param.cmd = CHARGE_STATE_CMD_GET_PARAM;
+			p = strtoull(argv[2], &e, 0);
+			if (e && *e) {
+				fprintf(stderr, "Bad param: %s\n", argv[2]);
+				return -1;
+			}
+			param.get_param.param = p;
+			r = cs_do_cmd(&param, &resp);
+			if (r)
+				return r;
+			v = resp.get_param.value;
+			if (p < CS_NUM_BASE_PARAMS)
+				printf("%d (0x%x)       # %s\n", v, v,
+				       base_params[p]);
+			else
+				printf("%d (0x%x)\n", v, v);
+			return 0;
+		case 4:
+			param.cmd = CHARGE_STATE_CMD_SET_PARAM;
+			p = strtoull(argv[2], &e, 0);
+			if (e && *e) {
+				fprintf(stderr, "Bad param: %s\n", argv[2]);
+				return -1;
+			}
+			v = strtoull(argv[3], &e, 0);
+			if (e && *e) {
+				fprintf(stderr, "Bad value: %s\n", argv[3]);
+				return -1;
+			}
+			param.set_param.param = p;
+			param.set_param.value = v;
+			return cs_do_cmd(&param, &resp);
+		}
+
+		printf("base params:\n");
+		for (i = 0; i < CS_NUM_BASE_PARAMS; i++)
+			printf("  %d   %s\n", i, base_params[i]);
+		printf("custom profile params:\n");
+		printf("  0x%x - 0x%x\n", CS_PARAM_CUSTOM_PROFILE_MIN,
+		       CS_PARAM_CUSTOM_PROFILE_MAX);
+
+		return 0;
+	}
+
+	printf("Usage:\n");
+	printf("  %s show                  - show current state\n", argv[0]);
+	printf("  %s param NUM [VALUE]     - get/set param NUM\n", argv[0]);
+	printf("  %s param help            - show known param NUMs\n", argv[0]);
+	return 0;
+}
+
+int cmd_gpio_get(int argc, char *argv[])
+{
+	struct ec_params_gpio_get_v1 p_v1;
+	struct ec_response_gpio_get_v1 r_v1;
+	int i, rv, subcmd, num_gpios;
+	int cmdver = 1;
+
+	if (!ec_cmd_version_supported(EC_CMD_GPIO_GET, cmdver)) {
+		struct ec_params_gpio_get p;
+		struct ec_response_gpio_get r;
+
+		/* Fall back to version 0 command */
+		cmdver = 0;
+		if (argc != 2) {
+			fprintf(stderr, "Usage: %s <GPIO name>\n", argv[0]);
+			return -1;
+		}
+
+		if (strlen(argv[1]) + 1 > sizeof(p.name)) {
+			fprintf(stderr, "GPIO name too long.\n");
+			return -1;
+		}
+		strcpy(p.name, argv[1]);
+
+		rv = ec_command(EC_CMD_GPIO_GET, cmdver, &p, sizeof(p), &r,
+				sizeof(r));
+		if (rv < 0)
+			return rv;
+
+		printf("GPIO %s = %d\n", p.name, r.val);
+		return 0;
+	}
+
+	if (argc > 2 || (argc == 2 && !strcmp(argv[1], "help"))) {
+		printf("Usage: %s [<subcmd> <GPIO name>]\n", argv[0]);
+		printf("'gpioget <GPIO_NAME>' - Get value by name\n");
+		printf("'gpioget count' - Get count of GPIOS\n");
+		printf("'gpioget all' - Get info for all GPIOs\n");
+		return -1;
+	}
+
+	/* Keeping it consistent with console command behavior */
+	if (argc == 1)
+		subcmd = EC_GPIO_GET_INFO;
+	else if (!strcmp(argv[1], "count"))
+		subcmd = EC_GPIO_GET_COUNT;
+	else if (!strcmp(argv[1], "all"))
+		subcmd = EC_GPIO_GET_INFO;
+	else
+		subcmd = EC_GPIO_GET_BY_NAME;
+
+	if (subcmd == EC_GPIO_GET_BY_NAME) {
+		p_v1.subcmd = EC_GPIO_GET_BY_NAME;
+		if (strlen(argv[1]) + 1 > sizeof(p_v1.get_value_by_name.name)) {
+			fprintf(stderr, "GPIO name too long.\n");
+			return -1;
+		}
+		strcpy(p_v1.get_value_by_name.name, argv[1]);
+
+		rv = ec_command(EC_CMD_GPIO_GET, cmdver, &p_v1, sizeof(p_v1),
+				&r_v1, sizeof(r_v1));
+
+		if (rv < 0)
+			return rv;
+
+		printf("GPIO %s = %d\n", p_v1.get_value_by_name.name,
+		       r_v1.get_value_by_name.val);
+		return 0;
+	}
+
+	/* Need GPIO count for EC_GPIO_GET_COUNT or EC_GPIO_GET_INFO */
+	p_v1.subcmd = EC_GPIO_GET_COUNT;
+	rv = ec_command(EC_CMD_GPIO_GET, cmdver, &p_v1, sizeof(p_v1), &r_v1,
+			sizeof(r_v1));
+	if (rv < 0)
+		return rv;
+
+	if (subcmd == EC_GPIO_GET_COUNT) {
+		printf("GPIO COUNT = %d\n", r_v1.get_count.val);
+		return 0;
+	}
+
+	/* subcmd EC_GPIO_GET_INFO */
+	num_gpios = r_v1.get_count.val;
+	p_v1.subcmd = EC_GPIO_GET_INFO;
+
+	for (i = 0; i < num_gpios; i++) {
+		p_v1.get_info.index = i;
+
+		rv = ec_command(EC_CMD_GPIO_GET, cmdver, &p_v1, sizeof(p_v1),
+				&r_v1, sizeof(r_v1));
+		if (rv < 0)
+			return rv;
+
+		printf("%2d %-32s 0x%04X\n", r_v1.get_info.val,
+		       r_v1.get_info.name, r_v1.get_info.flags);
+	}
+
+	return 0;
+}
+
+int cmd_gpio_set(int argc, char *argv[])
+{
+	struct ec_params_gpio_set p;
+	char *e;
+	int rv;
+
+	if (argc != 3) {
+		fprintf(stderr, "Usage: %s <GPIO name> <0 | 1>\n", argv[0]);
+		return -1;
+	}
+
+	if (strlen(argv[1]) + 1 > sizeof(p.name)) {
+		fprintf(stderr, "GPIO name too long.\n");
+		return -1;
+	}
+	strcpy(p.name, argv[1]);
+
+	p.val = strtol(argv[2], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad value.\n");
+		return -1;
+	}
+
+	rv = ec_command(EC_CMD_GPIO_SET, 0, &p, sizeof(p), NULL, 0);
+	if (rv < 0)
+		return rv;
+
+	printf("GPIO %s set to %d\n", p.name, p.val);
+	return 0;
+}
+
+void print_battery_flags(int flags)
+{
+	printf("  Flags                   0x%02x", flags);
+	if (flags & EC_BATT_FLAG_AC_PRESENT)
+		printf(" AC_PRESENT");
+	if (flags & EC_BATT_FLAG_BATT_PRESENT)
+		printf(" BATT_PRESENT");
+	if (flags & EC_BATT_FLAG_DISCHARGING)
+		printf(" DISCHARGING");
+	if (flags & EC_BATT_FLAG_CHARGING)
+		printf(" CHARGING");
+	if (flags & EC_BATT_FLAG_LEVEL_CRITICAL)
+		printf(" LEVEL_CRITICAL");
+	if (flags & EC_BATT_FLAG_CUT_OFF)
+		printf(" CUT_OFF");
+	printf("\n");
+}
+
+static int get_battery_command_print_info(
+	uint8_t index,
+	const struct ec_response_battery_static_info_v2 *const static_r)
+{
+	struct ec_params_battery_dynamic_info dynamic_p = {
+		.index = index,
+	};
+	struct ec_response_battery_dynamic_info dynamic_r;
+	int rv;
+
+	rv = ec_command(EC_CMD_BATTERY_GET_DYNAMIC, 0, &dynamic_p,
+			sizeof(dynamic_p), &dynamic_r, sizeof(dynamic_r));
+	if (rv < 0)
+		return -1;
+
+	printf("Battery %d info:\n", index);
+
+	if (dynamic_r.flags & EC_BATT_FLAG_INVALID_DATA) {
+		printf("  Invalid data (not present?)\n");
+		return -1;
+	}
+
+	if (!is_string_printable(static_r->manufacturer))
+		goto cmd_error;
+	printf("  OEM name:               %s\n", static_r->manufacturer);
+
+	if (!is_string_printable(static_r->device_name))
+		goto cmd_error;
+	printf("  Model number:           %s\n", static_r->device_name);
+
+	if (!is_string_printable(static_r->chemistry))
+		goto cmd_error;
+	printf("  Chemistry   :           %s\n", static_r->chemistry);
+
+	if (!is_string_printable(static_r->serial))
+		goto cmd_error;
+	printf("  Serial number:          %s\n", static_r->serial);
+
+	if (!is_battery_range(static_r->design_capacity))
+		goto cmd_error;
+	printf("  Design capacity:        %u mAh\n", static_r->design_capacity);
+
+	if (!is_battery_range(dynamic_r.full_capacity))
+		goto cmd_error;
+	printf("  Last full charge:       %u mAh\n", dynamic_r.full_capacity);
+
+	if (!is_battery_range(static_r->design_voltage))
+		goto cmd_error;
+	printf("  Design output voltage   %u mV\n", static_r->design_voltage);
+
+	if (!is_battery_range(static_r->cycle_count))
+		goto cmd_error;
+	printf("  Cycle count             %u\n", static_r->cycle_count);
+
+	if (!is_battery_range(dynamic_r.actual_voltage))
+		goto cmd_error;
+	printf("  Present voltage         %u mV\n", dynamic_r.actual_voltage);
+
+	/* current can be negative */
+	printf("  Present current         %d mA\n", dynamic_r.actual_current);
+
+	if (!is_battery_range(dynamic_r.remaining_capacity))
+		goto cmd_error;
+	printf("  Remaining capacity      %u mAh\n",
+	       dynamic_r.remaining_capacity);
+
+	if (!is_battery_range(dynamic_r.desired_voltage))
+		goto cmd_error;
+	printf("  Desired voltage         %u mV\n", dynamic_r.desired_voltage);
+
+	if (!is_battery_range(dynamic_r.desired_current))
+		goto cmd_error;
+	printf("  Desired current         %u mA\n", dynamic_r.desired_current);
+
+	print_battery_flags(dynamic_r.flags);
+	return 0;
+
+cmd_error:
+	fprintf(stderr, "Bad battery info value.\n");
+	return -1;
+}
+
+static int get_battery_command_v2(uint8_t index)
+{
+	struct ec_params_battery_static_info static_p = {
+		.index = index,
+	};
+	struct ec_response_battery_static_info_v2 static_r;
+	int rv;
+
+	rv = ec_command(EC_CMD_BATTERY_GET_STATIC, 2, &static_p,
+			sizeof(static_p), &static_r, sizeof(static_r));
+	if (rv < 0) {
+		fprintf(stderr, "CMD_BATTERY_GET_STATIC v2 failed: %d\n", rv);
+		return -1;
+	}
+
+	return get_battery_command_print_info(index, &static_r);
+}
+
+static int get_battery_command_v1(uint8_t index)
+{
+	struct ec_params_battery_static_info static_p {
+		.index = index,
+	};
+	struct ec_response_battery_static_info_v1 static_r;
+	int rv;
+
+	rv = ec_command(EC_CMD_BATTERY_GET_STATIC, 1, &static_p,
+			sizeof(static_p), &static_r, sizeof(static_r));
+	if (rv < 0) {
+		fprintf(stderr, "CMD_BATTERY_GET_STATIC v1 failed: %d\n", rv);
+		return -1;
+	}
+
+	/* Translate v1 response into v2 to display it */
+	struct ec_response_battery_static_info_v2 static_v2 = {
+		.design_capacity = static_r.design_capacity,
+		.design_voltage = static_r.design_voltage,
+		.cycle_count = static_r.cycle_count,
+	};
+	strncpy(static_v2.manufacturer, static_r.manufacturer_ext,
+		sizeof(static_v2.manufacturer) - 1);
+	strncpy(static_v2.device_name, static_r.model_ext,
+		sizeof(static_v2.device_name) - 1);
+	strncpy(static_v2.serial, static_r.serial_ext,
+		sizeof(static_v2.serial) - 1);
+	strncpy(static_v2.chemistry, static_r.type_ext,
+		sizeof(static_v2.chemistry) - 1);
+
+	return get_battery_command_print_info(index, &static_v2);
+}
+static int get_battery_command_v0(uint8_t index)
+{
+	struct ec_params_battery_static_info static_p = {
+		.index = index,
+	};
+	struct ec_response_battery_static_info static_r;
+	int rv;
+
+	rv = ec_command(EC_CMD_BATTERY_GET_STATIC, 0, &static_p,
+			sizeof(static_p), &static_r, sizeof(static_r));
+	if (rv < 0) {
+		fprintf(stderr, "CMD_BATTERY_GET_STATIC v0 failed: %d\n", rv);
+		return -1;
+	}
+
+	/* Translate v0 response into v2 to display it */
+	struct ec_response_battery_static_info_v2 static_v2 = {
+		.design_capacity = static_r.design_capacity,
+		.design_voltage = static_r.design_voltage,
+		.cycle_count = static_r.cycle_count,
+	};
+	strncpy(static_v2.manufacturer, static_r.manufacturer,
+		sizeof(static_v2.manufacturer) - 1);
+	strncpy(static_v2.device_name, static_r.model,
+		sizeof(static_v2.device_name) - 1);
+	strncpy(static_v2.serial, static_r.serial,
+		sizeof(static_v2.serial) - 1);
+	strncpy(static_v2.chemistry, static_r.type,
+		sizeof(static_v2.chemistry) - 1);
+
+	return get_battery_command_print_info(index, &static_v2);
+}
+
+int cmd_battery(int argc, char *argv[])
+{
+	char batt_text[EC_MEMMAP_TEXT_MAX];
+	int rv, val;
+	char *e;
+	int index = 0;
+	uint8_t flags;
+
+	if (argc > 2) {
+		fprintf(stderr, "Usage: %s [index]\n", argv[0]);
+		return -1;
+	} else if (argc == 2) {
+		index = strtol(argv[1], &e, 0);
+		if (e && *e) {
+			fprintf(stderr, "Bad battery index.\n");
+			return -1;
+		}
+	}
+
+	/*
+	 * Prefer to use newer hostcmd versions if supported because these allow
+	 * us to read longer strings, and always use hostcmd for non-primary
+	 * batteries because memmap doesn't export that data.
+	 */
+	uint32_t versions;
+	ec_get_cmd_versions(EC_CMD_BATTERY_GET_STATIC, &versions);
+
+	if (versions & EC_VER_MASK(2))
+		return get_battery_command_v2(index);
+	else if (versions & EC_VER_MASK(1))
+		return get_battery_command_v1(index);
+	else if (index > 0)
+		return get_battery_command_v0(index);
+
+	val = read_mapped_mem8(EC_MEMMAP_BATTERY_VERSION);
+	if (val < 1) {
+		fprintf(stderr, "Battery version %d is not supported\n", val);
+		return -1;
+	}
+
+	flags = read_mapped_mem8(EC_MEMMAP_BATT_FLAG);
+
+	printf("Battery info:\n");
+
+	rv = read_mapped_string(EC_MEMMAP_BATT_MFGR, batt_text,
+				sizeof(batt_text));
+	if (rv < 0 || !is_string_printable(batt_text))
+		goto cmd_error;
+	printf("  OEM name:               %s\n", batt_text);
+
+	rv = read_mapped_string(EC_MEMMAP_BATT_MODEL, batt_text,
+				sizeof(batt_text));
+	if (rv < 0 || !is_string_printable(batt_text))
+		goto cmd_error;
+	printf("  Model number:           %s\n", batt_text);
+
+	rv = read_mapped_string(EC_MEMMAP_BATT_TYPE, batt_text,
+				sizeof(batt_text));
+	if (rv < 0 || !is_string_printable(batt_text))
+		goto cmd_error;
+	printf("  Chemistry   :           %s\n", batt_text);
+
+	rv = read_mapped_string(EC_MEMMAP_BATT_SERIAL, batt_text,
+				sizeof(batt_text));
+	printf("  Serial number:          %s\n", batt_text);
+
+	val = read_mapped_mem32(EC_MEMMAP_BATT_DCAP);
+	if (!is_battery_range(val))
+		goto cmd_error;
+	printf("  Design capacity:        %u mAh\n", val);
+
+	val = read_mapped_mem32(EC_MEMMAP_BATT_LFCC);
+	if (!is_battery_range(val))
+		goto cmd_error;
+	printf("  Last full charge:       %u mAh\n", val);
+
+	val = read_mapped_mem32(EC_MEMMAP_BATT_DVLT);
+	if (!is_battery_range(val))
+		goto cmd_error;
+	printf("  Design output voltage   %u mV\n", val);
+
+	val = read_mapped_mem32(EC_MEMMAP_BATT_CCNT);
+	if (!is_battery_range(val))
+		goto cmd_error;
+	printf("  Cycle count             %u\n", val);
+
+	val = read_mapped_mem32(EC_MEMMAP_BATT_VOLT);
+	if (!is_battery_range(val))
+		goto cmd_error;
+	printf("  Present voltage         %u mV\n", val);
+
+	val = read_mapped_mem32(EC_MEMMAP_BATT_RATE);
+	if (!is_battery_range(val))
+		goto cmd_error;
+	printf("  Present current         %u mA%s\n", val,
+	       flags & EC_BATT_FLAG_DISCHARGING ? " (discharging)" : "");
+
+	val = read_mapped_mem32(EC_MEMMAP_BATT_CAP);
+	if (!is_battery_range(val))
+		goto cmd_error;
+	printf("  Remaining capacity      %u mAh\n", val);
+
+	print_battery_flags(flags);
+
+	return 0;
+cmd_error:
+	fprintf(stderr, "Bad battery info value. Check protocol version.\n");
+	return -1;
+}
+
+int cmd_battery_cut_off(int argc, char *argv[])
+{
+	struct ec_params_battery_cutoff p;
+	int cmd_version;
+	int rv;
+
+	memset(&p, 0, sizeof(p));
+	if (ec_cmd_version_supported(EC_CMD_BATTERY_CUT_OFF, 1)) {
+		cmd_version = 1;
+		if (argc > 1) {
+			if (!strcasecmp(argv[1], "at-shutdown")) {
+				p.flags = EC_BATTERY_CUTOFF_FLAG_AT_SHUTDOWN;
+			} else {
+				fprintf(stderr, "Bad parameter: %s\n", argv[1]);
+				return -1;
+			}
+		}
+	} else {
+		/* Fall back to version 0 command */
+		cmd_version = 0;
+		if (argc > 1) {
+			if (!strcasecmp(argv[1], "at-shutdown")) {
+				fprintf(stderr, "Explicit 'at-shutdown' ");
+				fprintf(stderr, "parameter not supported.\n");
+			} else {
+				fprintf(stderr, "Bad parameter: %s\n", argv[1]);
+			}
+			return -1;
+		}
+	}
+
+	rv = ec_command(EC_CMD_BATTERY_CUT_OFF, cmd_version, &p, sizeof(p),
+			NULL, 0);
+	rv = (rv < 0 ? rv : 0);
+
+	if (rv < 0) {
+		fprintf(stderr, "Failed to cut off battery, rv=%d\n", rv);
+		fprintf(stderr,
+			"It is expected if the rv is -%d "
+			"(EC_RES_INVALID_COMMAND) if the battery "
+			"doesn't support cut-off function.\n",
+			EC_RES_INVALID_COMMAND);
+	} else {
+		printf("\n");
+		printf("SUCCESS. The battery has arranged a cut-off.\n");
+
+		if (cmd_version == 1 &&
+		    (p.flags & EC_BATTERY_CUTOFF_FLAG_AT_SHUTDOWN))
+			printf("The battery will be cut off after shutdown.\n");
+		else
+			printf("The system should be shutdown immediately.\n");
+
+		printf("\n");
+	}
+	return rv;
+}
+
+int cmd_battery_vendor_param(int argc, char *argv[])
+{
+	struct ec_params_battery_vendor_param p;
+	struct ec_response_battery_vendor_param r;
+	char *e;
+	int rv;
+
+	if (argc < 3)
+		goto cmd_battery_vendor_param_usage;
+
+	if (!strcasecmp(argv[1], "get"))
+		p.mode = BATTERY_VENDOR_PARAM_MODE_GET;
+	else if (!strcasecmp(argv[1], "set"))
+		p.mode = BATTERY_VENDOR_PARAM_MODE_SET;
+	else
+		goto cmd_battery_vendor_param_usage;
+
+	p.param = strtol(argv[2], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Invalid param.\n");
+		goto cmd_battery_vendor_param_usage;
+	}
+
+	if (p.mode == BATTERY_VENDOR_PARAM_MODE_SET) {
+		if (argc != 4) {
+			fprintf(stderr, "Missing value.\n");
+			goto cmd_battery_vendor_param_usage;
+		}
+
+		p.value = strtol(argv[3], &e, 0);
+		if (e && *e) {
+			fprintf(stderr, "Invalid value.\n");
+			goto cmd_battery_vendor_param_usage;
+		}
+	}
+
+	rv = ec_command(EC_CMD_BATTERY_VENDOR_PARAM, 0, &p, sizeof(p), &r,
+			sizeof(r));
+
+	if (rv < 0)
+		return rv;
+
+	printf("0x%08x\n", r.value);
+
+	return 0;
+
+cmd_battery_vendor_param_usage:
+	fprintf(stderr,
+		"Usage:\t %s get <param>\n"
+		"\t %s set <param> <value>\n",
+		argv[0], argv[0]);
+	return -1;
+}
+
+int cmd_board_version(int argc, char *argv[])
+{
+	struct ec_response_board_version response;
+	int rv;
+
+	rv = ec_command(EC_CMD_GET_BOARD_VERSION, 0, NULL, 0, &response,
+			sizeof(response));
+	if (rv < 0)
+		return rv;
+
+	printf("%d\n", response.board_version);
+	return rv;
+}
+
+int cmd_boottime(int argc, char *argv[])
+{
+	struct ec_response_get_boot_time response;
+	int rv;
+
+	rv = ec_command(EC_CMD_GET_BOOT_TIME, 0, NULL, 0, &response,
+			sizeof(response));
+	if (rv < 0)
+		return rv;
+
+	printf("arail: %" PRIu64 "\n", response.timestamp[ARAIL]);
+	printf("rsmrst: %" PRIu64 "\n", response.timestamp[RSMRST]);
+	printf("espirst: %" PRIu64 "\n", response.timestamp[ESPIRST]);
+	printf("pltrst_low: %" PRIu64 "\n", response.timestamp[PLTRST_LOW]);
+	printf("pltrst_high: %" PRIu64 "\n", response.timestamp[PLTRST_HIGH]);
+	printf("cnt: %" PRIu16 "\n", response.cnt);
+	printf("ec_cur_time: %" PRIu64 "\n", response.timestamp[EC_CUR_TIME]);
+	return rv;
+}
+
+static void cmd_cbi_help(char *cmd)
+{
+	fprintf(stderr,
+		"  Usage: %s get <tag> [get_flag]\n"
+		"  Usage: %s set <tag> <value/string> <size> [set_flag]\n"
+		"  Usage: %s remove <tag> [set_flag]\n"
+		"    <tag> is one of:\n"
+		"      0: BOARD_VERSION\n"
+		"      1: OEM_ID\n"
+		"      2: SKU_ID\n"
+		"      3: DRAM_PART_NUM (string)\n"
+		"      4: OEM_NAME (string)\n"
+		"      5: MODEL_ID\n"
+		"      6: FW_CONFIG\n"
+		"      7: PCB_VENDOR\n"
+		"      8: SSFC\n"
+		"      9: REWORK_ID\n"
+		"      10: FACTORY_CALIBRATION_DATA\n"
+		"    <size> is the size of the data in byte. It should be zero for\n"
+		"      string types.\n"
+		"    <value/string> is an integer or a string to be set\n"
+		"    [get_flag] is combination of:\n"
+		"      01b: Invalidate cache and reload data from EEPROM\n"
+		"    [set_flag] is combination of:\n"
+		"      01b: Skip write to EEPROM. Use for back-to-back writes\n"
+		"      10b: Set all fields to defaults first\n",
+		cmd, cmd, cmd);
+}
+
+static int cmd_cbi_is_string_field(enum cbi_data_tag tag)
+{
+	return tag == CBI_TAG_DRAM_PART_NUM || tag == CBI_TAG_OEM_NAME ||
+	       tag == CBI_TAG_FUEL_GAUGE_MANUF_NAME ||
+	       tag == CBI_TAG_FUEL_GAUGE_DEVICE_NAME;
+}
+
+/*
+ * Write value to CBI
+ *
+ * TODO: Support asynchronous write
+ */
+static int cmd_cbi(int argc, char *argv[])
+{
+	enum cbi_data_tag tag;
+	char *e;
+	int rv;
+
+	if (argc < 3) {
+		fprintf(stderr, "Invalid number of params\n");
+		cmd_cbi_help(argv[0]);
+		return -1;
+	}
+
+	/* Tag */
+	tag = (enum cbi_data_tag)(strtol(argv[2], &e, 0));
+	if (e && *e) {
+		fprintf(stderr, "Bad tag\n");
+		return -1;
+	}
+
+	if (!strcasecmp(argv[1], "get")) {
+		struct ec_params_get_cbi p = { 0 };
+		int i;
+
+		p.tag = tag;
+		if (argc > 3) {
+			p.flag = strtol(argv[3], &e, 0);
+			if (e && *e) {
+				fprintf(stderr, "Bad flag\n");
+				return -1;
+			}
+		}
+		rv = ec_command(EC_CMD_GET_CROS_BOARD_INFO, 0, &p, sizeof(p),
+				ec_inbuf, ec_max_insize);
+		if (rv < 0) {
+			fprintf(stderr, "Error code: %d\n", rv);
+			return rv;
+		}
+		if (rv < sizeof(uint8_t)) {
+			fprintf(stderr, "Invalid size: %d\n", rv);
+			return -1;
+		}
+		if (cmd_cbi_is_string_field(tag)) {
+			printf("%.*s", rv, (const char *)ec_inbuf);
+		} else {
+			const uint8_t *const buffer =
+				(const uint8_t *const)(ec_inbuf);
+			uint64_t int_value = 0;
+			for (i = 0; i < rv; i++)
+				int_value |= (uint64_t)buffer[i] << (i * 8);
+
+			printf("As uint: %llu (0x%llx)\n",
+			       (unsigned long long)int_value,
+			       (unsigned long long)int_value);
+			printf("As binary:");
+			for (i = 0; i < rv; i++) {
+				if (i % 32 == 31)
+					printf("\n");
+				printf(" %02x", buffer[i]);
+			}
+		}
+		printf("\n");
+		return 0;
+	} else if (!strcasecmp(argv[1], "set")) {
+		struct ec_params_set_cbi *p =
+			(struct ec_params_set_cbi *)ec_outbuf;
+		void *val_ptr;
+		uint64_t val = 0;
+		uint8_t size;
+		uint8_t bad_size = 0;
+		if (argc < 5) {
+			fprintf(stderr, "Invalid number of params\n");
+			cmd_cbi_help(argv[0]);
+			return -1;
+		}
+		memset(p, 0, ec_max_outsize);
+		p->tag = tag;
+
+		if (cmd_cbi_is_string_field(tag)) {
+			val_ptr = argv[3];
+			size = strlen((char *)(val_ptr)) + 1;
+		} else {
+			val = strtoul(argv[3], &e, 0);
+			/* strtoul sets an errno for invalid input. If the value
+			 * read is out of range of representable values by an
+			 * unsigned long int, the function returns ULONG_MAX
+			 * or ULONG_MIN and the errno is set to ERANGE.
+			 */
+			if ((e && *e) || errno == ERANGE) {
+				fprintf(stderr, "Bad value\n");
+				return -1;
+			}
+			size = strtol(argv[4], &e, 0);
+			if (tag == CBI_TAG_REWORK_ID) {
+				if ((e && *e) || size < 1 || size > 8 ||
+				    (size < 8 && val >= (1ull << size * 8)))
+					bad_size = 1;
+			} else {
+				if ((e && *e) || size < 1 || 4 < size ||
+				    val >= (1ull << size * 8))
+					bad_size = 1;
+			}
+			if (bad_size == 1) {
+				fprintf(stderr, "Bad size: %d\n", size);
+				return -1;
+			}
+
+			val_ptr = &val;
+		}
+
+		if (size > ec_max_outsize - sizeof(*p)) {
+			fprintf(stderr, "Size exceeds parameter buffer: %d\n",
+				size);
+			return -1;
+		}
+		/* Little endian */
+		memcpy(p->data, val_ptr, size);
+		p->size = size;
+		if (argc > 5) {
+			p->flag = strtol(argv[5], &e, 0);
+			if (e && *e) {
+				fprintf(stderr, "Bad flag\n");
+				return -1;
+			}
+		}
+		rv = ec_command(EC_CMD_SET_CROS_BOARD_INFO, 0, p,
+				sizeof(*p) + size, NULL, 0);
+		if (rv < 0) {
+			if (rv == -EC_RES_ACCESS_DENIED - EECRESULT)
+				fprintf(stderr,
+					"Write-protect is enabled or "
+					"EC explicitly refused to change the "
+					"requested field.\n");
+			else
+				fprintf(stderr, "Error code: %d\n", rv);
+			return rv;
+		}
+		return 0;
+	} else if (!strcasecmp(argv[1], "remove")) {
+		struct ec_params_set_cbi p = { 0 };
+
+		p.tag = tag;
+		p.size = 0;
+		if (argc > 3) {
+			p.flag = strtol(argv[3], &e, 0);
+			if (e && *e) {
+				fprintf(stderr, "Bad flag\n");
+				return -1;
+			}
+		}
+		rv = ec_command(EC_CMD_SET_CROS_BOARD_INFO, 0, &p, sizeof(p),
+				NULL, 0);
+		if (rv < 0) {
+			if (rv == -EC_RES_ACCESS_DENIED - EECRESULT)
+				fprintf(stderr,
+					"Write-protect is enabled or "
+					"EC explicitly refused to change the "
+					"requested field.\n");
+			else
+				fprintf(stderr, "Error code: %d\n", rv);
+			return rv;
+		}
+		return 0;
+	}
+
+	fprintf(stderr, "Invalid sub command: %s\n", argv[1]);
+	cmd_cbi_help(argv[0]);
+
+	return -1;
+}
+
+int cmd_chipinfo(int argc, char *argv[])
+{
+	struct ec_response_get_chip_info info;
+	int rv;
+
+	printf("Chip info:\n");
+
+	rv = ec_command(EC_CMD_GET_CHIP_INFO, 0, NULL, 0, &info, sizeof(info));
+	if (rv < 0)
+		return rv;
+	printf("  vendor:    %s\n", info.vendor);
+	printf("  name:      %s\n", info.name);
+	printf("  revision:  %s\n", info.revision);
+
+	return 0;
+}
+
+int cmd_proto_info(int argc, char *argv[])
+{
+	struct ec_response_get_protocol_info info;
+	int rv;
+	int i;
+
+	printf("Protocol info:\n");
+
+	rv = ec_command(EC_CMD_GET_PROTOCOL_INFO, 0, NULL, 0, &info,
+			sizeof(info));
+	if (rv < 0) {
+		fprintf(stderr, "Protocol info unavailable.  EC probably only "
+				"supports protocol version 2.\n");
+		return rv;
+	}
+
+	printf("  protocol versions:");
+	for (i = 0; i < 32; i++) {
+		if (info.protocol_versions & BIT(i))
+			printf(" %d", i);
+	}
+	printf("\n");
+
+	printf("  max request:  %4d bytes\n", info.max_request_packet_size);
+	printf("  max response: %4d bytes\n", info.max_response_packet_size);
+	printf("  flags: 0x%08x\n", info.flags);
+	if (info.flags & EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED)
+		printf("    EC_RES_IN_PROGRESS supported\n");
+	return 0;
+}
+
+static int ec_hash_help(const char *cmd)
+{
+	printf("Usage:\n");
+	printf("  %s                        - get last hash\n", cmd);
+	printf("  %s abort                  - abort hashing\n", cmd);
+	printf("  %s start [<offset> <size> [<nonce>]] - start hashing\n", cmd);
+	printf("  %s recalc [<offset> <size> [<nonce>]] - sync rehash\n", cmd);
+	printf("\n"
+	       "If <offset> is RO or RW, offset and size are computed\n"
+	       "automatically for the EC-RO or EC-RW firmware image.\n");
+
+	return 0;
+}
+
+static int ec_hash_print(const struct ec_response_vboot_hash *r)
+{
+	int i;
+
+	if (r->status == EC_VBOOT_HASH_STATUS_BUSY) {
+		printf("status:  busy\n");
+		return 0;
+	} else if (r->status == EC_VBOOT_HASH_STATUS_NONE) {
+		printf("status:  unavailable\n");
+		return 0;
+	} else if (r->status != EC_VBOOT_HASH_STATUS_DONE) {
+		printf("status:  %d\n", r->status);
+		return 0;
+	}
+
+	printf("status:  done\n");
+	if (r->hash_type == EC_VBOOT_HASH_TYPE_SHA256)
+		printf("type:    SHA-256\n");
+	else
+		printf("type:    %d\n", r->hash_type);
+
+	printf("offset:  0x%08x\n", r->offset);
+	printf("size:    0x%08x\n", r->size);
+
+	printf("hash:    ");
+	for (i = 0; i < r->digest_size; i++)
+		printf("%02x", r->hash_digest[i]);
+	printf("\n");
+	return 0;
+}
+
+int cmd_ec_hash(int argc, char *argv[])
+{
+	struct ec_params_vboot_hash p;
+	struct ec_response_vboot_hash r;
+	char *e;
+	int rv;
+
+	memset(&p, 0, sizeof(p));
+	if (argc < 2) {
+		/* Get hash status */
+		p.cmd = EC_VBOOT_HASH_GET;
+		rv = ec_command(EC_CMD_VBOOT_HASH, 0, &p, sizeof(p), &r,
+				sizeof(r));
+		if (rv < 0)
+			return rv;
+
+		return ec_hash_print(&r);
+	}
+
+	if (argc == 2 && !strcasecmp(argv[1], "abort")) {
+		/* Abort hash calculation */
+		p.cmd = EC_VBOOT_HASH_ABORT;
+		rv = ec_command(EC_CMD_VBOOT_HASH, 0, &p, sizeof(p), &r,
+				sizeof(r));
+		return (rv < 0 ? rv : 0);
+	}
+
+	/* The only other commands are start and recalc */
+	if (!strcasecmp(argv[1], "start"))
+		p.cmd = EC_VBOOT_HASH_START;
+	else if (!strcasecmp(argv[1], "recalc"))
+		p.cmd = EC_VBOOT_HASH_RECALC;
+	else
+		return ec_hash_help(argv[0]);
+
+	p.hash_type = EC_VBOOT_HASH_TYPE_SHA256;
+
+	if (argc < 3) {
+		fprintf(stderr, "Must specify offset\n");
+		return -1;
+	}
+
+	if (!strcasecmp(argv[2], "ro")) {
+		p.offset = EC_VBOOT_HASH_OFFSET_RO;
+		p.size = 0;
+		printf("Hashing EC-RO...\n");
+	} else if (!strcasecmp(argv[2], "rw")) {
+		p.offset = EC_VBOOT_HASH_OFFSET_ACTIVE;
+		p.size = 0;
+		printf("Hashing EC-RW...\n");
+	} else if (argc < 4) {
+		fprintf(stderr, "Must specify size\n");
+		return -1;
+	} else {
+		p.offset = strtol(argv[2], &e, 0);
+		if (e && *e) {
+			fprintf(stderr, "Bad offset.\n");
+			return -1;
+		}
+		p.size = strtol(argv[3], &e, 0);
+		if (e && *e) {
+			fprintf(stderr, "Bad size.\n");
+			return -1;
+		}
+		printf("Hashing %d bytes at offset %d...\n", p.size, p.offset);
+	}
+
+	if (argc == 5) {
+		/*
+		 * Technically nonce can be any binary data up to 64 bytes,
+		 * but this command only supports a 32-bit value.
+		 */
+		uint32_t nonce = strtol(argv[4], &e, 0);
+		if (e && *e) {
+			fprintf(stderr, "Bad nonce integer.\n");
+			return -1;
+		}
+		memcpy(p.nonce_data, &nonce, sizeof(nonce));
+		p.nonce_size = sizeof(nonce);
+	} else
+		p.nonce_size = 0;
+
+	rv = ec_command(EC_CMD_VBOOT_HASH, 0, &p, sizeof(p), &r, sizeof(r));
+	if (rv < 0)
+		return rv;
+
+	/* Start command doesn't wait for hashing to finish */
+	if (p.cmd == EC_VBOOT_HASH_START)
+		return 0;
+
+	/* Recalc command does wait around, so a result is ready now */
+	return ec_hash_print(&r);
+}
+
+int cmd_rtc_get(int argc, char *argv[])
+{
+	struct ec_response_rtc r;
+	int rv;
+
+	rv = ec_command(EC_CMD_RTC_GET_VALUE, 0, NULL, 0, &r, sizeof(r));
+	if (rv < 0)
+		return rv;
+
+	printf("Current time: 0x%08x (%d)\n", r.time, r.time);
+	return 0;
+}
+
+int cmd_rtc_set(int argc, char *argv[])
+{
+	struct ec_params_rtc p;
+	char *e;
+	int rv;
+
+	if (argc != 2) {
+		fprintf(stderr, "Usage: %s <time>\n", argv[0]);
+		return -1;
+	}
+	p.time = strtol(argv[1], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad time.\n");
+		return -1;
+	}
+
+	rv = ec_command(EC_CMD_RTC_SET_VALUE, 0, &p, sizeof(p), NULL, 0);
+	if (rv < 0)
+		return rv;
+
+	printf("Time set.\n");
+	return 0;
+}
+
+int cmd_rtc_set_alarm(int argc, char *argv[])
+{
+	struct ec_params_rtc p;
+	char *e;
+	int rv;
+
+	if (argc != 2) {
+		fprintf(stderr, "Usage: %s <sec>\n", argv[0]);
+		return -1;
+	}
+	p.time = strtol(argv[1], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad time.\n");
+		return -1;
+	}
+
+	rv = ec_command(EC_CMD_RTC_SET_ALARM, 0, &p, sizeof(p), NULL, 0);
+	if (rv < 0)
+		return rv;
+
+	if (p.time == 0)
+		printf("Disabling alarm.\n");
+	else
+		printf("Alarm set to go off in %d secs.\n", p.time);
+	return 0;
+}
+
+int cmd_rtc_get_alarm(int argc, char *argv[])
+{
+	struct ec_response_rtc r;
+	int rv;
+
+	rv = ec_command(EC_CMD_RTC_GET_ALARM, 0, NULL, 0, &r, sizeof(r));
+	if (rv < 0)
+		return rv;
+
+	if (r.time == 0)
+		printf("Alarm not set\n");
+	else
+		printf("Alarm to go off in %d secs\n", r.time);
+	return 0;
+}
+
+int cmd_console(int argc, char *argv[])
+{
+	char *out = (char *)ec_inbuf;
+	int rv;
+
+	/* Snapshot the EC console */
+	rv = ec_command(EC_CMD_CONSOLE_SNAPSHOT, 0, NULL, 0, NULL, 0);
+	if (rv < 0)
+		return rv;
+
+	/* Loop and read from the snapshot until it's done */
+	while (1) {
+		rv = ec_command(EC_CMD_CONSOLE_READ, 0, NULL, 0, ec_inbuf,
+				ec_max_insize);
+		if (rv < 0)
+			return rv;
+
+		/* Empty response means done */
+		if (!rv || !*out)
+			break;
+
+		/* Make sure output is null-terminated, then dump it */
+		out[ec_max_insize - 1] = '\0';
+		fputs(out, stdout);
+	}
+	printf("\n");
+	return 0;
+}
+struct param_info {
+	const char *name; /* name of this parameter */
+	const char *help; /* help message */
+	int size; /* size in bytes */
+	int offset; /* offset within structure */
+};
+
+#define FIELD(fname, field, help_str)                                       \
+	{                                                                   \
+		.name = fname, .help = help_str,                            \
+		.size = sizeof(((struct ec_mkbp_config *)NULL)->field),     \
+		.offset = __builtin_offsetof(struct ec_mkbp_config, field), \
+	}
+
+static const struct param_info keyconfig_params[] = {
+	FIELD("scan_period", scan_period_us, "period between scans"),
+	FIELD("poll_timeout", poll_timeout_us,
+	      "revert to irq mode after no activity for this long"),
+	FIELD("min_post_scan_delay", min_post_scan_delay_us,
+	      "minimum post-scan delay before starting a new scan"),
+	FIELD("output_settle", output_settle_us,
+	      "delay to wait for output to settle"),
+	FIELD("debounce_down", debounce_down_us,
+	      "time for debounce on key down"),
+	FIELD("debounce_up", debounce_up_us, "time for debounce on key up"),
+	FIELD("fifo_max_depth", fifo_max_depth,
+	      "maximum depth to allow for fifo (0 = disable)"),
+	FIELD("flags", flags, "0 to disable scanning, 1 to enable"),
+};
+
+static const struct param_info *find_field(const struct param_info *params,
+					   int count, const char *name,
+					   unsigned int *nump)
+{
+	const struct param_info *param;
+	int i;
+
+	for (i = 0, param = params; i < count; i++, param++) {
+		if (0 == strcmp(param->name, name)) {
+			if (nump)
+				*nump = i;
+			return param;
+		}
+	}
+
+	fprintf(stderr, "Unknown parameter '%s'\n", name);
+	return NULL;
+}
+
+static int get_value(const struct param_info *param, const char *config)
+{
+	const char *field;
+
+	field = config + param->offset;
+	switch (param->size) {
+	case 1:
+		return *(uint8_t *)field;
+	case 2:
+		return *(uint16_t *)field;
+	case 4:
+		return *(uint32_t *)field;
+	default:
+		fprintf(stderr, "Internal error: unknown size %d\n",
+			param->size);
+	}
+
+	return -1;
+}
+
+static int show_fields(struct ec_mkbp_config *config, int argc, char *argv[])
+{
+	const struct param_info *param;
+	uint32_t mask;
+	int i;
+
+	if (!argc) {
+		mask = -1U; /* show all fields */
+	} else {
+		mask = 0;
+		while (argc > 0) {
+			unsigned int num;
+
+			param = find_field(keyconfig_params,
+					   ARRAY_SIZE(keyconfig_params),
+					   argv[0], &num);
+			if (!param)
+				return -1;
+			mask |= 1 << num;
+			argc--;
+			argv++;
+		}
+	}
+
+	param = keyconfig_params;
+	for (i = 0; i < ARRAY_SIZE(keyconfig_params); i++, param++) {
+		if (mask & BIT(i)) {
+			fprintf(stderr, "%-12s   %u\n", param->name,
+				get_value(param, (char *)config));
+		}
+	}
+
+	return 0;
+}
+
+static int cmd_kbinfo(int argc, char *argv[])
+{
+	struct ec_params_mkbp_info info = {
+		.info_type = EC_MKBP_INFO_KBD,
+	};
+	struct ec_response_mkbp_info resp;
+	int rv;
+
+	if (argc > 1) {
+		fprintf(stderr, "Too many args\n");
+		return -1;
+	}
+	rv = ec_command(EC_CMD_MKBP_INFO, 0, &info, sizeof(info), &resp,
+			sizeof(resp));
+	if (rv < 0)
+		return rv;
+
+	printf("Matrix rows: %d\n", resp.rows);
+	printf("Matrix columns: %d\n", resp.cols);
+
+	return 0;
+}
+
+static int cmd_keyconfig(int argc, char *argv[])
+{
+	struct ec_params_mkbp_set_config req;
+	int cmd;
+	int rv;
+
+	if (argc < 2) {
+		const struct param_info *param;
+		int i;
+
+		fprintf(stderr,
+			"Usage: %s get [<param>] - print params\n"
+			"\t%s set [<param>> <value>]\n"
+			"   Available params are: (all time values are in us)",
+			argv[0], argv[0]);
+
+		param = keyconfig_params;
+		for (i = 0; i < ARRAY_SIZE(keyconfig_params); i++, param++) {
+			fprintf(stderr, "%-12s   %s\n", param->name,
+				param->name);
+		}
+		return -1;
+	}
+
+	/* Get the command */
+	if (0 == strcmp(argv[1], "get")) {
+		cmd = EC_CMD_MKBP_GET_CONFIG;
+	} else if (0 == strcmp(argv[1], "set")) {
+		cmd = EC_CMD_MKBP_SET_CONFIG;
+	} else {
+		fprintf(stderr, "Invalid command '%s\n", argv[1]);
+		return -1;
+	}
+
+	switch (cmd) {
+	case EC_CMD_MKBP_GET_CONFIG:
+		/* Read the existing config */
+		rv = ec_command(cmd, 0, NULL, 0, &req, sizeof(req));
+		if (rv < 0)
+			return rv;
+		show_fields(&req.config, argc - 2, argv + 2);
+		break;
+	}
+
+	return 0;
+}
+
+static void cmd_memory_dump_usage(const char *command_name)
+{
+	fprintf(stderr,
+		"Usage: %s [<address> [<size>]]\n"
+		"  Prints the memory available for dumping in hexdump cononical format.\n"
+		"  <address> is a 32-bit address offset. Defaults to 0x0.\n"
+		"  <size> is the number of bytes to print after <address>."
+		" Defaults to end of RAM.\n"
+		"Usage: %s info\n"
+		"  Prints metadata about the memory available for dumping\n",
+		command_name, command_name);
+}
+
+static int cmd_memory_dump(int argc, char *argv[])
+{
+	int rv;
+	char *e;
+	bool just_info;
+	int response_max;
+	const char *command_name = argv[0];
+	void *read_mem_response = NULL;
+	uint32_t requested_address_start = 0;
+	uint32_t requested_address_end = UINT32_MAX;
+	/* Simple local structs for storing a memory dump */
+	struct mem_segment {
+		uint32_t addr_start;
+		uint32_t addr_end;
+		uint32_t size;
+		uint8_t *mem;
+		struct mem_segment *next;
+	};
+	uint16_t entry_count;
+	struct mem_segment *segments = NULL;
+	/* The real root is root.next, all other root fields are unused */
+	struct mem_segment root;
+	struct mem_segment *seg;
+	struct ec_response_memory_dump_get_metadata metadata_response;
+	struct ec_response_get_protocol_info protocol_info_response;
+
+	if (argc > 3 || (argc == 2 && strcmp(argv[1], "help") == 0)) {
+		cmd_memory_dump_usage(command_name);
+		return -1;
+	}
+	if (argc == 2 && strcmp(argv[1], "info") == 0) {
+		just_info = true;
+	}
+	if (argc >= 2 && !just_info) {
+		/* Parse requested address argument */
+		requested_address_start = strtoul(argv[1], &e, 0);
+		if (e && *e) {
+			fprintf(stderr, "Bad argument '%s'\n", argv[1]);
+			cmd_memory_dump_usage(command_name);
+			return -1;
+		}
+	}
+	if (argc == 3 && !just_info) {
+		/* Parse requested size argument */
+		uint32_t requested_size = strtoul(argv[2], &e, 0);
+		if (e && *e) {
+			fprintf(stderr, "Bad argument '%s'\n", argv[2]);
+			cmd_memory_dump_usage(command_name);
+			return -1;
+		}
+		/* Cap max address at UINT32_MAX */
+		requested_address_end =
+			MIN((uint64_t)requested_address_start + requested_size,
+			    (uint64_t)UINT32_MAX);
+	}
+
+	rv = ec_command(EC_CMD_GET_PROTOCOL_INFO, 0, NULL, 0,
+			&protocol_info_response,
+			sizeof(protocol_info_response));
+	if (rv < 0) {
+		fprintf(stderr, "Protocol info unavailable.\n");
+		goto cmd_memory_dump_cleanup;
+	}
+	response_max = protocol_info_response.max_response_packet_size;
+	read_mem_response = malloc(response_max);
+
+	/* Fetch memory dump metadata */
+	rv = ec_command(EC_CMD_MEMORY_DUMP_GET_METADATA, 0, NULL, 0,
+			&metadata_response, sizeof(metadata_response));
+	if (rv < 0) {
+		fprintf(stderr, "Failed to get memory dump metadata.\n");
+		goto cmd_memory_dump_cleanup;
+	}
+	entry_count = metadata_response.memory_dump_entry_count;
+	if (entry_count == 0) {
+		fprintf(stderr, "Memory dump is empty.\n");
+		rv = -1;
+		goto cmd_memory_dump_cleanup;
+	}
+	segments = (struct mem_segment *)malloc(sizeof(struct mem_segment) *
+						entry_count);
+	if (segments == NULL) {
+		fprintf(stderr, "malloc failed\n");
+		rv = -1;
+		goto cmd_memory_dump_cleanup;
+	}
+
+	/* Fetch all memory segments */
+	for (uint16_t entry_index = 0; entry_index < entry_count;
+	     entry_index++) {
+		seg = &segments[entry_index];
+		struct ec_params_memory_dump_get_entry_info entry_info_params = {
+			.memory_dump_entry_index = entry_index
+		};
+		struct ec_response_memory_dump_get_entry_info
+			entry_info_response;
+
+		rv = ec_command(EC_CMD_MEMORY_DUMP_GET_ENTRY_INFO, 0,
+				&entry_info_params, sizeof(entry_info_params),
+				&entry_info_response,
+				sizeof(entry_info_response));
+		if (rv < 0) {
+			fprintf(stderr,
+				"Failed to get memory dump info for entry %d.\n",
+				entry_index);
+			goto cmd_memory_dump_cleanup;
+		}
+
+		uint32_t entry_address_end =
+			entry_info_response.address + entry_info_response.size;
+
+		/* Check if entry is even in bounds of the requested range */
+		if (entry_info_response.address >= requested_address_end ||
+		    entry_address_end <= requested_address_start)
+			continue;
+
+		/* Clip memory segment boundaries based on requested range */
+		seg->addr_start = MAX(entry_info_response.address,
+				      requested_address_start);
+		seg->addr_end = MIN(entry_address_end, requested_address_end);
+		if (seg->addr_end - seg->addr_start <= 0)
+			continue;
+		seg->size = seg->addr_end - seg->addr_start;
+
+		if (just_info) {
+			printf("%-3d: %x-%x (%d bytes)\n", entry_index,
+			       seg->addr_start, seg->addr_end, seg->size);
+			continue;
+		}
+
+		seg->mem = (uint8_t *)malloc(seg->size);
+		if (seg->mem == NULL) {
+			fprintf(stderr, "malloc failed\n");
+			rv = -1;
+			goto cmd_memory_dump_cleanup;
+		}
+
+		/* Keep fetching until entire segment is copied */
+		uint32_t offset = 0;
+		while (offset < seg->size) {
+			struct ec_params_memory_dump_read_memory
+				read_mem_params = {
+					.memory_dump_entry_index = entry_index,
+					.address = seg->addr_start + offset,
+					.size = seg->size - offset,
+				};
+
+			rv = ec_command(EC_CMD_MEMORY_DUMP_READ_MEMORY, 0,
+					&read_mem_params,
+					sizeof(read_mem_params),
+					read_mem_response, response_max);
+			if (rv <= 0) {
+				fprintf(stderr,
+					"Failed to read memory at %x.\n",
+					read_mem_params.address);
+				rv = -1;
+				goto cmd_memory_dump_cleanup;
+			}
+
+			if (!memcpy(seg->mem + offset, read_mem_response, rv)) {
+				fprintf(stderr, "memcpy failed\n");
+				rv = -1;
+				goto cmd_memory_dump_cleanup;
+			}
+
+			offset += rv;
+		};
+
+		/* Sort segments in ascending order of starting address */
+		struct mem_segment *current = &root;
+		for (int i = 0; current->next && i < entry_count; i++) {
+			if (seg->addr_start < current->next->addr_start) {
+				/* Insert segment before current->next */
+				seg->next = current->next;
+				current->next = seg;
+				break;
+			}
+			current = current->next;
+		}
+		current->next = seg;
+	}
+
+	if (just_info) {
+		rv = 0;
+		goto cmd_memory_dump_cleanup;
+	}
+
+	/* Merge overlapping or touching segments */
+	seg = root.next;
+	for (int i = 0; seg && seg->next && i < entry_count; i++) {
+		if (seg->addr_end < seg->next->addr_start) {
+			/* No overlap */
+			seg = seg->next;
+			continue;
+		}
+		uint32_t overlap = seg->addr_end - seg->next->addr_start;
+		uint32_t new_size = seg->size + seg->next->size - overlap;
+		if (new_size != seg->next->addr_end - seg->addr_start) {
+			fprintf(stderr, "Segment size is not aligned\n");
+			rv = -1;
+			goto cmd_memory_dump_cleanup;
+		}
+		seg->mem = (uint8_t *)realloc(seg->mem, new_size);
+		if (seg->mem == NULL) {
+			fprintf(stderr, "realloc failed\n");
+			rv = -1;
+			goto cmd_memory_dump_cleanup;
+		}
+		if (!memcpy(seg->mem + seg->size, seg->next->mem + overlap,
+			    seg->next->size - overlap)) {
+			fprintf(stderr, "Merging segments failed\n");
+			rv = -1;
+			goto cmd_memory_dump_cleanup;
+		}
+		seg->addr_end = seg->next->addr_end;
+		seg->size = new_size;
+		seg->next = seg->next->next;
+	}
+
+	/* Print dump in hexdump cononical format */
+	seg = root.next;
+	for (int i = 0; seg && i < entry_count; i++) {
+		hexdump_canonical(seg->mem, seg->size, seg->addr_start);
+		/* Extra newline to delinate segments */
+		printf("\n");
+		seg = seg->next;
+	}
+	rv = 0;
+cmd_memory_dump_cleanup:
+	free(read_mem_response);
+	if (segments) {
+		for (int i = 0; i < entry_count; i++)
+			free(segments[i].mem);
+		free(segments);
+	}
+	return rv;
+}
+
+static const char *const mkbp_button_strings[] = {
+	[EC_MKBP_POWER_BUTTON] = "Power",
+	[EC_MKBP_VOL_UP] = "Volume up",
+	[EC_MKBP_VOL_DOWN] = "Volume down",
+	[EC_MKBP_RECOVERY] = "Recovery",
+};
+
+static const char *const mkbp_switch_strings[] = {
+	[EC_MKBP_LID_OPEN] = "Lid open",
+	[EC_MKBP_TABLET_MODE] = "Tablet mode",
+	[EC_MKBP_BASE_ATTACHED] = "Base attached",
+};
+
+static int cmd_mkbp_get(int argc, char *argv[])
+{
+	struct ec_params_mkbp_info p;
+	union ec_response_get_next_data r;
+	int rv;
+	int i;
+	uint32_t supported;
+
+	if (argc < 2) {
+		fprintf(stderr, "Usage: %s <buttons|switches>\n", argv[0]);
+		return -1;
+	}
+
+	if (strncmp(argv[1], "button", 6) == 0) {
+		p.event_type = EC_MKBP_EVENT_BUTTON;
+	} else if (strncmp(argv[1], "switch", 6) == 0) {
+		p.event_type = EC_MKBP_EVENT_SWITCH;
+	} else {
+		fprintf(stderr, "Invalid param: '%s'\n", argv[1]);
+		return -1;
+	}
+
+	p.info_type = EC_MKBP_INFO_SUPPORTED;
+	rv = ec_command(EC_CMD_MKBP_INFO, 0, &p, sizeof(p), &r, sizeof(r));
+	if (rv < 0)
+		return rv;
+	if (p.event_type == EC_MKBP_EVENT_BUTTON)
+		supported = r.buttons;
+	else if (p.event_type == EC_MKBP_EVENT_SWITCH)
+		supported = r.switches;
+	else
+		return -1;
+
+	p.info_type = EC_MKBP_INFO_CURRENT;
+	rv = ec_command(EC_CMD_MKBP_INFO, 0, &p, sizeof(p), &r, sizeof(r));
+	if (rv < 0)
+		return rv;
+
+	if (p.event_type == EC_MKBP_EVENT_BUTTON) {
+		printf("MKBP buttons state: 0x%04x (supported: 0x%04x)\n",
+		       r.buttons, supported);
+		for (i = 0; i < ARRAY_SIZE(mkbp_button_strings); i++) {
+			if (supported & BIT(i) && mkbp_button_strings[i]) {
+				printf("%s: %s\n", mkbp_button_strings[i],
+				       r.buttons & BIT(i) ? "ON" : "OFF");
+				supported &= ~BIT(i);
+			}
+		}
+		if (supported)
+			printf("Unknown buttons: 0x%04x\n", supported);
+	} else if (p.event_type == EC_MKBP_EVENT_SWITCH) {
+		printf("MKBP switches state: 0x%04x (supported: 0x%04x)\n",
+		       r.switches, supported);
+		for (i = 0; i < ARRAY_SIZE(mkbp_switch_strings); i++) {
+			if (supported & BIT(i) && mkbp_switch_strings[i]) {
+				printf("%s: %s\n", mkbp_switch_strings[i],
+				       r.switches & BIT(i) ? "ON" : "OFF");
+				supported &= ~BIT(i);
+			}
+		}
+		if (supported)
+			printf("Unknown switches: 0x%04x\n", supported);
+	}
+
+	return 0;
+}
+
+static int cmd_mkbp_wake_mask(int argc, char *argv[])
+{
+	struct ec_params_mkbp_event_wake_mask p;
+	struct ec_response_mkbp_event_wake_mask r;
+	int rv;
+
+	if (argc < 3) {
+		fprintf(stderr,
+			"Usage: %s get <event|hostevent>\n"
+			"\t%s set <event|hostevent> <mask>\n",
+			argv[0], argv[0]);
+		return -1;
+	}
+
+	/* Determine if the user want to get or set the wake mask. */
+	if (strncmp(argv[1], "get", 3) == 0) {
+		p.action = GET_WAKE_MASK;
+	} else if (strncmp(argv[1], "set", 3) == 0) {
+		p.action = SET_WAKE_MASK;
+	} else {
+		fprintf(stderr, "Invalid param: '%s'\n", argv[1]);
+		return -1;
+	}
+
+	/* Determine which mask is of interest. */
+	if (strncmp(argv[2], "event", 5) == 0) {
+		p.mask_type = EC_MKBP_EVENT_WAKE_MASK;
+	} else if (strncmp(argv[2], "hostevent", 9) == 0) {
+		p.mask_type = EC_MKBP_HOST_EVENT_WAKE_MASK;
+	} else {
+		fprintf(stderr, "Invalid param: '%s'\n", argv[2]);
+		return -1;
+	}
+
+	if (p.action == SET_WAKE_MASK) {
+		char *e;
+
+		if (argc < 4) {
+			fprintf(stderr, "Missing mask value!");
+			return -1;
+		}
+
+		p.new_wake_mask = strtol(argv[3], &e, 0);
+		if (e && *e) {
+			fprintf(stderr, "Bad mask: '%s'", argv[1]);
+			return -1;
+		}
+	}
+
+	rv = ec_command(EC_CMD_MKBP_WAKE_MASK, 0, &p, sizeof(p), &r, sizeof(r));
+	if (rv < 0) {
+		if (rv == -EECRESULT - EC_RES_INVALID_PARAM) {
+			fprintf(stderr,
+				"Unknown mask, or mask is not in use.  "
+				"You may need to enable the "
+				"CONFIG_MKBP_%s_WAKEUP_MASK option in the EC.\n",
+				p.mask_type == EC_MKBP_EVENT_WAKE_MASK ?
+					"EVENT" :
+					"HOSTEVENT");
+		}
+		return rv;
+	}
+
+	if (p.action == GET_WAKE_MASK)
+		printf("MBKP %s wake mask: 0x%08x\n", argv[2], r.wake_mask);
+	else if (p.action == SET_WAKE_MASK)
+		printf("MKBP %s wake mask set.\n", argv[2]);
+
+	return 0;
+}
+
+/* Index is already checked. argv[0] is first param value */
+static int cmd_tmp006cal_v0(int idx, int argc, char *argv[])
+{
+	struct ec_params_tmp006_get_calibration pg;
+	struct ec_response_tmp006_get_calibration_v0 rg;
+	struct ec_params_tmp006_set_calibration_v0 ps;
+	float val;
+	char *e;
+	int i, rv;
+
+	/* Get current values */
+	pg.index = idx;
+	rv = ec_command(EC_CMD_TMP006_GET_CALIBRATION, 0, &pg, sizeof(pg), &rg,
+			sizeof(rg));
+	if (rv < 0)
+		return rv;
+
+	if (!argc) {
+		/* If no new values are given, just print what we have */
+		printf("S0: %e\n", rg.s0);
+		printf("b0: %e\n", rg.b0);
+		printf("b1: %e\n", rg.b1);
+		printf("b2: %e\n", rg.b2);
+		return EC_SUCCESS;
+	}
+
+	/* Prepare to reuse the current values */
+	memset(&ps, 0, sizeof(ps));
+	ps.index = idx;
+	ps.s0 = rg.s0;
+	ps.b0 = rg.b0;
+	ps.b1 = rg.b1;
+	ps.b2 = rg.b2;
+
+	/* Parse up to four args, skipping any that are just "-" */
+	for (i = 0; i < argc && i < 4; i++) {
+		if (!strcmp(argv[i], "-"))
+			continue;
+		val = strtod(argv[i], &e);
+		if (e && *e) {
+			fprintf(stderr,
+				"Bad arg \"%s\". Use \"-\" to skip a param.\n",
+				argv[i]);
+			return -1;
+		}
+		switch (i) {
+		case 0:
+			ps.s0 = val;
+			break;
+		case 1:
+			ps.b0 = val;
+			break;
+		case 2:
+			ps.b1 = val;
+			break;
+		case 3:
+			ps.b2 = val;
+			break;
+		}
+	}
+
+	/* Set 'em */
+	return ec_command(EC_CMD_TMP006_SET_CALIBRATION, 0, &ps, sizeof(ps),
+			  NULL, 0);
+}
+
+/* Index is already checked. argv[0] is first param value */
+static int cmd_tmp006cal_v1(int idx, int argc, char *argv[])
+{
+	struct ec_params_tmp006_get_calibration pg;
+	struct ec_response_tmp006_get_calibration_v1 *rg =
+		(struct ec_response_tmp006_get_calibration_v1 *)(ec_inbuf);
+	struct ec_params_tmp006_set_calibration_v1 *ps =
+		(struct ec_params_tmp006_set_calibration_v1 *)(ec_outbuf);
+	float val;
+	char *e;
+	int i, rv, cmdsize;
+
+	/* Algorithm 1 parameter names */
+	static const char *const alg1_pname[] = {
+		"s0", "a1", "a2", "b0", "b1", "b2",
+		"c2", "d0", "d1", "ds", "e0", "e1",
+	};
+
+	/* Get current values */
+	pg.index = idx;
+	rv = ec_command(EC_CMD_TMP006_GET_CALIBRATION, 1, &pg, sizeof(pg), rg,
+			ec_max_insize);
+	if (rv < 0)
+		return rv;
+
+	if (!argc) {
+		/* If no new values are given, just print what we have */
+		printf("algorithm:  %d\n", rg->algorithm);
+		printf("params:\n");
+		/* We only know about alg 1 at the moment */
+		if (rg->algorithm == 1)
+			for (i = 0; i < rg->num_params; i++)
+				printf("  %s  %e\n", alg1_pname[i], rg->val[i]);
+		else
+			for (i = 0; i < rg->num_params; i++)
+				printf("  param%d  %e\n", i, rg->val[i]);
+		return EC_SUCCESS;
+	}
+
+	/* Prepare to reuse the current values */
+	memset(ps, 0, ec_max_outsize);
+	ps->index = idx;
+	ps->algorithm = rg->algorithm;
+	ps->num_params = rg->num_params;
+	for (i = 0; i < rg->num_params; i++)
+		ps->val[i] = rg->val[i];
+
+	/* Parse the args, skipping any that are just "-" */
+	for (i = 0; i < argc && i < rg->num_params; i++) {
+		if (!strcmp(argv[i], "-"))
+			continue;
+		val = strtod(argv[i], &e);
+		if (e && *e) {
+			fprintf(stderr,
+				"Bad arg \"%s\". Use \"-\" to skip a param.\n",
+				argv[i]);
+			return -1;
+		}
+		ps->val[i] = val;
+	}
+
+	/* Set 'em */
+	cmdsize = sizeof(*ps) + ps->num_params * sizeof(ps->val[0]);
+	return ec_command(EC_CMD_TMP006_SET_CALIBRATION, 1, ps, cmdsize, NULL,
+			  0);
+}
+
+int cmd_tmp006cal(int argc, char *argv[])
+{
+	char *e;
+	int idx;
+
+	if (argc < 2) {
+		fprintf(stderr, "Must specify tmp006 index.\n");
+		return -1;
+	}
+
+	idx = strtol(argv[1], &e, 0);
+	if ((e && *e) || idx < 0 || idx > 255) {
+		fprintf(stderr, "Bad index.\n");
+		return -1;
+	}
+
+	/* Pass just the params (if any) to the helper function */
+	argc -= 2;
+	argv += 2;
+
+	if (ec_cmd_version_supported(EC_CMD_TMP006_GET_CALIBRATION, 1))
+		return cmd_tmp006cal_v1(idx, argc, argv);
+
+	if (ec_cmd_version_supported(EC_CMD_TMP006_GET_CALIBRATION, 0))
+		return cmd_tmp006cal_v0(idx, argc, argv);
+
+	printf("The EC is being stupid\n");
+	return -1;
+}
+
+int cmd_tmp006raw(int argc, char *argv[])
+{
+	struct ec_params_tmp006_get_raw p;
+	struct ec_response_tmp006_get_raw r;
+	char *e;
+	int idx;
+	int rv;
+
+	if (argc != 2) {
+		fprintf(stderr, "Must specify tmp006 index.\n");
+		return -1;
+	}
+
+	idx = strtol(argv[1], &e, 0);
+	if ((e && *e) || idx < 0 || idx > 255) {
+		fprintf(stderr, "Bad index.\n");
+		return -1;
+	}
+
+	p.index = idx;
+
+	rv = ec_command(EC_CMD_TMP006_GET_RAW, 0, &p, sizeof(p), &r, sizeof(r));
+	if (rv < 0)
+		return rv;
+
+	printf("T: %d.%02d K\n", r.t / 100, r.t % 100);
+	printf("V: %d nV\n", r.v);
+	return EC_SUCCESS;
+}
+
+static int cmd_hang_detect(int argc, char *argv[])
+{
+	struct ec_params_hang_detect req;
+	char *e;
+
+	memset(&req, 0, sizeof(req));
+
+	if (argc == 2 && !strcasecmp(argv[1], "stop")) {
+		req.flags = EC_HANG_STOP_NOW;
+		return ec_command(EC_CMD_HANG_DETECT, 0, &req, sizeof(req),
+				  NULL, 0);
+	}
+
+	if (argc == 2 && !strcasecmp(argv[1], "start")) {
+		req.flags = EC_HANG_START_NOW;
+		return ec_command(EC_CMD_HANG_DETECT, 0, &req, sizeof(req),
+				  NULL, 0);
+	}
+
+	if (argc == 4) {
+		req.flags = strtol(argv[1], &e, 0);
+		if (e && *e) {
+			fprintf(stderr, "Bad flags.\n");
+			return -1;
+		}
+
+		req.host_event_timeout_msec = strtol(argv[2], &e, 0);
+		if (e && *e) {
+			fprintf(stderr, "Bad event timeout.\n");
+			return -1;
+		}
+
+		req.warm_reboot_timeout_msec = strtol(argv[3], &e, 0);
+		if (e && *e) {
+			fprintf(stderr, "Bad reboot timeout.\n");
+			return -1;
+		}
+
+		printf("hang flags=0x%x\n"
+		       "event_timeout=%d ms\n"
+		       "reboot_timeout=%d ms\n",
+		       req.flags, req.host_event_timeout_msec,
+		       req.warm_reboot_timeout_msec);
+
+		return ec_command(EC_CMD_HANG_DETECT, 0, &req, sizeof(req),
+				  NULL, 0);
+	}
+
+	fprintf(stderr,
+		"Must specify start/stop or <flags> <event_ms> <reboot_ms>\n");
+	return -1;
+}
+
+enum port_80_event {
+	PORT_80_EVENT_RESUME = 0x1001, /* S3->S0 transition */
+	PORT_80_EVENT_RESET = 0x1002, /* RESET transition */
+};
+
+int cmd_port80_read(int argc, char *argv[])
+{
+	struct ec_params_port80_read p;
+	int cmdver = 1, rv;
+	int i, head, tail;
+	uint16_t *history;
+	uint32_t writes, history_size;
+	struct ec_response_port80_read rsp;
+	int printed = 0;
+
+	if (!ec_cmd_version_supported(EC_CMD_PORT80_READ, cmdver)) {
+		/* fall back to last boot */
+		struct ec_response_port80_last_boot r;
+		rv = ec_command(EC_CMD_PORT80_LAST_BOOT, 0, NULL, 0, &r,
+				sizeof(r));
+		fprintf(stderr, "Last boot %2x\n", r.code);
+		printf("done.\n");
+		return 0;
+	}
+
+	/* read writes and history_size */
+	p.subcmd = EC_PORT80_GET_INFO;
+	rv = ec_command(EC_CMD_PORT80_READ, cmdver, &p, sizeof(p), &rsp,
+			sizeof(rsp));
+	if (rv < 0) {
+		fprintf(stderr, "Read error at writes\n");
+		return rv;
+	}
+	writes = rsp.get_info.writes;
+	history_size = rsp.get_info.history_size;
+
+	history = (uint16_t *)(malloc(history_size * sizeof(uint16_t)));
+	if (!history) {
+		fprintf(stderr, "Unable to allocate buffer.\n");
+		return -1;
+	}
+	/* As the history buffer is quite large, we read data in chunks, with
+	    size in bytes of EC_PORT80_SIZE_MAX in each chunk.
+	    Incrementing offset until all history buffer has been read. To
+	    simplify the design, chose HISTORY_LEN is always multiple of
+	    EC_PORT80_SIZE_MAX.
+
+	    offset: entry offset from the beginning of history buffer.
+	    num_entries: number of entries requested.
+	*/
+	p.subcmd = EC_PORT80_READ_BUFFER;
+	for (i = 0; i < history_size; i += EC_PORT80_SIZE_MAX) {
+		p.read_buffer.offset = i;
+		p.read_buffer.num_entries = EC_PORT80_SIZE_MAX;
+		rv = ec_command(EC_CMD_PORT80_READ, cmdver, &p, sizeof(p), &rsp,
+				sizeof(rsp));
+		if (rv < 0) {
+			fprintf(stderr, "Read error at offset %d\n", i);
+			free(history);
+			return rv;
+		}
+		memcpy((void *)(history + i), rsp.data.codes,
+		       EC_PORT80_SIZE_MAX * sizeof(uint16_t));
+	}
+
+	head = writes;
+	if (head > history_size)
+		tail = head - history_size;
+	else
+		tail = 0;
+
+	fprintf(stderr, "Port 80 writes");
+	for (i = tail; i < head; i++) {
+		int e = history[i % history_size];
+		switch (e) {
+		case PORT_80_EVENT_RESUME:
+			fprintf(stderr, "\n(S3->S0)");
+			printed = 0;
+			break;
+		case PORT_80_EVENT_RESET:
+			fprintf(stderr, "\n(RESET)");
+			printed = 0;
+			break;
+		default:
+			if (!(printed++ % 20))
+				fprintf(stderr, "\n ");
+			fprintf(stderr, " %02x", e);
+		}
+	}
+	fprintf(stderr, " <--new\n");
+
+	free(history);
+	printf("done.\n");
+	return 0;
+}
+
+int cmd_force_lid_open(int argc, char *argv[])
+{
+	struct ec_params_force_lid_open p;
+	char *e;
+	int rv;
+
+	if (argc != 2) {
+		fprintf(stderr, "Usage: %s <0|1>\n", argv[0]);
+		return -1;
+	}
+	p.enabled = strtol(argv[1], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad value.\n");
+		return -1;
+	}
+
+	rv = ec_command(EC_CMD_FORCE_LID_OPEN, 0, &p, sizeof(p), NULL, 0);
+	if (rv < 0)
+		return rv;
+	printf("Success.\n");
+	return 0;
+}
+
+int cmd_charge_port_override(int argc, char *argv[])
+{
+	struct ec_params_charge_port_override p;
+	char *e;
+	int rv;
+
+	if (argc < 2) {
+		fprintf(stderr, "Usage: %s <port# | dontcharge | off>\n",
+			argv[0]);
+		return -1;
+	}
+
+	if (!strcasecmp(argv[1], "dontcharge"))
+		p.override_port = OVERRIDE_DONT_CHARGE;
+	else if (!strcasecmp(argv[1], "off"))
+		p.override_port = OVERRIDE_OFF;
+	else {
+		p.override_port = strtol(argv[1], &e, 0);
+		if (e && *e) {
+			fprintf(stderr, "Bad parameter.\n");
+			return -1;
+		}
+	}
+
+	rv = ec_command(EC_CMD_PD_CHARGE_PORT_OVERRIDE, 0, &p, sizeof(p), NULL,
+			0);
+	if (rv < 0)
+		return rv;
+
+	printf("Override port set to %d\n", p.override_port);
+	return 0;
+}
+
+static void cmd_pchg_help(char *cmd)
+{
+	fprintf(stderr,
+		"  Usage1: %s\n"
+		"          Print the number of ports.\n"
+		"\n"
+		"  Usage2: %s <port>\n"
+		"          Print the status of <port>.\n"
+		"\n"
+		"  Usage3: %s <port> reset [mode]\n"
+		"          Reset <port> to [mode]. [mode]: 'normal'.\n"
+		"\n"
+		"  Usage4: %s <port> update <version> <addr1> <file1> <addr2> <file2> ...\n"
+		"          Update firmware of <port>.\n"
+		"\n"
+		"  Usage5: %s <port> passthru <on/off> ...\n"
+		"          Enable passthru mode for <port>.\n",
+		cmd, cmd, cmd, cmd, cmd);
+}
+
+static int cmd_pchg_info(const struct ec_response_pchg *res)
+{
+	static const char *const pchg_state_text[] = EC_PCHG_STATE_TEXT;
+
+	BUILD_ASSERT(ARRAY_SIZE(pchg_state_text) == PCHG_STATE_COUNT);
+
+	printf("State: %s (%d)\n",
+	       res->state < PCHG_STATE_COUNT ? pchg_state_text[res->state] :
+					       "UNDEF",
+	       res->state);
+	printf("Battery: %u%%\n", res->battery_percentage);
+	printf("Errors: 0x%x\n", res->error);
+	printf("FW Version: 0x%x\n", res->fw_version);
+	printf("Dropped events: %u\n", res->dropped_event_count);
+	return 0;
+}
+
+static int cmd_pchg_wait_event(int port, uint32_t expected)
+{
+	struct ec_response_get_next_event_v1 event;
+	const long timeout = 5000;
+	uint32_t *e = &event.data.host_event;
+	int rv;
+
+	rv = wait_event(EC_MKBP_EVENT_PCHG, &event, sizeof(event), timeout);
+	if (rv < 0)
+		return rv;
+
+	if (EC_MKBP_PCHG_EVENT_TO_PORT(*e) == port) {
+		if (*e & EC_MKBP_PCHG_UPDATE_ERROR) {
+			fprintf(stderr, "\nReceived update error\n");
+			return -1;
+		}
+		if (*e & expected)
+			return 0;
+	}
+
+	fprintf(stderr, "\nExpected event=0x%x but received 0x%x\n", expected,
+		*e);
+	return -1;
+}
+
+static int cmd_pchg_update_open(int port, uint32_t version,
+				uint32_t *block_size, uint32_t *crc)
+{
+	struct ec_params_pchg_update *pu =
+		(struct ec_params_pchg_update *)(ec_outbuf);
+	struct ec_response_pchg_update *r =
+		(struct ec_response_pchg_update *)(ec_inbuf);
+	struct ec_params_pchg p;
+	struct ec_response_pchg_v2 rv2;
+	int rv;
+
+	/* Open session. */
+	pu->port = port;
+	pu->cmd = EC_PCHG_UPDATE_CMD_OPEN;
+	pu->version = version;
+	rv = ec_command(EC_CMD_PCHG_UPDATE, 0, pu, sizeof(*pu), r, sizeof(*r));
+	if (rv < 0) {
+		fprintf(stderr, "\nFailed to open update session: %d\n", rv);
+		return rv;
+	}
+
+	if (r->block_size + sizeof(*pu) > ec_max_outsize) {
+		fprintf(stderr, "\nBlock size (%d) is too large.\n",
+			r->block_size);
+		return -1;
+	}
+
+	rv = cmd_pchg_wait_event(port, EC_MKBP_PCHG_DEVICE_EVENT);
+	if (rv)
+		return rv;
+
+	p.port = port;
+	rv = ec_command(EC_CMD_PCHG, 2, &p, sizeof(p), &rv2, sizeof(rv2));
+	if (rv == -EC_RES_INVALID_VERSION - EECRESULT)
+		/* We can use v2 because it's a superset of v1. */
+		rv = ec_command(EC_CMD_PCHG, 1, &p, sizeof(p), &rv2,
+				sizeof(struct ec_response_pchg));
+	if (rv < 0) {
+		fprintf(stderr, "EC_CMD_PCHG failed: %d\n", rv);
+		return rv;
+	}
+	if (rv2.state != PCHG_STATE_DOWNLOAD) {
+		fprintf(stderr, "Failed to reset to download mode: %d\n", rv);
+		return -1;
+	}
+
+	rv = cmd_pchg_wait_event(port, EC_MKBP_PCHG_UPDATE_OPENED);
+	if (rv)
+		return rv;
+
+	printf("Opened update session (port=%d ver=0x%x bsize=%d):\n", port,
+	       version, r->block_size);
+
+	*block_size = r->block_size;
+	crc32_ctx_init(crc);
+
+	return 0;
+}
+
+static int cmd_pchg_update_write(int port, uint32_t address,
+				 const char *filename, uint32_t block_size,
+				 uint32_t *crc)
+{
+	struct ec_params_pchg_update *p =
+		(struct ec_params_pchg_update *)(ec_outbuf);
+	FILE *fp;
+	size_t len, total;
+	int progress = 0;
+	int rv;
+
+	fp = fopen(filename, "rb");
+	if (!fp) {
+		fprintf(stderr, "\nCan't open %s: %s\n", filename,
+			strerror(errno));
+		return -1;
+	}
+
+	fseek(fp, 0L, SEEK_END);
+	total = ftell(fp);
+	rewind(fp);
+	printf("Writing %s (%zu bytes).\n", filename, total);
+
+	p->cmd = EC_PCHG_UPDATE_CMD_WRITE;
+	p->addr = address;
+
+	/* Write firmware in blocks. */
+	len = fread(p->data, 1, block_size, fp);
+	while (len > 0) {
+		int previous_progress = progress;
+		int i;
+
+		crc32_ctx_hash(crc, p->data, len);
+		p->size = len;
+		rv = ec_command(EC_CMD_PCHG_UPDATE, 0, p, sizeof(*p) + len,
+				NULL, 0);
+		if (rv < 0) {
+			fprintf(stderr, "\nFailed to write FW: %d\n", rv);
+			fclose(fp);
+			return rv;
+		}
+
+		rv = cmd_pchg_wait_event(port, EC_MKBP_PCHG_WRITE_COMPLETE);
+		if (rv)
+			return rv;
+
+		p->addr += len;
+		progress = (p->addr - address) * 100 / total;
+		for (i = 0; i < progress - previous_progress; i++) {
+			printf("*");
+			fflush(stdout);
+		}
+
+		len = fread(p->data, 1, block_size, fp);
+	}
+
+	printf("\n");
+	fclose(fp);
+
+	return 0;
+}
+
+static int cmd_pchg_update_close(int port, uint32_t *crc)
+{
+	struct ec_params_pchg_update *p =
+		(struct ec_params_pchg_update *)(ec_outbuf);
+	int rv;
+
+	p->cmd = EC_PCHG_UPDATE_CMD_CLOSE;
+	p->crc32 = crc32_ctx_result(crc);
+	rv = ec_command(EC_CMD_PCHG_UPDATE, 0, p, sizeof(*p), NULL, 0);
+
+	if (rv < 0) {
+		fprintf(stderr, "\nFailed to close update session: %d\n", rv);
+		return rv;
+	}
+
+	rv = cmd_pchg_wait_event(port, EC_MKBP_PCHG_UPDATE_CLOSED);
+	if (rv)
+		return rv;
+
+	printf("Firmware was updated successfully (CRC32=0x%x).\n", p->crc32);
+
+	return 0;
+}
+
+static int cmd_pchg(int argc, char *argv[])
+{
+	const size_t max_input_files = 8;
+	int port, port_count;
+	struct ec_response_pchg_count rcnt;
+	struct ec_params_pchg p;
+	struct ec_response_pchg r;
+	char *e;
+	int rv;
+
+	rv = ec_command(EC_CMD_PCHG_COUNT, 0, NULL, 0, &rcnt, sizeof(rcnt));
+	if (rv < 0) {
+		fprintf(stderr, "\nFailed to get port count: %d\n", rv);
+		return rv;
+	}
+	port_count = rcnt.port_count;
+
+	if (argc == 1) {
+		/* Usage.1 */
+		printf("%d\n", port_count);
+		return 0;
+	}
+
+	port = strtol(argv[1], &e, 0);
+	if ((e && *e) || port >= port_count) {
+		fprintf(stderr, "\nBad port index: %s\n", argv[1]);
+		cmd_pchg_help(argv[0]);
+		return -1;
+	}
+
+	p.port = port;
+	rv = ec_command(EC_CMD_PCHG, 1, &p, sizeof(p), &r, sizeof(r));
+	if (rv < 0) {
+		fprintf(stderr, "\nError code: %d\n", rv);
+		return rv;
+	}
+
+	if (argc == 2) {
+		/* Usage.2 */
+		return cmd_pchg_info(&r);
+	} else if (argc >= 3 && !strcmp(argv[2], "reset")) {
+		/* Usage.3 */
+		struct ec_params_pchg_update u;
+
+		u.port = port;
+
+		if (argc == 3) {
+			u.cmd = EC_PCHG_UPDATE_CMD_RESET;
+		} else if (argc == 4 && !strcmp(argv[3], "normal")) {
+			u.cmd = EC_PCHG_UPDATE_CMD_RESET_TO_NORMAL;
+		} else {
+			fprintf(stderr, "\nInvalid mode: '%s'\n", argv[3]);
+			return -1;
+		}
+
+		rv = ec_command(EC_CMD_PCHG_UPDATE, 0, &u, sizeof(u), NULL, 0);
+		if (rv < 0) {
+			fprintf(stderr, "\nFailed to reset port %d: %d\n", port,
+				rv);
+			cmd_pchg_help(argv[0]);
+			return rv;
+		}
+		printf("Reset port %d complete.\n", port);
+		return 0;
+	} else if (argc >= 6 && !strcmp(argv[2], "update")) {
+		/*
+		 * Usage.4:
+		 * argv[3]: <version>
+		 * argv[4]: <addr1>
+		 * argv[5]: <file1>
+		 * argv[6]: <addr2>
+		 * argv[7]: <file2>
+		 * ...
+		 */
+		uint32_t address, version;
+		uint32_t block_size = 0;
+		uint32_t crc;
+		int i;
+
+		if (argc > 4 + max_input_files * 2) {
+			fprintf(stderr, "\nToo many input files.\n");
+			return -1;
+		}
+
+		version = strtol(argv[3], &e, 0);
+		if (e && *e) {
+			fprintf(stderr, "\nBad version: %s.\n", argv[3]);
+			cmd_pchg_help(argv[0]);
+			return -1;
+		}
+
+		rv = cmd_pchg_update_open(port, version, &block_size, &crc);
+		if (rv < 0 || block_size == 0) {
+			fprintf(stderr, "\nFailed to open update session: %d\n",
+				rv);
+			return -1;
+		}
+
+		/* Write files one by one. */
+		for (i = 4; i + 1 < argc; i += 2) {
+			address = strtol(argv[i], &e, 0);
+			if (e && *e) {
+				fprintf(stderr, "\nBad address: %s\n", argv[i]);
+				cmd_pchg_help(argv[0]);
+				return -1;
+			}
+			rv = cmd_pchg_update_write(port, address, argv[i + 1],
+						   block_size, &crc);
+			if (rv < 0) {
+				fprintf(stderr,
+					"\nFailed to write file '%s': %d",
+					argv[i + i], rv);
+				return -1;
+			}
+		}
+
+		rv = cmd_pchg_update_close(port, &crc);
+		if (rv < 0) {
+			fprintf(stderr, "\nFailed to close update session: %d",
+				rv);
+			return -1;
+		}
+
+		return 0;
+	} else if (argc >= 4 && !strcmp(argv[2], "passthru")) {
+		/*
+		 * Usage 5
+		 */
+		struct ec_params_pchg_update u;
+		int onoff;
+
+		if (!parse_bool(argv[3], &onoff)) {
+			fprintf(stderr, "\nInvalid arg: '%s'\n", argv[3]);
+			return -1;
+		}
+
+		u.port = port;
+		u.cmd = EC_PCHG_UPDATE_CMD_ENABLE_PASSTHRU;
+
+		rv = ec_command(EC_CMD_PCHG_UPDATE, 0, &u, sizeof(u), NULL, 0);
+		if (rv < 0) {
+			fprintf(stderr, "\nFailed to enable pass-through: %d\n",
+				rv);
+			return rv;
+		}
+
+		printf("Pass-through is %s for port %d\n",
+		       onoff ? "enabled" : "disabled", port);
+		return 0;
+	}
+
+	fprintf(stderr, "Invalid parameter\n\n");
+	cmd_pchg_help(argv[0]);
+
+	return -1;
+}
+
+int cmd_pd_log(int argc, char *argv[])
+{
+	union {
+		struct ec_response_pd_log r;
+		uint32_t words[8]; /* space for the payload */
+	} u;
+	struct mcdp_info minfo;
+	struct ec_response_usb_pd_power_info pinfo;
+	int rv;
+	unsigned long long milliseconds;
+	unsigned int seconds;
+	time_t now;
+	struct tm ltime;
+	char time_str[64];
+
+	while (1) {
+		now = time(NULL);
+		rv = ec_command(EC_CMD_PD_GET_LOG_ENTRY, 0, NULL, 0, &u,
+				sizeof(u));
+		if (rv < 0)
+			return rv;
+
+		if (u.r.type == PD_EVENT_NO_ENTRY) {
+			printf("--- END OF LOG ---\n");
+			break;
+		}
+
+		/* the timestamp is in 1024th of seconds */
+		milliseconds =
+			((uint64_t)u.r.timestamp << PD_LOG_TIMESTAMP_SHIFT) /
+			1000;
+		/* the timestamp is the number of milliseconds in the past */
+		seconds = (milliseconds + 999) / 1000;
+		milliseconds -= seconds * 1000;
+		now -= seconds;
+		localtime_r(&now, &ltime);
+		strftime(time_str, sizeof(time_str), "%F %T", &ltime);
+		printf("%s.%03lld P%d ", time_str, -milliseconds,
+		       PD_LOG_PORT(u.r.size_port));
+		if (u.r.type == PD_EVENT_MCU_CHARGE) {
+			if (u.r.data & CHARGE_FLAGS_OVERRIDE)
+				printf("override ");
+			if (u.r.data & CHARGE_FLAGS_DELAYED_OVERRIDE)
+				printf("pending_override ");
+			memcpy(&pinfo.meas, u.r.payload,
+			       sizeof(struct usb_chg_measures));
+			pinfo.dualrole = !!(u.r.data & CHARGE_FLAGS_DUAL_ROLE);
+			pinfo.role = u.r.data & CHARGE_FLAGS_ROLE_MASK;
+			pinfo.type = (u.r.data & CHARGE_FLAGS_TYPE_MASK) >>
+				     CHARGE_FLAGS_TYPE_SHIFT;
+			pinfo.max_power = 0;
+			print_pd_power_info(&pinfo);
+		} else if (u.r.type == PD_EVENT_MCU_CONNECT) {
+			printf("New connection\n");
+		} else if (u.r.type == PD_EVENT_MCU_BOARD_CUSTOM) {
+			printf("Board-custom event\n");
+		} else if (u.r.type == PD_EVENT_ACC_RW_FAIL) {
+			printf("RW signature check failed\n");
+		} else if (u.r.type == PD_EVENT_PS_FAULT) {
+			static const char *const fault_names[] = {
+				"---", "OCP", "fast OCP", "OVP", "Discharge"
+			};
+			const char *fault = u.r.data < ARRAY_SIZE(fault_names) ?
+						    fault_names[u.r.data] :
+						    "???";
+			printf("Power supply fault: %s\n", fault);
+		} else if (u.r.type == PD_EVENT_VIDEO_DP_MODE) {
+			printf("DP mode %sabled\n",
+			       (u.r.data == 1) ? "en" : "dis");
+		} else if (u.r.type == PD_EVENT_VIDEO_CODEC) {
+			memcpy(&minfo, u.r.payload, sizeof(struct mcdp_info));
+			printf("HDMI info: family:%04x chipid:%04x "
+			       "irom:%d.%d.%d fw:%d.%d.%d\n",
+			       MCDP_FAMILY(minfo.family),
+			       MCDP_CHIPID(minfo.chipid), minfo.irom.major,
+			       minfo.irom.minor, minfo.irom.build,
+			       minfo.fw.major, minfo.fw.minor, minfo.fw.build);
+		} else { /* Unknown type */
+			int i;
+			printf("Event %02x (%04x) [", u.r.type, u.r.data);
+			for (i = 0; i < PD_LOG_SIZE(u.r.size_port); i++)
+				printf("%02x ", u.r.payload[i]);
+			printf("]\n");
+		}
+	}
+
+	return 0;
+}
+
+int cmd_pd_control(int argc, char *argv[])
+{
+	struct ec_params_pd_control p;
+	int rv;
+
+	if (argc < 2) {
+		fprintf(stderr, "Missing parameter\n");
+		return -1;
+	}
+
+	/* Parse command */
+	if (!strcmp(argv[1], "reset"))
+		p.subcmd = PD_RESET;
+	else if (!strcmp(argv[1], "suspend"))
+		p.subcmd = PD_SUSPEND;
+	else if (!strcmp(argv[1], "resume"))
+		p.subcmd = PD_RESUME;
+	else if (!strcmp(argv[1], "disable"))
+		p.subcmd = PD_CONTROL_DISABLE;
+	else if (!strcmp(argv[1], "on") || !strcmp(argv[1], "chip_on"))
+		p.subcmd = PD_CHIP_ON;
+	else {
+		fprintf(stderr, "Unknown command: %s\n", argv[1]);
+		return -1;
+	}
+
+	if (argc == 2) {
+		p.chip = 0;
+	} else {
+		char *e;
+		p.chip = strtol(argv[2], &e, 0);
+		if (e && *e) {
+			fprintf(stderr, "Bad port number '%s'.\n", argv[2]);
+			return -1;
+		}
+	}
+
+	rv = ec_command(EC_CMD_PD_CONTROL, 0, &p, sizeof(p), NULL, 0);
+	return (rv < 0 ? rv : 0);
+}
+
+int cmd_pd_chip_info(int argc, char *argv[])
+{
+	struct ec_params_pd_chip_info p;
+	struct ec_response_pd_chip_info_v1 r;
+	char *e;
+	int rv;
+	int cmdver = 1;
+
+	if (argc < 2 || 3 < argc) {
+		fprintf(stderr,
+			"Usage: %s <port> [<live>]\n"
+			"live parameter can take values 0 or 1\n"
+			"0 -> Return hard-coded value for VID/PID and\n"
+			"     cached value for Firmware Version\n"
+			"1 -> Return live chip value for VID/PID/FW Version\n",
+			argv[0]);
+		return -1;
+	}
+
+	p.port = strtol(argv[1], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad port number.\n");
+		return -1;
+	}
+
+	p.live = 0;
+	if (argc == 3) {
+		p.live = strtol(argv[2], &e, 0);
+		if (e && *e) {
+			fprintf(stderr, "invalid arg \"%s\"\n", argv[2]);
+			return -1;
+		}
+	}
+
+	if (!ec_cmd_version_supported(EC_CMD_PD_CHIP_INFO, cmdver))
+		cmdver = 0;
+
+	rv = ec_command(EC_CMD_PD_CHIP_INFO, cmdver, &p, sizeof(p), &r,
+			sizeof(r));
+	if (rv < 0)
+		return rv;
+
+	printf("vendor_id: 0x%x\n", r.vendor_id);
+	printf("product_id: 0x%x\n", r.product_id);
+	printf("device_id: 0x%x\n", r.device_id);
+
+	if (r.fw_version_number != -1)
+		printf("fw_version: 0x%" PRIx64 "\n", r.fw_version_number);
+	else
+		printf("fw_version: UNSUPPORTED\n");
+
+	if (cmdver >= 1)
+		printf("min_req_fw_version: 0x%" PRIx64 "\n",
+		       r.min_req_fw_version_number);
+	else
+		printf("min_req_fw_version: UNSUPPORTED\n");
+
+	return 0;
+}
+
+int cmd_pd_write_log(int argc, char *argv[])
+{
+	struct ec_params_pd_write_log_entry p;
+	char *e;
+
+	if (argc < 3) {
+		fprintf(stderr, "Usage: %s <log_type> <port>\n", argv[0]);
+		return -1;
+	}
+
+	if (!strcasecmp(argv[1], "charge"))
+		p.type = PD_EVENT_MCU_CHARGE;
+	else {
+		p.type = strtol(argv[1], &e, 0);
+		if (e && *e) {
+			fprintf(stderr, "Bad log_type parameter.\n");
+			return -1;
+		}
+	}
+
+	p.port = strtol(argv[2], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad port parameter.\n");
+		return -1;
+	}
+
+	return ec_command(EC_CMD_PD_WRITE_LOG_ENTRY, 0, &p, sizeof(p), NULL, 0);
+}
+
+int cmd_typec_control(int argc, char *argv[])
+{
+	struct ec_params_typec_control p;
+	long conversion_result;
+	char *endptr;
+	int rv;
+
+	if (argc < 3) {
+		fprintf(stderr,
+			"Usage: %s <port> <command> [args]\n"
+			"  <port> is the type-c port to query\n"
+			"  <command> is one of:\n"
+			"    0: Exit modes\n"
+			"    1: Clear events\n"
+			"        args: <event mask>\n"
+			"    2: Enter mode\n"
+			"        args: <0: DP, 1:TBT, 2:USB4>\n"
+			"    3: Set TBT UFP Reply\n"
+			"        args: <0: NAK, 1: ACK>\n"
+			"    4: Set USB mux mode\n"
+			"        args: <mux_index> <mux_mode>\n"
+			"        <mux_mode> is one of: dp, dock, usb, tbt,\n"
+			"                              usb4, none, safe\n"
+			"    5: Enable bist share mode\n"
+			"        args: <0: DISABLE, 1: ENABLE>\n"
+			"    6: Send VDM REQ\n"
+			"        args: <tx_type vdm_hdr [vdo...]>\n"
+			"        <tx_type> is 0 - SOP, 1 - SOP', 2 - SOP''\n",
+			argv[0]);
+		return -1;
+	}
+
+	p.port = strtol(argv[1], &endptr, 0);
+	if (endptr && *endptr) {
+		fprintf(stderr, "Bad port\n");
+		return -1;
+	}
+
+	p.command = strtol(argv[2], &endptr, 0);
+	if (endptr && *endptr) {
+		fprintf(stderr, "Bad command\n");
+		return -1;
+	}
+
+	switch (p.command) {
+	case TYPEC_CONTROL_COMMAND_CLEAR_EVENTS:
+		if (argc < 4) {
+			fprintf(stderr, "Missing event mask\n");
+			return -1;
+		}
+
+		p.clear_events_mask = strtol(argv[3], &endptr, 0);
+		if (endptr && *endptr) {
+			fprintf(stderr, "Bad event mask\n");
+			return -1;
+		}
+		break;
+	case TYPEC_CONTROL_COMMAND_ENTER_MODE:
+		if (argc < 4) {
+			fprintf(stderr, "Missing mode\n");
+			return -1;
+		}
+
+		conversion_result = strtol(argv[3], &endptr, 0);
+		if ((endptr && *endptr) || conversion_result > UINT8_MAX ||
+		    conversion_result < 0) {
+			fprintf(stderr, "Bad mode\n");
+			return -1;
+		}
+		p.mode_to_enter = conversion_result;
+		break;
+	case TYPEC_CONTROL_COMMAND_TBT_UFP_REPLY:
+		if (argc < 4) {
+			fprintf(stderr, "Missing reply\n");
+			return -1;
+		}
+
+		conversion_result = strtol(argv[3], &endptr, 0);
+		if ((endptr && *endptr) || conversion_result > UINT8_MAX ||
+		    conversion_result < 0) {
+			fprintf(stderr, "Bad reply\n");
+			return -1;
+		}
+		p.tbt_ufp_reply = conversion_result;
+		break;
+	case TYPEC_CONTROL_COMMAND_USB_MUX_SET:
+		if (argc < 5) {
+			fprintf(stderr, "Missing index or mode\n");
+			return -1;
+		}
+
+		conversion_result = strtol(argv[3], &endptr, 0);
+		if ((endptr && *endptr) || conversion_result > UINT8_MAX ||
+		    conversion_result < 0) {
+			fprintf(stderr, "Bad index\n");
+			return -1;
+		}
+		p.mux_params.mux_index = conversion_result;
+		if (!strcmp(argv[4], "dp")) {
+			p.mux_params.mux_flags = USB_PD_MUX_DP_ENABLED;
+		} else if (!strcmp(argv[4], "dock")) {
+			p.mux_params.mux_flags = USB_PD_MUX_DOCK;
+		} else if (!strcmp(argv[4], "usb")) {
+			p.mux_params.mux_flags = USB_PD_MUX_USB_ENABLED;
+		} else if (!strcmp(argv[4], "tbt")) {
+			p.mux_params.mux_flags = USB_PD_MUX_TBT_COMPAT_ENABLED;
+		} else if (!strcmp(argv[4], "usb4")) {
+			p.mux_params.mux_flags = USB_PD_MUX_USB4_ENABLED;
+		} else if (!strcmp(argv[4], "none")) {
+			p.mux_params.mux_flags = USB_PD_MUX_NONE;
+		} else if (!strcmp(argv[4], "safe")) {
+			p.mux_params.mux_flags = USB_PD_MUX_SAFE_MODE;
+		} else {
+			fprintf(stderr, "Bad mux mode\n");
+			return -1;
+		}
+		break;
+	case TYPEC_CONTROL_COMMAND_BIST_SHARE_MODE:
+		if (argc < 4) {
+			fprintf(stderr, "Missing reply\n");
+			return -1;
+		}
+
+		conversion_result = strtol(argv[3], &endptr, 0);
+		if ((endptr && *endptr) || conversion_result > UINT8_MAX ||
+		    conversion_result < 0) {
+			fprintf(stderr, "Bad index\n");
+			return -1;
+		}
+		p.bist_share_mode = conversion_result;
+		break;
+	case TYPEC_CONTROL_COMMAND_SEND_VDM_REQ:
+		if (argc < 5) {
+			fprintf(stderr, "Missing VDM header and type\n");
+			return -1;
+		}
+		if (argc > 4 + VDO_MAX_SIZE) {
+			fprintf(stderr, "Too many VDOs\n");
+			return -1;
+		}
+
+		conversion_result = strtol(argv[3], &endptr, 0);
+		if ((endptr && *endptr) || conversion_result > UINT8_MAX ||
+		    conversion_result < 0) {
+			fprintf(stderr, "Bad SOP* type\n");
+			return -1;
+		}
+		p.vdm_req_params.partner_type = conversion_result;
+
+		int vdm_index;
+		for (vdm_index = 0; vdm_index < argc - 4; vdm_index++) {
+			uint32_t vdm_entry =
+				strtoul(argv[vdm_index + 4], &endptr, 0);
+			if (endptr && *endptr) {
+				fprintf(stderr, "Bad VDO\n");
+				return -1;
+			}
+			p.vdm_req_params.vdm_data[vdm_index] = vdm_entry;
+		}
+		p.vdm_req_params.vdm_data_objects = vdm_index;
+	}
+
+	rv = ec_command(EC_CMD_TYPEC_CONTROL, 0, &p, sizeof(p), ec_inbuf,
+			ec_max_insize);
+	if (rv < 0)
+		return -1;
+
+	return 0;
+}
+
+int cmd_typec_discovery(int argc, char *argv[])
+{
+	struct ec_params_typec_discovery p;
+	struct ec_response_typec_discovery *r =
+		(struct ec_response_typec_discovery *)ec_inbuf;
+	char *e;
+	int rv, i, j;
+
+	if (argc < 3) {
+		fprintf(stderr,
+			"Usage: %s <port> <type>\n"
+			"  <port> is the type-c port to query\n"
+			"  <type> is one of:\n"
+			"    0: SOP\n"
+			"    1: SOP prime\n",
+			argv[0]);
+		return -1;
+	}
+
+	p.port = strtol(argv[1], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad port\n");
+		return -1;
+	}
+
+	p.partner_type = strtol(argv[2], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad type\n");
+		return -1;
+	}
+
+	rv = ec_command(EC_CMD_TYPEC_DISCOVERY, 0, &p, sizeof(p), ec_inbuf,
+			ec_max_insize);
+	if (rv < 0)
+		return -1;
+
+	if (r->identity_count == 0) {
+		printf("No identity discovered\n");
+		return 0;
+	}
+
+	printf("Identity VDOs:\n");
+	for (i = 0; i < r->identity_count; i++)
+		printf("0x%08x\n", r->discovery_vdo[i]);
+
+	if (r->svid_count == 0) {
+		printf("No SVIDs discovered\n");
+		return 0;
+	}
+
+	for (i = 0; i < r->svid_count; i++) {
+		printf("SVID 0x%04x Modes:\n", r->svids[i].svid);
+		for (j = 0; j < r->svids[i].mode_count; j++)
+			printf("0x%08x\n", r->svids[i].mode_vdo[j]);
+	}
+
+	return 0;
+}
+
+/* Print shared fields of sink and source cap PDOs */
+static inline void print_pdo_fixed(uint32_t pdo)
+{
+	printf("    Fixed: %dmV %dmA %s%s%s%s", PDO_FIXED_VOLTAGE(pdo),
+	       PDO_FIXED_CURRENT(pdo), pdo & PDO_FIXED_DUAL_ROLE ? "DRP " : "",
+	       pdo & PDO_FIXED_UNCONSTRAINED ? "UP " : "",
+	       pdo & PDO_FIXED_COMM_CAP ? "USB " : "",
+	       pdo & PDO_FIXED_DATA_SWAP ? "DRD" : "");
+}
+
+static inline void print_pdo_battery(uint32_t pdo)
+{
+	printf("    Battery: max %dmV min %dmV max %dmW\n",
+	       PDO_BATT_MAX_VOLTAGE(pdo), PDO_BATT_MIN_VOLTAGE(pdo),
+	       PDO_BATT_MAX_POWER(pdo));
+}
+
+static inline void print_pdo_variable(uint32_t pdo)
+{
+	printf("    Variable: max %dmV min %dmV max %dmA\n",
+	       PDO_VAR_MAX_VOLTAGE(pdo), PDO_VAR_MIN_VOLTAGE(pdo),
+	       PDO_VAR_MAX_CURRENT(pdo));
+}
+
+static inline void print_pdo_augmented(uint32_t pdo)
+{
+	printf("    Augmented: max %dmV min %dmV max %dmA\n",
+	       PDO_AUG_MAX_VOLTAGE(pdo), PDO_AUG_MIN_VOLTAGE(pdo),
+	       PDO_AUG_MAX_CURRENT(pdo));
+}
+
+int cmd_typec_status(int argc, char *argv[])
+{
+	struct ec_params_typec_status p;
+	struct ec_response_typec_status *r =
+		(struct ec_response_typec_status *)ec_inbuf;
+	char *endptr;
+	int rv, i;
+	const char *desc;
+
+	if (argc != 2) {
+		fprintf(stderr,
+			"Usage: %s <port>\n"
+			"  <port> is the type-c port to query\n",
+			argv[0]);
+		return -1;
+	}
+
+	p.port = strtol(argv[1], &endptr, 0);
+	if (endptr && *endptr) {
+		fprintf(stderr, "Bad port\n");
+		return -1;
+	}
+
+	rv = ec_command(EC_CMD_TYPEC_STATUS, 0, &p, sizeof(p), ec_inbuf,
+			ec_max_insize);
+	if (rv == -EC_RES_INVALID_COMMAND - EECRESULT)
+		/* Fall back to PD_CONTROL to support older ECs */
+		return cmd_usb_pd(argc, argv);
+	else if (rv < 0)
+		return -1;
+
+	printf("Port C%d: %s, %s  State:%s\n"
+	       "Role:%s %s%s, Polarity:CC%d\n",
+	       p.port, r->pd_enabled ? "enabled" : "disabled",
+	       r->dev_connected ? "connected" : "disconnected", r->tc_state,
+	       (r->power_role == PD_ROLE_SOURCE) ? "SRC" : "SNK",
+	       (r->data_role == PD_ROLE_DFP) ? "DFP" :
+	       (r->data_role == PD_ROLE_UFP) ? "UFP" :
+					       "",
+	       (r->vconn_role == PD_ROLE_VCONN_SRC) ? " VCONN" : "",
+	       (r->polarity % 2 + 1));
+
+	switch (r->cc_state) {
+	case PD_CC_NONE:
+		desc = "None";
+		break;
+	case PD_CC_UFP_AUDIO_ACC:
+		desc = "UFP Audio accessory";
+		break;
+	case PD_CC_UFP_DEBUG_ACC:
+		desc = "UFP Debug accessory";
+		break;
+	case PD_CC_UFP_ATTACHED:
+		desc = "UFP attached";
+		break;
+	case PD_CC_DFP_DEBUG_ACC:
+		desc = "DFP Debug accessory";
+		break;
+	case PD_CC_DFP_ATTACHED:
+		desc = "DFP attached";
+		break;
+	default:
+		desc = "UNKNOWN";
+		break;
+	}
+	printf("CC State: %s\n", desc);
+
+	if (r->dp_pin) {
+		switch (r->dp_pin) {
+		case MODE_DP_PIN_A:
+			desc = "A";
+			break;
+		case MODE_DP_PIN_B:
+			desc = "B";
+			break;
+		case MODE_DP_PIN_C:
+			desc = "C";
+			break;
+		case MODE_DP_PIN_D:
+			desc = "D";
+			break;
+		case MODE_DP_PIN_E:
+			desc = "E";
+			break;
+		case MODE_DP_PIN_F:
+			desc = "F";
+			break;
+		default:
+			desc = "UNKNOWN";
+			break;
+		}
+		printf("DP pin mode: %s\n", desc);
+	}
+
+	if (r->mux_state) {
+		printf("MUX: USB=%d DP=%d POLARITY=%s HPD_IRQ=%d HPD_LVL=%d\n"
+		       "     SAFE=%d TBT=%d USB4=%d\n",
+		       !!(r->mux_state & USB_PD_MUX_USB_ENABLED),
+		       !!(r->mux_state & USB_PD_MUX_DP_ENABLED),
+		       (r->mux_state & USB_PD_MUX_POLARITY_INVERTED) ?
+			       "INVERTED" :
+			       "NORMAL",
+		       !!(r->mux_state & USB_PD_MUX_HPD_IRQ),
+		       !!(r->mux_state & USB_PD_MUX_HPD_LVL),
+		       !!(r->mux_state & USB_PD_MUX_SAFE_MODE),
+		       !!(r->mux_state & USB_PD_MUX_TBT_COMPAT_ENABLED),
+		       !!(r->mux_state & USB_PD_MUX_USB4_ENABLED));
+	}
+
+	printf("Port events: 0x%08x\n", r->events);
+
+	if (r->sop_revision)
+		printf("SOP  PD Rev: %d.%d\n",
+		       PD_STATUS_REV_GET_MAJOR(r->sop_revision),
+		       PD_STATUS_REV_GET_MINOR(r->sop_revision));
+
+	if (r->sop_prime_revision)
+		printf("SOP' PD Rev: %d.%d\n",
+		       PD_STATUS_REV_GET_MAJOR(r->sop_prime_revision),
+		       PD_STATUS_REV_GET_MINOR(r->sop_prime_revision));
+
+	for (i = 0; i < r->source_cap_count; i++) {
+		/*
+		 * Bits 31:30 always indicate the type of PDO
+		 *
+		 * Table 6-7 PD Rev 3.0 Ver 2.0
+		 */
+		uint32_t pdo = r->source_cap_pdos[i];
+		int pdo_type = pdo & PDO_TYPE_MASK;
+
+		if (i == 0)
+			printf("Source Capabilities:\n");
+
+		if (pdo_type == PDO_TYPE_FIXED) {
+			print_pdo_fixed(pdo);
+			printf("\n");
+		} else if (pdo_type == PDO_TYPE_BATTERY) {
+			print_pdo_battery(pdo);
+		} else if (pdo_type == PDO_TYPE_VARIABLE) {
+			print_pdo_variable(pdo);
+		} else {
+			print_pdo_augmented(pdo);
+		}
+	}
+
+	for (i = 0; i < r->sink_cap_count; i++) {
+		/*
+		 * Bits 31:30 always indicate the type of PDO
+		 *
+		 * Table 6-7 PD Rev 3.0 Ver 2.0
+		 */
+		uint32_t pdo = r->sink_cap_pdos[i];
+		int pdo_type = pdo & PDO_TYPE_MASK;
+
+		if (i == 0)
+			printf("Sink Capabilities:\n");
+
+		if (pdo_type == PDO_TYPE_FIXED) {
+			print_pdo_fixed(pdo);
+			/* Note: FRS bits are reserved in PD 2.0 spec */
+			printf("%s\n",
+			       pdo & PDO_FIXED_FRS_CURR_MASK ? "FRS" : "");
+		} else if (pdo_type == PDO_TYPE_BATTERY) {
+			print_pdo_battery(pdo);
+		} else if (pdo_type == PDO_TYPE_VARIABLE) {
+			print_pdo_variable(pdo);
+		} else {
+			print_pdo_augmented(pdo);
+		}
+	}
+
+	return 0;
+}
+
+int cmd_typec_vdm_response(int argc, char *argv[])
+{
+	struct ec_params_typec_vdm_response p;
+	struct ec_response_typec_vdm_response *r =
+		(ec_response_typec_vdm_response *)ec_inbuf;
+	char *endptr;
+	int rv, i;
+
+	if (argc != 2) {
+		fprintf(stderr,
+			"Usage: %s <port>\n"
+			"  <port> is the type-c port to query\n",
+			argv[0]);
+		return -1;
+	}
+
+	p.port = strtol(argv[1], &endptr, 0);
+	if (endptr && *endptr) {
+		fprintf(stderr, "Bad port\n");
+		return -1;
+	}
+
+	rv = ec_command(EC_CMD_TYPEC_VDM_RESPONSE, 0, &p, sizeof(p), ec_inbuf,
+			ec_max_insize);
+	if (rv < 0)
+		return -1;
+
+	if (r->vdm_data_objects > 0 && r->vdm_response_err == EC_RES_SUCCESS) {
+		printf("VDM response from partner: %d", r->partner_type);
+		for (i = 0; i < r->vdm_data_objects; i++)
+			printf("\n  0x%08x", r->vdm_response[i]);
+		printf("\n");
+	} else {
+		printf("No VDM response found (err: %d)\n",
+		       r->vdm_response_err);
+	}
+
+	if (r->vdm_attention_objects > 0) {
+		printf("VDM Attention:");
+		for (i = 0; i < r->vdm_attention_objects; i++)
+			printf("\n  0x%08x", r->vdm_attention[i]);
+		printf("\n");
+		printf("%d Attention messages remaining\n",
+		       r->vdm_attention_left);
+	} else {
+		printf("No VDM Attention found");
+	}
+
+	return 0;
+}
+
+int cmd_tp_self_test(int argc, char *argv[])
+{
+	int rv;
+
+	rv = ec_command(EC_CMD_TP_SELF_TEST, 0, NULL, 0, NULL, 0);
+	if (rv < 0)
+		return rv;
+
+	printf("Touchpad self test: %s\n",
+	       rv == EC_RES_SUCCESS ? "passed" : "failed");
+
+	return rv;
+}
+
+int cmd_tp_frame_get(int argc, char *argv[])
+{
+	int i, j;
+	uint32_t remaining = 0, offset = 0;
+	int rv = EC_SUCCESS;
+	uint8_t *data;
+	struct ec_response_tp_frame_info *r;
+	struct ec_params_tp_frame_get p;
+
+	data = (uint8_t *)(malloc(ec_max_insize));
+	r = (struct ec_response_tp_frame_info *)(malloc(ec_max_insize));
+
+	if (data == NULL || r == NULL) {
+		fprintf(stderr, "Couldn't allocate memory.\n");
+		free(r);
+		free(data);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	rv = ec_command(EC_CMD_TP_FRAME_INFO, 0, NULL, 0, r, ec_max_insize);
+	if (rv < 0) {
+		fprintf(stderr, "Failed to get touchpad frame info.\n");
+		goto err;
+	}
+
+	rv = ec_command(EC_CMD_TP_FRAME_SNAPSHOT, 0, NULL, 0, NULL, 0);
+	if (rv < 0) {
+		fprintf(stderr, "Failed to snapshot frame.\n");
+		goto err;
+	}
+
+	for (i = 0; i < r->n_frames; i++) {
+		p.frame_index = i;
+		offset = 0;
+		remaining = r->frame_sizes[i];
+
+		while (remaining > 0) {
+			p.offset = offset;
+			p.size = MIN(remaining, ec_max_insize);
+
+			rv = ec_command(EC_CMD_TP_FRAME_GET, 0, &p, sizeof(p),
+					data, p.size);
+			if (rv < 0) {
+				fprintf(stderr,
+					"Failed to get frame data "
+					"at offset 0x%x\n",
+					offset);
+				goto err;
+			}
+
+			for (j = 0; j < p.size; j++)
+				printf("%02x ", data[j]);
+
+			offset += p.size;
+			remaining -= p.size;
+		}
+		printf("\n");
+	}
+
+err:
+	free(data);
+	free(r);
+
+	return rv < 0;
+}
+
+int cmd_wait_event(int argc, char *argv[])
+{
+	static const char *const mkbp_event_text[] = EC_MKBP_EVENT_TEXT;
+	static const char *const host_event_text[] = HOST_EVENT_TEXT;
+
+	int rv, i;
+	struct ec_response_get_next_event_v1 buffer;
+	long timeout = 5000;
+	long event_type;
+	char *e;
+
+	BUILD_ASSERT(ARRAY_SIZE(mkbp_event_text) == EC_MKBP_EVENT_COUNT);
+	/*
+	 * Only 64 host events are supported. The enum |host_event_code| uses
+	 * 1-based counting so it can skip 0 (NONE). The last legal host event
+	 * number is 64, so ARRAY_SIZE(host_event_text) <= 64+1.
+	 */
+	BUILD_ASSERT(ARRAY_SIZE(host_event_text) <= 65);
+
+	if (!ec_pollevent) {
+		fprintf(stderr, "Polling for MKBP event not supported\n");
+		return -EINVAL;
+	}
+
+	if (argc < 2) {
+		fprintf(stderr, "Usage: %s <type> [<timeout>]\n", argv[0]);
+		fprintf(stderr, "\n");
+		fprintf(stderr, "type: MKBP event number or name.\n");
+		for (int i = 0; i < ARRAY_SIZE(mkbp_event_text); i++) {
+			const char *name = mkbp_event_text[i];
+
+			if (name) {
+				fprintf(stderr, "      %s or %d\n", name, i);
+			}
+		}
+
+		return -1;
+	}
+
+	rv = find_enum_from_text(argv[1], mkbp_event_text,
+				 ARRAY_SIZE(mkbp_event_text), &event_type);
+	if (rv < 0 || event_type < 0 || event_type >= EC_MKBP_EVENT_COUNT) {
+		fprintf(stderr, "Bad event type '%s'.\n", argv[1]);
+		return -1;
+	}
+	if (argc >= 3) {
+		timeout = strtol(argv[2], &e, 0);
+		if (e && *e) {
+			fprintf(stderr, "Bad timeout value '%s'.\n", argv[2]);
+			return -1;
+		}
+	}
+
+	rv = wait_event(event_type, &buffer, sizeof(buffer), timeout);
+	if (rv < 0)
+		return rv;
+
+	printf("MKBP event %d data: ", buffer.event_type);
+	for (i = 0; i < rv - 1; ++i)
+		printf("%02x ", buffer.data.key_matrix[i]);
+	printf("\n");
+
+	switch (event_type) {
+	case EC_MKBP_EVENT_HOST_EVENT:
+		printf("Host events:");
+		for (int evt = 1; evt < ARRAY_SIZE(host_event_text); evt++) {
+			if (buffer.data.host_event & EC_HOST_EVENT_MASK(evt)) {
+				const char *name = host_event_text[evt];
+
+				printf(" %s", name ? name : "UNKNOWN");
+			}
+		}
+		printf("\n");
+		break;
+	}
+
+	return 0;
+}
+
+static void cmd_cec_help(const char *cmd)
+{
+	fprintf(stderr,
+		"  Usage: %s write [write bytes...]\n"
+		"    Write message on the CEC bus\n"
+		"  Usage: %s read [timeout]\n"
+		"    [timeout] in seconds\n"
+		"  Usage: %s get <param>\n"
+		"  Usage: %s set <param> <val>\n"
+		"    <param> is one of:\n"
+		"      address: CEC receive address\n"
+		"        <val> is the new CEC address\n"
+		"      enable: Enable or disable CEC\n"
+		"        <val> is 1 to enable, 0 to disable\n",
+		cmd, cmd, cmd, cmd);
+}
+
+static int cmd_cec_write(int argc, char *argv[])
+{
+	char *e;
+	long val;
+	int rv, i, msg_len;
+	struct ec_params_cec_write p;
+	struct ec_response_get_next_event_v1 buffer;
+
+	if (argc < 3 || argc > 18) {
+		fprintf(stderr, "Invalid number of params\n");
+		cmd_cec_help(argv[0]);
+		return -1;
+	}
+
+	msg_len = argc - 2;
+	for (i = 0; i < msg_len; i++) {
+		val = strtol(argv[i + 2], &e, 16);
+		if (e && *e)
+			return -1;
+		if (val < 0 || val > 0xff)
+			return -1;
+		p.msg[i] = (uint8_t)val;
+	}
+
+	printf("Write to CEC: ");
+	for (i = 0; i < msg_len; i++)
+		printf("0x%02x ", p.msg[i]);
+	printf("\n");
+
+	rv = ec_command(EC_CMD_CEC_WRITE_MSG, 0, &p, msg_len, NULL, 0);
+	if (rv < 0)
+		return rv;
+
+	rv = wait_event(EC_MKBP_EVENT_CEC_EVENT, &buffer, sizeof(buffer), 1000);
+	if (rv < 0)
+		return rv;
+
+	if (buffer.data.cec_events & EC_MKBP_CEC_SEND_OK)
+		return 0;
+
+	if (buffer.data.cec_events & EC_MKBP_CEC_SEND_FAILED) {
+		fprintf(stderr, "Send failed\n");
+		return -1;
+	}
+
+	fprintf(stderr, "No send result received\n");
+
+	return -1;
+}
+
+static int cmd_cec_read(int argc, char *argv[])
+{
+	int i, rv;
+	char *e;
+	struct ec_response_get_next_event_v1 buffer;
+	long timeout = 5000;
+
+	if (!ec_pollevent) {
+		fprintf(stderr, "Polling for MKBP event not supported\n");
+		return -EINVAL;
+	}
+
+	if (argc >= 3) {
+		timeout = strtol(argv[2], &e, 0);
+		if (e && *e) {
+			fprintf(stderr, "Bad timeout value '%s'.\n", argv[2]);
+			return -1;
+		}
+	}
+
+	rv = wait_event(EC_MKBP_EVENT_CEC_MESSAGE, &buffer, sizeof(buffer),
+			timeout);
+	if (rv < 0)
+		return rv;
+
+	printf("CEC data: ");
+	for (i = 0; i < rv - 1; i++)
+		printf("0x%02x ", buffer.data.cec_message[i]);
+	printf("\n");
+
+	return 0;
+}
+
+static int cec_cmd_from_str(const char *str)
+{
+	if (!strcmp("address", str))
+		return CEC_CMD_LOGICAL_ADDRESS;
+	if (!strcmp("enable", str))
+		return CEC_CMD_ENABLE;
+	return -1;
+}
+
+static int cmd_cec_set(int argc, char *argv[])
+{
+	char *e;
+	struct ec_params_cec_set p;
+	uint8_t val;
+	int cmd;
+
+	if (argc != 4) {
+		fprintf(stderr, "Invalid number of params\n");
+		cmd_cec_help(argv[0]);
+		return -1;
+	}
+
+	val = (uint8_t)strtol(argv[3], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad parameter '%s'.\n", argv[3]);
+		return -1;
+	}
+
+	cmd = cec_cmd_from_str(argv[2]);
+	if (cmd < 0) {
+		fprintf(stderr, "Invalid command '%s'.\n", argv[2]);
+		return -1;
+	}
+	p.cmd = cmd;
+	p.val = val;
+
+	return ec_command(EC_CMD_CEC_SET, 0, &p, sizeof(p), NULL, 0);
+}
+
+static int cmd_cec_get(int argc, char *argv[])
+{
+	int rv, cmd;
+	struct ec_params_cec_get p;
+	struct ec_response_cec_get r;
+
+	if (argc != 3) {
+		fprintf(stderr, "Invalid number of params\n");
+		cmd_cec_help(argv[0]);
+		return -1;
+	}
+
+	cmd = cec_cmd_from_str(argv[2]);
+	if (cmd < 0) {
+		fprintf(stderr, "Invalid command '%s'.\n", argv[2]);
+		return -1;
+	}
+	p.cmd = cmd;
+
+	rv = ec_command(EC_CMD_CEC_GET, 0, &p, sizeof(p), &r, sizeof(r));
+	if (rv < 0)
+		return rv;
+
+	printf("%d\n", r.val);
+
+	return 0;
+}
+
+int cmd_cec(int argc, char *argv[])
+{
+	if (argc < 2) {
+		fprintf(stderr, "Invalid number of params\n");
+		cmd_cec_help(argv[0]);
+		return -1;
+	}
+	if (!strcmp(argv[1], "write"))
+		return cmd_cec_write(argc, argv);
+	if (!strcmp(argv[1], "read"))
+		return cmd_cec_read(argc, argv);
+	if (!strcmp(argv[1], "get"))
+		return cmd_cec_get(argc, argv);
+	if (!strcmp(argv[1], "set"))
+		return cmd_cec_set(argc, argv);
+
+	fprintf(stderr, "Invalid sub command: %s\n", argv[1]);
+	cmd_cec_help(argv[0]);
+
+	return -1;
+}
+
+static void cmd_s0ix_counter_help(char *cmd)
+{
+	fprintf(stderr,
+		"  Usage: %s get - to get the value of s0ix counter\n"
+		"         %s reset - to reset s0ix counter \n",
+		cmd, cmd);
+}
+
+static int cmd_s0ix_counter(int argc, char *argv[])
+{
+	struct ec_params_s0ix_cnt p;
+	struct ec_response_s0ix_cnt r;
+	int rv;
+
+	if (argc != 2) {
+		fprintf(stderr, "Invalid number of params\n");
+		cmd_s0ix_counter_help(argv[0]);
+		return -1;
+	}
+
+	if (!strcasecmp(argv[1], "get")) {
+		p.flags = 0;
+	} else if (!strcasecmp(argv[1], "reset")) {
+		p.flags = EC_S0IX_COUNTER_RESET;
+	} else {
+		fprintf(stderr, "Bad subcommand: %s\n", argv[1]);
+		return -1;
+	}
+
+	rv = ec_command(EC_CMD_GET_S0IX_COUNTER, 0, &p, sizeof(p), &r,
+			sizeof(r));
+	if (rv < 0) {
+		return rv;
+	}
+
+	printf("s0ix_counter: %u\n", r.s0ix_counter);
+
+	return 0;
+}
+
+/* NULL-terminated list of commands */
+const struct command commands[] = {
+	{ "adcread", cmd_adc_read },
+	{ "addentropy", cmd_add_entropy },
+	{ "apreset", cmd_apreset },
+	{ "autofanctrl", cmd_thermal_auto_fan_ctrl },
+	{ "backlight", cmd_lcd_backlight },
+	{ "basestate", cmd_basestate },
+	{ "battery", cmd_battery },
+	{ "batterycutoff", cmd_battery_cut_off },
+	{ "batteryparam", cmd_battery_vendor_param },
+	{ "boardversion", cmd_board_version },
+	{ "boottime", cmd_boottime },
+	{ "button", cmd_button },
+	{ "cbi", cmd_cbi },
+	{ "chargecurrentlimit", cmd_charge_current_limit },
+	{ "chargecontrol", cmd_charge_control },
+	{ "chargeoverride", cmd_charge_port_override },
+	{ "chargesplash", cmd_chargesplash },
+	{ "chargestate", cmd_charge_state },
+	{ "chipinfo", cmd_chipinfo },
+	{ "cmdversions", cmd_cmdversions },
+	{ "console", cmd_console },
+	{ "cec", cmd_cec },
+	{ "echash", cmd_ec_hash },
+	{ "eventclear", cmd_host_event_clear },
+	{ "eventclearb", cmd_host_event_clear_b },
+	{ "eventget", cmd_host_event_get_raw },
+	{ "eventgetb", cmd_host_event_get_b },
+	{ "eventgetscimask", cmd_host_event_get_sci_mask },
+	{ "eventgetsmimask", cmd_host_event_get_smi_mask },
+	{ "eventgetwakemask", cmd_host_event_get_wake_mask },
+	{ "eventsetscimask", cmd_host_event_set_sci_mask },
+	{ "eventsetsmimask", cmd_host_event_set_smi_mask },
+	{ "eventsetwakemask", cmd_host_event_set_wake_mask },
+	{ "extpwrlimit", cmd_ext_power_limit },
+	{ "fanduty", cmd_fanduty },
+	{ "flasherase", cmd_flash_erase },
+	{ "flasheraseasync", cmd_flash_erase },
+	{ "flashprotect", cmd_flash_protect },
+	{ "flashread", cmd_flash_read },
+	{ "flashwrite", cmd_flash_write },
+	{ "flashinfo", cmd_flash_info },
+	{ "flashspiinfo", cmd_flash_spi_info },
+	{ "flashpd", cmd_flash_pd },
+	{ "forcelidopen", cmd_force_lid_open },
+	{ "fpcontext", cmd_fp_context },
+	{ "fpencstatus", cmd_fp_enc_status },
+	{ "fpframe", cmd_fp_frame },
+	{ "fpinfo", cmd_fp_info },
+	{ "fpmode", cmd_fp_mode },
+	{ "fpseed", cmd_fp_seed },
+	{ "fpstats", cmd_fp_stats },
+	{ "fptemplate", cmd_fp_template },
+	{ "gpioget", cmd_gpio_get },
+	{ "gpioset", cmd_gpio_set },
+	{ "hangdetect", cmd_hang_detect },
+	{ "hello", cmd_hello },
+	{ "hibdelay", cmd_hibdelay },
+	{ "hostevent", cmd_hostevent },
+	{ "hostsleepstate", cmd_hostsleepstate },
+	{ "locatechip", cmd_locate_chip },
+	{ "i2cprotect", cmd_i2c_protect },
+	{ "i2cread", cmd_i2c_read },
+	{ "i2cspeed", cmd_i2c_speed },
+	{ "i2cwrite", cmd_i2c_write },
+	{ "i2cxfer", cmd_i2c_xfer },
+	{ "infopddev", cmd_pd_device_info },
+	{ "inventory", cmd_inventory },
+	{ "led", cmd_led },
+	{ "lightbar", cmd_lightbar },
+	{ "kbfactorytest", cmd_keyboard_factory_test },
+	{ "kbinfo", cmd_kbinfo },
+	{ "kbpress", cmd_kbpress },
+	{ "keyconfig", cmd_keyconfig },
+	{ "keyscan", cmd_keyscan },
+	{ "memory_dump", cmd_memory_dump },
+	{ "mkbpget", cmd_mkbp_get },
+	{ "mkbpwakemask", cmd_mkbp_wake_mask },
+	{ "motionsense", cmd_motionsense },
+	{ "nextevent", cmd_next_event },
+	{ "panicinfo", cmd_panic_info },
+	{ "pause_in_s5", cmd_s5 },
+	{ "pchg", cmd_pchg },
+	{ "pdgetmode", cmd_pd_get_amode },
+	{ "pdsetmode", cmd_pd_set_amode },
+	{ "port80read", cmd_port80_read },
+	{ "pdlog", cmd_pd_log },
+	{ "pdcontrol", cmd_pd_control },
+	{ "pdchipinfo", cmd_pd_chip_info },
+	{ "pdwritelog", cmd_pd_write_log },
+	{ "powerinfo", cmd_power_info },
+	{ "protoinfo", cmd_proto_info },
+	{ "pse", cmd_pse },
+	{ "pstoreinfo", cmd_pstore_info },
+	{ "pstoreread", cmd_pstore_read },
+	{ "pstorewrite", cmd_pstore_write },
+	{ "pwmgetfanrpm", cmd_pwm_get_fan_rpm },
+	{ "pwmgetkblight", cmd_pwm_get_keyboard_backlight },
+	{ "pwmgetnumfans", cmd_pwm_get_num_fans },
+	{ "pwmgetduty", cmd_pwm_get_duty },
+	{ "pwmsetfanrpm", cmd_pwm_set_fan_rpm },
+	{ "pwmsetkblight", cmd_pwm_set_keyboard_backlight },
+	{ "pwmsetduty", cmd_pwm_set_duty },
+	{ "rand", cmd_rand },
+	{ "reboot_ec", cmd_reboot_ec },
+	{ "rgbkbd", cmd_rgbkbd },
+	{ "rollbackinfo", cmd_rollback_info },
+	{ "rtcget", cmd_rtc_get },
+	{ "rtcgetalarm", cmd_rtc_get_alarm },
+	{ "rtcset", cmd_rtc_set },
+	{ "rtcsetalarm", cmd_rtc_set_alarm },
+	{ "rwhashpd", cmd_rw_hash_pd },
+	{ "rwsig", cmd_rwsig },
+	{ "rwsigaction", cmd_rwsig_action_legacy },
+	{ "rwsigstatus", cmd_rwsig_status },
+	{ "sertest", cmd_serial_test },
+	{ "s0ix_counter", cmd_s0ix_counter },
+	{ "smartdischarge", cmd_smart_discharge },
+	{ "stress", cmd_stress_test },
+	{ "sysinfo", cmd_sysinfo },
+	{ "port80flood", cmd_port_80_flood },
+	{ "switches", cmd_switches },
+	{ "tabletmode", cmd_tabletmode },
+	{ "temps", cmd_temperature },
+	{ "tempsinfo", cmd_temp_sensor_info },
+	{ "test", cmd_test },
+	{ "thermalget", cmd_thermal_get_threshold },
+	{ "thermalset", cmd_thermal_set_threshold },
+	{ "tpselftest", cmd_tp_self_test },
+	{ "tpframeget", cmd_tp_frame_get },
+	{ "tmp006cal", cmd_tmp006cal },
+	{ "tmp006raw", cmd_tmp006raw },
+	{ "typeccontrol", cmd_typec_control },
+	{ "typecdiscovery", cmd_typec_discovery },
+	{ "typecstatus", cmd_typec_status },
+	{ "typecvdmresponse", cmd_typec_vdm_response },
+	{ "uptimeinfo", cmd_uptimeinfo },
+	{ "usbchargemode", cmd_usb_charge_set_mode },
+	{ "usbmux", cmd_usb_mux },
+	{ "usbpd", cmd_usb_pd },
+	{ "usbpddps", cmd_usb_pd_dps },
+	{ "usbpdmuxinfo", cmd_usb_pd_mux_info },
+	{ "usbpdpower", cmd_usb_pd_power },
+	{ "version", cmd_version },
+	{ "waitevent", cmd_wait_event },
+	{ "wireless", cmd_wireless },
+	{ "reboot_ap_on_g3", cmd_reboot_ap_on_g3 },
+	{ NULL, NULL }
+};
+
+int main(int argc, char *argv[])
+{
+	const struct command *cmd;
+	int dev = 0;
+	int interfaces = COMM_ALL;
+	int i2c_bus = -1;
+	char device_name[41] = CROS_EC_DEV_NAME;
+	uint16_t vid = USB_VID_GOOGLE, pid = USB_PID_HAMMER;
+	int rv = 1;
+	int parse_error = 0;
+	char *e;
+	int i;
+
+	BUILD_ASSERT(ARRAY_SIZE(lb_command_paramcount) == LIGHTBAR_NUM_CMDS);
+
+	while ((i = getopt_long(argc, argv, "?", long_opts, NULL)) != -1) {
+		switch (i) {
+		case '?':
+			/* Unhandled option */
+			parse_error = 1;
+			break;
+
+		case OPT_DEV:
+			dev = strtoull(optarg, &e, 0);
+			if (!*optarg || (e && *e)) {
+				fprintf(stderr, "Invalid --dev\n");
+				parse_error = 1;
+			}
+			break;
+
+		case OPT_INTERFACE:
+			if (!strcasecmp(optarg, "dev")) {
+				interfaces = COMM_DEV;
+			} else if (!strcasecmp(optarg, "lpc")) {
+				interfaces = COMM_LPC;
+			} else if (!strcasecmp(optarg, "i2c")) {
+				interfaces = COMM_I2C;
+			} else if (!strcasecmp(optarg, "servo")) {
+				interfaces = COMM_SERVO;
+			} else {
+				fprintf(stderr, "Invalid --interface\n");
+				parse_error = 1;
+			}
+			break;
+		case OPT_DEVICE:
+			if (parse_vidpid(optarg, &vid, &pid)) {
+				interfaces = COMM_USB;
+			} else {
+				fprintf(stderr, "Invalid --device\n");
+				parse_error = 1;
+			}
+			break;
+		case OPT_NAME:
+			strncpy(device_name, optarg, 40);
+			device_name[40] = '\0';
+			break;
+		case OPT_I2C_BUS:
+			i2c_bus = strtoull(optarg, &e, 0);
+			if (*optarg == '\0' || (e && *e != '\0') ||
+			    i2c_bus < 0) {
+				fprintf(stderr, "Invalid --i2c_bus\n");
+				parse_error = 1;
+			}
+			break;
+		case OPT_ASCII:
+			ascii_mode = 1;
+			break;
+		}
+	}
+
+	if (i2c_bus != -1) {
+		if (!(interfaces & COMM_I2C)) {
+			fprintf(stderr,
+				"--i2c_bus is specified, but --interface is set to something other than I2C\n");
+			parse_error = 1;
+		} else {
+			interfaces = COMM_I2C;
+		}
+	}
+
+	/* Must specify a command */
+	if (!parse_error && optind == argc)
+		parse_error = 1;
+
+	/* 'ectool help' prints help with commands */
+	if (!parse_error && !strcasecmp(argv[optind], "help")) {
+		print_help(argv[0], 1);
+		exit(1);
+	}
+
+	/* Handle sub-devices command offset */
+	if (dev > 0 && dev < 4) {
+		set_command_offset(EC_CMD_PASSTHRU_OFFSET(dev));
+	} else if (dev == 8) {
+		/* Special offset for Fingerprint MCU */
+		strcpy(device_name, "cros_fp");
+	} else if (dev != 0) {
+		fprintf(stderr, "Bad device number %d\n", dev);
+		parse_error = 1;
+	}
+
+	if (parse_error) {
+		print_help(argv[0], 0);
+		exit(1);
+	}
+
+	/* Prefer /dev method, which supports built-in mutex */
+	if (!(interfaces & COMM_DEV) || comm_init_dev(device_name)) {
+		/* If dev is excluded or isn't supported, find alternative */
+
+		/* Lock is not needed for COMM_USB */
+		if (!(interfaces & COMM_USB) &&
+		    acquire_gec_lock(GEC_LOCK_TIMEOUT_SECS) < 0) {
+			fprintf(stderr, "Could not acquire GEC lock.\n");
+			exit(1);
+		}
+		if (interfaces == COMM_USB) {
+			if (comm_init_usb(vid, pid)) {
+				fprintf(stderr, "Couldn't find EC on USB.\n");
+				goto out;
+			}
+		} else if (comm_init_alt(interfaces, device_name, i2c_bus)) {
+			fprintf(stderr, "Couldn't find EC\n");
+			goto out;
+		}
+	}
+
+	if (comm_init_buffer()) {
+		fprintf(stderr, "Couldn't initialize buffers\n");
+		goto out;
+	}
+
+	/* Handle commands */
+	for (cmd = commands; cmd->name; cmd++) {
+		if (!strcasecmp(argv[optind], cmd->name)) {
+			rv = cmd->handler(argc - optind, argv + optind);
+			goto out;
+		}
+	}
+
+	/* If we're still here, command was unknown */
+	fprintf(stderr, "Unknown command '%s'\n\n", argv[optind]);
+	print_help(argv[0], 0);
+
+out:
+	release_gec_lock();
+
+	if (interfaces == COMM_USB)
+		comm_usb_exit();
+
+	return !!rv;
+}
diff --git a/util/ectool.h b/util/ectool.h
index c47edbf27c..3b398af273 100644
--- a/util/ectool.h
+++ b/util/ectool.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -40,3 +40,12 @@ struct command {
  * The key matrix is read from the fdt.
  */
 int cmd_keyscan(int argc, char *argv[]);
+
+/* ASCII mode for printing, default off */
+extern int ascii_mode;
+
+int cmd_i2c_protect(int argc, char *argv[]);
+int cmd_i2c_read(int argc, char *argv[]);
+int cmd_i2c_speed(int argc, char *argv[]);
+int cmd_i2c_write(int argc, char *argv[]);
+int cmd_i2c_xfer(int argc, char *argv[]);
diff --git a/util/ectool_i2c.cc b/util/ectool_i2c.cc
new file mode 100644
index 0000000000..1ed4576127
--- /dev/null
+++ b/util/ectool_i2c.cc
@@ -0,0 +1,407 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "comm-host.h"
+#include "ectool.h"
+
+#include <ctype.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <endian.h>
+
+int cmd_i2c_protect(int argc, char *argv[])
+{
+	struct ec_params_i2c_passthru_protect p;
+	char *e;
+	int rv;
+
+	if (argc != 2 && (argc != 3 || strcmp(argv[2], "status"))) {
+		fprintf(stderr, "Usage: %s <port> [status]\n", argv[0]);
+		return -1;
+	}
+
+	p.port = strtol(argv[1], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad port.\n");
+		return -1;
+	}
+
+	if (argc == 3) {
+		struct ec_response_i2c_passthru_protect r;
+
+		p.subcmd = EC_CMD_I2C_PASSTHRU_PROTECT_STATUS;
+
+		rv = ec_command(EC_CMD_I2C_PASSTHRU_PROTECT, 0, &p, sizeof(p),
+				&r, sizeof(r));
+
+		if (rv < 0)
+			return rv;
+
+		printf("I2C port %d: %s (%d)\n", p.port,
+		       r.status ? "Protected" : "Unprotected", r.status);
+	} else {
+		p.subcmd = EC_CMD_I2C_PASSTHRU_PROTECT_ENABLE;
+
+		rv = ec_command(EC_CMD_I2C_PASSTHRU_PROTECT, 0, &p, sizeof(p),
+				NULL, 0);
+
+		if (rv < 0)
+			return rv;
+	}
+	return 0;
+}
+
+static int do_i2c_xfer(unsigned int port, unsigned int addr, uint8_t *write_buf,
+		       int write_len, uint8_t **read_buf, int read_len)
+{
+	struct ec_params_i2c_passthru *p =
+		(struct ec_params_i2c_passthru *)ec_outbuf;
+	struct ec_response_i2c_passthru *r =
+		(struct ec_response_i2c_passthru *)ec_inbuf;
+	struct ec_params_i2c_passthru_msg *msg = p->msg;
+	uint8_t *pdata;
+	int size;
+	int rv;
+
+	p->port = port;
+	p->num_msgs = (read_len != 0) + (write_len != 0);
+
+	size = sizeof(*p) + p->num_msgs * sizeof(*msg);
+	if (size + write_len > ec_max_outsize) {
+		fprintf(stderr, "Params too large for buffer\n");
+		return -1;
+	}
+	if (sizeof(*r) + read_len > ec_max_insize) {
+		fprintf(stderr, "Read length too big for buffer\n");
+		return -1;
+	}
+
+	pdata = (uint8_t *)p + size;
+	if (write_len) {
+		msg->addr_flags = addr;
+		msg->len = write_len;
+
+		memcpy(pdata, write_buf, write_len);
+		msg++;
+	}
+
+	if (read_len) {
+		msg->addr_flags = addr | EC_I2C_FLAG_READ;
+		msg->len = read_len;
+	}
+
+	rv = ec_command(EC_CMD_I2C_PASSTHRU, 0, p, size + write_len, r,
+			sizeof(*r) + read_len);
+	if (rv < 0)
+		return rv;
+
+	/* Parse response */
+	if (r->i2c_status & (EC_I2C_STATUS_NAK | EC_I2C_STATUS_TIMEOUT)) {
+		fprintf(stderr, "Transfer failed with status=0x%x\n",
+			r->i2c_status);
+		return -1;
+	}
+
+	if (rv < sizeof(*r) + read_len) {
+		fprintf(stderr, "Truncated read response\n");
+		return -1;
+	}
+
+	if (read_len)
+		*read_buf = r->data;
+
+	return 0;
+}
+
+static void cmd_i2c_help(void)
+{
+	fprintf(stderr,
+		"  Usage: i2cread <8 | 16> <port> <addr8> <offset>\n"
+		"  Usage: i2cspeed <port> [speed in kHz]\n"
+		"  Usage: i2cwrite <8 | 16> <port> <addr8> <offset> <data>\n"
+		"  Usage: i2cxfer <port> <addr7> <read_count> [bytes...]\n"
+		"    <port> i2c port number\n"
+		"    <addr8> 8-bit i2c address\n"
+		"    <addr7> 7-bit i2c address\n"
+		"    <offset> offset to read from or write to\n"
+		"    <data> data to write\n"
+		"    <read_count> number of bytes to read\n"
+		"    [bytes ...] data to write\n");
+}
+
+int cmd_i2c_read(int argc, char *argv[])
+{
+	unsigned int port, addr8, addr7;
+	int read_len, write_len;
+	uint8_t write_buf[1];
+	uint8_t *read_buf = NULL;
+	char *e;
+	int rv;
+
+	if (argc != 5) {
+		cmd_i2c_help();
+		return -1;
+	}
+
+	read_len = strtol(argv[1], &e, 0);
+	if ((e && *e) || (read_len != 8 && read_len != 16)) {
+		fprintf(stderr, "Bad read size.\n");
+		return -1;
+	}
+	read_len = read_len / 8;
+
+	port = strtol(argv[2], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad port.\n");
+		return -1;
+	}
+
+	addr8 = strtol(argv[3], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad address.\n");
+		return -1;
+	}
+	addr7 = addr8 >> 1;
+
+	write_buf[0] = strtol(argv[4], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad offset.\n");
+		return -1;
+	}
+	write_len = 1;
+
+	rv = do_i2c_xfer(port, addr7, write_buf, write_len, &read_buf,
+			 read_len);
+
+	if (rv < 0)
+		return rv;
+
+	printf("Read from I2C port %d at 0x%x offset 0x%x = 0x%x\n", port,
+	       addr8, write_buf[0], *(uint16_t *)read_buf);
+	return 0;
+}
+
+int cmd_i2c_write(int argc, char *argv[])
+{
+	unsigned int port, addr8, addr7;
+	int write_len;
+	uint8_t write_buf[3];
+	char *e;
+	int rv;
+
+	if (argc != 6) {
+		cmd_i2c_help();
+		return -1;
+	}
+
+	write_len = strtol(argv[1], &e, 0);
+	if ((e && *e) || (write_len != 8 && write_len != 16)) {
+		fprintf(stderr, "Bad write size.\n");
+		return -1;
+	}
+	/* Include offset (length 1) */
+	write_len = 1 + write_len / 8;
+
+	port = strtol(argv[2], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad port.\n");
+		return -1;
+	}
+
+	addr8 = strtol(argv[3], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad address.\n");
+		return -1;
+	}
+	addr7 = addr8 >> 1;
+
+	write_buf[0] = strtol(argv[4], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad offset.\n");
+		return -1;
+	}
+
+	*((uint16_t *)&write_buf[1]) = strtol(argv[5], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad data.\n");
+		return -1;
+	}
+
+	rv = do_i2c_xfer(port, addr7, write_buf, write_len, NULL, 0);
+
+	if (rv < 0)
+		return rv;
+
+	printf("Wrote 0x%x to I2C port %d at 0x%x offset 0x%x.\n",
+	       *((uint16_t *)&write_buf[1]), port, addr8, write_buf[0]);
+	return 0;
+}
+
+int cmd_i2c_xfer(int argc, char *argv[])
+{
+	unsigned int port, addr;
+	int read_len, write_len;
+	uint8_t *write_buf = NULL;
+	uint8_t *read_buf;
+	char *e;
+	int rv, i;
+
+	if (argc < 4) {
+		cmd_i2c_help();
+		return -1;
+	}
+
+	port = strtol(argv[1], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad port.\n");
+		return -1;
+	}
+
+	addr = strtol(argv[2], &e, 0) & 0x7f;
+	if (e && *e) {
+		fprintf(stderr, "Bad peripheral address.\n");
+		return -1;
+	}
+
+	read_len = strtol(argv[3], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad read length.\n");
+		return -1;
+	}
+
+	/* Skip over params to bytes to write */
+	argc -= 4;
+	argv += 4;
+	write_len = argc;
+
+	if (write_len) {
+		write_buf = (uint8_t *)(malloc(write_len));
+		if (write_buf == NULL)
+			return -1;
+		for (i = 0; i < write_len; i++) {
+			write_buf[i] = strtol(argv[i], &e, 0);
+			if (e && *e) {
+				fprintf(stderr, "Bad write byte %d\n", i);
+				free(write_buf);
+				return -1;
+			}
+		}
+	}
+
+	rv = do_i2c_xfer(port, addr, write_buf, write_len, &read_buf, read_len);
+
+	if (write_len)
+		free(write_buf);
+
+	if (rv)
+		return rv;
+
+	if (read_len) {
+		if (ascii_mode) {
+			for (i = 0; i < read_len; i++)
+				printf(isprint(read_buf[i]) ? "%c" : "\\x%02x",
+				       read_buf[i]);
+		} else {
+			printf("Read bytes:");
+			for (i = 0; i < read_len; i++)
+				printf(" %#02x", read_buf[i]);
+		}
+		printf("\n");
+	} else {
+		printf("Write successful.\n");
+	}
+
+	return 0;
+}
+
+static int i2c_get(int port)
+{
+	struct ec_params_i2c_control p;
+	struct ec_response_i2c_control r;
+	uint16_t speed_khz;
+	int rv;
+
+	memset(&p, 0, sizeof(p));
+	p.port = port;
+	p.cmd = EC_I2C_CONTROL_GET_SPEED;
+
+	rv = ec_command(EC_CMD_I2C_CONTROL, 0, &p, sizeof(p), &r, sizeof(r));
+	if (rv < 0)
+		return rv;
+
+	speed_khz = r.cmd_response.speed_khz;
+	if (speed_khz == EC_I2C_CONTROL_SPEED_UNKNOWN)
+		printf("I2C port %d: speed: unknown\n", port);
+	else
+		printf("I2C port %d: speed: %u kHz\n", port, speed_khz);
+
+	return 0;
+}
+
+static int i2c_set(int port, int new_speed_khz)
+{
+	struct ec_params_i2c_control p;
+	struct ec_response_i2c_control r;
+	uint16_t old_speed_khz;
+	int rv;
+
+	if ((new_speed_khz == EC_I2C_CONTROL_SPEED_UNKNOWN) ||
+	    (new_speed_khz < 0 || new_speed_khz > UINT16_MAX)) {
+		fprintf(stderr, "I2C speed %d kHz is not supported\n",
+			new_speed_khz);
+		return -1;
+	}
+
+	memset(&p, 0, sizeof(p));
+	p.port = port;
+	p.cmd = EC_I2C_CONTROL_SET_SPEED;
+	p.cmd_params.speed_khz = new_speed_khz;
+
+	rv = ec_command(EC_CMD_I2C_CONTROL, 0, &p, sizeof(p), &r, sizeof(r));
+	if (rv < 0)
+		return rv;
+
+	old_speed_khz = r.cmd_response.speed_khz;
+	if (old_speed_khz == EC_I2C_CONTROL_SPEED_UNKNOWN) {
+		printf("Port %d speed set to %d kHz\n", port, new_speed_khz);
+	} else {
+		printf("Port %d speed changed from %u kHz to %d kHz\n", port,
+		       old_speed_khz, new_speed_khz);
+	}
+
+	return 0;
+}
+
+int cmd_i2c_speed(int argc, char *argv[])
+{
+	unsigned int port, speed;
+	char *e;
+
+	if (argc < 2 || argc > 3) {
+		cmd_i2c_help();
+		return -1;
+	}
+
+	port = strtol(argv[1], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad port.\n");
+		return -1;
+	}
+
+	if (argc == 2)
+		return i2c_get(port);
+
+	speed = strtol(argv[2], &e, 0);
+	if (e && *e) {
+		fprintf(stderr, "Bad speed. "
+				"Typical speeds are one of {100,400,1000}.\n");
+		return -1;
+	}
+
+	return i2c_set(port, speed);
+}
diff --git a/util/ectool_keyscan.c b/util/ectool_keyscan.c
deleted file mode 100644
index 293857285a..0000000000
--- a/util/ectool_keyscan.c
+++ /dev/null
@@ -1,678 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <fcntl.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <termios.h>
-#include <unistd.h>
-#include <sys/stat.h>
-#include <endian.h>
-
-#include "comm-host.h"
-#include "keyboard_config.h"
-#include "ectool.h"
-
-enum {
-	/* Alloc this many more scans when needed */
-	KEYSCAN_ALLOC_STEP	= 64,
-	KEYSCAN_MAX_TESTS	= 10,	/* Maximum number of tests supported */
-	KEYSCAN_MAX_INPUT_LEN	= 20,	/* Maximum characters we can receive */
-};
-
-/* A single entry of the key matrix */
-struct matrix_entry {
-	int row;	/* key matrix row */
-	int col;	/* key matrix column */
-	int keycode;	/* corresponding linux key code */
-};
-
-struct keyscan_test_item {
-	uint32_t beat;			/* Beat number */
-	uint8_t scan[KEYBOARD_COLS_MAX];	/* Scan data */
-};
-
-/* A single test, consisting of a list of key scans and expected ascii input */
-struct keyscan_test {
-	char *name;		/* name of test */
-	char *expect;		/* resulting input we expect to see */
-	int item_count;		/* number of items in data */
-	int item_alloced;	/* number of items alloced in data */
-	struct keyscan_test_item *items;	/* key data for EC */
-};
-
-/* A list of tests that we can run */
-struct keyscan_info {
-	unsigned int beat_us;	/* length of each beat in microseconds */
-	struct keyscan_test tests[KEYSCAN_MAX_TESTS];	/* the tests */
-	int test_count;		/* number of tests */
-	struct matrix_entry *matrix;	/* the key matrix info */
-	int matrix_count;	/* number of keys in matrix */
-};
-
-/**
- * Read the key matrix from the device tree
- *
- * Keymap entries in the fdt take the form of 0xRRCCKKKK where
- * RR=Row CC=Column KKKK=Key Code
- *
- * @param keyscan	keyscan information
- * @param path		path to device tree file containing data
- * @return 0 if ok, -1 on error
- */
-static int keyscan_read_fdt_matrix(struct keyscan_info *keyscan,
-				   const char *path)
-{
-	struct stat buf;
-	uint32_t word;
-	int upto;
-	FILE *f;
-	int err;
-
-	/* Allocate memory for key matrix */
-	if (stat(path, &buf)) {
-		fprintf(stderr, "Cannot stat key matrix file '%s'\n", path);
-		return -1;
-	}
-	keyscan->matrix_count = buf.st_size / 4;
-	keyscan->matrix = calloc(keyscan->matrix_count,
-				 sizeof(*keyscan->matrix));
-	if (!keyscan->matrix) {
-		fprintf(stderr, "Out of memory for key matrix\n");
-		return -1;
-	}
-
-	f = fopen(path, "rb");
-	if (!f) {
-		fprintf(stderr, "Cannot open key matrix file '%s'\n", path);
-		return -1;
-	}
-
-	/* Now read the data */
-	upto = err = 0;
-	while (fread(&word, 1, sizeof(word), f) == sizeof(word)) {
-		struct matrix_entry *matrix = &keyscan->matrix[upto++];
-
-		word = be32toh(word);
-		matrix->row = word >> 24;
-		matrix->col = (word >> 16) & 0xff;
-		matrix->keycode = word & 0xffff;
-
-		/* Hard-code some limits for now */
-		if (matrix->row >= KEYBOARD_ROWS ||
-		    matrix->col >= KEYBOARD_COLS_MAX) {
-			fprintf(stderr, "Matrix pos out of range (%d,%d)\n",
-				matrix->row, matrix->col);
-			fclose(f);
-			return -1;
-		}
-	}
-	fclose(f);
-	if (!err && upto != keyscan->matrix_count) {
-		fprintf(stderr, "Read mismatch from matrix file '%s'\n", path);
-		err = -1;
-	}
-
-	return err;
-}
-
-/*
- * translate Linux's KEY_... values into ascii. We change space into 0xfe
- * since we use the numeric value (&32) for space. That avoids ambiguity
- * when we see a space in a key sequence file.
- */
-static const unsigned char kbd_plain_xlate[] = {
-	0xff, 0x1b, '1',  '2',  '3',  '4',  '5',  '6',
-	'7',  '8',  '9',  '0',  '-',  '=', '\b', '\t',	/* 0x00 - 0x0f */
-	'q',  'w',  'e',  'r',  't',  'y',  'u',  'i',
-	'o',  'p',  '[',  ']', '\r', 0xff,  'a',  's',  /* 0x10 - 0x1f */
-	'd',  'f',  'g',  'h',  'j',  'k',  'l',  ';',
-	'\'',  '`', 0xff, '\\', 'z',  'x',  'c',  'v',	/* 0x20 - 0x2f */
-	'b',  'n',  'm',  ',' ,  '.', '/', 0xff, 0xff, 0xff,
-	0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,	/* 0x30 - 0x3f */
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  '7',
-	'8',  '9',  '-',  '4',  '5',  '6',  '+',  '1',	/* 0x40 - 0x4f */
-	'2',  '3',  '0',  '.', 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,	/* 0x50 - 0x5F */
-	'\r', 0xff, 0xff
-};
-
-/**
- * Add a new key to a scan
- *
- * Given a new key, this looks it up in the matrix and adds it to the scan,
- * so that if this scan were reported by the EC, the AP would the given key.
- *
- * The format of keys is a list of ascii characters, or & followed by a numeric
- * ascii value, or * followed by a numeric keycode value. Spaces are ignored
- * (use '*32' for space).
- *
- * Examples:
- * a        - a
- * &20      - space
- * *58      - KEY_CAPSLOCK
- *
- * @param keyscan	keyscan information
- * @param keysp		point to the current key string on entry; on exit it
- *			is updated to point to just after the string, plus any
- *			following space
- * @param path		path to device tree file containing data
- * @return 0 if ok, -1 on error
- */
-static int keyscan_add_to_scan(struct keyscan_info *keyscan, char **keysp,
-			       uint8_t scan[])
-{
-	const uint8_t *pos;
-	struct matrix_entry *matrix;
-	int keycode = -1, i;
-	char *keys = *keysp;
-	int key = ' ';
-
-	if (*keys == '&') {
-		/* Numeric ascii code */
-		keys++;
-		key = strtol(keys, &keys, 10);
-		if (!key || keys == *keysp) {
-			fprintf(stderr, "Invalid numeric ascii\n");
-			return -1;
-		}
-		if (*keys == ' ')
-			keys++;
-		else if (*keys) {
-			fprintf(stderr, "Expect space after numeric ascii\n");
-			return -1;
-		}
-	} else if (*keys == '*') {
-		/* Numeric ascii code */
-		keys++;
-		keycode = strtol(keys, &keys, 10);
-		if (!keycode || keys == *keysp) {
-			fprintf(stderr, "Invalid numeric keycode\n");
-			return -1;
-		}
-		if (*keys == ' ')
-			keys++;
-		else if (*keys) {
-			fprintf(stderr, "Expect space after num. keycode\n");
-			return -1;
-		}
-	} else {
-		key = *keys++;
-	}
-
-	/* Convert keycode to key if needed */
-	if (keycode == -1) {
-		pos = strchr(kbd_plain_xlate, key);
-		if (!pos) {
-			fprintf(stderr, "Key '%c' not found in xlate table\n",
-				key);
-			return -1;
-		}
-		keycode = pos - kbd_plain_xlate;
-	}
-
-	/* Look up keycode in matrix */
-	for (i = 0, matrix = keyscan->matrix; i < keyscan->matrix_count;
-			i++, matrix++) {
-		if (matrix->keycode == keycode) {
-#ifdef DEBUG
-			printf("%d: %d,%d\n", matrix->keycode, matrix->row,
-			       matrix->col);
-#endif
-			scan[matrix->col] |= 1 << matrix->row;
-			*keysp = keys;
-			return 0;
-		}
-	}
-	fprintf(stderr, "Key '%c' (keycode %d) not found in matrix\n", key,
-		keycode);
-
-	return -1;
-}
-
-/**
- * Add a new keyscan to the given test
- *
- * This processes a new keyscan, consisting of a beat number and a sequence
- * of keys.
- *
- * The format of keys is a beat number followed by a list of keys, each
- * either ascii characters, or & followed by a numeric ascii value, or *
- * followed by a numeric keycode value. Spaces are ignored (use '*32' for
- * space).
- *
- * Examples:
- * 0 abc      - beat 0, press a, b and c
- * 4 a &20    - beat 4, press a and space
- * 8 *58 &13  - beat 8, press KEY_CAPSLOCK
- *
- * @param keyscan	keyscan information
- * @param linenum	line number we are reading from (for error reporting)
- * @param test		test to add this scan to
- * @param keys		key string to process
- * @return 0 if ok, -1 on error
- */
-static int keyscan_process_keys(struct keyscan_info *keyscan, int linenum,
-				struct keyscan_test *test, char *keys)
-{
-	struct keyscan_test_item *item;
-	unsigned long int beat;
-
-	/* Allocate more items if needed */
-	if (!test->item_alloced || test->item_count == test->item_alloced) {
-		int size, new_size;
-
-		size = test->item_alloced * sizeof(struct keyscan_test_item);
-		new_size = size + KEYSCAN_ALLOC_STEP *
-			sizeof(struct keyscan_test_item);
-		test->items = realloc(test->items, new_size);
-		if (!test->items) {
-			fprintf(stderr, "Out of memory realloc()\n");
-			return -1;
-		}
-		memset((char *)test->items + size, '\0', new_size - size);
-		test->item_alloced += KEYSCAN_ALLOC_STEP;
-		new_size = size;
-	}
-
-	/* read the beat number */
-	item = &test->items[test->item_count];
-	beat = strtol(keys, &keys, 10);
-	item->beat = beat;
-
-	/* Read keys and add them to our scan */
-	if (*keys == ' ') {
-		keys++;
-		while (*keys) {
-			if (keyscan_add_to_scan(keyscan, &keys, item->scan)) {
-				fprintf(stderr, "Line %d: Cannot parse"
-					" key input '%s'\n", linenum,
-					keys);
-				return -1;
-			}
-		}
-	} else if (*keys) {
-		fprintf(stderr, "Line %d: Need space after beat\n",
-			linenum);
-		return -1;
-	}
-	test->item_count++;
-
-	return 0;
-}
-
-/* These are the commands we understand in a key sequence file */
-enum keyscan_cmd {
-	KEYSCAN_CMD_TEST,	/* start a new test */
-	KEYSCAN_CMD_ENDTEST,	/* end a test */
-	KEYSCAN_CMD_SEQ,	/* add a keyscan to a test sequence */
-	KEYSCAN_CMD_EXPECT,	/* indicate what input is expected */
-
-	KEYSCAN_CMD_COUNT
-};
-
-/* Names for each of the keyscan commands */
-static const char *keyscan_cmd_name[KEYSCAN_CMD_COUNT] = {
-	"test",
-	"endtest",
-	"seq",
-	"expect",
-};
-
-/**
- * Read a command from a string and return it
- *
- * @param str	String containing command
- * @param len	Length of command string
- * @return detected command, or -1 if none
- */
-static enum keyscan_cmd keyscan_read_cmd(const char *str, int len)
-{
-	int i;
-
-	for (i = 0; i < KEYSCAN_CMD_COUNT; i++) {
-		if (!strncmp(keyscan_cmd_name[i], str, len))
-			return i;
-	}
-
-	return -1;
-}
-
-/**
- * Process a key sequence file a build up a list of tets from it
- *
- * @param f		File containing keyscan info
- * @param keyscan	keyscan information
- * @return 0 if ok, -1 on error
- */
-static int keyscan_process_file(FILE *f, struct keyscan_info *keyscan)
-{
-	struct keyscan_test *cur_test;
-	char line[256];
-	char *str;
-	int linenum;
-
-	keyscan->test_count = 0;
-
-	linenum = 0;
-	cur_test = NULL;
-	while (str = fgets(line, sizeof(line), f), str) {
-		char *args, *end;
-		int cmd, len;
-
-		linenum++;
-		len = strlen(str);
-
-		/* chomp the trailing newline */
-		if (len > 0 && str[len - 1] == '\n') {
-			len--;
-			str[len] = '\0';
-		}
-
-		/* deal with blank lines and comments */
-		if (!len || *str == '#')
-			continue;
-
-		/* get the command */
-		for (end = str; *end && *end != ' '; end++)
-			;
-
-		cmd = keyscan_read_cmd(str, end - str);
-		args = end + (*end != '\0');
-		switch (cmd) {
-		case KEYSCAN_CMD_TEST:
-			/* Start a new test */
-			if (keyscan->test_count == KEYSCAN_MAX_TESTS) {
-				fprintf(stderr, "KEYSCAN_MAX_TESTS "
-					"exceeded\n");
-				return -1;
-			}
-			cur_test = &keyscan->tests[keyscan->test_count];
-			cur_test->name = strdup(args);
-			if (!cur_test->name) {
-				fprintf(stderr, "Line %d: out of memory\n",
-					linenum);
-			}
-			break;
-		case KEYSCAN_CMD_EXPECT:
-			/* Get expect string */
-			if (!cur_test) {
-				fprintf(stderr, "Line %d: expect should be "
-					"inside test\n", linenum);
-				return -1;
-			}
-			cur_test->expect = strdup(args);
-			if (!cur_test->expect) {
-				fprintf(stderr, "Line %d: out of memory\n",
-					linenum);
-			}
-			break;
-		case KEYSCAN_CMD_ENDTEST:
-			/* End of a test */
-			keyscan->test_count++;
-			cur_test = NULL;
-			break;
-		case KEYSCAN_CMD_SEQ:
-			if (keyscan_process_keys(keyscan, linenum, cur_test,
-					args)) {
-				fprintf(stderr, "Line %d: Cannot parse key "
-					"input '%s'\n", linenum, args);
-				return -1;
-			}
-			break;
-		default:
-			fprintf(stderr, "Line %d: Uknown command '%1.*s'\n",
-				linenum, (int)(end - str), str);
-			return -1;
-		}
-	}
-
-	return 0;
-}
-
-/**
- * Print out a list of all tests
- *
- * @param keyscan	keyscan information
- */
-static void keyscan_print(struct keyscan_info *keyscan)
-{
-	int testnum;
-	int i;
-
-	for (testnum = 0; testnum < keyscan->test_count; testnum++) {
-		struct keyscan_test *test = &keyscan->tests[testnum];
-
-		printf("Test: %s\n", test->name);
-		for (i = 0; i < test->item_count; i++) {
-			struct keyscan_test_item *item;
-			int j;
-
-			item = &test->items[i];
-			printf("%2d  %7d:  ", i, item->beat);
-			for (j = 0; j < sizeof(item->scan); j++)
-				printf("%02x ", item->scan[j]);
-			printf("\n");
-		}
-		printf("\n");
-	}
-}
-
-/**
- * Set the terminal to raw mode, or cooked
- *
- * @param tty_fd	Terminal file descriptor to change
- * @Param raw		0 for cooked, non-zero for raw
- */
-static void set_to_raw(int tty_fd, int raw)
-{
-	struct termios tty_attr;
-	int value;
-
-	value = fcntl(tty_fd, F_GETFL);
-
-	tcgetattr(tty_fd, &tty_attr);
-	if (raw) {
-		tty_attr.c_lflag &= ~ICANON;
-		value |= O_NONBLOCK;
-	} else {
-		tty_attr.c_lflag |= ICANON;
-		value &= ~O_NONBLOCK;
-	}
-	tcsetattr(tty_fd, TCSANOW, &tty_attr);
-	fcntl(tty_fd, F_SETFL, value);
-}
-
-/**
- * Read input for a whlie until wee see no more
- *
- * @param fd		File descriptor for input
- * @param input		Place to put input string
- * @param max_len	Maximum length of input string
- * @param wait		Number of microseconds to wait for input
- */
-static void keyscan_get_input(int fd, char *input, int max_len, int wait)
-{
-	int len;
-
-	usleep(wait);
-	input[0] = '\0';
-	len = read(fd, input, max_len - 1);
-	if (len > 0)
-		input[len] = '\0';
-}
-
-static int keyscan_send_sequence(struct keyscan_info *keyscan,
-				 struct keyscan_test *test)
-{
-	struct ec_params_keyscan_seq_ctrl *req;
-	struct keyscan_test_item *item;
-	int upto, size, rv;
-
-	size = sizeof(*req) + sizeof(item->scan);
-	req = (struct ec_params_keyscan_seq_ctrl *)malloc(size);
-	if (!req) {
-		fprintf(stderr, "Out of memory for message\n");
-		return -1;
-	}
-	for (upto = rv = 0, item = test->items; rv >= 0 &&
-			upto < test->item_count; upto++, item++) {
-		req->cmd = EC_KEYSCAN_SEQ_ADD;
-		req->add.time_us = item->beat * keyscan->beat_us;
-		memcpy(req->add.scan, item->scan, sizeof(item->scan));
-		rv = ec_command(EC_CMD_KEYSCAN_SEQ_CTRL, 0, req, size, NULL, 0);
-	}
-	free(req);
-	if (rv < 0)
-		return rv;
-
-	return 0;
-}
-
-/**
- * Run a single test
- *
- * @param keyscan	keyscan information
- * @param test		test to run
- * @return 0 if test passes, -ve if some error occurred
- */
-static int run_test(struct keyscan_info *keyscan, struct keyscan_test *test)
-{
-	struct ec_params_keyscan_seq_ctrl ctrl;
-	char input[KEYSCAN_MAX_INPUT_LEN];
-	struct ec_result_keyscan_seq_ctrl *resp;
-	int wait_us;
-	int size;
-	int rv;
-	int fd = 0;
-	int i;
-
-	/* First clear the sequence */
-	ctrl.cmd = EC_KEYSCAN_SEQ_CLEAR;
-	rv = ec_command(EC_CMD_KEYSCAN_SEQ_CTRL, 0, &ctrl, sizeof(ctrl),
-			NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	rv = keyscan_send_sequence(keyscan, test);
-	if (rv < 0)
-		return rv;
-
-	/* Start it */
-	set_to_raw(fd, 1);
-	ctrl.cmd = EC_KEYSCAN_SEQ_START;
-	rv = ec_command(EC_CMD_KEYSCAN_SEQ_CTRL, 0, &ctrl, sizeof(ctrl),
-			NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	/* Work out how long we need to wait */
-	wait_us = 100 * 1000;	/* Wait 100ms to at least */
-	if (test->item_count) {
-		struct keyscan_test_item *ksi;
-
-		ksi = &test->items[test->item_count - 1];
-		wait_us += ksi->beat * keyscan->beat_us;
-	}
-
-	/* Wait for input */
-	keyscan_get_input(fd, input, sizeof(input), wait_us);
-	set_to_raw(fd, 0);
-
-	/* Ask EC for results */
-	size = sizeof(*resp) + test->item_count;
-	resp = malloc(size);
-	if (!resp) {
-		fprintf(stderr, "Out of memory for results\n");
-		return -1;
-	}
-	ctrl.cmd = EC_KEYSCAN_SEQ_COLLECT;
-	ctrl.collect.start_item = 0;
-	ctrl.collect.num_items = test->item_count;
-	rv = ec_command(EC_CMD_KEYSCAN_SEQ_CTRL, 0, &ctrl, sizeof(ctrl),
-			resp, size);
-	if (rv < 0)
-		return rv;
-
-	/* Check what scans were skipped */
-	for (i = 0; i < resp->collect.num_items; i++) {
-		struct ec_collect_item *item;
-		struct keyscan_test_item *ksi;
-
-		item = &resp->collect.item[i];
-		ksi = &test->items[i];
-		if (!(item->flags & EC_KEYSCAN_SEQ_FLAG_DONE))
-			printf(" [skip %d at beat %u] ", i, ksi->beat);
-	}
-
-	if (strcmp(input, test->expect)) {
-		printf("Expected '%s', got '%s' ", test->expect, input);
-		return -1;
-	}
-
-	return 0;
-}
-
-/**
- * Run all tests
- *
- * @param keyscan	keyscan information
- * @return 0 if ok, -1 on error
- */
-static int keyscan_run_tests(struct keyscan_info *keyscan)
-{
-	int testnum;
-	int any_err = 0;
-
-	for (testnum = 0; testnum < keyscan->test_count; testnum++) {
-		struct keyscan_test *test = &keyscan->tests[testnum];
-		int err;
-
-		fflush(stdout);
-		err = run_test(keyscan, test);
-		any_err |= err;
-		if (err) {
-			printf("%d: %s:  : FAIL\n", testnum, test->name);
-		}
-	}
-
-	return any_err ? -1 : 0;
-}
-
-int cmd_keyscan(int argc, char *argv[])
-{
-	struct keyscan_info keyscan;
-	FILE *f;
-	int err;
-
-	argc--;
-	argv++;
-	if (argc < 2) {
-		fprintf(stderr, "Must specify beat period and filename\n");
-		return -1;
-	}
-	memset(&keyscan, '\0', sizeof(keyscan));
-	keyscan.beat_us = atoi(argv[0]);
-	if (keyscan.beat_us < 100)
-		fprintf(stderr, "Warning: beat period is normally > 100us\n");
-	f = fopen(argv[1], "r");
-	if (!f) {
-		perror("Cannot open file\n");
-		return -1;
-	}
-
-	/* TODO(crosbug.com/p/23826): Read key matrix from fdt */
-	err = keyscan_read_fdt_matrix(&keyscan, "test/test-matrix.bin");
-	if (!err)
-		err = keyscan_process_file(f, &keyscan);
-	if (!err)
-		keyscan_print(&keyscan);
-	if (!err)
-		err = keyscan_run_tests(&keyscan);
-	fclose(f);
-
-	return err;
-}
diff --git a/util/ectool_keyscan.cc b/util/ectool_keyscan.cc
new file mode 100644
index 0000000000..8166703a07
--- /dev/null
+++ b/util/ectool_keyscan.cc
@@ -0,0 +1,684 @@
+/* Copyright 2012 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "comm-host.h"
+#include "ectool.h"
+#include "keyboard_config.h"
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <endian.h>
+#include <fcntl.h>
+#include <sys/stat.h>
+#include <termios.h>
+#include <unistd.h>
+
+enum {
+	/* Alloc this many more scans when needed */
+	KEYSCAN_ALLOC_STEP = 64,
+	KEYSCAN_MAX_TESTS = 10, /* Maximum number of tests supported */
+	KEYSCAN_MAX_INPUT_LEN = 20, /* Maximum characters we can receive */
+};
+
+/* A single entry of the key matrix */
+struct matrix_entry {
+	int row; /* key matrix row */
+	int col; /* key matrix column */
+	int keycode; /* corresponding linux key code */
+};
+
+struct keyscan_test_item {
+	uint32_t beat; /* Beat number */
+	uint8_t scan[KEYBOARD_COLS_MAX]; /* Scan data */
+};
+
+/* A single test, consisting of a list of key scans and expected ascii input */
+struct keyscan_test {
+	char *name; /* name of test */
+	char *expect; /* resulting input we expect to see */
+	int item_count; /* number of items in data */
+	int item_alloced; /* number of items alloced in data */
+	struct keyscan_test_item *items; /* key data for EC */
+};
+
+/* A list of tests that we can run */
+struct keyscan_info {
+	unsigned int beat_us; /* length of each beat in microseconds */
+	struct keyscan_test tests[KEYSCAN_MAX_TESTS]; /* the tests */
+	int test_count; /* number of tests */
+	struct matrix_entry *matrix; /* the key matrix info */
+	int matrix_count; /* number of keys in matrix */
+};
+
+/**
+ * Read the key matrix from the device tree
+ *
+ * Keymap entries in the fdt take the form of 0xRRCCKKKK where
+ * RR=Row CC=Column KKKK=Key Code
+ *
+ * @param keyscan	keyscan information
+ * @param path		path to device tree file containing data
+ * @return 0 if ok, -1 on error
+ */
+static int keyscan_read_fdt_matrix(struct keyscan_info *keyscan,
+				   const char *path)
+{
+	struct stat buf;
+	uint32_t word;
+	int upto;
+	FILE *f;
+	int err;
+
+	/* Allocate memory for key matrix */
+	if (stat(path, &buf)) {
+		fprintf(stderr, "Cannot stat key matrix file '%s'\n", path);
+		return -1;
+	}
+	keyscan->matrix_count = buf.st_size / 4;
+	keyscan->matrix = (struct matrix_entry *)(calloc(
+		keyscan->matrix_count, sizeof(*keyscan->matrix)));
+	if (!keyscan->matrix) {
+		fprintf(stderr, "Out of memory for key matrix\n");
+		return -1;
+	}
+
+	f = fopen(path, "rb");
+	if (!f) {
+		fprintf(stderr, "Cannot open key matrix file '%s'\n", path);
+		return -1;
+	}
+
+	/* Now read the data */
+	upto = err = 0;
+	while (fread(&word, 1, sizeof(word), f) == sizeof(word)) {
+		struct matrix_entry *matrix = &keyscan->matrix[upto++];
+
+		word = be32toh(word);
+		matrix->row = word >> 24;
+		matrix->col = (word >> 16) & 0xff;
+		matrix->keycode = word & 0xffff;
+
+		/* Hard-code some limits for now */
+		if (matrix->row >= KEYBOARD_ROWS ||
+		    matrix->col >= KEYBOARD_COLS_MAX) {
+			fprintf(stderr, "Matrix pos out of range (%d,%d)\n",
+				matrix->row, matrix->col);
+			fclose(f);
+			return -1;
+		}
+	}
+	fclose(f);
+	if (!err && upto != keyscan->matrix_count) {
+		fprintf(stderr, "Read mismatch from matrix file '%s'\n", path);
+		err = -1;
+	}
+
+	return err;
+}
+
+/*
+ * translate Linux's KEY_... values into ascii. We change space into 0xfe
+ * since we use the numeric value (&32) for space. That avoids ambiguity
+ * when we see a space in a key sequence file.
+ */
+static const unsigned char kbd_plain_xlate[] = {
+	0xff, 0x1b, '1',  '2',	'3',  '4',  '5',  '6',
+	'7',  '8',  '9',  '0',	'-',  '=',  '\b', '\t', /* 0x00 - 0x0f */
+	'q',  'w',  'e',  'r',	't',  'y',  'u',  'i',
+	'o',  'p',  '[',  ']',	'\r', 0xff, 'a',  's', /* 0x10 - 0x1f */
+	'd',  'f',  'g',  'h',	'j',  'k',  'l',  ';',
+	'\'', '`',  0xff, '\\', 'z',  'x',  'c',  'v', /* 0x20 - 0x2f */
+	'b',  'n',  'm',  ',',	'.',  '/',  0xff, 0xff,
+	0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x30 - 0x3f */
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, '7',
+	'8',  '9',  '-',  '4',	'5',  '6',  '+',  '1', /* 0x40 - 0x4f */
+	'2',  '3',  '0',  '.',	0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x50 - 0x5F */
+	'\r', 0xff, 0xff, '\0'
+};
+
+/**
+ * Add a new key to a scan
+ *
+ * Given a new key, this looks it up in the matrix and adds it to the scan,
+ * so that if this scan were reported by the EC, the AP would the given key.
+ *
+ * The format of keys is a list of ascii characters, or & followed by a numeric
+ * ascii value, or * followed by a numeric keycode value. Spaces are ignored
+ * (use '*32' for space).
+ *
+ * Examples:
+ * a        - a
+ * &20      - space
+ * *58      - KEY_CAPSLOCK
+ *
+ * @param keyscan	keyscan information
+ * @param keysp		point to the current key string on entry; on exit it
+ *			is updated to point to just after the string, plus any
+ *			following space
+ * @param path		path to device tree file containing data
+ * @return 0 if ok, -1 on error
+ */
+static int keyscan_add_to_scan(struct keyscan_info *keyscan, char **keysp,
+			       uint8_t scan[])
+{
+	const uint8_t *pos;
+	struct matrix_entry *matrix;
+	int keycode = -1, i;
+	char *keys = *keysp;
+	int key = ' ';
+
+	if (*keys == '&') {
+		/* Numeric ascii code */
+		keys++;
+		key = strtol(keys, &keys, 10);
+		if (!key || keys == *keysp) {
+			fprintf(stderr, "Invalid numeric ascii\n");
+			return -1;
+		}
+		if (*keys == ' ')
+			keys++;
+		else if (*keys) {
+			fprintf(stderr, "Expect space after numeric ascii\n");
+			return -1;
+		}
+	} else if (*keys == '*') {
+		/* Numeric ascii code */
+		keys++;
+		keycode = strtol(keys, &keys, 10);
+		if (!keycode || keys == *keysp) {
+			fprintf(stderr, "Invalid numeric keycode\n");
+			return -1;
+		}
+		if (*keys == ' ')
+			keys++;
+		else if (*keys) {
+			fprintf(stderr, "Expect space after num. keycode\n");
+			return -1;
+		}
+	} else {
+		key = *keys++;
+	}
+
+	/* Convert keycode to key if needed */
+	if (keycode == -1) {
+		pos = (uint8_t *)(strchr((char *)kbd_plain_xlate, key));
+		if (!pos) {
+			fprintf(stderr, "Key '%c' not found in xlate table\n",
+				key);
+			return -1;
+		}
+		keycode = pos - kbd_plain_xlate;
+	}
+
+	/* Look up keycode in matrix */
+	for (i = 0, matrix = keyscan->matrix; i < keyscan->matrix_count;
+	     i++, matrix++) {
+		if (matrix->keycode == keycode) {
+#ifdef DEBUG
+			printf("%d: %d,%d\n", matrix->keycode, matrix->row,
+			       matrix->col);
+#endif
+			scan[matrix->col] |= 1 << matrix->row;
+			*keysp = keys;
+			return 0;
+		}
+	}
+	fprintf(stderr, "Key '%c' (keycode %d) not found in matrix\n", key,
+		keycode);
+
+	return -1;
+}
+
+/**
+ * Add a new keyscan to the given test
+ *
+ * This processes a new keyscan, consisting of a beat number and a sequence
+ * of keys.
+ *
+ * The format of keys is a beat number followed by a list of keys, each
+ * either ascii characters, or & followed by a numeric ascii value, or *
+ * followed by a numeric keycode value. Spaces are ignored (use '*32' for
+ * space).
+ *
+ * Examples:
+ * 0 abc      - beat 0, press a, b and c
+ * 4 a &20    - beat 4, press a and space
+ * 8 *58 &13  - beat 8, press KEY_CAPSLOCK
+ *
+ * @param keyscan	keyscan information
+ * @param linenum	line number we are reading from (for error reporting)
+ * @param test		test to add this scan to
+ * @param keys		key string to process
+ * @return 0 if ok, -1 on error
+ */
+static int keyscan_process_keys(struct keyscan_info *keyscan, int linenum,
+				struct keyscan_test *test, char *keys)
+{
+	struct keyscan_test_item *item;
+	unsigned long int beat;
+
+	/* Allocate more items if needed */
+	if (!test->item_alloced || test->item_count == test->item_alloced) {
+		int size, new_size;
+
+		size = test->item_alloced * sizeof(struct keyscan_test_item);
+		new_size = size + KEYSCAN_ALLOC_STEP *
+					  sizeof(struct keyscan_test_item);
+		test->items = (struct keyscan_test_item *)(realloc(test->items,
+								   new_size));
+		if (!test->items) {
+			fprintf(stderr, "Out of memory realloc()\n");
+			return -1;
+		}
+		memset((char *)test->items + size, '\0', new_size - size);
+		test->item_alloced += KEYSCAN_ALLOC_STEP;
+		new_size = size;
+	}
+
+	/* read the beat number */
+	item = &test->items[test->item_count];
+	beat = strtol(keys, &keys, 10);
+	item->beat = beat;
+
+	/* Read keys and add them to our scan */
+	if (*keys == ' ') {
+		keys++;
+		while (*keys) {
+			if (keyscan_add_to_scan(keyscan, &keys, item->scan)) {
+				fprintf(stderr,
+					"Line %d: Cannot parse"
+					" key input '%s'\n",
+					linenum, keys);
+				return -1;
+			}
+		}
+	} else if (*keys) {
+		fprintf(stderr, "Line %d: Need space after beat\n", linenum);
+		return -1;
+	}
+	test->item_count++;
+
+	return 0;
+}
+
+/* These are the commands we understand in a key sequence file */
+enum keyscan_cmd {
+	KEYSCAN_CMD_TEST, /* start a new test */
+	KEYSCAN_CMD_ENDTEST, /* end a test */
+	KEYSCAN_CMD_SEQ, /* add a keyscan to a test sequence */
+	KEYSCAN_CMD_EXPECT, /* indicate what input is expected */
+
+	KEYSCAN_CMD_COUNT
+};
+
+/* Names for each of the keyscan commands */
+static const char *keyscan_cmd_name[KEYSCAN_CMD_COUNT] = {
+	"test",
+	"endtest",
+	"seq",
+	"expect",
+};
+
+/**
+ * Read a command from a string and return it
+ *
+ * @param str	String containing command
+ * @param len	Length of command string
+ * @return detected command, or -1 if none
+ */
+static enum keyscan_cmd keyscan_read_cmd(const char *str, int len)
+{
+	int i;
+
+	for (i = 0; i < KEYSCAN_CMD_COUNT; i++) {
+		if (!strncmp(keyscan_cmd_name[i], str, len))
+			return (enum keyscan_cmd)(i);
+	}
+
+	return (enum keyscan_cmd)(-1);
+}
+
+/**
+ * Process a key sequence file a build up a list of tets from it
+ *
+ * @param f		File containing keyscan info
+ * @param keyscan	keyscan information
+ * @return 0 if ok, -1 on error
+ */
+static int keyscan_process_file(FILE *f, struct keyscan_info *keyscan)
+{
+	struct keyscan_test *cur_test;
+	char line[256];
+	char *str;
+	int linenum;
+
+	keyscan->test_count = 0;
+
+	linenum = 0;
+	cur_test = NULL;
+	while (str = fgets(line, sizeof(line), f), str) {
+		char *args, *end;
+		int cmd, len;
+
+		linenum++;
+		len = strlen(str);
+
+		/* chomp the trailing newline */
+		if (len > 0 && str[len - 1] == '\n') {
+			len--;
+			str[len] = '\0';
+		}
+
+		/* deal with blank lines and comments */
+		if (!len || *str == '#')
+			continue;
+
+		/* get the command */
+		for (end = str; *end && *end != ' '; end++)
+			;
+
+		cmd = keyscan_read_cmd(str, end - str);
+		args = end + (*end != '\0');
+		switch (cmd) {
+		case KEYSCAN_CMD_TEST:
+			/* Start a new test */
+			if (keyscan->test_count == KEYSCAN_MAX_TESTS) {
+				fprintf(stderr, "KEYSCAN_MAX_TESTS "
+						"exceeded\n");
+				return -1;
+			}
+			cur_test = &keyscan->tests[keyscan->test_count];
+			cur_test->name = strdup(args);
+			if (!cur_test->name) {
+				fprintf(stderr, "Line %d: out of memory\n",
+					linenum);
+			}
+			break;
+		case KEYSCAN_CMD_EXPECT:
+			/* Get expect string */
+			if (!cur_test) {
+				fprintf(stderr,
+					"Line %d: expect should be "
+					"inside test\n",
+					linenum);
+				return -1;
+			}
+			cur_test->expect = strdup(args);
+			if (!cur_test->expect) {
+				fprintf(stderr, "Line %d: out of memory\n",
+					linenum);
+			}
+			break;
+		case KEYSCAN_CMD_ENDTEST:
+			/* End of a test */
+			keyscan->test_count++;
+			cur_test = NULL;
+			break;
+		case KEYSCAN_CMD_SEQ:
+			if (keyscan_process_keys(keyscan, linenum, cur_test,
+						 args)) {
+				fprintf(stderr,
+					"Line %d: Cannot parse key "
+					"input '%s'\n",
+					linenum, args);
+				return -1;
+			}
+			break;
+		default:
+			fprintf(stderr, "Line %d: Uknown command '%1.*s'\n",
+				linenum, (int)(end - str), str);
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
+/**
+ * Print out a list of all tests
+ *
+ * @param keyscan	keyscan information
+ */
+static void keyscan_print(struct keyscan_info *keyscan)
+{
+	int testnum;
+	int i;
+
+	for (testnum = 0; testnum < keyscan->test_count; testnum++) {
+		struct keyscan_test *test = &keyscan->tests[testnum];
+
+		printf("Test: %s\n", test->name);
+		for (i = 0; i < test->item_count; i++) {
+			struct keyscan_test_item *item;
+			int j;
+
+			item = &test->items[i];
+			printf("%2d  %7d:  ", i, item->beat);
+			for (j = 0; j < sizeof(item->scan); j++)
+				printf("%02x ", item->scan[j]);
+			printf("\n");
+		}
+		printf("\n");
+	}
+}
+
+/**
+ * Set the terminal to raw mode, or cooked
+ *
+ * @param tty_fd	Terminal file descriptor to change
+ * @Param raw		0 for cooked, non-zero for raw
+ */
+static void set_to_raw(int tty_fd, int raw)
+{
+	struct termios tty_attr;
+	int value;
+
+	value = fcntl(tty_fd, F_GETFL);
+
+	tcgetattr(tty_fd, &tty_attr);
+	if (raw) {
+		tty_attr.c_lflag &= ~ICANON;
+		value |= O_NONBLOCK;
+	} else {
+		tty_attr.c_lflag |= ICANON;
+		value &= ~O_NONBLOCK;
+	}
+	tcsetattr(tty_fd, TCSANOW, &tty_attr);
+	fcntl(tty_fd, F_SETFL, value);
+}
+
+/**
+ * Read input for a whlie until wee see no more
+ *
+ * @param fd		File descriptor for input
+ * @param input		Place to put input string
+ * @param max_len	Maximum length of input string
+ * @param wait		Number of microseconds to wait for input
+ */
+static void keyscan_get_input(int fd, char *input, int max_len, int wait)
+{
+	int len;
+
+	usleep(wait);
+	input[0] = '\0';
+	len = read(fd, input, max_len - 1);
+	if (len > 0)
+		input[len] = '\0';
+}
+
+static int keyscan_send_sequence(struct keyscan_info *keyscan,
+				 struct keyscan_test *test)
+{
+	struct ec_params_keyscan_seq_ctrl *req;
+	struct keyscan_test_item *item;
+	int upto, size, rv;
+
+	size = sizeof(*req) + sizeof(item->scan);
+	req = (struct ec_params_keyscan_seq_ctrl *)malloc(size);
+	if (!req) {
+		fprintf(stderr, "Out of memory for message\n");
+		return -1;
+	}
+	for (upto = rv = 0, item = test->items;
+	     rv >= 0 && upto < test->item_count; upto++, item++) {
+		req->cmd = EC_KEYSCAN_SEQ_ADD;
+		req->add.time_us = item->beat * keyscan->beat_us;
+		memcpy(req->add.scan, item->scan, sizeof(item->scan));
+		rv = ec_command(EC_CMD_KEYSCAN_SEQ_CTRL, 0, req, size, NULL, 0);
+	}
+	free(req);
+	if (rv < 0)
+		return rv;
+
+	return 0;
+}
+
+/**
+ * Run a single test
+ *
+ * @param keyscan	keyscan information
+ * @param test		test to run
+ * @return 0 if test passes, -ve if some error occurred
+ */
+static int run_test(struct keyscan_info *keyscan, struct keyscan_test *test)
+{
+	struct ec_params_keyscan_seq_ctrl ctrl;
+	char input[KEYSCAN_MAX_INPUT_LEN];
+	struct ec_result_keyscan_seq_ctrl *resp;
+	int wait_us;
+	int size;
+	int rv;
+	int fd = 0;
+	int i;
+
+	/* First clear the sequence */
+	ctrl.cmd = EC_KEYSCAN_SEQ_CLEAR;
+	rv = ec_command(EC_CMD_KEYSCAN_SEQ_CTRL, 0, &ctrl, sizeof(ctrl), NULL,
+			0);
+	if (rv < 0)
+		return rv;
+
+	rv = keyscan_send_sequence(keyscan, test);
+	if (rv < 0)
+		return rv;
+
+	/* Start it */
+	set_to_raw(fd, 1);
+	ctrl.cmd = EC_KEYSCAN_SEQ_START;
+	rv = ec_command(EC_CMD_KEYSCAN_SEQ_CTRL, 0, &ctrl, sizeof(ctrl), NULL,
+			0);
+	if (rv < 0)
+		return rv;
+
+	/* Work out how long we need to wait */
+	wait_us = 100 * 1000; /* Wait 100ms to at least */
+	if (test->item_count) {
+		struct keyscan_test_item *ksi;
+
+		ksi = &test->items[test->item_count - 1];
+		wait_us += ksi->beat * keyscan->beat_us;
+	}
+
+	/* Wait for input */
+	keyscan_get_input(fd, input, sizeof(input), wait_us);
+	set_to_raw(fd, 0);
+
+	/* Ask EC for results */
+	size = sizeof(*resp) + test->item_count;
+	resp = (struct ec_result_keyscan_seq_ctrl *)(malloc(size));
+	if (!resp) {
+		fprintf(stderr, "Out of memory for results\n");
+		return -1;
+	}
+	ctrl.cmd = EC_KEYSCAN_SEQ_COLLECT;
+	ctrl.collect.start_item = 0;
+	ctrl.collect.num_items = test->item_count;
+	rv = ec_command(EC_CMD_KEYSCAN_SEQ_CTRL, 0, &ctrl, sizeof(ctrl), resp,
+			size);
+	if (rv < 0)
+		return rv;
+
+	/* Check what scans were skipped */
+	for (i = 0; i < resp->collect.num_items; i++) {
+		struct ec_collect_item *item;
+		struct keyscan_test_item *ksi;
+
+		item = &resp->collect.item[i];
+		ksi = &test->items[i];
+		if (!(item->flags & EC_KEYSCAN_SEQ_FLAG_DONE))
+			printf(" [skip %d at beat %u] ", i, ksi->beat);
+	}
+
+	if (strcmp(input, test->expect)) {
+		printf("Expected '%s', got '%s' ", test->expect, input);
+		return -1;
+	}
+
+	return 0;
+}
+
+/**
+ * Run all tests
+ *
+ * @param keyscan	keyscan information
+ * @return 0 if ok, -1 on error
+ */
+static int keyscan_run_tests(struct keyscan_info *keyscan)
+{
+	int testnum;
+	int any_err = 0;
+
+	for (testnum = 0; testnum < keyscan->test_count; testnum++) {
+		struct keyscan_test *test = &keyscan->tests[testnum];
+		int err;
+
+		fflush(stdout);
+		err = run_test(keyscan, test);
+		any_err |= err;
+		if (err) {
+			printf("%d: %s:  : FAIL\n", testnum, test->name);
+		}
+	}
+
+	return any_err ? -1 : 0;
+}
+
+int cmd_keyscan(int argc, char *argv[])
+{
+	struct keyscan_info keyscan;
+	FILE *f;
+	int err;
+
+	argc--;
+	argv++;
+	if (argc < 2) {
+		fprintf(stderr, "Must specify beat period and filename\n");
+		return -1;
+	}
+	memset(&keyscan, '\0', sizeof(keyscan));
+	keyscan.beat_us = atoi(argv[0]);
+	if (keyscan.beat_us < 100)
+		fprintf(stderr, "Warning: beat period is normally > 100us\n");
+	f = fopen(argv[1], "r");
+	if (!f) {
+		perror("Cannot open file\n");
+		return -1;
+	}
+
+	/* TODO(crosbug.com/p/23826): Read key matrix from fdt */
+	err = keyscan_read_fdt_matrix(&keyscan, "test/test-matrix.bin");
+	if (!err)
+		err = keyscan_process_file(f, &keyscan);
+	if (!err)
+		keyscan_print(&keyscan);
+	if (!err)
+		err = keyscan_run_tests(&keyscan);
+	fclose(f);
+
+	return err;
+}
diff --git a/util/env_changed.sh b/util/env_changed.sh
index 5bab64760d..eadc94ae01 100755
--- a/util/env_changed.sh
+++ b/util/env_changed.sh
@@ -1,5 +1,5 @@
 #!/bin/bash
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/util/export_taskinfo.c b/util/export_taskinfo.c
index 4c09bafb90..0fe8644792 100644
--- a/util/export_taskinfo.c
+++ b/util/export_taskinfo.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -6,11 +6,11 @@
  * section definitions to export different tasklists.
  */
 
-#include <stdint.h>
-
 #include "config.h"
 #include "task_id.h"
 
+#include <stdint.h>
+
 #ifdef SECTION_IS_RO
 #define GET_TASKINFOS_FUNC get_ro_taskinfos
 #elif defined(SECTION_IS_RW)
@@ -25,14 +25,13 @@ struct taskinfo {
 	uint32_t stack_size;
 };
 
-#define TASK(n, r, d, s, ...)  {	\
-	.name = #n,			\
-	.routine = #r,			\
-	.stack_size = s,		\
-},
-static const struct taskinfo taskinfos[] = {
-	CONFIG_TASK_LIST
-};
+#define TASK(n, r, d, s, ...)    \
+	{                        \
+		.name = #n,      \
+		.routine = #r,   \
+		.stack_size = s, \
+	},
+static const struct taskinfo taskinfos[] = { CONFIG_TASK_LIST };
 #undef TASK
 
 uint32_t GET_TASKINFOS_FUNC(const struct taskinfo **infos)
diff --git a/util/find_non_exec_lines.py b/util/find_non_exec_lines.py
new file mode 100755
index 0000000000..af5e972c79
--- /dev/null
+++ b/util/find_non_exec_lines.py
@@ -0,0 +1,71 @@
+#!/usr/bin/env python3
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Read lcov files, and find lines that are probably not executable.
+
+Example run:
+zmake build --coverage -a && \
+./util/find_non_exec_lines.py build/zephyr/all_builds.info && \
+echo SUCCESS
+"""
+
+import re
+import sys
+
+
+BAD_COVERAGE = re.compile(r"^$|\*/\s*$")
+
+
+def main() -> int:
+    """Read lcov files, and find lines that are probably not executable."""
+    exit_code = 0
+    for input_file in sys.argv:
+        with open(input_file, encoding="utf-8") as lcov:
+            active_file = None
+            active_line = 0
+            active_name = ""
+            for line in lcov:
+                line = line.strip()
+                if line.startswith("SF:"):
+                    if active_file:
+                        active_file.close()
+                        active_file = None
+                    active_line = 0
+                    active_name = line[3:]
+                    # There are several files in zephyr that have odd coverage
+                    # but it seems consistent.
+                    if (
+                        not "src/third_party/zephyr/cmsis/CMSIS/Core/Include/core_cm4.h"
+                        in active_name
+                        and not "src/third_party/zephyr/main/arch/arm/core/aarch32/mpu/arm_mpu.c"
+                        in active_name
+                        and not "src/third_party/zephyr/main/drivers/clock_control/clock_control_mchp_xec.c"
+                        in active_name
+                        and not "src/third_party/zephyr/main/lib/libc/minimal/include/"
+                        in active_name
+                    ):
+                        active_file = open(  # pylint: disable=R1732
+                            active_name, encoding="utf-8"
+                        )
+                if active_file and line.startswith("DA:"):
+                    target_line = int(line[3:].split(",", 1)[0])
+                    target = "NO SUCH LINE\n"
+                    while target and target_line > active_line:
+                        target = active_file.readline()
+                        active_line += 1
+                    if target and target_line == active_line:
+                        target = target.strip()
+                        if BAD_COVERAGE.match(target):
+                            print(f"{active_name}:{active_line}={target}")
+                            exit_code = 1
+            if active_file:
+                active_file.close()
+                active_file = None
+
+    return exit_code
+
+
+if __name__ == "__main__":
+    sys.exit(main())  # next section explains the use of sys.exit
diff --git a/util/fingerprint-relevant-paths.txt b/util/fingerprint-relevant-paths.txt
new file mode 100644
index 0000000000..e530c038cd
--- /dev/null
+++ b/util/fingerprint-relevant-paths.txt
@@ -0,0 +1,6 @@
+# Paths of interest to be included in the commit message for
+# merge commits to the firmware-fpmcu-<BOARD>-release branch when
+# using update_release_branch.py.
+common/fpsensor
+docs/fingerprint
+driver/fingerprint
diff --git a/util/flash_cr50.py b/util/flash_cr50.py
deleted file mode 100755
index 5b4428cf07..0000000000
--- a/util/flash_cr50.py
+++ /dev/null
@@ -1,771 +0,0 @@
-#!/usr/bin/env python3
-# -*- coding: utf-8 -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-"""Flash Cr50 using gsctool or cr50-rescue.
-
-gsctool example:
-util/flash_cr50.py --image cr50.bin.prod
-util/flash_cr50.py --release prod
-
-cr50-rescue example:
-util/flash_cr50.py --image cr50.bin.prod -c cr50-rescue -p 9999
-util/flash_cr50.py --release prod -c cr50-rescue -p 9999
-"""
-
-import argparse
-import os
-import pprint
-import re
-import select
-import shutil
-import subprocess
-import sys
-import tempfile
-import threading
-import time
-
-from chromite.lib import cros_build_lib
-from chromite.lib import cros_logging as logging
-
-CR50_FIRMWARE_BASE = '/opt/google/cr50/firmware/cr50.bin.'
-RELEASE_PATHS = {
-    'prepvt': CR50_FIRMWARE_BASE + 'prepvt',
-    'prod': CR50_FIRMWARE_BASE + 'prod',
-}
-# Dictionary mapping a setup to controls used to verify that the setup is
-# correct. The keys are strings and the values are lists of strings.
-REQUIRED_CONTROLS = {
-    'cr50_uart': [
-        r'raw_cr50_uart_pty:\S+',
-        r'cr50_ec3po_interp_connect:\S+',
-    ],
-    'cr50_reset_odl': [
-        r'cr50_reset_odl:\S+',
-    ],
-    'ec_uart': [
-        r'ec_board:\S+',
-    ],
-    'flex': [
-        r'servo_type:.*servo_.[^4]',
-    ],
-    'type-c_servo_v4': [
-        r'servo_v4_type:type-c',
-        r'servo_v4_role:\S+',
-    ],
-}
-# Supported methods to resetting cr50.
-SUPPORTED_RESETS = (
-    'battery_cutoff',
-    'cr50_reset_odl',
-    'manual_reset',
-)
-
-
-class Error(Exception):
-    """Exception class for flash_cr50 utility."""
-
-
-def run_command(cmd, check_error=True):
-    """Run the given command.
-
-    Args:
-        cmd: The command to run as a list of arguments.
-        check_error: Raise an error if the command fails.
-
-    Returns:
-        (exit_status, The command output)
-
-    Raises:
-        The command error if the command fails and check_error is True.
-    """
-    try:
-        result = cros_build_lib.run(cmd,
-                                    check=check_error,
-                                    print_cmd=True,
-                                    capture_output=True,
-                                    encoding='utf-8',
-                                    stderr=subprocess.STDOUT,
-                                    debug_level=logging.DEBUG,
-                                    log_output=True)
-    except cros_build_lib.RunCommandError as cmd_error:
-        if check_error:
-            raise
-        # OSErrors are handled differently. They're raised even if check is
-        # False. Return the errno and message for OS errors.
-        return cmd_error.exception.errno, cmd_error.msg
-    return result.returncode, result.stdout.strip()
-
-
-class Cr50Image(object):
-    """Class to handle cr50 image conversions."""
-
-    SUFFIX_LEN = 6
-    RW_NAME_BASE = 'cr50.rw.'
-
-    def __init__(self, image, artifacts_dir):
-        """Create an image object that can be used by cr50 updaters."""
-        self._remove_dir = False
-        if not os.path.exists(image):
-            raise Error('Could not find image: %s' % image)
-        if not artifacts_dir:
-            self._remove_dir = tempfile.mkdtemp()
-            artifacts_dir = self._remove_dir
-        if not os.path.isdir(artifacts_dir):
-            raise Error('Directory does not exist: %s' % artifacts_dir)
-        self._original_image = image
-        self._artifacts_dir = artifacts_dir
-        self._generate_file_names()
-
-    def __del__(self):
-        """Remove temporary files."""
-        if self._remove_dir:
-            shutil.rmtree(self._remove_dir)
-
-    def _generate_file_names(self):
-        """Create some filenames to use for image conversion artifacts."""
-        self._tmp_rw_bin = os.path.join(self._artifacts_dir,
-                                        self.RW_NAME_BASE + '.bin')
-        self._tmp_rw_hex = os.path.join(self._artifacts_dir,
-                                        self.RW_NAME_BASE + '.hex')
-        self._tmp_cr50_bin = os.path.join(self._artifacts_dir,
-                                          self.RW_NAME_BASE + '.orig.bin')
-
-    def extract_rw_a_hex(self):
-        """Extract RW_A.hex from the original image."""
-        run_command(['cp', self.get_bin(), self._tmp_cr50_bin])
-        run_command(['dd', 'if=' + self._tmp_cr50_bin, 'of=' + self._tmp_rw_bin,
-                     'skip=16384', 'count=233472', 'bs=1'])
-        run_command(['objcopy', '-I', 'binary', '-O', 'ihex',
-                     '--change-addresses', '0x44000', self._tmp_rw_bin,
-                     self._tmp_rw_hex])
-
-    def get_rw_hex(self):
-        """cr50-rescue uses the .hex file."""
-        if not os.path.exists(self._tmp_rw_hex):
-            self.extract_rw_a_hex()
-        return self._tmp_rw_hex
-
-    def get_bin(self):
-        """Get the filename of the update image."""
-        return self._original_image
-
-    def get_original_basename(self):
-        """Get the basename of the original image."""
-        return os.path.basename(self._original_image)
-
-
-class Servo(object):
-    """Class to interact with servo."""
-
-    # Wait 3 seconds for device to settle after running the dut control command.
-    SHORT_WAIT = 3
-
-    def __init__(self, port):
-        """Initialize servo class.
-
-        Args:
-            port: The servo port for the device being updated.
-        """
-        self._port = port
-
-    def dut_control(self, cmd, check_error=True, wait=False):
-        """Run dut control commands
-
-        Args:
-            cmd: the command to run
-            check_error: Raise RunCommandError if the command returns a non-zero
-                         exit status.
-            wait: If True, wait SHORT_WAIT seconds after running the command
-
-        Returns:
-            (exit_status, output string) - The exit_status will be non-zero if
-            the command failed and check_error is True.
-
-        Raises:
-            RunCommandError if the command fails and check_error is False
-        """
-        dut_control_cmd = ['dut-control', cmd, '-p', self._port]
-        exit_status, output = run_command(dut_control_cmd, check_error)
-        if wait:
-            time.sleep(self.SHORT_WAIT)
-        return exit_status, output.split(':', 1)[-1]
-
-    def get_raw_cr50_pty(self):
-        """Return raw_cr50_pty. Disable ec3po, so the raw pty can be used."""
-        # Disconnect EC3PO, raw_cr50_uart_pty will control the cr50
-        # output and input.
-        self.dut_control('cr50_ec3po_interp_connect:off', wait=True)
-        return self.dut_control('raw_cr50_uart_pty')[1]
-
-    def get_cr50_version(self):
-        """Return the current cr50 version string."""
-        # Make sure ec3po is enabled, so getting cr50_version works.
-        self.dut_control('cr50_ec3po_interp_connect:on', wait=True)
-        return self.dut_control('cr50_version')[1]
-
-
-class Cr50Reset(object):
-    """Class to enter and exit cr50 reset."""
-
-    # A list of requirements for the setup. The requirement strings must match
-    # something in the REQUIRED_CONTROLS dictionary.
-    REQUIRED_SETUP = ()
-
-    def __init__(self, servo, name):
-        """Make sure the setup supports the given reset_type.
-
-        Args:
-            servo: The Servo object for the device.
-            name: The reset type.
-        """
-        self._servo = servo
-        self._reset_name = name
-        self.verify_setup()
-        self._original_watchdog_state = self.ccd_watchdog_enabled()
-        self._servo_type = self._servo.dut_control('servo_type')[1]
-
-    def verify_setup(self):
-        """Verify the setup has all required controls to flash cr50.
-
-        Raises:
-            Error if something is wrong with the setup.
-        """
-        # If this failed before and didn't cleanup correctly, the device may be
-        # cutoff. Try to set the servo_v4_role to recover the device before
-        # checking the device state.
-        self._servo.dut_control('servo_v4_role:src', check_error=False)
-
-        logging.info('Requirements for %s: %s', self._reset_name,
-                     pprint.pformat(self.REQUIRED_SETUP))
-
-        # Get the specific control requirements for the necessary categories.
-        required_controls = []
-        for category in self.REQUIRED_SETUP:
-            required_controls.extend(REQUIRED_CONTROLS[category])
-
-        logging.debug('Required controls for %r:\n%s', self._reset_name,
-                      pprint.pformat(required_controls))
-        setup_issues = []
-        # Check the setup has all required controls in the correct state.
-        for required_control in required_controls:
-            control, exp_response = required_control.split(':')
-            returncode, output = self._servo.dut_control(control, False)
-            logging.debug('%s: got %s expect %s', control, output, exp_response)
-            match = re.search(exp_response, output)
-            if returncode:
-                setup_issues.append('%s: %s' % (control, output))
-            elif not match:
-                setup_issues.append('%s: need %s found %s' %
-                                    (control, exp_response, output))
-            else:
-                logging.debug('matched control: %s:%s', control, match.string)
-                # Save controls, so they can be restored during cleanup.
-                setattr(self, '_' + control, output)
-
-        if setup_issues:
-            raise Error('Cannot run update using %s. Setup issues: %s' %
-                        (self._reset_name, setup_issues))
-        logging.info('Device Setup: ok')
-        logging.info('Reset Method: %s', self._reset_name)
-
-    def cleanup(self):
-        """Try to get the device out of reset and restore all controls."""
-        logging.info('Cleaning up')
-        self.restore_control('cr50_ec3po_interp_connect')
-
-        # Toggle the servo v4 role if possible to try and get the device out of
-        # cutoff.
-        self._servo.dut_control('servo_v4_role:snk', check_error=False)
-        self._servo.dut_control('servo_v4_role:src', check_error=False)
-        self.restore_control('servo_v4_role')
-
-        # Restore the ccd watchdog.
-        self.enable_ccd_watchdog(self._original_watchdog_state)
-
-    def restore_control(self, control):
-        """Restore the control setting, if it has been saved.
-
-        Args:
-            control: The name of the servo control to restore.
-        """
-        setting = getattr(self, control, None)
-        if setting is None:
-            return
-        self._servo.dut_control('%s:%s' % (control, setting))
-
-    def ccd_watchdog_enabled(self):
-        """Return True if servod is monitoring ccd"""
-        if 'ccd_cr50' not in self._servo_type:
-            return False
-        watchdog_state = self._servo.dut_control('watchdog')[1]
-        logging.debug(watchdog_state)
-        return not re.search('ccd:.*disconnect ok', watchdog_state)
-
-    def enable_ccd_watchdog(self, enable):
-        """Control the CCD watchdog.
-
-        Servo will die if it's watching CCD and cr50 is held in reset. Disable
-        the CCD watchdog, so it's ok for CCD to disconnect.
-
-        This function does nothing if ccd_cr50 isn't in the servo type.
-
-        Args:
-            enable: If True, enable the CCD watchdog. Otherwise disable it.
-        """
-        if 'ccd_cr50' not in self._servo_type:
-            logging.debug('Servo is not watching ccd device.')
-            return
-
-        if enable:
-            self._servo.dut_control('watchdog_add:ccd')
-        else:
-            self._servo.dut_control('watchdog_remove:ccd')
-
-        if self.ccd_watchdog_enabled() != enable:
-            raise Error('Could not %sable ccd watchdog' %
-                        ('en' if enable else 'dis'))
-
-    def enter_reset(self):
-        """Disable the CCD watchdog then run the reset cr50 function."""
-        logging.info('Using %r to enter reset', self._reset_name)
-        # Disable the CCD watchdog before putting servo into reset otherwise
-        # servo will die in the middle of flashing cr50.
-        self.enable_ccd_watchdog(False)
-        try:
-            self.run_reset()
-        except Exception as e:
-            logging.warning('%s enter reset failed: %s', self._reset_name, e)
-            raise
-
-    def exit_reset(self):
-        """Exit cr50 reset."""
-        logging.info('Recovering from %s', self._reset_name)
-        try:
-            self.recover_from_reset()
-        except Exception as e:
-            logging.warning('%s exit reset failed: %s', self._reset_name, e)
-            raise
-
-    def run_reset(self):
-        """Start the cr50 reset process.
-
-        Cr50 doesn't have to enter reset in this function. It just needs to do
-        whatever setup is necessary for the exit reset function.
-        """
-        raise NotImplementedError()
-
-    def recover_from_reset(self):
-        """Recover from Cr50 reset.
-
-        Cr50 has to hard or power-on reset during this function for rescue to
-        work. Uart is disabled on deep sleep recovery, so deep sleep is not a
-        valid reset.
-        """
-        raise NotImplementedError()
-
-
-class Cr50ResetODLReset(Cr50Reset):
-    """Class for using the servo cr50_reset_odl to reset cr50."""
-
-    REQUIRED_SETUP = (
-        # Rescue is done through Cr50 uart. It requires a flex cable not ccd.
-        'flex',
-        # cr50_reset_odl is used to hold cr50 in reset. This control only exists
-        # if it actually resets cr50.
-        'cr50_reset_odl',
-        # Cr50 rescue is done through cr50 uart.
-        'cr50_uart',
-    )
-
-    def cleanup(self):
-        """Use the Cr50 reset signal to hold Cr50 in reset."""
-        try:
-            self.restore_control('cr50_reset_odl')
-        finally:
-            super(Cr50ResetODLReset, self).cleanup()
-
-    def run_reset(self):
-        """Use cr50_reset_odl to hold Cr50 in reset."""
-        logging.info('cr50_reset_odl:on')
-        self._servo.dut_control('cr50_reset_odl:on')
-
-    def recover_from_reset(self):
-        """Release the reset signal."""
-        logging.info('cr50_reset_odl:off')
-        self._servo.dut_control('cr50_reset_odl:off')
-
-
-class BatteryCutoffReset(Cr50Reset):
-    """Class for using a battery cutoff through EC commands to reset cr50."""
-
-    REQUIRED_SETUP = (
-        # Rescue is done through Cr50 uart. It requires a flex cable not ccd.
-        'flex',
-        # We need type c servo v4 to recover from battery_cutoff.
-        'type-c_servo_v4',
-        # Cr50 rescue is done through cr50 uart.
-        'cr50_uart',
-        # EC console needs to be read-write to issue cutoff command.
-        'ec_uart',
-    )
-
-    def run_reset(self):
-        """Use EC commands to cutoff the battery."""
-        self._servo.dut_control('servo_v4_role:snk')
-
-        if self._servo.dut_control('ec_board', check_error=False)[0]:
-            logging.warning('EC is unresponsive. Cutoff may not work.')
-
-        self._servo.dut_control('ec_uart_cmd:cutoff', check_error=False,
-                                wait=True)
-        self._servo.dut_control('ec_uart_cmd:reboot', check_error=False,
-                                wait=True)
-
-        if not self._servo.dut_control('ec_board', check_error=False)[0]:
-            raise Error('EC still responsive after cutoff')
-        logging.info('Device is cutoff')
-
-    def recover_from_reset(self):
-        """Connect power using servo v4 to recover from cutoff."""
-        logging.info('"Connecting" adapter')
-        self._servo.dut_control('servo_v4_role:src', wait=True)
-
-
-class ManualReset(Cr50Reset):
-    """Class for using a manual reset to reset Cr50."""
-
-    REQUIRED_SETUP = (
-        # Rescue is done through Cr50 uart. It requires a flex cable not ccd.
-        'flex',
-        # Cr50 rescue is done through cr50 uart.
-        'cr50_uart',
-    )
-
-    PROMPT_WAIT = 5
-    USER_RESET_TIMEOUT = 60
-
-    def run_reset(self):
-        """Nothing to do. User will reset cr50."""
-
-    def recover_from_reset(self):
-        """Wait for the user to reset cr50."""
-        end_time = time.time() + self.USER_RESET_TIMEOUT
-        while time.time() < end_time:
-            logging.info('Press enter after you reset cr50')
-            user_input = select.select([sys.stdin], [], [], self.PROMPT_WAIT)[0]
-            if user_input:
-                logging.info('User reset done')
-                return
-        logging.warning('User input timeout: assuming cr50 reset')
-
-
-class FlashCr50(object):
-    """Class for updating cr50."""
-
-    NAME = 'FlashCr50'
-    PACKAGE = ''
-    DEFAULT_UPDATER = ''
-
-    def __init__(self, cmd):
-        """Verify the update command exists.
-
-        Args:
-            cmd: The updater command.
-
-        Raises:
-            Error if no valid updater command was found.
-        """
-        updater = self.get_updater(cmd)
-        if not updater:
-            emerge_msg = (('Try emerging ' + self.PACKAGE) if self.PACKAGE
-                          else '')
-            raise Error('Could not find %s command.%s' % (self, emerge_msg))
-        self._updater = updater
-
-    def get_updater(self, cmd):
-        """Find a valid updater command.
-
-        Args:
-            cmd: the updater command.
-
-        Returns:
-            A command string or None if none of the commands ran successfully.
-            The command string will be the one supplied or the DEFAULT_UPDATER
-            command.
-        """
-        if not self.updater_works(cmd):
-            return cmd
-
-        use_default = (self.DEFAULT_UPDATER and
-                       not self.updater_works(self.DEFAULT_UPDATER))
-        if use_default:
-            logging.debug('%r failed using %r to update.', cmd,
-                          self.DEFAULT_UPDATER)
-            return self.DEFAULT_UPDATER
-        return None
-
-    @staticmethod
-    def updater_works(cmd):
-        """Verify the updater command.
-
-        Returns:
-          non-zero status if the command failed.
-        """
-        logging.debug('Testing update command %r.', cmd)
-        exit_status, output = run_command([cmd, '-h'], check_error=False)
-        if 'Usage' in output:
-            return 0
-        if exit_status:
-            logging.debug('Could not run %r (%s): %s', cmd, exit_status, output)
-        return exit_status
-
-    def update(self, image):
-        """Try to update cr50 to the given image."""
-        raise NotImplementedError()
-
-    def __str__(self):
-        """Use the updater name for the tostring."""
-        return self.NAME
-
-
-class GsctoolUpdater(FlashCr50):
-    """Class to flash cr50 using gsctool."""
-
-    NAME = 'gsctool'
-    PACKAGE = 'ec-utils'
-    DEFAULT_UPDATER = '/usr/sbin/gsctool'
-
-    # Common failures exit with this status. Use STANDARD_ERRORS to map the
-    # exit status to reasons for the failure.
-    STANDARD_ERROR_REGEX = r'Error: status (\S+)'
-    STANDARD_ERRORS = {
-        '0x8': 'Rejected image with old header.',
-        '0x9': 'Update too soon.',
-        '0xc': 'Board id mismatch',
-    }
-
-    def __init__(self, cmd, serial=None):
-        """Generate the gsctool command.
-
-        Args:
-            cmd: gsctool updater command.
-            serial: The serial number of the CCD device being updated.
-        """
-        super(GsctoolUpdater, self).__init__(cmd)
-        self._gsctool_cmd = [self._updater]
-        if serial:
-            self._gsctool_cmd.extend(['-n', serial])
-
-    def update(self, image):
-        """Use gsctool to update cr50.
-
-        Args:
-            image: Cr50Image object.
-        """
-        update_cmd = self._gsctool_cmd[:]
-        update_cmd.append(image.get_bin())
-        exit_status, output = run_command(update_cmd, check_error=False)
-        if not exit_status or (exit_status == 1 and 'image updated' in output):
-            logging.info('update ok')
-            return
-        if exit_status == 3:
-            match = re.search(self.STANDARD_ERROR_REGEX, output)
-            if match:
-                update_error = match.group(1)
-                logging.info('Update error %s', update_error)
-                raise Error(self.STANDARD_ERRORS[update_error])
-        raise Error('gsctool update error: %s' % output.splitlines()[-1])
-
-
-class Cr50RescueUpdater(FlashCr50):
-    """Class to flash cr50 through servo micro uart."""
-
-    NAME = 'cr50-rescue'
-    PACKAGE = 'cr50-utils'
-    DEFAULT_UPDATER = '/usr/bin/cr50-rescue'
-
-    WAIT_FOR_UPDATE = 120
-    RESCUE_RESET_DELAY = 5
-
-    def __init__(self, cmd, port, reset_type):
-        """Initialize cr50-rescue updater.
-
-        cr50-rescue can only be done through servo, because it needs access to
-        a lot of dut-controls and cr50 uart through servo micro. During rescue
-        Cr50 has to do a hard reset, so the user should supply a valid reset
-        method for the setup that's being used.
-
-        Args:
-            cmd: The cr50-rescue command.
-            port: The servo port of the device being updated.
-            reset_type: A string (one of SUPPORTED_RESETS) that describes how
-                        to reset Cr50 during cr50-rescue.
-        """
-        super(Cr50RescueUpdater, self).__init__(cmd)
-        self._servo = Servo(port)
-        self._rescue_thread = None
-        self._rescue_process = None
-        self._cr50_reset = self.get_cr50_reset(reset_type)
-
-    def get_cr50_reset(self, reset_type):
-        """Get the cr50 reset object for the given reset_type.
-
-        Args:
-            reset_type: a string describing how cr50 will be reset. It must be
-                        in SUPPORTED_RESETS.
-
-        Returns:
-            The Cr50Reset object for the given reset_type.
-        """
-        assert reset_type in SUPPORTED_RESETS, '%s is unsupported.' % reset_type
-        if reset_type == 'battery_cutoff':
-            return BatteryCutoffReset(self._servo, reset_type)
-        elif reset_type == 'cr50_reset_odl':
-            return Cr50ResetODLReset(self._servo, reset_type)
-        return ManualReset(self._servo, reset_type)
-
-    def update(self, image):
-        """Use cr50-rescue to update cr50 then cleanup.
-
-        Args:
-            image: Cr50Image object.
-        """
-        update_file = image.get_rw_hex()
-        try:
-            self.run_update(update_file)
-        finally:
-            self.restore_state()
-
-    def start_rescue_process(self, update_file):
-        """Run cr50-rescue in a process, so it can be killed it if it hangs."""
-        pty = self._servo.get_raw_cr50_pty()
-
-        rescue_cmd = [self._updater, '-v', '-i', update_file, '-d', pty]
-        logging.info('Starting cr50-rescue: %s',
-                     cros_build_lib.CmdToStr(rescue_cmd))
-
-        self._rescue_process = subprocess.Popen(rescue_cmd)
-        self._rescue_process.communicate()
-        logging.info('Rescue Finished')
-
-    def start_rescue_thread(self, update_file):
-        """Start cr50-rescue."""
-        self._rescue_thread = threading.Thread(target=self.start_rescue_process,
-                                               args=[update_file])
-        self._rescue_thread.start()
-
-    def run_update(self, update_file):
-        """Run the Update"""
-        # Enter reset before starting rescue, so any extra cr50 messages won't
-        # interfere with cr50-rescue.
-        self._cr50_reset.enter_reset()
-
-        self.start_rescue_thread(update_file)
-
-        time.sleep(self.RESCUE_RESET_DELAY)
-        # Resume from cr50 reset.
-        self._cr50_reset.exit_reset()
-
-        self._rescue_thread.join(self.WAIT_FOR_UPDATE)
-
-        logging.info('cr50_version:%s', self._servo.get_cr50_version())
-
-    def restore_state(self):
-        """Try to get the device out of reset and restore all controls"""
-        try:
-            self._cr50_reset.cleanup()
-        finally:
-            self.cleanup_rescue_thread()
-
-    def cleanup_rescue_thread(self):
-        """Cleanup the rescue process and handle any errors."""
-        if not self._rescue_thread:
-            return
-        if self._rescue_thread.is_alive():
-            logging.info('Killing cr50-rescue process')
-            self._rescue_process.terminate()
-            self._rescue_thread.join()
-
-        self._rescue_thread = None
-        if self._rescue_process.returncode:
-            logging.info('cr50-rescue failed.')
-            logging.info('stderr: %s', self._rescue_process.stderr)
-            logging.info('stdout: %s', self._rescue_process.stdout)
-            logging.info('returncode: %s', self._rescue_process.returncode)
-            raise Error('cr50-rescue failed (%d)' %
-                        self._rescue_process.returncode)
-
-
-def parse_args(argv):
-    """Parse commandline arguments.
-
-    Args:
-        argv: command line args
-
-    Returns:
-        options: an argparse.Namespace.
-    """
-    usage = ('%s -i $IMAGE [ -c cr50-rescue -p $SERVO_PORT [ -r '
-             '$RESET_METHOD]]' % os.path.basename(argv[0]))
-    parser = argparse.ArgumentParser(usage=usage, description=__doc__)
-    parser.add_argument('-d', '--debug', action='store_true', default=False,
-                        help='enable debug messages.')
-    parser.add_argument('-i', '--image', type=str,
-                        help='Path to cr50 binary image.')
-    parser.add_argument('-R', '--release', type=str,
-                        choices=RELEASE_PATHS.keys(),
-                        help='Type of cr50 release. Use instead of the image '
-                        'arg.')
-    parser.add_argument('-c', '--updater-cmd', type=str, default='gsctool',
-                        help='Tool to update cr50. Either gsctool or '
-                        'cr50-rescue')
-    parser.add_argument('-s', '--serial', type=str, default='',
-                        help='serial number to pass to gsctool.')
-    parser.add_argument('-p', '--port', type=str, default='',
-                        help='port servod is listening on (required for '
-                        'rescue).')
-    parser.add_argument('-r', '--reset-type', default='battery_cutoff',
-                        choices=SUPPORTED_RESETS,
-                        type=str, help='The method for cr50 reset.')
-    parser.add_argument('-a', '--artifacts-dir', default=None, type=str,
-                        help='Location to store artifacts')
-    opts = parser.parse_args(argv[1:])
-    if 'cr50-rescue' in opts.updater_cmd and not opts.port:
-        raise parser.error('Servo port is required for cr50 rescue')
-    return opts
-
-
-def get_updater(opts):
-    """Get the updater object."""
-    if 'cr50-rescue' in opts.updater_cmd:
-        return Cr50RescueUpdater(opts.updater_cmd, opts.port, opts.reset_type)
-    if 'gsctool' in opts.updater_cmd:
-        return GsctoolUpdater(opts.updater_cmd, opts.serial)
-    raise Error('Unsupported update command %r' % opts.updater_cmd)
-
-
-def main(argv):
-    """Update cr50 using gsctool or cr50-rescue."""
-    opts = parse_args(argv)
-
-    loglevel = logging.INFO
-    log_format = '%(asctime)s - %(levelname)7s'
-    if opts.debug:
-        loglevel = logging.DEBUG
-        log_format += ' - %(lineno)3d:%(funcName)-15s'
-    log_format += ' - %(message)s'
-    logging.basicConfig(level=loglevel, format=log_format)
-
-    image = Cr50Image(RELEASE_PATHS.get(opts.release, opts.image),
-                      opts.artifacts_dir)
-    flash_cr50 = get_updater(opts)
-
-    logging.info('Using %s to update to %s', flash_cr50,
-                 image.get_original_basename())
-    flash_cr50.update(image)
-
-
-if __name__ == '__main__':
-    sys.exit(main(sys.argv))
diff --git a/util/flash_ec b/util/flash_ec
index dade6f1a24..8b86e451c6 100755
--- a/util/flash_ec
+++ b/util/flash_ec
@@ -1,11 +1,11 @@
 #!/bin/bash
 
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
+# Copyright 2014 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 SCRIPT="$(readlink -f "$0")"
-SCRIPT_DIR="$(dirname "$SCRIPT")"
+SCRIPT_DIR="$(dirname "${SCRIPT}")"
 
 EC_DIR="$(readlink -f "${SCRIPT_DIR}/..")"
 if [[ "$(basename "${EC_DIR}")" != "ec" ]]; then
@@ -49,14 +49,10 @@ die() {
 # not aware of its 'ec_chip'. If servod becomes able to answer 'ec_chip'
 # for the board, remove it from BOARDS_XXXX array below.
 BOARDS_IT83XX=(
-	glkrvp_ite
+	adlrvpm_ite
+	adlrvpp_ite
 	it83xx_evb
 	reef_it8320
-	tglrvpu_ite
-	tglrvpu_ite_tcpmv1
-	tglrvpy_ite
-	tglrvpy_ite_tcpmv1
-	jslrvp_ite
 )
 
 BOARDS_IT83XX_SPI_PROGRAMMING=(
@@ -74,22 +70,14 @@ BOARDS_STM32=(
 	glados_pd
 	hatch_fp
 	jerry
-	magnemite
-	masterball
 	minimuffin
-	moonball
 	nami_fp
 	nocturne_fp
 	oak_pd
 	pit
 	plankton
 	rainier
-	samus_pd
-	staff
 	strago_pd
-	wand
-	whiskers
-	zed
 	zinger
 )
 BOARDS_STM32_PROG_EN=(
@@ -128,7 +116,12 @@ BOARDS_NPCX_7M7X_JTAG=(
 )
 
 BOARDS_NPCX_SPI=(
-	glkrvp
+	helipilot
+)
+
+BOARDS_NPCX_INT_SPI=(
+	adlrvpp_npcx
+	mtlrvpp_npcx
 )
 
 BOARDS_SPI_1800MV=(
@@ -140,7 +133,6 @@ BOARDS_RAIDEN=(
 	coral
 	eve
 	fizz
-	flapjack
 	kukui
 	nami
 	nautilus
@@ -151,14 +143,17 @@ BOARDS_RAIDEN=(
 	soraka
 )
 
+BOARDS_MCHP_INT_SPI=(
+	mtlrvpp_mchp
+)
 DEFAULT_PORT="${SERVOD_PORT:-9999}"
 BITBANG_RATE="57600"  # Could be overwritten by a command line option.
 
 # Flags
 DEFINE_integer bitbang_rate "${BITBANG_RATE}" \
-	"UART baud rate to use when bit bang programming, "\
-"standard UART rates from 9600 to 57600 are supported."
-DEFINE_string board "${DEFAULT_BOARD}" \
+	"UART baud rate to use when bit bang programming, " \
+	"standard UART rates from 9600 to 57600 are supported."
+DEFINE_string board "" \
 	"The board to run debugger on."
 DEFINE_string chip "" \
 	"The chip to run debugger on."
@@ -166,6 +161,8 @@ DEFINE_boolean dry_run "${FLAGS_FALSE}" \
 	"Print the commands to be run instead of actually running them."
 DEFINE_string image "" \
 	"Full pathname of the EC firmware image to flash."
+DEFINE_string mchp_loader "" \
+	"Full pathname of the Microchip loader firmware image to SRAM."
 DEFINE_string logfile "" \
 	"Stm32 only: pathname of the file to store communications log."
 DEFINE_string offset "0" \
@@ -185,6 +182,10 @@ DEFINE_boolean verbose "${FLAGS_FALSE}" \
 	"Verbose hw control logging"
 DEFINE_boolean verify "${FLAGS_FALSE}" \
 	"Verify EC firmware image after programming."
+DEFINE_boolean zephyr "${FLAGS_FALSE}" \
+	"Program a Zephyr EC image instead of a CrOS EC image"
+DEFINE_boolean no_preserve "${FLAGS_FALSE}" \
+	"Avoid preserving the sections of firmware image with preserve property"
 
 # Parse command line
 FLAGS_HELP="usage: $0 [flags]"
@@ -230,15 +231,15 @@ function print_or_run() {
 function dut_control() {
 	local DUT_CTRL_CML=( "${DUT_CONTROL_CMD[@]}" )
 
-	for p in $@ ; do
+	for p in "$@" ; do
 		# Only add the prefix if the arg is a control name.
 		if [[ ${p} != -* ]] ; then
 			p="${DUT_CTRL_PREFIX}${p}"
 		fi
-		DUT_CTRL_CML+=( "$p" )
+		DUT_CTRL_CML+=( "${p}" )
 	done
 
-	if [ "${FLAGS_verbose}" = ${FLAGS_TRUE} ]; then
+	if [ "${FLAGS_verbose}" = "${FLAGS_TRUE}" ]; then
 		echo "${DUT_CTRL_CML[*]}" 1>&2
 	fi
 
@@ -251,7 +252,7 @@ function dut_control_or_die {
 
 function dut_control_get() {
 	if [ $# -gt 1 ]; then
-		error "${FUNCNAME[0]} failed: more than one argument: $@"
+		error "${FUNCNAME[0]} failed: more than one argument: $*"
 		return 1
 	fi
 
@@ -273,7 +274,7 @@ function dut_control_get_or_die {
 	    die "command exited $? (non-zero): dut-control --value_only $*"
 }
 
-BOARD=${FLAGS_board}
+: "${BOARD:=${FLAGS_board}}"
 
 in_array() {
 	local n=$#
@@ -289,44 +290,52 @@ in_array() {
 
 declare -a SUPPORTED_CHIPS
 
-if $(in_array "${BOARDS_STM32[@]}" "${BOARD}"); then
+if in_array "${BOARDS_STM32[@]}" "${BOARD}"; then
 	SUPPORTED_CHIPS+=("stm32")
 fi
 
-if $(in_array "${BOARDS_STM32_DFU[@]}" "${BOARD}"); then
+if in_array "${BOARDS_STM32_DFU[@]}" "${BOARD}"; then
 	SUPPORTED_CHIPS+=("stm32_dfu")
 fi
 
-if $(in_array "${BOARDS_NPCX_5M5G_JTAG[@]}" "${BOARD}"); then
+if in_array "${BOARDS_NPCX_5M5G_JTAG[@]}" "${BOARD}"; then
 	SUPPORTED_CHIPS+=("npcx_5m5g_jtag")
 fi
 
-if $(in_array "${BOARDS_NPCX_5M6G_JTAG[@]}" "${BOARD}"); then
+if in_array "${BOARDS_NPCX_5M6G_JTAG[@]}" "${BOARD}"; then
 	SUPPORTED_CHIPS+=("npcx_5m6g_jtag")
 fi
 
-if $(in_array "${BOARDS_NPCX_7M6X_JTAG[@]}" "${BOARD}"); then
+if in_array "${BOARDS_NPCX_7M6X_JTAG[@]}" "${BOARD}"; then
 	SUPPORTED_CHIPS+=("npcx_7m6x_jtag")
 fi
 
-if $(in_array "${BOARDS_NPCX_7M7X_JTAG[@]}" "${BOARD}"); then
+if in_array "${BOARDS_NPCX_7M7X_JTAG[@]}" "${BOARD}"; then
 	SUPPORTED_CHIPS+=("npcx_7m7x_jtag")
 fi
 
-if $(in_array "${BOARDS_NPCX_SPI[@]}" "${BOARD}"); then
+if in_array "${BOARDS_NPCX_SPI[@]}" "${BOARD}"; then
 	SUPPORTED_CHIPS+=("npcx_spi")
 fi
 
-if $(in_array "${BOARDS_IT83XX[@]}" "${BOARD}"); then
+if in_array "${BOARDS_NPCX_INT_SPI[@]}" "${BOARD}"; then
+	SUPPORTED_CHIPS+=("npcx_int_spi")
+fi
+
+if in_array "${BOARDS_IT83XX[@]}" "${BOARD}"; then
 	SUPPORTED_CHIPS+=("it83xx")
 fi
 
-if $(in_array "${BOARDS_IT83XX_SPI_PROGRAMMING[@]}" "${BOARD}"); then
+if in_array "${BOARDS_IT83XX_SPI_PROGRAMMING[@]}" "${BOARD}"; then
 	SUPPORTED_CHIPS+=("ite_spi")
 fi
 
+if in_array "${BOARDS_MCHP_INT_SPI[@]}" "${BOARD}"; then
+	SUPPORTED_CHIPS+=("mchp_int_spi")
+fi
+
 if [[ ${#SUPPORTED_CHIPS[@]} -eq 0 && -n "${FLAGS_chip}" ]]; then
-	SUPPORTED_CHIPS+="${FLAGS_chip}"
+	SUPPORTED_CHIPS+=("${FLAGS_chip}")
 fi
 
 if [[ ${#SUPPORTED_CHIPS[@]} -eq 0 ]]; then
@@ -348,10 +357,10 @@ if [[ ${#SUPPORTED_CHIPS[@]} -eq 0 ]]; then
 elif [[ ${#SUPPORTED_CHIPS[@]} -eq 1 ]]; then
 	CHIP="${SUPPORTED_CHIPS[0]}"
 elif [ -n "${FLAGS_chip}" ]; then
-	if $(in_array "${SUPPORTED_CHIPS[@]}" "${FLAGS_chip}"); then
+	if in_array "${SUPPORTED_CHIPS[@]}" "${FLAGS_chip}"; then
 		CHIP="${FLAGS_chip}"
 	else
-		die "board ${BOARD} only supports (${SUPPORTED_CHIPS[@]})," \
+		die "board ${BOARD} only supports (${SUPPORTED_CHIPS[*]})," \
 			"not ${FLAGS_chip}."
 	fi
 else
@@ -359,10 +368,10 @@ else
 	# file, instead of having multiple board-to-chip mapping info in this
 	# script. Please refer to crrev.com/c/1496460 for example.
 	die "board ${BOARD} supports multiple chips" \
-	"(${FILTERED_CHIPS[@]}). Use --chip= to choose one."
+	"(${SUPPORTED_CHIPS[*]}). Use --chip= to choose one."
 fi
 
-if [ -n "${FLAGS_chip}" -a "${CHIP}" != "${FLAGS_chip}" ]; then
+if [ -n "${FLAGS_chip}" ] && [ "${CHIP}" != "${FLAGS_chip}" ]; then
 	die "board ${BOARD} doesn't use chip ${FLAGS_chip}"
 fi
 
@@ -373,16 +382,16 @@ fi
 # Servo variables management
 case "${BOARD}" in
 	chocodile_bec ) MCU="usbpd" ;;
-	oak_pd|samus_pd|strago_pd ) MCU="usbpd" ;;
+	oak_pd|strago_pd ) MCU="usbpd" ;;
 	chell_pd|glados_pd ) MCU="usbpd" ;;
-	bloonchipper|dartmonkey|hatch_fp|nami_fp|nocturne_fp ) MCU="usbpd" ;;
+	bloonchipper|dartmonkey|hatch_fp|helipilot|nami_fp|nocturne_fp ) MCU="fpmcu" ;;
 	dingdong|hoho|twinkie ) DUT_CONTROL_CMD=( "true" ); MCU="ec" ;;
 	*) MCU="ec" ;;
 esac
 
 case "${CHIP}" in
 	"stm32"|"npcx_spi"|"npcx_int_spi"|"it83xx"|"npcx_uut"|"ite_spi"| \
-			"ite_spi_ccd_i2c")
+			"ite_spi_ccd_i2c"|"it8xxx2"|"mchp_int_spi")
 		;;
 	*)
 		if [[ -n "${FLAGS_read}" ]]; then
@@ -391,7 +400,7 @@ case "${CHIP}" in
 
 		# If verification is not supported, then show a warning message.
 		# Keep it running however.
-		if [[ "${FLAGS_verify}" == ${FLAGS_TRUE} ]]; then
+		if [[ "${FLAGS_verify}" == "${FLAGS_TRUE}" ]]; then
 			warn "Ignoring '--verify'" \
 			"since read is not supported on ${CHIP}."
 		fi
@@ -400,17 +409,22 @@ esac
 
 SERVO_TYPE="$(dut_control_get servo_type || :)"
 
-if [[ "${SERVO_TYPE}" =~ ^servo_v4_with_.*$ ]]; then
-	ACTIVE_DEVICE="$(dut_control_get active_v4_device)"
+if [[ "${SERVO_TYPE}" =~ ^servo_v4(p1)?_with_.*$ ]]; then
+	ACTIVE_DEVICE="$(dut_control_get active_dut_controller)"
+	if [[ ${ACTIVE_DEVICE} == neither ]]; then
+          die "Could not determine servo V4 active device"
+        fi
 else
 	ACTIVE_DEVICE="${SERVO_TYPE}"
 fi
 
-if [[ "${SERVO_TYPE}" =~ ^servo_v4_with_.*_and_.*$ ]]; then
+if [[ "${SERVO_TYPE}" =~ ^servo_v4(p1)?_with_.*_and_.*$ ]]; then
 	# If there are two devices, servo v4 type will show both devices. The
 	# default device is first. The other device is second.
-	# servo_type:servo_v4_with_servo_micro_and_ccd_cr50
+	# servo_type:servo_v4{p1}_with_servo_micro_and_ccd_cr50
 	SECOND_DEVICE="${SERVO_TYPE#*_and_}"
+	# servo_v4p1 can shared the same type with servo_v4, since there's no
+	# difference handling the flash.
 	SERVO_TYPE="servo_v4_with_${ACTIVE_DEVICE}"
 	# Controls sent through the default device don't have a prefix. The
 	# second device controls do. If the default device isn't active, we
@@ -421,6 +435,10 @@ if [[ "${SERVO_TYPE}" =~ ^servo_v4_with_.*_and_.*$ ]]; then
 	fi
 fi
 
+servo_is_ccd() {
+	[[ "${SERVO_TYPE}" =~ "ccd" ]]
+}
+
 servo_has_warm_reset() {
 	dut_control -i warm_reset >/dev/null 2>&1
 }
@@ -459,29 +477,51 @@ servo_usbpd_hard_reset() {
 	dut_control usbpd_reset:on sleep:0.5 usbpd_reset:off
 }
 
+servo_fpmcu_hard_reset() {
+	dut_control fpmcu_reset:on sleep:0.5 fpmcu_reset:off
+
+	# b/177331210: Workaround for an outstanding issue that prevents
+	# flashing dartmonkey with a servo_micro. The exact root cause is still
+	# unknown, but it's been observed that repeating the FPMCU reset
+	# sequence twice makes the operation succeed.
+	if [[ "${BOARD}" =~ "dartmonkey" ]] ; then
+		warn "Workaround for dartmonkey + servo_micro: repeat FPMCU reset sequence"
+		dut_control fpmcu_reset:on sleep:0.5 fpmcu_reset:off
+	fi
+}
+
 servo_sh_hard_reset() {
 	dut_control sh_reset:on
 	dut_control sh_reset:off
 }
 
-ccd_cr50_ec_hard_reset() {
-	servo_ec_hard_reset
-}
-
 ec_reset() {
-	stype=${SERVO_TYPE}
-	if [[ "${SERVO_TYPE}" =~ "servo" ]] ; then
-		stype=servo
+	local stype
+
+	if [[ "${SERVO_TYPE}" =~ "servo" ]] || servo_is_ccd; then
+		stype="servo"
+	else
+		stype=${SERVO_TYPE}
 	fi
 
 	if [[ -n "${stype}" ]]; then
-		eval ${stype}_${MCU}_hard_reset
+		eval "${stype}_${MCU}_hard_reset"
 	fi
 }
 
 ccd_ec_boot0() {
-	info "Using CCD $2."
-	dut_control ccd_ec_boot_mode_$2:$1
+	local on_value="${1}"
+	local boot_mode="${2}"
+
+	info "Using CCD ${boot_mode}."
+
+	if [[ "${on_value}" == "on" ]] && [[ "${boot_mode}" == "uut" ]] ; then
+		# Ti50 requires EC reset to be asserted before UUT mode can be
+		# enabled, Cr50 should not mind.
+		dut_control cold_reset:on
+	fi
+
+	dut_control "ccd_ec_boot_mode_${boot_mode}:${on_value}"
 }
 
 servo_micro_ec_boot0() {
@@ -489,7 +529,7 @@ servo_micro_ec_boot0() {
 	# circuit that is controlled by the EC_FLASH_ODL pin. For those boards,
 	# we want to continue to drive the EC_FLASH_ODL if they do not have the
 	# servo micro rework listed below.
-	if [[ "${FLAGS_servo_micro_uart_rx_rework}" == ${FLAGS_TRUE} ]]; then
+	if [[ "${FLAGS_servo_micro_uart_rx_rework}" == "${FLAGS_TRUE}" ]]; then
 		info "Servo micro $2 mode: $1 (using rx_rework)"
 
 		# Setting the test point allows the EC_TX_SERVO_RX line
@@ -499,24 +539,32 @@ servo_micro_ec_boot0() {
 		# HW Rework (b/143163043#comment3):
 		#   - Disconnect U45.1 from ground
 		#   - Connected U45.1 to TP1 pad
-		dut_control tp1:$1
-		dut_control servo_micro_ec_boot_mode_$2:$1
+		dut_control "tp1:$1"
+		dut_control "servo_micro_ec_boot_mode_$2:$1"
 	else
 		info "Servo micro $2 mode: $1 (using FW_UP_L)"
-		dut_control ec_boot_mode:$1
+		dut_control "ec_boot_mode:$1"
 	fi
 }
 
 servo_ec_boot0() {
-	dut_control ec_boot_mode:$1
+	dut_control "ec_boot_mode:$1"
 }
 
 c2d2_ec_boot0() {
-	dut_control ec_boot_mode_uut:$1
+	dut_control "ec_boot_mode_uut:$1"
 }
 
 servo_usbpd_boot0() {
-	dut_control usbpd_boot_mode:$1
+	dut_control "usbpd_boot_mode:$1"
+}
+
+servo_fpmcu_boot0() {
+	dut_control "fpmcu_boot_mode:$1"
+}
+
+servo_micro_fpmcu_boot0() {
+	servo_fpmcu_boot0 "$@"
 }
 
 servo_micro_usbpd_boot0() {
@@ -524,18 +572,18 @@ servo_micro_usbpd_boot0() {
 }
 
 servo_sh_boot0() {
-	dut_control sh_boot_mode:$1
+	dut_control "sh_boot_mode:$1"
 }
 
 ec_switch_boot0() {
-	on_value=$1
+	local on_value=$1
 	# Enable programming GPIOs
-	if $(in_array "${BOARDS_STM32_PROG_EN[@]}" "${BOARD}"); then
+	if in_array "${BOARDS_STM32_PROG_EN[@]}" "${BOARD}"; then
 		servo_save_add "prog_en"
 
 		dut_control prog_en:yes
 	fi
-	if [[ "${SERVO_TYPE}" =~ "ccd_cr50" ]] ; then
+	if servo_is_ccd ; then
 		stype=ccd
 	elif [[ "${SERVO_TYPE}" =~ "servo_micro" ]] ; then
 		stype=servo_micro
@@ -544,15 +592,15 @@ ec_switch_boot0() {
 	else
 		stype=${SERVO_TYPE}
 	fi
-	eval ${stype}_${MCU}_boot0 "${on_value}" $2
+	eval "${stype}_${MCU}_boot0" "${on_value}" "$2"
 }
 
 ec_enable_boot0() {
-	ec_switch_boot0 "on" $1
+	ec_switch_boot0 "on" "$1"
 }
 
 ec_disable_boot0() {
-	ec_switch_boot0 "off" $1
+	ec_switch_boot0 "off" "$1"
 }
 
 # Returns 0 on success (if on beaglebone)
@@ -564,14 +612,14 @@ on_servov3() {
 error_reported=  # Avoid double printing the error message.
 on_raiden() {
 	if [[ "${SERVO_TYPE}" =~ "servo_v4" ]] || \
-	   [[ "${SERVO_TYPE}" =~ "ccd_cr50" ]] || \
+	   servo_is_ccd || \
 	   [[ "${SERVO_TYPE}" =~ "servo_micro" ]]; then
 		return 0
 	fi
 	if [ -z "${BOARD}" ]; then
-		[ "${FLAGS_raiden}" = ${FLAGS_TRUE} ] && return 0 || return 1
+		[ "${FLAGS_raiden}" = "${FLAGS_TRUE}" ] && return 0 || return 1
 	fi
-	if [ "${FLAGS_raiden}" = ${FLAGS_TRUE} ]; then
+	if [ "${FLAGS_raiden}" = "${FLAGS_TRUE}" ]; then
 		if in_array "${BOARDS_RAIDEN[@]}" "${BOARD}"; then
 			return 0
 		fi
@@ -622,11 +670,11 @@ cleanup() {
 
 	servo_restore
 
-	if [ "${CHIP}" = "stm32" -o "${CHIP}" = "npcx_uut" ]; then
+	if [ "${CHIP}" = "stm32" ] || [ "${CHIP}" = "npcx_uut" ]; then
 		dut_control "${MCU}"_boot_mode:off
 	fi
 
-	if [[ "${SERVO_TYPE}" =~ "ccd_cr50" ]]; then
+	if servo_is_ccd; then
 		dut_control ccd_ec_boot_mode_uut:off
 		dut_control ccd_ec_boot_mode_bitbang:off
 	fi
@@ -637,8 +685,17 @@ cleanup() {
 }
 trap cleanup EXIT
 
+# TODO: the name of the RO images created for zephyr vary based on whether
+# the RO image includes a header.
+# NPCX images use "build-ro/zephyr/zephyr.npcx.bin"
+# ITE images use "build-ro/zephyr/zephyr.bin"
+if [ "${FLAGS_ro}" = "${FLAGS_TRUE}" ] && [ "${FLAGS_zephyr}" = "${FLAGS_TRUE}" ]
+then
+	die "The --ro flag is not supported with the --zephyr flag"
+fi
+
 # Possible default EC images
-if [ "${FLAGS_ro}" = ${FLAGS_TRUE} ] ; then
+if [ "${FLAGS_ro}" = "${FLAGS_TRUE}" ] ; then
 	EC_FILE=ec.RO.flat
 else
 	EC_FILE=ec.bin
@@ -646,8 +703,10 @@ fi
 
 LOCAL_BUILD=
 if [[ -n "${EC_DIR}" ]]; then
-	if [ "${FLAGS_ro}" = ${FLAGS_TRUE} ] ; then
+	if [ "${FLAGS_ro}" = "${FLAGS_TRUE}" ] ; then
 		LOCAL_BUILD="${EC_DIR}/build/${BOARD}/RO/${EC_FILE}"
+	elif [ "${FLAGS_zephyr}" = "${FLAGS_TRUE}" ] ; then
+		LOCAL_BUILD="${EC_DIR}/build/zephyr/${BOARD}/output/${EC_FILE}"
 	else
 		LOCAL_BUILD="${EC_DIR}/build/${BOARD}/${EC_FILE}"
 	fi
@@ -660,14 +719,15 @@ BASEBOARD=
 # setting BASEBOARD
 set +e
 if [[ -n "${EC_DIR}" ]]; then
-	BASEBOARD=$(make --quiet -C ${EC_DIR} BOARD=${BOARD} print-baseboard \
+	BASEBOARD=$(make --quiet -C "${EC_DIR}" BOARD="${BOARD}" print-baseboard \
 		2>/dev/null)
 elif [[ -d "${HOME}/trunk/src/platform/ec" ]]; then
-	BASEBOARD=$(make --quiet -C ${HOME}/trunk/src/platform/ec \
-		BOARD=${BOARD} print-baseboard 2>/dev/null)
+	BASEBOARD=$(make --quiet -C "${HOME}"/trunk/src/platform/ec \
+		BOARD="${BOARD}" print-baseboard 2>/dev/null)
 else
 	info "Could not find ec build folder to calculate baseboard."
 fi
+# shellcheck disable=SC2181
 if [ $? -ne 0 ]; then
 	info "EC build system didn't recognize ${BOARD}. Assuming no baseboard."
 fi
@@ -683,7 +743,7 @@ fi
 function ec_image() {
 	# No image specified on the command line, try default ones
 	if [[ -n "${FLAGS_image}" ]] ; then
-		if [ -f "${FLAGS_image}" ] || \
+		if [ -e "${FLAGS_image}" ] || \
 		   [ "${FLAGS_image}" == "-" ]; then
 			echo "${FLAGS_image}"
 			return
@@ -702,28 +762,56 @@ function ec_image() {
 	die "no EC image found : build one or specify one."
 }
 
+# Find the Loader image to use
+function mchp_loader_image() {
+	# If no image specified on the command line, try default ones
+	if [[ -n "${FLAGS_mchp_loader}" ]] ; then
+		if [ -e "${FLAGS_mchp_loader}" ] || \
+		   [ "${FLAGS_mchp_loader}" == "-" ]; then
+			echo "${FLAGS_mchp_loader}"
+			return
+		fi
+		die "Invalid image path: ${FLAGS_mchp_loader}"
+	else
+		if [ -f "${LOCAL_BUILD}" ]; then
+			echo "${LOCAL_BUILD}"
+			return
+		fi
+		if [ -f "${EMERGE_BUILD}" ]; then
+			echo "${EMERGE_BUILD}"
+			return
+		fi
+	fi
+	die "No loader image found: build one or specify one"
+}
+
+# Get the correct UART for flashing. The resulting string is concatenated with
+# the various UART control suffixes, such as "_pty", "_en", "_parity", etc.
+function servo_ec_uart_prefix() {
+	if [[ "${MCU}" == "fpmcu" ]]; then
+		# The FPMCU has multiple UARTs. Use the platform UART since it's a
+		# bootloader capable UART on all devices. See
+		# http://go/cros-fingerprint-reference-designs#uart-console.
+		echo "fpmcu_platform_uart"
+		return
+	fi
+
+	echo "${MCU}_uart"
+}
+
 # Find the EC UART provided by servo.
 function servo_ec_uart() {
 	SERVOD_FAIL="Cannot communicate with servod. Is servod running?"
-	PTY=$(dut_control_get raw_${MCU}_uart_pty ||
-	      dut_control_get ${MCU}_uart_pty)
+	local EC_UART_PREFIX
+	EC_UART_PREFIX="$(servo_ec_uart_prefix)"
+	PTY=$(dut_control_get "raw_${EC_UART_PREFIX}_pty" ||
+	      dut_control_get "${EC_UART_PREFIX}_pty")
 	if [[ -z "${PTY}" ]]; then
 	    die "${SERVOD_FAIL}"
 	fi
-	echo $PTY
+	echo "${PTY}"
 }
 
-# Not every control is supported on every servo type.  Therefore, define which
-# controls are supported by each servo type.
-servo_v2_VARS=( "cold_reset" )
-servo_micro_VARS=( "cold_reset" )
-servo_v4_with_ccd_cr50_VARS=( "cold_reset" )
-c2d2_VARS=( "cold_reset" )
-
-# Some servo boards use the same controls.
-servo_v3_VARS=( "${servo_v2_VARS[@]}" )
-servo_v4_with_servo_micro_VARS=( "${servo_micro_VARS[@]}" )
-
 declare -a save
 
 #######################################
@@ -736,12 +824,12 @@ function servo_save_add() {
 	local CTRL_RESULT=
 	case $# in
 		1) CTRL_RESULT="$( "${DUT_CONTROL_CMD[@]}" \
-				"${DUT_CTRL_PREFIX}$@" )"
+				"${DUT_CTRL_PREFIX}$*" )"
 		   if [[ -n "${CTRL_RESULT}" ]]; then
 			# Don't save the control with the prefix, because
 			# dut_control will add the prefix again when we restore
 			# the settings.
-			save=( "${CTRL_RESULT#$DUT_CTRL_PREFIX}" "${save[@]}" )
+			save=( "${CTRL_RESULT#"${DUT_CTRL_PREFIX}"}" "${save[@]}" )
 		   fi
 		   ;;
 		2) save=( "$1:$2" "${save[@]}" )
@@ -752,10 +840,7 @@ function servo_save_add() {
 }
 
 function servo_save() {
-	local SERVO_VARS_NAME="${SERVO_TYPE}_VARS[@]"
-	for ctrl in "${!SERVO_VARS_NAME}"; do
-		servo_save_add "${ctrl}"
-	done
+	servo_save_add "cold_reset"
 
 	if [[ "${SERVO_TYPE}" == "servo_v2" ]]; then
 		servo_save_add "i2c_mux_en"
@@ -777,8 +862,9 @@ function servo_restore() {
 
 function claim_pty() {
 	if grep -q cros_sdk /proc/1/cmdline; then
-		die "You must run this tool in a chroot that was entered with" \
-		    "'cros_sdk --no-ns-pid' (see crbug.com/444931 for details)"
+		warn "You might want to run this tool in a chroot that was" \
+		     "entered with 'cros_sdk --no-ns-pid'" \
+		     "(see crbug.com/444931 for details)"
 	fi
 
 	if [[ -z "$1" ]]; then
@@ -790,29 +876,30 @@ function claim_pty() {
 	# interfere with flashing.
 	servo_save_add "${MCU}_ec3po_interp_connect"
 
-	dut_control ${MCU}_ec3po_interp_connect:off || \
+	dut_control "${MCU}_ec3po_interp_connect:off" || \
 	    warn "hdctools cannot disconnect the EC-3PO interpreter from" \
 	    "the UART."
 
-	pids=$(lsof -FR 2>/dev/null -- $1 | grep -v '^f' | tr -d 'pR')
+	pids=$(lsof -FR 2>/dev/null -- "$1" | grep -v '^f' | tr -d 'pR')
 	FROZEN_PIDS=""
 
 	# reverse order to SIGSTOP parents before children
-	for pid in $(echo ${pids} | tac -s " "); do
+	for pid in $(echo "${pids}" | tac -s " "); do
+		# shellcheck disable=SC2009
 		if ps -o cmd= "${pid}" | grep -qE "(servod|/sbin/init)"; then
 			info "Skip stopping servod or init: process ${pid}."
 		else
 			info "Sending SIGSTOP to process ${pid}!"
 			FROZEN_PIDS+=" ${pid}"
 			sleep 0.02
-			kill -STOP ${pid}
+			kill -STOP "${pid}"
 		fi
 	done
 }
 
 # Returns the serialnumber of the specified servo.
 function get_serial() {
-	if [[ "${SERVO_TYPE}" =~ "servo_v4_with_servo_micro" ]]; then
+	if [[ "${SERVO_TYPE}" =~ ^servo_v4(p1)?_with_servo_micro ]]; then
 		if [[ -z "${BOARD}" ]]; then
 			sn_ctl="servo_micro_"
 		elif [[ "$(dut_control_get "servo_micro_for_${BOARD}_serialname")" =~ \
@@ -847,7 +934,7 @@ repo sync && sudo emerge hdctools servo-firmware && sudo servo_updater -b c2d2"
 		while [[ "$(dut_control_get h1_vref_present)" = "off" \
 			&& "${LOOP_COUNTER}" -gt 1 ]] ; do
 			sleep 0.1
-			let LOOP_COUNTER=LOOP_COUNTER-1
+			(( LOOP_COUNTER=LOOP_COUNTER-1 ))
 		done
 		# If we ran out of time, then just die now
 		if [[ "${LOOP_COUNTER}" -eq 1 ]] ; then
@@ -890,7 +977,7 @@ function flash_openocd() {
 
 # helper function for using servo with flashrom
 function flash_flashrom() {
-	TOOL_PATH="${EC_DIR}/build/${BOARD}/util:$PATH:/usr/sbin"
+	TOOL_PATH="${EC_DIR}/build/${BOARD}/util:${PATH}:/usr/sbin"
 	FLASHROM=$(PATH="${TOOL_PATH}" which flashrom)
 
 	if on_servov3; then
@@ -906,21 +993,24 @@ function flash_flashrom() {
 		FLASHROM_ARGS="-p ft2232_spi:type=google-servo-v2,port=B,"
 	fi
 
-	if [ ! -x "$FLASHROM" ]; then
+	if [ ! -x "${FLASHROM}" ]; then
 		die "no flashrom util found."
 	fi
 
 	if ! on_servov3; then
 		SERIALNAME=$(get_serial)
-		if [[ "$SERIALNAME" != "" ]] ; then
+		if [[ "${SERIALNAME}" != "" ]] ; then
 			FLASHROM_ARGS+="serial=${SERIALNAME}"
 		fi
 	fi
 
+	# Eventually remove ite_spi_ccd_i2c once all references are removed
 	if ! on_raiden || [[ "${SERVO_TYPE}" =~ "servo_micro" ]] ; then
-		if $(in_array "${BOARDS_SPI_1800MV[@]}" "${BOARD}"); then
+		if in_array "${BOARDS_SPI_1800MV[@]}" "${BOARD}"; then
 			SPI_VOLTAGE="pp1800"
-		elif [[ "${CHIP}" == "ite_spi" || "${CHIP}" == "ite_spi_ccd_i2c" ]]; then
+		elif [[ "${CHIP}" == "ite_spi" ||
+		        "${CHIP}" == "ite_spi_ccd_i2c" ||
+			"${CHIP}" == "it8xxx2" ]]; then
 			SPI_VOLTAGE="pp1800"
 		else
 			SPI_VOLTAGE="pp3300"
@@ -934,26 +1024,38 @@ function flash_flashrom() {
 
 			# Set GP_SEL# as low then start ec
 			dut_control fw_up:on
-			sleep 0.1
+			sleep 0.2
+			dut_control cold_reset:off
+		# Gang programmer mode for npcx_spi requires using dev_mode
+		# rather than fw_up
+		elif [[ "${CHIP}" == "npcx_spi" ]]; then
+			servo_save_add "dev_mode" "off"
+
+			dut_control dev_mode:on
+			sleep 0.2
 			dut_control cold_reset:off
 		fi
 
 		# Enable SPI programming mode.
-		if [[ "${CHIP}" == "ite_spi" || "${CHIP}" == "ite_spi_ccd_i2c" ]]; then
-			# Set hardware strap pin (GPG6) of SPI programming as low then start ec
-			dut_control fw_up:on
-			sleep 0.1
-			dut_control cold_reset:off
-			sleep 0.1
-			# We have to release the HW strap pin because it also SPI clock pin.
-			dut_control fw_up:off
+		if [[ "${CHIP}" == "ite_spi" ||
+			"${CHIP}" == "ite_spi_ccd_i2c" ||
+			"${CHIP}" == "it8xxx2" ]]; then
+					# Set hardware strap pin (GPG6) of SPI
+					# programming as low then start ec
+					dut_control fw_up:on
+					sleep 0.1
+					dut_control cold_reset:off
+					sleep 0.2
+					# We have to release the HW strap pin
+					# because it also SPI clock pin.
+					dut_control fw_up:off
 		fi
 
 		servo_save_add "spi1_vref" "off"
 		servo_save_add "spi1_buf_en" "off"
 
 		# Turn on SPI1 interface on servo for SPI Flash Chip
-		dut_control spi1_vref:${SPI_VOLTAGE} spi1_buf_en:on
+		dut_control "spi1_vref:${SPI_VOLTAGE}" spi1_buf_en:on
 		if [[ ! "${SERVO_TYPE}" =~ "servo_micro" ]]; then
 			# Servo micro doesn't support this control.
 			servo_save_add "spi1_buf_on_flex_en" "off"
@@ -966,7 +1068,7 @@ function flash_flashrom() {
 			# Set GP_SEL# as low then start ec
 			dut_control cold_reset:on
 			dut_control fw_up:on
-			# sleep 0.1
+			sleep 0.2
 			dut_control cold_reset:off
 		else
 			# Assert EC reset.
@@ -979,25 +1081,25 @@ function flash_flashrom() {
 
 		[[ -z "${FLAGS_read}" ]] && dump_fmap -F "${IMG}" > "${L}"
 
-		FLASHROM_OPTIONS="-i EC_RW -i WP_RO -l "${L}" --ignore-fmap"
-		FLASHROM_OPTIONS+=" --fast-verify"
+		FLASHROM_OPTIONS=(-i EC_RW -i WP_RO -l "${L}" --noverify-all)
 	fi
 
 	# Generate the correct flashrom command base.
-	FLASHROM_CMDLINE="${FLASHROM} ${FLASHROM_ARGS}"
+	# shellcheck disable=SC2206
+	FLASHROM_CMDLINE=("${FLASHROM}" ${FLASHROM_ARGS})
 	if [[ -z "${FLAGS_read}" ]]; then
 		# Program EC image.
 		# flashrom should report the image size at the end of the output.
-		local FLASHROM_GETSIZE="sudo ${FLASHROM_CMDLINE} --flash-size"
-		if [[ "${FLAGS_verbose}" == ${FLAGS_TRUE} ]]; then
+		local FLASHROM_GETSIZE=(sudo "${FLASHROM_CMDLINE[@]}" --flash-size)
+		if [[ "${FLAGS_verbose}" == "${FLAGS_TRUE}" ]]; then
 			info "Running flashrom:" 1>&2
-			echo " ${FLASHROM_GETSIZE}" 1>&2
+			echo " ${FLASHROM_GETSIZE[*]}" 1>&2
 		fi
-		SPI_SIZE=$(${FLASHROM_GETSIZE} | grep -oe '[0-9]\+$' |
+		SPI_SIZE=$("${FLASHROM_GETSIZE[@]}" | grep -oe '[0-9]\+$' |
 			   tail -n1) || die "Failed to determine chip size!"
 		[[ ${SPI_SIZE} -eq 0 ]] && die "Chip size is 0!"
 
-		PATCH_SIZE=$((${SPI_SIZE} - ${IMG_SIZE}))
+		PATCH_SIZE=$(( SPI_SIZE - IMG_SIZE ))
 
 		# Temp image
 		T=/tmp/flash_spi_$$
@@ -1005,65 +1107,67 @@ function flash_flashrom() {
 
 		if [[ "${CHIP}" =~ ^npcx(|_int)_spi$ ]] || \
 		   [[ "${CHIP}" =~ "ite_spi_ccd_i2c" ]] ||
+		   [[ "${CHIP}" =~ "it8xxx2" ]] ||
 		   [[ "${CHIP}" =~ "ite_spi" ]] ; then
 		{	# Patch temp image up to SPI_SIZE
-			cat "$IMG"
+			cat "${IMG}"
 			if [[ ${IMG_SIZE} -lt ${SPI_SIZE} ]] ; then
-				dd if=/dev/zero bs=${PATCH_SIZE} count=1 | \
+				dd if=/dev/zero bs="${PATCH_SIZE}" count=1 | \
 					tr '\0' '\377'
 			fi
-		} > $T
+		} > "${T}"
 		else
 		{	# Patch temp image up to SPI_SIZE
 			if [[ ${IMG_SIZE} -lt ${SPI_SIZE} ]] ; then
-				dd if=/dev/zero bs=${PATCH_SIZE} count=1 | \
+				dd if=/dev/zero bs="${PATCH_SIZE}" count=1 | \
 					tr '\0' '\377'
 			fi
-			cat "$IMG"
-		} > $T
+			cat "${IMG}"
+		} > "${T}"
 		fi
 
 		info "Programming EC firmware image."
-		local FLASHROM_WRITE="${FLASHROM_CMDLINE} ${FLASHROM_OPTIONS}"
-		if [[ "${FLAGS_verbose}" == ${FLAGS_TRUE} ]]; then
+		local FLASHROM_WRITE=("${FLASHROM_CMDLINE[@]}" "${FLASHROM_OPTIONS[@]}")
+		if [[ "${FLAGS_verbose}" == "${FLAGS_TRUE}" ]]; then
 			info "Running flashrom:" 1>&2
-			echo " ${FLASHROM_WRITE} -w ${T}" 1>&2
+			echo " ${FLASHROM_WRITE[*]} -w ${T}" 1>&2
 		fi
 		print_or_run sudo timeout -k 10 -s 9 "${FLAGS_timeout}" \
-			${FLASHROM_WRITE} -w "${T}" \
+			"${FLASHROM_WRITE[@]}" -w "${T}" \
 			|| die "${MSG_PROGRAM_FAIL}"
 	else
 		# Read EC image.
 		info "Reading EC firmware image."
-		if [[ "${FLAGS_verbose}" == ${FLAGS_TRUE} ]]; then
+		if [[ "${FLAGS_verbose}" == "${FLAGS_TRUE}" ]]; then
 			info "Running flashrom:" 1>&2
-			echo " ${FLASHROM_CMDLINE} -r ${FLAGS_read}" 1>&2
+			echo " ${FLASHROM_CMDLINE[*]} -r ${FLAGS_read}" 1>&2
 		fi
 		print_or_run sudo timeout -k 10 -s 9 "${FLAGS_timeout}" \
-			${FLASHROM_CMDLINE} -r "${FLAGS_read}" \
+			"${FLASHROM_CMDLINE[@]}" -r "${FLAGS_read}" \
 			|| die "${MSG_READ_FAIL}"
 	fi
 }
 
 function flash_stm32() {
 	local STM32MON
-	local STM32MON_OPT
+	local STM32MON_OPT=()
 
 	if ! servo_has_cold_reset; then
 		die "Cold reset must be available for STM32 programming"
 	fi
 
-	TOOL_PATH="${EC_DIR}/build/${BOARD}/util:$PATH"
+	TOOL_PATH="${EC_DIR}/build/${BOARD}/util:${PATH}"
 	STM32MON=$(PATH="${TOOL_PATH}" which stm32mon)
 	EC_UART="$(servo_ec_uart)"
-	if [ ! -x "$STM32MON" ]; then
+	EC_UART_PREFIX="$(servo_ec_uart_prefix)"
+	if [ ! -x "${STM32MON}" ]; then
 		die "no stm32mon util found."
 	fi
 
 	info "Using serial flasher : ${STM32MON}"
 	info "${MCU} UART pty : ${EC_UART}"
-	claim_pty ${EC_UART}
-	STM32MON_OPT="-d ${EC_UART}"
+	claim_pty "${EC_UART}"
+	STM32MON_OPT+=(-d "${EC_UART}")
 
 	# Make sure EC reboots in serial monitor mode.
 	ec_enable_boot0 "bitbang"
@@ -1072,16 +1176,16 @@ function flash_stm32() {
 	ec_reset
 
 	if ! on_raiden && [[ "${SERVO_TYPE}" =~ "servo" ]] ; then
-		servo_save_add "${MCU}_uart_en"
+		servo_save_add "${EC_UART_PREFIX}_en"
 
-		dut_control ${MCU}_uart_en:on
+		dut_control "${EC_UART_PREFIX}_en:on"
 	fi
 
-	servo_save_add "${MCU}_uart_parity"
+	servo_save_add "${EC_UART_PREFIX}_parity"
 
-	dut_control ${MCU}_uart_parity:even
+	dut_control "${EC_UART_PREFIX}_parity:even"
 
-	if [[ "${SERVO_TYPE}" =~ "ccd_cr50" ]] ; then
+	if servo_is_ccd ; then
 		case "${FLAGS_bitbang_rate}" in
 			(9600|19200|38400|57600) : ;;
 			(*)
@@ -1091,27 +1195,27 @@ function flash_stm32() {
 		esac
 		info "Programming at ${FLAGS_bitbang_rate} baud"
 
-		servo_save_add "${MCU}_uart_baudrate"
-		servo_save_add "${MCU}_uart_bitbang_en"
+		servo_save_add "${EC_UART_PREFIX}_baudrate"
+		servo_save_add "${EC_UART_PREFIX}_bitbang_en"
 
-		dut_control ${MCU}_uart_baudrate:"${FLAGS_bitbang_rate}"
-		dut_control ${MCU}_uart_bitbang_en:on
+		dut_control "${EC_UART_PREFIX}_baudrate:${FLAGS_bitbang_rate}"
+		dut_control "${EC_UART_PREFIX}_bitbang_en:on"
 	else
-		servo_save_add "${MCU}_uart_baudrate"
+		servo_save_add "${EC_UART_PREFIX}_baudrate"
 
-		dut_control ${MCU}_uart_baudrate:115200
+		dut_control "${EC_UART_PREFIX}_baudrate:115200"
 	fi
 
 	# Add a delay long enough for cr50 to update the ccdstate. Cr50 updates
 	# ccdstate once a second, so a 2 second delay should be safe.
-	if [[ "${SERVO_TYPE}" =~ "ccd_cr50" ]] ; then
+	if servo_is_ccd ; then
 		sleep 2
-		STM32MON_OPT+=" -c"
+		STM32MON_OPT+=(-c)
 	fi
 
 	if [ -n "${FLAGS_logfile}" ]; then
 		info "Saving log in ${FLAGS_logfile}"
-		STM32MON_OPT+=" -L ${FLAGS_logfile}"
+		STM32MON_OPT+=(-L "${FLAGS_logfile}")
 	fi
 
 	local IMG_READ="${FLAGS_read}"
@@ -1119,19 +1223,21 @@ function flash_stm32() {
 	if [[ -z "${IMG_READ}" ]]; then
 		info "Programming EC firmware image."
 		# Unprotect flash, erase, and write
-		local STM32MON_COMMAND="${STM32MON} ${STM32MON_OPT} -u -e -w"
-		if [[ "${FLAGS_verbose}" == ${FLAGS_TRUE} ]]; then
-			echo "${STM32MON_COMMAND} ${IMG}"
+		local STM32MON_COMMAND=("${STM32MON}" "${STM32MON_OPT[@]}" -U -u -e -w)
+		if [[ "${FLAGS_verbose}" == "${FLAGS_TRUE}" ]]; then
+			echo "${STM32MON_COMMAND[*]} ${IMG}"
 		fi
 		print_or_run timeout -k 10 -s 9 "${FLAGS_timeout}" \
-			${STM32MON_COMMAND} "${IMG}" \
+			"${STM32MON_COMMAND[@]}" "${IMG}" \
 			|| die "${MSG_PROGRAM_FAIL}"
 
 		# If it is a program-verify request, then make a temporary
 		# directory to store the image
-		if [[ "${FLAGS_verify}" == ${FLAGS_TRUE} ]]; then
-			local TEMP_SUFFIX=".$(basename ${SCRIPT}).${CHIP}"
-			local TEMP_DIR="$(mktemp -d --suffix="${TEMP_SUFFIX}")"
+		if [[ "${FLAGS_verify}" == "${FLAGS_TRUE}" ]]; then
+			local TEMP_SUFFIX
+			local TEMP_DIR
+			TEMP_SUFFIX=".$(basename "${SCRIPT}").${CHIP}"
+			TEMP_DIR="$(mktemp -d --suffix="${TEMP_SUFFIX}")"
 
 			IMG_READ="${TEMP_DIR}/ec.read.bin"
 			DELETE_LIST+=( "${TEMP_DIR}" )
@@ -1141,20 +1247,20 @@ function flash_stm32() {
 	# Read EC image.
 	if [[ -n "${IMG_READ}" ]]; then
 		info "Reading EC firmware image."
-		local STM32MON_READ_CMD="${STM32MON} ${STM32MON_OPT} -U -r"
-		if [[ "${FLAGS_verbose}" == ${FLAGS_TRUE} ]]; then
-			echo "${STM32MON_READ_CMD} ${IMG_READ}"
+		local STM32MON_READ_CMD=("${STM32MON}" "${STM32MON_OPT[@]}" -U -r)
+		if [[ "${FLAGS_verbose}" == "${FLAGS_TRUE}" ]]; then
+			echo "${STM32MON_READ_CMD[*]} ${IMG_READ}"
 		fi
 		print_or_run timeout -k 10 -s 9 "${FLAGS_timeout}" \
-			${STM32MON_READ_CMD} "${IMG_READ}" \
+			"${STM32MON_READ_CMD[@]}" "${IMG_READ}" \
 			|| die "${MSG_READ_FAIL}"
 	fi
 
 	# Verify the flash by comparing the source image to the read image,
 	# only if it was a flash write request.
-	if [[ -z "${FLAGS_read}" && "${FLAGS_verify}" == ${FLAGS_TRUE} ]]; then
+	if [[ -z "${FLAGS_read}" && "${FLAGS_verify}" == "${FLAGS_TRUE}" ]]; then
 		info "Verifying EC firmware image."
-		if [[ "${FLAGS_verbose}" == ${FLAGS_TRUE} ]]; then
+		if [[ "${FLAGS_verbose}" == "${FLAGS_TRUE}" ]]; then
 			echo "cmp -n ${IMG_SIZE} ${IMG} ${IMG_READ}"
 		fi
 		cmp -s -n "${IMG_SIZE}" "${IMG}" "${IMG_READ}" \
@@ -1172,48 +1278,58 @@ function flash_stm32_dfu() {
 	DFU_DEVICE=0483:df11
 	ADDR=0x08000000
 	DFU_UTIL='dfu-util'
-	which $DFU_UTIL &> /dev/null || die \
+	which "${DFU_UTIL}" &> /dev/null || die \
 		"no dfu-util util found.  Did you 'sudo emerge dfu-util'"
 
 	info "Using dfu flasher : ${DFU_UTIL}"
 
-	dev_cnt=$(lsusb -d $DFU_DEVICE | wc -l)
-	if [ $dev_cnt -eq 0 ] ; then
-		die "unable to locate dfu device at $DFU_DEVICE"
-	elif [ $dev_cnt -ne 1 ] ; then
+	dev_cnt=$(lsusb -d "${DFU_DEVICE}" | wc -l)
+	if [ "${dev_cnt}" -eq 0 ] ; then
+		die "unable to locate dfu device at ${DFU_DEVICE}"
+	elif [ "${dev_cnt}" -ne 1 ] ; then
 		die "too many dfu devices (${dev_cnt}). Disconnect all but one."
 	fi
 
-	SIZE=$(wc -c ${IMG} | cut -d' ' -f1)
+	SIZE=$(wc -c "${IMG}" | cut -d' ' -f1)
 	# Remove read protection
-	print_or_run sudo timeout -k 10 -s 9 "${FLAGS_timeout}" $DFU_UTIL -a 0 \
-		-d "${DFU_DEVICE}" -s ${ADDR}:${SIZE}:force:unprotect -D "${IMG}"
+	print_or_run sudo timeout -k 10 -s 9 "${FLAGS_timeout}" "${DFU_UTIL}" -a 0 \
+		-d "${DFU_DEVICE}" -s "${ADDR}:${SIZE}:force:unprotect" -D "${IMG}"
 	# Wait for mass-erase and reboot after unprotection
 	print_or_run sleep 1
 	# Actual image flashing
-	print_or_run sudo timeout -k 10 -s 9 "${FLAGS_timeout}" $DFU_UTIL -a 0 \
-		-d "${DFU_DEVICE}" -s ${ADDR}:${SIZE} -D "${IMG}"
+	print_or_run sudo timeout -k 10 -s 9 "${FLAGS_timeout}" "${DFU_UTIL}" -a 0 \
+		-d "${DFU_DEVICE}" -s "${ADDR}:${SIZE}" -D "${IMG}"
 }
 
 function dut_i2c_dev() {
-	if [ -n "$DUT_I2C_DEV" ]; then
-		[ -e "$DUT_I2C_DEV" ] ||
-			die "\$DUT_I2C_DEV is a non-existent path: $DUT_I2C_DEV"
-		echo "$DUT_I2C_DEV"
+	if [ -n "${DUT_I2C_DEV}" ]; then
+		[ -e "${DUT_I2C_DEV}" ] ||
+			die "\$DUT_I2C_DEV is a non-existent path: ${DUT_I2C_DEV}"
+		echo "${DUT_I2C_DEV}"
 		return
 	fi
 
+	local has_i2c_pseudo
+	has_i2c_pseudo="$(dut_control_get_or_die \
+		"${ACTIVE_DEVICE}_i2c_pseudo_is_running")"
+	if [[ "${has_i2c_pseudo}" == False ]]; then
+		error "i2c-pseudo module is not running on ${ACTIVE_DEVICE}."
+		error "Please follow https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/util/iteflash.md#i2c-pseudo"
+		die "to install i2c-pseudo module."
+	fi
+
 	local adap_num=
 	adap_num="$(dut_control_get_or_die \
 	    "${ACTIVE_DEVICE}_i2c_pseudo_adapter_num")"
-	echo /dev/i2c-"$adap_num"
+	echo /dev/i2c-"${adap_num}"
 }
 
 function flash_it83xx() {
-	local TOOL_PATH="${EC_DIR}/build/${BOARD}/util:$PATH"
-	local ITEFLASH_BIN=$(PATH="${TOOL_PATH}" which iteflash)
+	local TOOL_PATH="${EC_DIR}/build/${BOARD}/util:${PATH}"
+	local ITEFLASH_BIN
+	ITEFLASH_BIN=$(PATH="${TOOL_PATH}" which iteflash)
 
-	if [[ ! -x "$ITEFLASH_BIN" ]]; then
+	if [[ ! -x "${ITEFLASH_BIN}" ]]; then
 		die "no iteflash util found."
 	fi
 
@@ -1222,14 +1338,17 @@ function flash_it83xx() {
 		c2d2_wait_for_h1_power_on_or_reset
 
 		# Don't let the EC come out of reset after H1 reset
-		dut_control ec_reset:on
+		dut_control gsc_ec_reset:on
 
 		# Enable i2c bus on C2D2 at 400kbps
 		servo_save_add "i2c_ec_bus_speed"
 		dut_control_or_die i2c_ec_bus_speed:400
 
 		# We need to swing the DUT-side muxes to I2C instead of UART.
-		# This is done by convention with EC_FLASH_SELECT pin from H1
+		# This is done by convention with EC_FLASH_SELECT pin of the
+		# GSC. Also make sure that the setting is restored after
+		# completion.
+		servo_save_add "ec_flash_select" "off"
 		dut_control_or_die ec_flash_select:on
 	fi
 
@@ -1245,7 +1364,7 @@ function flash_it83xx() {
 	# We need to send the special waveform very soon after the EC powers on
 	if [[ "${SERVO_TYPE}" =~ "c2d2" ]]; then
 		# The EC was held in reset above
-		dut_control ec_reset:off
+		dut_control gsc_ec_reset:off
 	elif servo_has_cold_reset; then
 		servo_ec_hard_reset_or_die
 	fi
@@ -1255,8 +1374,9 @@ function flash_it83xx() {
 	      "${SERVO_TYPE}" =~ "c2d2" ]] ; then
 		info "Asking servo to send the dbgr special waveform to ${CHIP}"
 		dut_control_or_die enable_ite_dfu
-	elif [[ "${SERVO_TYPE}" =~ "ccd_cr50" ]]; then
-		local CCD_I2C_CAP="$(dut_control_get ccd_i2c_en)"
+	elif servo_is_ccd; then
+		local CCD_I2C_CAP
+		CCD_I2C_CAP="$(dut_control_get ccd_i2c_en)"
 		if [[ "${CCD_I2C_CAP,,}" != "always" ]]; then
 			die "CCD I2C capability is not set as 'Always'" \
 				": ${CCD_I2C_CAP}"
@@ -1282,7 +1402,7 @@ function flash_it83xx() {
 		ITEFLASH_ARGS=( "sudo" "--" "${ITEFLASH_ARGS[@]}" \
 			"--send-waveform=0" "--i2c-interface=linux" \
 			"--i2c-dev-path=$(dut_i2c_dev)" )
-		if [[ "${SERVO_TYPE}" =~ "ccd_cr50" ]]; then
+		if servo_is_ccd; then
 			ITEFLASH_ARGS+=( "--block-write-size=256" )
 		fi
 	fi
@@ -1298,7 +1418,11 @@ function flash_it83xx() {
 		ERROR_MSG="${MSG_PROGRAM_FAIL}"
 	fi
 
-	if [[ "${FLAGS_verbose}" == ${FLAGS_TRUE} ]]; then
+	if [[ "${FLAGS_verify}" == "${FLAGS_FALSE}" ]]; then
+		ITEFLASH_ARGS+=( "--noverify" )
+	fi
+
+	if [[ "${FLAGS_verbose}" == "${FLAGS_TRUE}" ]]; then
 		ITEFLASH_ARGS+=( "--debug" )
 		echo "${ITEFLASH_ARGS[@]}"
 	fi
@@ -1327,28 +1451,14 @@ function flash_ite_spi_ccd_i2c() {
 	fi
 }
 
-function flash_lm4() {
-	OCD_CHIP_CFG="lm4_chip.cfg"
-	OCD_CMDS="init; flash_lm4 ${IMG} ${FLAGS_offset}; shutdown;"
-
-	flash_openocd
-
-}
-
-function flash_nrf51() {
-	OCD_CHIP_CFG="nrf51_chip.cfg"
-	OCD_CMDS="init; flash_nrf51 ${IMG} ${FLAGS_offset}; exit_debug_mode_nrf51; shutdown;"
-
-	flash_openocd
-
-	# waiting 100us for the reset pulse is not necessary, it takes ~2.5ms
-	dut_control swd_reset:on swd_reset:off
+function flash_it8xxx2() {
+	flash_ite_spi_ccd_i2c
 }
 
 function flash_npcx_jtag() {
 	IMG_PATH="${EC_DIR}/build/${BOARD}"
 	OCD_CHIP_CFG="npcx_chip.cfg"
-	if [ "${FLAGS_ro}" = ${FLAGS_TRUE} ] ; then
+	if [ "${FLAGS_ro}" = "${FLAGS_TRUE}" ] ; then
 		# Program RO region only
 		OCD_CMDS="init; flash_npcx_ro ${CHIP} ${IMG_PATH} ${FLAGS_offset}; shutdown;"
 	else
@@ -1363,21 +1473,30 @@ function flash_npcx_jtag() {
 }
 
 function flash_npcx_uut() {
-	local TOOL_PATH="${EC_DIR}/build/${BOARD}/util:$PATH"
-	local NPCX_UUT=$(PATH="${TOOL_PATH}" which uartupdatetool)
-	local EC_UART="$(servo_ec_uart)"
+	local NPCX_UUT
+	local EC_UART
+	local TEMP_SUFFIX
+	local TEMP_DIR
+	local TOOL_PATH="${EC_DIR}/build/${BOARD}/util:${PATH}"
+	NPCX_UUT=$(PATH="${TOOL_PATH}" which uartupdatetool)
+	EC_UART="$(servo_ec_uart)"
+	TEMP_SUFFIX=".$(basename "${SCRIPT}").${CHIP}.$$"
+	TEMP_DIR="$(mktemp -d --suffix="${TEMP_SUFFIX}")"
+	DELETE_LIST+=("${TEMP_DIR}")
 
 	# Look for npcx_monitor.bin in multiple directories, starting with
 	# the same path as the EC binary.
 	local MON=""
 	for dir in \
-		"$(dirname "$IMG")" \
+		"$(dirname "${IMG}")/chip/npcx/spiflashfw" \
+		"$(dirname "${IMG}")" \
 		"${EC_DIR}/build/${BOARD}/chip/npcx/spiflashfw" \
-		"$(dirname "$LOCAL_BUILD")" \
-		"$(dirname "$EMERGE_BUILD")" ;
+		"${EC_DIR}/build/zephyr/${BOARD}/output" \
+		"$(dirname "${LOCAL_BUILD}")" \
+		"$(dirname "${EMERGE_BUILD}")" ;
 	do
-		if [ -f "$dir/npcx_monitor.bin" ] ; then
-			MON="$dir/npcx_monitor.bin"
+		if [ -f "${dir}/npcx_monitor.bin" ] ; then
+			MON="${dir}/npcx_monitor.bin"
 			break
 		fi
 	done
@@ -1390,15 +1509,18 @@ function flash_npcx_uut() {
 	# The start address to restore monitor firmware binary
 	local MON_ADDR="0x200C3020"
 
-	if [ ! -x "$NPCX_UUT" ]; then
+	if [ ! -x "${NPCX_UUT}" ]; then
 		die "no NPCX UART Update Tool found."
 	fi
 
 	info "Using: NPCX UART Update Tool"
 	info "${MCU} UART pty : ${EC_UART}"
-	claim_pty ${EC_UART}
+	claim_pty "${EC_UART}"
 
 	if [[ "${SERVO_TYPE}" =~ "ccd_cr50" ]] ; then
+		# Ti50 does not yet support ccd_keepalive option which
+		# requires ccdstate command on the GSC console.
+		# TODO(b/161483597) remove the check when Ti50 CCD is on par.
 		servo_save_add ccd_keepalive_en
 		dut_control ccd_keepalive_en:on
 	fi
@@ -1409,11 +1531,11 @@ function flash_npcx_uut() {
 		c2d2_wait_for_h1_power_on_or_reset
 
 		# Don't let the EC come out of reset after H1 reset
-		dut_control ec_reset:on
+		dut_control gsc_ec_reset:on
 
 		# Force the EC to boot in UART update mode coming out of reset
 		ec_enable_boot0 "uut"
-		dut_control ec_reset:off
+		dut_control gsc_ec_reset:off
 
 		# Ensure normal UART operation
 		ec_disable_boot0 "uut"
@@ -1442,17 +1564,53 @@ function flash_npcx_uut() {
 				"--file=${MON}" )
 
 		# Load monitor binary to address 0x200C3020
-		if [[ "${FLAGS_verbose}" = ${FLAGS_TRUE} ]]; then
+		if [[ "${FLAGS_verbose}" = "${FLAGS_TRUE}" ]]; then
 			echo "${UUT_MON[*]}"
 		fi
+
+		local monitor_res=0
 		print_or_run timeout -k 10 -s 9 "${FLAGS_timeout}" \
-			"${UUT_MON[@]}" || die "Failed to load monitor binary."
+			"${UUT_MON[@]}" || monitor_res=$?
+
+		if [[ ${monitor_res} != 0 ]]; then
+			# Try to determine if WP is enabled
+			local dut_res=0
+			local wp_state
+			wp_state=$(dut-control fw_wp_state) || dut_res=$?
+
+			if [[ ${dut_res} = 0 ]]; then
+				if echo "${wp_state}" | grep "on"; then
+					die "Failed to load monitor binary, WP is enabled"
+				fi
+			fi
+
+			die "Failed to load monitor binary."
+		fi
+
+		if [[ "${FLAGS_no_preserve}" == "${FLAGS_FALSE}" ]]; then
+			local CUR_IMG
+			local PRESERVE_STATUS
+
+			PRESERVE_STATUS=0
+			is_preservation_needed "${IMG}" "${TEMP_DIR}" || PRESERVE_STATUS=$?
+			if [[ "${PRESERVE_STATUS}" -eq 0 ]]; then
+				info "Reading current EC firmware image."
+				CUR_IMG="${TEMP_DIR}/ec.cur.bin"
+				local UUT_CUR_RD=( "${NPCX_UUT}" "${UUT_ARGS[@]}"   \
+							"--read-flash" "--file=${CUR_IMG}" )
+				echo "${UUT_CUR_RD[*]}"
+				print_or_run timeout -k 10 -s 9 "${FLAGS_timeout}" \
+					"${UUT_CUR_RD[@]}" || die "${MSG_READ_FAIL}"
+
+				preserve_sections "${CUR_IMG}" "${IMG}" "${TEMP_DIR}"
+			fi
+		fi
 
 		info "Programming EC firmware image."
 		local UUT_WR=( "${NPCX_UUT}" "${UUT_ARGS[@]}"      \
 			       "--auto" "--offset=${FLAGS_offset}" \
 			       "--file=${IMG}" )
-		if [[ "${FLAGS_verbose}" = ${FLAGS_TRUE} ]]; then
+		if [[ "${FLAGS_verbose}" = "${FLAGS_TRUE}" ]]; then
 			echo "${UUT_WR[*]}"
 		fi
 		print_or_run timeout -k 10 -s 9 "${FLAGS_timeout}" \
@@ -1460,12 +1618,8 @@ function flash_npcx_uut() {
 
 		# If it is a program-verify request, then make a temporary
 		# directory to store the image.
-		if [[ "${FLAGS_verify}" == ${FLAGS_TRUE} ]]; then
-			local TEMP_SUFFIX=".$(basename ${SCRIPT}).${CHIP}.$$"
-			local TEMP_DIR="$(mktemp -d --suffix="${TEMP_SUFFIX}")"
-
+		if [[ "${FLAGS_verify}" == "${FLAGS_TRUE}" ]]; then
 			IMG_READ="${TEMP_DIR}/ec.read.bin"
-			DELETE_LIST+=( "${TEMP_DIR}" )
 		fi
 	fi
 
@@ -1476,7 +1630,7 @@ function flash_npcx_uut() {
 		local UUT_RD=( "${NPCX_UUT}" "${UUT_ARGS[@]}"   \
 			      "--read-flash" "--file=${IMG_READ}" )
 
-		if [[ "${FLAGS_verbose}" == ${FLAGS_TRUE} ]]; then
+		if [[ "${FLAGS_verbose}" == "${FLAGS_TRUE}" ]]; then
 			echo "${UUT_RD[*]}"
 		fi
 		print_or_run timeout -k 10 -s 9 "${FLAGS_timeout}" \
@@ -1485,10 +1639,10 @@ function flash_npcx_uut() {
 
 	# Verify the flash by comparing the source image to the read image,
 	# only if it was a flash write request.
-	if [[ -z "${FLAGS_read}" && "${FLAGS_verify}" == ${FLAGS_TRUE} ]]; then
+	if [[ -z "${FLAGS_read}" && "${FLAGS_verify}" == "${FLAGS_TRUE}" ]]; then
 		info "Verifying EC firmware image."
 
-		if [[ "${FLAGS_verbose}" == ${FLAGS_TRUE} ]]; then
+		if [[ "${FLAGS_verbose}" == "${FLAGS_TRUE}" ]]; then
 			echo "cmp -n ${IMG_SIZE} ${IMG} ${IMG_READ}"
 		fi
 
@@ -1521,8 +1675,37 @@ function flash_npcx_int_spi() {
 	flash_flashrom
 }
 
-function flash_mec1322() {
-	flash_flashrom
+function flash_mchp_int_spi() {
+	EC_UART="$(servo_ec_uart)"
+	EC_UART_PREFIX="$(servo_ec_uart_prefix)"
+
+	# Use of --value_only argument helps to get only baudrate value.
+	current_baudrate="$(dut_control_get "${EC_UART_PREFIX}"_baudrate)"
+
+	# On script exit, serial port will be configured back with saved
+	# baudrate by servo_restore thru cleanup method
+	servo_save_add "${EC_UART_PREFIX}_baudrate" "${current_baudrate}"
+
+	# Reset chip in firmware update mode
+	dut_control cold_reset:on fw_up:on cold_reset:off
+
+	# Set 9600 baudrate to program Second loader image
+	sec_load_baudrate=9600
+	if [ "${current_baudrate}" != "${sec_load_baudrate}" ] ; then
+	   dut_control "${EC_UART_PREFIX}"_baudrate:"${sec_load_baudrate}"
+	fi
+	# Load Second loader image into SRAM
+	mchp/crisis_rcvry_util.py -s "$(mchp_loader_image)" -p "${EC_UART}"
+
+	# Set 57600 baudrate to program EC image
+	image_load_baudrate=57600
+	dut_control "${EC_UART_PREFIX}"_baudrate:"${image_load_baudrate}"
+
+	# Flash EC image into the internal flash
+	mchp/crisis_rcvry_util.py -e "$(ec_image)" -p "${EC_UART}"
+
+	# Reset chip in firmware execution mode
+	dut_control cold_reset:on fw_up:off cold_reset:off
 }
 
 info "Using ${SERVO_TYPE}."
@@ -1538,6 +1721,44 @@ if [ "${NEED_SERVO}" != "no" ] ; then
 	servo_save
 fi
 
+function is_preservation_needed() {
+	local NEW_IMG
+	local TEMP_DIR
+
+	NEW_IMG=${1:?"missing arg 1: EC image path"}
+	NEW_IMG=$(readlink -f "${NEW_IMG}")
+	TEMP_DIR=${2:?"missing arg 2: Temp directory path"}
+
+	(
+		cd "${TEMP_DIR}"
+		dump_fmap "${NEW_IMG}" -e | grep -q ' preserve'
+	)
+}
+
+function preserve_sections() {
+	local CUR_IMG
+	local NEW_IMG
+	local TEMP_DIR
+
+	CUR_IMG=${1:?"missing arg 1: Cur EC image path"}
+	NEW_IMG=${2:?"missing arg 2: New EC image path"}
+	NEW_IMG=$(readlink -f "${NEW_IMG}")
+	TEMP_DIR=${3:?"missing arg 3: Temp directory path"}
+	(
+		cd "${TEMP_DIR}"
+		dump_fmap "${NEW_IMG}" -e | grep ' preserve' | cut \
+			-f1 -d' ' |
+		while read -r line
+		do
+			info "Preserving ${line} section on EC chip"
+			local SEC_IMG="${TEMP_DIR}/ec.cur.${line}.bin"
+
+			cbfstool "${CUR_IMG}" read -r "${line}" -f "${SEC_IMG}"
+			cbfstool "${NEW_IMG}" write -r "${line}" -f "${SEC_IMG}"
+		done
+	)
+}
+
 info "Flashing chip ${CHIP}."
-flash_${CHIP}
+flash_"${CHIP}"
 info "Flashing done."
diff --git a/util/flash_fp_mcu b/util/flash_fp_mcu
index 08dad05802..4229dedadd 100644
--- a/util/flash_fp_mcu
+++ b/util/flash_fp_mcu
@@ -1,5 +1,5 @@
 #!/bin/bash
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -19,46 +19,77 @@ DEFINE_boolean 'remove_flash_write_protect' "${FLAGS_TRUE}" \
 DEFINE_integer 'retries' "${DEFAULT_RETRIES}" 'Specify number of retries' 'R'
 DEFINE_integer 'baudrate' "${STM32MON_SERIAL_BAUDRATE}" 'Specify UART baudrate' 'B'
 DEFINE_boolean 'hello' "${FLAGS_FALSE}" 'Only ping the bootloader' 'H'
-FLAGS_HELP="Usage: ${0} [flags] ec.bin"
+DEFINE_boolean 'services' "${FLAGS_TRUE}" \
+  'Stop and restart conflicting fingerprint services' 's'
+FLAGS_HELP="Usage: ${0} [flags] [ec.bin]"
+
+#        EXIT_SUCCESS=0
+#        EXIT_FAILURE=1
+#        EXIT_BASHBUILTIN=2
+readonly EXIT_ARGUMENT=3
+readonly EXIT_CONFIG=4
+readonly EXIT_PRECONDITION=5
+readonly EXIT_RUNTIME=6
 
 # Process commandline flags
-FLAGS "${@}" || exit 1
+FLAGS "${@}" || exit "${EXIT_ARGUMENT}"
 eval set -- "${FLAGS_ARGV}"
 
-if [[ "$#" -eq 0 ]] && [[ "${FLAGS_hello}" -eq "${FLAGS_FALSE}" ]]; then
-  echo "Missing filename"
-  flags_help
-  exit 1
-fi
-
-# print out canonical path to differentiate between /usr/local/bin and
-# /usr/bin installs
-echo "$(readlink -f "$0")"
-
 readonly CROS_EC_SPI_MODALIAS_STR="of:NcrfpTCgoogle,cros-ec-spi"
+readonly CROS_EC_FP_SPI_MODALIAS_STR="spi:cros-ec-fp"
 
 readonly CROS_EC_UART_MODALIAS_STR="of:NcrfpTCgoogle,cros-ec-uart"
 
+klog() {
+  echo "flash_fp_mcu: $*" > /dev/kmsg
+}
+
 check_hardware_write_protect_disabled() {
-  local hardware_write_protect_state="$(crossystem wpsw_cur)"
+  local hardware_write_protect_state
+  if ! hardware_write_protect_state="$(crossystem wpsw_cur)"; then
+    echo "Failed to get hardware write protect status" >&2
+    exit "${EXIT_PRECONDITION}"
+  fi
   if [[ "${hardware_write_protect_state}" != "0" ]]; then
-    echo "Please make sure hardware write protect is disabled."
+    echo "Unable to proceed because hardware write protect is enabled."
+    echo "Please disable the hardware write protect, so that we can" \
+    "reboot the FPMCU into the ROM bootloader."
     echo "See https://www.chromium.org/chromium-os/firmware-porting-guide/firmware-ec-write-protection"
-    exit 1
+    exit "${EXIT_PRECONDITION}"
   fi
 }
 
+# Get the gpiochip base number from sysfs that matches
+# a device path
+get_sysfs_gpiochip_base() {
+  local match="${1}"
+
+  for chip in /sys/class/gpio/gpiochip*
+  do
+    case "$(readlink ${chip})" in
+     ${match})
+      echo "${chip#/sys/class/gpio/gpiochip}"
+      return 0
+      ;;
+    esac
+  done
+
+  return 1
+}
+
 # Get the spiid for the fingerprint sensor based on the modalias
 # string: https://crbug.com/955117
 get_spiid() {
   for dev in /sys/bus/spi/devices/*; do
-    if [[ "$(cat "${dev}/modalias")" == "${CROS_EC_SPI_MODALIAS_STR}" ]]; then
-      echo "$(basename "${dev}")"
-      exit 0
-    fi
+    case "$(cat "${dev}/modalias")" in
+      "${CROS_EC_SPI_MODALIAS_STR}"|"${CROS_EC_FP_SPI_MODALIAS_STR}")
+        basename "${dev}"
+        return 0
+        ;;
+    esac
   done
 
-  exit 1
+  return 1
 }
 
 # Get the uartid for the fingerprint sensor based on the modalias
@@ -66,17 +97,69 @@ get_uartid() {
   for dev in /sys/bus/serial/devices/*; do
     if [ -f "${dev}/modalias" ]; then
       if [[ "$(cat "${dev}/modalias")" == "${CROS_EC_UART_MODALIAS_STR}" ]]; then
-        echo "$(basename "${dev}")"
-        exit 0
+        basename "${dev}"
+        return 0
       fi
     fi
   done
 
-  exit 1
+  return 1
+}
+
+# Usage: gpio <unexport|export|in|out|0|1|get> <signal> [signal...]
+gpio() {
+  local cmd="$1"
+  shift
+
+  for signal in "$@"; do
+    case "${cmd}" in
+      unexport|export)
+        klog "Set gpio ${signal} to ${cmd}"
+        echo "${signal}" > "/sys/class/gpio/${cmd}"
+        ;;
+      in|out)
+        local direction="${cmd}"
+        klog "Set gpio ${signal} direction to ${direction}"
+        echo "${direction}" > "/sys/class/gpio/gpio${signal}/direction"
+        ;;
+      0|1)
+        local value="${cmd}"
+        klog "Set gpio ${signal} to ${value}"
+        echo "${value}" > "/sys/class/gpio/gpio${signal}/value"
+        ;;
+      get)
+        local value="${cmd}"
+        klog "Get gpio ${signal}"
+        cat "/sys/class/gpio/gpio${signal}/value"
+        ;;
+      *)
+        echo "Invalid gpio command: ${cmd}" >&2
+        exit "${EXIT_RUNTIME}"
+        ;;
+    esac
+  done
+}
+
+# Usage: warn_gpio <signal> <expected_value> <msg>
+warn_gpio() {
+  local signal=$1
+  local expected_value=$2
+  local msg=$3
+
+  local value
+  if ! value="$(gpio get "${signal}")"; then
+    echo "Error fetching gpio value ${signal}" >&2
+    exit "${EXIT_RUNTIME}"
+  fi
+
+  if [[ "${value}" != "${expected_value}" ]]; then
+    echo "${msg}" >&2
+    return 1
+  fi
 }
 
 # Taken verbatim from
-# https://chromium.googlesource.com/chromiumos/docs/+/master/lsb-release.md#shell
+# https://chromium.googlesource.com/chromiumos/docs/+/HEAD/lsb-release.md#shell
 # This should not be used by anything except get_platform_name.
 # See https://crbug.com/98462.
 lsbval() {
@@ -97,6 +180,8 @@ lsbval() {
 
 # Get the underlying board (reference design) that we're running on (not the
 # FPMCU or sensor).
+# This may be an extended platform name, like nami-kernelnext, hatch-arc-r,
+# or hatch-borealis.
 get_platform_name() {
   local platform_name
 
@@ -117,18 +202,87 @@ get_platform_name() {
   echo "Getting platform name from /etc/lsb-release." 1>&2
   platform_name="$(lsbval "CHROMEOS_RELEASE_BOARD")"
   if [[ -z "${platform_name}" ]]; then
-    exit 1
+    return 1
   fi
 
   echo "${platform_name}"
 }
 
-check_gpio_chip_exists() {
-  local gpiochip="$1"
-  if [[ ! -e "/sys/class/gpio/${gpiochip}" ]]; then
-    echo "Cannot find GPIO chip: ${gpiochip}"
-    exit 1
+# Test the current running kernel version against a regular expression.
+# Returns 0 if the regex matches.
+match_kernel_regex() {
+  local match_exp=$1
+  local kversion
+  kversion=$(uname -r)
+  [[ $kversion =~ $match_exp ]]
+  return $?
+}
+
+# Given a full platform name, extract the base platform.
+#
+# Tests are also run on modified images, like hatch-arc-r, hatch-borealis, or
+# hatch-kernelnext. These devices still have fingerprint and are expected to
+# pass tests. The full platform name reflects these modifications and might
+# be needed to apply an alternative configuration (kernelnext). Other modified
+# tests (arc-r) just need to default to the base platform config, which is
+# identified by this function.
+# See b/186697064.
+#
+# Examples:
+# * platform_base_name "hatch-kernelnext" --> "hatch"
+# * platform_base_name "hatch-arc-r"      --> "hatch"
+# * platform_base_name "hatch-borealis"   --> "hatch"
+# * platform_base_name "hatch"            --> "hatch"
+# * platform_base_name "strongbad64"      --> "strongbad"
+#
+# Usage: platform_base_name <platform_name>
+platform_base_name() {
+  local platform_name="$1"
+
+  # We remove any suffix starting at the first '-'.
+  local base_name="${platform_name%%-*}"
+
+  # Remove any numbers from the base name.
+  echo "${base_name//[0-9]/}"
+}
+
+get_default_fw() {
+  local board
+  board="$(cros_config /fingerprint board)"
+
+  # If cros_config returns "", that is okay assuming there is only
+  # one firmware file on disk.
+
+  local -a fws
+  mapfile -t fws < <(find /opt/google/biod/fw -name "${board}*.bin")
+
+  if [[ "${#fws[@]}" -ne 1 ]]; then
+    return 1
   fi
+
+  echo "${fws[0]}"
+}
+
+# Find processes that have the named file, active or deleted, open.
+#
+# Deleted files are important because unbinding/rebinding cros-ec
+# with biod/timberslide running will result in the processes holding open
+# a deleted version of the files. Issues can arise if the process continue
+# to interact with the deleted files (ex kernel panic) while the raw driver
+# is being used in flash_fp_mcu. The lsof and fuser tools can't seem to
+# identify usages of the deleted named file directly, without listing all
+# files. This takes a large amount out time on Chromebooks, thus we need this
+# custom search routine.
+#
+# Usage: proc_open_file [file_pattern]
+proc_open_file() {
+  local file_pattern="$1"
+
+  # Avoid overloading kernel max arguments with the number of file names.
+  local -a FDS=( /proc/*/fd/* )
+  xargs ls -l <<<"${FDS[*]}" 2>/dev/null | grep "${file_pattern}" | \
+    awk '{split($9,p,"/"); print "PID", p[3], "->", $11, $12}'
+  return "${PIPESTATUS[1]}"
 }
 
 flash_fp_mcu_stm32() {
@@ -161,87 +315,113 @@ flash_fp_mcu_stm32() {
       # Read from FPMCU to file
       if [[ -e "${file}" ]]; then
         echo "Output file already exists: ${file}"
-        exit 1
+        return "${EXIT_PRECONDITION}"
       fi
+      echo "# Reading to '${file}' over ${transport}"
       stm32mon_flags+=" -r ${file}"
     else
       # Write to FPMCU from file
       if [[ ! -f "${file}" ]]; then
         echo "Invalid image file: ${file}"
-        exit 1
+        return "${EXIT_PRECONDITION}"
       fi
+      echo "# Flashing '${file}' over ${transport}"
       stm32mon_flags+=" -e -w ${file}"
     fi
+  else
+    echo "# Saying hello over ${transport}"
   fi
 
 
   check_hardware_write_protect_disabled
 
   if [[ "${transport}" == "UART" ]]; then
-    deviceid="$(get_uartid)"
-    if [[ $? -ne 0 ]]; then
+    if ! deviceid="$(get_uartid)"; then
+      # Failure to get Device ID when transport is UART is not critical.
+      # Cros-ec-uart driver was built on top of serial bus. Serial bus is
+      # created on top of UART driver (in our case it's dw-apb-uart).
+      # To get /dev/ttyS1 device, we need to unbind cros-ec-uart and rebind
+      # dw-apb-uart driver which creates ttyS1, but destroyes the serial bus.
+      # If we can't get the Device ID, it means that dw-apb-uart was rebound
+      # previously.
       echo "Unable to find FP sensor UART device: ${CROS_EC_UART_MODALIAS_STR}"
-      exit 1
     fi
   else
-    deviceid="$(get_spiid)"
-    if [[ $? -ne 0 ]]; then
+    if ! deviceid="$(get_spiid)"; then
+      # Failure to get Device ID when transport is SPI is critical.
+      # It means that the FPMCU is missing on the device or it's not defined
+      # in ACPI properly.
       echo "Unable to find FP sensor SPI device: ${CROS_EC_SPI_MODALIAS_STR}"
-      exit 1
+      return "${EXIT_PRECONDITION}"
     fi
   fi
 
-  echo "Flashing ${transport} device ID: ${deviceid}"
-
-  # Ensure the ACPI is not cutting power when unloading cros-ec-spi
-  if [[ "${gpio_pwren}" -gt 0 ]]; then
-    echo "${gpio_pwren}" > /sys/class/gpio/export
-    echo "out" > "/sys/class/gpio/gpio${gpio_pwren}/direction"
-    echo 1 > "/sys/class/gpio/gpio${gpio_pwren}/value"
-  fi
+  # Unbind cros-ec driver
+  if [[ ! -z "${deviceid}" ]]; then
+    klog "Unbinding cros-ec driver"
+    if [[ "${transport}" == "UART" ]]; then
+      echo "${deviceid}" > /sys/bus/serial/drivers/cros-ec-uart/unbind
+    else
+      echo "${deviceid}" > /sys/bus/spi/drivers/cros-ec-spi/unbind
+    fi
 
-  # Remove cros_fp if present
-  if [[ "${transport}" == "UART" ]]; then
-    echo "${deviceid}" > /sys/bus/serial/drivers/cros-ec-uart/unbind
-  else
-    echo "${deviceid}" > /sys/bus/spi/drivers/cros-ec-spi/unbind
+    echo "Flashing ${transport} device ID: ${deviceid}"
   fi
 
   # Configure the MCU Boot0 and NRST GPIOs
-  echo "${gpio_boot0}" > /sys/class/gpio/export
-  echo "out" > "/sys/class/gpio/gpio${gpio_boot0}/direction"
-  echo "${gpio_nrst}" > /sys/class/gpio/export
-  echo "out" > "/sys/class/gpio/gpio${gpio_nrst}/direction"
+  gpio export "${gpio_boot0}" "${gpio_nrst}"
+  gpio out    "${gpio_boot0}" "${gpio_nrst}"
 
   # Reset sequence to enter bootloader mode
-  echo 1 > "/sys/class/gpio/gpio${gpio_boot0}/value"
-  echo 0 > "/sys/class/gpio/gpio${gpio_nrst}/value"
+  gpio 1 "${gpio_boot0}"
+  gpio 0 "${gpio_nrst}"
   sleep 0.001
 
+  klog "Binding raw driver"
   if [[ "${transport}" == "UART" ]]; then
-    # load AMD0020:01 ttyS1
-    echo AMD0020:01 > /sys/bus/platform/drivers/dw-apb-uart/unbind;
-    echo AMD0020:01 > /sys/bus/platform/drivers/dw-apb-uart/bind;
+    # load AMDI0020:01 ttyS1
+    echo AMDI0020:01 > /sys/bus/platform/drivers/dw-apb-uart/unbind;
+    echo AMDI0020:01 > /sys/bus/platform/drivers/dw-apb-uart/bind;
   else
-    # load spidev (fail on cros-ec-spi first to change modalias)
-    echo "${deviceid}" > /sys/bus/spi/drivers/cros-ec-spi/bind 2>/dev/null
+    echo spidev > "/sys/bus/spi/devices/${deviceid}/driver_override"
     echo "${deviceid}" > /sys/bus/spi/drivers/spidev/bind
     # The following sleep is a workaround to mitigate the effects of a
     # poorly behaved chip select line. See b/145023809.
   fi
   sleep 0.5
 
+  # We do not expect the drivers to change the pin state when binding.
+  # If you receive this warning, the driver needs to be fixed on this board
+  # and this flash attempt will probably fail.
+  warn_gpio "${gpio_boot0}" 1 \
+    "WARNING: One of the drivers changed BOOT0 pin state on bind attempt."
+  warn_gpio "${gpio_nrst}" 0 \
+    "WARNING: One of the drivers changed NRST pin state on bind attempt."
+
+  if [[ ! -c "${device}" ]]; then
+    echo "Failed to bind raw device driver." >&2
+    return "${EXIT_RUNTIME}"
+  fi
+
   local attempt=0
   local cmd_exit_status=1
   local cmd="stm32mon ${stm32mon_flags}"
 
-  for attempt in $(seq ${FLAGS_retries}); do
+  for attempt in $(seq "${FLAGS_retries}"); do
     # Reset sequence to enter bootloader mode
-    echo 0 > "/sys/class/gpio/gpio${gpio_nrst}/value"
+    gpio 0 "${gpio_nrst}"
     sleep 0.01
 
     # Release reset as the SPI bus is now ready
-    echo 1 > "/sys/class/gpio/gpio${gpio_nrst}/value"
+    gpio 1 "${gpio_nrst}"
+
+    # As per section '68: Bootloader timings' from application note below:
+    # https://www.st.com/resource/en/application_note/cd00167594-stm32-microcontroller-system-memory-boot-mode-stmicroelectronics.pdf
+    # bootloader startup time is 16.63 ms for STM32F74xxx/75xxx and 53.975 ms
+    # for STM32H74xxx/75xxx. SPI needs 1 us delay for one SPI byte sending.
+    # Keeping some margin, add delay of 100 ms to consider minimum bootloader
+    # startup time after the reset for stm32 devices.
+    sleep 0.1
 
     # Print out the actual underlying command we're running and run it
     echo "# ${cmd}"
@@ -258,50 +438,87 @@ flash_fp_mcu_stm32() {
 
   # unload device
   if [[ "${transport}" != "UART" ]]; then
+    klog "Unbinding raw driver"
     echo "${deviceid}" > /sys/bus/spi/drivers/spidev/unbind
   fi
 
   # Go back to normal mode
-  echo "out" > "/sys/class/gpio/gpio${gpio_nrst}/direction"
-  echo 0 > "/sys/class/gpio/gpio${gpio_boot0}/value"
-  echo 0 > "/sys/class/gpio/gpio${gpio_nrst}/value"
-  echo 1 > "/sys/class/gpio/gpio${gpio_nrst}/value"
+  gpio 0   "${gpio_boot0}"
 
-  # Give up GPIO control
-  echo "in" > "/sys/class/gpio/gpio${gpio_boot0}/direction"
-  echo "in" > "/sys/class/gpio/gpio${gpio_nrst}/direction"
-  echo "${gpio_boot0}" > /sys/class/gpio/unexport
-  echo "${gpio_nrst}" > /sys/class/gpio/unexport
+  # Dartmonkey's RO has a flashprotect logic issue that forces reboot loops
+  # when SW-WP is enabled and HW-WP is disabled. It is avoided if a POR is
+  # detected on boot. We force a POR here to ensure we avoid this reboot loop.
+  # See to b/146428434.
+  if [[ "${gpio_pwren}" -gt 0 ]]; then
+    echo "Power cycling the FPMCU."
+    gpio export "${gpio_pwren}"
+    gpio out    "${gpio_pwren}"
+    gpio 0      "${gpio_pwren}"
+    # Must outlast hardware soft start, which is typically ~3ms.
+    sleep 0.5
+    gpio 1      "${gpio_pwren}"
+    # Power enable line is externally pulled down, so leave as output-high.
+    gpio unexport "${gpio_pwren}"
+  else
+    echo "Reset the FPMCU."
+    gpio out	"${gpio_nrst}"
+    gpio 0	"${gpio_nrst}"
+    # Make sure that we keep nRST line low long enough.
+    sleep 0.01
+    gpio 1	"${gpio_nrst}"
+  fi
 
-  # wait for FP MCU to come back up (including RWSIG delay)
-  sleep 2
+  # Give up GPIO control, unless we need to keep these driving as
+  # outputs because they're not open-drain signals.
+  # TODO(b/179839337): Make this the default and properly support
+  # open-drain outputs on other platforms.
+  if [[ "${PLATFORM_BASE_NAME}" != "strongbad" ]] &&
+     [[ "${PLATFORM_BASE_NAME}" != "herobrine" ]] &&
+     [[ "${PLATFORM_BASE_NAME}" != "zork" ]] &&
+     [[ "${PLATFORM_BASE_NAME}" != "myst" ]] &&
+     [[ "${PLATFORM_BASE_NAME}" != "skyrim" ]]; then
+    gpio in       "${gpio_boot0}" "${gpio_nrst}"
+  fi
+  gpio unexport "${gpio_boot0}" "${gpio_nrst}"
 
   # Put back cros_fp driver if transport is SPI
   if [[ "${transport}" != "UART" ]]; then
+    # wait for FP MCU to come back up (including RWSIG delay)
+    sleep 2
+    klog "Binding cros-ec driver"
+    echo "" > "/sys/bus/spi/devices/${deviceid}/driver_override"
     echo "${deviceid}" > /sys/bus/spi/drivers/cros-ec-spi/bind
-
-    # Kernel driver is back, we are no longer controlling power
-    if [[ "${gpio_pwren}" -gt 0 ]]; then
-      echo "${gpio_pwren}" > /sys/class/gpio/unexport
-    fi
+  else
+    # FPMCU can still have ro_now protection (sector write protection) enabled
+    # e.g. when flash_fp_mcu was run with --read option. It is disabled when
+    # FPMCU boots with HW write protect disabled.
+    # Disabling sector write protection takes some time due to flash internal
+    # structures update. During that time we can't reset or power cycle FPMCU
+    # otherwise we will corrupt internal flash state which will brick FPMCU.
+    # This situation can occur if DUT is rebooted immediately after flash_fp_mcu
+    # finishes, so give some time to remove sector write protection. No need to
+    # wait if transport is SPI because later we query for version and reset
+    # flags.
+    sleep 3
   fi
 
   if [[ "${cmd_exit_status}" -ne 0 ]]; then
-    exit 1
+    return "${EXIT_RUNTIME}"
   fi
 
   # Inform user to reboot if transport is UART.
-  # Display fw version is transport is SPI 
+  # Display fw version is transport is SPI
   if [[ "${transport}" == "UART" ]]; then
     echo "Please reboot this device."
   else
     # Test it
+    klog "Query version and reset flags"
     ectool --name=cros_fp version
+    ectool --name=cros_fp uptimeinfo
   fi
 }
 
 config_hatch() {
-  check_gpio_chip_exists "gpiochip200"
   readonly TRANSPORT="SPI"
   readonly DEVICE="/dev/spidev1.1"
   # See
@@ -309,21 +526,57 @@ config_hatch() {
   # for pin name to number mapping.
   # Examine `cat /sys/kernel/debug/pinctrl/INT34BB:00/gpio-ranges` on a hatch
   # device to determine gpio number from pin number.
-  # FPMCU RST_ODL is on GPP_A12 = 200 + 12 = 212
-  readonly GPIO_NRST=212
-  # FPMCU BOOT0 is on GPP_A22 = 200 + 22 = 222
-  readonly GPIO_BOOT0=222
-  # FP_PWR_EN is on GPP_C11 = 456 + (192 - 181) = 456 + 11 = 467
-  readonly GPIO_PWREN=467
+
+  local gpiochip_dev_path="*/pci0000\:00/INT34BB\:00/gpio/*"
+  local gpiobase
+  if ! gpiobase=$(get_sysfs_gpiochip_base "${gpiochip_dev_path}"); then
+    echo "Unable to find gpio chip base"
+    return "${EXIT_PRECONDITION}"
+  fi
+
+  local GPIO_CHIP="gpiochip${gpiobase}"
+
+  # FPMCU RST_ODL is on GPP_A12 = 12
+  local gpionrst=12
+  readonly GPIO_NRST=$(( gpionrst + gpiobase ))
+  # FPMCU BOOT0 is on GPP_A22 = 22
+  local gpioboot=22
+  readonly GPIO_BOOT0=$(( gpioboot + gpiobase ))
+  # FP_PWR_EN is on GPP_C11 = 256 + 11 = 267
+  local gpiopwren=267
+  readonly GPIO_PWREN=$(( gpiopwren + gpiobase ))
 }
 
+config_herobrine() {
+  readonly TRANSPORT="SPI"
+  readonly DEVICE="/dev/spidev9.0"
+
+  local dev_path="*/platform/soc@0/f100000.pinctrl/gpio/*"
+  local gpiobase
+  if ! gpiobase=$(get_sysfs_gpiochip_base "${dev_path}"); then
+    echo "Unable to find gpio chip base"
+    return "${EXIT_PRECONDITION}"
+  fi
+
+  readonly GPIO_CHIP="gpiochip${gpiobase}"
+  # FPMCU RST_ODL is $(gpiofind FP_RST_L) is gpiochip0 22
+  readonly GPIO_NRST=$((${gpiobase} + $(gpiofind FP_RST_L|cut -f2 -d" ")))
+  # FPMCU BOOT0 is $(gpiofind FPMCU_BOOT0) is gpiochip0 10
+  readonly GPIO_BOOT0=$((${gpiobase} + $(gpiofind FPMCU_BOOT0|cut -f2 -d" ")))
+
+  # EN FP RAILS is $(gpiofind EN_FP_RAILS) is gpiochip0 42
+  readonly GPIO_PWREN=$((${gpiobase} + $(gpiofind EN_FP_RAILS|cut -f2 -d" ")))
+}
 
 config_nami() {
-  check_gpio_chip_exists "gpiochip360"
+  local device="/dev/spidev1.0"
+  # Support kernel version 4.4 during transition to 5.4
+  match_kernel_regex "^4\.4\." && device="/dev/spidev32765.0"
 
   readonly TRANSPORT="SPI"
-  readonly DEVICE="/dev/spidev32765.0"
+  readonly DEVICE="${device}"
 
+  readonly GPIO_CHIP="gpiochip360"
   # FPMCU RST_ODL is on GPP_C9 = 360 + 57 = 417
   readonly GPIO_NRST=417
   # FPMCU BOOT0 is on GPP_D5 = 360 + 77 = 437
@@ -333,11 +586,14 @@ config_nami() {
 }
 
 config_nocturne() {
-  check_gpio_chip_exists "gpiochip360"
+  local device="/dev/spidev1.0"
+  # Support kernel version 4.4 during transition to 5.10
+  match_kernel_regex "^4\.4\." && device="/dev/spidev32765.0"
 
   readonly TRANSPORT="SPI"
-  readonly DEVICE="/dev/spidev32765.0"
+  readonly DEVICE="${device}"
 
+  readonly GPIO_CHIP="gpiochip360"
   # FPMCU RST_ODL is on GPP_C10 = 360 + 58 = 418
   readonly GPIO_NRST=418
   # FPMCU BOOT0 is on GPP_C8 = 360 + 56 = 416
@@ -346,9 +602,33 @@ config_nocturne() {
   readonly GPIO_PWREN=371
 }
 
-config_volteer() {
-  check_gpio_chip_exists "gpiochip152"
+config_strongbad() {
+  readonly TRANSPORT="SPI"
+  readonly DEVICE="/dev/spidev10.0"
+
+  local dev_path="*/platform/soc@0/3500000.pinctrl/gpio/*"
+  local gpiobase
+  if ! gpiobase=$(get_sysfs_gpiochip_base "${dev_path}"); then
+    echo "Unable to find gpio chip base"
+    return "${EXIT_PRECONDITION}"
+  fi
+
+  readonly GPIO_CHIP="gpiochip${gpiobase}"
+  # FPMCU RST_ODL is $(gpiofind FP_RST_L) is gpiochip0 22
+  readonly GPIO_NRST=$((${gpiobase} + $(gpiofind FP_RST_L|cut -f2 -d" ")))
+  # FPMCU BOOT0 is $(gpiofind FPMCU_BOOT0) is gpiochip0 10
+  readonly GPIO_BOOT0=$((${gpiobase} + $(gpiofind FPMCU_BOOT0|cut -f2 -d" ")))
+
+  # EN FP RAILS is $(gpiofind EN_FP_RAILS) is gpiochip0 74 (if available)
+  local en_fp_rails
+  if en_fp_rails=$(gpiofind EN_FP_RAILS); then
+    readonly GPIO_PWREN=$((${gpiobase} + $(echo $en_fp_rails|cut -f2 -d" ")))
+  else
+    readonly GPIO_PWREN=-1
+  fi
+}
 
+config_volteer() {
   readonly TRANSPORT="SPI"
   readonly DEVICE="/dev/spidev1.0"
 
@@ -358,59 +638,313 @@ config_volteer() {
   # volteer device to determine gpio number from pin number.
   # For example: GPP_C23 is UART2_CTS which can be queried from EDS
   # the pin number is 194. From the gpio-ranges, the gpio value is
-  # 408 + (194-171) = 431
-
-  # FPMCU RST_ODL is on GPP_C23 = 408 + (194 - 171) = 431
-  readonly GPIO_NRST=431
-  # FPMCU BOOT0 is on GPP_C22 = 408 + (193 - 171) = 430
-  readonly GPIO_BOOT0=430
-  # FP_PWR_EN is on GPP_A21 = 216 + (63 - 42) = 237
-  readonly GPIO_PWREN=237
+  # 920 + (194-171) = 943. The relative gpio value is 943 - 664 = 279.
+
+  local gpiochip_dev_path="*/pci0000\:00/INT34C5\:00/gpio/*"
+  local gpiobase
+  if ! gpiobase=$(get_sysfs_gpiochip_base "${gpiochip_dev_path}"); then
+    echo "Unable to find gpio chip base"
+    return "${EXIT_PRECONDITION}"
+  fi
+
+  local GPIO_CHIP="gpiochip${gpiobase}"
+
+  # FPMCU RST_ODL is on GPP_C23 = 256 + (194 - 171) = 279
+  local gpionrst=279
+  readonly GPIO_NRST=$(( gpionrst + gpiobase ))
+  # FPMCU BOOT0 is on GPP_C22 = 256 + (193 - 171) = 278
+  local gpioboot=278
+  readonly GPIO_BOOT0=$(( gpioboot + gpiobase ))
+  # FP_PWR_EN is on GPP_A21 = 64 + (63 - 42) = 85
+  local gpiopwren=85
+  readonly GPIO_PWREN=$(( gpiopwren + gpiobase ))
+}
+
+config_brya() {
+  readonly TRANSPORT="SPI"
+  readonly DEVICE="/dev/spidev0.0"
+
+  # See kernel/v5.10/drivers/pinctrl/intel/pinctrl-tigerlake.c
+  # for pin name and pin number.
+  # Examine `cat /sys/kernel/debug/pinctrl/INTC1055:00/gpio-ranges` on a
+  # brya device to determine gpio number from pin number.
+  # For example: GPP_D1 is ISH_GP_1 which can be queried from EDS
+  # the pin number is 100 from the pinctrl-tigerlake.c.
+  # From the gpio-ranges, the gpio value is 824 + (100-99) = 825
+
+  local gpiochip="gpiochip664"
+  # Support kernel version 5.10 during transition to 5.15+
+  match_kernel_regex "^5\.10\." && gpiochip="gpiochip152"
+  readonly GPIO_CHIP="${gpiochip}"
+
+  local offset=0
+  # Support kernel version 5.10 during transition to 5.15+
+  # v5.10 has GPIOs that are offset by -512
+  match_kernel_regex "^5\.10\." && offset=512
+
+  # FPMCU RST_ODL is on GPP_D1 = 824 + (100 - 99) = 825
+  local gpionrst=825
+  readonly GPIO_NRST=$(( gpionrst - offset ))
+  # FPMCU BOOT0 is on GPP_D0 = 824 + (99 - 99) = 824
+  local gpioboot=824
+  readonly GPIO_BOOT0=$(( gpioboot - offset ))
+  # FP_PWR_EN is on GPP_D2 = 824 + (101 - 99) = 826
+  local gpiopwren=826
+  readonly GPIO_PWREN=$(( gpiopwren - offset ))
+}
+
+config_brask() {
+  # Let's call the config_brya since brask follows the brya HW design
+  config_brya
+}
+
+config_ghost() {
+  # No changes to brya.
+  config_brya
+}
+
+config_rex() {
+  readonly TRANSPORT="SPI"
+  readonly DEVICE="/dev/spidev0.0"
+
+  # See kernel/v6.1/drivers/pinctrl/intel/pinctrl-meteorlake.c
+  # for pin name and pin number.
+  # Examine `cat /sys/kernel/debug/pinctrl/INTC1083:00/gpio-ranges` on a
+  # rex device to determine gpio number from pin number.
+  # For example: GPP_B11, the pin number is 215 from the pinctrl-meteorlake.c.
+  # From the gpio-ranges, the gpio value is 925 + (215-204) = 936
+
+  local gpiochip_dev_path="*/pci0000:00/INTC1083\:00/gpio/*"
+  local gpiobase
+  if ! gpiobase=$(get_sysfs_gpiochip_base "${gpiochip_dev_path}"); then
+    echo "Unable to find gpio chip base"
+    return "${EXIT_PRECONDITION}"
+  fi
+
+  readonly GPIO_CHIP="gpiochip${gpiobase}"
+
+  local model=$(cros_config / name)
+  case "${model}" in
+    screebo)
+      # Screebo is based off Rex but with different pins for FPMCU
+      # FPMCU RST_ODL is on GPP_C21 = 64 + (50 - 29) = 85
+      local gpionrst=85
+      readonly GPIO_NRST=$(( gpionrst + gpiobase ))
+      # FPMCU BOOT0 is on GPP_C20 = 64 + (49 - 29) = 84
+      local gpioboot=84
+      readonly GPIO_BOOT0=$(( gpioboot + gpiobase ))
+      # FP_PWR_EN is on GPP_B08 = 352 + (212-204) - 573 = 360
+      local gpiopwren=360
+      readonly GPIO_PWREN=$(( gpiopwren + gpiobase ))
+      ;;
+    *)
+      # FPMCU RST_ODL is on GPP_C23 = 64 + (52 - 29) = 87
+      local gpionrst=87
+      readonly GPIO_NRST=$(( gpionrst + gpiobase ))
+      # FPMCU BOOT0 is on GPP_C22 = 64 + (51 - 29) = 86
+      local gpioboot=86
+      readonly GPIO_BOOT0=$(( gpioboot + gpiobase ))
+      # FP_PWR_EN is on GPP_B11 = 352 + (215-204) = 363
+      local gpiopwren=363
+      readonly GPIO_PWREN=$(( gpiopwren + gpiobase ))
+      ;;
+  esac
 }
 
 config_zork() {
-  check_gpio_chip_exists "gpiochip320"
+  readonly TRANSPORT="UART"
+  readonly DEVICE="/dev/ttyS1"
+
+  local gpiochip="gpiochip768"
+  # Support kernel version 5.4 during transition to 5.15+
+  match_kernel_regex "^5\.4\." && gpiochip="gpiochip256"
+  readonly GPIO_CHIP="${gpiochip}"
+
+  local offset=0
+  # Support kernel version 5.4 during transition to 5.15+
+  # v5.4 has GPIOs that are offset by -512
+  match_kernel_regex "^5\.4\." && offset=512
+
+  # FPMCU RST_ODL is on AGPIO 11 = 768 + 11 = 779
+  local gpionrst=779
+  readonly GPIO_NRST=$(( gpionrst - offset ))
+  # FPMCU BOOT0 is on AGPIO 69 = 768 + 69 = 837
+  local gpioboot=837
+  readonly GPIO_BOOT0=$(( gpioboot - offset ))
+  # FPMCU PWR_EN is on AGPIO 32 = 768 + 32 = 800
+  local gpiopwren=800
+  readonly GPIO_PWREN=$(( gpiopwren - offset ))
+}
+
+config_guybrush() {
+  readonly TRANSPORT="UART"
+  readonly DEVICE="/dev/ttyS1"
+
+  local gpiochip_dev_path="*/platform/AMD0030\:00/gpio/*"
+  local gpiobase
+  if ! gpiobase=$(get_sysfs_gpiochip_base "${gpiochip_dev_path}"); then
+    echo "Unable to find gpio chip base"
+    return "${EXIT_PRECONDITION}"
+  fi
+
+  local GPIO_CHIP="gpiochip${gpiobase}"
+
+  # FPMCU RST_ODL is on AGPIO 11
+  local gpionrst=11
+  readonly GPIO_NRST=$(( gpionrst + gpiobase ))
+  # FPMCU BOOT0 is on AGPIO 144
+  local gpioboot=144
+  readonly GPIO_BOOT0=$(( gpioboot + gpiobase ))
+  # FPMCU PWR_EN is on AGPIO 3
+  local gpiopwren=3
+  readonly GPIO_PWREN=$(( gpiopwren + gpiobase ))
+}
+
+config_skyrim() {
+  readonly TRANSPORT="UART"
 
+  readonly DEVICE="/dev/ttyS1"
+
+  readonly GPIO_CHIP="gpiochip768"
+  # FPMCU RST_ODL is on AGPIO 12 = 768 + 12 = 780
+  readonly GPIO_NRST=780
+  # FPMCU BOOT0 is on AGPIO 130 = 768 + 130 = 898
+  readonly GPIO_BOOT0=898
+  # FPMCU PWR_EN is on AGPIO 4 = 768 + 4 = 772
+  readonly GPIO_PWREN=772
+}
+
+config_myst() {
   readonly TRANSPORT="UART"
 
   readonly DEVICE="/dev/ttyS1"
 
-  # FPMCU RST_ODL is on AGPIO 11 = 320 + 11 = 331
-  readonly GPIO_NRST=331
-  # FPMCU BOOT0 is on AGPIO 69 = 320 + 69 = 389
-  readonly GPIO_BOOT0=389
-  # FPMCU PWR_EN is not available on Zork. Set invalid value
-  readonly GPIO_PWREN=-1
+  readonly GPIO_CHIP="gpiochip768"
+  # FPMCU RST_ODL is on AGPIO 40 = 768 + 40 = 808
+  readonly GPIO_NRST=808
+  # FPMCU BOOT0 is on AGPIO 132 = 768 + 132 = 900
+  readonly GPIO_BOOT0=900
+  # FPMCU PWR_EN is on AGPIO 4 = 768 + 4 = 772
+  readonly GPIO_PWREN=772
+}
+
+main() {
+  local filename="$1"
+
+  # print out canonical path to differentiate between /usr/local/bin and
+  # /usr/bin installs
+  readlink -f "$0"
+
+  # The "platform name" corresponds to the underlying board (reference design)
+  # that we're running on (not the FPMCU or sensor). At the moment all of the
+  # reference designs use the same GPIOs. If for some reason a design differs in
+  # the future, we will want to add a nested check in the config_<platform_name>
+  # function. Doing it in this manner allows us to reduce the number of
+  # configurations that we have to maintain (and reduces the amount of testing
+  # if we're only updating a specific config_<platform_name>).
+  if ! PLATFORM_NAME="$(get_platform_name)"; then
+    echo "Failed to get platform name"
+    exit "${EXIT_CONFIG}"
+  fi
+  readonly PLATFORM_NAME
+
+  if ! PLATFORM_BASE_NAME="$(platform_base_name "${PLATFORM_NAME}")"; then
+    echo "Failed to get platform base name"
+    exit "${EXIT_CONFIG}"
+  fi
+  readonly PLATFORM_BASE_NAME
+
+  echo "Platform name is ${PLATFORM_NAME} (${PLATFORM_BASE_NAME})."
+
+  # Check that the config function exists
+  if [[ "$(type -t "config_${PLATFORM_NAME}")" == "function" ]]; then
+    readonly PLATFORM_CONFIG="${PLATFORM_NAME}"
+  elif [[ "$(type -t "config_${PLATFORM_BASE_NAME}")" == "function" ]]; then
+    readonly PLATFORM_CONFIG="${PLATFORM_BASE_NAME}"
+  else
+    echo "No config for platform ${PLATFORM_NAME}." >&2
+    exit "${EXIT_CONFIG}"
+  fi
+
+  echo "Using config for ${PLATFORM_CONFIG}."
+
+  if ! "config_${PLATFORM_CONFIG}"; then
+    echo "Configuration failed for platform ${PLATFORM_CONFIG}." >&2
+    exit "${EXIT_CONFIG}"
+  fi
+
+  # Help the user out with defaults, if no *file* was given.
+  if [[ "$#" -eq 0 ]]; then
+    # If we are actually reading, set to a timestamped temp file.
+    if [[ "${FLAGS_read}" -eq "${FLAGS_TRUE}" ]]; then
+      filename="/tmp/fpmcu-fw-$(date --iso-8601=seconds).bin"
+    else
+      # Assume we are "writing" the default firmware to the FPMCU.
+      if ! filename="$(get_default_fw)"; then
+        echo "Failed to identify a default firmware file" >&2
+        exit "${EXIT_CONFIG}"
+      fi
+    fi
+  fi
+
+  # Check that the gpiochip exists
+  if [[ ! -e "/sys/class/gpio/${GPIO_CHIP}" ]]; then
+    echo "Cannot find GPIO chip: ${GPIO_CHIP}"
+    exit "${EXIT_CONFIG}"
+  fi
+
+  if [[ "${FLAGS_services}" -eq "${FLAGS_TRUE}" ]]; then
+    echo "# Stopping biod and timberslide"
+    stop biod
+    stop timberslide LOG_PATH=/sys/kernel/debug/cros_fp/console_log
+  fi
+
+  # If cros-ec driver isn't bound on startup, this means the final rebinding
+  # may fail.
+  if [[ ! -c "/dev/cros_fp" ]]; then
+    echo "WARNING: The cros-ec driver was not bound on startup." >&2
+  fi
+  if [[ -c "${DEVICE}" ]]; then
+    echo "WARNING: The raw driver was bound on startup." >&2
+  fi
+  local files_open
+  # Ensure no processes have cros_fp device or debug device open.
+  # This might be biod and/or timberslide.
+  if files_open=$(proc_open_file "/dev/cros_fp\|/sys/kernel/debug/cros_fp/*")
+  then
+    echo "WARNING: Another process has a cros_fp device file open." >&2
+    echo "${files_open}" >&2
+    echo "Try 'stop biod' and" >&2
+    echo "'stop timberslide LOG_PATH=/sys/kernel/debug/cros_fp/console_log'" >&2
+    echo "before running this script." >&2
+    echo "See b/188985272." >&2
+  fi
+  # Ensure no processes are using the raw driver. This might be a wedged
+  # stm32mon process spawned by this script.
+  if files_open=$(proc_open_file "${DEVICE}"); then
+    echo "WARNING: Another process has ${DEVICE} open." >&2
+    echo "${files_open}" >&2
+    echo "Try 'fuser -k ${DEVICE}' before running this script." >&2
+    echo "See b/188985272." >&2
+  fi
+
+  local ret
+  flash_fp_mcu_stm32 \
+    "${TRANSPORT}"   \
+    "${DEVICE}"      \
+    "${GPIO_NRST}"   \
+    "${GPIO_BOOT0}"  \
+    "${GPIO_PWREN}"  \
+    "${filename}"
+  ret=$?
+
+  if [[ "${FLAGS_services}" -eq "${FLAGS_TRUE}" ]]; then
+    echo "# Restarting biod and timberslide"
+    start timberslide LOG_PATH=/sys/kernel/debug/cros_fp/console_log
+    start biod
+  fi
+
+  exit "${ret}"
 }
 
-# The "platform name" corresponds to the underlying board (reference design)
-# that we're running on (not the FPMCU or sensor). At the moment all of the
-# reference designs use the same GPIOs. If for some reason a design differs in
-# the future, we will want to add a nested check in the config_<platform_name>
-# function. Doing it in this manner allows us to reduce the number of
-# configurations that we have to maintain (and reduces the amount of testing
-# if we're only updating a specific config_<platform_name>).
-readonly PLATFORM_NAME="$(get_platform_name)"
-
-echo "Using config for ${PLATFORM_NAME}"
-
-# Check that the config function exists
-if [[ "$(type -t "config_${PLATFORM_NAME}")" != "function" ]]; then
-  echo "No config for platform ${PLATFORM_NAME}"
-  exit 1
-fi
-
-config_${PLATFORM_NAME}
-
-if [[ $? -ne 0 ]]; then
-  echo "Configuration failed for platform ${PLATFORM_NAME}"
-  exit 1
-fi
-
-flash_fp_mcu_stm32 \
-  "${TRANSPORT}"   \
-  "${DEVICE}"      \
-  "${GPIO_NRST}"   \
-  "${GPIO_BOOT0}"  \
-  "${GPIO_PWREN}"  \
-  "${1}"
+main "$@"
diff --git a/util/flash_jlink.py b/util/flash_jlink.py
index a0a67f93d9..3bfa26bd9c 100755
--- a/util/flash_jlink.py
+++ b/util/flash_jlink.py
@@ -1,76 +1,176 @@
 #!/usr/bin/env python3
 
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
+# pylint: disable=logging-fstring-interpolation
+
 """Flashes firmware using Segger J-Link.
 
 This script requires Segger hardware attached via JTAG/SWD.
+
+See
+https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/docs/fingerprint/fingerprint-debugging.md#flash
+for instructions.
 """
 
 import argparse
 import logging
 import os
 import shutil
+import socket
 import subprocess
 import sys
 import tempfile
+import time
+
+
+DEFAULT_SEGGER_REMOTE_PORT = 19020
 
 # Commands are documented here: https://wiki.segger.com/J-Link_Commander
-JLINK_COMMANDS = '''
+JLINK_COMMANDS = """
 exitonerror 1
 r
-loadfile {FIRMWARE}
+loadfile {FIRMWARE} {FLASH_ADDRESS}
 r
 go
 exit
-'''
+"""
 
 
 class BoardConfig:
-    def __init__(self, interface, device):
+    """Board configuration."""
+
+    def __init__(self, interface, device, flash_address):
         self.interface = interface
         self.device = device
-
-
-SWD_INTERFACE = 'SWD'
-DRAGONCLAW_CONFIG = BoardConfig(interface=SWD_INTERFACE, device='STM32F412CG')
-ICETOWER_CONFIG = BoardConfig(interface=SWD_INTERFACE, device='STM32H743ZI')
+        self.flash_address = flash_address
+
+
+SWD_INTERFACE = "SWD"
+STM32_DEFAULT_FLASH_ADDRESS = "0x8000000"
+DRAGONCLAW_CONFIG = BoardConfig(
+    interface=SWD_INTERFACE,
+    device="STM32F412CG",
+    flash_address=STM32_DEFAULT_FLASH_ADDRESS,
+)
+ICETOWER_CONFIG = BoardConfig(
+    interface=SWD_INTERFACE,
+    device="STM32H743ZI",
+    flash_address=STM32_DEFAULT_FLASH_ADDRESS,
+)
 
 BOARD_CONFIGS = {
-    'dragonclaw': DRAGONCLAW_CONFIG,
-    'bloonchipper': DRAGONCLAW_CONFIG,
-    'dartmonkey': ICETOWER_CONFIG,
-    'icetower': ICETOWER_CONFIG,
+    "dragonclaw": DRAGONCLAW_CONFIG,
+    "bloonchipper": DRAGONCLAW_CONFIG,
+    "nucleo-f412zg": DRAGONCLAW_CONFIG,
+    "dartmonkey": ICETOWER_CONFIG,
+    "icetower": ICETOWER_CONFIG,
+    "nucleo-dartmonkey": ICETOWER_CONFIG,
+    "nucleo-h743zi": ICETOWER_CONFIG,
 }
 
 
-def create_jlink_command_file(firmware_file):
+def is_tcp_port_open(host: str, tcp_port: int) -> bool:
+    """Checks if the TCP host port is open."""
+
+    sock = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
+    sock.settimeout(2)  # 2 Second Timeout
+    try:
+        sock.connect((host, tcp_port))
+        sock.shutdown(socket.SHUT_RDWR)
+    except ConnectionRefusedError:
+        return False
+    except socket.timeout:
+        return False
+    finally:
+        sock.close()
+    # Other errors are propagated as odd exceptions.
+
+    # We shutdown and closed the connection, but the server may need a second
+    # to start listening again. If the following error is seen, this timeout
+    # should be increased. 300ms seems to be the minimum.
+    #
+    # Connecting to J-Link via IP...FAILED: Can not connect to J-Link via \
+    #   TCP/IP (127.0.0.1, port 19020)
+    time.sleep(0.5)
+    return True
+
+
+def create_jlink_command_file(firmware_file, config):
     tmp = tempfile.NamedTemporaryFile()
-    tmp.write(JLINK_COMMANDS.format(FIRMWARE=firmware_file).encode('utf-8'))
+    tmp.write(
+        JLINK_COMMANDS.format(
+            FIRMWARE=firmware_file, FLASH_ADDRESS=config.flash_address
+        ).encode("utf-8")
+    )
     tmp.flush()
     return tmp
 
 
-def flash(jlink_exe, ip, device, interface, cmd_file):
+def flash(jlink_exe, remote, device, interface, cmd_file):
     cmd = [
         jlink_exe,
     ]
 
-    if len(ip) > 0:
-        cmd.extend(['-ip', ip])
-
-    cmd.extend([
-        '-device', device,
-        '-if', interface,
-        '-speed', 'auto',
-        '-autoconnect', '1',
-        '-CommandFile', cmd_file,
-        ])
-    logging.debug('Running command: "%s"', ' '.join(cmd))
-    completed_process = subprocess.run(cmd)
-    logging.debug('JLink return code: %d', completed_process.returncode)
+    if remote:
+        logging.debug(f"Connecting to J-Link over TCP/IP {remote}.")
+        remote_components = remote.split(":")
+        if len(remote_components) not in [1, 2]:
+            logging.debug(f'Given remote "{remote}" is malformed.')
+            return 1
+
+        host = remote_components[0]
+        try:
+            ip = socket.gethostbyname(host)
+        except socket.gaierror as e:
+            logging.error(f'Failed to resolve host "{host}": {e}.')
+            return 1
+        logging.debug(f"Resolved {host} as {ip}.")
+        port = DEFAULT_SEGGER_REMOTE_PORT
+
+        if len(remote_components) == 2:
+            try:
+                port = int(remote_components[1])
+            except ValueError:
+                logging.error(
+                    f'Given remote port "{remote_components[1]}" is malformed.'
+                )
+                return 1
+
+        remote = f"{ip}:{port}"
+
+        logging.debug(f"Checking connection to {remote}.")
+        if not is_tcp_port_open(ip, port):
+            logging.error(
+                f"JLink server doesn't seem to be listening on {remote}."
+            )
+            logging.error("Ensure that JLinkRemoteServerCLExe is running.")
+            return 1
+        cmd.extend(["-ip", remote])
+
+    cmd.extend(
+        [
+            "-device",
+            device,
+            "-if",
+            interface,
+            "-speed",
+            "auto",
+            "-autoconnect",
+            "1",
+            "-NoGui",
+            "1",
+            "-CommandFile",
+            cmd_file,
+        ]
+    )
+    logging.debug('Running command: "%s"', " ".join(cmd))
+    completed_process = subprocess.run(
+        cmd
+    )  # pylint: disable=subprocess-run-check
+    logging.debug("JLink return code: %d", completed_process.returncode)
     return completed_process.returncode
 
 
@@ -78,38 +178,42 @@ def main(argv: list):
 
     parser = argparse.ArgumentParser()
 
-    default_jlink = './JLink_Linux_V684a_x86_64/JLinkExe'
+    default_jlink = "./JLink_Linux_V684a_x86_64/JLinkExe"
     if shutil.which(default_jlink) is None:
-        default_jlink = 'JLinkExe'
+        default_jlink = "JLinkExe"
     parser.add_argument(
-        '--jlink', '-j',
-        help='JLinkExe path (default: ' + default_jlink + ')',
-        default=default_jlink)
+        "--jlink",
+        "-j",
+        help="JLinkExe path (default: " + default_jlink + ")",
+        default=default_jlink,
+    )
 
-    default_ip = '127.0.0.1:2551'
     parser.add_argument(
-        '--ip', '-n',
-        help='IP address of J-Link or machine running JLinkRemoteServerCLExe '
-             '(default: ' + default_ip + ')',
-        default=default_ip)
+        "--remote",
+        "-n",
+        help="Use TCP/IP host[:port] to connect to a J-Link or "
+        "JLinkRemoteServerCLExe. If unspecified, connect over USB.",
+    )
 
-    default_board = 'bloonchipper'
+    default_board = "bloonchipper"
     parser.add_argument(
-        '--board', '-b',
-        help='Board (default: ' + default_board + ')',
-        default=default_board)
+        "--board",
+        "-b",
+        help="Board (default: " + default_board + ")",
+        default=default_board,
+    )
 
-    default_firmware = os.path.join('./build', default_board, 'ec.bin')
+    default_firmware = os.path.join("./build", default_board, "ec.bin")
     parser.add_argument(
-        '--image', '-i',
-        help='Firmware binary (default: ' + default_firmware + ')',
-        default=default_firmware)
+        "--image",
+        "-i",
+        help="Firmware binary (default: " + default_firmware + ")",
+        default=default_firmware,
+    )
 
-    log_level_choices = ['DEBUG', 'INFO', 'WARNING', 'ERROR', 'CRITICAL']
+    log_level_choices = ["DEBUG", "INFO", "WARNING", "ERROR", "CRITICAL"]
     parser.add_argument(
-        '--log_level', '-l',
-        choices=log_level_choices,
-        default='DEBUG'
+        "--log_level", "-l", choices=log_level_choices, default="DEBUG"
     )
 
     args = parser.parse_args(argv)
@@ -124,12 +228,13 @@ def main(argv: list):
     args.image = os.path.realpath(args.image)
     args.jlink = args.jlink
 
-    cmd_file = create_jlink_command_file(args.image)
-    ret_code = flash(args.jlink, args.ip, config.device, config.interface,
-                     cmd_file.name)
+    cmd_file = create_jlink_command_file(args.image, config)
+    ret_code = flash(
+        args.jlink, args.remote, config.device, config.interface, cmd_file.name
+    )
     cmd_file.close()
     return ret_code
 
 
-if __name__ == '__main__':
+if __name__ == "__main__":
     sys.exit(main(sys.argv[1:]))
diff --git a/util/fpmcu_upload.py b/util/fpmcu_upload.py
new file mode 100755
index 0000000000..c127bf4508
--- /dev/null
+++ b/util/fpmcu_upload.py
@@ -0,0 +1,331 @@
+#!/usr/bin/env python3
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Uploads an image on to an FPMCU dev board.
+
+# Requirements
+
+Install the Python dependencies in your chroot:
+
+  (chroot) emerge pillow
+
+Build the EC image with debug mode enabled:
+
+  (chroot) platform/ec $ make BOARD=$BOARD EXTRA_CFLAGS=-DCONFIG_CMD_FPSENSOR_DEBUG
+
+# Usage
+
+Start servod with the board that is being tested:
+
+  (chroot) sudo servod --board ${BOARD}
+
+Flash the debug EC image onto FPMCU:
+
+  (chroot) ./util/flash_ec --board=$BOARD --image=./build/$BOARD/ec.bin
+
+Upload the image file:
+
+  (chroot) ./util/fpmcu_upload.py -i /tmp/img1.png -b ${BOARD}
+
+Run unit tests
+
+  (chroot) python -m unittest util/fpmcu_upload.py
+"""
+import argparse
+from dataclasses import dataclass
+from enum import Enum
+import io
+import logging
+import subprocess
+import sys
+from typing import List, Optional, Tuple
+import unittest
+
+# pylint: disable=import-error
+from contextlib2 import ExitStack
+from PIL import Image
+
+
+# pylint:enable=import-error
+
+
+class SensorByteOrder(Enum):
+    """Storage order of bytes returned by the sensor"""
+
+    ROW_MAJOR = 1
+    COLUMN_MAJOR = 2
+
+
+# TODO(b/267803007): Refactor this section of the code to remove duplication
+# with run_device_tests.py
+@dataclass
+class BoardConfig:
+    """Board-specific configuration."""
+
+    name: str
+    servo_uart_name: str
+    sensor_height: int
+    sensor_width: int
+    sensor_byte_order: SensorByteOrder
+
+
+BLOONCHIPPER_CONFIG = BoardConfig(
+    name="bloonchipper",
+    servo_uart_name="raw_fpmcu_console_uart_pty",
+    sensor_width=160,
+    sensor_height=160,
+    sensor_byte_order=SensorByteOrder.ROW_MAJOR,
+)
+
+DARTMONKEY_CONFIG = BoardConfig(
+    name="dartmonkey",
+    servo_uart_name="raw_fpmcu_console_uart_pty",
+    sensor_width=56,
+    sensor_height=192,
+    sensor_byte_order=SensorByteOrder.COLUMN_MAJOR,
+)
+
+BOARD_CONFIGS = {
+    "bloonchipper": BLOONCHIPPER_CONFIG,
+    "dartmonkey": DARTMONKEY_CONFIG,
+}
+
+
+def get_console(board_config: BoardConfig) -> Optional[str]:
+    """Get the name of the console for a given board."""
+    cmd = [
+        "dut-control",
+        board_config.servo_uart_name,
+    ]
+    logging.debug('Running command: "%s"', " ".join(cmd))
+
+    with subprocess.Popen(cmd, stdout=subprocess.PIPE) as proc:
+        for line in io.TextIOWrapper(proc.stdout):  # type: ignore[arg-type]
+            logging.debug(line)
+            pty = line.split(":")
+            if len(pty) == 2 and pty[0] == board_config.servo_uart_name:
+                return pty[1].strip()
+
+    return None
+
+
+def load_image_from_png(image_path: str) -> Image:
+    """Load a PNG image from file"""
+    if not image_path.endswith(".png"):
+        raise ValueError(
+            f"Input file must be png, sorry. Input was {image_path}"
+        )
+
+    return Image.open(image_path)
+
+
+def pixel_value_to_hex(value: int) -> str:
+    """Convert an 8-bit pixel value to a hex string of two characters"""
+    if value < 0 or value > 255:
+        raise ValueError(f"Pixel value {value} outside range 0-255")
+    return "{:02x}".format(value)
+
+
+def image_to_hex_str(image: Image, byte_order: SensorByteOrder) -> str:
+    """Convert an 8-bit image to a string of hex characters"""
+    image_str = ""
+    num_cols, num_rows = image.size
+    if byte_order == SensorByteOrder.ROW_MAJOR:
+        for row in range(num_rows):
+            for col in range(num_cols):
+                image_str += pixel_value_to_hex(image.getpixel((col, row)))
+    elif byte_order == SensorByteOrder.COLUMN_MAJOR:
+        for col in range(num_cols):
+            for row in range(num_rows):
+                image_str += pixel_value_to_hex(image.getpixel((col, row)))
+
+    return image_str
+
+
+def split_hex_str(hex_str: str, chunk_size: int) -> List[Tuple[int, str]]:
+    """Split a string with hex values into chunks with chunk_size values.
+
+    hex_str is expected to contain hex values represented with two
+    characters each.
+    chunk_size is the number of hex values so the output string will contain
+    2 x chunk_size characters.
+
+    Returns a list of tuples (offset, hex_str).
+    """
+
+    if len(hex_str) % 2:
+        raise ValueError("Input string does not represent hex values")
+
+    chunks = []
+    offset = 0
+    while 2 * offset < len(hex_str):
+        chunks.append((offset, hex_str[2 * offset : 2 * (offset + chunk_size)]))
+        offset += chunk_size
+
+    return chunks
+
+
+def get_fpupload_cmds(board_config: BoardConfig, image: Image) -> List[str]:
+    """Return the sequence of commands to upload the image on the FPMCU"""
+
+    # Check that image has the correct size for the board selected.
+    expected_size = (board_config.sensor_height, board_config.sensor_width)
+    if image.size != expected_size:
+        raise ValueError(
+            f"Image size is {image.size} but expected {expected_size}"
+        )
+
+    logging.info("Image size: %s", image.size)
+
+    # Convert the image as a string of hex values, then break it into chunks
+    image_str = image_to_hex_str(image, board_config.sensor_byte_order)
+
+    payload_size = 20
+    cmds = []
+    for offset, payload in split_hex_str(image_str, payload_size):
+        cmds.append(f"fpupload {offset} {payload}\n")
+    return cmds
+
+
+def main():
+    """Load a PNG image from file and transfer it to the FPMCU"""
+
+    parser = argparse.ArgumentParser()
+
+    default_board = "bloonchipper"
+    parser.add_argument(
+        "--board",
+        "-b",
+        help="Board (default: " + default_board + ")",
+        default=default_board,
+    )
+    parser.add_argument(
+        "--image",
+        "-i",
+        help="Image file in PNG",
+        default="",
+    )
+    parser.add_argument(
+        "--echo",
+        help="Debug: whether or not to echo back the input image.",
+        action="store_true",
+    )
+
+    args = parser.parse_args()
+    board_config = BOARD_CONFIGS[args.board]
+
+    image = load_image_from_png(args.image)
+    fpupload_cmds = get_fpupload_cmds(board_config, image)
+
+    with ExitStack() as stack:
+        console = stack.enter_context(
+            open(get_console(board_config), "wb+", buffering=0)
+        )
+        for cmd in fpupload_cmds:
+            console.write(cmd.encode())
+
+        if args.echo:
+            console.write("fpdownload".encode())
+
+
+if __name__ == "__main__":
+    sys.exit(main())
+
+
+# Disable docstrings for unit tests
+# pylint: disable=missing-module-docstring
+# pylint: disable=missing-class-docstring
+# pylint: disable=missing-function-docstring
+class TestLoadImageFromPng(unittest.TestCase):
+    def test_invalid_file_extension(self):
+        with self.assertRaises(ValueError):
+            load_image_from_png("not_a_png.jpg")
+
+    def test_empty_file_path(self):
+        with self.assertRaises(ValueError):
+            load_image_from_png("")
+
+
+class TestPixelValueToHex(unittest.TestCase):
+    def test_value_below_zero(self):
+        with self.assertRaises(ValueError):
+            pixel_value_to_hex(-1)
+
+    def test_value_above_255(self):
+        with self.assertRaises(ValueError):
+            pixel_value_to_hex(256)
+
+    def test_valid_values(self):
+        self.assertEqual(pixel_value_to_hex(0), "00")
+        self.assertEqual(pixel_value_to_hex(1), "01")
+        self.assertEqual(pixel_value_to_hex(10), "0a")
+        self.assertEqual(pixel_value_to_hex(255), "ff")
+
+
+class TestImageToHexStr(unittest.TestCase):
+    # Use a small image with width = 5 and height = 3
+    def test_row_major_order(self):
+        image = Image.new("P", (5, 3))
+        image.putpixel((0, 1), 255)
+        image_str = image_to_hex_str(image, SensorByteOrder.ROW_MAJOR)
+        self.assertEqual(len(image_str), 30)
+        self.assertEqual(image_str[:2], "00")
+        self.assertEqual(image_str[10:12], "ff")
+
+    def test_col_major_order(self):
+        image = Image.new("P", (5, 3))
+        image.putpixel((0, 1), 255)
+        image_str = image_to_hex_str(image, SensorByteOrder.COLUMN_MAJOR)
+        self.assertEqual(len(image_str), 30)
+        self.assertEqual(image_str[:2], "00")
+        self.assertEqual(image_str[2:4], "ff")
+
+
+class TestSplitHexStr(unittest.TestCase):
+    def test_invalid_hex_str(self):
+        with self.assertRaises(ValueError):
+            split_hex_str("123", 4)
+
+    def test_one_chunk(self):
+        res = split_hex_str("12345678", 4)
+        self.assertEqual(len(res), 1)
+        self.assertEqual(res[0], (0, "12345678"))
+
+    def test_one_partial_chunk(self):
+        res = split_hex_str("123456", 4)
+        self.assertEqual(len(res), 1)
+        self.assertEqual(res[0], (0, "123456"))
+
+    def test_two_chunks(self):
+        res = split_hex_str("12345678", 2)
+        self.assertEqual(len(res), 2)
+        self.assertEqual(res[0], (0, "1234"))
+        self.assertEqual(res[1], (2, "5678"))
+
+    def test_two_partial_chunks(self):
+        res = split_hex_str("12345678", 3)
+        self.assertEqual(len(res), 2)
+        self.assertEqual(res[0], (0, "123456"))
+        self.assertEqual(res[1], (3, "78"))
+
+
+class TestGetFpuploadCmds(unittest.TestCase):
+    def test_invalid_size(self):
+        image = Image.new("P", (10, 20))
+        with self.assertRaises(ValueError):
+            get_fpupload_cmds(DARTMONKEY_CONFIG, image)
+
+    def test_valid_size(self):
+        image = Image.new("P", (192, 56))
+        cmds = get_fpupload_cmds(DARTMONKEY_CONFIG, image)
+        self.assertEqual(len(cmds), 538)
+        self.assertEqual(cmds[0].split()[0], "fpupload")
+        self.assertEqual(cmds[0].split()[1], "0")
+        self.assertEqual(cmds[1].split()[0], "fpupload")
+        self.assertEqual(cmds[1].split()[1], "20")
+        # The image has 10752 pixels which requires 538 commands for chunk size 20.
+        self.assertEqual(cmds[537].split()[0], "fpupload")
+        # 537 commands * offset 20 = 10740 final offset.
+        self.assertEqual(cmds[537].split()[1], "10740")
diff --git a/util/fptool.py b/util/fptool.py
new file mode 100755
index 0000000000..ba00c0020a
--- /dev/null
+++ b/util/fptool.py
@@ -0,0 +1,56 @@
+#!/usr/bin/env python3
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""A tool to manage the fingerprint system on ChromeOS."""
+
+import argparse
+import os
+import shutil
+import subprocess
+import sys
+
+
+def cmd_flash(args: argparse.Namespace) -> int:
+    """Flash the entire firmware FPMCU using the native bootloader.
+
+    This requires the Chromebook to be in dev mode with hardware write protect
+    disabled.
+    """
+
+    if not shutil.which("flash_fp_mcu"):
+        print("Error - The flash_fp_mcu utility does not exist.")
+        return 1
+
+    cmd = ["flash_fp_mcu"]
+    if args.image:
+        if not os.path.isfile(args.image):
+            print(f"Error - image {args.image} is not a file.")
+            return 1
+        cmd.append(args.image)
+
+    print(f'Running {" ".join(cmd)}.')
+    sys.stdout.flush()
+    p = subprocess.run(cmd)  # pylint: disable=subprocess-run-check
+    return p.returncode
+
+
+def main(argv: list) -> int:
+    parser = argparse.ArgumentParser(description=__doc__)
+    subparsers = parser.add_subparsers(dest="subcommand", title="subcommands")
+    # This method of setting required is more compatible with older python.
+    subparsers.required = True
+
+    # Parser for "flash" subcommand.
+    parser_decrypt = subparsers.add_parser("flash", help=cmd_flash.__doc__)
+    parser_decrypt.add_argument(
+        "image", nargs="?", help="Path to the firmware image"
+    )
+    parser_decrypt.set_defaults(func=cmd_flash)
+    opts = parser.parse_args(argv)
+    return opts.func(opts)
+
+
+if __name__ == "__main__":
+    sys.exit(main(sys.argv[1:]))
diff --git a/util/gdbinit b/util/gdbinit
index ca2318be04..1854b4bdc0 100644
--- a/util/gdbinit
+++ b/util/gdbinit
@@ -1,4 +1,4 @@
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -125,9 +125,9 @@ end
 # Helper Functions                                                  #
 #####################################################################
 
-# Usage: reg32 <address> [offset]
+# Usage: ec-reg32 <address> [offset]
 # Read a 32 bit register
-define reg32
+define ec-reg32
     set $a = $arg0
     if $argc > 1
         set $a += $arg1
@@ -137,14 +137,15 @@ define reg32
     print /x $v
     print /t $v
 end
+alias reg32 = ec-reg32
 
 # Usage: ec-connect
 # Issue the overly long target connect command using the
 # specified gdb server port.
 define ec-connect
 python
-    # May want to only use "target remote".
-    gdb.execute('target extended-remote :%d'%GDBPORT)
+# May want to only use "target remote".
+gdb.execute(f'target extended-remote :{GDBPORT}')
 end
 end
 alias connect = ec-connect
@@ -215,4 +216,4 @@ define ec-brexception
     break exception_panic
     break bus_fault_handler
     break panic_assert_fail
-end
\ No newline at end of file
+end
diff --git a/util/gen_emmc_transfer_data.c b/util/gen_emmc_transfer_data.c
index 98417beb9b..1de9d6b5a0 100644
--- a/util/gen_emmc_transfer_data.c
+++ b/util/gen_emmc_transfer_data.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -6,18 +6,18 @@
  * eMMC protocol.
  */
 
-#include <err.h>
 #include <errno.h>
-#include <getopt.h>
 #include <stdint.h>
 #include <stdio.h>
 #include <string.h>
 
 #include <compile_time_macros.h>
+#include <err.h>
+#include <getopt.h>
 
 /* eMMC transfer block size */
-#define BLOCK_SIZE		512
-#define BLOCK_RAW_DATA		"bootblock_raw_data"
+#define BLOCK_SIZE 512
+#define BLOCK_RAW_DATA "bootblock_raw_data"
 
 uint16_t crc16_arg(uint8_t data, uint16_t previous_crc)
 {
@@ -42,12 +42,11 @@ void header_format(FILE *fin, FILE *fout)
 	size_t cnt = 0;
 
 	fprintf(fout, "/* This file is auto-generated. Do not modify. */\n"
-		"#ifndef __CROS_EC_BOOTBLOCK_DATA_H\n"
-		"#define __CROS_EC_BOOTBLOCK_DATA_H\n"
-		"\n"
-		"#include <stdint.h>\n"
-		"\n"
-		);
+		      "#ifndef __CROS_EC_BOOTBLOCK_DATA_H\n"
+		      "#define __CROS_EC_BOOTBLOCK_DATA_H\n"
+		      "\n"
+		      "#include <stdint.h>\n"
+		      "\n");
 
 	fprintf(fout,
 		"static const uint8_t %s[] __attribute__((aligned(4))) =\n"
@@ -64,18 +63,19 @@ void header_format(FILE *fin, FILE *fout)
 		if (cnt == 0)
 			break;
 		else if (cnt < BLOCK_SIZE)
-			memset(&data[cnt], 0xff, BLOCK_SIZE-cnt);
+			memset(&data[cnt], 0xff, BLOCK_SIZE - cnt);
 
 		fprintf(fout, "\t/* Block %d (%ld) */\n", blk, cnt);
 		fprintf(fout, "\t0xff, 0xfe, /* idle, start bit. */");
 		for (j = 0; j < sizeof(data); j++) {
-			fprintf(fout, "%s0x%02x,",
-				(j % 8) == 0 ? "\n\t" : " ", data[j]);
+			fprintf(fout, "%s0x%02x,", (j % 8) == 0 ? "\n\t" : " ",
+				data[j]);
 			crc16 = crc16_arg(data[j], crc16);
 		}
 		fprintf(fout, "\n");
 
-		fprintf(fout, "\t0x%02x, 0x%02x, 0xff,"
+		fprintf(fout,
+			"\t0x%02x, 0x%02x, 0xff,"
 			" /* CRC, end bit, idle */\n",
 			crc16 >> 8, crc16 & 0xff);
 	}
@@ -96,16 +96,14 @@ int main(int argc, char **argv)
 	FILE *fout = NULL;
 
 	const char short_opts[] = "i:ho:";
-	const struct option long_opts[] = {
-		{ "input", 1, NULL, 'i' },
-		{ "help", 0, NULL, 'h' },
-		{ "out", 1, NULL, 'o' },
-		{ NULL }
-	};
+	const struct option long_opts[] = { { "input", 1, NULL, 'i' },
+					    { "help", 0, NULL, 'h' },
+					    { "out", 1, NULL, 'o' },
+					    { NULL } };
 	const char usage[] = "USAGE: %s [-i <input>] -o <output>\n";
 
-	while ((nopt = getopt_long(argc, argv, short_opts, long_opts,
-								NULL)) != -1) {
+	while ((nopt = getopt_long(argc, argv, short_opts, long_opts, NULL)) !=
+	       -1) {
 		switch (nopt) {
 		case 'i': /* -i or --input*/
 			input_name = optarg;
diff --git a/util/gen_ipi_table.c b/util/gen_ipi_table.c
index 07a3a39be0..6c1407973c 100644
--- a/util/gen_ipi_table.c
+++ b/util/gen_ipi_table.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -12,7 +12,7 @@
 
 #include "board.h"
 
-#define FPRINTF(format, args...) fprintf(fout, format, ## args)
+#define FPRINTF(format, args...) fprintf(fout, format, ##args)
 
 int main(int argc, char **argv)
 {
diff --git a/util/gen_touchpad_hash.c b/util/gen_touchpad_hash.c
index e03c4638f3..edf1022bf9 100644
--- a/util/gen_touchpad_hash.c
+++ b/util/gen_touchpad_hash.c
@@ -1,18 +1,18 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <err.h>
-#include <getopt.h>
-#include <stdio.h>
+#include "config.h"
+
 #include <stdint.h>
+#include <stdio.h>
 #include <string.h>
-#include <unistd.h>
 
+#include <err.h>
+#include <getopt.h>
 #include <openssl/sha.h>
-
-#include "config.h"
+#include <unistd.h>
 
 static void print_hex(FILE *out, uint8_t *digest, int len, int last)
 {
@@ -35,7 +35,7 @@ static int hash_fw_blank(FILE *hashes)
 		CONFIG_TOUCHPAD_VIRTUAL_SIZE / CONFIG_UPDATE_PDU_SIZE,
 		SHA256_DIGEST_LENGTH);
 	for (len = 0; len < CONFIG_TOUCHPAD_VIRTUAL_SIZE;
-				len += CONFIG_UPDATE_PDU_SIZE) {
+	     len += CONFIG_UPDATE_PDU_SIZE) {
 		print_hex(hashes, digest, sizeof(digest), 0);
 	}
 	fputs("};\n", hashes);
@@ -93,7 +93,7 @@ static int hash_fw(FILE *tp_fw, FILE *hashes)
 
 	if (len != CONFIG_TOUCHPAD_VIRTUAL_SIZE) {
 		warnx("Incorrect TP FW size (%d vs %d)", len,
-			CONFIG_TOUCHPAD_VIRTUAL_SIZE);
+		      CONFIG_TOUCHPAD_VIRTUAL_SIZE);
 		return 1;
 	}
 
@@ -109,16 +109,14 @@ int main(int argc, char **argv)
 	FILE *tp_fw = NULL;
 	FILE *hashes;
 	const char short_opt[] = "f:ho:";
-	const struct option long_opts[] = {
-		{ "firmware", 1, NULL, 'f' },
-		{ "help", 0, NULL, 'h' },
-		{ "out", 1, NULL, 'o' },
-		{ NULL }
-	};
+	const struct option long_opts[] = { { "firmware", 1, NULL, 'f' },
+					    { "help", 0, NULL, 'h' },
+					    { "out", 1, NULL, 'o' },
+					    { NULL } };
 	const char usage[] = "USAGE: %s -f <touchpad FW> -o <output file>\n";
 
-	while ((nopt = getopt_long(argc, argv, short_opt,
-						long_opts, NULL)) != -1) {
+	while ((nopt = getopt_long(argc, argv, short_opt, long_opts, NULL)) !=
+	       -1) {
 		switch (nopt) {
 		case 'f': /* -f or --firmware */
 			tp_fw_name = optarg;
diff --git a/util/genvif.c b/util/genvif.c
index 919b81c64f..892bf14367 100644
--- a/util/genvif.c
+++ b/util/genvif.c
@@ -1,1066 +1,3866 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #define _GNU_SOURCE /* for asprintf */
 
+#include "charge_manager.h"
+#include "config.h"
+#include "genvif.h"
+#include "usb_pd.h"
+#include "usb_pd_pdo.h"
+#include "usb_pd_tcpm.h"
+
+#include <ctype.h>
 #include <errno.h>
+#include <limits.h>
 #include <stdarg.h>
+#include <stdbool.h>
 #include <stdint.h>
 #include <stdio.h>
-#include <string.h>
 #include <stdlib.h>
-#include <getopt.h>
+#include <string.h>
+
 #include <dirent.h>
-#include <limits.h>
+#include <getopt.h>
 
-#include "config.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "charge_manager.h"
-#include "system.h"
+#define VIF_APP_VENDOR_VALUE "Google"
+#define VIF_APP_NAME_VALUE "EC GENVIF"
+#define VIF_APP_VERSION_VALUE "3.2.3.0"
+#define VENDOR_NAME_VALUE "Google"
+
+#define DEFAULT_MISSING_TID 0xFFFF
+#define DEFAULT_MISSING_PID 0xFFFF
+#define DEFAULT_MISSING_BCD_DEV 0x0000
 
 /*
- * Vendor Info File Generator
- * Revision 1.40, Version 1.0
+ * XML namespace for VIF as of VifEditorRelease 3.2.3.0
  */
+#define VIF_ "vif:"
+
+const uint32_t *src_pdo;
+uint32_t src_pdo_cnt;
 
-#define GENVIF_TITLE  "EC GENVIF, Version 1.40"
-#define VIF_SPEC      "Revision 1.40, Version 1.0"
-#define VENDOR_NAME   "Google"
+struct vif_t vif;
+
+/*
+ * local type to make decisions on the output for Source, Sink and DRP
+ */
+enum dtype { SRC = 0, SNK, DRP };
+
+enum ptype {
+	PORT_CONSUMER_ONLY = 0,
+	PORT_CONSUMER_PRODUCER = 1,
+	PORT_PRODUCER_CONSUMER = 2,
+	PORT_PROVIDER_ONLY = 3,
+	PORT_DRP = 4,
+	PORT_EMARKER = 5,
+};
 
-enum spec_rev {
-	PD_REV_2_0 = 1,
-	PD_REV_3_0
+/*
+ * Device_Speed options, defined in the VIF specification
+ */
+enum usb_speed {
+	USB_2 = 0,
+	USB_GEN11 = 1,
+	USB_GEN21 = 2,
+	USB_GEN12 = 3,
+	USB_GEN22 = 4
 };
 
-enum field {
-	INTRO = 0,
-	PRODUCT,
-	GENERAL,
-	USB,
-	DEVICE,
-	SOURCE,
-	SINK,
-	DUAL_ROLE,
-	SOP,
-	BC12,
+/*
+ * BC_1_2_SUPPORT options
+ */
+enum bc_1_2_support {
+	BC_1_2_SUPPORT_NONE = 0,
+	BC_1_2_SUPPORT_PORTABLE_DEVICE = 1,
+	BC_1_2_SUPPORT_CHARGING_PORT = 2,
+	BC_1_2_SUPPORT_BOTH = 3
 };
 
-enum dtype {
-	SRC = 0,
-	SNK,
-	DRP
+enum power_source {
+	POWER_EXTERNAL = 0,
+	POWER_UFP = 1,
+	POWER_BOTH = 2,
 };
 
-enum vif_product_type {
-	PORT = 0,
-	CABLE,
-	RE_TIMER
+static void set_vif_field_c(struct vif_field_t *vif_field, const char *comment);
+
+/*
+ * index of component being set
+ */
+int component_index;
+
+/*
+ * TAG Name Strings
+ */
+#define NAME_INIT(str) [str] = VIF_ #str
+
+const char *vif_name[] = {
+	NAME_INIT(VIF_Specification),
+	NAME_INIT(Vendor_Name),
+	NAME_INIT(Model_Part_Number),
+	NAME_INIT(Product_Revision),
+	NAME_INIT(TID),
+	NAME_INIT(VIF_Product_Type),
+	NAME_INIT(Certification_Type),
 };
+BUILD_ASSERT(ARRAY_SIZE(vif_name) == VIF_Indexes);
 
-enum conn_type {
-	TYPE_A = 0,
-	TYPE_B,
-	TYPE_C,
-	MICRO_AB
+const char *vif_app_name[] = {
+	NAME_INIT(Vendor),
+	NAME_INIT(Name),
+	NAME_INIT(Version),
+};
+BUILD_ASSERT(ARRAY_SIZE(vif_app_name) == VIF_App_Indexes);
+
+const char *vif_component_name[] = {
+	NAME_INIT(Port_Label),
+	NAME_INIT(Connector_Type),
+	NAME_INIT(USB4_Supported),
+	NAME_INIT(USB_PD_Support),
+	NAME_INIT(PD_Port_Type),
+	NAME_INIT(Type_C_State_Machine),
+	NAME_INIT(Port_Battery_Powered),
+	NAME_INIT(BC_1_2_Support),
+	NAME_INIT(PD_Spec_Revision_Major),
+	NAME_INIT(PD_Spec_Revision_Minor),
+	NAME_INIT(PD_Spec_Version_Major),
+	NAME_INIT(PD_Spec_Version_Minor),
+	NAME_INIT(PD_Specification_Revision),
+	NAME_INIT(SOP_Capable),
+	NAME_INIT(SOP_P_Capable),
+	NAME_INIT(SOP_PP_Capable),
+	NAME_INIT(SOP_P_Debug_Capable),
+	NAME_INIT(SOP_PP_Debug_Capable),
+	NAME_INIT(Manufacturer_Info_Supported_Port),
+	NAME_INIT(Manufacturer_Info_VID_Port),
+	NAME_INIT(Manufacturer_Info_PID_Port),
+	NAME_INIT(USB_Comms_Capable),
+	NAME_INIT(DR_Swap_To_DFP_Supported),
+	NAME_INIT(DR_Swap_To_UFP_Supported),
+	NAME_INIT(Unconstrained_Power),
+	NAME_INIT(VCONN_Swap_To_On_Supported),
+	NAME_INIT(VCONN_Swap_To_Off_Supported),
+	NAME_INIT(Responds_To_Discov_SOP_UFP),
+	NAME_INIT(Responds_To_Discov_SOP_DFP),
+	NAME_INIT(Attempts_Discov_SOP),
+	NAME_INIT(Power_Interruption_Available),
+	NAME_INIT(Data_Reset_Supported),
+	NAME_INIT(Enter_USB_Supported),
+	NAME_INIT(Chunking_Implemented_SOP),
+	NAME_INIT(Unchunked_Extended_Messages_Supported),
+	NAME_INIT(Security_Msgs_Supported_SOP),
+	NAME_INIT(Num_Fixed_Batteries),
+	NAME_INIT(Num_Swappable_Battery_Slots),
+	NAME_INIT(ID_Header_Connector_Type_SOP),
+	NAME_INIT(Type_C_Can_Act_As_Host),
+	NAME_INIT(Type_C_Can_Act_As_Device),
+	NAME_INIT(Type_C_Implements_Try_SRC),
+	NAME_INIT(Type_C_Implements_Try_SNK),
+	NAME_INIT(Type_C_Supports_Audio_Accessory),
+	NAME_INIT(Type_C_Supports_VCONN_Powered_Accessory),
+	NAME_INIT(Type_C_Is_VCONN_Powered_Accessory),
+	NAME_INIT(Type_C_Is_Debug_Target_SRC),
+	NAME_INIT(Type_C_Is_Debug_Target_SNK),
+	NAME_INIT(Captive_Cable),
+	NAME_INIT(Captive_Cable_Is_eMarked),
+	NAME_INIT(RP_Value),
+	NAME_INIT(Type_C_Port_On_Hub),
+	NAME_INIT(Type_C_Power_Source),
+	NAME_INIT(Type_C_Sources_VCONN),
+	NAME_INIT(Type_C_Is_Alt_Mode_Controller),
+	NAME_INIT(Type_C_Is_Alt_Mode_Adapter),
+	NAME_INIT(USB4_Router_Index),
+	NAME_INIT(USB4_Lane_0_Adapter),
+	NAME_INIT(USB4_Max_Speed),
+	NAME_INIT(USB4_DFP_Supported),
+	NAME_INIT(USB4_UFP_Supported),
+	NAME_INIT(USB4_USB3_Tunneling_Supported),
+	NAME_INIT(USB4_DP_Tunneling_Supported),
+	NAME_INIT(USB4_PCIe_Tunneling_Supported),
+	NAME_INIT(USB4_TBT3_Compatibility_Supported),
+	NAME_INIT(USB4_CL1_State_Supported),
+	NAME_INIT(USB4_CL2_State_Supported),
+	NAME_INIT(USB4_Num_Retimers),
+	NAME_INIT(USB4_DP_Bit_Rate),
+	NAME_INIT(USB4_Num_DP_Lanes),
+	NAME_INIT(Host_Supports_USB_Data),
+	NAME_INIT(Host_Speed),
+	NAME_INIT(Host_Contains_Captive_Retimer),
+	NAME_INIT(Host_Truncates_DP_For_tDHPResponse),
+	NAME_INIT(Host_Gen1x1_tLinkTurnaround),
+	NAME_INIT(Host_Gen2x1_tLinkTurnaround),
+	NAME_INIT(Host_Is_Embedded),
+	NAME_INIT(Host_Suspend_Supported),
+	NAME_INIT(Is_DFP_On_Hub),
+	NAME_INIT(Hub_Port_Number),
+	NAME_INIT(Device_Supports_USB_Data),
+	NAME_INIT(Device_Speed),
+	NAME_INIT(Device_Contains_Captive_Retimer),
+	NAME_INIT(Device_Truncates_DP_For_tDHPResponse),
+	NAME_INIT(Device_Gen1x1_tLinkTurnaround),
+	NAME_INIT(Device_Gen2x1_tLinkTurnaround),
+	NAME_INIT(BC_1_2_Charging_Port_Type),
+	NAME_INIT(PD_Power_As_Source),
+	NAME_INIT(EPR_Supported_As_Src),
+	NAME_INIT(USB_Suspend_May_Be_Cleared),
+	NAME_INIT(Sends_Pings),
+	NAME_INIT(Accepts_PR_Swap_As_Src),
+	NAME_INIT(Accepts_PR_Swap_As_Snk),
+	NAME_INIT(Requests_PR_Swap_As_Src),
+	NAME_INIT(Requests_PR_Swap_As_Snk),
+	NAME_INIT(FR_Swap_Supported_As_Initial_Sink),
+	NAME_INIT(FR_Swap_Type_C_Current_Capability_As_Initial_Sink),
+	NAME_INIT(FR_Swap_Reqd_Type_C_Current_As_Initial_Source),
+	NAME_INIT(Master_Port),
+	NAME_INIT(Num_Src_PDOs),
+	NAME_INIT(PD_OC_Protection),
+	NAME_INIT(PD_OCP_Method),
+	NAME_INIT(PD_Power_As_Sink),
+	NAME_INIT(EPR_Supported_As_Snk),
+	NAME_INIT(No_USB_Suspend_May_Be_Set),
+	NAME_INIT(GiveBack_May_Be_Set),
+	NAME_INIT(Higher_Capability_Set),
+	NAME_INIT(Num_Snk_PDOs),
+	NAME_INIT(XID_SOP),
+	NAME_INIT(Data_Capable_As_USB_Host_SOP),
+	NAME_INIT(Data_Capable_As_USB_Device_SOP),
+	NAME_INIT(Product_Type_UFP_SOP),
+	NAME_INIT(Product_Type_DFP_SOP),
+	NAME_INIT(DFP_VDO_Port_Number),
+	NAME_INIT(Modal_Operation_Supported_SOP),
+	NAME_INIT(USB_VID_SOP),
+	NAME_INIT(PID_SOP),
+	NAME_INIT(bcdDevice_SOP),
+	NAME_INIT(SVID_Fixed_SOP),
+	NAME_INIT(Num_SVIDs_Min_SOP),
+	NAME_INIT(Num_SVIDs_Max_SOP),
+	NAME_INIT(AMA_HW_Vers),
+	NAME_INIT(AMA_FW_Vers),
+	NAME_INIT(AMA_VCONN_Reqd),
+	NAME_INIT(AMA_VCONN_Power),
+	NAME_INIT(AMA_VBUS_Reqd),
+	NAME_INIT(AMA_Superspeed_Support),
+	NAME_INIT(Product_Total_Source_Power_mW),
+	NAME_INIT(Port_Source_Power_Type),
+	NAME_INIT(Port_Source_Power_Gang),
+	NAME_INIT(Port_Source_Power_Gang_Max_Power),
+	NAME_INIT(XID),
+	NAME_INIT(Data_Capable_As_USB_Host),
+	NAME_INIT(Data_Capable_As_USB_Device),
+	NAME_INIT(Product_Type),
+	NAME_INIT(Modal_Operation_Supported),
+	NAME_INIT(USB_VID),
+	NAME_INIT(PID),
+	NAME_INIT(bcdDevice),
+	NAME_INIT(Cable_HW_Vers),
+	NAME_INIT(Cable_FW_Vers),
+	NAME_INIT(Type_C_To_Type_A_B_C),
+	NAME_INIT(Type_C_To_Type_C_Capt_Vdm_V2),
+	NAME_INIT(EPR_Mode_Capable),
+	NAME_INIT(Cable_Latency),
+	NAME_INIT(Cable_Termination_Type),
+	NAME_INIT(VBUS_Through_Cable),
+	NAME_INIT(Cable_VBUS_Current),
+	NAME_INIT(Cable_Superspeed_Support),
+	NAME_INIT(Cable_USB_Highest_Speed),
+	NAME_INIT(Max_VBUS_Voltage_Vdm_V2),
+	NAME_INIT(Manufacturer_Info_Supported),
+	NAME_INIT(Manufacturer_Info_VID),
+	NAME_INIT(Manufacturer_Info_PID),
+	NAME_INIT(Chunking_Implemented),
+	NAME_INIT(Security_Msgs_Supported),
+	NAME_INIT(ID_Header_Connector_Type),
+	NAME_INIT(SVID_Fixed),
+	NAME_INIT(Cable_Num_SVIDs_Min),
+	NAME_INIT(Cable_Num_SVIDs_Max),
+	NAME_INIT(VPD_HW_Vers),
+	NAME_INIT(VPD_FW_Vers),
+	NAME_INIT(VPD_Max_VBUS_Voltage),
+	NAME_INIT(VPD_Charge_Through_Support),
+	NAME_INIT(VPD_Charge_Through_Current),
+	NAME_INIT(VPD_VBUS_Impedance),
+	NAME_INIT(VPD_Ground_Impedance),
+	NAME_INIT(Cable_SOP_PP_Controller),
+	NAME_INIT(SBU_Supported),
+	NAME_INIT(SBU_Type),
+	NAME_INIT(Active_Cable_Max_Operating_Temp),
+	NAME_INIT(Active_Cable_Shutdown_Temp),
+	NAME_INIT(Active_Cable_U3_CLd_Power),
+	NAME_INIT(Active_Cable_U3_U0_Trans_Mode),
+	NAME_INIT(Active_Cable_Physical_Connection),
+	NAME_INIT(Active_Cable_Active_Element),
+	NAME_INIT(Active_Cable_USB4_Support),
+	NAME_INIT(Active_Cable_USB2_Hub_Hops_Consumed),
+	NAME_INIT(Active_Cable_USB2_Supported),
+	NAME_INIT(Active_Cable_USB32_Supported),
+	NAME_INIT(Active_Cable_USB_Lanes),
+	NAME_INIT(Active_Cable_Optically_Isolated),
+	NAME_INIT(Active_Cable_USB_Gen),
+	NAME_INIT(Repeater_One_Type),
+	NAME_INIT(Repeater_Two_Type),
 };
+BUILD_ASSERT(ARRAY_SIZE(vif_component_name) == Component_Indexes);
 
-enum port_type {
-	PT_CONSUMER = 0,
-	PT_CONSUMER_PROVIDER,
-	PT_PROVIDER_CONSUMER,
-	PT_PROVIDER,
-	PT_DRP,
-	PT_EMARKER
+const char *vif_component_snk_pdo_name[] = {
+	NAME_INIT(Snk_PDO_Supply_Type), NAME_INIT(Snk_PDO_APDO_Type),
+	NAME_INIT(Snk_PDO_Voltage),	NAME_INIT(Snk_PDO_PDP_Rating),
+	NAME_INIT(Snk_PDO_Op_Power),	NAME_INIT(Snk_PDO_Min_Voltage),
+	NAME_INIT(Snk_PDO_Max_Voltage), NAME_INIT(Snk_PDO_Op_Current),
 };
+BUILD_ASSERT(ARRAY_SIZE(vif_component_snk_pdo_name) == Snk_PDO_Indexes);
+
+const char *vif_component_src_pdo_name[] = {
+	NAME_INIT(Src_PDO_Supply_Type),
+	NAME_INIT(Src_PDO_APDO_Type),
+	NAME_INIT(Src_PDO_Peak_Current),
+	NAME_INIT(Src_PDO_Voltage),
+	NAME_INIT(Src_PDO_Max_Current),
+	NAME_INIT(Src_PDO_Min_Voltage),
+	NAME_INIT(Src_PDO_Max_Voltage),
+	NAME_INIT(Src_PDO_Max_Power),
+	NAME_INIT(Src_PD_OCP_OC_Debounce),
+	NAME_INIT(Src_PD_OCP_OC_Threshold),
+	NAME_INIT(Src_PD_OCP_UV_Debounce),
+	NAME_INIT(Src_PD_OCP_UV_Threshold_Type),
+	NAME_INIT(Src_PD_OCP_UV_Threshold),
+};
+BUILD_ASSERT(ARRAY_SIZE(vif_component_src_pdo_name) == Src_PDO_Indexes);
 
-enum bc_1_2_support {
-	BC_NONE = 0,
-	BC_PORTABLE_DEVICE,
-	BC_CHARGING_PORT,
-	BC_BOTH
+const char *vif_component_sop_svid_mode_name[] = {
+	NAME_INIT(SVID_Mode_Enter_SOP),
+	NAME_INIT(SVID_Mode_Recog_Mask_SOP),
+	NAME_INIT(SVID_Mode_Recog_Value_SOP),
 };
+BUILD_ASSERT(ARRAY_SIZE(vif_component_sop_svid_mode_name) ==
+	     SopSVID_Mode_Indexes);
+
+const char *vif_component_sop_svid_name[] = {
+	NAME_INIT(SVID_SOP),
+	NAME_INIT(SVID_Modes_Fixed_SOP),
+	NAME_INIT(SVID_Num_Modes_Min_SOP),
+	NAME_INIT(SVID_Num_Modes_Max_SOP),
+};
+BUILD_ASSERT(ARRAY_SIZE(vif_component_sop_svid_name) == SopSVID_Indexes);
 
-enum power_source {
-	PS_EXT_POWERED = 0,
-	PS_UFP_POWERED,
-	PS_BOTH
+const char *vif_cable_mode_name[] = {
+	NAME_INIT(SVID_Mode_Enter),
+	NAME_INIT(SVID_Mode_Recog_Mask),
+	NAME_INIT(SVID_Mode_Recog_Value),
 };
+BUILD_ASSERT(ARRAY_SIZE(vif_cable_mode_name) == CableSVID_Mode_Indexes);
 
-enum usb_speed {
-	USB_2,
-	USB_GEN11,
-	USB_GEN21,
-	USB_GEN12,
-	USB_GEN22
+const char *vif_cable_svid_name[] = {
+	NAME_INIT(SVID),
+	NAME_INIT(SVID_Modes_Fixed),
+	NAME_INIT(SVID_Num_Modes_Min),
+	NAME_INIT(SVID_Num_Modes_Max),
+};
+BUILD_ASSERT(ARRAY_SIZE(vif_cable_svid_name) == CableSVID_Indexes);
+
+const char *vif_product_name[] = {
+	NAME_INIT(USB4_DROM_Vendor_ID),
+	NAME_INIT(USB4_Dock),
+	NAME_INIT(USB4_Num_Internal_Host_Controllers),
+	NAME_INIT(USB4_Num_PCIe_DN_Bridges),
+	NAME_INIT(USB4_Device_HiFi_Bi_TMU_Mode_Required),
+	NAME_INIT(USB4_Audio_Supported),
+	NAME_INIT(USB4_HID_Supported),
+	NAME_INIT(USB4_Printer_Supported),
+	NAME_INIT(USB4_Mass_Storage_Supported),
+	NAME_INIT(USB4_Video_Supported),
+	NAME_INIT(USB4_Comms_Networking_Supported),
+	NAME_INIT(USB4_Media_Transfer_Protocol_Supported),
+	NAME_INIT(USB4_Smart_Card_Supported),
+	NAME_INIT(USB4_Still_Image_Capture_Supported),
+	NAME_INIT(USB4_Monitor_Device_Supported),
 };
+BUILD_ASSERT(ARRAY_SIZE(vif_product_name) == Product_Indexes);
 
-const uint32_t *src_pdo;
-uint32_t src_pdo_cnt;
+const char *vif_product_pcie_endpoint_name[] = {
+	NAME_INIT(USB4_PCIe_Endpoint_Vendor_ID),
+	NAME_INIT(USB4_PCIe_Endpoint_Device_ID),
+	NAME_INIT(USB4_PCIe_Endpoint_Class_Code),
+};
+BUILD_ASSERT(ARRAY_SIZE(vif_product_pcie_endpoint_name) ==
+	     PCIe_Endpoint_Indexes);
+
+const char *vif_product_usb4_router_name[] = {
+	NAME_INIT(USB4_Router_ID),
+	NAME_INIT(USB4_Silicon_VID),
+	NAME_INIT(USB4_Num_Lane_Adapters),
+	NAME_INIT(USB4_Num_USB3_DN_Adapters),
+	NAME_INIT(USB4_Num_DP_IN_Adapters),
+	NAME_INIT(USB4_Num_DP_OUT_Adapters),
+	NAME_INIT(USB4_Num_PCIe_DN_Adapters),
+	NAME_INIT(USB4_TBT3_Not_Supported),
+	NAME_INIT(USB4_PCIe_Wake_Supported),
+	NAME_INIT(USB4_USB3_Wake_Supported),
+	NAME_INIT(USB4_Num_Unused_Adapters),
+	NAME_INIT(USB4_TBT3_VID),
+	NAME_INIT(USB4_PCIe_Switch_Vendor_ID),
+	NAME_INIT(USB4_PCIe_Switch_Device_ID),
+	NAME_INIT(USB4_Num_PCIe_Endpoints),
+};
+BUILD_ASSERT(ARRAY_SIZE(vif_product_usb4_router_name) == USB4_Router_Indexes);
 
-char *yes_no(int val)
+static bool streq(const char *str1, const char *str2)
 {
-	return val ? "YES" : "NO";
+	if (str1 == NULL && str2 == NULL)
+		return 1;
+	if (str1 == NULL || str2 == NULL)
+		return 0;
+	return strcasecmp(str1, str2) == 0;
 }
 
-enum ec_image system_get_image_copy(void)
+static bool is_start_tag(const char *xmlstr, const char *viftag)
 {
-	return EC_IMAGE_RW;
-}
+	const char *xmltag;
 
-static void write_title(FILE *vif)
-{
-	fprintf(vif, ";\r\n");
-	fprintf(vif, "; %s \r\n", GENVIF_TITLE);
-	fprintf(vif, ";\r\n");
+	if (strncasecmp(xmlstr, VIF_, sizeof(VIF_) - 1) != 0)
+		return 0;
+
+	xmltag = xmlstr + sizeof(VIF_) - 1;
+	return strcasecmp(xmltag, viftag) == 0;
 }
 
-static void write_field(FILE *vif, enum field t)
+static bool is_end_tag(const char *xmlstr, const char *viftag)
 {
-	if (!vif)
-		return;
+	const char *xmltag;
 
-	fprintf(vif, "\r\n%s\r\n",
-	";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;");
-	switch (t) {
-	case INTRO:
-		fprintf(vif, ";   Intro Fields\r\n");
-		break;
-	case PRODUCT:
-		fprintf(vif, ";   VIF Product Fields\r\n");
-		break;
-	case GENERAL:
-		fprintf(vif, ";   General PD Fields\r\n");
-		break;
-	case USB:
-		fprintf(vif, ";   USB Type-C Fields\r\n");
-		break;
-	case DEVICE:
-		fprintf(vif, ";   USB Device Fields\r\n");
-		break;
-	case SOURCE:
-		fprintf(vif, ";   PD Source Fields\r\n");
-		break;
-	case SINK:
-		fprintf(vif, ";   PD Sink Fields\r\n");
-		break;
-	case DUAL_ROLE:
-		fprintf(vif, ";   PD Dual Role Fields\r\n");
-		break;
-	case SOP:
-		fprintf(vif, ";   SOP Discovery Fields\r\n");
-		break;
-	case BC12:
-		fprintf(vif, ":   Battery Charging 1.2 Fields\r\n");
-		break;
+	if (xmlstr[0] != '/')
+		return 0;
 
-	}
-	fprintf(vif, "%s\r\n",
-	";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;");
-}
+	if (strncasecmp(xmlstr + 1, VIF_, sizeof(VIF_) - 1) != 0)
+		return 0;
 
-static void init_src_pdos(void)
-{
-#ifdef CONFIG_USB_PD_DYNAMIC_SRC_CAP
-	src_pdo_cnt = charge_manager_get_source_pdo(&src_pdo, 0);
-#else
-	src_pdo_cnt = pd_src_pdo_cnt;
-	src_pdo = pd_src_pdo;
-#endif
+	xmltag = xmlstr + 1 + sizeof(VIF_) - 1;
+	return strcasecmp(xmltag, viftag) == 0;
 }
 
-static int is_src(void)
+/*****************************************************************************
+ * VIF Structure Override Value Retrieve Functions
+ */
+/** Number **/
+static bool get_vif_field_tag_number(struct vif_field_t *vif_field, int *value)
 {
-	return src_pdo_cnt;
-}
+	if (vif_field->tag_value == NULL)
+		return false;
 
-static int is_snk(void)
-{
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-	return pd_snk_pdo_cnt;
-#else
-	return 0;
-#endif
+	*value = atoi(vif_field->tag_value);
+	return true;
 }
-
-static int is_drp(void)
+static bool get_vif_field_str_number(struct vif_field_t *vif_field, int *value)
 {
-	if (is_src())
-		return !!(src_pdo[0] & PDO_FIXED_DUAL_ROLE);
-	else
-		return 0;
-}
+	if (vif_field->str_value == NULL)
+		return false;
 
-/* Application exits on failure */
-__attribute__((__format__(__printf__, 2, 3)))
-static void append(char **buf, const char *fmt, ...)
+	*value = atoi(vif_field->str_value);
+	return true;
+}
+static bool get_vif_field_number(struct vif_field_t *vif_field, int *value)
 {
-	va_list ap1, ap2;
-	int n;
-	static int offset;
-
-	va_start(ap1, fmt);
-	va_copy(ap2, ap1);
+	bool rv;
 
-	n = vsnprintf(NULL, 0, fmt, ap1) + 1;
+	rv = get_vif_field_tag_number(vif_field, value);
+	if (!rv)
+		rv = get_vif_field_str_number(vif_field, value);
 
-	if (*buf == NULL)
-		offset = 0;
-
-	*buf = (char *)realloc(*buf, offset + n);
-
-	if (*buf) {
-		vsnprintf(*buf + offset, n, fmt, ap2);
-	} else {
-		fprintf(stderr, "ERROR: Out of memory.\n");
-		exit(EXIT_FAILURE);
-	}
-
-	/* Overwrite NULL terminator the next time through. */
-	offset += (n-1);
-
-	va_end(ap1);
-	va_end(ap2);
+	return rv;
 }
-
-static int32_t write_pdo_to_buf(char **buf, uint32_t pdo,
-				enum dtype type, uint32_t pnum)
+__maybe_unused static int get_vif_number(struct vif_field_t *vif_field,
+					 int default_value)
 {
-	int32_t power;
+	int ret_value;
 
-	if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_FIXED) {
-		uint32_t current = pdo & 0x3ff;
-		uint32_t voltage = (pdo >> 10) & 0x3ff;
-
-		power = ((current * 10) * (voltage * 50)) / 1000;
-
-		append(buf, "\t%s_PDO_Supply_Type%d: 0\r\n",
-			(type == SRC) ? "Src" : "Snk", pnum);
-
-		if (type == SRC)
-			append(buf, "\tSrc_PDO_Peak_Current%d: 0\r\n", pnum);
-
-		append(buf, "\t%s_PDO_Voltage%d: %d\r\n",
-				(type == SRC) ? "Src" : "Snk", pnum, voltage);
-
-		if (type == SRC)
-			append(buf, "\tSrc_PDO_Max_Current%d: %d\r\n", pnum,
-				current);
-		else
-			append(buf, "\tSnk_PDO_Op_Current%d: %d\r\n", pnum,
-				current);
-
-	} else if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_BATTERY) {
-		uint32_t max_voltage = (pdo >> 20) & 0x3ff;
-		uint32_t min_voltage = (pdo >> 10) & 0x3ff;
-
-		power = pdo & 0x3ff;
+	if (!get_vif_field_number(vif_field, &ret_value))
+		ret_value = default_value;
 
-		append(buf, "\t%s_PDO_Supply_Type%d: 1\r\n",
-			(type == SRC) ? "Src" : "Snk", pnum);
+	return ret_value;
+}
 
-		append(buf, "\t%s_PDO_Min_Voltage%d: %d\r\n",
-			(type == SRC) ? "Src" : "Snk", pnum, min_voltage);
+/** Boolean **/
+static bool get_vif_field_tag_bool(struct vif_field_t *vif_field, bool *value)
+{
+	if (vif_field->tag_value == NULL)
+		return false;
 
-		append(buf, "\t%s_PDO_Max_Voltage%d: %d\r\n",
-			(type == SRC) ? "Src" : "Snk", pnum, max_voltage);
+	*value = streq(vif_field->tag_value, "true");
+	return true;
+}
+static bool get_vif_field_str_bool(struct vif_field_t *vif_field, bool *value)
+{
+	if (vif_field->str_value == NULL)
+		return false;
 
-		if (type == SRC)
-			append(buf, "\tSrc_PDO_Max_Power%d: %d\r\n", pnum,
-				power);
-		else
-			append(buf, "\tSnk_PDO_Op_Power%d: %d\r\n", pnum,
-				power);
+	*value = streq(vif_field->str_value, "YES");
+	return true;
+}
+static bool get_vif_field_bool(struct vif_field_t *vif_field, bool *value)
+{
+	bool rv;
 
-	} else if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_VARIABLE) {
-		uint32_t max_voltage = (pdo >> 20) & 0x3ff;
-		uint32_t min_voltage = (pdo >> 10) & 0x3ff;
-		uint32_t current = pdo & 0x3ff;
+	rv = get_vif_field_tag_bool(vif_field, value);
+	if (!rv)
+		rv = get_vif_field_str_bool(vif_field, value);
 
-		power = ((current * 10) * (max_voltage * 50)) / 1000;
+	return rv;
+}
+static bool get_vif_bool(struct vif_field_t *vif_field, bool default_value)
+{
+	bool ret_value;
 
-		append(buf, "\t%s_PDO_Supply_Type%d: 2\r\n",
-			(type == SRC) ? "Src" : "Snk", pnum);
+	if (!get_vif_field_bool(vif_field, &ret_value))
+		ret_value = default_value;
 
-		if (type == SRC)
-			append(buf, "\tSrc_PDO_Peak_Current%d: 0\r\n", pnum);
+	return ret_value;
+}
 
-		append(buf, "\t%s_PDO_Min_Voltage%d: %d\r\n",
-			(type == SRC) ? "Src" : "Snk", pnum, min_voltage);
+/** String **/
+__maybe_unused static bool get_vif_field_tag_str(struct vif_field_t *vif_field,
+						 char **value)
+{
+	if (vif_field->tag_value == NULL)
+		return false;
 
-		append(buf, "\t%s_PDO_Max_Voltage%d: %d\r\n",
-			(type == SRC) ? "Src" : "Snk", pnum, max_voltage);
+	*value = vif_field->tag_value;
+	return true;
+}
+__maybe_unused static bool get_vif_field_str_str(struct vif_field_t *vif_field,
+						 char **value)
+{
+	if (vif_field->str_value == NULL)
+		return false;
 
-		if (type == SRC)
-			append(buf, "\tSrc_PDO_Max_Current%d: %d\r\n", pnum,
-				current);
-		else
-			append(buf, "\tSnk_PDO_Op_Current%d: %d\r\n", pnum,
-				current);
-	} else if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_AUGMENTED) {
-		uint32_t pps = (pdo >> 28) & 3;
-		uint32_t pps_max_voltage = (pdo >> 17) & 0xff;
-		uint32_t pps_min_voltage = (pdo >> 8) & 0xff;
-		uint32_t pps_current = pdo & 0x7f;
+	*value = vif_field->str_value;
+	return true;
+}
+/*
+ * VIF Structure Override Value Retrieve Functions
+ *****************************************************************************/
 
-		if (pps) {
-			fprintf(stderr, "ERROR: Invalid PDO_TYPE %d.\n", pdo);
-			return -1;
+/*****************************************************************************
+ * Generic Helper Functions
+ */
+static bool is_src(void)
+{
+	int override_value;
+	bool was_overridden;
+
+	/* Determine if we are DRP, SRC or SNK */
+	was_overridden = get_vif_field_tag_number(
+		&vif.Component[component_index].vif_field[Type_C_State_Machine],
+		&override_value);
+	if (was_overridden) {
+		switch (override_value) {
+		case SRC:
+		case DRP:
+			return true;
+		case SNK:
+			return false;
+		default:
+			was_overridden = false;
+			break;
 		}
-
-		append(buf, "\t%s_PDO_Supply_Type%d: 3\r\n",
-			(type == SRC) ? "Src" : "Snk", pnum);
-
-		if (type == SRC)
-			append(buf, "\tSrc_PDO_Max_Current%d: %d\r\n", pnum,
-							pps_current);
-		else
-			append(buf, "\tSnk_PDO_Op_Current%d: %d\r\n", pnum,
-							pps_current);
-
-		append(buf, "\t%s_PDO_Min_Voltage%d: %d\r\n",
-			(type == SRC) ? "Src" : "Snk", pnum, pps_min_voltage);
-
-		append(buf, "\t%s_PDO_Max_Voltage%d: %d\r\n",
-			(type == SRC) ? "Src" : "Snk", pnum, pps_max_voltage);
-	} else {
-		fprintf(stderr, "ERROR: Invalid PDO_TYPE %d.\n", pdo);
-		return -1;
 	}
-
-	append(buf, "\r\n");
-
-	return power;
+	if (!was_overridden) {
+		was_overridden = get_vif_field_tag_number(
+			&vif.Component[component_index].vif_field[PD_Port_Type],
+			&override_value);
+		if (was_overridden) {
+			switch (override_value) {
+			case PORT_PROVIDER_ONLY: /* SRC */
+			case PORT_DRP: /* DRP */
+				return true;
+			case PORT_CONSUMER_ONLY: /* SNK */
+				return false;
+			default:
+				was_overridden = false;
+			}
+		}
+	}
+	return src_pdo_cnt;
+}
+static bool is_snk(void)
+{
+	int override_value;
+	bool was_overridden;
+
+	/* Determine if we are DRP, SRC or SNK */
+	was_overridden = get_vif_field_tag_number(
+		&vif.Component[component_index].vif_field[Type_C_State_Machine],
+		&override_value);
+	if (was_overridden) {
+		switch (override_value) {
+		case SNK:
+		case DRP:
+			return true;
+		case SRC:
+			return false;
+		default:
+			was_overridden = false;
+			break;
+		}
+	}
+	if (!was_overridden) {
+		was_overridden = get_vif_field_tag_number(
+			&vif.Component[component_index].vif_field[PD_Port_Type],
+			&override_value);
+		if (was_overridden) {
+			switch (override_value) {
+			case PORT_CONSUMER_ONLY: /* SNK */
+			case PORT_DRP: /* DRP */
+				return true;
+			case PORT_PROVIDER_ONLY: /* SRC */
+				return false;
+			default:
+				was_overridden = false;
+			}
+		}
+	}
+	return (IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE)) ? pd_snk_pdo_cnt : 0;
+}
+static bool is_drp(void)
+{
+	int override_value;
+	bool was_overridden;
+
+	/* Determine if we are DRP, SRC or SNK */
+	was_overridden = get_vif_field_tag_number(
+		&vif.Component[component_index].vif_field[Type_C_State_Machine],
+		&override_value);
+	if (was_overridden) {
+		switch (override_value) {
+		case DRP:
+			return true;
+		case SNK:
+			return false;
+		case SRC:
+		default:
+			was_overridden = false;
+			break;
+		}
+	}
+	if (!was_overridden) {
+		was_overridden = get_vif_field_tag_number(
+			&vif.Component[component_index].vif_field[PD_Port_Type],
+			&override_value);
+		if (was_overridden) {
+			switch (override_value) {
+			case PORT_DRP: /* DRP */
+				return true;
+			case PORT_CONSUMER_ONLY: /* SNK */
+				return false;
+			case PORT_PROVIDER_ONLY: /* SRC */
+			default:
+				was_overridden = false;
+			}
+		}
+	}
+	if (is_src())
+		return !!(src_pdo[0] & PDO_FIXED_DUAL_ROLE);
+	return false;
 }
 
-/*
- * Intro Fields
- */
-
-static void write_vif_specification(FILE *vif)
+static bool can_act_as_device(void)
 {
-	fprintf(vif, "$VIF_Specification: \"%s\"\r\n", VIF_SPEC);
+	return get_vif_bool(&vif.Component[component_index]
+				     .vif_field[Type_C_Can_Act_As_Device],
+#if defined(USB_DEV_CLASS) && defined(USB_CLASS_BILLBOARD)
+			    USB_DEV_CLASS == USB_CLASS_BILLBOARD
+#else
+			    false
+#endif
+	);
 }
 
-static void write_vif_producer(FILE *vif, const char *vp)
+static bool can_act_as_host(void)
 {
-	fprintf(vif, "$VIF_Producer: \"%s\"\r\n", vp);
+	return get_vif_bool(&vif.Component[component_index]
+				     .vif_field[Type_C_Can_Act_As_Host],
+			    (!(IS_ENABLED(CONFIG_USB_CTVPD) ||
+			       IS_ENABLED(CONFIG_USB_VPD))));
 }
 
-static void write_vendor_name(FILE *vif)
+static bool is_usb4_supported(void)
 {
-	fprintf(vif, "$Vendor_Name: \"%s\"\r\n", VENDOR_NAME);
+	return get_vif_bool(
+		&vif.Component[component_index].vif_field[USB4_Supported],
+		IS_ENABLED(CONFIG_USB_PD_USB4));
 }
 
-static void write_model_part_number(FILE *vif)
+static bool is_usb4_tbt3_compatible(void)
 {
-#ifdef CONFIG_USB_PD_MODEL_PART_NUMBER
-	fprintf(vif, "$Model_Part_Number: \"%s\"\r\n",
-					CONFIG_USB_PD_MODEL_PART_NUMBER);
-#endif
+	return get_vif_bool(
+		&vif.Component[component_index]
+			 .vif_field[USB4_TBT3_Compatibility_Supported],
+		IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE));
 }
 
-static void write_product_revision(FILE *vif)
+static bool is_usb4_pcie_tunneling_supported(void)
 {
-#ifdef CONFIG_USB_PD_PRODUCT_REVISION
-	fprintf(vif, "$Model_Part_Number: \"%s\"\r\n",
-					CONFIG_USB_PD_PRODUCT_REVISION);
-#endif
+	return get_vif_bool(&vif.Component[component_index]
+				     .vif_field[USB4_PCIe_Tunneling_Supported],
+			    IS_ENABLED(CONFIG_USB_PD_PCIE_TUNNELING));
 }
 
-static void write_tid(FILE *vif)
+static bool is_usb_pd_supported(void)
 {
-#ifdef CONFIG_USB_PD_TID
-	fprintf(vif, "$TID: \"%s\"\r\n", CONFIG_USB_PD_TID);
-#endif
+	return get_vif_bool(
+		&vif.Component[component_index].vif_field[USB_PD_Support],
+		(is_usb4_supported() || IS_ENABLED(CONFIG_USB_PRL_SM) ||
+		 IS_ENABLED(CONFIG_USB_POWER_DELIVERY)));
 }
 
-/*
- * VIF Product Fields
- */
-
-static void write_vif_product_type(FILE *vif)
+static bool is_usb_comms_capable(void)
 {
-	fprintf(vif, "VIF_Product_Type: %d\r\n", PORT);
+	return get_vif_bool(
+		&vif.Component[component_index].vif_field[USB_Comms_Capable],
+		is_usb4_supported() || (!(IS_ENABLED(CONFIG_USB_VPD) ||
+					  IS_ENABLED(CONFIG_USB_CTVPD))));
 }
 
-static void write_port_label(FILE *vif)
+static bool is_alt_mode_controller(void)
 {
-#ifdef CONFIG_USB_PD_PORT_LABEL
-	fprintf(vif, "$Port_Label: %s\r\n", CONFIG_USB_PD_PORT_LABEL);
-#endif
+	return get_vif_bool(&vif.Component[component_index]
+				     .vif_field[Type_C_Is_Alt_Mode_Controller],
+			    IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP));
 }
 
-static void write_connector_type(FILE *vif)
+static bool is_alt_mode_adapter(void)
 {
-	fprintf(vif, "Connector_Type: %d\r\n", TYPE_C);
+	return get_vif_bool(&vif.Component[component_index]
+				     .vif_field[Type_C_Is_Alt_Mode_Adapter],
+			    IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP));
 }
 
-static void write_usb_pd_support(FILE *vif)
+static bool does_respond_to_discov_sop_ufp(void)
 {
-	char *yn = "NO";
-
-#if defined(CONFIG_USB_PRL_SM) || defined(CONFIG_USB_POWER_DELIVERY)
-	yn = "YES";
-#endif
+	return get_vif_bool(&vif.Component[component_index]
+				     .vif_field[Responds_To_Discov_SOP_UFP],
+			    (is_usb4_supported() ||
+			     IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE)));
+}
 
-	fprintf(vif, "USB_PD_Support: %s\n", yn);
+static bool does_respond_to_discov_sop_dfp(void)
+{
+	return get_vif_bool(&vif.Component[component_index]
+				     .vif_field[Responds_To_Discov_SOP_DFP],
+			    (is_usb4_supported() ||
+			     IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE)));
 }
 
-static void write_pd_port_type(FILE *vif, enum dtype type)
+static bool does_support_device_usb_data(void)
+{
+	return get_vif_bool(&vif.Component[component_index]
+				     .vif_field[Device_Supports_USB_Data],
+			    (is_usb4_supported() || can_act_as_device()));
+}
 
+static bool does_support_host_usb_data(void)
 {
-	enum port_type pt;
+	int type_c_state_machine;
 
-	switch (type) {
-	case SNK:
-		pt = PT_CONSUMER;
-		break;
-	case SRC:
-		pt = PT_PROVIDER;
-		break;
-	case DRP:
-		pt = PT_DRP;
-		break;
-	}
+	if (!get_vif_field_tag_number(&vif.Component[component_index]
+					       .vif_field[Type_C_State_Machine],
+				      &type_c_state_machine))
+		return false;
 
-	fprintf(vif, "PD_Port_Type: %d\r\n", pt);
+	return get_vif_bool(&vif.Component[component_index]
+				     .vif_field[Host_Supports_USB_Data],
+			    can_act_as_host());
 }
 
-static void write_type_c_state_machine(FILE *vif, enum dtype type)
+static int vif_get_max_tbt_speed(void)
 {
-	fprintf(vif, "Type_C_State_Machine: %d\r\n", type);
-}
+	struct vif_Component_t *c;
 
-static void write_captive_cable(FILE *vif)
-{
-	fprintf(vif, "Captive_Cable: NO\r\n");
+	c = &vif.Component[component_index];
+	return get_vif_number(&c->vif_field[USB4_Max_Speed], -1);
 }
 
-static void write_port_battery_powered(FILE *vif)
+static void init_src_pdos(void)
 {
-#ifdef CONFIG_BATTERY
-	fprintf(vif, "Port_Battery_Powered: YES\r\n");
-#else
-	fprintf(vif, "Port_Battery_Powered: NO\r\n");
-#endif
+	if (IS_ENABLED(CONFIG_USB_PD_DYNAMIC_SRC_CAP)) {
+		src_pdo_cnt = charge_manager_get_source_pdo(&src_pdo, 0);
+	} else {
+		if (IS_ENABLED(CONFIG_USB_PD_CUSTOM_PDO)) {
+			src_pdo_cnt = pd_src_pdo_cnt;
+			src_pdo = pd_src_pdo;
+		} else {
+			src_pdo_cnt = pd_src_pdo_max_cnt;
+			src_pdo = pd_src_pdo_max;
+		}
+	}
 }
 
-static void write_bc_1_2_support(FILE *vif, enum dtype type)
+static bool vif_fields_present(const struct vif_field_t *vif_fields, int count)
 {
-	enum bc_1_2_support bc = BC_NONE;
+	int index;
 
-	fprintf(vif, "BC_1_2_Support: %d\r\n", bc);
+	for (index = 0; index < count; ++index) {
+		if (vif_fields[index].str_value ||
+		    vif_fields[index].tag_value) {
+			return true;
+		}
+	}
+	return false;
 }
-
 /*
- * General PD Fields
+ * Generic Helper Functions
+ *****************************************************************************/
+
+/*****************************************************************************
+ * VIF XML Output Functions
  */
+static void vif_out_str(FILE *vif_file, int level, const char *str)
+{
+	while (level-- > 0)
+		fprintf(vif_file, "  ");
+	fprintf(vif_file, "%s\r\n", str);
+}
 
-static void write_pd_spec_rev(FILE *vif)
+static void vif_out_start(FILE *vif_file, int level, const char *str)
 {
-	enum spec_rev rev;
+	while (level-- > 0)
+		fprintf(vif_file, "  ");
 
-#if defined(CONFIG_USB_PD_REV30) || defined(CONFIG_USB_PRL_SM)
-	rev = PD_REV_3_0;
-#else
-	rev = PD_REV_2_0;
-#endif
-	fprintf(vif, "PD_Specification_Revision: %d\r\n", rev);
+	fprintf(vif_file, "<" VIF_ "%s>\r\n", str);
 }
 
-static void write_usb_comms_capable(FILE *vif)
+static void vif_out_end(FILE *vif_file, int level, const char *str)
 {
-	char *yn = "YES";
+	while (level-- > 0)
+		fprintf(vif_file, "  ");
 
-#if defined(CONFIG_USB_VPD) || defined(CONFIG_USB_CTVPD)
-	yn = "NO";
-#endif
-	fprintf(vif, "USB_Comms_Capable: %s\r\n", yn);
+	fprintf(vif_file, "</" VIF_ "%s>\r\n", str);
 }
 
-static void write_dr_swap_to_dfp_supported(FILE *vif)
+static void vif_out_comment(FILE *vif_file, int level, const char *fmt, ...)
 {
-	char *yn = "NO";
+	va_list args;
+
+	while (level-- > 0)
+		fprintf(vif_file, "  ");
+
+	fprintf(vif_file, "<!--");
 
-	if (is_src() && (src_pdo[0] & PDO_FIXED_DATA_SWAP))
-		yn = yes_no(pd_check_data_swap(0, PD_ROLE_DFP));
+	va_start(args, fmt);
+	vfprintf(vif_file, fmt, args);
+	va_end(args);
 
-	fprintf(vif, "DR_Swap_To_DFP_Supported: %s\r\n", yn);
+	fprintf(vif_file, "-->\r\n");
 }
 
-static void write_dr_swap_to_ufp_supported(FILE *vif)
-{
-	char *yn = "NO";
+static const char vif_separator[] = ";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;"
+				    ";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;";
 
-	if (is_src() && (src_pdo[0] & PDO_FIXED_DATA_SWAP))
-		yn = yes_no(pd_check_data_swap(0, PD_ROLE_UFP));
+static void vif_out_field(FILE *vif_file, int level,
+			  const struct vif_field_t *vif_field)
+{
+	if (vif_field->name == NULL && vif_field->tag_value) {
+		int indent;
 
+		vif_out_comment(vif_file, level, vif_separator);
+		for (indent = level; indent-- > 0;)
+			fprintf(vif_file, "  ");
+		fprintf(vif_file, "<!--;%s-->\r\n", vif_field->tag_value);
+		vif_out_comment(vif_file, level, vif_separator);
+		return;
+	}
 
-	fprintf(vif, "DR_Swap_To_UFP_Supported: %s\r\n", yn);
+	if (vif_field->str_value || vif_field->tag_value) {
+		while (level-- > 0)
+			fprintf(vif_file, "  ");
+
+		fprintf(vif_file, "<%s", vif_field->name);
+		if (vif_field->tag_value)
+			fprintf(vif_file, " value=\"%s\"",
+				vif_field->tag_value);
+		if (vif_field->str_value)
+			fprintf(vif_file, ">%s</%s>\r\n", vif_field->str_value,
+				vif_field->name);
+		else
+			fprintf(vif_file, " />\r\n");
+	}
 }
 
-static void write_unconstrained_power(FILE *vif)
+static void vif_out_fields_range(FILE *vif_file, int level,
+				 const struct vif_field_t *vif_fields,
+				 int start, int count)
 {
-	int yn = 0;
+	int index;
 
-	if (is_src())
-		yn = !!(src_pdo[0] & PDO_FIXED_UNCONSTRAINED);
+	for (index = start; index < count; ++index)
+		vif_out_field(vif_file, level, &vif_fields[index]);
+}
 
-	fprintf(vif, "Unconstrained_Power: %s\r\n", yes_no(yn));
+static void vif_out_fields(FILE *vif_file, int level,
+			   const struct vif_field_t *vif_fields, int count)
+{
+	vif_out_fields_range(vif_file, level, vif_fields, 0, count);
 }
 
-static void write_vconn_swap_to_on_supported(FILE *vif)
+static void vif_output_vif_component_cable_svid_mode_list(
+	FILE *vif_file, const struct vif_cableSVIDList_t *svid_list, int level)
 {
-	char *yn = "NO";
+	int index;
 
-#ifdef CONFIG_USBC_VCONN_SWAP
-	yn = "YES";
-#endif
+	if (!vif_fields_present(svid_list->CableSVIDModeList[0].vif_field,
+				CableSVID_Mode_Indexes))
+		return;
+
+	vif_out_start(vif_file, level++, "CableSVIDModeList");
+	for (index = 0; index < MAX_NUM_CABLE_SVID_MODES; ++index) {
+		const struct vif_cableSVIDModeList_t *mode_list =
+			&svid_list->CableSVIDModeList[index];
 
-	fprintf(vif, "VCONN_Swap_To_On_Supported: %s\r\n", yn);
+		if (!vif_fields_present(mode_list->vif_field,
+					CableSVID_Mode_Indexes))
+			break;
+
+		vif_out_start(vif_file, level++, "SOPSVIDMode");
+		vif_out_fields(vif_file, level, mode_list->vif_field,
+			       CableSVID_Mode_Indexes);
+		vif_out_end(vif_file, --level, "SOPSVIDMode");
+	}
+	vif_out_end(vif_file, --level, "CableSVIDModeList");
 }
 
-static void write_vconn_swap_to_off_supported(FILE *vif)
+static void vif_output_vif_component_cable_svid_list(
+	FILE *vif_file, const struct vif_Component_t *component, int level)
 {
-	char *yn = "NO";
+	int index;
 
-#ifdef CONFIG_USBC_VCONN_SWAP
-	yn = "YES";
-#endif
+	if (!vif_fields_present(component->CableSVIDList[0].vif_field,
+				CableSVID_Indexes))
+		return;
+
+	vif_out_start(vif_file, level++, "CableSVIDList");
+	for (index = 0; index < MAX_NUM_CABLE_SVIDS; ++index) {
+		const struct vif_cableSVIDList_t *svid_list =
+			&component->CableSVIDList[index];
+
+		if (!vif_fields_present(svid_list->vif_field,
+					CableSVID_Indexes))
+			break;
 
-	fprintf(vif, "VCONN_Swap_To_Off_Supported: %s\r\n", yn);
+		vif_out_start(vif_file, level++, "CableSVID");
+		vif_out_fields(vif_file, level, svid_list->vif_field,
+			       CableSVID_Indexes);
+		vif_output_vif_component_cable_svid_mode_list(vif_file,
+							      svid_list, level);
+		vif_out_end(vif_file, --level, "CableSVID");
+	}
+	vif_out_end(vif_file, --level, "CableSVIDList");
 }
 
-static void write_responds_to_discov_sop_ufp(FILE *vif)
+static void vif_output_vif_component_sop_svid_mode_list(
+	FILE *vif_file, const struct vif_sopSVIDList_t *svid_list, int level)
 {
-	fprintf(vif, "Responds_To_Discov_SOP_UFP: NO\r\n");
+	int index;
+
+	if (!vif_fields_present(svid_list->SOPSVIDModeList[0].vif_field,
+				SopSVID_Mode_Indexes))
+		return;
+
+	vif_out_start(vif_file, level++, "SOPSVIDModeList");
+	for (index = 0; index < MAX_NUM_SOP_SVID_MODES; ++index) {
+		const struct vif_sopSVIDModeList_t *mode_list =
+			&svid_list->SOPSVIDModeList[index];
+
+		if (!vif_fields_present(mode_list->vif_field,
+					SopSVID_Mode_Indexes))
+			break;
+
+		vif_out_start(vif_file, level++, "SOPSVIDMode");
+		vif_out_fields(vif_file, level, mode_list->vif_field,
+			       SopSVID_Mode_Indexes);
+		vif_out_end(vif_file, --level, "SOPSVIDMode");
+	}
+	vif_out_end(vif_file, --level, "SOPSVIDModeList");
 }
 
-static void write_responds_to_discov_sop_dfp(FILE *vif)
+static void vif_output_vif_component_sop_svid_list(
+	FILE *vif_file, const struct vif_Component_t *component, int level)
 {
-	fprintf(vif, "Responds_To_Discov_SOP_DFP: NO\r\n");
+	int index;
+
+	if (!vif_fields_present(component->SOPSVIDList[0].vif_field,
+				SopSVID_Indexes))
+		return;
+
+	vif_out_start(vif_file, level++, "SOPSVIDList");
+	for (index = 0; index < MAX_NUM_SOP_SVIDS; ++index) {
+		const struct vif_sopSVIDList_t *svid_list =
+			&component->SOPSVIDList[index];
+
+		if (!vif_fields_present(svid_list->vif_field, SopSVID_Indexes))
+			break;
+
+		vif_out_start(vif_file, level++, "SOPSVID");
+		vif_out_fields(vif_file, level, svid_list->vif_field,
+			       SopSVID_Indexes);
+		vif_output_vif_component_sop_svid_mode_list(vif_file, svid_list,
+							    level);
+		vif_out_end(vif_file, --level, "SOPSVID");
+	}
+	vif_out_end(vif_file, --level, "SOPSVIDList");
 }
 
-static void write_attempts_discov_sop(FILE *vif, enum dtype type)
+static void vif_output_vif_component_snk_pdo_list(
+	FILE *vif_file, const struct vif_Component_t *component, int level)
 {
-	char *yn = "YES";
+	int index;
 
-#ifdef CONFIG_USB_PD_SIMPLE_DFP
-	if (type == SRC)
-		yn = "NO";
-	else
-		yn = "YES";
+	if (!vif_fields_present(component->SnkPdoList[0].vif_field,
+				Snk_PDO_Indexes))
+		return;
+
+	vif_out_comment(vif_file, level, "Bundle: SnkPdoList");
+	vif_out_start(vif_file, level++, "SnkPdoList");
+	for (index = 0; index < MAX_NUM_SNK_PDOS; ++index) {
+		const struct vif_snkPdoList_t *pdo_list =
+			&component->SnkPdoList[index];
+
+		if (!vif_fields_present(pdo_list->vif_field, Snk_PDO_Indexes))
+			break;
+
+		vif_out_start(vif_file, level++, "SnkPDO");
+		vif_out_comment(vif_file, level, "Sink PDO %d", index + 1);
+		vif_out_fields(vif_file, level, pdo_list->vif_field,
+			       Snk_PDO_Indexes);
+		vif_out_end(vif_file, --level, "SnkPDO");
+	}
+	vif_out_end(vif_file, --level, "SnkPdoList");
+}
+
+static void vif_output_vif_component_src_pdo_list(
+	FILE *vif_file, const struct vif_Component_t *component, int level)
+{
+	int index;
+
+	if (!vif_fields_present(component->SrcPdoList[0].vif_field,
+				Src_PDO_Indexes))
+		return;
+
+	vif_out_comment(vif_file, level, "Bundle: SrcPdoList");
+	vif_out_start(vif_file, level++, "SrcPdoList");
+	for (index = 0; index < MAX_NUM_SRC_PDOS; ++index) {
+		const struct vif_srcPdoList_t *pdo_list =
+			&component->SrcPdoList[index];
+
+		if (!vif_fields_present(pdo_list->vif_field, Src_PDO_Indexes))
+			break;
+
+		vif_out_start(vif_file, level++, "SrcPDO");
+		vif_out_comment(vif_file, level, "Source PDO %d", index + 1);
+		vif_out_fields(vif_file, level, pdo_list->vif_field,
+			       Src_PDO_Indexes);
+		vif_out_end(vif_file, --level, "SrcPDO");
+	}
+	vif_out_end(vif_file, --level, "SrcPdoList");
+}
+
+static void vif_output_vif_component(FILE *vif_file, const struct vif_t *vif,
+				     int level)
+{
+	int index;
+
+	for (index = 0; index < MAX_NUM_COMPONENTS; ++index) {
+		const struct vif_Component_t *component =
+			&vif->Component[index];
+
+		if (!vif_fields_present(component->vif_field,
+					Component_Indexes))
+			return;
+
+		vif_out_start(vif_file, level++, "Component");
+		vif_out_comment(vif_file, level, "Component %d", index);
+		vif_out_fields(vif_file, level, component->vif_field,
+			       Component_Indexes);
+		vif_output_vif_component_snk_pdo_list(vif_file, component,
+						      level);
+		vif_output_vif_component_src_pdo_list(vif_file, component,
+						      level);
+		vif_output_vif_component_sop_svid_list(vif_file, component,
+						       level);
+		vif_output_vif_component_cable_svid_list(vif_file, component,
+							 level);
+		vif_out_end(vif_file, --level, "Component");
+	}
+}
+
+static void vif_output_vif_product_usb4router_endpoint(
+	FILE *vif_file, const struct vif_Usb4RouterListType_t *router,
+	int level)
+{
+	int index;
+
+	if (!vif_fields_present(router->PCIeEndpointList[0].vif_field,
+				PCIe_Endpoint_Indexes))
+		return;
+
+	vif_out_start(vif_file, level++, "PCIeEndpointList");
+	for (index = 0; index < MAX_NUM_PCIE_ENDPOINTS; ++index) {
+		const struct vif_PCIeEndpointListType_t *endpont =
+			&router->PCIeEndpointList[index];
+
+		if (!vif_fields_present(endpont->vif_field,
+					PCIe_Endpoint_Indexes))
+			break;
+
+		vif_out_start(vif_file, level++, "PCIeEndpoint");
+		vif_out_fields(vif_file, level, endpont->vif_field,
+			       PCIe_Endpoint_Indexes);
+		vif_out_end(vif_file, --level, "PCIeEndpoint");
+	}
+	vif_out_end(vif_file, --level, "PCIeEndpointList");
+}
+
+static void vif_output_vif_product_usb4router(FILE *vif_file,
+					      const struct vif_t *vif,
+					      int level)
+{
+	int index;
+
+	if (!vif_fields_present(vif->Product.USB4RouterList[0].vif_field,
+				USB4_Router_Indexes))
+		return;
+
+	vif_out_comment(vif_file, level, "Bundle: USB4RouterList");
+	vif_out_start(vif_file, level++, "USB4RouterList");
+	for (index = 0; index < MAX_NUM_USB4_ROUTERS; ++index) {
+		const struct vif_Usb4RouterListType_t *router =
+			&vif->Product.USB4RouterList[index];
+
+		if (!vif_fields_present(router->vif_field, USB4_Router_Indexes))
+			break;
+
+		vif_out_start(vif_file, level++, "Usb4Router");
+		vif_out_comment(vif_file, level, "USB4 Router %d", index);
+		vif_out_fields(vif_file, level, router->vif_field,
+			       USB4_Router_Indexes);
+		vif_output_vif_product_usb4router_endpoint(vif_file, router,
+							   level);
+		vif_out_end(vif_file, --level, "Usb4Router");
+	}
+	vif_out_end(vif_file, --level, "USB4RouterList");
+}
+
+static void vif_output_vif_product(FILE *vif_file, const struct vif_t *vif,
+				   int level)
+{
+	if (!vif_fields_present(vif->Product.vif_field, Product_Indexes))
+		return;
+
+	vif_out_start(vif_file, level++, "Product");
+	vif_out_comment(vif_file, level, "Product Level Content:");
+	vif_out_fields(vif_file, level, vif->Product.vif_field,
+		       Product_Indexes);
+	vif_output_vif_product_usb4router(vif_file, vif, level);
+	vif_out_end(vif_file, --level, "Product");
+}
+
+static void vif_output_vif_xml(FILE *vif_file, struct vif_t *vif, int level)
+{
+	vif_out_field(vif_file, level, &vif->vif_field[VIF_Specification]);
+
+	vif_out_start(vif_file, level++, "VIF_App");
+	vif_out_fields(vif_file, level, vif->vif_app_field, VIF_App_Indexes);
+	vif_out_end(vif_file, --level, "VIF_App");
+
+	vif_out_fields_range(vif_file, level, vif->vif_field, Vendor_Name,
+			     VIF_Indexes);
+}
+
+static int vif_output_xml(const char *name, struct vif_t *vif)
+{
+	int level = 0;
+	FILE *vif_file;
+
+	vif_file = fopen(name, "w+");
+	if (vif_file == NULL) {
+		fprintf(stderr, "Output file '%s' could not be created\n",
+			name);
+		return 1;
+	}
+
+	vif_out_str(vif_file, level,
+		    "<?xml version=\"1.0\" encoding=\"utf-8\"?>");
+	vif_out_start(
+		vif_file, level++,
+		"VIF "
+		"xmlns:opt=\"http://usb.org/VendorInfoFileOptionalContent.xsd\" "
+		"xmlns:xsi=\"http://www.w3.org/2001/XMLSchema-instance\" "
+		"xmlns:vif=\"http://usb.org/VendorInfoFile.xsd\"");
+
+	vif_output_vif_xml(vif_file, vif, level);
+	vif_output_vif_product(vif_file, vif, level);
+	vif_output_vif_component(vif_file, vif, level);
+
+	vif_out_end(vif_file, --level, "VIF");
+
+	fclose(vif_file);
+	return 0;
+}
+/*
+ * VIF XML Output Functions
+ *****************************************************************************/
+
+/*****************************************************************************
+ * VIF Structure Override from XML file functions
+ */
+FILE *override_file;
+
+int pushback_cnt;
+char pushback_stack[20];
+
+static bool ov_open(const char *over_name)
+{
+	override_file = fopen(over_name, "r");
+
+	pushback_cnt = 0;
+	return override_file != NULL;
+}
+static int ov_getc(void)
+{
+	if (!override_file)
+		return EOF;
+
+	if (pushback_cnt > 0)
+		return pushback_stack[--pushback_cnt];
+	return getc(override_file);
+}
+static void ovpre_getc(int cnt)
+{
+	if (pushback_cnt < cnt) {
+		int new_pushback_cnt = cnt;
+
+		while (cnt > 0)
+			pushback_stack[--cnt] = ov_getc();
+		pushback_cnt = new_pushback_cnt;
+	}
+}
+static void ovpre_drop(int cnt)
+{
+	pushback_cnt -= cnt;
+	if (pushback_cnt < 0)
+		pushback_cnt = 0;
+}
+static int ovpre_peek(int index)
+{
+	return pushback_stack[pushback_cnt - index - 1];
+}
+static void ov_pushback(int ch)
+{
+	pushback_stack[pushback_cnt++] = ch;
+}
+static void ov_close(void)
+{
+	if (override_file)
+		fclose(override_file);
+
+	pushback_cnt = 0;
+	override_file = NULL;
+}
+
+static void set_override_vif_field(struct vif_field_t *vif_field,
+				   const char *name, const char *tag_value,
+				   const char *str_value)
+{
+	char *ptr;
+
+	if (vif_field->str_value) {
+		free(vif_field->str_value);
+		vif_field->str_value = NULL;
+	}
+	if (vif_field->tag_value) {
+		free(vif_field->tag_value);
+		vif_field->tag_value = NULL;
+	}
+
+	vif_field->name = name;
+	if (tag_value && tag_value[0]) {
+		ptr = malloc(strlen(tag_value) + 1);
+		strcpy(ptr, tag_value);
+		vif_field->tag_value = ptr;
+	}
+	if (str_value && str_value[0]) {
+		ptr = malloc(strlen(str_value) + 1);
+		strcpy(ptr, str_value);
+		vif_field->str_value = ptr;
+	}
+}
+
+static void ignore_xml_version_tag(void)
+{
+	int ch;
+
+	while ((ch = ov_getc()) != EOF) {
+		if (ch == '?') {
+			ch = ov_getc();
+			if (ch == '>')
+				break;
+			ov_pushback(ch);
+		}
+	}
+}
+static void ignore_comment_tag(void)
+{
+	int ch;
+
+	while ((ch = ov_getc()) != EOF) {
+		if (ch == '-') {
+			ovpre_getc(2);
+			if (ovpre_peek(0) == '-' && ovpre_peek(1) == '>') {
+				/* --> */
+				ovpre_drop(2);
+				break;
+			}
+		}
+	}
+}
+static void ignore_white_space(void)
+{
+	int ch;
+
+	while ((ch = ov_getc()) != EOF) {
+		if (!isspace(ch)) {
+			ov_pushback(ch);
+			break;
+		}
+	}
+}
+static void ignore_to_end_tag(void)
+{
+	int ch;
+
+	while ((ch = ov_getc()) != EOF) {
+		if (ch == '>')
+			break;
+	}
+}
+
+/*
+ * get_next_tag() consumes the entire element when there
+ * is no nested tag. there is no way to know if the end
+ * tag has been consumed:
+ *
+ * <tag></tag>                       next call returns </end>
+ * </end>
+ *
+ * <tag><nested value=x /></tag>     next call returns <nested>
+ */
+static bool get_next_tag(char *name, char *tag_value, char *str_value)
+{
+	int ch;
+	int name_index = 0;
+	int tag_index = 0;
+	int str_index = 0;
+
+	name[0] = '\0';
+	tag_value[0] = '\0';
+	str_value[0] = '\0';
+
+	/*
+	 * Ignore <? .... ?>
+	 * Ignore <!-- ... -->
+	 * Find tags <X/>, <X> and </X>
+	 */
+	while ((ch = ov_getc()) != EOF) {
+		if (ch == '<') {
+			/*
+			 * Ignore XML version <? ... ?>
+			 */
+			ovpre_getc(1);
+			if (ovpre_peek(0) == '?') {
+				ovpre_drop(1);
+				ignore_xml_version_tag();
+				continue;
+			}
+
+			/*
+			 * Ignore XML comment <!-- ... -->
+			 */
+			ovpre_getc(3);
+			if (ovpre_peek(0) == '!' && ovpre_peek(1) == '-' &&
+			    ovpre_peek(2) == '-') {
+				ovpre_drop(3);
+				ignore_comment_tag();
+				continue;
+			}
+
+			/* Looking for terminating tag */
+			ovpre_getc(1);
+			if (ovpre_peek(0) == '/') {
+				while ((ch = ov_getc()) != EOF) {
+					if (ch == '>')
+						break;
+					name[name_index++] = ch;
+				}
+				name[name_index] = '\0';
+				return true;
+			}
+
+			/* Looking for a tag name */
+			while ((ch = ov_getc()) != EOF) {
+				if (ch == '_' || ch == ':' || isalpha(ch) ||
+				    isdigit(ch)) {
+					name[name_index++] = ch;
+				} else {
+					ov_pushback(ch);
+					break;
+				}
+			}
+			name[name_index] = '\0';
+
+			/* Consume any whitespace */
+			ignore_white_space();
+
+			/* See if there is a tag_string value */
+			ovpre_getc(7);
+			if (ovpre_peek(0) == 'v' && ovpre_peek(1) == 'a' &&
+			    ovpre_peek(2) == 'l' && ovpre_peek(3) == 'u' &&
+			    ovpre_peek(4) == 'e' && ovpre_peek(5) == '=' &&
+			    ovpre_peek(6) == '"') {
+				ovpre_drop(7);
+				while ((ch = ov_getc()) != EOF) {
+					if (ch == '"')
+						break;
+					tag_value[tag_index++] = ch;
+				}
+				tag_value[tag_index] = '\0';
+			}
+
+			/* Consume any whitespace */
+			ignore_white_space();
+
+			/* /> ending the tag will conclude this tag */
+			ovpre_getc(2);
+			if (ovpre_peek(0) == '/' && ovpre_peek(1) == '>') {
+				ovpre_drop(2);
+				return true;
+			}
+			if (ovpre_peek(0) == '>') {
+				ovpre_drop(1);
+				while ((ch = ov_getc()) != EOF) {
+					if (ch == '<') {
+						ov_pushback(ch);
+						break;
+					}
+					str_value[str_index++] = ch;
+				}
+				str_value[str_index] = '\0';
+
+				ovpre_getc(2);
+				if (ovpre_peek(0) == '<' &&
+				    ovpre_peek(1) == '/') {
+					ovpre_drop(2);
+					ignore_to_end_tag();
+				}
+			}
+			return true;
+		}
+	}
+	return false;
+}
+
+static void override_vif_product_pcie_endpoint_field(
+	struct vif_PCIeEndpointListType_t *endpoint)
+{
+	char name[80];
+	char tag_value[80];
+	char str_value[80];
+
+	while (get_next_tag(name, tag_value, str_value)) {
+		int i;
+
+		if (is_end_tag(name, "PCIeEndpoint"))
+			break;
+
+		for (i = 0; i < PCIe_Endpoint_Indexes; i++)
+			if (streq(name, vif_product_pcie_endpoint_name[i]))
+				break;
+		if (i != PCIe_Endpoint_Indexes)
+			set_override_vif_field(
+				&endpoint->vif_field[i],
+				vif_product_pcie_endpoint_name[i], tag_value,
+				str_value);
+		else
+			fprintf(stderr,
+				"VIF/Component/Usb4Router/PCIeEndpoint:"
+				" Unknown tag '%s'\n",
+				name);
+	}
+}
+static void override_vif_product_pcie_endpoint_list_field(
+	struct vif_PCIeEndpointListType_t *endpoint_list)
+{
+	char name[80];
+	char tag_value[80];
+	char str_value[80];
+	int endpoint_index = 0;
+
+	while (get_next_tag(name, tag_value, str_value)) {
+		if (is_end_tag(name, "PCIeEndpointList"))
+			break;
+
+		if (is_start_tag(name, "PCIeEndpoint"))
+			override_vif_product_pcie_endpoint_field(
+				&endpoint_list[endpoint_index++]);
+		else
+			fprintf(stderr,
+				"VIF/Product/Usb4Router/PCIeEndpointList:"
+				" Unknown tag '%s'\n",
+				name);
+	}
+}
+
+static void
+override_vif_product_usb4router_fields(struct vif_Usb4RouterListType_t *router)
+{
+	char name[80];
+	char tag_value[80];
+	char str_value[80];
+	int endpoint_index = 0;
+
+	while (get_next_tag(name, tag_value, str_value)) {
+		if (is_end_tag(name, "Usb4Router"))
+			break;
+
+		if (is_start_tag(name, "PCIeEndpointList"))
+			override_vif_product_pcie_endpoint_list_field(
+				&router->PCIeEndpointList[endpoint_index++]);
+		else {
+			int i;
+
+			for (i = 0; i < USB4_Router_Indexes; i++)
+				if (streq(name,
+					  vif_product_usb4_router_name[i]))
+					break;
+			if (i != USB4_Router_Indexes)
+				set_override_vif_field(
+					&router->vif_field[i],
+					vif_product_usb4_router_name[i],
+					tag_value, str_value);
+			else
+				fprintf(stderr,
+					"VIF/Component/Usb4Router:"
+					" Unknown tag '%s'\n",
+					name);
+		}
+	}
+}
+static void override_vif_product_usb4routerlist_fields(
+	struct vif_Usb4RouterListType_t *router_list)
+{
+	char name[80];
+	char tag_value[80];
+	char str_value[80];
+	int router_index = 0;
+
+	while (get_next_tag(name, tag_value, str_value)) {
+		if (is_end_tag(name, "USB4RouterList"))
+			break;
+
+		if (is_start_tag(name, "Usb4Router"))
+			override_vif_product_usb4router_fields(
+				&router_list[router_index++]);
+		else
+			fprintf(stderr,
+				"VIF/Product/USB4RouterList:"
+				" Unknown tag '%s'\n",
+				name);
+	}
+}
+
+static void override_vif_product_fields(struct vif_Product_t *vif_product)
+{
+	char name[80];
+	char tag_value[80];
+	char str_value[80];
+
+	set_vif_field_c(&vif_product->vif_field[USB4_Product_Header],
+			"USB4\u2122 Product");
+
+	while (get_next_tag(name, tag_value, str_value)) {
+		if (is_end_tag(name, "Product"))
+			break;
+
+		if (is_start_tag(name, "USB4RouterList"))
+			override_vif_product_usb4routerlist_fields(
+				vif_product->USB4RouterList);
+		else {
+			int i;
+
+			for (i = 0; i < Product_Indexes; i++)
+				if (streq(name, vif_product_name[i]))
+					break;
+			if (i != Product_Indexes)
+				set_override_vif_field(
+					&vif_product->vif_field[i],
+					vif_product_name[i], tag_value,
+					str_value);
+			else
+				fprintf(stderr,
+					"VIF/Product:"
+					" Unknown tag '%s'\n",
+					name);
+		}
+	}
+}
+
+static void
+override_vif_component_src_pdo_fields(struct vif_srcPdoList_t *vif_src_pdo)
+{
+	char name[80];
+	char tag_value[80];
+	char str_value[80];
+
+	while (get_next_tag(name, tag_value, str_value)) {
+		int i;
+
+		if (is_end_tag(name, "SrcPdo"))
+			break;
+
+		for (i = 0; i < Src_PDO_Indexes; i++)
+			if (streq(name, vif_component_src_pdo_name[i]))
+				break;
+		if (i != Src_PDO_Indexes)
+			set_override_vif_field(&vif_src_pdo->vif_field[i],
+					       vif_component_src_pdo_name[i],
+					       tag_value, str_value);
+		else
+			fprintf(stderr,
+				"VIF/Component/SrcPdo:"
+				" Unknown tag '%s'\n",
+				name);
+	}
+}
+static void override_vif_component_src_pdo_list_fields(
+	struct vif_srcPdoList_t *vif_src_pdo_list)
+{
+	char name[80];
+	char tag_value[80];
+	char str_value[80];
+	int src_pdo_index = 0;
+
+	while (get_next_tag(name, tag_value, str_value)) {
+		if (is_end_tag(name, "SrcPdoList"))
+			break;
+
+		if (is_start_tag(name, "SrcPdo"))
+			override_vif_component_src_pdo_fields(
+				&vif_src_pdo_list[src_pdo_index++]);
+		else
+			fprintf(stderr,
+				"VIF/Component/SrcPdoList:"
+				" Unknown tag '%s'\n",
+				name);
+	}
+}
+
+static void
+override_vif_component_snk_pdo_fields(struct vif_snkPdoList_t *vif_snk_pdo)
+{
+	char name[80];
+	char tag_value[80];
+	char str_value[80];
+
+	while (get_next_tag(name, tag_value, str_value)) {
+		int i;
+
+		if (is_end_tag(name, "SnkPdo"))
+			break;
+
+		for (i = 0; i < Snk_PDO_Indexes; i++)
+			if (streq(name, vif_component_snk_pdo_name[i]))
+				break;
+		if (i != Snk_PDO_Indexes)
+			set_override_vif_field(&vif_snk_pdo->vif_field[i],
+					       vif_component_snk_pdo_name[i],
+					       tag_value, str_value);
+		else
+			fprintf(stderr,
+				"VIF/Component/SnkPdo:"
+				" Unknown tag '%s'\n",
+				name);
+	}
+}
+static void override_vif_component_snk_pdo_list_fields(
+	struct vif_snkPdoList_t *vif_snk_pdo_list)
+{
+	char name[80];
+	char tag_value[80];
+	char str_value[80];
+	int snk_pdo_index = 0;
+
+	while (get_next_tag(name, tag_value, str_value)) {
+		if (is_end_tag(name, "SnkPdoList"))
+			break;
+
+		if (is_start_tag(name, "SnkPdo"))
+			override_vif_component_snk_pdo_fields(
+				&vif_snk_pdo_list[snk_pdo_index++]);
+		else
+			fprintf(stderr,
+				"VIF/Component/SnkPdoList:"
+				" Unknown tag '%s'\n",
+				name);
+	}
+}
+
+static void override_vif_component_sop_svid_mode_fields(
+	struct vif_sopSVIDModeList_t *svid_mode)
+{
+	char name[80];
+	char tag_value[80];
+	char str_value[80];
+
+	while (get_next_tag(name, tag_value, str_value)) {
+		int i;
+
+		if (is_end_tag(name, "SOPSVIDMode"))
+			break;
+
+		for (i = 0; i < SopSVID_Indexes; i++)
+			if (streq(name, vif_component_sop_svid_mode_name[i]))
+				break;
+		if (i != SopSVID_Indexes)
+			set_override_vif_field(
+				&svid_mode->vif_field[i],
+				vif_component_sop_svid_mode_name[i], tag_value,
+				str_value);
+		else
+			fprintf(stderr,
+				"VIF/Component/SOPSVIDMode:"
+				" Unknown tag '%s'\n",
+				name);
+	}
+}
+static void override_vif_component_sop_svid_mode_list_fields(
+	struct vif_sopSVIDModeList_t *svid_mode_list)
+{
+	char name[80];
+	char tag_value[80];
+	char str_value[80];
+	int mode_index = 0;
+
+	while (get_next_tag(name, tag_value, str_value)) {
+		if (is_end_tag(name, "SOPSVIDModeList"))
+			break;
+
+		if (is_start_tag(name, "SOPSVIDMode"))
+			override_vif_component_sop_svid_mode_fields(
+				&svid_mode_list[mode_index++]);
+		else
+			fprintf(stderr,
+				"VIF/Component/SOPSVIDModeList:"
+				" Unknown tag '%s'\n",
+				name);
+	}
+}
+
+static void
+override_vif_component_sop_svid_fields(struct vif_sopSVIDList_t *vif_sop_svid)
+{
+	char name[80];
+	char tag_value[80];
+	char str_value[80];
+
+	while (get_next_tag(name, tag_value, str_value)) {
+		if (is_end_tag(name, "SOPSVID"))
+			break;
+
+		if (is_start_tag(name, "SOPSVIDModeList"))
+			override_vif_component_sop_svid_mode_list_fields(
+				vif_sop_svid->SOPSVIDModeList);
+		else {
+			int i;
+
+			for (i = 0; i < SopSVID_Indexes; i++)
+				if (streq(name, vif_component_sop_svid_name[i]))
+					break;
+			if (i != SopSVID_Indexes)
+				set_override_vif_field(
+					&vif_sop_svid->vif_field[i],
+					vif_component_sop_svid_name[i],
+					tag_value, str_value);
+			else
+				fprintf(stderr,
+					"VIF/Component/SOPSVID:"
+					" Unknown tag '%s'\n",
+					name);
+		}
+	}
+}
+static void override_vif_component_sop_svid_list_fields(
+	struct vif_sopSVIDList_t *vif_sop_svid_list)
+{
+	char name[80];
+	char tag_value[80];
+	char str_value[80];
+	int sop_svid_index = 0;
+
+	while (get_next_tag(name, tag_value, str_value)) {
+		if (is_end_tag(name, "SOPSVIDList"))
+			break;
+
+		if (is_start_tag(name, "SOPSVID"))
+			override_vif_component_sop_svid_fields(
+				&vif_sop_svid_list[sop_svid_index++]);
+		else
+			fprintf(stderr,
+				"VIF/Component/SOPSVIDList:"
+				" Unknown tag '%s'\n",
+				name);
+	}
+}
+
+static void override_vif_component_cable_svid_mode_fields(
+	struct vif_cableSVIDModeList_t *vif_cable_mode)
+{
+	char name[80];
+	char tag_value[80];
+	char str_value[80];
+
+	while (get_next_tag(name, tag_value, str_value)) {
+		int i;
+
+		if (is_end_tag(name, "CableSVIDMode"))
+			break;
+
+		for (i = 0; i < CableSVID_Mode_Indexes; i++)
+			if (streq(name, vif_cable_mode_name[i]))
+				break;
+		if (i != CableSVID_Mode_Indexes)
+			set_override_vif_field(&vif_cable_mode->vif_field[i],
+					       vif_cable_mode_name[i],
+					       tag_value, str_value);
+		else
+			fprintf(stderr,
+				"VIF/Component/CableSVIDMode:"
+				" Unknown tag '%s'\n",
+				name);
+	}
+}
+static void override_vif_component_cable_svid_mode_list_fields(
+	struct vif_cableSVIDModeList_t *vif_cable_mode_list)
+{
+	char name[80];
+	char tag_value[80];
+	char str_value[80];
+	int mode_index = 0;
+
+	while (get_next_tag(name, tag_value, str_value)) {
+		if (is_end_tag(name, "CableSVIDModeList"))
+			break;
+
+		if (is_start_tag(name, "CableSVIDMode"))
+			override_vif_component_cable_svid_mode_fields(
+				&vif_cable_mode_list[mode_index++]);
+		else
+			fprintf(stderr,
+				"VIF/Component/CableSVIDModeList:"
+				" Unknown tag '%s'\n",
+				name);
+	}
+}
+
+static void override_vif_component_cable_svid_fields(
+	struct vif_cableSVIDList_t *vif_cable_svid)
+{
+	char name[80];
+	char tag_value[80];
+	char str_value[80];
+	int mode_index = 0;
+
+	while (get_next_tag(name, tag_value, str_value)) {
+		if (is_end_tag(name, "CableSVID"))
+			break;
+
+		if (is_start_tag(name, "CableSVIDModeList"))
+			override_vif_component_cable_svid_mode_list_fields(
+				&vif_cable_svid
+					 ->CableSVIDModeList[mode_index++]);
+		else {
+			int i;
+
+			for (i = 0; i < CableSVID_Indexes; i++)
+				if (streq(name, vif_cable_svid_name[i]))
+					break;
+			if (i != CableSVID_Indexes)
+				set_override_vif_field(
+					&vif_cable_svid->vif_field[i],
+					vif_cable_svid_name[i], tag_value,
+					str_value);
+			else
+				fprintf(stderr,
+					"VIF/Component/CableSVID:"
+					" Unknown tag '%s'\n",
+					name);
+		}
+	}
+}
+static void override_vif_component_cable_svid_list_fields(
+	struct vif_cableSVIDList_t *vif_cable_svid_list)
+{
+	char name[80];
+	char tag_value[80];
+	char str_value[80];
+	int cable_svid_index = 0;
+
+	while (get_next_tag(name, tag_value, str_value)) {
+		if (is_end_tag(name, "CableSVIDList"))
+			break;
+
+		if (is_start_tag(name, "CableSVID"))
+			override_vif_component_cable_svid_fields(
+				&vif_cable_svid_list[cable_svid_index++]);
+		else
+			fprintf(stderr,
+				"VIF/Component/CableSVIDList:"
+				" Unknown tag '%s'\n",
+				name);
+	}
+}
+
+static void override_vif_component_fields(struct vif_Component_t *vif_component)
+{
+	char name[80];
+	char tag_value[80];
+	char str_value[80];
+
+	while (get_next_tag(name, tag_value, str_value)) {
+		if (is_end_tag(name, "Component"))
+			break;
+
+		if (is_start_tag(name, "SrcPdoList"))
+			override_vif_component_src_pdo_list_fields(
+				vif_component->SrcPdoList);
+		else if (is_start_tag(name, "SnkPdoList"))
+			override_vif_component_snk_pdo_list_fields(
+				vif_component->SnkPdoList);
+		else if (is_start_tag(name, "SOPSVIDList"))
+			override_vif_component_sop_svid_list_fields(
+				vif_component->SOPSVIDList);
+		else if (is_start_tag(name, "CableSVIDList"))
+			override_vif_component_cable_svid_list_fields(
+				vif_component->CableSVIDList);
+		else {
+			int i;
+
+			for (i = 0; i < Component_Indexes; i++)
+				if (streq(name, vif_component_name[i]))
+					break;
+			if (i != Component_Indexes)
+				set_override_vif_field(
+					&vif_component->vif_field[i],
+					vif_component_name[i], tag_value,
+					str_value);
+			else
+				fprintf(stderr,
+					"VIF/Component:"
+					" Unknown tag '%s'\n",
+					name);
+		}
+	}
+}
+
+static void override_vif_app_fields(struct vif_t *vif)
+{
+	char name[80];
+	char tag_value[80];
+	char str_value[80];
+
+	while (get_next_tag(name, tag_value, str_value)) {
+		int i;
+
+		if (is_end_tag(name, "VIF_App"))
+			break;
+
+		for (i = 0; i < VIF_App_Indexes; i++)
+			if (streq(name, vif_app_name[i]))
+				break;
+		if (i == VIF_App_Indexes)
+			fprintf(stderr,
+				"VIF/VIF_App:"
+				" Unknown tag '%s'\n",
+				name);
+	}
+}
+
+static void override_vif_fields(struct vif_t *vif)
+{
+	char name[80];
+	char tag_value[80];
+	char str_value[80];
+
+	component_index = 0;
+	while (get_next_tag(name, tag_value, str_value)) {
+		if (is_end_tag(name, "VIF"))
+			break;
+
+		if (is_start_tag(name, "VIF_App"))
+			override_vif_app_fields(vif);
+		else if (is_start_tag(name, "Component"))
+			override_vif_component_fields(
+				&vif->Component[component_index++]);
+		else if (is_start_tag(name, "Product"))
+			override_vif_product_fields(&vif->Product);
+		else {
+			int i;
+
+			for (i = 0; i < VIF_Indexes; i++)
+				if (streq(name, vif_name[i]))
+					break;
+			if (i != VIF_Indexes)
+				set_override_vif_field(&vif->vif_field[i],
+						       vif_name[i], tag_value,
+						       str_value);
+			else
+				fprintf(stderr,
+					"VIF:"
+					" Unknown tag '%s'\n",
+					name);
+		}
+	}
+
+	/*
+	 * Don't care what they requested, I am making the file and that
+	 * means VIF/VIF_App is to be set by me.
+	 */
+	set_override_vif_field(&vif->vif_app_field[Vendor],
+			       vif_app_name[Vendor], NULL,
+			       VIF_APP_VENDOR_VALUE);
+
+	set_override_vif_field(&vif->vif_app_field[Name], vif_app_name[Name],
+			       NULL, VIF_APP_NAME_VALUE);
+
+	set_override_vif_field(&vif->vif_app_field[Version],
+			       vif_app_name[Version], NULL,
+			       VIF_APP_VERSION_VALUE);
+}
+
+static int override_gen_vif(char *over_name, struct vif_t *vif)
+{
+	char name[80];
+	char tag_value[80];
+	char str_value[80];
+
+	if (!ov_open(over_name)) {
+		fprintf(stderr, "Override file '%s' could not be opened\n",
+			over_name);
+		return 1;
+	}
+
+	while (get_next_tag(name, tag_value, str_value)) {
+		if (is_start_tag(name, "VIF"))
+			override_vif_fields(vif);
+		else
+			fprintf(stderr, "Unknown tag '%s'\n", name);
+	}
+
+	ov_close();
+	return 0;
+}
+/*
+ * VIF Structure Override from XML file functions
+ *****************************************************************************/
+
+/*****************************************************************************
+ * VIF Structure Initialization Helper Functions
+ */
+static void set_vif_field(struct vif_field_t *vif_field, const char *name,
+			  const char *tag_value, const char *str_value)
+{
+	char *ptr;
+
+	/*
+	 * Override already set or trying to set to nothing should do
+	 * nothing. Just return
+	 */
+	if ((vif_field->name || vif_field->str_value || vif_field->tag_value) ||
+	    (str_value == NULL && tag_value == NULL))
+		return;
+
+	vif_field->name = name;
+	if (tag_value) {
+		ptr = malloc(strlen(tag_value) + 1);
+		strcpy(ptr, tag_value);
+		vif_field->tag_value = ptr;
+	}
+	if (str_value) {
+		ptr = malloc(strlen(str_value) + 1);
+		strcpy(ptr, str_value);
+		vif_field->str_value = ptr;
+	}
+}
+__maybe_unused static void set_vif_field_b(struct vif_field_t *vif_field,
+					   const char *name, const bool val)
+{
+	if (val)
+		set_vif_field(vif_field, name, "true", NULL);
+	else
+		set_vif_field(vif_field, name, "false", NULL);
+}
+__maybe_unused static void set_vif_field_stis(struct vif_field_t *vif_field,
+					      const char *name,
+					      const char *tag_value,
+					      const int str_value)
+{
+	char str_str[20];
+
+	sprintf(str_str, "%d", str_value);
+	set_vif_field(vif_field, name, tag_value, str_str);
+}
+__maybe_unused static void set_vif_field_itss(struct vif_field_t *vif_field,
+					      const char *name,
+					      const int tag_value,
+					      const char *str_value)
+{
+	char str_tag[20];
+
+	sprintf(str_tag, "%d", tag_value);
+	set_vif_field(vif_field, name, str_tag, str_value);
+}
+__maybe_unused static void set_vif_field_itis(struct vif_field_t *vif_field,
+					      const char *name,
+					      const int tag_value,
+					      const int str_value)
+{
+	char str_tag[20];
+	char str_str[20];
+
+	sprintf(str_tag, "%d", tag_value);
+	sprintf(str_str, "%d", str_value);
+	set_vif_field(vif_field, name, str_tag, str_str);
+}
+
+static void set_vif_field_c(struct vif_field_t *vif_field, const char *comment)
+{
+	set_vif_field(vif_field, NULL, comment, NULL);
+}
+
+/*
+ * VIF Structure Initialization Helper Functions
+ *****************************************************************************/
+
+/*****************************************************************************
+ * VIF Structure Initialization from Config Functions
+ */
+/*
+ * TODO: Generic todo to fill in additional fields as the need presents
+ * itself
+ *
+ * Fields that are not currently being initialized
+ *
+ * vif_Component USB4 Port Fields
+ *	USB4_Lane_0_Adapter			numericFieldType
+ *	USB4_DFP_Supported			booleanFieldType
+ *	USB4_UFP_Supported			booleanFieldType
+ *	USB4_USB3_Tunneling_Supported		booleanFieldType
+ *	USB4_DP_Tunneling_Supported		booleanFieldType
+ *	USB4_CL1_State_Supported		booleanFieldType
+ *	USB4_CL2_State_Supported		booleanFieldType
+ *	USB4_Num_Retimers			numericFieldType
+ *	USB4_DP_Bit_Rate			numericFieldType
+ *	USB4_Num_DP_Lanes			numericFieldType
+ *
+ * vif_Component USB4 Product Fields
+ *	USB4_Dock				booleanFieldType
+ *	USB4_Num_Internal_Host_Controllers	numericFieldType
+ *	USB4_Num_PCIe_DN_Bridges		numericFieldType
+ *	USB4_Device_HiFi_Bi_TMU_Mode_Required	booleanFieldType
+ *
+ * vif_Component USB4 Device Class Fallback Support
+ *	USB4_Audio_Supported			booleanFieldType
+ *	USB4_HID_Supported			booleanFieldType
+ *	USB4_Printer_Supported			booleanFieldType
+ *	USB4_Mass_Storage_Supported		booleanFieldType
+ *	USB4_Video_Supported			booleanFieldType
+ *	USB4_Comms_Networking_Supported		booleanFieldType
+ *	USB4_Media_Transfer_Protocol_Supported	booleanFieldType
+ *	USB4_Smart_Card_Supported		booleanFieldType
+ *	USB4_Still_Image_Capture_Supported	booleanFieldType
+ *	USB4_Monitor_Device_Supported		booleanFieldType
+ *
+ * vif_Usb4RouterListType USB4 Router Fields
+ *	USB4_Router_ID				numericFieldType
+ *	USB4_Silicon_VID			numericFieldType
+ *	USB4_Num_Lane_Adapters			numericFieldType
+ *	USB4_Num_USB3_DN_Adapters		numericFieldType
+ *	USB4_Num_DP_IN_Adapters			numericFieldType
+ *	USB4_Num_DP_OUT_Adapters		numericFieldType
+ *	USB4_Num_PCIe_DN_Adapters		numericFieldType
+ *	USB4_TBT3_Not_Supported			numericFieldType
+ *	USB4_PCIe_Wake_Supported		booleanFieldType
+ *	USB4_USB3_Wake_Supported		booleanFieldType
+ *	USB4_Num_Unused_Adapters		numericFieldType
+ *	USB4_TBT3_VID				numericFieldType
+ *	USB4_PCIe_Switch_Vendor_ID		numericFieldType
+ *	USB4_PCIe_Switch_Device_ID		numericFieldType
+ *	USB4_Num_PCIe_Endpoints			numericFieldType
+ *
+ * vif_PCIeEndpointListType PCIe Endpoint Fields
+ *	USB4_PCIe_Endpoint_Vendor_ID		numericFieldType
+ *	USB4_PCIe_Endpoint_Device_ID		numericFieldType
+ *	USB4_PCIe_Endpoint_Class_Code		numericFieldType
+ *
+ * vif_sopSVIDList SOP SVIDs
+ *	SVID_SOP				numericFieldType
+ *	SVID_Modes_Fixed_SOP			booleanFieldType
+ *	SVID_Num_Modes_Min_SOP			numericFieldType
+ *	SVID_Num_Modes_Max_SOP			numericFieldType
+ *
+ * vif_sopSVIDModeList SOP SVID Modes
+ *	SVID_Mode_Enter_SOP			booleanFieldType
+ *	SVID_Mode_Recog_Mask_SOP		numericFieldType
+ *	SVID_Mode_Recog_Value_SOP		numericFieldType
+ *
+ * vif_Component Alternate Mode Adapter Fields
+ *	AMA_HW_Vers				numericFieldType
+ *	AMA_FW_Vers				numericFieldType
+ *	AMA_VCONN_Power				booleanFieldType
+ *	AMA_VCONN_Reqd				booleanFieldType
+ *	AMA_VBUS_Reqd				booleanFieldType
+ *	AMA_Superspeed_Support			numericFieldType
+ *
+ * vif_Component Cable/eMarker Fields
+ *	XID					numericFieldType
+ *	Data_Capable_As_USB_Host		booleanFieldType
+ *	Data_Capable_As_USB_Device		booleanFieldType
+ *	Product_Type				numericFieldType
+ *	Modal_Operation_Supported		booleanFieldType
+ *	USB_VID					numericFieldType
+ *	PID					numericFieldType
+ *	bcdDevice				numericFieldType
+ *	Cable_HW_Vers				numericFieldType
+ *	Cable_FW_Vers				numericFieldType
+ *	Type_C_To_Type_A_B_C			numericFieldType
+ *	Type_C_To_Type_C_Capt_Vdm_V2		numericFieldType
+ *	Cable_Latency				numericFieldType
+ *	Cable_Termination_Type			numericFieldType
+ *	Cable_VBUS_Current			numericFieldType
+ *	VBUS_Through_Cable			booleanFieldType
+ *	Cable_Superspeed_Support		numericFieldType
+ *	Cable_USB_Highest_Speed			numericFieldType
+ *	Max_VBUS_Voltage_Vdm_V2			numericFieldType
+ *	Manufacturer_Info_Supported,		booleanFieldType
+ *	Manufacturer_Info_VID,			numericFieldType
+ *	Manufacturer_Info_PID,			numericFieldType
+ *	Chunking_Implemented			booleanFieldType
+ *	Security_Msgs_Supported			booleanFieldType
+ *	ID_Header_Connector_Type		numericFieldType
+ *	Cable_Num_SVIDs_Min			numericFieldType
+ *	Cable_Num_SVIDs_Max			numericFieldType
+ *	SVID_Fixed				booleanFieldType
+ *
+ * vif_cableSVIDList Cable SVIDs
+ *	SVID					numericFieldType
+ *	SVID_Modes_Fixed			booleanFieldType
+ *	SVID_Num_Modes_Min			numericFieldType
+ *	SVID_Num_Modes_Max			numericFieldType
+ *
+ * vif_cableSVIDModeList Cable SVID Modes
+ *	SVID_Mode_Enter				booleanFieldType
+ *	SVID_Mode_Recog_Mask			numericFieldType
+ *	SVID_Mode_Recog_Value			numericFieldType
+ *
+ * vif_Component Active Cable Fields
+ *	Cable_SOP_PP_Controller			booleanFieldType
+ *	SBU_Supported				booleanFieldType
+ *	SBU_Type				numericFieldType
+ *	Active_Cable_Operating_Temp_Support	booleanFieldType
+ *	Active_Cable_Max_Operating_Temp		numericFieldType
+ *	Active_Cable_Shutdown_Temp_Support	booleanFieldType
+ *	Active_Cable_Shutdown_Temp		numericFieldType
+ *	Active_Cable_U3_CLd_Power		numericFieldType
+ *	Active_Cable_U3_U0_Trans_Mode		numericFieldType
+ *	Active_Cable_Physical_Connection	numericFieldType
+ *	Active_Cable_Active_Element		numericFieldType
+ *	Active_Cable_USB4_Support		booleanFieldType
+ *	Active_Cable_USB2_Supported		booleanFieldType
+ *	Active_Cable_USB2_Hub_Hops_Consumed	numericFieldType
+ *	Active_Cable_USB32_Supported		booleanFieldType
+ *	Active_Cable_USB_Lanes			numericFieldType
+ *	Active_Cable_Optically_Isolated		booleanFieldType
+ *	Active_Cable_USB_Gen			numericFieldType
+ *
+ * vif_Component VCONN Powered Device
+ *	VPD_HW_Vers				numericFieldType
+ *	VPD_FW_Vers				numericFieldType
+ *	VPD_Max_VBUS_Voltage			numericFieldType
+ *	VPD_Charge_Through_Support		booleanFieldType
+ *	VPD_Charge_Through_Current		numericFieldType
+ *	VPD_VBUS_Impedance			numericFieldType
+ *	VPD_Ground_Impedance			numericFieldType
+ *
+ * vif_Component Repeater Fields
+ *	Repeater_One_Type			numericFieldType
+ *	Repeater_Two_Type			numericFieldType
+ */
+
+__maybe_unused static int32_t init_vif_snk_pdo(struct vif_snkPdoList_t *snkPdo,
+					       uint32_t pdo)
+{
+	int32_t power_mw;
+	char str[40];
+
+	/*********************************************************************
+	 * Sink PDOs
+	 */
+	if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_FIXED) {
+		uint32_t current = pdo & 0x3ff;
+		uint32_t current_ma = current * 10;
+		uint32_t voltage = (pdo >> 10) & 0x3ff;
+		uint32_t voltage_mv = voltage * 50;
+
+		power_mw = (current_ma * voltage_mv) / 1000;
+
+		set_vif_field(&snkPdo->vif_field[Snk_PDO_Supply_Type],
+			      vif_component_snk_pdo_name[Snk_PDO_Supply_Type],
+			      "0", "Fixed");
+		sprintf(str, "%d mV", voltage_mv);
+		set_vif_field_itss(&snkPdo->vif_field[Snk_PDO_Voltage],
+				   vif_component_snk_pdo_name[Snk_PDO_Voltage],
+				   voltage, str);
+		sprintf(str, "%d mA", current_ma);
+		set_vif_field_itss(
+			&snkPdo->vif_field[Snk_PDO_Op_Current],
+			vif_component_snk_pdo_name[Snk_PDO_Op_Current], current,
+			str);
+
+	} else if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_BATTERY) {
+		uint32_t max_voltage = (pdo >> 20) & 0x3ff;
+		uint32_t max_voltage_mv = max_voltage * 50;
+		uint32_t min_voltage = (pdo >> 10) & 0x3ff;
+		uint32_t min_voltage_mv = min_voltage * 50;
+		int32_t power;
+
+		power = pdo & 0x3ff;
+		power_mw = power * 250;
+
+		set_vif_field(&snkPdo->vif_field[Snk_PDO_Supply_Type],
+			      vif_component_snk_pdo_name[Snk_PDO_Supply_Type],
+			      "1", "Battery");
+		sprintf(str, "%d mV", min_voltage_mv);
+		set_vif_field_itss(
+			&snkPdo->vif_field[Snk_PDO_Min_Voltage],
+			vif_component_snk_pdo_name[Snk_PDO_Min_Voltage],
+			min_voltage, str);
+		sprintf(str, "%d mV", max_voltage_mv);
+		set_vif_field_itss(
+			&snkPdo->vif_field[Snk_PDO_Max_Voltage],
+			vif_component_snk_pdo_name[Snk_PDO_Max_Voltage],
+			max_voltage, str);
+		sprintf(str, "%d mW", power_mw);
+		set_vif_field_itss(&snkPdo->vif_field[Snk_PDO_Op_Power],
+				   vif_component_snk_pdo_name[Snk_PDO_Op_Power],
+				   power, str);
+
+	} else if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_VARIABLE) {
+		uint32_t max_voltage = (pdo >> 20) & 0x3ff;
+		uint32_t max_voltage_mv = max_voltage * 50;
+		uint32_t min_voltage = (pdo >> 10) & 0x3ff;
+		uint32_t min_voltage_mv = min_voltage * 50;
+		uint32_t current = pdo & 0x3ff;
+		uint32_t current_ma = current * 10;
+
+		power_mw = (current_ma * max_voltage_mv) / 1000;
+
+		set_vif_field(&snkPdo->vif_field[Snk_PDO_Supply_Type],
+			      vif_component_snk_pdo_name[Snk_PDO_Supply_Type],
+			      "2", "Variable");
+		sprintf(str, "%d mV", min_voltage_mv);
+		set_vif_field_itss(
+			&snkPdo->vif_field[Snk_PDO_Min_Voltage],
+			vif_component_snk_pdo_name[Snk_PDO_Min_Voltage],
+			min_voltage, str);
+		sprintf(str, "%d mV", max_voltage_mv);
+		set_vif_field_itss(
+			&snkPdo->vif_field[Snk_PDO_Max_Voltage],
+			vif_component_snk_pdo_name[Snk_PDO_Max_Voltage],
+			max_voltage, str);
+		sprintf(str, "%d mA", current_ma);
+		set_vif_field_itss(
+			&snkPdo->vif_field[Snk_PDO_Op_Current],
+			vif_component_snk_pdo_name[Snk_PDO_Op_Current], current,
+			str);
+
+	} else if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_AUGMENTED) {
+		uint32_t pps = (pdo >> 28) & 3;
+		uint32_t pps_max_voltage = (pdo >> 17) & 0xff;
+		uint32_t pps_max_voltage_mv = pps_max_voltage * 100;
+		uint32_t pps_min_voltage = (pdo >> 8) & 0xff;
+		uint32_t pps_min_voltage_mv = pps_min_voltage * 100;
+		uint32_t pps_current = pdo & 0x7f;
+		uint32_t pps_current_ma = pps_current * 50;
+
+		if (pps) {
+			fprintf(stderr, "ERROR: Invalid PDO_TYPE %d.\n", pdo);
+			return -1;
+		}
+
+		power_mw = (pps_current_ma * pps_max_voltage_mv) / 1000;
+
+		set_vif_field(&snkPdo->vif_field[Snk_PDO_Supply_Type],
+			      vif_component_snk_pdo_name[Snk_PDO_Supply_Type],
+			      "3", "PPS");
+		sprintf(str, "%d mA", pps_current_ma);
+		set_vif_field_itss(
+			&snkPdo->vif_field[Snk_PDO_Op_Current],
+			vif_component_snk_pdo_name[Snk_PDO_Op_Current],
+			pps_current, str);
+		sprintf(str, "%d mV", pps_min_voltage_mv);
+		set_vif_field_itss(
+			&snkPdo->vif_field[Snk_PDO_Min_Voltage],
+			vif_component_snk_pdo_name[Snk_PDO_Min_Voltage],
+			pps_min_voltage, str);
+		sprintf(str, "%d mV", pps_max_voltage_mv);
+		set_vif_field_itss(
+			&snkPdo->vif_field[Snk_PDO_Max_Voltage],
+			vif_component_snk_pdo_name[Snk_PDO_Max_Voltage],
+			pps_max_voltage, str);
+	} else {
+		fprintf(stderr, "ERROR: Invalid PDO_TYPE %d.\n", pdo);
+		return -1;
+	}
+
+	return power_mw;
+}
+
+__maybe_unused static int32_t init_vif_src_pdo(struct vif_srcPdoList_t *srcPdo,
+					       uint32_t pdo)
+{
+	int32_t power_mw;
+	char str[40];
+
+	/*********************************************************************
+	 * Source PDOs
+	 *
+	 * TODO: Generic todo to fill in additional fields as the need presents
+	 * itself
+	 *
+	 * Fields that are not currently being initialized
+	 *
+	 * vif_srcPdoList
+	 *	Src_PD_OCP_OC_Debounce			numericFieldType
+	 *	Src_PD_OCP_OC_Threshold			numericFieldType
+	 *	Src_PD_OCP_UV_Debounce			numericFieldType
+	 *	Src_PD_OCP_UV_Threshold_Type		numericFieldType
+	 *	Src_PD_OCP_UV_Threshold			numericFieldType
+	 */
+	if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_FIXED) {
+		uint32_t current = pdo & 0x3ff;
+		uint32_t current_ma = current * 10;
+		uint32_t voltage = (pdo >> 10) & 0x3ff;
+		uint32_t voltage_mv = voltage * 50;
+
+		power_mw = (current_ma * voltage_mv) / 1000;
+
+		set_vif_field(&srcPdo->vif_field[Src_PDO_Supply_Type],
+			      vif_component_src_pdo_name[Src_PDO_Supply_Type],
+			      "0", "Fixed");
+		set_vif_field(&srcPdo->vif_field[Src_PDO_Peak_Current],
+			      vif_component_src_pdo_name[Src_PDO_Peak_Current],
+			      "0", "100% IOC");
+		sprintf(str, "%d mV", voltage_mv);
+		set_vif_field_itss(&srcPdo->vif_field[Src_PDO_Voltage],
+				   vif_component_src_pdo_name[Src_PDO_Voltage],
+				   voltage, str);
+		sprintf(str, "%d mA", current_ma);
+		set_vif_field_itss(
+			&srcPdo->vif_field[Src_PDO_Max_Current],
+			vif_component_src_pdo_name[Src_PDO_Max_Current],
+			current, str);
+
+	} else if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_BATTERY) {
+		uint32_t max_voltage = (pdo >> 20) & 0x3ff;
+		uint32_t max_voltage_mv = max_voltage * 50;
+		uint32_t min_voltage = (pdo >> 10) & 0x3ff;
+		uint32_t min_voltage_mv = min_voltage * 50;
+		int32_t power;
+
+		power = pdo & 0x3ff;
+		power_mw = power * 250;
+
+		set_vif_field(&srcPdo->vif_field[Src_PDO_Supply_Type],
+			      vif_component_src_pdo_name[Src_PDO_Supply_Type],
+			      "1", "Battery");
+		sprintf(str, "%d mV", min_voltage_mv);
+		set_vif_field_itss(
+			&srcPdo->vif_field[Src_PDO_Min_Voltage],
+			vif_component_src_pdo_name[Src_PDO_Min_Voltage],
+			min_voltage, str);
+		sprintf(str, "%d mV", max_voltage_mv);
+		set_vif_field_itss(
+			&srcPdo->vif_field[Src_PDO_Max_Voltage],
+			vif_component_src_pdo_name[Src_PDO_Max_Voltage],
+			max_voltage, str);
+		sprintf(str, "%d mW", power_mw);
+		set_vif_field_itss(
+			&srcPdo->vif_field[Src_PDO_Max_Power],
+			vif_component_src_pdo_name[Src_PDO_Max_Power], power,
+			str);
+
+	} else if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_VARIABLE) {
+		uint32_t max_voltage = (pdo >> 20) & 0x3ff;
+		uint32_t max_voltage_mv = max_voltage * 50;
+		uint32_t min_voltage = (pdo >> 10) & 0x3ff;
+		uint32_t min_voltage_mv = min_voltage * 50;
+		uint32_t current = pdo & 0x3ff;
+		uint32_t current_ma = current * 10;
+
+		power_mw = (current_ma * max_voltage_mv) / 1000;
+
+		set_vif_field(&srcPdo->vif_field[Src_PDO_Supply_Type],
+			      vif_component_src_pdo_name[Src_PDO_Supply_Type],
+			      "2", "Variable");
+		set_vif_field(&srcPdo->vif_field[Src_PDO_Peak_Current],
+			      vif_component_src_pdo_name[Src_PDO_Peak_Current],
+			      "0", "100% IOC");
+		sprintf(str, "%d mV", min_voltage_mv);
+		set_vif_field_itss(
+			&srcPdo->vif_field[Src_PDO_Min_Voltage],
+			vif_component_src_pdo_name[Src_PDO_Min_Voltage],
+			min_voltage, str);
+		sprintf(str, "%d mV", max_voltage_mv);
+		set_vif_field_itss(
+			&srcPdo->vif_field[Src_PDO_Max_Voltage],
+			vif_component_src_pdo_name[Src_PDO_Max_Voltage],
+			max_voltage, str);
+		sprintf(str, "%d mA", current_ma);
+		set_vif_field_itss(
+			&srcPdo->vif_field[Src_PDO_Max_Current],
+			vif_component_src_pdo_name[Src_PDO_Max_Current],
+			current, str);
+
+	} else if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_AUGMENTED) {
+		uint32_t pps = (pdo >> 28) & 3;
+		uint32_t pps_max_voltage = (pdo >> 17) & 0xff;
+		uint32_t pps_max_voltage_mv = pps_max_voltage * 100;
+		uint32_t pps_min_voltage = (pdo >> 8) & 0xff;
+		uint32_t pps_min_voltage_mv = pps_min_voltage * 100;
+		uint32_t pps_current = pdo & 0x7f;
+		uint32_t pps_current_ma = pps_current * 50;
+
+		if (pps) {
+			fprintf(stderr, "ERROR: Invalid PDO_TYPE %d.\n", pdo);
+			return -1;
+		}
+
+		power_mw = (pps_current_ma * pps_max_voltage_mv) / 1000;
+
+		set_vif_field(&srcPdo->vif_field[Src_PDO_Supply_Type],
+			      vif_component_src_pdo_name[Src_PDO_Supply_Type],
+			      "3", "PPS");
+		sprintf(str, "%d mA", pps_current_ma);
+		set_vif_field_itss(
+			&srcPdo->vif_field[Src_PDO_Max_Current],
+			vif_component_src_pdo_name[Src_PDO_Max_Current],
+			pps_current, str);
+		sprintf(str, "%d mV", pps_min_voltage_mv);
+		set_vif_field_itss(
+			&srcPdo->vif_field[Src_PDO_Min_Voltage],
+			vif_component_src_pdo_name[Src_PDO_Min_Voltage],
+			pps_min_voltage, str);
+		sprintf(str, "%d mV", pps_max_voltage_mv);
+		set_vif_field_itss(
+			&srcPdo->vif_field[Src_PDO_Max_Voltage],
+			vif_component_src_pdo_name[Src_PDO_Max_Voltage],
+			pps_max_voltage, str);
+
+	} else {
+		fprintf(stderr, "ERROR: Invalid PDO_TYPE %d.\n", pdo);
+		return -1;
+	}
+
+	return power_mw;
+}
+
+/*********************************************************************
+ * Init VIF Fields
+ */
+static void init_vif_fields(struct vif_field_t *vif_fields,
+			    struct vif_field_t *vif_app_fields,
+			    const char *board)
+{
+	set_vif_field(&vif_fields[VIF_Specification],
+		      vif_name[VIF_Specification], NULL, "3.18");
+
+	set_vif_field(&vif_app_fields[Vendor], vif_app_name[Vendor], NULL,
+		      VIF_APP_VENDOR_VALUE);
+
+	set_vif_field(&vif_app_fields[Name], vif_app_name[Name], NULL,
+		      VIF_APP_NAME_VALUE);
+
+	set_vif_field(&vif_app_fields[Version], vif_app_name[Version], NULL,
+		      VIF_APP_VERSION_VALUE);
+
+	set_vif_field(&vif_fields[Vendor_Name], vif_name[Vendor_Name], NULL,
+		      VENDOR_NAME_VALUE);
+
+#if defined(CONFIG_USB_PD_MODEL_PART_NUMBER)
+	set_vif_field(&vif_fields[Model_Part_Number],
+		      vif_name[Model_Part_Number], NULL,
+		      CONFIG_USB_PD_MODEL_PART_NUMBER);
+#else
+	if (board && strlen(board) > 0)
+		set_vif_field(&vif_fields[Model_Part_Number],
+			      vif_name[Model_Part_Number], NULL, board);
+	else
+		set_vif_field(&vif_fields[Model_Part_Number],
+			      vif_name[Model_Part_Number], NULL, "FIX-ME");
 #endif
 
-	fprintf(vif, "Attempts_Discov_SOP: %s\r\n", yn);
+#if defined(CONFIG_USB_PD_PRODUCT_REVISION)
+	set_vif_field(&vif_fields[Product_Revision], vif_name[Product_Revision],
+		      NULL, CONFIG_USB_PD_PRODUCT_REVISION);
+#else
+	set_vif_field(&vif_fields[Product_Revision], vif_name[Product_Revision],
+		      NULL, "FIX-ME");
+#endif
+
+#if defined(CONFIG_USB_PD_TID)
+	set_vif_field_stis(&vif_fields[TID], vif_name[TID], NULL,
+			   CONFIG_USB_PD_TID);
+#else
+	set_vif_field_stis(&vif_fields[TID], vif_name[TID], NULL,
+			   DEFAULT_MISSING_TID);
+#endif
+
+	set_vif_field(&vif_fields[VIF_Product_Type], vif_name[VIF_Product_Type],
+		      "0", "Port Product");
+
+	set_vif_field(&vif_fields[Certification_Type],
+		      vif_name[Certification_Type], "0", "End Product");
+}
+
+/*********************************************************************
+ * Init VIF/Component[] Fields
+ */
+static void init_vif_component_fields(struct vif_field_t *vif_fields,
+				      enum bc_1_2_support *bc_support,
+				      enum dtype type)
+{
+#if defined(CONFIG_USB_PD_PORT_LABEL)
+	set_vif_field_stis(&vif_fields[Port_Label],
+			   vif_component_name[Port_Label], NULL,
+			   CONFIG_USB_PD_PORT_LABEL);
+#else
+	set_vif_field_stis(&vif_fields[Port_Label],
+			   vif_component_name[Port_Label], NULL,
+			   component_index);
+#endif
+
+	set_vif_field(&vif_fields[Connector_Type],
+		      vif_component_name[Connector_Type], "2", "Type-C®");
+
+	if (is_usb4_supported()) {
+		int router_index;
+
+		set_vif_field_b(&vif_fields[USB4_Supported],
+				vif_component_name[USB4_Supported], true);
+
+		if (!get_vif_field_tag_number(
+			    &vif.Product.USB4RouterList[0]
+				     .vif_field[USB4_Router_ID],
+			    &router_index)) {
+			router_index = 0;
+		}
+		set_vif_field_itss(&vif_fields[USB4_Router_Index],
+				   vif_component_name[USB4_Router_Index],
+				   router_index, NULL);
+	} else {
+		set_vif_field_b(&vif_fields[USB4_Supported],
+				vif_component_name[USB4_Supported], false);
+	}
+
+	set_vif_field_b(&vif_fields[USB_PD_Support],
+			vif_component_name[USB_PD_Support],
+			is_usb_pd_supported());
+
+	if (is_usb_pd_supported()) {
+		switch (type) {
+		case SNK:
+			set_vif_field(&vif_fields[PD_Port_Type],
+				      vif_component_name[PD_Port_Type], "0",
+				      "Consumer Only");
+			break;
+		case SRC:
+			set_vif_field(&vif_fields[PD_Port_Type],
+				      vif_component_name[PD_Port_Type], "3",
+				      "Provider Only");
+			break;
+		case DRP:
+			set_vif_field(&vif_fields[PD_Port_Type],
+				      vif_component_name[PD_Port_Type], "4",
+				      "DRP");
+			break;
+		}
+	}
+
+	switch (type) {
+	case SNK:
+		set_vif_field(&vif_fields[Type_C_State_Machine],
+			      vif_component_name[Type_C_State_Machine], "1",
+			      "SNK");
+		break;
+	case SRC:
+		set_vif_field(&vif_fields[Type_C_State_Machine],
+			      vif_component_name[Type_C_State_Machine], "0",
+			      "SRC");
+		break;
+	case DRP:
+		set_vif_field(&vif_fields[Type_C_State_Machine],
+			      vif_component_name[Type_C_State_Machine], "2",
+			      "DRP");
+		break;
+	}
+
+	set_vif_field_b(&vif_fields[Captive_Cable],
+			vif_component_name[Captive_Cable], false);
+
+	set_vif_field_b(&vif_fields[Port_Battery_Powered],
+			vif_component_name[Port_Battery_Powered],
+			IS_ENABLED(CONFIG_BATTERY));
+
+	*bc_support = BC_1_2_SUPPORT_NONE;
+	if (IS_ENABLED(CONFIG_BC12_DETECT_MAX14637))
+		*bc_support = BC_1_2_SUPPORT_PORTABLE_DEVICE;
+	if (IS_ENABLED(CONFIG_BC12_DETECT_MT6360))
+		*bc_support = BC_1_2_SUPPORT_PORTABLE_DEVICE;
+	if (IS_ENABLED(CONFIG_BC12_DETECT_PI3USB9201))
+		*bc_support = BC_1_2_SUPPORT_BOTH;
+	if (IS_ENABLED(CONFIG_BC12_DETECT_PI3USB9281))
+		*bc_support = BC_1_2_SUPPORT_PORTABLE_DEVICE;
+
+	switch (*bc_support) {
+	case BC_1_2_SUPPORT_NONE:
+		set_vif_field(&vif_fields[BC_1_2_Support],
+			      vif_component_name[BC_1_2_Support], "0", "None");
+		break;
+	case BC_1_2_SUPPORT_PORTABLE_DEVICE:
+		set_vif_field(&vif_fields[BC_1_2_Support],
+			      vif_component_name[BC_1_2_Support], "1",
+			      "Portable Device");
+		break;
+	case BC_1_2_SUPPORT_CHARGING_PORT:
+		set_vif_field(&vif_fields[BC_1_2_Support],
+			      vif_component_name[BC_1_2_Support], "2",
+			      "Charging Port");
+		break;
+	case BC_1_2_SUPPORT_BOTH:
+		set_vif_field(&vif_fields[BC_1_2_Support],
+			      vif_component_name[BC_1_2_Support], "3", "Both");
+		break;
+	}
 }
 
-static void write_chunking_implemented_sop(FILE *vif)
-{
-	char *yn = "NO";
-
-#if defined(CONFIG_USB_PD_REV30) && defined(CONFIG_USB_PRL_SM)
-	yn = "YES";
-#endif
+/*********************************************************************
+ * Init VIF/Component[] General PD Fields
+ */
+static void init_vif_component_general_pd_fields(struct vif_field_t *vif_fields,
+						 enum dtype type)
+{
+	if (IS_ENABLED(CONFIG_USB_PD_REV30) || IS_ENABLED(CONFIG_USB_PRL_SM)) {
+		set_vif_field(&vif_fields[PD_Spec_Revision_Major],
+			      vif_component_name[PD_Spec_Revision_Major], "3",
+			      NULL);
+		set_vif_field(&vif_fields[PD_Spec_Revision_Minor],
+			      vif_component_name[PD_Spec_Revision_Minor], "1",
+			      NULL);
+		set_vif_field(&vif_fields[PD_Spec_Version_Major],
+			      vif_component_name[PD_Spec_Version_Major], "1",
+			      NULL);
+		set_vif_field(&vif_fields[PD_Spec_Version_Minor],
+			      vif_component_name[PD_Spec_Version_Minor], "3",
+			      NULL);
+
+		set_vif_field(&vif_fields[PD_Specification_Revision],
+			      vif_component_name[PD_Specification_Revision],
+			      "2", "Revision 3");
+	} else {
+		set_vif_field(&vif_fields[PD_Spec_Revision_Major],
+			      vif_component_name[PD_Spec_Revision_Major], "2",
+			      NULL);
+		set_vif_field(&vif_fields[PD_Spec_Revision_Minor],
+			      vif_component_name[PD_Spec_Revision_Minor], "0",
+			      NULL);
+		set_vif_field(&vif_fields[PD_Spec_Version_Major],
+			      vif_component_name[PD_Spec_Version_Major], "1",
+			      NULL);
+		set_vif_field(&vif_fields[PD_Spec_Version_Minor],
+			      vif_component_name[PD_Spec_Version_Minor], "3",
+			      NULL);
+
+		set_vif_field(&vif_fields[PD_Specification_Revision],
+			      vif_component_name[PD_Specification_Revision],
+			      "1", "Revision 2");
+	}
 
-	fprintf(vif, "Chunking_Implemented_SOP: %s\r\n", yn);
-}
+	set_vif_field_b(&vif_fields[USB_Comms_Capable],
+			vif_component_name[USB_Comms_Capable],
+			is_usb_comms_capable());
 
-static void write_unchunked_extended_messages_supported(FILE *vif)
-{
-	fprintf(vif, "Unchunked_Extended_Messages_Supported: NO\r\n");
-}
+	/*
+	 * DR_Swap_To_DFP_Supported
+	 *
+	 * Set to YES if Qualifying Product can respond with an Accept to a
+	 * DR_Swap request to switch from a UFP to a DFP.
+	 *
+	 * If Type_C_State_Machine is set to DRP and Type_C_Can_Act_As_Host
+	 * is set to YES and Type_C_Can_Act_As_Device is set to NO then this
+	 * field shall be set to YES.
+	 *
+	 * If Type_C_State_Machine is set to SNK and either
+	 * Type_C_Can_Act_As_Host or Type_C_Is_Alt_Mode_Controller is set to
+	 * YES, then this field shall be set to YES.
+	 *
+	 * If Type_C_State_Machine is set to SRC and Type_C_Can_Act_As_Device
+	 * is set to YES, then this field shall be set to YES.
+	 *
+	 * If VIF_Product_Type is set to 1 (Cable) or PD_Port_Type is set to
+	 * 5 (eMarker) then this field shall be ignored by Testers.
+	 *
+	 * TODO(b/172437046): USB4 has not been added and this last statement
+	 * needs to be handled when it is:
+	 * If USB4_DFP_Supported is set to YES and Type_C_Port_On_Hub is set
+	 * to NO, then this field shall be set to YES.
+	 */
+	{
+		bool supports_to_dfp = false;
 
-static void write_manufacturer_info_supported_port(FILE *vif)
-{
-	char *yn = "NO";
+		switch (type) {
+		case SRC:
+			supports_to_dfp = can_act_as_device();
+			break;
+		case SNK:
+			supports_to_dfp =
+				(can_act_as_host() || is_alt_mode_controller());
+			break;
+		case DRP:
+			supports_to_dfp =
+				(can_act_as_host() && !can_act_as_device());
+			break;
+		}
 
-#ifdef CONFIG_USB_PD_MANUFACTURER_INFO
-	yn = "YES";
-#endif
+		set_vif_field_b(&vif_fields[DR_Swap_To_DFP_Supported],
+				vif_component_name[DR_Swap_To_DFP_Supported],
+				supports_to_dfp);
+	}
 
-	fprintf(vif, "Manufacturer_Info_Supported_Port: %s\r\n", yn);
-}
+	/*
+	 * DR_Swap_To_UFP_Supported
+	 *
+	 * Set to YES if Qualifying Product can respond with an Accept to a
+	 * DR_Swap request to switch from a DFP to a UFP.
+	 *
+	 * If Type_C_State_Machine is set to DRP and Type_C_Can_Act_As_Device
+	 * is set to YES and Type_C_Can_Act_As_Host is set to NO then this
+	 * field shall be set to YES.
+	 *
+	 * If Type_C_State_Machine is set to SNK and either
+	 * Type_C_Can_Act_As_Host or Type_C_Is_Alt_Mode_Controller is set to
+	 * YES, then this field shall be set to YES.
+	 *
+	 * If Type_C_State_Machine is set to SRC and Type_C_Can_Act_As_Device
+	 * is set to YES, then this field shall be set to YES.
+	 *
+	 * If VIF_Product_Type is set to 1 (Cable) or PD_Port_Type is set to
+	 * 5 (eMarker) then this field shall be ignored by Testers.
+	 */
+	{
+		bool supports_to_ufp = false;
 
-static void write_manufacturer_info_pid_port(FILE *vif)
-{
-#ifdef USB_PID_GOOGLE
-	fprintf(vif, "Manufacturer_Info_PID_Port: 0x%04x\r\n", USB_PID_GOOGLE);
-#endif
-}
+		switch (type) {
+		case SRC:
+			supports_to_ufp = can_act_as_device();
+			break;
+		case SNK:
+			supports_to_ufp =
+				(can_act_as_host() || is_alt_mode_controller());
+			break;
+		case DRP:
+			supports_to_ufp =
+				(can_act_as_device() && !can_act_as_host());
+			break;
+		}
 
-static void write_security_msgs_supported_sop(FILE *vif)
-{
-	char *yn = "NO";
+		set_vif_field_b(&vif_fields[DR_Swap_To_UFP_Supported],
+				vif_component_name[DR_Swap_To_UFP_Supported],
+				supports_to_ufp);
+	}
 
-#ifdef CONFIG_USB_PD_SECURITY_MSGS
-	yn = "YES";
+	if (is_src()) {
+		/* SRC capable */
+		if (IS_ENABLED(CONFIG_CHARGER))
+			/* USB-C UP bit set */
+			set_vif_field_b(&vif_fields[Unconstrained_Power],
+					vif_component_name[Unconstrained_Power],
+					(src_pdo[0] & PDO_FIXED_UNCONSTRAINED));
+		else {
+			/* Barrel charger being used */
+			int32_t dedicated_charge_port_count = 0;
+
+#ifdef CONFIG_DEDICATED_CHARGE_PORT_COUNT
+			dedicated_charge_port_count =
+				CONFIG_DEDICATED_CHARGE_PORT_COUNT;
 #endif
 
-	fprintf(vif, "Security_Msgs_Supported_SOP: %s\r\n", yn);
-}
-
-static void write_num_fixed_batteries(FILE *vif)
-{
-	int num = 1;
+			set_vif_field_b(&vif_fields[Unconstrained_Power],
+					vif_component_name[Unconstrained_Power],
+					(dedicated_charge_port_count > 0));
+		}
+	} else {
+		/* Not SRC capable */
+		set_vif_field_b(&vif_fields[Unconstrained_Power],
+				vif_component_name[Unconstrained_Power], false);
+	}
 
-#ifdef CONFIG_NUM_FIXED_BATTERIES
-	num = CONFIG_NUM_FIXED_BATTERIES;
+	set_vif_field_b(&vif_fields[VCONN_Swap_To_On_Supported],
+			vif_component_name[VCONN_Swap_To_On_Supported],
+			IS_ENABLED(CONFIG_USBC_VCONN_SWAP));
+
+	set_vif_field_b(&vif_fields[VCONN_Swap_To_Off_Supported],
+			vif_component_name[VCONN_Swap_To_Off_Supported],
+			IS_ENABLED(CONFIG_USBC_VCONN_SWAP));
+
+	set_vif_field_b(&vif_fields[Responds_To_Discov_SOP_UFP],
+			vif_component_name[Responds_To_Discov_SOP_UFP],
+			does_respond_to_discov_sop_ufp());
+
+	set_vif_field_b(&vif_fields[Responds_To_Discov_SOP_DFP],
+			vif_component_name[Responds_To_Discov_SOP_DFP],
+			does_respond_to_discov_sop_dfp());
+
+	set_vif_field_b(&vif_fields[Attempts_Discov_SOP],
+			vif_component_name[Attempts_Discov_SOP],
+			((!IS_ENABLED(CONFIG_USB_PD_SIMPLE_DFP)) ||
+			 (type != SRC)));
+
+	set_vif_field(&vif_fields[Power_Interruption_Available],
+		      vif_component_name[Power_Interruption_Available], "0",
+		      "No Interruption Possible");
+
+	set_vif_field_b(&vif_fields[Data_Reset_Supported],
+			vif_component_name[Data_Reset_Supported],
+			IS_ENABLED(CONFIG_USB_PD_USB4));
+
+	set_vif_field_b(&vif_fields[Enter_USB_Supported],
+			vif_component_name[Enter_USB_Supported],
+			IS_ENABLED(CONFIG_USB_PD_USB4));
+
+	set_vif_field_b(&vif_fields[Chunking_Implemented_SOP],
+			vif_component_name[Chunking_Implemented_SOP],
+			(IS_ENABLED(CONFIG_USB_PD_REV30) &&
+			 IS_ENABLED(CONFIG_USB_PRL_SM)));
+
+	set_vif_field_b(
+		&vif_fields[Unchunked_Extended_Messages_Supported],
+		vif_component_name[Unchunked_Extended_Messages_Supported],
+		false);
+
+	if (IS_ENABLED(CONFIG_USB_PD_MANUFACTURER_INFO)) {
+		char hex_str[10];
+
+		set_vif_field_b(
+			&vif_fields[Manufacturer_Info_Supported_Port],
+			vif_component_name[Manufacturer_Info_Supported_Port],
+			true);
+
+		sprintf(hex_str, "%04X", USB_VID_GOOGLE);
+		set_vif_field_itss(
+			&vif_fields[Manufacturer_Info_VID_Port],
+			vif_component_name[Manufacturer_Info_VID_Port],
+			USB_VID_GOOGLE, hex_str);
+
+#if defined(CONFIG_USB_PID)
+		sprintf(hex_str, "%04X", CONFIG_USB_PID);
+		set_vif_field_itss(
+			&vif_fields[Manufacturer_Info_PID_Port],
+			vif_component_name[Manufacturer_Info_PID_Port],
+			CONFIG_USB_PID, hex_str);
 #else
-#if defined(CONFIG_USB_CTVPD) || defined(CONFIG_USB_VPD)
-	num = 0;
+		sprintf(hex_str, "%04X", DEFAULT_MISSING_PID);
+		set_vif_field_itss(
+			&vif_fields[Manufacturer_Info_PID_Port],
+			vif_component_name[Manufacturer_Info_PID_Port],
+			DEFAULT_MISSING_PID, hex_str);
 #endif
-#endif
-
-	fprintf(vif, "Num_Fixed_Batteries: %d\r\n", num);
-}
-
-static void write_num_swappable_battery_slots(FILE *vif)
-{
-	fprintf(vif, "Num_Swappable_Battery_Slots: 0\r\n");
-}
-
-static void write_sop_capable(FILE *vif)
-{
-	char *yn = "YES";
+	} else {
+		set_vif_field_b(
+			&vif_fields[Manufacturer_Info_Supported_Port],
+			vif_component_name[Manufacturer_Info_Supported_Port],
+			false);
+	}
 
-#if defined(CONFIG_USB_CTVPD) || defined(CONFIG_USB_VPD)
-	yn = "NO";
+	set_vif_field_b(&vif_fields[Security_Msgs_Supported_SOP],
+			vif_component_name[Security_Msgs_Supported_SOP],
+			IS_ENABLED(CONFIG_USB_PD_SECURITY_MSGS));
+
+#if defined(CONFIG_NUM_FIXED_BATTERIES)
+	set_vif_field_itss(&vif_fields[Num_Fixed_Batteries],
+			   vif_component_name[Num_Fixed_Batteries],
+			   CONFIG_NUM_FIXED_BATTERIES, NULL);
+#elif defined(CONFIG_USB_CTVPD) || defined(CONFIG_USB_VPD)
+	set_vif_field(&vif_fields[Num_Fixed_Batteries],
+		      vif_component_name[Num_Fixed_Batteries], "0", NULL);
+#else
+	set_vif_field(&vif_fields[Num_Fixed_Batteries],
+		      vif_component_name[Num_Fixed_Batteries], "1", NULL);
 #endif
 
-	fprintf(vif, "SOP_Capable: %s\r\n", yn);
+	set_vif_field(&vif_fields[Num_Swappable_Battery_Slots],
+		      vif_component_name[Num_Swappable_Battery_Slots], "0",
+		      NULL);
+
+	set_vif_field(&vif_fields[ID_Header_Connector_Type_SOP],
+		      vif_component_name[ID_Header_Connector_Type_SOP], "2",
+		      "USB Type-C\u00ae Receptacle");
 }
 
-static void write_sop_p_capable(FILE *vif)
+/*********************************************************************
+ * Init VIF/Component[] SOP* Capabilities Fields
+ */
+static void
+init_vif_component_sop_capabilities_fields(struct vif_field_t *vif_fields)
 {
-	char *yn = "NO";
-
-#if defined(CONFIG_USB_CTVPD) || defined(CONFIG_USB_VPD)
-	yn = "YES";
-#endif
+	set_vif_field_b(&vif_fields[SOP_Capable],
+			vif_component_name[SOP_Capable], can_act_as_host());
 
-	fprintf(vif, "SOP_P_Capable: %s\r\n", yn);
-}
+	set_vif_field_b(&vif_fields[SOP_P_Capable],
+			vif_component_name[SOP_P_Capable],
+			IS_ENABLED(CONFIG_USB_PD_DECODE_SOP));
 
-static void write_sop_pp_capable(FILE *vif)
-{
-	fprintf(vif, "SOP_PP_Capable: NO\r\n");
-}
+	set_vif_field_b(&vif_fields[SOP_PP_Capable],
+			vif_component_name[SOP_PP_Capable],
+			IS_ENABLED(CONFIG_USB_PD_DECODE_SOP));
 
-static void write_sop_p_debug_capable(FILE *vif)
-{
-	fprintf(vif, "SOP_P_Debug_Capable: NO\r\n");
-}
+	set_vif_field_b(&vif_fields[SOP_P_Debug_Capable],
+			vif_component_name[SOP_P_Debug_Capable], false);
 
-static void write_sop_pp_debug_capable(FILE *vif)
-{
-	fprintf(vif, "SOP_PP_Debug_Capable: NO\r\n");
+	set_vif_field_b(&vif_fields[SOP_PP_Debug_Capable],
+			vif_component_name[SOP_PP_Debug_Capable], false);
 }
 
-/*
- * USB Type-C Fields
+/*********************************************************************
+ * Init VIF/Component[] USB Type-C Fields
  */
-
-static void write_type_c_implements_try_src(FILE *vif)
+static void init_vif_component_usb_type_c_fields(struct vif_field_t *vif_fields,
+						 enum dtype type)
 {
-	char *yn = "NO";
+	set_vif_field_b(&vif_fields[Type_C_Implements_Try_SRC],
+			vif_component_name[Type_C_Implements_Try_SRC],
+			IS_ENABLED(CONFIG_USB_PD_TRY_SRC));
 
-#ifdef CONFIG_USB_PD_TRY_SRC
-	yn = "YES";
-#endif
+	set_vif_field_b(&vif_fields[Type_C_Implements_Try_SNK],
+			vif_component_name[Type_C_Implements_Try_SNK], false);
 
-	fprintf(vif, "Type_C_Implements_Try_SRC: %s\r\n", yn);
-}
+	{
+		int rp = CONFIG_USB_PD_PULLUP;
 
-static void write_type_c_implements_try_snk(FILE *vif)
-{
-	fprintf(vif, "Type_C_Implements_Try_SNK: NO\r\n");
-}
+#if defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT)
+		rp = CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT;
+#endif
 
-static void write_rp_value(FILE *vif)
-{
-	/*
-	 * 0 - Default
-	 * 1 - 1.5A
-	 * 2 - 3A
-	 */
-	int rp = CONFIG_USB_PD_PULLUP;
+		switch (rp) {
+		case 0:
+			set_vif_field(&vif_fields[RP_Value],
+				      vif_component_name[RP_Value], "0",
+				      "Default");
+			break;
+		case 1:
+			set_vif_field(&vif_fields[RP_Value],
+				      vif_component_name[RP_Value], "1",
+				      "1.5A");
+			break;
+		case 2:
+			set_vif_field(&vif_fields[RP_Value],
+				      vif_component_name[RP_Value], "2", "3A");
+			break;
+		default:
+			set_vif_field_itss(&vif_fields[RP_Value],
+					   vif_component_name[RP_Value], rp,
+					   NULL);
+		}
+	}
 
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	rp = CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT;
-#endif
+	if (type == SNK)
+		set_vif_field_b(
+			&vif_fields[Type_C_Supports_VCONN_Powered_Accessory],
+			vif_component_name
+				[Type_C_Supports_VCONN_Powered_Accessory],
+			false);
+
+	set_vif_field_b(&vif_fields[Type_C_Is_VCONN_Powered_Accessory],
+			vif_component_name[Type_C_Is_VCONN_Powered_Accessory],
+			false);
+
+	set_vif_field_b(&vif_fields[Type_C_Is_Debug_Target_SRC],
+			vif_component_name[Type_C_Is_Debug_Target_SRC], true);
+
+	set_vif_field_b(&vif_fields[Type_C_Is_Debug_Target_SNK],
+			vif_component_name[Type_C_Is_Debug_Target_SNK], true);
+
+	set_vif_field_b(&vif_fields[Type_C_Can_Act_As_Host],
+			vif_component_name[Type_C_Can_Act_As_Host],
+			can_act_as_host());
+
+	set_vif_field_b(&vif_fields[Type_C_Is_Alt_Mode_Controller],
+			vif_component_name[Type_C_Is_Alt_Mode_Controller],
+			is_alt_mode_controller());
+
+	if (can_act_as_device()) {
+		set_vif_field_b(&vif_fields[Type_C_Can_Act_As_Device],
+				vif_component_name[Type_C_Can_Act_As_Device],
+				true);
+
+		if (is_usb_pd_supported() && does_respond_to_discov_sop_ufp())
+			set_vif_field_b(
+				&vif_fields[Type_C_Is_Alt_Mode_Adapter],
+				vif_component_name[Type_C_Is_Alt_Mode_Adapter],
+				IS_ENABLED(CONFIG_USB_ALT_MODE_ADAPTER));
+	} else {
+		set_vif_field_b(&vif_fields[Type_C_Can_Act_As_Device],
+				vif_component_name[Type_C_Can_Act_As_Device],
+				false);
+		set_vif_field_b(&vif_fields[Type_C_Is_Alt_Mode_Adapter],
+				vif_component_name[Type_C_Is_Alt_Mode_Adapter],
+				false);
+	}
 
-	fprintf(vif, "Rp_Value: %d\r\n", rp);
-}
+	set_vif_field_b(&vif_fields[Modal_Operation_Supported_SOP],
+			vif_component_name[Modal_Operation_Supported_SOP],
+			is_alt_mode_adapter());
 
-static void write_type_c_supports_vconn_powered_accessory(FILE *vif)
-{
-	fprintf(vif, "Type_C_Supports_VCONN_Powered_Accessory: NO\r\n");
-}
+	{
+		int ps = POWER_UFP;
 
-static void write_type_c_is_debug_target_src(FILE *vif)
-{
-	fprintf(vif, "Type_C_Is_Debug_Target_SRC: YES\r\n");
-}
+		if (IS_ENABLED(CONFIG_BATTERY))
+			ps = POWER_BOTH;
+#if defined(CONFIG_DEDICATED_CHARGE_PORT_COUNT)
+		else if (CONFIG_DEDICATED_CHARGE_PORT_COUNT == 1)
+			ps = POWER_EXTERNAL;
+		else if (CONFIG_DEDICATED_CHARGE_PORT_COUNT > 1)
+			ps = POWER_BOTH;
+#endif
 
-static void write_type_c_is_debug_target_snk(FILE *vif)
-{
-	fprintf(vif, "Type_C_Is_Debug_Target_SNK: YES\r\n");
-}
+		switch (ps) {
+		case POWER_EXTERNAL:
+			set_vif_field(&vif_fields[Type_C_Power_Source],
+				      vif_component_name[Type_C_Power_Source],
+				      "0", "Externally Powered");
+			break;
+		case POWER_UFP:
+			set_vif_field(&vif_fields[Type_C_Power_Source],
+				      vif_component_name[Type_C_Power_Source],
+				      "1", "UFP-powered");
+			break;
+		case POWER_BOTH:
+			set_vif_field(&vif_fields[Type_C_Power_Source],
+				      vif_component_name[Type_C_Power_Source],
+				      "2", "Both");
+			break;
+		default:
+			set_vif_field_itss(
+				&vif_fields[Type_C_Power_Source],
+				vif_component_name[Type_C_Power_Source], ps,
+				NULL);
+		}
+	}
 
-static void write_type_c_can_act_as_host(FILE *vif)
-{
-	char *yn = "YES";
+	set_vif_field_b(&vif_fields[Type_C_Port_On_Hub],
+			vif_component_name[Type_C_Port_On_Hub], false);
 
-	#if defined(CONFIG_USB_CTVPD) || defined(CONFIG_USB_VPD)
-		yn = "NO";
-	#endif
+	set_vif_field_b(&vif_fields[Type_C_Supports_Audio_Accessory],
+			vif_component_name[Type_C_Supports_Audio_Accessory],
+			false);
 
-	fprintf(vif, "Type_C_Can_Act_As_Host: %s\r\n", yn);
+	set_vif_field_b(&vif_fields[Type_C_Sources_VCONN],
+			vif_component_name[Type_C_Sources_VCONN],
+			IS_ENABLED(CONFIG_USBC_VCONN));
 }
 
-static void write_type_c_is_alt_mode_controller(FILE *vif)
+static void init_vif_component_usb4_port_fields(struct vif_field_t *vif_fields)
 {
-	fprintf(vif, "Type_C_Is_Alt_Mode_Controller: NO\r\n");
-}
+	int vi;
+	const char *vs;
 
-static void write_type_c_can_act_as_device(FILE *vif)
-{
-	char *yn = "NO";
+	if (!is_usb4_supported())
+		return;
 
-#if defined(USB_DEV_CLASS) && defined(USB_CLASS_BILLBOARD)
-	if (USB_DEV_CLASS == USB_CLASS_BILLBOARD)
-		yn = "YES";
-#endif
+	set_vif_field_c(&vif_fields[USB4_Port_Header], "USB4\u2122 Port");
 
-	fprintf(vif, "Type_C_Can_Act_As_Device: %s\r\n", yn);
-}
+	vi = vif_get_max_tbt_speed();
+	switch (vi) {
+	case 0:
+		vs = "Gen 2 (20Gb)";
+		break;
+	case 1:
+		vs = "Gen 3 (40Gb)";
+		break;
+	default:
+		vs = "Undefined";
+	}
 
-static void write_type_c_is_alt_mode_adapter(FILE *vif)
+	set_vif_field_itss(&vif_fields[USB4_Max_Speed],
+			   vif_component_name[USB4_Max_Speed], vi, vs);
+
+	set_vif_field_b(&vif_fields[USB4_TBT3_Compatibility_Supported],
+			vif_component_name[USB4_TBT3_Compatibility_Supported],
+			is_usb4_tbt3_compatible());
+
+	set_vif_field_b(&vif_fields[USB4_PCIe_Tunneling_Supported],
+			vif_component_name[USB4_PCIe_Tunneling_Supported],
+			is_usb4_pcie_tunneling_supported());
+}
+
+/*********************************************************************
+ * Init VIF/Component[] USB Data - Upstream Facing Port Fields
+ *
+ * TODO: Generic todo to fill in additional fields as the need presents
+ * itself
+ *
+ * Fields that are not currently being initialized
+ *
+ * vif_Component
+ *	Device_Contains_Captive_Retimer		booleanFieldType
+ *	Device_Truncates_DP_For_tDHPResponse	booleanFieldType
+ *	Device_Gen1x1_tLinkTurnaround		numericFieldType
+ *	Device_Gen2x1_tLinkTurnaround		numericFieldType
+ */
+static void
+init_vif_component_usb_data_ufp_fields(struct vif_field_t *vif_fields)
 {
-	char *yn = "NO";
+	/*
+	 * TOTO(b:172441959) Adjust the speed based on CONFIG_
+	 */
+	enum usb_speed ds = USB_GEN11;
+	bool supports_usb_data;
 
-	if (IS_ENABLED(CONFIG_USB_ALT_MODE_ADAPTER))
-		yn = "YES";
+	/*
+	 * The fields in this section shall be ignored by Testers unless
+	 * Connector_Type is set to 1 (Type-B) or 3 (Micro A/B), or
+	 * Connector_Type is set to 2 (Type-C) and Type_C_Can_Act_As_Device
+	 * is set to YES.
+	 *
+	 * NOTE: We currently are always a Connector_Type of 2 (Type-C)
+	 */
+	if (!can_act_as_device())
+		return;
 
-	fprintf(vif, "Type_C_Is_Alt_Mode_Adapter: %s\r\n", yn);
+	supports_usb_data = does_support_device_usb_data();
+	set_vif_field_b(&vif_fields[Device_Supports_USB_Data],
+			vif_component_name[Device_Supports_USB_Data],
+			supports_usb_data);
+
+	if (supports_usb_data) {
+		switch (ds) {
+		case USB_2:
+			set_vif_field_itss(&vif_fields[Device_Speed],
+					   vif_component_name[Device_Speed],
+					   USB_2, "USB 2");
+			break;
+		case USB_GEN11:
+			set_vif_field_itss(&vif_fields[Device_Speed],
+					   vif_component_name[Device_Speed],
+					   USB_GEN11, "USB 3.2 Gen 1x1");
+			break;
+		case USB_GEN21:
+			set_vif_field_itss(&vif_fields[Device_Speed],
+					   vif_component_name[Device_Speed],
+					   USB_GEN21, "USB 3.2 Gen 2x1");
+			break;
+		case USB_GEN12:
+			set_vif_field_itss(&vif_fields[Device_Speed],
+					   vif_component_name[Device_Speed],
+					   USB_GEN12, "USB 3.2 Gen 1x2");
+			break;
+		case USB_GEN22:
+			set_vif_field_itss(&vif_fields[Device_Speed],
+					   vif_component_name[Device_Speed],
+					   USB_GEN22, "USB 3.2 Gen 2x2");
+			break;
+		}
+	}
 }
 
-static void write_type_c_power_source(FILE *vif)
+/*********************************************************************
+ * Init VIF/Component[] USB Data - Downstream Facing Port Fields
+ *
+ * TODO: Generic todo to fill in additional fields as the need presents
+ * itself
+ *
+ * Fields that are not currently being initialized
+ *
+ * vif_Component
+ *	Hub_Port_Number				numericFieldType
+ *	Host_Truncates_DP_For_tDHPResponse	booleanFieldType
+ *	Host_Gen1x1_tLinkTurnaround		numericFieldType
+ *	Host_Gen2x1_tLinkTurnaround		numericFieldType
+ *	Host_Suspend_Supported			booleanFieldType
+ */
+static void
+init_vif_component_usb_data_dfp_fields(struct vif_field_t *vif_fields)
 {
 	/*
-	 * 0 - Externally Powered
-	 * 1 - USB-powered
-	 * 2 - Both
+	 * TOTO(b:172438944) Adjust the speed based on CONFIG_
 	 */
-	int ps = 1;
+	enum usb_speed ds = USB_GEN11;
+	bool supports_usb_data;
+	bool is_dfp_on_hub;
 
-	if (CONFIG_DEDICATED_CHARGE_PORT_COUNT == 1)
-		ps = 0;
-
-	fprintf(vif, "Type_C_Power_Source: %d\r\n", ps);
-}
+	/*
+	 * The fields in this section shall be ignored by Testers unless
+	 * Connector_Type is set to 0 (Type-A), or
+	 * COnnector Type is set to 3 (Micro A/B); or
+	 * Connector_Type is set to 2 (Type-C) and Type_C_Can_Act_As_Host
+	 * is set to YES
+	 *
+	 * NOTE: We currently are always a Connector_Type of 2 (Type-C)
+	 */
+	if (!can_act_as_host())
+		return;
 
-static void write_type_c_port_on_hub(FILE *vif)
-{
-	fprintf(vif, "Type_C_Port_On_Hub: NO\r\n");
-}
+	supports_usb_data = does_support_host_usb_data();
+	set_vif_field_b(&vif_fields[Host_Supports_USB_Data],
+			vif_component_name[Host_Supports_USB_Data],
+			supports_usb_data);
+
+	if (supports_usb_data) {
+		switch (ds) {
+		case USB_2:
+			set_vif_field_itss(&vif_fields[Host_Speed],
+					   vif_component_name[Host_Speed],
+					   USB_2, "USB 2");
+			break;
+		case USB_GEN11:
+			set_vif_field_itss(&vif_fields[Host_Speed],
+					   vif_component_name[Host_Speed],
+					   USB_GEN11, "USB 3.2 Gen 1x1");
+			break;
+		case USB_GEN21:
+			set_vif_field_itss(&vif_fields[Host_Speed],
+					   vif_component_name[Host_Speed],
+					   USB_GEN21, "USB 3.2 Gen 2x1");
+			break;
+		case USB_GEN12:
+			set_vif_field_itss(&vif_fields[Host_Speed],
+					   vif_component_name[Host_Speed],
+					   USB_GEN12, "USB 3.2 Gen 1x2");
+			break;
+		case USB_GEN22:
+			set_vif_field_itss(&vif_fields[Host_Speed],
+					   vif_component_name[Host_Speed],
+					   USB_GEN22, "USB 3.2 Gen 2x2");
+			break;
+		}
 
-static void write_type_c_supports_audio_accessory(FILE *vif)
-{
-	fprintf(vif, "Type_C_Supports_Audio_Accessory: NO\r\n");
-}
+		if (!get_vif_field_tag_bool(&vif_fields[Type_C_Port_On_Hub],
+					    &is_dfp_on_hub))
+			is_dfp_on_hub = false;
 
-static void write_type_c_sources_vconn(FILE *vif)
-{
-	char *yn = "NO";
+		set_vif_field_b(&vif_fields[Is_DFP_On_Hub],
+				vif_component_name[Is_DFP_On_Hub],
+				is_dfp_on_hub);
 
-#ifdef CONFIG_USBC_VCONN
-	yn = "YES";
-#endif
+		set_vif_field_b(
+			&vif_fields[Host_Contains_Captive_Retimer],
+			vif_component_name[Host_Contains_Captive_Retimer],
+			false);
 
-	fprintf(vif, "Type_C_Source_Vconn: %s\r\n", yn);
+		set_vif_field_b(&vif_fields[Host_Is_Embedded],
+				vif_component_name[Host_Is_Embedded], false);
+	}
 }
 
-/*
- * USB Device Fields
+/*********************************************************************
+ * Init VIF/Component[] PD Source Fields
  */
-
-static void write_device_speed(FILE *vif)
+static int
+init_vif_component_pd_source_fields(struct vif_field_t *vif_fields,
+				    struct vif_srcPdoList_t *comp_src_pdo_list,
+				    int32_t *src_max_power, enum dtype type)
 {
-	/*
-	 * TODO(shurst): USB_2 might not be true for all boards and will need
-	 * changing for future board that implement USB_GENx.
-	 */
-	enum usb_speed speed = USB_2;
-
-	fprintf(vif, "Device_Speed: %d\r\n", speed);
-}
+	if (type == DRP || type == SRC) {
+		int i;
+		char str[40];
 
-/*
- * PD Source Fields
- */
-static int write_pd_source_fields(FILE *vif, enum dtype type)
-{
-	uint32_t max_power = 0;
-	char *pdo_buf = NULL;
-	int i;
-	int32_t pwr;
+		set_vif_field_b(&vif_fields[EPR_Supported_As_Src],
+				vif_component_name[EPR_Supported_As_Src],
+				false);
 
-	if (type == DRP || type == SRC) {
 		/* Source PDOs */
 		for (i = 0; i < src_pdo_cnt; i++) {
-			pwr = write_pdo_to_buf(&pdo_buf, src_pdo[i], SRC, i+1);
+			int32_t pwr;
+
+			pwr = init_vif_src_pdo(&comp_src_pdo_list[i],
+					       src_pdo[i]);
 			if (pwr < 0) {
-				fprintf(stderr, "ERROR: Out of memory.\n");
-				fclose(vif);
+				fprintf(stderr, "ERROR: Setting SRC PDO.\n");
 				return 1;
 			}
 
-			if (pwr > max_power)
-				max_power = pwr;
+			if (pwr > *src_max_power)
+				*src_max_power = pwr;
 		}
 
-		/* Source Fields */
-		fprintf(vif, "PD_Power_as_Source: %d\r\n", max_power);
-		fprintf(vif, "USB_Suspend_May_Be_Cleared: YES\r\n");
-		fprintf(vif, "Sends_Pings: NO\r\n");
-		fprintf(vif, "Num_Src_PDOs: %d\r\n", src_pdo_cnt);
+		sprintf(str, "%d mW", *src_max_power);
+		set_vif_field_itss(&vif_fields[PD_Power_As_Source],
+				   vif_component_name[PD_Power_As_Source],
+				   *src_max_power, str);
+	}
+
+	if (type == DRP || type == SRC)
+		set_vif_field_b(&vif_fields[USB_Suspend_May_Be_Cleared],
+				vif_component_name[USB_Suspend_May_Be_Cleared],
+				false);
+
+	if (type == DRP || type == SRC)
+		set_vif_field_b(&vif_fields[Sends_Pings],
+				vif_component_name[Sends_Pings], false);
+
+	if (IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE) && type == DRP &&
+	    IS_ENABLED(CONFIG_USB_PD_FRS))
+		set_vif_field(
+			&vif_fields
+				[FR_Swap_Type_C_Current_Capability_As_Initial_Sink],
+			vif_component_name
+				[FR_Swap_Type_C_Current_Capability_As_Initial_Sink],
+			"3", "3A @ 5V");
+	else
+		set_vif_field(
+			&vif_fields
+				[FR_Swap_Type_C_Current_Capability_As_Initial_Sink],
+			vif_component_name
+				[FR_Swap_Type_C_Current_Capability_As_Initial_Sink],
+			"0", "FR_Swap not supported");
+
+	if (IS_ENABLED(CONFIG_USB_PD_REV30) || IS_ENABLED(CONFIG_USB_PRL_SM))
+		set_vif_field_b(&vif_fields[Master_Port],
+				vif_component_name[Master_Port], false);
+
+	if (type == DRP || type == SRC)
+		set_vif_field_itss(&vif_fields[Num_Src_PDOs],
+				   vif_component_name[Num_Src_PDOs],
+				   src_pdo_cnt, NULL);
 
-		if (IS_ENABLED(CONFIG_USBC_PPC)) {
-			/*
-			 * 0 – Over-Current Response
-			 * 1 – Under-Voltage Response
-			 * 2 – Both
-			 */
+	if (type == DRP || type == SRC) {
+		if (IS_ENABLED(CONFIG_USBC_OCP)) {
 			int resp = 0;
 
-			fprintf(vif, "PD_OC_Protection: YES\r\n");
-			fprintf(vif, "PD_OCP_Method: %d\r\n", resp);
+			set_vif_field_b(&vif_fields[PD_OC_Protection],
+					vif_component_name[PD_OC_Protection],
+					true);
+
+			switch (resp) {
+			case 0:
+				set_vif_field(&vif_fields[PD_OCP_Method],
+					      vif_component_name[PD_OCP_Method],
+					      "0", "Over-Current Response");
+				break;
+			case 1:
+				set_vif_field(&vif_fields[PD_OCP_Method],
+					      vif_component_name[PD_OCP_Method],
+					      "1", "Under-Voltage Response");
+				break;
+			case 2:
+				set_vif_field(&vif_fields[PD_OCP_Method],
+					      vif_component_name[PD_OCP_Method],
+					      "2", "Both");
+				break;
+			default:
+				set_vif_field_itss(
+					&vif_fields[PD_OCP_Method],
+					vif_component_name[PD_OCP_Method], resp,
+					NULL);
+			}
 		} else {
-			fprintf(vif, "PD_OC_Protection: NO\r\n");
+			set_vif_field_b(&vif_fields[PD_OC_Protection],
+					vif_component_name[PD_OC_Protection],
+					false);
 		}
-
-		fprintf(vif, "\r\n%s\r\n", pdo_buf);
-		free(pdo_buf);
 	}
 
 	return 0;
 }
 
-/*
- * PD Sink Fields
+/*********************************************************************
+ * Init VIF/Component[] PD Sink Fields
  */
-static int write_pd_sink_fields(FILE *vif, enum dtype type)
+static int
+init_vif_component_pd_sink_fields(struct vif_field_t *vif_fields,
+				  struct vif_snkPdoList_t *comp_snk_pdo_list,
+				  enum dtype type)
 {
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-	uint32_t max_power = 0;
-	char *pdo_buf = NULL;
-	int32_t pwr;
 	int i;
-	char *giveback = "NO";
+	int32_t snk_max_power = 0;
+	char str[40];
 
-#ifdef CONFIG_USB_PD_GIVE_BACK
-	giveback = "YES";
-#endif
+	if (!IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE) || type == SRC)
+		return 0;
 
-	if (type == DRP || type == SNK) {
-		/* Sink PDOs */
-		for (i = 0; i < pd_snk_pdo_cnt; i++) {
-			pwr = write_pdo_to_buf(&pdo_buf,
-						pd_snk_pdo[i], SNK, i+1);
+	set_vif_field_c(&vif_fields[PD_Sink_Header], "PD Sink");
 
-			if (pwr < 0) {
-				fprintf(stderr, "ERROR: Out of memory.\n");
-				fclose(vif);
-				return 1;
-			}
+	set_vif_field_b(&vif_fields[EPR_Supported_As_Snk],
+			vif_component_name[EPR_Supported_As_Snk], false);
+
+	/* Sink PDOs */
+	for (i = 0; i < pd_snk_pdo_cnt; i++) {
+		int32_t pwr;
 
-			if (pwr > max_power)
-				max_power = pwr;
+		pwr = init_vif_snk_pdo(&comp_snk_pdo_list[i], pd_snk_pdo[i]);
+		if (pwr < 0) {
+			fprintf(stderr, "ERROR: Setting SNK PDO.\n");
+			return 1;
 		}
 
-		/* Sink Fields */
-		fprintf(vif, "PD_Power_as_Sink: %d\r\n", max_power);
-		fprintf(vif, "No_USB_Suspend_May_Be_Set: YES\r\n");
-		fprintf(vif, "GiveBack_May_Be_Set: %s\r\n", giveback);
-		fprintf(vif, "Higher_Capability_Set: NO\r\n");
-		fprintf(vif, "Num_Snk_PDOs: %d\r\n", pd_snk_pdo_cnt);
-		fprintf(vif, "\r\n%s\r\n", pdo_buf);
-		free(pdo_buf);
+		if (pwr > snk_max_power)
+			snk_max_power = pwr;
 	}
-#endif
+
+	sprintf(str, "%d mW", snk_max_power);
+	set_vif_field_itss(&vif_fields[PD_Power_As_Sink],
+			   vif_component_name[PD_Power_As_Sink], snk_max_power,
+			   str);
+
+	set_vif_field_b(&vif_fields[No_USB_Suspend_May_Be_Set],
+			vif_component_name[No_USB_Suspend_May_Be_Set], true);
+
+	set_vif_field_b(&vif_fields[GiveBack_May_Be_Set],
+			vif_component_name[GiveBack_May_Be_Set],
+			IS_ENABLED(CONFIG_USB_PD_GIVE_BACK));
+
+	set_vif_field_b(&vif_fields[Higher_Capability_Set],
+			vif_component_name[Higher_Capability_Set], false);
+
+	set_vif_field(
+		&vif_fields[FR_Swap_Reqd_Type_C_Current_As_Initial_Source],
+		vif_component_name[FR_Swap_Reqd_Type_C_Current_As_Initial_Source],
+		"0", "FR_Swap not supported");
+
+	set_vif_field_itss(&vif_fields[Num_Snk_PDOs],
+			   vif_component_name[Num_Snk_PDOs], pd_snk_pdo_cnt,
+			   NULL);
+
 	return 0;
 }
 
-/*
- * PD Dual Role Fields
+/*********************************************************************
+ * Init VIF/Component[] PD Dual Role Fields
  */
-static void write_pd_drp_fields(FILE *vif, enum dtype type)
+static void
+init_vif_component_pd_dual_role_fields(struct vif_field_t *vif_fields,
+				       enum dtype type)
 {
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-	if (type == DRP) {
-		/* Dual Role Fields */
-		fprintf(vif, "Accepts_PR_Swap_As_Src: YES\r\n");
-		fprintf(vif, "Accepts_PR_Swap_As_Snk: YES\r\n");
-		fprintf(vif, "Requests_PR_Swap_As_Src: YES\r\n");
-		fprintf(vif, "FR_Swap_Supported_As_Initial_Sink: NO\r\n");
+	if (!IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE) || type != DRP)
+		return;
+
+	set_vif_field_b(&vif_fields[Accepts_PR_Swap_As_Src],
+			vif_component_name[Accepts_PR_Swap_As_Src], true);
+
+	set_vif_field_b(&vif_fields[Accepts_PR_Swap_As_Snk],
+			vif_component_name[Accepts_PR_Swap_As_Snk], true);
+
+	set_vif_field_b(&vif_fields[Requests_PR_Swap_As_Src],
+			vif_component_name[Requests_PR_Swap_As_Src], true);
+
+	set_vif_field_b(&vif_fields[Requests_PR_Swap_As_Snk],
+			vif_component_name[Requests_PR_Swap_As_Snk], true);
+
+	set_vif_field_b(&vif_fields[FR_Swap_Supported_As_Initial_Sink],
+			vif_component_name[FR_Swap_Supported_As_Initial_Sink],
+			IS_ENABLED(CONFIG_USB_PD_FRS));
+}
+
+/*********************************************************************
+ * Init VIF/Component[] SOP Discovery Fields
+ *
+ * TODO: Generic todo to fill in additional fields as the need presents
+ * itself
+ *
+ * Fields that are not currently being initialized
+ *
+ * vif_Component
+ *	Product_Type_UFP_SOP			numericFieldType
+ *	Product_Type_DFP_SOP			numericFieldType
+ *	Modal_Operation_Supported_SOP		booleanFieldType
+ *	Num_SVIDs_Min_SOP			numericFieldType
+ *	Num_SVIDs_Max_SOP			numericFieldType
+ *	SVID_Fixed_SOP				booleanFieldType
+ */
+static void
+init_vif_component_sop_discovery_fields(struct vif_field_t *vif_fields)
+{
+	char hex_str[10];
+
+	/*
+	 * The fields in this section shall be ignored by Testers unless at
+	 * least one of Responds_To_Discov_SOP_UFP and
+	 * Responds_To_Discov_SOP_DFP is set to YES.
+	 */
+	if (!does_respond_to_discov_sop_ufp() &&
+	    !does_respond_to_discov_sop_dfp())
+		return;
+
+	set_vif_field(&vif_fields[XID_SOP], vif_component_name[XID_SOP], "0",
+		      NULL);
+
+	set_vif_field_b(&vif_fields[Data_Capable_As_USB_Host_SOP],
+			vif_component_name[Data_Capable_As_USB_Host_SOP],
+			can_act_as_host());
+
+	set_vif_field_b(&vif_fields[Data_Capable_As_USB_Device_SOP],
+			vif_component_name[Data_Capable_As_USB_Device_SOP],
+			can_act_as_device());
+
+	if (does_respond_to_discov_sop_dfp() &&
+	    IS_ENABLED(CONFIG_USB_PD_REV30)) {
+#if defined(CONFIG_USB_PD_PORT_LABEL)
+		set_vif_field_stis(&vif_fields[DFP_VDO_Port_Number],
+				   vif_component_name[DFP_VDO_Port_Number],
+				   NULL, CONFIG_USB_PD_PORT_LABEL);
+#else
+		set_vif_field_itss(&vif_fields[DFP_VDO_Port_Number],
+				   vif_component_name[DFP_VDO_Port_Number],
+				   component_index, NULL);
+#endif
 	}
+
+	sprintf(hex_str, "%04X", USB_VID_GOOGLE);
+	set_vif_field_itss(&vif_fields[USB_VID_SOP],
+			   vif_component_name[USB_VID_SOP], USB_VID_GOOGLE,
+			   hex_str);
+
+#if defined(CONFIG_USB_PID)
+	sprintf(hex_str, "%04X", CONFIG_USB_PID);
+	set_vif_field_itss(&vif_fields[PID_SOP], vif_component_name[PID_SOP],
+			   CONFIG_USB_PID, hex_str);
+#else
+	sprintf(hex_str, "%04X", DEFAULT_MISSING_PID);
+	set_vif_field_itss(&vif_fields[PID_SOP], vif_component_name[PID_SOP],
+			   DEFAULT_MISSING_PID, hex_str);
+#endif
+
+#if defined(CONFIG_USB_BCD_DEV)
+	sprintf(hex_str, "%04X", CONFIG_USB_BCD_DEV);
+	set_vif_field_itss(&vif_fields[bcdDevice_SOP],
+			   vif_component_name[bcdDevice_SOP],
+			   CONFIG_USB_BCD_DEV, hex_str);
+#else
+	sprintf(hex_str, "%04X", DEFAULT_MISSING_BCD_DEV);
+	set_vif_field_itss(&vif_fields[bcdDevice_SOP],
+			   vif_component_name[bcdDevice_SOP],
+			   DEFAULT_MISSING_BCD_DEV, hex_str);
 #endif
 }
 
-/**
- * Carriage and line feed, '\r\n', is needed because the file is processed
- * on a Windows machine.
+/*********************************************************************
+ * Init VIF/Component[] Battery Charging 1.2 Fields
  */
-static int gen_vif(const char *name, const char *board,
-					const char *vif_producer)
+static void init_vif_component_bc_1_2_fields(struct vif_field_t *vif_fields,
+					     enum bc_1_2_support bc_support)
+{
+	if (bc_support == BC_1_2_SUPPORT_CHARGING_PORT ||
+	    bc_support == BC_1_2_SUPPORT_BOTH)
+		set_vif_field(&vif_fields[BC_1_2_Charging_Port_Type],
+			      vif_component_name[BC_1_2_Charging_Port_Type],
+			      "1", "CDP");
+}
+
+/*********************************************************************
+ * Init VIF/Component[] Product Power Fields
+ *
+ * TODO: Generic todo to fill in additional fields as the need presents
+ * itself
+ *
+ * Fields that are not currently being initialized
+ *
+ * vif_Component
+ *	Port_Source_Power_Gang			nonEmptyString
+ *	Port_Source_Power_Gang_Max_Power	numericFieldType
+ */
+static void
+init_vif_component_product_power_fields(struct vif_field_t *vif_fields,
+					int32_t src_max_power, enum dtype type)
 {
-	FILE *vif;
-	enum dtype type;
+	if (type == DRP || type == SRC) {
+		char str[14];
 
-	if (is_drp())
-		type = DRP;
-	else if (is_src() && is_snk())
-		/* No DRP with SRC and SNK PDOs detected. So ignore. */
-		/* ie. Twinkie or Plankton */
-		return 0;
-	else if (is_src())
-		type = SRC;
-	else if (is_snk())
-		type = SNK;
-	else
-		return 1;
+		sprintf(str, "%d mW", src_max_power);
+		set_vif_field_itss(
+			&vif_fields[Product_Total_Source_Power_mW],
+			vif_component_name[Product_Total_Source_Power_mW],
+			src_max_power, str);
+	}
 
-	/*
-	 * Create VIF
-	 */
-	vif = fopen(name, "w+");
-	if (vif == NULL)
-		return 1;
+	if (type == DRP || type == SRC)
+		set_vif_field(&vif_fields[Port_Source_Power_Type],
+			      vif_component_name[Port_Source_Power_Type], "0",
+			      "Assured");
+}
 
-	/*
-	 * Write VIF Title
-	 */
-	write_title(vif);
+static void init_remarks(struct vif_t *vif)
+{
+	struct vif_field_t *vif_fields;
+	int max_component_index = board_get_usb_pd_port_count();
 
-	/*
-	 * Write Intro Fields comment
-	 */
-	write_field(vif, INTRO);
+	for (int c = 0; c < max_component_index; ++c) {
+		vif_fields = vif->Component[c].vif_field;
 
-	write_vif_specification(vif);
-	write_vif_producer(vif, vif_producer);
-	write_vendor_name(vif);
-	write_model_part_number(vif);
-	write_product_revision(vif);
-	write_tid(vif);
+		set_vif_field_c(&vif_fields[Component_Header], "Component");
+		set_vif_field_c(&vif_fields[General_PD_Header], "General PD");
+		set_vif_field_c(&vif_fields[PD_Capabilities_Header],
+				"PD Capabilities");
 
-	/*
-	 * Write VIF Product Fields
-	 */
-	write_field(vif, PRODUCT);
+		set_vif_field_c(&vif_fields[USB_Type_C_Header],
+				"USB Type-C\u00ae");
 
-	write_vif_product_type(vif);
-	write_port_label(vif);
-	write_connector_type(vif);
-	write_usb_pd_support(vif);
-	write_pd_port_type(vif, type);
-	write_type_c_state_machine(vif, type);
-	write_captive_cable(vif);
-	write_port_battery_powered(vif);
-	write_bc_1_2_support(vif, type);
+		set_vif_field_c(&vif_fields[Product_Power_Header],
+				"Product Power");
 
+		set_vif_field_c(&vif_fields[USB_Host_Header], "USB Host");
 
-	/*
-	 * Write General PD Fields
-	 */
-	write_field(vif, GENERAL);
-
-	write_pd_spec_rev(vif);
-	write_usb_comms_capable(vif);
-	write_dr_swap_to_dfp_supported(vif);
-	write_dr_swap_to_ufp_supported(vif);
-	write_unconstrained_power(vif);
-	write_vconn_swap_to_on_supported(vif);
-	write_vconn_swap_to_off_supported(vif);
-	write_responds_to_discov_sop_ufp(vif);
-	write_responds_to_discov_sop_dfp(vif);
-	write_attempts_discov_sop(vif, type);
-	write_chunking_implemented_sop(vif);
-	write_unchunked_extended_messages_supported(vif);
-	write_manufacturer_info_supported_port(vif);
-	write_manufacturer_info_pid_port(vif);
-	write_security_msgs_supported_sop(vif);
-	write_num_fixed_batteries(vif);
-	write_num_swappable_battery_slots(vif);
-	write_sop_capable(vif);
-	write_sop_p_capable(vif);
-	write_sop_pp_capable(vif);
-	write_sop_p_debug_capable(vif);
-	write_sop_pp_debug_capable(vif);
+		set_vif_field_c(&vif_fields[BC_1_2_Header],
+				"Battery Charging 1.2");
 
-	/*
-	 * Write USB Type-C Fields
-	 */
-	write_field(vif, USB);
-
-	write_type_c_implements_try_src(vif);
-	write_type_c_implements_try_snk(vif);
-	write_rp_value(vif);
-	write_type_c_supports_vconn_powered_accessory(vif);
-	write_type_c_is_debug_target_src(vif);
-	write_type_c_is_debug_target_snk(vif);
-	write_type_c_can_act_as_host(vif);
-	write_type_c_is_alt_mode_controller(vif);
-	write_type_c_can_act_as_device(vif);
-	write_type_c_is_alt_mode_adapter(vif);
-	write_type_c_power_source(vif);
-	write_type_c_port_on_hub(vif);
-	write_type_c_supports_audio_accessory(vif);
-	write_type_c_sources_vconn(vif);
+		set_vif_field_c(&vif_fields[PD_Source_Header], "PD Source");
 
+		set_vif_field_c(&vif_fields[Dual_Role_Header], "Dual Role");
 
-	/*
-	 * Write USB Device Fields
-	 */
-	write_field(vif, DEVICE);
+		set_vif_field_c(&vif_fields[SOP_Discover_ID_Header],
+				"SOP Discover ID");
+	}
+}
 
-	write_device_speed(vif);
+static int gen_vif(const char *board, struct vif_t *vif)
+{
+	int max_component_index = board_get_usb_pd_port_count();
 
-	/*
-	 * Write PD Source Fields
+	/*********************************************************************
+	 * Initialize the vif structure
 	 */
-	write_field(vif, SOURCE);
+	init_vif_fields(vif->vif_field, vif->vif_app_field, board);
+
+	for (component_index = 0; component_index < max_component_index;
+	     component_index++) {
+		int override_value;
+		bool was_overridden;
+		enum dtype type;
+		int32_t src_max_power = 0;
+		enum bc_1_2_support bc_support = BC_1_2_SUPPORT_NONE;
+
+		/* Determine if we are DRP, SRC or SNK */
+		was_overridden = get_vif_field_tag_number(
+			&vif->Component[component_index]
+				 .vif_field[Type_C_State_Machine],
+			&override_value);
+		if (was_overridden) {
+			switch (override_value) {
+			case SRC:
+			case SNK:
+			case DRP:
+				type = (enum dtype)override_value;
+				break;
+			default:
+				was_overridden = false;
+			}
+		}
+		if (!was_overridden) {
+			was_overridden = get_vif_field_tag_number(
+				&vif->Component[component_index]
+					 .vif_field[PD_Port_Type],
+				&override_value);
+			if (was_overridden) {
+				switch (override_value) {
+				case PORT_CONSUMER_ONLY: /* SNK */
+					type = SNK;
+					break;
+				case PORT_PROVIDER_ONLY: /* SRC */
+					type = SRC;
+					break;
+				case PORT_DRP: /* DRP */
+					type = DRP;
+					break;
+				default:
+					was_overridden = false;
+				}
+			}
+		}
+		if (!was_overridden) {
+			if (is_drp())
+				type = DRP;
+			else if (is_src() && is_snk())
+				/*
+				 * No DRP with SRC and SNK PDOs detected. So
+				 * ignore.  ie. Twinkie or Plankton
+				 */
+				return 0;
+			else if (is_src())
+				type = SRC;
+			else if (is_snk())
+				type = SNK;
+			else
+				return 1;
+		}
 
-	write_pd_source_fields(vif, type);
+		init_vif_component_fields(
+			vif->Component[component_index].vif_field, &bc_support,
+			type);
 
-	/*
-	 * Write PD Sink Fields
-	 */
-	write_field(vif, SINK);
+		init_vif_component_general_pd_fields(
+			vif->Component[component_index].vif_field, type);
 
-	write_pd_sink_fields(vif, type);
+		init_vif_component_sop_capabilities_fields(
+			vif->Component[component_index].vif_field);
 
+		init_vif_component_usb_type_c_fields(
+			vif->Component[component_index].vif_field, type);
 
-	/*
-	 * Write DRP Fields
-	 */
-	write_field(vif, DUAL_ROLE);
+		init_vif_component_usb4_port_fields(
+			vif->Component[component_index].vif_field);
 
-	write_pd_drp_fields(vif, type);
+		init_vif_component_usb_data_ufp_fields(
+			vif->Component[component_index].vif_field);
 
-	/*
-	 * Battery Charging 1.2 Fields
-	 */
-	write_field(vif, BC12);
+		init_vif_component_usb_data_dfp_fields(
+			vif->Component[component_index].vif_field);
+
+		if (init_vif_component_pd_source_fields(
+			    vif->Component[component_index].vif_field,
+			    vif->Component[component_index].SrcPdoList,
+			    &src_max_power, type))
+			return 1;
+
+		if (init_vif_component_pd_sink_fields(
+			    vif->Component[component_index].vif_field,
+			    vif->Component[component_index].SnkPdoList, type))
+			return 1;
+
+		init_vif_component_pd_dual_role_fields(
+			vif->Component[component_index].vif_field, type);
+
+		init_vif_component_sop_discovery_fields(
+			vif->Component[component_index].vif_field);
+
+		init_vif_component_bc_1_2_fields(
+			vif->Component[component_index].vif_field, bc_support);
+
+		init_vif_component_product_power_fields(
+			vif->Component[component_index].vif_field,
+			src_max_power, type);
+	}
 
-	fclose(vif);
 	return 0;
 }
+/*
+ * VIF Structure Initialization from Config Functions
+ *****************************************************************************/
 
 int main(int argc, char **argv)
 {
@@ -1068,26 +3868,28 @@ int main(int argc, char **argv)
 	int ret;
 	const char *out = NULL;
 	const char *board = NULL;
-	const char *vif_producer;
+	bool do_config_init = true;
 	DIR *vifdir;
 	char *name;
 	int name_size;
-	const char * const short_opt = "hb:o:";
+	const char *const short_opt = "hb:o:nv:";
 	const struct option long_opts[] = {
-		{ "help", 0, NULL, 'h' },
-		{ "board", 1, NULL, 'b' },
-		{ "out", 1, NULL, 'o' },
-		{ NULL }
+		{ "help", 0, NULL, 'h' }, { "board", 1, NULL, 'b' },
+		{ "out", 1, NULL, 'o' },  { "no-config", 0, NULL, 'n' },
+		{ "over", 1, NULL, 'v' }, { NULL }
 	};
 
-	vif_producer = argv[0];
+	/* Clear the VIF structure */
+	memset(&vif, 0, sizeof(struct vif_t));
 
 	do {
 		nopt = getopt_long(argc, argv, short_opt, long_opts, NULL);
 		switch (nopt) {
 		case 'h': /* -h or --help */
-			printf("USAGE: %s -b <board name> -o <out directory>\n",
-					vif_producer);
+			printf("USAGE: genvif -b|--board <board name>\n"
+			       "              -o|--out <out directory>\n"
+			       "              [-n|--no-config]\n"
+			       "              [-v|--over <override XML file>]\n");
 			return 1;
 
 		case 'b': /* -b or --board */
@@ -1097,6 +3899,17 @@ int main(int argc, char **argv)
 		case 'o': /* -o or --out */
 			out = optarg;
 			break;
+
+		case 'n': /* -n or --no-config */
+			do_config_init = false;
+			break;
+
+		case 'v': /* -v or --over */
+			/* Handle overrides */
+			if (override_gen_vif(optarg, &vif))
+				return 1;
+			break;
+
 		case -1:
 			break;
 
@@ -1118,15 +3931,24 @@ int main(int argc, char **argv)
 
 	init_src_pdos();
 
-	name_size = asprintf(&name, "%s/%s_vif.txt", out, board);
+	init_remarks(&vif);
+
+	/* Finish CONFIG initialization file */
+	if (do_config_init) {
+		ret = gen_vif(board, &vif);
+		if (ret)
+			return 1;
+	}
+
+	name_size = asprintf(&name, "%s/%s_vif.xml", out, board);
 	if (name_size < 0) {
 		fprintf(stderr, "ERROR: Out of memory.\n");
 		return 1;
 	}
 
-	ret = gen_vif(name, board, vif_producer);
+	/* Format the structure in XML and output it to file */
+	ret = vif_output_xml(name, &vif);
 
 	free(name);
-
 	return ret;
 }
diff --git a/util/genvif.h b/util/genvif.h
new file mode 100644
index 0000000000..448d8bfb43
--- /dev/null
+++ b/util/genvif.h
@@ -0,0 +1,488 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#ifndef __GENVIF_H__
+#define __GENVIF_H__
+
+#define MAX_NUM_CABLE_SVIDS 10
+#define MAX_NUM_CABLE_SVID_MODES 10
+#define MAX_NUM_COMPONENTS 10
+#define MAX_NUM_PCIE_ENDPOINTS 10
+#define MAX_NUM_SNK_PDOS 10
+#define MAX_NUM_SRC_PDOS 10
+#define MAX_NUM_SOP_SVIDS 10
+#define MAX_NUM_SOP_SVID_MODES 10
+#define MAX_NUM_USB4_ROUTERS 16
+
+struct vif_field_t {
+	const char *name;
+	char *tag_value;
+	char *str_value;
+};
+
+/* 3.2.15.2 Cable SVID Modes */
+
+enum vif_cableSVIDModeList_indexes {
+	SVID_Mode_Enter, /* booleanFieldType */
+	SVID_Mode_Recog_Mask, /* numericFieldType */
+	SVID_Mode_Recog_Value, /* numericFieldType */
+	CableSVID_Mode_Indexes
+};
+
+struct vif_cableSVIDModeList_t {
+	struct vif_field_t vif_field[CableSVID_Mode_Indexes];
+};
+
+/* 3.2.15.1 Cable SVIDs */
+
+enum vif_cableSVIDList_indexes {
+	SVID, /* numericFieldType */
+	SVID_Num_Modes_Min, /* numericFieldType */
+	SVID_Num_Modes_Max, /* numericFieldType */
+	SVID_Modes_Fixed, /* booleanFieldType */
+	CableSVID_Indexes
+};
+
+struct vif_cableSVIDList_t {
+	struct vif_field_t vif_field[CableSVID_Indexes];
+
+	struct vif_cableSVIDModeList_t
+		CableSVIDModeList[MAX_NUM_CABLE_SVID_MODES];
+};
+
+/* 3.2.12.2 SOP SVID Modes */
+
+enum vif_sopSVIDModeList_indexes {
+	SVID_Mode_Enter_SOP, /* booleanFieldType */
+	SVID_Mode_Recog_Mask_SOP, /* numericFieldType */
+	SVID_Mode_Recog_Value_SOP, /* numericFieldType */
+	SopSVID_Mode_Indexes
+};
+
+struct vif_sopSVIDModeList_t {
+	struct vif_field_t vif_field[SopSVID_Mode_Indexes];
+};
+
+/* 3.2.12.1 SOP SVIDs */
+
+enum vif_sopSVIDList_indexes {
+	SVID_SOP, /* numericFieldType */
+	SVID_Num_Modes_Min_SOP, /* numericFieldType */
+	SVID_Num_Modes_Max_SOP, /* numericFieldType */
+	SVID_Modes_Fixed_SOP, /* booleanFieldType */
+	SopSVID_Indexes
+};
+
+struct vif_sopSVIDList_t {
+	struct vif_field_t vif_field[SopSVID_Indexes];
+
+	struct vif_sopSVIDModeList_t SOPSVIDModeList[MAX_NUM_SOP_SVID_MODES];
+};
+
+/* 3.2.10.1 Sink PDOs */
+
+enum vif_snkPdoList_indexes {
+	Snk_PDO_Supply_Type, /* numericFieldType */
+	Snk_PDO_APDO_Type, /* numericFieldType */
+	Snk_PDO_Voltage, /* numericFieldType */
+	Snk_PDO_PDP_Rating, /* numericFieldType */
+	Snk_PDO_Op_Power, /* numericFieldType */
+	Snk_PDO_Min_Voltage, /* numericFieldType */
+	Snk_PDO_Max_Voltage, /* numericFieldType */
+	Snk_PDO_Op_Current, /* numericFieldType */
+	Snk_PDO_Indexes
+};
+
+struct vif_snkPdoList_t {
+	struct vif_field_t vif_field[Snk_PDO_Indexes];
+};
+
+/* 3.2.9.1 Source PDOs */
+
+enum vif_srcPdoList_indexes {
+	Src_PDO_Supply_Type, /* numericFieldType */
+	Src_PDO_APDO_Type, /* numericFieldType */
+	Src_PDO_Peak_Current, /* numericFieldType */
+	Src_PDO_Voltage, /* numericFieldType */
+	Src_PDO_Max_Current, /* numericFieldType */
+	Src_PDO_Min_Voltage, /* numericFieldType */
+	Src_PDO_Max_Voltage, /* numericFieldType */
+	Src_PDO_Max_Power, /* numericFieldType */
+	Src_PD_OCP_OC_Debounce, /* numericFieldType */
+	Src_PD_OCP_OC_Threshold, /* numericFieldType */
+	Src_PD_OCP_UV_Debounce, /* numericFieldType */
+	Src_PD_OCP_UV_Threshold_Type, /* numericFieldType */
+	Src_PD_OCP_UV_Threshold, /* numericFieldType */
+	Src_PDO_Indexes
+};
+
+struct vif_srcPdoList_t {
+	struct vif_field_t vif_field[Src_PDO_Indexes];
+};
+
+/* 3.2.2.1.3 PCIe Endpoint Fields */
+
+enum vif_PCIeEndpointListType_indexes {
+	USB4_PCIe_Endpoint_Vendor_ID, /* numericFieldType */
+	USB4_PCIe_Endpoint_Device_ID, /* numericFieldType */
+	USB4_PCIe_Endpoint_Class_Code, /* numericFieldType */
+	PCIe_Endpoint_Indexes
+};
+
+struct vif_PCIeEndpointListType_t {
+	struct vif_field_t vif_field[PCIe_Endpoint_Indexes];
+};
+
+/* 3.2.2.1.2 USB4 Router Fields */
+
+enum vif_Usb4RouterListType_indexes {
+	USB4_Router_ID, /* numericFieldType */
+	USB4_Silicon_VID, /* numericFieldType */
+	USB4_Num_Lane_Adapters, /* numericFieldType */
+	USB4_Num_USB3_DN_Adapters, /* numericFieldType */
+	USB4_Num_DP_IN_Adapters, /* numericFieldType */
+	USB4_Num_DP_OUT_Adapters, /* numericFieldType */
+	USB4_Num_PCIe_DN_Adapters, /* numericFieldType */
+	USB4_TBT3_Not_Supported, /* numericFieldType */
+	USB4_PCIe_Wake_Supported, /* booleanFieldType */
+	USB4_USB3_Wake_Supported, /* booleanFieldType */
+	USB4_Num_Unused_Adapters, /* numericFieldType */
+	USB4_TBT3_VID, /* numericFieldType */
+	USB4_PCIe_Switch_Vendor_ID, /* numericFieldType */
+	USB4_PCIe_Switch_Device_ID, /* numericFieldType */
+	USB4_Num_PCIe_Endpoints, /* numericFieldType */
+	USB4_Router_Indexes
+};
+
+struct vif_Usb4RouterListType_t {
+	struct vif_field_t vif_field[USB4_Router_Indexes];
+
+	struct vif_PCIeEndpointListType_t
+		PCIeEndpointList[MAX_NUM_PCIE_ENDPOINTS];
+};
+
+/* 3.2.3 Component Fields */
+
+enum vif_Component_indexes {
+	Component_Header, /* comment */
+	Port_Label, /* nonEmptyString */
+	Connector_Type, /* numericFieldType */
+	USB4_Supported, /* booleanFieldType */
+	USB4_Router_Index, /* numericFieldType */
+	USB_PD_Support, /* booleanFieldType */
+	PD_Port_Type, /* numericFieldType */
+	Type_C_State_Machine, /* numericFieldType */
+	Port_Battery_Powered, /* booleanFieldType */
+	BC_1_2_Support, /* numericFieldType */
+	Captive_Cable, /* booleanFieldType */
+	Captive_Cable_Is_eMarked, /* booleanFieldType */
+
+	/* 3.2.4 General PD Fields */
+	General_PD_Header, /* comment */
+	PD_Spec_Revision_Major, /* numericFieldType */
+	PD_Spec_Revision_Minor, /* numericFieldType */
+	PD_Spec_Version_Major, /* numericFieldType */
+	PD_Spec_Version_Minor, /* numericFieldType */
+	PD_Specification_Revision, /* numericFieldType */
+
+	/* 3.2.4.1 SOP* Capabilities */
+	SOP_Capable, /* booleanFieldType */
+	SOP_P_Capable, /* booleanFieldType */
+	SOP_PP_Capable, /* booleanFieldType */
+	SOP_P_Debug_Capable, /* booleanFieldType */
+	SOP_PP_Debug_Capable, /* booleanFieldType */
+
+	Manufacturer_Info_Supported_Port, /* booleanFieldType */
+	Manufacturer_Info_VID_Port, /* numericFieldType */
+	Manufacturer_Info_PID_Port, /* numericFieldType */
+	Chunking_Implemented_SOP, /* booleanFieldType */
+	Unchunked_Extended_Messages_Supported, /* booleanFieldType */
+	Security_Msgs_Supported_SOP, /* booleanFieldType */
+	Unconstrained_Power, /* booleanFieldType */
+	Num_Fixed_Batteries, /* numericFieldType */
+	Num_Swappable_Battery_Slots, /* numericFieldType */
+	ID_Header_Connector_Type_SOP, /* numericFieldType */
+
+	/* 3.2.4 General PD Fields */
+	PD_Capabilities_Header, /* comment */
+	USB_Comms_Capable, /* booleanFieldType */
+	DR_Swap_To_DFP_Supported, /* booleanFieldType */
+	DR_Swap_To_UFP_Supported, /* booleanFieldType */
+	VCONN_Swap_To_On_Supported, /* booleanFieldType */
+	VCONN_Swap_To_Off_Supported, /* booleanFieldType */
+	Responds_To_Discov_SOP_UFP, /* booleanFieldType */
+	Responds_To_Discov_SOP_DFP, /* booleanFieldType */
+	Attempts_Discov_SOP, /* booleanFieldType */
+	Power_Interruption_Available, /* numericFieldType */
+	Data_Reset_Supported, /* booleanFieldType */
+	Enter_USB_Supported, /* booleanFieldType */
+
+	/* 3.2.5 USB Type-C Fields */
+	USB_Type_C_Header, /* comment */
+	Type_C_Can_Act_As_Host, /* booleanFieldType */
+	Type_C_Can_Act_As_Device, /* booleanFieldType */
+
+	/* 3.2.5 USB Type-C Fields */
+	Type_C_Implements_Try_SRC, /* booleanFieldType */
+	Type_C_Implements_Try_SNK, /* booleanFieldType */
+	Type_C_Supports_Audio_Accessory, /* booleanFieldType */
+	Type_C_Is_VCONN_Powered_Accessory, /* booleanFieldType */
+	Type_C_Is_Debug_Target_SRC, /* booleanFieldType */
+	Type_C_Is_Debug_Target_SNK, /* booleanFieldType */
+	RP_Value, /* numericFieldType */
+	Type_C_Supports_VCONN_Powered_Accessory, /* booleanFieldType */
+	Type_C_Port_On_Hub, /* booleanFieldType */
+	Type_C_Power_Source, /* numericFieldType */
+	Type_C_Sources_VCONN, /* booleanFieldType */
+	Type_C_Is_Alt_Mode_Controller, /* booleanFieldType */
+	Type_C_Is_Alt_Mode_Adapter, /* booleanFieldType */
+
+	/* 3.2.6 USB4 Port Fields (missing from output) */
+	USB4_Port_Header, /* comment */
+	USB4_Lane_0_Adapter, /* numericFieldType */
+	USB4_Max_Speed, /* numericFieldType */
+	USB4_DFP_Supported, /* booleanFieldType */
+	USB4_UFP_Supported, /* booleanFieldType */
+	USB4_USB3_Tunneling_Supported, /* booleanFieldType */
+	USB4_DP_Tunneling_Supported, /* booleanFieldType */
+	USB4_PCIe_Tunneling_Supported, /* booleanFieldType */
+	USB4_TBT3_Compatibility_Supported, /* booleanFieldType */
+	USB4_CL1_State_Supported, /* booleanFieldType */
+	USB4_CL2_State_Supported, /* booleanFieldType */
+	USB4_Num_Retimers, /* numericFieldType */
+	USB4_DP_Bit_Rate, /* numericFieldType */
+	USB4_Num_DP_Lanes, /* numericFieldType */
+
+	/* 3.2.7 USB Data - Upstream Facing Port Fields */
+	Device_Supports_USB_Data, /* booleanFieldType */
+	Device_Speed, /* numericFieldType */
+	Device_Contains_Captive_Retimer, /* booleanFieldType */
+	Device_Truncates_DP_For_tDHPResponse, /* booleanFieldType */
+	Device_Gen1x1_tLinkTurnaround, /* numericFieldType */
+	Device_Gen2x1_tLinkTurnaround, /* numericFieldType */
+
+	/* 3.2.19 Product Power Fields */
+	Product_Power_Header, /* comment */
+	Product_Total_Source_Power_mW, /* numericFieldType */
+	Port_Source_Power_Type, /* numericFieldType */
+	Port_Source_Power_Gang, /* nonEmptyString */
+	Port_Source_Power_Gang_Max_Power, /* numericFieldType */
+
+	/* 3.2.8 USB Data - Downstream Facing Port Fields */
+	USB_Host_Header, /* comment */
+	Host_Supports_USB_Data, /* booleanFieldType */
+	Host_Speed, /* numericFieldType */
+	Host_Contains_Captive_Retimer, /* booleanFieldType */
+	Host_Truncates_DP_For_tDHPResponse, /* booleanFieldType */
+	Host_Gen1x1_tLinkTurnaround, /* numericFieldType */
+	Host_Gen2x1_tLinkTurnaround, /* numericFieldType */
+	Host_Is_Embedded, /* booleanFieldType */
+	Host_Suspend_Supported, /* booleanFieldType */
+	Is_DFP_On_Hub, /* booleanFieldType */
+	Hub_Port_Number, /* numericFieldType */
+
+	/* 3.2.14 Battery Charging 1.2 Fields */
+	BC_1_2_Header, /* comment */
+	BC_1_2_Charging_Port_Type, /* numericFieldType */
+
+	/* 3.2.9 PD Source Fields */
+	PD_Source_Header, /* comment */
+	PD_Power_As_Source, /* numericFieldType */
+	EPR_Supported_As_Src, /* booleanFieldType */
+	USB_Suspend_May_Be_Cleared, /* booleanFieldType */
+	Sends_Pings, /* booleanFieldType */
+	FR_Swap_Type_C_Current_Capability_As_Initial_Sink, /* numericFieldType
+							    */
+	Master_Port, /* booleanFieldType */
+	Num_Src_PDOs, /* numericFieldType */
+	PD_OC_Protection, /* booleanFieldType */
+	PD_OCP_Method, /* numericFieldType */
+
+	/* insert: SrcPdoList */
+
+	/* 3.2.10 PD Sink Fields */
+	PD_Sink_Header, /* comment */
+	PD_Power_As_Sink, /* numericFieldType */
+	EPR_Supported_As_Snk, /* booleanFieldType */
+	No_USB_Suspend_May_Be_Set, /* booleanFieldType */
+	GiveBack_May_Be_Set, /* booleanFieldType */
+	Higher_Capability_Set, /* booleanFieldType */
+	FR_Swap_Reqd_Type_C_Current_As_Initial_Source, /* numericFieldType */
+	Num_Snk_PDOs, /* numericFieldType */
+
+	/* insert: SnkPdoList */
+
+	/* 3.2.11 PD Dual Role Fields */
+	Dual_Role_Header, /* comment */
+	Accepts_PR_Swap_As_Src, /* booleanFieldType */
+	Accepts_PR_Swap_As_Snk, /* booleanFieldType */
+	Requests_PR_Swap_As_Src, /* booleanFieldType */
+	Requests_PR_Swap_As_Snk, /* booleanFieldType */
+	FR_Swap_Supported_As_Initial_Sink, /* booleanFieldType */
+
+	/* 3.2.12 SOP Discover ID Fields */
+	SOP_Discover_ID_Header, /* comment */
+	XID_SOP, /* numericFieldType */
+	Data_Capable_As_USB_Host_SOP, /* booleanFieldType */
+	Data_Capable_As_USB_Device_SOP, /* booleanFieldType */
+	Product_Type_UFP_SOP, /* numericFieldType */
+	Product_Type_DFP_SOP, /* numericFieldType */
+	DFP_VDO_Port_Number, /* numericFieldType */
+	Modal_Operation_Supported_SOP, /* booleanFieldType */
+	USB_VID_SOP, /* numericFieldType */
+	PID_SOP, /* numericFieldType */
+	bcdDevice_SOP, /* numericFieldType */
+	Num_SVIDs_Min_SOP, /* numericFieldType */
+	Num_SVIDs_Max_SOP, /* numericFieldType */
+	SVID_Fixed_SOP, /* booleanFieldType */
+
+	/* 3.2.13 Alternate Mode Adapter (AMA) Fields */
+	AMA_HW_Vers, /* numericFieldType */
+	AMA_FW_Vers, /* numericFieldType */
+	AMA_VCONN_Power, /* booleanFieldType */
+	AMA_VCONN_Reqd, /* booleanFieldType */
+	AMA_VBUS_Reqd, /* booleanFieldType */
+	AMA_Superspeed_Support, /* numericFieldType */
+
+	/* 3.2.15 Cable/eMarker Fields */
+	XID, /* numericFieldType */
+	Data_Capable_As_USB_Host, /* booleanFieldType */
+	Data_Capable_As_USB_Device, /* booleanFieldType */
+	Product_Type, /* numericFieldType */
+	Modal_Operation_Supported, /* booleanFieldType */
+	USB_VID, /* numericFieldType */
+	PID, /* numericFieldType */
+	bcdDevice, /* numericFieldType */
+	Cable_HW_Vers, /* numericFieldType */
+	Cable_FW_Vers, /* numericFieldType */
+	Type_C_To_Type_A_B_C, /* numericFieldType */
+	Type_C_To_Type_C_Capt_Vdm_V2, /* numericFieldType */
+	EPR_Mode_Capable, /* booleanFieldType */
+	Cable_Latency, /* numericFieldType */
+	Cable_Termination_Type, /* numericFieldType */
+	Cable_VBUS_Current, /* numericFieldType */
+	VBUS_Through_Cable, /* booleanFieldType */
+	Cable_Superspeed_Support, /* numericFieldType */
+	Cable_USB_Highest_Speed, /* numericFieldType */
+	Max_VBUS_Voltage_Vdm_V2, /* numericFieldType */
+	Manufacturer_Info_Supported, /* booleanFieldType */
+	Manufacturer_Info_VID, /* numericFieldType */
+	Manufacturer_Info_PID, /* numericFieldType */
+	Chunking_Implemented, /* booleanFieldType */
+	Security_Msgs_Supported, /* booleanFieldType */
+	ID_Header_Connector_Type, /* numericFieldType */
+	Cable_Num_SVIDs_Min, /* numericFieldType */
+	Cable_Num_SVIDs_Max, /* numericFieldType */
+	SVID_Fixed, /* booleanFieldType */
+
+	/* 3.2.16 Active Cable Fields */
+	Cable_SOP_PP_Controller, /* booleanFieldType */
+	SBU_Supported, /* booleanFieldType */
+	SBU_Type, /* numericFieldType */
+	Active_Cable_Max_Operating_Temp, /* numericFieldType */
+	Active_Cable_Shutdown_Temp, /* numericFieldType */
+	Active_Cable_U3_CLd_Power, /* numericFieldType */
+	Active_Cable_U3_U0_Trans_Mode, /* numericFieldType */
+	Active_Cable_Physical_Connection, /* numericFieldType */
+	Active_Cable_Active_Element, /* numericFieldType */
+	Active_Cable_USB4_Support, /* booleanFieldType */
+	Active_Cable_USB2_Supported, /* booleanFieldType */
+	Active_Cable_USB2_Hub_Hops_Consumed, /* numericFieldType */
+	Active_Cable_USB32_Supported, /* booleanFieldType */
+	Active_Cable_USB_Lanes, /* numericFieldType */
+	Active_Cable_Optically_Isolated, /* booleanFieldType */
+	Active_Cable_USB_Gen, /* numericFieldType */
+
+	/* 3.2.17 VCONN Powered Devices */
+	VPD_HW_Vers, /* numericFieldType */
+	VPD_FW_Vers, /* numericFieldType */
+	VPD_Max_VBUS_Voltage, /* numericFieldType */
+	VPD_Charge_Through_Support, /* booleanFieldType */
+	VPD_Charge_Through_Current, /* numericFieldType */
+	VPD_VBUS_Impedance, /* numericFieldType */
+	VPD_Ground_Impedance, /* numericFieldType */
+
+	/* 3.2.18 Repeater Fields */
+	Repeater_One_Type, /* numericFieldType */
+	Repeater_Two_Type, /* numericFieldType */
+
+	Component_Indexes
+};
+
+struct vif_Component_t {
+	struct vif_field_t vif_field[Component_Indexes];
+
+	struct vif_srcPdoList_t SrcPdoList[MAX_NUM_SRC_PDOS];
+	struct vif_snkPdoList_t SnkPdoList[MAX_NUM_SNK_PDOS];
+	struct vif_sopSVIDList_t SOPSVIDList[MAX_NUM_SOP_SVIDS];
+	struct vif_cableSVIDList_t CableSVIDList[MAX_NUM_CABLE_SVIDS];
+
+	/*
+	 * The following fields are deprecated.  They should not be written
+	 * to file in this version or any later version of the schema.
+	 *
+	 * Deprecated in VIF Version 3.10
+	 *    vif_numericFieldType_t type_c_to_plug_receptacle;
+	 *    vif_numericFieldType_t retimer_type;
+	 * Deprecated in VIF Version 3.12
+	 *    vif_numericFieldType_t active_cable_usb2_hub_hops_supported;
+	 *    vif_booleanFieldType_t active_cable_optically_isololated;
+	 */
+};
+
+/* 3.2.2 Product Fields */
+
+enum vif_Product_indexes {
+	USB4_Product_Header, /* comment */
+	USB4_DROM_Vendor_ID, /* numericFieldType */
+	USB4_Dock, /* booleanFieldType */
+	USB4_Num_Internal_Host_Controllers, /* numericFieldType */
+	USB4_Num_PCIe_DN_Bridges, /* numericFieldType */
+	USB4_Device_HiFi_Bi_TMU_Mode_Required, /* booleanFieldType */
+	USB4_Audio_Supported, /* booleanFieldType */
+	USB4_HID_Supported, /* booleanFieldType */
+	USB4_Printer_Supported, /* booleanFieldType */
+	USB4_Mass_Storage_Supported, /* booleanFieldType */
+	USB4_Video_Supported, /* booleanFieldType */
+	USB4_Comms_Networking_Supported, /* booleanFieldType */
+	USB4_Media_Transfer_Protocol_Supported, /* booleanFieldType */
+	USB4_Smart_Card_Supported, /* booleanFieldType */
+	USB4_Still_Image_Capture_Supported, /* booleanFieldType */
+	USB4_Monitor_Device_Supported, /* booleanFieldType */
+	Product_Indexes
+};
+
+struct vif_Product_t {
+	struct vif_field_t vif_field[Product_Indexes];
+
+	struct vif_Usb4RouterListType_t USB4RouterList[MAX_NUM_USB4_ROUTERS];
+};
+
+enum vif_indexes {
+	VIF_Specification, /* version */
+	Vendor_Name, /* nonEmptyString */
+	Model_Part_Number, /* nonEmptyString */
+	Product_Revision, /* nonEmptyString */
+	TID, /* nonEmptyString */
+	VIF_Product_Type, /* numericFieldType */
+	Certification_Type, /* numericFieldType */
+	VIF_Indexes
+};
+
+enum vif_app_indexes {
+	Vendor, /* nonEmptyString */
+	Name, /* nonEmptyString */
+	Version, /* version */
+	VIF_App_Indexes
+};
+
+struct vif_t {
+	struct vif_field_t vif_field[VIF_Indexes];
+	struct vif_field_t vif_app_field[VIF_App_Indexes];
+
+	struct vif_Product_t Product;
+	struct vif_Component_t Component[MAX_NUM_COMPONENTS];
+};
+
+#endif /* __GENVIF_H__ */
diff --git a/util/getversion.sh b/util/getversion.sh
index 77a14c3324..605a304e3d 100755
--- a/util/getversion.sh
+++ b/util/getversion.sh
@@ -1,12 +1,18 @@
 #!/bin/bash
 #
-# Copyright 2012 The Chromium OS Authors. All rights reserved.
+# Copyright 2012 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
 # Generate version information for the EC binary
 
+: "${BOARD:=}"
+: "${CR50_DEV:=}"
+: "${CR50_SQA:=}"
+: "${CRYPTO_TEST:=}"
 : "${REPRODUCIBLE_BUILD:=}"
+: "${STATIC_VERSION:=}"
+: "${VCSID:=}"
 
 # Use this symbol as a separator to be able to reliably concatenate strings of
 # text.
@@ -15,6 +21,11 @@ dc=$'\001'
 # Default marker to indicate 'dirty' repositories
 dirty_marker='+'
 
+# Derive path to chromeos_version.sh script
+CHROOT_SOURCE_ROOT="/mnt/host/source"
+CHROMIUMOS_OVERLAY="${CHROOT_SOURCE_ROOT}/src/third_party/chromiumos-overlay"
+CROS_VERSION_SCRIPT="${CHROMIUMOS_OVERLAY}/chromeos/config/chromeos_version.sh"
+
 # This function examines the state of the current directory and attempts to
 # extract its version information: the latest tag, if any, how many patches
 # are there since the latest tag, the top sha1, and if there are local
@@ -63,8 +74,10 @@ get_tree_version() {
     vbase="${ver_major}.${ver_branch}.${numcommits}${marker}${ghash}"
   else
     # Fall back to the VCSID provided by the packaging system if available.
-    if ghash=${VCSID##*-}; then
-      vbase="1.1.9999-${ghash:0:7}"
+    # Ex VCSID: 0.0.1-r1519-9b368af6a4943b90941471d0bdf7e7208788f898
+    if [[ -n "${VCSID}" ]]; then
+      ghash="${VCSID##*-}"
+      vbase="v2.1.9999-${ghash:0:8}"
     else
       # then ultimately fails to "no_version"
       vbase="no_version"
@@ -115,6 +128,11 @@ main() {
         dir_list+=( ./private/fingerprint/fpc )
       fi
       ;;
+    (*_scp)
+      if [[ -d ./private-mt-scp ]]; then
+        dir_list+=( ./private-mt-scp )
+      fi
+      ;;
   esac
 
   # Create a combined version string for all component directories.
@@ -127,9 +145,11 @@ main() {
       if [[ -n "${values[1]}" ]]; then
         # From each modified repo get the most recently modified file.
         most_recent_file="$(git status --porcelain | \
-                                 awk '$1 ~ /[M|A|?]/ {print $2}' |  \
-                                 xargs ls -t | head -1)"
-        most_recents+=("$(realpath "${most_recent_file}")")
+                                 awk '$1 ~ /[M|A|?]/ {print $2}' | \
+                                 xargs -r ls -t | head -1)"
+        if [[ -n "${most_recent_file}" ]]; then
+          most_recents+=("$(realpath "${most_recent_file}")")
+        fi
       fi
       if [ "${component}" != "." ]; then
       ver+=" ${component}:"
@@ -188,6 +208,32 @@ main() {
       done | sort | tail -1 | cut -d ' ' -f '2 3')"
     echo "#define DATE \"${gitdate}\""
   fi
+
+  # Use the chromeos_version_string when available.
+  # This will not work if run from a standalone CrOS EC checkout.
+  echo "#define CROS_FWID_MISSING_STR \"CROS_FWID_MISSING\""
+  if [[ -f "${CROS_VERSION_SCRIPT}" ]]; then
+    cros_version_output=$("${CROS_VERSION_SCRIPT}")
+    CHROMEOS_BUILD=$(echo "${cros_version_output}" | \
+                     grep "^ *CHROMEOS_BUILD=" | cut -d= -f2)
+    CHROMEOS_BRANCH=$(echo "${cros_version_output}" | \
+                      grep "^ *CHROMEOS_BRANCH=" | cut -d= -f2)
+    CHROMEOS_PATCH=$(echo "${cros_version_output}" | \
+                     grep "^ *CHROMEOS_PATCH=" | cut -d= -f2)
+    # Official builds must set CHROMEOS_OFFICIAL=1.
+    if [ "${CHROMEOS_OFFICIAL:-0}" -ne 1 ]; then
+      # For developer builds, overwrite CHROMEOS_PATCH with the date.
+      # This date is abbreviated compared to chromeos_version.sh so
+      # fwid_version will more likely fit in 32 bytes.
+      CHROMEOS_PATCH=$(date +%y_%m_%d)
+    fi
+    fwid="${BOARD}_${CHROMEOS_BUILD}.${CHROMEOS_BRANCH}.${CHROMEOS_PATCH}"
+    echo "/* CrOS FWID of this build */"
+    echo "#define CROS_FWID32 \"${fwid:0:31}\""
+  else
+    echo "/* CrOS FWID is not available for this build */"
+    echo "#define CROS_FWID32 CROS_FWID_MISSING_STR"
+  fi
 }
 
 main
diff --git a/util/gpios_to_zephyr_dts.c b/util/gpios_to_zephyr_dts.c
new file mode 100644
index 0000000000..7efcd67ceb
--- /dev/null
+++ b/util/gpios_to_zephyr_dts.c
@@ -0,0 +1,117 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * This code is intended for developer use to convert a CrOS EC OS
+ * "gpio.inc" file into the expected device-tree format for Zephyr.
+ * The only use of it is to do a proof-of-concept build of a CrOS EC
+ * device using Zephyr OS, as Zephyr-only devices won't have a
+ * equivalent CrOS EC build.
+ *
+ * It does not handle all cases (i.e., low voltage selection), and
+ * some manual modifications to the output may be required.
+ *
+ **********************************************************************
+ * DO NOT CREATE TESTS, SYSTEMS, OR INFRASTRUCTURE WHICH RELIES ON    *
+ * THIS CODE.  It's seriously ugly code that's probably prone to      *
+ * breakage.  It leaks memory.  In other words, consider it           *
+ * "contrib-quality" code that should be deleted one day (once we are *
+ * no longer doing proof-of-concept Zephyr builds).                   *
+ **********************************************************************
+ *
+ * To compile:
+ *   gcc -Iboard/${BOARD} -std=gnu11 util/gpios_to_zephyr_dts.c \
+ *       -o /tmp/print_gpios
+ *
+ * Then run /tmp/print_gpios and paste the result into your gpio DTS
+ * overlay.
+ */
+
+#define _POSIX_C_SOURCE 200809L
+
+#include <ctype.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+/*
+ * Implement the macros used in the gpio.inc files, but print DTS
+ * format equivalents.
+ */
+#define GPIO_INT_RISING GPIO_INPUT
+#define GPIO_INT_FALLING GPIO_INPUT
+#define GPIO_INT_BOTH GPIO_INPUT
+#define GPIO_HIB_WAKE_HIGH 0
+#define GPIO_HIB_WAKE_LOW 0
+#define GPIO_LOCKED 0
+#define GPIO_SEL_1P8V 0
+#define GPIO_INT(name, pin, opts, int) GPIO(name, pin, opts)
+#define GPIO(name, pin, opts) _gpio(#name, pin, opts)
+#define UNUSED(pin)
+#define UNIMPLEMENTED(name)
+#define _gpio(name, pin, opts)                                   \
+	printf("%s {\n\tgpios = <&%s %s>;\n\tlabel = %s;\n};\n", \
+	       strlower(name), strlower(pin),                    \
+	       maybe_parens(strip_zero_ors(#opts)), #name);
+#define PIN(A, B) "gpio" #A " " #B
+#define ALTERNATE(...)
+#define IOEX(...)
+#define IOEX_INT(...)
+
+/* Strip out " | 0" and "0 | " from a string */
+static char *strip_zero_ors(const char *s)
+{
+	char *out = malloc(strlen(s) + 2);
+	const char *rd_ptr = s;
+	char *wr_ptr = out;
+
+	while (*rd_ptr) {
+		if (!strncmp(rd_ptr, " | 0", 4) ||
+		    !strncmp(rd_ptr, "0 | ", 4)) {
+			rd_ptr += 4;
+		} else {
+			*wr_ptr = *rd_ptr;
+			rd_ptr++;
+			wr_ptr++;
+		}
+	}
+
+	*wr_ptr = '\0';
+	return out;
+}
+
+/*
+ * Add parenthesis around the outside of a string if it contains the
+ * '|' character.
+ */
+static char *maybe_parens(const char *s)
+{
+	size_t out_sz = strlen(s) + 3;
+	char *out = malloc(out_sz);
+
+	if (strchr(s, '|'))
+		snprintf(out, out_sz, "(%s)", s);
+	else
+		snprintf(out, out_sz, "%s", s);
+
+	return out;
+}
+
+/* Convert a string to lowercase */
+static char *strlower(const char *s)
+{
+	char *out = strdup(s);
+
+	for (int i = 0; out[i]; i++)
+		out[i] = tolower(out[i]);
+
+	return out;
+}
+
+int main(int argc, char *argv[])
+{
+#include "gpio.inc"
+	return 0;
+}
diff --git a/util/host_command_check.sh b/util/host_command_check.sh
index 62911bb0c3..03dd570c4d 100755
--- a/util/host_command_check.sh
+++ b/util/host_command_check.sh
@@ -1,9 +1,11 @@
 #!/bin/bash
 #
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
+excludes=( --exclude-dir=build --exclude=TAGS )
+
 #######################################
 # Test if the following conditions hold for the ec host command
 # The alpha numeric value of the define starts with 0x
@@ -82,8 +84,9 @@ should_check() {
 main() {
 
   # Do not run the check unless an EC_[xxx]CMD change is present.
-  if [[ -z "$(git diff "${PRESUBMIT_COMMIT}~" "${PRESUBMIT_COMMIT}" -U0 |
-      egrep 'EC_[^ ]*CMD')" ]]; then
+  if [[ -z "$(git diff --no-ext-diff "${PRESUBMIT_COMMIT}~" \
+          "${PRESUBMIT_COMMIT}" -U0 |
+      grep -E 'EC_[^ ]*CMD')" ]]; then
     exit 0
   fi
 
@@ -91,7 +94,7 @@ main() {
   ei=0
   # Search all file occurrences of "EC_CMD" and store in array
   IFS=$'\n'
-  ec_cmds=($(grep -r "EC_CMD"))
+  ec_cmds=($(grep "${excludes[@]}" -r "EC_CMD"))
 
   # Loop through and find valid occurrences of "EC_CMD" to check
   length=${#ec_cmds[@]}
@@ -106,7 +109,7 @@ main() {
 
   # Search all file occurrances of "EC_PRV_CMD" and store in array
   IFS=$'\n'
-  ec_prv_cmds=($(grep -r "EC_PRV_CMD"))
+  ec_prv_cmds=($(grep "${excludes[@]}" -r "EC_PRV_CMD"))
 
   # Loop through and find valid occurrences of "EC_PRV_CMD" to check
   length=${#ec_prv_cmds[@]}
diff --git a/util/ide-config.sh b/util/ide-config.sh
index 03928065a7..a172cf5767 100755
--- a/util/ide-config.sh
+++ b/util/ide-config.sh
@@ -1,5 +1,5 @@
 #!/bin/bash
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -231,7 +231,9 @@ vscode() {
 				echo '"compilerPath": "/usr/bin/arm-none-eabi-gcc",'
 				# echo '"compilerArgs": [],'
 				# The macro __STDC_VERSION__ is 201710L, which corresponds to c18.
-				echo '"cStandard": "c18",'
+				# VSCode doesn't have a C18 option, so go with C17. Since we seem
+				# to use a lot of GNUC features, let's go with gnu17 instead of c17.
+				echo '"cStandard": "gnu17",'
 				# echo '"cppStandard": "c++17",'
 				echo '"intelliSenseMode": "gcc-x64"'
 			} | {
diff --git a/util/inject-keys.py b/util/inject-keys.py
index bd10b693ad..8efdb17208 100755
--- a/util/inject-keys.py
+++ b/util/inject-keys.py
@@ -1,65 +1,230 @@
 #!/usr/bin/env python
 # -*- coding: utf-8 -*-
 #
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 # Note: This is a py2/3 compatible file.
 
 from __future__ import print_function
+
 import string
 import subprocess
 import sys
 
 
-KEYMATRIX = {'`': (3, 1), '1': (6, 1), '2': (6, 4), '3': (6, 2), '4': (6, 3),
-             '5': (3, 3), '6': (3, 6), '7': (6, 6), '8': (6, 5), '9': (6, 9),
-             '0': (6, 8), '-': (3, 8), '=': (0, 8), 'q': (7, 1), 'w': (7, 4),
-             'e': (7, 2), 'r': (7, 3), 't': (2, 3), 'y': (2, 6), 'u': (7, 6),
-             'i': (7, 5), 'o': (7, 9), 'p': (7, 8), '[': (2, 8), ']': (2, 5),
-             '\\': (3, 11), 'a': (4, 1), 's': (4, 4), 'd': (4, 2), 'f': (4, 3),
-             'g': (1, 3), 'h': (1, 6), 'j': (4, 6), 'k': (4, 5), 'l': (4, 9),
-             ';': (4, 8), '\'': (1, 8), 'z': (5, 1), 'x': (5, 4), 'c': (5, 2),
-             'v': (5, 3), 'b': (0, 3), 'n': (0, 6), 'm': (5, 6), ',': (5, 5),
-             '.': (5, 9), '/': (5, 8), ' ': (5, 11), '<right>': (6, 12),
-             '<alt_r>': (0, 10), '<down>': (6, 11), '<tab>': (2, 1),
-             '<f10>': (0, 4), '<shift_r>': (7, 7), '<ctrl_r>': (4, 0),
-             '<esc>': (1, 1), '<backspace>': (1, 11), '<f2>': (3, 2),
-             '<alt_l>': (6, 10), '<ctrl_l>': (2, 0), '<f1>': (0, 2),
-             '<search>': (0, 1), '<f3>': (2, 2), '<f4>': (1, 2), '<f5>': (3, 4),
-             '<f6>': (2, 4), '<f7>': (1, 4), '<f8>': (2, 9), '<f9>': (1, 9),
-             '<up>': (7, 11), '<shift_l>': (5, 7), '<enter>': (4, 11),
-             '<left>': (7, 12)}
-
-
-UNSHIFT_TABLE = { '~': '`', '!': '1', '@': '2', '#': '3', '$': '4',
-                  '%': '5', '^': '6', '&': '7', '*': '8', '(': '9',
-                  ')': '0', '_': '-', '+': '=', '{': '[', '}': ']',
-                  '|': '\\',
-                  ':': ';', '"': "'", '<': ',', '>': '.', '?': '/'}
+KEYMATRIX_0 = {
+    "`": (3, 1),
+    "1": (6, 1),
+    "2": (6, 4),
+    "3": (6, 2),
+    "4": (6, 3),
+    "5": (3, 3),
+    "6": (3, 6),
+    "7": (6, 6),
+    "8": (6, 5),
+    "9": (6, 9),
+    "0": (6, 8),
+    "-": (3, 8),
+    "=": (0, 8),
+    "q": (7, 1),
+    "w": (7, 4),
+    "e": (7, 2),
+    "r": (7, 3),
+    "t": (2, 3),
+    "y": (2, 6),
+    "u": (7, 6),
+    "i": (7, 5),
+    "o": (7, 9),
+    "p": (7, 8),
+    "[": (2, 8),
+    "]": (2, 5),
+    "\\": (3, 11),
+    "a": (4, 1),
+    "s": (4, 4),
+    "d": (4, 2),
+    "f": (4, 3),
+    "g": (1, 3),
+    "h": (1, 6),
+    "j": (4, 6),
+    "k": (4, 5),
+    "l": (4, 9),
+    ";": (4, 8),
+    "'": (1, 8),
+    "z": (5, 1),
+    "x": (5, 4),
+    "c": (5, 2),
+    "v": (5, 3),
+    "b": (0, 3),
+    "n": (0, 6),
+    "m": (5, 6),
+    ",": (5, 5),
+    ".": (5, 9),
+    "/": (5, 8),
+    " ": (5, 11),
+    "<right>": (6, 12),
+    "<alt_r>": (0, 10),
+    "<down>": (6, 11),
+    "<tab>": (2, 1),
+    "<f10>": (0, 4),
+    "<shift_r>": (7, 7),
+    "<ctrl_r>": (4, 0),
+    "<esc>": (1, 1),
+    "<backspace>": (1, 11),
+    "<f2>": (3, 2),
+    "<alt_l>": (6, 10),
+    "<ctrl_l>": (2, 0),
+    "<f1>": (0, 2),
+    "<search>": (0, 1),
+    "<f3>": (2, 2),
+    "<f4>": (1, 2),
+    "<f5>": (3, 4),
+    "<f6>": (2, 4),
+    "<f7>": (1, 4),
+    "<f8>": (2, 9),
+    "<f9>": (1, 9),
+    "<up>": (7, 11),
+    "<shift_l>": (5, 7),
+    "<enter>": (4, 11),
+    "<left>": (7, 12),
+}
+
+KEYMATRIX_1 = {
+    "`": (3, 1),
+    "1": (7, 1),
+    "2": (6, 4),
+    "3": (6, 2),
+    "4": (6, 3),
+    "5": (3, 3),
+    "6": (3, 6),
+    "7": (6, 6),
+    "8": (6, 5),
+    "9": (6, 9),
+    "0": (0, 9),
+    "-": (3, 8),
+    "=": (0, 8),
+    "q": (6, 12),
+    "w": (7, 4),
+    "e": (5, 8),
+    "r": (7, 3),
+    "t": (2, 3),
+    "y": (2, 6),
+    "u": (7, 6),
+    "i": (7, 5),
+    "o": (6, 8),
+    "p": (7, 8),
+    "[": (2, 8),
+    "]": (2, 5),
+    "\\": (1, 11),
+    "a": (4, 1),
+    "s": (5, 6),
+    "d": (0, 14),
+    "f": (4, 3),
+    "g": (1, 3),
+    "h": (1, 6),
+    "j": (4, 6),
+    "k": (4, 5),
+    "l": (4, 9),
+    ";": (4, 8),
+    "'": (1, 8),
+    "z": (7, 9),
+    "x": (5, 5),
+    "c": (7, 13),
+    "v": (7, 2),
+    "b": (0, 3),
+    "n": (0, 6),
+    "m": (5, 1),
+    ",": (5, 4),
+    ".": (5, 9),
+    "/": (6, 11),
+    " ": (5, 3),
+    "<right>": (1, 12),
+    "<alt_r>": (0, 10),
+    "<down>": (5, 11),
+    "<tab>": (6, 1),
+    "<f10>": (1, 4),
+    "<shift_r>": (7, 7),
+    "<ctrl_r>": (4, 0),
+    "<esc>": (1, 1),
+    "<backspace>": (7, 11),
+    "<f2>": (3, 2),
+    "<alt_l>": (6, 10),
+    "<ctrl_l>": (2, 0),
+    "<f1>": (4, 2),
+    "<search>": (3, 0),
+    "<f3>": (2, 2),
+    "<f4>": (1, 2),
+    "<f5>": (4, 4),
+    "<f6>": (3, 4),
+    "<f7>": (2, 4),
+    "<f8>": (2, 9),
+    "<f9>": (1, 9),
+    "<up>": (2, 11),
+    "<shift_l>": (1, 7),
+    "<enter>": (4, 11),
+    "<left>": (0, 12),
+}
+
+# Extensible: when new model comes up in future that deviates from default keyboard matrix,
+# and most certainly different from frostflow, new KEYMATRIX_x entry can be defined first,
+# and then add an "model_name" : KEYMATRIX_x to here.
+MODEL_KBMATRIX_MAP = {
+    "default_matrix": KEYMATRIX_0,
+    "frostflow": KEYMATRIX_1,
+    # "mithrax" is another model that uses same kb matrix with frostflow,
+    # can add "mithrax" : KEYMATRIX_1
+}
+
+UNSHIFT_TABLE = {
+    "~": "`",
+    "!": "1",
+    "@": "2",
+    "#": "3",
+    "$": "4",
+    "%": "5",
+    "^": "6",
+    "&": "7",
+    "*": "8",
+    "(": "9",
+    ")": "0",
+    "_": "-",
+    "+": "=",
+    "{": "[",
+    "}": "]",
+    "|": "\\",
+    ":": ";",
+    '"': "'",
+    "<": ",",
+    ">": ".",
+    "?": "/",
+}
 
 for c in string.ascii_lowercase:
     UNSHIFT_TABLE[c.upper()] = c
 
 
 def inject_event(key, press):
-    if len(key) >= 2 and key[0] != '<':
-        key = '<' + key + '>'
+    """Function inject_event()."""
+    if len(key) >= 2 and key[0] != "<":
+        key = "<" + key + ">"
     if key not in KEYMATRIX:
         print("%s: invalid key: %s" % (this_script, key))
         sys.exit(1)
     (row, col) = KEYMATRIX[key]
-    subprocess.call(["ectool", "kbpress", str(row), str(col),
-                     "1" if press else "0"])
+    subprocess.call(
+        ["ectool", "kbpress", str(row), str(col), "1" if press else "0"]
+    )
 
 
 def inject_key(key):
+    """Function inject_key()."""
     inject_event(key, True)
     inject_event(key, False)
 
 
 def inject_string(string):
+    """Function inject_string()."""
     for c in string:
         if c in KEYMATRIX:
             inject_key(c)
@@ -72,20 +237,36 @@ def inject_string(string):
             sys.exit(1)
 
 
+def read_dutmodel():
+    """Function read_dutmodel()."""
+    try:
+        output = subprocess.check_output(
+            "cros_config / name", stderr=subprocess.DEVNULL, shell=True
+        )
+        modelstr = str(output, "UTF-8")
+    except subprocess.SubprocessError:
+        modelstr = ""
+    return modelstr
+
+
 def usage():
-    print("Usage: %s [-s <string>] [-k <key>]" % this_script,
-          "[-p <pressed-key>] [-r <released-key>] ...")
+    """Function usage()."""
+    print(
+        "Usage: %s [-s <string>] [-k <key>]" % this_script,
+        "[-p <pressed-key>] [-r <released-key>] ...",
+    )
     print("Examples:")
     print("%s -s MyPassw0rd -k enter" % this_script)
     print("%s -p ctrl_l -p alt_l -k f3 -r alt_l -r ctrl_l" % this_script)
 
 
 def help():
+    """Function help()."""
     usage()
     print("Valid keys are:")
     i = 0
     for key in KEYMATRIX:
-        print("%12s" % key, end='')
+        print("%12s" % key, end="")
         i += 1
         if i % 4 == 0:
             print()
@@ -94,6 +275,7 @@ def help():
 
 
 def usage_check(asserted_condition, message):
+    """Function usage_check()."""
     if asserted_condition:
         return
     print("%s:" % this_script, message)
@@ -114,12 +296,19 @@ def usage_check(asserted_condition, message):
 usage_check(arg_len % 2 == 1, "mismatched arguments")
 
 for i in range(1, arg_len, 2):
-    usage_check(sys.argv[i] in ("-s", "-k", "-p", "-r"),
-                "unknown flag: %s" % sys.argv[i])
+    usage_check(
+        sys.argv[i] in ("-s", "-k", "-p", "-r"),
+        "unknown flag: %s" % sys.argv[i],
+    )
+
+KEYMATRIX = KEYMATRIX_0
+model = read_dutmodel()
+if model in MODEL_KBMATRIX_MAP:
+    KEYMATRIX = MODEL_KBMATRIX_MAP[model]
 
 for i in range(1, arg_len, 2):
     flag = sys.argv[i]
-    arg = sys.argv[i+1]
+    arg = sys.argv[i + 1]
     if flag == "-s":
         inject_string(arg)
     elif flag == "-k":
diff --git a/util/iteflash.c b/util/iteflash.c
index 799ad3ca70..8b03c2e4cb 100644
--- a/util/iteflash.c
+++ b/util/iteflash.c
@@ -1,27 +1,33 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * ITE83xx SoC in-system programming tool
  */
 
+/* remove when ftdi_usb_purge_buffers has been replaced to follow libftdi */
+#define _FTDI_DISABLE_DEPRECATED
+
+#include "compile_time_macros.h"
+#include "usb_if.h"
+
 #include <errno.h>
-#include <fcntl.h>
-#include <ftdi.h>
-#include <getopt.h>
-#include <linux/i2c-dev.h>
-#include <linux/i2c.h>
 #include <signal.h>
+#include <stdbool.h>
 #include <stdint.h>
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
-#include <sys/ioctl.h>
 #include <time.h>
-#include <unistd.h>
 
-#include "compile_time_macros.h"
-#include "usb_if.h"
+#include <fcntl.h>
+#include <ftdi.h>
+#include <getopt.h>
+#include <linux/i2c-dev.h>
+#include <linux/i2c.h>
+#include <sys/ioctl.h>
+#include <sys/wait.h>
+#include <unistd.h>
 
 /* Default FTDI device : Servo v2. */
 #define SERVO_USB_VID 0x18d1
@@ -33,65 +39,65 @@
 #define CR50_USB_PID 0x5014
 
 /* Cr50 exposed properties of the USB I2C endpoint. */
-#define CR50_I2C_SUBCLASS  82
-#define CR50_I2C_PROTOCOL  1
+#define CR50_I2C_SUBCLASS 82
+#define CR50_I2C_PROTOCOL 1
 
-#define CROS_CMD_ADDR		0x78	/* USB_I2C_CMD_ADDR 0xF0 >> 1 */
-#define CROS_CMD_ITE_SYNC	0
+#define CROS_CMD_ADDR 0x78 /* USB_I2C_CMD_ADDR 0xF0 >> 1 */
+#define CROS_CMD_ITE_SYNC 0
 
 /* DBGR I2C addresses */
-#define I2C_CMD_ADDR   0x5A
-#define I2C_DATA_ADDR  0x35
+#define I2C_CMD_ADDR 0x5A
+#define I2C_DATA_ADDR 0x35
 #define I2C_BLOCK_ADDR 0x79
 
 #define FTDI_I2C_FREQ 400000
 
 /* I2C pins on the FTDI interface */
-#define SCL_BIT        BIT(0)
-#define SDA_BIT        BIT(1)
+#define SCL_BIT BIT(0)
+#define SDA_BIT BIT(1)
 
 /* Chip ID register value */
 #define CHIP_ID 0x8380
 
 /* Embedded flash page size */
-#define PAGE_SIZE		(1<<8)
+#define PAGE_SIZE (1 << 8)
 
 /* Embedded flash block write size for different programming modes. */
-#define FTDI_BLOCK_WRITE_SIZE	(1<<16)
+#define FTDI_BLOCK_WRITE_SIZE (1 << 16)
 
 /* JEDEC SPI Flash commands */
-#define SPI_CMD_PAGE_PROGRAM	0x02
-#define SPI_CMD_WRITE_DISABLE	0x04
-#define SPI_CMD_READ_STATUS	0x05
-#define SPI_CMD_WRITE_ENABLE	0x06
-#define SPI_CMD_FAST_READ	0x0B
-#define SPI_CMD_CHIP_ERASE	0x60
-#define SPI_CMD_SECTOR_ERASE_1K	0xD7
-#define SPI_CMD_SECTOR_ERASE_4K	0x20
-#define SPI_CMD_WORD_PROGRAM	0xAD
-#define SPI_CMD_EWSR		0x50 /* Enable Write Status Register */
-#define SPI_CMD_WRSR		0x01 /* Write Status Register */
-#define SPI_CMD_RDID		0x9F /* Read Flash ID */
+#define SPI_CMD_PAGE_PROGRAM 0x02
+#define SPI_CMD_WRITE_DISABLE 0x04
+#define SPI_CMD_READ_STATUS 0x05
+#define SPI_CMD_WRITE_ENABLE 0x06
+#define SPI_CMD_FAST_READ 0x0B
+#define SPI_CMD_CHIP_ERASE 0x60
+#define SPI_CMD_SECTOR_ERASE_1K 0xD7
+#define SPI_CMD_SECTOR_ERASE_4K 0x20
+#define SPI_CMD_WORD_PROGRAM 0xAD
+#define SPI_CMD_EWSR 0x50 /* Enable Write Status Register */
+#define SPI_CMD_WRSR 0x01 /* Write Status Register */
+#define SPI_CMD_RDID 0x9F /* Read Flash ID */
 
 /* Size for FTDI outgoing buffer */
-#define FTDI_CMD_BUF_SIZE (1<<12)
+#define FTDI_CMD_BUF_SIZE (1 << 12)
 
 /* Reset Status */
-#define RSTS_VCCDO_PW_ON	0x40
-#define RSTS_VFSPIPG		0x20
-#define RSTS_HGRST		0x08
-#define RSTS_GRST		0x04
+#define RSTS_VCCDO_PW_ON 0x40
+#define RSTS_VFSPIPG 0x20
+#define RSTS_HGRST 0x08
+#define RSTS_GRST 0x04
 
 /* I2C MUX Configuration: TCA9543 or PCA9546 */
-#define I2C_MUX_CMD_ADDR		0x70
-#define I2C_MUX_CMD_NONE		0x00
-#define I2C_MUX_CMD_INAS		0x01
-#define I2C_MUX_CMD_EC			0x02
+#define I2C_MUX_CMD_ADDR 0x70
+#define I2C_MUX_CMD_NONE 0x00
+#define I2C_MUX_CMD_INAS 0x01
+#define I2C_MUX_CMD_EC 0x02
 
 /* Eflash Type*/
-#define EFLASH_TYPE_8315	0x01
-#define EFLASH_TYPE_KGD		0x02
-#define EFLASH_TYPE_NONE	0xFF
+#define EFLASH_TYPE_8315 0x01
+#define EFLASH_TYPE_KGD 0x02
+#define EFLASH_TYPE_NONE 0xFF
 
 uint8_t eflash_type;
 uint8_t spi_cmd_sector_erase;
@@ -99,7 +105,6 @@ uint8_t spi_cmd_sector_erase;
 /* Embedded flash number of pages in a sector erase */
 uint8_t sector_erase_pages;
 
-
 static volatile sig_atomic_t exit_requested;
 
 struct i2c_interface;
@@ -108,16 +113,17 @@ struct i2c_interface;
 struct iteflash_config {
 	char *input_filename;
 	char *output_filename;
-	int send_waveform;  /* boolean */
-	int erase;  /* boolean */
+	int send_waveform; /* boolean */
+	int erase; /* boolean */
 	int i2c_mux; /* boolean */
-	int debug;  /* boolean */
-	int disable_watchdog;  /* boolean */
-	int disable_protect_path;  /* boolean */
+	int debug; /* boolean */
+	int disable_watchdog; /* boolean */
+	int disable_protect_path; /* boolean */
 	int block_write_size;
 	int usb_interface;
 	int usb_vid;
 	int usb_pid;
+	int verify; /* boolean */
 	char *usb_serial;
 	char *i2c_dev_path;
 	const struct i2c_interface *i2c_if;
@@ -128,8 +134,8 @@ struct iteflash_config {
 struct common_hnd {
 	struct iteflash_config conf;
 	int flash_size;
-	int flash_cmd_v2;      /* boolean */
-	int dbgr_addr_3bytes;  /* boolean */
+	int flash_cmd_v2; /* boolean */
+	int dbgr_addr_3bytes; /* boolean */
 	union {
 		int i2c_dev_fd;
 		struct usb_endpoint uep;
@@ -156,13 +162,13 @@ struct i2c_interface {
 	int (*send_special_waveform)(struct common_hnd *chnd);
 	/* Required, must not be NULL. */
 	int (*byte_transfer)(struct common_hnd *chnd, uint8_t addr,
-		uint8_t *data, int write, int numbytes);
+			     uint8_t *data, int write, int numbytes);
 	/* Required, must be positive. */
 	int default_block_write_size;
 };
 
-static int spi_flash_command_short(struct common_hnd *chnd,
-				   uint8_t cmd, char *desc);
+static int spi_flash_command_short(struct common_hnd *chnd, uint8_t cmd,
+				   char *desc);
 
 static void null_and_free(void **ptr)
 {
@@ -186,7 +192,7 @@ static void config_release(struct iteflash_config *conf)
 }
 
 /* number of bytes to send consecutively before checking for ACKs */
-#define FTDI_TX_BUFFER_LIMIT	32
+#define FTDI_TX_BUFFER_LIMIT 32
 
 static inline int i2c_byte_transfer(struct common_hnd *chnd, uint8_t addr,
 				    uint8_t *data, int write, int numbytes)
@@ -196,7 +202,7 @@ static inline int i2c_byte_transfer(struct common_hnd *chnd, uint8_t addr,
 		return -1;
 
 	return chnd->conf.i2c_if->byte_transfer(chnd, addr, data, write,
-		numbytes);
+						numbytes);
 }
 
 static int linux_i2c_byte_transfer(struct common_hnd *chnd, uint8_t addr,
@@ -219,8 +225,10 @@ static int linux_i2c_byte_transfer(struct common_hnd *chnd, uint8_t addr,
 	ret = ioctl(chnd->i2c_dev_fd, I2C_RDWR, &msgset);
 	if (ret < 0) {
 		extra_int = errno;
-		fprintf(stderr, "%s: ioctl() failed with return value %d and "
-			"errno %d\n", __func__, ret, extra_int);
+		fprintf(stderr,
+			"%s: ioctl() failed with return value %d and "
+			"errno %d\n",
+			__func__, ret, extra_int);
 		if (ret == -1 && extra_int)
 			ret = -abs(extra_int);
 	} else if (ret < nmsgs) {
@@ -244,12 +252,17 @@ static int i2c_add_send_byte(struct ftdi_context *ftdi, uint8_t *buf,
 
 	for (i = 0; i < tcnt; i++) {
 		/* WORKAROUND: force SDA before sending the next byte */
-		*b++ = SET_BITS_LOW; *b++ = SDA_BIT; *b++ = SCL_BIT | SDA_BIT;
+		*b++ = SET_BITS_LOW;
+		*b++ = SDA_BIT;
+		*b++ = SCL_BIT | SDA_BIT;
 		/* write byte */
 		*b++ = MPSSE_DO_WRITE | MPSSE_BITMODE | MPSSE_WRITE_NEG;
-		*b++ = 0x07; *b++ = *tbuf++;
+		*b++ = 0x07;
+		*b++ = *tbuf++;
 		/* prepare for ACK */
-		*b++ = SET_BITS_LOW; *b++ = 0; *b++ = SCL_BIT;
+		*b++ = SET_BITS_LOW;
+		*b++ = 0;
+		*b++ = SCL_BIT;
 		/* read ACK */
 		*b++ = MPSSE_DO_READ | MPSSE_BITMODE | MPSSE_LSB;
 		*b++ = 0;
@@ -261,7 +274,7 @@ static int i2c_add_send_byte(struct ftdi_context *ftdi, uint8_t *buf,
 		 * On the last byte, or every FTDI_TX_BUFFER_LIMIT bytes, read
 		 * the ACK bits.
 		 */
-		if (i == tcnt-1 || (tx_buffered == FTDI_TX_BUFFER_LIMIT)) {
+		if (i == tcnt - 1 || (tx_buffered == FTDI_TX_BUFFER_LIMIT)) {
 			/* write data */
 			ret = ftdi_write_data(ftdi, buf, b - buf);
 			if (ret < 0) {
@@ -274,7 +287,7 @@ static int i2c_add_send_byte(struct ftdi_context *ftdi, uint8_t *buf,
 			ack_idx = 0;
 			do {
 				ret = ftdi_read_data(ftdi, &ack[ack_idx],
-					remaining_data);
+						     remaining_data);
 				if (ret < 0) {
 					fprintf(stderr, "read ACK failed\n");
 					return ret;
@@ -293,7 +306,7 @@ static int i2c_add_send_byte(struct ftdi_context *ftdi, uint8_t *buf,
 					fprintf(stderr,
 						"write ACK fail: %d, 0x%02x\n",
 						ret, failed_ack);
-				return  -ENXIO;
+				return -ENXIO;
 			}
 
 			/* reset for next set of transactions */
@@ -312,20 +325,32 @@ static int i2c_add_recv_bytes(struct ftdi_context *ftdi, uint8_t *buf,
 
 	for (i = 0; i < rcnt; i++) {
 		/* set SCL low */
-		*b++ = SET_BITS_LOW; *b++ = 0; *b++ = SCL_BIT;
+		*b++ = SET_BITS_LOW;
+		*b++ = 0;
+		*b++ = SCL_BIT;
 		/* read the byte on the wire */
-		*b++ = MPSSE_DO_READ; *b++ = 0; *b++ = 0;
+		*b++ = MPSSE_DO_READ;
+		*b++ = 0;
+		*b++ = 0;
 
 		if (i == rcnt - 1) {
 			/* NACK last byte */
-			*b++ = SET_BITS_LOW; *b++ = 0; *b++ = SCL_BIT;
+			*b++ = SET_BITS_LOW;
+			*b++ = 0;
+			*b++ = SCL_BIT;
 			*b++ = MPSSE_DO_WRITE | MPSSE_BITMODE | MPSSE_WRITE_NEG;
-			*b++ = 0; *b++ = 0xff; *b++ = SEND_IMMEDIATE;
+			*b++ = 0;
+			*b++ = 0xff;
+			*b++ = SEND_IMMEDIATE;
 		} else {
 			/* ACK all other bytes */
-			*b++ = SET_BITS_LOW; *b++ = 0; *b++ = SCL_BIT | SDA_BIT;
+			*b++ = SET_BITS_LOW;
+			*b++ = 0;
+			*b++ = SCL_BIT | SDA_BIT;
 			*b++ = MPSSE_DO_WRITE | MPSSE_BITMODE | MPSSE_WRITE_NEG;
-			*b++ = 0; *b++ = 0; *b++ = SEND_IMMEDIATE;
+			*b++ = 0;
+			*b++ = 0;
+			*b++ = SEND_IMMEDIATE;
 		}
 	}
 
@@ -395,7 +420,7 @@ static int ccd_i2c_byte_transfer(struct common_hnd *chnd, uint8_t addr,
 		write ? sizeof(usb_buffer) : USB_I2C_HEADER_SIZE + extra,
 		usb_buffer, sizeof(usb_buffer), 1, &response_size);
 
-	if (response_size < (USB_I2C_HEADER_SIZE  + (write ? 0 : numbytes))) {
+	if (response_size < (USB_I2C_HEADER_SIZE + (write ? 0 : numbytes))) {
 		fprintf(stderr, "%s: got too few bytes (%zd) in response\n",
 			__func__, response_size);
 		return -1;
@@ -411,8 +436,7 @@ static int ccd_i2c_byte_transfer(struct common_hnd *chnd, uint8_t addr,
 		rv = usb_buffer[1];
 		rv = (rv << 8) + usb_buffer[0];
 
-		fprintf(stderr, "%s: usb i2c error %d\n",
-			__func__,
+		fprintf(stderr, "%s: usb i2c error %d\n", __func__,
 			(((uint16_t)usb_buffer[1]) << 8) + usb_buffer[0]);
 
 		return -rv;
@@ -439,14 +463,26 @@ static int ftdi_i2c_byte_transfer(struct common_hnd *chnd, uint8_t addr,
 
 	/* START condition */
 	/* SCL & SDA high */
-	*b++ = SET_BITS_LOW; *b++ = 0; *b++ = 0;
-	*b++ = SET_BITS_LOW; *b++ = 0; *b++ = 0;
+	*b++ = SET_BITS_LOW;
+	*b++ = 0;
+	*b++ = 0;
+	*b++ = SET_BITS_LOW;
+	*b++ = 0;
+	*b++ = 0;
 	/* SCL high, SDA low */
-	*b++ = SET_BITS_LOW; *b++ = 0; *b++ = SDA_BIT;
-	*b++ = SET_BITS_LOW; *b++ = 0; *b++ = SDA_BIT;
+	*b++ = SET_BITS_LOW;
+	*b++ = 0;
+	*b++ = SDA_BIT;
+	*b++ = SET_BITS_LOW;
+	*b++ = 0;
+	*b++ = SDA_BIT;
 	/* SCL low, SDA low */
-	*b++ = SET_BITS_LOW; *b++ = 0; *b++ = SCL_BIT | SDA_BIT;
-	*b++ = SET_BITS_LOW; *b++ = 0; *b++ = SCL_BIT | SDA_BIT;
+	*b++ = SET_BITS_LOW;
+	*b++ = 0;
+	*b++ = SCL_BIT | SDA_BIT;
+	*b++ = SET_BITS_LOW;
+	*b++ = 0;
+	*b++ = SCL_BIT | SDA_BIT;
 
 	/* send address */
 	slave_addr = (addr << 1) | (write ? 0 : 1);
@@ -461,7 +497,7 @@ static int ftdi_i2c_byte_transfer(struct common_hnd *chnd, uint8_t addr,
 	b = buf;
 	if (write) /* write data */
 		ret = i2c_add_send_byte(ftdi, buf, b, data, numbytes,
-			chnd->conf.debug);
+					chnd->conf.debug);
 	else /* read data */
 		ret = i2c_add_recv_bytes(ftdi, buf, b, data, numbytes);
 
@@ -469,11 +505,19 @@ static int ftdi_i2c_byte_transfer(struct common_hnd *chnd, uint8_t addr,
 	b = buf;
 	/* STOP condition */
 	/* SCL high, SDA low */
-	*b++ = SET_BITS_LOW; *b++ = 0; *b++ = SDA_BIT;
-	*b++ = SET_BITS_LOW; *b++ = 0; *b++ = SDA_BIT;
+	*b++ = SET_BITS_LOW;
+	*b++ = 0;
+	*b++ = SDA_BIT;
+	*b++ = SET_BITS_LOW;
+	*b++ = 0;
+	*b++ = SDA_BIT;
 	/* SCL high, SDA high */
-	*b++ = SET_BITS_LOW; *b++ = 0; *b++ = 0;
-	*b++ = SET_BITS_LOW; *b++ = 0; *b++ = 0;
+	*b++ = SET_BITS_LOW;
+	*b++ = 0;
+	*b++ = 0;
+	*b++ = SET_BITS_LOW;
+	*b++ = 0;
+	*b++ = 0;
 
 	rets = ftdi_write_data(ftdi, buf, b - buf);
 	if (rets < 0)
@@ -543,21 +587,16 @@ static int check_flashid(struct common_hnd *chnd)
 {
 	int ret = 0;
 	uint8_t id[16], i;
-	struct cmds commands[] = {
-		{0x07, 0x7f},
-		{0x06, 0xff},
-		{0x04, 0x00},
-		{0x05, 0xfe},
-		{0x08, 0x00},
-		{0x05, 0xfd},
-		{0x08, 0x9f}
-	};
+	struct cmds commands[] = { { 0x07, 0x7f }, { 0x06, 0xff },
+				   { 0x04, 0x00 }, { 0x05, 0xfe },
+				   { 0x08, 0x00 }, { 0x05, 0xfd },
+				   { 0x08, 0x9f } };
 
 	for (i = 0; i < ARRAY_SIZE(commands); i++) {
 		ret = i2c_write_byte(chnd, commands[i].addr, commands[i].cmd);
 		if (ret) {
 			fprintf(stderr, "Flash ID Failed : cmd %x ,data %x\n",
-			commands[i].addr, commands[i].cmd);
+				commands[i].addr, commands[i].cmd);
 			return ret;
 		}
 	}
@@ -589,7 +628,7 @@ static int check_chipid(struct common_hnd *chnd)
 	int ret;
 	uint8_t ver = 0xff;
 	uint32_t id = 0xffff;
-	uint16_t v2[7] = {128, 192, 256, 384, 512, 0, 1024};
+	uint16_t v2[7] = { 128, 192, 256, 384, 512, 0, 1024 };
 	/*
 	 * Chip Version is mapping from bit 3-0
 	 * Flash size is mapping from bit 7-4
@@ -631,7 +670,7 @@ static int check_chipid(struct common_hnd *chnd)
 
 	if ((id & 0xff00) != (CHIP_ID & 0xff00)) {
 		id |= 0xff0000;
-		ret = get_3rd_chip_id_byte(chnd, (uint8_t *)&id+2);
+		ret = get_3rd_chip_id_byte(chnd, (uint8_t *)&id + 2);
 		if (ret < 0)
 			return ret;
 
@@ -651,7 +690,7 @@ static int check_chipid(struct common_hnd *chnd)
 	}
 	/* compute embedded flash size from CHIPVER field */
 	if (chnd->flash_cmd_v2)
-		chnd->flash_size = v2[(ver & 0xF0)>>5] * 1024;
+		chnd->flash_size = v2[(ver & 0xF0) >> 5] * 1024;
 	else
 		chnd->flash_size = (128 + (ver & 0xF0)) * 1024;
 
@@ -661,29 +700,7 @@ static int check_chipid(struct common_hnd *chnd)
 	}
 
 	printf("CHIPID %05x, CHIPVER %02x, Flash size %d kB\n", id, ver,
-		chnd->flash_size / 1024);
-
-	return 0;
-}
-
-/* DBGR Reset */
-static int dbgr_reset(struct common_hnd *chnd, unsigned char val)
-{
-	int ret = 0;
-
-	/* Reset CPU only, and we keep power state until flashing is done. */
-	if (chnd->dbgr_addr_3bytes)
-		ret |= i2c_write_byte(chnd, 0x80, 0xf0);
-
-	ret |= i2c_write_byte(chnd, 0x2f, 0x20);
-	ret |= i2c_write_byte(chnd, 0x2e, 0x06);
-
-	/* Enable the Reset Status by val */
-	ret |= i2c_write_byte(chnd, 0x30, val);
-
-	ret |= i2c_write_byte(chnd, 0x27, 0x80);
-	if (ret < 0)
-		fprintf(stderr, "DBGR RESET FAILED\n");
+	       chnd->flash_size / 1024);
 
 	return 0;
 }
@@ -755,7 +772,7 @@ static int dbgr_disable_protect_path(struct common_hnd *chnd)
 
 	ret |= i2c_write_byte(chnd, 0x2f, 0x20);
 	for (i = 0; i < 32; i++) {
-		ret |= i2c_write_byte(chnd, 0x2e, 0xa0+i);
+		ret |= i2c_write_byte(chnd, 0x2e, 0xa0 + i);
 		ret |= i2c_write_byte(chnd, 0x30, 0);
 	}
 
@@ -794,8 +811,8 @@ static int spi_flash_follow_mode_exit(struct common_hnd *chnd, char *desc)
 
 	ret = (ret ? -EIO : 0);
 	if (ret < 0)
-		fprintf(stderr, "Flash %s exit follow mode FAILED (%d)\n",
-			desc, ret);
+		fprintf(stderr, "Flash %s exit follow mode FAILED (%d)\n", desc,
+			ret);
 
 	return ret;
 }
@@ -815,8 +832,8 @@ static int dbgr_stop_ec(struct common_hnd *chnd)
 }
 
 /* SPI Flash generic command, short version */
-static int spi_flash_command_short(struct common_hnd *chnd,
-				   uint8_t cmd, char *desc)
+static int spi_flash_command_short(struct common_hnd *chnd, uint8_t cmd,
+				   char *desc)
 {
 	int ret = 0;
 
@@ -833,8 +850,8 @@ static int spi_flash_command_short(struct common_hnd *chnd,
 }
 
 /* SPI Flash set erase page */
-static int spi_flash_set_erase_page(struct common_hnd *chnd,
-				    int page, char *desc)
+static int spi_flash_set_erase_page(struct common_hnd *chnd, int page,
+				    char *desc)
 {
 	int ret = 0;
 
@@ -856,7 +873,7 @@ static int spi_poll_busy(struct common_hnd *chnd, char *desc)
 	int ret = -EIO;
 
 	if (spi_flash_command_short(chnd, SPI_CMD_READ_STATUS,
-		"read status for busy bit") < 0) {
+				    "read status for busy bit") < 0) {
 		fprintf(stderr, "Flash %s wait busy cleared FAILED\n", desc);
 		goto failed_read_status;
 	}
@@ -883,7 +900,7 @@ static int spi_check_write_enable(struct common_hnd *chnd, char *desc)
 	int ret = -EIO;
 
 	if (spi_flash_command_short(chnd, SPI_CMD_READ_STATUS,
-		"read status for write enable bit") < 0) {
+				    "read status for write enable bit") < 0) {
 		fprintf(stderr, "Flash %s wait WE FAILED\n", desc);
 		goto failed_read_status;
 	}
@@ -909,12 +926,8 @@ static int ftdi_config_i2c(struct ftdi_context *ftdi)
 	int ret;
 	static const uint16_t divisor =
 		60000000 / (2 * FTDI_I2C_FREQ * 3 / 2 /* 3-phase CLK */) - 1;
-	uint8_t clock_buf[] = {
-		EN_3_PHASE,
-		DIS_DIV_5,
-		TCK_DIVISOR,
-		divisor & 0xff,
-		divisor >> 8};
+	uint8_t clock_buf[] = { EN_3_PHASE, DIS_DIV_5, TCK_DIVISOR,
+				divisor & 0xff, divisor >> 8 };
 
 	ret = ftdi_set_latency_timer(ftdi, 16 /* ms */);
 	if (ret < 0)
@@ -945,7 +958,7 @@ static int ftdi_config_i2c(struct ftdi_context *ftdi)
 
 /* Special waveform definition */
 #define SPECIAL_LEN_USEC 50000ULL /* us */
-#define SPECIAL_FREQ    400000ULL
+#define SPECIAL_FREQ 400000ULL
 
 #define SPECIAL_PATTERN 0x0000020301010302ULL
 #define SPECIAL_PATTERN_SDA_L_SCL_L 0x0000000000000000ULL
@@ -954,7 +967,7 @@ static int ftdi_config_i2c(struct ftdi_context *ftdi)
 #define SPECIAL_PATTERN_SDA_H_SCL_H 0x0303030303030303ULL
 #define TICK_COUNT 24
 
-#define MSEC    1000
+#define MSEC 1000
 #define USEC 1000000
 
 #define SPECIAL_BUFFER_SIZE \
@@ -969,8 +982,8 @@ static int connect_to_ccd_i2c_bridge(struct common_hnd *chnd)
 			CR50_I2C_PROTOCOL, &chnd->uep);
 
 	if (rv) {
-		fprintf(stderr, "%s: usb_findit returned error %d\n",
-			__func__, rv);
+		fprintf(stderr, "%s: usb_findit returned error %d\n", __func__,
+			rv);
 	}
 
 	return rv;
@@ -980,13 +993,11 @@ static int ccd_trigger_special_waveform(struct common_hnd *chnd)
 {
 	uint8_t response[20];
 	size_t rsize;
-	uint8_t req[] = {
-		0, /* Port 0. Might be necessary to modify. */
-		CROS_CMD_ADDR, /* Chrome OS dedicated address. */
-		1,	/* Will send a single byte command. */
-		0,	/* No need to read back anything. */
-		CROS_CMD_ITE_SYNC
-	};
+	uint8_t req[] = { 0, /* Port 0. Might be necessary to modify. */
+			  CROS_CMD_ADDR, /* Chrome OS dedicated address. */
+			  1, /* Will send a single byte command. */
+			  0, /* No need to read back anything. */
+			  CROS_CMD_ITE_SYNC };
 
 	usb_trx(&chnd->uep, req, sizeof(req), response, sizeof(response), 1,
 		&rsize);
@@ -1013,7 +1024,7 @@ static int ftdi_send_special_waveform(struct common_hnd *chnd)
 	int i;
 	uint64_t *wave;
 	struct ftdi_context *ftdi = chnd->ftdi_hnd;
-	uint8_t release_lines[] = {SET_BITS_LOW, 0, 0};
+	uint8_t release_lines[] = { SET_BITS_LOW, 0, 0 };
 
 	wave = malloc(SPECIAL_BUFFER_SIZE);
 	if (!wave) {
@@ -1052,7 +1063,7 @@ static int ftdi_send_special_waveform(struct common_hnd *chnd)
 	usleep(5000);
 
 	/* program each special tick */
-	for (i = 0; i < TICK_COUNT; ) {
+	for (i = 0; i < TICK_COUNT;) {
 		wave[i++] = SPECIAL_PATTERN_SDA_L_SCL_L;
 		wave[i++] = SPECIAL_PATTERN_SDA_H_SCL_L;
 		wave[i++] = SPECIAL_PATTERN_SDA_L_SCL_L;
@@ -1076,7 +1087,7 @@ static int ftdi_send_special_waveform(struct common_hnd *chnd)
 	ftdi_config_i2c(ftdi);
 	ftdi_write_data(ftdi, release_lines, sizeof(release_lines));
 
- free_and_return:
+free_and_return:
 	free(wave);
 	return ret;
 }
@@ -1088,7 +1099,8 @@ static int send_special_waveform(struct common_hnd *chnd)
 	int iterations;
 
 	if (!chnd->conf.i2c_if->send_special_waveform) {
-		fprintf(stderr, "This binary does not support sending the ITE "
+		fprintf(stderr,
+			"This binary does not support sending the ITE "
 			"special waveform with the chosen I2C interface.\n");
 		return -1;
 	}
@@ -1114,7 +1126,7 @@ static int send_special_waveform(struct common_hnd *chnd)
 			ret = -1;
 			if (!(iterations % max_iterations))
 				fprintf(stderr, "!please reset EC if flashing"
-					" sequence is not starting!\n");
+						" sequence is not starting!\n");
 		}
 	} while (ret && (iterations++ < max_iterations));
 
@@ -1127,10 +1139,10 @@ static int send_special_waveform(struct common_hnd *chnd)
 }
 
 static int windex;
-static const char wheel[] = {'|', '/', '-', '\\' };
+static const char wheel[] = { '|', '/', '-', '\\' };
 static void draw_spinner(uint32_t remaining, uint32_t size)
 {
-	int percent = (size - remaining)*100/size;
+	int percent = (size - remaining) * 100 / size;
 	fprintf(stderr, "\r%c%3d%%", wheel[windex++], percent);
 	windex %= sizeof(wheel);
 }
@@ -1145,8 +1157,8 @@ static int spi_send_cmd_fast_read(struct common_hnd *chnd, uint32_t addr)
 	ret = spi_flash_command_short(chnd, SPI_CMD_FAST_READ, "fast read");
 	/* Send address */
 	ret |= i2c_write_byte(chnd, 0x08, ((addr >> 16) & 0xff)); /* addr_h */
-	ret |= i2c_write_byte(chnd, 0x08, ((addr >> 8) & 0xff));  /* addr_m */
-	ret |= i2c_write_byte(chnd, 0x08, (addr & 0xff));         /* addr_l */
+	ret |= i2c_write_byte(chnd, 0x08, ((addr >> 8) & 0xff)); /* addr_m */
+	ret |= i2c_write_byte(chnd, 0x08, (addr & 0xff)); /* addr_l */
 	/* fake byte */
 	ret |= i2c_write_byte(chnd, 0x08, 0x00);
 	/* use i2c block read command */
@@ -1165,8 +1177,10 @@ static int command_read_pages(struct common_hnd *chnd, uint32_t address,
 	int cnt;
 
 	if (address & 0xFF) {
-		fprintf(stderr, "page read requested at non-page boundary: "
-			"0x%X\n", address);
+		fprintf(stderr,
+			"page read requested at non-page boundary: "
+			"0x%X\n",
+			address);
 		return -EINVAL;
 	}
 
@@ -1206,6 +1220,18 @@ static int command_read_pages(struct common_hnd *chnd, uint32_t address,
 	return res;
 }
 
+static bool is_empty_page(uint8_t *buffer, int size)
+{
+	int i;
+
+	for (i = 0; i < size; i++) {
+		if (buffer[i] != 0xFF)
+			return false;
+	}
+
+	return true;
+}
+
 static int command_write_pages(struct common_hnd *chnd, uint32_t address,
 			       uint32_t size, uint8_t *buffer)
 {
@@ -1220,8 +1246,8 @@ static int command_write_pages(struct common_hnd *chnd, uint32_t address,
 		goto failed_write;
 
 	while (remaining) {
-		cnt = (remaining > block_write_size) ?
-			block_write_size : remaining;
+		cnt = (remaining > block_write_size) ? block_write_size :
+						       remaining;
 		addr_H = (address >> 16) & 0xFF;
 		addr_M = (address >> 8) & 0xFF;
 		addr_L = address & 0xFF;
@@ -1230,7 +1256,7 @@ static int command_write_pages(struct common_hnd *chnd, uint32_t address,
 
 		/* Write enable */
 		if (spi_flash_command_short(chnd, SPI_CMD_WRITE_ENABLE,
-			"write enable for AAI write") < 0)
+					    "write enable for AAI write") < 0)
 			goto failed_write;
 
 		/* Check write enable bit */
@@ -1239,7 +1265,7 @@ static int command_write_pages(struct common_hnd *chnd, uint32_t address,
 
 		/* Setup write */
 		if (spi_flash_command_short(chnd, SPI_CMD_WORD_PROGRAM,
-			"AAI write") < 0)
+					    "AAI write") < 0)
 			goto failed_write;
 
 		/* Set eflash page address */
@@ -1248,7 +1274,7 @@ static int command_write_pages(struct common_hnd *chnd, uint32_t address,
 		res |= i2c_byte_transfer(chnd, I2C_DATA_ADDR, &addr_L, 1, 1);
 		if (res < 0) {
 			fprintf(stderr, "Flash write set page FAILED (%d)\n",
-					res);
+				res);
 			goto failed_write;
 		}
 
@@ -1271,13 +1297,13 @@ static int command_write_pages(struct common_hnd *chnd, uint32_t address,
 		res |= i2c_write_byte(chnd, 0x10, 0x00);
 		if (res < 0) {
 			fprintf(stderr, "Flash end data write FAILED (%d)\n",
-					res);
+				res);
 			goto failed_write;
 		}
 
 		/* Write disable */
 		if (spi_flash_command_short(chnd, SPI_CMD_WRITE_DISABLE,
-			"write disable for AAI write") < 0)
+					    "write disable for AAI write") < 0)
 			goto failed_write;
 
 		/* Wait until available */
@@ -1292,7 +1318,7 @@ static int command_write_pages(struct common_hnd *chnd, uint32_t address,
 	res = size;
 failed_write:
 	if (spi_flash_command_short(chnd, SPI_CMD_WRITE_DISABLE,
-		"write disable exit AAI write") < 0)
+				    "write disable exit AAI write") < 0)
 		res = -EIO;
 
 	if (spi_flash_follow_mode_exit(chnd, "AAI write") < 0)
@@ -1312,13 +1338,13 @@ static int command_write_pages3(struct common_hnd *chnd, uint32_t address,
 
 	/* SMB_SPI_Flash_Write_Enable */
 	if (spi_flash_command_short(chnd, SPI_CMD_WRITE_ENABLE,
-		"SPI Command Write Enable") < 0) {
+				    "SPI Command Write Enable") < 0) {
 		ret = -EIO;
 		goto failed_write;
 	}
 
 	if (spi_flash_command_short(chnd, SPI_CMD_PAGE_PROGRAM,
-		"SPI_CMD_PAGE_PROGRAM") < 0) {
+				    "SPI_CMD_PAGE_PROGRAM") < 0) {
 		ret = -EIO;
 		goto failed_write;
 	}
@@ -1343,8 +1369,6 @@ static int command_write_pages3(struct common_hnd *chnd, uint32_t address,
 	return ret;
 }
 
-
-
 static int command_erase(struct common_hnd *chnd, uint32_t len, uint32_t off)
 {
 	int res = -EIO;
@@ -1365,7 +1389,7 @@ static int command_erase(struct common_hnd *chnd, uint32_t len, uint32_t off)
 		draw_spinner(remaining, len);
 
 		if (spi_flash_command_short(chnd, SPI_CMD_WRITE_ENABLE,
-			"write enable for erase") < 0)
+					    "write enable for erase") < 0)
 			goto failed_erase;
 
 		if (spi_check_write_enable(chnd, "erase") < 0)
@@ -1374,28 +1398,28 @@ static int command_erase(struct common_hnd *chnd, uint32_t len, uint32_t off)
 		/* do chip erase */
 		if (remaining == chnd->flash_size) {
 			if (spi_flash_command_short(chnd, SPI_CMD_CHIP_ERASE,
-				"chip erase") < 0)
+						    "chip erase") < 0)
 				goto failed_erase;
 			goto wait_busy_cleared;
 		}
 
 		/* do sector erase */
 		if (spi_flash_command_short(chnd, spi_cmd_sector_erase,
-			"sector erase") < 0)
+					    "sector erase") < 0)
 			goto failed_erase;
 
 		if (spi_flash_set_erase_page(chnd, page, "sector erase") < 0)
 			goto failed_erase;
 
-wait_busy_cleared:
+	wait_busy_cleared:
 		if (spi_poll_busy(chnd, "erase") < 0)
 			goto failed_erase;
 
 		if (spi_flash_command_short(chnd, SPI_CMD_WRITE_DISABLE,
-			"write disable for erase") < 0)
+					    "write disable for erase") < 0)
 			goto failed_erase;
 
-		if (remaining == chnd->flash_size)  {
+		if (remaining == chnd->flash_size) {
 			remaining = 0;
 			draw_spinner(remaining, len);
 		} else {
@@ -1410,7 +1434,7 @@ static int command_erase(struct common_hnd *chnd, uint32_t len, uint32_t off)
 
 failed_erase:
 	if (spi_flash_command_short(chnd, SPI_CMD_WRITE_DISABLE,
-		"write disable exit erase") < 0)
+				    "write disable exit erase") < 0)
 		res = -EIO;
 
 	if (spi_flash_follow_mode_exit(chnd, "erase") < 0)
@@ -1425,8 +1449,8 @@ static int command_erase(struct common_hnd *chnd, uint32_t len, uint32_t off)
  * reset issue while flash.
  * Add such function to prevent the reset issue.
  */
-static int command_erase2(struct common_hnd *chnd, uint32_t len,
-			  uint32_t off, uint32_t reset)
+static int command_erase2(struct common_hnd *chnd, uint32_t len, uint32_t off,
+			  uint32_t reset)
 {
 	int res = -EIO;
 	int page = 0;
@@ -1450,11 +1474,10 @@ static int command_erase2(struct common_hnd *chnd, uint32_t len,
 		goto failed_erase;
 
 	while (remaining) {
-
 		draw_spinner(remaining, len);
 
 		if (spi_flash_command_short(chnd, SPI_CMD_WRITE_ENABLE,
-			"write enable for erase") < 0)
+					    "write enable for erase") < 0)
 			goto failed_erase;
 
 		if (spi_check_write_enable(chnd, "erase") < 0)
@@ -1462,7 +1485,7 @@ static int command_erase2(struct common_hnd *chnd, uint32_t len,
 
 		/* do sector erase */
 		if (spi_flash_command_short(chnd, spi_cmd_sector_erase,
-			"sector erase") < 0)
+					    "sector erase") < 0)
 			goto failed_erase;
 
 		if (spi_flash_set_erase_page(chnd, page, "sector erase") < 0)
@@ -1472,7 +1495,7 @@ static int command_erase2(struct common_hnd *chnd, uint32_t len,
 			goto failed_erase;
 
 		if (spi_flash_command_short(chnd, SPI_CMD_WRITE_DISABLE,
-			"write disable for erase") < 0)
+					    "write disable for erase") < 0)
 			goto failed_erase;
 
 		if (reset) {
@@ -1483,7 +1506,6 @@ static int command_erase2(struct common_hnd *chnd, uint32_t len,
 		page += sector_erase_pages;
 		remaining -= sector_erase_pages * PAGE_SIZE;
 		draw_spinner(remaining, len);
-
 	}
 
 	/* No error so far */
@@ -1492,7 +1514,7 @@ static int command_erase2(struct common_hnd *chnd, uint32_t len,
 
 failed_erase:
 	if (spi_flash_command_short(chnd, SPI_CMD_WRITE_DISABLE,
-		"write disable exit erase") < 0)
+				    "write disable exit erase") < 0)
 		res = -EIO;
 
 	if (spi_flash_follow_mode_exit(chnd, "erase") < 0)
@@ -1586,8 +1608,10 @@ static int write_flash(struct common_hnd *chnd, const char *filename,
 	}
 	res = fread(buffer, 1, size, hnd);
 	if (res <= 0) {
-		fprintf(stderr, "%s: Failed to read %d bytes from %s with "
-			"ferror() %d\n", __func__, size, filename, ferror(hnd));
+		fprintf(stderr,
+			"%s: Failed to read %d bytes from %s with "
+			"ferror() %d\n",
+			__func__, size, filename, ferror(hnd));
 		free(buffer);
 		fclose(hnd);
 		return -EIO;
@@ -1640,8 +1664,10 @@ static int write_flash2(struct common_hnd *chnd, const char *filename,
 	}
 	res = fread(buffer, 1, size, hnd);
 	if (res <= 0) {
-		fprintf(stderr, "%s: Failed to read %d bytes from %s with "
-			"ferror() %d\n", __func__, size, filename, ferror(hnd));
+		fprintf(stderr,
+			"%s: Failed to read %d bytes from %s with "
+			"ferror() %d\n",
+			__func__, size, filename, ferror(hnd));
 		fclose(hnd);
 		free(buffer);
 		return -EIO;
@@ -1671,7 +1697,8 @@ static int write_flash2(struct common_hnd *chnd, const char *filename,
 	ret |= i2c_byte_transfer(chnd, I2C_DATA_ADDR, &addr_l, 1, 1);
 	/* Send first two bytes of buffe */
 	ret |= i2c_byte_transfer(chnd, I2C_DATA_ADDR, &buffer[offset], 1, 1);
-	ret |= i2c_byte_transfer(chnd, I2C_DATA_ADDR, &buffer[offset+1], 1, 1);
+	ret |= i2c_byte_transfer(chnd, I2C_DATA_ADDR, &buffer[offset + 1], 1,
+				 1);
 	/* we had sent two bytes */
 	offset += 2;
 	res -= 2;
@@ -1693,8 +1720,8 @@ static int write_flash2(struct common_hnd *chnd, const char *filename,
 			two_bytes_sent = 0;
 			cnt -= 2;
 		}
-		if (i2c_byte_transfer(chnd, I2C_BLOCK_ADDR, &buffer[offset],
-			1, cnt) < 0) {
+		if (i2c_byte_transfer(chnd, I2C_BLOCK_ADDR, &buffer[offset], 1,
+				      cnt) < 0) {
 			ret = -EIO;
 			goto failed_write;
 		}
@@ -1710,7 +1737,7 @@ static int write_flash2(struct common_hnd *chnd, const char *filename,
 			i2c_write_byte(chnd, 0x10, 0x00);
 			/* write disable command */
 			spi_flash_command_short(chnd, SPI_CMD_WRITE_DISABLE,
-				"SPI write disable");
+						"SPI write disable");
 			goto __send_aai_cmd;
 		}
 	}
@@ -1721,7 +1748,7 @@ static int write_flash2(struct common_hnd *chnd, const char *filename,
 	i2c_write_byte(chnd, 0x10, 0x00);
 	/* write disable command */
 	spi_flash_command_short(chnd, SPI_CMD_WRITE_DISABLE,
-		"SPI write disable");
+				"SPI write disable");
 failed_enter_mode:
 	/* exit follow mode */
 	spi_flash_follow_mode_exit(chnd, "AAI write");
@@ -1768,8 +1795,10 @@ static int write_flash3(struct common_hnd *chnd, const char *filename,
 	}
 	res = fread(buf, 1, size, hnd);
 	if (res <= 0) {
-		fprintf(stderr, "%s: Failed to read %d bytes from %s with "
-			"ferror() %d\n", __func__, size, filename, ferror(hnd));
+		fprintf(stderr,
+			"%s: Failed to read %d bytes from %s with "
+			"ferror() %d\n",
+			__func__, size, filename, ferror(hnd));
 		fclose(hnd);
 		free(buf);
 		return -EIO;
@@ -1789,7 +1818,10 @@ static int write_flash3(struct common_hnd *chnd, const char *filename,
 
 	while (res) {
 		cnt = (res > block_write_size) ? block_write_size : res;
-		if (command_write_pages3(chnd, offset, cnt, &buf[offset]) < 0) {
+		if (chnd->conf.erase && is_empty_page(&buf[offset], cnt)) {
+			/* do nothing */
+		} else if (command_write_pages3(chnd, offset, cnt,
+						&buf[offset]) < 0) {
 			ret = -EIO;
 			goto failed_write;
 		}
@@ -1802,7 +1834,7 @@ static int write_flash3(struct common_hnd *chnd, const char *filename,
 failed_write:
 	free(buf);
 	spi_flash_command_short(chnd, SPI_CMD_WRITE_DISABLE,
-		"SPI write disable");
+				"SPI write disable");
 	spi_flash_follow_mode_exit(chnd, "Page program");
 	if (ret < 0)
 		fprintf(stderr, "%s: Error writing to flash\n", __func__);
@@ -1812,8 +1844,6 @@ static int write_flash3(struct common_hnd *chnd, const char *filename,
 	return ret;
 }
 
-
-
 /* Return zero on success, a non-zero value on failures. */
 static int verify_flash(struct common_hnd *chnd, const char *filename,
 			uint32_t offset)
@@ -1821,7 +1851,7 @@ static int verify_flash(struct common_hnd *chnd, const char *filename,
 	int res;
 	int file_size;
 	FILE *hnd;
-	uint8_t *buffer  = malloc(chnd->flash_size);
+	uint8_t *buffer = malloc(chnd->flash_size);
 	uint8_t *buffer2 = malloc(chnd->flash_size);
 
 	if (!buffer || !buffer2) {
@@ -1842,9 +1872,10 @@ static int verify_flash(struct common_hnd *chnd, const char *filename,
 
 	file_size = fread(buffer, 1, chnd->flash_size, hnd);
 	if (file_size <= 0) {
-		fprintf(stderr, "%s: Failed to read %d bytes from %s with "
-			"ferror() %d\n", __func__, chnd->flash_size, filename,
-			ferror(hnd));
+		fprintf(stderr,
+			"%s: Failed to read %d bytes from %s with "
+			"ferror() %d\n",
+			__func__, chnd->flash_size, filename, ferror(hnd));
 		fclose(hnd);
 		res = -EIO;
 		goto exit;
@@ -1864,8 +1895,8 @@ static int verify_flash(struct common_hnd *chnd, const char *filename,
 	return res;
 }
 
-static struct ftdi_context *open_ftdi_device(int vid, int pid,
-					     int interface, const char *serial)
+static struct ftdi_context *open_ftdi_device(int vid, int pid, int interface,
+					     const char *serial)
 {
 	struct ftdi_context *ftdi;
 	int ret;
@@ -1905,17 +1936,19 @@ static int linux_i2c_interface_init(struct common_hnd *chnd)
 		return -1;
 	}
 	printf("Attempting to open Linux i2c-dev path %s\n",
-		chnd->conf.i2c_dev_path);
+	       chnd->conf.i2c_dev_path);
 	chnd->i2c_dev_fd = open(chnd->conf.i2c_dev_path, O_RDWR);
 	if (chnd->i2c_dev_fd < 0) {
 		err = errno;
 		perror("Failed to open Linux i2c-dev file path with error");
-		fprintf(stderr, "Linux i2c-dev file path from --i2c_dev_path "
-			"is: %s\n", chnd->conf.i2c_dev_path);
+		fprintf(stderr,
+			"Linux i2c-dev file path from --i2c_dev_path "
+			"is: %s\n",
+			chnd->conf.i2c_dev_path);
 		return err ? err : -1;
 	}
 	printf("Successfully opened Linux i2c-dev path %s\n",
-		chnd->conf.i2c_dev_path);
+	       chnd->conf.i2c_dev_path);
 	return 0;
 }
 
@@ -1924,15 +1957,15 @@ static int linux_i2c_interface_shutdown(struct common_hnd *chnd)
 	int err;
 
 	printf("Attempting to close Linux i2c-dev file descriptor %d\n",
-		chnd->i2c_dev_fd);
+	       chnd->i2c_dev_fd);
 	if (close(chnd->i2c_dev_fd)) {
 		err = errno;
 		perror("Failed to close Linux i2c-dev file descriptor with "
-			"error");
+		       "error");
 		return err ? err : -1;
 	}
 	printf("Successfully closed Linux i2c-dev file descriptor %d\n",
-		chnd->i2c_dev_fd);
+	       chnd->i2c_dev_fd);
 	return 0;
 }
 
@@ -1952,8 +1985,9 @@ static int ccd_i2c_interface_shutdown(struct common_hnd *chnd)
 static int ftdi_i2c_interface_init(struct common_hnd *chnd)
 {
 	chnd->ftdi_hnd = open_ftdi_device(chnd->conf.usb_vid,
-		chnd->conf.usb_pid, chnd->conf.usb_interface,
-		chnd->conf.usb_serial);
+					  chnd->conf.usb_pid,
+					  chnd->conf.usb_interface,
+					  chnd->conf.usb_serial);
 	if (chnd->ftdi_hnd == NULL)
 		return -1;
 	return 0;
@@ -2046,30 +2080,31 @@ static int strdup_with_errmsg(const char *source, char **dest, const char *name)
 	return ret;
 }
 
-static const struct option longopts[] = {
-	{"block-write-size", 1, 0, 'b'},
-	{"debug", 0, 0, 'd'},
-	{"erase", 0, 0, 'e'},
-	{"help", 0, 0, 'h'},
-	{"i2c-dev-path", 1, 0, 'D'},
-	{"i2c-interface", 1, 0, 'c'},
-	{"i2c-mux", 0, 0, 'm'},
-	{"interface", 1, 0, 'i'},
-	{"nodisable-protect-path", 0, 0, 'Z'},
-	{"nodisable-watchdog", 0, 0, 'z'},
-	{"product", 1, 0, 'p'},
-	{"range", 1, 0, 'R'},
-	{"read", 1, 0, 'r'},
-	{"send-waveform", 1, 0, 'W'},
-	{"serial", 1, 0, 's'},
-	{"vendor", 1, 0, 'v'},
-	{"write", 1, 0, 'w'},
-	{NULL, 0, 0, 0}
-};
+static const struct option longopts[] = { { "block-write-size", 1, 0, 'b' },
+					  { "debug", 0, 0, 'd' },
+					  { "erase", 0, 0, 'e' },
+					  { "help", 0, 0, 'h' },
+					  { "i2c-dev-path", 1, 0, 'D' },
+					  { "i2c-interface", 1, 0, 'c' },
+					  { "i2c-mux", 0, 0, 'm' },
+					  { "interface", 1, 0, 'i' },
+					  { "nodisable-protect-path", 0, 0,
+					    'Z' },
+					  { "nodisable-watchdog", 0, 0, 'z' },
+					  { "noverify", 0, 0, 'n' },
+					  { "product", 1, 0, 'p' },
+					  { "range", 1, 0, 'R' },
+					  { "read", 1, 0, 'r' },
+					  { "send-waveform", 1, 0, 'W' },
+					  { "serial", 1, 0, 's' },
+					  { "vendor", 1, 0, 'v' },
+					  { "write", 1, 0, 'w' },
+					  { NULL, 0, 0, 0 } };
 
 static void display_usage(const char *program)
 {
-	fprintf(stderr, "Usage: %s [-d] [-v <VID>] [-p <PID>] \\\n"
+	fprintf(stderr,
+		"Usage: %s [-d] [-v <VID>] [-p <PID>] \\\n"
 		"\t[-c <linux|ccd|ftdi>] [-D /dev/i2c-<N>] [-i <1|2>] [-S] \\\n"
 		"\t[-s <serial>] [-e] [-r <file>] [-W <0|1|false|true>] \\\n"
 		"\t[-w <file>] [-R base[:size]] [-m] [-b <size>]\n",
@@ -2083,13 +2118,16 @@ static void display_usage(const char *program)
 			"\tonly applicable with --i2c-interface=linux\n");
 	fprintf(stderr, "-i, --interface <1> : FTDI interface: A=1, B=2,"
 			" ...\n");
-	fprintf(stderr, "-m, --i2c-mux : Enable i2c-mux (to EC).\n"
+	fprintf(stderr,
+		"-m, --i2c-mux : Enable i2c-mux (to EC).\n"
 		"\tSpecify this flag only if the board has an I2C MUX and\n"
 		"\tyou are not using servod.\n");
+	fprintf(stderr, "-n, --noverify : Don't auto verify.\n");
 	fprintf(stderr, "-b, --block-write-size <size> : Perform writes in\n"
-		"\tblocks of this many bytes.\n");
+			"\tblocks of this many bytes.\n");
 	fprintf(stderr, "-p, --product <0x1234> : USB product ID\n");
-	fprintf(stderr, "-R, --range base[:size] : Allow to read or write"
+	fprintf(stderr,
+		"-R, --range base[:size] : Allow to read or write"
 		" just a slice\n"
 		"\tof the file, starting at <base>:<size> bytes, or til\n"
 		"\tthe end of the file if <size> is not specified, expressed\n"
@@ -2098,15 +2136,16 @@ static void display_usage(const char *program)
 			" write it into <file>.\n");
 	fprintf(stderr, "-s, --serial <serialname> : USB serial string\n");
 	fprintf(stderr, "-v, --vendor <0x1234> : USB vendor ID\n");
-	fprintf(stderr, "-W, --send-waveform <0|1|false|true> : Send the"
+	fprintf(stderr,
+		"-W, --send-waveform <0|1|false|true> : Send the"
 		" special waveform.\n"
 		"\tDefault is true. Set to false if ITE direct firmware\n"
 		"\tupdate mode has already been enabled.\n");
 	fprintf(stderr, "-w, --write <file> : Write <file> to flash.\n");
 	fprintf(stderr, "-z, --nodisable-watchdog : Do *not* disable EC "
-		"watchdog.\n");
+			"watchdog.\n");
 	fprintf(stderr, "-Z, --nodisable-protect-path : Do *not* disable EC "
-		"protect path.\n");
+			"protect path.\n");
 }
 
 /*
@@ -2118,11 +2157,11 @@ static int parse_range_options(char *str, struct iteflash_config *conf)
 	char *size;
 
 	if (!str) {
-		fprintf(stderr,	"missing range base address specification\n");
+		fprintf(stderr, "missing range base address specification\n");
 		return -1;
 	}
 
-	conf->range_base = strtoul(str, &size, 16);
+	conf->range_base = strtoull(str, &size, 16);
 	if (!size || !*size)
 		return 0;
 
@@ -2136,7 +2175,7 @@ static int parse_range_options(char *str, struct iteflash_config *conf)
 		return -1;
 	}
 
-	conf->range_size = strtoul(size, &size, 16);
+	conf->range_size = strtoull(size, &size, 16);
 	if ((size && *size) || !conf->range_size) {
 		fprintf(stderr, "wrong range size specification\n");
 		return -1;
@@ -2164,14 +2203,16 @@ static int parse_parameters(int argc, char **argv, struct iteflash_config *conf)
 			} else if (!strcasecmp(optarg, "ftdi")) {
 				conf->i2c_if = &ftdi_i2c_interface;
 			} else {
-				fprintf(stderr, "Unexpected -c / "
-					"--i2c-interface value: %s\n", optarg);
+				fprintf(stderr,
+					"Unexpected -c / "
+					"--i2c-interface value: %s\n",
+					optarg);
 				ret = -1;
 			}
 			break;
 		case 'D':
 			ret = strdup_with_errmsg(optarg, &conf->i2c_dev_path,
-				"-D / --i2c-dev-path");
+						 "-D / --i2c-dev-path");
 			break;
 		case 'd':
 			conf->debug = 1;
@@ -2190,6 +2231,9 @@ static int parse_parameters(int argc, char **argv, struct iteflash_config *conf)
 		case 'm':
 			conf->i2c_mux = 1;
 			break;
+		case 'n':
+			conf->verify = 0;
+			break;
 		case 'p':
 			conf->usb_pid = strtol(optarg, NULL, 16);
 			break;
@@ -2198,11 +2242,11 @@ static int parse_parameters(int argc, char **argv, struct iteflash_config *conf)
 			break;
 		case 'r':
 			ret = strdup_with_errmsg(optarg, &conf->input_filename,
-				"-r / --read");
+						 "-r / --read");
 			break;
 		case 's':
 			ret = strdup_with_errmsg(optarg, &conf->usb_serial,
-				"-s / --serial");
+						 "-s / --serial");
 			break;
 		case 'v':
 			conf->usb_vid = strtol(optarg, NULL, 16);
@@ -2218,13 +2262,15 @@ static int parse_parameters(int argc, char **argv, struct iteflash_config *conf)
 				conf->send_waveform = 1;
 				break;
 			}
-			fprintf(stderr, "Unexpected -W / --special-waveform "
-				"value: %s\n", optarg);
+			fprintf(stderr,
+				"Unexpected -W / --special-waveform "
+				"value: %s\n",
+				optarg);
 			ret = -1;
 			break;
 		case 'w':
 			ret = strdup_with_errmsg(optarg, &conf->output_filename,
-				"-w / --write");
+						 "-w / --write");
 			break;
 		case 'z':
 			conf->disable_watchdog = 0;
@@ -2242,15 +2288,18 @@ static int parse_parameters(int argc, char **argv, struct iteflash_config *conf)
 
 static void sighandler(int signum)
 {
-	printf("\nCaught signal %d: %s\nExiting...\n",
-		signum, sys_siglist[signum]);
-	exit_requested = 1;
+	int status;
+	printf("\nCaught signal %d: %s\nExiting...\n", signum,
+	       strsignal(signum));
+	wait(&status);
+	exit_requested = status;
 }
 
 static void register_sigaction(void)
 {
 	struct sigaction sigact;
 
+	memset(&sigact, 0, sizeof(sigact));
 	sigact.sa_handler = sighandler;
 	sigemptyset(&sigact.sa_mask);
 	sigact.sa_flags = 0;
@@ -2271,6 +2320,7 @@ int main(int argc, char **argv)
 			.usb_interface = SERVO_INTERFACE,
 			.usb_vid = SERVO_USB_VID,
 			.usb_pid = SERVO_USB_PID,
+			.verify = 1,
 			.i2c_if = &ftdi_i2c_interface,
 		},
 	};
@@ -2310,7 +2360,8 @@ int main(int argc, char **argv)
 
 		ret = check_chipid(&chnd);
 		if (ret) {
-			fprintf(stderr, "Failed to get ITE chip ID.  This "
+			fprintf(stderr,
+				"Failed to get ITE chip ID.  This "
 				"could be because the ITE direct firmware "
 				"update (DFU) mode is not enabled.\n");
 			goto return_after_init;
@@ -2356,20 +2407,18 @@ int main(int argc, char **argv)
 			command_erase2(&chnd, chnd.flash_size, 0, 0);
 		else
 			command_erase(&chnd, chnd.flash_size, 0);
-		/* Call DBGR Rest to clear the EC lock status after erasing */
-		dbgr_reset(&chnd, RSTS_VCCDO_PW_ON|RSTS_HGRST|RSTS_GRST);
 	}
 
 	if (chnd.conf.output_filename) {
 		if (chnd.flash_cmd_v2)
 			switch (eflash_type) {
 			case EFLASH_TYPE_8315:
-				ret = write_flash2(&chnd,
-					chnd.conf.output_filename, 0);
+				ret = write_flash2(
+					&chnd, chnd.conf.output_filename, 0);
 				break;
 			case EFLASH_TYPE_KGD:
-				ret = write_flash3(&chnd,
-					chnd.conf.output_filename, 0);
+				ret = write_flash3(
+					&chnd, chnd.conf.output_filename, 0);
 				break;
 			default:
 				printf("Invalid EFLASH TYPE!");
@@ -2380,15 +2429,17 @@ int main(int argc, char **argv)
 			ret = write_flash(&chnd, chnd.conf.output_filename, 0);
 		if (ret)
 			goto return_after_init;
-		ret = verify_flash(&chnd, chnd.conf.output_filename, 0);
-		if (ret)
-			goto return_after_init;
+		if (chnd.conf.verify) {
+			ret = verify_flash(&chnd, chnd.conf.output_filename, 0);
+			if (ret)
+				goto return_after_init;
+		}
 	}
 
 	/* Normal exit */
 	ret = 0;
 
- return_after_init:
+return_after_init:
 	/*
 	 * Exit DBGR mode. This ensures EC won't hold clock/data pins of I2C.
 	 * Avoid resetting EC here because flash_ec will after iteflash exits.
@@ -2407,7 +2458,7 @@ int main(int argc, char **argv)
 			ret = other_ret;
 	}
 
- return_after_parse:
+return_after_parse:
 	config_release(&chnd.conf);
 	return ret;
 }
diff --git a/util/iteflash.md b/util/iteflash.md
index fb4e35dc58..6f17bdcbef 100644
--- a/util/iteflash.md
+++ b/util/iteflash.md
@@ -6,7 +6,8 @@ First written: 2019-04-02
 <br>
 Last updated: 2019-04-03
 
-Familiarity with [Chromium OS](https://www.chromium.org/chromium-os) [Embedded Controller (EC) development](../README.md) is assumed.
+Familiarity with [Chromium OS](https://www.chromium.org/chromium-os) and
+[Embedded Controller (EC)](../README.md) development is assumed.
 
 [TOC]
 
@@ -14,106 +15,158 @@ Familiarity with [Chromium OS](https://www.chromium.org/chromium-os) [Embedded C
 
 ### Terminology
 
-**ITE EC** refers to the [ITE](http://www.ite.com.tw/) [IT8320](http://www.ite.com.tw/en/product/view?mid=96) [Embedded Controller (EC)](https://en.wikipedia.org/wiki/Embedded_controller) microcontroller when used as a Chromium OS / Chrome OS EC.
-
-**CrOS** refers to Chromium OS, Chrome OS, or both, depending on the context.  The distinction between Chromium OS and Chrome OS is largely immaterial to this document.
-
-**Servo** refers to a debug board providing direct debug access to various circuits on a Chrome OS device motherboard.  As of this writing, the most common [servos](https://www.chromium.org/chromium-os/servo) used by CrOS developers are [CR50 (CCD)](https://www.chromium.org/chromium-os/ccd), [Servo Micro](https://www.chromium.org/chromium-os/servo/servomicro), and [Servo v2](https://www.chromium.org/chromium-os/servo/servo-v2).  (Note that [Servo v4](https://www.chromium.org/chromium-os/servo/servov4) is **not** a Servo in this sense.  It is a USB hub with a microcontroller that proxies Servo functionality from either CR50 or Servo Micro.)  See also [Case-Closed Debug in Chromebooks and Servo Micro](https://chromium.googlesource.com/chromiumos/platform/ec/+/master/board/servo_micro/ccd.md).
+**ITE EC** refers to the [ITE](http://www.ite.com.tw/)
+[IT8320](http://www.ite.com.tw/en/product/view?mid=96)
+[Embedded Controller (EC)](https://en.wikipedia.org/wiki/Embedded_controller)
+microcontroller when used as a Chromium OS / Chrome OS EC.
+
+**CrOS** refers to Chromium OS, Chrome OS, or both, depending on the context.
+The distinction between Chromium OS and Chrome OS is largely immaterial to this
+document.
+
+**Servo** refers to a debug board providing direct debug access to various
+circuits on a Chrome OS device motherboard. As of this writing, the most common
+[servos](https://www.chromium.org/chromium-os/servo) used by CrOS developers are
+[CR50 (CCD)](https://www.chromium.org/chromium-os/ccd),
+[Servo Micro](https://www.chromium.org/chromium-os/servo/servomicro), and
+[Servo v2](https://www.chromium.org/chromium-os/servo/servo-v2). (Note that
+[Servo v4](https://www.chromium.org/chromium-os/servo/servov4) is **not** a
+Servo in this sense. It is a USB hub with a microcontroller that proxies Servo
+functionality from either CR50 or Servo Micro.) See also
+[Case-Closed Debug in Chromebooks and Servo Micro](https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/board/servo_micro/ccd.md).
 
 ### How ITE EC reflashing works
 
 An ITE EC is reflashed using a Servo by:
 
-1. Sending special non-I2C waveforms over its I2C clock and data lines, to enable a debug mode / direct firmware update (DFU) mode.
+1.  Sending special non-I2C waveforms over its I2C clock and data lines, to
+    enable a debug mode / direct firmware update (DFU) mode.
 
-1. Communicating with it using I2C, including transferring the actual EC image over I2C.  The ITE EC will only respond over I2C after receiving the special waveforms.
+1.  Communicating with it using I2C, including transferring the actual EC image
+    over I2C.  The ITE EC will only respond over I2C after receiving the special
+    waveforms.
 
 ### Further reading
 
-Googlers, and Partners involved in ITE EC projects, see [The State of ITE CrOS EC Reflashing](https://docs.google.com/document/d/1fs29eBvwKrOWYozLZXTg7ObwAO5dyM4Js2Vq301EwAU/preview).  That document is not public, do not request access if you lack it.
+* [ITE EC firmware reflashing via Servo: How it works](../docs/ite-ec-reflashing.md)
+* Googlers, and Partners involved in ITE EC projects *only*:
+[The State of ITE CrOS EC Reflashing](https://docs.google.com/document/d/1fs29eBvwKrOWYozLZXTg7ObwAO5dyM4Js2Vq301EwAU/preview)
+  * That document is not public, do not request access if you lack it.
 
 ## How to reflash
 
 ### Prerequisites for CR50 CCD
 
-This section applies whether using CR50 CCD via [Servo v4](https://www.chromium.org/chromium-os/servo/servov4) or [SuzyQ aka SuzyQable](https://www.sparkfun.com/products/14746).
+This section applies whether using CR50 CCD via
+[Servo v4](https://www.chromium.org/chromium-os/servo/servov4) or
+[SuzyQ aka SuzyQable](https://www.sparkfun.com/products/14746).
 
 CR50 MP minimum firmware version: `0.3.15`
 <br>
 CR50 pre-PVT minimum firmware version: `0.4.15`
 
-Googlers, to upgrade CR50 firmware if needed see [How to use CCD on CR50](https://docs.google.com/document/d/1MqDAoBsmGTmrFi-WNOoC5R-UFeuQK37_9kaEdCFU8QE/preview).  That document is not public, do not request access if you lack it.
+Googlers, to upgrade CR50 firmware if needed see
+[How to use CCD on CR50](https://docs.google.com/document/d/1MqDAoBsmGTmrFi-WNOoC5R-UFeuQK37_9kaEdCFU8QE/preview).
+That document is not public, do not request access if you lack it.
 
-The CR50 CCD capabilities must be set to `always`.  To achieve this:
+The CR50 CCD capabilities must be set to `always`. To achieve this:
 
-1. Open CCD.
-    * root shell: `$ gsctool -o`
-    * CR50 console: `ccd open`
-1. Reset CCD to `factory` mode.
-    * CR50 console: `ccd reset factory`
+1.  Open CCD.
+    *   root shell: `$ gsctool -o`
+    *   CR50 console: `ccd open`
+1.  Reset CCD to `factory` mode.
+    *   CR50 console: `ccd reset factory`
 
-Reflashing with CR50 also requires the [i2c-pseudo kernel module](#i2c-pseudo), unless using the [CR50 CCD sans servod](#ccd-sans-servod) alternative method.
+Reflashing with CR50 also requires the [i2c-pseudo kernel module](#i2c-pseudo),
+unless using the [CR50 CCD sans servod](#ccd-sans-servod) alternative method.
 
 ### Prerequisites for Servo Micro
 
-This section applies whether the [Servo Micro](https://www.chromium.org/chromium-os/servo/servomicro) is connected directly to your development host, or through a [Servo v4](https://www.chromium.org/chromium-os/servo/servov4).
+This section applies whether the
+[Servo Micro](https://www.chromium.org/chromium-os/servo/servomicro) is
+connected directly to your development host, or through a
+[Servo v4](https://www.chromium.org/chromium-os/servo/servov4).
 
 Servo Micro minimum firmware version: `servo_micro_v2.3.5`
 
 To upgrade Servo Micro firmware if needed:
 
-1. Enter the chroot.
-    * `$ cros_sdk`
-1. Run servo_updater.
-    * `$ sudo servo_updater --board=servo_micro`
+1.  Enter the chroot.
+    *   `$ cros_sdk`
+1.  Run servo_updater.
+    *   `$ sudo servo_updater --board=servo_micro`
 
-If that still results in too old of a firmware version, use `repo sync` and `update_chroot` to update your CrOS development environment, then try again.
+If that still results in too old of a firmware version, use `repo sync` and
+`update_chroot` to update your CrOS development environment, then try again.
 
-Reflashing with Servo Micro also requires the [i2c-pseudo kernel module](#i2c-pseudo).
+Reflashing with Servo Micro also requires the
+[i2c-pseudo kernel module](#i2c-pseudo).
 
 ### Installing i2c-pseudo {#i2c-pseudo}
 
-1. Install the `i2c-pseudo` Linux kernel module.  (Do this **outside** of the chroot!)
-    * `$ cd src/platform/ec/extra/i2c_pseudo`
-    * `$ ./install`
+1.  Install the `i2c-pseudo` Linux kernel module. (Do this **outside** of the
+    chroot!)
+    *   `$ cd src/platform/ec/extra/i2c_pseudo`
+    *   `$ ./install`
+
+**NOTE**: You will need to restart servod after installation.
 
-If the above fails, your system may be missing packages necessary for building kernel modules.  Consult your Linux distribution's documentation and support forums.  After installing any packages that might be missing, simply try the install script again.
+If the above fails, your system may be missing packages necessary for building
+kernel modules. Consult your Linux distribution's documentation and support
+forums. After installing any packages that might be missing, simply try the
+install script again.
 
-You will need to reinstall `i2c-pseudo` after each kernel upgrade.
+If DKMS is not available, you will need to reinstall `i2c-pseudo` after each
+kernel upgrade. Otherwise DKMS should automatically install the module in each
+new kernel, which you can verify with `dkms status`.
 
-There is an intention to [upstream i2c-pseudo](https://issuetracker.google.com/129565355), though even if accepted upstream, it may or may not become included with common Linux distribution kernels.
+There is an intention to
+[upstream i2c-pseudo](https://issuetracker.google.com/129565355), though even if
+accepted upstream, it may or may not become included with common Linux
+distribution kernels.
 
 ### Common reflash instructions
 
-These instructions apply when using any kind of Servo, including those with no special prerequisites (such as [Servo v2](https://www.chromium.org/chromium-os/servo/servo-v2) with its Yoshi flex cable connected to the DUT).
-
-1. Enter the chroot (for servod).
-    * `$ cros_sdk --no-ns-pid`
-1. Start servod.
-    * `$ sudo servod --board=<servod_board_name>`
-    * For some boards the servod board name is different than the EC codebase board name used below!
-1. Enter the chroot (for flash_ec).
-    * `$ cros_sdk`
-1. Build the EC image for your board.
-    * `$ cd ~/trunk/src/platform/ec`
-    * `$ board=<board_name>`
-    * `$ make -j BOARD="$board"`
-1. Run flash_ec from the util directory.
-    * `$ util/flash_ec --board="$board" --image=build/"$board"/ec.bin`
+These instructions apply when using any kind of Servo, including those with no
+special prerequisites (such as
+[Servo v2](https://www.chromium.org/chromium-os/servo/servo-v2) with its Yoshi
+flex cable connected to the DUT).
+
+1.  Enter the chroot (for servod).
+    *   `$ cros_sdk --no-ns-pid`
+1.  Start servod.
+    *   `$ sudo servod --board=<servod_board_name>`
+    *   For some boards the servod board name is different than the EC codebase
+        board name used below!
+1.  Enter the chroot (for flash_ec).
+    *   `$ cros_sdk`
+1.  Build the EC image for your board.
+    *   `$ cd ~/trunk/src/platform/ec`
+    *   `$ board=<board_name>`
+    *   `$ make -j BOARD="$board"`
+1.  Run flash_ec from the util directory.
+    *   `$ util/flash_ec --board="$board" --image=build/"$board"/ec.bin`
 
 ## CR50 CCD sans servod alternative {#ccd-sans-servod}
 
-This section applies whether using CR50 CCD via [Servo v4](https://www.chromium.org/chromium-os/servo/servov4) or [SuzyQ aka SuzyQable](https://www.sparkfun.com/products/14746).
-
-When using CR50 CCD, it is possible to reflash without servod, which _must not_ be running when using this method.
-
-1. Enter the chroot.
-    * `$ cros_sdk`
-1. Build the EC image for your board.
-    * `$ cd ~/trunk/src/platform/ec`
-    * `$ board=<board_name>`
-    * `$ make -j BOARD="$board"`
-1. Run iteflash from the build/\<board\>/util directory.
-    * `$ build/"$board"/util/iteflash --i2c-interface=ccd --i2c-mux --send-waveform=1 --erase --write=build/"$board"/ec.bin`
-
-WARNING: The `--i2c-mux` flag is only required for some ITE EC boards.  For boards without an I2C mux between CR50 and the EC, that flag _must not_ be specified.  (This is handled for you when using `flash_ec` + `servod` because the latter has knowledge of which boards are expected to have the I2C mux.)
+This section applies whether using CR50 CCD via
+[Servo v4](https://www.chromium.org/chromium-os/servo/servov4) or
+[SuzyQ aka SuzyQable](https://www.sparkfun.com/products/14746).
+
+When using CR50 CCD, it is possible to reflash without servod, which _must not_
+be running when using this method.
+
+1.  Enter the chroot.
+    *   `$ cros_sdk`
+1.  Build the EC image for your board.
+    *   `$ cd ~/trunk/src/platform/ec`
+    *   `$ board=<board_name>`
+    *   `$ make -j BOARD="$board"`
+1.  Run iteflash from the build/\<board\>/util directory.
+    *   `$ build/"$board"/util/iteflash --i2c-interface=ccd --i2c-mux
+        --send-waveform=1 --erase --write=build/"$board"/ec.bin`
+
+WARNING: The `--i2c-mux` flag is only required for some ITE EC boards. For
+boards without an I2C mux between CR50 and the EC, that flag _must not_ be
+specified. (This is handled for you when using `flash_ec` + `servod` because the
+latter has knowledge of which boards are expected to have the I2C mux.)
diff --git a/util/kconfig/.gitignore b/util/kconfig/.gitignore
deleted file mode 100644
index b5bf92f66d..0000000000
--- a/util/kconfig/.gitignore
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# Generated files
-#
-*.moc
-*conf-cfg
-
-#
-# configuration programs
-#
-conf
-mconf
-nconf
-qconf
-gconf
diff --git a/util/kconfig/Makefile b/util/kconfig/Makefile
deleted file mode 100644
index ef2f2336c4..0000000000
--- a/util/kconfig/Makefile
+++ /dev/null
@@ -1,210 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-# ===========================================================================
-# Kernel configuration targets
-# These targets are used from top-level makefile
-
-PHONY += xconfig gconfig menuconfig config localmodconfig localyesconfig \
-	build_menuconfig build_nconfig build_gconfig build_xconfig
-
-ifdef KBUILD_KCONFIG
-Kconfig := $(KBUILD_KCONFIG)
-else
-Kconfig := Kconfig
-endif
-
-ifndef KBUILD_DEFCONFIG
-KBUILD_DEFCONFIG := defconfig
-endif
-
-ifeq ($(quiet),silent_)
-silent := -s
-endif
-
-# We need this, in case the user has it in its environment
-unexport CONFIG_
-
-xconfig: $(obj)/qconf
-	$< $(silent) $(Kconfig)
-
-gconfig: $(obj)/gconf
-	$< $(silent) $(Kconfig)
-
-menuconfig: $(obj)/mconf
-	$< $(silent) $(Kconfig)
-
-config: $(obj)/conf
-	$< $(silent) --oldaskconfig $(Kconfig)
-
-nconfig: $(obj)/nconf
-	$< $(silent) $(Kconfig)
-
-build_menuconfig: $(obj)/mconf
-
-build_nconfig: $(obj)/nconf
-
-build_gconfig: $(obj)/gconf
-
-build_xconfig: $(obj)/qconf
-
-localyesconfig localmodconfig: $(obj)/conf
-	$(Q)perl $(srctree)/$(src)/streamline_config.pl --$@ $(srctree) $(Kconfig) > .tmp.config
-	$(Q)if [ -f .config ]; then 					\
-			cmp -s .tmp.config .config ||			\
-			(mv -f .config .config.old.1;			\
-			 mv -f .tmp.config .config;			\
-			 $< $(silent) --oldconfig $(Kconfig);		\
-			 mv -f .config.old.1 .config.old)		\
-	else								\
-			mv -f .tmp.config .config;			\
-			$< $(silent) --oldconfig $(Kconfig);		\
-	fi
-	$(Q)rm -f .tmp.config
-
-# These targets map 1:1 to the commandline options of 'conf'
-#
-# Note:
-#  syncconfig has become an internal implementation detail and is now
-#  deprecated for external use
-simple-targets := oldconfig allnoconfig allyesconfig allmodconfig \
-	alldefconfig randconfig listnewconfig olddefconfig syncconfig
-PHONY += $(simple-targets)
-
-$(simple-targets): $(obj)/conf
-	$< $(silent) --$@ $(Kconfig)
-
-PHONY += savedefconfig defconfig
-
-savedefconfig: $(obj)/conf
-	$< $(silent) --$@=defconfig $(Kconfig)
-
-defconfig: $(obj)/conf
-ifneq ($(wildcard $(srctree)/arch/$(SRCARCH)/configs/$(KBUILD_DEFCONFIG)),)
-	@$(kecho) "*** Default configuration is based on '$(KBUILD_DEFCONFIG)'"
-	$(Q)$< $(silent) --defconfig=arch/$(SRCARCH)/configs/$(KBUILD_DEFCONFIG) $(Kconfig)
-else
-	@$(kecho) "*** Default configuration is based on target '$(KBUILD_DEFCONFIG)'"
-	$(Q)$(MAKE) -f $(srctree)/Makefile $(KBUILD_DEFCONFIG)
-endif
-
-%_defconfig: $(obj)/conf
-	$(Q)$< $(silent) --defconfig=arch/$(SRCARCH)/configs/$@ $(Kconfig)
-
-configfiles=$(wildcard $(srctree)/kernel/configs/$@ $(srctree)/arch/$(SRCARCH)/configs/$@)
-
-%.config: $(obj)/conf
-	$(if $(call configfiles),, $(error No configuration exists for this target on this architecture))
-	$(Q)$(CONFIG_SHELL) $(srctree)/scripts/kconfig/merge_config.sh -m .config $(configfiles)
-	$(Q)$(MAKE) -f $(srctree)/Makefile olddefconfig
-
-PHONY += kvmconfig
-kvmconfig: kvm_guest.config
-	@:
-
-PHONY += xenconfig
-xenconfig: xen.config
-	@:
-
-PHONY += tinyconfig
-tinyconfig:
-	$(Q)$(MAKE) -f $(srctree)/Makefile allnoconfig tiny.config
-
-# CHECK: -o cache_dir=<path> working?
-PHONY += testconfig
-testconfig: $(obj)/conf
-	$(PYTHON3) -B -m pytest $(srctree)/$(src)/tests \
-	-o cache_dir=$(abspath $(obj)/tests/.cache) \
-	$(if $(findstring 1,$(KBUILD_VERBOSE)),--capture=no)
-clean-files += tests/.cache
-
-# Help text used by make help
-help:
-	@echo  '  config	  - Update current config utilising a line-oriented program'
-	@echo  '  nconfig         - Update current config utilising a ncurses menu based program'
-	@echo  '  menuconfig	  - Update current config utilising a menu based program'
-	@echo  '  xconfig	  - Update current config utilising a Qt based front-end'
-	@echo  '  gconfig	  - Update current config utilising a GTK+ based front-end'
-	@echo  '  oldconfig	  - Update current config utilising a provided .config as base'
-	@echo  '  localmodconfig  - Update current config disabling modules not loaded'
-	@echo  '  localyesconfig  - Update current config converting local mods to core'
-	@echo  '  defconfig	  - New config with default from ARCH supplied defconfig'
-	@echo  '  savedefconfig   - Save current config as ./defconfig (minimal config)'
-	@echo  '  allnoconfig	  - New config where all options are answered with no'
-	@echo  '  allyesconfig	  - New config where all options are accepted with yes'
-	@echo  '  allmodconfig	  - New config selecting modules when possible'
-	@echo  '  alldefconfig    - New config with all symbols set to default'
-	@echo  '  randconfig	  - New config with random answer to all options'
-	@echo  '  listnewconfig   - List new options'
-	@echo  '  olddefconfig	  - Same as oldconfig but sets new symbols to their'
-	@echo  '                    default value without prompting'
-	@echo  '  kvmconfig	  - Enable additional options for kvm guest kernel support'
-	@echo  '  xenconfig       - Enable additional options for xen dom0 and guest kernel support'
-	@echo  '  tinyconfig	  - Configure the tiniest possible kernel'
-	@echo  '  testconfig	  - Run Kconfig unit tests (requires python3 and pytest)'
-
-# ===========================================================================
-# object files used by all kconfig flavours
-common-objs	:= confdata.o expr.o lexer.lex.o parser.tab.o preprocess.o \
-		   symbol.o
-
-$(obj)/lexer.lex.o: $(obj)/parser.tab.h
-HOSTCFLAGS_lexer.lex.o	:= -I $(srctree)/$(src)
-HOSTCFLAGS_parser.tab.o	:= -I $(srctree)/$(src)
-
-# conf: Used for defconfig, oldconfig and related targets
-hostprogs-y	+= conf
-conf-objs	:= conf.o $(common-objs)
-
-# nconf: Used for the nconfig target based on ncurses
-hostprogs-y	+= nconf
-nconf-objs	:= nconf.o nconf.gui.o $(common-objs)
-
-HOSTLDLIBS_nconf	= $(shell . $(obj)/nconf-cfg && echo $$libs)
-HOSTCFLAGS_nconf.o	= $(shell . $(obj)/nconf-cfg && echo $$cflags)
-HOSTCFLAGS_nconf.gui.o	= $(shell . $(obj)/nconf-cfg && echo $$cflags)
-
-$(obj)/nconf.o $(obj)/nconf.gui.o: $(obj)/nconf-cfg
-
-# mconf: Used for the menuconfig target based on lxdialog
-hostprogs-y	+= mconf
-lxdialog	:= $(addprefix lxdialog/, \
-		     checklist.o inputbox.o menubox.o textbox.o util.o yesno.o)
-mconf-objs	:= mconf.o $(lxdialog) $(common-objs)
-
-HOSTLDLIBS_mconf = $(shell . $(obj)/mconf-cfg && echo $$libs)
-$(foreach f, mconf.o $(lxdialog), \
-  $(eval HOSTCFLAGS_$f = $$(shell . $(obj)/mconf-cfg && echo $$$$cflags)))
-
-$(addprefix $(obj)/, mconf.o $(lxdialog)): $(obj)/mconf-cfg
-
-# qconf: Used for the xconfig target based on Qt
-hostprogs-y	+= qconf
-qconf-cxxobjs	:= qconf.o
-qconf-objs	:= images.o $(common-objs)
-
-HOSTLDLIBS_qconf	= $(shell . $(obj)/qconf-cfg && echo $$libs)
-HOSTCXXFLAGS_qconf.o	= $(shell . $(obj)/qconf-cfg && echo $$cflags)
-
-$(obj)/qconf.o: $(obj)/qconf-cfg $(obj)/qconf.moc
-
-quiet_cmd_moc = MOC     $@
-      cmd_moc = $(shell . $(obj)/qconf-cfg && echo $$moc) -i $< -o $@
-
-$(obj)/%.moc: $(src)/%.h $(obj)/qconf-cfg
-	$(call cmd,moc)
-
-# gconf: Used for the gconfig target based on GTK+
-hostprogs-y	+= gconf
-gconf-objs	:= gconf.o images.o $(common-objs)
-
-HOSTLDLIBS_gconf    = $(shell . $(obj)/gconf-cfg && echo $$libs)
-HOSTCFLAGS_gconf.o  = $(shell . $(obj)/gconf-cfg && echo $$cflags)
-
-$(obj)/gconf.o: $(obj)/gconf-cfg
-
-# check if necessary packages are available, and configure build flags
-filechk_conf_cfg = $(CONFIG_SHELL) $<
-
-$(obj)/%conf-cfg: $(src)/%conf-cfg.sh FORCE
-	$(call filechk,conf_cfg)
-
-clean-files += *conf-cfg
diff --git a/util/kconfig/conf.c b/util/kconfig/conf.c
deleted file mode 100644
index 40e16e871a..0000000000
--- a/util/kconfig/conf.c
+++ /dev/null
@@ -1,700 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org>
- */
-
-#include <ctype.h>
-#include <limits.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <time.h>
-#include <unistd.h>
-#include <getopt.h>
-#include <sys/stat.h>
-#include <sys/time.h>
-#include <errno.h>
-
-#include "lkc.h"
-
-static void conf(struct menu *menu);
-static void check_conf(struct menu *menu);
-
-enum input_mode {
-	oldaskconfig,
-	syncconfig,
-	oldconfig,
-	allnoconfig,
-	allyesconfig,
-	allmodconfig,
-	alldefconfig,
-	randconfig,
-	defconfig,
-	savedefconfig,
-	listnewconfig,
-	olddefconfig,
-};
-static enum input_mode input_mode = oldaskconfig;
-
-static int indent = 1;
-static int tty_stdio;
-static int sync_kconfig;
-static int conf_cnt;
-static char line[PATH_MAX];
-static struct menu *rootEntry;
-
-static void print_help(struct menu *menu)
-{
-	struct gstr help = str_new();
-
-	menu_get_ext_help(menu, &help);
-
-	printf("\n%s\n", str_get(&help));
-	str_free(&help);
-}
-
-static void strip(char *str)
-{
-	char *p = str;
-	int l;
-
-	while ((isspace(*p)))
-		p++;
-	l = strlen(p);
-	if (p != str)
-		memmove(str, p, l + 1);
-	if (!l)
-		return;
-	p = str + l - 1;
-	while ((isspace(*p)))
-		*p-- = 0;
-}
-
-/* Helper function to facilitate fgets() by Jean Sacren. */
-static void xfgets(char *str, int size, FILE *in)
-{
-	if (!fgets(str, size, in))
-		fprintf(stderr, "\nError in reading or end of file.\n");
-
-	if (!tty_stdio)
-		printf("%s", str);
-}
-
-static int conf_askvalue(struct symbol *sym, const char *def)
-{
-	enum symbol_type type = sym_get_type(sym);
-
-	if (!sym_has_value(sym))
-		printf("(NEW) ");
-
-	line[0] = '\n';
-	line[1] = 0;
-
-	if (!sym_is_changeable(sym)) {
-		printf("%s\n", def);
-		line[0] = '\n';
-		line[1] = 0;
-		return 0;
-	}
-
-	switch (input_mode) {
-	case oldconfig:
-	case syncconfig:
-		if (sym_has_value(sym)) {
-			printf("%s\n", def);
-			return 0;
-		}
-		/* fall through */
-	case oldaskconfig:
-		fflush(stdout);
-		xfgets(line, sizeof(line), stdin);
-		return 1;
-	default:
-		break;
-	}
-
-	switch (type) {
-	case S_INT:
-	case S_HEX:
-	case S_STRING:
-		printf("%s\n", def);
-		return 1;
-	default:
-		;
-	}
-	printf("%s", line);
-	return 1;
-}
-
-static int conf_string(struct menu *menu)
-{
-	struct symbol *sym = menu->sym;
-	const char *def;
-
-	while (1) {
-		printf("%*s%s ", indent - 1, "", menu->prompt->text);
-		printf("(%s) ", sym->name);
-		def = sym_get_string_value(sym);
-		if (sym_get_string_value(sym))
-			printf("[%s] ", def);
-		if (!conf_askvalue(sym, def))
-			return 0;
-		switch (line[0]) {
-		case '\n':
-			break;
-		case '?':
-			/* print help */
-			if (line[1] == '\n') {
-				print_help(menu);
-				def = NULL;
-				break;
-			}
-			/* fall through */
-		default:
-			line[strlen(line)-1] = 0;
-			def = line;
-		}
-		if (def && sym_set_string_value(sym, def))
-			return 0;
-	}
-}
-
-static int conf_sym(struct menu *menu)
-{
-	struct symbol *sym = menu->sym;
-	tristate oldval, newval;
-
-	while (1) {
-		printf("%*s%s ", indent - 1, "", menu->prompt->text);
-		if (sym->name)
-			printf("(%s) ", sym->name);
-		putchar('[');
-		oldval = sym_get_tristate_value(sym);
-		switch (oldval) {
-		case no:
-			putchar('N');
-			break;
-		case mod:
-			putchar('M');
-			break;
-		case yes:
-			putchar('Y');
-			break;
-		}
-		if (oldval != no && sym_tristate_within_range(sym, no))
-			printf("/n");
-		if (oldval != mod && sym_tristate_within_range(sym, mod))
-			printf("/m");
-		if (oldval != yes && sym_tristate_within_range(sym, yes))
-			printf("/y");
-		printf("/?] ");
-		if (!conf_askvalue(sym, sym_get_string_value(sym)))
-			return 0;
-		strip(line);
-
-		switch (line[0]) {
-		case 'n':
-		case 'N':
-			newval = no;
-			if (!line[1] || !strcmp(&line[1], "o"))
-				break;
-			continue;
-		case 'm':
-		case 'M':
-			newval = mod;
-			if (!line[1])
-				break;
-			continue;
-		case 'y':
-		case 'Y':
-			newval = yes;
-			if (!line[1] || !strcmp(&line[1], "es"))
-				break;
-			continue;
-		case 0:
-			newval = oldval;
-			break;
-		case '?':
-			goto help;
-		default:
-			continue;
-		}
-		if (sym_set_tristate_value(sym, newval))
-			return 0;
-help:
-		print_help(menu);
-	}
-}
-
-static int conf_choice(struct menu *menu)
-{
-	struct symbol *sym, *def_sym;
-	struct menu *child;
-	bool is_new;
-
-	sym = menu->sym;
-	is_new = !sym_has_value(sym);
-	if (sym_is_changeable(sym)) {
-		conf_sym(menu);
-		sym_calc_value(sym);
-		switch (sym_get_tristate_value(sym)) {
-		case no:
-			return 1;
-		case mod:
-			return 0;
-		case yes:
-			break;
-		}
-	} else {
-		switch (sym_get_tristate_value(sym)) {
-		case no:
-			return 1;
-		case mod:
-			printf("%*s%s\n", indent - 1, "", menu_get_prompt(menu));
-			return 0;
-		case yes:
-			break;
-		}
-	}
-
-	while (1) {
-		int cnt, def;
-
-		printf("%*s%s\n", indent - 1, "", menu_get_prompt(menu));
-		def_sym = sym_get_choice_value(sym);
-		cnt = def = 0;
-		line[0] = 0;
-		for (child = menu->list; child; child = child->next) {
-			if (!menu_is_visible(child))
-				continue;
-			if (!child->sym) {
-				printf("%*c %s\n", indent, '*', menu_get_prompt(child));
-				continue;
-			}
-			cnt++;
-			if (child->sym == def_sym) {
-				def = cnt;
-				printf("%*c", indent, '>');
-			} else
-				printf("%*c", indent, ' ');
-			printf(" %d. %s", cnt, menu_get_prompt(child));
-			if (child->sym->name)
-				printf(" (%s)", child->sym->name);
-			if (!sym_has_value(child->sym))
-				printf(" (NEW)");
-			printf("\n");
-		}
-		printf("%*schoice", indent - 1, "");
-		if (cnt == 1) {
-			printf("[1]: 1\n");
-			goto conf_childs;
-		}
-		printf("[1-%d?]: ", cnt);
-		switch (input_mode) {
-		case oldconfig:
-		case syncconfig:
-			if (!is_new) {
-				cnt = def;
-				printf("%d\n", cnt);
-				break;
-			}
-			/* fall through */
-		case oldaskconfig:
-			fflush(stdout);
-			xfgets(line, sizeof(line), stdin);
-			strip(line);
-			if (line[0] == '?') {
-				print_help(menu);
-				continue;
-			}
-			if (!line[0])
-				cnt = def;
-			else if (isdigit(line[0]))
-				cnt = atoi(line);
-			else
-				continue;
-			break;
-		default:
-			break;
-		}
-
-	conf_childs:
-		for (child = menu->list; child; child = child->next) {
-			if (!child->sym || !menu_is_visible(child))
-				continue;
-			if (!--cnt)
-				break;
-		}
-		if (!child)
-			continue;
-		if (line[0] && line[strlen(line) - 1] == '?') {
-			print_help(child);
-			continue;
-		}
-		sym_set_choice_value(sym, child->sym);
-		for (child = child->list; child; child = child->next) {
-			indent += 2;
-			conf(child);
-			indent -= 2;
-		}
-		return 1;
-	}
-}
-
-static void conf(struct menu *menu)
-{
-	struct symbol *sym;
-	struct property *prop;
-	struct menu *child;
-
-	if (!menu_is_visible(menu))
-		return;
-
-	sym = menu->sym;
-	prop = menu->prompt;
-	if (prop) {
-		const char *prompt;
-
-		switch (prop->type) {
-		case P_MENU:
-			/*
-			 * Except in oldaskconfig mode, we show only menus that
-			 * contain new symbols.
-			 */
-			if (input_mode != oldaskconfig && rootEntry != menu) {
-				check_conf(menu);
-				return;
-			}
-			/* fall through */
-		case P_COMMENT:
-			prompt = menu_get_prompt(menu);
-			if (prompt)
-				printf("%*c\n%*c %s\n%*c\n",
-					indent, '*',
-					indent, '*', prompt,
-					indent, '*');
-		default:
-			;
-		}
-	}
-
-	if (!sym)
-		goto conf_childs;
-
-	if (sym_is_choice(sym)) {
-		conf_choice(menu);
-		if (sym->curr.tri != mod)
-			return;
-		goto conf_childs;
-	}
-
-	switch (sym->type) {
-	case S_INT:
-	case S_HEX:
-	case S_STRING:
-		conf_string(menu);
-		break;
-	default:
-		conf_sym(menu);
-		break;
-	}
-
-conf_childs:
-	if (sym)
-		indent += 2;
-	for (child = menu->list; child; child = child->next)
-		conf(child);
-	if (sym)
-		indent -= 2;
-}
-
-static void check_conf(struct menu *menu)
-{
-	struct symbol *sym;
-	struct menu *child;
-
-	if (!menu_is_visible(menu))
-		return;
-
-	sym = menu->sym;
-	if (sym && !sym_has_value(sym)) {
-		if (sym_is_changeable(sym) ||
-		    (sym_is_choice(sym) && sym_get_tristate_value(sym) == yes)) {
-			if (input_mode == listnewconfig) {
-				if (sym->name) {
-					const char *str;
-
-					if (sym->type == S_STRING) {
-						str = sym_get_string_value(sym);
-						str = sym_escape_string_value(str);
-						printf("%s%s=%s\n", CONFIG_, sym->name, str);
-						free((void *)str);
-					} else {
-						str = sym_get_string_value(sym);
-						printf("%s%s=%s\n", CONFIG_, sym->name, str);
-					}
-				}
-			} else {
-				if (!conf_cnt++)
-					printf("*\n* Restart config...\n*\n");
-				rootEntry = menu_get_parent_menu(menu);
-				conf(rootEntry);
-			}
-		}
-	}
-
-	for (child = menu->list; child; child = child->next)
-		check_conf(child);
-}
-
-static struct option long_opts[] = {
-	{"oldaskconfig",    no_argument,       NULL, oldaskconfig},
-	{"oldconfig",       no_argument,       NULL, oldconfig},
-	{"syncconfig",      no_argument,       NULL, syncconfig},
-	{"defconfig",       required_argument, NULL, defconfig},
-	{"savedefconfig",   required_argument, NULL, savedefconfig},
-	{"allnoconfig",     no_argument,       NULL, allnoconfig},
-	{"allyesconfig",    no_argument,       NULL, allyesconfig},
-	{"allmodconfig",    no_argument,       NULL, allmodconfig},
-	{"alldefconfig",    no_argument,       NULL, alldefconfig},
-	{"randconfig",      no_argument,       NULL, randconfig},
-	{"listnewconfig",   no_argument,       NULL, listnewconfig},
-	{"olddefconfig",    no_argument,       NULL, olddefconfig},
-	{NULL, 0, NULL, 0}
-};
-
-static void conf_usage(const char *progname)
-{
-
-	printf("Usage: %s [-s] [option] <kconfig-file>\n", progname);
-	printf("[option] is _one_ of the following:\n");
-	printf("  --listnewconfig         List new options\n");
-	printf("  --oldaskconfig          Start a new configuration using a line-oriented program\n");
-	printf("  --oldconfig             Update a configuration using a provided .config as base\n");
-	printf("  --syncconfig            Similar to oldconfig but generates configuration in\n"
-	       "                          include/{generated/,config/}\n");
-	printf("  --olddefconfig          Same as oldconfig but sets new symbols to their default value\n");
-	printf("  --defconfig <file>      New config with default defined in <file>\n");
-	printf("  --savedefconfig <file>  Save the minimal current configuration to <file>\n");
-	printf("  --allnoconfig           New config where all options are answered with no\n");
-	printf("  --allyesconfig          New config where all options are answered with yes\n");
-	printf("  --allmodconfig          New config where all options are answered with mod\n");
-	printf("  --alldefconfig          New config with all symbols set to default\n");
-	printf("  --randconfig            New config with random answer to all options\n");
-}
-
-int main(int ac, char **av)
-{
-	const char *progname = av[0];
-	int opt;
-	const char *name, *defconfig_file = NULL /* gcc uninit */;
-	int no_conf_write = 0;
-
-	tty_stdio = isatty(0) && isatty(1);
-
-	while ((opt = getopt_long(ac, av, "s", long_opts, NULL)) != -1) {
-		if (opt == 's') {
-			conf_set_message_callback(NULL);
-			continue;
-		}
-		input_mode = (enum input_mode)opt;
-		switch (opt) {
-		case syncconfig:
-			/*
-			 * syncconfig is invoked during the build stage.
-			 * Suppress distracting "configuration written to ..."
-			 */
-			conf_set_message_callback(NULL);
-			sync_kconfig = 1;
-			break;
-		case defconfig:
-		case savedefconfig:
-			defconfig_file = optarg;
-			break;
-		case randconfig:
-		{
-			struct timeval now;
-			unsigned int seed;
-			char *seed_env;
-
-			/*
-			 * Use microseconds derived seed,
-			 * compensate for systems where it may be zero
-			 */
-			gettimeofday(&now, NULL);
-			seed = (unsigned int)((now.tv_sec + 1) * (now.tv_usec + 1));
-
-			seed_env = getenv("KCONFIG_SEED");
-			if( seed_env && *seed_env ) {
-				char *endp;
-				int tmp = (int)strtol(seed_env, &endp, 0);
-				if (*endp == '\0') {
-					seed = tmp;
-				}
-			}
-			fprintf( stderr, "KCONFIG_SEED=0x%X\n", seed );
-			srand(seed);
-			break;
-		}
-		case oldaskconfig:
-		case oldconfig:
-		case allnoconfig:
-		case allyesconfig:
-		case allmodconfig:
-		case alldefconfig:
-		case listnewconfig:
-		case olddefconfig:
-			break;
-		case '?':
-			conf_usage(progname);
-			exit(1);
-			break;
-		}
-	}
-	if (ac == optind) {
-		fprintf(stderr, "%s: Kconfig file missing\n", av[0]);
-		conf_usage(progname);
-		exit(1);
-	}
-	name = av[optind];
-	conf_parse(name);
-	//zconfdump(stdout);
-
-	switch (input_mode) {
-	case defconfig:
-		if (conf_read(defconfig_file)) {
-			fprintf(stderr,
-				"***\n"
-				  "*** Can't find default configuration \"%s\"!\n"
-				  "***\n",
-				defconfig_file);
-			exit(1);
-		}
-		break;
-	case savedefconfig:
-	case syncconfig:
-	case oldaskconfig:
-	case oldconfig:
-	case listnewconfig:
-	case olddefconfig:
-		conf_read(NULL);
-		break;
-	case allnoconfig:
-	case allyesconfig:
-	case allmodconfig:
-	case alldefconfig:
-	case randconfig:
-		name = getenv("KCONFIG_ALLCONFIG");
-		if (!name)
-			break;
-		if ((strcmp(name, "") != 0) && (strcmp(name, "1") != 0)) {
-			if (conf_read_simple(name, S_DEF_USER)) {
-				fprintf(stderr,
-					"*** Can't read seed configuration \"%s\"!\n",
-					name);
-				exit(1);
-			}
-			break;
-		}
-		switch (input_mode) {
-		case allnoconfig:	name = "allno.config"; break;
-		case allyesconfig:	name = "allyes.config"; break;
-		case allmodconfig:	name = "allmod.config"; break;
-		case alldefconfig:	name = "alldef.config"; break;
-		case randconfig:	name = "allrandom.config"; break;
-		default: break;
-		}
-		if (conf_read_simple(name, S_DEF_USER) &&
-		    conf_read_simple("all.config", S_DEF_USER)) {
-			fprintf(stderr,
-				"*** KCONFIG_ALLCONFIG set, but no \"%s\" or \"all.config\" file found\n",
-				name);
-			exit(1);
-		}
-		break;
-	default:
-		break;
-	}
-
-	if (sync_kconfig) {
-		name = getenv("KCONFIG_NOSILENTUPDATE");
-		if (name && *name) {
-			if (conf_get_changed()) {
-				fprintf(stderr,
-					"\n*** The configuration requires explicit update.\n\n");
-				return 1;
-			}
-			no_conf_write = 1;
-		}
-	}
-
-	switch (input_mode) {
-	case allnoconfig:
-		conf_set_all_new_symbols(def_no);
-		break;
-	case allyesconfig:
-		conf_set_all_new_symbols(def_yes);
-		break;
-	case allmodconfig:
-		conf_set_all_new_symbols(def_mod);
-		break;
-	case alldefconfig:
-		conf_set_all_new_symbols(def_default);
-		break;
-	case randconfig:
-		/* Really nothing to do in this loop */
-		while (conf_set_all_new_symbols(def_random)) ;
-		break;
-	case defconfig:
-		conf_set_all_new_symbols(def_default);
-		break;
-	case savedefconfig:
-		break;
-	case oldaskconfig:
-		rootEntry = &rootmenu;
-		conf(&rootmenu);
-		input_mode = oldconfig;
-		/* fall through */
-	case oldconfig:
-	case listnewconfig:
-	case syncconfig:
-		/* Update until a loop caused no more changes */
-		do {
-			conf_cnt = 0;
-			check_conf(&rootmenu);
-		} while (conf_cnt);
-		break;
-	case olddefconfig:
-	default:
-		break;
-	}
-
-	if (input_mode == savedefconfig) {
-		if (conf_write_defconfig(defconfig_file)) {
-			fprintf(stderr, "n*** Error while saving defconfig to: %s\n\n",
-				defconfig_file);
-			return 1;
-		}
-	} else if (input_mode != listnewconfig) {
-		if (!no_conf_write && conf_write(NULL)) {
-			fprintf(stderr, "\n*** Error during writing of the configuration.\n\n");
-			exit(1);
-		}
-
-		/*
-		 * Create auto.conf if it does not exist.
-		 * This prevents GNU Make 4.1 or older from emitting
-		 * "include/config/auto.conf: No such file or directory"
-		 * in the top-level Makefile
-		 *
-		 * syncconfig always creates or updates auto.conf because it is
-		 * used during the build.
-		 */
-		if (conf_write_autoconf(sync_kconfig) && sync_kconfig) {
-			fprintf(stderr,
-				"\n*** Error during sync of the configuration.\n\n");
-			return 1;
-		}
-	}
-	return 0;
-}
diff --git a/util/kconfig/confdata.c b/util/kconfig/confdata.c
deleted file mode 100644
index 3569d2dec3..0000000000
--- a/util/kconfig/confdata.c
+++ /dev/null
@@ -1,1364 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org>
- */
-
-#include <sys/mman.h>
-#include <sys/stat.h>
-#include <ctype.h>
-#include <errno.h>
-#include <fcntl.h>
-#include <limits.h>
-#include <stdarg.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <time.h>
-#include <unistd.h>
-
-#include "lkc.h"
-
-/* return true if 'path' exists, false otherwise */
-static bool is_present(const char *path)
-{
-	struct stat st;
-
-	return !stat(path, &st);
-}
-
-/* return true if 'path' exists and it is a directory, false otherwise */
-static bool is_dir(const char *path)
-{
-	struct stat st;
-
-	if (stat(path, &st))
-		return 0;
-
-	return S_ISDIR(st.st_mode);
-}
-
-/* return true if the given two files are the same, false otherwise */
-static bool is_same(const char *file1, const char *file2)
-{
-	int fd1, fd2;
-	struct stat st1, st2;
-	void *map1, *map2;
-	bool ret = false;
-
-	fd1 = open(file1, O_RDONLY);
-	if (fd1 < 0)
-		return ret;
-
-	fd2 = open(file2, O_RDONLY);
-	if (fd2 < 0)
-		goto close1;
-
-	ret = fstat(fd1, &st1);
-	if (ret)
-		goto close2;
-	ret = fstat(fd2, &st2);
-	if (ret)
-		goto close2;
-
-	if (st1.st_size != st2.st_size)
-		goto close2;
-
-	map1 = mmap(NULL, st1.st_size, PROT_READ, MAP_PRIVATE, fd1, 0);
-	if (map1 == MAP_FAILED)
-		goto close2;
-
-	map2 = mmap(NULL, st2.st_size, PROT_READ, MAP_PRIVATE, fd2, 0);
-	if (map2 == MAP_FAILED)
-		goto close2;
-
-	if (bcmp(map1, map2, st1.st_size))
-		goto close2;
-
-	ret = true;
-close2:
-	close(fd2);
-close1:
-	close(fd1);
-
-	return ret;
-}
-
-/*
- * Create the parent directory of the given path.
- *
- * For example, if 'include/config/auto.conf' is given, create 'include/config'.
- */
-static int make_parent_dir(const char *path)
-{
-	char tmp[PATH_MAX + 1];
-	char *p;
-
-	strncpy(tmp, path, sizeof(tmp));
-	tmp[sizeof(tmp) - 1] = 0;
-
-	/* Remove the base name. Just return if nothing is left */
-	p = strrchr(tmp, '/');
-	if (!p)
-		return 0;
-	*(p + 1) = 0;
-
-	/* Just in case it is an absolute path */
-	p = tmp;
-	while (*p == '/')
-		p++;
-
-	while ((p = strchr(p, '/'))) {
-		*p = 0;
-
-		/* skip if the directory exists */
-		if (!is_dir(tmp) && mkdir(tmp, 0755))
-			return -1;
-
-		*p = '/';
-		while (*p == '/')
-			p++;
-	}
-
-	return 0;
-}
-
-static char depfile_path[PATH_MAX];
-static size_t depfile_prefix_len;
-
-/* touch depfile for symbol 'name' */
-static int conf_touch_dep(const char *name)
-{
-	int fd, ret;
-	const char *s;
-	char *d, c;
-
-	/* check overflow: prefix + name + ".h" + '\0' must fit in buffer. */
-	if (depfile_prefix_len + strlen(name) + 3 > sizeof(depfile_path))
-		return -1;
-
-	d = depfile_path + depfile_prefix_len;
-	s = name;
-
-	while ((c = *s++))
-		*d++ = (c == '_') ? '/' : tolower(c);
-	strcpy(d, ".h");
-
-	/* Assume directory path already exists. */
-	fd = open(depfile_path, O_WRONLY | O_CREAT | O_TRUNC, 0644);
-	if (fd == -1) {
-		if (errno != ENOENT)
-			return -1;
-
-		ret = make_parent_dir(depfile_path);
-		if (ret)
-			return ret;
-
-		/* Try it again. */
-		fd = open(depfile_path, O_WRONLY | O_CREAT | O_TRUNC, 0644);
-		if (fd == -1)
-			return -1;
-	}
-	close(fd);
-
-	return 0;
-}
-
-struct conf_printer {
-	void (*print_symbol)(FILE *, struct symbol *, const char *, void *);
-	void (*print_comment)(FILE *, const char *, void *);
-};
-
-static void conf_warning(const char *fmt, ...)
-	__attribute__ ((format (printf, 1, 2)));
-
-static void conf_message(const char *fmt, ...)
-	__attribute__ ((format (printf, 1, 2)));
-
-static const char *conf_filename;
-static int conf_lineno, conf_warnings;
-
-static void conf_warning(const char *fmt, ...)
-{
-	va_list ap;
-	va_start(ap, fmt);
-	fprintf(stderr, "%s:%d:warning: ", conf_filename, conf_lineno);
-	vfprintf(stderr, fmt, ap);
-	fprintf(stderr, "\n");
-	va_end(ap);
-	conf_warnings++;
-}
-
-static void conf_default_message_callback(const char *s)
-{
-	printf("#\n# ");
-	printf("%s", s);
-	printf("\n#\n");
-}
-
-static void (*conf_message_callback)(const char *s) =
-	conf_default_message_callback;
-void conf_set_message_callback(void (*fn)(const char *s))
-{
-	conf_message_callback = fn;
-}
-
-static void conf_message(const char *fmt, ...)
-{
-	va_list ap;
-	char buf[4096];
-
-	if (!conf_message_callback)
-		return;
-
-	va_start(ap, fmt);
-
-	vsnprintf(buf, sizeof(buf), fmt, ap);
-	conf_message_callback(buf);
-	va_end(ap);
-}
-
-const char *conf_get_configname(void)
-{
-	char *name = getenv("KCONFIG_CONFIG");
-
-	return name ? name : ".config";
-}
-
-static const char *conf_get_autoconfig_name(void)
-{
-	char *name = getenv("KCONFIG_AUTOCONFIG");
-
-	return name ? name : "include/config/auto.conf";
-}
-
-static int conf_set_sym_val(struct symbol *sym, int def, int def_flags, char *p)
-{
-	char *p2;
-
-	switch (sym->type) {
-	case S_TRISTATE:
-		if (p[0] == 'm') {
-			sym->def[def].tri = mod;
-			sym->flags |= def_flags;
-			break;
-		}
-		/* fall through */
-	case S_BOOLEAN:
-		if (p[0] == 'y') {
-			sym->def[def].tri = yes;
-			sym->flags |= def_flags;
-			break;
-		}
-		if (p[0] == 'n') {
-			sym->def[def].tri = no;
-			sym->flags |= def_flags;
-			break;
-		}
-		if (def != S_DEF_AUTO)
-			conf_warning("symbol value '%s' invalid for %s",
-				     p, sym->name);
-		return 1;
-	case S_STRING:
-		if (*p++ != '"')
-			break;
-		for (p2 = p; (p2 = strpbrk(p2, "\"\\")); p2++) {
-			if (*p2 == '"') {
-				*p2 = 0;
-				break;
-			}
-			memmove(p2, p2 + 1, strlen(p2));
-		}
-		if (!p2) {
-			if (def != S_DEF_AUTO)
-				conf_warning("invalid string found");
-			return 1;
-		}
-		/* fall through */
-	case S_INT:
-	case S_HEX:
-		if (sym_string_valid(sym, p)) {
-			sym->def[def].val = xstrdup(p);
-			sym->flags |= def_flags;
-		} else {
-			if (def != S_DEF_AUTO)
-				conf_warning("symbol value '%s' invalid for %s",
-					     p, sym->name);
-			return 1;
-		}
-		break;
-	default:
-		;
-	}
-	return 0;
-}
-
-#define LINE_GROWTH 16
-static int add_byte(int c, char **lineptr, size_t slen, size_t *n)
-{
-	char *nline;
-	size_t new_size = slen + 1;
-	if (new_size > *n) {
-		new_size += LINE_GROWTH - 1;
-		new_size *= 2;
-		nline = xrealloc(*lineptr, new_size);
-		if (!nline)
-			return -1;
-
-		*lineptr = nline;
-		*n = new_size;
-	}
-
-	(*lineptr)[slen] = c;
-
-	return 0;
-}
-
-static ssize_t compat_getline(char **lineptr, size_t *n, FILE *stream)
-{
-	char *line = *lineptr;
-	size_t slen = 0;
-
-	for (;;) {
-		int c = getc(stream);
-
-		switch (c) {
-		case '\n':
-			if (add_byte(c, &line, slen, n) < 0)
-				goto e_out;
-			slen++;
-			/* fall through */
-		case EOF:
-			if (add_byte('\0', &line, slen, n) < 0)
-				goto e_out;
-			*lineptr = line;
-			if (slen == 0)
-				return -1;
-			return slen;
-		default:
-			if (add_byte(c, &line, slen, n) < 0)
-				goto e_out;
-			slen++;
-		}
-	}
-
-e_out:
-	line[slen-1] = '\0';
-	*lineptr = line;
-	return -1;
-}
-
-int conf_read_simple(const char *name, int def)
-{
-	FILE *in = NULL;
-	char   *line = NULL;
-	size_t  line_asize = 0;
-	char *p, *p2;
-	struct symbol *sym;
-	int i, def_flags;
-
-	if (name) {
-		in = zconf_fopen(name);
-	} else {
-		struct property *prop;
-
-		name = conf_get_configname();
-		in = zconf_fopen(name);
-		if (in)
-			goto load;
-		sym_add_change_count(1);
-		if (!sym_defconfig_list)
-			return 1;
-
-		for_all_defaults(sym_defconfig_list, prop) {
-			if (expr_calc_value(prop->visible.expr) == no ||
-			    prop->expr->type != E_SYMBOL)
-				continue;
-			sym_calc_value(prop->expr->left.sym);
-			name = sym_get_string_value(prop->expr->left.sym);
-			in = zconf_fopen(name);
-			if (in) {
-				conf_message("using defaults found in %s",
-					 name);
-				goto load;
-			}
-		}
-	}
-	if (!in)
-		return 1;
-
-load:
-	conf_filename = name;
-	conf_lineno = 0;
-	conf_warnings = 0;
-
-	def_flags = SYMBOL_DEF << def;
-	for_all_symbols(i, sym) {
-		sym->flags |= SYMBOL_CHANGED;
-		sym->flags &= ~(def_flags|SYMBOL_VALID);
-		if (sym_is_choice(sym))
-			sym->flags |= def_flags;
-		switch (sym->type) {
-		case S_INT:
-		case S_HEX:
-		case S_STRING:
-			if (sym->def[def].val)
-				free(sym->def[def].val);
-			/* fall through */
-		default:
-			sym->def[def].val = NULL;
-			sym->def[def].tri = no;
-		}
-	}
-
-	while (compat_getline(&line, &line_asize, in) != -1) {
-		conf_lineno++;
-		sym = NULL;
-		if (line[0] == '#') {
-			if (memcmp(line + 2, CONFIG_, strlen(CONFIG_)))
-				continue;
-			p = strchr(line + 2 + strlen(CONFIG_), ' ');
-			if (!p)
-				continue;
-			*p++ = 0;
-			if (strncmp(p, "is not set", 10))
-				continue;
-			if (def == S_DEF_USER) {
-				sym = sym_find(line + 2 + strlen(CONFIG_));
-				if (!sym) {
-					sym_add_change_count(1);
-					continue;
-				}
-			} else {
-				sym = sym_lookup(line + 2 + strlen(CONFIG_), 0);
-				if (sym->type == S_UNKNOWN)
-					sym->type = S_BOOLEAN;
-			}
-			if (sym->flags & def_flags) {
-				conf_warning("override: reassigning to symbol %s", sym->name);
-			}
-			switch (sym->type) {
-			case S_BOOLEAN:
-			case S_TRISTATE:
-				sym->def[def].tri = no;
-				sym->flags |= def_flags;
-				break;
-			default:
-				;
-			}
-		} else if (memcmp(line, CONFIG_, strlen(CONFIG_)) == 0) {
-			p = strchr(line + strlen(CONFIG_), '=');
-			if (!p)
-				continue;
-			*p++ = 0;
-			p2 = strchr(p, '\n');
-			if (p2) {
-				*p2-- = 0;
-				if (*p2 == '\r')
-					*p2 = 0;
-			}
-
-			sym = sym_find(line + strlen(CONFIG_));
-			if (!sym) {
-				if (def == S_DEF_AUTO)
-					/*
-					 * Reading from include/config/auto.conf
-					 * If CONFIG_FOO previously existed in
-					 * auto.conf but it is missing now,
-					 * include/config/foo.h must be touched.
-					 */
-					conf_touch_dep(line + strlen(CONFIG_));
-				else
-					sym_add_change_count(1);
-				continue;
-			}
-
-			if (sym->flags & def_flags) {
-				conf_warning("override: reassigning to symbol %s", sym->name);
-			}
-			if (conf_set_sym_val(sym, def, def_flags, p))
-				continue;
-		} else {
-			if (line[0] != '\r' && line[0] != '\n')
-				conf_warning("unexpected data: %.*s",
-					     (int)strcspn(line, "\r\n"), line);
-
-			continue;
-		}
-
-		if (sym && sym_is_choice_value(sym)) {
-			struct symbol *cs = prop_get_symbol(sym_get_choice_prop(sym));
-			switch (sym->def[def].tri) {
-			case no:
-				break;
-			case mod:
-				if (cs->def[def].tri == yes) {
-					conf_warning("%s creates inconsistent choice state", sym->name);
-					cs->flags &= ~def_flags;
-				}
-				break;
-			case yes:
-				if (cs->def[def].tri != no)
-					conf_warning("override: %s changes choice state", sym->name);
-				cs->def[def].val = sym;
-				break;
-			}
-			cs->def[def].tri = EXPR_OR(cs->def[def].tri, sym->def[def].tri);
-		}
-	}
-	free(line);
-	fclose(in);
-	return 0;
-}
-
-int conf_read(const char *name)
-{
-	struct symbol *sym;
-	int conf_unsaved = 0;
-	int i;
-
-	sym_set_change_count(0);
-
-	if (conf_read_simple(name, S_DEF_USER)) {
-		sym_calc_value(modules_sym);
-		return 1;
-	}
-
-	sym_calc_value(modules_sym);
-
-	for_all_symbols(i, sym) {
-		sym_calc_value(sym);
-		if (sym_is_choice(sym) || (sym->flags & SYMBOL_NO_WRITE))
-			continue;
-		if (sym_has_value(sym) && (sym->flags & SYMBOL_WRITE)) {
-			/* check that calculated value agrees with saved value */
-			switch (sym->type) {
-			case S_BOOLEAN:
-			case S_TRISTATE:
-				if (sym->def[S_DEF_USER].tri == sym_get_tristate_value(sym))
-					continue;
-				break;
-			default:
-				if (!strcmp(sym->curr.val, sym->def[S_DEF_USER].val))
-					continue;
-				break;
-			}
-		} else if (!sym_has_value(sym) && !(sym->flags & SYMBOL_WRITE))
-			/* no previous value and not saved */
-			continue;
-		conf_unsaved++;
-		/* maybe print value in verbose mode... */
-	}
-
-	for_all_symbols(i, sym) {
-		if (sym_has_value(sym) && !sym_is_choice_value(sym)) {
-			/* Reset values of generates values, so they'll appear
-			 * as new, if they should become visible, but that
-			 * doesn't quite work if the Kconfig and the saved
-			 * configuration disagree.
-			 */
-			if (sym->visible == no && !conf_unsaved)
-				sym->flags &= ~SYMBOL_DEF_USER;
-			switch (sym->type) {
-			case S_STRING:
-			case S_INT:
-			case S_HEX:
-				/* Reset a string value if it's out of range */
-				if (sym_string_within_range(sym, sym->def[S_DEF_USER].val))
-					break;
-				sym->flags &= ~(SYMBOL_VALID|SYMBOL_DEF_USER);
-				conf_unsaved++;
-				break;
-			default:
-				break;
-			}
-		}
-	}
-
-	sym_add_change_count(conf_warnings || conf_unsaved);
-
-	return 0;
-}
-
-/*
- * Kconfig configuration printer
- *
- * This printer is used when generating the resulting configuration after
- * kconfig invocation and `defconfig' files. Unset symbol might be omitted by
- * passing a non-NULL argument to the printer.
- *
- */
-static void
-kconfig_print_symbol(FILE *fp, struct symbol *sym, const char *value, void *arg)
-{
-
-	switch (sym->type) {
-	case S_BOOLEAN:
-	case S_TRISTATE:
-		if (*value == 'n') {
-			bool skip_unset = (arg != NULL);
-
-			if (!skip_unset)
-				fprintf(fp, "# %s%s is not set\n",
-				    CONFIG_, sym->name);
-			return;
-		}
-		break;
-	default:
-		break;
-	}
-
-	fprintf(fp, "%s%s=%s\n", CONFIG_, sym->name, value);
-}
-
-static void
-kconfig_print_comment(FILE *fp, const char *value, void *arg)
-{
-	const char *p = value;
-	size_t l;
-
-	for (;;) {
-		l = strcspn(p, "\n");
-		fprintf(fp, "#");
-		if (l) {
-			fprintf(fp, " ");
-			xfwrite(p, l, 1, fp);
-			p += l;
-		}
-		fprintf(fp, "\n");
-		if (*p++ == '\0')
-			break;
-	}
-}
-
-static struct conf_printer kconfig_printer_cb =
-{
-	.print_symbol = kconfig_print_symbol,
-	.print_comment = kconfig_print_comment,
-};
-
-/*
- * Header printer
- *
- * This printer is used when generating the `include/generated/autoconf.h' file.
- */
-static void
-header_print_symbol(FILE *fp, struct symbol *sym, const char *value, void *arg)
-{
-
-	switch (sym->type) {
-	case S_BOOLEAN:
-	case S_TRISTATE: {
-		const char *suffix = "";
-
-		switch (*value) {
-		case 'n':
-			break;
-		case 'm':
-			suffix = "_MODULE";
-			/* fall through */
-		default:
-			fprintf(fp, "#define %s%s%s 1\n",
-			    CONFIG_, sym->name, suffix);
-		}
-		break;
-	}
-	case S_HEX: {
-		const char *prefix = "";
-
-		if (value[0] != '0' || (value[1] != 'x' && value[1] != 'X'))
-			prefix = "0x";
-		fprintf(fp, "#define %s%s %s%s\n",
-		    CONFIG_, sym->name, prefix, value);
-		break;
-	}
-	case S_STRING:
-	case S_INT:
-		fprintf(fp, "#define %s%s %s\n",
-		    CONFIG_, sym->name, value);
-		break;
-	default:
-		break;
-	}
-
-}
-
-static void
-header_print_comment(FILE *fp, const char *value, void *arg)
-{
-	const char *p = value;
-	size_t l;
-
-	fprintf(fp, "/*\n");
-	for (;;) {
-		l = strcspn(p, "\n");
-		fprintf(fp, " *");
-		if (l) {
-			fprintf(fp, " ");
-			xfwrite(p, l, 1, fp);
-			p += l;
-		}
-		fprintf(fp, "\n");
-		if (*p++ == '\0')
-			break;
-	}
-	fprintf(fp, " */\n");
-}
-
-static struct conf_printer header_printer_cb =
-{
-	.print_symbol = header_print_symbol,
-	.print_comment = header_print_comment,
-};
-
-/*
- * Tristate printer
- *
- * This printer is used when generating the `include/config/tristate.conf' file.
- */
-static void
-tristate_print_symbol(FILE *fp, struct symbol *sym, const char *value, void *arg)
-{
-
-	if (sym->type == S_TRISTATE && *value != 'n')
-		fprintf(fp, "%s%s=%c\n", CONFIG_, sym->name, (char)toupper(*value));
-}
-
-static struct conf_printer tristate_printer_cb =
-{
-	.print_symbol = tristate_print_symbol,
-	.print_comment = kconfig_print_comment,
-};
-
-static void conf_write_symbol(FILE *fp, struct symbol *sym,
-			      struct conf_printer *printer, void *printer_arg)
-{
-	const char *str;
-
-	switch (sym->type) {
-	case S_UNKNOWN:
-		break;
-	case S_STRING:
-		str = sym_get_string_value(sym);
-		str = sym_escape_string_value(str);
-		printer->print_symbol(fp, sym, str, printer_arg);
-		free((void *)str);
-		break;
-	default:
-		str = sym_get_string_value(sym);
-		printer->print_symbol(fp, sym, str, printer_arg);
-	}
-}
-
-static void
-conf_write_heading(FILE *fp, struct conf_printer *printer, void *printer_arg)
-{
-	char buf[256];
-
-	snprintf(buf, sizeof(buf),
-	    "\n"
-	    "Automatically generated file; DO NOT EDIT.\n"
-	    "%s\n",
-	    rootmenu.prompt->text);
-
-	printer->print_comment(fp, buf, printer_arg);
-}
-
-/*
- * Write out a minimal config.
- * All values that has default values are skipped as this is redundant.
- */
-int conf_write_defconfig(const char *filename)
-{
-	struct symbol *sym;
-	struct menu *menu;
-	FILE *out;
-
-	out = fopen(filename, "w");
-	if (!out)
-		return 1;
-
-	sym_clear_all_valid();
-
-	/* Traverse all menus to find all relevant symbols */
-	menu = rootmenu.list;
-
-	while (menu != NULL)
-	{
-		sym = menu->sym;
-		if (sym == NULL) {
-			if (!menu_is_visible(menu))
-				goto next_menu;
-		} else if (!sym_is_choice(sym)) {
-			sym_calc_value(sym);
-			if (!(sym->flags & SYMBOL_WRITE))
-				goto next_menu;
-			sym->flags &= ~SYMBOL_WRITE;
-			/* If we cannot change the symbol - skip */
-			if (!sym_is_changeable(sym))
-				goto next_menu;
-			/* If symbol equals to default value - skip */
-			if (strcmp(sym_get_string_value(sym), sym_get_string_default(sym)) == 0)
-				goto next_menu;
-
-			/*
-			 * If symbol is a choice value and equals to the
-			 * default for a choice - skip.
-			 * But only if value is bool and equal to "y" and
-			 * choice is not "optional".
-			 * (If choice is "optional" then all values can be "n")
-			 */
-			if (sym_is_choice_value(sym)) {
-				struct symbol *cs;
-				struct symbol *ds;
-
-				cs = prop_get_symbol(sym_get_choice_prop(sym));
-				ds = sym_choice_default(cs);
-				if (!sym_is_optional(cs) && sym == ds) {
-					if ((sym->type == S_BOOLEAN) &&
-					    sym_get_tristate_value(sym) == yes)
-						goto next_menu;
-				}
-			}
-			conf_write_symbol(out, sym, &kconfig_printer_cb, NULL);
-		}
-next_menu:
-		if (menu->list != NULL) {
-			menu = menu->list;
-		}
-		else if (menu->next != NULL) {
-			menu = menu->next;
-		} else {
-			while ((menu = menu->parent)) {
-				if (menu->next != NULL) {
-					menu = menu->next;
-					break;
-				}
-			}
-		}
-	}
-	fclose(out);
-	return 0;
-}
-
-int conf_write(const char *name)
-{
-	FILE *out;
-	struct symbol *sym;
-	struct menu *menu;
-	const char *str;
-	char tmpname[PATH_MAX + 1], oldname[PATH_MAX + 1];
-	char *env;
-	int i;
-	bool need_newline = false;
-
-	if (!name)
-		name = conf_get_configname();
-
-	if (!*name) {
-		fprintf(stderr, "config name is empty\n");
-		return -1;
-	}
-
-	if (is_dir(name)) {
-		fprintf(stderr, "%s: Is a directory\n", name);
-		return -1;
-	}
-
-	if (make_parent_dir(name))
-		return -1;
-
-	env = getenv("KCONFIG_OVERWRITECONFIG");
-	if (env && *env) {
-		*tmpname = 0;
-		out = fopen(name, "w");
-	} else {
-		snprintf(tmpname, sizeof(tmpname), "%s.%d.tmp",
-			 name, (int)getpid());
-		out = fopen(tmpname, "w");
-	}
-	if (!out)
-		return 1;
-
-	conf_write_heading(out, &kconfig_printer_cb, NULL);
-
-	if (!conf_get_changed())
-		sym_clear_all_valid();
-
-	menu = rootmenu.list;
-	while (menu) {
-		sym = menu->sym;
-		if (!sym) {
-			if (!menu_is_visible(menu))
-				goto next;
-			str = menu_get_prompt(menu);
-			fprintf(out, "\n"
-				     "#\n"
-				     "# %s\n"
-				     "#\n", str);
-			need_newline = false;
-		} else if (!(sym->flags & SYMBOL_CHOICE) &&
-			   !(sym->flags & SYMBOL_WRITTEN)) {
-			sym_calc_value(sym);
-			if (!(sym->flags & SYMBOL_WRITE))
-				goto next;
-			if (need_newline) {
-				fprintf(out, "\n");
-				need_newline = false;
-			}
-			sym->flags |= SYMBOL_WRITTEN;
-			conf_write_symbol(out, sym, &kconfig_printer_cb, NULL);
-		}
-
-next:
-		if (menu->list) {
-			menu = menu->list;
-			continue;
-		}
-		if (menu->next)
-			menu = menu->next;
-		else while ((menu = menu->parent)) {
-			if (!menu->sym && menu_is_visible(menu) &&
-			    menu != &rootmenu) {
-				str = menu_get_prompt(menu);
-				fprintf(out, "# end of %s\n", str);
-				need_newline = true;
-			}
-			if (menu->next) {
-				menu = menu->next;
-				break;
-			}
-		}
-	}
-	fclose(out);
-
-	for_all_symbols(i, sym)
-		sym->flags &= ~SYMBOL_WRITTEN;
-
-	if (*tmpname) {
-		if (is_same(name, tmpname)) {
-			conf_message("No change to %s", name);
-			unlink(tmpname);
-			sym_set_change_count(0);
-			return 0;
-		}
-
-		snprintf(oldname, sizeof(oldname), "%s.old", name);
-		rename(name, oldname);
-		if (rename(tmpname, name))
-			return 1;
-	}
-
-	conf_message("configuration written to %s", name);
-
-	sym_set_change_count(0);
-
-	return 0;
-}
-
-/* write a dependency file as used by kbuild to track dependencies */
-static int conf_write_dep(const char *name)
-{
-	struct file *file;
-	FILE *out;
-
-	out = fopen("..config.tmp", "w");
-	if (!out)
-		return 1;
-	fprintf(out, "deps_config := \\\n");
-	for (file = file_list; file; file = file->next) {
-		if (file->next)
-			fprintf(out, "\t%s \\\n", file->name);
-		else
-			fprintf(out, "\t%s\n", file->name);
-	}
-	fprintf(out, "\n%s: \\\n"
-		     "\t$(deps_config)\n\n", conf_get_autoconfig_name());
-
-	env_write_dep(out, conf_get_autoconfig_name());
-
-	fprintf(out, "\n$(deps_config): ;\n");
-	fclose(out);
-
-	if (make_parent_dir(name))
-		return 1;
-	rename("..config.tmp", name);
-	return 0;
-}
-
-static int conf_touch_deps(void)
-{
-	const char *name;
-	struct symbol *sym;
-	int res, i;
-
-	strcpy(depfile_path, "include/config/");
-	depfile_prefix_len = strlen(depfile_path);
-
-	name = conf_get_autoconfig_name();
-	conf_read_simple(name, S_DEF_AUTO);
-	sym_calc_value(modules_sym);
-
-	for_all_symbols(i, sym) {
-		sym_calc_value(sym);
-		if ((sym->flags & SYMBOL_NO_WRITE) || !sym->name)
-			continue;
-		if (sym->flags & SYMBOL_WRITE) {
-			if (sym->flags & SYMBOL_DEF_AUTO) {
-				/*
-				 * symbol has old and new value,
-				 * so compare them...
-				 */
-				switch (sym->type) {
-				case S_BOOLEAN:
-				case S_TRISTATE:
-					if (sym_get_tristate_value(sym) ==
-					    sym->def[S_DEF_AUTO].tri)
-						continue;
-					break;
-				case S_STRING:
-				case S_HEX:
-				case S_INT:
-					if (!strcmp(sym_get_string_value(sym),
-						    sym->def[S_DEF_AUTO].val))
-						continue;
-					break;
-				default:
-					break;
-				}
-			} else {
-				/*
-				 * If there is no old value, only 'no' (unset)
-				 * is allowed as new value.
-				 */
-				switch (sym->type) {
-				case S_BOOLEAN:
-				case S_TRISTATE:
-					if (sym_get_tristate_value(sym) == no)
-						continue;
-					break;
-				default:
-					break;
-				}
-			}
-		} else if (!(sym->flags & SYMBOL_DEF_AUTO))
-			/* There is neither an old nor a new value. */
-			continue;
-		/* else
-		 *	There is an old value, but no new value ('no' (unset)
-		 *	isn't saved in auto.conf, so the old value is always
-		 *	different from 'no').
-		 */
-
-		res = conf_touch_dep(sym->name);
-		if (res)
-			return res;
-	}
-
-	return 0;
-}
-
-int conf_write_autoconf(int overwrite)
-{
-	struct symbol *sym;
-	const char *name;
-	const char *autoconf_name = conf_get_autoconfig_name();
-	FILE *out, *tristate, *out_h;
-	int i;
-
-	if (!overwrite && is_present(autoconf_name))
-		return 0;
-
-	conf_write_dep("include/config/auto.conf.cmd");
-
-	if (conf_touch_deps())
-		return 1;
-
-	out = fopen(".tmpconfig", "w");
-	if (!out)
-		return 1;
-
-	tristate = fopen(".tmpconfig_tristate", "w");
-	if (!tristate) {
-		fclose(out);
-		return 1;
-	}
-
-	out_h = fopen(".tmpconfig.h", "w");
-	if (!out_h) {
-		fclose(out);
-		fclose(tristate);
-		return 1;
-	}
-
-	conf_write_heading(out, &kconfig_printer_cb, NULL);
-
-	conf_write_heading(tristate, &tristate_printer_cb, NULL);
-
-	conf_write_heading(out_h, &header_printer_cb, NULL);
-
-	for_all_symbols(i, sym) {
-		sym_calc_value(sym);
-		if (!(sym->flags & SYMBOL_WRITE) || !sym->name)
-			continue;
-
-		/* write symbol to auto.conf, tristate and header files */
-		conf_write_symbol(out, sym, &kconfig_printer_cb, (void *)1);
-
-		conf_write_symbol(tristate, sym, &tristate_printer_cb, (void *)1);
-
-		conf_write_symbol(out_h, sym, &header_printer_cb, NULL);
-	}
-	fclose(out);
-	fclose(tristate);
-	fclose(out_h);
-
-	name = getenv("KCONFIG_AUTOHEADER");
-	if (!name)
-		name = "include/generated/autoconf.h";
-	if (make_parent_dir(name))
-		return 1;
-	if (rename(".tmpconfig.h", name))
-		return 1;
-
-	name = getenv("KCONFIG_TRISTATE");
-	if (!name)
-		name = "include/config/tristate.conf";
-	if (make_parent_dir(name))
-		return 1;
-	if (rename(".tmpconfig_tristate", name))
-		return 1;
-
-	if (make_parent_dir(autoconf_name))
-		return 1;
-	/*
-	 * This must be the last step, kbuild has a dependency on auto.conf
-	 * and this marks the successful completion of the previous steps.
-	 */
-	if (rename(".tmpconfig", autoconf_name))
-		return 1;
-
-	return 0;
-}
-
-static int sym_change_count;
-static void (*conf_changed_callback)(void);
-
-void sym_set_change_count(int count)
-{
-	int _sym_change_count = sym_change_count;
-	sym_change_count = count;
-	if (conf_changed_callback &&
-	    (bool)_sym_change_count != (bool)count)
-		conf_changed_callback();
-}
-
-void sym_add_change_count(int count)
-{
-	sym_set_change_count(count + sym_change_count);
-}
-
-bool conf_get_changed(void)
-{
-	return sym_change_count;
-}
-
-void conf_set_changed_callback(void (*fn)(void))
-{
-	conf_changed_callback = fn;
-}
-
-static bool randomize_choice_values(struct symbol *csym)
-{
-	struct property *prop;
-	struct symbol *sym;
-	struct expr *e;
-	int cnt, def;
-
-	/*
-	 * If choice is mod then we may have more items selected
-	 * and if no then no-one.
-	 * In both cases stop.
-	 */
-	if (csym->curr.tri != yes)
-		return false;
-
-	prop = sym_get_choice_prop(csym);
-
-	/* count entries in choice block */
-	cnt = 0;
-	expr_list_for_each_sym(prop->expr, e, sym)
-		cnt++;
-
-	/*
-	 * find a random value and set it to yes,
-	 * set the rest to no so we have only one set
-	 */
-	def = (rand() % cnt);
-
-	cnt = 0;
-	expr_list_for_each_sym(prop->expr, e, sym) {
-		if (def == cnt++) {
-			sym->def[S_DEF_USER].tri = yes;
-			csym->def[S_DEF_USER].val = sym;
-		}
-		else {
-			sym->def[S_DEF_USER].tri = no;
-		}
-		sym->flags |= SYMBOL_DEF_USER;
-		/* clear VALID to get value calculated */
-		sym->flags &= ~SYMBOL_VALID;
-	}
-	csym->flags |= SYMBOL_DEF_USER;
-	/* clear VALID to get value calculated */
-	csym->flags &= ~(SYMBOL_VALID);
-
-	return true;
-}
-
-void set_all_choice_values(struct symbol *csym)
-{
-	struct property *prop;
-	struct symbol *sym;
-	struct expr *e;
-
-	prop = sym_get_choice_prop(csym);
-
-	/*
-	 * Set all non-assinged choice values to no
-	 */
-	expr_list_for_each_sym(prop->expr, e, sym) {
-		if (!sym_has_value(sym))
-			sym->def[S_DEF_USER].tri = no;
-	}
-	csym->flags |= SYMBOL_DEF_USER;
-	/* clear VALID to get value calculated */
-	csym->flags &= ~(SYMBOL_VALID | SYMBOL_NEED_SET_CHOICE_VALUES);
-}
-
-bool conf_set_all_new_symbols(enum conf_def_mode mode)
-{
-	struct symbol *sym, *csym;
-	int i, cnt, pby, pty, ptm;	/* pby: probability of bool     = y
-					 * pty: probability of tristate = y
-					 * ptm: probability of tristate = m
-					 */
-
-	pby = 50; pty = ptm = 33; /* can't go as the default in switch-case
-				   * below, otherwise gcc whines about
-				   * -Wmaybe-uninitialized */
-	if (mode == def_random) {
-		int n, p[3];
-		char *env = getenv("KCONFIG_PROBABILITY");
-		n = 0;
-		while( env && *env ) {
-			char *endp;
-			int tmp = strtol( env, &endp, 10 );
-			if( tmp >= 0 && tmp <= 100 ) {
-				p[n++] = tmp;
-			} else {
-				errno = ERANGE;
-				perror( "KCONFIG_PROBABILITY" );
-				exit( 1 );
-			}
-			env = (*endp == ':') ? endp+1 : endp;
-			if( n >=3 ) {
-				break;
-			}
-		}
-		switch( n ) {
-		case 1:
-			pby = p[0]; ptm = pby/2; pty = pby-ptm;
-			break;
-		case 2:
-			pty = p[0]; ptm = p[1]; pby = pty + ptm;
-			break;
-		case 3:
-			pby = p[0]; pty = p[1]; ptm = p[2];
-			break;
-		}
-
-		if( pty+ptm > 100 ) {
-			errno = ERANGE;
-			perror( "KCONFIG_PROBABILITY" );
-			exit( 1 );
-		}
-	}
-	bool has_changed = false;
-
-	for_all_symbols(i, sym) {
-		if (sym_has_value(sym) || (sym->flags & SYMBOL_VALID))
-			continue;
-		switch (sym_get_type(sym)) {
-		case S_BOOLEAN:
-		case S_TRISTATE:
-			has_changed = true;
-			switch (mode) {
-			case def_yes:
-				sym->def[S_DEF_USER].tri = yes;
-				break;
-			case def_mod:
-				sym->def[S_DEF_USER].tri = mod;
-				break;
-			case def_no:
-				if (sym->flags & SYMBOL_ALLNOCONFIG_Y)
-					sym->def[S_DEF_USER].tri = yes;
-				else
-					sym->def[S_DEF_USER].tri = no;
-				break;
-			case def_random:
-				sym->def[S_DEF_USER].tri = no;
-				cnt = rand() % 100;
-				if (sym->type == S_TRISTATE) {
-					if (cnt < pty)
-						sym->def[S_DEF_USER].tri = yes;
-					else if (cnt < (pty+ptm))
-						sym->def[S_DEF_USER].tri = mod;
-				} else if (cnt < pby)
-					sym->def[S_DEF_USER].tri = yes;
-				break;
-			default:
-				continue;
-			}
-			if (!(sym_is_choice(sym) && mode == def_random))
-				sym->flags |= SYMBOL_DEF_USER;
-			break;
-		default:
-			break;
-		}
-
-	}
-
-	sym_clear_all_valid();
-
-	/*
-	 * We have different type of choice blocks.
-	 * If curr.tri equals to mod then we can select several
-	 * choice symbols in one block.
-	 * In this case we do nothing.
-	 * If curr.tri equals yes then only one symbol can be
-	 * selected in a choice block and we set it to yes,
-	 * and the rest to no.
-	 */
-	if (mode != def_random) {
-		for_all_symbols(i, csym) {
-			if ((sym_is_choice(csym) && !sym_has_value(csym)) ||
-			    sym_is_choice_value(csym))
-				csym->flags |= SYMBOL_NEED_SET_CHOICE_VALUES;
-		}
-	}
-
-	for_all_symbols(i, csym) {
-		if (sym_has_value(csym) || !sym_is_choice(csym))
-			continue;
-
-		sym_calc_value(csym);
-		if (mode == def_random)
-			has_changed = randomize_choice_values(csym);
-		else {
-			set_all_choice_values(csym);
-			has_changed = true;
-		}
-	}
-
-	return has_changed;
-}
diff --git a/util/kconfig/expr.c b/util/kconfig/expr.c
deleted file mode 100644
index 77ffff3a05..0000000000
--- a/util/kconfig/expr.c
+++ /dev/null
@@ -1,1297 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org>
- */
-
-#include <ctype.h>
-#include <errno.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "lkc.h"
-
-#define DEBUG_EXPR	0
-
-static int expr_eq(struct expr *e1, struct expr *e2);
-static struct expr *expr_eliminate_yn(struct expr *e);
-
-struct expr *expr_alloc_symbol(struct symbol *sym)
-{
-	struct expr *e = xcalloc(1, sizeof(*e));
-	e->type = E_SYMBOL;
-	e->left.sym = sym;
-	return e;
-}
-
-struct expr *expr_alloc_one(enum expr_type type, struct expr *ce)
-{
-	struct expr *e = xcalloc(1, sizeof(*e));
-	e->type = type;
-	e->left.expr = ce;
-	return e;
-}
-
-struct expr *expr_alloc_two(enum expr_type type, struct expr *e1, struct expr *e2)
-{
-	struct expr *e = xcalloc(1, sizeof(*e));
-	e->type = type;
-	e->left.expr = e1;
-	e->right.expr = e2;
-	return e;
-}
-
-struct expr *expr_alloc_comp(enum expr_type type, struct symbol *s1, struct symbol *s2)
-{
-	struct expr *e = xcalloc(1, sizeof(*e));
-	e->type = type;
-	e->left.sym = s1;
-	e->right.sym = s2;
-	return e;
-}
-
-struct expr *expr_alloc_and(struct expr *e1, struct expr *e2)
-{
-	if (!e1)
-		return e2;
-	return e2 ? expr_alloc_two(E_AND, e1, e2) : e1;
-}
-
-struct expr *expr_alloc_or(struct expr *e1, struct expr *e2)
-{
-	if (!e1)
-		return e2;
-	return e2 ? expr_alloc_two(E_OR, e1, e2) : e1;
-}
-
-struct expr *expr_copy(const struct expr *org)
-{
-	struct expr *e;
-
-	if (!org)
-		return NULL;
-
-	e = xmalloc(sizeof(*org));
-	memcpy(e, org, sizeof(*org));
-	switch (org->type) {
-	case E_SYMBOL:
-		e->left = org->left;
-		break;
-	case E_NOT:
-		e->left.expr = expr_copy(org->left.expr);
-		break;
-	case E_EQUAL:
-	case E_GEQ:
-	case E_GTH:
-	case E_LEQ:
-	case E_LTH:
-	case E_UNEQUAL:
-		e->left.sym = org->left.sym;
-		e->right.sym = org->right.sym;
-		break;
-	case E_AND:
-	case E_OR:
-	case E_LIST:
-		e->left.expr = expr_copy(org->left.expr);
-		e->right.expr = expr_copy(org->right.expr);
-		break;
-	default:
-		fprintf(stderr, "can't copy type %d\n", e->type);
-		free(e);
-		e = NULL;
-		break;
-	}
-
-	return e;
-}
-
-void expr_free(struct expr *e)
-{
-	if (!e)
-		return;
-
-	switch (e->type) {
-	case E_SYMBOL:
-		break;
-	case E_NOT:
-		expr_free(e->left.expr);
-		break;
-	case E_EQUAL:
-	case E_GEQ:
-	case E_GTH:
-	case E_LEQ:
-	case E_LTH:
-	case E_UNEQUAL:
-		break;
-	case E_OR:
-	case E_AND:
-		expr_free(e->left.expr);
-		expr_free(e->right.expr);
-		break;
-	default:
-		fprintf(stderr, "how to free type %d?\n", e->type);
-		break;
-	}
-	free(e);
-}
-
-static int trans_count;
-
-#define e1 (*ep1)
-#define e2 (*ep2)
-
-/*
- * expr_eliminate_eq() helper.
- *
- * Walks the two expression trees given in 'ep1' and 'ep2'. Any node that does
- * not have type 'type' (E_OR/E_AND) is considered a leaf, and is compared
- * against all other leaves. Two equal leaves are both replaced with either 'y'
- * or 'n' as appropriate for 'type', to be eliminated later.
- */
-static void __expr_eliminate_eq(enum expr_type type, struct expr **ep1, struct expr **ep2)
-{
-	/* Recurse down to leaves */
-
-	if (e1->type == type) {
-		__expr_eliminate_eq(type, &e1->left.expr, &e2);
-		__expr_eliminate_eq(type, &e1->right.expr, &e2);
-		return;
-	}
-	if (e2->type == type) {
-		__expr_eliminate_eq(type, &e1, &e2->left.expr);
-		__expr_eliminate_eq(type, &e1, &e2->right.expr);
-		return;
-	}
-
-	/* e1 and e2 are leaves. Compare them. */
-
-	if (e1->type == E_SYMBOL && e2->type == E_SYMBOL &&
-	    e1->left.sym == e2->left.sym &&
-	    (e1->left.sym == &symbol_yes || e1->left.sym == &symbol_no))
-		return;
-	if (!expr_eq(e1, e2))
-		return;
-
-	/* e1 and e2 are equal leaves. Prepare them for elimination. */
-
-	trans_count++;
-	expr_free(e1); expr_free(e2);
-	switch (type) {
-	case E_OR:
-		e1 = expr_alloc_symbol(&symbol_no);
-		e2 = expr_alloc_symbol(&symbol_no);
-		break;
-	case E_AND:
-		e1 = expr_alloc_symbol(&symbol_yes);
-		e2 = expr_alloc_symbol(&symbol_yes);
-		break;
-	default:
-		;
-	}
-}
-
-/*
- * Rewrites the expressions 'ep1' and 'ep2' to remove operands common to both.
- * Example reductions:
- *
- *	ep1: A && B           ->  ep1: y
- *	ep2: A && B && C      ->  ep2: C
- *
- *	ep1: A || B           ->  ep1: n
- *	ep2: A || B || C      ->  ep2: C
- *
- *	ep1: A && (B && FOO)  ->  ep1: FOO
- *	ep2: (BAR && B) && A  ->  ep2: BAR
- *
- *	ep1: A && (B || C)    ->  ep1: y
- *	ep2: (C || B) && A    ->  ep2: y
- *
- * Comparisons are done between all operands at the same "level" of && or ||.
- * For example, in the expression 'e1 && (e2 || e3) && (e4 || e5)', the
- * following operands will be compared:
- *
- *	- 'e1', 'e2 || e3', and 'e4 || e5', against each other
- *	- e2 against e3
- *	- e4 against e5
- *
- * Parentheses are irrelevant within a single level. 'e1 && (e2 && e3)' and
- * '(e1 && e2) && e3' are both a single level.
- *
- * See __expr_eliminate_eq() as well.
- */
-void expr_eliminate_eq(struct expr **ep1, struct expr **ep2)
-{
-	if (!e1 || !e2)
-		return;
-	switch (e1->type) {
-	case E_OR:
-	case E_AND:
-		__expr_eliminate_eq(e1->type, ep1, ep2);
-	default:
-		;
-	}
-	if (e1->type != e2->type) switch (e2->type) {
-	case E_OR:
-	case E_AND:
-		__expr_eliminate_eq(e2->type, ep1, ep2);
-	default:
-		;
-	}
-	e1 = expr_eliminate_yn(e1);
-	e2 = expr_eliminate_yn(e2);
-}
-
-#undef e1
-#undef e2
-
-/*
- * Returns true if 'e1' and 'e2' are equal, after minor simplification. Two
- * &&/|| expressions are considered equal if every operand in one expression
- * equals some operand in the other (operands do not need to appear in the same
- * order), recursively.
- */
-static int expr_eq(struct expr *e1, struct expr *e2)
-{
-	int res, old_count;
-
-	if (e1->type != e2->type)
-		return 0;
-	switch (e1->type) {
-	case E_EQUAL:
-	case E_GEQ:
-	case E_GTH:
-	case E_LEQ:
-	case E_LTH:
-	case E_UNEQUAL:
-		return e1->left.sym == e2->left.sym && e1->right.sym == e2->right.sym;
-	case E_SYMBOL:
-		return e1->left.sym == e2->left.sym;
-	case E_NOT:
-		return expr_eq(e1->left.expr, e2->left.expr);
-	case E_AND:
-	case E_OR:
-		e1 = expr_copy(e1);
-		e2 = expr_copy(e2);
-		old_count = trans_count;
-		expr_eliminate_eq(&e1, &e2);
-		res = (e1->type == E_SYMBOL && e2->type == E_SYMBOL &&
-		       e1->left.sym == e2->left.sym);
-		expr_free(e1);
-		expr_free(e2);
-		trans_count = old_count;
-		return res;
-	case E_LIST:
-	case E_RANGE:
-	case E_NONE:
-		/* panic */;
-	}
-
-	if (DEBUG_EXPR) {
-		expr_fprint(e1, stdout);
-		printf(" = ");
-		expr_fprint(e2, stdout);
-		printf(" ?\n");
-	}
-
-	return 0;
-}
-
-/*
- * Recursively performs the following simplifications in-place (as well as the
- * corresponding simplifications with swapped operands):
- *
- *	expr && n  ->  n
- *	expr && y  ->  expr
- *	expr || n  ->  expr
- *	expr || y  ->  y
- *
- * Returns the optimized expression.
- */
-static struct expr *expr_eliminate_yn(struct expr *e)
-{
-	struct expr *tmp;
-
-	if (e) switch (e->type) {
-	case E_AND:
-		e->left.expr = expr_eliminate_yn(e->left.expr);
-		e->right.expr = expr_eliminate_yn(e->right.expr);
-		if (e->left.expr->type == E_SYMBOL) {
-			if (e->left.expr->left.sym == &symbol_no) {
-				expr_free(e->left.expr);
-				expr_free(e->right.expr);
-				e->type = E_SYMBOL;
-				e->left.sym = &symbol_no;
-				e->right.expr = NULL;
-				return e;
-			} else if (e->left.expr->left.sym == &symbol_yes) {
-				free(e->left.expr);
-				tmp = e->right.expr;
-				*e = *(e->right.expr);
-				free(tmp);
-				return e;
-			}
-		}
-		if (e->right.expr->type == E_SYMBOL) {
-			if (e->right.expr->left.sym == &symbol_no) {
-				expr_free(e->left.expr);
-				expr_free(e->right.expr);
-				e->type = E_SYMBOL;
-				e->left.sym = &symbol_no;
-				e->right.expr = NULL;
-				return e;
-			} else if (e->right.expr->left.sym == &symbol_yes) {
-				free(e->right.expr);
-				tmp = e->left.expr;
-				*e = *(e->left.expr);
-				free(tmp);
-				return e;
-			}
-		}
-		break;
-	case E_OR:
-		e->left.expr = expr_eliminate_yn(e->left.expr);
-		e->right.expr = expr_eliminate_yn(e->right.expr);
-		if (e->left.expr->type == E_SYMBOL) {
-			if (e->left.expr->left.sym == &symbol_no) {
-				free(e->left.expr);
-				tmp = e->right.expr;
-				*e = *(e->right.expr);
-				free(tmp);
-				return e;
-			} else if (e->left.expr->left.sym == &symbol_yes) {
-				expr_free(e->left.expr);
-				expr_free(e->right.expr);
-				e->type = E_SYMBOL;
-				e->left.sym = &symbol_yes;
-				e->right.expr = NULL;
-				return e;
-			}
-		}
-		if (e->right.expr->type == E_SYMBOL) {
-			if (e->right.expr->left.sym == &symbol_no) {
-				free(e->right.expr);
-				tmp = e->left.expr;
-				*e = *(e->left.expr);
-				free(tmp);
-				return e;
-			} else if (e->right.expr->left.sym == &symbol_yes) {
-				expr_free(e->left.expr);
-				expr_free(e->right.expr);
-				e->type = E_SYMBOL;
-				e->left.sym = &symbol_yes;
-				e->right.expr = NULL;
-				return e;
-			}
-		}
-		break;
-	default:
-		;
-	}
-	return e;
-}
-
-/*
- * bool FOO!=n => FOO
- */
-struct expr *expr_trans_bool(struct expr *e)
-{
-	if (!e)
-		return NULL;
-	switch (e->type) {
-	case E_AND:
-	case E_OR:
-	case E_NOT:
-		e->left.expr = expr_trans_bool(e->left.expr);
-		e->right.expr = expr_trans_bool(e->right.expr);
-		break;
-	case E_UNEQUAL:
-		// FOO!=n -> FOO
-		if (e->left.sym->type == S_TRISTATE) {
-			if (e->right.sym == &symbol_no) {
-				e->type = E_SYMBOL;
-				e->right.sym = NULL;
-			}
-		}
-		break;
-	default:
-		;
-	}
-	return e;
-}
-
-/*
- * e1 || e2 -> ?
- */
-static struct expr *expr_join_or(struct expr *e1, struct expr *e2)
-{
-	struct expr *tmp;
-	struct symbol *sym1, *sym2;
-
-	if (expr_eq(e1, e2))
-		return expr_copy(e1);
-	if (e1->type != E_EQUAL && e1->type != E_UNEQUAL && e1->type != E_SYMBOL && e1->type != E_NOT)
-		return NULL;
-	if (e2->type != E_EQUAL && e2->type != E_UNEQUAL && e2->type != E_SYMBOL && e2->type != E_NOT)
-		return NULL;
-	if (e1->type == E_NOT) {
-		tmp = e1->left.expr;
-		if (tmp->type != E_EQUAL && tmp->type != E_UNEQUAL && tmp->type != E_SYMBOL)
-			return NULL;
-		sym1 = tmp->left.sym;
-	} else
-		sym1 = e1->left.sym;
-	if (e2->type == E_NOT) {
-		if (e2->left.expr->type != E_SYMBOL)
-			return NULL;
-		sym2 = e2->left.expr->left.sym;
-	} else
-		sym2 = e2->left.sym;
-	if (sym1 != sym2)
-		return NULL;
-	if (sym1->type != S_BOOLEAN && sym1->type != S_TRISTATE)
-		return NULL;
-	if (sym1->type == S_TRISTATE) {
-		if (e1->type == E_EQUAL && e2->type == E_EQUAL &&
-		    ((e1->right.sym == &symbol_yes && e2->right.sym == &symbol_mod) ||
-		     (e1->right.sym == &symbol_mod && e2->right.sym == &symbol_yes))) {
-			// (a='y') || (a='m') -> (a!='n')
-			return expr_alloc_comp(E_UNEQUAL, sym1, &symbol_no);
-		}
-		if (e1->type == E_EQUAL && e2->type == E_EQUAL &&
-		    ((e1->right.sym == &symbol_yes && e2->right.sym == &symbol_no) ||
-		     (e1->right.sym == &symbol_no && e2->right.sym == &symbol_yes))) {
-			// (a='y') || (a='n') -> (a!='m')
-			return expr_alloc_comp(E_UNEQUAL, sym1, &symbol_mod);
-		}
-		if (e1->type == E_EQUAL && e2->type == E_EQUAL &&
-		    ((e1->right.sym == &symbol_mod && e2->right.sym == &symbol_no) ||
-		     (e1->right.sym == &symbol_no && e2->right.sym == &symbol_mod))) {
-			// (a='m') || (a='n') -> (a!='y')
-			return expr_alloc_comp(E_UNEQUAL, sym1, &symbol_yes);
-		}
-	}
-	if (sym1->type == S_BOOLEAN && sym1 == sym2) {
-		if ((e1->type == E_NOT && e1->left.expr->type == E_SYMBOL && e2->type == E_SYMBOL) ||
-		    (e2->type == E_NOT && e2->left.expr->type == E_SYMBOL && e1->type == E_SYMBOL))
-			return expr_alloc_symbol(&symbol_yes);
-	}
-
-	if (DEBUG_EXPR) {
-		printf("optimize (");
-		expr_fprint(e1, stdout);
-		printf(") || (");
-		expr_fprint(e2, stdout);
-		printf(")?\n");
-	}
-	return NULL;
-}
-
-static struct expr *expr_join_and(struct expr *e1, struct expr *e2)
-{
-	struct expr *tmp;
-	struct symbol *sym1, *sym2;
-
-	if (expr_eq(e1, e2))
-		return expr_copy(e1);
-	if (e1->type != E_EQUAL && e1->type != E_UNEQUAL && e1->type != E_SYMBOL && e1->type != E_NOT)
-		return NULL;
-	if (e2->type != E_EQUAL && e2->type != E_UNEQUAL && e2->type != E_SYMBOL && e2->type != E_NOT)
-		return NULL;
-	if (e1->type == E_NOT) {
-		tmp = e1->left.expr;
-		if (tmp->type != E_EQUAL && tmp->type != E_UNEQUAL && tmp->type != E_SYMBOL)
-			return NULL;
-		sym1 = tmp->left.sym;
-	} else
-		sym1 = e1->left.sym;
-	if (e2->type == E_NOT) {
-		if (e2->left.expr->type != E_SYMBOL)
-			return NULL;
-		sym2 = e2->left.expr->left.sym;
-	} else
-		sym2 = e2->left.sym;
-	if (sym1 != sym2)
-		return NULL;
-	if (sym1->type != S_BOOLEAN && sym1->type != S_TRISTATE)
-		return NULL;
-
-	if ((e1->type == E_SYMBOL && e2->type == E_EQUAL && e2->right.sym == &symbol_yes) ||
-	    (e2->type == E_SYMBOL && e1->type == E_EQUAL && e1->right.sym == &symbol_yes))
-		// (a) && (a='y') -> (a='y')
-		return expr_alloc_comp(E_EQUAL, sym1, &symbol_yes);
-
-	if ((e1->type == E_SYMBOL && e2->type == E_UNEQUAL && e2->right.sym == &symbol_no) ||
-	    (e2->type == E_SYMBOL && e1->type == E_UNEQUAL && e1->right.sym == &symbol_no))
-		// (a) && (a!='n') -> (a)
-		return expr_alloc_symbol(sym1);
-
-	if ((e1->type == E_SYMBOL && e2->type == E_UNEQUAL && e2->right.sym == &symbol_mod) ||
-	    (e2->type == E_SYMBOL && e1->type == E_UNEQUAL && e1->right.sym == &symbol_mod))
-		// (a) && (a!='m') -> (a='y')
-		return expr_alloc_comp(E_EQUAL, sym1, &symbol_yes);
-
-	if (sym1->type == S_TRISTATE) {
-		if (e1->type == E_EQUAL && e2->type == E_UNEQUAL) {
-			// (a='b') && (a!='c') -> 'b'='c' ? 'n' : a='b'
-			sym2 = e1->right.sym;
-			if ((e2->right.sym->flags & SYMBOL_CONST) && (sym2->flags & SYMBOL_CONST))
-				return sym2 != e2->right.sym ? expr_alloc_comp(E_EQUAL, sym1, sym2)
-							     : expr_alloc_symbol(&symbol_no);
-		}
-		if (e1->type == E_UNEQUAL && e2->type == E_EQUAL) {
-			// (a='b') && (a!='c') -> 'b'='c' ? 'n' : a='b'
-			sym2 = e2->right.sym;
-			if ((e1->right.sym->flags & SYMBOL_CONST) && (sym2->flags & SYMBOL_CONST))
-				return sym2 != e1->right.sym ? expr_alloc_comp(E_EQUAL, sym1, sym2)
-							     : expr_alloc_symbol(&symbol_no);
-		}
-		if (e1->type == E_UNEQUAL && e2->type == E_UNEQUAL &&
-			   ((e1->right.sym == &symbol_yes && e2->right.sym == &symbol_no) ||
-			    (e1->right.sym == &symbol_no && e2->right.sym == &symbol_yes)))
-			// (a!='y') && (a!='n') -> (a='m')
-			return expr_alloc_comp(E_EQUAL, sym1, &symbol_mod);
-
-		if (e1->type == E_UNEQUAL && e2->type == E_UNEQUAL &&
-			   ((e1->right.sym == &symbol_yes && e2->right.sym == &symbol_mod) ||
-			    (e1->right.sym == &symbol_mod && e2->right.sym == &symbol_yes)))
-			// (a!='y') && (a!='m') -> (a='n')
-			return expr_alloc_comp(E_EQUAL, sym1, &symbol_no);
-
-		if (e1->type == E_UNEQUAL && e2->type == E_UNEQUAL &&
-			   ((e1->right.sym == &symbol_mod && e2->right.sym == &symbol_no) ||
-			    (e1->right.sym == &symbol_no && e2->right.sym == &symbol_mod)))
-			// (a!='m') && (a!='n') -> (a='m')
-			return expr_alloc_comp(E_EQUAL, sym1, &symbol_yes);
-
-		if ((e1->type == E_SYMBOL && e2->type == E_EQUAL && e2->right.sym == &symbol_mod) ||
-		    (e2->type == E_SYMBOL && e1->type == E_EQUAL && e1->right.sym == &symbol_mod) ||
-		    (e1->type == E_SYMBOL && e2->type == E_UNEQUAL && e2->right.sym == &symbol_yes) ||
-		    (e2->type == E_SYMBOL && e1->type == E_UNEQUAL && e1->right.sym == &symbol_yes))
-			return NULL;
-	}
-
-	if (DEBUG_EXPR) {
-		printf("optimize (");
-		expr_fprint(e1, stdout);
-		printf(") && (");
-		expr_fprint(e2, stdout);
-		printf(")?\n");
-	}
-	return NULL;
-}
-
-/*
- * expr_eliminate_dups() helper.
- *
- * Walks the two expression trees given in 'ep1' and 'ep2'. Any node that does
- * not have type 'type' (E_OR/E_AND) is considered a leaf, and is compared
- * against all other leaves to look for simplifications.
- */
-static void expr_eliminate_dups1(enum expr_type type, struct expr **ep1, struct expr **ep2)
-{
-#define e1 (*ep1)
-#define e2 (*ep2)
-	struct expr *tmp;
-
-	/* Recurse down to leaves */
-
-	if (e1->type == type) {
-		expr_eliminate_dups1(type, &e1->left.expr, &e2);
-		expr_eliminate_dups1(type, &e1->right.expr, &e2);
-		return;
-	}
-	if (e2->type == type) {
-		expr_eliminate_dups1(type, &e1, &e2->left.expr);
-		expr_eliminate_dups1(type, &e1, &e2->right.expr);
-		return;
-	}
-
-	/* e1 and e2 are leaves. Compare and process them. */
-
-	if (e1 == e2)
-		return;
-
-	switch (e1->type) {
-	case E_OR: case E_AND:
-		expr_eliminate_dups1(e1->type, &e1, &e1);
-	default:
-		;
-	}
-
-	switch (type) {
-	case E_OR:
-		tmp = expr_join_or(e1, e2);
-		if (tmp) {
-			expr_free(e1); expr_free(e2);
-			e1 = expr_alloc_symbol(&symbol_no);
-			e2 = tmp;
-			trans_count++;
-		}
-		break;
-	case E_AND:
-		tmp = expr_join_and(e1, e2);
-		if (tmp) {
-			expr_free(e1); expr_free(e2);
-			e1 = expr_alloc_symbol(&symbol_yes);
-			e2 = tmp;
-			trans_count++;
-		}
-		break;
-	default:
-		;
-	}
-#undef e1
-#undef e2
-}
-
-/*
- * Rewrites 'e' in-place to remove ("join") duplicate and other redundant
- * operands.
- *
- * Example simplifications:
- *
- *	A || B || A    ->  A || B
- *	A && B && A=y  ->  A=y && B
- *
- * Returns the deduplicated expression.
- */
-struct expr *expr_eliminate_dups(struct expr *e)
-{
-	int oldcount;
-	if (!e)
-		return e;
-
-	oldcount = trans_count;
-	while (1) {
-		trans_count = 0;
-		switch (e->type) {
-		case E_OR: case E_AND:
-			expr_eliminate_dups1(e->type, &e, &e);
-		default:
-			;
-		}
-		if (!trans_count)
-			/* No simplifications done in this pass. We're done */
-			break;
-		e = expr_eliminate_yn(e);
-	}
-	trans_count = oldcount;
-	return e;
-}
-
-/*
- * Performs various simplifications involving logical operators and
- * comparisons.
- *
- * Allocates and returns a new expression.
- */
-struct expr *expr_transform(struct expr *e)
-{
-	struct expr *tmp;
-
-	if (!e)
-		return NULL;
-	switch (e->type) {
-	case E_EQUAL:
-	case E_GEQ:
-	case E_GTH:
-	case E_LEQ:
-	case E_LTH:
-	case E_UNEQUAL:
-	case E_SYMBOL:
-	case E_LIST:
-		break;
-	default:
-		e->left.expr = expr_transform(e->left.expr);
-		e->right.expr = expr_transform(e->right.expr);
-	}
-
-	switch (e->type) {
-	case E_EQUAL:
-		if (e->left.sym->type != S_BOOLEAN)
-			break;
-		if (e->right.sym == &symbol_no) {
-			e->type = E_NOT;
-			e->left.expr = expr_alloc_symbol(e->left.sym);
-			e->right.sym = NULL;
-			break;
-		}
-		if (e->right.sym == &symbol_mod) {
-			printf("boolean symbol %s tested for 'm'? test forced to 'n'\n", e->left.sym->name);
-			e->type = E_SYMBOL;
-			e->left.sym = &symbol_no;
-			e->right.sym = NULL;
-			break;
-		}
-		if (e->right.sym == &symbol_yes) {
-			e->type = E_SYMBOL;
-			e->right.sym = NULL;
-			break;
-		}
-		break;
-	case E_UNEQUAL:
-		if (e->left.sym->type != S_BOOLEAN)
-			break;
-		if (e->right.sym == &symbol_no) {
-			e->type = E_SYMBOL;
-			e->right.sym = NULL;
-			break;
-		}
-		if (e->right.sym == &symbol_mod) {
-			printf("boolean symbol %s tested for 'm'? test forced to 'y'\n", e->left.sym->name);
-			e->type = E_SYMBOL;
-			e->left.sym = &symbol_yes;
-			e->right.sym = NULL;
-			break;
-		}
-		if (e->right.sym == &symbol_yes) {
-			e->type = E_NOT;
-			e->left.expr = expr_alloc_symbol(e->left.sym);
-			e->right.sym = NULL;
-			break;
-		}
-		break;
-	case E_NOT:
-		switch (e->left.expr->type) {
-		case E_NOT:
-			// !!a -> a
-			tmp = e->left.expr->left.expr;
-			free(e->left.expr);
-			free(e);
-			e = tmp;
-			e = expr_transform(e);
-			break;
-		case E_EQUAL:
-		case E_UNEQUAL:
-			// !a='x' -> a!='x'
-			tmp = e->left.expr;
-			free(e);
-			e = tmp;
-			e->type = e->type == E_EQUAL ? E_UNEQUAL : E_EQUAL;
-			break;
-		case E_LEQ:
-		case E_GEQ:
-			// !a<='x' -> a>'x'
-			tmp = e->left.expr;
-			free(e);
-			e = tmp;
-			e->type = e->type == E_LEQ ? E_GTH : E_LTH;
-			break;
-		case E_LTH:
-		case E_GTH:
-			// !a<'x' -> a>='x'
-			tmp = e->left.expr;
-			free(e);
-			e = tmp;
-			e->type = e->type == E_LTH ? E_GEQ : E_LEQ;
-			break;
-		case E_OR:
-			// !(a || b) -> !a && !b
-			tmp = e->left.expr;
-			e->type = E_AND;
-			e->right.expr = expr_alloc_one(E_NOT, tmp->right.expr);
-			tmp->type = E_NOT;
-			tmp->right.expr = NULL;
-			e = expr_transform(e);
-			break;
-		case E_AND:
-			// !(a && b) -> !a || !b
-			tmp = e->left.expr;
-			e->type = E_OR;
-			e->right.expr = expr_alloc_one(E_NOT, tmp->right.expr);
-			tmp->type = E_NOT;
-			tmp->right.expr = NULL;
-			e = expr_transform(e);
-			break;
-		case E_SYMBOL:
-			if (e->left.expr->left.sym == &symbol_yes) {
-				// !'y' -> 'n'
-				tmp = e->left.expr;
-				free(e);
-				e = tmp;
-				e->type = E_SYMBOL;
-				e->left.sym = &symbol_no;
-				break;
-			}
-			if (e->left.expr->left.sym == &symbol_mod) {
-				// !'m' -> 'm'
-				tmp = e->left.expr;
-				free(e);
-				e = tmp;
-				e->type = E_SYMBOL;
-				e->left.sym = &symbol_mod;
-				break;
-			}
-			if (e->left.expr->left.sym == &symbol_no) {
-				// !'n' -> 'y'
-				tmp = e->left.expr;
-				free(e);
-				e = tmp;
-				e->type = E_SYMBOL;
-				e->left.sym = &symbol_yes;
-				break;
-			}
-			break;
-		default:
-			;
-		}
-		break;
-	default:
-		;
-	}
-	return e;
-}
-
-int expr_contains_symbol(struct expr *dep, struct symbol *sym)
-{
-	if (!dep)
-		return 0;
-
-	switch (dep->type) {
-	case E_AND:
-	case E_OR:
-		return expr_contains_symbol(dep->left.expr, sym) ||
-		       expr_contains_symbol(dep->right.expr, sym);
-	case E_SYMBOL:
-		return dep->left.sym == sym;
-	case E_EQUAL:
-	case E_GEQ:
-	case E_GTH:
-	case E_LEQ:
-	case E_LTH:
-	case E_UNEQUAL:
-		return dep->left.sym == sym ||
-		       dep->right.sym == sym;
-	case E_NOT:
-		return expr_contains_symbol(dep->left.expr, sym);
-	default:
-		;
-	}
-	return 0;
-}
-
-bool expr_depends_symbol(struct expr *dep, struct symbol *sym)
-{
-	if (!dep)
-		return false;
-
-	switch (dep->type) {
-	case E_AND:
-		return expr_depends_symbol(dep->left.expr, sym) ||
-		       expr_depends_symbol(dep->right.expr, sym);
-	case E_SYMBOL:
-		return dep->left.sym == sym;
-	case E_EQUAL:
-		if (dep->left.sym == sym) {
-			if (dep->right.sym == &symbol_yes || dep->right.sym == &symbol_mod)
-				return true;
-		}
-		break;
-	case E_UNEQUAL:
-		if (dep->left.sym == sym) {
-			if (dep->right.sym == &symbol_no)
-				return true;
-		}
-		break;
-	default:
-		;
-	}
- 	return false;
-}
-
-/*
- * Inserts explicit comparisons of type 'type' to symbol 'sym' into the
- * expression 'e'.
- *
- * Examples transformations for type == E_UNEQUAL, sym == &symbol_no:
- *
- *	A              ->  A!=n
- *	!A             ->  A=n
- *	A && B         ->  !(A=n || B=n)
- *	A || B         ->  !(A=n && B=n)
- *	A && (B || C)  ->  !(A=n || (B=n && C=n))
- *
- * Allocates and returns a new expression.
- */
-struct expr *expr_trans_compare(struct expr *e, enum expr_type type, struct symbol *sym)
-{
-	struct expr *e1, *e2;
-
-	if (!e) {
-		e = expr_alloc_symbol(sym);
-		if (type == E_UNEQUAL)
-			e = expr_alloc_one(E_NOT, e);
-		return e;
-	}
-	switch (e->type) {
-	case E_AND:
-		e1 = expr_trans_compare(e->left.expr, E_EQUAL, sym);
-		e2 = expr_trans_compare(e->right.expr, E_EQUAL, sym);
-		if (sym == &symbol_yes)
-			e = expr_alloc_two(E_AND, e1, e2);
-		if (sym == &symbol_no)
-			e = expr_alloc_two(E_OR, e1, e2);
-		if (type == E_UNEQUAL)
-			e = expr_alloc_one(E_NOT, e);
-		return e;
-	case E_OR:
-		e1 = expr_trans_compare(e->left.expr, E_EQUAL, sym);
-		e2 = expr_trans_compare(e->right.expr, E_EQUAL, sym);
-		if (sym == &symbol_yes)
-			e = expr_alloc_two(E_OR, e1, e2);
-		if (sym == &symbol_no)
-			e = expr_alloc_two(E_AND, e1, e2);
-		if (type == E_UNEQUAL)
-			e = expr_alloc_one(E_NOT, e);
-		return e;
-	case E_NOT:
-		return expr_trans_compare(e->left.expr, type == E_EQUAL ? E_UNEQUAL : E_EQUAL, sym);
-	case E_UNEQUAL:
-	case E_LTH:
-	case E_LEQ:
-	case E_GTH:
-	case E_GEQ:
-	case E_EQUAL:
-		if (type == E_EQUAL) {
-			if (sym == &symbol_yes)
-				return expr_copy(e);
-			if (sym == &symbol_mod)
-				return expr_alloc_symbol(&symbol_no);
-			if (sym == &symbol_no)
-				return expr_alloc_one(E_NOT, expr_copy(e));
-		} else {
-			if (sym == &symbol_yes)
-				return expr_alloc_one(E_NOT, expr_copy(e));
-			if (sym == &symbol_mod)
-				return expr_alloc_symbol(&symbol_yes);
-			if (sym == &symbol_no)
-				return expr_copy(e);
-		}
-		break;
-	case E_SYMBOL:
-		return expr_alloc_comp(type, e->left.sym, sym);
-	case E_LIST:
-	case E_RANGE:
-	case E_NONE:
-		/* panic */;
-	}
-	return NULL;
-}
-
-enum string_value_kind {
-	k_string,
-	k_signed,
-	k_unsigned,
-};
-
-union string_value {
-	unsigned long long u;
-	signed long long s;
-};
-
-static enum string_value_kind expr_parse_string(const char *str,
-						enum symbol_type type,
-						union string_value *val)
-{
-	char *tail;
-	enum string_value_kind kind;
-
-	errno = 0;
-	switch (type) {
-	case S_BOOLEAN:
-	case S_TRISTATE:
-		val->s = !strcmp(str, "n") ? 0 :
-			 !strcmp(str, "m") ? 1 :
-			 !strcmp(str, "y") ? 2 : -1;
-		return k_signed;
-	case S_INT:
-		val->s = strtoll(str, &tail, 10);
-		kind = k_signed;
-		break;
-	case S_HEX:
-		val->u = strtoull(str, &tail, 16);
-		kind = k_unsigned;
-		break;
-	default:
-		val->s = strtoll(str, &tail, 0);
-		kind = k_signed;
-		break;
-	}
-	return !errno && !*tail && tail > str && isxdigit(tail[-1])
-	       ? kind : k_string;
-}
-
-tristate expr_calc_value(struct expr *e)
-{
-	tristate val1, val2;
-	const char *str1, *str2;
-	enum string_value_kind k1 = k_string, k2 = k_string;
-	union string_value lval = {}, rval = {};
-	int res;
-
-	if (!e)
-		return yes;
-
-	switch (e->type) {
-	case E_SYMBOL:
-		sym_calc_value(e->left.sym);
-		return e->left.sym->curr.tri;
-	case E_AND:
-		val1 = expr_calc_value(e->left.expr);
-		val2 = expr_calc_value(e->right.expr);
-		return EXPR_AND(val1, val2);
-	case E_OR:
-		val1 = expr_calc_value(e->left.expr);
-		val2 = expr_calc_value(e->right.expr);
-		return EXPR_OR(val1, val2);
-	case E_NOT:
-		val1 = expr_calc_value(e->left.expr);
-		return EXPR_NOT(val1);
-	case E_EQUAL:
-	case E_GEQ:
-	case E_GTH:
-	case E_LEQ:
-	case E_LTH:
-	case E_UNEQUAL:
-		break;
-	default:
-		printf("expr_calc_value: %d?\n", e->type);
-		return no;
-	}
-
-	sym_calc_value(e->left.sym);
-	sym_calc_value(e->right.sym);
-	str1 = sym_get_string_value(e->left.sym);
-	str2 = sym_get_string_value(e->right.sym);
-
-	if (e->left.sym->type != S_STRING || e->right.sym->type != S_STRING) {
-		k1 = expr_parse_string(str1, e->left.sym->type, &lval);
-		k2 = expr_parse_string(str2, e->right.sym->type, &rval);
-	}
-
-	if (k1 == k_string || k2 == k_string)
-		res = strcmp(str1, str2);
-	else if (k1 == k_unsigned || k2 == k_unsigned)
-		res = (lval.u > rval.u) - (lval.u < rval.u);
-	else /* if (k1 == k_signed && k2 == k_signed) */
-		res = (lval.s > rval.s) - (lval.s < rval.s);
-
-	switch(e->type) {
-	case E_EQUAL:
-		return res ? no : yes;
-	case E_GEQ:
-		return res >= 0 ? yes : no;
-	case E_GTH:
-		return res > 0 ? yes : no;
-	case E_LEQ:
-		return res <= 0 ? yes : no;
-	case E_LTH:
-		return res < 0 ? yes : no;
-	case E_UNEQUAL:
-		return res ? yes : no;
-	default:
-		printf("expr_calc_value: relation %d?\n", e->type);
-		return no;
-	}
-}
-
-static int expr_compare_type(enum expr_type t1, enum expr_type t2)
-{
-	if (t1 == t2)
-		return 0;
-	switch (t1) {
-	case E_LEQ:
-	case E_LTH:
-	case E_GEQ:
-	case E_GTH:
-		if (t2 == E_EQUAL || t2 == E_UNEQUAL)
-			return 1;
-	case E_EQUAL:
-	case E_UNEQUAL:
-		if (t2 == E_NOT)
-			return 1;
-	case E_NOT:
-		if (t2 == E_AND)
-			return 1;
-	case E_AND:
-		if (t2 == E_OR)
-			return 1;
-	case E_OR:
-		if (t2 == E_LIST)
-			return 1;
-	case E_LIST:
-		if (t2 == 0)
-			return 1;
-	default:
-		return -1;
-	}
-	printf("[%dgt%d?]", t1, t2);
-	return 0;
-}
-
-void expr_print(struct expr *e,
-		void (*fn)(void *, struct symbol *, const char *),
-		void *data, int prevtoken)
-{
-	if (!e) {
-		fn(data, NULL, "y");
-		return;
-	}
-
-	if (expr_compare_type(prevtoken, e->type) > 0)
-		fn(data, NULL, "(");
-	switch (e->type) {
-	case E_SYMBOL:
-		if (e->left.sym->name)
-			fn(data, e->left.sym, e->left.sym->name);
-		else
-			fn(data, NULL, "<choice>");
-		break;
-	case E_NOT:
-		fn(data, NULL, "!");
-		expr_print(e->left.expr, fn, data, E_NOT);
-		break;
-	case E_EQUAL:
-		if (e->left.sym->name)
-			fn(data, e->left.sym, e->left.sym->name);
-		else
-			fn(data, NULL, "<choice>");
-		fn(data, NULL, "=");
-		fn(data, e->right.sym, e->right.sym->name);
-		break;
-	case E_LEQ:
-	case E_LTH:
-		if (e->left.sym->name)
-			fn(data, e->left.sym, e->left.sym->name);
-		else
-			fn(data, NULL, "<choice>");
-		fn(data, NULL, e->type == E_LEQ ? "<=" : "<");
-		fn(data, e->right.sym, e->right.sym->name);
-		break;
-	case E_GEQ:
-	case E_GTH:
-		if (e->left.sym->name)
-			fn(data, e->left.sym, e->left.sym->name);
-		else
-			fn(data, NULL, "<choice>");
-		fn(data, NULL, e->type == E_GEQ ? ">=" : ">");
-		fn(data, e->right.sym, e->right.sym->name);
-		break;
-	case E_UNEQUAL:
-		if (e->left.sym->name)
-			fn(data, e->left.sym, e->left.sym->name);
-		else
-			fn(data, NULL, "<choice>");
-		fn(data, NULL, "!=");
-		fn(data, e->right.sym, e->right.sym->name);
-		break;
-	case E_OR:
-		expr_print(e->left.expr, fn, data, E_OR);
-		fn(data, NULL, " || ");
-		expr_print(e->right.expr, fn, data, E_OR);
-		break;
-	case E_AND:
-		expr_print(e->left.expr, fn, data, E_AND);
-		fn(data, NULL, " && ");
-		expr_print(e->right.expr, fn, data, E_AND);
-		break;
-	case E_LIST:
-		fn(data, e->right.sym, e->right.sym->name);
-		if (e->left.expr) {
-			fn(data, NULL, " ^ ");
-			expr_print(e->left.expr, fn, data, E_LIST);
-		}
-		break;
-	case E_RANGE:
-		fn(data, NULL, "[");
-		fn(data, e->left.sym, e->left.sym->name);
-		fn(data, NULL, " ");
-		fn(data, e->right.sym, e->right.sym->name);
-		fn(data, NULL, "]");
-		break;
-	default:
-	  {
-		char buf[32];
-		sprintf(buf, "<unknown type %d>", e->type);
-		fn(data, NULL, buf);
-		break;
-	  }
-	}
-	if (expr_compare_type(prevtoken, e->type) > 0)
-		fn(data, NULL, ")");
-}
-
-static void expr_print_file_helper(void *data, struct symbol *sym, const char *str)
-{
-	xfwrite(str, strlen(str), 1, data);
-}
-
-void expr_fprint(struct expr *e, FILE *out)
-{
-	expr_print(e, expr_print_file_helper, out, E_NONE);
-}
-
-static void expr_print_gstr_helper(void *data, struct symbol *sym, const char *str)
-{
-	struct gstr *gs = (struct gstr*)data;
-	const char *sym_str = NULL;
-
-	if (sym)
-		sym_str = sym_get_string_value(sym);
-
-	if (gs->max_width) {
-		unsigned extra_length = strlen(str);
-		const char *last_cr = strrchr(gs->s, '\n');
-		unsigned last_line_length;
-
-		if (sym_str)
-			extra_length += 4 + strlen(sym_str);
-
-		if (!last_cr)
-			last_cr = gs->s;
-
-		last_line_length = strlen(gs->s) - (last_cr - gs->s);
-
-		if ((last_line_length + extra_length) > gs->max_width)
-			str_append(gs, "\\\n");
-	}
-
-	str_append(gs, str);
-	if (sym && sym->type != S_UNKNOWN)
-		str_printf(gs, " [=%s]", sym_str);
-}
-
-void expr_gstr_print(struct expr *e, struct gstr *gs)
-{
-	expr_print(e, expr_print_gstr_helper, gs, E_NONE);
-}
-
-/*
- * Transform the top level "||" tokens into newlines and prepend each
- * line with a minus. This makes expressions much easier to read.
- * Suitable for reverse dependency expressions.
- */
-static void expr_print_revdep(struct expr *e,
-			      void (*fn)(void *, struct symbol *, const char *),
-			      void *data, tristate pr_type, const char **title)
-{
-	if (e->type == E_OR) {
-		expr_print_revdep(e->left.expr, fn, data, pr_type, title);
-		expr_print_revdep(e->right.expr, fn, data, pr_type, title);
-	} else if (expr_calc_value(e) == pr_type) {
-		if (*title) {
-			fn(data, NULL, *title);
-			*title = NULL;
-		}
-
-		fn(data, NULL, "  - ");
-		expr_print(e, fn, data, E_NONE);
-		fn(data, NULL, "\n");
-	}
-}
-
-void expr_gstr_print_revdep(struct expr *e, struct gstr *gs,
-			    tristate pr_type, const char *title)
-{
-	expr_print_revdep(e, expr_print_gstr_helper, gs, pr_type, &title);
-}
diff --git a/util/kconfig/expr.h b/util/kconfig/expr.h
deleted file mode 100644
index 017843c9a4..0000000000
--- a/util/kconfig/expr.h
+++ /dev/null
@@ -1,332 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org>
- */
-
-#ifndef EXPR_H
-#define EXPR_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <assert.h>
-#include <stdio.h>
-#include "list.h"
-#ifndef __cplusplus
-#include <stdbool.h>
-#endif
-
-struct file {
-	struct file *next;
-	struct file *parent;
-	const char *name;
-	int lineno;
-};
-
-typedef enum tristate {
-	no, mod, yes
-} tristate;
-
-enum expr_type {
-	E_NONE, E_OR, E_AND, E_NOT,
-	E_EQUAL, E_UNEQUAL, E_LTH, E_LEQ, E_GTH, E_GEQ,
-	E_LIST, E_SYMBOL, E_RANGE
-};
-
-union expr_data {
-	struct expr *expr;
-	struct symbol *sym;
-};
-
-struct expr {
-	enum expr_type type;
-	union expr_data left, right;
-};
-
-#define EXPR_OR(dep1, dep2)	(((dep1)>(dep2))?(dep1):(dep2))
-#define EXPR_AND(dep1, dep2)	(((dep1)<(dep2))?(dep1):(dep2))
-#define EXPR_NOT(dep)		(2-(dep))
-
-#define expr_list_for_each_sym(l, e, s) \
-	for (e = (l); e && (s = e->right.sym); e = e->left.expr)
-
-struct expr_value {
-	struct expr *expr;
-	tristate tri;
-};
-
-struct symbol_value {
-	void *val;
-	tristate tri;
-};
-
-enum symbol_type {
-	S_UNKNOWN, S_BOOLEAN, S_TRISTATE, S_INT, S_HEX, S_STRING
-};
-
-/* enum values are used as index to symbol.def[] */
-enum {
-	S_DEF_USER,		/* main user value */
-	S_DEF_AUTO,		/* values read from auto.conf */
-	S_DEF_DEF3,		/* Reserved for UI usage */
-	S_DEF_DEF4,		/* Reserved for UI usage */
-	S_DEF_COUNT
-};
-
-/*
- * Represents a configuration symbol.
- *
- * Choices are represented as a special kind of symbol and have the
- * SYMBOL_CHOICE bit set in 'flags'.
- */
-struct symbol {
-	/* The next symbol in the same bucket in the symbol hash table */
-	struct symbol *next;
-
-	/* The name of the symbol, e.g. "FOO" for 'config FOO' */
-	char *name;
-
-	/* S_BOOLEAN, S_TRISTATE, ... */
-	enum symbol_type type;
-
-	/*
-	 * The calculated value of the symbol. The SYMBOL_VALID bit is set in
-	 * 'flags' when this is up to date. Note that this value might differ
-	 * from the user value set in e.g. a .config file, due to visibility.
-	 */
-	struct symbol_value curr;
-
-	/*
-	 * Values for the symbol provided from outside. def[S_DEF_USER] holds
-	 * the .config value.
-	 */
-	struct symbol_value def[S_DEF_COUNT];
-
-	/*
-	 * An upper bound on the tristate value the user can set for the symbol
-	 * if it is a boolean or tristate. Calculated from prompt dependencies,
-	 * which also inherit dependencies from enclosing menus, choices, and
-	 * ifs. If 'n', the user value will be ignored.
-	 *
-	 * Symbols lacking prompts always have visibility 'n'.
-	 */
-	tristate visible;
-
-	/* SYMBOL_* flags */
-	int flags;
-
-	/* List of properties. See prop_type. */
-	struct property *prop;
-
-	/* Dependencies from enclosing menus, choices, and ifs */
-	struct expr_value dir_dep;
-
-	/* Reverse dependencies through being selected by other symbols */
-	struct expr_value rev_dep;
-
-	/*
-	 * "Weak" reverse dependencies through being implied by other symbols
-	 */
-	struct expr_value implied;
-};
-
-#define for_all_symbols(i, sym) for (i = 0; i < SYMBOL_HASHSIZE; i++) for (sym = symbol_hash[i]; sym; sym = sym->next)
-
-#define SYMBOL_CONST      0x0001  /* symbol is const */
-#define SYMBOL_CHECK      0x0008  /* used during dependency checking */
-#define SYMBOL_CHOICE     0x0010  /* start of a choice block (null name) */
-#define SYMBOL_CHOICEVAL  0x0020  /* used as a value in a choice block */
-#define SYMBOL_VALID      0x0080  /* set when symbol.curr is calculated */
-#define SYMBOL_OPTIONAL   0x0100  /* choice is optional - values can be 'n' */
-#define SYMBOL_WRITE      0x0200  /* write symbol to file (KCONFIG_CONFIG) */
-#define SYMBOL_CHANGED    0x0400  /* ? */
-#define SYMBOL_WRITTEN    0x0800  /* track info to avoid double-write to .config */
-#define SYMBOL_NO_WRITE   0x1000  /* Symbol for internal use only; it will not be written */
-#define SYMBOL_CHECKED    0x2000  /* used during dependency checking */
-#define SYMBOL_WARNED     0x8000  /* warning has been issued */
-
-/* Set when symbol.def[] is used */
-#define SYMBOL_DEF        0x10000  /* First bit of SYMBOL_DEF */
-#define SYMBOL_DEF_USER   0x10000  /* symbol.def[S_DEF_USER] is valid */
-#define SYMBOL_DEF_AUTO   0x20000  /* symbol.def[S_DEF_AUTO] is valid */
-#define SYMBOL_DEF3       0x40000  /* symbol.def[S_DEF_3] is valid */
-#define SYMBOL_DEF4       0x80000  /* symbol.def[S_DEF_4] is valid */
-
-/* choice values need to be set before calculating this symbol value */
-#define SYMBOL_NEED_SET_CHOICE_VALUES  0x100000
-
-/* Set symbol to y if allnoconfig; used for symbols that hide others */
-#define SYMBOL_ALLNOCONFIG_Y 0x200000
-
-#define SYMBOL_MAXLENGTH	256
-#define SYMBOL_HASHSIZE		9973
-
-/* A property represent the config options that can be associated
- * with a config "symbol".
- * Sample:
- * config FOO
- *         default y
- *         prompt "foo prompt"
- *         select BAR
- * config BAZ
- *         int "BAZ Value"
- *         range 1..255
- *
- * Please, also check parser.y:print_symbol() when modifying the
- * list of property types!
- */
-enum prop_type {
-	P_UNKNOWN,
-	P_PROMPT,   /* prompt "foo prompt" or "BAZ Value" */
-	P_COMMENT,  /* text associated with a comment */
-	P_MENU,     /* prompt associated with a menu or menuconfig symbol */
-	P_DEFAULT,  /* default y */
-	P_CHOICE,   /* choice value */
-	P_SELECT,   /* select BAR */
-	P_IMPLY,    /* imply BAR */
-	P_RANGE,    /* range 7..100 (for a symbol) */
-	P_SYMBOL,   /* where a symbol is defined */
-};
-
-struct property {
-	struct property *next;     /* next property - null if last */
-	struct symbol *sym;        /* the symbol for which the property is associated */
-	enum prop_type type;       /* type of property */
-	const char *text;          /* the prompt value - P_PROMPT, P_MENU, P_COMMENT */
-	struct expr_value visible;
-	struct expr *expr;         /* the optional conditional part of the property */
-	struct menu *menu;         /* the menu the property are associated with
-	                            * valid for: P_SELECT, P_RANGE, P_CHOICE,
-	                            * P_PROMPT, P_DEFAULT, P_MENU, P_COMMENT */
-	struct file *file;         /* what file was this property defined */
-	int lineno;                /* what lineno was this property defined */
-};
-
-#define for_all_properties(sym, st, tok) \
-	for (st = sym->prop; st; st = st->next) \
-		if (st->type == (tok))
-#define for_all_defaults(sym, st) for_all_properties(sym, st, P_DEFAULT)
-#define for_all_choices(sym, st) for_all_properties(sym, st, P_CHOICE)
-#define for_all_prompts(sym, st) \
-	for (st = sym->prop; st; st = st->next) \
-		if (st->text)
-
-/*
- * Represents a node in the menu tree, as seen in e.g. menuconfig (though used
- * for all front ends). Each symbol, menu, etc. defined in the Kconfig files
- * gets a node. A symbol defined in multiple locations gets one node at each
- * location.
- */
-struct menu {
-	/* The next menu node at the same level */
-	struct menu *next;
-
-	/* The parent menu node, corresponding to e.g. a menu or choice */
-	struct menu *parent;
-
-	/* The first child menu node, for e.g. menus and choices */
-	struct menu *list;
-
-	/*
-	 * The symbol associated with the menu node. Choices are implemented as
-	 * a special kind of symbol. NULL for menus, comments, and ifs.
-	 */
-	struct symbol *sym;
-
-	/*
-	 * The prompt associated with the node. This holds the prompt for a
-	 * symbol as well as the text for a menu or comment, along with the
-	 * type (P_PROMPT, P_MENU, etc.)
-	 */
-	struct property *prompt;
-
-	/*
-	 * 'visible if' dependencies. If more than one is given, they will be
-	 * ANDed together.
-	 */
-	struct expr *visibility;
-
-	/*
-	 * Ordinary dependencies from e.g. 'depends on' and 'if', ANDed
-	 * together
-	 */
-	struct expr *dep;
-
-	/* MENU_* flags */
-	unsigned int flags;
-
-	/* Any help text associated with the node */
-	char *help;
-
-	/* The location where the menu node appears in the Kconfig files */
-	struct file *file;
-	int lineno;
-
-	/* For use by front ends that need to store auxiliary data */
-	void *data;
-};
-
-/*
- * Set on a menu node when the corresponding symbol changes state in some way.
- * Can be checked by front ends.
- */
-#define MENU_CHANGED		0x0001
-
-#define MENU_ROOT		0x0002
-
-struct jump_key {
-	struct list_head entries;
-	size_t offset;
-	struct menu *target;
-	int index;
-};
-
-#define JUMP_NB			9
-
-extern struct file *file_list;
-extern struct file *current_file;
-struct file *lookup_file(const char *name);
-
-extern struct symbol symbol_yes, symbol_no, symbol_mod;
-extern struct symbol *modules_sym;
-extern struct symbol *sym_defconfig_list;
-extern int cdebug;
-struct expr *expr_alloc_symbol(struct symbol *sym);
-struct expr *expr_alloc_one(enum expr_type type, struct expr *ce);
-struct expr *expr_alloc_two(enum expr_type type, struct expr *e1, struct expr *e2);
-struct expr *expr_alloc_comp(enum expr_type type, struct symbol *s1, struct symbol *s2);
-struct expr *expr_alloc_and(struct expr *e1, struct expr *e2);
-struct expr *expr_alloc_or(struct expr *e1, struct expr *e2);
-struct expr *expr_copy(const struct expr *org);
-void expr_free(struct expr *e);
-void expr_eliminate_eq(struct expr **ep1, struct expr **ep2);
-tristate expr_calc_value(struct expr *e);
-struct expr *expr_trans_bool(struct expr *e);
-struct expr *expr_eliminate_dups(struct expr *e);
-struct expr *expr_transform(struct expr *e);
-int expr_contains_symbol(struct expr *dep, struct symbol *sym);
-bool expr_depends_symbol(struct expr *dep, struct symbol *sym);
-struct expr *expr_trans_compare(struct expr *e, enum expr_type type, struct symbol *sym);
-
-void expr_fprint(struct expr *e, FILE *out);
-struct gstr; /* forward */
-void expr_gstr_print(struct expr *e, struct gstr *gs);
-void expr_gstr_print_revdep(struct expr *e, struct gstr *gs,
-			    tristate pr_type, const char *title);
-
-static inline int expr_is_yes(struct expr *e)
-{
-	return !e || (e->type == E_SYMBOL && e->left.sym == &symbol_yes);
-}
-
-static inline int expr_is_no(struct expr *e)
-{
-	return e && (e->type == E_SYMBOL && e->left.sym == &symbol_no);
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* EXPR_H */
diff --git a/util/kconfig/gconf-cfg.sh b/util/kconfig/gconf-cfg.sh
deleted file mode 100755
index 480ecd8b9f..0000000000
--- a/util/kconfig/gconf-cfg.sh
+++ /dev/null
@@ -1,30 +0,0 @@
-#!/bin/sh
-# SPDX-License-Identifier: GPL-2.0
-
-PKG="gtk+-2.0 gmodule-2.0 libglade-2.0"
-
-if [ -z "$(command -v pkg-config)" ]; then
-	echo >&2 "*"
-	echo >&2 "* 'make gconfig' requires 'pkg-config'. Please install it."
-	echo >&2 "*"
-	exit 1
-fi
-
-if ! pkg-config --exists $PKG; then
-	echo >&2 "*"
-	echo >&2 "* Unable to find the GTK+ installation. Please make sure that"
-	echo >&2 "* the GTK+ 2.0 development package is correctly installed."
-	echo >&2 "* You need $PKG"
-	echo >&2 "*"
-	exit 1
-fi
-
-if ! pkg-config --atleast-version=2.0.0 gtk+-2.0; then
-	echo >&2 "*"
-	echo >&2 "* GTK+ is present but version >= 2.0.0 is required."
-	echo >&2 "*"
-	exit 1
-fi
-
-echo cflags=\"$(pkg-config --cflags $PKG)\"
-echo libs=\"$(pkg-config --libs $PKG)\"
diff --git a/util/kconfig/gconf.c b/util/kconfig/gconf.c
deleted file mode 100644
index e36b342f10..0000000000
--- a/util/kconfig/gconf.c
+++ /dev/null
@@ -1,1516 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2002-2003 Romain Lievin <roms@tilp.info>
- */
-
-#ifdef HAVE_CONFIG_H
-#  include <config.h>
-#endif
-
-#include <stdlib.h>
-#include "lkc.h"
-#include "images.h"
-
-#include <glade/glade.h>
-#include <gtk/gtk.h>
-#include <glib.h>
-#include <gdk/gdkkeysyms.h>
-
-#include <stdio.h>
-#include <string.h>
-#include <unistd.h>
-#include <time.h>
-
-//#define DEBUG
-
-enum {
-	SINGLE_VIEW, SPLIT_VIEW, FULL_VIEW
-};
-
-enum {
-	OPT_NORMAL, OPT_ALL, OPT_PROMPT
-};
-
-static gint view_mode = FULL_VIEW;
-static gboolean show_name = TRUE;
-static gboolean show_range = TRUE;
-static gboolean show_value = TRUE;
-static gboolean resizeable = FALSE;
-static int opt_mode = OPT_NORMAL;
-
-GtkWidget *main_wnd = NULL;
-GtkWidget *tree1_w = NULL;	// left  frame
-GtkWidget *tree2_w = NULL;	// right frame
-GtkWidget *text_w = NULL;
-GtkWidget *hpaned = NULL;
-GtkWidget *vpaned = NULL;
-GtkWidget *back_btn = NULL;
-GtkWidget *save_btn = NULL;
-GtkWidget *save_menu_item = NULL;
-
-GtkTextTag *tag1, *tag2;
-GdkColor color;
-
-GtkTreeStore *tree1, *tree2, *tree;
-GtkTreeModel *model1, *model2;
-static GtkTreeIter *parents[256];
-static gint indent;
-
-static struct menu *current; // current node for SINGLE view
-static struct menu *browsed; // browsed node for SPLIT view
-
-enum {
-	COL_OPTION, COL_NAME, COL_NO, COL_MOD, COL_YES, COL_VALUE,
-	COL_MENU, COL_COLOR, COL_EDIT, COL_PIXBUF,
-	COL_PIXVIS, COL_BTNVIS, COL_BTNACT, COL_BTNINC, COL_BTNRAD,
-	COL_NUMBER
-};
-
-static void display_list(void);
-static void display_tree(struct menu *menu);
-static void display_tree_part(void);
-static void update_tree(struct menu *src, GtkTreeIter * dst);
-static void set_node(GtkTreeIter * node, struct menu *menu, gchar ** row);
-static gchar **fill_row(struct menu *menu);
-static void conf_changed(void);
-
-/* Helping/Debugging Functions */
-#ifdef DEBUG
-static const char *dbg_sym_flags(int val)
-{
-	static char buf[256];
-
-	bzero(buf, 256);
-
-	if (val & SYMBOL_CONST)
-		strcat(buf, "const/");
-	if (val & SYMBOL_CHECK)
-		strcat(buf, "check/");
-	if (val & SYMBOL_CHOICE)
-		strcat(buf, "choice/");
-	if (val & SYMBOL_CHOICEVAL)
-		strcat(buf, "choiceval/");
-	if (val & SYMBOL_VALID)
-		strcat(buf, "valid/");
-	if (val & SYMBOL_OPTIONAL)
-		strcat(buf, "optional/");
-	if (val & SYMBOL_WRITE)
-		strcat(buf, "write/");
-	if (val & SYMBOL_CHANGED)
-		strcat(buf, "changed/");
-	if (val & SYMBOL_NO_WRITE)
-		strcat(buf, "no_write/");
-
-	buf[strlen(buf) - 1] = '\0';
-
-	return buf;
-}
-#endif
-
-static void replace_button_icon(GladeXML *xml, GdkDrawable *window,
-				GtkStyle *style, gchar *btn_name, gchar **xpm)
-{
-	GdkPixmap *pixmap;
-	GdkBitmap *mask;
-	GtkToolButton *button;
-	GtkWidget *image;
-
-	pixmap = gdk_pixmap_create_from_xpm_d(window, &mask,
-					      &style->bg[GTK_STATE_NORMAL],
-					      xpm);
-
-	button = GTK_TOOL_BUTTON(glade_xml_get_widget(xml, btn_name));
-	image = gtk_image_new_from_pixmap(pixmap, mask);
-	gtk_widget_show(image);
-	gtk_tool_button_set_icon_widget(button, image);
-}
-
-/* Main Window Initialization */
-static void init_main_window(const gchar *glade_file)
-{
-	GladeXML *xml;
-	GtkWidget *widget;
-	GtkTextBuffer *txtbuf;
-	GtkStyle *style;
-
-	xml = glade_xml_new(glade_file, "window1", NULL);
-	if (!xml)
-		g_error("GUI loading failed !\n");
-	glade_xml_signal_autoconnect(xml);
-
-	main_wnd = glade_xml_get_widget(xml, "window1");
-	hpaned = glade_xml_get_widget(xml, "hpaned1");
-	vpaned = glade_xml_get_widget(xml, "vpaned1");
-	tree1_w = glade_xml_get_widget(xml, "treeview1");
-	tree2_w = glade_xml_get_widget(xml, "treeview2");
-	text_w = glade_xml_get_widget(xml, "textview3");
-
-	back_btn = glade_xml_get_widget(xml, "button1");
-	gtk_widget_set_sensitive(back_btn, FALSE);
-
-	widget = glade_xml_get_widget(xml, "show_name1");
-	gtk_check_menu_item_set_active((GtkCheckMenuItem *) widget,
-				       show_name);
-
-	widget = glade_xml_get_widget(xml, "show_range1");
-	gtk_check_menu_item_set_active((GtkCheckMenuItem *) widget,
-				       show_range);
-
-	widget = glade_xml_get_widget(xml, "show_data1");
-	gtk_check_menu_item_set_active((GtkCheckMenuItem *) widget,
-				       show_value);
-
-	save_btn = glade_xml_get_widget(xml, "button3");
-	save_menu_item = glade_xml_get_widget(xml, "save1");
-	conf_set_changed_callback(conf_changed);
-
-	style = gtk_widget_get_style(main_wnd);
-	widget = glade_xml_get_widget(xml, "toolbar1");
-
-	replace_button_icon(xml, main_wnd->window, style,
-			    "button4", (gchar **) xpm_single_view);
-	replace_button_icon(xml, main_wnd->window, style,
-			    "button5", (gchar **) xpm_split_view);
-	replace_button_icon(xml, main_wnd->window, style,
-			    "button6", (gchar **) xpm_tree_view);
-
-	txtbuf = gtk_text_view_get_buffer(GTK_TEXT_VIEW(text_w));
-	tag1 = gtk_text_buffer_create_tag(txtbuf, "mytag1",
-					  "foreground", "red",
-					  "weight", PANGO_WEIGHT_BOLD,
-					  NULL);
-	tag2 = gtk_text_buffer_create_tag(txtbuf, "mytag2",
-					  /*"style", PANGO_STYLE_OBLIQUE, */
-					  NULL);
-
-	gtk_window_set_title(GTK_WINDOW(main_wnd), rootmenu.prompt->text);
-
-	gtk_widget_show(main_wnd);
-}
-
-static void init_tree_model(void)
-{
-	gint i;
-
-	tree = tree2 = gtk_tree_store_new(COL_NUMBER,
-					  G_TYPE_STRING, G_TYPE_STRING,
-					  G_TYPE_STRING, G_TYPE_STRING,
-					  G_TYPE_STRING, G_TYPE_STRING,
-					  G_TYPE_POINTER, GDK_TYPE_COLOR,
-					  G_TYPE_BOOLEAN, GDK_TYPE_PIXBUF,
-					  G_TYPE_BOOLEAN, G_TYPE_BOOLEAN,
-					  G_TYPE_BOOLEAN, G_TYPE_BOOLEAN,
-					  G_TYPE_BOOLEAN);
-	model2 = GTK_TREE_MODEL(tree2);
-
-	for (parents[0] = NULL, i = 1; i < 256; i++)
-		parents[i] = (GtkTreeIter *) g_malloc(sizeof(GtkTreeIter));
-
-	tree1 = gtk_tree_store_new(COL_NUMBER,
-				   G_TYPE_STRING, G_TYPE_STRING,
-				   G_TYPE_STRING, G_TYPE_STRING,
-				   G_TYPE_STRING, G_TYPE_STRING,
-				   G_TYPE_POINTER, GDK_TYPE_COLOR,
-				   G_TYPE_BOOLEAN, GDK_TYPE_PIXBUF,
-				   G_TYPE_BOOLEAN, G_TYPE_BOOLEAN,
-				   G_TYPE_BOOLEAN, G_TYPE_BOOLEAN,
-				   G_TYPE_BOOLEAN);
-	model1 = GTK_TREE_MODEL(tree1);
-}
-
-static void init_left_tree(void)
-{
-	GtkTreeView *view = GTK_TREE_VIEW(tree1_w);
-	GtkCellRenderer *renderer;
-	GtkTreeSelection *sel;
-	GtkTreeViewColumn *column;
-
-	gtk_tree_view_set_model(view, model1);
-	gtk_tree_view_set_headers_visible(view, TRUE);
-	gtk_tree_view_set_rules_hint(view, TRUE);
-
-	column = gtk_tree_view_column_new();
-	gtk_tree_view_append_column(view, column);
-	gtk_tree_view_column_set_title(column, "Options");
-
-	renderer = gtk_cell_renderer_toggle_new();
-	gtk_tree_view_column_pack_start(GTK_TREE_VIEW_COLUMN(column),
-					renderer, FALSE);
-	gtk_tree_view_column_set_attributes(GTK_TREE_VIEW_COLUMN(column),
-					    renderer,
-					    "active", COL_BTNACT,
-					    "inconsistent", COL_BTNINC,
-					    "visible", COL_BTNVIS,
-					    "radio", COL_BTNRAD, NULL);
-	renderer = gtk_cell_renderer_text_new();
-	gtk_tree_view_column_pack_start(GTK_TREE_VIEW_COLUMN(column),
-					renderer, FALSE);
-	gtk_tree_view_column_set_attributes(GTK_TREE_VIEW_COLUMN(column),
-					    renderer,
-					    "text", COL_OPTION,
-					    "foreground-gdk",
-					    COL_COLOR, NULL);
-
-	sel = gtk_tree_view_get_selection(view);
-	gtk_tree_selection_set_mode(sel, GTK_SELECTION_SINGLE);
-	gtk_widget_realize(tree1_w);
-}
-
-static void renderer_edited(GtkCellRendererText * cell,
-			    const gchar * path_string,
-			    const gchar * new_text, gpointer user_data);
-
-static void init_right_tree(void)
-{
-	GtkTreeView *view = GTK_TREE_VIEW(tree2_w);
-	GtkCellRenderer *renderer;
-	GtkTreeSelection *sel;
-	GtkTreeViewColumn *column;
-	gint i;
-
-	gtk_tree_view_set_model(view, model2);
-	gtk_tree_view_set_headers_visible(view, TRUE);
-	gtk_tree_view_set_rules_hint(view, TRUE);
-
-	column = gtk_tree_view_column_new();
-	gtk_tree_view_append_column(view, column);
-	gtk_tree_view_column_set_title(column, "Options");
-
-	renderer = gtk_cell_renderer_pixbuf_new();
-	gtk_tree_view_column_pack_start(GTK_TREE_VIEW_COLUMN(column),
-					renderer, FALSE);
-	gtk_tree_view_column_set_attributes(GTK_TREE_VIEW_COLUMN(column),
-					    renderer,
-					    "pixbuf", COL_PIXBUF,
-					    "visible", COL_PIXVIS, NULL);
-	renderer = gtk_cell_renderer_toggle_new();
-	gtk_tree_view_column_pack_start(GTK_TREE_VIEW_COLUMN(column),
-					renderer, FALSE);
-	gtk_tree_view_column_set_attributes(GTK_TREE_VIEW_COLUMN(column),
-					    renderer,
-					    "active", COL_BTNACT,
-					    "inconsistent", COL_BTNINC,
-					    "visible", COL_BTNVIS,
-					    "radio", COL_BTNRAD, NULL);
-	renderer = gtk_cell_renderer_text_new();
-	gtk_tree_view_column_pack_start(GTK_TREE_VIEW_COLUMN(column),
-					renderer, FALSE);
-	gtk_tree_view_column_set_attributes(GTK_TREE_VIEW_COLUMN(column),
-					    renderer,
-					    "text", COL_OPTION,
-					    "foreground-gdk",
-					    COL_COLOR, NULL);
-
-	renderer = gtk_cell_renderer_text_new();
-	gtk_tree_view_insert_column_with_attributes(view, -1,
-						    "Name", renderer,
-						    "text", COL_NAME,
-						    "foreground-gdk",
-						    COL_COLOR, NULL);
-	renderer = gtk_cell_renderer_text_new();
-	gtk_tree_view_insert_column_with_attributes(view, -1,
-						    "N", renderer,
-						    "text", COL_NO,
-						    "foreground-gdk",
-						    COL_COLOR, NULL);
-	renderer = gtk_cell_renderer_text_new();
-	gtk_tree_view_insert_column_with_attributes(view, -1,
-						    "M", renderer,
-						    "text", COL_MOD,
-						    "foreground-gdk",
-						    COL_COLOR, NULL);
-	renderer = gtk_cell_renderer_text_new();
-	gtk_tree_view_insert_column_with_attributes(view, -1,
-						    "Y", renderer,
-						    "text", COL_YES,
-						    "foreground-gdk",
-						    COL_COLOR, NULL);
-	renderer = gtk_cell_renderer_text_new();
-	gtk_tree_view_insert_column_with_attributes(view, -1,
-						    "Value", renderer,
-						    "text", COL_VALUE,
-						    "editable",
-						    COL_EDIT,
-						    "foreground-gdk",
-						    COL_COLOR, NULL);
-	g_signal_connect(G_OBJECT(renderer), "edited",
-			 G_CALLBACK(renderer_edited), NULL);
-
-	column = gtk_tree_view_get_column(view, COL_NAME);
-	gtk_tree_view_column_set_visible(column, show_name);
-	column = gtk_tree_view_get_column(view, COL_NO);
-	gtk_tree_view_column_set_visible(column, show_range);
-	column = gtk_tree_view_get_column(view, COL_MOD);
-	gtk_tree_view_column_set_visible(column, show_range);
-	column = gtk_tree_view_get_column(view, COL_YES);
-	gtk_tree_view_column_set_visible(column, show_range);
-	column = gtk_tree_view_get_column(view, COL_VALUE);
-	gtk_tree_view_column_set_visible(column, show_value);
-
-	if (resizeable) {
-		for (i = 0; i < COL_VALUE; i++) {
-			column = gtk_tree_view_get_column(view, i);
-			gtk_tree_view_column_set_resizable(column, TRUE);
-		}
-	}
-
-	sel = gtk_tree_view_get_selection(view);
-	gtk_tree_selection_set_mode(sel, GTK_SELECTION_SINGLE);
-}
-
-
-/* Utility Functions */
-
-
-static void text_insert_help(struct menu *menu)
-{
-	GtkTextBuffer *buffer;
-	GtkTextIter start, end;
-	const char *prompt = menu_get_prompt(menu);
-	struct gstr help = str_new();
-
-	menu_get_ext_help(menu, &help);
-
-	buffer = gtk_text_view_get_buffer(GTK_TEXT_VIEW(text_w));
-	gtk_text_buffer_get_bounds(buffer, &start, &end);
-	gtk_text_buffer_delete(buffer, &start, &end);
-	gtk_text_view_set_left_margin(GTK_TEXT_VIEW(text_w), 15);
-
-	gtk_text_buffer_get_end_iter(buffer, &end);
-	gtk_text_buffer_insert_with_tags(buffer, &end, prompt, -1, tag1,
-					 NULL);
-	gtk_text_buffer_insert_at_cursor(buffer, "\n\n", 2);
-	gtk_text_buffer_get_end_iter(buffer, &end);
-	gtk_text_buffer_insert_with_tags(buffer, &end, str_get(&help), -1, tag2,
-					 NULL);
-	str_free(&help);
-}
-
-
-static void text_insert_msg(const char *title, const char *message)
-{
-	GtkTextBuffer *buffer;
-	GtkTextIter start, end;
-	const char *msg = message;
-
-	buffer = gtk_text_view_get_buffer(GTK_TEXT_VIEW(text_w));
-	gtk_text_buffer_get_bounds(buffer, &start, &end);
-	gtk_text_buffer_delete(buffer, &start, &end);
-	gtk_text_view_set_left_margin(GTK_TEXT_VIEW(text_w), 15);
-
-	gtk_text_buffer_get_end_iter(buffer, &end);
-	gtk_text_buffer_insert_with_tags(buffer, &end, title, -1, tag1,
-					 NULL);
-	gtk_text_buffer_insert_at_cursor(buffer, "\n\n", 2);
-	gtk_text_buffer_get_end_iter(buffer, &end);
-	gtk_text_buffer_insert_with_tags(buffer, &end, msg, -1, tag2,
-					 NULL);
-}
-
-
-/* Main Windows Callbacks */
-
-void on_save_activate(GtkMenuItem * menuitem, gpointer user_data);
-gboolean on_window1_delete_event(GtkWidget * widget, GdkEvent * event,
-				 gpointer user_data)
-{
-	GtkWidget *dialog, *label;
-	gint result;
-
-	if (!conf_get_changed())
-		return FALSE;
-
-	dialog = gtk_dialog_new_with_buttons("Warning !",
-					     GTK_WINDOW(main_wnd),
-					     (GtkDialogFlags)
-					     (GTK_DIALOG_MODAL |
-					      GTK_DIALOG_DESTROY_WITH_PARENT),
-					     GTK_STOCK_OK,
-					     GTK_RESPONSE_YES,
-					     GTK_STOCK_NO,
-					     GTK_RESPONSE_NO,
-					     GTK_STOCK_CANCEL,
-					     GTK_RESPONSE_CANCEL, NULL);
-	gtk_dialog_set_default_response(GTK_DIALOG(dialog),
-					GTK_RESPONSE_CANCEL);
-
-	label = gtk_label_new("\nSave configuration ?\n");
-	gtk_container_add(GTK_CONTAINER(GTK_DIALOG(dialog)->vbox), label);
-	gtk_widget_show(label);
-
-	result = gtk_dialog_run(GTK_DIALOG(dialog));
-	switch (result) {
-	case GTK_RESPONSE_YES:
-		on_save_activate(NULL, NULL);
-		return FALSE;
-	case GTK_RESPONSE_NO:
-		return FALSE;
-	case GTK_RESPONSE_CANCEL:
-	case GTK_RESPONSE_DELETE_EVENT:
-	default:
-		gtk_widget_destroy(dialog);
-		return TRUE;
-	}
-
-	return FALSE;
-}
-
-
-void on_window1_destroy(GtkObject * object, gpointer user_data)
-{
-	gtk_main_quit();
-}
-
-
-void
-on_window1_size_request(GtkWidget * widget,
-			GtkRequisition * requisition, gpointer user_data)
-{
-	static gint old_h;
-	gint w, h;
-
-	if (widget->window == NULL)
-		gtk_window_get_default_size(GTK_WINDOW(main_wnd), &w, &h);
-	else
-		gdk_window_get_size(widget->window, &w, &h);
-
-	if (h == old_h)
-		return;
-	old_h = h;
-
-	gtk_paned_set_position(GTK_PANED(vpaned), 2 * h / 3);
-}
-
-
-/* Menu & Toolbar Callbacks */
-
-
-static void
-load_filename(GtkFileSelection * file_selector, gpointer user_data)
-{
-	const gchar *fn;
-
-	fn = gtk_file_selection_get_filename(GTK_FILE_SELECTION
-					     (user_data));
-
-	if (conf_read(fn))
-		text_insert_msg("Error", "Unable to load configuration !");
-	else
-		display_tree(&rootmenu);
-}
-
-void on_load1_activate(GtkMenuItem * menuitem, gpointer user_data)
-{
-	GtkWidget *fs;
-
-	fs = gtk_file_selection_new("Load file...");
-	g_signal_connect(GTK_OBJECT(GTK_FILE_SELECTION(fs)->ok_button),
-			 "clicked",
-			 G_CALLBACK(load_filename), (gpointer) fs);
-	g_signal_connect_swapped(GTK_OBJECT
-				 (GTK_FILE_SELECTION(fs)->ok_button),
-				 "clicked", G_CALLBACK(gtk_widget_destroy),
-				 (gpointer) fs);
-	g_signal_connect_swapped(GTK_OBJECT
-				 (GTK_FILE_SELECTION(fs)->cancel_button),
-				 "clicked", G_CALLBACK(gtk_widget_destroy),
-				 (gpointer) fs);
-	gtk_widget_show(fs);
-}
-
-
-void on_save_activate(GtkMenuItem * menuitem, gpointer user_data)
-{
-	if (conf_write(NULL))
-		text_insert_msg("Error", "Unable to save configuration !");
-	conf_write_autoconf(0);
-}
-
-
-static void
-store_filename(GtkFileSelection * file_selector, gpointer user_data)
-{
-	const gchar *fn;
-
-	fn = gtk_file_selection_get_filename(GTK_FILE_SELECTION
-					     (user_data));
-
-	if (conf_write(fn))
-		text_insert_msg("Error", "Unable to save configuration !");
-
-	gtk_widget_destroy(GTK_WIDGET(user_data));
-}
-
-void on_save_as1_activate(GtkMenuItem * menuitem, gpointer user_data)
-{
-	GtkWidget *fs;
-
-	fs = gtk_file_selection_new("Save file as...");
-	g_signal_connect(GTK_OBJECT(GTK_FILE_SELECTION(fs)->ok_button),
-			 "clicked",
-			 G_CALLBACK(store_filename), (gpointer) fs);
-	g_signal_connect_swapped(GTK_OBJECT
-				 (GTK_FILE_SELECTION(fs)->ok_button),
-				 "clicked", G_CALLBACK(gtk_widget_destroy),
-				 (gpointer) fs);
-	g_signal_connect_swapped(GTK_OBJECT
-				 (GTK_FILE_SELECTION(fs)->cancel_button),
-				 "clicked", G_CALLBACK(gtk_widget_destroy),
-				 (gpointer) fs);
-	gtk_widget_show(fs);
-}
-
-
-void on_quit1_activate(GtkMenuItem * menuitem, gpointer user_data)
-{
-	if (!on_window1_delete_event(NULL, NULL, NULL))
-		gtk_widget_destroy(GTK_WIDGET(main_wnd));
-}
-
-
-void on_show_name1_activate(GtkMenuItem * menuitem, gpointer user_data)
-{
-	GtkTreeViewColumn *col;
-
-	show_name = GTK_CHECK_MENU_ITEM(menuitem)->active;
-	col = gtk_tree_view_get_column(GTK_TREE_VIEW(tree2_w), COL_NAME);
-	if (col)
-		gtk_tree_view_column_set_visible(col, show_name);
-}
-
-
-void on_show_range1_activate(GtkMenuItem * menuitem, gpointer user_data)
-{
-	GtkTreeViewColumn *col;
-
-	show_range = GTK_CHECK_MENU_ITEM(menuitem)->active;
-	col = gtk_tree_view_get_column(GTK_TREE_VIEW(tree2_w), COL_NO);
-	if (col)
-		gtk_tree_view_column_set_visible(col, show_range);
-	col = gtk_tree_view_get_column(GTK_TREE_VIEW(tree2_w), COL_MOD);
-	if (col)
-		gtk_tree_view_column_set_visible(col, show_range);
-	col = gtk_tree_view_get_column(GTK_TREE_VIEW(tree2_w), COL_YES);
-	if (col)
-		gtk_tree_view_column_set_visible(col, show_range);
-
-}
-
-
-void on_show_data1_activate(GtkMenuItem * menuitem, gpointer user_data)
-{
-	GtkTreeViewColumn *col;
-
-	show_value = GTK_CHECK_MENU_ITEM(menuitem)->active;
-	col = gtk_tree_view_get_column(GTK_TREE_VIEW(tree2_w), COL_VALUE);
-	if (col)
-		gtk_tree_view_column_set_visible(col, show_value);
-}
-
-
-void
-on_set_option_mode1_activate(GtkMenuItem *menuitem, gpointer user_data)
-{
-	opt_mode = OPT_NORMAL;
-	gtk_tree_store_clear(tree2);
-	display_tree(&rootmenu);	/* instead of update_tree to speed-up */
-}
-
-
-void
-on_set_option_mode2_activate(GtkMenuItem *menuitem, gpointer user_data)
-{
-	opt_mode = OPT_ALL;
-	gtk_tree_store_clear(tree2);
-	display_tree(&rootmenu);	/* instead of update_tree to speed-up */
-}
-
-
-void
-on_set_option_mode3_activate(GtkMenuItem *menuitem, gpointer user_data)
-{
-	opt_mode = OPT_PROMPT;
-	gtk_tree_store_clear(tree2);
-	display_tree(&rootmenu);	/* instead of update_tree to speed-up */
-}
-
-
-void on_introduction1_activate(GtkMenuItem * menuitem, gpointer user_data)
-{
-	GtkWidget *dialog;
-	const gchar *intro_text =
-	    "Welcome to gkc, the GTK+ graphical configuration tool\n"
-	    "For each option, a blank box indicates the feature is disabled, a\n"
-	    "check indicates it is enabled, and a dot indicates that it is to\n"
-	    "be compiled as a module.  Clicking on the box will cycle through the three states.\n"
-	    "\n"
-	    "If you do not see an option (e.g., a device driver) that you\n"
-	    "believe should be present, try turning on Show All Options\n"
-	    "under the Options menu.\n"
-	    "Although there is no cross reference yet to help you figure out\n"
-	    "what other options must be enabled to support the option you\n"
-	    "are interested in, you can still view the help of a grayed-out\n"
-	    "option.\n"
-	    "\n"
-	    "Toggling Show Debug Info under the Options menu will show \n"
-	    "the dependencies, which you can then match by examining other options.";
-
-	dialog = gtk_message_dialog_new(GTK_WINDOW(main_wnd),
-					GTK_DIALOG_DESTROY_WITH_PARENT,
-					GTK_MESSAGE_INFO,
-					GTK_BUTTONS_CLOSE, "%s", intro_text);
-	g_signal_connect_swapped(GTK_OBJECT(dialog), "response",
-				 G_CALLBACK(gtk_widget_destroy),
-				 GTK_OBJECT(dialog));
-	gtk_widget_show_all(dialog);
-}
-
-
-void on_about1_activate(GtkMenuItem * menuitem, gpointer user_data)
-{
-	GtkWidget *dialog;
-	const gchar *about_text =
-	    "gkc is copyright (c) 2002 Romain Lievin <roms@lpg.ticalc.org>.\n"
-	      "Based on the source code from Roman Zippel.\n";
-
-	dialog = gtk_message_dialog_new(GTK_WINDOW(main_wnd),
-					GTK_DIALOG_DESTROY_WITH_PARENT,
-					GTK_MESSAGE_INFO,
-					GTK_BUTTONS_CLOSE, "%s", about_text);
-	g_signal_connect_swapped(GTK_OBJECT(dialog), "response",
-				 G_CALLBACK(gtk_widget_destroy),
-				 GTK_OBJECT(dialog));
-	gtk_widget_show_all(dialog);
-}
-
-
-void on_license1_activate(GtkMenuItem * menuitem, gpointer user_data)
-{
-	GtkWidget *dialog;
-	const gchar *license_text =
-	    "gkc is released under the terms of the GNU GPL v2.\n"
-	      "For more information, please see the source code or\n"
-	      "visit http://www.fsf.org/licenses/licenses.html\n";
-
-	dialog = gtk_message_dialog_new(GTK_WINDOW(main_wnd),
-					GTK_DIALOG_DESTROY_WITH_PARENT,
-					GTK_MESSAGE_INFO,
-					GTK_BUTTONS_CLOSE, "%s", license_text);
-	g_signal_connect_swapped(GTK_OBJECT(dialog), "response",
-				 G_CALLBACK(gtk_widget_destroy),
-				 GTK_OBJECT(dialog));
-	gtk_widget_show_all(dialog);
-}
-
-
-void on_back_clicked(GtkButton * button, gpointer user_data)
-{
-	enum prop_type ptype;
-
-	current = current->parent;
-	ptype = current->prompt ? current->prompt->type : P_UNKNOWN;
-	if (ptype != P_MENU)
-		current = current->parent;
-	display_tree_part();
-
-	if (current == &rootmenu)
-		gtk_widget_set_sensitive(back_btn, FALSE);
-}
-
-
-void on_load_clicked(GtkButton * button, gpointer user_data)
-{
-	on_load1_activate(NULL, user_data);
-}
-
-
-void on_single_clicked(GtkButton * button, gpointer user_data)
-{
-	view_mode = SINGLE_VIEW;
-	gtk_widget_hide(tree1_w);
-	current = &rootmenu;
-	display_tree_part();
-}
-
-
-void on_split_clicked(GtkButton * button, gpointer user_data)
-{
-	gint w, h;
-	view_mode = SPLIT_VIEW;
-	gtk_widget_show(tree1_w);
-	gtk_window_get_default_size(GTK_WINDOW(main_wnd), &w, &h);
-	gtk_paned_set_position(GTK_PANED(hpaned), w / 2);
-	if (tree2)
-		gtk_tree_store_clear(tree2);
-	display_list();
-
-	/* Disable back btn, like in full mode. */
-	gtk_widget_set_sensitive(back_btn, FALSE);
-}
-
-
-void on_full_clicked(GtkButton * button, gpointer user_data)
-{
-	view_mode = FULL_VIEW;
-	gtk_widget_hide(tree1_w);
-	if (tree2)
-		gtk_tree_store_clear(tree2);
-	display_tree(&rootmenu);
-	gtk_widget_set_sensitive(back_btn, FALSE);
-}
-
-
-void on_collapse_clicked(GtkButton * button, gpointer user_data)
-{
-	gtk_tree_view_collapse_all(GTK_TREE_VIEW(tree2_w));
-}
-
-
-void on_expand_clicked(GtkButton * button, gpointer user_data)
-{
-	gtk_tree_view_expand_all(GTK_TREE_VIEW(tree2_w));
-}
-
-
-/* CTree Callbacks */
-
-/* Change hex/int/string value in the cell */
-static void renderer_edited(GtkCellRendererText * cell,
-			    const gchar * path_string,
-			    const gchar * new_text, gpointer user_data)
-{
-	GtkTreePath *path = gtk_tree_path_new_from_string(path_string);
-	GtkTreeIter iter;
-	const char *old_def, *new_def;
-	struct menu *menu;
-	struct symbol *sym;
-
-	if (!gtk_tree_model_get_iter(model2, &iter, path))
-		return;
-
-	gtk_tree_model_get(model2, &iter, COL_MENU, &menu, -1);
-	sym = menu->sym;
-
-	gtk_tree_model_get(model2, &iter, COL_VALUE, &old_def, -1);
-	new_def = new_text;
-
-	sym_set_string_value(sym, new_def);
-
-	update_tree(&rootmenu, NULL);
-
-	gtk_tree_path_free(path);
-}
-
-/* Change the value of a symbol and update the tree */
-static void change_sym_value(struct menu *menu, gint col)
-{
-	struct symbol *sym = menu->sym;
-	tristate newval;
-
-	if (!sym)
-		return;
-
-	if (col == COL_NO)
-		newval = no;
-	else if (col == COL_MOD)
-		newval = mod;
-	else if (col == COL_YES)
-		newval = yes;
-	else
-		return;
-
-	switch (sym_get_type(sym)) {
-	case S_BOOLEAN:
-	case S_TRISTATE:
-		if (!sym_tristate_within_range(sym, newval))
-			newval = yes;
-		sym_set_tristate_value(sym, newval);
-		if (view_mode == FULL_VIEW)
-			update_tree(&rootmenu, NULL);
-		else if (view_mode == SPLIT_VIEW) {
-			update_tree(browsed, NULL);
-			display_list();
-		}
-		else if (view_mode == SINGLE_VIEW)
-			display_tree_part();	//fixme: keep exp/coll
-		break;
-	case S_INT:
-	case S_HEX:
-	case S_STRING:
-	default:
-		break;
-	}
-}
-
-static void toggle_sym_value(struct menu *menu)
-{
-	if (!menu->sym)
-		return;
-
-	sym_toggle_tristate_value(menu->sym);
-	if (view_mode == FULL_VIEW)
-		update_tree(&rootmenu, NULL);
-	else if (view_mode == SPLIT_VIEW) {
-		update_tree(browsed, NULL);
-		display_list();
-	}
-	else if (view_mode == SINGLE_VIEW)
-		display_tree_part();	//fixme: keep exp/coll
-}
-
-static gint column2index(GtkTreeViewColumn * column)
-{
-	gint i;
-
-	for (i = 0; i < COL_NUMBER; i++) {
-		GtkTreeViewColumn *col;
-
-		col = gtk_tree_view_get_column(GTK_TREE_VIEW(tree2_w), i);
-		if (col == column)
-			return i;
-	}
-
-	return -1;
-}
-
-
-/* User click: update choice (full) or goes down (single) */
-gboolean
-on_treeview2_button_press_event(GtkWidget * widget,
-				GdkEventButton * event, gpointer user_data)
-{
-	GtkTreeView *view = GTK_TREE_VIEW(widget);
-	GtkTreePath *path;
-	GtkTreeViewColumn *column;
-	GtkTreeIter iter;
-	struct menu *menu;
-	gint col;
-
-#if GTK_CHECK_VERSION(2,1,4) // bug in ctree with earlier version of GTK
-	gint tx = (gint) event->x;
-	gint ty = (gint) event->y;
-	gint cx, cy;
-
-	gtk_tree_view_get_path_at_pos(view, tx, ty, &path, &column, &cx,
-				      &cy);
-#else
-	gtk_tree_view_get_cursor(view, &path, &column);
-#endif
-	if (path == NULL)
-		return FALSE;
-
-	if (!gtk_tree_model_get_iter(model2, &iter, path))
-		return FALSE;
-	gtk_tree_model_get(model2, &iter, COL_MENU, &menu, -1);
-
-	col = column2index(column);
-	if (event->type == GDK_2BUTTON_PRESS) {
-		enum prop_type ptype;
-		ptype = menu->prompt ? menu->prompt->type : P_UNKNOWN;
-
-		if (ptype == P_MENU && view_mode != FULL_VIEW && col == COL_OPTION) {
-			// goes down into menu
-			current = menu;
-			display_tree_part();
-			gtk_widget_set_sensitive(back_btn, TRUE);
-		} else if (col == COL_OPTION) {
-			toggle_sym_value(menu);
-			gtk_tree_view_expand_row(view, path, TRUE);
-		}
-	} else {
-		if (col == COL_VALUE) {
-			toggle_sym_value(menu);
-			gtk_tree_view_expand_row(view, path, TRUE);
-		} else if (col == COL_NO || col == COL_MOD
-			   || col == COL_YES) {
-			change_sym_value(menu, col);
-			gtk_tree_view_expand_row(view, path, TRUE);
-		}
-	}
-
-	return FALSE;
-}
-
-/* Key pressed: update choice */
-gboolean
-on_treeview2_key_press_event(GtkWidget * widget,
-			     GdkEventKey * event, gpointer user_data)
-{
-	GtkTreeView *view = GTK_TREE_VIEW(widget);
-	GtkTreePath *path;
-	GtkTreeViewColumn *column;
-	GtkTreeIter iter;
-	struct menu *menu;
-	gint col;
-
-	gtk_tree_view_get_cursor(view, &path, &column);
-	if (path == NULL)
-		return FALSE;
-
-	if (event->keyval == GDK_space) {
-		if (gtk_tree_view_row_expanded(view, path))
-			gtk_tree_view_collapse_row(view, path);
-		else
-			gtk_tree_view_expand_row(view, path, FALSE);
-		return TRUE;
-	}
-	if (event->keyval == GDK_KP_Enter) {
-	}
-	if (widget == tree1_w)
-		return FALSE;
-
-	gtk_tree_model_get_iter(model2, &iter, path);
-	gtk_tree_model_get(model2, &iter, COL_MENU, &menu, -1);
-
-	if (!strcasecmp(event->string, "n"))
-		col = COL_NO;
-	else if (!strcasecmp(event->string, "m"))
-		col = COL_MOD;
-	else if (!strcasecmp(event->string, "y"))
-		col = COL_YES;
-	else
-		col = -1;
-	change_sym_value(menu, col);
-
-	return FALSE;
-}
-
-
-/* Row selection changed: update help */
-void
-on_treeview2_cursor_changed(GtkTreeView * treeview, gpointer user_data)
-{
-	GtkTreeSelection *selection;
-	GtkTreeIter iter;
-	struct menu *menu;
-
-	selection = gtk_tree_view_get_selection(treeview);
-	if (gtk_tree_selection_get_selected(selection, &model2, &iter)) {
-		gtk_tree_model_get(model2, &iter, COL_MENU, &menu, -1);
-		text_insert_help(menu);
-	}
-}
-
-
-/* User click: display sub-tree in the right frame. */
-gboolean
-on_treeview1_button_press_event(GtkWidget * widget,
-				GdkEventButton * event, gpointer user_data)
-{
-	GtkTreeView *view = GTK_TREE_VIEW(widget);
-	GtkTreePath *path;
-	GtkTreeViewColumn *column;
-	GtkTreeIter iter;
-	struct menu *menu;
-
-	gint tx = (gint) event->x;
-	gint ty = (gint) event->y;
-	gint cx, cy;
-
-	gtk_tree_view_get_path_at_pos(view, tx, ty, &path, &column, &cx,
-				      &cy);
-	if (path == NULL)
-		return FALSE;
-
-	gtk_tree_model_get_iter(model1, &iter, path);
-	gtk_tree_model_get(model1, &iter, COL_MENU, &menu, -1);
-
-	if (event->type == GDK_2BUTTON_PRESS) {
-		toggle_sym_value(menu);
-		current = menu;
-		display_tree_part();
-	} else {
-		browsed = menu;
-		display_tree_part();
-	}
-
-	gtk_widget_realize(tree2_w);
-	gtk_tree_view_set_cursor(view, path, NULL, FALSE);
-	gtk_widget_grab_focus(tree2_w);
-
-	return FALSE;
-}
-
-
-/* Fill a row of strings */
-static gchar **fill_row(struct menu *menu)
-{
-	static gchar *row[COL_NUMBER];
-	struct symbol *sym = menu->sym;
-	const char *def;
-	int stype;
-	tristate val;
-	enum prop_type ptype;
-	int i;
-
-	for (i = COL_OPTION; i <= COL_COLOR; i++)
-		g_free(row[i]);
-	bzero(row, sizeof(row));
-
-	row[COL_OPTION] =
-	    g_strdup_printf("%s %s", menu_get_prompt(menu),
-			    sym && !sym_has_value(sym) ? "(NEW)" : "");
-
-	if (opt_mode == OPT_ALL && !menu_is_visible(menu))
-		row[COL_COLOR] = g_strdup("DarkGray");
-	else if (opt_mode == OPT_PROMPT &&
-			menu_has_prompt(menu) && !menu_is_visible(menu))
-		row[COL_COLOR] = g_strdup("DarkGray");
-	else
-		row[COL_COLOR] = g_strdup("Black");
-
-	ptype = menu->prompt ? menu->prompt->type : P_UNKNOWN;
-	switch (ptype) {
-	case P_MENU:
-		row[COL_PIXBUF] = (gchar *) xpm_menu;
-		if (view_mode == SINGLE_VIEW)
-			row[COL_PIXVIS] = GINT_TO_POINTER(TRUE);
-		row[COL_BTNVIS] = GINT_TO_POINTER(FALSE);
-		break;
-	case P_COMMENT:
-		row[COL_PIXBUF] = (gchar *) xpm_void;
-		row[COL_PIXVIS] = GINT_TO_POINTER(FALSE);
-		row[COL_BTNVIS] = GINT_TO_POINTER(FALSE);
-		break;
-	default:
-		row[COL_PIXBUF] = (gchar *) xpm_void;
-		row[COL_PIXVIS] = GINT_TO_POINTER(FALSE);
-		row[COL_BTNVIS] = GINT_TO_POINTER(TRUE);
-		break;
-	}
-
-	if (!sym)
-		return row;
-	row[COL_NAME] = g_strdup(sym->name);
-
-	sym_calc_value(sym);
-	sym->flags &= ~SYMBOL_CHANGED;
-
-	if (sym_is_choice(sym)) {	// parse childs for getting final value
-		struct menu *child;
-		struct symbol *def_sym = sym_get_choice_value(sym);
-		struct menu *def_menu = NULL;
-
-		row[COL_BTNVIS] = GINT_TO_POINTER(FALSE);
-
-		for (child = menu->list; child; child = child->next) {
-			if (menu_is_visible(child)
-			    && child->sym == def_sym)
-				def_menu = child;
-		}
-
-		if (def_menu)
-			row[COL_VALUE] =
-			    g_strdup(menu_get_prompt(def_menu));
-	}
-	if (sym->flags & SYMBOL_CHOICEVAL)
-		row[COL_BTNRAD] = GINT_TO_POINTER(TRUE);
-
-	stype = sym_get_type(sym);
-	switch (stype) {
-	case S_BOOLEAN:
-		if (GPOINTER_TO_INT(row[COL_PIXVIS]) == FALSE)
-			row[COL_BTNVIS] = GINT_TO_POINTER(TRUE);
-		if (sym_is_choice(sym))
-			break;
-		/* fall through */
-	case S_TRISTATE:
-		val = sym_get_tristate_value(sym);
-		switch (val) {
-		case no:
-			row[COL_NO] = g_strdup("N");
-			row[COL_VALUE] = g_strdup("N");
-			row[COL_BTNACT] = GINT_TO_POINTER(FALSE);
-			row[COL_BTNINC] = GINT_TO_POINTER(FALSE);
-			break;
-		case mod:
-			row[COL_MOD] = g_strdup("M");
-			row[COL_VALUE] = g_strdup("M");
-			row[COL_BTNINC] = GINT_TO_POINTER(TRUE);
-			break;
-		case yes:
-			row[COL_YES] = g_strdup("Y");
-			row[COL_VALUE] = g_strdup("Y");
-			row[COL_BTNACT] = GINT_TO_POINTER(TRUE);
-			row[COL_BTNINC] = GINT_TO_POINTER(FALSE);
-			break;
-		}
-
-		if (val != no && sym_tristate_within_range(sym, no))
-			row[COL_NO] = g_strdup("_");
-		if (val != mod && sym_tristate_within_range(sym, mod))
-			row[COL_MOD] = g_strdup("_");
-		if (val != yes && sym_tristate_within_range(sym, yes))
-			row[COL_YES] = g_strdup("_");
-		break;
-	case S_INT:
-	case S_HEX:
-	case S_STRING:
-		def = sym_get_string_value(sym);
-		row[COL_VALUE] = g_strdup(def);
-		row[COL_EDIT] = GINT_TO_POINTER(TRUE);
-		row[COL_BTNVIS] = GINT_TO_POINTER(FALSE);
-		break;
-	}
-
-	return row;
-}
-
-
-/* Set the node content with a row of strings */
-static void set_node(GtkTreeIter * node, struct menu *menu, gchar ** row)
-{
-	GdkColor color;
-	gboolean success;
-	GdkPixbuf *pix;
-
-	pix = gdk_pixbuf_new_from_xpm_data((const char **)
-					   row[COL_PIXBUF]);
-
-	gdk_color_parse(row[COL_COLOR], &color);
-	gdk_colormap_alloc_colors(gdk_colormap_get_system(), &color, 1,
-				  FALSE, FALSE, &success);
-
-	gtk_tree_store_set(tree, node,
-			   COL_OPTION, row[COL_OPTION],
-			   COL_NAME, row[COL_NAME],
-			   COL_NO, row[COL_NO],
-			   COL_MOD, row[COL_MOD],
-			   COL_YES, row[COL_YES],
-			   COL_VALUE, row[COL_VALUE],
-			   COL_MENU, (gpointer) menu,
-			   COL_COLOR, &color,
-			   COL_EDIT, GPOINTER_TO_INT(row[COL_EDIT]),
-			   COL_PIXBUF, pix,
-			   COL_PIXVIS, GPOINTER_TO_INT(row[COL_PIXVIS]),
-			   COL_BTNVIS, GPOINTER_TO_INT(row[COL_BTNVIS]),
-			   COL_BTNACT, GPOINTER_TO_INT(row[COL_BTNACT]),
-			   COL_BTNINC, GPOINTER_TO_INT(row[COL_BTNINC]),
-			   COL_BTNRAD, GPOINTER_TO_INT(row[COL_BTNRAD]),
-			   -1);
-
-	g_object_unref(pix);
-}
-
-
-/* Add a node to the tree */
-static void place_node(struct menu *menu, char **row)
-{
-	GtkTreeIter *parent = parents[indent - 1];
-	GtkTreeIter *node = parents[indent];
-
-	gtk_tree_store_append(tree, node, parent);
-	set_node(node, menu, row);
-}
-
-
-/* Find a node in the GTK+ tree */
-static GtkTreeIter found;
-
-/*
- * Find a menu in the GtkTree starting at parent.
- */
-static GtkTreeIter *gtktree_iter_find_node(GtkTreeIter *parent,
-					   struct menu *tofind)
-{
-	GtkTreeIter iter;
-	GtkTreeIter *child = &iter;
-	gboolean valid;
-	GtkTreeIter *ret;
-
-	valid = gtk_tree_model_iter_children(model2, child, parent);
-	while (valid) {
-		struct menu *menu;
-
-		gtk_tree_model_get(model2, child, 6, &menu, -1);
-
-		if (menu == tofind) {
-			memcpy(&found, child, sizeof(GtkTreeIter));
-			return &found;
-		}
-
-		ret = gtktree_iter_find_node(child, tofind);
-		if (ret)
-			return ret;
-
-		valid = gtk_tree_model_iter_next(model2, child);
-	}
-
-	return NULL;
-}
-
-
-/*
- * Update the tree by adding/removing entries
- * Does not change other nodes
- */
-static void update_tree(struct menu *src, GtkTreeIter * dst)
-{
-	struct menu *child1;
-	GtkTreeIter iter, tmp;
-	GtkTreeIter *child2 = &iter;
-	gboolean valid;
-	GtkTreeIter *sibling;
-	struct symbol *sym;
-	struct menu *menu1, *menu2;
-
-	if (src == &rootmenu)
-		indent = 1;
-
-	valid = gtk_tree_model_iter_children(model2, child2, dst);
-	for (child1 = src->list; child1; child1 = child1->next) {
-
-		sym = child1->sym;
-
-	      reparse:
-		menu1 = child1;
-		if (valid)
-			gtk_tree_model_get(model2, child2, COL_MENU,
-					   &menu2, -1);
-		else
-			menu2 = NULL;	// force adding of a first child
-
-#ifdef DEBUG
-		printf("%*c%s | %s\n", indent, ' ',
-		       menu1 ? menu_get_prompt(menu1) : "nil",
-		       menu2 ? menu_get_prompt(menu2) : "nil");
-#endif
-
-		if ((opt_mode == OPT_NORMAL && !menu_is_visible(child1)) ||
-		    (opt_mode == OPT_PROMPT && !menu_has_prompt(child1)) ||
-		    (opt_mode == OPT_ALL    && !menu_get_prompt(child1))) {
-
-			/* remove node */
-			if (gtktree_iter_find_node(dst, menu1) != NULL) {
-				memcpy(&tmp, child2, sizeof(GtkTreeIter));
-				valid = gtk_tree_model_iter_next(model2,
-								 child2);
-				gtk_tree_store_remove(tree2, &tmp);
-				if (!valid)
-					return;		/* next parent */
-				else
-					goto reparse;	/* next child */
-			} else
-				continue;
-		}
-
-		if (menu1 != menu2) {
-			if (gtktree_iter_find_node(dst, menu1) == NULL) {	// add node
-				if (!valid && !menu2)
-					sibling = NULL;
-				else
-					sibling = child2;
-				gtk_tree_store_insert_before(tree2,
-							     child2,
-							     dst, sibling);
-				set_node(child2, menu1, fill_row(menu1));
-				if (menu2 == NULL)
-					valid = TRUE;
-			} else {	// remove node
-				memcpy(&tmp, child2, sizeof(GtkTreeIter));
-				valid = gtk_tree_model_iter_next(model2,
-								 child2);
-				gtk_tree_store_remove(tree2, &tmp);
-				if (!valid)
-					return;	// next parent
-				else
-					goto reparse;	// next child
-			}
-		} else if (sym && (sym->flags & SYMBOL_CHANGED)) {
-			set_node(child2, menu1, fill_row(menu1));
-		}
-
-		indent++;
-		update_tree(child1, child2);
-		indent--;
-
-		valid = gtk_tree_model_iter_next(model2, child2);
-	}
-}
-
-
-/* Display the whole tree (single/split/full view) */
-static void display_tree(struct menu *menu)
-{
-	struct symbol *sym;
-	struct property *prop;
-	struct menu *child;
-	enum prop_type ptype;
-
-	if (menu == &rootmenu) {
-		indent = 1;
-		current = &rootmenu;
-	}
-
-	for (child = menu->list; child; child = child->next) {
-		prop = child->prompt;
-		sym = child->sym;
-		ptype = prop ? prop->type : P_UNKNOWN;
-
-		if (sym)
-			sym->flags &= ~SYMBOL_CHANGED;
-
-		if ((view_mode == SPLIT_VIEW)
-		    && !(child->flags & MENU_ROOT) && (tree == tree1))
-			continue;
-
-		if ((view_mode == SPLIT_VIEW) && (child->flags & MENU_ROOT)
-		    && (tree == tree2))
-			continue;
-
-		if ((opt_mode == OPT_NORMAL && menu_is_visible(child)) ||
-		    (opt_mode == OPT_PROMPT && menu_has_prompt(child)) ||
-		    (opt_mode == OPT_ALL    && menu_get_prompt(child)))
-			place_node(child, fill_row(child));
-#ifdef DEBUG
-		printf("%*c%s: ", indent, ' ', menu_get_prompt(child));
-		printf("%s", child->flags & MENU_ROOT ? "rootmenu | " : "");
-		printf("%s", prop_get_type_name(ptype));
-		printf(" | ");
-		if (sym) {
-			printf("%s", sym_type_name(sym->type));
-			printf(" | ");
-			printf("%s", dbg_sym_flags(sym->flags));
-			printf("\n");
-		} else
-			printf("\n");
-#endif
-		if ((view_mode != FULL_VIEW) && (ptype == P_MENU)
-		    && (tree == tree2))
-			continue;
-/*
-		if (((menu != &rootmenu) && !(menu->flags & MENU_ROOT))
-		    || (view_mode == FULL_VIEW)
-		    || (view_mode == SPLIT_VIEW))*/
-
-		/* Change paned position if the view is not in 'split mode' */
-		if (view_mode == SINGLE_VIEW || view_mode == FULL_VIEW) {
-			gtk_paned_set_position(GTK_PANED(hpaned), 0);
-		}
-
-		if (((view_mode == SINGLE_VIEW) && (menu->flags & MENU_ROOT))
-		    || (view_mode == FULL_VIEW)
-		    || (view_mode == SPLIT_VIEW)) {
-			indent++;
-			display_tree(child);
-			indent--;
-		}
-	}
-}
-
-/* Display a part of the tree starting at current node (single/split view) */
-static void display_tree_part(void)
-{
-	if (tree2)
-		gtk_tree_store_clear(tree2);
-	if (view_mode == SINGLE_VIEW)
-		display_tree(current);
-	else if (view_mode == SPLIT_VIEW)
-		display_tree(browsed);
-	gtk_tree_view_expand_all(GTK_TREE_VIEW(tree2_w));
-}
-
-/* Display the list in the left frame (split view) */
-static void display_list(void)
-{
-	if (tree1)
-		gtk_tree_store_clear(tree1);
-
-	tree = tree1;
-	display_tree(&rootmenu);
-	gtk_tree_view_expand_all(GTK_TREE_VIEW(tree1_w));
-	tree = tree2;
-}
-
-static void fixup_rootmenu(struct menu *menu)
-{
-	struct menu *child;
-	static int menu_cnt = 0;
-
-	menu->flags |= MENU_ROOT;
-	for (child = menu->list; child; child = child->next) {
-		if (child->prompt && child->prompt->type == P_MENU) {
-			menu_cnt++;
-			fixup_rootmenu(child);
-			menu_cnt--;
-		} else if (!menu_cnt)
-			fixup_rootmenu(child);
-	}
-}
-
-
-/* Main */
-int main(int ac, char *av[])
-{
-	const char *name;
-	char *env;
-	gchar *glade_file;
-
-	/* GTK stuffs */
-	gtk_set_locale();
-	gtk_init(&ac, &av);
-	glade_init();
-
-	//add_pixmap_directory (PACKAGE_DATA_DIR "/" PACKAGE "/pixmaps");
-	//add_pixmap_directory (PACKAGE_SOURCE_DIR "/pixmaps");
-
-	/* Determine GUI path */
-	env = getenv(SRCTREE);
-	if (env)
-		glade_file = g_strconcat(env, "/scripts/kconfig/gconf.glade", NULL);
-	else if (av[0][0] == '/')
-		glade_file = g_strconcat(av[0], ".glade", NULL);
-	else
-		glade_file = g_strconcat(g_get_current_dir(), "/", av[0], ".glade", NULL);
-
-	/* Conf stuffs */
-	if (ac > 1 && av[1][0] == '-') {
-		switch (av[1][1]) {
-		case 'a':
-			//showAll = 1;
-			break;
-		case 's':
-			conf_set_message_callback(NULL);
-			break;
-		case 'h':
-		case '?':
-			printf("%s [-s] <config>\n", av[0]);
-			exit(0);
-		}
-		name = av[2];
-	} else
-		name = av[1];
-
-	conf_parse(name);
-	fixup_rootmenu(&rootmenu);
-	conf_read(NULL);
-
-	/* Load the interface and connect signals */
-	init_main_window(glade_file);
-	init_tree_model();
-	init_left_tree();
-	init_right_tree();
-
-	switch (view_mode) {
-	case SINGLE_VIEW:
-		display_tree_part();
-		break;
-	case SPLIT_VIEW:
-		display_list();
-		break;
-	case FULL_VIEW:
-		display_tree(&rootmenu);
-		break;
-	}
-
-	gtk_main();
-
-	return 0;
-}
-
-static void conf_changed(void)
-{
-	bool changed = conf_get_changed();
-	gtk_widget_set_sensitive(save_btn, changed);
-	gtk_widget_set_sensitive(save_menu_item, changed);
-}
diff --git a/util/kconfig/gconf.glade b/util/kconfig/gconf.glade
deleted file mode 100644
index aa483cb327..0000000000
--- a/util/kconfig/gconf.glade
+++ /dev/null
@@ -1,661 +0,0 @@
-<?xml version="1.0" standalone="no"?> <!--*- mode: xml -*-->
-
-<glade-interface>
-
-<widget class="GtkWindow" id="window1">
-  <property name="visible">True</property>
-  <property name="title" translatable="yes">Gtk Kernel Configurator</property>
-  <property name="type">GTK_WINDOW_TOPLEVEL</property>
-  <property name="window_position">GTK_WIN_POS_NONE</property>
-  <property name="modal">False</property>
-  <property name="default_width">640</property>
-  <property name="default_height">480</property>
-  <property name="resizable">True</property>
-  <property name="destroy_with_parent">False</property>
-  <property name="decorated">True</property>
-  <property name="skip_taskbar_hint">False</property>
-  <property name="skip_pager_hint">False</property>
-  <property name="type_hint">GDK_WINDOW_TYPE_HINT_NORMAL</property>
-  <property name="gravity">GDK_GRAVITY_NORTH_WEST</property>
-  <signal name="destroy" handler="on_window1_destroy" object="window1"/>
-  <signal name="size_request" handler="on_window1_size_request" object="vpaned1" last_modification_time="Fri, 11 Jan 2002 16:17:11 GMT"/>
-  <signal name="delete_event" handler="on_window1_delete_event" object="window1" last_modification_time="Sun, 09 Mar 2003 19:42:46 GMT"/>
-
-  <child>
-    <widget class="GtkVBox" id="vbox1">
-      <property name="visible">True</property>
-      <property name="homogeneous">False</property>
-      <property name="spacing">0</property>
-
-      <child>
-	<widget class="GtkMenuBar" id="menubar1">
-	  <property name="visible">True</property>
-
-	  <child>
-	    <widget class="GtkMenuItem" id="file1">
-	      <property name="visible">True</property>
-	      <property name="label" translatable="yes">_File</property>
-	      <property name="use_underline">True</property>
-
-	      <child>
-		<widget class="GtkMenu" id="file1_menu">
-
-		  <child>
-		    <widget class="GtkImageMenuItem" id="load1">
-		      <property name="visible">True</property>
-		      <property name="tooltip" translatable="yes">Load a config file</property>
-		      <property name="label" translatable="yes">_Load</property>
-		      <property name="use_underline">True</property>
-		      <signal name="activate" handler="on_load1_activate"/>
-		      <accelerator key="L" modifiers="GDK_CONTROL_MASK" signal="activate"/>
-
-		      <child internal-child="image">
-			<widget class="GtkImage" id="image39">
-			  <property name="visible">True</property>
-			  <property name="stock">gtk-open</property>
-			  <property name="icon_size">1</property>
-			  <property name="xalign">0.5</property>
-			  <property name="yalign">0.5</property>
-			  <property name="xpad">0</property>
-			  <property name="ypad">0</property>
-			</widget>
-		      </child>
-		    </widget>
-		  </child>
-
-		  <child>
-		    <widget class="GtkImageMenuItem" id="save1">
-		      <property name="visible">True</property>
-		      <property name="tooltip" translatable="yes">Save the config in .config</property>
-		      <property name="label" translatable="yes">_Save</property>
-		      <property name="use_underline">True</property>
-		      <signal name="activate" handler="on_save_activate"/>
-		      <accelerator key="S" modifiers="GDK_CONTROL_MASK" signal="activate"/>
-
-		      <child internal-child="image">
-			<widget class="GtkImage" id="image40">
-			  <property name="visible">True</property>
-			  <property name="stock">gtk-save</property>
-			  <property name="icon_size">1</property>
-			  <property name="xalign">0.5</property>
-			  <property name="yalign">0.5</property>
-			  <property name="xpad">0</property>
-			  <property name="ypad">0</property>
-			</widget>
-		      </child>
-		    </widget>
-		  </child>
-
-		  <child>
-		    <widget class="GtkImageMenuItem" id="save_as1">
-		      <property name="visible">True</property>
-		      <property name="tooltip" translatable="yes">Save the config in a file</property>
-		      <property name="label" translatable="yes">Save _as</property>
-		      <property name="use_underline">True</property>
-		      <signal name="activate" handler="on_save_as1_activate"/>
-
-		      <child internal-child="image">
-			<widget class="GtkImage" id="image41">
-			  <property name="visible">True</property>
-			  <property name="stock">gtk-save-as</property>
-			  <property name="icon_size">1</property>
-			  <property name="xalign">0.5</property>
-			  <property name="yalign">0.5</property>
-			  <property name="xpad">0</property>
-			  <property name="ypad">0</property>
-			</widget>
-		      </child>
-		    </widget>
-		  </child>
-
-		  <child>
-		    <widget class="GtkSeparatorMenuItem" id="separator1">
-		      <property name="visible">True</property>
-		    </widget>
-		  </child>
-
-		  <child>
-		    <widget class="GtkImageMenuItem" id="quit1">
-		      <property name="visible">True</property>
-		      <property name="label" translatable="yes">_Quit</property>
-		      <property name="use_underline">True</property>
-		      <signal name="activate" handler="on_quit1_activate"/>
-		      <accelerator key="Q" modifiers="GDK_CONTROL_MASK" signal="activate"/>
-
-		      <child internal-child="image">
-			<widget class="GtkImage" id="image42">
-			  <property name="visible">True</property>
-			  <property name="stock">gtk-quit</property>
-			  <property name="icon_size">1</property>
-			  <property name="xalign">0.5</property>
-			  <property name="yalign">0.5</property>
-			  <property name="xpad">0</property>
-			  <property name="ypad">0</property>
-			</widget>
-		      </child>
-		    </widget>
-		  </child>
-		</widget>
-	      </child>
-	    </widget>
-	  </child>
-
-	  <child>
-	    <widget class="GtkMenuItem" id="options1">
-	      <property name="visible">True</property>
-	      <property name="label" translatable="yes">_Options</property>
-	      <property name="use_underline">True</property>
-
-	      <child>
-		<widget class="GtkMenu" id="options1_menu">
-
-		  <child>
-		    <widget class="GtkCheckMenuItem" id="show_name1">
-		      <property name="visible">True</property>
-		      <property name="tooltip" translatable="yes">Show name</property>
-		      <property name="label" translatable="yes">Show _name</property>
-		      <property name="use_underline">True</property>
-		      <property name="active">False</property>
-		      <signal name="activate" handler="on_show_name1_activate"/>
-		    </widget>
-		  </child>
-
-		  <child>
-		    <widget class="GtkCheckMenuItem" id="show_range1">
-		      <property name="visible">True</property>
-		      <property name="tooltip" translatable="yes">Show range (Y/M/N)</property>
-		      <property name="label" translatable="yes">Show _range</property>
-		      <property name="use_underline">True</property>
-		      <property name="active">False</property>
-		      <signal name="activate" handler="on_show_range1_activate"/>
-		    </widget>
-		  </child>
-
-		  <child>
-		    <widget class="GtkCheckMenuItem" id="show_data1">
-		      <property name="visible">True</property>
-		      <property name="tooltip" translatable="yes">Show value of the option</property>
-		      <property name="label" translatable="yes">Show _data</property>
-		      <property name="use_underline">True</property>
-		      <property name="active">False</property>
-		      <signal name="activate" handler="on_show_data1_activate"/>
-		    </widget>
-		  </child>
-
-		  <child>
-		    <widget class="GtkSeparatorMenuItem" id="separator2">
-		      <property name="visible">True</property>
-		    </widget>
-		  </child>
-
-		  <child>
-		    <widget class="GtkRadioMenuItem" id="set_option_mode1">
-		      <property name="visible">True</property>
-		      <property name="tooltip" translatable="yes">Show normal options</property>
-		      <property name="label" translatable="yes">Show normal options</property>
-		      <property name="use_underline">True</property>
-		      <property name="active">True</property>
-		      <signal name="activate" handler="on_set_option_mode1_activate"/>
-		    </widget>
-		  </child>
-
-		  <child>
-		    <widget class="GtkRadioMenuItem" id="set_option_mode2">
-		      <property name="visible">True</property>
-		      <property name="tooltip" translatable="yes">Show all options</property>
-		      <property name="label" translatable="yes">Show all _options</property>
-		      <property name="use_underline">True</property>
-		      <property name="active">False</property>
-		      <property name="group">set_option_mode1</property>
-		      <signal name="activate" handler="on_set_option_mode2_activate"/>
-		    </widget>
-		  </child>
-
-		  <child>
-		    <widget class="GtkRadioMenuItem" id="set_option_mode3">
-		      <property name="visible">True</property>
-		      <property name="tooltip" translatable="yes">Show all options with prompts</property>
-		      <property name="label" translatable="yes">Show all prompt options</property>
-		      <property name="use_underline">True</property>
-		      <property name="active">False</property>
-		      <property name="group">set_option_mode1</property>
-		      <signal name="activate" handler="on_set_option_mode3_activate"/>
-		    </widget>
-		  </child>
-
-		</widget>
-	      </child>
-	    </widget>
-	  </child>
-
-	  <child>
-	    <widget class="GtkMenuItem" id="help1">
-	      <property name="visible">True</property>
-	      <property name="label" translatable="yes">_Help</property>
-	      <property name="use_underline">True</property>
-
-	      <child>
-		<widget class="GtkMenu" id="help1_menu">
-
-		  <child>
-		    <widget class="GtkImageMenuItem" id="introduction1">
-		      <property name="visible">True</property>
-		      <property name="label" translatable="yes">_Introduction</property>
-		      <property name="use_underline">True</property>
-		      <signal name="activate" handler="on_introduction1_activate" last_modification_time="Fri, 15 Nov 2002 20:26:30 GMT"/>
-		      <accelerator key="I" modifiers="GDK_CONTROL_MASK" signal="activate"/>
-
-		      <child internal-child="image">
-			<widget class="GtkImage" id="image43">
-			  <property name="visible">True</property>
-			  <property name="stock">gtk-dialog-question</property>
-			  <property name="icon_size">1</property>
-			  <property name="xalign">0.5</property>
-			  <property name="yalign">0.5</property>
-			  <property name="xpad">0</property>
-			  <property name="ypad">0</property>
-			</widget>
-		      </child>
-		    </widget>
-		  </child>
-
-		  <child>
-		    <widget class="GtkImageMenuItem" id="about1">
-		      <property name="visible">True</property>
-		      <property name="label" translatable="yes">_About</property>
-		      <property name="use_underline">True</property>
-		      <signal name="activate" handler="on_about1_activate" last_modification_time="Fri, 15 Nov 2002 20:26:30 GMT"/>
-		      <accelerator key="A" modifiers="GDK_CONTROL_MASK" signal="activate"/>
-
-		      <child internal-child="image">
-			<widget class="GtkImage" id="image44">
-			  <property name="visible">True</property>
-			  <property name="stock">gtk-properties</property>
-			  <property name="icon_size">1</property>
-			  <property name="xalign">0.5</property>
-			  <property name="yalign">0.5</property>
-			  <property name="xpad">0</property>
-			  <property name="ypad">0</property>
-			</widget>
-		      </child>
-		    </widget>
-		  </child>
-
-		  <child>
-		    <widget class="GtkImageMenuItem" id="license1">
-		      <property name="visible">True</property>
-		      <property name="label" translatable="yes">_License</property>
-		      <property name="use_underline">True</property>
-		      <signal name="activate" handler="on_license1_activate" last_modification_time="Fri, 15 Nov 2002 20:26:30 GMT"/>
-
-		      <child internal-child="image">
-			<widget class="GtkImage" id="image45">
-			  <property name="visible">True</property>
-			  <property name="stock">gtk-justify-fill</property>
-			  <property name="icon_size">1</property>
-			  <property name="xalign">0.5</property>
-			  <property name="yalign">0.5</property>
-			  <property name="xpad">0</property>
-			  <property name="ypad">0</property>
-			</widget>
-		      </child>
-		    </widget>
-		  </child>
-		</widget>
-	      </child>
-	    </widget>
-	  </child>
-	</widget>
-	<packing>
-	  <property name="padding">0</property>
-	  <property name="expand">False</property>
-	  <property name="fill">False</property>
-	</packing>
-      </child>
-
-      <child>
-	<widget class="GtkHandleBox" id="handlebox1">
-	  <property name="visible">True</property>
-	  <property name="shadow_type">GTK_SHADOW_OUT</property>
-	  <property name="handle_position">GTK_POS_LEFT</property>
-	  <property name="snap_edge">GTK_POS_TOP</property>
-
-	  <child>
-	    <widget class="GtkToolbar" id="toolbar1">
-	      <property name="visible">True</property>
-	      <property name="orientation">GTK_ORIENTATION_HORIZONTAL</property>
-	      <property name="toolbar_style">GTK_TOOLBAR_BOTH</property>
-	      <property name="tooltips">True</property>
-	      <property name="show_arrow">True</property>
-
-	      <child>
-		<widget class="GtkToolButton" id="button1">
-		  <property name="visible">True</property>
-		  <property name="tooltip" translatable="yes">Goes up of one level (single view)</property>
-		  <property name="label" translatable="yes">Back</property>
-		  <property name="use_underline">True</property>
-		  <property name="stock_id">gtk-undo</property>
-		  <property name="visible_horizontal">True</property>
-		  <property name="visible_vertical">True</property>
-		  <property name="is_important">False</property>
-		  <signal name="clicked" handler="on_back_clicked"/>
-		</widget>
-		<packing>
-		  <property name="expand">False</property>
-		  <property name="homogeneous">True</property>
-		</packing>
-	      </child>
-
-	      <child>
-		<widget class="GtkToolItem" id="toolitem1">
-		  <property name="visible">True</property>
-		  <property name="visible_horizontal">True</property>
-		  <property name="visible_vertical">True</property>
-		  <property name="is_important">False</property>
-
-		  <child>
-		    <widget class="GtkVSeparator" id="vseparator1">
-		      <property name="visible">True</property>
-		    </widget>
-		  </child>
-		</widget>
-		<packing>
-		  <property name="expand">False</property>
-		  <property name="homogeneous">False</property>
-		</packing>
-	      </child>
-
-	      <child>
-		<widget class="GtkToolButton" id="button2">
-		  <property name="visible">True</property>
-		  <property name="tooltip" translatable="yes">Load a config file</property>
-		  <property name="label" translatable="yes">Load</property>
-		  <property name="use_underline">True</property>
-		  <property name="stock_id">gtk-open</property>
-		  <property name="visible_horizontal">True</property>
-		  <property name="visible_vertical">True</property>
-		  <property name="is_important">False</property>
-		  <signal name="clicked" handler="on_load_clicked"/>
-		</widget>
-		<packing>
-		  <property name="expand">False</property>
-		  <property name="homogeneous">True</property>
-		</packing>
-	      </child>
-
-	      <child>
-		<widget class="GtkToolButton" id="button3">
-		  <property name="visible">True</property>
-		  <property name="tooltip" translatable="yes">Save a config file</property>
-		  <property name="label" translatable="yes">Save</property>
-		  <property name="use_underline">True</property>
-		  <property name="stock_id">gtk-save</property>
-		  <property name="visible_horizontal">True</property>
-		  <property name="visible_vertical">True</property>
-		  <property name="is_important">False</property>
-		  <signal name="clicked" handler="on_save_activate"/>
-		</widget>
-		<packing>
-		  <property name="expand">False</property>
-		  <property name="homogeneous">True</property>
-		</packing>
-	      </child>
-
-	      <child>
-		<widget class="GtkToolItem" id="toolitem2">
-		  <property name="visible">True</property>
-		  <property name="visible_horizontal">True</property>
-		  <property name="visible_vertical">True</property>
-		  <property name="is_important">False</property>
-
-		  <child>
-		    <widget class="GtkVSeparator" id="vseparator2">
-		      <property name="visible">True</property>
-		    </widget>
-		  </child>
-		</widget>
-		<packing>
-		  <property name="expand">False</property>
-		  <property name="homogeneous">False</property>
-		</packing>
-	      </child>
-
-	      <child>
-		<widget class="GtkToolButton" id="button4">
-		  <property name="visible">True</property>
-		  <property name="tooltip" translatable="yes">Single view</property>
-		  <property name="label" translatable="yes">Single</property>
-		  <property name="use_underline">True</property>
-		  <property name="stock_id">gtk-missing-image</property>
-		  <property name="visible_horizontal">True</property>
-		  <property name="visible_vertical">True</property>
-		  <property name="is_important">False</property>
-		  <signal name="clicked" handler="on_single_clicked" last_modification_time="Sun, 12 Jan 2003 14:28:39 GMT"/>
-		</widget>
-		<packing>
-		  <property name="expand">False</property>
-		  <property name="homogeneous">True</property>
-		</packing>
-	      </child>
-
-	      <child>
-		<widget class="GtkToolButton" id="button5">
-		  <property name="visible">True</property>
-		  <property name="tooltip" translatable="yes">Split view</property>
-		  <property name="label" translatable="yes">Split</property>
-		  <property name="use_underline">True</property>
-		  <property name="stock_id">gtk-missing-image</property>
-		  <property name="visible_horizontal">True</property>
-		  <property name="visible_vertical">True</property>
-		  <property name="is_important">False</property>
-		  <signal name="clicked" handler="on_split_clicked" last_modification_time="Sun, 12 Jan 2003 14:28:45 GMT"/>
-		</widget>
-		<packing>
-		  <property name="expand">False</property>
-		  <property name="homogeneous">True</property>
-		</packing>
-	      </child>
-
-	      <child>
-		<widget class="GtkToolButton" id="button6">
-		  <property name="visible">True</property>
-		  <property name="tooltip" translatable="yes">Full view</property>
-		  <property name="label" translatable="yes">Full</property>
-		  <property name="use_underline">True</property>
-		  <property name="stock_id">gtk-missing-image</property>
-		  <property name="visible_horizontal">True</property>
-		  <property name="visible_vertical">True</property>
-		  <property name="is_important">False</property>
-		  <signal name="clicked" handler="on_full_clicked" last_modification_time="Sun, 12 Jan 2003 14:28:50 GMT"/>
-		</widget>
-		<packing>
-		  <property name="expand">False</property>
-		  <property name="homogeneous">True</property>
-		</packing>
-	      </child>
-
-	      <child>
-		<widget class="GtkToolItem" id="toolitem3">
-		  <property name="visible">True</property>
-		  <property name="visible_horizontal">True</property>
-		  <property name="visible_vertical">True</property>
-		  <property name="is_important">False</property>
-
-		  <child>
-		    <widget class="GtkVSeparator" id="vseparator3">
-		      <property name="visible">True</property>
-		    </widget>
-		  </child>
-		</widget>
-		<packing>
-		  <property name="expand">False</property>
-		  <property name="homogeneous">False</property>
-		</packing>
-	      </child>
-
-	      <child>
-		<widget class="GtkToolButton" id="button7">
-		  <property name="visible">True</property>
-		  <property name="tooltip" translatable="yes">Collapse the whole tree in the right frame</property>
-		  <property name="label" translatable="yes">Collapse</property>
-		  <property name="use_underline">True</property>
-		  <property name="stock_id">gtk-remove</property>
-		  <property name="visible_horizontal">True</property>
-		  <property name="visible_vertical">True</property>
-		  <property name="is_important">False</property>
-		  <signal name="clicked" handler="on_collapse_clicked"/>
-		</widget>
-		<packing>
-		  <property name="expand">False</property>
-		  <property name="homogeneous">True</property>
-		</packing>
-	      </child>
-
-	      <child>
-		<widget class="GtkToolButton" id="button8">
-		  <property name="visible">True</property>
-		  <property name="tooltip" translatable="yes">Expand the whole tree in the right frame</property>
-		  <property name="label" translatable="yes">Expand</property>
-		  <property name="use_underline">True</property>
-		  <property name="stock_id">gtk-add</property>
-		  <property name="visible_horizontal">True</property>
-		  <property name="visible_vertical">True</property>
-		  <property name="is_important">False</property>
-		  <signal name="clicked" handler="on_expand_clicked"/>
-		</widget>
-		<packing>
-		  <property name="expand">False</property>
-		  <property name="homogeneous">True</property>
-		</packing>
-	      </child>
-	    </widget>
-	  </child>
-	</widget>
-	<packing>
-	  <property name="padding">0</property>
-	  <property name="expand">False</property>
-	  <property name="fill">False</property>
-	</packing>
-      </child>
-
-      <child>
-	<widget class="GtkHPaned" id="hpaned1">
-	  <property name="width_request">1</property>
-	  <property name="visible">True</property>
-	  <property name="can_focus">True</property>
-	  <property name="position">0</property>
-
-	  <child>
-	    <widget class="GtkScrolledWindow" id="scrolledwindow1">
-	      <property name="visible">True</property>
-	      <property name="hscrollbar_policy">GTK_POLICY_AUTOMATIC</property>
-	      <property name="vscrollbar_policy">GTK_POLICY_AUTOMATIC</property>
-	      <property name="shadow_type">GTK_SHADOW_IN</property>
-	      <property name="window_placement">GTK_CORNER_TOP_LEFT</property>
-
-	      <child>
-		<widget class="GtkTreeView" id="treeview1">
-		  <property name="visible">True</property>
-		  <property name="can_focus">True</property>
-		  <property name="headers_visible">True</property>
-		  <property name="rules_hint">False</property>
-		  <property name="reorderable">False</property>
-		  <property name="enable_search">False</property>
-		  <signal name="cursor_changed" handler="on_treeview2_cursor_changed" last_modification_time="Sun, 12 Jan 2003 15:58:22 GMT"/>
-		  <signal name="button_press_event" handler="on_treeview1_button_press_event" last_modification_time="Sun, 12 Jan 2003 16:03:52 GMT"/>
-		  <signal name="key_press_event" handler="on_treeview2_key_press_event" last_modification_time="Sun, 12 Jan 2003 16:11:44 GMT"/>
-		</widget>
-	      </child>
-	    </widget>
-	    <packing>
-	      <property name="shrink">True</property>
-	      <property name="resize">False</property>
-	    </packing>
-	  </child>
-
-	  <child>
-	    <widget class="GtkVPaned" id="vpaned1">
-	      <property name="visible">True</property>
-	      <property name="can_focus">True</property>
-	      <property name="position">0</property>
-
-	      <child>
-		<widget class="GtkScrolledWindow" id="scrolledwindow2">
-		  <property name="visible">True</property>
-		  <property name="hscrollbar_policy">GTK_POLICY_AUTOMATIC</property>
-		  <property name="vscrollbar_policy">GTK_POLICY_AUTOMATIC</property>
-		  <property name="shadow_type">GTK_SHADOW_IN</property>
-		  <property name="window_placement">GTK_CORNER_TOP_LEFT</property>
-
-		  <child>
-		    <widget class="GtkTreeView" id="treeview2">
-		      <property name="visible">True</property>
-		      <property name="can_focus">True</property>
-		      <property name="has_focus">True</property>
-		      <property name="headers_visible">True</property>
-		      <property name="rules_hint">False</property>
-		      <property name="reorderable">False</property>
-		      <property name="enable_search">False</property>
-		      <signal name="cursor_changed" handler="on_treeview2_cursor_changed" last_modification_time="Sun, 12 Jan 2003 15:57:55 GMT"/>
-		      <signal name="button_press_event" handler="on_treeview2_button_press_event" last_modification_time="Sun, 12 Jan 2003 15:57:58 GMT"/>
-		      <signal name="key_press_event" handler="on_treeview2_key_press_event" last_modification_time="Sun, 12 Jan 2003 15:58:01 GMT"/>
-		    </widget>
-		  </child>
-		</widget>
-		<packing>
-		  <property name="shrink">True</property>
-		  <property name="resize">False</property>
-		</packing>
-	      </child>
-
-	      <child>
-		<widget class="GtkScrolledWindow" id="scrolledwindow3">
-		  <property name="visible">True</property>
-		  <property name="hscrollbar_policy">GTK_POLICY_NEVER</property>
-		  <property name="vscrollbar_policy">GTK_POLICY_AUTOMATIC</property>
-		  <property name="shadow_type">GTK_SHADOW_IN</property>
-		  <property name="window_placement">GTK_CORNER_TOP_LEFT</property>
-
-		  <child>
-		    <widget class="GtkTextView" id="textview3">
-		      <property name="visible">True</property>
-		      <property name="can_focus">True</property>
-		      <property name="editable">False</property>
-		      <property name="overwrite">False</property>
-		      <property name="accepts_tab">True</property>
-		      <property name="justification">GTK_JUSTIFY_LEFT</property>
-		      <property name="wrap_mode">GTK_WRAP_WORD</property>
-		      <property name="cursor_visible">True</property>
-		      <property name="pixels_above_lines">0</property>
-		      <property name="pixels_below_lines">0</property>
-		      <property name="pixels_inside_wrap">0</property>
-		      <property name="left_margin">0</property>
-		      <property name="right_margin">0</property>
-		      <property name="indent">0</property>
-		      <property name="text" translatable="yes">Sorry, no help available for this option yet.</property>
-		    </widget>
-		  </child>
-		</widget>
-		<packing>
-		  <property name="shrink">True</property>
-		  <property name="resize">True</property>
-		</packing>
-	      </child>
-	    </widget>
-	    <packing>
-	      <property name="shrink">True</property>
-	      <property name="resize">True</property>
-	    </packing>
-	  </child>
-	</widget>
-	<packing>
-	  <property name="padding">0</property>
-	  <property name="expand">True</property>
-	  <property name="fill">True</property>
-	</packing>
-      </child>
-    </widget>
-  </child>
-</widget>
-
-</glade-interface>
diff --git a/util/kconfig/images.c b/util/kconfig/images.c
deleted file mode 100644
index b4fa0e4a63..0000000000
--- a/util/kconfig/images.c
+++ /dev/null
@@ -1,328 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org>
- */
-
-#include "images.h"
-
-const char *xpm_load[] = {
-"22 22 5 1",
-". c None",
-"# c #000000",
-"c c #838100",
-"a c #ffff00",
-"b c #ffffff",
-"......................",
-"......................",
-"......................",
-"............####....#.",
-"...........#....##.##.",
-"..................###.",
-".................####.",
-".####...........#####.",
-"#abab##########.......",
-"#babababababab#.......",
-"#ababababababa#.......",
-"#babababababab#.......",
-"#ababab###############",
-"#babab##cccccccccccc##",
-"#abab##cccccccccccc##.",
-"#bab##cccccccccccc##..",
-"#ab##cccccccccccc##...",
-"#b##cccccccccccc##....",
-"###cccccccccccc##.....",
-"##cccccccccccc##......",
-"###############.......",
-"......................"};
-
-const char *xpm_save[] = {
-"22 22 5 1",
-". c None",
-"# c #000000",
-"a c #838100",
-"b c #c5c2c5",
-"c c #cdb6d5",
-"......................",
-".####################.",
-".#aa#bbbbbbbbbbbb#bb#.",
-".#aa#bbbbbbbbbbbb#bb#.",
-".#aa#bbbbbbbbbcbb####.",
-".#aa#bbbccbbbbbbb#aa#.",
-".#aa#bbbccbbbbbbb#aa#.",
-".#aa#bbbbbbbbbbbb#aa#.",
-".#aa#bbbbbbbbbbbb#aa#.",
-".#aa#bbbbbbbbbbbb#aa#.",
-".#aa#bbbbbbbbbbbb#aa#.",
-".#aaa############aaa#.",
-".#aaaaaaaaaaaaaaaaaa#.",
-".#aaaaaaaaaaaaaaaaaa#.",
-".#aaa#############aa#.",
-".#aaa#########bbb#aa#.",
-".#aaa#########bbb#aa#.",
-".#aaa#########bbb#aa#.",
-".#aaa#########bbb#aa#.",
-".#aaa#########bbb#aa#.",
-"..##################..",
-"......................"};
-
-const char *xpm_back[] = {
-"22 22 3 1",
-". c None",
-"# c #000083",
-"a c #838183",
-"......................",
-"......................",
-"......................",
-"......................",
-"......................",
-"...........######a....",
-"..#......##########...",
-"..##...####......##a..",
-"..###.###.........##..",
-"..######..........##..",
-"..#####...........##..",
-"..######..........##..",
-"..#######.........##..",
-"..########.......##a..",
-"...............a###...",
-"...............###....",
-"......................",
-"......................",
-"......................",
-"......................",
-"......................",
-"......................"};
-
-const char *xpm_tree_view[] = {
-"22 22 2 1",
-". c None",
-"# c #000000",
-"......................",
-"......................",
-"......#...............",
-"......#...............",
-"......#...............",
-"......#...............",
-"......#...............",
-"......########........",
-"......#...............",
-"......#...............",
-"......#...............",
-"......#...............",
-"......#...............",
-"......########........",
-"......#...............",
-"......#...............",
-"......#...............",
-"......#...............",
-"......#...............",
-"......########........",
-"......................",
-"......................"};
-
-const char *xpm_single_view[] = {
-"22 22 2 1",
-". c None",
-"# c #000000",
-"......................",
-"......................",
-"..........#...........",
-"..........#...........",
-"..........#...........",
-"..........#...........",
-"..........#...........",
-"..........#...........",
-"..........#...........",
-"..........#...........",
-"..........#...........",
-"..........#...........",
-"..........#...........",
-"..........#...........",
-"..........#...........",
-"..........#...........",
-"..........#...........",
-"..........#...........",
-"..........#...........",
-"..........#...........",
-"......................",
-"......................"};
-
-const char *xpm_split_view[] = {
-"22 22 2 1",
-". c None",
-"# c #000000",
-"......................",
-"......................",
-"......#......#........",
-"......#......#........",
-"......#......#........",
-"......#......#........",
-"......#......#........",
-"......#......#........",
-"......#......#........",
-"......#......#........",
-"......#......#........",
-"......#......#........",
-"......#......#........",
-"......#......#........",
-"......#......#........",
-"......#......#........",
-"......#......#........",
-"......#......#........",
-"......#......#........",
-"......#......#........",
-"......................",
-"......................"};
-
-const char *xpm_symbol_no[] = {
-"12 12 2 1",
-"  c white",
-". c black",
-"            ",
-" .......... ",
-" .        . ",
-" .        . ",
-" .        . ",
-" .        . ",
-" .        . ",
-" .        . ",
-" .        . ",
-" .        . ",
-" .......... ",
-"            "};
-
-const char *xpm_symbol_mod[] = {
-"12 12 2 1",
-"  c white",
-". c black",
-"            ",
-" .......... ",
-" .        . ",
-" .        . ",
-" .   ..   . ",
-" .  ....  . ",
-" .  ....  . ",
-" .   ..   . ",
-" .        . ",
-" .        . ",
-" .......... ",
-"            "};
-
-const char *xpm_symbol_yes[] = {
-"12 12 2 1",
-"  c white",
-". c black",
-"            ",
-" .......... ",
-" .        . ",
-" .        . ",
-" .      . . ",
-" .     .. . ",
-" . .  ..  . ",
-" . ....   . ",
-" .  ..    . ",
-" .        . ",
-" .......... ",
-"            "};
-
-const char *xpm_choice_no[] = {
-"12 12 2 1",
-"  c white",
-". c black",
-"            ",
-"    ....    ",
-"  ..    ..  ",
-"  .      .  ",
-" .        . ",
-" .        . ",
-" .        . ",
-" .        . ",
-"  .      .  ",
-"  ..    ..  ",
-"    ....    ",
-"            "};
-
-const char *xpm_choice_yes[] = {
-"12 12 2 1",
-"  c white",
-". c black",
-"            ",
-"    ....    ",
-"  ..    ..  ",
-"  .      .  ",
-" .   ..   . ",
-" .  ....  . ",
-" .  ....  . ",
-" .   ..   . ",
-"  .      .  ",
-"  ..    ..  ",
-"    ....    ",
-"            "};
-
-const char *xpm_menu[] = {
-"12 12 2 1",
-"  c white",
-". c black",
-"            ",
-" .......... ",
-" .        . ",
-" . ..     . ",
-" . ....   . ",
-" . ...... . ",
-" . ...... . ",
-" . ....   . ",
-" . ..     . ",
-" .        . ",
-" .......... ",
-"            "};
-
-const char *xpm_menu_inv[] = {
-"12 12 2 1",
-"  c white",
-". c black",
-"            ",
-" .......... ",
-" .......... ",
-" ..  ...... ",
-" ..    .... ",
-" ..      .. ",
-" ..      .. ",
-" ..    .... ",
-" ..  ...... ",
-" .......... ",
-" .......... ",
-"            "};
-
-const char *xpm_menuback[] = {
-"12 12 2 1",
-"  c white",
-". c black",
-"            ",
-" .......... ",
-" .        . ",
-" .     .. . ",
-" .   .... . ",
-" . ...... . ",
-" . ...... . ",
-" .   .... . ",
-" .     .. . ",
-" .        . ",
-" .......... ",
-"            "};
-
-const char *xpm_void[] = {
-"12 12 2 1",
-"  c white",
-". c black",
-"            ",
-"            ",
-"            ",
-"            ",
-"            ",
-"            ",
-"            ",
-"            ",
-"            ",
-"            ",
-"            ",
-"            "};
diff --git a/util/kconfig/images.h b/util/kconfig/images.h
deleted file mode 100644
index d8ff614bd0..0000000000
--- a/util/kconfig/images.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org>
- */
-
-#ifndef IMAGES_H
-#define IMAGES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-extern const char *xpm_load[];
-extern const char *xpm_save[];
-extern const char *xpm_back[];
-extern const char *xpm_tree_view[];
-extern const char *xpm_single_view[];
-extern const char *xpm_split_view[];
-extern const char *xpm_symbol_no[];
-extern const char *xpm_symbol_mod[];
-extern const char *xpm_symbol_yes[];
-extern const char *xpm_choice_no[];
-extern const char *xpm_choice_yes[];
-extern const char *xpm_menu[];
-extern const char *xpm_menu_inv[];
-extern const char *xpm_menuback[];
-extern const char *xpm_void[];
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* IMAGES_H */
diff --git a/util/kconfig/lexer.l b/util/kconfig/lexer.l
deleted file mode 100644
index 6354c905b0..0000000000
--- a/util/kconfig/lexer.l
+++ /dev/null
@@ -1,471 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org>
- */
-%option nostdinit noyywrap never-interactive full ecs
-%option 8bit nodefault yylineno
-%x ASSIGN_VAL HELP STRING
-%{
-
-#include <assert.h>
-#include <limits.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
-
-#include "lkc.h"
-#include "parser.tab.h"
-
-#define YY_DECL		static int yylex1(void)
-
-#define START_STRSIZE	16
-
-static struct {
-	struct file *file;
-	int lineno;
-} current_pos;
-
-static int prev_prev_token = T_EOL;
-static int prev_token = T_EOL;
-static char *text;
-static int text_size, text_asize;
-
-struct buffer {
-	struct buffer *parent;
-	YY_BUFFER_STATE state;
-};
-
-struct buffer *current_buf;
-
-static int last_ts, first_ts;
-
-static char *expand_token(const char *in, size_t n);
-static void append_expanded_string(const char *in);
-static void zconf_endhelp(void);
-static void zconf_endfile(void);
-
-static void new_string(void)
-{
-	text = xmalloc(START_STRSIZE);
-	text_asize = START_STRSIZE;
-	text_size = 0;
-	*text = 0;
-}
-
-static void append_string(const char *str, int size)
-{
-	int new_size = text_size + size + 1;
-	if (new_size > text_asize) {
-		new_size += START_STRSIZE - 1;
-		new_size &= -START_STRSIZE;
-		text = xrealloc(text, new_size);
-		text_asize = new_size;
-	}
-	memcpy(text + text_size, str, size);
-	text_size += size;
-	text[text_size] = 0;
-}
-
-static void alloc_string(const char *str, int size)
-{
-	text = xmalloc(size + 1);
-	memcpy(text, str, size);
-	text[size] = 0;
-}
-
-static void warn_ignored_character(char chr)
-{
-	fprintf(stderr,
-	        "%s:%d:warning: ignoring unsupported character '%c'\n",
-	        current_file->name, yylineno, chr);
-}
-%}
-
-n	[A-Za-z0-9_-]
-
-%%
-	int str = 0;
-	int ts, i;
-
-#.*			/* ignore comment */
-[ \t]*			/* whitespaces */
-\\\n			/* escaped new line */
-\n			return T_EOL;
-"allnoconfig_y"		return T_ALLNOCONFIG_Y;
-"bool"			return T_BOOL;
-"choice"		return T_CHOICE;
-"comment"		return T_COMMENT;
-"config"		return T_CONFIG;
-"def_bool"		return T_DEF_BOOL;
-"def_tristate"		return T_DEF_TRISTATE;
-"default"		return T_DEFAULT;
-"defconfig_list"	return T_DEFCONFIG_LIST;
-"depends"		return T_DEPENDS;
-"endchoice"		return T_ENDCHOICE;
-"endif"			return T_ENDIF;
-"endmenu"		return T_ENDMENU;
-"help"|"---help---"	return T_HELP;
-"hex"			return T_HEX;
-"if"			return T_IF;
-"imply"			return T_IMPLY;
-"int"			return T_INT;
-"mainmenu"		return T_MAINMENU;
-"menu"			return T_MENU;
-"menuconfig"		return T_MENUCONFIG;
-"modules"		return T_MODULES;
-"on"			return T_ON;
-"option"		return T_OPTION;
-"optional"		return T_OPTIONAL;
-"prompt"		return T_PROMPT;
-"range"			return T_RANGE;
-"select"		return T_SELECT;
-"source"		return T_SOURCE;
-"string"		return T_STRING;
-"tristate"		return T_TRISTATE;
-"visible"		return T_VISIBLE;
-"||"			return T_OR;
-"&&"			return T_AND;
-"="			return T_EQUAL;
-"!="			return T_UNEQUAL;
-"<"			return T_LESS;
-"<="			return T_LESS_EQUAL;
-">"			return T_GREATER;
-">="			return T_GREATER_EQUAL;
-"!"			return T_NOT;
-"("			return T_OPEN_PAREN;
-")"			return T_CLOSE_PAREN;
-":="			return T_COLON_EQUAL;
-"+="			return T_PLUS_EQUAL;
-\"|\'			{
-				str = yytext[0];
-				new_string();
-				BEGIN(STRING);
-			}
-{n}+			{
-				alloc_string(yytext, yyleng);
-				yylval.string = text;
-				return T_WORD;
-			}
-({n}|$)+		{
-				/* this token includes at least one '$' */
-				yylval.string = expand_token(yytext, yyleng);
-				if (strlen(yylval.string))
-					return T_WORD;
-				free(yylval.string);
-			}
-.			warn_ignored_character(*yytext);
-
-<ASSIGN_VAL>{
-	[^[:blank:]\n]+.*	{
-		alloc_string(yytext, yyleng);
-		yylval.string = text;
-		return T_ASSIGN_VAL;
-	}
-	\n	{ BEGIN(INITIAL); return T_EOL; }
-	.
-}
-
-<STRING>{
-	"$".*	append_expanded_string(yytext);
-	[^$'"\\\n]+	{
-		append_string(yytext, yyleng);
-	}
-	\\.?	{
-		append_string(yytext + 1, yyleng - 1);
-	}
-	\'|\"	{
-		if (str == yytext[0]) {
-			BEGIN(INITIAL);
-			yylval.string = text;
-			return T_WORD_QUOTE;
-		} else
-			append_string(yytext, 1);
-	}
-	\n	{
-		fprintf(stderr,
-			"%s:%d:warning: multi-line strings not supported\n",
-			zconf_curname(), zconf_lineno());
-		unput('\n');
-		BEGIN(INITIAL);
-		yylval.string = text;
-		return T_WORD_QUOTE;
-	}
-	<<EOF>>	{
-		BEGIN(INITIAL);
-		yylval.string = text;
-		return T_WORD_QUOTE;
-	}
-}
-
-<HELP>{
-	[ \t]+	{
-		ts = 0;
-		for (i = 0; i < yyleng; i++) {
-			if (yytext[i] == '\t')
-				ts = (ts & ~7) + 8;
-			else
-				ts++;
-		}
-		last_ts = ts;
-		if (first_ts) {
-			if (ts < first_ts) {
-				zconf_endhelp();
-				return T_HELPTEXT;
-			}
-			ts -= first_ts;
-			while (ts > 8) {
-				append_string("        ", 8);
-				ts -= 8;
-			}
-			append_string("        ", ts);
-		}
-	}
-	[ \t]*\n/[^ \t\n] {
-		zconf_endhelp();
-		return T_HELPTEXT;
-	}
-	[ \t]*\n	{
-		append_string("\n", 1);
-	}
-	[^ \t\n].* {
-		while (yyleng) {
-			if ((yytext[yyleng-1] != ' ') && (yytext[yyleng-1] != '\t'))
-				break;
-			yyleng--;
-		}
-		append_string(yytext, yyleng);
-		if (!first_ts)
-			first_ts = last_ts;
-	}
-	<<EOF>>	{
-		zconf_endhelp();
-		return T_HELPTEXT;
-	}
-}
-
-<<EOF>>	{
-	BEGIN(INITIAL);
-
-	if (prev_token != T_EOL && prev_token != T_HELPTEXT)
-		fprintf(stderr, "%s:%d:warning: no new line at end of file\n",
-			current_file->name, yylineno);
-
-	if (current_file) {
-		zconf_endfile();
-		return T_EOL;
-	}
-	fclose(yyin);
-	yyterminate();
-}
-
-%%
-
-/* second stage lexer */
-int yylex(void)
-{
-	int token;
-
-repeat:
-	token = yylex1();
-
-	if (prev_token == T_EOL || prev_token == T_HELPTEXT) {
-		if (token == T_EOL) {
-			/* Do not pass unneeded T_EOL to the parser. */
-			goto repeat;
-		} else {
-			/*
-			 * For the parser, update file/lineno at the first token
-			 * of each statement. Generally, \n is a statement
-			 * terminator in Kconfig, but it is not always true
-			 * because \n could be escaped by a backslash.
-			 */
-			current_pos.file = current_file;
-			current_pos.lineno = yylineno;
-		}
-	}
-
-	if (prev_prev_token == T_EOL && prev_token == T_WORD &&
-	    (token == T_EQUAL || token == T_COLON_EQUAL || token == T_PLUS_EQUAL))
-		BEGIN(ASSIGN_VAL);
-
-	prev_prev_token = prev_token;
-	prev_token = token;
-
-	return token;
-}
-
-static char *expand_token(const char *in, size_t n)
-{
-	char *out;
-	int c;
-	char c2;
-	const char *rest, *end;
-
-	new_string();
-	append_string(in, n);
-
-	/* get the whole line because we do not know the end of token. */
-	while ((c = input()) != EOF) {
-		if (c == '\n') {
-			unput(c);
-			break;
-		}
-		c2 = c;
-		append_string(&c2, 1);
-	}
-
-	rest = text;
-	out = expand_one_token(&rest);
-
-	/* push back unused characters to the input stream */
-	end = rest + strlen(rest);
-	while (end > rest)
-		unput(*--end);
-
-	free(text);
-
-	return out;
-}
-
-static void append_expanded_string(const char *str)
-{
-	const char *end;
-	char *res;
-
-	str++;
-
-	res = expand_dollar(&str);
-
-	/* push back unused characters to the input stream */
-	end = str + strlen(str);
-	while (end > str)
-		unput(*--end);
-
-	append_string(res, strlen(res));
-
-	free(res);
-}
-
-void zconf_starthelp(void)
-{
-	new_string();
-	last_ts = first_ts = 0;
-	BEGIN(HELP);
-}
-
-static void zconf_endhelp(void)
-{
-	yylval.string = text;
-	BEGIN(INITIAL);
-}
-
-
-/*
- * Try to open specified file with following names:
- * ./name
- * $(srctree)/name
- * The latter is used when srctree is separate from objtree
- * when compiling the kernel.
- * Return NULL if file is not found.
- */
-FILE *zconf_fopen(const char *name)
-{
-	char *env, fullname[PATH_MAX+1];
-	FILE *f;
-
-	f = fopen(name, "r");
-	if (!f && name != NULL && name[0] != '/') {
-		env = getenv(SRCTREE);
-		if (env) {
-			snprintf(fullname, sizeof(fullname),
-				 "%s/%s", env, name);
-			f = fopen(fullname, "r");
-		}
-	}
-	return f;
-}
-
-void zconf_initscan(const char *name)
-{
-	yyin = zconf_fopen(name);
-	if (!yyin) {
-		fprintf(stderr, "can't find file %s\n", name);
-		exit(1);
-	}
-
-	current_buf = xmalloc(sizeof(*current_buf));
-	memset(current_buf, 0, sizeof(*current_buf));
-
-	current_file = file_lookup(name);
-	yylineno = 1;
-}
-
-void zconf_nextfile(const char *name)
-{
-	struct file *iter;
-	struct file *file = file_lookup(name);
-	struct buffer *buf = xmalloc(sizeof(*buf));
-	memset(buf, 0, sizeof(*buf));
-
-	current_buf->state = YY_CURRENT_BUFFER;
-	yyin = zconf_fopen(file->name);
-	if (!yyin) {
-		fprintf(stderr, "%s:%d: can't open file \"%s\"\n",
-			zconf_curname(), zconf_lineno(), file->name);
-		exit(1);
-	}
-	yy_switch_to_buffer(yy_create_buffer(yyin, YY_BUF_SIZE));
-	buf->parent = current_buf;
-	current_buf = buf;
-
-	current_file->lineno = yylineno;
-	file->parent = current_file;
-
-	for (iter = current_file; iter; iter = iter->parent) {
-		if (!strcmp(iter->name, file->name)) {
-			fprintf(stderr,
-				"Recursive inclusion detected.\n"
-				"Inclusion path:\n"
-				"  current file : %s\n", file->name);
-			iter = file;
-			do {
-				iter = iter->parent;
-				fprintf(stderr, "  included from: %s:%d\n",
-					iter->name, iter->lineno - 1);
-			} while (strcmp(iter->name, file->name));
-			exit(1);
-		}
-	}
-
-	yylineno = 1;
-	current_file = file;
-}
-
-static void zconf_endfile(void)
-{
-	struct buffer *parent;
-
-	current_file = current_file->parent;
-	if (current_file)
-		yylineno = current_file->lineno;
-
-	parent = current_buf->parent;
-	if (parent) {
-		fclose(yyin);
-		yy_delete_buffer(YY_CURRENT_BUFFER);
-		yy_switch_to_buffer(parent->state);
-	}
-	free(current_buf);
-	current_buf = parent;
-}
-
-int zconf_lineno(void)
-{
-	return current_pos.lineno;
-}
-
-const char *zconf_curname(void)
-{
-	return current_pos.file ? current_pos.file->name : "<none>";
-}
diff --git a/util/kconfig/list.h b/util/kconfig/list.h
deleted file mode 100644
index 45cb237ab7..0000000000
--- a/util/kconfig/list.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef LIST_H
-#define LIST_H
-
-/*
- * Copied from include/linux/...
- */
-
-#undef offsetof
-#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
-
-/**
- * container_of - cast a member of a structure out to the containing structure
- * @ptr:        the pointer to the member.
- * @type:       the type of the container struct this is embedded in.
- * @member:     the name of the member within the struct.
- *
- */
-#define container_of(ptr, type, member) ({                      \
-	const typeof( ((type *)0)->member ) *__mptr = (ptr);    \
-	(type *)( (char *)__mptr - offsetof(type,member) );})
-
-
-struct list_head {
-	struct list_head *next, *prev;
-};
-
-
-#define LIST_HEAD_INIT(name) { &(name), &(name) }
-
-#define LIST_HEAD(name) \
-	struct list_head name = LIST_HEAD_INIT(name)
-
-/**
- * list_entry - get the struct for this entry
- * @ptr:	the &struct list_head pointer.
- * @type:	the type of the struct this is embedded in.
- * @member:	the name of the list_head within the struct.
- */
-#define list_entry(ptr, type, member) \
-	container_of(ptr, type, member)
-
-/**
- * list_for_each_entry	-	iterate over list of given type
- * @pos:	the type * to use as a loop cursor.
- * @head:	the head for your list.
- * @member:	the name of the list_head within the struct.
- */
-#define list_for_each_entry(pos, head, member)				\
-	for (pos = list_entry((head)->next, typeof(*pos), member);	\
-	     &pos->member != (head); 	\
-	     pos = list_entry(pos->member.next, typeof(*pos), member))
-
-/**
- * list_for_each_entry_safe - iterate over list of given type safe against removal of list entry
- * @pos:	the type * to use as a loop cursor.
- * @n:		another type * to use as temporary storage
- * @head:	the head for your list.
- * @member:	the name of the list_head within the struct.
- */
-#define list_for_each_entry_safe(pos, n, head, member)			\
-	for (pos = list_entry((head)->next, typeof(*pos), member),	\
-		n = list_entry(pos->member.next, typeof(*pos), member);	\
-	     &pos->member != (head);					\
-	     pos = n, n = list_entry(n->member.next, typeof(*n), member))
-
-/**
- * list_empty - tests whether a list is empty
- * @head: the list to test.
- */
-static inline int list_empty(const struct list_head *head)
-{
-	return head->next == head;
-}
-
-/*
- * Insert a new entry between two known consecutive entries.
- *
- * This is only for internal list manipulation where we know
- * the prev/next entries already!
- */
-static inline void __list_add(struct list_head *_new,
-			      struct list_head *prev,
-			      struct list_head *next)
-{
-	next->prev = _new;
-	_new->next = next;
-	_new->prev = prev;
-	prev->next = _new;
-}
-
-/**
- * list_add_tail - add a new entry
- * @new: new entry to be added
- * @head: list head to add it before
- *
- * Insert a new entry before the specified head.
- * This is useful for implementing queues.
- */
-static inline void list_add_tail(struct list_head *_new, struct list_head *head)
-{
-	__list_add(_new, head->prev, head);
-}
-
-/*
- * Delete a list entry by making the prev/next entries
- * point to each other.
- *
- * This is only for internal list manipulation where we know
- * the prev/next entries already!
- */
-static inline void __list_del(struct list_head *prev, struct list_head *next)
-{
-	next->prev = prev;
-	prev->next = next;
-}
-
-#define LIST_POISON1  ((void *) 0x00100100)
-#define LIST_POISON2  ((void *) 0x00200200)
-/**
- * list_del - deletes entry from list.
- * @entry: the element to delete from the list.
- * Note: list_empty() on entry does not return true after this, the entry is
- * in an undefined state.
- */
-static inline void list_del(struct list_head *entry)
-{
-	__list_del(entry->prev, entry->next);
-	entry->next = (struct list_head*)LIST_POISON1;
-	entry->prev = (struct list_head*)LIST_POISON2;
-}
-#endif
diff --git a/util/kconfig/lkc.h b/util/kconfig/lkc.h
deleted file mode 100644
index 4fb16f3166..0000000000
--- a/util/kconfig/lkc.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org>
- */
-
-#ifndef LKC_H
-#define LKC_H
-
-#include "expr.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "lkc_proto.h"
-
-#define SRCTREE "srctree"
-
-#ifndef PACKAGE
-#define PACKAGE "linux"
-#endif
-
-#ifndef CONFIG_
-#define CONFIG_ "CONFIG_"
-#endif
-static inline const char *CONFIG_prefix(void)
-{
-	return getenv( "CONFIG_" ) ?: CONFIG_;
-}
-#undef CONFIG_
-#define CONFIG_ CONFIG_prefix()
-
-enum conf_def_mode {
-	def_default,
-	def_yes,
-	def_mod,
-	def_no,
-	def_random
-};
-
-extern int yylineno;
-void zconfdump(FILE *out);
-void zconf_starthelp(void);
-FILE *zconf_fopen(const char *name);
-void zconf_initscan(const char *name);
-void zconf_nextfile(const char *name);
-int zconf_lineno(void);
-const char *zconf_curname(void);
-
-/* confdata.c */
-const char *conf_get_configname(void);
-void sym_set_change_count(int count);
-void sym_add_change_count(int count);
-bool conf_set_all_new_symbols(enum conf_def_mode mode);
-void set_all_choice_values(struct symbol *csym);
-
-/* confdata.c and expr.c */
-static inline void xfwrite(const void *str, size_t len, size_t count, FILE *out)
-{
-	assert(len != 0);
-
-	if (fwrite(str, len, count, out) != count)
-		fprintf(stderr, "Error in writing or end of file.\n");
-}
-
-/* menu.c */
-void _menu_init(void);
-void menu_warn(struct menu *menu, const char *fmt, ...);
-struct menu *menu_add_menu(void);
-void menu_end_menu(void);
-void menu_add_entry(struct symbol *sym);
-void menu_add_dep(struct expr *dep);
-void menu_add_visibility(struct expr *dep);
-struct property *menu_add_prompt(enum prop_type type, char *prompt, struct expr *dep);
-void menu_add_expr(enum prop_type type, struct expr *expr, struct expr *dep);
-void menu_add_symbol(enum prop_type type, struct symbol *sym, struct expr *dep);
-void menu_add_option_modules(void);
-void menu_add_option_defconfig_list(void);
-void menu_add_option_allnoconfig_y(void);
-void menu_finalize(struct menu *parent);
-void menu_set_type(int type);
-
-/* util.c */
-struct file *file_lookup(const char *name);
-void *xmalloc(size_t size);
-void *xcalloc(size_t nmemb, size_t size);
-void *xrealloc(void *p, size_t size);
-char *xstrdup(const char *s);
-char *xstrndup(const char *s, size_t n);
-
-/* lexer.l */
-int yylex(void);
-
-struct gstr {
-	size_t len;
-	char  *s;
-	/*
-	* when max_width is not zero long lines in string s (if any) get
-	* wrapped not to exceed the max_width value
-	*/
-	int max_width;
-};
-struct gstr str_new(void);
-void str_free(struct gstr *gs);
-void str_append(struct gstr *gs, const char *s);
-void str_printf(struct gstr *gs, const char *fmt, ...);
-const char *str_get(struct gstr *gs);
-
-/* symbol.c */
-void sym_clear_all_valid(void);
-struct symbol *sym_choice_default(struct symbol *sym);
-struct property *sym_get_range_prop(struct symbol *sym);
-const char *sym_get_string_default(struct symbol *sym);
-struct symbol *sym_check_deps(struct symbol *sym);
-struct property *prop_alloc(enum prop_type type, struct symbol *sym);
-struct symbol *prop_get_symbol(struct property *prop);
-
-static inline tristate sym_get_tristate_value(struct symbol *sym)
-{
-	return sym->curr.tri;
-}
-
-
-static inline struct symbol *sym_get_choice_value(struct symbol *sym)
-{
-	return (struct symbol *)sym->curr.val;
-}
-
-static inline bool sym_set_choice_value(struct symbol *ch, struct symbol *chval)
-{
-	return sym_set_tristate_value(chval, yes);
-}
-
-static inline bool sym_is_choice(struct symbol *sym)
-{
-	return sym->flags & SYMBOL_CHOICE ? true : false;
-}
-
-static inline bool sym_is_choice_value(struct symbol *sym)
-{
-	return sym->flags & SYMBOL_CHOICEVAL ? true : false;
-}
-
-static inline bool sym_is_optional(struct symbol *sym)
-{
-	return sym->flags & SYMBOL_OPTIONAL ? true : false;
-}
-
-static inline bool sym_has_value(struct symbol *sym)
-{
-	return sym->flags & SYMBOL_DEF_USER ? true : false;
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LKC_H */
diff --git a/util/kconfig/lkc_proto.h b/util/kconfig/lkc_proto.h
deleted file mode 100644
index f9ab98238a..0000000000
--- a/util/kconfig/lkc_proto.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#include <stdarg.h>
-
-/* confdata.c */
-void conf_parse(const char *name);
-int conf_read(const char *name);
-int conf_read_simple(const char *name, int);
-int conf_write_defconfig(const char *name);
-int conf_write(const char *name);
-int conf_write_autoconf(int overwrite);
-bool conf_get_changed(void);
-void conf_set_changed_callback(void (*fn)(void));
-void conf_set_message_callback(void (*fn)(const char *s));
-
-/* menu.c */
-extern struct menu rootmenu;
-
-bool menu_is_empty(struct menu *menu);
-bool menu_is_visible(struct menu *menu);
-bool menu_has_prompt(struct menu *menu);
-const char * menu_get_prompt(struct menu *menu);
-struct menu * menu_get_root_menu(struct menu *menu);
-struct menu * menu_get_parent_menu(struct menu *menu);
-bool menu_has_help(struct menu *menu);
-const char * menu_get_help(struct menu *menu);
-struct gstr get_relations_str(struct symbol **sym_arr, struct list_head *head);
-void menu_get_ext_help(struct menu *menu, struct gstr *help);
-
-/* symbol.c */
-extern struct symbol * symbol_hash[SYMBOL_HASHSIZE];
-
-struct symbol * sym_lookup(const char *name, int flags);
-struct symbol * sym_find(const char *name);
-const char * sym_escape_string_value(const char *in);
-struct symbol ** sym_re_search(const char *pattern);
-const char * sym_type_name(enum symbol_type type);
-void sym_calc_value(struct symbol *sym);
-enum symbol_type sym_get_type(struct symbol *sym);
-bool sym_tristate_within_range(struct symbol *sym,tristate tri);
-bool sym_set_tristate_value(struct symbol *sym,tristate tri);
-tristate sym_toggle_tristate_value(struct symbol *sym);
-bool sym_string_valid(struct symbol *sym, const char *newval);
-bool sym_string_within_range(struct symbol *sym, const char *str);
-bool sym_set_string_value(struct symbol *sym, const char *newval);
-bool sym_is_changeable(struct symbol *sym);
-struct property * sym_get_choice_prop(struct symbol *sym);
-const char * sym_get_string_value(struct symbol *sym);
-
-const char * prop_get_type_name(enum prop_type type);
-
-/* preprocess.c */
-enum variable_flavor {
-	VAR_SIMPLE,
-	VAR_RECURSIVE,
-	VAR_APPEND,
-};
-void env_write_dep(FILE *f, const char *auto_conf_name);
-void variable_add(const char *name, const char *value,
-		  enum variable_flavor flavor);
-void variable_all_del(void);
-char *expand_dollar(const char **str);
-char *expand_one_token(const char **str);
-
-/* expr.c */
-void expr_print(struct expr *e, void (*fn)(void *, struct symbol *, const char *), void *data, int prevtoken);
diff --git a/util/kconfig/lxdialog/BIG.FAT.WARNING b/util/kconfig/lxdialog/BIG.FAT.WARNING
deleted file mode 100644
index 7cb5a7ec93..0000000000
--- a/util/kconfig/lxdialog/BIG.FAT.WARNING
+++ /dev/null
@@ -1,4 +0,0 @@
-This is NOT the official version of dialog.  This version has been
-significantly modified from the original.  It is for use by the Linux
-kernel configuration script.  Please do not bother Savio Lam with
-questions about this program.
diff --git a/util/kconfig/lxdialog/checklist.c b/util/kconfig/lxdialog/checklist.c
deleted file mode 100644
index fd161cfff1..0000000000
--- a/util/kconfig/lxdialog/checklist.c
+++ /dev/null
@@ -1,319 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- *  checklist.c -- implements the checklist box
- *
- *  ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk)
- *     Stuart Herbert - S.Herbert@sheffield.ac.uk: radiolist extension
- *     Alessandro Rubini - rubini@ipvvis.unipv.it: merged the two
- *  MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com)
- */
-
-#include "dialog.h"
-
-static int list_width, check_x, item_x;
-
-/*
- * Print list item
- */
-static void print_item(WINDOW * win, int choice, int selected)
-{
-	int i;
-	char *list_item = malloc(list_width + 1);
-
-	strncpy(list_item, item_str(), list_width - item_x);
-	list_item[list_width - item_x] = '\0';
-
-	/* Clear 'residue' of last item */
-	wattrset(win, dlg.menubox.atr);
-	wmove(win, choice, 0);
-	for (i = 0; i < list_width; i++)
-		waddch(win, ' ');
-
-	wmove(win, choice, check_x);
-	wattrset(win, selected ? dlg.check_selected.atr
-		 : dlg.check.atr);
-	if (!item_is_tag(':'))
-		wprintw(win, "(%c)", item_is_tag('X') ? 'X' : ' ');
-
-	wattrset(win, selected ? dlg.tag_selected.atr : dlg.tag.atr);
-	mvwaddch(win, choice, item_x, list_item[0]);
-	wattrset(win, selected ? dlg.item_selected.atr : dlg.item.atr);
-	waddstr(win, list_item + 1);
-	if (selected) {
-		wmove(win, choice, check_x + 1);
-		wrefresh(win);
-	}
-	free(list_item);
-}
-
-/*
- * Print the scroll indicators.
- */
-static void print_arrows(WINDOW * win, int choice, int item_no, int scroll,
-	     int y, int x, int height)
-{
-	wmove(win, y, x);
-
-	if (scroll > 0) {
-		wattrset(win, dlg.uarrow.atr);
-		waddch(win, ACS_UARROW);
-		waddstr(win, "(-)");
-	} else {
-		wattrset(win, dlg.menubox.atr);
-		waddch(win, ACS_HLINE);
-		waddch(win, ACS_HLINE);
-		waddch(win, ACS_HLINE);
-		waddch(win, ACS_HLINE);
-	}
-
-	y = y + height + 1;
-	wmove(win, y, x);
-
-	if ((height < item_no) && (scroll + choice < item_no - 1)) {
-		wattrset(win, dlg.darrow.atr);
-		waddch(win, ACS_DARROW);
-		waddstr(win, "(+)");
-	} else {
-		wattrset(win, dlg.menubox_border.atr);
-		waddch(win, ACS_HLINE);
-		waddch(win, ACS_HLINE);
-		waddch(win, ACS_HLINE);
-		waddch(win, ACS_HLINE);
-	}
-}
-
-/*
- *  Display the termination buttons
- */
-static void print_buttons(WINDOW * dialog, int height, int width, int selected)
-{
-	int x = width / 2 - 11;
-	int y = height - 2;
-
-	print_button(dialog, "Select", y, x, selected == 0);
-	print_button(dialog, " Help ", y, x + 14, selected == 1);
-
-	wmove(dialog, y, x + 1 + 14 * selected);
-	wrefresh(dialog);
-}
-
-/*
- * Display a dialog box with a list of options that can be turned on or off
- * in the style of radiolist (only one option turned on at a time).
- */
-int dialog_checklist(const char *title, const char *prompt, int height,
-		     int width, int list_height)
-{
-	int i, x, y, box_x, box_y;
-	int key = 0, button = 0, choice = 0, scroll = 0, max_choice;
-	WINDOW *dialog, *list;
-
-	/* which item to highlight */
-	item_foreach() {
-		if (item_is_tag('X'))
-			choice = item_n();
-		if (item_is_selected()) {
-			choice = item_n();
-			break;
-		}
-	}
-
-do_resize:
-	if (getmaxy(stdscr) < (height + CHECKLIST_HEIGTH_MIN))
-		return -ERRDISPLAYTOOSMALL;
-	if (getmaxx(stdscr) < (width + CHECKLIST_WIDTH_MIN))
-		return -ERRDISPLAYTOOSMALL;
-
-	max_choice = MIN(list_height, item_count());
-
-	/* center dialog box on screen */
-	x = (getmaxx(stdscr) - width) / 2;
-	y = (getmaxy(stdscr) - height) / 2;
-
-	draw_shadow(stdscr, y, x, height, width);
-
-	dialog = newwin(height, width, y, x);
-	keypad(dialog, TRUE);
-
-	draw_box(dialog, 0, 0, height, width,
-		 dlg.dialog.atr, dlg.border.atr);
-	wattrset(dialog, dlg.border.atr);
-	mvwaddch(dialog, height - 3, 0, ACS_LTEE);
-	for (i = 0; i < width - 2; i++)
-		waddch(dialog, ACS_HLINE);
-	wattrset(dialog, dlg.dialog.atr);
-	waddch(dialog, ACS_RTEE);
-
-	print_title(dialog, title, width);
-
-	wattrset(dialog, dlg.dialog.atr);
-	print_autowrap(dialog, prompt, width - 2, 1, 3);
-
-	list_width = width - 6;
-	box_y = height - list_height - 5;
-	box_x = (width - list_width) / 2 - 1;
-
-	/* create new window for the list */
-	list = subwin(dialog, list_height, list_width, y + box_y + 1,
-		      x + box_x + 1);
-
-	keypad(list, TRUE);
-
-	/* draw a box around the list items */
-	draw_box(dialog, box_y, box_x, list_height + 2, list_width + 2,
-		 dlg.menubox_border.atr, dlg.menubox.atr);
-
-	/* Find length of longest item in order to center checklist */
-	check_x = 0;
-	item_foreach()
-		check_x = MAX(check_x, strlen(item_str()) + 4);
-	check_x = MIN(check_x, list_width);
-
-	check_x = (list_width - check_x) / 2;
-	item_x = check_x + 4;
-
-	if (choice >= list_height) {
-		scroll = choice - list_height + 1;
-		choice -= scroll;
-	}
-
-	/* Print the list */
-	for (i = 0; i < max_choice; i++) {
-		item_set(scroll + i);
-		print_item(list, i, i == choice);
-	}
-
-	print_arrows(dialog, choice, item_count(), scroll,
-		     box_y, box_x + check_x + 5, list_height);
-
-	print_buttons(dialog, height, width, 0);
-
-	wnoutrefresh(dialog);
-	wnoutrefresh(list);
-	doupdate();
-
-	while (key != KEY_ESC) {
-		key = wgetch(dialog);
-
-		for (i = 0; i < max_choice; i++) {
-			item_set(i + scroll);
-			if (toupper(key) == toupper(item_str()[0]))
-				break;
-		}
-
-		if (i < max_choice || key == KEY_UP || key == KEY_DOWN ||
-		    key == '+' || key == '-') {
-			if (key == KEY_UP || key == '-') {
-				if (!choice) {
-					if (!scroll)
-						continue;
-					/* Scroll list down */
-					if (list_height > 1) {
-						/* De-highlight current first item */
-						item_set(scroll);
-						print_item(list, 0, FALSE);
-						scrollok(list, TRUE);
-						wscrl(list, -1);
-						scrollok(list, FALSE);
-					}
-					scroll--;
-					item_set(scroll);
-					print_item(list, 0, TRUE);
-					print_arrows(dialog, choice, item_count(),
-						     scroll, box_y, box_x + check_x + 5, list_height);
-
-					wnoutrefresh(dialog);
-					wrefresh(list);
-
-					continue;	/* wait for another key press */
-				} else
-					i = choice - 1;
-			} else if (key == KEY_DOWN || key == '+') {
-				if (choice == max_choice - 1) {
-					if (scroll + choice >= item_count() - 1)
-						continue;
-					/* Scroll list up */
-					if (list_height > 1) {
-						/* De-highlight current last item before scrolling up */
-						item_set(scroll + max_choice - 1);
-						print_item(list,
-							    max_choice - 1,
-							    FALSE);
-						scrollok(list, TRUE);
-						wscrl(list, 1);
-						scrollok(list, FALSE);
-					}
-					scroll++;
-					item_set(scroll + max_choice - 1);
-					print_item(list, max_choice - 1, TRUE);
-
-					print_arrows(dialog, choice, item_count(),
-						     scroll, box_y, box_x + check_x + 5, list_height);
-
-					wnoutrefresh(dialog);
-					wrefresh(list);
-
-					continue;	/* wait for another key press */
-				} else
-					i = choice + 1;
-			}
-			if (i != choice) {
-				/* De-highlight current item */
-				item_set(scroll + choice);
-				print_item(list, choice, FALSE);
-				/* Highlight new item */
-				choice = i;
-				item_set(scroll + choice);
-				print_item(list, choice, TRUE);
-				wnoutrefresh(dialog);
-				wrefresh(list);
-			}
-			continue;	/* wait for another key press */
-		}
-		switch (key) {
-		case 'H':
-		case 'h':
-		case '?':
-			button = 1;
-			/* fall-through */
-		case 'S':
-		case 's':
-		case ' ':
-		case '\n':
-			item_foreach()
-				item_set_selected(0);
-			item_set(scroll + choice);
-			item_set_selected(1);
-			delwin(list);
-			delwin(dialog);
-			return button;
-		case TAB:
-		case KEY_LEFT:
-		case KEY_RIGHT:
-			button = ((key == KEY_LEFT ? --button : ++button) < 0)
-			    ? 1 : (button > 1 ? 0 : button);
-
-			print_buttons(dialog, height, width, button);
-			wrefresh(dialog);
-			break;
-		case 'X':
-		case 'x':
-			key = KEY_ESC;
-			break;
-		case KEY_ESC:
-			key = on_key_esc(dialog);
-			break;
-		case KEY_RESIZE:
-			delwin(list);
-			delwin(dialog);
-			on_key_resize();
-			goto do_resize;
-		}
-
-		/* Now, update everything... */
-		doupdate();
-	}
-	delwin(list);
-	delwin(dialog);
-	return key;		/* ESC pressed */
-}
diff --git a/util/kconfig/lxdialog/dialog.h b/util/kconfig/lxdialog/dialog.h
deleted file mode 100644
index 68b565e3c4..0000000000
--- a/util/kconfig/lxdialog/dialog.h
+++ /dev/null
@@ -1,238 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- *  dialog.h -- common declarations for all dialog modules
- *
- *  AUTHOR: Savio Lam (lam836@cs.cuhk.hk)
- */
-
-#include <sys/types.h>
-#include <fcntl.h>
-#include <unistd.h>
-#include <ctype.h>
-#include <stdlib.h>
-#include <string.h>
-#include <stdbool.h>
-
-#ifdef __sun__
-#define CURS_MACROS
-#endif
-#include <ncurses.h>
-
-/*
- * Colors in ncurses 1.9.9e do not work properly since foreground and
- * background colors are OR'd rather than separately masked.  This version
- * of dialog was hacked to work with ncurses 1.9.9e, making it incompatible
- * with standard curses.  The simplest fix (to make this work with standard
- * curses) uses the wbkgdset() function, not used in the original hack.
- * Turn it off if we're building with 1.9.9e, since it just confuses things.
- */
-#if defined(NCURSES_VERSION) && defined(_NEED_WRAP) && !defined(GCC_PRINTFLIKE)
-#define OLD_NCURSES 1
-#undef  wbkgdset
-#define wbkgdset(w,p)		/*nothing */
-#else
-#define OLD_NCURSES 0
-#endif
-
-#define TR(params) _tracef params
-
-#define KEY_ESC 27
-#define TAB 9
-#define MAX_LEN 2048
-#define BUF_SIZE (10*1024)
-#define MIN(x,y) (x < y ? x : y)
-#define MAX(x,y) (x > y ? x : y)
-
-#ifndef ACS_ULCORNER
-#define ACS_ULCORNER '+'
-#endif
-#ifndef ACS_LLCORNER
-#define ACS_LLCORNER '+'
-#endif
-#ifndef ACS_URCORNER
-#define ACS_URCORNER '+'
-#endif
-#ifndef ACS_LRCORNER
-#define ACS_LRCORNER '+'
-#endif
-#ifndef ACS_HLINE
-#define ACS_HLINE '-'
-#endif
-#ifndef ACS_VLINE
-#define ACS_VLINE '|'
-#endif
-#ifndef ACS_LTEE
-#define ACS_LTEE '+'
-#endif
-#ifndef ACS_RTEE
-#define ACS_RTEE '+'
-#endif
-#ifndef ACS_UARROW
-#define ACS_UARROW '^'
-#endif
-#ifndef ACS_DARROW
-#define ACS_DARROW 'v'
-#endif
-
-/* error return codes */
-#define ERRDISPLAYTOOSMALL (KEY_MAX + 1)
-
-/*
- *   Color definitions
- */
-struct dialog_color {
-	chtype atr;	/* Color attribute */
-	int fg;		/* foreground */
-	int bg;		/* background */
-	int hl;		/* highlight this item */
-};
-
-struct subtitle_list {
-	struct subtitle_list *next;
-	const char *text;
-};
-
-struct dialog_info {
-	const char *backtitle;
-	struct subtitle_list *subtitles;
-	struct dialog_color screen;
-	struct dialog_color shadow;
-	struct dialog_color dialog;
-	struct dialog_color title;
-	struct dialog_color border;
-	struct dialog_color button_active;
-	struct dialog_color button_inactive;
-	struct dialog_color button_key_active;
-	struct dialog_color button_key_inactive;
-	struct dialog_color button_label_active;
-	struct dialog_color button_label_inactive;
-	struct dialog_color inputbox;
-	struct dialog_color inputbox_border;
-	struct dialog_color searchbox;
-	struct dialog_color searchbox_title;
-	struct dialog_color searchbox_border;
-	struct dialog_color position_indicator;
-	struct dialog_color menubox;
-	struct dialog_color menubox_border;
-	struct dialog_color item;
-	struct dialog_color item_selected;
-	struct dialog_color tag;
-	struct dialog_color tag_selected;
-	struct dialog_color tag_key;
-	struct dialog_color tag_key_selected;
-	struct dialog_color check;
-	struct dialog_color check_selected;
-	struct dialog_color uarrow;
-	struct dialog_color darrow;
-};
-
-/*
- * Global variables
- */
-extern struct dialog_info dlg;
-extern char dialog_input_result[];
-extern int saved_x, saved_y;		/* Needed in signal handler in mconf.c */
-
-/*
- * Function prototypes
- */
-
-/* item list as used by checklist and menubox */
-void item_reset(void);
-void item_make(const char *fmt, ...);
-void item_add_str(const char *fmt, ...);
-void item_set_tag(char tag);
-void item_set_data(void *p);
-void item_set_selected(int val);
-int item_activate_selected(void);
-void *item_data(void);
-char item_tag(void);
-
-/* item list manipulation for lxdialog use */
-#define MAXITEMSTR 200
-struct dialog_item {
-	char str[MAXITEMSTR];	/* prompt displayed */
-	char tag;
-	void *data;	/* pointer to menu item - used by menubox+checklist */
-	int selected;	/* Set to 1 by dialog_*() function if selected. */
-};
-
-/* list of lialog_items */
-struct dialog_list {
-	struct dialog_item node;
-	struct dialog_list *next;
-};
-
-extern struct dialog_list *item_cur;
-extern struct dialog_list item_nil;
-extern struct dialog_list *item_head;
-
-int item_count(void);
-void item_set(int n);
-int item_n(void);
-const char *item_str(void);
-int item_is_selected(void);
-int item_is_tag(char tag);
-#define item_foreach() \
-	for (item_cur = item_head ? item_head: item_cur; \
-	     item_cur && (item_cur != &item_nil); item_cur = item_cur->next)
-
-/* generic key handlers */
-int on_key_esc(WINDOW *win);
-int on_key_resize(void);
-
-/* minimum (re)size values */
-#define CHECKLIST_HEIGTH_MIN 6	/* For dialog_checklist() */
-#define CHECKLIST_WIDTH_MIN 6
-#define INPUTBOX_HEIGTH_MIN 2	/* For dialog_inputbox() */
-#define INPUTBOX_WIDTH_MIN 2
-#define MENUBOX_HEIGTH_MIN 15	/* For dialog_menu() */
-#define MENUBOX_WIDTH_MIN 65
-#define TEXTBOX_HEIGTH_MIN 8	/* For dialog_textbox() */
-#define TEXTBOX_WIDTH_MIN 8
-#define YESNO_HEIGTH_MIN 4	/* For dialog_yesno() */
-#define YESNO_WIDTH_MIN 4
-#define WINDOW_HEIGTH_MIN 19	/* For init_dialog() */
-#define WINDOW_WIDTH_MIN 80
-
-int init_dialog(const char *backtitle);
-void set_dialog_backtitle(const char *backtitle);
-void set_dialog_subtitles(struct subtitle_list *subtitles);
-void end_dialog(int x, int y);
-void attr_clear(WINDOW * win, int height, int width, chtype attr);
-void dialog_clear(void);
-void print_autowrap(WINDOW * win, const char *prompt, int width, int y, int x);
-void print_button(WINDOW * win, const char *label, int y, int x, int selected);
-void print_title(WINDOW *dialog, const char *title, int width);
-void draw_box(WINDOW * win, int y, int x, int height, int width, chtype box,
-	      chtype border);
-void draw_shadow(WINDOW * win, int y, int x, int height, int width);
-
-int first_alpha(const char *string, const char *exempt);
-int dialog_yesno(const char *title, const char *prompt, int height, int width);
-int dialog_msgbox(const char *title, const char *prompt, int height,
-		  int width, int pause);
-
-
-typedef void (*update_text_fn)(char *buf, size_t start, size_t end, void
-			       *_data);
-int dialog_textbox(const char *title, char *tbuf, int initial_height,
-		   int initial_width, int *keys, int *_vscroll, int *_hscroll,
-		   update_text_fn update_text, void *data);
-int dialog_menu(const char *title, const char *prompt,
-		const void *selected, int *s_scroll);
-int dialog_checklist(const char *title, const char *prompt, int height,
-		     int width, int list_height);
-int dialog_inputbox(const char *title, const char *prompt, int height,
-		    int width, const char *init);
-
-/*
- * This is the base for fictitious keys, which activate
- * the buttons.
- *
- * Mouse-generated keys are the following:
- *   -- the first 32 are used as numbers, in addition to '0'-'9'
- *   -- the lowercase are used to signal mouse-enter events (M_EVENT + 'o')
- *   -- uppercase chars are used to invoke the button (M_EVENT + 'O')
- */
-#define M_EVENT (KEY_MAX+1)
diff --git a/util/kconfig/lxdialog/inputbox.c b/util/kconfig/lxdialog/inputbox.c
deleted file mode 100644
index 1dcfb288ee..0000000000
--- a/util/kconfig/lxdialog/inputbox.c
+++ /dev/null
@@ -1,289 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- *  inputbox.c -- implements the input box
- *
- *  ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk)
- *  MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com)
- */
-
-#include "dialog.h"
-
-char dialog_input_result[MAX_LEN + 1];
-
-/*
- *  Print the termination buttons
- */
-static void print_buttons(WINDOW * dialog, int height, int width, int selected)
-{
-	int x = width / 2 - 11;
-	int y = height - 2;
-
-	print_button(dialog, "  Ok  ", y, x, selected == 0);
-	print_button(dialog, " Help ", y, x + 14, selected == 1);
-
-	wmove(dialog, y, x + 1 + 14 * selected);
-	wrefresh(dialog);
-}
-
-/*
- * Display a dialog box for inputing a string
- */
-int dialog_inputbox(const char *title, const char *prompt, int height, int width,
-		    const char *init)
-{
-	int i, x, y, box_y, box_x, box_width;
-	int input_x = 0, key = 0, button = -1;
-	int show_x, len, pos;
-	char *instr = dialog_input_result;
-	WINDOW *dialog;
-
-	if (!init)
-		instr[0] = '\0';
-	else
-		strcpy(instr, init);
-
-do_resize:
-	if (getmaxy(stdscr) <= (height - INPUTBOX_HEIGTH_MIN))
-		return -ERRDISPLAYTOOSMALL;
-	if (getmaxx(stdscr) <= (width - INPUTBOX_WIDTH_MIN))
-		return -ERRDISPLAYTOOSMALL;
-
-	/* center dialog box on screen */
-	x = (getmaxx(stdscr) - width) / 2;
-	y = (getmaxy(stdscr) - height) / 2;
-
-	draw_shadow(stdscr, y, x, height, width);
-
-	dialog = newwin(height, width, y, x);
-	keypad(dialog, TRUE);
-
-	draw_box(dialog, 0, 0, height, width,
-		 dlg.dialog.atr, dlg.border.atr);
-	wattrset(dialog, dlg.border.atr);
-	mvwaddch(dialog, height - 3, 0, ACS_LTEE);
-	for (i = 0; i < width - 2; i++)
-		waddch(dialog, ACS_HLINE);
-	wattrset(dialog, dlg.dialog.atr);
-	waddch(dialog, ACS_RTEE);
-
-	print_title(dialog, title, width);
-
-	wattrset(dialog, dlg.dialog.atr);
-	print_autowrap(dialog, prompt, width - 2, 1, 3);
-
-	/* Draw the input field box */
-	box_width = width - 6;
-	getyx(dialog, y, x);
-	box_y = y + 2;
-	box_x = (width - box_width) / 2;
-	draw_box(dialog, y + 1, box_x - 1, 3, box_width + 2,
-		 dlg.dialog.atr, dlg.border.atr);
-
-	print_buttons(dialog, height, width, 0);
-
-	/* Set up the initial value */
-	wmove(dialog, box_y, box_x);
-	wattrset(dialog, dlg.inputbox.atr);
-
-	len = strlen(instr);
-	pos = len;
-
-	if (len >= box_width) {
-		show_x = len - box_width + 1;
-		input_x = box_width - 1;
-		for (i = 0; i < box_width - 1; i++)
-			waddch(dialog, instr[show_x + i]);
-	} else {
-		show_x = 0;
-		input_x = len;
-		waddstr(dialog, instr);
-	}
-
-	wmove(dialog, box_y, box_x + input_x);
-
-	wrefresh(dialog);
-
-	while (key != KEY_ESC) {
-		key = wgetch(dialog);
-
-		if (button == -1) {	/* Input box selected */
-			switch (key) {
-			case TAB:
-			case KEY_UP:
-			case KEY_DOWN:
-				break;
-			case KEY_BACKSPACE:
-			case 8:   /* ^H */
-			case 127: /* ^? */
-				if (pos) {
-					wattrset(dialog, dlg.inputbox.atr);
-					if (input_x == 0) {
-						show_x--;
-					} else
-						input_x--;
-
-					if (pos < len) {
-						for (i = pos - 1; i < len; i++) {
-							instr[i] = instr[i+1];
-						}
-					}
-
-					pos--;
-					len--;
-					instr[len] = '\0';
-					wmove(dialog, box_y, box_x);
-					for (i = 0; i < box_width; i++) {
-						if (!instr[show_x + i]) {
-							waddch(dialog, ' ');
-							break;
-						}
-						waddch(dialog, instr[show_x + i]);
-					}
-					wmove(dialog, box_y, input_x + box_x);
-					wrefresh(dialog);
-				}
-				continue;
-			case KEY_LEFT:
-				if (pos > 0) {
-					if (input_x > 0) {
-						wmove(dialog, box_y, --input_x + box_x);
-					} else if (input_x == 0) {
-						show_x--;
-						wmove(dialog, box_y, box_x);
-						for (i = 0; i < box_width; i++) {
-							if (!instr[show_x + i]) {
-								waddch(dialog, ' ');
-								break;
-							}
-							waddch(dialog, instr[show_x + i]);
-						}
-						wmove(dialog, box_y, box_x);
-					}
-					pos--;
-				}
-				continue;
-			case KEY_RIGHT:
-				if (pos < len) {
-					if (input_x < box_width - 1) {
-						wmove(dialog, box_y, ++input_x + box_x);
-					} else if (input_x == box_width - 1) {
-						show_x++;
-						wmove(dialog, box_y, box_x);
-						for (i = 0; i < box_width; i++) {
-							if (!instr[show_x + i]) {
-								waddch(dialog, ' ');
-								break;
-							}
-							waddch(dialog, instr[show_x + i]);
-						}
-						wmove(dialog, box_y, input_x + box_x);
-					}
-					pos++;
-				}
-				continue;
-			default:
-				if (key < 0x100 && isprint(key)) {
-					if (len < MAX_LEN) {
-						wattrset(dialog, dlg.inputbox.atr);
-						if (pos < len) {
-							for (i = len; i > pos; i--)
-								instr[i] = instr[i-1];
-							instr[pos] = key;
-						} else {
-							instr[len] = key;
-						}
-						pos++;
-						len++;
-						instr[len] = '\0';
-
-						if (input_x == box_width - 1) {
-							show_x++;
-						} else {
-							input_x++;
-						}
-
-						wmove(dialog, box_y, box_x);
-						for (i = 0; i < box_width; i++) {
-							if (!instr[show_x + i]) {
-								waddch(dialog, ' ');
-								break;
-							}
-							waddch(dialog, instr[show_x + i]);
-						}
-						wmove(dialog, box_y, input_x + box_x);
-						wrefresh(dialog);
-					} else
-						flash();	/* Alarm user about overflow */
-					continue;
-				}
-			}
-		}
-		switch (key) {
-		case 'O':
-		case 'o':
-			delwin(dialog);
-			return 0;
-		case 'H':
-		case 'h':
-			delwin(dialog);
-			return 1;
-		case KEY_UP:
-		case KEY_LEFT:
-			switch (button) {
-			case -1:
-				button = 1;	/* Indicates "Help" button is selected */
-				print_buttons(dialog, height, width, 1);
-				break;
-			case 0:
-				button = -1;	/* Indicates input box is selected */
-				print_buttons(dialog, height, width, 0);
-				wmove(dialog, box_y, box_x + input_x);
-				wrefresh(dialog);
-				break;
-			case 1:
-				button = 0;	/* Indicates "OK" button is selected */
-				print_buttons(dialog, height, width, 0);
-				break;
-			}
-			break;
-		case TAB:
-		case KEY_DOWN:
-		case KEY_RIGHT:
-			switch (button) {
-			case -1:
-				button = 0;	/* Indicates "OK" button is selected */
-				print_buttons(dialog, height, width, 0);
-				break;
-			case 0:
-				button = 1;	/* Indicates "Help" button is selected */
-				print_buttons(dialog, height, width, 1);
-				break;
-			case 1:
-				button = -1;	/* Indicates input box is selected */
-				print_buttons(dialog, height, width, 0);
-				wmove(dialog, box_y, box_x + input_x);
-				wrefresh(dialog);
-				break;
-			}
-			break;
-		case ' ':
-		case '\n':
-			delwin(dialog);
-			return (button == -1 ? 0 : button);
-		case 'X':
-		case 'x':
-			key = KEY_ESC;
-			break;
-		case KEY_ESC:
-			key = on_key_esc(dialog);
-			break;
-		case KEY_RESIZE:
-			delwin(dialog);
-			on_key_resize();
-			goto do_resize;
-		}
-	}
-
-	delwin(dialog);
-	return KEY_ESC;		/* ESC pressed */
-}
diff --git a/util/kconfig/lxdialog/menubox.c b/util/kconfig/lxdialog/menubox.c
deleted file mode 100644
index 58c2f8afe5..0000000000
--- a/util/kconfig/lxdialog/menubox.c
+++ /dev/null
@@ -1,424 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- *  menubox.c -- implements the menu box
- *
- *  ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk)
- *  MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcapw@cfw.com)
- */
-
-/*
- *  Changes by Clifford Wolf (god@clifford.at)
- *
- *  [ 1998-06-13 ]
- *
- *    *)  A bugfix for the Page-Down problem
- *
- *    *)  Formerly when I used Page Down and Page Up, the cursor would be set
- *        to the first position in the menu box.  Now lxdialog is a bit
- *        smarter and works more like other menu systems (just have a look at
- *        it).
- *
- *    *)  Formerly if I selected something my scrolling would be broken because
- *        lxdialog is re-invoked by the Menuconfig shell script, can't
- *        remember the last scrolling position, and just sets it so that the
- *        cursor is at the bottom of the box.  Now it writes the temporary file
- *        lxdialog.scrltmp which contains this information. The file is
- *        deleted by lxdialog if the user leaves a submenu or enters a new
- *        one, but it would be nice if Menuconfig could make another "rm -f"
- *        just to be sure.  Just try it out - you will recognise a difference!
- *
- *  [ 1998-06-14 ]
- *
- *    *)  Now lxdialog is crash-safe against broken "lxdialog.scrltmp" files
- *        and menus change their size on the fly.
- *
- *    *)  If for some reason the last scrolling position is not saved by
- *        lxdialog, it sets the scrolling so that the selected item is in the
- *        middle of the menu box, not at the bottom.
- *
- * 02 January 1999, Michael Elizabeth Chastain (mec@shout.net)
- * Reset 'scroll' to 0 if the value from lxdialog.scrltmp is bogus.
- * This fixes a bug in Menuconfig where using ' ' to descend into menus
- * would leave mis-synchronized lxdialog.scrltmp files lying around,
- * fscanf would read in 'scroll', and eventually that value would get used.
- */
-
-#include "dialog.h"
-
-static int menu_width, item_x;
-
-/*
- * Print menu item
- */
-static void do_print_item(WINDOW * win, const char *item, int line_y,
-			  int selected, int hotkey)
-{
-	int j;
-	char *menu_item = malloc(menu_width + 1);
-
-	strncpy(menu_item, item, menu_width - item_x);
-	menu_item[menu_width - item_x] = '\0';
-	j = first_alpha(menu_item, "YyNnMmHh");
-
-	/* Clear 'residue' of last item */
-	wattrset(win, dlg.menubox.atr);
-	wmove(win, line_y, 0);
-#if OLD_NCURSES
-	{
-		int i;
-		for (i = 0; i < menu_width; i++)
-			waddch(win, ' ');
-	}
-#else
-	wclrtoeol(win);
-#endif
-	wattrset(win, selected ? dlg.item_selected.atr : dlg.item.atr);
-	mvwaddstr(win, line_y, item_x, menu_item);
-	if (hotkey) {
-		wattrset(win, selected ? dlg.tag_key_selected.atr
-			 : dlg.tag_key.atr);
-		mvwaddch(win, line_y, item_x + j, menu_item[j]);
-	}
-	if (selected) {
-		wmove(win, line_y, item_x + 1);
-	}
-	free(menu_item);
-	wrefresh(win);
-}
-
-#define print_item(index, choice, selected)				\
-do {									\
-	item_set(index);						\
-	do_print_item(menu, item_str(), choice, selected, !item_is_tag(':')); \
-} while (0)
-
-/*
- * Print the scroll indicators.
- */
-static void print_arrows(WINDOW * win, int item_no, int scroll, int y, int x,
-			 int height)
-{
-	int cur_y, cur_x;
-
-	getyx(win, cur_y, cur_x);
-
-	wmove(win, y, x);
-
-	if (scroll > 0) {
-		wattrset(win, dlg.uarrow.atr);
-		waddch(win, ACS_UARROW);
-		waddstr(win, "(-)");
-	} else {
-		wattrset(win, dlg.menubox.atr);
-		waddch(win, ACS_HLINE);
-		waddch(win, ACS_HLINE);
-		waddch(win, ACS_HLINE);
-		waddch(win, ACS_HLINE);
-	}
-
-	y = y + height + 1;
-	wmove(win, y, x);
-	wrefresh(win);
-
-	if ((height < item_no) && (scroll + height < item_no)) {
-		wattrset(win, dlg.darrow.atr);
-		waddch(win, ACS_DARROW);
-		waddstr(win, "(+)");
-	} else {
-		wattrset(win, dlg.menubox_border.atr);
-		waddch(win, ACS_HLINE);
-		waddch(win, ACS_HLINE);
-		waddch(win, ACS_HLINE);
-		waddch(win, ACS_HLINE);
-	}
-
-	wmove(win, cur_y, cur_x);
-	wrefresh(win);
-}
-
-/*
- * Display the termination buttons.
- */
-static void print_buttons(WINDOW * win, int height, int width, int selected)
-{
-	int x = width / 2 - 28;
-	int y = height - 2;
-
-	print_button(win, "Select", y, x, selected == 0);
-	print_button(win, " Exit ", y, x + 12, selected == 1);
-	print_button(win, " Help ", y, x + 24, selected == 2);
-	print_button(win, " Save ", y, x + 36, selected == 3);
-	print_button(win, " Load ", y, x + 48, selected == 4);
-
-	wmove(win, y, x + 1 + 12 * selected);
-	wrefresh(win);
-}
-
-/* scroll up n lines (n may be negative) */
-static void do_scroll(WINDOW *win, int *scroll, int n)
-{
-	/* Scroll menu up */
-	scrollok(win, TRUE);
-	wscrl(win, n);
-	scrollok(win, FALSE);
-	*scroll = *scroll + n;
-	wrefresh(win);
-}
-
-/*
- * Display a menu for choosing among a number of options
- */
-int dialog_menu(const char *title, const char *prompt,
-		const void *selected, int *s_scroll)
-{
-	int i, j, x, y, box_x, box_y;
-	int height, width, menu_height;
-	int key = 0, button = 0, scroll = 0, choice = 0;
-	int first_item =  0, max_choice;
-	WINDOW *dialog, *menu;
-
-do_resize:
-	height = getmaxy(stdscr);
-	width = getmaxx(stdscr);
-	if (height < MENUBOX_HEIGTH_MIN || width < MENUBOX_WIDTH_MIN)
-		return -ERRDISPLAYTOOSMALL;
-
-	height -= 4;
-	width  -= 5;
-	menu_height = height - 10;
-
-	max_choice = MIN(menu_height, item_count());
-
-	/* center dialog box on screen */
-	x = (getmaxx(stdscr) - width) / 2;
-	y = (getmaxy(stdscr) - height) / 2;
-
-	draw_shadow(stdscr, y, x, height, width);
-
-	dialog = newwin(height, width, y, x);
-	keypad(dialog, TRUE);
-
-	draw_box(dialog, 0, 0, height, width,
-		 dlg.dialog.atr, dlg.border.atr);
-	wattrset(dialog, dlg.border.atr);
-	mvwaddch(dialog, height - 3, 0, ACS_LTEE);
-	for (i = 0; i < width - 2; i++)
-		waddch(dialog, ACS_HLINE);
-	wattrset(dialog, dlg.dialog.atr);
-	wbkgdset(dialog, dlg.dialog.atr & A_COLOR);
-	waddch(dialog, ACS_RTEE);
-
-	print_title(dialog, title, width);
-
-	wattrset(dialog, dlg.dialog.atr);
-	print_autowrap(dialog, prompt, width - 2, 1, 3);
-
-	menu_width = width - 6;
-	box_y = height - menu_height - 5;
-	box_x = (width - menu_width) / 2 - 1;
-
-	/* create new window for the menu */
-	menu = subwin(dialog, menu_height, menu_width,
-		      y + box_y + 1, x + box_x + 1);
-	keypad(menu, TRUE);
-
-	/* draw a box around the menu items */
-	draw_box(dialog, box_y, box_x, menu_height + 2, menu_width + 2,
-		 dlg.menubox_border.atr, dlg.menubox.atr);
-
-	if (menu_width >= 80)
-		item_x = (menu_width - 70) / 2;
-	else
-		item_x = 4;
-
-	/* Set choice to default item */
-	item_foreach()
-		if (selected && (selected == item_data()))
-			choice = item_n();
-	/* get the saved scroll info */
-	scroll = *s_scroll;
-	if ((scroll <= choice) && (scroll + max_choice > choice) &&
-	   (scroll >= 0) && (scroll + max_choice <= item_count())) {
-		first_item = scroll;
-		choice = choice - scroll;
-	} else {
-		scroll = 0;
-	}
-	if ((choice >= max_choice)) {
-		if (choice >= item_count() - max_choice / 2)
-			scroll = first_item = item_count() - max_choice;
-		else
-			scroll = first_item = choice - max_choice / 2;
-		choice = choice - scroll;
-	}
-
-	/* Print the menu */
-	for (i = 0; i < max_choice; i++) {
-		print_item(first_item + i, i, i == choice);
-	}
-
-	wnoutrefresh(menu);
-
-	print_arrows(dialog, item_count(), scroll,
-		     box_y, box_x + item_x + 1, menu_height);
-
-	print_buttons(dialog, height, width, 0);
-	wmove(menu, choice, item_x + 1);
-	wrefresh(menu);
-
-	while (key != KEY_ESC) {
-		key = wgetch(menu);
-
-		if (key < 256 && isalpha(key))
-			key = tolower(key);
-
-		if (strchr("ynmh", key))
-			i = max_choice;
-		else {
-			for (i = choice + 1; i < max_choice; i++) {
-				item_set(scroll + i);
-				j = first_alpha(item_str(), "YyNnMmHh");
-				if (key == tolower(item_str()[j]))
-					break;
-			}
-			if (i == max_choice)
-				for (i = 0; i < max_choice; i++) {
-					item_set(scroll + i);
-					j = first_alpha(item_str(), "YyNnMmHh");
-					if (key == tolower(item_str()[j]))
-						break;
-				}
-		}
-
-		if (item_count() != 0 &&
-		    (i < max_choice ||
-		     key == KEY_UP || key == KEY_DOWN ||
-		     key == '-' || key == '+' ||
-		     key == KEY_PPAGE || key == KEY_NPAGE)) {
-			/* Remove highligt of current item */
-			print_item(scroll + choice, choice, FALSE);
-
-			if (key == KEY_UP || key == '-') {
-				if (choice < 2 && scroll) {
-					/* Scroll menu down */
-					do_scroll(menu, &scroll, -1);
-
-					print_item(scroll, 0, FALSE);
-				} else
-					choice = MAX(choice - 1, 0);
-
-			} else if (key == KEY_DOWN || key == '+') {
-				print_item(scroll+choice, choice, FALSE);
-
-				if ((choice > max_choice - 3) &&
-				    (scroll + max_choice < item_count())) {
-					/* Scroll menu up */
-					do_scroll(menu, &scroll, 1);
-
-					print_item(scroll+max_choice - 1,
-						   max_choice - 1, FALSE);
-				} else
-					choice = MIN(choice + 1, max_choice - 1);
-
-			} else if (key == KEY_PPAGE) {
-				scrollok(menu, TRUE);
-				for (i = 0; (i < max_choice); i++) {
-					if (scroll > 0) {
-						do_scroll(menu, &scroll, -1);
-						print_item(scroll, 0, FALSE);
-					} else {
-						if (choice > 0)
-							choice--;
-					}
-				}
-
-			} else if (key == KEY_NPAGE) {
-				for (i = 0; (i < max_choice); i++) {
-					if (scroll + max_choice < item_count()) {
-						do_scroll(menu, &scroll, 1);
-						print_item(scroll+max_choice-1,
-							   max_choice - 1, FALSE);
-					} else {
-						if (choice + 1 < max_choice)
-							choice++;
-					}
-				}
-			} else
-				choice = i;
-
-			print_item(scroll + choice, choice, TRUE);
-
-			print_arrows(dialog, item_count(), scroll,
-				     box_y, box_x + item_x + 1, menu_height);
-
-			wnoutrefresh(dialog);
-			wrefresh(menu);
-
-			continue;	/* wait for another key press */
-		}
-
-		switch (key) {
-		case KEY_LEFT:
-		case TAB:
-		case KEY_RIGHT:
-			button = ((key == KEY_LEFT ? --button : ++button) < 0)
-			    ? 4 : (button > 4 ? 0 : button);
-
-			print_buttons(dialog, height, width, button);
-			wrefresh(menu);
-			break;
-		case ' ':
-		case 's':
-		case 'y':
-		case 'n':
-		case 'm':
-		case '/':
-		case 'h':
-		case '?':
-		case 'z':
-		case '\n':
-			/* save scroll info */
-			*s_scroll = scroll;
-			delwin(menu);
-			delwin(dialog);
-			item_set(scroll + choice);
-			item_set_selected(1);
-			switch (key) {
-			case 'h':
-			case '?':
-				return 2;
-			case 's':
-			case 'y':
-				return 5;
-			case 'n':
-				return 6;
-			case 'm':
-				return 7;
-			case ' ':
-				return 8;
-			case '/':
-				return 9;
-			case 'z':
-				return 10;
-			case '\n':
-				return button;
-			}
-			return 0;
-		case 'e':
-		case 'x':
-			key = KEY_ESC;
-			break;
-		case KEY_ESC:
-			key = on_key_esc(menu);
-			break;
-		case KEY_RESIZE:
-			on_key_resize();
-			delwin(menu);
-			delwin(dialog);
-			goto do_resize;
-		}
-	}
-	delwin(menu);
-	delwin(dialog);
-	return key;		/* ESC pressed */
-}
diff --git a/util/kconfig/lxdialog/textbox.c b/util/kconfig/lxdialog/textbox.c
deleted file mode 100644
index 4e339b1266..0000000000
--- a/util/kconfig/lxdialog/textbox.c
+++ /dev/null
@@ -1,395 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- *  textbox.c -- implements the text box
- *
- *  ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk)
- *  MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com)
- */
-
-#include "dialog.h"
-
-static void back_lines(int n);
-static void print_page(WINDOW *win, int height, int width, update_text_fn
-		       update_text, void *data);
-static void print_line(WINDOW *win, int row, int width);
-static char *get_line(void);
-static void print_position(WINDOW * win);
-
-static int hscroll;
-static int begin_reached, end_reached, page_length;
-static char *buf;
-static char *page;
-
-/*
- * refresh window content
- */
-static void refresh_text_box(WINDOW *dialog, WINDOW *box, int boxh, int boxw,
-			     int cur_y, int cur_x, update_text_fn update_text,
-			     void *data)
-{
-	print_page(box, boxh, boxw, update_text, data);
-	print_position(dialog);
-	wmove(dialog, cur_y, cur_x);	/* Restore cursor position */
-	wrefresh(dialog);
-}
-
-
-/*
- * Display text from a file in a dialog box.
- *
- * keys is a null-terminated array
- * update_text() may not add or remove any '\n' or '\0' in tbuf
- */
-int dialog_textbox(const char *title, char *tbuf, int initial_height,
-		   int initial_width, int *keys, int *_vscroll, int *_hscroll,
-		   update_text_fn update_text, void *data)
-{
-	int i, x, y, cur_x, cur_y, key = 0;
-	int height, width, boxh, boxw;
-	WINDOW *dialog, *box;
-	bool done = false;
-
-	begin_reached = 1;
-	end_reached = 0;
-	page_length = 0;
-	hscroll = 0;
-	buf = tbuf;
-	page = buf;	/* page is pointer to start of page to be displayed */
-
-	if (_vscroll && *_vscroll) {
-		begin_reached = 0;
-
-		for (i = 0; i < *_vscroll; i++)
-			get_line();
-	}
-	if (_hscroll)
-		hscroll = *_hscroll;
-
-do_resize:
-	getmaxyx(stdscr, height, width);
-	if (height < TEXTBOX_HEIGTH_MIN || width < TEXTBOX_WIDTH_MIN)
-		return -ERRDISPLAYTOOSMALL;
-	if (initial_height != 0)
-		height = initial_height;
-	else
-		if (height > 4)
-			height -= 4;
-		else
-			height = 0;
-	if (initial_width != 0)
-		width = initial_width;
-	else
-		if (width > 5)
-			width -= 5;
-		else
-			width = 0;
-
-	/* center dialog box on screen */
-	x = (getmaxx(stdscr) - width) / 2;
-	y = (getmaxy(stdscr) - height) / 2;
-
-	draw_shadow(stdscr, y, x, height, width);
-
-	dialog = newwin(height, width, y, x);
-	keypad(dialog, TRUE);
-
-	/* Create window for box region, used for scrolling text */
-	boxh = height - 4;
-	boxw = width - 2;
-	box = subwin(dialog, boxh, boxw, y + 1, x + 1);
-	wattrset(box, dlg.dialog.atr);
-	wbkgdset(box, dlg.dialog.atr & A_COLOR);
-
-	keypad(box, TRUE);
-
-	/* register the new window, along with its borders */
-	draw_box(dialog, 0, 0, height, width,
-		 dlg.dialog.atr, dlg.border.atr);
-
-	wattrset(dialog, dlg.border.atr);
-	mvwaddch(dialog, height - 3, 0, ACS_LTEE);
-	for (i = 0; i < width - 2; i++)
-		waddch(dialog, ACS_HLINE);
-	wattrset(dialog, dlg.dialog.atr);
-	wbkgdset(dialog, dlg.dialog.atr & A_COLOR);
-	waddch(dialog, ACS_RTEE);
-
-	print_title(dialog, title, width);
-
-	print_button(dialog, " Exit ", height - 2, width / 2 - 4, TRUE);
-	wnoutrefresh(dialog);
-	getyx(dialog, cur_y, cur_x);	/* Save cursor position */
-
-	/* Print first page of text */
-	attr_clear(box, boxh, boxw, dlg.dialog.atr);
-	refresh_text_box(dialog, box, boxh, boxw, cur_y, cur_x, update_text,
-			 data);
-
-	while (!done) {
-		key = wgetch(dialog);
-		switch (key) {
-		case 'E':	/* Exit */
-		case 'e':
-		case 'X':
-		case 'x':
-		case 'q':
-		case '\n':
-			done = true;
-			break;
-		case 'g':	/* First page */
-		case KEY_HOME:
-			if (!begin_reached) {
-				begin_reached = 1;
-				page = buf;
-				refresh_text_box(dialog, box, boxh, boxw,
-						 cur_y, cur_x, update_text,
-						 data);
-			}
-			break;
-		case 'G':	/* Last page */
-		case KEY_END:
-
-			end_reached = 1;
-			/* point to last char in buf */
-			page = buf + strlen(buf);
-			back_lines(boxh);
-			refresh_text_box(dialog, box, boxh, boxw, cur_y,
-					 cur_x, update_text, data);
-			break;
-		case 'K':	/* Previous line */
-		case 'k':
-		case KEY_UP:
-			if (begin_reached)
-				break;
-
-			back_lines(page_length + 1);
-			refresh_text_box(dialog, box, boxh, boxw, cur_y,
-					 cur_x, update_text, data);
-			break;
-		case 'B':	/* Previous page */
-		case 'b':
-		case 'u':
-		case KEY_PPAGE:
-			if (begin_reached)
-				break;
-			back_lines(page_length + boxh);
-			refresh_text_box(dialog, box, boxh, boxw, cur_y,
-					 cur_x, update_text, data);
-			break;
-		case 'J':	/* Next line */
-		case 'j':
-		case KEY_DOWN:
-			if (end_reached)
-				break;
-
-			back_lines(page_length - 1);
-			refresh_text_box(dialog, box, boxh, boxw, cur_y,
-					 cur_x, update_text, data);
-			break;
-		case KEY_NPAGE:	/* Next page */
-		case ' ':
-		case 'd':
-			if (end_reached)
-				break;
-
-			begin_reached = 0;
-			refresh_text_box(dialog, box, boxh, boxw, cur_y,
-					 cur_x, update_text, data);
-			break;
-		case '0':	/* Beginning of line */
-		case 'H':	/* Scroll left */
-		case 'h':
-		case KEY_LEFT:
-			if (hscroll <= 0)
-				break;
-
-			if (key == '0')
-				hscroll = 0;
-			else
-				hscroll--;
-			/* Reprint current page to scroll horizontally */
-			back_lines(page_length);
-			refresh_text_box(dialog, box, boxh, boxw, cur_y,
-					 cur_x, update_text, data);
-			break;
-		case 'L':	/* Scroll right */
-		case 'l':
-		case KEY_RIGHT:
-			if (hscroll >= MAX_LEN)
-				break;
-			hscroll++;
-			/* Reprint current page to scroll horizontally */
-			back_lines(page_length);
-			refresh_text_box(dialog, box, boxh, boxw, cur_y,
-					 cur_x, update_text, data);
-			break;
-		case KEY_ESC:
-			if (on_key_esc(dialog) == KEY_ESC)
-				done = true;
-			break;
-		case KEY_RESIZE:
-			back_lines(height);
-			delwin(box);
-			delwin(dialog);
-			on_key_resize();
-			goto do_resize;
-		default:
-			for (i = 0; keys[i]; i++) {
-				if (key == keys[i]) {
-					done = true;
-					break;
-				}
-			}
-		}
-	}
-	delwin(box);
-	delwin(dialog);
-	if (_vscroll) {
-		const char *s;
-
-		s = buf;
-		*_vscroll = 0;
-		back_lines(page_length);
-		while (s < page && (s = strchr(s, '\n'))) {
-			(*_vscroll)++;
-			s++;
-		}
-	}
-	if (_hscroll)
-		*_hscroll = hscroll;
-	return key;
-}
-
-/*
- * Go back 'n' lines in text. Called by dialog_textbox().
- * 'page' will be updated to point to the desired line in 'buf'.
- */
-static void back_lines(int n)
-{
-	int i;
-
-	begin_reached = 0;
-	/* Go back 'n' lines */
-	for (i = 0; i < n; i++) {
-		if (*page == '\0') {
-			if (end_reached) {
-				end_reached = 0;
-				continue;
-			}
-		}
-		if (page == buf) {
-			begin_reached = 1;
-			return;
-		}
-		page--;
-		do {
-			if (page == buf) {
-				begin_reached = 1;
-				return;
-			}
-			page--;
-		} while (*page != '\n');
-		page++;
-	}
-}
-
-/*
- * Print a new page of text.
- */
-static void print_page(WINDOW *win, int height, int width, update_text_fn
-		       update_text, void *data)
-{
-	int i, passed_end = 0;
-
-	if (update_text) {
-		char *end;
-
-		for (i = 0; i < height; i++)
-			get_line();
-		end = page;
-		back_lines(height);
-		update_text(buf, page - buf, end - buf, data);
-	}
-
-	page_length = 0;
-	for (i = 0; i < height; i++) {
-		print_line(win, i, width);
-		if (!passed_end)
-			page_length++;
-		if (end_reached && !passed_end)
-			passed_end = 1;
-	}
-	wnoutrefresh(win);
-}
-
-/*
- * Print a new line of text.
- */
-static void print_line(WINDOW * win, int row, int width)
-{
-	char *line;
-
-	line = get_line();
-	line += MIN(strlen(line), hscroll);	/* Scroll horizontally */
-	wmove(win, row, 0);	/* move cursor to correct line */
-	waddch(win, ' ');
-	waddnstr(win, line, MIN(strlen(line), width - 2));
-
-	/* Clear 'residue' of previous line */
-#if OLD_NCURSES
-	{
-		int x = getcurx(win);
-		int i;
-		for (i = 0; i < width - x; i++)
-			waddch(win, ' ');
-	}
-#else
-	wclrtoeol(win);
-#endif
-}
-
-/*
- * Return current line of text. Called by dialog_textbox() and print_line().
- * 'page' should point to start of current line before calling, and will be
- * updated to point to start of next line.
- */
-static char *get_line(void)
-{
-	int i = 0;
-	static char line[MAX_LEN + 1];
-
-	end_reached = 0;
-	while (*page != '\n') {
-		if (*page == '\0') {
-			end_reached = 1;
-			break;
-		} else if (i < MAX_LEN)
-			line[i++] = *(page++);
-		else {
-			/* Truncate lines longer than MAX_LEN characters */
-			if (i == MAX_LEN)
-				line[i++] = '\0';
-			page++;
-		}
-	}
-	if (i <= MAX_LEN)
-		line[i] = '\0';
-	if (!end_reached)
-		page++;		/* move past '\n' */
-
-	return line;
-}
-
-/*
- * Print current position
- */
-static void print_position(WINDOW * win)
-{
-	int percent;
-
-	wattrset(win, dlg.position_indicator.atr);
-	wbkgdset(win, dlg.position_indicator.atr & A_COLOR);
-	percent = (page - buf) * 100 / strlen(buf);
-	wmove(win, getmaxy(win) - 3, getmaxx(win) - 9);
-	wprintw(win, "(%3d%%)", percent);
-}
diff --git a/util/kconfig/lxdialog/util.c b/util/kconfig/lxdialog/util.c
deleted file mode 100644
index 1b490d4af0..0000000000
--- a/util/kconfig/lxdialog/util.c
+++ /dev/null
@@ -1,700 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- *  util.c
- *
- *  ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk)
- *  MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com)
- */
-
-#include <stdarg.h>
-
-#include "dialog.h"
-
-/* Needed in signal handler in mconf.c */
-int saved_x, saved_y;
-
-struct dialog_info dlg;
-
-static void set_mono_theme(void)
-{
-	dlg.screen.atr = A_NORMAL;
-	dlg.shadow.atr = A_NORMAL;
-	dlg.dialog.atr = A_NORMAL;
-	dlg.title.atr = A_BOLD;
-	dlg.border.atr = A_NORMAL;
-	dlg.button_active.atr = A_REVERSE;
-	dlg.button_inactive.atr = A_DIM;
-	dlg.button_key_active.atr = A_REVERSE;
-	dlg.button_key_inactive.atr = A_BOLD;
-	dlg.button_label_active.atr = A_REVERSE;
-	dlg.button_label_inactive.atr = A_NORMAL;
-	dlg.inputbox.atr = A_NORMAL;
-	dlg.inputbox_border.atr = A_NORMAL;
-	dlg.searchbox.atr = A_NORMAL;
-	dlg.searchbox_title.atr = A_BOLD;
-	dlg.searchbox_border.atr = A_NORMAL;
-	dlg.position_indicator.atr = A_BOLD;
-	dlg.menubox.atr = A_NORMAL;
-	dlg.menubox_border.atr = A_NORMAL;
-	dlg.item.atr = A_NORMAL;
-	dlg.item_selected.atr = A_REVERSE;
-	dlg.tag.atr = A_BOLD;
-	dlg.tag_selected.atr = A_REVERSE;
-	dlg.tag_key.atr = A_BOLD;
-	dlg.tag_key_selected.atr = A_REVERSE;
-	dlg.check.atr = A_BOLD;
-	dlg.check_selected.atr = A_REVERSE;
-	dlg.uarrow.atr = A_BOLD;
-	dlg.darrow.atr = A_BOLD;
-}
-
-#define DLG_COLOR(dialog, f, b, h) \
-do {                               \
-	dlg.dialog.fg = (f);       \
-	dlg.dialog.bg = (b);       \
-	dlg.dialog.hl = (h);       \
-} while (0)
-
-static void set_classic_theme(void)
-{
-	DLG_COLOR(screen,                COLOR_CYAN,   COLOR_BLUE,   true);
-	DLG_COLOR(shadow,                COLOR_BLACK,  COLOR_BLACK,  true);
-	DLG_COLOR(dialog,                COLOR_BLACK,  COLOR_WHITE,  false);
-	DLG_COLOR(title,                 COLOR_YELLOW, COLOR_WHITE,  true);
-	DLG_COLOR(border,                COLOR_WHITE,  COLOR_WHITE,  true);
-	DLG_COLOR(button_active,         COLOR_WHITE,  COLOR_BLUE,   true);
-	DLG_COLOR(button_inactive,       COLOR_BLACK,  COLOR_WHITE,  false);
-	DLG_COLOR(button_key_active,     COLOR_WHITE,  COLOR_BLUE,   true);
-	DLG_COLOR(button_key_inactive,   COLOR_RED,    COLOR_WHITE,  false);
-	DLG_COLOR(button_label_active,   COLOR_YELLOW, COLOR_BLUE,   true);
-	DLG_COLOR(button_label_inactive, COLOR_BLACK,  COLOR_WHITE,  true);
-	DLG_COLOR(inputbox,              COLOR_BLACK,  COLOR_WHITE,  false);
-	DLG_COLOR(inputbox_border,       COLOR_BLACK,  COLOR_WHITE,  false);
-	DLG_COLOR(searchbox,             COLOR_BLACK,  COLOR_WHITE,  false);
-	DLG_COLOR(searchbox_title,       COLOR_YELLOW, COLOR_WHITE,  true);
-	DLG_COLOR(searchbox_border,      COLOR_WHITE,  COLOR_WHITE,  true);
-	DLG_COLOR(position_indicator,    COLOR_YELLOW, COLOR_WHITE,  true);
-	DLG_COLOR(menubox,               COLOR_BLACK,  COLOR_WHITE,  false);
-	DLG_COLOR(menubox_border,        COLOR_WHITE,  COLOR_WHITE,  true);
-	DLG_COLOR(item,                  COLOR_BLACK,  COLOR_WHITE,  false);
-	DLG_COLOR(item_selected,         COLOR_WHITE,  COLOR_BLUE,   true);
-	DLG_COLOR(tag,                   COLOR_YELLOW, COLOR_WHITE,  true);
-	DLG_COLOR(tag_selected,          COLOR_YELLOW, COLOR_BLUE,   true);
-	DLG_COLOR(tag_key,               COLOR_YELLOW, COLOR_WHITE,  true);
-	DLG_COLOR(tag_key_selected,      COLOR_YELLOW, COLOR_BLUE,   true);
-	DLG_COLOR(check,                 COLOR_BLACK,  COLOR_WHITE,  false);
-	DLG_COLOR(check_selected,        COLOR_WHITE,  COLOR_BLUE,   true);
-	DLG_COLOR(uarrow,                COLOR_GREEN,  COLOR_WHITE,  true);
-	DLG_COLOR(darrow,                COLOR_GREEN,  COLOR_WHITE,  true);
-}
-
-static void set_blackbg_theme(void)
-{
-	DLG_COLOR(screen, COLOR_RED,   COLOR_BLACK, true);
-	DLG_COLOR(shadow, COLOR_BLACK, COLOR_BLACK, false);
-	DLG_COLOR(dialog, COLOR_WHITE, COLOR_BLACK, false);
-	DLG_COLOR(title,  COLOR_RED,   COLOR_BLACK, false);
-	DLG_COLOR(border, COLOR_BLACK, COLOR_BLACK, true);
-
-	DLG_COLOR(button_active,         COLOR_YELLOW, COLOR_RED,   false);
-	DLG_COLOR(button_inactive,       COLOR_YELLOW, COLOR_BLACK, false);
-	DLG_COLOR(button_key_active,     COLOR_YELLOW, COLOR_RED,   true);
-	DLG_COLOR(button_key_inactive,   COLOR_RED,    COLOR_BLACK, false);
-	DLG_COLOR(button_label_active,   COLOR_WHITE,  COLOR_RED,   false);
-	DLG_COLOR(button_label_inactive, COLOR_BLACK,  COLOR_BLACK, true);
-
-	DLG_COLOR(inputbox,         COLOR_YELLOW, COLOR_BLACK, false);
-	DLG_COLOR(inputbox_border,  COLOR_YELLOW, COLOR_BLACK, false);
-
-	DLG_COLOR(searchbox,        COLOR_YELLOW, COLOR_BLACK, false);
-	DLG_COLOR(searchbox_title,  COLOR_YELLOW, COLOR_BLACK, true);
-	DLG_COLOR(searchbox_border, COLOR_BLACK,  COLOR_BLACK, true);
-
-	DLG_COLOR(position_indicator, COLOR_RED, COLOR_BLACK,  false);
-
-	DLG_COLOR(menubox,          COLOR_YELLOW, COLOR_BLACK, false);
-	DLG_COLOR(menubox_border,   COLOR_BLACK,  COLOR_BLACK, true);
-
-	DLG_COLOR(item,             COLOR_WHITE, COLOR_BLACK, false);
-	DLG_COLOR(item_selected,    COLOR_WHITE, COLOR_RED,   false);
-
-	DLG_COLOR(tag,              COLOR_RED,    COLOR_BLACK, false);
-	DLG_COLOR(tag_selected,     COLOR_YELLOW, COLOR_RED,   true);
-	DLG_COLOR(tag_key,          COLOR_RED,    COLOR_BLACK, false);
-	DLG_COLOR(tag_key_selected, COLOR_YELLOW, COLOR_RED,   true);
-
-	DLG_COLOR(check,            COLOR_YELLOW, COLOR_BLACK, false);
-	DLG_COLOR(check_selected,   COLOR_YELLOW, COLOR_RED,   true);
-
-	DLG_COLOR(uarrow, COLOR_RED, COLOR_BLACK, false);
-	DLG_COLOR(darrow, COLOR_RED, COLOR_BLACK, false);
-}
-
-static void set_bluetitle_theme(void)
-{
-	set_classic_theme();
-	DLG_COLOR(title,               COLOR_BLUE,   COLOR_WHITE, true);
-	DLG_COLOR(button_key_active,   COLOR_YELLOW, COLOR_BLUE,  true);
-	DLG_COLOR(button_label_active, COLOR_WHITE,  COLOR_BLUE,  true);
-	DLG_COLOR(searchbox_title,     COLOR_BLUE,   COLOR_WHITE, true);
-	DLG_COLOR(position_indicator,  COLOR_BLUE,   COLOR_WHITE, true);
-	DLG_COLOR(tag,                 COLOR_BLUE,   COLOR_WHITE, true);
-	DLG_COLOR(tag_key,             COLOR_BLUE,   COLOR_WHITE, true);
-
-}
-
-/*
- * Select color theme
- */
-static int set_theme(const char *theme)
-{
-	int use_color = 1;
-	if (!theme)
-		set_bluetitle_theme();
-	else if (strcmp(theme, "classic") == 0)
-		set_classic_theme();
-	else if (strcmp(theme, "bluetitle") == 0)
-		set_bluetitle_theme();
-	else if (strcmp(theme, "blackbg") == 0)
-		set_blackbg_theme();
-	else if (strcmp(theme, "mono") == 0)
-		use_color = 0;
-
-	return use_color;
-}
-
-static void init_one_color(struct dialog_color *color)
-{
-	static int pair = 0;
-
-	pair++;
-	init_pair(pair, color->fg, color->bg);
-	if (color->hl)
-		color->atr = A_BOLD | COLOR_PAIR(pair);
-	else
-		color->atr = COLOR_PAIR(pair);
-}
-
-static void init_dialog_colors(void)
-{
-	init_one_color(&dlg.screen);
-	init_one_color(&dlg.shadow);
-	init_one_color(&dlg.dialog);
-	init_one_color(&dlg.title);
-	init_one_color(&dlg.border);
-	init_one_color(&dlg.button_active);
-	init_one_color(&dlg.button_inactive);
-	init_one_color(&dlg.button_key_active);
-	init_one_color(&dlg.button_key_inactive);
-	init_one_color(&dlg.button_label_active);
-	init_one_color(&dlg.button_label_inactive);
-	init_one_color(&dlg.inputbox);
-	init_one_color(&dlg.inputbox_border);
-	init_one_color(&dlg.searchbox);
-	init_one_color(&dlg.searchbox_title);
-	init_one_color(&dlg.searchbox_border);
-	init_one_color(&dlg.position_indicator);
-	init_one_color(&dlg.menubox);
-	init_one_color(&dlg.menubox_border);
-	init_one_color(&dlg.item);
-	init_one_color(&dlg.item_selected);
-	init_one_color(&dlg.tag);
-	init_one_color(&dlg.tag_selected);
-	init_one_color(&dlg.tag_key);
-	init_one_color(&dlg.tag_key_selected);
-	init_one_color(&dlg.check);
-	init_one_color(&dlg.check_selected);
-	init_one_color(&dlg.uarrow);
-	init_one_color(&dlg.darrow);
-}
-
-/*
- * Setup for color display
- */
-static void color_setup(const char *theme)
-{
-	int use_color;
-
-	use_color = set_theme(theme);
-	if (use_color && has_colors()) {
-		start_color();
-		init_dialog_colors();
-	} else
-		set_mono_theme();
-}
-
-/*
- * Set window to attribute 'attr'
- */
-void attr_clear(WINDOW * win, int height, int width, chtype attr)
-{
-	int i, j;
-
-	wattrset(win, attr);
-	for (i = 0; i < height; i++) {
-		wmove(win, i, 0);
-		for (j = 0; j < width; j++)
-			waddch(win, ' ');
-	}
-	touchwin(win);
-}
-
-void dialog_clear(void)
-{
-	int lines, columns;
-
-	lines = getmaxy(stdscr);
-	columns = getmaxx(stdscr);
-
-	attr_clear(stdscr, lines, columns, dlg.screen.atr);
-	/* Display background title if it exists ... - SLH */
-	if (dlg.backtitle != NULL) {
-		int i, len = 0, skip = 0;
-		struct subtitle_list *pos;
-
-		wattrset(stdscr, dlg.screen.atr);
-		mvwaddstr(stdscr, 0, 1, (char *)dlg.backtitle);
-
-		for (pos = dlg.subtitles; pos != NULL; pos = pos->next) {
-			/* 3 is for the arrow and spaces */
-			len += strlen(pos->text) + 3;
-		}
-
-		wmove(stdscr, 1, 1);
-		if (len > columns - 2) {
-			const char *ellipsis = "[...] ";
-			waddstr(stdscr, ellipsis);
-			skip = len - (columns - 2 - strlen(ellipsis));
-		}
-
-		for (pos = dlg.subtitles; pos != NULL; pos = pos->next) {
-			if (skip == 0)
-				waddch(stdscr, ACS_RARROW);
-			else
-				skip--;
-
-			if (skip == 0)
-				waddch(stdscr, ' ');
-			else
-				skip--;
-
-			if (skip < strlen(pos->text)) {
-				waddstr(stdscr, pos->text + skip);
-				skip = 0;
-			} else
-				skip -= strlen(pos->text);
-
-			if (skip == 0)
-				waddch(stdscr, ' ');
-			else
-				skip--;
-		}
-
-		for (i = len + 1; i < columns - 1; i++)
-			waddch(stdscr, ACS_HLINE);
-	}
-	wnoutrefresh(stdscr);
-}
-
-/*
- * Do some initialization for dialog
- */
-int init_dialog(const char *backtitle)
-{
-	int height, width;
-
-	initscr();		/* Init curses */
-
-	/* Get current cursor position for signal handler in mconf.c */
-	getyx(stdscr, saved_y, saved_x);
-
-	getmaxyx(stdscr, height, width);
-	if (height < WINDOW_HEIGTH_MIN || width < WINDOW_WIDTH_MIN) {
-		endwin();
-		return -ERRDISPLAYTOOSMALL;
-	}
-
-	dlg.backtitle = backtitle;
-	color_setup(getenv("MENUCONFIG_COLOR"));
-
-	keypad(stdscr, TRUE);
-	cbreak();
-	noecho();
-	dialog_clear();
-
-	return 0;
-}
-
-void set_dialog_backtitle(const char *backtitle)
-{
-	dlg.backtitle = backtitle;
-}
-
-void set_dialog_subtitles(struct subtitle_list *subtitles)
-{
-	dlg.subtitles = subtitles;
-}
-
-/*
- * End using dialog functions.
- */
-void end_dialog(int x, int y)
-{
-	/* move cursor back to original position */
-	move(y, x);
-	refresh();
-	endwin();
-}
-
-/* Print the title of the dialog. Center the title and truncate
- * tile if wider than dialog (- 2 chars).
- **/
-void print_title(WINDOW *dialog, const char *title, int width)
-{
-	if (title) {
-		int tlen = MIN(width - 2, strlen(title));
-		wattrset(dialog, dlg.title.atr);
-		mvwaddch(dialog, 0, (width - tlen) / 2 - 1, ' ');
-		mvwaddnstr(dialog, 0, (width - tlen)/2, title, tlen);
-		waddch(dialog, ' ');
-	}
-}
-
-/*
- * Print a string of text in a window, automatically wrap around to the
- * next line if the string is too long to fit on one line. Newline
- * characters '\n' are propperly processed.  We start on a new line
- * if there is no room for at least 4 nonblanks following a double-space.
- */
-void print_autowrap(WINDOW * win, const char *prompt, int width, int y, int x)
-{
-	int newl, cur_x, cur_y;
-	int prompt_len, room, wlen;
-	char tempstr[MAX_LEN + 1], *word, *sp, *sp2, *newline_separator = 0;
-
-	strcpy(tempstr, prompt);
-
-	prompt_len = strlen(tempstr);
-
-	if (prompt_len <= width - x * 2) {	/* If prompt is short */
-		wmove(win, y, (width - prompt_len) / 2);
-		waddstr(win, tempstr);
-	} else {
-		cur_x = x;
-		cur_y = y;
-		newl = 1;
-		word = tempstr;
-		while (word && *word) {
-			sp = strpbrk(word, "\n ");
-			if (sp && *sp == '\n')
-				newline_separator = sp;
-
-			if (sp)
-				*sp++ = 0;
-
-			/* Wrap to next line if either the word does not fit,
-			   or it is the first word of a new sentence, and it is
-			   short, and the next word does not fit. */
-			room = width - cur_x;
-			wlen = strlen(word);
-			if (wlen > room ||
-			    (newl && wlen < 4 && sp
-			     && wlen + 1 + strlen(sp) > room
-			     && (!(sp2 = strpbrk(sp, "\n "))
-				 || wlen + 1 + (sp2 - sp) > room))) {
-				cur_y++;
-				cur_x = x;
-			}
-			wmove(win, cur_y, cur_x);
-			waddstr(win, word);
-			getyx(win, cur_y, cur_x);
-
-			/* Move to the next line if the word separator was a newline */
-			if (newline_separator) {
-				cur_y++;
-				cur_x = x;
-				newline_separator = 0;
-			} else
-				cur_x++;
-
-			if (sp && *sp == ' ') {
-				cur_x++;	/* double space */
-				while (*++sp == ' ') ;
-				newl = 1;
-			} else
-				newl = 0;
-			word = sp;
-		}
-	}
-}
-
-/*
- * Print a button
- */
-void print_button(WINDOW * win, const char *label, int y, int x, int selected)
-{
-	int i, temp;
-
-	wmove(win, y, x);
-	wattrset(win, selected ? dlg.button_active.atr
-		 : dlg.button_inactive.atr);
-	waddstr(win, "<");
-	temp = strspn(label, " ");
-	label += temp;
-	wattrset(win, selected ? dlg.button_label_active.atr
-		 : dlg.button_label_inactive.atr);
-	for (i = 0; i < temp; i++)
-		waddch(win, ' ');
-	wattrset(win, selected ? dlg.button_key_active.atr
-		 : dlg.button_key_inactive.atr);
-	waddch(win, label[0]);
-	wattrset(win, selected ? dlg.button_label_active.atr
-		 : dlg.button_label_inactive.atr);
-	waddstr(win, (char *)label + 1);
-	wattrset(win, selected ? dlg.button_active.atr
-		 : dlg.button_inactive.atr);
-	waddstr(win, ">");
-	wmove(win, y, x + temp + 1);
-}
-
-/*
- * Draw a rectangular box with line drawing characters
- */
-void
-draw_box(WINDOW * win, int y, int x, int height, int width,
-	 chtype box, chtype border)
-{
-	int i, j;
-
-	wattrset(win, 0);
-	for (i = 0; i < height; i++) {
-		wmove(win, y + i, x);
-		for (j = 0; j < width; j++)
-			if (!i && !j)
-				waddch(win, border | ACS_ULCORNER);
-			else if (i == height - 1 && !j)
-				waddch(win, border | ACS_LLCORNER);
-			else if (!i && j == width - 1)
-				waddch(win, box | ACS_URCORNER);
-			else if (i == height - 1 && j == width - 1)
-				waddch(win, box | ACS_LRCORNER);
-			else if (!i)
-				waddch(win, border | ACS_HLINE);
-			else if (i == height - 1)
-				waddch(win, box | ACS_HLINE);
-			else if (!j)
-				waddch(win, border | ACS_VLINE);
-			else if (j == width - 1)
-				waddch(win, box | ACS_VLINE);
-			else
-				waddch(win, box | ' ');
-	}
-}
-
-/*
- * Draw shadows along the right and bottom edge to give a more 3D look
- * to the boxes
- */
-void draw_shadow(WINDOW * win, int y, int x, int height, int width)
-{
-	int i;
-
-	if (has_colors()) {	/* Whether terminal supports color? */
-		wattrset(win, dlg.shadow.atr);
-		wmove(win, y + height, x + 2);
-		for (i = 0; i < width; i++)
-			waddch(win, winch(win) & A_CHARTEXT);
-		for (i = y + 1; i < y + height + 1; i++) {
-			wmove(win, i, x + width);
-			waddch(win, winch(win) & A_CHARTEXT);
-			waddch(win, winch(win) & A_CHARTEXT);
-		}
-		wnoutrefresh(win);
-	}
-}
-
-/*
- *  Return the position of the first alphabetic character in a string.
- */
-int first_alpha(const char *string, const char *exempt)
-{
-	int i, in_paren = 0, c;
-
-	for (i = 0; i < strlen(string); i++) {
-		c = tolower(string[i]);
-
-		if (strchr("<[(", c))
-			++in_paren;
-		if (strchr(">])", c) && in_paren > 0)
-			--in_paren;
-
-		if ((!in_paren) && isalpha(c) && strchr(exempt, c) == 0)
-			return i;
-	}
-
-	return 0;
-}
-
-/*
- * ncurses uses ESC to detect escaped char sequences. This resutl in
- * a small timeout before ESC is actually delivered to the application.
- * lxdialog suggest <ESC> <ESC> which is correctly translated to two
- * times esc. But then we need to ignore the second esc to avoid stepping
- * out one menu too much. Filter away all escaped key sequences since
- * keypad(FALSE) turn off ncurses support for escape sequences - and thats
- * needed to make notimeout() do as expected.
- */
-int on_key_esc(WINDOW *win)
-{
-	int key;
-	int key2;
-	int key3;
-
-	nodelay(win, TRUE);
-	keypad(win, FALSE);
-	key = wgetch(win);
-	key2 = wgetch(win);
-	do {
-		key3 = wgetch(win);
-	} while (key3 != ERR);
-	nodelay(win, FALSE);
-	keypad(win, TRUE);
-	if (key == KEY_ESC && key2 == ERR)
-		return KEY_ESC;
-	else if (key != ERR && key != KEY_ESC && key2 == ERR)
-		ungetch(key);
-
-	return -1;
-}
-
-/* redraw screen in new size */
-int on_key_resize(void)
-{
-	dialog_clear();
-	return KEY_RESIZE;
-}
-
-struct dialog_list *item_cur;
-struct dialog_list item_nil;
-struct dialog_list *item_head;
-
-void item_reset(void)
-{
-	struct dialog_list *p, *next;
-
-	for (p = item_head; p; p = next) {
-		next = p->next;
-		free(p);
-	}
-	item_head = NULL;
-	item_cur = &item_nil;
-}
-
-void item_make(const char *fmt, ...)
-{
-	va_list ap;
-	struct dialog_list *p = malloc(sizeof(*p));
-
-	if (item_head)
-		item_cur->next = p;
-	else
-		item_head = p;
-	item_cur = p;
-	memset(p, 0, sizeof(*p));
-
-	va_start(ap, fmt);
-	vsnprintf(item_cur->node.str, sizeof(item_cur->node.str), fmt, ap);
-	va_end(ap);
-}
-
-void item_add_str(const char *fmt, ...)
-{
-	va_list ap;
-	size_t avail;
-
-	avail = sizeof(item_cur->node.str) - strlen(item_cur->node.str);
-
-	va_start(ap, fmt);
-	vsnprintf(item_cur->node.str + strlen(item_cur->node.str),
-		  avail, fmt, ap);
-	item_cur->node.str[sizeof(item_cur->node.str) - 1] = '\0';
-	va_end(ap);
-}
-
-void item_set_tag(char tag)
-{
-	item_cur->node.tag = tag;
-}
-void item_set_data(void *ptr)
-{
-	item_cur->node.data = ptr;
-}
-
-void item_set_selected(int val)
-{
-	item_cur->node.selected = val;
-}
-
-int item_activate_selected(void)
-{
-	item_foreach()
-		if (item_is_selected())
-			return 1;
-	return 0;
-}
-
-void *item_data(void)
-{
-	return item_cur->node.data;
-}
-
-char item_tag(void)
-{
-	return item_cur->node.tag;
-}
-
-int item_count(void)
-{
-	int n = 0;
-	struct dialog_list *p;
-
-	for (p = item_head; p; p = p->next)
-		n++;
-	return n;
-}
-
-void item_set(int n)
-{
-	int i = 0;
-	item_foreach()
-		if (i++ == n)
-			return;
-}
-
-int item_n(void)
-{
-	int n = 0;
-	struct dialog_list *p;
-
-	for (p = item_head; p; p = p->next) {
-		if (p == item_cur)
-			return n;
-		n++;
-	}
-	return 0;
-}
-
-const char *item_str(void)
-{
-	return item_cur->node.str;
-}
-
-int item_is_selected(void)
-{
-	return (item_cur->node.selected != 0);
-}
-
-int item_is_tag(char tag)
-{
-	return (item_cur->node.tag == tag);
-}
diff --git a/util/kconfig/lxdialog/yesno.c b/util/kconfig/lxdialog/yesno.c
deleted file mode 100644
index bcaac9b7ba..0000000000
--- a/util/kconfig/lxdialog/yesno.c
+++ /dev/null
@@ -1,101 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- *  yesno.c -- implements the yes/no box
- *
- *  ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk)
- *  MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com)
- */
-
-#include "dialog.h"
-
-/*
- * Display termination buttons
- */
-static void print_buttons(WINDOW * dialog, int height, int width, int selected)
-{
-	int x = width / 2 - 10;
-	int y = height - 2;
-
-	print_button(dialog, " Yes ", y, x, selected == 0);
-	print_button(dialog, "  No  ", y, x + 13, selected == 1);
-
-	wmove(dialog, y, x + 1 + 13 * selected);
-	wrefresh(dialog);
-}
-
-/*
- * Display a dialog box with two buttons - Yes and No
- */
-int dialog_yesno(const char *title, const char *prompt, int height, int width)
-{
-	int i, x, y, key = 0, button = 0;
-	WINDOW *dialog;
-
-do_resize:
-	if (getmaxy(stdscr) < (height + YESNO_HEIGTH_MIN))
-		return -ERRDISPLAYTOOSMALL;
-	if (getmaxx(stdscr) < (width + YESNO_WIDTH_MIN))
-		return -ERRDISPLAYTOOSMALL;
-
-	/* center dialog box on screen */
-	x = (getmaxx(stdscr) - width) / 2;
-	y = (getmaxy(stdscr) - height) / 2;
-
-	draw_shadow(stdscr, y, x, height, width);
-
-	dialog = newwin(height, width, y, x);
-	keypad(dialog, TRUE);
-
-	draw_box(dialog, 0, 0, height, width,
-		 dlg.dialog.atr, dlg.border.atr);
-	wattrset(dialog, dlg.border.atr);
-	mvwaddch(dialog, height - 3, 0, ACS_LTEE);
-	for (i = 0; i < width - 2; i++)
-		waddch(dialog, ACS_HLINE);
-	wattrset(dialog, dlg.dialog.atr);
-	waddch(dialog, ACS_RTEE);
-
-	print_title(dialog, title, width);
-
-	wattrset(dialog, dlg.dialog.atr);
-	print_autowrap(dialog, prompt, width - 2, 1, 3);
-
-	print_buttons(dialog, height, width, 0);
-
-	while (key != KEY_ESC) {
-		key = wgetch(dialog);
-		switch (key) {
-		case 'Y':
-		case 'y':
-			delwin(dialog);
-			return 0;
-		case 'N':
-		case 'n':
-			delwin(dialog);
-			return 1;
-
-		case TAB:
-		case KEY_LEFT:
-		case KEY_RIGHT:
-			button = ((key == KEY_LEFT ? --button : ++button) < 0) ? 1 : (button > 1 ? 0 : button);
-
-			print_buttons(dialog, height, width, button);
-			wrefresh(dialog);
-			break;
-		case ' ':
-		case '\n':
-			delwin(dialog);
-			return button;
-		case KEY_ESC:
-			key = on_key_esc(dialog);
-			break;
-		case KEY_RESIZE:
-			delwin(dialog);
-			on_key_resize();
-			goto do_resize;
-		}
-	}
-
-	delwin(dialog);
-	return key;		/* ESC pressed */
-}
diff --git a/util/kconfig/mconf-cfg.sh b/util/kconfig/mconf-cfg.sh
deleted file mode 100755
index c812872d7f..0000000000
--- a/util/kconfig/mconf-cfg.sh
+++ /dev/null
@@ -1,47 +0,0 @@
-#!/bin/sh
-# SPDX-License-Identifier: GPL-2.0
-
-PKG="ncursesw"
-PKG2="ncurses"
-
-if [ -n "$(command -v pkg-config)" ]; then
-	if pkg-config --exists $PKG; then
-		echo cflags=\"$(pkg-config --cflags $PKG)\"
-		echo libs=\"$(pkg-config --libs $PKG)\"
-		exit 0
-	fi
-
-	if pkg-config --exists $PKG2; then
-		echo cflags=\"$(pkg-config --cflags $PKG2)\"
-		echo libs=\"$(pkg-config --libs $PKG2)\"
-		exit 0
-	fi
-fi
-
-# Check the default paths in case pkg-config is not installed.
-# (Even if it is installed, some distributions such as openSUSE cannot
-# find ncurses by pkg-config.)
-if [ -f /usr/include/ncursesw/ncurses.h ]; then
-	echo cflags=\"-D_GNU_SOURCE -I/usr/include/ncursesw\"
-	echo libs=\"-lncursesw\"
-	exit 0
-fi
-
-if [ -f /usr/include/ncurses/ncurses.h ]; then
-	echo cflags=\"-D_GNU_SOURCE -I/usr/include/ncurses\"
-	echo libs=\"-lncurses\"
-	exit 0
-fi
-
-if [ -f /usr/include/ncurses.h ]; then
-	echo cflags=\"-D_GNU_SOURCE\"
-	echo libs=\"-lncurses\"
-	exit 0
-fi
-
-echo >&2 "*"
-echo >&2 "* Unable to find the ncurses package."
-echo >&2 "* Install ncurses (ncurses-devel or libncurses-dev"
-echo >&2 "* depending on your distribution)."
-echo >&2 "*"
-exit 1
diff --git a/util/kconfig/mconf.c b/util/kconfig/mconf.c
deleted file mode 100644
index 49c26ea9dd..0000000000
--- a/util/kconfig/mconf.c
+++ /dev/null
@@ -1,1039 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org>
- *
- * Introduced single menu mode (show all sub-menus in one large tree).
- * 2002-11-06 Petr Baudis <pasky@ucw.cz>
- *
- * i18n, 2005, Arnaldo Carvalho de Melo <acme@conectiva.com.br>
- */
-
-#include <ctype.h>
-#include <errno.h>
-#include <fcntl.h>
-#include <limits.h>
-#include <stdarg.h>
-#include <stdlib.h>
-#include <string.h>
-#include <signal.h>
-#include <unistd.h>
-
-#include "lkc.h"
-#include "lxdialog/dialog.h"
-
-static const char mconf_readme[] =
-"Overview\n"
-"--------\n"
-"This interface lets you select features and parameters for the build.\n"
-"Features can either be built-in, modularized, or ignored. Parameters\n"
-"must be entered in as decimal or hexadecimal numbers or text.\n"
-"\n"
-"Menu items beginning with following braces represent features that\n"
-"  [ ] can be built in or removed\n"
-"  < > can be built in, modularized or removed\n"
-"  { } can be built in or modularized (selected by other feature)\n"
-"  - - are selected by other feature,\n"
-"while *, M or whitespace inside braces means to build in, build as\n"
-"a module or to exclude the feature respectively.\n"
-"\n"
-"To change any of these features, highlight it with the cursor\n"
-"keys and press <Y> to build it in, <M> to make it a module or\n"
-"<N> to remove it.  You may also press the <Space Bar> to cycle\n"
-"through the available options (i.e. Y->N->M->Y).\n"
-"\n"
-"Some additional keyboard hints:\n"
-"\n"
-"Menus\n"
-"----------\n"
-"o  Use the Up/Down arrow keys (cursor keys) to highlight the item you\n"
-"   wish to change or the submenu you wish to select and press <Enter>.\n"
-"   Submenus are designated by \"--->\", empty ones by \"----\".\n"
-"\n"
-"   Shortcut: Press the option's highlighted letter (hotkey).\n"
-"             Pressing a hotkey more than once will sequence\n"
-"             through all visible items which use that hotkey.\n"
-"\n"
-"   You may also use the <PAGE UP> and <PAGE DOWN> keys to scroll\n"
-"   unseen options into view.\n"
-"\n"
-"o  To exit a menu use the cursor keys to highlight the <Exit> button\n"
-"   and press <ENTER>.\n"
-"\n"
-"   Shortcut: Press <ESC><ESC> or <E> or <X> if there is no hotkey\n"
-"             using those letters.  You may press a single <ESC>, but\n"
-"             there is a delayed response which you may find annoying.\n"
-"\n"
-"   Also, the <TAB> and cursor keys will cycle between <Select>,\n"
-"   <Exit>, <Help>, <Save>, and <Load>.\n"
-"\n"
-"o  To get help with an item, use the cursor keys to highlight <Help>\n"
-"   and press <ENTER>.\n"
-"\n"
-"   Shortcut: Press <H> or <?>.\n"
-"\n"
-"o  To toggle the display of hidden options, press <Z>.\n"
-"\n"
-"\n"
-"Radiolists  (Choice lists)\n"
-"-----------\n"
-"o  Use the cursor keys to select the option you wish to set and press\n"
-"   <S> or the <SPACE BAR>.\n"
-"\n"
-"   Shortcut: Press the first letter of the option you wish to set then\n"
-"             press <S> or <SPACE BAR>.\n"
-"\n"
-"o  To see available help for the item, use the cursor keys to highlight\n"
-"   <Help> and Press <ENTER>.\n"
-"\n"
-"   Shortcut: Press <H> or <?>.\n"
-"\n"
-"   Also, the <TAB> and cursor keys will cycle between <Select> and\n"
-"   <Help>\n"
-"\n"
-"\n"
-"Data Entry\n"
-"-----------\n"
-"o  Enter the requested information and press <ENTER>\n"
-"   If you are entering hexadecimal values, it is not necessary to\n"
-"   add the '0x' prefix to the entry.\n"
-"\n"
-"o  For help, use the <TAB> or cursor keys to highlight the help option\n"
-"   and press <ENTER>.  You can try <TAB><H> as well.\n"
-"\n"
-"\n"
-"Text Box    (Help Window)\n"
-"--------\n"
-"o  Use the cursor keys to scroll up/down/left/right.  The VI editor\n"
-"   keys h,j,k,l function here as do <u>, <d>, <SPACE BAR> and <B> for\n"
-"   those who are familiar with less and lynx.\n"
-"\n"
-"o  Press <E>, <X>, <q>, <Enter> or <Esc><Esc> to exit.\n"
-"\n"
-"\n"
-"Alternate Configuration Files\n"
-"-----------------------------\n"
-"Menuconfig supports the use of alternate configuration files for\n"
-"those who, for various reasons, find it necessary to switch\n"
-"between different configurations.\n"
-"\n"
-"The <Save> button will let you save the current configuration to\n"
-"a file of your choosing.  Use the <Load> button to load a previously\n"
-"saved alternate configuration.\n"
-"\n"
-"Even if you don't use alternate configuration files, but you find\n"
-"during a Menuconfig session that you have completely messed up your\n"
-"settings, you may use the <Load> button to restore your previously\n"
-"saved settings from \".config\" without restarting Menuconfig.\n"
-"\n"
-"Other information\n"
-"-----------------\n"
-"If you use Menuconfig in an XTERM window, make sure you have your\n"
-"$TERM variable set to point to an xterm definition which supports\n"
-"color.  Otherwise, Menuconfig will look rather bad.  Menuconfig will\n"
-"not display correctly in an RXVT window because rxvt displays only one\n"
-"intensity of color, bright.\n"
-"\n"
-"Menuconfig will display larger menus on screens or xterms which are\n"
-"set to display more than the standard 25 row by 80 column geometry.\n"
-"In order for this to work, the \"stty size\" command must be able to\n"
-"display the screen's current row and column geometry.  I STRONGLY\n"
-"RECOMMEND that you make sure you do NOT have the shell variables\n"
-"LINES and COLUMNS exported into your environment.  Some distributions\n"
-"export those variables via /etc/profile.  Some ncurses programs can\n"
-"become confused when those variables (LINES & COLUMNS) don't reflect\n"
-"the true screen size.\n"
-"\n"
-"Optional personality available\n"
-"------------------------------\n"
-"If you prefer to have all of the options listed in a single menu,\n"
-"rather than the default multimenu hierarchy, run the menuconfig with\n"
-"MENUCONFIG_MODE environment variable set to single_menu. Example:\n"
-"\n"
-"make MENUCONFIG_MODE=single_menu menuconfig\n"
-"\n"
-"<Enter> will then unroll the appropriate category, or enfold it if it\n"
-"is already unrolled.\n"
-"\n"
-"Note that this mode can eventually be a little more CPU expensive\n"
-"(especially with a larger number of unrolled categories) than the\n"
-"default mode.\n"
-"\n"
-"Different color themes available\n"
-"--------------------------------\n"
-"It is possible to select different color themes using the variable\n"
-"MENUCONFIG_COLOR. To select a theme use:\n"
-"\n"
-"make MENUCONFIG_COLOR=<theme> menuconfig\n"
-"\n"
-"Available themes are\n"
-" mono       => selects colors suitable for monochrome displays\n"
-" blackbg    => selects a color scheme with black background\n"
-" classic    => theme with blue background. The classic look\n"
-" bluetitle  => an LCD friendly version of classic. (default)\n"
-"\n",
-menu_instructions[] =
-	"Arrow keys navigate the menu.  "
-	"<Enter> selects submenus ---> (or empty submenus ----).  "
-	"Highlighted letters are hotkeys.  "
-	"Pressing <Y> includes, <N> excludes, <M> modularizes features.  "
-	"Press <Esc><Esc> to exit, <?> for Help, </> for Search.  "
-	"Legend: [*] built-in  [ ] excluded  <M> module  < > module capable",
-radiolist_instructions[] =
-	"Use the arrow keys to navigate this window or "
-	"press the hotkey of the item you wish to select "
-	"followed by the <SPACE BAR>. "
-	"Press <?> for additional information about this option.",
-inputbox_instructions_int[] =
-	"Please enter a decimal value. "
-	"Fractions will not be accepted.  "
-	"Use the <TAB> key to move from the input field to the buttons below it.",
-inputbox_instructions_hex[] =
-	"Please enter a hexadecimal value. "
-	"Use the <TAB> key to move from the input field to the buttons below it.",
-inputbox_instructions_string[] =
-	"Please enter a string value. "
-	"Use the <TAB> key to move from the input field to the buttons below it.",
-setmod_text[] =
-	"This feature depends on another which has been configured as a module.\n"
-	"As a result, this feature will be built as a module.",
-load_config_text[] =
-	"Enter the name of the configuration file you wish to load.  "
-	"Accept the name shown to restore the configuration you "
-	"last retrieved.  Leave blank to abort.",
-load_config_help[] =
-	"\n"
-	"For various reasons, one may wish to keep several different\n"
-	"configurations available on a single machine.\n"
-	"\n"
-	"If you have saved a previous configuration in a file other than the\n"
-	"default one, entering its name here will allow you to modify that\n"
-	"configuration.\n"
-	"\n"
-	"If you are uncertain, then you have probably never used alternate\n"
-	"configuration files. You should therefore leave this blank to abort.\n",
-save_config_text[] =
-	"Enter a filename to which this configuration should be saved "
-	"as an alternate.  Leave blank to abort.",
-save_config_help[] =
-	"\n"
-	"For various reasons, one may wish to keep different configurations\n"
-	"available on a single machine.\n"
-	"\n"
-	"Entering a file name here will allow you to later retrieve, modify\n"
-	"and use the current configuration as an alternate to whatever\n"
-	"configuration options you have selected at that time.\n"
-	"\n"
-	"If you are uncertain what all this means then you should probably\n"
-	"leave this blank.\n",
-search_help[] =
-	"\n"
-	"Search for symbols and display their relations.\n"
-	"Regular expressions are allowed.\n"
-	"Example: search for \"^FOO\"\n"
-	"Result:\n"
-	"-----------------------------------------------------------------\n"
-	"Symbol: FOO [=m]\n"
-	"Type  : tristate\n"
-	"Prompt: Foo bus is used to drive the bar HW\n"
-	"  Location:\n"
-	"    -> Bus options (PCI, PCMCIA, EISA, ISA)\n"
-	"      -> PCI support (PCI [=y])\n"
-	"(1)     -> PCI access mode (<choice> [=y])\n"
-	"  Defined at drivers/pci/Kconfig:47\n"
-	"  Depends on: X86_LOCAL_APIC && X86_IO_APIC || IA64\n"
-	"  Selects: LIBCRC32\n"
-	"  Selected by: BAR [=n]\n"
-	"-----------------------------------------------------------------\n"
-	"o The line 'Type:' shows the type of the configuration option for\n"
-	"  this symbol (bool, tristate, string, ...)\n"
-	"o The line 'Prompt:' shows the text used in the menu structure for\n"
-	"  this symbol\n"
-	"o The 'Defined at' line tells at what file / line number the symbol\n"
-	"  is defined\n"
-	"o The 'Depends on:' line tells what symbols need to be defined for\n"
-	"  this symbol to be visible in the menu (selectable)\n"
-	"o The 'Location:' lines tells where in the menu structure this symbol\n"
-	"  is located\n"
-	"    A location followed by a [=y] indicates that this is a\n"
-	"    selectable menu item - and the current value is displayed inside\n"
-	"    brackets.\n"
-	"    Press the key in the (#) prefix to jump directly to that\n"
-	"    location. You will be returned to the current search results\n"
-	"    after exiting this new menu.\n"
-	"o The 'Selects:' line tells what symbols will be automatically\n"
-	"  selected if this symbol is selected (y or m)\n"
-	"o The 'Selected by' line tells what symbol has selected this symbol\n"
-	"\n"
-	"Only relevant lines are shown.\n"
-	"\n\n"
-	"Search examples:\n"
-	"Examples: USB	=> find all symbols containing USB\n"
-	"          ^USB => find all symbols starting with USB\n"
-	"          USB$ => find all symbols ending with USB\n"
-	"\n";
-
-static int indent;
-static struct menu *current_menu;
-static int child_count;
-static int single_menu_mode;
-static int show_all_options;
-static int save_and_exit;
-static int silent;
-
-static void conf(struct menu *menu, struct menu *active_menu);
-static void conf_choice(struct menu *menu);
-static void conf_string(struct menu *menu);
-static void conf_load(void);
-static void conf_save(void);
-static int show_textbox_ext(const char *title, char *text, int r, int c,
-			    int *keys, int *vscroll, int *hscroll,
-			    update_text_fn update_text, void *data);
-static void show_textbox(const char *title, const char *text, int r, int c);
-static void show_helptext(const char *title, const char *text);
-static void show_help(struct menu *menu);
-
-static char filename[PATH_MAX+1];
-static void set_config_filename(const char *config_filename)
-{
-	static char menu_backtitle[PATH_MAX+128];
-	int size;
-
-	size = snprintf(menu_backtitle, sizeof(menu_backtitle),
-			"%s - %s", config_filename, rootmenu.prompt->text);
-	if (size >= sizeof(menu_backtitle))
-		menu_backtitle[sizeof(menu_backtitle)-1] = '\0';
-	set_dialog_backtitle(menu_backtitle);
-
-	size = snprintf(filename, sizeof(filename), "%s", config_filename);
-	if (size >= sizeof(filename))
-		filename[sizeof(filename)-1] = '\0';
-}
-
-struct subtitle_part {
-	struct list_head entries;
-	const char *text;
-};
-static LIST_HEAD(trail);
-
-static struct subtitle_list *subtitles;
-static void set_subtitle(void)
-{
-	struct subtitle_part *sp;
-	struct subtitle_list *pos, *tmp;
-
-	for (pos = subtitles; pos != NULL; pos = tmp) {
-		tmp = pos->next;
-		free(pos);
-	}
-
-	subtitles = NULL;
-	list_for_each_entry(sp, &trail, entries) {
-		if (sp->text) {
-			if (pos) {
-				pos->next = xcalloc(1, sizeof(*pos));
-				pos = pos->next;
-			} else {
-				subtitles = pos = xcalloc(1, sizeof(*pos));
-			}
-			pos->text = sp->text;
-		}
-	}
-
-	set_dialog_subtitles(subtitles);
-}
-
-static void reset_subtitle(void)
-{
-	struct subtitle_list *pos, *tmp;
-
-	for (pos = subtitles; pos != NULL; pos = tmp) {
-		tmp = pos->next;
-		free(pos);
-	}
-	subtitles = NULL;
-	set_dialog_subtitles(subtitles);
-}
-
-struct search_data {
-	struct list_head *head;
-	struct menu **targets;
-	int *keys;
-};
-
-static void update_text(char *buf, size_t start, size_t end, void *_data)
-{
-	struct search_data *data = _data;
-	struct jump_key *pos;
-	int k = 0;
-
-	list_for_each_entry(pos, data->head, entries) {
-		if (pos->offset >= start && pos->offset < end) {
-			char header[4];
-
-			if (k < JUMP_NB) {
-				int key = '0' + (pos->index % JUMP_NB) + 1;
-
-				sprintf(header, "(%c)", key);
-				data->keys[k] = key;
-				data->targets[k] = pos->target;
-				k++;
-			} else {
-				sprintf(header, "   ");
-			}
-
-			memcpy(buf + pos->offset, header, sizeof(header) - 1);
-		}
-	}
-	data->keys[k] = 0;
-}
-
-static void search_conf(void)
-{
-	struct symbol **sym_arr;
-	struct gstr res;
-	struct gstr title;
-	char *dialog_input;
-	int dres, vscroll = 0, hscroll = 0;
-	bool again;
-	struct gstr sttext;
-	struct subtitle_part stpart;
-
-	title = str_new();
-	str_printf( &title, "Enter (sub)string or regexp to search for "
-			      "(with or without \"%s\")", CONFIG_);
-
-again:
-	dialog_clear();
-	dres = dialog_inputbox("Search Configuration Parameter",
-			      str_get(&title),
-			      10, 75, "");
-	switch (dres) {
-	case 0:
-		break;
-	case 1:
-		show_helptext("Search Configuration", search_help);
-		goto again;
-	default:
-		str_free(&title);
-		return;
-	}
-
-	/* strip the prefix if necessary */
-	dialog_input = dialog_input_result;
-	if (strncasecmp(dialog_input_result, CONFIG_, strlen(CONFIG_)) == 0)
-		dialog_input += strlen(CONFIG_);
-
-	sttext = str_new();
-	str_printf(&sttext, "Search (%s)", dialog_input_result);
-	stpart.text = str_get(&sttext);
-	list_add_tail(&stpart.entries, &trail);
-
-	sym_arr = sym_re_search(dialog_input);
-	do {
-		LIST_HEAD(head);
-		struct menu *targets[JUMP_NB];
-		int keys[JUMP_NB + 1], i;
-		struct search_data data = {
-			.head = &head,
-			.targets = targets,
-			.keys = keys,
-		};
-		struct jump_key *pos, *tmp;
-
-		res = get_relations_str(sym_arr, &head);
-		set_subtitle();
-		dres = show_textbox_ext("Search Results", (char *)
-					str_get(&res), 0, 0, keys, &vscroll,
-					&hscroll, &update_text, (void *)
-					&data);
-		again = false;
-		for (i = 0; i < JUMP_NB && keys[i]; i++)
-			if (dres == keys[i]) {
-				conf(targets[i]->parent, targets[i]);
-				again = true;
-			}
-		str_free(&res);
-		list_for_each_entry_safe(pos, tmp, &head, entries)
-			free(pos);
-	} while (again);
-	free(sym_arr);
-	str_free(&title);
-	list_del(trail.prev);
-	str_free(&sttext);
-}
-
-static void build_conf(struct menu *menu)
-{
-	struct symbol *sym;
-	struct property *prop;
-	struct menu *child;
-	int type, tmp, doint = 2;
-	tristate val;
-	char ch;
-	bool visible;
-
-	/*
-	 * note: menu_is_visible() has side effect that it will
-	 * recalc the value of the symbol.
-	 */
-	visible = menu_is_visible(menu);
-	if (show_all_options && !menu_has_prompt(menu))
-		return;
-	else if (!show_all_options && !visible)
-		return;
-
-	sym = menu->sym;
-	prop = menu->prompt;
-	if (!sym) {
-		if (prop && menu != current_menu) {
-			const char *prompt = menu_get_prompt(menu);
-			switch (prop->type) {
-			case P_MENU:
-				child_count++;
-				if (single_menu_mode) {
-					item_make("%s%*c%s",
-						  menu->data ? "-->" : "++>",
-						  indent + 1, ' ', prompt);
-				} else
-					item_make("   %*c%s  %s",
-						  indent + 1, ' ', prompt,
-						  menu_is_empty(menu) ? "----" : "--->");
-				item_set_tag('m');
-				item_set_data(menu);
-				if (single_menu_mode && menu->data)
-					goto conf_childs;
-				return;
-			case P_COMMENT:
-				if (prompt) {
-					child_count++;
-					item_make("   %*c*** %s ***", indent + 1, ' ', prompt);
-					item_set_tag(':');
-					item_set_data(menu);
-				}
-				break;
-			default:
-				if (prompt) {
-					child_count++;
-					item_make("---%*c%s", indent + 1, ' ', prompt);
-					item_set_tag(':');
-					item_set_data(menu);
-				}
-			}
-		} else
-			doint = 0;
-		goto conf_childs;
-	}
-
-	type = sym_get_type(sym);
-	if (sym_is_choice(sym)) {
-		struct symbol *def_sym = sym_get_choice_value(sym);
-		struct menu *def_menu = NULL;
-
-		child_count++;
-		for (child = menu->list; child; child = child->next) {
-			if (menu_is_visible(child) && child->sym == def_sym)
-				def_menu = child;
-		}
-
-		val = sym_get_tristate_value(sym);
-		if (sym_is_changeable(sym)) {
-			switch (type) {
-			case S_BOOLEAN:
-				item_make("[%c]", val == no ? ' ' : '*');
-				break;
-			case S_TRISTATE:
-				switch (val) {
-				case yes: ch = '*'; break;
-				case mod: ch = 'M'; break;
-				default:  ch = ' '; break;
-				}
-				item_make("<%c>", ch);
-				break;
-			}
-			item_set_tag('t');
-			item_set_data(menu);
-		} else {
-			item_make("   ");
-			item_set_tag(def_menu ? 't' : ':');
-			item_set_data(menu);
-		}
-
-		item_add_str("%*c%s", indent + 1, ' ', menu_get_prompt(menu));
-		if (val == yes) {
-			if (def_menu) {
-				item_add_str(" (%s)", menu_get_prompt(def_menu));
-				item_add_str("  --->");
-				if (def_menu->list) {
-					indent += 2;
-					build_conf(def_menu);
-					indent -= 2;
-				}
-			}
-			return;
-		}
-	} else {
-		if (menu == current_menu) {
-			item_make("---%*c%s", indent + 1, ' ', menu_get_prompt(menu));
-			item_set_tag(':');
-			item_set_data(menu);
-			goto conf_childs;
-		}
-		child_count++;
-		val = sym_get_tristate_value(sym);
-		if (sym_is_choice_value(sym) && val == yes) {
-			item_make("   ");
-			item_set_tag(':');
-			item_set_data(menu);
-		} else {
-			switch (type) {
-			case S_BOOLEAN:
-				if (sym_is_changeable(sym))
-					item_make("[%c]", val == no ? ' ' : '*');
-				else
-					item_make("-%c-", val == no ? ' ' : '*');
-				item_set_tag('t');
-				item_set_data(menu);
-				break;
-			case S_TRISTATE:
-				switch (val) {
-				case yes: ch = '*'; break;
-				case mod: ch = 'M'; break;
-				default:  ch = ' '; break;
-				}
-				if (sym_is_changeable(sym)) {
-					if (sym->rev_dep.tri == mod)
-						item_make("{%c}", ch);
-					else
-						item_make("<%c>", ch);
-				} else
-					item_make("-%c-", ch);
-				item_set_tag('t');
-				item_set_data(menu);
-				break;
-			default:
-				tmp = 2 + strlen(sym_get_string_value(sym)); /* () = 2 */
-				item_make("(%s)", sym_get_string_value(sym));
-				tmp = indent - tmp + 4;
-				if (tmp < 0)
-					tmp = 0;
-				item_add_str("%*c%s%s", tmp, ' ', menu_get_prompt(menu),
-					     (sym_has_value(sym) || !sym_is_changeable(sym)) ?
-					     "" : " (NEW)");
-				item_set_tag('s');
-				item_set_data(menu);
-				goto conf_childs;
-			}
-		}
-		item_add_str("%*c%s%s", indent + 1, ' ', menu_get_prompt(menu),
-			  (sym_has_value(sym) || !sym_is_changeable(sym)) ?
-			  "" : " (NEW)");
-		if (menu->prompt->type == P_MENU) {
-			item_add_str("  %s", menu_is_empty(menu) ? "----" : "--->");
-			return;
-		}
-	}
-
-conf_childs:
-	indent += doint;
-	for (child = menu->list; child; child = child->next)
-		build_conf(child);
-	indent -= doint;
-}
-
-static void conf(struct menu *menu, struct menu *active_menu)
-{
-	struct menu *submenu;
-	const char *prompt = menu_get_prompt(menu);
-	struct subtitle_part stpart;
-	struct symbol *sym;
-	int res;
-	int s_scroll = 0;
-
-	if (menu != &rootmenu)
-		stpart.text = menu_get_prompt(menu);
-	else
-		stpart.text = NULL;
-	list_add_tail(&stpart.entries, &trail);
-
-	while (1) {
-		item_reset();
-		current_menu = menu;
-		build_conf(menu);
-		if (!child_count)
-			break;
-		set_subtitle();
-		dialog_clear();
-		res = dialog_menu(prompt ? prompt : "Main Menu",
-				  menu_instructions,
-				  active_menu, &s_scroll);
-		if (res == 1 || res == KEY_ESC || res == -ERRDISPLAYTOOSMALL)
-			break;
-		if (item_count() != 0) {
-			if (!item_activate_selected())
-				continue;
-			if (!item_tag())
-				continue;
-		}
-		submenu = item_data();
-		active_menu = item_data();
-		if (submenu)
-			sym = submenu->sym;
-		else
-			sym = NULL;
-
-		switch (res) {
-		case 0:
-			switch (item_tag()) {
-			case 'm':
-				if (single_menu_mode)
-					submenu->data = (void *) (long) !submenu->data;
-				else
-					conf(submenu, NULL);
-				break;
-			case 't':
-				if (sym_is_choice(sym) && sym_get_tristate_value(sym) == yes)
-					conf_choice(submenu);
-				else if (submenu->prompt->type == P_MENU)
-					conf(submenu, NULL);
-				break;
-			case 's':
-				conf_string(submenu);
-				break;
-			}
-			break;
-		case 2:
-			if (sym)
-				show_help(submenu);
-			else {
-				reset_subtitle();
-				show_helptext("README", mconf_readme);
-			}
-			break;
-		case 3:
-			reset_subtitle();
-			conf_save();
-			break;
-		case 4:
-			reset_subtitle();
-			conf_load();
-			break;
-		case 5:
-			if (item_is_tag('t')) {
-				if (sym_set_tristate_value(sym, yes))
-					break;
-				if (sym_set_tristate_value(sym, mod))
-					show_textbox(NULL, setmod_text, 6, 74);
-			}
-			break;
-		case 6:
-			if (item_is_tag('t'))
-				sym_set_tristate_value(sym, no);
-			break;
-		case 7:
-			if (item_is_tag('t'))
-				sym_set_tristate_value(sym, mod);
-			break;
-		case 8:
-			if (item_is_tag('t'))
-				sym_toggle_tristate_value(sym);
-			else if (item_is_tag('m'))
-				conf(submenu, NULL);
-			break;
-		case 9:
-			search_conf();
-			break;
-		case 10:
-			show_all_options = !show_all_options;
-			break;
-		}
-	}
-
-	list_del(trail.prev);
-}
-
-static int show_textbox_ext(const char *title, char *text, int r, int c, int
-			    *keys, int *vscroll, int *hscroll, update_text_fn
-			    update_text, void *data)
-{
-	dialog_clear();
-	return dialog_textbox(title, text, r, c, keys, vscroll, hscroll,
-			      update_text, data);
-}
-
-static void show_textbox(const char *title, const char *text, int r, int c)
-{
-	show_textbox_ext(title, (char *) text, r, c, (int []) {0}, NULL, NULL,
-			 NULL, NULL);
-}
-
-static void show_helptext(const char *title, const char *text)
-{
-	show_textbox(title, text, 0, 0);
-}
-
-static void conf_message_callback(const char *s)
-{
-	if (save_and_exit) {
-		if (!silent)
-			printf("%s", s);
-	} else {
-		show_textbox(NULL, s, 6, 60);
-	}
-}
-
-static void show_help(struct menu *menu)
-{
-	struct gstr help = str_new();
-
-	help.max_width = getmaxx(stdscr) - 10;
-	menu_get_ext_help(menu, &help);
-
-	show_helptext(menu_get_prompt(menu), str_get(&help));
-	str_free(&help);
-}
-
-static void conf_choice(struct menu *menu)
-{
-	const char *prompt = menu_get_prompt(menu);
-	struct menu *child;
-	struct symbol *active;
-
-	active = sym_get_choice_value(menu->sym);
-	while (1) {
-		int res;
-		int selected;
-		item_reset();
-
-		current_menu = menu;
-		for (child = menu->list; child; child = child->next) {
-			if (!menu_is_visible(child))
-				continue;
-			if (child->sym)
-				item_make("%s", menu_get_prompt(child));
-			else {
-				item_make("*** %s ***", menu_get_prompt(child));
-				item_set_tag(':');
-			}
-			item_set_data(child);
-			if (child->sym == active)
-				item_set_selected(1);
-			if (child->sym == sym_get_choice_value(menu->sym))
-				item_set_tag('X');
-		}
-		dialog_clear();
-		res = dialog_checklist(prompt ? prompt : "Main Menu",
-					radiolist_instructions,
-					MENUBOX_HEIGTH_MIN,
-					MENUBOX_WIDTH_MIN,
-					CHECKLIST_HEIGTH_MIN);
-		selected = item_activate_selected();
-		switch (res) {
-		case 0:
-			if (selected) {
-				child = item_data();
-				if (!child->sym)
-					break;
-
-				sym_set_tristate_value(child->sym, yes);
-			}
-			return;
-		case 1:
-			if (selected) {
-				child = item_data();
-				show_help(child);
-				active = child->sym;
-			} else
-				show_help(menu);
-			break;
-		case KEY_ESC:
-			return;
-		case -ERRDISPLAYTOOSMALL:
-			return;
-		}
-	}
-}
-
-static void conf_string(struct menu *menu)
-{
-	const char *prompt = menu_get_prompt(menu);
-
-	while (1) {
-		int res;
-		const char *heading;
-
-		switch (sym_get_type(menu->sym)) {
-		case S_INT:
-			heading = inputbox_instructions_int;
-			break;
-		case S_HEX:
-			heading = inputbox_instructions_hex;
-			break;
-		case S_STRING:
-			heading = inputbox_instructions_string;
-			break;
-		default:
-			heading = "Internal mconf error!";
-		}
-		dialog_clear();
-		res = dialog_inputbox(prompt ? prompt : "Main Menu",
-				      heading, 10, 75,
-				      sym_get_string_value(menu->sym));
-		switch (res) {
-		case 0:
-			if (sym_set_string_value(menu->sym, dialog_input_result))
-				return;
-			show_textbox(NULL, "You have made an invalid entry.", 5, 43);
-			break;
-		case 1:
-			show_help(menu);
-			break;
-		case KEY_ESC:
-			return;
-		}
-	}
-}
-
-static void conf_load(void)
-{
-
-	while (1) {
-		int res;
-		dialog_clear();
-		res = dialog_inputbox(NULL, load_config_text,
-				      11, 55, filename);
-		switch(res) {
-		case 0:
-			if (!dialog_input_result[0])
-				return;
-			if (!conf_read(dialog_input_result)) {
-				set_config_filename(dialog_input_result);
-				sym_set_change_count(1);
-				return;
-			}
-			show_textbox(NULL, "File does not exist!", 5, 38);
-			break;
-		case 1:
-			show_helptext("Load Alternate Configuration", load_config_help);
-			break;
-		case KEY_ESC:
-			return;
-		}
-	}
-}
-
-static void conf_save(void)
-{
-	while (1) {
-		int res;
-		dialog_clear();
-		res = dialog_inputbox(NULL, save_config_text,
-				      11, 55, filename);
-		switch(res) {
-		case 0:
-			if (!dialog_input_result[0])
-				return;
-			if (!conf_write(dialog_input_result)) {
-				set_config_filename(dialog_input_result);
-				return;
-			}
-			show_textbox(NULL, "Can't create file!", 5, 60);
-			break;
-		case 1:
-			show_helptext("Save Alternate Configuration", save_config_help);
-			break;
-		case KEY_ESC:
-			return;
-		}
-	}
-}
-
-static int handle_exit(void)
-{
-	int res;
-
-	save_and_exit = 1;
-	reset_subtitle();
-	dialog_clear();
-	if (conf_get_changed())
-		res = dialog_yesno(NULL,
-				   "Do you wish to save your new configuration?\n"
-				     "(Press <ESC><ESC> to continue kernel configuration.)",
-				   6, 60);
-	else
-		res = -1;
-
-	end_dialog(saved_x, saved_y);
-
-	switch (res) {
-	case 0:
-		if (conf_write(filename)) {
-			fprintf(stderr, "\n\n"
-					  "Error while writing of the configuration.\n"
-					  "Your configuration changes were NOT saved."
-					  "\n\n");
-			return 1;
-		}
-		conf_write_autoconf(0);
-		/* fall through */
-	case -1:
-		if (!silent)
-			printf("\n\n"
-				 "*** End of the configuration.\n"
-				 "*** Execute 'make' to start the build or try 'make help'."
-				 "\n\n");
-		res = 0;
-		break;
-	default:
-		if (!silent)
-			fprintf(stderr, "\n\n"
-					  "Your configuration changes were NOT saved."
-					  "\n\n");
-		if (res != KEY_ESC)
-			res = 0;
-	}
-
-	return res;
-}
-
-static void sig_handler(int signo)
-{
-	exit(handle_exit());
-}
-
-int main(int ac, char **av)
-{
-	char *mode;
-	int res;
-
-	signal(SIGINT, sig_handler);
-
-	if (ac > 1 && strcmp(av[1], "-s") == 0) {
-		silent = 1;
-		/* Silence conf_read() until the real callback is set up */
-		conf_set_message_callback(NULL);
-		av++;
-	}
-	conf_parse(av[1]);
-	conf_read(NULL);
-
-	mode = getenv("MENUCONFIG_MODE");
-	if (mode) {
-		if (!strcasecmp(mode, "single_menu"))
-			single_menu_mode = 1;
-	}
-
-	if (init_dialog(NULL)) {
-		fprintf(stderr, "Your display is too small to run Menuconfig!\n");
-		fprintf(stderr, "It must be at least 19 lines by 80 columns.\n");
-		return 1;
-	}
-
-	set_config_filename(conf_get_configname());
-	conf_set_message_callback(conf_message_callback);
-	do {
-		conf(&rootmenu, NULL);
-		res = handle_exit();
-	} while (res == KEY_ESC);
-
-	return res;
-}
diff --git a/util/kconfig/menu.c b/util/kconfig/menu.c
deleted file mode 100644
index d9d1646985..0000000000
--- a/util/kconfig/menu.c
+++ /dev/null
@@ -1,867 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org>
- */
-
-#include <ctype.h>
-#include <stdarg.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "lkc.h"
-
-static const char nohelp_text[] = "There is no help available for this option.";
-
-struct menu rootmenu;
-static struct menu **last_entry_ptr;
-
-struct file *file_list;
-struct file *current_file;
-
-void menu_warn(struct menu *menu, const char *fmt, ...)
-{
-	va_list ap;
-	va_start(ap, fmt);
-	fprintf(stderr, "%s:%d:warning: ", menu->file->name, menu->lineno);
-	vfprintf(stderr, fmt, ap);
-	fprintf(stderr, "\n");
-	va_end(ap);
-}
-
-static void prop_warn(struct property *prop, const char *fmt, ...)
-{
-	va_list ap;
-	va_start(ap, fmt);
-	fprintf(stderr, "%s:%d:warning: ", prop->file->name, prop->lineno);
-	vfprintf(stderr, fmt, ap);
-	fprintf(stderr, "\n");
-	va_end(ap);
-}
-
-void _menu_init(void)
-{
-	current_entry = current_menu = &rootmenu;
-	last_entry_ptr = &rootmenu.list;
-}
-
-void menu_add_entry(struct symbol *sym)
-{
-	struct menu *menu;
-
-	menu = xmalloc(sizeof(*menu));
-	memset(menu, 0, sizeof(*menu));
-	menu->sym = sym;
-	menu->parent = current_menu;
-	menu->file = current_file;
-	menu->lineno = zconf_lineno();
-
-	*last_entry_ptr = menu;
-	last_entry_ptr = &menu->next;
-	current_entry = menu;
-	if (sym)
-		menu_add_symbol(P_SYMBOL, sym, NULL);
-}
-
-struct menu *menu_add_menu(void)
-{
-	last_entry_ptr = &current_entry->list;
-	return current_menu = current_entry;
-}
-
-void menu_end_menu(void)
-{
-	last_entry_ptr = &current_menu->next;
-	current_menu = current_menu->parent;
-}
-
-/*
- * Rewrites 'm' to 'm' && MODULES, so that it evaluates to 'n' when running
- * without modules
- */
-static struct expr *rewrite_m(struct expr *e)
-{
-	if (!e)
-		return e;
-
-	switch (e->type) {
-	case E_NOT:
-		e->left.expr = rewrite_m(e->left.expr);
-		break;
-	case E_OR:
-	case E_AND:
-		e->left.expr = rewrite_m(e->left.expr);
-		e->right.expr = rewrite_m(e->right.expr);
-		break;
-	case E_SYMBOL:
-		/* change 'm' into 'm' && MODULES */
-		if (e->left.sym == &symbol_mod)
-			return expr_alloc_and(e, expr_alloc_symbol(modules_sym));
-		break;
-	default:
-		break;
-	}
-	return e;
-}
-
-void menu_add_dep(struct expr *dep)
-{
-	current_entry->dep = expr_alloc_and(current_entry->dep, dep);
-}
-
-void menu_set_type(int type)
-{
-	struct symbol *sym = current_entry->sym;
-
-	if (sym->type == type)
-		return;
-	if (sym->type == S_UNKNOWN) {
-		sym->type = type;
-		return;
-	}
-	menu_warn(current_entry,
-		"ignoring type redefinition of '%s' from '%s' to '%s'",
-		sym->name ? sym->name : "<choice>",
-		sym_type_name(sym->type), sym_type_name(type));
-}
-
-static struct property *menu_add_prop(enum prop_type type, char *prompt, struct expr *expr, struct expr *dep)
-{
-	struct property *prop = prop_alloc(type, current_entry->sym);
-
-	prop->menu = current_entry;
-	prop->expr = expr;
-	prop->visible.expr = dep;
-
-	if (prompt) {
-		if (isspace(*prompt)) {
-			prop_warn(prop, "leading whitespace ignored");
-			while (isspace(*prompt))
-				prompt++;
-		}
-		if (current_entry->prompt && current_entry != &rootmenu)
-			prop_warn(prop, "prompt redefined");
-
-		/* Apply all upper menus' visibilities to actual prompts. */
-		if(type == P_PROMPT) {
-			struct menu *menu = current_entry;
-
-			while ((menu = menu->parent) != NULL) {
-				struct expr *dup_expr;
-
-				if (!menu->visibility)
-					continue;
-				/*
-				 * Do not add a reference to the
-				 * menu's visibility expression but
-				 * use a copy of it.  Otherwise the
-				 * expression reduction functions
-				 * will modify expressions that have
-				 * multiple references which can
-				 * cause unwanted side effects.
-				 */
-				dup_expr = expr_copy(menu->visibility);
-
-				prop->visible.expr
-					= expr_alloc_and(prop->visible.expr,
-							 dup_expr);
-			}
-		}
-
-		current_entry->prompt = prop;
-	}
-	prop->text = prompt;
-
-	return prop;
-}
-
-struct property *menu_add_prompt(enum prop_type type, char *prompt, struct expr *dep)
-{
-	return menu_add_prop(type, prompt, NULL, dep);
-}
-
-void menu_add_visibility(struct expr *expr)
-{
-	current_entry->visibility = expr_alloc_and(current_entry->visibility,
-	    expr);
-}
-
-void menu_add_expr(enum prop_type type, struct expr *expr, struct expr *dep)
-{
-	menu_add_prop(type, NULL, expr, dep);
-}
-
-void menu_add_symbol(enum prop_type type, struct symbol *sym, struct expr *dep)
-{
-	menu_add_prop(type, NULL, expr_alloc_symbol(sym), dep);
-}
-
-void menu_add_option_modules(void)
-{
-	if (modules_sym)
-		zconf_error("symbol '%s' redefines option 'modules' already defined by symbol '%s'",
-			    current_entry->sym->name, modules_sym->name);
-	modules_sym = current_entry->sym;
-}
-
-void menu_add_option_defconfig_list(void)
-{
-	if (!sym_defconfig_list)
-		sym_defconfig_list = current_entry->sym;
-	else if (sym_defconfig_list != current_entry->sym)
-		zconf_error("trying to redefine defconfig symbol");
-	sym_defconfig_list->flags |= SYMBOL_NO_WRITE;
-}
-
-void menu_add_option_allnoconfig_y(void)
-{
-	current_entry->sym->flags |= SYMBOL_ALLNOCONFIG_Y;
-}
-
-static int menu_validate_number(struct symbol *sym, struct symbol *sym2)
-{
-	return sym2->type == S_INT || sym2->type == S_HEX ||
-	       (sym2->type == S_UNKNOWN && sym_string_valid(sym, sym2->name));
-}
-
-static void sym_check_prop(struct symbol *sym)
-{
-	struct property *prop;
-	struct symbol *sym2;
-	char *use;
-
-	for (prop = sym->prop; prop; prop = prop->next) {
-		switch (prop->type) {
-		case P_DEFAULT:
-			if ((sym->type == S_STRING || sym->type == S_INT || sym->type == S_HEX) &&
-			    prop->expr->type != E_SYMBOL)
-				prop_warn(prop,
-				    "default for config symbol '%s'"
-				    " must be a single symbol", sym->name);
-			if (prop->expr->type != E_SYMBOL)
-				break;
-			sym2 = prop_get_symbol(prop);
-			if (sym->type == S_HEX || sym->type == S_INT) {
-				if (!menu_validate_number(sym, sym2))
-					prop_warn(prop,
-					    "'%s': number is invalid",
-					    sym->name);
-			}
-			if (sym_is_choice(sym)) {
-				struct property *choice_prop =
-					sym_get_choice_prop(sym2);
-
-				if (!choice_prop ||
-				    prop_get_symbol(choice_prop) != sym)
-					prop_warn(prop,
-						  "choice default symbol '%s' is not contained in the choice",
-						  sym2->name);
-			}
-			break;
-		case P_SELECT:
-		case P_IMPLY:
-			use = prop->type == P_SELECT ? "select" : "imply";
-			sym2 = prop_get_symbol(prop);
-			if (sym->type != S_BOOLEAN && sym->type != S_TRISTATE)
-				prop_warn(prop,
-				    "config symbol '%s' uses %s, but is "
-				    "not bool or tristate", sym->name, use);
-			else if (sym2->type != S_UNKNOWN &&
-				 sym2->type != S_BOOLEAN &&
-				 sym2->type != S_TRISTATE)
-				prop_warn(prop,
-				    "'%s' has wrong type. '%s' only "
-				    "accept arguments of bool and "
-				    "tristate type", sym2->name, use);
-			break;
-		case P_RANGE:
-			if (sym->type != S_INT && sym->type != S_HEX)
-				prop_warn(prop, "range is only allowed "
-						"for int or hex symbols");
-			if (!menu_validate_number(sym, prop->expr->left.sym) ||
-			    !menu_validate_number(sym, prop->expr->right.sym))
-				prop_warn(prop, "range is invalid");
-			break;
-		default:
-			;
-		}
-	}
-}
-
-void menu_finalize(struct menu *parent)
-{
-	struct menu *menu, *last_menu;
-	struct symbol *sym;
-	struct property *prop;
-	struct expr *parentdep, *basedep, *dep, *dep2, **ep;
-
-	sym = parent->sym;
-	if (parent->list) {
-		/*
-		 * This menu node has children. We (recursively) process them
-		 * and propagate parent dependencies before moving on.
-		 */
-
-		if (sym && sym_is_choice(sym)) {
-			if (sym->type == S_UNKNOWN) {
-				/* find the first choice value to find out choice type */
-				current_entry = parent;
-				for (menu = parent->list; menu; menu = menu->next) {
-					if (menu->sym && menu->sym->type != S_UNKNOWN) {
-						menu_set_type(menu->sym->type);
-						break;
-					}
-				}
-			}
-			/* set the type of the remaining choice values */
-			for (menu = parent->list; menu; menu = menu->next) {
-				current_entry = menu;
-				if (menu->sym && menu->sym->type == S_UNKNOWN)
-					menu_set_type(sym->type);
-			}
-
-			/*
-			 * Use the choice itself as the parent dependency of
-			 * the contained items. This turns the mode of the
-			 * choice into an upper bound on the visibility of the
-			 * choice value symbols.
-			 */
-			parentdep = expr_alloc_symbol(sym);
-		} else if (parent->prompt)
-			/* Menu node for 'menu' */
-			parentdep = parent->prompt->visible.expr;
-		else
-			/* Menu node for 'if' */
-			parentdep = parent->dep;
-
-		/* For each child menu node... */
-		for (menu = parent->list; menu; menu = menu->next) {
-			/*
-			 * Propagate parent dependencies to the child menu
-			 * node, also rewriting and simplifying expressions
-			 */
-			basedep = rewrite_m(menu->dep);
-			basedep = expr_transform(basedep);
-			basedep = expr_alloc_and(expr_copy(parentdep), basedep);
-			basedep = expr_eliminate_dups(basedep);
-			menu->dep = basedep;
-
-			if (menu->sym)
-				/*
-				 * Note: For symbols, all prompts are included
-				 * too in the symbol's own property list
-				 */
-				prop = menu->sym->prop;
-			else
-				/*
-				 * For non-symbol menu nodes, we just need to
-				 * handle the prompt
-				 */
-				prop = menu->prompt;
-
-			/* For each property... */
-			for (; prop; prop = prop->next) {
-				if (prop->menu != menu)
-					/*
-					 * Two possibilities:
-					 *
-					 * 1. The property lacks dependencies
-					 *    and so isn't location-specific,
-					 *    e.g. an 'option'
-					 *
-					 * 2. The property belongs to a symbol
-					 *    defined in multiple locations and
-					 *    is from some other location. It
-					 *    will be handled there in that
-					 *    case.
-					 *
-					 * Skip the property.
-					 */
-					continue;
-
-				/*
-				 * Propagate parent dependencies to the
-				 * property's condition, rewriting and
-				 * simplifying expressions at the same time
-				 */
-				dep = rewrite_m(prop->visible.expr);
-				dep = expr_transform(dep);
-				dep = expr_alloc_and(expr_copy(basedep), dep);
-				dep = expr_eliminate_dups(dep);
-				if (menu->sym && menu->sym->type != S_TRISTATE)
-					dep = expr_trans_bool(dep);
-				prop->visible.expr = dep;
-
-				/*
-				 * Handle selects and implies, which modify the
-				 * dependencies of the selected/implied symbol
-				 */
-				if (prop->type == P_SELECT) {
-					struct symbol *es = prop_get_symbol(prop);
-					es->rev_dep.expr = expr_alloc_or(es->rev_dep.expr,
-							expr_alloc_and(expr_alloc_symbol(menu->sym), expr_copy(dep)));
-				} else if (prop->type == P_IMPLY) {
-					struct symbol *es = prop_get_symbol(prop);
-					es->implied.expr = expr_alloc_or(es->implied.expr,
-							expr_alloc_and(expr_alloc_symbol(menu->sym), expr_copy(dep)));
-				}
-			}
-		}
-
-		if (sym && sym_is_choice(sym))
-			expr_free(parentdep);
-
-		/*
-		 * Recursively process children in the same fashion before
-		 * moving on
-		 */
-		for (menu = parent->list; menu; menu = menu->next)
-			menu_finalize(menu);
-	} else if (sym) {
-		/*
-		 * Automatic submenu creation. If sym is a symbol and A, B, C,
-		 * ... are consecutive items (symbols, menus, ifs, etc.) that
-		 * all depend on sym, then the following menu structure is
-		 * created:
-		 *
-		 *	sym
-		 *	 +-A
-		 *	 +-B
-		 *	 +-C
-		 *	 ...
-		 *
-		 * This also works recursively, giving the following structure
-		 * if A is a symbol and B depends on A:
-		 *
-		 *	sym
-		 *	 +-A
-		 *	 | +-B
-		 *	 +-C
-		 *	 ...
-		 */
-
-		basedep = parent->prompt ? parent->prompt->visible.expr : NULL;
-		basedep = expr_trans_compare(basedep, E_UNEQUAL, &symbol_no);
-		basedep = expr_eliminate_dups(expr_transform(basedep));
-
-		/* Examine consecutive elements after sym */
-		last_menu = NULL;
-		for (menu = parent->next; menu; menu = menu->next) {
-			dep = menu->prompt ? menu->prompt->visible.expr : menu->dep;
-			if (!expr_contains_symbol(dep, sym))
-				/* No dependency, quit */
-				break;
-			if (expr_depends_symbol(dep, sym))
-				/* Absolute dependency, put in submenu */
-				goto next;
-
-			/*
-			 * Also consider it a dependency on sym if our
-			 * dependencies contain sym and are a "superset" of
-			 * sym's dependencies, e.g. '(sym || Q) && R' when sym
-			 * depends on R.
-			 *
-			 * Note that 'R' might be from an enclosing menu or if,
-			 * making this a more common case than it might seem.
-			 */
-			dep = expr_trans_compare(dep, E_UNEQUAL, &symbol_no);
-			dep = expr_eliminate_dups(expr_transform(dep));
-			dep2 = expr_copy(basedep);
-			expr_eliminate_eq(&dep, &dep2);
-			expr_free(dep);
-			if (!expr_is_yes(dep2)) {
-				/* Not superset, quit */
-				expr_free(dep2);
-				break;
-			}
-			/* Superset, put in submenu */
-			expr_free(dep2);
-		next:
-			menu_finalize(menu);
-			menu->parent = parent;
-			last_menu = menu;
-		}
-		expr_free(basedep);
-		if (last_menu) {
-			parent->list = parent->next;
-			parent->next = last_menu->next;
-			last_menu->next = NULL;
-		}
-
-		sym->dir_dep.expr = expr_alloc_or(sym->dir_dep.expr, parent->dep);
-	}
-	for (menu = parent->list; menu; menu = menu->next) {
-		if (sym && sym_is_choice(sym) &&
-		    menu->sym && !sym_is_choice_value(menu->sym)) {
-			current_entry = menu;
-			menu->sym->flags |= SYMBOL_CHOICEVAL;
-			if (!menu->prompt)
-				menu_warn(menu, "choice value must have a prompt");
-			for (prop = menu->sym->prop; prop; prop = prop->next) {
-				if (prop->type == P_DEFAULT)
-					prop_warn(prop, "defaults for choice "
-						  "values not supported");
-				if (prop->menu == menu)
-					continue;
-				if (prop->type == P_PROMPT &&
-				    prop->menu->parent->sym != sym)
-					prop_warn(prop, "choice value used outside its choice group");
-			}
-			/* Non-tristate choice values of tristate choices must
-			 * depend on the choice being set to Y. The choice
-			 * values' dependencies were propagated to their
-			 * properties above, so the change here must be re-
-			 * propagated.
-			 */
-			if (sym->type == S_TRISTATE && menu->sym->type != S_TRISTATE) {
-				basedep = expr_alloc_comp(E_EQUAL, sym, &symbol_yes);
-				menu->dep = expr_alloc_and(basedep, menu->dep);
-				for (prop = menu->sym->prop; prop; prop = prop->next) {
-					if (prop->menu != menu)
-						continue;
-					prop->visible.expr = expr_alloc_and(expr_copy(basedep),
-									    prop->visible.expr);
-				}
-			}
-			menu_add_symbol(P_CHOICE, sym, NULL);
-			prop = sym_get_choice_prop(sym);
-			for (ep = &prop->expr; *ep; ep = &(*ep)->left.expr)
-				;
-			*ep = expr_alloc_one(E_LIST, NULL);
-			(*ep)->right.sym = menu->sym;
-		}
-
-		/*
-		 * This code serves two purposes:
-		 *
-		 * (1) Flattening 'if' blocks, which do not specify a submenu
-		 *     and only add dependencies.
-		 *
-		 *     (Automatic submenu creation might still create a submenu
-		 *     from an 'if' before this code runs.)
-		 *
-		 * (2) "Undoing" any automatic submenus created earlier below
-		 *     promptless symbols.
-		 *
-		 * Before:
-		 *
-		 *	A
-		 *	if ... (or promptless symbol)
-		 *	 +-B
-		 *	 +-C
-		 *	D
-		 *
-		 * After:
-		 *
-		 *	A
-		 *	if ... (or promptless symbol)
-		 *	B
-		 *	C
-		 *	D
-		 */
-		if (menu->list && (!menu->prompt || !menu->prompt->text)) {
-			for (last_menu = menu->list; ; last_menu = last_menu->next) {
-				last_menu->parent = parent;
-				if (!last_menu->next)
-					break;
-			}
-			last_menu->next = menu->next;
-			menu->next = menu->list;
-			menu->list = NULL;
-		}
-	}
-
-	if (sym && !(sym->flags & SYMBOL_WARNED)) {
-		if (sym->type == S_UNKNOWN)
-			menu_warn(parent, "config symbol defined without type");
-
-		if (sym_is_choice(sym) && !parent->prompt)
-			menu_warn(parent, "choice must have a prompt");
-
-		/* Check properties connected to this symbol */
-		sym_check_prop(sym);
-		sym->flags |= SYMBOL_WARNED;
-	}
-
-	/*
-	 * For non-optional choices, add a reverse dependency (corresponding to
-	 * a select) of '<visibility> && m'. This prevents the user from
-	 * setting the choice mode to 'n' when the choice is visible.
-	 *
-	 * This would also work for non-choice symbols, but only non-optional
-	 * choices clear SYMBOL_OPTIONAL as of writing. Choices are implemented
-	 * as a type of symbol.
-	 */
-	if (sym && !sym_is_optional(sym) && parent->prompt) {
-		sym->rev_dep.expr = expr_alloc_or(sym->rev_dep.expr,
-				expr_alloc_and(parent->prompt->visible.expr,
-					expr_alloc_symbol(&symbol_mod)));
-	}
-}
-
-bool menu_has_prompt(struct menu *menu)
-{
-	if (!menu->prompt)
-		return false;
-	return true;
-}
-
-/*
- * Determine if a menu is empty.
- * A menu is considered empty if it contains no or only
- * invisible entries.
- */
-bool menu_is_empty(struct menu *menu)
-{
-	struct menu *child;
-
-	for (child = menu->list; child; child = child->next) {
-		if (menu_is_visible(child))
-			return(false);
-	}
-	return(true);
-}
-
-bool menu_is_visible(struct menu *menu)
-{
-	struct menu *child;
-	struct symbol *sym;
-	tristate visible;
-
-	if (!menu->prompt)
-		return false;
-
-	if (menu->visibility) {
-		if (expr_calc_value(menu->visibility) == no)
-			return false;
-	}
-
-	sym = menu->sym;
-	if (sym) {
-		sym_calc_value(sym);
-		visible = menu->prompt->visible.tri;
-	} else
-		visible = menu->prompt->visible.tri = expr_calc_value(menu->prompt->visible.expr);
-
-	if (visible != no)
-		return true;
-
-	if (!sym || sym_get_tristate_value(menu->sym) == no)
-		return false;
-
-	for (child = menu->list; child; child = child->next) {
-		if (menu_is_visible(child)) {
-			if (sym)
-				sym->flags |= SYMBOL_DEF_USER;
-			return true;
-		}
-	}
-
-	return false;
-}
-
-const char *menu_get_prompt(struct menu *menu)
-{
-	if (menu->prompt)
-		return menu->prompt->text;
-	else if (menu->sym)
-		return menu->sym->name;
-	return NULL;
-}
-
-struct menu *menu_get_root_menu(struct menu *menu)
-{
-	return &rootmenu;
-}
-
-struct menu *menu_get_parent_menu(struct menu *menu)
-{
-	enum prop_type type;
-
-	for (; menu != &rootmenu; menu = menu->parent) {
-		type = menu->prompt ? menu->prompt->type : 0;
-		if (type == P_MENU)
-			break;
-	}
-	return menu;
-}
-
-bool menu_has_help(struct menu *menu)
-{
-	return menu->help != NULL;
-}
-
-const char *menu_get_help(struct menu *menu)
-{
-	if (menu->help)
-		return menu->help;
-	else
-		return "";
-}
-
-static void get_prompt_str(struct gstr *r, struct property *prop,
-			   struct list_head *head)
-{
-	int i, j;
-	struct menu *submenu[8], *menu, *location = NULL;
-	struct jump_key *jump = NULL;
-
-	str_printf(r, "Prompt: %s\n", prop->text);
-	menu = prop->menu->parent;
-	for (i = 0; menu != &rootmenu && i < 8; menu = menu->parent) {
-		bool accessible = menu_is_visible(menu);
-
-		submenu[i++] = menu;
-		if (location == NULL && accessible)
-			location = menu;
-	}
-	if (head && location) {
-		jump = xmalloc(sizeof(struct jump_key));
-
-		if (menu_is_visible(prop->menu)) {
-			/*
-			 * There is not enough room to put the hint at the
-			 * beginning of the "Prompt" line. Put the hint on the
-			 * last "Location" line even when it would belong on
-			 * the former.
-			 */
-			jump->target = prop->menu;
-		} else
-			jump->target = location;
-
-		if (list_empty(head))
-			jump->index = 0;
-		else
-			jump->index = list_entry(head->prev, struct jump_key,
-						 entries)->index + 1;
-
-		list_add_tail(&jump->entries, head);
-	}
-
-	if (i > 0) {
-		str_printf(r, "  Location:\n");
-		for (j = 4; --i >= 0; j += 2) {
-			menu = submenu[i];
-			if (jump && menu == location)
-				jump->offset = strlen(r->s);
-			str_printf(r, "%*c-> %s", j, ' ',
-				   menu_get_prompt(menu));
-			if (menu->sym) {
-				str_printf(r, " (%s [=%s])", menu->sym->name ?
-					menu->sym->name : "<choice>",
-					sym_get_string_value(menu->sym));
-			}
-			str_append(r, "\n");
-		}
-	}
-}
-
-/*
- * get property of type P_SYMBOL
- */
-static struct property *get_symbol_prop(struct symbol *sym)
-{
-	struct property *prop = NULL;
-
-	for_all_properties(sym, prop, P_SYMBOL)
-		break;
-	return prop;
-}
-
-static void get_symbol_props_str(struct gstr *r, struct symbol *sym,
-				 enum prop_type tok, const char *prefix)
-{
-	bool hit = false;
-	struct property *prop;
-
-	for_all_properties(sym, prop, tok) {
-		if (!hit) {
-			str_append(r, prefix);
-			hit = true;
-		} else
-			str_printf(r, " && ");
-		expr_gstr_print(prop->expr, r);
-	}
-	if (hit)
-		str_append(r, "\n");
-}
-
-/*
- * head is optional and may be NULL
- */
-static void get_symbol_str(struct gstr *r, struct symbol *sym,
-		    struct list_head *head)
-{
-	struct property *prop;
-
-	if (sym && sym->name) {
-		str_printf(r, "Symbol: %s [=%s]\n", sym->name,
-			   sym_get_string_value(sym));
-		str_printf(r, "Type  : %s\n", sym_type_name(sym->type));
-		if (sym->type == S_INT || sym->type == S_HEX) {
-			prop = sym_get_range_prop(sym);
-			if (prop) {
-				str_printf(r, "Range : ");
-				expr_gstr_print(prop->expr, r);
-				str_append(r, "\n");
-			}
-		}
-	}
-	for_all_prompts(sym, prop)
-		get_prompt_str(r, prop, head);
-
-	prop = get_symbol_prop(sym);
-	if (prop) {
-		str_printf(r, "  Defined at %s:%d\n", prop->menu->file->name,
-			prop->menu->lineno);
-		if (!expr_is_yes(prop->visible.expr)) {
-			str_append(r, "  Depends on: ");
-			expr_gstr_print(prop->visible.expr, r);
-			str_append(r, "\n");
-		}
-	}
-
-	get_symbol_props_str(r, sym, P_SELECT, "  Selects: ");
-	if (sym->rev_dep.expr) {
-		expr_gstr_print_revdep(sym->rev_dep.expr, r, yes, "  Selected by [y]:\n");
-		expr_gstr_print_revdep(sym->rev_dep.expr, r, mod, "  Selected by [m]:\n");
-		expr_gstr_print_revdep(sym->rev_dep.expr, r, no, "  Selected by [n]:\n");
-	}
-
-	get_symbol_props_str(r, sym, P_IMPLY, "  Implies: ");
-	if (sym->implied.expr) {
-		expr_gstr_print_revdep(sym->implied.expr, r, yes, "  Implied by [y]:\n");
-		expr_gstr_print_revdep(sym->implied.expr, r, mod, "  Implied by [m]:\n");
-		expr_gstr_print_revdep(sym->implied.expr, r, no, "  Implied by [n]:\n");
-	}
-
-	str_append(r, "\n\n");
-}
-
-struct gstr get_relations_str(struct symbol **sym_arr, struct list_head *head)
-{
-	struct symbol *sym;
-	struct gstr res = str_new();
-	int i;
-
-	for (i = 0; sym_arr && (sym = sym_arr[i]); i++)
-		get_symbol_str(&res, sym, head);
-	if (!i)
-		str_append(&res, "No matches found.\n");
-	return res;
-}
-
-
-void menu_get_ext_help(struct menu *menu, struct gstr *help)
-{
-	struct symbol *sym = menu->sym;
-	const char *help_text = nohelp_text;
-
-	if (menu_has_help(menu)) {
-		if (sym->name)
-			str_printf(help, "%s%s:\n\n", CONFIG_, sym->name);
-		help_text = menu_get_help(menu);
-	}
-	str_printf(help, "%s\n", help_text);
-	if (sym)
-		get_symbol_str(help, sym, NULL);
-}
diff --git a/util/kconfig/merge_config.sh b/util/kconfig/merge_config.sh
deleted file mode 100755
index 63c8565206..0000000000
--- a/util/kconfig/merge_config.sh
+++ /dev/null
@@ -1,189 +0,0 @@
-#!/bin/sh
-# SPDX-License-Identifier: GPL-2.0
-#
-#  merge_config.sh - Takes a list of config fragment values, and merges
-#  them one by one. Provides warnings on overridden values, and specified
-#  values that did not make it to the resulting .config file (due to missed
-#  dependencies or config symbol removal).
-#
-#  Portions reused from kconf_check and generate_cfg:
-#  http://git.yoctoproject.org/cgit/cgit.cgi/yocto-kernel-tools/tree/tools/kconf_check
-#  http://git.yoctoproject.org/cgit/cgit.cgi/yocto-kernel-tools/tree/tools/generate_cfg
-#
-#  Copyright (c) 2009-2010 Wind River Systems, Inc.
-#  Copyright 2011 Linaro
-
-set -e
-
-clean_up() {
-	rm -f $TMP_FILE
-	rm -f $MERGE_FILE
-}
-
-usage() {
-	echo "Usage: $0 [OPTIONS] [CONFIG [...]]"
-	echo "  -h    display this help text"
-	echo "  -m    only merge the fragments, do not execute the make command"
-	echo "  -n    use allnoconfig instead of alldefconfig"
-	echo "  -r    list redundant entries when merging fragments"
-	echo "  -y    make builtin have precedence over modules"
-	echo "  -O    dir to put generated output files.  Consider setting \$KCONFIG_CONFIG instead."
-	echo
-	echo "Used prefix: '$CONFIG_PREFIX'. You can redefine it with \$CONFIG_ environment variable."
-}
-
-RUNMAKE=true
-ALLTARGET=alldefconfig
-WARNREDUN=false
-BUILTIN=false
-OUTPUT=.
-CONFIG_PREFIX=${CONFIG_-CONFIG_}
-
-while true; do
-	case $1 in
-	"-n")
-		ALLTARGET=allnoconfig
-		shift
-		continue
-		;;
-	"-m")
-		RUNMAKE=false
-		shift
-		continue
-		;;
-	"-h")
-		usage
-		exit
-		;;
-	"-r")
-		WARNREDUN=true
-		shift
-		continue
-		;;
-	"-y")
-		BUILTIN=true
-		shift
-		continue
-		;;
-	"-O")
-		if [ -d $2 ];then
-			OUTPUT=$(echo $2 | sed 's/\/*$//')
-		else
-			echo "output directory $2 does not exist" 1>&2
-			exit 1
-		fi
-		shift 2
-		continue
-		;;
-	*)
-		break
-		;;
-	esac
-done
-
-if [ "$#" -lt 1 ] ; then
-	usage
-	exit
-fi
-
-if [ -z "$KCONFIG_CONFIG" ]; then
-	if [ "$OUTPUT" != . ]; then
-		KCONFIG_CONFIG=$(readlink -m -- "$OUTPUT/.config")
-	else
-		KCONFIG_CONFIG=.config
-	fi
-fi
-
-INITFILE=$1
-shift;
-
-if [ ! -r "$INITFILE" ]; then
-	echo "The base file '$INITFILE' does not exist.  Exit." >&2
-	exit 1
-fi
-
-MERGE_LIST=$*
-SED_CONFIG_EXP1="s/^\(${CONFIG_PREFIX}[a-zA-Z0-9_]*\)=.*/\1/p"
-SED_CONFIG_EXP2="s/^# \(${CONFIG_PREFIX}[a-zA-Z0-9_]*\) is not set$/\1/p"
-
-TMP_FILE=$(mktemp ./.tmp.config.XXXXXXXXXX)
-MERGE_FILE=$(mktemp ./.merge_tmp.config.XXXXXXXXXX)
-
-echo "Using $INITFILE as base"
-
-trap clean_up EXIT
-
-cat $INITFILE > $TMP_FILE
-
-# Merge files, printing warnings on overridden values
-for ORIG_MERGE_FILE in $MERGE_LIST ; do
-	echo "Merging $ORIG_MERGE_FILE"
-	if [ ! -r "$ORIG_MERGE_FILE" ]; then
-		echo "The merge file '$ORIG_MERGE_FILE' does not exist.  Exit." >&2
-		exit 1
-	fi
-	cat $ORIG_MERGE_FILE > $MERGE_FILE
-	CFG_LIST=$(sed -n -e "$SED_CONFIG_EXP1" -e "$SED_CONFIG_EXP2" $MERGE_FILE)
-
-	for CFG in $CFG_LIST ; do
-		grep -q -w $CFG $TMP_FILE || continue
-		PREV_VAL=$(grep -w $CFG $TMP_FILE)
-		NEW_VAL=$(grep -w $CFG $MERGE_FILE)
-		BUILTIN_FLAG=false
-		if [ "$BUILTIN" = "true" ] && [ "${NEW_VAL#CONFIG_*=}" = "m" ] && [ "${PREV_VAL#CONFIG_*=}" = "y" ]; then
-			echo Previous  value: $PREV_VAL
-			echo New value:       $NEW_VAL
-			echo -y passed, will not demote y to m
-			echo
-			BUILTIN_FLAG=true
-		elif [ "x$PREV_VAL" != "x$NEW_VAL" ] ; then
-			echo Value of $CFG is redefined by fragment $ORIG_MERGE_FILE:
-			echo Previous  value: $PREV_VAL
-			echo New value:       $NEW_VAL
-			echo
-		elif [ "$WARNREDUN" = "true" ]; then
-			echo Value of $CFG is redundant by fragment $ORIG_MERGE_FILE:
-		fi
-		if [ "$BUILTIN_FLAG" = "false" ]; then
-			sed -i "/$CFG[ =]/d" $TMP_FILE
-		else
-			sed -i "/$CFG[ =]/d" $MERGE_FILE
-		fi
-	done
-	cat $MERGE_FILE >> $TMP_FILE
-done
-
-if [ "$RUNMAKE" = "false" ]; then
-	cp -T -- "$TMP_FILE" "$KCONFIG_CONFIG"
-	echo "#"
-	echo "# merged configuration written to $KCONFIG_CONFIG (needs make)"
-	echo "#"
-	exit
-fi
-
-# If we have an output dir, setup the O= argument, otherwise leave
-# it blank, since O=. will create an unnecessary ./source softlink
-OUTPUT_ARG=""
-if [ "$OUTPUT" != "." ] ; then
-	OUTPUT_ARG="O=$OUTPUT"
-fi
-
-
-# Use the merged file as the starting point for:
-# alldefconfig: Fills in any missing symbols with Kconfig default
-# allnoconfig: Fills in any missing symbols with # CONFIG_* is not set
-make KCONFIG_ALLCONFIG=$TMP_FILE $OUTPUT_ARG $ALLTARGET
-
-
-# Check all specified config values took (might have missed-dependency issues)
-for CFG in $(sed -n -e "$SED_CONFIG_EXP1" -e "$SED_CONFIG_EXP2" $TMP_FILE); do
-
-	REQUESTED_VAL=$(grep -w -e "$CFG" $TMP_FILE)
-	ACTUAL_VAL=$(grep -w -e "$CFG" "$KCONFIG_CONFIG" || true)
-	if [ "x$REQUESTED_VAL" != "x$ACTUAL_VAL" ] ; then
-		echo "Value requested for $CFG not in final .config"
-		echo "Requested value:  $REQUESTED_VAL"
-		echo "Actual value:     $ACTUAL_VAL"
-		echo ""
-	fi
-done
diff --git a/util/kconfig/nconf-cfg.sh b/util/kconfig/nconf-cfg.sh
deleted file mode 100755
index 001559ef0a..0000000000
--- a/util/kconfig/nconf-cfg.sh
+++ /dev/null
@@ -1,47 +0,0 @@
-#!/bin/sh
-# SPDX-License-Identifier: GPL-2.0
-
-PKG="ncursesw menuw panelw"
-PKG2="ncurses menu panel"
-
-if [ -n "$(command -v pkg-config)" ]; then
-	if pkg-config --exists $PKG; then
-		echo cflags=\"$(pkg-config --cflags $PKG)\"
-		echo libs=\"$(pkg-config --libs $PKG)\"
-		exit 0
-	fi
-
-	if pkg-config --exists $PKG2; then
-		echo cflags=\"$(pkg-config --cflags $PKG2)\"
-		echo libs=\"$(pkg-config --libs $PKG2)\"
-		exit 0
-	fi
-fi
-
-# Check the default paths in case pkg-config is not installed.
-# (Even if it is installed, some distributions such as openSUSE cannot
-# find ncurses by pkg-config.)
-if [ -f /usr/include/ncursesw/ncurses.h ]; then
-	echo cflags=\"-D_GNU_SOURCE -I/usr/include/ncursesw\"
-	echo libs=\"-lncursesw -lmenuw -lpanelw\"
-	exit 0
-fi
-
-if [ -f /usr/include/ncurses/ncurses.h ]; then
-	echo cflags=\"-D_GNU_SOURCE -I/usr/include/ncurses\"
-	echo libs=\"-lncurses -lmenu -lpanel\"
-	exit 0
-fi
-
-if [ -f /usr/include/ncurses.h ]; then
-	echo cflags=\"-D_GNU_SOURCE\"
-	echo libs=\"-lncurses -lmenu -lpanel\"
-	exit 0
-fi
-
-echo >&2 "*"
-echo >&2 "* Unable to find the ncurses package."
-echo >&2 "* Install ncurses (ncurses-devel or libncurses-dev"
-echo >&2 "* depending on your distribution)."
-echo >&2 "*"
-exit 1
diff --git a/util/kconfig/nconf.c b/util/kconfig/nconf.c
deleted file mode 100644
index b7c1ef7571..0000000000
--- a/util/kconfig/nconf.c
+++ /dev/null
@@ -1,1555 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2008 Nir Tzachar <nir.tzachar@gmail.com>
- *
- * Derived from menuconfig.
- */
-#ifndef _GNU_SOURCE
-#define _GNU_SOURCE
-#endif
-#include <string.h>
-#include <stdlib.h>
-
-#include "lkc.h"
-#include "nconf.h"
-#include <ctype.h>
-
-static const char nconf_global_help[] =
-"Help windows\n"
-"------------\n"
-"o  Global help:  Unless in a data entry window, pressing <F1> will give \n"
-"   you the global help window, which you are just reading.\n"
-"\n"
-"o  A short version of the global help is available by pressing <F3>.\n"
-"\n"
-"o  Local help:  To get help related to the current menu entry, use any\n"
-"   of <?> <h>, or if in a data entry window then press <F1>.\n"
-"\n"
-"\n"
-"Menu entries\n"
-"------------\n"
-"This interface lets you select features and parameters for the kernel\n"
-"build.  Kernel features can either be built-in, modularized, or removed.\n"
-"Parameters must be entered as text or decimal or hexadecimal numbers.\n"
-"\n"
-"Menu entries beginning with following braces represent features that\n"
-"  [ ]  can be built in or removed\n"
-"  < >  can be built in, modularized or removed\n"
-"  { }  can be built in or modularized, are selected by another feature\n"
-"  - -  are selected by another feature\n"
-"  XXX  cannot be selected.  Symbol Info <F2> tells you why.\n"
-"*, M or whitespace inside braces means to build in, build as a module\n"
-"or to exclude the feature respectively.\n"
-"\n"
-"To change any of these features, highlight it with the movement keys\n"
-"listed below and press <y> to build it in, <m> to make it a module or\n"
-"<n> to remove it.  You may press the <Space> key to cycle through the\n"
-"available options.\n"
-"\n"
-"A trailing \"--->\" designates a submenu, a trailing \"----\" an\n"
-"empty submenu.\n"
-"\n"
-"Menu navigation keys\n"
-"----------------------------------------------------------------------\n"
-"Linewise up                 <Up>\n"
-"Linewise down               <Down>\n"
-"Pagewise up                 <Page Up>\n"
-"Pagewise down               <Page Down>\n"
-"First entry                 <Home>\n"
-"Last entry                  <End>\n"
-"Enter a submenu             <Right>  <Enter>\n"
-"Go back to parent menu      <Left>   <Esc>  <F5>\n"
-"Close a help window         <Enter>  <Esc>  <F5>\n"
-"Close entry window, apply   <Enter>\n"
-"Close entry window, forget  <Esc>  <F5>\n"
-"Start incremental, case-insensitive search for STRING in menu entries,\n"
-"    no regex support, STRING is displayed in upper left corner\n"
-"                            </>STRING\n"
-"    Remove last character   <Backspace>\n"
-"    Jump to next hit        <Down>\n"
-"    Jump to previous hit    <Up>\n"
-"Exit menu search mode       </>  <Esc>\n"
-"Search for configuration variables with or without leading CONFIG_\n"
-"                            <F8>RegExpr<Enter>\n"
-"Verbose search help         <F8><F1>\n"
-"----------------------------------------------------------------------\n"
-"\n"
-"Unless in a data entry window, key <1> may be used instead of <F1>,\n"
-"<2> instead of <F2>, etc.\n"
-"\n"
-"\n"
-"Radiolist (Choice list)\n"
-"-----------------------\n"
-"Use the movement keys listed above to select the option you wish to set\n"
-"and press <Space>.\n"
-"\n"
-"\n"
-"Data entry\n"
-"----------\n"
-"Enter the requested information and press <Enter>.  Hexadecimal values\n"
-"may be entered without the \"0x\" prefix.\n"
-"\n"
-"\n"
-"Text Box (Help Window)\n"
-"----------------------\n"
-"Use movement keys as listed in table above.\n"
-"\n"
-"Press any of <Enter> <Esc> <q> <F5> <F9> to exit.\n"
-"\n"
-"\n"
-"Alternate configuration files\n"
-"-----------------------------\n"
-"nconfig supports switching between different configurations.\n"
-"Press <F6> to save your current configuration.  Press <F7> and enter\n"
-"a file name to load a previously saved configuration.\n"
-"\n"
-"\n"
-"Terminal configuration\n"
-"----------------------\n"
-"If you use nconfig in a xterm window, make sure your TERM environment\n"
-"variable specifies a terminal configuration which supports at least\n"
-"16 colors.  Otherwise nconfig will look rather bad.\n"
-"\n"
-"If the \"stty size\" command reports the current terminalsize correctly,\n"
-"nconfig will adapt to sizes larger than the traditional 80x25 \"standard\"\n"
-"and display longer menus properly.\n"
-"\n"
-"\n"
-"Single menu mode\n"
-"----------------\n"
-"If you prefer to have all of the menu entries listed in a single menu,\n"
-"rather than the default multimenu hierarchy, run nconfig with\n"
-"NCONFIG_MODE environment variable set to single_menu.  Example:\n"
-"\n"
-"make NCONFIG_MODE=single_menu nconfig\n"
-"\n"
-"<Enter> will then unfold the appropriate category, or fold it if it\n"
-"is already unfolded.  Folded menu entries will be designated by a\n"
-"leading \"++>\" and unfolded entries by a leading \"-->\".\n"
-"\n"
-"Note that this mode can eventually be a little more CPU expensive than\n"
-"the default mode, especially with a larger number of unfolded submenus.\n"
-"\n",
-menu_no_f_instructions[] =
-"Legend:  [*] built-in  [ ] excluded  <M> module  < > module capable.\n"
-"Submenus are designated by a trailing \"--->\", empty ones by \"----\".\n"
-"\n"
-"Use the following keys to navigate the menus:\n"
-"Move up or down with <Up> and <Down>.\n"
-"Enter a submenu with <Enter> or <Right>.\n"
-"Exit a submenu to its parent menu with <Esc> or <Left>.\n"
-"Pressing <y> includes, <n> excludes, <m> modularizes features.\n"
-"Pressing <Space> cycles through the available options.\n"
-"To search for menu entries press </>.\n"
-"<Esc> always leaves the current window.\n"
-"\n"
-"You do not have function keys support.\n"
-"Press <1> instead of <F1>, <2> instead of <F2>, etc.\n"
-"For verbose global help use key <1>.\n"
-"For help related to the current menu entry press <?> or <h>.\n",
-menu_instructions[] =
-"Legend:  [*] built-in  [ ] excluded  <M> module  < > module capable.\n"
-"Submenus are designated by a trailing \"--->\", empty ones by \"----\".\n"
-"\n"
-"Use the following keys to navigate the menus:\n"
-"Move up or down with <Up> or <Down>.\n"
-"Enter a submenu with <Enter> or <Right>.\n"
-"Exit a submenu to its parent menu with <Esc> or <Left>.\n"
-"Pressing <y> includes, <n> excludes, <m> modularizes features.\n"
-"Pressing <Space> cycles through the available options.\n"
-"To search for menu entries press </>.\n"
-"<Esc> always leaves the current window.\n"
-"\n"
-"Pressing <1> may be used instead of <F1>, <2> instead of <F2>, etc.\n"
-"For verbose global help press <F1>.\n"
-"For help related to the current menu entry press <?> or <h>.\n",
-radiolist_instructions[] =
-"Press <Up>, <Down>, <Home> or <End> to navigate a radiolist, select\n"
-"with <Space>.\n"
-"For help related to the current entry press <?> or <h>.\n"
-"For global help press <F1>.\n",
-inputbox_instructions_int[] =
-"Please enter a decimal value.\n"
-"Fractions will not be accepted.\n"
-"Press <Enter> to apply, <Esc> to cancel.",
-inputbox_instructions_hex[] =
-"Please enter a hexadecimal value.\n"
-"Press <Enter> to apply, <Esc> to cancel.",
-inputbox_instructions_string[] =
-"Please enter a string value.\n"
-"Press <Enter> to apply, <Esc> to cancel.",
-setmod_text[] =
-"This feature depends on another feature which has been configured as a\n"
-"module.  As a result, the current feature will be built as a module too.",
-load_config_text[] =
-"Enter the name of the configuration file you wish to load.\n"
-"Accept the name shown to restore the configuration you last\n"
-"retrieved.  Leave empty to abort.",
-load_config_help[] =
-"For various reasons, one may wish to keep several different\n"
-"configurations available on a single machine.\n"
-"\n"
-"If you have saved a previous configuration in a file other than the\n"
-"default one, entering its name here will allow you to load and modify\n"
-"that configuration.\n"
-"\n"
-"Leave empty to abort.\n",
-save_config_text[] =
-"Enter a filename to which this configuration should be saved\n"
-"as an alternate.  Leave empty to abort.",
-save_config_help[] =
-"For various reasons, one may wish to keep several different\n"
-"configurations available on a single machine.\n"
-"\n"
-"Entering a file name here will allow you to later retrieve, modify\n"
-"and use the current configuration as an alternate to whatever\n"
-"configuration options you have selected at that time.\n"
-"\n"
-"Leave empty to abort.\n",
-search_help[] =
-"Search for symbols (configuration variable names CONFIG_*) and display\n"
-"their relations.  Regular expressions are supported.\n"
-"Example:  Search for \"^FOO\".\n"
-"Result:\n"
-"-----------------------------------------------------------------\n"
-"Symbol: FOO [ = m]\n"
-"Prompt: Foo bus is used to drive the bar HW\n"
-"Defined at drivers/pci/Kconfig:47\n"
-"Depends on: X86_LOCAL_APIC && X86_IO_APIC || IA64\n"
-"Location:\n"
-"  -> Bus options (PCI, PCMCIA, EISA, ISA)\n"
-"    -> PCI support (PCI [ = y])\n"
-"      -> PCI access mode (<choice> [ = y])\n"
-"Selects: LIBCRC32\n"
-"Selected by: BAR\n"
-"-----------------------------------------------------------------\n"
-"o  The line 'Prompt:' shows the text displayed for this symbol in\n"
-"   the menu hierarchy.\n"
-"o  The 'Defined at' line tells at what file / line number the symbol is\n"
-"   defined.\n"
-"o  The 'Depends on:' line lists symbols that need to be defined for\n"
-"   this symbol to be visible and selectable in the menu.\n"
-"o  The 'Location:' lines tell, where in the menu structure this symbol\n"
-"   is located.  A location followed by a [ = y] indicates that this is\n"
-"   a selectable menu item, and the current value is displayed inside\n"
-"   brackets.\n"
-"o  The 'Selects:' line tells, what symbol will be automatically selected\n"
-"   if this symbol is selected (y or m).\n"
-"o  The 'Selected by' line tells what symbol has selected this symbol.\n"
-"\n"
-"Only relevant lines are shown.\n"
-"\n\n"
-"Search examples:\n"
-"USB  => find all symbols containing USB\n"
-"^USB => find all symbols starting with USB\n"
-"USB$ => find all symbols ending with USB\n"
-"\n";
-
-struct mitem {
-	char str[256];
-	char tag;
-	void *usrptr;
-	int is_visible;
-};
-
-#define MAX_MENU_ITEMS 4096
-static int show_all_items;
-static int indent;
-static struct menu *current_menu;
-static int child_count;
-static int single_menu_mode;
-/* the window in which all information appears */
-static WINDOW *main_window;
-/* the largest size of the menu window */
-static int mwin_max_lines;
-static int mwin_max_cols;
-/* the window in which we show option buttons */
-static MENU *curses_menu;
-static ITEM *curses_menu_items[MAX_MENU_ITEMS];
-static struct mitem k_menu_items[MAX_MENU_ITEMS];
-static int items_num;
-static int global_exit;
-/* the currently selected button */
-static const char *current_instructions = menu_instructions;
-
-static char *dialog_input_result;
-static int dialog_input_result_len;
-
-static void conf(struct menu *menu);
-static void conf_choice(struct menu *menu);
-static void conf_string(struct menu *menu);
-static void conf_load(void);
-static void conf_save(void);
-static void show_help(struct menu *menu);
-static int do_exit(void);
-static void setup_windows(void);
-static void search_conf(void);
-
-typedef void (*function_key_handler_t)(int *key, struct menu *menu);
-static void handle_f1(int *key, struct menu *current_item);
-static void handle_f2(int *key, struct menu *current_item);
-static void handle_f3(int *key, struct menu *current_item);
-static void handle_f4(int *key, struct menu *current_item);
-static void handle_f5(int *key, struct menu *current_item);
-static void handle_f6(int *key, struct menu *current_item);
-static void handle_f7(int *key, struct menu *current_item);
-static void handle_f8(int *key, struct menu *current_item);
-static void handle_f9(int *key, struct menu *current_item);
-
-struct function_keys {
-	const char *key_str;
-	const char *func;
-	function_key key;
-	function_key_handler_t handler;
-};
-
-static const int function_keys_num = 9;
-static struct function_keys function_keys[] = {
-	{
-		.key_str = "F1",
-		.func = "Help",
-		.key = F_HELP,
-		.handler = handle_f1,
-	},
-	{
-		.key_str = "F2",
-		.func = "SymInfo",
-		.key = F_SYMBOL,
-		.handler = handle_f2,
-	},
-	{
-		.key_str = "F3",
-		.func = "Help 2",
-		.key = F_INSTS,
-		.handler = handle_f3,
-	},
-	{
-		.key_str = "F4",
-		.func = "ShowAll",
-		.key = F_CONF,
-		.handler = handle_f4,
-	},
-	{
-		.key_str = "F5",
-		.func = "Back",
-		.key = F_BACK,
-		.handler = handle_f5,
-	},
-	{
-		.key_str = "F6",
-		.func = "Save",
-		.key = F_SAVE,
-		.handler = handle_f6,
-	},
-	{
-		.key_str = "F7",
-		.func = "Load",
-		.key = F_LOAD,
-		.handler = handle_f7,
-	},
-	{
-		.key_str = "F8",
-		.func = "SymSearch",
-		.key = F_SEARCH,
-		.handler = handle_f8,
-	},
-	{
-		.key_str = "F9",
-		.func = "Exit",
-		.key = F_EXIT,
-		.handler = handle_f9,
-	},
-};
-
-static void print_function_line(void)
-{
-	int i;
-	int offset = 1;
-	const int skip = 1;
-	int lines = getmaxy(stdscr);
-
-	for (i = 0; i < function_keys_num; i++) {
-		(void) wattrset(main_window, attributes[FUNCTION_HIGHLIGHT]);
-		mvwprintw(main_window, lines-3, offset,
-				"%s",
-				function_keys[i].key_str);
-		(void) wattrset(main_window, attributes[FUNCTION_TEXT]);
-		offset += strlen(function_keys[i].key_str);
-		mvwprintw(main_window, lines-3,
-				offset, "%s",
-				function_keys[i].func);
-		offset += strlen(function_keys[i].func) + skip;
-	}
-	(void) wattrset(main_window, attributes[NORMAL]);
-}
-
-/* help */
-static void handle_f1(int *key, struct menu *current_item)
-{
-	show_scroll_win(main_window,
-			"Global help", nconf_global_help);
-	return;
-}
-
-/* symbole help */
-static void handle_f2(int *key, struct menu *current_item)
-{
-	show_help(current_item);
-	return;
-}
-
-/* instructions */
-static void handle_f3(int *key, struct menu *current_item)
-{
-	show_scroll_win(main_window,
-			"Short help",
-			current_instructions);
-	return;
-}
-
-/* config */
-static void handle_f4(int *key, struct menu *current_item)
-{
-	int res = btn_dialog(main_window,
-			"Show all symbols?",
-			2,
-			"   <Show All>   ",
-			"<Don't show all>");
-	if (res == 0)
-		show_all_items = 1;
-	else if (res == 1)
-		show_all_items = 0;
-
-	return;
-}
-
-/* back */
-static void handle_f5(int *key, struct menu *current_item)
-{
-	*key = KEY_LEFT;
-	return;
-}
-
-/* save */
-static void handle_f6(int *key, struct menu *current_item)
-{
-	conf_save();
-	return;
-}
-
-/* load */
-static void handle_f7(int *key, struct menu *current_item)
-{
-	conf_load();
-	return;
-}
-
-/* search */
-static void handle_f8(int *key, struct menu *current_item)
-{
-	search_conf();
-	return;
-}
-
-/* exit */
-static void handle_f9(int *key, struct menu *current_item)
-{
-	do_exit();
-	return;
-}
-
-/* return != 0 to indicate the key was handles */
-static int process_special_keys(int *key, struct menu *menu)
-{
-	int i;
-
-	if (*key == KEY_RESIZE) {
-		setup_windows();
-		return 1;
-	}
-
-	for (i = 0; i < function_keys_num; i++) {
-		if (*key == KEY_F(function_keys[i].key) ||
-		    *key == '0' + function_keys[i].key){
-			function_keys[i].handler(key, menu);
-			return 1;
-		}
-	}
-
-	return 0;
-}
-
-static void clean_items(void)
-{
-	int i;
-	for (i = 0; curses_menu_items[i]; i++)
-		free_item(curses_menu_items[i]);
-	bzero(curses_menu_items, sizeof(curses_menu_items));
-	bzero(k_menu_items, sizeof(k_menu_items));
-	items_num = 0;
-}
-
-typedef enum {MATCH_TINKER_PATTERN_UP, MATCH_TINKER_PATTERN_DOWN,
-	FIND_NEXT_MATCH_DOWN, FIND_NEXT_MATCH_UP} match_f;
-
-/* return the index of the matched item, or -1 if no such item exists */
-static int get_mext_match(const char *match_str, match_f flag)
-{
-	int match_start = item_index(current_item(curses_menu));
-	int index;
-
-	if (flag == FIND_NEXT_MATCH_DOWN)
-		++match_start;
-	else if (flag == FIND_NEXT_MATCH_UP)
-		--match_start;
-
-	index = match_start;
-	index = (index + items_num) % items_num;
-	while (true) {
-		char *str = k_menu_items[index].str;
-		if (strcasestr(str, match_str) != NULL)
-			return index;
-		if (flag == FIND_NEXT_MATCH_UP ||
-		    flag == MATCH_TINKER_PATTERN_UP)
-			--index;
-		else
-			++index;
-		index = (index + items_num) % items_num;
-		if (index == match_start)
-			return -1;
-	}
-}
-
-/* Make a new item. */
-static void item_make(struct menu *menu, char tag, const char *fmt, ...)
-{
-	va_list ap;
-
-	if (items_num > MAX_MENU_ITEMS-1)
-		return;
-
-	bzero(&k_menu_items[items_num], sizeof(k_menu_items[0]));
-	k_menu_items[items_num].tag = tag;
-	k_menu_items[items_num].usrptr = menu;
-	if (menu != NULL)
-		k_menu_items[items_num].is_visible =
-			menu_is_visible(menu);
-	else
-		k_menu_items[items_num].is_visible = 1;
-
-	va_start(ap, fmt);
-	vsnprintf(k_menu_items[items_num].str,
-		  sizeof(k_menu_items[items_num].str),
-		  fmt, ap);
-	va_end(ap);
-
-	if (!k_menu_items[items_num].is_visible)
-		memcpy(k_menu_items[items_num].str, "XXX", 3);
-
-	curses_menu_items[items_num] = new_item(
-			k_menu_items[items_num].str,
-			k_menu_items[items_num].str);
-	set_item_userptr(curses_menu_items[items_num],
-			&k_menu_items[items_num]);
-	/*
-	if (!k_menu_items[items_num].is_visible)
-		item_opts_off(curses_menu_items[items_num], O_SELECTABLE);
-	*/
-
-	items_num++;
-	curses_menu_items[items_num] = NULL;
-}
-
-/* very hackish. adds a string to the last item added */
-static void item_add_str(const char *fmt, ...)
-{
-	va_list ap;
-	int index = items_num-1;
-	char new_str[256];
-	char tmp_str[256];
-
-	if (index < 0)
-		return;
-
-	va_start(ap, fmt);
-	vsnprintf(new_str, sizeof(new_str), fmt, ap);
-	va_end(ap);
-	snprintf(tmp_str, sizeof(tmp_str), "%s%s",
-			k_menu_items[index].str, new_str);
-	strncpy(k_menu_items[index].str,
-		tmp_str,
-		sizeof(k_menu_items[index].str));
-
-	free_item(curses_menu_items[index]);
-	curses_menu_items[index] = new_item(
-			k_menu_items[index].str,
-			k_menu_items[index].str);
-	set_item_userptr(curses_menu_items[index],
-			&k_menu_items[index]);
-}
-
-/* get the tag of the currently selected item */
-static char item_tag(void)
-{
-	ITEM *cur;
-	struct mitem *mcur;
-
-	cur = current_item(curses_menu);
-	if (cur == NULL)
-		return 0;
-	mcur = (struct mitem *) item_userptr(cur);
-	return mcur->tag;
-}
-
-static int curses_item_index(void)
-{
-	return  item_index(current_item(curses_menu));
-}
-
-static void *item_data(void)
-{
-	ITEM *cur;
-	struct mitem *mcur;
-
-	cur = current_item(curses_menu);
-	if (!cur)
-		return NULL;
-	mcur = (struct mitem *) item_userptr(cur);
-	return mcur->usrptr;
-
-}
-
-static int item_is_tag(char tag)
-{
-	return item_tag() == tag;
-}
-
-static char filename[PATH_MAX+1];
-static char menu_backtitle[PATH_MAX+128];
-static const char *set_config_filename(const char *config_filename)
-{
-	int size;
-
-	size = snprintf(menu_backtitle, sizeof(menu_backtitle),
-			"%s - %s", config_filename, rootmenu.prompt->text);
-	if (size >= sizeof(menu_backtitle))
-		menu_backtitle[sizeof(menu_backtitle)-1] = '\0';
-
-	size = snprintf(filename, sizeof(filename), "%s", config_filename);
-	if (size >= sizeof(filename))
-		filename[sizeof(filename)-1] = '\0';
-	return menu_backtitle;
-}
-
-/* return = 0 means we are successful.
- * -1 means go on doing what you were doing
- */
-static int do_exit(void)
-{
-	int res;
-	if (!conf_get_changed()) {
-		global_exit = 1;
-		return 0;
-	}
-	res = btn_dialog(main_window,
-			"Do you wish to save your new configuration?\n"
-				"<ESC> to cancel and resume nconfig.",
-			2,
-			"   <save>   ",
-			"<don't save>");
-	if (res == KEY_EXIT) {
-		global_exit = 0;
-		return -1;
-	}
-
-	/* if we got here, the user really wants to exit */
-	switch (res) {
-	case 0:
-		res = conf_write(filename);
-		if (res)
-			btn_dialog(
-				main_window,
-				"Error during writing of configuration.\n"
-				  "Your configuration changes were NOT saved.",
-				  1,
-				  "<OK>");
-		conf_write_autoconf(0);
-		break;
-	default:
-		btn_dialog(
-			main_window,
-			"Your configuration changes were NOT saved.",
-			1,
-			"<OK>");
-		break;
-	}
-	global_exit = 1;
-	return 0;
-}
-
-
-static void search_conf(void)
-{
-	struct symbol **sym_arr;
-	struct gstr res;
-	struct gstr title;
-	char *dialog_input;
-	int dres;
-
-	title = str_new();
-	str_printf( &title, "Enter (sub)string or regexp to search for "
-			      "(with or without \"%s\")", CONFIG_);
-
-again:
-	dres = dialog_inputbox(main_window,
-			"Search Configuration Parameter",
-			str_get(&title),
-			"", &dialog_input_result, &dialog_input_result_len);
-	switch (dres) {
-	case 0:
-		break;
-	case 1:
-		show_scroll_win(main_window,
-				"Search Configuration", search_help);
-		goto again;
-	default:
-		str_free(&title);
-		return;
-	}
-
-	/* strip the prefix if necessary */
-	dialog_input = dialog_input_result;
-	if (strncasecmp(dialog_input_result, CONFIG_, strlen(CONFIG_)) == 0)
-		dialog_input += strlen(CONFIG_);
-
-	sym_arr = sym_re_search(dialog_input);
-	res = get_relations_str(sym_arr, NULL);
-	free(sym_arr);
-	show_scroll_win(main_window,
-			"Search Results", str_get(&res));
-	str_free(&res);
-	str_free(&title);
-}
-
-
-static void build_conf(struct menu *menu)
-{
-	struct symbol *sym;
-	struct property *prop;
-	struct menu *child;
-	int type, tmp, doint = 2;
-	tristate val;
-	char ch;
-
-	if (!menu || (!show_all_items && !menu_is_visible(menu)))
-		return;
-
-	sym = menu->sym;
-	prop = menu->prompt;
-	if (!sym) {
-		if (prop && menu != current_menu) {
-			const char *prompt = menu_get_prompt(menu);
-			enum prop_type ptype;
-			ptype = menu->prompt ? menu->prompt->type : P_UNKNOWN;
-			switch (ptype) {
-			case P_MENU:
-				child_count++;
-				prompt = prompt;
-				if (single_menu_mode) {
-					item_make(menu, 'm',
-						"%s%*c%s",
-						menu->data ? "-->" : "++>",
-						indent + 1, ' ', prompt);
-				} else
-					item_make(menu, 'm',
-						  "   %*c%s  %s",
-						  indent + 1, ' ', prompt,
-						  menu_is_empty(menu) ? "----" : "--->");
-
-				if (single_menu_mode && menu->data)
-					goto conf_childs;
-				return;
-			case P_COMMENT:
-				if (prompt) {
-					child_count++;
-					item_make(menu, ':',
-						"   %*c*** %s ***",
-						indent + 1, ' ',
-						prompt);
-				}
-				break;
-			default:
-				if (prompt) {
-					child_count++;
-					item_make(menu, ':', "---%*c%s",
-						indent + 1, ' ',
-						prompt);
-				}
-			}
-		} else
-			doint = 0;
-		goto conf_childs;
-	}
-
-	type = sym_get_type(sym);
-	if (sym_is_choice(sym)) {
-		struct symbol *def_sym = sym_get_choice_value(sym);
-		struct menu *def_menu = NULL;
-
-		child_count++;
-		for (child = menu->list; child; child = child->next) {
-			if (menu_is_visible(child) && child->sym == def_sym)
-				def_menu = child;
-		}
-
-		val = sym_get_tristate_value(sym);
-		if (sym_is_changeable(sym)) {
-			switch (type) {
-			case S_BOOLEAN:
-				item_make(menu, 't', "[%c]",
-						val == no ? ' ' : '*');
-				break;
-			case S_TRISTATE:
-				switch (val) {
-				case yes:
-					ch = '*';
-					break;
-				case mod:
-					ch = 'M';
-					break;
-				default:
-					ch = ' ';
-					break;
-				}
-				item_make(menu, 't', "<%c>", ch);
-				break;
-			}
-		} else {
-			item_make(menu, def_menu ? 't' : ':', "   ");
-		}
-
-		item_add_str("%*c%s", indent + 1,
-				' ', menu_get_prompt(menu));
-		if (val == yes) {
-			if (def_menu) {
-				item_add_str(" (%s)",
-					menu_get_prompt(def_menu));
-				item_add_str("  --->");
-				if (def_menu->list) {
-					indent += 2;
-					build_conf(def_menu);
-					indent -= 2;
-				}
-			}
-			return;
-		}
-	} else {
-		if (menu == current_menu) {
-			item_make(menu, ':',
-				"---%*c%s", indent + 1,
-				' ', menu_get_prompt(menu));
-			goto conf_childs;
-		}
-		child_count++;
-		val = sym_get_tristate_value(sym);
-		if (sym_is_choice_value(sym) && val == yes) {
-			item_make(menu, ':', "   ");
-		} else {
-			switch (type) {
-			case S_BOOLEAN:
-				if (sym_is_changeable(sym))
-					item_make(menu, 't', "[%c]",
-						val == no ? ' ' : '*');
-				else
-					item_make(menu, 't', "-%c-",
-						val == no ? ' ' : '*');
-				break;
-			case S_TRISTATE:
-				switch (val) {
-				case yes:
-					ch = '*';
-					break;
-				case mod:
-					ch = 'M';
-					break;
-				default:
-					ch = ' ';
-					break;
-				}
-				if (sym_is_changeable(sym)) {
-					if (sym->rev_dep.tri == mod)
-						item_make(menu,
-							't', "{%c}", ch);
-					else
-						item_make(menu,
-							't', "<%c>", ch);
-				} else
-					item_make(menu, 't', "-%c-", ch);
-				break;
-			default:
-				tmp = 2 + strlen(sym_get_string_value(sym));
-				item_make(menu, 's', "    (%s)",
-						sym_get_string_value(sym));
-				tmp = indent - tmp + 4;
-				if (tmp < 0)
-					tmp = 0;
-				item_add_str("%*c%s%s", tmp, ' ',
-						menu_get_prompt(menu),
-						(sym_has_value(sym) ||
-						 !sym_is_changeable(sym)) ? "" :
-						" (NEW)");
-				goto conf_childs;
-			}
-		}
-		item_add_str("%*c%s%s", indent + 1, ' ',
-				menu_get_prompt(menu),
-				(sym_has_value(sym) || !sym_is_changeable(sym)) ?
-				"" : " (NEW)");
-		if (menu->prompt && menu->prompt->type == P_MENU) {
-			item_add_str("  %s", menu_is_empty(menu) ? "----" : "--->");
-			return;
-		}
-	}
-
-conf_childs:
-	indent += doint;
-	for (child = menu->list; child; child = child->next)
-		build_conf(child);
-	indent -= doint;
-}
-
-static void reset_menu(void)
-{
-	unpost_menu(curses_menu);
-	clean_items();
-}
-
-/* adjust the menu to show this item.
- * prefer not to scroll the menu if possible*/
-static void center_item(int selected_index, int *last_top_row)
-{
-	int toprow;
-
-	set_top_row(curses_menu, *last_top_row);
-	toprow = top_row(curses_menu);
-	if (selected_index < toprow ||
-	    selected_index >= toprow+mwin_max_lines) {
-		toprow = max(selected_index-mwin_max_lines/2, 0);
-		if (toprow >= item_count(curses_menu)-mwin_max_lines)
-			toprow = item_count(curses_menu)-mwin_max_lines;
-		set_top_row(curses_menu, toprow);
-	}
-	set_current_item(curses_menu,
-			curses_menu_items[selected_index]);
-	*last_top_row = toprow;
-	post_menu(curses_menu);
-	refresh_all_windows(main_window);
-}
-
-/* this function assumes reset_menu has been called before */
-static void show_menu(const char *prompt, const char *instructions,
-		int selected_index, int *last_top_row)
-{
-	int maxx, maxy;
-	WINDOW *menu_window;
-
-	current_instructions = instructions;
-
-	clear();
-	(void) wattrset(main_window, attributes[NORMAL]);
-	print_in_middle(stdscr, 1, 0, getmaxx(stdscr),
-			menu_backtitle,
-			attributes[MAIN_HEADING]);
-
-	(void) wattrset(main_window, attributes[MAIN_MENU_BOX]);
-	box(main_window, 0, 0);
-	(void) wattrset(main_window, attributes[MAIN_MENU_HEADING]);
-	mvwprintw(main_window, 0, 3, " %s ", prompt);
-	(void) wattrset(main_window, attributes[NORMAL]);
-
-	set_menu_items(curses_menu, curses_menu_items);
-
-	/* position the menu at the middle of the screen */
-	scale_menu(curses_menu, &maxy, &maxx);
-	maxx = min(maxx, mwin_max_cols-2);
-	maxy = mwin_max_lines;
-	menu_window = derwin(main_window,
-			maxy,
-			maxx,
-			2,
-			(mwin_max_cols-maxx)/2);
-	keypad(menu_window, TRUE);
-	set_menu_win(curses_menu, menu_window);
-	set_menu_sub(curses_menu, menu_window);
-
-	/* must reassert this after changing items, otherwise returns to a
-	 * default of 16
-	 */
-	set_menu_format(curses_menu, maxy, 1);
-	center_item(selected_index, last_top_row);
-	set_menu_format(curses_menu, maxy, 1);
-
-	print_function_line();
-
-	/* Post the menu */
-	post_menu(curses_menu);
-	refresh_all_windows(main_window);
-}
-
-static void adj_match_dir(match_f *match_direction)
-{
-	if (*match_direction == FIND_NEXT_MATCH_DOWN)
-		*match_direction =
-			MATCH_TINKER_PATTERN_DOWN;
-	else if (*match_direction == FIND_NEXT_MATCH_UP)
-		*match_direction =
-			MATCH_TINKER_PATTERN_UP;
-	/* else, do no change.. */
-}
-
-struct match_state
-{
-	int in_search;
-	match_f match_direction;
-	char pattern[256];
-};
-
-/* Return 0 means I have handled the key. In such a case, ans should hold the
- * item to center, or -1 otherwise.
- * Else return -1 .
- */
-static int do_match(int key, struct match_state *state, int *ans)
-{
-	char c = (char) key;
-	int terminate_search = 0;
-	*ans = -1;
-	if (key == '/' || (state->in_search && key == 27)) {
-		move(0, 0);
-		refresh();
-		clrtoeol();
-		state->in_search = 1-state->in_search;
-		bzero(state->pattern, sizeof(state->pattern));
-		state->match_direction = MATCH_TINKER_PATTERN_DOWN;
-		return 0;
-	} else if (!state->in_search)
-		return 1;
-
-	if (isalnum(c) || isgraph(c) || c == ' ') {
-		state->pattern[strlen(state->pattern)] = c;
-		state->pattern[strlen(state->pattern)] = '\0';
-		adj_match_dir(&state->match_direction);
-		*ans = get_mext_match(state->pattern,
-				state->match_direction);
-	} else if (key == KEY_DOWN) {
-		state->match_direction = FIND_NEXT_MATCH_DOWN;
-		*ans = get_mext_match(state->pattern,
-				state->match_direction);
-	} else if (key == KEY_UP) {
-		state->match_direction = FIND_NEXT_MATCH_UP;
-		*ans = get_mext_match(state->pattern,
-				state->match_direction);
-	} else if (key == KEY_BACKSPACE || key == 8 || key == 127) {
-		state->pattern[strlen(state->pattern)-1] = '\0';
-		adj_match_dir(&state->match_direction);
-	} else
-		terminate_search = 1;
-
-	if (terminate_search) {
-		state->in_search = 0;
-		bzero(state->pattern, sizeof(state->pattern));
-		move(0, 0);
-		refresh();
-		clrtoeol();
-		return -1;
-	}
-	return 0;
-}
-
-static void conf(struct menu *menu)
-{
-	struct menu *submenu = NULL;
-	const char *prompt = menu_get_prompt(menu);
-	struct symbol *sym;
-	int res;
-	int current_index = 0;
-	int last_top_row = 0;
-	struct match_state match_state = {
-		.in_search = 0,
-		.match_direction = MATCH_TINKER_PATTERN_DOWN,
-		.pattern = "",
-	};
-
-	while (!global_exit) {
-		reset_menu();
-		current_menu = menu;
-		build_conf(menu);
-		if (!child_count)
-			break;
-
-		show_menu(prompt ? prompt : "Main Menu",
-				menu_instructions,
-				current_index, &last_top_row);
-		keypad((menu_win(curses_menu)), TRUE);
-		while (!global_exit) {
-			if (match_state.in_search) {
-				mvprintw(0, 0,
-					"searching: %s", match_state.pattern);
-				clrtoeol();
-			}
-			refresh_all_windows(main_window);
-			res = wgetch(menu_win(curses_menu));
-			if (!res)
-				break;
-			if (do_match(res, &match_state, &current_index) == 0) {
-				if (current_index != -1)
-					center_item(current_index,
-						    &last_top_row);
-				continue;
-			}
-			if (process_special_keys(&res,
-						(struct menu *) item_data()))
-				break;
-			switch (res) {
-			case KEY_DOWN:
-				menu_driver(curses_menu, REQ_DOWN_ITEM);
-				break;
-			case KEY_UP:
-				menu_driver(curses_menu, REQ_UP_ITEM);
-				break;
-			case KEY_NPAGE:
-				menu_driver(curses_menu, REQ_SCR_DPAGE);
-				break;
-			case KEY_PPAGE:
-				menu_driver(curses_menu, REQ_SCR_UPAGE);
-				break;
-			case KEY_HOME:
-				menu_driver(curses_menu, REQ_FIRST_ITEM);
-				break;
-			case KEY_END:
-				menu_driver(curses_menu, REQ_LAST_ITEM);
-				break;
-			case 'h':
-			case '?':
-				show_help((struct menu *) item_data());
-				break;
-			}
-			if (res == 10 || res == 27 ||
-				res == 32 || res == 'n' || res == 'y' ||
-				res == KEY_LEFT || res == KEY_RIGHT ||
-				res == 'm')
-				break;
-			refresh_all_windows(main_window);
-		}
-
-		refresh_all_windows(main_window);
-		/* if ESC or left*/
-		if (res == 27 || (menu != &rootmenu && res == KEY_LEFT))
-			break;
-
-		/* remember location in the menu */
-		last_top_row = top_row(curses_menu);
-		current_index = curses_item_index();
-
-		if (!item_tag())
-			continue;
-
-		submenu = (struct menu *) item_data();
-		if (!submenu || !menu_is_visible(submenu))
-			continue;
-		sym = submenu->sym;
-
-		switch (res) {
-		case ' ':
-			if (item_is_tag('t'))
-				sym_toggle_tristate_value(sym);
-			else if (item_is_tag('m'))
-				conf(submenu);
-			break;
-		case KEY_RIGHT:
-		case 10: /* ENTER WAS PRESSED */
-			switch (item_tag()) {
-			case 'm':
-				if (single_menu_mode)
-					submenu->data =
-						(void *) (long) !submenu->data;
-				else
-					conf(submenu);
-				break;
-			case 't':
-				if (sym_is_choice(sym) &&
-				    sym_get_tristate_value(sym) == yes)
-					conf_choice(submenu);
-				else if (submenu->prompt &&
-					 submenu->prompt->type == P_MENU)
-					conf(submenu);
-				else if (res == 10)
-					sym_toggle_tristate_value(sym);
-				break;
-			case 's':
-				conf_string(submenu);
-				break;
-			}
-			break;
-		case 'y':
-			if (item_is_tag('t')) {
-				if (sym_set_tristate_value(sym, yes))
-					break;
-				if (sym_set_tristate_value(sym, mod))
-					btn_dialog(main_window, setmod_text, 0);
-			}
-			break;
-		case 'n':
-			if (item_is_tag('t'))
-				sym_set_tristate_value(sym, no);
-			break;
-		case 'm':
-			if (item_is_tag('t'))
-				sym_set_tristate_value(sym, mod);
-			break;
-		}
-	}
-}
-
-static void conf_message_callback(const char *s)
-{
-	btn_dialog(main_window, s, 1, "<OK>");
-}
-
-static void show_help(struct menu *menu)
-{
-	struct gstr help;
-
-	if (!menu)
-		return;
-
-	help = str_new();
-	menu_get_ext_help(menu, &help);
-	show_scroll_win(main_window, menu_get_prompt(menu), str_get(&help));
-	str_free(&help);
-}
-
-static void conf_choice(struct menu *menu)
-{
-	const char *prompt = menu_get_prompt(menu);
-	struct menu *child = NULL;
-	struct symbol *active;
-	int selected_index = 0;
-	int last_top_row = 0;
-	int res, i = 0;
-	struct match_state match_state = {
-		.in_search = 0,
-		.match_direction = MATCH_TINKER_PATTERN_DOWN,
-		.pattern = "",
-	};
-
-	active = sym_get_choice_value(menu->sym);
-	/* this is mostly duplicated from the conf() function. */
-	while (!global_exit) {
-		reset_menu();
-
-		for (i = 0, child = menu->list; child; child = child->next) {
-			if (!show_all_items && !menu_is_visible(child))
-				continue;
-
-			if (child->sym == sym_get_choice_value(menu->sym))
-				item_make(child, ':', "<X> %s",
-						menu_get_prompt(child));
-			else if (child->sym)
-				item_make(child, ':', "    %s",
-						menu_get_prompt(child));
-			else
-				item_make(child, ':', "*** %s ***",
-						menu_get_prompt(child));
-
-			if (child->sym == active){
-				last_top_row = top_row(curses_menu);
-				selected_index = i;
-			}
-			i++;
-		}
-		show_menu(prompt ? prompt : "Choice Menu",
-				radiolist_instructions,
-				selected_index,
-				&last_top_row);
-		while (!global_exit) {
-			if (match_state.in_search) {
-				mvprintw(0, 0, "searching: %s",
-					 match_state.pattern);
-				clrtoeol();
-			}
-			refresh_all_windows(main_window);
-			res = wgetch(menu_win(curses_menu));
-			if (!res)
-				break;
-			if (do_match(res, &match_state, &selected_index) == 0) {
-				if (selected_index != -1)
-					center_item(selected_index,
-						    &last_top_row);
-				continue;
-			}
-			if (process_special_keys(
-						&res,
-						(struct menu *) item_data()))
-				break;
-			switch (res) {
-			case KEY_DOWN:
-				menu_driver(curses_menu, REQ_DOWN_ITEM);
-				break;
-			case KEY_UP:
-				menu_driver(curses_menu, REQ_UP_ITEM);
-				break;
-			case KEY_NPAGE:
-				menu_driver(curses_menu, REQ_SCR_DPAGE);
-				break;
-			case KEY_PPAGE:
-				menu_driver(curses_menu, REQ_SCR_UPAGE);
-				break;
-			case KEY_HOME:
-				menu_driver(curses_menu, REQ_FIRST_ITEM);
-				break;
-			case KEY_END:
-				menu_driver(curses_menu, REQ_LAST_ITEM);
-				break;
-			case 'h':
-			case '?':
-				show_help((struct menu *) item_data());
-				break;
-			}
-			if (res == 10 || res == 27 || res == ' ' ||
-					res == KEY_LEFT){
-				break;
-			}
-			refresh_all_windows(main_window);
-		}
-		/* if ESC or left */
-		if (res == 27 || res == KEY_LEFT)
-			break;
-
-		child = item_data();
-		if (!child || !menu_is_visible(child) || !child->sym)
-			continue;
-		switch (res) {
-		case ' ':
-		case  10:
-		case KEY_RIGHT:
-			sym_set_tristate_value(child->sym, yes);
-			return;
-		case 'h':
-		case '?':
-			show_help(child);
-			active = child->sym;
-			break;
-		case KEY_EXIT:
-			return;
-		}
-	}
-}
-
-static void conf_string(struct menu *menu)
-{
-	const char *prompt = menu_get_prompt(menu);
-
-	while (1) {
-		int res;
-		const char *heading;
-
-		switch (sym_get_type(menu->sym)) {
-		case S_INT:
-			heading = inputbox_instructions_int;
-			break;
-		case S_HEX:
-			heading = inputbox_instructions_hex;
-			break;
-		case S_STRING:
-			heading = inputbox_instructions_string;
-			break;
-		default:
-			heading = "Internal nconf error!";
-		}
-		res = dialog_inputbox(main_window,
-				prompt ? prompt : "Main Menu",
-				heading,
-				sym_get_string_value(menu->sym),
-				&dialog_input_result,
-				&dialog_input_result_len);
-		switch (res) {
-		case 0:
-			if (sym_set_string_value(menu->sym,
-						dialog_input_result))
-				return;
-			btn_dialog(main_window,
-				"You have made an invalid entry.", 0);
-			break;
-		case 1:
-			show_help(menu);
-			break;
-		case KEY_EXIT:
-			return;
-		}
-	}
-}
-
-static void conf_load(void)
-{
-	while (1) {
-		int res;
-		res = dialog_inputbox(main_window,
-				NULL, load_config_text,
-				filename,
-				&dialog_input_result,
-				&dialog_input_result_len);
-		switch (res) {
-		case 0:
-			if (!dialog_input_result[0])
-				return;
-			if (!conf_read(dialog_input_result)) {
-				set_config_filename(dialog_input_result);
-				sym_set_change_count(1);
-				return;
-			}
-			btn_dialog(main_window, "File does not exist!", 0);
-			break;
-		case 1:
-			show_scroll_win(main_window,
-					"Load Alternate Configuration",
-					load_config_help);
-			break;
-		case KEY_EXIT:
-			return;
-		}
-	}
-}
-
-static void conf_save(void)
-{
-	while (1) {
-		int res;
-		res = dialog_inputbox(main_window,
-				NULL, save_config_text,
-				filename,
-				&dialog_input_result,
-				&dialog_input_result_len);
-		switch (res) {
-		case 0:
-			if (!dialog_input_result[0])
-				return;
-			res = conf_write(dialog_input_result);
-			if (!res) {
-				set_config_filename(dialog_input_result);
-				return;
-			}
-			btn_dialog(main_window, "Can't create file!",
-				1, "<OK>");
-			break;
-		case 1:
-			show_scroll_win(main_window,
-				"Save Alternate Configuration",
-				save_config_help);
-			break;
-		case KEY_EXIT:
-			return;
-		}
-	}
-}
-
-static void setup_windows(void)
-{
-	int lines, columns;
-
-	getmaxyx(stdscr, lines, columns);
-
-	if (main_window != NULL)
-		delwin(main_window);
-
-	/* set up the menu and menu window */
-	main_window = newwin(lines-2, columns-2, 2, 1);
-	keypad(main_window, TRUE);
-	mwin_max_lines = lines-7;
-	mwin_max_cols = columns-6;
-
-	/* panels order is from bottom to top */
-	new_panel(main_window);
-}
-
-int main(int ac, char **av)
-{
-	int lines, columns;
-	char *mode;
-
-	if (ac > 1 && strcmp(av[1], "-s") == 0) {
-		/* Silence conf_read() until the real callback is set up */
-		conf_set_message_callback(NULL);
-		av++;
-	}
-	conf_parse(av[1]);
-	conf_read(NULL);
-
-	mode = getenv("NCONFIG_MODE");
-	if (mode) {
-		if (!strcasecmp(mode, "single_menu"))
-			single_menu_mode = 1;
-	}
-
-	/* Initialize curses */
-	initscr();
-	/* set color theme */
-	set_colors();
-
-	cbreak();
-	noecho();
-	keypad(stdscr, TRUE);
-	curs_set(0);
-
-	getmaxyx(stdscr, lines, columns);
-	if (columns < 75 || lines < 20) {
-		endwin();
-		printf("Your terminal should have at "
-			"least 20 lines and 75 columns\n");
-		return 1;
-	}
-
-	notimeout(stdscr, FALSE);
-#if NCURSES_REENTRANT
-	set_escdelay(1);
-#else
-	ESCDELAY = 1;
-#endif
-
-	/* set btns menu */
-	curses_menu = new_menu(curses_menu_items);
-	menu_opts_off(curses_menu, O_SHOWDESC);
-	menu_opts_on(curses_menu, O_SHOWMATCH);
-	menu_opts_on(curses_menu, O_ONEVALUE);
-	menu_opts_on(curses_menu, O_NONCYCLIC);
-	menu_opts_on(curses_menu, O_IGNORECASE);
-	set_menu_mark(curses_menu, " ");
-	set_menu_fore(curses_menu, attributes[MAIN_MENU_FORE]);
-	set_menu_back(curses_menu, attributes[MAIN_MENU_BACK]);
-	set_menu_grey(curses_menu, attributes[MAIN_MENU_GREY]);
-
-	set_config_filename(conf_get_configname());
-	setup_windows();
-
-	/* check for KEY_FUNC(1) */
-	if (has_key(KEY_F(1)) == FALSE) {
-		show_scroll_win(main_window,
-				"Instructions",
-				menu_no_f_instructions);
-	}
-
-	conf_set_message_callback(conf_message_callback);
-	/* do the work */
-	while (!global_exit) {
-		conf(&rootmenu);
-		if (!global_exit && do_exit() == 0)
-			break;
-	}
-	/* ok, we are done */
-	unpost_menu(curses_menu);
-	free_menu(curses_menu);
-	delwin(main_window);
-	clear();
-	refresh();
-	endwin();
-	return 0;
-}
diff --git a/util/kconfig/nconf.gui.c b/util/kconfig/nconf.gui.c
deleted file mode 100644
index 77f525a861..0000000000
--- a/util/kconfig/nconf.gui.c
+++ /dev/null
@@ -1,664 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2008 Nir Tzachar <nir.tzachar@gmail.com>
- *
- * Derived from menuconfig.
- */
-#include "nconf.h"
-#include "lkc.h"
-
-/* a list of all the different widgets we use */
-attributes_t attributes[ATTR_MAX+1] = {0};
-
-/* available colors:
-   COLOR_BLACK   0
-   COLOR_RED     1
-   COLOR_GREEN   2
-   COLOR_YELLOW  3
-   COLOR_BLUE    4
-   COLOR_MAGENTA 5
-   COLOR_CYAN    6
-   COLOR_WHITE   7
-   */
-static void set_normal_colors(void)
-{
-	init_pair(NORMAL, -1, -1);
-	init_pair(MAIN_HEADING, COLOR_MAGENTA, -1);
-
-	/* FORE is for the selected item */
-	init_pair(MAIN_MENU_FORE, -1, -1);
-	/* BACK for all the rest */
-	init_pair(MAIN_MENU_BACK, -1, -1);
-	init_pair(MAIN_MENU_GREY, -1, -1);
-	init_pair(MAIN_MENU_HEADING, COLOR_GREEN, -1);
-	init_pair(MAIN_MENU_BOX, COLOR_YELLOW, -1);
-
-	init_pair(SCROLLWIN_TEXT, -1, -1);
-	init_pair(SCROLLWIN_HEADING, COLOR_GREEN, -1);
-	init_pair(SCROLLWIN_BOX, COLOR_YELLOW, -1);
-
-	init_pair(DIALOG_TEXT, -1, -1);
-	init_pair(DIALOG_BOX, COLOR_YELLOW, -1);
-	init_pair(DIALOG_MENU_BACK, COLOR_YELLOW, -1);
-	init_pair(DIALOG_MENU_FORE, COLOR_RED, -1);
-
-	init_pair(INPUT_BOX, COLOR_YELLOW, -1);
-	init_pair(INPUT_HEADING, COLOR_GREEN, -1);
-	init_pair(INPUT_TEXT, -1, -1);
-	init_pair(INPUT_FIELD, -1, -1);
-
-	init_pair(FUNCTION_HIGHLIGHT, -1, -1);
-	init_pair(FUNCTION_TEXT, COLOR_YELLOW, -1);
-}
-
-/* available attributes:
-   A_NORMAL        Normal display (no highlight)
-   A_STANDOUT      Best highlighting mode of the terminal.
-   A_UNDERLINE     Underlining
-   A_REVERSE       Reverse video
-   A_BLINK         Blinking
-   A_DIM           Half bright
-   A_BOLD          Extra bright or bold
-   A_PROTECT       Protected mode
-   A_INVIS         Invisible or blank mode
-   A_ALTCHARSET    Alternate character set
-   A_CHARTEXT      Bit-mask to extract a character
-   COLOR_PAIR(n)   Color-pair number n
-   */
-static void normal_color_theme(void)
-{
-	/* automatically add color... */
-#define mkattr(name, attr) do { \
-attributes[name] = attr | COLOR_PAIR(name); } while (0)
-	mkattr(NORMAL, NORMAL);
-	mkattr(MAIN_HEADING, A_BOLD | A_UNDERLINE);
-
-	mkattr(MAIN_MENU_FORE, A_REVERSE);
-	mkattr(MAIN_MENU_BACK, A_NORMAL);
-	mkattr(MAIN_MENU_GREY, A_NORMAL);
-	mkattr(MAIN_MENU_HEADING, A_BOLD);
-	mkattr(MAIN_MENU_BOX, A_NORMAL);
-
-	mkattr(SCROLLWIN_TEXT, A_NORMAL);
-	mkattr(SCROLLWIN_HEADING, A_BOLD);
-	mkattr(SCROLLWIN_BOX, A_BOLD);
-
-	mkattr(DIALOG_TEXT, A_BOLD);
-	mkattr(DIALOG_BOX, A_BOLD);
-	mkattr(DIALOG_MENU_FORE, A_STANDOUT);
-	mkattr(DIALOG_MENU_BACK, A_NORMAL);
-
-	mkattr(INPUT_BOX, A_NORMAL);
-	mkattr(INPUT_HEADING, A_BOLD);
-	mkattr(INPUT_TEXT, A_NORMAL);
-	mkattr(INPUT_FIELD, A_UNDERLINE);
-
-	mkattr(FUNCTION_HIGHLIGHT, A_BOLD);
-	mkattr(FUNCTION_TEXT, A_REVERSE);
-}
-
-static void no_colors_theme(void)
-{
-	/* automatically add highlight, no color */
-#define mkattrn(name, attr) { attributes[name] = attr; }
-
-	mkattrn(NORMAL, NORMAL);
-	mkattrn(MAIN_HEADING, A_BOLD | A_UNDERLINE);
-
-	mkattrn(MAIN_MENU_FORE, A_STANDOUT);
-	mkattrn(MAIN_MENU_BACK, A_NORMAL);
-	mkattrn(MAIN_MENU_GREY, A_NORMAL);
-	mkattrn(MAIN_MENU_HEADING, A_BOLD);
-	mkattrn(MAIN_MENU_BOX, A_NORMAL);
-
-	mkattrn(SCROLLWIN_TEXT, A_NORMAL);
-	mkattrn(SCROLLWIN_HEADING, A_BOLD);
-	mkattrn(SCROLLWIN_BOX, A_BOLD);
-
-	mkattrn(DIALOG_TEXT, A_NORMAL);
-	mkattrn(DIALOG_BOX, A_BOLD);
-	mkattrn(DIALOG_MENU_FORE, A_STANDOUT);
-	mkattrn(DIALOG_MENU_BACK, A_NORMAL);
-
-	mkattrn(INPUT_BOX, A_BOLD);
-	mkattrn(INPUT_HEADING, A_BOLD);
-	mkattrn(INPUT_TEXT, A_NORMAL);
-	mkattrn(INPUT_FIELD, A_UNDERLINE);
-
-	mkattrn(FUNCTION_HIGHLIGHT, A_BOLD);
-	mkattrn(FUNCTION_TEXT, A_REVERSE);
-}
-
-void set_colors(void)
-{
-	start_color();
-	use_default_colors();
-	set_normal_colors();
-	if (has_colors()) {
-		normal_color_theme();
-	} else {
-		/* give defaults */
-		no_colors_theme();
-	}
-}
-
-
-/* this changes the windows attributes !!! */
-void print_in_middle(WINDOW *win,
-		int starty,
-		int startx,
-		int width,
-		const char *string,
-		chtype color)
-{      int length, x, y;
-	float temp;
-
-
-	if (win == NULL)
-		win = stdscr;
-	getyx(win, y, x);
-	if (startx != 0)
-		x = startx;
-	if (starty != 0)
-		y = starty;
-	if (width == 0)
-		width = 80;
-
-	length = strlen(string);
-	temp = (width - length) / 2;
-	x = startx + (int)temp;
-	(void) wattrset(win, color);
-	mvwprintw(win, y, x, "%s", string);
-	refresh();
-}
-
-int get_line_no(const char *text)
-{
-	int i;
-	int total = 1;
-
-	if (!text)
-		return 0;
-
-	for (i = 0; text[i] != '\0'; i++)
-		if (text[i] == '\n')
-			total++;
-	return total;
-}
-
-const char *get_line(const char *text, int line_no)
-{
-	int i;
-	int lines = 0;
-
-	if (!text)
-		return NULL;
-
-	for (i = 0; text[i] != '\0' && lines < line_no; i++)
-		if (text[i] == '\n')
-			lines++;
-	return text+i;
-}
-
-int get_line_length(const char *line)
-{
-	int res = 0;
-	while (*line != '\0' && *line != '\n') {
-		line++;
-		res++;
-	}
-	return res;
-}
-
-/* print all lines to the window. */
-void fill_window(WINDOW *win, const char *text)
-{
-	int x, y;
-	int total_lines = get_line_no(text);
-	int i;
-
-	getmaxyx(win, y, x);
-	/* do not go over end of line */
-	total_lines = min(total_lines, y);
-	for (i = 0; i < total_lines; i++) {
-		char tmp[x+10];
-		const char *line = get_line(text, i);
-		int len = get_line_length(line);
-		strncpy(tmp, line, min(len, x));
-		tmp[len] = '\0';
-		mvwprintw(win, i, 0, "%s", tmp);
-	}
-}
-
-/* get the message, and buttons.
- * each button must be a char*
- * return the selected button
- *
- * this dialog is used for 2 different things:
- * 1) show a text box, no buttons.
- * 2) show a dialog, with horizontal buttons
- */
-int btn_dialog(WINDOW *main_window, const char *msg, int btn_num, ...)
-{
-	va_list ap;
-	char *btn;
-	int btns_width = 0;
-	int msg_lines = 0;
-	int msg_width = 0;
-	int total_width;
-	int win_rows = 0;
-	WINDOW *win;
-	WINDOW *msg_win;
-	WINDOW *menu_win;
-	MENU *menu;
-	ITEM *btns[btn_num+1];
-	int i, x, y;
-	int res = -1;
-
-
-	va_start(ap, btn_num);
-	for (i = 0; i < btn_num; i++) {
-		btn = va_arg(ap, char *);
-		btns[i] = new_item(btn, "");
-		btns_width += strlen(btn)+1;
-	}
-	va_end(ap);
-	btns[btn_num] = NULL;
-
-	/* find the widest line of msg: */
-	msg_lines = get_line_no(msg);
-	for (i = 0; i < msg_lines; i++) {
-		const char *line = get_line(msg, i);
-		int len = get_line_length(line);
-		if (msg_width < len)
-			msg_width = len;
-	}
-
-	total_width = max(msg_width, btns_width);
-	/* place dialog in middle of screen */
-	y = (getmaxy(stdscr)-(msg_lines+4))/2;
-	x = (getmaxx(stdscr)-(total_width+4))/2;
-
-
-	/* create the windows */
-	if (btn_num > 0)
-		win_rows = msg_lines+4;
-	else
-		win_rows = msg_lines+2;
-
-	win = newwin(win_rows, total_width+4, y, x);
-	keypad(win, TRUE);
-	menu_win = derwin(win, 1, btns_width, win_rows-2,
-			1+(total_width+2-btns_width)/2);
-	menu = new_menu(btns);
-	msg_win = derwin(win, win_rows-2, msg_width, 1,
-			1+(total_width+2-msg_width)/2);
-
-	set_menu_fore(menu, attributes[DIALOG_MENU_FORE]);
-	set_menu_back(menu, attributes[DIALOG_MENU_BACK]);
-
-	(void) wattrset(win, attributes[DIALOG_BOX]);
-	box(win, 0, 0);
-
-	/* print message */
-	(void) wattrset(msg_win, attributes[DIALOG_TEXT]);
-	fill_window(msg_win, msg);
-
-	set_menu_win(menu, win);
-	set_menu_sub(menu, menu_win);
-	set_menu_format(menu, 1, btn_num);
-	menu_opts_off(menu, O_SHOWDESC);
-	menu_opts_off(menu, O_SHOWMATCH);
-	menu_opts_on(menu, O_ONEVALUE);
-	menu_opts_on(menu, O_NONCYCLIC);
-	set_menu_mark(menu, "");
-	post_menu(menu);
-
-
-	touchwin(win);
-	refresh_all_windows(main_window);
-	while ((res = wgetch(win))) {
-		switch (res) {
-		case KEY_LEFT:
-			menu_driver(menu, REQ_LEFT_ITEM);
-			break;
-		case KEY_RIGHT:
-			menu_driver(menu, REQ_RIGHT_ITEM);
-			break;
-		case 10: /* ENTER */
-		case 27: /* ESCAPE */
-		case ' ':
-		case KEY_F(F_BACK):
-		case KEY_F(F_EXIT):
-			break;
-		}
-		touchwin(win);
-		refresh_all_windows(main_window);
-
-		if (res == 10 || res == ' ') {
-			res = item_index(current_item(menu));
-			break;
-		} else if (res == 27 || res == KEY_F(F_BACK) ||
-				res == KEY_F(F_EXIT)) {
-			res = KEY_EXIT;
-			break;
-		}
-	}
-
-	unpost_menu(menu);
-	free_menu(menu);
-	for (i = 0; i < btn_num; i++)
-		free_item(btns[i]);
-
-	delwin(win);
-	return res;
-}
-
-int dialog_inputbox(WINDOW *main_window,
-		const char *title, const char *prompt,
-		const char *init, char **resultp, int *result_len)
-{
-	int prompt_lines = 0;
-	int prompt_width = 0;
-	WINDOW *win;
-	WINDOW *prompt_win;
-	WINDOW *form_win;
-	PANEL *panel;
-	int i, x, y, lines, columns, win_lines, win_cols;
-	int res = -1;
-	int cursor_position = strlen(init);
-	int cursor_form_win;
-	char *result = *resultp;
-
-	getmaxyx(stdscr, lines, columns);
-
-	if (strlen(init)+1 > *result_len) {
-		*result_len = strlen(init)+1;
-		*resultp = result = xrealloc(result, *result_len);
-	}
-
-	/* find the widest line of msg: */
-	prompt_lines = get_line_no(prompt);
-	for (i = 0; i < prompt_lines; i++) {
-		const char *line = get_line(prompt, i);
-		int len = get_line_length(line);
-		prompt_width = max(prompt_width, len);
-	}
-
-	if (title)
-		prompt_width = max(prompt_width, strlen(title));
-
-	win_lines = min(prompt_lines+6, lines-2);
-	win_cols = min(prompt_width+7, columns-2);
-	prompt_lines = max(win_lines-6, 0);
-	prompt_width = max(win_cols-7, 0);
-
-	/* place dialog in middle of screen */
-	y = (lines-win_lines)/2;
-	x = (columns-win_cols)/2;
-
-	strncpy(result, init, *result_len);
-
-	/* create the windows */
-	win = newwin(win_lines, win_cols, y, x);
-	prompt_win = derwin(win, prompt_lines+1, prompt_width, 2, 2);
-	form_win = derwin(win, 1, prompt_width, prompt_lines+3, 2);
-	keypad(form_win, TRUE);
-
-	(void) wattrset(form_win, attributes[INPUT_FIELD]);
-
-	(void) wattrset(win, attributes[INPUT_BOX]);
-	box(win, 0, 0);
-	(void) wattrset(win, attributes[INPUT_HEADING]);
-	if (title)
-		mvwprintw(win, 0, 3, "%s", title);
-
-	/* print message */
-	(void) wattrset(prompt_win, attributes[INPUT_TEXT]);
-	fill_window(prompt_win, prompt);
-
-	mvwprintw(form_win, 0, 0, "%*s", prompt_width, " ");
-	cursor_form_win = min(cursor_position, prompt_width-1);
-	mvwprintw(form_win, 0, 0, "%s",
-		  result + cursor_position-cursor_form_win);
-
-	/* create panels */
-	panel = new_panel(win);
-
-	/* show the cursor */
-	curs_set(1);
-
-	touchwin(win);
-	refresh_all_windows(main_window);
-	while ((res = wgetch(form_win))) {
-		int len = strlen(result);
-		switch (res) {
-		case 10: /* ENTER */
-		case 27: /* ESCAPE */
-		case KEY_F(F_HELP):
-		case KEY_F(F_EXIT):
-		case KEY_F(F_BACK):
-			break;
-		case 8:   /* ^H */
-		case 127: /* ^? */
-		case KEY_BACKSPACE:
-			if (cursor_position > 0) {
-				memmove(&result[cursor_position-1],
-						&result[cursor_position],
-						len-cursor_position+1);
-				cursor_position--;
-				cursor_form_win--;
-				len--;
-			}
-			break;
-		case KEY_DC:
-			if (cursor_position >= 0 && cursor_position < len) {
-				memmove(&result[cursor_position],
-						&result[cursor_position+1],
-						len-cursor_position+1);
-				len--;
-			}
-			break;
-		case KEY_UP:
-		case KEY_RIGHT:
-			if (cursor_position < len) {
-				cursor_position++;
-				cursor_form_win++;
-			}
-			break;
-		case KEY_DOWN:
-		case KEY_LEFT:
-			if (cursor_position > 0) {
-				cursor_position--;
-				cursor_form_win--;
-			}
-			break;
-		case KEY_HOME:
-			cursor_position = 0;
-			cursor_form_win = 0;
-			break;
-		case KEY_END:
-			cursor_position = len;
-			cursor_form_win = min(cursor_position, prompt_width-1);
-			break;
-		default:
-			if ((isgraph(res) || isspace(res))) {
-				/* one for new char, one for '\0' */
-				if (len+2 > *result_len) {
-					*result_len = len+2;
-					*resultp = result = realloc(result,
-								*result_len);
-				}
-				/* insert the char at the proper position */
-				memmove(&result[cursor_position+1],
-						&result[cursor_position],
-						len-cursor_position+1);
-				result[cursor_position] = res;
-				cursor_position++;
-				cursor_form_win++;
-				len++;
-			} else {
-				mvprintw(0, 0, "unknown key: %d\n", res);
-			}
-			break;
-		}
-		if (cursor_form_win < 0)
-			cursor_form_win = 0;
-		else if (cursor_form_win > prompt_width-1)
-			cursor_form_win = prompt_width-1;
-
-		wmove(form_win, 0, 0);
-		wclrtoeol(form_win);
-		mvwprintw(form_win, 0, 0, "%*s", prompt_width, " ");
-		mvwprintw(form_win, 0, 0, "%s",
-			result + cursor_position-cursor_form_win);
-		wmove(form_win, 0, cursor_form_win);
-		touchwin(win);
-		refresh_all_windows(main_window);
-
-		if (res == 10) {
-			res = 0;
-			break;
-		} else if (res == 27 || res == KEY_F(F_BACK) ||
-				res == KEY_F(F_EXIT)) {
-			res = KEY_EXIT;
-			break;
-		} else if (res == KEY_F(F_HELP)) {
-			res = 1;
-			break;
-		}
-	}
-
-	/* hide the cursor */
-	curs_set(0);
-	del_panel(panel);
-	delwin(prompt_win);
-	delwin(form_win);
-	delwin(win);
-	return res;
-}
-
-/* refresh all windows in the correct order */
-void refresh_all_windows(WINDOW *main_window)
-{
-	update_panels();
-	touchwin(main_window);
-	refresh();
-}
-
-/* layman's scrollable window... */
-void show_scroll_win(WINDOW *main_window,
-		const char *title,
-		const char *text)
-{
-	int res;
-	int total_lines = get_line_no(text);
-	int x, y, lines, columns;
-	int start_x = 0, start_y = 0;
-	int text_lines = 0, text_cols = 0;
-	int total_cols = 0;
-	int win_cols = 0;
-	int win_lines = 0;
-	int i = 0;
-	WINDOW *win;
-	WINDOW *pad;
-	PANEL *panel;
-
-	getmaxyx(stdscr, lines, columns);
-
-	/* find the widest line of msg: */
-	total_lines = get_line_no(text);
-	for (i = 0; i < total_lines; i++) {
-		const char *line = get_line(text, i);
-		int len = get_line_length(line);
-		total_cols = max(total_cols, len+2);
-	}
-
-	/* create the pad */
-	pad = newpad(total_lines+10, total_cols+10);
-	(void) wattrset(pad, attributes[SCROLLWIN_TEXT]);
-	fill_window(pad, text);
-
-	win_lines = min(total_lines+4, lines-2);
-	win_cols = min(total_cols+2, columns-2);
-	text_lines = max(win_lines-4, 0);
-	text_cols = max(win_cols-2, 0);
-
-	/* place window in middle of screen */
-	y = (lines-win_lines)/2;
-	x = (columns-win_cols)/2;
-
-	win = newwin(win_lines, win_cols, y, x);
-	keypad(win, TRUE);
-	/* show the help in the help window, and show the help panel */
-	(void) wattrset(win, attributes[SCROLLWIN_BOX]);
-	box(win, 0, 0);
-	(void) wattrset(win, attributes[SCROLLWIN_HEADING]);
-	mvwprintw(win, 0, 3, " %s ", title);
-	panel = new_panel(win);
-
-	/* handle scrolling */
-	do {
-
-		copywin(pad, win, start_y, start_x, 2, 2, text_lines,
-				text_cols, 0);
-		print_in_middle(win,
-				text_lines+2,
-				0,
-				text_cols,
-				"<OK>",
-				attributes[DIALOG_MENU_FORE]);
-		wrefresh(win);
-
-		res = wgetch(win);
-		switch (res) {
-		case KEY_NPAGE:
-		case ' ':
-		case 'd':
-			start_y += text_lines-2;
-			break;
-		case KEY_PPAGE:
-		case 'u':
-			start_y -= text_lines+2;
-			break;
-		case KEY_HOME:
-			start_y = 0;
-			break;
-		case KEY_END:
-			start_y = total_lines-text_lines;
-			break;
-		case KEY_DOWN:
-		case 'j':
-			start_y++;
-			break;
-		case KEY_UP:
-		case 'k':
-			start_y--;
-			break;
-		case KEY_LEFT:
-		case 'h':
-			start_x--;
-			break;
-		case KEY_RIGHT:
-		case 'l':
-			start_x++;
-			break;
-		}
-		if (res == 10 || res == 27 || res == 'q' ||
-			res == KEY_F(F_HELP) || res == KEY_F(F_BACK) ||
-			res == KEY_F(F_EXIT))
-			break;
-		if (start_y < 0)
-			start_y = 0;
-		if (start_y >= total_lines-text_lines)
-			start_y = total_lines-text_lines;
-		if (start_x < 0)
-			start_x = 0;
-		if (start_x >= total_cols-text_cols)
-			start_x = total_cols-text_cols;
-	} while (res);
-
-	del_panel(panel);
-	delwin(win);
-	refresh_all_windows(main_window);
-}
diff --git a/util/kconfig/nconf.h b/util/kconfig/nconf.h
deleted file mode 100644
index fa5245eb93..0000000000
--- a/util/kconfig/nconf.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2008 Nir Tzachar <nir.tzachar@gmail.com>
- *
- * Derived from menuconfig.
- */
-
-#include <ctype.h>
-#include <errno.h>
-#include <fcntl.h>
-#include <limits.h>
-#include <stdarg.h>
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
-#include <ncurses.h>
-#include <menu.h>
-#include <panel.h>
-#include <form.h>
-
-#include <stdio.h>
-#include <time.h>
-#include <sys/time.h>
-
-#define max(a, b) ({\
-		typeof(a) _a = a;\
-		typeof(b) _b = b;\
-		_a > _b ? _a : _b; })
-
-#define min(a, b) ({\
-		typeof(a) _a = a;\
-		typeof(b) _b = b;\
-		_a < _b ? _a : _b; })
-
-typedef enum {
-	NORMAL = 1,
-	MAIN_HEADING,
-	MAIN_MENU_BOX,
-	MAIN_MENU_FORE,
-	MAIN_MENU_BACK,
-	MAIN_MENU_GREY,
-	MAIN_MENU_HEADING,
-	SCROLLWIN_TEXT,
-	SCROLLWIN_HEADING,
-	SCROLLWIN_BOX,
-	DIALOG_TEXT,
-	DIALOG_MENU_FORE,
-	DIALOG_MENU_BACK,
-	DIALOG_BOX,
-	INPUT_BOX,
-	INPUT_HEADING,
-	INPUT_TEXT,
-	INPUT_FIELD,
-	FUNCTION_TEXT,
-	FUNCTION_HIGHLIGHT,
-	ATTR_MAX
-} attributes_t;
-extern attributes_t attributes[];
-
-typedef enum {
-	F_HELP = 1,
-	F_SYMBOL = 2,
-	F_INSTS = 3,
-	F_CONF = 4,
-	F_BACK = 5,
-	F_SAVE = 6,
-	F_LOAD = 7,
-	F_SEARCH = 8,
-	F_EXIT = 9,
-} function_key;
-
-void set_colors(void);
-
-/* this changes the windows attributes !!! */
-void print_in_middle(WINDOW *win,
-		int starty,
-		int startx,
-		int width,
-		const char *string,
-		chtype color);
-int get_line_length(const char *line);
-int get_line_no(const char *text);
-const char *get_line(const char *text, int line_no);
-void fill_window(WINDOW *win, const char *text);
-int btn_dialog(WINDOW *main_window, const char *msg, int btn_num, ...);
-int dialog_inputbox(WINDOW *main_window,
-		const char *title, const char *prompt,
-		const char *init, char **resultp, int *result_len);
-void refresh_all_windows(WINDOW *main_window);
-void show_scroll_win(WINDOW *main_window,
-		const char *title,
-		const char *text);
diff --git a/util/kconfig/parser.y b/util/kconfig/parser.y
deleted file mode 100644
index 60936c7686..0000000000
--- a/util/kconfig/parser.y
+++ /dev/null
@@ -1,731 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org>
- */
-%{
-
-#include <ctype.h>
-#include <stdarg.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <stdbool.h>
-
-#include "lkc.h"
-
-#define printd(mask, fmt...) if (cdebug & (mask)) printf(fmt)
-
-#define PRINTD		0x0001
-#define DEBUG_PARSE	0x0002
-
-int cdebug = PRINTD;
-
-static void yyerror(const char *err);
-static void zconfprint(const char *err, ...);
-static void zconf_error(const char *err, ...);
-static bool zconf_endtoken(const char *tokenname,
-			   const char *expected_tokenname);
-
-struct symbol *symbol_hash[SYMBOL_HASHSIZE];
-
-static struct menu *current_menu, *current_entry;
-
-%}
-
-%union
-{
-	char *string;
-	struct symbol *symbol;
-	struct expr *expr;
-	struct menu *menu;
-	enum symbol_type type;
-	enum variable_flavor flavor;
-}
-
-%token <string> T_HELPTEXT
-%token <string> T_WORD
-%token <string> T_WORD_QUOTE
-%token T_ALLNOCONFIG_Y
-%token T_BOOL
-%token T_CHOICE
-%token T_CLOSE_PAREN
-%token T_COLON_EQUAL
-%token T_COMMENT
-%token T_CONFIG
-%token T_DEFAULT
-%token T_DEFCONFIG_LIST
-%token T_DEF_BOOL
-%token T_DEF_TRISTATE
-%token T_DEPENDS
-%token T_ENDCHOICE
-%token T_ENDIF
-%token T_ENDMENU
-%token T_HELP
-%token T_HEX
-%token T_IF
-%token T_IMPLY
-%token T_INT
-%token T_MAINMENU
-%token T_MENU
-%token T_MENUCONFIG
-%token T_MODULES
-%token T_ON
-%token T_OPEN_PAREN
-%token T_OPTION
-%token T_OPTIONAL
-%token T_PLUS_EQUAL
-%token T_PROMPT
-%token T_RANGE
-%token T_SELECT
-%token T_SOURCE
-%token T_STRING
-%token T_TRISTATE
-%token T_VISIBLE
-%token T_EOL
-%token <string> T_ASSIGN_VAL
-
-%left T_OR
-%left T_AND
-%left T_EQUAL T_UNEQUAL
-%left T_LESS T_LESS_EQUAL T_GREATER T_GREATER_EQUAL
-%nonassoc T_NOT
-
-%type <string> prompt
-%type <symbol> nonconst_symbol
-%type <symbol> symbol
-%type <type> type logic_type default
-%type <expr> expr
-%type <expr> if_expr
-%type <string> end
-%type <menu> if_entry menu_entry choice_entry
-%type <string> word_opt assign_val
-%type <flavor> assign_op
-
-%destructor {
-	fprintf(stderr, "%s:%d: missing end statement for this entry\n",
-		$$->file->name, $$->lineno);
-	if (current_menu == $$)
-		menu_end_menu();
-} if_entry menu_entry choice_entry
-
-%%
-input: mainmenu_stmt stmt_list | stmt_list;
-
-/* mainmenu entry */
-
-mainmenu_stmt: T_MAINMENU prompt T_EOL
-{
-	menu_add_prompt(P_MENU, $2, NULL);
-};
-
-stmt_list:
-	  /* empty */
-	| stmt_list common_stmt
-	| stmt_list choice_stmt
-	| stmt_list menu_stmt
-	| stmt_list T_WORD error T_EOL	{ zconf_error("unknown statement \"%s\"", $2); }
-	| stmt_list error T_EOL		{ zconf_error("invalid statement"); }
-;
-
-common_stmt:
-	  if_stmt
-	| comment_stmt
-	| config_stmt
-	| menuconfig_stmt
-	| source_stmt
-	| assignment_stmt
-;
-
-/* config/menuconfig entry */
-
-config_entry_start: T_CONFIG nonconst_symbol T_EOL
-{
-	$2->flags |= SYMBOL_OPTIONAL;
-	menu_add_entry($2);
-	printd(DEBUG_PARSE, "%s:%d:config %s\n", zconf_curname(), zconf_lineno(), $2->name);
-};
-
-config_stmt: config_entry_start config_option_list
-{
-	printd(DEBUG_PARSE, "%s:%d:endconfig\n", zconf_curname(), zconf_lineno());
-};
-
-menuconfig_entry_start: T_MENUCONFIG nonconst_symbol T_EOL
-{
-	$2->flags |= SYMBOL_OPTIONAL;
-	menu_add_entry($2);
-	printd(DEBUG_PARSE, "%s:%d:menuconfig %s\n", zconf_curname(), zconf_lineno(), $2->name);
-};
-
-menuconfig_stmt: menuconfig_entry_start config_option_list
-{
-	if (current_entry->prompt)
-		current_entry->prompt->type = P_MENU;
-	else
-		zconfprint("warning: menuconfig statement without prompt");
-	printd(DEBUG_PARSE, "%s:%d:endconfig\n", zconf_curname(), zconf_lineno());
-};
-
-config_option_list:
-	  /* empty */
-	| config_option_list config_option
-	| config_option_list depends
-	| config_option_list help
-;
-
-config_option: type prompt_stmt_opt T_EOL
-{
-	menu_set_type($1);
-	printd(DEBUG_PARSE, "%s:%d:type(%u)\n",
-		zconf_curname(), zconf_lineno(),
-		$1);
-};
-
-config_option: T_PROMPT prompt if_expr T_EOL
-{
-	menu_add_prompt(P_PROMPT, $2, $3);
-	printd(DEBUG_PARSE, "%s:%d:prompt\n", zconf_curname(), zconf_lineno());
-};
-
-config_option: default expr if_expr T_EOL
-{
-	menu_add_expr(P_DEFAULT, $2, $3);
-	if ($1 != S_UNKNOWN)
-		menu_set_type($1);
-	printd(DEBUG_PARSE, "%s:%d:default(%u)\n",
-		zconf_curname(), zconf_lineno(),
-		$1);
-};
-
-config_option: T_SELECT nonconst_symbol if_expr T_EOL
-{
-	menu_add_symbol(P_SELECT, $2, $3);
-	printd(DEBUG_PARSE, "%s:%d:select\n", zconf_curname(), zconf_lineno());
-};
-
-config_option: T_IMPLY nonconst_symbol if_expr T_EOL
-{
-	menu_add_symbol(P_IMPLY, $2, $3);
-	printd(DEBUG_PARSE, "%s:%d:imply\n", zconf_curname(), zconf_lineno());
-};
-
-config_option: T_RANGE symbol symbol if_expr T_EOL
-{
-	menu_add_expr(P_RANGE, expr_alloc_comp(E_RANGE,$2, $3), $4);
-	printd(DEBUG_PARSE, "%s:%d:range\n", zconf_curname(), zconf_lineno());
-};
-
-config_option: T_OPTION T_MODULES T_EOL
-{
-	menu_add_option_modules();
-};
-
-config_option: T_OPTION T_DEFCONFIG_LIST T_EOL
-{
-	menu_add_option_defconfig_list();
-};
-
-config_option: T_OPTION T_ALLNOCONFIG_Y T_EOL
-{
-	menu_add_option_allnoconfig_y();
-};
-
-/* choice entry */
-
-choice: T_CHOICE word_opt T_EOL
-{
-	struct symbol *sym = sym_lookup($2, SYMBOL_CHOICE);
-	sym->flags |= SYMBOL_NO_WRITE;
-	menu_add_entry(sym);
-	menu_add_expr(P_CHOICE, NULL, NULL);
-	free($2);
-	printd(DEBUG_PARSE, "%s:%d:choice\n", zconf_curname(), zconf_lineno());
-};
-
-choice_entry: choice choice_option_list
-{
-	$$ = menu_add_menu();
-};
-
-choice_end: end
-{
-	if (zconf_endtoken($1, "choice")) {
-		menu_end_menu();
-		printd(DEBUG_PARSE, "%s:%d:endchoice\n", zconf_curname(), zconf_lineno());
-	}
-};
-
-choice_stmt: choice_entry choice_block choice_end
-;
-
-choice_option_list:
-	  /* empty */
-	| choice_option_list choice_option
-	| choice_option_list depends
-	| choice_option_list help
-;
-
-choice_option: T_PROMPT prompt if_expr T_EOL
-{
-	menu_add_prompt(P_PROMPT, $2, $3);
-	printd(DEBUG_PARSE, "%s:%d:prompt\n", zconf_curname(), zconf_lineno());
-};
-
-choice_option: logic_type prompt_stmt_opt T_EOL
-{
-	menu_set_type($1);
-	printd(DEBUG_PARSE, "%s:%d:type(%u)\n",
-	       zconf_curname(), zconf_lineno(), $1);
-};
-
-choice_option: T_OPTIONAL T_EOL
-{
-	current_entry->sym->flags |= SYMBOL_OPTIONAL;
-	printd(DEBUG_PARSE, "%s:%d:optional\n", zconf_curname(), zconf_lineno());
-};
-
-choice_option: T_DEFAULT nonconst_symbol if_expr T_EOL
-{
-	menu_add_symbol(P_DEFAULT, $2, $3);
-	printd(DEBUG_PARSE, "%s:%d:default\n",
-	       zconf_curname(), zconf_lineno());
-};
-
-type:
-	  logic_type
-	| T_INT			{ $$ = S_INT; }
-	| T_HEX			{ $$ = S_HEX; }
-	| T_STRING		{ $$ = S_STRING; }
-
-logic_type:
-	  T_BOOL		{ $$ = S_BOOLEAN; }
-	| T_TRISTATE		{ $$ = S_TRISTATE; }
-
-default:
-	  T_DEFAULT		{ $$ = S_UNKNOWN; }
-	| T_DEF_BOOL		{ $$ = S_BOOLEAN; }
-	| T_DEF_TRISTATE	{ $$ = S_TRISTATE; }
-
-choice_block:
-	  /* empty */
-	| choice_block common_stmt
-;
-
-/* if entry */
-
-if_entry: T_IF expr T_EOL
-{
-	printd(DEBUG_PARSE, "%s:%d:if\n", zconf_curname(), zconf_lineno());
-	menu_add_entry(NULL);
-	menu_add_dep($2);
-	$$ = menu_add_menu();
-};
-
-if_end: end
-{
-	if (zconf_endtoken($1, "if")) {
-		menu_end_menu();
-		printd(DEBUG_PARSE, "%s:%d:endif\n", zconf_curname(), zconf_lineno());
-	}
-};
-
-if_stmt: if_entry stmt_list if_end
-;
-
-/* menu entry */
-
-menu: T_MENU prompt T_EOL
-{
-	menu_add_entry(NULL);
-	menu_add_prompt(P_MENU, $2, NULL);
-	printd(DEBUG_PARSE, "%s:%d:menu\n", zconf_curname(), zconf_lineno());
-};
-
-menu_entry: menu menu_option_list
-{
-	$$ = menu_add_menu();
-};
-
-menu_end: end
-{
-	if (zconf_endtoken($1, "menu")) {
-		menu_end_menu();
-		printd(DEBUG_PARSE, "%s:%d:endmenu\n", zconf_curname(), zconf_lineno());
-	}
-};
-
-menu_stmt: menu_entry stmt_list menu_end
-;
-
-menu_option_list:
-	  /* empty */
-	| menu_option_list visible
-	| menu_option_list depends
-;
-
-source_stmt: T_SOURCE prompt T_EOL
-{
-	printd(DEBUG_PARSE, "%s:%d:source %s\n", zconf_curname(), zconf_lineno(), $2);
-	zconf_nextfile($2);
-	free($2);
-};
-
-/* comment entry */
-
-comment: T_COMMENT prompt T_EOL
-{
-	menu_add_entry(NULL);
-	menu_add_prompt(P_COMMENT, $2, NULL);
-	printd(DEBUG_PARSE, "%s:%d:comment\n", zconf_curname(), zconf_lineno());
-};
-
-comment_stmt: comment comment_option_list
-;
-
-comment_option_list:
-	  /* empty */
-	| comment_option_list depends
-;
-
-/* help option */
-
-help_start: T_HELP T_EOL
-{
-	printd(DEBUG_PARSE, "%s:%d:help\n", zconf_curname(), zconf_lineno());
-	zconf_starthelp();
-};
-
-help: help_start T_HELPTEXT
-{
-	if (current_entry->help) {
-		free(current_entry->help);
-		zconfprint("warning: '%s' defined with more than one help text -- only the last one will be used",
-			   current_entry->sym->name ?: "<choice>");
-	}
-
-	/* Is the help text empty or all whitespace? */
-	if ($2[strspn($2, " \f\n\r\t\v")] == '\0')
-		zconfprint("warning: '%s' defined with blank help text",
-			   current_entry->sym->name ?: "<choice>");
-
-	current_entry->help = $2;
-};
-
-/* depends option */
-
-depends: T_DEPENDS T_ON expr T_EOL
-{
-	menu_add_dep($3);
-	printd(DEBUG_PARSE, "%s:%d:depends on\n", zconf_curname(), zconf_lineno());
-};
-
-/* visibility option */
-visible: T_VISIBLE if_expr T_EOL
-{
-	menu_add_visibility($2);
-};
-
-/* prompt statement */
-
-prompt_stmt_opt:
-	  /* empty */
-	| prompt if_expr
-{
-	menu_add_prompt(P_PROMPT, $1, $2);
-};
-
-prompt:	  T_WORD
-	| T_WORD_QUOTE
-;
-
-end:	  T_ENDMENU T_EOL	{ $$ = "menu"; }
-	| T_ENDCHOICE T_EOL	{ $$ = "choice"; }
-	| T_ENDIF T_EOL		{ $$ = "if"; }
-;
-
-if_expr:  /* empty */			{ $$ = NULL; }
-	| T_IF expr			{ $$ = $2; }
-;
-
-expr:	  symbol				{ $$ = expr_alloc_symbol($1); }
-	| symbol T_LESS symbol			{ $$ = expr_alloc_comp(E_LTH, $1, $3); }
-	| symbol T_LESS_EQUAL symbol		{ $$ = expr_alloc_comp(E_LEQ, $1, $3); }
-	| symbol T_GREATER symbol		{ $$ = expr_alloc_comp(E_GTH, $1, $3); }
-	| symbol T_GREATER_EQUAL symbol		{ $$ = expr_alloc_comp(E_GEQ, $1, $3); }
-	| symbol T_EQUAL symbol			{ $$ = expr_alloc_comp(E_EQUAL, $1, $3); }
-	| symbol T_UNEQUAL symbol		{ $$ = expr_alloc_comp(E_UNEQUAL, $1, $3); }
-	| T_OPEN_PAREN expr T_CLOSE_PAREN	{ $$ = $2; }
-	| T_NOT expr				{ $$ = expr_alloc_one(E_NOT, $2); }
-	| expr T_OR expr			{ $$ = expr_alloc_two(E_OR, $1, $3); }
-	| expr T_AND expr			{ $$ = expr_alloc_two(E_AND, $1, $3); }
-;
-
-/* For symbol definitions, selects, etc., where quotes are not accepted */
-nonconst_symbol: T_WORD { $$ = sym_lookup($1, 0); free($1); };
-
-symbol:	  nonconst_symbol
-	| T_WORD_QUOTE	{ $$ = sym_lookup($1, SYMBOL_CONST); free($1); }
-;
-
-word_opt: /* empty */			{ $$ = NULL; }
-	| T_WORD
-
-/* assignment statement */
-
-assignment_stmt:  T_WORD assign_op assign_val T_EOL	{ variable_add($1, $3, $2); free($1); free($3); }
-
-assign_op:
-	  T_EQUAL	{ $$ = VAR_RECURSIVE; }
-	| T_COLON_EQUAL	{ $$ = VAR_SIMPLE; }
-	| T_PLUS_EQUAL	{ $$ = VAR_APPEND; }
-;
-
-assign_val:
-	/* empty */		{ $$ = xstrdup(""); };
-	| T_ASSIGN_VAL
-;
-
-%%
-
-void conf_parse(const char *name)
-{
-	struct symbol *sym;
-	int i;
-
-	zconf_initscan(name);
-
-	_menu_init();
-
-	if (getenv("ZCONF_DEBUG"))
-		yydebug = 1;
-	yyparse();
-
-	/* Variables are expanded in the parse phase. We can free them here. */
-	variable_all_del();
-
-	if (yynerrs)
-		exit(1);
-	if (!modules_sym)
-		modules_sym = sym_find( "n" );
-
-	if (!menu_has_prompt(&rootmenu)) {
-		current_entry = &rootmenu;
-		menu_add_prompt(P_MENU, "Main menu", NULL);
-	}
-
-	menu_finalize(&rootmenu);
-	for_all_symbols(i, sym) {
-		if (sym_check_deps(sym))
-			yynerrs++;
-	}
-	if (yynerrs)
-		exit(1);
-	sym_set_change_count(1);
-}
-
-static bool zconf_endtoken(const char *tokenname,
-			   const char *expected_tokenname)
-{
-	if (strcmp(tokenname, expected_tokenname)) {
-		zconf_error("unexpected '%s' within %s block",
-			    tokenname, expected_tokenname);
-		yynerrs++;
-		return false;
-	}
-	if (current_menu->file != current_file) {
-		zconf_error("'%s' in different file than '%s'",
-			    tokenname, expected_tokenname);
-		fprintf(stderr, "%s:%d: location of the '%s'\n",
-			current_menu->file->name, current_menu->lineno,
-			expected_tokenname);
-		yynerrs++;
-		return false;
-	}
-	return true;
-}
-
-static void zconfprint(const char *err, ...)
-{
-	va_list ap;
-
-	fprintf(stderr, "%s:%d: ", zconf_curname(), zconf_lineno());
-	va_start(ap, err);
-	vfprintf(stderr, err, ap);
-	va_end(ap);
-	fprintf(stderr, "\n");
-}
-
-static void zconf_error(const char *err, ...)
-{
-	va_list ap;
-
-	yynerrs++;
-	fprintf(stderr, "%s:%d: ", zconf_curname(), zconf_lineno());
-	va_start(ap, err);
-	vfprintf(stderr, err, ap);
-	va_end(ap);
-	fprintf(stderr, "\n");
-}
-
-static void yyerror(const char *err)
-{
-	fprintf(stderr, "%s:%d: %s\n", zconf_curname(), zconf_lineno() + 1, err);
-}
-
-static void print_quoted_string(FILE *out, const char *str)
-{
-	const char *p;
-	int len;
-
-	putc('"', out);
-	while ((p = strchr(str, '"'))) {
-		len = p - str;
-		if (len)
-			fprintf(out, "%.*s", len, str);
-		fputs("\\\"", out);
-		str = p + 1;
-	}
-	fputs(str, out);
-	putc('"', out);
-}
-
-static void print_symbol(FILE *out, struct menu *menu)
-{
-	struct symbol *sym = menu->sym;
-	struct property *prop;
-
-	if (sym_is_choice(sym))
-		fprintf(out, "\nchoice\n");
-	else
-		fprintf(out, "\nconfig %s\n", sym->name);
-	switch (sym->type) {
-	case S_BOOLEAN:
-		fputs("  bool\n", out);
-		break;
-	case S_TRISTATE:
-		fputs("  tristate\n", out);
-		break;
-	case S_STRING:
-		fputs("  string\n", out);
-		break;
-	case S_INT:
-		fputs("  integer\n", out);
-		break;
-	case S_HEX:
-		fputs("  hex\n", out);
-		break;
-	default:
-		fputs("  ???\n", out);
-		break;
-	}
-	for (prop = sym->prop; prop; prop = prop->next) {
-		if (prop->menu != menu)
-			continue;
-		switch (prop->type) {
-		case P_PROMPT:
-			fputs("  prompt ", out);
-			print_quoted_string(out, prop->text);
-			if (!expr_is_yes(prop->visible.expr)) {
-				fputs(" if ", out);
-				expr_fprint(prop->visible.expr, out);
-			}
-			fputc('\n', out);
-			break;
-		case P_DEFAULT:
-			fputs( "  default ", out);
-			expr_fprint(prop->expr, out);
-			if (!expr_is_yes(prop->visible.expr)) {
-				fputs(" if ", out);
-				expr_fprint(prop->visible.expr, out);
-			}
-			fputc('\n', out);
-			break;
-		case P_CHOICE:
-			fputs("  #choice value\n", out);
-			break;
-		case P_SELECT:
-			fputs( "  select ", out);
-			expr_fprint(prop->expr, out);
-			fputc('\n', out);
-			break;
-		case P_IMPLY:
-			fputs( "  imply ", out);
-			expr_fprint(prop->expr, out);
-			fputc('\n', out);
-			break;
-		case P_RANGE:
-			fputs( "  range ", out);
-			expr_fprint(prop->expr, out);
-			fputc('\n', out);
-			break;
-		case P_MENU:
-			fputs( "  menu ", out);
-			print_quoted_string(out, prop->text);
-			fputc('\n', out);
-			break;
-		case P_SYMBOL:
-			fputs( "  symbol ", out);
-			fprintf(out, "%s\n", prop->sym->name);
-			break;
-		default:
-			fprintf(out, "  unknown prop %d!\n", prop->type);
-			break;
-		}
-	}
-	if (menu->help) {
-		int len = strlen(menu->help);
-		while (menu->help[--len] == '\n')
-			menu->help[len] = 0;
-		fprintf(out, "  help\n%s\n", menu->help);
-	}
-}
-
-void zconfdump(FILE *out)
-{
-	struct property *prop;
-	struct symbol *sym;
-	struct menu *menu;
-
-	menu = rootmenu.list;
-	while (menu) {
-		if ((sym = menu->sym))
-			print_symbol(out, menu);
-		else if ((prop = menu->prompt)) {
-			switch (prop->type) {
-			case P_COMMENT:
-				fputs("\ncomment ", out);
-				print_quoted_string(out, prop->text);
-				fputs("\n", out);
-				break;
-			case P_MENU:
-				fputs("\nmenu ", out);
-				print_quoted_string(out, prop->text);
-				fputs("\n", out);
-				break;
-			default:
-				;
-			}
-			if (!expr_is_yes(prop->visible.expr)) {
-				fputs("  depends ", out);
-				expr_fprint(prop->visible.expr, out);
-				fputc('\n', out);
-			}
-		}
-
-		if (menu->list)
-			menu = menu->list;
-		else if (menu->next)
-			menu = menu->next;
-		else while ((menu = menu->parent)) {
-			if (menu->prompt && menu->prompt->type == P_MENU)
-				fputs("\nendmenu\n", out);
-			if (menu->next) {
-				menu = menu->next;
-				break;
-			}
-		}
-	}
-}
-
-#include "util.c"
-#include "menu.c"
diff --git a/util/kconfig/preprocess.c b/util/kconfig/preprocess.c
deleted file mode 100644
index 67b9731a0a..0000000000
--- a/util/kconfig/preprocess.c
+++ /dev/null
@@ -1,575 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-//
-// Copyright (C) 2018 Masahiro Yamada <yamada.masahiro@socionext.com>
-
-#include <ctype.h>
-#include <stdarg.h>
-#include <stdbool.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <stdnoreturn.h>
-
-#include "list.h"
-#include "lkc.h"
-
-#define ARRAY_SIZE(arr)		(sizeof(arr) / sizeof((arr)[0]))
-
-static char *expand_string_with_args(const char *in, int argc, char *argv[]);
-static char *expand_string(const char *in);
-
-static noreturn void pperror(const char *format, ...)
-{
-	va_list ap;
-
-	fprintf(stderr, "%s:%d: ", current_file->name, yylineno);
-	va_start(ap, format);
-	vfprintf(stderr, format, ap);
-	va_end(ap);
-	fprintf(stderr, "\n");
-
-	exit(1);
-}
-
-/*
- * Environment variables
- */
-static LIST_HEAD(env_list);
-
-struct env {
-	char *name;
-	char *value;
-	struct list_head node;
-};
-
-static void env_add(const char *name, const char *value)
-{
-	struct env *e;
-
-	e = xmalloc(sizeof(*e));
-	e->name = xstrdup(name);
-	e->value = xstrdup(value);
-
-	list_add_tail(&e->node, &env_list);
-}
-
-static void env_del(struct env *e)
-{
-	list_del(&e->node);
-	free(e->name);
-	free(e->value);
-	free(e);
-}
-
-/* The returned pointer must be freed when done */
-static char *env_expand(const char *name)
-{
-	struct env *e;
-	const char *value;
-
-	if (!*name)
-		return NULL;
-
-	list_for_each_entry(e, &env_list, node) {
-		if (!strcmp(name, e->name))
-			return xstrdup(e->value);
-	}
-
-	value = getenv(name);
-	if (!value)
-		return NULL;
-
-	/*
-	 * We need to remember all referenced environment variables.
-	 * They will be written out to include/config/auto.conf.cmd
-	 */
-	env_add(name, value);
-
-	return xstrdup(value);
-}
-
-void env_write_dep(FILE *f, const char *autoconfig_name)
-{
-	struct env *e, *tmp;
-
-	list_for_each_entry_safe(e, tmp, &env_list, node) {
-		fprintf(f, "ifneq \"$(%s)\" \"%s\"\n", e->name, e->value);
-		fprintf(f, "%s: FORCE\n", autoconfig_name);
-		fprintf(f, "endif\n");
-		env_del(e);
-	}
-}
-
-/*
- * Built-in functions
- */
-struct function {
-	const char *name;
-	unsigned int min_args;
-	unsigned int max_args;
-	char *(*func)(int argc, char *argv[]);
-};
-
-static char *do_error_if(int argc, char *argv[])
-{
-	if (!strcmp(argv[0], "y"))
-		pperror("%s", argv[1]);
-
-	return NULL;
-}
-
-static char *do_filename(int argc, char *argv[])
-{
-	return xstrdup(current_file->name);
-}
-
-static char *do_info(int argc, char *argv[])
-{
-	printf("%s\n", argv[0]);
-
-	return xstrdup("");
-}
-
-static char *do_lineno(int argc, char *argv[])
-{
-	char buf[16];
-
-	sprintf(buf, "%d", yylineno);
-
-	return xstrdup(buf);
-}
-
-static char *do_shell(int argc, char *argv[])
-{
-	FILE *p;
-	char buf[256];
-	char *cmd;
-	size_t nread;
-	int i;
-
-	cmd = argv[0];
-
-	p = popen(cmd, "r");
-	if (!p) {
-		perror(cmd);
-		exit(1);
-	}
-
-	nread = fread(buf, 1, sizeof(buf), p);
-	if (nread == sizeof(buf))
-		nread--;
-
-	/* remove trailing new lines */
-	while (nread > 0 && buf[nread - 1] == '\n')
-		nread--;
-
-	buf[nread] = 0;
-
-	/* replace a new line with a space */
-	for (i = 0; i < nread; i++) {
-		if (buf[i] == '\n')
-			buf[i] = ' ';
-	}
-
-	if (pclose(p) == -1) {
-		perror(cmd);
-		exit(1);
-	}
-
-	return xstrdup(buf);
-}
-
-static char *do_warning_if(int argc, char *argv[])
-{
-	if (!strcmp(argv[0], "y"))
-		fprintf(stderr, "%s:%d: %s\n",
-			current_file->name, yylineno, argv[1]);
-
-	return xstrdup("");
-}
-
-static const struct function function_table[] = {
-	/* Name		MIN	MAX	Function */
-	{ "error-if",	2,	2,	do_error_if },
-	{ "filename",	0,	0,	do_filename },
-	{ "info",	1,	1,	do_info },
-	{ "lineno",	0,	0,	do_lineno },
-	{ "shell",	1,	1,	do_shell },
-	{ "warning-if",	2,	2,	do_warning_if },
-};
-
-#define FUNCTION_MAX_ARGS		16
-
-static char *function_expand(const char *name, int argc, char *argv[])
-{
-	const struct function *f;
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(function_table); i++) {
-		f = &function_table[i];
-		if (strcmp(f->name, name))
-			continue;
-
-		if (argc < f->min_args)
-			pperror("too few function arguments passed to '%s'",
-				name);
-
-		if (argc > f->max_args)
-			pperror("too many function arguments passed to '%s'",
-				name);
-
-		return f->func(argc, argv);
-	}
-
-	return NULL;
-}
-
-/*
- * Variables (and user-defined functions)
- */
-static LIST_HEAD(variable_list);
-
-struct variable {
-	char *name;
-	char *value;
-	enum variable_flavor flavor;
-	int exp_count;
-	struct list_head node;
-};
-
-static struct variable *variable_lookup(const char *name)
-{
-	struct variable *v;
-
-	list_for_each_entry(v, &variable_list, node) {
-		if (!strcmp(name, v->name))
-			return v;
-	}
-
-	return NULL;
-}
-
-static char *variable_expand(const char *name, int argc, char *argv[])
-{
-	struct variable *v;
-	char *res;
-
-	v = variable_lookup(name);
-	if (!v)
-		return NULL;
-
-	if (argc == 0 && v->exp_count)
-		pperror("Recursive variable '%s' references itself (eventually)",
-			name);
-
-	if (v->exp_count > 1000)
-		pperror("Too deep recursive expansion");
-
-	v->exp_count++;
-
-	if (v->flavor == VAR_RECURSIVE)
-		res = expand_string_with_args(v->value, argc, argv);
-	else
-		res = xstrdup(v->value);
-
-	v->exp_count--;
-
-	return res;
-}
-
-void variable_add(const char *name, const char *value,
-		  enum variable_flavor flavor)
-{
-	struct variable *v;
-	char *new_value;
-	bool append = false;
-
-	v = variable_lookup(name);
-	if (v) {
-		/* For defined variables, += inherits the existing flavor */
-		if (flavor == VAR_APPEND) {
-			flavor = v->flavor;
-			append = true;
-		} else {
-			free(v->value);
-		}
-	} else {
-		/* For undefined variables, += assumes the recursive flavor */
-		if (flavor == VAR_APPEND)
-			flavor = VAR_RECURSIVE;
-
-		v = xmalloc(sizeof(*v));
-		v->name = xstrdup(name);
-		v->exp_count = 0;
-		list_add_tail(&v->node, &variable_list);
-	}
-
-	v->flavor = flavor;
-
-	if (flavor == VAR_SIMPLE)
-		new_value = expand_string(value);
-	else
-		new_value = xstrdup(value);
-
-	if (append) {
-		v->value = xrealloc(v->value,
-				    strlen(v->value) + strlen(new_value) + 2);
-		strcat(v->value, " ");
-		strcat(v->value, new_value);
-		free(new_value);
-	} else {
-		v->value = new_value;
-	}
-}
-
-static void variable_del(struct variable *v)
-{
-	list_del(&v->node);
-	free(v->name);
-	free(v->value);
-	free(v);
-}
-
-void variable_all_del(void)
-{
-	struct variable *v, *tmp;
-
-	list_for_each_entry_safe(v, tmp, &variable_list, node)
-		variable_del(v);
-}
-
-/*
- * Evaluate a clause with arguments.  argc/argv are arguments from the upper
- * function call.
- *
- * Returned string must be freed when done
- */
-static char *eval_clause(const char *str, size_t len, int argc, char *argv[])
-{
-	char *tmp, *name, *res, *endptr, *prev, *p;
-	int new_argc = 0;
-	char *new_argv[FUNCTION_MAX_ARGS];
-	int nest = 0;
-	int i;
-	unsigned long n;
-
-	tmp = xstrndup(str, len);
-
-	/*
-	 * If variable name is '1', '2', etc.  It is generally an argument
-	 * from a user-function call (i.e. local-scope variable).  If not
-	 * available, then look-up global-scope variables.
-	 */
-	n = strtoul(tmp, &endptr, 10);
-	if (!*endptr && n > 0 && n <= argc) {
-		res = xstrdup(argv[n - 1]);
-		goto free_tmp;
-	}
-
-	prev = p = tmp;
-
-	/*
-	 * Split into tokens
-	 * The function name and arguments are separated by a comma.
-	 * For example, if the function call is like this:
-	 *   $(foo,$(x),$(y))
-	 *
-	 * The input string for this helper should be:
-	 *   foo,$(x),$(y)
-	 *
-	 * and split into:
-	 *   new_argv[0] = 'foo'
-	 *   new_argv[1] = '$(x)'
-	 *   new_argv[2] = '$(y)'
-	 */
-	while (*p) {
-		if (nest == 0 && *p == ',') {
-			*p = 0;
-			if (new_argc >= FUNCTION_MAX_ARGS)
-				pperror("too many function arguments");
-			new_argv[new_argc++] = prev;
-			prev = p + 1;
-		} else if (*p == '(') {
-			nest++;
-		} else if (*p == ')') {
-			nest--;
-		}
-
-		p++;
-	}
-	new_argv[new_argc++] = prev;
-
-	/*
-	 * Shift arguments
-	 * new_argv[0] represents a function name or a variable name.  Put it
-	 * into 'name', then shift the rest of the arguments.  This simplifies
-	 * 'const' handling.
-	 */
-	name = expand_string_with_args(new_argv[0], argc, argv);
-	new_argc--;
-	for (i = 0; i < new_argc; i++)
-		new_argv[i] = expand_string_with_args(new_argv[i + 1],
-						      argc, argv);
-
-	/* Search for variables */
-	res = variable_expand(name, new_argc, new_argv);
-	if (res)
-		goto free;
-
-	/* Look for built-in functions */
-	res = function_expand(name, new_argc, new_argv);
-	if (res)
-		goto free;
-
-	/* Last, try environment variable */
-	if (new_argc == 0) {
-		res = env_expand(name);
-		if (res)
-			goto free;
-	}
-
-	res = xstrdup("");
-free:
-	for (i = 0; i < new_argc; i++)
-		free(new_argv[i]);
-	free(name);
-free_tmp:
-	free(tmp);
-
-	return res;
-}
-
-/*
- * Expand a string that follows '$'
- *
- * For example, if the input string is
- *     ($(FOO)$($(BAR)))$(BAZ)
- * this helper evaluates
- *     $($(FOO)$($(BAR)))
- * and returns a new string containing the expansion (note that the string is
- * recursively expanded), also advancing 'str' to point to the next character
- * after the corresponding closing parenthesis, in this case, *str will be
- *     $(BAR)
- */
-static char *expand_dollar_with_args(const char **str, int argc, char *argv[])
-{
-	const char *p = *str;
-	const char *q;
-	int nest = 0;
-
-	/*
-	 * In Kconfig, variable/function references always start with "$(".
-	 * Neither single-letter variables as in $A nor curly braces as in ${CC}
-	 * are supported.  '$' not followed by '(' loses its special meaning.
-	 */
-	if (*p != '(') {
-		*str = p;
-		return xstrdup("$");
-	}
-
-	p++;
-	q = p;
-	while (*q) {
-		if (*q == '(') {
-			nest++;
-		} else if (*q == ')') {
-			if (nest-- == 0)
-				break;
-		}
-		q++;
-	}
-
-	if (!*q)
-		pperror("unterminated reference to '%s': missing ')'", p);
-
-	/* Advance 'str' to after the expanded initial portion of the string */
-	*str = q + 1;
-
-	return eval_clause(p, q - p, argc, argv);
-}
-
-char *expand_dollar(const char **str)
-{
-	return expand_dollar_with_args(str, 0, NULL);
-}
-
-static char *__expand_string(const char **str, bool (*is_end)(char c),
-			     int argc, char *argv[])
-{
-	const char *in, *p;
-	char *expansion, *out;
-	size_t in_len, out_len;
-
-	out = xmalloc(1);
-	*out = 0;
-	out_len = 1;
-
-	p = in = *str;
-
-	while (1) {
-		if (*p == '$') {
-			in_len = p - in;
-			p++;
-			expansion = expand_dollar_with_args(&p, argc, argv);
-			out_len += in_len + strlen(expansion);
-			out = xrealloc(out, out_len);
-			strncat(out, in, in_len);
-			strcat(out, expansion);
-			free(expansion);
-			in = p;
-			continue;
-		}
-
-		if (is_end(*p))
-			break;
-
-		p++;
-	}
-
-	in_len = p - in;
-	out_len += in_len;
-	out = xrealloc(out, out_len);
-	strncat(out, in, in_len);
-
-	/* Advance 'str' to the end character */
-	*str = p;
-
-	return out;
-}
-
-static bool is_end_of_str(char c)
-{
-	return !c;
-}
-
-/*
- * Expand variables and functions in the given string.  Undefined variables
- * expand to an empty string.
- * The returned string must be freed when done.
- */
-static char *expand_string_with_args(const char *in, int argc, char *argv[])
-{
-	return __expand_string(&in, is_end_of_str, argc, argv);
-}
-
-static char *expand_string(const char *in)
-{
-	return expand_string_with_args(in, 0, NULL);
-}
-
-static bool is_end_of_token(char c)
-{
-	return !(isalnum(c) || c == '_' || c == '-');
-}
-
-/*
- * Expand variables in a token.  The parsing stops when a token separater
- * (in most cases, it is a whitespace) is encountered.  'str' is updated to
- * point to the next character.
- *
- * The returned string must be freed when done.
- */
-char *expand_one_token(const char **str)
-{
-	return __expand_string(str, is_end_of_token, 0, NULL);
-}
diff --git a/util/kconfig/qconf-cfg.sh b/util/kconfig/qconf-cfg.sh
deleted file mode 100755
index 02ccc0ae10..0000000000
--- a/util/kconfig/qconf-cfg.sh
+++ /dev/null
@@ -1,32 +0,0 @@
-#!/bin/sh
-# SPDX-License-Identifier: GPL-2.0
-
-PKG="Qt5Core Qt5Gui Qt5Widgets"
-PKG2="QtCore QtGui"
-
-if [ -z "$(command -v pkg-config)" ]; then
-	echo >&2 "*"
-	echo >&2 "* 'make xconfig' requires 'pkg-config'. Please install it."
-	echo >&2 "*"
-	exit 1
-fi
-
-if pkg-config --exists $PKG; then
-	echo cflags=\"-std=c++11 -fPIC $(pkg-config --cflags Qt5Core Qt5Gui Qt5Widgets)\"
-	echo libs=\"$(pkg-config --libs $PKG)\"
-	echo moc=\"$(pkg-config --variable=host_bins Qt5Core)/moc\"
-	exit 0
-fi
-
-if pkg-config --exists $PKG2; then
-	echo cflags=\"$(pkg-config --cflags $PKG2)\"
-	echo libs=\"$(pkg-config --libs $PKG2)\"
-	echo moc=\"$(pkg-config --variable=moc_location QtCore)\"
-	exit 0
-fi
-
-echo >&2 "*"
-echo >&2 "* Could not find Qt via pkg-config."
-echo >&2 "* Please install either Qt 4.8 or 5.x. and make sure it's in PKG_CONFIG_PATH"
-echo >&2 "*"
-exit 1
diff --git a/util/kconfig/qconf.cc b/util/kconfig/qconf.cc
deleted file mode 100644
index 82773cc35d..0000000000
--- a/util/kconfig/qconf.cc
+++ /dev/null
@@ -1,1896 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org>
- * Copyright (C) 2015 Boris Barbulovski <bbarbulovski@gmail.com>
- */
-
-#include <qglobal.h>
-
-#include <QMainWindow>
-#include <QList>
-#include <qtextbrowser.h>
-#include <QAction>
-#include <QFileDialog>
-#include <QMenu>
-
-#include <qapplication.h>
-#include <qdesktopwidget.h>
-#include <qtoolbar.h>
-#include <qlayout.h>
-#include <qsplitter.h>
-#include <qlineedit.h>
-#include <qlabel.h>
-#include <qpushbutton.h>
-#include <qmenubar.h>
-#include <qmessagebox.h>
-#include <qregexp.h>
-#include <qevent.h>
-
-#include <stdlib.h>
-
-#include "lkc.h"
-#include "qconf.h"
-
-#include "qconf.moc"
-#include "images.h"
-
-
-static QApplication *configApp;
-static ConfigSettings *configSettings;
-
-QAction *ConfigMainWindow::saveAction;
-
-static inline QString qgettext(const char* str)
-{
-	return QString::fromLocal8Bit(str);
-}
-
-ConfigSettings::ConfigSettings()
-	: QSettings("kernel.org", "qconf")
-{
-}
-
-/**
- * Reads a list of integer values from the application settings.
- */
-QList<int> ConfigSettings::readSizes(const QString& key, bool *ok)
-{
-	QList<int> result;
-
-	if (contains(key))
-	{
-		QStringList entryList = value(key).toStringList();
-		QStringList::Iterator it;
-
-		for (it = entryList.begin(); it != entryList.end(); ++it)
-			result.push_back((*it).toInt());
-
-		*ok = true;
-	}
-	else
-		*ok = false;
-
-	return result;
-}
-
-/**
- * Writes a list of integer values to the application settings.
- */
-bool ConfigSettings::writeSizes(const QString& key, const QList<int>& value)
-{
-	QStringList stringList;
-	QList<int>::ConstIterator it;
-
-	for (it = value.begin(); it != value.end(); ++it)
-		stringList.push_back(QString::number(*it));
-	setValue(key, stringList);
-
-	return true;
-}
-
-
-/*
- * set the new data
- * TODO check the value
- */
-void ConfigItem::okRename(int col)
-{
-}
-
-/*
- * update the displayed of a menu entry
- */
-void ConfigItem::updateMenu(void)
-{
-	ConfigList* list;
-	struct symbol* sym;
-	struct property *prop;
-	QString prompt;
-	int type;
-	tristate expr;
-
-	list = listView();
-	if (goParent) {
-		setPixmap(promptColIdx, list->menuBackPix);
-		prompt = "..";
-		goto set_prompt;
-	}
-
-	sym = menu->sym;
-	prop = menu->prompt;
-	prompt = qgettext(menu_get_prompt(menu));
-
-	if (prop) switch (prop->type) {
-	case P_MENU:
-		if (list->mode == singleMode || list->mode == symbolMode) {
-			/* a menuconfig entry is displayed differently
-			 * depending whether it's at the view root or a child.
-			 */
-			if (sym && list->rootEntry == menu)
-				break;
-			setPixmap(promptColIdx, list->menuPix);
-		} else {
-			if (sym)
-				break;
-			setPixmap(promptColIdx, QIcon());
-		}
-		goto set_prompt;
-	case P_COMMENT:
-		setPixmap(promptColIdx, QIcon());
-		goto set_prompt;
-	default:
-		;
-	}
-	if (!sym)
-		goto set_prompt;
-
-	setText(nameColIdx, QString::fromLocal8Bit(sym->name));
-
-	type = sym_get_type(sym);
-	switch (type) {
-	case S_BOOLEAN:
-	case S_TRISTATE:
-		char ch;
-
-		if (!sym_is_changeable(sym) && list->optMode == normalOpt) {
-			setPixmap(promptColIdx, QIcon());
-			setText(noColIdx, QString::null);
-			setText(modColIdx, QString::null);
-			setText(yesColIdx, QString::null);
-			break;
-		}
-		expr = sym_get_tristate_value(sym);
-		switch (expr) {
-		case yes:
-			if (sym_is_choice_value(sym) && type == S_BOOLEAN)
-				setPixmap(promptColIdx, list->choiceYesPix);
-			else
-				setPixmap(promptColIdx, list->symbolYesPix);
-			setText(yesColIdx, "Y");
-			ch = 'Y';
-			break;
-		case mod:
-			setPixmap(promptColIdx, list->symbolModPix);
-			setText(modColIdx, "M");
-			ch = 'M';
-			break;
-		default:
-			if (sym_is_choice_value(sym) && type == S_BOOLEAN)
-				setPixmap(promptColIdx, list->choiceNoPix);
-			else
-				setPixmap(promptColIdx, list->symbolNoPix);
-			setText(noColIdx, "N");
-			ch = 'N';
-			break;
-		}
-		if (expr != no)
-			setText(noColIdx, sym_tristate_within_range(sym, no) ? "_" : 0);
-		if (expr != mod)
-			setText(modColIdx, sym_tristate_within_range(sym, mod) ? "_" : 0);
-		if (expr != yes)
-			setText(yesColIdx, sym_tristate_within_range(sym, yes) ? "_" : 0);
-
-		setText(dataColIdx, QChar(ch));
-		break;
-	case S_INT:
-	case S_HEX:
-	case S_STRING:
-		const char* data;
-
-		data = sym_get_string_value(sym);
-
-		setText(dataColIdx, data);
-		if (type == S_STRING)
-			prompt = QString("%1: %2").arg(prompt).arg(data);
-		else
-			prompt = QString("(%2) %1").arg(prompt).arg(data);
-		break;
-	}
-	if (!sym_has_value(sym) && visible)
-		prompt += " (NEW)";
-set_prompt:
-	setText(promptColIdx, prompt);
-}
-
-void ConfigItem::testUpdateMenu(bool v)
-{
-	ConfigItem* i;
-
-	visible = v;
-	if (!menu)
-		return;
-
-	sym_calc_value(menu->sym);
-	if (menu->flags & MENU_CHANGED) {
-		/* the menu entry changed, so update all list items */
-		menu->flags &= ~MENU_CHANGED;
-		for (i = (ConfigItem*)menu->data; i; i = i->nextItem)
-			i->updateMenu();
-	} else if (listView()->updateAll)
-		updateMenu();
-}
-
-
-/*
- * construct a menu entry
- */
-void ConfigItem::init(void)
-{
-	if (menu) {
-		ConfigList* list = listView();
-		nextItem = (ConfigItem*)menu->data;
-		menu->data = this;
-
-		if (list->mode != fullMode)
-			setExpanded(true);
-		sym_calc_value(menu->sym);
-	}
-	updateMenu();
-}
-
-/*
- * destruct a menu entry
- */
-ConfigItem::~ConfigItem(void)
-{
-	if (menu) {
-		ConfigItem** ip = (ConfigItem**)&menu->data;
-		for (; *ip; ip = &(*ip)->nextItem) {
-			if (*ip == this) {
-				*ip = nextItem;
-				break;
-			}
-		}
-	}
-}
-
-ConfigLineEdit::ConfigLineEdit(ConfigView* parent)
-	: Parent(parent)
-{
-	connect(this, SIGNAL(editingFinished()), SLOT(hide()));
-}
-
-void ConfigLineEdit::show(ConfigItem* i)
-{
-	item = i;
-	if (sym_get_string_value(item->menu->sym))
-		setText(QString::fromLocal8Bit(sym_get_string_value(item->menu->sym)));
-	else
-		setText(QString::null);
-	Parent::show();
-	setFocus();
-}
-
-void ConfigLineEdit::keyPressEvent(QKeyEvent* e)
-{
-	switch (e->key()) {
-	case Qt::Key_Escape:
-		break;
-	case Qt::Key_Return:
-	case Qt::Key_Enter:
-		sym_set_string_value(item->menu->sym, text().toLatin1());
-		parent()->updateList(item);
-		break;
-	default:
-		Parent::keyPressEvent(e);
-		return;
-	}
-	e->accept();
-	parent()->list->setFocus();
-	hide();
-}
-
-ConfigList::ConfigList(ConfigView* p, const char *name)
-	: Parent(p),
-	  updateAll(false),
-	  symbolYesPix(xpm_symbol_yes), symbolModPix(xpm_symbol_mod), symbolNoPix(xpm_symbol_no),
-	  choiceYesPix(xpm_choice_yes), choiceNoPix(xpm_choice_no),
-	  menuPix(xpm_menu), menuInvPix(xpm_menu_inv), menuBackPix(xpm_menuback), voidPix(xpm_void),
-	  showName(false), showRange(false), showData(false), mode(singleMode), optMode(normalOpt),
-	  rootEntry(0), headerPopup(0)
-{
-	int i;
-
-	setObjectName(name);
-	setSortingEnabled(false);
-	setRootIsDecorated(true);
-
-	setVerticalScrollMode(ScrollPerPixel);
-	setHorizontalScrollMode(ScrollPerPixel);
-
-	setHeaderLabels(QStringList() << "Option" << "Name" << "N" << "M" << "Y" << "Value");
-
-	connect(this, SIGNAL(itemSelectionChanged(void)),
-		SLOT(updateSelection(void)));
-
-	if (name) {
-		configSettings->beginGroup(name);
-		showName = configSettings->value("/showName", false).toBool();
-		showRange = configSettings->value("/showRange", false).toBool();
-		showData = configSettings->value("/showData", false).toBool();
-		optMode = (enum optionMode)configSettings->value("/optionMode", 0).toInt();
-		configSettings->endGroup();
-		connect(configApp, SIGNAL(aboutToQuit()), SLOT(saveSettings()));
-	}
-
-	addColumn(promptColIdx);
-
-	reinit();
-}
-
-bool ConfigList::menuSkip(struct menu *menu)
-{
-	if (optMode == normalOpt && menu_is_visible(menu))
-		return false;
-	if (optMode == promptOpt && menu_has_prompt(menu))
-		return false;
-	if (optMode == allOpt)
-		return false;
-	return true;
-}
-
-void ConfigList::reinit(void)
-{
-	removeColumn(dataColIdx);
-	removeColumn(yesColIdx);
-	removeColumn(modColIdx);
-	removeColumn(noColIdx);
-	removeColumn(nameColIdx);
-
-	if (showName)
-		addColumn(nameColIdx);
-	if (showRange) {
-		addColumn(noColIdx);
-		addColumn(modColIdx);
-		addColumn(yesColIdx);
-	}
-	if (showData)
-		addColumn(dataColIdx);
-
-	updateListAll();
-}
-
-void ConfigList::saveSettings(void)
-{
-	if (!objectName().isEmpty()) {
-		configSettings->beginGroup(objectName());
-		configSettings->setValue("/showName", showName);
-		configSettings->setValue("/showRange", showRange);
-		configSettings->setValue("/showData", showData);
-		configSettings->setValue("/optionMode", (int)optMode);
-		configSettings->endGroup();
-	}
-}
-
-ConfigItem* ConfigList::findConfigItem(struct menu *menu)
-{
-	ConfigItem* item = (ConfigItem*)menu->data;
-
-	for (; item; item = item->nextItem) {
-		if (this == item->listView())
-			break;
-	}
-
-	return item;
-}
-
-void ConfigList::updateSelection(void)
-{
-	struct menu *menu;
-	enum prop_type type;
-
-	if (selectedItems().count() == 0)
-		return;
-
-	ConfigItem* item = (ConfigItem*)selectedItems().first();
-	if (!item)
-		return;
-
-	menu = item->menu;
-	emit menuChanged(menu);
-	if (!menu)
-		return;
-	type = menu->prompt ? menu->prompt->type : P_UNKNOWN;
-	if (mode == menuMode && type == P_MENU)
-		emit menuSelected(menu);
-}
-
-void ConfigList::updateList(ConfigItem* item)
-{
-	ConfigItem* last = 0;
-
-	if (!rootEntry) {
-		if (mode != listMode)
-			goto update;
-		QTreeWidgetItemIterator it(this);
-		ConfigItem* item;
-
-		while (*it) {
-			item = (ConfigItem*)(*it);
-			if (!item->menu)
-				continue;
-			item->testUpdateMenu(menu_is_visible(item->menu));
-
-			++it;
-		}
-		return;
-	}
-
-	if (rootEntry != &rootmenu && (mode == singleMode ||
-	    (mode == symbolMode && rootEntry->parent != &rootmenu))) {
-		item = (ConfigItem *)topLevelItem(0);
-		if (!item)
-			item = new ConfigItem(this, 0, true);
-		last = item;
-	}
-	if ((mode == singleMode || (mode == symbolMode && !(rootEntry->flags & MENU_ROOT))) &&
-	    rootEntry->sym && rootEntry->prompt) {
-		item = last ? last->nextSibling() : firstChild();
-		if (!item)
-			item = new ConfigItem(this, last, rootEntry, true);
-		else
-			item->testUpdateMenu(true);
-
-		updateMenuList(item, rootEntry);
-		update();
-		resizeColumnToContents(0);
-		return;
-	}
-update:
-	updateMenuList(this, rootEntry);
-	update();
-	resizeColumnToContents(0);
-}
-
-void ConfigList::setValue(ConfigItem* item, tristate val)
-{
-	struct symbol* sym;
-	int type;
-	tristate oldval;
-
-	sym = item->menu ? item->menu->sym : 0;
-	if (!sym)
-		return;
-
-	type = sym_get_type(sym);
-	switch (type) {
-	case S_BOOLEAN:
-	case S_TRISTATE:
-		oldval = sym_get_tristate_value(sym);
-
-		if (!sym_set_tristate_value(sym, val))
-			return;
-		if (oldval == no && item->menu->list)
-			item->setExpanded(true);
-		parent()->updateList(item);
-		break;
-	}
-}
-
-void ConfigList::changeValue(ConfigItem* item)
-{
-	struct symbol* sym;
-	struct menu* menu;
-	int type, oldexpr, newexpr;
-
-	menu = item->menu;
-	if (!menu)
-		return;
-	sym = menu->sym;
-	if (!sym) {
-		if (item->menu->list)
-			item->setExpanded(!item->isExpanded());
-		return;
-	}
-
-	type = sym_get_type(sym);
-	switch (type) {
-	case S_BOOLEAN:
-	case S_TRISTATE:
-		oldexpr = sym_get_tristate_value(sym);
-		newexpr = sym_toggle_tristate_value(sym);
-		if (item->menu->list) {
-			if (oldexpr == newexpr)
-				item->setExpanded(!item->isExpanded());
-			else if (oldexpr == no)
-				item->setExpanded(true);
-		}
-		if (oldexpr != newexpr)
-			parent()->updateList(item);
-		break;
-	case S_INT:
-	case S_HEX:
-	case S_STRING:
-		parent()->lineEdit->show(item);
-		break;
-	}
-}
-
-void ConfigList::setRootMenu(struct menu *menu)
-{
-	enum prop_type type;
-
-	if (rootEntry == menu)
-		return;
-	type = menu && menu->prompt ? menu->prompt->type : P_UNKNOWN;
-	if (type != P_MENU)
-		return;
-	updateMenuList(this, 0);
-	rootEntry = menu;
-	updateListAll();
-	if (currentItem()) {
-		currentItem()->setSelected(hasFocus());
-		scrollToItem(currentItem());
-	}
-}
-
-void ConfigList::setParentMenu(void)
-{
-	ConfigItem* item;
-	struct menu *oldroot;
-
-	oldroot = rootEntry;
-	if (rootEntry == &rootmenu)
-		return;
-	setRootMenu(menu_get_parent_menu(rootEntry->parent));
-
-	QTreeWidgetItemIterator it(this);
-	while (*it) {
-		item = (ConfigItem *)(*it);
-		if (item->menu == oldroot) {
-			setCurrentItem(item);
-			scrollToItem(item);
-			break;
-		}
-
-		++it;
-	}
-}
-
-/*
- * update all the children of a menu entry
- *   removes/adds the entries from the parent widget as necessary
- *
- * parent: either the menu list widget or a menu entry widget
- * menu: entry to be updated
- */
-void ConfigList::updateMenuList(ConfigItem *parent, struct menu* menu)
-{
-	struct menu* child;
-	ConfigItem* item;
-	ConfigItem* last;
-	bool visible;
-	enum prop_type type;
-
-	if (!menu) {
-		while (parent->childCount() > 0)
-		{
-			delete parent->takeChild(0);
-		}
-
-		return;
-	}
-
-	last = parent->firstChild();
-	if (last && !last->goParent)
-		last = 0;
-	for (child = menu->list; child; child = child->next) {
-		item = last ? last->nextSibling() : parent->firstChild();
-		type = child->prompt ? child->prompt->type : P_UNKNOWN;
-
-		switch (mode) {
-		case menuMode:
-			if (!(child->flags & MENU_ROOT))
-				goto hide;
-			break;
-		case symbolMode:
-			if (child->flags & MENU_ROOT)
-				goto hide;
-			break;
-		default:
-			break;
-		}
-
-		visible = menu_is_visible(child);
-		if (!menuSkip(child)) {
-			if (!child->sym && !child->list && !child->prompt)
-				continue;
-			if (!item || item->menu != child)
-				item = new ConfigItem(parent, last, child, visible);
-			else
-				item->testUpdateMenu(visible);
-
-			if (mode == fullMode || mode == menuMode || type != P_MENU)
-				updateMenuList(item, child);
-			else
-				updateMenuList(item, 0);
-			last = item;
-			continue;
-		}
-	hide:
-		if (item && item->menu == child) {
-			last = parent->firstChild();
-			if (last == item)
-				last = 0;
-			else while (last->nextSibling() != item)
-				last = last->nextSibling();
-			delete item;
-		}
-	}
-}
-
-void ConfigList::updateMenuList(ConfigList *parent, struct menu* menu)
-{
-	struct menu* child;
-	ConfigItem* item;
-	ConfigItem* last;
-	bool visible;
-	enum prop_type type;
-
-	if (!menu) {
-		while (parent->topLevelItemCount() > 0)
-		{
-			delete parent->takeTopLevelItem(0);
-		}
-
-		return;
-	}
-
-	last = (ConfigItem*)parent->topLevelItem(0);
-	if (last && !last->goParent)
-		last = 0;
-	for (child = menu->list; child; child = child->next) {
-		item = last ? last->nextSibling() : (ConfigItem*)parent->topLevelItem(0);
-		type = child->prompt ? child->prompt->type : P_UNKNOWN;
-
-		switch (mode) {
-		case menuMode:
-			if (!(child->flags & MENU_ROOT))
-				goto hide;
-			break;
-		case symbolMode:
-			if (child->flags & MENU_ROOT)
-				goto hide;
-			break;
-		default:
-			break;
-		}
-
-		visible = menu_is_visible(child);
-		if (!menuSkip(child)) {
-			if (!child->sym && !child->list && !child->prompt)
-				continue;
-			if (!item || item->menu != child)
-				item = new ConfigItem(parent, last, child, visible);
-			else
-				item->testUpdateMenu(visible);
-
-			if (mode == fullMode || mode == menuMode || type != P_MENU)
-				updateMenuList(item, child);
-			else
-				updateMenuList(item, 0);
-			last = item;
-			continue;
-		}
-	hide:
-		if (item && item->menu == child) {
-			last = (ConfigItem*)parent->topLevelItem(0);
-			if (last == item)
-				last = 0;
-			else while (last->nextSibling() != item)
-				last = last->nextSibling();
-			delete item;
-		}
-	}
-}
-
-void ConfigList::keyPressEvent(QKeyEvent* ev)
-{
-	QTreeWidgetItem* i = currentItem();
-	ConfigItem* item;
-	struct menu *menu;
-	enum prop_type type;
-
-	if (ev->key() == Qt::Key_Escape && mode != fullMode && mode != listMode) {
-		emit parentSelected();
-		ev->accept();
-		return;
-	}
-
-	if (!i) {
-		Parent::keyPressEvent(ev);
-		return;
-	}
-	item = (ConfigItem*)i;
-
-	switch (ev->key()) {
-	case Qt::Key_Return:
-	case Qt::Key_Enter:
-		if (item->goParent) {
-			emit parentSelected();
-			break;
-		}
-		menu = item->menu;
-		if (!menu)
-			break;
-		type = menu->prompt ? menu->prompt->type : P_UNKNOWN;
-		if (type == P_MENU && rootEntry != menu &&
-		    mode != fullMode && mode != menuMode) {
-			emit menuSelected(menu);
-			break;
-		}
-	case Qt::Key_Space:
-		changeValue(item);
-		break;
-	case Qt::Key_N:
-		setValue(item, no);
-		break;
-	case Qt::Key_M:
-		setValue(item, mod);
-		break;
-	case Qt::Key_Y:
-		setValue(item, yes);
-		break;
-	default:
-		Parent::keyPressEvent(ev);
-		return;
-	}
-	ev->accept();
-}
-
-void ConfigList::mousePressEvent(QMouseEvent* e)
-{
-	//QPoint p(contentsToViewport(e->pos()));
-	//printf("contentsMousePressEvent: %d,%d\n", p.x(), p.y());
-	Parent::mousePressEvent(e);
-}
-
-void ConfigList::mouseReleaseEvent(QMouseEvent* e)
-{
-	QPoint p = e->pos();
-	ConfigItem* item = (ConfigItem*)itemAt(p);
-	struct menu *menu;
-	enum prop_type ptype;
-	QIcon icon;
-	int idx, x;
-
-	if (!item)
-		goto skip;
-
-	menu = item->menu;
-	x = header()->offset() + p.x();
-	idx = header()->logicalIndexAt(x);
-	switch (idx) {
-	case promptColIdx:
-		icon = item->pixmap(promptColIdx);
-		if (!icon.isNull()) {
-			int off = header()->sectionPosition(0) + visualRect(indexAt(p)).x() + 4; // 4 is Hardcoded image offset. There might be a way to do it properly.
-			if (x >= off && x < off + icon.availableSizes().first().width()) {
-				if (item->goParent) {
-					emit parentSelected();
-					break;
-				} else if (!menu)
-					break;
-				ptype = menu->prompt ? menu->prompt->type : P_UNKNOWN;
-				if (ptype == P_MENU && rootEntry != menu &&
-				    mode != fullMode && mode != menuMode)
-					emit menuSelected(menu);
-				else
-					changeValue(item);
-			}
-		}
-		break;
-	case noColIdx:
-		setValue(item, no);
-		break;
-	case modColIdx:
-		setValue(item, mod);
-		break;
-	case yesColIdx:
-		setValue(item, yes);
-		break;
-	case dataColIdx:
-		changeValue(item);
-		break;
-	}
-
-skip:
-	//printf("contentsMouseReleaseEvent: %d,%d\n", p.x(), p.y());
-	Parent::mouseReleaseEvent(e);
-}
-
-void ConfigList::mouseMoveEvent(QMouseEvent* e)
-{
-	//QPoint p(contentsToViewport(e->pos()));
-	//printf("contentsMouseMoveEvent: %d,%d\n", p.x(), p.y());
-	Parent::mouseMoveEvent(e);
-}
-
-void ConfigList::mouseDoubleClickEvent(QMouseEvent* e)
-{
-	QPoint p = e->pos(); // TODO: Check if this works(was contentsToViewport).
-	ConfigItem* item = (ConfigItem*)itemAt(p);
-	struct menu *menu;
-	enum prop_type ptype;
-
-	if (!item)
-		goto skip;
-	if (item->goParent) {
-		emit parentSelected();
-		goto skip;
-	}
-	menu = item->menu;
-	if (!menu)
-		goto skip;
-	ptype = menu->prompt ? menu->prompt->type : P_UNKNOWN;
-	if (ptype == P_MENU && (mode == singleMode || mode == symbolMode))
-		emit menuSelected(menu);
-	else if (menu->sym)
-		changeValue(item);
-
-skip:
-	//printf("contentsMouseDoubleClickEvent: %d,%d\n", p.x(), p.y());
-	Parent::mouseDoubleClickEvent(e);
-}
-
-void ConfigList::focusInEvent(QFocusEvent *e)
-{
-	struct menu *menu = NULL;
-
-	Parent::focusInEvent(e);
-
-	ConfigItem* item = (ConfigItem *)currentItem();
-	if (item) {
-		item->setSelected(true);
-		menu = item->menu;
-	}
-	emit gotFocus(menu);
-}
-
-void ConfigList::contextMenuEvent(QContextMenuEvent *e)
-{
-	if (e->y() <= header()->geometry().bottom()) {
-		if (!headerPopup) {
-			QAction *action;
-
-			headerPopup = new QMenu(this);
-			action = new QAction("Show Name", this);
-			  action->setCheckable(true);
-			  connect(action, SIGNAL(toggled(bool)),
-				  parent(), SLOT(setShowName(bool)));
-			  connect(parent(), SIGNAL(showNameChanged(bool)),
-				  action, SLOT(setOn(bool)));
-			  action->setChecked(showName);
-			  headerPopup->addAction(action);
-			action = new QAction("Show Range", this);
-			  action->setCheckable(true);
-			  connect(action, SIGNAL(toggled(bool)),
-				  parent(), SLOT(setShowRange(bool)));
-			  connect(parent(), SIGNAL(showRangeChanged(bool)),
-				  action, SLOT(setOn(bool)));
-			  action->setChecked(showRange);
-			  headerPopup->addAction(action);
-			action = new QAction("Show Data", this);
-			  action->setCheckable(true);
-			  connect(action, SIGNAL(toggled(bool)),
-				  parent(), SLOT(setShowData(bool)));
-			  connect(parent(), SIGNAL(showDataChanged(bool)),
-				  action, SLOT(setOn(bool)));
-			  action->setChecked(showData);
-			  headerPopup->addAction(action);
-		}
-		headerPopup->exec(e->globalPos());
-		e->accept();
-	} else
-		e->ignore();
-}
-
-ConfigView*ConfigView::viewList;
-QAction *ConfigView::showNormalAction;
-QAction *ConfigView::showAllAction;
-QAction *ConfigView::showPromptAction;
-
-ConfigView::ConfigView(QWidget* parent, const char *name)
-	: Parent(parent)
-{
-	setObjectName(name);
-	QVBoxLayout *verticalLayout = new QVBoxLayout(this);
-	verticalLayout->setContentsMargins(0, 0, 0, 0);
-
-	list = new ConfigList(this);
-	verticalLayout->addWidget(list);
-	lineEdit = new ConfigLineEdit(this);
-	lineEdit->hide();
-	verticalLayout->addWidget(lineEdit);
-
-	this->nextView = viewList;
-	viewList = this;
-}
-
-ConfigView::~ConfigView(void)
-{
-	ConfigView** vp;
-
-	for (vp = &viewList; *vp; vp = &(*vp)->nextView) {
-		if (*vp == this) {
-			*vp = nextView;
-			break;
-		}
-	}
-}
-
-void ConfigView::setOptionMode(QAction *act)
-{
-	if (act == showNormalAction)
-		list->optMode = normalOpt;
-	else if (act == showAllAction)
-		list->optMode = allOpt;
-	else
-		list->optMode = promptOpt;
-
-	list->updateListAll();
-}
-
-void ConfigView::setShowName(bool b)
-{
-	if (list->showName != b) {
-		list->showName = b;
-		list->reinit();
-		emit showNameChanged(b);
-	}
-}
-
-void ConfigView::setShowRange(bool b)
-{
-	if (list->showRange != b) {
-		list->showRange = b;
-		list->reinit();
-		emit showRangeChanged(b);
-	}
-}
-
-void ConfigView::setShowData(bool b)
-{
-	if (list->showData != b) {
-		list->showData = b;
-		list->reinit();
-		emit showDataChanged(b);
-	}
-}
-
-void ConfigList::setAllOpen(bool open)
-{
-	QTreeWidgetItemIterator it(this);
-
-	while (*it) {
-		(*it)->setExpanded(open);
-
-		++it;
-	}
-}
-
-void ConfigView::updateList(ConfigItem* item)
-{
-	ConfigView* v;
-
-	for (v = viewList; v; v = v->nextView)
-		v->list->updateList(item);
-}
-
-void ConfigView::updateListAll(void)
-{
-	ConfigView* v;
-
-	for (v = viewList; v; v = v->nextView)
-		v->list->updateListAll();
-}
-
-ConfigInfoView::ConfigInfoView(QWidget* parent, const char *name)
-	: Parent(parent), sym(0), _menu(0)
-{
-	setObjectName(name);
-
-
-	if (!objectName().isEmpty()) {
-		configSettings->beginGroup(objectName());
-		setShowDebug(configSettings->value("/showDebug", false).toBool());
-		configSettings->endGroup();
-		connect(configApp, SIGNAL(aboutToQuit()), SLOT(saveSettings()));
-	}
-}
-
-void ConfigInfoView::saveSettings(void)
-{
-	if (!objectName().isEmpty()) {
-		configSettings->beginGroup(objectName());
-		configSettings->setValue("/showDebug", showDebug());
-		configSettings->endGroup();
-	}
-}
-
-void ConfigInfoView::setShowDebug(bool b)
-{
-	if (_showDebug != b) {
-		_showDebug = b;
-		if (_menu)
-			menuInfo();
-		else if (sym)
-			symbolInfo();
-		emit showDebugChanged(b);
-	}
-}
-
-void ConfigInfoView::setInfo(struct menu *m)
-{
-	if (_menu == m)
-		return;
-	_menu = m;
-	sym = NULL;
-	if (!_menu)
-		clear();
-	else
-		menuInfo();
-}
-
-void ConfigInfoView::symbolInfo(void)
-{
-	QString str;
-
-	str += "<big>Symbol: <b>";
-	str += print_filter(sym->name);
-	str += "</b></big><br><br>value: ";
-	str += print_filter(sym_get_string_value(sym));
-	str += "<br>visibility: ";
-	str += sym->visible == yes ? "y" : sym->visible == mod ? "m" : "n";
-	str += "<br>";
-	str += debug_info(sym);
-
-	setText(str);
-}
-
-void ConfigInfoView::menuInfo(void)
-{
-	struct symbol* sym;
-	QString head, debug, help;
-
-	sym = _menu->sym;
-	if (sym) {
-		if (_menu->prompt) {
-			head += "<big><b>";
-			head += print_filter(_menu->prompt->text);
-			head += "</b></big>";
-			if (sym->name) {
-				head += " (";
-				if (showDebug())
-					head += QString().sprintf("<a href=\"s%p\">", sym);
-				head += print_filter(sym->name);
-				if (showDebug())
-					head += "</a>";
-				head += ")";
-			}
-		} else if (sym->name) {
-			head += "<big><b>";
-			if (showDebug())
-				head += QString().sprintf("<a href=\"s%p\">", sym);
-			head += print_filter(sym->name);
-			if (showDebug())
-				head += "</a>";
-			head += "</b></big>";
-		}
-		head += "<br><br>";
-
-		if (showDebug())
-			debug = debug_info(sym);
-
-		struct gstr help_gstr = str_new();
-		menu_get_ext_help(_menu, &help_gstr);
-		help = print_filter(str_get(&help_gstr));
-		str_free(&help_gstr);
-	} else if (_menu->prompt) {
-		head += "<big><b>";
-		head += print_filter(_menu->prompt->text);
-		head += "</b></big><br><br>";
-		if (showDebug()) {
-			if (_menu->prompt->visible.expr) {
-				debug += "&nbsp;&nbsp;dep: ";
-				expr_print(_menu->prompt->visible.expr, expr_print_help, &debug, E_NONE);
-				debug += "<br><br>";
-			}
-		}
-	}
-	if (showDebug())
-		debug += QString().sprintf("defined at %s:%d<br><br>", _menu->file->name, _menu->lineno);
-
-	setText(head + debug + help);
-}
-
-QString ConfigInfoView::debug_info(struct symbol *sym)
-{
-	QString debug;
-
-	debug += "type: ";
-	debug += print_filter(sym_type_name(sym->type));
-	if (sym_is_choice(sym))
-		debug += " (choice)";
-	debug += "<br>";
-	if (sym->rev_dep.expr) {
-		debug += "reverse dep: ";
-		expr_print(sym->rev_dep.expr, expr_print_help, &debug, E_NONE);
-		debug += "<br>";
-	}
-	for (struct property *prop = sym->prop; prop; prop = prop->next) {
-		switch (prop->type) {
-		case P_PROMPT:
-		case P_MENU:
-			debug += QString().sprintf("prompt: <a href=\"m%p\">", prop->menu);
-			debug += print_filter(prop->text);
-			debug += "</a><br>";
-			break;
-		case P_DEFAULT:
-		case P_SELECT:
-		case P_RANGE:
-			debug += prop_get_type_name(prop->type);
-			debug += ": ";
-			expr_print(prop->expr, expr_print_help, &debug, E_NONE);
-			debug += "<br>";
-			break;
-		case P_CHOICE:
-			if (sym_is_choice(sym)) {
-				debug += "choice: ";
-				expr_print(prop->expr, expr_print_help, &debug, E_NONE);
-				debug += "<br>";
-			}
-			break;
-		default:
-			debug += "unknown property: ";
-			debug += prop_get_type_name(prop->type);
-			debug += "<br>";
-		}
-		if (prop->visible.expr) {
-			debug += "&nbsp;&nbsp;&nbsp;&nbsp;dep: ";
-			expr_print(prop->visible.expr, expr_print_help, &debug, E_NONE);
-			debug += "<br>";
-		}
-	}
-	debug += "<br>";
-
-	return debug;
-}
-
-QString ConfigInfoView::print_filter(const QString &str)
-{
-	QRegExp re("[<>&\"\\n]");
-	QString res = str;
-	for (int i = 0; (i = res.indexOf(re, i)) >= 0;) {
-		switch (res[i].toLatin1()) {
-		case '<':
-			res.replace(i, 1, "&lt;");
-			i += 4;
-			break;
-		case '>':
-			res.replace(i, 1, "&gt;");
-			i += 4;
-			break;
-		case '&':
-			res.replace(i, 1, "&amp;");
-			i += 5;
-			break;
-		case '"':
-			res.replace(i, 1, "&quot;");
-			i += 6;
-			break;
-		case '\n':
-			res.replace(i, 1, "<br>");
-			i += 4;
-			break;
-		}
-	}
-	return res;
-}
-
-void ConfigInfoView::expr_print_help(void *data, struct symbol *sym, const char *str)
-{
-	QString* text = reinterpret_cast<QString*>(data);
-	QString str2 = print_filter(str);
-
-	if (sym && sym->name && !(sym->flags & SYMBOL_CONST)) {
-		*text += QString().sprintf("<a href=\"s%p\">", sym);
-		*text += str2;
-		*text += "</a>";
-	} else
-		*text += str2;
-}
-
-QMenu* ConfigInfoView::createStandardContextMenu(const QPoint & pos)
-{
-	QMenu* popup = Parent::createStandardContextMenu(pos);
-	QAction* action = new QAction("Show Debug Info", popup);
-	  action->setCheckable(true);
-	  connect(action, SIGNAL(toggled(bool)), SLOT(setShowDebug(bool)));
-	  connect(this, SIGNAL(showDebugChanged(bool)), action, SLOT(setOn(bool)));
-	  action->setChecked(showDebug());
-	popup->addSeparator();
-	popup->addAction(action);
-	return popup;
-}
-
-void ConfigInfoView::contextMenuEvent(QContextMenuEvent *e)
-{
-	Parent::contextMenuEvent(e);
-}
-
-ConfigSearchWindow::ConfigSearchWindow(ConfigMainWindow* parent, const char *name)
-	: Parent(parent), result(NULL)
-{
-	setObjectName(name);
-	setWindowTitle("Search Config");
-
-	QVBoxLayout* layout1 = new QVBoxLayout(this);
-	layout1->setContentsMargins(11, 11, 11, 11);
-	layout1->setSpacing(6);
-	QHBoxLayout* layout2 = new QHBoxLayout(0);
-	layout2->setContentsMargins(0, 0, 0, 0);
-	layout2->setSpacing(6);
-	layout2->addWidget(new QLabel("Find:", this));
-	editField = new QLineEdit(this);
-	connect(editField, SIGNAL(returnPressed()), SLOT(search()));
-	layout2->addWidget(editField);
-	searchButton = new QPushButton("Search", this);
-	searchButton->setAutoDefault(false);
-	connect(searchButton, SIGNAL(clicked()), SLOT(search()));
-	layout2->addWidget(searchButton);
-	layout1->addLayout(layout2);
-
-	split = new QSplitter(this);
-	split->setOrientation(Qt::Vertical);
-	list = new ConfigView(split, name);
-	list->list->mode = listMode;
-	info = new ConfigInfoView(split, name);
-	connect(list->list, SIGNAL(menuChanged(struct menu *)),
-		info, SLOT(setInfo(struct menu *)));
-	connect(list->list, SIGNAL(menuChanged(struct menu *)),
-		parent, SLOT(setMenuLink(struct menu *)));
-
-	layout1->addWidget(split);
-
-	if (name) {
-		QVariant x, y;
-		int width, height;
-		bool ok;
-
-		configSettings->beginGroup(name);
-		width = configSettings->value("/window width", parent->width() / 2).toInt();
-		height = configSettings->value("/window height", parent->height() / 2).toInt();
-		resize(width, height);
-		x = configSettings->value("/window x");
-		y = configSettings->value("/window y");
-		if ((x.isValid())&&(y.isValid()))
-			move(x.toInt(), y.toInt());
-		QList<int> sizes = configSettings->readSizes("/split", &ok);
-		if (ok)
-			split->setSizes(sizes);
-		configSettings->endGroup();
-		connect(configApp, SIGNAL(aboutToQuit()), SLOT(saveSettings()));
-	}
-}
-
-void ConfigSearchWindow::saveSettings(void)
-{
-	if (!objectName().isEmpty()) {
-		configSettings->beginGroup(objectName());
-		configSettings->setValue("/window x", pos().x());
-		configSettings->setValue("/window y", pos().y());
-		configSettings->setValue("/window width", size().width());
-		configSettings->setValue("/window height", size().height());
-		configSettings->writeSizes("/split", split->sizes());
-		configSettings->endGroup();
-	}
-}
-
-void ConfigSearchWindow::search(void)
-{
-	struct symbol **p;
-	struct property *prop;
-	ConfigItem *lastItem = NULL;
-
-	free(result);
-	list->list->clear();
-	info->clear();
-
-	result = sym_re_search(editField->text().toLatin1());
-	if (!result)
-		return;
-	for (p = result; *p; p++) {
-		for_all_prompts((*p), prop)
-			lastItem = new ConfigItem(list->list, lastItem, prop->menu,
-						  menu_is_visible(prop->menu));
-	}
-}
-
-/*
- * Construct the complete config widget
- */
-ConfigMainWindow::ConfigMainWindow(void)
-	: searchWindow(0)
-{
-	QMenuBar* menu;
-	bool ok = true;
-	QVariant x, y;
-	int width, height;
-	char title[256];
-
-	QDesktopWidget *d = configApp->desktop();
-	snprintf(title, sizeof(title), "%s%s",
-		rootmenu.prompt->text,
-		""
-		);
-	setWindowTitle(title);
-
-	width = configSettings->value("/window width", d->width() - 64).toInt();
-	height = configSettings->value("/window height", d->height() - 64).toInt();
-	resize(width, height);
-	x = configSettings->value("/window x");
-	y = configSettings->value("/window y");
-	if ((x.isValid())&&(y.isValid()))
-		move(x.toInt(), y.toInt());
-
-	split1 = new QSplitter(this);
-	split1->setOrientation(Qt::Horizontal);
-	setCentralWidget(split1);
-
-	menuView = new ConfigView(split1, "menu");
-	menuList = menuView->list;
-
-	split2 = new QSplitter(split1);
-	split2->setOrientation(Qt::Vertical);
-
-	// create config tree
-	configView = new ConfigView(split2, "config");
-	configList = configView->list;
-
-	helpText = new ConfigInfoView(split2, "help");
-
-	setTabOrder(configList, helpText);
-	configList->setFocus();
-
-	menu = menuBar();
-	toolBar = new QToolBar("Tools", this);
-	addToolBar(toolBar);
-
-	backAction = new QAction(QPixmap(xpm_back), "Back", this);
-	  connect(backAction, SIGNAL(triggered(bool)), SLOT(goBack()));
-	  backAction->setEnabled(false);
-	QAction *quitAction = new QAction("&Quit", this);
-	quitAction->setShortcut(Qt::CTRL + Qt::Key_Q);
-	  connect(quitAction, SIGNAL(triggered(bool)), SLOT(close()));
-	QAction *loadAction = new QAction(QPixmap(xpm_load), "&Load", this);
-	loadAction->setShortcut(Qt::CTRL + Qt::Key_L);
-	  connect(loadAction, SIGNAL(triggered(bool)), SLOT(loadConfig()));
-	saveAction = new QAction(QPixmap(xpm_save), "&Save", this);
-	saveAction->setShortcut(Qt::CTRL + Qt::Key_S);
-	  connect(saveAction, SIGNAL(triggered(bool)), SLOT(saveConfig()));
-	conf_set_changed_callback(conf_changed);
-	// Set saveAction's initial state
-	conf_changed();
-	configname = xstrdup(conf_get_configname());
-
-	QAction *saveAsAction = new QAction("Save &As...", this);
-	  connect(saveAsAction, SIGNAL(triggered(bool)), SLOT(saveConfigAs()));
-	QAction *searchAction = new QAction("&Find", this);
-	searchAction->setShortcut(Qt::CTRL + Qt::Key_F);
-	  connect(searchAction, SIGNAL(triggered(bool)), SLOT(searchConfig()));
-	singleViewAction = new QAction(QPixmap(xpm_single_view), "Single View", this);
-	singleViewAction->setCheckable(true);
-	  connect(singleViewAction, SIGNAL(triggered(bool)), SLOT(showSingleView()));
-	splitViewAction = new QAction(QPixmap(xpm_split_view), "Split View", this);
-	splitViewAction->setCheckable(true);
-	  connect(splitViewAction, SIGNAL(triggered(bool)), SLOT(showSplitView()));
-	fullViewAction = new QAction(QPixmap(xpm_tree_view), "Full View", this);
-	fullViewAction->setCheckable(true);
-	  connect(fullViewAction, SIGNAL(triggered(bool)), SLOT(showFullView()));
-
-	QAction *showNameAction = new QAction("Show Name", this);
-	  showNameAction->setCheckable(true);
-	  connect(showNameAction, SIGNAL(toggled(bool)), configView, SLOT(setShowName(bool)));
-	  showNameAction->setChecked(configView->showName());
-	QAction *showRangeAction = new QAction("Show Range", this);
-	  showRangeAction->setCheckable(true);
-	  connect(showRangeAction, SIGNAL(toggled(bool)), configView, SLOT(setShowRange(bool)));
-	QAction *showDataAction = new QAction("Show Data", this);
-	  showDataAction->setCheckable(true);
-	  connect(showDataAction, SIGNAL(toggled(bool)), configView, SLOT(setShowData(bool)));
-
-	QActionGroup *optGroup = new QActionGroup(this);
-	optGroup->setExclusive(true);
-	connect(optGroup, SIGNAL(triggered(QAction*)), configView,
-		SLOT(setOptionMode(QAction *)));
-	connect(optGroup, SIGNAL(triggered(QAction *)), menuView,
-		SLOT(setOptionMode(QAction *)));
-
-	configView->showNormalAction = new QAction("Show Normal Options", optGroup);
-	configView->showAllAction = new QAction("Show All Options", optGroup);
-	configView->showPromptAction = new QAction("Show Prompt Options", optGroup);
-	configView->showNormalAction->setCheckable(true);
-	configView->showAllAction->setCheckable(true);
-	configView->showPromptAction->setCheckable(true);
-
-	QAction *showDebugAction = new QAction("Show Debug Info", this);
-	  showDebugAction->setCheckable(true);
-	  connect(showDebugAction, SIGNAL(toggled(bool)), helpText, SLOT(setShowDebug(bool)));
-	  showDebugAction->setChecked(helpText->showDebug());
-
-	QAction *showIntroAction = new QAction("Introduction", this);
-	  connect(showIntroAction, SIGNAL(triggered(bool)), SLOT(showIntro()));
-	QAction *showAboutAction = new QAction("About", this);
-	  connect(showAboutAction, SIGNAL(triggered(bool)), SLOT(showAbout()));
-
-	// init tool bar
-	toolBar->addAction(backAction);
-	toolBar->addSeparator();
-	toolBar->addAction(loadAction);
-	toolBar->addAction(saveAction);
-	toolBar->addSeparator();
-	toolBar->addAction(singleViewAction);
-	toolBar->addAction(splitViewAction);
-	toolBar->addAction(fullViewAction);
-
-	// create config menu
-	QMenu* config = menu->addMenu("&File");
-	config->addAction(loadAction);
-	config->addAction(saveAction);
-	config->addAction(saveAsAction);
-	config->addSeparator();
-	config->addAction(quitAction);
-
-	// create edit menu
-	QMenu* editMenu = menu->addMenu("&Edit");
-	editMenu->addAction(searchAction);
-
-	// create options menu
-	QMenu* optionMenu = menu->addMenu("&Option");
-	optionMenu->addAction(showNameAction);
-	optionMenu->addAction(showRangeAction);
-	optionMenu->addAction(showDataAction);
-	optionMenu->addSeparator();
-	optionMenu->addActions(optGroup->actions());
-	optionMenu->addSeparator();
-	optionMenu->addAction(showDebugAction);
-
-	// create help menu
-	menu->addSeparator();
-	QMenu* helpMenu = menu->addMenu("&Help");
-	helpMenu->addAction(showIntroAction);
-	helpMenu->addAction(showAboutAction);
-
-	connect(configList, SIGNAL(menuChanged(struct menu *)),
-		helpText, SLOT(setInfo(struct menu *)));
-	connect(configList, SIGNAL(menuSelected(struct menu *)),
-		SLOT(changeMenu(struct menu *)));
-	connect(configList, SIGNAL(parentSelected()),
-		SLOT(goBack()));
-	connect(menuList, SIGNAL(menuChanged(struct menu *)),
-		helpText, SLOT(setInfo(struct menu *)));
-	connect(menuList, SIGNAL(menuSelected(struct menu *)),
-		SLOT(changeMenu(struct menu *)));
-
-	connect(configList, SIGNAL(gotFocus(struct menu *)),
-		helpText, SLOT(setInfo(struct menu *)));
-	connect(menuList, SIGNAL(gotFocus(struct menu *)),
-		helpText, SLOT(setInfo(struct menu *)));
-	connect(menuList, SIGNAL(gotFocus(struct menu *)),
-		SLOT(listFocusChanged(void)));
-	connect(helpText, SIGNAL(menuSelected(struct menu *)),
-		SLOT(setMenuLink(struct menu *)));
-
-	QString listMode = configSettings->value("/listMode", "symbol").toString();
-	if (listMode == "single")
-		showSingleView();
-	else if (listMode == "full")
-		showFullView();
-	else /*if (listMode == "split")*/
-		showSplitView();
-
-	// UI setup done, restore splitter positions
-	QList<int> sizes = configSettings->readSizes("/split1", &ok);
-	if (ok)
-		split1->setSizes(sizes);
-
-	sizes = configSettings->readSizes("/split2", &ok);
-	if (ok)
-		split2->setSizes(sizes);
-}
-
-void ConfigMainWindow::loadConfig(void)
-{
-	QString str;
-	QByteArray ba;
-	const char *name;
-
-	str = QFileDialog::getOpenFileName(this, "", configname);
-	if (str.isNull())
-		return;
-
-	ba = str.toLocal8Bit();
-	name = ba.data();
-
-	if (conf_read(name))
-		QMessageBox::information(this, "qconf", "Unable to load configuration!");
-
-	free(configname);
-	configname = xstrdup(name);
-
-	ConfigView::updateListAll();
-}
-
-bool ConfigMainWindow::saveConfig(void)
-{
-	if (conf_write(configname)) {
-		QMessageBox::information(this, "qconf", "Unable to save configuration!");
-		return false;
-	}
-	conf_write_autoconf(0);
-
-	return true;
-}
-
-void ConfigMainWindow::saveConfigAs(void)
-{
-	QString str;
-	QByteArray ba;
-	const char *name;
-
-	str = QFileDialog::getSaveFileName(this, "", configname);
-	if (str.isNull())
-		return;
-
-	ba = str.toLocal8Bit();
-	name = ba.data();
-
-	if (conf_write(name)) {
-		QMessageBox::information(this, "qconf", "Unable to save configuration!");
-	}
-	conf_write_autoconf(0);
-
-	free(configname);
-	configname = xstrdup(name);
-}
-
-void ConfigMainWindow::searchConfig(void)
-{
-	if (!searchWindow)
-		searchWindow = new ConfigSearchWindow(this, "search");
-	searchWindow->show();
-}
-
-void ConfigMainWindow::changeMenu(struct menu *menu)
-{
-	configList->setRootMenu(menu);
-	if (configList->rootEntry->parent == &rootmenu)
-		backAction->setEnabled(false);
-	else
-		backAction->setEnabled(true);
-}
-
-void ConfigMainWindow::setMenuLink(struct menu *menu)
-{
-	struct menu *parent;
-	ConfigList* list = NULL;
-	ConfigItem* item;
-
-	if (configList->menuSkip(menu))
-		return;
-
-	switch (configList->mode) {
-	case singleMode:
-		list = configList;
-		parent = menu_get_parent_menu(menu);
-		if (!parent)
-			return;
-		list->setRootMenu(parent);
-		break;
-	case symbolMode:
-		if (menu->flags & MENU_ROOT) {
-			configList->setRootMenu(menu);
-			configList->clearSelection();
-			list = menuList;
-		} else {
-			list = configList;
-			parent = menu_get_parent_menu(menu->parent);
-			if (!parent)
-				return;
-			item = menuList->findConfigItem(parent);
-			if (item) {
-				item->setSelected(true);
-				menuList->scrollToItem(item);
-			}
-			list->setRootMenu(parent);
-		}
-		break;
-	case fullMode:
-		list = configList;
-		break;
-	default:
-		break;
-	}
-
-	if (list) {
-		item = list->findConfigItem(menu);
-		if (item) {
-			item->setSelected(true);
-			list->scrollToItem(item);
-			list->setFocus();
-		}
-	}
-}
-
-void ConfigMainWindow::listFocusChanged(void)
-{
-	if (menuList->mode == menuMode)
-		configList->clearSelection();
-}
-
-void ConfigMainWindow::goBack(void)
-{
-	ConfigItem* item, *oldSelection;
-
-	configList->setParentMenu();
-	if (configList->rootEntry == &rootmenu)
-		backAction->setEnabled(false);
-
-	if (menuList->selectedItems().count() == 0)
-		return;
-
-	item = (ConfigItem*)menuList->selectedItems().first();
-	oldSelection = item;
-	while (item) {
-		if (item->menu == configList->rootEntry) {
-			oldSelection->setSelected(false);
-			item->setSelected(true);
-			break;
-		}
-		item = (ConfigItem*)item->parent();
-	}
-}
-
-void ConfigMainWindow::showSingleView(void)
-{
-	singleViewAction->setEnabled(false);
-	singleViewAction->setChecked(true);
-	splitViewAction->setEnabled(true);
-	splitViewAction->setChecked(false);
-	fullViewAction->setEnabled(true);
-	fullViewAction->setChecked(false);
-
-	menuView->hide();
-	menuList->setRootMenu(0);
-	configList->mode = singleMode;
-	if (configList->rootEntry == &rootmenu)
-		configList->updateListAll();
-	else
-		configList->setRootMenu(&rootmenu);
-	configList->setFocus();
-}
-
-void ConfigMainWindow::showSplitView(void)
-{
-	singleViewAction->setEnabled(true);
-	singleViewAction->setChecked(false);
-	splitViewAction->setEnabled(false);
-	splitViewAction->setChecked(true);
-	fullViewAction->setEnabled(true);
-	fullViewAction->setChecked(false);
-
-	configList->mode = symbolMode;
-	if (configList->rootEntry == &rootmenu)
-		configList->updateListAll();
-	else
-		configList->setRootMenu(&rootmenu);
-	configList->setAllOpen(true);
-	configApp->processEvents();
-	menuList->mode = menuMode;
-	menuList->setRootMenu(&rootmenu);
-	menuList->setAllOpen(true);
-	menuView->show();
-	menuList->setFocus();
-}
-
-void ConfigMainWindow::showFullView(void)
-{
-	singleViewAction->setEnabled(true);
-	singleViewAction->setChecked(false);
-	splitViewAction->setEnabled(true);
-	splitViewAction->setChecked(false);
-	fullViewAction->setEnabled(false);
-	fullViewAction->setChecked(true);
-
-	menuView->hide();
-	menuList->setRootMenu(0);
-	configList->mode = fullMode;
-	if (configList->rootEntry == &rootmenu)
-		configList->updateListAll();
-	else
-		configList->setRootMenu(&rootmenu);
-	configList->setFocus();
-}
-
-/*
- * ask for saving configuration before quitting
- * TODO ask only when something changed
- */
-void ConfigMainWindow::closeEvent(QCloseEvent* e)
-{
-	if (!conf_get_changed()) {
-		e->accept();
-		return;
-	}
-	QMessageBox mb("qconf", "Save configuration?", QMessageBox::Warning,
-			QMessageBox::Yes | QMessageBox::Default, QMessageBox::No, QMessageBox::Cancel | QMessageBox::Escape);
-	mb.setButtonText(QMessageBox::Yes, "&Save Changes");
-	mb.setButtonText(QMessageBox::No, "&Discard Changes");
-	mb.setButtonText(QMessageBox::Cancel, "Cancel Exit");
-	switch (mb.exec()) {
-	case QMessageBox::Yes:
-		if (saveConfig())
-			e->accept();
-		else
-			e->ignore();
-		break;
-	case QMessageBox::No:
-		e->accept();
-		break;
-	case QMessageBox::Cancel:
-		e->ignore();
-		break;
-	}
-}
-
-void ConfigMainWindow::showIntro(void)
-{
-	static const QString str = "Welcome to the qconf graphical configuration tool.\n\n"
-		"For each option, a blank box indicates the feature is disabled, a check\n"
-		"indicates it is enabled, and a dot indicates that it is to be compiled\n"
-		"as a module.  Clicking on the box will cycle through the three states.\n\n"
-		"If you do not see an option (e.g., a device driver) that you believe\n"
-		"should be present, try turning on Show All Options under the Options menu.\n"
-		"Although there is no cross reference yet to help you figure out what other\n"
-		"options must be enabled to support the option you are interested in, you can\n"
-		"still view the help of a grayed-out option.\n\n"
-		"Toggling Show Debug Info under the Options menu will show the dependencies,\n"
-		"which you can then match by examining other options.\n\n";
-
-	QMessageBox::information(this, "qconf", str);
-}
-
-void ConfigMainWindow::showAbout(void)
-{
-	static const QString str = "qconf is Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org>.\n"
-		"Copyright (C) 2015 Boris Barbulovski <bbarbulovski@gmail.com>.\n\n"
-		"Bug reports and feature request can also be entered at http://bugzilla.kernel.org/\n";
-
-	QMessageBox::information(this, "qconf", str);
-}
-
-void ConfigMainWindow::saveSettings(void)
-{
-	configSettings->setValue("/window x", pos().x());
-	configSettings->setValue("/window y", pos().y());
-	configSettings->setValue("/window width", size().width());
-	configSettings->setValue("/window height", size().height());
-
-	QString entry;
-	switch(configList->mode) {
-	case singleMode :
-		entry = "single";
-		break;
-
-	case symbolMode :
-		entry = "split";
-		break;
-
-	case fullMode :
-		entry = "full";
-		break;
-
-	default:
-		break;
-	}
-	configSettings->setValue("/listMode", entry);
-
-	configSettings->writeSizes("/split1", split1->sizes());
-	configSettings->writeSizes("/split2", split2->sizes());
-}
-
-void ConfigMainWindow::conf_changed(void)
-{
-	if (saveAction)
-		saveAction->setEnabled(conf_get_changed());
-}
-
-void fixup_rootmenu(struct menu *menu)
-{
-	struct menu *child;
-	static int menu_cnt = 0;
-
-	menu->flags |= MENU_ROOT;
-	for (child = menu->list; child; child = child->next) {
-		if (child->prompt && child->prompt->type == P_MENU) {
-			menu_cnt++;
-			fixup_rootmenu(child);
-			menu_cnt--;
-		} else if (!menu_cnt)
-			fixup_rootmenu(child);
-	}
-}
-
-static const char *progname;
-
-static void usage(void)
-{
-	printf("%s [-s] <config>\n", progname);
-	exit(0);
-}
-
-int main(int ac, char** av)
-{
-	ConfigMainWindow* v;
-	const char *name;
-
-	progname = av[0];
-	configApp = new QApplication(ac, av);
-	if (ac > 1 && av[1][0] == '-') {
-		switch (av[1][1]) {
-		case 's':
-			conf_set_message_callback(NULL);
-			break;
-		case 'h':
-		case '?':
-			usage();
-		}
-		name = av[2];
-	} else
-		name = av[1];
-	if (!name)
-		usage();
-
-	conf_parse(name);
-	fixup_rootmenu(&rootmenu);
-	conf_read(NULL);
-	//zconfdump(stdout);
-
-	configSettings = new ConfigSettings();
-	configSettings->beginGroup("/kconfig/qconf");
-	v = new ConfigMainWindow();
-
-	//zconfdump(stdout);
-	configApp->connect(configApp, SIGNAL(lastWindowClosed()), SLOT(quit()));
-	configApp->connect(configApp, SIGNAL(aboutToQuit()), v, SLOT(saveSettings()));
-	v->show();
-	configApp->exec();
-
-	configSettings->endGroup();
-	delete configSettings;
-	delete v;
-	delete configApp;
-
-	return 0;
-}
diff --git a/util/kconfig/qconf.h b/util/kconfig/qconf.h
deleted file mode 100644
index 45bfe9b2b9..0000000000
--- a/util/kconfig/qconf.h
+++ /dev/null
@@ -1,331 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org>
- */
-
-#include <QTextBrowser>
-#include <QTreeWidget>
-#include <QMainWindow>
-#include <QHeaderView>
-#include <qsettings.h>
-#include <QPushButton>
-#include <QSettings>
-#include <QLineEdit>
-#include <QSplitter>
-#include <QCheckBox>
-#include <QDialog>
-#include "expr.h"
-
-class ConfigView;
-class ConfigList;
-class ConfigItem;
-class ConfigLineEdit;
-class ConfigMainWindow;
-
-class ConfigSettings : public QSettings {
-public:
-	ConfigSettings();
-	QList<int> readSizes(const QString& key, bool *ok);
-	bool writeSizes(const QString& key, const QList<int>& value);
-};
-
-enum colIdx {
-	promptColIdx, nameColIdx, noColIdx, modColIdx, yesColIdx, dataColIdx, colNr
-};
-enum listMode {
-	singleMode, menuMode, symbolMode, fullMode, listMode
-};
-enum optionMode {
-	normalOpt = 0, allOpt, promptOpt
-};
-
-class ConfigList : public QTreeWidget {
-	Q_OBJECT
-	typedef class QTreeWidget Parent;
-public:
-	ConfigList(ConfigView* p, const char *name = 0);
-	void reinit(void);
-	ConfigView* parent(void) const
-	{
-		return (ConfigView*)Parent::parent();
-	}
-	ConfigItem* findConfigItem(struct menu *);
-
-protected:
-	void keyPressEvent(QKeyEvent *e);
-	void mousePressEvent(QMouseEvent *e);
-	void mouseReleaseEvent(QMouseEvent *e);
-	void mouseMoveEvent(QMouseEvent *e);
-	void mouseDoubleClickEvent(QMouseEvent *e);
-	void focusInEvent(QFocusEvent *e);
-	void contextMenuEvent(QContextMenuEvent *e);
-
-public slots:
-	void setRootMenu(struct menu *menu);
-
-	void updateList(ConfigItem *item);
-	void setValue(ConfigItem* item, tristate val);
-	void changeValue(ConfigItem* item);
-	void updateSelection(void);
-	void saveSettings(void);
-signals:
-	void menuChanged(struct menu *menu);
-	void menuSelected(struct menu *menu);
-	void parentSelected(void);
-	void gotFocus(struct menu *);
-
-public:
-	void updateListAll(void)
-	{
-		updateAll = true;
-		updateList(NULL);
-		updateAll = false;
-	}
-	ConfigList* listView()
-	{
-		return this;
-	}
-	ConfigItem* firstChild() const
-	{
-		return (ConfigItem *)children().first();
-	}
-	void addColumn(colIdx idx)
-	{
-		showColumn(idx);
-	}
-	void removeColumn(colIdx idx)
-	{
-		hideColumn(idx);
-	}
-	void setAllOpen(bool open);
-	void setParentMenu(void);
-
-	bool menuSkip(struct menu *);
-
-	void updateMenuList(ConfigItem *parent, struct menu*);
-	void updateMenuList(ConfigList *parent, struct menu*);
-
-	bool updateAll;
-
-	QPixmap symbolYesPix, symbolModPix, symbolNoPix;
-	QPixmap choiceYesPix, choiceNoPix;
-	QPixmap menuPix, menuInvPix, menuBackPix, voidPix;
-
-	bool showName, showRange, showData;
-	enum listMode mode;
-	enum optionMode optMode;
-	struct menu *rootEntry;
-	QPalette disabledColorGroup;
-	QPalette inactivedColorGroup;
-	QMenu* headerPopup;
-};
-
-class ConfigItem : public QTreeWidgetItem {
-	typedef class QTreeWidgetItem Parent;
-public:
-	ConfigItem(ConfigList *parent, ConfigItem *after, struct menu *m, bool v)
-	: Parent(parent, after), nextItem(0), menu(m), visible(v), goParent(false)
-	{
-		init();
-	}
-	ConfigItem(ConfigItem *parent, ConfigItem *after, struct menu *m, bool v)
-	: Parent(parent, after), nextItem(0), menu(m), visible(v), goParent(false)
-	{
-		init();
-	}
-	ConfigItem(ConfigList *parent, ConfigItem *after, bool v)
-	: Parent(parent, after), nextItem(0), menu(0), visible(v), goParent(true)
-	{
-		init();
-	}
-	~ConfigItem(void);
-	void init(void);
-	void okRename(int col);
-	void updateMenu(void);
-	void testUpdateMenu(bool v);
-	ConfigList* listView() const
-	{
-		return (ConfigList*)Parent::treeWidget();
-	}
-	ConfigItem* firstChild() const
-	{
-		return (ConfigItem *)Parent::child(0);
-	}
-	ConfigItem* nextSibling()
-	{
-		ConfigItem *ret = NULL;
-		ConfigItem *_parent = (ConfigItem *)parent();
-
-		if(_parent) {
-			ret = (ConfigItem *)_parent->child(_parent->indexOfChild(this)+1);
-		} else {
-			QTreeWidget *_treeWidget = treeWidget();
-			ret = (ConfigItem *)_treeWidget->topLevelItem(_treeWidget->indexOfTopLevelItem(this)+1);
-		}
-
-		return ret;
-	}
-	void setText(colIdx idx, const QString& text)
-	{
-		Parent::setText(idx, text);
-	}
-	QString text(colIdx idx) const
-	{
-		return Parent::text(idx);
-	}
-	void setPixmap(colIdx idx, const QIcon &icon)
-	{
-		Parent::setIcon(idx, icon);
-	}
-	const QIcon pixmap(colIdx idx) const
-	{
-		return icon(idx);
-	}
-	// TODO: Implement paintCell
-
-	ConfigItem* nextItem;
-	struct menu *menu;
-	bool visible;
-	bool goParent;
-};
-
-class ConfigLineEdit : public QLineEdit {
-	Q_OBJECT
-	typedef class QLineEdit Parent;
-public:
-	ConfigLineEdit(ConfigView* parent);
-	ConfigView* parent(void) const
-	{
-		return (ConfigView*)Parent::parent();
-	}
-	void show(ConfigItem *i);
-	void keyPressEvent(QKeyEvent *e);
-
-public:
-	ConfigItem *item;
-};
-
-class ConfigView : public QWidget {
-	Q_OBJECT
-	typedef class QWidget Parent;
-public:
-	ConfigView(QWidget* parent, const char *name = 0);
-	~ConfigView(void);
-	static void updateList(ConfigItem* item);
-	static void updateListAll(void);
-
-	bool showName(void) const { return list->showName; }
-	bool showRange(void) const { return list->showRange; }
-	bool showData(void) const { return list->showData; }
-public slots:
-	void setShowName(bool);
-	void setShowRange(bool);
-	void setShowData(bool);
-	void setOptionMode(QAction *);
-signals:
-	void showNameChanged(bool);
-	void showRangeChanged(bool);
-	void showDataChanged(bool);
-public:
-	ConfigList* list;
-	ConfigLineEdit* lineEdit;
-
-	static ConfigView* viewList;
-	ConfigView* nextView;
-
-	static QAction *showNormalAction;
-	static QAction *showAllAction;
-	static QAction *showPromptAction;
-};
-
-class ConfigInfoView : public QTextBrowser {
-	Q_OBJECT
-	typedef class QTextBrowser Parent;
-public:
-	ConfigInfoView(QWidget* parent, const char *name = 0);
-	bool showDebug(void) const { return _showDebug; }
-
-public slots:
-	void setInfo(struct menu *menu);
-	void saveSettings(void);
-	void setShowDebug(bool);
-
-signals:
-	void showDebugChanged(bool);
-	void menuSelected(struct menu *);
-
-protected:
-	void symbolInfo(void);
-	void menuInfo(void);
-	QString debug_info(struct symbol *sym);
-	static QString print_filter(const QString &str);
-	static void expr_print_help(void *data, struct symbol *sym, const char *str);
-	QMenu *createStandardContextMenu(const QPoint & pos);
-	void contextMenuEvent(QContextMenuEvent *e);
-
-	struct symbol *sym;
-	struct menu *_menu;
-	bool _showDebug;
-};
-
-class ConfigSearchWindow : public QDialog {
-	Q_OBJECT
-	typedef class QDialog Parent;
-public:
-	ConfigSearchWindow(ConfigMainWindow* parent, const char *name = 0);
-
-public slots:
-	void saveSettings(void);
-	void search(void);
-
-protected:
-	QLineEdit* editField;
-	QPushButton* searchButton;
-	QSplitter* split;
-	ConfigView* list;
-	ConfigInfoView* info;
-
-	struct symbol **result;
-};
-
-class ConfigMainWindow : public QMainWindow {
-	Q_OBJECT
-
-	char *configname;
-	static QAction *saveAction;
-	static void conf_changed(void);
-public:
-	ConfigMainWindow(void);
-public slots:
-	void changeMenu(struct menu *);
-	void setMenuLink(struct menu *);
-	void listFocusChanged(void);
-	void goBack(void);
-	void loadConfig(void);
-	bool saveConfig(void);
-	void saveConfigAs(void);
-	void searchConfig(void);
-	void showSingleView(void);
-	void showSplitView(void);
-	void showFullView(void);
-	void showIntro(void);
-	void showAbout(void);
-	void saveSettings(void);
-
-protected:
-	void closeEvent(QCloseEvent *e);
-
-	ConfigSearchWindow *searchWindow;
-	ConfigView *menuView;
-	ConfigList *menuList;
-	ConfigView *configView;
-	ConfigList *configList;
-	ConfigInfoView *helpText;
-	QToolBar *toolBar;
-	QAction *backAction;
-	QAction *singleViewAction;
-	QAction *splitViewAction;
-	QAction *fullViewAction;
-	QSplitter *split1;
-	QSplitter *split2;
-};
diff --git a/util/kconfig/streamline_config.pl b/util/kconfig/streamline_config.pl
deleted file mode 100755
index 08d76d7b3b..0000000000
--- a/util/kconfig/streamline_config.pl
+++ /dev/null
@@ -1,682 +0,0 @@
-#!/usr/bin/env perl
-# SPDX-License-Identifier: GPL-2.0
-#
-# Copyright 2005-2009 - Steven Rostedt
-#
-#  It's simple enough to figure out how this works.
-#  If not, then you can ask me at stripconfig@goodmis.org
-#
-# What it does?
-#
-#   If you have installed a Linux kernel from a distribution
-#   that turns on way too many modules than you need, and
-#   you only want the modules you use, then this program
-#   is perfect for you.
-#
-#   It gives you the ability to turn off all the modules that are
-#   not loaded on your system.
-#
-# Howto:
-#
-#  1. Boot up the kernel that you want to stream line the config on.
-#  2. Change directory to the directory holding the source of the
-#       kernel that you just booted.
-#  3. Copy the configuraton file to this directory as .config
-#  4. Have all your devices that you need modules for connected and
-#      operational (make sure that their corresponding modules are loaded)
-#  5. Run this script redirecting the output to some other file
-#       like config_strip.
-#  6. Back up your old config (if you want too).
-#  7. copy the config_strip file to .config
-#  8. Run "make oldconfig"
-#
-#  Now your kernel is ready to be built with only the modules that
-#  are loaded.
-#
-# Here's what I did with my Debian distribution.
-#
-#    cd /usr/src/linux-2.6.10
-#    cp /boot/config-2.6.10-1-686-smp .config
-#    ~/bin/streamline_config > config_strip
-#    mv .config config_sav
-#    mv config_strip .config
-#    make oldconfig
-#
-use warnings;
-use strict;
-use Getopt::Long;
-
-# set the environment variable LOCALMODCONFIG_DEBUG to get
-# debug output.
-my $debugprint = 0;
-$debugprint = 1 if (defined($ENV{LOCALMODCONFIG_DEBUG}));
-
-sub dprint {
-    return if (!$debugprint);
-    print STDERR @_;
-}
-
-my $config = ".config";
-
-my $uname = `uname -r`;
-chomp $uname;
-
-my @searchconfigs = (
-	{
-	    "file" => ".config",
-	    "exec" => "cat",
-	},
-	{
-	    "file" => "/proc/config.gz",
-	    "exec" => "zcat",
-	},
-	{
-	    "file" => "/boot/config-$uname",
-	    "exec" => "cat",
-	},
-	{
-	    "file" => "/boot/vmlinuz-$uname",
-	    "exec" => "scripts/extract-ikconfig",
-	    "test" => "scripts/extract-ikconfig",
-	},
-	{
-	    "file" => "vmlinux",
-	    "exec" => "scripts/extract-ikconfig",
-	    "test" => "scripts/extract-ikconfig",
-	},
-	{
-	    "file" => "/lib/modules/$uname/kernel/kernel/configs.ko",
-	    "exec" => "scripts/extract-ikconfig",
-	    "test" => "scripts/extract-ikconfig",
-	},
-	{
-	    "file" => "kernel/configs.ko",
-	    "exec" => "scripts/extract-ikconfig",
-	    "test" => "scripts/extract-ikconfig",
-	},
-	{
-	    "file" => "kernel/configs.o",
-	    "exec" => "scripts/extract-ikconfig",
-	    "test" => "scripts/extract-ikconfig",
-	},
-);
-
-sub read_config {
-    foreach my $conf (@searchconfigs) {
-	my $file = $conf->{"file"};
-
-	next if ( ! -f "$file");
-
-	if (defined($conf->{"test"})) {
-	    `$conf->{"test"} $conf->{"file"} 2>/dev/null`;
-	    next if ($?);
-	}
-
-	my $exec = $conf->{"exec"};
-
-	print STDERR "using config: '$file'\n";
-
-	open(my $infile, '-|', "$exec $file") || die "Failed to run $exec $file";
-	my @x = <$infile>;
-	close $infile;
-	return @x;
-    }
-    die "No config file found";
-}
-
-my @config_file = read_config;
-
-# Parse options
-my $localmodconfig = 0;
-my $localyesconfig = 0;
-
-GetOptions("localmodconfig" => \$localmodconfig,
-	   "localyesconfig" => \$localyesconfig);
-
-# Get the build source and top level Kconfig file (passed in)
-my $ksource = ($ARGV[0] ? $ARGV[0] : '.');
-my $kconfig = $ARGV[1];
-my $lsmod_file = $ENV{'LSMOD'};
-
-my @makefiles = `find $ksource -name Makefile -or -name Kbuild 2>/dev/null`;
-chomp @makefiles;
-
-my %depends;
-my %selects;
-my %prompts;
-my %objects;
-my $var;
-my $iflevel = 0;
-my @ifdeps;
-
-# prevent recursion
-my %read_kconfigs;
-
-sub read_kconfig {
-    my ($kconfig) = @_;
-
-    my $state = "NONE";
-    my $config;
-
-    my $cont = 0;
-    my $line;
-
-    my $source = "$ksource/$kconfig";
-    my $last_source = "";
-
-    # Check for any environment variables used
-    while ($source =~ /\$\((\w+)\)/ && $last_source ne $source) {
-	my $env = $1;
-	$last_source = $source;
-	$source =~ s/\$\($env\)/$ENV{$env}/;
-    }
-
-    open(my $kinfile, '<', $source) || die "Can't open $kconfig";
-    while (<$kinfile>) {
-	chomp;
-
-	# Make sure that lines ending with \ continue
-	if ($cont) {
-	    $_ = $line . " " . $_;
-	}
-
-	if (s/\\$//) {
-	    $cont = 1;
-	    $line = $_;
-	    next;
-	}
-
-	$cont = 0;
-
-	# collect any Kconfig sources
-	if (/^source\s+"?([^"]+)/) {
-	    my $kconfig = $1;
-	    # prevent reading twice.
-	    if (!defined($read_kconfigs{$kconfig})) {
-		$read_kconfigs{$kconfig} = 1;
-		read_kconfig($kconfig);
-	    }
-	    next;
-	}
-
-	# configs found
-	if (/^\s*(menu)?config\s+(\S+)\s*$/) {
-	    $state = "NEW";
-	    $config = $2;
-
-	    # Add depends for 'if' nesting
-	    for (my $i = 0; $i < $iflevel; $i++) {
-		if ($i) {
-		    $depends{$config} .= " " . $ifdeps[$i];
-		} else {
-		    $depends{$config} = $ifdeps[$i];
-		}
-		$state = "DEP";
-	    }
-
-	# collect the depends for the config
-	} elsif ($state eq "NEW" && /^\s*depends\s+on\s+(.*)$/) {
-	    $state = "DEP";
-	    $depends{$config} = $1;
-	} elsif ($state eq "DEP" && /^\s*depends\s+on\s+(.*)$/) {
-	    $depends{$config} .= " " . $1;
-	} elsif ($state eq "DEP" && /^\s*def(_(bool|tristate)|ault)\s+(\S.*)$/) {
-	    my $dep = $3;
-	    if ($dep !~ /^\s*(y|m|n)\s*$/) {
-		$dep =~ s/.*\sif\s+//;
-		$depends{$config} .= " " . $dep;
-		dprint "Added default depends $dep to $config\n";
-	    }
-
-	# Get the configs that select this config
-	} elsif ($state ne "NONE" && /^\s*select\s+(\S+)/) {
-	    my $conf = $1;
-	    if (defined($selects{$conf})) {
-		$selects{$conf} .= " " . $config;
-	    } else {
-		$selects{$conf} = $config;
-	    }
-
-	# configs without prompts must be selected
-	} elsif ($state ne "NONE" && /^\s*(tristate\s+\S|prompt\b)/) {
-	    # note if the config has a prompt
-	    $prompts{$config} = 1;
-
-	# Check for if statements
-	} elsif (/^if\s+(.*\S)\s*$/) {
-	    my $deps = $1;
-	    # remove beginning and ending non text
-	    $deps =~ s/^[^a-zA-Z0-9_]*//;
-	    $deps =~ s/[^a-zA-Z0-9_]*$//;
-
-	    my @deps = split /[^a-zA-Z0-9_]+/, $deps;
-
-	    $ifdeps[$iflevel++] = join ':', @deps;
-
-	} elsif (/^endif/) {
-
-	    $iflevel-- if ($iflevel);
-
-	# stop on "help" and keywords that end a menu entry
-	} elsif (/^\s*(---)?help(---)?\s*$/ || /^(comment|choice|menu)\b/) {
-	    $state = "NONE";
-	}
-    }
-    close($kinfile);
-}
-
-if ($kconfig) {
-    read_kconfig($kconfig);
-}
-
-# Makefiles can use variables to define their dependencies
-sub convert_vars {
-    my ($line, %vars) = @_;
-
-    my $process = "";
-
-    while ($line =~ s/^(.*?)(\$\((.*?)\))//) {
-	my $start = $1;
-	my $variable = $2;
-	my $var = $3;
-
-	if (defined($vars{$var})) {
-	    $process .= $start . $vars{$var};
-	} else {
-	    $process .= $start . $variable;
-	}
-    }
-
-    $process .= $line;
-
-    return $process;
-}
-
-# Read all Makefiles to map the configs to the objects
-foreach my $makefile (@makefiles) {
-
-    my $line = "";
-    my %make_vars;
-
-    open(my $infile, '<', $makefile) || die "Can't open $makefile";
-    while (<$infile>) {
-	# if this line ends with a backslash, continue
-	chomp;
-	if (/^(.*)\\$/) {
-	    $line .= $1;
-	    next;
-	}
-
-	$line .= $_;
-	$_ = $line;
-	$line = "";
-
-	my $objs;
-
-	# Convert variables in a line (could define configs)
-	$_ = convert_vars($_, %make_vars);
-
-	# collect objects after obj-$(CONFIG_FOO_BAR)
-	if (/obj-\$\((CONFIG_[^\)]*)\)\s*[+:]?=\s*(.*)/) {
-	    $var = $1;
-	    $objs = $2;
-
-	# check if variables are set
-	} elsif (/^\s*(\S+)\s*[:]?=\s*(.*\S)/) {
-	    $make_vars{$1} = $2;
-	}
-	if (defined($objs)) {
-	    foreach my $obj (split /\s+/,$objs) {
-		$obj =~ s/-/_/g;
-		if ($obj =~ /(.*)\.o$/) {
-		    # Objects may be enabled by more than one config.
-		    # Store configs in an array.
-		    my @arr;
-
-		    if (defined($objects{$1})) {
-			@arr = @{$objects{$1}};
-		    }
-
-		    $arr[$#arr+1] = $var;
-
-		    # The objects have a hash mapping to a reference
-		    # of an array of configs.
-		    $objects{$1} = \@arr;
-		}
-	    }
-	}
-    }
-    close($infile);
-}
-
-my %modules;
-my $linfile;
-
-if (defined($lsmod_file)) {
-    if ( ! -f $lsmod_file) {
-	if ( -f $ENV{'objtree'}."/".$lsmod_file) {
-	    $lsmod_file = $ENV{'objtree'}."/".$lsmod_file;
-	} else {
-		die "$lsmod_file not found";
-	}
-    }
-
-    my $otype = ( -x $lsmod_file) ? '-|' : '<';
-    open($linfile, $otype, $lsmod_file);
-
-} else {
-
-    # see what modules are loaded on this system
-    my $lsmod;
-
-    foreach my $dir ( ("/sbin", "/bin", "/usr/sbin", "/usr/bin") ) {
-	if ( -x "$dir/lsmod" ) {
-	    $lsmod = "$dir/lsmod";
-	    last;
-	}
-}
-    if (!defined($lsmod)) {
-	# try just the path
-	$lsmod = "lsmod";
-    }
-
-    open($linfile, '-|', $lsmod) || die "Can not call lsmod with $lsmod";
-}
-
-while (<$linfile>) {
-	next if (/^Module/);  # Skip the first line.
-	if (/^(\S+)/) {
-		$modules{$1} = 1;
-	}
-}
-close ($linfile);
-
-# add to the configs hash all configs that are needed to enable
-# a loaded module. This is a direct obj-${CONFIG_FOO} += bar.o
-# where we know we need bar.o so we add FOO to the list.
-my %configs;
-foreach my $module (keys(%modules)) {
-    if (defined($objects{$module})) {
-	my @arr = @{$objects{$module}};
-	foreach my $conf (@arr) {
-	    $configs{$conf} = $module;
-	    dprint "$conf added by direct ($module)\n";
-	    if ($debugprint) {
-		my $c=$conf;
-		$c =~ s/^CONFIG_//;
-		if (defined($depends{$c})) {
-		    dprint " deps = $depends{$c}\n";
-		} else {
-		    dprint " no deps\n";
-		}
-	    }
-	}
-    } else {
-	# Most likely, someone has a custom (binary?) module loaded.
-	print STDERR "$module config not found!!\n";
-    }
-}
-
-# Read the current config, and see what is enabled. We want to
-# ignore configs that we would not enable anyway.
-
-my %orig_configs;
-my $valid = "A-Za-z_0-9";
-
-foreach my $line (@config_file) {
-    $_ = $line;
-
-    if (/(CONFIG_[$valid]*)=(m|y)/) {
-	$orig_configs{$1} = $2;
-    }
-}
-
-my $repeat = 1;
-
-my $depconfig;
-
-#
-# Note, we do not care about operands (like: &&, ||, !) we want to add any
-# config that is in the depend list of another config. This script does
-# not enable configs that are not already enabled. If we come across a
-# config A that depends on !B, we can still add B to the list of depends
-# to keep on. If A was on in the original config, B would not have been
-# and B would not be turned on by this script.
-#
-sub parse_config_depends
-{
-    my ($p) = @_;
-
-    while ($p =~ /[$valid]/) {
-
-	if ($p =~ /^[^$valid]*([$valid]+)/) {
-	    my $conf = "CONFIG_" . $1;
-
-	    $p =~ s/^[^$valid]*[$valid]+//;
-
-	    # We only need to process if the depend config is a module
-	    if (!defined($orig_configs{$conf}) || $orig_configs{$conf} eq "y") {
-		next;
-	    }
-
-	    if (!defined($configs{$conf})) {
-		# We must make sure that this config has its
-		# dependencies met.
-		$repeat = 1; # do again
-		dprint "$conf selected by depend $depconfig\n";
-		$configs{$conf} = 1;
-	    }
-	} else {
-	    die "this should never happen";
-	}
-    }
-}
-
-# Select is treated a bit differently than depends. We call this
-# when a config has no prompt and requires another config to be
-# selected. We use to just select all configs that selected this
-# config, but found that that can balloon into enabling hundreds
-# of configs that we do not care about.
-#
-# The idea is we look at all the configs that select it. If one
-# is already in our list of configs to enable, then there's nothing
-# else to do. If there isn't, we pick the first config that was
-# enabled in the orignal config and use that.
-sub parse_config_selects
-{
-    my ($config, $p) = @_;
-
-    my $next_config;
-
-    while ($p =~ /[$valid]/) {
-
-	if ($p =~ /^[^$valid]*([$valid]+)/) {
-	    my $conf = "CONFIG_" . $1;
-
-	    $p =~ s/^[^$valid]*[$valid]+//;
-
-	    # Make sure that this config exists in the current .config file
-	    if (!defined($orig_configs{$conf})) {
-		dprint "$conf not set for $config select\n";
-		next;
-	    }
-
-	    # Check if something other than a module selects this config
-	    if (defined($orig_configs{$conf}) && $orig_configs{$conf} ne "m") {
-		dprint "$conf (non module) selects config, we are good\n";
-		# we are good with this
-		return;
-	    }
-	    if (defined($configs{$conf})) {
-		dprint "$conf selects $config so we are good\n";
-		# A set config selects this config, we are good
-		return;
-	    }
-	    # Set this config to be selected
-	    if (!defined($next_config)) {
-		$next_config = $conf;
-	    }
-	} else {
-	    die "this should never happen";
-	}
-    }
-
-    # If no possible config selected this, then something happened.
-    if (!defined($next_config)) {
-	print STDERR "WARNING: $config is required, but nothing in the\n";
-	print STDERR "  current config selects it.\n";
-	return;
-    }
-
-    # If we are here, then we found no config that is set and
-    # selects this config. Repeat.
-    $repeat = 1;
-    # Make this config need to be selected
-    $configs{$next_config} = 1;
-    dprint "$next_config selected by select $config\n";
-}
-
-my %process_selects;
-
-# loop through all configs, select their dependencies.
-sub loop_depend {
-    $repeat = 1;
-
-    while ($repeat) {
-	$repeat = 0;
-
-      forloop:
-	foreach my $config (keys %configs) {
-
-	    # If this config is not a module, we do not need to process it
-	    if (defined($orig_configs{$config}) && $orig_configs{$config} ne "m") {
-		next forloop;
-	    }
-
-	    $config =~ s/^CONFIG_//;
-	    $depconfig = $config;
-
-	    if (defined($depends{$config})) {
-		# This config has dependencies. Make sure they are also included
-		parse_config_depends $depends{$config};
-	    }
-
-	    # If the config has no prompt, then we need to check if a config
-	    # that is enabled selected it. Or if we need to enable one.
-	    if (!defined($prompts{$config}) && defined($selects{$config})) {
-		$process_selects{$config} = 1;
-	    }
-	}
-    }
-}
-
-sub loop_select {
-
-    foreach my $config (keys %process_selects) {
-	$config =~ s/^CONFIG_//;
-
-	dprint "Process select $config\n";
-
-	# config has no prompt and must be selected.
-	parse_config_selects $config, $selects{$config};
-    }
-}
-
-while ($repeat) {
-    # Get the first set of configs and their dependencies.
-    loop_depend;
-
-    $repeat = 0;
-
-    # Now we need to see if we have to check selects;
-    loop_select;
-}
-
-my %setconfigs;
-
-# Finally, read the .config file and turn off any module enabled that
-# we could not find a reason to keep enabled.
-foreach my $line (@config_file) {
-    $_ = $line;
-
-    if (/CONFIG_IKCONFIG/) {
-	if (/# CONFIG_IKCONFIG is not set/) {
-	    # enable IKCONFIG at least as a module
-	    print "CONFIG_IKCONFIG=m\n";
-	    # don't ask about PROC
-	    print "# CONFIG_IKCONFIG_PROC is not set\n";
-	} else {
-	    print;
-	}
-	next;
-    }
-
-    if (/CONFIG_MODULE_SIG_KEY="(.+)"/) {
-        my $orig_cert = $1;
-        my $default_cert = "certs/signing_key.pem";
-
-        # Check that the logic in this script still matches the one in Kconfig
-        if (!defined($depends{"MODULE_SIG_KEY"}) ||
-            $depends{"MODULE_SIG_KEY"} !~ /"\Q$default_cert\E"/) {
-            print STDERR "WARNING: MODULE_SIG_KEY assertion failure, ",
-                "update needed to ", __FILE__, " line ", __LINE__, "\n";
-            print;
-        } elsif ($orig_cert ne $default_cert && ! -f $orig_cert) {
-            print STDERR "Module signature verification enabled but ",
-                "module signing key \"$orig_cert\" not found. Resetting ",
-                "signing key to default value.\n";
-            print "CONFIG_MODULE_SIG_KEY=\"$default_cert\"\n";
-        } else {
-            print;
-        }
-        next;
-    }
-
-    if (/CONFIG_SYSTEM_TRUSTED_KEYS="(.+)"/) {
-        my $orig_keys = $1;
-
-        if (! -f $orig_keys) {
-            print STDERR "System keyring enabled but keys \"$orig_keys\" ",
-                "not found. Resetting keys to default value.\n";
-            print "CONFIG_SYSTEM_TRUSTED_KEYS=\"\"\n";
-        } else {
-            print;
-        }
-        next;
-    }
-
-    if (/^(CONFIG.*)=(m|y)/) {
-	if (defined($configs{$1})) {
-	    if ($localyesconfig) {
-	        $setconfigs{$1} = 'y';
-		print "$1=y\n";
-		next;
-	    } else {
-	        $setconfigs{$1} = $2;
-	    }
-	} elsif ($2 eq "m") {
-	    print "# $1 is not set\n";
-	    next;
-	}
-    }
-    print;
-}
-
-# Integrity check, make sure all modules that we want enabled do
-# indeed have their configs set.
-loop:
-foreach my $module (keys(%modules)) {
-    if (defined($objects{$module})) {
-	my @arr = @{$objects{$module}};
-	foreach my $conf (@arr) {
-	    if (defined($setconfigs{$conf})) {
-		next loop;
-	    }
-	}
-	print STDERR "module $module did not have configs";
-	foreach my $conf (@arr) {
-	    print STDERR " " , $conf;
-	}
-	print STDERR "\n";
-    }
-}
diff --git a/util/kconfig/symbol.c b/util/kconfig/symbol.c
deleted file mode 100644
index f56eec5ea4..0000000000
--- a/util/kconfig/symbol.c
+++ /dev/null
@@ -1,1331 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org>
- */
-
-#include <ctype.h>
-#include <stdlib.h>
-#include <string.h>
-#include <regex.h>
-#include <sys/utsname.h>
-
-#include "lkc.h"
-
-struct symbol symbol_yes = {
-	.name = "y",
-	.curr = { "y", yes },
-	.flags = SYMBOL_CONST|SYMBOL_VALID,
-}, symbol_mod = {
-	.name = "m",
-	.curr = { "m", mod },
-	.flags = SYMBOL_CONST|SYMBOL_VALID,
-}, symbol_no = {
-	.name = "n",
-	.curr = { "n", no },
-	.flags = SYMBOL_CONST|SYMBOL_VALID,
-}, symbol_empty = {
-	.name = "",
-	.curr = { "", no },
-	.flags = SYMBOL_VALID,
-};
-
-struct symbol *sym_defconfig_list;
-struct symbol *modules_sym;
-tristate modules_val;
-
-enum symbol_type sym_get_type(struct symbol *sym)
-{
-	enum symbol_type type = sym->type;
-
-	if (type == S_TRISTATE) {
-		if (sym_is_choice_value(sym) && sym->visible == yes)
-			type = S_BOOLEAN;
-		else if (modules_val == no)
-			type = S_BOOLEAN;
-	}
-	return type;
-}
-
-const char *sym_type_name(enum symbol_type type)
-{
-	switch (type) {
-	case S_BOOLEAN:
-		return "bool";
-	case S_TRISTATE:
-		return "tristate";
-	case S_INT:
-		return "integer";
-	case S_HEX:
-		return "hex";
-	case S_STRING:
-		return "string";
-	case S_UNKNOWN:
-		return "unknown";
-	}
-	return "???";
-}
-
-struct property *sym_get_choice_prop(struct symbol *sym)
-{
-	struct property *prop;
-
-	for_all_choices(sym, prop)
-		return prop;
-	return NULL;
-}
-
-static struct property *sym_get_default_prop(struct symbol *sym)
-{
-	struct property *prop;
-
-	for_all_defaults(sym, prop) {
-		prop->visible.tri = expr_calc_value(prop->visible.expr);
-		if (prop->visible.tri != no)
-			return prop;
-	}
-	return NULL;
-}
-
-struct property *sym_get_range_prop(struct symbol *sym)
-{
-	struct property *prop;
-
-	for_all_properties(sym, prop, P_RANGE) {
-		prop->visible.tri = expr_calc_value(prop->visible.expr);
-		if (prop->visible.tri != no)
-			return prop;
-	}
-	return NULL;
-}
-
-static long long sym_get_range_val(struct symbol *sym, int base)
-{
-	sym_calc_value(sym);
-	switch (sym->type) {
-	case S_INT:
-		base = 10;
-		break;
-	case S_HEX:
-		base = 16;
-		break;
-	default:
-		break;
-	}
-	return strtoll(sym->curr.val, NULL, base);
-}
-
-static void sym_validate_range(struct symbol *sym)
-{
-	struct property *prop;
-	int base;
-	long long val, val2;
-	char str[64];
-
-	switch (sym->type) {
-	case S_INT:
-		base = 10;
-		break;
-	case S_HEX:
-		base = 16;
-		break;
-	default:
-		return;
-	}
-	prop = sym_get_range_prop(sym);
-	if (!prop)
-		return;
-	val = strtoll(sym->curr.val, NULL, base);
-	val2 = sym_get_range_val(prop->expr->left.sym, base);
-	if (val >= val2) {
-		val2 = sym_get_range_val(prop->expr->right.sym, base);
-		if (val <= val2)
-			return;
-	}
-	if (sym->type == S_INT)
-		sprintf(str, "%lld", val2);
-	else
-		sprintf(str, "0x%llx", val2);
-	sym->curr.val = xstrdup(str);
-}
-
-static void sym_set_changed(struct symbol *sym)
-{
-	struct property *prop;
-
-	sym->flags |= SYMBOL_CHANGED;
-	for (prop = sym->prop; prop; prop = prop->next) {
-		if (prop->menu)
-			prop->menu->flags |= MENU_CHANGED;
-	}
-}
-
-static void sym_set_all_changed(void)
-{
-	struct symbol *sym;
-	int i;
-
-	for_all_symbols(i, sym)
-		sym_set_changed(sym);
-}
-
-static void sym_calc_visibility(struct symbol *sym)
-{
-	struct property *prop;
-	struct symbol *choice_sym = NULL;
-	tristate tri;
-
-	/* any prompt visible? */
-	tri = no;
-
-	if (sym_is_choice_value(sym))
-		choice_sym = prop_get_symbol(sym_get_choice_prop(sym));
-
-	for_all_prompts(sym, prop) {
-		prop->visible.tri = expr_calc_value(prop->visible.expr);
-		/*
-		 * Tristate choice_values with visibility 'mod' are
-		 * not visible if the corresponding choice's value is
-		 * 'yes'.
-		 */
-		if (choice_sym && sym->type == S_TRISTATE &&
-		    prop->visible.tri == mod && choice_sym->curr.tri == yes)
-			prop->visible.tri = no;
-
-		tri = EXPR_OR(tri, prop->visible.tri);
-	}
-	if (tri == mod && (sym->type != S_TRISTATE || modules_val == no))
-		tri = yes;
-	if (sym->visible != tri) {
-		sym->visible = tri;
-		sym_set_changed(sym);
-	}
-	if (sym_is_choice_value(sym))
-		return;
-	/* defaulting to "yes" if no explicit "depends on" are given */
-	tri = yes;
-	if (sym->dir_dep.expr)
-		tri = expr_calc_value(sym->dir_dep.expr);
-	if (tri == mod && sym_get_type(sym) == S_BOOLEAN)
-		tri = yes;
-	if (sym->dir_dep.tri != tri) {
-		sym->dir_dep.tri = tri;
-		sym_set_changed(sym);
-	}
-	tri = no;
-	if (sym->rev_dep.expr)
-		tri = expr_calc_value(sym->rev_dep.expr);
-	if (tri == mod && sym_get_type(sym) == S_BOOLEAN)
-		tri = yes;
-	if (sym->rev_dep.tri != tri) {
-		sym->rev_dep.tri = tri;
-		sym_set_changed(sym);
-	}
-	tri = no;
-	if (sym->implied.expr && sym->dir_dep.tri != no)
-		tri = expr_calc_value(sym->implied.expr);
-	if (tri == mod && sym_get_type(sym) == S_BOOLEAN)
-		tri = yes;
-	if (sym->implied.tri != tri) {
-		sym->implied.tri = tri;
-		sym_set_changed(sym);
-	}
-}
-
-/*
- * Find the default symbol for a choice.
- * First try the default values for the choice symbol
- * Next locate the first visible choice value
- * Return NULL if none was found
- */
-struct symbol *sym_choice_default(struct symbol *sym)
-{
-	struct symbol *def_sym;
-	struct property *prop;
-	struct expr *e;
-
-	/* any of the defaults visible? */
-	for_all_defaults(sym, prop) {
-		prop->visible.tri = expr_calc_value(prop->visible.expr);
-		if (prop->visible.tri == no)
-			continue;
-		def_sym = prop_get_symbol(prop);
-		if (def_sym->visible != no)
-			return def_sym;
-	}
-
-	/* just get the first visible value */
-	prop = sym_get_choice_prop(sym);
-	expr_list_for_each_sym(prop->expr, e, def_sym)
-		if (def_sym->visible != no)
-			return def_sym;
-
-	/* failed to locate any defaults */
-	return NULL;
-}
-
-static struct symbol *sym_calc_choice(struct symbol *sym)
-{
-	struct symbol *def_sym;
-	struct property *prop;
-	struct expr *e;
-	int flags;
-
-	/* first calculate all choice values' visibilities */
-	flags = sym->flags;
-	prop = sym_get_choice_prop(sym);
-	expr_list_for_each_sym(prop->expr, e, def_sym) {
-		sym_calc_visibility(def_sym);
-		if (def_sym->visible != no)
-			flags &= def_sym->flags;
-	}
-
-	sym->flags &= flags | ~SYMBOL_DEF_USER;
-
-	/* is the user choice visible? */
-	def_sym = sym->def[S_DEF_USER].val;
-	if (def_sym && def_sym->visible != no)
-		return def_sym;
-
-	def_sym = sym_choice_default(sym);
-
-	if (def_sym == NULL)
-		/* no choice? reset tristate value */
-		sym->curr.tri = no;
-
-	return def_sym;
-}
-
-static void sym_warn_unmet_dep(struct symbol *sym)
-{
-	struct gstr gs = str_new();
-
-	str_printf(&gs,
-		   "\nWARNING: unmet direct dependencies detected for %s\n",
-		   sym->name);
-	str_printf(&gs,
-		   "  Depends on [%c]: ",
-		   sym->dir_dep.tri == mod ? 'm' : 'n');
-	expr_gstr_print(sym->dir_dep.expr, &gs);
-	str_printf(&gs, "\n");
-
-	expr_gstr_print_revdep(sym->rev_dep.expr, &gs, yes,
-			       "  Selected by [y]:\n");
-	expr_gstr_print_revdep(sym->rev_dep.expr, &gs, mod,
-			       "  Selected by [m]:\n");
-
-	fputs(str_get(&gs), stderr);
-}
-
-void sym_calc_value(struct symbol *sym)
-{
-	struct symbol_value newval, oldval;
-	struct property *prop;
-	struct expr *e;
-
-	if (!sym)
-		return;
-
-	if (sym->flags & SYMBOL_VALID)
-		return;
-
-	if (sym_is_choice_value(sym) &&
-	    sym->flags & SYMBOL_NEED_SET_CHOICE_VALUES) {
-		sym->flags &= ~SYMBOL_NEED_SET_CHOICE_VALUES;
-		prop = sym_get_choice_prop(sym);
-		sym_calc_value(prop_get_symbol(prop));
-	}
-
-	sym->flags |= SYMBOL_VALID;
-
-	oldval = sym->curr;
-
-	switch (sym->type) {
-	case S_INT:
-	case S_HEX:
-	case S_STRING:
-		newval = symbol_empty.curr;
-		break;
-	case S_BOOLEAN:
-	case S_TRISTATE:
-		newval = symbol_no.curr;
-		break;
-	default:
-		sym->curr.val = sym->name;
-		sym->curr.tri = no;
-		return;
-	}
-	sym->flags &= ~SYMBOL_WRITE;
-
-	sym_calc_visibility(sym);
-
-	if (sym->visible != no)
-		sym->flags |= SYMBOL_WRITE;
-
-	/* set default if recursively called */
-	sym->curr = newval;
-
-	switch (sym_get_type(sym)) {
-	case S_BOOLEAN:
-	case S_TRISTATE:
-		if (sym_is_choice_value(sym) && sym->visible == yes) {
-			prop = sym_get_choice_prop(sym);
-			newval.tri = (prop_get_symbol(prop)->curr.val == sym) ? yes : no;
-		} else {
-			if (sym->visible != no) {
-				/* if the symbol is visible use the user value
-				 * if available, otherwise try the default value
-				 */
-				if (sym_has_value(sym)) {
-					newval.tri = EXPR_AND(sym->def[S_DEF_USER].tri,
-							      sym->visible);
-					goto calc_newval;
-				}
-			}
-			if (sym->rev_dep.tri != no)
-				sym->flags |= SYMBOL_WRITE;
-			if (!sym_is_choice(sym)) {
-				prop = sym_get_default_prop(sym);
-				if (prop) {
-					newval.tri = EXPR_AND(expr_calc_value(prop->expr),
-							      prop->visible.tri);
-					if (newval.tri != no)
-						sym->flags |= SYMBOL_WRITE;
-				}
-				if (sym->implied.tri != no) {
-					sym->flags |= SYMBOL_WRITE;
-					newval.tri = EXPR_OR(newval.tri, sym->implied.tri);
-				}
-			}
-		calc_newval:
-			if (sym->dir_dep.tri < sym->rev_dep.tri)
-				sym_warn_unmet_dep(sym);
-			newval.tri = EXPR_OR(newval.tri, sym->rev_dep.tri);
-		}
-		if (newval.tri == mod &&
-		    (sym_get_type(sym) == S_BOOLEAN || sym->implied.tri == yes))
-			newval.tri = yes;
-		break;
-	case S_STRING:
-	case S_HEX:
-	case S_INT:
-		if (sym->visible != no && sym_has_value(sym)) {
-			newval.val = sym->def[S_DEF_USER].val;
-			break;
-		}
-		prop = sym_get_default_prop(sym);
-		if (prop) {
-			struct symbol *ds = prop_get_symbol(prop);
-			if (ds) {
-				sym->flags |= SYMBOL_WRITE;
-				sym_calc_value(ds);
-				newval.val = ds->curr.val;
-			}
-		}
-		break;
-	default:
-		;
-	}
-
-	sym->curr = newval;
-	if (sym_is_choice(sym) && newval.tri == yes)
-		sym->curr.val = sym_calc_choice(sym);
-	sym_validate_range(sym);
-
-	if (memcmp(&oldval, &sym->curr, sizeof(oldval))) {
-		sym_set_changed(sym);
-		if (modules_sym == sym) {
-			sym_set_all_changed();
-			modules_val = modules_sym->curr.tri;
-		}
-	}
-
-	if (sym_is_choice(sym)) {
-		struct symbol *choice_sym;
-
-		prop = sym_get_choice_prop(sym);
-		expr_list_for_each_sym(prop->expr, e, choice_sym) {
-			if ((sym->flags & SYMBOL_WRITE) &&
-			    choice_sym->visible != no)
-				choice_sym->flags |= SYMBOL_WRITE;
-			if (sym->flags & SYMBOL_CHANGED)
-				sym_set_changed(choice_sym);
-		}
-	}
-
-	if (sym->flags & SYMBOL_NO_WRITE)
-		sym->flags &= ~SYMBOL_WRITE;
-
-	if (sym->flags & SYMBOL_NEED_SET_CHOICE_VALUES)
-		set_all_choice_values(sym);
-}
-
-void sym_clear_all_valid(void)
-{
-	struct symbol *sym;
-	int i;
-
-	for_all_symbols(i, sym)
-		sym->flags &= ~SYMBOL_VALID;
-	sym_add_change_count(1);
-	sym_calc_value(modules_sym);
-}
-
-bool sym_tristate_within_range(struct symbol *sym, tristate val)
-{
-	int type = sym_get_type(sym);
-
-	if (sym->visible == no)
-		return false;
-
-	if (type != S_BOOLEAN && type != S_TRISTATE)
-		return false;
-
-	if (type == S_BOOLEAN && val == mod)
-		return false;
-	if (sym->visible <= sym->rev_dep.tri)
-		return false;
-	if (sym->implied.tri == yes && val == mod)
-		return false;
-	if (sym_is_choice_value(sym) && sym->visible == yes)
-		return val == yes;
-	return val >= sym->rev_dep.tri && val <= sym->visible;
-}
-
-bool sym_set_tristate_value(struct symbol *sym, tristate val)
-{
-	tristate oldval = sym_get_tristate_value(sym);
-
-	if (oldval != val && !sym_tristate_within_range(sym, val))
-		return false;
-
-	if (!(sym->flags & SYMBOL_DEF_USER)) {
-		sym->flags |= SYMBOL_DEF_USER;
-		sym_set_changed(sym);
-	}
-	/*
-	 * setting a choice value also resets the new flag of the choice
-	 * symbol and all other choice values.
-	 */
-	if (sym_is_choice_value(sym) && val == yes) {
-		struct symbol *cs = prop_get_symbol(sym_get_choice_prop(sym));
-		struct property *prop;
-		struct expr *e;
-
-		cs->def[S_DEF_USER].val = sym;
-		cs->flags |= SYMBOL_DEF_USER;
-		prop = sym_get_choice_prop(cs);
-		for (e = prop->expr; e; e = e->left.expr) {
-			if (e->right.sym->visible != no)
-				e->right.sym->flags |= SYMBOL_DEF_USER;
-		}
-	}
-
-	sym->def[S_DEF_USER].tri = val;
-	if (oldval != val)
-		sym_clear_all_valid();
-
-	return true;
-}
-
-tristate sym_toggle_tristate_value(struct symbol *sym)
-{
-	tristate oldval, newval;
-
-	oldval = newval = sym_get_tristate_value(sym);
-	do {
-		switch (newval) {
-		case no:
-			newval = mod;
-			break;
-		case mod:
-			newval = yes;
-			break;
-		case yes:
-			newval = no;
-			break;
-		}
-		if (sym_set_tristate_value(sym, newval))
-			break;
-	} while (oldval != newval);
-	return newval;
-}
-
-bool sym_string_valid(struct symbol *sym, const char *str)
-{
-	signed char ch;
-
-	switch (sym->type) {
-	case S_STRING:
-		return true;
-	case S_INT:
-		ch = *str++;
-		if (ch == '-')
-			ch = *str++;
-		if (!isdigit(ch))
-			return false;
-		if (ch == '0' && *str != 0)
-			return false;
-		while ((ch = *str++)) {
-			if (!isdigit(ch))
-				return false;
-		}
-		return true;
-	case S_HEX:
-		if (str[0] == '0' && (str[1] == 'x' || str[1] == 'X'))
-			str += 2;
-		ch = *str++;
-		do {
-			if (!isxdigit(ch))
-				return false;
-		} while ((ch = *str++));
-		return true;
-	case S_BOOLEAN:
-	case S_TRISTATE:
-		switch (str[0]) {
-		case 'y': case 'Y':
-		case 'm': case 'M':
-		case 'n': case 'N':
-			return true;
-		}
-		return false;
-	default:
-		return false;
-	}
-}
-
-bool sym_string_within_range(struct symbol *sym, const char *str)
-{
-	struct property *prop;
-	long long val;
-
-	switch (sym->type) {
-	case S_STRING:
-		return sym_string_valid(sym, str);
-	case S_INT:
-		if (!sym_string_valid(sym, str))
-			return false;
-		prop = sym_get_range_prop(sym);
-		if (!prop)
-			return true;
-		val = strtoll(str, NULL, 10);
-		return val >= sym_get_range_val(prop->expr->left.sym, 10) &&
-		       val <= sym_get_range_val(prop->expr->right.sym, 10);
-	case S_HEX:
-		if (!sym_string_valid(sym, str))
-			return false;
-		prop = sym_get_range_prop(sym);
-		if (!prop)
-			return true;
-		val = strtoll(str, NULL, 16);
-		return val >= sym_get_range_val(prop->expr->left.sym, 16) &&
-		       val <= sym_get_range_val(prop->expr->right.sym, 16);
-	case S_BOOLEAN:
-	case S_TRISTATE:
-		switch (str[0]) {
-		case 'y': case 'Y':
-			return sym_tristate_within_range(sym, yes);
-		case 'm': case 'M':
-			return sym_tristate_within_range(sym, mod);
-		case 'n': case 'N':
-			return sym_tristate_within_range(sym, no);
-		}
-		return false;
-	default:
-		return false;
-	}
-}
-
-bool sym_set_string_value(struct symbol *sym, const char *newval)
-{
-	const char *oldval;
-	char *val;
-	int size;
-
-	switch (sym->type) {
-	case S_BOOLEAN:
-	case S_TRISTATE:
-		switch (newval[0]) {
-		case 'y': case 'Y':
-			return sym_set_tristate_value(sym, yes);
-		case 'm': case 'M':
-			return sym_set_tristate_value(sym, mod);
-		case 'n': case 'N':
-			return sym_set_tristate_value(sym, no);
-		}
-		return false;
-	default:
-		;
-	}
-
-	if (!sym_string_within_range(sym, newval))
-		return false;
-
-	if (!(sym->flags & SYMBOL_DEF_USER)) {
-		sym->flags |= SYMBOL_DEF_USER;
-		sym_set_changed(sym);
-	}
-
-	oldval = sym->def[S_DEF_USER].val;
-	size = strlen(newval) + 1;
-	if (sym->type == S_HEX && (newval[0] != '0' || (newval[1] != 'x' && newval[1] != 'X'))) {
-		size += 2;
-		sym->def[S_DEF_USER].val = val = xmalloc(size);
-		*val++ = '0';
-		*val++ = 'x';
-	} else if (!oldval || strcmp(oldval, newval))
-		sym->def[S_DEF_USER].val = val = xmalloc(size);
-	else
-		return true;
-
-	strcpy(val, newval);
-	free((void *)oldval);
-	sym_clear_all_valid();
-
-	return true;
-}
-
-/*
- * Find the default value associated to a symbol.
- * For tristate symbol handle the modules=n case
- * in which case "m" becomes "y".
- * If the symbol does not have any default then fallback
- * to the fixed default values.
- */
-const char *sym_get_string_default(struct symbol *sym)
-{
-	struct property *prop;
-	struct symbol *ds;
-	const char *str;
-	tristate val;
-
-	sym_calc_visibility(sym);
-	sym_calc_value(modules_sym);
-	val = symbol_no.curr.tri;
-	str = symbol_empty.curr.val;
-
-	/* If symbol has a default value look it up */
-	prop = sym_get_default_prop(sym);
-	if (prop != NULL) {
-		switch (sym->type) {
-		case S_BOOLEAN:
-		case S_TRISTATE:
-			/* The visibility may limit the value from yes => mod */
-			val = EXPR_AND(expr_calc_value(prop->expr), prop->visible.tri);
-			break;
-		default:
-			/*
-			 * The following fails to handle the situation
-			 * where a default value is further limited by
-			 * the valid range.
-			 */
-			ds = prop_get_symbol(prop);
-			if (ds != NULL) {
-				sym_calc_value(ds);
-				str = (const char *)ds->curr.val;
-			}
-		}
-	}
-
-	/* Handle select statements */
-	val = EXPR_OR(val, sym->rev_dep.tri);
-
-	/* transpose mod to yes if modules are not enabled */
-	if (val == mod)
-		if (!sym_is_choice_value(sym) && modules_sym->curr.tri == no)
-			val = yes;
-
-	/* transpose mod to yes if type is bool */
-	if (sym->type == S_BOOLEAN && val == mod)
-		val = yes;
-
-	/* adjust the default value if this symbol is implied by another */
-	if (val < sym->implied.tri)
-		val = sym->implied.tri;
-
-	switch (sym->type) {
-	case S_BOOLEAN:
-	case S_TRISTATE:
-		switch (val) {
-		case no: return "n";
-		case mod: return "m";
-		case yes: return "y";
-		}
-	case S_INT:
-	case S_HEX:
-		return str;
-	case S_STRING:
-		return str;
-	case S_UNKNOWN:
-		break;
-	}
-	return "";
-}
-
-const char *sym_get_string_value(struct symbol *sym)
-{
-	tristate val;
-
-	switch (sym->type) {
-	case S_BOOLEAN:
-	case S_TRISTATE:
-		val = sym_get_tristate_value(sym);
-		switch (val) {
-		case no:
-			return "n";
-		case mod:
-			sym_calc_value(modules_sym);
-			return (modules_sym->curr.tri == no) ? "n" : "m";
-		case yes:
-			return "y";
-		}
-		break;
-	default:
-		;
-	}
-	return (const char *)sym->curr.val;
-}
-
-bool sym_is_changeable(struct symbol *sym)
-{
-	return sym->visible > sym->rev_dep.tri;
-}
-
-static unsigned strhash(const char *s)
-{
-	/* fnv32 hash */
-	unsigned hash = 2166136261U;
-	for (; *s; s++)
-		hash = (hash ^ *s) * 0x01000193;
-	return hash;
-}
-
-struct symbol *sym_lookup(const char *name, int flags)
-{
-	struct symbol *symbol;
-	char *new_name;
-	int hash;
-
-	if (name) {
-		if (name[0] && !name[1]) {
-			switch (name[0]) {
-			case 'y': return &symbol_yes;
-			case 'm': return &symbol_mod;
-			case 'n': return &symbol_no;
-			}
-		}
-		hash = strhash(name) % SYMBOL_HASHSIZE;
-
-		for (symbol = symbol_hash[hash]; symbol; symbol = symbol->next) {
-			if (symbol->name &&
-			    !strcmp(symbol->name, name) &&
-			    (flags ? symbol->flags & flags
-				   : !(symbol->flags & (SYMBOL_CONST|SYMBOL_CHOICE))))
-				return symbol;
-		}
-		new_name = xstrdup(name);
-	} else {
-		new_name = NULL;
-		hash = 0;
-	}
-
-	symbol = xmalloc(sizeof(*symbol));
-	memset(symbol, 0, sizeof(*symbol));
-	symbol->name = new_name;
-	symbol->type = S_UNKNOWN;
-	symbol->flags |= flags;
-
-	symbol->next = symbol_hash[hash];
-	symbol_hash[hash] = symbol;
-
-	return symbol;
-}
-
-struct symbol *sym_find(const char *name)
-{
-	struct symbol *symbol = NULL;
-	int hash = 0;
-
-	if (!name)
-		return NULL;
-
-	if (name[0] && !name[1]) {
-		switch (name[0]) {
-		case 'y': return &symbol_yes;
-		case 'm': return &symbol_mod;
-		case 'n': return &symbol_no;
-		}
-	}
-	hash = strhash(name) % SYMBOL_HASHSIZE;
-
-	for (symbol = symbol_hash[hash]; symbol; symbol = symbol->next) {
-		if (symbol->name &&
-		    !strcmp(symbol->name, name) &&
-		    !(symbol->flags & SYMBOL_CONST))
-				break;
-	}
-
-	return symbol;
-}
-
-const char *sym_escape_string_value(const char *in)
-{
-	const char *p;
-	size_t reslen;
-	char *res;
-	size_t l;
-
-	reslen = strlen(in) + strlen("\"\"") + 1;
-
-	p = in;
-	for (;;) {
-		l = strcspn(p, "\"\\");
-		p += l;
-
-		if (p[0] == '\0')
-			break;
-
-		reslen++;
-		p++;
-	}
-
-	res = xmalloc(reslen);
-	res[0] = '\0';
-
-	strcat(res, "\"");
-
-	p = in;
-	for (;;) {
-		l = strcspn(p, "\"\\");
-		strncat(res, p, l);
-		p += l;
-
-		if (p[0] == '\0')
-			break;
-
-		strcat(res, "\\");
-		strncat(res, p++, 1);
-	}
-
-	strcat(res, "\"");
-	return res;
-}
-
-struct sym_match {
-	struct symbol	*sym;
-	off_t		so, eo;
-};
-
-/* Compare matched symbols as thus:
- * - first, symbols that match exactly
- * - then, alphabetical sort
- */
-static int sym_rel_comp(const void *sym1, const void *sym2)
-{
-	const struct sym_match *s1 = sym1;
-	const struct sym_match *s2 = sym2;
-	int exact1, exact2;
-
-	/* Exact match:
-	 * - if matched length on symbol s1 is the length of that symbol,
-	 *   then this symbol should come first;
-	 * - if matched length on symbol s2 is the length of that symbol,
-	 *   then this symbol should come first.
-	 * Note: since the search can be a regexp, both symbols may match
-	 * exactly; if this is the case, we can't decide which comes first,
-	 * and we fallback to sorting alphabetically.
-	 */
-	exact1 = (s1->eo - s1->so) == strlen(s1->sym->name);
-	exact2 = (s2->eo - s2->so) == strlen(s2->sym->name);
-	if (exact1 && !exact2)
-		return -1;
-	if (!exact1 && exact2)
-		return 1;
-
-	/* As a fallback, sort symbols alphabetically */
-	return strcmp(s1->sym->name, s2->sym->name);
-}
-
-struct symbol **sym_re_search(const char *pattern)
-{
-	struct symbol *sym, **sym_arr = NULL;
-	struct sym_match *sym_match_arr = NULL;
-	int i, cnt, size;
-	regex_t re;
-	regmatch_t match[1];
-
-	cnt = size = 0;
-	/* Skip if empty */
-	if (strlen(pattern) == 0)
-		return NULL;
-	if (regcomp(&re, pattern, REG_EXTENDED|REG_ICASE))
-		return NULL;
-
-	for_all_symbols(i, sym) {
-		if (sym->flags & SYMBOL_CONST || !sym->name)
-			continue;
-		if (regexec(&re, sym->name, 1, match, 0))
-			continue;
-		if (cnt >= size) {
-			void *tmp;
-			size += 16;
-			tmp = realloc(sym_match_arr, size * sizeof(struct sym_match));
-			if (!tmp)
-				goto sym_re_search_free;
-			sym_match_arr = tmp;
-		}
-		sym_calc_value(sym);
-		/* As regexec returned 0, we know we have a match, so
-		 * we can use match[0].rm_[se]o without further checks
-		 */
-		sym_match_arr[cnt].so = match[0].rm_so;
-		sym_match_arr[cnt].eo = match[0].rm_eo;
-		sym_match_arr[cnt++].sym = sym;
-	}
-	if (sym_match_arr) {
-		qsort(sym_match_arr, cnt, sizeof(struct sym_match), sym_rel_comp);
-		sym_arr = malloc((cnt+1) * sizeof(struct symbol *));
-		if (!sym_arr)
-			goto sym_re_search_free;
-		for (i = 0; i < cnt; i++)
-			sym_arr[i] = sym_match_arr[i].sym;
-		sym_arr[cnt] = NULL;
-	}
-sym_re_search_free:
-	/* sym_match_arr can be NULL if no match, but free(NULL) is OK */
-	free(sym_match_arr);
-	regfree(&re);
-
-	return sym_arr;
-}
-
-/*
- * When we check for recursive dependencies we use a stack to save
- * current state so we can print out relevant info to user.
- * The entries are located on the call stack so no need to free memory.
- * Note insert() remove() must always match to properly clear the stack.
- */
-static struct dep_stack {
-	struct dep_stack *prev, *next;
-	struct symbol *sym;
-	struct property *prop;
-	struct expr **expr;
-} *check_top;
-
-static void dep_stack_insert(struct dep_stack *stack, struct symbol *sym)
-{
-	memset(stack, 0, sizeof(*stack));
-	if (check_top)
-		check_top->next = stack;
-	stack->prev = check_top;
-	stack->sym = sym;
-	check_top = stack;
-}
-
-static void dep_stack_remove(void)
-{
-	check_top = check_top->prev;
-	if (check_top)
-		check_top->next = NULL;
-}
-
-/*
- * Called when we have detected a recursive dependency.
- * check_top point to the top of the stact so we use
- * the ->prev pointer to locate the bottom of the stack.
- */
-static void sym_check_print_recursive(struct symbol *last_sym)
-{
-	struct dep_stack *stack;
-	struct symbol *sym, *next_sym;
-	struct menu *menu = NULL;
-	struct property *prop;
-	struct dep_stack cv_stack;
-
-	if (sym_is_choice_value(last_sym)) {
-		dep_stack_insert(&cv_stack, last_sym);
-		last_sym = prop_get_symbol(sym_get_choice_prop(last_sym));
-	}
-
-	for (stack = check_top; stack != NULL; stack = stack->prev)
-		if (stack->sym == last_sym)
-			break;
-	if (!stack) {
-		fprintf(stderr, "unexpected recursive dependency error\n");
-		return;
-	}
-
-	for (; stack; stack = stack->next) {
-		sym = stack->sym;
-		next_sym = stack->next ? stack->next->sym : last_sym;
-		prop = stack->prop;
-		if (prop == NULL)
-			prop = stack->sym->prop;
-
-		/* for choice values find the menu entry (used below) */
-		if (sym_is_choice(sym) || sym_is_choice_value(sym)) {
-			for (prop = sym->prop; prop; prop = prop->next) {
-				menu = prop->menu;
-				if (prop->menu)
-					break;
-			}
-		}
-		if (stack->sym == last_sym)
-			fprintf(stderr, "%s:%d:error: recursive dependency detected!\n",
-				prop->file->name, prop->lineno);
-
-		if (sym_is_choice(sym)) {
-			fprintf(stderr, "%s:%d:\tchoice %s contains symbol %s\n",
-				menu->file->name, menu->lineno,
-				sym->name ? sym->name : "<choice>",
-				next_sym->name ? next_sym->name : "<choice>");
-		} else if (sym_is_choice_value(sym)) {
-			fprintf(stderr, "%s:%d:\tsymbol %s is part of choice %s\n",
-				menu->file->name, menu->lineno,
-				sym->name ? sym->name : "<choice>",
-				next_sym->name ? next_sym->name : "<choice>");
-		} else if (stack->expr == &sym->dir_dep.expr) {
-			fprintf(stderr, "%s:%d:\tsymbol %s depends on %s\n",
-				prop->file->name, prop->lineno,
-				sym->name ? sym->name : "<choice>",
-				next_sym->name ? next_sym->name : "<choice>");
-		} else if (stack->expr == &sym->rev_dep.expr) {
-			fprintf(stderr, "%s:%d:\tsymbol %s is selected by %s\n",
-				prop->file->name, prop->lineno,
-				sym->name ? sym->name : "<choice>",
-				next_sym->name ? next_sym->name : "<choice>");
-		} else if (stack->expr == &sym->implied.expr) {
-			fprintf(stderr, "%s:%d:\tsymbol %s is implied by %s\n",
-				prop->file->name, prop->lineno,
-				sym->name ? sym->name : "<choice>",
-				next_sym->name ? next_sym->name : "<choice>");
-		} else if (stack->expr) {
-			fprintf(stderr, "%s:%d:\tsymbol %s %s value contains %s\n",
-				prop->file->name, prop->lineno,
-				sym->name ? sym->name : "<choice>",
-				prop_get_type_name(prop->type),
-				next_sym->name ? next_sym->name : "<choice>");
-		} else {
-			fprintf(stderr, "%s:%d:\tsymbol %s %s is visible depending on %s\n",
-				prop->file->name, prop->lineno,
-				sym->name ? sym->name : "<choice>",
-				prop_get_type_name(prop->type),
-				next_sym->name ? next_sym->name : "<choice>");
-		}
-	}
-
-	fprintf(stderr,
-		"For a resolution refer to Documentation/kbuild/kconfig-language.rst\n"
-		"subsection \"Kconfig recursive dependency limitations\"\n"
-		"\n");
-
-	if (check_top == &cv_stack)
-		dep_stack_remove();
-}
-
-static struct symbol *sym_check_expr_deps(struct expr *e)
-{
-	struct symbol *sym;
-
-	if (!e)
-		return NULL;
-	switch (e->type) {
-	case E_OR:
-	case E_AND:
-		sym = sym_check_expr_deps(e->left.expr);
-		if (sym)
-			return sym;
-		return sym_check_expr_deps(e->right.expr);
-	case E_NOT:
-		return sym_check_expr_deps(e->left.expr);
-	case E_EQUAL:
-	case E_GEQ:
-	case E_GTH:
-	case E_LEQ:
-	case E_LTH:
-	case E_UNEQUAL:
-		sym = sym_check_deps(e->left.sym);
-		if (sym)
-			return sym;
-		return sym_check_deps(e->right.sym);
-	case E_SYMBOL:
-		return sym_check_deps(e->left.sym);
-	default:
-		break;
-	}
-	fprintf(stderr, "Oops! How to check %d?\n", e->type);
-	return NULL;
-}
-
-/* return NULL when dependencies are OK */
-static struct symbol *sym_check_sym_deps(struct symbol *sym)
-{
-	struct symbol *sym2;
-	struct property *prop;
-	struct dep_stack stack;
-
-	dep_stack_insert(&stack, sym);
-
-	stack.expr = &sym->dir_dep.expr;
-	sym2 = sym_check_expr_deps(sym->dir_dep.expr);
-	if (sym2)
-		goto out;
-
-	stack.expr = &sym->rev_dep.expr;
-	sym2 = sym_check_expr_deps(sym->rev_dep.expr);
-	if (sym2)
-		goto out;
-
-	stack.expr = &sym->implied.expr;
-	sym2 = sym_check_expr_deps(sym->implied.expr);
-	if (sym2)
-		goto out;
-
-	stack.expr = NULL;
-
-	for (prop = sym->prop; prop; prop = prop->next) {
-		if (prop->type == P_CHOICE || prop->type == P_SELECT ||
-		    prop->type == P_IMPLY)
-			continue;
-		stack.prop = prop;
-		sym2 = sym_check_expr_deps(prop->visible.expr);
-		if (sym2)
-			break;
-		if (prop->type != P_DEFAULT || sym_is_choice(sym))
-			continue;
-		stack.expr = &prop->expr;
-		sym2 = sym_check_expr_deps(prop->expr);
-		if (sym2)
-			break;
-		stack.expr = NULL;
-	}
-
-out:
-	dep_stack_remove();
-
-	return sym2;
-}
-
-static struct symbol *sym_check_choice_deps(struct symbol *choice)
-{
-	struct symbol *sym, *sym2;
-	struct property *prop;
-	struct expr *e;
-	struct dep_stack stack;
-
-	dep_stack_insert(&stack, choice);
-
-	prop = sym_get_choice_prop(choice);
-	expr_list_for_each_sym(prop->expr, e, sym)
-		sym->flags |= (SYMBOL_CHECK | SYMBOL_CHECKED);
-
-	choice->flags |= (SYMBOL_CHECK | SYMBOL_CHECKED);
-	sym2 = sym_check_sym_deps(choice);
-	choice->flags &= ~SYMBOL_CHECK;
-	if (sym2)
-		goto out;
-
-	expr_list_for_each_sym(prop->expr, e, sym) {
-		sym2 = sym_check_sym_deps(sym);
-		if (sym2)
-			break;
-	}
-out:
-	expr_list_for_each_sym(prop->expr, e, sym)
-		sym->flags &= ~SYMBOL_CHECK;
-
-	if (sym2 && sym_is_choice_value(sym2) &&
-	    prop_get_symbol(sym_get_choice_prop(sym2)) == choice)
-		sym2 = choice;
-
-	dep_stack_remove();
-
-	return sym2;
-}
-
-struct symbol *sym_check_deps(struct symbol *sym)
-{
-	struct symbol *sym2;
-	struct property *prop;
-
-	if (sym->flags & SYMBOL_CHECK) {
-		sym_check_print_recursive(sym);
-		return sym;
-	}
-	if (sym->flags & SYMBOL_CHECKED)
-		return NULL;
-
-	if (sym_is_choice_value(sym)) {
-		struct dep_stack stack;
-
-		/* for choice groups start the check with main choice symbol */
-		dep_stack_insert(&stack, sym);
-		prop = sym_get_choice_prop(sym);
-		sym2 = sym_check_deps(prop_get_symbol(prop));
-		dep_stack_remove();
-	} else if (sym_is_choice(sym)) {
-		sym2 = sym_check_choice_deps(sym);
-	} else {
-		sym->flags |= (SYMBOL_CHECK | SYMBOL_CHECKED);
-		sym2 = sym_check_sym_deps(sym);
-		sym->flags &= ~SYMBOL_CHECK;
-	}
-
-	return sym2;
-}
-
-struct property *prop_alloc(enum prop_type type, struct symbol *sym)
-{
-	struct property *prop;
-	struct property **propp;
-
-	prop = xmalloc(sizeof(*prop));
-	memset(prop, 0, sizeof(*prop));
-	prop->type = type;
-	prop->sym = sym;
-	prop->file = current_file;
-	prop->lineno = zconf_lineno();
-
-	/* append property to the prop list of symbol */
-	if (sym) {
-		for (propp = &sym->prop; *propp; propp = &(*propp)->next)
-			;
-		*propp = prop;
-	}
-
-	return prop;
-}
-
-struct symbol *prop_get_symbol(struct property *prop)
-{
-	if (prop->expr && (prop->expr->type == E_SYMBOL ||
-			   prop->expr->type == E_LIST))
-		return prop->expr->left.sym;
-	return NULL;
-}
-
-const char *prop_get_type_name(enum prop_type type)
-{
-	switch (type) {
-	case P_PROMPT:
-		return "prompt";
-	case P_COMMENT:
-		return "comment";
-	case P_MENU:
-		return "menu";
-	case P_DEFAULT:
-		return "default";
-	case P_CHOICE:
-		return "choice";
-	case P_SELECT:
-		return "select";
-	case P_IMPLY:
-		return "imply";
-	case P_RANGE:
-		return "range";
-	case P_SYMBOL:
-		return "symbol";
-	case P_UNKNOWN:
-		break;
-	}
-	return "unknown";
-}
diff --git a/util/kconfig/util.c b/util/kconfig/util.c
deleted file mode 100644
index 29585394df..0000000000
--- a/util/kconfig/util.c
+++ /dev/null
@@ -1,129 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2002-2005 Roman Zippel <zippel@linux-m68k.org>
- * Copyright (C) 2002-2005 Sam Ravnborg <sam@ravnborg.org>
- */
-
-#include <stdarg.h>
-#include <stdlib.h>
-#include <string.h>
-#include "lkc.h"
-
-/* file already present in list? If not add it */
-struct file *file_lookup(const char *name)
-{
-	struct file *file;
-
-	for (file = file_list; file; file = file->next) {
-		if (!strcmp(name, file->name)) {
-			return file;
-		}
-	}
-
-	file = xmalloc(sizeof(*file));
-	memset(file, 0, sizeof(*file));
-	file->name = xstrdup(name);
-	file->next = file_list;
-	file_list = file;
-	return file;
-}
-
-/* Allocate initial growable string */
-struct gstr str_new(void)
-{
-	struct gstr gs;
-	gs.s = xmalloc(sizeof(char) * 64);
-	gs.len = 64;
-	gs.max_width = 0;
-	strcpy(gs.s, "\0");
-	return gs;
-}
-
-/* Free storage for growable string */
-void str_free(struct gstr *gs)
-{
-	if (gs->s)
-		free(gs->s);
-	gs->s = NULL;
-	gs->len = 0;
-}
-
-/* Append to growable string */
-void str_append(struct gstr *gs, const char *s)
-{
-	size_t l;
-	if (s) {
-		l = strlen(gs->s) + strlen(s) + 1;
-		if (l > gs->len) {
-			gs->s = xrealloc(gs->s, l);
-			gs->len = l;
-		}
-		strcat(gs->s, s);
-	}
-}
-
-/* Append printf formatted string to growable string */
-void str_printf(struct gstr *gs, const char *fmt, ...)
-{
-	va_list ap;
-	char s[10000]; /* big enough... */
-	va_start(ap, fmt);
-	vsnprintf(s, sizeof(s), fmt, ap);
-	str_append(gs, s);
-	va_end(ap);
-}
-
-/* Retrieve value of growable string */
-const char *str_get(struct gstr *gs)
-{
-	return gs->s;
-}
-
-void *xmalloc(size_t size)
-{
-	void *p = malloc(size);
-	if (p)
-		return p;
-	fprintf(stderr, "Out of memory.\n");
-	exit(1);
-}
-
-void *xcalloc(size_t nmemb, size_t size)
-{
-	void *p = calloc(nmemb, size);
-	if (p)
-		return p;
-	fprintf(stderr, "Out of memory.\n");
-	exit(1);
-}
-
-void *xrealloc(void *p, size_t size)
-{
-	p = realloc(p, size);
-	if (p)
-		return p;
-	fprintf(stderr, "Out of memory.\n");
-	exit(1);
-}
-
-char *xstrdup(const char *s)
-{
-	char *p;
-
-	p = strdup(s);
-	if (p)
-		return p;
-	fprintf(stderr, "Out of memory.\n");
-	exit(1);
-}
-
-char *xstrndup(const char *s, size_t n)
-{
-	char *p;
-
-	p = strndup(s, n);
-	if (p)
-		return p;
-	fprintf(stderr, "Out of memory.\n");
-	exit(1);
-}
diff --git a/util/kconfig_check.py b/util/kconfig_check.py
new file mode 100755
index 0000000000..48060f6782
--- /dev/null
+++ b/util/kconfig_check.py
@@ -0,0 +1,600 @@
+#!/usr/bin/env python3
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Kconfig checker
+
+Checks that the .config file provided does not introduce any new ad-hoc CONFIG
+options
+
+This tool is also present in U-Boot, so we should keep the two in sync.
+
+The tool supports two formats for the 'configs' file:
+
+   CONFIG_SOMETHING=xx
+
+and
+
+   #define CONFIG_SOMETHING xx
+
+Use the -d flag to select the second format.
+"""
+
+import argparse
+import glob
+import os
+import pathlib
+import re
+import sys
+import traceback
+
+
+# Try to use kconfiglib if available, but fall back to a simple recursive grep.
+# This is used by U-Boot in some situations so we keep it to avoid forking this
+# script.
+USE_KCONFIGLIB = False
+try:
+    import kconfiglib
+
+    USE_KCONFIGLIB = True
+except ImportError:
+    pass
+
+# Where we put the new config_allowed file
+NEW_ALLOWED_FNAME = pathlib.Path("/tmp/new_config_allowed.txt")
+
+
+def parse_args(argv):
+    """Parse the program arguments
+
+    Args:
+        argv: List of arguments to parse, excluding the program name
+
+    Returns:
+        argparse.Namespace object containing the results
+    """
+    epilog = """Checks that new ad-hoc CONFIG options are not introduced without
+a corresponding Kconfig option for Zephyr"""
+
+    parser = argparse.ArgumentParser(epilog=epilog)
+    parser.add_argument(
+        "-a",
+        "--allowed",
+        type=str,
+        default="util/config_allowed.txt",
+        help="File containing list of allowed ad-hoc CONFIGs",
+    )
+    parser.add_argument(
+        "-c",
+        "--configs",
+        type=str,
+        default=".config",
+        help="File containing CONFIG options to check",
+    )
+    parser.add_argument(
+        "-d",
+        "--use-defines",
+        action="store_true",
+        help="Lines in the configs file use #define",
+    )
+    parser.add_argument(
+        "-D",
+        "--debug",
+        action="store_true",
+        help="Enabling debugging (provides a full traceback on error)",
+    )
+    parser.add_argument(
+        "-i",
+        "--ignore",
+        action="append",
+        help="Kconfig options to ignore (without CONFIG_ prefix)",
+    )
+    parser.add_argument(
+        "-I",
+        "--search-path",
+        type=str,
+        action="append",
+        help="Search paths to look for Kconfigs",
+    )
+    parser.add_argument(
+        "-p",
+        "--prefix",
+        type=str,
+        default="PLATFORM_EC_",
+        help="Prefix to string from Kconfig options",
+    )
+    parser.add_argument(
+        "-s",
+        "--srctree",
+        type=str,
+        default="zephyr/",
+        help="Path to source tree to look for Kconfigs",
+    )
+
+    # TODO(sjg@chromium.org): The chroot uses a very old Python. Once it moves
+    # to 3.7 or later we can use this instead:
+    #    subparsers = parser.add_subparsers(dest='cmd', required=True)
+    subparsers = parser.add_subparsers(dest="cmd")
+    subparsers.required = True
+
+    subparsers.add_parser("build", help="Build new list of ad-hoc CONFIGs")
+    subparsers.add_parser("check", help="Check for new ad-hoc CONFIGs")
+    subparsers.add_parser(
+        "check_undef", help="Verify #undef directives in ec headers"
+    )
+
+    return parser.parse_args(argv)
+
+
+class KconfigCheck:
+    """Class for handling checking of CONFIG options against Kconfig options
+
+    The goal is to make sure that CONFIG_xxx options used by a build have an
+    equivalent Kconfig option defined as well.
+
+    For example if a Kconfig file has:
+
+         config PREFIX_MY_CONFIG
+             ...
+
+    and the CONFIG files has
+
+         CONFIG_MY_CONFIG
+
+    then we consider these equivalent (with the prefix 'PREFIX_') and thus
+    CONFIG_MY_CONFIG is allowed to be used.
+
+    If any CONFIG option is found that does not have an equivalent in the Kconfig,
+    the user is exhorted to add a new Kconfig. This helps avoid adding new ad-hoc
+    CONFIG options, eventually returning the number to zero.
+    """
+
+    @classmethod
+    def find_new_adhoc(cls, configs, kconfigs, allowed):
+        """Get a list of new ad-hoc CONFIG options
+
+        Arguments and return value should omit the 'CONFIG_' prefix, so
+        CONFIG_LTO should be provided as 'LTO'.
+
+        Args:
+            configs: List of existing CONFIG options
+            kconfigs: List of existing Kconfig options
+            allowed: List of allowed CONFIG options
+
+        Returns:
+            List of new CONFIG options, with the CONFIG_ prefix removed
+        """
+        return sorted(set(configs) - set(kconfigs) - set(allowed))
+
+    @classmethod
+    def find_unneeded_adhoc(cls, kconfigs, allowed):
+        """Get a list of ad-hoc CONFIG options that now have Kconfig options
+
+        Arguments and return value should omit the 'CONFIG_' prefix, so
+        CONFIG_LTO should be provided as 'LTO'.
+
+        Args:
+            kconfigs: List of existing Kconfig options
+            allowed: List of allowed CONFIG options
+
+        Returns:
+            List of new CONFIG options, with the CONFIG_ prefix removed
+        """
+        return sorted(set(allowed) & set(kconfigs))
+
+    @classmethod
+    def get_updated_adhoc(cls, unneeded_adhoc, allowed):
+        """Get a list of ad-hoc CONFIG options that are still needed
+
+        Arguments and return value should omit the 'CONFIG_' prefix, so
+        CONFIG_LTO should be provided as 'LTO'.
+
+        Args:
+            unneeded_adhoc: List of ad-hoc CONFIG options to remove
+            allowed: Current list of allowed CONFIG options
+
+        Returns:
+            New version of allowed CONFIG options, with the CONFIG_ prefix
+            removed
+        """
+        return sorted(set(allowed) - set(unneeded_adhoc))
+
+    @classmethod
+    def read_configs(cls, configs_file, use_defines=False):
+        """Read CONFIG options from a file
+
+        The file consists of a number of lines, each containing a CONFIG
+        option
+
+        Args:
+            configs_file: Filename to read from (e.g. u-boot.cfg)
+            use_defines: True if each line of the file starts with #define
+
+        Returns:
+            List of CONFIG_xxx options found in the file, with the 'CONFIG_'
+                prefix removed
+        """
+        with open(configs_file, "r") as inf:
+            configs = re.findall(
+                "%sCONFIG_([A-Za-z0-9_]*)%s"
+                % (
+                    (use_defines and "#define " or ""),
+                    (use_defines and " " or ""),
+                ),
+                inf.read(),
+            )
+        return configs
+
+    @classmethod
+    def read_allowed(cls, allowed_file):
+        """Read allowed CONFIG options from a file
+
+        Args:
+            allowed_file: Filename to read from
+
+        Returns:
+            List of CONFIG_xxx options found in the file, with the 'CONFIG_'
+                prefix removed
+        """
+        with open(allowed_file, "r") as inf:
+            configs = re.findall("CONFIG_([A-Za-z0-9_]*)", inf.read())
+        return configs
+
+    @classmethod
+    def find_kconfigs(cls, srcdir):
+        """Find all the Kconfig files in a source directory, recursively
+
+        Any subdirectory called 'Kconfig' is ignored, since Zephyr generates
+        this in its build directory.
+
+        Args:
+            srcdir: Directory to scan
+
+        Returns:
+            List of pathnames found
+        """
+        kconfig_files = []
+        for root, dirs, files in os.walk(srcdir):
+            kconfig_files += [
+                os.path.join(root, fname)
+                for fname in files
+                if fname.startswith("Kconfig")
+            ]
+            if "Kconfig" in dirs:
+                dirs.remove("Kconfig")
+            if "boards" in dirs:
+                dirs.remove("boards")
+            if "program" in dirs:
+                dirs.remove("program")
+            if "test" in dirs:
+                dirs.remove("test")
+            if "chip" in dirs:
+                dirs.remove("chip")
+        return kconfig_files
+
+    @classmethod
+    def scan_kconfigs(
+        cls, srcdir, prefix="", search_paths=None, try_kconfiglib=True
+    ):
+        """Scan a source tree for Kconfig options
+
+        Args:
+            srcdir: Directory to scan (containing top-level Kconfig file)
+            prefix: Prefix to strip from the name (e.g. 'PLATFORM_EC_')
+            search_paths: List of project paths to search for Kconfig files, in
+                addition to the current directory
+            try_kconfiglib: Use kconfiglib if available
+
+        Returns:
+            List of config and menuconfig options found
+        """
+        if USE_KCONFIGLIB and try_kconfiglib:
+            os.environ.update(
+                {
+                    "srctree": srcdir,
+                    "SOC_DIR": "soc",
+                    "ARCH_DIR": "arch",
+                    "BOARD_DIR": "boards/*/*",
+                    "ARCH": "*",
+                }
+            )
+            kconfigs = []
+            for filename in [
+                "Kconfig",
+                os.path.join(os.environ["ZEPHYR_BASE"], "Kconfig.zephyr"),
+            ]:
+                kconf = kconfiglib.Kconfig(
+                    filename,
+                    warn=False,
+                    search_paths=search_paths,
+                    allow_empty_macros=True,
+                )
+
+                symbols = [
+                    node.item.name
+                    for node in kconf.node_iter()
+                    if isinstance(node.item, kconfiglib.Symbol)
+                ]
+
+                if prefix:
+                    re_drop_prefix = re.compile(r"^%s" % prefix)
+                    symbols = [re_drop_prefix.sub("", name) for name in symbols]
+                kconfigs += symbols
+        else:
+            kconfigs = []
+            # Remove the prefix if present
+            expr = re.compile(
+                r"\n(config|menuconfig) (%s)?([A-Za-z0-9_]*)\n" % prefix
+            )
+            for fname in cls.find_kconfigs(srcdir):
+                with open(fname) as inf:
+                    found = re.findall(expr, inf.read())
+                    kconfigs += [name for kctype, _, name in found]
+        return sorted(kconfigs)
+
+    def check_adhoc_configs(
+        self,
+        configs_file,
+        srcdir,
+        allowed_file,
+        prefix="",
+        use_defines=False,
+        search_paths=None,
+    ):
+        """Find new and unneeded ad-hoc configs in the configs_file
+
+        Args:
+            configs_file: Filename containing CONFIG options to check
+            srcdir: Source directory to scan for Kconfig files
+            allowed_file: File containing allowed CONFIG options
+            prefix: Prefix to strip from the start of each Kconfig
+                (e.g. 'PLATFORM_EC_')
+            use_defines: True if each line of the file starts with #define
+            search_paths: List of project paths to search for Kconfig files, in
+                addition to the current directory
+
+        Returns:
+            Tuple:
+                List of new ad-hoc CONFIG options (without 'CONFIG_' prefix)
+                List of ad-hoc CONFIG options (without 'CONFIG_' prefix) that
+                    are no-longer needed, since they now have an associated
+                    Kconfig
+                List of ad-hoc CONFIG options that are still needed, given the
+                    current state of the Kconfig options
+        """
+        configs = self.read_configs(configs_file, use_defines)
+        try:
+            kconfigs = self.scan_kconfigs(srcdir, prefix, search_paths)
+        except kconfiglib.KconfigError:
+            # If we don't actually have access to the full Kconfig then we may
+            # get an error. Fall back to using manual methods.
+            print("WARNING: kconfiglib failed", file=sys.stderr)
+            traceback.print_exc()
+            kconfigs = self.scan_kconfigs(
+                srcdir, prefix, search_paths, try_kconfiglib=False
+            )
+
+        allowed = self.read_allowed(allowed_file)
+        new_adhoc = self.find_new_adhoc(configs, kconfigs, allowed)
+        unneeded_adhoc = self.find_unneeded_adhoc(kconfigs, allowed)
+        updated_adhoc = self.get_updated_adhoc(unneeded_adhoc, allowed)
+        return new_adhoc, unneeded_adhoc, updated_adhoc
+
+    def do_check(
+        self,
+        configs_file,
+        srcdir,
+        allowed_file,
+        prefix,
+        use_defines,
+        search_paths,
+        ignore=None,
+    ):
+        """Find new ad-hoc configs in the configs_file
+
+        Args:
+            configs_file: Filename containing CONFIG options to check
+            srcdir: Source directory to scan for Kconfig files
+            allowed_file: File containing allowed CONFIG options
+            prefix: Prefix to strip from the start of each Kconfig
+                (e.g. 'PLATFORM_EC_')
+            use_defines: True if each line of the file starts with #define
+            search_paths: List of project paths to search for Kconfig files, in
+                addition to the current directory
+            ignore: List of Kconfig options to ignore if they match an ad-hoc
+                CONFIG. This means they will not cause an error if they match
+                an ad-hoc CONFIG.
+
+        Returns:
+            Exit code: 0 if OK, 1 if a problem was found
+        """
+        new_adhoc, unneeded_adhoc, updated_adhoc = self.check_adhoc_configs(
+            configs_file,
+            srcdir,
+            allowed_file,
+            prefix,
+            use_defines,
+            search_paths,
+        )
+        if new_adhoc:
+            file_list = "\n".join(["CONFIG_%s" % name for name in new_adhoc])
+            print(
+                f"""Error:\tThe EC is in the process of migrating to Zephyr.
+\tZephyr uses Kconfig for configuration rather than ad-hoc #defines.
+\tAny new EC CONFIG options must ALSO be added to Zephyr so that new
+\tfunctionality is available in Zephyr also. The following new ad-hoc
+\tCONFIG options were detected:
+
+{file_list}
+
+Please add these via Kconfig instead. Find a suitable Kconfig
+file in zephyr/ and add a 'config' or 'menuconfig' option.
+Also see details in http://issuetracker.google.com/181253613
+
+To temporarily disable this, use: ALLOW_CONFIG=1 make ...
+""",
+                file=sys.stderr,
+            )
+            return 1
+
+        if not ignore:
+            ignore = []
+        unneeded_adhoc = [name for name in unneeded_adhoc if name not in ignore]
+        if unneeded_adhoc:
+            with open(NEW_ALLOWED_FNAME, "w") as out:
+                for config in updated_adhoc:
+                    print("CONFIG_%s" % config, file=out)
+            now_in_kconfig = "\n".join(
+                ["CONFIG_%s" % name for name in unneeded_adhoc]
+            )
+            print(
+                f"""The following options are now in Kconfig:
+
+{now_in_kconfig}
+
+Please run this to update the list of allowed ad-hoc CONFIGs and include this
+update in your CL:
+
+   cp {NEW_ALLOWED_FNAME} util/config_allowed.txt
+"""
+            )
+            return 1
+        return 0
+
+    def do_build(
+        self,
+        configs_file,
+        srcdir,
+        allowed_file,
+        prefix,
+        use_defines,
+        search_paths,
+    ):
+        """Find new ad-hoc configs in the configs_file
+
+        Args:
+            configs_file: Filename containing CONFIG options to check
+            srcdir: Source directory to scan for Kconfig files
+            allowed_file: File containing allowed CONFIG options
+            prefix: Prefix to strip from the start of each Kconfig
+                (e.g. 'PLATFORM_EC_')
+            use_defines: True if each line of the file starts with #define
+            search_paths: List of project paths to search for Kconfig files, in
+                addition to the current directory
+
+        Returns:
+            Exit code: 0 if OK, 1 if a problem was found
+        """
+        new_adhoc, _, updated_adhoc = self.check_adhoc_configs(
+            configs_file,
+            srcdir,
+            allowed_file,
+            prefix,
+            use_defines,
+            search_paths,
+        )
+        with open(NEW_ALLOWED_FNAME, "w") as out:
+            combined = sorted(new_adhoc + updated_adhoc)
+            for config in combined:
+                print(f"CONFIG_{config}", file=out)
+        print(f"New list is in {NEW_ALLOWED_FNAME}")
+
+    def check_undef(
+        self,
+        srcdir,
+        search_paths,
+    ):
+        """Parse the ec header files and find zephyr Kconfigs that are
+        incorrectly undefined or defined to a default value.
+
+        Args:
+            srcdir: Source directory to scan for Kconfig files
+            search_paths: List of project paths to search for Kconfig files, in
+                addition to the current directory
+
+        Returns:
+            Exit code: 0 if OK, 1 if a problem was found
+        """
+        kconfigs = set(self.scan_kconfigs(srcdir, "", search_paths))
+
+        if_re = re.compile(r"^\s*#\s*if(ndef CONFIG_ZEPHYR)?")
+        endif_re = re.compile(r"^\s*#\s*endif")
+        modify_config_re = re.compile(r"^\s*#\s*(define|undef)\s+CONFIG_(\S*)")
+        exit_code = 0
+        files_to_check = glob.glob(
+            os.path.join(srcdir, "include/**/*.h"), recursive=True
+        )
+        files_to_check += glob.glob(
+            os.path.join(srcdir, "common/**/public/*.h"), recursive=True
+        )
+        files_to_check += glob.glob(
+            os.path.join(srcdir, "driver/**/*.h"), recursive=True
+        )
+        for filename in files_to_check:
+            with open(filename, "r") as config_h:
+                depth = 0
+                ignore_depth = 0
+                line_count = 0
+                for line in config_h.readlines():
+                    line_count += 1
+                    line = line.strip("\n")
+                    match = if_re.match(line)
+                    if match:
+                        depth += 1
+                        if match[1] or ignore_depth > 0:
+                            ignore_depth += 1
+                    if endif_re.match(line):
+                        if depth > 0:
+                            depth -= 1
+                        if ignore_depth > 0:
+                            ignore_depth -= 1
+                    if ignore_depth == 0:
+                        match = modify_config_re.match(line)
+                        if match:
+                            if match[2] in kconfigs:
+                                print(
+                                    f"ERROR: Modifying CONFIG_{match[2]} "
+                                    "outside of #ifndef CONFIG_ZEPHYR not "
+                                    f"allowed at {filename}:{line_count}",
+                                    file=sys.stderr,
+                                )
+                                exit_code = 1
+        return exit_code
+
+
+def main(argv):
+    """Main function"""
+    args = parse_args(argv)
+    if not args.debug:
+        sys.tracebacklimit = 0
+    checker = KconfigCheck()
+    if args.cmd == "check":
+        return checker.do_check(
+            configs_file=args.configs,
+            srcdir=args.srctree,
+            allowed_file=args.allowed,
+            prefix=args.prefix,
+            use_defines=args.use_defines,
+            search_paths=args.search_path,
+            ignore=args.ignore,
+        )
+    if args.cmd == "build":
+        return checker.do_build(
+            configs_file=args.configs,
+            srcdir=args.srctree,
+            allowed_file=args.allowed,
+            prefix=args.prefix,
+            use_defines=args.use_defines,
+            search_paths=args.search_path,
+        )
+    if args.cmd == "check_undef":
+        return checker.check_undef(
+            srcdir=args.srctree,
+            search_paths=args.search_path,
+        )
+    return 2
+
+
+if __name__ == "__main__":
+    sys.exit(main(sys.argv[1:]))
diff --git a/util/keeby-relevant-paths.txt b/util/keeby-relevant-paths.txt
new file mode 120000
index 0000000000..9b63ef59c7
--- /dev/null
+++ b/util/keeby-relevant-paths.txt
@@ -0,0 +1 @@
+dedede-relevant-paths.txt
\ No newline at end of file
diff --git a/util/lbcc.c b/util/lbcc.c
deleted file mode 100644
index 1a201e90d8..0000000000
--- a/util/lbcc.c
+++ /dev/null
@@ -1,690 +0,0 @@
-/*
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <errno.h>
-#include <stdarg.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
-
-#include "compile_time_macros.h"
-#include "ec_commands.h"
-#include "lb_common.h"
-#include "lightbar.h"
-
-static const char usage[] =
-	"\n"
-	"Usage:  %s [OPTIONS] [INFILE [OUTFILE]]\n"
-	"\n"
-	"This compiles or decompiles the lightbar programmable bytecode.\n"
-	"\n"
-	"Options:\n"
-	"  -d         Decode binary to ascii\n"
-	"  -v         Decode output should be verbose\n"
-	"\n";
-
-/* globals */
-static int hit_errors;
-static int opt_verbose;
-static int is_jump_target[EC_LB_PROG_LEN];	/* does program jump here? */
-static int is_instruction[EC_LB_PROG_LEN];	/* instruction or operand? */
-static char *label[EC_LB_PROG_LEN];		/* labels we've seen */
-static char *reloc_label[EC_LB_PROG_LEN];	/* put label target here */
-
-static void Error(const char *format, ...)
-{
-	va_list ap;
-	va_start(ap, format);
-	fprintf(stderr, "ERROR: ");
-	vfprintf(stderr, format, ap);
-	va_end(ap);
-	hit_errors++;
-}
-
-static void Warning(const char *format, ...)
-{
-	va_list ap;
-	va_start(ap, format);
-	fprintf(stderr, "Warning: ");
-	vfprintf(stderr, format, ap);
-	va_end(ap);
-}
-
-/* The longest line should have a label, an opcode, and the max operands */
-#define LB_PROG_MAX_OPERANDS 4
-#define MAX_WORDS (2 + LB_PROG_MAX_OPERANDS)
-
-struct safe_lightbar_program {
-	struct lightbar_program p;
-	uint8_t zeros[LB_PROG_MAX_OPERANDS];
-} __packed;
-
-#define OP(NAME, BYTES, MNEMONIC) NAME,
-#include "lightbar_opcode_list.h"
-enum lightbyte_opcode {
-	LIGHTBAR_OPCODE_TABLE
-	MAX_OPCODE
-};
-#undef OP
-
-#define OP(NAME, BYTES, MNEMONIC) BYTES,
-#include "lightbar_opcode_list.h"
-static const int num_operands[] = {
-	LIGHTBAR_OPCODE_TABLE
-};
-#undef OP
-
-#define OP(NAME, BYTES, MNEMONIC) MNEMONIC,
-#include "lightbar_opcode_list.h"
-static const char * const opcode_sym[] = {
-	LIGHTBAR_OPCODE_TABLE
-};
-#undef OP
-
-static const char * const control_sym[] = {
-	"beg", "end", "phase", "<invalid>"
-};
-static const char * const color_sym[] = {
-	"r", "g", "b", "<invalid>"
-};
-
-static void read_binary(FILE *fp, struct safe_lightbar_program *prog)
-{
-	int got;
-
-	memset(prog, 0, sizeof(*prog));
-
-	/* Read up to one more byte than we need, so we know if it's too big */
-	got = fread(prog->p.data, 1, EC_LB_PROG_LEN + 1, fp);
-	if (got < 1) {
-		Error("Unable to read any input: ");
-		if (feof(fp))
-			fprintf(stderr, "EOF\n");
-		else if (ferror(fp))
-			fprintf(stderr, "%s\n", strerror(errno));
-		else
-			fprintf(stderr, "no idea why.\n");
-	} else if (got > EC_LB_PROG_LEN) {
-		Warning("Truncating input at %d bytes\n", EC_LB_PROG_LEN);
-		prog->zeros[0] = 0;
-		got = EC_LB_PROG_LEN;
-	} else {
-		prog->p.size = got;
-	}
-}
-
-static uint32_t val32(uint8_t *ptr)
-{
-	uint32_t val;
-	val = (ptr[0] << 24) | (ptr[1] << 16) | (ptr[2] << 8) | ptr[3];
-	return val;
-}
-
-static int is_jump(uint8_t op)
-{
-	/* TODO: probably should be a field in the opcode list */
-	return op >= JUMP && op <= JUMP_IF_CHARGING;
-}
-
-static void print_led_set(FILE *fp, uint8_t led)
-{
-	int i, first = 1;
-
-	fprintf(fp, "{");
-	for (i = 0; i < NUM_LEDS; i++)
-		if (led & BIT(i)) {
-			if (!first)
-				fprintf(fp, ",");
-			fprintf(fp, "%d", i);
-			first = 0;
-		}
-	fprintf(fp, "}");
-}
-
-/* returns number of operands consumed */
-static int print_op(FILE *fp, uint8_t addr, uint8_t cmd, uint8_t *arg)
-{
-	uint8_t led, color, control;
-	int i, operands;
-
-	operands = num_operands[cmd];
-
-	/* assume valid instruction for now */
-	is_instruction[addr] = 1;
-
-	if (opt_verbose) {
-		fprintf(fp, "%02x:  %02x", addr, cmd);
-		for (i = 0; i < LB_PROG_MAX_OPERANDS; i++)
-			if (i < operands)
-				fprintf(fp, " %02x", arg[i]);
-			else
-				fprintf(fp, "   ");
-		fprintf(fp, "\t");
-	}
-	if (is_jump_target[addr])
-		fprintf(fp, "L00%02x:", addr);
-	fprintf(fp, "\t");
-
-	if (cmd < MAX_OPCODE)
-		fprintf(fp, "%s", opcode_sym[cmd]);
-
-	switch (cmd) {
-	case JUMP:
-	case JUMP_IF_CHARGING:
-		fprintf(fp, "\tL00%02x\n", arg[0]);
-		break;
-	case JUMP_BATTERY:
-		fprintf(fp, "\tL00%02x L00%02x\n", arg[0], arg[1]);
-		break;
-	case SET_WAIT_DELAY:
-	case SET_RAMP_DELAY:
-		fprintf(fp, "\t%d\n", val32(arg));
-		break;
-	case SET_BRIGHTNESS:
-		fprintf(fp, "\t%d\n", arg[0]);
-		break;
-	case SET_COLOR_SINGLE:
-		led = arg[0] >> 4;
-		control = (arg[0] >> 2) & 0x03;
-		color = arg[0] & 0x03;
-		fprintf(fp, "\t");
-
-		print_led_set(fp, led);
-		fprintf(fp, ".%s", control_sym[control]);
-		fprintf(fp, ".%s", color_sym[color]);
-		fprintf(fp, "\t0x%02x\n", arg[1]);
-		break;
-	case SET_COLOR_RGB:
-		led = arg[0] >> 4;
-		control = (arg[0] >> 2) & 0x03;
-		fprintf(fp, "\t");
-
-		print_led_set(fp, led);
-		fprintf(fp, ".%s", control_sym[control]);
-		fprintf(fp, "\t0x%02x 0x%02x 0x%02x\n", arg[1], arg[2], arg[3]);
-		break;
-	case ON:
-	case OFF:
-	case WAIT:
-	case GET_COLORS:
-	case SWAP_COLORS:
-	case RAMP_ONCE:
-	case CYCLE_ONCE:
-	case CYCLE:
-	case HALT:
-		fprintf(fp, "\n");
-		break;
-	default:
-		fprintf(fp, "-- invalid opcode 0x%02x --\n", cmd);
-		is_instruction[addr] = 0;
-		hit_errors++;
-	}
-
-	return operands;
-}
-
-static void set_jump_target(uint8_t targ)
-{
-	if (targ >= EC_LB_PROG_LEN) {
-		Warning("program jumps to 0x%02x, "
-			"which out of bounds\n", targ);
-		return;
-	}
-	is_jump_target[targ] = 1;
-}
-
-static void disassemble_prog(FILE *fp, struct safe_lightbar_program *prog)
-{
-	int i;
-	uint8_t *ptr, op;
-
-	/* Scan the program once to identify all the jump targets,
-	 * so we can print the labels when we encounter them. */
-	for (i = 0; i < prog->p.size; i++) {
-		ptr = &prog->p.data[i];
-		op = *ptr;
-		if (is_jump(op))
-			set_jump_target(ptr[1]);
-		if (op == JUMP_BATTERY)
-			set_jump_target(ptr[2]);
-		i += num_operands[op];
-	}
-
-	/* Now disassemble */
-	for (i = 0; i < prog->p.size; i++) {
-		ptr = &prog->p.data[i];
-		i += print_op(fp, i, *ptr, ptr + 1);
-	}
-
-	/* Finally, make sure the program doesn't jump to any location other
-	 * than a valid instruction */
-	for (i = 0; i < EC_LB_PROG_LEN; i++)
-		if (is_jump_target[i] && !is_instruction[i]) {
-			Warning("program jumps to 0x%02x, "
-				"which is not a valid instruction\n", i);
-		}
-}
-
-/* We'll split each line into an array of these. */
-struct parse_s {
-	char *word;
-	int is_num;
-	uint32_t val;
-};
-
-/* Fills in struct, returns number of words found. Note that pointers are only
- * copied. The strings they point to are not duplicated.  */
-static int split_line(char *buf, char *delim, struct parse_s *elt, int max)
-{
-	char *w, *ptr, *buf_savetok;
-	int i;
-	char *e = 0;
-
-	memset(elt, 0, max * sizeof(*elt));
-
-	for (ptr = buf, i = 0;
-	     i < max && (w = strtok_r(ptr, delim, &buf_savetok)) != 0;
-	     ptr = 0, i++) {
-		elt[i].word = w;
-		elt[i].val = (uint32_t)strtoul(w, &e, 0);
-		if (!e || !*e)
-			elt[i].is_num = 1;
-
-	}
-
-	return i;
-}
-
-/* Decode led set. Return 0 if bogus, 1 if okay. */
-static int is_led_set(char *buf, uint8_t *valp)
-{
-	uint8_t led = 0;
-	unsigned long int next_led;
-	char *ptr;
-
-	if (!buf)
-		return 0;
-
-	if (*buf != '{')
-		return 0;
-
-	buf++;
-	for (;;) {
-		next_led = strtoul(buf, &ptr, 0);
-		if (buf == ptr) {
-			if (buf[0] == '}' && buf[1] == 0) {
-				*valp = led;
-				return 1;
-			} else
-				return 0;
-		}
-
-		if (next_led >= NUM_LEDS)
-			return 0;
-
-		led |= 1 << next_led;
-
-		buf = ptr;
-		if (*buf == ',')
-			buf++;
-	}
-}
-
-/* Decode color arg based on expected control param sections.
- * Return 0 if bogus, 1 if okay.
- */
-static int is_color_arg(char *buf, int expected, uint32_t *valp)
-{
-	struct parse_s token[MAX_WORDS];
-	uint8_t led, control, color;
-	int i;
-
-	if (!buf)
-		return 0;
-
-	/* There should be three terms, separated with '.' */
-	i = split_line(buf, ".", token, MAX_WORDS);
-	if (i != expected)
-		return 0;
-
-	if (!is_led_set(token[0].word, &led)) {
-		Error("Invalid LED set \"%s\"\n", token[0].word);
-		return 0;
-	}
-
-	for (i = 0; i < LB_CONT_MAX; i++)
-		if (!strcmp(token[1].word, control_sym[i])) {
-			control = i;
-			break;
-		}
-	if (i >= LB_CONT_MAX)
-		return 0;
-
-	if (expected == 3) {
-		for (i = 0; i < ARRAY_SIZE(color_sym); i++)
-			if (!strcmp(token[2].word, color_sym[i])) {
-				color = i;
-				break;
-			}
-		if (i >= ARRAY_SIZE(color_sym))
-			return 0;
-	} else
-		color = 0;
-
-
-	*valp = ((led & 0xF) << 4) | ((control & 0x3) << 2) | (color & 0x3);
-	return 1;
-}
-
-static void fixup_symbols(struct safe_lightbar_program *prog)
-{
-	int i, j;
-
-	for (i = 0; i < EC_LB_PROG_LEN; i++) {
-		if (reloc_label[i]) {
-			/* Looking for reloc label */
-			for (j = 0; j < EC_LB_PROG_LEN; j++) {
-				if (label[j] && !strcmp(label[j],
-							reloc_label[i])) {
-					prog->p.data[i] = j;
-					break;
-				}
-			}
-			if (j >= EC_LB_PROG_LEN)
-				Error("Can't find label %s\n", reloc_label[i]);
-		}
-	}
-}
-
-
-static void compile(FILE *fp, struct safe_lightbar_program *prog)
-{
-	char buf[128];
-	struct parse_s token[MAX_WORDS];
-	char *s;
-	int line = 0, chopping = 0;
-	uint8_t addr = 0;
-	int opcode;
-	int wnum, wordcnt;
-	int i;
-
-	while (fgets(buf, sizeof(buf), fp)) {
-
-		/* We truncate lines that are too long */
-		s = strchr(buf, '\n');
-		if (chopping) {
-			if (s)
-				chopping = 0;
-			continue;
-		}
-
-		/* Got something to look at */
-		line++;
-		if (!s) {
-			chopping = 1;
-			Warning("truncating line %d\n", line);
-		}
-
-		/* Ignore comments */
-		s = strchr(buf, '#');
-		if (s)
-			*s = '\0';
-
-		wordcnt = split_line(buf, " \t\n", token, MAX_WORDS);
-		if (!wordcnt)
-			continue;
-
-		wnum = 0;
-
-		/* A label must be the first word, ends with a ':' (no spaces
-		 * before it), and doesn't start with a ':' */
-		s = strchr(token[0].word, ':');
-		if (s && s[1] == '\0' && s != token[0].word) {
-			*s = '\0';
-			label[addr] = strdup(token[0].word);
-			wnum++;
-		}
-
-		/* How about an opcode? */
-		for (opcode = 0; opcode < MAX_OPCODE; opcode++)
-			if (!strcasecmp(token[wnum].word, opcode_sym[opcode]))
-				break;
-
-		if (opcode >= MAX_OPCODE) {
-			Error("Unrecognized opcode \"%s\""
-			      " at line %d\n", token[wnum].word, line);
-			continue;
-		}
-
-		/* Do we even have a place to write this opcode? */
-		if (addr >= EC_LB_PROG_LEN) {
-			Error("out of program space at line %d\n", line);
-			break;
-		}
-
-		/* Got an opcode. Save it! */
-		prog->p.data[addr++] = opcode;
-		wnum++;
-
-		/* Now we need operands. */
-		switch (opcode) {
-		case JUMP:
-		case JUMP_IF_CHARGING:
-			/* a label */
-			if (token[wnum].word)
-				reloc_label[addr++] = strdup(token[wnum].word);
-			else
-				Error("Missing jump target at line %d\n", line);
-			break;
-		case JUMP_BATTERY:
-			/* two labels*/
-			if (token[wnum].word)
-				reloc_label[addr++] = strdup(token[wnum].word);
-			else {
-				Error("Missing first jump target "
-				      "at line %d\n", line);
-				break;
-			}
-			wnum++;
-			if (token[wnum].word)
-				reloc_label[addr++] = strdup(token[wnum].word);
-			else
-				Error("Missing second jump target "
-				      "at line %d\n", line);
-			break;
-
-		case SET_BRIGHTNESS:
-			/* one 8-bit arg */
-			if (token[wnum].is_num)
-				prog->p.data[addr++] = token[wnum].val;
-			else
-				Error("Missing/invalid arg at line %d\n", line);
-			break;
-
-		case SET_WAIT_DELAY:
-		case SET_RAMP_DELAY:
-			/* one 32-bit arg */
-			if (token[wnum].is_num) {
-				prog->p.data[addr++] =
-					(token[wnum].val >> 24) & 0xff;
-				prog->p.data[addr++] =
-					(token[wnum].val >> 16) & 0xff;
-				prog->p.data[addr++] =
-					(token[wnum].val >> 8) & 0xff;
-				prog->p.data[addr++] =
-					token[wnum].val & 0xff;
-			} else {
-				Error("Missing/invalid arg at line %d\n", line);
-			}
-			break;
-
-		case SET_COLOR_SINGLE:
-			/* one magic word, then one more 8-bit arg */
-			i = is_color_arg(token[wnum].word, 3, &token[wnum].val);
-			if (!i) {
-				Error("Missing/invalid arg at line %d\n", line);
-				break;
-			}
-			/* save the magic number */
-			prog->p.data[addr++] = token[wnum++].val;
-			/* and the color immediate */
-			if (token[wnum].is_num) {
-				prog->p.data[addr++] =
-					token[wnum++].val;
-			} else {
-				Error("Missing/Invalid arg "
-				      "at line %d\n", line);
-				break;
-			}
-			break;
-		case SET_COLOR_RGB:
-			/* one magic word, then three more 8-bit args */
-			i = is_color_arg(token[wnum].word, 2, &token[wnum].val);
-			if (!i) {
-				Error("Missing/invalid arg at line %d\n", line);
-				break;
-			}
-			/* save the magic number */
-			prog->p.data[addr++] = token[wnum++].val;
-			/* and the color immediates */
-			for (i = 0; i < 3; i++) {
-				if (token[wnum].is_num) {
-					prog->p.data[addr++] =
-						token[wnum++].val;
-				} else {
-					Error("Missing/Invalid arg "
-					      "at line %d\n", line);
-					break;
-				}
-			}
-			break;
-
-		default:
-			/* No args needed */
-			break;
-		}
-
-		/* Did we run past the end? */
-		if (addr > EC_LB_PROG_LEN) {
-			Error("out of program space at line %d\n", line);
-			break;
-		}
-	}
-	if (ferror(fp))
-		Error("problem while reading input: %s\n", strerror(errno));
-
-	if (!hit_errors)
-		fixup_symbols(prog);
-
-	if (!hit_errors)
-		prog->p.size = addr;
-
-	if (!prog->p.size)
-		Error("input file produced no output bytes\n");
-}
-
-int main(int argc, char *argv[])
-{
-	struct safe_lightbar_program safe_prog;
-	int opt_decode = 0;
-	int c;
-	int errorcnt = 0;
-	char *infile, *outfile;
-	FILE *ifp, *ofp;
-
-	char *progname = strrchr(argv[0], '/');
-	if (progname)
-		progname++;
-	else
-		progname = argv[0];
-
-	opterr = 0;                     /* quiet, you */
-	while ((c = getopt(argc, argv, ":dv")) != -1) {
-		switch (c) {
-		case 'd':
-			opt_decode = 1;
-			break;
-		case 'v':
-			opt_verbose = 1;
-			break;
-
-		case '?':
-			fprintf(stderr, "%s: unrecognized switch: -%c\n",
-				progname, optopt);
-			errorcnt++;
-			break;
-		case ':':
-			fprintf(stderr, "%s: missing argument to -%c\n",
-				progname, optopt);
-			errorcnt++;
-			break;
-		default:
-			errorcnt++;
-			break;
-		}
-	}
-
-	if (errorcnt) {
-		fprintf(stderr, usage, progname);
-		exit(1);
-	}
-
-	if (argc - optind > 0) {
-		infile = argv[optind];
-		ifp = fopen(infile, "rb");
-		if (!ifp) {
-			fprintf(stderr,
-				"%s: Unable to open %s for reading: %s\n",
-				progname, infile, strerror(errno));
-			exit(1);
-		}
-	} else {
-		infile = "stdin";
-		ifp = stdin;
-	}
-
-	if (argc - optind > 1) {
-		outfile = argv[optind + 1];
-		ofp = fopen(outfile, "wb");
-		if (!ofp) {
-			fprintf(stderr,
-				"%s: Unable to open %s for writing: %s\n",
-				progname, outfile, strerror(errno));
-			exit(1);
-		}
-	} else {
-		outfile = "stdout";
-		ofp = stdout;
-	}
-
-	if (opt_decode) {
-		read_binary(ifp, &safe_prog);
-		fclose(ifp);
-		if (hit_errors)
-			return 1;
-		fprintf(ofp, "# %s\n", infile);
-		disassemble_prog(ofp, &safe_prog);
-		fclose(ofp);
-	} else {
-		memset(&safe_prog, 0, sizeof(safe_prog));
-		compile(ifp, &safe_prog);
-		fclose(ifp);
-		if (!hit_errors) {
-			if (1 != fwrite(safe_prog.p.data,
-					safe_prog.p.size, 1, ofp))
-				Error("%s: Unable to write to %s: %s\n",
-				      progname, outfile, strerror(errno));
-			else
-				fprintf(stderr, "0x%02x bytes written to %s\n",
-					safe_prog.p.size, outfile);
-		}
-		fclose(ofp);
-	}
-
-	return hit_errors;
-}
diff --git a/util/lbcc.cc b/util/lbcc.cc
new file mode 100644
index 0000000000..5fa0a2e232
--- /dev/null
+++ b/util/lbcc.cc
@@ -0,0 +1,682 @@
+/*
+ * Copyright 2014 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "compile_time_macros.h"
+#include "ec_commands.h"
+#include "lb_common.h"
+#include "lightbar.h"
+
+#include <errno.h>
+#include <stdarg.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <unistd.h>
+
+static const char usage[] =
+	"\n"
+	"Usage:  %s [OPTIONS] [INFILE [OUTFILE]]\n"
+	"\n"
+	"This compiles or decompiles the lightbar programmable bytecode.\n"
+	"\n"
+	"Options:\n"
+	"  -d         Decode binary to ascii\n"
+	"  -v         Decode output should be verbose\n"
+	"\n";
+
+/* globals */
+static int hit_errors;
+static int opt_verbose;
+static int is_jump_target[EC_LB_PROG_LEN]; /* does program jump here? */
+static int is_instruction[EC_LB_PROG_LEN]; /* instruction or operand? */
+static char *label[EC_LB_PROG_LEN]; /* labels we've seen */
+static char *reloc_label[EC_LB_PROG_LEN]; /* put label target here */
+
+static void Error(const char *format, ...)
+{
+	va_list ap;
+	va_start(ap, format);
+	fprintf(stderr, "ERROR: ");
+	vfprintf(stderr, format, ap);
+	va_end(ap);
+	hit_errors++;
+}
+
+static void Warning(const char *format, ...)
+{
+	va_list ap;
+	va_start(ap, format);
+	fprintf(stderr, "Warning: ");
+	vfprintf(stderr, format, ap);
+	va_end(ap);
+}
+
+/* The longest line should have a label, an opcode, and the max operands */
+#define LB_PROG_MAX_OPERANDS 4
+#define MAX_WORDS (2 + LB_PROG_MAX_OPERANDS)
+
+struct safe_lightbar_program {
+	struct lightbar_program p;
+	uint8_t zeros[LB_PROG_MAX_OPERANDS];
+} __packed;
+
+#define OP(NAME, BYTES, MNEMONIC) NAME,
+#include "lightbar_opcode_list.h"
+enum lightbyte_opcode { LIGHTBAR_OPCODE_TABLE MAX_OPCODE };
+#undef OP
+
+#define OP(NAME, BYTES, MNEMONIC) BYTES,
+#include "lightbar_opcode_list.h"
+static const int num_operands[] = { LIGHTBAR_OPCODE_TABLE };
+#undef OP
+
+#define OP(NAME, BYTES, MNEMONIC) MNEMONIC,
+#include "lightbar_opcode_list.h"
+static const char *const opcode_sym[] = { LIGHTBAR_OPCODE_TABLE };
+#undef OP
+
+static const char *const control_sym[] = { "beg", "end", "phase", "<invalid>" };
+static const char *const color_sym[] = { "r", "g", "b", "<invalid>" };
+
+static void read_binary(FILE *fp, struct safe_lightbar_program *prog)
+{
+	int got;
+
+	memset(prog, 0, sizeof(*prog));
+
+	/* Read up to one more byte than we need, so we know if it's too big */
+	got = fread(prog->p.data, 1, EC_LB_PROG_LEN + 1, fp);
+	if (got < 1) {
+		Error("Unable to read any input: ");
+		if (feof(fp))
+			fprintf(stderr, "EOF\n");
+		else if (ferror(fp))
+			fprintf(stderr, "%s\n", strerror(errno));
+		else
+			fprintf(stderr, "no idea why.\n");
+	} else if (got > EC_LB_PROG_LEN) {
+		Warning("Truncating input at %d bytes\n", EC_LB_PROG_LEN);
+		prog->zeros[0] = 0;
+		got = EC_LB_PROG_LEN;
+	} else {
+		prog->p.size = got;
+	}
+}
+
+static uint32_t val32(uint8_t *ptr)
+{
+	uint32_t val;
+	val = (ptr[0] << 24) | (ptr[1] << 16) | (ptr[2] << 8) | ptr[3];
+	return val;
+}
+
+static int is_jump(uint8_t op)
+{
+	/* TODO: probably should be a field in the opcode list */
+	return op >= JUMP && op <= JUMP_IF_CHARGING;
+}
+
+static void print_led_set(FILE *fp, uint8_t led)
+{
+	int i, first = 1;
+
+	fprintf(fp, "{");
+	for (i = 0; i < NUM_LEDS; i++)
+		if (led & BIT(i)) {
+			if (!first)
+				fprintf(fp, ",");
+			fprintf(fp, "%d", i);
+			first = 0;
+		}
+	fprintf(fp, "}");
+}
+
+/* returns number of operands consumed */
+static int print_op(FILE *fp, uint8_t addr, uint8_t cmd, uint8_t *arg)
+{
+	uint8_t led, color, control;
+	int i, operands;
+
+	operands = num_operands[cmd];
+
+	/* assume valid instruction for now */
+	is_instruction[addr] = 1;
+
+	if (opt_verbose) {
+		fprintf(fp, "%02x:  %02x", addr, cmd);
+		for (i = 0; i < LB_PROG_MAX_OPERANDS; i++)
+			if (i < operands)
+				fprintf(fp, " %02x", arg[i]);
+			else
+				fprintf(fp, "   ");
+		fprintf(fp, "\t");
+	}
+	if (is_jump_target[addr])
+		fprintf(fp, "L00%02x:", addr);
+	fprintf(fp, "\t");
+
+	if (cmd < MAX_OPCODE)
+		fprintf(fp, "%s", opcode_sym[cmd]);
+
+	switch (cmd) {
+	case JUMP:
+	case JUMP_IF_CHARGING:
+		fprintf(fp, "\tL00%02x\n", arg[0]);
+		break;
+	case JUMP_BATTERY:
+		fprintf(fp, "\tL00%02x L00%02x\n", arg[0], arg[1]);
+		break;
+	case SET_WAIT_DELAY:
+	case SET_RAMP_DELAY:
+		fprintf(fp, "\t%d\n", val32(arg));
+		break;
+	case SET_BRIGHTNESS:
+		fprintf(fp, "\t%d\n", arg[0]);
+		break;
+	case SET_COLOR_SINGLE:
+		led = arg[0] >> 4;
+		control = (arg[0] >> 2) & 0x03;
+		color = arg[0] & 0x03;
+		fprintf(fp, "\t");
+
+		print_led_set(fp, led);
+		fprintf(fp, ".%s", control_sym[control]);
+		fprintf(fp, ".%s", color_sym[color]);
+		fprintf(fp, "\t0x%02x\n", arg[1]);
+		break;
+	case SET_COLOR_RGB:
+		led = arg[0] >> 4;
+		control = (arg[0] >> 2) & 0x03;
+		fprintf(fp, "\t");
+
+		print_led_set(fp, led);
+		fprintf(fp, ".%s", control_sym[control]);
+		fprintf(fp, "\t0x%02x 0x%02x 0x%02x\n", arg[1], arg[2], arg[3]);
+		break;
+	case ON:
+	case OFF:
+	case WAIT:
+	case GET_COLORS:
+	case SWAP_COLORS:
+	case RAMP_ONCE:
+	case CYCLE_ONCE:
+	case CYCLE:
+	case HALT:
+		fprintf(fp, "\n");
+		break;
+	default:
+		fprintf(fp, "-- invalid opcode 0x%02x --\n", cmd);
+		is_instruction[addr] = 0;
+		hit_errors++;
+	}
+
+	return operands;
+}
+
+static void set_jump_target(uint8_t targ)
+{
+	if (targ >= EC_LB_PROG_LEN) {
+		Warning("program jumps to 0x%02x, "
+			"which out of bounds\n",
+			targ);
+		return;
+	}
+	is_jump_target[targ] = 1;
+}
+
+static void disassemble_prog(FILE *fp, struct safe_lightbar_program *prog)
+{
+	int i;
+	uint8_t *ptr, op;
+
+	/* Scan the program once to identify all the jump targets,
+	 * so we can print the labels when we encounter them. */
+	for (i = 0; i < prog->p.size; i++) {
+		ptr = &prog->p.data[i];
+		op = *ptr;
+		if (is_jump(op))
+			set_jump_target(ptr[1]);
+		if (op == JUMP_BATTERY)
+			set_jump_target(ptr[2]);
+		i += num_operands[op];
+	}
+
+	/* Now disassemble */
+	for (i = 0; i < prog->p.size; i++) {
+		ptr = &prog->p.data[i];
+		i += print_op(fp, i, *ptr, ptr + 1);
+	}
+
+	/* Finally, make sure the program doesn't jump to any location other
+	 * than a valid instruction */
+	for (i = 0; i < EC_LB_PROG_LEN; i++)
+		if (is_jump_target[i] && !is_instruction[i]) {
+			Warning("program jumps to 0x%02x, "
+				"which is not a valid instruction\n",
+				i);
+		}
+}
+
+/* We'll split each line into an array of these. */
+struct parse_s {
+	char *word;
+	int is_num;
+	uint32_t val;
+};
+
+/* Fills in struct, returns number of words found. Note that pointers are only
+ * copied. The strings they point to are not duplicated.  */
+static int split_line(char *buf, const char *delim, struct parse_s *elt,
+		      int max)
+{
+	char *w, *ptr, *buf_savetok;
+	int i;
+	char *e = 0;
+
+	memset(elt, 0, max * sizeof(*elt));
+
+	for (ptr = buf, i = 0;
+	     i < max && (w = strtok_r(ptr, delim, &buf_savetok)) != 0;
+	     ptr = 0, i++) {
+		elt[i].word = w;
+		elt[i].val = (uint32_t)strtoull(w, &e, 0);
+		if (!e || !*e)
+			elt[i].is_num = 1;
+	}
+
+	return i;
+}
+
+/* Decode led set. Return 0 if bogus, 1 if okay. */
+static int is_led_set(char *buf, uint8_t *valp)
+{
+	uint8_t led = 0;
+	unsigned long int next_led;
+	char *ptr;
+
+	if (!buf)
+		return 0;
+
+	if (*buf != '{')
+		return 0;
+
+	buf++;
+	for (;;) {
+		next_led = strtoull(buf, &ptr, 0);
+		if (buf == ptr) {
+			if (buf[0] == '}' && buf[1] == 0) {
+				*valp = led;
+				return 1;
+			} else
+				return 0;
+		}
+
+		if (next_led >= NUM_LEDS)
+			return 0;
+
+		led |= 1 << next_led;
+
+		buf = ptr;
+		if (*buf == ',')
+			buf++;
+	}
+}
+
+/* Decode color arg based on expected control param sections.
+ * Return 0 if bogus, 1 if okay.
+ */
+static int is_color_arg(char *buf, int expected, uint32_t *valp)
+{
+	struct parse_s token[MAX_WORDS];
+	uint8_t led, control, color;
+	int i;
+
+	if (!buf)
+		return 0;
+
+	/* There should be three terms, separated with '.' */
+	i = split_line(buf, ".", token, MAX_WORDS);
+	if (i != expected)
+		return 0;
+
+	if (!is_led_set(token[0].word, &led)) {
+		Error("Invalid LED set \"%s\"\n", token[0].word);
+		return 0;
+	}
+
+	for (i = 0; i < LB_CONT_MAX; i++)
+		if (!strcmp(token[1].word, control_sym[i])) {
+			control = i;
+			break;
+		}
+	if (i >= LB_CONT_MAX)
+		return 0;
+
+	if (expected == 3) {
+		for (i = 0; i < ARRAY_SIZE(color_sym); i++)
+			if (!strcmp(token[2].word, color_sym[i])) {
+				color = i;
+				break;
+			}
+		if (i >= ARRAY_SIZE(color_sym))
+			return 0;
+	} else
+		color = 0;
+
+	*valp = ((led & 0xF) << 4) | ((control & 0x3) << 2) | (color & 0x3);
+	return 1;
+}
+
+static void fixup_symbols(struct safe_lightbar_program *prog)
+{
+	int i, j;
+
+	for (i = 0; i < EC_LB_PROG_LEN; i++) {
+		if (reloc_label[i]) {
+			/* Looking for reloc label */
+			for (j = 0; j < EC_LB_PROG_LEN; j++) {
+				if (label[j] &&
+				    !strcmp(label[j], reloc_label[i])) {
+					prog->p.data[i] = j;
+					break;
+				}
+			}
+			if (j >= EC_LB_PROG_LEN)
+				Error("Can't find label %s\n", reloc_label[i]);
+		}
+	}
+}
+
+static void compile(FILE *fp, struct safe_lightbar_program *prog)
+{
+	char buf[128];
+	struct parse_s token[MAX_WORDS];
+	char *s;
+	int line = 0, chopping = 0;
+	uint8_t addr = 0;
+	int opcode;
+	int wnum, wordcnt;
+	int i;
+
+	while (fgets(buf, sizeof(buf), fp)) {
+		/* We truncate lines that are too long */
+		s = strchr(buf, '\n');
+		if (chopping) {
+			if (s)
+				chopping = 0;
+			continue;
+		}
+
+		/* Got something to look at */
+		line++;
+		if (!s) {
+			chopping = 1;
+			Warning("truncating line %d\n", line);
+		}
+
+		/* Ignore comments */
+		s = strchr(buf, '#');
+		if (s)
+			*s = '\0';
+
+		wordcnt = split_line(buf, " \t\n", token, MAX_WORDS);
+		if (!wordcnt)
+			continue;
+
+		wnum = 0;
+
+		/* A label must be the first word, ends with a ':' (no spaces
+		 * before it), and doesn't start with a ':' */
+		s = strchr(token[0].word, ':');
+		if (s && s[1] == '\0' && s != token[0].word) {
+			*s = '\0';
+			label[addr] = strdup(token[0].word);
+			wnum++;
+		}
+
+		/* How about an opcode? */
+		for (opcode = 0; opcode < MAX_OPCODE; opcode++)
+			if (!strcasecmp(token[wnum].word, opcode_sym[opcode]))
+				break;
+
+		if (opcode >= MAX_OPCODE) {
+			Error("Unrecognized opcode \"%s\""
+			      " at line %d\n",
+			      token[wnum].word, line);
+			continue;
+		}
+
+		/* Do we even have a place to write this opcode? */
+		if (addr >= EC_LB_PROG_LEN) {
+			Error("out of program space at line %d\n", line);
+			break;
+		}
+
+		/* Got an opcode. Save it! */
+		prog->p.data[addr++] = opcode;
+		wnum++;
+
+		/* Now we need operands. */
+		switch (opcode) {
+		case JUMP:
+		case JUMP_IF_CHARGING:
+			/* a label */
+			if (token[wnum].word)
+				reloc_label[addr++] = strdup(token[wnum].word);
+			else
+				Error("Missing jump target at line %d\n", line);
+			break;
+		case JUMP_BATTERY:
+			/* two labels*/
+			if (token[wnum].word)
+				reloc_label[addr++] = strdup(token[wnum].word);
+			else {
+				Error("Missing first jump target "
+				      "at line %d\n",
+				      line);
+				break;
+			}
+			wnum++;
+			if (token[wnum].word)
+				reloc_label[addr++] = strdup(token[wnum].word);
+			else
+				Error("Missing second jump target "
+				      "at line %d\n",
+				      line);
+			break;
+
+		case SET_BRIGHTNESS:
+			/* one 8-bit arg */
+			if (token[wnum].is_num)
+				prog->p.data[addr++] = token[wnum].val;
+			else
+				Error("Missing/invalid arg at line %d\n", line);
+			break;
+
+		case SET_WAIT_DELAY:
+		case SET_RAMP_DELAY:
+			/* one 32-bit arg */
+			if (token[wnum].is_num) {
+				prog->p.data[addr++] = (token[wnum].val >> 24) &
+						       0xff;
+				prog->p.data[addr++] = (token[wnum].val >> 16) &
+						       0xff;
+				prog->p.data[addr++] = (token[wnum].val >> 8) &
+						       0xff;
+				prog->p.data[addr++] = token[wnum].val & 0xff;
+			} else {
+				Error("Missing/invalid arg at line %d\n", line);
+			}
+			break;
+
+		case SET_COLOR_SINGLE:
+			/* one magic word, then one more 8-bit arg */
+			i = is_color_arg(token[wnum].word, 3, &token[wnum].val);
+			if (!i) {
+				Error("Missing/invalid arg at line %d\n", line);
+				break;
+			}
+			/* save the magic number */
+			prog->p.data[addr++] = token[wnum++].val;
+			/* and the color immediate */
+			if (token[wnum].is_num) {
+				prog->p.data[addr++] = token[wnum++].val;
+			} else {
+				Error("Missing/Invalid arg "
+				      "at line %d\n",
+				      line);
+				break;
+			}
+			break;
+		case SET_COLOR_RGB:
+			/* one magic word, then three more 8-bit args */
+			i = is_color_arg(token[wnum].word, 2, &token[wnum].val);
+			if (!i) {
+				Error("Missing/invalid arg at line %d\n", line);
+				break;
+			}
+			/* save the magic number */
+			prog->p.data[addr++] = token[wnum++].val;
+			/* and the color immediates */
+			for (i = 0; i < 3; i++) {
+				if (token[wnum].is_num) {
+					prog->p.data[addr++] =
+						token[wnum++].val;
+				} else {
+					Error("Missing/Invalid arg "
+					      "at line %d\n",
+					      line);
+					break;
+				}
+			}
+			break;
+
+		default:
+			/* No args needed */
+			break;
+		}
+
+		/* Did we run past the end? */
+		if (addr > EC_LB_PROG_LEN) {
+			Error("out of program space at line %d\n", line);
+			break;
+		}
+	}
+	if (ferror(fp))
+		Error("problem while reading input: %s\n", strerror(errno));
+
+	if (!hit_errors)
+		fixup_symbols(prog);
+
+	if (!hit_errors)
+		prog->p.size = addr;
+
+	if (!prog->p.size)
+		Error("input file produced no output bytes\n");
+}
+
+int main(int argc, char *argv[])
+{
+	struct safe_lightbar_program safe_prog;
+	int opt_decode = 0;
+	int c;
+	int errorcnt = 0;
+	const char *infile, *outfile;
+	FILE *ifp, *ofp;
+
+	char *progname = strrchr(argv[0], '/');
+	if (progname)
+		progname++;
+	else
+		progname = argv[0];
+
+	opterr = 0; /* quiet, you */
+	while ((c = getopt(argc, argv, ":dv")) != -1) {
+		switch (c) {
+		case 'd':
+			opt_decode = 1;
+			break;
+		case 'v':
+			opt_verbose = 1;
+			break;
+
+		case '?':
+			fprintf(stderr, "%s: unrecognized switch: -%c\n",
+				progname, optopt);
+			errorcnt++;
+			break;
+		case ':':
+			fprintf(stderr, "%s: missing argument to -%c\n",
+				progname, optopt);
+			errorcnt++;
+			break;
+		default:
+			errorcnt++;
+			break;
+		}
+	}
+
+	if (errorcnt) {
+		fprintf(stderr, usage, progname);
+		exit(1);
+	}
+
+	if (argc - optind > 0) {
+		infile = argv[optind];
+		ifp = fopen(infile, "rb");
+		if (!ifp) {
+			fprintf(stderr,
+				"%s: Unable to open %s for reading: %s\n",
+				progname, infile, strerror(errno));
+			exit(1);
+		}
+	} else {
+		infile = "stdin";
+		ifp = stdin;
+	}
+
+	if (argc - optind > 1) {
+		outfile = argv[optind + 1];
+		ofp = fopen(outfile, "wb");
+		if (!ofp) {
+			fprintf(stderr,
+				"%s: Unable to open %s for writing: %s\n",
+				progname, outfile, strerror(errno));
+			exit(1);
+		}
+	} else {
+		outfile = "stdout";
+		ofp = stdout;
+	}
+
+	if (opt_decode) {
+		read_binary(ifp, &safe_prog);
+		fclose(ifp);
+		if (hit_errors)
+			return 1;
+		fprintf(ofp, "# %s\n", infile);
+		disassemble_prog(ofp, &safe_prog);
+		fclose(ofp);
+	} else {
+		memset(&safe_prog, 0, sizeof(safe_prog));
+		compile(ifp, &safe_prog);
+		fclose(ifp);
+		if (!hit_errors) {
+			if (1 !=
+			    fwrite(safe_prog.p.data, safe_prog.p.size, 1, ofp))
+				Error("%s: Unable to write to %s: %s\n",
+				      progname, outfile, strerror(errno));
+			else
+				fprintf(stderr, "0x%02x bytes written to %s\n",
+					safe_prog.p.size, outfile);
+		}
+		fclose(ofp);
+	}
+
+	return hit_errors;
+}
diff --git a/util/lbplay.c b/util/lbplay.c
deleted file mode 100644
index 9ab0564b74..0000000000
--- a/util/lbplay.c
+++ /dev/null
@@ -1,165 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <errno.h>
-#include <fcntl.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <string.h>
-#include <strings.h>
-#include <sys/file.h>
-#include <sys/stat.h>
-#include <sys/types.h>
-#include <unistd.h>
-
-#define LIGHTBAR "/sys/devices/virtual/chromeos/cros_ec/lightbar"
-
-int main(int argc, char **argv)
-{
-	int major, minor, fd_v;
-	int i, tries, fd_s, fd_l;
-	char buf[80];
-	int ret = 1;
-
-	/* Check version */
-	fd_v = open(LIGHTBAR "/version", O_RDONLY);
-	if (fd_v < 0) {
-		perror("can't open version file");
-		goto out;
-	}
-	ret = read(fd_v, buf, sizeof(buf) - 1);
-	if (ret <= 0) {
-		perror("can't read version");
-		close(fd_v);
-		goto out;
-	}
-	buf[ret] = '\0';
-	close(fd_v);
-
-	errno = 0;
-	/* Expect "MAJOR MINOR" */
-	if (2 != sscanf(buf, "%d %d", &major, &minor)) {
-		if (errno)
-			perror("can't parse version string");
-		else
-			fprintf(stderr, "can't parse version string\n");
-		goto out;
-	}
-	/* Pixel is "0 0". Minor change will be compatible, Major may not */
-	if (major != 0) {
-		fprintf(stderr, "Don't know how to handle version %d.%d\n",
-			major, minor);
-		goto out;
-	}
-
-	/* Take over lightbar sequencing. */
-	fd_s = open(LIGHTBAR "/sequence", O_RDWR | O_SYNC);
-	if (fd_s < 0) {
-		perror("can't open sequence control");
-		goto out;
-	}
-
-	/* NOTE: Cooperative locking only. Rude programs may not play nice. */
-	if (flock(fd_s, LOCK_EX | LOCK_NB) < 0) {
-		perror("can't lock sequence control");
-		goto out_close;
-	}
-
-	/*
-	 * If power events are changing the sequence our request to stop may
-	 * be missed, so try a few times before giving up.
-	 *
-	 * Note that every write to a control file should be prefaced with an
-	 * lseek() to the beginning. sysfs files don't work quite like normal
-	 * files.
-	 */
-	tries = 3;
-	while (1) {
-		lseek(fd_s, 0, SEEK_SET);
-		if (read(fd_s, buf, sizeof(buf)) <= 0) {
-			perror("can't read sequence control");
-			goto out_unlock;
-		}
-
-		if (!strncasecmp(buf, "stop", 4))
-			break;
-
-		if (!tries--) {
-			fprintf(stderr, "couldn't get EC to stop\n");
-			goto out_unlock;
-		}
-
-		lseek(fd_s, 0, SEEK_SET);
-		strcpy(buf, "stop");
-		if (write(fd_s, buf, strlen(buf) + 1) <= 0) {
-			perror("can't write sequence control");
-			goto out_unlock;
-		}
-	}
-
-	/* Turn the brightness all the way up */
-	fd_l = open(LIGHTBAR "/brightness", O_WRONLY | O_SYNC);
-	if (fd_l < 0) {
-		perror("can't open brightness control");
-		goto out_run;
-	}
-	strcpy(buf, "255");
-	if (write(fd_l, buf, strlen(buf) + 1) < 0) {
-		perror("can't write brightness control");
-		goto out_led;
-	}
-	close(fd_l);
-
-	/* Now let's drive the colors. */
-	fd_l = open(LIGHTBAR "/led_rgb", O_WRONLY | O_SYNC);
-	if (fd_l < 0) {
-		perror("can't open led control");
-		goto out_run;
-	}
-
-	/* Cycle through some colors. We can update multiple LEDs at once,
-	 * but there's a limit on how often we can send commands to the
-	 * lightbar. Going too fast will block, although buffering combined
-	 * with lseek() may just cause data to be lost. Read "/interval_msec"
-	 * to see what the limit is. The default is 50msec (20Hz).
-	 */
-	for (i = 0; i < 256; i += 4) {
-		sprintf(buf, "0 %d %d %d 1 %d %d %d 2 %d %d %d 3 %d %d %d",
-			i, 0, 0,
-			0, 0, i,
-			255-i, 255, 0,
-			0, 255, 255-i);
-		lseek(fd_l, 0, SEEK_SET);
-		if (write(fd_l, buf, strlen(buf) + 1) < 0)
-			perror("write to led control");
-
-		usleep(100000);
-	}
-
-	/* all white */
-	strcpy(buf, "4 255 255 255");
-	lseek(fd_l, 0, SEEK_SET);
-	if (write(fd_l, buf, strlen(buf) + 1) < 0)
-		perror("write to led control");
-
-	usleep(400000);
-
-	/* Done. */
-	ret = 0;
-out_led:
-	close(fd_l);
-out_run:
-	/* Let EC drive lightbar again */
-	strcpy(buf, "run");
-	lseek(fd_s, 0, SEEK_SET);
-	if (write(fd_s, buf, strlen(buf) + 1) < 0)
-		perror("write to sequence control");
-out_unlock:
-	flock(fd_s, LOCK_UN);
-out_close:
-	close(fd_s);
-out:
-	return ret;
-}
diff --git a/util/lbplay.cc b/util/lbplay.cc
new file mode 100644
index 0000000000..f8a510d664
--- /dev/null
+++ b/util/lbplay.cc
@@ -0,0 +1,163 @@
+/* Copyright 2014 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <errno.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+
+#include <fcntl.h>
+#include <strings.h>
+#include <sys/file.h>
+#include <sys/stat.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+#define LIGHTBAR "/sys/devices/virtual/chromeos/cros_ec/lightbar"
+
+int main(int argc, char **argv)
+{
+	int major, minor, fd_v;
+	int i, tries, fd_s, fd_l;
+	char buf[80];
+	int ret = 1;
+
+	/* Check version */
+	fd_v = open(LIGHTBAR "/version", O_RDONLY);
+	if (fd_v < 0) {
+		perror("can't open version file");
+		goto out;
+	}
+	ret = read(fd_v, buf, sizeof(buf) - 1);
+	if (ret <= 0) {
+		perror("can't read version");
+		close(fd_v);
+		goto out;
+	}
+	buf[ret] = '\0';
+	close(fd_v);
+
+	errno = 0;
+	/* Expect "MAJOR MINOR" */
+	if (2 != sscanf(buf, "%d %d", &major, &minor)) {
+		if (errno)
+			perror("can't parse version string");
+		else
+			fprintf(stderr, "can't parse version string\n");
+		goto out;
+	}
+	/* Pixel is "0 0". Minor change will be compatible, Major may not */
+	if (major != 0) {
+		fprintf(stderr, "Don't know how to handle version %d.%d\n",
+			major, minor);
+		goto out;
+	}
+
+	/* Take over lightbar sequencing. */
+	fd_s = open(LIGHTBAR "/sequence", O_RDWR | O_SYNC);
+	if (fd_s < 0) {
+		perror("can't open sequence control");
+		goto out;
+	}
+
+	/* NOTE: Cooperative locking only. Rude programs may not play nice. */
+	if (flock(fd_s, LOCK_EX | LOCK_NB) < 0) {
+		perror("can't lock sequence control");
+		goto out_close;
+	}
+
+	/*
+	 * If power events are changing the sequence our request to stop may
+	 * be missed, so try a few times before giving up.
+	 *
+	 * Note that every write to a control file should be prefaced with an
+	 * lseek() to the beginning. sysfs files don't work quite like normal
+	 * files.
+	 */
+	tries = 3;
+	while (1) {
+		lseek(fd_s, 0, SEEK_SET);
+		if (read(fd_s, buf, sizeof(buf)) <= 0) {
+			perror("can't read sequence control");
+			goto out_unlock;
+		}
+
+		if (!strncasecmp(buf, "stop", 4))
+			break;
+
+		if (!tries--) {
+			fprintf(stderr, "couldn't get EC to stop\n");
+			goto out_unlock;
+		}
+
+		lseek(fd_s, 0, SEEK_SET);
+		strcpy(buf, "stop");
+		if (write(fd_s, buf, strlen(buf) + 1) <= 0) {
+			perror("can't write sequence control");
+			goto out_unlock;
+		}
+	}
+
+	/* Turn the brightness all the way up */
+	fd_l = open(LIGHTBAR "/brightness", O_WRONLY | O_SYNC);
+	if (fd_l < 0) {
+		perror("can't open brightness control");
+		goto out_run;
+	}
+	strcpy(buf, "255");
+	if (write(fd_l, buf, strlen(buf) + 1) < 0) {
+		perror("can't write brightness control");
+		goto out_led;
+	}
+	close(fd_l);
+
+	/* Now let's drive the colors. */
+	fd_l = open(LIGHTBAR "/led_rgb", O_WRONLY | O_SYNC);
+	if (fd_l < 0) {
+		perror("can't open led control");
+		goto out_run;
+	}
+
+	/* Cycle through some colors. We can update multiple LEDs at once,
+	 * but there's a limit on how often we can send commands to the
+	 * lightbar. Going too fast will block, although buffering combined
+	 * with lseek() may just cause data to be lost. Read "/interval_msec"
+	 * to see what the limit is. The default is 50msec (20Hz).
+	 */
+	for (i = 0; i < 256; i += 4) {
+		sprintf(buf, "0 %d %d %d 1 %d %d %d 2 %d %d %d 3 %d %d %d", i,
+			0, 0, 0, 0, i, 255 - i, 255, 0, 0, 255, 255 - i);
+		lseek(fd_l, 0, SEEK_SET);
+		if (write(fd_l, buf, strlen(buf) + 1) < 0)
+			perror("write to led control");
+
+		usleep(100000);
+	}
+
+	/* all white */
+	strcpy(buf, "4 255 255 255");
+	lseek(fd_l, 0, SEEK_SET);
+	if (write(fd_l, buf, strlen(buf) + 1) < 0)
+		perror("write to led control");
+
+	usleep(400000);
+
+	/* Done. */
+	ret = 0;
+out_led:
+	close(fd_l);
+out_run:
+	/* Let EC drive lightbar again */
+	strcpy(buf, "run");
+	lseek(fd_s, 0, SEEK_SET);
+	if (write(fd_s, buf, strlen(buf) + 1) < 0)
+		perror("write to sequence control");
+out_unlock:
+	flock(fd_s, LOCK_UN);
+out_close:
+	close(fd_s);
+out:
+	return ret;
+}
diff --git a/util/lcov_stencil.py b/util/lcov_stencil.py
new file mode 100755
index 0000000000..ba08f0ccaa
--- /dev/null
+++ b/util/lcov_stencil.py
@@ -0,0 +1,231 @@
+#!/usr/bin/env python3
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Merge lcov files, discarding all lines that are not in the template file.
+
+Given 2 or more lcov files, merge the results only for the lines present in
+the template file.
+
+File format reverse engineered from
+https://github.com/linux-test-project/lcov/blob/master/bin/geninfo
+"""
+
+import argparse
+from collections import defaultdict
+import logging
+import re
+import sys
+from typing import Dict, Set
+
+
+EXTRACT_LINE = re.compile(r"^(FN|DA|BRDA):(\d+),")
+EXTRACT_FN = re.compile(r"^(FN):(\d+),(\S+)")
+EXTRACT_FNDA = re.compile(r"^(FNDA):(\d+),(\S+)")
+EXTRACT_DA = re.compile(r"^(DA):(\d+),(\d+)")
+EXTRACT_BRDA = re.compile(r"^(BRDA):(\d+),(\d+),(\d+),([-\d]+)")
+EXTRACT_COUNT = re.compile(r"^([A-Z]+):(\d+)")
+
+
+def parse_args(argv=None):
+    """Parses command line args"""
+    parser = argparse.ArgumentParser()
+    parser.add_argument(
+        "--log-level",
+        choices=[
+            "CRITICAL",
+            "ERROR",
+            "WARNING",
+            "INFO",
+            "DEBUG",
+        ],
+        default="INFO",
+        help="Set logging level to report at.",
+    )
+    parser.add_argument(
+        "--output-file",
+        "-o",
+        help="destination filename, defaults to stdout",
+    )
+    parser.add_argument(
+        "template_file",
+        help="lcov info file to use as template",
+    )
+    parser.add_argument(
+        "lcov_input",
+        nargs="+",
+        help="lcov info file to merge",
+    )
+    return parser.parse_args(argv)
+
+
+def parse_template_file(filename) -> Dict[str, Set[str]]:
+    """Reads the template file and returns covered lines.
+
+    Reads the lines that indicate covered line numbers (FN, DA, and BRDA)
+    and adds them to the returned data structure.
+
+    Returns
+    -------
+    Dict[str, Set[str]]
+        A dictionary of filename to set of covered line numbers (as strings)
+    """
+    logging.info("Reading template file %s", filename)
+    with open(filename, "r") as template_file:
+        data_by_path: Dict[str, Set[str]] = defaultdict(set)
+        file_name = None
+        for line in template_file.readlines():
+            line = line.strip()
+            if line == "end_of_record":
+                file_name = None
+            elif (
+                line.startswith(  # pylint:disable=too-many-boolean-expressions
+                    "TN:"
+                )
+                or line.startswith("FNDA:")
+                or line.startswith("FNF:")
+                or line.startswith("FNH:")
+                or line.startswith("BRF:")
+                or line.startswith("BRH:")
+                or line.startswith("LF:")
+                or line.startswith("LH:")
+            ):
+                pass
+            elif line.startswith("SF:"):
+                file_name = line
+            else:
+                match = EXTRACT_LINE.match(line)
+                if file_name and match:
+                    data_by_path[file_name].add(match.group(2))
+                else:
+                    raise NotImplementedError(line)
+        return data_by_path
+
+
+def filter_coverage_file(filename, output_file, data_by_path):
+    """Reads a coverage file from filename and writes filtered lines to
+    output_file.
+
+    For each line in filename, if it covers the same lines as the template
+    in data_by_path, then write the line to output_file.
+
+    Directives that act as totals (FNF, FNH, BRF, BRH, LF, LH) are recalculated
+    after filtering, and records that refer to unknown files are omitted.
+    """
+    logging.info("Merging file %s", filename)
+    with open(filename, "r") as input_file:
+
+        def empty_record():
+            return {
+                "text": "",
+                "function_names": set(),
+            }
+
+        record = empty_record()
+        for line in input_file.readlines():
+            line = line.strip()
+            if line == "end_of_record":
+                record["text"] += line + "\n"
+                if record.get("should_write_record", False):
+                    output_file.write(record["text"])
+                else:
+                    logging.debug("Omitting record %s", record["text"])
+                record = empty_record()
+            elif line.startswith("SF:"):
+                record["file_name"] = line
+                record["text"] += line + "\n"
+            elif line.startswith("TN:"):
+                record["text"] += line + "\n"
+            elif line.startswith("FN:"):
+                match = EXTRACT_FN.match(line)
+                if (
+                    match
+                    and match.group(2) in data_by_path[record["file_name"]]
+                ):
+                    record["text"] += line + "\n"
+                    record["functions_found"] = (
+                        record.get("functions_found", 0) + 1
+                    )
+                    record["should_write_record"] = True
+                    record["function_names"].add(match.group(3))
+                else:
+                    logging.debug("Omitting %s", line)
+            elif line.startswith("FNDA:"):
+                match = EXTRACT_FNDA.match(line)
+                if match and match.group(3) in record["function_names"]:
+                    record["text"] += line + "\n"
+                    record["should_write_record"] = True
+                    if match.group(2) != "0":
+                        record["functions_hit"] = (
+                            record.get("functions_hit", 0) + 1
+                        )
+                else:
+                    logging.debug("Omitting %s", line)
+            elif line.startswith("DA:"):
+                match = EXTRACT_DA.match(line)
+                if (
+                    match
+                    and match.group(2) in data_by_path[record["file_name"]]
+                ):
+                    record["text"] += line + "\n"
+                    record["lines_found"] = record.get("lines_found", 0) + 1
+                    record["should_write_record"] = True
+                    if match.group(3) != "0":
+                        record["lines_hit"] = record.get("lines_hit", 0) + 1
+                else:
+                    logging.debug("Omitting %s", line)
+            elif line.startswith("BRDA:"):
+                match = EXTRACT_BRDA.match(line)
+                if (
+                    match
+                    and match.group(2) in data_by_path[record["file_name"]]
+                ):
+                    record["text"] += line + "\n"
+                    record["branches_found"] = (
+                        record.get("branches_found", 0) + 1
+                    )
+                    record["should_write_record"] = True
+                    if match.group(4) != "-" and match.group(4) != "0":
+                        record["branches_hit"] = (
+                            record.get("branches_hit", 0) + 1
+                        )
+                else:
+                    logging.debug("Omitting %s", line)
+            elif line.startswith("FNF:"):
+                record["text"] += "FNF:%s\n" % record.get("functions_found", 0)
+            elif line.startswith("FNH:"):
+                record["text"] += "FNH:%s\n" % record.get("functions_hit", 0)
+            elif line.startswith("BRF:"):
+                record["text"] += "BRF:%s\n" % record.get("branches_found", 0)
+            elif line.startswith("BRH:"):
+                record["text"] += "BRH:%s\n" % record.get("branches_hit", 0)
+            elif line.startswith("LF:"):
+                record["text"] += "LF:%s\n" % record.get("lines_found", 0)
+            elif line.startswith("LH:"):
+                record["text"] += "LH:%s\n" % record.get("lines_hit", 0)
+            else:
+                logging.debug("record = %s", record)
+                raise NotImplementedError(line)
+
+
+def main(argv=None):
+    """Merges lcov files."""
+    opts = parse_args(argv)
+    logging.basicConfig(level=opts.log_level)
+
+    output_file = sys.stdout
+    if opts.output_file:
+        logging.info("Writing output to %s", opts.output_file)
+        output_file = open(  # pylint:disable=consider-using-with
+            opts.output_file, "w"
+        )
+
+    data_by_path = parse_template_file(opts.template_file)
+    with output_file:
+        for lcov_input in [opts.template_file] + opts.lcov_input:
+            filter_coverage_file(lcov_input, output_file, data_by_path)
+
+
+if __name__ == "__main__":
+    sys.exit(main(sys.argv[1:]))
diff --git a/util/linux_ec_commands_h_check.sh b/util/linux_ec_commands_h_check.sh
index 4c55faca0a..e10687e980 100755
--- a/util/linux_ec_commands_h_check.sh
+++ b/util/linux_ec_commands_h_check.sh
@@ -1,11 +1,13 @@
 #!/bin/bash
 #
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 set -e
 
+: "${ZEPHYR_BASE:=$(realpath ../../../src/third_party/zephyr/main)}"
+
 ec_commands_file_in="include/ec_commands.h"
 ec_commands_file_out="build/kernel/include/linux/mfd/cros_ec_commands.h"
 
@@ -23,3 +25,5 @@ if [ "${ec_commands_file_out}" -ot "${ec_commands_file_in}" ]; then
   echo 'Please run "make buildall" or "make build_cros_ec_commands"'.
   exit 1
 fi
+
+"${ZEPHYR_BASE}/scripts/checkpatch.pl" -f "${ec_commands_file_out}"
diff --git a/util/llvm-gcov.sh b/util/llvm-gcov.sh
new file mode 100755
index 0000000000..826a901134
--- /dev/null
+++ b/util/llvm-gcov.sh
@@ -0,0 +1,7 @@
+#!/bin/bash
+#
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+exec llvm-cov gcov "$@"
diff --git a/util/lock/android.c b/util/lock/android.c
deleted file mode 100644
index 8472b6db68..0000000000
--- a/util/lock/android.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright 2016, Google Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- *    * Redistributions of source code must retain the above copyright
- *      notice, this list of conditions and the following disclaimer.
- *    * Redistributions in binary form must reproduce the above
- *      copyright notice, this list of conditions and the following
- *      disclaimer in the documentation and/or other materials provided
- *      with the distribution.
- *    * Neither the name of Google Inc. nor the names of its
- *      contributors may be used to endorse or promote products derived
- *      from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Alternatively, this software may be distributed under the terms of the
- * GNU General Public License ("GPL") version 2 as published by the Free
- * Software Foundation.
- */
-
-#include <stdlib.h>
-
-#include "android.h"
-
-int in_android(void)
-{
-	if (getenv("ANDROID_ROOT"))
-		return 1;
-
-	return 0;
-}
-
-char *android_tmpdir_path(void)
-{
-	return getenv("TMPDIR");
-}
diff --git a/util/lock/android.cc b/util/lock/android.cc
new file mode 100644
index 0000000000..2ba47a04d2
--- /dev/null
+++ b/util/lock/android.cc
@@ -0,0 +1,21 @@
+/* Copyright 2016 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "android.h"
+
+#include <stdlib.h>
+
+int in_android(void)
+{
+	if (getenv("ANDROID_ROOT"))
+		return 1;
+
+	return 0;
+}
+
+char *android_tmpdir_path(void)
+{
+	return getenv("TMPDIR");
+}
diff --git a/util/lock/android.h b/util/lock/android.h
index bb08486919..cad45326da 100644
--- a/util/lock/android.h
+++ b/util/lock/android.h
@@ -1,36 +1,6 @@
-/*
- * Copyright 2016, Google Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- *    * Redistributions of source code must retain the above copyright
- *      notice, this list of conditions and the following disclaimer.
- *    * Redistributions in binary form must reproduce the above
- *      copyright notice, this list of conditions and the following
- *      disclaimer in the documentation and/or other materials provided
- *      with the distribution.
- *    * Neither the name of Google Inc. nor the names of its
- *      contributors may be used to endorse or promote products derived
- *      from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Alternatively, this software may be distributed under the terms of the
- * GNU General Public License ("GPL") version 2 as published by the Free
- * Software Foundation.
+/* Copyright 2016 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
  */
 
 #ifndef ANDROID_H__
diff --git a/util/lock/build.mk b/util/lock/build.mk
index 65a63ab9db..ea9bf9bf04 100644
--- a/util/lock/build.mk
+++ b/util/lock/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2012 The Chromium OS Authors. All rights reserved.
+# Copyright 2012 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/util/lock/file_lock.c b/util/lock/file_lock.c
deleted file mode 100644
index 36b420d287..0000000000
--- a/util/lock/file_lock.c
+++ /dev/null
@@ -1,262 +0,0 @@
-/* Copyright 2016, Google Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- *    * Redistributions of source code must retain the above copyright
- *      notice, this list of conditions and the following disclaimer.
- *    * Redistributions in binary form must reproduce the above
- *      copyright notice, this list of conditions and the following
- *      disclaimer in the documentation and/or other materials provided
- *      with the distribution.
- *    * Neither the name of Google Inc. nor the names of its
- *      contributors may be used to endorse or promote products derived
- *      from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Alternatively, this software may be distributed under the terms of the
- * GNU General Public License ("GPL") version 2 as published by the Free
- * Software Foundation.
- *
- * file_lock.c: Implementation for a binary semaphore using a file lock.
- *
- * Warning: This relies on flock() which is known to be broken on NFS.
- *
- * The file will remain persistent once the lock has been used. Unfortunately,
- * unlinking the file can introduce a race condition so we leave the file
- * in place.
- *
- * The current process's PID will be written to the file for debug purposes.
- */
-
-#include <errno.h>
-#include <fcntl.h>
-#include <inttypes.h>
-#include <limits.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <time.h>
-#include <unistd.h>
-#include <sys/file.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-
-#include "android.h"
-#include "ipc_lock.h"
-#include "locks.h"
-
-#define SLEEP_INTERVAL_MS	50
-
-static void msecs_to_timespec(int msecs, struct timespec *tmspec)
-{
-	tmspec->tv_sec = msecs / 1000;
-	tmspec->tv_nsec = (msecs % 1000) * 1000 * 1000;
-}
-
-static int lock_is_held(struct ipc_lock *lock)
-{
-	return lock->is_held;
-}
-
-static int test_dir(const char *path)
-{
-	struct stat s;
-
-	if (lstat(path, &s) < 0) {
-		fprintf(stderr, "Cannot stat %s.\n", path);
-		return -1;
-	}
-
-	if (!S_ISDIR(s.st_mode)) {
-		fprintf(stderr, "%s is not a directory.\n", path);
-		return -1;
-	}
-
-	return 0;
-}
-
-static int file_lock_open_or_create(struct ipc_lock *lock)
-{
-	char path[PATH_MAX];
-
-	if (in_android()) {
-		char *tmpdir;
-
-		tmpdir = android_tmpdir_path();
-		if (!tmpdir)
-			return -1;
-
-		if (snprintf(path, sizeof(path), "%s/%s",
-				tmpdir, lock->filename) < 0) {
-			return -1;
-		}
-	} else {
-		const char *dir = SYSTEM_LOCKFILE_DIR;
-		const char fallback[] = "/tmp";
-
-		if (test_dir(dir)) {
-			dir = fallback;
-			fprintf(stderr, "Trying fallback directory: %s\n", dir);
-			if (test_dir(dir))
-				return -1;
-		}
-
-		if (snprintf(path, sizeof(path),
-			"%s/%s", dir, lock->filename) < 0)
-			return -1;
-
-	}
-
-	lock->fd = open(path, O_RDWR | O_CREAT, 0600);
-	if (lock->fd < 0) {
-		fprintf(stderr, "Cannot open lockfile %s", path);
-		return -1;
-	}
-
-	return 0;
-}
-
-static int file_lock_get(struct ipc_lock *lock, int timeout_msecs)
-{
-	int msecs_remaining = timeout_msecs;
-	struct timespec sleep_interval, rem;
-	int ret = -1;
-
-	if (timeout_msecs == 0)
-		return flock(lock->fd, LOCK_EX | LOCK_NB);
-
-	msecs_to_timespec(SLEEP_INTERVAL_MS, &sleep_interval);
-
-	while ((ret = flock(lock->fd, LOCK_EX | LOCK_NB)) != 0) {
-		if (errno != EWOULDBLOCK) {
-			fprintf(stderr, "Error obtaining lock");
-			return -1;
-		}
-
-		if (msecs_remaining < SLEEP_INTERVAL_MS)
-			msecs_to_timespec(msecs_remaining, &sleep_interval);
-
-		while (nanosleep(&sleep_interval, &rem) != 0) {
-			if (errno == EINTR) {
-				sleep_interval = rem;
-				continue;
-			} else {
-				fprintf(stderr, "nanosleep() failed");
-				return ret;
-			}
-		}
-
-		if (timeout_msecs < 0)
-			continue;
-
-		msecs_remaining -= SLEEP_INTERVAL_MS;
-		if (msecs_remaining < 0)
-			break;
-	}
-
-	if (ret != 0) {
-		fprintf(stderr, "Timed out waiting for file lock.\n");
-		return -1;
-	}
-
-	return 0;
-}
-
-static int file_lock_write_pid(struct ipc_lock *lock)
-{
-	ssize_t len;
-	/*
-         * PIDs are usually 5 digits, but we'll reserve enough room for
-	 * a value of 2^32 (10 digits) out of paranoia.
-         */
-	char pid_str[11];
-
-	if (ftruncate(lock->fd, 0) < 0) {
-		fprintf(stderr, "Cannot truncate lockfile");
-		return -1;
-	}
-
-	snprintf(pid_str, sizeof(pid_str), "%lu", (unsigned long)getpid());
-	len = write(lock->fd, pid_str, strlen(pid_str));
-	if (len < 0) {
-		fprintf(stderr, "Cannot write PID to lockfile");
-		return -1;
-	}
-
-	return 0;
-}
-
-static void file_lock_release(struct ipc_lock *lock)
-{
-	if (flock(lock->fd, LOCK_UN) < 0)
-		fprintf(stderr, "Cannot release lock");
-
-	if (close(lock->fd) < 0)
-		fprintf(stderr, "Cannot close lockfile");
-}
-
-/*
- * timeout <0 = no timeout (try forever)
- * timeout 0  = do not wait (return immediately)
- * timeout >0 = wait up to $timeout milliseconds
- *
- * returns 0 to indicate lock acquired
- * returns >0 to indicate lock was already held
- * returns <0 to indicate failed to acquire lock
- */
-int acquire_lock(struct ipc_lock *lock, int timeout_msecs)
-{
-	/* check if it is already held */
-	if (lock_is_held(lock))
-		return 1;
-
-	if (file_lock_open_or_create(lock))
-		return -1;
-
-	if (file_lock_get(lock, timeout_msecs)) {
-		lock->is_held = 0;
-		close(lock->fd);
-		return -1;
-	} else {
-		lock->is_held = 1;
-	}
-
-	/*
-	 * Write PID to lockfile for debug purposes. Failure to write to
-	 * the file should not be considered fatal. There might be something
-	 * bad happening with the filesystem, but the lock has already been
-	 * obtained and we may need our tools for diagnostics and repairs
-	 * so we should continue anyway.
-	 */
-	file_lock_write_pid(lock);
-	return 0;
-}
-
-/*
- * returns 0 if lock was released successfully
- * returns -1 if lock had not been held before the call
- */
-int release_lock(struct ipc_lock *lock)
-{
-	if (lock_is_held(lock)) {
-		file_lock_release(lock);
-		lock->is_held = 0;
-		return 0;
-	}
-
-	return -1;
-}
diff --git a/util/lock/file_lock.cc b/util/lock/file_lock.cc
new file mode 100644
index 0000000000..7c7de880a6
--- /dev/null
+++ b/util/lock/file_lock.cc
@@ -0,0 +1,235 @@
+/* Copyright 2016 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * file_lock.c: Implementation for a binary semaphore using a file lock.
+ *
+ * Warning: This relies on flock() which is known to be broken on NFS.
+ *
+ * The file will remain persistent once the lock has been used. Unfortunately,
+ * unlinking the file can introduce a race condition so we leave the file
+ * in place.
+ *
+ * The current process's PID will be written to the file for debug purposes.
+ */
+
+#include "android.h"
+#include "ipc_lock.h"
+#include "locks.h"
+
+#include <errno.h>
+#include <inttypes.h>
+#include <limits.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <time.h>
+
+#include <fcntl.h>
+#include <sys/file.h>
+#include <sys/stat.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+#define SLEEP_INTERVAL_MS 50
+
+static void msecs_to_timespec(int msecs, struct timespec *tmspec)
+{
+	tmspec->tv_sec = msecs / 1000;
+	tmspec->tv_nsec = (msecs % 1000) * 1000 * 1000;
+}
+
+static int lock_is_held(struct ipc_lock *lock)
+{
+	return lock->is_held;
+}
+
+static int test_dir(const char *path)
+{
+	struct stat s;
+
+	if (lstat(path, &s) < 0) {
+		fprintf(stderr, "Cannot stat %s.\n", path);
+		return -1;
+	}
+
+	if (!S_ISDIR(s.st_mode)) {
+		fprintf(stderr, "%s is not a directory.\n", path);
+		return -1;
+	}
+
+	return 0;
+}
+
+static int file_lock_open_or_create(struct ipc_lock *lock)
+{
+	char path[PATH_MAX];
+
+	if (in_android()) {
+		char *tmpdir;
+
+		tmpdir = android_tmpdir_path();
+		if (!tmpdir)
+			return -1;
+
+		if (snprintf(path, sizeof(path), "%s/%s", tmpdir,
+			     lock->filename) < 0) {
+			return -1;
+		}
+	} else {
+		const char *dir = SYSTEM_LOCKFILE_DIR;
+		const char fallback[] = "/tmp";
+
+		if (test_dir(dir)) {
+			dir = fallback;
+			fprintf(stderr, "Trying fallback directory: %s\n", dir);
+			if (test_dir(dir))
+				return -1;
+		}
+
+		if (snprintf(path, sizeof(path), "%s/%s", dir, lock->filename) <
+		    0)
+			return -1;
+	}
+
+	lock->fd = open(path, O_RDWR | O_CREAT, 0600);
+	if (lock->fd < 0) {
+		fprintf(stderr, "Cannot open lockfile %s", path);
+		return -1;
+	}
+
+	return 0;
+}
+
+static int file_lock_get(struct ipc_lock *lock, int timeout_msecs)
+{
+	int msecs_remaining = timeout_msecs;
+	struct timespec sleep_interval, rem;
+	int ret = -1;
+
+	if (timeout_msecs == 0)
+		return flock(lock->fd, LOCK_EX | LOCK_NB);
+
+	msecs_to_timespec(SLEEP_INTERVAL_MS, &sleep_interval);
+
+	while ((ret = flock(lock->fd, LOCK_EX | LOCK_NB)) != 0) {
+		if (errno != EWOULDBLOCK) {
+			fprintf(stderr, "Error obtaining lock");
+			return -1;
+		}
+
+		if (msecs_remaining < SLEEP_INTERVAL_MS)
+			msecs_to_timespec(msecs_remaining, &sleep_interval);
+
+		while (nanosleep(&sleep_interval, &rem) != 0) {
+			if (errno == EINTR) {
+				sleep_interval = rem;
+				continue;
+			} else {
+				fprintf(stderr, "nanosleep() failed");
+				return ret;
+			}
+		}
+
+		if (timeout_msecs < 0)
+			continue;
+
+		msecs_remaining -= SLEEP_INTERVAL_MS;
+		if (msecs_remaining < 0)
+			break;
+	}
+
+	if (ret != 0) {
+		fprintf(stderr, "Timed out waiting for file lock.\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+static int file_lock_write_pid(struct ipc_lock *lock)
+{
+	ssize_t len;
+	/*
+	 * PIDs are usually 5 digits, but we'll reserve enough room for
+	 * a value of 2^32 (10 digits) out of paranoia.
+	 */
+	char pid_str[11];
+
+	if (ftruncate(lock->fd, 0) < 0) {
+		fprintf(stderr, "Cannot truncate lockfile");
+		return -1;
+	}
+
+	snprintf(pid_str, sizeof(pid_str), "%lu", (unsigned long)getpid());
+	len = write(lock->fd, pid_str, strlen(pid_str));
+	if (len < 0) {
+		fprintf(stderr, "Cannot write PID to lockfile");
+		return -1;
+	}
+
+	return 0;
+}
+
+static void file_lock_release(struct ipc_lock *lock)
+{
+	if (flock(lock->fd, LOCK_UN) < 0)
+		fprintf(stderr, "Cannot release lock");
+
+	if (close(lock->fd) < 0)
+		fprintf(stderr, "Cannot close lockfile");
+}
+
+/*
+ * timeout <0 = no timeout (try forever)
+ * timeout 0  = do not wait (return immediately)
+ * timeout >0 = wait up to $timeout milliseconds
+ *
+ * returns 0 to indicate lock acquired
+ * returns >0 to indicate lock was already held
+ * returns <0 to indicate failed to acquire lock
+ */
+int acquire_lock(struct ipc_lock *lock, int timeout_msecs)
+{
+	/* check if it is already held */
+	if (lock_is_held(lock))
+		return 1;
+
+	if (file_lock_open_or_create(lock))
+		return -1;
+
+	if (file_lock_get(lock, timeout_msecs)) {
+		lock->is_held = 0;
+		close(lock->fd);
+		return -1;
+	} else {
+		lock->is_held = 1;
+	}
+
+	/*
+	 * Write PID to lockfile for debug purposes. Failure to write to
+	 * the file should not be considered fatal. There might be something
+	 * bad happening with the filesystem, but the lock has already been
+	 * obtained and we may need our tools for diagnostics and repairs
+	 * so we should continue anyway.
+	 */
+	file_lock_write_pid(lock);
+	return 0;
+}
+
+/*
+ * returns 0 if lock was released successfully
+ * returns -1 if lock had not been held before the call
+ */
+int release_lock(struct ipc_lock *lock)
+{
+	if (lock_is_held(lock)) {
+		file_lock_release(lock);
+		lock->is_held = 0;
+		return 0;
+	}
+
+	return -1;
+}
diff --git a/util/lock/gec_lock.c b/util/lock/gec_lock.c
deleted file mode 100644
index d354ea08f3..0000000000
--- a/util/lock/gec_lock.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/* Copyright 2012, Google Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- *    * Redistributions of source code must retain the above copyright
- *      notice, this list of conditions and the following disclaimer.
- *    * Redistributions in binary form must reproduce the above
- *      copyright notice, this list of conditions and the following
- *      disclaimer in the documentation and/or other materials provided
- *      with the distribution.
- *    * Neither the name of Google Inc. nor the names of its
- *      contributors may be used to endorse or promote products derived
- *      from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "gec_lock.h"
-#include "ipc_lock.h"
-#include "locks.h"
-
-static struct ipc_lock gec_lock = LOCKFILE_INIT(CROS_EC_LOCKFILE_NAME);
-
-int acquire_gec_lock(int timeout_secs)
-{
-	return acquire_lock(&gec_lock, timeout_secs * 1000);
-}
-
-int release_gec_lock(void)
-{
-	return release_lock(&gec_lock);
-}
diff --git a/util/lock/gec_lock.cc b/util/lock/gec_lock.cc
new file mode 100644
index 0000000000..e46be17fcb
--- /dev/null
+++ b/util/lock/gec_lock.cc
@@ -0,0 +1,20 @@
+/* Copyright 2012 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "gec_lock.h"
+#include "ipc_lock.h"
+#include "locks.h"
+
+static struct ipc_lock gec_lock = LOCKFILE_INIT(CROS_EC_LOCKFILE_NAME);
+
+int acquire_gec_lock(int timeout_secs)
+{
+	return acquire_lock(&gec_lock, timeout_secs * 1000);
+}
+
+int release_gec_lock(void)
+{
+	return release_lock(&gec_lock);
+}
diff --git a/util/lock/gec_lock.h b/util/lock/gec_lock.h
index 8480700ddd..1758ad57c1 100644
--- a/util/lock/gec_lock.h
+++ b/util/lock/gec_lock.h
@@ -1,31 +1,6 @@
-/* Copyright 2012, Google Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- *    * Redistributions of source code must retain the above copyright
- *      notice, this list of conditions and the following disclaimer.
- *    * Redistributions in binary form must reproduce the above
- *      copyright notice, this list of conditions and the following
- *      disclaimer in the documentation and/or other materials provided
- *      with the distribution.
- *    * Neither the name of Google Inc. nor the names of its
- *      contributors may be used to endorse or promote products derived
- *      from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+/* Copyright 2012 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
  */
 
 #ifndef __UTIL_GEC_LOCK_H
diff --git a/util/lock/ipc_lock.h b/util/lock/ipc_lock.h
index ca739ac04e..21873f4d42 100644
--- a/util/lock/ipc_lock.h
+++ b/util/lock/ipc_lock.h
@@ -1,48 +1,23 @@
-/* Copyright 2012, Google Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- *    * Redistributions of source code must retain the above copyright
- *      notice, this list of conditions and the following disclaimer.
- *    * Redistributions in binary form must reproduce the above
- *      copyright notice, this list of conditions and the following
- *      disclaimer in the documentation and/or other materials provided
- *      with the distribution.
- *    * Neither the name of Google Inc. nor the names of its
- *      contributors may be used to endorse or promote products derived
- *      from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+/* Copyright 2012 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
  */
 
 #ifndef __UTIL_IPC_LOCK_H
 #define __UTIL_IPC_LOCK_H
 
 struct ipc_lock {
-	int is_held;	/* internal */
-	char *filename;	/* provided by the developer */
-	int fd;		/* internal */
+	int is_held; /* internal */
+	const char *filename; /* provided by the developer */
+	int fd; /* internal */
 };
 
 /* don't use C99 initializers here, so this can be used in C++ code */
-#define LOCKFILE_INIT(lockfile) \
-	{ \
-		0,		/* is_held */	\
-		lockfile,	/* filename */	\
-		-1,		/* fd */	\
+#define LOCKFILE_INIT(lockfile)                  \
+	{                                        \
+		0, /* is_held */                 \
+			lockfile, /* filename */ \
+			-1, /* fd */             \
 	}
 
 /*
diff --git a/util/lock/locks.h b/util/lock/locks.h
index 6875d91454..cffbb420ee 100644
--- a/util/lock/locks.h
+++ b/util/lock/locks.h
@@ -1,38 +1,13 @@
-/* Copyright 2012, Google Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- *    * Redistributions of source code must retain the above copyright
- *      notice, this list of conditions and the following disclaimer.
- *    * Redistributions in binary form must reproduce the above
- *      copyright notice, this list of conditions and the following
- *      disclaimer in the documentation and/or other materials provided
- *      with the distribution.
- *    * Neither the name of Google Inc. nor the names of its
- *      contributors may be used to endorse or promote products derived
- *      from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+/* Copyright 2012 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
  */
 
 #ifndef __UTIL_LOCKS_H
 #define __UTIL_LOCKS_H
 
-#define SYSTEM_LOCKFILE_DIR	"/run/lock"
-#define LOCKFILE_NAME		"firmware_utility_lock"
-#define CROS_EC_LOCKFILE_NAME	"cros_ec_lock"
+#define SYSTEM_LOCKFILE_DIR "/run/lock"
+#define LOCKFILE_NAME "firmware_utility_lock"
+#define CROS_EC_LOCKFILE_NAME "cros_ec_lock"
 
 #endif /* __UTIL_LOCKS_H */
diff --git a/util/make_linux_ec_commands_h.sh b/util/make_linux_ec_commands_h.sh
index 4deeaeef32..dfb2c6919a 100755
--- a/util/make_linux_ec_commands_h.sh
+++ b/util/make_linux_ec_commands_h.sh
@@ -1,6 +1,6 @@
 #!/bin/bash
 #
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -27,12 +27,6 @@ if [ $# -ne 2 ]; then
   exit 1
 fi
 
-if [ ! -d "${CROS_WORKON_SRCROOT}" ]; then
-  printf "Not in Chrome OS chroot!\n\n"
-  usage
-  exit 0
-fi
-
 out_dir="$(dirname "${out}")"
 mkdir -p "${out_dir}"
 tmp="$(mktemp -p "${out_dir}" cros_ec_XXX.h)"
@@ -47,17 +41,17 @@ trap cleanup EXIT
 # Replace license
 patch "${tmp}" << EOF
 @@ -1,6 +1,11 @@
--/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+-/* Copyright 2014 The ChromiumOS Authors
 - * Use of this source code is governed by a BSD-style license that can be
 - * found in the LICENSE file.
 +/* SPDX-License-Identifier: GPL-2.0-only */
 +/*
 + * Host communication command constants for ChromeOS EC
 + *
-+ * Copyright (C) 2012 Google, Inc
++ * Copyright 2012 Google, Inc
 + *
 + * NOTE: This file is auto-generated from ChromeOS EC Open Source code from
-+ * https://chromium.googlesource.com/chromiumos/platform/ec/+/master/include/ec_commands.h
++ * https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/include/ec_commands.h
   */
  
  /* Host communication command constants for Chrome EC */
@@ -75,7 +69,4 @@ sed -i "s/INT\([0-9]\{1,2\}\)_MIN/S\1_MIN/" "${tmp}"
 unifdef -x2 -m -UCONFIG_HOSTCMD_ALIGNED -U__ACPI__ -D__KERNEL__ -U__cplusplus \
   -UCHROMIUM_EC "${tmp}"
 
-# Check kernel checkpatch passes.
-"${CROS_WORKON_SRCROOT}/src/repohooks/checkpatch.pl" -f "${tmp}"
-
 cp "${tmp}" "${out}"
diff --git a/util/mchp/crisis_rcvry_util.py b/util/mchp/crisis_rcvry_util.py
new file mode 100755
index 0000000000..c78b71e9f0
--- /dev/null
+++ b/util/mchp/crisis_rcvry_util.py
@@ -0,0 +1,500 @@
+#!/usr/bin/env python3
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""
+Script to program a Microchip EC with erased or a bricked flash.
+
+General usage:
+1. Assert UART crisis recovery pin and toggle EC reset
+2. Set baud rate of serial port on host to 9600
+3. Download and execute Second Loader into SRAM:
+    crisis_rcvry_util.py -s <mchp-loader-image> -p <serial-port>
+4. Set baud rate of serial port on host to 57600
+5. Download and program new EC images into flash:
+    crisis_rcvry_util.py -e <ec-image> -p <serial-port>
+6. De-assert UART crisis recovery pin, and toggle EC reset
+7. EC boots programmed image
+8. Set baud rate of serial port on host to match EC image configuration
+
+Refer to the Microchip Crisis_Mode-cmdSequence document for full details.
+"""
+
+import argparse
+import binascii
+from dataclasses import dataclass
+import logging
+import os
+import struct
+import sys
+import time
+
+import serial  # pylint:disable=import-error
+
+
+CRC_LENGTH = 4
+
+HEADER_WRITE_CMD_ID = 0x65
+FW_IMAGE_WRITE_CMD_ID = 0x67
+SRAM_EXE_CMD_ID = 0x69
+EC_RESPONSE_BYTES_COUNT = 262272
+IMAGE_CHUNK_LENGTH = 128
+HEADER_CHUNK_LENGTH = 64
+HEADER_LENGTH = 320
+START_OFFSET = 0
+RESPONSE_LENGTH = 5
+RETRY_COUNT = 3
+DELAY_50_MS = 0.05
+IMG_LEN_ENCRYPTION = 512
+IMG_LEN_NO_ENCRYPTION = 384
+RESPONSE_STATUS_IMAGE_INVA_MASK = 0x06
+RESPONSE_PACKET_ERROR_MASK = 0x80
+
+HOST_NEGO_CMD_SEQ = b"\x55\xAA"
+HOST_NEGO_CMD_RESP_SEQ = b"\x5A\xA5"
+FLASH_PGM_CMD_SEQ = b"\x33\xCC"
+FLASH_PGM_CMD_RESP_SEQ = b"\x3C\xC3"
+
+VENDOR_ID = b"MCHP"
+PGM_HEADER = b"\x01\x08"
+PRG_HEADER_LEN = b"\x08"
+TERMINATOR_ID = b"XEOF"
+PRG_HDR_TOTAL_LEN = 0xF0
+
+MCHP_VENDOR_ID_START = 0
+MCHP_VENDOR_ID_END = len(VENDOR_ID)
+MCHP_PGM_HDR_START = 6
+MCHP_PGM_HDR_END = MCHP_PGM_HDR_START + len(PGM_HEADER)
+MCHP_PGM_HDR_LEN_START = 13
+MCHP_PGM_HDR_LEN_END = MCHP_PGM_HDR_LEN_START + len(PRG_HEADER_LEN)
+MCHP_TERM_ID_START = PRG_HDR_TOTAL_LEN - 8
+MCHP_TERM_ID_END = MCHP_TERM_ID_START + len(TERMINATOR_ID)
+
+
+logging.basicConfig(level=logging.INFO)
+
+
+@dataclass
+class PacketProperties:
+    """A class for holding transfer method argument"""
+
+    uart_handle: int
+    command_id: int
+    max_write_length: int
+    payload_length: int
+    payload: bytearray
+    bootloader_active: bool
+
+
+def update_progress(curr_val, max_val):
+    """Updates the header/firmware transfer status in console.
+
+    Args:
+        curr_val: Size currently transferred
+        max_val: Maximum size needs to be transferred
+    """
+    print(f"Transfer {curr_val} of {max_val}.", end="\r")
+
+
+def response_bytes(command_id):
+    """Returns the response bytes for the FW IMAGE WRITE CMD.
+
+    Args:
+        command_id: Given command ID
+
+    Returns:
+        resp_bytes: Response byte for the given command ID
+    """
+    resp_bytes = bytearray()
+
+    resp_bytes.append(command_id)
+    resp_bytes.extend(get_crc_bytes(resp_bytes))
+
+    return resp_bytes
+
+
+def ec_image_transfer(uart_handle, ec_file):
+    """Transfer EC image into the internal flash.
+
+    Args:
+        uart_handle: Handle of the UART port
+        ec_file: EC image file path
+    """
+
+    header_gen = bytearray(PRG_HDR_TOTAL_LEN)
+
+    header_gen[MCHP_VENDOR_ID_START:MCHP_VENDOR_ID_END] = VENDOR_ID
+    header_gen[MCHP_PGM_HDR_START:MCHP_PGM_HDR_END] = PGM_HEADER
+    header_gen[MCHP_PGM_HDR_LEN_START:MCHP_PGM_HDR_LEN_END] = PRG_HEADER_LEN
+    header_gen[MCHP_TERM_ID_START:MCHP_TERM_ID_END] = TERMINATOR_ID
+
+    logging.info("EC program header transfer in progress")
+    trans_prop = PacketProperties(
+        uart_handle,
+        HEADER_WRITE_CMD_ID,
+        PRG_HDR_TOTAL_LEN,
+        PRG_HDR_TOTAL_LEN,
+        header_gen,
+        False,
+    )
+    transfer(trans_prop)
+    logging.info("EC program header transfer completed")
+
+    logging.info("EC FW image transfer in progress")
+    with open(ec_file, mode="rb") as data:
+        image = data.read()
+    max_len = os.path.getsize(ec_file)
+
+    trans_prop = PacketProperties(
+        uart_handle,
+        FW_IMAGE_WRITE_CMD_ID,
+        IMAGE_CHUNK_LENGTH,
+        max_len,
+        image,
+        False,
+    )
+    transfer(trans_prop)
+    logging.info("EC FW image transfer completed")
+
+
+def transfer(prop_obj):
+    """Transfer the payload with the command sequence.
+
+    Args:
+        prop_obj.uart_handle: Handle of the UART port
+        prop_obj.command_id: Given command ID
+        prop_obj.max_write_length: Maximum number of bytes
+                 written to the UART during a single write
+        prop_obj.payload_length: Total length of the payload
+        prop_obj.payload: Payload bytes to write
+        prop_obj.bootloader_active: Differentiate whether
+                 second loader or bootloader is active in EC.
+    """
+
+    resp_bytes = response_bytes(prop_obj.command_id)
+
+    offset = START_OFFSET
+    retry_count = RETRY_COUNT
+    while offset < prop_obj.payload_length:
+        update_progress(offset, prop_obj.payload_length)
+
+        program_length = min(
+            prop_obj.max_write_length, prop_obj.payload_length - offset
+        )
+        file_content = prop_obj.payload[offset : offset + program_length]
+        cmd_bytes = construct_write_packet(
+            prop_obj.command_id, program_length, offset, file_content
+        )
+
+        if cmd_bytes is None:
+            sys.exit(1)
+
+        prop_obj.uart_handle.write(cmd_bytes)
+
+        if prop_obj.bootloader_active:
+            # Bootloader need some time to generate response
+            # It runs slower than the Second loader that execute from SRAM
+            time.sleep(DELAY_50_MS)
+
+        prop_obj.uart_handle.reset_input_buffer()
+
+        rf_cont_disp = prop_obj.uart_handle.read(RESPONSE_LENGTH)
+
+        # Success response:
+        # Size: 5Bytes
+        #    0th byte -> Rxd Command
+        #    1st to 4th bytes -> CRC
+
+        # Failure response:
+        # (Error has been detected in the last received packet(Host->EC) by EC)
+        # Size: 6Bytes
+        #    0th byte -> Rxd Command | 0x80
+        #    1st byte -> Status byte
+        #        0th bit -> CRC failure
+        #        1st bit -> Incorrect payload length
+        #        2nd bit -> Incorrect header offset
+        #    2nd to 5th bytes -> CRC
+
+        if rf_cont_disp != resp_bytes:
+            # Less than RESPONSE_LENGTH could be because of read timeout
+            if len(rf_cont_disp) < RESPONSE_LENGTH:
+                logging.critical("Timeout Error")
+                sys.exit(1)
+            elif rf_cont_disp[0] & RESPONSE_PACKET_ERROR_MASK:
+                # Check for Host -> EC packet error
+                # Since its Failure response, read one more byte.
+                rf_cont_disp.append(prop_obj.uart_handle.read(1))
+                # Check status for Incorrect payload length or header offset
+                if rf_cont_disp[1] & RESPONSE_STATUS_IMAGE_INVA_MASK:
+                    logging.critical("Image not valid")
+                    sys.exit(1)
+
+            # CRC failure
+            retry_count = retry_count - 1
+            if retry_count == 0:
+                logging.critical("CRC mis-match observed")
+                sys.exit(1)
+            logging.info("CRC mis-match on the last transfer, retrying")
+            continue
+
+        offset = offset + program_length
+
+
+def second_loader_image_transfer(uart_handle, spi_file):
+    """Transfer the second loader image into SRAM.
+
+    Args:
+        uart_handle: Handle of the UART port
+        spi_file: Given Second Loader image file
+    """
+    tag_base_addr = 0
+    with open(spi_file, mode="rb") as data:
+        image = data.read()
+
+    # Extracting the content
+    addr = (struct.unpack("<I", image[0:4]))[0]
+    addr &= 0xFFFFFF
+    if addr != 0xFFFFFF:
+        tag_base_addr = addr << 8
+
+    hdr_addr = tag_base_addr
+    header_len = HEADER_LENGTH
+    img_offset = hdr_addr + header_len
+    hdr_file_data = image[tag_base_addr : tag_base_addr + header_len]
+    encryption_enable = struct.unpack("B", hdr_file_data[0x06:0x07])[0]
+    img_len = (
+        struct.unpack("<H", hdr_file_data[0x10:0x12])[0]
+    ) * IMAGE_CHUNK_LENGTH
+    if encryption_enable == 0x80:
+        img_len = int(img_len) + IMG_LEN_ENCRYPTION - 16
+    else:
+        img_len = int(img_len) + IMG_LEN_NO_ENCRYPTION - 16
+
+    logging.info("Second loader header transfer in progress")
+
+    trans_prop = PacketProperties(
+        uart_handle,
+        HEADER_WRITE_CMD_ID,
+        HEADER_CHUNK_LENGTH,
+        header_len,
+        image[hdr_addr : hdr_addr + header_len],
+        True,
+    )
+    transfer(trans_prop)
+    logging.info("Second loader header transfer completed")
+
+    logging.info("Second loader FW image transfer in progress")
+    trans_prop = PacketProperties(
+        uart_handle,
+        FW_IMAGE_WRITE_CMD_ID,
+        IMAGE_CHUNK_LENGTH,
+        img_len,
+        image[img_offset : img_offset + img_len],
+        True,
+    )
+    transfer(trans_prop)
+    logging.info("Second loader FW image transfer completed")
+
+
+def get_crc_bytes(_bytes):
+    """The below routine will calculate CRC for given
+
+    Args:
+        _bytes: Given bytes
+
+    Returns:
+        crc_bytes: integer to bytes of crc32
+    """
+    crc_data = binascii.crc32(_bytes)
+    crc_bytes = convert_crc_int_to_bytes(crc_data)
+    return crc_bytes
+
+
+def convert_crc_int_to_bytes(integer_crc_data):
+    """The below function will convert the integer crc to
+        byte array format
+
+    Args:
+        integer_crc_data: integer value
+
+    Returns:
+        crc_bytes: computed crc for the given data
+        e.g. Input: Integer crc = 0xb016f118 will return
+        bytearray[4] = {0x18, 0xf1, 0x16, 0xb0}
+    """
+    crc_bytes = bytearray()
+    for _ in range(CRC_LENGTH):
+        data = integer_crc_data & 0xFF
+        crc_bytes.append(data)
+        integer_crc_data = integer_crc_data >> 8
+    return crc_bytes
+
+
+def construct_write_packet(command, length, offset, data_bytes):
+    """Construct the byte array Packet start with
+    command, length, offset, data_bytes and CRC
+
+    Args:
+        command: Identifier for the current packet
+        length: Length of the packet, excluding command
+        offset: packet offset address
+        data_bytes: packet payload
+
+    Returns:
+        cmd_byte_seq: Packet as byte array
+    """
+    if length < 1:
+        logging.critical("Invalid length to construct write packet")
+        return None
+
+    cmd_bytes_seq = bytearray()
+    cmd_bytes_seq.append(command)
+    cmd_bytes_seq.append(length)
+    cmd_bytes_seq.append(offset & 0xFF)
+    cmd_bytes_seq.append((offset >> 8) & 0xFF)
+    cmd_bytes_seq.append((offset >> 16) & 0xFF)
+    cmd_bytes_seq.extend(data_bytes)
+    cmd_bytes_seq.extend(get_crc_bytes(cmd_bytes_seq))
+    return cmd_bytes_seq
+
+
+def command_write(uart_handle, cmd_seq, resp_seq):
+    """flash program command is used to establish communication
+
+    Args:
+        uart_handle: Handle of the UART port
+        cmd_seq: Sequence of command bytes to transfer
+        resp_seq: Expected response sequence
+
+    Returns:
+        Compares the received response against the expected one
+        and returns True/False
+    """
+    uart_handle.reset_input_buffer()
+    uart_handle.write(cmd_seq)
+
+    i = 0
+    while i < RETRY_COUNT:
+        read = uart_handle.read(2)
+        if len(read) == 0:
+            i += 1
+        elif read == resp_seq:
+            return True
+        else:
+            break
+
+    return False
+
+
+def req_ec_to_run_second_loader(uart_handle):
+    """Send SRAM EXE command to BROM to run the second loader image from SRAM
+
+    Args:
+        uart_handle: Handle of the UART port
+    """
+    cmd_bytes = bytearray()
+    resp_bytes = response_bytes(SRAM_EXE_CMD_ID)
+
+    cmd_bytes.append(SRAM_EXE_CMD_ID)
+    cmd_bytes.extend(get_crc_bytes(cmd_bytes))
+
+    uart_handle.write(cmd_bytes)
+
+    uart_handle.reset_input_buffer()
+    time.sleep(DELAY_50_MS)
+
+    response_sram_exe = uart_handle.read(RESPONSE_LENGTH)
+
+    if resp_bytes != response_sram_exe:
+        logging.critical("Fail to transfer Second Loader execute command.")
+        sys.exit(1)
+
+
+def open_serial_port(port, baud):
+    """Routine to open the comp port number handle.
+
+    Args:
+        port: Comport number
+        baud: Given baud rate
+
+    Returns:
+        comport: UART port handle
+    """
+    comport = serial.Serial(port, baudrate=baud, stopbits=1, timeout=10)
+    return comport
+
+
+def main(args):
+    """Crisis recovery utility routine for second loader into SRAM
+    and program the ec image into the internal flash ."""
+    parser = argparse.ArgumentParser(add_help=False)
+    parser.add_argument(
+        "-p",
+        "--uart_port",
+        type=str,
+        required=True,
+        help="Servo EC UART port path to be specified",
+    )
+    group = parser.add_mutually_exclusive_group(required=True)
+    group.add_argument(
+        "-s",
+        "--second_loader_file_path",
+        type=str,
+        help="second loader image file path",
+    )
+    group.add_argument(
+        "-e",
+        "--ec_file_path",
+        type=str,
+        help="EC image file path",
+    )
+
+    args = parser.parse_args()
+
+    comp_port = os.path.normpath(args.uart_port)
+
+    if args.second_loader_file_path:
+        if not os.path.exists(args.second_loader_file_path):
+            logging.error("Second Loader File not exist")
+            sys.exit(1)
+
+        uart_handle = open_serial_port(comp_port, 9600)
+        process = command_write(
+            uart_handle, HOST_NEGO_CMD_SEQ, HOST_NEGO_CMD_RESP_SEQ
+        )
+        if not process:
+            logging.critical(
+                "Timeout Error - Did not receive response from EC."
+            )
+            sys.exit(1)
+
+        second_loader_image_transfer(uart_handle, args.second_loader_file_path)
+        uart_handle.reset_input_buffer()
+        req_ec_to_run_second_loader(uart_handle)
+
+        uart_handle.close()
+
+    elif args.ec_file_path:
+        if not os.path.exists(args.ec_file_path):
+            logging.error("EC File not exist")
+            sys.exit(1)
+
+        uart_handle = open_serial_port(comp_port, 57600)
+
+        process = command_write(
+            uart_handle, FLASH_PGM_CMD_SEQ, FLASH_PGM_CMD_RESP_SEQ
+        )
+        if not process:
+            logging.critical(
+                "Timeout Error - Did not receive response from EC."
+            )
+            sys.exit(1)
+
+        ec_image_transfer(uart_handle, args.ec_file_path)
+
+        uart_handle.close()
+
+
+if __name__ == "__main__":
+    sys.exit(main(sys.argv[1:]))
diff --git a/util/migrated_files.sh b/util/migrated_files.sh
new file mode 100755
index 0000000000..7e6873fed9
--- /dev/null
+++ b/util/migrated_files.sh
@@ -0,0 +1,28 @@
+#!/bin/bash
+#
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+mapfile -d '' cmakes < <(find zephyr \( -path zephyr/test -prune \) -o \
+  -name CMakeLists.txt -print0)
+
+exit_code=0
+
+for file in "$@"; do
+  ec_file="${file##**/platform/ec/}"
+  case "${ec_file}" in
+    baseboard/*|board/*|chip/*|driver/fingerprint/*|*fpsensor*|test/*|\
+    util/*|zephyr/*) ;;
+    **.c)
+      if ! grep -q -F "\${PLATFORM_EC}/${ec_file}" "${cmakes[@]}" ; then
+        echo -n "WARNING: ${ec_file} is not used in Zephyr EC. Do not edit this"
+        echo -n " unless you also find the zephyr copy and fix the same code"
+        echo " there."
+        exit_code=1
+      fi
+      ;;
+  esac
+done
+
+exit "${exit_code}"
diff --git a/util/misc_util.c b/util/misc_util.c
deleted file mode 100644
index 9813dc72b4..0000000000
--- a/util/misc_util.c
+++ /dev/null
@@ -1,175 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <ctype.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/utsname.h>
-
-#include "comm-host.h"
-#include "misc_util.h"
-
-int write_file(const char *filename, const char *buf, int size)
-{
-	FILE *f;
-	int i;
-
-	/* Write to file */
-	f = fopen(filename, "wb");
-	if (!f) {
-		perror("Error opening output file");
-		return -1;
-	}
-	i = fwrite(buf, 1, size, f);
-	fclose(f);
-	if (i != size) {
-		perror("Error writing to file");
-		return -1;
-	}
-
-	return 0;
-}
-
-char *read_file(const char *filename, int *size)
-{
-	FILE *f = fopen(filename, "rb");
-	char *buf;
-	int i;
-
-	if (!f) {
-		perror("Error opening input file");
-		return NULL;
-	}
-
-	fseek(f, 0, SEEK_END);
-	*size = ftell(f);
-	rewind(f);
-	if ((*size > 0x100000) || (*size < 0)) {
-		if (*size < 0)
-			perror("ftell failed");
-		else
-			fprintf(stderr, "File seems unreasonably large\n");
-		fclose(f);
-		return NULL;
-	}
-
-	buf = (char *)malloc(*size);
-	if (!buf) {
-		fprintf(stderr, "Unable to allocate buffer.\n");
-		fclose(f);
-		return NULL;
-	}
-
-	printf("Reading %d bytes from %s...\n", *size, filename);
-	i = fread(buf, 1, *size, f);
-	fclose(f);
-	if (i != *size) {
-		perror("Error reading file");
-		free(buf);
-		return NULL;
-	}
-
-	return buf;
-}
-
-int is_string_printable(const char *buf)
-{
-	while (*buf) {
-		if (!isprint(*buf))
-			return 0;
-		buf++;
-	}
-
-	return 1;
-}
-
-/**
- * Get the versions of the command supported by the EC.
- *
- * @param cmd		Command
- * @param pmask		Destination for version mask; will be set to 0 on
- *			error.
- * @return 0 if success, <0 if error
- */
-int ec_get_cmd_versions(int cmd, uint32_t *pmask)
-{
-	struct ec_params_get_cmd_versions_v1 pver_v1;
-	struct ec_params_get_cmd_versions pver;
-	struct ec_response_get_cmd_versions rver;
-	int rv;
-
-	*pmask = 0;
-
-	pver_v1.cmd = cmd;
-	rv = ec_command(EC_CMD_GET_CMD_VERSIONS, 1, &pver_v1, sizeof(pver_v1),
-			&rver, sizeof(rver));
-
-	if (rv < 0) {
-		pver.cmd = cmd;
-		rv = ec_command(EC_CMD_GET_CMD_VERSIONS, 0, &pver, sizeof(pver),
-				&rver, sizeof(rver));
-	}
-
-	if (rv < 0)
-		return rv;
-
-	*pmask = rver.version_mask;
-	return 0;
-}
-
-/**
- * Return non-zero if the EC supports the command and version
- *
- * @param cmd		Command to check
- * @param ver		Version to check
- * @return non-zero if command version supported; 0 if not.
- */
-int ec_cmd_version_supported(int cmd, int ver)
-{
-	uint32_t mask = 0;
-
-	if (ec_get_cmd_versions(cmd, &mask))
-		return 0;
-
-	return (mask & EC_VER_MASK(ver)) ? 1 : 0;
-}
-
-/**
- * Return 1 is the current kernel version is greater or equal to
- * <major>.<minor>.<sublevel>
- */
-int kernel_version_ge(int major, int minor, int sublevel)
-{
-	struct utsname uts;
-	int atoms, kmajor, kminor, ksublevel;
-
-	if (uname(&uts) < 0)
-		return -1;
-	atoms = sscanf(uts.release, "%d.%d.%d", &kmajor, &kminor, &ksublevel);
-	if (atoms < 1)
-		return -1;
-
-	if (kmajor > major)
-		return 1;
-	if (kmajor < major)
-		return 0;
-
-	/* kmajor == major */
-	if (atoms < 2)
-		return 0 == minor && 0 == sublevel;
-	if (kminor > minor)
-		return 1;
-	if (kminor < minor)
-		return 0;
-
-	/* kminor == minor */
-	if (atoms < 3)
-		return 0 == sublevel;
-
-	return ksublevel >= sublevel;
-}
-
diff --git a/util/misc_util.cc b/util/misc_util.cc
new file mode 100644
index 0000000000..4d1e1c5876
--- /dev/null
+++ b/util/misc_util.cc
@@ -0,0 +1,212 @@
+/* Copyright 2013 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "comm-host.h"
+#include "misc_util.h"
+
+#include <ctype.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <sys/utsname.h>
+
+int write_file(const char *filename, const char *buf, int size)
+{
+	FILE *f;
+	int i;
+
+	/* Write to file */
+	f = fopen(filename, "wb");
+	if (!f) {
+		perror("Error opening output file");
+		return -1;
+	}
+	i = fwrite(buf, 1, size, f);
+	fclose(f);
+	if (i != size) {
+		perror("Error writing to file");
+		return -1;
+	}
+
+	return 0;
+}
+
+char *read_file(const char *filename, int *size)
+{
+	FILE *f = fopen(filename, "rb");
+	char *buf;
+	int i;
+
+	if (!f) {
+		perror("Error opening input file");
+		return NULL;
+	}
+
+	fseek(f, 0, SEEK_END);
+	*size = ftell(f);
+	rewind(f);
+	if ((*size > 0x100000) || (*size < 0)) {
+		if (*size < 0)
+			perror("ftell failed");
+		else
+			fprintf(stderr, "File seems unreasonably large\n");
+		fclose(f);
+		return NULL;
+	}
+
+	buf = (char *)malloc(*size);
+	if (!buf) {
+		fprintf(stderr, "Unable to allocate buffer.\n");
+		fclose(f);
+		return NULL;
+	}
+
+	printf("Reading %d bytes from %s...\n", *size, filename);
+	i = fread(buf, 1, *size, f);
+	fclose(f);
+	if (i != *size) {
+		perror("Error reading file");
+		free(buf);
+		return NULL;
+	}
+
+	return buf;
+}
+
+int is_string_printable(const char *buf)
+{
+	while (*buf) {
+		if (!isprint(*buf))
+			return 0;
+		buf++;
+	}
+
+	return 1;
+}
+
+/**
+ * Get the versions of the command supported by the EC.
+ *
+ * @param cmd		Command
+ * @param pmask		Destination for version mask; will be set to 0 on
+ *			error.
+ * @return 0 if success, <0 if error
+ */
+int ec_get_cmd_versions(int cmd, uint32_t *pmask)
+{
+	struct ec_params_get_cmd_versions_v1 pver_v1;
+	struct ec_params_get_cmd_versions pver;
+	struct ec_response_get_cmd_versions rver;
+	int rv;
+
+	*pmask = 0;
+
+	pver_v1.cmd = cmd;
+	rv = ec_command(EC_CMD_GET_CMD_VERSIONS, 1, &pver_v1, sizeof(pver_v1),
+			&rver, sizeof(rver));
+
+	if (rv < 0) {
+		pver.cmd = cmd;
+		rv = ec_command(EC_CMD_GET_CMD_VERSIONS, 0, &pver, sizeof(pver),
+				&rver, sizeof(rver));
+	}
+
+	if (rv < 0)
+		return rv;
+
+	*pmask = rver.version_mask;
+	return 0;
+}
+
+/**
+ * Return non-zero if the EC supports the command and version
+ *
+ * @param cmd		Command to check
+ * @param ver		Version to check
+ * @return non-zero if command version supported; 0 if not.
+ */
+int ec_cmd_version_supported(int cmd, int ver)
+{
+	uint32_t mask = 0;
+
+	if (ec_get_cmd_versions(cmd, &mask))
+		return 0;
+
+	return (mask & EC_VER_MASK(ver)) ? 1 : 0;
+}
+
+/**
+ * Return 1 is the current kernel version is greater or equal to
+ * <major>.<minor>.<sublevel>
+ */
+int kernel_version_ge(int major, int minor, int sublevel)
+{
+	struct utsname uts;
+	int atoms, kmajor, kminor, ksublevel;
+
+	if (uname(&uts) < 0)
+		return -1;
+	atoms = sscanf(uts.release, "%d.%d.%d", &kmajor, &kminor, &ksublevel);
+	if (atoms < 1)
+		return -1;
+
+	if (kmajor > major)
+		return 1;
+	if (kmajor < major)
+		return 0;
+
+	/* kmajor == major */
+	if (atoms < 2)
+		return 0 == minor && 0 == sublevel;
+	if (kminor > minor)
+		return 1;
+	if (kminor < minor)
+		return 0;
+
+	/* kminor == minor */
+	if (atoms < 3)
+		return 0 == sublevel;
+
+	return ksublevel >= sublevel;
+}
+
+/**
+ * Prints data in hexdump canonical format.
+ *
+ * @param data Buffer of data to print
+ * @param len Length of data to print
+ * @param offset_start Starting offset added to the displayed offset.
+ *        This only affects how the offset is printed, it does not affect
+ *        what data is printed.
+ */
+void hexdump_canonical(const uint8_t *data, size_t len, uint32_t offset_start)
+{
+	uint32_t i, j;
+
+	if (!data || !len)
+		return;
+
+	for (i = 0; i < len; i += 16) {
+		printf("%08x  ", i + offset_start);
+		for (j = i; j < i + 16; j++) {
+			if (j == i + 8)
+				printf(" ");
+			if (j < len)
+				printf("%02x ", data[j]);
+			else
+				printf("   ");
+		}
+		printf(" |");
+		for (j = i; j < i + 16 && j < len; j++)
+			if (isprint(data[i + j]))
+				printf("%c", data[i + j]);
+			else
+				printf(".");
+		printf("|\n");
+	}
+	printf("%08x\n", i + offset_start);
+}
diff --git a/util/misc_util.h b/util/misc_util.h
index 240d735556..80286f2a88 100644
--- a/util/misc_util.h
+++ b/util/misc_util.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,9 +6,29 @@
 #ifndef __UTIL_MISC_UTIL_H
 #define __UTIL_MISC_UTIL_H
 
-/* Don't use a macro where an inline will do... */
-static inline int MIN(int a, int b) { return a < b ? a : b; }
-static inline int MAX(int a, int b) { return a > b ? a : b; }
+#include <stddef.h>
+#include <stdint.h>
+
+#define GENERIC_MAX(x, y) ((x) > (y) ? (x) : (y))
+#define GENERIC_MIN(x, y) ((x) < (y) ? (x) : (y))
+#ifndef MAX
+#define MAX(a, b)                            \
+	({                                   \
+		__typeof__(a) temp_a = (a);  \
+		__typeof__(b) temp_b = (b);  \
+                                             \
+		GENERIC_MAX(temp_a, temp_b); \
+	})
+#endif
+#ifndef MIN
+#define MIN(a, b)                            \
+	({                                   \
+		__typeof__(a) temp_a = (a);  \
+		__typeof__(b) temp_b = (b);  \
+                                             \
+		GENERIC_MIN(temp_a, temp_b); \
+	})
+#endif
 
 /**
  * Write a buffer to the file.
@@ -62,4 +82,16 @@ int ec_cmd_version_supported(int cmd, int ver);
  * <major>.<minor>.<sublevel>
  */
 int kernel_version_ge(int major, int minor, int sublevel);
+
+/**
+ * Prints data in hexdump canonical format.
+ *
+ * @param data Buffer of data to print
+ * @param len Length of data to print
+ * @param offset_start Starting offset added to the printed offset.
+ *     This only affects how the offset is printed, it does not affect
+ *     what data is printed.
+ */
+void hexdump_canonical(const uint8_t *data, size_t len, uint32_t offset_start);
+
 #endif
diff --git a/util/openocd/board/rex.cfg b/util/openocd/board/rex.cfg
new file mode 100644
index 0000000000..9c0f2c8153
--- /dev/null
+++ b/util/openocd/board/rex.cfg
@@ -0,0 +1,7 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+transport select swd
+
+source [find target/npcx993f.cfg]
diff --git a/util/openocd/board/skyrim.cfg b/util/openocd/board/skyrim.cfg
new file mode 100644
index 0000000000..a13e24c3fb
--- /dev/null
+++ b/util/openocd/board/skyrim.cfg
@@ -0,0 +1,7 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+transport select swd
+
+source [find target/npcx993f.cfg]
diff --git a/util/openocd/lm4_chip.cfg b/util/openocd/lm4_chip.cfg
deleted file mode 100644
index 3dffa2dc66..0000000000
--- a/util/openocd/lm4_chip.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-
-ftdi_layout_init 0x0018 0x009b
-
-# open collector oe only
-ftdi_layout_signal nSRST -oe 0x0020
-
-reset_config trst_only
-
-source [find target/stellaris.cfg]
-source [find lm4x_cmds.tcl]
-
diff --git a/util/openocd/lm4x_cmds.tcl b/util/openocd/lm4x_cmds.tcl
deleted file mode 100644
index 59c2dbdeb6..0000000000
--- a/util/openocd/lm4x_cmds.tcl
+++ /dev/null
@@ -1,51 +0,0 @@
-# Copyright 2012 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Command automation for Blizzard LM4F chip
-
-# Program internal flash
-
-proc flash_lm4 {path offset} {
-	reset halt;
-	flash write_image erase $path $offset;
-	reset
-}
-
-proc flash_lm4_board {board} {
-	flash_lm4 ../../build/$board/ec.bin 0
-}
-
-proc flash_lm4_ro {board} {
-	flash_lm4 ../../build/$board/RO/ec.RO.flat 0
-}
-
-proc flash_lm4_rw {board} {
-	flash_lm4 ../../build/$board/RW/ec.RW.bin 131072
-}
-
-# Boards with CONFIG_FLASH_PSTATE_BANK have pstate following RO
-proc unprotect_pstate { } {
-	reset halt
-	flash erase_sector 0 126 127
-	reset
-}
-
-# Boot a software using internal RAM only
-
-proc ramboot_lm4 {path} {
-	reset halt
-	load_image $path 0x20000000 bin
-	reg 15 0x20000400
-	resume
-}
-
-proc ramboot_lm4_board {board} {
-	ramboot_lm4 ../../../build/$board/ec.RO.flat
-}
-
-proc flash_emerged_board {board} {
-	set firmware_image ../../../../../../chroot/build/$board/firmware/ec.bin
-
-	flash_lm4 $firmware_image 0
-}
diff --git a/util/openocd/npcx.cfg b/util/openocd/npcx.cfg
index 0ab2b42888..888ebafcec 100644
--- a/util/openocd/npcx.cfg
+++ b/util/openocd/npcx.cfg
@@ -1,4 +1,4 @@
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
+# Copyright 2014 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/util/openocd/npcx_cmds.tcl b/util/openocd/npcx_cmds.tcl
index 759e897131..fb7f634bff 100644
--- a/util/openocd/npcx_cmds.tcl
+++ b/util/openocd/npcx_cmds.tcl
@@ -1,4 +1,4 @@
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
+# Copyright 2014 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/util/openocd/nrf51_chip.cfg b/util/openocd/nrf51_chip.cfg
deleted file mode 100644
index f0e78897d6..0000000000
--- a/util/openocd/nrf51_chip.cfg
+++ /dev/null
@@ -1,14 +0,0 @@
-
-#nRF51 uses SWD
-transport select swd
-# Since nTRST is repurposed, we need a different layout_init setting
-ftdi_layout_init 0x0008 0x009b
-
-ftdi_layout_signal SWDIO_OE -nalias nTRST
-ftdi_layout_signal SWD_EN -alias TMS
-
-#Disable fast flashing, it only works with ST-Link and CMSIS-DAP
-set WORKAREASIZE 0
-source [find target/nrf51.cfg]
-source [find nrf51_cmds.tcl]
-
diff --git a/util/openocd/nrf51_cmds.tcl b/util/openocd/nrf51_cmds.tcl
deleted file mode 100644
index 711b27574d..0000000000
--- a/util/openocd/nrf51_cmds.tcl
+++ /dev/null
@@ -1,22 +0,0 @@
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Command automation for Nordic nRF51 chip
-
-proc flash_nrf51 {path offset} {
-	reset halt;
-	program $path $offset;
-}
-
-proc unprotect_nrf51 { } {
-	reset halt;
-	nrf51 mass_erase;
-}
-
-# enable reset by writing 1 to the RESET register
-# This will disconnect the debugger with the following message:
-# Polling target nrf51.cpu failed, trying to reexamine
-proc exit_debug_mode_nrf51 { } {
-	mww 0x40000544 1;
-}
diff --git a/util/openocd/target/npcx993f.cfg b/util/openocd/target/npcx993f.cfg
new file mode 100644
index 0000000000..b9c7c4e43d
--- /dev/null
+++ b/util/openocd/target/npcx993f.cfg
@@ -0,0 +1,11 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Also works for the 7F and 6F as these all share 64K of RAM at 0x200C0000
+set WORKAREASIZE 0x10000
+set WORKAREAADDR 0x200c0000
+set CHIPNAME NPCX993F
+set CPUTAPID 0x2ba01477
+
+source [find target/npcx99nf.cfg]
\ No newline at end of file
diff --git a/util/openocd/target/npcx99nf.cfg b/util/openocd/target/npcx99nf.cfg
new file mode 100644
index 0000000000..8d0828c4c1
--- /dev/null
+++ b/util/openocd/target/npcx99nf.cfg
@@ -0,0 +1,106 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+source [find mem_helper.tcl]
+
+set _ENDIAN little
+
+if { [info exists CHIPNAME] } {
+    set _CHIPNAME $CHIPNAME
+} else {
+    set _CHIPNAME NPCX99nF
+}
+
+if { [info exists WORKAREAADDR] } {
+    set _WORKAREAADDR $WORKAREAADDR
+} else {
+    set _WORKAREAADDR 0
+}
+
+if { [info exists WORKAREASIZE] } {
+    set _WORKAREASIZE $WORKAREASIZE
+} else {
+    set _WORKAREASIZE 0
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x2ba01477
+}
+
+if { [info exists FLASHADDR] } {
+    set _FLASHADDR $FLASHADDR
+} else {
+    set _FLASHADDR 0x64000000
+}
+
+adapter speed 600
+
+swd newdap $_CHIPNAME cpu -enable
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+# Work area in RAM used during flashing
+$_TARGETNAME configure -work-area-phys $_WORKAREAADDR -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# The npcx driver detects and autoconfigures various flash parameters
+set _FLASHNAME $_CHIPNAME.internal_flash
+flash bank $_FLASHNAME npcx $_FLASHADDR 0 0 0 $_TARGETNAME
+
+# use sysresetreq to perform a system reset
+cortex_m reset_config sysresetreq
+adapter srst delay 100
+
+# Freeze various clocks, counters and destructive reads
+# Otherwise something like the watchdog time can interfere with debugging/flashing
+proc debug_freeze { } {
+    mwb 0x400C3078 0x7F
+}
+
+proc handle_gdb_attach { } {
+    halt
+    debug_freeze
+
+    # Read the address of the reset handler from the vector table
+    # The bootloader runs first, but it's not a good place to halt
+    # as it sets up various things, including debug support
+    set RESET_HANDLER [mrw 0x10080004]
+    bp $RESET_HANDLER 2 hw
+    reset run
+
+    # Wait to hit the reset handler bp
+    wait_halt 250
+    # OpenOCD can get stuck in the reset handler
+    # removing the BP prevents that
+    rbp $RESET_HANDLER
+}
+
+proc handle_gdb_detach { } {
+    shutdown
+}
+
+proc flash_target { image verify } {
+    global _FLASHADDR
+    echo "Resetting and halting target..."
+    reset halt
+    echo "Flashing image..."
+    flash write_image erase $image $_FLASHADDR bin
+    if { $verify == 1} {
+        echo "Verifying image..."
+        flash verify_image $image $_FLASHADDR bin
+    }
+    echo "Resuming target..."
+    reset run
+}
+
+$_TARGETNAME configure -event halted debug_freeze
+
+# GDB connection config
+$_TARGETNAME configure -event gdb-attach handle_gdb_attach
+$_TARGETNAME configure -event gdb-detach handle_gdb_detach
+
+gdb_memory_map enable
\ No newline at end of file
diff --git a/util/powerd_lock.c b/util/powerd_lock.c
deleted file mode 100644
index df34d03c6c..0000000000
--- a/util/powerd_lock.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * This file is ported from the flashrom project.
- *
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- *
- * powerd_lock.c: power management routines
- */
-
-#include <errno.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/types.h>
-#include <unistd.h>
-
-#include "powerd_lock.h"
-
-/*
- * Path to a file containing flashrom's PID. While present, powerd avoids
- * suspending or shutting down the system.
- */
-static const char lock_file_path[] =
-	"/run/lock/power_override/battery_tool.lock";
-
-int disable_power_management()
-{
-	FILE *lock_file;
-	int rc = 0;
-	lock_file = fopen(lock_file_path, "w");
-	if (!lock_file)
-		return POWERD_CREATE_LOCK_FILE_ERROR;
-
-	if (fprintf(lock_file, "%ld", (long)getpid()) < 0)
-		rc = POWERD_WRITE_LOCK_FILE_ERROR;
-
-	if (fclose(lock_file) != 0)
-		rc |= POWERD_CLOSE_LOCK_FILE_ERROR;
-	return rc;
-}
-
-int restore_power_management()
-{
-	int result = 0;
-	result = unlink(lock_file_path);
-	if (result != 0 && errno != ENOENT)
-		return POWERD_DELETE_LOCK_FILE_ERROR;
-	return 0;
-}
diff --git a/util/powerd_lock.cc b/util/powerd_lock.cc
new file mode 100644
index 0000000000..0515d66e52
--- /dev/null
+++ b/util/powerd_lock.cc
@@ -0,0 +1,64 @@
+/*
+ * This file is ported from the flashrom project.
+ *
+ * Copyright 2015 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ *
+ * powerd_lock.c: power management routines
+ */
+
+#include "powerd_lock.h"
+
+#include <errno.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <sys/types.h>
+#include <unistd.h>
+
+/*
+ * Path to a file containing flashrom's PID. While present, powerd avoids
+ * suspending or shutting down the system.
+ */
+static const char lock_file_path[] =
+	"/run/lock/power_override/battery_tool.lock";
+
+int disable_power_management(void)
+{
+	FILE *lock_file;
+	int rc = 0;
+	lock_file = fopen(lock_file_path, "w");
+	if (!lock_file)
+		return POWERD_CREATE_LOCK_FILE_ERROR;
+
+	if (fprintf(lock_file, "%ld", (long)getpid()) < 0)
+		rc = POWERD_WRITE_LOCK_FILE_ERROR;
+
+	if (fclose(lock_file) != 0)
+		rc |= POWERD_CLOSE_LOCK_FILE_ERROR;
+	return rc;
+}
+
+int restore_power_management(void)
+{
+	int result = 0;
+	result = unlink(lock_file_path);
+	if (result != 0 && errno != ENOENT)
+		return POWERD_DELETE_LOCK_FILE_ERROR;
+	return 0;
+}
diff --git a/util/powerd_lock.h b/util/powerd_lock.h
index 86be184a19..1487f28bb7 100644
--- a/util/powerd_lock.h
+++ b/util/powerd_lock.h
@@ -1,7 +1,7 @@
 /*
  * This file is ported from the flashrom project.
  *
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -27,8 +27,8 @@
 enum POWERD_ERROR_CODE {
 	POWERD_OK = 0,
 	POWERD_CREATE_LOCK_FILE_ERROR = 0x1,
-	POWERD_WRITE_LOCK_FILE_ERROR  = 0x2,
-	POWERD_CLOSE_LOCK_FILE_ERROR  = 0x4,
+	POWERD_WRITE_LOCK_FILE_ERROR = 0x2,
+	POWERD_CLOSE_LOCK_FILE_ERROR = 0x4,
 	POWERD_DELETE_LOCK_FILE_ERROR = 0x8
 };
 
@@ -38,4 +38,4 @@ int disable_power_management(void);
 /* Re-enable power management. */
 int restore_power_management(void);
 
-#endif	/* __UTIL_POWERD_LOCK_H */
+#endif /* __UTIL_POWERD_LOCK_H */
diff --git a/util/presubmit_check.sh b/util/presubmit_check.sh
deleted file mode 100755
index bbf4338fad..0000000000
--- a/util/presubmit_check.sh
+++ /dev/null
@@ -1,43 +0,0 @@
-#!/bin/bash
-#
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Verify there is no CPRINTS("....\n", ...) statements added to the code.
-upstream_branch="$(git rev-parse --abbrev-ref --symbolic-full-name @{u} \
-    2>/dev/null)"
-if [[ -z ${upstream_branch} ]]; then
-  echo "Current branch does not have an upstream branch" >&2
-  exit 1
-fi
-# This will print the offending CPRINTS invocations, if any, and the names of
-# the files they are in.
-if git diff "${upstream_branch}" HEAD | grep -e '^+\(.*CPRINTS(.*\\n"\|++\)' |
-    grep CPRINTS -B1 >&2 ; then
-  echo "error: CPRINTS strings should not include newline characters" >&2
-  exit 1
-fi
-
-# Directories that need to be tested by separate unit tests.
-unittest_dirs="util/ec3po/ extra/stack_analyzer/"
-
-for dir in $unittest_dirs; do
-    dir_files=$(echo "${PRESUBMIT_FILES}" | grep "${dir}")
-    if [[ -z "${dir_files}" ]]; then
-        continue
-    fi
-
-    if [[ ! -e "${dir}/.tests-passed" ]]; then
-        echo "Unit tests have not passed.  Please run \"${dir}run_tests.sh\"."
-        exit 1
-    fi
-
-    changed_files=$(find ${dir_files} -newer "${dir}/.tests-passed")
-    if [[ -n "${changed_files}" ]] && [[ -n "${dir_files}" ]]; then
-        echo "Files have changed since last time unit tests passed:"
-        echo "${changed_files}" | sed -e 's/^/  /'
-        echo "Please run \"${dir}run_tests.sh\"."
-        exit 1
-    fi
-done
diff --git a/util/preupload/__init__.py b/util/preupload/__init__.py
new file mode 100644
index 0000000000..96bb372274
--- /dev/null
+++ b/util/preupload/__init__.py
@@ -0,0 +1,3 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
diff --git a/util/preupload/lib.py b/util/preupload/lib.py
new file mode 100644
index 0000000000..ced5f2a980
--- /dev/null
+++ b/util/preupload/lib.py
@@ -0,0 +1,34 @@
+# Lint as: python3
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Common utilities for pre-upload checks."""
+
+import argparse
+from pathlib import Path
+import subprocess
+
+
+PRE_SUBMIT = "pre-submit"
+
+
+def cat_file(args, filename) -> str:
+    """Read a file either from disk, or from a git commit."""
+    if args.commit == PRE_SUBMIT:
+        with open(filename, encoding="utf-8") as infile:
+            return infile.read()
+    return subprocess.run(
+        ["git", "show", f"{args.commit}:{filename}"],
+        universal_newlines=True,
+        stdout=subprocess.PIPE,
+        check=True,
+    ).stdout
+
+
+def argument_parser():
+    """Returns an ArgumentParser with standard options configured."""
+    parser = argparse.ArgumentParser()
+    parser.add_argument("-c", "--commit", default=PRE_SUBMIT)
+    parser.add_argument("filename", nargs="*", type=Path)
+    return parser
diff --git a/util/run_ects.py b/util/run_ects.py
index a633430113..e9ab944938 100644
--- a/util/run_ects.py
+++ b/util/run_ects.py
@@ -1,4 +1,4 @@
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -11,82 +11,86 @@
 import subprocess
 import sys
 
+
 # List of tests to run.
-TESTS = ['meta', 'gpio', 'hook', 'i2c', 'interrupt', 'mutex', 'task', 'timer']
+TESTS = ["meta", "gpio", "hook", "i2c", "interrupt", "mutex", "task", "timer"]
 
 
 class CtsRunner(object):
-  """Class running eCTS tests."""
-
-  def __init__(self, ec_dir, dryrun):
-    self.ec_dir = ec_dir
-    self.cts_py = []
-    if dryrun:
-      self.cts_py += ['echo']
-    self.cts_py += [os.path.join(ec_dir, 'cts/cts.py')]
-
-  def run_cmd(self, cmd):
-    try:
-      rc = subprocess.call(cmd)
-      if rc != 0:
-        return False
-    except OSError:
-      return False
-    return True
-
-  def run_test(self, test):
-    cmd = self.cts_py + ['-m', test]
-    self.run_cmd(cmd)
-
-  def run(self, tests):
-    for test in tests:
-      logging.info('Running', test, 'test.')
-      self.run_test(test)
-
-  def sync(self):
-    logging.info('Syncing tree...')
-    os.chdir(self.ec_dir)
-    cmd = ['repo', 'sync', '.']
-    return self.run_cmd(cmd)
-
-  def upload(self):
-    logging.info('Uploading results...')
+    """Class running eCTS tests."""
+
+    def __init__(self, ec_dir, dryrun):
+        self.ec_dir = ec_dir
+        self.cts_py = []
+        if dryrun:
+            self.cts_py += ["echo"]
+        self.cts_py += [os.path.join(ec_dir, "cts/cts.py")]
+
+    def run_cmd(self, cmd):
+        try:
+            rc = subprocess.call(cmd)
+            if rc != 0:
+                return False
+        except OSError:
+            return False
+        return True
+
+    def run_test(self, test):
+        cmd = self.cts_py + ["-m", test]
+        self.run_cmd(cmd)
+
+    def run(self, tests):
+        for test in tests:
+            logging.info("Running %s test.", test)
+            self.run_test(test)
+
+    def sync(self):
+        logging.info("Syncing tree...")
+        os.chdir(self.ec_dir)
+        cmd = ["repo", "sync", "."]
+        return self.run_cmd(cmd)
+
+    def upload(self):
+        logging.info("Uploading results...")
 
 
 def main():
-  if not os.path.exists('/etc/cros_chroot_version'):
-    logging.error('This script has to run inside chroot.')
-    sys.exit(-1)
-
-  ec_dir = os.path.realpath(os.path.dirname(__file__) + '/..')
-
-  parser = argparse.ArgumentParser(description='Run eCTS and report results.')
-  parser.add_argument('-d',
-                      '--dryrun',
-                      action='store_true',
-                      help='Echo commands to be executed without running them.')
-  parser.add_argument('-s',
-                      '--sync',
-                      action='store_true',
-                      help='Sync tree before running tests.')
-  parser.add_argument('-u',
-                      '--upload',
-                      action='store_true',
-                      help='Upload test results.')
-  args = parser.parse_args()
-
-  runner = CtsRunner(ec_dir, args.dryrun)
-
-  if args.sync:
-    if not runner.sync():
-      logging.error('Failed to sync.')
-      sys.exit(-1)
-
-  runner.run(TESTS)
-
-  if args.upload:
-    runner.upload()
-
-
-if __name__ == '__main__':
-  main()
+    if not os.path.exists("/etc/cros_chroot_version"):
+        logging.error("This script has to run inside chroot.")
+        sys.exit(-1)
+
+    ec_dir = os.path.realpath(os.path.dirname(__file__) + "/..")
+
+    parser = argparse.ArgumentParser(description="Run eCTS and report results.")
+    parser.add_argument(
+        "-d",
+        "--dryrun",
+        action="store_true",
+        help="Echo commands to be executed without running them.",
+    )
+    parser.add_argument(
+        "-s",
+        "--sync",
+        action="store_true",
+        help="Sync tree before running tests.",
+    )
+    parser.add_argument(
+        "-u", "--upload", action="store_true", help="Upload test results."
+    )
+    args = parser.parse_args()
+
+    runner = CtsRunner(ec_dir, args.dryrun)
+
+    if args.sync:
+        if not runner.sync():
+            logging.error("Failed to sync.")
+            sys.exit(-1)
+
+    runner.run(TESTS)
+
+    if args.upload:
+        runner.upload()
+
+
+if __name__ == "__main__":
+    main()
diff --git a/util/run_host_test b/util/run_host_test
index ce33722c3a..3ee8ccc7ed 100755
--- a/util/run_host_test
+++ b/util/run_host_test
@@ -1,13 +1,11 @@
 #!/usr/bin/env python3
 # -*- coding: utf-8 -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 """Wrapper that runs a host test. Handles timeout and stopping the emulator."""
 
-from __future__ import print_function
-
 import argparse
 import enum
 import io
@@ -20,113 +18,121 @@ import time
 
 
 class TestResult(enum.Enum):
-  """An Enum representing the result of running a test."""
-  SUCCESS = enum.auto()
-  FAIL = enum.auto()
-  TIMEOUT = enum.auto()
-  UNEXPECTED_TERMINATION = enum.auto()
-
-  @property
-  def exit_code(self):
-    if self is TestResult.SUCCESS:
-      return 0
-    return 1
-
-  @property
-  def reason(self):
-    return {
-        TestResult.SUCCESS: 'passed',
-        TestResult.FAIL: 'failed',
-        TestResult.TIMEOUT: 'timed out',
-        TestResult.UNEXPECTED_TERMINATION: 'terminated unexpectedly',
-    }[self]
+    """An Enum representing the result of running a test."""
+    SUCCESS = 0
+    FAIL = 1
+    TIMEOUT = 2
+    UNEXPECTED_TERMINATION = 3
+
+    @property
+    def reason(self):
+        """Return a map of test result enums to descriptions."""
+        return {
+            TestResult.SUCCESS: 'passed',
+            TestResult.FAIL: 'failed',
+            TestResult.TIMEOUT: 'timed out',
+            TestResult.UNEXPECTED_TERMINATION: 'terminated unexpectedly',
+        }[self]
 
 
 def run_test(path, timeout=10):
-  start_time = time.monotonic()
-  env = dict(os.environ)
-  env['ASAN_OPTIONS'] = 'log_path=stderr'
-
-  proc = subprocess.Popen(
-      [path],
-      bufsize=0,
-      stdin=subprocess.PIPE,
-      stdout=subprocess.PIPE,
-      env=env)
-
-  # Put the output pipe in non-blocking mode. We will then select(2)
-  # on the pipe to know when we have bytes to process.
-  os.set_blocking(proc.stdout.fileno(), False)
-
-  try:
-    output_buffer = io.BytesIO()
-    while True:
-      select_timeout = timeout - (time.monotonic() - start_time)
-      if select_timeout <= 0:
-        return TestResult.TIMEOUT, output_buffer.getvalue()
-
-      readable, _, _ = select.select([proc.stdout], [], [], select_timeout)
-
-      if not readable:
-        # Indicates that select(2) timed out.
-        return TestResult.TIMEOUT, output_buffer.getvalue()
-
-      output_buffer.write(proc.stdout.read())
-      output_log = output_buffer.getvalue()
-
-      if b'Pass!' in output_log:
-        return TestResult.SUCCESS, output_log
-      if b'Fail!' in output_log:
-        return TestResult.FAIL, output_log
-      if proc.poll():
-        return TestResult.UNEXPECTED_TERMINATION, output_log
-  finally:
-    # Check if the process has exited. If not, send it a SIGTERM, wait for it
-    # to exit, and if it times out, kill the process directly.
-    if not proc.poll():
-      try:
-        proc.terminate()
-        proc.wait(timeout)
-      except subprocess.TimeoutExpired:
-        proc.kill()
+    """Runs a test."""
+    start_time = time.monotonic()
+    env = dict(os.environ)
+    env['ASAN_OPTIONS'] = 'log_path=stderr'
+
+    with subprocess.Popen(
+        [path],
+        bufsize=0,
+        stdin=subprocess.PIPE,
+        stdout=subprocess.PIPE,
+        env=env,
+        encoding='utf-8',
+        errors='replace',
+    ) as proc:
+
+        # Put the output pipe in non-blocking mode. We will then select(2)
+        # on the pipe to know when we have bytes to process.
+        os.set_blocking(proc.stdout.fileno(), False)
+
+        try:
+            output_buffer = io.StringIO()
+            while True:
+                select_timeout = timeout - (time.monotonic() - start_time)
+                if select_timeout <= 0:
+                    return TestResult.TIMEOUT, output_buffer.getvalue()
+
+                readable, _, _ = select.select(
+                    [proc.stdout], [], [], select_timeout)
+
+                if not readable:
+                    # Indicates that select(2) timed out.
+                    return TestResult.TIMEOUT, output_buffer.getvalue()
+
+                output_buffer.write(proc.stdout.read())
+                output_log = output_buffer.getvalue()
+
+                if 'Pass!' in output_log:
+                    return TestResult.SUCCESS, output_log
+                if 'Fail!' in output_log:
+                    return TestResult.FAIL, output_log
+                if proc.poll():
+                    return TestResult.UNEXPECTED_TERMINATION, output_log
+        finally:
+            # Check if the process has exited. If not, send it a SIGTERM, wait
+            # for it to exit, and if it times out, kill the process directly.
+            if not proc.poll():
+                try:
+                    proc.terminate()
+                    proc.wait(timeout)
+                except subprocess.TimeoutExpired:
+                    proc.kill()
 
 
 def parse_options(argv):
-  parser = argparse.ArgumentParser()
-  parser.add_argument('-t', '--timeout', type=float, default=60,
-                      help='Timeout to kill test after.')
-  parser.add_argument('--coverage', action='store_const', const='coverage',
-                      default='host', dest='test_target',
-                      help='Flag if this is a code coverage test.')
-  parser.add_argument('test_name', type=str)
-  return parser.parse_args(argv)
+    """Parse command line flags."""
+    parser = argparse.ArgumentParser()
+    parser.add_argument('-t', '--timeout', type=float, default=120,
+                        help='Timeout to kill test after.')
+    parser.add_argument('--coverage', action='store_const', const='coverage',
+                        default='host', dest='test_target',
+                        help='Flag if this is a code coverage test.')
+    parser.add_argument('--verbose', '-v', action='store_true',
+                        help='Dump emulator output always, even if successful.')
+    parser.add_argument('test_name', type=str)
+    return parser.parse_args(argv)
 
 
 def main(argv):
-  opts = parse_options(argv)
+    """The main function."""
+    opts = parse_options(argv)
+
+    # Tests will be located in build/host, unless the --coverage flag was
+    # provided, in which case they will be in build/coverage.
+    exec_path = pathlib.Path('build', opts.test_target, opts.test_name,
+                             f'{opts.test_name}.exe')
+    if not exec_path.is_file():
+        print(f'No test named {opts.test_name} exists!')
+        return 1
 
-  # Tests will be located in build/host, unless the --coverage flag was
-  # provided, in which case they will be in build/coverage.
-  exec_path = pathlib.Path('build', opts.test_target, opts.test_name,
-                           f'{opts.test_name}.exe')
-  if not exec_path.is_file():
-    print(f'No test named {opts.test_name} exists!')
-    return 1
+    # Host tests that use persistence.c leave these files laying around.
+    for persist in pathlib.Path('/dev/shm').glob(
+            f'EC_persist_*_{opts.test_name}.exe_*'):
+        persist.unlink()
 
-  start_time = time.monotonic()
-  result, output = run_test(exec_path, timeout=opts.timeout)
-  elapsed_time = time.monotonic() - start_time
+    start_time = time.monotonic()
+    result, output = run_test(exec_path, timeout=opts.timeout)
+    elapsed_time = time.monotonic() - start_time
 
-  print('{} {}! ({:.3f} seconds)'.format(
-      opts.test_name, result.reason, elapsed_time),
-        file=sys.stderr)
+    print(f'{opts.test_name} {result.reason}! ({elapsed_time:.3f} seconds)',
+          file=sys.stderr)
 
-  if result is not TestResult.SUCCESS:
-    print('====== Emulator output ======', file=sys.stderr)
-    print(output.decode('utf-8'), file=sys.stderr)
-    print('=============================', file=sys.stderr)
-  return result.exit_code
+    if result is not TestResult.SUCCESS or opts.verbose:
+        print('====== Emulator output ======', file=sys.stderr)
+        print(output, file=sys.stderr)
+        print('=============================', file=sys.stderr)
+    return result.value
 
 
 if __name__ == '__main__':
-  sys.exit(main(sys.argv[1:]))
+    sys.exit(main(sys.argv[1:]))
diff --git a/util/run_tests.sh b/util/run_tests.sh
new file mode 100755
index 0000000000..729faf517d
--- /dev/null
+++ b/util/run_tests.sh
@@ -0,0 +1,32 @@
+#!/bin/bash
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Runs all the unit tests in the util dir. Uses relative paths, so don't run
+# from any ebuild.
+
+# Show commands being run.
+set -x
+
+# Exit if any command exits non-zero.
+set -e
+
+# cd to the ec directory.
+cd "$(dirname "$(realpath -e "${BASH_SOURCE[0]}")")"/..
+
+# Run pytest
+pytest util "$@"
+
+# Run shell tests
+cd util
+./test-inject-keys.sh
+
+# Run the Zephyr config tests
+# NOTE: this uses the Zephyr version of kconfiglib, runs separately from
+# test_kconfig_check.py
+pytest check_zephyr_project_config_unittest.py
+
+# Run the Zephyr check_compliance wrapper test.
+# NOTE: this uses vpython so it does not run correctly through pytest.
+./zephyr_check_compliance_unittest.py
diff --git a/util/shuffle_test.sh b/util/shuffle_test.sh
new file mode 100755
index 0000000000..dfbc1b7a15
--- /dev/null
+++ b/util/shuffle_test.sh
@@ -0,0 +1,59 @@
+#!/bin/bash
+
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+set +x
+
+if [ $# -ne 2 ]; then
+  echo "Usage: $0 <target> <error regex>"
+  exit 1
+fi
+
+target=$1
+pattern=$2
+
+zmake build --clobber "${target}" || exit 1
+
+echo "Searching for '${pattern}'..."
+found_errors=0
+loop_count=100
+start_time=$(date +%Y-%m-%d_%H.%M.%S)
+log_dir="/tmp"
+EXECUTABLE=./build/zephyr/${target}/build-singleimage/zephyr/zephyr.exe
+while [ "${loop_count}" -gt 0 ]; do
+  seed=${RANDOM}
+  log_file_prefix="${log_dir}"/shuffle_"${start_time}"_"${seed}"
+
+  echo "[$((100 - loop_count))] Using seed=${seed}"
+  error_count=$(timeout 150s "${EXECUTABLE}" -seed="${seed}" 2>&1 |
+    tee "${log_file_prefix}".log |
+    grep -c "${pattern}")
+  status=$?
+
+  result="0-matches"
+  if [ "${status}" -eq 124 ]; then
+    echo "    Timeout"
+    result="timed-out"
+  elif [ "${status}" -eq 0 ]; then
+    echo "    Error/timeout"
+    result="exit-code-${status}"
+  fi
+  if [ "${error_count}" -gt 0 ]; then
+    echo "    Found ${error_count} errors matching '${pattern}'"
+    result="${error_count}-matches"
+  fi
+
+  # Rename the log file to include the outcome
+  mv \
+    "${log_file_prefix}".log \
+    "${log_file_prefix}"_"${result}".log
+
+  found_errors=$((found_errors + error_count))
+  loop_count=$((loop_count - 1))
+done
+
+if [ "${found_errors}" -ne 0 ]; then
+  exit 1
+fi
diff --git a/util/sort_by_unconvered.py b/util/sort_by_unconvered.py
new file mode 100755
index 0000000000..217c613aaa
--- /dev/null
+++ b/util/sort_by_unconvered.py
@@ -0,0 +1,59 @@
+#!/usr/bin/python3
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Prints out the lines in an lcov info file in order by uncovered lines.
+
+For example to find the file with the most uncovered lines in herobrine (and
+therefore the likest easy win) run the coverage commands in zephyr/README.md
+and then run:
+
+util/sort_by_unconvered.py build/zephyr/herobrine_final.info | head
+"""
+
+import argparse
+import re
+import subprocess
+
+
+def main():
+    """Main function"""
+    parser = argparse.ArgumentParser(allow_abbrev=False)
+    parser.add_argument(
+        "lcov_files",
+        nargs="+",
+        metavar="lcov_file",
+        help="Name(s) of the lcov files to analyze",
+        default=[],
+    )
+    args = parser.parse_args()
+
+    cmd = ["lcov", "--list-full-path", "--list"] + args.lcov_files
+    output = subprocess.run(
+        cmd, check=True, stdout=subprocess.PIPE, universal_newlines=True
+    ).stdout
+
+    pattern = re.compile(r"^(/\S+)\s*\|\s*([0-9\.]*)%\s*(\d+)\s*\|")
+    results = []
+    for line in output.splitlines():
+        match = pattern.match(line)
+        if match:
+            results.append(
+                (
+                    match[1],  # Filename
+                    match[2],  # Percent
+                    int(match[3]),  # Total lines
+                    int(
+                        float(match[2]) * int(match[3]) / 100.0
+                    ),  # Covered Lines
+                )
+            )
+
+    results.sort(key=lambda x: x[2] - x[3], reverse=True)
+    for res in results:
+        print(f"{res[0]}: {res[3]}/{res[2]} ({res[1]}%)")
+
+
+if __name__ == "__main__":
+    main()
diff --git a/util/stm32mon.c b/util/stm32mon.c
deleted file mode 100644
index 6b3b0040be..0000000000
--- a/util/stm32mon.c
+++ /dev/null
@@ -1,1713 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * STM32 SoC system monitor interface tool
- * For Serial, implement protocol v2.0 as defined in:
- * http://www.st.com/st-web-ui/static/active/en/resource/technical/\
- * document/application_note/CD00264342.pdf
- *
- * For i2C, implement protocol v1.0 as defined in:
- * http://www.st.com/st-web-ui/static/active/en/resource/technical/\
- * document/application_note/DM00072315.pdf
- *
- * For SPI, implement protocol v1.1 as defined in:
- * https://www.st.com/resource/en/application_note/dm00081379.pdf
- */
-
-/* use cfmakeraw() */
-#define _DEFAULT_SOURCE /* Newer glibc */
-#define _BSD_SOURCE     /* Older glibc */
-
-#include <arpa/inet.h>
-#include <compile_time_macros.h>
-#include <errno.h>
-#include <fcntl.h>
-#include <getopt.h>
-#include <inttypes.h>
-#include <stdio.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/ioctl.h>
-#include <sys/stat.h>
-#include <linux/i2c-dev.h>
-#include <linux/spi/spidev.h>
-#include <termios.h>
-#include <time.h>
-#include <unistd.h>
-
-#include "ec_version.h"
-
-#define KBYTES_TO_BYTES		1024
-
-/*
- * Some Ubuntu versions do not export SPI_IOC_WR_MODE32 even though
- * the kernel shipped on those supports it.
- */
-#ifndef SPI_IOC_WR_MODE32
-#define SPI_IOC_WR_MODE32		_IOW(SPI_IOC_MAGIC, 5, __u32)
-#endif
-
-/* Monitor command set */
-#define CMD_INIT 0x7f    /* Starts the monitor */
-
-#define CMD_GETCMD   0x00 /* Gets the allowed commands */
-#define CMD_GETVER   0x01 /* Gets the bootloader version */
-#define CMD_GETID    0x02 /* Gets the Chip ID */
-#define CMD_READMEM  0x11 /* Reads memory */
-#define CMD_GO       0x21 /* Jumps to user code */
-#define CMD_WRITEMEM 0x31 /* Writes memory (SRAM or Flash) */
-#define CMD_ERASE    0x43 /* Erases n pages of Flash memory */
-#define CMD_EXTERASE 0x44 /* Erases n pages of Flash memory */
-#define CMD_NO_STRETCH_ERASE 0x45 /* Erases while sending busy frame */
-#define CMD_WP       0x63 /* Enables write protect */
-#define CMD_WU       0x73 /* Disables write protect */
-#define CMD_RP       0x82 /* Enables the read protection */
-#define CMD_RU       0x92 /* Disables the read protection */
-
-#define RESP_NACK        0x1f
-#define RESP_ACK         0x79 /* 0b 0111 1001 */
-#define RESP_BUSY        0x76
-#define RESP_DAMAGED_ACK 0xBC /* 0b 1011 1100, 1 bit shifted REST_ACK */
-
-/* SPI Start of Frame */
-#define SOF          0x5A
-
-/* Extended erase special parameters */
-#define ERASE_ALL    0xffff
-#define ERASE_BANK1  0xfffe
-#define ERASE_BANK2  0xfffd
-
-/* Upper bound of rebooting the monitor */
-#define MAX_DELAY_REBOOT 100000 /* us */
-
-/* Standard addresses common across various ST chips */
-#define STM32_MAIN_MEMORY_ADDR		0x08000000
-#define STM32_SYSTEM_MEMORY_ADDR	0x1FFF0000
-
-#define STM32_UNIQUE_ID_SIZE_BYTES	12
-
-/*
- * Device electronic signature contains factory-programmed identification
- * and calibration data to automatically match the characteristics of the
- * microcontroller.
- */
-struct stm32_device_signature {
-	/*
-	 * Address of the Unique Device ID register. This register contains a
-	 * 96-bit value that is unique across all chips.
-	 * Zero means ignore/unknown.
-	 */
-	uint32_t unique_device_id_addr;
-	/*
-	 * Address of the Flash Size register. This 16-bit register contains the
-	 * flash size in KB.
-	 * Zero means ignore/unknown.
-	 */
-	uint32_t flash_size_addr;
-	/*
-	 * Address of the Package Data register. This 16-bit register contains a
-	 * value that differentiates between package types of a given chip.
-	 * Zero means ignore/unknown.
-	 */
-	uint32_t package_data_addr;
-};
-
-struct memory_info {
-	/* Zero means ignore/unknown/not-applicable */
-	uint32_t addr;
-	/* If addr is non-zero
-	 * - zero here means value is dynamic and will be read from bootloader.
-	 * If addr is zero,
-	 * - zero here means ignore/unknown/not-applicable.
-	 */
-	uint32_t size_bytes;
-};
-
-struct memory_layout {
-	struct memory_info main_memory;
-	struct memory_info system_memory;
-	struct memory_info otp_area;
-	struct memory_info option_bytes;
-};
-
-/* known STM32 SoC parameters */
-struct stm32_def {
-	uint16_t   id;
-	const char *name;
-	uint32_t flash_size;
-	uint32_t page_size;
-	uint32_t cmds_len[2];
-	const struct memory_layout memory_layout;
-	const struct stm32_device_signature device_signature;
-} chip_defs[] = {
-	{0x416, "STM32L15xxB",   0x20000,   256, {13, 13}, { { 0 } }, { 0 } },
-	{0x429, "STM32L15xxB-A", 0x20000,   256, {13, 13}, { { 0 } }, { 0 } },
-	{0x427, "STM32L15xxC",   0x40000,   256, {13, 13}, { { 0 } }, { 0 } },
-	{0x435, "STM32L44xx",    0x40000,  2048, {13, 13}, { { 0 } }, { 0 } },
-	{0x420, "STM32F100xx",   0x20000,  1024, {13, 13}, { { 0 } }, { 0 } },
-	{0x410, "STM32F102R8",   0x10000,  1024, {13, 13}, { { 0 } }, { 0 } },
-	{0x440, "STM32F05x",     0x10000,  1024, {13, 13}, { { 0 } }, { 0 } },
-	{0x444, "STM32F03x",     0x08000,  1024, {13, 13}, { { 0 } }, { 0 } },
-	{0x448, "STM32F07xB",    0x20000,  2048, {13, 13}, { { 0 } }, { 0 } },
-	{0x432, "STM32F37xx",    0x40000,  2048, {13, 13}, { { 0 } }, { 0 } },
-	{0x442, "STM32F09x",     0x40000,  2048, {13, 13}, { { 0 } }, { 0 } },
-	{0x431, "STM32F411",     0x80000, 16384, {13, 19}, { { 0 } }, { 0 } },
-	{
-		.id =		0x441,
-		.name =		"STM32F412",
-		.flash_size =	0x100000,
-		.page_size =	16384,
-		.cmds_len =	{13, 19},
-		/*
-		 * STM32F412:
-		 * See https://www.st.com/resource/en/reference_manual/dm00180369.pdf
-		 * Section 3.3 Table 5 Flash module organization
-		 */
-		.memory_layout = {
-			.main_memory = {
-				.addr = STM32_MAIN_MEMORY_ADDR,
-				.size_bytes = 0, /* set by flash reg read */
-			},
-			.system_memory = {
-				.addr = STM32_SYSTEM_MEMORY_ADDR,
-				.size_bytes = 30 * KBYTES_TO_BYTES,
-			},
-			.otp_area = {
-				.addr = 0x1FFF7800,
-				.size_bytes = 528,
-			},
-			.option_bytes = {
-				.addr = 0x1FFFC000,
-				.size_bytes = 16,
-			}
-		},
-		/*
-		 * STM32F412:
-		 * See https://www.st.com/resource/en/reference_manual/dm00180369.pdf
-		 * Section 31 Device electronic signature
-		 */
-		.device_signature = {
-			.unique_device_id_addr =	0x1FFF7A10,
-			.flash_size_addr =		0x1FFF7A22,
-			/*
-			 * Out of range for bootloader on this chip, so we don't
-			 * attempt to read.
-			 */
-			.package_data_addr =		0, /* 0x1FFF7BF0 */
-		}
-	},
-	{0x450, "STM32H74x",    0x200000, 131768, {13, 19}, { { 0 } }, { 0 } },
-	{0x451, "STM32F76x",    0x200000, 32768, {13, 19}, { { 0 } }, { 0 } },
-	{
-		.id =		0x460,
-		.name =		"STM32G071xx",
-		.flash_size =	0x20000,
-		.page_size =	2048,
-		.cmds_len =	{13, 13},
-		/*
-		 * STM32G0x1:
-		 * See https://www.st.com/resource/en/reference_manual/dm00371828.pdf
-		 * Section 3.3.1 Table 6 Flash module organization
-		 */
-		.memory_layout = {
-			.main_memory = {
-				.addr = STM32_MAIN_MEMORY_ADDR,
-				.size_bytes = 0, /* set by flash reg read */
-			},
-			.system_memory = {
-				.addr = STM32_SYSTEM_MEMORY_ADDR,
-				.size_bytes = 28 * KBYTES_TO_BYTES,
-			},
-			.otp_area = {
-				.addr = 0x1FFF7000,
-				.size_bytes = 1024,
-			},
-			.option_bytes = {
-				.addr = 0x1FFF7800,
-				.size_bytes = 128,
-			}
-		},
-		/*
-		 * STM32G0x1:
-		 * See https://www.st.com/resource/en/reference_manual/dm00371828.pdf
-		 * Section 38 Device electronic signature
-		 */
-		.device_signature = {
-			.unique_device_id_addr =	0x1FFF7590,
-			.flash_size_addr =		0x1FFF75E0,
-			/*
-			 * Datasheet litst as same address as e.g. STM32F412,
-			 * hence declaring as zero as for that other chip.
-			 */
-			.package_data_addr =		0, /* 0x1FFF7500 */
-		}
-	},
-	{ 0 }
-};
-
-#define DEFAULT_CONNECT_RETRIES 5
-#define DEFAULT_TIMEOUT 4 /* seconds */
-#define EXT_ERASE_TIMEOUT 20 /* seconds */
-#define DEFAULT_BAUDRATE B38400
-#define PAGE_SIZE 256
-#define INVALID_I2C_ADAPTER -1
-#define MAX_ACK_RETRY_COUNT	(EXT_ERASE_TIMEOUT / DEFAULT_TIMEOUT)
-#define MAX_RETRY_COUNT		3
-
-enum interface_mode {
-	MODE_SERIAL,
-	MODE_I2C,
-	MODE_SPI,
-} mode = MODE_SERIAL;
-
-/* I2c address the EC is listening depends on the device:
- * stm32f07xxx: 0x76
- * stm32f411xx: 0x72
- */
-#define DEFAULT_I2C_SLAVE_ADDRESS 0x76
-
-/* store custom parameters */
-speed_t baudrate = DEFAULT_BAUDRATE;
-int connect_retries = DEFAULT_CONNECT_RETRIES;
-int i2c_adapter = INVALID_I2C_ADAPTER;
-const char *spi_adapter;
-int i2c_slave_address = DEFAULT_I2C_SLAVE_ADDRESS;
-uint8_t boot_loader_version;
-const char *serial_port = "/dev/ttyUSB1";
-const char *input_filename;
-const char *output_filename;
-uint32_t offset = 0x08000000, length = 0;
-int retry_on_damaged_ack;
-
-/* STM32MON function return values */
-enum {
-	STM32_SUCCESS   = 0,
-	STM32_EIO       = -1,	/* IO error */
-	STM32_EINVAL    = -2,	/* Got a faulty response from device */
-	STM32_ETIMEDOUT = -3,	/* Device didn't respond in a time window. */
-	STM32_ENOMEM    = -4,	/* Failed to allocate memory. */
-	STM32_ENACK     = -5,	/* Got NACK. */
-	STM32_EDACK     = -6,	/* Got a damanged ACK. */
-};
-BUILD_ASSERT(STM32_SUCCESS == 0);
-#define IS_STM32_ERROR(res)		((res) < STM32_SUCCESS)
-
-/* optional command flags */
-enum {
-	FLAG_UNPROTECT      = 0x01,
-	FLAG_ERASE          = 0x02,
-	FLAG_GO             = 0x04,
-	FLAG_READ_UNPROTECT = 0x08,
-	FLAG_CR50_MODE	    = 0x10,
-};
-
-typedef struct {
-	int size;
-	uint8_t *data;
-} payload_t;
-
-/* List all possible flash erase functions */
-typedef int command_erase_t(int fd, uint16_t count, uint16_t start);
-command_erase_t command_erase;
-command_erase_t command_ext_erase;
-command_erase_t command_erase_i2c;
-
-command_erase_t *erase;
-
-static void discard_input(int);
-
-#define MIN(a, b) ((a) < (b) ? (a) : (b))
-
-/* On user request save all data exchange with the target in this log file. */
-static FILE *log_file;
-
-/* Statistic data structure for response kind. */
-struct {
-	const char * const event_name;
-	uint32_t event_count;
-} stat_resp[] = {
-	{ "RESP_ACK",	0 },
-	{ "RESP_NACK",	0 },
-	{ "RESP_BUSY",	0 },
-	{ "RESP_DAMAGED_ACK", 0 },
-	{ "JUNK",	0 },
-};
-
-enum {
-	RESP_ACK_IDX = 0,
-	RESP_NACK_IDX,
-	RESP_BUSY_IDX,
-	RESP_DAMAGED_ACK_IDX,
-	JUNK_IDX,
-	MAX_EVENT_IDX
-};
-
-BUILD_ASSERT(ARRAY_SIZE(stat_resp) == MAX_EVENT_IDX);
-
-/*
- * Print data into the log file, in hex, 16 bytes per line, prefix the first
- * line with the value supplied by the caller (usually 'r' or 'w' for
- * read/write).
- */
-static void dump_log(const char *prefix, const void *data, size_t count)
-{
-	size_t i;
-
-	fprintf(log_file, "%s: ", prefix);
-	for (i = 0; i < count; i++) {
-		if (i && !(i  % 16))
-			fprintf(log_file, "\n   ");
-		fprintf(log_file, " %02x", ((uint8_t *)data)[i]);
-	}
-
-	if (count % 16)
-		fprintf(log_file, "\n");
-
-	/* Make sure all data is there even in case of aborts/crashes. */
-	fflush(log_file);
-}
-
-/*
- * Wrappers for standard library read() and write() functions. Add transferred
- * data to the log if log file is opened.
- */
-static ssize_t read_wrapper(int fd, void *buf, size_t count)
-{
-	ssize_t rv = read(fd, buf, count);
-
-	if (log_file && (rv > 0))
-		dump_log("r", buf, rv);
-
-	return rv;
-}
-
-static ssize_t write_wrapper(int fd, const void *buf, size_t count)
-{
-	ssize_t rv;
-
-	rv = write(fd, buf, count);
-
-	if (log_file && (rv > 0))
-		dump_log("w", buf, rv);
-
-	return rv;
-}
-
-int open_serial(const char *port, int cr50_mode)
-{
-	int fd, res;
-	struct termios cfg, cfg_copy;
-
-	fd = open(port, O_RDWR | O_NOCTTY);
-	if (fd == -1) {
-		perror("Unable to open serial port");
-		return -1;
-	}
-
-	/* put the tty in "raw" mode at the defined baudrate */
-	res = tcgetattr(fd, &cfg);
-	if (res == -1) {
-		perror("Cannot read tty attributes");
-		close(fd);
-		return -1;
-	}
-	cfmakeraw(&cfg);
-
-	/* Don't bother setting speed and parity when programming over Cr50. */
-	if (!cr50_mode) {
-		cfsetspeed(&cfg, baudrate);
-		/* serial mode should be 8e1 */
-		cfg.c_cflag |= PARENB;
-	}
-
-	/* 200 ms timeout */
-	cfg.c_cc[VTIME] = 2;
-	cfg.c_cc[VMIN] = 0;
-	memcpy(&cfg_copy, &cfg, sizeof(cfg_copy));
-
-	/*
-	 * tcsetattr() returns success if any of the modifications succeed, so
-	 * its return value of zero is not an indication of success, one needs
-	 * to check the result explicitly.
-	 */
-	tcsetattr(fd, TCSANOW, &cfg);
-	if (tcgetattr(fd, &cfg)) {
-		perror("Failed to re-read tty attributes");
-		close(fd);
-		return -1;
-	}
-
-	if (memcmp(&cfg, &cfg_copy, sizeof(cfg))) {
-		/*
-		 * On some systems the setting which does not come through is
-		 * the parity. We can try continuing without it when using
-		 * certain interfaces, let's try.
-		 */
-		cfg_copy.c_cflag &= ~PARENB;
-		if (memcmp(&cfg, &cfg_copy, sizeof(cfg))) {
-			/*
-			 * Something other than parity failed to get set, this
-			 * is an error.
-			 */
-			perror("Cannot set tty attributes");
-			close(fd);
-			return -1;
-		} else {
-			fprintf(stderr, "Failed to enable parity\n");
-		}
-	}
-
-	discard_input(fd); /* in case were were invoked soon after reset */
-	return fd;
-}
-
-int open_i2c(const int port)
-{
-	int fd;
-	char filename[20];
-
-	snprintf(filename, 19, "/dev/i2c-%d", port);
-	fd = open(filename, O_RDWR);
-	if (fd < 0) {
-		perror("Unable to open i2c adapter");
-		return -1;
-	}
-	if (ioctl(fd, I2C_SLAVE, i2c_slave_address >> 1) < 0) {
-		perror("Unable to select proper address");
-		close(fd);
-		return -1;
-	}
-
-	return fd;
-}
-
-int open_spi(const char *port)
-{
-	int fd;
-	int res;
-	uint32_t mode = SPI_MODE_0;
-	uint8_t bits = 8;
-
-	fd = open(port, O_RDWR);
-	if (fd == -1) {
-		perror("Unable to open SPI controller");
-		return -1;
-	}
-
-	res = ioctl(fd, SPI_IOC_WR_MODE32, &mode);
-	if (res == -1) {
-		perror("Cannot set SPI mode");
-		close(fd);
-		return -1;
-	}
-
-	res = ioctl(fd, SPI_IOC_WR_BITS_PER_WORD, &bits);
-	if (res == -1) {
-		perror("Cannot set SPI bits per word");
-		close(fd);
-		return -1;
-	}
-
-	return fd;
-}
-
-static void discard_input(int fd)
-{
-	uint8_t buffer[64];
-	int res, i;
-	int count_of_zeros;
-
-	/* Skip in i2c and spi modes */
-	if (mode != MODE_SERIAL)
-		return;
-
-	/* eat trailing garbage */
-	count_of_zeros = 0;
-	do {
-		res = read_wrapper(fd, buffer, sizeof(buffer));
-		if (res > 0) {
-
-			/* Discard zeros in the beginning of the buffer. */
-			for (i = 0; i < res; i++)
-				if (buffer[i])
-					break;
-
-			count_of_zeros += i;
-			if (i == res) {
-				/* Only zeros, nothing to print out. */
-				continue;
-			}
-
-			/* Discard zeros in the end of the buffer. */
-			while (!buffer[res - 1]) {
-				count_of_zeros++;
-				res--;
-			}
-
-			printf("Recv[%d]:", res - i);
-			for (; i < res; i++)
-				printf("%02x ", buffer[i]);
-			printf("\n");
-		}
-	} while (res > 0);
-
-	if (count_of_zeros)
-		printf("%d zeros ignored\n", count_of_zeros);
-}
-
-int wait_for_ack(int fd)
-{
-	uint8_t resp;
-	int res;
-	time_t deadline = time(NULL) + DEFAULT_TIMEOUT;
-	const uint8_t ack = RESP_ACK;
-
-	while (time(NULL) < deadline) {
-		res = read_wrapper(fd, &resp, 1);
-		if ((res < 0) && (errno != EAGAIN)) {
-			perror("Failed to read answer");
-			return STM32_EIO;
-		}
-
-		if (res != 1)
-			continue;
-
-		switch (resp) {
-		case RESP_ACK:
-			stat_resp[RESP_ACK_IDX].event_count++;
-			if (mode == MODE_SPI) /* Ack the ACK */
-				if (write_wrapper(fd, &ack, 1) != 1)
-					return STM32_EIO;
-			return STM32_SUCCESS;
-
-		case RESP_NACK:
-			stat_resp[RESP_NACK_IDX].event_count++;
-			fprintf(stderr, "NACK\n");
-			if (mode == MODE_SPI) /* Ack the NACK */
-				if (write_wrapper(fd, &ack, 1) != 1)
-					return STM32_EIO;
-			discard_input(fd);
-			return STM32_ENACK;
-
-		case RESP_BUSY:
-			stat_resp[RESP_BUSY_IDX].event_count++;
-			/* I2C Boot protocol 1.1 */
-			deadline = time(NULL) + DEFAULT_TIMEOUT;
-			break;
-
-		case RESP_DAMAGED_ACK:
-			if (retry_on_damaged_ack) {
-				/* It is a damaged ACK. However, device is
-				 * likely to believe it sent ACK, so let's not
-				 * treat it as junk.
-				 */
-				stat_resp[RESP_DAMAGED_ACK_IDX].event_count++;
-				fprintf(stderr, "DAMAGED_ACK\n");
-				return STM32_EDACK;
-			}
-
-			/* Do not break so that it can be handled as junk */
-		default:
-			stat_resp[JUNK_IDX].event_count++;
-			if (mode == MODE_SERIAL)
-				fprintf(stderr, "Receive junk: %02x\n", resp);
-			break;
-		}
-	}
-	fprintf(stderr, "Timeout\n");
-	return STM32_ETIMEDOUT;
-}
-
-int send_command(int fd, uint8_t cmd, payload_t *loads, int cnt,
-		 uint8_t *resp, int resp_size, int ack_requested)
-{
-	int res, i, c;
-	payload_t *p;
-	int readcnt = 0;
-	uint8_t cmd_frame[] = { SOF, cmd, 0xff ^ cmd }; /* XOR checksum */
-	/* only the SPI mode needs the Start Of Frame byte */
-	int cmd_off = mode == MODE_SPI ? 0 : 1;
-	int count_damaged_ack = 0;
-
-	/* Send the command index */
-	res = write_wrapper(fd, cmd_frame + cmd_off,
-			    sizeof(cmd_frame) - cmd_off);
-	if (res <= 0) {
-		perror("Failed to write command frame");
-		return STM32_EIO;
-	}
-
-	/* Wait for the ACK */
-	res = wait_for_ack(fd);
-	if (res == STM32_EDACK) {
-		++count_damaged_ack;
-	} else if (IS_STM32_ERROR(res)) {
-		fprintf(stderr, "Failed to get command 0x%02x ACK\n", cmd);
-		return res;
-	}
-
-	/* Send the command payloads */
-	for (p = loads, c = 0; c < cnt; c++, p++) {
-		uint8_t crc = 0;
-		int size = p->size;
-		uint8_t *data = malloc(size + 1), *data_ptr;
-
-		if (data == NULL) {
-			fprintf(stderr,
-				"Failed to allocate memory for load %d\n", c);
-			return STM32_ENOMEM;
-		}
-		memcpy(data, p->data, size);
-		for (i = 0; i < size; i++)
-			crc ^= data[i];
-		if (size == 1)
-			crc = 0xff ^ crc;
-		data[size] = crc;
-		size++;
-		data_ptr = data;
-		while (size) {
-			res = write_wrapper(fd, data_ptr, size);
-			if (res < 0) {
-				perror("Failed to write command payload");
-				free(data);
-				return STM32_EIO;
-			}
-			size -= res;
-			data_ptr += res;
-		}
-		free(data);
-
-		/* Wait for the ACK */
-		res = wait_for_ack(fd);
-		if (res == STM32_EDACK) {
-			++count_damaged_ack;
-		} else if (IS_STM32_ERROR(res)) {
-			if (res != STM32_ETIMEDOUT)
-				fprintf(stderr,
-					"payload %d ACK failed for CMD%02x\n",
-					c, cmd);
-			return res;
-		}
-	}
-
-	/* Read the answer payload */
-	if (resp) {
-		if (mode == MODE_SPI) /* ignore extra byte */
-			if (read_wrapper(fd, resp, 1) < 0)
-				return STM32_EIO;
-		while ((resp_size > 0) &&
-		       (res = read_wrapper(fd, resp, resp_size))) {
-			if (res < 0) {
-				perror("Failed to read payload");
-				return STM32_EIO;
-			}
-			readcnt += res;
-			resp += res;
-			resp_size -= res;
-		}
-
-		/* Wait for the ACK */
-		if (ack_requested) {
-			res = wait_for_ack(fd);
-			if (res == STM32_EDACK) {
-				++count_damaged_ack;
-			} else if (IS_STM32_ERROR(res)) {
-				fprintf(stderr,
-					"Failed to get response to command"
-					" 0x%02x ACK\n", cmd);
-				return res;
-			}
-		}
-	}
-
-	if (count_damaged_ack)
-		return STM32_EDACK;
-
-	return readcnt;
-}
-
-int send_command_retry(int fd, uint8_t cmd, payload_t *loads,
-		int cnt, uint8_t *resp, int resp_size, int ack_requested)
-{
-	int res;
-	int retries = MAX_RETRY_COUNT;
-
-	do {
-		int ack_tries = MAX_ACK_RETRY_COUNT;
-
-		res = send_command(fd, cmd, loads, cnt, resp, resp_size,
-			ack_requested);
-
-		while (res == STM32_ETIMEDOUT && ack_tries--) {
-			if (cmd == CMD_WRITEMEM) {
-				/* send garbage byte */
-				res = write_wrapper(fd, loads->data, 1);
-				/* Don't care much since it is a  garbage
-				 * transfer to let the device not wait for
-				 * any missing data, if any.
-				 */
-				if (res < 0)
-					fprintf(stderr, "warn: write failed\n");
-			}
-			res = wait_for_ack(fd);
-		}
-	} while ((res == STM32_ENACK || res == STM32_EDACK) && retries--);
-
-	return res;
-}
-
-struct stm32_def *command_get_id(int fd)
-{
-	int res;
-	uint8_t id[3];
-	uint16_t chipid;
-	struct stm32_def *def;
-
-	res = send_command(fd, CMD_GETID, NULL, 0, id, sizeof(id), 1);
-	if (res > 0) {
-		if (id[0] != 1) {
-			fprintf(stderr, "unknown ID : %02x %02x %02x\n",
-				id[0], id[1], id[2]);
-			return NULL;
-		}
-		chipid = (id[1] << 8) | id[2];
-		for (def = chip_defs; def->id; def++)
-			if (def->id == chipid)
-				break;
-		if (def->id == 0)
-			def = NULL;
-		printf("ChipID 0x%03x : %s\n", chipid, def ? def->name : "???");
-		return def;
-	}
-
-	return NULL;
-}
-
-int init_monitor(int fd)
-{
-	int res = 0;
-	int attempts = connect_retries + 1;
-	uint8_t init = mode == MODE_SPI ? SOF : CMD_INIT;
-
-	/* Skip in i2c mode */
-	if (mode == MODE_I2C)
-		return STM32_SUCCESS;
-
-	printf("Waiting for the monitor startup ...");
-	fflush(stdout);
-
-	while (connect_retries < 0 || attempts--) {
-		/* Send the command index */
-		res = write_wrapper(fd, &init, 1);
-		if (res <= 0) {
-			perror("Failed to write command");
-			return STM32_EIO;
-		}
-		/* Wait for the ACK */
-		res = wait_for_ack(fd);
-		if (res == STM32_SUCCESS)
-			break;
-		if (res == STM32_ENACK) {
-			/* we got NACK'ed, the loader might be already started
-			 * let's ping it to check
-			 */
-			if (command_get_id(fd)) {
-				printf("Monitor already started.\n");
-				return STM32_SUCCESS;
-			}
-		}
-		if (IS_STM32_ERROR(res) && res != STM32_ETIMEDOUT)
-			return res;
-		fflush(stdout);
-	}
-
-	if (IS_STM32_ERROR(res)) {
-		printf("Giving up after %d attempts.\n", connect_retries + 1);
-		return res;
-	}
-
-	printf("Done.\n");
-
-	/* read trailing chars */
-	discard_input(fd);
-
-	return STM32_SUCCESS;
-}
-
-int command_get_commands(int fd, struct stm32_def *chip)
-{
-	int res, i;
-	uint8_t cmds[64];
-
-	/*
-	 * For i2c, we have to request the exact amount of bytes we expect.
-	 */
-	res = send_command(fd, CMD_GETCMD, NULL, 0, cmds,
-			   chip->cmds_len[(mode == MODE_I2C ? 1 : 0)], 1);
-	if (res > 0) {
-		if (cmds[0] > sizeof(cmds) - 2) {
-			fprintf(stderr, "invalid GET answer (%02x...)\n",
-				cmds[0]);
-			return STM32_EINVAL;
-		}
-		printf("Bootloader v%d.%d, commands : ",
-		       cmds[1] >> 4, cmds[1] & 0xf);
-		boot_loader_version = cmds[1];
-
-		erase = command_erase;
-		for (i = 2; i < 2 + cmds[0]; i++) {
-			if (cmds[i] == CMD_EXTERASE)
-				erase = command_ext_erase;
-			printf("%02x ", cmds[i]);
-		}
-
-		if (mode == MODE_I2C)
-			erase = command_erase_i2c;
-		printf("\n");
-
-		return STM32_SUCCESS;
-	}
-
-	fprintf(stderr, "Cannot get bootloader command list.\n");
-	return STM32_EINVAL;
-}
-
-static int use_progressbar;
-static int windex;
-static const char wheel[] = {'|', '/', '-', '\\' };
-static void draw_spinner(uint32_t remaining, uint32_t size)
-{
-	int percent = (size - remaining)*100/size;
-	if (use_progressbar) {
-		int dots = percent / 4;
-
-		while (dots > windex) {
-			putchar('#');
-			windex++;
-		}
-	} else {
-		printf("\r%c%3d%%", wheel[windex++], percent);
-		windex %= sizeof(wheel);
-	}
-	fflush(stdout);
-}
-
-int command_read_mem(int fd, uint32_t address, uint32_t size, uint8_t *buffer)
-{
-	int res;
-	uint32_t remaining = size;
-	uint32_t addr_be;
-	uint8_t cnt;
-	payload_t loads[2] = {
-		{4, (uint8_t *)&addr_be},
-		{1, &cnt}
-	};
-
-	while (remaining) {
-		uint32_t bytes = MIN(remaining, PAGE_SIZE);
-
-		cnt = (uint8_t) (bytes - 1);
-		addr_be = htonl(address);
-
-		draw_spinner(remaining, size);
-
-		res = send_command_retry(fd, CMD_READMEM, loads, 2, buffer,
-					 bytes, 0);
-		if (IS_STM32_ERROR(res))
-			return STM32_EIO;
-
-		buffer += bytes;
-		address += bytes;
-		remaining -= bytes;
-	}
-
-	return size;
-}
-
-int command_write_mem(int fd, uint32_t address, uint32_t size, uint8_t *buffer)
-{
-	int res = 0;
-	int i;
-	uint32_t remaining = size;
-	uint32_t addr_be;
-	uint32_t cnt;
-	uint8_t outbuf[257];
-	payload_t loads[2] = {
-		{4, (uint8_t *)&addr_be},
-		{sizeof(outbuf), outbuf}
-	};
-
-	while (remaining) {
-		cnt = MIN(remaining, PAGE_SIZE);
-		/* skip empty blocks to save time */
-		for (i = 0; i < cnt && buffer[i] == 0xff; i++)
-			;
-		if (i != cnt) {
-			addr_be = htonl(address);
-			outbuf[0] = cnt - 1;
-			loads[1].size = cnt + 1;
-			memcpy(outbuf + 1, buffer, cnt);
-
-			draw_spinner(remaining, size);
-
-			res = send_command_retry(fd, CMD_WRITEMEM, loads, 2,
-					   NULL, 0, 1);
-			if (IS_STM32_ERROR(res))
-				return STM32_EIO;
-		}
-		buffer += cnt;
-		address += cnt;
-		remaining -= cnt;
-	}
-
-	return size;
-}
-
-int command_ext_erase(int fd, uint16_t count, uint16_t start)
-{
-	int res;
-	uint16_t count_be = htons(count);
-	payload_t load = { 2, (uint8_t *)&count_be };
-	uint16_t *pages = NULL;
-
-	if (count < 0xfff0) {
-		int i;
-		/* not a special value : build a list of pages */
-		load.size = 2 * (count + 1);
-		pages = malloc(load.size);
-		if (!pages)
-			return STM32_ENOMEM;
-		load.data = (uint8_t *)pages;
-		pages[0] = htons(count - 1);
-		for (i = 0; i < count; i++)
-			pages[i+1] = htons(start + i);
-	}
-
-	printf("Erasing...\n");
-	res = send_command_retry(fd, CMD_EXTERASE, &load, 1, NULL, 0, 1);
-	if (!IS_STM32_ERROR(res))
-		printf("Flash erased.\n");
-
-	if (pages)
-		free(pages);
-	return res;
-}
-
-int command_erase_i2c(int fd, uint16_t count, uint16_t start)
-{
-	int res;
-	uint8_t erase_cmd;
-	uint16_t count_be = htons(count);
-	payload_t load[2] = {
-		{ 2, (uint8_t *)&count_be},
-		{ 0, NULL},
-	};
-	int load_cnt = 1;
-	uint16_t *pages = NULL;
-
-	if (count < 0xfff) {
-		int i;
-		/* not a special value : build a list of pages */
-		/*
-		 * I2c protocol requires 2 messages, the count has to be acked
-		 * before the addresses can be sent.
-		 * TODO(gwendal): Still broken on i2c.
-		 */
-		load_cnt = 2;
-		load[1].size = 2 * count;
-		pages = malloc(load[1].size);
-		if (!pages)
-			return STM32_ENOMEM;
-		load[1].data = (uint8_t *)pages;
-		count_be = htons(count - 1);
-		for (i = 0; i < count; i++)
-			pages[i] = htons(start + i);
-	}
-
-	erase_cmd = (boot_loader_version == 0x10) ? CMD_EXTERASE :
-		     CMD_NO_STRETCH_ERASE;
-
-	printf("Erasing...\n");
-	res = send_command(fd, erase_cmd, load, load_cnt, NULL, 0, 1);
-	if (!IS_STM32_ERROR(res))
-		printf("Flash erased.\n");
-
-	if (pages)
-		free(pages);
-	return res;
-}
-
-
-int command_erase(int fd, uint16_t count, uint16_t start)
-{
-	int res;
-	uint8_t count_8bit = count;
-	payload_t load = { 1, &count_8bit };
-	uint8_t *pages = NULL;
-
-	if (count < 0xff) {
-		int i;
-		/* not a special value : build a list of pages */
-		load.size = count + 1;
-		pages = malloc(load.size);
-		if (!pages)
-			return STM32_ENOMEM;
-		load.data = (uint8_t *)pages;
-		pages[0] = count - 1;
-		for (i = 0; i < count; i++)
-			pages[i+1] = start + i;
-	}
-
-	printf("Erasing...\n");
-	res = send_command(fd, CMD_ERASE, &load, 1, NULL, 0, 1);
-	if (!IS_STM32_ERROR(res))
-		printf("Flash erased.\n");
-
-	if (pages)
-		free(pages);
-	return res;
-}
-
-int command_read_unprotect(int fd)
-{
-	int res;
-	int retries = MAX_RETRY_COUNT;
-
-	printf("Unprotecting flash read...\n");
-
-	res = send_command(fd, CMD_RU, NULL, 0, NULL, 0, 1);
-	/*
-	 * Read unprotect can trigger a mass erase, which can take long time
-	 * (e.g. 13s+ on STM32H7)
-	 */
-	do {
-		res = wait_for_ack(fd);
-	} while ((res == STM32_ETIMEDOUT) && --retries);
-
-	if (IS_STM32_ERROR(res)) {
-		fprintf(stderr, "Failed to get read-protect ACK\n");
-		return res;
-	}
-	printf("Flash read unprotected.\n");
-
-	/*
-	 * This command triggers a reset.
-	 *
-	 * Wait at least the reboot delay, else we could reconnect
-	 * before the actual reset depending on the bootloader.
-	 */
-	usleep(MAX_DELAY_REBOOT);
-	if (IS_STM32_ERROR(init_monitor(fd))) {
-		fprintf(stderr, "Cannot recover after RU reset\n");
-		return STM32_EIO;
-	}
-
-	return STM32_SUCCESS;
-}
-
-int command_write_unprotect(int fd)
-{
-	int res;
-
-	res = send_command(fd, CMD_WU, NULL, 0, NULL, 0, 1);
-	if (IS_STM32_ERROR(res))
-		return STM32_EIO;
-
-	/* Wait for the ACK */
-	if (wait_for_ack(fd) < 0) {
-		fprintf(stderr, "Failed to get write-protect ACK\n");
-		return STM32_EINVAL;
-	}
-	printf("Flash write unprotected.\n");
-
-	/*
-	 * This command triggers a reset.
-	 *
-	 * Wait at least the reboot delay, else we could reconnect
-	 * before the actual reset depending on the bootloader.
-	 */
-	usleep(MAX_DELAY_REBOOT);
-	if (IS_STM32_ERROR(init_monitor(fd))) {
-		fprintf(stderr, "Cannot recover after WP reset\n");
-		return STM32_EIO;
-	}
-
-	return STM32_SUCCESS;
-}
-
-int command_go(int fd, uint32_t address)
-{
-	int res;
-	uint32_t addr_be = htonl(address);
-	payload_t load = { 4, (uint8_t *)&addr_be };
-
-	res = send_command(fd, CMD_GO, &load, 1, NULL, 0, 1);
-	if (IS_STM32_ERROR(res))
-		return STM32_EIO;
-
-#if 0 /* this ACK should exist according to the documentation ... */
-	/* Wait for the ACK */
-	if (wait_for_ack(fd) < 0) {
-		fprintf(stderr, "Failed to get GO ACK\n");
-		return -EINVAL;
-	}
-#endif
-
-	printf("Program started at 0x%08x.\n", address);
-	return STM32_SUCCESS;
-}
-
-/*
- * The bootloader does not allow reading directly from the "device signature"
- * registers. However, it does allow reading the OTP region, so this function
- * starts a read from the last byte in that region and reads an additional
- * number of bytes to read the requested register.
- *
- * Example:
- *
- * Given a chip with OTP region starting at address 0x1FFF7800 with a size of
- * 528 bytes and a register that we want to read at address 0x1FFF7A10 with a
- * size of 12 bytes:
- *
- * We start the read at the last byte in the OTP region:
- *
- * 0x1FFF7800 + 528 - 1 = 0x1FFF7A0F
- *
- * From 0x1FFF7A0F we perform a read of (12 + 1) = 13 bytes in order to read the
- * 12 bytes starting at 0x1FFF7A10 (the actual register we care about).
- *
- * Returns zero on success, negative on failure.
- */
-int read_device_signature_register(int fd, const struct stm32_def *chip,
-				   uint32_t addr, uint32_t size_bytes,
-				   uint8_t *out_buffer)
-{
-	int res;
-	uint8_t *buffer;
-	struct memory_info otp = chip->memory_layout.otp_area;
-	uint32_t otp_end_addr = otp.addr + otp.size_bytes - 1;
-	uint32_t offset = addr - otp_end_addr;
-	uint32_t read_size_bytes = offset + size_bytes;
-
-	if (!otp.addr) {
-		fprintf(stderr, "No otp_area.addr specified for given chip.\n");
-		return STM32_EINVAL;
-	}
-
-	if (addr <= otp_end_addr) {
-		fprintf(stderr, "Attempting to read from invalid address: "
-				"%08X\n", addr);
-		return STM32_EINVAL;
-	}
-
-	/*
-	 * The USART/SPI/I2C bootloader can only read at most 256 bytes in a
-	 * single read command (see AN4286 section 2.5 or AN3155 section 3.4).
-	 *
-	 * command_read_mem will correctly chunk larger requests, but the
-	 * subsequent reads will fail because the bootloader won't allow reads
-	 * from a starting address that is beyond the OTP region.
-	 */
-	if (read_size_bytes > PAGE_SIZE) {
-		fprintf(stderr,
-			"Requested register 0x%08X is outside read range.\n",
-			addr);
-		return STM32_EINVAL;
-	}
-
-	buffer = malloc(read_size_bytes);
-	if (!buffer) {
-		fprintf(stderr, "Cannot allocate %" PRIu32 " bytes\n",
-			read_size_bytes);
-		return STM32_ENOMEM;
-	}
-
-	res = command_read_mem(fd, otp_end_addr, read_size_bytes, buffer);
-	if (res == read_size_bytes)
-		memcpy(out_buffer, buffer + offset, size_bytes);
-	else
-		fprintf(stderr,
-			"Cannot read %" PRIu32 " bytes from address 0x%08X",
-			read_size_bytes, otp_end_addr);
-
-	free(buffer);
-	return IS_STM32_ERROR(res) ? res : STM32_SUCCESS;
-}
-
-/* Return zero on success, a negative error value on failures. */
-int read_flash_size_register(int fd, struct stm32_def *chip,
-			     uint16_t *flash_size_kbytes)
-{
-	int res;
-	uint32_t flash_size_addr = chip->device_signature.flash_size_addr;
-
-	if (!flash_size_addr)
-		return STM32_EINVAL;
-
-	res = read_device_signature_register(fd, chip,
-		flash_size_addr, sizeof(*flash_size_kbytes),
-		(uint8_t *)flash_size_kbytes);
-
-	if (!IS_STM32_ERROR(res))
-		printf("Flash size: %" PRIu16 " KB\n", *flash_size_kbytes);
-	else
-		fprintf(stderr,
-			"Unable to read flash size register (0x%08X).\n",
-			flash_size_addr);
-
-	return res;
-}
-
-/* Return zero on success, a negative error value on failures. */
-int read_unique_device_id_register(int fd, struct stm32_def *chip,
-	uint8_t device_id[STM32_UNIQUE_ID_SIZE_BYTES])
-{
-	int i;
-	int res;
-	uint32_t unique_device_id_addr =
-		chip->device_signature.unique_device_id_addr;
-
-	if (!unique_device_id_addr)
-		return STM32_EINVAL;
-
-	res = read_device_signature_register(fd, chip, unique_device_id_addr,
-		STM32_UNIQUE_ID_SIZE_BYTES, device_id);
-
-	if (!IS_STM32_ERROR(res)) {
-		printf("Unique Device ID: 0x");
-		for (i = STM32_UNIQUE_ID_SIZE_BYTES - 1; i >= 0; i--)
-			printf("%02X", device_id[i]);
-		printf("\n");
-	} else {
-		fprintf(stderr,
-			"Unable to read unique device ID register (0x%08X). "
-			"Ignoring non-critical failure.\n",
-			unique_device_id_addr);
-	}
-
-	return res;
-}
-
-/* Return zero on success, a negative error value on failures. */
-int read_package_data_register(int fd, struct stm32_def *chip,
-			       uint16_t *package_data)
-{
-	int res;
-	uint32_t package_data_addr = chip->device_signature.package_data_addr;
-
-	if (!package_data_addr)
-		return STM32_EINVAL;
-
-	res = read_device_signature_register(fd, chip, package_data_addr,
-					     sizeof(*package_data),
-					     (uint8_t *)package_data);
-
-	if (!IS_STM32_ERROR(res))
-		printf("Package data register: %04X\n", *package_data);
-	else
-		fprintf(stderr,
-			"Failed to read package data register (0x%08X). "
-			"Ignoring non-critical failure.\n", package_data_addr);
-
-	return res;
-}
-
-/* Return zero on success, a negative error value on failures. */
-int read_flash(int fd, struct stm32_def *chip, const char *filename,
-	       uint32_t offset, uint32_t size)
-{
-	int res;
-	FILE *hnd;
-	uint8_t *buffer;
-
-	if (!size)
-		size = chip->flash_size;
-	buffer = malloc(size);
-	if (!buffer) {
-		fprintf(stderr, "Cannot allocate %d bytes\n", size);
-		return STM32_ENOMEM;
-	}
-
-	hnd = fopen(filename, "w");
-	if (!hnd) {
-		fprintf(stderr, "Cannot open file %s for writing\n", filename);
-		free(buffer);
-		return STM32_EIO;
-	}
-
-	printf("Reading %d bytes at 0x%08x\n", size, offset);
-	res = command_read_mem(fd, offset, size, buffer);
-	if (res > 0) {
-		if (fwrite(buffer, res, 1, hnd) != 1)
-			fprintf(stderr, "Cannot write %s\n", filename);
-	}
-	printf("\r   %d bytes read.\n", res);
-
-	fclose(hnd);
-	free(buffer);
-	return IS_STM32_ERROR(res) ? res : STM32_SUCCESS;
-}
-
-/* Return zero on success, a negative error value on failures. */
-int write_flash(int fd, struct stm32_def *chip, const char *filename,
-		uint32_t offset)
-{
-	int res, written;
-	FILE *hnd;
-	int size = chip->flash_size;
-	uint8_t *buffer = malloc(size);
-
-	if (!buffer) {
-		fprintf(stderr, "Cannot allocate %d bytes\n", size);
-		return STM32_ENOMEM;
-	}
-
-	if (!strncmp(filename, "-", sizeof("-")))
-		hnd = fdopen(STDIN_FILENO, "r");
-	else
-		hnd = fopen(filename, "r");
-	if (!hnd) {
-		fprintf(stderr, "Cannot open file %s for reading\n", filename);
-		free(buffer);
-		return STM32_EIO;
-	}
-	res = fread(buffer, 1, size, hnd);
-	fclose(hnd);
-	if (res <= 0) {
-		fprintf(stderr, "Cannot read %s\n", filename);
-		free(buffer);
-		return STM32_EIO;
-	}
-
-	/* faster write: skip empty trailing space */
-	while (res && buffer[res - 1] == 0xff)
-		res--;
-	/* ensure 'res' is multiple of 4 given 'size' is and res <= size */
-	res = (res + 3) & ~3;
-
-	printf("Writing %d bytes at 0x%08x\n", res, offset);
-	written = command_write_mem(fd, offset, res, buffer);
-	if (written != res) {
-		fprintf(stderr, "Error writing to flash\n");
-		free(buffer);
-		return STM32_EIO;
-	}
-	printf("\r   %d bytes written.\n", written);
-
-	free(buffer);
-	return STM32_SUCCESS;
-}
-
-static const struct option longopts[] = {
-	{"adapter", 1, 0, 'a'},
-	{"baudrate", 1, 0, 'b'},
-	{"cr50", 0, 0, 'c'},
-	{"device", 1, 0, 'd'},
-	{"erase", 0, 0, 'e'},
-	{"go", 0, 0, 'g'},
-	{"help", 0, 0, 'h'},
-	{"length", 1, 0, 'n'},
-	{"location", 1, 0, 'l'},
-	{"logfile", 1, 0, 'L'},
-	{"offset", 1, 0, 'o'},
-	{"progressbar", 0, 0, 'p'},
-	{"read", 1, 0, 'r'},
-	{"retries", 1, 0, 'R'},
-	{"spi", 1, 0, 's'},
-	{"unprotect", 0, 0, 'u'},
-	{"version", 0, 0, 'v'},
-	{"write", 1, 0, 'w'},
-	{NULL, 0, 0, 0}
-};
-
-void display_usage(char *program)
-{
-	fprintf(stderr,
-		"Usage: %s [-a <i2c_adapter> [-l address ]] | [-s]"
-		" [-d <tty>] [-b <baudrate>]] [-u] [-e] [-U]"
-		" [-r <file>] [-w <file>] [-o offset] [-n length] [-g] [-p]"
-		" [-L <log_file>] [-c] [-v]\n",
-		program);
-	fprintf(stderr, "Can access the controller via serial port or i2c\n");
-	fprintf(stderr, "Serial port mode:\n");
-	fprintf(stderr, "--d[evice] <tty> : use <tty> as the serial port\n");
-	fprintf(stderr, "--b[audrate] <baudrate> : set serial port speed "
-			"to <baudrate> bauds\n");
-	fprintf(stderr, "i2c mode:\n");
-	fprintf(stderr, "--a[dapter] <id> : use i2c adapter <id>.\n");
-	fprintf(stderr, "--l[ocation]  <address> : use address <address>.\n");
-	fprintf(stderr, "--s[pi]: use spi mode.\n");
-	fprintf(stderr, "--u[nprotect] : remove flash write protect\n");
-	fprintf(stderr, "--U[nprotect] : remove flash read protect\n");
-	fprintf(stderr, "--e[rase] : erase all the flash content\n");
-	fprintf(stderr, "--r[ead] <file> : read the flash content and "
-			"write it into <file>\n");
-	fprintf(stderr, "--s[pi] </dev/spi> : use SPI adapter on </dev>.\n");
-	fprintf(stderr, "--w[rite] <file|-> : read <file> or\n\t"
-			"standard input and write it to flash\n");
-	fprintf(stderr, "--o[ffset] : offset to read/write/start from/to\n");
-	fprintf(stderr, "--n[length] : amount to read/write\n");
-	fprintf(stderr, "--g[o] : jump to execute flash entrypoint\n");
-	fprintf(stderr, "--p[rogressbar] : use a progress bar instead of "
-			"the spinner\n");
-	fprintf(stderr, "--R[etries] <num> : limit connect retries to num\n");
-	fprintf(stderr, "-L[ogfile] <file> : save all communications exchange "
-		"in a log file\n");
-	fprintf(stderr, "-c[r50_mode] : consider device to be a Cr50 interface,"
-		" no need to set UART port attributes\n");
-	fprintf(stderr, "--v[ersion] : print version and exit\n");
-
-	exit(2);
-}
-
-void display_version(const char *exe_name)
-{
-	printf("%s version: %s %s %s\n", exe_name, CROS_STM32MON_VERSION, DATE,
-		BUILDER);
-}
-
-speed_t parse_baudrate(const char *value)
-{
-	int rate = atoi(value);
-
-	switch (rate) {
-	case 9600:
-		return B9600;
-	case 19200:
-		return B19200;
-	case 38400:
-		return B38400;
-	case 57600:
-		return B57600;
-	case 115200:
-		return B115200;
-	default:
-		fprintf(stderr, "Invalid baudrate %s, using %d\n",
-			value, DEFAULT_BAUDRATE);
-		return DEFAULT_BAUDRATE;
-	}
-}
-
-int parse_parameters(int argc, char **argv)
-{
-	int opt, idx;
-	int flags = 0;
-	const char *log_file_name = NULL;
-
-	while ((opt = getopt_long(argc, argv, "a:l:b:cd:eghL:n:o:pr:R:s:w:uUv?",
-				  longopts, &idx)) != -1) {
-		switch (opt) {
-		case 'a':
-			i2c_adapter = atoi(optarg);
-			mode = MODE_I2C;
-			break;
-		case 'l':
-			i2c_slave_address = strtol(optarg, NULL, 0);
-			break;
-		case 'b':
-			baudrate = parse_baudrate(optarg);
-			break;
-		case 'c':
-			flags |= FLAG_CR50_MODE;
-			break;
-		case 'd':
-			serial_port = optarg;
-			mode = MODE_SERIAL;
-			break;
-		case 'e':
-			flags |= FLAG_ERASE;
-			break;
-		case 'g':
-			flags |= FLAG_GO;
-			break;
-		case 'h':
-		case '?':
-			display_usage(argv[0]);
-			break;
-		case 'L':
-			log_file_name = optarg;
-			break;
-		case 'n':
-			length = strtol(optarg, NULL, 0);
-			break;
-		case 'o':
-			offset = strtol(optarg, NULL, 0);
-			break;
-		case 'p':
-			use_progressbar = 1;
-			break;
-		case 'r':
-			input_filename = optarg;
-			break;
-		case 'R':
-			connect_retries = atoi(optarg);
-			break;
-		case 's':
-			spi_adapter = optarg;
-			mode = MODE_SPI;
-			break;
-		case 'w':
-			output_filename = optarg;
-			break;
-		case 'u':
-			flags |= FLAG_UNPROTECT;
-			break;
-		case 'U':
-			flags |= FLAG_READ_UNPROTECT;
-			break;
-		case 'v':
-			display_version(argv[0]);
-			exit(0);
-		}
-	}
-
-	if (log_file_name) {
-		log_file = fopen(log_file_name, "w");
-		if (!log_file) {
-			fprintf(stderr, "failed to open %s for writing\n",
-				log_file_name);
-			exit(2);
-		}
-	}
-	return flags;
-}
-
-static void display_stat_response(void)
-{
-	uint32_t total_events = MAX_EVENT_IDX;
-	uint32_t idx;
-
-	printf("--\n");
-	for (idx = 0; idx < total_events; ++idx) {
-		printf("%-18s %d\n", stat_resp[idx].event_name,
-				stat_resp[idx].event_count);
-	}
-	printf("--\n");
-}
-
-int main(int argc, char **argv)
-{
-	int ser;
-	struct stm32_def *chip;
-	int ret = STM32_EIO;
-	int res;
-	int flags;
-	uint16_t flash_size_kbytes = 0;
-	uint8_t unique_device_id[STM32_UNIQUE_ID_SIZE_BYTES] = { 0 };
-	uint16_t package_data_reg = 0;
-
-	/* Parse command line options */
-	flags = parse_parameters(argc, argv);
-
-	display_version(argv[0]);
-
-	retry_on_damaged_ack = !!(flags & FLAG_CR50_MODE);
-
-	switch (mode) {
-	case MODE_SPI:
-		ser = open_spi(spi_adapter);
-		break;
-	case MODE_I2C:
-		ser = open_i2c(i2c_adapter);
-		break;
-	case MODE_SERIAL:
-	default:
-		/* Open the serial port tty */
-		ser = open_serial(serial_port, !!(flags & FLAG_CR50_MODE));
-	}
-	if (ser < 0)
-		return 1;
-	/* Trigger embedded monitor detection */
-	res = init_monitor(ser);
-	if (IS_STM32_ERROR(res))
-		goto terminate;
-
-	chip = command_get_id(ser);
-	if (!chip)
-		goto terminate;
-
-	/*
-	 * Use the actual size if we were able to read it since some chips
-	 * have the same chip ID, but different flash sizes based on the
-	 * package.
-	 */
-	res = read_flash_size_register(ser, chip, &flash_size_kbytes);
-	if (!IS_STM32_ERROR(res))
-		chip->flash_size = flash_size_kbytes * KBYTES_TO_BYTES;
-
-	/*
-	 * This is simply informative at the moment, so we don't care about the
-	 * return value.
-	 */
-	(void)read_unique_device_id_register(ser, chip, unique_device_id);
-
-	/*
-	 * This is simply informative at the moment, so we don't care about the
-	 * return value.
-	 */
-	(void)read_package_data_register(ser, chip, &package_data_reg);
-
-	if (command_get_commands(ser, chip) < 0)
-		goto terminate;
-
-	if (flags & FLAG_READ_UNPROTECT)
-		command_read_unprotect(ser);
-	if (flags & FLAG_UNPROTECT)
-		command_write_unprotect(ser);
-
-	if (flags & FLAG_ERASE || output_filename) {
-		if ((!strncmp("STM32L15", chip->name, 8)) ||
-		    (!strncmp("STM32F411", chip->name, 9))) {
-			/* Mass erase is not supported on these chips*/
-			int i, page_count = chip->flash_size / chip->page_size;
-			for (i = 0; i < page_count; i += 128) {
-				int count = MIN(128, page_count - i);
-				ret = erase(ser, count, i);
-				if (IS_STM32_ERROR(ret))
-					goto terminate;
-			}
-		} else {
-			ret = erase(ser, 0xFFFF, 0);
-			if (IS_STM32_ERROR(ret))
-				goto terminate;
-		}
-	}
-
-	if (input_filename) {
-		ret = read_flash(ser, chip, input_filename, offset, length);
-		if (IS_STM32_ERROR(ret))
-			goto terminate;
-	}
-
-	if (output_filename) {
-		ret = write_flash(ser, chip, output_filename, offset);
-		if (IS_STM32_ERROR(ret))
-			goto terminate;
-	}
-
-	/* Run the program from flash */
-	if (flags & FLAG_GO)
-		command_go(ser, offset);
-
-	/* Normal exit */
-	ret = STM32_SUCCESS;
-terminate:
-	if (log_file)
-		fclose(log_file);
-
-	/* Close serial port */
-	close(ser);
-
-	if (retry_on_damaged_ack)
-		display_stat_response();
-
-	if (IS_STM32_ERROR(ret)) {
-		fprintf(stderr, "Failed: %d\n", ret);
-		return 1;
-	}
-
-	printf("Done.\n");
-	return 0;
-}
diff --git a/util/stm32mon.cc b/util/stm32mon.cc
new file mode 100644
index 0000000000..561201f213
--- /dev/null
+++ b/util/stm32mon.cc
@@ -0,0 +1,1742 @@
+/* Copyright 2012 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * STM32 SoC system monitor interface tool
+ * For Serial, implement protocol v2.0 as defined in:
+ * http://www.st.com/st-web-ui/static/active/en/resource/technical/\
+ * document/application_note/CD00264342.pdf
+ *
+ * For i2C, implement protocol v1.0 as defined in:
+ * http://www.st.com/st-web-ui/static/active/en/resource/technical/\
+ * document/application_note/DM00072315.pdf
+ *
+ * For SPI, implement protocol v1.1 as defined in:
+ * https://www.st.com/resource/en/application_note/dm00081379.pdf
+ */
+
+/* use cfmakeraw() */
+#define _DEFAULT_SOURCE /* Newer glibc */
+#define _BSD_SOURCE /* Older glibc */
+
+#include "ec_version.h"
+
+#include <errno.h>
+#include <inttypes.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <time.h>
+
+#include <arpa/inet.h>
+#include <compile_time_macros.h>
+#include <fcntl.h>
+#include <getopt.h>
+#include <linux/i2c-dev.h>
+#include <linux/spi/spidev.h>
+#include <sys/ioctl.h>
+#include <sys/stat.h>
+#include <termios.h>
+#include <unistd.h>
+
+#define KBYTES_TO_BYTES 1024
+
+/*
+ * Some Ubuntu versions do not export SPI_IOC_WR_MODE32 even though
+ * the kernel shipped on those supports it.
+ */
+#ifndef SPI_IOC_WR_MODE32
+#define SPI_IOC_WR_MODE32 _IOW(SPI_IOC_MAGIC, 5, __u32)
+#endif
+
+/* Monitor command set */
+#define CMD_INIT 0x7f /* Starts the monitor */
+
+#define CMD_GETCMD 0x00 /* Gets the allowed commands */
+#define CMD_GETVER 0x01 /* Gets the bootloader version */
+#define CMD_GETID 0x02 /* Gets the Chip ID */
+#define CMD_READMEM 0x11 /* Reads memory */
+#define CMD_GO 0x21 /* Jumps to user code */
+#define CMD_WRITEMEM 0x31 /* Writes memory (SRAM or Flash) */
+#define CMD_ERASE 0x43 /* Erases n pages of Flash memory */
+#define CMD_EXTERASE 0x44 /* Erases n pages of Flash memory */
+#define CMD_NO_STRETCH_ERASE 0x45 /* Erases while sending busy frame */
+#define CMD_WP 0x63 /* Enables write protect */
+#define CMD_WU 0x73 /* Disables write protect */
+#define CMD_RP 0x82 /* Enables the read protection */
+#define CMD_RU 0x92 /* Disables the read protection */
+
+#define CMD_LOOKUP_ENTRY(COMMAND)       \
+	{                               \
+		CMD_##COMMAND, #COMMAND \
+	}
+const struct {
+	const uint8_t cmd;
+	const char *name;
+} cmd_lookup_table[] = {
+	CMD_LOOKUP_ENTRY(INIT),	    CMD_LOOKUP_ENTRY(GETCMD),
+	CMD_LOOKUP_ENTRY(GETVER),   CMD_LOOKUP_ENTRY(GETID),
+	CMD_LOOKUP_ENTRY(READMEM),  CMD_LOOKUP_ENTRY(GO),
+	CMD_LOOKUP_ENTRY(WRITEMEM), CMD_LOOKUP_ENTRY(ERASE),
+	CMD_LOOKUP_ENTRY(EXTERASE), CMD_LOOKUP_ENTRY(NO_STRETCH_ERASE),
+	CMD_LOOKUP_ENTRY(WP),	    CMD_LOOKUP_ENTRY(WU),
+	CMD_LOOKUP_ENTRY(RP),	    CMD_LOOKUP_ENTRY(RU),
+};
+
+const char *cmd_lookup_name(uint8_t cmd)
+{
+	int i;
+	for (i = 0; i < ARRAY_SIZE(cmd_lookup_table); i++) {
+		if (cmd_lookup_table[i].cmd == cmd)
+			return cmd_lookup_table[i].name;
+	}
+
+	return NULL;
+}
+
+#define RESP_NACK 0x1f
+#define RESP_ACK 0x79 /* 0b 0111 1001 */
+#define RESP_BUSY 0x76
+#define RESP_DAMAGED_ACK 0xBC /* 0b 1011 1100, 1 bit shifted REST_ACK */
+
+/* SPI Start of Frame */
+#define SOF 0x5A
+
+/* Extended erase special parameters */
+#define ERASE_ALL 0xffff
+#define ERASE_BANK1 0xfffe
+#define ERASE_BANK2 0xfffd
+
+/* Upper bound of rebooting the monitor */
+#define MAX_DELAY_REBOOT 100000 /* us */
+
+/* Standard addresses common across various ST chips */
+#define STM32_MAIN_MEMORY_ADDR 0x08000000
+#define STM32_SYSTEM_MEMORY_ADDR 0x1FFF0000
+
+#define STM32_UNIQUE_ID_SIZE_BYTES 12
+
+/*
+ * Device electronic signature contains factory-programmed identification
+ * and calibration data to automatically match the characteristics of the
+ * microcontroller.
+ */
+struct stm32_device_signature {
+	/*
+	 * Address of the Unique Device ID register. This register contains a
+	 * 96-bit value that is unique across all chips.
+	 * Zero means ignore/unknown.
+	 */
+	uint32_t unique_device_id_addr;
+	/*
+	 * Address of the Flash Size register. This 16-bit register contains the
+	 * flash size in KB.
+	 * Zero means ignore/unknown.
+	 */
+	uint32_t flash_size_addr;
+	/*
+	 * Address of the Package Data register. This 16-bit register contains a
+	 * value that differentiates between package types of a given chip.
+	 * Zero means ignore/unknown.
+	 */
+	uint32_t package_data_addr;
+};
+
+struct memory_info {
+	/* Zero means ignore/unknown/not-applicable */
+	uint32_t addr;
+	/* If addr is non-zero
+	 * - zero here means value is dynamic and will be read from bootloader.
+	 * If addr is zero,
+	 * - zero here means ignore/unknown/not-applicable.
+	 */
+	uint32_t size_bytes;
+};
+
+struct memory_layout {
+	struct memory_info main_memory;
+	struct memory_info system_memory;
+	struct memory_info otp_area;
+	struct memory_info option_bytes;
+};
+
+/* known STM32 SoC parameters */
+struct stm32_def {
+	uint16_t id;
+	const char *name;
+	uint32_t flash_size;
+	uint32_t page_size;
+	uint32_t cmds_len[2];
+	const struct memory_layout memory_layout;
+	const struct stm32_device_signature device_signature;
+} chip_defs[] = {
+	{0x416, "STM32L15xxB",   0x20000,   256, {13, 13}, { { 0 } }, { 0 } },
+	{0x429, "STM32L15xxB-A", 0x20000,   256, {13, 13}, { { 0 } }, { 0 } },
+	{0x427, "STM32L15xxC",   0x40000,   256, {13, 13}, { { 0 } }, { 0 } },
+	{0x435, "STM32L44xx",    0x40000,  2048, {13, 13}, { { 0 } }, { 0 } },
+	{0x420, "STM32F100xx",   0x20000,  1024, {13, 13}, { { 0 } }, { 0 } },
+	{0x410, "STM32F102R8",   0x10000,  1024, {13, 13}, { { 0 } }, { 0 } },
+	{0x440, "STM32F05x",     0x10000,  1024, {13, 13}, { { 0 } }, { 0 } },
+	{0x444, "STM32F03x",     0x08000,  1024, {13, 13}, { { 0 } }, { 0 } },
+	{0x448, "STM32F07xB",    0x20000,  2048, {13, 13}, { { 0 } }, { 0 } },
+	{0x432, "STM32F37xx",    0x40000,  2048, {13, 13}, { { 0 } }, { 0 } },
+	{0x442, "STM32F09x",     0x40000,  2048, {13, 13}, { { 0 } }, { 0 } },
+	{0x431, "STM32F411",     0x80000, 16384, {13, 19}, { { 0 } }, { 0 } },
+	{
+		.id =		0x441,
+		.name =		"STM32F412",
+		.flash_size =	0x100000,
+		.page_size =	16384,
+		.cmds_len =	{13, 19},
+		/*
+		 * STM32F412:
+		 * See https://www.st.com/resource/en/reference_manual/dm00180369.pdf
+		 * Section 3.3 Table 5 Flash module organization
+		 */
+		.memory_layout = {
+			.main_memory = {
+				.addr = STM32_MAIN_MEMORY_ADDR,
+				.size_bytes = 0, /* set by flash reg read */
+			},
+			.system_memory = {
+				.addr = STM32_SYSTEM_MEMORY_ADDR,
+				.size_bytes = 30 * KBYTES_TO_BYTES,
+			},
+			.otp_area = {
+				.addr = 0x1FFF7800,
+				.size_bytes = 528,
+			},
+			.option_bytes = {
+				.addr = 0x1FFFC000,
+				.size_bytes = 16,
+			}
+		},
+		/*
+		 * STM32F412:
+		 * See https://www.st.com/resource/en/reference_manual/dm00180369.pdf
+		 * Section 31 Device electronic signature
+		 */
+		.device_signature = {
+			.unique_device_id_addr =	0x1FFF7A10,
+			.flash_size_addr =		0x1FFF7A22,
+			/*
+			 * Out of range for bootloader on this chip, so we don't
+			 * attempt to read.
+			 */
+			.package_data_addr =		0, /* 0x1FFF7BF0 */
+		}
+	},
+	{0x450, "STM32H74x",    0x200000, 131768, {13, 19}, { { 0 } }, { 0 } },
+	{0x451, "STM32F76x",    0x200000, 32768, {13, 19}, { { 0 } }, { 0 } },
+	{
+		.id =		0x460,
+		.name =		"STM32G071xx",
+		.flash_size =	0x20000,
+		.page_size =	2048,
+		.cmds_len =	{13, 13},
+		/*
+		 * STM32G0x1:
+		 * See https://www.st.com/resource/en/reference_manual/dm00371828.pdf
+		 * Section 3.3.1 Table 6 Flash module organization
+		 */
+		.memory_layout = {
+			.main_memory = {
+				.addr = STM32_MAIN_MEMORY_ADDR,
+				.size_bytes = 0, /* set by flash reg read */
+			},
+			.system_memory = {
+				.addr = STM32_SYSTEM_MEMORY_ADDR,
+				.size_bytes = 28 * KBYTES_TO_BYTES,
+			},
+			.otp_area = {
+				.addr = 0x1FFF7000,
+				.size_bytes = 1024,
+			},
+			.option_bytes = {
+				.addr = 0x1FFF7800,
+				.size_bytes = 128,
+			}
+		},
+		/*
+		 * STM32G0x1:
+		 * See https://www.st.com/resource/en/reference_manual/dm00371828.pdf
+		 * Section 38 Device electronic signature
+		 */
+		.device_signature = {
+			.unique_device_id_addr =	0x1FFF7590,
+			.flash_size_addr =		0x1FFF75E0,
+			/*
+			 * Datasheet litst as same address as e.g. STM32F412,
+			 * hence declaring as zero as for that other chip.
+			 */
+			.package_data_addr =		0, /* 0x1FFF7500 */
+		}
+	},
+	{ 0 }
+};
+
+#define DEFAULT_CONNECT_RETRIES 5
+#define DEFAULT_TIMEOUT 4 /* seconds */
+#define EXT_ERASE_TIMEOUT 20 /* seconds */
+#define DEFAULT_BAUDRATE B38400
+#define PAGE_SIZE 256
+#define INVALID_I2C_ADAPTER -1
+#define MAX_ACK_RETRY_COUNT (EXT_ERASE_TIMEOUT / DEFAULT_TIMEOUT)
+#define MAX_RETRY_COUNT 3
+
+enum interface_mode {
+	MODE_SERIAL,
+	MODE_I2C,
+	MODE_SPI,
+} mode = MODE_SERIAL;
+
+/* I2c address the EC is listening depends on the device:
+ * stm32f07xxx: 0x76
+ * stm32f411xx: 0x72
+ */
+#define DEFAULT_I2C_PERIPHERAL_ADDRESS 0x76
+
+/* store custom parameters */
+speed_t baudrate = DEFAULT_BAUDRATE;
+int connect_retries = DEFAULT_CONNECT_RETRIES;
+int i2c_adapter = INVALID_I2C_ADAPTER;
+const char *spi_adapter;
+int i2c_peripheral_address = DEFAULT_I2C_PERIPHERAL_ADDRESS;
+uint8_t boot_loader_version;
+const char *serial_port = "/dev/ttyUSB1";
+const char *input_filename;
+const char *output_filename;
+uint32_t offset = 0x08000000, length = 0;
+int retry_on_damaged_ack;
+
+/* STM32MON function return values */
+enum {
+	STM32_SUCCESS = 0,
+	STM32_EIO = -1, /* IO error */
+	STM32_EINVAL = -2, /* Got a faulty response from device */
+	STM32_ETIMEDOUT = -3, /* Device didn't respond in a time window. */
+	STM32_ENOMEM = -4, /* Failed to allocate memory. */
+	STM32_ENACK = -5, /* Got NACK. */
+	STM32_EDACK = -6, /* Got a damanged ACK. */
+};
+BUILD_ASSERT(STM32_SUCCESS == 0);
+#define IS_STM32_ERROR(res) ((res) < STM32_SUCCESS)
+
+/* optional command flags */
+enum {
+	FLAG_UNPROTECT = 0x01,
+	FLAG_ERASE = 0x02,
+	FLAG_GO = 0x04,
+	FLAG_READ_UNPROTECT = 0x08,
+	FLAG_CR50_MODE = 0x10,
+};
+
+typedef struct {
+	int size;
+	uint8_t *data;
+} payload_t;
+
+/* List all possible flash erase functions */
+typedef int command_erase_t(int fd, uint16_t count, uint16_t start);
+command_erase_t command_erase;
+command_erase_t command_ext_erase;
+command_erase_t command_erase_i2c;
+
+command_erase_t *erase;
+
+static void discard_input(int);
+
+#define MIN(a, b) ((a) < (b) ? (a) : (b))
+
+/* On user request save all data exchange with the target in this log file. */
+static FILE *log_file;
+
+/* Statistic data structure for response kind. */
+struct {
+	const char *const event_name;
+	uint32_t event_count;
+} stat_resp[] = {
+	{ "RESP_ACK", 0 },	   { "RESP_NACK", 0 }, { "RESP_BUSY", 0 },
+	{ "RESP_DAMAGED_ACK", 0 }, { "JUNK", 0 },
+};
+
+enum {
+	RESP_ACK_IDX = 0,
+	RESP_NACK_IDX,
+	RESP_BUSY_IDX,
+	RESP_DAMAGED_ACK_IDX,
+	JUNK_IDX,
+	MAX_EVENT_IDX
+};
+
+BUILD_ASSERT(ARRAY_SIZE(stat_resp) == MAX_EVENT_IDX);
+
+/*
+ * Print data into the log file, in hex, 16 bytes per line, prefix the first
+ * line with the value supplied by the caller (usually 'r' or 'w' for
+ * read/write).
+ */
+static void dump_log(const char *prefix, const void *data, size_t count)
+{
+	size_t i;
+
+	fprintf(log_file, "%s: ", prefix);
+	for (i = 0; i < count; i++) {
+		if (i && !(i % 16))
+			fprintf(log_file, "\n   ");
+		fprintf(log_file, " %02x", ((uint8_t *)data)[i]);
+	}
+
+	if (count % 16)
+		fprintf(log_file, "\n");
+
+	/* Make sure all data is there even in case of aborts/crashes. */
+	fflush(log_file);
+}
+
+/*
+ * Wrappers for standard library read() and write() functions. Add transferred
+ * data to the log if log file is opened.
+ */
+static ssize_t read_wrapper(int fd, void *buf, size_t count)
+{
+	ssize_t rv = read(fd, buf, count);
+
+	if (log_file && (rv > 0))
+		dump_log("r", buf, rv);
+
+	return rv;
+}
+
+static ssize_t write_wrapper(int fd, const void *buf, size_t count)
+{
+	ssize_t rv;
+
+	rv = write(fd, buf, count);
+
+	if (log_file && (rv > 0))
+		dump_log("w", buf, rv);
+
+	return rv;
+}
+
+int open_serial(const char *port, int cr50_mode)
+{
+	int fd, res;
+	struct termios cfg, cfg_copy;
+
+	fd = open(port, O_RDWR | O_NOCTTY);
+	if (fd == -1) {
+		perror("Unable to open serial port");
+		return -1;
+	}
+
+	/* put the tty in "raw" mode at the defined baudrate */
+	res = tcgetattr(fd, &cfg);
+	if (res == -1) {
+		perror("Cannot read tty attributes");
+		close(fd);
+		return -1;
+	}
+	cfmakeraw(&cfg);
+
+	/* Don't bother setting speed and parity when programming over Cr50. */
+	if (!cr50_mode) {
+		cfsetspeed(&cfg, baudrate);
+		/* serial mode should be 8e1 */
+		cfg.c_cflag |= PARENB;
+	}
+
+	/* 200 ms timeout */
+	cfg.c_cc[VTIME] = 2;
+	cfg.c_cc[VMIN] = 0;
+	memcpy(&cfg_copy, &cfg, sizeof(cfg_copy));
+
+	/*
+	 * tcsetattr() returns success if any of the modifications succeed, so
+	 * its return value of zero is not an indication of success, one needs
+	 * to check the result explicitly.
+	 */
+	tcsetattr(fd, TCSANOW, &cfg);
+	if (tcgetattr(fd, &cfg)) {
+		perror("Failed to re-read tty attributes");
+		close(fd);
+		return -1;
+	}
+
+	if (memcmp(&cfg, &cfg_copy, sizeof(cfg))) {
+		/*
+		 * On some systems the setting which does not come through is
+		 * the parity. We can try continuing without it when using
+		 * certain interfaces, let's try.
+		 */
+		cfg_copy.c_cflag &= ~PARENB;
+		if (memcmp(&cfg, &cfg_copy, sizeof(cfg))) {
+			/*
+			 * Something other than parity failed to get set, this
+			 * is an error.
+			 */
+			perror("Cannot set tty attributes");
+			close(fd);
+			return -1;
+		} else {
+			fprintf(stderr, "Failed to enable parity\n");
+		}
+	}
+
+	discard_input(fd); /* in case were were invoked soon after reset */
+	return fd;
+}
+
+int open_i2c(const int port)
+{
+	int fd;
+	char filename[20];
+
+	snprintf(filename, 19, "/dev/i2c-%d", port);
+	fd = open(filename, O_RDWR);
+	if (fd < 0) {
+		perror("Unable to open i2c adapter");
+		return -1;
+	}
+	if (ioctl(fd, I2C_SLAVE, i2c_peripheral_address >> 1) < 0) {
+		perror("Unable to select proper address");
+		close(fd);
+		return -1;
+	}
+
+	return fd;
+}
+
+int open_spi(const char *port)
+{
+	int fd;
+	int res;
+	uint32_t mode = SPI_MODE_0;
+	uint8_t bits = 8;
+
+	fd = open(port, O_RDWR);
+	if (fd == -1) {
+		perror("Unable to open SPI controller");
+		return -1;
+	}
+
+	res = ioctl(fd, SPI_IOC_WR_MODE32, &mode);
+	if (res == -1) {
+		perror("Cannot set SPI mode");
+		close(fd);
+		return -1;
+	}
+
+	res = ioctl(fd, SPI_IOC_WR_BITS_PER_WORD, &bits);
+	if (res == -1) {
+		perror("Cannot set SPI bits per word");
+		close(fd);
+		return -1;
+	}
+
+	return fd;
+}
+
+static void discard_input(int fd)
+{
+	uint8_t buffer[64];
+	int res, i;
+	int count_of_zeros;
+
+	/* Skip in i2c and spi modes */
+	if (mode != MODE_SERIAL)
+		return;
+
+	/* eat trailing garbage */
+	count_of_zeros = 0;
+	do {
+		res = read_wrapper(fd, buffer, sizeof(buffer));
+		if (res > 0) {
+			/* Discard zeros in the beginning of the buffer. */
+			for (i = 0; i < res; i++)
+				if (buffer[i])
+					break;
+
+			count_of_zeros += i;
+			if (i == res) {
+				/* Only zeros, nothing to print out. */
+				continue;
+			}
+
+			/* Discard zeros in the end of the buffer. */
+			while (!buffer[res - 1]) {
+				count_of_zeros++;
+				res--;
+			}
+
+			printf("Recv[%d]:", res - i);
+			for (; i < res; i++)
+				printf("%02x ", buffer[i]);
+			printf("\n");
+		}
+	} while (res > 0);
+
+	if (count_of_zeros)
+		printf("%d zeros ignored\n", count_of_zeros);
+}
+
+int wait_for_ack(int fd)
+{
+	uint8_t resp;
+	int res;
+	time_t deadline = time(NULL) + DEFAULT_TIMEOUT;
+	const uint8_t ack = RESP_ACK;
+
+	while (time(NULL) < deadline) {
+		res = read_wrapper(fd, &resp, 1);
+		if ((res < 0) && (errno != EAGAIN)) {
+			perror("Failed to read answer");
+			return STM32_EIO;
+		}
+
+		if (res != 1)
+			continue;
+
+		switch (resp) {
+		case RESP_ACK:
+			stat_resp[RESP_ACK_IDX].event_count++;
+			if (mode == MODE_SPI) /* Ack the ACK */
+				if (write_wrapper(fd, &ack, 1) != 1)
+					return STM32_EIO;
+			return STM32_SUCCESS;
+
+		case RESP_NACK:
+			stat_resp[RESP_NACK_IDX].event_count++;
+			fprintf(stderr, "NACK\n");
+			if (mode == MODE_SPI) /* Ack the NACK */
+				if (write_wrapper(fd, &ack, 1) != 1)
+					return STM32_EIO;
+			discard_input(fd);
+			return STM32_ENACK;
+
+		case RESP_BUSY:
+			stat_resp[RESP_BUSY_IDX].event_count++;
+			/* I2C Boot protocol 1.1 */
+			deadline = time(NULL) + DEFAULT_TIMEOUT;
+			break;
+
+		case RESP_DAMAGED_ACK:
+			if (retry_on_damaged_ack) {
+				/* It is a damaged ACK. However, device is
+				 * likely to believe it sent ACK, so let's not
+				 * treat it as junk.
+				 */
+				stat_resp[RESP_DAMAGED_ACK_IDX].event_count++;
+				fprintf(stderr, "DAMAGED_ACK\n");
+				return STM32_EDACK;
+			}
+
+			/* Do not break so that it can be handled as junk */
+			__attribute__((fallthrough));
+		default:
+			stat_resp[JUNK_IDX].event_count++;
+			if (mode == MODE_SERIAL)
+				fprintf(stderr, "Receive junk: %02x\n", resp);
+			break;
+		}
+	}
+	fprintf(stderr, "Timeout\n");
+	return STM32_ETIMEDOUT;
+}
+
+int send_command(int fd, uint8_t cmd, payload_t *loads, int cnt, uint8_t *resp,
+		 int resp_size, int ack_requested)
+{
+	int res, i, c;
+	payload_t *p;
+	int readcnt = 0;
+
+	uint8_t cmd_frame[] = { SOF, cmd,
+				/* XOR checksum */
+				(uint8_t)(0xff ^ cmd) };
+	/* only the SPI mode needs the Start Of Frame byte */
+	int cmd_off = mode == MODE_SPI ? 0 : 1;
+	int count_damaged_ack = 0;
+
+	/* Send the command index */
+	res = write_wrapper(fd, cmd_frame + cmd_off,
+			    sizeof(cmd_frame) - cmd_off);
+	if (res <= 0) {
+		perror("Failed to write command frame");
+		return STM32_EIO;
+	}
+
+	/* Wait for the ACK */
+	res = wait_for_ack(fd);
+	if (res == STM32_EDACK) {
+		++count_damaged_ack;
+	} else if (IS_STM32_ERROR(res)) {
+		const char *name = cmd_lookup_name(cmd);
+		char hex[sizeof("0xFF")];
+		snprintf(hex, sizeof(hex), "0x%02x", cmd);
+		fprintf(stderr, "Failed to get command %s ACK\n",
+			name ? name : hex);
+		return res;
+	}
+
+	/* Send the command payloads */
+	for (p = loads, c = 0; c < cnt; c++, p++) {
+		uint8_t crc = 0;
+		int size = p->size;
+		uint8_t *data = (uint8_t *)(malloc(size + 1)), *data_ptr;
+
+		if (data == NULL) {
+			fprintf(stderr,
+				"Failed to allocate memory for load %d\n", c);
+			return STM32_ENOMEM;
+		}
+		memcpy(data, p->data, size);
+		for (i = 0; i < size; i++)
+			crc ^= data[i];
+		if (size == 1)
+			crc = 0xff ^ crc;
+		data[size] = crc;
+		size++;
+		data_ptr = data;
+		while (size) {
+			res = write_wrapper(fd, data_ptr, size);
+			if (res < 0) {
+				perror("Failed to write command payload");
+				free(data);
+				return STM32_EIO;
+			}
+			size -= res;
+			data_ptr += res;
+		}
+		free(data);
+
+		/* Wait for the ACK */
+		res = wait_for_ack(fd);
+		if (res == STM32_EDACK) {
+			++count_damaged_ack;
+		} else if (IS_STM32_ERROR(res)) {
+			if (res != STM32_ETIMEDOUT)
+				fprintf(stderr,
+					"payload %d ACK failed for CMD%02x\n",
+					c, cmd);
+			return res;
+		}
+	}
+
+	/* Read the answer payload */
+	if (resp) {
+		if (mode == MODE_SPI) /* ignore extra byte */
+			if (read_wrapper(fd, resp, 1) < 0)
+				return STM32_EIO;
+		while ((resp_size > 0) &&
+		       (res = read_wrapper(fd, resp, resp_size))) {
+			if (res < 0) {
+				perror("Failed to read payload");
+				return STM32_EIO;
+			}
+			readcnt += res;
+			resp += res;
+			resp_size -= res;
+		}
+
+		/* Wait for the ACK */
+		if (ack_requested) {
+			res = wait_for_ack(fd);
+			if (res == STM32_EDACK) {
+				++count_damaged_ack;
+			} else if (IS_STM32_ERROR(res)) {
+				fprintf(stderr,
+					"Failed to get response to command"
+					" 0x%02x ACK\n",
+					cmd);
+				return res;
+			}
+		}
+	}
+
+	if (count_damaged_ack)
+		return STM32_EDACK;
+
+	return readcnt;
+}
+
+int send_command_retry(int fd, uint8_t cmd, payload_t *loads, int cnt,
+		       uint8_t *resp, int resp_size, int ack_requested)
+{
+	int res;
+	int retries = MAX_RETRY_COUNT;
+
+	do {
+		int ack_tries = MAX_ACK_RETRY_COUNT;
+
+		res = send_command(fd, cmd, loads, cnt, resp, resp_size,
+				   ack_requested);
+
+		while (res == STM32_ETIMEDOUT && ack_tries--) {
+			if (cmd == CMD_WRITEMEM) {
+				/* send garbage byte */
+				res = write_wrapper(fd, loads->data, 1);
+				/* Don't care much since it is a  garbage
+				 * transfer to let the device not wait for
+				 * any missing data, if any.
+				 */
+				if (res < 0)
+					fprintf(stderr, "warn: write failed\n");
+			}
+			res = wait_for_ack(fd);
+		}
+	} while ((res == STM32_ENACK || res == STM32_EDACK) && retries--);
+
+	return res;
+}
+
+struct stm32_def *command_get_id(int fd)
+{
+	int res;
+	uint8_t id[3];
+	uint16_t chipid;
+	struct stm32_def *def;
+
+	res = send_command(fd, CMD_GETID, NULL, 0, id, sizeof(id), 1);
+	if (res > 0) {
+		if (id[0] != 1) {
+			fprintf(stderr, "unknown ID : %02x %02x %02x\n", id[0],
+				id[1], id[2]);
+			return NULL;
+		}
+		chipid = (id[1] << 8) | id[2];
+		for (def = chip_defs; def->id; def++)
+			if (def->id == chipid)
+				break;
+		if (def->id == 0)
+			def = NULL;
+		printf("ChipID 0x%03x : %s\n", chipid, def ? def->name : "???");
+		return def;
+	}
+
+	return NULL;
+}
+
+int init_monitor(int fd)
+{
+	int res = 0;
+	int attempts = connect_retries + 1;
+	uint8_t init = mode == MODE_SPI ? SOF : CMD_INIT;
+
+	/* Skip in i2c mode */
+	if (mode == MODE_I2C)
+		return STM32_SUCCESS;
+
+	printf("Waiting for the monitor startup ...");
+	fflush(stdout);
+
+	while (connect_retries < 0 || attempts--) {
+		/* Send the command index */
+		res = write_wrapper(fd, &init, 1);
+		if (res <= 0) {
+			perror("Failed to write command");
+			return STM32_EIO;
+		}
+		/* Wait for the ACK */
+		res = wait_for_ack(fd);
+		if (res == STM32_SUCCESS)
+			break;
+		if (res == STM32_ENACK) {
+			/* we got NACK'ed, the loader might be already started
+			 * let's ping it to check
+			 */
+			if (command_get_id(fd)) {
+				printf("Monitor already started.\n");
+				return STM32_SUCCESS;
+			}
+		}
+		if (IS_STM32_ERROR(res) && res != STM32_ETIMEDOUT)
+			return res;
+		fflush(stdout);
+	}
+
+	if (IS_STM32_ERROR(res)) {
+		printf("Giving up after %d attempts.\n", connect_retries + 1);
+		return res;
+	}
+
+	printf("Done.\n");
+
+	/* read trailing chars */
+	discard_input(fd);
+
+	return STM32_SUCCESS;
+}
+
+int command_get_commands(int fd, struct stm32_def *chip)
+{
+	int res, i;
+	uint8_t cmds[64];
+
+	/*
+	 * For i2c, we have to request the exact amount of bytes we expect.
+	 */
+	res = send_command(fd, CMD_GETCMD, NULL, 0, cmds,
+			   chip->cmds_len[(mode == MODE_I2C ? 1 : 0)], 1);
+	if (res > 0) {
+		if (cmds[0] > sizeof(cmds) - 2) {
+			fprintf(stderr, "invalid GET answer (%02x...)\n",
+				cmds[0]);
+			return STM32_EINVAL;
+		}
+		printf("Bootloader v%d.%d, commands : ", cmds[1] >> 4,
+		       cmds[1] & 0xf);
+		boot_loader_version = cmds[1];
+
+		erase = command_erase;
+		for (i = 2; i < 2 + cmds[0]; i++) {
+			const char *name;
+			if (cmds[i] == CMD_EXTERASE)
+				erase = command_ext_erase;
+			name = cmd_lookup_name(cmds[i]);
+			if (name)
+				printf("%s ", name);
+			else
+				printf("0x%02x ", cmds[i]);
+		}
+
+		if (mode == MODE_I2C)
+			erase = command_erase_i2c;
+		printf("\n");
+
+		return STM32_SUCCESS;
+	}
+
+	fprintf(stderr, "Cannot get bootloader command list.\n");
+	return STM32_EINVAL;
+}
+
+static int use_progressbar;
+static int windex;
+static const char wheel[] = { '|', '/', '-', '\\' };
+static void draw_spinner(uint32_t remaining, uint32_t size)
+{
+	int percent = (size - remaining) * 100 / size;
+	if (use_progressbar) {
+		int dots = percent / 4;
+
+		while (dots > windex) {
+			putchar('#');
+			windex++;
+		}
+	} else {
+		printf("\r%c%3d%%", wheel[windex++], percent);
+		windex %= sizeof(wheel);
+	}
+	fflush(stdout);
+}
+
+int command_read_mem(int fd, uint32_t address, uint32_t size, uint8_t *buffer)
+{
+	int res;
+	uint32_t remaining = size;
+	uint32_t addr_be;
+	uint8_t cnt;
+	payload_t loads[2] = { { 4, (uint8_t *)&addr_be }, { 1, &cnt } };
+
+	while (remaining) {
+		uint32_t bytes = MIN(remaining, PAGE_SIZE);
+
+		cnt = (uint8_t)(bytes - 1);
+		addr_be = htonl(address);
+
+		draw_spinner(remaining, size);
+
+		res = send_command_retry(fd, CMD_READMEM, loads, 2, buffer,
+					 bytes, 0);
+		if (IS_STM32_ERROR(res))
+			return STM32_EIO;
+
+		buffer += bytes;
+		address += bytes;
+		remaining -= bytes;
+	}
+
+	return size;
+}
+
+int command_write_mem(int fd, uint32_t address, uint32_t size, uint8_t *buffer)
+{
+	int res = 0;
+	int i;
+	uint32_t remaining = size;
+	uint32_t addr_be;
+	uint32_t cnt;
+	uint8_t outbuf[257];
+	payload_t loads[2] = { { 4, (uint8_t *)&addr_be },
+			       { sizeof(outbuf), outbuf } };
+
+	while (remaining) {
+		cnt = MIN(remaining, PAGE_SIZE);
+		/* skip empty blocks to save time */
+		for (i = 0; i < cnt && buffer[i] == 0xff; i++)
+			;
+		if (i != cnt) {
+			addr_be = htonl(address);
+			outbuf[0] = cnt - 1;
+			loads[1].size = cnt + 1;
+			memcpy(outbuf + 1, buffer, cnt);
+
+			draw_spinner(remaining, size);
+
+			res = send_command_retry(fd, CMD_WRITEMEM, loads, 2,
+						 NULL, 0, 1);
+			if (IS_STM32_ERROR(res))
+				return STM32_EIO;
+		}
+		buffer += cnt;
+		address += cnt;
+		remaining -= cnt;
+	}
+
+	return size;
+}
+
+int command_ext_erase(int fd, uint16_t count, uint16_t start)
+{
+	int res;
+	uint16_t count_be = htons(count);
+	payload_t load = { 2, (uint8_t *)&count_be };
+	uint16_t *pages = NULL;
+
+	if (count < 0xfff0) {
+		int i;
+		/* not a special value : build a list of pages */
+		load.size = 2 * (count + 1);
+		pages = (uint16_t *)(malloc(load.size));
+		if (!pages)
+			return STM32_ENOMEM;
+		load.data = (uint8_t *)pages;
+		pages[0] = htons(count - 1);
+		for (i = 0; i < count; i++)
+			pages[i + 1] = htons(start + i);
+	}
+
+	printf("Erasing...\n");
+	res = send_command_retry(fd, CMD_EXTERASE, &load, 1, NULL, 0, 1);
+	if (!IS_STM32_ERROR(res))
+		printf("Flash erased.\n");
+
+	if (pages)
+		free(pages);
+	return res;
+}
+
+int command_erase_i2c(int fd, uint16_t count, uint16_t start)
+{
+	int res;
+	uint8_t erase_cmd;
+	uint16_t count_be = htons(count);
+	payload_t load[2] = {
+		{ 2, (uint8_t *)&count_be },
+		{ 0, NULL },
+	};
+	int load_cnt = 1;
+	uint16_t *pages = NULL;
+
+	if (count < 0xfff) {
+		int i;
+		/* not a special value : build a list of pages */
+		/*
+		 * I2c protocol requires 2 messages, the count has to be acked
+		 * before the addresses can be sent.
+		 * TODO(gwendal): Still broken on i2c.
+		 */
+		load_cnt = 2;
+		load[1].size = 2 * count;
+		pages = (uint16_t *)(malloc(load[1].size));
+		if (!pages)
+			return STM32_ENOMEM;
+		load[1].data = (uint8_t *)pages;
+		count_be = htons(count - 1);
+		for (i = 0; i < count; i++)
+			pages[i] = htons(start + i);
+	}
+
+	erase_cmd = (boot_loader_version == 0x10) ? CMD_EXTERASE :
+						    CMD_NO_STRETCH_ERASE;
+
+	printf("Erasing...\n");
+	res = send_command(fd, erase_cmd, load, load_cnt, NULL, 0, 1);
+	if (!IS_STM32_ERROR(res))
+		printf("Flash erased.\n");
+
+	if (pages)
+		free(pages);
+	return res;
+}
+
+int command_erase(int fd, uint16_t count, uint16_t start)
+{
+	int res;
+	uint8_t count_8bit = count;
+	payload_t load = { 1, &count_8bit };
+	uint8_t *pages = NULL;
+
+	if (count < 0xff) {
+		int i;
+		/* not a special value : build a list of pages */
+		load.size = count + 1;
+		pages = (uint8_t *)(malloc(load.size));
+		if (!pages)
+			return STM32_ENOMEM;
+		load.data = (uint8_t *)pages;
+		pages[0] = count - 1;
+		for (i = 0; i < count; i++)
+			pages[i + 1] = start + i;
+	}
+
+	printf("Erasing...\n");
+	res = send_command(fd, CMD_ERASE, &load, 1, NULL, 0, 1);
+	if (!IS_STM32_ERROR(res))
+		printf("Flash erased.\n");
+
+	if (pages)
+		free(pages);
+	return res;
+}
+
+int command_read_unprotect(int fd)
+{
+	int res;
+	int retries = MAX_ACK_RETRY_COUNT;
+
+	printf("Unprotecting flash read...\n");
+
+	res = send_command(fd, CMD_RU, NULL, 0, NULL, 0, 1);
+	/*
+	 * Read unprotect can trigger a mass erase, which can take long time
+	 * (e.g. 13s+ on STM32H7)
+	 */
+	do {
+		res = wait_for_ack(fd);
+	} while ((res == STM32_ETIMEDOUT) && --retries);
+
+	if (IS_STM32_ERROR(res)) {
+		fprintf(stderr, "Failed to get read-protect ACK\n");
+		return res;
+	}
+	printf("Flash read unprotected.\n");
+
+	/*
+	 * This command triggers a reset.
+	 *
+	 * Wait at least the reboot delay, else we could reconnect
+	 * before the actual reset depending on the bootloader.
+	 */
+	usleep(MAX_DELAY_REBOOT);
+	if (IS_STM32_ERROR(init_monitor(fd))) {
+		fprintf(stderr, "Cannot recover after RU reset\n");
+		return STM32_EIO;
+	}
+
+	return STM32_SUCCESS;
+}
+
+int command_write_unprotect(int fd)
+{
+	int res;
+
+	res = send_command(fd, CMD_WU, NULL, 0, NULL, 0, 1);
+	if (IS_STM32_ERROR(res))
+		return STM32_EIO;
+
+	/* Wait for the ACK */
+	if (wait_for_ack(fd) < 0) {
+		fprintf(stderr, "Failed to get write-protect ACK\n");
+		return STM32_EINVAL;
+	}
+	printf("Flash write unprotected.\n");
+
+	/*
+	 * This command triggers a reset.
+	 *
+	 * Wait at least the reboot delay, else we could reconnect
+	 * before the actual reset depending on the bootloader.
+	 */
+	usleep(MAX_DELAY_REBOOT);
+	if (IS_STM32_ERROR(init_monitor(fd))) {
+		fprintf(stderr, "Cannot recover after WP reset\n");
+		return STM32_EIO;
+	}
+
+	return STM32_SUCCESS;
+}
+
+int command_go(int fd, uint32_t address)
+{
+	int res;
+	uint32_t addr_be = htonl(address);
+	payload_t load = { 4, (uint8_t *)&addr_be };
+
+	res = send_command(fd, CMD_GO, &load, 1, NULL, 0, 1);
+	if (IS_STM32_ERROR(res))
+		return STM32_EIO;
+
+#if 0 /* this ACK should exist according to the documentation ... */
+	/* Wait for the ACK */
+	if (wait_for_ack(fd) < 0) {
+		fprintf(stderr, "Failed to get GO ACK\n");
+		return -EINVAL;
+	}
+#endif
+
+	printf("Program started at 0x%08x.\n", address);
+	return STM32_SUCCESS;
+}
+
+/*
+ * The bootloader does not allow reading directly from the "device signature"
+ * registers. However, it does allow reading the OTP region, so this function
+ * starts a read from the last byte in that region and reads an additional
+ * number of bytes to read the requested register.
+ *
+ * Example:
+ *
+ * Given a chip with OTP region starting at address 0x1FFF7800 with a size of
+ * 528 bytes and a register that we want to read at address 0x1FFF7A10 with a
+ * size of 12 bytes:
+ *
+ * We start the read at the last byte in the OTP region:
+ *
+ * 0x1FFF7800 + 528 - 1 = 0x1FFF7A0F
+ *
+ * From 0x1FFF7A0F we perform a read of (12 + 1) = 13 bytes in order to read the
+ * 12 bytes starting at 0x1FFF7A10 (the actual register we care about).
+ *
+ * Returns zero on success, negative on failure.
+ */
+int read_device_signature_register(int fd, const struct stm32_def *chip,
+				   uint32_t addr, uint32_t size_bytes,
+				   uint8_t *out_buffer)
+{
+	int res;
+	uint8_t *buffer;
+	struct memory_info otp = chip->memory_layout.otp_area;
+	uint32_t otp_end_addr = otp.addr + otp.size_bytes - 1;
+	uint32_t offset = addr - otp_end_addr;
+	uint32_t read_size_bytes = offset + size_bytes;
+
+	if (!otp.addr) {
+		fprintf(stderr, "No otp_area.addr specified for given chip.\n");
+		return STM32_EINVAL;
+	}
+
+	if (addr <= otp_end_addr) {
+		fprintf(stderr,
+			"Attempting to read from invalid address: "
+			"%08X\n",
+			addr);
+		return STM32_EINVAL;
+	}
+
+	/*
+	 * The USART/SPI/I2C bootloader can only read at most 256 bytes in a
+	 * single read command (see AN4286 section 2.5 or AN3155 section 3.4).
+	 *
+	 * command_read_mem will correctly chunk larger requests, but the
+	 * subsequent reads will fail because the bootloader won't allow reads
+	 * from a starting address that is beyond the OTP region.
+	 */
+	if (read_size_bytes > PAGE_SIZE) {
+		fprintf(stderr,
+			"Requested register 0x%08X is outside read range.\n",
+			addr);
+		return STM32_EINVAL;
+	}
+
+	buffer = (uint8_t *)(malloc(read_size_bytes));
+	if (!buffer) {
+		fprintf(stderr, "Cannot allocate %" PRIu32 " bytes\n",
+			read_size_bytes);
+		return STM32_ENOMEM;
+	}
+
+	res = command_read_mem(fd, otp_end_addr, read_size_bytes, buffer);
+	if (res == read_size_bytes)
+		memcpy(out_buffer, buffer + offset, size_bytes);
+	else
+		fprintf(stderr,
+			"Cannot read %" PRIu32 " bytes from address 0x%08X",
+			read_size_bytes, otp_end_addr);
+
+	free(buffer);
+	return IS_STM32_ERROR(res) ? res : STM32_SUCCESS;
+}
+
+/* Return zero on success, a negative error value on failures. */
+int read_flash_size_register(int fd, struct stm32_def *chip,
+			     uint16_t *flash_size_kbytes)
+{
+	int res;
+	uint32_t flash_size_addr = chip->device_signature.flash_size_addr;
+
+	if (!flash_size_addr)
+		return STM32_EINVAL;
+
+	res = read_device_signature_register(fd, chip, flash_size_addr,
+					     sizeof(*flash_size_kbytes),
+					     (uint8_t *)flash_size_kbytes);
+
+	if (!IS_STM32_ERROR(res))
+		printf("Flash size: %" PRIu16 " KB\n", *flash_size_kbytes);
+	else
+		fprintf(stderr,
+			"Unable to read flash size register (0x%08X).\n",
+			flash_size_addr);
+
+	return res;
+}
+
+/* Return zero on success, a negative error value on failures. */
+int read_unique_device_id_register(int fd, struct stm32_def *chip,
+				   uint8_t device_id[STM32_UNIQUE_ID_SIZE_BYTES])
+{
+	int i;
+	int res;
+	uint32_t unique_device_id_addr =
+		chip->device_signature.unique_device_id_addr;
+
+	if (!unique_device_id_addr)
+		return STM32_EINVAL;
+
+	res = read_device_signature_register(fd, chip, unique_device_id_addr,
+					     STM32_UNIQUE_ID_SIZE_BYTES,
+					     device_id);
+
+	if (!IS_STM32_ERROR(res)) {
+		printf("Unique Device ID: 0x");
+		for (i = STM32_UNIQUE_ID_SIZE_BYTES - 1; i >= 0; i--)
+			printf("%02X", device_id[i]);
+		printf("\n");
+	} else {
+		fprintf(stderr,
+			"Unable to read unique device ID register (0x%08X). "
+			"Ignoring non-critical failure.\n",
+			unique_device_id_addr);
+	}
+
+	return res;
+}
+
+/* Return zero on success, a negative error value on failures. */
+int read_package_data_register(int fd, struct stm32_def *chip,
+			       uint16_t *package_data)
+{
+	int res;
+	uint32_t package_data_addr = chip->device_signature.package_data_addr;
+
+	if (!package_data_addr)
+		return STM32_EINVAL;
+
+	res = read_device_signature_register(fd, chip, package_data_addr,
+					     sizeof(*package_data),
+					     (uint8_t *)package_data);
+
+	if (!IS_STM32_ERROR(res))
+		printf("Package data register: %04X\n", *package_data);
+	else
+		fprintf(stderr,
+			"Failed to read package data register (0x%08X). "
+			"Ignoring non-critical failure.\n",
+			package_data_addr);
+
+	return res;
+}
+
+/* Return zero on success, a negative error value on failures. */
+int read_flash(int fd, struct stm32_def *chip, const char *filename,
+	       uint32_t offset, uint32_t size)
+{
+	int res;
+	FILE *hnd;
+	uint8_t *buffer;
+
+	if (!size)
+		size = chip->flash_size;
+	buffer = (uint8_t *)(malloc(size));
+	if (!buffer) {
+		fprintf(stderr, "Cannot allocate %d bytes\n", size);
+		return STM32_ENOMEM;
+	}
+
+	hnd = fopen(filename, "w");
+	if (!hnd) {
+		fprintf(stderr, "Cannot open file %s for writing\n", filename);
+		free(buffer);
+		return STM32_EIO;
+	}
+
+	printf("Reading %d bytes at 0x%08x\n", size, offset);
+	res = command_read_mem(fd, offset, size, buffer);
+	if (res > 0) {
+		if (fwrite(buffer, res, 1, hnd) != 1)
+			fprintf(stderr, "Cannot write %s\n", filename);
+	}
+	printf("\r   %d bytes read.\n", res);
+
+	fclose(hnd);
+	free(buffer);
+	return IS_STM32_ERROR(res) ? res : STM32_SUCCESS;
+}
+
+/* Return zero on success, a negative error value on failures. */
+int write_flash(int fd, struct stm32_def *chip, const char *filename,
+		uint32_t offset)
+{
+	int res, written;
+	FILE *hnd;
+	int size = chip->flash_size;
+	uint8_t *buffer = (uint8_t *)(malloc(size));
+
+	if (!buffer) {
+		fprintf(stderr, "Cannot allocate %d bytes\n", size);
+		return STM32_ENOMEM;
+	}
+
+	if (!strncmp(filename, "-", sizeof("-")))
+		hnd = fdopen(STDIN_FILENO, "r");
+	else
+		hnd = fopen(filename, "r");
+	if (!hnd) {
+		fprintf(stderr, "Cannot open file %s for reading\n", filename);
+		free(buffer);
+		return STM32_EIO;
+	}
+	res = fread(buffer, 1, size, hnd);
+	fclose(hnd);
+	if (res <= 0) {
+		fprintf(stderr, "Cannot read %s\n", filename);
+		free(buffer);
+		return STM32_EIO;
+	}
+
+	/* faster write: skip empty trailing space */
+	while (res && buffer[res - 1] == 0xff)
+		res--;
+	/* ensure 'res' is multiple of 4 given 'size' is and res <= size */
+	res = (res + 3) & ~3;
+
+	printf("Writing %d bytes at 0x%08x\n", res, offset);
+	written = command_write_mem(fd, offset, res, buffer);
+	if (written != res) {
+		fprintf(stderr, "Error writing to flash\n");
+		free(buffer);
+		return STM32_EIO;
+	}
+	printf("\r   %d bytes written.\n", written);
+
+	free(buffer);
+	return STM32_SUCCESS;
+}
+
+static const struct option longopts[] = {
+	{ "adapter", 1, 0, 'a' },  { "baudrate", 1, 0, 'b' },
+	{ "cr50", 0, 0, 'c' },	   { "device", 1, 0, 'd' },
+	{ "erase", 0, 0, 'e' },	   { "go", 0, 0, 'g' },
+	{ "help", 0, 0, 'h' },	   { "length", 1, 0, 'n' },
+	{ "location", 1, 0, 'l' }, { "logfile", 1, 0, 'L' },
+	{ "offset", 1, 0, 'o' },   { "progressbar", 0, 0, 'p' },
+	{ "read", 1, 0, 'r' },	   { "retries", 1, 0, 'R' },
+	{ "spi", 1, 0, 's' },	   { "unprotect", 0, 0, 'u' },
+	{ "version", 0, 0, 'v' },  { "write", 1, 0, 'w' },
+	{ NULL, 0, 0, 0 }
+};
+
+void display_usage(char *program)
+{
+	fprintf(stderr,
+		"Usage: %s [-a <i2c_adapter> [-l address ]] | [-s]"
+		" [-d <tty>] [-b <baudrate>]] [-u] [-e] [-U]"
+		" [-r <file>] [-w <file>] [-o offset] [-n length] [-g] [-p]"
+		" [-L <log_file>] [-c] [-v]\n",
+		program);
+	fprintf(stderr, "Can access the controller via serial port or i2c\n");
+	fprintf(stderr, "Serial port mode:\n");
+	fprintf(stderr, "--d[evice] <tty> : use <tty> as the serial port\n");
+	fprintf(stderr, "--b[audrate] <baudrate> : set serial port speed "
+			"to <baudrate> bauds\n");
+	fprintf(stderr, "i2c mode:\n");
+	fprintf(stderr, "--a[dapter] <id> : use i2c adapter <id>.\n");
+	fprintf(stderr, "--l[ocation]  <address> : use address <address>.\n");
+	fprintf(stderr, "--s[pi]: use spi mode.\n");
+	fprintf(stderr, "--u[nprotect] : remove flash write protect\n");
+	fprintf(stderr, "--U[nprotect] : remove flash read protect\n");
+	fprintf(stderr, "--e[rase] : erase all the flash content\n");
+	fprintf(stderr, "--r[ead] <file> : read the flash content and "
+			"write it into <file>\n");
+	fprintf(stderr, "--s[pi] </dev/spi> : use SPI adapter on </dev>.\n");
+	fprintf(stderr, "--w[rite] <file|-> : read <file> or\n\t"
+			"standard input and write it to flash\n");
+	fprintf(stderr, "--o[ffset] : offset to read/write/start from/to\n");
+	fprintf(stderr, "--n[length] : amount to read/write\n");
+	fprintf(stderr, "--g[o] : jump to execute flash entrypoint\n");
+	fprintf(stderr, "--p[rogressbar] : use a progress bar instead of "
+			"the spinner\n");
+	fprintf(stderr, "--R[etries] <num> : limit connect retries to num\n");
+	fprintf(stderr, "-L[ogfile] <file> : save all communications exchange "
+			"in a log file\n");
+	fprintf(stderr, "-c[r50_mode] : consider device to be a Cr50 interface,"
+			" no need to set UART port attributes\n");
+	fprintf(stderr, "--v[ersion] : print version and exit\n");
+
+	exit(2);
+}
+
+void display_version(const char *exe_name)
+{
+	printf("%s version: %s %s %s\n", exe_name, CROS_STM32MON_VERSION, DATE,
+	       BUILDER);
+}
+
+speed_t parse_baudrate(const char *value)
+{
+	int rate = atoi(value);
+
+	switch (rate) {
+	case 9600:
+		return B9600;
+	case 19200:
+		return B19200;
+	case 38400:
+		return B38400;
+	case 57600:
+		return B57600;
+	case 115200:
+		return B115200;
+	default:
+		fprintf(stderr, "Invalid baudrate %s, using %d\n", value,
+			DEFAULT_BAUDRATE);
+		return DEFAULT_BAUDRATE;
+	}
+}
+
+int parse_parameters(int argc, char **argv)
+{
+	int opt, idx;
+	int flags = 0;
+	const char *log_file_name = NULL;
+
+	while ((opt = getopt_long(argc, argv, "a:l:b:cd:eghL:n:o:pr:R:s:w:uUv?",
+				  longopts, &idx)) != -1) {
+		switch (opt) {
+		case 'a':
+			i2c_adapter = atoi(optarg);
+			mode = MODE_I2C;
+			break;
+		case 'l':
+			i2c_peripheral_address = strtol(optarg, NULL, 0);
+			break;
+		case 'b':
+			baudrate = parse_baudrate(optarg);
+			break;
+		case 'c':
+			flags |= FLAG_CR50_MODE;
+			break;
+		case 'd':
+			serial_port = optarg;
+			mode = MODE_SERIAL;
+			break;
+		case 'e':
+			flags |= FLAG_ERASE;
+			break;
+		case 'g':
+			flags |= FLAG_GO;
+			break;
+		case 'h':
+		case '?':
+			display_usage(argv[0]);
+			break;
+		case 'L':
+			log_file_name = optarg;
+			break;
+		case 'n':
+			length = strtol(optarg, NULL, 0);
+			break;
+		case 'o':
+			offset = strtol(optarg, NULL, 0);
+			break;
+		case 'p':
+			use_progressbar = 1;
+			break;
+		case 'r':
+			input_filename = optarg;
+			break;
+		case 'R':
+			connect_retries = atoi(optarg);
+			break;
+		case 's':
+			spi_adapter = optarg;
+			mode = MODE_SPI;
+			break;
+		case 'w':
+			output_filename = optarg;
+			break;
+		case 'u':
+			flags |= FLAG_UNPROTECT;
+			break;
+		case 'U':
+			flags |= FLAG_READ_UNPROTECT;
+			break;
+		case 'v':
+			display_version(argv[0]);
+			exit(0);
+		}
+	}
+
+	if (log_file_name) {
+		log_file = fopen(log_file_name, "w");
+		if (!log_file) {
+			fprintf(stderr, "failed to open %s for writing\n",
+				log_file_name);
+			exit(2);
+		}
+	}
+	return flags;
+}
+
+static void display_stat_response(void)
+{
+	uint32_t total_events = MAX_EVENT_IDX;
+	uint32_t idx;
+
+	printf("--\n");
+	for (idx = 0; idx < total_events; ++idx) {
+		printf("%-18s %d\n", stat_resp[idx].event_name,
+		       stat_resp[idx].event_count);
+	}
+	printf("--\n");
+}
+
+int main(int argc, char **argv)
+{
+	int ser;
+	struct stm32_def *chip;
+	int ret = STM32_EIO;
+	int res;
+	int flags;
+	uint16_t flash_size_kbytes = 0;
+	uint8_t unique_device_id[STM32_UNIQUE_ID_SIZE_BYTES] = { 0 };
+	uint16_t package_data_reg = 0;
+
+	/* Parse command line options */
+	flags = parse_parameters(argc, argv);
+
+	display_version(argv[0]);
+
+	retry_on_damaged_ack = !!(flags & FLAG_CR50_MODE);
+
+	switch (mode) {
+	case MODE_SPI:
+		ser = open_spi(spi_adapter);
+		break;
+	case MODE_I2C:
+		ser = open_i2c(i2c_adapter);
+		break;
+	case MODE_SERIAL:
+	default:
+		/* Open the serial port tty */
+		ser = open_serial(serial_port, !!(flags & FLAG_CR50_MODE));
+	}
+	if (ser < 0)
+		return 1;
+	/* Trigger embedded monitor detection */
+	res = init_monitor(ser);
+	if (IS_STM32_ERROR(res))
+		goto terminate;
+
+	chip = command_get_id(ser);
+	if (!chip)
+		goto terminate;
+
+	if (command_get_commands(ser, chip) < 0)
+		goto terminate;
+
+	if (flags & FLAG_READ_UNPROTECT)
+		command_read_unprotect(ser);
+
+	/*
+	 * Use the actual size if we were able to read it since some chips
+	 * have the same chip ID, but different flash sizes based on the
+	 * package.
+	 */
+	res = read_flash_size_register(ser, chip, &flash_size_kbytes);
+	if (!IS_STM32_ERROR(res))
+		chip->flash_size = flash_size_kbytes * KBYTES_TO_BYTES;
+
+	/*
+	 * This is simply informative at the moment, so we don't care about the
+	 * return value.
+	 */
+	(void)read_unique_device_id_register(ser, chip, unique_device_id);
+
+	/*
+	 * This is simply informative at the moment, so we don't care about the
+	 * return value.
+	 */
+	(void)read_package_data_register(ser, chip, &package_data_reg);
+
+	if (flags & FLAG_UNPROTECT)
+		command_write_unprotect(ser);
+
+	if (flags & FLAG_ERASE || output_filename) {
+		if ((!strncmp("STM32L15", chip->name, 8)) ||
+		    (!strncmp("STM32F411", chip->name, 9))) {
+			/* Mass erase is not supported on these chips*/
+			int i, page_count = chip->flash_size / chip->page_size;
+			for (i = 0; i < page_count; i += 128) {
+				int count = MIN(128, page_count - i);
+				ret = erase(ser, count, i);
+				if (IS_STM32_ERROR(ret))
+					goto terminate;
+			}
+		} else {
+			ret = erase(ser, 0xFFFF, 0);
+			if (IS_STM32_ERROR(ret))
+				goto terminate;
+		}
+	}
+
+	if (input_filename) {
+		ret = read_flash(ser, chip, input_filename, offset, length);
+		if (IS_STM32_ERROR(ret))
+			goto terminate;
+	}
+
+	if (output_filename) {
+		ret = write_flash(ser, chip, output_filename, offset);
+		if (IS_STM32_ERROR(ret))
+			goto terminate;
+	}
+
+	/* Run the program from flash */
+	if (flags & FLAG_GO)
+		command_go(ser, offset);
+
+	/* Normal exit */
+	ret = STM32_SUCCESS;
+terminate:
+	if (log_file)
+		fclose(log_file);
+
+	/* Close serial port */
+	close(ser);
+
+	if (retry_on_damaged_ack)
+		display_stat_response();
+
+	if (IS_STM32_ERROR(ret)) {
+		fprintf(stderr, "Failed: %d\n", ret);
+		return 1;
+	}
+
+	printf("Done.\n");
+	return 0;
+}
diff --git a/util/tagbranch.sh b/util/tagbranch.sh
index 3e196b6f25..850886e08c 100755
--- a/util/tagbranch.sh
+++ b/util/tagbranch.sh
@@ -1,6 +1,6 @@
 #!/bin/bash
 #
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -29,7 +29,7 @@
 # - the remote git server name shows up in 'git config -l' output in the
 #   line starting with "remote.cros.url="
 # - firmware branch names have format of firmware-<board>-XXXXXX
-# - the current branch was cut off of <remote name>/master
+# - the current branch was cut off of <remote name>/main
 #
 # The tag name generated by this script would be the XXXXX string with dots,
 # if any, replaced by underscores.
@@ -44,10 +44,10 @@ fi
 export ORIGIN_NAME="cros"
 ORIGIN="$(git config "remote.${ORIGIN_NAME}.url")"
 
-# The last common patch between this branch and the master.
-BRANCH_POINT="$(git merge-base "${UPSTREAM}" "${ORIGIN_NAME}/master")"
+# The last common patch between this branch and main.
+BRANCH_POINT="$(git merge-base "${UPSTREAM}" "${ORIGIN_NAME}/main")"
 if [[ -z "${BRANCH_POINT}" ]]; then
-  echo "Failed to determine cros/master branch point" >&2
+  echo "Failed to determine cros/main branch point" >&2
   exit 1
 fi
 
@@ -56,8 +56,8 @@ TAG_BASE="$(sed 's/.*-//       # drop everything up to including the last -
                  s/\./_/g      # replace dots and dashes with underscores
       ' <<< "${UPSTREAM}" )"
 
-if [[ "${TAG_BASE}" == "master" ]]; then
-  echo "Nothing to tag in master branch" >&2
+if [[ "${TAG_BASE}" == "main" ]]; then
+  echo "Nothing to tag in main branch" >&2
   exit 1
 fi
 
diff --git a/util/temp_metrics.conf b/util/temp_metrics.conf
index ccd3254beb..174571f72a 100644
--- a/util/temp_metrics.conf
+++ b/util/temp_metrics.conf
@@ -1,4 +1,4 @@
-# Copyright 2012 The Chromium OS Authors. All rights reserved.
+# Copyright 2012 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/util/test-inject-keys.sh b/util/test-inject-keys.sh
index 031452150e..44ba3324d3 100755
--- a/util/test-inject-keys.sh
+++ b/util/test-inject-keys.sh
@@ -1,6 +1,6 @@
 #!/bin/bash
 #
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/util/test_kconfig_check.py b/util/test_kconfig_check.py
new file mode 100644
index 0000000000..12721cc7ef
--- /dev/null
+++ b/util/test_kconfig_check.py
@@ -0,0 +1,314 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Test for Kconfig checker"""
+
+import contextlib
+import io
+import os
+import pathlib
+import re
+import sys
+import tempfile
+import unittest
+
+import kconfig_check
+
+
+# Prefix that we strip from each Kconfig option, when considering whether it is
+# equivalent to a CONFIG option with the same name
+PREFIX = "PLATFORM_EC_"
+
+
+@contextlib.contextmanager
+def capture_sys_output():
+    """Capture output for testing purposes
+
+    Use this to suppress stdout/stderr output:
+        with capture_sys_output() as (stdout, stderr)
+            ...do something...
+    """
+    capture_out, capture_err = io.StringIO(), io.StringIO()
+    old_out, old_err = sys.stdout, sys.stderr
+    try:
+        sys.stdout, sys.stderr = capture_out, capture_err
+        yield capture_out, capture_err
+    finally:
+        sys.stdout, sys.stderr = old_out, old_err
+
+
+# Use unittest since it produced less verbose output than pytest and can be run
+# directly from Python. You can still run this test with 'pytest' if you like.
+class KconfigCheck(unittest.TestCase):
+    """Tests for the KconfigCheck class"""
+
+    def test_simple_check(self):
+        """Check it detected a new ad-hoc CONFIG"""
+        checker = kconfig_check.KconfigCheck()
+        self.assertEqual(
+            ["NEW_ONE"],
+            checker.find_new_adhoc(
+                configs=["NEW_ONE", "OLD_ONE", "IN_KCONFIG"],
+                kconfigs=["IN_KCONFIG"],
+                allowed=["OLD_ONE"],
+            ),
+        )
+
+    def test_sorted_check(self):
+        """Check it sorts the results in order"""
+        checker = kconfig_check.KconfigCheck()
+        self.assertSequenceEqual(
+            ["ANOTHER_NEW_ONE", "NEW_ONE"],
+            checker.find_new_adhoc(
+                configs=["NEW_ONE", "ANOTHER_NEW_ONE", "OLD_ONE", "IN_KCONFIG"],
+                kconfigs=["IN_KCONFIG"],
+                allowed=["OLD_ONE"],
+            ),
+        )
+
+    def check_read_configs(self, use_defines):
+        """Check that kconfigs can be read."""
+        checker = kconfig_check.KconfigCheck()
+        with tempfile.NamedTemporaryFile() as configs:
+            with open(configs.name, "w") as out:
+                prefix = "#define " if use_defines else ""
+                suffix = " " if use_defines else "="
+                out.write(
+                    f"""{prefix}CONFIG_OLD_ONE{suffix}y
+{prefix}NOT_A_CONFIG{suffix}
+{prefix}CONFIG_STRING{suffix}"something"
+{prefix}CONFIG_INT{suffix}123
+{prefix}CONFIG_HEX{suffix}45ab
+"""
+                )
+            self.assertEqual(
+                ["OLD_ONE", "STRING", "INT", "HEX"],
+                checker.read_configs(configs.name, use_defines),
+            )
+
+    def test_read_configs(self):
+        """Test KconfigCheck.read_configs()"""
+        self.check_read_configs(False)
+
+    def test_read_configs_defines(self):
+        """Test KconfigCheck.read_configs() containing #defines"""
+        self.check_read_configs(True)
+
+    @classmethod
+    def setup_srctree(cls, srctree):
+        """Set up some Kconfig files in a directory and subdirs
+
+        Args:
+            srctree: Directory to write to
+        """
+        with open(os.path.join(srctree, "Kconfig"), "w") as out:
+            out.write(
+                f"""config {PREFIX}MY_KCONFIG
+\tbool "my kconfig"
+
+rsource "subdir/Kconfig.wibble"
+"""
+            )
+        subdir = os.path.join(srctree, "subdir")
+        os.mkdir(subdir)
+        with open(os.path.join(subdir, "Kconfig.wibble"), "w") as out:
+            out.write("menuconfig %sMENU_KCONFIG\n" % PREFIX)
+
+        # Add a directory which should be ignored
+        bad_subdir = os.path.join(subdir, "Kconfig")
+        os.mkdir(bad_subdir)
+        with open(os.path.join(bad_subdir, "Kconfig.bad"), "w") as out:
+            out.write("menuconfig %sBAD_KCONFIG" % PREFIX)
+
+    @classmethod
+    def setup_zephyr_base(cls, zephyr_base):
+        """Set up some Kconfig files in a directory and subdirs
+
+        Args:
+            zephyr_base: Directory to write to
+        """
+        with open(os.path.join(zephyr_base, "Kconfig.zephyr"), "w") as out:
+            out.write(
+                """config ZCONFIG
+\tbool "zephyr kconfig"
+
+rsource "subdir/Kconfig.wobble"
+"""
+            )
+        subdir = os.path.join(zephyr_base, "subdir")
+        os.mkdir(subdir)
+        with open(os.path.join(subdir, "Kconfig.wobble"), "w") as out:
+            out.write("menuconfig WOBBLE_MENU_KCONFIG\n")
+
+        # Add a directory which should be ignored
+        bad_subdir = os.path.join(subdir, "Kconfig")
+        os.mkdir(bad_subdir)
+        with open(os.path.join(bad_subdir, "Kconfig.bad"), "w") as out:
+            out.write("menuconfig BAD_KCONFIG")
+
+    def test_find_kconfigs(self):
+        """Test KconfigCheck.find_kconfigs()"""
+        checker = kconfig_check.KconfigCheck()
+        with tempfile.TemporaryDirectory() as srctree:
+            self.setup_srctree(srctree)
+            files = checker.find_kconfigs(srctree)
+            fnames = [fname[len(srctree) :] for fname in files]
+            self.assertEqual(["/Kconfig", "/subdir/Kconfig.wibble"], fnames)
+
+    def test_scan_kconfigs(self):
+        """Test KconfigCheck.scan_configs()"""
+        checker = kconfig_check.KconfigCheck()
+        with tempfile.TemporaryDirectory() as srctree:
+            with tempfile.TemporaryDirectory() as zephyr_path:
+                self.setup_zephyr_base(zephyr_path)
+                os.environ["ZEPHYR_BASE"] = str(zephyr_path)
+                self.setup_srctree(srctree)
+                self.assertEqual(
+                    [
+                        "MENU_KCONFIG",
+                        "MY_KCONFIG",
+                        "WOBBLE_MENU_KCONFIG",
+                        "ZCONFIG",
+                    ],
+                    checker.scan_kconfigs(srctree, PREFIX),
+                )
+
+    @classmethod
+    def setup_allowed_and_configs(
+        cls, allowed_fname, configs_fname, add_new_one=True
+    ):
+        """Set up the 'allowed' and 'configs' files for tests
+
+        Args:
+            allowed_fname: Filename to write allowed CONFIGs to
+            configs_fname: Filename to which CONFIGs to check should be written
+            add_new_one: True to add CONFIG_NEW_ONE to the configs_fname file
+        """
+        with open(allowed_fname, "w") as out:
+            out.write("CONFIG_OLD_ONE\n")
+            out.write("CONFIG_MENU_KCONFIG\n")
+        with open(configs_fname, "w") as out:
+            to_add = ["CONFIG_OLD_ONE", "CONFIG_MY_KCONFIG"]
+            if add_new_one:
+                to_add.append("CONFIG_NEW_ONE")
+            out.write("\n".join(to_add))
+
+    def test_check_adhoc_configs(self):
+        """Test KconfigCheck.check_adhoc_configs()"""
+        checker = kconfig_check.KconfigCheck()
+        with tempfile.TemporaryDirectory() as srctree:
+            self.setup_srctree(srctree)
+            with tempfile.NamedTemporaryFile() as allowed:
+                with tempfile.NamedTemporaryFile() as configs:
+                    with tempfile.TemporaryDirectory() as zephyr_path:
+                        self.setup_zephyr_base(zephyr_path)
+                        os.environ["ZEPHYR_BASE"] = str(zephyr_path)
+                        self.setup_allowed_and_configs(
+                            allowed.name, configs.name
+                        )
+                        (
+                            new_adhoc,
+                            unneeded_adhoc,
+                            updated_adhoc,
+                        ) = checker.check_adhoc_configs(
+                            configs.name, srctree, allowed.name, PREFIX
+                        )
+                        self.assertEqual(["NEW_ONE"], new_adhoc)
+                        self.assertEqual(["MENU_KCONFIG"], unneeded_adhoc)
+                        self.assertEqual(["OLD_ONE"], updated_adhoc)
+
+    def test_check(self):
+        """Test running the 'check' subcommand"""
+        with capture_sys_output() as (
+            stdout,
+            stderr,
+        ), tempfile.TemporaryDirectory() as srctree:
+            with tempfile.NamedTemporaryFile() as allowed:
+                with tempfile.NamedTemporaryFile() as configs:
+                    with tempfile.TemporaryDirectory() as zephyr_path:
+                        self.setup_srctree(srctree)
+                        self.setup_zephyr_base(zephyr_path)
+                        os.environ["ZEPHYR_BASE"] = str(zephyr_path)
+                        self.setup_allowed_and_configs(
+                            allowed.name, configs.name
+                        )
+                        ret_code = kconfig_check.main(
+                            [
+                                "-c",
+                                configs.name,
+                                "-s",
+                                srctree,
+                                "-a",
+                                allowed.name,
+                                "-p",
+                                PREFIX,
+                                "check",
+                            ]
+                        )
+                        self.assertEqual(1, ret_code)
+        self.assertEqual("", stdout.getvalue())
+        found = re.findall("(CONFIG_.*)", stderr.getvalue())
+        self.assertEqual(["CONFIG_NEW_ONE"], found)
+
+    def test_real_kconfig(self):
+        """Same Kconfig should be returned for kconfiglib / adhoc"""
+        if not kconfig_check.USE_KCONFIGLIB:
+            self.fail("No kconfiglib available")
+        zephyr_path = pathlib.Path(
+            "../../../src/third_party/zephyr/main"
+        ).resolve()
+        if not zephyr_path.exists():
+            self.fail("No zephyr tree available")
+        os.environ["ZEPHYR_BASE"] = str(zephyr_path)
+
+        checker = kconfig_check.KconfigCheck()
+        srcdir = "zephyr"
+        search_paths = [zephyr_path]
+        kc_version = checker.scan_kconfigs(
+            srcdir, search_paths=search_paths, try_kconfiglib=True
+        )
+        adhoc_version = checker.scan_kconfigs(srcdir, try_kconfiglib=False)
+
+        # List of things missing from the Kconfig
+        missing = sorted(list(set(adhoc_version) - set(kc_version)))
+
+        # There should be no differences between adhoc and kconfig versions
+        self.assertListEqual([], missing)
+
+    def test_check_unneeded(self):
+        """Test running the 'check' subcommand with unneeded ad-hoc configs"""
+        with capture_sys_output() as (stdout, stderr):
+            with tempfile.TemporaryDirectory() as srctree:
+                self.setup_srctree(srctree)
+                with tempfile.NamedTemporaryFile() as allowed:
+                    with tempfile.NamedTemporaryFile() as configs:
+                        with tempfile.TemporaryDirectory() as zephyr_path:
+                            self.setup_zephyr_base(zephyr_path)
+                            os.environ["ZEPHYR_BASE"] = str(zephyr_path)
+                            self.setup_allowed_and_configs(
+                                allowed.name, configs.name, False
+                            )
+                            ret_code = kconfig_check.main(
+                                [
+                                    "-c",
+                                    configs.name,
+                                    "-s",
+                                    srctree,
+                                    "-a",
+                                    allowed.name,
+                                    "-p",
+                                    PREFIX,
+                                    "check",
+                                ]
+                            )
+                            self.assertEqual(1, ret_code)
+        self.assertEqual("", stderr.getvalue())
+        found = re.findall("(CONFIG_.*)", stdout.getvalue())
+        self.assertEqual(["CONFIG_MENU_KCONFIG"], found)
+        allowed = kconfig_check.NEW_ALLOWED_FNAME.read_text().splitlines()
+        self.assertEqual(["CONFIG_OLD_ONE"], allowed)
+
+
+if __name__ == "__main__":
+    unittest.main()
diff --git a/util/twister_launcher.py b/util/twister_launcher.py
new file mode 100755
index 0000000000..2af4ef0332
--- /dev/null
+++ b/util/twister_launcher.py
@@ -0,0 +1,572 @@
+#!/usr/bin/env vpython3
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""
+This script is a wrapper for invoking Twister, the Zephyr test runner, using
+default parameters for the ChromiumOS EC project. For an overview of CLI
+parameters that may be used, please consult the Twister documentation.
+"""
+
+# [VPYTHON:BEGIN]
+# python_version: "3.8"
+# wheel: <
+#   name: "infra/python/wheels/anytree-py2_py3"
+#   version: "version:2.8.0"
+# >
+# wheel: <
+#   name: "infra/python/wheels/colorama-py3"
+#   version: "version:0.4.1"
+# >
+# wheel: <
+#   name: "infra/python/wheels/docopt-py2_py3"
+#   version: "version:0.6.2"
+# >
+# wheel: <
+#   name: "infra/python/wheels/natsort-py3"
+#   version: "version:8.3.1"
+# >
+# wheel: <
+#   name: "infra/python/wheels/packaging-py2_py3"
+#   version: "version:16.8"
+# >
+# wheel: <
+#   name: "infra/python/wheels/ply-py2_py3"
+#   version: "version:3.11"
+# >
+# wheel: <
+#   name: "infra/python/wheels/psutil/${vpython_platform}"
+#   version: "version:5.8.0.chromium.3"
+# >
+# wheel: <
+#   name: "infra/python/wheels/pyelftools-py2_py3"
+#   version: "version:0.29"
+# >
+# wheel: <
+#   name: "infra/python/wheels/pykwalify-py2_py3"
+#   version: "version:1.8.0"
+# >
+# wheel: <
+#   name: "infra/python/wheels/pyparsing-py3"
+#   version: "version:3.0.7"
+# >
+# wheel: <
+#   name: "infra/python/wheels/pyserial-py2_py3"
+#   version: "version:3.4"
+# >
+# wheel: <
+#   name: "infra/python/wheels/python-dateutil-py2_py3"
+#   version: "version:2.8.1"
+# >
+# wheel: <
+#   name: "infra/python/wheels/pyyaml-py3"
+#   version: "version:5.3.1"
+# >
+# wheel: <
+#   name: "infra/python/wheels/ruamel_yaml_clib/${vpython_platform}"
+#   version: "version:0.2.6"
+# >
+# wheel: <
+#   name: "infra/python/wheels/ruamel_yaml-py3"
+#   version: "version:0.17.16"
+# >
+# wheel: <
+#   name: "infra/python/wheels/six-py2_py3"
+#   version: "version:1.16.0"
+# >
+# wheel: <
+#   name: "infra/python/wheels/west-py3"
+#   version: "version:0.14.0"
+# >
+# [VPYTHON:END]
+
+import argparse
+import hashlib
+import json
+import os
+import pathlib
+from pathlib import Path
+import re
+import shlex
+import shutil
+from shutil import which
+import socket
+import subprocess
+import sys
+import tempfile
+import time
+from typing import List
+
+
+# Paths under the EC base dir that contain tests. This is used to define
+# Twister's search scope.
+EC_TEST_PATHS = [
+    Path("common"),
+    Path("zephyr/test"),
+]
+
+# Paths under ZEPHYR_BASE that we also wish to search for test cases.
+ZEPHYR_TEST_PATHS = [
+    Path("tests/subsys/shell"),
+]
+
+
+def find_checkout() -> Path:
+    """Find the location of the source checkout or return None."""
+    cros_checkout = os.environ.get("CROS_WORKON_SRCROOT")
+    if cros_checkout is not None:
+        return Path(cros_checkout)
+
+    # Attempt to locate checkout location relatively if being run outside of
+    # chroot.
+    try:
+        cros_checkout = Path(__file__).resolve().parents[4]
+        assert (cros_checkout / "src").exists()
+        return cros_checkout
+    except (IndexError, AssertionError):
+        # Not in the chroot or matching directory structure
+        return None
+
+
+def find_paths():
+    """Find EC base, Zephyr base, and Zephyr modules paths and return as a 3-tuple."""
+
+    # Determine where the source tree is checked out. Will be None if operating outside
+    # of the chroot (e.g. Gitlab builds). In this case, additional paths need to be
+    # passed in through environment variables.
+    cros_checkout = find_checkout()
+
+    if cros_checkout:
+        ec_base = cros_checkout / "src" / "platform" / "ec"
+        try:
+            zephyr_base = Path(os.environ["ZEPHYR_BASE"]).resolve()
+        except KeyError:
+            zephyr_base = (
+                cros_checkout / "src" / "third_party" / "zephyr" / "main"
+            )
+        zephyr_modules_dir = cros_checkout / "src" / "third_party" / "zephyr"
+    else:
+        try:
+            ec_base = Path(os.environ["EC_DIR"]).resolve()
+        except KeyError as err:
+            raise RuntimeError(
+                "EC_DIR unspecified. Please pass as env var or use chroot."
+            ) from err
+
+        try:
+            zephyr_base = Path(os.environ["ZEPHYR_BASE"]).resolve()
+        except KeyError as err:
+            raise RuntimeError(
+                "ZEPHYR_BASE unspecified. Please pass as env var or use chroot."
+            ) from err
+
+        try:
+            zephyr_modules_dir = Path(os.environ["MODULES_DIR"]).resolve()
+        except KeyError as err:
+            raise RuntimeError(
+                "MODULES_DIR unspecified. Please pass as env var or use chroot."
+            ) from err
+
+    return (ec_base, zephyr_base, zephyr_modules_dir)
+
+
+def find_modules(mod_dir: Path) -> list:
+    """Find Zephyr modules in the given directory `dir`."""
+
+    modules = []
+    for child in mod_dir.iterdir():
+        if child.is_dir() and (child / "zephyr" / "module.yml").exists():
+            modules.append(child.resolve())
+    return modules
+
+
+def is_tool(name):
+    """Check if 'name' is on PATH and marked executable."""
+    return which(name) is not None
+
+
+def is_rdb_login():
+    """Checks if user is logged into rdb"""
+    cmd = ["rdb", "auth-info"]
+    ret = subprocess.run(cmd, capture_output=True, text=True, check=False)
+
+    if ret.returncode == 0:
+        print("\nrdb auth-info: " + ret.stdout.split("\n")[0])
+    else:
+        print("\nrdb auth-info: " + ret.stderr)
+
+    return ret.returncode == 0
+
+
+def upload_results(ec_base, outdir):
+    """Uploads Zephyr Test results to ResultDB"""
+    flag = False
+
+    if is_rdb_login():
+        json_path = pathlib.Path(outdir) / "twister.json"
+
+        if json_path.exists():
+            hostname = socket.gethostname().split(".")[0]
+            cmd = [
+                "rdb",
+                "stream",
+                "-new",
+                "-realm",
+                "chromium:public",
+                "-tag",
+                "builder_name:" + hostname,
+                "--",
+                "vpython3",
+                str(ec_base / "util/zephyr_to_resultdb.py"),
+                "--result=" + str(json_path),
+                "--upload=True",
+            ]
+
+            start_time = time.time()
+            ret = subprocess.run(
+                cmd, capture_output=True, text=True, check=True
+            )
+            end_time = time.time()
+
+            # Extract URL to test report from captured output
+            rdb_url = re.search(
+                r"(?P<url>https?://[^\s]+)", ret.stderr.split("\n")[0]
+            ).group("url")
+            print(f"\nTEST RESULTS ({end_time - start_time:.3f}s): {rdb_url}\n")
+            flag = ret.returncode == 0
+    else:
+        print("Unable to upload test results, please run 'rdb auth-login'\n")
+
+    return flag
+
+
+def check_for_skipped_tests(outdir):
+    """Checks Twister json test report for skipped tests"""
+    found_skipped = False
+    json_path = pathlib.Path(outdir) / "twister.json"
+    if json_path.exists():
+        with open(json_path, encoding="utf-8") as file:
+            data = json.load(file)
+
+            for testsuite in data["testsuites"]:
+                for testcase in testsuite["testcases"]:
+                    if testcase["status"] == "skipped":
+                        tc_name = testcase["identifier"]
+                        print(f"TEST SKIPPED: {tc_name}")
+                        found_skipped = True
+
+            file.close()
+
+    return found_skipped
+
+
+def append_cmake_compiler(cmdline, cmake_var, exe_options):
+    """Picks the first available exe from exe_options and adds a cmake variable
+    to cmdline."""
+    for exe in exe_options:
+        exe_path = shutil.which(exe)
+        if exe_path:
+            cmdline.append(f"-x={cmake_var}={exe_path}")
+            return
+
+
+def in_cros_sdk() -> bool:
+    """Detect if the development environment is CrOS SDK.
+
+    Returns:
+        True if the environment looks like Firmware SDK, False otherwise.
+    """
+    return Path("/etc/cros_chroot_version").is_file()
+
+
+def running_in_bazel() -> bool:
+    """Detect if we're running as inside of a Bazel build already.
+
+    Returns:
+        True if it looks like we're running from a Bazel rule, False otherwise.
+    """
+    return "BAZEL_TWISTER_CWD" in os.environ
+
+
+def in_fwsdk() -> bool:
+    """Detect if the development environment is Firmware SDK.
+
+    Returns:
+        True if the environment looks like Firmware SDK, False otherwise.
+    """
+    # CrOS SDK cannot be FWSDK.  Check early and stop to prevent us from
+    # breaking anything in CrOS SDK.
+    if in_cros_sdk():
+        return False
+
+    # If we're already re-launched under Bazel, we're in Firmware SDK.
+    if running_in_bazel():
+        return True
+
+    # Otherwise, ask Bazel to see if it knows about Firmware SDK rules.
+    try:
+        subprocess.run(
+            [
+                "bazel",
+                "query",
+                "//platform/rules_cros_firmware/cros_firmware:*",
+            ],
+            stdout=subprocess.DEVNULL,
+            stderr=subprocess.DEVNULL,
+            check=True,
+        )
+    except subprocess.CalledProcessError:
+        return False
+    return True
+
+
+def maybe_relaunch_in_bazel(
+    argv: List[str], cwd: Path, sandbox_debug: bool = False
+):
+    """If Firmware SDK environment is detected, relaunch in Bazel.
+
+    Args:
+        argv: The command line to re-launch with.
+        cwd: The directory to run inside.
+        sandbox_debug: If True, run bazel with --sandbox_debug.
+    """
+    if not in_fwsdk():
+        return False
+
+    if running_in_bazel():
+        return False
+
+    gen_starlark = f"""
+load(
+    "//platform/rules_cros_firmware/cros_firmware/twister:twister.bzl",
+    "twister_test_binary",
+)
+twister_test_binary(
+    name = "run_twister",
+    args = {argv!r},
+    cwd = {str(cwd)!r},
+)"""
+    run_hash = hashlib.md5(gen_starlark.encode("utf-8")).hexdigest()
+    twister_bzl_dir = Path(__file__).parent.parent / "build" / "twister-bzl"
+    run_dir = twister_bzl_dir / run_hash
+
+    if not run_dir.is_dir():
+        run_dir.mkdir(parents=True)
+        (run_dir / "BUILD.bazel").write_text(gen_starlark, encoding="utf-8")
+
+    bazel_cmd = ["bazel", "build", ":run_twister"]
+    if sandbox_debug:
+        bazel_cmd.append("--sandbox_debug")
+
+    result = subprocess.run(bazel_cmd, cwd=run_dir, check=False)
+    sys.exit(result.returncode)
+
+
+def main():
+    """Run Twister using defaults for the EC project."""
+
+    bazel_outdir = None
+    if "BAZEL_TWISTER_CWD" in os.environ:
+        # Resolve any paths relative to the execroot prior to changing
+        # directories.
+        bazel_outdir = Path(os.environ["BAZEL_TWISTER_OUTDIR"]).resolve()
+        os.environ["TOOLCHAIN_ROOT"] = str(
+            Path(os.environ["TOOLCHAIN_ROOT"]).resolve()
+        )
+        os.chdir(os.environ["BAZEL_TWISTER_CWD"])
+
+    # Get paths for the build.
+    ec_base, zephyr_base, zephyr_modules_dir = find_paths()
+
+    zephyr_modules = find_modules(zephyr_modules_dir)
+
+    # Add the EC dir as a module if not already included (resolve all paths to
+    # account for symlinked or relative paths)
+    if ec_base.resolve() not in zephyr_modules:
+        zephyr_modules.append(ec_base)
+
+    # Twister CLI args
+    twister_cli = [
+        sys.executable,
+        str(zephyr_base / "scripts" / "twister"),  # Executable path
+        "--ninja",
+        f"-x=DTS_ROOT={str( ec_base / 'zephyr')}",
+        f"-x=SYSCALL_INCLUDE_DIRS={str(ec_base / 'zephyr' / 'include' / 'drivers')}",
+        f"-x=ZEPHYR_BASE={zephyr_base}",
+        f"-x=ZEPHYR_MODULES={';'.join([str(p) for p in zephyr_modules])}",
+        f"-x=PYTHON_EXECUTABLE={sys.executable}",
+    ]
+
+    # `-T` flags (used for specifying test directories to build and run)
+    # require special handling. When run without `-T` flags, Twister will
+    # search for tests in `zephyr_base`. This is undesirable and we want
+    # Twister to look in the EC tree by default, instead. Use argparse to
+    # intercept `-T` flags and pass in a new default if none are found. If
+    # user does pass their own `-T` flags, pass them through instead. Do the
+    # same with verbosity. Other arguments get passed straight through,
+    # including -h/--help so that Twister's own help text gets displayed.
+    parser = argparse.ArgumentParser(add_help=False, allow_abbrev=False)
+    parser.add_argument("-T", "--testsuite-root", action="append")
+    parser.add_argument("-p", "--platform", action="append")
+    parser.add_argument("-v", "--verbose", action="count", default=0)
+    parser.add_argument("--gcov-tool")
+    parser.add_argument(
+        "--no-upload-cros-rdb", dest="upload_cros_rdb", action="store_false"
+    )
+    parser.add_argument(
+        "-O",
+        "--outdir",
+        default=bazel_outdir or os.path.join(os.getcwd(), "twister-out"),
+    )
+    parser.add_argument(
+        "--toolchain",
+        default=os.environ.get(
+            "ZEPHYR_TOOLCHAIN_VARIANT",
+            "llvm" if in_cros_sdk() else "host",
+        ),
+    )
+    parser.add_argument(
+        "--gcc", dest="toolchain", action="store_const", const="host"
+    )
+    parser.add_argument(
+        "--llvm",
+        "--clang",
+        dest="toolchain",
+        action="store_const",
+        const="llvm",
+    )
+    parser.add_argument(
+        "--sandbox-debug",
+        action="store_true",
+        default=False,
+        help="When running under Bazel, enable sandbox debugging mode.",
+    )
+    parser.add_argument(
+        "-h",
+        "--help",
+        action="store_true",
+    )
+
+    intercepted_args, other_args = parser.parse_known_args()
+
+    # We allow help to run outside the sandbox.
+    if intercepted_args.help:
+        twister_cli.append("--help")
+    else:
+        maybe_relaunch_in_bazel(
+            sys.argv[1:],
+            Path.cwd(),
+            sandbox_debug=intercepted_args.sandbox_debug,
+        )
+
+    for _ in range(intercepted_args.verbose):
+        # Pass verbosity setting through to twister
+        twister_cli.append("-v")
+
+    if intercepted_args.testsuite_root:
+        # Pass user-provided -T args when present.
+        for arg in intercepted_args.testsuite_root:
+            twister_cli.extend(["-T", arg])
+    else:
+        # Use this set of test suite roots when no -T args are present. This
+        # should encompass all current Zephyr EC tests. The paths are meant to
+        # be as specific as possible to limit Twister's search scope. This saves
+        # significant time when starting Twister.
+        for path in EC_TEST_PATHS:
+            twister_cli.extend(["-T", str(ec_base / path)])
+
+        # Upstream tests we also wish to run:
+        for path in ZEPHYR_TEST_PATHS:
+            twister_cli.extend(["-T", str(zephyr_base / path)])
+
+    if intercepted_args.platform:
+        # Pass user-provided -p args when present.
+        for arg in intercepted_args.platform:
+            twister_cli.extend(["-p", arg])
+    else:
+        # posix_native and unit_testing when nothing was requested by user.
+        twister_cli.extend(["-p", "native_posix"])
+        twister_cli.extend(["-p", "unit_testing"])
+
+    twister_cli.extend(["--outdir", intercepted_args.outdir])
+
+    toolchain_root = (
+        str(ec_base / "zephyr") if in_cros_sdk() else str(zephyr_base)
+    )
+    twister_cli.extend([f"-x=TOOLCHAIN_ROOT={toolchain_root}"])
+
+    # Prepare environment variables for export to Twister. Inherit the parent
+    # process's environment, but set some default values if not already set.
+    twister_env = dict(os.environ)
+    with tempfile.TemporaryDirectory() as parsetab_dir:
+        extra_env_vars = {
+            "TOOLCHAIN_ROOT": os.environ.get(
+                "TOOLCHAIN_ROOT",
+                str(ec_base / "zephyr") if in_cros_sdk() else str(zephyr_base),
+            ),
+            # TODO(https://github.com/zephyrproject-rtos/zephyr/issues/59453):
+            # This ought to be passed as a CMake variable but can't due to how
+            # Zephyr calls verify-toolchain.cmake
+            "ZEPHYR_TOOLCHAIN_VARIANT": intercepted_args.toolchain,
+            "PARSETAB_DIR": parsetab_dir,
+        }
+        gcov_tool = None
+        if intercepted_args.toolchain == "host":
+            gcov_tool = "gcov"
+            # Inside the chroot, the binutils is still at v2.36 and does not
+            # support the -no-pie flag with the linker and generates warnings.
+            # Disable warnings as errors for the GCC toolchain only.
+            twister_cli.extend(["--disable-warnings-as-errors"])
+        elif intercepted_args.toolchain == "llvm":
+            gcov_tool = str(ec_base / "util" / "llvm-gcov.sh")
+        else:
+            print("Unknown toolchain specified:", intercepted_args.toolchain)
+        if intercepted_args.gcov_tool:
+            gcov_tool = intercepted_args.gcov_tool
+        if gcov_tool:
+            twister_cli.extend(["--gcov-tool", gcov_tool])
+
+        twister_env.update(extra_env_vars)
+
+        # Append additional user-supplied args
+        twister_cli.extend(other_args)
+
+        # Print exact CLI args and environment variables depending on verbosity.
+        if intercepted_args.verbose > 0:
+            print(
+                "Calling:", " ".join(shlex.quote(str(x)) for x in twister_cli)
+            )
+            print(
+                "With environment overrides:",
+                " ".join(
+                    f"{name}={shlex.quote(val)}"
+                    for name, val in extra_env_vars.items()
+                ),
+            )
+            sys.stdout.flush()
+
+        # Invoke Twister and wait for it to exit.
+        result = subprocess.run(
+            twister_cli,
+            env=twister_env,
+            check=False,
+            close_fds=False,  # For GNUMakefile jobserver
+        )
+
+        if check_for_skipped_tests(intercepted_args.outdir):
+            result.returncode = 1
+
+        if result.returncode == 0:
+            print("TEST EXECUTION SUCCESSFUL")
+        else:
+            print("TEST EXECUTION FAILED")
+
+        if is_tool("rdb") and intercepted_args.upload_cros_rdb:
+            upload_results(ec_base, intercepted_args.outdir)
+
+        sys.exit(result.returncode)
+
+
+if __name__ == "__main__":
+    main()
diff --git a/util/twister_tags.py b/util/twister_tags.py
new file mode 100755
index 0000000000..851c526bac
--- /dev/null
+++ b/util/twister_tags.py
@@ -0,0 +1,96 @@
+#!/usr/bin/env vpython3
+
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+"""
+Script that contains definitions for Twister test tags while also checking
+testcase.yaml files to see if they only used predefined tags.
+"""
+
+# [VPYTHON:BEGIN]
+# python_version: "3.8"
+# wheel: <
+#   name: "infra/python/wheels/pyyaml-py3"
+#   version: "version:5.3.1"
+# >
+# [VPYTHON:END]
+
+import argparse
+import logging
+import os
+import pathlib
+import sys
+
+import yaml  # pylint: disable=import-error
+
+
+TAG_TO_DESCRIPTION = {
+    "common": "Directly test shared code in the ec/common dir",
+    "mkbp": "Testing the MKBP (Matrix Keyboard Protocol) stack",
+    "system": "Directly test functions in common/system.c or shim/src/system.c",
+    "spi": "SPI related tests",
+    "uart": "UART related tests",
+}
+
+SCRIPT_PATH = os.path.realpath(__file__)
+
+
+def main(args):
+    """List and/or validate testcase.yaml tags."""
+    parser = argparse.ArgumentParser()
+    parser.add_argument("-l", "--list-tags", action="store_true")
+    parser.add_argument("--validate-files", nargs="*", type=pathlib.Path)
+    args = parser.parse_args()
+
+    list_tags = args.list_tags
+    validate_files = args.validate_files
+
+    logging.basicConfig(level=logging.INFO)
+    logger = logging.getLogger(__file__)
+
+    if list_tags:
+        logger.info("Listing defined Twister testcase.yaml test tags:")
+        for tag, description in TAG_TO_DESCRIPTION.items():
+            logger.info("%s=%s", tag, description)
+
+    if validate_files:
+        testcase_yamls = []
+
+        bad_tag = False
+
+        for validated_file in validate_files:
+            if os.path.basename(validated_file) == "testcase.yaml":
+                if validated_file.exists():
+                    testcase_yamls.append(validated_file)
+
+        def test_tags_generator(root):
+            """Returns space separated tags denoted by a tags key"""
+            if "tags" in root:
+                for tag in root["tags"].split(" "):
+                    yield tag
+
+            for val in root.values():
+                if isinstance(val, dict):
+                    for found in test_tags_generator(val):
+                        yield found
+
+        for testcase_yaml in testcase_yamls:
+            logger.info("Validating test tags in %s", testcase_yaml)
+            with open(testcase_yaml) as yaml_fd:
+                yaml_obj = yaml.safe_load(yaml_fd)
+                for tag in test_tags_generator(yaml_obj):
+                    if tag not in TAG_TO_DESCRIPTION:
+                        bad_tag = True
+                        # TODO(b/249280155) Suggest tag
+                        logger.error(
+                            f'Unrecognized tag: "{tag}" in {testcase_yaml}'
+                            + f' define "{tag}" in {SCRIPT_PATH}',
+                        )
+
+        if bad_tag:
+            sys.exit(1)
+
+
+if __name__ == "__main__":
+    main(sys.argv[1:])
diff --git a/util/uart_stress_tester.py b/util/uart_stress_tester.py
index c71826da25..2e96174930 100755
--- a/util/uart_stress_tester.py
+++ b/util/uart_stress_tester.py
@@ -1,6 +1,6 @@
 #!/usr/bin/env python3
 # -*- coding: utf-8 -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -30,474 +30,522 @@
 import threading
 import time
 
-import serial
+import serial  # pylint:disable=import-error
 
-BAUDRATE = 115200                # Default baudrate setting for UART port
-CROS_USERNAME = 'root'           # Account name to login to ChromeOS
-CROS_PASSWORD = 'test0000'       # Password to login to ChromeOS
-CHARGEN_TXT = '0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz'
-                                 # The result of 'chargen 62 62'
+
+BAUDRATE = 115200  # Default baudrate setting for UART port
+CROS_USERNAME = "root"  # Account name to login to ChromeOS
+CROS_PASSWORD = "test0000"  # Password to login to ChromeOS
+CHARGEN_TXT = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz"
+# The result of 'chargen 62 62'
 CHARGEN_TXT_LEN = len(CHARGEN_TXT)
-CR = '\r'                        # Carriage Return
-LF = '\n'                        # Line Feed
+CR = "\r"  # Carriage Return
+LF = "\n"  # Line Feed
 CRLF = CR + LF
-FLAG_FILENAME = '/tmp/chargen_testing'
-TPM_CMD = ('trunks_client --key_create --rsa=2048 --usage=sign'
-           ' --key_blob=/tmp/blob &> /dev/null')
-                                 # A ChromeOS TPM command for the cr50 stress
-                                 # purpose.
-CR50_LOAD_GEN_CMD = ('while [[ -f %s ]]; do   %s; done &'
-                     % (FLAG_FILENAME, TPM_CMD))
-                                 # A command line to run TPM_CMD in background
-                                 # infinitely.
+FLAG_FILENAME = "/tmp/chargen_testing"
+TPM_CMD = (
+    "trunks_client --key_create --rsa=2048 --usage=sign"
+    " --key_blob=/tmp/blob &> /dev/null"
+)
+# A ChromeOS TPM command for the cr50 stress
+# purpose.
+CR50_LOAD_GEN_CMD = "while [[ -f %s ]]; do   %s; done &" % (
+    FLAG_FILENAME,
+    TPM_CMD,
+)
+# A command line to run TPM_CMD in background
+# infinitely.
 
 
 class ChargenTestError(Exception):
-  """Exception for Uart Stress Test Error"""
-  pass
-
-
-class UartSerial(object):
-  """Test Object for a single UART serial device
-
-  Attributes:
-    UART_DEV_PROFILES
-    char_loss_occurrences: Number that character loss happens
-    cleanup_cli: Command list to perform before the test exits
-    cr50_workload: True if cr50 should be stressed, or False otherwise
-    usb_output: True if output should be generated to USB channel
-    dev_prof: Dictionary of device profile
-    duration: Time to keep chargen running
-    eol: Characters to add at the end of input
-    logger: object that store the log
-    num_ch_exp: Expected number of characters in output
-    num_ch_cap: Number of captured characters in output
-    test_cli: Command list to run for chargen test
-    test_thread: Thread object that captures the UART output
-    serial: serial.Serial object
-  """
-  UART_DEV_PROFILES = (
-      # Kernel
-      {
-          'prompt':'localhost login:',
-          'device_type':'AP',
-          'prepare_cmd':[
-              CROS_USERNAME,             # Login
-              CROS_PASSWORD,             # Password
-              'dmesg -D',                # Disable console message
-              'touch ' + FLAG_FILENAME,  # Create a temp file
-          ],
-          'cleanup_cmd':[
-              'rm -f ' + FLAG_FILENAME,  # Remove the temp file
-              'dmesg -E',                # Enable console message
-              'logout',                  # Logout
-          ],
-          'end_of_input':LF,
-      },
-      # EC
-      {
-          'prompt':'> ',
-          'device_type':'EC',
-          'prepare_cmd':[
-              'chan save',
-              'chan 0'                   # Disable console message
-          ],
-          'cleanup_cmd':['', 'chan restore'],
-          'end_of_input':CRLF,
-      },
-  )
-
-  def __init__(self, port, duration, timeout=1,
-               baudrate=BAUDRATE, cr50_workload=False,
-               usb_output=False):
-    """Initialize UartSerial
-
-    Args:
-      port: UART device path. e.g. /dev/ttyUSB0
-      duration: Time to test, in seconds
-      timeout: Read timeout value.
-      baudrate: Baud rate such as 9600 or 115200.
-      cr50_workload: True if a workload should be generated on cr50
-      usb_output: True if a workload should be generated to USB channel
-    """
-
-    # Initialize serial object
-    self.serial = serial.Serial()
-    self.serial.port = port
-    self.serial.timeout = timeout
-    self.serial.baudrate = baudrate
-
-    self.duration = duration
-    self.cr50_workload = cr50_workload
-    self.usb_output = usb_output
-
-    self.logger = logging.getLogger(type(self).__name__ + '| ' + port)
-    self.test_thread = threading.Thread(target=self.stress_test_thread)
-
-    self.dev_prof = {}
-    self.cleanup_cli = []
-    self.test_cli = []
-    self.eol = CRLF
-    self.num_ch_exp = 0
-    self.num_ch_cap = 0
-    self.char_loss_occurrences = 0
-    atexit.register(self.cleanup)
-
-  def run_command(self, command_lines, delay=0):
-    """Run command(s) at UART prompt
-
-    Args:
-      command_lines: list of commands to run.
-      delay: delay after a command in second
+    """Exception for Uart Stress Test Error"""
+
+
+class UartSerial:
+    """Test Object for a single UART serial device
+
+    Attributes:
+      UART_DEV_PROFILES
+      char_loss_occurrences: Number that character loss happens
+      cleanup_cli: Command list to perform before the test exits
+      cr50_workload: True if cr50 should be stressed, or False otherwise
+      usb_output: True if output should be generated to USB channel
+      dev_prof: Dictionary of device profile
+      duration: Time to keep chargen running
+      eol: Characters to add at the end of input
+      logger: object that store the log
+      num_ch_exp: Expected number of characters in output
+      num_ch_cap: Number of captured characters in output
+      test_cli: Command list to run for chargen test
+      test_thread: Thread object that captures the UART output
+      serial: serial.Serial object
     """
-    for cli in command_lines:
-      self.logger.debug('run %r', cli)
-
-      self.serial.write((cli + self.eol).encode())
-      self.serial.flush()
-      if delay:
-        time.sleep(delay)
-
-  def cleanup(self):
-    """Before termination, clean up the UART device."""
-    self.logger.debug('Closing...')
-
-    self.serial.open()
-    self.run_command(self.cleanup_cli)          # Run cleanup commands
-    self.serial.close()
 
-    self.logger.debug('Cleanup done')
-
-  def get_output(self):
-    """Capture the UART output
-
-    Args:
-      stop_char: Read output buffer until it reads stop_char.
-
-    Returns:
-      text from UART output.
+    UART_DEV_PROFILES = (
+        # Kernel
+        {
+            "prompt": "localhost login:",
+            "device_type": "AP",
+            "prepare_cmd": [
+                CROS_USERNAME,  # Login
+                CROS_PASSWORD,  # Password
+                "dmesg -D",  # Disable console message
+                "touch " + FLAG_FILENAME,  # Create a temp file
+            ],
+            "cleanup_cmd": [
+                "\x03",
+                "rm -f " + FLAG_FILENAME,  # Remove the temp file
+                "dmesg -E",  # Enable console message
+                "logout",  # Logout
+            ],
+            "end_of_input": LF,
+        },
+        # EC legacy
+        {
+            "prompt": ">",
+            "device_type": "EC(legacy)",
+            "prepare_cmd": ["chan save", "chan 0"],  # Disable console message
+            "cleanup_cmd": ["", "chan restore"],
+            "end_of_input": CRLF,
+        },
+        # EC Zephyr
+        {
+            "prompt": "ec:~$",
+            "device_type": "EC(Zephyr)",
+            "prepare_cmd": ["chan save", "chan 0"],  # Disable console message
+            "cleanup_cmd": ["x", "", "chan restore"],
+            "end_of_input": CRLF,
+        },
+    )
+
+    def __init__(
+        self,
+        port,
+        duration,
+        timeout=1,
+        baudrate=BAUDRATE,
+        cr50_workload=False,
+        usb_output=False,
+    ):
+        """Initialize UartSerial
+
+        Args:
+          port: UART device path. e.g. /dev/ttyUSB0
+          duration: Time to test, in seconds
+          timeout: Read timeout value.
+          baudrate: Baud rate such as 9600 or 115200.
+          cr50_workload: True if a workload should be generated on cr50
+          usb_output: True if a workload should be generated to USB channel
+        """
+
+        # Initialize serial object
+        self.serial = serial.Serial()
+        self.serial.port = port
+        self.serial.timeout = timeout
+        self.serial.baudrate = baudrate
+
+        self.duration = duration
+        self.cr50_workload = cr50_workload
+        self.usb_output = usb_output
+
+        self.logger = logging.getLogger(type(self).__name__ + "| " + port)
+        self.test_thread = threading.Thread(target=self.stress_test_thread)
+
+        self.dev_prof = {}
+        self.cleanup_cli = []
+        self.test_cli = []
+        self.eol = CRLF
+        self.num_ch_exp = 0
+        self.num_ch_cap = 0
+        self.char_loss_occurrences = 0
+        atexit.register(self.cleanup)
+
+    def run_command(self, command_lines, delay=0):
+        """Run command(s) at UART prompt
+
+        Args:
+          command_lines: list of commands to run.
+          delay: delay after a command in second
+        """
+        for cli in command_lines:
+            self.logger.debug("run %r", cli)
+
+            self.serial.write((cli + self.eol).encode())
+            self.serial.flush()
+            if delay:
+                time.sleep(delay)
+
+    def cleanup(self):
+        """Before termination, clean up the UART device."""
+        self.logger.debug("Closing...")
+
+        self.serial.open()
+        self.run_command(self.cleanup_cli)  # Run cleanup commands
+        self.serial.close()
+
+        self.logger.debug("Cleanup done")
+
+    def get_output(self):
+        """Capture the UART output
+
+        Args:
+          stop_char: Read output buffer until it reads stop_char.
+
+        Returns:
+          text from UART output.
+        """
+        if self.serial.inWaiting() == 0:
+            time.sleep(1)
+
+        return self.serial.read(self.serial.inWaiting()).decode(errors="ignore")
+
+    def prepare(self):
+        """Prepare the test:
+
+        Identify the type of UART device (EC or Kernel?), then
+        decide what kind of commands to use to generate stress loads.
+
+        Raises:
+          ChargenTestError if UART source can't be identified.
+        """
+        try:
+            self.logger.info("Preparing...")
+
+            self.serial.open()
+
+            # Prepare the device for test
+            self.serial.flushInput()
+            self.serial.flushOutput()
+
+            self.get_output()  # drain data
+
+            # Send a couple of line feeds, and capture the prompt text.
+            self.run_command(["", ""], delay=1)
+            prompt_txt = self.get_output()
+
+            # Detect the device source: EC or AP?
+            # Detect if the device is AP or EC console based on the captured.
+            for dev_prof in self.UART_DEV_PROFILES:
+                if dev_prof["prompt"] in prompt_txt:
+                    self.dev_prof = dev_prof
+                    break
+            else:
+                # No prompt patterns were found. UART seems not responding or in
+                # an undesirable status.
+                if prompt_txt:
+                    raise ChargenTestError(
+                        "%s: Got an unknown prompt text: %s\n"
+                        "Check manually whether %s is available."
+                        % (self.serial.port, prompt_txt, self.serial.port)
+                    )
+                raise ChargenTestError(
+                    "%s: Got no input. Close any other connections"
+                    " to this port, and try it again." % self.serial.port
+                )
+
+            self.logger.info(
+                "Detected as %s UART", self.dev_prof["device_type"]
+            )
+            # Log displays the UART type (AP|EC) instead of device filename.
+            self.logger = logging.getLogger(
+                type(self).__name__ + "| " + self.dev_prof["device_type"]
+            )
+
+            # Either login to AP or run some commands to prepare the device
+            # for test
+            self.eol = self.dev_prof["end_of_input"]
+            self.run_command(self.dev_prof["prepare_cmd"], delay=2)
+            self.cleanup_cli += self.dev_prof["cleanup_cmd"]
+
+            # 'chargen' of AP does not have option for USB output.
+            # Force it work on UART.
+            if self.dev_prof["device_type"] == "AP":
+                self.usb_output = False
+
+            # Check whether the command 'chargen' is available in the device.
+            # 'chargen 1 4' is supposed to print '0000'
+            self.get_output()  # drain data
+
+            chargen_cmd = "chargen 1 4"
+            if self.usb_output:
+                chargen_cmd += " usb"
+            self.run_command([chargen_cmd], delay=1)
+            tmp_txt = self.get_output()
+
+            # Check whether chargen command is available.
+            if "0000" not in tmp_txt:
+                raise ChargenTestError(
+                    "%s: Chargen got an unexpected result: %s"
+                    % (self.dev_prof["device_type"], tmp_txt)
+                )
+
+            self.num_ch_exp = int(self.serial.baudrate * self.duration / 10)
+            chargen_cmd = (
+                "chargen " + str(CHARGEN_TXT_LEN) + " " + str(self.num_ch_exp)
+            )
+            if self.usb_output:
+                chargen_cmd += " usb"
+            self.test_cli = [chargen_cmd]
+
+            self.logger.info("Ready to test")
+        finally:
+            self.serial.close()
+
+    def stress_test_thread(self):
+        """Test thread
+
+        Raises:
+          ChargenTestError: if broken character is found.
+        """
+        try:
+            self.serial.open()
+            self.serial.flushInput()
+            self.serial.flushOutput()
+
+            # Run TPM command in background to burden cr50.
+            if self.dev_prof["device_type"] == "AP" and self.cr50_workload:
+                self.run_command([CR50_LOAD_GEN_CMD])
+                self.logger.debug("run TPM job while %s exists", FLAG_FILENAME)
+
+            # Run the command 'chargen', one time
+            self.run_command([""])  # Give a line feed
+            self.get_output()  # Drain the output
+            self.run_command(self.test_cli, delay=1)
+            self.serial.readline()  # Drain the echoed command line.
+
+            err_msg = "%s: Expected %r but got %s after %d char received"
+
+            # Keep capturing the output until the test timer is expired.
+            self.num_ch_cap = 0
+            self.char_loss_occurrences = 0
+            data_starve_count = 0
+
+            # Expected number of characters in total
+            total_num_ch = self.num_ch_exp
+            ch_exp = CHARGEN_TXT[0]
+            # Any character value is ok for loop initial condition.
+            ch_cap = "z"
+
+            while self.num_ch_cap < total_num_ch:
+                captured = self.get_output()
+
+                if captured:
+                    if self.num_ch_cap == 0:
+                        # Strip prompt on first read (if it's there)
+                        start = captured.find("0123")
+                        if start > 0:
+                            captured = captured[start:]
+                    # There is some output data. Reset the data starvation count.
+                    data_starve_count = 0
+                else:
+                    data_starve_count += 1
+                    if data_starve_count > 1:
+                        # If nothing was captured more than once, then terminate the test.
+                        self.logger.debug("No more output")
+                        break
+
+                for ch_cap in captured:
+                    if ch_cap not in CHARGEN_TXT:
+                        self.logger.error(
+                            "Whole captured characters: %r", captured
+                        )
+                        raise ChargenTestError(
+                            err_msg
+                            % (
+                                "Broken char captured",
+                                ch_exp,
+                                hex(ord(ch_cap)),
+                                self.num_ch_cap,
+                            )
+                        )
+
+                    if ch_exp != ch_cap:
+                        # If it is alpha-numeric but not continuous, then some characters
+                        # are lost.
+                        self.logger.error(
+                            err_msg,
+                            "Char loss detected",
+                            ch_exp,
+                            repr(ch_cap),
+                            self.num_ch_cap,
+                        )
+                        self.char_loss_occurrences += 1
+
+                        # Recalculate the expected number of characters to adjust
+                        # termination condition. The loss might be bigger than this
+                        # adjustment, but it is okay since it will terminates by either
+                        # CR/LF detection or by data starvation.
+                        idx_ch_exp = CHARGEN_TXT.find(ch_exp)
+                        idx_ch_cap = CHARGEN_TXT.find(ch_cap)
+                        if idx_ch_cap < idx_ch_exp:
+                            idx_ch_cap += len(CHARGEN_TXT)
+                        total_num_ch -= idx_ch_cap - idx_ch_exp
+
+                    self.num_ch_cap += 1
+                    if self.num_ch_cap >= total_num_ch:
+                        break
+
+                    # Determine What character is expected next?
+                    ch_exp = CHARGEN_TXT[
+                        (CHARGEN_TXT.find(ch_cap) + 1) % CHARGEN_TXT_LEN
+                    ]
+
+        finally:
+            self.serial.close()
+
+    def start_test(self):
+        """Start the test thread"""
+        self.logger.info("Test thread starts")
+        self.test_thread.start()
+
+    def wait_test_done(self):
+        """Wait until the test thread get done and join"""
+        self.test_thread.join()
+        self.logger.info("Test thread is done")
+
+    def get_result(self):
+        """Display the result
+
+        Returns:
+          Integer = the number of lost character
+
+        Raises:
+          ChargenTestError: if the capture is corrupted.
+        """
+        # If more characters than expected are captured, it means some messages
+        # from other than chargen are mixed. Stop processing further.
+        if self.num_ch_exp < self.num_ch_cap:
+            raise ChargenTestError(
+                "%s: UART output is corrupted." % self.dev_prof["device_type"]
+            )
+
+        # Get the count difference between the expected to the captured
+        # as the number of lost character.
+        char_lost = self.num_ch_exp - self.num_ch_cap
+        self.logger.info(
+            "%8d char lost / %10d (%.1f %%)",
+            char_lost,
+            self.num_ch_exp,
+            char_lost * 100.0 / self.num_ch_exp,
+        )
+
+        return char_lost, self.num_ch_exp, self.char_loss_occurrences
+
+
+class ChargenTest:
+    """UART stress tester
+
+    Attributes:
+      logger: logging object
+      serials: Dictionary where key is filename of UART device, and the value is
+               UartSerial object
     """
-    if self.serial.inWaiting() == 0:
-      time.sleep(1)
-
-    return self.serial.read(self.serial.inWaiting()).decode()
-
-  def prepare(self):
-    """Prepare the test:
 
-    Identify the type of UART device (EC or Kernel?), then
-    decide what kind of commands to use to generate stress loads.
-
-    Raises:
-      ChargenTestError if UART source can't be identified.
-    """
-    try:
-      self.logger.info('Preparing...')
-
-      self.serial.open()
-
-      # Prepare the device for test
-      self.serial.flushInput()
-      self.serial.flushOutput()
-
-      self.get_output()      # drain data
-
-      # Give a couple of line feeds, and capture the prompt text
-      self.run_command(['', ''])
-      prompt_txt = self.get_output()
-
-      # Detect the device source: EC or AP?
-      # Detect if the device is AP or EC console based on the captured.
-      for dev_prof in self.UART_DEV_PROFILES:
-        if dev_prof['prompt'] in prompt_txt:
-          self.dev_prof = dev_prof
-          break
-      else:
-        # No prompt patterns were found. UART seems not responding or in
-        # an undesirable status.
-        if prompt_txt:
-          raise ChargenTestError('%s: Got an unknown prompt text: %s\n'
-                                 'Check manually whether %s is available.' %
-                                 (self.serial.port, prompt_txt,
-                                  self.serial.port))
+    def __init__(self, ports, duration, cr50_workload=False, usb_output=False):
+        """Initialize UART stress tester
+
+        Args:
+          ports: List of UART ports to test.
+          duration: Time to keep testing in seconds.
+          cr50_workload: True if a workload should be generated on cr50
+          usb_output: True if a workload should be generated to USB channel
+
+        Raises:
+          ChargenTestError: if any of ports is not a valid character device.
+        """
+
+        # Save the arguments
+        for port in ports:
+            try:
+                mode = os.stat(port).st_mode
+            except OSError as e:
+                raise ChargenTestError(e)
+            if not stat.S_ISCHR(mode):
+                raise ChargenTestError("%s is not a character device." % port)
+
+        if duration <= 0:
+            raise ChargenTestError("Input error: duration is not positive.")
+
+        # Initialize logging object
+        self.logger = logging.getLogger(type(self).__name__)
+
+        # Create an UartSerial object per UART port
+        self.serials = {}  # UartSerial objects
+        for port in ports:
+            self.serials[port] = UartSerial(
+                port=port,
+                duration=duration,
+                cr50_workload=cr50_workload,
+                usb_output=usb_output,
+            )
+
+    def prepare(self):
+        """Prepare the test for each UART port"""
+        self.logger.info("Prepare ports for test")
+        for _, ser in self.serials.items():
+            ser.prepare()
+        self.logger.info("Ports are ready to test")
+
+    def print_result(self):
+        """Display the test result for each UART port
+
+        Returns:
+          char_lost: Total number of characters lost
+        """
+        char_lost = 0
+        for _, ser in self.serials.items():
+            (tmp_lost, _, _) = ser.get_result()
+            char_lost += tmp_lost
+
+        # If any characters are lost, then test fails.
+        msg = "lost %d character(s) from the test" % char_lost
+        if char_lost > 0:
+            self.logger.error("FAIL: %s", msg)
         else:
-          raise ChargenTestError('%s: Got no input. Close any other connections'
-                                 ' to this port, and try it again.' %
-                                 self.serial.port)
-
-      self.logger.info('Detected as %s UART', self.dev_prof['device_type'])
-      # Log displays the UART type (AP|EC) instead of device filename.
-      self.logger = logging.getLogger(type(self).__name__ + '| ' +
-                                      self.dev_prof['device_type'])
-
-      # Either login to AP or run some commands to prepare the device
-      # for test
-      self.eol = self.dev_prof['end_of_input']
-      self.run_command(self.dev_prof['prepare_cmd'], delay=2)
-      self.cleanup_cli += self.dev_prof['cleanup_cmd']
-
-      # 'chargen' of AP does not have option for USB output.
-      # Force it work on UART.
-      if self.dev_prof['device_type'] == 'AP':
-        self.usb_output = False
-
-      # Check whether the command 'chargen' is available in the device.
-      # 'chargen 1 4' is supposed to print '0000'
-      self.get_output()      # drain data
-
-      chargen_cmd = 'chargen 1 4'
-      if self.usb_output:
-        chargen_cmd += ' usb'
-      self.run_command([chargen_cmd])
-      tmp_txt = self.get_output()
-
-      # Check whether chargen command is available.
-      if '0000' not in tmp_txt:
-        raise ChargenTestError('%s: Chargen got an unexpected result: %s' %
-                               (self.dev_prof['device_type'], tmp_txt))
-
-      self.num_ch_exp = int(self.serial.baudrate * self.duration / 10)
-      chargen_cmd = 'chargen ' + str(CHARGEN_TXT_LEN) + ' ' + \
-                    str(self.num_ch_exp)
-      if self.usb_output:
-        chargen_cmd += ' usb'
-      self.test_cli = [chargen_cmd]
-
-      self.logger.info('Ready to test')
-    finally:
-      self.serial.close()
-
-  def stress_test_thread(self):
-    """Test thread
-
-    Raises:
-      ChargenTestError: if broken character is found.
-    """
-    try:
-      self.serial.open()
-      self.serial.flushInput()
-      self.serial.flushOutput()
-
-      # Run TPM command in background to burden cr50.
-      if self.dev_prof['device_type'] == 'AP' and self.cr50_workload:
-        self.run_command([CR50_LOAD_GEN_CMD])
-        self.logger.debug('run TPM job while %s exists', FLAG_FILENAME)
-
-      # Run the command 'chargen', one time
-      self.run_command([''])  # Give a line feed
-      self.get_output()    # Drain the output
-      self.run_command(self.test_cli)
-      self.serial.readline()    # Drain the echoed command line.
-
-      err_msg = '%s: Expected %r but got %s after %d char received'
-
-      # Keep capturing the output until the test timer is expired.
-      self.num_ch_cap = 0
-      self.char_loss_occurrences = 0
-      data_starve_count = 0
-
-      total_num_ch = self.num_ch_exp    # Expected number of characters in total
-      ch_exp = CHARGEN_TXT[0]
-      ch_cap = 'z'      # any character value is ok for loop initial condition.
-      while self.num_ch_cap < total_num_ch:
-        captured = self.get_output()
-
-        if captured:
-          # There is some output data. Reset the data starvation count.
-          data_starve_count = 0
-        else:
-          data_starve_count += 1
-          if data_starve_count > 1:
-            # If nothing was captured more than once, then terminate the test.
-            self.logger.debug('No more output')
-            break
-
-        for ch_cap in captured:
-          if ch_cap not in CHARGEN_TXT:
-            # If it is not alpha-numeric, terminate the test.
-            if ch_cap not in CRLF:
-              # If it is neither a CR nor LF, then it is an error case.
-              self.logger.error('Whole captured characters: %r', captured)
-              raise ChargenTestError(err_msg % ('Broken char captured', ch_exp,
-                                                hex(ord(ch_cap)),
-                                                self.num_ch_cap))
-
-            # Set the loop termination condition true.
-            total_num_ch = self.num_ch_cap
-
-          if self.num_ch_cap >= total_num_ch:
-            break
-
-          if ch_exp != ch_cap:
-            # If it is alpha-numeric but not continuous, then some characters
-            # are lost.
-            self.logger.error(err_msg, 'Char loss detected',
-                              ch_exp, repr(ch_cap), self.num_ch_cap)
-            self.char_loss_occurrences += 1
-
-            # Recalculate the expected number of characters to adjust
-            # termination condition. The loss might be bigger than this
-            # adjustment, but it is okay since it will terminates by either
-            # CR/LF detection or by data starvation.
-            idx_ch_exp = CHARGEN_TXT.find(ch_exp)
-            idx_ch_cap = CHARGEN_TXT.find(ch_cap)
-            if idx_ch_cap < idx_ch_exp:
-              idx_ch_cap += len(CHARGEN_TXT)
-            total_num_ch -= (idx_ch_cap - idx_ch_exp)
-
-          self.num_ch_cap += 1
-
-          # Determine What character is expected next?
-          ch_exp = CHARGEN_TXT[(CHARGEN_TXT.find(ch_cap) + 1) % CHARGEN_TXT_LEN]
-
-    finally:
-      self.serial.close()
-
-  def start_test(self):
-    """Start the test thread"""
-    self.logger.info('Test thread starts')
-    self.test_thread.start()
-
-  def wait_test_done(self):
-    """Wait until the test thread get done and join"""
-    self.test_thread.join()
-    self.logger.info('Test thread is done')
-
-  def get_result(self):
-    """Display the result
+            self.logger.info("PASS: %s", msg)
 
-    Returns:
-      Integer = the number of lost character
+        return char_lost
 
-    Raises:
-      ChargenTestError: if the capture is corrupted.
-    """
-    # If more characters than expected are captured, it means some messages
-    # from other than chargen are mixed. Stop processing further.
-    if self.num_ch_exp < self.num_ch_cap:
-      raise ChargenTestError('%s: UART output is corrupted.' %
-                             self.dev_prof['device_type'])
+    def run(self):
+        """Run the stress test on UART port(s)
 
-    # Get the count difference between the expected to the captured
-    # as the number of lost character.
-    char_lost = self.num_ch_exp - self.num_ch_cap
-    self.logger.info('%8d char lost / %10d (%.1f %%)',
-                     char_lost, self.num_ch_exp,
-                     char_lost * 100.0 / self.num_ch_exp)
+        Raises:
+          ChargenTestError: If any characters are lost.
+        """
 
-    return char_lost, self.num_ch_exp, self.char_loss_occurrences
+        # Detect UART source type, and decide which command to test.
+        self.prepare()
 
+        # Run the test on each UART port in thread.
+        self.logger.info("Test starts")
+        for _, ser in self.serials.items():
+            ser.start_test()
 
-class ChargenTest(object):
-  """UART stress tester
+        # Wait all tests to finish.
+        for _, ser in self.serials.items():
+            ser.wait_test_done()
 
-  Attributes:
-    logger: logging object
-    serials: Dictionary where key is filename of UART device, and the value is
-             UartSerial object
-  """
+        # Print the result.
+        char_lost = self.print_result()
+        if char_lost:
+            raise ChargenTestError(
+                "Test failed: lost %d character(s)" % char_lost
+            )
 
-  def __init__(self, ports, duration, cr50_workload=False,
-               usb_output=False):
-    """Initialize UART stress tester
+        self.logger.info("Test is done")
 
-    Args:
-      ports: List of UART ports to test.
-      duration: Time to keep testing in seconds.
-      cr50_workload: True if a workload should be generated on cr50
-      usb_output: True if a workload should be generated to USB channel
 
-    Raises:
-      ChargenTestError: if any of ports is not a valid character device.
-    """
+def parse_args(cmdline):
+    """Parse command line arguments.
 
-    # Save the arguments
-    for port in ports:
-      try:
-        mode = os.stat(port).st_mode
-      except OSError as e:
-        raise ChargenTestError(e)
-      if not stat.S_ISCHR(mode):
-        raise ChargenTestError('%s is not a character device.' % port)
-
-    if duration <= 0:
-      raise ChargenTestError('Input error: duration is not positive.')
-
-    # Initialize logging object
-    self.logger = logging.getLogger(type(self).__name__)
-
-    # Create an UartSerial object per UART port
-    self.serials = {}     # UartSerial objects
-    for port in ports:
-      self.serials[port] = UartSerial(port=port, duration=duration,
-                                      cr50_workload=cr50_workload,
-                                      usb_output=usb_output)
-
-  def prepare(self):
-    """Prepare the test for each UART port"""
-    self.logger.info('Prepare ports for test')
-    for _, ser in self.serials.items():
-      ser.prepare()
-    self.logger.info('Ports are ready to test')
-
-  def print_result(self):
-    """Display the test result for each UART port
+    Args:
+      cmdline: list to be parsed
 
     Returns:
-      char_lost: Total number of characters lost
-    """
-    char_lost = 0
-    for _, ser in self.serials.items():
-      (tmp_lost, _, _) = ser.get_result()
-      char_lost += tmp_lost
-
-    # If any characters are lost, then test fails.
-    msg = 'lost %d character(s) from the test' % char_lost
-    if char_lost > 0:
-      self.logger.error('FAIL: %s', msg)
-    else:
-      self.logger.info('PASS: %s', msg)
-
-    return char_lost
-
-  def run(self):
-    """Run the stress test on UART port(s)
-
-    Raises:
-      ChargenTestError: If any characters are lost.
+      tuple (options, args) where args is a list of cmdline arguments that the
+      parser was unable to match i.e. they're servod controls, not options.
     """
-
-    # Detect UART source type, and decide which command to test.
-    self.prepare()
-
-    # Run the test on each UART port in thread.
-    self.logger.info('Test starts')
-    for _, ser in self.serials.items():
-      ser.start_test()
-
-    # Wait all tests to finish.
-    for _, ser in self.serials.items():
-      ser.wait_test_done()
-
-    # Print the result.
-    char_lost = self.print_result()
-    if char_lost:
-      raise ChargenTestError('Test failed: lost %d character(s)' %
-                             char_lost)
-
-    self.logger.info('Test is done')
-
-def parse_args(cmdline):
-  """Parse command line arguments.
-
-  Args:
-    cmdline: list to be parsed
-
-  Returns:
-    tuple (options, args) where args is a list of cmdline arguments that the
-    parser was unable to match i.e. they're servod controls, not options.
-  """
-  description = """%(prog)s repeats sending a uart console command
+    description = """%(prog)s repeats sending a uart console command
 to each UART device for a given time, and check if output
 has any missing characters.
 
@@ -507,52 +555,74 @@ def parse_args(cmdline):
     %(prog)s /dev/ttyUSB1 /dev/ttyUSB2 --cr50
 """
 
-  parser = argparse.ArgumentParser(description=description,
-                                   formatter_class=argparse.RawTextHelpFormatter
-                                  )
-  parser.add_argument('port', type=str, nargs='*',
-                      help='UART device path to test')
-  parser.add_argument('-c', '--cr50', action='store_true', default=False,
-                      help='generate TPM workload on cr50')
-  parser.add_argument('-d', '--debug', action='store_true', default=False,
-                      help='enable debug messages')
-  parser.add_argument('-t', '--time', type=int,
-                      help='Test duration in second', default=300)
-  parser.add_argument('-u', '--usb', action='store_true', default=False,
-                      help='Generate output to USB channel instead')
-  return parser.parse_known_args(cmdline)
+    parser = argparse.ArgumentParser(
+        description=description, formatter_class=argparse.RawTextHelpFormatter
+    )
+    parser.add_argument(
+        "port", type=str, nargs="*", help="UART device path to test"
+    )
+    parser.add_argument(
+        "-c",
+        "--cr50",
+        action="store_true",
+        default=False,
+        help="generate TPM workload on cr50",
+    )
+    parser.add_argument(
+        "-d",
+        "--debug",
+        action="store_true",
+        default=False,
+        help="enable debug messages",
+    )
+    parser.add_argument(
+        "-t", "--time", type=int, help="Test duration in second", default=300
+    )
+    parser.add_argument(
+        "-u",
+        "--usb",
+        action="store_true",
+        default=False,
+        help="Generate output to USB channel instead",
+    )
+    return parser.parse_known_args(cmdline)
 
 
 def main():
-  """Main function wrapper"""
-  try:
-    (options, _) = parse_args(sys.argv[1:])
-
-    # Set Log format
-    log_format = '%(asctime)s %(levelname)-6s | %(name)-25s'
-    date_format = '%Y-%m-%d %H:%M:%S'
-    if options.debug:
-      log_format += ' | %(filename)s:%(lineno)4d:%(funcName)-18s'
-      loglevel = logging.DEBUG
-    else:
-      loglevel = logging.INFO
-    log_format += ' | %(message)s'
-
-    logging.basicConfig(level=loglevel, format=log_format,
-                        datefmt=date_format)
-
-    # Create a ChargenTest object
-    utest = ChargenTest(options.port, options.time,
-                        cr50_workload=options.cr50,
-                        usb_output=options.usb)
-    utest.run()    # Run
-
-  except KeyboardInterrupt:
-    sys.exit(0)
-
-  except ChargenTestError as e:
-    logging.error(str(e))
-    sys.exit(1)
-
-if __name__ == '__main__':
-  main()
+    """Main function wrapper"""
+    try:
+        (options, _) = parse_args(sys.argv[1:])
+
+        # Set Log format
+        log_format = "%(asctime)s %(levelname)-6s | %(name)-25s"
+        date_format = "%Y-%m-%d %H:%M:%S"
+        if options.debug:
+            log_format += " | %(filename)s:%(lineno)4d:%(funcName)-18s"
+            loglevel = logging.DEBUG
+        else:
+            loglevel = logging.INFO
+        log_format += " | %(message)s"
+
+        logging.basicConfig(
+            level=loglevel, format=log_format, datefmt=date_format
+        )
+
+        # Create a ChargenTest object
+        utest = ChargenTest(
+            options.port,
+            options.time,
+            cr50_workload=options.cr50,
+            usb_output=options.usb,
+        )
+        utest.run()  # Run
+
+    except KeyboardInterrupt:
+        sys.exit(0)
+
+    except ChargenTestError as e:
+        logging.error(str(e))
+        sys.exit(1)
+
+
+if __name__ == "__main__":
+    main()
diff --git a/util/unpack_ftb.py b/util/unpack_ftb.py
index 62f5161a4a..4873190fb3 100755
--- a/util/unpack_ftb.py
+++ b/util/unpack_ftb.py
@@ -1,31 +1,33 @@
 #!/usr/bin/env python
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 # Note: This is a py2/3 compatible file.
 
 from __future__ import print_function
+
 import argparse
 import ctypes
 import os
 
 
 class Header(ctypes.Structure):
-  _pack_ = 1
-  _fields_ = [
-      ('signature', ctypes.c_uint32),
-      ('ftb_ver', ctypes.c_uint32),
-      ('chip_id', ctypes.c_uint32),
-      ('svn_ver', ctypes.c_uint32),
-      ('fw_ver', ctypes.c_uint32),
-      ('config_id', ctypes.c_uint32),
-      ('config_ver', ctypes.c_uint32),
-      ('reserved', ctypes.c_uint8 * 8),
-      ('release_info', ctypes.c_ulonglong),
-      ('sec_size', ctypes.c_uint32 * 4),
-      ('crc', ctypes.c_uint32),
-  ]
+    _pack_ = 1
+    _fields_ = [
+        ("signature", ctypes.c_uint32),
+        ("ftb_ver", ctypes.c_uint32),
+        ("chip_id", ctypes.c_uint32),
+        ("svn_ver", ctypes.c_uint32),
+        ("fw_ver", ctypes.c_uint32),
+        ("config_id", ctypes.c_uint32),
+        ("config_ver", ctypes.c_uint32),
+        ("reserved", ctypes.c_uint8 * 8),
+        ("release_info", ctypes.c_ulonglong),
+        ("sec_size", ctypes.c_uint32 * 4),
+        ("crc", ctypes.c_uint32),
+    ]
+
 
 FW_HEADER_SIZE = 64
 FW_HEADER_SIGNATURE = 0xAA55AA55
@@ -40,7 +42,7 @@ class Header(ctypes.Structure):
     0x0000 * 4,  # CODE
     0x7C00 * 4,  # CONFIG
     0x7000 * 4,  # CX
-    None  # This section shouldn't exist
+    None,  # This section shouldn't exist
 ]
 
 UPDATE_PDU_SIZE = 4096
@@ -55,64 +57,66 @@ class Header(ctypes.Structure):
 
 
 def main():
-  parser = argparse.ArgumentParser()
-  parser.add_argument('--input', '-i', required=True)
-  parser.add_argument('--output', '-o', required=True)
-  args = parser.parse_args()
+    parser = argparse.ArgumentParser()
+    parser.add_argument("--input", "-i", required=True)
+    parser.add_argument("--output", "-o", required=True)
+    args = parser.parse_args()
 
-  with open(args.input, 'rb') as f:
-    bs = f.read()
+    with open(args.input, "rb") as f:
+        bs = f.read()
 
-  size = len(bs)
-  if size < FW_HEADER_SIZE + FW_BYTES_ALIGN:
-    raise Exception('FW size too small')
+    size = len(bs)
+    if size < FW_HEADER_SIZE + FW_BYTES_ALIGN:
+        raise Exception("FW size too small")
 
-  print('FTB file size:', size)
+    print("FTB file size:", size)
 
-  header = Header()
-  assert ctypes.sizeof(header) == FW_HEADER_SIZE
+    header = Header()
+    assert ctypes.sizeof(header) == FW_HEADER_SIZE
 
-  ctypes.memmove(ctypes.addressof(header), bs, ctypes.sizeof(header))
-  if (header.signature != FW_HEADER_SIGNATURE or
-      header.ftb_ver != FW_FTB_VER or
-      header.chip_id != FW_CHIP_ID):
-    raise Exception('Invalid header')
+    ctypes.memmove(ctypes.addressof(header), bs, ctypes.sizeof(header))
+    if (
+        header.signature != FW_HEADER_SIGNATURE
+        or header.ftb_ver != FW_FTB_VER
+        or header.chip_id != FW_CHIP_ID
+    ):
+        raise Exception("Invalid header")
 
-  for key, _ in header._fields_:
-    v = getattr(header, key)
-    if isinstance(v, ctypes.Array):
-      print(key, list(map(hex, v)))
-    else:
-      print(key, hex(v))
+    for key, _ in header._fields_:
+        v = getattr(header, key)
+        if isinstance(v, ctypes.Array):
+            print(key, list(map(hex, v)))
+        else:
+            print(key, hex(v))
 
-  dimension = sum(header.sec_size)
+    dimension = sum(header.sec_size)
 
-  assert dimension + FW_HEADER_SIZE + FW_BYTES_ALIGN == size
-  data = bs[FW_HEADER_SIZE:FW_HEADER_SIZE + dimension]
+    assert dimension + FW_HEADER_SIZE + FW_BYTES_ALIGN == size
+    data = bs[FW_HEADER_SIZE : FW_HEADER_SIZE + dimension]
 
-  with open(args.output, 'wb') as f:
-    # ensure the file size
-    f.seek(OUTPUT_FILE_SIZE - 1, os.SEEK_SET)
-    f.write(b'\x00')
+    with open(args.output, "wb") as f:
+        # ensure the file size
+        f.seek(OUTPUT_FILE_SIZE - 1, os.SEEK_SET)
+        f.write(b"\x00")
 
-    f.seek(0, os.SEEK_SET)
-    f.write(bs[0 : ctypes.sizeof(header)])
+        f.seek(0, os.SEEK_SET)
+        f.write(bs[0 : ctypes.sizeof(header)])
 
-    offset = 0
-    # write each sections
-    for i, addr in enumerate(FLASH_SEC_ADDR):
-      size = header.sec_size[i]
-      assert addr is not None or size == 0
+        offset = 0
+        # write each sections
+        for i, addr in enumerate(FLASH_SEC_ADDR):
+            size = header.sec_size[i]
+            assert addr is not None or size == 0
 
-      if size == 0:
-        continue
+            if size == 0:
+                continue
 
-      f.seek(UPDATE_PDU_SIZE + addr, os.SEEK_SET)
-      f.write(data[offset : offset + size])
-      offset += size
+            f.seek(UPDATE_PDU_SIZE + addr, os.SEEK_SET)
+            f.write(data[offset : offset + size])
+            offset += size
 
-    f.flush()
+        f.flush()
 
 
-if __name__ == '__main__':
-  main()
+if __name__ == "__main__":
+    main()
diff --git a/util/update_release_branch.py b/util/update_release_branch.py
new file mode 100755
index 0000000000..93527c312c
--- /dev/null
+++ b/util/update_release_branch.py
@@ -0,0 +1,519 @@
+#!/usr/bin/env python3
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+"""Release branch updater tool.
+
+This is a tool to merge from the main branch into a release branch.
+
+Inspired by the fingerprint release process:
+http://go/cros-fingerprint-firmware-branching-and-signing and now used by other
+boards.
+"""
+from __future__ import print_function
+
+import argparse
+import os
+import re
+import subprocess
+import sys
+import textwrap
+
+
+BUG_NONE_PATTERN = re.compile("none", flags=re.IGNORECASE)
+
+
+def git_commit_msg(cros_main, branch, head, merge_head, rel_paths, cmd):
+    """Generates a merge commit message based off of relevant changes.
+
+    This function obtains the relevant commits from the given relative paths in
+    order to extract the bug numbers. It constructs the git commit message
+    showing the command used to find the relevant commits.
+
+    Args:
+        cros_main: String indicating the origin branch name
+        branch: String indicating the release branch name
+        head: String indicating the HEAD refspec
+        merge_head: String indicating the merge branch refspec.
+        rel_paths: String containing all the relevant paths for this particular
+                   baseboard or board.
+        cmd: String of the input command.
+
+    Returns:
+        A String containing the git commit message with the exception of the
+        Signed-Off-By field and Change-ID field.
+    """
+    relevant_commits_cmd, relevant_commits, relevant_hdr = get_relevant_commits(
+        head, merge_head, "--oneline", rel_paths
+    )
+
+    _, relevant_bugs, _ = get_relevant_commits(head, merge_head, "", rel_paths)
+    relevant_bugs = set(re.findall("BUG=(.*)", relevant_bugs))
+    # Filter out "none" from set of bugs
+    filtered = []
+    for bug_line in relevant_bugs:
+        bug_line = bug_line.replace(",", " ")
+        bugs = bug_line.split(" ")
+        for bug in bugs:
+            if bug and not BUG_NONE_PATTERN.match(bug):
+                filtered.append(bug)
+    relevant_bugs = filtered
+
+    # TODO(b/179509333): remove Cq-Include-Trybots line when regular CQ and
+    # firmware CQ do not behave differently.
+    commit_msg_template = """
+Merge remote-tracking branch {CROS_MAIN} into {BRANCH}
+
+Generated by: {COMMAND_LINE}
+
+{RELEVANT_COMMITS_HEADER}
+
+{RELEVANT_COMMITS_CMD}
+
+{RELEVANT_COMMITS}
+
+BRANCH=None
+{BUG_FIELD}
+TEST=`make -j buildall`
+
+Force-Relevant-Builds: all
+"""
+    # Wrap the commands and bug field such that we don't exceed 72 cols.
+    relevant_commits_cmd = textwrap.fill(relevant_commits_cmd, width=72)
+    cmd = textwrap.fill(cmd, width=72)
+    # Wrap at 68 cols to save room for 'BUG='
+    bugs = textwrap.wrap(" ".join(relevant_bugs), width=68)
+    bug_field = ""
+    for line in bugs:
+        bug_field += "BUG=" + line + "\n"
+    # Remove the final newline since the template adds it for us.
+    bug_field = bug_field[:-1]
+
+    return commit_msg_template.format(
+        CROS_MAIN=cros_main,
+        BRANCH=branch,
+        RELEVANT_COMMITS_CMD=relevant_commits_cmd,
+        RELEVANT_COMMITS=relevant_commits,
+        RELEVANT_COMMITS_HEADER=relevant_hdr,
+        BUG_FIELD=bug_field,
+        COMMAND_LINE=cmd,
+    )
+
+
+def get_relevant_boards(baseboard):
+    """Searches the EC repo looking for boards that use the given baseboard.
+
+    Args:
+        baseboard: String containing the baseboard to consider
+
+    Returns:
+        A list of strings containing the boards based off of the baseboard.
+    """
+    proc = subprocess.run(
+        ["git", "grep", "BASEBOARD:=" + baseboard, "--", "board/"],
+        stdout=subprocess.PIPE,
+        encoding="utf-8",
+        check=True,
+    )
+    boards = []
+    res = proc.stdout.splitlines()
+    for line in res:
+        boards.append(line.split("/")[1])
+    return boards
+
+
+def get_relevant_commits(head, merge_head, fmt, relevant_paths):
+    """Find relevant changes since last merge.
+
+    Searches git history to find changes since the last merge which modify
+    files present in relevant_paths.
+
+    Args:
+        head: String indicating the HEAD refspec
+        merge_head: String indicating the merge branch refspec.
+        fmt: An optional string containing the format option for `git log`
+        relevant_paths: String containing all the relevant paths for this
+                        particular baseboard or board.
+
+    Returns:
+        A tuple containing the arguments passed to the git log command and
+        stdout, and the header for the message
+    """
+    if not relevant_paths:
+        return "", "", ""
+    if fmt:
+        cmd = [
+            "git",
+            "log",
+            fmt,
+            head + ".." + merge_head,
+            "--",
+            relevant_paths,
+        ]
+    else:
+        cmd = ["git", "log", head + ".." + merge_head, "--", relevant_paths]
+
+    # Pass cmd as a string to subprocess.run() since we need to run with shell
+    # equal to True.  The reason we are using shell equal to True is to take
+    # advantage of the glob expansion for the relevant paths.
+    cmd = " ".join(cmd)
+    proc = subprocess.run(
+        cmd, stdout=subprocess.PIPE, encoding="utf-8", check=True, shell=True
+    )
+    return "".join(proc.args), proc.stdout, "Relevant changes:"
+
+
+def merge_repo(
+    base, cros_main, cmd_checkout, strategy, cmd, prunelist, relevant_paths
+):
+    """Merge changes from ToT into this repo's branch.
+
+    For this repo, merge the changes from ToT to the branch set
+    in the merge command.
+
+    Args:
+        base: String indicating the Source directory of repo.
+        cros_main: String indicating the origin branch name
+        cmd_checkout: String list containing the checkout command to use.
+        strategy: String list containing the merge strategy,
+        cmd: String containing the command line
+        prunelist: String list containing the files to remove.
+        relevant_paths: String containing all the relevant paths for this
+                        particular baseboard or board.
+    """
+    # Change directory to the repo being merged
+    print('Starting merge in "%s"' % base)
+    print('Checkout command: "%s"' % " ".join(cmd_checkout))
+    os.chdir(base)
+    # Check if we are already in merge process
+    result = subprocess.run(
+        ["git", "rev-parse", "--quiet", "--verify", "MERGE_HEAD"],
+        stdout=subprocess.DEVNULL,
+        stderr=subprocess.DEVNULL,
+        check=False,
+    )
+
+    if result.returncode:
+        # Let's perform the merge
+        print("Updating remote...")
+        subprocess.run(["git", "remote", "update"], check=True)
+        subprocess.run(cmd_checkout, check=True)
+        cmd_merge = [
+            "git",
+            "merge",
+            "--no-ff",
+            "--no-commit",
+            cros_main,
+            "-s",
+        ]
+        cmd_merge.extend(strategy)
+        print('Merge command: "%s"' % " ".join(cmd_merge))
+        try:
+            subprocess.run(cmd_merge, check=True)
+        except subprocess.CalledProcessError:
+            # We've likely encountered a merge conflict due to new OWNERS file
+            # modifications. If we're removing the owners, we'll delete them.
+            if prunelist:
+                # Find the unmerged files
+                unmerged = (
+                    subprocess.run(
+                        ["git", "diff", "--name-only", "--diff-filter=U"],
+                        stdout=subprocess.PIPE,
+                        encoding="utf-8",
+                        check=True,
+                    )
+                    .stdout.rstrip()
+                    .split()
+                )
+
+                # Prune OWNERS files
+                for file in unmerged:
+                    if file in prunelist:
+                        subprocess.run(["git", "rm", file], check=False)
+                        unmerged.remove(file)
+
+                print("Removed non-root OWNERS files.")
+                if unmerged:
+                    print(
+                        "Unmerged files still exist! You need to manually resolve this."
+                    )
+                    print("\n".join(unmerged))
+                    sys.exit(1)
+            else:
+                raise
+    else:
+        print(
+            "We have already started merge process.",
+            "Attempt to generate commit.",
+        )
+    # Check whether any commit is needed.
+    changes = subprocess.run(
+        ["git", "status", "--porcelain"],
+        stdout=subprocess.PIPE,
+        encoding="utf-8",
+        check=True,
+    ).stdout.rstrip()
+    if not changes:
+        print("No changes have been found, skipping commit.")
+        return
+
+    print("Generating commit message...")
+    branch = subprocess.run(
+        ["git", "rev-parse", "--abbrev-ref", "HEAD"],
+        stdout=subprocess.PIPE,
+        encoding="utf-8",
+        check=True,
+    ).stdout.rstrip()
+    head = subprocess.run(
+        ["git", "rev-parse", "--short", "HEAD"],
+        stdout=subprocess.PIPE,
+        encoding="utf-8",
+        check=True,
+    ).stdout.rstrip()
+    merge_head = subprocess.run(
+        ["git", "rev-parse", "--short", "MERGE_HEAD"],
+        stdout=subprocess.PIPE,
+        encoding="utf-8",
+        check=True,
+    ).stdout.rstrip()
+
+    print("Typing as fast as I can...")
+    commit_msg = git_commit_msg(
+        cros_main, branch, head, merge_head, relevant_paths, cmd
+    )
+    subprocess.run(["git", "commit", "--signoff", "-m", commit_msg], check=True)
+    subprocess.run(["git", "commit", "--amend"], check=True)
+
+
+def main(argv):
+    """Generates a merge commit from ToT to a desired release branch.
+
+    For the commit message, it finds all the commits that have modified a
+    relevant path. By default this is the baseboard or board directory.  The
+    user may optionally specify a path to a text file which contains a longer
+    list of relevant files.  The format should be in the glob syntax that git
+    log expects.
+
+    Args:
+        argv: A list of the command line arguments passed to this script.
+    """
+    # Set up argument parser.
+    parser = argparse.ArgumentParser(
+        description=(
+            "A script that generates a "
+            "merge commit from cros/main"
+            " to a desired release "
+            "branch.  By default, the "
+            '"recursive" merge strategy '
+            'with the "theirs" strategy '
+            "option is used."
+        )
+    )
+    parser.add_argument("--baseboard")
+    parser.add_argument("--board")
+    parser.add_argument(
+        "release_branch",
+        help=(
+            "The name of the target release branch, "
+            "without the trailing '-main'."
+        ),
+    )
+    parser.add_argument(
+        "--remote_prefix",
+        help=(
+            "The name of the remote branch prefix (default cros). "
+            "Private repos typically use cros-internal instead."
+        ),
+        default="cros",
+    )
+    parser.add_argument(
+        "--srcbase",
+        help=("The base directory where the src tree exists."),
+        default="/mnt/host/source/",
+    )
+    parser.add_argument(
+        "--relevant_paths_file",
+        help=(
+            "A path to a text file which includes other "
+            "relevant paths of interest for this board "
+            "or baseboard"
+        ),
+    )
+    parser.add_argument(
+        "--merge_strategy",
+        "-s",
+        default="recursive",
+        help="The merge strategy to pass to `git merge -s`",
+    )
+    parser.add_argument(
+        "--strategy_option",
+        "-X",
+        help=("The strategy option for the chosen merge strategy"),
+    )
+    parser.add_argument(
+        "--remove_owners",
+        "-r",
+        action=("store_true"),
+        help=("Remove non-root OWNERS level files if present"),
+    )
+    parser.add_argument(
+        "--zephyr",
+        "-z",
+        action=("store_true"),
+        help=("If set, treat the board as a Zephyr based program"),
+    )
+
+    opts = parser.parse_args(argv[1:])
+
+    baseboard_dir = ""
+    board_dir = ""
+
+    if opts.baseboard:
+        # If a zephyr board, no baseboard allowed
+        if opts.zephyr:
+            raise Exception("--baseboard not allowed for Zephyr boards")
+        # Dereference symlinks so "git log" works as expected.
+        baseboard_dir = os.path.relpath("baseboard/" + opts.baseboard)
+        baseboard_dir = os.path.relpath(os.path.realpath(baseboard_dir))
+
+        boards = get_relevant_boards(opts.baseboard)
+    elif opts.board:
+        if opts.zephyr:
+            board_dir = os.path.relpath("zephyr/program/" + opts.board)
+        else:
+            board_dir = os.path.relpath("board/" + opts.board)
+        board_dir = os.path.relpath(os.path.realpath(board_dir))
+        boards = [opts.board]
+    else:
+        # With no board or baseboard, not sure whether this should proceed
+        raise Exception("no board or baseboard specified")
+
+    print("Gathering relevant paths...")
+    relevant_paths = []
+    if opts.baseboard:
+        relevant_paths.append(baseboard_dir)
+    elif opts.board:
+        relevant_paths.append(board_dir)
+
+    if not opts.zephyr:
+        for board in boards:
+            relevant_paths.append("board/" + board)
+
+    # Check for the existence of a file that has other paths of interest.
+    # Also check for 'relevant-paths.txt' in the board directory
+    if opts.relevant_paths_file and os.path.exists(opts.relevant_paths_file):
+        with open(opts.relevant_paths_file, "r") as relevant_paths_file:
+            for line in relevant_paths_file:
+                if not line.startswith("#"):
+                    relevant_paths.append(line.rstrip())
+    if os.path.exists("util/getversion.sh"):
+        relevant_paths.append("util/getversion.sh")
+    relevant_paths = " ".join(relevant_paths)
+
+    # Prune OWNERS files if desired
+    prunelist = []
+    if opts.remove_owners:
+        for root, dirs, files in os.walk("."):
+            for name in dirs:
+                if "build" in name:
+                    continue
+            for name in files:
+                if "OWNERS" in name:
+                    path = os.path.join(root, name)
+                    prunelist.append(path[2:])  # Strip the "./"
+
+        # Remove the top level OWNERS file from the prunelist.
+        try:
+            prunelist.remove("OWNERS")
+        except ValueError:
+            pass
+
+        if prunelist:
+            print("Not merging the following OWNERS files:")
+            for path in prunelist:
+                print("  " + path)
+
+    # Create the merge and checkout commands to use.
+    cmd_checkout = [
+        "git",
+        "checkout",
+        "-B",
+        opts.release_branch,
+        opts.remote_prefix + "/" + opts.release_branch,
+    ]
+    if opts.merge_strategy == "recursive" and not opts.strategy_option:
+        opts.strategy_option = "theirs"
+    print(
+        'Using "%s" merge strategy' % opts.merge_strategy,
+        (
+            "with strategy option '%s'" % opts.strategy_option
+            if opts.strategy_option
+            else ""
+        ),
+    )
+    cros_main = opts.remote_prefix + "/" + "main"
+    strategy = [
+        opts.merge_strategy,
+    ]
+    if opts.strategy_option:
+        strategy.append("-X" + opts.strategy_option)
+    cmd = " ".join(argv)
+
+    # Merge each of the repos
+    merge_repo(
+        os.path.join(opts.srcbase, "src/platform/ec"),
+        cros_main,
+        cmd_checkout,
+        strategy,
+        cmd,
+        prunelist,
+        relevant_paths,
+    )
+    if opts.zephyr:
+        # Strip off any trailing -main or -master from branch name
+        if opts.release_branch.endswith("-main"):
+            opts.release_branch = opts.release_branch[:-5]
+        if opts.release_branch.endswith("-master"):
+            opts.release_branch = opts.release_branch[:-7]
+        cmd_checkout = [
+            "git",
+            "checkout",
+            "-B",
+            opts.release_branch,
+            opts.remote_prefix + "/" + opts.release_branch,
+        ]
+        prunelist = []
+        if opts.remove_owners:
+            # Remove the top level OWNERS file from the list
+            # to avoid any conflict with the modified branch file.
+            prunelist.append("OWNERS")
+        merge_repo(
+            os.path.join(opts.srcbase, "src/third_party/zephyr/main"),
+            cros_main,
+            cmd_checkout,
+            strategy,
+            cmd,
+            prunelist,
+            [],
+        )
+        # cmsis repo has different remote
+        cros_main = opts.remote_prefix + "/" + "chromeos-main"
+        merge_repo(
+            os.path.join(opts.srcbase, "src/third_party/zephyr/cmsis"),
+            cros_main,
+            cmd_checkout,
+            strategy,
+            cmd,
+            prunelist,
+            [],
+        )
+    print(
+        (
+            "Finished! **Please review the commit(s) to see if they're to your "
+            "liking.**"
+        )
+    )
+
+
+if __name__ == "__main__":
+    main(sys.argv)
diff --git a/util/update_release_branch.sh b/util/update_release_branch.sh
deleted file mode 100755
index 4013c75ee3..0000000000
--- a/util/update_release_branch.sh
+++ /dev/null
@@ -1,95 +0,0 @@
-#!/bin/bash
-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Tool to merge master branch into a release branch. Currently specific to the
-# fingerprint sensor, but can easily be generalized. See
-# http://go/cros-fingerprint-firmware-branching-and-signing.
-
-. /usr/share/misc/shflags
-
-DEFINE_string 'board' "bloonchipper" 'EC board (FPMCU) to update' 'b'
-
-# Process commandline flags.
-FLAGS "${@}" || exit 1
-eval set -- "${FLAGS_ARGV}"
-
-set -e
-
-# Dereference symlinks so "git log" works as expected.
-readonly BOARD_DIR="$(realpath --relative-to=. "board/${FLAGS_board}")"
-readonly RELEVANT_PATHS=(
-  "${BOARD_DIR}"
-  common/fpsensor
-  docs/fingerprint
-  driver/fingerprint
-  util/getversion.sh
-)
-readonly RELEASE_BRANCH="firmware-fpmcu-${FLAGS_board}-release"
-
-get_relevant_commits_cmd() {
-  local head="${1}"
-  local merge_head="${2}"
-  local format="${3}"
-
-  local relevant_commits_cmd="git log ${format} ${head}..${merge_head}"
-  relevant_commits_cmd+=" -- ${RELEVANT_PATHS[*]}"
-  echo "${relevant_commits_cmd}"
-}
-
-git_commit_msg() {
-  local branch="${1}"
-  local head="${2}"
-  local merge_head="${3}"
-
-  local relevant_commits_cmd
-  local relevant_commits
-  local relevant_bugs_cmd
-  local relevant_bugs
-
-  relevant_commits_cmd="$(get_relevant_commits_cmd "${head}" \
-    "${merge_head}" "--oneline")"
-  relevant_commits="$(${relevant_commits_cmd})"
-  relevant_bugs_cmd="$(get_relevant_commits_cmd "${head}" \
-    "${merge_head}" "")"
-  relevant_bugs="$(${relevant_bugs_cmd} | \
-    pcregrep -o1 'BUG=(.*)' | pcregrep -v none | \
-    tr ' ' '\n' | tr ',' '\n' | \
-    sort | uniq | xargs)"
-
-  cat <<HEREDOC
-Merge remote-tracking branch 'm/master' into ${branch}
-
-Relevant changes:
-
-${relevant_commits_cmd}
-
-${relevant_commits}
-
-BRANCH=none
-BUG=${relevant_bugs}
-TEST=test_that --board <board> <IP> suite:fingerprint
-HEREDOC
-}
-
-merge_master() {
-  git remote update
-  git checkout -B "${RELEASE_BRANCH}" "cros/${RELEASE_BRANCH}"
-  git merge --no-ff --no-commit m/master
-
-  local branch
-  local head
-  local merge_head
-
-  branch="$(git rev-parse --abbrev-ref HEAD)"
-  head="$(git rev-parse --short HEAD)"
-  merge_head="$(git rev-parse --short MERGE_HEAD)"
-
-  git commit --signoff -m "$(git_commit_msg "${branch}" \
-    "${head}" "${merge_head}")"
-  git commit --amend
-}
-
-merge_master
diff --git a/util/usb_if.c b/util/usb_if.c
index f8aa6bfd7e..eec8b22f5b 100644
--- a/util/usb_if.c
+++ b/util/usb_if.c
@@ -1,27 +1,25 @@
 /*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "usb_if.h"
+
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
 
-#include "usb_if.h"
-
 /* Return 0 on error, since it's never gonna be EP 0 */
 static int find_endpoint(const struct libusb_interface_descriptor *iface,
-			 uint16_t subclass,
-			 uint16_t protocol,
+			 uint16_t subclass, uint16_t protocol,
 			 struct usb_endpoint *uep)
 {
 	const struct libusb_endpoint_descriptor *ep;
 
 	if (iface->bInterfaceClass == 255 &&
 	    iface->bInterfaceSubClass == subclass &&
-	    iface->bInterfaceProtocol == protocol &&
-	    iface->bNumEndpoints) {
+	    iface->bInterfaceProtocol == protocol && iface->bNumEndpoints) {
 		ep = &iface->endpoint[0];
 		uep->ep_num = ep->bEndpointAddress & 0x7f;
 		uep->chunk_len = ep->wMaxPacketSize;
@@ -32,8 +30,7 @@ static int find_endpoint(const struct libusb_interface_descriptor *iface,
 }
 
 /* Return -1 on error */
-static int find_interface(uint16_t subclass,
-			  uint16_t protocol,
+static int find_interface(uint16_t subclass, uint16_t protocol,
 			  struct usb_endpoint *uep)
 {
 	int iface_num = -1;
@@ -66,8 +63,8 @@ static int find_interface(uint16_t subclass,
 	return iface_num;
 }
 
-static libusb_device_handle *check_device(libusb_device *dev,
-	uint16_t vid, uint16_t pid, const char *serial)
+static libusb_device_handle *check_device(libusb_device *dev, uint16_t vid,
+					  uint16_t pid, const char *serial)
 {
 	struct libusb_device_descriptor desc;
 	libusb_device_handle *handle = NULL;
@@ -81,18 +78,17 @@ static libusb_device_handle *check_device(libusb_device *dev,
 		return NULL;
 
 	if (desc.iSerialNumber && serial) {
-		sn_size = libusb_get_string_descriptor_ascii(handle,
-				desc.iSerialNumber, (unsigned char *)sn,
-				sizeof(sn));
+		sn_size = libusb_get_string_descriptor_ascii(
+			handle, desc.iSerialNumber, (unsigned char *)sn,
+			sizeof(sn));
 	}
 	/*
 	 * If the VID, PID, and serial number don't match, then it's not the
 	 * correct device. Close the handle and return NULL.
 	 */
-	if ((vid && vid != desc.idVendor) ||
-	    (pid && pid != desc.idProduct) ||
-	    (serial && ((sn_size != strlen(serial)) ||
-	    memcmp(sn, serial, sn_size)))) {
+	if ((vid && vid != desc.idVendor) || (pid && pid != desc.idProduct) ||
+	    (serial &&
+	     ((sn_size != strlen(serial)) || memcmp(sn, serial, sn_size)))) {
 		libusb_close(handle);
 		return NULL;
 	}
@@ -156,8 +152,8 @@ int usb_findit(const char *serial, uint16_t vid, uint16_t pid,
 		goto terminate_usb_findit;
 	}
 
-	printf("found interface %d endpoint %d, chunk_len %d\n",
-	       iface_num, uep->ep_num, uep->chunk_len);
+	printf("found interface %d endpoint %d, chunk_len %d\n", iface_num,
+	       uep->ep_num, uep->chunk_len);
 
 	libusb_set_auto_detach_kernel_driver(uep->devh, 1);
 	r = libusb_claim_interface(uep->devh, iface_num);
@@ -175,17 +171,15 @@ int usb_findit(const char *serial, uint16_t vid, uint16_t pid,
 	return -1;
 }
 
-int usb_trx(struct usb_endpoint *uep, void *outbuf, int outlen,
-	    void *inbuf, int inlen, int allow_less, size_t *rxed_count)
+int usb_trx(struct usb_endpoint *uep, void *outbuf, int outlen, void *inbuf,
+	    int inlen, int allow_less, size_t *rxed_count)
 {
-
 	int r, actual;
 
 	/* Send data out */
 	if (outbuf && outlen) {
 		actual = 0;
-		r = libusb_bulk_transfer(uep->devh, uep->ep_num,
-					 outbuf, outlen,
+		r = libusb_bulk_transfer(uep->devh, uep->ep_num, outbuf, outlen,
 					 &actual, 1000);
 		if (r < 0) {
 			USB_ERROR("libusb_bulk_transfer", r);
@@ -200,11 +194,9 @@ int usb_trx(struct usb_endpoint *uep, void *outbuf, int outlen,
 
 	/* Read reply back */
 	if (inbuf && inlen) {
-
 		actual = 0;
-		r = libusb_bulk_transfer(uep->devh, uep->ep_num | 0x80,
-					 inbuf, inlen,
-					 &actual, 1000);
+		r = libusb_bulk_transfer(uep->devh, uep->ep_num | 0x80, inbuf,
+					 inlen, &actual, 1000);
 		if (r < 0) {
 			USB_ERROR("libusb_bulk_transfer", r);
 			return -1;
diff --git a/util/usb_if.h b/util/usb_if.h
index 8cc1088c6e..37a33f6287 100644
--- a/util/usb_if.h
+++ b/util/usb_if.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,7 +13,7 @@
 struct usb_endpoint {
 	struct libusb_device_handle *devh;
 	uint8_t ep_num;
-	int     chunk_len;
+	int chunk_len;
 };
 
 /*
@@ -34,9 +34,8 @@ int usb_findit(const char *serialno, uint16_t vid, uint16_t pid,
  * pointer, if provided along with 'allow_less', lets the caller know how many
  * bytes were received.
  */
-int usb_trx(struct usb_endpoint *uep, void *outbuf, int outlen,
-	    void *inbuf, int inlen, int allow_less,
-	    size_t *rxed_count);
+int usb_trx(struct usb_endpoint *uep, void *outbuf, int outlen, void *inbuf,
+	    int inlen, int allow_less, size_t *rxed_count);
 
 /*
  * This function should be called for graceful tear down of the USB interface
@@ -46,8 +45,8 @@ int usb_trx(struct usb_endpoint *uep, void *outbuf, int outlen,
  */
 void usb_shut_down(struct usb_endpoint *uep);
 
-#define USB_ERROR(m, r) \
-	fprintf(stderr, "%s:%d, %s returned %d (%s)\n", __FILE__, __LINE__, \
-		m, r, libusb_strerror(r))
+#define USB_ERROR(m, r)                                                        \
+	fprintf(stderr, "%s:%d, %s returned %d (%s)\n", __FILE__, __LINE__, m, \
+		r, libusb_strerror(r))
 
-#endif  /* ! __EC_EXTRA_USB_UPDATER_USB_IF_H */
+#endif /* ! __EC_EXTRA_USB_UPDATER_USB_IF_H */
diff --git a/util/uut/cmd.c b/util/uut/cmd.c
deleted file mode 100644
index 57cf75a29e..0000000000
--- a/util/uut/cmd.c
+++ /dev/null
@@ -1,482 +0,0 @@
-/*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* This file creates the UART Program Protocol API commands. */
-
-#include <stdint.h>
-#include <stdio.h>
-#include <string.h>
-
-#include "cmd.h"
-#include "lib_crc.h"
-#include "main.h"
-
- /* Extracting Byte - 8 bit: MSB, LSB */
-#define MSB(u16) ((uint8_t)((uint16_t)(u16) >> 8))
-#define LSB(u16) ((uint8_t)(u16))
-
-/*----------------------------------------------------------------------------
- *  SPI Flash commands
- *---------------------------------------------------------------------------
- */
-
-#define SPI_READ_JEDEC_ID_CMD 0x9F
-#define SPI_WRITE_ENABLE_CMD 0x06
-#define SPI_WRITE_DISABLE_CMD 0x04
-#define SPI_READ_STATUS_REG_CMD 0x05
-#define SPI_WRITE_STATUS_REG_CMD 0x01
-#define SPI_READ_DATA_CMD 0x03
-#define SPI_PAGE_PRGM_CMD 0x02
-#define SPI_SECTOR_ERASE_CMD 0xD8
-#define SPI_BULK_ERASE_CMD 0xC7
-#define SPI_READ_PID_CMD 0x90
-
-union cmd_addr {
-	uint8_t c_adr[4];
-	uint32_t h_adr;
-};
-
-/*----------------------------------------------------------------------------
- * Function implementation
- *---------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * Function:	cmd_create_sync
- *
- * Parameters:	   cmd_info - Pointer to a command buffer.
- *		   cmd_len  - Pointer to command length.
- * Returns:	   none.
- * Side effects:
- * Description:
- *		Create a Host to Device SYNC protocol command.
- *		The total command length is written to 'cmd_len'.
- *---------------------------------------------------------------------------
- */
-void cmd_create_sync(uint8_t *cmd_info, uint32_t *cmd_len)
-{
-	uint32_t len = 0;
-
-	/* Build the command buffer */
-	cmd_info[len++] = UFPP_H2D_SYNC_CMD;
-
-	/* Return total command length */
-	*cmd_len = len;
-}
-
-/*---------------------------------------------------------------------------
- * Function:       cmd_create_write
- *
- * Parameters:	addr    - Memory address to write to.
- *		size    - Size of daya (in bytes) to write to memory.
- *		data_buf - Pointer to data buffer containing raw data to write.
- *		cmd_info - Pointer to a command buffer.
- *		cmd_len  - Pointer to command length.
- * Returns:     none.
- * Side effects:
- * Description:
- *	Create a WRITE protocol command.
- *	The command buffer is enclosed by CRC, calculated on command
- *	information and raw data.
- *	The total command length is written to 'cmd_len'.
- *---------------------------------------------------------------------------
- */
-void cmd_create_write(uint32_t addr, uint32_t size, uint8_t *data_buf,
-					uint8_t *cmd_info, uint32_t *cmd_len)
-{
-	uint32_t i;
-	union cmd_addr adr_tr;
-	uint16_t crc = 0;
-	uint32_t len = 0;
-
-	/* Build the command buffer */
-	cmd_info[len++] = UFPP_WRITE_CMD;
-	cmd_info[len++] = (uint8_t)(size - 1);
-
-	/* Insert Address */
-	adr_tr.h_adr = addr;
-	cmd_info[len++] = adr_tr.c_adr[3];
-	cmd_info[len++] = adr_tr.c_adr[2];
-	cmd_info[len++] = adr_tr.c_adr[1];
-	cmd_info[len++] = adr_tr.c_adr[0];
-
-	/* Insert data */
-	memcpy(&cmd_info[len], data_buf, size);
-	len += size;
-
-	/* Calculate CRC */
-	for (i = 0; i < len; i++)
-		crc = update_crc(crc, (char)cmd_info[i]);
-
-	/* Insert CRC */
-	cmd_info[len++] = MSB(crc);
-	cmd_info[len++] = LSB(crc);
-
-	/* Return total command length */
-	*cmd_len = len;
-}
-
-/*----------------------------------------------------------------------------
- * Function:	cmd_create_read
- *
- * Parameters:	addr    - Memory address to read from.
- *		size    - Size of daya (in bytes) to read from memory.
- *		cmd_info - Pointer to a command buffer.
- *		cmd_len  - Pointer to command length.
- * Returns:	none.
- * Side effects:
- * Description:
- *		Create a READ protocol command.
- *		The command buffer is enclosed by CRC, calculated on command
- *		information and raw data.
- *		The total command length is written to 'cmd_len'.
- *---------------------------------------------------------------------------
- */
-void cmd_create_read(uint32_t addr, uint8_t size, uint8_t *cmd_info,
-					uint32_t *cmd_len)
-{
-	uint32_t i;
-	union cmd_addr adr_tr;
-	uint16_t crc = 0;
-	uint32_t len = 0;
-
-	/* Build the command buffer */
-	cmd_info[len++] = UFPP_READ_CMD;
-	cmd_info[len++] = (uint8_t)size;
-
-	/* Insert Address */
-	adr_tr.h_adr = addr;
-	cmd_info[len++] = adr_tr.c_adr[3];
-	cmd_info[len++] = adr_tr.c_adr[2];
-	cmd_info[len++] = adr_tr.c_adr[1];
-	cmd_info[len++] = adr_tr.c_adr[0];
-
-	/* Calculate CRC */
-	for (i = 0; i < len; i++)
-		crc = update_crc(crc, (char)cmd_info[i]);
-
-	/* Insert CRC */
-	cmd_info[len++] = MSB(crc);
-	cmd_info[len++] = LSB(crc);
-
-	/* Return total command length */
-	*cmd_len = len;
-}
-
-/*----------------------------------------------------------------------------
- * Function:	cmd_create_exec
- *
- * Parameters:	addr    - Memory address to execute from.
- *		cmd_info - Pointer to a command buffer.
- *		cmd_len  - Pointer to command length.
- * Returns:     none.
- * Side effects:
- * Description:
- *		Create an FCALL protocol command.
- *		The command buffer is enclosed by CRC, calculated on command
- *		information and raw data.
- *		The total command length is written to 'cmd_len'.
- *---------------------------------------------------------------------------
- */
-void cmd_create_exec(uint32_t addr, uint8_t *cmd_info, uint32_t *cmd_len)
-{
-	uint32_t i;
-	union cmd_addr adr_tr;
-	uint16_t crc = 0;
-	uint32_t len = 0;
-
-	/* Build the command buffer */
-	cmd_info[len++] = UFPP_FCALL_CMD;
-	cmd_info[len++] = 0;
-
-	/* Insert Address */
-	adr_tr.h_adr = addr;
-	cmd_info[len++] = adr_tr.c_adr[3];
-	cmd_info[len++] = adr_tr.c_adr[2];
-	cmd_info[len++] = adr_tr.c_adr[1];
-	cmd_info[len++] = adr_tr.c_adr[0];
-
-	/* Calculate CRC */
-	for (i = 0; i < len; i++)
-		crc = update_crc(crc, (char)cmd_info[i]);
-
-	/* Insert CRC */
-	cmd_info[len++] = MSB(crc);
-	cmd_info[len++] = LSB(crc);
-
-	/* Return total command length */
-	*cmd_len = len;
-}
-
-/*---------------------------------------------------------------------------
- * Function:        cmd_build_sync
- *
- * Parameters:	cmd_buf - Pointer to a command buffer.
- *		cmd_num - Pointer to command number.
- * Returns:	none.
- * Description:
- *		Build a synchronization command buffer.
- *		The total command number is written to 'cmd_num'.
- *---------------------------------------------------------------------------
- */
-void cmd_build_sync(struct command_node *cmd_buf, uint32_t *cmd_num)
-{
-	uint32_t cmd = 0;
-
-	cmd_create_sync(cmd_buf[cmd].cmd, &cmd_buf[cmd].cmd_size);
-	cmd_buf[cmd].resp_size = 1;
-	cmd++;
-
-	*cmd_num = cmd;
-}
-
-/*----------------------------------------------------------------------------
- * Function:	cmd_build_exec_exit
- *
- * Parameters:	addr   - Memory address to execute from.
- *		cmd_buf - Pointer to a command buffer.
- *		cmd_num - Pointer to command number.
- * Returns:	none.
- * Side effects:
- * Description:
- *		Build an Excute command buffer.
- *		Command does not expect the executed code to return, that is,
- *		only FCALL protocol
- *		command code is expected.
- *		Determine the expected response size per each command.
- *		The total command number is written to 'cmd_num'.
- *---------------------------------------------------------------------------
- */
-void cmd_build_exec_exit(uint32_t addr, struct command_node *cmd_buf,
-						uint32_t *cmd_num)
-{
-	uint32_t cmd = 0;
-
-	cmd_create_exec(addr, cmd_buf[cmd].cmd, &cmd_buf[cmd].cmd_size);
-	cmd_buf[cmd].resp_size = 1;
-	cmd++;
-
-	*cmd_num = cmd;
-}
-
-/*----------------------------------------------------------------------------
- * Function:	cmd_build_exec_ret
- *
- * Parameters:	addr   - Memory address to execute from.
- *		cmd_buf - Pointer to a command buffer.
- *		cmd_num - Pointer to command number.
- * Returns:	none.
- * Side effects:
- * Description:
- *		Build an Excute command buffer.
- *		Command expects the executed code to return, that is,
- *		FCALL_RSLT protocol command
- *		code is expected, together with the execution result.
- *		Determine the expected response size per each command.
- *		The total command number is written to 'cmd_num'.
- *---------------------------------------------------------------------------
- */
-void cmd_build_exec_ret(uint32_t addr, struct command_node *cmd_buf,
-						uint32_t *cmd_num)
-{
-	uint32_t cmd = 0;
-
-	cmd_create_exec(addr, cmd_buf[cmd].cmd, &cmd_buf[cmd].cmd_size);
-	cmd_buf[cmd].resp_size = 3;
-	cmd++;
-
-	*cmd_num = cmd;
-}
-
-/*----------------------------------------------------------------------------
- * Function:	cmd_disp_sync
- *
- * Parameters:	resp_buf - Pointer to a response buffer.
- * Returns:	TRUE if successful, FALSE in the case of an error.
- * Side effects:
- * Description:
- *		Display SYNC command response information.
- *---------------------------------------------------------------------------
- */
-bool cmd_disp_sync(uint8_t *resp_buf)
-{
-	if (resp_buf[0] == (uint8_t)(UFPP_D2H_SYNC_CMD)) {
-		display_color_msg(SUCCESS, "Host/Device are synchronized\n");
-		return true;
-	}
-
-	display_color_msg(FAIL, "Host/Device synchronization failed!!!\n");
-	return false;
-}
-
-/*----------------------------------------------------------------------------
- * Function:	cmd_disp_write
- *
- * Parameters:	resp_buf - Pointer to a response buffer.
- *		resp_size - Response size.
- *		resp_num - Response packet number.
- * Returns:	TRUE if successful, FALSE in the case of an error.
- * Side effects:
- * Description:
- *		Display WRITE command response information.
- *---------------------------------------------------------------------------
- */
-bool cmd_disp_write(uint8_t *resp_buf, uint32_t resp_size, uint32_t resp_num,
-					  uint32_t total_size)
-{
-	if (resp_buf[0] == (uint8_t)(UFPP_WRITE_CMD)) {
-		display_color_msg(SUCCESS,
-			"\rTransmitted packet of size %u bytes, packet "
-			"[%u]out of [%u]",
-			resp_size, resp_num, total_size);
-		return true;
-	}
-
-	display_color_msg(FAIL, "\nWrite packet [%lu] Failed\n", resp_num);
-	return false;
-}
-
-/*-----------------------------------------------------------------------------
- * Function:	cmd_disp_read
- *
- * Parameters:	resp_buf  - Pointer to a response buffer.
- *		resp_size - Response size.
- *		resp_num  - Response packet number.
- * Returns:	TRUE if successful, FALSE in the case of an error.
- * Side effects:
- * Description:
- *		Display READ command response information.
- *---------------------------------------------------------------------------
- */
-bool cmd_disp_read(uint8_t *resp_buf, uint32_t resp_size, uint32_t resp_num,
-					uint32_t total_size)
-{
-	if (resp_buf[0] == (uint8_t)(UFPP_READ_CMD)) {
-		display_color_msg(SUCCESS,
-			"\rReceived packet of size %u bytes, packet [%u] out "
-			"of [%u]",
-			resp_size, resp_num, total_size);
-		return true;
-	}
-
-	display_color_msg(FAIL, "\nRead packet [%u] Failed\n", resp_num);
-	return false;
-}
-
-/*----------------------------------------------------------------------------
- * Function:	cmd_disp_data
- *
- * Parameters:	resp_buf  - Pointer to a response buffer.
- *		resp_size - Response size.
- * Returns:	none.
- * Side effects:
- * Description:
- *		Display raw data, read from memory.
- *---------------------------------------------------------------------------
- */
-void cmd_disp_data(uint8_t *resp_buf, uint32_t resp_size)
-{
-	uint32_t idx;
-	uint32_t i;
-
-	for (idx = 0; idx < resp_size; idx += 4) {
-		if ((idx % 16) == 0)
-			printf("\n");
-
-		printf("0x");
-		for (i = 4; i > 0; i--)
-			printf("%02x", resp_buf[idx + i - 1]);
-
-		if ((idx % 4) == 0)
-			printf(" ");
-	}
-
-	printf("\n");
-}
-
-/*----------------------------------------------------------------------------
- * Function:	cmd_disp_flash_erase_dev
- *
- * Parameters:	resp_buf - Pointer to a response buffer.
- *		dev_num  - Flash Device Number.
- * Returns:	none.
- * Side effects:
- * Description:
- *		Display BULK_ERASE command response information.
- *---------------------------------------------------------------------------
- */
-void cmd_disp_flash_erase_dev(uint8_t *resp_buf, uint32_t dev_num)
-{
-	if (resp_buf[0] == (uint8_t)(UFPP_WRITE_CMD)) {
-		display_color_msg(SUCCESS,
-			"Flash Erase of device [%u] Passed\n", dev_num);
-	} else {
-		display_color_msg(
-			FAIL, "Flash Erase of device [%u] Failed\n", dev_num);
-	}
-}
-
-/*---------------------------------------------------------------------------
- * Function:	cmd_disp_flash_erase_sect
- *
- * Parameters:	resp_buf - Pointer to a response buffer.
- * Returns:	none.
- * Side effects:
- * Description:
- *		Display BULK_ERASE command response information.
- *---------------------------------------------------------------------------
- */
-void cmd_disp_flash_erase_sect(uint8_t *resp_buf, uint32_t dev_num)
-{
-	if (resp_buf[0] == (uint8_t)(UFPP_WRITE_CMD)) {
-		display_color_msg(SUCCESS,
-			"Sector Erase of device [%lu] Passed\n", dev_num);
-	} else {
-		display_color_msg(
-			FAIL, "Sector Erase of device [%lu] Failed\n", dev_num);
-	}
-}
-
-/*---------------------------------------------------------------------------
- * Function:	cmd_disp_exec_exit
- *
- * Parameters:	resp_buf - Pointer to a response buffer.
- * Returns:	none.
- * Side effects:
- * Description:
- *		Display Execute command response information.
- *---------------------------------------------------------------------------
- */
-void cmd_disp_exec_exit(uint8_t *resp_buf)
-{
-	if (resp_buf[0] == (uint8_t)(UFPP_FCALL_CMD))
-		display_color_msg(SUCCESS, "Execute Command Passed\n");
-	else
-		display_color_msg(FAIL, "Execute Command Failed\n");
-}
-
-/*---------------------------------------------------------------------------
- * Function:	cmd_disp_exec_ret
- *
- * Parameters:	resp_buf - Pointer to a response buffer.
- * Returns:	none.
- * Side effects:
- * Description:
- *		Display Execute Result command response information.
- *---------------------------------------------------------------------------
- */
-void cmd_disp_exec_ret(uint8_t *resp_buf)
-{
-	if (resp_buf[1] == (uint8_t)(UFPP_FCALL_RSLT_CMD)) {
-		display_color_msg(SUCCESS,
-			"Execute Command Passed, execution result is [0x%X]\n",
-			resp_buf[2]);
-	} else {
-		display_color_msg(FAIL,
-			"Execute Command Failed  [0x%X]  [0x%X], rslt=[0x%X]\n",
-			resp_buf[0], resp_buf[1], resp_buf[2]);
-	}
-}
diff --git a/util/uut/cmd.cc b/util/uut/cmd.cc
new file mode 100644
index 0000000000..6a57cb7c75
--- /dev/null
+++ b/util/uut/cmd.cc
@@ -0,0 +1,488 @@
+/*
+ * Copyright 2018 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* This file creates the UART Program Protocol API commands. */
+
+#include "cmd.h"
+#include "lib_crc.h"
+#include "main.h"
+
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+
+/* Extracting Byte - 8 bit: MSB, LSB */
+#define MSB(u16) ((uint8_t)((uint16_t)(u16) >> 8))
+#define LSB(u16) ((uint8_t)(u16))
+
+/*----------------------------------------------------------------------------
+ *  SPI Flash commands
+ *---------------------------------------------------------------------------
+ */
+
+#define SPI_READ_JEDEC_ID_CMD 0x9F
+#define SPI_WRITE_ENABLE_CMD 0x06
+#define SPI_WRITE_DISABLE_CMD 0x04
+#define SPI_READ_STATUS_REG_CMD 0x05
+#define SPI_WRITE_STATUS_REG_CMD 0x01
+#define SPI_READ_DATA_CMD 0x03
+#define SPI_PAGE_PRGM_CMD 0x02
+#define SPI_SECTOR_ERASE_CMD 0xD8
+#define SPI_BULK_ERASE_CMD 0xC7
+#define SPI_READ_PID_CMD 0x90
+
+union cmd_addr {
+	uint8_t c_adr[4];
+	uint32_t h_adr;
+};
+
+/*----------------------------------------------------------------------------
+ * Function implementation
+ *---------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ * Function:	cmd_create_sync
+ *
+ * Parameters:	   cmd_info - Pointer to a command buffer.
+ *		   cmd_len  - Pointer to command length.
+ * Returns:	   none.
+ * Side effects:
+ * Description:
+ *		Create a Host to Device SYNC protocol command.
+ *		The total command length is written to 'cmd_len'.
+ *---------------------------------------------------------------------------
+ */
+void cmd_create_sync(uint8_t *cmd_info, uint32_t *cmd_len)
+{
+	uint32_t len = 0;
+
+	/* Build the command buffer */
+	cmd_info[len++] = UFPP_H2D_SYNC_CMD;
+
+	/* Return total command length */
+	*cmd_len = len;
+}
+
+/*---------------------------------------------------------------------------
+ * Function:       cmd_create_write
+ *
+ * Parameters:	addr    - Memory address to write to.
+ *		size    - Size of daya (in bytes) to write to memory.
+ *		data_buf - Pointer to data buffer containing raw data to write.
+ *		cmd_info - Pointer to a command buffer.
+ *		cmd_len  - Pointer to command length.
+ * Returns:     none.
+ * Side effects:
+ * Description:
+ *	Create a WRITE protocol command.
+ *	The command buffer is enclosed by CRC, calculated on command
+ *	information and raw data.
+ *	The total command length is written to 'cmd_len'.
+ *---------------------------------------------------------------------------
+ */
+void cmd_create_write(uint32_t addr, uint32_t size, uint8_t *data_buf,
+		      uint8_t *cmd_info, uint32_t *cmd_len)
+{
+	uint32_t i;
+	union cmd_addr adr_tr;
+	uint16_t crc = 0;
+	uint32_t len = 0;
+
+	/* Build the command buffer */
+	cmd_info[len++] = UFPP_WRITE_CMD;
+	cmd_info[len++] = (uint8_t)(size - 1);
+
+	/* Insert Address */
+	adr_tr.h_adr = addr;
+	cmd_info[len++] = adr_tr.c_adr[3];
+	cmd_info[len++] = adr_tr.c_adr[2];
+	cmd_info[len++] = adr_tr.c_adr[1];
+	cmd_info[len++] = adr_tr.c_adr[0];
+
+	/* Insert data */
+	memcpy(&cmd_info[len], data_buf, size);
+	len += size;
+
+	/* Calculate CRC */
+	for (i = 0; i < len; i++)
+		crc = update_crc(crc, (char)cmd_info[i]);
+
+	/* Insert CRC */
+	cmd_info[len++] = MSB(crc);
+	cmd_info[len++] = LSB(crc);
+
+	/* Return total command length */
+	*cmd_len = len;
+}
+
+/*----------------------------------------------------------------------------
+ * Function:	cmd_create_read
+ *
+ * Parameters:	addr    - Memory address to read from.
+ *		size    - Size of daya (in bytes) to read from memory.
+ *		cmd_info - Pointer to a command buffer.
+ *		cmd_len  - Pointer to command length.
+ * Returns:	none.
+ * Side effects:
+ * Description:
+ *		Create a READ protocol command.
+ *		The command buffer is enclosed by CRC, calculated on command
+ *		information and raw data.
+ *		The total command length is written to 'cmd_len'.
+ *---------------------------------------------------------------------------
+ */
+void cmd_create_read(uint32_t addr, uint8_t size, uint8_t *cmd_info,
+		     uint32_t *cmd_len)
+{
+	uint32_t i;
+	union cmd_addr adr_tr;
+	uint16_t crc = 0;
+	uint32_t len = 0;
+
+	/* Build the command buffer */
+	cmd_info[len++] = UFPP_READ_CMD;
+	cmd_info[len++] = (uint8_t)size;
+
+	/* Insert Address */
+	adr_tr.h_adr = addr;
+	cmd_info[len++] = adr_tr.c_adr[3];
+	cmd_info[len++] = adr_tr.c_adr[2];
+	cmd_info[len++] = adr_tr.c_adr[1];
+	cmd_info[len++] = adr_tr.c_adr[0];
+
+	/* Calculate CRC */
+	for (i = 0; i < len; i++)
+		crc = update_crc(crc, (char)cmd_info[i]);
+
+	/* Insert CRC */
+	cmd_info[len++] = MSB(crc);
+	cmd_info[len++] = LSB(crc);
+
+	/* Return total command length */
+	*cmd_len = len;
+}
+
+/*----------------------------------------------------------------------------
+ * Function:	cmd_create_exec
+ *
+ * Parameters:	addr    - Memory address to execute from.
+ *		cmd_info - Pointer to a command buffer.
+ *		cmd_len  - Pointer to command length.
+ * Returns:     none.
+ * Side effects:
+ * Description:
+ *		Create an FCALL protocol command.
+ *		The command buffer is enclosed by CRC, calculated on command
+ *		information and raw data.
+ *		The total command length is written to 'cmd_len'.
+ *---------------------------------------------------------------------------
+ */
+void cmd_create_exec(uint32_t addr, uint8_t *cmd_info, uint32_t *cmd_len)
+{
+	uint32_t i;
+	union cmd_addr adr_tr;
+	uint16_t crc = 0;
+	uint32_t len = 0;
+
+	/* Build the command buffer */
+	cmd_info[len++] = UFPP_FCALL_CMD;
+	cmd_info[len++] = 0;
+
+	/* Insert Address */
+	adr_tr.h_adr = addr;
+	cmd_info[len++] = adr_tr.c_adr[3];
+	cmd_info[len++] = adr_tr.c_adr[2];
+	cmd_info[len++] = adr_tr.c_adr[1];
+	cmd_info[len++] = adr_tr.c_adr[0];
+
+	/* Calculate CRC */
+	for (i = 0; i < len; i++)
+		crc = update_crc(crc, (char)cmd_info[i]);
+
+	/* Insert CRC */
+	cmd_info[len++] = MSB(crc);
+	cmd_info[len++] = LSB(crc);
+
+	/* Return total command length */
+	*cmd_len = len;
+}
+
+/*---------------------------------------------------------------------------
+ * Function:        cmd_build_sync
+ *
+ * Parameters:	cmd_buf - Pointer to a command buffer.
+ *		cmd_num - Pointer to command number.
+ * Returns:	none.
+ * Description:
+ *		Build a synchronization command buffer.
+ *		The total command number is written to 'cmd_num'.
+ *---------------------------------------------------------------------------
+ */
+void cmd_build_sync(struct command_node *cmd_buf, uint32_t *cmd_num)
+{
+	uint32_t cmd = 0;
+
+	cmd_create_sync(cmd_buf[cmd].cmd, &cmd_buf[cmd].cmd_size);
+	cmd_buf[cmd].resp_size = 1;
+	cmd++;
+
+	*cmd_num = cmd;
+}
+
+/*----------------------------------------------------------------------------
+ * Function:	cmd_build_exec_exit
+ *
+ * Parameters:	addr   - Memory address to execute from.
+ *		cmd_buf - Pointer to a command buffer.
+ *		cmd_num - Pointer to command number.
+ * Returns:	none.
+ * Side effects:
+ * Description:
+ *		Build an Excute command buffer.
+ *		Command does not expect the executed code to return, that is,
+ *		only FCALL protocol
+ *		command code is expected.
+ *		Determine the expected response size per each command.
+ *		The total command number is written to 'cmd_num'.
+ *---------------------------------------------------------------------------
+ */
+void cmd_build_exec_exit(uint32_t addr, struct command_node *cmd_buf,
+			 uint32_t *cmd_num)
+{
+	uint32_t cmd = 0;
+
+	cmd_create_exec(addr, cmd_buf[cmd].cmd, &cmd_buf[cmd].cmd_size);
+	cmd_buf[cmd].resp_size = 1;
+	cmd++;
+
+	*cmd_num = cmd;
+}
+
+/*----------------------------------------------------------------------------
+ * Function:	cmd_build_exec_ret
+ *
+ * Parameters:	addr   - Memory address to execute from.
+ *		cmd_buf - Pointer to a command buffer.
+ *		cmd_num - Pointer to command number.
+ * Returns:	none.
+ * Side effects:
+ * Description:
+ *		Build an Excute command buffer.
+ *		Command expects the executed code to return, that is,
+ *		FCALL_RSLT protocol command
+ *		code is expected, together with the execution result.
+ *		Determine the expected response size per each command.
+ *		The total command number is written to 'cmd_num'.
+ *---------------------------------------------------------------------------
+ */
+void cmd_build_exec_ret(uint32_t addr, struct command_node *cmd_buf,
+			uint32_t *cmd_num)
+{
+	uint32_t cmd = 0;
+
+	cmd_create_exec(addr, cmd_buf[cmd].cmd, &cmd_buf[cmd].cmd_size);
+	cmd_buf[cmd].resp_size = 3;
+	cmd++;
+
+	*cmd_num = cmd;
+}
+
+/*----------------------------------------------------------------------------
+ * Function:	cmd_disp_sync
+ *
+ * Parameters:	resp_buf - Pointer to a response buffer.
+ * Returns:	TRUE if successful, FALSE in the case of an error.
+ * Side effects:
+ * Description:
+ *		Display SYNC command response information.
+ *---------------------------------------------------------------------------
+ */
+bool cmd_disp_sync(uint8_t *resp_buf)
+{
+	if (resp_buf[0] == (uint8_t)(UFPP_D2H_SYNC_CMD)) {
+		display_color_msg(SUCCESS, "Host/Device are synchronized\n");
+		return true;
+	}
+
+	display_color_msg(FAIL, "Host/Device synchronization failed!!!\n");
+	return false;
+}
+
+/*----------------------------------------------------------------------------
+ * Function:	cmd_disp_write
+ *
+ * Parameters:	resp_buf - Pointer to a response buffer.
+ *		resp_size - Response size.
+ *		resp_num - Response packet number.
+ * Returns:	TRUE if successful, FALSE in the case of an error.
+ * Side effects:
+ * Description:
+ *		Display WRITE command response information.
+ *---------------------------------------------------------------------------
+ */
+bool cmd_disp_write(uint8_t *resp_buf, uint32_t resp_size, uint32_t resp_num,
+		    uint32_t total_size)
+{
+	if (resp_buf[0] == (uint8_t)(UFPP_WRITE_CMD)) {
+		display_color_msg(
+			SUCCESS,
+			"\rTransmitted packet of size %u bytes, packet "
+			"[%u]out of [%u]",
+			resp_size, resp_num, total_size);
+		return true;
+	}
+
+	display_color_msg(FAIL, "\nWrite packet [%lu] Failed\n", resp_num);
+	return false;
+}
+
+/*-----------------------------------------------------------------------------
+ * Function:	cmd_disp_read
+ *
+ * Parameters:	resp_buf  - Pointer to a response buffer.
+ *		resp_size - Response size.
+ *		resp_num  - Response packet number.
+ * Returns:	TRUE if successful, FALSE in the case of an error.
+ * Side effects:
+ * Description:
+ *		Display READ command response information.
+ *---------------------------------------------------------------------------
+ */
+bool cmd_disp_read(uint8_t *resp_buf, uint32_t resp_size, uint32_t resp_num,
+		   uint32_t total_size)
+{
+	if (resp_buf[0] == (uint8_t)(UFPP_READ_CMD)) {
+		display_color_msg(
+			SUCCESS,
+			"\rReceived packet of size %u bytes, packet [%u] out "
+			"of [%u]",
+			resp_size, resp_num, total_size);
+		return true;
+	}
+
+	display_color_msg(FAIL, "\nRead packet [%u] Failed\n", resp_num);
+	return false;
+}
+
+/*----------------------------------------------------------------------------
+ * Function:	cmd_disp_data
+ *
+ * Parameters:	resp_buf  - Pointer to a response buffer.
+ *		resp_size - Response size.
+ * Returns:	none.
+ * Side effects:
+ * Description:
+ *		Display raw data, read from memory.
+ *---------------------------------------------------------------------------
+ */
+void cmd_disp_data(uint8_t *resp_buf, uint32_t resp_size)
+{
+	uint32_t idx;
+	uint32_t i;
+
+	for (idx = 0; idx < resp_size; idx += 4) {
+		if ((idx % 16) == 0)
+			printf("\n");
+
+		printf("0x");
+		for (i = 4; i > 0; i--)
+			printf("%02x", resp_buf[idx + i - 1]);
+
+		if ((idx % 4) == 0)
+			printf(" ");
+	}
+
+	printf("\n");
+}
+
+/*----------------------------------------------------------------------------
+ * Function:	cmd_disp_flash_erase_dev
+ *
+ * Parameters:	resp_buf - Pointer to a response buffer.
+ *		dev_num  - Flash Device Number.
+ * Returns:	none.
+ * Side effects:
+ * Description:
+ *		Display BULK_ERASE command response information.
+ *---------------------------------------------------------------------------
+ */
+void cmd_disp_flash_erase_dev(uint8_t *resp_buf, uint32_t dev_num)
+{
+	if (resp_buf[0] == (uint8_t)(UFPP_WRITE_CMD)) {
+		display_color_msg(SUCCESS,
+				  "Flash Erase of device [%u] Passed\n",
+				  dev_num);
+	} else {
+		display_color_msg(FAIL, "Flash Erase of device [%u] Failed\n",
+				  dev_num);
+	}
+}
+
+/*---------------------------------------------------------------------------
+ * Function:	cmd_disp_flash_erase_sect
+ *
+ * Parameters:	resp_buf - Pointer to a response buffer.
+ * Returns:	none.
+ * Side effects:
+ * Description:
+ *		Display BULK_ERASE command response information.
+ *---------------------------------------------------------------------------
+ */
+void cmd_disp_flash_erase_sect(uint8_t *resp_buf, uint32_t dev_num)
+{
+	if (resp_buf[0] == (uint8_t)(UFPP_WRITE_CMD)) {
+		display_color_msg(SUCCESS,
+				  "Sector Erase of device [%lu] Passed\n",
+				  dev_num);
+	} else {
+		display_color_msg(FAIL, "Sector Erase of device [%lu] Failed\n",
+				  dev_num);
+	}
+}
+
+/*---------------------------------------------------------------------------
+ * Function:	cmd_disp_exec_exit
+ *
+ * Parameters:	resp_buf - Pointer to a response buffer.
+ * Returns:	none.
+ * Side effects:
+ * Description:
+ *		Display Execute command response information.
+ *---------------------------------------------------------------------------
+ */
+void cmd_disp_exec_exit(uint8_t *resp_buf)
+{
+	if (resp_buf[0] == (uint8_t)(UFPP_FCALL_CMD))
+		display_color_msg(SUCCESS, "Execute Command Passed\n");
+	else
+		display_color_msg(FAIL, "Execute Command Failed\n");
+}
+
+/*---------------------------------------------------------------------------
+ * Function:	cmd_disp_exec_ret
+ *
+ * Parameters:	resp_buf - Pointer to a response buffer.
+ * Returns:	none.
+ * Side effects:
+ * Description:
+ *		Display Execute Result command response information.
+ *---------------------------------------------------------------------------
+ */
+void cmd_disp_exec_ret(uint8_t *resp_buf)
+{
+	if (resp_buf[1] == (uint8_t)(UFPP_FCALL_RSLT_CMD)) {
+		display_color_msg(
+			SUCCESS,
+			"Execute Command Passed, execution result is [0x%X]\n",
+			resp_buf[2]);
+	} else {
+		display_color_msg(
+			FAIL,
+			"Execute Command Failed  [0x%X]  [0x%X], rslt=[0x%X]\n",
+			resp_buf[0], resp_buf[1], resp_buf[2]);
+	}
+}
diff --git a/util/uut/cmd.h b/util/uut/cmd.h
index 44cebbe989..1ec6b07aef 100644
--- a/util/uut/cmd.h
+++ b/util/uut/cmd.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,6 +8,7 @@
 #define __UTIL_UUT_CMD_H
 
 #include <stdbool.h>
+#include <stdint.h>
 
 /*---------------------------------------------------------------------------
  * Constant definitions
@@ -18,17 +19,17 @@
 #define MAX_RESP_BUF_SIZE 512
 
 enum uart_protocol_cmd {
-	UFPP_H2D_SYNC_CMD = 0x55,   /* Single-Byte Host to Device	 */
-				    /* synchronization command	 */
-	UFPP_D2H_SYNC_CMD = 0x5A,   /* Single-Byte Device to Host	 */
-				    /* synchronization response	 */
-	UFPP_WRITE_CMD = 0x07,      /* Write command and response	 */
-	UFPP_READ_CMD = 0x1C,       /* Read command and response	 */
-	UFPP_READ_CRC_CMD = 0x89,   /* Read CRC command and response */
-	UFPP_FCALL_CMD = 0x70,      /* Call function command	 */
+	UFPP_H2D_SYNC_CMD = 0x55, /* Single-Byte Host to Device	 */
+	/* synchronization command	 */
+	UFPP_D2H_SYNC_CMD = 0x5A, /* Single-Byte Device to Host	 */
+	/* synchronization response	 */
+	UFPP_WRITE_CMD = 0x07, /* Write command and response	 */
+	UFPP_READ_CMD = 0x1C, /* Read command and response	 */
+	UFPP_READ_CRC_CMD = 0x89, /* Read CRC command and response */
+	UFPP_FCALL_CMD = 0x70, /* Call function command	 */
 	UFPP_FCALL_RSLT_CMD = 0x73, /* Call function response	 */
-	UFPP_SPI_CMD = 0x92,        /* SPI specific command		 */
-	UFPP_ERROR_CMD = 0xFF       /* Error response		 */
+	UFPP_SPI_CMD = 0x92, /* SPI specific command		 */
+	UFPP_ERROR_CMD = 0xFF /* Error response		 */
 };
 
 struct command_node {
@@ -44,22 +45,22 @@ struct command_node {
 
 void cmd_create_sync(uint8_t *cmd_info, uint32_t *cmd_len);
 void cmd_create_write(uint32_t addr, uint32_t size, uint8_t *data_buf,
-					uint8_t *cmd_info, uint32_t *cmd_len);
+		      uint8_t *cmd_info, uint32_t *cmd_len);
 void cmd_create_read(uint32_t addr, uint8_t size, uint8_t *cmd_info,
-					uint32_t *cmd_len);
+		     uint32_t *cmd_len);
 void cmd_create_exec(uint32_t addr, uint8_t *cmd_info, uint32_t *cmd_len);
 
 void cmd_build_sync(struct command_node *cmd_buf, uint32_t *cmd_num);
 void cmd_build_exec_exit(uint32_t addr, struct command_node *cmd_buf,
-						uint32_t *cmd_num);
+			 uint32_t *cmd_num);
 void cmd_build_exec_ret(uint32_t addr, struct command_node *cmd_buf,
-						uint32_t *cmd_num);
+			uint32_t *cmd_num);
 
 bool cmd_disp_sync(uint8_t *resp_buf);
 bool cmd_disp_write(uint8_t *resp_buf, uint32_t resp_size, uint32_t resp_num,
-					uint32_t total_size);
+		    uint32_t total_size);
 bool cmd_disp_read(uint8_t *resp_buf, uint32_t resp_size, uint32_t resp_num,
-					uint32_t total_size);
+		   uint32_t total_size);
 void cmd_disp_data(uint8_t *resp_buf, uint32_t resp_size);
 void cmd_disp_flash_erase_dev(uint8_t *resp_buf, uint32_t dev_num);
 void cmd_disp_flash_erase_sect(uint8_t *resp_buf, uint32_t dev_num);
diff --git a/util/uut/com_port.h b/util/uut/com_port.h
index 36331f2fb6..76ff9e9e16 100644
--- a/util/uut/com_port.h
+++ b/util/uut/com_port.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,6 +10,8 @@
 #define __UTIL_UUT_COM_PORT_H
 
 #include <stdbool.h>
+#include <stdint.h>
+
 #include <termios.h>
 
 #ifdef __cplusplus
@@ -35,10 +37,10 @@ extern "C" {
 #define COMP_PORT_PREFIX_3 "pts"
 
 struct comport_fields {
-	uint32_t baudrate;    /* Baudrate at which running               */
-	tcflag_t byte_size;   /* Number of bits/byte, 4-8                */
-	tcflag_t parity;       /* 0-4=None,Odd,Even,Mark,Space            */
-	uint8_t stop_bits;    /* 0,1,2 = 1, 1.5, 2                       */
+	uint32_t baudrate; /* Baudrate at which running               */
+	tcflag_t byte_size; /* Number of bits/byte, 4-8                */
+	tcflag_t parity; /* 0-4=None,Odd,Even,Mark,Space            */
+	uint8_t stop_bits; /* 0,1,2 = 1, 1.5, 2                       */
 	uint8_t flow_control; /* 0-none, 1-SwFlowControl,2-HwFlowControl */
 };
 
@@ -60,7 +62,7 @@ struct comport_fields {
  *---------------------------------------------------------------------------
  */
 int com_port_open(const char *com_port_dev_name,
-				struct comport_fields com_port_fields);
+		  struct comport_fields com_port_fields);
 
 /*---------------------------------------------------------------------------
  * Function: int com_config_uart()
@@ -110,7 +112,7 @@ bool com_port_close(int device_id);
  *---------------------------------------------------------------------------
  */
 bool com_port_write_bin(int device_id, const uint8_t *buffer,
-						uint32_t buf_size);
+			uint32_t buf_size);
 
 /*---------------------------------------------------------------------------
  * Function: uint32_t com_port_read_bin()
diff --git a/util/uut/l_com_port.c b/util/uut/l_com_port.c
deleted file mode 100644
index 018dec9950..0000000000
--- a/util/uut/l_com_port.c
+++ /dev/null
@@ -1,446 +0,0 @@
-/*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <errno.h>
-#include <fcntl.h>
-#include <poll.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <string.h>
-#include <sys/ioctl.h>
-#include <termios.h>
-#include <unistd.h>
-
-#include "com_port.h"
-#include "main.h"
-
-/*---------------------------------------------------------------------------
- * Constant definitions
- *---------------------------------------------------------------------------
- */
-
-#define INBUFSIZE 2048
-#define OUTBUFSIZE 2048
-#define LOWER_THRESHOLD 16
-#define UPPER_THRESHOLD 512
-#define XOFF_CHAR 0x13
-#define XON_CHAR 0x11
-
-#define UART_FIFO_SIZE 16
-
-#define COMMAND_TIMEOUT 10000 /* 10 seconds */
-
-/*---------------------------------------------------------------------------
- * Global variables
- *---------------------------------------------------------------------------
- */
-static struct termios savetty;
-
-/*---------------------------------------------------------------------------
- * Functions prototypes
- *---------------------------------------------------------------------------
- */
-
-/*--------------------------------------------------------------------------
- * Local Function implementation
- *--------------------------------------------------------------------------
- */
-
-/*--------------------------------------------------------------------------
- * Function:	convert_baudrate_to_baudrate_mask
- *
- * Parameters:
- *		baudrate - Bauderate value.
- *
- * Returns:	Baudrate mask.
- * Side effects:
- * Description:
- *		This routine convert from baudrate mode to paudrate mask.
- *--------------------------------------------------------------------------
- */
-static speed_t convert_baudrate_to_baudrate_mask(uint32_t baudrate)
-{
-	switch (baudrate) {
-	case 9600:
-		return B9600;
-	case 19200:
-		return B19200;
-	case 38400:
-		return B38400;
-	case 57600:
-		return B57600;
-	case 115200:
-		return B115200;
-	default:
-		return B0;
-	}
-}
-
-/*-------------------------------------------------------------------------
- * Function:	set_read_blocking
- *
- * Parameters:
- *		dev_drv	- The opened handle returned by com_port_open()
- *		block		- TRUE means read in blocking mode
- *				  FALSE means read in non-blocking mode.
- *
- * Returns:	none
- * Side effects:
- * Description:
- *		This routine set/unset read blocking mode.
- *--------------------------------------------------------------------------
- */
-void set_read_blocking(int dev_drv, bool block)
-{
-	struct termios tty;
-
-	memset(&tty, 0, sizeof(tty));
-
-	if (tcgetattr(dev_drv, &tty) != 0) {
-		display_color_msg(FAIL,
-			"set_read_blocking Error: %d Fail to get attribute "
-			"from Device number %d.\n",
-			errno, dev_drv);
-		return;
-	}
-
-	tty.c_cc[VMIN] = block;
-	tty.c_cc[VTIME] = 5; /* 0.5 seconds read timeout */
-
-	if (tcsetattr(dev_drv, TCSANOW, &tty) != 0) {
-		display_color_msg(FAIL,
-			"set_read_blocking Error: %d Fail to set attribute to "
-			"Device number %d.\n",
-			errno, dev_drv);
-	}
-}
-
-/*--------------------------------------------------------------------------
- * Global Function implementation
- *--------------------------------------------------------------------------
- */
-
-/******************************************************************************
- * Function: int com_config_uart()
- *
- * Purpose:  Configures the Uart port properties.
- *
- * Params:   h_dev_drv - the opened handle returned by com_port_open()
- *	    com_port_fields  - a struct filled with Comport settings, see
- *			     definition above.
- *
- * Returns:  1 if successful
- *	    0 in the case of an error.
- *
- *****************************************************************************
- */
-bool com_config_uart(int h_dev_drv, struct comport_fields com_port_fields)
-{
-	struct termios tty;
-	speed_t baudrate;
-
-	memset(&tty, 0, sizeof(tty));
-
-	if (tcgetattr(h_dev_drv, &tty) != 0) {
-		display_color_msg(FAIL,
-			"com_config_uart Error: Fail to get attribute from "
-			"Device number %d.\n",
-			h_dev_drv);
-		return false;
-	}
-
-	baudrate = convert_baudrate_to_baudrate_mask(com_port_fields.baudrate);
-	cfsetospeed(&tty, baudrate);
-	cfsetispeed(&tty, baudrate);
-
-	tty.c_cflag |= baudrate;
-
-	tty.c_cflag |= com_port_fields.byte_size;
-
-	/*
-	 * disable IGNBRK for mismatched speed tests; otherwise receive break
-	 * as \000 chars
-	 */
-
-	/* Set port to be in a "raw" mode. */
-	tty.c_iflag &= ~(IGNBRK | BRKINT | PARMRK | ISTRIP | INLCR | IGNCR |
-			 ICRNL | IXON);
-	tty.c_lflag &= ~(ECHO | ECHONL | ICANON | ISIG | IEXTEN);
-
-	tty.c_oflag = ~OPOST;
-	tty.c_cc[VMIN] = 0;  /* read doesn't block		*/
-	tty.c_cc[VTIME] = 5; /* 0.5 seconds read timeout	*/
-
-	tty.c_iflag |= (com_port_fields.flow_control == 0x01)
-			       ? (IXON | IXOFF)
-			       : 0x00; /* xon/xoff ctrl */
-
-	tty.c_cflag |= (CLOCAL | CREAD); /* ignore modem controls */
-	/* enable reading */
-	tty.c_cflag &= ~(PARENB | PARODD); /* shut off parity */
-	tty.c_cflag |= com_port_fields.parity;
-	/* Stop bits */
-	tty.c_cflag |= (com_port_fields.stop_bits == 0x02) ? CSTOPB : 0x00;
-	/* HW flow control */
-	tty.c_cflag |= (com_port_fields.flow_control == 0x02) ? CRTSCTS : 0x00;
-
-	/* Flush Port, then applies attributes */
-	tcflush(h_dev_drv, TCIFLUSH);
-
-	if (tcsetattr(h_dev_drv, TCSANOW, &tty) != 0) {
-		display_color_msg(FAIL,
-			"com_config_uart Error: %d setting port handle %d: %s.\n",
-			errno, h_dev_drv, strerror(errno));
-		return false;
-	}
-
-	return true;
-}
-
-/**
- * Drain the console RX buffer before programming. The device should be in
- * programming mode and shouldn't be printing anything. Anything that's
- * currently in the buffer could interfere with programming. discard_input
- * will discard everything currently in the buffer. It prints any non zero
- * characters and returns when the console is empty and ready for programming.
- *
- * This is the same as discard_input in stm32mon.
- * TODO: create common library for initializing serial consoles.
- */
-static void discard_input(int fd)
-{
-	uint8_t buffer[64];
-	int res, i;
-	int count_of_zeros;
-
-	/* Keep track of discarded zeros */
-	count_of_zeros = 0;
-	do {
-		res = read(fd, buffer, sizeof(buffer));
-		if (res > 0) {
-
-			/* Discard zeros in the beginning of the buffer. */
-			for (i = 0; i < res; i++)
-				if (buffer[i])
-					break;
-
-			count_of_zeros += i;
-			if (i == res) {
-				/* Only zeros, nothing to print out. */
-				continue;
-			}
-
-			/* Discard zeros in the end of the buffer. */
-			while (!buffer[res - 1]) {
-				count_of_zeros++;
-				res--;
-			}
-
-			printf("Recv[%d]:", res - i);
-			for (; i < res; i++)
-				printf("%02x ", buffer[i]);
-			printf("\n");
-		}
-	} while (res > 0);
-
-	if (count_of_zeros)
-		printf("%d zeros ignored\n", count_of_zeros);
-}
-
-
-/******************************************************************************
- * Function: int com_port_open()
- *
- * Purpose:  Open the specified ComPort device and return its handle.
- *
- * Params:   com_port_dev_name - The name of the device to open
- *           com_port_fields - a struct filled with Comport settings
- *
- * Returns:  INVALID_HANDLE_VALUE (-1) - invalid handle.
- *           Other value - Handle to be used in other Comport APIs
- *
- * Comments: The returned handle can be used for other Win32 API communication
- *           function.
- *
- *****************************************************************************
- */
-int com_port_open(const char *com_port_dev_name,
-				struct comport_fields com_port_fields)
-{
-	int port_handler;
-
-	port_handler = open(com_port_dev_name, O_RDWR | O_NOCTTY);
-
-	if (port_handler < 0) {
-		display_color_msg(FAIL,
-				"com_port_open Error %d opening %s: %s\n",
-				errno, com_port_dev_name, strerror(errno));
-		return INVALID_HANDLE_VALUE;
-	}
-
-	tcgetattr(port_handler, &savetty);
-
-	if (!com_config_uart(port_handler, com_port_fields)) {
-		display_color_msg(FAIL,
-			"com_port_open() Error %d, Failed on com_config_uart() %s, "
-			"%s\n",
-			errno, com_port_dev_name, strerror(errno));
-		close(port_handler);
-		return INVALID_HANDLE_VALUE;
-	}
-
-	/*
-	 * Drain the console, so what ever is already in the EC console wont
-	 * interfere with programming.
-	 */
-	discard_input(port_handler);
-
-	return port_handler;
-}
-
-/******************************************************************************
- * Function: com_port_close()
- *
- * Purpose:  Close the ComPort device specified by Handle
- *
- * Params:   device_id - the opened handle returned by com_port_open()
- *
- * Returns:  1 if successful
- *           0 in the case of an error.
- *
- *****************************************************************************
- */
-bool com_port_close(int device_id)
-{
-	tcsetattr(device_id, TCSANOW, &savetty);
-
-	if (close(device_id) == INVALID_HANDLE_VALUE) {
-		display_color_msg(FAIL,
-			"com_port_close() Error: %d Device com%u was not opened, "
-			"%s.\n",
-			errno, (uint32_t)device_id, strerror(errno));
-		return false;
-	}
-
-	return true;
-}
-
-/******************************************************************************
- * Function: com_port_write_bin()
- *
- * Purpose:  Send binary data through Comport
- *
- * Params:   device_id - the opened handle returned by com_port_open()
- *           buffer - contains the binary data to send
- *           buf_size - the size of data to send
- *
- * Returns:  1 if successful
- *           0 in the case of an error.
- *
- * Comments: The caller must ensure that buf_size is not bigger than
- *           buffer size.
- *
- *****************************************************************************
- */
-bool com_port_write_bin(int device_id, const uint8_t *buffer,
-						uint32_t buf_size)
-{
-	uint32_t bytes_written;
-
-	bytes_written = write(device_id, buffer, buf_size);
-	if (bytes_written != buf_size) {
-		display_color_msg(FAIL,
-			"com_port_write_bin() Error: %d  Failed to write data to "
-			"Uart Port %d, %s.\n",
-			errno, (uint32_t)device_id, strerror(errno));
-
-		return false;
-	}
-
-	return true;
-}
-
-/******************************************************************************
- * Function: uint32_t com_port_read_bin()
- *
- * Purpose:  Read a binary data from Comport
- *
- * Params:   device_id - the opened handle returned by com_port_open()
- *           buffer - this buffer will contain the arrived data
- *           buf_size - maximum data size to read
- *
- * Returns:  The number of bytes read.
- *
- * Comments: The caller must ensure that Size is not bigger than buffer size.
- *
- *****************************************************************************
- */
-uint32_t com_port_read_bin(int device_id, uint8_t *buffer, uint32_t buf_size)
-{
-	int32_t read_bytes;
-
-	/* Reset read blocking mode */
-	set_read_blocking(device_id, false);
-
-	read_bytes = read(device_id, buffer, buf_size);
-
-	if (read_bytes == -1) {
-		display_color_msg(FAIL,
-			"%s() Error: %d Device number %u was not "
-			"opened, %s.\n",
-			__func__, errno, (uint32_t)device_id, strerror(errno));
-	}
-
-	return read_bytes;
-}
-
-/******************************************************************************
- * Function: uint32_t com_port_wait_read()
- *
- * Purpose:  Wait until a byte is received for read
- *
- * Params:   device_id - the opened handle returned by com_port_open()
- *
- * Returns:  The number of bytes that are waiting in RX queue.
- *
- *****************************************************************************
- */
-uint32_t com_port_wait_read(int device_id)
-{
-	int32_t bytes;
-	int32_t ret_val;
-	struct pollfd fds;
-
-	/* Set read blocking mode */
-	set_read_blocking(device_id, true);
-
-	/* Wait up to 10 sec until byte is received for read. */
-	fds.fd = device_id;
-	fds.events = POLLIN;
-	ret_val = poll(&fds, 1, COMMAND_TIMEOUT);
-	if (ret_val < 0) {
-		display_color_msg(FAIL,
-			"%s() Error: %d Device number %u %s\n",
-			__func__, errno, (uint32_t)device_id, strerror(errno));
-		return 0;
-	}
-
-	bytes = 0;
-
-	/* If data is ready for read. */
-	if (ret_val > 0) {
-		/* Get number of bytes that are ready to be read. */
-		if (ioctl(device_id, FIONREAD, &bytes) < 0) {
-			display_color_msg(FAIL,
-				"com_port_wait_for_read() Error: %d Device number "
-				"%u %s\n",
-				errno, (uint32_t)device_id, strerror(errno));
-			return 0;
-		}
-	}
-
-	return bytes;
-}
diff --git a/util/uut/l_com_port.cc b/util/uut/l_com_port.cc
new file mode 100644
index 0000000000..2e280ff7e1
--- /dev/null
+++ b/util/uut/l_com_port.cc
@@ -0,0 +1,454 @@
+/*
+ * Copyright 2018 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "com_port.h"
+#include "main.h"
+
+#include <errno.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+
+#include <fcntl.h>
+#include <poll.h>
+#include <sys/ioctl.h>
+#include <termios.h>
+#include <unistd.h>
+
+/*---------------------------------------------------------------------------
+ * Constant definitions
+ *---------------------------------------------------------------------------
+ */
+
+#define INBUFSIZE 2048
+#define OUTBUFSIZE 2048
+#define LOWER_THRESHOLD 16
+#define UPPER_THRESHOLD 512
+#define XOFF_CHAR 0x13
+#define XON_CHAR 0x11
+
+#define UART_FIFO_SIZE 16
+
+#define COMMAND_TIMEOUT 10000 /* 10 seconds */
+
+/*---------------------------------------------------------------------------
+ * Global variables
+ *---------------------------------------------------------------------------
+ */
+static struct termios savetty;
+
+/*---------------------------------------------------------------------------
+ * Functions prototypes
+ *---------------------------------------------------------------------------
+ */
+
+/*--------------------------------------------------------------------------
+ * Local Function implementation
+ *--------------------------------------------------------------------------
+ */
+
+/*--------------------------------------------------------------------------
+ * Function:	convert_baudrate_to_baudrate_mask
+ *
+ * Parameters:
+ *		baudrate - Bauderate value.
+ *
+ * Returns:	Baudrate mask.
+ * Side effects:
+ * Description:
+ *		This routine convert from baudrate mode to paudrate mask.
+ *--------------------------------------------------------------------------
+ */
+static speed_t convert_baudrate_to_baudrate_mask(uint32_t baudrate)
+{
+	switch (baudrate) {
+	case 9600:
+		return B9600;
+	case 19200:
+		return B19200;
+	case 38400:
+		return B38400;
+	case 57600:
+		return B57600;
+	case 115200:
+		return B115200;
+	default:
+		return B0;
+	}
+}
+
+/*-------------------------------------------------------------------------
+ * Function:	set_read_blocking
+ *
+ * Parameters:
+ *		dev_drv	- The opened handle returned by com_port_open()
+ *		block		- TRUE means read in blocking mode
+ *				  FALSE means read in non-blocking mode.
+ *
+ * Returns:	none
+ * Side effects:
+ * Description:
+ *		This routine set/unset read blocking mode.
+ *--------------------------------------------------------------------------
+ */
+void set_read_blocking(int dev_drv, bool block)
+{
+	struct termios tty;
+
+	memset(&tty, 0, sizeof(tty));
+
+	if (tcgetattr(dev_drv, &tty) != 0) {
+		display_color_msg(
+			FAIL,
+			"set_read_blocking Error: %d Fail to get attribute "
+			"from Device number %d.\n",
+			errno, dev_drv);
+		return;
+	}
+
+	tty.c_cc[VMIN] = block;
+	tty.c_cc[VTIME] = 5; /* 0.5 seconds read timeout */
+
+	if (tcsetattr(dev_drv, TCSANOW, &tty) != 0) {
+		display_color_msg(
+			FAIL,
+			"set_read_blocking Error: %d Fail to set attribute to "
+			"Device number %d.\n",
+			errno, dev_drv);
+	}
+}
+
+/*--------------------------------------------------------------------------
+ * Global Function implementation
+ *--------------------------------------------------------------------------
+ */
+
+/******************************************************************************
+ * Function: int com_config_uart()
+ *
+ * Purpose:  Configures the Uart port properties.
+ *
+ * Params:   h_dev_drv - the opened handle returned by com_port_open()
+ *	    com_port_fields  - a struct filled with Comport settings, see
+ *			     definition above.
+ *
+ * Returns:  1 if successful
+ *	    0 in the case of an error.
+ *
+ *****************************************************************************
+ */
+bool com_config_uart(int h_dev_drv, struct comport_fields com_port_fields)
+{
+	struct termios tty;
+	speed_t baudrate;
+
+	memset(&tty, 0, sizeof(tty));
+
+	if (tcgetattr(h_dev_drv, &tty) != 0) {
+		display_color_msg(
+			FAIL,
+			"com_config_uart Error: Fail to get attribute from "
+			"Device number %d.\n",
+			h_dev_drv);
+		return false;
+	}
+
+	baudrate = convert_baudrate_to_baudrate_mask(com_port_fields.baudrate);
+	cfsetospeed(&tty, baudrate);
+	cfsetispeed(&tty, baudrate);
+
+	tty.c_cflag |= baudrate;
+
+	tty.c_cflag |= com_port_fields.byte_size;
+
+	/*
+	 * disable IGNBRK for mismatched speed tests; otherwise receive break
+	 * as \000 chars
+	 */
+
+	/* Set port to be in a "raw" mode. */
+	tty.c_iflag &= ~(IGNBRK | BRKINT | PARMRK | ISTRIP | INLCR | IGNCR |
+			 ICRNL | IXON);
+	tty.c_lflag &= ~(ECHO | ECHONL | ICANON | ISIG | IEXTEN);
+
+	tty.c_oflag = ~OPOST;
+	tty.c_cc[VMIN] = 0; /* read doesn't block		*/
+	tty.c_cc[VTIME] = 5; /* 0.5 seconds read timeout	*/
+
+	tty.c_iflag |= (com_port_fields.flow_control == 0x01) ?
+			       (IXON | IXOFF) :
+			       0x00; /* xon/xoff
+					ctrl */
+
+	tty.c_cflag |= (CLOCAL | CREAD); /* ignore modem controls */
+	/* enable reading */
+	tty.c_cflag &= ~(PARENB | PARODD); /* shut off parity */
+	tty.c_cflag |= com_port_fields.parity;
+	/* Stop bits */
+	tty.c_cflag |= (com_port_fields.stop_bits == 0x02) ? CSTOPB : 0x00;
+	/* HW flow control */
+	tty.c_cflag |= (com_port_fields.flow_control == 0x02) ? CRTSCTS : 0x00;
+
+	/* Flush Port, then applies attributes */
+	tcflush(h_dev_drv, TCIFLUSH);
+
+	if (tcsetattr(h_dev_drv, TCSANOW, &tty) != 0) {
+		display_color_msg(
+			FAIL,
+			"com_config_uart Error: %d setting port handle %d: %s.\n",
+			errno, h_dev_drv, strerror(errno));
+		return false;
+	}
+
+	return true;
+}
+
+/**
+ * Drain the console RX buffer before programming. The device should be in
+ * programming mode and shouldn't be printing anything. Anything that's
+ * currently in the buffer could interfere with programming. discard_input
+ * will discard everything currently in the buffer. It prints any non zero
+ * characters and returns when the console is empty and ready for programming.
+ *
+ * This is the same as discard_input in stm32mon.
+ * TODO: create common library for initializing serial consoles.
+ */
+static void discard_input(int fd)
+{
+	uint8_t buffer[64];
+	int res, i;
+	int count_of_zeros;
+
+	/* Keep track of discarded zeros */
+	count_of_zeros = 0;
+	do {
+		res = read(fd, buffer, sizeof(buffer));
+		if (res > 0) {
+			/* Discard zeros in the beginning of the buffer. */
+			for (i = 0; i < res; i++)
+				if (buffer[i])
+					break;
+
+			count_of_zeros += i;
+			if (i == res) {
+				/* Only zeros, nothing to print out. */
+				continue;
+			}
+
+			/* Discard zeros in the end of the buffer. */
+			while (!buffer[res - 1]) {
+				count_of_zeros++;
+				res--;
+			}
+
+			printf("Recv[%d]:", res - i);
+			for (; i < res; i++)
+				printf("%02x ", buffer[i]);
+			printf("\n");
+		}
+	} while (res > 0);
+
+	if (count_of_zeros)
+		printf("%d zeros ignored\n", count_of_zeros);
+}
+
+/******************************************************************************
+ * Function: int com_port_open()
+ *
+ * Purpose:  Open the specified ComPort device and return its handle.
+ *
+ * Params:   com_port_dev_name - The name of the device to open
+ *           com_port_fields - a struct filled with Comport settings
+ *
+ * Returns:  INVALID_HANDLE_VALUE (-1) - invalid handle.
+ *           Other value - Handle to be used in other Comport APIs
+ *
+ * Comments: The returned handle can be used for other Win32 API communication
+ *           function.
+ *
+ *****************************************************************************
+ */
+int com_port_open(const char *com_port_dev_name,
+		  struct comport_fields com_port_fields)
+{
+	int port_handler;
+
+	port_handler = open(com_port_dev_name, O_RDWR | O_NOCTTY);
+
+	if (port_handler < 0) {
+		display_color_msg(FAIL,
+				  "com_port_open Error %d opening %s: %s\n",
+				  errno, com_port_dev_name, strerror(errno));
+		return INVALID_HANDLE_VALUE;
+	}
+
+	tcgetattr(port_handler, &savetty);
+
+	if (!com_config_uart(port_handler, com_port_fields)) {
+		display_color_msg(
+			FAIL,
+			"com_port_open() Error %d, Failed on com_config_uart() %s, "
+			"%s\n",
+			errno, com_port_dev_name, strerror(errno));
+		close(port_handler);
+		return INVALID_HANDLE_VALUE;
+	}
+
+	/*
+	 * Drain the console, so what ever is already in the EC console wont
+	 * interfere with programming.
+	 */
+	discard_input(port_handler);
+
+	return port_handler;
+}
+
+/******************************************************************************
+ * Function: com_port_close()
+ *
+ * Purpose:  Close the ComPort device specified by Handle
+ *
+ * Params:   device_id - the opened handle returned by com_port_open()
+ *
+ * Returns:  1 if successful
+ *           0 in the case of an error.
+ *
+ *****************************************************************************
+ */
+bool com_port_close(int device_id)
+{
+	tcsetattr(device_id, TCSANOW, &savetty);
+
+	if (close(device_id) == INVALID_HANDLE_VALUE) {
+		display_color_msg(
+			FAIL,
+			"com_port_close() Error: %d Device com%u was not opened, "
+			"%s.\n",
+			errno, (uint32_t)device_id, strerror(errno));
+		return false;
+	}
+
+	return true;
+}
+
+/******************************************************************************
+ * Function: com_port_write_bin()
+ *
+ * Purpose:  Send binary data through Comport
+ *
+ * Params:   device_id - the opened handle returned by com_port_open()
+ *           buffer - contains the binary data to send
+ *           buf_size - the size of data to send
+ *
+ * Returns:  1 if successful
+ *           0 in the case of an error.
+ *
+ * Comments: The caller must ensure that buf_size is not bigger than
+ *           buffer size.
+ *
+ *****************************************************************************
+ */
+bool com_port_write_bin(int device_id, const uint8_t *buffer, uint32_t buf_size)
+{
+	uint32_t bytes_written;
+
+	bytes_written = write(device_id, buffer, buf_size);
+	if (bytes_written != buf_size) {
+		display_color_msg(
+			FAIL,
+			"com_port_write_bin() Error: %d  Failed to write data to "
+			"Uart Port %d, %s.\n",
+			errno, (uint32_t)device_id, strerror(errno));
+
+		return false;
+	}
+
+	return true;
+}
+
+/******************************************************************************
+ * Function: uint32_t com_port_read_bin()
+ *
+ * Purpose:  Read a binary data from Comport
+ *
+ * Params:   device_id - the opened handle returned by com_port_open()
+ *           buffer - this buffer will contain the arrived data
+ *           buf_size - maximum data size to read
+ *
+ * Returns:  The number of bytes read.
+ *
+ * Comments: The caller must ensure that Size is not bigger than buffer size.
+ *
+ *****************************************************************************
+ */
+uint32_t com_port_read_bin(int device_id, uint8_t *buffer, uint32_t buf_size)
+{
+	int32_t read_bytes;
+
+	/* Reset read blocking mode */
+	set_read_blocking(device_id, false);
+
+	read_bytes = read(device_id, buffer, buf_size);
+
+	if (read_bytes == -1) {
+		display_color_msg(FAIL,
+				  "%s() Error: %d Device number %u was not "
+				  "opened, %s.\n",
+				  __func__, errno, (uint32_t)device_id,
+				  strerror(errno));
+	}
+
+	return read_bytes;
+}
+
+/******************************************************************************
+ * Function: uint32_t com_port_wait_read()
+ *
+ * Purpose:  Wait until a byte is received for read
+ *
+ * Params:   device_id - the opened handle returned by com_port_open()
+ *
+ * Returns:  The number of bytes that are waiting in RX queue.
+ *
+ *****************************************************************************
+ */
+uint32_t com_port_wait_read(int device_id)
+{
+	int32_t bytes;
+	int32_t ret_val;
+	struct pollfd fds;
+
+	/* Set read blocking mode */
+	set_read_blocking(device_id, true);
+
+	/* Wait up to 10 sec until byte is received for read. */
+	fds.fd = device_id;
+	fds.events = POLLIN;
+	ret_val = poll(&fds, 1, COMMAND_TIMEOUT);
+	if (ret_val < 0) {
+		display_color_msg(FAIL, "%s() Error: %d Device number %u %s\n",
+				  __func__, errno, (uint32_t)device_id,
+				  strerror(errno));
+		return 0;
+	}
+
+	bytes = 0;
+
+	/* If data is ready for read. */
+	if (ret_val > 0) {
+		/* Get number of bytes that are ready to be read. */
+		if (ioctl(device_id, FIONREAD, &bytes) < 0) {
+			display_color_msg(
+				FAIL,
+				"com_port_wait_for_read() Error: %d Device number "
+				"%u %s\n",
+				errno, (uint32_t)device_id, strerror(errno));
+			return 0;
+		}
+	}
+
+	return bytes;
+}
diff --git a/util/uut/lib_crc.c b/util/uut/lib_crc.c
deleted file mode 100644
index 176e91327c..0000000000
--- a/util/uut/lib_crc.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * The file lib_crc.c contains the  functions used for the calculation of
- * CRC-16 cyclic redundancy values.
- */
-
-#include "lib_crc.h"
-
-/*********************************************************************
- *                                                                   *
- *   Library         : lib_crc                                       *
- *   File            : lib_crc.c                                     *
- *   Author          : Lammert Bies  1999-2005                       *
- *   E-mail          : info@lammertbies.nl                           *
- *   Language        : ANSI C                                        *
- *                                                                   *
- *                                                                   *
- *   Description                                                     *
- *   ===========                                                     *
- *                                                                   *
- *   The file lib_crc.c contains the private  and  public  func-     *
- *   tions  used  for  the  calculation of CRC-16, CRC-CCITT and     *
- *   CRC-32 cyclic redundancy values.                                *
- *                                                                   *
- *                                                                   *
- *   Dependencies                                                    *
- *   ============                                                    *
- *                                                                   *
- *   lib_crc.h       CRC definitions and prototypes                  *
- *                                                                   *
- *                                                                   *
- *   Modification history                                            *
- *   ====================                                            *
- *                                                                   *
- *   Date        Version Comment                                     *
- *                                                                   *
- *   2005-05-14  1.12    Added CRC-CCITT with start value 0          *
- *                                                                   *
- *   2005-02-05  1.11    Fixed bug in CRC-DNP routine                *
- *                                                                   *
- *   2005-02-04  1.10    Added CRC-DNP routines                      *
- *                                                                   *
- *   1999-02-21  1.01    Added FALSE and TRUE mnemonics              *
- *                                                                   *
- *   1999-01-22  1.00    Initial source                              *
- *                                                                   *
- *********************************************************************
- */
-
-/* CRC16 lookup table for polynom 0xA001 */
-static const unsigned short crc16_tab[256] = {
-	0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
-	0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
-	0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
-	0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
-	0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
-	0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
-	0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
-	0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
-	0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
-	0x3600, 0xF6C1, 0xF781, 0x3740, 0xF501, 0x35C0, 0x3480, 0xF441,
-	0x3C00, 0xFCC1, 0xFD81, 0x3D40, 0xFF01, 0x3FC0, 0x3E80, 0xFE41,
-	0xFA01, 0x3AC0, 0x3B80, 0xFB41, 0x3900, 0xF9C1, 0xF881, 0x3840,
-	0x2800, 0xE8C1, 0xE981, 0x2940, 0xEB01, 0x2BC0, 0x2A80, 0xEA41,
-	0xEE01, 0x2EC0, 0x2F80, 0xEF41, 0x2D00, 0xEDC1, 0xEC81, 0x2C40,
-	0xE401, 0x24C0, 0x2580, 0xE541, 0x2700, 0xE7C1, 0xE681, 0x2640,
-	0x2200, 0xE2C1, 0xE381, 0x2340, 0xE101, 0x21C0, 0x2080, 0xE041,
-	0xA001, 0x60C0, 0x6180, 0xA141, 0x6300, 0xA3C1, 0xA281, 0x6240,
-	0x6600, 0xA6C1, 0xA781, 0x6740, 0xA501, 0x65C0, 0x6480, 0xA441,
-	0x6C00, 0xACC1, 0xAD81, 0x6D40, 0xAF01, 0x6FC0, 0x6E80, 0xAE41,
-	0xAA01, 0x6AC0, 0x6B80, 0xAB41, 0x6900, 0xA9C1, 0xA881, 0x6840,
-	0x7800, 0xB8C1, 0xB981, 0x7940, 0xBB01, 0x7BC0, 0x7A80, 0xBA41,
-	0xBE01, 0x7EC0, 0x7F80, 0xBF41, 0x7D00, 0xBDC1, 0xBC81, 0x7C40,
-	0xB401, 0x74C0, 0x7580, 0xB541, 0x7700, 0xB7C1, 0xB681, 0x7640,
-	0x7200, 0xB2C1, 0xB381, 0x7340, 0xB101, 0x71C0, 0x7080, 0xB041,
-	0x5000, 0x90C1, 0x9181, 0x5140, 0x9301, 0x53C0, 0x5280, 0x9241,
-	0x9601, 0x56C0, 0x5780, 0x9741, 0x5500, 0x95C1, 0x9481, 0x5440,
-	0x9C01, 0x5CC0, 0x5D80, 0x9D41, 0x5F00, 0x9FC1, 0x9E81, 0x5E40,
-	0x5A00, 0x9AC1, 0x9B81, 0x5B40, 0x9901, 0x59C0, 0x5880, 0x9841,
-	0x8801, 0x48C0, 0x4980, 0x8941, 0x4B00, 0x8BC1, 0x8A81, 0x4A40,
-	0x4E00, 0x8EC1, 0x8F81, 0x4F40, 0x8D01, 0x4DC0, 0x4C80, 0x8C41,
-	0x4400, 0x84C1, 0x8581, 0x4540, 0x8701, 0x47C0, 0x4680, 0x8641,
-	0x8201, 0x42C0, 0x4380, 0x8341, 0x4100, 0x81C1, 0x8081, 0x4040
-};
-
-/*********************************************************************
- *                                                                   *
- *   unsigned short update_crc( unsigned long crc, unsigned char c ) *
- *                                                                   *
- *   The function update_crc calculates a  new  CRC-16  value        *
- *   based  on  the  previous value of the CRC and the next byte     *
- *   of the data to be checked.                                      *
- *                                                                   *
- *********************************************************************
- */
-unsigned short update_crc(unsigned short crc, unsigned char c)
-{
-	unsigned short tmp;
-
-	tmp = crc ^ (0x00ff & (unsigned short)c);
-	crc = (crc >> 8) ^ crc16_tab[tmp & 0xff];
-
-	return crc;
-}
diff --git a/util/uut/lib_crc.cc b/util/uut/lib_crc.cc
new file mode 100644
index 0000000000..ae83581063
--- /dev/null
+++ b/util/uut/lib_crc.cc
@@ -0,0 +1,106 @@
+/*
+ * Copyright 2018 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * The file lib_crc.c contains the  functions used for the calculation of
+ * CRC-16 cyclic redundancy values.
+ */
+
+#include "lib_crc.h"
+
+/*********************************************************************
+ *                                                                   *
+ *   Library         : lib_crc                                       *
+ *   File            : lib_crc.c                                     *
+ *   Author          : Lammert Bies  1999-2005                       *
+ *   E-mail          : info@lammertbies.nl                           *
+ *   Language        : ANSI C                                        *
+ *                                                                   *
+ *                                                                   *
+ *   Description                                                     *
+ *   ===========                                                     *
+ *                                                                   *
+ *   The file lib_crc.c contains the private  and  public  func-     *
+ *   tions  used  for  the  calculation of CRC-16, CRC-CCITT and     *
+ *   CRC-32 cyclic redundancy values.                                *
+ *                                                                   *
+ *                                                                   *
+ *   Dependencies                                                    *
+ *   ============                                                    *
+ *                                                                   *
+ *   lib_crc.h       CRC definitions and prototypes                  *
+ *                                                                   *
+ *                                                                   *
+ *   Modification history                                            *
+ *   ====================                                            *
+ *                                                                   *
+ *   Date        Version Comment                                     *
+ *                                                                   *
+ *   2005-05-14  1.12    Added CRC-CCITT with start value 0          *
+ *                                                                   *
+ *   2005-02-05  1.11    Fixed bug in CRC-DNP routine                *
+ *                                                                   *
+ *   2005-02-04  1.10    Added CRC-DNP routines                      *
+ *                                                                   *
+ *   1999-02-21  1.01    Added FALSE and TRUE mnemonics              *
+ *                                                                   *
+ *   1999-01-22  1.00    Initial source                              *
+ *                                                                   *
+ *********************************************************************
+ */
+
+/* CRC16 lookup table for polynom 0xA001 */
+static const unsigned short crc16_tab[256] = {
+	0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241, 0xC601,
+	0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440, 0xCC01, 0x0CC0,
+	0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40, 0x0A00, 0xCAC1, 0xCB81,
+	0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841, 0xD801, 0x18C0, 0x1980, 0xD941,
+	0x1B00, 0xDBC1, 0xDA81, 0x1A40, 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01,
+	0x1DC0, 0x1C80, 0xDC41, 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0,
+	0x1680, 0xD641, 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081,
+	0x1040, 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
+	0x3600, 0xF6C1, 0xF781, 0x3740, 0xF501, 0x35C0, 0x3480, 0xF441, 0x3C00,
+	0xFCC1, 0xFD81, 0x3D40, 0xFF01, 0x3FC0, 0x3E80, 0xFE41, 0xFA01, 0x3AC0,
+	0x3B80, 0xFB41, 0x3900, 0xF9C1, 0xF881, 0x3840, 0x2800, 0xE8C1, 0xE981,
+	0x2940, 0xEB01, 0x2BC0, 0x2A80, 0xEA41, 0xEE01, 0x2EC0, 0x2F80, 0xEF41,
+	0x2D00, 0xEDC1, 0xEC81, 0x2C40, 0xE401, 0x24C0, 0x2580, 0xE541, 0x2700,
+	0xE7C1, 0xE681, 0x2640, 0x2200, 0xE2C1, 0xE381, 0x2340, 0xE101, 0x21C0,
+	0x2080, 0xE041, 0xA001, 0x60C0, 0x6180, 0xA141, 0x6300, 0xA3C1, 0xA281,
+	0x6240, 0x6600, 0xA6C1, 0xA781, 0x6740, 0xA501, 0x65C0, 0x6480, 0xA441,
+	0x6C00, 0xACC1, 0xAD81, 0x6D40, 0xAF01, 0x6FC0, 0x6E80, 0xAE41, 0xAA01,
+	0x6AC0, 0x6B80, 0xAB41, 0x6900, 0xA9C1, 0xA881, 0x6840, 0x7800, 0xB8C1,
+	0xB981, 0x7940, 0xBB01, 0x7BC0, 0x7A80, 0xBA41, 0xBE01, 0x7EC0, 0x7F80,
+	0xBF41, 0x7D00, 0xBDC1, 0xBC81, 0x7C40, 0xB401, 0x74C0, 0x7580, 0xB541,
+	0x7700, 0xB7C1, 0xB681, 0x7640, 0x7200, 0xB2C1, 0xB381, 0x7340, 0xB101,
+	0x71C0, 0x7080, 0xB041, 0x5000, 0x90C1, 0x9181, 0x5140, 0x9301, 0x53C0,
+	0x5280, 0x9241, 0x9601, 0x56C0, 0x5780, 0x9741, 0x5500, 0x95C1, 0x9481,
+	0x5440, 0x9C01, 0x5CC0, 0x5D80, 0x9D41, 0x5F00, 0x9FC1, 0x9E81, 0x5E40,
+	0x5A00, 0x9AC1, 0x9B81, 0x5B40, 0x9901, 0x59C0, 0x5880, 0x9841, 0x8801,
+	0x48C0, 0x4980, 0x8941, 0x4B00, 0x8BC1, 0x8A81, 0x4A40, 0x4E00, 0x8EC1,
+	0x8F81, 0x4F40, 0x8D01, 0x4DC0, 0x4C80, 0x8C41, 0x4400, 0x84C1, 0x8581,
+	0x4540, 0x8701, 0x47C0, 0x4680, 0x8641, 0x8201, 0x42C0, 0x4380, 0x8341,
+	0x4100, 0x81C1, 0x8081, 0x4040
+};
+
+/*********************************************************************
+ *                                                                   *
+ *   unsigned short update_crc( unsigned long crc, unsigned char c ) *
+ *                                                                   *
+ *   The function update_crc calculates a  new  CRC-16  value        *
+ *   based  on  the  previous value of the CRC and the next byte     *
+ *   of the data to be checked.                                      *
+ *                                                                   *
+ *********************************************************************
+ */
+unsigned short update_crc(unsigned short crc, unsigned char c)
+{
+	unsigned short tmp;
+
+	tmp = crc ^ (0x00ff & (unsigned short)c);
+	crc = (crc >> 8) ^ crc16_tab[tmp & 0xff];
+
+	return crc;
+}
diff --git a/util/uut/lib_crc.h b/util/uut/lib_crc.h
index 58db81c4e5..7d75c9b501 100644
--- a/util/uut/lib_crc.h
+++ b/util/uut/lib_crc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/util/uut/main.c b/util/uut/main.c
deleted file mode 100644
index 94f8cd66c8..0000000000
--- a/util/uut/main.c
+++ /dev/null
@@ -1,770 +0,0 @@
-/*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <errno.h>
-#include <getopt.h>
-#include <stdarg.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/stat.h>
-
-#include "com_port.h"
-#include "compile_time_macros.h"
-#include "main.h"
-#include "misc_util.h"
-#include "opr.h"
-
-/*----------------------------------------------------------------------------
- * Constant definitions
- *---------------------------------------------------------------------------
- */
-
-#define MAX_FILE_NAME_SIZE 512
-#define MAX_PARAM_SIZE 32
-#define MAX_MSG_SIZE 128
-#define MAX_SYNC_RETRIES 3
-
-/* Default values */
-#define DEFAULT_BAUD_RATE 115200
-#define DEFAULT_PORT_NAME "ttyS0"
-#define DEFAULT_DEV_NUM 0
-#define DEFAULT_FLASH_OFFSET 0
-
-/* The magic number in monitor header */
-#define MONITOR_HDR_TAG        0xA5075001
-/* The location of monitor header */
-#define MONITOR_HDR_ADDR       0x200C3000
-/* The start address of the monitor little firmware to execute */
-#define MONITOR_ADDR           0x200C3020
-/* The start address to store the firmware segment to be programmed */
-#define FIRMWARE_START_ADDR    0x10090000
-/* Divide the ec firmware image into 4K byte */
-#define FIRMWARE_SEGMENT       0x1000
-/* Register address for chip ID */
-#define NPCX_SRID_CR           0x400C101C
-/* Register address for device ID */
-#define NPCX_DEVICE_ID_CR      0x400C1022
-#define NPCX_FLASH_BASE_ADDR   0x64000000
-
-/*---------------------------------------------------------------------------
- * Global variables
- *---------------------------------------------------------------------------
- */
-bool verbose;
-bool console;
-struct comport_fields port_cfg;
-
-/*---------------------------------------------------------------------------
- * Local variables
- *---------------------------------------------------------------------------
- */
-
-static const char tool_name[] = {"LINUX UART Update Tool"};
-static const char tool_version[] = {"2.0.1"};
-
-static char port_name[MAX_PARAM_SIZE];
-static char opr_name[MAX_PARAM_SIZE];
-static char file_name[MAX_FILE_NAME_SIZE];
-static char addr_str[MAX_PARAM_SIZE];
-static char size_str[MAX_PARAM_SIZE];
-static uint32_t baudrate;
-static uint32_t dev_num;
-static uint32_t flash_offset;
-static bool auto_mode;
-static bool read_flash_flag;
-
-struct npcx_chip_info {
-	uint8_t device_id;
-	uint8_t chip_id;
-	uint32_t flash_size;
-};
-
-const static struct npcx_chip_info chip_info[] = {
-	{
-		/* NPCX796FA */
-		.device_id = 0x21,
-		.chip_id = 0x06,
-		.flash_size = 1024 * 1024,
-	},
-
-	{
-		/* NPCX796FB */
-		.device_id = 0x21,
-		.chip_id = 0x07,
-		.flash_size = 1024 * 1024,
-	},
-
-	{
-		/* NPCX796FC */
-		.device_id = 0x29,
-		.chip_id = 0x07,
-		.flash_size = 512 * 1024,
-	},
-
-	{
-		/* NPCX797FC */
-		.device_id = 0x20,
-		.chip_id = 0x07,
-		.flash_size = 512 * 1024,
-	},
-
-	{
-		/* NPCX797WB */
-		.device_id = 0x24,
-		.chip_id = 0x07,
-		.flash_size = 1024 * 1024,
-	},
-
-	{
-		/* NPCX797WC */
-		.device_id = 0x2C,
-		.chip_id = 0x07,
-		.flash_size = 512 * 1024,
-	},
-
-	{
-		/* NPCX993F */
-		.device_id = 0x25,
-		.chip_id = 0x09,
-		.flash_size = 512 * 1024,
-	},
-
-	{
-		/* NPCX996F */
-		.device_id = 0x21,
-		.chip_id = 0x09,
-		.flash_size = 512 * 1024,
-	},
-};
-/*---------------------------------------------------------------------------
- * Functions prototypes
- *---------------------------------------------------------------------------
- */
-
-static void param_parse_cmd_line(int argc, char *argv[]);
-static void param_check_opr_num(const char *opr);
-static uint32_t param_get_file_size(const char *file_name);
-static uint32_t param_get_str_size(char *string);
-static void main_print_version(void);
-static void tool_usage(void);
-static void exit_uart_app(int32_t exit_status);
-
-enum EXIT_CODE {
-	EC_OK = 0x00,
-	EC_PORT_ERR = 0x01,
-	EC_BAUDRATE_ERR = 0x02,
-	EC_SYNC_ERR = 0x03,
-	EC_DEV_NUM_ERR = 0x04,
-	EC_OPR_MUM_ERR = 0x05,
-	EC_ALIGN_ERR = 0x06,
-	EC_FILE_ERR = 0x07,
-	EC_UNSUPPORTED_CMD_ERR = 0x08
-};
-
-/*---------------------------------------------------------------------------
- * Function implementation
- *---------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------
- * Function:	image_auto_write
- *
- * Parameters:    offset - The start address of the flash to write the firmware
- *                         to.
- *                buffer - The buffer holds data of the firmware.
- *                file_size - the size to be programmed.
- * Returns:       1 for a successful operation, 0 otherwise.
- * Side effects:
- * Description:
- *               Divide the firmware to segments and program them one by one.
- *---------------------------------------------------------------------------
- */
-static bool image_auto_write(uint32_t offset, uint8_t *buffer,
-				uint32_t file_size)
-{
-	uint32_t data_buf[4];
-	uint32_t addr, chunk_remain, file_seg, flash_index, seg;
-	uint32_t count, percent, total;
-	uint32_t i;
-
-	flash_index = offset;
-	/* Monitor tag */
-	data_buf[0] = MONITOR_HDR_TAG;
-
-	file_seg = file_size;
-	total = 0;
-	while (file_seg) {
-		seg = (file_seg > FIRMWARE_SEGMENT) ?
-					FIRMWARE_SEGMENT : file_seg;
-		/*
-		 * Check if the content of the segment is all 0xff.
-		 * If yes, there is no need to write.
-		 * Call the monitor to erase the segment only for
-		 * time efficiency.
-		 */
-		for (i = 0; i < seg && buffer[i] == 0xFF; i++)
-			;
-		if (i == seg) {
-			data_buf[1] = seg;
-			/*
-			 * Set src_addr = 0 as a flag. When the monitor read 0
-			 * from this field, it will do sector erase only.
-			 */
-			data_buf[2] = 0;
-			data_buf[3] = flash_index;
-			opr_write_chunk((uint8_t *)data_buf, MONITOR_HDR_ADDR,
-						sizeof(data_buf));
-			if (opr_execute_return(MONITOR_ADDR) != true)
-				return false;
-			file_seg -= seg;
-			flash_index += seg;
-			buffer += seg;
-			total += seg;
-			percent = total * 100 / file_size;
-			printf("\r[%d%%] %d/%d", percent, total, file_size);
-			fflush(stdout);
-			continue;
-		}
-		chunk_remain = seg;
-		addr = FIRMWARE_START_ADDR;
-		/* the size to be programmed */
-		data_buf[1] = seg;
-		/* The source(RAM) address where the firmware is stored. */
-		data_buf[2] = FIRMWARE_START_ADDR;
-		/*
-		 * The offset of the flash where the segment to be programmed.
-		 */
-		data_buf[3] = flash_index;
-		/* Write the monitor header to RAM */
-		opr_write_chunk((uint8_t *)data_buf, MONITOR_HDR_ADDR,
-						sizeof(data_buf));
-		while (chunk_remain) {
-			count = (chunk_remain > MAX_RW_DATA_SIZE) ?
-						MAX_RW_DATA_SIZE : chunk_remain;
-			if (opr_write_chunk(buffer, addr, count) != true)
-				return false;
-
-			addr += count;
-			buffer += count;
-			chunk_remain -= count;
-			total += count;
-			percent = total * 100 / file_size;
-			printf("\r[%d%%] %d/%d", percent, total, file_size);
-		}
-		fflush(stdout);
-		if (opr_execute_return(MONITOR_ADDR) != true)
-			return false;
-		file_seg -= seg;
-		flash_index += seg;
-	}
-	printf("\n");
-	/* Clear the UUT header tag */
-	data_buf[0] = 0;
-	opr_write_chunk((uint8_t *)data_buf, MONITOR_HDR_ADDR, 4);
-	return true;
-}
-
-static bool get_flash_size(uint32_t *flash_size)
-{
-	uint8_t dev_id, chip_id, i;
-
-	if (opr_read_chunk(&dev_id, NPCX_DEVICE_ID_CR, 1) != true)
-		return false;
-
-	if (opr_read_chunk(&chip_id, NPCX_SRID_CR, 1) != true)
-		return false;
-
-	for (i = 0; i < ARRAY_SIZE(chip_info); i++) {
-		if (chip_info[i].device_id == dev_id &&
-				chip_info[i].chip_id == chip_id) {
-			*flash_size = chip_info[i].flash_size;
-			return true;
-		}
-	}
-	printf("Unknown NPCX device ID:0x%02x chip ID:0x%02x\n",
-				dev_id, chip_id);
-
-	return false;
-}
-
-/*---------------------------------------------------------------------------
- * Function:	read_input_file
- *
- * Parameters:    size - The size of input file.
- *                file_name - The name if input file.
- * Returns:       The address of the buffer allocated to stroe file content.
- * Side effects:
- * Description:
- *               Read the file content into an allocated buffer.
- *---------------------------------------------------------------------------
- */
-static uint8_t *read_input_file(uint32_t size, const char *file_name)
-{
-	uint8_t *buffer;
-	FILE *input_fp;
-
-	buffer = malloc(size);
-	if (!buffer) {
-		fprintf(stderr, "Cannot allocate %d bytes\n", size);
-		return NULL;
-	}
-	input_fp = fopen(file_name, "r");
-	if (!input_fp) {
-		display_color_msg(FAIL,
-			"ERROR: cannot open file %s\n", file_name);
-		free(buffer);
-		return NULL;
-	}
-	if (fread(buffer, size, 1, input_fp) != 1) {
-		fprintf(stderr, "Cannot read %s\n", file_name);
-		fclose(input_fp);
-		free(buffer);
-		return NULL;
-	}
-	fclose(input_fp);
-	return buffer;
-}
-
-/*---------------------------------------------------------------------------
- * Function:	main
- *
- * Parameters:		argc - Argument Count.
- *			argv - Argument Vector.
- * Returns:		1 for a successful operation, 0 otherwise.
- * Side effects:
- * Description:
- *		Console application main operation.
- *---------------------------------------------------------------------------
- */
-int main(int argc, char *argv[])
-{
-	char *stop_str;
-	char aux_buf[MAX_FILE_NAME_SIZE];
-	uint32_t size = 0;
-	uint32_t addr = 0;
-	enum sync_result sr;
-	uint8_t *buffer;
-	int sync_cnt;
-
-	if (argc <= 1)
-		exit(EC_UNSUPPORTED_CMD_ERR);
-
-	/* Setup defaults */
-	strncpy(port_name, DEFAULT_PORT_NAME, sizeof(port_name));
-	baudrate = DEFAULT_BAUD_RATE;
-	dev_num = DEFAULT_DEV_NUM;
-	flash_offset = DEFAULT_FLASH_OFFSET;
-	opr_name[0] = '\0';
-	verbose = true;
-	console = false;
-	auto_mode = false;
-	read_flash_flag = false;
-
-	param_parse_cmd_line(argc, argv);
-
-	/* Configure COM Port parameters */
-	port_cfg.baudrate = MAX(baudrate, BR_LOW_LIMIT);
-	port_cfg.byte_size = CS8;
-	port_cfg.flow_control = 0;
-	port_cfg.parity = 0;
-	port_cfg.stop_bits = 0;
-
-	/*
-	 * Open a ComPort device. If user haven't specified such, use ComPort 1
-	 */
-	if (opr_open_port(port_name, port_cfg) != true)
-		exit(EC_PORT_ERR);
-
-	if (baudrate == 0) { /* Scan baud rate range */
-		opr_scan_baudrate();
-		exit_uart_app(EC_OK);
-	}
-
-	/* Verify Host and Device are synchronized */
-	DISPLAY_MSG(("Performing a Host/Device synchronization check...\n"));
-	for (sync_cnt = 1; sync_cnt <= MAX_SYNC_RETRIES; sync_cnt++) {
-		sr = opr_check_sync(baudrate);
-		if (sr == SR_OK)
-			break;
-		/*
-		 * If it fails, try it again up to three times.
-		 * It might fail for garbage data drainage from H1, or
-		 * for timeout due to unstable data transfer yet.
-		 */
-		display_color_msg(FAIL,
-			"Host/Device synchronization failed, error = %d,"
-			" fail count = %d\n", sr, sync_cnt);
-	}
-	if (sync_cnt > MAX_SYNC_RETRIES)
-		exit_uart_app(EC_SYNC_ERR);
-
-	if (auto_mode) {
-		size = param_get_file_size(file_name);
-		if (size == 0)
-			exit_uart_app(EC_FILE_ERR);
-
-		buffer = read_input_file(size, file_name);
-		if (!buffer)
-			exit_uart_app(EC_FILE_ERR);
-
-		printf("Write file %s at %d with %d bytes\n",
-					file_name, flash_offset, size);
-		if (image_auto_write(flash_offset, buffer, size)) {
-			printf("Flash Done.\n");
-			free(buffer);
-			exit_uart_app(EC_OK);
-		}
-		free(buffer);
-		exit_uart_app(-1);
-	}
-
-	if (read_flash_flag) {
-		uint32_t flash_size;
-
-		if (get_flash_size(&flash_size)) {
-			printf("Read %d bytes from flash...\n", flash_size);
-			opr_read_mem(file_name, NPCX_FLASH_BASE_ADDR,
-					flash_size);
-			exit_uart_app(EC_OK);
-		}
-
-		printf("Fail to read the flash size\n");
-		exit_uart_app(-1);
-	}
-
-	param_check_opr_num(opr_name);
-
-	/* Write buffer data to chosen address */
-	if (strcmp(opr_name, OPR_WRITE_MEM) == 0) {
-		addr = strtoul(addr_str, &stop_str, 0);
-
-		if (console) {
-			/*
-			 * Copy the input string to an auxiliary buffer, since
-			 * string is altered by param_get_str_size
-			 */
-			memcpy(aux_buf, file_name, sizeof(file_name));
-			/* Retrieve input size */
-			size = param_get_str_size(file_name);
-			/* Ensure non-zero size */
-			if (size == 0)
-				exit_uart_app(EC_FILE_ERR);
-			opr_write_mem(aux_buf, addr, size);
-		} else {
-			size = param_get_file_size(file_name);
-			if (size == 0)
-				exit_uart_app(EC_FILE_ERR);
-			buffer = read_input_file(size, file_name);
-			if (!buffer)
-				exit_uart_app(EC_FILE_ERR);
-			opr_write_mem(buffer, addr, size);
-			free(buffer);
-		}
-	} else if (strcmp(opr_name, OPR_READ_MEM) == 0) {
-		/* Read data to chosen address */
-
-		addr = strtoul(addr_str, &stop_str, 0);
-		size = strtoul(size_str, &stop_str, 0);
-
-		opr_read_mem(file_name, addr, size);
-	} else if (strcmp(opr_name, OPR_EXECUTE_EXIT) == 0) {
-		/* Execute From Address a non-return code */
-
-		addr = strtoul(addr_str, &stop_str, 0);
-
-		opr_execute_exit(addr);
-		exit_uart_app(EC_OK);
-	} else if (strcmp(opr_name, OPR_EXECUTE_CONT) == 0) {
-		/* Execute From Address a returnable code */
-
-		addr = strtoul(addr_str, &stop_str, 0);
-
-		opr_execute_return(addr);
-	} else {
-		exit_uart_app(EC_UNSUPPORTED_CMD_ERR);
-	}
-
-	exit_uart_app(EC_OK);
-	return 0;
-}
-
-/*---------------------------------------------------------------------------
- * Function:	param_parse_cmd_line
- *
- * Parameters:		argc - Argument Count.
- *			argv - Argument Vector.
- * Returns:		None.
- * Side effects:
- * Description:
- *		Parse command line parameters.
- *---------------------------------------------------------------------------
- */
-
-static const struct option long_opts[] = {
-	{"version",         0, 0, 'v'},
-	{"help",            0, 0, 'h'},
-	{"quiet",           0, 0, 'q'},
-	{"console",         0, 0, 'c'},
-	{"auto",            0, 0, 'A'},
-	{"read-flash",      0, 0, 'r'},
-	{"baudrate",        1, 0, 'b'},
-	{"opr",             1, 0, 'o'},
-	{"port",            1, 0, 'p'},
-	{"file",            1, 0, 'f'},
-	{"addr",            1, 0, 'a'},
-	{"size",            1, 0, 's'},
-	{"offset",          1, 0, 'O'},
-	{NULL,       0, 0, 0}
-};
-
-static char *short_opts = "vhqcArb:o:p:f:a:s:O:?";
-
-static void param_parse_cmd_line(int argc, char *argv[])
-{
-	int opt, idx;
-
-	while ((opt = getopt_long(argc, argv, short_opts,
-				long_opts, &idx)) != -1) {
-
-		switch (opt) {
-		case 'v':
-			main_print_version();
-			exit(EC_OK);
-		case 'h':
-		case '?':
-			tool_usage();
-			opr_usage();
-			exit(EC_OK);
-		case 'q':
-			verbose = false;
-			break;
-		case 'c':
-			console = true;
-			break;
-		case 'A':
-			auto_mode = true;
-			break;
-		case 'r':
-			read_flash_flag = true;
-			break;
-		case 'b':
-			if (sscanf(optarg, "%du", &baudrate) == 0)
-				exit(EC_BAUDRATE_ERR);
-			break;
-		case 'o':
-			strncpy(opr_name, optarg, sizeof(opr_name));
-			opr_name[sizeof(opr_name)-1] = '\0';
-			break;
-		case 'p':
-			strncpy(port_name, optarg, sizeof(port_name));
-			port_name[sizeof(port_name)-1] = '\0';
-			break;
-		case 'f':
-			strncpy(file_name, optarg, sizeof(file_name));
-			file_name[sizeof(file_name)-1] = '\0';
-			break;
-		case 'a':
-			strncpy(addr_str, optarg, sizeof(addr_str));
-			addr_str[sizeof(addr_str)-1] = '\0';
-			break;
-		case 's':
-			strncpy(size_str, optarg, sizeof(size_str));
-			size_str[sizeof(size_str)-1] = '\0';
-			break;
-		case 'O':
-			flash_offset = strtol(optarg, NULL, 0);
-			break;
-		}
-	}
-}
-
-/*---------------------------------------------------------------------------
- * Function:	param_check_opr_num
- *
- * Parameters:	opr - Operation Number.
- * Returns:	none.
- * Side effects:
- * Description:
- *		Verify the validity of operation Number.
- *---------------------------------------------------------------------------
- */
-static void param_check_opr_num(const char *opr)
-{
-
-	if ((strcasecmp(opr, OPR_WRITE_MEM) != 0) &&
-		(strcasecmp(opr, OPR_READ_MEM) != 0) &&
-		(strcasecmp(opr, OPR_EXECUTE_EXIT) != 0) &&
-		(strcasecmp(opr, OPR_EXECUTE_CONT) != 0)) {
-		display_color_msg(FAIL,
-			"ERROR: Operation %s not supported, Supported "
-			"operations are %s, %s, %s & %s\n",
-			opr, OPR_WRITE_MEM, OPR_READ_MEM, OPR_EXECUTE_EXIT,
-			OPR_EXECUTE_CONT);
-		exit_uart_app(EC_OPR_MUM_ERR);
-	}
-}
-
-/*---------------------------------------------------------------------------
- * Function:	param_get_file_size
- *
- * Parameters:	file_name - input file name.
- * Returns:	size of file (in bytes).
- * Side effects:
- * Description:
- *		Retrieve the size (in bytes) of a given file.
- *--------------------------------------------------------------------------
- */
-static uint32_t param_get_file_size(const char *file_name)
-{
-	struct stat fst;
-
-	if (stat(file_name, &fst)) {
-		display_color_msg(FAIL,
-				"ERROR: Could not stat file [%s]\n", file_name);
-		return 0;
-	}
-	return fst.st_size;
-
-}
-
-/*---------------------------------------------------------------------------
- * Function:	param_get_str_size
- *
- * Parameters:	string - input string.
- * Returns:	size of double-words (in bytes).
- * Side effects:
- * Description:
- *	Retrieve the size (in bytes) of double-word values in a given string.
- *	E.g., given the string "1234 AB5678 FF", return 12 (for three
- *	double-words).
- *---------------------------------------------------------------------------
- */
-static uint32_t param_get_str_size(char *string)
-{
-	uint32_t str_size = 0;
-	char seps[] = " ";
-	char *token = NULL;
-
-	/* Verify string is non-NULL */
-	if ((string == NULL) || (strlen(string) == 0)) {
-		display_color_msg(FAIL,
-			"ERROR: Zero length input string provided\n");
-		return 0;
-	}
-
-	/* Read first token from string */
-	token = strtok(string, seps);
-
-	/* Loop while there are tokens in "string" */
-	while (token != NULL) {
-		str_size++;
-		token = strtok(NULL, seps);
-	}
-
-	/* Refer to each token as a double-word */
-	str_size *= sizeof(uint32_t);
-	return str_size;
-}
-
-/*--------------------------------------------------------------------------
- * Function:	tool_usage
- *
- * Parameters:	none.
- * Returns:	none.
- * Side effects:
- * Description:
- *		Prints the console application help menu.
- *--------------------------------------------------------------------------
- */
-static void tool_usage(void)
-{
-	printf("%s version %s\n\n", tool_name, tool_version);
-	printf("General switches:\n");
-	printf("  -v, --version        - Print version\n");
-	printf("  -h, --help           - Help menu\n");
-	printf("  -q, --quiet          - Suppress verbose mode (default is "
-	       "verbose ON)\n");
-	printf("  -c, --console        - Print data to console (default is "
-	       "print to file)\n");
-	printf("  -p, --port <name>    - Serial port name (default is %s)\n",
-		DEFAULT_PORT_NAME);
-	printf("  -b, --baudrate <num> - COM Port baud-rate (default is %d)\n",
-		DEFAULT_BAUD_RATE);
-	printf("  -A, --auto           - Enable auto mode. (default is off)\n");
-	printf("  -O, --offset <num>   - With --auto, assign the offset of");
-	printf(" flash where the image to be written.\n");
-	printf("  -r, --read-flash     - With --file=<file>, Read the whole"
-			" flash content and write it to <file>.\n");
-	printf("\n");
-	printf("Operation specific switches:\n");
-	printf("  -o, --opr   <name>   - Operation number (see list below)\n");
-	printf("  -f, --file  <name>   - Input/output file name\n");
-	printf("  -a, --addr  <num>    - Start memory address\n");
-	printf("  -s, --size  <num>    - Size of data to read\n");
-	printf("\n");
-}
-
-/*--------------------------------------------------------------------------
- * Function:	main_print_version
- *
- * Parameters:	none
- * Returns:	none
- * Side effects:
- * Description:
- *		This routine prints the tool version
- *--------------------------------------------------------------------------
- */
-static void main_print_version(void)
-{
-	printf("%s version %s\n\n", tool_name, tool_version);
-}
-
-/*---------------------------------------------------------------------------
- * Function:	exit_uart_app
- *
- * Parameters:	none.
- * Returns:	none.
- * Side effects:
- * Description:
- *		Exit "nicely" the application.
- *---------------------------------------------------------------------------
- */
-static void exit_uart_app(int32_t exit_status)
-{
-	if (opr_close_port() != true)
-		display_color_msg(FAIL, "ERROR: Port close failed.\n");
-
-	exit(exit_status);
-}
-
-/*---------------------------------------------------------------------------
- * Function:	display_color_msg
- *
- * Parameters:
- *		success - SUCCESS for successful message, FAIL for erroneous
- *			  massage.
- *		fmt     - Massage to dispaly (format and arguments).
- *
- * Returns:	none
- * Side effects: Using DISPLAY_MSG macro.
- * Description:
- *		This routine displays a message using color attributes:
- *		In case of a successful message, use green foreground text on
- *		black background.
- *		In case of an erroneous message, use red foreground text on
- *		black background.
- *---------------------------------------------------------------------------
- */
-void display_color_msg(bool success, char *fmt, ...)
-{
-	va_list argptr;
-
-	va_start(argptr, fmt);
-	vprintf(fmt, argptr);
-	va_end(argptr);
-}
diff --git a/util/uut/main.cc b/util/uut/main.cc
new file mode 100644
index 0000000000..df34191acc
--- /dev/null
+++ b/util/uut/main.cc
@@ -0,0 +1,771 @@
+/*
+ * Copyright 2018 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "com_port.h"
+#include "compile_time_macros.h"
+#include "main.h"
+#include "misc_util.h"
+#include "opr.h"
+
+#include <errno.h>
+#include <stdarg.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <getopt.h>
+#include <sys/stat.h>
+
+/*----------------------------------------------------------------------------
+ * Constant definitions
+ *---------------------------------------------------------------------------
+ */
+
+#define MAX_FILE_NAME_SIZE 512
+#define MAX_PARAM_SIZE 32
+#define MAX_MSG_SIZE 128
+#define MAX_SYNC_RETRIES 3
+
+/* Default values */
+#define DEFAULT_BAUD_RATE 115200
+#define DEFAULT_PORT_NAME "ttyS0"
+#define DEFAULT_DEV_NUM 0
+#define DEFAULT_FLASH_OFFSET 0
+
+/* The magic number in monitor header */
+#define MONITOR_HDR_TAG 0xA5075001
+/* The location of monitor header */
+#define MONITOR_HDR_ADDR 0x200C3000
+/* The start address of the monitor little firmware to execute */
+#define MONITOR_ADDR 0x200C3020
+/* The start address to store the firmware segment to be programmed */
+#define FIRMWARE_START_ADDR 0x10090000
+/* Divide the ec firmware image into 4K byte */
+#define FIRMWARE_SEGMENT 0x1000
+/* Register address for chip ID */
+#define NPCX_SRID_CR 0x400C101C
+/* Register address for device ID */
+#define NPCX_DEVICE_ID_CR 0x400C1022
+#define NPCX_FLASH_BASE_ADDR 0x64000000
+
+/*---------------------------------------------------------------------------
+ * Global variables
+ *---------------------------------------------------------------------------
+ */
+bool verbose;
+bool console;
+struct comport_fields port_cfg;
+
+/*---------------------------------------------------------------------------
+ * Local variables
+ *---------------------------------------------------------------------------
+ */
+
+static const char tool_name[] = { "LINUX UART Update Tool" };
+static const char tool_version[] = { "2.0.1" };
+
+static char port_name[MAX_PARAM_SIZE];
+static char opr_name[MAX_PARAM_SIZE];
+static char file_name[MAX_FILE_NAME_SIZE];
+static char addr_str[MAX_PARAM_SIZE];
+static char size_str[MAX_PARAM_SIZE];
+static uint32_t baudrate;
+static uint32_t dev_num;
+static uint32_t flash_offset;
+static bool auto_mode;
+static bool read_flash_flag;
+
+struct npcx_chip_info {
+	uint8_t device_id;
+	uint8_t chip_id;
+	uint32_t flash_size;
+};
+
+const static struct npcx_chip_info chip_info[] = {
+	{
+		/* NPCX796FA */
+		.device_id = 0x21,
+		.chip_id = 0x06,
+		.flash_size = 1024 * 1024,
+	},
+
+	{
+		/* NPCX796FB */
+		.device_id = 0x21,
+		.chip_id = 0x07,
+		.flash_size = 1024 * 1024,
+	},
+
+	{
+		/* NPCX796FC */
+		.device_id = 0x29,
+		.chip_id = 0x07,
+		.flash_size = 512 * 1024,
+	},
+
+	{
+		/* NPCX797FC */
+		.device_id = 0x20,
+		.chip_id = 0x07,
+		.flash_size = 512 * 1024,
+	},
+
+	{
+		/* NPCX797WB */
+		.device_id = 0x24,
+		.chip_id = 0x07,
+		.flash_size = 1024 * 1024,
+	},
+
+	{
+		/* NPCX797WC */
+		.device_id = 0x2C,
+		.chip_id = 0x07,
+		.flash_size = 512 * 1024,
+	},
+
+	{
+		/* NPCX993F */
+		.device_id = 0x25,
+		.chip_id = 0x09,
+		.flash_size = 512 * 1024,
+	},
+
+	{
+		/* NPCX996F */
+		.device_id = 0x21,
+		.chip_id = 0x09,
+		.flash_size = 512 * 1024,
+	},
+	{
+		/* NPCX997F */
+		.device_id = 0x22,
+		.chip_id = 0x09,
+		.flash_size = 1024 * 1024,
+	},
+};
+/*---------------------------------------------------------------------------
+ * Functions prototypes
+ *---------------------------------------------------------------------------
+ */
+
+static void param_parse_cmd_line(int argc, char *argv[]);
+static void param_check_opr_num(const char *opr);
+static uint32_t param_get_file_size(const char *file_name);
+static uint32_t param_get_str_size(char *string);
+static void main_print_version(void);
+static void tool_usage(void);
+static void exit_uart_app(int32_t exit_status);
+
+enum EXIT_CODE {
+	EC_OK = 0x00,
+	EC_PORT_ERR = 0x01,
+	EC_BAUDRATE_ERR = 0x02,
+	EC_SYNC_ERR = 0x03,
+	EC_DEV_NUM_ERR = 0x04,
+	EC_OPR_MUM_ERR = 0x05,
+	EC_ALIGN_ERR = 0x06,
+	EC_FILE_ERR = 0x07,
+	EC_UNSUPPORTED_CMD_ERR = 0x08
+};
+
+/*---------------------------------------------------------------------------
+ * Function implementation
+ *---------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------
+ * Function:	image_auto_write
+ *
+ * Parameters:    offset - The start address of the flash to write the firmware
+ *                         to.
+ *                buffer - The buffer holds data of the firmware.
+ *                file_size - the size to be programmed.
+ * Returns:       1 for a successful operation, 0 otherwise.
+ * Side effects:
+ * Description:
+ *               Divide the firmware to segments and program them one by one.
+ *---------------------------------------------------------------------------
+ */
+static bool image_auto_write(uint32_t offset, uint8_t *buffer,
+			     uint32_t file_size)
+{
+	uint32_t data_buf[4];
+	uint32_t addr, chunk_remain, file_seg, flash_index, seg;
+	uint32_t count, percent, total;
+	uint32_t i;
+
+	flash_index = offset;
+	/* Monitor tag */
+	data_buf[0] = MONITOR_HDR_TAG;
+
+	file_seg = file_size;
+	total = 0;
+	while (file_seg) {
+		seg = (file_seg > FIRMWARE_SEGMENT) ? FIRMWARE_SEGMENT :
+						      file_seg;
+		/*
+		 * Check if the content of the segment is all 0xff.
+		 * If yes, there is no need to write.
+		 * Call the monitor to erase the segment only for
+		 * time efficiency.
+		 */
+		for (i = 0; i < seg && buffer[i] == 0xFF; i++)
+			;
+		if (i == seg) {
+			data_buf[1] = seg;
+			/*
+			 * Set src_addr = 0 as a flag. When the monitor read 0
+			 * from this field, it will do sector erase only.
+			 */
+			data_buf[2] = 0;
+			data_buf[3] = flash_index;
+			opr_write_chunk((uint8_t *)data_buf, MONITOR_HDR_ADDR,
+					sizeof(data_buf));
+			if (opr_execute_return(MONITOR_ADDR) != true)
+				return false;
+			file_seg -= seg;
+			flash_index += seg;
+			buffer += seg;
+			total += seg;
+			percent = total * 100 / file_size;
+			printf("\r[%d%%] %d/%d", percent, total, file_size);
+			fflush(stdout);
+			continue;
+		}
+		chunk_remain = seg;
+		addr = FIRMWARE_START_ADDR;
+		/* the size to be programmed */
+		data_buf[1] = seg;
+		/* The source(RAM) address where the firmware is stored. */
+		data_buf[2] = FIRMWARE_START_ADDR;
+		/*
+		 * The offset of the flash where the segment to be programmed.
+		 */
+		data_buf[3] = flash_index;
+		/* Write the monitor header to RAM */
+		opr_write_chunk((uint8_t *)data_buf, MONITOR_HDR_ADDR,
+				sizeof(data_buf));
+		while (chunk_remain) {
+			count = (chunk_remain > MAX_RW_DATA_SIZE) ?
+					MAX_RW_DATA_SIZE :
+					chunk_remain;
+			if (opr_write_chunk(buffer, addr, count) != true)
+				return false;
+
+			addr += count;
+			buffer += count;
+			chunk_remain -= count;
+			total += count;
+			percent = total * 100 / file_size;
+			printf("\r[%d%%] %d/%d", percent, total, file_size);
+		}
+		fflush(stdout);
+		if (opr_execute_return(MONITOR_ADDR) != true)
+			return false;
+		file_seg -= seg;
+		flash_index += seg;
+	}
+	printf("\n");
+	/* Clear the UUT header tag */
+	data_buf[0] = 0;
+	opr_write_chunk((uint8_t *)data_buf, MONITOR_HDR_ADDR, 4);
+	return true;
+}
+
+static bool get_flash_size(uint32_t *flash_size)
+{
+	uint8_t dev_id, chip_id, i;
+
+	if (opr_read_chunk(&dev_id, NPCX_DEVICE_ID_CR, 1) != true)
+		return false;
+
+	if (opr_read_chunk(&chip_id, NPCX_SRID_CR, 1) != true)
+		return false;
+
+	for (i = 0; i < ARRAY_SIZE(chip_info); i++) {
+		if (chip_info[i].device_id == dev_id &&
+		    chip_info[i].chip_id == chip_id) {
+			*flash_size = chip_info[i].flash_size;
+			return true;
+		}
+	}
+	printf("Unknown NPCX device ID:0x%02x chip ID:0x%02x\n", dev_id,
+	       chip_id);
+
+	return false;
+}
+
+/*---------------------------------------------------------------------------
+ * Function:	read_input_file
+ *
+ * Parameters:    size - The size of input file.
+ *                file_name - The name if input file.
+ * Returns:       The address of the buffer allocated to stroe file content.
+ * Side effects:
+ * Description:
+ *               Read the file content into an allocated buffer.
+ *---------------------------------------------------------------------------
+ */
+static uint8_t *read_input_file(uint32_t size, const char *file_name)
+{
+	uint8_t *buffer;
+	FILE *input_fp;
+
+	buffer = (uint8_t *)(malloc(size));
+	if (!buffer) {
+		fprintf(stderr, "Cannot allocate %d bytes\n", size);
+		return NULL;
+	}
+	input_fp = fopen(file_name, "r");
+	if (!input_fp) {
+		display_color_msg(FAIL, "ERROR: cannot open file %s\n",
+				  file_name);
+		free(buffer);
+		return NULL;
+	}
+	if (fread(buffer, size, 1, input_fp) != 1) {
+		fprintf(stderr, "Cannot read %s\n", file_name);
+		fclose(input_fp);
+		free(buffer);
+		return NULL;
+	}
+	fclose(input_fp);
+	return buffer;
+}
+
+/*---------------------------------------------------------------------------
+ * Function:	main
+ *
+ * Parameters:		argc - Argument Count.
+ *			argv - Argument Vector.
+ * Returns:		1 for a successful operation, 0 otherwise.
+ * Side effects:
+ * Description:
+ *		Console application main operation.
+ *---------------------------------------------------------------------------
+ */
+int main(int argc, char *argv[])
+{
+	char *stop_str;
+	char aux_buf[MAX_FILE_NAME_SIZE];
+	uint32_t size = 0;
+	uint32_t addr = 0;
+	enum sync_result sr;
+	uint8_t *buffer;
+	int sync_cnt;
+
+	if (argc <= 1)
+		exit(EC_UNSUPPORTED_CMD_ERR);
+
+	/* Setup defaults */
+	strncpy(port_name, DEFAULT_PORT_NAME, sizeof(port_name));
+	baudrate = DEFAULT_BAUD_RATE;
+	dev_num = DEFAULT_DEV_NUM;
+	flash_offset = DEFAULT_FLASH_OFFSET;
+	opr_name[0] = '\0';
+	verbose = true;
+	console = false;
+	auto_mode = false;
+	read_flash_flag = false;
+
+	param_parse_cmd_line(argc, argv);
+
+	/* Configure COM Port parameters */
+	port_cfg.baudrate = MAX(baudrate, BR_LOW_LIMIT);
+	port_cfg.byte_size = CS8;
+	port_cfg.flow_control = 0;
+	port_cfg.parity = 0;
+	port_cfg.stop_bits = 0;
+
+	/*
+	 * Open a ComPort device. If user haven't specified such, use ComPort 1
+	 */
+	if (opr_open_port(port_name, port_cfg) != true)
+		exit(EC_PORT_ERR);
+
+	if (baudrate == 0) { /* Scan baud rate range */
+		opr_scan_baudrate();
+		exit_uart_app(EC_OK);
+	}
+
+	/* Verify Host and Device are synchronized */
+	DISPLAY_MSG(("Performing a Host/Device synchronization check...\n"));
+	for (sync_cnt = 1; sync_cnt <= MAX_SYNC_RETRIES; sync_cnt++) {
+		sr = opr_check_sync(baudrate);
+		if (sr == SR_OK)
+			break;
+		/*
+		 * If it fails, try it again up to three times.
+		 * It might fail for garbage data drainage from H1, or
+		 * for timeout due to unstable data transfer yet.
+		 */
+		display_color_msg(
+			FAIL,
+			"Host/Device synchronization failed, error = %d,"
+			" fail count = %d\n",
+			sr, sync_cnt);
+	}
+	if (sync_cnt > MAX_SYNC_RETRIES)
+		exit_uart_app(EC_SYNC_ERR);
+
+	if (auto_mode) {
+		size = param_get_file_size(file_name);
+		if (size == 0)
+			exit_uart_app(EC_FILE_ERR);
+
+		buffer = read_input_file(size, file_name);
+		if (!buffer)
+			exit_uart_app(EC_FILE_ERR);
+
+		printf("Write file %s at %d with %d bytes\n", file_name,
+		       flash_offset, size);
+		if (image_auto_write(flash_offset, buffer, size)) {
+			printf("Flash Done.\n");
+			free(buffer);
+			exit_uart_app(EC_OK);
+		}
+		free(buffer);
+		exit_uart_app(-1);
+	}
+
+	if (read_flash_flag) {
+		uint32_t flash_size;
+
+		if (get_flash_size(&flash_size)) {
+			printf("Read %d bytes from flash...\n", flash_size);
+			opr_read_mem(file_name, NPCX_FLASH_BASE_ADDR,
+				     flash_size);
+			exit_uart_app(EC_OK);
+		}
+
+		printf("Fail to read the flash size\n");
+		exit_uart_app(-1);
+	}
+
+	param_check_opr_num(opr_name);
+
+	/* Write buffer data to chosen address */
+	if (strcmp(opr_name, OPR_WRITE_MEM) == 0) {
+		addr = strtoull(addr_str, &stop_str, 0);
+
+		if (console) {
+			/*
+			 * Copy the input string to an auxiliary buffer, since
+			 * string is altered by param_get_str_size
+			 */
+			memcpy(aux_buf, file_name, sizeof(file_name));
+			/* Retrieve input size */
+			size = param_get_str_size(file_name);
+			/* Ensure non-zero size */
+			if (size == 0)
+				exit_uart_app(EC_FILE_ERR);
+			opr_write_mem((uint8_t *)(aux_buf), addr, size);
+		} else {
+			size = param_get_file_size(file_name);
+			if (size == 0)
+				exit_uart_app(EC_FILE_ERR);
+			buffer = read_input_file(size, file_name);
+			if (!buffer)
+				exit_uart_app(EC_FILE_ERR);
+			opr_write_mem(buffer, addr, size);
+			free(buffer);
+		}
+	} else if (strcmp(opr_name, OPR_READ_MEM) == 0) {
+		/* Read data to chosen address */
+
+		addr = strtoull(addr_str, &stop_str, 0);
+		size = strtoull(size_str, &stop_str, 0);
+
+		opr_read_mem(file_name, addr, size);
+	} else if (strcmp(opr_name, OPR_EXECUTE_EXIT) == 0) {
+		/* Execute From Address a non-return code */
+
+		addr = strtoull(addr_str, &stop_str, 0);
+
+		opr_execute_exit(addr);
+		exit_uart_app(EC_OK);
+	} else if (strcmp(opr_name, OPR_EXECUTE_CONT) == 0) {
+		/* Execute From Address a returnable code */
+
+		addr = strtoull(addr_str, &stop_str, 0);
+
+		opr_execute_return(addr);
+	} else {
+		exit_uart_app(EC_UNSUPPORTED_CMD_ERR);
+	}
+
+	exit_uart_app(EC_OK);
+	return 0;
+}
+
+/*---------------------------------------------------------------------------
+ * Function:	param_parse_cmd_line
+ *
+ * Parameters:		argc - Argument Count.
+ *			argv - Argument Vector.
+ * Returns:		None.
+ * Side effects:
+ * Description:
+ *		Parse command line parameters.
+ *---------------------------------------------------------------------------
+ */
+
+static const struct option long_opts[] = {
+	{ "version", 0, 0, 'v' },  { "help", 0, 0, 'h' },
+	{ "quiet", 0, 0, 'q' },	   { "console", 0, 0, 'c' },
+	{ "auto", 0, 0, 'A' },	   { "read-flash", 0, 0, 'r' },
+	{ "baudrate", 1, 0, 'b' }, { "opr", 1, 0, 'o' },
+	{ "port", 1, 0, 'p' },	   { "file", 1, 0, 'f' },
+	{ "addr", 1, 0, 'a' },	   { "size", 1, 0, 's' },
+	{ "offset", 1, 0, 'O' },   { NULL, 0, 0, 0 }
+};
+
+static const char *short_opts = "vhqcArb:o:p:f:a:s:O:?";
+
+static void param_parse_cmd_line(int argc, char *argv[])
+{
+	int opt, idx;
+
+	while ((opt = getopt_long(argc, argv, short_opts, long_opts, &idx)) !=
+	       -1) {
+		switch (opt) {
+		case 'v':
+			main_print_version();
+			exit(EC_OK);
+		case 'h':
+		case '?':
+			tool_usage();
+			opr_usage();
+			exit(EC_OK);
+		case 'q':
+			verbose = false;
+			break;
+		case 'c':
+			console = true;
+			break;
+		case 'A':
+			auto_mode = true;
+			break;
+		case 'r':
+			read_flash_flag = true;
+			break;
+		case 'b':
+			if (sscanf(optarg, "%du", &baudrate) == 0)
+				exit(EC_BAUDRATE_ERR);
+			break;
+		case 'o':
+			strncpy(opr_name, optarg, sizeof(opr_name));
+			opr_name[sizeof(opr_name) - 1] = '\0';
+			break;
+		case 'p':
+			strncpy(port_name, optarg, sizeof(port_name));
+			port_name[sizeof(port_name) - 1] = '\0';
+			break;
+		case 'f':
+			strncpy(file_name, optarg, sizeof(file_name));
+			file_name[sizeof(file_name) - 1] = '\0';
+			break;
+		case 'a':
+			strncpy(addr_str, optarg, sizeof(addr_str));
+			addr_str[sizeof(addr_str) - 1] = '\0';
+			break;
+		case 's':
+			strncpy(size_str, optarg, sizeof(size_str));
+			size_str[sizeof(size_str) - 1] = '\0';
+			break;
+		case 'O':
+			flash_offset = strtol(optarg, NULL, 0);
+			break;
+		}
+	}
+}
+
+/*---------------------------------------------------------------------------
+ * Function:	param_check_opr_num
+ *
+ * Parameters:	opr - Operation Number.
+ * Returns:	none.
+ * Side effects:
+ * Description:
+ *		Verify the validity of operation Number.
+ *---------------------------------------------------------------------------
+ */
+static void param_check_opr_num(const char *opr)
+{
+	if ((strcasecmp(opr, OPR_WRITE_MEM) != 0) &&
+	    (strcasecmp(opr, OPR_READ_MEM) != 0) &&
+	    (strcasecmp(opr, OPR_EXECUTE_EXIT) != 0) &&
+	    (strcasecmp(opr, OPR_EXECUTE_CONT) != 0)) {
+		display_color_msg(
+			FAIL,
+			"ERROR: Operation %s not supported, Supported "
+			"operations are %s, %s, %s & %s\n",
+			opr, OPR_WRITE_MEM, OPR_READ_MEM, OPR_EXECUTE_EXIT,
+			OPR_EXECUTE_CONT);
+		exit_uart_app(EC_OPR_MUM_ERR);
+	}
+}
+
+/*---------------------------------------------------------------------------
+ * Function:	param_get_file_size
+ *
+ * Parameters:	file_name - input file name.
+ * Returns:	size of file (in bytes).
+ * Side effects:
+ * Description:
+ *		Retrieve the size (in bytes) of a given file.
+ *--------------------------------------------------------------------------
+ */
+static uint32_t param_get_file_size(const char *file_name)
+{
+	struct stat fst;
+
+	if (stat(file_name, &fst)) {
+		display_color_msg(FAIL, "ERROR: Could not stat file [%s]\n",
+				  file_name);
+		return 0;
+	}
+	return fst.st_size;
+}
+
+/*---------------------------------------------------------------------------
+ * Function:	param_get_str_size
+ *
+ * Parameters:	string - input string.
+ * Returns:	size of double-words (in bytes).
+ * Side effects:
+ * Description:
+ *	Retrieve the size (in bytes) of double-word values in a given string.
+ *	E.g., given the string "1234 AB5678 FF", return 12 (for three
+ *	double-words).
+ *---------------------------------------------------------------------------
+ */
+static uint32_t param_get_str_size(char *string)
+{
+	uint32_t str_size = 0;
+	char seps[] = " ";
+	char *token = NULL;
+
+	/* Verify string is non-NULL */
+	if ((string == NULL) || (strlen(string) == 0)) {
+		display_color_msg(FAIL,
+				  "ERROR: Zero length input string provided\n");
+		return 0;
+	}
+
+	/* Read first token from string */
+	token = strtok(string, seps);
+
+	/* Loop while there are tokens in "string" */
+	while (token != NULL) {
+		str_size++;
+		token = strtok(NULL, seps);
+	}
+
+	/* Refer to each token as a double-word */
+	str_size *= sizeof(uint32_t);
+	return str_size;
+}
+
+/*--------------------------------------------------------------------------
+ * Function:	tool_usage
+ *
+ * Parameters:	none.
+ * Returns:	none.
+ * Side effects:
+ * Description:
+ *		Prints the console application help menu.
+ *--------------------------------------------------------------------------
+ */
+static void tool_usage(void)
+{
+	printf("%s version %s\n\n", tool_name, tool_version);
+	printf("General switches:\n");
+	printf("  -v, --version        - Print version\n");
+	printf("  -h, --help           - Help menu\n");
+	printf("  -q, --quiet          - Suppress verbose mode (default is "
+	       "verbose ON)\n");
+	printf("  -c, --console        - Print data to console (default is "
+	       "print to file)\n");
+	printf("  -p, --port <name>    - Serial port name (default is %s)\n",
+	       DEFAULT_PORT_NAME);
+	printf("  -b, --baudrate <num> - COM Port baud-rate (default is %d)\n",
+	       DEFAULT_BAUD_RATE);
+	printf("  -A, --auto           - Enable auto mode. (default is off)\n");
+	printf("  -O, --offset <num>   - With --auto, assign the offset of");
+	printf(" flash where the image to be written.\n");
+	printf("  -r, --read-flash     - With --file=<file>, Read the whole"
+	       " flash content and write it to <file>.\n");
+	printf("\n");
+	printf("Operation specific switches:\n");
+	printf("  -o, --opr   <name>   - Operation number (see list below)\n");
+	printf("  -f, --file  <name>   - Input/output file name\n");
+	printf("  -a, --addr  <num>    - Start memory address\n");
+	printf("  -s, --size  <num>    - Size of data to read\n");
+	printf("\n");
+}
+
+/*--------------------------------------------------------------------------
+ * Function:	main_print_version
+ *
+ * Parameters:	none
+ * Returns:	none
+ * Side effects:
+ * Description:
+ *		This routine prints the tool version
+ *--------------------------------------------------------------------------
+ */
+static void main_print_version(void)
+{
+	printf("%s version %s\n\n", tool_name, tool_version);
+}
+
+/*---------------------------------------------------------------------------
+ * Function:	exit_uart_app
+ *
+ * Parameters:	none.
+ * Returns:	none.
+ * Side effects:
+ * Description:
+ *		Exit "nicely" the application.
+ *---------------------------------------------------------------------------
+ */
+static void exit_uart_app(int32_t exit_status)
+{
+	if (opr_close_port() != true)
+		display_color_msg(FAIL, "ERROR: Port close failed.\n");
+
+	exit(exit_status);
+}
+
+/*---------------------------------------------------------------------------
+ * Function:	display_color_msg
+ *
+ * Parameters:
+ *		success - SUCCESS for successful message, FAIL for erroneous
+ *			  massage.
+ *		fmt     - Massage to dispaly (format and arguments).
+ *
+ * Returns:	none
+ * Side effects: Using DISPLAY_MSG macro.
+ * Description:
+ *		This routine displays a message using color attributes:
+ *		In case of a successful message, use green foreground text on
+ *		black background.
+ *		In case of an erroneous message, use red foreground text on
+ *		black background.
+ *---------------------------------------------------------------------------
+ */
+void display_color_msg(bool success, const char *fmt, ...)
+{
+	va_list argptr;
+
+	va_start(argptr, fmt);
+	vprintf(fmt, argptr);
+	va_end(argptr);
+}
diff --git a/util/uut/main.h b/util/uut/main.h
index 10c1391136..43c80dddae 100644
--- a/util/uut/main.h
+++ b/util/uut/main.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,11 +21,11 @@
 #define BASE_HEXADECIMAL 16
 
 /* Verbose control messages display */
-#define DISPLAY_MSG(msg) \
-{                        \
-	if (verbose)         \
-		printf msg;      \
-}
+#define DISPLAY_MSG(msg)            \
+	{                           \
+		if (verbose)        \
+			printf msg; \
+	}
 
 #define SUCCESS true
 #define FAIL false
@@ -65,7 +65,7 @@ extern bool console;
  *		black background.
  *--------------------------------------------------------------------------
  */
-void display_color_msg(bool success, char *fmt, ...);
+void display_color_msg(bool success, const char *fmt, ...);
 
 #ifdef __cplusplus
 }
diff --git a/util/uut/opr.c b/util/uut/opr.c
deleted file mode 100644
index bc60898ce4..0000000000
--- a/util/uut/opr.c
+++ /dev/null
@@ -1,549 +0,0 @@
-/*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* This file implements the UART console application operations. */
-#define _GNU_SOURCE
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <time.h>
-#include <unistd.h>
-
-#include "com_port.h"
-#include "cmd.h"
-#include "main.h"
-#include "misc_util.h"
-#include "opr.h"
-
-/*----------------------------------------------------------------------------
- * Global Variables
- *---------------------------------------------------------------------------
- */
-int port_handle = INVALID_HANDLE_VALUE;
-
-/*----------------------------------------------------------------------------
- * Constant definitions
- *---------------------------------------------------------------------------
- */
-#define MAX_PORT_NAME_SIZE 32
-#define OPR_TIMEOUT 10L		 /* 10  seconds */
-#define FLASH_ERASE_TIMEOUT 120L /* 120 seconds */
-
-#define STS_MSG_MIN_SIZE 8
-#define STS_MSG_APP_END 0x09
-
-#define MAX_SYNC_TRIALS 3
-
-/*----------------------------------------------------------------------------
- * Global variables
- *---------------------------------------------------------------------------
- */
-struct command_node cmd_buf[MAX_CMD_BUF_SIZE];
-uint8_t resp_buf[MAX_RESP_BUF_SIZE];
-
-/*---------------------------------------------------------------------------
- * Functions prototypes
- *---------------------------------------------------------------------------
- */
-static bool opr_send_cmds(struct command_node *cmd_buf, uint32_t cmd_num);
-
-/*----------------------------------------------------------------------------
- * Function implementation
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * Function:	opr_usage
- *
- * Parameters:	none.
- * Returns:	none.
- * Side effects:
- * Description:
- *		Prints the console application operation menu.
- *---------------------------------------------------------------------------
- */
-void opr_usage(void)
-{
-	printf("Operations:\n");
-	printf("       %s\t\t- Write To Memory/Flash\n", OPR_WRITE_MEM);
-	printf("       %s\t\t- Read From Memory/Flash\n", OPR_READ_MEM);
-	printf("       %s\t\t- Execute a non-return code\n", OPR_EXECUTE_EXIT);
-	printf("       %s\t\t- Execute a returnable code\n", OPR_EXECUTE_CONT);
-}
-
-/*----------------------------------------------------------------------------
- * Function:	opr_close_port
- *
- * Parameters:	none
- * Returns:
- * Side effects:
- * Description:
- *		This routine closes the opened COM port by the application
- *---------------------------------------------------------------------------
- */
-bool opr_close_port(void)
-{
-	return com_port_close(port_handle);
-}
-
-/*----------------------------------------------------------------------------
- * Function:        opr_open_port
- *
- * Parameters:	port_name - COM Port name.
- *		port_cfg - COM Port configuration structure.
- * Returns:	1 if successful, 0 in the case of an error.
- * Side effects:
- * Description:
- *		Open a specified ComPort device.
- *---------------------------------------------------------------------------
- */
-bool opr_open_port(const char *port_name, struct comport_fields port_cfg)
-{
-	char *full_port_name;
-
-	if (asprintf(&full_port_name, "/dev/%s", port_name) == -1)
-		return false;
-
-	if (port_handle > 0)
-		com_port_close(port_handle);
-
-	port_handle = com_port_open((const char *)full_port_name, port_cfg);
-
-	if (port_handle <= 0) {
-		display_color_msg(FAIL, "\nERROR: COM Port failed to open.\n");
-		DISPLAY_MSG(
-			("Please select the right serial port or check if "
-			 "other serial\n"));
-		DISPLAY_MSG(("communication applications are opened.\n"));
-		return false;
-	}
-
-	display_color_msg(SUCCESS, "Port %s Opened\n", full_port_name);
-
-	return true;
-}
-
-/*----------------------------------------------------------------------------
- * Function:	opr_write_chunk
- *
- * Parameters:
- *      buffer  - Input data buffer.
- *      addr    - Memory address to write to.
- *      size    - Data size to write.
- * Returns: true if successful, false in the case of an error.
- * Side effects:
- * Description:
- *   Write data to RAM, starting from the given  address (addr).
- *   Data size is limited to the max chunk size (256 bytes).
- *---------------------------------------------------------------------------
- */
-bool opr_write_chunk(uint8_t *buffer, uint32_t addr, uint32_t size)
-{
-	struct command_node wr_cmd_buf;
-
-	if (size > MAX_RW_DATA_SIZE) {
-		display_color_msg(FAIL,
-			"ERROR: Block cannot exceed %d\n", MAX_RW_DATA_SIZE);
-	}
-	/* Initialize response size */
-	wr_cmd_buf.resp_size = 1;
-	cmd_create_write(addr, size, buffer,
-			wr_cmd_buf.cmd, &wr_cmd_buf.cmd_size);
-	return opr_send_cmds(&wr_cmd_buf, 1);
-}
-
-/*----------------------------------------------------------------------------
- * Function:	opr_read_chunk
- *
- * Parameters:
- *      buffer  - Data read buffer.
- *      addr    - Memory address to read from.
- *      size    - Data size to read.
- * Returns: true if successful, false in the case of an error.
- * Side effects:
- * Description:
- *   Read data from RAM, starting from the given  address (addr).
- *   Data size is limited to the max chunk size (256 bytes).
- *---------------------------------------------------------------------------
- */
-bool opr_read_chunk(uint8_t *buffer, uint32_t addr, uint32_t size)
-{
-	struct command_node rd_cmd_buf;
-
-	if (size > MAX_RW_DATA_SIZE) {
-		display_color_msg(FAIL,
-			"ERROR: Block cannot exceed %d\n", MAX_RW_DATA_SIZE);
-		return false;
-	}
-
-	cmd_create_read(addr, ((uint8_t)size - 1),
-					rd_cmd_buf.cmd, &rd_cmd_buf.cmd_size);
-	rd_cmd_buf.resp_size = size + 3;
-	if (opr_send_cmds(&rd_cmd_buf, 1)) {
-		if (resp_buf[0] == (uint8_t)(UFPP_READ_CMD)) {
-			memcpy(buffer, &resp_buf[1], size);
-			return true;
-		}
-	}
-	return false;
-}
-/*----------------------------------------------------------------------------
- * Function:	opr_write_mem
- *
- * Parameters:	input	- Input (file-name/console), containing data to write.
- *		addr	- Memory address to write to.
- *		size	- Data size to write.
- * Returns:	none.
- * Side effects:
- * Description:
- *	Write data to memory, starting from a given address.
- *	Memory may be Flash (SPI), DRAM (DDR) or SRAM.
- *	The data is retrieved either from an input file or from a console.
- *	Data size is not limited.
- *	Data is sent in 256 bytes chunks (file mode) or 4 bytes chunks
- *	(console mode).
- *---------------------------------------------------------------------------
- */
-void opr_write_mem(uint8_t *buffer, uint32_t addr, uint32_t size)
-{
-	uint32_t cur_addr = addr;
-	uint8_t data_buf[256];
-	uint32_t write_size, size_remain;
-	uint32_t cmd_idx = 1;
-	char seps[] = " ";
-	char *token = NULL;
-	char *stop_str;
-	uint32_t block_size = (console) ? sizeof(uint32_t) : MAX_RW_DATA_SIZE;
-	struct command_node wr_cmd_buf;
-
-	/* Initialize response size */
-	wr_cmd_buf.resp_size = 1;
-
-	DISPLAY_MSG(("Writing [%d] bytes in [%d] packets\n", size,
-		((size + (block_size - 1)) / block_size)));
-
-	/* Read first token from string */
-	if (console)
-		token = strtok(buffer, seps);
-
-	size_remain = size;
-	/* Main write loop */
-	while (true) {
-		if (console) {
-			/*
-			 * Invert token to double-word and insert the value to
-			 * data buffer
-			 */
-			(*(uint32_t *)data_buf) =
-				strtoul(token, &stop_str, BASE_HEXADECIMAL);
-
-			/* Prepare the next iteration */
-			token = strtok(NULL, seps);
-		}
-		write_size = (size_remain > block_size) ?
-					block_size : size_remain;
-		if (console) {
-			cmd_create_write(cur_addr, write_size, data_buf,
-					wr_cmd_buf.cmd, &wr_cmd_buf.cmd_size);
-		} else {
-			cmd_create_write(cur_addr, write_size, buffer,
-					wr_cmd_buf.cmd, &wr_cmd_buf.cmd_size);
-			buffer += write_size;
-		}
-		if (opr_send_cmds(&wr_cmd_buf, 1) != true)
-			break;
-
-		cmd_disp_write(resp_buf, write_size, cmd_idx,
-			((size + (block_size - 1)) / block_size));
-		cur_addr += write_size;
-		size_remain -= write_size;
-		cmd_idx++;
-		if (size_remain == 0)
-			break;
-	}
-
-	DISPLAY_MSG(("\n"));
-}
-
-/*----------------------------------------------------------------------------
- * Function:	opr_read_mem
- *
- * Parameters:	output - Output file name, containing data that was read.
- *		addr   - Memory address to read from.
- *		size   - Data size to read.
- * Returns:	none.
- * Side effects:
- * Description:
- *		Read data from memory, starting from a given address.
- *		Memory may be Flash (SPI), DRAM (DDR) or SRAM.
- *		The data is written into an output file, data size is limited
- *		as specified.
- *		Data is received in 256 bytes chunks.
- *---------------------------------------------------------------------------
- */
-void opr_read_mem(char *output, uint32_t addr, uint32_t size)
-{
-	FILE *output_file_id = NULL;
-	uint32_t cur_addr;
-	uint32_t bytes_left;
-	uint32_t read_size;
-	uint32_t cmd_idx = 1;
-	struct command_node rd_cmd_buf;
-
-	if (!console) {
-		output_file_id = fopen(output, "w+b");
-
-		if (output_file_id == NULL) {
-			display_color_msg(FAIL,
-				"ERROR: could not open output file [%s]\n",
-				output);
-			return;
-		}
-	}
-
-	DISPLAY_MSG(("Reading [%d] bytes in [%d] packets\n", size,
-		((size + (MAX_RW_DATA_SIZE - 1)) / MAX_RW_DATA_SIZE)));
-
-	for (cur_addr = addr; cur_addr < (addr + size);
-		cur_addr += MAX_RW_DATA_SIZE) {
-		bytes_left = (uint32_t)(addr + size - cur_addr);
-		read_size = MIN(bytes_left, MAX_RW_DATA_SIZE);
-
-		cmd_create_read(cur_addr, ((uint8_t)read_size - 1),
-					rd_cmd_buf.cmd, &rd_cmd_buf.cmd_size);
-		rd_cmd_buf.resp_size = read_size + 3;
-
-		if (opr_send_cmds(&rd_cmd_buf, 1) != true)
-			break;
-
-		cmd_disp_read(resp_buf, read_size, cmd_idx,
-			((size + (MAX_RW_DATA_SIZE - 1)) / MAX_RW_DATA_SIZE));
-
-		if (console)
-			cmd_disp_data((resp_buf + 1), read_size);
-		else
-			fwrite((resp_buf + 1), 1, read_size, output_file_id);
-
-		cmd_idx++;
-	}
-
-	DISPLAY_MSG(("\n"));
-	if (!console)
-		fclose(output_file_id);
-}
-
-/*----------------------------------------------------------------------------
- * Function:	opr_execute_exit
- *
- * Parameters:	addr - Start address to execute from.
- * Returns:	none.
- * Side effects:	ROM-Code is not in UART command mode anymore.
- * Description:
- *	Execute code starting from a given address.
- *	Memory address may be in Flash (SPI), DRAM (DDR) or SRAM.
- *	No further communication with thr ROM-Code is expected at this point.
- *---------------------------------------------------------------------------
- */
-void opr_execute_exit(uint32_t addr)
-{
-	uint32_t cmd_num;
-
-	cmd_build_exec_exit(addr, cmd_buf, &cmd_num);
-	if (opr_send_cmds(cmd_buf, cmd_num) != true)
-		return;
-
-	cmd_disp_exec_exit(resp_buf);
-}
-
-/*----------------------------------------------------------------------------
- * Function:	opr_execute_return
- *
- * Parameters:	addr - Start address to execute from.
- * Returns:	true if successful, false in the case of an error.
- * Side effects:
- * Description:
- *  Execute code starting from the given address and then check the result.
- *  The executed code should return with the execution result.
- *---------------------------------------------------------------------------
- */
-bool opr_execute_return(uint32_t addr)
-{
-	uint32_t cmd_num;
-
-	cmd_build_exec_ret(addr, cmd_buf, &cmd_num);
-	if (opr_send_cmds(cmd_buf, cmd_num) != true)
-		return false;
-
-	/*
-	 * Check the response command code is UFPP_FCALL_RSLT_CMD and
-	 * the return value from monitor is 0x03. (program finish and verify ok)
-	 */
-	if (resp_buf[1] != (uint8_t)(UFPP_FCALL_RSLT_CMD)
-					|| resp_buf[2] != 0x03)
-		return false;
-	return true;
-}
-
-/*----------------------------------------------------------------------------
- * Function:	opr_check_sync
- *
- * Parameters:
- *		baudrate - baud rate to check
- *
- * Returns:
- * Side effects:
- * Description:
- *	Checks whether the Host and the Core are synchoronized in the
- *	specified baud rate
- *---------------------------------------------------------------------------
- */
-enum sync_result opr_check_sync(uint32_t baudrate)
-{
-	uint32_t cmd_num;
-	struct command_node *cur_cmd = cmd_buf;
-	uint32_t bytes_read = 0;
-	uint32_t i;
-
-	port_cfg.baudrate = baudrate;
-	if (!com_config_uart(port_handle, port_cfg))
-		return SR_ERROR;
-
-	cmd_build_sync(cmd_buf, &cmd_num);
-
-	if (!com_port_write_bin(port_handle, cur_cmd->cmd, cur_cmd->cmd_size))
-		return SR_ERROR;
-
-	/* Allow several SYNC trials */
-	for (i = 0; i < MAX_SYNC_TRIALS; i++) {
-		bytes_read = com_port_read_bin(port_handle, resp_buf, 1);
-
-		/* Quit if succeeded to read a response */
-		if (bytes_read == 1)
-			break;
-		/* Otherwise give the ROM-Code time to answer */
-		sleep(1);
-	}
-
-	if (bytes_read == 0)
-		/*
-		 * Unable to read a response from ROM-Code in a reasonable
-		 * time
-		 */
-		return SR_TIMEOUT;
-
-	if (resp_buf[0] != (uint8_t)(UFPP_D2H_SYNC_CMD))
-		/* ROM-Code response is not as expected */
-		return SR_WRONG_DATA;
-
-	/* Good response */
-	return SR_OK;
-}
-
-/*----------------------------------------------------------------------------
- * Function:	opr_scan_baudrate
- *
- * Parameters:	none
- * Returns:
- * Side effects:
- * Description:
- *		Scans the baud rate range by sending sync request to the core
- *		and prints the response
- *---------------------------------------------------------------------------
- */
-bool opr_scan_baudrate(void)
-{
-	uint32_t baud = 0;
-	uint32_t step;
-	enum sync_result sr;
-	bool synched = false;
-	bool data_received = false;
-
-	/* Scan with HUGE STEPS */
-	/* BR_BIG_STEP is percents */
-	step = (BR_LOW_LIMIT * BR_BIG_STEP) / 100;
-	for (baud = BR_LOW_LIMIT; baud < BR_HIGH_LIMIT; baud += step) {
-		sr = opr_check_sync(baud);
-		step = (baud * BR_BIG_STEP) / 100;
-		if (sr == SR_OK) {
-			printf("SR_OK: Baud rate - %d, resp_buf - 0x%x\n",
-				baud, resp_buf[0]);
-			synched = true;
-			step = (baud * BR_SMALL_STEP) / 100;
-		} else if (sr == SR_WRONG_DATA) {
-			printf("SR_WRONG_DATA: Baud rate - %d, resp_buf - "
-			       "0x%x\n", baud, resp_buf[0]);
-			data_received = true;
-			step = (baud * BR_MEDIUM_STEP) / 100;
-		} else if (sr == SR_TIMEOUT) {
-			printf("SR_TIMEOUT: Baud rate - %d, resp_buf - 0x%x\n",
-				baud, resp_buf[0]);
-
-			if (synched || data_received)
-				break;
-		} else if (sr == SR_ERROR) {
-			printf("SR_ERROR: Baud rate - %d, resp_buf - 0x%x\n",
-				baud, resp_buf[0]);
-			if (synched || data_received)
-				break;
-		} else
-			printf("Unknown error code: Baud rate - %d, resp_buf - "
-				"0x%x\n", baud, resp_buf[0]);
-	}
-
-	return true;
-}
-
-/*----------------------------------------------------------------------------
- * Function:	opr_send_cmds
- *
- * Parameters:	cmd_buf - Pointer to a Command Buffer.
- *		cmd_num - Number of commands to send.
- * Returns:	1 if successful, 0 in the case of an error.
- * Side effects:
- * Description:
- *	Send a group of commands through COM port.
- *	A command is sent only after a valid response for the previous command
- *	was received.
- *---------------------------------------------------------------------------
- */
-static bool opr_send_cmds(struct command_node *cmd_buf, uint32_t cmd_num)
-{
-	struct command_node *cur_cmd = cmd_buf;
-	uint32_t cmd;
-	uint32_t read;
-	time_t start;
-	double elapsed_time;
-
-	for (cmd = 0; cmd < cmd_num; cmd++, cur_cmd++) {
-		if (com_port_write_bin(port_handle, cur_cmd->cmd,
-						cur_cmd->cmd_size) == true) {
-			time(&start);
-
-			do {
-				read = com_port_wait_read(port_handle);
-				elapsed_time = difftime(time(NULL), start);
-			} while ((read < cur_cmd->resp_size) &&
-				 (elapsed_time <= OPR_TIMEOUT));
-			com_port_read_bin(port_handle, resp_buf,
-							cur_cmd->resp_size);
-
-			if (elapsed_time > OPR_TIMEOUT)
-				display_color_msg(FAIL,
-					"ERROR: [%d] bytes received for read, "
-					"[%d] bytes are expected\n",
-					read, cur_cmd->resp_size);
-		} else {
-			display_color_msg(FAIL,
-				"ERROR: Failed to send Command number %d\n",
-				cmd);
-			return false;
-		}
-	}
-
-	return true;
-}
-
diff --git a/util/uut/opr.cc b/util/uut/opr.cc
new file mode 100644
index 0000000000..b52eb880bb
--- /dev/null
+++ b/util/uut/opr.cc
@@ -0,0 +1,558 @@
+/*
+ * Copyright 2018 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* This file implements the UART console application operations. */
+
+#ifndef _GNU_SOURCE
+#define _GNU_SOURCE /* for asprintf */
+#endif
+
+#include "cmd.h"
+#include "com_port.h"
+#include "main.h"
+#include "misc_util.h"
+#include "opr.h"
+
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <time.h>
+
+#include <unistd.h>
+
+/*----------------------------------------------------------------------------
+ * Global Variables
+ *---------------------------------------------------------------------------
+ */
+int port_handle = INVALID_HANDLE_VALUE;
+
+/*----------------------------------------------------------------------------
+ * Constant definitions
+ *---------------------------------------------------------------------------
+ */
+#define MAX_PORT_NAME_SIZE 32
+#define OPR_TIMEOUT 10L /* 10  seconds */
+#define FLASH_ERASE_TIMEOUT 120L /* 120 seconds */
+
+#define STS_MSG_MIN_SIZE 8
+#define STS_MSG_APP_END 0x09
+
+#define MAX_SYNC_TRIALS 3
+
+/*----------------------------------------------------------------------------
+ * Global variables
+ *---------------------------------------------------------------------------
+ */
+struct command_node cmd_buf[MAX_CMD_BUF_SIZE];
+uint8_t resp_buf[MAX_RESP_BUF_SIZE];
+
+/*---------------------------------------------------------------------------
+ * Functions prototypes
+ *---------------------------------------------------------------------------
+ */
+static bool opr_send_cmds(struct command_node *cmd_buf, uint32_t cmd_num);
+
+/*----------------------------------------------------------------------------
+ * Function implementation
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ * Function:	opr_usage
+ *
+ * Parameters:	none.
+ * Returns:	none.
+ * Side effects:
+ * Description:
+ *		Prints the console application operation menu.
+ *---------------------------------------------------------------------------
+ */
+void opr_usage(void)
+{
+	printf("Operations:\n");
+	printf("       %s\t\t- Write To Memory/Flash\n", OPR_WRITE_MEM);
+	printf("       %s\t\t- Read From Memory/Flash\n", OPR_READ_MEM);
+	printf("       %s\t\t- Execute a non-return code\n", OPR_EXECUTE_EXIT);
+	printf("       %s\t\t- Execute a returnable code\n", OPR_EXECUTE_CONT);
+}
+
+/*----------------------------------------------------------------------------
+ * Function:	opr_close_port
+ *
+ * Parameters:	none
+ * Returns:
+ * Side effects:
+ * Description:
+ *		This routine closes the opened COM port by the application
+ *---------------------------------------------------------------------------
+ */
+bool opr_close_port(void)
+{
+	return com_port_close(port_handle);
+}
+
+/*----------------------------------------------------------------------------
+ * Function:        opr_open_port
+ *
+ * Parameters:	port_name - COM Port name.
+ *		port_cfg - COM Port configuration structure.
+ * Returns:	1 if successful, 0 in the case of an error.
+ * Side effects:
+ * Description:
+ *		Open a specified ComPort device.
+ *---------------------------------------------------------------------------
+ */
+bool opr_open_port(const char *port_name, struct comport_fields port_cfg)
+{
+	char *full_port_name;
+
+	if (asprintf(&full_port_name, "/dev/%s", port_name) == -1)
+		return false;
+
+	if (port_handle > 0)
+		com_port_close(port_handle);
+
+	port_handle = com_port_open((const char *)full_port_name, port_cfg);
+
+	if (port_handle <= 0) {
+		display_color_msg(FAIL, "\nERROR: COM Port failed to open.\n");
+		DISPLAY_MSG(("Please select the right serial port or check if "
+			     "other serial\n"));
+		DISPLAY_MSG(("communication applications are opened.\n"));
+		return false;
+	}
+
+	display_color_msg(SUCCESS, "Port %s Opened\n", full_port_name);
+
+	return true;
+}
+
+/*----------------------------------------------------------------------------
+ * Function:	opr_write_chunk
+ *
+ * Parameters:
+ *      buffer  - Input data buffer.
+ *      addr    - Memory address to write to.
+ *      size    - Data size to write.
+ * Returns: true if successful, false in the case of an error.
+ * Side effects:
+ * Description:
+ *   Write data to RAM, starting from the given  address (addr).
+ *   Data size is limited to the max chunk size (256 bytes).
+ *---------------------------------------------------------------------------
+ */
+bool opr_write_chunk(uint8_t *buffer, uint32_t addr, uint32_t size)
+{
+	struct command_node wr_cmd_buf;
+
+	if (size > MAX_RW_DATA_SIZE) {
+		display_color_msg(FAIL, "ERROR: Block cannot exceed %d\n",
+				  MAX_RW_DATA_SIZE);
+	}
+	/* Initialize response size */
+	wr_cmd_buf.resp_size = 1;
+	cmd_create_write(addr, size, buffer, wr_cmd_buf.cmd,
+			 &wr_cmd_buf.cmd_size);
+	return opr_send_cmds(&wr_cmd_buf, 1);
+}
+
+/*----------------------------------------------------------------------------
+ * Function:	opr_read_chunk
+ *
+ * Parameters:
+ *      buffer  - Data read buffer.
+ *      addr    - Memory address to read from.
+ *      size    - Data size to read.
+ * Returns: true if successful, false in the case of an error.
+ * Side effects:
+ * Description:
+ *   Read data from RAM, starting from the given  address (addr).
+ *   Data size is limited to the max chunk size (256 bytes).
+ *---------------------------------------------------------------------------
+ */
+bool opr_read_chunk(uint8_t *buffer, uint32_t addr, uint32_t size)
+{
+	struct command_node rd_cmd_buf;
+
+	if (size > MAX_RW_DATA_SIZE) {
+		display_color_msg(FAIL, "ERROR: Block cannot exceed %d\n",
+				  MAX_RW_DATA_SIZE);
+		return false;
+	}
+
+	cmd_create_read(addr, ((uint8_t)size - 1), rd_cmd_buf.cmd,
+			&rd_cmd_buf.cmd_size);
+	rd_cmd_buf.resp_size = size + 3;
+	if (opr_send_cmds(&rd_cmd_buf, 1)) {
+		if (resp_buf[0] == (uint8_t)(UFPP_READ_CMD)) {
+			memcpy(buffer, &resp_buf[1], size);
+			return true;
+		}
+	}
+	return false;
+}
+/*----------------------------------------------------------------------------
+ * Function:	opr_write_mem
+ *
+ * Parameters:	input	- Input (file-name/console), containing data to write.
+ *		addr	- Memory address to write to.
+ *		size	- Data size to write.
+ * Returns:	none.
+ * Side effects:
+ * Description:
+ *	Write data to memory, starting from a given address.
+ *	Memory may be Flash (SPI), DRAM (DDR) or SRAM.
+ *	The data is retrieved either from an input file or from a console.
+ *	Data size is not limited.
+ *	Data is sent in 256 bytes chunks (file mode) or 4 bytes chunks
+ *	(console mode).
+ *---------------------------------------------------------------------------
+ */
+void opr_write_mem(uint8_t *buffer, uint32_t addr, uint32_t size)
+{
+	uint32_t cur_addr = addr;
+	uint8_t data_buf[256];
+	uint32_t write_size, size_remain;
+	uint32_t cmd_idx = 1;
+	char seps[] = " ";
+	char *token = NULL;
+	char *stop_str;
+	uint32_t block_size = (console) ? sizeof(uint32_t) : MAX_RW_DATA_SIZE;
+	struct command_node wr_cmd_buf;
+
+	/* Initialize response size */
+	wr_cmd_buf.resp_size = 1;
+
+	DISPLAY_MSG(("Writing [%d] bytes in [%d] packets\n", size,
+		     ((size + (block_size - 1)) / block_size)));
+
+	/* Read first token from string */
+	if (console)
+		token = strtok((char *)(buffer), seps);
+
+	size_remain = size;
+	/* Main write loop */
+	while (true) {
+		if (console) {
+			/*
+			 * Invert token to double-word and insert the value to
+			 * data buffer
+			 */
+			(*(uint32_t *)data_buf) =
+				strtoull(token, &stop_str, BASE_HEXADECIMAL);
+
+			/* Prepare the next iteration */
+			token = strtok(NULL, seps);
+		}
+		write_size = (size_remain > block_size) ? block_size :
+							  size_remain;
+		if (console) {
+			cmd_create_write(cur_addr, write_size, data_buf,
+					 wr_cmd_buf.cmd, &wr_cmd_buf.cmd_size);
+		} else {
+			cmd_create_write(cur_addr, write_size, buffer,
+					 wr_cmd_buf.cmd, &wr_cmd_buf.cmd_size);
+			buffer += write_size;
+		}
+		if (opr_send_cmds(&wr_cmd_buf, 1) != true)
+			break;
+
+		cmd_disp_write(resp_buf, write_size, cmd_idx,
+			       ((size + (block_size - 1)) / block_size));
+		cur_addr += write_size;
+		size_remain -= write_size;
+		cmd_idx++;
+		if (size_remain == 0)
+			break;
+	}
+
+	DISPLAY_MSG(("\n"));
+}
+
+/*----------------------------------------------------------------------------
+ * Function:	opr_read_mem
+ *
+ * Parameters:	output - Output file name, containing data that was read.
+ *		addr   - Memory address to read from.
+ *		size   - Data size to read.
+ * Returns:	none.
+ * Side effects:
+ * Description:
+ *		Read data from memory, starting from a given address.
+ *		Memory may be Flash (SPI), DRAM (DDR) or SRAM.
+ *		The data is written into an output file, data size is limited
+ *		as specified.
+ *		Data is received in 256 bytes chunks.
+ *---------------------------------------------------------------------------
+ */
+void opr_read_mem(char *output, uint32_t addr, uint32_t size)
+{
+	FILE *output_file_id = NULL;
+	uint32_t cur_addr;
+	uint32_t bytes_left;
+	uint32_t read_size;
+	uint32_t cmd_idx = 1;
+	struct command_node rd_cmd_buf;
+
+	if (!console) {
+		output_file_id = fopen(output, "w+b");
+
+		if (output_file_id == NULL) {
+			display_color_msg(
+				FAIL,
+				"ERROR: could not open output file [%s]\n",
+				output);
+			return;
+		}
+	}
+
+	DISPLAY_MSG(("Reading [%d] bytes in [%d] packets\n", size,
+		     ((size + (MAX_RW_DATA_SIZE - 1)) / MAX_RW_DATA_SIZE)));
+
+	for (cur_addr = addr; cur_addr < (addr + size);
+	     cur_addr += MAX_RW_DATA_SIZE) {
+		bytes_left = (uint32_t)(addr + size - cur_addr);
+		read_size = MIN(bytes_left, MAX_RW_DATA_SIZE);
+
+		cmd_create_read(cur_addr, ((uint8_t)read_size - 1),
+				rd_cmd_buf.cmd, &rd_cmd_buf.cmd_size);
+		rd_cmd_buf.resp_size = read_size + 3;
+
+		if (opr_send_cmds(&rd_cmd_buf, 1) != true)
+			break;
+
+		cmd_disp_read(
+			resp_buf, read_size, cmd_idx,
+			((size + (MAX_RW_DATA_SIZE - 1)) / MAX_RW_DATA_SIZE));
+
+		if (console)
+			cmd_disp_data((resp_buf + 1), read_size);
+		else
+			fwrite((resp_buf + 1), 1, read_size, output_file_id);
+
+		cmd_idx++;
+	}
+
+	DISPLAY_MSG(("\n"));
+	if (!console)
+		fclose(output_file_id);
+}
+
+/*----------------------------------------------------------------------------
+ * Function:	opr_execute_exit
+ *
+ * Parameters:	addr - Start address to execute from.
+ * Returns:	none.
+ * Side effects:	ROM-Code is not in UART command mode anymore.
+ * Description:
+ *	Execute code starting from a given address.
+ *	Memory address may be in Flash (SPI), DRAM (DDR) or SRAM.
+ *	No further communication with thr ROM-Code is expected at this point.
+ *---------------------------------------------------------------------------
+ */
+void opr_execute_exit(uint32_t addr)
+{
+	uint32_t cmd_num;
+
+	cmd_build_exec_exit(addr, cmd_buf, &cmd_num);
+	if (opr_send_cmds(cmd_buf, cmd_num) != true)
+		return;
+
+	cmd_disp_exec_exit(resp_buf);
+}
+
+/*----------------------------------------------------------------------------
+ * Function:	opr_execute_return
+ *
+ * Parameters:	addr - Start address to execute from.
+ * Returns:	true if successful, false in the case of an error.
+ * Side effects:
+ * Description:
+ *  Execute code starting from the given address and then check the result.
+ *  The executed code should return with the execution result.
+ *---------------------------------------------------------------------------
+ */
+bool opr_execute_return(uint32_t addr)
+{
+	uint32_t cmd_num;
+
+	cmd_build_exec_ret(addr, cmd_buf, &cmd_num);
+	if (opr_send_cmds(cmd_buf, cmd_num) != true)
+		return false;
+
+	/*
+	 * Check the response command code is UFPP_FCALL_RSLT_CMD and
+	 * the return value from monitor is 0x03. (program finish and verify ok)
+	 */
+	if (resp_buf[1] != (uint8_t)(UFPP_FCALL_RSLT_CMD) ||
+	    resp_buf[2] != 0x03)
+		return false;
+	return true;
+}
+
+/*----------------------------------------------------------------------------
+ * Function:	opr_check_sync
+ *
+ * Parameters:
+ *		baudrate - baud rate to check
+ *
+ * Returns:
+ * Side effects:
+ * Description:
+ *	Checks whether the Host and the Core are synchoronized in the
+ *	specified baud rate
+ *---------------------------------------------------------------------------
+ */
+enum sync_result opr_check_sync(uint32_t baudrate)
+{
+	uint32_t cmd_num;
+	struct command_node *cur_cmd = cmd_buf;
+	uint32_t bytes_read = 0;
+	uint32_t i;
+
+	port_cfg.baudrate = baudrate;
+	if (!com_config_uart(port_handle, port_cfg))
+		return SR_ERROR;
+
+	cmd_build_sync(cmd_buf, &cmd_num);
+
+	if (!com_port_write_bin(port_handle, cur_cmd->cmd, cur_cmd->cmd_size))
+		return SR_ERROR;
+
+	/* Allow several SYNC trials */
+	for (i = 0; i < MAX_SYNC_TRIALS; i++) {
+		bytes_read = com_port_read_bin(port_handle, resp_buf, 1);
+
+		/* Quit if succeeded to read a response */
+		if (bytes_read == 1)
+			break;
+		/* Otherwise give the ROM-Code time to answer */
+		sleep(1);
+	}
+
+	if (bytes_read == 0)
+		/*
+		 * Unable to read a response from ROM-Code in a reasonable
+		 * time
+		 */
+		return SR_TIMEOUT;
+
+	if (resp_buf[0] != (uint8_t)(UFPP_D2H_SYNC_CMD))
+		/* ROM-Code response is not as expected */
+		return SR_WRONG_DATA;
+
+	/* Good response */
+	return SR_OK;
+}
+
+/*----------------------------------------------------------------------------
+ * Function:	opr_scan_baudrate
+ *
+ * Parameters:	none
+ * Returns:
+ * Side effects:
+ * Description:
+ *		Scans the baud rate range by sending sync request to the core
+ *		and prints the response
+ *---------------------------------------------------------------------------
+ */
+bool opr_scan_baudrate(void)
+{
+	uint32_t baud = 0;
+	uint32_t step;
+	enum sync_result sr;
+	bool synched = false;
+	bool data_received = false;
+
+	/* Scan with HUGE STEPS */
+	/* BR_BIG_STEP is percents */
+	step = (BR_LOW_LIMIT * BR_BIG_STEP) / 100;
+	for (baud = BR_LOW_LIMIT; baud < BR_HIGH_LIMIT; baud += step) {
+		sr = opr_check_sync(baud);
+		step = (baud * BR_BIG_STEP) / 100;
+		if (sr == SR_OK) {
+			printf("SR_OK: Baud rate - %d, resp_buf - 0x%x\n", baud,
+			       resp_buf[0]);
+			synched = true;
+			step = (baud * BR_SMALL_STEP) / 100;
+		} else if (sr == SR_WRONG_DATA) {
+			printf("SR_WRONG_DATA: Baud rate - %d, resp_buf - "
+			       "0x%x\n",
+			       baud, resp_buf[0]);
+			data_received = true;
+			step = (baud * BR_MEDIUM_STEP) / 100;
+		} else if (sr == SR_TIMEOUT) {
+			printf("SR_TIMEOUT: Baud rate - %d, resp_buf - 0x%x\n",
+			       baud, resp_buf[0]);
+
+			if (synched || data_received)
+				break;
+		} else if (sr == SR_ERROR) {
+			printf("SR_ERROR: Baud rate - %d, resp_buf - 0x%x\n",
+			       baud, resp_buf[0]);
+			if (synched || data_received)
+				break;
+		} else
+			printf("Unknown error code: Baud rate - %d, resp_buf - "
+			       "0x%x\n",
+			       baud, resp_buf[0]);
+	}
+
+	return true;
+}
+
+/*----------------------------------------------------------------------------
+ * Function:	opr_send_cmds
+ *
+ * Parameters:	cmd_buf - Pointer to a Command Buffer.
+ *		cmd_num - Number of commands to send.
+ * Returns:	1 if successful, 0 in the case of an error.
+ * Side effects:
+ * Description:
+ *	Send a group of commands through COM port.
+ *	A command is sent only after a valid response for the previous command
+ *	was received.
+ *---------------------------------------------------------------------------
+ */
+static bool opr_send_cmds(struct command_node *cmd_buf, uint32_t cmd_num)
+{
+	struct command_node *cur_cmd = cmd_buf;
+	uint32_t cmd;
+	uint32_t read;
+	time_t start;
+	double elapsed_time;
+
+	for (cmd = 0; cmd < cmd_num; cmd++, cur_cmd++) {
+		if (com_port_write_bin(port_handle, cur_cmd->cmd,
+				       cur_cmd->cmd_size) == true) {
+			time(&start);
+
+			do {
+				read = com_port_wait_read(port_handle);
+				elapsed_time = difftime(time(NULL), start);
+			} while ((read < cur_cmd->resp_size) &&
+				 (elapsed_time <= OPR_TIMEOUT));
+			com_port_read_bin(port_handle, resp_buf,
+					  cur_cmd->resp_size);
+
+			if (elapsed_time > OPR_TIMEOUT)
+				display_color_msg(
+					FAIL,
+					"ERROR: [%d] bytes received for read, "
+					"[%d] bytes are expected\n",
+					read, cur_cmd->resp_size);
+		} else {
+			display_color_msg(
+				FAIL,
+				"ERROR: Failed to send Command number %d\n",
+				cmd);
+			return false;
+		}
+	}
+
+	return true;
+}
diff --git a/util/uut/opr.h b/util/uut/opr.h
index 3b166f0c7e..820639d6a1 100644
--- a/util/uut/opr.h
+++ b/util/uut/opr.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,16 +15,16 @@
  */
 
 /* Baud rate scan steps: */
-#define BR_BIG_STEP 20       /* in percents from current baud rate */
-#define BR_MEDIUM_STEP 10    /* in percents from current baud rate */
-#define BR_SMALL_STEP 1      /* in percents from current baud rate */
-#define BR_MIN_STEP 5        /* in absolute baud rate units */
-#define BR_LOW_LIMIT 400     /* Automatic BR detection starts at this value */
+#define BR_BIG_STEP 20 /* in percents from current baud rate */
+#define BR_MEDIUM_STEP 10 /* in percents from current baud rate */
+#define BR_SMALL_STEP 1 /* in percents from current baud rate */
+#define BR_MIN_STEP 5 /* in absolute baud rate units */
+#define BR_LOW_LIMIT 400 /* Automatic BR detection starts at this value */
 #define BR_HIGH_LIMIT 150000 /* Automatic BR detection ends at this value */
 
-#define OPR_WRITE_MEM "wr"      /* Write To Memory/Flash */
-#define OPR_READ_MEM "rd"       /* Read From Memory/Flash */
-#define OPR_EXECUTE_EXIT "go"   /* Execute a non-return code */
+#define OPR_WRITE_MEM "wr" /* Write To Memory/Flash */
+#define OPR_READ_MEM "rd" /* Read From Memory/Flash */
+#define OPR_EXECUTE_EXIT "go" /* Execute a non-return code */
 #define OPR_EXECUTE_CONT "call" /* Execute returnable code */
 
 enum sync_result {
diff --git a/util/volteer-relevant-paths.txt b/util/volteer-relevant-paths.txt
new file mode 100644
index 0000000000..a45c44dcf6
--- /dev/null
+++ b/util/volteer-relevant-paths.txt
@@ -0,0 +1,15 @@
+# Here you can place files of interest to be included in the commit message for
+# merge commits to firmware-volteer-13672.B-main
+chip/npcx/*npcx7*
+driver/accel_bma2x2.*
+driver/accelgyro_bmi260.*
+driver/als_tcs3400.*
+driver/bc12/piusb9201.*
+driver/charger/isl9241.*
+driver/ppc/sn5s330.*
+driver/ppc/syv682x.*
+driver/retimer/bb_retimer.*
+driver/retimer/kb800x.*
+driver/tcpm/ps8xxx.*
+driver/tcpm/rt1715.*
+driver/usb_mux/virtual.*
diff --git a/util/zephyr_check_compliance.py b/util/zephyr_check_compliance.py
new file mode 100755
index 0000000000..24fea8594e
--- /dev/null
+++ b/util/zephyr_check_compliance.py
@@ -0,0 +1,136 @@
+#!/usr/bin/env vpython3
+
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Check a single commit using the Zephyr check_compliance.py script."""
+
+# [VPYTHON:BEGIN]
+# python_version: "3.8"
+# wheel: <
+#   name: "infra/python/wheels/junitparser-py2_py3"
+#   version: "version:2.8.0"
+# >
+# wheel: <
+#   name: "infra/python/wheels/future-py2_py3"
+#   version: "version:0.18.2"
+# >
+# wheel: <
+#   name: "infra/python/wheels/python-magic-py2_py3"
+#   version: "version:0.4.24"
+# >
+# wheel: <
+#   name: "infra/python/wheels/pyyaml-py3"
+#   version: "version:5.3.1"
+# >
+# wheel: <
+#   name: "infra/python/wheels/yamllint-py3"
+#   version: "version:1.29.0"
+# >
+# wheel: <
+#   name: "infra/python/wheels/pathspec-py3"
+#   version: "version:0.9.0"
+# >
+# wheel: <
+#   name: "infra/python/wheels/lxml/${vpython_platform}"
+#   version: "version:4.6.3"
+# >
+# [VPYTHON:END]
+
+import argparse
+import os
+import pathlib
+import site
+import sys
+
+
+EC_BASE = pathlib.Path(__file__).parent.parent
+
+if "ZEPHYR_BASE" in os.environ:
+    ZEPHYR_BASE = pathlib.Path(os.environ.get("ZEPHYR_BASE"))
+else:
+    ZEPHYR_BASE = pathlib.Path(
+        EC_BASE.resolve().parent.parent / "third_party" / "zephyr" / "main"
+    )
+
+site.addsitedir(ZEPHYR_BASE / "scripts" / "ci")
+# pylint:disable=import-error,wrong-import-position
+import check_compliance
+
+
+# pylint:enable=import-error,wrong-import-position
+
+
+# Fake ref used by "pre-upload.py --pre-submit"
+PRE_SUBMIT_REF = "pre-submit"
+
+
+def _parse_args(argv):
+    parser = argparse.ArgumentParser(description=__doc__)
+
+    parser.add_argument(
+        "commit",
+        help="Git commit to be checked, hash or reference.",
+    )
+
+    return parser.parse_args(argv)
+
+
+def _patch_get_files():
+    """Patch compliance get_files() to exclude non zephyr files."""
+    original_get_files = check_compliance.get_files
+
+    def patched_get_files(**kwargs):
+        out = []
+        for file in original_get_files(**kwargs):
+            if file.startswith("zephyr/"):
+                out.append(file)
+        return out
+
+    check_compliance.get_files = patched_get_files
+
+
+def _changed_files(commit_range):
+    check_compliance.COMMIT_RANGE = commit_range
+    check_compliance.GIT_TOP = EC_BASE
+
+    files = check_compliance.get_files(filter="d")
+    if len(files) > 0:
+        return True
+
+    return False
+
+
+def main(argv):
+    """Main function"""
+    args = _parse_args(argv)
+
+    if args.commit == PRE_SUBMIT_REF:
+        # Skip if there's no actual commit
+        return
+
+    commit_range = f"{args.commit}~1..{args.commit}"
+
+    _patch_get_files()
+
+    if not _changed_files(commit_range):
+        # Exit early if nothing changed
+        return
+
+    # TODO: also enable DevicetreeBindings
+    check_compliance.main(
+        [
+            "--output=",
+            "--no-case-output",
+            "-m",
+            "YAMLLint",
+            "-c",
+            commit_range,
+        ]
+    )
+    # Never returns, check_compliance.main() calls sys.exit()
+
+
+if __name__ == "__main__":
+    main(sys.argv[1:])
diff --git a/util/zephyr_check_compliance_unittest.py b/util/zephyr_check_compliance_unittest.py
new file mode 100755
index 0000000000..1d4be968d0
--- /dev/null
+++ b/util/zephyr_check_compliance_unittest.py
@@ -0,0 +1,119 @@
+#!/usr/bin/env vpython3
+
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Unit tests for check_zephyr_project_config.py"""
+
+# [VPYTHON:BEGIN]
+# python_version: "3.8"
+# wheel: <
+#   name: "infra/python/wheels/mock-py3"
+#   version: "version:4.0.3"
+# >
+# wheel: <
+#   name: "infra/python/wheels/junitparser-py2_py3"
+#   version: "version:2.8.0"
+# >
+# wheel: <
+#   name: "infra/python/wheels/future-py2_py3"
+#   version: "version:0.18.2"
+# >
+# wheel: <
+#   name: "infra/python/wheels/python-magic-py2_py3"
+#   version: "version:0.4.24"
+# >
+# wheel: <
+#   name: "infra/python/wheels/pyyaml-py3"
+#   version: "version:5.3.1"
+# >
+# wheel: <
+#   name: "infra/python/wheels/yamllint-py3"
+#   version: "version:1.29.0"
+# >
+# wheel: <
+#   name: "infra/python/wheels/pathspec-py3"
+#   version: "version:0.9.0"
+# >
+# wheel: <
+#   name: "infra/python/wheels/lxml/${vpython_platform}"
+#   version: "version:4.6.3"
+# >
+# [VPYTHON:END]
+
+import unittest
+
+import mock  # pylint:disable=import-error
+import zephyr_check_compliance
+
+
+# pylint:disable=protected-access,no-self-use
+
+
+class TestZephyrCheckCompliance(unittest.TestCase):
+    """Tests for zephyr_check_compliance."""
+
+    @mock.patch("check_compliance.get_files")
+    def test_changed_files(self, get_files_mock):
+        """Test _changed_files."""
+        get_files_mock.return_value = [
+            "file1",
+            "file2",
+        ]
+
+        zephyr_check_compliance._patch_get_files()
+        out = zephyr_check_compliance._changed_files("ref")
+        self.assertFalse(out)
+
+        get_files_mock.return_value.append("zephyr/file3")
+
+        zephyr_check_compliance._patch_get_files()
+        out = zephyr_check_compliance._changed_files("ref")
+        self.assertTrue(out)
+
+    @mock.patch("zephyr_check_compliance._changed_files")
+    @mock.patch("check_compliance.main")
+    def test_main(self, main_mock, changed_files_mock):
+        """Tests the main function."""
+        changed_files_mock.return_value = True
+
+        zephyr_check_compliance.main(["ref"])
+
+        changed_files_mock.assert_called_with("ref~1..ref")
+        main_mock.assert_called_with(
+            [
+                "--output=",
+                "--no-case-output",
+                "-m",
+                "YAMLLint",
+                "-c",
+                "ref~1..ref",
+            ]
+        )
+
+    @mock.patch("zephyr_check_compliance._changed_files")
+    @mock.patch("check_compliance.main")
+    def test_main_skip_presubmit(self, main_mock, changed_files_mock):
+        """Tests the main function."""
+        changed_files_mock.return_value = False
+
+        zephyr_check_compliance.main([zephyr_check_compliance.PRE_SUBMIT_REF])
+
+        self.assertEqual(changed_files_mock.call_count, 0)
+        self.assertEqual(main_mock.call_count, 0)
+
+    @mock.patch("zephyr_check_compliance._changed_files")
+    @mock.patch("check_compliance.main")
+    def test_main_skip(self, main_mock, changed_files_mock):
+        """Tests the main function."""
+        changed_files_mock.return_value = False
+
+        zephyr_check_compliance.main(["ref"])
+
+        changed_files_mock.assert_called_with("ref~1..ref")
+        self.assertEqual(main_mock.call_count, 0)
+
+
+if __name__ == "__main__":
+    unittest.main()
diff --git a/util/zephyr_check_testcase_yaml.py b/util/zephyr_check_testcase_yaml.py
new file mode 100755
index 0000000000..51ff71db89
--- /dev/null
+++ b/util/zephyr_check_testcase_yaml.py
@@ -0,0 +1,65 @@
+#!/usr/bin/env vpython3
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Perform pre-submit checks on testcase.yaml files"""
+
+# [VPYTHON:BEGIN]
+# python_version: "3.8"
+# wheel: <
+#   name: "infra/python/wheels/pyyaml-py3"
+#   version: "version:5.3.1"
+# >
+# [VPYTHON:END]
+
+import sys
+from typing import List, Optional
+
+import preupload.lib
+import yaml  # pylint: disable=import-error
+
+
+BLOCKED_FIELDS = {
+    "CONF_FILE": "extra_conf_files",
+    "OVERLAY_CONFIG": "extra_overlay_confs",
+    "DTC_OVERLAY_FILE": "extra_dtc_overlay_files",
+}
+
+
+def main(argv: Optional[List[str]] = None) -> Optional[int]:
+    """Look at all testcase.yaml files passed in on commandline for invalid fields."""
+    return_code = 0
+    parser = preupload.lib.argument_parser()
+
+    args = parser.parse_args(argv)
+    for filename in args.filename:
+        if filename.name == "/testcase.yaml":
+            lines = preupload.lib.cat_file(args, filename)
+            data = yaml.load(lines, Loader=yaml.SafeLoader)
+
+            def scan_section(section, filename):
+                nonlocal return_code
+                if "extra_args" in section:
+                    for field, replacement in BLOCKED_FIELDS.items():
+                        if field in section["extra_args"]:
+                            print(
+                                f"error: Don't specify {field} in "
+                                f"`extra_args`. Use `{replacement}`: "
+                                f"{filename}",
+                                file=sys.stderr,
+                            )
+                            return_code = 1
+
+            if "common" in data:
+                scan_section(data["common"], filename)
+            if "tests" in data:
+                for section in data["tests"]:
+                    scan_section(data["tests"][section], filename)
+            continue
+
+    return return_code
+
+
+if __name__ == "__main__":
+    sys.exit(main(sys.argv[1:]))
diff --git a/util/zephyr_to_resultdb.py b/util/zephyr_to_resultdb.py
new file mode 100755
index 0000000000..dbcba89605
--- /dev/null
+++ b/util/zephyr_to_resultdb.py
@@ -0,0 +1,258 @@
+#!/usr/bin/env python3
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+""" Upload twister results to ResultDB
+
+    Usage:
+    $ rdb stream -new -realm chromium:public -tag builder_name:${HOSTNAME%%.*}
+      -- ./util/zephyr_to_resultdb.py --results=twister-out/twister.json
+      --upload=True
+"""
+
+import argparse
+import base64
+import datetime
+import json
+import os
+import pathlib
+import re
+
+import requests  # pylint: disable=import-error
+
+
+def translate_status(status):
+    """Translates ZTEST status to ResultDB status"""
+    ret_status = "SKIP"
+
+    if status == "passed":
+        ret_status = "PASS"
+    elif status == "failed":
+        ret_status = "FAIL"
+    elif status in ["skipped", "filtered"]:
+        ret_status = "SKIP"
+    elif status == "blocked":
+        # Twister status for tests that didn't run due to test suite timeout
+        ret_status = "ABORT"
+
+    return ret_status
+
+
+def translate_expected(status):
+    """Translates ZTEST status to ResultDB expected"""
+    flag = False
+
+    if status in ["passed", "filtered"]:
+        flag = True
+
+    return flag
+
+
+def translate_duration(testcase):
+    """Translates ZTEST execution_time to ResultDB duration"""
+    time = testcase.get("execution_time")
+    if not time:
+        return None
+
+    return f"{float(time)/1000:.9f}s"
+
+
+def testcase_summary(testcase):
+    """Translates ZTEST testcase to ResultDB summaryHtml"""
+    html = "<p>None</p>"
+
+    if (
+        "log" in testcase
+        or "reason" in testcase
+        or translate_status(testcase["status"]) == "SKIP"
+    ):
+        html = '<p><text-artifact artifact-id="test_log"></p>'
+
+    return html
+
+
+def testcase_artifact(testcase):
+    """Translates ZTEST testcase to ResultDB artifact"""
+    artifact = "Unknown"
+
+    if "log" in testcase and testcase["log"]:
+        artifact = testcase["log"]
+    elif "reason" in testcase and testcase["reason"]:
+        artifact = testcase["reason"]
+    elif testcase["status"] == "filtered":
+        artifact = "filtered"
+    elif testcase["status"] == "skipped":
+        artifact = "skipped"
+
+    return base64.b64encode(artifact.encode())
+
+
+def testsuite_artifact(testsuite):
+    """Translates ZTEST testcase to ResultDB artifact"""
+    artifact = "Unknown"
+
+    if "log" in testsuite and testsuite["log"]:
+        artifact = testsuite["log"]
+
+    return base64.b64encode(artifact.encode())
+
+
+def testcase_to_result(testsuite, testcase, base_tags, config_tags):
+    """Translates ZTEST testcase to ResultDB format
+    See TestResult type in
+    https://crsrc.org/i/go/src/go.chromium.org/luci/resultdb/sink/proto/v1/test_result.proto
+    """
+    result = {
+        "testId": testcase["identifier"],
+        "status": translate_status(testcase["status"]),
+        "expected": translate_expected(testcase["status"]),
+        "summaryHtml": testcase_summary(testcase),
+        "artifacts": {
+            "test_log": {
+                "contents": testcase_artifact(testcase),
+            },
+            "testsuite_log": {
+                "contents": testsuite_artifact(testsuite),
+            },
+        },
+        "tags": [
+            {"key": "suite", "value": testsuite["name"]},
+            {"key": "platform", "value": testsuite["platform"]},
+        ],
+        "duration": translate_duration(testcase),
+        "testMetadata": {"name": testcase["identifier"]},
+    }
+
+    for (key, value) in base_tags:
+        result["tags"].append({"key": key, "value": value})
+
+    for (key, value) in config_tags:
+        result["tags"].append({"key": key.lower(), "value": value})
+
+    if result["status"] == "FAIL" and "log" in testcase and testcase["log"]:
+        assert_msg = re.findall(
+            r"Assertion failed.*$", testcase["log"], re.MULTILINE
+        )
+        if assert_msg:
+            result["failureReason"] = {"primaryErrorMessage": assert_msg[0]}
+        else:
+            result["failureReason"] = {
+                "primaryErrorMessage": "Assert not found - possibly occurred in test setup"
+            }
+
+    return result
+
+
+def get_testsuite_config_tags(twister_dir, testsuite):
+    """Creates config tags from the testsuite"""
+    config_tags = []
+    suite_path = f"{twister_dir}/{testsuite['platform']}/{testsuite['name']}"
+    dot_config = f"{suite_path}/zephyr/.config"
+
+    if pathlib.Path(dot_config).exists():
+        with open(dot_config) as file:
+            lines = file.readlines()
+
+            for line in lines:
+                # Ignore empty lines and comments
+                if line.strip() and not line.startswith("#"):
+                    result = re.search(r"(\w+)=(.+$)", line)
+                    config_tags.append((result.group(1), result.group(2)))
+    else:
+        print(f"Can't find config file for {testsuite['name']}")
+
+    return config_tags
+
+
+def create_base_tags(data):
+    """Creates base tags needed for Testhaus"""
+    base_tags = []
+
+    queued_time = datetime.datetime.fromisoformat(
+        data["environment"]["run_date"]
+    )
+    base_tags.append(
+        ("queued_time", queued_time.strftime("%Y-%m-%d %H:%M:%S.%f UTC"))
+    )
+
+    base_tags.append(("zephyr_version", data["environment"]["zephyr_version"]))
+    base_tags.append(("board", data["environment"]["os"]))
+    base_tags.append(("toolchain", data["environment"]["toolchain"]))
+
+    return base_tags
+
+
+def json_to_resultdb(result_file):
+    """Translates Twister json test report to ResultDB format"""
+    with open(result_file) as file:
+        data = json.load(file)
+        results = []
+        base_tags = create_base_tags(data)
+
+        for testsuite in data["testsuites"]:
+            config_tags = get_testsuite_config_tags(
+                os.path.dirname(result_file), testsuite
+            )
+            for testcase in testsuite["testcases"]:
+                if testcase["status"]:
+                    results.append(
+                        testcase_to_result(
+                            testsuite, testcase, base_tags, config_tags
+                        )
+                    )
+
+        file.close()
+
+    return results
+
+
+class BytesEncoder(json.JSONEncoder):
+    """Encoder for ResultDB format"""
+
+    def default(self, o):
+        if isinstance(o, bytes):
+            return o.decode("utf-8")
+        return json.JSONEncoder.default(self, o)
+
+
+def upload_results(results):
+    """Upload results to ResultDB"""
+    with open(os.environ["LUCI_CONTEXT"]) as file:
+        sink = json.load(file)["result_sink"]
+
+    # Uploads all test results at once.
+    res = requests.post(
+        url="http://%s/prpc/luci.resultsink.v1.Sink/ReportTestResults"
+        % sink["address"],
+        headers={
+            "Content-Type": "application/json",
+            "Accept": "application/json",
+            "Authorization": "ResultSink %s" % sink["auth_token"],
+        },
+        data=json.dumps({"testResults": results}, cls=BytesEncoder),
+    )
+    res.raise_for_status()
+
+
+def main():
+    """main"""
+    # Set up argument parser.
+    parser = argparse.ArgumentParser(
+        description=("Upload Zephyr Twister test results to ResultDB")
+    )
+    parser.add_argument("--results")
+    parser.add_argument("--upload", default=False)
+    args = parser.parse_args()
+
+    if args.results:
+        print(f"Converting: {args.results}")
+        rdb_results = json_to_resultdb(args.results)
+        if args.upload:
+            upload_results(rdb_results)
+    else:
+        raise Exception("Missing test result file for conversion")
+
+
+if __name__ == "__main__":
+    main()
diff --git a/util/zephyr_to_resultdb.py.vpython3 b/util/zephyr_to_resultdb.py.vpython3
new file mode 100644
index 0000000000..9a086bffdf
--- /dev/null
+++ b/util/zephyr_to_resultdb.py.vpython3
@@ -0,0 +1,18 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# vpython VirtualEnv protobuf for "zephyr_to_resultdb.py".
+#
+# Dependencies needed to run zephyr_to_resultdb.py in
+#   infra/recipes/recipes/build_firmware.py
+#
+# For info on this file, see:
+# https://chromium.googlesource.com/infra/infra/+/HEAD/doc/users/vpython.md#available-wheels
+#
+
+python_version: "3.8"
+wheel: <
+  name: "infra/python/wheels/requests-py2_py3"
+  version: "version:2.13.0"
+>
diff --git a/west.yml b/west.yml
new file mode 100644
index 0000000000..535873790d
--- /dev/null
+++ b/west.yml
@@ -0,0 +1,44 @@
+manifest:
+  self:
+    path: modules/ec
+
+  remotes:
+    - name: chromium
+      url-base: https://chromium.googlesource.com/chromiumos
+
+  projects:
+    - name: zephyr
+      remote: chromium
+      repo-path: third_party/zephyr
+      revision: main
+      path: zephyr
+      west-commands: scripts/west-commands.yml
+      clone-depth: 500
+
+    - name: cmsis
+      remote: chromium
+      repo-path: third_party/zephyr/cmsis
+      revision: chromeos-main
+      path: modules/cmsis
+      clone-depth: 500
+
+    - name: hal_stm32
+      remote: chromium
+      repo-path: third_party/zephyr/hal_stm32
+      revision: chromeos-main
+      path: modules/hal_stm32
+      clone-depth: 500
+
+    - name: nanopb
+      remote: chromium
+      repo-path: third_party/zephyr/nanopb
+      revision: main
+      path: modules/nanopb
+      clone-depth: 500
+
+    - name: cryptoc
+      remote: chromium
+      repo-path: third_party/cryptoc
+      revision: main
+      path: modules/cryptoc
+      clone-depth: 500
diff --git a/zephyr/.pylintrc b/zephyr/.pylintrc
new file mode 100644
index 0000000000..066e00da9d
--- /dev/null
+++ b/zephyr/.pylintrc
@@ -0,0 +1,20 @@
+[MASTER]
+init-hook='import sys; sys.path.extend(["zephyr/zmake"])'
+
+# cros lint doesn't inherit the pylintrc from the parent dir.
+# These settings are copied from platform/ec/pylintrc
+[MESSAGES CONTROL]
+
+disable=
+    bad-continuation,
+    bad-whitespace,
+    # These have nothing to do with black, they are just annoying
+    fixme,
+    too-many-arguments,
+    too-many-statements,
+    too-many-branches,
+    too-many-locals
+
+[format]
+
+string-quote=double
diff --git a/zephyr/CMakeLists.txt b/zephyr/CMakeLists.txt
index 1959486797..b7cc0f034d 100644
--- a/zephyr/CMakeLists.txt
+++ b/zephyr/CMakeLists.txt
@@ -1,31 +1,658 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
-# Note: this cmake system implements only a zephyr module, and is not
-# intended to build a complete EC.  To build projects in platform/ec,
-# you should continue to use the Makefile system.
+if(DEFINED CONFIG_PLATFORM_EC AND EXISTS "${EDT_PICKLE}")
+  message(STATUS "Performing EC specific devicetree checks")
+
+  # Zephyr's gen_defines.py creates an EDT object of the final devicetree,
+  # saving it as pickle file in the build directory.
+  set(NAMED_GPIOS_SCRIPT ${PLATFORM_EC}/zephyr/scripts/named_gpios.py)
+  set(CMD_NAMED_GPIOS ${PYTHON_EXECUTABLE} ${NAMED_GPIOS_SCRIPT}
+    --zephyr-base ${ZEPHYR_BASE}
+    --edt-pickle ${EDT_PICKLE}
+  )
+  execute_process(COMMAND ${CMD_NAMED_GPIOS} RESULT_VARIABLE ret)
+  if(NOT "${ret}" STREQUAL "0")
+    message(FATAL_ERROR "named_gpios.py failed with return code: ${ret}")
+  endif()
+endif()
+
+if(DEFINED ZMAKE_INCLUDE_DIR)
+  zephyr_include_directories("${ZMAKE_INCLUDE_DIR}")
+endif()
+
+# When CONFIG_ASSERT is enabled, the __FILE__ macro may add full paths into the
+# read-only strings. This wastes space and can cause non-reproducible builds.
+# When the compiler supports it, replace common path prefixes with static
+# strings.
+
+# PLATFORM_EC points to the build directory, which symlinks to the actual
+# source. ZEPHYR_CURRENT_CMAKE_DIR points to the actual source directory
+# containing this file.  Set the PLATFORM_EC_SRC to the parent.
+# Replace the paths of the both the build and source directories with "EC_BASE".
+cmake_path(GET ZEPHYR_CURRENT_CMAKE_DIR PARENT_PATH PLATFORM_EC_SRC)
+zephyr_cc_option(-fmacro-prefix-map=${PLATFORM_EC}=EC_BASE)
+zephyr_cc_option(-fmacro-prefix-map=${PLATFORM_EC_SRC}=EC_BASE)
+
+if(DEFINED CONFIG_PLATFORM_EC)
+  # Add CHROMIUM_EC definition, which is used by ec_commands.h to
+  # determine that the header is being compiled for the EC instead of
+  # by another third-party C codebase.
+  zephyr_compile_definitions("CHROMIUM_EC")
+
+  # Add CONFIG_ZEPHYR, which is commonly used to guard code for use
+  # with Zephyr builds only.
+  zephyr_compile_definitions("CONFIG_ZEPHYR")
+
+  include(fpu.cmake)
+
+  # When LTO is enabled, enable only for the "app" library, which compiles
+  # and links all Chromium OS sources.
+  # TODO: Enable LTO for all sources when Zephyr supports it.
+  # See https://github.com/zephyrproject-rtos/zephyr/issues/2112
+  if (DEFINED CONFIG_LTO)
+    # The Zephyr toolchain generates linker errors if both CONFIG_LTO and
+    # CONFIG_FPU are used. See b/184302085.
+    if(("${ZEPHYR_TOOLCHAIN_VARIANT}" STREQUAL "zephyr") AND
+     (DEFINED CONFIG_FPU))
+      message(STATUS "Zephyr toolchain and CONFIG_FPU detected: disabling LTO")
+    else()
+      set_property(TARGET app PROPERTY INTERPROCEDURAL_OPTIMIZATION True)
+    endif()
+  endif()
+endif()
+
+# Set extra compiler flags.
+if (DEFINED CONFIG_ARM)
+  # This flag is only used by ARM
+  zephyr_cc_option(-mno-unaligned-access)
+endif()
+zephyr_cc_option(-Wimplicit-fallthrough)
+
+if (DEFINED CONFIG_RISCV)
+  zephyr_cc_option(-fsanitize=integer-divide-by-zero)
+  zephyr_cc_option(-fsanitize-undefined-trap-on-error)
+endif()
+
+# The EC application is split into two libraries:
+#   app: contains all the legacy code
+#   ec_shim: contains all the code under platform/ec/shim
 #
-# Googlers can find the design doc at go/zephyr-shim.
+# This allows us to add an extra compiler definition __REQUIRE_ZEPHYR_GPIOS__
+# that is applied only to the Zephyr sources. This is used to verify that
+# all Zephyr sources are using the upstream Zephyr GPIO API and not the legacy
+# EC API.
+zephyr_library_named(ec_shim)
+get_property(APP_LTO_PROPERTY TARGET app PROPERTY INTERPROCEDURAL_OPTIMIZATION)
+set_property(TARGET ec_shim PROPERTY INTERPROCEDURAL_OPTIMIZATION ${APP_LTO_PROPERTY})
+set_property(TARGET ec_shim APPEND PROPERTY COMPILE_DEFINITIONS __REQUIRE_ZEPHYR_GPIOS__)
+
+# Create an interface library for CrosEC (cros_ec_interface) that can be used
+# as a dependency for individual CrosEC libraries. To use:
+#  zephyr_library_named(my_lib)
+#  target_link_libraries(my_lib PRIVATE cros_ec_interface)
+add_library(cros_ec_interface INTERFACE)
 
-if(NOT DEFINED ZEPHYR_CURRENT_MODULE_DIR)
-  message(FATAL_ERROR "This Cmake system implements only a Zephyr module, and
-          should not be invoked directly.  Please continue to use the Makefile
-          system for non-Zephyr builds.")
+# Switch from the "zephyr" library to the "app" library for all Chromium OS
+# sources.
+set(ZEPHYR_CURRENT_LIBRARY app)
+
+# Custom function that ensures the include path is always updated for both
+# libraries.
+function(cros_ec_library_include_directories)
+  target_include_directories(app PUBLIC ${ARGN})
+  target_include_directories(ec_shim PRIVATE ${ARGN})
+  target_include_directories(cros_ec_interface INTERFACE ${ARGN})
+endfunction()
+function(cros_ec_library_include_directories_ifdef feature_toggle)
+  if(${${feature_toggle}})
+    target_include_directories(app PUBLIC ${ARGN})
+    target_include_directories(ec_shim PRIVATE ${ARGN})
+    target_include_directories(cros_ec_interface INTERFACE ${ARGN})
+  endif()
+endfunction()
+
+cros_ec_library_include_directories(include)
+
+if (DEFINED CONFIG_PLATFORM_EC)
+  cros_ec_library_include_directories(
+    "${PLATFORM_EC}/zephyr/shim/include"
+    "${PLATFORM_EC}/fuzz"
+    "${PLATFORM_EC}/test"
+    "${PLATFORM_EC}"
+    "${PLATFORM_EC}/include"
+    "${PLATFORM_EC}/include/driver"
+    "${PLATFORM_EC}/third_party")
 endif()
 
-set(PLATFORM_EC "${ZEPHYR_CURRENT_MODULE_DIR}/.." CACHE PATH
-    "Path to the platform/ec repo.")
+add_subdirectory("subsys")
+
+# Creates a phony target all.libraries in case you only want to build the
+# libraries and not the binaries. For example for creating the initial zero
+# coverage files.
+get_property(ZEPHYR_LIBS_PROPERTY GLOBAL PROPERTY ZEPHYR_LIBS)
+add_custom_target(
+  all.libraries
+  DEPENDS
+  ${ZEPHYR_LIBS_PROPERTY}
+  kernel
+  ${CMAKE_BINARY_DIR}/gcov.sh
+  )
+configure_file(gcov.tmpl.sh ${CMAKE_BINARY_DIR}/gcov.sh)
+
+# CONFIG_PLATFORM_EC files that don't relate to something below should be
+# included here, sorted by filename. This is common functionality which is
+# supported by all boards and emulators (including unit tests) using the shim
+# layer.
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC
+                                                # TODO(b/237712836): Remove once
+                                                # Zephyr's libc has strcasecmp.
+                                                "${PLATFORM_EC}/builtin/stdlib.c"
+                                                "${PLATFORM_EC}/common/base32.c"
+                                                "${PLATFORM_EC}/common/console_output.c"
+                                                "${PLATFORM_EC}/common/ec_features.c"
+                                                "${PLATFORM_EC}/common/gpio_commands.c"
+                                                "${PLATFORM_EC}/common/peripheral.c"
+                                                "${PLATFORM_EC}/common/printf.c"
+                                                "${PLATFORM_EC}/common/queue.c"
+                                                "${PLATFORM_EC}/common/shared_mem.c"
+                                                "${PLATFORM_EC}/common/system.c"
+                                                "${PLATFORM_EC}/common/system_boot_time.c"
+                                                "${PLATFORM_EC}/common/uart_printf.c"
+                                                "${PLATFORM_EC}/common/util.c"
+                                                "${PLATFORM_EC}/common/version.c")
 
-zephyr_include_directories_ifdef(
-  CONFIG_PLATFORM_EC
-  "${PLATFORM_EC}/zephyr/shim/include"
-  "${PLATFORM_EC}/fuzz"
-  "${PLATFORM_EC}/test"
-  "${PLATFORM_EC}/include")
+# Now include files that depend on or relate to other CONFIG options, sorted by
+# CONFIG
+zephyr_library_sources_ifdef(CONFIG_HAS_TASK_POWERBTN
+                                                "${PLATFORM_EC}/common/power_button_x86.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ACCEL_BMA255
+                                                "${PLATFORM_EC}/driver/accel_bma2x2.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ACCEL_BMA4XX
+                                                "${PLATFORM_EC}/driver/accel_bma4xx.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ACCEL_KX022
+                                                "${PLATFORM_EC}/driver/accel_kionix.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ACCEL_LIS2DW12
+                                                "${PLATFORM_EC}/driver/accel_lis2dw12.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ACCELGYRO_BMI
+                                                "${PLATFORM_EC}/driver/accelgyro_bmi_common.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ACCELGYRO_BMI160
+                                                "${PLATFORM_EC}/driver/accelgyro_bmi160.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ACCELGYRO_BMI260
+                                                "${PLATFORM_EC}/driver/accelgyro_bmi260.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX
+                                                "${PLATFORM_EC}/driver/accelgyro_bmi3xx.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ACCELGYRO_ICM
+                                                "${PLATFORM_EC}/driver/accelgyro_icm_common.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ACCELGYRO_ICM426XX
+                                                "${PLATFORM_EC}/driver/accelgyro_icm426xx.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ACCELGYRO_ICM42607
+                                                "${PLATFORM_EC}/driver/accelgyro_icm42607.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSO
+                                                "${PLATFORM_EC}/driver/accelgyro_lsm6dso.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSM
+                                                "${PLATFORM_EC}/driver/accelgyro_lsm6dsm.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ACCEL_FIFO
+                                                "${PLATFORM_EC}/common/motion_sense_fifo.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_AMD_STB_DUMP
+                                                "${PLATFORM_EC}/driver/amd_stb.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_BODY_DETECTION
+                                                "${PLATFORM_EC}/common/body_detection.c")
+zephyr_library_sources_ifdef(CONFIG_NAMED_ADC_CHANNELS
+                                                "${PLATFORM_EC}/common/adc.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_DEDICATED_ALS
+                                                "${PLATFORM_EC}/common/als.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ALS_TCS3400
+                                                "${PLATFORM_EC}/driver/als_tcs3400.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ALS_CM32183
+                                                "${PLATFORM_EC}/driver/als_cm32183.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ACPI
+                                                "${PLATFORM_EC}/common/acpi.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_AMD_SB_RMI
+						"${PLATFORM_EC}/driver/sb_rmi.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_AMD_STT
+						"${PLATFORM_EC}/driver/amd_stt.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_BACKLIGHT_LID
+                                                "${PLATFORM_EC}/common/backlight_lid.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_DETACHABLE_BASE
+                                                "${PLATFORM_EC}/common/base_state.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_BATTERY
+                                                "${PLATFORM_EC}/common/battery.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_BATTERY_V1
+                                                "${PLATFORM_EC}/common/battery_v1.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_BATTERY_V2
+                                                "${PLATFORM_EC}/common/battery_v2.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE
+                                                "${PLATFORM_EC}/common/battery_fuel_gauge.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_BATTERY_SMART
+                                                "${PLATFORM_EC}/driver/battery/smart.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_BC12_DETECT_RT1718S
+                                                "${PLATFORM_EC}/driver/bc12/rt1718s.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_BC12_DETECT_PI3USB9201
+                                                "${PLATFORM_EC}/driver/bc12/pi3usb9201.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_BC12_DETECT_MT6360
+                                                "${PLATFORM_EC}/driver/bc12/mt6360.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER_ISL9237
+                                                "${PLATFORM_EC}/driver/charger/isl923x.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER_ISL9238
+                                                "${PLATFORM_EC}/driver/charger/isl923x.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER_ISL9238C
+                                                "${PLATFORM_EC}/driver/charger/isl923x.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER_RAA489000
+                                                "${PLATFORM_EC}/driver/charger/isl923x.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER_ISL9241
+                                                "${PLATFORM_EC}/driver/charger/isl9241.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER_BQ25710
+                                                "${PLATFORM_EC}/driver/charger/bq25710.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER_BQ25720
+                                                "${PLATFORM_EC}/driver/charger/bq25710.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER_RT9490
+                                                "${PLATFORM_EC}/driver/charger/rt9490.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER_SM5803
+                                                "${PLATFORM_EC}/driver/charger/sm5803.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGESPLASH
+                                                "${PLATFORM_EC}/common/chargesplash.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGE_MANAGER
+                                                "${PLATFORM_EC}/common/charger.c"
+                                                "${PLATFORM_EC}/common/charge_manager.c"
+                                                "${PLATFORM_EC}/common/charge_state.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGE_RAMP_HW
+                                                "${PLATFORM_EC}/common/charge_ramp.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGE_RAMP_SW
+                                                "${PLATFORM_EC}/common/charge_ramp.c"
+                                                "${PLATFORM_EC}/common/charge_ramp_sw.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CPS8100
+                                                "${PLATFORM_EC}/driver/wpc/cps8100.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_OCPC
+                                                "${PLATFORM_EC}/common/ocpc.c")
 
-add_subdirectory_ifdef(CONFIG_PLATFORM_EC "shim/src")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CBI
+                                                "${PLATFORM_EC}/common/cbi.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CBI_GPIO
+                                                "${PLATFORM_EC}/common/cbi_gpio.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CONSOLE_CMD_MEM
+                                                "${PLATFORM_EC}/common/memory_commands.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_DPTF
+                                                "${PLATFORM_EC}/common/dptf.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_POWERSEQ
+                                                "${PLATFORM_EC}/common/chipset.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI
+                                                "${PLATFORM_EC}/common/espi.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_EXTPOWER
+						"${PLATFORM_EC}/common/extpower_common.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_EXTPOWER_GPIO
+                                                "${PLATFORM_EC}/common/extpower_gpio.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FAN
+                                                "${PLATFORM_EC}/common/fan.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FLASH_CROS
+                                                "${PLATFORM_EC}/common/flash.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_HOSTCMD
+                                                "${PLATFORM_EC}/common/host_command.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_HOSTCMD
+                                                "${PLATFORM_EC}/common/host_event_commands.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_HOSTCMD_CONSOLE
+                                                "${PLATFORM_EC}/common/uart_hostcmd.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_HOSTCMD_GET_UPTIME_INFO
+                                                "${PLATFORM_EC}/common/uptime.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_HOSTCMD_REGULATOR
+                                                "${PLATFORM_EC}/common/regulator.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_I2C
+                                                "${PLATFORM_EC}/common/i2c_controller.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_I2C_DEBUG
+                                                "${PLATFORM_EC}/common/i2c_trace.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_I2C_VIRTUAL_BATTERY
+                                                "${PLATFORM_EC}/common/virtual_battery.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_IOEX_CCGXXF
+                                                "${PLATFORM_EC}/driver/ioexpander/ccgxxf.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_IOEX_IT8801
+                                                "${PLATFORM_EC}/driver/ioexpander/it8801.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_IOEX_NCT38XX
+                                                "${PLATFORM_EC}/driver/ioexpander/ioexpander_nct38xx.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_IOEX_PCA9675
+                                                "${PLATFORM_EC}/driver/ioexpander/pca9675.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_IOEX_PCAL6408
+                                                "${PLATFORM_EC}/driver/ioexpander/pcal6408.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_IOEX_TCA64XXA
+                                                "${PLATFORM_EC}/driver/ioexpander/tca64xxa.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_KEYBOARD
+                                                "${PLATFORM_EC}/common/keyboard_scan.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_RGB_KEYBOARD
+                                                "${PLATFORM_EC}/common/rgb_keyboard.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_8042
+                                                "${PLATFORM_EC}/common/keyboard_8042.c"
+                                                "${PLATFORM_EC}/common/keyboard_8042_sharedlib.c")
+zephyr_library_sources_ifdef(CONFIG_MKBP_PROTOCOL
+                                                "${PLATFORM_EC}/common/mkbp_fifo.c"
+                                                "${PLATFORM_EC}/common/mkbp_info.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_MKBP
+                                                "${PLATFORM_EC}/common/keyboard_mkbp.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_MKBP_INPUT_DEVICES
+                                                "${PLATFORM_EC}/common/mkbp_input_devices.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_KEYBOARD_VIVALDI
+                                                "${PLATFORM_EC}/common/keyboard_vivaldi.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_PWM_KBLIGHT
+                                                "${PLATFORM_EC}/common/keyboard_backlight.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LED_COMMON
+                                                "${PLATFORM_EC}/common/led_common.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LED_DT
+                                                "${PLATFORM_EC}/common/led_common.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LED_PWM
+                                                "${PLATFORM_EC}/common/led_pwm.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LED_ONOFF_STATES
+                                                "${PLATFORM_EC}/common/led_onoff_states.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LID_ANGLE
+                                                "${PLATFORM_EC}/common/motion_lid.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE
+                                                "${PLATFORM_EC}/common/lid_angle.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LID_SWITCH
+                                                "${PLATFORM_EC}/common/lid_switch.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_MKBP_EVENT
+                                                "${PLATFORM_EC}/common/mkbp_event.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_MOTIONSENSE
+                                                "${PLATFORM_EC}/common/motion_sense.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_MP2964
+                                                "${PLATFORM_EC}/driver/mp2964.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_INA236
+                                                "${PLATFORM_EC}/driver/ina2xx.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_PERIPHERAL_CHARGER
+                                                "${PLATFORM_EC}/common/peripheral_charger.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_PORT80
+                                                "${PLATFORM_EC}/common/port80.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_POWER_BUTTON
+                                                "${PLATFORM_EC}/common/power_button.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_POWERSEQ
+                                                "${PLATFORM_EC}/power/common.c")
+zephyr_library_sources_ifdef(CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540
+                                                "${PLATFORM_EC}/power/alderlake_slg4bd44540.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_POWERSEQ_AMD
+                                                "${PLATFORM_EC}/power/amd_x86.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_POWERSEQ_COMETLAKE
+                                                "${PLATFORM_EC}/power/cometlake.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_POWERSEQ_ICELAKE
+                                                "${PLATFORM_EC}/power/icelake.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_POWERSEQ_INTEL
+                                                "${PLATFORM_EC}/power/intel_x86.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_POWERSEQ_METEORLAKE
+                                                "${PLATFORM_EC}/power/meteorlake.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_POWERSEQ_HOST_SLEEP
+                                                "${PLATFORM_EC}/power/host_sleep.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_POWERSEQ_MT8186
+                                                "${PLATFORM_EC}/power/mt8186.c")
+# Re-use mt8186.c code
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_POWERSEQ_MT8188
+                                                "${PLATFORM_EC}/power/mt8186.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_POWERSEQ_MT8192
+                                                "${PLATFORM_EC}/power/mt8192.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_POWERSEQ_SC7180
+                                                "${PLATFORM_EC}/power/qcom.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_POWERSEQ_SC7280
+                                                "${PLATFORM_EC}/power/qcom.c")
+if (CONFIG_PLATFORM_EC_HIBERNATE AND CONFIG_AP_PWRSEQ)
+	zephyr_library_sources(			"${PLATFORM_EC}/power/hibernate.c")
+endif ()
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_PANIC
+                                                "${PLATFORM_EC}/common/panic_output.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_PSE_LTC4291
+                                                "${PLATFORM_EC}/driver/pse_ltc4291.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_RSA
+                                                "${PLATFORM_EC}/common/rsa.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_RWSIG
+                                                "${PLATFORM_EC}/common/rwsig.c"
+                                                "${PLATFORM_EC}/common/vboot/common.c"
+                                                "${PLATFORM_EC}/common/vboot/vb21_lib.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_SHA256_SW
+                                                "${PLATFORM_EC}/common/sha256.c")
+zephyr_library_sources_ifdef(CONFIG_SOC_IT8XXX2_SHA256_HW_ACCELERATE
+                                                "${PLATFORM_EC}/driver/sha256/sha256_it8xxx2.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_SWITCH
+                                                "${PLATFORM_EC}/common/switch.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_SWITCHCAP_LN9310
+                                                "${PLATFORM_EC}/driver/ln9310.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_STM_MEMS_COMMON
+                                                "${PLATFORM_EC}/driver/stm_mems_common.c")
 
-# Shimmed modules
-zephyr_sources_ifdef(CONFIG_PLATFORM_EC "${PLATFORM_EC}/common/util.c")
-zephyr_sources_ifdef(CONFIG_PLATFORM_EC_TIMER "${PLATFORM_EC}/common/timer.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_TABLET_MODE
+                                                "${PLATFORM_EC}/common/tablet_mode.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_TEMP_SENSOR
+                                                "${PLATFORM_EC}/common/thermal.c"
+                                                "${PLATFORM_EC}/common/temp_sensor.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_THERMISTOR
+                                                "${PLATFORM_EC}/driver/temp_sensor/thermistor.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_TEMP_SENSOR_PCT2075
+                                                "${PLATFORM_EC}/driver/temp_sensor/pct2075.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_TEMP_SENSOR_SB_TSI
+                                                "${PLATFORM_EC}/driver/temp_sensor/sb_tsi.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_TEMP_SENSOR_TMP112
+                                                "${PLATFORM_EC}/driver/temp_sensor/tmp112.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_TEMP_SENSOR_F75303
+                                                "${PLATFORM_EC}/driver/temp_sensor/f75303.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_THROTTLE_AP
+                                                "${PLATFORM_EC}/common/throttle_ap.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_TIMER
+                                                "${PLATFORM_EC}/common/timer.c")
+
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_CHARGER
+                                                "${PLATFORM_EC}/common/usb_charger.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PORT_POWER_DUMB
+                                                "${PLATFORM_EC}/common/usb_port_power_dumb.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART
+                                                "${PLATFORM_EC}/common/usb_port_power_smart.c")
+
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_POWER_DELIVERY
+                                                "${PLATFORM_EC}/common/typec_control.c"
+                                                "${PLATFORM_EC}/common/usb_common.c"
+                                                "${PLATFORM_EC}/common/usb_pd_pdo.c"
+                                                "${PLATFORM_EC}/common/usbc/usbc_task.c"
+                                                "${PLATFORM_EC}/common/usbc/usb_pd_timer.c"
+                                                "${PLATFORM_EC}/common/usbc/usb_sm.c"
+                                                "${PLATFORM_EC}/common/usbc_intr_task.c"
+                                                "${PLATFORM_EC}/common/usb_pd_flags.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_TOUCHPAD_ELAN
+                                                "${PLATFORM_EC}/driver/touchpad_elan.c")
+
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGEN
+                                                "${PLATFORM_EC}/common/chargen.c")
+
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CONSOLE_CMD_PD
+                                                "${PLATFORM_EC}/common/usbc/usb_pd_console.c")
+
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC_RETIMER_FW_UPDATE
+                                                "${PLATFORM_EC}/common/usbc/usb_retimer_fw_update.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC_RETIMER_ANX7483
+                                                "${PLATFORM_EC}/driver/retimer/anx7483.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC_RETIMER_ANX7452
+                                                "${PLATFORM_EC}/driver/retimer/anx7452.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_BB
+                                                "${PLATFORM_EC}/driver/retimer/bb_retimer.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_HB
+                                                "${PLATFORM_EC}/driver/retimer/bb_retimer.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC_RETIMER_KB8010
+                                                "${PLATFORM_EC}/driver/retimer/kb8010.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC_RETIMER_PS8818
+                                                "${PLATFORM_EC}/driver/retimer/ps8818.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC_RETIMER_PS8811
+                                                "${PLATFORM_EC}/driver/retimer/ps8811.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC_RETIMER_ANX7451
+                                                "${PLATFORM_EC}/driver/usb_mux/anx7451.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC_SS_MUX
+                                                "${PLATFORM_EC}/driver/usb_mux/usb_mux.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_MUX_AMD_FP6
+                                                "${PLATFORM_EC}/driver/usb_mux/amd_fp6.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_MUX_IT5205
+                                                "${PLATFORM_EC}/driver/usb_mux/it5205.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_MUX_PS8743
+                                                "${PLATFORM_EC}/driver/usb_mux/ps8743.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_MUX_TUSB546
+                                                "${PLATFORM_EC}/driver/usb_mux/tusb1064.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_MUX_TUSB1044
+                                                "${PLATFORM_EC}/driver/usb_mux/tusb1064.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_MUX_TUSB1064
+                                                "${PLATFORM_EC}/driver/usb_mux/tusb1064.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_MUX_VIRTUAL
+                                                "${PLATFORM_EC}/driver/usb_mux/virtual.c")
+
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_DPS
+                                                "${PLATFORM_EC}/common/dps.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_LOGGING
+                                                "${PLATFORM_EC}/common/event_log.c"
+                                                "${PLATFORM_EC}/common/pd_log.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE
+                                                "${PLATFORM_EC}/common/usbc/tbt_alt_mode.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_USB4
+                                                "${PLATFORM_EC}/common/usbc/usb_mode.c")
+zephyr_library_sources_ifdef(CONFIG_SVDM_RSP_DFP_ONLY
+                                                "${PLATFORM_EC}/common/usbc/svdm_rsp_dfp_only.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC_OCP
+                                                "${PLATFORM_EC}/common/usbc_ocp.c")
+
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_DISCOVERY
+                                                "${PLATFORM_EC}/common/usb_pd_discovery.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_ALT_MODE_UFP
+                                                "${PLATFORM_EC}/common/usb_pd_alt_mode_ufp.c")
+
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_DUAL_ROLE
+                                                "${PLATFORM_EC}/common/usb_pd_dual_role.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_CONSOLE_CMD
+                                                "${PLATFORM_EC}/common/usb_pd_console_cmd.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_HOST_CMD
+                                                "${PLATFORM_EC}/common/usb_pd_host_cmd.c"
+                                                "${PLATFORM_EC}/common/usbc/usb_pd_host.c")
+
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_VPD
+                                                "${PLATFORM_EC}/common/usbc/usb_tc_vpd_sm.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_CTVPD
+                                                "${PLATFORM_EC}/common/usbc/usb_tc_ctvpd_sm.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_DRP_ACC_TRYSRC
+                                                "${PLATFORM_EC}/common/usbc/usb_tc_drp_acc_trysrc_sm.c"
+                                                "${PLATFORM_EC}/common/usbc/usb_pe_drp_sm.c"
+                                                "${PLATFORM_EC}/common/usbc/usb_pd_dpm.c"
+						"${PLATFORM_EC}/common/usbc/usbc_pd_policy.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_DP_MODE
+                                                "${PLATFORM_EC}/common/usbc/dp_alt_mode.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_DP_HPD_GPIO
+                                                "${PLATFORM_EC}/common/usbc/dp_hpd_gpio.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_VDM_AP_CONTROL
+                                                "${PLATFORM_EC}/common/usbc/ap_vdm_control.c")
+
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PRL_SM
+                                                "${PLATFORM_EC}/common/usbc/usb_prl_sm.c")
+
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_TCPM_ANX7447
+                                                "${PLATFORM_EC}/driver/tcpm/anx7447.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_TCPM_CCGXXF
+                                                "${PLATFORM_EC}/driver/tcpm/ccgxxf.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_TCPM_NCT38XX
+                                                "${PLATFORM_EC}/driver/tcpm/nct38xx.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8XXX
+                                                "${PLATFORM_EC}/driver/tcpm/ps8xxx.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_TCPM_RAA489000
+                                                "${PLATFORM_EC}/driver/tcpm/raa489000.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_TCPM_RT1715
+                                                "${PLATFORM_EC}/driver/tcpm/rt1715.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_TCPM_RT1718S
+                                                "${PLATFORM_EC}/driver/tcpm/rt1718s.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_TCPM_TUSB422
+                                                "${PLATFORM_EC}/driver/tcpm/tusb422.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_TCPM_TCPCI
+                                                "${PLATFORM_EC}/driver/tcpm/tcpci.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_TCPM_ITE_ON_CHIP
+                                                "${PLATFORM_EC}/driver/tcpm/ite_pd_intc.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_TCPM_DRIVER_IT83XX
+                                                "${PLATFORM_EC}/driver/tcpm/it83xx.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_TCPM_DRIVER_IT8XXX2
+                                                "${PLATFORM_EC}/driver/tcpm/it8xxx2.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_TCPM_FUSB302
+                                                "${PLATFORM_EC}/driver/tcpm/fusb302.c")
+
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC_PPC
+                                                "${PLATFORM_EC}/common/usbc_ppc.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC_PPC_AOZ1380
+                                                "${PLATFORM_EC}/driver/ppc/aoz1380.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC_PPC_KTU1125
+                                                "${PLATFORM_EC}/driver/ppc/ktu1125.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC_PPC_NX20P3481
+                                                "${PLATFORM_EC}/driver/ppc/nx20p348x.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC_PPC_NX20P3483
+                                                "${PLATFORM_EC}/driver/ppc/nx20p348x.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC_PPC_RT1739
+                                                "${PLATFORM_EC}/driver/ppc/rt1739.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC_PPC_SN5S330
+                                                "${PLATFORM_EC}/driver/ppc/sn5s330.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC_PPC_SYV682X
+                                                "${PLATFORM_EC}/driver/ppc/syv682x.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC_PPC_RT1718S
+                                                "${PLATFORM_EC}/driver/ppc/rt1718s.c")
+
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_VBOOT_HASH
+                                                "${PLATFORM_EC}/common/vboot_hash.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_VOLUME_BUTTONS
+                                                "${PLATFORM_EC}/common/button.c")
+
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_VBOOT_EFS2
+                                                "${PLATFORM_EC}/common/vboot/efs2.c")
+
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_VSTORE
+                                                "${PLATFORM_EC}/common/vstore.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_RTC
+						"${PLATFORM_EC}/common/rtc.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_MATH_UTIL
+						"${PLATFORM_EC}/common/math_util.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_MAX695X_SEVEN_SEGMENT_DISPLAY
+						"${PLATFORM_EC}/driver/led/max695x.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LED_DRIVER_TLC59116F
+                                                "${PLATFORM_EC}/driver/led/tlc59116f.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_SYSTEM_SAFE_MODE
+                                                "${PLATFORM_EC}/common/system_safe_mode.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_HOST_COMMAND_MEMORY_DUMP
+                                                "${PLATFORM_EC}/common/host_command_memory_dump.c")
+
+# Switch to ec_shim library for all Zephyr sources
+set(ZEPHYR_CURRENT_LIBRARY ec_shim)
+
+add_subdirectory(linker)
+add_subdirectory("app")
+add_subdirectory("drivers")
+add_subdirectory("emul")
+add_subdirectory("fake")
+add_subdirectory("mock")
+add_subdirectory_ifdef(CONFIG_PLATFORM_EC "shim")
+
+# Use external script to generate the ec_version.h header and add as
+# a dependency to the EC application library.
+add_custom_target(
+  ec_version_header
+  VERBATIM COMMAND
+  "PYTHONPATH=${PLATFORM_EC}/zephyr/zmake/" ${PYTHON_EXECUTABLE}
+  "${PLATFORM_EC}/zephyr/zmake/zephyr_build_tools/generate_ec_version.py"
+  "${CMAKE_CURRENT_BINARY_DIR}/include/ec_version.h"
+  "--base" "${ZEPHYR_BASE}"
+  "--name" "${CMAKE_PROJECT_NAME}"
+  "--module" "${ZEPHYR_MODULES}"
+  ${EXTRA_EC_VERSION_FLAGS}
+)
+add_dependencies(app ec_version_header)
+
+# Include the directory containing the generated header.
+zephyr_include_directories("${CMAKE_CURRENT_BINARY_DIR}/include")
+
+# Sign RW firmware if RWSIG enabled
+if (DEFINED CONFIG_CROS_EC_RW AND DEFINED CONFIG_PLATFORM_EC_RWSIG)
+  add_custom_target(key_extract
+    COMMAND futility create
+      "${PLATFORM_EC}/${CONFIG_PLATFORM_EC_RWSIG_KEY_PATH}"
+      "${CMAKE_BINARY_DIR}/key"
+    COMMENT "Extracting signing keys"
+    VERBATIM
+  )
+
+  add_custom_target(sign_rw ALL
+    COMMAND futility sign --type rwsig
+            --prikey "${CMAKE_BINARY_DIR}/key.vbprik2"
+            "${CMAKE_BINARY_DIR}/zephyr/zephyr.bin"
+            "${CMAKE_BINARY_DIR}/ec.sig"
+    COMMENT "Signing EC RW"
+    DEPENDS zephyr_final key_extract
+    VERBATIM
+  )
+endif()
diff --git a/zephyr/DIR_METADATA b/zephyr/DIR_METADATA
new file mode 100644
index 0000000000..c7bfb79d83
--- /dev/null
+++ b/zephyr/DIR_METADATA
@@ -0,0 +1,9 @@
+# Metadata information for this directory.
+#
+# For more information on DIR_METADATA files, see:
+#   https://source.chromium.org/chromium/infra/infra/+/main:go/src/infra/tools/dirmd/README.md
+#
+# For the schema of this file, see Metadata message:
+#   https://source.chromium.org/chromium/infra/infra/+/main:go/src/infra/tools/dirmd/proto/dir_metadata.proto
+
+team_email: "zephyr-task-force@google.com"
diff --git a/zephyr/Kconfig b/zephyr/Kconfig
index e2a5f62ff4..e332c81d46 100644
--- a/zephyr/Kconfig
+++ b/zephyr/Kconfig
@@ -1,59 +1,958 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
+rsource "app/Kconfig"
+rsource "drivers/Kconfig"
+rsource "emul/Kconfig"
+rsource "fake/Kconfig"
+rsource "mock/Kconfig"
+rsource "subsys/Kconfig"
+rsource "subsys/emul/Kconfig"
+
+if ZTEST
+
+config HAS_TEST_TASKS
+	bool "Whether or not this test includes custom tasks"
+	help
+	  This enables custom tasks for tests. When set to 'y', the file
+	  "shimmed_test_tasks.h" will be included and is expected to set
+	  CROS_EC_TASK_LIST.
+
+endif # ZTEST
+
 menuconfig PLATFORM_EC
-	bool "Enable building code from the platform/ec Zephyr module"
+	bool "Chromium OS EC shim"
 	imply PRINTK
 	imply SHELL
 	help
 	  The platform/ec Zephyr module allows some code from the
-	  existing Chrome OS EC project to be "shimmed" into Zephyr.
+	  existing Chromium OS EC project to be "shimmed" into Zephyr. With
+	  this it is possible to use the existing code base within Zephyr.
+
+	  Once we manage to get a platform fully running with Zephyr we will
+	  progressively upstream components and turn off the shim for each
+	  one until eventually all code is on the Zephyr side.
 
 if PLATFORM_EC
 
-# Below is a hack to use CONFIG_ZEPHYR in platform/ec code before
-# config.h has been included.  There is some tricky ordering in some
-# header files that we cannot use config.h (e.g., common.h and
-# compile_time_macros.h), as many board.h and config_chip.h files
-# use these macros, and thus would be included by an include of
-# config.h.  We work around this by initially defining CONFIG_ZEPHYR
-# in Kconfig as an invisible symbol (it should always be enabled).
-# Then, once config.h gets included, it subsequently gets undef'ed by
-# config.h, and then redefined by config_chip.h in the Zephyr shim.
-config ZEPHYR
+rsource "shim/chip/npcx/Kconfig.npcx"
+rsource "shim/chip/mchp/Kconfig.xec"
+rsource "Kconfig.adc"
+rsource "Kconfig.ap_power"
+rsource "Kconfig.battery"
+rsource "Kconfig.charger"
+rsource "Kconfig.chargesplash"
+rsource "Kconfig.board_version"
+rsource "Kconfig.cbi"
+rsource "Kconfig.cec"
+rsource "Kconfig.console"
+rsource "Kconfig.console_cmd_mem"
+rsource "Kconfig.debug_assert"
+rsource "Kconfig.defaults"
+rsource "Kconfig.detachable_base"
+rsource "Kconfig.espi"
+rsource "Kconfig.flash"
+rsource "Kconfig.header"
+rsource "Kconfig.host_interface"
+rsource "Kconfig.i2c"
+rsource "Kconfig.ina2xx"
+rsource "Kconfig.init_priority"
+rsource "Kconfig.ioex"
+rsource "Kconfig.keyboard"
+rsource "Kconfig.led"
+rsource "Kconfig.led_dt"
+rsource "Kconfig.panic"
+rsource "Kconfig.port80"
+rsource "Kconfig.powerseq"
+rsource "Kconfig.pmic"
+rsource "Kconfig.mkbp_event"
+rsource "Kconfig.motionsense"
+rsource "Kconfig.random"
+rsource "Kconfig.rsa"
+rsource "Kconfig.rtc"
+rsource "Kconfig.stacks"
+rsource "Kconfig.system"
+rsource "Kconfig.tasks"
+rsource "Kconfig.temperature"
+rsource "Kconfig.timer"
+rsource "Kconfig.throttle_ap"
+rsource "Kconfig.touchpad"
+rsource "Kconfig.usba"
+rsource "Kconfig.usbc"
+rsource "Kconfig.watchdog"
+rsource "Kconfig.wireless_charger"
+
+# Define PLATFORM_EC_... options to enable EC features. Each Kconfig should be
+# matched by a line in zephyr/shim/include/config_chip.h which #defines the
+# corresponding EC CONFIG if this Kconfig is enabled.
+#
+# Please keep these in alphabetical order
+
+config PLATFORM_EC_CUSTOMIZED_DESIGN
+	bool "Enabled the customized design in common code"
+	default n
+	help
+	  Enable the customized design in common code.
+	  This config is only used at non-chromeOS project.
+
+config PLATFORM_EC_GPU
+	bool "Project supports the GPU board"
+	default n
+	help
+	  Project supports the GPU board.
+	  Enable this config to call the GPU related function.
+
+config PLATFORM_EC_ACPI
+	bool "Advanced Confiugration and Power Interface (ACPI)"
+	default y if AP_X86 && PLATFORM_EC_HOST_INTERFACE_ESPI
+	help
+	  Enable the Advanced Configuration and Power Interface (ACPI) in the
+	  EC. ACPI is a standard interface to the Application Processor (AP)
+	  that abstracts the hardware specific details for controlling and
+	  managing the board.
+
+	  This includes interfaces for monitoring or controlling features,
+	  including:
+	    keyboard backlight
+	    fan speed
+	    temperature sensors
+	    charging properties
+	    device orientation (tablet or laptop mode)
+
+	  https://uefi.org/sites/default/files/resources/ACPI_Spec_6_4_Jan22.pdf
+
+config PLATFORM_EC_AP_RESET_LOG
+	bool "Enable the Application Processor reset log"
+	depends on PLATFORM_EC_HOSTCMD_GET_UPTIME_INFO
+	default y if PLATFORM_EC_POWERSEQ
+	help
+	  Enable logging of AP reset events. This information is provided in
+	  response to the EC_CMD_GET_UPTIME_INFO host command.
+
+config PLATFORM_EC_BACKLIGHT_LID
+	bool "Control the display backlight based on the lid switch"
+	depends on PLATFORM_EC_HOSTCMD
+	default y
+	help
+	  Support controlling the display backlight based on the state of the
+	  lid switch. The EC will disable the backlight when the lid is closed.
+
+	  This option enables the EC_CMD_SWITCH_ENABLE_BKLIGHT host command,
+	  which allows the AP to override the backlight setting until the next
+	  change in the lid state.
+
+config PLATFORM_EC_BACKLIGHT_LID_ACTIVE_LOW
+	bool "Control for the display backlight is active low"
+	depends on PLATFORM_EC_BACKLIGHT_LID
+	help
+	  Support controlling the backlight with an active low GPIO signal.
+          This config option expects a GPIO_ENABLE_BACKLIGHT_L defined.
+
+config PLATFORM_EC_BOARD_RESET_AFTER_POWER_ON
+	bool "Work around H1 reset issue"
+	help
+	  Enable this if H1 resets the EC after power-on. This is needed so the EC
+	  can delay its start-up until the reset happens. Without this option
+	  the EC starts up, performs some amount of processing and then gets a
+	  reset that it is not expecting.
+
+config PLATFORM_EC_BOOT_NO_SLEEP
+	bool "Disable deep sleep after boot"
+	default y if !ZTEST
+	help
+	  Disable deep sleep for PLATFORM_EC_BOOT_NO_SLEEP_MS after boot.
+
+config PLATFORM_EC_BOOT_NO_SLEEP_MS
+	int "No deep sleep after boot duration"
+	default 15000
+	help
+	  Duration for PLATFORM_EC_BOOT_NO_SLEEP in ms.
+
+config PLATFORM_EC_WAIT_RESET_CYCLES_PER_ITERATION
+	int "CPU execution cycle per iteration for waiting the H1 reset"
+	default 4
+	depends on PLATFORM_EC_BOARD_RESET_AFTER_POWER_ON
+	help
+	  This options specifies the number of CPU execution cycles per delay
+	  loop iteration, while waiting for the H1 to reset.
+
+config PLATFORM_EC_PREINIT_HW_CYCLES_PER_SEC
+	int "CPU power up clock cycle per second"
+	default 100000000
+	depends on PLATFORM_EC_BOARD_RESET_AFTER_POWER_ON
+	help
+	  This option specifies the frequency (in Hz) of the CPU core when
+	  coming out of a power on reset.
+
+config PLATFORM_EC_BRINGUP
+	bool "Enable early bringup debugging features"
+	help
+	  Enable the CONFIG_BRINGUP platform/ec configuration option,
+	  turning on a variety of miscellaneous early bringup
+	  debugging features.
+
+	  These features include:
+	  - The device will not power on when the EC starts.  The
+	    power button will need to be pressed, or the "powerbtn"
+	    command issued.
+	  - Enable power signal logging, showing relative timestamps
+	    for each power signal change.
+	  - And more!  You can search the codebase for CONFIG_BRINGUP
+            to see all of the features this flag will toggle.
+
+config PLATFORM_EC_CHIPSET_RESET_HOOK
+	bool "Provide a hook for when the AP resets"
+	default y
+	help
+	  Enables support for the legacy HOOK_CHIPSET_RESET hook.
+	  This can be used by code that needs to run before a programmatic
+	  reset actually happens.  Note that these hooks don't run with a
+	  cold reset, only when the AP decides to reset itself.
+
+	  The hook is shimmed into the AP callback API, so you can
+	  set up a ap_power_ev_callback with the AP_POWER_RESET
+	  event to call a handler when the AP is about to be reset.
+
+config PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK
+	bool "Enable chipset resume-init and suspend-complete hooks"
+	help
+	  Enables support for the HOOK_CHIPSET_RESUME_INIT and
+	  HOOK_CHIPSET_SUSPEND_COMPLETE hooks. These hooks are usually used to
+	  initialize/disable the SPI driver, which goes to sleep on suspend.
+	  Require to initialize it first such that it can receive a host resume
+	  event, that notifies the normal resume hook.
+	  The legacy hooks are shimmed into the AP callback API, so
+	  a ap_power_ev_callback can be set up with the events
+	  AP_POWER_RESUME_INIT and AP_POWER_SUSPEND_COMPLETE to
+	  call a handler when these events are triggered.
+
+config PLATFORM_EC_CHIP_INIT_ROM_REGION
+	bool "Enables the use of a dedicated init ROM region"
+	help
+	  Enable this flag if the board has a `.init_rom` region. This will
+	  activate routines in `init_rom.h` to access objects in this region.
+
+config PLATFORM_EC_CMD_GPIO_EXTENDED
+	bool "Console command: gpioset"
+	default n
+	help
+	  Enable the `gpioset name <value> abilities.
+
+	  NOTE: This flag should be removed on a shipping device.
+
+config PLATFORM_EC_CMD_POWERINDEBUG
+	bool "Console command: powerindebug"
+	default y
+	help
+	  Enable the `powerindebug` console command. This command is used to
+	  get and set power signal. This flag should be disabled on a shipping
+	  device.
+
+config PLATFORM_EC_CONSOLE_CMD_HCDEBUG
+	bool "Console command: hcdebug"
+	default y
+	depends on PLATFORM_EC_HOSTCMD
+	help
+	  Enable the 'hcdebug' console command. This comamnd is used to change,
+	  at runtime, the amount of debug generated by the host command
+	  processing.
+
+	    hcdebug [off | normal | every | params]
+
+	  See PLATFORM_EC_HOSTCMD_DEBUG_MODE_CHOICE for more detail.
+
+config PLATFORM_EC_CONSOLE_CMD_IRQ
+	bool "Console command: irq"
+	depends on TRACING_ISR && TRACING_USER
+	help
+	  Enable the "irq" console command. This command lists the number of
+	  IRQ calls.
+
+config PLATFORM_EC_CONSOLE_CMD_MEM
+	bool "Console command: md, rw"
+	default y
+	help
+	  Enable memory related console commands.
+
+	     md - dump memory values
+	     rw - read or write in memory
+
+config PLATFORM_EC_CONSOLE_CMD_SLEEPMASK
+	bool "Console command: sleepmask read"
+	default y if PM
+	help
+	  Enable the 'sleepmask' console command. This command is used to
+	  display the state of the sleep mask, which controls whether the EC
+	  chip is allowed to enter deep sleep states to save power.
+
+config PLATFORM_EC_CONSOLE_CMD_SLEEPMASK_SET
+	bool "Console command: sleepmask set"
+	depends on PLATFORM_EC_CONSOLE_CMD_SLEEPMASK
+	default y
+	help
+	  Enable changing the state of the current sleep mask.
+
+	    sleepmask on     -  Sets the SLEEP_MASK_FORCE_NO_DSLEEP bit in the
+	                        sleep mask, preventing the system from entering
+	                        sleep.
+	    sleepmask off    -  Clears the SLEEP_MASK_FORCE_NO_DSLEEP bit in the
+	                        sleep mask. The system may enter deep sleep
+	                        depending on the state of other mask bits.
+	    sleepmask <value> - Sets the sleepmask to <value>, overriding all
+	                        bits with the specified value.
+
+config PLATFORM_EC_CONSOLE_CMD_S5_TIMEOUT
+	bool "Console command: s5_timeout"
+	default n
+	help
+	  This command allows the user to specify a time to remain in S5 before
+	  dropping to G3, in order to help power testing.
+
+config PLATFORM_EC_CONSOLE_CMD_SHMEM
+	bool "Console command: shmem"
+	default y
+	help
+	  This command prints basic information about the EC shared memory,
+	  located at the top of RAM, above all RAM symbols: total size, bytes
+	  used and the maximum number of bytes that have been used since
+	  the EC started running.
+
+config PLATFORM_EC_CROS_FWID_VERSION
+	bool "Include CrOS FWID version"
+	default n
+	help
+	  Include Chrome OS FWID in version output. The CrOS FWID will be common
+	  across OS, AP firmware and EC firmware when built together.
+
+config PLATFORM_EC_DEBUG_ASSERT
+	bool "Enable assertion failures"
+	default n
+	select ASSERT
+	help
+	  Assertion failures are used to flag conditions which should not occur
+	  and thus indicate the software is unable to continue execution. This
+	  option can be disabled so that the assert() macro becomes a NOP. In
+	  this case, execution will continue but the results are unpredictable.
+
+	  Messages are of the form:
+
+	     ASSERTION FAILURE '<expr>' in function() at file:line
+
+	  Note: There is also ASSERT() which is an alias of assert(), used in
+	  host code where cstdlib is used.
+
+config PLATFORM_EC_DP_REDRIVER_TDP142
+	bool "Include TDP142 DisplayPort redriver driver"
+	default n
+	help
+	  Include a driver for the Texas Instruments TDP142 DisplayPort linear
+	  redriver chip.
+
+config PLATFORM_EC_EMULATED_SYSRQ
+	bool "Emulate sysrq events to AP"
+	help
+	  The magic SysRq key is a key combo which allows the user to perform
+	  various low-level commands regardless of the system's state.
+
+	  See here for the key combos:
+
+	  https://www.kernel.org/doc/html/latest/admin-guide/sysrq.html
+
+	  This option enables support for sending emulated SysRq events to AP
+	  (on designs with a keyboard, SysRq is passed as normal key presses).
+
+config PLATFORM_EC_EXTPOWER
+	bool "Support external power detection"
+	depends on PLATFORM_EC_HOOKS && PLATFORM_EC_HOSTCMD
+	help
+	  Enable code for handling the detection of external power.
+	  If PLATFORM_EC_EXTPOWER_GPIO is not set, then the board
+	  must supply the function board_check_extpower in order
+	  to check for external power, and update the state via
+	  extpower_handle_update().
+
+config PLATFORM_EC_EXTPOWER_GPIO
+	bool "GPIO-based external power detection"
+	select PLATFORM_EC_EXTPOWER
+	depends on PLATFORM_EC_HOOKS && PLATFORM_EC_HOSTCMD
+	help
+	  Enable shimming the extpower_gpio module, which provides
+	  GPIO-based external power presence detection features.  The
+	  project should define a GPIO pin named GPIO_AC_PRESENT, with
+	  extpower_interrupt configured as the handler.
+
+config PLATFORM_EC_EXTPOWER_DEBOUNCE_MS
+	int "Debounce time for external power signal"
+	default 30
+	help
+	  Enable external power signal debounce time. Extend the
+	  debounce time to ensure that the external power signal can
+	  supply stable power.
+
+config PLATFORM_EC_FLASH_CROS
+	bool
+	help
+	  Enables access to the device's flash through a simple API. With
+	  this is it possible for the EC to update its flash while running,
+	  e.g. to support auto-update. Various write-protection features are
+	  also provided.
+
+config PLATFORM_EC_FLASH_PROTECT_DEFERRED
+	bool "Enable Async Flash Protect"
+	help
+	  Enable the async version of the FLASH_PROTECT command. This uses
+	  a deferred flash_protect_set.
+
+config PLATFORM_EC_HOOKS
+	bool "Hooks and deferred compatibility shim"
+	default y
+	help
+	  Enable translation of DECLARE_DEFERRED() and hook_call_deferred()
+	  to Zephyr's work queues, along with a compatible DECLARE_HOOK
+	  implementation.
+
+	  This option is needed by many features in the EC. Disabling it will
+	  likely cause build errors.
+
+menuconfig PLATFORM_EC_HOSTCMD
+	bool "Host commands"
+	default n if ARCH_POSIX
+	default y if AP
+	select HAS_TASK_HOSTCMD
+	help
+	  Enable the host commands shim in platform/ec. This handles
+	  communication with the AP. The AP sends a command to the EC and it
+	  responds when able. An interrupt can be used to indicate to the AP
+	  that the EC has something for it.
+
+	  The host interface type is selected based on the AP type, but can be
+	  changed though the CONFIG_PLATFORM_EC_HOST_INTERFACE_TYPE choice.
+
+config PLATFORM_EC_HOSTCMD_GET_UPTIME_INFO
+	bool "Host command: EC_CMD_GET_UPTIME_INFO"
+	default PLATFORM_EC_HOSTCMD
+	help
+	  Enable the EC_CMD_GET_UPTIME_INFO host command which reports the time
+	  the EC has been powered up, the number of AP resets, an optional log
+	  of AP-reset events and some flags.
+
+config PLATFORM_EC_HOSTCMD_REGULATOR
+	bool "Host command of voltage regulator control"
+	help
+	  Enable host commands (EC_CMD_REGULATOR_) for controlling voltage
+	  regulator. The board should also implement board functions defined in
+	  include/regulator.h.
+
+config PLATFORM_EC_HOSTCMD_DEBUG_MODE
+	int
+	default 0 if HCDEBUG_OFF
+	default 1 if HCDEBUG_NORMAL
+	default 2 if HCDEBUG_EVERY
+	default 4 if HCDEBUG_PARAMS
+	default 0
+	help
+	  This is a helper symbol that sets the host command debug level as an
+	  integer value.  This symbol is set automatically based on the
+	  configuration of PLATFORM_EC_HOSTCMD_DEBUG_MODE_CHOICE.
+
+choice PLATFORM_EC_HOSTCMD_DEBUG_MODE_CHOICE
+	prompt "Select method to use for HostCmd Debug Mode"
+	depends on PLATFORM_EC_HOSTCMD
+	default HCDEBUG_NORMAL
+	help
+	  Sets the value of the host command debug mode to use on
+	  startup.
+
+config HCDEBUG_OFF
+	bool "Host command debug mode OFF"
+	help
+	  No host command debug messages are shown.  Host
+	  command error messages will still output.
+
+config HCDEBUG_NORMAL
+	bool "Host command debug mode NORMAL"
+	help
+	  Display host commands receieved from the AP. Repeated
+	  commands are shown with a "+" and "++" symbol.
+
+config HCDEBUG_EVERY
+	bool "Host command debug mode EVERY"
+	help
+	  Display all host commands received from the AP,
+	  including repeated commands.
+
+config HCDEBUG_PARAMS
+	bool "Host command debug mode PARAMS"
+	help
+	  Display all host commands and the parameters received
+	  from the AP.
+
+endchoice # PLATFORM_EC_HOSTCMD_DEBUG_MODE_CHOICE
+
+config PLATFORM_EC_LID_SWITCH
+	bool "Lid switch"
+	help
+	  Enable shimming the lid switch implementation and related
+	  commands in platform/ec. The lid switch can affect power-on
+	  behaviour. For example, when the lid is opened, the device may
+	  automatically power on.
+
+	  This requires a GPIO named GPIO_LID_OPEN to be defined or aliased.
+
+config MKBP_PROTOCOL
+	bool "MKBP protocol support"
+	help
+	  Enable the MKBP support protocol code.
+
+config PLATFORM_EC_MKBP_INPUT_DEVICES
+	bool "Input devices via MKBP"
+	select MKBP_PROTOCOL
+	help
+	  Enable passing events from various input sources to AP via MKBP.
+	  This include buttons (power, volume); switches (lid, tablet mode)
+	  and sysrq.
+
+config PLATFORM_EC_LOW_POWER_IDLE
+	bool
+	default y if PM
+	help
+	  Enable low power idle modes in the EC chipset. This is automatically
+	  enabled when the Zephyr power management options are enabled with the
+	  PM option.
+
+config PLATFORM_EC_LOW_POWER_S0
+	bool "Enable deep sleep during S0"
+	help
+	  Enable deep sleep during S0 (ignores SLEEP_MASK_AP_RUN).
+
+config PLATFORM_EC_POWER_COMMON
+	bool
+	default y
+	depends on PLATFORM_EC_POWERSEQ
+	help
+	  Compile common code for AP power state machine.
+
+config CROS_EC_POWER_SIGNAL_LIST
+	bool "Define the power signal list from the devicetree"
+	default y
+	depends on $(dt_nodelabel_enabled,power_signal_list)
+	help
+	  Define the global power_signal_list[] from the devicetree. Requires a
+	  node with nodelabel power_signal_list.
+
+config PLATFORM_EC_MKBP_EVENT
+    bool "MKBP event"
+    help
+      Enable this to support MKBP event. MKBP event is used not only
+      for matrix keyboard but also for other many events like button,
+      switch, fingerprint, and etc.
+
+      This requires a MKBP event delivery method(GPIO, HOST_EVENT, and etc)
+
+config PLATFORM_EC_MKBP_EVENT_WAKEUP_MASK
+    bool
+    default y
+    depends on DT_HAS_CROS_EC_MKBP_EVENT_WAKEUP_MASK_ENABLED
+    depends on PLATFORM_EC_MKBP_EVENT
+    help
+      Enable which MKBP events should wakeup the system in suspend.
+      For example:
+        The MKBP events are enabled in the devicetree by the wakeup-mask
+        property of the ec-mkbp-event-wakeup-mask node as follows:
+        wakeup-mask = <(MKBP_EVENT_KEY_MATRIX | \
+                          MKBP_EVENT_HOST_EVENT | \
+                          MKBP_EVENT_SENSOR_FIFO)>;
+      The mkbp events are defined in dt-bindings/wake_mask_event_defines.h
+
+config PLATFORM_EC_MKBP_HOST_EVENT_WAKEUP_MASK
+    bool
+    default y
+    depends on DT_HAS_CROS_EC_MKBP_HOST_EVENT_WAKEUP_MASK_ENABLED
+    depends on PLATFORM_EC_MKBP_EVENT
+    help
+      Enable which host events should wakeup the system in suspend.
+      For example:
+        The host events are enabled in the devicetree by the wakeup-mask
+        property of the ec-mkbp-host-event-wakeup-mask node as follows:
+          wakeup-mask = <(HOST_EVENT_LID_OPEN | \
+                          HOST_EVENT_POWER_BUTTON | \
+                          HOST_EVENT_AC_CONNECTED)>;
+      The host events are defined in dt-bindings/wake_mask_event_defines.h
+
+config PLATFORM_EC_PANIC
+	bool "Panic output"
+	default y
+	help
+	  Enable support for collecting and reporting panic information,
+	  caused by exceptions in the EC. This can be the result of a watchdog
+	  firing, a division by zero, unaligned access, stack overflow or
+	  assertion failure.
+
+	  The panic information is made available to the AP via the
+	  EC_CMD_GET_PANIC_INFO host command and a 'panicinfo' console command
+
+config PLATFORM_EC_PORT80
+	bool "Port 80 support"
+	default y if AP_X86 && PLATFORM_EC_POWERSEQ
+	help
+	  Enable the port80 module, a way to report progress of the AP's boot
+	  sequence, assuming that the EC can detect these writes on the I/O
+	  bus. The EC buffers calls to port_80_write() and occasionally prints
+	  a message when there are new writes.
+
+	  See here for more information:
+
+	  https://en.wikipedia.org/wiki/Power-on_self-test#Progress_and_error_reporting
+
+config PLATFORM_EC_POWER_BUTTON
+	bool "Power-button support"
+	depends on PLATFORM_EC_HOSTCMD && !INPUT_GPIO_KEYS
+	help
+	  Enable shimming the power button implementation and related
+	  commands in platform/ec.  This is used to implement the Chromium OS
+	  shutdown sequence.
+
+	  This requires a GPIO named GPIO_POWER_BUTTON_L.
+
+config PLATFORM_EC_POWER_BUTTON_IGNORE_LID
+	bool "Ignore lid switch for power button press"
+	default y if !PLATFORM_EC_LID_SWITCH
+	depends on PLATFORM_EC_POWER_BUTTON
+	help
+	  Don't check for lid_is_open when processing power button presses.
+	  This option should be used when power button support is required,
+	  but there is no lid switch present.
+
+config PLATFORM_EC_BUTTON_DEBOUNCE
+	int "button debounce in us"
+	default 30000
+	help
+	  Configure the button debounce time in us per project requirement.
+
+config PLATFORM_EC_PSE_LTC4291
+	bool "power sourcing equipment (PSE)  support"
+	help
+	  Enable the power sourcing equipment (PSE) driver support for
+	  Analog Device power over ethernet (PoE) power sourcing equipment (PSE)
+	  controller.
+
+config PLATFORM_EC_PWM_HC
 	bool
+	help
+	  Enable the PWM (Pulse Width Modulation) host command support. This
+	  implements EC_CMD_PWM_SET_DUTY and EC_CMD_PWM_GET_DUTY.
+
+config PLATFORM_EC_PWM_DISPLIGHT
+	bool "PWM display backlight"
 	default y
+	depends on DT_HAS_CROS_EC_DISPLIGHT_ENABLED
+	select PWM
+	select PLATFORM_EC_PWM_HC
 	help
-	  This should always be enabled.  It's a workaround for
-	  config.h not being available in some headers.
+	  Enables display backlight controlled by a PWM signal connected
+	  directly to the EC chipset. The board devicetree file must define a
+	  "cros-ec,displight" compatible device node.
+
+CHOSEN_CROS_RTC := cros,rtc
+
+config PLATFORM_EC_RTC
+	bool "Real-time clock (RTC)"
+	depends on $(dt_chosen_enabled,$(CHOSEN_CROS_RTC))
+	help
+	  Enable support for a real-time clock. Typically this is available
+	  on-chip in the EC. It provides a way to track the passage of time
+	  in terms of second and minutes. Once set, and provided that it has a
+	  suitable power source, it should be able to keep reasonably accurate
+	  time over a period of days and weeks.
+
+	  The starting EC clock is typically set by the AP, since it has access
+	  to the outside world and can often obtain the current time when
+	  desired.
+
+# Workaround for not being able to have commas in macro arguments
+DT_CHOSEN_CROS_EC_SHA := cros-ec,sha
+
+config PLATFORM_EC_SHA256_HW_ZEPHYR
+	bool
+	default "$(dt_chosen_enabled,$(DT_CHOSEN_CROS_EC_SHA))"
+	select CRYPTO
+	help
+	  Use the Zephyr crypto_sha driver to compute SHA256 hashing.
+	  Enabling this config implies PLATFORM_EC_SHA256_HW_ACCELERATE is
+	  selected.
+
+choice PLATFORM_EC_SHA256_MODE
+	prompt "Select method to use for computing SHA256 hashes"
+	default PLATFORM_EC_SHA256_HW_ACCELERATE if $(dt_chosen_enabled,$(DT_CHOSEN_CROS_EC_SHA))
+	help
+	  The verified boot mechanism requests the hash of the entire read-write
+	  portion of the EC image. This is typically done using a hashing block
+	  in the EC, so that it is as fast as possible. A fallback software
+	  algorithm is available if needed.
+
+config PLATFORM_EC_SHA256_SW
+	bool "Compute SHA256 in software"
+	help
+	  Enable this if your EC chip does not support hardware-accelerated
+	  SHA256 computation. This enables the software algorithm which is
+	  quite slow but will work in a pinch.
+
+config PLATFORM_EC_SHA256_HW_ACCELERATE
+	bool "Compute SHA256 in hardware"
+	help
+	  Enable this if your EC chip supports hardware-accelerated SHA256
+	  computation. This is faster than running the algorithm in software,
+	  so is desirable.
+
+	  The chip support must implement the functions in sha256.h
+
+endchoice # PLATFORM_EC_SHA256_MODE
+
+config PLATFORM_EC_SHA256_UNROLLED
+	bool "Manually unroll sha256 transform"
+	depends on PLATFORM_EC_SHA256_SW
+	default n
+	help
+	  Enable loop unroll to improve the performance of sha256 software
+	  decoding.
+
+config PLATFORM_EC_SWITCH
+	bool "Memory mapped switches"
+	depends on PLATFORM_EC_HOSTCMD
+	default y
+	help
+	  Enable the reporting of the platform switches state to the AP using
+	  memory mapped storage provided by the host command interface.
+
+	  The platform switches include:
+	    LID open
+	    power button pressed
+	    write protect disabled
+	    recovery switch
+
+          This also enables the "mmapinfo" console command to report the current
+          state of all switches.
+
+config PLATFORM_EC_SWITCHCAP_GPIO
+	bool "GPIO controlled switchcap"
+	default y
+	depends on DT_HAS_CROS_EC_SWITCHCAP_GPIO_ENABLED
+	help
+	  Enable support for the GPIO controlled switchcap.
+	  Pins used for controlling the switchcap must be defined in board's
+	  device tree.
+
+config PLATFORM_EC_SWITCHCAP_LN9310
+	bool "LN9310 switchcap common code"
+	help
+	  Enable support for the LION Semiconductor LN9310 switched
+	  capacitor converter.  This will export definitions for
+	  ln9310_init, ln9310_interrupt, and ln9310_power_good, which
+	  project-specific code should call appropriately if there's
+	  no switchcap node in device tree.
+
+config CROS_EC_SWITCHCAP_LN9310
+	bool "LN9310 switchcap generic driver"
+	default y
+	depends on DT_HAS_LION_LN9310_ENABLED
+	help
+	  Enable support for the generic driver for the LION Semiconductor
+	  LN9310 switched capacitor converter. This requires a lion,ln9310 node
+	  to be defined.
+
+config PLATFORM_EC_SYSTEM_UNLOCKED
+	bool "System unlocked: allow dangerous commands while in development"
+	default y if PLATFORM_EC_BRINGUP
+	help
+	  System should remain unlocked even if write protect is enabled.
+
+	  NOTE: This should ONLY be defined during bringup, and should never be
+	  defined on a shipping / released platform.
+
+	  When defined, CBI allows ectool to reprogram all the fields.
+	  Normally, it refuses to change certain fields. (e.g. board version,
+	  OEM ID)
+
+	  Also, this enables PD in RO for TCPMv2.
+
+config PLATFORM_EC_THROTTLE_AP
+	bool "CPU throttling"
+	help
+	  Enable throttling the CPU. When triggered this reduces the CPU's
+	  power output and eventually results in a lower temperature.
+
+if PLATFORM_EC_THROTTLE_AP
+
+config PLATFORM_EC_THROTTLE_AP_SINGLE_PIN
+	bool "CPU throttling and interrupt detection on a single pin"
+	help
+	  Enable detection of throttling interrupts on the same pin used to
+	  trigger throttling. The GPIO should be configured as an output by
+	  default. throttle_ap_config_prochot will configure the GPIO as
+	  an interrupt. Chipset specific functions are responsible for
+	  handling any subsequent changes.
+
+config PLATFORM_EC_THROTTLE_AP_NO_FAN
+	bool "No automatic fan control for AP throttling"
+	help
+	  Disable automatic fan control when an AP throttling interrupt occurs
+
+config PLATFORM_EC_CONSOLE_CMD_APTHROTTLE
+	bool "Enable apthrottle command to disable throttling state"
+	default n
+
+endif #PLATFORM_EC_THROTTLE_AP
 
 menuconfig PLATFORM_EC_TIMER
-	bool "Enable the EC timer module"
+	bool "Timer module"
 	default y
 	help
-	  Enable compilation of the EC timer module
+	  Enable compilation of the EC timer module. This provides support for
+	  delays, getting the current time and setting alarms.
 
-if PLATFORM_EC_TIMER
+	  This option is needed by many features in the EC. Disabling it will
+	  likely cause build errors.
 
-config PLATFORM_EC_TIMER_CMD_GETTIME
-	bool "Enable the gettime command"
+config PLATFORM_EC_VBOOT_EFS2
+	bool "EFS2 verified EC boot"
+	default y if !SOC_POSIX
+	help
+	  Enables Early Firmware Selection v2 (EFS2) verified boot. When booting
+	  a Chromium OS image we're actually packing both an RO image and an RW
+	  image into flash. The RO image is loaded first. EFS2 runs at boot and
+	  verifies the integrity of the RW image by sending a hash of the image
+	  to the Google Security Chip (GSC). Once the GSC verifies the hash,
+	  EFS2 calls sysjump and reboot the EC using the RW image.
+
+config PLATFORM_EC_VBOOT_HASH
+	bool "Host command: EC_CMD_VBOOT_HASH"
+	depends on PLATFORM_EC_HOSTCMD
 	default y
 	help
-	  Enable the "gettime" command
+	  Allows the AP to request hashing functions from the EC.
 
-config PLATFORM_EC_TIMER_CMD_TIMERINFO
-	bool "Enable the timerinfo command"
+	  Verified boot can update the EC's read/write code when it detects
+	  that it is an incorrect version. It detects this by asking the EC to
+	  hash itself. If the hash is incorrect, new code is write to the EC's
+	  read/write area.
+
+config PLATFORM_EC_VSTORE
+	bool "Secure temporary storage for verified boot"
 	default y
 	help
-	  Enable the "timerinfo" command
+	  Enable support for storing a block of data received from the AP so it
+	  can be read back later by the AP. This is helpful since the AP may
+	  reboot or resume and want the data early in its start-up before it
+	  has access to SDRAM.
+
+	  There are a fixed number of slots and each can hold a fixed amount of
+	  data (EC_VSTORE_SLOT_SIZE bytes). Once a slot is written it is locked
+	  and cannot be written again unless explicitly unlocked.
+
+	  Stored data is preserved when the EC moved from RO to RW.
+
+config PLATFORM_EC_VSTORE_SLOT_COUNT
+	int "Number of slots"
+	depends on PLATFORM_EC_VSTORE
+	default 1
+	help
+	  Set the number of slots available in the verified-boot store. The
+	  number required depends on the AP firmware. Typically the vstore is
+	  used only for recording a hash of the read-write AP firmware for
+	  checking on resume. For this, one slot is enough.
+
+config PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API
+	bool "Workaround needed for npcx9 ES1 chip"
+	depends on SOC_SERIES_NPCX9
+	help
+	  There's a bug in the flash download API on the ES1 version of the
+	  npcx9 chips that requires some workarounds. This is needed for sysjump
+	  to work properly.
+
+config PLATFORM_EC_ASSERT_CCD_MODE_ON_DTS_CONNECT
+	bool "Assert CCD Mode"
+	help
+	  Assert CCD_MODE_ODL when a DTS debug accessory is connected to the
+	  CCD USBC port. GPIO_CCD_MODE_ODL should be configured with
+	  GPIO_ODR_HIGH flag.
+
+config PLATFORM_EC_CCD_USBC_PORT_NUMBER
+	int "CCD USB Port Number"
+	default 0
+	help
+	  USB port number of the CCD enabled USBC port.
+
+config PLATFORM_EC_HOST_COMMAND_STATUS
+	bool "Return in-progress status for slow host commands"
+	default y if PLATFORM_EC_HOST_INTERFACE_SHI
+	help
+	  When the AP is attached to the EC via a serialized bus such as I2C or
+	  SPI, it needs a way to minimize the length of time an EC command will
+	  tie up the bus (and the kernel driver on the AP). If this config is
+	  defined, the EC may return an in-progress result code for slow
+	  commands such as flash erase/write instead of stalling until the
+	  command finishes processing, and the AP may then inquire the status
+	  of the current command and/or the result of the previous command.
 
-config PLATFORM_EC_TIMER_CMD_WAITMS
-	bool "Enable the waitms command"
+config PLATFORM_EC_AMD_SB_RMI
+	bool "Enable driver for AMD SB-RMI interface"
+	help
+	  AMD platforms provide the Side-Band Remote Management Interface.
+	  SB-RMI provides an interface for an external SMBus controller to
+	  perform tasks such as managing power consumption and power limits of
+	  the CPU socket.
+
+config PLATFORM_EC_AMD_STB_DUMP
+	bool "Enable STB dumping feature"
+	help
+	  Enable STB dumping when AP hangs during suspend/resume.
+
+config PLATFORM_EC_AMD_STB_DUMP_CMD
+	bool "Enable `amdstbdump` console command"
+	depends on PLATFORM_EC_AMD_STB_DUMP
+	help
+	  Enables the `amdstbdump` command to manually trigger an STB dump.
+
+config PLATFORM_EC_AMD_STT
+	bool "Enable driver for AMD STT interface"
+	depends on PLATFORM_EC_AMD_SB_RMI
+	help
+	  AMD platforms provide the Skin Temperature Tracking (STT) interface.
+	  Skin temperature management can be used to maximize the system
+	  performance while keeping the skin temperature within its
+	  specification. It makes use of the thermal capacitance of the system
+	  to temporarily boost above the sustainable power limit, while the
+	  chassis skin temperatures are below limits.
+
+config PLATFORM_EC_MATH_UTIL
+	bool "Math utility"
+	default y
+	help
+	  Math utilities including bitmask manipulation, division rounding,
+	  trigonometric function, etc.
+
+config PLATFORM_EC_GPIO_ID
+        bool "Enable GPIO ID handling for board and sku ids"
 	default y
+	depends on DT_HAS_CROS_EC_GPIO_ID_ENABLED
 	help
-	  Enable the "waitms" command
+	  Enable setting board and sku IDs using GPIOs. Defines the
+	  board_get_sku_id and board_get_version functions based on the
+	  devicetree node using the known nodelabels gpio_id_sku and
+	  gpio_id_board.
 
-endif # PLATFORM_EC_TIMER
+config PLATFORM_EC_UNIMPLEMENTED_GPIO
+        bool "Remove pin control in Zephyr code"
+	default n
+	help
+	  In Zephyr shim, some gpios should not be controlled if project
+	  does not implement this pin.
+
+config SYSTEM_BOOT_TIME_LOGGING
+	bool "boot time logging"
+	help
+	  This config enables boot time logging functionality in EC which
+	  is used for calculating system boot time.
 
 endif # PLATFORM_EC
diff --git a/zephyr/Kconfig.accelgyro_bmi b/zephyr/Kconfig.accelgyro_bmi
new file mode 100644
index 0000000000..e08ba08838
--- /dev/null
+++ b/zephyr/Kconfig.accelgyro_bmi
@@ -0,0 +1,33 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+
+if PLATFORM_EC_ACCELGYRO_BMI
+menu "BMI Sensor Common"
+
+choice PLATFORM_EC_ACCELGYRO_BMI_COMM
+	prompt "Accelgyro BMI's communication mode"
+	help
+	  When using the BMI drivers, there's the option to communicate with the
+	  chip via several methods. This choice helps improve code size by only
+	  compiling the needed communication channels.
+
+config PLATFORM_EC_ACCELGYRO_BMI_COMM_SPI
+	bool "Use SPI communication"
+	help
+	  The BMI chip is using SPI communication. This config value is used to
+	  save on code size as only the SPI communication code will be included
+	  for the BMI chip.
+
+config PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C
+	bool "Use I2C communication"
+	help
+	  The BMI chip is using I2C communication. This config value is used to
+	  save on code size as only the I2C communication code will be included
+	  for the BMI chip.
+
+endchoice
+
+endmenu # BMI Sensor
+endif # PLATFORM_EC_ACCELGYRO_BMI
\ No newline at end of file
diff --git a/zephyr/Kconfig.accelgyro_icm b/zephyr/Kconfig.accelgyro_icm
new file mode 100644
index 0000000000..a8b52c0d38
--- /dev/null
+++ b/zephyr/Kconfig.accelgyro_icm
@@ -0,0 +1,33 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+
+if PLATFORM_EC_ACCELGYRO_ICM
+menu "ICM Sensor Common"
+
+choice PLATFORM_EC_ACCELGYRO_ICM_COMM
+	prompt "Accelgyro ICM's communication mode"
+	help
+	  When using the ICM drivers, there's the option to communicate with the
+	  chip via several methods. This choice helps improve code size by only
+	  compiling the needed communication channels.
+
+config PLATFORM_EC_ACCELGYRO_ICM_COMM_SPI
+	bool "Use SPI communication"
+	help
+	  The ICM chip is using SPI communication. This config value is used to
+	  save on code size as only the SPI communication code will be included
+	  for the ICM chip.
+
+config PLATFORM_EC_ACCELGYRO_ICM_COMM_I2C
+	bool "Use I2C communication"
+	help
+	  The ICM chip is using I2C communication. This config value is used to
+	  save on code size as only the I2C communication code will be included
+	  for the ICM chip.
+
+endchoice
+
+endmenu # ICM Sensor
+endif # PLATFORM_EC_ACCELGYRO_ICM
\ No newline at end of file
diff --git a/zephyr/Kconfig.adc b/zephyr/Kconfig.adc
new file mode 100644
index 0000000000..37245f5070
--- /dev/null
+++ b/zephyr/Kconfig.adc
@@ -0,0 +1,65 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config NAMED_ADC_CHANNELS
+	bool "Named ADC Channels support"
+	default y
+	depends on DT_HAS_NAMED_ADC_CHANNELS_ENABLED
+	select ADC
+
+# Options using the named channels APIs.
+if NAMED_ADC_CHANNELS
+
+# Chromium EC provides it's own "adc" command.  Disable the Zephyr
+# built-in ADC shell command.
+# TODO(b:188434233) Investigate moving to zephyr adc shell
+config ADC_SHELL
+	default n
+
+config PLATFORM_EC_ADC_CMD
+	bool "ADC host/console command"
+	default y
+	help
+	  Enables support for printing ADC channels state with the "adc"
+	  console command and reading a state of ADC channel with the
+	  EC_CMD_ADC_READ host command. Replaces generic Zephyr "adc"
+	  command.
+
+endif # NAMED_ADC_CHANNELS
+
+# Options used by native drivers as well.
+if ADC
+
+config PLATFORM_EC_ADC_RESOLUTION
+	int "ADC resolution"
+	default 10
+	help
+	  The resolution, in bits, to use for the ADC conversion. Determines
+	  the sample values range: 0 .. 2^resolution -1. The supported
+	  resolution values depend on specific hardware.
+
+config PLATFORM_EC_ADC_OVERSAMPLING
+	int "ADC oversampling"
+	default 0
+	help
+	  ADC oversampling to use for the ADC conversion. Each sample is
+	  averaged from 2^oversampling conversion results. Oversampling can
+	  help in providing more stable readings. The supported oversampling
+	  values depend on specific hardware.
+
+config PLATFORM_EC_ADC_CHANNELS_RUNTIME_CONFIG
+	bool "ADC runtime config"
+	default n
+	help
+	  Allows the configuration of the ADC channels to be set up at
+	  runtime. This makes the adc_channels[] array writable,
+	  i.e. not const. It should be declared as such in the board
+	  config.
+
+	  This is useful when the board has runtime information that
+	  changes the configuration, such as board revision information.
+	  Without this, multiple EC images would need to be installed
+	  depending on the board.
+
+endif # ADC
diff --git a/zephyr/Kconfig.ap_power b/zephyr/Kconfig.ap_power
new file mode 100644
index 0000000000..1aeae88faf
--- /dev/null
+++ b/zephyr/Kconfig.ap_power
@@ -0,0 +1,75 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config AP_POWER_CONTROL
+    bool
+    default y if PLATFORM_EC_POWERSEQ || AP_PWRSEQ
+    help
+      Whether the EC has control over AP power states.
+
+      This is automatically enabled if an implementation of AP power
+      sequencing is enabled.
+
+menuconfig PLATFORM_EC_BOOT_AP_POWER_REQUIREMENTS
+	bool "Power requirements to boot AP"
+	default y
+	help
+	  Power thresholds for AP boot.
+	  If one of the following conditions is met, EC boots AP:
+	   1. Battery charge >= CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON.
+	   2. AC power >= CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON.
+	   3. Battery charge >= CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC
+	    and
+	    AC power >= CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT.
+
+if PLATFORM_EC_BOOT_AP_POWER_REQUIREMENTS
+
+config PLATFORM_EC_POWER_BUTTON_INIT_TIMEOUT
+	int "Timeout before power button task gives up starting system"
+	depends on HAS_TASK_POWERBTN || HAS_TASK_POWERBTN_CUSTOMER
+	default 1
+	help
+	  Sets the maximum time, in seconds, before the power button
+	  task stops waiting for conditions to be OK to start
+	  the system. If the timeout is reached, the AP is
+	  not started, and the power task's state is set to idle.
+
+config PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON
+	int "Minimal battery level to boot AP without AC"
+	depends on PLATFORM_EC_BATTERY
+	default 3
+	help
+	  Sets the minimum battery capacity, as a percentage, needed to boot
+	  the AP when AC power is not supplied.
+
+config PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC
+	int "Minimal battery level to boot AP with AC"
+	depends on PLATFORM_EC_BATTERY && PLATFORM_EC_CHARGE_MANAGER
+	default 1
+	help
+	  Sets the minimum battery capacity, as a percentage, needed to boot
+	  the AP when AC power is supplied. The AC power supplied must also
+	  be greater than CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT.
+
+config PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT
+	int "Minimal AC power to boot AP with battery"
+	depends on PLATFORM_EC_BATTERY && PLATFORM_EC_CHARGE_MANAGER
+	default 15000
+	help
+	  Sets the minimum power, in milliwatts, supplied by an external
+	  charger required to boot the AP when the battery capacity is also
+	  above CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC.
+
+config PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON
+	int "Minimal AC power to boot AP without battery"
+	depends on PLATFORM_EC_CHARGE_MANAGER
+	default 15000
+	help
+	  Sets the minimum power, in milliwatts, supplied by an external
+	  charger requires to boot the AP when no battery is present or
+	  under dead battery conditions. If the AP requires greater than
+	  15W to boot, check the
+	  CONFIG_PLATFORM_EC_CHARGER_LIMIT_POWER_THRESH_CHG_MW setting.
+
+endif # PLATFORM_EC_BOOT_AP_POWER_REQUIREMENTS
diff --git a/zephyr/Kconfig.battery b/zephyr/Kconfig.battery
new file mode 100644
index 0000000000..cb807406bd
--- /dev/null
+++ b/zephyr/Kconfig.battery
@@ -0,0 +1,328 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+menuconfig PLATFORM_EC_BATTERY
+	bool "Battery support"
+	default y
+	depends on DT_HAS_BATTERY_SMART_ENABLED
+	help
+	  Enables battery support on the board. Requires selection of a battery
+	  and a charger IC.
+
+	  If using I2C batteries, you must define I2C_PORT_BATTERY in your
+	  board's i2c_map.h file so that the EC code will know which I2C
+	  port the battery is on.
+
+if PLATFORM_EC_BATTERY
+
+config PLATFORM_EC_BATTERY_CONFIG_IN_CBI
+	bool "Support battery-config-in-CBI"
+	depends on CBI_EEPROM
+	help
+	  If this is enabled, a board reads battery config from CBI and updates
+	  each param in the default battery info using discovered data.
+
+config PLATFORM_EC_CONSOLE_CMD_BATTERY_CONFIG
+	bool "Console commands: bcfg"
+	depends on PLATFORM_EC_BATTERY_CONFIG_IN_CBI
+	help
+	  Enables console commands:
+
+          bcfg read | dump | reset - Read, dump, reset battery config read from
+          CBI.
+
+choice PLATFORM_EC_BATTERY_SELECT
+	prompt "Select the battery to use"
+	default PLATFORM_EC_BATTERY_SMART if DT_HAS_BATTERY_SMART_ENABLED
+	help
+	  Select the battery used on the board. If you are ensure, select the
+	  smart battery option.
+
+config PLATFORM_EC_BATTERY_SMART
+	bool "Support a smart battery"
+	select PLATFORM_EC_I2C
+	help
+	  Many batteries support the Smart Battery Specification and therefore
+	  have common registers which can be accessed to control and monitor
+	  the battery.
+
+	  See here for the spec: http://sbs-forum.org/specs/sbdat110.pdf
+
+endchoice # PLATFORM_EC_BATTERY_SELECT
+
+choice PLATFORM_EC_BATTERY_PRESENT_MODE
+	prompt "Method to use to detect the battery"
+	default PLATFORM_EC_BATTERY_PRESENT_GPIO if $(dt_path_enabled,/named-gpios/ec_batt_pres_odl)
+	help
+	  This selects the method to use to detect the presence of a battery.
+
+	  Battery detection is important since it can be used to indicate that
+	  the case is open, so security features can be disabled. It is also
+	  useful to report to the user when the battery is missing, e.g. with
+	  a desktop icon.
+
+config PLATFORM_EC_BATTERY_PRESENT_CUSTOM
+	bool "Call a board-provided function"
+	help
+	  Use this method to provide a board-provided battery_is_present()
+	  function to determine whether the battery is currently present.
+	  This should be implemented in the board code and can use any
+	  reasonable method to detect the battery.
+
+config PLATFORM_EC_BATTERY_PRESENT_GPIO
+	bool "Check a GPIO"
+	help
+	  Use this method if a GPIO signals whether the battery is present. The
+	  GPIO should read low if the battery is present, high if absent.
+
+	  The GPIO is hard-coded to GPIO_BATT_PRES_ODL so you should define this
+	  in the device tree. The convention is to use the signal
+	  name from schematic as both the node name and label for the GPIO. For
+	  example:
+
+	    /* gpio.dts */
+	    ec_batt_pres_odl {
+	    	gpios = <&gpioe 5 GPIO_INPUT>;
+	    	enum-name = "EC_BATT_PRES_ODL";
+		alias = "GPIO_BATT_PRES_ODL";
+	    };
+
+endchoice # PLATFORM_EC_BATTERY_PRESENT_MODE
+
+config PLATFORM_EC_USE_BATTERY_DEVICE_CHEMISTRY
+	bool "Provide information about battery chemistry"
+	help
+	  Enable this to specify the chemistry of the battery device. It is
+	  only used for stress testing of reading the battery information over
+	  I2C.
+
+config PLATFORM_EC_BATTERY_DEVICE_CHEMISTRY
+	string "Battery-device chemistry"
+	depends on PLATFORM_EC_USE_BATTERY_DEVICE_CHEMISTRY
+	help
+	  Specify the battery chemistry for use with the I2C stress test.
+	  The value provided here must match what is read from the real
+	  battery. This is used in sb_i2c_test_read() to check that the battery
+	  is returning the right information. If it is not, there might be
+	  something wrong with the I2C implementation.
+
+config PLATFORM_EC_I2C_VIRTUAL_BATTERY
+	bool "I2C virtual battery"
+	help
+	  Enables driver for a virtual battery. It is used to minimalize I2C
+	  traffic which is generated by the I2C_PASSTHRU host command.
+	  The battery parameters, which are already cached in EC are used to
+	  return desired data to host instead of issuing I2C transaction every
+	  time.
+
+config PLATFORM_EC_I2C_VIRTUAL_BATTERY_ADDR
+	hex "I2C virtual battery address"
+	default 0x0B if PLATFORM_EC_BATTERY_SMART
+	range 0x00 0x7f
+	depends on PLATFORM_EC_I2C_VIRTUAL_BATTERY
+	help
+	  This config sets i2c address that will be intercepted by virtual
+	  battery feature. All communication to this port will be cached
+	  to decrease i2c communication traffic.
+	  This should be equal to the address of real battery.
+
+config PLATFORM_EC_BATTERY_CRITICAL_SHUTDOWN_CUT_OFF
+	bool "Enable battery cut off on critical power level"
+	help
+	  If this option is enabled, the battery will enter cut-off
+	  mode in case of critical power level.
+
+config PLATFORM_EC_BATTERY_CHECK_CHARGE_TEMP_LIMITS
+	bool "Monitor battery temperature while charging"
+	help
+	  Enable monitoring of battery temperature while charging and
+	  stop charging if is outside of the safe range.
+
+config PLATFORM_EC_BATTERY_CUT_OFF
+	bool "Host/Console command: battery cut-off"
+	help
+	  Enables support for disconnecting the battery using the "cutoff"
+	  console command and the EC_CMD_BATTERY_CUT_OFF host command.
+	  Once defined, a board specific board_cut_off_battery() function
+	  has to be provided.
+
+config PLATFORM_EC_BATTERY_FUEL_GAUGE
+	bool "Board supplies battery info"
+	help
+	  The fuel gauge information is used to cut off the battery for shipping
+	  mode and to check the charge/discharge FET status.  The battery
+	  information is used to set voltage, current and temperature operating
+	  limits for the battery.
+
+config PLATFORM_EC_BATTERY_HW_PRESENT_CUSTOM
+	bool "Hardware check of battery presence"
+	help
+	  Once defined, the charger will check a board specific function
+	  battery_hw_present() for battery hw presence as an additional
+	  condition to determine if power on is allowed for factory override,
+	  where allowing booting of a bare board with no battery and no power
+	  button press is required.
+
+config PLATFORM_EC_BATTERY_REVIVE_DISCONNECT
+	bool "Check battery disconnect state"
+	help
+	  Check for battery in disconnect state (similar to cut-off state).
+	  If this battery is found to be in disconnect state, take it out of
+	  this state by force-applying a charge current. Once defined,
+	  a battery_get_disconnect_state() function has to be provided.
+
+config PLATFORM_EC_BATTERY_MEASURE_IMBALANCE
+	bool "Measure the battery cells imbalance"
+	help
+	  Smart battery driver should measure the voltage cell imbalance in the
+	  battery pack.
+	  This requires a battery driver capable of the measurement.
+	  If enabled, the AP enabling may be prevented if battery is too
+	  imbalanced.
+
+config PLATFORM_EC_BATTERY_MAX_IMBALANCE_MV
+	int "Max battery imbalance in millivolts"
+	depends on PLATFORM_EC_BATTERY_MEASURE_IMBALANCE
+	default 200
+	help
+	  Imbalanced battery packs in this situation appear to have balanced
+	  charge very quickly after beginning the charging cycle, since dV/dQ
+	  rapidly decreases as the cell is charged out of deep discharge.
+	  Increasing the value of
+	  CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_IMBALANCED_POWER_ON will make a
+	  system tolerant of larger values of
+	  CONFIG_PLATFORM_EC_BATTERY_MAX_IMBALANCE_MV.
+
+config PLATFORM_EC_BATTERY_STBL_STAT
+	bool "Check whether the battery is initialized and stable"
+	help
+	  Enables support for checking the specific battery status to
+	  judge whether the battery is initialized and stable when the battery
+	  wakes up from ship mode. Use two MASKs to provide logical AND and
+	  logical OR options for different status.
+
+	  For example:
+	    STATUS_TERMINATE_CHARGE_ALARM(TCA):0x4000
+	    STATUS_TERMINATE_DISCHARGE_ALARM(TDA):0x0800
+
+	  Logical OR -- just check one of TCA/TDA mask:
+	    CONFIG_PLATFORM_EC_BATT_ALARM_MASK1=(0x4000 | 0x0800)
+	    CONFIG_PLATFORM_EC_BATT_ALARM_MASK2=0xFFFF
+
+	  Logical AND -- check both TCA/TDA mask:
+	    CONFIG_PLATFORM_EC_BATT_ALARM_MASK1=0x4000
+	    CONFIG_PLATFORM_EC_BATT_ALARM_MASK2=0x0800
+
+	  The default configuration is logical OR.
+
+if PLATFORM_EC_BATTERY_STBL_STAT
+
+config PLATFORM_EC_BATT_ALARM_MASK1
+	hex "The battery status mask"
+	default 0x4800
+	help
+	  Use two MASKs to provide logical AND and logical OR options for different
+	  status. Default mask 0x4800 means
+	  (STATUS_TERMINATE_CHARGE_ALARM | STATUS_TERMINATE_DISCHARGE_ALARM),
+	  any one of these two masks is set, the battery state can be considered
+	  stable.
+
+config PLATFORM_EC_BATT_ALARM_MASK2
+	hex "The battery status mask"
+	default 0xFFFF
+	help
+	  Use two MASKs to provide logical AND and logical OR options for different
+	  status. Default mask 0xFFFF means do not use this mask.
+
+endif # PLATFORM_EC_BATTERY_STBL_STAT
+
+config PLATFORM_EC_CHARGER_MIN_BAT_PCT_IMBALANCED_POWER_ON
+	int "Minimum battery percentage for power on with an imbalanced pack"
+	depends on PLATFORM_EC_BATTERY_MEASURE_IMBALANCE
+	default 5
+	range 0 100
+	help
+	  If battery pack is in imbalanced state and current state of charge is
+	  below this value, the AP won't be powered on.
+
+config PLATFORM_EC_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV
+	int "Voltage limit in mV when battery is full and AP is off"
+	depends on PLATFORM_EC_USB_PE_SM && PLATFORM_EC_CHARGE_MANAGER
+	default -1
+	help
+	  If set to a non-negative value, input voltage will be reduced to given
+	  value when chipset is in S5/G3 state and battery is fully charged.
+	  This condition is checked on chipset shutdown and startup, AC change
+	  and battery SOC change.
+
+choice PLATFORM_EC_BATTERY_API
+	prompt "Battery API version"
+	default PLATFORM_EC_BATTERY_V2
+	help
+	  Select the battery API version. V2 is required on dual-battery-systems
+	  and hostless bases with a battery. V1 should not be used except for
+	  testing on legacy boards.
+
+config PLATFORM_EC_BATTERY_V1
+	bool "Enable battery API v1"
+	depends on !PLATFORM_EC_BATTERY_V2
+	help
+	  This enables battery API version 1, with support for only a single
+	  battery. Battery information strings are trimmed to 8 characters.
+
+config PLATFORM_EC_BATTERY_V2
+	bool "Enable battery API v2"
+	help
+	  This enables battery API version 2. This version can support multiple
+	  batteries and full size string values in the battery information
+	  including manufacturer, model, chemistry.
+
+endchoice
+
+if PLATFORM_EC_BATTERY_V2
+
+config PLATFORM_EC_BATTERY_COUNT
+	int "Battery count"
+	default 1
+	help
+	  The number of batteries in the system. It matters only when
+	  PLATFORM_EC_BATTERY_V2 is enabled. Note this is different from
+	  BATTERY_TYPE_COUNT.
+
+config PLATFORM_EC_HOSTCMD_BATTERY_V2
+	bool "Enable host command battery API v2"
+	default y
+	help
+	  Include host commands to fetch battery information from
+	  ec_response_battery_static/dynamic_info structures, only make sense
+	  when PLATFORM_EC_BATTERY_V2 is enabled.
+
+endif # PLATFORM_EC_BATTERY_V2
+
+config PLATFORM_EC_BATTERY_TYPE_NO_AUTO_DETECT
+	bool "Disable battery auto detection"
+	help
+	  Enable this option when the battery type cannot be distinguished
+	  based on only the manufacturer and device name. Your board code
+	  must call battery_set_fixed_battery_type() to set the fixed battery
+	  type, during board initialization.
+
+if PLATFORM_EC_I2C_VIRTUAL_BATTERY
+
+config PLATFORM_EC_SMART_BATTERY_OPTIONAL_MFG_FUNC
+	bool "Support smart battery optional MFG function"
+	help
+	  Enable this option when need support smart battery optional commands.
+	  Only make sense when PLATFORM_EC_I2C_VIRTUAL_BATTERY.
+
+endif # PLATFORM_EC_I2C_VIRTUAL_BATTERY
+
+config PLATFORM_EC_BATT_HOST_FULL_FACTOR
+	int "This value is used by the host to calculate the ETA for full charge"
+	default 97
+	help
+	  Today, EC's PLATFORM_EC_BATT_HOST_FULL_FACTOR is the source of truth.
+	  Powerd gets the value from the EC over EC_CMD_DISPLAY_SOC.
+
+endif # PLATFORM_EC_BATTERY
diff --git a/zephyr/Kconfig.board_version b/zephyr/Kconfig.board_version
new file mode 100644
index 0000000000..6410e8b6c0
--- /dev/null
+++ b/zephyr/Kconfig.board_version
@@ -0,0 +1,34 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+choice PLATFORM_EC_BOARD_VERSION_SOURCE
+	prompt "Select the source of the board version number"
+	optional
+	help
+	  This allow selection of the source of the board version number
+	  information. Several options are available, but BOARD_VERSION_CBI is
+	  preferred for new boards, so long as the hardware supports it (i.e.
+	  has an EEPROM).
+
+config PLATFORM_EC_BOARD_VERSION_CBI
+	bool "Chromium OS Board Info (CBI)"
+	depends on PLATFORM_EC_CBI_EEPROM || PLATFORM_EC_CBI_FLASH
+	help
+	  Choose this if the board version comes from Chromium Board Info
+	  within the EEPROM or EC Flash. This is the recommended approach
+	  and is used on newer boards. The version information is written
+	  into the EEPROM or EC flash as part of the factory process.
+
+config PLATFORM_EC_BOARD_VERSION_GPIO
+	bool "Strapping GPIOs"
+	help
+	  Choose this if the board version is encoded with three GPIO signals
+	  (GPIO_BOARD_VERSION1, GPIO_BOARD_VERSION2 and GPIO_BOARD_VERSION3)
+	  forming the 3-digit binary number. GPIO_BOARD_VERSION1 is the LSB.
+	  This provides 8 possible combinations.
+
+	  The GPIOs should have external pull-up/pull-down resistors installed
+	  at the factory to select the correct value.
+
+endchoice
diff --git a/zephyr/Kconfig.body_detection b/zephyr/Kconfig.body_detection
new file mode 100644
index 0000000000..df163799c6
--- /dev/null
+++ b/zephyr/Kconfig.body_detection
@@ -0,0 +1,104 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+menuconfig PLATFORM_EC_BODY_DETECTION
+	bool "Sensor body detection"
+	help
+	  Enable the body detection function.
+
+	  The Power Reduction Algorithm is based on the Motion Detector
+	  output of In Motion (on body) state or Stationary (off body) state.
+	  The input of the Motion Detector is the X and Y axis signal
+	  from an accelerometer.
+
+if PLATFORM_EC_BODY_DETECTION
+
+config PLATFORM_EC_BODY_DETECTION_MAX_WINDOW_SIZE
+	int "Maximal sensor data rate"
+	default 250
+	help
+	  Sets the maximum sensor data rate, in Hz. Note that larger data rate
+	  values consume more memory and computing resource.
+
+config PLATFORM_EC_BODY_DETECTION_VAR_THRESHOLD
+	int "The threshold of acceleration variance for confidence calculation"
+	default 550
+	help
+	  The unit is (mm/s^2)^2
+
+	  The motion confidence is calculated if the variance is within
+	  variance_threshold +/- confidence_delta. Otherwise, if variance is
+	  too high/low, confidence will be 100%/0%
+
+config PLATFORM_EC_BODY_DETECTION_CONFIDENCE_DELTA
+	int "The delta of acceleration variance for confidence calculation"
+	default 525
+	help
+	  The unit is (mm/s^2)^2
+
+	  The motion confidence is calculated if the variance is within
+	  variance_threshold +/- confidence_delta. Otherwise, if variance is
+	  too high/low, confidence will be 100%/0%
+
+config PLATFORM_EC_BODY_DETECTION_VAR_NOISE_FACTOR
+	int "How much noise affects the threshold of variance"
+	default 120
+	help
+	  The unit is percentage
+
+	  This is used for mitigate the effect of the noise from the sensor.
+	  If set to 100%, the average noise is canceled out. This is set to
+	  120% by default because the noise might get larger than average
+	  sometimes.
+
+config PLATFORM_EC_BODY_DETECTION_ON_BODY_CON
+	int "The confidence limit of on_body"
+	default 50
+	help
+	  The unit is percentage
+
+	  Higher the value, more diffcult to enter the on-body from off-body
+
+config PLATFORM_EC_BODY_DETECTION_OFF_BODY_CON
+	int "The confidence limit of off body"
+	default 10
+	help
+	  The unit is percentage
+
+	  Lower the value, more diffcult to enter the off-body from on-body.
+	  Should be set less than the PLATFORM_EC_BODY_DETECTION_ON_BODY_CON
+
+config PLATFORM_EC_BODY_DETECTION_STATIONARY_DURATION
+	int "The threshold duration to change to off_body"
+	default 15
+	help
+	  The unit is seconds
+
+	  How long should we stay in on-body state before entering to off-body
+	  state when the motion confidence is less than
+	  PLATFORM_EC_BODY_DETECTION_OFF_BODY_CON
+
+config PLATFORM_EC_BODY_DETECTION_NOTIFY_MODE_CHANGE
+	bool "Notify host with a specific host event when body status is changed"
+	default n
+	help
+	  Notify the host via SCI events EC_HOST_EVENT_BODY_DETECT_CHANGE when body
+	  status is changed, in addition to adding an event in the motion sensor
+	  FIFO queue.
+
+config PLATFORM_EC_BODY_DETECTION_NOTIFY_MKBP
+	bool "Notify host with MKBP event when the body on/off"
+	default n
+	help
+	  Notify the host via EC_MKBP_FRONT_PROXIMITY
+	  when the body status changed.
+
+config PLATFORM_EC_BODY_DETECTION_ALWAYS_ENABLE_IN_S0
+	bool "Always enable body detection function in S0"
+	default n
+	help
+	  Always enable the body detection function in S0
+	  w/o the host command
+
+endif # PLATFORM_EC_BODY_DETECTION
diff --git a/zephyr/Kconfig.cbi b/zephyr/Kconfig.cbi
new file mode 100644
index 0000000000..6b5a44a5ed
--- /dev/null
+++ b/zephyr/Kconfig.cbi
@@ -0,0 +1,67 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config PLATFORM_EC_BYPASS_CBI_EEPROM_WP_CHECK
+	bool "Bypass CBI EEPROM Write Protect"
+	depends on PLATFORM_EC_CBI_EEPROM
+	help
+	  Bypass the CBI EEPROM write protect checks. This should ONLY be
+	  defined during bringup, and should never be defined on a shipping or
+	  release platform.
+
+	  When defined, ectool can be used to reprogram all CBI fields,
+	  regardless of the state of the hardware write protect.
+
+config PLATFORM_EC_EEPROM_CBI_WP
+	bool "EC can independently set the CBI EEPROM WP signal"
+	depends on PLATFORM_EC_CBI_EEPROM
+	help
+	   Define this if the EC can independently set the CBI EEPROM WP
+	   signal. The accompanying hardware must ensure that the CBI WP gets
+	   latched and is only reset when EC_RST_ODL is asserted.
+
+config PLATFORM_EC_CBI
+	bool "CBI support"
+	default y
+	help
+	  CBI is a means for accessing board information, typically set
+	  during the factory process. This allows selection of the physical
+	  storage of CBI source.
+
+	  See here for detailed information on CBI:
+
+	  https://chromium.googlesource.com/chromiumos/docs/+/HEAD/design_docs/cros_board_info.md
+
+if PLATFORM_EC_CBI
+
+choice PLATFORM_EC_CBI_STORAGE_TYPE
+	prompt "CBI storage type"
+	default PLATFORM_EC_CBI_EEPROM if $(dt_nodelabel_enabled,cbi_eeprom)
+	default PLATFORM_EC_CBI_FLASH if $(dt_nodelabel_enabled,cbi_flash)
+	help
+	  Select the backing storage type for CBI data.
+
+config PLATFORM_EC_CBI_EEPROM
+	bool "CBI EEPROM support"
+	depends on EEPROM
+	help
+	  Enables full Chromium OS Board Info (CBI) support, with CBI data
+	  stored in an on-board EEPROM.
+
+config PLATFORM_EC_CBI_GPIO
+	bool "CBI GPIO support"
+	help
+	  Enables Chromium OS Board Info (CBI) from strapping pins. EC reads
+	  the BOARD ID and SKU ID from GPIOs and then substantiate in-memory
+	  CBI for AP to query.
+
+config PLATFORM_EC_CBI_FLASH
+	bool "CBI flash support"
+	help
+	  Enables full Chromium OS Board Info (CBI) support, with CBI data
+	  stored in an on-board flash.
+
+endchoice
+
+endif # PLATFORM_EC_CBI
diff --git a/zephyr/Kconfig.cec b/zephyr/Kconfig.cec
new file mode 100644
index 0000000000..dc6137fcb8
--- /dev/null
+++ b/zephyr/Kconfig.cec
@@ -0,0 +1,25 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config PLATFORM_EC_CEC
+	bool "EC CEC support"
+	help
+	  Enable support for HDMI CEC (Consumer Electronics Control).
+
+if PLATFORM_EC_CEC
+
+config PLATFORM_EC_CEC_DEBUG
+	bool "CEC debug logs"
+	help
+	  Enable CEC debug logs.
+
+config PLATFORM_EC_CEC_BITBANG
+	bool "CEC bitbang driver"
+	help
+	  Enable the CEC bitbang driver. This driver uses GPIOs and a hardware
+	  timer to send and receive CEC messages. It can be used on ECs without
+	  a CEC peripheral, or in addition to a CEC peripheral to enable more
+	  CEC ports.
+
+endif # PLATFORM_EC_CEC
diff --git a/zephyr/Kconfig.charger b/zephyr/Kconfig.charger
new file mode 100644
index 0000000000..9f5abea099
--- /dev/null
+++ b/zephyr/Kconfig.charger
@@ -0,0 +1,855 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+menuconfig PLATFORM_EC_CHARGER
+	bool "Charging support"
+	default y
+	select HAS_TASK_CHARGER
+	select PLATFORM_EC_EXTPOWER
+	depends on PLATFORM_EC_BATTERY
+	help
+	  Enable the EC charging task.
+
+if PLATFORM_EC_CHARGER
+
+choice PLATFORM_EC_CHARGER_TYPE
+	prompt "Select how many chargers are on the board"
+	default PLATFORM_EC_CHARGER_SINGLE_CHIP
+	help
+	  Select a single charger or multiple chargers.
+	  Multiple chargers imply one charger per type-C port (OCPC).
+
+config PLATFORM_EC_CHARGER_SINGLE_CHIP
+	bool "Board has a single charger"
+	help
+	  Enables a single charger for the board, which is assigned
+	  index 0.
+
+config PLATFORM_EC_OCPC
+	bool "Board has multiple chargers"
+	help
+	  Enables multiple chargers, one for each type-C port (OCPC).
+	  The assumption is that that primary charger is index 0 and is the
+	  charger IC connected to the battery FET.
+	  Additionally, `chgnum` is assumed to be the same as the
+	  charge port index.
+
+endchoice # PLATFORM_EC_CHARGER_TYPE
+
+config PLATFORM_EC_CHARGER_INIT_CUSTOM
+	bool "Allow the customized initial configuration"
+	default name
+	help
+	  When enabled, the board layer must create the charger_chips_init()
+	  function for customizing the initial configuration.
+
+config PLATFORM_EC_CHARGER_BYPASS_REVERSE_TURBO
+	bool "Enable charger reverse turbo when running in bypass"
+	default n
+	help
+	  When enabled, the charger will allow the battery to suppliment
+	  the ac power by boosting the battery up to the system bus voltage.
+
+config PLATFORM_EC_CHARGER_RUNTIME_CONFIG
+	bool "Allow charger configuration at runtime"
+	default n
+	help
+	  When enabled, the internal array of charger chip configuration will
+	  not be made constant. This allows board code to do runtime
+	  reconfiguration, such as to configure ports that may only be present
+	  in some hardware configurations or when ports in some configurations
+	  are setup differently.
+
+config PLATFORM_EC_CHARGE_MANAGER
+	bool "Charge manager"
+	default y
+	help
+	  The EC charge manager manages charging the battery from all supported
+	  power sources.  This includes dedicated charge ports (such as a
+	  barrel jack connector), BC1.2 (Battery Charging 1.2) sources, and
+	  USB-C sources. When multiple charge sources are connected to a
+	  Chromebook simultaneously, the charge manager is responsible for
+	  picking the best source. This also enables compilation of the
+	  charge_state_v2 code.
+
+	  Note that the charge manager assumes that at least one USB-C power
+	  source is available on the hardware, so cannot be built without
+	  PLATFORM_EC_USBC.
+
+config PLATFORM_EC_CHARGE_STATE_DEBUG
+	bool "Debug information about the charge state"
+	depends on PLATFORM_EC_CHARGE_MANAGER
+	help
+	  Enables debug information regarding the current charge state. Enabling
+	  this config will allow the EC_CMD_CHARGE_STATE host command to use the
+	  CHARGE_STATE_CMD_GET_PARAM command to query the current charge state.
+
+config PLATFORM_EC_CHARGE_DEBUG
+	bool "Add a debug sub-command to the 'chgstate' command"
+	depends on PLATFORM_EC_CHARGE_MANAGER
+	default y
+	help
+	  Enables the 'chgstate debug' command which allows extra debugging to
+	  be shown when charging, or when a separate base (with battery) is
+	  used. This adds a little to the code size, but can normally be safely
+	  enabled.
+
+config PLATFORM_EC_CMD_PWR_AVG
+	bool "Enable the console command to print power average"
+	depends on PLATFORM_EC_CHARGE_MANAGER
+	help
+	  Enables the console command which prints out the current (past 1
+	  minute) power average.
+
+config PLATFORM_EC_CHARGESPLASH
+	bool "Charging splashscreen support"
+	help
+	  Enable visual charging indicator to display on-screen when
+	  AC is initially connected.
+
+config PLATFORM_EC_CHARGER_ISL9237
+	bool "Use the ISL9237 charger"
+	depends on PLATFORM_EC_I2C
+	select PLATFORM_EC_CHARGER_NARROW_VDC
+	select PLATFORM_EC_CHARGER_OTG_SUPPORTED
+	help
+	  Enables a driver for the ISL9237 VCD Battery Charger. This is a
+	  digitally-configurable, buck-boost battery charger that supporting
+	  Narrow Voltage Direct Charging (NVDC). It supports an input voltage
+	  range of 3.2-23.4V and output of 2.4-13.8V. It provides an I2C
+	  interface for configuration an provides a USB On-The-Go (OTG)
+	  function for 2- and 3-cell battery applications.
+
+config PLATFORM_EC_CHARGER_ISL9238
+	bool "Use the ISL9238 charger"
+	depends on PLATFORM_EC_I2C
+	select PLATFORM_EC_CHARGER_NARROW_VDC
+	select PLATFORM_EC_CHARGER_OTG_SUPPORTED
+	help
+	  Enables a driver for the ISL9238 VCD Battery Charger. This is a
+	  digitally-configurable, buck-boost battery charger that supporting
+	  Narrow Voltage Direct Charging (NVDC). It supports an input voltage
+	  range of 3.2-23.4V and output of 2.4-18.3V. It provides an I2C
+	  interface for configuration.
+
+config PLATFORM_EC_CHARGER_ISL9238C
+	bool "Use the ISL9238 Rev C charger"
+	depends on PLATFORM_EC_I2C
+	select PLATFORM_EC_CHARGER_NARROW_VDC
+	select PLATFORM_EC_CHARGER_OTG_SUPPORTED
+	help
+	  Enable a driver for the ISL9238 Rev C VCD Battery Charger. This
+	  is a digitally-configurable, buck-boost battery charger that
+	  supporting Narrow Voltage Direct Charging (NVDC). It supports an input
+	  voltage range of 3.2-23.4V and output of 2.4-18.3V. It provides an I2C
+	  interface for configuration.
+
+	  This option is separate from PLATFORM_EC_CHARGER_ISL9238 since there
+	  is no way in software to distinguish between rev. A/B and rev. C.
+
+config PLATFORM_EC_CHARGER_ISL9241
+	bool "Use the ISL9241 charger"
+	depends on PLATFORM_EC_I2C
+	# Hardware based charge ramp is broken in the ISL9241 (b/169350714)
+	select PLATFORM_EC_CHARGER_CHGRAMP_BROKEN
+	help
+	  Enables a driver for the ISL9241 VCD Battery Charger. This is a
+	  digitally-configurable, buck-boost battery charger that can support
+	  both Narrow Voltage Direct Charging (NVDC) and Hybrid Power Buck Boost
+	  (HPBB/Bypass) charging and switch between the modes under firmware
+	  control. It supports an input voltage range of 3.9-23.4V and output
+	  of 3.9-18.3V. It provides an I2C interface for configuration.
+
+config PLATFORM_EC_CHARGER_RAA489110
+	bool "Use the RAA489110 charger"
+	depends on PLATFORM_EC_I2C
+	# Hardware based charge ramp is broken in the ISL9241 (b/169350714)
+	# Probably also broken for RAA489110.
+	select PLATFORM_EC_CHARGER_CHGRAMP_BROKEN
+	help
+	  Enables a driver for the RAA489110 VCD Battery Charger. This is a
+	  EPR capable version of ISL9241.
+
+if PLATFORM_EC_CHARGER_ISL9241
+
+config PLATFORM_EC_ISL9241_SWITCHING_FREQ
+	int "ISL9241 switching frequency"
+	default -1
+	help
+	  Switching frequency for all ISL9241 chips. ISL9241 configures the
+	  switching frequency and overrides the default one set by PROG pin.
+	  Setting -1 means the no-override option, the default value is not
+	  changed. The valid frequency settings are listed in
+	  driver/charger/isl9241.h
+
+endif
+
+config PLATFORM_EC_CHARGER_BQ25710
+	bool "Use the BQ25710 charger"
+	depends on PLATFORM_EC_I2C
+	select PLATFORM_EC_CHARGER_NARROW_VDC
+	help
+	  Enables the driver for the TI BQ25710 battery charger
+	  controller. This is a synchronous narrow voltage DC buck-boost
+	  battery charger for one to four battery cell applications. A
+	  wide range of input power sources are supported such as high
+	  voltage USB-C power delivery.
+
+config PLATFORM_EC_CHARGER_BQ25720
+	bool "Use the BQ25720 charger"
+	depends on PLATFORM_EC_I2C
+	select PLATFORM_EC_CHARGER_NARROW_VDC
+	help
+	  Enables the driver for the TI BQ25720 battery charger
+	  controller. This is a synchronous narrow voltage DC buck-boost
+	  battery charger for one to four battery cell applications. A
+	  wide range of input power sources are supported such as high
+	  voltage USB-C power delivery.
+
+config PLATFORM_EC_CHARGER_RAA489000
+	bool "Use the RAA489000 charger"
+	depends on PLATFORM_EC_I2C
+	depends on PLATFORM_EC_CHARGER_SENSE_RESISTOR > 0
+	depends on PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC > 0
+	select PLATFORM_EC_CHARGER_NARROW_VDC
+	select PLATFORM_EC_CHARGER_TRICKLE
+	help
+	  Enables the driver for the Renesas RAA489000 battery charger
+	  with integrated USB-C TCPC.
+
+config PLATFORM_EC_RAA489000_AC_PRESENT_CONTROL
+	bool "Invert the AC_PRESENT signal when in OTG mode"
+	depends on PLATFORM_EC_CHARGER_RAA489000 && !PLATFORM_EC_EXTPOWER_GPIO
+	help
+	  Enables the RAA489000 chip to invert the AC_PRESENT signal
+	  when the charger is in OTG (sourcing) mode.
+	  This is required when the internal comparator is used to
+	  generate the AC_PRESENT signal from the ACOK signal.
+	  In OTG mode the ACOK signal is high, but the AC_PRESENT
+	  should be set low, so the comparator output must be inverted.
+	  The GPIO_AC_PRESENT gpio signal must not be configured.
+
+config PLATFORM_EC_CHARGER_RT9490
+	bool "Use the RT9490 charger"
+	default y
+	depends on DT_HAS_RICHTEK_RT9490_ENABLED || DT_HAS_ZEPHYR_RT9490_EMUL_ENABLED
+	depends on PLATFORM_EC_I2C
+	select PLATFORM_EC_CHARGER_OTG_SUPPORTED
+	help
+	  Enables the driver for the Richtek RT9490 battery charger
+	  controller. This is a highly-integrated 5A Buck-Boost switch mode
+	  battery charge management and system power path management device for
+	  1-4 cell Li-Ion and Li-polymer battery.
+
+config PLATFORM_EC_CHARGER_SM5803
+	bool "Use the SM5803 charger"
+	depends on PLATFORM_EC_I2C
+	select PLATFORM_EC_CHARGER_NARROW_VDC
+	help
+	  Enables the driver for the SM5803.
+	  The SM5803 is the Silicon Mitus SM5803 Buck-Boost Charger.
+
+	  This charger is known to be very inefficient when operating in buck-boost
+	  mode (when input voltage is close to output voltage), such that permanent
+	  damage may be done to the charger. Users should exercise caution around
+	  choice of supported configurations: see b:260271871, b:258754576, and
+	  b:230712704 for more information.
+
+
+if PLATFORM_EC_OCPC
+
+config PLATFORM_EC_OCPC_DEF_RBATT_MOHMS
+	int "Resistance between the secondary charger IC and the battery"
+	help
+	  Boards using OCPC must define this value in order to seed the
+	  starting board battery and system resistance between the secondary
+	  charger IC and the battery.
+	  This should be at a minimum the Rds(on) resistance of the BFET plus
+	  the series sense resistor.
+
+config PLATFORM_EC_OCPC_DEF_DRIVELIMIT_MILLIVOLTS
+	int "Drive Limit for the OCPC PID control loop"
+	default 10
+	help
+	  Sets how agressively the OCPC PID control loop can adjust VSYS to drive
+	  the battery with the correct current.
+
+endif  # PLATFORM_EC_OCPC
+
+config PLATFORM_EC_CHARGER_DISCHARGE_ON_AC
+	bool "Board supports discharge mode"
+	help
+	  Enable this if the board supports discharging the battery even when
+	  AC power is present. This is used for testing. The function is
+	  provided either by the charger or by custom code in the board.
+
+if PLATFORM_EC_CHARGER_DISCHARGE_ON_AC
+
+choice PLATFORM_EC_CHARGER_DISCHARGE_MODE
+	prompt "Select the method of controlling discharge"
+	help
+	  Select which method is provided to enable and disable the discharge
+	  mode.
+
+config PLATFORM_EC_CHARGER_DISCHARGE_ON_AC_CHARGER
+	bool "Charger controls discharge mode"
+	help
+	  Enable this if the charger controls selection of discharge mode.
+	  In this case the charger must provide a function:
+
+	     int charger_discharge_on_ac(int enabled)
+
+	  It should enable this feature if enabled is true, else disable it.
+	  The function should return EC_SUCCESS
+
+config PLATFORM_EC_CHARGER_DISCHARGE_ON_AC_CUSTOM
+	bool "Custom control of discharge mode"
+	help
+	  Enable this if the discharge mode is controlled by a custom function.
+	  This function is typically provided by the board implementation:
+
+	     int board_discharge_on_ac(int enabled)
+
+	  It should enable this feature if enabled is true, else disable it.
+	  The function should return EC_SUCCESS
+
+endchoice # PLATFORM_EC_CHARGER_DISCHARGE_MODE
+
+endif # PLATFORM_EC_CHARGER_DISCHARGE_ON_AC
+
+config PLATFORM_EC_CHARGER_BQ25710_PSYS_SENSING
+	bool "Charger monitors PSYS"
+	default n
+	depends on PLATFORM_EC_CHARGER_BQ25710 || PLATFORM_EC_CHARGER_BQ25720
+	help
+	  This enables the PSYS sensing circuit on the BQ25710 and
+	  BQ25720 chargers. This is used for system power monitoring on
+	  board designs that support this capability. This circuit is
+	  disabled by default (reset) and needs to be explicitly enabled
+	  for meaningful results.
+
+config PLATFORM_EC_CHARGER_BQ25710_CMP_REF_1P2
+	bool "Use 1.2 V for internal comparator reference voltage"
+	default n
+	depends on PLATFORM_EC_CHARGER_BQ25710 || PLATFORM_EC_CHARGER_BQ25720
+	help
+	  This changes the charger's internal comparator reference
+	  voltage to 1.2 V. The power-on default is 2.3 V. This must be
+	  enabled if the board was designed for 1.2 V instead of 2.3 V.
+
+config PLATFORM_EC_CHARGER_BQ25710_CMP_POL_EXTERNAL
+	bool "independent comparator output polarity"
+	default n
+	depends on PLATFORM_EC_CHARGER_BQ25710 || PLATFORM_EC_CHARGER_BQ25720
+	help
+	  Set the CMP_POL register. When CMPIN is above internal threshold,
+	  CMPOUT is LOW setting value is 0. When CMPIN is below internal threshold,
+	  CMPOUT is LOW setting value is 1.
+
+config PLATFORM_EC_CHARGER_BQ25710_PKPWR_TOVLD_DEG_CUSTOM
+	bool "PKPWR_TOVLD_DEG override"
+	default n
+	depends on PLATFORM_EC_CHARGER_BQ25710 || PLATFORM_EC_CHARGER_BQ25720
+	help
+	  Enable customizing the charger's PKPWR_TOVLD_DEG period.
+
+config PLATFORM_EC_CHARGER_BQ25710_PKPWR_TOVLD_DEG
+	int "PKPWR_TOVLD_DEG period"
+	range 0 3
+	default 0
+	depends on PLATFORM_EC_CHARGER_BQ25710 || PLATFORM_EC_CHARGER_BQ25720
+	help
+	  Sets the input overload time when in peak power mode
+	  (PKPWR_TOVLD_DEG). This limits how long the charger can draw
+	  ILIM2 from the adapter. This is a 2 bit field. On the bq25710
+	  1 ms to 20 ms can be encoded. On the bq25720 1 ms to 10 ms can
+	  be encoded.
+
+config PLATFORM_EC_CHARGER_BQ25710_EN_ACOC
+	bool "Enable AC over-current protection"
+	default n
+	depends on PLATFORM_EC_CHARGER_BQ25710 || PLATFORM_EC_CHARGER_BQ25720
+	help
+	  This enables the charger's AC over-current protection. The
+	  converter turns off when the OC threshold is reached. The
+	  threshold is selected using the ACOC_VTH bit.
+
+config PLATFORM_EC_CHARGER_BQ25710_ACOC_VTH_1P33
+	bool "Set ACOC threshold to 133% of ILIM2"
+	default n
+	depends on PLATFORM_EC_CHARGER_BQ25710 || PLATFORM_EC_CHARGER_BQ25720
+	help
+          This selects which ACOC protection threshold is used with
+	  EN_ACOC. Enabling this option selects 133% of
+	  ILIM2. Otherwise, the default is 200% of ILIM2.
+
+config PLATFORM_EC_CHARGER_BQ25710_BATOC_VTH_MINIMUM
+	bool "Select the minimum BATOC threshold"
+	default n
+	depends on PLATFORM_EC_CHARGER_BQ25710 || PLATFORM_EC_CHARGER_BQ25720
+	help
+          This selects the minimum BATOC protection threshold to be used
+          with EN_BATOC. The minimum threshold is 150% of PROCHOT IDCHG
+          on the bq25710 and 133% of PROCHOT IDCHG_TH2 on the
+          bq25720. The default threshold is 200% on both chips.
+
+config PLATFORM_EC_CHARGER_BQ25710_PP_COMP
+	bool "Enable independent comparator PROCHOT"
+	default n
+	depends on PLATFORM_EC_CHARGER_BQ25710 || PLATFORM_EC_CHARGER_BQ25720
+	help
+	  Sets the PP_COMP in Prochot Option 1 register. When in low power
+	  mode(Battery only), this bit will lose controllability to independent
+	  comparator PROCHOT profiles. Need to use EN_PROCHOT_LPWR to enable
+	  independent comparator and its PROCHOT profile.
+
+config PLATFORM_EC_CHARGER_BQ25710_PP_INOM
+	bool "Enable PROCHOT on adapter current exceeding INOM"
+	default n
+	depends on PLATFORM_EC_CHARGER_BQ25710 || PLATFORM_EC_CHARGER_BQ25720
+	help
+	  Sets the PP_INOM bit in Prochot Option 1 register. This causes
+	  PROCHOT to be pulsed when the nominal adapter current
+	  threshold is reached. INOM is 110% of IDPM/IIN_DPM (input
+	  current setting).
+
+config PLATFORM_EC_CHARGER_BQ25710_PP_BATPRES
+	bool "Enable PROCHOT on battery removal"
+	default n
+	depends on PLATFORM_EC_CHARGER_BQ25710 || PLATFORM_EC_CHARGER_BQ25720
+	help
+	  Sets the PP_BATPRES bit in Prochot Option 1 register. This
+	  causes PROCHOT to be pulsed when the battery is removed.
+
+config PLATFORM_EC_CHARGER_BQ25710_PP_ACOK
+	bool "Enable PROCHOT on AC removal"
+	default n
+	depends on PLATFORM_EC_CHARGER_BQ25710 || PLATFORM_EC_CHARGER_BQ25720
+	help
+	  Sets the PP_ACOK in Prochot Option 1 register. This causes
+	  PROCHOT to be pulsed when the AC adapter is removed.
+
+config PLATFORM_EC_CHARGER_BQ25720_PP_IDCHG2
+	bool "Enable PROCHOT on battery current exceeding IDCHG_TH2"
+	default n
+	depends on PLATFORM_EC_CHARGER_BQ25720
+	help
+	  Sets the PP_IDCHG2 bit in Charge Option 4 register. This
+	  causes PROCHOT to be pulsed when the battery discharge current
+	  exceeds IDCHG_TH2.
+
+config PLATFORM_EC_CHARGER_BQ25710_SENSE_RESISTOR
+	int "Value of the charge sense-resistor, in mOhms"
+	default 10
+	depends on PLATFORM_EC_CHARGER_BQ25710 || PLATFORM_EC_CHARGER_BQ25720
+	help
+	  The charge sense-resistor is used to detect the charge current to the
+	  battery. Its value must be known for the calculation to be correct.
+	  The value is typically around 10 mOhms.
+
+config PLATFORM_EC_CHARGER_BQ25710_SENSE_RESISTOR_AC
+	int "Value of the input sense-resistor, in mOhms"
+	default 10
+	depends on PLATFORM_EC_CHARGER_BQ25710 || PLATFORM_EC_CHARGER_BQ25720
+	help
+	  The input sense-resistor is used to detect the input current from the
+	  external AC power supply. Its value must be known for the calculation
+	  to be correct. The value is typically around 10 mOhms.
+
+config PLATFORM_EC_CHARGER_BQ257X0_ILIM2_VTH_CUSTOM
+	bool "ILIM2_VTH override"
+	depends on PLATFORM_EC_CHARGER_BQ25710 || PLATFORM_EC_CHARGER_BQ25720
+	help
+	  Enable customizing the charhger's ILIM2_VTH threshold
+
+config PLATFORM_EC_CHARGER_BQ257X0_ILIM2_VTH
+	int "ILIM2 threshold"
+	range 1 30
+	default 9
+	depends on PLATFORM_EC_CHARGER_BQ257X0_ILIM2_VTH_CUSTOM
+	help
+	  Set percentage of IDPM as threshold. ICRIT threshold is set to be 110%
+	  of ILIM2. Input overcurrent protection (ACOC) threshold is also 1.33x
+	  or 2x of ILIM2 (1.33x or 2x based on ACOC limit field).
+	  1  - 25: 110% - 230%, step is 5%.
+	  26 - 30: 250% - 450%, step is 50%.
+	  31: Out of range (ignored).
+
+config PLATFORM_EC_CHARGER_BQ25720_VSYS_TH2_CUSTOM
+	bool "VSYS_TH2 override"
+	depends on PLATFORM_EC_CHARGER_BQ25720
+	help
+	  Enable customizing the charger's VSYS_TH2 threshold.
+
+config PLATFORM_EC_CHARGER_BQ25720_VSYS_TH2_DV
+	int "VSYS threshold 2 in deci-volts"
+	range 32 95
+	default 32
+	depends on PLATFORM_EC_CHARGER_BQ25720_VSYS_TH2_CUSTOM
+	help
+	  Sets the VSYS threshold 2 in deci volts. This is the first
+	  threshold that will be encountered when VSYS droops, typically
+	  due to high power demand from the main processor. The charger
+	  chip reacts by asserting PROCHOT which the main processor uses
+	  as an indication to throttle back and reduce power demand. The
+	  charger chip uses default thresholds which may be low enough
+	  to cause system instability. The default for 1S batteries is
+	  3.2v and 5.9v for 2S or higher batteries.  The valid range is
+	  3.2v - 3.9v for 1S and 3.2 - 9.5v for 2S or higher batteries.
+
+config PLATFORM_EC_CHARGER_BQ25720_VSYS_UVP_CUSTOM
+       	bool "VSYS_UVP override"
+	depends on PLATFORM_EC_CHARGER_BQ25720
+	help
+	  Enable customizing the charger's VSYS_UVP threshold.
+
+config PLATFORM_EC_CHARGER_BQ25720_VSYS_UVP
+       	int "VSYS_UVP threshold"
+	range 0 7
+	default 0
+	depends on PLATFORM_EC_CHARGER_BQ25720_VSYS_UVP_CUSTOM
+	help
+	  Sets the VSYS under voltage (VSYS_UVP) lockout threshold. This
+	  is a 3 bit field with default value 0. The actual voltage
+	  encoded is (0.8 * <value> + 2.4), allowing a threshold in the
+	  range of 2.4 V to 8.0 V to be specified.
+
+config PLATFORM_EC_CHARGER_BQ25720_IDCHG_DEG2_CUSTOM
+	bool "IDCHG_TH2 deglitch time override"
+	depends on PLATFORM_EC_CHARGER_BQ25720
+	help
+	  Enable customizing the charger's 2nd battery discharge current
+	  limit (IDCHG_TH2) deglitch time (IDCHG_DEG2).
+
+config PLATFORM_EC_CHARGER_BQ25720_IDCHG_DEG2
+	int "IDCHG_TH2 deglitch time"
+	range 0 3
+	default 1
+	depends on PLATFORM_EC_CHARGER_BQ25720_IDCHG_DEG2_CUSTOM
+	help
+	  Sets the 2nd battery discharge current limit (IDCHG_TH2)
+	  deglitch time (IDCHG_DEG2). This is a 2 bit field with default
+	  value 1 (1.6 ms). The encoded value ranges from 100 us to 12
+	  ms.
+
+config PLATFORM_EC_CHARGER_BQ25720_IDCHG_TH2_CUSTOM
+	bool "IDCHG_TH2 override"
+	depends on PLATFORM_EC_CHARGER_BQ25720
+	help
+	  Enable customizing the charger's 2nd battery discharge current
+	  limit (IDCHG_TH2).
+
+config PLATFORM_EC_CHARGER_BQ25720_IDCHG_TH2
+	int "IDCHG threshold 2"
+	range 0 7
+	default 1
+	depends on PLATFORM_EC_CHARGER_BQ25720_IDCHG_TH2_CUSTOM
+	help
+	  Sets the charger's 2nd battery discharge current limit
+	  (IDCHG_TH2) as a percentage of IDCHG_TH1. This is a 3 bit
+	  field with default value 1 (150%). The encoded value ranges
+	  from 125% to 400%.
+
+config PLATFORM_EC_CHARGER_BQ25710_VSYS_MIN_VOLTAGE_CUSTOM
+	bool "Enable minimum system voltage override"
+	depends on PLATFORM_EC_CHARGER_BQ25710 || PLATFORM_EC_CHARGER_BQ25720
+	help
+	  Enable customizing the charger's 2nd battery discharge current
+	  limit (IDCHG_TH2).
+
+config PLATFORM_EC_CHARGER_BQ25710_VSYS_MIN_VOLTAGE_MV
+	int "Minimum system voltage in milli-volts"
+	default 0
+	depends on PLATFORM_EC_CHARGER_BQ25710_VSYS_MIN_VOLTAGE_CUSTOM
+	help
+	  Sets the minimum system voltage in milli-volts. The bq25710
+	  uses 6 bits of resolution and can be configured from 1.024 V
+	  to 16.128 V in 256 mV increments. The bq25720 uses 8 bits of
+	  resolution and can be set from 1.0 V to 19.2 V in 100 mV
+	  increments. The default value depends on configured number of
+	  battery cells connected in series using the CELL_BATPRESZ
+	  strap.
+
+config PLATFORM_EC_CHARGER_MAINTAIN_VBAT
+	bool "Maintain VBAT voltage regardless of AC state"
+	help
+	  Leave the charger VBAT configured to battery-requested voltage under
+	  all conditions, even when AC is not present. This may be necessary to
+	  work around quirks of certain charger chips, such as the BD9995X.
+
+config PLATFORM_EC_CHARGER_BYPASS_MODE
+	bool "enable charger bypass mode"
+	help
+	  Select this option if the charger will be used in a bypass mode in
+	  order to pass the input current from AC directly to the system
+	  power rail for efficiency.
+
+config PLATFORM_EC_CHARGER_NARROW_VDC
+	bool
+	help
+	  Select this if the charger uses a Narrow Voltage Direct Charging.
+	  Narrow VDC (NVDC) reduces power loss by reducing the voltage range of
+	  the VDC node. This reduction is accomplished by replacing the
+	  battery-charger circuit with a system-charger voltage regulator, thus
+	  narrowing the VDC range. This in turn enables DC/DC converter
+	  optimisations in the system and allows the removal of the power-path
+	  switch, saving additional power, board area, and cost.
+
+	  This should be enabled by charger drivers which need it. It cannot
+	  be set otherwise, even in prj.conf
+
+config PLATFORM_EC_CHARGER_TRICKLE
+	bool
+	help
+	  Select this if the charger allows trickle charging, which allows
+	  the battery to charge with a minimum voltage.
+
+	  This should be enabled by charger drivers which need it.
+
+config PLATFORM_EC_CHARGER_OTG_SUPPORTED
+	bool
+	help
+	  Indicates that the charger supports an OTG (On-The-Go) function,
+	  which allows supplying output power from the battery to a connected
+	  device.
+
+	  This should be enabled by charger drivers which support it. It cannot
+	  be set otherwise, even in prj.conf
+
+config PLATFORM_EC_CHARGER_OTG
+	bool "Allow supplying output power from the battery"
+	depends on PLATFORM_EC_CHARGER_OTG_SUPPORTED
+	help
+	  Enable charger's OTG functions, i.e. make it possible to supply
+	  output power from the battery. This option is available if the
+	  selected charger supports it.
+
+config PLATFORM_EC_CHARGER_PROFILE_OVERRIDE
+	bool "Override the charger profile"
+	help
+	  Select this if the charger should call battery_override_params() to
+	  limit/correct the voltage and current requested by the battery pack
+	  before acting on the request.
+
+	  The board must provide this function:
+
+	    void battery_override_params(struct batt_params *batt);
+
+	  It may modify the parameters as needed.
+
+config PLATFORM_EC_CHARGER_PSYS
+	bool "Support system power-monitor (PSYS) function"
+	help
+	  Enable this to support monitoring of system power using the charger's
+	  PSYS function. The charger provides an output which can be read
+	  using an ADC channel on the EC.
+
+config PLATFORM_EC_CHARGER_PSYS_READ
+	bool "Allow reading PSYS (system power) value"
+	depends on PLATFORM_EC_CHARGER_PSYS
+	help
+	  Enable support for reading the system-power value (PSYS). This
+	  calls the function charger_get_system_power() which is provided
+	  by the charger.
+
+	  It also enables the "psys" console command.
+
+	  Sample output:
+
+	    PSYS from chg_adc: 456 mW
+
+config PLATFORM_EC_CHARGER_SENSE_RESISTOR
+	int "Value of the charge sense-resistor, in mOhms"
+	help
+	  The charge sense-resistor is used to detect the charge current to the
+	  battery. Its value must be known for the calculation to be correct.
+	  The value is typically around 10 mOhms.
+
+config PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC
+	int "Value of the input sense-resistor, in mOhms"
+	help
+	  The input sense-resistor is used to detect the input current from the
+	  external AC power supply. Its value must be known for the calculation
+	  to be correct. The value is typically around 10 mOhms.
+
+config PLATFORM_EC_CHARGER_CHGRAMP_BROKEN
+	bool
+	help
+	  This is selected if the charger's support for hardware-controlled
+	  charge ramping is broken. In some cases the charger has problems
+	  which make it unusable and we must fall back to software-controlled
+	  charge ramping.
+
+	  This should be enabled by charger drivers which need it. It cannot
+	  be set otherwise, even in prj.conf
+
+choice PLATFORM_EC_CHARGE_RAMP_TYPE
+	prompt "Select the charge-ramp method"
+	optional
+	help
+	  Select the method used for ramping up charging of a battery. It is
+	  preferred to use the hardware method if the charger chip can support
+	  it. If not, software-controlled charging can be used, with a slight
+	  increase in code size.
+
+config PLATFORM_EC_CHARGE_RAMP_HW
+	bool "Hardware-controlled charging"
+	depends on !PLATFORM_EC_CHARGER_CHGRAMP_BROKEN
+	help
+	   Disables software control of ramping up charging. This is used when
+	   the hardware has a mechanism for ramping input current and
+	   backing-off as needed.
+
+config PLATFORM_EC_CHARGE_RAMP_SW
+	bool "Software-controlled charging"
+	select HAS_TASK_CHG_RAMP
+	help
+	  Enables ramping up charging from an external source to the maximum
+	  available within the source's limits and taking into account the
+	  current needs of the device. It handles the user plugging chargers in
+	  and removing them.
+
+endchoice # PLATFORM_EC_CHARGE_RAMP_TYPE
+
+config PLATFORM_EC_CONSOLE_CMD_CHARGER_ADC_AMON_BMON
+	bool "Console command: amonbmon"
+	help
+	  Enable the 'amonbmon' command. This shows the charger adapter-current
+	  monitor (AMON) and battery-charging current monitor (BMON).
+
+	     amonbmon a | b
+
+config PLATFORM_EC_CONSOLE_CMD_CHGRAMP
+	bool "Console command: chgramp"
+	depends on PLATFORM_EC_CHARGE_RAMP_SW
+	default y
+	help
+	  Enable the "chgramp" command. This shows the current state of the
+	  chg_ramp task. It shows the state of each port and the current limit
+	  for each port. The 'State' shown is from enum chg_ramp_state.
+
+	  Chg Ramp:
+	    State: 5
+	    Min ICL: 2000
+	    Active ICL: 2000
+	    Port 0:
+	      OC idx:0
+	      OC 0: s-1 oc_det0 icl0
+	      OC 1: s0 oc_det0 icl0
+	      OC 2: s0 oc_det0 icl0
+	    Port 1:
+	      OC idx:0
+	      OC 0: s-1 oc_det0 icl0
+	      OC 1: s0 oc_det0 icl0
+	      OC 2: s0 oc_det0 icl0
+
+config PLATFORM_EC_CONSOLE_CMD_CHARGER_DUMP
+	bool "Console command: charger dump"
+	help
+	  Enable the "charger dump" subcommand. If the charger driver provides
+	  a dump_registers() function, this command shows its register dump.
+
+# TODO(b/229236582): Move this to devicetree
+config PLATFORM_EC_DEDICATED_CHARGE_PORT
+	bool "Dedicated charging port"
+	help
+	  Enable if there is a dedicated charging port on the system.
+
+if PLATFORM_EC_CHARGER_RAA489000
+
+choice
+	prompt "RAA489000 trickle charge current"
+	default PLATFORM_EC_RAA489000_TRICKLE_CHARGE_CURRENT_128MA
+	help
+	  Set the current limit when trickle-charging.
+
+config PLATFORM_EC_RAA489000_TRICKLE_CHARGE_CURRENT_64MA
+	bool "64 mA"
+	help
+	  Set the trickle charge current to 64 mA.
+
+config PLATFORM_EC_RAA489000_TRICKLE_CHARGE_CURRENT_96MA
+	bool "96 mA"
+	help
+	  Set the trickle charge current to 96 mA.
+
+config PLATFORM_EC_RAA489000_TRICKLE_CHARGE_CURRENT_128MA
+	bool "128 mA"
+	help
+	  Set the trickle charge current to 128 mA.
+
+config PLATFORM_EC_RAA489000_TRICKLE_CHARGE_CURRENT_160MA
+	bool "160 mA"
+	help
+	  Set the trickle charge current to 160 mA.
+
+config PLATFORM_EC_RAA489000_TRICKLE_CHARGE_CURRENT_192MA
+	bool "192 mA"
+	help
+	  Set the trickle charge current to 192 mA.
+
+config PLATFORM_EC_RAA489000_TRICKLE_CHARGE_CURRENT_224MA
+	bool "224 mA"
+	help
+	  Set the trickle charge current to 224 mA.
+
+config PLATFORM_EC_RAA489000_TRICKLE_CHARGE_CURRENT_256MA
+	bool "256 mA"
+	help
+	  Set the trickle charge current to 256 mA.
+
+endchoice
+
+config PLATFORM_EC_RAA489000_TRICKLE_CHARGE_CURRENT
+	int
+	default 64 if PLATFORM_EC_RAA489000_TRICKLE_CHARGE_CURRENT_64MA
+	default 96 if PLATFORM_EC_RAA489000_TRICKLE_CHARGE_CURRENT_96MA
+	default 128 if PLATFORM_EC_RAA489000_TRICKLE_CHARGE_CURRENT_128MA
+	default 160 if PLATFORM_EC_RAA489000_TRICKLE_CHARGE_CURRENT_160MA
+	default 192 if PLATFORM_EC_RAA489000_TRICKLE_CHARGE_CURRENT_192MA
+	default 224 if PLATFORM_EC_RAA489000_TRICKLE_CHARGE_CURRENT_224MA
+	default 256 if PLATFORM_EC_RAA489000_TRICKLE_CHARGE_CURRENT_256MA
+
+endif # PLATFORM_EC_CHARGER_RAA489000
+
+config PLATFORM_EC_ISL9238C_DISABLE_CMOUT_LATCH
+	bool "Disable the CMOUT latch function"
+	depends on PLATFORM_EC_CHARGER_ISL9238C
+	help
+	  Disable the CMOUT latch function for ISL9238C.
+
+config PLATFORM_EC_ISL9238C_ENABLE_BUCK_MODE
+	bool "Enable Force Buck mode"
+	default n
+	depends on PLATFORM_EC_CHARGER_ISL9238C
+	help
+	  Enable Force Buck mode for ISL9238C.
+	  If the Force Buck mode is enabled, the Buck-Boost window narrows.
+
+config PLATFORM_EC_ISL9238C_BUCK_PHASE_VOLTAGE
+	int "Value of phase comparator threshold offset"
+	default 0
+	help
+	  Adjusts the phase comparator threshold offset for forward buck
+	  and buck-boost.
+
+config PLATFORM_EC_AC_PROCHOT_CURRENT_MA
+	int "Value of the prochot threshold current in mA"
+	default 3328
+	help
+	  To set the PROCHOT# assertion threshold for adapter overcurrent
+	  conditions.
+
+config PLATFORM_EC_DC_PROCHOT_CURRENT_MA
+	int "Value of the prochot threshold current in mA"
+	default 6570
+	help
+	  To set the PROCHOT# signal assertion threshold for battery over
+	  discharging current conditions.
+
+config PLATFORM_EC_CHARGER_DUMP_PROCHOT
+	bool "Enable support for prochot status dumping functions"
+	default n
+
+endif # PLATFORM_EC_CHARGER
diff --git a/zephyr/Kconfig.chargesplash b/zephyr/Kconfig.chargesplash
new file mode 100644
index 0000000000..c23b51f2a7
--- /dev/null
+++ b/zephyr/Kconfig.chargesplash
@@ -0,0 +1,46 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+menuconfig PLATFORM_EC_CHARGESPLASH
+	bool "Charging splashscreen support"
+	depends on PLATFORM_EC_CHARGER
+	help
+	  Enable visual charging indicator to display on-screen when
+	  AC is initially connected.
+
+if PLATFORM_EC_CHARGESPLASH
+
+config PLATFORM_EC_CHARGESPLASH_PERIOD
+	int "Seconds for which chargesplash requests are tracked"
+	default 900
+	help
+	  A charger which is connecting and disconnecting frequently
+	  can indicate damage to the charger or port.  To prevent
+	  excessive power usage on a device plugged in and
+	  experiencing frequent AC connects, we monitor the number of
+	  AC connects over a period of time.  If the number of AC
+	  connects exceeds a defined value during that period of time,
+	  we inhibit all chargesplash requests until an entire period
+	  passes with no new AC connections.
+
+	  This config option defines the length of the period, in
+	  seconds.
+
+config PLATFORM_EC_CHARGESPLASH_MAX_REQUESTS_PER_PERIOD
+	int "Number of chargesplash requests per period which triggers lockout"
+	default 5
+	help
+	  A charger which is connecting and disconnecting frequently
+	  can indicate damage to the charger or port.  To prevent
+	  excessive power usage on a device plugged in and
+	  experiencing frequent AC connects, we monitor the number of
+	  AC connects over a period of time.  If the number of AC
+	  connects exceeds a defined value during that period of time,
+	  we inhibit all chargesplash requests until an entire period
+	  passes with no new AC connections.
+
+	  This config option defines the number of requests that must
+	  happen in one period to trigger the lockout condition.
+
+endif  # PLATFORM_EC_CHARGESPLASH
diff --git a/zephyr/Kconfig.console b/zephyr/Kconfig.console
new file mode 100644
index 0000000000..030217a87f
--- /dev/null
+++ b/zephyr/Kconfig.console
@@ -0,0 +1,103 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config PLATFORM_EC_CONSOLE_CHANNEL
+	bool "Console channels"
+	depends on CONSOLE
+	default y
+	help
+	  Make it possible for console to be output to different channels that
+	  can be turned on and off. Channels are organized by functional area
+	  such as "charger", "motionsense", "usbpd" and others.
+
+	  This is useful as a developer convenience when the console is crowded
+	  with messages, to make it easier to use the interactive console.
+
+	  The `chan` console command with no arguments shows all available
+	  channels.
+
+	  FAFT and servod also use this feature.
+
+	  Boards may #undef this to reduce image size.
+
+# Adjusted to the account for the build_info[] string (about 160 bytes) plus
+# the image type (about 16 bytes).
+# printed by the banner.
+config SHELL_PRINTF_BUFF_SIZE
+	default 180
+
+# Some boards may need to increase the size, depending on the amount of output
+config SHELL_BACKEND_SERIAL_TX_RING_BUFFER_SIZE
+	default 1024
+
+# For FAFT, need a larger RX ring
+config SHELL_BACKEND_SERIAL_RX_RING_BUFFER_SIZE
+	default 192
+
+config PLATFORM_EC_ISR_CONSOLE_OUTPUT
+	bool "Log in ISRs"
+	depends on CONSOLE
+	default y
+	help
+	  If enabled, allowing console output when in interrupt service routines
+	  via printk. If disabled, silently drop these messages.
+
+	  Console output via printk is unbuffered, so console output when in ISRs
+	  should be avoided if possible - larger amounts of output will prevent
+	  the EC from timely interrupt servicing.
+
+menuconfig PLATFORM_EC_HOSTCMD_CONSOLE
+	bool "Console Host Command"
+	depends on PLATFORM_EC_HOSTCMD
+	default y
+	help
+	  Enable the EC_CMD_CONSOLE_SNAPSHOT and EC_CMD_CONSOLE_READ
+	  host commands, used for reading the EC console from the AP.
+
+if PLATFORM_EC_HOSTCMD_CONSOLE
+
+config PLATFORM_EC_HOSTCMD_CONSOLE_BUF_SIZE
+	int "Console buffer size"
+	default 4096
+	help
+	  The EC will use a circular buffer to store bytes outputted
+	  to the console for the AP to read.  This changes the maximal
+	  number of bytes from the console output which can be saved.
+
+	  Choosing a power-of-two for this value is optimal, as
+	  modular arithmetic is used.
+
+endif # PLATFORM_EC_HOSTCMD_CONSOLE
+
+menuconfig PLATFORM_EC_CONSOLE_DEBUG
+	bool "Console Debug"
+	depends on CONSOLE
+	default n
+	help
+	  Write all zephyr_print() messages to printk() also. Not recommended
+	  outside of tests.
+
+
+config PLATFORM_EC_LOG_BACKEND_CONSOLE_BUFFER
+	bool "Logging backend for the console buffer"
+	depends on PLATFORM_EC_HOSTCMD_CONSOLE
+	depends on !LOG_MODE_MINIMAL
+	select LOG_OUTPUT
+	help
+	  Enable the logging backend for the console buffer.
+
+	  This will copy messages sent to the zephyr logging subsystem
+	  to the EC console buffer. This allows the AP to access the
+	  log messages with the console host command.
+
+config PLATFORM_EC_LOG_BACKEND_CONSOLE_BUFFER_TMP_BUF_SIZE
+	int "Size of temporary buffer used by console buffer logging backend"
+	default 128 if LOG_MODE_DEFERRED
+	default 1
+	depends on PLATFORM_EC_LOG_BACKEND_CONSOLE_BUFFER
+	help
+	  The size of the temporary buffer used by the console buffer backend.
+	  The logging subsystem will buffer up to this many bytes before calling
+	  the backend in deferred logging mode. Ideally this will be large
+	  enough to fit an entire log line.
diff --git a/zephyr/Kconfig.console_cmd_mem b/zephyr/Kconfig.console_cmd_mem
new file mode 100644
index 0000000000..9be465b488
--- /dev/null
+++ b/zephyr/Kconfig.console_cmd_mem
@@ -0,0 +1,32 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if PLATFORM_EC_CONSOLE_CMD_MEM
+config PLATFORM_EC_CONSOLE_CMD_MD
+	bool "Console command: md"
+	default y
+	help
+	  Enable the "md" command. This dumps memory value from a specified
+	  address, optionally specifying the format.
+
+	  Example:
+	     md 0x64000000 10
+
+	     64000000: 2a3b4d5e 030054e1 07000000 09297110
+	     64000010: 00000010 03db4f00 03db5000 00000100
+	     64000020: 00000000 00000000
+
+config PLATFORM_EC_CONSOLE_CMD_RW
+	bool "Console command: rw"
+	default y
+	help
+	  Enable the "rw" command. This Read or write in memory optionally
+	  specifying the size.
+
+	  Example:
+	     rw 0x64000000
+
+	     read 0x64000000 = 0x2a3b4d5e
+
+endif # PLATFORM_EC_CONSOLE_CMD_MEM
diff --git a/zephyr/Kconfig.debug_assert b/zephyr/Kconfig.debug_assert
new file mode 100644
index 0000000000..0d0fddbf6c
--- /dev/null
+++ b/zephyr/Kconfig.debug_assert
@@ -0,0 +1,50 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if PLATFORM_EC_DEBUG_ASSERT
+
+choice PLATFORM_EC_DEBUG_ASSERT_MODE
+	prompt "Select behaviour on assertion failure"
+	help
+	  This selects the action taken when the board hits an assertion
+	  failure in the code. This should not happen in normal operation,
+	  but can appear during development when the code is not yet fully
+	  tested.
+
+config PLATFORM_EC_DEBUG_ASSERT_REBOOTS
+	bool "Reboot"
+	help
+	  Prints a message and reboot if an assert() macro fails at runtime.
+	  If PLATFORM_EC_SOFTWARE_PANIC is enabled then the information is
+	  written to the panic log before rebooting.
+
+config PLATFORM_EC_DEBUG_ASSERT_BREAKPOINT
+	bool "Generate a breakpoint"
+	help
+	  Immediately hits a breakpoint instruction (without printing a message)
+	  so that a connected JTAG debugger can be used to debug the problem
+	  from there. If there is no debugger connected then the breakpoint
+	  instruction will cause the board to reboot immediately.
+
+endchoice # PLATFORM_EC_DEBUG_ASSERT_MODE
+
+config PLATFORM_EC_DEBUG_ASSERT_BRIEF
+	bool "Use brief assertion-failure messages"
+	depends on PLATFORM_EC_DEBUG_ASSERT_REBOOTS
+	select ASSERT_NO_COND_INFO
+	help
+	  Normally the assertion-failure messages include the expression that
+	  failed and the function name where the failure occurred. These are
+	  both stored as strings and can add a lot to the size of the image,
+	  since they are generated for every call to assert(). Use this option
+	  to drop them so that only the file and line number are shown.
+
+	  This option is of course not available with
+	  PLATFORM_EC_DEBUG_ASSERT_BREAKPOINT, since that does not print a
+	  message at all.
+
+	  ASSERT_NO_FILE_INFO and ASSERT_NO_MSG_INFO can also be enabled to
+	  further limit image size.
+
+endif # PLATFORM_EC_DEBUG_ASSERT
diff --git a/zephyr/Kconfig.defaults b/zephyr/Kconfig.defaults
new file mode 100644
index 0000000000..2f5ed71b24
--- /dev/null
+++ b/zephyr/Kconfig.defaults
@@ -0,0 +1,59 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Zephyr Kconfig overrides that applies to all platforms.
+
+# Disable timeslicing, it's compiled in by default and can be enabled at
+# runtime but not used in Zephyr EC.
+config TIMESLICING
+	default n
+
+config LOG
+	default y
+	imply LOG_DEFAULT_MINIMAL
+
+config GPIO
+	default y if ARCH_POSIX
+
+config THREAD_MAX_NAME_LEN
+	default 16
+
+config SHELL_PROMPT_UART
+	default "ec:~$ "
+
+config SHELL_VT100_COLORS
+	default n
+
+config SHELL_THREAD_PRIORITY_OVERRIDE
+	default y
+
+config SHELL_THREAD_PRIORITY
+	default 20
+
+config EXTRA_EXCEPTION_INFO
+	default y if ARCH_HAS_EXTRA_EXCEPTION_INFO
+
+config EEPROM_SHELL
+	default n
+
+config PWM_SHELL
+	default n
+
+config SENSOR_SHELL
+	default n
+
+config ESPI_NPCX_PERIPHERAL_DEBUG_PORT_80_MULTI_BYTE
+	default y
+
+choice INPUT_MODE
+	default INPUT_MODE_SYNCHRONOUS
+endchoice
+
+config CHECK_INIT_PRIORITIES
+	default y if !ZTEST
+
+config CHECK_INIT_PRIORITIES_FAIL_ON_WARNING
+	default y if !ZTEST
+
+orsource "Kconfig.defaults-$(ARCH)"
diff --git a/zephyr/Kconfig.defaults-arm b/zephyr/Kconfig.defaults-arm
new file mode 100644
index 0000000000..dd7e48fcee
--- /dev/null
+++ b/zephyr/Kconfig.defaults-arm
@@ -0,0 +1,17 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# ARM specific Kconfig overrides.
+
+config TRAP_UNALIGNED_ACCESS
+	default y
+
+choice NULL_POINTER_EXCEPTION_DETECTION
+	default NULL_POINTER_EXCEPTION_DETECTION_MPU
+endchoice
+
+config CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE
+	# Using 0x20 because NPCX accesses 0x40 for down_from_flash_api.
+	# See b/282983670 for other NPCX ROM accesses.
+	default "0x20"
diff --git a/zephyr/Kconfig.detachable_base b/zephyr/Kconfig.detachable_base
new file mode 100644
index 0000000000..08aed98aff
--- /dev/null
+++ b/zephyr/Kconfig.detachable_base
@@ -0,0 +1,20 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config PLATFORM_EC_DETACHABLE_BASE
+	bool "Detachable base support"
+	help
+		Enable base state related helpers.
+
+		If enabled, the board should implement a base_force_state()
+		function and board-specific base attach detection algorithm.
+
+		Enable this if the board has a detachable base.
+
+config PLATFORM_EC_BASE_ATTACHED_SWITCH
+	bool "Base attached switch"
+	depends on PLATFORM_EC_DETACHABLE_BASE
+	help
+		Add a virtual switch to indicate when detachable device has
+		base attached.
diff --git a/zephyr/Kconfig.espi b/zephyr/Kconfig.espi
new file mode 100644
index 0000000000..3e7210362c
--- /dev/null
+++ b/zephyr/Kconfig.espi
@@ -0,0 +1,41 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if PLATFORM_EC_HOST_INTERFACE_ESPI
+
+config PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S3
+	bool "SLP_S3 is an eSPI virtual wire instead of a GPIO"
+	help
+	  For power sequencing, use an eSPI virtual wire instead of
+	  defining GPIO_PCH_SLP_S3 in the GPIO device tree.
+
+config PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S4
+	bool "SLP_S4 is an eSPI virtual wire instead of a GPIO"
+	help
+	  For power sequencing, use an eSPI virtual wire instead of
+	  defining GPIO_PCH_SLP_S4 in the GPIO device tree.
+
+config PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S5
+	bool "SLP_S5 is an eSPI virtual wire instead of an alias for SLP_S4"
+	help
+	  For power sequencing, use an eSPI virtual wire to read the SLP_S5 line,
+	  as opposed to merging it into the same net as SLP_S4.
+
+config PLATFORM_EC_HOST_INTERFACE_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST
+	bool "Reset SLP VW signals on eSPI reset"
+	help
+	  Enable this config to reset SLP* VW when eSPI_RST is asserted
+	  for the Global Reset event case.  Don't enable this config if
+	  the platform implements the Deep-Sx entry as EC needs to
+	  maintain these pins' states per request. Note that this is
+	  currently unimplemented for Zephyr. Please see b/183148073.
+
+config PLATFORM_EC_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US
+	int "Virtual wire pulse width (microseconds)"
+	default 65
+	help
+	  The minimum pulse width of a eSPI/LPC virtual wire signals to the
+	  host. May vary by host chipset.
+
+endif # PLATFORM_EC_HOST_INTERFACE_ESPI
diff --git a/zephyr/Kconfig.flash b/zephyr/Kconfig.flash
new file mode 100644
index 0000000000..219238ce36
--- /dev/null
+++ b/zephyr/Kconfig.flash
@@ -0,0 +1,163 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if PLATFORM_EC_FLASH_CROS
+
+config PLATFORM_EC_CONSOLE_CMD_CHARGEN
+	bool "Console command: chargen"
+	default y
+	help
+	  Enables the "chargen" console command, which sends a continuous
+	  stream of characters to the EC console.
+
+	  This allows to create tests which validate console output by
+	  verifying that no characters in the received sequence were lost.
+
+config PLATFORM_EC_CONSOLE_CMD_FLASH
+	bool "Console commands: flasherase, flashread, flashwrite"
+	help
+	  Enables various console commands:
+
+	     flasherase - erase flash region
+	     flashread - read from flash to memory
+	     flashwrite - write memory to flash
+
+config PLATFORM_EC_CONSOLE_CMD_FLASHINFO
+	bool "Console commands: flashinfo"
+	default y
+	help
+	  Enables various console commands:
+
+	     flashinfo - displays information about the flash storage
+
+config PLATFORM_EC_CONSOLE_CMD_FLASH_WP
+	bool "Console commands: flashwp"
+	default y
+	help
+	  Enables various console commands:
+
+	     flashwp - change write-protection settings
+
+config PLATFORM_EC_CONSOLE_CMD_SYSJUMP
+	bool "Console command: sysjump"
+	default y
+	help
+	  Enables the sysjump console command used for testing and verifying
+	  that we're able to jump between images. Normally, in an EC build,
+	  there will exist 2 images (sometimes more): read-only (RO) and
+	  read-write (RW). This console command allows us to manually jump
+	  between the various images (or even to a random starting address) by
+	  copying the image data from flash to ram, then jumping to the image's
+	  entry point.
+
+choice PLATFORM_EC_STORAGE_TYPE
+       prompt "Code storage type"
+       default PLATFORM_EC_EXTERNAL_STORAGE if SOC_FAMILY_NPCX
+       default PLATFORM_EC_EXTERNAL_STORAGE if SOC_FAMILY_MEC
+       default PLATFORM_EC_INTERNAL_STORAGE if SOC_FAMILY_RISCV_ITE
+       default PLATFORM_EC_INTERNAL_STORAGE if SOC_FAMILY_STM32
+       help
+         Sets the EC code storage type.
+
+config PLATFORM_EC_EXTERNAL_STORAGE
+	bool "Flash is stored external to the EC"
+	help
+	  This indicates that the EC's flash is stored separately and is it
+	  not possible execute directly from it. Code must be loaded from
+	  the flash into internal SRAM before it can be executed. It is still
+	  possible to read and write the flash.
+
+config PLATFORM_EC_INTERNAL_STORAGE
+	bool "Flash is stored internal to the EC"
+	help
+	  This indicates that the EC code can reside on internal storage.
+	  This option implies XIP(eXecute-In-Place) semantics.
+	  i.e. code is being fetched directly from storage media.
+
+endchoice
+
+config PLATFORM_EC_RW_TOTAL_IMAGE_SIZE
+	hex
+	default $(dt_node_int_prop_hex,/binman/ec-rw,size)
+	help
+	  Total size of the EC RW image, including the 32-byte RW_FWID. The
+	  source of truth for this setting is the binman devicetree node.
+
+# Workaround for not being able to have commas in macro arguments
+DT_CHOSEN_CROS_FLASH := cros-ec,flash
+
+config PLATFORM_EC_FLASH_SIZE_BYTES
+	hex "flash size"
+	default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_CROS_FLASH))
+	help
+	  Total size of writable flash.
+
+config PLATFORM_EC_MAPPED_STORAGE
+	bool "Flash is mapped into the EC's address space"
+	default y if SOC_FAMILY_NPCX || SOC_FAMILY_RISCV_ITE
+	help
+	  This indicates that the EC's flash is directly mapped into
+	  its address space. This makes it easier to read and write the flash.
+	  If this is not defined, the flash driver must implement
+	  flash_physical_read().
+
+config PLATFORM_EC_MAPPED_STORAGE_BASE
+	hex "Mapped storage size"
+	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_CROS_FLASH))
+	depends on PLATFORM_EC_MAPPED_STORAGE
+	help
+	  Base address of memory-mapped flash storage, for platforms which
+	  define CONFIG_MAPPED_STORAGE.
+
+config PLATFORM_EC_FLASH_PSTATE
+	bool "Store persistent write protect for the flash inside"
+	default y if SOC_FAMILY_RISCV_ITE
+	help
+	  Store persistent write protect for the flash inside the flash data
+	  itself.  This allows ECs with internal flash to emulate something
+	  closer to a SPI flash write protect register.  If this is not
+	  defined, write protect state is maintained solely by the physical
+	  flash driver.
+
+config PLATFORM_EC_NPCX_FLASH_ERASE_SIZE
+	hex "Change the NPCX EC chip erase size"
+	default 0x10000
+	help
+	  THE NPCX supports erase sizes of 64 KiB, 32 KiB, and 4 KiB.
+	  The NPCX flash driver does not currently support CONFIG_FLASH_MULTIPLE_REGION,
+	  so set the erase size to the maximum (64 KiB) for the best performance.
+
+if PLATFORM_EC_FLASH_PSTATE
+
+config PLATFORM_EC_FLASH_PSTATE_BANK
+	bool "Store the pstate data in its own dedicated bank of flash"
+	default y
+	help
+	  Store the pstate data in its own dedicated bank of flash.  This allows
+	  disabling the protect-RO-at-boot flag without rewriting the RO
+	  firmware, but costs a bank of flash.
+
+	  If this is not defined, the pstate data is stored inside the RO
+	  firmware image itself.  This is more space-efficient, but the only way
+	  to clear the flag once it's set is to rewrite the RO firmware (after
+	  removing the WP screw, of course).
+
+config PLATFORM_EC_FLASH_PSTATE_LOCKED
+	bool "Lock the pstate by default"
+	depends on !PLATFORM_EC_FLASH_PSTATE_BANK
+	help
+	  Lock the pstate by default, Currently only supported when
+	  PLATFORM_EC_FLASH_PSTATE_BANK is not defined.
+
+endif # PLATFORM_EC_FLASH_PSTATE
+
+config PLATFORM_EC_USE_ZEPHYR_FLASH_PAGE_LAYOUT
+	bool "Use Zephyr flash page layout API to get sector information"
+	default y if SOC_FAMILY_STM32
+	select FLASH_PAGE_LAYOUT
+	help
+	  When enabled, EC will use flash page layout API to get information
+	  about flash sectors (index, offset, and size).
+
+endif # PLATFORM_EC_FLASH_CROS
diff --git a/zephyr/Kconfig.header b/zephyr/Kconfig.header
new file mode 100644
index 0000000000..02f9ecc1a7
--- /dev/null
+++ b/zephyr/Kconfig.header
@@ -0,0 +1,31 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config PLATFORM_EC_RO_HEADER
+	bool "RO section includes a header"
+	default y
+	depends on CROS_EC_RO
+	depends on SOC_FAMILY_NPCX || SOC_FAMILY_MEC
+	help
+	  The RO image residing on flash memory has a header section. The header
+	  is used on some chips (such as the npcx) to load the image correctly
+	  from flash. The values for offset and size are used by the linker
+	  scripts to generate the header. See core/cortex-m/ec.lds.S for
+	  reference.
+
+config PLATFORM_EC_RO_HEADER_OFFSET
+	hex "Offset in memory for the location of the header"
+	default 0x1000 if SOC_SERIES_MEC172X
+	default 0x0
+	help
+	  The offset (in bytes) of the header relative to the start address of
+	  the RO image.
+
+config PLATFORM_EC_RO_HEADER_SIZE
+	hex "Size of the RO header"
+	default 0x40 if SOC_FAMILY_NPCX
+	default 0x0
+	help
+	  The size of the RO header in bytes. This values should come from the
+	  datasheet of the chip being used.
diff --git a/zephyr/Kconfig.host_interface b/zephyr/Kconfig.host_interface
new file mode 100644
index 0000000000..50aee2dbb1
--- /dev/null
+++ b/zephyr/Kconfig.host_interface
@@ -0,0 +1,77 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if PLATFORM_EC_HOSTCMD
+
+choice PLATFORM_EC_HOST_INTERFACE_TYPE
+	prompt "Select the host interface type"
+	default PLATFORM_EC_HOST_INTERFACE_ESPI if AP_X86
+	default PLATFORM_EC_HOST_INTERFACE_SHI if AP_ARM
+	help
+	  The AP communicates with the EC using one of several host interface
+	  types.  The selection of the host interface type is based on the
+	  capability of both the AP and the EC.
+
+	  x86-compatible application processors typically use the enhanced SPI
+	  (ESPI) interface while other application processors use the SPI host
+	  interface (SHI).
+
+config PLATFORM_EC_HOST_INTERFACE_ESPI
+	bool "eSPI"
+	depends on ESPI && AP
+	help
+	  Enable the Enhanced Serial Peripheral Interface (eSPI) host interface.
+	  eSPI supports a shared physical connection between several on-board
+	  devices, similar to SPI. It adds a few optional signals and a protocol
+	  layer to provide independent 'channels' for each device to communicate
+	  over.
+
+	  eSPI is the replacement for LPC (Low-Pin-Count bus).
+
+	  See here for information about eSPI:
+
+	  https://www.intel.com/content/dam/support/us/en/documents/software/chipset-software/327432-004_espi_base_specification_rev1.0_cb.pdf
+
+config PLATFORM_EC_HOST_INTERFACE_HECI
+	bool "HECI"
+	depends on AP
+	help
+	  Enable the Host Embedded Controller Interface (HECI).
+
+
+config PLATFORM_EC_HOST_INTERFACE_LPC
+	bool "LPC"
+	depends on AP
+	help
+	  Enable the Low-Pin-Count (LPC) bus.
+
+config PLATFORM_EC_HOST_INTERFACE_SHI
+	bool "SPI Host Interface"
+	depends on AP
+	help
+	  Enable the SPI Host Interface (SHI). This is a traditional SPI (serial
+	  peripheral interface), where the AP is the SPI controller and the EC
+	  is the SPI peripheral.
+
+config PLATFORM_EC_HOST_INTERFACE_USB
+	bool "USB"
+	depends on AP
+	help
+	  Enable the USB host interface.
+
+endchoice # PLATFORM_EC_HOST_INTERFACE_TYPE
+
+config PLATFORM_EC_SCI_GPIO
+	bool "generated the SCI event via GPIO"
+	help
+	  Generated the SCI event vai the EC GPIO. This config just for verifying
+	  the SCI event and will remove when eSPI interface is workable.
+
+config PLATFORM_EC_HOST_EVENT64
+	bool "support 64-bit events"
+	help
+	  Config option to support 64-bit hostevents and
+	  wake-masks.
+
+endif # PLATFORM_EC_HOSTCMD
\ No newline at end of file
diff --git a/zephyr/Kconfig.i2c b/zephyr/Kconfig.i2c
new file mode 100644
index 0000000000..fa65ec8f9d
--- /dev/null
+++ b/zephyr/Kconfig.i2c
@@ -0,0 +1,87 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config PLATFORM_EC_I2C
+	bool "EC I2C Support"
+	default y
+	depends on DT_HAS_NAMED_I2C_PORTS_ENABLED
+	select I2C
+	help
+	  Enable compilation of the EC i2c module. Once enabled, it will be
+	  possible to make calls using the old platform/ec i2c APIs defined
+	  in include/i2c.h and implemented in common/i2c_controller.c. Doing so
+	  should make shimming other platform/ec modules which rely on i2c
+	  communication "just work" without requiring any further code changes.
+
+if PLATFORM_EC_I2C
+
+config PLATFORM_EC_I2C_DEBUG
+	bool "I2C Tracing"
+	help
+	  This option enables I2C bus communication tracing. Use the console
+	  command "i2ctrace" to enable and disable tracing on specific I2C
+	  peripherals.
+
+	  Please see the I2C debugging documentation for more details:
+
+	  https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/docs/i2c-debugging.md
+
+config PLATFORM_EC_I2C_PASSTHRU_RESTRICTED
+	bool "Restrict I2C PASSTHRU command"
+	help
+	  Enables board-specific restrictions for the I2C PASSTHRU host command.
+	  Once enabled, board_allow_i2c_passthru function has to be implemented,
+	  which defines the allowed usage of the command.
+
+config PLATFORM_EC_I2C_DEBUG_PASSTHRU
+	bool "I2C Passthru Debug"
+	help
+	  This option enables extra debug for I2C passthru operations initiated
+	  by the AP.
+
+config PLATFORM_EC_CONSOLE_CMD_I2C_PORTMAP
+	bool "Console command: i2c_portmap"
+	default y
+	help
+	  Enable the 'i2c_portmap' console command. This comamnd is used to
+	  display the mapping of the I2C ports defined by the named-i2c-ports
+	  node to the physical port and remote port indexes.
+
+config PLATFORM_EC_CONSOLE_CMD_I2C_SPEED
+	bool "Console command: i2cspeed"
+	help
+	  Enable the 'i2cspeed' console command. This comamnd is used to
+	  display an I2C port's bus speed. Additionally, for ports with
+	  the DYNAMIC_SPEED port flag set, the speed can be set. In all
+	  cases, the bus speed is in units of kHz.
+
+config PLATFORM_EC_HOSTCMD_I2C_CONTROL
+	bool "Host command: i2c_control"
+	help
+	  Enable the I2C_CONTROL host command. This comamnd is used to
+	  display an I2C port's bus speed. Additionally, for ports with
+	  the DYNAMIC_SPEED port flag set, the speed can be set. In all
+	  cases, the bus speed is in units of kHz. More functionality of
+	  the command may be added in the future.
+
+config PLATFORM_EC_SMBUS_PEC
+	bool "Packet error checking support for SMBus"
+	help
+	  If enabled, adds error checking support for i2c_readN, i2c_writeN,
+	  i2c_read_string and i2c_write_block. Where
+	  - write operation appends an error checking byte at end of transfer, and
+	  - read operatoin verifies the correctness of error checking byte from the
+	  peripheral.
+	  Set I2C_FLAG on addr_flags parameter to use this feature.
+
+	  This option also enables error checking function on smart batteries.
+
+config PLATFORM_EC_I2C_NACK_RETRY_COUNT
+	int "I2C operation retry count when transaction error"
+	default 0
+	help
+	  Defines I2C operation retry count when transaction general input/output
+	  error (-EIO) and also when the I2C is busy.
+
+endif # PLATFORM_EC_I2C
diff --git a/zephyr/Kconfig.ina2xx b/zephyr/Kconfig.ina2xx
new file mode 100644
index 0000000000..ce704deddb
--- /dev/null
+++ b/zephyr/Kconfig.ina2xx
@@ -0,0 +1,24 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+menuconfig PLATFORM_EC_INA2XX
+	bool "Support current-shunt and power monitor"
+	help
+	  Enables support for current-shunt and power monitor chips.
+	  Some project will use the current-shunt and power monitor chips
+	  to read the actaully current.
+
+if PLATFORM_EC_INA2XX
+
+config PLATFORM_EC_INA236
+	bool "Enable INA236 support"
+	depends on PLATFORM_EC_I2C
+	help
+	  Enables support for the INA236.
+	  This is a 16-bit digital current monitor with an I2C/SMBus-compatible
+	  interface that is compliant with a wide rang of digital bus voltages.
+	  The device monitors the voltage across an external sense resistor and
+	  reports values for current, bus voltage, and power.
+
+endif # PLATFORM_EC_INA2XX
diff --git a/zephyr/Kconfig.init_priority b/zephyr/Kconfig.init_priority
new file mode 100644
index 0000000000..421e8f7019
--- /dev/null
+++ b/zephyr/Kconfig.init_priority
@@ -0,0 +1,31 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config PLATFORM_EC_FLASH_INIT_PRIORITY
+  int "Init priority of the flash module"
+  default 90 if SOC_FAMILY_NPCX
+  default 90 if SOC_FAMILY_MEC
+  default 52
+  help
+    The initialization priority of the flash module. This should always be
+    greater than PLATFORM_EC_GPIO_INIT_PRIORITY.
+
+config PLATFORM_EC_GPIO_INIT_PRIORITY
+  int "Init priority of the GPIO module"
+  default 51
+  help
+    The initialization priority of the GPIO module. This should always happen
+    after the gpio drivers are initialized.
+
+config PLATFORM_EC_PWM_INIT_PRIORITY
+	int "Initialization priority of the PWM module"
+	depends on PLATFORM_EC_PWM
+	default 51
+	help
+	  Sets the initialization priority of the PWM module. This MUST be a
+	  value greater than the PWM driver's initialization priority which
+	  currently defaults to KERNEL_INIT_PRIORITY_DEVICE.
+
+config EEPROM_INIT_PRIORITY
+	default 70
diff --git a/zephyr/Kconfig.ioex b/zephyr/Kconfig.ioex
new file mode 100644
index 0000000000..9be34197db
--- /dev/null
+++ b/zephyr/Kconfig.ioex
@@ -0,0 +1,52 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+menuconfig PLATFORM_EC_IOEX_CROS_DRV
+	bool "IO expander support"
+	default y
+	depends on I2C && DT_HAS_CROS_IOEX_CHIP_ENABLED
+	help
+	  Enable support for CrOS EC ioex drivers.
+
+if PLATFORM_EC_IOEX_CROS_DRV
+
+config PLATFORM_EC_IOEX_INIT_PRIORITY
+	int "IO expander init priority"
+	range 0 99
+	default 50
+	help
+	  Sets the priority of function that initializes
+	  the IO expander subsystem
+
+config PLATFORM_EC_IOEX_CCGXXF
+	bool "Cypress CCGXXF"
+	help
+	  Enables driver for Cypress CCGXXF IO expander (built inside PD chip)
+
+config PLATFORM_EC_IOEX_IT8801
+	bool "IT8801"
+	help
+	  Enables support for IT8801 IO expander with keyboard matrix controller
+
+config PLATFORM_EC_IOEX_NCT38XX
+	bool "Nuvoton NCT38xx"
+	help
+	  Enables support for IO expander built inside Nuvoton NCT38xx TCPC
+
+config PLATFORM_EC_IOEX_PCA9675
+	bool "NXP PCA9675PW"
+	help
+	  Enables support for NXP PCA9675PW IO expander
+
+config PLATFORM_EC_IOEX_PCAL6408
+	bool "NXP PCA(L)6408"
+	help
+	  Enables support for NXP PCA(L)6408 IO expander
+
+config PLATFORM_EC_IOEX_TCA64XXA
+	bool "TI TCA64xA"
+	help
+	  Enables support for Texas Instruments TCA64xxA IO expanders family
+
+endif
diff --git a/zephyr/Kconfig.keyboard b/zephyr/Kconfig.keyboard
new file mode 100644
index 0000000000..a1c87929e9
--- /dev/null
+++ b/zephyr/Kconfig.keyboard
@@ -0,0 +1,317 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CHOSEN_CROS_EC_RAW_KB := cros-ec,raw-kb
+
+menuconfig PLATFORM_EC_KEYBOARD
+	bool "Keyboard support"
+	default y
+	depends on DT_HAS_CROS_KEYSCAN_ENABLED || $(dt_chosen_enabled,$(CHOSEN_CROS_EC_RAW_KB))
+	select HAS_TASK_KEYSCAN
+	help
+	  Enable compilation of support for scanning a keyboard and providing
+	  the resulting input to the AP over the host interface. This consists
+	  of a keyboard-scanning task which provides key scans via it calling
+	  keyboard_state_changed() (for i8042) or its client calling
+	  keyboard_scan_get_state() (for MKBP).
+
+	  Enabling this automatically enables HAS_TASK_KEYSCAN since keyboard
+	  scanning must run in its own task.
+
+if PLATFORM_EC_KEYBOARD
+
+config CROS_EC_KEYSCAN
+	bool "Devicetree based keyscan map"
+	default y
+	depends on DT_HAS_CROS_EC_KEYSCAN_ENABLED
+	help
+	  Define a keyscan_config data structure based on a the keyscan
+	  configuration found in devicetree. Requires a cros-ec,keyscan node to
+	  be defined.
+
+choice PLATFORM_EC_KEYBOARD_PROTOCOL_MODE
+	prompt "Select the keyboard protocol to use"
+	depends on AP
+	help
+	  Select the keyboard protocol used to communicate key presses to the
+	  AP. PLATFORM_EC_KEYBOARD_PROTOCOL_8042 is supported by x86-compatible
+	  application processors, and PLATFORM_EC_KEYBOARD_PROTOCOL_MKBP is
+	  used for ARM application processors.
+
+config PLATFORM_EC_KEYBOARD_PROTOCOL_8042
+	bool "i8042"
+	select HAS_TASK_KEYPROTO
+	help
+	  Use the i8042 protocol to communicate with the AP. This dates from the
+	  Intel 8042 keyboard controller chip released in 1976. It uses two-way
+	  communication via a few 8-bit registers, allowing key codes to be
+	  sent to the AP when keys are pressed and released.
+
+	  See here for docs: https://wiki.osdev.org/%228042%22_PS/2_Controller
+
+config PLATFORM_EC_KEYBOARD_PROTOCOL_MKBP
+	bool "mkbp"
+	select MKBP_PROTOCOL
+	help
+	  Use the MKBP protocol to communicate with the AP. This protocol is
+	  usually used on ARM-based platforms. It sends the raw scan code, like
+	  (row, col), to the AP and the kernel driver will map this scan code to
+	  a key.
+
+endchoice # PLATFORM_EC_KEYBOARD_PROTOCOL_MODE
+
+config PLATFORM_EC_KEYBOARD_DISCRETE
+	bool "Support discrete Keyboard"
+	default y
+	depends on $(dt_nodelabel_enabled,kb_discrete)
+	help
+	  Enable support for a discrete Keyboard if the platform needs one
+	  or the raw Keyboard support is not built-in in the EC.
+
+config PLATFORM_EC_KEYBOARD_DEBUG
+	bool "Enable keyboard debug prints"
+	depends on PLATFORM_EC_SYSTEM_UNLOCKED
+	help
+	  Enable keyboard debug prints to show up in early bringup, for example
+	  if the board is currently headless and keyboard functionality is being
+	  checked.
+
+config PLATFORM_EC_KEYBOARD_FACTORY_TEST
+	bool "Support keyboard factory test"
+	help
+	  Enable support "ectool kbfactorytest" command.
+	  Need to map keyboard connector pins to EC GPIO pins in
+	  keyboard_factory_scan_pins table.
+
+config PLATFORM_EC_KEYBOARD_KEYPAD
+	bool "Support a numeric keypad"
+	help
+	  Enable support for a keypad, a palm-sized keyboard section usually
+	  placed on the far right. This contains nuumber keys and also some
+	  commonly used symbols, to help speed up numeric data entry.
+
+config PLATFORM_EC_KEYBOARD_VIVALDI
+	bool "Vivaldi keyboard support"
+	depends on PLATFORM_EC_KEYBOARD_PROTOCOL_8042
+	default y
+	help
+	  Enable code for Vivaldi keyboard (standard for new Chromium OS
+	  devices). A Chromium OS device is Vivaldi compatible if the keyboard
+	  matrix complies with: go/vivaldi-matrix.
+
+	  Vivaldi code enables:
+	  - A response to EC_CMD_GET_KEYBD_CONFIG command.
+	  - Boards can specify their custom layout for top keys.
+
+config PLATFORM_EC_KEYBOARD_CUSTOMIZATION
+	bool "Support keyboard customization"
+	help
+	  Enable support for customization keyboard, some boards need to custom matrix
+	  because those board keyboard layout doesn't follow a common matrix.
+
+	  If define, the board layer
+	  needs to implement:
+	  1. the scancode_set2 and keycap_label array
+	  2. keyboard_customization.h which is similar to keyboard_config.h
+
+	  Note that if your board has the standard chromeos keyboard layout other
+	  than the top row, and you are looking only for top row customization,
+	  then you should be looking at overriding board_vivaldi_keybd_config() instead.
+
+choice PLATFORM_EC_KEYBOARD_PWRBTN_MODE
+	prompt "Select the impact of pressing the power button"
+	help
+	  On some boards one of the keyboard-scan inputs is affected by pressing
+	  the power button. When the power button is pressed, that input needs
+	  to be ignored in that case.
+
+config PLATFORM_EC_KEYBOARD_PWRBTN_INDEPENDENT
+	bool "No impact on keyboard-scan inputs"
+	help
+	  Select this if pressing the power button does not affect any
+	  keyboard-scan inputs.
+
+config PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI2
+	bool "Forces KSI2 to be asserted"
+	help
+	  Enable this if KSI2 is stuck 'asserted' for all scan columns if the
+	  power button is held. This applies if the refresh key is on KSI2.
+	  The GSC will assert this row for all columns during a recovery boot.
+
+config PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI3
+	bool "Forces KSI3 to be asserted"
+	help
+	  Enable this if KSI3 is stuck 'asserted' for all scan columns if the
+	  power button is held. This applies if the refresh key is on KSI3.
+	  The GSC will assert this row for all columns during a recovery boot.
+
+endchoice # PLATFORM_EC_KEYBOARD_PWRBTN_MODE
+
+config PLATFORM_EC_KEYBOARD_COL2_INVERTED
+	bool "A mechanism for passing KSO2 to H1 which inverts the signal"
+	help
+	  This option enables a mechanism for passing the column 2
+	  to H1 which inverts the signal. The signal passing through H1
+	  adds more delay. Need a larger delay value. Otherwise, pressing
+	  Refresh key will also trigger T key, which is in the next scanning
+	  column line. See http://b/156007029.
+
+	  Your board file must define the node alias "gpio-kbd-kso2" that points
+	  to the GPIO pin used for the column 2 output.
+
+config PLATFORM_EC_KEYBOARD_REFRESH_ROW3
+	bool "Move the refresh key matrix to row 3 instead of row 2"
+	help
+	  The Vivaldi keyboards have the refresh key on row 3 instead of row 2.
+	  The legacy keyboards with the assistant key also move the refresh key
+	  matrix to row 3. This is used by the boot key detection code to
+	  determine if the refresh key is held down at boot.
+
+config PLATFORM_EC_KEYBOARD_SCAN_ADC
+	bool "Keyboard supports antighost feature"
+	help
+	  Enable this to support anti-ghost feature. KSI lines need to be
+	  connected to adc channels to identify key presses by reading adc
+	  voltage.
+
+config PLATFORM_EC_VOLUME_BUTTONS
+	bool "Board has volume-up and volume-down buttons"
+	help
+	  Enable this if the board has physical buttons for the volume controls.
+	  These are buttons controlled by GPIOs and are not part of the keyboard
+	  matrix.
+
+	  Your board must define GPIO_VOLUME_UP_L and GPIO_VOLUME_DOWN_L as
+	  GPIOs names or as aliases in the GPIO devicetree configuration.
+
+config PLATFORM_EC_BUTTONS_RUNTIME_CONFIG
+	bool "Enable buttons runtime configuration"
+	help
+	  This command allow the runtime configuration of the buttons[]
+	  array.
+
+config PLATFORM_EC_CMD_BUTTON
+	bool "Console command: button"
+	help
+	  This command simulates button press. The buttons are like volume-up,
+	  volume-down, and recovery buttons.
+
+config PLATFORM_EC_BUTTON_TRIGGERED_RECOVERY
+	bool "Support entering recovery mode using buttons"
+	help
+	  Support for entering recovery mode using the volume buttons or a
+	  dedicated recovery button. Note that these are *buttons* and not keys
+	  in the keyboard matrix.
+
+config PLATFORM_EC_CONSOLE_CMD_KEYBOARD
+	bool "Console command: ksstate, kbpress, 8042"
+	default y if PLATFORM_EC_KEYBOARD
+	help
+	  Enable keyboard related console commands.
+
+	    ksstate     - Show or toggle printing keyboard scan state
+	    kbpress     - Simulate keypress
+
+	  If PLATFORM_EC_KEYBOARD_PROTOCOL_8042 is enabled, it includes 8042
+	  command which prints the state of the i8042 keyboard protocol and
+	  includes the following subcommands:
+
+	    codeset	- Get/set keyboard codeset
+	    ctrlram	- Get/set keyboard controller RAM
+	    internal    - Show internal information
+	    kbd		- Print or toggle keyboard info
+	    kblog	- Print or toggle keyboard event log (current disabled)
+	    typematic	- Get/set typematic delays
+
+config PLATFORM_EC_KEYBOARD_BACKLIGHT
+	bool "Keyboard backlight"
+	help
+	  Enables support for a keyboard backlight. The board specific code must
+	  define the board_kblight_init() routine, unless the
+	  CONFIG_PLATFORM_EC_PWM_KBLIGHT option is enabled.
+
+config PLATFORM_EC_PWM_KBLIGHT
+	bool "PWM keyboard backlight"
+	default y
+	depends on DT_HAS_CROS_EC_KBLIGHT_PWM_ENABLED
+	select PWM
+	select PLATFORM_EC_PWM_HC
+	select PLATFORM_EC_KEYBOARD_BACKLIGHT
+	help
+	  Enables a PWM-controlled keyboard backlight controlled by a PWM signal
+	  connected directly to the EC chipset. The board devicetree file must
+	  define a "cros-ec,kblight-pwm" compatible device node.
+
+config PLATFORM_EC_KBLIGHT_ENABLE_PIN
+	bool "Keyboard backlight enable pin"
+	help
+	  Enables control of the keyboard backlight through a GPIO enable and
+	  disable pin.  This pin must be defined as GPIO_EN_KEYBOARD_BACKLIGHT.
+
+config PLATFORM_EC_KEYBOARD_STRICT_DEBOUNCE
+	bool "Keyboard strict debouncer"
+	help
+	  Enable strict debouncer. A strict debouncer waits until debounce
+	  is done before registering key up/down while a non-strict debouncer
+	  registers a key up/down as soon as a key is pressed or released.
+	  If a strict debouncer is used, it's recommended to set
+	  debounce_down_us and debounce_up_us to an equal value. This guarantees
+	  key events are registered in the order the keys are pressed.
+
+config PLATFORM_KEYBOARD_SCANCODE_CALLBACK
+	bool "Keyboard scan code callback support"
+	help
+	  Enable callback support, board-specific 8042 keyboard callback
+	  when a key state is changed.
+
+endif # PLATFORM_EC_KEYBOARD
+
+
+menuconfig PLATFORM_EC_RGB_KEYBOARD
+	bool "RGB keyboard support"
+	select HAS_TASK_RGBKBD
+	help
+	  Enable RGB keyboard backlight control. This consists of a RGB matrix
+	  control task. Note this feature does not include key scanning.
+
+if PLATFORM_EC_RGB_KEYBOARD
+
+config PLATFORM_EC_RGB_KEYBOARD_DEBUG
+	bool "RGB Keyboard Debug"
+	default n
+	help
+	  Enable debug messages from a RGB keyboard task.
+
+choice PLATFORM_EC_RGBKBD_DEMO
+	prompt "RGB Keyboard demo to run on reset"
+	optional
+	help
+	  Enable demo of RGB keyboard to run on reset.
+
+config PLATFORM_EC_RGBKBD_DEMO_FLOW
+	bool "Flow"
+	help
+	  In each iteration, a new color is placed in (0,0) and the rest of
+	  LEDs copy colors from adjacent LEDs.
+
+config PLATFORM_EC_RGBKBD_DEMO_DOT
+	bool "Dot"
+	help
+	  A red dot is placed on (0,0) and traverses the grid from top to buttom
+	  left to right. After the entire matrix is traversed, it's repeated with
+	  a new color.
+
+endchoice # PLATFORM_EC_RGBKBD_DEMO
+
+config PLATFORM_EC_LED_DRIVER_IS31FL3743B
+	bool "Driver for IS31FL3743B LED controller"
+	help
+	  Enable driver for IS31FL3743B LED controller.
+
+config PLATFORM_EC_LED_DRIVER_AW20198
+	bool "Driver for AW20198 LED controller"
+	help
+	  Enable driver for AW20198 LED controller.
+
+endif # PLATFORM_EC_RGB_KEYBOARD
diff --git a/zephyr/Kconfig.led b/zephyr/Kconfig.led
new file mode 100644
index 0000000000..da00d6ff9c
--- /dev/null
+++ b/zephyr/Kconfig.led
@@ -0,0 +1,186 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+menuconfig PLATFORM_EC_LED_COMMON
+	depends on !PLATFORM_EC_LED_DT
+	bool "LED Support"
+	help
+	  Enable the common LED module supporting automatic control of the
+	  battery and power LEDs.
+
+if PLATFORM_EC_LED_COMMON
+
+# TODO: Add other choices
+#  CONFIG_LED_POLICY_STD
+#  CONFIG_LED_PWM_CHARGE_STATE_ONLY
+#  CONFIG_LED_PWM_ACTIVE_CHARGE_PORT_ONLY
+#  CONFIG_LED_ONOFF_STATES
+
+config PLATFORM_EC_LED_PWM
+	bool "PWM (Pulse Width Modulation) LEDs"
+	default y
+	depends on DT_HAS_CROS_EC_PWM_LEDS_ENABLED
+	select PWM
+	help
+	  Enable PWM (Pulse Width Modulation) controlled LEDs that conform to
+	  the Chromium OS LED behavior specification.
+
+	  Your board files must implement led_set_brightness() function, which
+	  is used by the LED PWM module to set the board LEDs in response to
+	  power and charging events.
+
+if PLATFORM_EC_LED_PWM
+
+config PLATFORM_EC_LED_PWM_TASK_DISABLED
+	bool "Disable common PWM LEDs Task"
+	help
+	  Support common PWM (Pulse Width Modulation) controlled LEDs that do
+	  not conform to the Chromium OS LED behavior specification.
+
+	  Your board code must define and enable it's own task for managing the
+	  LEDs.
+
+config PLATFORM_EC_CONSOLE_CMD_LEDTEST
+	bool "Console command: ledtest"
+	default y
+	help
+	  Enable the "ledtest" command. This command lets you override the
+	  automatic control of the platform LEDs. For example:
+
+	    ledtest 0 enable red
+
+	  disables automatic control of the first PWM LED and forces the LED
+	  color to red.  Set the 2nd parameter to "disable" to return back
+	  to automatic control:
+
+	    ledtest 0 disable
+
+config PLATFORM_EC_LED_PWM_CHARGE_COLOR
+	int "Battery charging LED color"
+	default 5
+	range 0 5
+	help
+	  Configure the color of LED when battery is charging:
+	    0 - EC_LED_COLOR_RED
+	    1 - EC_LED_COLOR_GREEN
+	    2 - EC_LED_COLOR_BLUE
+	    3 - EC_LED_COLOR_YELLOW
+	    4 - EC_LED_COLOR_WHITE
+	    5 - EC_LED_COLOR_AMBER
+
+	  This value is mapped directly to enum ec_led_colors.
+
+config PLATFORM_EC_LED_PWM_CHARGE_ERROR_COLOR
+	int "Charging error LED color"
+	default 0
+	range 0 5
+	help
+	  Configure the color of LED when Charging error or battery not present:
+	    0 - EC_LED_COLOR_RED
+	    1 - EC_LED_COLOR_GREEN
+	    2 - EC_LED_COLOR_BLUE
+	    3 - EC_LED_COLOR_YELLOW
+	    4 - EC_LED_COLOR_WHITE
+	    5 - EC_LED_COLOR_AMBER
+
+	  This value is mapped directly to enum ec_led_colors.
+
+config PLATFORM_EC_LED_PWM_NEAR_FULL_COLOR
+	int "Battery almost full LED color"
+	default 1
+	range 0 5
+	help
+	  Configure the color of LED when charge battery is almost full:
+	    0 - EC_LED_COLOR_RED
+	    1 - EC_LED_COLOR_GREEN
+	    2 - EC_LED_COLOR_BLUE
+	    3 - EC_LED_COLOR_YELLOW
+	    4 - EC_LED_COLOR_WHITE
+	    5 - EC_LED_COLOR_AMBER
+
+	  This value is mapped directly to enum ec_led_colors.
+
+config PLATFORM_EC_LED_PWM_SOC_ON_COLOR
+	int "AP powered on LED color"
+	default 1
+	range 0 5
+	help
+	  Configure the color of LED when AP powered on:
+	    0 - EC_LED_COLOR_RED
+	    1 - EC_LED_COLOR_GREEN
+	    2 - EC_LED_COLOR_BLUE
+	    3 - EC_LED_COLOR_YELLOW
+	    4 - EC_LED_COLOR_WHITE
+	    5 - EC_LED_COLOR_AMBER
+
+	  This value is mapped directly to enum ec_led_colors.
+
+config PLATFORM_EC_LED_PWM_SOC_SUSPEND_COLOR
+	int "AP suspended LED color"
+	default 1
+	range 0 5
+	help
+	  Configure the color of LED when AP suspended:
+	    0 - EC_LED_COLOR_RED
+	    1 - EC_LED_COLOR_GREEN
+	    2 - EC_LED_COLOR_BLUE
+	    3 - EC_LED_COLOR_YELLOW
+	    4 - EC_LED_COLOR_WHITE
+	    5 - EC_LED_COLOR_AMBER
+
+	  This value is mapped directly to enum ec_led_colors.
+
+config PLATFORM_EC_LED_PWM_LOW_BATT_COLOR
+	int "Low battery LED color"
+	default 5
+	range 0 5
+	help
+	  Configure the color of LED when battery is low:
+	    0 - EC_LED_COLOR_RED
+	    1 - EC_LED_COLOR_GREEN
+	    2 - EC_LED_COLOR_BLUE
+	    3 - EC_LED_COLOR_YELLOW
+	    4 - EC_LED_COLOR_WHITE
+	    5 - EC_LED_COLOR_AMBER
+
+	  This value is mapped directly to enum ec_led_colors.
+
+endif # PLATFORM_EC_LED_PWM
+
+config PLATFORM_EC_LED_ONOFF_STATES
+	bool "EC LED On-Off States"
+	help
+	  Enable EC Standard LED On-Off state code that conforms to the
+	  Chromium OS LED On-Off state behavior.
+
+if PLATFORM_EC_LED_ONOFF_STATES
+
+config PLATFORM_EC_LED_ONOFF_STATES_BAT_LOW
+	int "EC LED On-Off State Battery Low Percentage"
+	default 10
+	help
+	  Enable EC Standard LED On-Off bettery low percentage
+	  for standard Chromium OS LED On-Off battery low
+	  state behavior.
+
+endif # PLATFORM_EC_LED_ONOFF_STATES
+
+endif # PLATFORM_EC_LED_COMMON
+
+config PLATFORM_EC_MAX695X_SEVEN_SEGMENT_DISPLAY
+	bool "MAX695X Seven Segment Display"
+	default y
+	depends on DT_HAS_MAXIM_MAX695X_ENABLED
+	help
+	  Enable this to support MAX6958/MAX6959 7-Segment LED Display.
+	  The MAX6958/MAX6959 is a compact multiplexed common - cathode display
+	  designed to interface microprocessors with seven - segment numerical
+	  LED digits or to discrete LEDs via a 2-wire serial interface
+	  compatible with SMBusTM and I2C.
+
+config PLATFORM_EC_CONSOLE_CMD_SEVEN_SEGMENT_DISPLAY
+	bool "Console command: seg"
+	help
+	  Enable the "seg" console command. This command allow the user to write
+	  on seven segment display.
diff --git a/zephyr/Kconfig.led_dt b/zephyr/Kconfig.led_dt
new file mode 100644
index 0000000000..5f27c4b5a7
--- /dev/null
+++ b/zephyr/Kconfig.led_dt
@@ -0,0 +1,31 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+menuconfig PLATFORM_EC_LED_DT
+	bool "DT LED Support"
+	default y
+	depends on DT_HAS_CROS_EC_LED_POLICY_ENABLED
+	help
+	  Enable devicetree based LED module supporting automatic control of the
+	  battery and power LEDs.
+
+if PLATFORM_EC_LED_DT
+
+config PLATFORM_EC_LED_DT_GPIO
+	bool "DT LED Support (GPIO)"
+	default y
+	depends on DT_HAS_CROS_EC_GPIO_LED_PINS_ENABLED
+	help
+	  Enable support for devicetree GPIO LEDs, requires a node using the
+	  cros-ec,gpio-led-pins compatible.
+
+config PLATFORM_EC_LED_DT_PWM
+	bool "DT LED Support (PWM)"
+	default y
+	depends on DT_HAS_CROS_EC_PWM_LED_PINS_ENABLED
+	select PWM
+	help
+	  Enable support for devicetree PWM LEDs, requires a node using the
+          cros-ec,pwm-led-pins compatible.
+endif
diff --git a/zephyr/Kconfig.mkbp_event b/zephyr/Kconfig.mkbp_event
new file mode 100644
index 0000000000..636f3fb08e
--- /dev/null
+++ b/zephyr/Kconfig.mkbp_event
@@ -0,0 +1,61 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if PLATFORM_EC_MKBP_EVENT
+
+choice
+    prompt "MKBP delivery method"
+    default PLATFORM_EC_MKBP_USE_GPIO
+    help
+      Select MKBP delivery method
+
+config PLATFORM_EC_MKBP_USE_GPIO
+    bool "Use GPIO"
+    help
+      Select to send MKBP events via GPIO. You should define GPIO_EC_INT_L
+      as a GPIO output from the EC. The GPIO is used to indicate an
+      event is ready for serving by the AP.
+
+config PLATFORM_EC_MKBP_USE_HOST_EVENT
+    bool "Use host event"
+    help
+      Select to send MKBP events via host event.
+
+config PLATFORM_EC_MKBP_USE_HECI
+    bool "Use HECI"
+    help
+      Select to send MKBP events via HECI.
+
+config PLATFORM_EC_MKBP_USE_GPIO_AND_HOST_EVENT
+    bool "Use GPIO and host event"
+    help
+      MKBP events are notified by using both a GPIO and a host event.
+
+      You should use this if you are using a GPIO to notify the AP of an MKBP
+      event, and you need an MKBP event to wake the AP in suspend and the
+      AP cannot wake from the GPIO.  Since you are using both a GPIO and
+      a hostevent for the notification, make sure that the S0 hostevent mask
+      does NOT include MKBP events.  Otherwise, you will have multiple
+      consumers for a single event. However, make sure to configure the
+      host event *sleep* mask in coreboot to include MKBP events. In order to
+      prevent all MKBP events from waking the AP, use
+      CONFIG_MKBP_EVENT_WAKEUP_MASK to filter the events.
+
+config PLATFORM_EC_MKBP_USE_CUSTOM
+    bool "Use custom method"
+    help
+      Select to send MKBP events using custom method. You need to define
+      mkbp_set_host_active_via_custom() which is called when there's a MKBP event
+      to be sent. for more about the function, refer to mkbp_event.h.
+
+endchoice
+
+config PLATFORM_EC_MKBP_USE_GPIO_ACTIVE_HIGH
+    bool "EC_SOC_INT active high"
+    default n
+    depends on PLATFORM_EC_MKBP_USE_GPIO
+    help
+      Select if HW invert the SOC_INT signal on EC side.
+
+endif # PLATFORM_EC_MKBP_EVENT
diff --git a/zephyr/Kconfig.motionsense b/zephyr/Kconfig.motionsense
new file mode 100644
index 0000000000..30a7e0543b
--- /dev/null
+++ b/zephyr/Kconfig.motionsense
@@ -0,0 +1,209 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+menuconfig PLATFORM_EC_MOTIONSENSE
+    bool "Motion Sense"
+    default y
+    depends on DT_HAS_CROS_EC_MOTIONSENSE_SENSOR_INFO_ENABLED || \
+      $(dt_nodelabel_enabled,lid_accel) || \
+      $(dt_nodelabel_enabled,base_accel) || \
+      $(dt_nodelabel_enabled,base_gyro)
+    select HAS_TASK_MOTIONSENSE
+    help
+      Enable motion sense task. The task collects data from available sensors
+      and report them to AP. Besides the task reports the sensor data to AP.
+      Based on the data, it also does other things like calculating lid angle
+      and detect tablet mode.
+
+if PLATFORM_EC_MOTIONSENSE
+
+config PLATFORM_EC_ACCEL_FIFO
+    bool "Sensor FIFO"
+    help
+      Enable this to add the sensor FIFO used by sensor device drivers to fill.
+      Using FIFO reduces power consumption since it reduces the number of
+      AP wake-ups.
+
+if PLATFORM_EC_ACCEL_FIFO
+
+config PLATFORM_EC_ACCEL_FIFO_SIZE
+    int "Motion Sense FIFO Size"
+    default 256
+    help
+      This sets the size of the sensor FIFO, must be a power of 2.
+
+config PLATFORM_EC_ACCEL_FIFO_THRES
+    int "FIFO Threshold"
+    default 85      # (PLATFORM_EC_ACCEL_FIFO_SIZE / 3)
+    help
+      This sets the amount of free entries that trigger an interrupt to the AP.
+
+endif # PLATFORM_EC_ACCEL_FIFO
+
+config PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS
+    bool "Extra Sensor Timestamp"
+    help
+      If this is defined, motion_sense sends
+      sensor events to the AP in the format
+      +-----------+
+      | Timestamp |
+      |  Payload  |
+      | Timestamp |
+      |  Payload  |
+      |    ...    |
+      +-----------+
+      If this is not defined, the events will be sent in the format
+      +-----------+
+      |  Payload  |
+      |  Payload  |
+      |  Payload  |
+      |    ...    |
+      | Timestamp |
+      +-----------+
+      The former format enables improved filtering of sensor event
+      timestamps on the AP, but comes with stricter jitter requirements.
+
+# TODO(b/173507858) config PLATFORM_EC_MOTION_FILL_LPC_SENSE_DATA
+# if PLATFORM_EC_MOTION_FILL_LPC_SENSE_DATA
+#endif # PLATFORM_EC_MOTION_FILL_LPC_SENSE_DATA
+
+config PLATFORM_EC_MAX_SENSOR_FREQ_MILLIHZ
+    int "Maximal EC sampling rate"
+    default 250000
+    help
+       Lower this limit for slower EC (in mHz).
+
+config PLATFORM_EC_ALS
+    bool "Ambient Light Sensor(ALS)"
+    help
+      Enable this to indicate there's at least one or more ALS devices available.
+      If PLATFORM_EC_MOTION_FILL_LPC_SENSE_DATA is set, then motion task updates
+      the designated part of EC memmap with the ALS data. The updating EC memmap
+      can be also done by the dedicated ALS task with HAS_ALS_TASK set.
+      Number of ALS entries reserved in EC memmap are defined by EC_ALS_ENTRIES
+      in ec_commands.h.
+
+config PLATFORM_EC_DYNAMIC_MOTION_SENSOR_COUNT
+    bool "Dynamic Motion Sensor Count"
+    help
+      Enable this to allow changing motion sensor count dynamically.
+
+config PLATFORM_EC_LID_ANGLE
+    bool "Lid Angle"
+    select PLATFORM_EC_MATH_UTIL
+    help
+      Enable this to detect lid angle with two accelerometers. The andgle
+      calculation requires the information about which sensor is on the lid
+      and which one is on the base. The measured lid angle can be used for
+      tablet mode detection(refer "Tablet Mode below") and enabling/disabling
+      peripheral devices(refer "Lid Angle Update" below).
+      # TODO(b/173507858): add more detail after .dts change
+
+config PLATFORM_EC_LID_ANGLE_UPDATE
+    bool "Lid Angle Update"
+    depends on PLATFORM_EC_LID_ANGLE
+    help
+      Enable this to allow using the lid angle measurement to determine if
+      peripheral devices should be enabled or disabled, like key scanning,
+      trackpad interrupt.
+
+config PLATFORM_EC_TABLET_MODE
+    bool "Tablet Mode"
+    help
+      Enable this for a device which can be a tablet as well as a clamshell.
+      Tablet mode detection is done either by using the lid angle measurement
+      or by the dedicated GMR sensor.
+
+if PLATFORM_EC_TABLET_MODE
+
+config PLATFORM_EC_TABLET_MODE_SWITCH
+    bool "Tablet Mode Switch"
+    depends on PLATFORM_EC_MKBP_INPUT_DEVICES
+    help
+      Enable a virtual switch to indicate when we are in tablet mode. The tablet
+      mode state is sent to AP via MKBP protocol(switch event).
+
+config PLATFORM_EC_GMR_TABLET_MODE
+    bool "Giant Magnetoresistance(GMR) Tablet Mode"
+    help
+      Enable this to use GMR sensor to detect tablet mode.
+      It requires to set GPIO_TABLET_MODE_L to map the interrupt from
+      the sensor and direct its mapping to gmr_tablet_switch_isr
+      in common/tablet_mode.c.
+
+endif # PLATFORM_EC_TABLET_MODE
+
+config PLATFORM_EC_CONSOLE_CMD_ACCELS
+    bool "Console commands: accels, accelrate, accelinit, accelinfo, etc."
+    help
+      Enables console commands:
+
+        accelrange <sensor id> <data> <roundup> - Read or write accelerometer
+        range
+        accelres <sensor id> <data> <roundup> - Read or write accelerometer
+        resolution
+        accelrate <sensor id> <data> <roundup> - Read or write accelerometer
+        ODR
+        accelread <sensor id> [n(iteration)] - Read sensor x/y/z
+        accelinit <sensor id> - Init sensor
+
+if PLATFORM_EC_CONSOLE_CMD_ACCELS
+
+config PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO
+    bool "Console Command: accelinfo"
+    help
+      Enable console command:
+
+        accelinfo on/off [interval] - Print motion sensor info, lid angle
+        calculations and set calculation frequency.
+
+endif # PLATFORM_EC_CONSOLE_CMD_ACCELS
+
+config PLATFORM_EC_ACCEL_SPOOF_MODE
+	bool "Sensor spoof mode"
+	help
+	  Enable this to allow sensors values spoofed to any arbitrary value.
+	  This is useful for testing the motion sense framework if the hardware
+	  sensor or the sensor driver code is not ready.
+
+if PLATFORM_EC_ACCEL_SPOOF_MODE
+
+config PLATFORM_EC_CONSOLE_CMD_ACCEL_SPOOF
+	bool "Console Command: accelspoof"
+	help
+	  Enable console command:
+
+	    accelspoof id [on/off] [X] [Y] [Z] - Enable/Disable spoofing of
+	    sensor readings.
+
+endif # PLATFORM_EC_ACCEL_SPOOF_MODE
+
+config PLATFORM_EC_GESTURE_DETECTION
+	bool "Gesture detection"
+	help
+	  Enable this to support gesture detection.
+
+config PLATFORM_EC_GESTURE_HOST_DETECTION
+	bool "Gesture host detection"
+	help
+	  Enable gesture host interface
+
+rsource "Kconfig.sensor_devices"
+rsource "Kconfig.body_detection"
+
+endif # PLATFORM_EC_MOTIONSENSE
+
+config PLATFORM_EC_DEDICATED_ALS
+  bool "Enable als task without motionsense config"
+  default n
+  select HAS_TASK_ALS
+  help
+    Enable ALS task without motionsense.
+    This config must defines the als_t als[] in project layer.
+
+if PLATFORM_EC_DEDICATED_ALS
+
+rsource "Kconfig.sensor_devices"
+
+endif #PLATFORM_EC_DEDICATED_ALS
diff --git a/zephyr/Kconfig.panic b/zephyr/Kconfig.panic
new file mode 100644
index 0000000000..86f0034d08
--- /dev/null
+++ b/zephyr/Kconfig.panic
@@ -0,0 +1,48 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config PLATFORM_EC_PRESERVED_END_OF_RAM_SIZE
+	int "Size of preserved ram for panic and jump data"
+	default 1024
+	help
+	  Size of preserved non-initialized memory at end of ram for panic and
+	  jump data. The linker will ensure at least this much space is
+	  unallocated.
+
+if PLATFORM_EC_PANIC
+
+config PLATFORM_EC_SOFTWARE_PANIC
+	bool "Software panic"
+	default y
+	help
+	  Sometimes the EC has bugs that are provoked by unexpected events.
+	  This enables storing a panic log and halt the system for
+	  software-related reasons, such as stack overflow or assertion
+	  failure.
+
+config PLATFORM_EC_CONSOLE_CMD_CRASH
+	bool "Console command: crash"
+	default y
+	help
+	  For testing purposes it is useful to be able to generation exceptions
+	  to check that the panic reporting is working correctly. The enables
+	  the 'crash' command which supports generating various exceptions,
+	  selected by its parameter:
+
+	     assert              - assertion failure (ASSERT() macro)
+	     divzero             - division by zero
+	     udivzero            - division of unsigned value by zero
+	     stack (if enabled)  - stack overflow
+	     unaligned           - unaligned access (e.g. word load from 0x123)
+	     watchdog            - watchdog timer fired
+	     hang                - infinite loop in the EC code
+
+config PLATFORM_EC_DEBUG_ASSERT_BRIEF
+	bool "Enable brief panic messages"
+	default n
+	help
+	  On assertion failure, prints only the file name and the line number.
+	  Boards typically define this option in order to reduce image size.
+
+endif # PLATFORM_EC_PANIC
diff --git a/zephyr/Kconfig.pd b/zephyr/Kconfig.pd
new file mode 100644
index 0000000000..ee7b2e7ee5
--- /dev/null
+++ b/zephyr/Kconfig.pd
@@ -0,0 +1,508 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if PLATFORM_EC_USBC
+
+menuconfig PLATFORM_EC_USB_POWER_DELIVERY
+	bool "USB Type-C Power Delivery (PD)"
+	default y
+	help
+	  USB has always provided basic power to an attached peripheral. USB-C
+	  PD is part of the USB 3.0 standard and allows a lot more functionality
+	  than the basic 500mA @ 5V. It allows negotiating power delivery over
+	  the USB cable to select voltages up to 20V with current up to 5A.
+
+	  This option also enables the Type-C Port Manager (TCPM) on the EC. The
+	  TCPM deals with the various state changes in the system as devices are
+	  plugged and unplugged, as well as changes in power requirements from
+	  those devices.
+
+if PLATFORM_EC_USB_POWER_DELIVERY
+
+config PLATFORM_EC_USB_PD_HOST_CMD
+	bool "Host commands related to USB Power Delivery"
+	default y
+	help
+	  This enables host commands which allow finding out the capabilities
+	  of USB PD, checking is status and controlling how it operates. For
+	  devices which support firmware update, this is provided as well,
+	  with the firmware being sent from the AP.
+
+config PLATFORM_EC_CONSOLE_CMD_MFALLOW
+	bool "Console command: mfallow"
+	default y
+	depends on CONFIG_USB_PD_DP_MODE
+	help
+	  Controls whether multi-function support is allowed for DP (Display
+	  Port) connections. Default setting allows multi-function support when
+	  the attached device also supports multi-function mode.
+
+	    mfallow <port> [true | false]
+
+config PLATFORM_EC_CONSOLE_CMD_PD
+	bool "Console command: pd"
+	default y
+	help
+	  Provides information about the current USB Power Delivery state and
+	  also allows various changes to be made for testing purposes.
+
+	  It has a number of subcommands:
+
+	     pd dump <n>  - sets the debug level (0-3). This affects all layers
+	                    of the stack
+	     pd trysrc [0/1/2] - prints or sets the Try.SRC override. Use 0 to
+	                    force Try.SRC off, 1 to force Try.SRC on, and 2 to
+	                    let USB PD stack control the Try.SRC behavior.
+	     pd version   - show PD version in use
+	     pd <port> state  - show start for a PD port
+
+	  Ssee usb_pd_console.c for full details including various commands
+	  for role swap, reset, enable/disable, requesting SNK or SRC, etc.
+
+config PLATFORM_EC_USB_PD_DEBUG_FIXED_LEVEL
+	bool "USB Power Delivery debug level is fixed at build time"
+	help
+	  Enable this to set the debug level to a fixed value in the build.
+	  This saves space but means that the level cannot be changed using
+	  commands like 'pd dump'. Typically this should be set when a platform
+	  is shipped.
+
+config PLATFORM_EC_USB_PD_DEBUG_LEVEL
+	int "Debug level to use"
+	depends on PLATFORM_EC_USB_PD_DEBUG_FIXED_LEVEL
+	help
+	  Sets the value of the debug level to use. If this is 0 then no
+	  debugging output is available from the USB Power Delivery stack.
+	  The meaning of each level depends on the module in question, but
+	  the maximum available level is 3.
+
+config PLATFORM_EC_USB_PD_INITIAL_DEBUG_LEVEL
+	int "Initial debug level to use"
+	default 1
+	help
+	  Sets the initial value of the debug level to use, while
+	  still allowing the debug level to be changed using 'pd dump'.
+	  A value of 0 will initially disable debug logging, and values 1
+	  through to 3 will increase the level of debug logging.
+	  If this config is not set, the default level will be set to 1.
+
+config PLATFORM_EC_USB_PD_FLAGS
+	bool "Whether to build USB PD flag support"
+	default 1
+	help
+	  Enable this to support checking the USB PD configuration via flags.
+	  The usb_pd_flags modules provides functions such as
+	  get_usb_pd_vbus_detect to get the type of VBUS detection performed on
+	  this platform.
+
+if PLATFORM_EC_USB_PD_FLAGS
+
+config PLATFORM_EC_USB_PD_RUNTIME_FLAGS
+	bool "Whether to set PD flags at runtime"
+	default false
+	help
+	  Sets PD flag values at runtime instead of based on static CONFIG_*
+	  settings. The usb_pd_flags module provides functions such as
+	  set_usb_pd_vbus_detect to set how VBUS detection will be performed on
+	  this platform.
+
+endif # PLATFORM_EC_USB_PD_FLAGS
+
+config USB_PD_XID
+	int "USB XID"
+	default 0
+	help
+	  Sets the device XID reported for USB-C Authentication. Devices that
+	  have not been submitted for certification and assigned XIDs by USB-IF
+	  should use 0.
+
+config PLATFORM_EC_USB_PD_5V_EN_CUSTOM
+	bool "Custom method of detecting VBUS"
+	help
+	  Enable this if your board needs a custom method to determine if VBUS
+	  is enabled on a source port. You must provide an implementation of:
+
+	     int board_is_sourcing_vbus(int port)
+
+	  It should return 0 if not sourcing VBUS on that port and non-zero
+	  if sourcing.
+
+config PLATFORM_EC_USB_PD_5V_CHARGER_CTRL
+	bool "Ask charger if VBUS is enabled on a source port"
+	help
+	  Enable this if the charger controls VBUS on a source port.
+	  The function charger_is_sourcing_otg_power is called
+	  to determine if VBUS is enabled on the source port.
+
+config PLATFORM_EC_USBC_VCONN_SWAP
+	bool
+	help
+	  Enable VCONN swap support. This is a helper symbol and should not be
+	  manually enabled or disabled.
+
+config PLATFORM_EC_USBC_VCONN
+	bool "Support USB Type-C VCONN"
+	default y
+	select PLATFORM_EC_USBC_VCONN_SWAP
+	help
+	  This enables support for USB Type-C connector voltage (VCONN). This
+	  option must be enabled to communicate with electronically marked
+	  (E-Mark) cables. This option is required for operation with USB4 and
+	  Thunderbolt devices.
+
+	  This is not needed for captive cables.
+
+config PLATFORM_EC_USB_PD_DUAL_ROLE
+	bool "Board can act as a dual-role Power Delivery port"
+	default y
+	help
+	  This enables support for switching between source and sink during
+	  operation. This means that the port can accept power (e.g. to charge
+	  up its battery), or send out power to an attached device on the same
+	  port.
+
+menuconfig PLATFORM_EC_USB_PD_DPS
+	bool "Board can support Dynamic PDO Selection"
+	depends on PLATFORM_EC_BATTERY
+	depends on PLATFORM_EC_USB_POWER_DELIVERY
+	default n
+	select HAS_TASK_DPS
+	help
+	  Enable this to permit dynamic PDO selection (DPS). DPS can select different
+	  USB PDOs depending on system load and battery configuration to select input
+	  characteristics (particularly voltage) that allow the system to operate more
+	  efficiently.
+
+	  This should not be enabled without evaluating charger efficiency against
+	  input voltage and overriding `dps_config` as necessary to accurately reflect
+	  actual platform behavior: untuned behavior is likely to be worse than
+	  leaving DPS disabled.
+
+config PLATFORM_EC_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+	bool "Board can use TCPC-controlled DRP toggle"
+	depends on PLATFORM_EC_USB_PD_DUAL_ROLE
+	default y
+	help
+	  Enable this if the USB Type-C Port Controllers (TCPC) used on the
+	  board supports toggling of the power role autonomously. When this is
+	  disabled, the USB power delivery task is responsible for manually
+	  toggling the power role.
+
+config PLATFORM_EC_USB_PD_REV30
+	bool "USB PD Rev3.0 functionality"
+	default y
+	help
+	  Enable this to allow Rev3.0 functionality, including features such as
+	  Fast Role Swap, advertising the available power across all ports of a
+	  multi-port charger, and USB4. If disabled, only USB Power Delivery
+	  Rev2.0 functionality is supported.
+
+	  This defaults to y because PD Rev3.0 is required for USB4
+	  functionality.
+
+config PLATFORM_EC_USB_PD_EXTENDED_MESSAGES
+	bool "USB 3.0 Extended Message Support"
+	default y
+	depends on PLATFORM_EC_USB_PD_REV30
+	help
+	  Support USB PD 3.0 Extended Messages. Note that Chromebooks disabling
+	  this config item are non-compliant with PD 3.0, because they have
+	  batteries but do not support Get_Battery_Cap or Get_Battery_Status.
+
+config PLATFORM_EC_USB_PD_ALT_MODE
+	bool "USB Power Delivery alternate mode"
+	default y
+	help
+	  Enable this to support USB PD alternate mode. This allows negotiation
+	  of a different mode of operation to allow non-USB traffic to pass over
+	  a USB Type-C link. This makes use of some or all of the USB 3.0 bus
+	  differential pairs. If all are used for the alternate mode, then USB
+	  transmission is not available at all while in this mode.
+
+config PLATFORM_EC_USB_PD_REQUIRE_AP_MODE_ENTRY
+	bool "USB Power delivery requires AP to enter alternate modes"
+	depends on PLATFORM_EC_USB_PD_ALT_MODE
+	help
+	  Do not enter USB PD alternate modes or USB4 automatically, Wait for
+	  the AP to direct the EC to enter a mode. This requires AP software
+	  support.
+
+config PLATFORM_EC_USB_PD_VDM_AP_CONTROL
+	bool "USB Power Delivery VDMs may be sent by the AP"
+	depends on PLATFORM_EC_USB_MUX_AP_CONTROL
+	select PLATFORM_EC_USB_PD_REQUIRE_AP_MODE_ENTRY
+	help
+	  Allow the AP an interface to send any VDM REQ message it would like
+	  to.  This allows the AP to fully drive the alternate mode entry
+	  process, and requires that the AP also be able to control the USB
+	  muxes in order to sequence that mode entry.
+
+config PLATFORM_EC_USB_PD_ALT_MODE_DFP
+	bool "Downward Facing Port support"
+	default y
+	depends on PLATFORM_EC_USB_PD_DISCOVERY
+	help
+	  Enable support for USB Power Delivery alternate mode of Downward
+	  Facing Port.
+
+	  TODO: Add more help here
+
+config PLATFORM_EC_USB_PD_ALT_MODE_UFP
+	bool "Upward Facing Port support"
+	help
+	  Enable support for USB Power Delivery alternate mode of Upward
+	  Facing Port (UFP).
+
+	  By default, Chromium OS only enables alternate modes (Display Port,
+	  USB4, Thuderbolt, etc) when the USB data role resolves to the
+	  Downstream Facing Port (DFP) role. Enable this option to support
+	  USB4 and ThunderBolt operation when the Chromium OS data role
+	  resolves to the UFP role.
+
+config PLATFORM_EC_USB_PD_DISCOVERY
+	bool "Enable EC to direct Discover VDMs"
+	default y
+	help
+	  This enables support for the EC probing and storing the various
+	  partner discovery messages (DiscoverIdentity, DiscoverModes,
+	  DiscoverSVIDs).
+
+config PLATFORM_EC_USB_PD_USB32_DRD
+	bool "Port is capable of operating as a USB3.2 device"
+	default n
+	help
+	  Enable this if the board's USB Power Delivery Downward Facing Port is
+	  capable of operating as both a USB Host (DFP, assumed by default) and a USB
+	  Device (UFP): it is a Dual-Role Data (DRD) device.
+
+	  This is advertised to port partners so they can potentially take advantage
+	  of the additional features available.
+
+config PLATFORM_EC_USB_PD_DP_HPD_GPIO
+	bool "Hotplug Detect (HPD) is controlled by an EC GPIO"
+	help
+	  Enable this if the EC must send the Hotplug Detect (HPD) signal to
+	  the DisplayPort Graphics Processing Unit (GPU) via a GPIO. Otherwise
+	  this is sent by the display device.
+
+config PLATFORM_EC_USB_PD_DP_HPD_GPIO_CUSTOM
+	bool "Custom handling of HPD GPIO"
+	depends on PLATFORM_EC_USB_PD_DP_HPD_GPIO
+	help
+	  Enable this if the Hotplug Detect (HPD) GPIO level has to be handled
+	  by custom functions. In this case your board must implement a
+	  function to enable the feature for a port and another function to
+	  check the current state:
+
+	    void svdm_set_hpd_gpio(int port, int enable);
+
+	    int svdm_get_hpd_gpio(int port);
+
+config PLATFORM_EC_USB_PD_DATA_RESET_MSG
+	bool "Enable the PD Data Reset Message."
+	depends on PLATFORM_EC_USB_PD_REV30
+	help
+	  Enable this to support the Data Reset PD message flows. This is
+	  mandatory for products supporting USB4 but optional for other PD 3.0
+	  products.
+
+config PLATFORM_EC_USB_TYPEC_SM
+	bool "Type-C (TC) physical-layer state machine"
+	default y
+	help
+	  This enables the bottom layer of the TCPMv2 state machine which
+	  handles using CC lines to set the voltage-level of the power supplied.
+	  You should normally define this unless you want to override it in your
+	  board code, which is not recommended.
+
+config PLATFORM_EC_USB_PRL_SM
+	bool "Protocol layer (PRL) state machine"
+	default y
+	help
+	  This enables the middle layer of the power-delivery (PD) protocol,
+	  which deals with the flow of power messages across the USB Type-C
+	  interface. You should normally define this unless you want to override
+	  it in your board code, which is not recommended.
+
+config PLATFORM_EC_USB_PE_SM
+	bool "Policy engine (PE) state machine"
+	default y
+	help
+	  This enables the top layer of the power-delivery (PD) protocol, which
+	  deals with the actually PD messages that are exchanged with attached
+	  USB devices. You should normally define this unless you want to
+	  override it in your board code, which is not recommended.
+
+config PLATFORM_EC_USB_DPM_SM
+	bool "Device Policy Manager (DPM) state machine"
+	default y
+	help
+	  This enables the device policy manager portion of the power-delivery
+	  (PD), protocol which is used to define port policy decision.  You
+	  should normally define this unless you want to override it in your
+	  board code, which is not recommended.
+
+config PLATFORM_EC_USB_PD_DECODE_SOP
+	def_bool y  # Required for TCPMV2
+	help
+	  This enables support for encoding of the message's Start Of Packet
+	  (SOP, SOP' and SOP'', collectively called SOP*) in bits 31-28 of the
+	  32-bit msg header type.
+
+config PLATFORM_EC_HOSTCMD_PD_CONTROL
+	bool "Host command: EC_CMD_PD_CONTROL"
+	default y
+	help
+	  Enable the EC_CMD_PD_CONTROL host command. This allows control
+	  of the USB-PD chip from the AP, including reset, suspend/resume
+	  and enabling power.
+
+	  This host command can be manually executed using the
+	  "ectool pdcontrol" command from the Chromium OS shell.
+
+config PLATFORM_EC_USB_PD_LOGGING
+	bool "Host command: EC_CMD_PD_GET_LOG_ENTRY"
+	help
+	  Enable logging of USB Power Delivery events. The AP can request the
+	  log to see what has happened recently.
+
+	  The log events are stored in a circular buffer, each one being a
+	  struct event_log_entry.
+
+config PLATFORM_EC_USB_PD_PRL_EVENT_LOG
+	bool "Log PRL state changes to a ring buffer"
+	help
+	  Logs every PRL layer state change to a ring buffer, allowing those
+	  events to be inspected at a later time with the `prllog` console
+	  command.
+
+	  Logging to a ring buffer instead of increasing the overall PD log
+	  verbosity has a much smaller effect on overall performance than
+	  synchronous prints, making it easier to debug timing-sensitive
+	  behavior.
+
+config PLATFORM_EC_USB_PD_PRL_EVENT_LOG_CAPACITY
+	int "PRL state log buffer capacity"
+	depends on PLATFORM_EC_USB_PD_PRL_EVENT_LOG
+	default 128
+	help
+	  Sets the number of entries stored in the PRL event log. Larger values
+	  store a longer history but require more RAM. When the buffer is
+	  filled, the oldest entries are replaced with new ones as they are
+	  logged.
+
+config PLATFORM_EC_USB_PD_TRY_SRC
+	bool "Enable Try.SRC mode"
+	depends on PLATFORM_EC_USB_DRP_ACC_TRYSRC
+	default y
+	help
+	  This enables Try.SRC mode so that the board will try to be a source
+	  for power if the other end offers both options. This can be useful
+	  for laptops, for example, since when attaching to a cellphone we want
+	  the laptop to charge the phone, not vice versa.
+
+config PLATFORM_EC_USB_PD_DP_MODE
+	bool "EC-driven DP support"
+	depends on !PLATFORM_EC_USB_PD_VDM_AP_CONTROL
+	default y
+	help
+	  This enables support for entering DisplayPort alternate mode as a
+	  DFP from the Embedded Controller directly.  This flag gates all the
+	  on-EC logic for determining specifics such as VDM contents.
+
+config PLATFORM_EC_USB_PD_USB4
+	bool "USB4 support"
+	depends on PLATFORM_EC_USB_PD_REV30
+	default n
+	help
+	  This enables support for entering into USB4 mode between two port
+	  partners. The provides new features such as higher speeds and more
+	  flexible multiplexing of data on the cable for different purposes,
+	  e.g. attaching multiple displays and storage devices on the same bus.
+
+config PLATFORM_EC_USB_PD_TBT_COMPAT_MODE
+	bool "Thunderbolt-compatible mode support"
+	depends on PLATFORM_EC_USB_PD_REV30
+	default n
+	help
+	  Enable this to allow entering into Thunderbolt-compatible mode between
+	  two port partners. This does not require that USB4 mode be enabled.
+
+config PLATFORM_EC_USB_PD_STARTUP_DELAY_MS
+	int "PD thread startup delay time in milliseconds"
+	default 0
+	help
+	  Have the USB-PD thread(s) delay this many milliseconds after startup
+	  before beginning regular processing. This can be helpful if external
+	  processes need to happen shortly after reset and PD initialization may
+	  interfere with them.
+
+	  For instance, if the EC enters programming mode when it receives a special
+	  signal but requires USB-PD power in order to remain alive, PD
+	  initialization can cause the system to reset and interrupt programming.
+	  Adding a delay to startup can provide a wider window to enter programming
+	  mode and help prevent such issues.
+
+config PLATFORM_EC_CONFIG_USB_PD_3A_PORTS
+	int "Number of USBC ports that can supply 3A"
+	default 1
+	help
+	 Ensure that CONFIG_USB_PD_TCPMV2 is not being used with charge_manager source
+	 defines, and define a default number of 3.0 A ports if not selected. Note
+	 that the functionality of this default of 1 is equivalent to both previous
+	 defines, which only ever allocated one 3.0 A port.
+
+	 To turn off the TCPMv2 3.0 A current allocation from the DPM, set
+	 CONFIG_USB_PD_3A_PORTS to 0.
+
+config PLATFORM_EC_USB_PD_TEMP_SENSOR
+	int "Temperature sensor used in PD messages"
+	depends on PLATFORM_EC_TEMP_SENSOR
+	default 0
+	help
+	 Temperature related fields in USB PD messages assume a device only has
+	 one temperature. But, Chromebooks can have multiple temperature sensors.
+	 This option selects which temperature sensor is used for USB PD.
+
+config PLATFORM_EC_USB_PD_SHORT_PRESS_MAX_MS
+	int "Time limit in ms for short presses with a USB PD power button"
+	default 4000
+	help
+	 USB PD supports power buttons over USB-C using button press and button
+	 release alerts. How a chromeOS device responds depends on whether the button
+	 press is considered short or long. This config is used to set the short press
+	 time limit in ms. Any press shorter will be a short press and any press
+	 longer will either be a long press or invalid.
+
+config PLATFORM_EC_USB_PD_LONG_PRESS_MAX_MS
+	int "Time limit in ms for valid presses with a USB PD power button"
+	default 8000
+	help
+	 USB PD supports power buttons over USB-C using button press and button
+	 release alerts. If a USB PD partner sends a press but never a release alert,
+	 the EC should time out while waiting for the release and return to an idle
+	 state. This value sets how long the EC waits for a release alert from the
+	 partner in ms. Any press longer than this will not be considered a valid USB
+	 PD button press.
+
+config PLATFORM_EC_USB_PD_EPR
+	bool "USB PD Extended Power Range support"
+	depends on PLATFORM_EC_USB_PD_REV30
+	default n
+	help
+	  This enables support for EPR (Extended Power Range).
+
+rsource "Kconfig.svdm_rsp"
+
+endif  # PLATFORM_EC_USB_POWER_DELIVERY
+
+endif # PLATFORM_EC_USBC
+
+config PLATFORM_EC_STANDALONE_PD_CHIP
+	bool "The project uses the standalone PD chip"
+	default n
+	select HAS_TASK_CYPD
+	help
+	  Enable if project use the standalone PD chip instead of the structure of
+	  TCPC + TCPM.
diff --git a/zephyr/Kconfig.pd_console_cmd b/zephyr/Kconfig.pd_console_cmd
new file mode 100644
index 0000000000..bba130718f
--- /dev/null
+++ b/zephyr/Kconfig.pd_console_cmd
@@ -0,0 +1,59 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if PLATFORM_EC_USBC
+if PLATFORM_EC_USB_POWER_DELIVERY
+
+menuconfig PLATFORM_EC_USB_PD_CONSOLE_CMD
+	bool "Enable USB PD console commands"
+	default y if PLATFORM_EC_USB_PD_ALT_MODE_DFP
+	help
+	  Enables various USB-C PD related console commands.
+
+if PLATFORM_EC_USB_PD_CONSOLE_CMD
+
+config PLATFORM_EC_CONSOLE_CMD_USB_PD_PE
+	bool "Console command: pe"
+	default y
+	help
+	  This command dumps information about the USB PD alternate mode options
+	  discovered from the partner device. It can be useful for debugging.
+
+	  Example: pe 1 dump
+	     IDENT SOP:
+
+	             [ID Header] 2c000bda :: AMA, VID:0bda
+	             [Cert Stat] 00000000
+	             [2] 00000209    [3] 11000f09
+	     IDENT SOP':
+	             [ID Header] 1c000489 :: PCable, VID:0489
+	             [Cert Stat] 000001c6
+	             [2] f6810000    [3] 11082051
+	     SVID[0]: ff01 MODES: [1] 000c0045
+	     MODE[1]: svid:ff01 caps:000c0045
+
+config PLATFORM_EC_CONSOLE_CMD_USB_PD_CABLE
+	bool "Console command: pdcable"
+	default y
+	help
+	  This commands shows the USB cable charactistics as detected from the
+	  device. It can be useful for debugging problems with cables and the
+	  device's response to them.
+
+	  Example: pdcable 1
+	     Cable Type: Passive
+	     Cable Rev: 1.0
+	     Connector Type: 2
+	     Cable Current: 5A
+	     USB Superspeed Signaling support: 1
+	     Rounded support: No
+	     Optical cable: No
+	     Retimer support: No
+	     Link training: Bi-directional
+	     Thunderbolt cable type: Passive
+
+endif  # PLATFORM_EC_USB_PD_CONSOLE_CMD
+
+endif # PLATFORM_EC_USB_POWER_DELIVERY
+endif # PLATFORM_EC_USBC
diff --git a/zephyr/Kconfig.pd_discharge b/zephyr/Kconfig.pd_discharge
new file mode 100644
index 0000000000..6d2bd58b82
--- /dev/null
+++ b/zephyr/Kconfig.pd_discharge
@@ -0,0 +1,42 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if PLATFORM_EC_USBC
+if PLATFORM_EC_USB_POWER_DELIVERY
+
+config PLATFORM_EC_USB_PD_DISCHARGE
+	bool "Board can discharge VBUS"
+	default y
+	help
+	  Enable this if the board can enable VBUS discharge (eg. through a
+	  GPIO-controlled discharge circuit, or through port controller
+	  registers) to discharge VBUS rapidly on disconnect
+
+choice PLATFORM_EC_USB_PD_DISCHARGE_MODE
+	prompt "Select the discharge method"
+	depends on PLATFORM_EC_USB_PD_DISCHARGE
+
+config PLATFORM_EC_USB_PD_DISCHARGE_GPIO
+	bool "GPIO control"
+	help
+	  Enable this if the discharge circuit is controlled by a GPIO
+
+	  TODO: How to specify the GPIO?
+
+config PLATFORM_EC_USB_PD_DISCHARGE_TCPC
+	bool "Discharge circuit is provided by the TCPC"
+	help
+	  Enable this if the discharge circuit is provided by Power-Delivery
+	  resistors on the USB Type-C Port Controller (TCPC).
+
+config PLATFORM_EC_USB_PD_DISCHARGE_PPC
+	bool "Discharge circuit is provided by the PPC"
+	help
+	  Enable this if the discharge circuit is using Power Delivery
+	  resistors on the Power Path Controller.
+
+endchoice # PLATFORM_EC_USB_PD_DISCHARGE_MODE
+
+endif # PLATFORM_EC_USB_POWER_DELIVERY
+endif # PLATFORM_EC_USBC
diff --git a/zephyr/Kconfig.pd_frs b/zephyr/Kconfig.pd_frs
new file mode 100644
index 0000000000..5faf16b05c
--- /dev/null
+++ b/zephyr/Kconfig.pd_frs
@@ -0,0 +1,50 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if PLATFORM_EC_USBC
+if PLATFORM_EC_USB_POWER_DELIVERY
+
+config PLATFORM_EC_USB_PD_FRS
+	bool "Support Fast Role Swap protocol"
+	help
+	  Enables the protocol side of Fast Role Swap (FRS). This allows the
+	  device to switch from a SNK to a SRC (or vice versa) based on
+	  communication with the partner device.
+
+	  For this to work the trigger must be implemented in either the
+	  Type-C Port Controller (TCPC) or Power Path Controller (PPC).
+
+	  FRS differs from the traditional power-role swap in that FRS
+	  guarantees there is no interruption of power nor disruption of data
+	  communication to any downstream devices (such as devices connected
+	  to a USB-C hub or dock).
+
+if PLATFORM_EC_USB_PD_FRS
+
+choice PLATFORM_EC_USB_PD_FRS_MODE
+	prompt "Select where the trigger is implemented"
+	help
+	  The Fast Role Swap (protocol requires that a trigger be implemented to
+	  initiate the swap. Use this option to select which of the available
+	  options should be used.
+
+config PLATFORM_EC_USB_PD_FRS_PPC
+	bool "PPC"
+	depends on PLATFORM_EC_USBC_PPC
+	help
+	  Enable this if the Fast Role Swap trigger is implemented in the
+	  Power Path Controller (PPC).
+
+config PLATFORM_EC_USB_PD_FRS_TCPC
+	bool "TCPC"
+	help
+	  Enable this if the Fast Role Swap trigger is implemented in the
+	  Type-C Port Controller (TCPC).
+
+endchoice # PLATFORM_EC_USB_PD_FRS_MODE
+
+endif # PLATFORM_EC_USB_PD_FRS
+
+endif # PLATFORM_EC_USB_POWER_DELIVERY
+endif # PLATFORM_EC_USBC
diff --git a/zephyr/Kconfig.pd_int_shared b/zephyr/Kconfig.pd_int_shared
new file mode 100644
index 0000000000..8385496b62
--- /dev/null
+++ b/zephyr/Kconfig.pd_int_shared
@@ -0,0 +1,45 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if PLATFORM_EC_USBC
+if PLATFORM_EC_USB_POWER_DELIVERY
+
+menuconfig PLATFORM_EC_USB_PD_INT_SHARED
+	bool "USB-C ports share PD interrupts"
+	select HAS_TASK_PD_INT_SHARED
+	help
+	  This enables processing of shared interrupts where multiple ports
+	  share a single IRQ on the EC. Only one shared IRQ is supported,
+	  but any combination of ports can be serviced by that one IRQ.
+
+if PLATFORM_EC_USB_PD_INT_SHARED
+
+config PLATFORM_EC_USB_PD_PORT_0_SHARED
+	bool "Port 0 IRQ is shared"
+	help
+	  Enable handling of port 0 PD interrupts signalled by an IRQ that is
+	  shared by every other port enabled in this section.
+
+config PLATFORM_EC_USB_PD_PORT_1_SHARED
+	bool "Port 1 IRQ is shared"
+	help
+	  Enable handling of port 1 PD interrupts signalled by an IRQ that is
+	  shared by every other port enabled in this section.
+
+config PLATFORM_EC_USB_PD_PORT_2_SHARED
+	bool "Port 2 IRQ is shared"
+	help
+	  Enable handling of port 2 PD interrupts signalled by an IRQ that is
+	  shared by every other port enabled in this section.
+
+config PLATFORM_EC_USB_PD_PORT_3_SHARED
+	bool "Port 3 IRQ is shared"
+	help
+	  Enable handling of port 3 PD interrupts signalled by an IRQ that is
+	  shared by every other port enabled in this section.
+
+endif # PLATFORM_EC_USB_PD_INT_SHARED
+
+endif # PLATFORM_EC_USB_POWER_DELIVERY
+endif # PLATFORM_EC_USBC
diff --git a/zephyr/Kconfig.pd_meas_vbus b/zephyr/Kconfig.pd_meas_vbus
new file mode 100644
index 0000000000..bf85609a9b
--- /dev/null
+++ b/zephyr/Kconfig.pd_meas_vbus
@@ -0,0 +1,52 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+choice PLATFORM_EC_USB_PD_VBUS_MEASURE_MODE
+	prompt "Select how VBUS voltage is measured"
+	optional
+
+config PLATFORM_EC_USB_PD_VBUS_MEASURE_NOT_PRESENT
+	bool "VBUS voltage cannot be read"
+	help
+	  Enable this if the board does not provide any mechanism for the EC to
+	  read the analog VBUS voltage.
+
+config PLATFORM_EC_USB_PD_VBUS_MEASURE_CHARGER
+	bool "On-board charger supports VBUS measurement"
+	help
+	  Enable this if the VBUS voltage can be read using a charger on the
+	  board.
+
+if PLATFORM_EC_USBC
+if PLATFORM_EC_USB_POWER_DELIVERY
+
+config PLATFORM_EC_USB_PD_VBUS_MEASURE_TCPC
+	bool "Type-C Port Controller supports VBUS measurement"
+	help
+	  Enable this if the VBUS voltage can be read using the on-board
+	  TCPC.
+
+config PLATFORM_EC_USB_PD_VBUS_MEASURE_ADC_EACH_PORT
+	bool "VBUS on each port is measured using an ADC channel"
+	help
+	  Enable this if there is a separate ADC channel for each USB-C VBUS
+	  voltage.
+
+endif # PLATFORM_EC_USB_POWER_DELIVERY
+endif # PLATFORM_EC_USBC
+
+config PLATFORM_EC_USB_PD_VBUS_MEASURE_BY_BOARD
+	bool "VBUS on each port is measured per board specific"
+	help
+	  Enable this if there are different VBUS measurement approaches on
+	  the board, and also `board_get_vbus_voltage()` has to be implemented.
+
+endchoice # PLATFORM_EC_USB_PD_VBUS_MEASURE_MODE
+
+config PLATFORM_EC_CMD_VBUS
+	bool "Console command to print VBUS"
+	help
+	  Support console command vbus to print the VBUS on each port
+	  respectively.
+
diff --git a/zephyr/Kconfig.pd_usbc_device_type b/zephyr/Kconfig.pd_usbc_device_type
new file mode 100644
index 0000000000..62797128cd
--- /dev/null
+++ b/zephyr/Kconfig.pd_usbc_device_type
@@ -0,0 +1,39 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if PLATFORM_EC_USBC
+if PLATFORM_EC_USB_POWER_DELIVERY
+
+choice PLATFORM_EC_USB_DEVICE_TYPE
+	prompt "Select the USB-C device type"
+	default PLATFORM_EC_USB_DRP_ACC_TRYSRC
+
+config PLATFORM_EC_USB_VPD
+	bool "VCONN-Powered Device"
+	help
+	  This enables support for supplying power to devices that accept power
+	  over the USB VCONN line.
+
+	  See here for details:
+
+	  https://www.usb.org/sites/default/files/D1T2-3a%20-%20CTVPDs%20and%20Making%20Your%20Own%20USB-C%20Thingamajig.pdf
+
+config PLATFORM_EC_USB_CTVPD
+	bool "Charge-Through VCONN-Powered Device"
+	help
+	  This enables support for supplying power to devices, with a circuit
+	  that deals with this without needing the involvement of the main
+	  device.
+
+config PLATFORM_EC_USB_DRP_ACC_TRYSRC
+	bool "Dual-Role Port, Audio Accessory, and Try.SRC Device"
+	help
+	  This is the most flexible option, allowing the port to operate in
+	  a dual-role capacity, so that power can be accepted or supplied on
+	  a port.
+
+endchoice # PLATFORM_EC_USB_DEVICE_TYPE
+
+endif # PLATFORM_EC_USB_POWER_DELIVERY
+endif # PLATFORM_EC_USBC
diff --git a/zephyr/Kconfig.pd_vbus_detection b/zephyr/Kconfig.pd_vbus_detection
new file mode 100644
index 0000000000..8e25d973eb
--- /dev/null
+++ b/zephyr/Kconfig.pd_vbus_detection
@@ -0,0 +1,32 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if PLATFORM_EC_USBC
+if PLATFORM_EC_USB_POWER_DELIVERY
+
+config PLATFORM_EC_USB_PD_VBUS_DETECT_NONE
+	bool "No way to detect VBUS"
+	help
+	  Choose this option if it is not possible to detect VBUS. This causes
+	  the `check_vbus_level` function pointer in the driver struct to be NULL.
+
+config PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC
+	bool "TCPC detects VBUS"
+	help
+	  Choose this option if the TCPC can detect the presence of VBUS
+
+config PLATFORM_EC_USB_PD_VBUS_DETECT_CHARGER
+	bool "Charger detects VBUS"
+	help
+	  Choose this option if the battery charger can detect the presence
+	  of VBUS
+
+config PLATFORM_EC_USB_PD_VBUS_DETECT_PPC
+	bool "PPC detects VBUS"
+	help
+	  Choose this option if the Power-Path Controller (PPC) can detect the
+	  presence of VBUS
+
+endif # PLATFORM_EC_USB_POWER_DELIVERY
+endif # PLATFORM_EC_USBC
diff --git a/zephyr/Kconfig.pmic b/zephyr/Kconfig.pmic
new file mode 100644
index 0000000000..ef1df085c8
--- /dev/null
+++ b/zephyr/Kconfig.pmic
@@ -0,0 +1,27 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+menuconfig PLATFORM_EC_PMIC
+	bool "Power Management IC support"
+	help
+	  Enables support for controlling PMICs (Power Management ICs).
+	  A system may have one or more PMICs to control various power
+	  rails. These devices operate autonomously, but can sometimes
+	  be accessed to tune operational parameters or read fault
+	  codes.
+
+if PLATFORM_EC_PMIC
+
+config PLATFORM_EC_MP2964
+	bool "Enable MP2964 PMIC support"
+	default y
+	depends on DT_HAS_MPS_MP2964_ENABLED
+	help
+	  Enables support for the MPS MP2964 PMIC (Power Management IC).
+	  This is a dual rail IMVP8 - IMVP9.1 compatible Digital
+	  Multi-Phase Controller with an I2C interface.  This driver
+	  enables reprogramming configuration registers when initial the
+	  factory settings need to be tuned in prototype devices.
+
+endif # PLATFORM_EC_PMIC
diff --git a/zephyr/Kconfig.port80 b/zephyr/Kconfig.port80
new file mode 100644
index 0000000000..8addf4f46e
--- /dev/null
+++ b/zephyr/Kconfig.port80
@@ -0,0 +1,28 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if PLATFORM_EC_HOST_INTERFACE_ESPI
+
+config PLATFORM_EC_PORT80_4_BYTE
+	bool "Allow accept 4-byte Port80 codes"
+	help
+	  Enable this config to allow the common Port80 layer to accept 4-byte
+	  codes when AP sends 4-byte Port80 codes via eSPI PUT_IOWR_SHORT
+	  protocol in a single transaction.
+
+config PLATFORM_EC_PORT80_QUIET
+	bool "Do not log Port80 codes when they are received"
+	help
+	  Enable this config to avoid logging the entire buffer of
+	  Port80 codes as each are received.
+	  The history is still available via the 'port80' EC command.
+	  Enabling this will reduce the logging overhead during AP startup.
+
+config PLATFORM_EC_PORT80_CUSTOM_FORMAT
+	bool "Print Port80 code for customized format"
+	help
+	  Enable this config to print the port80 code for customized
+	  format.
+
+endif # PLATFORM_EC_HOST_INTERFACE_ESPI
diff --git a/zephyr/Kconfig.powerseq b/zephyr/Kconfig.powerseq
new file mode 100644
index 0000000000..716a08b323
--- /dev/null
+++ b/zephyr/Kconfig.powerseq
@@ -0,0 +1,282 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+menuconfig PLATFORM_EC_POWERSEQ
+	bool "Power sequencing"
+	depends on AP
+	depends on !AP_PWRSEQ
+	select HAS_TASK_CHIPSET
+	help
+	  Enable shimming the platform/ec AP power sequencing code. This
+	  handles powering the chipset on and off.
+
+	  Enabling this automatically enables HAS_TASK_CHIPSET since power
+	  sequencing must run in its own task.
+
+if PLATFORM_EC_POWERSEQ
+
+config PLATFORM_EC_POWERSEQ_S0IX
+	bool "Enable S0ix sleep states"
+	select PLATFORM_EC_POWERSEQ_HOST_SLEEP
+	help
+	  Enable the CONFIG_POWER_S0IX platform/ec configuration
+	  option, Intel's low-power idle sleep state, also known as
+	  "modern sleep".
+
+config PLATFORM_EC_POWERSEQ_CPU_PROCHOT_ACTIVE_LOW
+	bool "The CPU_PROCHOT signal is an active low signal"
+	default y
+	help
+	  If CPU_PROCHOT should be treated as active-low, enable this
+	  configuration option.
+
+config PLATFORM_EC_POWERSEQ_HOST_SLEEP
+	bool "Track host sleep states"
+	help
+	  Enable EC code to track the AP sleep states.  This is
+	  required for S0ix support on Intel platforms, and optional
+	  for boards without S0ix support.
+
+config PLATFORM_EC_POWER_SLEEP_FAILURE_DETECTION
+	bool "Detect failure to enter a sleep state (S0ix/S3)"
+	depends on PLATFORM_EC_POWERSEQ_HOST_SLEEP
+	help
+	  Enables detection of the AP failing to go to sleep, perhaps due to a
+	  bug in the internal SoC periodic housekeeping code.
+
+	  Failure information is reported via the EC_CMD_HOST_SLEEP_EVENT host
+	  command.
+
+config PLATFORM_EC_POWERSEQ_S0IX_COUNTER
+	bool "Enable S0ix counter"
+	depends on PLATFORM_EC_POWERSEQ_S0IX
+	depends on PLATFORM_EC_POWERSEQ_HOST_SLEEP
+	default y
+	help
+	  Enables counter which increases at every transitions to S0ix state.
+	  Counter can be read via host command.
+
+config PLATFORM_EC_HOSTCMD_AP_RESET
+	bool "Host command: EC_CMD_AP_RESET"
+	depends on PLATFORM_EC_HOSTCMD
+	help
+	  Enable support for EC_CMD_AP_RESET, used by the AP to request that
+	  the EC perform a reset of the AP.
+
+	  Warning: This command skips the normal reset mechanism on the AP and
+	  may leave data unsaved.
+
+config PLATFORM_EC_POWERSEQ_PP5000_CONTROL
+	bool "Enable a task-safe way to control the PP5000 rail"
+	depends on !AP_X86_AMD
+	default y
+	help
+	  Guard access to the PP5000 GPIO using mutex locks, allowing
+	  the rail to be changed in a task-safe manner.
+
+config PLATFORM_EC_POWERSEQ_RSMRST_DELAY
+	bool "Wait at least 10ms before deasserting RSMRST to PCH"
+	default y if AP_X86_INTEL_TGL
+	depends on AP_X86_AMD || AP_X86_INTEL
+	help
+	  Wait at least 10ms between power signals going high and
+	  deasserting RSMRST to PCH.
+
+config PLATFORM_EC_POWERSEQ_FAKE_CONTROL
+	bool "Console command: powerfake"
+	depends on PLATFORM_EC_SYSTEM_UNLOCKED
+	help
+	  Enable fake control of the power sequencing on the platform.  This
+	  will require some SoC-specific implementation and allows a fake boot
+	  without an SoC present.  This command should not be used on platforms
+	  with an SoC present.
+
+menuconfig PLATFORM_EC_POWERSEQ_CUSTOMER
+	bool "AMD power sequencing"
+	depends on AP_X86_AMD || AP_X86_INTEL
+	select HAS_TASK_POWERBTN_CUSTOMER
+	default n
+	help
+	  Enable customer power sequencing code.
+	  Must create the power_sequence.c in board layer.
+
+menuconfig PLATFORM_EC_POWERSEQ_AMD
+	bool "AMD power sequencing"
+	depends on AP_X86_AMD
+	select HAS_TASK_POWERBTN
+	default y
+	help
+	  Enable AMD power sequencing code.
+
+if PLATFORM_EC_POWERSEQ_AMD
+
+config PLATFORM_EC_POWER_BUTTON_TO_PCH_CUSTOM
+	bool "Custom board_pwrbtn_to_pch"
+	help
+	  The board support code provides a custom function,
+	  board_pwrbtn_to_pch, that replaces the standard GPIO set
+	  level to the SoC.
+
+endif  # PLATFORM_EC_POWERSEQ_AMD
+
+menuconfig PLATFORM_EC_POWERSEQ_INTEL
+	bool "Enable shimming common Intel power sequencing code"
+	depends on AP_X86_INTEL
+	select HAS_TASK_POWERBTN
+	default y
+	help
+	  Enable shimming platform/ec AP power sequencing code for
+	  Intel.
+
+if PLATFORM_EC_POWERSEQ_INTEL
+
+config PLATFORM_EC_POWERSEQ_CPU_PROCHOT_GATE_ON_C10
+	bool "Gate PROCHOT detection based on the AP C10 state"
+	default y if PLATFORM_EC_POWERSEQ_CPU_PROCHOT_ACTIVE_LOW
+	help
+	  When the AP enters C10, the power rails VCCIO, VCCSTG, and VCCPLL_OC
+	  may be turned off by the board.  If the PROCHOT# signal is pulled up
+	  by any of these rails, PROCHOT is not valid while the AP is in C10,
+	  Enable this option to gate PROCHOT detection when C10 is active.
+
+config PLATFORM_EC_POWERSEQ_RTC_RESET
+	bool "Board has an RTC reset"
+	help
+	  This project has a gpio named GPIO_PCH_RTCRST defined in
+	  the GPIO configuration, which can be used to reset the AP's RTC when
+	  set high.
+
+config PLATFORM_EC_POWERSEQ_S4
+	bool "Advertise S4 residency"
+	depends on PLATFORM_HOST_INTERFACE_EC_HOST_INTERFACE_ESPI_VW_SLP_S5
+	default y if AP_X86_INTEL_TGL
+	default y if AP_X86_INTEL_ADL
+	default y if AP_X86_INTEL_MTL
+	help
+	  Advertise S4 residency capabilities to the AP. This is required for
+	  AP hibernate (suspend-to-disk) on Intel platforms with Key Locker
+	  support (TGL+)
+
+config PLATFORM_EC_POWERSEQ_COMETLAKE
+	bool "Use common Comet Lake code for power sequencing"
+	depends on AP_X86_INTEL_CML
+	default y
+	help
+	  Use the Comet Lake code for power sequencing.
+
+config CHIPSET_ALDERLAKE_SLG4BD44540
+       bool "Use powersequencing with Silego"
+       depends on AP_X86_INTEL_ADL
+       default y
+       help
+          Use this for AlderLake power sequencing with the
+          Silego chips.
+
+config PLATFORM_EC_POWERSEQ_METEORLAKE
+	bool "Use common Meteorlake code for power sequencing"
+	depends on AP_X86_INTEL_MTL
+	default n
+	help
+	  Use the Meteorlake common code for power sequencing. Note that
+	  this applies to Meteorlake and potentially future SoCs.
+
+menuconfig PLATFORM_EC_POWERSEQ_ICELAKE
+	bool "Use common Icelake code for power sequencing"
+	depends on AP_X86_INTEL_TGL
+	default n
+	help
+	  Use the Icelake common code for power sequencing.  Note that
+	  this applies to more platforms than just Icelake.  For
+	  example, Tigerlake uses this code too.
+
+if PLATFORM_EC_POWERSEQ_ICELAKE
+
+config PLATFORM_EC_POWERSEQ_SLP_S3_L_OVERRIDE
+	bool "Enable a quirk to release SLP_S3_L after DSW_PWROK is high"
+	default y if AP_X86_INTEL_TGL
+	help
+	  Enable a quirk to reconfigure SLP_S3_L back to an input a
+	  short delay after DSW_PWROK goes high.
+
+config PLATFORM_EC_POWERSEQ_PP3300_RAIL_FIRST
+	bool "Turn on the PP3300 rail before PP5000"
+	default y if AP_X86_INTEL_TGL
+	help
+	  When switching from G3 to S5, turn on the PP3300 rail before
+	  the PP5500 rail.
+
+endif # PLATFORM_EC_POWERSEQ_ICELAKE
+
+if PLATFORM_EC_POWERSEQ_RTC_RESET
+
+config PLATFORM_EC_S5_EXIT_WAIT
+	int "time(in secs) for EC to wait for system to exit from S5"
+	default 4
+	help
+	  Timeout value for which EC has to wait for system to exit from S5
+	  before performing RTC reset and moving the system to G3.
+
+endif # PLATFORM_EC_POWERSEQ_RTC_RESET
+
+endif # PLATFORM_EC_POWERSEQ_INTEL
+
+config PLATFORM_EC_POWERSEQ_MT8192
+	bool "Use common MT8192 code for power sequencing"
+	default y
+	depends on AP_ARM_MTK_MT8192
+	help
+	  Use the MT8192 code for power sequencing.
+
+config PLATFORM_EC_POWERSEQ_MT8186
+	bool "Use common MT8186 code for power sequencing"
+	default y
+	depends on AP_ARM_MTK_MT8186
+	help
+	  Use the MT8186 code for power sequencing.
+
+config PLATFORM_EC_POWERSEQ_MT8188
+	bool "Use common MT8188 code for power sequencing"
+	default y
+	depends on AP_ARM_MTK_MT8188
+	help
+	  Use the MT8188 code for power sequencing. Re-use MT8186 common
+	  code.
+
+config PLATFORM_EC_POWERSEQ_SC7180
+	bool "SC7180 power sequencing"
+	depends on AP_ARM_QUALCOMM_SC7180
+	default y
+	help
+	  Enable power sequencing for the Qualcomm Snapdragon SC7180
+	  chipset.
+
+config PLATFORM_EC_POWERSEQ_SC7280
+	bool "SC7280 power sequencing"
+	depends on AP_ARM_QUALCOMM_SC7280
+	default y
+	help
+	  Enable power sequencing for the Qualcomm Snapdragon SC7280
+	  chipset.
+
+config PLATFORM_EC_CONSOLE_CMD_S5_TIMEOUT
+	bool "Console command: s5_timeout"
+	help
+	  Enable the console command 's5_timeout'. This command is used to
+	  change the timeout waiting for inactivity in the S5 power state before
+	  transitioning to the G3 state. This command is useful for power
+	  testing.
+
+config PLATFORM_EC_CDECK_POWER_CONTROL
+	bool "Poll C deck status for power sequencing"
+	default y
+	help
+	  Poll the C deck status and switch on and off if modules are removed or added
+
+config PLATFORM_EC_GPU_POWER_CONTROL
+	bool "Poll GPU status for power sequencing"
+	default y
+	help
+	  EPoll the GPU bay status and switch off if modules are removed
+
+endif # PLATFORM_EC_POWERSEQ
diff --git a/zephyr/Kconfig.ppc b/zephyr/Kconfig.ppc
new file mode 100644
index 0000000000..142e7cf12e
--- /dev/null
+++ b/zephyr/Kconfig.ppc
@@ -0,0 +1,207 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if PLATFORM_EC_USBC
+
+menuconfig PLATFORM_EC_USBC_PPC
+	bool "USB Type-C Power Path Controller"
+	default y
+	help
+	  Enable this to support the USB Type-C PPC on your board. This enables
+	  common routines for things like figuring out whether power is being
+	  supplied to the Chromebook over USB-C, whether the Chromebook is
+	  supplying power to another device, etc.
+
+if PLATFORM_EC_USBC_PPC
+
+config PLATFORM_EC_USBC_PPC_POLARITY
+	bool
+	help
+	  Enable this if a Power Path Controller needs to be informed of
+	  the polarity of the Configuration Channel (CC) pins. This can change
+	  depending on which way up the USB-C cable is inserted into the
+	  device.
+
+	  This should be enabled by drivers which can detect this. It cannot be
+	  set otherwise, even in prj.conf
+
+config PLATFORM_EC_USBC_PPC_SBU
+	bool
+	help
+	  Enable this if a Power Path Controller is capable of gating the
+	  Sideband Use (SBU) lines. If so, the USB mux will use this feature
+	  to isolate the lines before entering into alternate mode.
+
+	  This should be enabled by drivers which can detect this. It cannot be
+	  set otherwise, even in prj.conf
+
+config PLATFORM_EC_USBC_PPC_VCONN
+	bool
+	depends on PLATFORM_EC_USBC_VCONN
+	help
+	  Enable this if a Power Path Controller is capable of providing
+	  VCONN. If so, the USB stack will enable / disable VCONN as needed.
+
+	  This should be enabled by drivers which can detect this. It cannot be
+	  set otherwise, even in prj.conf
+
+	  Note: This may not be true, as there may be scenarios where the board
+	  might need to disable this feature (for instance when both the PPC and
+	  TCPC can supply VCONN). We can cross that bridge when we come to it.
+
+config PLATFORM_EC_USBC_PPC_AOZ1380
+	bool "Alpha & Omega USB Type-C PD Sink and Source Protection Switch"
+	default y
+	depends on DT_HAS_AOZ_AOZ1380_ENABLED
+	select PLATFORM_EC_USBC_OCP
+	help
+	  AOZ1380DI integrates two power switches and control circuitry to
+	  provide all the functionality and protection needed for sourcing
+	  and sinking current through a USB Type-C port with PD capability.
+
+config PLATFORM_EC_USBC_PPC_TCPCI
+	bool "USB-C TCPCI PD Sink and Source Protection Switch"
+	select PLATFORM_EC_USBC_OCP
+	help
+	  A TCPC which supports TCPCI integrates two power switches and control
+	  circuitry to provide the functionality and protection needed for
+	  sourcing and sinking current through a USB Type-C port with PD
+	  capability.
+
+config PLATFORM_EC_USBC_PPC_RT1718S
+	bool "Richtek RT1718S TCPC/PPC"
+	select PLATFORM_EC_USB_PD_TCPM_RT1718S
+	select PLATFORM_EC_USBC_OCP
+	select PLATFORM_EC_USBC_PPC_POLARITY
+	select PLATFORM_EC_USBC_PPC_SBU
+	select PLATFORM_EC_USBC_PPC_VCONN if PLATFORM_EC_USBC_VCONN
+	default y
+	depends on DT_HAS_RICHTEK_RT1718S_TCPC_ENABLED
+	help
+	  RT1718S integrates several high voltage protection switch of
+	  SBU1/SBU2/DP/DM from high voltage VBUS touching the adjacent pins. The
+	  AMR of SBU OVP switch is 24V. High Voltage USB 2.0 Switches also
+	  support HV DCP & fast charging protocols. The GPIOs in RT1718S can
+	  be also configured to control system block such as USB3.0 to DP Mux
+	  for alternated mode usage. VCONN Switch with OVP/OCP/RVP/RCP/UVP
+	  protection is also integrated.
+
+config PLATFORM_EC_USBC_PPC_KTU1125
+	bool "Kinetic KTU1125 Power Path Controller"
+	default y
+	depends on DT_HAS_KINETIC_KTU1125_ENABLED
+	select PLATFORM_EC_USBC_OCP
+	select PLATFORM_EC_USBC_PPC_SBU
+	select PLATFORM_EC_USBC_PPC_VCONN if PLATFORM_EC_USBC_VCONN
+	help
+	  KTU1125 integrates power switches to provide a compact protection
+	  solution to USB Type-C applications by eliminating the dependence
+	  on external components.
+
+config PLATFORM_EC_USBC_PPC_NX20P3481
+	bool "NX20P3481 High Voltage Sink/Source Combo Switch"
+	depends on DT_HAS_NXP_NX20P348X_ENABLED
+	select PLATFORM_EC_USBC_OCP
+	help
+	  The NX20P3481 is a product with combined multiple power switches
+	  and a LDO for USB PD application.
+
+config PLATFORM_EC_USBC_PPC_NX20P3483
+	bool "NX20P3483 High Voltage Sink/Source Combo Switch"
+	default y
+	depends on DT_HAS_NXP_NX20P348X_ENABLED
+	select PLATFORM_EC_USBC_OCP
+	help
+	  The NX20P3483 is a product with combined multiple power switches
+	  and a LDO for USB PD application.
+
+config PLATFORM_EC_USBC_NX20P348X_RCP_5VSRC_MASK_ENABLE
+	bool "NX20P3483 RCP 5VSRC MASK enable"
+	depends on PLATFORM_EC_USBC_PPC_NX20P3483
+	help
+	  The NX20P3483 is a product with 5V SRC reverse current protection
+	  mask enable and disable.
+
+config PLATFORM_EC_USBC_PPC_RT1739
+	bool "Richtek RT1739 Type-C Power Path Controller"
+	default y
+	depends on DT_HAS_RICHTEK_RT1739_PPC_ENABLED
+	help
+	  RT1739 is a highly integrated USB-C Bi-Directional Power Mux and
+	  Protection IC which includes IEC-61000-4-2 ESD protection cell for
+	  VBUS/CC/SBU/DP/DM.
+
+config PLATFORM_EC_USBC_PPC_SN5S330
+	bool "TI SN5S330 PD 3.0 power mux"
+	select PLATFORM_EC_USBC_OCP
+	select PLATFORM_EC_USBC_PPC_POLARITY
+	select PLATFORM_EC_USBC_PPC_SBU
+	select PLATFORM_EC_USBC_PPC_VCONN if PLATFORM_EC_USBC_VCONN
+	default y if DT_HAS_TI_SN5S330_ENABLED || DT_HAS_CROS_SN5S330_EMUL_ENABLED
+	help
+	  This is a USB Type-C Power Delivery 3.0 Bidirectional Power Mux with
+	  CC and SBU short-to-VBUS Protection and Integrated Dead Battery
+	  LDO. This chips provides protection against pins shorting to Vbus as
+	  well as ESD (Electostatic discharge) protection. It provides a simple
+	  I2C interface for for Mode Selection, Fast Role Swap, and Fault
+	  Reporting.
+
+config PLATFORM_EC_USBC_PPC_SYV682X
+	bool "SYV682X which is a Power Mux for USB PD"
+	select PLATFORM_EC_USBC_OCP
+	select PLATFORM_EC_USBC_PPC_POLARITY
+	select PLATFORM_EC_USBC_PPC_VCONN if PLATFORM_EC_USBC_VCONN
+	default y if DT_HAS_SILERGY_SYV682X_ENABLED
+	help
+	  The SYV682A is a 2 to 1 power mux switch for USB PD applications. The
+	  SYV682A supports dead battery wake up function and Fast Role Swap
+	  features. It provides protection against overcurrent, overvoltage,
+	  thermal shutdown, and undervoltage conditions.
+
+config PLATFORM_EC_USBC_PPC_SYV682C
+	bool "SYV682C Power Mux for USB PD (subset of SYV682X)"
+	depends on PLATFORM_EC_USBC_PPC_SYV682X
+	help
+	  The C version of this chip won't block I2C accessing to the CONTROL4
+	  rer (to on/off Vconn) when smart discahrge is enabled. This allows us
+	  to re-enable the smart discharge on boards using SYV682C.
+
+config PLATFORM_EC_USBC_PPC_SYV682X_HV_ILIM
+	int "SYV682X high-voltage current limit"
+	depends on PLATFORM_EC_USBC_PPC_SYV682X
+	default 2
+	help
+	  SYV682x PPC high voltage power path current limit. Valid values are
+	  0 (1.25A), 1 (1.75A), 2 (3.3A), or 3 (5.5A). See syv682x.h.
+
+config PLATFORM_EC_USBC_PPC_SYV682X_NO_CC
+	bool "SYV682X does not pass through CC"
+	help
+	  Enable this if a SYV682X does not pass through CC.
+	  There is a 3.6V limit on the HOST_CC signals, so the TCPC
+	  should not source 5V VCONN. This config determines if
+	  sourcing VCONN should be enabled by default.
+
+config PLATFORM_EC_USBC_PPC_SYV682X_SMART_DISCHARGE
+	bool "Enable smart discharge on the SYV682X PPC"
+	help
+	  Enable the smart discharge feature on VBUS provided by the SYV682x
+	  PPC.  This should be enabled for revision C and above of the SYV682X.
+	  Earlier revisions of the chip block I2C transactions during smart
+	  discharge, causing USB PD compliance issues.
+
+config PLATFORM_EC_USBC_PPC_DEDICATED_INT
+	bool "Power Power Controller has a dedicated interrupt pin"
+	help
+	  Enable this if the Power Power Controller (PPC) has level interrupts
+	  (as opposed to edge) and a dedicated interrupt pin to check the
+	  current state.
+
+	  If this is enabled the USB Power Delivery (PD) stack will call
+	  ppc_get_alert_status() to find out he interrupt status for a port.
+	  This function should be provided by the board code.
+
+endif  # PLATFORM_EC_USBC_PPC
+
+endif # PLATFORM_EC_USBC
diff --git a/zephyr/Kconfig.random b/zephyr/Kconfig.random
new file mode 100644
index 0000000000..e501df0f14
--- /dev/null
+++ b/zephyr/Kconfig.random
@@ -0,0 +1,33 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Workaround for not being able to have commas in macro arguments
+DT_CHOSEN_ZEPHYR_ENTROPY := zephyr,entropy
+
+config PLATFORM_EC_RANDOM
+	bool "Enable shim for random number generator"
+	depends on $(dt_chosen_enabled,$(DT_CHOSEN_ZEPHYR_ENTROPY))
+	select ENTROPY_GENERATOR
+	help
+	  If enabled, trng_rand() and trng_rand_bytes() functions will be
+	  available. These functions are implemented using Zephyr's entropy API.
+
+if PLATFORM_EC_RANDOM
+
+config PLATFORM_EC_HOSTCMD_RAND
+	bool "Host Command: EC_CMD_RAND_NUM"
+	default n
+	help
+	  Enable the EC_CMD_RAND_NUM host commnand which provides random number
+	  to host.
+
+config PLATFORM_EC_CONSOLE_CMD_RAND
+	bool "Enable 'rand' console command"
+	depends on SHELL
+	default n
+	help
+	  Enable the 'rand' console command. The command is used to check random
+	  number generator.
+
+endif  # PLATFORM_EC_RANDOM
diff --git a/zephyr/Kconfig.retimer b/zephyr/Kconfig.retimer
new file mode 100644
index 0000000000..63dcce65de
--- /dev/null
+++ b/zephyr/Kconfig.retimer
@@ -0,0 +1,168 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if PLATFORM_EC_USBC
+
+config PLATFORM_EC_USBC_RETIMER_INTEL_BB
+	bool "Support Intel Burnside Bridge retimer"
+	default y
+	depends on PLATFORM_EC_USB_MUX
+	depends on DT_HAS_INTEL_JHL8040R_ENABLED
+	select PLATFORM_EC_CONSOLE_CMD_RETIMER
+	select PLATFORM_EC_USB_PD_USB4
+	select PLATFORM_EC_USB_PD_TBT_COMPAT_MODE
+	select PLATFORM_EC_USBC_RETIMER_FW_UPDATE
+	help
+	  Enable this to support the Intel Burnside Bridge Thunderbolt / USB /
+	  DisplayPort retimer.
+
+	  Intel Burnside Bridge is a Type-C multi-protocol retimer to be used
+	  in on-board applications. Burnside Bridge offers the ability to latch
+	  protocol signals into on-chip memory before retransmitting them
+	  onwards. It can be used to extend the physical length of the system
+	  without increasing high-frequency jitter.
+
+	  Burnside Bridge supports spec compliant retimer of following
+	  protocols:
+
+	    - Display Port: four unidirectional DP lanes
+	    - USB3.1 Gen1/2: one bi-directional USB lane
+	    - Thunderbolt: two bi-directional CIO lanes
+	    - Multifunction Display (MFD): two unidirectional lanes of DP and
+	      one bidirectional lane of USB3.1 Gen1/2
+
+config PLATFORM_EC_USBC_RETIMER_INTEL_HB
+	bool "Support Intel Hayden Bridge retimer"
+	default y
+	depends on PLATFORM_EC_USB_MUX
+	depends on DT_HAS_INTEL_JHL9040R_ENABLED
+	select PLATFORM_EC_CONSOLE_CMD_RETIMER
+	select PLATFORM_EC_USB_PD_USB4
+	select PLATFORM_EC_USB_PD_TBT_COMPAT_MODE
+	select PLATFORM_EC_USBC_RETIMER_FW_UPDATE
+	help
+	  Enable this to support the Intel Hayden Bridge Thunderbolt / USB /
+	  DisplayPort retimer.
+
+	  Intel Hayden Bridge is a Type-C multi-protocol retimer to be used
+	  in on-board applications. Hayden Bridge offers the ability to latch
+	  protocol signals into on-chip memory before retransmitting them
+	  onwards. It can be used to extend the physical length of the system
+	  without increasing high-frequency jitter.
+
+	  Hayden Bridge supports spec compliant retimer of following
+	  protocols:
+	  - Display Port: four unidirectional DP lanes
+	  - USB3.2 Gen1/2: two bi-directional USB lanes
+	  - Thunderbolt/USB4: two bi-directional USB4 lanes
+	  - Multifunction Display (MFD): two unidirectional lanes of DP and
+	    one bi-directional lane of USB3.2 Gen1/2
+
+config PLATFORM_EC_USBC_RETIMER_INTEL_BB_RUNTIME_CONFIG
+	bool "Use runtime configuration of Intel Burnside Bridge"
+	depends on PLATFORM_EC_USBC_RETIMER_INTEL_BB
+	default y
+	help
+	  Enable this to allow run-time configuration of the Burnside Bridge
+	  driver structure. This makes the bb_controls[] array writable, i.e.
+	  not const. It should be declared as such in the board config.
+
+	  This is useful when the board has runtime information that changes
+	  the configuration, such as Chromium OS Board Info (CBI set in the
+	  factory. Without this, multiple EC images would need to be installed
+	  depending on the board.
+
+config PLATFORM_EC_USBC_RETIMER_INTEL_BB_VPRO_CAPABLE
+	bool "Enable vPro support for Intel Burnside Bridge"
+	depends on PLATFORM_EC_USBC_RETIMER_INTEL_BB
+	default n
+	help
+	  Enable this config for Intel vPro supported platforms. It allows to
+	  configure the Burnside Bridge retimer to support vPro, when connected
+	  dock supports vPro.
+
+config PLATFORM_EC_USBC_RETIMER_ANX7451
+	bool "Support Analogix ANX7451 10G Active Mux and Retimer"
+	help
+	  ANX7451 is a 4x4 re-timing mux capable of switching DisplayPort (DP)
+	  and USB3.2 Gen 2 10Gbps signals to support a single USB Type-C port.
+	  ANX7451 has built-in re-timers to recover both the USB and DP signals
+	  with loss compensation of 23dB for USB and up to 27dB for DP.
+
+config PLATFORM_EC_USBC_RETIMER_PS8818
+	bool "Parade PS8818 USB Type-C Retimer for USB and DP Alternate Mode"
+	default y
+	depends on DT_HAS_PARADE_PS8818_ENABLED
+	help
+	  PS8818 is a 10Gbps retimer for Type-C applications with the
+	  integrated USB3.1 and DisplayPort alternate mode port.
+
+config PLATFORM_EC_USBC_RETIMER_KB800X
+	bool "Enable KB800X retimer"
+	select PLATFORM_EC_CONSOLE_CMD_RETIMER
+	help
+	  The KB8001 is a Universal Serial Bus (USB) Type-C 40 Gb/s multiprotocol
+	  switch and bidirectional Bit-Level Retimer (BLR) which supports:
+	    - Display Port: four unidirectional DP lanes
+	    - USB3.1 Gen1/2: one bi-directional USB lane
+	    - USB4/Thunderbolt: two bi-directional CIO lanes
+	    - Multifunction Display (MFD): two unidirectional lanes of DP and
+	      one bidirectional lane of USB3.1 Gen1/2
+
+config PLATFORM_EC_KB800X_CUSTOM_XBAR
+	bool "Use custom remapping of HSIO XBAR"
+	depends on PLATFORM_EC_USBC_RETIMER_KB800X
+	default n
+	help
+	  Enable this to allow using a custom crossbar configuration for the HSIO
+	  lanes.
+
+config PLATFORM_EC_CONSOLE_CMD_RETIMER
+	bool "Console command: retimer"
+	help
+	  This console command allows read or write to the retimer registers
+	  connected in a chain.
+
+config PLATFORM_EC_USBC_RETIMER_KB8010
+	bool "Enable Kandou KB8010 Active Retimer"
+	default y
+	depends on DT_HAS_KANDOU_KB8010_ENABLED
+	help
+	  The KB8001 is a Universal Serial Bus (USB) Type-C 40 Gb/s multiprotocol
+	  switch and bidirectional Bit-Level Retimer (BLR) which supports:
+	    - Display Port: four unidirectional DP lanes
+	    - USB3.1 Gen1/2: one bi-directional USB lane
+	    - USB4/Thunderbolt: two bi-directional lanes
+	    - Multifunction Display (MFD): two unidirectional lanes of DP and
+	      one bidirectional lane of USB3.1 Gen1/2
+
+endif # PLATFORM_EC_USBC
+
+config PLATFORM_EC_USBC_RETIMER_ANX7483
+	bool "Support Analogix ANX7483 10G Active Retimer"
+	default y
+	depends on DT_HAS_ANALOGIX_ANX7483_ENABLED && (PLATFORM_EC_USBC || TEST_DISABLE_PLATFORM_EC_USBC)
+	help
+	  ANX7483 is a 4x4 re-driver capable of switching DisplayPort and
+	  USB3.2 Gen 2 10Gbps signals to support type-C (USB-C) ports with
+	  DisplayPort Alternate Mode.
+
+config PLATFORM_EC_USBC_RETIMER_PS8811
+	bool "Support Parade PS8811 Single Port USB 3.1 Gen 2 10G Retimer"
+	depends on PLATFORM_EC_USBC || TEST_DISABLE_PLATFORM_EC_USBC
+	help
+	  The PS8811 is a one-port bidirectional USB 3.1 Gen 2 retimer that
+	  integrates the UniEye equalizer and a retimer to re-condition USB 3.1
+	  signals for long media link applications. It supports USB 3.1 Gen 2
+	  with operation speed up to 10Gbps as well as Gen 1 operation at 5Gbps.
+
+config PLATFORM_EC_USBC_RETIMER_ANX7452
+	bool "Support Analogix ANX7452 Active Retimer"
+	default y
+	depends on DT_HAS_ANALOGIX_ANX7452_ENABLED
+	help
+	  ANX7452 is a 2-lane USB4 Re-timer MUX capable of switching the USB4
+	  fabric protocol to support a single USB Type-C™ (USB-C™) port. ANX7452
+	  can be also configured to a DisplayPort (DP)2.0 Re-timer which
+	  supports up to 4-lane UHBR20.
diff --git a/zephyr/Kconfig.rsa b/zephyr/Kconfig.rsa
new file mode 100644
index 0000000000..4933087a81
--- /dev/null
+++ b/zephyr/Kconfig.rsa
@@ -0,0 +1,74 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config PLATFORM_EC_RSA
+	bool "Support verifying RSA signature"
+	help
+	  Includes a library for verifying RSA signature.
+
+	  The algorithm parameters are pre-defined and configurable using
+	  following config variables.
+
+if PLATFORM_EC_RSA
+
+config PLATFORM_EC_RSA_KEY_SIZE
+	int "RSA key size"
+	default 2048
+	help
+	  This option specifies the key size used by RSA algorithm.
+
+config PLATFORM_EC_RSA_EXPONENT_3
+	bool "Use RSA exponent 3"
+	help
+	  Use public exponent 3 instead of F4(65537). Keys with exponent 3 are
+	  much quicker to verify, can be used on time critical tasks.
+
+endif # PLATFORM_EC_RSA
+
+config PLATFORM_EC_RWSIG
+	bool "Verify the RW firmware using the RSA signature."
+	select HAS_TASK_RWSIG
+	select PLATFORM_EC_RSA
+	help
+	  For accessories without software sync, enable this option to allow RO
+	  verify the RW firmware using RSA signature.
+
+	  If enabled, an extra signing step is added after linker stage, which
+	  signs and inserts the keys and signatures into the final image.
+
+	  Board should specify the path to the private key using
+	  PLATFORM_EC_RWSIG_KEY_PATH config variable.
+
+if PLATFORM_EC_RWSIG
+
+config PLATFORM_EC_RWSIG_KEY_PATH
+	string "Path to the RSA private key for RWSIG signing"
+	help
+	  Path to the RSA private key in PEM format, relative to the platform/ec
+	  repo.
+
+choice PLATFORM_EC_RWSIG_TYPE
+	bool "futility signature type"
+	default PLATFORM_EC_RWSIG_TYPE_RWSIG
+
+config PLATFORM_EC_RWSIG_TYPE_RWSIG
+	bool "RWSIG"
+	help
+	  Use command `futility sign --type rwsig` to sign the firmware.
+
+	  Requires RO firmware contains a 1kB KEY_RO section that holds the
+	  public key in vboot v2.1 format, and RW firmware contains a 1kB
+	  SIG_RW section that holds the signature.
+
+config PLATFORM_EC_RWSIG_TYPE_USBPD1
+	bool "USBPD1"
+	select DEPRECATED
+	help
+	  Use command `futility sign --type usbpd1` to sign the firmware.
+
+	  [DEPRECATED] use PLATFORM_EC_RWSIG_TYPE_RWSIG instead.
+
+endchoice
+
+endif # PLATFORM_EC_RWSIG
diff --git a/zephyr/Kconfig.rtc b/zephyr/Kconfig.rtc
new file mode 100644
index 0000000000..a157ffdc77
--- /dev/null
+++ b/zephyr/Kconfig.rtc
@@ -0,0 +1,40 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if PLATFORM_EC_RTC
+
+config PLATFORM_EC_CONSOLE_CMD_RTC
+	bool "Console command: rtc"
+	help
+	  This command allows getting and setting the current RTC value. The
+	  value is in seconds since the Epoch (midnight on 1/1/70). You can
+	  convert this to a human date on the command line with 'date -u -d @n'
+	  where n is the numeric value. To convert a time to seconds, use:
+
+	     date -d '1970-01-01 UTC + n seconds'
+
+config PLATFORM_EC_CONSOLE_CMD_RTC_ALARM
+	bool "Console command: rtc_alarm"
+	depends on PLATFORM_EC_CONSOLE_CMD_RTC
+	help
+	  This command supports setting a real-time-clock (RTC) alarm that
+	  causes an interrupt when the timer reaches that point. To set the
+	  alarm:
+
+	     rtc <sec> [<usec>]
+
+	  where:
+	    <sec> is the number of seconds since the epoch
+	    <usec> is the optional number of microseconds (fractional seconds)
+
+config PLATFORM_EC_HOSTCMD_RTC
+	bool "Host command: EC_CMD_RTC_GET_VALUE etc."
+	depends on PLATFORM_EC_HOSTCMD
+	help
+	  Enables support for EC_CMD_RTC_GET_VALUE, EC_CMD_RTC_SET_VALUE,
+	  EC_CMD_RTC_GET_ALARM and EC_CMD_RTC_SET_ALARM which colectively allow
+	  the AP to control the EC's real-time-clock. The AP typically makes
+	  use of the EC's RTC to avoid needing a discrete RTC chip on the board.
+
+endif # PLATFORM_EC_RTC
diff --git a/zephyr/Kconfig.sensor_devices b/zephyr/Kconfig.sensor_devices
new file mode 100644
index 0000000000..12f5951ff5
--- /dev/null
+++ b/zephyr/Kconfig.sensor_devices
@@ -0,0 +1,135 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+menu "Sensor Devices"
+
+config PLATFORM_EC_ACCELGYRO_BMI
+	bool
+	select PLATFORM_EC_MATH_UTIL
+	help
+	  This config does not contain a prompt on purpose, it cannot be set
+	  directly from a .conf file. This value should be set using an `select`
+	  statement in other BMI family of drivers such as BMI260.
+
+config PLATFORM_EC_ACCELGYRO_ICM
+	bool
+	help
+	  This config does not contain a prompt on purpose, it cannot be set
+	  directly from a .conf file. This value should be set using an `select`
+	  statement in other BMI family of drivers such as ICM426XX.
+
+config PLATFORM_EC_ACCEL_BMA255
+	bool "BMA2X2 Accelerometer Family Driver"
+	select PLATFORM_EC_MATH_UTIL
+	help
+	  The driver supports Bosch's a triaxial, low-g acceleration sensor.
+	  It allows measurements of acceleration in three perpendicular axes.
+	  Currently the driver supports BMA253, BMA255, BMA355, BMA280, BMA282,
+	  BMA223, BMA254, BMA284, BMA250E, BMA222E, BMC150 BMC056, BMC156.
+
+config PLATFORM_EC_ACCEL_BMA4XX
+	bool "BMA4XX Accelerometer Family Driver"
+	help
+	  The driver supports Bosch's a triaxial, low-g acceleration sensor.
+	  It allows measurements of acceleration in three perpendicular axes.
+	  Currently the driver supports BMA4XX.
+
+config PLATFORM_EC_ACCEL_KX022
+	bool "KX022 Accelerometer Driver"
+	help
+	  The driver supports Kionix's KX022 triaxial low-g acceleration sensor.
+	  It allows measurements of acceleration in three perpendicular axes.
+
+config PLATFORM_EC_ACCEL_LIS2DW12
+	bool "LIS2DW12 Accelerometer Driver"
+	select PLATFORM_EC_STM_MEMS_COMMON
+	help
+	  The driver supports ST's LIS2DW12 3D digital accelerometer sensor.
+	  It allows measurements of acceleration in three perpendicular axes.
+
+config PLATFORM_EC_ACCELGYRO_BMI160
+	bool "BMI160 Accelgyrometer Driver"
+	select PLATFORM_EC_ACCELGYRO_BMI
+	help
+	  The driver supports Bosch's BMI160 which is an Inertial Measurement
+	  Unit (IMU) consisting of a 16-bit tri-axial gyroscope and a 16-bit
+	  tri-axial accelerometer.
+
+config PLATFORM_EC_ACCELGYRO_BMI260
+	bool "BMI260 Accelgyrometer Driver"
+	select PLATFORM_EC_ACCELGYRO_BMI
+	help
+	  The driver supports Bosch's BMI260 which is an Inertial Measurement
+	  Unit (IMU) consisting of a 16-bit tri-axial gyroscope and a 16-bit
+	  tri-axial accelerometer.
+
+config PLATFORM_EC_ACCELGYRO_BMI3XX
+	bool "BMI3XX Accelgyrometer Driver"
+	select PLATFORM_EC_ACCELGYRO_BMI
+	help
+	  The driver supports Bosch's BMI3XX which is an Inertial Measurement
+	  Unit (IMU) consisting of a 16-bit tri-axial gyroscope and a 16-bit
+	  tri-axial accelerometer.
+
+config PLATFORM_EC_ALS_TCS3400
+	bool "TCS3400 Ambient Light Senseor Driver"
+	help
+	  The driver supports TCS3400 which provides color and
+	  IR (red, green, blue, clear and IR) ambient light sensing.
+
+config PLATFORM_EC_ALS_CM32183
+	bool "CM32183 Ambient Light Sensor Driver"
+	help
+	  The driver supports CM32183 which provides ambient
+	  light sensing.
+
+config PLATFORM_EC_ALS_TCS3400_EMULATED_IRQ_EVENT
+	bool "Enable TCS3400 Ambient Light Sensor Driver Polling mode"
+	help
+	  Enable tcs3400 to operate without interrupt pin. This config is used in
+	  conjunction with CONFIG_ALS_TCS3400_INT_EVENT. When this option is enabled,
+	  the read is initiated in the same manner as when interrupts are used, but the
+	  event which triggers the irq_handler is generated by deferred call.
+
+config PLATFORM_EC_ACCELGYRO_ICM426XX
+	bool "ICM426XX Accelgyro Driver"
+	select PLATFORM_EC_ACCELGYRO_ICM
+	help
+	  The driver supports ICM426XX which provides both accelerometer and
+	  gyroscope readings.
+
+config PLATFORM_EC_ACCELGYRO_ICM42607
+	bool "ICM42607 Accelgyro Driver"
+	select PLATFORM_EC_ACCELGYRO_ICM
+	help
+	  The driver supports ICM42607 which provides both accelerometer and
+	  gyroscope readings.
+
+config PLATFORM_EC_ACCELGYRO_LSM6DSO
+	bool "LSM6DSO Accelgyro Driver"
+	select PLATFORM_EC_STM_MEMS_COMMON
+	help
+	  The driver supports ST's LSM6DSO 3D digital accelerometer sensor.
+	  It allows measurements of acceleration in three perpendicular axes.
+
+config PLATFORM_EC_ACCELGYRO_LSM6DSM
+	bool "LSM6DSM Accelgyro Driver"
+	select PLATFORM_EC_STM_MEMS_COMMON
+	help
+	  The driver supports ST's LSM6DSM 3D digital accelerometer sensor.
+	  It allows measurements of acceleration in three perpendicular axes.
+
+config PLATFORM_EC_STM_MEMS_COMMON
+	bool
+	help
+	  The driver supports functionality that is common to
+	  STMicroelectronics(STM) micro-electromechanical system(MEMS)
+	  sensor devices.  This should be enabled by drivers that use
+	  this common framework.  It cannot be set otherwise, even in
+	  prj.conf.
+
+rsource "Kconfig.accelgyro_bmi"
+rsource "Kconfig.accelgyro_icm"
+
+endmenu # Sensor devices
diff --git a/zephyr/Kconfig.stacks b/zephyr/Kconfig.stacks
new file mode 100644
index 0000000000..cac0732e3f
--- /dev/null
+++ b/zephyr/Kconfig.stacks
@@ -0,0 +1,108 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+##############################################################################
+
+# Zephyr internal stack sizes
+#
+# The intent is to try and keep the stack sizes in one place.
+
+config MAIN_STACK_SIZE
+	default 1536 if SOC_SERIES_RISCV32_IT8XXX2
+	default 1200 if SOC_SERIES_NPCX7
+	default 1200 if SOC_SERIES_NPCX9
+
+config IDLE_STACK_SIZE
+	default 500 if SOC_SERIES_RISCV32_IT8XXX2
+	default 192 if SOC_SERIES_NPCX7
+	default 400 if SOC_SERIES_NPCX9
+
+config ISR_STACK_SIZE
+	default 1024 if SOC_SERIES_RISCV32_IT8XXX2
+	default 1024 if SOC_SERIES_NPCX7
+	default 1024 if SOC_SERIES_NPCX9
+
+config SHELL_STACK_SIZE
+	default 1536 if SOC_SERIES_RISCV32_IT8XXX2
+	default 1536 if SOC_SERIES_NPCX7
+	default 1536 if SOC_SERIES_NPCX9
+
+config SYSTEM_WORKQUEUE_STACK_SIZE
+	default 1536 if SOC_SERIES_RISCV32_IT8XXX2
+	default 1024 if SOC_SERIES_NPCX7
+	default 1024 if SOC_SERIES_NPCX9
+
+# Chromium EC stack sizes
+
+config TASK_CHARGER_STACK_SIZE
+	default 1280 if SOC_SERIES_RISCV32_IT8XXX2
+	default 704 if SOC_SERIES_NPCX7
+	default 1056 if SOC_SERIES_NPCX9
+
+config TASK_CHIPSET_STACK_SIZE
+	default 820 if SOC_SERIES_RISCV32_IT8XXX2
+	default 1056 if AP_x86
+	default 684 if AP_ARM && SOC_SERIES_NPCX7
+	default 1056 if AP_ARM && SOC_SERIES_NPCX9
+
+config TASK_HOSTCMD_STACK_SIZE
+	default 1152 if SOC_SERIES_RISCV32_IT8XXX2
+	default 800 if SOC_SERIES_NPCX7
+	default 800 if SOC_SERIES_NPCX9
+
+config TASK_KEYPROTO_STACK_SIZE
+	default 1280 if SOC_SERIES_RISCV32_IT8XXX2
+	default 800 if SOC_SERIES_NPCX7
+	default 800 if SOC_SERIES_NPCX9
+
+config TASK_KEYSCAN_STACK_SIZE
+	default 1280 if SOC_SERIES_RISCV32_IT8XXX2
+	default 1024 if SOC_SERIES_NPCX7
+	default 1024 if SOC_SERIES_NPCX9
+
+config TASK_MOTIONSENSE_STACK_SIZE
+	default 1280 if SOC_SERIES_RISCV32_IT8XXX2
+	default 1024 if SOC_SERIES_NPCX7
+	default 1024 if SOC_SERIES_NPCX9
+
+config TASK_POWERBTN_STACK_SIZE
+	default 1280 if SOC_SERIES_RISCV32_IT8XXX2
+	default 800 if SOC_SERIES_NPCX7
+	default 800 if SOC_SERIES_NPCX9
+
+config TASK_PD_STACK_SIZE
+	default 1536 if SOC_SERIES_RISCV32_IT8XXX2
+	default 1184 if SOC_SERIES_NPCX7
+	default 1184 if SOC_SERIES_NPCX9
+
+config TASK_PD_INT_STACK_SIZE
+	default 1152 if SOC_SERIES_RISCV32_IT8XXX2
+	default 880 if SOC_SERIES_NPCX7
+	default 880 if SOC_SERIES_NPCX9
+
+config TASK_CYPD_STACK_SIZE
+	default 1280 if SOC_SERIES_RISCV32_IT8XXX2
+	default 1024 if SOC_SERIES_NPCX7
+	default 1024 if SOC_SERIES_NPCX9
+
+config TASK_ALS_STACK_SIZE
+	default 1280 if SOC_SERIES_RISCV32_IT8XXX2
+	default 1024 if SOC_SERIES_NPCX7
+	default 1024 if SOC_SERIES_NPCX9
+
+config TASK_USB_CHG_STACK_SIZE
+	default 1152 if SOC_SERIES_RISCV32_IT8XXX2
+	default 800 if SOC_SERIES_NPCX7
+	default 800 if SOC_SERIES_NPCX9
+
+config TASK_USB_MUX_STACK_SIZE
+	default 1280 if SOC_SERIES_RISCV32_IT8XXX2
+	default 1024 if SOC_SERIES_NPCX7
+	default 1024 if SOC_SERIES_NPCX9
+
+config AP_PWRSEQ_STACK_SIZE
+	default 1280 if SOC_SERIES_RISCV32_IT8XXX2
+	default 1280 if SOC_SERIES_NPCX7
+	default 1280 if SOC_SERIES_NPCX9
+	default 1280 # Needed since there is no other default
diff --git a/zephyr/Kconfig.svdm_rsp b/zephyr/Kconfig.svdm_rsp
new file mode 100644
index 0000000000..a7b0a61a5e
--- /dev/null
+++ b/zephyr/Kconfig.svdm_rsp
@@ -0,0 +1,44 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if PLATFORM_EC_USB_POWER_DELIVERY
+
+choice SVDM_RSP_CHOICE
+	prompt "SVDM handler implementation"
+	# Default value is the first listed choice that has satisfied
+	# dependencies: this defaults to DFP_ONLY if possible.
+	help
+	  Select how USB-PD Structured Vendor Defined Messages (SVDM) will be
+	  handled.
+
+config SVDM_RSP_DFP_ONLY
+	bool "DFP-only"
+	# USB4 and TBT modes require more support
+	depends on !PLATFORM_EC_USB_PD_USB4
+	depends on !PLATFORM_EC_USB_PD_TBT_COMPAT_MODE
+	# DRDs are not DFP-only
+	depends on !PLATFORM_EC_USB_PD_USB32_DRD
+	help
+	  Respond to Discover Identity requests only, reporting DFP-only
+	  operation on all ports. The Identity response indicates the device has
+	  Type-C receptacles and supports USB 3.2, operating as a USB-PD host.
+
+	  This is appropriate for systems that only ever operate as USB hosts
+	  and do not require support for more complex modes like USB4 or TBT.
+
+config SVDM_RSP_CUSTOM
+	bool "Custom"
+	help
+	  The application defines SVDM handler functions appropriate to its
+	  feature set by populating fields of the svdm_rsp struct:
+
+	      __override const struct svdm_response svdm_rsp = { ... };
+
+	  If any pointer in this struct is NULL, that command is unsupported:
+	  matching SVDM commands that are received will be ignored and a
+	  Not_Supported reply sent if required. If no definition __overrides
+	  the default, all SVDM commands are treated as unsupported.
+
+endchoice
+endif  # PLATFORM_EC_USB_POWER_DELIVERY
diff --git a/zephyr/Kconfig.system b/zephyr/Kconfig.system
new file mode 100644
index 0000000000..2c854c85dd
--- /dev/null
+++ b/zephyr/Kconfig.system
@@ -0,0 +1,125 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if PLATFORM_EC
+
+config PLATFORM_EC_CONSOLE_CMD_SCRATCHPAD
+	bool "Console Command: scratchpad"
+	help
+	  Enable the scratchpad console command. The scratchpad register
+	  maintain its contents across a software-requested warm reset. The
+	  command is used to set or get the scratchpad.
+
+config PLATFORM_EC_CONSOLE_CMD_SYSINFO
+	bool "Console Command: sysinfo"
+	default y
+	help
+	  Enable the sysinfo console command, which shows statistics
+	  about the current image copy running, reset flags, etc.
+
+config PLATFORM_EC_HIBERNATE
+	bool
+	help
+	  Enable system hibernation.
+	  The type of hibernation supported must be selected.
+
+choice PLATFORM_EC_HIBERNATE_TYPE
+	prompt "Choose a hibernate type"
+	default PLATFORM_EC_HIBERNATE_PSL if DT_HAS_NUVOTON_NPCX_POWER_PSL_ENABLED && SOC_FAMILY_NPCX
+	default PLATFORM_EC_HIBERNATE_WAKE_PINS if !DT_HAS_NUVOTON_NPCX_POWER_PSL_ENABLED || !SOC_FAMILY_NPCX
+	help
+	  Select the type of hibernation supported. Either
+	  PLATFORM_EC_HIBERNATE_PSL (for power switch logic support) or
+	  PLATFORM_EC_HIBERNATE_WAKE_PINS (using wake pins) are
+	  supported.
+
+config PLATFORM_EC_HIBERNATE_PSL
+	bool "System hibernating with PSL (Power Switch Logic) mechanism"
+	depends on DT_HAS_NUVOTON_NPCX_POWER_PSL_ENABLED
+	depends on SOC_FAMILY_NPCX
+	select PLATFORM_EC_HIBERNATE
+	help
+	  Use PSL (Power Switch Logic) for hibernating. It turns off VCC power
+	  rail for ultra-low power consumption and uses PSL inputs rely on VSBY
+	  power rail to wake up ec and the whole system.
+
+config PLATFORM_EC_HIBERNATE_WAKE_PINS
+	bool "System hibernating with wake-source pins"
+	select PLATFORM_EC_HIBERNATE
+	help
+	  Use wake source pins for hibernating. It turns off VCC power
+	  rail for ultra-low power consumption and uses a low power
+	  power rail. Changes on wake source pins will wake up the EC.
+
+endchoice # PLATFORM_EC_HIBERNATE_TYPE
+
+config PLATFORM_EC_HIBERNATE_DELAY_SEC
+	int "Delay in seconds from AP power off to hibernate"
+	depends on PLATFORM_EC_HIBERNATE
+	default 3600
+	help
+	  This value is the delay in seconds from when the AP enters G3
+	  to when the system is hibernated.
+
+config PLATFORM_EC_SYSTEM_PRE_INIT_PRIORITY
+	int "System pre-initialization priority"
+	default 20
+	range 0 99
+	help
+	  This defines the initialization priority for the CROS
+	  system_pre_init() function. system_pre_init() reads chip level reset
+	  cause and stores it into the system reset flags. All drivers, except
+	  those critical to determining the reset type, should be initialized at
+	  lower priority so that the system reset flags are valid.
+
+config PLATFORM_EC_FW_RESET_VECTOR
+	bool "Firmware Reset Vector chip specific retrieval"
+	default y if SOC_FAMILY_RISCV_ITE
+	help
+	  This defines if there is a chip specific machanism for
+	  retrieving the firmware reset vector. The function that
+	  needs to be provided is system_get_fw_reset_vector that
+	  will return the address of the reset vector.
+
+config PLATFORM_EC_WP_DISABLE
+	bool "Always disable the write protect function"
+	default n
+	help
+	  This defines if the project does not connect the HW write
+	  protect pin, always return the write protect disable when
+	  system get the write protect status.
+
+config PLATFORM_EC_SYSTEM_SAFE_MODE
+	bool "Enable System Safe Mode"
+	default n
+	depends on (CPU_CORTEX_M || ARCH_POSIX)
+	help
+	  This enables system safe mode for retrieving system state after
+	  a panic occurs. System safe mode only runs briefly after a panic.
+
+config PLATFORM_EC_SYSTEM_SAFE_MODE_TIMEOUT_MSEC
+	int "System safe mode timeout"
+	default 2000
+	depends on PLATFORM_EC_SYSTEM_SAFE_MODE
+	help
+	  Safe mode will force a system reset after this timeout. The system may
+	  reset sooner if all safe mode tasks are completed before the timeout.
+
+config PLATFORM_EC_SYSTEM_SAFE_MODE_PRINT_STACK
+	bool "Print stack to log after panic"
+	default y
+	depends on PLATFORM_EC_SYSTEM_SAFE_MODE
+	help
+	  Prints the stack of the faulting thread to the console buffer in
+	  system safe mode.
+
+config PLATFORM_EC_HOST_COMMAND_MEMORY_DUMP
+	bool "Enable Memory Dump Host Commands"
+	select THREAD_STACK_INFO
+	help
+	  Enables fetching a memory dump using host commands. This is useful when
+	  debugging panics. May not dump all memory, e.g. sensitive memory will
+	  not be dumped.
+
+endif # PLATFORM_EC
diff --git a/zephyr/Kconfig.tasks b/zephyr/Kconfig.tasks
new file mode 100644
index 0000000000..5d103b9414
--- /dev/null
+++ b/zephyr/Kconfig.tasks
@@ -0,0 +1,327 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Please keep these tasks in alphabetical order
+
+menu "Tasks"
+
+config TASKS_SET_TEST_RUNNER_TID_RULE
+	bool "Automatically call set_test_runner_tid() for each test"
+	depends on ZTEST && ZTEST_NEW_API
+	help
+	  This enables the test rule which will run before each unit test and
+	  call set_test_runner_tid(). This function is needed to allow-list the
+	  new thread created by ztest to access some of the components in the
+	  EC.
+
+config HAS_TASK_CHARGER
+	bool
+	depends on PLATFORM_EC_BATTERY
+	help
+	  This turns on the charger task. This deals with monitoring the
+	  battery to make sure it is present and is responding properly to
+	  requests. If the battery is not full, it enables charging from a
+	  suitable power source.
+
+if HAS_TASK_CHARGER
+
+config TASK_CHARGER_STACK_SIZE
+	int "CHARGER task stack size"
+	default 1024	# EC uses VENTI_TASK_STACK_SIZE which is 896
+	help
+	  The stack size of the charger task.
+
+	  See b/176180736 for checking these stack sizes.
+
+endif # HAS_TASK_CHARGER
+
+config HAS_TASK_CHG_RAMP
+	bool
+	depends on PLATFORM_EC_BATTERY
+	help
+	  This turns on the charger ramp task. This attempts to ramp up the
+	  current from an attached charger to the maximum available current.
+	  It handles the incoming VBUS voltage sagging as well as the user
+	  attaching different chargers.
+
+if HAS_TASK_CHG_RAMP
+
+config TASK_CHG_RAMP_STACK_SIZE
+	int "CHG_RAMP task stack size"
+	default 768	# EC uses TASK_STACK_SIZE which is 512 for npcx
+	help
+	  The stack size of the charger task.
+
+	  See b/176180736 for checking these stack sizes.
+
+endif # HAS_TASK_CHG_RAMP
+
+config HAS_TASK_CHIPSET
+	bool
+	depends on PLATFORM_EC_POWERSEQ
+	help
+	  This turns on the chipset task which handles powering the chipset
+	  on and off. Powering on involves going through a sequence of enabling
+	  different power rails (e.g. by enabling GPIOs that control a PMIC)
+	  and monitoring power-good indicators to meet the specifications
+	  defined by the vendor.
+
+if HAS_TASK_CHIPSET
+
+config TASK_CHIPSET_STACK_SIZE
+	int "CHIPSET task stack size"
+	default 1024
+	help
+	  The stack size of the power button task.
+
+endif # HAS_TASK_CHIPSET
+
+config HAS_TASK_HOSTCMD
+	bool
+	depends on PLATFORM_EC_HOSTCMD
+	help
+	  This turns on the hostcmd task which handles communication with the
+	  AP. The AP sends a command to the EC and it responds when able. An
+	  interrupt can be used to indicate to the AP that the EC has something
+	  for it.
+
+if HAS_TASK_HOSTCMD
+
+choice TASK_HOSTCMD_THREAD_MODE
+	prompt "Host command thread selection"
+	default TASK_HOSTCMD_THREAD_DEDICATED if ZTEST
+
+config TASK_HOSTCMD_THREAD_MAIN
+	bool "Run the host command in the main thread"
+	help
+	  Run the HOSTCMD task in the main thread, reusing the main thread
+	  resources. Set the stack size using MAIN_STACK_SIZE.
+
+config TASK_HOSTCMD_THREAD_DEDICATED
+	bool "Run the host command in a dedicated thread"
+	help
+	  Run the HOSTCMD task in a dedicated thread.
+
+endchoice
+
+config TASK_HOSTCMD_STACK_SIZE
+	int "HOSTCMD task stack size"
+	depends on TASK_HOSTCMD_THREAD_DEDICATED
+	default 1024
+	help
+	  The size of the host-command task stack.
+
+endif # HAS_TASK_HOSTCMD
+
+config HAS_TASK_KEYPROTO
+	bool
+	depends on PLATFORM_EC_KEYBOARD_PROTOCOL_8042
+	help
+	  This turns on the keyproto task which handles conversion of keyboard
+	  scans into i8042 messages on x86 platforms. This is not used or needed
+	  on ARM platforms, which send the raw keyboard scans to the AP for
+	  processing.
+
+if HAS_TASK_KEYPROTO
+
+config TASK_KEYPROTO_STACK_SIZE
+	int "KEYPROTO task stack size"
+	default 768
+	help
+	  The stack size of the keyproto task.
+
+endif # HAS_TASK_KEYPROTO
+
+config HAS_TASK_KEYSCAN
+	bool
+	depends on PLATFORM_EC_KEYBOARD
+	help
+	  This turns on the keyscan task which handles scanning the keyboard
+	  and producing a list of changes in the key state. This list can either
+	  be sent to the keyboard-protocol task or directly to the AP for
+	  processing.
+
+if HAS_TASK_KEYSCAN
+
+config TASK_KEYSCAN_STACK_SIZE
+	int "KEYSCAN task stack size"
+	default 768
+	help
+	  The stack size of the keyscan task.
+
+endif # HAS_TASK_KEYSCAN
+
+config HAS_TASK_MOTIONSENSE
+	bool
+	help
+	  This turns on the motion sense task which collects sensor data from the
+	  sensors and reports them to AP. Using the data, it also produces other
+	  meaningful reports to AP like lid angle and tablet mode.
+
+if HAS_TASK_MOTIONSENSE
+
+config TASK_MOTIONSENSE_STACK_SIZE
+	int "MOTIONSENSE task stack size"
+	default 4096
+	help
+	  The size of the motion sense task stack.
+
+endif # HAS_TASK_MOTIONSENSE
+
+config HAS_TASK_POWERBTN
+	bool
+	depends on PLATFORM_EC_POWER_BUTTON
+	help
+	  This turns on the powerbtn task which handles monitoring the power
+	  button. When the application processor (AP) is off (S5 or G3 states),
+	  this task triggers a power-up sequence on a power-button press. When
+	  the AP is on (S3 or above state) x86 machines normally reset when the
+	  power button is held for 4 seconds but this tasks adjusts that to 8
+	  seconds, to allow time for the usual Chromium OS shutdown sequence.
+
+config HAS_TASK_POWERBTN_CUSTOMER
+	bool
+	depends on PLATFORM_EC_POWER_BUTTON
+	help
+	  This turns on the powerbtn task which handles monitoring the power
+	  button. When the application processor (AP) is off (S5 or G3 states),
+	  this task triggers a power-up sequence on a power-button press.
+
+if HAS_TASK_POWERBTN || HAS_TASK_POWERBTN_CUSTOMER
+
+config TASK_POWERBTN_STACK_SIZE
+	int "POWERBTN task stack size"
+	default 1024
+	help
+	  The stack size of the power-button task.
+
+endif # HAS_TASK_POWERBTN
+
+if PLATFORM_EC_USB_POWER_DELIVERY
+
+config TASK_PD_STACK_SIZE
+	int "PD tasks stack size"
+	default 1024	# EC uses VENTI_TASK_STACK_SIZE which is 896
+	help
+	  The stack size of the PD_Cx tasks.
+
+config TASK_PD_INT_STACK_SIZE
+	int "PD_INT task stack size"
+	default 1280
+	help
+	  The stack size of the PD_Cn_INT tasks.
+
+endif # PLATFORM_EC_USB_POWER_DELIVERY
+
+if HAS_TASK_DPS
+
+config TASK_DPS_STACK_SIZE
+	int "DPS task stack size"
+	default 1024
+	help
+	  The stack size of the DPS task.
+
+endif # HAS_TASK_DPS
+
+config HAS_TASK_DPS
+	bool
+	depends on PLATFORM_EC_USB_PD_DPS
+	help
+	  This turns on the DPS task which evalutes the SRCCAP from all the SNK
+	  ports and issues a new power request to the port which has the most
+	  efficient power data object (PDO).
+
+
+config HAS_TASK_PD_INT_SHARED
+	bool # Selected by PLATFORM_EC_USB_PD_INT_SHARED
+	help
+	  This turns on the PD_INT_SHARED task which services PD message
+	  interrupts for any port which has a shared IRQ enabled.
+
+
+if PLATFORM_EC_USB_POWER_DELIVERY
+
+config TASK_USB_CHG_STACK_SIZE
+	int "USB_CHG tasks stack size"
+	default 1280	# EC uses VENTI_TASK_STACK_SIZE which is 896
+	help
+	  The stack size of the USB charger task. If there are multiple tasks,
+	  each one gets the same stack size.
+
+	  See b/176180736 for checking these stack sizes.
+
+endif # PLATFORM_EC_USB_POWER_DELIVERY
+
+config HAS_TASK_CYPD
+	bool
+	depends on PLATFORM_EC_STANDALONE_PD_CHIP
+	help
+	  This turns on the CYPD task which handles standalone PD chip
+	  to service PD message interrupts for any port.
+
+if HAS_TASK_CYPD
+
+config TASK_CYPD_STACK_SIZE
+	int "CYPD task stack size"
+	default 768
+	help
+	  The stack size of the cypd task.
+
+endif # HASK_TASK_CYPD
+
+config HAS_TASK_ALS
+	bool
+	depends on PLATFORM_EC_DEDICATED_ALS
+	help
+	  This turns on the ALS task which store the ASL sensor value into
+	  EC memmap.
+
+if HAS_TASK_ALS
+
+config TASK_ALS_STACK_SIZE
+	int "ALS task stack size"
+	default 768
+	help
+	  The stack size of the ALS task.
+
+endif # HAS_TASK_ALS
+
+config HAS_TASK_TOUCHPAD
+	bool
+	help
+	  This turns on the touchpad task which handles the input event from
+	  touchpad, and forwards the event to AP through either USB-HID or MKBP
+	  interface.
+
+if HAS_TASK_TOUCHPAD
+
+config TASK_TOUCHPAD_STACK_SIZE
+	int "TOUCHPAD task stack size"
+	default 1280
+	help
+	  The stack size of the touchpad task.
+
+	  See b/176180736 for checking these stack sizes.
+
+endif # HAS_TASK_TOUCHPAD
+
+config HAS_TASK_RWSIG
+	bool # Selected by PLATFORM_EC_RWSIG
+	help
+	  This turns on the RWSIG task which verifys and jumps to the RW
+	  firmware automatically.
+
+if HAS_TASK_RWSIG
+
+config TASK_RWSIG_STACK_SIZE
+	int "RWSIG task stack size"
+	default 1536
+	help
+	  The stack size of the RWSIG task.
+
+	  See b/176180736 for checking these stack sizes.
+
+endif # HAS_TASK_RWSIG
+
+endmenu # Tasks
diff --git a/zephyr/Kconfig.tcpm b/zephyr/Kconfig.tcpm
new file mode 100644
index 0000000000..729866f4f0
--- /dev/null
+++ b/zephyr/Kconfig.tcpm
@@ -0,0 +1,354 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if PLATFORM_EC_USBC
+
+config PLATFORM_EC_USB_PD_TCPM_TCPCI
+	bool "TCPCI Compatible Driver"
+	select PLATFORM_EC_USBC_OCP
+	help
+	  Enable a TCPC compatible with the Type-C Port Controller Interface
+	  (TCPCI) Specification. This driver supports both Rev1 v1.2 and Rev2
+	  v1.0 of the TCPCI specification. Select this driver directly only
+	  if your specific TCPC chip is not listed as a separate config option.
+
+	  This driver currently is required by all TCPM drivers below, even
+	  drivers that do not implement the TCPCI specification.
+
+config PLATFORM_EC_USB_PD_TCPM_CCGXXF
+	bool "Cypress CCGXXF Single/Dual USB-C Port Controller with Source PPC"
+	default y
+	depends on DT_HAS_CYPRESS_CCGXXF_ENABLED
+	select PLATFORM_EC_USB_PD_TCPM_TCPCI
+	help
+	  CCGXXF are Single/Dual port USB Type-C controllers that comply with
+	  the USB Type-C and PD specifications. These devices include an
+	  integrated Port Protection, VBUS Source path load switch and contain
+	  a True Random Type-C Transceiver including the Type-C termination
+	  resistors Rp, Rd, and dead battery Rd termination.
+
+config PLATFORM_EC_USB_PD_TCPM_ITE_ON_CHIP
+	bool
+	help
+	  Use the ITE-series TCPM driver built into the EC chip.
+
+	  This is automatically selected by the ITE USB Type-C drivers. It
+	  cannot be set otherwise, even in prj.conf
+
+config PLATFORM_EC_USB_PD_TCPM_DRIVER_IT83XX
+	bool "Enable IT83XX driver"
+	select PLATFORM_EC_USB_PD_TCPM_ITE_ON_CHIP
+	select PLATFORM_EC_USB_PD_TCPM_TCPCI
+	help
+	  Enable a driver for the ITE IT83XX on-chip UBB Type-C Port Manager.
+	  This supports up to two USB Type-C ports with Dual Role function
+	  (provider and consumer) and Fast Role Swap detection.
+
+config PLATFORM_EC_USB_PD_TCPM_DRIVER_IT8XXX2
+	bool "Enable IT8XXX2 driver"
+	default y
+	select PLATFORM_EC_USB_PD_TCPM_ITE_ON_CHIP
+	depends on DT_HAS_ITE_IT8XXX2_USBPD_ENABLED
+	select PLATFORM_EC_USB_PD_TCPM_TCPCI
+	help
+	  Enable a driver for the ITE IT8XXX2 on-chip UBB Type-C Port Manager.
+	  This supports up to two USB Type-C ports with Dual Role function
+	  (provider and consumer) and Fast Role Swap detection.
+
+config PLATFORM_EC_IT83XX_TUNE_CC_PHY
+	bool "Enable tune cc physical parameters"
+	depends on PLATFORM_EC_USB_PD_TCPM_DRIVER_IT8XXX2
+	help
+	  Enable board to tune cc physical parameters (ex.rising, falling time).
+	  Board must define board_get_cc_tuning_parameter(enum usbpd_port port)
+	  function.
+
+config PLATFORM_EC_USB_PD_PPC
+	bool "Enable Power Path Control from PD"
+	default n
+	help
+	  Some PD chips have integrated SRC FET and control the SRC/SINK FET
+	  from internal GPIOs. Enable this if the Power Path Control is
+	  controlled by the PD chip without EC GPIOs.
+
+config PLATFORM_EC_USB_PD_TCPC_RUNTIME_CONFIG
+	bool "Type-C Port Controller runtime config"
+	default y
+	help
+	  Allows the configuration of the TCPC to be set up at runtime. This
+	  makes the tcpc_config[] array writable, i.e. not const. It should be
+	  declared as such in the board config.
+
+	  This is useful when the board has runtime information that sets
+	  the configuration, such as Chromium OS Board Info (CBI set in the
+	  factory. Without this, multiple EC images would need to be installed
+	  depending on the board.
+
+config PLATFORM_EC_USB_PD_TCPM_ANX7406
+	bool "Analogix ANX7406 USB-C Gen 2 Type-C Port Controller"
+	select PLATFORM_EC_USB_PD_TCPM_TCPCI
+	select PLATFORM_EC_USB_PD_TCPM_MUX
+	help
+	  The Analogix ANX7406 is a USB Type-C Port Controller (TCPC)
+	  for USB Type-C v1.2 Host, USB3.1 Gen2 and DisplayPort applications.
+	  It has an on-chip microcontroller (OCM) to manage the signal
+	  switching. It supports Power Delivery Rev. 3.0 and the DisplayPort
+	  Alt Mode version 1.4a HBR3.
+
+	  Supported chips are:
+	     ANX7406
+
+config PLATFORM_EC_USB_PD_TCPM_ANX7447
+	bool "Analogix ANX7447 USB-C Gen 2 Type-C Port Controller"
+	default y
+	depends on DT_HAS_ANALOGIX_ANX7447_TCPC_ENABLED || \
+		DT_HAS_CROS_ANX7447_TCPC_EMUL_ENABLED
+	select PLATFORM_EC_USB_PD_TCPM_TCPCI
+	select PLATFORM_EC_USB_PD_TCPM_MUX
+	default y if DT_HAS_ANALOGIX_ANX7447_TCPC_ENABLED
+	help
+	  The Analogix ANX7447 is a USB Type-C Port Controller (TCPC)
+	  for USB Type-C v1.2 Host, USB3.1 Gen2 and DisplayPort applications.
+	  It has an on-chip microcontroller (OCM) to manage the signal
+	  switching. It supports Power Delivery Rev. 3.0 and the DisplayPort
+	  Alt Mode version 1.4a HBR3.
+
+	  Supported chips are:
+	     ANX3447
+	     ANX7447
+
+if PLATFORM_EC_USB_PD_TCPM_ANX7447
+config PLATFORM_EC_USB_PD_TCPM_ANX7447_AUX_PU_PD
+	bool "Enable ANX77447 AUX_N internal PU, and AUX_P internal PD."
+	depends on PLATFORM_EC_USB_PD_TCPM_ANX7447
+	help
+	  Use this config option to enable and internal pullup resistor on the
+	  AUX_N and internal pulldown resistor on the AUX_P line. Only use this
+	  config option if there are no external pu/pd resistors on these
+	  signals. This configuration should be used to avoid noise issues on
+	  the DDI1_AUX_N & DDI1_AUX_P signals (b/122873171)
+
+config PLATFORM_EC_USB_PD_TCPM_ANX7447_OCM_ERASE_COMMAND
+	bool "Enable console command to erase ANX7447 OCM flash"
+	depends on PLATFORM_EC_USB_PD_TCPM_ANX7447
+	help
+	  Adds an EC console command to erase the ANX7447 OCM flash.
+	  Note: this is intended to be a temporary option and won't be needed
+	  when ANX7447 are put on boards with OCM already erased
+endif # PLATFORM_EC_USB_PD_TCPM_ANX7447
+
+config PLATFORM_EC_USB_PD_TCPM_FUSB302
+	bool "Fairchild's FUSB302 Type-C port controller with USB PD"
+	default y
+	depends on DT_HAS_FAIRCHILD_FUSB302_ENABLED
+	select PLATFORM_EC_USB_PD_TCPM_TCPCI
+	help
+	  This is a USB Type-C port controller which enables the USB Type-C
+	  detection including attach, and orientation. It integrates the
+	  physical layer of the USB power delivery protocol to allow
+	  up to 100 W of power and role swap. The PD block enables full
+	  support for alternative interfaces of the Type-C specification.
+
+config PLATFORM_EC_USB_PD_TCPM_NCT38XX
+	bool "Nuvoton 3807/8 Single/Dual Port Controller with Power Delivery"
+	default y
+	depends on DT_HAS_NUVOTON_NCT38XX_ENABLED
+	select PLATFORM_EC_USB_PD_TCPM_TCPCI
+	help
+	  The NCT38n7/8 is a single/dual-port, USB Type-C Port Controller
+	  (TCPC). It incorporates a Power Delivery (PD) PHY with BMC encoding,
+	  Protocol logic and USB Type-C Configuration Channel (CC) logic.
+
+config PLATFORM_EC_USB_PD_TCPM_PS8XXX
+	bool
+	select PLATFORM_EC_USB_PD_TCPM_TCPCI
+	select PLATFORM_EC_USB_PD_TCPM_MUX
+	imply PLATFORM_EC_HOSTCMD_I2C_CONTROL
+	help
+	  Enable the driver for PS8xxx active retimer/redrivers with integrated
+	  USB Type-C Port Controller (TCPC) for USB Type-C Host and DisplayPort
+	  applications. They support Power Delivery and the DisplayPort Alt
+	  Mode.
+
+	  Support for specific devices in the driver (below) must also be
+	  enabled.
+
+if PLATFORM_EC_USB_PD_TCPM_PS8XXX
+config PLATFORM_EC_USB_PD_TCPM_MULTI_PS8XXX
+	bool "Support multiple PS8xxx devices"
+	help
+	  PS8XXX-series chips are all supported by a single driver. Enable
+	  this if a board with the same EC firmware is expected to support
+	  multiple products here.
+
+	  In this case the board must provide a function to return the correct
+	  product ID actually used by a particular board:
+
+	     uint16_t board_get_ps8xxx_product_id(int port)
+
+	  Supported return values are:
+
+	     PS8705_PRODUCT_ID
+	     PS8745_PRODUCT_ID
+	     PS8751_PRODUCT_ID
+	     PS8755_PRODUCT_ID
+	     PS8805_PRODUCT_ID
+	     PS8815_PRODUCT_ID
+endif # PLATFORM_EC_USB_PD_TCPM_PS8XXX
+
+config PLATFORM_EC_USB_PD_TCPM_PS8745
+	bool "Parade PS8745 USB-C Gen 2 Type-C Port Controller"
+	select PLATFORM_EC_USB_PD_TCPM_PS8XXX
+	help
+	  The Parade Technologies PS8815 is an active retiming/redriving
+	  (respectively for USB 3.1 Gen 2 / DisplayPort 1.4a HBR3) integrated
+	  with a USB Type-C Port Controller (TCPC) for USB Type-C Host and
+	  DisplayPort applications. It supports Power Delivery and the
+	  DisplayPort Alt Mode.
+
+if PLATFORM_EC_USB_PD_TCPM_PS8745
+config PLATFORM_EC_USB_PD_TCPM_PS8745_FORCE_ID
+	bool "Disambiguate PS8745 and PS8815"
+	default y
+	help
+	  Some firmware versions of the PS8745 report incorrect product and device
+	  IDs. Enable this option to check vendor-specific registers and force the
+	  correct device and product IDs.
+endif # PLATFORM_EC_USB_PD_TCPM_PS8745
+
+config PLATFORM_EC_USB_PD_TCPM_PS8751
+	bool "Parade PS8751 USB-C Gen 2 Type-C Port Controller"
+	select PLATFORM_EC_USB_PD_TCPM_PS8XXX
+	help
+	  The Parade Technologies PS8751 is a USB Type-C Port Controller (TCPC)
+	  for USB Type-C Host and DisplayPort applications. It supports
+	  Power Delivery Rev. 2.0 and the DisplayPort Alt Mode version 1.0a.
+
+config PLATFORM_EC_USB_PD_TCPM_PS8805
+	bool "Parade PS8805 USB-C Gen 2 Type-C Port Controller"
+	select PLATFORM_EC_USB_PD_TCPM_PS8XXX
+	help
+	  The Parade Technologies PS8805 is an active retiming/redriving
+	  (respectively for USB 3.1 Gen 2 / DisplayPort 1.4a HBR3) integrated
+	  with a USB Type-C Port Controller (TCPC) for USB Type-C Host and
+	  DisplayPort applications. It supports Power Delivery and the
+	  DisplayPort Alt Mode.
+
+if PLATFORM_EC_USB_PD_TCPM_PS8805
+config PLATFORM_EC_USB_PD_TCPM_PS8805_FORCE_DID
+	bool "Parade PS8805 Force Device ID"
+	default y
+	help
+	  Early firmware versions of the PS8805 report an incorrect device ID
+	  value for A3 silicon. Enable this option to check the vendor specific
+	  chip version register and force the correct device ID.
+endif # PLATFORM_EC_USB_PD_TCPM_PS8805
+
+config PLATFORM_EC_USB_PD_TCPM_PS8815
+	bool "Parade PS8815 USB-C Gen 2 Type-C Port Controller"
+	select PLATFORM_EC_USB_PD_TCPM_PS8XXX
+	help
+	  The Parade Technologies PS8815 is an active retiming/redriving
+	  (respectively for USB 3.1 Gen 2 / DisplayPort 1.4a HBR3) integrated
+	  with a USB Type-C Port Controller (TCPC) for USB Type-C Host and
+	  DisplayPort applications. It supports Power Delivery and the
+	  DisplayPort Alt Mode.
+
+if PLATFORM_EC_USB_PD_TCPM_PS8815
+config PLATFORM_EC_USB_PD_TCPM_PS8815_FORCE_DID
+	bool "Parade PS8815 Force Device ID"
+	default y
+	help
+	  Early firmware versions of the PS8815 report an incorrect device ID
+	  value for A1 silicon. Enable this option to check the vendor specific
+	  chip version register and force the correct device ID.
+endif # PLATFORM_EC_USB_PD_TCPM_PS8815
+
+config PLATFORM_EC_USB_PD_TCPM_RAA489000
+	bool "Renesas RAA489000 Type-C port controller and battery charger"
+	select PLATFORM_EC_USB_PD_TCPM_TCPCI
+	select PLATFORM_EC_USB_PD_PPC
+	help
+	  Build drivers for the RAA489000, a combined battery charger and USB-C
+	  TCPCI.
+
+if PLATFORM_EC_USB_PD_TCPM_RAA489000
+
+config PLATFORM_EC_RAA489000_OCP_UV_THRESHOLD_MV
+	int "Undervoltage threshold while sourcing VBUS (mV)"
+	default 4750
+	help
+	  Sets the RAA489000 undervoltage theshold when sourcing VBUS, in mV.
+
+	  If VBUS drops below this level while sourcing, the chip disables
+	  sourcing under the assumption that too much current was being drawn.
+	  Rated accuracy of this measurement is 5%, with 25 mV resolution.
+
+endif
+
+config PLATFORM_EC_USB_PD_TCPM_RT1715
+	bool "Richtek RT1715 Type-C Port Controller"
+	default y
+	depends on DT_HAS_RICHTEK_RT1715_TCPC_ENABLED
+	help
+	  The RT1715 is a USB Type-C controller, integrating a complete Type-C
+	  Transceiver including the Rp and Rd resistors. It does the USB Type-C
+	  detection including attach and orientation. The RT1715 integrates the
+	  physical layer of the USB BMC power delivery protocol to allow up to
+	  100W of power and role swap. The BMC PD block enables full support
+	  for alternative interfaces of the Type-C specification. This driver is
+	  also used for RT1716 TCPC.
+
+config PLATFORM_EC_USB_PD_TCPM_RT1718S
+	bool "Richtek RT1718S Type-C Port Controller"
+        default y
+        depends on DT_HAS_RICHTEK_RT1718S_TCPC_ENABLED
+	select PLATFORM_EC_USB_PD_TCPM_TCPCI
+	help
+	  The RT1718S is an integrated USB Type-C TCPC controller which
+	  includes IEC-61000-4-2 ESD protection cell for CC/SBU/DP/DM.
+	  High voltage USB 2.0 switches also support HV DCP & fast charging
+	  protocols. RT1718S supports TCPC Version 1.2, and Battery Charging
+	  version 1.2 (BC1.2).
+
+config PLATFORM_EC_USB_PD_TCPM_TUSB422
+	bool "TI TUSB422 Port Control with USB PD"
+	select PLATFORM_EC_USB_PD_TCPM_TCPCI
+	help
+	  This is a a USB PD PHY that enables a USB Type-C port with the
+	  Configuration Channel (CC) logic needed for USB Type-C ecosystems. It
+	  integrates the physical layer of the USB BMC power delivery (PD)
+	  protocol to allow up to 100-W of power and support for alternate mode
+	  interfaces. An external microprocessor, containing USB Type-C Port
+	  Manager (TCPM), communicates with the TUSB422 through an I2C
+	  interface.
+
+config PLATFORM_EC_USB_PD_TCPM_MUX
+	bool "Support optional register 18h steer the high-speed muxes"
+	help
+	  Enable this option if the TCPC port controller supports the optional
+	  register 18h CONFIG_STANDARD_OUTPUT to steer the high-speed muxes.
+
+	  See section 4.4.4 (CONFIGURE STANDARD OUTPUT) of the USB Type-C Port
+	  Controller Interface Specification, Revision 2.0, Version 1.2 for more
+	  information.
+
+config PLATFORM_EC_USB_PD_TCPM_SBU
+	bool "PD chip has integrated port protection for SBU lines"
+	help
+	  Some PD chips have integrated port protection for SBU lines.
+	  If the switches to enable those SBU lines are controlled by the PD
+	  chip, enable this config.
+
+config PLATFORM_EC_CONSOLE_CMD_TCPC_DUMP
+	bool "Console command: tcpc_dump"
+	# anx7447 also supports this command, but is not yet enabled
+	default y
+	help
+	  Allows dumping of the Type-C Port Controller (TCPC) state, which is
+	  basically a list of registers and their values. By reference to the
+	  Universal Serial Bus Type-C Port Controller Interface Specification
+	  this can help you figure out what is going on.
+
+endif  # PLATFORM_EC_USBC
diff --git a/zephyr/Kconfig.temperature b/zephyr/Kconfig.temperature
new file mode 100644
index 0000000000..7662b0184b
--- /dev/null
+++ b/zephyr/Kconfig.temperature
@@ -0,0 +1,162 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+menuconfig PLATFORM_EC_TEMP_SENSOR
+	bool "Temperature sensors"
+	default y
+	depends on DT_HAS_CROS_EC_TEMP_SENSORS_ENABLED
+	help
+	  Support for temperature sensors. Once enabled, "temps" console
+	  command and EC_CMD_TEMP_SENSOR_GET_INFO host command are available.
+
+if PLATFORM_EC_TEMP_SENSOR
+
+config PLATFORM_EC_TEMP_SENSOR_POWER
+	bool "Temperature sensors are not always powered on"
+	help
+	  If enabled, temperature sensors require enabling power rail before
+	  being read. Enabling it requires to define a pin enabling the power
+	  as GPIO_TEMP_SENSOR_POWER.
+
+config PLATFORM_EC_DPTF
+	bool "Dynamic Platform and Thermal Framework"
+	default y if PLATFORM_EC_ACPI
+	help
+	  Enables the Dynamic Platform and Thermal Framework (DPTF). DPTF
+	  exposes the temperature sensors and the fan controls to the
+	  Applicaiton Processor (AP) using Advanced Configuration and Power
+	  Interface (ACPI). This permits the AP to control thermal management
+	  independent of the EC.
+
+	  Even when DPTF is enabled, the EC still monitors temperature sensors
+	  and will take corrective actions for high temperatures such as turning
+	  on the fans or powering down the AP.
+
+config PLATFORM_EC_THERMISTOR
+	bool "Thermistor support"
+	default y
+	depends on DT_HAS_CROS_EC_THERMISTOR_ENABLED
+	depends on ADC
+	help
+	  Enables support for thermistors (resistor whose resistance is
+	  strongly dependent on temperature) as temperature-sensor type.
+
+config PLATFORM_EC_TEMP_SENSOR_PCT2075
+	bool "PCT2075 support"
+	default y
+	depends on DT_HAS_NXP_PCT2075_ENABLED
+	help
+	  Enables support for the CrosEC PCT2075 sensor, an i2c peripheral
+	  temperature sensor from NXP.
+
+config PLATFORM_EC_TEMP_SENSOR_SB_TSI
+	bool "SB TSI support"
+	default y
+	depends on DT_HAS_AMD_SB_TSI_ENABLED
+	help
+	  Enables support for the Side Band Temperature Sensor Interface,
+	  an i2c peripheral available on AMD platforms.
+
+config PLATFORM_EC_TEMP_SENSOR_TMP112
+	bool "TMP112 support"
+	default y
+	depends on DT_HAS_CROS_EC_TEMP_SENSOR_TMP112_ENABLED
+	help
+	  Enables support for the CrosEC TMP112 driver, an i2c peripheral
+	  temperature sensor from TI.
+
+config PLATFORM_EC_TEMP_SENSOR_F75303
+	bool "F75303 support"
+	default y
+	depends on DT_HAS_CROS_EC_TEMP_SENSOR_F75303_ENABLED
+	help
+	  Enables support for the CrosEC F75303 driver, an i2c peripheral
+	  temperature sensor from TI.
+
+config PLATFORM_EC_TEMP_SENSOR_AMD_R23M
+	bool "AMD R23M support"
+	default y
+	depends on DT_HAS_CROS_EC_TEMP_SENSOR_AMDR23M_ENABLED
+	help
+	  Enables support for the CrosEC AMD R23M driver, an i2c peripheral
+	  temperature sensor from AMD.
+
+endif # PLATFORM_EC_TEMP_SENSOR
+
+
+config PLATFORM_EC_TEMP_SENSOR_FIRST_READ_DELAY
+	bool "Enable a delay before reading temperature seensors"
+	help
+	  Enables a delay on the first read of temperature sensors after
+	  the EC powers on. This allows for setting of any power rails that
+	  control the temperature sensors on the platform.
+
+if PLATFORM_EC_TEMP_SENSOR_FIRST_READ_DELAY
+
+config PLATFORM_EC_TEMP_SENSOR_FIRST_READ_DELAY_MS
+	int "Temperature sensor read delay time"
+	default 500
+	help
+	  Sets the delay time, in milliseconds, before the first the EC will
+	  read any temperature sensors and perform any thermal management.
+
+endif # PLATFORM_EC_TEMP_SENSOR_FIRST_READ_DELAY
+
+config PLATFORM_EC_FAN
+	bool "Fan support"
+	default y
+	depends on DT_HAS_CROS_EC_FANS_ENABLED
+	select PWM
+	select SENSOR
+	help
+	  Enables support for fans. Allows periodic thermal task to
+	  automatically set the fan speed (control temperature).
+	  Once enabled fanduty, fanset, faninfo, fanauto consol command and
+	  EC_CMD_PWM_GET_FAN_TARGET_RPM, EC_CMD_PWM_SET_FAN_TARGET_RPM,
+	  EC_CMD_PWM_SET_FAN_DUTY, EC_CMD_THERMAL_AUTO_FAN_CTRL are
+	  available. Also enables a periodic task (1s) to verify fan is
+	  running (is not stalled).
+
+if PLATFORM_EC_FAN
+
+config PLATFORM_EC_CUSTOM_FAN_CONTROL
+	bool "Fan custom control support"
+	default n
+	help
+	  Enable fan custom control to let projects define
+	  their own fan control mechanism by EC.
+
+config PLATFORM_EC_CUSTOM_FAN_DUTY_CONTROL
+	bool "Fan custom control support"
+	default n
+	help
+	  Enable fan duty custom control to let projects define
+	  their own fan duty control mechanism by implementing
+	  the routine board_override_fan_control_duty().
+
+
+config PLATFORM_EC_NUM_FANS
+	int "Number of fans"
+	default 1
+	help
+	  Declare the number of fans supported on this board and avilable
+	  for control through fan APIs.
+
+config PLATFORM_EC_FAN_RPM_CUSTOM
+	bool "Fan rpm custom control suuport"
+	default n
+	help
+	  Replace the default fan_percent_to_rpm() function with a board-specific
+	  implementation in board.c
+
+endif # PLATFORM_EC_FAN
+
+config PLATFORM_EC_FAN_BYPASS_SLOW_RESPONSE
+	bool "Enable fan slow response control mechanism"
+	default n
+	help
+	  A specific type of fan needs a longer time to output the TACH
+	  signal to EC after EC outputs the PWM signal to the fan.
+	  During this period, the driver will read two consecutive RPM = 0.
+	  In this case, don't step the PWM duty too aggressively.
diff --git a/zephyr/Kconfig.throttle_ap b/zephyr/Kconfig.throttle_ap
new file mode 100644
index 0000000000..90849aa81f
--- /dev/null
+++ b/zephyr/Kconfig.throttle_ap
@@ -0,0 +1,57 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if PLATFORM_EC_THROTTLE_AP
+
+config PLATFORM_EC_CHIPSET_CAN_THROTTLE
+	bool "CPU can support throttling"
+	default y
+	help
+	  Indicates that the SoC supports throttling. This means that a
+	  chipset_throttle_cpu() function is provided by the chipset, to be
+	  called to set the throttle state. The typical implementation asserts
+	  GPIO_CPU_PROCHOT, to make the CPU slow down.
+
+config PLATFORM_EC_CONSOLE_CMD_APTHROTTLE
+	bool "Console command: apthrottle"
+	default y
+	help
+	  This command shows the current status of AP throttling. Both soft
+	  (type 0) and hard (type 1) throttling are supported. Soft throttling
+	  is typically controlled by the AP via a host event. Hard throttling
+	  typically uses the PROCHOT (Processor Hot) signal on x86 CPUs.
+
+	  Example output:
+
+	     AP throttling type 0 is off (0x00000000)
+	     AP throttling type 1 is off (0x00000000)
+
+config PLATFORM_EC_THROTTLE_AP_ON_BAT_DISCHG_CURRENT
+	bool "Throttle AP based on battery discharge current"
+	default n
+	help
+	  Throttle the CPU when battery discharge current is too high. When
+	  this feature is enabled, the threshold value must be set in
+	  PLATFORM_EC_THROTTLE_AP_ON_BAT_DISCHG_CURRENT_LIMIT.
+
+config PLATFORM_EC_THROTTLE_AP_ON_BAT_LOW_VOLTAGE
+	bool "Throttle AP based on battery voltage"
+	default n
+	help
+	  Throttle the CPU when battery voltage drops below a defined threshold
+	  where the board still boots but some components don't function
+	  perfectly. When this feature is enabled, the threshold value must be
+	  set in PLATFORM_EC_THROTTLE_AP_ON_BAT_LOW_VOLTAGE_THRESH.
+
+config PLATFORM_EC_GPU_NVIDIA
+	bool "Nvidia GPU supports throttling"
+	default n
+	help
+	  Enable GPU throttling. When the GPU is throttled, a software (D-Notify)
+	  and a hardware throttle (GPIO_NVIDIA_GPU_ACOFF_ODL) are enabled. A
+	  hardware throttle will be automatically disabled after a fixed period
+	  of time but a software throttle may remain and keep changing as the
+	  situation changes.
+
+endif # PLATFORM_EC_THROTTLE_AP
diff --git a/zephyr/Kconfig.timer b/zephyr/Kconfig.timer
new file mode 100644
index 0000000000..0e19f2d551
--- /dev/null
+++ b/zephyr/Kconfig.timer
@@ -0,0 +1,50 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if PLATFORM_EC_TIMER
+
+config PLATFORM_EC_CONSOLE_CMD_GETTIME
+	bool "Console command: gettime"
+	default y
+	help
+	  Enable the "gettime" command. This shows the current time (in
+	  microseconds since boot) in both hex and in decimal converted to
+	  seconds. For example:
+
+	     Time: 0x0000000002706a62 = 40.921698 s
+
+
+config PLATFORM_EC_CONSOLE_CMD_TIMERINFO
+	bool "Console command: timerinfo"
+	default y
+	help
+	  Enable the "timerinfo" command which shows the current time (in
+	  microseconds and seconds since boot), the deadline (next time the EC
+	  needs to wake up) and a list of active timers along with when they
+	  will next fire.
+
+	  Example:
+
+	    Time:     0x0000000002706a62 us,   40.921698 s
+	    Deadline: 0x000000000270774d ->    0.003307 s from now
+	    Active timers:
+	      Tsk  1  0x000000000271db8f ->    0.094509
+	      Tsk  4  0x00000000027396b3 ->    0.207953
+	      Tsk 13  0x00000000027133a1 ->    0.051519
+
+
+config PLATFORM_EC_CONSOLE_CMD_WAITMS
+	bool "Console command: waitms"
+	default y
+	help
+	  Enable the "waitms" command. This waits for a given number of
+	  milliseconds. For example:
+
+	    waitms 100
+
+	  waits for 100ms. Note that long waits can introduce problems since
+	  it stops the EC from executing its normal tasks. For example, a
+	  two-second wait can cause the EC to reset.
+
+endif # PLATFORM_EC_TIMER
diff --git a/zephyr/Kconfig.touchpad b/zephyr/Kconfig.touchpad
new file mode 100644
index 0000000000..2f3e804898
--- /dev/null
+++ b/zephyr/Kconfig.touchpad
@@ -0,0 +1,19 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config PLATFORM_EC_TOUCHPAD
+	bool "Touchpad support"
+	select HAS_TASK_TOUCHPAD
+	help
+	  Enable touchpad support. Enabling this automatically enables
+	  HAS_TASK_TOUCHPAD to have a dedicated task for touchpad data
+	  pipeline.
+
+	  Must pick a driver from the options below.
+
+config PLATFORM_EC_TOUCHPAD_ELAN
+	bool "Elan touchpad driver"
+	select PLATFORM_EC_TOUCHPAD
+	help
+	  Adds support for Elan I2C touchpad.
diff --git a/zephyr/Kconfig.usb_charger b/zephyr/Kconfig.usb_charger
new file mode 100644
index 0000000000..ab0d4665fa
--- /dev/null
+++ b/zephyr/Kconfig.usb_charger
@@ -0,0 +1,109 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if PLATFORM_EC_USBC
+
+config PLATFORM_EC_USB_CHARGER
+	bool "Support charging from a USB-C port"
+	default y
+	help
+	  This enables common BC1.2 (Battery-Charging Specification Rev1.2)
+	  charger-detection routines. With this is possible to negotiate a
+	  power contract with an attached battery charger and use this to
+	  charge the device's battery.
+
+if PLATFORM_EC_USB_CHARGER
+
+config PLATFORM_EC_USB_CHARGER_SINGLE_TASK
+	bool
+	default y
+	help
+	  Helper symbol use in the common EC code for Zephyr specific charger
+	  changes.
+
+
+config PLATFORM_EC_BC12_DETECT_DATA_ROLE_TRIGGER
+	bool
+	help
+	  This is a helper symbol that indicates the BC1.2 chip needs to be
+	  triggered on data role swaps in addition to VBUS changes.
+
+config PLATFORM_EC_BC12_DETECT_RT1718S
+	bool "Enable support for BC 1.2 detection on the RT1718S"
+	depends on DT_HAS_RICHTEK_RT1718S_BC12_ENABLED && PLATFORM_EC_USB_PD_TCPM_RT1718S
+	default y
+	help
+	   This enables the BC 1.2 detection on the highly-integrated RT1718S
+	   chip.  Note this chip also functions as a TCPC and a PPC. While the
+	   TCPC may be enabled without the BC 1.2 detection, the BC 1.2
+	   detection module is currently dependent on the TCPC existing.
+
+config PLATFORM_EC_BC12_DETECT_RT9490
+	bool "Enable BC 1.2 detection on the RT9490"
+	default y
+	depends on DT_HAS_RICHTEK_RT9490_ENABLED || DT_HAS_ZEPHYR_RT9490_EMUL_ENABLED
+	depends on PLATFORM_EC_I2C
+	help
+	   This enables the BC 1.2 detection on the R9490 charging chip.
+	   Note this chip provides both charging and BC1.2 detection
+	   capabilities. While the charger may be enabled without the BC 1.2
+	   detection, the BC 1.2 detection module is currently dependent on the
+	   charger existing.
+
+config PLATFORM_EC_BC12_CLIENT_MODE_ONLY_PI3USB9201
+	bool "Run as BC1.2 client while using PI3USB9201"
+	depends on PLATFORM_EC_BC12_DETECT_PI3USB9201
+	default n
+	help
+	  This is a helper symbol that indicates the PI3USB9201 will only
+	  advertise itself as a BC1.2 client, not a BC1.2 host.
+
+config PLATFORM_EC_BC12_DETECT_PI3USB9201
+	bool "Enable support for Pericom PI3USB9201"
+	default y
+	depends on DT_HAS_PERICOM_PI3USB9201_ENABLED || DT_HAS_ZEPHYR_PI3USB9201_EMUL_ENABLED
+	select PLATFORM_EC_BC12_DETECT_DATA_ROLE_TRIGGER
+	help
+	  This is a Dual-Role USB Charging-Type Detector. It can operate in
+	  host or client mode. It supports Battery Charging Specification, rev
+	  1.2 (BC1.2) with Standard/Charging/Dedicated downstream port
+	  (SDP/CDP/DCP) advertisement when in host mode. In client mode it
+	  starts BC1.2 detection to detect the attached host type. It provides
+	  an I2C interface to report detection results.
+
+config PLATFORM_EC_BC12_DETECT_MT6360
+	bool "MediaTek MT6360P PMIC"
+	help
+	  This PMIC includes a battery charger with an On-The-Go (OTG) output
+	  range of 4.85 to 5.825V. It provides integrated ADCs for system
+	  monitoring. The MT6360 also supports USB Power Delivery 3.0 with
+	  Dual-Role, with host or client mode. It supports alternate mode as
+	  well as VCONN with programmable over-current protection (OCP).
+
+config PLATFORM_EC_MT6360_BC12_GPIO
+	bool "USB-PHY connection is controlled by a GPIO"
+	depends on PLATFORM_EC_BC12_DETECT_MT6360
+	help
+	  If enabled, the MT6360 USB-PHY connection is controlled by
+	  a GPIO: GPIO_BC12_DET_EN. Assert GPIO_BC12_DET_EN to detect a BC1.2
+	  device, and deassert GPIO_BC12_DET_EN to mux the USB-PHY back.
+
+config PLATFORM_EC_BC12_SINGLE_DRIVER
+	bool "Only support a single BC12 driver"
+	default y
+	help
+	  Enable this if the board only needs one BC12 driver. This includes
+	  the case that has multiple chips that use the same driver.
+
+	  If undefined, the board should define a bc12_ports[] array which
+	  associates each port to its bc12 driver:
+
+	     struct bc12_config bc12_ports[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	        { .drv = &xxx_drv },
+	        { .drv = &yyy_drv },
+	     };
+
+endif  # PLATFORM_EC_USB_CHARGER
+
+endif # PLATFORM_EC_USBC
diff --git a/zephyr/Kconfig.usb_mux b/zephyr/Kconfig.usb_mux
new file mode 100644
index 0000000000..4af8caa545
--- /dev/null
+++ b/zephyr/Kconfig.usb_mux
@@ -0,0 +1,103 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if PLATFORM_EC_USBC
+
+menuconfig PLATFORM_EC_USB_MUX
+	bool "USB muxes"
+	default y
+	depends on DT_HAS_CROS_EC_USB_MUX_CHAIN_ENABLED
+	help
+	  Enables support for USB muxes. These allow multiplexing
+
+if PLATFORM_EC_USB_MUX
+
+config PLATFORM_EC_USB_MUX_TASK
+	bool "Run mux set operations in a dedicated thread"
+	default n
+	help
+	  Run a dedicated task to process USB mux sets and HPD, which avoids
+	  blocking the PD task on mux updates. This is useful if a mux is slow
+	  to update, since blocking PD handling during mux operations can cause
+	  timing violations.
+
+config TASK_USB_MUX_STACK_SIZE
+	int "USB mux task stack size"
+	depends on PLATFORM_EC_USB_MUX_TASK
+	default 1024
+	help
+	  Set the size of the USB mux task stack, in bytes.
+
+config PLATFORM_EC_USB_MUX_AP_CONTROL
+	bool "AP USB mux control"
+	depends on PLATFORM_EC_USB_MUX_TASK
+	help
+	  Allows the AP to send commands in order to control any muxes and
+	  retimers for the board.
+
+config PLATFORM_EC_USB_MUX_AMD_FP6
+	bool "AMD FP6 integrated mux"
+	default y
+	depends on DT_HAS_AMD_USBC_MUX_AMD_FP6_ENABLED
+	help
+	  Integrated AMD FP6 mux for USB and DP.  Mux control happens over
+	  an i2c channel.
+
+config PLATFORM_EC_USB_MUX_IT5205
+	bool "ITE IT5205 USB Type-C 3:2 Alternative mode passive mux"
+	default y
+	depends on DT_HAS_ITE_IT5205_ENABLED
+	help
+	  This is a USB Type-C 3:2 Alternative mode mux, supporting USB 3.1
+	  Gen 2 10Gbps as well as DisplayPort (DP1.4) at 8Gbps. It provides a
+	  cross-point mux for low-speed Side-Band-Use (SBU) pins. The mux can
+	  be controlled via I2C.
+
+config PLATFORM_EC_USB_MUX_PS8743
+	bool "Parade PS8743 USB-C Host Switch with redriver"
+	default y
+	depends on DT_HAS_PARADE_PS8743_ENABLED || DT_HAS_ZEPHYR_PS8743_EMUL_ENABLED
+	help
+	  This is a Parade USB 3.1 Gen 1 / DisplayPort (DP) Alt Mode
+	  High-Bit-Rate 2 (HBR2) redriver. It provides control of switching
+	  modes through either GPIO or I2C.
+
+choice PLATFORM_EC_USB_MUX_TUSB_TYPE
+	prompt "Select the TUSB USB-C Redriver type"
+	default PLATFORM_EC_USB_MUX_TUSB1064 if DT_HAS_TI_TUSB1064_ENABLED
+	default PLATFORM_EC_USB_MUX_TUSB1064 if DT_HAS_ZEPHYR_TUSB1064_EMUL_ENABLED
+	help
+	  There are three supported types of TUSB USB-C Redriver: TUSB546,
+	  TUSB1044, and TUSB1064.
+
+config PLATFORM_EC_USB_MUX_TUSB_NONE
+	bool "None"
+	help
+	  Default option if the board doesn't contain any model of TUSB family.
+
+config PLATFORM_EC_USB_MUX_TUSB546
+	bool "TI TUSB546 USB-C DP ALT Mode Linear Redriver Crosspoint Switch"
+	help
+	  This is a USB Type-C Alt Mode redriving switch supporting USB 3.1 data
+	  rates up to 5 Gbps and DisplayPort 1.4 up to 8.1 Gbps for downstream
+	  facing port.
+
+config PLATFORM_EC_USB_MUX_TUSB1044
+	bool "TI TUSB1044 USB-C 10 Gbps Linear Redriver"
+	help
+	  This is a USB Type-C Alt Mode redriver. This supports USB 3.1
+	  Gen 2 and DisplayPort 1.4 as Alternate Mode. It Provides GPIO and
+	  I2C Control for Channel Direction and Equalization.
+
+config PLATFORM_EC_USB_MUX_TUSB1064
+	bool "TI TUSB1064 USB-C 10 Gbps Linear Redriver"
+	help
+	  This is a USB Type-C Alt Mode redriver. This supports USB 3.1
+	  Gen 2 and DisplayPort 1.4.
+
+endchoice # PLATFORM_EC_USB_MUX_TUSB_TYPE
+
+endif # PLATFORM_EC_USB_MUX
+
+endif # PLATFORM_EC_USBC
diff --git a/zephyr/Kconfig.usba b/zephyr/Kconfig.usba
new file mode 100644
index 0000000000..b5413d2c83
--- /dev/null
+++ b/zephyr/Kconfig.usba
@@ -0,0 +1,112 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+menuconfig PLATFORM_EC_USBA
+	bool "USB Type-A support"
+	default y
+	depends on DT_HAS_CROS_EC_USBA_PORT_ENABLE_PINS_ENABLED
+	help
+	  Enable USB Type A ports
+
+	  To use this your board code must provide a usb_port_enable[] array
+	  with the GPIOs to use for each port, which may be specified via
+	  device tree with "cros-ec,usba-port-enable-pins" nodes. This
+	  implements the EC_CMD_USB_CHARGE_SET_MODE host command and provides
+	  a 'usbchargemode' console command.
+
+if PLATFORM_EC_USBA
+
+config PLATFORM_EC_USB_PORT_ENABLE_DYNAMIC
+	bool "USB Type-A dynamic port count"
+	help
+	  Allow the USB Type-A port array to be dynamically
+	  modified by board specific code.
+
+	  This allows boards to selectively disable any of the
+	  USB Type-A ports by setting the enable entry to
+	  a negative value.
+
+choice PLATFORM_EC_USBA_PORT_POWER_TYPE
+	prompt "Port power control mode"
+	default PLATFORM_EC_USB_PORT_POWER_DUMB
+
+config PLATFORM_EC_USB_PORT_POWER_DUMB
+	bool "Dumb"
+	help
+	  USB-A ports are controlled with a single GPIO each, where turning it
+	  on enables the port and turning it off disables the port.
+
+config PLATFORM_EC_USB_PORT_POWER_SMART
+	bool "Smart"
+	help
+	  USB-A ports are controlled via a smart switch, which allows dynamic
+	  selection of port current limits and BC1.2 charging modes as well
+	  as a signal to enable or disable power to the port.
+
+endchoice
+
+config PLATFORM_EC_USB_PORT_POWER_DUMB_CUSTOM_HOOK
+	bool "Disable default dumb port power hooks"
+	depends on PLATFORM_EC_USB_PORT_POWER_DUMB
+	help
+	  Enable this if your board does not want to use the default S3 hooks
+	  from USB_PORT_POWER_DUMB.
+
+if PLATFORM_EC_USB_PORT_POWER_SMART
+
+config PLATFORM_EC_USB_PORT_POWER_SMART_CDP_SDP_ONLY
+	bool "CDP/SDP mode only"
+	help
+	  Enable this if the USB-A smart switch mode selection is fixed and
+	  the only control is for CDP or SDP mode via current limit selection.
+	  Only the ILIM GPIOs will be controlled, not CTL*.
+
+config PLATFORM_EC_USB_PORT_POWER_SMART_SIMPLE
+	bool "Shared 2-wire control"
+	depends on !PLATFORM_EC_USB_PORT_POWER_SMART_CDP_SDP_ONLY
+	select PLATFORM_EC_USB_PORT_POWER_SMART_INVERTED
+	help
+	  Enable this if the EC has a single GPIO tied to the CTL1 line and a
+	  single ILIM signal, each shared with every USB-A port. This implies
+	  that only these lines can be manipulated (CTL2 and CTL3 are fixed in
+	  hardware) and that any configuration to one port will also adjust the
+	  others.
+
+	  If disabled, the EC controls all of ILIM and CTL1 through CTL3 for
+	  every port individually.
+
+config PLATFORM_EC_USB_PORT_POWER_SMART_INVERTED
+	bool "ILIM signal polarity is inverted"
+	help
+	  Select this option if the ILIM signal going to the port controller(s)
+	  is inverted, meaning a low value indicates a high current limit and a
+	  high value requests a low current limit.
+
+choice PLATFORM_EC_USBA_PORT_POWER_SMART_DEFAULT_MODE
+	prompt "Port power smart charging default mode"
+	default PLATFORM_EC_USB_PORT_POWER_SMART_DEFAULT_SDP
+
+config PLATFORM_EC_USB_PORT_POWER_SMART_DEFAULT_DISABLED
+	bool "Disabled"
+	help
+	  USB-A ports charging mode default set to disabled.
+	  If set, the USB-A charging mode is disabled.
+
+config PLATFORM_EC_USB_PORT_POWER_SMART_DEFAULT_SDP
+	bool "SDP"
+	help
+	  USB-A ports charging mode default set to Standard Downstream
+	  Port, USB 2.0 mode.
+
+config PLATFORM_EC_USB_PORT_POWER_SMART_DEFAULT_CDP
+	bool "CDP"
+	help
+	  USB-A ports charging mode default set to Charging Downstream
+	  Port, BC 1.2.
+
+endchoice
+
+endif # PLATFORM_EC_USB_PORT_POWER_SMART
+
+endif # PLATFORM_EC_USBA
diff --git a/zephyr/Kconfig.usbc b/zephyr/Kconfig.usbc
new file mode 100644
index 0000000000..7f653ff599
--- /dev/null
+++ b/zephyr/Kconfig.usbc
@@ -0,0 +1,307 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+menuconfig PLATFORM_EC_USBC
+	bool "USB Type-C"
+	default y if PLATFORM_EC_BATTERY
+	depends on PLATFORM_EC_MATH_UTIL
+	help
+	  Enable this to support various USB Type-C features chosen by the
+	  options below. USB-C is widely used on modern Chromebooks and the EC's
+	  role is to negotiate power contracts (for sourcing or sinking power
+	  over USB). The EC is also responsible for discovering the capabilities
+	  of attached USB-C partners and enabling alternate operational modes,
+	  including Display Port, Thunderbolt, and USB4.
+
+config TEST_DISABLE_PLATFORM_EC_USBC
+	bool "Test disable USB type-C"
+	depends on ZTEST && !PLATFORM_EC_USBC
+	help
+	  Use this config to allow tests for code that doesn't actually rely on
+	  USBC.
+
+rsource "Kconfig.retimer"
+rsource "Kconfig.pd_int_shared"
+rsource "Kconfig.pd_meas_vbus"
+rsource "Kconfig.pd_frs"
+rsource "Kconfig.pd_discharge"
+rsource "Kconfig.pd_vbus_detection"
+rsource "Kconfig.pd_console_cmd"
+rsource "Kconfig.pd_usbc_device_type"
+rsource "Kconfig.pd"
+rsource "Kconfig.ppc"
+rsource "Kconfig.usb_mux"
+rsource "Kconfig.usbc_ss_mux"
+rsource "Kconfig.tcpm"
+rsource "Kconfig.usb_charger"
+
+# if PLATFORM_EC_USBC
+
+config PLATFORM_EC_TCPC_INTERRUPT
+	bool "Enables tcpc driver"
+	default y
+	help
+	  By default, the tcpc driver is automatically enabled and will
+	  initialize using the devicetree configs. Disable to stop tcpc
+	  interrupt callbacks from being generated and save space on flash if a
+	  custom driver is used instead.
+
+config PLATFORM_EC_CHARGER_DEFAULT_CURRENT_LIMIT
+	int "Charger input current in mA"
+	depends on PLATFORM_EC_CHARGE_MANAGER
+	default 512
+	help
+	  Default input current limit for the board in mA.
+
+	  This value should depend on external power adapter, designed charging
+	  voltage, and the maximum power of the running system. For type-C
+	  chargers, this should be set to no more than 512 mA in order to not
+	  brown-out low-current USB charge ports in accordance with USB-PD r3.0
+	  Sec. 7.3.
+
+config PLATFORM_EC_CHARGER_MIN_INPUT_CURRENT_LIMIT
+	int "Minimum charger input current limit in mA"
+	default 0
+	depends on PLATFORM_EC_CHARGE_MANAGER
+	help
+	  Minimum current limit in mA that will ever be set for chargers, even if a
+	  lower limit is requested.
+
+	  If set, this should usually be set to no more than 2.5W divided by the
+	  maximum supported input voltage in order to satisfy USB-PD pSnkStdby
+	  requirements. Higher values may help devices stay alive under low-battery
+	  conditions at the cost of violating standby power limits.
+
+	  Many boards set this to large values, since historically this number was
+	  usually equal to the default current limit. New boards should avoid doing
+	  so if possible, and usually leave this unset: customization of
+	  board_set_charge_limit() should be considered instead if a device sometimes
+	  requires amounts of power in violation of specs, to limit those violations
+	  only to situations where they are necessary.
+
+config PLATFORM_EC_CHARGER_INPUT_CURRENT_DERATE_PCT
+	int "Charger input current derating percentage"
+	default 5
+	depends on PLATFORM_EC_CHARGE_MANAGER
+	help
+	  Setting this to a nonzero value causes actual charger current limits
+	  to be adjusted by the given percentage. For example, setting this to
+	  4 and requesting a current limit of 1000 mA causes the charge manager
+	  to program an actual current limit of 960 mA.
+
+	  This is useful if a charger consistently draws more current than the
+	  programmed limit, or if it is desired to derate for other
+	  safety-related reasons. If a more complex (non-linear) adjustment is
+	  required, boards should override the board_set_charge_limit()
+	  function instead of configuring this option.
+
+	  The default value is set to prevent most overcurrent conditions during
+	  load transients, because power supplies vary in their tolerance to
+	  such short-lived overcurrent conditions and many chargers respond
+	  slowly to those transients.
+
+	  Projects SHOULD characterize system behavior to tune for system
+	  behavior and charger response in order to optimize this (allowing the
+	  derating to be reduced) and ensure transients do not exceed the range
+	  of acceptable current (which might require greater derating).
+
+config PLATFORM_EC_USB_PD_PULLUP
+	int "Default source Rp value"
+	default 1
+	help
+	  Default pull-up value on the USB-C ports when they are used as source.
+	  Valid values are 0 (USB default current), 1 (1.5A), and 2 (3.0A). See
+	  enum tcpc_rp_value.
+
+if PLATFORM_EC_USBC
+
+config PLATFORM_EC_USBC_OCP
+	bool
+	help
+	  USB-C overcurrent protection: Enable this to detect when a connected
+	  USB-C partner draws too much power from the Chromebook and
+	  automatically shut off power to the USB-C partner.
+
+	  This should be enabled by drivers which can detect over-current. It
+	  cannot be set otherwise, even in prj.conf
+
+config PLATFORM_EC_USB_PID
+	hex "USB Product ID"
+	default 0
+	help
+	  Each platform (e.g. baseboard set) should have a single VID/PID
+	  combination. If there is a big enough change within a platform,
+	  then we can differentiate USB topologies by varying the hardware
+	  version field in the Sink and Source Capabilities Extended messages.
+
+	  To reserve a new PID within Google, use go/usb and see
+	  http://google3/hardware/standards/usb
+
+config PLATFORM_EC_USB_BCD_DEV
+	hex "USB Device ID"
+	default 0
+	help
+	  This specifies the USB device version, reported by board when acting
+	  as the upstream facing port (UFP). This is a 16-bit unsigned integer
+	  and should be set to a version number relevant to the release version
+	  of the product.
+
+config PLATFORM_EC_USB_VID
+	hex "USB Vendor ID"
+	default 0x18d1
+	help
+	  This specifies the USB vendor ID used for boards which expose a
+	  USB endpont when the port is in UFP mode. The default value is
+	  set to Google's assigned VID and typically would not need to be
+	  changed. But, in certain cases this may need to be changed to
+	  match an OEM's vendor ID.
+
+config PLATFORM_EC_USB_MS_EXTENDED_COMPAT_ID_DESCRIPTOR
+	bool "USB MS Extended Compat ID Feature Descriptor"
+	help
+	  This enables USB-EP to contain a MS Windows USB string descriptor
+	  which is then used by MS Windows to request a Extended Compatible
+	  ID Feature descriptor so that Windows will know to load its WINUSB
+	  driver.
+
+config PLATFORM_EC_USB_PD_TCPC_LOW_POWER
+	bool "Allow Type-C Port Controller to enter low-power mode"
+	default y
+	help
+	  Allows entry to a low power mode when the USB port is idle.
+	  When enabled, an enter_low_power_mode member is present in tcpm_drv
+	  and should be set to a function that selects that mode, such as
+	  tcpci_enter_low_power_mode() for TCPCI-compatible TCPCs.
+
+config PLATFORM_EC_USB_PD_TCPC_LPM_EXIT_DEBOUNCE_US
+	int "Debounce delay when exiting low-power mode (uS)"
+	depends on PLATFORM_EC_USB_PD_TCPC_LOW_POWER
+	default 25000
+	help
+	  Some TCPCs need additional time following a VBUS change to internally
+	  debounce the CC line status and update the CC_STATUS register. This
+	  is the delay in microseconds to allow before checking the CC line
+	  status in the EC.
+
+config PLATFORM_EC_USB_PD_TCPC_VCONN
+	bool "If VCONN is enabled, the TCPC will provide VCONN"
+	default y if !PLATFORM_EC_USBC_PPC_SYV682X
+	default y if PLATFORM_EC_USB_PD_TCPM_ITE_ON_CHIP
+	default y if PLATFORM_EC_USBC_PPC_SYV682X_NO_CC
+	help
+	  Source USB Type-C connector voltage (VCONN) from the Type-C Port
+	  Controller (TCPC), and also the Power Path Controller (PPC) if
+	  present. Some TCPC/PPC can't handle 5V on its host-side CC pins, so
+          disable this config in those cases.
+
+config PLATFORM_EC_USB_PD_CLEAR_HARD_RESET_STATUS
+	bool "Clear PD hard reset status when PD setup completes"
+	default y if SOC_SERIES_RISCV32_IT8XXX2
+	help
+	  Enabling this config will clear the Hard Reset event status
+	  after the PD connection is finished initialization,
+	  to avoid the AP getting a stale event notification.
+
+	  The detection of a PD Hard Reset sets an status flag that
+	  is then read by the AP in order to reset the USB muxes.
+	  However by the time this is read, the connection may
+	  have been re-initialized and is ready, but the AP may
+	  process the hard reset as if it were still current,
+	  causing the USB port to be incorrectly disabled.
+	  The hard reset of the PD connection can be triggered
+	  when the EC is detected as being initially powered on
+	  (as opposed to being reset), to force clearing the connection.
+
+	  This config is set by default for the IT8XXX2 EC, which
+	  cannot distinguish between a reset and power-on, so a power-on
+	  is assumed, which leads to the PD hard reset when the EC
+	  undergoes a reset (such as when entering recovery mode).
+
+config PLATFORM_EC_CONSOLE_CMD_PPC_DUMP
+	bool "Console command: ppc_dump"
+	depends on PLATFORM_EC_USBC_PPC
+	default y
+	help
+	  Allows dumping of the Power Path Controller (PPC) state, which is
+	  basically a list of registers and their values. The actual dump
+	  function is driver-specific (the reg_dump member of ppc_drv). By
+	  reference to the datasheet for the part this can help you figure out
+	  what is going on.
+
+config PLATFORM_EC_USBC_PPC_LOGGING
+	bool "Enable PPC Related logging"
+	depends on PLATFORM_EC_USBC_PPC
+	default y
+	help
+	  PPC drivers use two print functions for logging error messages
+	  (ppc_prints and ppc_err_prints). Setting this config adds the
+	  CPRINTS call to both of these function which will enable PPC
+	  related logging but increase EC image size.
+
+config PLATFORM_EC_USB_PD_PULLUP
+	int "Default source Rp value"
+	default 1
+	help
+	  Default pull-up value on the USB-C ports when they are used as source.
+	  Valid values are 0 (USB default current), 1 (1.5A), and 2 (3.0A). See
+	  enum tcpc_rp_value.
+
+config PLATFORM_EC_USB_PD_ONLY_FIXED_PDOS
+	bool "Only support FIXED type PDOs"
+	help
+	  Ignore all non-fixed PDOs received from a src_caps message. Enable
+	  this for boards (like servo_v4) which only support FIXED PDO types.
+
+# Define power related settings here for now to allow projects to overwrite
+# them. Ideally they would be defined in the devicetree.
+config PLATFORM_EC_PD_OPERATING_POWER_MW
+	int "PD operating power in milliwatt"
+	default 15000
+	help
+	  Base configuration for PD power operating power value, which is used
+	  in PD negotiation. The final PD parameter used in negotiation is
+	  affected by PLATFORM_EC_PD_MAX_POWER_MW,
+	  PLATFORM_EC_PD_MAX_CURRENT_MA, and PLATFORM_EC_PD_MAX_VOLTAGE_MV.
+	  Increase this value is the system requires more than 15 watts to boot
+	  without a battery.
+
+config PLATFORM_EC_PD_MAX_POWER_MW
+	int "PD maximum power in milliwatt"
+	default 60000
+	help
+	  The maximum PD negotiated power for the system. The value should match
+	  with configured PLATFORM_EC_PD_MAX_CURRENT_MA and
+	  PLATFORM_EC_PD_MAX_VOLTAGE_MV.
+
+config PLATFORM_EC_PD_MAX_CURRENT_MA
+	int "PD maximum current in milliampere"
+	default 3000
+	help
+	  The maximum PD negotiated current for the system. The value should
+	  match with configured PLATFORM_EC_PD_MAX_POWER_MW and
+	  PLATFORM_EC_PD_MAX_VOLTAGE_MV.
+
+config PLATFORM_EC_PD_MAX_VOLTAGE_MV
+	int "PD maximum voltage in millivolt"
+	default 20000
+	help
+	  The maximum PD negotiated voltage for the system. The value should
+	  match with configured PLATFORM_EC_PD_MAX_POWER_MW and
+	  PLATFORM_EC_PD_MAX_CURRENT_MA.
+
+config PLATFORM_EC_PD_POWER_SUPPLY_TURN_ON_DELAY
+	int "Power supply turn on delay in us"
+	default 30000
+	help
+	  Each platform could have different power sequencing and transition
+	  timing for turning on the power on the PD port.
+
+config PLATFORM_EC_PD_POWER_SUPPLY_TURN_OFF_DELAY
+	int "Power supply turn off delay in us"
+	default 30000
+	help
+	  Each platform could have different power sequencing and transition
+	  timing for turning off the power on the PD port.
+
+endif  # PLATFORM_EC_USBC
diff --git a/zephyr/Kconfig.usbc_ss_mux b/zephyr/Kconfig.usbc_ss_mux
new file mode 100644
index 0000000000..6b8b689816
--- /dev/null
+++ b/zephyr/Kconfig.usbc_ss_mux
@@ -0,0 +1,64 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if PLATFORM_EC_USBC
+
+config PLATFORM_EC_USBC_SS_MUX
+	bool "SuperSpeed mux"
+	default y
+	help
+	  Enable this to support the USB Type-C SuperSpeed Mux. If enabled,
+	  the USB stack will call usb_mux_set() to change the mux settings.
+	  The board must provide a driver in usb_muxes[] for each port so
+	  that this can work.
+
+if PLATFORM_EC_USBC_SS_MUX
+
+config PLATFORM_EC_USB_MUX_RUNTIME_CONFIG
+	bool "USB mux runtime config"
+	default y
+	help
+	  Allows the configuration of the USB mux to be set up at runtime. This
+	  makes the usb_muxes[] array writable, i.e. not const. It should be
+	  declared as such in the board config.
+
+	  This is useful when the board has runtime information that changes
+	  the configuration, such as Chromium OS Board Info (CBI set in the
+	  factory. Without this, multiple EC images would need to be installed
+	  depending on the board.
+
+config PLATFORM_EC_USBC_SS_MUX_DFP_ONLY
+	bool "Use SuperSpeed mux only when DFP"
+        help
+	  Only configure the USB Type-C SuperSpeed Mux when a port is a
+	  Downstream Facing Port (DFP). This is needed for chipsets which
+	  don't support being an Upstream Facing Port UFP).
+
+config PLATFORM_EC_USB_MUX_VIRTUAL
+	bool "USB Mux is virtual"
+	default y
+	depends on DT_HAS_CROS_EC_USBC_MUX_VIRTUAL_ENABLED
+	depends on PLATFORM_EC_USBC_SS_MUX
+	help
+	  Enable this if a virtual USB mux is supported on the EC, which is
+	  actually handled by the AP. In this case the AP gets an interrupt
+	  and is is informed when status changes, via the
+	  EC_CMD_USB_PD_MUX_INFO host command.
+
+config PLATFORM_EC_USBC_RETIMER_FW_UPDATE
+	bool "Support firmware update of USB Type-C retimers"
+	depends on PLATFORM_EC_USBC_SS_MUX
+	help
+	   Enable this to support USB Type-C retimer firmware update. Each
+	   Type-C retimer indicates its capability of supporting firmware update
+	   independently in its usb_mux_driver.
+
+	   During AP boot-up, the AP scans each PD port for retimers but only
+	   if there are no Type-C devices attached to the port. The firmware
+	   update can only be performed on retimers which show up in the AP
+	   thunderbolt device entries.
+
+endif  # PLATFORM_EC_USBC_SS_MUX
+
+endif #  PLATFORM_EC_USBC
diff --git a/zephyr/Kconfig.watchdog b/zephyr/Kconfig.watchdog
new file mode 100644
index 0000000000..bca08f22fe
--- /dev/null
+++ b/zephyr/Kconfig.watchdog
@@ -0,0 +1,40 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if WATCHDOG
+
+config PLATFORM_EC_WATCHDOG_PERIOD_MS
+	int "Watchdog timeout in ms"
+	default 1600
+	help
+	  Set the timeout of the watchdog timer. The watchdog timer reboots
+	  the system if no one reloads the watchdog timer before the timeout.
+
+config PLATFORM_EC_WATCHDOG_WARNING_LEADING_TIME_MS
+	int "Leading time of the watchdog warning timer in ms"
+	default 500
+	depends on !WDT_NPCX && !WDT_ITE_IT8XXX2
+	help
+	  Set the leading time of the watchdog warning timer. Chromium EC system
+	  uses an auxiliary timer to handle the system warning event. The
+	  auxiliary timer period (CONFIG_AUX_TIMER_PERIOD_MS) is set to
+	  PLATFORM_EC_WATCHDOG_PERIOD_MS -
+	  PLATFORM_EC_WATCHDOG_WARNING_LEADING_TIME_MS.
+
+	  For the NPCX chip, use WDT_NPCX_DELAY_CYCLES instead of this config.
+	  For the MCHP chip, use WDT_XEC_DELAY_CYCLES instead of this config.
+	  For the ITE chip, use CONFIG_WDT_ITE_WARNING_LEADING_TIME_MS instead
+	  of this config.
+
+config PLATFORM_EC_WATCHDOG_HELPER
+	bool "Use watchdog helper to trigger warning"
+	default n
+	depends on WDT_COUNTER
+	help
+	  If enabled, watchdog shim will setup cros-ec,watchdog-helper
+	  with CONFIG_WATCHDOG_AUX_TIMER_PERIOD_MS timeout.
+	  Watchdog helper is used to trigger warning and gather debugging
+	  information before hardware watchdog resets the SoC.
+
+endif # WATCHDOG
diff --git a/zephyr/Kconfig.wireless_charger b/zephyr/Kconfig.wireless_charger
new file mode 100644
index 0000000000..c53bd6f7cc
--- /dev/null
+++ b/zephyr/Kconfig.wireless_charger
@@ -0,0 +1,18 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config PLATFORM_EC_PERIPHERAL_CHARGER
+	bool "Enable peripheral charger task"
+	help
+	  Enable peripheral charger task.
+
+if PLATFORM_EC_PERIPHERAL_CHARGER
+
+config PLATFORM_EC_CPS8100
+	bool "Use CPS8100 driver"
+	help
+	  Use CPS8100 driver. CPS8100 is a Qi wireless power transmitter.
+
+
+endif # PLATFORM_EC_PERIPHERAL_CHARGER
\ No newline at end of file
diff --git a/zephyr/Makefile.cq b/zephyr/Makefile.cq
new file mode 100644
index 0000000000..bc272edb1a
--- /dev/null
+++ b/zephyr/Makefile.cq
@@ -0,0 +1,140 @@
+# -*- makefile -*-
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# This makefile is used only by firmware_builder.py to achieve parallelism.
+# The paths in this file need to match the ones in firmware_builder.py,
+# so be careful.
+
+# This also assumes that you ran zmake build -a before this in the build stage
+
+TWISTER_COMMAND=cd $(PLATFORM_EC) && ./twister --outdir \
+	twister-out-$(TOOLCHAIN) -v -i --no-upload-cros-rdb --toolchain \
+	$(TOOLCHAIN)
+ifdef COVERAGE
+TWISTER_COMMAND+=--coverage
+endif
+
+PLATFORM_EC=$(abspath ..)
+THIRD_PARTY=$(abspath ../../../third_party)
+BUILD=$(PLATFORM_EC)/build
+
+GENERATED_AND_SYSTEM_PATTERNS='$(PLATFORM_EC)/build/**' \
+	'$(PLATFORM_EC)/twister-out*/**' \
+	'/usr/include/**' \
+	'/usr/lib/**'
+TEST_PATTERNS='$(PLATFORM_EC)/test/**' \
+	'$(PLATFORM_EC)/include/tests/**' \
+	'$(PLATFORM_EC)/private/test/**' \
+	'$(PLATFORM_EC)/private/fingerprint/*/mcutest/**' \
+	'$(PLATFORM_EC)/zephyr/test/**' \
+	'$(THIRD_PARTY)/zephyr/main/subsys/testsuite/**' \
+	'$(PLATFORM_EC)/include/mock/**' \
+	'$(PLATFORM_EC)/common/mock/**' \
+	'$(PLATFORM_EC)/board/host/**' \
+	'$(PLATFORM_EC)/chip/host/**' \
+	'$(PLATFORM_EC)/core/host/**' \
+	'$(PLATFORM_EC)/zephyr/emul/**' \
+	'$(PLATFORM_EC)/zephyr/mock/**' \
+	'$(PLATFORM_EC)/zephyr/program/dev/**' \
+	'$(THIRD_PARTY)/zephyr/main/subsys/emul/**' \
+	'$(THIRD_PARTY)/zephyr/main/arch/posix/**' \
+	'**/*_benchmark.cc' \
+	'**/*_test.c' \
+	'**/*_test.cc' \
+	'**/*_test.h' \
+	'**/*_emul.c' \
+	'**/*_emul.cc' \
+	'**/*_emul.h' \
+	'$(PLATFORM_EC)/include/test_util.h' \
+	'$(PLATFORM_EC)/common/test_util.c' \
+	'$(PLATFORM_EC)/zephyr/shim/src/test_util.c' \
+	'$(PLATFORM_EC)/zephyr/shim/src/ztest_system.c'
+
+.PHONY: test twister_host twister_llvm
+
+test: zmake_unit_tests
+ifdef COVERAGE
+# List all of the files expected by firmware_builder.py
+test: $(PLATFORM_EC)/twister-out-llvm/coverage.info # EC_ZEPHYR_TESTS
+test: $(PLATFORM_EC)/twister-out-host/coverage.info # EC_ZEPHYR_TESTS_GCC
+test: $(BUILD)/coverage/lcov.info # EC_LEGACY_TESTS
+test: $(BUILD)/zephyr/all_tests.info # ALL_TESTS
+test: $(BUILD)/zephyr/zephyr_merged.info # EC_ZEPHYR_MERGED
+test: $(BUILD)/zephyr/lcov.info # ALL_MERGED
+test: $(BUILD)/zephyr/lcov_no_tests.info # ALL_FILTERED
+test: $(BUILD)/zephyr/lcov_rpt # html artifact
+test: special_boards # BOARD_ metric and html artifact
+else
+test: twister_host twister_llvm
+endif
+
+ifdef COVERAGE
+zmake_unit_tests:
+	zmake/run_tests.sh --coverage
+else
+zmake_unit_tests:
+	zmake/run_tests.sh
+endif
+
+twister_host $(PLATFORM_EC)/twister-out-host/coverage.info: TOOLCHAIN=host
+twister_host $(PLATFORM_EC)/twister-out-host/coverage.info:
+	+$(TWISTER_COMMAND)
+
+twister_llvm $(PLATFORM_EC)/twister-out-llvm/coverage.info: TOOLCHAIN=llvm
+twister_llvm $(PLATFORM_EC)/twister-out-llvm/coverage.info:
+	+$(TWISTER_COMMAND)
+
+$(BUILD)/coverage/lcov.info:
+	$(MAKE) -C .. test-coverage
+
+$(BUILD)/zephyr/all_tests.info: $(PLATFORM_EC)/twister-out-host/coverage.info $(PLATFORM_EC)/twister-out-llvm/coverage.info $(BUILD)/coverage/lcov.info
+	/usr/bin/lcov -o $@ --rc lcov_branch_coverage=1 \
+	-a $(BUILD)/coverage/lcov.info -a $(PLATFORM_EC)/twister-out-llvm/coverage.info \
+	-a $(PLATFORM_EC)/twister-out-host/coverage.info
+
+$(BUILD)/zephyr/zephyr_merged.info: $(BUILD)/zephyr/all_tests.info $(BUILD)/zephyr/all_builds.info
+	/usr/bin/lcov -o $@ --rc lcov_branch_coverage=1 \
+	-a $(BUILD)/zephyr/all_tests.info -a $(BUILD)/zephyr/all_builds.info
+
+$(BUILD)/zephyr/lcov.info: $(BUILD)/zephyr/zephyr_merged.info
+	/usr/bin/lcov -o $@ --rc lcov_branch_coverage=1 \
+	-r $(BUILD)/zephyr/zephyr_merged.info \
+	$(GENERATED_AND_SYSTEM_PATTERNS)
+
+$(BUILD)/zephyr/lcov_no_tests.info: $(BUILD)/zephyr/lcov.info
+	/usr/bin/lcov -o $@ --rc lcov_branch_coverage=1 \
+	-r $(BUILD)/zephyr/lcov.info \
+	$(TEST_PATTERNS)
+
+$(BUILD)/zephyr/lcov_rpt: $(BUILD)/zephyr/lcov.info
+	/usr/bin/genhtml --branch-coverage -q -o $@ \
+	-t 'All boards and tests merged' -s $^
+
+special_boards: $(foreach b, $(SPECIAL_BOARDS), $(BUILD)/zephyr/$(b)_rpt)
+
+$(BUILD)/zephyr/%_merged.info: $(BUILD)/zephyr/%/output/zephyr.info $(BUILD)/zephyr/all_tests.info
+	/usr/bin/lcov -o $@ --rc lcov_branch_coverage=1 \
+	-a $(BUILD)/zephyr/all_tests.info -a $<
+
+$(BUILD)/zephyr/%_stenciled.info: $(BUILD)/zephyr/%/output/zephyr.info $(BUILD)/zephyr/%_merged.info
+	$(PLATFORM_EC)/util/lcov_stencil.py -o $@ $^
+
+.PRECIOUS: $(BUILD)/zephyr/%_final.info
+$(BUILD)/zephyr/%_final.info: $(BUILD)/zephyr/%_stenciled.info
+	/usr/bin/lcov -o $@ --rc lcov_branch_coverage=1 \
+	-r $< \
+	'$(THIRD_PARTY)/**' \
+	'$(PLATFORM_EC)/zephyr/drivers/**' \
+	'$(PLATFORM_EC)/zephyr/include/drivers/**' \
+	'$(PLATFORM_EC)/zephyr/shim/chip/**' \
+	'$(PLATFORM_EC)/zephyr/shim/chip/npcx/npcx_monitor/**' \
+	'$(PLATFORM_EC)/zephyr/shim/core/**' \
+	'$(PLATFORM_EC)/driver/tcpm/it8xxx2.c' \
+	$(GENERATED_AND_SYSTEM_PATTERNS) $(TEST_PATTERNS)
+
+.PRECIOUS: $(BUILD)/zephyr/%_rpt
+$(BUILD)/zephyr/%_rpt: $(BUILD)/zephyr/%_final.info
+	/usr/bin/genhtml --branch-coverage -q -o $@ \
+	-t '$* ec code only' -s $^
diff --git a/zephyr/README.md b/zephyr/README.md
new file mode 100644
index 0000000000..c63113610b
--- /dev/null
+++ b/zephyr/README.md
@@ -0,0 +1,146 @@
+# Zephyr EC
+
+[TOC]
+
+## Introduction
+
+Zephyr EC is an effort to create an industry-standard Embedded Controller
+implementation for use primarily on laptops. It is born out of the Chromium OS
+EC.
+
+## native-posix development
+
+Zephyr can be built to run on your host machine, making it easier to develop
+and test features. This is called the native_posix build.
+
+To build it::
+
+```
+  cd ~/chromium/src/platform/ec
+  zmake build minimal-posix
+```
+
+and run it:
+
+```
+  build/zephyr/minimal-posix/build-singleimage/zephyr/zephyr.elf
+```
+
+Check the display for the pseudotty and connect an xterm to it, e.g.:
+
+```
+   xterm -e screen /dev/pts/28
+```
+
+You will then see the EC prompt and you can type commands, e.g. type 'help':
+
+```
+  Please press the <Tab> button to see all available commands.
+  You can also use the <Tab> button to prompt or auto-complete all commands or its subcommands.
+  You can try to call commands with <-h> or <--help> parameter for more information.
+
+  Available commands:
+    cbi        :Print or change Cros Board Info from flash
+    chan       :Save, restore, get or set console channel mask
+    crash      :Crash the system (for testing)
+    feat       :Print feature flags
+    gettime    :Print current time
+    gpioget    :Read GPIO value(s)
+    gpioset    :Set a GPIO
+    help       :Prints the help message.
+    hibernate  :Hibernate the EC
+    kernel     :Kernel commands
+    log        :Commands for controlling logger
+    md         :dump memory values, optionally specifying the format
+    panicinfo  :Print info from a previous panic
+    reboot     :Reboot the EC
+    rw         :Read or write a word in memory optionally specifying the size
+    shmem      :Print shared memory stats
+    sysinfo    :Print system info
+    syslock    :Lock the system, even if WP is disabled
+    timerinfo  :Print timer info
+    version    :Print versions
+    waitms     :Busy-wait for msec (large delays will reset)
+```
+
+Use Ctrl-C to quit (from the main terminal) as normal.
+
+You can run zephyr under gdb just like any other program.
+
+If you want to share the same terminal, add this line to
+`zephyr/program/minimal/prj.conf` and rebuild:
+
+```
+  CONFIG_NATIVE_UART_0_ON_STDINOUT=y
+```
+
+Running that will show an EC prompt on your terminal. Use Ctrl-\ to quit.
+
+## Gitlab integration
+
+As an experiment we have a basic gitlab integration. It watches the EC repo and
+kicks of a build when new commits appear. So far it just builds for volteer and
+does not run any tests. For firmware branches, it also builds, but fails.
+
+The gitlab builder works without a chroot and uses the Zephyr toolchain. This
+is intended to ensure that we have a path to upstreaming our code eventually and
+do not rely on Chrome OS-specific tools. It does make use of 'zmake', however.
+
+See the piplines [here](https://gitlab.com/zephyr-ec/ec/-/pipelines).
+
+## CQ builder
+
+To test the cq builder script run these commands:
+
+### firmware-zephyr-cq
+
+```
+rm -rf /tmp/artifact_bundles /tmp/artifact_bundle_metadata \
+ ~/chromiumos/src/platform/ec/build
+( cd ~/chromiumos/src/platform/ec/zephyr ; \
+./firmware_builder.py --metrics /tmp/metrics-build build && \
+./firmware_builder.py --metrics /tmp/metrics-test test && \
+./firmware_builder.py --metrics /tmp/metrics-bundle bundle && \
+echo PASSED )
+cat /tmp/artifact_bundle_metadata
+cat /tmp/metrics-build
+ls -l /tmp/artifact_bundles/
+```
+
+### firmware-zephyr-cov-cq
+
+```
+rm -rf /tmp/artifact_bundles-cov /tmp/artifact_bundle_metadata-cov \
+  ~/chromiumos/src/platform/ec/build && \
+cd ~/chromiumos/src/platform/ec/zephyr && \
+./firmware_builder.py --metrics /tmp/metrics --code-coverage build && \
+./firmware_builder.py --metrics /tmp/metrics --code-coverage test && \
+./firmware_builder.py --metrics /tmp/metrics --code-coverage \
+  --output-dir=/tmp/artifact_bundles-cov \
+  --metadata=/tmp/artifact_bundle_metadata-cov bundle && \
+echo PASSED
+cat /tmp/artifact_bundle_metadata-cov
+ls -l /tmp/artifact_bundles-cov
+```
+
+## Zmake unit tests
+
+Run the tests with `zephyr/zmake/run_tests.sh`.  You can generate a coverage
+report, but not in the chroot, as some pip modules are missing there.
+
+The [latest coverage report](https://gitlab.com/zephyr-ec/ec/-/jobs/artifacts/main/file/zephyr/zmake/htmlcov/index.html?job=zmake_coverage
+) is on gitlab.
+
+You can run the coverage report outside of the chroot easily:
+
+```
+# Install test dependencies
+cd ~/chromiumos/src/platform/ec
+python3 -m pip install 'zephyr/zmake[tests]' --user
+# Run tests with coverage
+cd ~/chromiumos/src/platform/ec/zephyr/zmake
+coverage run --source=zmake -m pytest .
+coverage report
+coverage html
+xdg-open htmlcov/index.html
+```
diff --git a/zephyr/app/CMakeLists.txt b/zephyr/app/CMakeLists.txt
new file mode 100644
index 0000000000..0365782963
--- /dev/null
+++ b/zephyr/app/CMakeLists.txt
@@ -0,0 +1,5 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+add_subdirectory_ifdef(CONFIG_CROS_EC ec)
diff --git a/zephyr/app/Kconfig b/zephyr/app/Kconfig
new file mode 100644
index 0000000000..7fb8c917ed
--- /dev/null
+++ b/zephyr/app/Kconfig
@@ -0,0 +1,5 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+rsource "ec/Kconfig"
diff --git a/zephyr/app/ec/CMakeLists.txt b/zephyr/app/ec/CMakeLists.txt
new file mode 100644
index 0000000000..ac3d3fe3d2
--- /dev/null
+++ b/zephyr/app/ec/CMakeLists.txt
@@ -0,0 +1,11 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cros_ec_library_include_directories(include)
+zephyr_library_sources(ec_app_main.c)
+if(NOT DEFINED CONFIG_ZTEST)
+    zephyr_library_sources(main_shim.c)
+endif()
+
+add_subdirectory(chip)
\ No newline at end of file
diff --git a/zephyr/app/ec/Kconfig b/zephyr/app/ec/Kconfig
new file mode 100644
index 0000000000..465756b5f0
--- /dev/null
+++ b/zephyr/app/ec/Kconfig
@@ -0,0 +1,203 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+menuconfig CROS_EC
+	bool "Chromium OS EC app"
+	imply PRINTK
+	imply SHELL
+	imply SHELL_MINIMAL
+	imply STACK_SENTINEL
+	help
+	  Enable the common Chromium OS EC application. This prints a message,
+	  starts the EC tasks and sets up any drivers that are needed.
+
+	  This depends on PLATFORM_EC at present, since without the shimmed
+	  tasks, almost nothing can operate.
+
+if CROS_EC
+
+rsource "soc/Kconfig"
+orsource "chip/$(ARCH)/*/Kconfig.*"
+
+#
+# Override the maximum number of preemptive priority levels.
+#
+config NUM_PREEMPT_PRIORITIES
+	default 26
+
+#
+# Override the LOG_PRINTK to be no as it currently makes multiple
+# tests timeout and a few others fail in console assertions
+# TODO(b/http://b/260772137) Fix LOG_PRINTK issue and remove override
+#
+config LOG_PRINTK
+       default n
+
+#
+# In Zephyr, the default system workqueue thread priority level is the lowest
+# cooperative priority. Override its priority to the second lowest preempt
+# priority. (i.e. NUM_PREEMPT_PRIORITIES - 1)
+#
+config SYSTEM_WORKQUEUE_PRIORITY
+	default 24
+
+# eSPI is chatty, so default to Error only
+choice ESPI_LOG_LEVEL_CHOICE
+	default ESPI_LOG_LEVEL_ERR
+endchoice
+
+config LTO
+	bool "Link Time Optimization (LTO)"
+	default y if !SOC_POSIX
+	help
+	  Enable the Link Time Optimization (LTO) feature for the toolchain.
+	  LTO expands the scope of optimizations to encompass the whole program,
+	  reducing the image size.
+
+	  At this time, LTO is only enabled for Chromium OS source files and
+	  is not enabled for the Zephyr kernel or drivers due.
+	  https://github.com/zephyrproject-rtos/zephyr/issues/2112
+
+choice CBPRINTF_IMPLEMENTATION
+	default CBPRINTF_NANO
+
+endchoice
+
+choice
+	prompt "Chromium OS EC firmware section"
+
+config CROS_EC_RO
+	bool "This build is will be for the RO copy of the EC"
+	help
+	  This build will be used to produce a copy for the read-only
+	  section of the EC firmware.
+
+config CROS_EC_RW
+	bool "This build is will be for the RW copy of the EC"
+	help
+	  This build will be used to produce a copy for the read-write
+	  section of the EC firmware.
+
+endchoice
+
+config CROS_EC_ACTIVE_COPY
+	string
+	default "RO" if CROS_EC_RO
+	default "RW" if CROS_EC_RW
+	help
+	  When the active copy name is output to a console, this
+	  string will be displayed.
+
+config CROS_EC_HOOK_TICK_INTERVAL
+	int "The interval time for the HOOK_TICK"
+	default 250000
+	help
+	  Specificies the interval time for the HOOK_TICK, specified in
+	  microseconds. Modules register with HOOK_TICK to be called
+	  periodically by the HOOKS task. The interval must be shorter than
+	  1 second and is set according the EC chipset's sleep requirements.
+
+# When building for the host, we still need values for the various memory
+# sizes, though they aren't actually used, so just set some reasonable-looking
+# values and then ignore them.
+config CROS_EC_RAM_SIZE
+	hex "The total available RAM size."
+	default 0x0000f800 if ARCH_POSIX
+	help
+		This value describes the total available RAM size for the chip.
+
+config CROS_EC_DATA_RAM_SIZE
+	hex "The total available RAM size for data."
+	default 0x00010000 if ARCH_POSIX
+	help
+		This value describes the total available RAM size for data on the chip.
+
+config CROS_EC_RAM_BASE
+	hex "Base address of RAM for the chip."
+	default 0x200c0000 if ARCH_POSIX
+	help
+		Base address of RAM for the chip.
+
+config CROS_EC_PROGRAM_MEMORY_BASE
+	hex "The base address of the program memory region."
+	default 0x10090000 if ARCH_POSIX
+	help
+		This will be used (among other things) to calculate the current PC's
+		offset within the program memory.
+
+config CROS_EC_RO_MEM_OFF
+	hex "The RO region's offset."
+	default 0x0 if ARCH_POSIX
+	help
+		This will be used to determine if the current PC is in the RO section.
+
+config CROS_EC_RO_SIZE
+	hex "The size of the RO region."
+	default 0xb000 if ARCH_POSIX
+	default $(dt_node_int_prop_hex,/binman/wp-ro,size)
+	help
+		This will be used (along with SYSTEM_RO_MEM_OFF) to determine if the
+		current PC is in the RO section.
+
+config CROS_EC_RW_MEM_OFF
+	hex "The RW region's offset."
+	default 0xb000 if ARCH_POSIX
+	help
+		This will be used to determine if the current PC is in the RW section.
+
+config CROS_EC_RW_SIZE
+	hex "The size of the RW region."
+	default 0x75000 if ARCH_POSIX
+	default $(dt_node_int_prop_hex,/binman/ec-rw,size)
+	help
+		This will be used (along with SYSTEM_RW_MEM_OFF) to determine if the
+		current PC is in the RW section.
+
+# By default, a unit test doesn't need shimmed tasks.
+config SHIMMED_TASKS
+	bool "Add support for shimming in platform/ec tasks as Zephyr threads"
+	default n if ARCH_POSIX
+	default y if PLATFORM_EC_USB_CHARGER
+	default y if HAS_TASK_CHARGER
+	default y if HAS_TASK_CHG_RAMP
+	default y if HAS_TASK_CHIPSET
+	default y if HAS_TASK_DPS
+	default y if HAS_TASK_HOSTCMD
+	default y if HAS_TASK_KEYSCAN
+	default y if HAS_TASK_KEYPROTO
+	default y if HAS_TASK_MOTIONSENSE
+	default y if HAS_TASK_PD_INT_SHARED
+	default y if HAS_TASK_POWERBTN
+	default y if HAS_TASK_RWSIG
+	default y if HAS_TASK_USB_MUX
+	default y if TASK_HOSTCMD_THREAD_DEDICATED
+	default y if HAS_TASK_MAIN
+	default y if HAS_TASK_TOUCHPAD
+	default y if HAS_TASK_PD_C0
+	default y if HAS_TASK_PD_INT_C0
+	help
+	  When this option is enabled, a shimmed_tasks.h header with the
+	  CROS_EC_TASK_LIST defined needs to be included for the project to
+	  build. The CROS_EC_TASK_LIST defines a list of CROS_EC_TASK that
+	  should be shimmed in.
+
+#
+# These shell options are turned off by MINIMAL_SHELL, but are important to us;
+# override Zephyr's default to keep them on.
+#
+config SHELL_HISTORY
+  default y
+
+config SHELL_TAB
+  default y
+
+config SHELL_TAB_AUTOCOMPLETION
+  default y if SHELL_TAB
+
+config SHELL_HELP
+  default y
+
+config KERNEL_SHELL
+  default y
+endif # CROS_EC
diff --git a/zephyr/app/ec/chip/CMakeLists.txt b/zephyr/app/ec/chip/CMakeLists.txt
new file mode 100644
index 0000000000..e92dbc5d5d
--- /dev/null
+++ b/zephyr/app/ec/chip/CMakeLists.txt
@@ -0,0 +1 @@
+add_subdirectory_ifdef(CONFIG_RISCV riscv)
\ No newline at end of file
diff --git a/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec b/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec
new file mode 100644
index 0000000000..3baca08d04
--- /dev/null
+++ b/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec
@@ -0,0 +1,26 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+#
+# This file defines the default config values shared by all MEC chipsets
+#
+
+if SOC_FAMILY_MEC
+
+# Enable MPU for ARM targets
+config ARM_MPU
+	default y
+
+# ADC
+config PLATFORM_EC_ADC_RESOLUTION
+	default 10
+
+config PLATFORM_EC_ADC_OVERSAMPLING
+	default 0
+
+# Set the system clock
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 32768
+
+endif # SOC_FAMILY_MEC
diff --git a/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec_mec172x b/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec_mec172x
new file mode 100644
index 0000000000..ba4b795ca9
--- /dev/null
+++ b/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec_mec172x
@@ -0,0 +1,49 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+#
+# This file defines the correct defaults when using the MEC172x series chipset
+#
+
+if SOC_SERIES_MEC172X
+
+#
+# MEC1727NSZ: 416KB total SRAM as 352 KiB Code and 64 KiB data.
+#             Top 2KB of data SRAM used by Boot-ROM and a 1KB persistent
+#             region for customer use.
+#             512 KiB internal SPI flash
+
+# Code RAM base for MEC172x series
+# First 4KB reserved for SRAM based EC LFW functionality
+# Experiment remove reserve of first 4KB and use ROM load API
+config CROS_EC_PROGRAM_MEMORY_BASE
+	default 0xc0000
+
+# Data SRAM base
+config CROS_EC_RAM_BASE
+	default 0x118000
+
+# Total data SRAM size
+config CROS_EC_DATA_RAM_SIZE
+	default 0x010000
+
+# Top 2KB reserved for PUF leaving 62KB
+# 61KB for data + 1KB persistent across chip reset.
+config CROS_EC_RAM_SIZE
+	default 0x00f800
+
+config CROS_EC_RO_MEM_OFF
+	default 0x0
+
+# was 0x40000
+# TODO(b/268254046): mchp Zephyr: MEC172x: verify RO flash size.
+config CROS_EC_RO_SIZE
+	default 0x3F000
+
+# RW firmware in program memory - Identical to RO, only one image loaded at a
+# time.
+config CROS_EC_RW_MEM_OFF
+	default 0x0
+
+endif # SOC_SERIES_MEC172X
diff --git a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx b/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx
new file mode 100644
index 0000000000..17936ab05d
--- /dev/null
+++ b/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx
@@ -0,0 +1,57 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+#
+# This file defines the default config values shared by all NPCX chipsets
+#
+
+if SOC_FAMILY_NPCX
+
+# Enable MPU for ARM targets
+config ARM_MPU
+	default y
+
+# Enable NPCX firmware header generator
+config NPCX_HEADER
+	default y
+
+choice NPCX_HEADER_SPI_MAX_CLOCK_CHOICE
+	default NPCX_HEADER_SPI_MAX_CLOCK_50
+endchoice
+
+choice NPCX_HEADER_SPI_READ_MODE_CHOICE
+	default NPCX_HEADER_SPI_READ_MODE_DUAL
+endchoice
+
+choice NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_CHOICE
+	default NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_2
+endchoice
+
+# ADC
+# The resolution and oversamplig values are fixed by the NPCX ADC driver
+config PLATFORM_EC_ADC_RESOLUTION
+	default 10
+
+config PLATFORM_EC_ADC_OVERSAMPLING
+	default 0
+
+# Set the system clock to 15MHz.
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 15000000
+
+if WATCHDOG
+
+# Set the delay time for printing panic data.
+# 1 cycle is about 32ms. 500ms is about 16 cycles.
+config WDT_NPCX_DELAY_CYCLES
+	default 16
+
+endif # WATCHDOG
+
+# The maximum supported time the NPCX can spend in deep-sleep with instant
+# wake is 200 ms, so the hook tick interval is set to match.
+config CROS_EC_HOOK_TICK_INTERVAL
+	default 200000
+
+endif # SOC_FAMILY_NPCX
diff --git a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx7 b/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx7
new file mode 100644
index 0000000000..cb00db3345
--- /dev/null
+++ b/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx7
@@ -0,0 +1,49 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+#
+# This file defines the correct defaults when using the NPCX7 series chipset
+#
+
+if SOC_SERIES_NPCX7
+
+#
+# NPCX796FB: 1024 KiB Flash, 192 KiB code RAM, 62 KiB data RAM
+# NPCX796FC: 512 KiB Flash, 192 KiB code RAM, 62 KiB data RAM
+# NPCX797FC: 512 KiB Flash, 320 KiB code RAM, 62 KiB data RAM
+#
+
+# Code RAM base for NPCX7 series
+config CROS_EC_PROGRAM_MEMORY_BASE
+	default 0x10090000 if SOC_NPCX7M6FB || SOC_NPCX7M6FC
+	default 0x10070000 if SOC_NPCX7M7FC
+
+config CROS_EC_RAM_BASE
+	default 0x200c0000
+
+config CROS_EC_DATA_RAM_SIZE
+	default 0x00010000
+
+config CROS_EC_RAM_SIZE
+	default 0x0000f800
+
+config CROS_EC_RO_MEM_OFF
+	default 0x0
+
+# NPCX796FB/NPCX796FC: Image size limited by code RAM size (192 KiB)
+# NPCX797FC:           Image size limited by 1/2 Flash size (256 KiB)
+config CROS_EC_RO_SIZE
+	default 0x30000 if SOC_NPCX7M6FB || SOC_NPCX7M6FC
+	default 0x40000 if SOC_NPCX7M7FC
+
+# RW firmware in program memory - Identical to RO, only one image loaded at a
+# time.
+config CROS_EC_RW_MEM_OFF
+	default 0x0
+
+config CROS_EC_RW_SIZE
+	default 0x30000 if SOC_NPCX7M6FB || SOC_NPCX7M6FC
+	default 0x40000 if SOC_NPCX7M7FC
+
+endif # SOC_SERIES_NPCX7
diff --git a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx9 b/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx9
new file mode 100644
index 0000000000..9c807a732c
--- /dev/null
+++ b/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx9
@@ -0,0 +1,53 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+#
+# This file defines the correct defaults when using the NPCX9 series chipset
+#
+
+if SOC_SERIES_NPCX9
+
+#
+# NPCX993F: 512 KiB Flash, 256 KiB code RAM, 64 KiB data RAM
+# NPCX996F: 512 KiB Flash, 192 KiB code RAM, 64 KiB data RAM
+# NPCX997F: 1024 KiB Flash, 320 KiB code RAM, 64 KiB data RAM
+#
+
+# Code RAM base for NPCX9 series
+config CROS_EC_PROGRAM_MEMORY_BASE
+	default 0x10080000 if SOC_NPCX9M3F
+	default 0x10090000 if SOC_NPCX9M6F
+	default 0x10070000 if SOC_NPCX9M7F
+
+config CROS_EC_RAM_BASE
+	default 0x200c0000
+
+config CROS_EC_DATA_RAM_SIZE
+	default 0x0000f800
+
+config CROS_EC_RAM_SIZE
+	default 0x0000f800
+
+config CROS_EC_RO_MEM_OFF
+	default 0x0
+
+# NPCX993F: Image size limited by 1/2 Flash size (256 KiB) and
+#           code RAM size (256 KiB)
+# NPCX996F: Image size limited by code RAM size (192 KiB)
+# NPCX997F: Image size limited by code RAM size (320 KiB)
+
+config CROS_EC_RO_SIZE
+	default 0x40000 if SOC_NPCX9M3F
+	default 0x30000 if SOC_NPCX9M6F
+	default 0x50000 if SOC_NPCX9M7F
+
+config CROS_EC_RW_MEM_OFF
+	default 0x0
+
+config CROS_EC_RW_SIZE
+	default 0x40000 if SOC_NPCX9M3F
+	default 0x30000 if SOC_NPCX9M6F
+	default 0x50000 if SOC_NPCX9M7F
+
+endif # SOC_SERIES_NPCX9
diff --git a/zephyr/app/ec/chip/arm/st_stm32/Kconfig.stm32 b/zephyr/app/ec/chip/arm/st_stm32/Kconfig.stm32
new file mode 100644
index 0000000000..17f712028e
--- /dev/null
+++ b/zephyr/app/ec/chip/arm/st_stm32/Kconfig.stm32
@@ -0,0 +1,32 @@
+# Copyright 2023 The ChromiumOS Authors.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if SOC_FAMILY_STM32
+
+DT_CHOSEN_Z_SRAM := zephyr,sram
+
+config CROS_EC_PROGRAM_MEMORY_BASE
+	default FLASH_BASE_ADDRESS
+
+config CROS_EC_RAM_BASE
+	default SRAM_BASE_ADDRESS
+
+config CROS_EC_DATA_RAM_SIZE
+	default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_SRAM))
+
+config CROS_EC_RAM_SIZE
+	default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_SRAM))
+
+config CROS_EC_RO_MEM_OFF
+	default $(dt_node_int_prop_hex,/binman/wp-ro,offset)
+
+config CROS_EC_RW_MEM_OFF
+	default $(dt_node_int_prop_hex,/binman/ec-rw,offset)
+
+# Tell the linker where the RO/RW part is.
+config FLASH_LOAD_OFFSET
+	default CROS_EC_RO_MEM_OFF if CROS_EC_RO
+	default CROS_EC_RW_MEM_OFF if CROS_EC_RW
+
+endif # SOC_FAMILY_STM32
diff --git a/zephyr/app/ec/chip/riscv/CMakeLists.txt b/zephyr/app/ec/chip/riscv/CMakeLists.txt
new file mode 100644
index 0000000000..b11c4e9a90
--- /dev/null
+++ b/zephyr/app/ec/chip/riscv/CMakeLists.txt
@@ -0,0 +1 @@
+add_subdirectory_ifdef(CONFIG_SOC_FAMILY_RISCV_ITE riscv-ite)
\ No newline at end of file
diff --git a/zephyr/app/ec/chip/riscv/riscv-ite/CMakeLists.txt b/zephyr/app/ec/chip/riscv/riscv-ite/CMakeLists.txt
new file mode 100644
index 0000000000..69608c33e3
--- /dev/null
+++ b/zephyr/app/ec/chip/riscv/riscv-ite/CMakeLists.txt
@@ -0,0 +1,3 @@
+if (CONFIG_ESPI_IT8XXX2)
+    zephyr_library_sources_ifdef(CONFIG_AP_POWER_CONTROL it8xxx2-espi.c)
+endif ()
\ No newline at end of file
diff --git a/zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2 b/zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2
new file mode 100644
index 0000000000..5afcfe1db0
--- /dev/null
+++ b/zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2
@@ -0,0 +1,34 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if SOC_FAMILY_RISCV_ITE
+
+# Code RAM base for IT8XXX2
+config CROS_EC_PROGRAM_MEMORY_BASE
+	default 0x80000000
+
+# The total RAM size of IT8xxx2 is 60 KB.
+# The first 4KB block be always reserved for ram code functions,
+# so the total available RAM size will be 56KB.
+config CROS_EC_RAM_BASE
+	default 0x80101000
+
+config CROS_EC_DATA_RAM_SIZE
+	default 0x0000e000
+
+config CROS_EC_RAM_SIZE
+	default 0x0000e000
+
+# Image size is configured with binman's property.
+# (CROS_EC_RO_SIZE and CROS_EC_RW_SIZE)
+config CROS_EC_RO_MEM_OFF
+	default 0x0
+
+config CROS_EC_RW_MEM_OFF
+	default $(dt_node_int_prop_hex,/binman/ec-rw,offset)
+
+config FLASH_LOAD_OFFSET
+	default CROS_EC_RW_MEM_OFF if CROS_EC_RW
+
+endif # SOC_FAMILY_RISCV_ITE
diff --git a/zephyr/app/ec/chip/riscv/riscv-ite/it8xxx2-espi.c b/zephyr/app/ec/chip/riscv/riscv-ite/it8xxx2-espi.c
new file mode 100644
index 0000000000..c32d1ccd14
--- /dev/null
+++ b/zephyr/app/ec/chip/riscv/riscv-ite/it8xxx2-espi.c
@@ -0,0 +1,64 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include <zephyr/devicetree.h>
+#include <zephyr/logging/log.h>
+
+#include <ap_power/ap_power.h>
+#include <chipset.h>
+#include <soc_espi.h>
+
+LOG_MODULE_REGISTER(ec_chip_it8xxx2_espi, CONFIG_ESPI_LOG_LEVEL);
+
+/*
+ * When eSPI CS# is held low, it prevents IT8xxx2 from entering deep doze.
+ * To allow deep doze and save power, disable the eSPI inputs while the AP is
+ * in G3.
+ */
+static const struct device *const espi_device =
+	DEVICE_DT_GET(DT_NODELABEL(espi0));
+
+static void espi_enable_callback(struct ap_power_ev_callback *cb,
+				 struct ap_power_ev_data data)
+{
+	switch (data.event) {
+	case AP_POWER_INITIALIZED:
+		/* When AP power state becomes known, sync eSPI enable */
+		if (chipset_in_state(CHIPSET_STATE_HARD_OFF)) {
+			LOG_DBG("AP off; disabling eSPI");
+			espi_it8xxx2_enable_pad_ctrl(espi_device, false);
+		}
+		break;
+	case AP_POWER_PRE_INIT:
+	case AP_POWER_HARD_OFF: {
+		bool enable = data.event == AP_POWER_PRE_INIT;
+
+		LOG_DBG("%sabling eSPI in response to AP power event",
+			enable ? "en" : "dis");
+		espi_it8xxx2_enable_pad_ctrl(espi_device, enable);
+		break;
+	}
+	default:
+		__ASSERT(false, "%s: unhandled event: %d", __func__,
+			 data.event);
+		break;
+	}
+}
+
+static int init_espi_enable_callback(void)
+{
+	static struct ap_power_ev_callback cb;
+
+	if (!device_is_ready(espi_device))
+		k_oops();
+
+	ap_power_ev_init_callback(&cb, espi_enable_callback,
+				  AP_POWER_INITIALIZED | AP_POWER_PRE_INIT |
+					  AP_POWER_HARD_OFF);
+	ap_power_ev_add_callback(&cb);
+
+	return 0;
+}
+/* Should run before power sequencing init so INITIALIZED callback can fire */
+SYS_INIT(init_espi_enable_callback, APPLICATION, 0);
diff --git a/zephyr/app/ec/ec_app_main.c b/zephyr/app/ec/ec_app_main.c
new file mode 100644
index 0000000000..6b8e113728
--- /dev/null
+++ b/zephyr/app/ec/ec_app_main.c
@@ -0,0 +1,119 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ap_power/ap_power_interface.h"
+#include "button.h"
+#include "chipset.h"
+#include "cros_board_info.h"
+#include "ec_app_main.h"
+#include "ec_tasks.h"
+#include "hooks.h"
+#include "keyboard_scan.h"
+#include "lpc.h"
+#include "system.h"
+#include "vboot.h"
+#include "watchdog.h"
+#include "zephyr_espi_shim.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/pm/policy.h>
+#include <zephyr/shell/shell_uart.h>
+#include <zephyr/sys/printk.h>
+
+static struct k_timer no_sleep_boot_timer;
+static void boot_allow_sleep(struct k_timer *timer)
+{
+	pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
+}
+
+/* For testing purposes this is not named main. See main_shim.c for the real
+ * main() function.
+ */
+void ec_app_main(void)
+{
+	/*
+	 * Initialize reset logs. This needs to be done before any updates of
+	 * reset logs because we need to verify if the values remain the same
+	 * after every EC reset.
+	 */
+	if (IS_ENABLED(CONFIG_CMD_AP_RESET_LOG)) {
+		init_reset_log();
+	}
+
+	system_print_banner();
+
+	if (IS_ENABLED(CONFIG_WATCHDOG) &&
+	    !IS_ENABLED(CONFIG_WDT_DISABLE_AT_BOOT)) {
+		watchdog_init();
+	}
+
+	if (IS_ENABLED(CONFIG_PLATFORM_EC_BOOT_NO_SLEEP)) {
+		k_timeout_t duration =
+			K_MSEC(CONFIG_PLATFORM_EC_BOOT_NO_SLEEP_MS);
+
+		k_timer_init(&no_sleep_boot_timer, boot_allow_sleep, NULL);
+		k_timer_start(&no_sleep_boot_timer, duration, K_NO_WAIT);
+
+		pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_IDLE,
+					 PM_ALL_SUBSTATES);
+	}
+
+	/*
+	 * Keyboard scan init/Button init can set recovery events to
+	 * indicate to host entry into recovery mode. Before this is
+	 * done, LPC_HOST_EVENT_ALWAYS_REPORT mask needs to be initialized
+	 * correctly.
+	 */
+	if (IS_ENABLED(CONFIG_HOSTCMD_X86)) {
+		lpc_init_mask();
+	}
+
+	if (IS_ENABLED(HAS_TASK_KEYSCAN)) {
+		keyboard_scan_init();
+	}
+
+	if (IS_ENABLED(CONFIG_DEDICATED_RECOVERY_BUTTON) ||
+	    IS_ENABLED(CONFIG_VOLUME_BUTTONS)) {
+		button_init();
+	}
+
+	if (IS_ENABLED(CONFIG_PLATFORM_EC_VBOOT_EFS2)) {
+		/*
+		 * For RO, it behaves as follows:
+		 *   In recovery, it enables PD communication and returns.
+		 *   In normal boot, it verifies and jumps to RW.
+		 * For RW, it returns immediately.
+		 */
+		vboot_main();
+	}
+
+	/* Call init hooks before main tasks start */
+	if (IS_ENABLED(CONFIG_PLATFORM_EC_HOOKS)) {
+		hook_notify(HOOK_INIT);
+	}
+
+	/*
+	 * If the EC has exclusive control over the CBI EEPROM WP signal, have
+	 * the EC set the WP if appropriate.  Note that once the WP is set, the
+	 * EC must be reset via EC_RST_ODL in order for the WP to become unset.
+	 */
+	if (IS_ENABLED(CONFIG_PLATFORM_EC_EEPROM_CBI_WP) && system_is_locked())
+		cbi_latch_eeprom_wp();
+
+	/*
+	 * Print the init time.  Not completely accurate because it can't take
+	 * into account the time before timer_init(), but it'll at least catch
+	 * the majority of the time.
+	 */
+	cprints(CC_SYSTEM, "Inits done");
+
+	/* Start the EC tasks after performing all main initialization */
+	if (IS_ENABLED(CONFIG_SHIMMED_TASKS)) {
+		start_ec_tasks();
+	}
+	if (IS_ENABLED(CONFIG_AP_PWRSEQ)) {
+		ap_pwrseq_task_start();
+	}
+}
diff --git a/zephyr/app/ec/include/ec_app_main.h b/zephyr/app/ec/include/ec_app_main.h
new file mode 100644
index 0000000000..472e0b5c0e
--- /dev/null
+++ b/zephyr/app/ec/include/ec_app_main.h
@@ -0,0 +1,6 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+void ec_app_main(void);
diff --git a/zephyr/app/ec/main_shim.c b/zephyr/app/ec/main_shim.c
new file mode 100644
index 0000000000..0ec92b70bf
--- /dev/null
+++ b/zephyr/app/ec/main_shim.c
@@ -0,0 +1,26 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_app_main.h"
+#include "host_command.h"
+
+#include <zephyr/kernel.h>
+
+/** A stub main to call the real ec app main function. LCOV_EXCL_START */
+void main(void)
+{
+	ec_app_main();
+
+	if (IS_ENABLED(CONFIG_TASK_HOSTCMD_THREAD_MAIN)) {
+		host_command_main();
+	} else if (IS_ENABLED(CONFIG_THREAD_MONITOR)) {
+		/*
+		 * Avoid returning so that the main stack is displayed by the
+		 * "kernel stacks" shell command.
+		 */
+		k_sleep(K_FOREVER);
+	}
+}
+/* LCOV_EXCL_STOP */
diff --git a/zephyr/app/ec/soc/Kconfig b/zephyr/app/ec/soc/Kconfig
new file mode 100644
index 0000000000..f3da740ccf
--- /dev/null
+++ b/zephyr/app/ec/soc/Kconfig
@@ -0,0 +1,104 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+menuconfig AP
+	bool "Enable AP SoC support code"
+	default y
+	help
+	  This device has an application processor (AP) on-board and
+	  support code should be enabled.
+
+if AP
+
+choice
+	prompt "SoC chipset generation"
+
+config AP_X86_INTEL_CML
+	bool "AP is CML chipset"
+	select AP_X86_INTEL
+	help
+	  The application processor is Intel Comet Lake (CML) chipset.
+
+config AP_X86_INTEL_TGL
+	bool "AP is TGL chipset"
+	select AP_X86_INTEL
+	help
+	  The application processor is Intel Tiger Lake (TGL) chipset.
+
+config AP_X86_INTEL_ADL
+	bool "AP is ADL chipset"
+	select AP_X86_INTEL
+	help
+	  The application processor is Intel Alder Lake (ADL) chipset.
+
+config AP_X86_AMD
+	bool "AP is an AMD chipset"
+	select AP_X86
+	help
+	  The application processor is a product of AMD.
+
+config AP_X86_INTEL_MTL
+	bool "AP is MTL chipset"
+	select AP_X86_INTEL
+	help
+	  The application processor is Intel Meteor Lake (MTL) chipset.
+
+config AP_ARM_MTK_MT8192
+	bool "MediaTek MT8192"
+	select AP_AARCH64
+	help
+	  The application processor is a MediaTek MT8192 processor.
+
+config AP_ARM_MTK_MT8186
+	bool "MediaTek MT8186"
+	select AP_AARCH64
+	help
+	  The application processor is a MediaTek MT8186 processor.
+
+config AP_ARM_MTK_MT8188
+	bool "MediaTek MT8188"
+	select AP_AARCH64
+	help
+	  The application processor is a MediaTek MT8188 processor.
+
+config AP_ARM_QUALCOMM_SC7180
+	bool "Qualcomm Snapdragon SC7180"
+	select AP_AARCH64
+	help
+	  The application processor is a Qualcomm Snapdragon SC7180
+	  ARMv8 processor.
+
+config AP_ARM_QUALCOMM_SC7280
+	bool "Qualcomm Snapdragon SC7280"
+	select AP_AARCH64
+	help
+	  The application processor is a Qualcomm Snapdragon SC7280
+	  ARMv8 processor.
+
+endchoice
+
+# Invisible meta-symbols generated by the selected chipset.
+config AP_X86_INTEL
+	bool
+	select AP_X86
+	help
+	  The application processor (AP) is an Intel SoC.
+
+config AP_X86
+	bool
+	help
+	  The application processor (AP) is X86-like.
+
+config AP_AARCH64
+	bool
+	select AP_ARM
+	help
+	  The application processor (AP) is 64-bit ARMv8 architecture.
+
+config AP_ARM
+	bool
+	help
+	  The application processor (AP) is ARM-like.
+
+endif # AP
diff --git a/zephyr/boards/arm/mec1727/Kconfig.board b/zephyr/boards/arm/mec1727/Kconfig.board
new file mode 100644
index 0000000000..7b11c1a0e9
--- /dev/null
+++ b/zephyr/boards/arm/mec1727/Kconfig.board
@@ -0,0 +1,15 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# "BOARD" below refers to a Zephyr board, which does not have a 1:1
+# mapping with the Chrome OS concept of a board.  By Zephyr's
+# conventions, we'll still call it "BOARD_*" to make this more
+# applicable to be upstreamed, even though this code is shared by all
+# projects using the MEC172x EVB board.
+config BOARD_MEC1727
+	bool "MEC1727 Zephyr Board"
+	depends on SOC_MEC172X_NSZ
+	# MCHP XEC doesn't actually have enough ram for coverage, but this will
+	# allow generating initial 0 line coverage.
+	select HAS_COVERAGE_SUPPORT
diff --git a/zephyr/boards/arm/mec1727/Kconfig.defconfig b/zephyr/boards/arm/mec1727/Kconfig.defconfig
new file mode 100644
index 0000000000..8afdc63abf
--- /dev/null
+++ b/zephyr/boards/arm/mec1727/Kconfig.defconfig
@@ -0,0 +1,35 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if BOARD_MEC1727
+
+config BOARD
+	default "mec1727"
+
+# Zephyr internal stack sizes
+
+config IDLE_STACK_SIZE
+	default 400
+
+config SYSTEM_WORKQUEUE_STACK_SIZE
+	default 1024
+
+# Chromium EC stack sizes
+
+config TASK_CHARGER_STACK_SIZE
+	default 1056
+
+config TASK_KEYSCAN_STACK_SIZE
+	default 1024
+
+config TASK_PD_STACK_SIZE
+	default 1184
+
+config TASK_PD_INT_STACK_SIZE
+	default 1024
+
+config TASK_USB_CHG_STACK_SIZE
+	default 1024
+
+endif # BOARD_MEC1727
diff --git a/zephyr/boards/arm/mec1727/board.cmake b/zephyr/boards/arm/mec1727/board.cmake
new file mode 100644
index 0000000000..d28d9c55e2
--- /dev/null
+++ b/zephyr/boards/arm/mec1727/board.cmake
@@ -0,0 +1,5 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+set(MCHP_IMAGE_FILE ${PROJECT_BINARY_DIR}/zephyr.mchp.bin)
diff --git a/zephyr/boards/arm/mec1727/mec1727.dts b/zephyr/boards/arm/mec1727/mec1727.dts
new file mode 100644
index 0000000000..000e54579f
--- /dev/null
+++ b/zephyr/boards/arm/mec1727/mec1727.dts
@@ -0,0 +1,209 @@
+/* Copyright 2022 Microchip Technology Inc. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/dts-v1/;
+
+#include <cros/microchip/mec1727.dtsi>
+#include <cros/thermistor/thermistor.dtsi>
+#include <dt-bindings/gpio_defines.h>
+#include <microchip/mec1727nsz.dtsi>
+#include <zephyr/dt-bindings/pwm/pwm.h>
+
+#define GPIO_VOLTAGE_1P8 (1U << 11)
+
+/ {
+	model = "MEC1727";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,flash = &flash0;
+		zephyr,flash-controller = &int_flash;
+	};
+
+	/* MEC172x Chrome design - 256KB code size */
+	flash0: flash@c0000 {
+		reg = <0x000C0000 0x40000>;
+	};
+
+	named-pwms {
+		compatible = "named-pwms";
+	};
+
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		adc_ddr_soc: ddr_soc {
+			enum-name = "ADC_TEMP_SENSOR_1_DDR_SOC";
+			io-channels = <&adc0 5>;
+		};
+		adc_ambient: ambient {
+			enum-name = "ADC_TEMP_SENSOR_2_AMBIENT";
+			io-channels = <&adc0 3>;
+		};
+		adc_charger: charger {
+			enum-name = "ADC_TEMP_SENSOR_3_CHARGER";
+			io-channels = <&adc0 0>;
+		};
+		adc_wwan: wwan {
+			enum-name = "ADC_TEMP_SENSOR_4_WWAN";
+			io-channels = <&adc0 4>;
+		};
+	};
+
+	soc {
+		/delete-node/ rtc@400f5000;
+		/delete-node/ kscan@40009c00;
+
+		crtc: cros-rtc@400f5000 {
+			compatible = "microchip,xec-cros-rtc";
+			reg = <0x400f5000 0x100>;
+			interrupts = <119 0>, <120 0>;
+			label = "CRTC";
+		};
+
+		cros_kb_raw: cros-kb-raw@40009c00 {
+			compatible = "microchip,xec-cros-kb-raw";
+			reg = <0x40009c00 0x18>;
+			interrupts = <135 0>;
+			status = "disabled";
+		};
+	};
+};
+
+&cpu0 {
+	status = "okay";
+/* cpu-power-states = <&suspend_to_idle_instant &suspend_to_idle_normal>; */
+};
+
+&bbram {
+	status = "okay";
+};
+
+&ecia {
+	status = "okay";
+};
+
+/* Enable aggregated GIRQ24/25 for eSPI virtual wires */
+&girq24 {
+	status = "okay";
+};
+
+&girq25 {
+	status = "okay";
+};
+
+&espi0 {
+	status = "okay";
+	pinctrl-0 = <&espi_reset_n_gpio061
+		     &espi_cs_n_gpio066
+		     &espi_clk_gpio065
+		     &espi_io0_gpio070
+		     &espi_io1_gpio071
+		     &espi_io2_gpio072
+		     &espi_io3_gpio073>;
+	pinctrl-names = "default";
+};
+
+/* Host facing devices on eSPI bus */
+&kbc0 {
+	status = "okay";
+};
+
+&acpi_ec0 {
+	status = "okay";
+};
+
+&acpi_ec1 {
+	status = "okay";
+};
+
+&emi0 {
+	status = "okay";
+};
+
+&p80bd0 {
+	status = "okay";
+};
+
+&crtc {
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart0_tx_gpio104 &uart0_rx_gpio105>;
+	pinctrl-names = "default";
+};
+
+&spi0 {
+	status = "okay";
+	compatible = "microchip,xec-qmspi-ldma";
+	clock-frequency = <12000000>;
+	lines = <2>;
+	chip-select = <0>;
+	pinctrl-0 = < &gpspi_cs_n_gpio116
+		      &gpspi_clk_gpio117
+		      &gpspi_io0_gpio074
+		      &gpspi_io1_gpio075
+		      &gpspi_wp_n_gpio076 >;
+	pinctrl-names = "default";
+
+	int_flash: sst25pf040@0 {
+		compatible ="jedec,spi-nor";
+		/*  4194304 bits = 512K Bytes */
+		size = <0x400000>;
+		label = "SST25PF040";
+		reg = <0>;
+		spi-max-frequency = <40000000>;
+		status = "okay";
+		jedec-id = [62 06 13];
+	};
+};
+
+&cros_kb_raw {
+	status = "okay";
+	/*
+	 * No KSO2 (It's inverted and implemented by GPIO for
+	 * CONFIG_KEYBOARD_COL2_INVERTED.)
+	 */
+	pinctrl-0 = <&ksi0_gpio017
+		     &ksi1_gpio020
+			 &ksi2_gpio021
+		     &ksi3_gpio026
+		     &ksi4_gpio027
+		     &ksi5_gpio030
+		     &ksi6_gpio031
+		     &ksi7_gpio032
+		     &kso00_gpio040
+		     &kso01_gpio045
+		     &kso03_gpio047
+		     &kso04_gpio107
+		     &kso05_gpio112
+		     &kso06_gpio113
+		     &kso07_gpio120
+		     &kso08_gpio121
+		     &kso09_gpio122
+		     &kso10_gpio123
+		     &kso11_gpio124
+		     &kso12_gpio125>;
+	pinctrl-names = "default";
+};
+
+/* Chrome design: KSI02 to H1 has not pull-up resistor */
+&ksi2_gpio021 {
+	bias-pull-up;
+};
+
+&adc0 {
+	status = "okay";
+	pinctrl-0 = <&adc00_gpio200
+		     &adc03_gpio203
+		     &adc04_gpio204
+		     &adc05_gpio205>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/boards/arm/mec1727/mec1727_defconfig b/zephyr/boards/arm/mec1727/mec1727_defconfig
new file mode 100644
index 0000000000..9aba7881ac
--- /dev/null
+++ b/zephyr/boards/arm/mec1727/mec1727_defconfig
@@ -0,0 +1,52 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Zephyr Kernel Configuration
+CONFIG_SOC_SERIES_MEC172X=y
+
+# Platform Configuration
+CONFIG_SOC_MEC172X_NSZ=y
+CONFIG_BOARD_MEC1727=y
+CONFIG_RTOS_TIMER=y
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=32768
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=32768
+
+# Serial Drivers
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Pinctrl Driver
+CONFIG_PINCTRL=y
+
+# GPIO Controller
+CONFIG_GPIO=y
+CONFIG_GPIO_GET_CONFIG=y
+
+# Clock configuration
+CONFIG_CLOCK_CONTROL=y
+
+# WATCHDOG configuration
+CONFIG_WATCHDOG=y
+
+# Power Management
+#CONFIG_PM=y
+#CONFIG_PM_POLICY_APP=y
+#CONFIG_UART_CONSOLE_INPUT_EXPIRED=y
+
+# BBRAM
+CONFIG_BBRAM=y
+
+# SPI
+CONFIG_SPI=y
+# MCHP build config error CONFIG_SPI_FLASH=y
+
+# Flash
+CONFIG_FLASH=y
+# disabling this causes build error: calling function to read JEDEC ID
+# MEC1727 internal SST25PF040 does not support SFDP
+CONFIG_FLASH_JESD216_API=y
diff --git a/zephyr/boards/arm/npcx7/Kconfig.board b/zephyr/boards/arm/npcx7/Kconfig.board
new file mode 100644
index 0000000000..b5c0134b75
--- /dev/null
+++ b/zephyr/boards/arm/npcx7/Kconfig.board
@@ -0,0 +1,10 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config BOARD_NPCX7
+	bool "NPCX7 Zephyr Baseboard"
+	depends on SOC_SERIES_NPCX7
+	# NPCX doesn't actually have enough ram for coverage, but this will
+	# allow generating initial 0 line coverage.
+	select HAS_COVERAGE_SUPPORT
diff --git a/zephyr/boards/arm/npcx7/Kconfig.defconfig b/zephyr/boards/arm/npcx7/Kconfig.defconfig
new file mode 100644
index 0000000000..afa9640b5a
--- /dev/null
+++ b/zephyr/boards/arm/npcx7/Kconfig.defconfig
@@ -0,0 +1,10 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if BOARD_NPCX7
+
+config BOARD
+	default "npcx7"
+
+endif # BOARD_NPCX7
diff --git a/zephyr/boards/arm/npcx7/board.cmake b/zephyr/boards/arm/npcx7/board.cmake
new file mode 100644
index 0000000000..e1d12397eb
--- /dev/null
+++ b/zephyr/boards/arm/npcx7/board.cmake
@@ -0,0 +1,5 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+set(NPCX_IMAGE_FILE ${PROJECT_BINARY_DIR}/zephyr.npcx.bin)
diff --git a/zephyr/boards/arm/npcx7/npcx7.dts b/zephyr/boards/arm/npcx7/npcx7.dts
new file mode 100644
index 0000000000..32e6704a95
--- /dev/null
+++ b/zephyr/boards/arm/npcx7/npcx7.dts
@@ -0,0 +1,67 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/dts-v1/;
+
+#include <cros/nuvoton/npcx7.dtsi>
+#include <dt-bindings/gpio_defines.h>
+#include <dt-bindings/gpio/nuvoton-npcx-gpio.h>
+#include <nuvoton/npcx7m7fc.dtsi>
+#include <nuvoton/npcx/npcx7/npcx7-pinctrl.dtsi>
+
+#define GPIO_VOLTAGE_1P8 NPCX_GPIO_VOLTAGE_1P8
+
+/ {
+	model = "NPCX7";
+
+	aliases {
+		i2c-0 = &i2c0_0;
+		i2c-1 = &i2c1_0;
+		i2c-2 = &i2c2_0;
+		i2c-3 = &i2c3_0;
+		i2c-5 = &i2c5_0;
+		i2c-7 = &i2c7_0;
+	};
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,console = &uart1;
+		zephyr,shell-uart = &uart1;
+		zephyr,flash = &flash0;
+		zephyr,flash-controller = &int_flash;
+		cros,rtc = &mtc;
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+	};
+
+	named-adc-channels {
+		compatible = "named-adc-channels";
+	};
+};
+
+&uart1 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart1_2_sin_sout_gp64_65>;
+	pinctrl-names = "default";
+};
+
+&pinctrl {
+	/*
+	 * TODO(b/232573074): Move pinctrl to set SHI pins to GPIO mode
+	 * upstream.
+	 */
+	/omit-if-no-ref/ shi_gpio_gp46_47_53_55: periph-shi-gpio {
+		pinmux = <&altc_shi_sl>;
+		pinmux-gpio;
+	};
+};
+
+/* PSL_OUT is fixed to GPIO85 in npcx7 series. */
+&power_ctrl_psl {
+	enable-gpios = <&gpio8 5 0>;
+};
diff --git a/zephyr/boards/arm/npcx7/npcx7_defconfig b/zephyr/boards/arm/npcx7/npcx7_defconfig
new file mode 100644
index 0000000000..09b6784eeb
--- /dev/null
+++ b/zephyr/boards/arm/npcx7/npcx7_defconfig
@@ -0,0 +1,46 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Zephyr Kernel Configuration
+CONFIG_SOC_SERIES_NPCX7=y
+
+# Platform Configuration
+CONFIG_BOARD_NPCX7=y
+
+# Serial Drivers
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Pinctrl Driver
+CONFIG_PINCTRL=y
+
+# GPIO Controller
+CONFIG_GPIO=y
+CONFIG_GPIO_GET_CONFIG=y
+
+# Clock configuration
+CONFIG_CLOCK_CONTROL=y
+
+# WATCHDOG configuration
+CONFIG_WATCHDOG=y
+
+# Power Management
+CONFIG_PM=y
+CONFIG_PM_DEVICE=y
+CONFIG_PM_POLICY_CUSTOM=y
+CONFIG_UART_CONSOLE_INPUT_EXPIRED=y
+
+# BBRAM
+CONFIG_BBRAM=y
+
+# SPI
+CONFIG_SPI=y
+
+# Flash
+CONFIG_FLASH=y
+CONFIG_FLASH_JESD216_API=y
diff --git a/zephyr/boards/arm/npcx9/Kconfig.board b/zephyr/boards/arm/npcx9/Kconfig.board
new file mode 100644
index 0000000000..64e02d2c92
--- /dev/null
+++ b/zephyr/boards/arm/npcx9/Kconfig.board
@@ -0,0 +1,10 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config BOARD_NPCX9
+	bool "NPCX9 Zephyr Board"
+	depends on SOC_NPCX9M3F || SOC_NPCX9M7F
+	# NPCX doesn't actually have enough ram for coverage, but this will
+	# allow generating initial 0 line coverage.
+	select HAS_COVERAGE_SUPPORT
diff --git a/zephyr/boards/arm/npcx9/Kconfig.defconfig b/zephyr/boards/arm/npcx9/Kconfig.defconfig
new file mode 100644
index 0000000000..22b5f397cd
--- /dev/null
+++ b/zephyr/boards/arm/npcx9/Kconfig.defconfig
@@ -0,0 +1,15 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if BOARD_NPCX9
+
+config BOARD
+	default "npcx9"
+
+if FLASH
+config PLATFORM_EC_CONSOLE_CMD_FLASH
+	default y
+endif # FLASH
+
+endif # BOARD_NPCX9
diff --git a/zephyr/boards/arm/npcx9/board.cmake b/zephyr/boards/arm/npcx9/board.cmake
new file mode 100644
index 0000000000..e5e2fedd4f
--- /dev/null
+++ b/zephyr/boards/arm/npcx9/board.cmake
@@ -0,0 +1,5 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+set(NPCX_IMAGE_FILE ${PROJECT_BINARY_DIR}/zephyr.npcx.bin)
diff --git a/zephyr/boards/arm/npcx9/npcx9.dtsi b/zephyr/boards/arm/npcx9/npcx9.dtsi
new file mode 100644
index 0000000000..4971699a13
--- /dev/null
+++ b/zephyr/boards/arm/npcx9/npcx9.dtsi
@@ -0,0 +1,168 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/gpio_defines.h>
+#include <dt-bindings/gpio/nuvoton-npcx-gpio.h>
+#include <nuvoton/npcx/npcx9/npcx9-pinctrl.dtsi>
+
+#define GPIO_VOLTAGE_1P8 NPCX_GPIO_VOLTAGE_1P8
+
+/ {
+	model = "NPCX9";
+
+	aliases {
+		i2c-0 = &i2c0_0;
+		i2c-1 = &i2c1_0;
+		i2c-2 = &i2c2_0;
+		i2c-3 = &i2c3_0;
+		i2c-5 = &i2c5_0;
+		i2c-7 = &i2c7_0;
+	};
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,console = &uart1;
+		zephyr,shell-uart = &uart1;
+		zephyr,flash = &flash0;
+		zephyr,flash-controller = &int_flash;
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+	};
+
+	named-adc-channels {
+		compatible = "named-adc-channels";
+	};
+};
+
+&uart1 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart1_2_sin_gp64 &uart1_2_sout_gp65>;
+	pinctrl-names = "default";
+};
+
+&pinctrl {
+	/*
+	 * TODO(b/232573074): Move pinctrl to set SHI pins to GPIO mode
+	 * upstream.
+	 */
+	 /omit-if-no-ref/ shi_gpio_gp46_47_53_55: periph-shi-gpio {
+		pinmux = <&altc_shi_sl>;
+		pinmux-gpio;
+	};
+
+	/* Keyboard peripheral interfaces */
+	/omit-if-no-ref/ ksi0_gpio_gp31: periph-kbscan-ksi0-gpio {
+		pinmux = <&alt7_no_ksi0_sl>;
+		pinmux-gpio;
+	};
+	/omit-if-no-ref/ ksi1_gpio_gp30: periph-kbscan-ksi1-gpio {
+		pinmux = <&alt7_no_ksi1_sl>;
+		pinmux-gpio;
+	};
+	/omit-if-no-ref/ ksi2_gpio_gp27: periph-kbscan-ksi2-gpio {
+		pinmux = <&alt7_no_ksi2_sl>;
+		pinmux-gpio;
+	};
+	/omit-if-no-ref/ ksi3_gpio_gp26: periph-kbscan-ksi3-gpio {
+		pinmux = <&alt7_no_ksi3_sl>;
+		pinmux-gpio;
+	};
+	/omit-if-no-ref/ ksi4_gpio_gp25: periph-kbscan-ksi4-gpio {
+		pinmux = <&alt7_no_ksi4_sl>;
+		pinmux-gpio;
+	};
+	/omit-if-no-ref/ ksi5_gpio_gp24: periph-kbscan-ksi5-gpio {
+		pinmux = <&alt7_no_ksi5_sl>;
+		pinmux-gpio;
+	};
+	/omit-if-no-ref/ ksi6_gpio_gp23: periph-kbscan-ksi6-gpio {
+		pinmux = <&alt7_no_ksi6_sl>;
+		pinmux-gpio;
+	};
+	/omit-if-no-ref/ ksi7_gpio_gp22: periph-kbscan-ksi7-gpio {
+		pinmux = <&alt7_no_ksi7_sl>;
+		pinmux-gpio;
+	};
+	/omit-if-no-ref/ kso00_gpio_gp21: periph-kbscan-kso00-gpio {
+		pinmux = <&alt8_no_kso00_sl>;
+		pinmux-gpio;
+	};
+	/omit-if-no-ref/ kso01_gpio_gp20: periph-kbscan-kso01-gpio {
+		pinmux = <&alt8_no_kso01_sl>;
+		pinmux-gpio;
+	};
+	/omit-if-no-ref/ kso02_gpio_gp17: periph-kbscan-kso02-gpio {
+		pinmux = <&alt8_no_kso02_sl>;
+		pinmux-gpio;
+	};
+	/omit-if-no-ref/ kso03_gpio_gp16: periph-kbscan-kso03-gpio {
+		pinmux = <&alt8_no_kso03_sl>;
+		pinmux-gpio;
+	};
+	/omit-if-no-ref/ kso04_gpio_gp15: periph-kbscan-kso04-gpio {
+		pinmux = <&alt8_no_kso04_sl>;
+		pinmux-gpio;
+	};
+	/omit-if-no-ref/ kso05_gpio_gp14: periph-kbscan-kso05-gpio {
+		pinmux = <&alt8_no_kso05_sl>;
+		pinmux-gpio;
+	};
+	/omit-if-no-ref/ kso06_gpio_gp13: periph-kbscan-kso06-gpio {
+		pinmux = <&alt8_no_kso06_sl>;
+		pinmux-gpio;
+	};
+	/omit-if-no-ref/ kso07_gpio_gp12: periph-kbscan-kso07-gpio {
+		pinmux = <&alt8_no_kso07_sl>;
+		pinmux-gpio;
+	};
+	/omit-if-no-ref/ kso08_gpio_gp11: periph-kbscan-kso08-gpio {
+		pinmux = <&alt9_no_kso08_sl>;
+		pinmux-gpio;
+	};
+	/omit-if-no-ref/ kso09_gpio_gp10: periph-kbscan-kso09-gpio {
+		pinmux = <&alt9_no_kso09_sl>;
+		pinmux-gpio;
+	};
+	/omit-if-no-ref/ kso10_gpio_gp07: periph-kbscan-kso10-gpio {
+		pinmux = <&alt9_no_kso10_sl>;
+		pinmux-gpio;
+	};
+	/omit-if-no-ref/ kso11_gpio_gp06: periph-kbscan-kso11-gpio {
+		pinmux = <&alt9_no_kso11_sl>;
+		pinmux-gpio;
+	};
+	/omit-if-no-ref/ kso12_gpio_gp05: periph-kbscan-kso12-gpio {
+		pinmux = <&alt9_no_kso12_sl>;
+		pinmux-gpio;
+	};
+	/omit-if-no-ref/ kso13_gpio_gp04: periph-kbscan-kso13-gpio {
+		pinmux = <&alt9_no_kso13_sl>;
+		pinmux-gpio;
+	};
+	/omit-if-no-ref/ kso14_gpio_gp82: periph-kbscan-kso14-gpio {
+		pinmux = <&alt9_no_kso14_sl>;
+		pinmux-gpio;
+	};
+	/omit-if-no-ref/ kso15_gpio_gp83: periph-kbscan-kso15-gpio {
+		pinmux = <&alt9_no_kso15_sl>;
+		pinmux-gpio;
+	};
+	/omit-if-no-ref/ kso16_gpio_gp03: periph-kbscan-kso16-gpio {
+		pinmux = <&alta_no_kso16_sl>;
+		pinmux-gpio;
+	};
+	/omit-if-no-ref/ kso17_gpio_gpb1: periph-kbscan-kso17-gpio {
+		pinmux = <&alta_no_kso17_sl>;
+		pinmux-gpio;
+	};
+};
+
+/* PSL_OUT is fixed to GPIO85 in npcx9 series. */
+&power_ctrl_psl {
+	enable-gpios = <&gpio8 5 0>;
+};
diff --git a/zephyr/boards/arm/npcx9/npcx9m3f.dts b/zephyr/boards/arm/npcx9/npcx9m3f.dts
new file mode 100644
index 0000000000..a51aeccae1
--- /dev/null
+++ b/zephyr/boards/arm/npcx9/npcx9m3f.dts
@@ -0,0 +1,10 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/dts-v1/;
+
+#include <cros/nuvoton/npcx9.dtsi>
+#include <nuvoton/npcx9m3f.dtsi>
+#include "npcx9.dtsi"
diff --git a/zephyr/boards/arm/npcx9/npcx9m3f_defconfig b/zephyr/boards/arm/npcx9/npcx9m3f_defconfig
new file mode 100644
index 0000000000..46ef3925e9
--- /dev/null
+++ b/zephyr/boards/arm/npcx9/npcx9m3f_defconfig
@@ -0,0 +1,47 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Zephyr Kernel Configuration
+CONFIG_SOC_SERIES_NPCX9=y
+CONFIG_SOC_NPCX9M3F=y
+
+# Platform Configuration
+CONFIG_BOARD_NPCX9=y
+
+# Serial Drivers
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Pinctrl Driver
+CONFIG_PINCTRL=y
+
+# GPIO Controller
+CONFIG_GPIO=y
+CONFIG_GPIO_GET_CONFIG=y
+
+# Clock configuration
+CONFIG_CLOCK_CONTROL=y
+
+# WATCHDOG configuration
+CONFIG_WATCHDOG=y
+
+# Power Management
+CONFIG_PM=y
+CONFIG_PM_DEVICE=y
+CONFIG_PM_POLICY_CUSTOM=y
+CONFIG_UART_CONSOLE_INPUT_EXPIRED=y
+
+# BBRAM
+CONFIG_BBRAM=y
+
+# SPI
+CONFIG_SPI=y
+
+# Flash
+CONFIG_FLASH=y
+CONFIG_FLASH_JESD216_API=y
diff --git a/zephyr/boards/arm/npcx9/npcx9m7f.dts b/zephyr/boards/arm/npcx9/npcx9m7f.dts
new file mode 100644
index 0000000000..2f02cb9887
--- /dev/null
+++ b/zephyr/boards/arm/npcx9/npcx9m7f.dts
@@ -0,0 +1,45 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/dts-v1/;
+
+#include <cros/nuvoton/npcx9.dtsi>
+#include <nuvoton/npcx9m7f.dtsi>
+#include "npcx9.dtsi"
+
+/*
+ * The NPCX9m7F includes 384 kB of code RAM, and 1 MB flash. Padding
+ * is added to make the image the same size as the internal flash. This
+ * is required to support the flashrom tool which requires an image that
+ * matches the full internal flash size.
+ */
+&binman {
+	wp-ro {
+		/*
+		 * wp-ro must match a block protect region supported by
+		 * by the internal flash device. In practice, that's
+		 * 512 KiB starting at address 0.
+		 */
+		offset = <0x0>;
+		size = <0x80000>;
+	};
+	ec-rw {
+		offset = <0x80000>;
+		size = <0x50000>;
+		rw-fw {
+			rw-fwid {
+				/* Fix the lcoation of the FWID to the
+				 * last 32 bytes of the flash. This
+				 * ensures the RW entries in the FMAP
+				 * stored in the RO section of flash
+				 * are always correct.
+				 */
+				offset = <(0x50000 - 32)>;
+			};
+		};
+	};
+	pad-byte = <0xff>;
+	pad-after = <0x30000>;
+};
diff --git a/zephyr/boards/arm/npcx9/npcx9m7f_defconfig b/zephyr/boards/arm/npcx9/npcx9m7f_defconfig
new file mode 100644
index 0000000000..2485d6e77d
--- /dev/null
+++ b/zephyr/boards/arm/npcx9/npcx9m7f_defconfig
@@ -0,0 +1,47 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Zephyr Kernel Configuration
+CONFIG_SOC_SERIES_NPCX9=y
+CONFIG_SOC_NPCX9M7F=y
+
+# Platform Configuration
+CONFIG_BOARD_NPCX9=y
+
+# Serial Drivers
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Pinctrl Driver
+CONFIG_PINCTRL=y
+
+# GPIO Controller
+CONFIG_GPIO=y
+CONFIG_GPIO_GET_CONFIG=y
+
+# Clock configuration
+CONFIG_CLOCK_CONTROL=y
+
+# WATCHDOG configuration
+CONFIG_WATCHDOG=y
+
+# Power Management
+CONFIG_PM=y
+CONFIG_PM_DEVICE=y
+CONFIG_PM_POLICY_CUSTOM=y
+CONFIG_UART_CONSOLE_INPUT_EXPIRED=y
+
+# BBRAM
+CONFIG_BBRAM=y
+
+# SPI
+CONFIG_SPI=y
+
+# Flash
+CONFIG_FLASH=y
+CONFIG_FLASH_JESD216_API=y
diff --git a/zephyr/boards/arm/npcx_evb/Kconfig.board b/zephyr/boards/arm/npcx_evb/Kconfig.board
new file mode 100644
index 0000000000..00b6b75f72
--- /dev/null
+++ b/zephyr/boards/arm/npcx_evb/Kconfig.board
@@ -0,0 +1,18 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Note: this Zephyr board more closely represents the Chrome OS
+# concept of a baseboard.  Zephyr boards and Chrome OS boards do not
+# have a 1:1 mapping.
+config BOARD_NPCX7_EVB
+	bool "NPCX7 Evaluation Board"
+	depends on SOC_NPCX7M6FB || SOC_NPCX7M6FC || SOC_NPCX7M7FC
+	# Allow generating initial 0 line coverage.
+	select HAS_COVERAGE_SUPPORT
+
+config BOARD_NPCX9_EVB
+	bool "NPCX9 Evaluation Board"
+	depends on SOC_NPCX9M3F || SOC_NPCX9M6F || SOC_NPCX9M7F
+	# Allow generating initial 0 line coverage.
+	select HAS_COVERAGE_SUPPORT
diff --git a/zephyr/boards/arm/npcx_evb/Kconfig.defconfig b/zephyr/boards/arm/npcx_evb/Kconfig.defconfig
new file mode 100644
index 0000000000..512a8403e7
--- /dev/null
+++ b/zephyr/boards/arm/npcx_evb/Kconfig.defconfig
@@ -0,0 +1,7 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config BOARD
+	default "npcx7_evb" if BOARD_NPCX7_EVB
+	default "npcx9_evb" if BOARD_NPCX9_EVB
diff --git a/zephyr/boards/arm/npcx_evb/npcx7_evb.dts b/zephyr/boards/arm/npcx_evb/npcx7_evb.dts
new file mode 100644
index 0000000000..75ad9e33a6
--- /dev/null
+++ b/zephyr/boards/arm/npcx_evb/npcx7_evb.dts
@@ -0,0 +1,29 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/dts-v1/;
+
+#include <cros/nuvoton/npcx7.dtsi>
+#include <nuvoton/npcx/npcx7/npcx7-pinctrl.dtsi>
+
+/*
+ * #include <nuvoton/npcx7m6fb.dtsi>
+ * #include <nuvoton/npcx7m6fc.dtsi>
+ * #include <nuvoton/npcx7m7fc.dtsi>
+ */
+#include <nuvoton/npcx7m6fc.dtsi>
+#include "npcx_evb.dtsi"
+
+&uart1 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart1_2_sin_sout_gp64_65>;
+	pinctrl-names = "default";
+};
+
+/* PSL_OUT is fixed to GPIO85 in npcx7 series. */
+&power_ctrl_psl {
+	enable-gpios = <&gpio8 5 0>;
+};
diff --git a/zephyr/boards/arm/npcx_evb/npcx7_evb_defconfig b/zephyr/boards/arm/npcx_evb/npcx7_evb_defconfig
new file mode 100644
index 0000000000..9cd1465742
--- /dev/null
+++ b/zephyr/boards/arm/npcx_evb/npcx7_evb_defconfig
@@ -0,0 +1,54 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Zephyr Kernel Configuration
+CONFIG_SOC_SERIES_NPCX7=y
+# NPCX7 soc list
+#  CONFIG_SOC_NPCX7M6FB
+#  CONFIG_SOC_NPCX7M6FC
+#  CONFIG_SOC_NPCX7M7FC
+CONFIG_SOC_NPCX7M6FC=y
+
+# Platform Configuration
+CONFIG_BOARD_NPCX7_EVB=y
+
+# Serial Drivers
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Pinctrl Driver
+CONFIG_PINCTRL=y
+
+# GPIO Controller
+CONFIG_GPIO=y
+CONFIG_GPIO_GET_CONFIG=y
+
+# Clock configuration
+CONFIG_CLOCK_CONTROL=y
+
+# WATCHDOG configuration
+CONFIG_WATCHDOG=y
+
+# I2C
+CONFIG_I2C=y
+
+# Power Management
+CONFIG_PM=y
+CONFIG_PM_DEVICE=y
+CONFIG_PM_POLICY_CUSTOM=y
+CONFIG_UART_CONSOLE_INPUT_EXPIRED=y
+
+# BBRAM
+CONFIG_BBRAM=y
+
+# SPI
+CONFIG_SPI=y
+
+# Flash
+CONFIG_FLASH=y
+CONFIG_FLASH_JESD216_API=y
diff --git a/zephyr/boards/arm/npcx_evb/npcx9_evb.dts b/zephyr/boards/arm/npcx_evb/npcx9_evb.dts
new file mode 100644
index 0000000000..1def8dc48f
--- /dev/null
+++ b/zephyr/boards/arm/npcx_evb/npcx9_evb.dts
@@ -0,0 +1,30 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/dts-v1/;
+
+#include <cros/nuvoton/npcx9.dtsi>
+#include <nuvoton/npcx/npcx9/npcx9-pinctrl.dtsi>
+
+/*
+ * #include <nuvoton/npcx9m3f.dtsi>
+ * #include <nuvoton/npcx9m6f.dtsi>
+ * #include <nuvoton/npcx9m7f.dtsi>
+ */
+#include <nuvoton/npcx9m6f.dtsi>
+#include "npcx_evb.dtsi"
+
+&uart1 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart1_2_sin_gp64
+		     &uart1_2_sout_gp65>;
+	pinctrl-names = "default";
+};
+
+/* PSL_OUT is fixed to GPIO85 in npcx9 series. */
+&power_ctrl_psl {
+	enable-gpios = <&gpio8 5 0>;
+};
diff --git a/zephyr/boards/arm/npcx_evb/npcx9_evb_defconfig b/zephyr/boards/arm/npcx_evb/npcx9_evb_defconfig
new file mode 100644
index 0000000000..7da95916df
--- /dev/null
+++ b/zephyr/boards/arm/npcx_evb/npcx9_evb_defconfig
@@ -0,0 +1,51 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Zephyr Kernel Configuration
+CONFIG_SOC_SERIES_NPCX9=y
+# NPCX9 soc list
+#  CONFIG_SOC_NPCX9M3F
+#  CONFIG_SOC_NPCX9M6F
+#  CONFIG_SOC_NPCX9M7F
+CONFIG_SOC_NPCX9M6F=y
+
+# Platform Configuration
+CONFIG_BOARD_NPCX9_EVB=y
+
+# Serial Drivers
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Pinctrl Driver
+CONFIG_PINCTRL=y
+
+# GPIO Controller
+CONFIG_GPIO=y
+CONFIG_GPIO_GET_CONFIG=y
+
+# Clock configuration
+CONFIG_CLOCK_CONTROL=y
+
+# WATCHDOG configuration
+CONFIG_WATCHDOG=y
+
+# Power Management
+CONFIG_PM=y
+CONFIG_PM_DEVICE=y
+CONFIG_PM_POLICY_CUSTOM=y
+CONFIG_UART_CONSOLE_INPUT_EXPIRED=y
+
+# BBRAM
+CONFIG_BBRAM=y
+
+# SPI
+CONFIG_SPI=y
+
+# Flash
+CONFIG_FLASH=y
+CONFIG_FLASH_JESD216_API=y
diff --git a/zephyr/boards/arm/npcx_evb/npcx_evb.dtsi b/zephyr/boards/arm/npcx_evb/npcx_evb.dtsi
new file mode 100644
index 0000000000..615df09a64
--- /dev/null
+++ b/zephyr/boards/arm/npcx_evb/npcx_evb.dtsi
@@ -0,0 +1,167 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/gpio_defines.h>
+
+/ {
+	model = "Nuvoton NPCX Evaluation Board";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,console = &uart1;
+		zephyr,shell-uart = &uart1;
+		zephyr,flash = &flash0;
+		zephyr,flash-controller = &int_flash;
+		cros,rtc = &mtc;
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		i2c_evb_0_0 {
+			i2c-port = <&i2c0_0>;
+			enum-names = "I2C_PORT_EVB_0";
+		};
+		i2c_evb_1_0 {
+			i2c-port = <&i2c1_0>;
+			enum-names = "I2C_PORT_EVB_1";
+		};
+		i2c_evb_2_0 {
+			i2c-port = <&i2c2_0>;
+			enum-names = "I2C_PORT_EVB_2";
+		};
+		i2c_evb_3_0 {
+			i2c-port = <&i2c3_0>;
+			enum-names = "I2C_PORT_EVB_3";
+		};
+		i2c_evb_7_0 {
+			i2c-port = <&i2c7_0>;
+			enum-names = "I2C_PORT_EVB_7";
+		};
+	};
+
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		adc_ch_0 {
+			enum-name = "ADC_EVB_CH_0";
+			io-channels = <&adc0 0>;
+		};
+		adc_ch_1 {
+			enum-name = "ADC_EVB_CH_1";
+			io-channels = <&adc0 1>;
+		};
+		adc_ch_2 {
+			enum-name = "ADC_EVB_CH_2";
+			io-channels = <&adc0 2>;
+		};
+		adc_ch_3 {
+			enum-name = "ADC_EVB_CH_3";
+			io-channels = <&adc0 3>;
+		};
+		adc_ch_4 {
+			enum-name = "ADC_EVB_CH_4";
+			io-channels = <&adc0 4>;
+		};
+	};
+};
+
+&i2c0_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>;
+	pinctrl-names = "default";
+};
+
+&i2c_ctrl0 {
+	status = "okay";
+};
+
+&i2c1_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>;
+	pinctrl-names = "default";
+};
+
+&i2c_ctrl1 {
+	status = "okay";
+};
+
+&i2c2_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	pinctrl-0 = <&i2c2_0_sda_scl_gp91_92>;
+	pinctrl-names = "default";
+};
+
+&i2c_ctrl2 {
+	status = "okay";
+};
+
+&i2c3_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>;
+	pinctrl-names = "default";
+};
+
+&i2c_ctrl3 {
+	status = "okay";
+};
+
+&i2c7_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>;
+	pinctrl-names = "default";
+};
+
+&i2c_ctrl7 {
+	status = "okay";
+};
+
+&adc0 {
+	status = "okay";
+	pinctrl-0 = <&adc0_chan0_gp45
+		     &adc0_chan1_gp44
+		     &adc0_chan2_gp43
+		     &adc0_chan3_gp42
+		     &adc0_chan4_gp41>;
+	pinctrl-names = "default";
+};
+
+&espi0 {
+	status = "okay";
+	pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>;
+	pinctrl-names = "default";
+};
+
+&cros_kb_raw {
+	status = "okay";
+	pinctrl-0 = <&ksi0_gp31
+		     &ksi1_gp30
+		     &ksi2_gp27
+		     &ksi3_gp26
+		     &ksi4_gp25
+		     &ksi5_gp24
+		     &ksi6_gp23
+		     &ksi7_gp22
+		     &kso00_gp21
+		     &kso01_gp20
+		     &kso02_gp17
+		     &kso03_gp16
+		     &kso04_gp15
+		     &kso05_gp14
+		     &kso06_gp13
+		     &kso07_gp12
+		     &kso08_gp11
+		     &kso09_gp10
+		     &kso10_gp07
+		     &kso11_gp06
+		     &kso12_gp05
+		     >;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/boards/arm/stm32g4/Kconfig.board b/zephyr/boards/arm/stm32g4/Kconfig.board
new file mode 100644
index 0000000000..115115b5fc
--- /dev/null
+++ b/zephyr/boards/arm/stm32g4/Kconfig.board
@@ -0,0 +1,10 @@
+# Copyright 2023 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config BOARD_STM32G4_G473
+	bool "STM32G473"
+	depends on SOC_STM32G473XX
+	# Enables support for the STM32 HAL drivers
+	select HAS_STM32CUBE
+	select USE_STM32_HAL_CORTEX
diff --git a/zephyr/boards/arm/stm32g4/Kconfig.defconfig b/zephyr/boards/arm/stm32g4/Kconfig.defconfig
new file mode 100644
index 0000000000..f22cbf7879
--- /dev/null
+++ b/zephyr/boards/arm/stm32g4/Kconfig.defconfig
@@ -0,0 +1,6 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config BOARD
+	default "stm32g473" if BOARD_STM32G4_G473
diff --git a/zephyr/boards/arm/stm32g4/stm32g473.dts b/zephyr/boards/arm/stm32g4/stm32g473.dts
new file mode 100644
index 0000000000..0c8c63f936
--- /dev/null
+++ b/zephyr/boards/arm/stm32g4/stm32g473.dts
@@ -0,0 +1,18 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/dts-v1/;
+
+#include <st/g4/stm32g473Xc.dtsi>
+#include <st/g4/stm32g473m(b-c-e)tx-pinctrl.dtsi>
+
+/ {
+	model = "STMicroelectronics STM32G473";
+	compatible = "st,stm32g473";
+
+	chosen {
+		zephyr,sram = &sram0;
+	};
+};
diff --git a/zephyr/boards/arm/stm32g4/stm32g473_defconfig b/zephyr/boards/arm/stm32g4/stm32g473_defconfig
new file mode 100644
index 0000000000..5df31bb6f0
--- /dev/null
+++ b/zephyr/boards/arm/stm32g4/stm32g473_defconfig
@@ -0,0 +1,32 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+
+# SOC Config
+CONFIG_ARM_MPU=y
+CONFIG_SOC_SERIES_STM32G4X=y
+CONFIG_SOC_STM32G473XX=y
+
+# Pinctrl Driver
+CONFIG_PINCTRL=y
+
+# GPIO Controller
+CONFIG_GPIO=y
+
+# Enable sys_reboot
+CONFIG_REBOOT=y
+
+# Clock configuration
+CONFIG_CLOCK_CONTROL=y
+
+# Watchdog configuration
+CONFIG_WATCHDOG=y
+
+# Enable HW Stack protection
+CONFIG_HW_STACK_PROTECTION=y
+
+# USB configuration
+CONFIG_USB_DEVICE_MANUFACTURER="Google Inc."
+CONFIG_USB_DEVICE_VID=0x18d1
+
diff --git a/zephyr/boards/riscv/it8xxx2/Kconfig.board b/zephyr/boards/riscv/it8xxx2/Kconfig.board
new file mode 100644
index 0000000000..157d269c77
--- /dev/null
+++ b/zephyr/boards/riscv/it8xxx2/Kconfig.board
@@ -0,0 +1,14 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# "BOARD" below refers to a Zephyr board, which does not have a 1:1
+# mapping with the Chrome OS concept of a board.  By Zephyr's
+# conventions, we'll still call it "BOARD_*" to make this more
+# applicable to be upstreamed, even though this code is shared by all
+# projects using Trogdor baseboard.
+config BOARD_IT8XXX2
+	bool "IT8XXX2 Zephyr Board"
+	depends on SOC_IT8XXX2
+	# Allow generating initial 0 line coverage.
+	select HAS_COVERAGE_SUPPORT
diff --git a/zephyr/boards/riscv/it8xxx2/Kconfig.defconfig b/zephyr/boards/riscv/it8xxx2/Kconfig.defconfig
new file mode 100644
index 0000000000..251fd93c4e
--- /dev/null
+++ b/zephyr/boards/riscv/it8xxx2/Kconfig.defconfig
@@ -0,0 +1,70 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if BOARD_IT8XXX2
+
+config BOARD
+	default "it8xxx2"
+
+choice PLATFORM_EC_HOSTCMD_DEBUG_MODE_CHOICE
+	default HCDEBUG_OFF
+endchoice # PLATFORM_EC_HOSTCMD_DEBUG_MODE_CHOICE
+
+config CROS_EC_HOOK_TICK_INTERVAL
+	default 500000
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 32768
+
+config SYS_CLOCK_TICKS_PER_SEC
+	default 32768
+
+if ADC
+config PLATFORM_EC_ADC_RESOLUTION
+	default 10
+endif # ADC
+
+if CONSOLE
+config UART_CONSOLE
+	default y
+	depends on SERIAL
+endif # CONSOLE
+
+if FLASH
+config PLATFORM_EC_CONSOLE_CMD_FLASH
+	default y
+endif # FLASH
+
+if SERIAL
+config UART_INTERRUPT_DRIVEN
+	default y
+endif # SERIAL
+
+if SHELL
+config SHELL_TAB
+	default y
+config SHELL_TAB_AUTOCOMPLETION
+	default y
+config SHELL_HISTORY
+	default y
+endif # SHELL
+
+if WATCHDOG
+config PLATFORM_EC_WATCHDOG_PERIOD_MS
+	default 2500
+config WDT_ITE_WARNING_LEADING_TIME_MS
+	default 500
+config WDT_ITE_REDUCE_WARNING_LEADING_TIME
+	default y
+endif # WATCHDOG
+
+if PLATFORM_EC_VBOOT_HASH
+config SOC_IT8XXX2_SHA256_HW_ACCELERATE
+	default y
+choice PLATFORM_EC_SHA256_MODE
+	default PLATFORM_EC_SHA256_HW_ACCELERATE if SOC_IT8XXX2_SHA256_HW_ACCELERATE
+endchoice
+endif # PLATFORM_EC_VBOOT_HASH
+
+endif # BOARD_IT8XXX2
diff --git a/zephyr/boards/riscv/it8xxx2/it81202bx.dts b/zephyr/boards/riscv/it8xxx2/it81202bx.dts
new file mode 100644
index 0000000000..cb8084c560
--- /dev/null
+++ b/zephyr/boards/riscv/it8xxx2/it81202bx.dts
@@ -0,0 +1,9 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/dts-v1/;
+
+#include <ite/it81xx2.dtsi>
+#include "it8xxx2.dts"
diff --git a/zephyr/boards/riscv/it8xxx2/it81202bx_defconfig b/zephyr/boards/riscv/it8xxx2/it81202bx_defconfig
new file mode 100644
index 0000000000..82a8a0f63f
--- /dev/null
+++ b/zephyr/boards/riscv/it8xxx2/it81202bx_defconfig
@@ -0,0 +1,35 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Zephyr Kernel Configuration
+CONFIG_SOC_SERIES_RISCV32_IT8XXX2=y
+CONFIG_SOC_IT8XXX2=y
+CONFIG_SOC_IT81202_BX=y
+
+# Platform Configuration
+CONFIG_BOARD_IT8XXX2=y
+
+# Power Management
+CONFIG_PM=y
+CONFIG_PM_DEVICE=y
+CONFIG_PM_POLICY_CUSTOM=y
+
+# Console
+CONFIG_CONSOLE=y
+
+# GPIO Controller
+CONFIG_GPIO=y
+CONFIG_GPIO_GET_CONFIG=y
+
+# Clock Controller
+CONFIG_CLOCK_CONTROL=n
+
+# Serial Drivers
+CONFIG_SERIAL=y
+
+# WATCHDOG configuration
+CONFIG_WATCHDOG=y
+
+# BBRAM
+CONFIG_BBRAM=y
diff --git a/zephyr/boards/riscv/it8xxx2/it81202cx.dts b/zephyr/boards/riscv/it8xxx2/it81202cx.dts
new file mode 100644
index 0000000000..fe3e5f6b8b
--- /dev/null
+++ b/zephyr/boards/riscv/it8xxx2/it81202cx.dts
@@ -0,0 +1,10 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/dts-v1/;
+
+#include <ite/it81xx2.dtsi>
+#include <ite/it81202cx.dtsi>
+#include "it8xxx2.dts"
diff --git a/zephyr/boards/riscv/it8xxx2/it81202cx_defconfig b/zephyr/boards/riscv/it8xxx2/it81202cx_defconfig
new file mode 100644
index 0000000000..45cc267eee
--- /dev/null
+++ b/zephyr/boards/riscv/it8xxx2/it81202cx_defconfig
@@ -0,0 +1,35 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Zephyr Kernel Configuration
+CONFIG_SOC_SERIES_RISCV32_IT8XXX2=y
+CONFIG_SOC_IT8XXX2=y
+CONFIG_SOC_IT81202_CX=y
+
+# Platform Configuration
+CONFIG_BOARD_IT8XXX2=y
+
+# Power Management
+CONFIG_PM=y
+CONFIG_PM_DEVICE=y
+CONFIG_PM_POLICY_CUSTOM=y
+
+# Console
+CONFIG_CONSOLE=y
+
+# GPIO Controller
+CONFIG_GPIO=y
+CONFIG_GPIO_GET_CONFIG=y
+
+# Clock Controller
+CONFIG_CLOCK_CONTROL=n
+
+# Serial Drivers
+CONFIG_SERIAL=y
+
+# WATCHDOG configuration
+CONFIG_WATCHDOG=y
+
+# BBRAM
+CONFIG_BBRAM=y
diff --git a/zephyr/boards/riscv/it8xxx2/it81302bx.dts b/zephyr/boards/riscv/it8xxx2/it81302bx.dts
new file mode 100644
index 0000000000..cb8084c560
--- /dev/null
+++ b/zephyr/boards/riscv/it8xxx2/it81302bx.dts
@@ -0,0 +1,9 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/dts-v1/;
+
+#include <ite/it81xx2.dtsi>
+#include "it8xxx2.dts"
diff --git a/zephyr/boards/riscv/it8xxx2/it81302bx_defconfig b/zephyr/boards/riscv/it8xxx2/it81302bx_defconfig
new file mode 100644
index 0000000000..6cfac9eeb5
--- /dev/null
+++ b/zephyr/boards/riscv/it8xxx2/it81302bx_defconfig
@@ -0,0 +1,35 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Zephyr Kernel Configuration
+CONFIG_SOC_SERIES_RISCV32_IT8XXX2=y
+CONFIG_SOC_IT8XXX2=y
+CONFIG_SOC_IT81302_BX=y
+
+# Platform Configuration
+CONFIG_BOARD_IT8XXX2=y
+
+# Power Management
+CONFIG_PM=y
+CONFIG_PM_DEVICE=y
+CONFIG_PM_POLICY_CUSTOM=y
+
+# Console
+CONFIG_CONSOLE=y
+
+# GPIO Controller
+CONFIG_GPIO=y
+CONFIG_GPIO_GET_CONFIG=y
+
+# Clock Controller
+CONFIG_CLOCK_CONTROL=n
+
+# Serial Drivers
+CONFIG_SERIAL=y
+
+# WATCHDOG configuration
+CONFIG_WATCHDOG=y
+
+# BBRAM
+CONFIG_BBRAM=y
diff --git a/zephyr/boards/riscv/it8xxx2/it81302cx.dts b/zephyr/boards/riscv/it8xxx2/it81302cx.dts
new file mode 100644
index 0000000000..c452bb5a68
--- /dev/null
+++ b/zephyr/boards/riscv/it8xxx2/it81302cx.dts
@@ -0,0 +1,10 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/dts-v1/;
+
+#include <ite/it81xx2.dtsi>
+#include <ite/it81302cx.dtsi>
+#include "it8xxx2.dts"
diff --git a/zephyr/boards/riscv/it8xxx2/it81302cx_defconfig b/zephyr/boards/riscv/it8xxx2/it81302cx_defconfig
new file mode 100644
index 0000000000..95b38a61dc
--- /dev/null
+++ b/zephyr/boards/riscv/it8xxx2/it81302cx_defconfig
@@ -0,0 +1,35 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Zephyr Kernel Configuration
+CONFIG_SOC_SERIES_RISCV32_IT8XXX2=y
+CONFIG_SOC_IT8XXX2=y
+CONFIG_SOC_IT81302_CX=y
+
+# Platform Configuration
+CONFIG_BOARD_IT8XXX2=y
+
+# Power Management
+CONFIG_PM=y
+CONFIG_PM_DEVICE=y
+CONFIG_PM_POLICY_CUSTOM=y
+
+# Console
+CONFIG_CONSOLE=y
+
+# GPIO Controller
+CONFIG_GPIO=y
+CONFIG_GPIO_GET_CONFIG=y
+
+# Clock Controller
+CONFIG_CLOCK_CONTROL=n
+
+# Serial Drivers
+CONFIG_SERIAL=y
+
+# WATCHDOG configuration
+CONFIG_WATCHDOG=y
+
+# BBRAM
+CONFIG_BBRAM=y
diff --git a/zephyr/boards/riscv/it8xxx2/it82202ax-512.dts b/zephyr/boards/riscv/it8xxx2/it82202ax-512.dts
new file mode 100644
index 0000000000..09fd4a0e2c
--- /dev/null
+++ b/zephyr/boards/riscv/it8xxx2/it82202ax-512.dts
@@ -0,0 +1,40 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/dts-v1/;
+
+#include <ite/it82xx2.dtsi>
+#include <ite/it82202ax-512.dtsi>
+#include "it8xxx2.dts"
+
+/ {
+	/* it82xx2/512 has 512KB of flash. */
+	binman {
+		wp-ro {
+			offset = <0x0>;
+			size = <0x40000>;
+
+			pstate {
+				offset = <(0x40000 - 4096)>;
+			};
+		};
+		ec-rw {
+			offset = <0x40000>;
+			size = <0x40000>;
+			rw-fw {
+				rw-fwid {
+					/* Fix the location of the FWID to the
+					 * last 32 bytes of the flash. This
+					 * ensures the RW entries in the FMAP
+					 * stored in the RO section of flash
+					 * are always correct.
+					 */
+					offset = <(0x40000 - 32)>;
+				};
+			};
+		};
+		pad-after = <0>;
+	};
+};
diff --git a/zephyr/boards/riscv/it8xxx2/it82202ax-512_defconfig b/zephyr/boards/riscv/it8xxx2/it82202ax-512_defconfig
new file mode 100644
index 0000000000..5750814a5a
--- /dev/null
+++ b/zephyr/boards/riscv/it8xxx2/it82202ax-512_defconfig
@@ -0,0 +1,35 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Zephyr Kernel Configuration
+CONFIG_SOC_SERIES_RISCV32_IT8XXX2=y
+CONFIG_SOC_IT8XXX2=y
+CONFIG_SOC_IT82202_AX=y
+
+# Platform Configuration
+CONFIG_BOARD_IT8XXX2=y
+
+# Power Management
+CONFIG_PM=y
+CONFIG_PM_DEVICE=y
+CONFIG_PM_POLICY_CUSTOM=y
+
+# Console
+CONFIG_CONSOLE=y
+
+# GPIO Controller
+CONFIG_GPIO=y
+CONFIG_GPIO_GET_CONFIG=y
+
+# Clock Controller
+CONFIG_CLOCK_CONTROL=n
+
+# Serial Drivers
+CONFIG_SERIAL=y
+
+# WATCHDOG configuration
+CONFIG_WATCHDOG=y
+
+# BBRAM
+CONFIG_BBRAM=y
diff --git a/zephyr/boards/riscv/it8xxx2/it82202ax.dts b/zephyr/boards/riscv/it8xxx2/it82202ax.dts
new file mode 100644
index 0000000000..b6ed731405
--- /dev/null
+++ b/zephyr/boards/riscv/it8xxx2/it82202ax.dts
@@ -0,0 +1,9 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/dts-v1/;
+
+#include <ite/it82xx2.dtsi>
+#include "it8xxx2.dts"
diff --git a/zephyr/boards/riscv/it8xxx2/it82202ax_defconfig b/zephyr/boards/riscv/it8xxx2/it82202ax_defconfig
new file mode 100644
index 0000000000..5750814a5a
--- /dev/null
+++ b/zephyr/boards/riscv/it8xxx2/it82202ax_defconfig
@@ -0,0 +1,35 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Zephyr Kernel Configuration
+CONFIG_SOC_SERIES_RISCV32_IT8XXX2=y
+CONFIG_SOC_IT8XXX2=y
+CONFIG_SOC_IT82202_AX=y
+
+# Platform Configuration
+CONFIG_BOARD_IT8XXX2=y
+
+# Power Management
+CONFIG_PM=y
+CONFIG_PM_DEVICE=y
+CONFIG_PM_POLICY_CUSTOM=y
+
+# Console
+CONFIG_CONSOLE=y
+
+# GPIO Controller
+CONFIG_GPIO=y
+CONFIG_GPIO_GET_CONFIG=y
+
+# Clock Controller
+CONFIG_CLOCK_CONTROL=n
+
+# Serial Drivers
+CONFIG_SERIAL=y
+
+# WATCHDOG configuration
+CONFIG_WATCHDOG=y
+
+# BBRAM
+CONFIG_BBRAM=y
diff --git a/zephyr/boards/riscv/it8xxx2/it8xxx2.dts b/zephyr/boards/riscv/it8xxx2/it8xxx2.dts
new file mode 100644
index 0000000000..422821d478
--- /dev/null
+++ b/zephyr/boards/riscv/it8xxx2/it8xxx2.dts
@@ -0,0 +1,45 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <cros/ite/it8xxx2.dtsi>
+#include <dt-bindings/gpio_defines.h>
+#include <dt-bindings/gpio/ite-it8xxx2-gpio.h>
+#include <ite/it8xxx2-pinctrl-map.dtsi>
+
+#define GPIO_VOLTAGE_1P8 IT8XXX2_GPIO_VOLTAGE_1P8
+
+/ {
+	model = "Google IT8XXX2 Baseboard";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,console = &uart1;
+		zephyr,shell-uart = &uart1;
+		zephyr,flash = &flash0;
+		zephyr,flash-controller = &flashctrl;
+	};
+
+	/* Override keyboard scanning */
+	soc {
+		/delete-node/ kscan@f01d00;
+	};
+};
+
+&uart1 {
+	status = "okay";
+	current-speed = <115200>;
+	clock-frequency = <1804800>;
+};
+
+&ite_uart1_wrapper {
+	status = "okay";
+	pinctrl-0 = <&uart1_rx_gpb0_default
+		     &uart1_tx_gpb1_default>;
+	pinctrl-names = "default";
+};
+
+&espi0 {
+	status = "okay";
+};
diff --git a/zephyr/cmake/bintools/gnu/target.cmake b/zephyr/cmake/bintools/gnu/target.cmake
new file mode 100644
index 0000000000..13e81ed4a0
--- /dev/null
+++ b/zephyr/cmake/bintools/gnu/target.cmake
@@ -0,0 +1,7 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Zephyr cmake system looks into ${TOOLCHAIN_ROOT}, but we just send
+# this out to the copy in ${ZEPHYR_BASE}.
+include("${ZEPHYR_BASE}/cmake/bintools/gnu/target.cmake")
diff --git a/zephyr/cmake/bintools/llvm/generic.cmake b/zephyr/cmake/bintools/llvm/generic.cmake
new file mode 100644
index 0000000000..f85236d39c
--- /dev/null
+++ b/zephyr/cmake/bintools/llvm/generic.cmake
@@ -0,0 +1,10 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+set(CMAKE_AR         "/usr/bin/llvm-ar")
+set(CMAKE_NM         "/usr/bin/llvm-nm")
+set(CMAKE_OBJCOPY    "/usr/bin/llvm-objcopy")
+set(CMAKE_OBJDUMP    "/usr/bin/llvm-objdump")
+set(CMAKE_RANLIB     "/usr/bin/llvm-ranlib")
+set(CMAKE_READELF    "/usr/bin/llvm-readelf")
diff --git a/zephyr/cmake/bintools/llvm/target.cmake b/zephyr/cmake/bintools/llvm/target.cmake
new file mode 100644
index 0000000000..ec18e2ca7b
--- /dev/null
+++ b/zephyr/cmake/bintools/llvm/target.cmake
@@ -0,0 +1,28 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Use generic bintools.
+include("${TOOLCHAIN_ROOT}/cmake/bintools/llvm/generic.cmake")
+
+if("${ARCH}" STREQUAL "arm")
+  set(CMAKE_AR         "${CROSS_COMPILE}ar")
+  set(CMAKE_NM         "${CROSS_COMPILE}nm")
+  set(CMAKE_OBJCOPY    "${CROSS_COMPILE}objcopy")
+  set(CMAKE_OBJDUMP    "${CROSS_COMPILE}objdump")
+  set(CMAKE_RANLIB     "${CROSS_COMPILE}ranlib")
+  set(CMAKE_READELF    "${CROSS_COMPILE}readelf")
+
+  # CMake is looking for bintools by adding a suffix to compiler binary
+  # e.g for AR it would be armv7m-cros-eabi-clang-ar, which doesn't exist.
+  # Set bintools locations manually
+  set(CMAKE_C_COMPILER_AR         "${CROSS_COMPILE}ar")
+  set(CMAKE_C_COMPILER_NM         "${CROSS_COMPILE}nm")
+  set(CMAKE_C_COMPILER_OBJCOPY    "${CROSS_COMPILE}objcopy")
+  set(CMAKE_C_COMPILER_OBJDUMP    "${CROSS_COMPILE}objdump")
+  set(CMAKE_C_COMPILER_RANLIB     "${CROSS_COMPILE}ranlib")
+  set(CMAKE_C_COMPILER_READELF    "${CROSS_COMPILE}readelf")
+endif()
+
+# Include the GNU bintools properties as a base.
+include("${ZEPHYR_BASE}/cmake/bintools/gnu/target_bintools.cmake")
diff --git a/zephyr/cmake/compiler/clang/compiler_flags.cmake b/zephyr/cmake/compiler/clang/compiler_flags.cmake
new file mode 100644
index 0000000000..7332934a9b
--- /dev/null
+++ b/zephyr/cmake/compiler/clang/compiler_flags.cmake
@@ -0,0 +1,27 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+include("${ZEPHYR_BASE}/cmake/compiler/clang/compiler_flags.cmake")
+
+# Disable -fno-freestanding.
+set_compiler_property(PROPERTY hosted)
+
+# When testing, look for stack smashing
+add_compile_option_ifdef(CONFIG_ZTEST -fstack-protector-all)
+
+if(DEFINED CONFIG_COMPILER_WARNINGS_AS_ERRORS)
+  check_set_compiler_property(APPEND PROPERTY warning_extended -Wunused-variable
+    -Werror=unused-variable -Werror=missing-braces
+    -Werror=sometimes-uninitialized -Werror=unused-function
+    -Werror=array-bounds)
+endif()
+
+# clang flags for coverage generation
+set_property(TARGET compiler PROPERTY coverage --coverage -fno-inline)
+
+# Compiler flags for disabling position independent code / executable
+set_compiler_property(PROPERTY no_position_independent
+                      -fno-PIC
+                      -fno-PIE
+)
diff --git a/zephyr/cmake/compiler/clang/generic.cmake b/zephyr/cmake/compiler/clang/generic.cmake
new file mode 100644
index 0000000000..087e4d0c47
--- /dev/null
+++ b/zephyr/cmake/compiler/clang/generic.cmake
@@ -0,0 +1,13 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if(EXISTS /etc/cros_chroot_version)
+  set(CMAKE_C_COMPILER "/usr/bin/x86_64-pc-linux-gnu-clang")
+  set(CMAKE_CXX_COMPILER "/usr/bin/x86_64-pc-linux-gnu-clang++")
+  set(CMAKE_GCOV "/usr/bin/llvm-cov gcov")
+else()
+  find_program(CMAKE_C_COMPILER clang)
+  find_program(CMAKE_CXX_COMPILER clang++)
+  find_program(CMAKE_GCOV gcov)
+endif()
diff --git a/zephyr/cmake/compiler/clang/target.cmake b/zephyr/cmake/compiler/clang/target.cmake
new file mode 100644
index 0000000000..1f0bf0a0e6
--- /dev/null
+++ b/zephyr/cmake/compiler/clang/target.cmake
@@ -0,0 +1,8 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+include("${ZEPHYR_BASE}/cmake/compiler/clang/target.cmake")
+
+set(CMAKE_C_COMPILER "${CROSS_COMPILE}clang")
+set(CMAKE_CXX_COMPILER "${CROSS_COMPILE}clang++")
diff --git a/zephyr/cmake/compiler/gcc/compiler_flags.cmake b/zephyr/cmake/compiler/gcc/compiler_flags.cmake
new file mode 100644
index 0000000000..befd1f34d4
--- /dev/null
+++ b/zephyr/cmake/compiler/gcc/compiler_flags.cmake
@@ -0,0 +1,10 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Zephyr cmake system looks into ${TOOLCHAIN_ROOT}, but we just send
+# this out to the copy in ${ZEPHYR_BASE}.
+include("${ZEPHYR_BASE}/cmake/compiler/gcc/compiler_flags.cmake")
+
+# gcc flags for coverage generation
+set_compiler_property(PROPERTY coverage -fprofile-arcs -ftest-coverage -fno-inline)
diff --git a/zephyr/cmake/compiler/gcc/generic.cmake b/zephyr/cmake/compiler/gcc/generic.cmake
new file mode 100644
index 0000000000..8f41f59bee
--- /dev/null
+++ b/zephyr/cmake/compiler/gcc/generic.cmake
@@ -0,0 +1,5 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+include("${ZEPHYR_BASE}/cmake/compiler/gcc/generic.cmake")
diff --git a/zephyr/cmake/compiler/gcc/target.cmake b/zephyr/cmake/compiler/gcc/target.cmake
new file mode 100644
index 0000000000..943ea167ca
--- /dev/null
+++ b/zephyr/cmake/compiler/gcc/target.cmake
@@ -0,0 +1,14 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Zephyr cmake system looks into ${TOOLCHAIN_ROOT}, but we just send
+# this out to the copy in ${ZEPHYR_BASE}.
+include("${ZEPHYR_BASE}/cmake/compiler/gcc/target.cmake")
+
+# no_libgcc support has been removed in upstream zephyr, but we still
+# depend on it.  This ugly hack emulates what it used to do by undoing
+# what some of target.cmake does.
+if(no_libgcc)
+  list(REMOVE_ITEM TOOLCHAIN_LIBS gcc)
+endif()
diff --git a/zephyr/cmake/linker/ld/clang/linker_flags.cmake b/zephyr/cmake/linker/ld/clang/linker_flags.cmake
new file mode 100644
index 0000000000..38f5428d13
--- /dev/null
+++ b/zephyr/cmake/linker/ld/clang/linker_flags.cmake
@@ -0,0 +1,7 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if (NOT CONFIG_COVERAGE_GCOV)
+  set_property(TARGET linker PROPERTY coverage --coverage)
+endif()
diff --git a/zephyr/cmake/linker/ld/gcc/linker_flags.cmake b/zephyr/cmake/linker/ld/gcc/linker_flags.cmake
new file mode 100644
index 0000000000..b5ec8b05ca
--- /dev/null
+++ b/zephyr/cmake/linker/ld/gcc/linker_flags.cmake
@@ -0,0 +1,11 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if (NOT CONFIG_COVERAGE_GCOV)
+  set_property(TARGET linker PROPERTY coverage -lgcov)
+endif()
+
+# GCC 11 by default emits DWARF version 5 which cannot be parsed by
+# pyelftools. Can be removed once pyelftools supports v5.
+add_link_options(-gdwarf-4)
diff --git a/zephyr/cmake/linker/ld/linker_flags.cmake b/zephyr/cmake/linker/ld/linker_flags.cmake
new file mode 100644
index 0000000000..d6045ba6ed
--- /dev/null
+++ b/zephyr/cmake/linker/ld/linker_flags.cmake
@@ -0,0 +1,11 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Zephyr cmake system looks into ${TOOLCHAIN_ROOT}, but we just send
+# this out to the copy in ${ZEPHYR_BASE}.
+include("${ZEPHYR_BASE}/cmake/linker/ld/linker_flags.cmake")
+
+# There can also be compiler specific linker options, so try to include
+# our version of that also.
+include("${TOOLCHAIN_ROOT}/cmake/linker/${LINKER}/${COMPILER}/linker_flags.cmake" OPTIONAL)
diff --git a/zephyr/cmake/linker/ld/target.cmake b/zephyr/cmake/linker/ld/target.cmake
new file mode 100644
index 0000000000..02dd95b236
--- /dev/null
+++ b/zephyr/cmake/linker/ld/target.cmake
@@ -0,0 +1,7 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Zephyr cmake system looks into ${TOOLCHAIN_ROOT}, but we just send
+# this out to the copy in ${ZEPHYR_BASE}.
+include("${ZEPHYR_BASE}/cmake/linker/ld/target.cmake")
diff --git a/zephyr/cmake/linker/lld/linker_flags.cmake b/zephyr/cmake/linker/lld/linker_flags.cmake
new file mode 100644
index 0000000000..6bf67490ed
--- /dev/null
+++ b/zephyr/cmake/linker/lld/linker_flags.cmake
@@ -0,0 +1,12 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Include definitions for bfd as a base.
+include("${ZEPHYR_BASE}/cmake/linker/ld/linker_flags.cmake")
+# ld/linker_flags.cmake includes ${LINKER}/${COMPILER}/linker_flags.cmake but
+# that doesn't exist for ldd, so import the path that actually exists.
+include("${ZEPHYR_BASE}/cmake/linker/ld/${COMPILER}/linker_flags.cmake" OPTIONAL)
+
+# Add the -nopie option to the linker flags to match the compilation options
+set_property(TARGET linker PROPERTY no_position_independent "-nopie")
diff --git a/zephyr/cmake/linker/lld/target.cmake b/zephyr/cmake/linker/lld/target.cmake
new file mode 100644
index 0000000000..c5084bb2a1
--- /dev/null
+++ b/zephyr/cmake/linker/lld/target.cmake
@@ -0,0 +1,5 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+include("${ZEPHYR_BASE}/cmake/linker/lld/target.cmake")
diff --git a/zephyr/cmake/toolchain/coreboot-sdk/generic.cmake b/zephyr/cmake/toolchain/coreboot-sdk/generic.cmake
new file mode 100644
index 0000000000..d20f19528d
--- /dev/null
+++ b/zephyr/cmake/toolchain/coreboot-sdk/generic.cmake
@@ -0,0 +1,9 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# generic.cmake is used for host-side compilation and preprocessing
+# (e.g., for device-tree).  Thus, we should use LLVM for this
+# actually, as that's what's currently supported compiler-wise in the
+# chroot right now.
+include("${TOOLCHAIN_ROOT}/cmake/toolchain/llvm/generic.cmake")
diff --git a/zephyr/cmake/toolchain/coreboot-sdk/target.cmake b/zephyr/cmake/toolchain/coreboot-sdk/target.cmake
new file mode 100644
index 0000000000..15858e09d9
--- /dev/null
+++ b/zephyr/cmake/toolchain/coreboot-sdk/target.cmake
@@ -0,0 +1,43 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Coreboot SDK uses GCC
+set(COMPILER gcc)
+set(LINKER ld)
+set(BINTOOLS gnu)
+
+# Mapping of Zephyr architecture -> coreboot-sdk toolchain
+set(CROSS_COMPILE_TARGET_arm    arm-eabi)
+set(CROSS_COMPILE_TARGET_riscv  riscv64-elf)
+set(CROSS_COMPILE_TARGET_x86    i386-elf)
+
+set(CROSS_COMPILE_TARGET        ${CROSS_COMPILE_TARGET_${ARCH}})
+
+if("${ARCH}" STREQUAL "arm" AND CONFIG_ARM64)
+  set(CROSS_COMPILE_TARGET      aarch64-elf)
+elseif("${ARCH}" STREQUAL "x86" AND CONFIG_X86_64)
+  set(CROSS_COMPILE_TARGET      x86_64-elf)
+endif()
+
+if(NOT DEFINED COREBOOT_SDK_ROOT)
+  set(COREBOOT_SDK_ROOT "$ENV{COREBOOT_SDK_ROOT}")
+endif()
+
+set(CC gcc)
+set(CROSS_COMPILE "${COREBOOT_SDK_ROOT}/bin/${CROSS_COMPILE_TARGET}-")
+
+set(CMAKE_AR         "${CROSS_COMPILE}ar")
+set(CMAKE_NM         "${CROSS_COMPILE}nm")
+set(CMAKE_OBJCOPY    "${CROSS_COMPILE}objcopy")
+set(CMAKE_OBJDUMP    "${CROSS_COMPILE}objdump")
+set(CMAKE_RANLIB     "${CROSS_COMPILE}ranlib")
+set(CMAKE_READELF    "${CROSS_COMPILE}readelf")
+
+# On ARM, we don't use libgcc: It's built against a fixed target (e.g.
+# used instruction set, ABI, ISA extensions) and doesn't adapt when
+# compiler flags change any of these assumptions. Use our own mini-libgcc
+# instead.
+if("${ARCH}" STREQUAL "arm")
+  set(no_libgcc True)
+endif()
diff --git a/zephyr/cmake/toolchain/host/generic.cmake b/zephyr/cmake/toolchain/host/generic.cmake
new file mode 100644
index 0000000000..4cc0fbd352
--- /dev/null
+++ b/zephyr/cmake/toolchain/host/generic.cmake
@@ -0,0 +1,18 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+set(CROSS_COMPILE_TARGET_posix        x86_64-pc-linux-gnu)
+set(CROSS_COMPILE_TARGET_unit_testing x86_64-pc-linux-gnu)
+set(CROSS_COMPILE_TARGET          ${CROSS_COMPILE_TARGET_${ARCH}})
+
+set(CC gcc)
+set(CROSS_COMPILE "/usr/bin/${CROSS_COMPILE_TARGET}-")
+
+set(COMPILER gcc)
+set(LINKER ld)
+set(BINTOOLS gnu)
+
+set(TOOLCHAIN_HAS_NEWLIB OFF CACHE BOOL "True if toolchain supports newlib")
+
+message(STATUS "Found toolchain: host ${ARCH} (gcc/ld)")
diff --git a/zephyr/cmake/toolchain/host/target.cmake b/zephyr/cmake/toolchain/host/target.cmake
new file mode 100644
index 0000000000..9d540f97ff
--- /dev/null
+++ b/zephyr/cmake/toolchain/host/target.cmake
@@ -0,0 +1,5 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+include("${ZEPHYR_BASE}/cmake/toolchain/host/target.cmake")
diff --git a/zephyr/cmake/toolchain/llvm/generic.cmake b/zephyr/cmake/toolchain/llvm/generic.cmake
new file mode 100644
index 0000000000..933162d9bb
--- /dev/null
+++ b/zephyr/cmake/toolchain/llvm/generic.cmake
@@ -0,0 +1,7 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+set(COMPILER clang)
+set(LINKER   lld)
+set(BINTOOLS llvm)
diff --git a/zephyr/cmake/toolchain/llvm/target.cmake b/zephyr/cmake/toolchain/llvm/target.cmake
new file mode 100644
index 0000000000..a187f200cc
--- /dev/null
+++ b/zephyr/cmake/toolchain/llvm/target.cmake
@@ -0,0 +1,33 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+set(COMPILER clang)
+set(LINKER lld)
+set(BINTOOLS llvm)
+
+# Mapping of Zephyr architecture -> toolchain triple
+set(CROSS_COMPILE_TARGET_posix        x86_64-pc-linux-gnu)
+set(CROSS_COMPILE_TARGET_unit_testing x86_64-pc-linux-gnu)
+
+set(CROSS_COMPILE_TARGET          ${CROSS_COMPILE_TARGET_${ARCH}})
+
+if("${ARCH}" STREQUAL "arm")
+  if(DEFINED CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
+    # ARMV7_M_ARMV8_M_MAINLINE means that ARMv7-M or backward compatible ARMv8-M
+    # processor is used.
+    set(CROSS_COMPILE_TARGET armv7m-cros-eabi)
+  elseif(DEFINED CONFIG_ARMV6_M_ARMV8_M_BASELINE)
+    # ARMV6_M_ARMV8_M_BASELINE means that ARMv6-M or ARMv8-M supporting the
+    # Baseline implementation processor is used.
+    set(CROSS_COMPILE_TARGET arm-none-eabi)
+  endif()
+endif()
+
+set(CC clang)
+
+# TODO(b/286589977): Remove if() when hermetic host toolchain is added to fwsdk.
+# Use non-hermetic host toolchain when running outside chroot.
+if(EXISTS /etc/cros_chroot_version)
+  set(CROSS_COMPILE "/usr/bin/${CROSS_COMPILE_TARGET}-")
+endif()
diff --git a/zephyr/drivers/CMakeLists.txt b/zephyr/drivers/CMakeLists.txt
new file mode 100644
index 0000000000..38d8b3f7bb
--- /dev/null
+++ b/zephyr/drivers/CMakeLists.txt
@@ -0,0 +1,11 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+add_subdirectory(cros_displight)
+add_subdirectory(cros_flash)
+add_subdirectory(cros_kb_raw)
+add_subdirectory(cros_kblight)
+add_subdirectory(cros_rtc)
+add_subdirectory(cros_shi)
+add_subdirectory(cros_system)
diff --git a/zephyr/drivers/Kconfig b/zephyr/drivers/Kconfig
new file mode 100644
index 0000000000..0848d83939
--- /dev/null
+++ b/zephyr/drivers/Kconfig
@@ -0,0 +1,9 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+rsource "cros_flash/Kconfig"
+rsource "cros_kb_raw/Kconfig"
+rsource "cros_rtc/Kconfig"
+rsource "cros_system/Kconfig"
+rsource "cros_shi/Kconfig"
diff --git a/zephyr/drivers/cros_displight/CMakeLists.txt b/zephyr/drivers/cros_displight/CMakeLists.txt
new file mode 100644
index 0000000000..5e43d5fedd
--- /dev/null
+++ b/zephyr/drivers/cros_displight/CMakeLists.txt
@@ -0,0 +1,5 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_PWM_DISPLIGHT cros_displight.c)
diff --git a/zephyr/drivers/cros_displight/cros_displight.c b/zephyr/drivers/cros_displight/cros_displight.c
new file mode 100644
index 0000000000..850b0d7c90
--- /dev/null
+++ b/zephyr/drivers/cros_displight/cros_displight.c
@@ -0,0 +1,58 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define DT_DRV_COMPAT cros_ec_displight
+
+#include "common.h"
+#include "util.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/pwm.h>
+#include <zephyr/logging/log.h>
+
+#include <drivers/cros_displight.h>
+
+LOG_MODULE_REGISTER(displight, LOG_LEVEL_ERR);
+
+BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
+	     "Exactly one instance of cros-ec,displight should be defined.");
+
+static const struct pwm_dt_spec displight_pwm = PWM_DT_SPEC_INST_GET(0);
+
+static int displight_percent;
+
+static void displight_set_duty(int percent)
+{
+	const struct device *pwm_dev = displight_pwm.dev;
+	uint32_t pulse_ns;
+	int rv;
+
+	if (!device_is_ready(pwm_dev)) {
+		LOG_ERR("PWM device %s not ready", pwm_dev->name);
+		return;
+	}
+
+	pulse_ns = DIV_ROUND_NEAREST(displight_pwm.period * percent, 100);
+
+	LOG_DBG("displight PWM %s set percent (%d), pulse %d", pwm_dev->name,
+		percent, pulse_ns);
+
+	rv = pwm_set_pulse_dt(&displight_pwm, pulse_ns);
+	if (rv) {
+		LOG_ERR("pwm_set_pulse_dt failed %s (%d)", pwm_dev->name, rv);
+	}
+}
+
+int displight_set(int percent)
+{
+	displight_percent = percent;
+	displight_set_duty(percent);
+	return EC_SUCCESS;
+}
+
+int displight_get(void)
+{
+	return displight_percent;
+}
diff --git a/zephyr/drivers/cros_flash/CMakeLists.txt b/zephyr/drivers/cros_flash/CMakeLists.txt
new file mode 100644
index 0000000000..2a8d110bff
--- /dev/null
+++ b/zephyr/drivers/cros_flash/CMakeLists.txt
@@ -0,0 +1,14 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+zephyr_library_sources_ifdef(CONFIG_CROS_FLASH_IT8XXX2	cros_flash_it8xxx2.c)
+zephyr_library_sources_ifdef(CONFIG_CROS_FLASH_NPCX	cros_flash_npcx.c)
+zephyr_library_sources_ifdef(CONFIG_CROS_FLASH_XEC	cros_flash_xec.c)
+zephyr_library_sources_ifdef(CONFIG_CROS_FLASH	        cros_flash.c)
+zephyr_library_sources_ifdef(CONFIG_CROS_FLASH_BACKEND_STM32
+	                                                cros_flash_stm32_backend.c)
+
+zephyr_library_link_libraries_ifdef(CONFIG_PLATFORM_EC_SPI_FLASH_REGS
+    spi_flash_reg
+)
diff --git a/zephyr/drivers/cros_flash/Kconfig b/zephyr/drivers/cros_flash/Kconfig
new file mode 100644
index 0000000000..f8b30d9b6c
--- /dev/null
+++ b/zephyr/drivers/cros_flash/Kconfig
@@ -0,0 +1,145 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+menuconfig CROS_FLASH_NPCX
+	bool "Nuvoton NPCX flash driver for the Zephyr shim"
+	default y
+	depends on DT_HAS_NUVOTON_NPCX_CROS_FLASH_ENABLED
+	select PLATFORM_EC_FLASH_CROS
+	select PLATFORM_EC_SPI_FLASH_REGS
+	help
+	  This option enables a flash unit interface (FIU) driver for the NPCX
+	  chip. This is used instead of the flash memory interface so we can
+	  continue to use most of the existing flash memory processing code in
+	  ECOS.
+
+if CROS_FLASH_NPCX
+
+config CROS_FLASH_NPCX_INIT_PRIORITY
+	int "Nuvoton NPCX flash driver priority for the Zephyr shim"
+	default 85
+	help
+	  This sets the priority of the NPCX flash driver for zephyr shim.
+	  This driver depends on the SPI controller and SPI NOR flash drivers.
+	  Its priority must be lower than CONFIG_SPI_INIT_PRIORITY and
+	  CONFIG_SPI_NOR_INIT_PRIORITY.
+
+endif # CROS_FLASH_NPCX
+
+config CROS_FLASH_IT8XXX2
+	bool "ITE IT81202 flash driver for the Zephyr shim"
+	depends on SOC_FAMILY_RISCV_ITE
+	default y
+	select PLATFORM_EC_FLASH_CROS
+	help
+	  This option enables the flash driver for the it8xxx2 chip. We can
+	  access the flash by read, write and erase. The it8xxx2 flash size
+	  is 1M byte.
+
+config CROS_FLASH_XEC
+	bool "Microchip XEC flash driver for the Zephyr shim"
+	default y
+	depends on DT_HAS_MICROCHIP_XEC_CROS_FLASH_ENABLED
+	select PLATFORM_EC_FLASH_CROS
+	select PLATFORM_EC_SPI_FLASH_REGS
+	help
+	  This option enables the flash driver for the MEC172x chips. Flash
+	  access is via the QSPI driver to one of three ports: internal 512KB
+	  SPI flash in the MEC1727 or external shared or private ports on
+	  MEC1723, etc.
+
+if CROS_FLASH_XEC
+
+config CROS_FLASH_XEC_INIT_PRIORITY
+	int "Microchip XEC flash driver priority for the Zephyr shim"
+	default 85
+	help
+	  This sets the priority of the MCHP flash driver for zephyr shim.
+	  This driver depends on the SPI controller and SPI NOR flash drivers.
+	  Its priority must be lower than CONFIG_SPI_INIT_PRIORITY and
+	  CONFIG_SPI_NOR_INIT_PRIORITY.
+
+endif # CROS_FLASH_XEC
+
+config CROS_FLASH
+	bool "Generic cros-flash driver for the Zephyr shim"
+	depends on DT_HAS_CROS_EC_CROS_FLASH_ENABLED
+	default y
+	select PLATFORM_EC_FLASH_CROS
+	help
+	  This option enables the cros-flash driver used by EC code.
+	  This driver actually acts as a translation layer between Zephyr flash
+	  driver and EC flash protection flags (ro_now, ro_at_boot, etc.). The
+	  driver uses a backend to perform flash specific operations, e.g.
+	  change protection settings.
+
+if CROS_FLASH
+
+config CROS_FLASH_HAS_READOUT_PROTECTION
+	bool
+	help
+	  This option is enabled if readout protection is supported.
+
+choice CROS_FLASH_BACKEND
+	prompt "Backend for cros-flash driver"
+	default CROS_FLASH_BACKEND_STM32 if SOC_FAMILY_STM32
+	help
+	  Backend for cros-flash driver provides functions responsible for
+	  changing write protection and readout protection state, blocking
+	  flash protection changes or basic flash operations.
+
+	  Backend performs these operations using extended operations exposed by
+	  flash API or can interact with the hardware directly.
+
+config CROS_FLASH_BACKEND_STM32
+	bool "STM32 backend for cros-flash driver"
+	depends on SOC_FLASH_STM32
+	select CROS_FLASH_HAS_READOUT_PROTECTION if FLASH_STM32_READOUT_PROTECTION
+	select FLASH_EX_OP_ENABLED
+	select FLASH_STM32_WRITE_PROTECT
+
+config CROS_FLASH_BACKEND_FAKE
+	bool "Fake backend for cros-flash driver"
+	select CROS_FLASH_HAS_READOUT_PROTECTION
+	help
+	  Fake backend is just set functions provided by test. It's used to test
+	  the driver only.
+endchoice
+
+config CROS_FLASH_READOUT_PROTECTION
+	bool "Enable flash readout protection"
+	depends on CROS_FLASH_HAS_READOUT_PROTECTION
+	default n
+	help
+	  This option enables support for readout protection in cros-flash driver.
+
+config CROS_FLASH_CUSTOM_JUMP_STRUCTURE
+	bool "Use custom functions to encode/decode flash jump data"
+	help
+	  If enabled, the driver will call decode_wp_from_sysjump() and
+	  prepare_wp_jump() to decode/encode flash jump data.
+
+config CROS_FLASH_INIT_PRIORITY
+	int "Generic flash driver priority for the Zephyr shim"
+	default 55
+	help
+	  This sets the priority of the cros-flash driver for Zephyr shim.
+	  This driver depends on the flash-controller driver in Zephyr.
+	  Its priority must be lower than CONFIG_FLASH_INIT_PRIORITY.
+
+# Backend-specific configs
+
+config CROS_FLASH_STM32_EC_JUMP_STRUCTURE
+	bool "Enable backward compatibility with EC flash jump structure"
+	depends on CROS_FLASH_BACKEND_STM32 && SOC_SERIES_STM32F4X
+	default n
+	select CROS_FLASH_CUSTOM_JUMP_STRUCTURE
+	help
+	  This option enables backward compatibility with EC flash protection
+	  data. During sysjump, flash protection information is saved in jump
+	  tags. The part we've jumped to will read the data, so it will report
+	  protection correctly. This includes the code for coverting the data
+	  between old and new formats.
+
+endif # CROS_FLASH
diff --git a/zephyr/drivers/cros_flash/cros_flash.c b/zephyr/drivers/cros_flash/cros_flash.c
new file mode 100644
index 0000000000..d3681aa2ac
--- /dev/null
+++ b/zephyr/drivers/cros_flash/cros_flash.c
@@ -0,0 +1,597 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define DT_DRV_COMPAT cros_ec_cros_flash
+
+#include "assert.h"
+#include "cros_flash.h"
+#include "flash.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "system.h"
+#include "watchdog.h"
+#include "write_protect.h"
+
+#include <zephyr/drivers/flash.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+
+#include <drivers/cros_flash.h>
+
+LOG_MODULE_REGISTER(cros_flash, LOG_LEVEL_INF);
+
+/* Device data */
+struct cros_flash_data {
+	struct cros_flash_protection protection;
+};
+
+/* Driver convenience defines */
+#define DRV_DATA(dev) ((struct cros_flash_data *)(dev)->data)
+
+#define FLASH_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))
+
+static const struct device *const flash_controller =
+	DEVICE_DT_GET(DT_CHOSEN(zephyr_flash_controller));
+
+/* cros ec flash api functions */
+static int cros_flash_write(const struct device *dev, int offset, int size,
+			    const char *src_data)
+{
+	struct cros_flash_data *const data = DRV_DATA(dev);
+
+	if (data->protection.control_access_blocked) {
+		return -EACCES;
+	}
+
+	/*
+	 * If AP sends write flash command continuously, EC might not have
+	 * chance to go back to hook task to touch watchdog. Reload watchdog
+	 * on each flash write to prevent the reset.
+	 */
+	if (IS_ENABLED(CONFIG_PLATFORM_EC_WATCHDOG))
+		watchdog_reload();
+
+	return flash_write(flash_controller, offset, src_data, size);
+}
+
+static int cros_flash_erase(const struct device *dev, int offset, int size)
+{
+	struct cros_flash_data *const data = DRV_DATA(dev);
+
+	if (data->protection.control_access_blocked) {
+		return -EACCES;
+	}
+
+	if (IS_ENABLED(CONFIG_PLATFORM_EC_WATCHDOG))
+		watchdog_reload();
+
+	return flash_erase(flash_controller, offset, size);
+}
+
+static int cros_flash_sector_mask_from_offset(const struct device *dev,
+					      off_t offset, size_t size,
+					      uint32_t *sector_mask)
+{
+	struct flash_pages_info start_page, end_page;
+
+	if (flash_get_page_info_by_offs(dev, offset, &start_page) ||
+	    flash_get_page_info_by_offs(dev, offset + size - 1, &end_page)) {
+		LOG_ERR("Flash range invalid. offset: 0x%lx, len: 0x%zx",
+			(long)offset, size);
+		return -EINVAL;
+	}
+
+	/* Check if sectors don't cover wider range than requested. */
+	if (start_page.start_offset != offset ||
+	    end_page.start_offset + end_page.size != offset + size) {
+		LOG_ERR("Range covered by sectors doesn't match requested "
+			"range. Requested (0x%lx, 0x%lx), "
+			"covered (0x%lx, 0x%lx).",
+			offset, offset + size - 1, start_page.start_offset,
+			end_page.start_offset + end_page.size - 1);
+		return -EINVAL;
+	}
+
+	__ASSERT(start_page.index < NUM_BITS(uint32_t) &&
+			 end_page.index < NUM_BITS(uint32_t),
+		 "Page index doesn't fit in uint32_t");
+	*sector_mask = GENMASK(end_page.index, start_page.index);
+
+	LOG_DBG("Sector mask for offset 0x%lx, size 0x%zx is 0x%x", offset,
+		size, *sector_mask);
+
+	return 0;
+}
+
+static int cros_flash_flags_to_sectors(const struct device *dev,
+				       uint32_t prot_flags,
+				       uint32_t *enable_mask,
+				       uint32_t *disable_mask)
+{
+	int err, first_err = 0;
+	uint32_t range_sectors;
+
+	*enable_mask = 0;
+	*disable_mask = 0;
+
+	if (prot_flags & EC_FLASH_PROTECT_ALL_AT_BOOT) {
+		return cros_flash_sector_mask_from_offset(dev, 0, FLASH_SIZE,
+							  enable_mask);
+	}
+
+	err = cros_flash_sector_mask_from_offset(dev, CONFIG_WP_STORAGE_OFF,
+						 CONFIG_WP_STORAGE_SIZE,
+						 &range_sectors);
+	if (err == 0) {
+		if (prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT)
+			*enable_mask |= range_sectors;
+		else
+			*disable_mask |= range_sectors;
+	} else if (first_err == 0) {
+		first_err = err;
+	}
+#ifdef CONFIG_ROLLBACK
+	err = cros_flash_sector_mask_from_offset(
+		dev, CONFIG_ROLLBACK_OFF, CONFIG_ROLLBACK_SIZE, &range_sectors);
+	if (err == 0) {
+		if (prot_flags & EC_FLASH_PROTECT_ROLLBACK_AT_BOOT)
+			*enable_mask |= range_sectors;
+		else
+			*disable_mask |= range_sectors;
+	} else if (first_err == 0) {
+		first_err = err;
+	}
+#endif
+#ifdef CONFIG_FLASH_PROTECT_RW
+	err = cros_flash_sector_mask_from_offset(
+		dev, CONFIG_EC_WRITABLE_STORAGE_OFF,
+		CONFIG_EC_WRITABLE_STORAGE_SIZE, &range_sectors);
+	if (err == 0) {
+		if (prot_flags & EC_FLASH_PROTECT_RW_AT_BOOT)
+			*enable_mask |= range_sectors;
+		else
+			*disable_mask |= range_sectors;
+	} else if (first_err == 0) {
+		first_err = err;
+	}
+#endif
+
+	if (first_err) {
+		LOG_WRN("Failed converting protection flags 0x%x, "
+			"to sector mask: %d",
+			prot_flags, first_err);
+	}
+	return first_err;
+}
+
+static int cros_flash_protect_at_boot(const struct device *dev,
+				      uint32_t new_flags)
+{
+	struct cros_flash_data *const data = DRV_DATA(dev);
+	int err, first_err = 0;
+	uint32_t enable_mask = 0, disable_mask = 0;
+
+	if (data->protection.protection_changes_blocked) {
+		return -EACCES;
+	}
+
+	if (write_protect_is_asserted()) {
+		first_err = cros_flash_flags_to_sectors(flash_controller,
+							new_flags, &enable_mask,
+							&disable_mask);
+		/*
+		 * We still want to change write protection settings, even when
+		 * cros_flash_flags_to_sectors() returned error. Masks can
+		 * contain sectors that should be enabled or disabled (even when
+		 * error was returned).
+		 */
+
+		/* Commit write protect changes */
+		LOG_INF("Commit WP changes: disabling: 0x%x, enabling: 0x%x",
+			disable_mask, enable_mask);
+		err = flash_change_wp(flash_controller, disable_mask,
+				      enable_mask);
+		if (err) {
+			LOG_ERR("Can't modify flash write protection, "
+				"error: %d",
+				err);
+			if (first_err == 0)
+				first_err = err;
+		}
+	}
+
+#if defined(CONFIG_CROS_FLASH_READOUT_PROTECTION)
+	/*
+	 * Enable readout protection if RO_AT_BOOT is set.
+	 *
+	 * This is intentionally a one-way latch. Once we have enabled RDP
+	 * Level 1, we will only allow going back to Level 0 using the
+	 * bootloader (e.g., "stm32mon -U") since transitioning from Level 1 to
+	 * Level 0 triggers a mass erase.
+	 */
+	if (new_flags & EC_FLASH_PROTECT_RO_AT_BOOT) {
+		err = flash_change_rdp(flash_controller, true, false);
+		if (err) {
+			LOG_ERR("Can't enable RDP, error: %d", err);
+			if (first_err == 0) {
+				first_err = err;
+			}
+		}
+	}
+#endif
+
+	return first_err;
+}
+
+/**
+ * Check if write protect register state is consistent with *_AT_BOOT in
+ * prot_flags.
+ *
+ * @retval zero if consistent.
+ * @retval positive value if inconsistent.
+ * @retval negative value on error.
+ */
+static int wp_settings_are_incorrect(const struct device *dev,
+				     uint32_t prot_flags)
+{
+	uint32_t expect_enabled = 0, expect_disabled = 0;
+	uint32_t protected_mask;
+	int err, first_err = 0;
+	bool consistent;
+
+	first_err = cros_flash_flags_to_sectors(flash_controller, prot_flags,
+						&expect_enabled,
+						&expect_disabled);
+	/*
+	 * Continue even when error occurred. Masks can contain sectors that
+	 * should be enabled or disabled (even when error was returned).
+	 */
+
+	err = flash_get_wp(flash_controller, &protected_mask);
+	if (err) {
+		LOG_ERR("Can't get flash write protect status, error: %d", err);
+		if (first_err == 0) {
+			first_err = err;
+		}
+	}
+	if (first_err) {
+		return first_err;
+	}
+
+	/*
+	 * Write protect settings are consistent when supported regions are
+	 * entirely enabled or disabled. We don't care about sectors which are
+	 * not covered by any region.
+	 */
+	consistent = (protected_mask & expect_enabled) == expect_enabled &&
+		     (protected_mask & expect_disabled) == 0;
+
+	return consistent ? 0 : 1;
+}
+
+static bool wp_all_disabled(const struct device *dev)
+{
+	uint32_t protected_mask;
+	int err;
+
+	err = flash_get_wp(flash_controller, &protected_mask);
+	if (err) {
+		LOG_ERR("Can't get flash write protect status, error: %d", err);
+		return false;
+	}
+
+	return !protected_mask;
+}
+
+static int cros_flash_disable_wp_all(const struct device *dev)
+{
+	struct cros_flash_data *const data = DRV_DATA(dev);
+	uint32_t disable_mask;
+	int err;
+
+	if (data->protection.protection_changes_blocked) {
+		return -EACCES;
+	}
+
+	err = cros_flash_sector_mask_from_offset(flash_controller, 0,
+						 FLASH_SIZE, &disable_mask);
+	if (err) {
+		return err;
+	}
+
+	return flash_change_wp(flash_controller, disable_mask, 0);
+}
+
+static int cros_flash_get_protect(const struct device *dev, int bank)
+{
+	struct cros_flash_data *const data = DRV_DATA(dev);
+	uint32_t protected_mask;
+	int err;
+
+	if (data->protection.control_access_blocked) {
+		return 1;
+	}
+
+	err = flash_get_wp(flash_controller, &protected_mask);
+	if (err) {
+		LOG_ERR("Can't get flash write protect status, error: %d", err);
+		return 0;
+	}
+
+	return (protected_mask & BIT(bank)) ? 1 : 0;
+}
+
+#if defined(CONFIG_CROS_FLASH_READOUT_PROTECTION)
+/**
+ * Check if readout protection is enabled.
+ *
+ * @retval positive value if RDP is enabled.
+ * @retval zero if RDP is disabled.
+ * @retval negative value on error.
+ */
+static int rdp_is_enabled(const struct device *dev)
+{
+	bool enabled;
+	int err = flash_get_rdp(flash_controller, &enabled, NULL);
+
+	if (err)
+		return err;
+
+	return enabled ? 1 : 0;
+}
+#endif
+
+static uint32_t cros_flash_get_protect_flags(const struct device *dev)
+{
+	struct cros_flash_data *const data = DRV_DATA(dev);
+	uint32_t flags = 0;
+
+	/* Read all-protected state from our shadow copy */
+	if (data->protection.control_access_blocked)
+		flags |= EC_FLASH_PROTECT_ALL_NOW;
+
+#if defined(CONFIG_CROS_FLASH_READOUT_PROTECTION)
+	/* Readout protection as a PSTATE */
+	int rdp = rdp_is_enabled(dev);
+
+	if (rdp < 0)
+		flags |= EC_FLASH_PROTECT_ERROR_UNKNOWN;
+	else if (rdp == 1)
+		flags |= EC_FLASH_PROTECT_RO_AT_BOOT;
+#endif
+
+	return flags;
+}
+
+static int disable_option_bytes(const struct device *dev)
+{
+	struct cros_flash_data *const data = DRV_DATA(dev);
+	int ret;
+
+	LOG_INF("Block protection changes");
+
+	ret = flash_block_protection_changes(flash_controller);
+	if (ret)
+		return ret;
+
+	data->protection.protection_changes_blocked = true;
+
+	return EC_SUCCESS;
+}
+
+static int disable_control_register(const struct device *dev)
+{
+	struct cros_flash_data *const data = DRV_DATA(dev);
+	int ret;
+
+	LOG_INF("Block flash control access");
+
+	ret = flash_block_control_access(flash_controller);
+	if (ret)
+		return ret;
+
+	data->protection.control_access_blocked = true;
+
+	return EC_SUCCESS;
+}
+
+static int cros_flash_protect_now(const struct device *dev, int all)
+{
+	int err;
+
+	err = disable_option_bytes(dev);
+
+	if (all) {
+		int protect_all_err;
+
+		protect_all_err = disable_control_register(dev);
+		if (protect_all_err && err == EC_SUCCESS)
+			err = protect_all_err;
+	}
+
+	return err;
+}
+
+#define CROS_FLASH_PROT_VERSION 1
+
+static int cros_flash_restore_state(const struct device *dev,
+				    uint32_t prot_flags)
+{
+	struct cros_flash_data *const data = DRV_DATA(dev);
+	int version, size;
+	const void *prev;
+
+	prev = system_get_jump_tag(FLASH_SYSJUMP_TAG, &version, &size);
+	if (!prev)
+		return -ENODATA;
+
+#ifdef CONFIG_CROS_FLASH_CUSTOM_JUMP_STRUCTURE
+	return decode_wp_from_sysjump(&data->protection, prot_flags, prev, size,
+				      version);
+#else
+	if (version != CROS_FLASH_PROT_VERSION ||
+	    size != sizeof(struct cros_flash_protection)) {
+		return -ENOENT;
+	}
+
+	const struct cros_flash_protection *prev_prot = prev;
+
+	data->protection.control_access_blocked =
+		prev_prot->control_access_blocked;
+	data->protection.protection_changes_blocked =
+		prev_prot->protection_changes_blocked;
+
+	return 0;
+#endif /* CONFIG_CROS_FLASH_CUSTOM_JUMP_STRUCTURE */
+}
+
+static void cros_flash_preserve_state(void)
+{
+	struct cros_flash_data *const data =
+		DRV_DATA(DEVICE_DT_GET(DT_CHOSEN(cros_ec_flash_controller)));
+
+#ifdef CONFIG_CROS_FLASH_CUSTOM_JUMP_STRUCTURE
+	prepare_wp_jump(&data->protection);
+#else
+	system_add_jump_tag(FLASH_SYSJUMP_TAG, CROS_FLASH_PROT_VERSION,
+			    sizeof(struct cros_flash_protection),
+			    &data->protection);
+#endif /* CONFIG_CROS_FLASH_CUSTOM_JUMP_STRUCTURE */
+}
+DECLARE_HOOK(HOOK_SYSJUMP, cros_flash_preserve_state, HOOK_PRIO_DEFAULT);
+
+static int cros_flash_driver_init(const struct device *dev)
+{
+	struct cros_flash_data *const data = DRV_DATA(dev);
+	uint32_t reset_flags = system_get_reset_flags();
+	uint32_t prot_flags = crec_flash_get_protect();
+	int need_reset = 0;
+	int err;
+
+	data->protection.control_access_blocked = false;
+	data->protection.protection_changes_blocked = false;
+
+	/*
+	 * If we have already jumped between images, an earlier image could
+	 * have applied write protection. Restore protection information and
+	 * exit.
+	 */
+	if (reset_flags & EC_RESET_FLAG_SYSJUMP) {
+		err = cros_flash_restore_state(dev, prot_flags);
+		if (err)
+			LOG_ERR("Failed to restore flash protection state, "
+				"error: %d",
+				err);
+		/*
+		 * Exit even when we were not able to restore protection state
+		 * correctly.
+		 */
+		return err;
+	}
+
+	if (prot_flags & EC_FLASH_PROTECT_GPIO_ASSERTED) {
+		if (
+#if defined(CONFIG_CROS_FLASH_READOUT_PROTECTION)
+			((prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT) &&
+			 rdp_is_enabled(dev) <= 0) ||
+#endif
+			wp_settings_are_incorrect(dev, prot_flags) != 0) {
+			/*
+			 * Fix incorrect WP settings and RDP settings if
+			 * RO_AT_BOOT is set.
+			 *
+			 * RO_AT_BOOT is set but the RO_NOW is not.
+			 * It means that we have RO protection enabled somewhere
+			 * (PSTATE, hardcoded, RDP) but it's not actually
+			 * enabled now.
+			 *
+			 * wp_settings_are_incorrect() checks whether write
+			 * protection on all supported regions matches AT_BOOT
+			 * flag. It doesn't care about sectors not covered by
+			 * any region. We can't check INCONSISTENT flag here
+			 * because it's also reported if:
+			 * - Write protection is enabled on a sector that is not
+			 *   covered by any region.
+			 * - Other regions are protected but RO is not,
+			 *   regardless of RO_AT_BOOT flag.
+			 * In above cases we will just leave the write
+			 * protection inconsistent.
+			 *
+			 * All of these problems can be fixed by requesting
+			 * *_AT_BOOT flags again. We can safely call function
+			 * from this driver, because we are not setting any new
+			 * flags. After enabling, we request a reset, so we can
+			 * check it once again.
+			 */
+			cros_flash_protect_at_boot(dev, prot_flags);
+			need_reset = 1;
+		} else if ((prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT) &&
+			   (prot_flags & EC_FLASH_PROTECT_RO_NOW)) {
+			/*
+			 * Here RO is fully protected and write protect settings
+			 * are consistent.
+			 *
+			 * Disable option bytes until next boot. The intention
+			 * here is to prevent from disabling sector write
+			 * protection. Please note that this has also following
+			 * side effects:
+			 * - It's not possible to enable write protection.
+			 * - It's not possible to enable RDP protection.
+			 */
+			disable_option_bytes(dev);
+		}
+	} else {
+		if (!wp_all_disabled(dev)) {
+			/*
+			 * Write protect pin unasserted but some section is
+			 * protected. Drop it and reboot.
+			 *
+			 * Please note that some additional protection
+			 * (e.g. RDP) will be still enabled.
+			 */
+			if (cros_flash_disable_wp_all(dev) == 0)
+				need_reset = 1;
+		}
+	}
+
+	if (need_reset)
+		system_reset(SYSTEM_RESET_HARD | SYSTEM_RESET_PRESERVE_FLAGS);
+
+	return EC_SUCCESS;
+}
+
+/* CrOS EC flash driver registration. */
+static const struct cros_flash_driver_api cros_flash_driver_api = {
+	.init = cros_flash_driver_init,
+	.physical_write = cros_flash_write,
+	.physical_erase = cros_flash_erase,
+	.physical_get_protect = cros_flash_get_protect,
+	.physical_get_protect_flags = cros_flash_get_protect_flags,
+	.physical_protect_at_boot = cros_flash_protect_at_boot,
+	.physical_protect_now = cros_flash_protect_now,
+};
+
+static int flash_init(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	if (!device_is_ready(flash_controller)) {
+		LOG_ERR("Selected flash device %s is not ready",
+			flash_controller->name);
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+static struct cros_flash_data cros_flash_data;
+
+#if CONFIG_CROS_FLASH_INIT_PRIORITY <= CONFIG_FLASH_INIT_PRIORITY
+#error "CONFIG_CROS_FLASH_INIT_PRIORITY must be greater than" \
+	"CONFIG_FLASH_INIT_PRIORITY."
+#endif
+
+DEVICE_DT_INST_DEFINE(0, flash_init, NULL, &cros_flash_data, NULL, POST_KERNEL,
+		      CONFIG_CROS_FLASH_INIT_PRIORITY, &cros_flash_driver_api);
diff --git a/zephyr/drivers/cros_flash/cros_flash.h b/zephyr/drivers/cros_flash/cros_flash.h
new file mode 100644
index 0000000000..280b650af9
--- /dev/null
+++ b/zephyr/drivers/cros_flash/cros_flash.h
@@ -0,0 +1,30 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef ZEPHYR_DRIVERS_CROS_FLASH_CROS_FLASH_H_
+#define ZEPHYR_DRIVERS_CROS_FLASH_CROS_FLASH_H_
+
+#include <zephyr/device.h>
+
+#define FLASH_SYSJUMP_TAG 0x5750 /* "WP" - Write Protect */
+
+struct cros_flash_protection {
+	bool control_access_blocked;
+	bool protection_changes_blocked;
+};
+
+int flash_change_wp(const struct device *dev, uint32_t disable_mask,
+		    uint32_t enable_mask);
+int flash_get_wp(const struct device *dev, uint32_t *protected_mask);
+int flash_change_rdp(const struct device *dev, bool enable, bool permanent);
+int flash_get_rdp(const struct device *dev, bool *enable, bool *permanent);
+int flash_block_protection_changes(const struct device *dev);
+int flash_block_control_access(const struct device *dev);
+
+int decode_wp_from_sysjump(struct cros_flash_protection *protection,
+			   uint32_t prot_flags, const void *jump_data,
+			   size_t size, int version);
+void prepare_wp_jump(struct cros_flash_protection *protection);
+#endif /* ZEPHYR_DRIVERS_CROS_FLASH_CROS_FLASH_H_ */
diff --git a/zephyr/drivers/cros_flash/cros_flash_it8xxx2.c b/zephyr/drivers/cros_flash/cros_flash_it8xxx2.c
new file mode 100644
index 0000000000..ee687c8f61
--- /dev/null
+++ b/zephyr/drivers/cros_flash/cros_flash_it8xxx2.c
@@ -0,0 +1,328 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define DT_DRV_COMPAT ite_it8xxx2_cros_flash
+
+#include "flash.h"
+#include "host_command.h"
+#include "system.h"
+#include "watchdog.h"
+
+#include <zephyr/drivers/flash.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+
+#include <drivers/cros_flash.h>
+#include <soc.h>
+
+LOG_MODULE_REGISTER(cros_flash, LOG_LEVEL_ERR);
+
+/* Device data */
+struct cros_flash_it8xxx2_data {
+	bool stuck_locked;
+	bool inconsistent_locked;
+	bool all_protected;
+};
+
+#define GCTRL_IT8XXX2_REG_BASE \
+	((struct gctrl_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(gctrl)))
+
+/* Driver convenience defines */
+#define DRV_DATA(dev) ((struct cros_flash_it8xxx2_data *)(dev)->data)
+
+static const struct device *const flash_controller =
+	DEVICE_DT_GET(DT_CHOSEN(zephyr_flash_controller));
+
+#define FWP_REG(bank) (bank / 8)
+#define FWP_MASK(bank) (1 << (bank % 8))
+
+enum flash_wp_interface {
+	FLASH_WP_HOST = 0x01,
+	FLASH_WP_DBGR = 0x02,
+	FLASH_WP_EC = 0x04,
+};
+
+enum flash_wp_status {
+	FLASH_WP_STATUS_PROTECT_RO = EC_FLASH_PROTECT_RO_NOW,
+	FLASH_WP_STATUS_PROTECT_ALL = EC_FLASH_PROTECT_ALL_NOW,
+};
+
+/**
+ * Protect flash banks until reboot.
+ *
+ * @param start_bank    Start bank to protect
+ * @param bank_count    Number of banks to protect
+ */
+static void flash_protect_banks(int start_bank, int bank_count,
+				enum flash_wp_interface wp_if)
+{
+	int bank;
+
+	for (bank = start_bank; bank < start_bank + bank_count; bank++) {
+		if (wp_if & FLASH_WP_EC)
+			IT83XX_GCTRL_EWPR0PFEC(FWP_REG(bank)) |= FWP_MASK(bank);
+		if (wp_if & FLASH_WP_HOST)
+			IT83XX_GCTRL_EWPR0PFH(FWP_REG(bank)) |= FWP_MASK(bank);
+		if (wp_if & FLASH_WP_DBGR)
+			IT83XX_GCTRL_EWPR0PFD(FWP_REG(bank)) |= FWP_MASK(bank);
+	}
+}
+
+static enum flash_wp_status flash_check_wp(void)
+{
+	enum flash_wp_status wp_status;
+	int all_bank_count, bank;
+
+	all_bank_count = CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE;
+
+	for (bank = 0; bank < all_bank_count; bank++) {
+		if (!(IT83XX_GCTRL_EWPR0PFEC(FWP_REG(bank)) & FWP_MASK(bank)))
+			break;
+	}
+
+	if (bank == WP_BANK_COUNT)
+		wp_status = FLASH_WP_STATUS_PROTECT_RO;
+	else if (bank == (WP_BANK_COUNT + PSTATE_BANK_COUNT))
+		wp_status = FLASH_WP_STATUS_PROTECT_RO;
+	else if (bank == all_bank_count)
+		wp_status = FLASH_WP_STATUS_PROTECT_ALL;
+	else
+		wp_status = 0;
+
+	return wp_status;
+}
+
+/* cros ec flash api functions */
+static int cros_flash_it8xxx2_init(const struct device *dev)
+{
+	struct cros_flash_it8xxx2_data *const data = DRV_DATA(dev);
+	int32_t reset_flags, prot_flags, unwanted_prot_flags;
+
+	reset_flags = system_get_reset_flags();
+	prot_flags = crec_flash_get_protect();
+	unwanted_prot_flags = EC_FLASH_PROTECT_ALL_NOW |
+			      EC_FLASH_PROTECT_ERROR_INCONSISTENT;
+
+	/*
+	 * If we have already jumped between images, an earlier image could
+	 * have applied write protection.  Nothing additional needs to be done.
+	 */
+	if (reset_flags & EC_RESET_FLAG_SYSJUMP)
+		return EC_SUCCESS;
+
+	if (prot_flags & EC_FLASH_PROTECT_GPIO_ASSERTED) {
+		/* Protect the entire flash of host interface */
+		flash_protect_banks(
+			0, CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE,
+			FLASH_WP_HOST);
+		/* Protect the entire flash of DBGR interface */
+		flash_protect_banks(
+			0, CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE,
+			FLASH_WP_DBGR);
+		/*
+		 * Write protect is asserted.  If we want RO flash protected,
+		 * protect it now.
+		 */
+		if ((prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT) &&
+		    !(prot_flags & EC_FLASH_PROTECT_RO_NOW)) {
+			int rv =
+				crec_flash_set_protect(EC_FLASH_PROTECT_RO_NOW,
+						       EC_FLASH_PROTECT_RO_NOW);
+			if (rv)
+				return rv;
+
+			/* Re-read flags */
+			prot_flags = crec_flash_get_protect();
+		}
+	} else {
+		/* Don't want RO flash protected */
+		unwanted_prot_flags |= EC_FLASH_PROTECT_RO_NOW;
+	}
+
+	/* If there are no unwanted flags, done */
+	if (!(prot_flags & unwanted_prot_flags))
+		return EC_SUCCESS;
+
+	/*
+	 * If the last reboot was a power-on reset, it should have cleared
+	 * write-protect.  If it didn't, then the flash write protect registers
+	 * have been permanently committed and we can't fix that.
+	 */
+	if (reset_flags & EC_RESET_FLAG_POWER_ON) {
+		data->stuck_locked = 1;
+		return EC_ERROR_ACCESS_DENIED;
+	} else {
+		/*
+		 * Set inconsistent flag, because there is no software
+		 * reset can clear write-protect.
+		 */
+		data->inconsistent_locked = 1;
+		return EC_ERROR_ACCESS_DENIED;
+	}
+
+	/* That doesn't return, so if we're still here that's an error */
+	return EC_ERROR_UNKNOWN;
+}
+
+static int cros_flash_it8xxx2_write(const struct device *dev, int offset,
+				    int size, const char *src_data)
+{
+	struct cros_flash_it8xxx2_data *const data = DRV_DATA(dev);
+
+	if (data->all_protected) {
+		return -EACCES;
+	}
+
+	/*
+	 * If AP sends write flash command continuously, EC might not have
+	 * chance to go back to hook task to touch watchdog. Reload watchdog
+	 * on each flash write to prevent the reset.
+	 */
+	if (IS_ENABLED(CONFIG_WATCHDOG))
+		watchdog_reload();
+
+	return flash_write(flash_controller, offset, src_data, size);
+}
+
+static int cros_flash_it8xxx2_erase(const struct device *dev, int offset,
+				    int size)
+{
+	struct cros_flash_it8xxx2_data *const data = DRV_DATA(dev);
+	int ret = 0;
+
+	if (data->all_protected) {
+		return -EACCES;
+	}
+	/*
+	 * Before the flash erasing, the interrupts should be disabled. In
+	 * the flash erasing loop, the SHI interrupt should be enabled to
+	 * handle AP's command, so irq_lock() is not used here.
+	 */
+	if (IS_ENABLED(CONFIG_ITE_IT8XXX2_INTC)) {
+		ite_intc_save_and_disable_interrupts();
+	}
+	/*
+	 * EC still need to handle AP's EC_CMD_GET_COMMS_STATUS command
+	 * during erasing.
+	 */
+	if (IS_ENABLED(HAS_TASK_HOSTCMD) &&
+	    IS_ENABLED(CONFIG_HOST_COMMAND_STATUS)) {
+		irq_enable(DT_IRQN(DT_NODELABEL(shi0)));
+	}
+	/* Always use sector erase command */
+	for (; size > 0; size -= CONFIG_FLASH_ERASE_SIZE) {
+		ret = flash_erase(flash_controller, offset,
+				  CONFIG_FLASH_ERASE_SIZE);
+		if (ret)
+			break;
+
+		offset += CONFIG_FLASH_ERASE_SIZE;
+		/*
+		 * If requested erase size is too large at one time on KGD
+		 * flash, we need to reload watchdog to prevent the reset.
+		 */
+		if (IS_ENABLED(CONFIG_WATCHDOG) && (size > 0x10000))
+			watchdog_reload();
+	}
+	/* Restore interrupts */
+	if (IS_ENABLED(CONFIG_ITE_IT8XXX2_INTC)) {
+		ite_intc_restore_interrupts();
+	}
+
+	return ret;
+}
+
+static int cros_flash_it8xxx2_get_protect(const struct device *dev, int bank)
+{
+	ARG_UNUSED(dev);
+
+	return IT83XX_GCTRL_EWPR0PFEC(FWP_REG(bank)) & FWP_MASK(bank);
+}
+
+static uint32_t cros_flash_it8xxx2_get_protect_flags(const struct device *dev)
+{
+	struct cros_flash_it8xxx2_data *const data = DRV_DATA(dev);
+	uint32_t flags = 0;
+
+	flags |= flash_check_wp();
+
+	if (data->all_protected)
+		flags |= EC_FLASH_PROTECT_ALL_NOW;
+
+	/* Check if blocks were stuck locked at pre-init */
+	if (data->stuck_locked)
+		flags |= EC_FLASH_PROTECT_ERROR_STUCK;
+
+	/* Check if flash protection is in inconsistent state at pre-init */
+	if (data->inconsistent_locked)
+		flags |= EC_FLASH_PROTECT_ERROR_INCONSISTENT;
+
+	return flags;
+}
+
+static int cros_flash_it8xxx2_protect_at_boot(const struct device *dev,
+					      uint32_t new_flags)
+{
+	return -ENOTSUP;
+}
+
+static int cros_flash_it8xxx2_protect_now(const struct device *dev, int all)
+{
+	struct gctrl_it8xxx2_regs *const gctrl_base = GCTRL_IT8XXX2_REG_BASE;
+	struct cros_flash_it8xxx2_data *const data = DRV_DATA(dev);
+
+	if (all) {
+		/* Protect the entire flash */
+		flash_protect_banks(
+			0, CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE,
+			FLASH_WP_EC);
+		data->all_protected = 1;
+	} else {
+		/* Protect the read-only section and persistent state */
+		flash_protect_banks(WP_BANK_OFFSET, WP_BANK_COUNT, FLASH_WP_EC);
+#ifdef PSTATE_BANK
+		flash_protect_banks(PSTATE_BANK, PSTATE_BANK_COUNT,
+				    FLASH_WP_EC);
+#endif
+	}
+
+	/*
+	 * Eflash protect lock register which can only be write 1 and only be
+	 * cleared by power-on reset.
+	 */
+	gctrl_base->GCTRL_EPLR |= IT8XXX2_GCTRL_EPLR_ENABLE;
+
+	return EC_SUCCESS;
+}
+
+/* cros ec flash driver registration */
+static const struct cros_flash_driver_api cros_flash_it8xxx2_driver_api = {
+	.init = cros_flash_it8xxx2_init,
+	.physical_write = cros_flash_it8xxx2_write,
+	.physical_erase = cros_flash_it8xxx2_erase,
+	.physical_get_protect = cros_flash_it8xxx2_get_protect,
+	.physical_get_protect_flags = cros_flash_it8xxx2_get_protect_flags,
+	.physical_protect_at_boot = cros_flash_it8xxx2_protect_at_boot,
+	.physical_protect_now = cros_flash_it8xxx2_protect_now,
+};
+
+static int flash_it8xxx2_init(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	if (!device_is_ready(flash_controller)) {
+		LOG_ERR("Selected flash device %s is not ready",
+			flash_controller->name);
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+static struct cros_flash_it8xxx2_data cros_flash_data;
+
+DEVICE_DT_INST_DEFINE(0, flash_it8xxx2_init, NULL, &cros_flash_data, NULL,
+		      POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
+		      &cros_flash_it8xxx2_driver_api);
diff --git a/zephyr/drivers/cros_flash/cros_flash_npcx.c b/zephyr/drivers/cros_flash/cros_flash_npcx.c
new file mode 100644
index 0000000000..6a0a87f7c1
--- /dev/null
+++ b/zephyr/drivers/cros_flash/cros_flash_npcx.c
@@ -0,0 +1,664 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define DT_DRV_COMPAT nuvoton_npcx_cros_flash
+
+#include "../drivers/flash/spi_nor.h"
+#include "flash.h"
+#include "spi_flash_reg.h"
+#include "watchdog.h"
+#include "write_protect.h"
+
+#include <zephyr/drivers/flash.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/spi.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+
+#include <drivers/cros_flash.h>
+#include <soc.h>
+
+LOG_MODULE_REGISTER(cros_flash, LOG_LEVEL_ERR);
+
+static int all_protected; /* Has all-flash protection been requested? */
+static int addr_prot_start;
+static int addr_prot_length;
+static uint8_t saved_sr1;
+static uint8_t saved_sr2;
+
+/* Device data */
+struct cros_flash_npcx_data {
+	const struct device *flash_dev;
+	const struct device *spi_ctrl_dev;
+};
+
+static struct spi_config spi_cfg;
+
+#define FLASH_DEV DT_CHOSEN(zephyr_flash_controller)
+#define SPI_CONTROLLER_DEV DT_NODELABEL(spi_fiu0)
+
+#define DRV_DATA(dev) ((struct cros_flash_npcx_data *)(dev)->data)
+
+#define SPI_NOR_CMD_RDSR2 0x35
+
+/* cros ec flash local functions */
+static int cros_flash_npcx_get_status_reg(const struct device *dev,
+					  uint8_t cmd_code, uint8_t *data)
+{
+	uint8_t opcode;
+	struct cros_flash_npcx_data *dev_data = DRV_DATA(dev);
+
+	struct spi_buf spi_buf[2] = {
+		[0] = {
+			.buf = &opcode,
+			.len = 1,
+		},
+		[1] = {
+			.buf = data,
+			.len = 1,
+		}
+	};
+
+	const struct spi_buf_set tx_set = {
+		.buffers = spi_buf,
+		.count = 2,
+	};
+
+	const struct spi_buf_set rx_set = {
+		.buffers = spi_buf,
+		.count = 2,
+	};
+
+	if (data == 0)
+		return -EINVAL;
+
+	opcode = cmd_code;
+	return spi_transceive(dev_data->spi_ctrl_dev, &spi_cfg, &tx_set,
+			      &rx_set);
+}
+
+static int cros_flash_npcx_wait_ready(const struct device *dev)
+{
+	int wait_period = 10; /* 10 us period t0 check status register */
+	int timeout = (10 * USEC_PER_SEC) / wait_period; /* 10 seconds */
+
+	do {
+		uint8_t reg;
+
+		cros_flash_npcx_get_status_reg(dev, SPI_NOR_CMD_RDSR, &reg);
+		if ((reg & SPI_NOR_WIP_BIT) == 0)
+			break;
+		k_usleep(wait_period);
+	} while (--timeout); /* Wait for busy bit clear */
+
+	if (timeout) {
+		return 0;
+	} else {
+		return -ETIMEDOUT;
+	}
+}
+
+/* Check the BUSY bit is cleared and WE bit is set */
+static int cros_flash_npcx_wait_ready_and_we(const struct device *dev)
+{
+	int wait_period = 10; /* 10 us period t0 check status register */
+	int timeout = (10 * USEC_PER_SEC) / wait_period; /* 10 seconds */
+
+	do {
+		uint8_t reg;
+
+		cros_flash_npcx_get_status_reg(dev, SPI_NOR_CMD_RDSR, &reg);
+		if ((reg & SPI_NOR_WIP_BIT) == 0 &&
+		    (reg & SPI_NOR_WEL_BIT) != 0)
+			break;
+		k_usleep(wait_period);
+	} while (--timeout); /* Wait for busy bit clear */
+
+	if (timeout) {
+		return 0;
+	} else {
+		return -ETIMEDOUT;
+	}
+}
+
+static int cros_flash_npcx_set_write_enable(const struct device *dev)
+{
+	int ret;
+	uint8_t opcode = SPI_NOR_CMD_WREN;
+	struct cros_flash_npcx_data *data = DRV_DATA(dev);
+
+	struct spi_buf spi_buf = {
+		.buf = &opcode,
+		.len = 1,
+	};
+
+	const struct spi_buf_set tx_set = {
+		.buffers = &spi_buf,
+		.count = 1,
+	};
+
+	/* Wait for previous operation to complete */
+	ret = cros_flash_npcx_wait_ready(dev);
+	if (ret != 0)
+		return ret;
+
+	/* Write enable command */
+	ret = spi_transceive(data->spi_ctrl_dev, &spi_cfg, &tx_set, NULL);
+	if (ret != 0)
+		return ret;
+
+	/* Wait for flash is not busy */
+	return cros_flash_npcx_wait_ready_and_we(dev);
+}
+
+static int cros_flash_npcx_set_status_reg(const struct device *dev,
+					  uint8_t *data)
+{
+	uint8_t opcode = SPI_NOR_CMD_WRSR;
+	int ret = 0;
+	struct cros_flash_npcx_data *dev_data = DRV_DATA(dev);
+
+	struct spi_buf spi_buf[2] = {
+		[0] = {
+			.buf = &opcode,
+			.len = 1,
+		},
+		[1] = {
+			.buf = data,
+			.len = 2,
+		}
+	};
+
+	const struct spi_buf_set tx_set = {
+		.buffers = spi_buf,
+		.count = 2,
+	};
+
+	if (data == 0) {
+		return -EINVAL;
+	}
+
+	/* Enable write */
+	ret = cros_flash_npcx_set_write_enable(dev);
+	if (ret != 0)
+		return ret;
+
+	ret = spi_transceive(dev_data->spi_ctrl_dev, &spi_cfg, &tx_set, NULL);
+	if (ret != 0)
+		return ret;
+	return cros_flash_npcx_wait_ready(dev);
+}
+
+static int cros_flash_npcx_write_protection_set(const struct device *dev,
+						bool enable)
+{
+	int ret = 0;
+
+	/* Write protection can be cleared only by core domain reset */
+	if (!enable) {
+		LOG_ERR("WP can be disabled only via core domain reset ");
+		return -ENOTSUP;
+	}
+	ret = npcx_pinctrl_flash_write_protect_set();
+
+	return ret;
+}
+
+static int cros_flash_npcx_write_protection_is_set(const struct device *dev)
+{
+	return npcx_pinctrl_flash_write_protect_is_set();
+}
+
+static int cros_flash_npcx_uma_lock(const struct device *dev, bool enable)
+{
+	struct cros_flash_npcx_data *data = DRV_DATA(dev);
+
+	if (enable) {
+		spi_cfg.operation |= SPI_LOCK_ON;
+	} else {
+		spi_cfg.operation &= ~SPI_LOCK_ON;
+	}
+
+	return spi_transceive(data->spi_ctrl_dev, &spi_cfg, NULL, NULL);
+}
+
+static void flash_get_status(const struct device *dev, uint8_t *sr1,
+			     uint8_t *sr2)
+{
+	if (all_protected) {
+		*sr1 = saved_sr1;
+		*sr2 = saved_sr2;
+		return;
+	}
+
+	/* Lock physical flash operations */
+	crec_flash_lock_mapped_storage(1);
+
+	/* Read status register1 */
+	cros_flash_npcx_get_status_reg(dev, SPI_NOR_CMD_RDSR, sr1);
+	/* Read status register2 */
+	cros_flash_npcx_get_status_reg(dev, SPI_NOR_CMD_RDSR2, sr2);
+
+	/* Unlock physical flash operations */
+	crec_flash_lock_mapped_storage(0);
+}
+
+static int flash_set_status(const struct device *dev, uint8_t sr1, uint8_t sr2)
+{
+	int rv;
+	uint8_t regs[2];
+
+	regs[0] = sr1;
+	regs[1] = sr2;
+
+	/* Lock physical flash operations */
+	crec_flash_lock_mapped_storage(1);
+	rv = cros_flash_npcx_set_status_reg(dev, regs);
+	/* Unlock physical flash operations */
+	crec_flash_lock_mapped_storage(0);
+
+	return rv;
+}
+
+static int is_int_flash_protected(const struct device *dev)
+{
+	return cros_flash_npcx_write_protection_is_set(dev);
+}
+
+static void flash_protect_int_flash(const struct device *dev, int enable)
+{
+	/*
+	 * Please notice the type of WP_IF bit is R/W1S. Once it's set,
+	 * only rebooting EC can clear it.
+	 */
+	if (enable)
+		cros_flash_npcx_write_protection_set(dev, enable);
+}
+
+static void flash_uma_lock(const struct device *dev, int enable)
+{
+	if (enable && !all_protected) {
+		/*
+		 * Store SR1 / SR2 for later use since we're about to lock
+		 * out all access (including read access) to these regs.
+		 */
+		flash_get_status(dev, &saved_sr1, &saved_sr2);
+	}
+
+	cros_flash_npcx_uma_lock(dev, enable);
+	all_protected = enable;
+}
+
+static int flash_set_status_for_prot(const struct device *dev, int reg1,
+				     int reg2)
+{
+	/*
+	 * Writing SR regs will fail if our UMA lock is enabled. If WP
+	 * is deasserted then remove the lock and allow the write.
+	 */
+	if (all_protected) {
+		if (is_int_flash_protected(dev))
+			return EC_ERROR_ACCESS_DENIED;
+
+		if (crec_flash_get_protect() & EC_FLASH_PROTECT_GPIO_ASSERTED)
+			return EC_ERROR_ACCESS_DENIED;
+		flash_uma_lock(dev, 0);
+	}
+
+	/*
+	 * If WP# is active and ec doesn't protect the status registers of
+	 * internal spi-flash, protect it now before setting them.
+	 */
+	flash_protect_int_flash(dev, write_protect_is_asserted());
+
+	flash_set_status(dev, reg1, reg2);
+
+	spi_flash_reg_to_protect(reg1, reg2, &addr_prot_start,
+				 &addr_prot_length);
+
+	return EC_SUCCESS;
+}
+
+static int flash_check_prot_reg(const struct device *dev, unsigned int offset,
+				unsigned int bytes)
+{
+	unsigned int start;
+	unsigned int len;
+	uint8_t sr1, sr2;
+	int rv = EC_SUCCESS;
+
+	/*
+	 * If WP# is active and ec doesn't protect the status registers of
+	 * internal spi-flash, protect it now.
+	 */
+	flash_protect_int_flash(dev, write_protect_is_asserted());
+
+	/* Invalid value */
+	if (offset + bytes > CONFIG_FLASH_SIZE_BYTES)
+		return EC_ERROR_INVAL;
+
+	/* Compute current protect range */
+	flash_get_status(dev, &sr1, &sr2);
+	rv = spi_flash_reg_to_protect(sr1, sr2, &start, &len);
+	if (rv)
+		return rv;
+
+	/* Check if ranges overlap */
+	if (MAX(start, offset) < MIN(start + len, offset + bytes))
+		return EC_ERROR_ACCESS_DENIED;
+
+	return EC_SUCCESS;
+}
+
+static int flash_write_prot_reg(const struct device *dev, unsigned int offset,
+				unsigned int bytes, int hw_protect)
+{
+	int rv;
+	uint8_t sr1, sr2;
+
+	/* Invalid values */
+	if (offset + bytes > CONFIG_FLASH_SIZE_BYTES)
+		return EC_ERROR_INVAL;
+
+	/* Compute desired protect range */
+	flash_get_status(dev, &sr1, &sr2);
+	rv = spi_flash_protect_to_reg(offset, bytes, &sr1, &sr2);
+	if (rv)
+		return rv;
+
+	if (hw_protect)
+		sr1 |= SPI_FLASH_SR1_SRP0;
+
+	return flash_set_status_for_prot(dev, sr1, sr2);
+}
+
+static int flash_check_prot_range(unsigned int offset, unsigned int bytes)
+{
+	/* Invalid value */
+	if (offset + bytes > CONFIG_FLASH_SIZE_BYTES)
+		return EC_ERROR_INVAL;
+
+	/* Check if ranges overlap */
+	if (MAX(addr_prot_start, offset) <
+	    MIN(addr_prot_start + addr_prot_length, offset + bytes))
+		return EC_ERROR_ACCESS_DENIED;
+
+	return EC_SUCCESS;
+}
+
+static void flash_set_quad_enable(const struct device *dev, bool enable)
+{
+	uint8_t sr1, sr2;
+
+	flash_get_status(dev, &sr1, &sr2);
+
+	/* If QE is the same value, return directly. */
+	if (!!(sr2 & SPI_FLASH_SR2_QE) == enable)
+		return;
+
+	if (enable)
+		sr2 |= SPI_FLASH_SR2_QE;
+	else
+		sr2 &= ~SPI_FLASH_SR2_QE;
+	flash_set_status(dev, sr1, sr2);
+}
+
+/* cros ec flash api functions */
+static int cros_flash_npcx_init(const struct device *dev)
+{
+	/* Initialize UMA to unlocked */
+	flash_uma_lock(dev, 0);
+
+	/*
+	 * Disable flash quad enable to avoid /WP pin function is not
+	 * available. */
+	flash_set_quad_enable(dev, false);
+
+	/*
+	 * Protect status registers of internal spi-flash if WP# is active
+	 * during ec initialization.
+	 */
+	flash_protect_int_flash(dev, write_protect_is_asserted());
+
+	return 0;
+}
+
+static int cros_flash_npcx_write(const struct device *dev, int offset, int size,
+				 const char *src_data)
+{
+	int ret = 0;
+	struct cros_flash_npcx_data *data = DRV_DATA(dev);
+
+	/* check protection */
+	if (all_protected)
+		return EC_ERROR_ACCESS_DENIED;
+
+	/* check protection */
+	if (flash_check_prot_range(offset, size))
+		return EC_ERROR_ACCESS_DENIED;
+
+	/* Invalid data pointer? */
+	if (src_data == 0) {
+		return -EINVAL;
+	}
+
+	/*
+	 * If the AP sends a sequence of write commands, we may not have time to
+	 * reload the watchdog normally.  Force a reload here to avoid the
+	 * watchdog triggering in the middle of flashing.
+	 */
+	if (IS_ENABLED(CONFIG_WATCHDOG))
+		watchdog_reload();
+
+	/* Lock physical flash operations */
+	crec_flash_lock_mapped_storage(1);
+
+	ret = flash_write(data->flash_dev, offset, src_data, size);
+
+	/* Unlock physical flash operations */
+	crec_flash_lock_mapped_storage(0);
+
+	return ret;
+}
+
+static int cros_flash_npcx_erase(const struct device *dev, int offset, int size)
+{
+	int ret = 0;
+	struct cros_flash_npcx_data *data = DRV_DATA(dev);
+
+	/* check protection */
+	if (all_protected)
+		return EC_ERROR_ACCESS_DENIED;
+
+	/* check protection */
+	if (flash_check_prot_range(offset, size))
+		return EC_ERROR_ACCESS_DENIED;
+
+	/* address must be aligned to erase size */
+	if ((offset % CONFIG_FLASH_ERASE_SIZE) != 0) {
+		return -EINVAL;
+	}
+
+	/* Erase size must be a non-zero multiple of sectors */
+	if ((size == 0) || (size % CONFIG_FLASH_ERASE_SIZE) != 0) {
+		return -EINVAL;
+	}
+
+	/* Lock physical flash operations */
+	crec_flash_lock_mapped_storage(1);
+
+	for (; size > 0; size -= CONFIG_FLASH_ERASE_SIZE) {
+		/*
+		 * Reload the watchdog timer, so that erasing many flash pages
+		 * doesn't cause a watchdog reset
+		 */
+		if (IS_ENABLED(CONFIG_WATCHDOG))
+			watchdog_reload();
+
+		/* Start erase */
+		ret = flash_erase(data->flash_dev, offset,
+				  CONFIG_FLASH_ERASE_SIZE);
+		if (ret)
+			break;
+
+		offset += CONFIG_FLASH_ERASE_SIZE;
+	}
+
+	/* Unlock physical flash operations */
+	crec_flash_lock_mapped_storage(0);
+
+	return ret;
+}
+
+static int cros_flash_npcx_get_protect(const struct device *dev, int bank)
+{
+	uint32_t addr = bank * CONFIG_FLASH_BANK_SIZE;
+
+	return flash_check_prot_reg(dev, addr, CONFIG_FLASH_BANK_SIZE);
+}
+
+static uint32_t cros_flash_npcx_get_protect_flags(const struct device *dev)
+{
+	uint32_t flags = 0;
+	int rv;
+	uint8_t sr1, sr2;
+	unsigned int start, len;
+
+	/* Check if WP region is protected in status register */
+	rv = flash_check_prot_reg(dev, WP_BANK_OFFSET * CONFIG_FLASH_BANK_SIZE,
+				  WP_BANK_COUNT * CONFIG_FLASH_BANK_SIZE);
+	if (rv == EC_ERROR_ACCESS_DENIED)
+		flags |= EC_FLASH_PROTECT_RO_AT_BOOT;
+	else if (rv)
+		return EC_FLASH_PROTECT_ERROR_UNKNOWN;
+
+	/*
+	 * If the status register protects a range, but SRP0 is not set,
+	 * or Quad Enable (QE) is set,
+	 * flags should indicate EC_FLASH_PROTECT_ERROR_INCONSISTENT.
+	 */
+	flash_get_status(dev, &sr1, &sr2);
+	rv = spi_flash_reg_to_protect(sr1, sr2, &start, &len);
+	if (rv)
+		return EC_FLASH_PROTECT_ERROR_UNKNOWN;
+	if (len && (!(sr1 & SPI_FLASH_SR1_SRP0) || (sr2 & SPI_FLASH_SR2_QE)))
+		flags |= EC_FLASH_PROTECT_ERROR_INCONSISTENT;
+
+	/* Read all-protected state from our shadow copy */
+	if (all_protected)
+		flags |= EC_FLASH_PROTECT_ALL_NOW;
+
+	return flags;
+}
+
+static int cros_flash_npcx_protect_at_boot(const struct device *dev,
+					   uint32_t new_flags)
+{
+	int ret;
+
+	if ((new_flags & (EC_FLASH_PROTECT_RO_AT_BOOT |
+			  EC_FLASH_PROTECT_ALL_AT_BOOT)) == 0) {
+		/* Clear protection bits in status register */
+		return flash_set_status_for_prot(dev, 0, 0);
+	}
+
+	ret = flash_write_prot_reg(dev, CONFIG_WP_STORAGE_OFF,
+				   CONFIG_WP_STORAGE_SIZE, 1);
+
+	/*
+	 * Set UMA_LOCK bit for locking all UMA transaction.
+	 * But we still can read directly from flash mapping address
+	 */
+	if (new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT)
+		flash_uma_lock(dev, 1);
+
+	return ret;
+}
+
+static int cros_flash_npcx_protect_now(const struct device *dev, int all)
+{
+	if (all) {
+		/*
+		 * Set UMA_LOCK bit for locking all UMA transaction.
+		 * But we still can read directly from flash mapping address
+		 */
+		flash_uma_lock(dev, 1);
+	} else {
+		/* TODO: Implement RO "now" protection */
+	}
+
+	return EC_SUCCESS;
+}
+
+static int cros_flash_npcx_get_jedec_id(const struct device *dev,
+					uint8_t *manufacturer, uint16_t *device)
+{
+	int ret;
+	uint8_t jedec_id[3];
+	struct cros_flash_npcx_data *data = DRV_DATA(dev);
+
+	/* Lock physical flash operations */
+	crec_flash_lock_mapped_storage(1);
+
+	ret = flash_read_jedec_id(data->flash_dev, jedec_id);
+	if (ret == 0) {
+		*manufacturer = jedec_id[0];
+		*device = (jedec_id[1] << 8) | jedec_id[2];
+	}
+
+	/* Unlock physical flash operations */
+	crec_flash_lock_mapped_storage(0);
+
+	return ret;
+}
+
+static int cros_flash_npcx_get_status(const struct device *dev, uint8_t *sr1,
+				      uint8_t *sr2)
+{
+	flash_get_status(dev, sr1, sr2);
+
+	return EC_SUCCESS;
+}
+
+/* cros ec flash driver registration */
+static const struct cros_flash_driver_api cros_flash_npcx_driver_api = {
+	.init = cros_flash_npcx_init,
+	.physical_write = cros_flash_npcx_write,
+	.physical_erase = cros_flash_npcx_erase,
+	.physical_get_protect = cros_flash_npcx_get_protect,
+	.physical_get_protect_flags = cros_flash_npcx_get_protect_flags,
+	.physical_protect_at_boot = cros_flash_npcx_protect_at_boot,
+	.physical_protect_now = cros_flash_npcx_protect_now,
+	.physical_get_jedec_id = cros_flash_npcx_get_jedec_id,
+	.physical_get_status = cros_flash_npcx_get_status,
+};
+
+static int flash_npcx_init(const struct device *dev)
+{
+	struct cros_flash_npcx_data *data = DRV_DATA(dev);
+
+	data->flash_dev = DEVICE_DT_GET(FLASH_DEV);
+	if (!device_is_ready(data->flash_dev)) {
+		LOG_ERR("%s device not ready", data->flash_dev->name);
+		return -ENODEV;
+	}
+
+	data->spi_ctrl_dev = DEVICE_DT_GET(SPI_CONTROLLER_DEV);
+	if (!device_is_ready(data->spi_ctrl_dev)) {
+		LOG_ERR("%s device not ready", data->spi_ctrl_dev->name);
+		return -ENODEV;
+	}
+
+	return EC_SUCCESS;
+}
+
+#if CONFIG_CROS_FLASH_NPCX_INIT_PRIORITY <= CONFIG_SPI_NOR_INIT_PRIORITY
+#error "CONFIG_CROS_FLASH_NPCX_INIT_PRIORITY must be greater than" \
+	"CONFIG_SPI_NOR_INIT_PRIORITY."
+#endif
+static struct cros_flash_npcx_data cros_flash_data;
+DEVICE_DT_INST_DEFINE(0, flash_npcx_init, NULL, &cros_flash_data, NULL,
+		      POST_KERNEL, CONFIG_CROS_FLASH_NPCX_INIT_PRIORITY,
+		      &cros_flash_npcx_driver_api);
diff --git a/zephyr/drivers/cros_flash/cros_flash_stm32_backend.c b/zephyr/drivers/cros_flash/cros_flash_stm32_backend.c
new file mode 100644
index 0000000000..5101139e3e
--- /dev/null
+++ b/zephyr/drivers/cros_flash/cros_flash_stm32_backend.c
@@ -0,0 +1,133 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cros_flash.h"
+#include "system.h"
+
+#include <zephyr/drivers/flash/stm32_flash_api_extensions.h>
+
+int flash_change_wp(const struct device *dev, uint32_t disable_mask,
+		    uint32_t enable_mask)
+{
+	int err;
+	struct flash_stm32_ex_op_sector_wp_in wp_request = {
+		.enable_mask = enable_mask,
+		.disable_mask = disable_mask,
+	};
+
+	err = flash_ex_op(dev, FLASH_STM32_EX_OP_SECTOR_WP,
+			  (uintptr_t)&wp_request, NULL);
+
+	return err;
+}
+
+int flash_get_wp(const struct device *dev, uint32_t *protected_mask)
+{
+	int err;
+	struct flash_stm32_ex_op_sector_wp_out wp_status;
+
+	if (!protected_mask)
+		return -EINVAL;
+
+	err = flash_ex_op(dev, FLASH_STM32_EX_OP_SECTOR_WP, (uintptr_t)NULL,
+			  &wp_status);
+	*protected_mask = wp_status.protected_mask;
+
+	return err;
+}
+
+int flash_change_rdp(const struct device *dev, bool enable, bool permanent)
+{
+	int err;
+	struct flash_stm32_ex_op_rdp rdp_request = {
+		.enable = enable,
+		.permanent = permanent,
+	};
+
+	err = flash_ex_op(dev, FLASH_STM32_EX_OP_RDP, (uintptr_t)&rdp_request,
+			  NULL);
+
+	return err;
+}
+
+int flash_get_rdp(const struct device *dev, bool *enable, bool *permanent)
+{
+	int err;
+	struct flash_stm32_ex_op_rdp rdp_status;
+
+	err = flash_ex_op(dev, FLASH_STM32_EX_OP_RDP, (uintptr_t)NULL,
+			  &rdp_status);
+
+	if (enable)
+		*enable = rdp_status.enable;
+
+	if (permanent)
+		*permanent = rdp_status.permanent;
+
+	return err;
+}
+
+int flash_block_protection_changes(const struct device *dev)
+{
+	return flash_ex_op(dev, FLASH_STM32_EX_OP_BLOCK_OPTION_REG,
+			   (uintptr_t)NULL, NULL);
+}
+
+int flash_block_control_access(const struct device *dev)
+{
+	return flash_ex_op(dev, FLASH_STM32_EX_OP_BLOCK_CONTROL_REG,
+			   (uintptr_t)NULL, NULL);
+}
+
+#ifdef CONFIG_CROS_FLASH_STM32_EC_JUMP_STRUCTURE
+
+#define CROS_FLASH_STM32_PROT_VERSION 1
+#ifdef CONFIG_SOC_SERIES_STM32F4X
+struct jump_wp_state {
+	int entire_flash_locked;
+};
+
+int decode_wp_from_sysjump(struct cros_flash_protection *protection,
+			   uint32_t prot_flags, const void *jump_data,
+			   size_t size, int version)
+{
+	const struct jump_wp_state *wp =
+		(const struct jump_wp_state *)jump_data;
+
+	if (!protection || !wp || size != sizeof(*wp) ||
+	    version != CROS_FLASH_STM32_PROT_VERSION)
+		return -EINVAL;
+
+	if (wp->entire_flash_locked) {
+		protection->control_access_blocked = true;
+		protection->protection_changes_blocked = true;
+	} else if (prot_flags & EC_FLASH_PROTECT_RO_NOW) {
+		/*
+		 * If RO_NOW flag is set we know that RO image disabled option
+		 * bytes.
+		 */
+		protection->protection_changes_blocked = true;
+	}
+
+	return EC_SUCCESS;
+}
+
+void prepare_wp_jump(struct cros_flash_protection *protection)
+{
+	struct jump_wp_state wp_state;
+
+	if (!protection)
+		return;
+
+	wp_state.entire_flash_locked = 0;
+
+	if (protection->control_access_blocked)
+		wp_state.entire_flash_locked = 1;
+
+	system_add_jump_tag(FLASH_SYSJUMP_TAG, CROS_FLASH_STM32_PROT_VERSION,
+			    sizeof(wp_state), &wp_state);
+}
+#endif /* CONFIG_SOC_SERIES_STM32F4X */
+#endif /* CONFIG_CROS_FLASH_STM32_EC_JUMP_STRUCTURE */
diff --git a/zephyr/drivers/cros_flash/cros_flash_xec.c b/zephyr/drivers/cros_flash/cros_flash_xec.c
new file mode 100644
index 0000000000..6cb36bce66
--- /dev/null
+++ b/zephyr/drivers/cros_flash/cros_flash_xec.c
@@ -0,0 +1,599 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define DT_DRV_COMPAT microchip_xec_cros_flash
+
+#include "../drivers/flash/spi_nor.h"
+#include "flash.h"
+#include "spi_flash_reg.h"
+#include "write_protect.h"
+
+#include <zephyr/drivers/flash.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/spi.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+
+#include <drivers/cros_flash.h>
+#include <soc.h>
+
+LOG_MODULE_REGISTER(cros_flash, LOG_LEVEL_ERR);
+
+static int all_protected;
+static int addr_prot_start;
+static int addr_prot_length;
+static uint8_t saved_sr1;
+
+/* Device data */
+struct cros_flash_xec_data {
+	const struct device *flash_dev;
+	const struct device *spi_ctrl_dev;
+};
+
+/* initialize spi_cfg, SPI driver checks "SPI word size" field */
+static struct spi_config spi_cfg = {
+	.operation = SPI_WORD_SET(8) | SPI_LINES_SINGLE,
+	.frequency = DT_PROP(DT_NODELABEL(int_flash), spi_max_frequency)
+};
+
+#define FLASH_DEV DT_NODELABEL(int_flash)
+#define SPI_CONTROLLER_DEV DT_NODELABEL(spi0)
+
+/* cros ec flash local functions */
+static int cros_flash_xec_get_status_reg(const struct device *dev,
+					 uint8_t cmd_code, uint8_t *data)
+{
+	uint8_t opcode;
+	struct cros_flash_xec_data *dev_data = dev->data;
+
+	struct spi_buf spi_buf[2] = {
+		[0] = {
+			.buf = &opcode,
+			.len = 1,
+		},
+		[1] = {
+			.buf = data,
+			.len = 1,
+		}
+	};
+
+	const struct spi_buf_set tx_set = {
+		.buffers = spi_buf,
+		.count = 2,
+	};
+
+	const struct spi_buf_set rx_set = {
+		.buffers = spi_buf,
+		.count = 2,
+	};
+
+	if (data == 0)
+		return -EINVAL;
+
+	opcode = cmd_code;
+	return spi_transceive(dev_data->spi_ctrl_dev, &spi_cfg, &tx_set,
+			      &rx_set);
+}
+
+static int cros_flash_xec_wait_ready(const struct device *dev)
+{
+	int wait_period = 10; /* 10 us period t0 check status register */
+	int timeout = (10 * USEC_PER_SEC) / wait_period; /* 10 seconds */
+
+	do {
+		uint8_t reg;
+
+		cros_flash_xec_get_status_reg(dev, SPI_NOR_CMD_RDSR, &reg);
+		if ((reg & SPI_NOR_WIP_BIT) == 0)
+			break;
+
+		k_usleep(wait_period);
+	} while (--timeout); /* Wait for busy bit clear */
+
+	if (timeout)
+		return 0;
+	else
+		return -ETIMEDOUT;
+}
+
+/* Check the BUSY bit is cleared and WE bit is set */
+static int cros_flash_xec_wait_ready_and_we(const struct device *dev)
+{
+	int wait_period = 10; /* 10 us period t0 check status register */
+	int timeout = (10 * USEC_PER_SEC) / wait_period; /* 10 seconds */
+
+	do {
+		uint8_t reg;
+
+		cros_flash_xec_get_status_reg(dev, SPI_NOR_CMD_RDSR, &reg);
+		if ((reg & SPI_NOR_WIP_BIT) == 0 &&
+		    (reg & SPI_NOR_WEL_BIT) != 0) {
+			break;
+		}
+		k_usleep(wait_period);
+	} while (--timeout); /* Wait for busy bit clear */
+
+	if (timeout)
+		return 0;
+	else
+		return -ETIMEDOUT;
+}
+
+static int cros_flash_xec_set_write_enable(const struct device *dev)
+{
+	int ret;
+	uint8_t opcode = SPI_NOR_CMD_WREN;
+	struct cros_flash_xec_data *data = dev->data;
+
+	struct spi_buf spi_buf = {
+		.buf = &opcode,
+		.len = 1,
+	};
+
+	const struct spi_buf_set tx_set = {
+		.buffers = &spi_buf,
+		.count = 1,
+	};
+
+	/* Wait for previous operation to complete */
+	ret = cros_flash_xec_wait_ready(dev);
+	if (ret != 0)
+		return ret;
+
+	/* Write enable command */
+	ret = spi_transceive(data->spi_ctrl_dev, &spi_cfg, &tx_set, NULL);
+	if (ret != 0)
+		return ret;
+
+	/* Wait for flash is not busy */
+	return cros_flash_xec_wait_ready_and_we(dev);
+}
+
+static int cros_flash_xec_set_status_reg(const struct device *dev,
+					 uint8_t *data)
+{
+	uint8_t opcode = SPI_NOR_CMD_WRSR;
+	int ret = 0;
+	struct cros_flash_xec_data *dev_data = dev->data;
+
+	struct spi_buf spi_buf[2] = {
+		[0] = {
+			.buf = &opcode,
+			.len = 1,
+		},
+		[1] = {
+			.buf = data,
+			.len = 1,
+		}
+	};
+
+	const struct spi_buf_set tx_set = {
+		.buffers = spi_buf,
+		.count = 2,
+	};
+
+	if (data == 0)
+		return -EINVAL;
+
+	/* Enable write */
+	ret = cros_flash_xec_set_write_enable(dev);
+	if (ret != 0)
+		return ret;
+
+	ret = spi_transceive(dev_data->spi_ctrl_dev, &spi_cfg, &tx_set, NULL);
+	if (ret != 0)
+		return ret;
+	return cros_flash_xec_wait_ready(dev);
+}
+
+static int cros_flash_xec_write_protection_set(const struct device *dev,
+					       bool enable)
+{
+	int ret = 0;
+
+	/* Write protection can be cleared only by core domain reset */
+	if (!enable) {
+		LOG_ERR("WP can be disabled only via core domain reset ");
+		return -ENOTSUP;
+	}
+	/* MCHP TODO need API call to set flash WP# pin active: GPIO driver? */
+
+	return ret;
+}
+
+static int cros_flash_xec_write_protection_is_set(const struct device *dev)
+{
+	/* MCHP TODO - Read WP# pin state: GPIO driver? */
+	return 0;
+}
+
+static int cros_flash_xec_uma_lock(const struct device *dev, bool enable)
+{
+	struct cros_flash_xec_data *data = dev->data;
+
+	if (enable)
+		spi_cfg.operation |= SPI_LOCK_ON;
+	else
+		spi_cfg.operation &= ~SPI_LOCK_ON;
+
+	return spi_transceive(data->spi_ctrl_dev, &spi_cfg, NULL, NULL);
+}
+
+static void flash_get_status(const struct device *dev, uint8_t *sr1)
+{
+	if (all_protected) {
+		*sr1 = saved_sr1;
+		return;
+	}
+
+	/* Lock physical flash operations */
+	crec_flash_lock_mapped_storage(1);
+
+	/* Read status register1 */
+	cros_flash_xec_get_status_reg(dev, SPI_NOR_CMD_RDSR, sr1);
+
+	/* Unlock physical flash operations */
+	crec_flash_lock_mapped_storage(0);
+}
+
+static int flash_set_status(const struct device *dev, uint8_t sr1)
+{
+	int rv;
+	uint8_t regs[2];
+
+	regs[0] = sr1;
+	regs[1] = 0;
+
+	/* Lock physical flash operations */
+	crec_flash_lock_mapped_storage(1);
+	rv = cros_flash_xec_set_status_reg(dev, regs);
+	/* Unlock physical flash operations */
+	crec_flash_lock_mapped_storage(0);
+
+	return rv;
+}
+
+static int is_int_flash_protected(const struct device *dev)
+{
+	return cros_flash_xec_write_protection_is_set(dev);
+}
+
+static void flash_protect_int_flash(const struct device *dev, int enable)
+{
+	/*
+	 * Please notice the type of WP_IF bit is R/W1S. Once it's set,
+	 * only rebooting EC can clear it.
+	 */
+	if (enable)
+		cros_flash_xec_write_protection_set(dev, enable);
+}
+
+static void flash_uma_lock(const struct device *dev, int enable)
+{
+	if (enable && !all_protected) {
+		/*
+		 * Store SR1 for later use since we're about to lock
+		 * out all access (including read access) to these regs.
+		 */
+		flash_get_status(dev, &saved_sr1);
+	}
+
+	cros_flash_xec_uma_lock(dev, enable);
+	all_protected = enable;
+}
+
+static int flash_set_status_for_prot(const struct device *dev, int reg1)
+{
+	/*
+	 * Writing SR regs will fail if our UMA lock is enabled. If WP
+	 * is deasserted then remove the lock and allow the write.
+	 */
+	if (all_protected) {
+		if (is_int_flash_protected(dev))
+			return EC_ERROR_ACCESS_DENIED;
+
+		if (crec_flash_get_protect() & EC_FLASH_PROTECT_GPIO_ASSERTED)
+			return EC_ERROR_ACCESS_DENIED;
+
+		flash_uma_lock(dev, 0);
+	}
+
+	/*
+	 * If WP# is active and ec doesn't protect the status registers of
+	 * internal spi-flash, protect it now before setting them.
+	 */
+	flash_protect_int_flash(dev, write_protect_is_asserted());
+
+	flash_set_status(dev, reg1);
+
+	spi_flash_reg_to_protect(reg1, 0, &addr_prot_start, &addr_prot_length);
+
+	return EC_SUCCESS;
+}
+
+static int flash_check_prot_reg(const struct device *dev, unsigned int offset,
+				unsigned int bytes)
+{
+	unsigned int start;
+	unsigned int len;
+	uint8_t sr1;
+	int rv = EC_SUCCESS;
+
+	/*
+	 * If WP# is active and ec doesn't protect the status registers of
+	 * internal spi-flash, protect it now.
+	 */
+	flash_protect_int_flash(dev, write_protect_is_asserted());
+
+	/* Invalid value */
+	if (offset + bytes > CONFIG_FLASH_SIZE_BYTES)
+		return EC_ERROR_INVAL;
+
+	/* Compute current protect range */
+	flash_get_status(dev, &sr1);
+	rv = spi_flash_reg_to_protect(sr1, 0, &start, &len);
+	if (rv)
+		return rv;
+
+	/* Check if ranges overlap */
+	if (MAX(start, offset) < MIN(start + len, offset + bytes))
+		return EC_ERROR_ACCESS_DENIED;
+
+	return EC_SUCCESS;
+}
+
+static int flash_write_prot_reg(const struct device *dev, unsigned int offset,
+				unsigned int bytes, int hw_protect)
+{
+	int rv;
+	uint8_t sr1;
+
+	/* Invalid values */
+	if (offset + bytes > CONFIG_FLASH_SIZE_BYTES)
+		return EC_ERROR_INVAL;
+
+	/* Compute desired protect range */
+	flash_get_status(dev, &sr1);
+	rv = spi_flash_protect_to_reg(offset, bytes, &sr1, 0);
+	if (rv)
+		return rv;
+
+	if (hw_protect)
+		sr1 |= SPI_FLASH_SR1_SRP0;
+
+	return flash_set_status_for_prot(dev, sr1);
+}
+
+static int flash_check_prot_range(unsigned int offset, unsigned int bytes)
+{
+	/* Invalid value */
+	if (offset + bytes > CONFIG_FLASH_SIZE_BYTES)
+		return EC_ERROR_INVAL;
+
+	/* Check if ranges overlap */
+	if (MAX(addr_prot_start, offset) <
+	    MIN(addr_prot_start + addr_prot_length, offset + bytes)) {
+		return EC_ERROR_ACCESS_DENIED;
+	}
+
+	return EC_SUCCESS;
+}
+
+/* cros ec flash api functions */
+static int cros_flash_xec_init(const struct device *dev)
+{
+	/* Initialize UMA to unlocked */
+	flash_uma_lock(dev, 0);
+
+	/*
+	 * Protect status registers of internal spi-flash if WP# is active
+	 * during ec initialization.
+	 */
+	flash_protect_int_flash(dev, write_protect_is_asserted());
+
+	return 0;
+}
+
+static int cros_flash_xec_write(const struct device *dev, int offset, int size,
+				const char *src_data)
+{
+	int ret = 0;
+	struct cros_flash_xec_data *data = dev->data;
+
+	/* check protection */
+	if (all_protected)
+		return EC_ERROR_ACCESS_DENIED;
+
+	/* check protection */
+	if (flash_check_prot_range(offset, size))
+		return EC_ERROR_ACCESS_DENIED;
+
+	/* Invalid data pointer? */
+	if (src_data == 0)
+		return -EINVAL;
+
+	ret = flash_write(data->flash_dev, offset, src_data, size);
+
+	return ret;
+}
+
+static int cros_flash_xec_erase(const struct device *dev, int offset, int size)
+{
+	int ret = 0;
+	struct cros_flash_xec_data *data = dev->data;
+
+	/* check protection */
+	if (all_protected)
+		return EC_ERROR_ACCESS_DENIED;
+
+	/* check protection */
+	if (flash_check_prot_range(offset, size))
+		return EC_ERROR_ACCESS_DENIED;
+
+	/* address must be aligned to erase size */
+	if ((offset % CONFIG_FLASH_ERASE_SIZE) != 0)
+		return -EINVAL;
+
+	/* Erase size must be a non-zero multiple of sectors */
+	if ((size == 0) || (size % CONFIG_FLASH_ERASE_SIZE) != 0)
+		return -EINVAL;
+
+	ret = flash_erase(data->flash_dev, offset, size);
+
+	return ret;
+}
+
+static int cros_flash_xec_get_protect(const struct device *dev, int bank)
+{
+	uint32_t addr = bank * CONFIG_FLASH_BANK_SIZE;
+
+	return flash_check_prot_reg(dev, addr, CONFIG_FLASH_BANK_SIZE);
+}
+
+static uint32_t cros_flash_xec_get_protect_flags(const struct device *dev)
+{
+	uint32_t flags = 0;
+	int rv;
+	uint8_t sr1;
+	unsigned int start, len;
+
+	/* Check if WP region is protected in status register */
+	rv = flash_check_prot_reg(dev, WP_BANK_OFFSET * CONFIG_FLASH_BANK_SIZE,
+				  WP_BANK_COUNT * CONFIG_FLASH_BANK_SIZE);
+	if (rv == EC_ERROR_ACCESS_DENIED)
+		flags |= EC_FLASH_PROTECT_RO_AT_BOOT;
+	else if (rv)
+		return EC_FLASH_PROTECT_ERROR_UNKNOWN;
+
+	/*
+	 * If the status register protects a range, but SRP0 is not set,
+	 * or Quad Enable (QE) is set,
+	 * flags should indicate EC_FLASH_PROTECT_ERROR_INCONSISTENT.
+	 */
+	flash_get_status(dev, &sr1);
+	rv = spi_flash_reg_to_protect(sr1, 0, &start, &len);
+	if (rv)
+		return EC_FLASH_PROTECT_ERROR_UNKNOWN;
+
+	if (len && (!(sr1 & SPI_FLASH_SR1_SRP0)))
+		flags |= EC_FLASH_PROTECT_ERROR_INCONSISTENT;
+
+	/* Read all-protected state from our shadow copy */
+	if (all_protected)
+		flags |= EC_FLASH_PROTECT_ALL_NOW;
+
+	return flags;
+}
+
+static int cros_flash_xec_protect_at_boot(const struct device *dev,
+					  uint32_t new_flags)
+{
+	int ret;
+
+	if ((new_flags & (EC_FLASH_PROTECT_RO_AT_BOOT |
+			  EC_FLASH_PROTECT_ALL_AT_BOOT)) == 0) {
+		/* Clear protection bits in status register */
+		return flash_set_status_for_prot(dev, 0);
+	}
+
+	ret = flash_write_prot_reg(dev, CONFIG_WP_STORAGE_OFF,
+				   CONFIG_WP_STORAGE_SIZE, 1);
+
+	/*
+	 * Set UMA_LOCK bit for locking all UMA transaction.
+	 * But we still can read directly from flash mapping address
+	 */
+	if (new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT)
+		flash_uma_lock(dev, 1);
+
+	return ret;
+}
+
+static int cros_flash_xec_protect_now(const struct device *dev, int all)
+{
+	if (all) {
+		/*
+		 * Set UMA_LOCK bit for locking all UMA transaction.
+		 * But we still can read directly from flash mapping address
+		 */
+		flash_uma_lock(dev, 1);
+	} else {
+		/* TODO: Implement RO "now" protection */
+	}
+
+	return EC_SUCCESS;
+}
+
+static int cros_flash_xec_get_jedec_id(const struct device *dev,
+				       uint8_t *manufacturer, uint16_t *device)
+{
+	int ret;
+	uint8_t jedec_id[3];
+	struct cros_flash_xec_data *data = dev->data;
+
+	/* Lock physical flash operations */
+	crec_flash_lock_mapped_storage(1);
+
+	ret = flash_read_jedec_id(data->flash_dev, jedec_id);
+	if (ret == 0) {
+		*manufacturer = jedec_id[0];
+		*device = (jedec_id[1] << 8) | jedec_id[2];
+	}
+
+	/* Unlock physical flash operations */
+	crec_flash_lock_mapped_storage(0);
+
+	return ret;
+}
+
+static int cros_flash_xec_get_status(const struct device *dev, uint8_t *sr1,
+				     uint8_t *sr2)
+{
+	flash_get_status(dev, sr1);
+	*sr2 = 0;
+
+	return EC_SUCCESS;
+}
+
+/* cros ec flash driver registration */
+static const struct cros_flash_driver_api cros_flash_xec_driver_api = {
+	.init = cros_flash_xec_init,
+	.physical_write = cros_flash_xec_write,
+	.physical_erase = cros_flash_xec_erase,
+	.physical_get_protect = cros_flash_xec_get_protect,
+	.physical_get_protect_flags = cros_flash_xec_get_protect_flags,
+	.physical_protect_at_boot = cros_flash_xec_protect_at_boot,
+	.physical_protect_now = cros_flash_xec_protect_now,
+	.physical_get_jedec_id = cros_flash_xec_get_jedec_id,
+	.physical_get_status = cros_flash_xec_get_status,
+};
+
+static int flash_xec_init(const struct device *dev)
+{
+	struct cros_flash_xec_data *data = dev->data;
+
+	data->flash_dev = DEVICE_DT_GET(FLASH_DEV);
+	if (!device_is_ready(data->flash_dev)) {
+		LOG_ERR("%s device not ready", data->flash_dev->name);
+		return -ENODEV;
+	}
+
+	data->spi_ctrl_dev = DEVICE_DT_GET(SPI_CONTROLLER_DEV);
+	if (!device_is_ready(data->spi_ctrl_dev)) {
+		LOG_ERR("%s device not ready", data->spi_ctrl_dev->name);
+		return -ENODEV;
+	}
+
+	return EC_SUCCESS;
+}
+
+#if CONFIG_CROS_FLASH_XEC_INIT_PRIORITY <= CONFIG_SPI_NOR_INIT_PRIORITY
+#error "CONFIG_CROS_FLASH_XEC_INIT_PRIORITY must be greater than" \
+	"CONFIG_SPI_NOR_INIT_PRIORITY."
+#endif
+static struct cros_flash_xec_data cros_flash_data;
+DEVICE_DT_INST_DEFINE(0, flash_xec_init, NULL, &cros_flash_data, NULL,
+		      POST_KERNEL, CONFIG_CROS_FLASH_XEC_INIT_PRIORITY,
+		      &cros_flash_xec_driver_api);
diff --git a/zephyr/drivers/cros_kb_raw/CMakeLists.txt b/zephyr/drivers/cros_kb_raw/CMakeLists.txt
new file mode 100644
index 0000000000..680b15342e
--- /dev/null
+++ b/zephyr/drivers/cros_kb_raw/CMakeLists.txt
@@ -0,0 +1,7 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+zephyr_library_sources_ifdef(CONFIG_CROS_KB_RAW_NPCX	cros_kb_raw_npcx.c)
+zephyr_library_sources_ifdef(CONFIG_CROS_KB_RAW_ITE	cros_kb_raw_ite.c)
+zephyr_library_sources_ifdef(CONFIG_CROS_KB_RAW_XEC	cros_kb_raw_xec.c)
diff --git a/zephyr/drivers/cros_kb_raw/Kconfig b/zephyr/drivers/cros_kb_raw/Kconfig
new file mode 100644
index 0000000000..1e10f38bbe
--- /dev/null
+++ b/zephyr/drivers/cros_kb_raw/Kconfig
@@ -0,0 +1,48 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if PLATFORM_EC_KEYBOARD
+
+menuconfig CROS_KB_RAW_NPCX
+	bool "Nuvoton NPCX raw-keyboard-scan driver for the Zephyr shim"
+	default y
+	depends on DT_HAS_NUVOTON_NPCX_CROS_KB_RAW_ENABLED
+	help
+	  This option enables a driver for providing raw access to the
+	  keyboard-scan peripheral in the chip. This is used instead of the
+	  kscan interface so we can continue to use most of the existing
+	  keyboard-scanning code in ECOS.
+
+if CROS_KB_RAW_NPCX
+
+config CROS_KB_RAW_NPCX_KSO_HIGH_DRIVE
+	bool "Enable quasi-bidirectional buffers for KSO pins"
+	help
+	  This option enables quasi-bidirectional buffers for KSO pins. The
+	  low-impedance high drive is active when ec changes the output data
+	  buffers from 0 to 1, thereby reducing the low-to-high transition time.
+
+endif # CROS_KB_RAW_NPCX
+
+config CROS_KB_RAW_ITE
+	bool "ITE raw-keyboard-scan driver for the Zephyr shim"
+	default y
+	depends on DT_HAS_ITE_IT8XXX2_CROS_KB_RAW_ENABLED
+	help
+	  This option enables a driver for providing raw access to the
+	  keyboard-scan peripheral in the chip. This is used instead of the
+	  kscan interface so we can continue to use most of the existing
+	  keyboard-scanning code in ECOS.
+
+menuconfig CROS_KB_RAW_XEC
+	bool "Microchip raw-keyboard-scan driver for the Zephyr shim"
+	default y
+	depends on DT_HAS_MICROCHIP_XEC_CROS_KB_RAW_ENABLED
+	help
+	  This option enables a driver for providing raw access to the
+	  keyboard-scan peripheral in the chip. This is used instead of the
+	  kscan interface so we can continue to use most of the existing
+	  keyboard-scanning code in ECOS.
+
+endif # PLATFORM_EC_KEYBOARD
diff --git a/zephyr/drivers/cros_kb_raw/cros_kb_raw_ite.c b/zephyr/drivers/cros_kb_raw/cros_kb_raw_ite.c
new file mode 100644
index 0000000000..7de488b059
--- /dev/null
+++ b/zephyr/drivers/cros_kb_raw/cros_kb_raw_ite.c
@@ -0,0 +1,289 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define DT_DRV_COMPAT ite_it8xxx2_cros_kb_raw
+
+#include "ec_tasks.h"
+#include "keyboard_raw.h"
+#include "task.h"
+
+#include <assert.h>
+
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/interrupt_controller/wuc_ite_it8xxx2.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/dt-bindings/interrupt-controller/it8xxx2-wuc.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+
+#include <drivers/cros_kb_raw.h>
+#include <soc.h>
+#include <soc/ite_it8xxx2/reg_def_cros.h>
+#include <soc_dt.h>
+LOG_MODULE_REGISTER(cros_kb_raw, LOG_LEVEL_ERR);
+
+#define KEYBOARD_KSI_PIN_COUNT IT8XXX2_DT_INST_WUCCTRL_LEN(0)
+#define KSOH_PIN_MASK (((1 << (KEYBOARD_COLS_MAX - 8)) - 1) & 0xff)
+
+/* Device config */
+struct cros_kb_raw_wuc_map_cfg {
+	/* WUC control device structure */
+	const struct device *wucs;
+	/* WUC pin mask */
+	uint8_t mask;
+};
+
+struct cros_kb_raw_ite_config {
+	/* keyboard scan controller base address */
+	struct kscan_it8xxx2_regs *base;
+	/* Keyboard scan input (KSI) wake-up irq */
+	int irq;
+	/* KSI[7:0] wake-up input source configuration list */
+	const struct cros_kb_raw_wuc_map_cfg *wuc_map_list;
+	/* KSI/KSO keyboard scan alternate configuration */
+	const struct pinctrl_dev_config *pcfg;
+};
+
+struct cros_kb_raw_ite_data {
+	/* KSI[7:0] wake-up interrupt status mask */
+	uint8_t ksi_pin_mask;
+};
+
+static int kb_raw_ite_init(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	/* Clock default is on */
+	return 0;
+}
+
+/* Cros ec keyboard raw api functions */
+static int cros_kb_raw_ite_enable_interrupt(const struct device *dev,
+					    int enable)
+{
+	const struct cros_kb_raw_ite_config *config = dev->config;
+	struct cros_kb_raw_ite_data *data = dev->data;
+
+	if (enable) {
+		/*
+		 * W/C wakeup interrupt status of KSI[7:0] pins
+		 *
+		 * NOTE: We want to clear the status as soon as possible,
+		 *       so clear KSI[7:0] pins at a time.
+		 */
+		it8xxx2_wuc_clear_status(config->wuc_map_list[0].wucs,
+					 data->ksi_pin_mask);
+		ite_intc_isr_clear(config->irq);
+		irq_enable(config->irq);
+	} else {
+		irq_disable(config->irq);
+	}
+
+	return 0;
+}
+
+static int cros_kb_raw_ite_read_row(const struct device *dev)
+{
+	const struct cros_kb_raw_ite_config *config = dev->config;
+	struct kscan_it8xxx2_regs *const inst = config->base;
+
+	/* Bits are active-low, so invert returned levels */
+	return ((inst->KBS_KSI) ^ 0xff);
+}
+
+static int cros_kb_raw_ite_drive_column(const struct device *dev, int col)
+{
+	int mask;
+	unsigned int key;
+	const struct cros_kb_raw_ite_config *config = dev->config;
+	struct kscan_it8xxx2_regs *const inst = config->base;
+
+	/* Tri-state all outputs */
+	if (col == KEYBOARD_COLUMN_NONE)
+		mask = 0xffff;
+	/* Assert all outputs */
+	else if (col == KEYBOARD_COLUMN_ALL)
+		mask = 0;
+	/* Assert a single output */
+	else
+		mask = 0xffff ^ BIT(col);
+#ifdef CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED
+	/* KSO[2] is inverted. */
+	mask ^= BIT(2);
+#endif
+	inst->KBS_KSOL = mask & 0xff;
+	/* critical section with interrupts off */
+	key = irq_lock();
+	/*
+	 * Because IT8XXX2_KBS_KSOH1 register is shared by keyboard scan
+	 * out and GPIO output mode, so we don't drive all KSOH pins
+	 * here (this depends on how many keyboard matrix output pin
+	 * we are using).
+	 */
+	inst->KBS_KSOH1 = ((inst->KBS_KSOH1) & ~KSOH_PIN_MASK) |
+			  ((mask >> 8) & KSOH_PIN_MASK);
+	/* restore interrupts */
+	irq_unlock(key);
+
+	return 0;
+}
+
+#ifdef CONFIG_PLATFORM_EC_KEYBOARD_FACTORY_TEST
+static int cros_kb_raw_ite_config_alt(const struct device *dev, bool enable)
+{
+	const struct cros_kb_raw_ite_config *config = dev->config;
+	int status = 0;
+
+	if (enable) {
+		/* Set KSI/KSO pins of cros_kb_raw node to kbs mode */
+		status = pinctrl_apply_state(config->pcfg,
+					     PINCTRL_STATE_DEFAULT);
+		if (status < 0) {
+			LOG_ERR("Failed to enable KSI and KSO kbs mode");
+			return status;
+		}
+	} else {
+		/* Set KSI/KSO pins of cros_kb_raw node to gpio mode */
+		status = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_SLEEP);
+		if (status < 0) {
+			LOG_ERR("Failed to enable KSI and KSO gpio mode");
+			return status;
+		}
+	}
+
+	return 0;
+}
+#endif
+
+static void cros_kb_raw_ite_ksi_isr(const struct device *dev)
+{
+	const struct cros_kb_raw_ite_config *config = dev->config;
+	struct cros_kb_raw_ite_data *data = dev->data;
+
+	/*
+	 * We clear IT8XXX2_IRQ_WKINTC irq status in
+	 * ite_intc_irq_handler(), after interrupt was fired.
+	 */
+	/*
+	 * W/C wakeup interrupt status of KSI[7:0] pins
+	 *
+	 * NOTE: We want to clear the status as soon as possible,
+	 *       so clear KSI[7:0] pins at a time.
+	 */
+	it8xxx2_wuc_clear_status(config->wuc_map_list[0].wucs,
+				 data->ksi_pin_mask);
+
+	/* Wake-up keyboard scan task */
+	task_wake(TASK_ID_KEYSCAN);
+}
+
+static int cros_kb_raw_ite_init(const struct device *dev)
+{
+	unsigned int key;
+	const struct cros_kb_raw_ite_config *config = dev->config;
+	struct cros_kb_raw_ite_data *data = dev->data;
+	struct kscan_it8xxx2_regs *const inst = config->base;
+	int status;
+
+	/* Ensure top-level interrupt is disabled */
+	cros_kb_raw_ite_enable_interrupt(dev, 0);
+
+	/*
+	 * Enable the internal pull-up and kbs mode of the KSI[7:0] pins.
+	 * Enable the internal pull-up and kbs mode of the KSO[15:0] pins.
+	 * Enable the open-drain mode of the KSO[17:0] pins.
+	 */
+	status = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
+	if (status < 0) {
+		LOG_ERR("Failed to configure KSI[7:0] and KSO[15:0] pins");
+		return status;
+	}
+
+#ifdef CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED
+	/* KSO[2] output high, others output low. */
+	inst->KBS_KSOL = BIT(2);
+	/* Enable KSO2's push-pull */
+	inst->KBS_KSOLGCTRL |= IT8XXX2_KBS_KSO2GCTRL;
+	inst->KBS_KSOLGOEN |= IT8XXX2_KBS_KSO2GOEN;
+#else
+	/* KSO[7:0] pins output low. */
+	inst->KBS_KSOL = 0x00;
+#endif
+	/* critical section with interrupts off */
+	key = irq_lock();
+	/*
+	 * KSO[COLS_MAX:8] pins low.
+	 * NOTE: KSO[15:8] pins can part be enabled for keyboard function and
+	 *       rest be configured as GPIO output mode. In this case that we
+	 *       disable the ISR in critical section to avoid race condition.
+	 */
+	inst->KBS_KSOH1 &= ~KSOH_PIN_MASK;
+	/* restore interrupts */
+	irq_unlock(key);
+
+	for (int i = 0; i < KEYBOARD_KSI_PIN_COUNT; i++) {
+		/* Select wakeup interrupt falling-edge triggered of KSI[7:0] */
+		it8xxx2_wuc_set_polarity(config->wuc_map_list[i].wucs,
+					 config->wuc_map_list[i].mask,
+					 WUC_TYPE_EDGE_FALLING);
+		/* W/C wakeup interrupt status of KSI[7:0] pins */
+		it8xxx2_wuc_clear_status(config->wuc_map_list[i].wucs,
+					 config->wuc_map_list[i].mask);
+		/* Enable wakeup interrupt of KSI[7:0] pins */
+		it8xxx2_wuc_enable(config->wuc_map_list[i].wucs,
+				   config->wuc_map_list[i].mask);
+
+		/*
+		 * We want to clear KSI[7:0] pins status at a time when wakeup
+		 * interrupt fire, so gather the KSI[7:0] pin mask value here.
+		 */
+		if (IS_ENABLED(CONFIG_LOG)) {
+			if (config->wuc_map_list[i].wucs !=
+			    config->wuc_map_list[0].wucs) {
+				LOG_ERR("KSI%d isn't in the same wuc node!", i);
+			}
+		}
+		data->ksi_pin_mask |= config->wuc_map_list[i].mask;
+	}
+
+	/* W/C interrupt status of KSI[7:0] pins */
+	ite_intc_isr_clear(config->irq);
+
+	irq_connect_dynamic(config->irq, 0,
+			    (void (*)(const void *))cros_kb_raw_ite_ksi_isr,
+			    (const void *)dev, 0);
+
+	return 0;
+}
+
+static const struct cros_kb_raw_driver_api cros_kb_raw_ite_driver_api = {
+	.init = cros_kb_raw_ite_init,
+	.drive_colum = cros_kb_raw_ite_drive_column,
+	.read_rows = cros_kb_raw_ite_read_row,
+	.enable_interrupt = cros_kb_raw_ite_enable_interrupt,
+#ifdef CONFIG_PLATFORM_EC_KEYBOARD_FACTORY_TEST
+	.config_alt = cros_kb_raw_ite_config_alt,
+#endif
+};
+static const struct cros_kb_raw_wuc_map_cfg
+	cros_kb_raw_wuc_0[IT8XXX2_DT_INST_WUCCTRL_LEN(0)] =
+		IT8XXX2_DT_WUC_ITEMS_LIST(0);
+
+PINCTRL_DT_INST_DEFINE(0);
+
+static const struct cros_kb_raw_ite_config cros_kb_raw_cfg = {
+	.base = (struct kscan_it8xxx2_regs *)DT_INST_REG_ADDR(0),
+	.irq = DT_INST_IRQN(0),
+	.wuc_map_list = cros_kb_raw_wuc_0,
+	.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
+};
+
+static struct cros_kb_raw_ite_data cros_kb_raw_data;
+
+DEVICE_DT_INST_DEFINE(0, kb_raw_ite_init, NULL, &cros_kb_raw_data,
+		      &cros_kb_raw_cfg, PRE_KERNEL_1,
+		      CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
+		      &cros_kb_raw_ite_driver_api);
diff --git a/zephyr/drivers/cros_kb_raw/cros_kb_raw_npcx.c b/zephyr/drivers/cros_kb_raw/cros_kb_raw_npcx.c
new file mode 100644
index 0000000000..1974883961
--- /dev/null
+++ b/zephyr/drivers/cros_kb_raw/cros_kb_raw_npcx.c
@@ -0,0 +1,269 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * TODO(b/272518464): Work around coreboot GCC preprocessor bug.
+ * #line marks the *next* line, so it is off by one.
+ */
+#line 11
+
+#define DT_DRV_COMPAT nuvoton_npcx_cros_kb_raw
+
+#include "ec_tasks.h"
+#include "keyboard_raw.h"
+#include "soc_miwu.h"
+#include "task.h"
+
+#include <assert.h>
+
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/dt-bindings/clock/npcx_clock.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+
+#include <drivers/cros_kb_raw.h>
+#include <soc.h>
+#include <soc/nuvoton_npcx/reg_def_cros.h>
+LOG_MODULE_REGISTER(cros_kb_raw, LOG_LEVEL_ERR);
+
+#ifdef CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED
+#if !DT_NODE_EXISTS(KBD_KSO2_NODE)
+#error gpio_kbd_kso2 alias has to point to the keyboard column 2 output pin.
+#endif
+#endif /* CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED */
+
+#define NPCX_MAX_KEY_COLS 18 /* Maximum rows of keyboard matrix */
+#define NPCX_MAX_KEY_ROWS 8 /* Maximum columns of keyboard matrix */
+#define NPCX_KB_ROW_MASK (BIT(NPCX_MAX_KEY_ROWS) - 1)
+
+/* Device config */
+struct cros_kb_raw_npcx_config {
+	/* keyboard scan controller base address */
+	uintptr_t base;
+	/* clock configuration */
+	struct npcx_clk_cfg clk_cfg;
+	/* Pin control configuration */
+	const struct pinctrl_dev_config *pcfg;
+	/* Keyboard scan input (KSI) wake-up irq */
+	int irq;
+	/* Size of keyboard inputs-wui mapping array */
+	int wui_size;
+	/* Mapping table between keyboard inputs and wui */
+	struct npcx_wui wui_maps[];
+};
+
+/* Driver convenience defines */
+#define DRV_CONFIG(dev) ((const struct cros_kb_raw_npcx_config *)(dev)->config)
+#define HAL_INSTANCE(dev) (struct kbs_reg *)(DRV_CONFIG(dev)->base)
+
+/* Keyboard Scan local functions */
+static struct miwu_callback ksi_callback[NPCX_MAX_KEY_ROWS];
+
+static void kb_raw_npcx_init_ksi_wui_callback(
+	const struct device *dev, struct miwu_callback *callback,
+	const struct npcx_wui *wui, miwu_dev_callback_handler_t handler)
+{
+	/* KSI signal which has no wake-up input source */
+	if (wui->table == NPCX_MIWU_TABLE_NONE)
+		return;
+
+	/* Install callback function */
+	npcx_miwu_init_dev_callback(callback, wui, handler, dev);
+	npcx_miwu_manage_callback(callback, 1);
+
+	/* Configure MIWU setting and enable its interrupt */
+	npcx_miwu_interrupt_configure(wui, NPCX_MIWU_MODE_EDGE,
+				      NPCX_MIWU_TRIG_BOTH);
+	npcx_miwu_irq_enable(wui);
+}
+
+static int kb_raw_npcx_init(const struct device *dev)
+{
+	const struct cros_kb_raw_npcx_config *const config = DRV_CONFIG(dev);
+	const struct device *clk_dev = DEVICE_DT_GET(NPCX_CLK_CTRL_NODE);
+	int ret;
+
+	/* Turn on device clock first and get source clock freq. */
+	ret = clock_control_on(clk_dev,
+			       (clock_control_subsys_t *)&config->clk_cfg);
+	if (ret < 0) {
+		LOG_ERR("Turn on KSCAN clock fail %d", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+/* Cros ec keyboard raw api functions */
+static int cros_kb_raw_npcx_enable_interrupt(const struct device *dev,
+					     int enable)
+{
+	const struct cros_kb_raw_npcx_config *const config = DRV_CONFIG(dev);
+
+	if (enable)
+		irq_enable(config->irq);
+	else
+		irq_disable(config->irq);
+
+	return 0;
+}
+
+static int cros_kb_raw_npcx_read_row(const struct device *dev)
+{
+	struct kbs_reg *const inst = HAL_INSTANCE(dev);
+	int val;
+
+	val = inst->KBSIN;
+	LOG_DBG("rows raw %02x", val);
+
+	/* 1 means key pressed, otherwise means key released. */
+	return (~val & NPCX_KB_ROW_MASK);
+}
+
+static int cros_kb_raw_npcx_drive_column(const struct device *dev, int col)
+{
+	struct kbs_reg *const inst = HAL_INSTANCE(dev);
+
+	/*
+	 * Nuvoton 'Keyboard Scan' module supports 18x8 matrix
+	 * It also support automatic scan functionality.
+	 */
+	uint32_t mask, col_out;
+
+	/* Add support for CONFIG_KEYBOARD_KSO_BASE shifting */
+	col_out = col + CONFIG_KEYBOARD_KSO_BASE;
+
+	/* Drive all lines to high. ie. Key detection is disabled. */
+	if (col == KEYBOARD_COLUMN_NONE) {
+		mask = ~0;
+		/* Set logical level high on COL2 */
+		cros_kb_raw_set_col2(1);
+	}
+	/* Drive all lines to low for detection any key press */
+	else if (col == KEYBOARD_COLUMN_ALL) {
+		mask = ~(BIT(keyboard_cols) - 1);
+		/* Set logical level low on COL2 */
+		cros_kb_raw_set_col2(0);
+	}
+	/* Drive one line to low for determining which key's state changed. */
+	else {
+		if (col == 2) {
+			/* Set logical level low on COL2 */
+			cros_kb_raw_set_col2(0);
+		} else {
+			/* Set logical level high on COL2 */
+			cros_kb_raw_set_col2(1);
+		}
+		mask = ~BIT(col_out);
+	}
+
+	/* Set KBSOUT */
+	inst->KBSOUT0 = (mask & 0xFFFF);
+	inst->KBSOUT1 = ((mask >> 16) & 0x03);
+
+	return 0;
+}
+
+static void cros_kb_raw_npcx_ksi_isr(const struct device *dev,
+				     struct npcx_wui *wui)
+{
+	ARG_UNUSED(dev);
+	ARG_UNUSED(wui);
+
+	LOG_DBG("%s: KSI%d is changed", __func__, wui->bit);
+	/* Wake-up keyboard scan task */
+	task_wake(TASK_ID_KEYSCAN);
+}
+
+static int cros_kb_raw_npcx_init(const struct device *dev)
+{
+	const struct cros_kb_raw_npcx_config *const config = DRV_CONFIG(dev);
+	struct kbs_reg *const inst = HAL_INSTANCE(dev);
+	int ret;
+
+	/* Pull-up KBSIN0-7 internally */
+	inst->KBSINPU = 0xFF;
+
+	/*
+	 * Keyboard Scan Control Register
+	 *
+	 * [6:7] - KBHDRV KBSOUTn signals output buffers are open-drain.
+	 * [3] - KBSINC   Auto-increment of Buffer Data register is disabled
+	 * [2] - KBSIEN   Interrupt of Auto-Scan is disabled
+	 * [1] - KBSMODE  Key detection mechanism is implemented by firmware
+	 * [0] - START    Write 0 to this field is not affected
+	 */
+	inst->KBSCTL = 0x00;
+
+	/*
+	 * Select quasi-bidirectional buffers for KSO pins. It reduces the
+	 * low-to-high transition time. This feature only supports in npcx7.
+	 */
+	if (IS_ENABLED(CONFIG_CROS_KB_RAW_NPCX_KSO_HIGH_DRIVE)) {
+		SET_FIELD(inst->KBSCTL, NPCX_KBSCTL_KBHDRV_FIELD, 0x01);
+	}
+
+	/* Configure pin control for kscan device */
+	ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
+	if (ret < 0) {
+		LOG_ERR("KB Raw pinctrl setup failed (%d)", ret);
+		return ret;
+	}
+
+	/* Drive all column lines to low for detection any key press */
+	cros_kb_raw_npcx_drive_column(dev, KEYBOARD_COLUMN_ALL);
+
+	/* Configure wake-up input and callback for keyboard input signal */
+	for (int i = 0; i < ARRAY_SIZE(ksi_callback); i++)
+		kb_raw_npcx_init_ksi_wui_callback(dev, &ksi_callback[i],
+						  &config->wui_maps[i],
+						  cros_kb_raw_npcx_ksi_isr);
+
+	return 0;
+}
+
+#ifdef CONFIG_PLATFORM_EC_KEYBOARD_FACTORY_TEST
+static int cros_kb_raw_npcx_config_alt(const struct device *dev, bool enable)
+{
+	const struct cros_kb_raw_npcx_config *const config = DRV_CONFIG(dev);
+	uint8_t id = enable ? PINCTRL_STATE_DEFAULT : PINCTRL_STATE_SLEEP;
+
+	return pinctrl_apply_state(config->pcfg, id);
+}
+#endif
+
+static const struct cros_kb_raw_driver_api cros_kb_raw_npcx_driver_api = {
+	.init = cros_kb_raw_npcx_init,
+	.drive_colum = cros_kb_raw_npcx_drive_column,
+	.read_rows = cros_kb_raw_npcx_read_row,
+	.enable_interrupt = cros_kb_raw_npcx_enable_interrupt,
+#ifdef CONFIG_PLATFORM_EC_KEYBOARD_FACTORY_TEST
+	.config_alt = cros_kb_raw_npcx_config_alt,
+#endif
+};
+
+PINCTRL_DT_INST_DEFINE(0);
+
+static const struct cros_kb_raw_npcx_config cros_kb_raw_cfg = {
+	.base = DT_INST_REG_ADDR(0),
+	.clk_cfg = NPCX_DT_CLK_CFG_ITEM(0),
+	.irq = DT_INST_IRQN(0),
+	.wui_size = NPCX_DT_WUI_ITEMS_LEN(0),
+	.wui_maps = NPCX_DT_WUI_ITEMS_LIST(0),
+	.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
+};
+
+/* Verify there's exactly 1 enabled cros,kb-raw-npcx node. */
+BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1);
+DEVICE_DT_INST_DEFINE(0, kb_raw_npcx_init, NULL, NULL, &cros_kb_raw_cfg,
+		      PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
+		      &cros_kb_raw_npcx_driver_api);
+
+/* KBS register structure check */
+NPCX_REG_SIZE_CHECK(kbs_reg, 0x010);
+NPCX_REG_OFFSET_CHECK(kbs_reg, KBSIN, 0x004);
+NPCX_REG_OFFSET_CHECK(kbs_reg, KBSOUT0, 0x006);
+NPCX_REG_OFFSET_CHECK(kbs_reg, KBS_BUF_INDX, 0x00a);
diff --git a/zephyr/drivers/cros_kb_raw/cros_kb_raw_xec.c b/zephyr/drivers/cros_kb_raw/cros_kb_raw_xec.c
new file mode 100644
index 0000000000..83d5cdc54f
--- /dev/null
+++ b/zephyr/drivers/cros_kb_raw/cros_kb_raw_xec.c
@@ -0,0 +1,202 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define DT_DRV_COMPAT microchip_xec_cros_kb_raw
+
+#include "ec_tasks.h"
+#include "keyboard_raw.h"
+#include "task.h"
+
+#include <assert.h>
+
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/drivers/interrupt_controller/intc_mchp_xec_ecia.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/logging/log.h>
+
+#include <drivers/cros_kb_raw.h>
+#include <soc.h>
+#include <soc/microchip_xec/reg_def_cros.h>
+LOG_MODULE_REGISTER(cros_kb_raw, LOG_LEVEL_ERR);
+
+#ifdef CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED
+#if !DT_NODE_EXISTS(KBD_KSO2_NODE)
+#error gpio_kbd_kso2 alias has to point to the keyboard column 2 output pin.
+#endif
+#endif /* CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED */
+
+#define XEC_MAX_KEY_COLS 18 /* Maximum rows of keyboard matrix */
+#define XEC_MAX_KEY_ROWS 8 /* Maximum columns of keyboard matrix */
+#define XEC_KB_ROW_MASK (BIT(XEC_MAX_KEY_ROWS) - 1)
+
+/* Device config */
+struct cros_kb_raw_xec_config {
+	/* keyboard scan controller base address */
+	uintptr_t base;
+	/* Keyboard scan input (KSI) wake-up irq */
+	int irq;
+	const struct pinctrl_dev_config *pcfg;
+};
+
+static int kb_raw_xec_init(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	/* Clock default is on */
+	return 0;
+}
+
+/* Clear keyboard source bits: hw status, block source and NVIC pending */
+static void kb_raw_xec_clr_src(const struct device *dev)
+{
+	struct cros_kb_raw_xec_config const *cfg = dev->config;
+	struct kscan_regs *const inst = (struct kscan_regs *)cfg->base;
+
+	inst->KSI_STS = 0xff;
+	mchp_soc_ecia_girq_src_clr(MCHP_GIRQ21_ID, MCHP_KEYSCAN_GIRQ_POS);
+	mchp_xec_ecia_nvic_clr_pend(MCHP_KEYSCAN_GIRQ_NVIC_DIRECT);
+}
+
+/* Cros ec keyboard raw api functions */
+static int cros_kb_raw_xec_enable_interrupt(const struct device *dev,
+					    int enable)
+{
+	struct cros_kb_raw_xec_config const *cfg = dev->config;
+
+	if (enable) {
+		kb_raw_xec_clr_src(dev);
+		/* Enable Kscan NVIC interrupt */
+		irq_enable(cfg->irq);
+	} else {
+		/* Disable Kscan NVIC interrupt */
+		irq_disable(cfg->irq);
+	}
+
+	return 0;
+}
+
+static int cros_kb_raw_xec_read_row(const struct device *dev)
+{
+	struct cros_kb_raw_xec_config const *cfg = dev->config;
+	struct kscan_regs *const inst = (struct kscan_regs *)cfg->base;
+	int val;
+
+	val = inst->KSI_IN;
+	LOG_DBG("rows raw %02x", val);
+
+	/* 1 means key pressed, otherwise means key released. */
+	return (~val & 0xFF);
+}
+
+static int cros_kb_raw_xec_drive_column(const struct device *dev, int col)
+{
+	struct cros_kb_raw_xec_config const *cfg = dev->config;
+	struct kscan_regs *const inst = (struct kscan_regs *)cfg->base;
+
+	/* Drive all lines to high. i.e. Key detection is disabled. */
+	if (col == KEYBOARD_COLUMN_NONE) {
+		inst->KSO_SEL = MCHP_KSCAN_KSO_EN;
+		/* Set logical level high on COL2 */
+		cros_kb_raw_set_col2(1);
+	}
+	/* Drive all lines to low for detection any key press */
+	else if (col == KEYBOARD_COLUMN_ALL) {
+		mchp_soc_ecia_girq_src_dis(MCHP_GIRQ21_ID,
+					   MCHP_KEYSCAN_GIRQ_POS);
+		inst->KSO_SEL = MCHP_KSCAN_KSO_ALL;
+		/* Set logical level low on COL2 */
+		cros_kb_raw_set_col2(0);
+
+		/*
+		 * Fix glitches on KSIs pins as all KSOs are driven low
+		 * As keyboard is enabled, either in POR initialization
+		 * or after previous key's break scan code sent to host,
+		 * EC will drive all KSOs low for ready next key press
+		 * detection. KSIs may have glitches based on differnt
+		 * hardward design, this source bit checking and clean
+		 * can prevent one faulty interrupt occurring, thought
+		 * this faulty interrupt is harmless.
+		 */
+		if (inst->KSI_IN != 0xff) {
+			kb_raw_xec_clr_src(dev);
+		}
+		mchp_soc_ecia_girq_src_en(MCHP_GIRQ21_ID,
+					  MCHP_KEYSCAN_GIRQ_POS);
+	}
+	/* Drive one line to low for determining
+	 * which key's state changed.
+	 */
+	else if (IS_ENABLED(CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED)) {
+		if (col == 2) {
+			inst->KSO_SEL = MCHP_KSCAN_KSO_EN;
+			/* Set logical level low on COL2 */
+			cros_kb_raw_set_col2(0);
+		} else {
+			inst->KSO_SEL = col + CONFIG_KEYBOARD_KSO_BASE;
+			/* Set logical level high on COL2 */
+			cros_kb_raw_set_col2(1);
+		}
+	} else {
+		inst->KSO_SEL = col + CONFIG_KEYBOARD_KSO_BASE;
+	}
+
+	return 0;
+}
+
+static void cros_kb_raw_xec_ksi_isr(const struct device *dev)
+{
+	kb_raw_xec_clr_src(dev);
+	/* Wake-up keyboard scan task */
+	task_wake(TASK_ID_KEYSCAN);
+}
+
+static int cros_kb_raw_xec_init(const struct device *dev)
+{
+	struct cros_kb_raw_xec_config const *cfg = dev->config;
+	struct kscan_regs *const inst = (struct kscan_regs *)cfg->base;
+
+	/* Use zephyr pinctrl to initialize pins */
+	int ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
+
+	if (ret)
+		return ret;
+
+	/* Set up Kscan IRQ and ISR */
+	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
+		    cros_kb_raw_xec_ksi_isr, DEVICE_DT_INST_GET(0), 0);
+
+	/* Disable Kscan NVIC and source interrupts */
+	irq_disable(cfg->irq);
+	mchp_soc_ecia_girq_src_dis(MCHP_GIRQ21_ID, MCHP_KEYSCAN_GIRQ_POS);
+	kb_raw_xec_clr_src(dev);
+	/* Enable all Kscan KSIs interrupt */
+	inst->KSI_IEN = 0xff;
+	/* Enable Kscan source interrupt */
+	mchp_soc_ecia_girq_src_en(MCHP_GIRQ21_ID, MCHP_KEYSCAN_GIRQ_POS);
+
+	return 0;
+}
+
+static const struct cros_kb_raw_driver_api cros_kb_raw_xec_driver_api = {
+	.init = cros_kb_raw_xec_init,
+	.drive_colum = cros_kb_raw_xec_drive_column,
+	.read_rows = cros_kb_raw_xec_read_row,
+	.enable_interrupt = cros_kb_raw_xec_enable_interrupt,
+};
+
+/* instantiate zephyr pinctrl constant info */
+PINCTRL_DT_INST_DEFINE(0);
+
+static const struct cros_kb_raw_xec_config cros_kb_raw_cfg = {
+	.base = DT_INST_REG_ADDR(0),
+	.irq = DT_INST_IRQN(0),
+	.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
+};
+
+/* Verify there's exactly one enabled cros,kb-raw-xec node. */
+BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1);
+DEVICE_DT_INST_DEFINE(0, kb_raw_xec_init, NULL, NULL, &cros_kb_raw_cfg,
+		      PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
+		      &cros_kb_raw_xec_driver_api);
diff --git a/zephyr/drivers/cros_kblight/CMakeLists.txt b/zephyr/drivers/cros_kblight/CMakeLists.txt
new file mode 100644
index 0000000000..6371370b65
--- /dev/null
+++ b/zephyr/drivers/cros_kblight/CMakeLists.txt
@@ -0,0 +1,5 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_PWM_KBLIGHT pwm_kblight.c)
diff --git a/zephyr/drivers/cros_kblight/pwm_kblight.c b/zephyr/drivers/cros_kblight/pwm_kblight.c
new file mode 100644
index 0000000000..ca395f8dba
--- /dev/null
+++ b/zephyr/drivers/cros_kblight/pwm_kblight.c
@@ -0,0 +1,84 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define DT_DRV_COMPAT cros_ec_kblight_pwm
+
+#include "common.h"
+#include "keyboard_backlight.h"
+#include "util.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/pwm.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(kblight, LOG_LEVEL_ERR);
+
+BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
+	     "Exactly one instance of cros-ec,kblight-pwm should be defined.");
+
+static const struct pwm_dt_spec kblight_pwm_dt = PWM_DT_SPEC_INST_GET(0);
+
+static bool kblight_enabled;
+static int kblight_percent;
+
+static void kblight_pwm_set_duty(int percent)
+{
+	const struct device *pwm_dev = kblight_pwm_dt.dev;
+	uint32_t pulse_ns;
+	int rv;
+
+	if (!device_is_ready(pwm_dev)) {
+		LOG_ERR("PWM device %s not ready", pwm_dev->name);
+		return;
+	}
+
+	pulse_ns = DIV_ROUND_NEAREST(kblight_pwm_dt.period * percent, 100);
+
+	LOG_DBG("kblight PWM %s set percent (%d), pulse %d", pwm_dev->name,
+		percent, pulse_ns);
+
+	rv = pwm_set_pulse_dt(&kblight_pwm_dt, pulse_ns);
+	if (rv) {
+		LOG_ERR("pwm_set_pulse_dt failed %s (%d)", pwm_dev->name, rv);
+	}
+}
+
+static int kblight_pwm_set(int percent)
+{
+	kblight_percent = percent;
+	kblight_pwm_set_duty(percent);
+	return EC_SUCCESS;
+}
+
+static int kblight_pwm_enable(int enable)
+{
+	kblight_enabled = enable;
+	if (enable) {
+		kblight_pwm_set_duty(kblight_percent);
+	} else {
+		/* Disable but hold kblight_percent. */
+		kblight_pwm_set_duty(0);
+	}
+	return EC_SUCCESS;
+}
+
+static int kblight_pwm_get_enabled(void)
+{
+	return kblight_enabled;
+}
+
+static int kblight_pwm_init(void)
+{
+	kblight_percent = 0;
+	kblight_pwm_enable(0);
+	return EC_SUCCESS;
+}
+
+const struct kblight_drv kblight_pwm = {
+	.init = kblight_pwm_init,
+	.set = kblight_pwm_set,
+	.enable = kblight_pwm_enable,
+	.get_enabled = kblight_pwm_get_enabled,
+};
diff --git a/zephyr/drivers/cros_rtc/CMakeLists.txt b/zephyr/drivers/cros_rtc/CMakeLists.txt
new file mode 100644
index 0000000000..d9ae577254
--- /dev/null
+++ b/zephyr/drivers/cros_rtc/CMakeLists.txt
@@ -0,0 +1,10 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+zephyr_library_sources_ifdef(CONFIG_CROS_RTC_NPCX	cros_rtc_npcx.c)
+zephyr_library_sources_ifdef(CONFIG_CROS_RTC_NXP_PCF85063A
+	nxp_rtc_pcf85063a.c)
+zephyr_library_sources_ifdef(CONFIG_CROS_RTC_RENESAS_IDT1337AG
+	renesas_rtc_idt1337ag.c)
+zephyr_library_sources_ifdef(CONFIG_CROS_RTC_XEC	cros_rtc_xec.c)
diff --git a/zephyr/drivers/cros_rtc/Kconfig b/zephyr/drivers/cros_rtc/Kconfig
new file mode 100644
index 0000000000..2f064b4db8
--- /dev/null
+++ b/zephyr/drivers/cros_rtc/Kconfig
@@ -0,0 +1,55 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if PLATFORM_EC_RTC && !ARCH_POSIX
+
+choice CROS_RTC_TYPE
+	prompt "Select the RTC to use"
+	# List standalone controllers before embedded once so that they get
+	# higher priority.
+	default CROS_RTC_NXP_PCF85063A if DT_HAS_NXP_RTC_PCF85063A_ENABLED
+	default CROS_RTC_RENESAS_IDT1337AG if DT_HAS_RENESAS_RTC_IDT1337AG_ENABLED
+	default CROS_RTC_NPCX if DT_HAS_NUVOTON_NPCX_CROS_MTC_ENABLED
+	default CROS_RTC_XEC if DT_HAS_MICROCHIP_XEC_CROS_RTC_ENABLED
+	help
+	  Select the RTC used on the board.
+
+config CROS_RTC_NPCX
+	bool "Nuvoton NPCX Real-Time Clock (RTC) driver for the Zephyr shim"
+	depends on SOC_FAMILY_NPCX
+	help
+	  This option enables a driver for providing the support of Real-Time
+	  Clock (RTC) on the NPCX chip.
+
+config CROS_RTC_XEC
+	bool "Microchip XEC Real-Time Clock (RTC) driver for the Zephyr shim"
+	depends on SOC_FAMILY_MEC
+	help
+	  This option enables a driver for providing the support of Real-Time
+	  Clock (RTC) on the MCHP XEC chip.
+
+config CROS_RTC_NXP_PCF85063A
+	bool "NXP PCF85063A Real-Time Clock (RTC) driver for the Zephyr shim"
+	depends on I2C
+	help
+	  This option enables a driver for providing the support of NXP
+	  Real-Time Clock (RTC) on the the I2C bus.
+
+config CROS_RTC_RENESAS_IDT1337AG
+	bool "RENESAS IDT1337AG Real-Time Clock (RTC) driver for the Zephyr shim"
+	depends on I2C
+	help
+	  This option enables a driver for providing the support of RENESAS
+	  Real-Time Clock (RTC) on the the I2C bus.
+
+endchoice # CROS_RTC_TYPE
+
+config PLATFORM_EC_PCF85063A_CAP_SEL
+	bool "Set CAP_SEL of PCF85063A"
+	depends on CROS_RTC_NXP_PCF85063A
+	help
+	  This option select the internal oscillator capacitor to 12.5 pF,
+	  default is 7 pF.
+
+endif # PLATFORM_EC_RTC
diff --git a/zephyr/drivers/cros_rtc/cros_rtc_npcx.c b/zephyr/drivers/cros_rtc/cros_rtc_npcx.c
new file mode 100644
index 0000000000..a781ac684e
--- /dev/null
+++ b/zephyr/drivers/cros_rtc/cros_rtc_npcx.c
@@ -0,0 +1,241 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define DT_DRV_COMPAT nuvoton_npcx_cros_mtc
+
+#include "ec_tasks.h"
+#include "soc_miwu.h"
+#include "task.h"
+
+#include <assert.h>
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+
+#include <drivers/cros_rtc.h>
+#include <soc.h>
+#include <soc/nuvoton_npcx/reg_def_cros.h>
+LOG_MODULE_REGISTER(cros_rtc, LOG_LEVEL_ERR);
+
+#define NPCX_MTC_TTC_LOAD_DELAY_US 250 /* Delay after writing TTC */
+#define NPCX_MTC_ALARM_MASK GENMASK(24, 0) /* Valid field of alarm in WTC */
+
+/* Driver config */
+struct cros_rtc_npcx_config {
+	/* Monotonic counter base address */
+	uintptr_t base;
+	/* Monotonic counter wake-up input source configuration */
+	const struct npcx_wui mtc_alarm;
+};
+
+/* Driver data */
+struct cros_rtc_npcx_data {
+	/* Monotonic counter wake-up callback object */
+	struct miwu_callback miwu_mtc_cb;
+	cros_rtc_alarm_callback_t alarm_callback;
+};
+
+/* Driver convenience defines */
+#define DRV_CONFIG(dev) ((const struct cros_rtc_npcx_config *)(dev)->config)
+
+#define DRV_DATA(dev) ((struct cros_rtc_npcx_data *)(dev)->data)
+
+#define HAL_INSTANCE(dev) (struct mtc_reg *)(DRV_CONFIG(dev)->base)
+
+/* Counter internal local functions */
+static uint32_t counter_npcx_get_val(const struct device *dev)
+{
+	struct mtc_reg *const inst = HAL_INSTANCE(dev);
+
+	/*
+	 * Get value of monotonic counter which keeps counting when VCC1 power
+	 * domain exists (Unit:sec)
+	 */
+	return inst->TTC;
+}
+
+static void counter_npcx_set_val(const struct device *dev, uint32_t val)
+{
+	struct mtc_reg *const inst = HAL_INSTANCE(dev);
+
+	/*
+	 * Set monotonic counter. Write it twice to ensure the value latch to
+	 * TTC register. A delay (~250 us) is also needed before writing again.
+	 */
+	inst->TTC = val;
+	k_busy_wait(NPCX_MTC_TTC_LOAD_DELAY_US);
+
+	inst->TTC = val;
+	k_busy_wait(NPCX_MTC_TTC_LOAD_DELAY_US);
+}
+
+static uint32_t counter_npcx_get_alarm_val(const struct device *dev)
+{
+	struct mtc_reg *const inst = HAL_INSTANCE(dev);
+
+	/*
+	 * If alarm is not set or it is set and has already gone off, return
+	 * zero directly.
+	 */
+	if (!IS_BIT_SET(inst->WTC, NPCX_WTC_WIE) ||
+	    IS_BIT_SET(inst->WTC, NPCX_WTC_PTO)) {
+		return 0;
+	}
+
+	/* Return 25-bit alarm value */
+	return inst->WTC & NPCX_MTC_ALARM_MASK;
+}
+
+static void counter_npcx_set_alarm_val(const struct device *dev, uint32_t val)
+{
+	struct mtc_reg *const inst = HAL_INSTANCE(dev);
+
+	/* Disable alarm interrupt */
+	inst->WTC &= ~BIT(NPCX_WTC_WIE);
+
+	/* Set new alarm value */
+	inst->WTC = val & NPCX_MTC_ALARM_MASK;
+
+	/* Enable alarm interrupt */
+	inst->WTC |= BIT(NPCX_WTC_WIE);
+}
+
+static void counter_npcx_reset_alarm(const struct device *dev)
+{
+	struct mtc_reg *const inst = HAL_INSTANCE(dev);
+
+	/* Disable alarm interrupt first */
+	if (IS_BIT_SET(inst->WTC, NPCX_WTC_WIE)) {
+		inst->WTC &= ~BIT(NPCX_WTC_WIE);
+	}
+
+	/* Set alarm to maximum value and clear its pending bit */
+	if (IS_BIT_SET(inst->WTC, NPCX_WTC_PTO)) {
+		inst->WTC = NPCX_MTC_ALARM_MASK;
+		inst->WTC |= BIT(NPCX_WTC_PTO);
+	}
+}
+
+/* Counter local functions */
+static void counter_npcx_isr(const struct device *dev, struct npcx_wui *wui)
+{
+	struct cros_rtc_npcx_data *data = DRV_DATA(dev);
+
+	LOG_DBG("%s", __func__);
+
+	/* Alarm is one-shot, so reset alarm to default */
+	counter_npcx_reset_alarm(dev);
+
+	/* Call callback function */
+	if (data->alarm_callback) {
+		data->alarm_callback(dev);
+	}
+}
+
+/* cros ec RTC api functions */
+static int cros_rtc_npcx_configure(const struct device *dev,
+				   cros_rtc_alarm_callback_t callback)
+{
+	struct cros_rtc_npcx_data *data = DRV_DATA(dev);
+
+	if (callback == NULL) {
+		return -EINVAL;
+	}
+
+	data->alarm_callback = callback;
+	return 0;
+}
+
+static int cros_rtc_npcx_get_value(const struct device *dev, uint32_t *value)
+{
+	*value = counter_npcx_get_val(dev);
+
+	return 0;
+}
+
+static int cros_rtc_npcx_set_value(const struct device *dev, uint32_t value)
+{
+	counter_npcx_set_val(dev, value);
+
+	return 0;
+}
+static int cros_rtc_npcx_get_alarm(const struct device *dev, uint32_t *seconds,
+				   uint32_t *microseconds)
+{
+	*seconds = counter_npcx_get_alarm_val(dev);
+	*microseconds = 0;
+
+	return 0;
+}
+static int cros_rtc_npcx_set_alarm(const struct device *dev, uint32_t seconds,
+				   uint32_t microseconds)
+{
+	const struct cros_rtc_npcx_config *config = DRV_CONFIG(dev);
+	ARG_UNUSED(microseconds);
+
+	/* Enable interrupt of the MTC alarm wake-up input source */
+	npcx_miwu_irq_enable(&config->mtc_alarm);
+
+	/* Make sure alarm restore to default state */
+	counter_npcx_reset_alarm(dev);
+	counter_npcx_set_alarm_val(dev, seconds);
+
+	return 0;
+}
+
+static int cros_rtc_npcx_reset_alarm(const struct device *dev)
+{
+	const struct cros_rtc_npcx_config *config = DRV_CONFIG(dev);
+
+	/* Disable interrupt of the MTC alarm wake-up input source */
+	npcx_miwu_irq_disable(&config->mtc_alarm);
+
+	counter_npcx_reset_alarm(dev);
+
+	return 0;
+}
+
+/* cros ec RTC driver registration */
+static const struct cros_rtc_driver_api cros_rtc_npcx_driver_api = {
+	.configure = cros_rtc_npcx_configure,
+	.get_value = cros_rtc_npcx_get_value,
+	.set_value = cros_rtc_npcx_set_value,
+	.get_alarm = cros_rtc_npcx_get_alarm,
+	.set_alarm = cros_rtc_npcx_set_alarm,
+	.reset_alarm = cros_rtc_npcx_reset_alarm,
+};
+
+static int cros_rtc_npcx_init(const struct device *dev)
+{
+	const struct cros_rtc_npcx_config *config = DRV_CONFIG(dev);
+	struct cros_rtc_npcx_data *data = DRV_DATA(dev);
+
+	/* Initialize the miwu input and its callback for monotonic counter */
+	npcx_miwu_init_dev_callback(&data->miwu_mtc_cb, &config->mtc_alarm,
+				    counter_npcx_isr, dev);
+	npcx_miwu_manage_callback(&data->miwu_mtc_cb, true);
+
+	/*
+	 * Configure the monotonic counter wake-up event triggered from a rising
+	 * edge on its signal.
+	 */
+	npcx_miwu_interrupt_configure(&config->mtc_alarm, NPCX_MIWU_MODE_EDGE,
+				      NPCX_MIWU_TRIG_HIGH);
+
+	return 0;
+}
+
+static const struct cros_rtc_npcx_config cros_rtc_npcx_cfg_0 = {
+	.base = DT_INST_REG_ADDR(0),
+	.mtc_alarm = NPCX_DT_WUI_ITEM_BY_NAME(0, mtc_alarm)
+};
+
+static struct cros_rtc_npcx_data cros_rtc_npcx_data_0;
+
+DEVICE_DT_INST_DEFINE(0, cros_rtc_npcx_init, /* pm_control_fn= */ NULL,
+		      &cros_rtc_npcx_data_0, &cros_rtc_npcx_cfg_0, POST_KERNEL,
+		      CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
+		      &cros_rtc_npcx_driver_api);
diff --git a/zephyr/drivers/cros_rtc/cros_rtc_xec.c b/zephyr/drivers/cros_rtc/cros_rtc_xec.c
new file mode 100644
index 0000000000..f42560e107
--- /dev/null
+++ b/zephyr/drivers/cros_rtc/cros_rtc_xec.c
@@ -0,0 +1,130 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define DT_DRV_COMPAT microchip_xec_cros_rtc
+
+#include "ec_tasks.h"
+#include "task.h"
+
+#include <assert.h>
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+
+#include <drivers/cros_rtc.h>
+#include <soc.h>
+#include <soc/microchip_xec/reg_def_cros.h>
+LOG_MODULE_REGISTER(cros_rtc, LOG_LEVEL_ERR);
+
+/* Driver config */
+struct cros_rtc_xec_config {
+	uintptr_t base;
+};
+
+/* Driver data */
+struct cros_rtc_xec_data {
+	cros_rtc_alarm_callback_t alarm_callback;
+};
+
+/* Driver convenience defines */
+#define DRV_CONFIG(dev) ((const struct cros_rtc_xec_config *)(dev)->config)
+
+#define DRV_DATA(dev) ((struct cros_rtc_xec_data *)(dev)->data)
+
+#define HAL_INSTANCE(dev) (struct rtc_hw *)(DRV_CONFIG(dev)->base)
+
+/* cros ec RTC api functions */
+static int cros_rtc_xec_configure(const struct device *dev,
+				  cros_rtc_alarm_callback_t callback)
+{
+	ARG_UNUSED(dev);
+	ARG_UNUSED(callback);
+
+	/* TODO(b/214988394): Chip has RTC hardware, need to implement code */
+
+	return 0;
+}
+
+static int cros_rtc_xec_get_value(const struct device *dev, uint32_t *value)
+{
+	ARG_UNUSED(dev);
+
+	/* TODO(b/214988394): Chip has RTC hardware, need to implement code */
+	*value = 0;
+
+	return 0;
+}
+
+static int cros_rtc_xec_set_value(const struct device *dev, uint32_t value)
+{
+	ARG_UNUSED(dev);
+	ARG_UNUSED(value);
+
+	/* TODO(b/214988394): Chip has RTC hardware, need to implement code */
+
+	return 0;
+}
+
+static int cros_rtc_xec_get_alarm(const struct device *dev, uint32_t *seconds,
+				  uint32_t *microseconds)
+{
+	ARG_UNUSED(dev);
+
+	/* TODO(b/214988394): Chip has RTC hardware, need to implement code */
+	*seconds = 0;
+	*microseconds = 0;
+
+	return 0;
+}
+
+static int cros_rtc_xec_set_alarm(const struct device *dev, uint32_t seconds,
+				  uint32_t microseconds)
+{
+	ARG_UNUSED(dev);
+	ARG_UNUSED(seconds);
+	ARG_UNUSED(microseconds);
+
+	/* TODO(b/214988394): Chip has RTC hardware, need to implement code */
+	return -ENOTSUP;
+}
+
+static int cros_rtc_xec_reset_alarm(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	/* TODO(b/214988394): Chip has RTC hardware, need to implement code */
+	return -ENOTSUP;
+}
+
+/* cros ec RTC driver registration */
+static const struct cros_rtc_driver_api cros_rtc_xec_driver_api = {
+	.configure = cros_rtc_xec_configure,
+	.get_value = cros_rtc_xec_get_value,
+	.set_value = cros_rtc_xec_set_value,
+	.get_alarm = cros_rtc_xec_get_alarm,
+	.set_alarm = cros_rtc_xec_set_alarm,
+	.reset_alarm = cros_rtc_xec_reset_alarm,
+};
+
+static int cros_rtc_xec_init(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	/* TODO(b/214988394): Chip has RTC hardware, need to implement code */
+	return 0;
+}
+
+static const struct cros_rtc_xec_config cros_rtc_xec_cfg_0 = {
+	.base = DT_INST_REG_ADDR(0),
+	/* TODO(b/214988394): Chip has RTC hardware, need to implement code */
+};
+
+static struct cros_rtc_xec_data cros_rtc_xec_data_0;
+
+DEVICE_DT_INST_DEFINE(0, cros_rtc_xec_init, NULL, &cros_rtc_xec_data_0,
+		      &cros_rtc_xec_cfg_0, POST_KERNEL,
+		      CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
+		      &cros_rtc_xec_driver_api);
diff --git a/zephyr/drivers/cros_rtc/nxp_rtc_pcf85063a.c b/zephyr/drivers/cros_rtc/nxp_rtc_pcf85063a.c
new file mode 100644
index 0000000000..5ff7e148dd
--- /dev/null
+++ b/zephyr/drivers/cros_rtc/nxp_rtc_pcf85063a.c
@@ -0,0 +1,461 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define DT_DRV_COMPAT nxp_rtc_pcf85063a
+
+#include "nxp_rtc_pcf85063a.h"
+
+#include <assert.h>
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+
+#include <drivers/cros_rtc.h>
+#include <rtc.h>
+#include <soc.h>
+LOG_MODULE_REGISTER(cros_rtc, LOG_LEVEL_ERR);
+
+/* Driver config */
+struct nxp_rtc_pcf85063a_config {
+	const struct device *bus;
+	const uint16_t i2c_addr_flags;
+	const struct gpio_dt_spec gpio_alert;
+};
+
+/* Driver data */
+struct nxp_rtc_pcf85063a_data {
+	const struct device *dev;
+	uint8_t time_reg[NUM_TIMER_REGS];
+	struct gpio_callback gpio_cb;
+	cros_rtc_alarm_callback_t alarm_callback;
+};
+
+/* Driver convenience defines */
+#define DRV_CONFIG(dev) ((const struct nxp_rtc_pcf85063a_config *)(dev)->config)
+#define DRV_DATA(dev) ((struct nxp_rtc_pcf85063a_data *)(dev)->data)
+
+/*
+ * is_alarm == true: Reads alarm registers SECONDS, MINUTES, HOURS, and DAYS
+ * is_alarm == false: Reads time registers SECONDS, MINUTES, HOURS, DAYS, and
+ *			MONTHS, YEARS
+ */
+static int pcf85063a_read_time_regs(const struct device *dev, bool is_alarm)
+{
+	const struct nxp_rtc_pcf85063a_config *const config = DRV_CONFIG(dev);
+	struct nxp_rtc_pcf85063a_data *data = DRV_DATA(dev);
+	uint8_t start_reg;
+	uint8_t num_reg;
+
+	if (is_alarm) {
+		start_reg = REG_SECOND_ALARM;
+		num_reg = NUM_ALARM_REGS;
+	} else {
+		start_reg = REG_SECONDS;
+		num_reg = NUM_TIMER_REGS;
+	}
+
+	return i2c_burst_read(config->bus, config->i2c_addr_flags, start_reg,
+			      data->time_reg, num_reg);
+}
+
+static int pcf85063a_read_reg(const struct device *dev, uint8_t reg,
+			      uint8_t *val)
+{
+	const struct nxp_rtc_pcf85063a_config *const config = DRV_CONFIG(dev);
+
+	return i2c_reg_read_byte(config->bus, config->i2c_addr_flags, reg, val);
+}
+
+/*
+ * is_alarm == true: Writes alarm registers SECONDS, MINUTES, HOURS, and DAYS
+ * is_alarm == false: Writes time registers SECONDS, MINUTES, HOURS, DAYS, and
+ *			MONTHS, YEARS
+ */
+static int pcf85063a_write_time_regs(const struct device *dev, bool is_alarm)
+{
+	const struct nxp_rtc_pcf85063a_config *const config = DRV_CONFIG(dev);
+	struct nxp_rtc_pcf85063a_data *data = DRV_DATA(dev);
+	uint8_t tx_buf[NUM_TIMER_REGS];
+	uint8_t start_reg;
+	uint8_t num_reg;
+
+	if (is_alarm) {
+		start_reg = REG_SECOND_ALARM;
+		num_reg = NUM_ALARM_REGS;
+	} else {
+		start_reg = REG_SECONDS;
+		num_reg = NUM_TIMER_REGS;
+	}
+
+	for (int i = 0; i < num_reg; i++) {
+		tx_buf[i] = data->time_reg[i];
+	}
+
+	return i2c_burst_write(config->bus, config->i2c_addr_flags, start_reg,
+			       tx_buf, num_reg);
+}
+
+static int pcf85063a_write_reg(const struct device *dev, uint8_t reg,
+			       uint8_t val)
+{
+	const struct nxp_rtc_pcf85063a_config *const config = DRV_CONFIG(dev);
+	uint8_t tx_buf[2];
+
+	tx_buf[0] = reg;
+	tx_buf[1] = val;
+
+	return i2c_write(config->bus, tx_buf, sizeof(tx_buf),
+			 config->i2c_addr_flags);
+}
+
+/*
+ * val bits 7 to 4 - tens place
+ * val bits 3 to 0 - ones place
+ */
+static int bcd_to_dec(uint8_t val, enum bcd_mask mask)
+{
+	int tens = ((val & mask) >> 4) * 10;
+	int ones = (val & 0xf);
+
+	return tens + ones;
+}
+
+/*
+ * val bits 7 to 4 - tens place
+ * val bits 3 to 0 - ones place
+ */
+static uint8_t dec_to_bcd(uint32_t val, enum bcd_mask mask)
+{
+	int tens = val / 10;
+	int ones = val - (tens * 10);
+
+	return ((tens << 4) & mask) | ones;
+}
+
+static int nxp_rtc_pcf85063a_read_seconds(const struct device *dev,
+					  uint32_t *value, bool is_alarm)
+{
+	struct nxp_rtc_pcf85063a_data *data = DRV_DATA(dev);
+	struct calendar_date time;
+	int ret;
+
+	ret = pcf85063a_read_time_regs(dev, is_alarm);
+
+	if (ret < 0) {
+		return ret;
+	}
+
+	if (is_alarm) {
+		*value = (bcd_to_dec(data->time_reg[DAYS], DAYS_MASK) *
+			  SECS_PER_DAY) +
+			 (bcd_to_dec(data->time_reg[HOURS], HOURS24_MASK) *
+			  SECS_PER_HOUR) +
+			 (bcd_to_dec(data->time_reg[MINUTES], MINUTES_MASK) *
+			  SECS_PER_MINUTE) +
+			 bcd_to_dec(data->time_reg[SECONDS], SECONDS_MASK);
+	} else {
+		time.year = bcd_to_dec(data->time_reg[YEARS], YEARS_MASK);
+		time.month = bcd_to_dec(data->time_reg[MONTHS], MONTHS_MASK);
+		time.day = bcd_to_dec(data->time_reg[DAYS], DAYS_MASK);
+
+		*value = date_to_sec(time) - SECS_TILL_YEAR_2K +
+			 (bcd_to_dec(data->time_reg[HOURS], HOURS24_MASK) *
+			  SECS_PER_HOUR) +
+			 (bcd_to_dec(data->time_reg[MINUTES], MINUTES_MASK) *
+			  SECS_PER_MINUTE) +
+			 bcd_to_dec(data->time_reg[SECONDS], SECONDS_MASK);
+	}
+
+	return ret;
+}
+
+static int nxp_rtc_pcf85063a_write_seconds(const struct device *dev,
+					   uint32_t value, bool is_alarm)
+{
+	struct nxp_rtc_pcf85063a_data *data = DRV_DATA(dev);
+	struct calendar_date time;
+	uint32_t tmp_sec;
+
+	time = sec_to_date(value + SECS_TILL_YEAR_2K);
+
+	if (!is_alarm) {
+		data->time_reg[YEARS] = dec_to_bcd(time.year, YEARS_MASK);
+		data->time_reg[MONTHS] = dec_to_bcd(time.month, MONTHS_MASK);
+	}
+
+	data->time_reg[DAYS] = dec_to_bcd(time.day, DAYS_MASK);
+
+	if (is_alarm && data->time_reg[DAYS] == 0) {
+		data->time_reg[DAYS] |= DISABLE_ALARM;
+	}
+
+	value %= SECS_PER_DAY;
+	tmp_sec = value / SECS_PER_HOUR;
+	data->time_reg[HOURS] = dec_to_bcd(tmp_sec, HOURS24_MASK);
+
+	if (is_alarm && data->time_reg[HOURS] == 0) {
+		data->time_reg[HOURS] |= DISABLE_ALARM;
+	}
+
+	value -= (tmp_sec * SECS_PER_HOUR);
+	tmp_sec = value / SECS_PER_MINUTE;
+	data->time_reg[MINUTES] = dec_to_bcd(tmp_sec, MINUTES_MASK);
+
+	if (is_alarm && data->time_reg[MINUTES] == 0) {
+		data->time_reg[MINUTES] |= DISABLE_ALARM;
+	}
+
+	value -= (tmp_sec * SECS_PER_MINUTE);
+	data->time_reg[SECONDS] = dec_to_bcd(value, SECONDS_MASK);
+
+	if (is_alarm && data->time_reg[SECONDS] == 0) {
+		data->time_reg[SECONDS] |= DISABLE_ALARM;
+	}
+
+	return pcf85063a_write_time_regs(dev, is_alarm);
+}
+
+static int nxp_rtc_pcf85063a_configure(const struct device *dev,
+				       cros_rtc_alarm_callback_t callback)
+{
+	struct nxp_rtc_pcf85063a_data *data = DRV_DATA(dev);
+
+	if (callback == NULL) {
+		return -EINVAL;
+	}
+
+	data->alarm_callback = callback;
+
+	return 0;
+}
+
+static int nxp_rtc_pcf85063a_get_value(const struct device *dev,
+				       uint32_t *value)
+{
+	return nxp_rtc_pcf85063a_read_seconds(dev, value, false);
+}
+
+static int nxp_rtc_pcf85063a_set_value(const struct device *dev, uint32_t value)
+{
+	return nxp_rtc_pcf85063a_write_seconds(dev, value, false);
+}
+
+static int nxp_rtc_pcf85063a_get_alarm(const struct device *dev,
+				       uint32_t *seconds,
+				       uint32_t *microseconds)
+{
+	*microseconds = 0;
+	return nxp_rtc_pcf85063a_read_seconds(dev, seconds, true);
+}
+
+static int nxp_rtc_pcf85063a_reset_alarm(const struct device *dev)
+{
+	struct nxp_rtc_pcf85063a_data *data = DRV_DATA(dev);
+	int ret;
+
+	/* Disable alarm interrupt and clear pending alarm flag */
+	ret = pcf85063a_write_reg(dev, REG_CONTROL_2, 0);
+	if (ret < 0) {
+		return ret;
+	}
+
+	/* Clear and disable the alarm registers */
+	data->time_reg[SECONDS] = DISABLE_ALARM;
+	data->time_reg[MINUTES] = DISABLE_ALARM;
+	data->time_reg[HOURS] = DISABLE_ALARM;
+	data->time_reg[DAYS] = DISABLE_ALARM;
+
+	return pcf85063a_write_time_regs(dev, true);
+}
+
+static int nxp_rtc_pcf85063a_set_alarm(const struct device *dev,
+				       uint32_t seconds, uint32_t microseconds)
+{
+	int ret;
+
+	ARG_UNUSED(microseconds);
+
+	ret = nxp_rtc_pcf85063a_reset_alarm(dev);
+
+	if (ret < 0) {
+		return ret;
+	}
+
+	ret = nxp_rtc_pcf85063a_write_seconds(dev, seconds, true);
+
+	if (ret < 0) {
+		return ret;
+	}
+
+	return pcf85063a_write_reg(dev, REG_CONTROL_2, ENABLE_ALARM_INTERRUPT);
+}
+
+static void nxp_pcf85063a_isr(const struct device *port,
+			      struct gpio_callback *cb, uint32_t pin)
+{
+	struct nxp_rtc_pcf85063a_data *data =
+		CONTAINER_OF(cb, struct nxp_rtc_pcf85063a_data, gpio_cb);
+	const struct device *dev = (const struct device *)data->dev;
+
+	ARG_UNUSED(port);
+	ARG_UNUSED(pin);
+	ARG_UNUSED(cb);
+
+	LOG_DBG("%s", __func__);
+
+	/* Call callback function */
+	if (data->alarm_callback) {
+		data->alarm_callback(dev);
+	}
+}
+
+static const struct cros_rtc_driver_api nxp_rtc_pcf85063a_driver_api = {
+	.configure = nxp_rtc_pcf85063a_configure,
+	.get_value = nxp_rtc_pcf85063a_get_value,
+	.set_value = nxp_rtc_pcf85063a_set_value,
+	.get_alarm = nxp_rtc_pcf85063a_get_alarm,
+	.set_alarm = nxp_rtc_pcf85063a_set_alarm,
+	.reset_alarm = nxp_rtc_pcf85063a_reset_alarm,
+};
+
+static int nxp_rtc_pcf85063a_init(const struct device *dev)
+{
+	const struct nxp_rtc_pcf85063a_config *const config = DRV_CONFIG(dev);
+	struct nxp_rtc_pcf85063a_data *data = DRV_DATA(dev);
+	uint8_t default_val;
+	uint8_t val;
+	int ret;
+
+	if (!device_is_ready(config->bus)) {
+		LOG_ERR("Device %s is not ready", config->bus->name);
+		return -ENODEV;
+	}
+
+	/*
+	 * Read Control_1 register. For normal operation,
+	 * the values should be as follows:
+	 *	Bit 7 (external clock test mode)    : (0) normal mode
+	 *	Bit 6 (unused)                      : (0)
+	 *	Bit 5 (STOP bit)                    : (0) RTC clock runs
+	 *	BIT 4 (software reset)              : (0) no software reset
+	 *	BIT 3 (unused)                      : (0)
+	 *	BIT 2 (correction interrupt enable) : (0) no correction
+	 *	                                          interrupt generated
+	 *	BIT 1 (12 or 24-hour mode)          : (0) 24-hour mode
+	 *	BIT 0 (internal oscillator capacitor: (0) 7pF
+	 */
+	default_val = CONTROL_1_DEFAULT_VALUE;
+#ifdef CONFIG_PLATFORM_EC_PCF85063A_CAP_SEL
+	default_val |= CAP_SEL;
+#endif
+
+	ret = pcf85063a_read_reg(dev, REG_CONTROL_1, &val);
+
+	if (ret < 0) {
+		return ret;
+	}
+
+	if (val != default_val) {
+		/* PCF85063A is not initialized, so send soft reset */
+		ret = pcf85063a_write_reg(dev, REG_CONTROL_1, SOFT_RESET);
+
+		if (ret < 0) {
+			return ret;
+		}
+	}
+
+#ifdef CONFIG_PLATFORM_EC_PCF85063A_CAP_SEL
+	ret = pcf85063a_write_reg(dev, REG_CONTROL_1,
+				  (CONTROL_1_DEFAULT_VALUE | CAP_SEL));
+
+	if (ret < 0) {
+		LOG_ERR("PCF85063A set CAP_SEL Fail!");
+		return ret;
+	}
+#endif
+
+	/*
+	 * Read Seconds register and check if oscillator is stopped.
+	 * If so, clear the bit.
+	 */
+	ret = pcf85063a_read_reg(dev, REG_SECONDS, &val);
+
+	if (ret < 0) {
+		return ret;
+	}
+
+	if (val & OS_BIT) {
+		/* Oscillator stop bit is set, clear it. */
+		val &= ~OS_BIT;
+		ret = pcf85063a_write_reg(dev, REG_SECONDS, val);
+
+		if (ret < 0) {
+			return ret;
+		}
+	}
+
+	nxp_rtc_pcf85063a_reset_alarm(dev);
+
+	/* Configure GPIO interrupt pin for PCF85063A alarm pin */
+
+	if (!device_is_ready(config->gpio_alert.port)) {
+		LOG_ERR("Alert GPIO device not ready");
+		return -ENODEV;
+	}
+
+	ret = gpio_pin_configure_dt(&config->gpio_alert, GPIO_INPUT);
+
+	if (ret < 0) {
+		LOG_ERR("Could not configure RTC alert pin");
+		return ret;
+	}
+
+	gpio_init_callback(&data->gpio_cb, nxp_pcf85063a_isr,
+			   BIT(config->gpio_alert.pin));
+
+	ret = gpio_add_callback(config->gpio_alert.port, &data->gpio_cb);
+
+	if (ret < 0) {
+		LOG_ERR("Could not set RTC alert pin callback");
+		return ret;
+	}
+
+	data->dev = dev;
+
+	return gpio_pin_interrupt_configure_dt(&config->gpio_alert,
+					       GPIO_INT_EDGE_FALLING);
+}
+
+#define PCF85063A_INT_GPIOS DT_PHANDLE(DT_NODELABEL(pcf85063a), int_pin)
+
+/*
+ * dt_flags is a uint8_t type.  However, for platform/ec
+ * the GPIO flags in the devicetree are expanded past 8 bits
+ * to support the INPUT/OUTPUT and PULLUP/PULLDOWN properties.
+ * Cast back to a gpio_dt_flags to compile, discarding the bits
+ * that are not supported by the Zephyr GPIO API.
+ */
+#define CROS_EC_GPIO_DT_SPEC_GET(node_id, prop)                            \
+	{                                                                  \
+		.port = DEVICE_DT_GET(DT_GPIO_CTLR(node_id, prop)),        \
+		.pin = DT_GPIO_PIN(node_id, prop),                         \
+		.dt_flags = (gpio_dt_flags_t)DT_GPIO_FLAGS(node_id, prop), \
+	}
+
+static const struct nxp_rtc_pcf85063a_config nxp_rtc_pcf85063a_cfg_0 = {
+	.bus = DEVICE_DT_GET(DT_INST_BUS(0)),
+	.i2c_addr_flags = DT_INST_REG_ADDR(0),
+	.gpio_alert = CROS_EC_GPIO_DT_SPEC_GET(PCF85063A_INT_GPIOS, gpios)
+};
+
+static struct nxp_rtc_pcf85063a_data nxp_rtc_pcf85063a_data_0;
+
+DEVICE_DT_INST_DEFINE(0, nxp_rtc_pcf85063a_init, /* pm_control_fn= */ NULL,
+		      &nxp_rtc_pcf85063a_data_0, &nxp_rtc_pcf85063a_cfg_0,
+		      POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
+		      &nxp_rtc_pcf85063a_driver_api);
diff --git a/zephyr/drivers/cros_rtc/nxp_rtc_pcf85063a.h b/zephyr/drivers/cros_rtc/nxp_rtc_pcf85063a.h
new file mode 100644
index 0000000000..c0139db631
--- /dev/null
+++ b/zephyr/drivers/cros_rtc/nxp_rtc_pcf85063a.h
@@ -0,0 +1,59 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_RTC_PCF85063A_H
+#define __CROS_EC_RTC_PCF85063A_H
+
+#define PCF85063A_REG_NUM 18
+#define SOFT_RESET 0x58
+#define CONTROL_1_DEFAULT_VALUE 0
+#define OS_BIT 0x80
+#define CAP_SEL 0x01
+#define DISABLE_ALARM 0x80
+#define ENABLE_ALARM_INTERRUPT 0x80
+#define RTC_STOP_CLOCKS 0x20
+#define RTC_START_CLOCKS 0x00
+
+#define NUM_TIMER_REGS 7
+#define NUM_ALARM_REGS 4
+
+#define REG_CONTROL_1 0x00
+#define REG_CONTROL_2 0x01
+#define REG_OFFSET 0x02
+#define REG_RAM_BYTE 0x03
+#define REG_SECONDS 0x04
+#define REG_MINUTES 0x05
+#define REG_HOURS 0x06
+#define REG_DAYS 0x07
+#define REG_WEEKDAYS 0x08
+#define REG_MONTHS 0x09
+#define REG_YEARS 0x0a
+#define REG_SECOND_ALARM 0x0b
+#define REG_MINUTE_ALARM 0x0c
+#define REG_HOUR_ALARM 0x0d
+#define REG_DAY_ALARM 0x0e
+#define REG_WEEKDAY_ALARM 0x0f
+#define REG_TIMER_VALUE 0x10
+#define REG_TIMER_MODE 0x11
+
+/* Macros for indexing time_reg buffer */
+#define SECONDS 0
+#define MINUTES 1
+#define HOURS 2
+#define DAYS 3
+#define WEEKDAYS 4
+#define MONTHS 5
+#define YEARS 6
+
+enum bcd_mask {
+	SECONDS_MASK = 0x70,
+	MINUTES_MASK = 0x70,
+	HOURS24_MASK = 0x30,
+	DAYS_MASK = 0x30,
+	MONTHS_MASK = 0x10,
+	YEARS_MASK = 0xf0
+};
+
+#endif /* __CROS_EC_RTC_PCF85063A_H */
diff --git a/zephyr/drivers/cros_rtc/renesas_rtc_idt1337ag.c b/zephyr/drivers/cros_rtc/renesas_rtc_idt1337ag.c
new file mode 100644
index 0000000000..f6d3a7c292
--- /dev/null
+++ b/zephyr/drivers/cros_rtc/renesas_rtc_idt1337ag.c
@@ -0,0 +1,481 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define DT_DRV_COMPAT renesas_rtc_idt1337ag
+
+#include "renesas_rtc_idt1337ag.h"
+
+#include <assert.h>
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+
+#include <drivers/cros_rtc.h>
+#include <rtc.h>
+#include <soc.h>
+LOG_MODULE_REGISTER(cros_rtc, LOG_LEVEL_ERR);
+
+/* Driver config */
+struct renesas_rtc_idt1337ag_config {
+	const struct device *bus;
+	const uint16_t i2c_addr_flags;
+	const struct gpio_dt_spec gpio_alert;
+};
+
+/* Driver data */
+struct renesas_rtc_idt1337ag_data {
+	const struct device *dev;
+	struct gpio_callback gpio_cb;
+	cros_rtc_alarm_callback_t alarm_callback;
+};
+
+enum timer_type {
+	RTC_TIMER,
+	ALARM_TIMER,
+};
+
+/*
+ * type == ALARM_TIMER: Reads alarm registers SECONDS, MINUTES, HOURS, and DAYS
+ * type == RTC_TIMER: Reads time registers SECONDS, MINUTES, HOURS, DAYS, and
+ *			MONTHS, YEARS
+ */
+static int idt1337ag_read_time_regs(const struct device *dev, uint8_t *time_reg,
+				    enum timer_type type)
+{
+	const struct renesas_rtc_idt1337ag_config *const config = dev->config;
+	uint8_t start_reg;
+	uint8_t num_reg;
+
+	if (type == ALARM_TIMER) {
+		start_reg = REG_SECOND_ALARM1;
+		num_reg = NUM_ALARM_REGS;
+	} else {
+		start_reg = REG_SECONDS;
+		num_reg = NUM_TIMER_REGS;
+	}
+
+	return i2c_burst_read(config->bus, config->i2c_addr_flags, start_reg,
+			      time_reg, num_reg);
+}
+
+static int idt1337ag_read_reg(const struct device *dev, uint8_t reg,
+			      uint8_t *val)
+{
+	const struct renesas_rtc_idt1337ag_config *const config = dev->config;
+
+	return i2c_reg_read_byte(config->bus, config->i2c_addr_flags, reg, val);
+}
+
+/*
+ * type == ALARM_TIMER: Writes alarm registers SECONDS, MINUTES, HOURS, and DAYS
+ * type == RTC_TIMER: Writes time registers SECONDS, MINUTES, HOURS, DAYS, and
+ *			MONTHS, YEARS
+ */
+static int idt1337ag_write_time_regs(const struct device *dev,
+				     uint8_t *time_reg, enum timer_type type)
+{
+	const struct renesas_rtc_idt1337ag_config *const config = dev->config;
+	uint8_t start_reg;
+	uint8_t num_reg;
+
+	if (type == ALARM_TIMER) {
+		/*
+		 * Register 0x0A bit 6 determines if the DAY(1b) or DATE(0b)
+		 * alarm is selected.
+		 * Select the DAY alarm
+		 */
+		time_reg[DAYS] |= SELECT_DAYS_ALARM;
+
+		start_reg = REG_SECOND_ALARM1;
+		num_reg = NUM_ALARM_REGS;
+	} else {
+		start_reg = REG_SECONDS;
+		num_reg = NUM_TIMER_REGS;
+	}
+
+	return i2c_burst_write(config->bus, config->i2c_addr_flags, start_reg,
+			       time_reg, num_reg);
+}
+
+static int idt1337ag_write_reg(const struct device *dev, uint8_t reg,
+			       uint8_t val)
+{
+	const struct renesas_rtc_idt1337ag_config *const config = dev->config;
+	uint8_t tx_buf[2];
+
+	tx_buf[0] = reg;
+	tx_buf[1] = val;
+
+	return i2c_write(config->bus, tx_buf, sizeof(tx_buf),
+			 config->i2c_addr_flags);
+}
+
+/*
+ * val bits 7 to 4 - tens place
+ * val bits 3 to 0 - ones place
+ */
+static int bcd_to_dec(uint8_t val, enum bcd_mask mask)
+{
+	int tens = ((val & mask) >> 4) * 10;
+	int ones = (val & 0xf);
+
+	return tens + ones;
+}
+
+/*
+ * val bits 7 to 4 - tens place
+ * val bits 3 to 0 - ones place
+ */
+static uint8_t dec_to_bcd(uint32_t val, enum bcd_mask mask)
+{
+	int tens = val / 10;
+	int ones = val - (tens * 10);
+
+	return ((tens << 4) & mask) | ones;
+}
+
+static int renesas_rtc_idt1337ag_read_seconds(const struct device *dev,
+					      uint32_t *value,
+					      enum timer_type type)
+{
+	uint8_t time_reg[NUM_TIMER_REGS];
+	struct calendar_date time;
+	int ret;
+
+	ret = idt1337ag_read_time_regs(dev, time_reg, type);
+
+	if (ret < 0) {
+		return ret;
+	}
+
+	if (type == ALARM_TIMER) {
+		*value =
+			(bcd_to_dec(time_reg[DAYS], DAYS_MASK) * SECS_PER_DAY) +
+			(bcd_to_dec(time_reg[HOURS], HOURS24_MASK) *
+			 SECS_PER_HOUR) +
+			(bcd_to_dec(time_reg[MINUTES], MINUTES_MASK) *
+			 SECS_PER_MINUTE) +
+			bcd_to_dec(time_reg[SECONDS], SECONDS_MASK);
+	} else {
+		time.year = bcd_to_dec(time_reg[YEARS], YEARS_MASK);
+		time.month = bcd_to_dec(time_reg[MONTHS], MONTHS_MASK);
+		time.day = bcd_to_dec(time_reg[DAYS], DAYS_MASK);
+
+		*value = date_to_sec(time) - SECS_TILL_YEAR_2K +
+			 (bcd_to_dec(time_reg[HOURS], HOURS24_MASK) *
+			  SECS_PER_HOUR) +
+			 (bcd_to_dec(time_reg[MINUTES], MINUTES_MASK) *
+			  SECS_PER_MINUTE) +
+			 bcd_to_dec(time_reg[SECONDS], SECONDS_MASK);
+	}
+
+	return ret;
+}
+
+static int renesas_rtc_idt1337ag_write_seconds(const struct device *dev,
+					       uint32_t value,
+					       enum timer_type type)
+{
+	uint8_t time_reg[NUM_TIMER_REGS];
+	struct calendar_date time;
+	uint32_t tmp_sec;
+
+	time = sec_to_date(value + SECS_TILL_YEAR_2K);
+
+	if (type == RTC_TIMER) {
+		time_reg[YEARS] = dec_to_bcd(time.year, YEARS_MASK);
+		time_reg[MONTHS] = dec_to_bcd(time.month, MONTHS_MASK);
+	}
+
+	time_reg[DAYS] = dec_to_bcd(time.day, DAYS_MASK);
+
+	value %= SECS_PER_DAY;
+	tmp_sec = value / SECS_PER_HOUR;
+	time_reg[HOURS] = dec_to_bcd(tmp_sec, HOURS24_MASK);
+
+	value -= (tmp_sec * SECS_PER_HOUR);
+	tmp_sec = value / SECS_PER_MINUTE;
+	time_reg[MINUTES] = dec_to_bcd(tmp_sec, MINUTES_MASK);
+
+	value -= (tmp_sec * SECS_PER_MINUTE);
+	time_reg[SECONDS] = dec_to_bcd(value, SECONDS_MASK);
+
+	return idt1337ag_write_time_regs(dev, time_reg, type);
+}
+
+static int renesas_rtc_idt1337ag_configure(const struct device *dev,
+					   cros_rtc_alarm_callback_t callback)
+{
+	struct renesas_rtc_idt1337ag_data *data = dev->data;
+
+	if (callback == NULL) {
+		return -EINVAL;
+	}
+
+	data->alarm_callback = callback;
+
+	return 0;
+}
+
+static int renesas_rtc_idt1337ag_get_value(const struct device *dev,
+					   uint32_t *value)
+{
+	return renesas_rtc_idt1337ag_read_seconds(dev, value, RTC_TIMER);
+}
+
+static int renesas_rtc_idt1337ag_set_value(const struct device *dev,
+					   uint32_t value)
+{
+	return renesas_rtc_idt1337ag_write_seconds(dev, value, RTC_TIMER);
+}
+
+static int renesas_rtc_idt1337ag_get_alarm(const struct device *dev,
+					   uint32_t *seconds,
+					   uint32_t *microseconds)
+{
+	*microseconds = 0;
+	return renesas_rtc_idt1337ag_read_seconds(dev, seconds, ALARM_TIMER);
+}
+
+static int renesas_rtc_idt1337ag_reset_alarm(const struct device *dev)
+{
+	uint8_t time_reg[NUM_ALARM_REGS];
+	int ret;
+	uint8_t val;
+
+	ret = idt1337ag_read_reg(dev, REG_CONTROL, &val);
+
+	if (ret < 0) {
+		return ret;
+	}
+
+	/* Disable alarm interrupt and clear pending alarm flag */
+	val &= ~CONTROL_A1IE;
+	ret = idt1337ag_write_reg(dev, REG_CONTROL, val);
+
+	if (ret < 0) {
+		return ret;
+	}
+
+	/* Clear alarm1 flag if set */
+	ret = idt1337ag_read_reg(dev, REG_STATUS, &val);
+
+	if (ret < 0) {
+		return ret;
+	}
+
+	/* Clear the alarm1 and alarm2 flag */
+	val &= ~(STATUS_A1F | STATUS_A2F);
+	ret = idt1337ag_write_reg(dev, REG_STATUS, val);
+
+	if (ret < 0) {
+		return ret;
+	}
+
+	/* Clear and disable the alarm registers */
+	time_reg[SECONDS] = DISABLE_ALARM;
+	time_reg[MINUTES] = DISABLE_ALARM;
+	time_reg[HOURS] = DISABLE_ALARM;
+	time_reg[DAYS] = DISABLE_ALARM;
+
+	return idt1337ag_write_time_regs(dev, time_reg, ALARM_TIMER);
+}
+
+static int renesas_rtc_idt1337ag_set_alarm(const struct device *dev,
+					   uint32_t seconds,
+					   uint32_t microseconds)
+{
+	int ret;
+	uint8_t val;
+
+	ARG_UNUSED(microseconds);
+
+	ret = renesas_rtc_idt1337ag_reset_alarm(dev);
+	if (ret < 0) {
+		return ret;
+	}
+
+	ret = renesas_rtc_idt1337ag_write_seconds(dev, seconds, ALARM_TIMER);
+	if (ret < 0) {
+		return ret;
+	}
+
+	ret = idt1337ag_read_reg(dev, REG_CONTROL, &val);
+	if (ret < 0) {
+		return ret;
+	}
+
+	val |= CONTROL_A1IE;
+	idt1337ag_write_reg(dev, REG_CONTROL, val);
+
+	return 0;
+}
+
+static void renesas_rtc_idt1337ag_isr(const struct device *port,
+				      struct gpio_callback *cb, uint32_t pin)
+{
+	struct renesas_rtc_idt1337ag_data *data =
+		CONTAINER_OF(cb, struct renesas_rtc_idt1337ag_data, gpio_cb);
+	const struct device *dev = data->dev;
+
+	ARG_UNUSED(port);
+	ARG_UNUSED(pin);
+	ARG_UNUSED(cb);
+
+	LOG_DBG("%s", __func__);
+
+	/* Call callback function */
+	if (data->alarm_callback) {
+		data->alarm_callback(dev);
+	}
+}
+
+static const struct cros_rtc_driver_api renesas_rtc_idt1337ag_driver_api = {
+	.configure = renesas_rtc_idt1337ag_configure,
+	.get_value = renesas_rtc_idt1337ag_get_value,
+	.set_value = renesas_rtc_idt1337ag_set_value,
+	.get_alarm = renesas_rtc_idt1337ag_get_alarm,
+	.set_alarm = renesas_rtc_idt1337ag_set_alarm,
+	.reset_alarm = renesas_rtc_idt1337ag_reset_alarm,
+};
+
+static int renesas_rtc_idt1337ag_init(const struct device *dev)
+{
+	const struct renesas_rtc_idt1337ag_config *const config = dev->config;
+	struct renesas_rtc_idt1337ag_data *data = dev->data;
+	uint8_t val;
+	int ret;
+
+	if (!device_is_ready(config->bus)) {
+		LOG_ERR("Device %s is not ready", config->bus->name);
+		return -ENODEV;
+	}
+
+	/*
+	 * Read Control register. For normal operation,
+	 * the values should be as follows:
+	 *	Bit 7 (enable oscillator) : (0) normal mode
+	 *	Bit 6 (unused)            : (0)
+	 *	Bit 5 (unused)            : (0)
+	 *	BIT 4 (RS2)               : (0) Not used when INTCN == 1
+	 *	BIT 3 (RS1)               : (0) Not used when INTCN == 1
+	 *	BIT 2 (INTCN)             : (1) a match between the timekeeping
+	 *	                                registers and the alarm 1
+	 *	                                registers activate the INTA pin
+	 *	BIT 1 (A2IE)              : (0) Alarm 2 is not used
+	 *	BIT 0 (A1IE)              : (1) Enables Alarm 1
+	 */
+	ret = idt1337ag_read_reg(dev, REG_CONTROL, &val);
+
+	if (ret < 0) {
+		return ret;
+	}
+
+	/* Enable IDT1337AG oscillator */
+	val &= ~CONTROL_EOSC;
+
+	/* Disable Alarm 2 */
+	val &= ~CONTROL_A2IE;
+
+	/* Alarm 1 assert INTA pin */
+	val |= CONTROL_INTCN;
+
+	ret = idt1337ag_write_reg(dev, REG_CONTROL, val);
+
+	if (ret < 0) {
+		return ret;
+	}
+
+	/* Date register isn't used. Set it to zero */
+	ret = idt1337ag_write_reg(dev, REG_DATE, 0);
+
+	/* Make sure the oscillator is running */
+	ret = idt1337ag_read_reg(dev, REG_STATUS, &val);
+
+	if (ret < 0) {
+		return ret;
+	}
+
+	/* Clear IDT1337AG oscillator not running flag */
+	val &= ~STATUS_OSF;
+
+	/* Clear Alarm 2 flag */
+	val &= ~STATUS_A2F;
+
+	ret = idt1337ag_write_reg(dev, REG_STATUS, val);
+
+	if (ret < 0) {
+		return ret;
+	}
+
+	renesas_rtc_idt1337ag_reset_alarm(dev);
+
+	/* Disable Alarm2 */
+	idt1337ag_write_reg(dev, REG_MINUTE_ALARM2, DISABLE_ALARM);
+	idt1337ag_write_reg(dev, REG_HOUR_ALARM2, DISABLE_ALARM);
+	idt1337ag_write_reg(dev, REG_DAY_ALARM2, DISABLE_ALARM);
+
+	/* Configure GPIO interrupt pin for IDT1337AG alarm pin */
+
+	if (!device_is_ready(config->gpio_alert.port)) {
+		LOG_ERR("Alert GPIO device not ready");
+		return -ENODEV;
+	}
+
+	ret = gpio_pin_configure_dt(&config->gpio_alert, GPIO_INPUT);
+
+	if (ret < 0) {
+		LOG_ERR("Could not configure RTC alert pin");
+		return ret;
+	}
+
+	gpio_init_callback(&data->gpio_cb, renesas_rtc_idt1337ag_isr,
+			   BIT(config->gpio_alert.pin));
+
+	ret = gpio_add_callback(config->gpio_alert.port, &data->gpio_cb);
+
+	if (ret < 0) {
+		LOG_ERR("Could not set RTC alert pin callback");
+		return ret;
+	}
+
+	data->dev = dev;
+
+	return gpio_pin_interrupt_configure_dt(&config->gpio_alert,
+					       GPIO_INT_EDGE_FALLING);
+}
+
+#define IDT1337AG_INT_PIN DT_PHANDLE(DT_NODELABEL(idt1337ag), int_pin)
+
+/*
+ * dt_flags is a uint8_t type.  However, for platform/ec
+ * the GPIO flags in the devicetree are expanded past 8 bits
+ * to support the INPUT/OUTPUT and PULLUP/PULLDOWN properties.
+ * Cast back to a gpio_dt_flags to compile, discarding the bits
+ * that are not supported by the Zephyr GPIO API.
+ */
+#define CROS_EC_GPIO_DT_SPEC_GET(node_id, prop)                            \
+	{                                                                  \
+		.port = DEVICE_DT_GET(DT_GPIO_CTLR(node_id, prop)),        \
+		.pin = DT_GPIO_PIN(node_id, prop),                         \
+		.dt_flags = (gpio_dt_flags_t)DT_GPIO_FLAGS(node_id, prop), \
+	}
+
+static const struct renesas_rtc_idt1337ag_config renesas_rtc_idt1337ag_cfg_0 = {
+	.bus = DEVICE_DT_GET(DT_INST_BUS(0)),
+	.i2c_addr_flags = DT_INST_REG_ADDR(0),
+	.gpio_alert = CROS_EC_GPIO_DT_SPEC_GET(IDT1337AG_INT_PIN, gpios)
+};
+
+static struct renesas_rtc_idt1337ag_data renesas_rtc_idt1337ag_data_0;
+
+DEVICE_DT_INST_DEFINE(0, renesas_rtc_idt1337ag_init, /* pm_control_fn= */ NULL,
+		      &renesas_rtc_idt1337ag_data_0,
+		      &renesas_rtc_idt1337ag_cfg_0, POST_KERNEL,
+		      CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
+		      &renesas_rtc_idt1337ag_driver_api);
diff --git a/zephyr/drivers/cros_rtc/renesas_rtc_idt1337ag.h b/zephyr/drivers/cros_rtc/renesas_rtc_idt1337ag.h
new file mode 100644
index 0000000000..9dd195e8c3
--- /dev/null
+++ b/zephyr/drivers/cros_rtc/renesas_rtc_idt1337ag.h
@@ -0,0 +1,60 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_RTC_IDT1337AG_H
+#define __CROS_EC_RTC_IDT1337AG_H
+
+/* Setting bit 6 of register 0Ah selects the DAY as alarm source */
+#define SELECT_DAYS_ALARM 0x40
+#define DISABLE_ALARM 0x80
+
+#define CONTROL_A1IE BIT(0)
+#define CONTROL_A2IE BIT(1)
+#define CONTROL_INTCN BIT(2)
+#define CONTROL_EOSC BIT(7)
+
+#define STATUS_A1F BIT(0)
+#define STATUS_A2F BIT(1)
+#define STATUS_OSF BIT(7)
+
+#define NUM_TIMER_REGS 7
+#define NUM_ALARM_REGS 4
+
+#define REG_SECONDS 0x00
+#define REG_MINUTES 0x01
+#define REG_HOURS 0x02
+#define REG_DAYS 0x03
+#define REG_DATE 0x04
+#define REG_MONTHS 0x05
+#define REG_YEARS 0x06
+#define REG_SECOND_ALARM1 0x07
+#define REG_MINUTE_ALARM1 0x08
+#define REG_HOUR_ALARM1 0x09
+#define REG_DAY_ALARM1 0x0a
+#define REG_MINUTE_ALARM2 0x0b
+#define REG_HOUR_ALARM2 0x0c
+#define REG_DAY_ALARM2 0x0d
+#define REG_CONTROL 0x0e
+#define REG_STATUS 0x0f
+
+/* Macros for indexing time_reg buffer */
+#define SECONDS 0
+#define MINUTES 1
+#define HOURS 2
+#define DAYS 3
+#define DATE 4
+#define MONTHS 5
+#define YEARS 6
+
+enum bcd_mask {
+	SECONDS_MASK = 0x70,
+	MINUTES_MASK = 0x70,
+	HOURS24_MASK = 0x30,
+	DAYS_MASK = 0x00,
+	MONTHS_MASK = 0x10,
+	YEARS_MASK = 0xf0
+};
+
+#endif /* __CROS_EC_RTC_IDT1337AG_H */
diff --git a/zephyr/drivers/cros_shi/CMakeLists.txt b/zephyr/drivers/cros_shi/CMakeLists.txt
new file mode 100644
index 0000000000..c4708f3551
--- /dev/null
+++ b/zephyr/drivers/cros_shi/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+zephyr_library_sources_ifdef(CONFIG_CROS_SHI_IT8XXX2	cros_shi_it8xxx2.c)
+zephyr_library_sources_ifdef(CONFIG_CROS_SHI_NPCX	cros_shi_npcx.c)
diff --git a/zephyr/drivers/cros_shi/Kconfig b/zephyr/drivers/cros_shi/Kconfig
new file mode 100644
index 0000000000..8f9475ea6d
--- /dev/null
+++ b/zephyr/drivers/cros_shi/Kconfig
@@ -0,0 +1,63 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if PLATFORM_EC_HOST_INTERFACE_SHI
+
+config CROS_SHI_NPCX
+	bool
+	default y
+	depends on DT_HAS_NUVOTON_NPCX_SHI_ENABLED
+	help
+	  This option enables Serial Host Interface driver for the NPCX family
+	  of processors. This is used for host-command communication on the
+	  platform which AP is ARM-based SoC.
+
+if CROS_SHI_NPCX
+
+config CROS_SHI_MAX_REQUEST
+	hex "Max data size for the version 3 request packet"
+	default 0x220
+	help
+	  This option indicates maximum data size for a version 3 request
+	  packet. This must be big enough to handle a request header of host
+	  command, flash write offset/size, and 512 bytes of flash data.
+
+config CROS_SHI_MAX_RESPONSE
+	hex "Max data size for the version 3 response packet"
+	default 0x220
+	help
+	  This option indicates maximum data size for a version 3 response
+	  packet. This must be big enough to handle a response header of host
+	  command, flash read offset/size, and 512 bytes of flash data.
+
+config CROS_SHI_NPCX_DEBUG
+	bool "Enable SHI debug"
+	help
+	  print the debug messages for SHI module
+
+endif # CROS_SHI_NPCX
+
+config CROS_SHI_IT8XXX2
+	bool
+	default y
+	depends on DT_HAS_ITE_IT8XXX2_SHI_ENABLED
+	help
+	  This option enables spi host interface driver which is required to
+	  communicate with the EC when the CPU is the ARM processor.
+
+if CROS_SHI_IT8XXX2
+
+config CROS_SHI_IT8XXX2_INIT_PRIORITY
+	int "cros_shi it8xxx2 initialization priority"
+	default 52
+	help
+	  This sets the it8xxx2 cros_shi driver initialization priority.
+	  In the GPIO shim, the alt function of SHI will be configured
+	  as GPIO input pin. So the priority of cros_shi driver must be
+	  lower than CONFIG_PLATFORM_EC_GPIO_INIT_PRIORITY, and
+	  configuration these pins to alt function of SHI.
+
+endif # CROS_SHI_IT8XXX2
+
+endif # PLATFORM_EC_HOST_INTERFACE_SHI
diff --git a/zephyr/drivers/cros_shi/cros_shi_it8xxx2.c b/zephyr/drivers/cros_shi/cros_shi_it8xxx2.c
new file mode 100644
index 0000000000..75d94f49d1
--- /dev/null
+++ b/zephyr/drivers/cros_shi/cros_shi_it8xxx2.c
@@ -0,0 +1,443 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define DT_DRV_COMPAT ite_it8xxx2_shi
+
+#include "chipset.h"
+#include "console.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "system.h"
+
+#include <errno.h>
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/dt-bindings/pinctrl/it8xxx2-pinctrl.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+
+#include <ap_power/ap_power.h>
+#include <soc.h>
+#include <soc_dt.h>
+
+/* Console output macros */
+#define CPRINTS(format, args...) cprints(CC_SPI, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SPI, format, ##args)
+
+LOG_MODULE_REGISTER(cros_shi, LOG_LEVEL_ERR);
+
+#define DRV_CONFIG(dev) ((struct cros_shi_it8xxx2_cfg *const)(dev)->config)
+
+/*
+ * Strcture cros_shi_it8xxx2_cfg is about the setting of SHI,
+ * this config will be used at initial time
+ */
+struct cros_shi_it8xxx2_cfg {
+	/* SHI alternate configuration */
+	const struct pinctrl_dev_config *pcfg;
+};
+
+#define SPI_RX_MAX_FIFO_SIZE 256
+#define SPI_TX_MAX_FIFO_SIZE 256
+
+#define EC_SPI_PREAMBLE_LENGTH 4
+#define EC_SPI_PAST_END_LENGTH 4
+
+/* Max data size for a version 3 request/response packet. */
+#define SPI_MAX_REQUEST_SIZE SPI_RX_MAX_FIFO_SIZE
+#define SPI_MAX_RESPONSE_SIZE \
+	(SPI_TX_MAX_FIFO_SIZE - EC_SPI_PREAMBLE_LENGTH - EC_SPI_PAST_END_LENGTH)
+
+static const uint8_t out_preamble[EC_SPI_PREAMBLE_LENGTH] = {
+	EC_SPI_PROCESSING,
+	EC_SPI_PROCESSING,
+	EC_SPI_PROCESSING,
+	/* This is the byte which matters */
+	EC_SPI_FRAME_START,
+};
+
+/* Store read and write data buffer */
+static uint8_t in_msg[SPI_RX_MAX_FIFO_SIZE] __aligned(4);
+static uint8_t out_msg[SPI_TX_MAX_FIFO_SIZE] __aligned(4);
+
+/* Parameters used by host protocols */
+static struct host_packet spi_packet;
+
+enum shi_state_machine {
+	/* Ready to receive next request */
+	SPI_STATE_READY_TO_RECV,
+	/* Receiving request */
+	SPI_STATE_RECEIVING,
+	/* Processing request */
+	SPI_STATE_PROCESSING,
+	/* Received bad data */
+	SPI_STATE_RX_BAD,
+
+	SPI_STATE_COUNT,
+};
+
+static enum shi_state_machine shi_state;
+
+static const int spi_response_state[] = {
+	[SPI_STATE_READY_TO_RECV] = EC_SPI_RX_READY,
+	[SPI_STATE_RECEIVING] = EC_SPI_RECEIVING,
+	[SPI_STATE_PROCESSING] = EC_SPI_PROCESSING,
+	[SPI_STATE_RX_BAD] = EC_SPI_RX_BAD_DATA,
+};
+BUILD_ASSERT(ARRAY_SIZE(spi_response_state) == SPI_STATE_COUNT);
+
+static void spi_set_state(int state)
+{
+	/* SPI peripheral state machine */
+	shi_state = state;
+	/* Response spi peripheral state */
+	IT83XX_SPI_SPISRDR = spi_response_state[state];
+}
+
+static void reset_rx_fifo(void)
+{
+	/* End Rx FIFO access */
+	IT83XX_SPI_TXRXFAR = 0x00;
+	/* Rx FIFO reset and count monitor reset */
+	IT83XX_SPI_FCR = IT83XX_SPI_RXFR | IT83XX_SPI_RXFCMR;
+}
+
+/* This routine handles spi received unexcepted data */
+static void spi_bad_received_data(int count)
+{
+	/* State machine mismatch, timeout, or protocol we can't handle. */
+	spi_set_state(SPI_STATE_RX_BAD);
+	/* End CPU access Rx FIFO, so it can clock in bytes from AP again. */
+	IT83XX_SPI_TXRXFAR = 0;
+
+	CPRINTS("SPI rx bad data");
+	CPRINTF("in_msg=[");
+	for (int i = 0; i < count; i++)
+		CPRINTF("%02x ", in_msg[i]);
+	CPRINTF("]\n");
+}
+
+static void spi_response_host_data(uint8_t *out_msg_addr, int tx_size)
+{
+	/*
+	 * Protect sequence of filling response packet for host.
+	 * This will ensure CPU access FIFO is disabled at SPI end interrupt no
+	 * matter the interrupt is triggered before or after the sequence.
+	 */
+	unsigned int key = irq_lock();
+
+	if (shi_state == SPI_STATE_PROCESSING) {
+		/* Tx FIFO reset and count monitor reset */
+		IT83XX_SPI_TXFCR = IT83XX_SPI_TXFR | IT83XX_SPI_TXFCMR;
+		/* CPU Tx FIFO1 and FIFO2 access */
+		IT83XX_SPI_TXRXFAR = IT83XX_SPI_CPUTFA;
+
+		for (int i = 0; i < tx_size; i += 4) {
+			/* Write response data from out_msg buffer to Tx FIFO */
+			IT83XX_SPI_CPUWTFDB0 = *(uint32_t *)(out_msg_addr + i);
+		}
+
+		/*
+		 * After writing data to Tx FIFO is finished, this bit will
+		 * be to indicate the SPI peripheral controller.
+		 */
+		IT83XX_SPI_TXFCR = IT83XX_SPI_TXFS;
+		/* End Tx FIFO access */
+		IT83XX_SPI_TXRXFAR = 0;
+		/* SPI peripheral read Tx FIFO */
+		IT83XX_SPI_FCR = IT83XX_SPI_SPISRTXF;
+	}
+
+	irq_unlock(key);
+}
+
+/*
+ * Called to send a response back to the host.
+ *
+ * Some commands can continue for a while. This function is called by
+ * host_command when it completes.
+ *
+ */
+static void spi_send_response_packet(struct host_packet *pkt)
+{
+	int tx_size;
+
+	if (shi_state != SPI_STATE_PROCESSING) {
+		CPRINTS("The request data is not processing.");
+		return;
+	}
+
+	/* Append our past-end byte, which we reserved space for. */
+	for (int i = 0; i < EC_SPI_PAST_END_LENGTH; i++) {
+		((uint8_t *)pkt->response)[pkt->response_size + i] =
+			EC_SPI_PAST_END;
+	}
+
+	tx_size = pkt->response_size + EC_SPI_PREAMBLE_LENGTH +
+		  EC_SPI_PAST_END_LENGTH;
+
+	/* Transmit the reply */
+	spi_response_host_data(out_msg, tx_size);
+}
+
+/* Store request data from Rx FIFO to in_msg buffer */
+static void spi_host_request_data(uint8_t *in_msg_addr, int count)
+{
+	/* CPU Rx FIFO1 access */
+	IT83XX_SPI_TXRXFAR = IT83XX_SPI_CPURXF1A;
+	/*
+	 * In spi_parse_header, the request data will separate to
+	 * write in_msg buffer so we cannot set CPU to end accessing
+	 * Rx FIFO in this function. We will set IT83XX_SPI_TXRXFAR = 0
+	 * in reset_rx_fifo.
+	 */
+
+	for (int i = 0; i < count; i += 4) {
+		/* Get data from master to buffer */
+		*(uint32_t *)(in_msg_addr + i) = IT83XX_SPI_RXFRDRB0;
+	}
+}
+
+/* Parse header for version of spi-protocol */
+static void spi_parse_header(void)
+{
+	struct ec_host_request *r = (struct ec_host_request *)in_msg;
+
+	/* Store request data from Rx FIFO to in_msg buffer */
+	spi_host_request_data(in_msg, sizeof(*r));
+
+	/* Protocol version 3 */
+	if (in_msg[0] == EC_HOST_REQUEST_VERSION) {
+		int pkt_size;
+
+		/* Check how big the packet should be */
+		pkt_size = host_request_expected_size(r);
+
+		if (pkt_size == 0 || pkt_size > sizeof(in_msg)) {
+			spi_bad_received_data(pkt_size);
+			return;
+		}
+
+		/* Store request data from Rx FIFO to in_msg buffer */
+		spi_host_request_data(in_msg + sizeof(*r),
+				      pkt_size - sizeof(*r));
+
+		/* Set up parameters for host request */
+		spi_packet.send_response = spi_send_response_packet;
+		spi_packet.request = in_msg;
+		spi_packet.request_temp = NULL;
+		spi_packet.request_max = sizeof(in_msg);
+		spi_packet.request_size = pkt_size;
+
+		/* Response must start with the preamble */
+		memcpy(out_msg, out_preamble, sizeof(out_preamble));
+
+		spi_packet.response = out_msg + EC_SPI_PREAMBLE_LENGTH;
+		/* Reserve space for frame start and trailing past-end byte */
+		spi_packet.response_max = SPI_MAX_RESPONSE_SIZE;
+		spi_packet.response_size = 0;
+		spi_packet.driver_result = EC_RES_SUCCESS;
+
+		/* Go to common-layer to handle request */
+		host_packet_receive(&spi_packet);
+	} else {
+		/* Invalid version number */
+		CPRINTS("Invalid version number");
+		spi_bad_received_data(1);
+	}
+}
+
+static void shi_ite_int_handler(const void *arg)
+{
+	/*
+	 * The status of SPI end detection interrupt bit is set, it
+	 * means that host command parse has been completed and AP
+	 * has received the last byte which is EC_SPI_PAST_END from
+	 * EC responded data, then AP ended the transaction.
+	 */
+	if (IT83XX_SPI_ISR & IT83XX_SPI_ENDDETECTINT) {
+		/* Disable CPU access Rx FIFO to clock in data from AP again */
+		IT83XX_SPI_TXRXFAR = 0;
+		/* Ready to receive */
+		spi_set_state(SPI_STATE_READY_TO_RECV);
+		/*
+		 * Once there is no SPI active, enable idle task deep
+		 * sleep bit of SPI in S3 or lower.
+		 */
+		enable_sleep(SLEEP_MASK_SPI);
+		/* CS# is deasserted, so write clear all slave status */
+		IT83XX_SPI_ISR = 0xff;
+	}
+	/*
+	 * The status of Rx valid length interrupt bit is set that
+	 * indicates reached target count(IT83XX_SPI_FTCB1R,
+	 * IT83XX_SPI_FTCB0R) and the length field of the host
+	 * requested data.
+	 */
+	if (IT83XX_SPI_RX_VLISR & IT83XX_SPI_RVLI) {
+		/* write clear slave status */
+		IT83XX_SPI_RX_VLISR = IT83XX_SPI_RVLI;
+		/* Move to processing state */
+		spi_set_state(SPI_STATE_PROCESSING);
+		/* Parse header for version of spi-protocol */
+		spi_parse_header();
+	}
+}
+
+void spi_event(enum gpio_signal signal)
+{
+	if (chipset_in_state(CHIPSET_STATE_ON)) {
+		/* Move to processing state */
+		spi_set_state(SPI_STATE_PROCESSING);
+		/* Disable idle task deep sleep bit of SPI in S0. */
+		disable_sleep(SLEEP_MASK_SPI);
+	}
+}
+
+/*
+ * SHI init priority is behind CONFIG_PLATFORM_EC_GPIO_INIT_PRIORITY to
+ * overwrite GPIO_INPUT setting of spi chip select pin.
+ */
+static int cros_shi_ite_init(const struct device *dev)
+{
+	const struct cros_shi_it8xxx2_cfg *const config = DRV_CONFIG(dev);
+	/* Set FIFO data target count */
+	struct ec_host_request cmd_head;
+	int status;
+
+	/*
+	 * Target count means the size of host request.
+	 * And plus extra 4 bytes because the CPU accesses FIFO base on
+	 * word. If host requested data length is one byte, we need to
+	 * align the data length to 4 bytes.
+	 */
+	int target_count = sizeof(cmd_head) + 4;
+	/* Offset of data_len member of host request. */
+	int offset = (char *)&cmd_head.data_len - (char *)&cmd_head;
+
+	IT83XX_SPI_FTCB1R = (target_count >> 8) & 0xff;
+	IT83XX_SPI_FTCB0R = target_count & 0xff;
+	/*
+	 * The register setting can capture the length field of host
+	 * request.
+	 */
+	IT83XX_SPI_TCCB1 = (offset >> 8) & 0xff;
+	IT83XX_SPI_TCCB0 = offset & 0xff;
+
+	/*
+	 * Memory controller configuration register 3.
+	 * bit6 : SPI pin function select (0b:Enable, 1b:Mask)
+	 */
+	IT83XX_GCTRL_MCCR3 |= IT83XX_GCTRL_SPISLVPFE;
+	/* Set unused blocked byte */
+	IT83XX_SPI_HPR2 = 0x00;
+	/* Rx valid length interrupt enabled */
+	IT83XX_SPI_RX_VLISMR &= ~IT83XX_SPI_RVLIM;
+	/*
+	 * General control register2
+	 * bit4 : Rx FIFO2 will not be overwrited once it's full.
+	 * bit3 : Rx FIFO1 will not be overwrited once it's full.
+	 * bit0 : Rx FIFO1/FIFO2 will reset after each CS_N goes high.
+	 */
+	IT83XX_SPI_GCR2 = IT83XX_SPI_RXF2OC | IT83XX_SPI_RXF1OC |
+			  IT83XX_SPI_RXFAR;
+	/*
+	 * Interrupt mask register (0b:Enable, 1b:Mask)
+	 * bit5 : Rx byte reach interrupt mask
+	 * bit2 : SPI end detection interrupt mask
+	 */
+	IT83XX_SPI_IMR &= ~IT83XX_SPI_EDIM;
+	/* Reset fifo and prepare to for next transaction */
+	reset_rx_fifo();
+	/* Ready to receive */
+	spi_set_state(SPI_STATE_READY_TO_RECV);
+	/* Interrupt status register(write one to clear) */
+	IT83XX_SPI_ISR = 0xff;
+	/* SPI peripheral controller enable (after settings are ready) */
+	IT83XX_SPI_SPISGCR = IT83XX_SPI_SPISCEN;
+
+	/* Set the pin to SHI alternate function. */
+	status = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
+	if (status < 0) {
+		LOG_ERR("Failed to configure SHI pins");
+		return status;
+	}
+
+	/* Enable SPI peripheral interrupt */
+	IRQ_CONNECT(DT_INST_IRQN(0), 0, shi_ite_int_handler, 0, 0);
+	irq_enable(DT_INST_IRQN(0));
+
+	/* Enable SPI chip select pin interrupt */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_spi0_cs));
+
+	return 0;
+}
+
+static void shi_disable(void)
+{
+	/* Enable sleep mask of SHI to enter deep sleep of power plicy. */
+	enable_sleep(SLEEP_MASK_SPI);
+}
+
+static void shi_power_shutdown_handler(struct ap_power_ev_callback *cb,
+				       struct ap_power_ev_data data)
+{
+	switch (data.event) {
+	case AP_POWER_SHUTDOWN_COMPLETE:
+		/* Disable SHI bus */
+		shi_disable();
+		break;
+	default:
+		__ASSERT(false, "%s: unhandled event: %d", __func__,
+			 data.event);
+		break;
+	}
+}
+
+static void install_power_change_handler(void)
+{
+	static struct ap_power_ev_callback cb;
+
+	/* Add a callback of power shutdown complete to enable sleep mask. */
+	ap_power_ev_init_callback(&cb, shi_power_shutdown_handler,
+				  AP_POWER_SHUTDOWN_COMPLETE);
+	ap_power_ev_add_callback(&cb);
+}
+/* Call hook after chipset sets initial power state */
+DECLARE_HOOK(HOOK_INIT, install_power_change_handler, HOOK_PRIO_POST_CHIPSET);
+
+PINCTRL_DT_INST_DEFINE(0);
+
+static const struct cros_shi_it8xxx2_cfg cros_shi_cfg = {
+	.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
+};
+
+#if CONFIG_CROS_SHI_IT8XXX2_INIT_PRIORITY <= \
+	CONFIG_PLATFORM_EC_GPIO_INIT_PRIORITY
+#error "CROS_SHI must initialize after the GPIOs initialization"
+#endif
+DEVICE_DT_INST_DEFINE(0, cros_shi_ite_init, NULL, NULL, &cros_shi_cfg,
+		      POST_KERNEL, CONFIG_CROS_SHI_IT8XXX2_INIT_PRIORITY, NULL);
+
+/* Get protocol information */
+enum ec_status spi_get_protocol_info(struct host_cmd_handler_args *args)
+{
+	struct ec_response_get_protocol_info *r = args->response;
+
+	memset(r, 0, sizeof(*r));
+	r->protocol_versions = BIT(3);
+	r->max_request_packet_size = SPI_MAX_REQUEST_SIZE;
+	r->max_response_packet_size = SPI_MAX_RESPONSE_SIZE;
+	r->flags = EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED;
+
+	args->response_size = sizeof(*r);
+
+	return EC_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, spi_get_protocol_info,
+		     EC_VER_MASK(0));
diff --git a/zephyr/drivers/cros_shi/cros_shi_npcx.c b/zephyr/drivers/cros_shi/cros_shi_npcx.c
new file mode 100644
index 0000000000..39485ecced
--- /dev/null
+++ b/zephyr/drivers/cros_shi/cros_shi_npcx.c
@@ -0,0 +1,927 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define DT_DRV_COMPAT nuvoton_npcx_shi
+
+#include "host_command.h"
+#include "soc_miwu.h"
+#include "system.h"
+
+#include <assert.h>
+
+#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/dt-bindings/clock/npcx_clock.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+
+#include <drivers/cros_shi.h>
+#include <soc.h>
+#include <soc/nuvoton_npcx/reg_def_cros.h>
+
+#ifdef CONFIG_CROS_SHI_NPCX_DEBUG
+#define DEBUG_CPRINTS(format, args...) cprints(CC_SPI, format, ##args)
+#define DEBUG_CPRINTF(format, args...) cprintf(CC_SPI, format, ##args)
+#else
+#define DEBUG_CPRINTS(...)
+#define DEBUG_CPRINTF(...)
+#endif
+
+LOG_MODULE_REGISTER(cros_shi, LOG_LEVEL_DBG);
+
+#define SHI_NODE DT_NODELABEL(shi0)
+#define SHI_VER_CTRL_PH DT_PHANDLE_BY_IDX(SHI_NODE, ver_ctrl, 0)
+#define SHI_VER_CTRL_ALT_FILED(f) DT_PHA_BY_IDX(SHI_VER_CTRL_PH, alts, 0, f)
+
+/* Full output buffer size */
+#define SHI_OBUF_FULL_SIZE 128
+/* Full input buffer size  */
+#define SHI_IBUF_FULL_SIZE 128
+/* Configure the IBUFLVL2 = the size of V3 protocol header */
+#define SHI_IBUFLVL2_THRESHOLD (sizeof(struct ec_host_request))
+/* Half output buffer size */
+#define SHI_OBUF_HALF_SIZE (SHI_OBUF_FULL_SIZE / 2)
+/* Half input buffer size */
+#define SHI_IBUF_HALF_SIZE (SHI_IBUF_FULL_SIZE / 2)
+
+/*
+ * Timeout to wait for SHI request packet
+ *
+ * This affects the slowest SPI clock we can support. A delay of 8192 us
+ * permits a 512-byte request at 500 KHz, assuming the SPI controller starts
+ * sending bytes as soon as it asserts chip select. That's as slow as we would
+ * practically want to run the SHI interface, since running it slower
+ * significantly impacts firmware update times.
+ */
+#define SHI_CMD_RX_TIMEOUT_US 8192
+
+/*
+ * The AP blindly clocks back bytes over the SPI interface looking for a
+ * framing byte.  So this preamble must always precede the actual response
+ * packet.
+ */
+#define SHI_OUT_PREAMBLE_LENGTH 2
+
+/*
+ * Space allocation of the past-end status byte (EC_SPI_PAST_END) in the out_msg
+ * buffer.
+ */
+#define EC_SPI_PAST_END_LENGTH 1
+/*
+ * Space allocation of the frame status byte (EC_SPI_FRAME_START) in the out_msg
+ * buffer.
+ */
+#define EC_SPI_FRAME_START_LENGTH 1
+
+/*
+ * Offset of output parameters needs to account for pad and framing bytes and
+ * one last past-end byte at the end so any additional bytes clocked out by
+ * the AP will have a known and identifiable value.
+ */
+#define SHI_PROTO3_OVERHEAD (EC_SPI_PAST_END_LENGTH + EC_SPI_FRAME_START_LENGTH)
+
+/*
+ * Max data size for a version 3 request/response packet.  This is big enough
+ * to handle a request/response header, flash write offset/size, and 512 bytes
+ * of flash data:
+ *  sizeof(ec_host_request):          8
+ *  sizeof(ec_params_flash_write):    8
+ *  payload                         512
+ */
+#define SHI_MAX_REQUEST_SIZE CONFIG_CROS_SHI_MAX_REQUEST
+#define SHI_MAX_RESPONSE_SIZE CONFIG_CROS_SHI_MAX_RESPONSE
+
+/*
+ * Our input and output msg buffers. These must be large enough for our largest
+ * message, including protocol overhead.  The pointers after the protocol
+ * overhead, as passed to the host command handler, must be 32-bit aligned.
+ */
+#define SHI_OUT_START_PAD (4 * (EC_SPI_FRAME_START_LENGTH / 4 + 1))
+#define SHI_OUT_END_PAD (4 * (EC_SPI_PAST_END_LENGTH / 4 + 1))
+static uint8_t out_msg_padded[SHI_OUT_START_PAD + SHI_MAX_RESPONSE_SIZE +
+			      SHI_OUT_END_PAD] __aligned(4);
+static uint8_t *const out_msg =
+	out_msg_padded + SHI_OUT_START_PAD - EC_SPI_FRAME_START_LENGTH;
+static uint8_t in_msg[SHI_MAX_REQUEST_SIZE] __aligned(4);
+
+/* Parameters used by host protocols */
+static struct host_packet shi_packet;
+
+enum cros_shi_npcx_state {
+	SHI_STATE_NONE = -1,
+	/* SHI not enabled (initial state, and when chipset is off) */
+	SHI_STATE_DISABLED = 0,
+	/* Ready to receive next request */
+	SHI_STATE_READY_TO_RECV,
+	/* Receiving request */
+	SHI_STATE_RECEIVING,
+	/* Processing request */
+	SHI_STATE_PROCESSING,
+	/* Canceling response since CS deasserted and output NOT_READY byte */
+	SHI_STATE_CNL_RESP_NOT_RDY,
+	/* Sending response */
+	SHI_STATE_SENDING,
+	/* Received data is invalid */
+	SHI_STATE_BAD_RECEIVED_DATA,
+};
+
+static enum cros_shi_npcx_state state;
+
+/* Device config */
+struct cros_shi_npcx_config {
+	/* Serial Host Interface (SHI) base address */
+	uintptr_t base;
+	/* clock configuration */
+	struct npcx_clk_cfg clk_cfg;
+	/* Pin control configuration */
+	const struct pinctrl_dev_config *pcfg;
+	/* SHI IRQ */
+	int irq;
+	struct npcx_wui shi_cs_wui;
+};
+
+/* SHI bus parameters */
+struct shi_bus_parameters {
+	uint8_t *rx_msg; /* Entry pointer of msg rx buffer   */
+	uint8_t *tx_msg; /* Entry pointer of msg tx buffer   */
+	volatile uint8_t *rx_buf; /* Entry pointer of receive buffer  */
+	volatile uint8_t *tx_buf; /* Entry pointer of transmit buffer */
+	uint16_t sz_received; /* Size of received data in bytes   */
+	uint16_t sz_sending; /* Size of sending data in bytes    */
+	uint16_t sz_request; /* request bytes need to receive    */
+	uint16_t sz_response; /* response bytes need to receive   */
+	uint64_t rx_deadline; /* deadline of receiving            */
+} shi_params;
+
+PINCTRL_DT_INST_DEFINE(0);
+
+static const struct cros_shi_npcx_config cros_shi_cfg = {
+	.base = DT_INST_REG_ADDR(0),
+	.clk_cfg = NPCX_DT_CLK_CFG_ITEM(0),
+	.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
+	.irq = DT_INST_IRQN(0),
+	.shi_cs_wui = NPCX_DT_WUI_ITEM_BY_NAME(0, shi_cs_wui),
+};
+
+struct cros_shi_npcx_data {
+	struct host_packet shi_packet;
+	sys_slist_t callbacks;
+};
+
+/* Driver convenience defines */
+#define DRV_CONFIG(dev) ((const struct cros_shi_npcx_config *)(dev)->config)
+#define DRV_DATA(dev) ((struct cros_shi_npcx_data *)(dev)->data)
+#define HAL_INSTANCE(dev) (struct shi_reg *)(DRV_CONFIG(dev)->base)
+
+/* Forward declaration */
+static void cros_shi_npcx_reset_prepare(struct shi_reg *const inst);
+
+/* Read pointer of input or output buffer by consecutive reading */
+static uint32_t shi_read_buf_pointer(struct shi_reg *const inst)
+{
+	uint8_t stat;
+
+	/* Wait for two consecutive equal values are read */
+	do {
+		stat = inst->IBUFSTAT;
+	} while (stat != inst->IBUFSTAT);
+
+	return (uint32_t)stat;
+}
+
+/*
+ * Valid offset of SHI output buffer to write.
+ * When SIMUL bit is set, IBUFPTR can be used instead of OBUFPTR
+ */
+static uint32_t shi_valid_obuf_offset(struct shi_reg *const inst)
+{
+	return (shi_read_buf_pointer(inst) + SHI_OUT_PREAMBLE_LENGTH) %
+	       SHI_OBUF_FULL_SIZE;
+}
+
+/*
+ * This routine write SHI next half output buffer from msg buffer
+ */
+static void shi_write_half_outbuf(void)
+{
+	const uint32_t size =
+		MIN(SHI_OBUF_HALF_SIZE,
+		    shi_params.sz_response - shi_params.sz_sending);
+	uint8_t *obuf_ptr = (uint8_t *)shi_params.tx_buf;
+	const uint8_t *obuf_end = obuf_ptr + size;
+	uint8_t *msg_ptr = shi_params.tx_msg;
+
+	/* Fill half output buffer */
+	while (obuf_ptr != obuf_end)
+		*obuf_ptr++ = *msg_ptr++;
+
+	shi_params.sz_sending += size;
+	shi_params.tx_buf = obuf_ptr;
+	shi_params.tx_msg = msg_ptr;
+}
+
+/*
+ * This routine read SHI input buffer to msg buffer until
+ * we have received a certain number of bytes
+ */
+static int shi_read_inbuf_wait(struct shi_reg *const inst, uint32_t szbytes)
+{
+	/* Copy data to msg buffer from input buffer */
+	for (uint32_t i = 0; i < szbytes; i++, shi_params.sz_received++) {
+		/*
+		 * If input buffer pointer equals pointer which wants to read,
+		 * it means data is not ready.
+		 */
+		while (shi_params.rx_buf ==
+		       inst->IBUF + shi_read_buf_pointer(inst)) {
+			if (k_cycle_get_64() >= shi_params.rx_deadline) {
+				return 0;
+			}
+		}
+		/* Restore data to msg buffer */
+		*shi_params.rx_msg++ = *shi_params.rx_buf++;
+	}
+	return 1;
+}
+
+/* This routine fills out all SHI output buffer with status byte */
+static void shi_fill_out_status(struct shi_reg *const inst, uint8_t status)
+{
+	uint8_t start, end;
+	volatile uint8_t *fill_ptr;
+	volatile uint8_t *fill_end;
+	volatile uint8_t *obuf_end;
+
+	/*
+	 * Disable interrupts in case the interfere by the other interrupts.
+	 * Use __disable_irq/__enable_irq instead of using irq_lock/irq_unlock
+	 * here because irq_lock/irq_unlock leave some system exceptions (like
+	 * SVC, NMI, and faults) still enabled.
+	 */
+	__disable_irq();
+
+	/*
+	 * Fill out output buffer with status byte and leave a gap for PREAMBLE.
+	 * The gap guarantees the synchronization. The critical section should
+	 * be done within this gap. No racing happens.
+	 */
+	start = shi_valid_obuf_offset(inst);
+	end = (start + SHI_OBUF_FULL_SIZE - SHI_OUT_PREAMBLE_LENGTH) %
+	      SHI_OBUF_FULL_SIZE;
+
+	fill_ptr = inst->OBUF + start;
+	fill_end = inst->OBUF + end;
+	obuf_end = inst->OBUF + SHI_OBUF_FULL_SIZE;
+	while (fill_ptr != fill_end) {
+		*fill_ptr++ = status;
+		if (fill_ptr == obuf_end)
+			fill_ptr = inst->OBUF;
+	}
+
+	/* End of critical section */
+	__enable_irq();
+}
+
+/* This routine handles shi received unexpected data */
+static void shi_bad_received_data(struct shi_reg *const inst)
+{
+	/* State machine mismatch, timeout, or protocol we can't handle. */
+	shi_fill_out_status(inst, EC_SPI_RX_BAD_DATA);
+	state = SHI_STATE_BAD_RECEIVED_DATA;
+
+	DEBUG_CPRINTF("BAD-");
+	DEBUG_CPRINTF("in_msg=[");
+	for (uint32_t i = 0; i < shi_params.sz_received; i++)
+		DEBUG_CPRINTF("%02x ", in_msg[i]);
+	DEBUG_CPRINTF("]\n");
+
+	/* Reset shi's state machine for error recovery */
+	cros_shi_npcx_reset_prepare(inst);
+
+	DEBUG_CPRINTF("END\n");
+}
+
+/*
+ * This routine write SHI output buffer from msg buffer over halt of it.
+ * It make sure we have enough time to handle next operations.
+ */
+static void shi_write_first_pkg_outbuf(struct shi_reg *const inst,
+				       uint16_t szbytes)
+{
+	uint8_t size, offset;
+	volatile uint8_t *obuf_ptr;
+	volatile uint8_t *obuf_end;
+	uint8_t *msg_ptr;
+	uint32_t half_buf_remain; /* Remains in half buffer are free to write */
+
+	/* Start writing at our current OBUF position */
+	offset = shi_valid_obuf_offset(inst);
+	obuf_ptr = inst->OBUF + offset;
+	msg_ptr = shi_params.tx_msg;
+
+	/* Fill up to OBUF mid point, or OBUF end */
+	half_buf_remain = SHI_OBUF_HALF_SIZE - (offset % SHI_OBUF_HALF_SIZE);
+	size = MIN(half_buf_remain, szbytes - shi_params.sz_sending);
+	obuf_end = obuf_ptr + size;
+	while (obuf_ptr != obuf_end)
+		*obuf_ptr++ = *msg_ptr++;
+
+	/* Track bytes sent for later accounting */
+	shi_params.sz_sending += size;
+
+	/* Write data to beginning of OBUF if we've reached the end */
+	if (obuf_ptr == inst->OBUF + SHI_IBUF_FULL_SIZE)
+		obuf_ptr = inst->OBUF;
+
+	/* Fill next half output buffer */
+	size = MIN(SHI_OBUF_HALF_SIZE, szbytes - shi_params.sz_sending);
+	obuf_end = obuf_ptr + size;
+	while (obuf_ptr != obuf_end)
+		*obuf_ptr++ = *msg_ptr++;
+
+	/* Track bytes sent / last OBUF position written for later accounting */
+	shi_params.sz_sending += size;
+	shi_params.tx_buf = obuf_ptr;
+	shi_params.tx_msg = msg_ptr;
+}
+
+/**
+ * Called to send a response back to the host.
+ *
+ * Some commands can continue for a while. This function is called by
+ * host_command task after processing request is completed. It fills up the
+ * FIFOs with response package and the remaining data is handled in shi's ISR.
+ */
+static void shi_send_response_packet(struct host_packet *pkt)
+{
+	struct shi_reg *const inst = (struct shi_reg *)(cros_shi_cfg.base);
+
+	/*
+	 * Disable interrupts. This routine is not called from interrupt
+	 * context and buffer underrun will likely occur if it is
+	 * preempted after writing its initial reply byte. Also, we must be
+	 * sure our state doesn't unexpectedly change, in case we're expected
+	 * to take RESP_NOT_RDY actions.
+	 */
+	__disable_irq();
+
+	if (state == SHI_STATE_PROCESSING) {
+		/* Append our past-end byte, which we reserved space for. */
+		((uint8_t *)pkt->response)[pkt->response_size] =
+			EC_SPI_PAST_END;
+
+		/* Computing sending bytes of response */
+		shi_params.sz_response =
+			pkt->response_size + SHI_PROTO3_OVERHEAD;
+
+		/* Start to fill output buffer with msg buffer */
+		shi_write_first_pkg_outbuf(inst, shi_params.sz_response);
+		/* Transmit the reply */
+		state = SHI_STATE_SENDING;
+		DEBUG_CPRINTF("SND-");
+	} else if (state == SHI_STATE_CNL_RESP_NOT_RDY) {
+		/*
+		 * If we're not processing, then the AP has already terminated
+		 * the transaction, and won't be listening for a response.
+		 * Reset state machine for next transaction.
+		 */
+		cros_shi_npcx_reset_prepare(inst);
+		DEBUG_CPRINTF("END\n");
+	} else
+		DEBUG_CPRINTS("Unexpected state %d in response handler", state);
+
+	__enable_irq();
+}
+
+void shi_handle_host_package(struct shi_reg *const inst)
+{
+	uint32_t sz_inbuf_int = shi_params.sz_request / SHI_IBUF_HALF_SIZE;
+	uint32_t cnt_inbuf_int = shi_params.sz_received / SHI_IBUF_HALF_SIZE;
+
+	if (sz_inbuf_int - cnt_inbuf_int)
+		/* Need to receive data from buffer */
+		return;
+	uint32_t remain_bytes = shi_params.sz_request - shi_params.sz_received;
+
+	/* Read remaining bytes from input buffer */
+	if (!shi_read_inbuf_wait(inst, remain_bytes))
+		return shi_bad_received_data(inst);
+
+	/* Move to processing state */
+	state = SHI_STATE_PROCESSING;
+	DEBUG_CPRINTF("PRC-");
+
+	/* Fill output buffer to indicate we`re processing request */
+	shi_fill_out_status(inst, EC_SPI_PROCESSING);
+
+	/* Set up parameters for host request */
+	shi_packet.send_response = shi_send_response_packet;
+
+	shi_packet.request = in_msg;
+	shi_packet.request_temp = NULL;
+	shi_packet.request_max = sizeof(in_msg);
+	shi_packet.request_size = shi_params.sz_request;
+
+	/* Put FRAME_START in first byte */
+	out_msg[0] = EC_SPI_FRAME_START;
+	shi_packet.response = out_msg + EC_SPI_FRAME_START_LENGTH;
+
+	/* Reserve space for frame start and trailing past-end byte */
+	shi_packet.response_max = SHI_MAX_RESPONSE_SIZE;
+	shi_packet.response_size = 0;
+	shi_packet.driver_result = EC_RES_SUCCESS;
+
+	/* Go to common layer to handle request */
+	host_packet_receive(&shi_packet);
+}
+
+static void shi_parse_header(struct shi_reg *const inst)
+{
+	/* We're now inside a transaction */
+	state = SHI_STATE_RECEIVING;
+	DEBUG_CPRINTF("RV-");
+
+	/* Setup deadline time for receiving */
+	shi_params.rx_deadline =
+		k_cycle_get_64() + k_us_to_cyc_near64(SHI_CMD_RX_TIMEOUT_US);
+
+	/* Wait for version, command, length bytes */
+	if (!shi_read_inbuf_wait(inst, 3))
+		return shi_bad_received_data(inst);
+
+	if (in_msg[0] == EC_HOST_REQUEST_VERSION) {
+		/* Protocol version 3 */
+		struct ec_host_request *r = (struct ec_host_request *)in_msg;
+		int pkt_size;
+		/*
+		 * If request is over half of input buffer,
+		 * we need to modified the algorithm again.
+		 */
+		__ASSERT_NO_MSG(sizeof(*r) < SHI_IBUF_HALF_SIZE);
+
+		/* Wait for the rest of the command header */
+		if (!shi_read_inbuf_wait(inst, sizeof(*r) - 3))
+			return shi_bad_received_data(inst);
+
+		/* Check how big the packet should be */
+		pkt_size = host_request_expected_size(r);
+		if (pkt_size == 0 || pkt_size > sizeof(in_msg))
+			return shi_bad_received_data(inst);
+
+		/* Computing total bytes need to receive */
+		shi_params.sz_request = pkt_size;
+
+		shi_handle_host_package(inst);
+	} else {
+		/* Invalid version number */
+		return shi_bad_received_data(inst);
+	}
+}
+
+static void shi_sec_ibf_int_enable(struct shi_reg *const inst, int enable)
+{
+	if (enable) {
+		/* Setup IBUFLVL2 threshold and enable it */
+		inst->SHICFG5 |= BIT(NPCX_SHICFG5_IBUFLVL2DIS);
+		SET_FIELD(inst->SHICFG5, NPCX_SHICFG5_IBUFLVL2,
+			  SHI_IBUFLVL2_THRESHOLD);
+		inst->SHICFG5 &= ~BIT(NPCX_SHICFG5_IBUFLVL2DIS);
+		/* Enable IBHF2 event */
+		inst->EVENABLE2 |= BIT(NPCX_EVENABLE2_IBHF2EN);
+	} else {
+		/* Disable IBHF2 event first */
+		inst->EVENABLE2 &= ~BIT(NPCX_EVENABLE2_IBHF2EN);
+		/* Disable IBUFLVL2 and set threshold back to zero */
+		inst->SHICFG5 |= BIT(NPCX_SHICFG5_IBUFLVL2DIS);
+		SET_FIELD(inst->SHICFG5, NPCX_SHICFG5_IBUFLVL2, 0);
+	}
+}
+
+/* This routine copies SHI half input buffer data to msg buffer */
+static void shi_read_half_inbuf(void)
+{
+	/*
+	 * Copy to read buffer until reaching middle/top address of
+	 * input buffer or completing receiving data
+	 */
+	do {
+		/* Restore data to msg buffer */
+		*shi_params.rx_msg++ = *shi_params.rx_buf++;
+		shi_params.sz_received++;
+	} while (shi_params.sz_received % SHI_IBUF_HALF_SIZE &&
+		 shi_params.sz_received != shi_params.sz_request);
+}
+
+/*
+ * Avoid spamming the console with prints every IBF / IBHF interrupt, if
+ * we find ourselves in an unexpected state.
+ */
+static enum cros_shi_npcx_state last_error_state = SHI_STATE_NONE;
+
+static void log_unexpected_state(char *isr_name)
+{
+	if (state != last_error_state)
+		DEBUG_CPRINTF("Unexpected state %d in %s ISR", state, isr_name);
+	last_error_state = state;
+}
+
+static void shi_handle_cs_assert(struct shi_reg *const inst)
+{
+	/* If not enabled, ignore glitches on SHI_CS_L */
+	if (state == SHI_STATE_DISABLED)
+		return;
+
+	/* NOT_READY should be sent and there're no spi transaction now. */
+	if (state == SHI_STATE_CNL_RESP_NOT_RDY)
+		return;
+
+	/* Chip select is low = asserted */
+	if (state != SHI_STATE_READY_TO_RECV) {
+		/* State machine should be reset in EVSTAT_EOR ISR */
+		DEBUG_CPRINTF("Unexpected state %d in CS ISR", state);
+		return;
+	}
+
+	DEBUG_CPRINTF("CSL-");
+
+	/*
+	 * Clear possible EOR event from previous transaction since it's
+	 * irrelevant now that CS is re-asserted.
+	 */
+	inst->EVSTAT = BIT(NPCX_EVSTAT_EOR);
+
+	/* Do not deep sleep during SHI transaction */
+	disable_sleep(SLEEP_MASK_SPI);
+}
+
+static void shi_handle_cs_deassert(struct shi_reg *const inst)
+{
+	/*
+	 * If the buffer is still used by the host command.
+	 * Change state machine for response handler.
+	 */
+	if (state == SHI_STATE_PROCESSING) {
+		/*
+		 * Mark not ready to prevent the other
+		 * transaction immediately
+		 */
+		shi_fill_out_status(inst, EC_SPI_NOT_READY);
+
+		state = SHI_STATE_CNL_RESP_NOT_RDY;
+
+		/*
+		 * Disable SHI interrupt, it will remain disabled
+		 * until shi_send_response_packet() is called and
+		 * CS is asserted for a new transaction.
+		 */
+		irq_disable(DT_INST_IRQN(0));
+
+		DEBUG_CPRINTF("CNL-");
+		return;
+		/* Next transaction but we're not ready */
+	} else if (state == SHI_STATE_CNL_RESP_NOT_RDY) {
+		return;
+	}
+
+	/* Error state for checking*/
+	if (state != SHI_STATE_SENDING) {
+		log_unexpected_state("CSNRE");
+	}
+	/* reset SHI and prepare to next transaction again */
+	cros_shi_npcx_reset_prepare(inst);
+	DEBUG_CPRINTF("END\n");
+}
+
+static void shi_handle_input_buf_half_full(struct shi_reg *const inst)
+{
+	if (state == SHI_STATE_RECEIVING) {
+		/* Read data from input to msg buffer */
+		shi_read_half_inbuf();
+		return shi_handle_host_package(inst);
+	} else if (state == SHI_STATE_SENDING) {
+		/* Write data from msg buffer to output buffer */
+		if (shi_params.tx_buf == inst->OBUF + SHI_OBUF_FULL_SIZE) {
+			/* Write data from bottom address again */
+			shi_params.tx_buf = inst->OBUF;
+			return shi_write_half_outbuf();
+		} else /* ignore it */
+			return;
+	} else if (state == SHI_STATE_PROCESSING) {
+		/* Wait for host to handle request */
+	} else {
+		/* Unexpected status */
+		log_unexpected_state("IBHF");
+	}
+}
+
+static void shi_handle_input_buf_full(struct shi_reg *const inst)
+{
+	if (state == SHI_STATE_RECEIVING) {
+		/* read data from input to msg buffer */
+		shi_read_half_inbuf();
+		/* Read to bottom address again */
+		shi_params.rx_buf = inst->IBUF;
+		return shi_handle_host_package(inst);
+	} else if (state == SHI_STATE_SENDING) {
+		/* Write data from msg buffer to output buffer */
+		if (shi_params.tx_buf == inst->OBUF + SHI_OBUF_HALF_SIZE)
+			return shi_write_half_outbuf();
+		else /* ignore it */
+			return;
+	} else if (state == SHI_STATE_PROCESSING) {
+		/* Wait for host to handle request */
+		return;
+	}
+	/* Unexpected status */
+	log_unexpected_state("IBF");
+}
+
+static void cros_shi_npcx_isr(const struct device *dev)
+{
+	uint8_t stat;
+	uint8_t stat2;
+	struct shi_reg *const inst = HAL_INSTANCE(dev);
+
+	/* Read status register and clear interrupt status early */
+	stat = inst->EVSTAT;
+	inst->EVSTAT = stat;
+	stat2 = inst->EVSTAT2;
+
+	/* SHI CS pin is asserted in EVSTAT2 */
+	if (IS_BIT_SET(stat2, NPCX_EVSTAT2_CSNFE)) {
+		/* Clear pending bit of CSNFE */
+		inst->EVSTAT2 = BIT(NPCX_EVSTAT2_CSNFE);
+		DEBUG_CPRINTF("CSNFE-");
+		/*
+		 * BUSY bit is set when SHI_CS is asserted. If not, leave it for
+		 * SHI_CS de-asserted event.
+		 */
+		if (!IS_BIT_SET(inst->SHICFG2, NPCX_SHICFG2_BUSY)) {
+			DEBUG_CPRINTF("CSNB-");
+			return;
+		}
+		shi_handle_cs_assert(inst);
+	}
+
+	/*
+	 * End of data for read/write transaction. i.e. SHI_CS is deasserted.
+	 * Host completed or aborted transaction
+	 *
+	 * EOR has the limitation that it will not be set even if the SHI_CS is
+	 * deasserted without SPI clocks. The new SHI module introduce the
+	 * CSNRE bit which will be set when SHI_CS is deasserted regardless of
+	 * SPI clocks.
+	 */
+	if (IS_BIT_SET(stat2, NPCX_EVSTAT2_CSNRE)) {
+		/* Clear pending bit of CSNRE */
+		inst->EVSTAT2 = BIT(NPCX_EVSTAT2_CSNRE);
+		/*
+		 * We're not in proper state.
+		 * Mark not ready to abort next transaction
+		 */
+		DEBUG_CPRINTF("CSH-");
+		return shi_handle_cs_deassert(inst);
+	}
+
+	/*
+	 * The number of bytes received reaches the size of
+	 * protocol V3 header(=8) after CS asserted.
+	 */
+	if (IS_BIT_SET(stat2, NPCX_EVSTAT2_IBHF2)) {
+		/* Clear IBHF2 */
+		inst->EVSTAT2 = BIT(NPCX_EVSTAT2_IBHF2);
+		DEBUG_CPRINTF("HDR-");
+		/* Disable second IBF interrupt and start to parse header */
+		shi_sec_ibf_int_enable(inst, 0);
+		shi_parse_header(inst);
+	}
+
+	/*
+	 * Indicate input/output buffer pointer reaches the half buffer size.
+	 * Transaction is processing.
+	 */
+	if (IS_BIT_SET(stat, NPCX_EVSTAT_IBHF)) {
+		return shi_handle_input_buf_half_full(inst);
+	}
+
+	/*
+	 * Indicate input/output buffer pointer reaches the full buffer size.
+	 * Transaction is processing.
+	 */
+	if (IS_BIT_SET(stat, NPCX_EVSTAT_IBF)) {
+		return shi_handle_input_buf_full(inst);
+	}
+}
+
+static void cros_shi_npcx_reset_prepare(struct shi_reg *const inst)
+{
+	uint32_t i;
+
+	state = SHI_STATE_DISABLED;
+
+	irq_disable(DT_INST_IRQN(0));
+
+	/* Disable SHI unit to clear all status bits */
+	inst->SHICFG1 &= ~BIT(NPCX_SHICFG1_EN);
+
+	/* Initialize parameters of next transaction */
+	shi_params.rx_msg = in_msg;
+	shi_params.tx_msg = out_msg;
+	shi_params.rx_buf = inst->IBUF;
+	shi_params.tx_buf = inst->IBUF + SHI_OBUF_HALF_SIZE;
+	shi_params.sz_received = 0;
+	shi_params.sz_sending = 0;
+	shi_params.sz_request = 0;
+	shi_params.sz_response = 0;
+
+	/*
+	 * Fill output buffer to indicate we`re
+	 * ready to receive next transaction.
+	 */
+	for (i = 1; i < SHI_OBUF_FULL_SIZE; i++)
+		inst->OBUF[i] = EC_SPI_RECEIVING;
+	inst->OBUF[0] = EC_SPI_RX_READY;
+
+	/* SHI/Host Write/input buffer wrap-around enable */
+	inst->SHICFG1 = BIT(NPCX_SHICFG1_IWRAP) | BIT(NPCX_SHICFG1_WEN) |
+			BIT(NPCX_SHICFG1_EN);
+
+	state = SHI_STATE_READY_TO_RECV;
+	last_error_state = SHI_STATE_NONE;
+
+	shi_sec_ibf_int_enable(inst, 1);
+	irq_enable(DT_INST_IRQN(0));
+
+	/* Allow deep sleep at the end of SHI transaction */
+	enable_sleep(SLEEP_MASK_SPI);
+
+	DEBUG_CPRINTF("RDY-");
+}
+
+static int cros_shi_npcx_enable(const struct device *dev)
+{
+	const struct cros_shi_npcx_config *const config = DRV_CONFIG(dev);
+	const struct device *clk_dev = DEVICE_DT_GET(NPCX_CLK_CTRL_NODE);
+	struct shi_reg *const inst = HAL_INSTANCE(dev);
+	int ret;
+
+	ret = clock_control_on(clk_dev,
+			       (clock_control_subsys_t *)&config->clk_cfg);
+	if (ret < 0) {
+		DEBUG_CPRINTF("Turn on SHI clock fail %d", ret);
+		return ret;
+	}
+
+	cros_shi_npcx_reset_prepare(inst);
+	npcx_miwu_irq_disable(&config->shi_cs_wui);
+
+	/* Configure pin control for SHI */
+	ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
+	if (ret < 0) {
+		LOG_ERR("cros_shi_npcx pinctrl setup failed (%d)", ret);
+		return ret;
+	}
+
+	NVIC_ClearPendingIRQ(DT_INST_IRQN(0));
+	npcx_miwu_irq_enable(&config->shi_cs_wui);
+	irq_enable(DT_INST_IRQN(0));
+
+	return 0;
+}
+
+static int cros_shi_npcx_disable(const struct device *dev)
+{
+	const struct cros_shi_npcx_config *const config = DRV_CONFIG(dev);
+	const struct device *clk_dev = DEVICE_DT_GET(NPCX_CLK_CTRL_NODE);
+	int ret;
+
+	state = SHI_STATE_DISABLED;
+
+	irq_disable(DT_INST_IRQN(0));
+	npcx_miwu_irq_disable(&config->shi_cs_wui);
+
+	/* Configure pin control back to GPIO */
+	ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_SLEEP);
+	if (ret < 0) {
+		LOG_ERR("KB Raw pinctrl setup failed (%d)", ret);
+		return ret;
+	}
+
+	ret = clock_control_off(clk_dev,
+				(clock_control_subsys_t *)&config->clk_cfg);
+	if (ret < 0) {
+		DEBUG_CPRINTF("Turn off SHI clock fail %d", ret);
+		return ret;
+	}
+
+	/*
+	 * Allow deep sleep again in case CS dropped before ec was
+	 * informed in hook function and turn off SHI's interrupt in time.
+	 */
+	enable_sleep(SLEEP_MASK_SPI);
+
+	return 0;
+}
+
+static int shi_npcx_init(const struct device *dev)
+{
+	int ret;
+	const struct cros_shi_npcx_config *const config = DRV_CONFIG(dev);
+	struct shi_reg *const inst = HAL_INSTANCE(dev);
+	const struct device *clk_dev = DEVICE_DT_GET(NPCX_CLK_CTRL_NODE);
+
+	/* Turn on shi device clock first */
+	ret = clock_control_on(clk_dev,
+			       (clock_control_subsys_t *)&config->clk_cfg);
+	if (ret < 0) {
+		DEBUG_CPRINTF("Turn on SHI clock fail %d", ret);
+		return ret;
+	}
+
+	/* If booter doesn't set the host interface type */
+	if (!NPCX_BOOTER_IS_HIF_TYPE_SET()) {
+		npcx_host_interface_sel(NPCX_HIF_TYPE_ESPI_SHI);
+	}
+
+	/*
+	 * SHICFG1 (SHI Configuration 1) setting
+	 * [7] - IWRAP	= 1: Wrap input buffer to the first address
+	 * [6] - CPOL	= 0: Sampling on rising edge and output on falling edge
+	 * [5] - DAS	= 0: return STATUS reg data after Status command
+	 * [4] - AUTOBE	= 0: Automatically update the OBES bit in STATUS reg
+	 * [3] - AUTIBF	= 0: Automatically update the IBFS bit in STATUS reg
+	 * [2] - WEN    = 0: Enable host write to input buffer
+	 * [1] - Reserved 0
+	 * [0] - ENABLE	= 0: Disable SHI at the beginning
+	 */
+	inst->SHICFG1 = 0x80;
+
+	/*
+	 * SHICFG2 (SHI Configuration 2) setting
+	 * [7] - Reserved 0
+	 * [6] - REEVEN = 0: Restart events are not used
+	 * [5] - Reserved 0
+	 * [4] - REEN   = 0: Restart transactions are not used
+	 * [3] - SLWU   = 0: Seem-less wake-up is enabled by default
+	 * [2] - ONESHOT= 0: WEN is cleared at the end of a write transaction
+	 * [1] - BUSY   = 0: SHI bus is busy 0: idle.
+	 * [0] - SIMUL	= 1: Turn on simultaneous Read/Write
+	 */
+	inst->SHICFG2 = 0x01;
+
+	/*
+	 * EVENABLE (Event Enable) setting
+	 * [7] - IBOREN = 0: Input buffer overrun interrupt enable
+	 * [6] - STSREN = 0: status read interrupt disable
+	 * [5] - EOWEN  = 0: End-of-Data for Write Transaction Interrupt Enable
+	 * [4] - EOREN  = 1: End-of-Data for Read Transaction Interrupt Enable
+	 * [3] - IBHFEN = 1: Input Buffer Half Full Interrupt Enable
+	 * [2] - IBFEN  = 1: Input Buffer Full Interrupt Enable
+	 * [1] - OBHEEN = 0: Output Buffer Half Empty Interrupt Enable
+	 * [0] - OBEEN  = 0: Output Buffer Empty Interrupt Enable
+	 */
+	inst->EVENABLE = 0x1C;
+
+	/*
+	 * EVENABLE2 (Event Enable 2) setting
+	 * [2] - CSNFEEN = 1: SHI_CS Falling Edge Interrupt Enable
+	 * [1] - CSNREEN = 1: SHI_CS Rising Edge Interrupt Enable
+	 * [0] - IBHF2EN = 0: Input Buffer Half Full 2 Interrupt Enable
+	 */
+	inst->EVENABLE2 = 0x06;
+
+	/* Clear SHI events status register */
+	inst->EVSTAT = 0xff;
+
+	npcx_miwu_interrupt_configure(&config->shi_cs_wui, NPCX_MIWU_MODE_EDGE,
+				      NPCX_MIWU_TRIG_LOW);
+	/* SHI interrupt installation */
+	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
+		    cros_shi_npcx_isr, DEVICE_DT_INST_GET(0), 0);
+
+	return ret;
+}
+
+static const struct cros_shi_driver_api cros_shi_npcx_driver_api = {
+	.enable = cros_shi_npcx_enable,
+	.disable = cros_shi_npcx_disable,
+};
+
+static struct cros_shi_npcx_data cros_shi_data;
+DEVICE_DT_INST_DEFINE(0, shi_npcx_init, /* pm_control_fn= */ NULL,
+		      &cros_shi_data, &cros_shi_cfg, PRE_KERNEL_1,
+		      CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
+		      &cros_shi_npcx_driver_api);
+
+/* KBS register structure check */
+NPCX_REG_SIZE_CHECK(shi_reg, 0x120);
+NPCX_REG_OFFSET_CHECK(shi_reg, SHICFG1, 0x001);
+NPCX_REG_OFFSET_CHECK(shi_reg, EVENABLE, 0x005);
+NPCX_REG_OFFSET_CHECK(shi_reg, IBUFSTAT, 0x00a);
+NPCX_REG_OFFSET_CHECK(shi_reg, EVENABLE2, 0x010);
+NPCX_REG_OFFSET_CHECK(shi_reg, OBUF, 0x020);
+NPCX_REG_OFFSET_CHECK(shi_reg, IBUF, 0x0A0);
diff --git a/zephyr/drivers/cros_system/CMakeLists.txt b/zephyr/drivers/cros_system/CMakeLists.txt
new file mode 100644
index 0000000000..526255c370
--- /dev/null
+++ b/zephyr/drivers/cros_system/CMakeLists.txt
@@ -0,0 +1,9 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+zephyr_library_sources_ifdef(CONFIG_CROS_SYSTEM_IT8XXX2	cros_system_it8xxx2.c)
+zephyr_library_sources_ifdef(CONFIG_CROS_SYSTEM_NPCX	cros_system_npcx.c)
+zephyr_library_sources_ifdef(CONFIG_CROS_SYSTEM_XEC	cros_system_xec.c)
+zephyr_library_sources_ifdef(CONFIG_CROS_SYSTEM_NATIVE_POSIX	cros_system_native_posix.c)
+zephyr_library_sources_ifdef(CONFIG_CROS_SYSTEM_STM32	cros_system_stm32.c)
diff --git a/zephyr/drivers/cros_system/Kconfig b/zephyr/drivers/cros_system/Kconfig
new file mode 100644
index 0000000000..254e870179
--- /dev/null
+++ b/zephyr/drivers/cros_system/Kconfig
@@ -0,0 +1,117 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+menuconfig CROS_SYSTEM_NPCX
+	bool "Nuvoton NPCX cros system driver"
+	depends on SOC_FAMILY_NPCX
+	default y
+	help
+	  This option enables the cros system driver for the NPCX family of
+	  processors. Currently, Zephyr doesn't provide the system related API.
+	  The cros system driver provides the low-level driver related to
+	  chromium ec system functionality.
+
+if CROS_SYSTEM_NPCX
+
+config CROS_SYSTEM_NPCX_INIT_PRIORITY
+	int "cros_system npcx initialization priority"
+	default 10
+	range 10 19
+	help
+	  This sets the npcx cros_system driver initialization priority. The
+	  cros_system driver provides access to the NPCX reset cause and must be
+	  higher priority than CONFIG_SYSTEM_PRE_INIT_PRIORITY.
+
+endif # CROS_SYSTEM_NPCX
+
+config CROS_SYSTEM_IT8XXX2
+	bool "ITE IT8XXX2 cros system driver"
+	depends on SOC_FAMILY_RISCV_ITE
+	default y
+	help
+	  This option enables the cros system driver for the it8xxx2 family of
+	  processors.
+
+if CROS_SYSTEM_IT8XXX2
+
+config CROS_SYSTEM_IT8XXX2_INIT_PRIORITY
+	int "cros_system it8xxx2 initialization priority"
+	default 10
+	help
+	  This sets the it8xxx2 cros_system driver initialization priority.
+	  The cros_system driver provides access to the it8xxx2 reset cause
+	  and must be higher priority than
+	  CONFIG_PLATFORM_EC_SYSTEM_PRE_INIT_PRIORITY.
+
+endif # CROS_SYSTEM_IT8XXX2
+
+menuconfig CROS_SYSTEM_XEC
+	bool "Microchip XEC cros system driver"
+	depends on SOC_FAMILY_MEC
+	default y
+	help
+	  This option enables the cros system driver for the MCHP XEC family of
+	  processors. Currently, Zephyr doesn't provide the system related API.
+	  The cros system driver provides the low-level driver related to
+	  chromium ec system functionality.
+
+if CROS_SYSTEM_XEC
+
+config CROS_SYSTEM_XEC_INIT_PRIORITY
+	int "cros_system MEC initialization priority"
+	default 10
+	help
+	  This sets the MEC cros_system driver initialization priority.
+	  The cros_system driver provides access to the MEC reset cause
+	  and must be higher priority than
+	  CONFIG_PLATFORM_EC_SYSTEM_PRE_INIT_PRIORITY.
+
+endif # CONFIG_CROS_SYSTEM_XEC
+
+menuconfig CROS_SYSTEM_NATIVE_POSIX
+	bool "Native POSIX cros system driver (test only)"
+	depends on SOC_POSIX && CROS_EC
+	default y
+	help
+	  This option enables the cros system driver for the native POSIX
+	  testing board. Currently, Zephyr doesn't provide the system related
+	  API.  The cros system driver provides fakable stubs for the low-level
+	  driver related to chromium ec system functionality.
+
+if CROS_SYSTEM_NATIVE_POSIX
+
+config CROS_SYSTEM_NATIVE_POSIX_INIT_PRIORITY
+	int "cros_system native POSIX initialization priority (test only)"
+	default 10
+	range 10 19
+	help
+	  This sets the native POSIX cros_system driver initialization
+	  priority. The cros_system driver provides access to mockable cros
+	  system functions to facillitate testing and must be higher priority
+	  than CONFIG_SYSTEM_PRE_INIT_PRIORITY.
+
+endif # CROS_SYSTEM_NATIVE_POSIX
+
+menuconfig CROS_SYSTEM_STM32
+	bool "ST STM32 cros system driver"
+	depends on SOC_FAMILY_STM32 && IWDG_STM32 && HWINFO
+	select REBOOT
+	default y
+	help
+	  This option enables the cros system driver for the STM32 family of
+	  processors. The cros system driver provides the low-level driver
+	  related to chromium ec system functionality.
+
+if CROS_SYSTEM_STM32
+
+config CROS_SYSTEM_STM32_INIT_PRIORITY
+	int "cros_system STM32 initialization priority"
+	default 10
+	help
+	  This sets the STM32 cros_system driver initialization priority.
+	  The cros_system driver provides access to the STM32 reset cause
+	  and must be higher priority than
+	  CONFIG_PLATFORM_EC_SYSTEM_PRE_INIT_PRIORITY.
+
+endif # CONFIG_CROS_SYSTEM_STM32
diff --git a/zephyr/drivers/cros_system/cros_system_it8xxx2.c b/zephyr/drivers/cros_system/cros_system_it8xxx2.c
new file mode 100644
index 0000000000..a78b5c929c
--- /dev/null
+++ b/zephyr/drivers/cros_system/cros_system_it8xxx2.c
@@ -0,0 +1,270 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define DT_DRV_COMPAT ite_it8xxx2_gctrl
+
+#include "drivers/cros_system.h"
+#include "gpio/gpio_int.h"
+#include "system.h"
+#include "util.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/logging/log.h>
+
+#include <soc.h>
+#include <soc/ite_it8xxx2/reg_def_cros.h>
+
+LOG_MODULE_REGISTER(cros_system, LOG_LEVEL_ERR);
+
+#define GCTRL_IT8XXX2_REG_BASE \
+	((struct gctrl_it8xxx2_regs *)DT_INST_REG_ADDR(0))
+
+#define WDT_IT8XXX2_REG_BASE \
+	((struct wdt_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(twd0)))
+
+static const char *cros_system_it8xxx2_get_chip_vendor(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	return "ite";
+}
+
+static uint32_t system_get_chip_id(void)
+{
+	struct gctrl_it8xxx2_regs *const gctrl_base = GCTRL_IT8XXX2_REG_BASE;
+
+	return (gctrl_base->GCTRL_ECHIPID1 << 16) |
+	       (gctrl_base->GCTRL_ECHIPID2 << 8) | gctrl_base->GCTRL_ECHIPID3;
+}
+
+static uint8_t system_get_chip_version(void)
+{
+	struct gctrl_it8xxx2_regs *const gctrl_base = GCTRL_IT8XXX2_REG_BASE;
+
+	/* bit[3-0], chip version */
+	return gctrl_base->GCTRL_ECHIPVER & 0x0F;
+}
+
+static const char *cros_system_it8xxx2_get_chip_name(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	static char buf[8] = { 'i', 't' };
+	uint32_t chip_id = system_get_chip_id();
+	int num = 4;
+
+	for (int n = 2; num >= 0; n++, num--)
+		snprintf(buf + n, (sizeof(buf) - n), "%x",
+			 chip_id >> (num * 4) & 0xF);
+
+	return buf;
+}
+
+static const char *
+cros_system_it8xxx2_get_chip_revision(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	static char buf[3];
+	uint8_t rev = system_get_chip_version();
+
+	snprintf(buf, sizeof(buf), "%1xx", rev + 0xa);
+
+	return buf;
+}
+
+static int cros_system_it8xxx2_get_reset_cause(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+	struct gctrl_it8xxx2_regs *const gctrl_base = GCTRL_IT8XXX2_REG_BASE;
+	uint8_t last_reset_source = gctrl_base->GCTRL_RSTS & IT8XXX2_GCTRL_LRS;
+	uint8_t raw_reset_cause2 =
+		gctrl_base->GCTRL_SPCTRL4 &
+		(IT8XXX2_GCTRL_LRSIWR | IT8XXX2_GCTRL_LRSIPWRSWTR |
+		 IT8XXX2_GCTRL_LRSIPGWR);
+
+	/* Clear reset cause. */
+	gctrl_base->GCTRL_RSTS |= IT8XXX2_GCTRL_LRS;
+	gctrl_base->GCTRL_SPCTRL4 |=
+		(IT8XXX2_GCTRL_LRSIWR | IT8XXX2_GCTRL_LRSIPWRSWTR |
+		 IT8XXX2_GCTRL_LRSIPGWR);
+
+	if (last_reset_source & IT8XXX2_GCTRL_IWDTR) {
+		return WATCHDOG_RST;
+	}
+	if (raw_reset_cause2 & IT8XXX2_GCTRL_LRSIWR) {
+		/*
+		 * We can't differentiate between power-on and reset pin because
+		 * LRSIWR is set on both ~WRST assertion and power-on, and LRS
+		 * is either 0 or 1 in both cases. Conservatively treat both as
+		 * power-on.
+		 */
+		return POWERUP;
+	}
+	return UNKNOWN_RST;
+}
+
+static int cros_system_it8xxx2_init(const struct device *dev)
+{
+	struct gctrl_it8xxx2_regs *const gctrl_base = GCTRL_IT8XXX2_REG_BASE;
+
+	/* System triggers a soft reset by default (command: reboot). */
+	gctrl_base->GCTRL_ETWDUARTCR &= ~IT8XXX2_GCTRL_ETWD_HW_RST_EN;
+
+	return 0;
+}
+
+static int cros_system_it8xxx2_soc_reset(const struct device *dev)
+{
+	struct gctrl_it8xxx2_regs *const gctrl_base = GCTRL_IT8XXX2_REG_BASE;
+	struct wdt_it8xxx2_regs *const wdt_base = WDT_IT8XXX2_REG_BASE;
+	uint32_t chip_reset_flags = chip_read_reset_flags();
+
+	/* Disable interrupts to avoid task swaps during reboot. */
+	interrupt_disable_all();
+
+	if (chip_reset_flags & (EC_RESET_FLAG_HARD | EC_RESET_FLAG_HIBERNATE))
+		gctrl_base->GCTRL_ETWDUARTCR |= IT8XXX2_GCTRL_ETWD_HW_RST_EN;
+
+	/*
+	 * Writing invalid key to watchdog module triggers a soft or hardware
+	 * reset. It depends on the setting of bit0 at ETWDUARTCR register.
+	 */
+	wdt_base->ETWCFG |= IT8XXX2_WDT_EWDKEYEN;
+	wdt_base->EWDKEYR = 0x00;
+
+	/* Spin and wait for reboot */
+	while (1)
+		;
+
+	/* Should never return */
+	return 0;
+}
+
+/*
+ * Fake wake ISR handler, needed for pins that do not have a handler.
+ */
+void wake_isr(enum gpio_signal signal)
+{
+}
+
+static int cros_system_it8xxx2_hibernate(const struct device *dev,
+					 uint32_t seconds,
+					 uint32_t microseconds)
+{
+	struct wdt_it8xxx2_regs *const wdt_base = WDT_IT8XXX2_REG_BASE;
+
+	/* Disable all interrupts. */
+	interrupt_disable_all();
+
+	/* Save and disable interrupts */
+	if (IS_ENABLED(CONFIG_ITE_IT8XXX2_INTC))
+		ite_intc_save_and_disable_interrupts();
+
+	/* bit5: watchdog is disabled. */
+	wdt_base->ETWCTRL |= IT8XXX2_WDT_EWDSCEN;
+
+	/*
+	 * Setup GPIOs for hibernate. On some boards, it's possible that this
+	 * may not return at all. On those boards, power to the EC is likely
+	 * being turn off entirely.
+	 */
+	if (board_hibernate_late) {
+		/*
+		 * Set reset flag in case board_hibernate_late() doesn't
+		 * return.
+		 */
+		chip_save_reset_flags(EC_RESET_FLAG_HIBERNATE);
+		board_hibernate_late();
+	}
+
+	if (seconds || microseconds) {
+		/*
+		 * Convert milliseconds(or at least 1 ms) to 32 Hz
+		 * free run timer count for hibernate.
+		 */
+		uint32_t c =
+			(seconds * 1000 + microseconds / 1000 + 1) * 32 / 1000;
+
+		/* Enable a 32-bit timer and clock source is 32 Hz */
+		/* Disable external timer x */
+		IT8XXX2_EXT_CTRLX(FREE_RUN_TIMER) &= ~IT8XXX2_EXT_ETXEN;
+		irq_disable(FREE_RUN_TIMER_IRQ);
+		IT8XXX2_EXT_PSRX(FREE_RUN_TIMER) = EXT_PSR_32;
+		IT8XXX2_EXT_CNTX(FREE_RUN_TIMER) = c & FREE_RUN_TIMER_MAX_CNT;
+		/* Enable and re-start external timer x */
+		IT8XXX2_EXT_CTRLX(FREE_RUN_TIMER) |=
+			(IT8XXX2_EXT_ETXEN | IT8XXX2_EXT_ETXRST);
+		irq_enable(FREE_RUN_TIMER_IRQ);
+	}
+
+#if DT_NODE_EXISTS(SYSTEM_DT_NODE_HIBERNATE_CONFIG)
+
+/*
+ * Get the interrupt DTS node for this wakeup pin
+ */
+#define WAKEUP_INT(id, prop, idx) DT_PHANDLE_BY_IDX(id, prop, idx)
+
+/*
+ * Get the named-gpio node for this wakeup pin by reading the
+ * irq-gpio property from the interrupt node.
+ */
+#define WAKEUP_NGPIO(id, prop, idx) \
+	DT_PHANDLE(WAKEUP_INT(id, prop, idx), irq_pin)
+
+/*
+ * Reset and re-enable interrupts on this wake pin.
+ */
+#define WAKEUP_SETUP(id, prop, idx)                                     \
+	do {                                                            \
+		gpio_pin_configure_dt(                                  \
+			GPIO_DT_FROM_NODE(WAKEUP_NGPIO(id, prop, idx)), \
+			GPIO_INPUT);                                    \
+		gpio_enable_dt_interrupt(                               \
+			GPIO_INT_FROM_NODE(WAKEUP_INT(id, prop, idx))); \
+	} while (0);
+
+	/*
+	 * For all the wake-pins, re-init the GPIO and re-enable the interrupt.
+	 */
+	DT_FOREACH_PROP_ELEM(SYSTEM_DT_NODE_HIBERNATE_CONFIG, wakeup_irqs,
+			     WAKEUP_SETUP);
+
+#undef WAKEUP_INT
+#undef WAKEUP_NGPIO
+#undef WAKEUP_SETUP
+
+#endif
+
+	/* EC sleep mode */
+	chip_pll_ctrl(CHIP_PLL_SLEEP);
+
+	/* Chip sleep and wait timer wake it up */
+	__asm__ volatile("wfi");
+
+	/* Reset EC when wake up from sleep mode (system hibernate) */
+	system_reset(SYSTEM_RESET_HIBERNATE);
+
+	return 0;
+}
+
+static const struct cros_system_driver_api cros_system_driver_it8xxx2_api = {
+	.get_reset_cause = cros_system_it8xxx2_get_reset_cause,
+	.soc_reset = cros_system_it8xxx2_soc_reset,
+	.hibernate = cros_system_it8xxx2_hibernate,
+	.chip_vendor = cros_system_it8xxx2_get_chip_vendor,
+	.chip_name = cros_system_it8xxx2_get_chip_name,
+	.chip_revision = cros_system_it8xxx2_get_chip_revision,
+};
+
+#if CONFIG_CROS_SYSTEM_IT8XXX2_INIT_PRIORITY >= \
+	CONFIG_PLATFORM_EC_SYSTEM_PRE_INIT_PRIORITY
+#error "CROS_SYSTEM must initialize before the SYSTEM_PRE initialization"
+#endif
+DEVICE_DEFINE(cros_system_it8xxx2_0, "CROS_SYSTEM", cros_system_it8xxx2_init,
+	      NULL, NULL, NULL, PRE_KERNEL_1,
+	      CONFIG_CROS_SYSTEM_IT8XXX2_INIT_PRIORITY,
+	      &cros_system_driver_it8xxx2_api);
diff --git a/zephyr/drivers/cros_system/cros_system_native_posix.c b/zephyr/drivers/cros_system/cros_system_native_posix.c
new file mode 100644
index 0000000000..59fdb39972
--- /dev/null
+++ b/zephyr/drivers/cros_system/cros_system_native_posix.c
@@ -0,0 +1,117 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* LCOV_EXCL_START */
+/* This is test code, so it should be excluded from coverage */
+
+#include "common.h"
+#include "drivers/cros_system.h"
+
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/util.h>
+
+LOG_MODULE_REGISTER(cros_system, LOG_LEVEL_ERR);
+
+/* Driver config stub */
+struct cros_system_native_posix_config {};
+
+/* Driver data stub */
+struct cros_system_native_posix_data {};
+
+test_mockable_static int cros_system_native_posix_init(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	return 0;
+}
+
+/* Stubbed cros_system API */
+
+test_mockable_static int
+cros_system_native_posix_get_reset_cause(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	return 0;
+}
+
+test_mockable_static int
+cros_system_native_posix_soc_reset(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	return 0;
+}
+
+test_mockable_static int
+cros_system_native_posix_hibernate(const struct device *dev, uint32_t seconds,
+				   uint32_t microseconds)
+{
+	ARG_UNUSED(dev);
+	ARG_UNUSED(seconds);
+	ARG_UNUSED(microseconds);
+
+	return 0;
+}
+
+test_mockable_static const char *
+cros_system_native_posix_get_chip_vendor(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	return "NATIVE_POSIX_VENDOR";
+}
+
+test_mockable_static const char *
+cros_system_native_posix_get_chip_name(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	return "NATIVE_POSIX_CHIP";
+}
+
+test_mockable_static const char *
+cros_system_native_posix_get_chip_revision(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	return "NATIVE_POSIX_REVISION";
+}
+
+__maybe_unused test_mockable_static uint64_t
+cros_system_native_posix_deep_sleep_ticks(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	return 0;
+}
+
+static struct cros_system_native_posix_data cros_system_native_posix_dev_data;
+
+static const struct cros_system_native_posix_config cros_system_dev_cfg = {};
+
+/* clang-format off */
+/* clang-format extends past 80 lines here */
+static const struct
+cros_system_driver_api cros_system_driver_native_posix_api = {
+	.get_reset_cause = cros_system_native_posix_get_reset_cause,
+	.soc_reset = cros_system_native_posix_soc_reset,
+	.hibernate = cros_system_native_posix_hibernate,
+	.chip_vendor = cros_system_native_posix_get_chip_vendor,
+	.chip_name = cros_system_native_posix_get_chip_name,
+	.chip_revision = cros_system_native_posix_get_chip_revision,
+#ifdef CONFIG_PM
+	.deep_sleep_ticks = cros_system_native_posix_deep_sleep_ticks,
+#endif
+};
+/* clang-format on */
+
+DEVICE_DEFINE(cros_system_native_posix_0, "CROS_SYSTEM",
+	      cros_system_native_posix_init, NULL,
+	      &cros_system_native_posix_dev_data, &cros_system_dev_cfg,
+	      PRE_KERNEL_1, CONFIG_CROS_SYSTEM_NATIVE_POSIX_INIT_PRIORITY,
+	      &cros_system_driver_native_posix_api);
+
+/* LCOV_EXCL_STOP */
diff --git a/zephyr/drivers/cros_system/cros_system_npcx.c b/zephyr/drivers/cros_system/cros_system_npcx.c
new file mode 100644
index 0000000000..3a11821a32
--- /dev/null
+++ b/zephyr/drivers/cros_system/cros_system_npcx.c
@@ -0,0 +1,658 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "bbram.h"
+#include "drivers/cros_system.h"
+#include "gpio/gpio_int.h"
+#include "rom_chip.h"
+#include "soc_gpio.h"
+#include "soc_miwu.h"
+#include "system.h"
+#include "util.h"
+
+#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/drivers/watchdog.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/util.h>
+
+#include <soc.h>
+#include <soc/nuvoton_npcx/reg_def_cros.h>
+
+LOG_MODULE_REGISTER(cros_system, LOG_LEVEL_ERR);
+
+/* Driver config */
+struct cros_system_npcx_config {
+	/* hardware module base address */
+	uintptr_t base_scfg;
+	uintptr_t base_twd;
+	uintptr_t base_mswc;
+};
+
+/* Driver data */
+struct cros_system_npcx_data {
+	int reset; /* reset cause */
+};
+
+/* Driver convenience defines */
+#define DRV_CONFIG(dev) ((const struct cros_system_npcx_config *)(dev)->config)
+
+#define HAL_SCFG_INST(dev) (struct scfg_reg *)(DRV_CONFIG(dev)->base_scfg)
+#define HAL_TWD_INST(dev) (struct twd_reg *)(DRV_CONFIG(dev)->base_twd)
+#define HAL_MSWC_INST(dev) (struct mswc_reg *)(DRV_CONFIG(dev)->base_mswc)
+
+#define DRV_DATA(dev) ((struct cros_system_npcx_data *)(dev)->data)
+
+#define SYSTEM_DT_NODE_SOC_ID_CONFIG DT_INST(0, nuvoton_npcx_soc_id)
+
+/* Chip info devicetree data */
+#define NPCX_FAMILY_ID DT_PROP(SYSTEM_DT_NODE_SOC_ID_CONFIG, family_id)
+
+#define NPCX_CHIP_ID DT_PROP(SYSTEM_DT_NODE_SOC_ID_CONFIG, chip_id)
+
+#define NPCX_DEVICE_ID DT_PROP(SYSTEM_DT_NODE_SOC_ID_CONFIG, device_id)
+
+#define NPCX_REVISION_ADDR \
+	DT_PROP_BY_IDX(SYSTEM_DT_NODE_SOC_ID_CONFIG, revision_reg, 0)
+#define NPCX_REVISION_LEN \
+	DT_PROP_BY_IDX(SYSTEM_DT_NODE_SOC_ID_CONFIG, revision_reg, 1)
+
+/* RAM block size in npcx family (Unit: bytes) */
+#define NPCX_RAM_BLOCK_SIZE (32 * 1024)
+/* RAM block number in npcx7 series */
+
+/* Calculate the number of RAM blocks:
+ * total RAM size = code ram + data ram + extra 2K for ROM functions
+ * divided by the block size 32k.
+ */
+#if DT_NODE_EXISTS(DT_NODELABEL(bootloader_ram))
+#define BT_RAM_SIZE DT_REG_SIZE(DT_NODELABEL(bootloader_ram))
+#else
+#define BT_RAM_SIZE 0
+#endif
+#define DATA_RAM_SIZE DT_REG_SIZE(DT_NODELABEL(sram0))
+#define CODE_RAM_SIZE DT_REG_SIZE(DT_NODELABEL(flash0))
+#define NPCX_RAM_BLOCK_COUNT \
+	((DATA_RAM_SIZE + CODE_RAM_SIZE + BT_RAM_SIZE) / NPCX_RAM_BLOCK_SIZE)
+
+/* Valid bit-depth of RAM block Power-Down control (RAM_PD) registers. Use its
+ * mask to power down all unnecessary RAM blocks before hibernating.
+ */
+#define NPCX_RAM_PD_DEPTH DT_PROP(DT_NODELABEL(pcc), ram_pd_depth)
+#define NPCX_RAM_BLOCK_PD_MASK (BIT(NPCX_RAM_PD_DEPTH) - 1)
+
+/* Get saved reset flag address in battery-backed ram */
+#define BBRAM_SAVED_RESET_FLAG_ADDR                    \
+	(DT_REG_ADDR(DT_INST(0, nuvoton_npcx_bbram)) + \
+	 BBRAM_REGION_OFFSET(saved_reset_flags))
+
+/* Soc specific system local functions */
+static int system_npcx_watchdog_stop(void)
+{
+	if (IS_ENABLED(CONFIG_WATCHDOG)) {
+		const struct device *wdt_dev =
+			DEVICE_DT_GET(DT_NODELABEL(twd0));
+		if (!device_is_ready(wdt_dev)) {
+			LOG_ERR("Error: device %s is not ready", wdt_dev->name);
+			return -ENODEV;
+		}
+
+		wdt_disable(wdt_dev);
+	}
+
+	return 0;
+}
+
+static void system_npcx_set_flash_pins_tri_state(const struct device *dev)
+{
+	struct scfg_reg *const inst_scfg = HAL_SCFG_INST(dev);
+
+	inst_scfg->DEVCNT |= BIT(NPCX_DEVCNT_F_SPI_TRIS);
+}
+
+static void system_npcx_init_watchdog_reset(const struct device *dev)
+{
+	struct twd_reg *const inst_twd = HAL_TWD_INST(dev);
+
+	/* Enable early touch */
+	inst_twd->T0CSR &= ~BIT(NPCX_T0CSR_TESDIS);
+	/* watchdog touched by writing 5Ch to WDSDM */
+	inst_twd->TWCFG |= BIT(NPCX_TWCFG_WDSDME);
+}
+
+static void system_npcx_turn_off_adc(void)
+{
+	struct adc_reg *const inst_adc =
+		(struct adc_reg *)(DT_REG_ADDR(DT_INST(0, nuvoton_npcx_adc)));
+
+	inst_adc->ADCCNF = 0;
+	/* Wait for 1000 us to make sure conversion is completed. */
+	k_busy_wait(1000);
+}
+
+static void system_npcx_turn_off_kernel_timer(void)
+{
+	static struct itim32_reg *const evt_tmr =
+		(struct itim32_reg *)DT_REG_ADDR_BY_NAME(
+			DT_INST(0, nuvoton_npcx_itim_timer), evt_itim);
+
+	evt_tmr->ITCTS32 &= ~BIT(NPCX_ITCTSXX_ITEN);
+}
+
+static void system_npcx_disable_instant_wakeup(void)
+{
+	struct pmc_reg *const inst_pmc = (struct pmc_reg *)(DT_REG_ADDR_BY_NAME(
+		DT_INST(0, nuvoton_npcx_pcc), pmc));
+
+	inst_pmc->ENIDL_CTL &= ~BIT(NPCX_ENIDL_CTL_LP_WK_CTL);
+}
+
+/*
+ * Fake wake ISR handler, needed for pins that do not have a handler.
+ */
+void wake_isr(enum gpio_signal signal)
+{
+}
+
+static void system_npcx_set_wakeup_gpios_before_hibernate(void)
+{
+	const uintptr_t miwu_base[] = {
+		DT_REG_ADDR(DT_INST(0, nuvoton_npcx_miwu)),
+		DT_REG_ADDR(DT_INST(1, nuvoton_npcx_miwu)),
+		DT_REG_ADDR(DT_INST(2, nuvoton_npcx_miwu)),
+	};
+
+	/* Disable all MIWU inputs before entering hibernate */
+	for (int table = 0; table < ARRAY_SIZE(miwu_base); table++) {
+		for (int group = 0; group < NPCX_MIWU_GROUP_COUNT; group++) {
+			/* Disable all wake-ups */
+			NPCX_WKEN(miwu_base[table], group) = 0x00;
+			/* Clear all pending bits of wake-ups */
+			NPCX_WKPCL(miwu_base[table], group) = 0xFF;
+			/*
+			 * Disable all inputs of wake-ups to prevent leakage
+			 * caused by input floating.
+			 */
+			NPCX_WKINEN(miwu_base[table], group) = 0x00;
+		}
+	}
+
+#if DT_NODE_EXISTS(SYSTEM_DT_NODE_HIBERNATE_CONFIG)
+
+/*
+ * Get the interrupt DTS node for this wakeup pin
+ */
+#define WAKEUP_INT(id, prop, idx) DT_PHANDLE_BY_IDX(id, prop, idx)
+
+/*
+ * Get the named-gpio node for this wakeup pin by reading the
+ * irq-gpio property from the interrupt node.
+ */
+#define WAKEUP_NGPIO(id, prop, idx) \
+	DT_PHANDLE(WAKEUP_INT(id, prop, idx), irq_pin)
+
+/*
+ * Reset and re-enable interrupts on this wake pin.
+ */
+#define WAKEUP_SETUP(id, prop, idx)                                     \
+	do {                                                            \
+		gpio_pin_configure_dt(                                  \
+			GPIO_DT_FROM_NODE(WAKEUP_NGPIO(id, prop, idx)), \
+			GPIO_INPUT);                                    \
+		gpio_enable_dt_interrupt(                               \
+			GPIO_INT_FROM_NODE(WAKEUP_INT(id, prop, idx))); \
+	} while (0);
+
+	/*
+	 * For all the wake-pins, re-init the GPIO and re-enable the interrupt.
+	 */
+	DT_FOREACH_PROP_ELEM(SYSTEM_DT_NODE_HIBERNATE_CONFIG, wakeup_irqs,
+			     WAKEUP_SETUP);
+
+#undef WAKEUP_INT
+#undef WAKEUP_NGPIO
+#undef WAKEUP_SETUP
+
+#endif
+}
+
+/*
+ * Hibernate function locates in the last 32K ram block in npcx7 series.
+ * Do not use global variables or call functions since we have turned off
+ * the other ram blocks.
+ */
+noreturn void __keep __attribute__((section(".lfw.hiber")))
+system_npcx_hibernate_by_lfw_in_last_ram(const struct device *dev,
+					 uint32_t pd_ram_mask)
+{
+	/* Modules used for hibernating */
+	struct twd_reg *const inst_twd = HAL_TWD_INST(dev);
+	struct mtc_reg *const inst_mtc = (struct mtc_reg *)(DT_REG_ADDR(
+		DT_INST(0, nuvoton_npcx_cros_mtc)));
+	struct pmc_reg *const inst_pmc = (struct pmc_reg *)(DT_REG_ADDR_BY_NAME(
+		DT_INST(0, nuvoton_npcx_pcc), pmc));
+	uint32_t reset_flags;
+	volatile uint8_t *saved_reset_flags =
+		(volatile uint8_t *)BBRAM_SAVED_RESET_FLAG_ADDR;
+
+	/* Turn off all blocks except last one for better power consumption */
+	inst_pmc->RAM_PD[0] = (uint8_t)pd_ram_mask;
+	inst_pmc->RAM_PD[1] = (uint8_t)(pd_ram_mask >> 8);
+
+	/* Set deep idle mode */
+	inst_pmc->PMCSR = BIT(NPCX_PMCSR_IDLE) | BIT(NPCX_PMCSR_DHF);
+
+	/* Enter system sleep mode */
+	__asm__ volatile("wfi");
+
+	/*
+	 * Mark wake-up reason for hibernate. Do not call bbram utilities
+	 * directly since the other ram blocks are power down.
+	 */
+	if (IS_BIT_SET(inst_mtc->WTC, NPCX_WTC_PTO)) {
+		/* Save wake-up reason as RTC alarm. */
+		reset_flags = EC_RESET_FLAG_RTC_ALARM;
+	} else {
+		/* Otherwise, we treat it as GPIOs wake-up */
+		reset_flags = EC_RESET_FLAG_WAKE_PIN;
+	}
+
+	saved_reset_flags[0] |= reset_flags;
+	saved_reset_flags[1] |= reset_flags >> 8;
+	saved_reset_flags[2] |= reset_flags >> 16;
+	saved_reset_flags[3] |= reset_flags >> 24;
+
+	/*
+	 * The trigger of a watchdog event by a "too early service" condition.
+	 * When the watchdog is written more than once during three watchdog
+	 * clock cycle.
+	 */
+	inst_twd->WDSDM = 0x5C;
+	inst_twd->WDSDM = 0x5C;
+
+	/* Spin and wait for reboot; should never return */
+	while (1)
+		continue;
+}
+
+static inline int system_npcx_get_ram_blk_by_lfw_addr(char *address)
+{
+	return NPCX_RAM_BLOCK_COUNT -
+	       DIV_ROUND_UP((uint32_t)address -
+				    CONFIG_CROS_EC_PROGRAM_MEMORY_BASE,
+			    NPCX_RAM_BLOCK_SIZE);
+}
+
+static void system_npcx_hibernate_by_disable_ram(const struct device *dev,
+						 uint32_t seconds,
+						 uint32_t microseconds)
+{
+	/* Get 32kb ram block order of lfw function */
+	extern char __lfw_text_start[], __lfw_text_end[];
+	int lfw_block = system_npcx_get_ram_blk_by_lfw_addr(__lfw_text_start);
+	uint32_t pd_ram_mask = ~BIT(lfw_block) & NPCX_RAM_BLOCK_PD_MASK;
+
+	if (lfw_block != system_npcx_get_ram_blk_by_lfw_addr(__lfw_text_end)) {
+		LOG_ERR("LFW cannot cross ram blocks!");
+		return;
+	}
+
+	/*
+	 * Set status of pins which connect to flash to tri-state in case
+	 * the leakage current.
+	 */
+	system_npcx_set_flash_pins_tri_state(dev);
+
+	/* Initialize watchdog for reset after wake-up from hibernating */
+	system_npcx_init_watchdog_reset(dev);
+
+	/* Disable ADC and wait for 1000 us to make sure conversion is done */
+	if (IS_ENABLED(CONFIG_ADC))
+		system_npcx_turn_off_adc();
+
+	/* Disable kernel timer */
+	system_npcx_turn_off_kernel_timer();
+
+	/* Disable instant wake up mode for better power consumption */
+	system_npcx_disable_instant_wakeup();
+
+	/*
+	 * Set wake-up input GPIOs and turn off the other sources for better
+	 * power consumption before entering hibernate mode.
+	 */
+	system_npcx_set_wakeup_gpios_before_hibernate();
+
+	/*
+	 * Give the board a chance to do any late stage hibernation work.  This
+	 * is likely going to configure GPIOs for hibernation.  On some boards,
+	 * it's possible that this may not return at all.  On those boards,
+	 * power to the EC is likely being turn off entirely.
+	 */
+	if (board_hibernate_late) {
+		board_hibernate_late();
+	}
+
+	/* Setup a RTC alarm if needed */
+	if (IS_ENABLED(CONFIG_RTC) && (seconds || microseconds)) {
+		system_set_rtc_alarm(seconds, microseconds);
+	}
+
+	/* Clear all pending IRQs in case wake-up immediately after sleeping */
+	for (int i = 0; i < CONFIG_NUM_IRQS; i++) {
+		NVIC_ClearPendingIRQ(i);
+	}
+
+	/* Execute hibernate by lfw which locates in last 32K block ram */
+	system_npcx_hibernate_by_lfw_in_last_ram(dev, pd_ram_mask);
+}
+
+static const char *cros_system_npcx_get_chip_vendor(const struct device *dev)
+{
+	struct mswc_reg *const inst_mswc = HAL_MSWC_INST(dev);
+	static char str[11] = "Unknown-XX";
+	char *p = str + 8;
+	uint8_t fam_id = inst_mswc->SID_CR;
+
+#if DT_NODE_EXISTS(SYSTEM_DT_NODE_SOC_ID_CONFIG)
+	if (fam_id == NPCX_FAMILY_ID) {
+		return "Nuvoton";
+	}
+#endif
+
+	hex2char(fam_id >> 4, p++);
+	hex2char(fam_id & 0xf, p);
+	return str;
+}
+
+static const char *cros_system_npcx_get_chip_name(const struct device *dev)
+{
+	struct mswc_reg *const inst_mswc = HAL_MSWC_INST(dev);
+	static char str[13] = "Unknown-XXXX";
+	char *p = str + 8;
+	uint8_t chip_id = inst_mswc->SRID_CR;
+	uint8_t device_id = inst_mswc->DEVICE_ID_CR;
+
+#if DT_NODE_EXISTS(SYSTEM_DT_NODE_SOC_ID_CONFIG)
+	if (chip_id == NPCX_CHIP_ID && device_id == NPCX_DEVICE_ID) {
+		return CONFIG_SOC;
+	}
+#endif
+
+	hex2char(chip_id >> 4, p++);
+	hex2char(chip_id & 0xf, p++);
+	hex2char(device_id >> 4, p++);
+	hex2char(device_id & 0xf, p);
+	return str;
+}
+
+static const char *cros_system_npcx_get_chip_revision(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+#if DT_NODE_EXISTS(SYSTEM_DT_NODE_SOC_ID_CONFIG)
+	static char rev[NPCX_REVISION_LEN * 2 + 1];
+#else
+	static char rev[1];
+#endif
+	char *p = rev;
+
+#if DT_NODE_EXISTS(SYSTEM_DT_NODE_SOC_ID_CONFIG)
+	/*
+	 * For NPCX7, the revision number is 1 byte.
+	 * For NPCX9 and later chips, the revision number is 4 bytes.
+	 */
+	for (int s = NPCX_REVISION_ADDR + NPCX_REVISION_LEN - 1;
+	     s >= NPCX_REVISION_ADDR; s--) {
+		uint8_t r = *((volatile uint8_t *)s);
+		hex2char(r >> 4, p++);
+		hex2char(r & 0xf, p++);
+	}
+#endif
+	*p = '\0';
+
+	return rev;
+}
+
+#define PSL_NODE DT_INST(0, nuvoton_npcx_power_psl)
+#if DT_NODE_HAS_STATUS(PSL_NODE, okay)
+PINCTRL_DT_DEFINE(PSL_NODE);
+static int cros_system_npcx_configure_psl_in(void)
+{
+	const struct pinctrl_dev_config *pcfg =
+		PINCTRL_DT_DEV_CONFIG_GET(PSL_NODE);
+
+	return pinctrl_apply_state(pcfg, PINCTRL_STATE_SLEEP);
+}
+
+static void cros_system_npcx_psl_out_inactive(void)
+{
+	struct gpio_dt_spec enable = GPIO_DT_SPEC_GET(PSL_NODE, enable_gpios);
+
+	gpio_pin_set_dt(&enable, 1);
+}
+#else
+static int cros_system_npcx_configure_psl_in(void)
+{
+	return -EINVAL;
+}
+
+static void cros_system_npcx_psl_out_inactive(void)
+{
+	return;
+}
+#endif
+
+static void system_npcx_hibernate_by_psl(const struct device *dev,
+					 uint32_t seconds,
+					 uint32_t microseconds)
+{
+	ARG_UNUSED(dev);
+	int ret;
+
+	/*
+	 * TODO(b/178230662): RTC wake-up in PSL mode only support in npcx9
+	 * series. Nuvoton will introduce CLs for it later.
+	 */
+	ARG_UNUSED(seconds);
+	ARG_UNUSED(microseconds);
+
+	/* Configure detection settings of PSL_IN pads first */
+	ret = cros_system_npcx_configure_psl_in();
+	if (ret < 0) {
+		LOG_ERR("PSL_IN pinctrl setup failed (%d)", ret);
+		return;
+	}
+
+	/*
+	 * Give the board a chance to do any late stage hibernation work.  This
+	 * is likely going to configure GPIOs for hibernation.  On some boards,
+	 * it's possible that this may not return at all.  On those boards,
+	 * power to the EC is likely being turn off entirely.
+	 */
+	if (board_hibernate_late)
+		board_hibernate_late();
+
+	/*
+	 * A transition from 0 to 1 of specific IO (GPIO85) data-out bit
+	 * set PSL_OUT to inactive state. Then, it will turn Core Domain
+	 * power supply (VCC1) off for better power consumption.
+	 */
+	cros_system_npcx_psl_out_inactive();
+}
+
+static int cros_system_npcx_get_reset_cause(const struct device *dev)
+{
+	struct cros_system_npcx_data *data = DRV_DATA(dev);
+
+	return data->reset;
+}
+
+static int cros_system_npcx_init(const struct device *dev)
+{
+	struct scfg_reg *const inst_scfg = HAL_SCFG_INST(dev);
+	struct twd_reg *const inst_twd = HAL_TWD_INST(dev);
+	struct cros_system_npcx_data *data = DRV_DATA(dev);
+
+	/* check reset cause */
+	data->reset = UNKNOWN_RST;
+	/* Use scratch bit to check power on reset or VCC1_RST reset. */
+	if (!IS_BIT_SET(inst_scfg->RSTCTL, NPCX_RSTCTL_VCC1_RST_SCRATCH)) {
+		bool is_vcc1_rst =
+			IS_BIT_SET(inst_scfg->RSTCTL, NPCX_RSTCTL_VCC1_RST_STS);
+		data->reset = is_vcc1_rst ? VCC1_RST_PIN : POWERUP;
+	}
+
+	/*
+	 * Set scratch bit to distinguish VCC1_RST# is asserted again
+	 * or not. This bit will be clear automatically when VCC1_RST#
+	 * is asserted or power-on reset occurs.
+	 */
+	inst_scfg->RSTCTL |= BIT(NPCX_RSTCTL_VCC1_RST_SCRATCH);
+
+	if (IS_BIT_SET(inst_scfg->RSTCTL, NPCX_RSTCTL_DBGRST_STS)) {
+		data->reset = DEBUG_RST;
+		/* Clear debugger reset status initially */
+		inst_scfg->RSTCTL |= BIT(NPCX_RSTCTL_DBGRST_STS);
+	}
+	if (IS_BIT_SET(inst_twd->T0CSR, NPCX_T0CSR_WDRST_STS)) {
+		data->reset = WATCHDOG_RST;
+		/* Clear watchdog reset status initially */
+		inst_twd->T0CSR |= BIT(NPCX_T0CSR_WDRST_STS);
+	}
+
+	return 0;
+}
+
+static int cros_system_npcx_soc_reset(const struct device *dev)
+{
+	struct twd_reg *const inst_twd = HAL_TWD_INST(dev);
+
+	/* Disable interrupts to avoid task swaps during reboot */
+	interrupt_disable_all();
+
+	/*
+	 * NPCX chip doesn't have the specific system reset functionality. Use
+	 * watchdog reset as a system reset.
+	 */
+
+	/* Stop the watchdog */
+	system_npcx_watchdog_stop();
+
+	/* Initialize watchdog for reset */
+	system_npcx_init_watchdog_reset(dev);
+
+	/*
+	 * The trigger of a watchdog event by a "too early service" condition.
+	 * When the watchdog is written more than once during three watchdog
+	 * clock cycle.
+	 */
+	inst_twd->WDSDM = 0x5C;
+	inst_twd->WDSDM = 0x5C;
+
+	/* Wait for the soc reset. */
+	while (1) {
+		;
+	}
+
+	/* should never return */
+	return 0;
+}
+
+#if defined(CONFIG_PLATFORM_EC_HIBERNATE_PSL)
+#if DT_HAS_COMPAT_STATUS_OKAY(cros_ec_hibernate_wake_pins)
+#error "cros-ec,hibernate-wake-pins cannot be used with HIBERNATE_PSL"
+#endif
+#else
+#if DT_NODE_HAS_STATUS(PSL_NODE, okay)
+#error "power_ctrl_psl cannot be used with non-HIBERNATE_PSL"
+#endif
+#endif
+
+static int cros_system_npcx_hibernate(const struct device *dev,
+				      uint32_t seconds, uint32_t microseconds)
+{
+	/* Disable interrupt first */
+	interrupt_disable_all();
+
+	/* Stop the watchdog */
+	system_npcx_watchdog_stop();
+
+	/* Enter hibernate mode */
+	if (IS_ENABLED(CONFIG_PLATFORM_EC_HIBERNATE_PSL)) {
+		system_npcx_hibernate_by_psl(dev, seconds, microseconds);
+	} else {
+		system_npcx_hibernate_by_disable_ram(dev, seconds,
+						     microseconds);
+	}
+
+	return 0;
+}
+
+__maybe_unused static uint64_t
+cros_system_npcx_deep_sleep_ticks(const struct device *dev)
+{
+	return npcx_clock_get_sleep_ticks();
+}
+
+static struct cros_system_npcx_data cros_system_npcx_dev_data;
+
+static const struct cros_system_npcx_config cros_system_dev_cfg = {
+	.base_scfg = DT_REG_ADDR(DT_INST(0, nuvoton_npcx_scfg)),
+	.base_twd = DT_REG_ADDR(DT_INST(0, nuvoton_npcx_watchdog)),
+	.base_mswc =
+		DT_REG_ADDR_BY_NAME(DT_INST(0, nuvoton_npcx_host_sub), mswc),
+};
+
+static const struct cros_system_driver_api cros_system_driver_npcx_api = {
+	.get_reset_cause = cros_system_npcx_get_reset_cause,
+	.soc_reset = cros_system_npcx_soc_reset,
+	.hibernate = cros_system_npcx_hibernate,
+	.chip_vendor = cros_system_npcx_get_chip_vendor,
+	.chip_name = cros_system_npcx_get_chip_name,
+	.chip_revision = cros_system_npcx_get_chip_revision,
+#ifdef CONFIG_PM
+	.deep_sleep_ticks = cros_system_npcx_deep_sleep_ticks,
+#endif
+};
+
+DEVICE_DEFINE(cros_system_npcx_0, "CROS_SYSTEM", cros_system_npcx_init, NULL,
+	      &cros_system_npcx_dev_data, &cros_system_dev_cfg, PRE_KERNEL_1,
+	      CONFIG_CROS_SYSTEM_NPCX_INIT_PRIORITY,
+	      &cros_system_driver_npcx_api);
+
+#if DT_NODE_EXISTS(DT_NODELABEL(dbg))
+#define HAL_DBG_REG_BASE_ADDR \
+	((struct dbg_reg *)DT_REG_ADDR(DT_INST(0, nuvoton_npcx_cros_dbg)))
+
+#define DBG_NODE DT_NODELABEL(dbg)
+#define DBG_PINCTRL_PH DT_PHANDLE_BY_IDX(DBG_NODE, pinctrl_0, 0)
+#define DBG_ALT_FILED(f) DT_PHA_BY_IDX(DBG_PINCTRL_PH, alts, 0, f)
+
+PINCTRL_DT_DEFINE(DBG_NODE);
+
+static int jtag_init(void)
+{
+	struct dbg_reg *const dbg_reg_base = HAL_DBG_REG_BASE_ADDR;
+	const struct pinctrl_dev_config *pcfg =
+		PINCTRL_DT_DEV_CONFIG_GET(DBG_NODE);
+	dbg_reg_base->DBGCTRL = 0x04;
+	dbg_reg_base->DBGFRZEN3 &= ~BIT(NPCX_DBGFRZEN3_GLBL_FRZ_DIS);
+	if (DT_NODE_HAS_STATUS(DT_NODELABEL(dbg), okay)) {
+		int ret;
+
+		ret = pinctrl_apply_state(pcfg, PINCTRL_STATE_DEFAULT);
+		if (ret < 0) {
+			LOG_ERR("DBG pinctrl setup failed (%d)", ret);
+		}
+		return ret;
+	}
+
+	return 0;
+}
+#if CONFIG_KERNEL_INIT_PRIORITY_DEFAULT >= 41
+#error "jtag_init must be called after default kernel init"
+#endif
+SYS_INIT(jtag_init, PRE_KERNEL_1, 41);
+#endif /* DT_NODE_EXISTS(DT_NODELABEL(dbg)) */
diff --git a/zephyr/drivers/cros_system/cros_system_stm32.c b/zephyr/drivers/cros_system/cros_system_stm32.c
new file mode 100644
index 0000000000..bc42909666
--- /dev/null
+++ b/zephyr/drivers/cros_system/cros_system_stm32.c
@@ -0,0 +1,150 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define DT_DRV_COMPAT st_stm32_rcc
+
+#include "drivers/cros_system.h"
+#include "system.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/hwinfo.h>
+#include <zephyr/drivers/watchdog.h>
+#include <zephyr/sys/reboot.h>
+
+/* Driver data */
+struct cros_system_stm32_data {
+	int reset; /* reset cause */
+};
+
+#define DRV_DATA(dev) ((struct cros_system_stm32_data *)(dev)->data)
+
+static const struct device *const watchdog =
+	DEVICE_DT_GET(DT_CHOSEN(cros_ec_watchdog));
+
+static const char *cros_system_stm32_get_chip_vendor(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	return "st";
+}
+
+static const char *cros_system_stm32_get_chip_name(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	return CONFIG_SOC;
+}
+
+static const char *cros_system_stm32_get_chip_revision(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	return "";
+}
+
+static int cros_system_stm32_get_reset_cause(const struct device *dev)
+{
+	struct cros_system_stm32_data *data = DRV_DATA(dev);
+
+	return data->reset;
+}
+
+static int cros_system_stm32_soc_reset(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	uint32_t chip_reset_flags = chip_read_reset_flags();
+
+	/*
+	 * We are going to reboot MCU here, so we need to disable caches here.
+	 * SCB_DisableDCache also flushes data cache lines.
+	 */
+#ifdef CONFIG_DCACHE
+	SCB_DisableDCache();
+#endif
+
+#ifdef CONFIG_ICACHE
+	SCB_DisableICache();
+#endif
+
+	if (chip_reset_flags & EC_RESET_FLAG_HARD) {
+		/*
+		 * Set minimal watchdog timeout - 1 millisecond.
+		 * STM32 IWDG can be set for lower value, but we are limited by
+		 * Zephyr API.
+		 */
+		struct wdt_timeout_cfg minimal_timeout = { .window.max = 1 };
+
+		/* Setup watchdog */
+		wdt_install_timeout(watchdog, &minimal_timeout);
+
+		/* Apply the changes (the driver will reload watchdog) */
+		wdt_setup(watchdog, 0);
+
+		/* Spin and wait for reboot */
+		while (1)
+			;
+	} else {
+		/* Reset implementation for ARM ignores the reset type */
+		sys_reboot(0);
+	}
+
+	/* Should never return */
+	return 0;
+}
+
+static uint64_t cros_system_stm32_deep_sleep_ticks(const struct device *dev)
+{
+	/* Deep sleep is not supported for now */
+	return 0;
+}
+
+static int cros_system_stm32_init(const struct device *dev)
+{
+	struct cros_system_stm32_data *data = DRV_DATA(dev);
+	uint32_t reset_cause;
+
+	data->reset = UNKNOWN_RST;
+	hwinfo_get_reset_cause(&reset_cause);
+
+	/* Clear the hardware reset cause. */
+	hwinfo_clear_reset_cause();
+
+	if (reset_cause & RESET_WATCHDOG) {
+		data->reset = WATCHDOG_RST;
+	} else if (reset_cause & RESET_SOFTWARE) {
+		/* Use DEBUG_RST because it maps to EC_RESET_FLAG_SOFT. */
+		data->reset = DEBUG_RST;
+	} else if (reset_cause & RESET_POR) {
+		data->reset = POWERUP;
+	} else if (reset_cause & RESET_PIN) {
+		data->reset = VCC1_RST_PIN;
+	}
+
+	return 0;
+}
+
+static struct cros_system_stm32_data cros_system_stm32_dev_data;
+
+static const struct cros_system_driver_api cros_system_driver_stm32_api = {
+	.get_reset_cause = cros_system_stm32_get_reset_cause,
+	.soc_reset = cros_system_stm32_soc_reset,
+	.chip_vendor = cros_system_stm32_get_chip_vendor,
+	.chip_name = cros_system_stm32_get_chip_name,
+	.chip_revision = cros_system_stm32_get_chip_revision,
+#ifdef CONFIG_PM
+	.deep_sleep_ticks = cros_system_stm32_deep_sleep_ticks,
+#endif
+};
+
+DEVICE_DEFINE(cros_system_stm32_0, "CROS_SYSTEM", cros_system_stm32_init, NULL,
+	      &cros_system_stm32_dev_data, NULL, PRE_KERNEL_1,
+	      CONFIG_CROS_SYSTEM_STM32_INIT_PRIORITY,
+	      &cros_system_driver_stm32_api);
+
+#if CONFIG_CROS_SYSTEM_STM32_INIT_PRIORITY >= \
+	CONFIG_PLATFORM_EC_SYSTEM_PRE_INIT_PRIORITY
+#error "CROS_SYSTEM must initialize before the SYSTEM_PRE initialization"
+#endif
diff --git a/zephyr/drivers/cros_system/cros_system_xec.c b/zephyr/drivers/cros_system/cros_system_xec.c
new file mode 100644
index 0000000000..7cbf0330e8
--- /dev/null
+++ b/zephyr/drivers/cros_system/cros_system_xec.c
@@ -0,0 +1,440 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "bbram.h"
+#include "gpio/gpio_int.h"
+#include "system.h"
+#include "system_chip.h"
+
+#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <zephyr/drivers/interrupt_controller/intc_mchp_xec_ecia.h>
+#include <zephyr/drivers/watchdog.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/util.h>
+
+#include <drivers/cros_system.h>
+#include <soc.h>
+#include <soc/microchip_xec/reg_def_cros.h>
+
+LOG_MODULE_REGISTER(cros_system, LOG_LEVEL_ERR);
+
+/* Modules Map */
+#define STRUCT_ADC_REG_BASE_ADDR \
+	((struct adc_regs *)(DT_REG_ADDR(DT_NODELABEL(adc0))))
+
+#define STRUCT_UART_REG_BASE_ADDR \
+	((struct uart_regs *)(DT_REG_ADDR(DT_NODELABEL(uart0))))
+
+#define STRUCT_ECS_REG_BASE_ADDR \
+	((struct ecs_regs *)(DT_REG_ADDR(DT_NODELABEL(ecs))))
+
+#define STRUCT_TIMER4_REG_BASE_ADDR \
+	((struct btmr_regs *)(DT_REG_ADDR(DT_NODELABEL(timer4))))
+
+#define STRUCT_ESPI_REG_BASE_ADDR \
+	((struct espi_iom_regs *)(DT_REG_ADDR(DT_NODELABEL(espi0))))
+
+#define STRUCT_KBD_REG_BASE_ADDR \
+	((struct kscan_regs *)(DT_REG_ADDR(DT_NODELABEL(cros_kb_raw))))
+
+#define STRUCT_QMSPI_REG_BASE_ADDR \
+	((struct qmspi_regs *)(DT_REG_ADDR(DT_NODELABEL(spi0))))
+
+#define STRUCT_PWM_REG_BASE_ADDR \
+	((struct pwm_regs *)(DT_REG_ADDR(DT_NODELABEL(pwm0))))
+
+#define STRUCT_TACH_REG_BASE_ADDR \
+	((struct tach_regs *)(DT_REG_ADDR(DT_NODELABEL(tach0))))
+
+#define STRUCT_HTMR0_REG_BASE_ADDR \
+	((struct htmr_regs *)(DT_REG_ADDR(DT_NODELABEL(hibtimer0))))
+
+/* Driver config */
+struct cros_system_xec_config {
+	/* hardware module base address */
+	uintptr_t base_pcr;
+	uintptr_t base_vbr;
+	uintptr_t base_wdog;
+};
+
+/* Driver data */
+struct cros_system_xec_data {
+	int reset; /* reset cause */
+};
+
+/* Driver convenience defines */
+#define DRV_CONFIG(dev) ((const struct cros_system_xec_config *)(dev)->config)
+#define DRV_DATA(dev) ((struct cros_system_xec_data *)(dev)->data)
+
+#define HAL_PCR_INST(dev) (struct pcr_regs *)(DRV_CONFIG(dev)->base_pcr)
+#define HAL_VBATR_INST(dev) (struct vbatr_regs *)(DRV_CONFIG(dev)->base_vbr)
+#define HAL_WDOG_INST(dev) (struct wdt_regs *)(DRV_CONFIG(dev)->base_wdog)
+
+/* Get saved reset flag address in battery-backed ram */
+#define BBRAM_SAVED_RESET_FLAG_ADDR                     \
+	(DT_REG_ADDR(DT_INST(0, microchip_xec_bbram)) + \
+	 BBRAM_REGION_OFFSET(offset)
+
+/* Soc specific system local functions */
+static int system_xec_watchdog_stop(void)
+{
+	if (IS_ENABLED(CONFIG_WATCHDOG)) {
+		const struct device *wdt_dev =
+			DEVICE_DT_GET(DT_NODELABEL(wdog));
+		if (!device_is_ready(wdt_dev)) {
+			LOG_ERR("Error: device %s is not ready", wdt_dev->name);
+			return -ENODEV;
+		}
+
+		wdt_disable(wdt_dev);
+	}
+
+	return 0;
+}
+
+static const char *cros_system_xec_get_chip_vendor(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	return "MCHP";
+}
+
+/* TODO - return specific chip name such as MEC1727 or MEC1723 */
+static const char *cros_system_xec_get_chip_name(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	return "MEC172X";
+}
+
+/* TODO return chip revision from HW as an ASCII string */
+static const char *cros_system_xec_get_chip_revision(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	return "B0";
+}
+
+static int cros_system_xec_get_reset_cause(const struct device *dev)
+{
+	struct cros_system_xec_data *data = DRV_DATA(dev);
+
+	return data->reset;
+}
+
+/* MCHP TODO check and verify this logic for all corner cases:
+ * Someone doing ARM Vector Reset insead of SYSRESETREQ or HW reset.
+ * Does NRESETIN# status get set also on power on from no power state?
+ */
+static int cros_system_xec_init(const struct device *dev)
+{
+	struct vbatr_regs *vbr = HAL_VBATR_INST(dev);
+	struct cros_system_xec_data *data = DRV_DATA(dev);
+	uint32_t pfsr = vbr->PFRS;
+
+	if (IS_BIT_SET(pfsr, MCHP_VBATR_PFRS_WDT_POS)) {
+		data->reset = WATCHDOG_RST;
+		vbr->PFRS = BIT(MCHP_VBATR_PFRS_WDT_POS);
+	} else if (IS_BIT_SET(pfsr, MCHP_VBATR_PFRS_SYSRESETREQ_POS)) {
+		data->reset = DEBUG_RST;
+		vbr->PFRS = BIT(MCHP_VBATR_PFRS_SYSRESETREQ_POS);
+	} else if (IS_BIT_SET(pfsr, MCHP_VBATR_PFRS_RESETI_POS)) {
+		data->reset = VCC1_RST_PIN;
+	} else {
+		data->reset = POWERUP;
+	}
+
+	return 0;
+}
+
+noreturn static int cros_system_xec_soc_reset(const struct device *dev)
+{
+	struct pcr_regs *const pcr = HAL_PCR_INST(dev);
+
+	/* Disable interrupts to avoid task swaps during reboot */
+	interrupt_disable_all();
+	/* Stop the watchdog */
+	system_xec_watchdog_stop();
+
+	/* Trigger chip reset */
+	pcr->SYS_RST |= MCHP_PCR_SYS_RESET_NOW;
+	/* Wait for the soc reset */
+	while (1)
+		;
+	/* should never return */
+	/* return 0; */
+}
+
+/* Configure wakeup GPIOs in hibernate (from hibernate-wake-pins). */
+static void system_xec_set_wakeup_gpios_before_hibernate(void)
+{
+#if DT_NODE_EXISTS(SYSTEM_DT_NODE_HIBERNATE_CONFIG)
+
+/*
+ * Get the interrupt DTS node for this wakeup pin
+ */
+#define WAKEUP_INT(id, prop, idx) DT_PHANDLE_BY_IDX(id, prop, idx)
+
+/*
+ * Get the named-gpio node for this wakeup pin by reading the
+ * irq-gpio property from the interrupt node.
+ */
+#define WAKEUP_NGPIO(id, prop, idx) \
+	DT_PHANDLE(WAKEUP_INT(id, prop, idx), irq_pin)
+
+/*
+ * Reset and re-enable interrupts on this wake pin.
+ */
+#define WAKEUP_SETUP(id, prop, idx)                                     \
+	do {                                                            \
+		gpio_pin_configure_dt(                                  \
+			GPIO_DT_FROM_NODE(WAKEUP_NGPIO(id, prop, idx)), \
+			GPIO_INPUT);                                    \
+		gpio_enable_dt_interrupt(                               \
+			GPIO_INT_FROM_NODE(WAKEUP_INT(id, prop, idx))); \
+	} while (0);
+
+	/*
+	 * For all the wake-pins, re-init the GPIO and re-enable the interrupt.
+	 */
+	DT_FOREACH_PROP_ELEM(SYSTEM_DT_NODE_HIBERNATE_CONFIG, wakeup_irqs,
+			     WAKEUP_SETUP);
+
+#undef WAKEUP_INT
+#undef WAKEUP_NGPIO
+#undef WAKEUP_SETUP
+
+#endif
+}
+
+/**
+ * initialization of Hibernation timer 0
+ * GIRQ=23, aggregator bit = 16, Direct NVIC = 112
+ * NVIC direct connect interrupts are used for all peripherals
+ * (exception GPIO's)
+ */
+static void htimer_init(void)
+{
+	struct htmr_regs *htmr0 = STRUCT_HTMR0_REG_BASE_ADDR;
+
+	/* disable HT0 at beginning */
+	htmr0->PRLD = 0U;
+	mchp_soc_ecia_girq_src_clr(MCHP_GIRQ23_ID, MCHP_HTMR_0_GIRQ_POS);
+	mchp_soc_ecia_girq_src_en(MCHP_GIRQ23_ID, MCHP_HTMR_0_GIRQ_POS);
+
+	/* enable NVIC interrupt for HT0 */
+	irq_enable(MCHP_HTMR_0_GIRQ_NVIC_DIRECT);
+}
+
+/**
+ * Use hibernate module to set up an htimer interrupt at a given
+ * time from now
+ *
+ * @param seconds      Number of seconds before htimer interrupt
+ * @param microseconds Number of microseconds before htimer interrupt
+ * @note hibernation timer input clock is 32.768KHz.
+ */
+static void system_set_htimer_alarm(uint32_t seconds, uint32_t microseconds)
+{
+	uint32_t hcnt, ns;
+	uint8_t hctrl;
+	struct htmr_regs *htmr0 = STRUCT_HTMR0_REG_BASE_ADDR;
+
+	/* disable HT0 */
+	htmr0->PRLD = 0U;
+
+	if (microseconds > 1000000ul) {
+		ns = (microseconds / 1000000ul);
+		microseconds %= 1000000ul;
+		if ((0xfffffffful - seconds) > ns)
+			seconds += ns;
+		else
+			seconds = 0xfffffffful;
+	}
+
+	/*
+	 * Hibernation timer input clock is 32.768KHz.
+	 * Control register bit[0] selects the divider.
+	 * If bit[0] is 0, divide by 1 for 30.5 us per LSB for a maximum of
+	 * 65535 * 30.5 us = 1998817.5 us or 32.786 counts per second
+	 * If bit[0] is 1, divide by 4096 for 0.125 s per LSB for a maximum
+	 * of ~2 hours, 65535 * 0.125 s ~ 8192 s = 2.27 hours
+	 */
+	if (seconds > 1) {
+		hcnt = (seconds << 3); /* divide by 0.125 */
+		if (hcnt > 0xfffful)
+			hcnt = 0xfffful;
+		hctrl = 1;
+	} else {
+		/*
+		 * approximate(~2% error) as seconds is 0 or 1
+		 * seconds / 30.5e-6 + microseconds / 30.5
+		 */
+		hcnt = (seconds << 15) + (microseconds >> 5) +
+		       (microseconds >> 10);
+		hctrl = 0;
+	}
+
+	htmr0->CTRL = hctrl;
+	htmr0->PRLD = hcnt;
+}
+
+/* Put the EC in hibernate (lowest EC power state). */
+noreturn static int cros_system_xec_hibernate(const struct device *dev,
+					      uint32_t seconds,
+					      uint32_t microseconds)
+{
+	struct pcr_regs *const pcr = HAL_PCR_INST(dev);
+#ifdef CONFIG_ADC_XEC_V2
+	struct adc_regs *adc0 = STRUCT_ADC_REG_BASE_ADDR;
+#endif
+#ifdef CONFIG_UART_XEC
+	struct uart_regs *uart0 = STRUCT_UART_REG_BASE_ADDR;
+#endif
+	struct ecs_regs *ecs = STRUCT_ECS_REG_BASE_ADDR;
+	struct btmr_regs *btmr4 = STRUCT_TIMER4_REG_BASE_ADDR;
+	struct espi_iom_regs *espi0 = STRUCT_ESPI_REG_BASE_ADDR;
+#ifdef CONFIG_CROS_KB_RAW_XEC
+	struct kscan_regs *kbd = STRUCT_KBD_REG_BASE_ADDR;
+#endif
+	struct qmspi_regs *qmspi0 = STRUCT_QMSPI_REG_BASE_ADDR;
+#if defined(CONFIG_PWM_XEC)
+	struct pwm_regs *pwm0 = STRUCT_PWM_REG_BASE_ADDR;
+#endif
+#if defined(CONFIG_TACH_XEC)
+	struct tach_regs *tach0 = STRUCT_TACH_REG_BASE_ADDR;
+#endif
+	struct ecia_regs *ecia = (struct ecia_regs *)(ECIA_BASE_ADDR);
+	int i;
+
+	/* Disable interrupt first */
+	interrupt_disable_all();
+	/* Stop the watchdog */
+	system_xec_watchdog_stop();
+
+	/* Disable all individaul block interrupt and source */
+	for (i = 0; i < MCHP_GIRQ_IDX_MAX; ++i) {
+		ecia->GIRQ[i].EN_CLR = 0xffffffff;
+		ecia->GIRQ[i].SRC = 0xffffffff;
+	}
+
+	/* Disable and clear all NVIC interrupt pending */
+	for (i = 0; i < MCHP_MAX_NVIC_EXT_INPUTS; ++i) {
+		mchp_xec_ecia_nvic_clr_pend(i);
+	}
+
+	/* Disable blocks */
+#ifdef CONFIG_ADC_XEC_V2
+	/* Disable ADC */
+	adc0->CONTROL &= ~(MCHP_ADC_CTRL_ACTV);
+#endif
+	/* Disable eSPI */
+	espi0->ACTV &= ~0x01;
+#ifdef CONFIG_CROS_KB_RAW_XEC
+	/* Disable Keyboard Scanner */
+	kbd->KSO_SEL &= ~(MCHP_KSCAN_KSO_EN);
+#endif
+#ifdef CONFIG_I2C
+	/* Disable SMB / I2C */
+	for (i = 0; i < MCHP_I2C_SMB_INSTANCES; i++) {
+		uint32_t addr =
+			MCHP_I2C_SMB_BASE_ADDR(i) + MCHP_I2C_SMB_CFG_OFS;
+		uint32_t regval = sys_read32(addr);
+
+		sys_write32(regval & ~(MCHP_I2C_SMB_CFG_ENAB), addr);
+	}
+#endif
+	/* Disable QMSPI */
+	qmspi0->MODE &= ~MCHP_QMSPI_M_ACTIVATE;
+#if defined(CONFIG_PWM_XEC)
+	/* Disable PWM0 */
+	pwm0->CONFIG &= ~MCHP_PWM_CFG_ENABLE;
+#endif
+#if defined(CONFIG_TACH_XEC)
+	/* Disable TACH0 */
+	tach0->CONTROL &= ~MCHP_TACH_CTRL_EN;
+#endif
+#if defined(CONFIG_TACH_XEC) || defined(CONFIG_PWM_XEC)
+	/* This low-speed clock derived from the 48MHz clock domain is used as
+	 * a time base for PWMs and TACHs
+	 * Set SLOW_CLOCK_DIVIDE = CLKOFF to save additional power
+	 */
+	pcr->SLOW_CLK_CTRL &=
+		(~MCHP_PCR_SLOW_CLK_CTRL_100KHZ & MCHP_PCR_SLOW_CLK_CTRL_MASK);
+#endif
+	/* Disable timers - 32bit timer 0 */
+	btmr4->CTRL &= ~MCHP_BTMR_CTRL_ENABLE;
+	/*
+	 * Give the board a chance to do any late stage hibernation work.  This
+	 * is likely going to configure GPIOs for hibernation.  On some boards,
+	 * it's possible that this may not return at all.  On those boards,
+	 * power to the EC is likely being turn off entirely.
+	 */
+	if (board_hibernate_late) {
+		board_hibernate_late();
+	}
+
+	/* Setup wakeup GPIOs for hibernate */
+	system_xec_set_wakeup_gpios_before_hibernate();
+	/* Init htimer and enable interrupt if times are not 0 */
+	if (seconds || microseconds) {
+		htimer_init();
+		system_set_htimer_alarm(seconds, microseconds);
+	}
+
+#ifdef CONFIG_UART_XEC
+	/* Disable UART0 */
+	/* Flush console before hibernating */
+	cflush();
+	uart0->ACTV &= ~(MCHP_UART_LD_ACTIVATE);
+#endif
+
+	/* Disable JATG and RTM */
+	ecs->DEBUG_CTRL = 0;
+	ecs->ETM_CTRL = 0;
+
+	/*
+	 * Set sleep state
+	 * arm sleep state to trigger on next WFI
+	 */
+	pcr->SYS_SLP_CTRL |= MCHP_PCR_SYS_SLP_HEAVY;
+	/*
+	 * Set PRIMASK = 1 so on wake the CPU will not vector to any ISR.
+	 * Set BASEPRI = 0 to allow any priority to wake.
+	 */
+	__set_BASEPRI(0);
+	/* triggers sleep hardware */
+	__WFI();
+	__NOP();
+	__NOP();
+
+	/* Reset EC chip */
+	cros_system_xec_soc_reset(dev);
+
+	/* Should not reach here... */
+	/* return 0; */
+}
+
+static struct cros_system_xec_data cros_system_xec_dev_data;
+
+static const struct cros_system_xec_config cros_system_dev_cfg = {
+	.base_pcr = DT_REG_ADDR_BY_NAME(DT_INST(0, microchip_xec_pcr), pcrr),
+	.base_vbr = DT_REG_ADDR_BY_NAME(DT_INST(0, microchip_xec_pcr), vbatr),
+	.base_wdog = DT_REG_ADDR(DT_INST(0, microchip_xec_watchdog)),
+};
+
+static const struct cros_system_driver_api cros_system_driver_xec_api = {
+	.get_reset_cause = cros_system_xec_get_reset_cause,
+	.soc_reset = cros_system_xec_soc_reset,
+	.hibernate = cros_system_xec_hibernate,
+	.chip_vendor = cros_system_xec_get_chip_vendor,
+	.chip_name = cros_system_xec_get_chip_name,
+	.chip_revision = cros_system_xec_get_chip_revision,
+};
+
+DEVICE_DEFINE(cros_system_xec_0, "CROS_SYSTEM", cros_system_xec_init, NULL,
+	      &cros_system_xec_dev_data, &cros_system_dev_cfg, PRE_KERNEL_1,
+	      CONFIG_CROS_SYSTEM_XEC_INIT_PRIORITY,
+	      &cros_system_driver_xec_api);
diff --git a/zephyr/dts/bindings/adc/named-adc-channels.yaml b/zephyr/dts/bindings/adc/named-adc-channels.yaml
new file mode 100644
index 0000000000..5d4873746d
--- /dev/null
+++ b/zephyr/dts/bindings/adc/named-adc-channels.yaml
@@ -0,0 +1,131 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: ADC parent node
+
+compatible: "named-adc-channels"
+
+child-binding:
+  description: Named ADCs child node
+  properties:
+    io-channels:
+      required: true
+      type: phandle-array
+      description: IO channels specifiers ADC channel used
+    mul:
+      required: false
+      type: int
+      default: 1
+      description: Multiplication factor of ADC measurement
+    div:
+      required: false
+      type: int
+      default: 1
+      description: Division factor of ADC measurement
+    gain:
+      required: false
+      type: string
+      description:
+        Gain selection for the ADC channel. Source of valid gain settings is
+        "enum adc_gain" found in <zephyr-base>/include/drivers/adc.h
+      enum:
+        - ADC_GAIN_1_6
+        - ADC_GAIN_1_5
+        - ADC_GAIN_1_4
+        - ADC_GAIN_1_3
+        - ADC_GAIN_1_2
+        - ADC_GAIN_2_3
+        - ADC_GAIN_1
+        - ADC_GAIN_2
+        - ADC_GAIN_3
+        - ADC_GAIN_4
+        - ADC_GAIN_8
+        - ADC_GAIN_16
+        - ADC_GAIN_32
+        - ADC_GAIN_64
+        - ADC_GAIN_128
+      default: ADC_GAIN_1
+    reference:
+      required: false
+      type: string
+      description:
+        Sets the reference voltage for the ADC channel. Source of valid
+        reference voltages is "enum adc_reference" found in
+        <zephyr-base>/include/drivers/adc.
+      enum:
+        - ADC_REF_VDD_1
+        - ADC_REF_VDD_1_2
+        - ADC_REF_VDD_1_3
+        - ADC_REF_VDD_1_4
+        - ADC_REF_INTERNAL
+        - ADC_REF_EXTERNAL0
+        - ADC_REF_EXTERNAL1
+      default: ADC_REF_INTERNAL
+    acquisition-time:
+      required: false
+      type: int
+      description:
+        Set the acquisition time for ADC conversion. Use the ADC_ACQ_TIME macro
+        to compose this value. If the hardware doesn't support a configurable
+        acquisition time, use ADC_ACQ_TIME_DEFAULT (0).
+      default: 0
+    differential:
+      required: false
+      type: boolean
+      description:
+        Set the ADC acquisition mode to differential. Default mode is
+        single-ended acquisition.
+    enum-name:
+      type: string
+      required: true
+      description:
+        Enum values used in the source code to refer to the ADC channels
+      enum:
+        - ADC_AMON_BMON
+        - ADC_BASE_DET
+        - ADC_BOARD_ID_0
+        - ADC_BOARD_ID_1
+        - ADC_CORE_IMON1
+        - ADC_ID_0
+        - ADC_ID_1
+        - ADC_PMON
+        - ADC_PP1050_PROC
+        - ADC_PP3300_S5
+        - ADC_PSYS
+        - ADC_SOC_IMON2
+        - ADC_TEMP_SENSOR_1
+        - ADC_TEMP_SENSOR_2
+        - ADC_TEMP_SENSOR_3
+        - ADC_TEMP_SENSOR_4
+        - ADC_TEMP_SENSOR_5
+        - ADC_TEMP_SENSOR_6
+        - ADC_TEMP_SENSOR_CHARGER
+        - ADC_TEMP_SENSOR_DDR_SOC
+        - ADC_TEMP_SENSOR_FAN
+        - ADC_TEMP_SENSOR_MEMORY
+        - ADC_TEMP_SENSOR_PP3300_REGULATOR
+        - ADC_TEMP_SENSOR_SOC
+        - ADC_TEMP_SENSOR_1_DDR_SOC
+        - ADC_TEMP_SENSOR_2_AMBIENT
+        - ADC_TEMP_SENSOR_3_CHARGER
+        - ADC_TEMP_SENSOR_4_WWAN
+        - ADC_VBUS
+        - ADC_VBUS_C0
+        - ADC_VBUS_C1
+        - ADC_EVB_CH_0
+        - ADC_EVB_CH_1
+        - ADC_EVB_CH_2
+        - ADC_EVB_CH_3
+        - ADC_EVB_CH_4
+        - ADC_MAIN_BOARD_ID
+        - ADC_HUB_BOARD_ID
+        - ADC_GPU_BOARD_ID_0
+        - ADC_GPU_BOARD_ID_1
+        - ADC_HUB_DEVICE_ID_0
+        - ADC_HUB_DEVICE_ID_1
+        - ADC_HUB_DEVICE_ID_2
+        - ADC_ADAPTER_CURRENT
+        - ADC_TOUCHPAD_ID
+        - ADC_AUDIO_ID
+        - ADC_VCIN1_BATT_TEMP
diff --git a/zephyr/dts/bindings/battery/aec,5477109.yaml b/zephyr/dts/bindings/battery/aec,5477109.yaml
new file mode 100644
index 0000000000..0017def088
--- /dev/null
+++ b/zephyr/dts/bindings/battery/aec,5477109.yaml
@@ -0,0 +1,54 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "AEC 5477109"
+compatible: "aec,5477109"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "aec,5477109"
+
+  # Fuel gauge
+  manuf_name:
+    default: "AEC"
+  device_name:
+    default: "5477109"
+  ship_mode_reg_addr:
+    default: 0x00
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  # Documentation: b/182847979
+  fet_mfgacc_support:
+    default: 0
+  fet_reg_addr:
+    default: 0x0
+  fet_reg_mask:
+    default: 0x2000
+  fet_disconnect_val:
+    default: 0x2000
+
+  # Battery info
+  voltage_max:
+    default: 8700
+  voltage_normal:
+    default: 7600
+  voltage_min:
+    default: 6000
+  precharge_current:
+    default: 100
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 45
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 50
+  discharging_min_c:
+    default: -20
+  discharging_max_c:
+    default: 60
diff --git a/zephyr/dts/bindings/battery/atl,cfd72.yaml b/zephyr/dts/bindings/battery/atl,cfd72.yaml
new file mode 100644
index 0000000000..25ae33ecfc
--- /dev/null
+++ b/zephyr/dts/bindings/battery/atl,cfd72.yaml
@@ -0,0 +1,53 @@
+description: "ATL-NVT ATL-ATL3.66 DELL CFD72"
+compatible: "atl,cfd72"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "atl,cfd72"
+
+  # Fuel Gauge
+  manuf_name:
+    default: "ATL-ATL3.66"
+  device_name:
+    default: "DELL CFD72"
+  ship_mode_reg_addr:
+    default: 0x00
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  fet_mfgacc_support:
+    default: 0
+  fet_reg_addr:
+    default: 0x43
+  fet_reg_mask:
+    default: 0x0001
+  fet_disconnect_val:
+    default: 0x0000
+  fet_cfet_mask:
+    default: 0x0002
+  fet_cfet_off_val:
+    default: 0x0000
+
+  # Battery info
+  voltage_max:
+    default: 17600
+  voltage_normal:
+    default: 15000
+  voltage_min:
+    default: 12000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 45
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 50
+  discharging_min_c:
+    default: -20
+  discharging_max_c:
+    default: 70
diff --git a/zephyr/dts/bindings/battery/atl,framework55w.yaml b/zephyr/dts/bindings/battery/atl,framework55w.yaml
new file mode 100644
index 0000000000..9b613f3202
--- /dev/null
+++ b/zephyr/dts/bindings/battery/atl,framework55w.yaml
@@ -0,0 +1,53 @@
+description: "ATL NVT Framework Laptop"
+compatible: "atl,framework55w"
+
+include: battery-smart.yaml
+
+properties:
+   enum-name:
+      type: string
+      default: "atl,framework55w"
+
+   # Fuel gauge
+   manuf_name:
+      default: "NVT"
+   device_name:
+      default: "Framework Laptop"
+   ship_mode_reg_addr:
+      default: 0x00
+   ship_mode_reg_data:
+      default: [ 0x0010, 0x0010 ]
+   # Bit 0 - DFET - Condition of D-FET ( 0=OFF, 1=ON )
+   # Bit 1 - CFET - Condition of C-FET ( 0=OFF, 1=ON )
+   fet_mfgacc_support:
+      default: 1
+   fet_reg_mask:
+      default: 0x0002
+   fet_disconnect_val:
+      default: 0x0000
+   fet_cfet_mask:
+      default: 0x0004
+   fet_cfet_off_val:
+      default: 0x0000
+
+   # Battery info
+   voltage_max:
+      default: 17600
+   voltage_normal:
+      default: 15400
+   voltage_min:
+      default: 12000
+   precharge_current:
+      default: 72
+   start_charging_min_c:
+      default: 0
+   start_charging_max_c:
+      default: 55
+   charging_min_c:
+      default: 0
+   charging_max_c:
+      default: 55
+   discharging_min_c:
+      default: 0
+   discharging_max_c:
+      default: 70
diff --git a/zephyr/dts/bindings/battery/atl,framework61w.yaml b/zephyr/dts/bindings/battery/atl,framework61w.yaml
new file mode 100644
index 0000000000..fd9d8d4fdc
--- /dev/null
+++ b/zephyr/dts/bindings/battery/atl,framework61w.yaml
@@ -0,0 +1,53 @@
+description: "ATL NVT Framework Laptop"
+compatible: "atl,framework61w"
+
+include: battery-smart.yaml
+
+properties:
+   enum-name:
+      type: string
+      default: "atl,framework61w"
+
+   # Fuel gauge
+   manuf_name:
+      default: "NVT"
+   device_name:
+      default: "FRANGWAT01"
+   ship_mode_reg_addr:
+      default: 0x00
+   ship_mode_reg_data:
+      default: [ 0x0010, 0x0010 ]
+   # Bit 0 - DFET - Condition of D-FET ( 0=OFF, 1=ON )
+   # Bit 1 - CFET - Condition of C-FET ( 0=OFF, 1=ON )
+   fet_mfgacc_support:
+      default: 1
+   fet_reg_mask:
+      default: 0x0002
+   fet_disconnect_val:
+      default: 0x0000
+   fet_cfet_mask:
+      default: 0x0004
+   fet_cfet_off_val:
+      default: 0x0000
+
+   # Battery info
+   voltage_max:
+      default: 17800
+   voltage_normal:
+      default: 15480
+   voltage_min:
+      default: 12000
+   precharge_current:
+      default: 80
+   start_charging_min_c:
+      default: 0
+   start_charging_max_c:
+      default: 55
+   charging_min_c:
+      default: 0
+   charging_max_c:
+      default: 55
+   discharging_min_c:
+      default: 0
+   discharging_max_c:
+      default: 70
diff --git a/zephyr/dts/bindings/battery/atl,framework85w.yaml b/zephyr/dts/bindings/battery/atl,framework85w.yaml
new file mode 100644
index 0000000000..a45244d62c
--- /dev/null
+++ b/zephyr/dts/bindings/battery/atl,framework85w.yaml
@@ -0,0 +1,53 @@
+description: "ATL NVT FRANDBAT01"
+compatible: "atl,framework85w"
+
+include: battery-smart.yaml
+
+properties:
+   enum-name:
+      type: string
+      default: "atl,framework85w"
+
+   # Fuel gauge
+   manuf_name:
+      default: "NVT"
+   device_name:
+      default: "FRANDBAT01"
+   ship_mode_reg_addr:
+      default: 0x00
+   ship_mode_reg_data:
+      default: [ 0x0010, 0x0010 ]
+   # Bit 0 - DFET - Condition of D-FET ( 0=OFF, 1=ON )
+   # Bit 1 - CFET - Condition of C-FET ( 0=OFF, 1=ON )
+   fet_mfgacc_support:
+      default: 1
+   fet_reg_mask:
+      default: 0x0002
+   fet_disconnect_val:
+      default: 0x0000
+   fet_cfet_mask:
+      default: 0x0004
+   fet_cfet_off_val:
+      default: 0x0000
+
+   # Battery info
+   voltage_max:
+      default: 17800
+   voltage_normal:
+      default: 15480
+   voltage_min:
+      default: 12000
+   precharge_current:
+      default: 110
+   start_charging_min_c:
+      default: 0
+   start_charging_max_c:
+      default: 55
+   charging_min_c:
+      default: 0
+   charging_max_c:
+      default: 55
+   discharging_min_c:
+      default: 0
+   discharging_max_c:
+      default: 70
diff --git a/zephyr/dts/bindings/battery/atl,gb-s20-4473a9.yaml b/zephyr/dts/bindings/battery/atl,gb-s20-4473a9.yaml
new file mode 100644
index 0000000000..f65c5c6619
--- /dev/null
+++ b/zephyr/dts/bindings/battery/atl,gb-s20-4473a9.yaml
@@ -0,0 +1,53 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "ATL GB-S20-4473A9"
+compatible: "atl,gb-s20-4473a9"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "atl,gb-s20-4473a9"
+
+  # Fuel gauge
+  manuf_name:
+    default: "313-B7-0D-A"
+  device_name:
+    default: "GG02047XL"
+  ship_mode_reg_addr:
+    default: 0x00
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  fet_mfgacc_support:
+    default: 0
+  fet_reg_addr:
+    default: 0x43
+  fet_reg_mask:
+    default: 0x0003
+  fet_disconnect_val:
+    default: 0x0
+
+  # Battery info
+  voltage_max:
+    default: 8800
+  voltage_normal:
+    default: 7700
+  voltage_min:
+    default: 6000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 45
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 45
+  discharging_min_c:
+    default: -10
+  discharging_max_c:
+    default: 60
diff --git a/zephyr/dts/bindings/battery/battery-fuel-gauge.yaml b/zephyr/dts/bindings/battery/battery-fuel-gauge.yaml
new file mode 100644
index 0000000000..423e17b2da
--- /dev/null
+++ b/zephyr/dts/bindings/battery/battery-fuel-gauge.yaml
@@ -0,0 +1,97 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: |
+   Battery fuel gauge parameters
+
+properties:
+  manuf_name:
+    description: |
+      String returned by the smart battery attribute
+      ManufacturerName (0x20), which is used to help
+      uniquely identify the type of battery.
+    type: string
+  device_name:
+    description: |
+      String returned by the smart battery attribute
+      DeviceName (0x21), which is used to help
+      uniquely identify the type of battery.
+    type: string
+  ship_mode_wb_support:
+    description: |
+       Write Block support. If this is true, then i2c write block command
+       will be used instead of a 16-bit write
+       Value must be either 0 or 1.
+    type: int
+  ship_mode_reg_addr:
+    description: |
+       Address of register responsible for enabling ship mode.
+    type: int
+  ship_mode_reg_data:
+    description: |
+       Values written to register to enable ship mode.
+    type: array
+  sleep_mode_support:
+    description: |
+       Defines if battery support fuel gauge sleep command.
+       Value must be either 0 or 1.
+    type: int
+  sleep_mode_reg_addr:
+    description: |
+       Defines address where command will be sent to go into sleep mode.
+    type: int
+  sleep_mode_reg_data:
+    description: |
+       Defines value which will be sent to register to go into sleep mode.
+    type: int
+  fet_mfgacc_support:
+    description: |
+       Defines if battery supports manufacturer access command.
+       If enabled, FET status is read using the ManufacturerBlockAccess (0x44)
+       to read the OperationStatus (0x54) register.
+       The fet_reg_mask and fet_disconnect_val properties must still be
+       defined.
+       Value must be either 0 or 1.
+    type: int
+  fet_mfgacc_smb_block:
+    description: |
+       Battery supports manufacturer access command.
+       If enabled, Write command by the SMB block protocol.
+       FET status is read using the ManufacturerBlockAccess (0x44)
+       to read the OperationStatus (0x54) register.
+       Value must be either 0 or 1.
+    type: int
+  fet_reg_addr:
+    description: |
+       Address of register which reports charging and discharging FETs status.
+       This property is ignored if fet_mfgacc_support is true.
+    type: int
+  fet_reg_mask:
+    description: |
+       Mask which determines which bit in status value contains the
+       discharge FET status.
+    type: int
+  fet_disconnect_val:
+    description: |
+       Value that describes which bits must be set to determine that
+       discharge FET has disconnected the battery.
+    type: int
+  fet_cfet_mask:
+    description: |
+       Mask which determines which bit in status value contains the
+       charge FET status. If this value is 0, this means there's
+       no charge FET.
+    type: int
+  fet_cfet_off_val:
+    description: |
+       Value that describes which bits must be set to determine that
+       charge FET has disconnected the battery.
+    type: int
+  imbalance_mv:
+    description: |
+       This property is used only if
+       CONFIG_PLATFORM_EC_BATTERY_MEASURE_IMBALANCE is enabled.
+       It should be an enum and its value should be a name of function
+       which will be assigned to imbalance_mv pointer.
+    type: string
diff --git a/zephyr/dts/bindings/battery/battery-info.yaml b/zephyr/dts/bindings/battery/battery-info.yaml
new file mode 100644
index 0000000000..01911743e5
--- /dev/null
+++ b/zephyr/dts/bindings/battery/battery-info.yaml
@@ -0,0 +1,69 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description:
+  Information about battery
+  Voltage is in millivolts
+  Current is in milliamperes
+  Temperature is in Celsius degrees
+
+properties:
+  voltage_max:
+    description: |
+       Maximum voltage that can be applied to the battery.
+    type: int
+  voltage_normal:
+    description: |
+       Nominal voltage of the battery.
+    type: int
+  voltage_min:
+    description: |
+       Minimum voltage of the battery.
+       If current voltage is below this value, system will shutdown.
+    type: int
+  precharge_voltage:
+    description: |
+       Voltage used during the precharge phase. Not all chargers
+       may take these into account.
+    type: int
+  precharge_current:
+    description: |
+       Maximum current used during the precharge phase.
+    type: int
+  start_charging_min_c:
+    description: |
+       Minimum temperature of battery to start charging it.
+       This value is used only if
+       CONFIG_PLATFORM_EC_BATTERY_CHECK_CHARGE_TEMP_LIMITS is enabled.
+    type: int
+  start_charging_max_c:
+    description: |
+       Maximum temperature of battery to start charging it.
+       This value is used only if
+       CONFIG_PLATFORM_EC_BATTERY_CHECK_CHARGE_TEMP_LIMITS is enabled.
+    type: int
+  charging_min_c:
+    description: |
+       Minimum temperature of battery during charging it. If the battery
+       temperature falls below this value, charging will be stopped.
+       This value is used only if
+       CONFIG_PLATFORM_EC_BATTERY_CHECK_CHARGE_TEMP_LIMITS is enabled.
+    type: int
+  charging_max_c:
+    description: |
+       Maximum temperature of battery during charging it. If the battery
+       temperature raises above this value, charging will be stopped.
+       This value is used only if
+       CONFIG_PLATFORM_EC_BATTERY_CHECK_CHARGE_TEMP_LIMITS is enabled.
+    type: int
+  discharging_min_c:
+    description: |
+       Minimum working temperature of battery.
+       If temperature is below this value, the system will shutdown.
+    type: int
+  discharging_max_c:
+    description: |
+       Maximum working temperature of battery.
+       If temperature is above this value, the system will shutdown.
+    type: int
diff --git a/zephyr/dts/bindings/battery/battery-smart.yaml b/zephyr/dts/bindings/battery/battery-smart.yaml
new file mode 100644
index 0000000000..0eb5747ffa
--- /dev/null
+++ b/zephyr/dts/bindings/battery/battery-smart.yaml
@@ -0,0 +1,90 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+compatible: "battery-smart"
+
+include: ["base.yaml", "battery-info.yaml", "battery-fuel-gauge.yaml"]
+
+properties:
+  enum-name:
+    description: Unique value used for creating enum of batteries types
+    type: string
+    enum:
+      - "aec,5477109"
+      - "atl,cfd72"
+      - "atl,gb-s20-4473a9"
+      - "bms-gf,cr50"
+      - "byd,yt39x"
+      - "byd,l22b3pg0"
+      - "byd,x0y5m"
+      - "byd,wv3k8"
+      - "cdt,c340152"
+      - "celxpert,b300049"
+      - "celxpert,c235-41"
+      - "celxpert,c340152"
+      - "celxpert,l22c3pg0"
+      - "cosmx,ap20cbl"
+      - "cosmx,ap20cbl-2"
+      - "cosmx,ap20cbl-3"
+      - "cosmx,gg02047xl"
+      - "cosmx,gh02047xl"
+      - "cosmx,si03058xl"
+      - "cosmx,l22x3pg0"
+      - "cosmx,mvk11"
+      - "dynapack,atl_gh02047xl"
+      - "dynapack,byd_gg02047xl"
+      - "dynapack,cosmx_gh02047xl"
+      - "dynapack,c140254"
+      - "dynapack,hpp_gg02047xl"
+      - "ganfeng,7c01"
+      - "ganfeng,sg20"
+      - "pow-tech,sg20qt1c"
+      - "getac,bq40z50-R3-S3"
+      - "getac,bq40z50-R3-S2"
+      - "gfl,mfp-549358"
+      - "lgc,ac17a8m"
+      - "lgc,ap16l8j"
+      - "lgc,ap18c8k"
+      - "lgc,ap19a8k"
+      - "lgc,ap19b8k"
+      - "lgc,ap19b8m"
+      - "lgc,ap19b8m-2"
+      - "lgc,l20l3pg2"
+      - "lgc,8ghcx"
+      - "lgc,xphx8"
+      - "murata,ap18c4k"
+      - "panasonic,ap16l5j"
+      - "panasonic,ap16l5j-009"
+      - "panasonic,ap19a5k"
+      - "panasonic,ap19b5k"
+      - "powertech,batgqa05l22"
+      - "smp,ap18c7k"
+      - "smp,atlrf9h3"
+      - "smp,atl26jgk"
+      - "smp,atlxdy9k"
+      - "smp,c31n1915"
+      - "smp,c31n2005"
+      - "smp,cosrf9h3"
+      - "smp,cos26jgk"
+      - "smp,l20m3pg0"
+      - "smp,l20m3pg1"
+      - "smp,l20m3pg2"
+      - "smp,l21m4pg0"
+      - "smp,l22m3pg0"
+      - "smp,l22m3pg1"
+      - "smp,pc-vp-bp153"
+      - "smp,coslight_gh02047xl"
+      - "smp,cosxdy9k"
+      - "smp,highpower_gh02047xl"
+      - "smp,highpower_si03058xl"
+      - "smp,si03054xl"
+      - "sunwoda,atlvkyjx"
+      - "sunwoda,cosvkyjx"
+      - "sunwoda,cosctgkt"
+      - "sunwoda,l22d3pg0"
+      - "sunwoda,l22d3pg1"
+      - "sunwoda,ctgkt"
+      - "atl,framework55w"
+      - "atl,framework61w"
+      - "atl,framework85w"
diff --git a/zephyr/dts/bindings/battery/bms-gf,cr50.yaml b/zephyr/dts/bindings/battery/bms-gf,cr50.yaml
new file mode 100644
index 0000000000..cd5cc8c05a
--- /dev/null
+++ b/zephyr/dts/bindings/battery/bms-gf,cr50.yaml
@@ -0,0 +1,53 @@
+description: "BMS-GF CR50"
+compatible: "bms-gf,cr50"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "bms-gf,cr50"
+
+  # Fuel gauge
+  manuf_name:
+    default: "BMS-GF"
+  device_name:
+    default: "CR50"
+  ship_mode_reg_addr:
+    default: 0x00
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  fet_mfgacc_support:
+    default: 0
+  fet_reg_addr:
+    default: 0x43
+  fet_reg_mask:
+    default: 0x0001
+  fet_disconnect_val:
+    default: 0x0000
+  fet_cfet_mask:
+    default: 0x0002
+  fet_cfet_off_val:
+    default: 0x0000
+
+  # Battery info
+  voltage_max:
+    default: 17600
+  voltage_normal:
+    default: 15000
+  voltage_min:
+    default: 12000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 50
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -20
+  discharging_max_c:
+    default: 60
diff --git a/zephyr/dts/bindings/battery/byd,l22b3pg0.yaml b/zephyr/dts/bindings/battery/byd,l22b3pg0.yaml
new file mode 100644
index 0000000000..91d37d302a
--- /dev/null
+++ b/zephyr/dts/bindings/battery/byd,l22b3pg0.yaml
@@ -0,0 +1,53 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "BYD L22B3PG0"
+compatible: "byd,l22b3pg0"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "byd,l22b3pg0"
+
+  # Fuel gauge
+  manuf_name:
+    default: "BYD"
+  device_name:
+    default: "L22B3PG0"
+  ship_mode_reg_addr:
+    default: 0x34
+  ship_mode_reg_data:
+    default: [0x0000, 0x1000]
+  fet_mfgacc_support:
+    default: 0
+  fet_reg_addr:
+    default: 0x34
+  fet_reg_mask:
+    default: 0x0100
+  fet_disconnect_val:
+    default: 0x0100
+
+  # Battery info
+  voltage_max:
+    default: 13200
+  voltage_normal:
+    default: 11310
+  voltage_min:
+    default: 9000
+  precharge_current:
+    default: 416
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 50
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -20
+  discharging_max_c:
+    default: 70
diff --git a/zephyr/dts/bindings/battery/byd,wv3k8.yaml b/zephyr/dts/bindings/battery/byd,wv3k8.yaml
new file mode 100644
index 0000000000..f2c25d75ca
--- /dev/null
+++ b/zephyr/dts/bindings/battery/byd,wv3k8.yaml
@@ -0,0 +1,55 @@
+description: "BYD DELL WV3K8"
+compatible: "byd,wv3k8"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "byd,wv3k8"
+
+  # Fuel gauge
+  manuf_name:
+    default: "BYD"
+  device_name:
+    default: "DELL WV3K8"
+  ship_mode_reg_addr:
+    default: 0x00
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  fet_mfgacc_support:
+    default: 1
+  fet_mfgacc_smb_block:
+    default: 1
+  fet_reg_addr:
+    default: 0x54
+  fet_reg_mask:
+    default: 0x0002
+  fet_disconnect_val:
+    default: 0x0000
+  fet_cfet_mask:
+    default: 0x0004
+  fet_cfet_off_val:
+    default: 0x0000
+
+  # Battery info
+  voltage_max:
+    default: 17400
+  voltage_normal:
+    default: 15000
+  voltage_min:
+    default: 12000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: -3
+  start_charging_max_c:
+    default: 45
+  charging_min_c:
+    default: -3
+  charging_max_c:
+    default: 50
+  discharging_min_c:
+    default: -5
+  discharging_max_c:
+    default: 70
diff --git a/zephyr/dts/bindings/battery/byd,x0y5m.yaml b/zephyr/dts/bindings/battery/byd,x0y5m.yaml
new file mode 100644
index 0000000000..c32f358d61
--- /dev/null
+++ b/zephyr/dts/bindings/battery/byd,x0y5m.yaml
@@ -0,0 +1,53 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "BYD X0Y5M"
+compatible: "byd,x0y5m"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "byd,x0y5m"
+
+  # Fuel gauge
+  manuf_name:
+    default: "BYD"
+  device_name:
+    default: "DELL X0Y5M"
+  ship_mode_reg_addr:
+    default: 0x00
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  fet_mfgacc_support:
+    default: 0
+  fet_reg_addr:
+    default: 0x0043
+  fet_reg_mask:
+    default: 0x0003
+  fet_disconnect_val:
+    default: 0x0000
+
+  # Battery info
+  voltage_max:
+    default: 13200
+  voltage_normal:
+    default: 11400
+  voltage_min:
+    default: 9000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: -3
+  start_charging_max_c:
+    default: 50
+  charging_min_c:
+    default: -3
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -5
+  discharging_max_c:
+    default: 70
diff --git a/zephyr/dts/bindings/battery/byd,yt39x.yaml b/zephyr/dts/bindings/battery/byd,yt39x.yaml
new file mode 100644
index 0000000000..e9e38e62ee
--- /dev/null
+++ b/zephyr/dts/bindings/battery/byd,yt39x.yaml
@@ -0,0 +1,57 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "BYD YT39X"
+compatible: "byd,yt39x"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "byd,yt39x"
+
+  # Fuel gauge
+  manuf_name:
+    default: "BYD"
+  device_name:
+    default: "DELL YT39X"
+  ship_mode_wb_support:
+    default: 1
+  ship_mode_reg_addr:
+    default: 0x44
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  fet_mfgacc_support:
+    default: 1
+  fet_mfgacc_smb_block:
+    default: 1
+  fet_reg_addr:
+    default: 0x0054
+  fet_reg_mask:
+    default: 0x0006
+  fet_disconnect_val:
+    default: 0x0000
+
+  # Battery info
+  voltage_max:
+    default: 13200
+  voltage_normal:
+    default: 11400
+  voltage_min:
+    default: 9000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: -3
+  start_charging_max_c:
+    default: 50
+  charging_min_c:
+    default: -3
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -5
+  discharging_max_c:
+    default: 70
diff --git a/zephyr/dts/bindings/battery/cdt,c340152.yaml b/zephyr/dts/bindings/battery/cdt,c340152.yaml
new file mode 100644
index 0000000000..3ec9d9f38f
--- /dev/null
+++ b/zephyr/dts/bindings/battery/cdt,c340152.yaml
@@ -0,0 +1,58 @@
+# CDT CosMX 5260mAh
+description: "CDT CosMX 5260mAh AS3FXXD3KB C340152"
+compatible: "cdt,c340152"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "cdt,c340152"
+
+  # Fuel Gauge
+  manuf_name:
+    default: "AS3FXXD3KB"
+  device_name:
+    default: "C340152"
+  ship_mode_reg_addr:
+    default: 0x00
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  # Charging/Discharging FETs Status
+  # Register SBS_PackStatus_ACCESS (0x99)
+  # Discharging disabled  Bit-3: XDSG       1 = Active
+  # Charging disabled     Bit-2: XCHG       0 = Inactive
+  fet_mfgacc_support:
+    default: 0
+  fet_reg_addr:
+    default: 0x99
+  fet_reg_mask:
+    default: 0x000C
+  fet_disconnect_val:
+    default: 0x000C
+  fet_cfet_mask:
+    default: 0x0004
+  fet_cfet_off_val:
+    default: 0x0004
+
+  # Battery info
+  voltage_max:
+    default: 13350
+  voltage_normal:
+    default: 11985
+  voltage_min:
+    default: 9000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 45
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -20
+  discharging_max_c:
+    default: 60
diff --git a/zephyr/dts/bindings/battery/celxpert,c235-41.yaml b/zephyr/dts/bindings/battery/celxpert,c235-41.yaml
new file mode 100644
index 0000000000..5b41a3d091
--- /dev/null
+++ b/zephyr/dts/bindings/battery/celxpert,c235-41.yaml
@@ -0,0 +1,56 @@
+description: "Celxpert C235-41"
+compatible: "celxpert,c235-41"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "celxpert,c235-41"
+
+  # Fuel gauge
+  manuf_name:
+    default: "AS3GWRc3KA"
+  device_name:
+    default: "C235-41"
+  ship_mode_reg_addr:
+    default: 0x00
+  ship_mode_reg_data:
+    default: [0x10, 0x10]
+  # Documentation: b/150833879
+  # Charging/Discharging FETs Status
+  # Register SBS_PackStatus_ACCESS (0x99)
+  # Bit-3: XDSG
+  # Bit-2: XCHG
+  fet_reg_addr:
+    default: 0x99
+  fet_reg_mask:
+    default: 0x08
+  fet_disconnect_val:
+    default: 0x08
+  fet_cfet_mask:
+    default: 0x04
+  fet_cfet_off_val:
+    default: 0x04
+
+  # Battery info
+  voltage_max:
+    default: 8800
+  voltage_normal:
+    default: 7700
+  voltage_min:
+    default: 6000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 45
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: 0
+  discharging_max_c:
+    default: 60
diff --git a/zephyr/dts/bindings/battery/celxpert,c340152.yaml b/zephyr/dts/bindings/battery/celxpert,c340152.yaml
new file mode 100644
index 0000000000..19c13d611b
--- /dev/null
+++ b/zephyr/dts/bindings/battery/celxpert,c340152.yaml
@@ -0,0 +1,60 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+description: "CELXPERT AS3FXXD3KB C340152"
+compatible: "celxpert,c340152"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "celxpert,c340152"
+
+  # Fuel Gauge
+  manuf_name:
+    default: "AS3FXXD3KB"
+  device_name:
+    default: "C340152"
+  ship_mode_reg_addr:
+    default: 0x00
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  # Charging/Discharging FETs Status
+  # Register SBS_PackStatus_ACCESS (0x99)
+  # Discharging disabled  Bit-3: XDSG       1 = Active
+  # Charging disabled     Bit-2: XCHG       0 = Inactive
+  fet_mfgacc_support:
+    default: 0
+  fet_reg_addr:
+    default: 0x99
+  fet_reg_mask:
+    default: 0x000C
+  fet_disconnect_val:
+    default: 0x000C
+  fet_cfet_mask:
+    default: 0x0004
+  fet_cfet_off_val:
+    default: 0x0004
+
+  # Battery info
+  voltage_max:
+    default: 13350
+  voltage_normal:
+    default: 11985
+  voltage_min:
+    default: 9000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 45
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -20
+  discharging_max_c:
+    default: 60
diff --git a/zephyr/dts/bindings/battery/celxpert,l22c3pg0.yaml b/zephyr/dts/bindings/battery/celxpert,l22c3pg0.yaml
new file mode 100644
index 0000000000..131971f374
--- /dev/null
+++ b/zephyr/dts/bindings/battery/celxpert,l22c3pg0.yaml
@@ -0,0 +1,53 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "CELXPERT L22C3PG0"
+compatible: "celxpert,l22c3pg0"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "celxpert,l22c3pg0"
+
+  # Fuel gauge
+  manuf_name:
+    default: "Celxpert"
+  device_name:
+    default: "L22C3PG0"
+  ship_mode_reg_addr:
+    default: 0x34
+  ship_mode_reg_data:
+    default: [0x0000, 0x1000]
+  fet_mfgacc_support:
+    default: 0
+  fet_reg_addr:
+    default: 0x00
+  fet_reg_mask:
+    default: 0x0018
+  fet_disconnect_val:
+    default: 0x0000
+
+  # Battery info
+  voltage_max:
+    default: 13200
+  voltage_normal:
+    default: 11310
+  voltage_min:
+    default: 9000
+  precharge_current:
+    default: 416
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 50
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -20
+  discharging_max_c:
+    default: 60
diff --git a/zephyr/dts/bindings/battery/celxpert_b300049.yaml b/zephyr/dts/bindings/battery/celxpert_b300049.yaml
new file mode 100644
index 0000000000..eb16ee69f6
--- /dev/null
+++ b/zephyr/dts/bindings/battery/celxpert_b300049.yaml
@@ -0,0 +1,59 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "Celxpert B300049"
+compatible: "celxpert,b300049"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "celxpert,b300049"
+
+  # Fuel gauge
+  manuf_name:
+    default: "AS3FXXE3KA"
+  device_name:
+    default: "B300049"
+  ship_mode_reg_addr:
+    default: 0x00
+  ship_mode_reg_data:
+    default: [0x10, 0x10]
+  # Charging/Discharging FETs Status
+  # Register SBS_PackStatus_ACCESS (0x99)
+  # Bit-3: XDSG
+  # Bit-2: XCHG
+  fet_reg_addr:
+    default: 0x99
+  fet_reg_mask:
+    default: 0x08
+  fet_disconnect_val:
+    default: 0x08
+  fet_cfet_mask:
+    default: 0x04
+  fet_cfet_off_val:
+    default: 0x04
+
+  # Battery info
+  voltage_max:
+    default: 8800
+  voltage_normal:
+    default: 7920
+  voltage_min:
+    default: 6000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 45
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -20
+  discharging_max_c:
+    default: 60
diff --git a/zephyr/dts/bindings/battery/cosmx,ap20cbl-2.yaml b/zephyr/dts/bindings/battery/cosmx,ap20cbl-2.yaml
new file mode 100644
index 0000000000..4a946b8056
--- /dev/null
+++ b/zephyr/dts/bindings/battery/cosmx,ap20cbl-2.yaml
@@ -0,0 +1,57 @@
+description: "COSMX AP20CBL-2"
+compatible: "cosmx,ap20cbl-2"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "cosmx,ap20cbl-2"
+
+  # Fuel gauge
+  manuf_name:
+    default: "COSMX KT0030B004"
+  device_name:
+    default: "AP20CBL"
+  ship_mode_reg_addr:
+    default: 0x3A
+  ship_mode_reg_data:
+    default: [0xC574, 0xC574]
+  # Documentation: b/257860663#comment7
+  # Manufacturer Access 0x00
+  # b14: Charging Disabled (0: Off, 1: On)
+  # b13: Discharging Disabled (0: Off, 1: On)
+  fet_mfgacc_support:
+    default: 1
+  fet_reg_addr:
+    default: 0x0
+  fet_reg_mask:
+    default: 0x2000
+  fet_disconnect_val:
+    default: 0x2000
+  fet_cfet_mask:
+    default: 0x4000
+  fet_cfet_off_val:
+    default: 0x4000
+
+  # Battery info
+  voltage_max:
+    default: 13200
+  voltage_normal:
+    default: 11550
+  voltage_min:
+    default: 9000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 50
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -20
+  discharging_max_c:
+    default: 75
diff --git a/zephyr/dts/bindings/battery/cosmx,ap20cbl-3.yaml b/zephyr/dts/bindings/battery/cosmx,ap20cbl-3.yaml
new file mode 100644
index 0000000000..412f67ecab
--- /dev/null
+++ b/zephyr/dts/bindings/battery/cosmx,ap20cbl-3.yaml
@@ -0,0 +1,57 @@
+description: "COSMX AP20CBL-3"
+compatible: "cosmx,ap20cbl-3"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "cosmx,ap20cbl-3"
+
+  # Fuel gauge
+  manuf_name:
+    default: "COSMX KT0030B004"
+  device_name:
+    default: "AP20CBL"
+  ship_mode_reg_addr:
+    default: 0x3A
+  ship_mode_reg_data:
+    default: [0xC574, 0xC574]
+  # Documentation: b/263692236#comment2
+  # Manufacturer Access 0x00
+  # b1: D-FET
+  # b2: C-FET
+  fet_mfgacc_support:
+    default: 1
+  fet_reg_addr:
+    default: 0x0
+  fet_reg_mask:
+    default: 0x0002
+  fet_disconnect_val:
+    default: 0x0000
+  fet_cfet_mask:
+    default: 0x0004
+  fet_cfet_off_val:
+    default: 0x0000
+
+  # Battery info
+  voltage_max:
+    default: 13200
+  voltage_normal:
+    default: 11550
+  voltage_min:
+    default: 9000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 50
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -20
+  discharging_max_c:
+    default: 75
diff --git a/zephyr/dts/bindings/battery/cosmx,ap20cbl.yaml b/zephyr/dts/bindings/battery/cosmx,ap20cbl.yaml
new file mode 100644
index 0000000000..7701097251
--- /dev/null
+++ b/zephyr/dts/bindings/battery/cosmx,ap20cbl.yaml
@@ -0,0 +1,57 @@
+description: "COSMX AP20CBL"
+compatible: "cosmx,ap20cbl"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "cosmx,ap20cbl"
+
+  # Fuel gauge
+  manuf_name:
+    default: "COSMX KT0030B002"
+  device_name:
+    default: "AP20CBL"
+  ship_mode_reg_addr:
+    default: 0x3A
+  ship_mode_reg_data:
+    default: [0xC574, 0xC574]
+  # Documentation: b/230427330
+  # Manufacturer Access 0x00
+  # b14: Charging Disabled (0: Off, 1: On)
+  # b13: Discharging Disabled (0: Off, 1: On)
+  fet_mfgacc_support:
+    default: 1
+  fet_reg_addr:
+    default: 0x0
+  fet_reg_mask:
+    default: 0x2000
+  fet_disconnect_val:
+    default: 0x2000
+  fet_cfet_mask:
+    default: 0x4000
+  fet_cfet_off_val:
+    default: 0x4000
+
+  # Battery info
+  voltage_max:
+    default: 13200
+  voltage_normal:
+    default: 11550
+  voltage_min:
+    default: 9000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 50
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -20
+  discharging_max_c:
+    default: 75
diff --git a/zephyr/dts/bindings/battery/cosmx,gg02047xl.yaml b/zephyr/dts/bindings/battery/cosmx,gg02047xl.yaml
new file mode 100644
index 0000000000..9ad7773ddd
--- /dev/null
+++ b/zephyr/dts/bindings/battery/cosmx,gg02047xl.yaml
@@ -0,0 +1,53 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "COSMX GG02047XL"
+compatible: "cosmx,gg02047xl"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "cosmx,gg02047xl"
+
+  # Fuel gauge
+  manuf_name:
+    default: "333-AC-0D-A"
+  device_name:
+    default: "GG02047XL"
+  ship_mode_reg_addr:
+    default: 0x00
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  fet_mfgacc_support:
+    default: 1
+  fet_reg_addr:
+    default: 0x0
+  fet_reg_mask:
+    default: 0x0006
+  fet_disconnect_val:
+    default: 0x0
+
+  # Battery info
+  voltage_max:
+    default: 8800
+  voltage_normal:
+    default: 7700
+  voltage_min:
+    default: 6000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 45
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 45
+  discharging_min_c:
+    default: -10
+  discharging_max_c:
+    default: 60
diff --git a/zephyr/dts/bindings/battery/cosmx,gh02047xl.yaml b/zephyr/dts/bindings/battery/cosmx,gh02047xl.yaml
new file mode 100644
index 0000000000..b3606308ac
--- /dev/null
+++ b/zephyr/dts/bindings/battery/cosmx,gh02047xl.yaml
@@ -0,0 +1,53 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "COSMX GH02047XL"
+compatible: "cosmx,gh02047xl"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "cosmx,gh02047xl"
+
+  # Fuel gauge
+  manuf_name:
+    default: "333-AC-DA-A"
+  device_name:
+    default: "GH02047XL"
+  ship_mode_reg_addr:
+    default: 0x00
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  fet_mfgacc_support:
+    default: 1
+  fet_reg_addr:
+    default: 0x0
+  fet_reg_mask:
+    default: 0x0006
+  fet_disconnect_val:
+    default: 0x0
+
+  # Battery info
+  voltage_max:
+    default: 8800
+  voltage_normal:
+    default: 7700
+  voltage_min:
+    default: 6000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 45
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 45
+  discharging_min_c:
+    default: -10
+  discharging_max_c:
+    default: 60
diff --git a/zephyr/dts/bindings/battery/cosmx,l22x3pg0.yaml b/zephyr/dts/bindings/battery/cosmx,l22x3pg0.yaml
new file mode 100644
index 0000000000..bcceff5364
--- /dev/null
+++ b/zephyr/dts/bindings/battery/cosmx,l22x3pg0.yaml
@@ -0,0 +1,53 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "COSMX L22X3PG0"
+compatible: "cosmx,l22x3pg0"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "cosmx,l22x3pg0"
+
+  # Fuel gauge
+  manuf_name:
+    default: "COSMX"
+  device_name:
+    default: "L22X3PG0"
+  ship_mode_reg_addr:
+    default: 0x34
+  ship_mode_reg_data:
+    default: [0x0000, 0x1000]
+  fet_mfgacc_support:
+    default: 0
+  fet_reg_addr:
+    default: 0x34
+  fet_reg_mask:
+    default: 0x0100
+  fet_disconnect_val:
+    default: 0x0100
+
+  # Battery info
+  voltage_max:
+    default: 13200
+  voltage_normal:
+    default: 11310
+  voltage_min:
+    default: 9000
+  precharge_current:
+    default: 207
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 50
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -20
+  discharging_max_c:
+    default: 70
diff --git a/zephyr/dts/bindings/battery/cosmx,mvk11.yaml b/zephyr/dts/bindings/battery/cosmx,mvk11.yaml
new file mode 100644
index 0000000000..9bb3830019
--- /dev/null
+++ b/zephyr/dts/bindings/battery/cosmx,mvk11.yaml
@@ -0,0 +1,55 @@
+description: "COSMX COM DELL MVK11"
+compatible: "cosmx,mvk11"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "cosmx,mvk11"
+
+  # Fuel Gauge
+  manuf_name:
+    default: "COM"
+  device_name:
+    default: "DELL MVK11"
+  ship_mode_reg_addr:
+    default: 0x00
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  fet_mfgacc_support:
+    default: 1
+  fet_mfgacc_smb_block:
+    default: 1
+  fet_reg_addr:
+    default: 0x54
+  fet_reg_mask:
+    default: 0x0002
+  fet_disconnect_val:
+    default: 0x0000
+  fet_cfet_mask:
+    default: 0x0004
+  fet_cfet_off_val:
+    default: 0x0000
+
+  # Battery info
+  voltage_max:
+    default: 17600
+  voltage_normal:
+    default: 15000
+  voltage_min:
+    default: 12000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 50
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -20
+  discharging_max_c:
+    default: 70
diff --git a/zephyr/dts/bindings/battery/cosmx,si03058xl.yaml b/zephyr/dts/bindings/battery/cosmx,si03058xl.yaml
new file mode 100644
index 0000000000..85a3a68101
--- /dev/null
+++ b/zephyr/dts/bindings/battery/cosmx,si03058xl.yaml
@@ -0,0 +1,53 @@
+# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "COSMX SI03058XL"
+compatible: "cosmx,si03058xl"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "cosmx,si03058xl"
+
+  # Fuel gauge
+  manuf_name:
+    default: "333-AC-11-A"
+  device_name:
+    default: "SI03058XL"
+  ship_mode_reg_addr:
+    default: 0x00
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  fet_mfgacc_support:
+    default: 1
+  fet_reg_addr:
+    default: 0x0
+  fet_reg_mask:
+    default: 0x0006
+  fet_disconnect_val:
+    default: 0x0
+
+  # Battery info
+  voltage_max:
+    default: 13200
+  voltage_normal:
+    default: 11550
+  voltage_min:
+    default: 9000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 45
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 45
+  discharging_min_c:
+    default: -10
+  discharging_max_c:
+    default: 60
diff --git a/zephyr/dts/bindings/battery/dynapack,atl_gh02047xl.yaml b/zephyr/dts/bindings/battery/dynapack,atl_gh02047xl.yaml
new file mode 100644
index 0000000000..a92e4359c2
--- /dev/null
+++ b/zephyr/dts/bindings/battery/dynapack,atl_gh02047xl.yaml
@@ -0,0 +1,53 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "DYNAPACK ATL_GH02047XL"
+compatible: "dynapack,atl_gh02047xl"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "dynapack,atl_gh02047xl"
+
+  # Fuel gauge
+  manuf_name:
+    default: "333-27-DA-A"
+  device_name:
+    default: "GH02047XL"
+  ship_mode_reg_addr:
+    default: 0x00
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  fet_mfgacc_support:
+    default: 1
+  fet_reg_addr:
+    default: 0x0
+  fet_reg_mask:
+    default: 0x0006
+  fet_disconnect_val:
+    default: 0x0
+
+  # Battery info
+  voltage_max:
+    default: 8800
+  voltage_normal:
+    default: 7700
+  voltage_min:
+    default: 6000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 45
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 45
+  discharging_min_c:
+    default: -10
+  discharging_max_c:
+    default: 60
diff --git a/zephyr/dts/bindings/battery/dynapack,byd_gg02047xl.yaml b/zephyr/dts/bindings/battery/dynapack,byd_gg02047xl.yaml
new file mode 100644
index 0000000000..1b16bed39d
--- /dev/null
+++ b/zephyr/dts/bindings/battery/dynapack,byd_gg02047xl.yaml
@@ -0,0 +1,53 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "DYNAPACK BYD_GG02047XL"
+compatible: "dynapack,byd_gg02047xl"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "dynapack,byd_gg02047xl"
+
+  # Fuel gauge
+  manuf_name:
+    default: "333-2E-0D-A"
+  device_name:
+    default: "GG02047XL"
+  ship_mode_reg_addr:
+    default: 0x00
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  fet_mfgacc_support:
+    default: 1
+  fet_reg_addr:
+    default: 0x0
+  fet_reg_mask:
+    default: 0x0006
+  fet_disconnect_val:
+    default: 0x0
+
+  # Battery info
+  voltage_max:
+    default: 8800
+  voltage_normal:
+    default: 7700
+  voltage_min:
+    default: 6000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 45
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 45
+  discharging_min_c:
+    default: -10
+  discharging_max_c:
+    default: 60
diff --git a/zephyr/dts/bindings/battery/dynapack,c140254.yaml b/zephyr/dts/bindings/battery/dynapack,c140254.yaml
new file mode 100644
index 0000000000..0b78702031
--- /dev/null
+++ b/zephyr/dts/bindings/battery/dynapack,c140254.yaml
@@ -0,0 +1,56 @@
+description: "DYNAPACK AS3GXXE3KA C140254"
+compatible: "dynapack,c140254"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "dynapack,c140254"
+
+  # Fuel gauge
+  manuf_name:
+    default: "AS3GXXE3KA"
+  device_name:
+    default: "C140254"
+  ship_mode_reg_addr:
+    default: 0x00
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  # Documentation: b/150833879
+  # Charging/Discharging FETs Status
+  # Register SBS_PackStatus_ACCESS (0x99)
+  # Bit-3: XDSG
+  # Bit-2: XCHG
+  fet_reg_addr:
+    default: 0x99
+  fet_reg_mask:
+    default: 0x0C
+  fet_disconnect_val:
+    default: 0x0C
+  fet_cfet_mask:
+    default: 0x04
+  fet_cfet_off_val:
+    default: 0x04
+
+  # Battery info
+  voltage_max:
+    default: 8900
+  voltage_normal:
+    default: 7970
+  voltage_min:
+    default: 6000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 45
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -20
+  discharging_max_c:
+    default: 60
diff --git a/zephyr/dts/bindings/battery/dynapack,cosmx_gh02047xl.yaml b/zephyr/dts/bindings/battery/dynapack,cosmx_gh02047xl.yaml
new file mode 100644
index 0000000000..d00b6826f0
--- /dev/null
+++ b/zephyr/dts/bindings/battery/dynapack,cosmx_gh02047xl.yaml
@@ -0,0 +1,53 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "DYNAPACK COSMX_GH02047XL"
+compatible: "dynapack,cosmx_gh02047xl"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "dynapack,cosmx_gh02047xl"
+
+  # Fuel gauge
+  manuf_name:
+    default: "333-2C-DA-A"
+  device_name:
+    default: "GH02047XL"
+  ship_mode_reg_addr:
+    default: 0x00
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  fet_mfgacc_support:
+    default: 1
+  fet_reg_addr:
+    default: 0x0
+  fet_reg_mask:
+    default: 0x0006
+  fet_disconnect_val:
+    default: 0x0
+
+  # Battery info
+  voltage_max:
+    default: 8800
+  voltage_normal:
+    default: 7700
+  voltage_min:
+    default: 6000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 45
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 45
+  discharging_min_c:
+    default: -10
+  discharging_max_c:
+    default: 60
diff --git a/zephyr/dts/bindings/battery/dynapack,hpp_gg02047xl.yaml b/zephyr/dts/bindings/battery/dynapack,hpp_gg02047xl.yaml
new file mode 100644
index 0000000000..7d7a690592
--- /dev/null
+++ b/zephyr/dts/bindings/battery/dynapack,hpp_gg02047xl.yaml
@@ -0,0 +1,53 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "DYNAPACK HPP_GG02047XL"
+compatible: "dynapack,hpp_gg02047xl"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "dynapack,hpp_gg02047xl"
+
+  # Fuel gauge
+  manuf_name:
+    default: "333-2D-0D-A"
+  device_name:
+    default: "GG02047XL"
+  ship_mode_reg_addr:
+    default: 0x00
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  fet_mfgacc_support:
+    default: 1
+  fet_reg_addr:
+    default: 0x0
+  fet_reg_mask:
+    default: 0x0006
+  fet_disconnect_val:
+    default: 0x0
+
+  # Battery info
+  voltage_max:
+    default: 8800
+  voltage_normal:
+    default: 7700
+  voltage_min:
+    default: 6000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 45
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 45
+  discharging_min_c:
+    default: -10
+  discharging_max_c:
+    default: 60
diff --git a/zephyr/dts/bindings/battery/ganfeng,7c01.yaml b/zephyr/dts/bindings/battery/ganfeng,7c01.yaml
new file mode 100644
index 0000000000..4ae9527390
--- /dev/null
+++ b/zephyr/dts/bindings/battery/ganfeng,7c01.yaml
@@ -0,0 +1,54 @@
+description: "Ganfeng 7C01"
+compatible: "ganfeng,7c01"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "ganfeng,7c01"
+
+  # Fuel gauge
+  manuf_name:
+    default: "Ganfeng"
+  device_name:
+    default: "7C01"
+  ship_mode_reg_addr:
+    default: 0x00
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  # Documentation: b/226820234
+  fet_mfgacc_support:
+    default: 0
+  fet_reg_addr:
+    default: 0x43
+  fet_reg_mask:
+    default: 0x0001
+  fet_disconnect_val:
+    default: 0x0000
+  fet_cfet_mask:
+    default: 0x0002
+  fet_cfet_off_val:
+    default: 0x0000
+
+  # Battery info
+  voltage_max:
+    default: 8700
+  voltage_normal:
+    default: 7600
+  voltage_min:
+    default: 6000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: -20
+  start_charging_max_c:
+    default: 60
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -20
+  discharging_max_c:
+    default: 60
diff --git a/zephyr/dts/bindings/battery/ganfeng,sg20.yaml b/zephyr/dts/bindings/battery/ganfeng,sg20.yaml
new file mode 100644
index 0000000000..f5f0193f26
--- /dev/null
+++ b/zephyr/dts/bindings/battery/ganfeng,sg20.yaml
@@ -0,0 +1,53 @@
+description: "Ganfeng SG20"
+compatible: "ganfeng,sg20"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "ganfeng,sg20"
+
+  # Fuel gauge
+  manuf_name:
+    default: "Ganfeng"
+  device_name:
+    default: "SG20"
+  ship_mode_reg_addr:
+    default: 0x00
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  fet_mfgacc_support:
+    default: 0
+  fet_reg_addr:
+    default: 0x43
+  fet_reg_mask:
+    default: 0x0001
+  fet_disconnect_val:
+    default: 0x0000
+  fet_cfet_mask:
+    default: 0x0002
+  fet_cfet_off_val:
+    default: 0x0000
+
+  # Battery info
+  voltage_max:
+    default: 8700
+  voltage_normal:
+    default: 7600
+  voltage_min:
+    default: 6000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 50
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -20
+  discharging_max_c:
+    default: 60
diff --git a/zephyr/dts/bindings/battery/getac,bq40z50-R3-S2.yaml b/zephyr/dts/bindings/battery/getac,bq40z50-R3-S2.yaml
new file mode 100644
index 0000000000..3406116ae1
--- /dev/null
+++ b/zephyr/dts/bindings/battery/getac,bq40z50-R3-S2.yaml
@@ -0,0 +1,53 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "Getac BQ40Z50-R3 2 Cell battery"
+compatible: "getac,bq40z50-R3-S2"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "getac,bq40z50-R3-S2"
+
+  # Fuel gauge
+  manuf_name:
+    default: "Getac"
+  device_name:
+    default: "BQ40Z50-R3"
+  ship_mode_reg_addr:
+    default: 0x00
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  fet_mfgacc_support:
+    default: 0
+  fet_reg_addr:
+    default: 0x00
+  fet_reg_mask:
+    default: 0x6000
+  fet_disconnect_val:
+    default: 0x6000
+
+  # Battery info
+  voltage_max:
+    default: 8800
+  voltage_normal:
+    default: 7700
+  voltage_min:
+    default: 6000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 45
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 45
+  discharging_min_c:
+    default: 0
+  discharging_max_c:
+    default: 60
diff --git a/zephyr/dts/bindings/battery/getac,bq40z50-R3-S3.yaml b/zephyr/dts/bindings/battery/getac,bq40z50-R3-S3.yaml
new file mode 100644
index 0000000000..77b24ee366
--- /dev/null
+++ b/zephyr/dts/bindings/battery/getac,bq40z50-R3-S3.yaml
@@ -0,0 +1,53 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "Getac BQ40Z50-R3 3 Cell battery"
+compatible: "getac,bq40z50-R3-S3"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "getac,bq40z50-R3-S3"
+
+  # Fuel gauge
+  manuf_name:
+    default: "Getac"
+  device_name:
+    default: "BQ40Z50-R3"
+  ship_mode_reg_addr:
+    default: 0x00
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  fet_mfgacc_support:
+    default: 0
+  fet_reg_addr:
+    default: 0x00
+  fet_reg_mask:
+    default: 0x6000
+  fet_disconnect_val:
+    default: 0x6000
+
+  # Battery info
+  voltage_max:
+    default: 13050
+  voltage_normal:
+    default: 11400
+  voltage_min:
+    default: 9000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 45
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 45
+  discharging_min_c:
+    default: 0
+  discharging_max_c:
+    default: 60
diff --git a/zephyr/dts/bindings/battery/gfl,mfp-549358.yaml b/zephyr/dts/bindings/battery/gfl,mfp-549358.yaml
new file mode 100644
index 0000000000..1cf4181b58
--- /dev/null
+++ b/zephyr/dts/bindings/battery/gfl,mfp-549358.yaml
@@ -0,0 +1,53 @@
+description: "Gfl MFP-549358"
+compatible: "gfl,mfp-549358"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "gfl,mfp-549358"
+
+  # Fuel gauge
+  manuf_name:
+    default: "GFL"
+  device_name:
+    default: "MFP-549358"
+  ship_mode_reg_addr:
+    default: 0x00
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  fet_mfgacc_support:
+    default: 1
+  fet_reg_addr:
+    default: 0x54
+  fet_reg_mask:
+    default: 0x0006
+  fet_disconnect_val:
+    default: 0x0000
+  fet_cfet_mask:
+    default: 0x4000
+  fet_cfet_off_val:
+    default: 0x4000
+
+  # Battery info
+  voltage_max:
+    default: 13200
+  voltage_normal:
+    default: 11550
+  voltage_min:
+    default: 9000
+  precharge_current:
+    default: 100
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 50
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -20
+  discharging_max_c:
+    default: 60
diff --git a/zephyr/dts/bindings/battery/lgc,8ghcx.yaml b/zephyr/dts/bindings/battery/lgc,8ghcx.yaml
new file mode 100644
index 0000000000..d564b00637
--- /dev/null
+++ b/zephyr/dts/bindings/battery/lgc,8ghcx.yaml
@@ -0,0 +1,60 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "LGC-LGC3.685 DELL 8GHCX"
+compatible: "lgc,8ghcx"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "lgc,8ghcx"
+
+  manuf_name:
+    default: "LGC-LGC3.65"
+  device_name:
+    default: "DELL 8GHCX"
+  ship_mode_wb_support:
+    default: 1
+  ship_mode_reg_addr:
+    default: 0x44
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  fet_mfgacc_support:
+    default: 1
+  fet_mfgacc_smb_block:
+    default: 1
+  fet_reg_addr:
+    default: 0x0054
+  fet_reg_mask:
+    default: 0x0006
+  fet_disconnect_val:
+    default: 0x0000
+  fet_cfet_mask:
+    default: 0x0004
+  fet_cfet_off_val:
+    default: 0x0000
+
+  # Battery info
+  voltage_max:
+    default: 13200
+  voltage_normal:
+    default: 11460
+  voltage_min:
+    default: 9000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: -3
+  start_charging_max_c:
+    default: 50
+  charging_min_c:
+    default: -3
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -5
+  discharging_max_c:
+    default: 70
diff --git a/zephyr/dts/bindings/battery/lgc,ac17a8m.yaml b/zephyr/dts/bindings/battery/lgc,ac17a8m.yaml
new file mode 100644
index 0000000000..e3b790b93f
--- /dev/null
+++ b/zephyr/dts/bindings/battery/lgc,ac17a8m.yaml
@@ -0,0 +1,59 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "LGC AC17A8M"
+compatible: "lgc,ac17a8m"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "lgc,ac17a8m"
+
+  # TI BQ40Z55 Fuel Gauge
+  manuf_name:
+    default: "LGC"
+  device_name:
+    default: "AC17A8M"
+  ship_mode_reg_addr:
+    default: 0x00
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  fet_mfgacc_support:
+    default: 0
+  fet_reg_addr:
+    default: 0x00
+  fet_reg_mask:
+    default: 0x2000
+  fet_disconnect_val:
+    default: 0x2000
+  fet_cfet_mask:
+    default: 0x4000
+  fet_cfet_off_val:
+    default: 0x4000
+
+  # Battery info
+  # voltage_max =13200, Calculated value with 5 tenth % error margin
+  # considered is: ((13200 * 1000) / (1000 + 5)) = 13134
+  voltage_max:
+    default: 13134
+  voltage_normal:
+    default: 11550
+  voltage_min:
+    default: 9000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 45
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: 0
+  discharging_max_c:
+    default: 75
diff --git a/zephyr/dts/bindings/battery/lgc,ap16l8j.yaml b/zephyr/dts/bindings/battery/lgc,ap16l8j.yaml
new file mode 100644
index 0000000000..4516c190ae
--- /dev/null
+++ b/zephyr/dts/bindings/battery/lgc,ap16l8j.yaml
@@ -0,0 +1,55 @@
+description: "LGC KT0020G010 AP16L8J"
+compatible: "lgc,ap16l8j"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "lgc,ap16l8j"
+
+  # Fuel gauge
+  manuf_name:
+    default: "LGC KT0020G010"
+  device_name:
+    default: "AP16L8J"
+  ship_mode_reg_addr:
+    default: 0x3A
+  ship_mode_reg_data:
+    default: [0xC574, 0xC574]
+  # Documentation: b/148625782
+  # ManufacturerAccess() 0x0054 OperationStatus
+  # CHG (Bit 2): CHG FET status (1 = Active 0 = Inactive)
+  # DSG (Bit 1): DSG FET status (1 = Active 0 = Inactive)
+  fet_mfgacc_support:
+    default: 1
+  fet_reg_mask:
+    default: 0x0002
+  fet_disconnect_val:
+    default: 0x0000
+  fet_cfet_mask:
+    default: 0x0004
+  fet_cfet_off_val:
+    default: 0x0000
+
+  # Battery info
+  voltage_max:
+    default: 8700
+  voltage_normal:
+    default: 7500
+  voltage_min:
+    default: 6000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 50
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -20
+  discharging_max_c:
+    default: 75
diff --git a/zephyr/dts/bindings/battery/lgc,ap18c8k.yaml b/zephyr/dts/bindings/battery/lgc,ap18c8k.yaml
new file mode 100644
index 0000000000..1171be4d3c
--- /dev/null
+++ b/zephyr/dts/bindings/battery/lgc,ap18c8k.yaml
@@ -0,0 +1,57 @@
+description: "LGC KT0030G020 AP18C8K"
+compatible: "lgc,ap18c8k"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "lgc,ap18c8k"
+
+  # Fuel gauge
+  manuf_name:
+    default: "LGC KT0030G020"
+  device_name:
+    default: "AP18C8K"
+  ship_mode_reg_addr:
+    default: 0x3A
+  ship_mode_reg_data:
+    default: [0xC574, 0xC574]
+  # Documentation: b/130608940
+  # Command Code: 0x43
+  # Bit 0 - DFET - Condition of D-FET ( 0=OFF, 1=ON )
+  # Bit 1 - CFET - Condition of C-FET ( 0=OFF, 1=ON )
+  fet_mfgacc_support:
+    default: 0
+  fet_reg_addr:
+    default: 0x43
+  fet_reg_mask:
+    default: 0x0001
+  fet_disconnect_val:
+    default: 0x0000
+  fet_cfet_mask:
+    default: 0x0002
+  fet_cfet_off_val:
+    default: 0x0000
+
+  # Battery info
+  voltage_max:
+    default: 13050
+  voltage_normal:
+    default: 11250
+  voltage_min:
+    default: 9000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 50
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -20
+  discharging_max_c:
+    default: 75
diff --git a/zephyr/dts/bindings/battery/lgc,ap19a8k.yaml b/zephyr/dts/bindings/battery/lgc,ap19a8k.yaml
new file mode 100644
index 0000000000..137af0e9a2
--- /dev/null
+++ b/zephyr/dts/bindings/battery/lgc,ap19a8k.yaml
@@ -0,0 +1,54 @@
+description: "LGC KT0030G023 AP19A8K"
+compatible: "lgc,ap19a8k"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "lgc,ap19a8k"
+
+  # Fuel gauge
+  manuf_name:
+    default: "LGC KT0030G023"
+  device_name:
+    default: "AP19A8K"
+  ship_mode_reg_addr:
+    default: 0x3A
+  ship_mode_reg_data:
+    default: [0xC574, 0xC574]
+  # Documentation: b/135496272
+  fet_mfgacc_support:
+    default: 0
+  fet_reg_addr:
+    default: 0x43
+  fet_reg_mask:
+    default: 0x0001
+  fet_disconnect_val:
+    default: 0x0000
+  fet_cfet_mask:
+    default: 0x0002
+  fet_cfet_off_val:
+    default: 0x0000
+
+  # Battery info
+  voltage_max:
+    default: 13200
+  voltage_normal:
+    default: 11550
+  voltage_min:
+    default: 9000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 50
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -20
+  discharging_max_c:
+    default: 75
diff --git a/zephyr/dts/bindings/battery/lgc,ap19b8k.yaml b/zephyr/dts/bindings/battery/lgc,ap19b8k.yaml
new file mode 100644
index 0000000000..70e59e9969
--- /dev/null
+++ b/zephyr/dts/bindings/battery/lgc,ap19b8k.yaml
@@ -0,0 +1,58 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "LGC KT0030G022 AP19B8K"
+compatible: "lgc,ap19b8k"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "lgc,ap19b8k"
+
+  # Fuel gauge
+  manuf_name:
+    default: "LGC KT0030G022"
+  device_name:
+    default: "AP19B8K"
+  ship_mode_reg_addr:
+    default: 0x3A
+  ship_mode_reg_data:
+    default: [0xC574, 0xC574]
+  # Documentation: b/259913834
+  fet_mfgacc_support:
+    default: 0
+  fet_reg_addr:
+    default: 0x43
+  fet_reg_mask:
+    default: 0x0001
+  fet_disconnect_val:
+    default: 0x0000
+  fet_cfet_mask:
+    default: 0x0002
+  fet_cfet_off_val:
+    default: 0x0000
+
+  # Battery info
+  voltage_max:
+    default: 13050
+  voltage_normal:
+    default: 11250
+  voltage_min:
+    default: 9000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 50
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -20
+  discharging_max_c:
+    default: 75
diff --git a/zephyr/dts/bindings/battery/lgc,ap19b8m-2.yaml b/zephyr/dts/bindings/battery/lgc,ap19b8m-2.yaml
new file mode 100644
index 0000000000..63c67b102f
--- /dev/null
+++ b/zephyr/dts/bindings/battery/lgc,ap19b8m-2.yaml
@@ -0,0 +1,57 @@
+description: "LGC KT0030G024 AP19B8M-2"
+compatible: "lgc,ap19b8m-2"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "lgc,ap19b8m-2"
+
+  # Fuel gauge
+  manuf_name:
+    default: "LGC KT0030G024"
+  device_name:
+    default: "AP19B8M"
+  ship_mode_reg_addr:
+    default: 0x00
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  # Documentation: b/263692236#comment2
+  # Manufacturer Access 0x00
+  # b1: D-FET
+  # b2: C-FET
+  fet_mfgacc_support:
+    default: 0
+  fet_reg_addr:
+    default: 0x43
+  fet_reg_mask:
+    default: 0x0001
+  fet_disconnect_val:
+    default: 0x0000
+  fet_cfet_mask:
+    default: 0x0002
+  fet_cfet_off_val:
+    default: 0x0000
+
+  # Battery info
+  voltage_max:
+    default: 13350
+  voltage_normal:
+    default: 11610
+  voltage_min:
+    default: 9000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 50
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -20
+  discharging_max_c:
+    default: 75
diff --git a/zephyr/dts/bindings/battery/lgc,ap19b8m.yaml b/zephyr/dts/bindings/battery/lgc,ap19b8m.yaml
new file mode 100644
index 0000000000..c993014aae
--- /dev/null
+++ b/zephyr/dts/bindings/battery/lgc,ap19b8m.yaml
@@ -0,0 +1,54 @@
+description: "LGC KT0030G024 AP19B8M"
+compatible: "lgc,ap19b8m"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "lgc,ap19b8m"
+
+  # Fuel gauge
+  manuf_name:
+    default: "LGC KT0030G024"
+  device_name:
+    default: "AP19B8M"
+  ship_mode_reg_addr:
+    default: 0x3A
+  ship_mode_reg_data:
+    default: [0xC574, 0xC574]
+  # Documentation: b/135496272
+  fet_mfgacc_support:
+    default: 0
+  fet_reg_addr:
+    default: 0x43
+  fet_reg_mask:
+    default: 0x0001
+  fet_disconnect_val:
+    default: 0x0000
+  fet_cfet_mask:
+    default: 0x0002
+  fet_cfet_off_val:
+    default: 0x0000
+
+  # Battery info
+  voltage_max:
+    default: 13350
+  voltage_normal:
+    default: 11610
+  voltage_min:
+    default: 9000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 50
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -20
+  discharging_max_c:
+    default: 75
diff --git a/zephyr/dts/bindings/battery/lgc,l20l3pg2.yaml b/zephyr/dts/bindings/battery/lgc,l20l3pg2.yaml
new file mode 100644
index 0000000000..f2186425ad
--- /dev/null
+++ b/zephyr/dts/bindings/battery/lgc,l20l3pg2.yaml
@@ -0,0 +1,53 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "LGC L20L3PG2"
+compatible: "lgc,l20l3pg2"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "lgc,l20l3pg2"
+
+  # Fuel gauge
+  manuf_name:
+    default: "LGC"
+  device_name:
+    default: "L20L3PG2"
+  ship_mode_reg_addr:
+    default: 0x34
+  ship_mode_reg_data:
+    default: [0x0000, 0x1000]
+  fet_mfgacc_support:
+    default: 0
+  fet_reg_addr:
+    default: 0x34
+  fet_reg_mask:
+    default: 0x0100
+  fet_disconnect_val:
+    default: 0x0100
+
+  # Battery info
+  voltage_max:
+    default: 13050
+  voltage_normal:
+    default: 11400
+  voltage_min:
+    default: 9000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 50
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -20
+  discharging_max_c:
+    default: 73
diff --git a/zephyr/dts/bindings/battery/lgc,xphx8.yaml b/zephyr/dts/bindings/battery/lgc,xphx8.yaml
new file mode 100644
index 0000000000..fd011ff837
--- /dev/null
+++ b/zephyr/dts/bindings/battery/lgc,xphx8.yaml
@@ -0,0 +1,57 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "LGC-LGC3.600 DELL_XPHX8"
+compatible: "lgc,xphx8"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "lgc,xphx8"
+
+  # Fuel Gauge
+  manuf_name:
+    default: "LGC-LGC3.600"
+  device_name:
+    default: "DELL XPHX8"
+  ship_mode_reg_addr:
+    default: 0x00
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  fet_mfgacc_support:
+    default: 0
+  fet_reg_addr:
+    default: 0x43
+  fet_reg_mask:
+    default: 0x0001
+  fet_disconnect_val:
+    default: 0x0000
+  fet_cfet_mask:
+    default: 0x0002
+  fet_cfet_off_val:
+    default: 0x0000
+
+  # Battery info
+  voltage_max:
+    default: 17600
+  voltage_normal:
+    default: 15000
+  voltage_min:
+    default: 12000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: -3
+  start_charging_max_c:
+    default: 45
+  charging_min_c:
+    default: -3
+  charging_max_c:
+    default: 50
+  discharging_min_c:
+    default: -20
+  discharging_max_c:
+    default: 70
diff --git a/zephyr/dts/bindings/battery/murata,ap18c4k.yaml b/zephyr/dts/bindings/battery/murata,ap18c4k.yaml
new file mode 100644
index 0000000000..ef3c9fd3f6
--- /dev/null
+++ b/zephyr/dts/bindings/battery/murata,ap18c4k.yaml
@@ -0,0 +1,57 @@
+description: "Murata KT00304012 AP18C4K"
+compatible: "murata,ap18c4k"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "murata,ap18c4k"
+
+  # Fuel gauge
+  manuf_name:
+    default: "Murata KT00304012"
+  device_name:
+    default: "AP18C4K"
+  ship_mode_reg_addr:
+    default: 0x3A
+  ship_mode_reg_data:
+    default: [0xC574, 0xC574]
+  # Documentation: b/130615670
+  # Manufacturer Access 0x00
+  # b14: Charging Disabled (0: Off, 1: On)
+  # b13: Discharging Disabled (0: Off, 1: On)
+  fet_mfgacc_support:
+    default: 0
+  fet_reg_addr:
+    default: 0x0
+  fet_reg_mask:
+    default: 0x2000
+  fet_disconnect_val:
+    default: 0x2000
+  fet_cfet_mask:
+    default: 0x4000
+  fet_cfet_off_val:
+    default: 0x4000
+
+  # Battery info
+  voltage_max:
+    default: 13200
+  voltage_normal:
+    default: 11400
+  voltage_min:
+    default: 9000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 50
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -20
+  discharging_max_c:
+    default: 75
diff --git a/zephyr/dts/bindings/battery/panasonic,ap16l5j-009.yaml b/zephyr/dts/bindings/battery/panasonic,ap16l5j-009.yaml
new file mode 100644
index 0000000000..1da54f2e73
--- /dev/null
+++ b/zephyr/dts/bindings/battery/panasonic,ap16l5j-009.yaml
@@ -0,0 +1,59 @@
+description: "Panasonic KT00205009 AP16L5J"
+compatible: "panasonic,ap16l5j-009"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "panasonic,ap16l5j-009"
+
+  # Fuel gauge
+  manuf_name:
+    default: "PANASONIC KT00205009"
+  device_name:
+    default: "AP16L5J"
+  ship_mode_reg_addr:
+    default: 0x3A
+  ship_mode_reg_data:
+    default: [0xC574, 0xC574]
+  # Documentation: b/144674480
+  # ManufacturerAccess() 0x00
+  # Bit14 Discharge FET status
+  # Set - Discharge FET is ON, Reset - Discharge FET is OFF
+  # Bit15 Charge FET status
+  # Set - Charge FET is ON, Reset - Charge FET is OFF
+  fet_mfgacc_support:
+    default: 0
+  fet_reg_addr:
+    default: 0x0
+  fet_reg_mask:
+    default: 0x4000
+  fet_disconnect_val:
+    default: 0x0000
+  fet_cfet_mask:
+    default: 0x8000
+  fet_cfet_off_val:
+    default: 0x0000
+
+  # Battery info
+  voltage_max:
+    default: 8800
+  voltage_normal:
+    default: 7700
+  voltage_min:
+    default: 6000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 50
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -20
+  discharging_max_c:
+    default: 75
diff --git a/zephyr/dts/bindings/battery/panasonic,ap16l5j.yaml b/zephyr/dts/bindings/battery/panasonic,ap16l5j.yaml
new file mode 100644
index 0000000000..0f79ac9cbe
--- /dev/null
+++ b/zephyr/dts/bindings/battery/panasonic,ap16l5j.yaml
@@ -0,0 +1,59 @@
+description: "Panasonic AP16L5J"
+compatible: "panasonic,ap16l5j"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "panasonic,ap16l5j"
+
+  # Fuel gauge
+  manuf_name:
+    default: "PANASONIC"
+  device_name:
+    default: "AP16L5J"
+  ship_mode_reg_addr:
+    default: 0x3A
+  ship_mode_reg_data:
+    default: [0xC574, 0xC574]
+  # Documentation: b/144674480
+  # ManufacturerAccess() 0x00
+  # Bit14 Discharge FET status
+  # Set - Discharge FET is ON, Reset - Discharge FET is OFF
+  # Bit15 Charge FET status
+  # Set - Charge FET is ON, Reset - Charge FET is OFF
+  fet_mfgacc_support:
+    default: 0
+  fet_reg_addr:
+    default: 0x0
+  fet_reg_mask:
+    default: 0x4000
+  fet_disconnect_val:
+    default: 0x0000
+  fet_cfet_mask:
+    default: 0x8000
+  fet_cfet_off_val:
+    default: 0x0000
+
+  # Battery info
+  voltage_max:
+    default: 8800
+  voltage_normal:
+    default: 7700
+  voltage_min:
+    default: 6000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 50
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -20
+  discharging_max_c:
+    default: 75
diff --git a/zephyr/dts/bindings/battery/panasonic,ap19a5k.yaml b/zephyr/dts/bindings/battery/panasonic,ap19a5k.yaml
new file mode 100644
index 0000000000..d581b92b15
--- /dev/null
+++ b/zephyr/dts/bindings/battery/panasonic,ap19a5k.yaml
@@ -0,0 +1,59 @@
+description: "Panasonic KT00305012 AP19A5K"
+compatible: "panasonic,ap19a5k"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "panasonic,ap19a5k"
+
+  # Fuel gauge
+  manuf_name:
+    default: "PANASONIC KT00305012"
+  device_name:
+    default: "AP19A5K"
+  ship_mode_reg_addr:
+    default: 0x3A
+  ship_mode_reg_data:
+    default: [0xC574, 0xC574]
+  # Documentation: b/224888442
+  # ManufacturerAccess() 0x00
+  # Bit14 Discharge FET status
+  # Set - Discharge FET is ON, Reset - Discharge FET is OFF
+  # Bit15 Charge FET status
+  # Set - Charge FET is ON, Reset - Charge FET is OFF
+  fet_mfgacc_support:
+    default: 0
+  fet_reg_addr:
+    default: 0x0
+  fet_reg_mask:
+    default: 0x4000
+  fet_disconnect_val:
+    default: 0x0000
+  fet_cfet_mask:
+    default: 0x8000
+  fet_cfet_off_val:
+    default: 0x0000
+
+  # Battery info
+  voltage_max:
+    default: 13200
+  voltage_normal:
+    default: 7700
+  voltage_min:
+    default: 6000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 50
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -20
+  discharging_max_c:
+    default: 75
diff --git a/zephyr/dts/bindings/battery/panasonic,ap19b5k.yaml b/zephyr/dts/bindings/battery/panasonic,ap19b5k.yaml
new file mode 100644
index 0000000000..18aa08bbf3
--- /dev/null
+++ b/zephyr/dts/bindings/battery/panasonic,ap19b5k.yaml
@@ -0,0 +1,58 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "Panasonic KT00305011 AP19B5K"
+compatible: "panasonic,ap19b5k"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "panasonic,ap19b5k"
+
+  # Fuel gauge
+  manuf_name:
+    default: "PANASONIC KT00305011"
+  device_name:
+    default: "AP19B5K"
+  ship_mode_reg_addr:
+    default: 0x3A
+  ship_mode_reg_data:
+    default: [0xC574, 0xC574]
+  # Documentation: b/259913834
+  fet_mfgacc_support:
+    default: 0
+  fet_reg_addr:
+    default: 0x0
+  fet_reg_mask:
+    default: 0x4000
+  fet_disconnect_val:
+    default: 0x0000
+  fet_cfet_mask:
+    default: 0x8000
+  fet_cfet_off_val:
+    default: 0x0000
+
+  # Battery info
+  voltage_max:
+    default: 13200
+  voltage_normal:
+    default: 11550
+  voltage_min:
+    default: 9000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 50
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -20
+  discharging_max_c:
+    default: 75
diff --git a/zephyr/dts/bindings/battery/pow-tech,sg20qt1c.yaml b/zephyr/dts/bindings/battery/pow-tech,sg20qt1c.yaml
new file mode 100644
index 0000000000..7df7bcc274
--- /dev/null
+++ b/zephyr/dts/bindings/battery/pow-tech,sg20qt1c.yaml
@@ -0,0 +1,57 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "POW-TECH SG20QT1C"
+compatible: "pow-tech,sg20qt1c"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "pow-tech,sg20qt1c"
+
+  # TI BQ40Z50 Fuel Gauge
+  manuf_name:
+    default: "POW-TECH"
+  device_name:
+    default: "SG20QT1C"
+  ship_mode_reg_addr:
+    default: 0x00
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  fet_mfgacc_support:
+    default: 1
+  fet_reg_addr:
+    default: 0x54
+  fet_reg_mask:
+    default: 0x0006
+  fet_disconnect_val:
+    default: 0x0000
+  fet_cfet_mask:
+    default: 0x4000
+  fet_cfet_off_val:
+    default: 0x4000
+
+  # Battery info
+  voltage_max:
+    default: 8700
+  voltage_normal:
+    default: 7600
+  voltage_min:
+    default: 6000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 45
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 53
+  discharging_min_c:
+    default: -23
+  discharging_max_c:
+    default: 63
diff --git a/zephyr/dts/bindings/battery/powertech,batgqa05l22.yaml b/zephyr/dts/bindings/battery/powertech,batgqa05l22.yaml
new file mode 100644
index 0000000000..ff2213e5d5
--- /dev/null
+++ b/zephyr/dts/bindings/battery/powertech,batgqa05l22.yaml
@@ -0,0 +1,59 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "POWERTECH BATGQA05L22"
+compatible: "powertech,batgqa05l22"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "powertech,batgqa05l22"
+
+  # TI BQ40Z50 Fuel Gauge
+  manuf_name:
+    default: "POW-TECH"
+  device_name:
+    default: "BATGQA05L22"
+  ship_mode_reg_addr:
+    default: 0x00
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  fet_mfgacc_support:
+    default: 1
+  fet_reg_addr:
+    default: 0x00
+  fet_reg_mask:
+    default: 0x2000
+  fet_disconnect_val:
+    default: 0x2000
+  fet_cfet_mask:
+    default: 0x4000
+  fet_cfet_off_val:
+    default: 0x4000
+
+  # Battery info
+  # voltage_max = 13050, Calculated value with 5 tenth % error margin
+  # considered is: ((13050 * 1000) / (1000 + 5)) = 12985
+  voltage_max:
+    default: 12985
+  voltage_normal:
+    default: 11400
+  voltage_min:
+    default: 9000
+  precharge_current:
+    default: 280
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 45
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 45
+  discharging_min_c:
+    default: -10
+  discharging_max_c:
+    default: 60
diff --git a/zephyr/dts/bindings/battery/smp,ap18c7k.yaml b/zephyr/dts/bindings/battery/smp,ap18c7k.yaml
new file mode 100644
index 0000000000..2d4e2f48a5
--- /dev/null
+++ b/zephyr/dts/bindings/battery/smp,ap18c7k.yaml
@@ -0,0 +1,58 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "SMP KT00307011 AP18C7K"
+compatible: "smp,ap18c7k"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "smp,ap18c7k"
+
+  # Fuel gauge
+  manuf_name:
+    default: "SMP KT00307011"
+  device_name:
+    default: "AP18C7K"
+  ship_mode_reg_addr:
+    default: 0x3A
+  ship_mode_reg_data:
+    default: [0xC574, 0xC574]
+  # Documentation: b/259913834
+  fet_mfgacc_support:
+    default: 0
+  fet_reg_addr:
+    default: 0x0
+  fet_reg_mask:
+    default: 0x8000
+  fet_disconnect_val:
+    default: 0x0000
+  fet_cfet_mask:
+    default: 0x4000
+  fet_cfet_off_val:
+    default: 0x0000
+
+  # Battery info
+  voltage_max:
+    default: 13200
+  voltage_normal:
+    default: 11550
+  voltage_min:
+    default: 9000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 45
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -20
+  discharging_max_c:
+    default: 75
diff --git a/zephyr/dts/bindings/battery/smp,atl26jgk.yaml b/zephyr/dts/bindings/battery/smp,atl26jgk.yaml
new file mode 100644
index 0000000000..9f7f299a6b
--- /dev/null
+++ b/zephyr/dts/bindings/battery/smp,atl26jgk.yaml
@@ -0,0 +1,61 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "SMP-ATL3.61 DELL 26JGK"
+compatible: "smp,atl26jgk"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "smp,atl26jgk"
+
+  # Fuel gauge
+  manuf_name:
+    default: "SMP-ATL-3.61"
+  device_name:
+    default: "DELL 26JGK"
+  ship_mode_wb_support:
+    default: 1
+  ship_mode_reg_addr:
+    default: 0x44
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  fet_mfgacc_support:
+    default: 1
+  fet_mfgacc_smb_block:
+    default: 1
+  fet_reg_addr:
+    default: 0x0054
+  fet_reg_mask:
+    default: 0x0006
+  fet_disconnect_val:
+    default: 0x0000
+  fet_cfet_mask:
+    default: 0x0004
+  fet_cfet_off_val:
+    default: 0x0000
+
+  # Battery info
+  voltage_max:
+    default: 13200
+  voltage_normal:
+    default: 11400
+  voltage_min:
+    default: 9000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: -3
+  start_charging_max_c:
+    default: 50
+  charging_min_c:
+    default: -3
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -5
+  discharging_max_c:
+    default: 70
diff --git a/zephyr/dts/bindings/battery/smp,atlrf9h3.yaml b/zephyr/dts/bindings/battery/smp,atlrf9h3.yaml
new file mode 100644
index 0000000000..9c0ebeeb6a
--- /dev/null
+++ b/zephyr/dts/bindings/battery/smp,atlrf9h3.yaml
@@ -0,0 +1,55 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "SMP-ATL3.61 DELL RF9H3"
+compatible: "smp,atlrf9h3"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "smp,atlrf9h3"
+
+  # Fuel gauge
+  manuf_name:
+    default: "SMP-ATL-3.61"
+  device_name:
+    default: "DELL RF9H3"
+  ship_mode_reg_addr:
+    default: 0x00
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  fet_reg_addr:
+    default: 0x43
+  fet_reg_mask:
+    default: 0x0003
+  fet_disconnect_val:
+    default: 0x0000
+  fet_cfet_mask:
+    default: 0x0002
+  fet_cfet_off_val:
+    default: 0x0000
+
+  # Battery info
+  voltage_max:
+    default: 13200
+  voltage_normal:
+    default: 11400
+  voltage_min:
+    default: 9000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: -3
+  start_charging_max_c:
+    default: 50
+  charging_min_c:
+    default: -3
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -5
+  discharging_max_c:
+    default: 70
diff --git a/zephyr/dts/bindings/battery/smp,atlxdy9k.yaml b/zephyr/dts/bindings/battery/smp,atlxdy9k.yaml
new file mode 100644
index 0000000000..11addac14c
--- /dev/null
+++ b/zephyr/dts/bindings/battery/smp,atlxdy9k.yaml
@@ -0,0 +1,53 @@
+description: "SMP-ATL SMP-ATL3.66 "
+compatible: "smp,atlxdy9k"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "smp,atlxdy9k"
+
+  # Fuel gauge
+  manuf_name:
+    default: "SMP-ATL3.66"
+  device_name:
+    default: "DELL XDY9K"
+  ship_mode_reg_addr:
+    default: 0x00
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  fet_mfgacc_support:
+    default: 0
+  fet_reg_addr:
+    default: 0x43
+  fet_reg_mask:
+    default: 0x0001
+  fet_disconnect_val:
+    default: 0x0000
+  fet_cfet_mask:
+    default: 0x0002
+  fet_cfet_off_val:
+    default: 0x0000
+
+  # Battery info
+  voltage_max:
+    default: 17600
+  voltage_normal:
+    default: 15000
+  voltage_min:
+    default: 12000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: -3
+  start_charging_max_c:
+    default: 45
+  charging_min_c:
+    default: -3
+  charging_max_c:
+    default: 50
+  discharging_min_c:
+    default: -17
+  discharging_max_c:
+    default: 70
diff --git a/zephyr/dts/bindings/battery/smp,c31n1915.yaml b/zephyr/dts/bindings/battery/smp,c31n1915.yaml
new file mode 100644
index 0000000000..c4b1f68b51
--- /dev/null
+++ b/zephyr/dts/bindings/battery/smp,c31n1915.yaml
@@ -0,0 +1,47 @@
+description: "SMP Rechargeable Li-Polymer Battery Pack 3640mAh"
+compatible: "smp,c31n1915"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "smp,c31n1915"
+
+  # Fuel gauge
+  manuf_name:
+    default: "AS3GWND3jB"
+  device_name:
+    default: "B340035"
+  ship_mode_reg_addr:
+    default: 0x00
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  fet_reg_addr:
+    default: 0x99
+  fet_reg_mask:
+    default: 0x000c
+  fet_disconnect_val:
+    default: 0x000c
+
+  # Battery info
+  voltage_max:
+    default: 13200
+  voltage_normal:
+    default: 11850
+  voltage_min:
+    default: 9000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 45
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -20
+  discharging_max_c:
+    default: 60
diff --git a/zephyr/dts/bindings/battery/smp,c31n2005.yaml b/zephyr/dts/bindings/battery/smp,c31n2005.yaml
new file mode 100644
index 0000000000..51888cc875
--- /dev/null
+++ b/zephyr/dts/bindings/battery/smp,c31n2005.yaml
@@ -0,0 +1,48 @@
+# SMP Li-Po 4335mAh
+description: "SMP LiPo 4335mAh AS3GWQd3jB C490-42"
+compatible: "smp,c31n2005"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "smp,c31n2005"
+
+  # Fuel gauge
+  manuf_name:
+    default: "AS3GWQd3jB"
+  device_name:
+    default: "C490-42"
+  ship_mode_reg_addr:
+    default: 0x00
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  fet_reg_addr:
+    default: 0x99
+  fet_reg_mask:
+    default: 0x000c
+  fet_disconnect_val:
+    default: 0x000c
+
+  # Battery info
+  voltage_max:
+    default: 13200
+  voltage_normal:
+    default: 11880
+  voltage_min:
+    default: 9000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 45
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -20
+  discharging_max_c:
+    default: 60
diff --git a/zephyr/dts/bindings/battery/smp,cos26jgk.yaml b/zephyr/dts/bindings/battery/smp,cos26jgk.yaml
new file mode 100644
index 0000000000..4e0697c74e
--- /dev/null
+++ b/zephyr/dts/bindings/battery/smp,cos26jgk.yaml
@@ -0,0 +1,61 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "SMP-COS3.63 DELL 26JGK"
+compatible: "smp,cos26jgk"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "smp,cos26jgk"
+
+  # Fuel gauge
+  manuf_name:
+    default: "SMP-COS3.63"
+  device_name:
+    default: "DELL 26JGK"
+  ship_mode_wb_support:
+    default: 1
+  ship_mode_reg_addr:
+    default: 0x44
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  fet_mfgacc_support:
+    default: 1
+  fet_mfgacc_smb_block:
+    default: 1
+  fet_reg_addr:
+    default: 0x0054
+  fet_reg_mask:
+    default: 0x0006
+  fet_disconnect_val:
+    default: 0x0000
+  fet_cfet_mask:
+    default: 0x0004
+  fet_cfet_off_val:
+    default: 0x0000
+
+  # Battery info
+  voltage_max:
+    default: 13200
+  voltage_normal:
+    default: 11400
+  voltage_min:
+    default: 9000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: -3
+  start_charging_max_c:
+    default: 50
+  charging_min_c:
+    default: -3
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -5
+  discharging_max_c:
+    default: 70
diff --git a/zephyr/dts/bindings/battery/smp,coslight_gh02047xl.yaml b/zephyr/dts/bindings/battery/smp,coslight_gh02047xl.yaml
new file mode 100644
index 0000000000..7851b496a6
--- /dev/null
+++ b/zephyr/dts/bindings/battery/smp,coslight_gh02047xl.yaml
@@ -0,0 +1,53 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "SMP COSLIGHT_GH02047XL"
+compatible: "smp,coslight_gh02047xl"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "smp,coslight_gh02047xl"
+
+  # Fuel gauge
+  manuf_name:
+    default: "333-1C-DA-A"
+  device_name:
+    default: "GH02047XL"
+  ship_mode_reg_addr:
+    default: 0x00
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  fet_mfgacc_support:
+    default: 1
+  fet_reg_addr:
+    default: 0x0
+  fet_reg_mask:
+    default: 0x0006
+  fet_disconnect_val:
+    default: 0x0
+
+  # Battery info
+  voltage_max:
+    default: 8800
+  voltage_normal:
+    default: 7700
+  voltage_min:
+    default: 6000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 45
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 45
+  discharging_min_c:
+    default: -10
+  discharging_max_c:
+    default: 60
diff --git a/zephyr/dts/bindings/battery/smp,cosrf9h3.yaml b/zephyr/dts/bindings/battery/smp,cosrf9h3.yaml
new file mode 100644
index 0000000000..bc18f77a28
--- /dev/null
+++ b/zephyr/dts/bindings/battery/smp,cosrf9h3.yaml
@@ -0,0 +1,55 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "SMP-COS3.63 DELL RF9H3"
+compatible: "smp,cosrf9h3"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "smp,cosrf9h3"
+
+  # Fuel gauge
+  manuf_name:
+    default: "SMP-COS3.63"
+  device_name:
+    default: "DELL RF9H3"
+  ship_mode_reg_addr:
+    default: 0x00
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  fet_reg_addr:
+    default: 0x43
+  fet_reg_mask:
+    default: 0x0003
+  fet_disconnect_val:
+    default: 0x0000
+  fet_cfet_mask:
+    default: 0x0002
+  fet_cfet_off_val:
+    default: 0x0000
+
+  # Battery info
+  voltage_max:
+    default: 13200
+  voltage_normal:
+    default: 11400
+  voltage_min:
+    default: 9000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: -3
+  start_charging_max_c:
+    default: 50
+  charging_min_c:
+    default: -3
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -5
+  discharging_max_c:
+    default: 70
diff --git a/zephyr/dts/bindings/battery/smp,cosxdy9k.yaml b/zephyr/dts/bindings/battery/smp,cosxdy9k.yaml
new file mode 100644
index 0000000000..6037a27ef0
--- /dev/null
+++ b/zephyr/dts/bindings/battery/smp,cosxdy9k.yaml
@@ -0,0 +1,51 @@
+description: "SMP-ATL SMP-COS3.66 "
+compatible: "smp,cosxdy9k"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "smp,cosxdy9k"
+
+  # Fuel gauge
+  manuf_name:
+    default: "SMP-COS3.66"
+  device_name:
+    default: "DELL XDY9K"
+  ship_mode_reg_addr:
+    default: 0x00
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  fet_reg_addr:
+    default: 0x43
+  fet_reg_mask:
+    default: 0x0001
+  fet_disconnect_val:
+    default: 0x0000
+  fet_cfet_mask:
+    default: 0x0002
+  fet_cfet_off_val:
+    default: 0x0000
+
+  # Battery info
+  voltage_max:
+    default: 17600
+  voltage_normal:
+    default: 15000
+  voltage_min:
+    default: 12000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: -3
+  start_charging_max_c:
+    default: 45
+  charging_min_c:
+    default: -3
+  charging_max_c:
+    default: 50
+  discharging_min_c:
+    default: -17
+  discharging_max_c:
+    default: 70
diff --git a/zephyr/dts/bindings/battery/smp,highpower_gh02047xl.yaml b/zephyr/dts/bindings/battery/smp,highpower_gh02047xl.yaml
new file mode 100644
index 0000000000..bd9b70daa1
--- /dev/null
+++ b/zephyr/dts/bindings/battery/smp,highpower_gh02047xl.yaml
@@ -0,0 +1,53 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "SMP HIGHPOWER_GH02047XL"
+compatible: "smp,highpower_gh02047xl"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "smp,highpower_gh02047xl"
+
+  # Fuel gauge
+  manuf_name:
+    default: "333-1D-DA-A"
+  device_name:
+    default: "GH02047XL"
+  ship_mode_reg_addr:
+    default: 0x00
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  fet_mfgacc_support:
+    default: 1
+  fet_reg_addr:
+    default: 0x0
+  fet_reg_mask:
+    default: 0x0006
+  fet_disconnect_val:
+    default: 0x0
+
+  # Battery info
+  voltage_max:
+    default: 8800
+  voltage_normal:
+    default: 7700
+  voltage_min:
+    default: 6000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 45
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 45
+  discharging_min_c:
+    default: -10
+  discharging_max_c:
+    default: 60
diff --git a/zephyr/dts/bindings/battery/smp,highpower_si03058xl.yaml b/zephyr/dts/bindings/battery/smp,highpower_si03058xl.yaml
new file mode 100644
index 0000000000..5346241090
--- /dev/null
+++ b/zephyr/dts/bindings/battery/smp,highpower_si03058xl.yaml
@@ -0,0 +1,53 @@
+# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "SMP HIGHPOWER_SI03058XL"
+compatible: "smp,highpower_si03058xl"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "smp,highpower_si03058xl"
+
+  # Fuel gauge
+  manuf_name:
+    default: "333-1D-11-A"
+  device_name:
+    default: "SI03058XL"
+  ship_mode_reg_addr:
+    default: 0x00
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  fet_mfgacc_support:
+    default: 1
+  fet_reg_addr:
+    default: 0x0
+  fet_reg_mask:
+    default: 0x0006
+  fet_disconnect_val:
+    default: 0x0
+
+  # Battery info
+  voltage_max:
+    default: 13200
+  voltage_normal:
+    default: 11550
+  voltage_min:
+    default: 9000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 45
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 45
+  discharging_min_c:
+    default: -20
+  discharging_max_c:
+    default: 60
diff --git a/zephyr/dts/bindings/battery/smp,l20m3pg0.yaml b/zephyr/dts/bindings/battery/smp,l20m3pg0.yaml
new file mode 100644
index 0000000000..67e09a311e
--- /dev/null
+++ b/zephyr/dts/bindings/battery/smp,l20m3pg0.yaml
@@ -0,0 +1,53 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "SMP L20M3PG0"
+compatible: "smp,l20m3pg0"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "smp,l20m3pg0"
+
+  # Fuel gauge
+  manuf_name:
+    default: "SMP"
+  device_name:
+    default: "L20M3PG0"
+  ship_mode_reg_addr:
+    default: 0x34
+  ship_mode_reg_data:
+    default: [0x0000, 0x1000]
+  fet_mfgacc_support:
+    default: 0
+  fet_reg_addr:
+    default: 0x34
+  fet_reg_mask:
+    default: 0x0100
+  fet_disconnect_val:
+    default: 0x0100
+
+  # Battery info
+  voltage_max:
+    default: 13200
+  voltage_normal:
+    default: 11520
+  voltage_min:
+    default: 9000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 45
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -20
+  discharging_max_c:
+    default: 50
diff --git a/zephyr/dts/bindings/battery/smp,l20m3pg1.yaml b/zephyr/dts/bindings/battery/smp,l20m3pg1.yaml
new file mode 100644
index 0000000000..693df956db
--- /dev/null
+++ b/zephyr/dts/bindings/battery/smp,l20m3pg1.yaml
@@ -0,0 +1,57 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "SMP L20M30PG1"
+compatible: "smp,l20m3pg1"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "smp,l20m3pg1"
+
+  # TI L20M3PG1 Fuel Gauge
+  manuf_name:
+    default: "SMP"
+  device_name:
+    default: "L20M3PG1"
+  ship_mode_reg_addr:
+    default: 0x00
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  fet_mfgacc_support:
+    default: 1
+  fet_reg_addr:
+    default: 0x0054
+  fet_reg_mask:
+    default: 0x2000
+  fet_disconnect_val:
+    default: 0x2000
+  fet_cfet_mask:
+    default: 0x6000
+  fet_cfet_off_val:
+    default: 0x6000
+
+  # Battery info
+  voltage_max:
+    default: 13200
+  voltage_normal:
+    default: 11520
+  voltage_min:
+    default: 9000
+  precharge_current:
+    default: 247
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 50
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -40
+  discharging_max_c:
+    default: 73
diff --git a/zephyr/dts/bindings/battery/smp,l20m3pg2.yaml b/zephyr/dts/bindings/battery/smp,l20m3pg2.yaml
new file mode 100644
index 0000000000..6b7b18ba4a
--- /dev/null
+++ b/zephyr/dts/bindings/battery/smp,l20m3pg2.yaml
@@ -0,0 +1,53 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "SMP L20M3PG2"
+compatible: "smp,l20m3pg2"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "smp,l20m3pg2"
+
+  # Fuel gauge
+  manuf_name:
+    default: "SMP"
+  device_name:
+    default: "L20M3PG2"
+  ship_mode_reg_addr:
+    default: 0x34
+  ship_mode_reg_data:
+    default: [0x0000, 0x0100]
+  fet_mfgacc_support:
+    default: 0
+  fet_reg_addr:
+    default: 0x34
+  fet_reg_mask:
+    default: 0x0100
+  fet_disconnect_val:
+    default: 0x0100
+
+  # Battery info
+  voltage_max:
+    default: 13050
+  voltage_normal:
+    default: 11250
+  voltage_min:
+    default: 9000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 45
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 45
+  discharging_min_c:
+    default: -20
+  discharging_max_c:
+    default: 60
diff --git a/zephyr/dts/bindings/battery/smp,l21m4pg0.yaml b/zephyr/dts/bindings/battery/smp,l21m4pg0.yaml
new file mode 100644
index 0000000000..6f3f093fa8
--- /dev/null
+++ b/zephyr/dts/bindings/battery/smp,l21m4pg0.yaml
@@ -0,0 +1,53 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "SMP L21M4PG0"
+compatible: "smp,l21m4pg0"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "smp,l21m4pg0"
+
+  # Fuel gauge
+  manuf_name:
+    default: "SMP"
+  device_name:
+    default: "L21M4PG0"
+  ship_mode_reg_addr:
+    default: 0x34
+  ship_mode_reg_data:
+    default: [0x0000, 0x1000]
+  fet_mfgacc_support:
+    default: 0
+  fet_reg_addr:
+    default: 0x34
+  fet_reg_mask:
+    default: 0x0100
+  fet_disconnect_val:
+    default: 0x0100
+
+  # Battery info
+  voltage_max:
+    default: 8900
+  voltage_normal:
+    default: 7720
+  voltage_min:
+    default: 6000
+  precharge_current:
+    default: 274
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 50
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -20
+  discharging_max_c:
+    default: 60
diff --git a/zephyr/dts/bindings/battery/smp,l22m3pg0.yaml b/zephyr/dts/bindings/battery/smp,l22m3pg0.yaml
new file mode 100644
index 0000000000..76fb5ae6d4
--- /dev/null
+++ b/zephyr/dts/bindings/battery/smp,l22m3pg0.yaml
@@ -0,0 +1,53 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "SMP L22M3PG0"
+compatible: "smp,l22m3pg0"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "smp,l22m3pg0"
+
+  # Fuel gauge
+  manuf_name:
+    default: "SMP"
+  device_name:
+    default: "L22M3PG0"
+  ship_mode_reg_addr:
+    default: 0x34
+  ship_mode_reg_data:
+    default: [0x0000, 0x1000]
+  fet_mfgacc_support:
+    default: 0
+  fet_reg_addr:
+    default: 0x00
+  fet_reg_mask:
+    default: 0x0018
+  fet_disconnect_val:
+    default: 0x0000
+
+  # Battery info
+  voltage_max:
+    default: 13200
+  voltage_normal:
+    default: 11310
+  voltage_min:
+    default: 9000
+  precharge_current:
+    default: 208
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 50
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -20
+  discharging_max_c:
+    default: 60
diff --git a/zephyr/dts/bindings/battery/smp,l22m3pg1.yaml b/zephyr/dts/bindings/battery/smp,l22m3pg1.yaml
new file mode 100644
index 0000000000..8b6c1dd790
--- /dev/null
+++ b/zephyr/dts/bindings/battery/smp,l22m3pg1.yaml
@@ -0,0 +1,53 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "SMP L22M3PG1"
+compatible: "smp,l22m3pg1"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "smp,l22m3pg1"
+
+  # Fuel gauge
+  manuf_name:
+    default: "SMP"
+  device_name:
+    default: "L22M3PG1"
+  ship_mode_reg_addr:
+    default: 0x34
+  ship_mode_reg_data:
+    default: [0x0000, 0x1000]
+  fet_mfgacc_support:
+    default: 0
+  fet_reg_addr:
+    default: 0x00
+  fet_reg_mask:
+    default: 0x0018
+  fet_disconnect_val:
+    default: 0x0000
+
+  # Battery info
+  voltage_max:
+    default: 13200
+  voltage_normal:
+    default: 11520
+  voltage_min:
+    default: 9000
+  precharge_current:
+    default: 248
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 50
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -20
+  discharging_max_c:
+    default: 60
diff --git a/zephyr/dts/bindings/battery/smp,pc-vp-bp153.yaml b/zephyr/dts/bindings/battery/smp,pc-vp-bp153.yaml
new file mode 100644
index 0000000000..d666b83e2b
--- /dev/null
+++ b/zephyr/dts/bindings/battery/smp,pc-vp-bp153.yaml
@@ -0,0 +1,53 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "SMP PC-VP-BP153"
+compatible: "smp,pc-vp-bp153"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "smp,pc-vp-bp153"
+
+  # Fuel gauge
+  manuf_name:
+    default: "SIMPLO"
+  device_name:
+    default: "PC-VP-BP153"
+  ship_mode_reg_addr:
+    default: 0x34
+  ship_mode_reg_data:
+    default: [0x0000, 0x1000]
+  fet_mfgacc_support:
+    default: 0
+  fet_reg_addr:
+    default: 0x00
+  fet_reg_mask:
+    default: 0x10
+  fet_disconnect_val:
+    default: 0x00
+
+  # Battery info
+  voltage_max:
+    default: 8800
+  voltage_normal:
+    default: 7680
+  voltage_min:
+    default: 6000
+  precharge_current:
+    default: 128
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 50
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -20
+  discharging_max_c:
+    default: 70
diff --git a/zephyr/dts/bindings/battery/smp,si03054xl.yaml b/zephyr/dts/bindings/battery/smp,si03054xl.yaml
new file mode 100644
index 0000000000..ba16bc66f6
--- /dev/null
+++ b/zephyr/dts/bindings/battery/smp,si03054xl.yaml
@@ -0,0 +1,53 @@
+# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "SMP SI03054XL"
+compatible: "smp,si03054xl"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "smp,si03054xl"
+
+  # Fuel gauge
+  manuf_name:
+    default: "333-1D-1A-A"
+  device_name:
+    default: "si03054XL"
+  ship_mode_reg_addr:
+    default: 0x00
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  fet_mfgacc_support:
+    default: 1
+  fet_reg_addr:
+    default: 0x0
+  fet_reg_mask:
+    default: 0x0006
+  fet_disconnect_val:
+    default: 0x0
+
+  # Battery info
+  voltage_max:
+    default: 13200
+  voltage_normal:
+    default: 11550
+  voltage_min:
+    default: 9000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 45
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 45
+  discharging_min_c:
+    default: -20
+  discharging_max_c:
+    default: 60
diff --git a/zephyr/dts/bindings/battery/sunwoda,atlvkyjx.yaml b/zephyr/dts/bindings/battery/sunwoda,atlvkyjx.yaml
new file mode 100644
index 0000000000..4b54e922c3
--- /dev/null
+++ b/zephyr/dts/bindings/battery/sunwoda,atlvkyjx.yaml
@@ -0,0 +1,55 @@
+description: "SUNWODA SWD-ATL3.660"
+compatible: "sunwoda,atlvkyjx"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "sunwoda,atlvkyjx"
+
+  # Fuel Gauge
+  manuf_name:
+    default: "SWD-ATL3.660"
+  device_name:
+    default: "DELL VKYJX"
+  ship_mode_reg_addr:
+    default: 0x00
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  fet_mfgacc_support:
+    default: 1
+  fet_mfgacc_smb_block:
+    default: 1
+  fet_reg_addr:
+    default: 0x54
+  fet_reg_mask:
+    default: 0x0002
+  fet_disconnect_val:
+    default: 0x0000
+  fet_cfet_mask:
+    default: 0x0004
+  fet_cfet_off_val:
+    default: 0x0000
+
+  # Battery info
+  voltage_max:
+    default: 17600
+  voltage_normal:
+    default: 15000
+  voltage_min:
+    default: 12000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 45
+  charging_min_c:
+    default: -3
+  charging_max_c:
+    default: 50
+  discharging_min_c:
+    default: -5
+  discharging_max_c:
+    default: 70
diff --git a/zephyr/dts/bindings/battery/sunwoda,cosctgkt.yaml b/zephyr/dts/bindings/battery/sunwoda,cosctgkt.yaml
new file mode 100644
index 0000000000..6b6d412930
--- /dev/null
+++ b/zephyr/dts/bindings/battery/sunwoda,cosctgkt.yaml
@@ -0,0 +1,61 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "SWD-COS3.634 DELL CTGKT"
+compatible: "sunwoda,cosctgkt"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "sunwoda,cosctgkt"
+
+  # Fuel Gauge
+  manuf_name:
+    default: "SWD-COS3.634"
+  device_name:
+    default: "DELL CTGKT"
+  ship_mode_wb_support:
+    default: 1
+  ship_mode_reg_addr:
+    default: 0x44
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  fet_mfgacc_support:
+    default: 1
+  fet_mfgacc_smb_block:
+    default: 1
+  fet_reg_addr:
+    default: 0x0054
+  fet_reg_mask:
+    default: 0x0006
+  fet_disconnect_val:
+    default: 0x0000
+  fet_cfet_mask:
+    default: 0x0004
+  fet_cfet_off_val:
+    default: 0x0000
+
+  # Battery info
+  voltage_max:
+    default: 13200
+  voltage_normal:
+    default: 11400
+  voltage_min:
+    default: 9000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 50
+  charging_min_c:
+    default: -3
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -5
+  discharging_max_c:
+    default: 70
diff --git a/zephyr/dts/bindings/battery/sunwoda,cosvkyjx.yaml b/zephyr/dts/bindings/battery/sunwoda,cosvkyjx.yaml
new file mode 100644
index 0000000000..64f40761bd
--- /dev/null
+++ b/zephyr/dts/bindings/battery/sunwoda,cosvkyjx.yaml
@@ -0,0 +1,55 @@
+description: "SUNWODA SWD-COS3.661"
+compatible: "sunwoda,cosvkyjx"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "sunwoda,cosvkyjx"
+
+  # Fuel Gauge
+  manuf_name:
+    default: "SWD-COS3.661"
+  device_name:
+    default: "DELL VKYJX"
+  ship_mode_reg_addr:
+    default: 0x00
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  fet_mfgacc_support:
+    default: 1
+  fet_mfgacc_smb_block:
+    default: 1
+  fet_reg_addr:
+    default: 0x54
+  fet_reg_mask:
+    default: 0x0002
+  fet_disconnect_val:
+    default: 0x0000
+  fet_cfet_mask:
+    default: 0x0004
+  fet_cfet_off_val:
+    default: 0x0000
+
+  # Battery info
+  voltage_max:
+    default: 17600
+  voltage_normal:
+    default: 15000
+  voltage_min:
+    default: 12000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 45
+  charging_min_c:
+    default: -3
+  charging_max_c:
+    default: 50
+  discharging_min_c:
+    default: -5
+  discharging_max_c:
+    default: 70
diff --git a/zephyr/dts/bindings/battery/sunwoda,ctgkt.yaml b/zephyr/dts/bindings/battery/sunwoda,ctgkt.yaml
new file mode 100644
index 0000000000..baf81cd446
--- /dev/null
+++ b/zephyr/dts/bindings/battery/sunwoda,ctgkt.yaml
@@ -0,0 +1,61 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "SWD-ATL3.618 DELL CTGKT"
+compatible: "sunwoda,ctgkt"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "sunwoda,ctgkt"
+
+  # Fuel Gauge
+  manuf_name:
+    default: "SWD-ATL3.618"
+  device_name:
+    default: "DELL CTGKT"
+  ship_mode_wb_support:
+    default: 1
+  ship_mode_reg_addr:
+    default: 0x44
+  ship_mode_reg_data:
+    default: [0x0010, 0x0010]
+  fet_mfgacc_support:
+    default: 1
+  fet_mfgacc_smb_block:
+    default: 1
+  fet_reg_addr:
+    default: 0x0054
+  fet_reg_mask:
+    default: 0x0006
+  fet_disconnect_val:
+    default: 0x0000
+  fet_cfet_mask:
+    default: 0x0004
+  fet_cfet_off_val:
+    default: 0x0000
+
+  # Battery info
+  voltage_max:
+    default: 13200
+  voltage_normal:
+    default: 11400
+  voltage_min:
+    default: 9000
+  precharge_current:
+    default: 256
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 50
+  charging_min_c:
+    default: -3
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -5
+  discharging_max_c:
+    default: 70
diff --git a/zephyr/dts/bindings/battery/sunwoda,l22d3pg0.yaml b/zephyr/dts/bindings/battery/sunwoda,l22d3pg0.yaml
new file mode 100644
index 0000000000..d96b035293
--- /dev/null
+++ b/zephyr/dts/bindings/battery/sunwoda,l22d3pg0.yaml
@@ -0,0 +1,53 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "SUNWODA L22D3PG0"
+compatible: "sunwoda,l22d3pg0"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "sunwoda,l22d3pg0"
+
+  # Fuel gauge
+  manuf_name:
+    default: "Sunwoda"
+  device_name:
+    default: "L22D3PG0"
+  ship_mode_reg_addr:
+    default: 0x34
+  ship_mode_reg_data:
+    default: [0x0000, 0x1000]
+  fet_mfgacc_support:
+    default: 0
+  fet_reg_addr:
+    default: 0x00
+  fet_reg_mask:
+    default: 0x0018
+  fet_disconnect_val:
+    default: 0x0000
+
+  # Battery info
+  voltage_max:
+    default: 13200
+  voltage_normal:
+    default: 11310
+  voltage_min:
+    default: 9000
+  precharge_current:
+    default: 209
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 50
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -20
+  discharging_max_c:
+    default: 60
diff --git a/zephyr/dts/bindings/battery/sunwoda,l22d3pg1.yaml b/zephyr/dts/bindings/battery/sunwoda,l22d3pg1.yaml
new file mode 100644
index 0000000000..6a83d8f9d3
--- /dev/null
+++ b/zephyr/dts/bindings/battery/sunwoda,l22d3pg1.yaml
@@ -0,0 +1,53 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "SUNWODA L22D3PG1"
+compatible: "sunwoda,l22d3pg1"
+
+include: battery-smart.yaml
+
+properties:
+  enum-name:
+    type: string
+    default: "sunwoda,l22d3pg1"
+
+  # Fuel gauge
+  manuf_name:
+    default: "Sunwoda"
+  device_name:
+    default: "L22D3PG1"
+  ship_mode_reg_addr:
+    default: 0x34
+  ship_mode_reg_data:
+    default: [0x0000, 0x1000]
+  fet_mfgacc_support:
+    default: 0
+  fet_reg_addr:
+    default: 0x00
+  fet_reg_mask:
+    default: 0x0018
+  fet_disconnect_val:
+    default: 0x0000
+
+  # Battery info
+  voltage_max:
+    default: 13200
+  voltage_normal:
+    default: 11520
+  voltage_min:
+    default: 9000
+  precharge_current:
+    default: 251
+  start_charging_min_c:
+    default: 0
+  start_charging_max_c:
+    default: 50
+  charging_min_c:
+    default: 0
+  charging_max_c:
+    default: 60
+  discharging_min_c:
+    default: -20
+  discharging_max_c:
+    default: 60
diff --git a/zephyr/dts/bindings/cbi/cros-ec,cbi-fw-config-value.yaml b/zephyr/dts/bindings/cbi/cros-ec,cbi-fw-config-value.yaml
new file mode 100644
index 0000000000..5a0edc8f72
--- /dev/null
+++ b/zephyr/dts/bindings/cbi/cros-ec,cbi-fw-config-value.yaml
@@ -0,0 +1,27 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description:
+  Possible CBI FW_CONFIG individual field values.
+  It has to be defined as a grandchild on the "cros-ec,cbi-fw-config" nodes
+
+compatible: "cros-ec,cbi-fw-config-value"
+
+properties:
+  enum-name:
+    type: string
+    required: true
+    description:
+      Name of the value used for description purposes
+  value:
+    type: int
+    required: true
+    description:
+      Unique value within the parent CBI FW_CONFIG field
+  default:
+    type: boolean
+    description:
+      If set, this value will be the default value of this field
+      if the FW_CONFIG data is invalid or unavailable. It must
+      appear only once for any single field.
diff --git a/zephyr/dts/bindings/cbi/cros-ec,cbi-fw-config.yaml b/zephyr/dts/bindings/cbi/cros-ec,cbi-fw-config.yaml
new file mode 100644
index 0000000000..530ec24b25
--- /dev/null
+++ b/zephyr/dts/bindings/cbi/cros-ec,cbi-fw-config.yaml
@@ -0,0 +1,54 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: CBI Firmware Config fields (FW_CONFIG)
+
+compatible: "cros-ec,cbi-fw-config"
+
+child-binding:
+  description:
+    ChromeOS CBI Firmware Config fields definition.
+    Each field is defined via a start bit (from LSB) and a size.
+    The total size of all FW_CONFIG bit fields must not exceed 32 bits.
+    One default value for each field may be indicated.
+  properties:
+    enum-name:
+      type: string
+      required: true
+      description:
+        Name of field used for description purposes
+    start:
+      type: int
+      required: true
+      description: The starting bit of the field (LSB = 0)
+    size:
+      type: int
+      required: true
+      description: The size of the field in bits.
+
+# Example:
+#
+# cbi-fw-config {
+#     compatible = "cros-ec,cbi-fw-config";
+#
+#     fan {
+#         enum-name = "FAN";
+#         start = <0>
+#         size = <1>;
+#         fan_absent {
+#             enum-name = "ABSENT"
+#             compatible = "cros-ec,cbi-fw-config-value";
+#             value = <0>;
+#         fan_present {
+#             enum-name = "PRESENT"
+#             compatible = "cros-ec,cbi-fw-config-value";
+#             value = <1>;
+#             default;
+#         };
+#     };
+# };
+#
+# This will generate an enum field id for CBI_FW_CONFIG_FIELD_FAN,
+# and separate values for CBI_FW_CONFIG_FIELD_FAN_ABSENT = 0 and
+# CBI_FW_CONFIG_FIELD_FAN_PRESENT = 1
diff --git a/zephyr/dts/bindings/cbi/cros-ec,cbi-ssfc-value.yaml b/zephyr/dts/bindings/cbi/cros-ec,cbi-ssfc-value.yaml
new file mode 100644
index 0000000000..e76cd08293
--- /dev/null
+++ b/zephyr/dts/bindings/cbi/cros-ec,cbi-ssfc-value.yaml
@@ -0,0 +1,22 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description:
+  Possible CBI SSFC field values.
+  It has to be defined as grandchild on the "cros-ec,cbi-ssfc"
+
+compatible: "cros-ec,cbi-ssfc-value"
+
+properties:
+  value:
+    type: int
+    required: true
+    description:
+      Unique value of CBI SSFC field
+  default:
+    type: boolean
+    description:
+      Indicates that the specified value is default for the parent
+      CBI SSFC field node. It should appear only once for the CBI SSFC
+      definition.
diff --git a/zephyr/dts/bindings/cbi/cros-ec,cbi-ssfc.yaml b/zephyr/dts/bindings/cbi/cros-ec,cbi-ssfc.yaml
new file mode 100644
index 0000000000..442be1b4dc
--- /dev/null
+++ b/zephyr/dts/bindings/cbi/cros-ec,cbi-ssfc.yaml
@@ -0,0 +1,56 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: CBI Second Source Factory Cache (SSFC)
+
+compatible: "cros-ec,cbi-ssfc"
+
+child-binding:
+  description:
+    CBI SSFC fields definition.
+    The order of the children in this node define the order
+    of the SSFC bit fields from least significant bit to most
+    significant bit. The total size of all SSFC bit fields
+    must not exceed 32 bits.
+  properties:
+    enum-name:
+      type: string
+      required: true
+      description:
+        Enum values used only for description purposes
+      enum:
+      - AUDIO_CODEC
+      - BASE_SENSOR
+      - LID_SENSOR
+      - LIGHTBAR
+      - USB_SS_MUX
+    size:
+      type: int
+      required: true
+      description: The size of the field in bits.
+
+# Example:
+#
+# cbi-ssfc {
+#     compatible = "cros-ec,cbi-ssfc";
+#
+#     base_sensor {
+#         enum-name = "BASE_SENSOR";
+#         size = <3>;
+#         bmi160 {
+#             compatible = "cros-ec,cbi-ssfc-value";
+#             status = "okay";
+#
+#             value = <1>;
+#             devices = <&alt_base_accel &alt_base_gyro>;
+#         };
+#         kx022 {
+#             compatible = "cros-ec,cbi-ssfc-value";
+#             status = "okay";
+#
+#             value = <3>;
+#             devices = <&base_accel_kx022>;
+#         };
+#     };
+# };
diff --git a/zephyr/dts/bindings/charger/chg-chip.yaml b/zephyr/dts/bindings/charger/chg-chip.yaml
new file mode 100644
index 0000000000..5d6bee1ecc
--- /dev/null
+++ b/zephyr/dts/bindings/charger/chg-chip.yaml
@@ -0,0 +1,72 @@
+# Copyright 2022 The ChromiumOS Authors
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Charger chip
+
+  Example
+  The charger chips nodes have to be placed under the USB-C
+  nodes(named-usbc-port).If the OCPC(on-charger per type-c port) config is
+  enabled, the charger chips has to be defiend per USB-C port, with the primary
+  one defined under port 0. If the CHARGER_SINGLE_CHIP config is enabled, only
+  one charger chip must be defined. It has to be done under the port 0.
+  For OCPC:
+        usbc {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                port0@0 {
+                        compatible = "named-usbc-port";
+                        reg = <0>;
+                        bc12 = <&bc12_port0>;
+                        chg = <&chg_port0>;
+                };
+                port1@1 {
+                        compatible = "named-usbc-port";
+                        reg = <1>;
+                        bc12 = <&bc12_port1>;
+                        chg = <&chg_port1>;
+                };
+        };
+
+        &i2c5 {
+                        compatible = "siliconmitus,sm5803";
+                        status = "okay";
+                        reg = <0x32>;
+                };
+        };
+
+        &i2c4 {
+                chg_port1: sm5803@32 {
+                        compatible = "siliconmitus,sm5803";
+                        status = "okay";
+                        reg = <0x32>;
+                };
+        };
+
+  For CHARGER_SINGLE_CHIP:
+        usbc {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                port0@0 {
+                        compatible = "named-usbc-port";
+                        reg = <0>;
+                        chg = <&charger>;
+                };
+                port1@1 {
+                        compatible = "named-usbc-port";
+                        reg = <1>;
+                        bc12 = <&bc12_port1>;
+                };
+        };
+
+        &i2c5 {
+                charger: sm5803@32 {
+                        compatible = "siliconmitus,sm5803";
+                        status = "okay";
+                        reg = <0x32>;
+                };
+        };
+
+include: i2c-device.yaml
diff --git a/zephyr/dts/bindings/charger/intersil,isl923x.yaml b/zephyr/dts/bindings/charger/intersil,isl923x.yaml
new file mode 100644
index 0000000000..a9c2e8f814
--- /dev/null
+++ b/zephyr/dts/bindings/charger/intersil,isl923x.yaml
@@ -0,0 +1,9 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Intersil ISL923x Charger IC
+
+compatible: "intersil,isl923x"
+
+include: chg-chip.yaml
diff --git a/zephyr/dts/bindings/charger/intersil,isl9241.yaml b/zephyr/dts/bindings/charger/intersil,isl9241.yaml
new file mode 100644
index 0000000000..7423e46a23
--- /dev/null
+++ b/zephyr/dts/bindings/charger/intersil,isl9241.yaml
@@ -0,0 +1,9 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Intersil ISL9241 Charger IC
+
+compatible: "intersil,isl9241"
+
+include: chg-chip.yaml
diff --git a/zephyr/dts/bindings/charger/richtek,rt9490.yaml b/zephyr/dts/bindings/charger/richtek,rt9490.yaml
new file mode 100644
index 0000000000..b26169c6c9
--- /dev/null
+++ b/zephyr/dts/bindings/charger/richtek,rt9490.yaml
@@ -0,0 +1,39 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Richtek RT9490 Charger
+
+compatible: "richtek,rt9490"
+
+include: chg-chip.yaml
+
+properties:
+  irq:
+    type: phandles
+    description: |
+        GPIO interrupt from BC1.2
+
+  thermistor:
+    type: phandle
+    description: Underlying thermistor device to measure temperature
+
+  eoc-current:
+    type: int
+    default: 240
+    description: End-of-charge current in mA, between 40 to 1000.
+
+  mivr:
+    type: int
+    default: 3800
+    description: Minimum input voltage regulation in mV, between 3600 to 22000.
+
+  boost-voltage:
+    type: int
+    default: 5050
+    description: OTG voltage limit regulation in mV, between 2800 to 22000.
+
+  boost-current:
+    type: int
+    default: 1500
+    description: OTG current limit regulation in mA, between 120 to 3320.
diff --git a/zephyr/dts/bindings/charger/siliconmitus,sm5803.yaml b/zephyr/dts/bindings/charger/siliconmitus,sm5803.yaml
new file mode 100644
index 0000000000..20d88d1659
--- /dev/null
+++ b/zephyr/dts/bindings/charger/siliconmitus,sm5803.yaml
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Silicon Mitus SM5803 Charger
+
+compatible: "siliconmitus,sm5803"
+
+include: chg-chip.yaml
diff --git a/zephyr/dts/bindings/charger/ti,bq25710.yaml b/zephyr/dts/bindings/charger/ti,bq25710.yaml
new file mode 100644
index 0000000000..d0bc20a015
--- /dev/null
+++ b/zephyr/dts/bindings/charger/ti,bq25710.yaml
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: TI BQ25710 Charger
+
+compatible: "ti,bq25710"
+
+include: chg-chip.yaml
diff --git a/zephyr/dts/bindings/console/ec-console.yaml b/zephyr/dts/bindings/console/ec-console.yaml
new file mode 100644
index 0000000000..ba28681dce
--- /dev/null
+++ b/zephyr/dts/bindings/console/ec-console.yaml
@@ -0,0 +1,14 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: EC Console node
+
+compatible: "ec-console"
+
+properties:
+  disabled:
+    required: false
+    type: string-array
+    description:
+      List of EC channel names that are disabled in the output by default.
diff --git a/zephyr/dts/bindings/cros_bbram/named-bbram-regions.yaml b/zephyr/dts/bindings/cros_bbram/named-bbram-regions.yaml
new file mode 100644
index 0000000000..65be1fa48e
--- /dev/null
+++ b/zephyr/dts/bindings/cros_bbram/named-bbram-regions.yaml
@@ -0,0 +1,15 @@
+# Copyright 2021 Google LLC
+# SPDX-License-Identifier: Apache-2.0
+description: Named battery-backed RAM parent node
+
+compatible: "named-bbram-regions"
+
+child-binding:
+  description: Named battery-backed RAM child node
+  properties:
+    offset:
+      type: int
+      required: true
+    size:
+      type: int
+      required: true
diff --git a/zephyr/dts/bindings/cros_dbg/nuvoton,npcx-cros-dbg.yaml b/zephyr/dts/bindings/cros_dbg/nuvoton,npcx-cros-dbg.yaml
new file mode 100644
index 0000000000..2319458502
--- /dev/null
+++ b/zephyr/dts/bindings/cros_dbg/nuvoton,npcx-cros-dbg.yaml
@@ -0,0 +1,19 @@
+# Copyright 2021 Google LLC
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nuvoton, NPCX Debug Interface
+
+compatible: "nuvoton,npcx-cros-dbg"
+
+include: [base.yaml, pinctrl-device.yaml]
+
+
+properties:
+  reg:
+    required: true
+
+  pinctrl-0:
+    required: true
+
+  pinctrl-names:
+    required: true
diff --git a/zephyr/dts/bindings/cros_displight/cros-ec,displight.yaml b/zephyr/dts/bindings/cros_displight/cros-ec,displight.yaml
new file mode 100644
index 0000000000..1ce1892fd2
--- /dev/null
+++ b/zephyr/dts/bindings/cros_displight/cros-ec,displight.yaml
@@ -0,0 +1,20 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Display backlight configuration
+
+compatible: "cros-ec,displight"
+
+include: base.yaml
+
+properties:
+  pwms:
+    type: phandle-array
+    required: true
+    description: PWM controlling the display backlight level.
+
+  generic-pwm-channel:
+    type: int
+    required: false
+    description: Generic PWM channel number for legacy compatibility.
diff --git a/zephyr/dts/bindings/cros_flash/cros-ec,cros-flash.yaml b/zephyr/dts/bindings/cros_flash/cros-ec,cros-flash.yaml
new file mode 100644
index 0000000000..1f110313da
--- /dev/null
+++ b/zephyr/dts/bindings/cros_flash/cros-ec,cros-flash.yaml
@@ -0,0 +1,8 @@
+# Copyright 2023 Google LLC
+# SPDX-License-Identifier: Apache-2.0
+
+description: Generic cros-flash node
+
+compatible: "cros-ec,cros-flash"
+
+include: cros-flash-controller.yaml
diff --git a/zephyr/dts/bindings/cros_flash/cros-ec,flash-layout.yaml b/zephyr/dts/bindings/cros_flash/cros-ec,flash-layout.yaml
new file mode 100644
index 0000000000..ea2b1e4727
--- /dev/null
+++ b/zephyr/dts/bindings/cros_flash/cros-ec,flash-layout.yaml
@@ -0,0 +1,50 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Describes the size and offset of the RO and RW regions
+
+compatible: "cros-ec,flash-layout"
+
+include: base.yaml
+
+properties:
+  type:
+    type: string
+    required: true
+    description: >-
+      A property required by the binman utility, defined here only to
+      prevent Zephyr's binding generator from erroring about
+      additional properties.
+
+      The property should be set to the value "section" (done by
+      binman.dtsi) and should not be used anywhere in C code.
+
+      See README.entries in binman for a description of what binman
+      uses this for.
+  offset:
+    type: int
+    required: true
+    description: >-
+      The offset of the flash region from the base of the flash.
+  size:
+    type: int
+    required: true
+    description: >-
+      The size of the flash region, in bytes.
+  read-only:
+    type: boolean
+    required: false
+    description: >-
+      Set if the section should be read-only.
+  preserve:
+    type: boolean
+    required: false
+    description: >-
+      Set if the section should be preserved when updating firmware. This is
+      just a signal. Enforcement of this is upto the updater.
+  fill-byte:
+    type: uint8-array
+    required: false
+    description: >-
+      Set if the section bytes should be filled with configured byte value.
diff --git a/zephyr/dts/bindings/cros_flash/cros-flash-controller.yaml b/zephyr/dts/bindings/cros_flash/cros-flash-controller.yaml
new file mode 100644
index 0000000000..9469a02004
--- /dev/null
+++ b/zephyr/dts/bindings/cros_flash/cros-flash-controller.yaml
@@ -0,0 +1,8 @@
+# Copyright 2020 Google LLC
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for Chrome OS flash devices
+
+include: base.yaml
+
+bus: crosflash
diff --git a/zephyr/dts/bindings/cros_flash/microchip,xec-cros-flash.yaml b/zephyr/dts/bindings/cros_flash/microchip,xec-cros-flash.yaml
new file mode 100644
index 0000000000..a5c1155b9e
--- /dev/null
+++ b/zephyr/dts/bindings/cros_flash/microchip,xec-cros-flash.yaml
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Microchip, XEC-cros-flash node
+
+compatible: "microchip,xec-cros-flash"
+
+include: cros-flash-controller.yaml
diff --git a/zephyr/dts/bindings/cros_flash/nuvoton,npcx-cros-flash.yaml b/zephyr/dts/bindings/cros_flash/nuvoton,npcx-cros-flash.yaml
new file mode 100644
index 0000000000..f67bf1fe5c
--- /dev/null
+++ b/zephyr/dts/bindings/cros_flash/nuvoton,npcx-cros-flash.yaml
@@ -0,0 +1,8 @@
+# Copyright 2020 Google LLC
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nuvoton, NPCX-cros-flash node
+
+compatible: "nuvoton,npcx-cros-flash"
+
+include: cros-flash-controller.yaml
diff --git a/zephyr/dts/bindings/cros_kb_raw/ite,it8xxx2-cros-kb-raw.yaml b/zephyr/dts/bindings/cros_kb_raw/ite,it8xxx2-cros-kb-raw.yaml
new file mode 100644
index 0000000000..134a036dbd
--- /dev/null
+++ b/zephyr/dts/bindings/cros_kb_raw/ite,it8xxx2-cros-kb-raw.yaml
@@ -0,0 +1,30 @@
+# Copyright 2022 Google LLC
+# SPDX-License-Identifier: Apache-2.0
+
+description: ITE, it8xxx2-cros-kb-raw node
+
+compatible: "ite,it8xxx2-cros-kb-raw"
+
+include: [base.yaml, pinctrl-device.yaml]
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  wucctrl:
+    type: phandles
+    description: |
+      Configure wakeup controller, this controller is used to set that
+      when the interrupt is triggered in EC low power mode, it can wakeup
+      EC or not. Via this controller, we set the wakeup trigger edge,
+      enable, disable, and clear wakeup status for the specific pin which
+      may be gpio pins or alternate pins.
+
+  pinctrl-0:
+    required: true
+
+  pinctrl-names:
+    required: true
diff --git a/zephyr/dts/bindings/cros_kb_raw/microchip,xec-cros-kb-raw.yaml b/zephyr/dts/bindings/cros_kb_raw/microchip,xec-cros-kb-raw.yaml
new file mode 100644
index 0000000000..d20f905e7f
--- /dev/null
+++ b/zephyr/dts/bindings/cros_kb_raw/microchip,xec-cros-kb-raw.yaml
@@ -0,0 +1,19 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Microchip, xec-cros-kb-raw node
+
+compatible: "microchip,xec-cros-kb-raw"
+
+include: [base.yaml, pinctrl-device.yaml]
+
+properties:
+  reg:
+    required: true
+
+  pinctrl-0:
+    required: true
+
+  pinctrl-names:
+    required: true
diff --git a/zephyr/dts/bindings/cros_kb_raw/nuvoton,npcx-cros-kb-raw.yaml b/zephyr/dts/bindings/cros_kb_raw/nuvoton,npcx-cros-kb-raw.yaml
new file mode 100644
index 0000000000..0b4f6ed9b2
--- /dev/null
+++ b/zephyr/dts/bindings/cros_kb_raw/nuvoton,npcx-cros-kb-raw.yaml
@@ -0,0 +1,33 @@
+# Copyright 2020 Google LLC
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nuvoton, NPCX-cros-kb-raw node
+
+compatible: "nuvoton,npcx-cros-kb-raw"
+
+include: [base.yaml, pinctrl-device.yaml]
+
+properties:
+  reg:
+    required: true
+
+  clocks:
+    required: true
+
+  pinctrl-0:
+    required: true
+
+  pinctrl-names:
+    required: true
+
+  wui_maps:
+    type: phandles
+    required: true
+    description: |
+        Mapping table between Wake-Up Input (WUI) and 8 IOs belong to this device.
+        Please notice not all IOs connect to WUIs.
+
+        In this case, it will be presented by wui_none.
+        For example the WUI mapping on NPCX7 KSI pads would be
+           wui_maps = <&wui_io30 &wui_io31 &wui_io27 &wui_io26
+                       &wui_io25 &wui_io24 &wui_io23 &wui_io22>;
diff --git a/zephyr/dts/bindings/cros_mkbp_event/cros-ec,mkbp-event-wakeup-mask.yaml b/zephyr/dts/bindings/cros_mkbp_event/cros-ec,mkbp-event-wakeup-mask.yaml
new file mode 100644
index 0000000000..b1877ffa4c
--- /dev/null
+++ b/zephyr/dts/bindings/cros_mkbp_event/cros-ec,mkbp-event-wakeup-mask.yaml
@@ -0,0 +1,9 @@
+# Copyright 2022 Google LLC
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: EC MKBP event wakeup node
+
+compatible: "cros-ec,mkbp-event-wakeup-mask"
+
+include: ["ec-event-wakeup-mask-base.yaml"]
diff --git a/zephyr/dts/bindings/cros_mkbp_event/cros-ec,mkbp-host-event-wakeup-mask.yaml b/zephyr/dts/bindings/cros_mkbp_event/cros-ec,mkbp-host-event-wakeup-mask.yaml
new file mode 100644
index 0000000000..6f18936ad3
--- /dev/null
+++ b/zephyr/dts/bindings/cros_mkbp_event/cros-ec,mkbp-host-event-wakeup-mask.yaml
@@ -0,0 +1,9 @@
+# Copyright 2022 Google LLC
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: EC MKBP host event wakeup node
+
+compatible: "cros-ec,mkbp-host-event-wakeup-mask"
+
+include: ["ec-event-wakeup-mask-base.yaml"]
diff --git a/zephyr/dts/bindings/cros_mkbp_event/ec-event-wakeup-mask-base.yaml b/zephyr/dts/bindings/cros_mkbp_event/ec-event-wakeup-mask-base.yaml
new file mode 100644
index 0000000000..e1a00fe4e3
--- /dev/null
+++ b/zephyr/dts/bindings/cros_mkbp_event/ec-event-wakeup-mask-base.yaml
@@ -0,0 +1,27 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Common fields for EC MKBP event nodes
+
+properties:
+  wakeup-mask:
+    required: false
+    type: int
+    default: 0
+    description:
+      Define the MKBP or host events that will wake up the application
+      processor from suspend mode.
+      e.g.
+      ec-mkbp-host-event-wakeup-mask {
+        compatible = "cros-ec,mkbp-host-event-wakeup-mask";
+        wakeup-mask = <(
+          HOST_EVENT_LID_OPEN |
+          HOST_EVENT_POWER_BUTTON |
+          HOST_EVENT_AC_CONNECTED |
+          HOST_EVENT_AC_DISCONNECTED |
+          HOST_EVENT_HANG_DETECT |
+          HOST_EVENT_RTC |
+          HOST_EVENT_MODE_CHANGE |
+          HOST_EVENT_DEVICE)>;
+      };
diff --git a/zephyr/dts/bindings/cros_pwr_signal/mediatek,mt8186-power-signal-list.yaml b/zephyr/dts/bindings/cros_pwr_signal/mediatek,mt8186-power-signal-list.yaml
new file mode 100644
index 0000000000..5f0e75f717
--- /dev/null
+++ b/zephyr/dts/bindings/cros_pwr_signal/mediatek,mt8186-power-signal-list.yaml
@@ -0,0 +1,20 @@
+# Copyright 2021 Google LLC
+# SPDX-License-Identifier: Apache-2.0
+
+description: MediaTek MT8186, Power Signal List
+compatible: "mediatek,mt8186-power-signal-list"
+
+include: power-signal-list.yaml
+
+properties:
+  power-signals-required:
+    default: 4
+
+child-binding:
+  properties:
+    power-enum-name:
+      enum:
+        - AP_IN_RST
+        - AP_IN_S3
+        - AP_WDT_ASSERTED
+        - AP_WARM_RST_REQ
diff --git a/zephyr/dts/bindings/cros_pwr_signal/mediatek,mt8188-power-signal-list.yaml b/zephyr/dts/bindings/cros_pwr_signal/mediatek,mt8188-power-signal-list.yaml
new file mode 100644
index 0000000000..7c0d0fcff1
--- /dev/null
+++ b/zephyr/dts/bindings/cros_pwr_signal/mediatek,mt8188-power-signal-list.yaml
@@ -0,0 +1,22 @@
+# Copyright 2023 Google LLC
+# SPDX-License-Identifier: Apache-2.0
+
+description: MediaTek MT8188, Power Signal List
+compatible: "mediatek,mt8188-power-signal-list"
+
+include: power-signal-list.yaml
+
+properties:
+  power-signals-required:
+    default: 6
+
+child-binding:
+  properties:
+    power-enum-name:
+      enum:
+        - AP_IN_RST
+        - AP_IN_S3
+        - AP_WDT_ASSERTED
+        - AP_WARM_RST_REQ
+        - PG_PP4200_S5
+        - PMIC_AP_RST
diff --git a/zephyr/dts/bindings/cros_pwr_signal/mediatek,mt8192-power-signal-list.yaml b/zephyr/dts/bindings/cros_pwr_signal/mediatek,mt8192-power-signal-list.yaml
new file mode 100644
index 0000000000..8bbd1207eb
--- /dev/null
+++ b/zephyr/dts/bindings/cros_pwr_signal/mediatek,mt8192-power-signal-list.yaml
@@ -0,0 +1,19 @@
+# Copyright 2021 Google LLC
+# SPDX-License-Identifier: Apache-2.0
+
+description: MediaTek, Power Signal List
+compatible: "mediatek,mt8192-power-signal-list"
+
+include: power-signal-list.yaml
+
+properties:
+  power-signals-required:
+    default: 3
+
+child-binding:
+  properties:
+    power-enum-name:
+      enum:
+        - AP_IN_S3_L
+        - AP_WDT_ASSERTED
+        - PMIC_PWR_GOOD
diff --git a/zephyr/dts/bindings/cros_pwr_signal/power-signal-list.yaml b/zephyr/dts/bindings/cros_pwr_signal/power-signal-list.yaml
new file mode 100644
index 0000000000..89ad4f5d5e
--- /dev/null
+++ b/zephyr/dts/bindings/cros_pwr_signal/power-signal-list.yaml
@@ -0,0 +1,24 @@
+# Copyright 2021 Google LLC
+# SPDX-License-Identifier: Apache-2.0
+
+description: Power Signal List
+
+properties:
+  power-signals-required:
+    description:
+      Number of power-signal children there should be for the current AP
+    type: int
+
+child-binding:
+  description: Power Signal List child node
+  properties:
+    power-gpio-pin:
+      description:
+        PHandle to the associated GPIO
+      type: phandle
+      required: true
+    power-enum-name:
+      description:
+        Enumeration values for power-signal-list
+      type: string
+      required: true
diff --git a/zephyr/dts/bindings/cros_rtc/microchip,xec-cros-rtc.yaml b/zephyr/dts/bindings/cros_rtc/microchip,xec-cros-rtc.yaml
new file mode 100644
index 0000000000..0b61e6e0b9
--- /dev/null
+++ b/zephyr/dts/bindings/cros_rtc/microchip,xec-cros-rtc.yaml
@@ -0,0 +1,13 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Microchip, XEC Real time clock (RTC) node
+
+compatible: "microchip,xec-cros-rtc"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
diff --git a/zephyr/dts/bindings/cros_rtc/nuvoton,npcx-cros-mtc.yaml b/zephyr/dts/bindings/cros_rtc/nuvoton,npcx-cros-mtc.yaml
new file mode 100644
index 0000000000..b1e7e83f73
--- /dev/null
+++ b/zephyr/dts/bindings/cros_rtc/nuvoton,npcx-cros-mtc.yaml
@@ -0,0 +1,22 @@
+# Copyright 2021 Google LLC
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nuvoton, NPCX Monotonic Counter (MTC) node
+
+compatible: "nuvoton,npcx-cros-mtc"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
+
+  mtc-alarm:
+    type: phandle
+    required: true
+    description: |
+      Mapping table between Wake-Up Input (WUI) and monotonic counter alarm
+      signal.
+
+      For example, the WUI mapping on NPCX7 monotonic counter alarm would be
+         mtc-alarm = <&wui_mtc>;
diff --git a/zephyr/dts/bindings/cros_rtc/nxp,rtc-pcf85063a.yaml b/zephyr/dts/bindings/cros_rtc/nxp,rtc-pcf85063a.yaml
new file mode 100644
index 0000000000..60cc645f81
--- /dev/null
+++ b/zephyr/dts/bindings/cros_rtc/nxp,rtc-pcf85063a.yaml
@@ -0,0 +1,14 @@
+# Copyright 2021 Google LLC
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP, Real-Time Clock
+
+compatible: "nxp,rtc-pcf85063a"
+
+include: [base.yaml, i2c-device.yaml]
+
+properties:
+  int-pin:
+    type: phandle
+    required: true
+    description: Interrupt from RTC
diff --git a/zephyr/dts/bindings/cros_rtc/renesas,rtc-idt1337ag.yaml b/zephyr/dts/bindings/cros_rtc/renesas,rtc-idt1337ag.yaml
new file mode 100644
index 0000000000..96a549c05a
--- /dev/null
+++ b/zephyr/dts/bindings/cros_rtc/renesas,rtc-idt1337ag.yaml
@@ -0,0 +1,14 @@
+# Copyright 2021 Google LLC
+# SPDX-License-Identifier: Apache-2.0
+
+description: RENESAS, Real-Time Clock
+
+compatible: "renesas,rtc-idt1337ag"
+
+include: [base.yaml, i2c-device.yaml]
+
+properties:
+  int-pin:
+    type: phandle
+    required: true
+    description: Interrupt from RTC
diff --git a/zephyr/dts/bindings/emul/cros,anx7447-tcpc-emul.yaml b/zephyr/dts/bindings/emul/cros,anx7447-tcpc-emul.yaml
new file mode 100644
index 0000000000..a4b41a0cec
--- /dev/null
+++ b/zephyr/dts/bindings/emul/cros,anx7447-tcpc-emul.yaml
@@ -0,0 +1,16 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+description: Zephyr ANX7447 emulator
+
+compatible: "cros,anx7447-tcpc-emul"
+
+include: i2c-device.yaml
+
+properties:
+  tcpc-flags:
+    type: int
+    default: 0
+    description: |
+      TCPC configuration flags
diff --git a/zephyr/dts/bindings/emul/cros,anx7483-emul.yaml b/zephyr/dts/bindings/emul/cros,anx7483-emul.yaml
new file mode 100644
index 0000000000..5c00e0b8fe
--- /dev/null
+++ b/zephyr/dts/bindings/emul/cros,anx7483-emul.yaml
@@ -0,0 +1,9 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Zephyr ANX7483 emulator
+
+compatible: "cros,anx7483-emul"
+
+include: ["base.yaml", "cros-ec,usbc-mux.yaml"]
diff --git a/zephyr/dts/bindings/emul/cros,bma4xx-emul.yaml b/zephyr/dts/bindings/emul/cros,bma4xx-emul.yaml
new file mode 100644
index 0000000000..fada419c5f
--- /dev/null
+++ b/zephyr/dts/bindings/emul/cros,bma4xx-emul.yaml
@@ -0,0 +1,19 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Emulator for the BMA4xx family of accelerometers.
+
+compatible: "cros,bma4xx-emul"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
+  motionsense-sensor:
+    required: true
+    type: phandle
+    description: |
+      Reference to the /motionsense-sensor node representing the sensor
+      associated with this emulator.
diff --git a/zephyr/dts/bindings/emul/cros,clock-control-emul.yaml b/zephyr/dts/bindings/emul/cros,clock-control-emul.yaml
new file mode 100644
index 0000000000..04e6f611af
--- /dev/null
+++ b/zephyr/dts/bindings/emul/cros,clock-control-emul.yaml
@@ -0,0 +1,15 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Emulated clock
+
+compatible: "cros,clock-control-emul"
+
+include: base.yaml
+properties:
+  clock-frequency:
+    type: int
+    required: true
+    description: |
+      Default frequency in Hz for the output clock.
diff --git a/zephyr/dts/bindings/emul/cros,i2c-mock.yaml b/zephyr/dts/bindings/emul/cros,i2c-mock.yaml
new file mode 100644
index 0000000000..2ba03571ce
--- /dev/null
+++ b/zephyr/dts/bindings/emul/cros,i2c-mock.yaml
@@ -0,0 +1,13 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: A generic I2C mock
+
+compatible: "cros,i2c-mock"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
diff --git a/zephyr/dts/bindings/emul/cros,isl923x-emul.yaml b/zephyr/dts/bindings/emul/cros,isl923x-emul.yaml
new file mode 100644
index 0000000000..ca326d78bb
--- /dev/null
+++ b/zephyr/dts/bindings/emul/cros,isl923x-emul.yaml
@@ -0,0 +1,18 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: ISL923X Charger emulator
+
+compatible: "cros,isl923x-emul"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
+  battery:
+    type: phandle
+    required: false
+    description:
+      Reference to battery emulator.
diff --git a/zephyr/dts/bindings/emul/cros,lis2dw12-emul.yaml b/zephyr/dts/bindings/emul/cros,lis2dw12-emul.yaml
new file mode 100644
index 0000000000..f0a8632c18
--- /dev/null
+++ b/zephyr/dts/bindings/emul/cros,lis2dw12-emul.yaml
@@ -0,0 +1,13 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: CROS implementation of the LIS2DW12 emulator
+
+compatible: "cros,lis2dw12-emul"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
diff --git a/zephyr/dts/bindings/emul/cros,ln9310-emul.yaml b/zephyr/dts/bindings/emul/cros,ln9310-emul.yaml
new file mode 100644
index 0000000000..7f086cd5f2
--- /dev/null
+++ b/zephyr/dts/bindings/emul/cros,ln9310-emul.yaml
@@ -0,0 +1,18 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Cros LN9310 Emulator
+
+compatible: "cros,ln9310-emul"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
+  pg-int-pin:
+    type: phandle
+    description:
+      GPIO that receives interrupt signal from this device.
+    required: true
diff --git a/zephyr/dts/bindings/emul/cros,ps8811-emul.yaml b/zephyr/dts/bindings/emul/cros,ps8811-emul.yaml
new file mode 100644
index 0000000000..1c46f0bfd2
--- /dev/null
+++ b/zephyr/dts/bindings/emul/cros,ps8811-emul.yaml
@@ -0,0 +1,9 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Zephyr PS8811 emulator
+
+compatible: "cros,ps8811-emul"
+
+include: base.yaml
diff --git a/zephyr/dts/bindings/emul/cros,ps8xxx-emul.yaml b/zephyr/dts/bindings/emul/cros,ps8xxx-emul.yaml
new file mode 100644
index 0000000000..6de2d3864d
--- /dev/null
+++ b/zephyr/dts/bindings/emul/cros,ps8xxx-emul.yaml
@@ -0,0 +1,32 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Zephyr PS8xxx emulator
+
+compatible: "cros,ps8xxx-emul"
+
+include: tcpci.yaml
+
+properties:
+  p0-i2c-addr:
+    type: int
+    required: true
+    description:
+      First hidden I2C address (PS8xxx emulator will register device with
+      that address)
+
+  p1-i2c-addr:
+    type: int
+    required: true
+    description:
+      Second hidden I2C address (PS8xxx emulator will register device with
+      that address)
+
+  gpio-i2c-addr:
+    type: int
+    required: false
+    default: 0
+    description:
+      GPIO I2C address. When set to zero GPIO I2C device is not registered
+      by PS8xxx emulator.
diff --git a/zephyr/dts/bindings/emul/cros,pwm-mock.yaml b/zephyr/dts/bindings/emul/cros,pwm-mock.yaml
new file mode 100644
index 0000000000..2c706b2909
--- /dev/null
+++ b/zephyr/dts/bindings/emul/cros,pwm-mock.yaml
@@ -0,0 +1,15 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: A generic PWM mock
+compatible: "cros,pwm-mock"
+include: [pwm-controller.yaml, base.yaml]
+properties:
+  reg:
+    required: true
+
+pwm-cells:
+  - channel
+  - period
+  - flags
diff --git a/zephyr/dts/bindings/emul/cros,rt1718s-tcpc-emul.yaml b/zephyr/dts/bindings/emul/cros,rt1718s-tcpc-emul.yaml
new file mode 100644
index 0000000000..a8276cc159
--- /dev/null
+++ b/zephyr/dts/bindings/emul/cros,rt1718s-tcpc-emul.yaml
@@ -0,0 +1,21 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Zephyr RT1718S Emulator
+
+compatible: "cros,rt1718s-tcpc-emul"
+
+include: i2c-device.yaml
+
+properties:
+  tcpc-flags:
+    type: int
+    default: 0
+    description: |
+      TCPC configuration flags
+  irq-gpios:
+    type: phandle-array
+    required: false
+    description: |
+      Interrupt from TCPC
diff --git a/zephyr/dts/bindings/emul/cros,sm5803-emul.yaml b/zephyr/dts/bindings/emul/cros,sm5803-emul.yaml
new file mode 100644
index 0000000000..a3e42682e6
--- /dev/null
+++ b/zephyr/dts/bindings/emul/cros,sm5803-emul.yaml
@@ -0,0 +1,34 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: SM5803 charger emulator
+
+compatible: "cros,sm5803-emul"
+
+include: base.yaml
+
+properties:
+  main-addr:
+    type: int
+    default: 0x30
+    description: |
+      I2C address of the charger base registers. This is always 0x30 on
+      hardware.
+  meas-addr:
+    type: int
+    default: 0x31
+    description: |
+      I2C address of the charger measurement registers. This is always 0x31 on
+      hardware.
+  test-addr:
+    type: int
+    default: 0x37
+    description: |
+      I2C address of the charger test registers. This is always 0x37 on
+      hardware.
+  interrupt-gpios:
+    type: phandle-array
+    description: |
+      Emulated GPIO pin acting as the active-low interrupt input from the
+      charger.
diff --git a/zephyr/dts/bindings/emul/cros,sn5s330-emul.yaml b/zephyr/dts/bindings/emul/cros,sn5s330-emul.yaml
new file mode 100644
index 0000000000..c8ad8bd943
--- /dev/null
+++ b/zephyr/dts/bindings/emul/cros,sn5s330-emul.yaml
@@ -0,0 +1,16 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: sn5s330 emulator
+
+compatible: "cros,sn5s330-emul"
+
+include: base.yaml
+properties:
+  reg:
+    required: true
+  int-pin:
+    type: phandle
+    description: The GPIO that receives an interrupt signal from this device
+    required: true
diff --git a/zephyr/dts/bindings/emul/cros,tcpci-generic-emul.yaml b/zephyr/dts/bindings/emul/cros,tcpci-generic-emul.yaml
new file mode 100644
index 0000000000..73d115f5ed
--- /dev/null
+++ b/zephyr/dts/bindings/emul/cros,tcpci-generic-emul.yaml
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Zephyr TCPCI Generic Emulator
+
+compatible: "cros,tcpci-generic-emul"
+
+include: tcpci.yaml
diff --git a/zephyr/dts/bindings/emul/cros,vcmp-mock.yaml b/zephyr/dts/bindings/emul/cros,vcmp-mock.yaml
new file mode 100644
index 0000000000..1a3f14c875
--- /dev/null
+++ b/zephyr/dts/bindings/emul/cros,vcmp-mock.yaml
@@ -0,0 +1,17 @@
+# Copyright Google LLC
+# SPDX-License-Identifier: Apache-2.0
+
+description: Generic voltage comparator device mock implementation
+
+compatible: "cros,vcmp-mock"
+
+include: sensor-device.yaml
+
+properties:
+  io-channels:
+    type: phandle-array
+    required: true
+
+  threshold-mv:
+    type: int
+    required: true
diff --git a/zephyr/dts/bindings/emul/cros-ec,flash-emul.yaml b/zephyr/dts/bindings/emul/cros-ec,flash-emul.yaml
new file mode 100644
index 0000000000..c6a20f9991
--- /dev/null
+++ b/zephyr/dts/bindings/emul/cros-ec,flash-emul.yaml
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Emulator for Chromiumos EC flash driver.
+
+compatible: "cros-ec,flash-emul"
+
+include: cros-flash-controller.yaml
diff --git a/zephyr/dts/bindings/emul/cros-ec,kb-raw-emul.yaml b/zephyr/dts/bindings/emul/cros-ec,kb-raw-emul.yaml
new file mode 100644
index 0000000000..f6821dbc2b
--- /dev/null
+++ b/zephyr/dts/bindings/emul/cros-ec,kb-raw-emul.yaml
@@ -0,0 +1,21 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Emulator for Chromiumos EC raw keyboard driver.
+
+compatible: "cros-ec,kb-raw-emul"
+
+include: base.yaml
+
+properties:
+  rows:
+    required: false
+    type: int
+    default: 8
+    description: Number of keyboard scan rows
+  cols:
+    required: false
+    type: int
+    default: 18
+    description: Number of keyboard scan columns
diff --git a/zephyr/dts/bindings/emul/cros-ec,rtc-emul.yaml b/zephyr/dts/bindings/emul/cros-ec,rtc-emul.yaml
new file mode 100644
index 0000000000..35e7b7f677
--- /dev/null
+++ b/zephyr/dts/bindings/emul/cros-ec,rtc-emul.yaml
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Emulator for Chromiumos EC real-time-clock (RTC).
+
+compatible: "cros-ec,rtc-emul"
+
+include: base.yaml
diff --git a/zephyr/dts/bindings/emul/tcpci.yaml b/zephyr/dts/bindings/emul/tcpci.yaml
new file mode 100644
index 0000000000..937aa51489
--- /dev/null
+++ b/zephyr/dts/bindings/emul/tcpci.yaml
@@ -0,0 +1,26 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Common TCPCI properties
+
+include: base.yaml
+
+properties:
+  irq-gpios:
+    type: phandle-array
+    required: false
+    description: |
+      Interrupt from TCPC using shim driver
+
+  rst-gpios:
+    type: phandle-array
+    required: false
+    description: |
+      TCPC reset line using shim driver
+
+  int-pin:
+    type: phandles
+    required: false
+    description: |
+      Interrupt from TCPC using gpio-int
diff --git a/zephyr/dts/bindings/emul/zephyr,bma255-emul.yaml b/zephyr/dts/bindings/emul/zephyr,bma255-emul.yaml
new file mode 100644
index 0000000000..b2bba58779
--- /dev/null
+++ b/zephyr/dts/bindings/emul/zephyr,bma255-emul.yaml
@@ -0,0 +1,83 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Zephyr BMA255 Emulator
+
+compatible: "zephyr,bma255-emul"
+
+include: base.yaml
+
+properties:
+  nvm-off-x:
+    type: int
+    required: false
+    default: 0
+    description: Accelerometer offset of x axis stored in NVM.
+
+  nvm-off-y:
+    type: int
+    required: false
+    default: 0
+    description: Accelerometer offset of y axis stored in NVM.
+
+  nvm-off-z:
+    type: int
+    required: false
+    default: 0
+    description: Accelerometer offset of z axis stored in NVM.
+
+  nvm-gp0:
+    type: int
+    required: false
+    default: 0
+    description: GP0 value stored in NVM.
+
+  nvm-gp1:
+    type: int
+    required: false
+    default: 0
+    description: GP1 value stored in NVM.
+
+  nvm-acc-x:
+    type: int
+    required: false
+    default: 0
+    description: Accelerometer value of x axis used until new value is set.
+
+  nvm-acc-y:
+    type: int
+    required: false
+    default: 0
+    description: Accelerometer value of y axis used until new value is set.
+
+  nvm-acc-z:
+    type: int
+    required: false
+    default: 0
+    description: Accelerometer value of z axis used until new value is set.
+
+  error-on-compensation-not-ready:
+    type: boolean
+    description:
+      Flag indicating if error should be generated when fast compensation
+      is started when not ready bit is set.
+
+  error-on-ro-write:
+    type: boolean
+    description:
+      Flag indicating if error should be generated when read only register
+      is being written.
+
+  error-on-reserved-bit-write:
+    type: boolean
+    description:
+      Flag indicating if error should be generated when reserved bit
+      is being written.
+
+  error-on-msb-first-access:
+    type: boolean
+    description:
+      Flag indicating if error should be generated when MSB register of
+      accelerometer value is accessed before LSB and shadowing is enabled
+      at the same time.
diff --git a/zephyr/dts/bindings/emul/zephyr,bmi-emul.yaml b/zephyr/dts/bindings/emul/zephyr,bmi-emul.yaml
new file mode 100644
index 0000000000..1e66166257
--- /dev/null
+++ b/zephyr/dts/bindings/emul/zephyr,bmi-emul.yaml
@@ -0,0 +1,42 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Zephyr BMI Emulator
+
+compatible: "zephyr,bmi-emul"
+
+include: base.yaml
+
+properties:
+  device-model:
+    type: string
+    required: true
+    enum:
+      - BMI_EMUL_160
+      - BMI_EMUL_260
+    description: Model of device that is emulated.
+
+  error-on-ro-write:
+    type: boolean
+    description:
+      Flag indicating if error should be generated when read only register
+      is being written.
+
+  error-on-wo-read:
+    type: boolean
+    description:
+      Flag indicating if error should be generated when write only register
+      is being read.
+
+  error-on-reserved-bit-write:
+    type: boolean
+    description:
+      Flag indicating if error should be generated when reserved bit
+      is being written.
+
+  simulate-command-exec-time:
+    type: boolean
+    description:
+      Flag indicating if emulator should wait the same amount of time before
+      finishing command as real device would.
diff --git a/zephyr/dts/bindings/emul/zephyr,icm42607-emul.yaml b/zephyr/dts/bindings/emul/zephyr,icm42607-emul.yaml
new file mode 100644
index 0000000000..c3bffa33c8
--- /dev/null
+++ b/zephyr/dts/bindings/emul/zephyr,icm42607-emul.yaml
@@ -0,0 +1,9 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Zephyr ICM42607 Emulator
+
+compatible: "zephyr,icm42607-emul"
+
+include: base.yaml
diff --git a/zephyr/dts/bindings/emul/zephyr,ps8743-emul.yaml b/zephyr/dts/bindings/emul/zephyr,ps8743-emul.yaml
new file mode 100644
index 0000000000..80ba56896e
--- /dev/null
+++ b/zephyr/dts/bindings/emul/zephyr,ps8743-emul.yaml
@@ -0,0 +1,9 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+description: Zephyr PS8743 Emulator
+
+compatible: "zephyr,ps8743-emul"
+
+include: "parade,ps8743.yaml"
diff --git a/zephyr/dts/bindings/emul/zephyr,rt9490-emul.yaml b/zephyr/dts/bindings/emul/zephyr,rt9490-emul.yaml
new file mode 100644
index 0000000000..0fbe71f228
--- /dev/null
+++ b/zephyr/dts/bindings/emul/zephyr,rt9490-emul.yaml
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Zephyr rt9490 Emulator
+
+compatible: "zephyr,rt9490-emul"
+
+include: base.yaml
diff --git a/zephyr/dts/bindings/emul/zephyr,smart-battery-emul.yaml b/zephyr/dts/bindings/emul/zephyr,smart-battery-emul.yaml
new file mode 100644
index 0000000000..c1e4686b8c
--- /dev/null
+++ b/zephyr/dts/bindings/emul/zephyr,smart-battery-emul.yaml
@@ -0,0 +1,161 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Zephyr Smart Battery Emulator
+
+compatible: "zephyr,smart-battery-emul"
+
+include: base.yaml
+
+properties:
+  mf-access:
+    type: int
+    required: false
+    default: 0
+    description: Word returned on manufacturer access command.
+
+  at-rate-full-mw-support:
+    type: boolean
+    description:
+      Flag indicating if AT_RATE_TIME_TO_FULL command supports mW capacity
+      mode.
+
+  version:
+    type: string
+    required: false
+    enum:
+      - BATTERY_SPEC_VER_1_0
+      - BATTERY_SPEC_VER_1_1
+      - BATTERY_SPEC_VER_1_1_WITH_PEC
+    default: BATTERY_SPEC_VER_1_1_WITH_PEC
+    description: Version of Smart Battery.
+
+  vscale:
+    type: int
+    required: false
+    default: 0
+    description: Scaling of voltage.
+
+  ipscale:
+    type: int
+    required: false
+    default: 0
+    description: Scaling of current.
+
+  int-charge-controller:
+    type: boolean
+    description: Flag indicating if internal charge controller is supported.
+
+  primary-battery:
+    type: boolean
+    description:
+      Flag indicating if primary battery role selection is supported.
+
+  design-mv:
+    type: int
+    required: false
+    default: 5000
+    description: Design battery voltage in mV.
+
+  design-cap:
+    type: int
+    required: false
+    default: 5000
+    description: Design battery capacity in mAh.
+
+  temperature:
+    type: int
+    required: false
+    default: 2930
+    description: Battery temperature in 0.1 Kelvins.
+
+  volt:
+    type: int
+    required: false
+    default: 5000
+    description: Battery voltage in mV.
+
+  cur:
+    type: int
+    required: false
+    default: 1000
+    description: Current charging (> 0) or discharging (< 0) battery in mA.
+
+  avg-cur:
+    type: int
+    required: false
+    default: 1000
+    description: Average current from 1 minute.
+
+  max-error:
+    type: int
+    required: false
+    default: 0
+    description: Maximum error of commands return value in percent.
+
+  cap:
+    type: int
+    required: false
+    default: 2000
+    description: Capacity of the battery in mAh.
+
+  full-cap:
+    type: int
+    required: false
+    default: 4000
+    description: Full capacity of the battery in mAh.
+
+  desired-charg-cur:
+    type: int
+    required: false
+    default: 2000
+    description: Charging current requested by battery.
+
+  desired-charg-volt:
+    type: int
+    required: false
+    default: 7000
+    description: Charging voltage requested by battery.
+
+  cycle-count:
+    type: int
+    required: false
+    default: 125
+    description: Number of cycles.
+
+  serial-number:
+    type: int
+    required: false
+    default: 7
+    description: Serial number of battery.
+
+  mf-name:
+    type: string
+    required: false
+    default: "zephyr"
+    description: Manufacturer name. Length has to be smaller than 32 bytes.
+
+  dev-name:
+    type: string
+    required: false
+    default: "smartbat"
+    description: Device name. Length has to be smaller than 32 bytes.
+
+  dev-chem:
+    type: string
+    required: false
+    default: "LION"
+    description: Device chemistry. Length has to be smaller than 32 bytes.
+
+  mf-data:
+    type: string
+    required: false
+    default: "LION"
+    description: Manufacturer data. Length has to be smaller than 32 bytes.
+
+  mf-info:
+    type: string
+    required: false
+    default: "LION"
+    description: Manufacturer info. Length has to be smaller than 32 bytes.
diff --git a/zephyr/dts/bindings/emul/zephyr,syv682x-emul.yaml b/zephyr/dts/bindings/emul/zephyr,syv682x-emul.yaml
new file mode 100644
index 0000000000..2ad9241f96
--- /dev/null
+++ b/zephyr/dts/bindings/emul/zephyr,syv682x-emul.yaml
@@ -0,0 +1,19 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Zephyr SYV682X Emulator
+
+compatible: "zephyr,syv682x-emul"
+
+include: base.yaml
+
+properties:
+  frs_en_gpio:
+    type: phandle
+    description: The GPIO that controls FRS enable on this device
+    required: true
+  alert_gpio:
+    type: phandle
+    description: The GPIO that receives the alert signal from this device
+    required: true
diff --git a/zephyr/dts/bindings/emul/zephyr,tcs3400-emul.yaml b/zephyr/dts/bindings/emul/zephyr,tcs3400-emul.yaml
new file mode 100644
index 0000000000..cbfb8fa9c3
--- /dev/null
+++ b/zephyr/dts/bindings/emul/zephyr,tcs3400-emul.yaml
@@ -0,0 +1,44 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Zephyr ALS TCS3400 light sensor i2c emulator
+
+compatible: "zephyr,tcs3400-emul"
+
+include: base.yaml
+
+properties:
+  device-id:
+    type: string
+    required: false
+    enum:
+      - TCS340015_DEVICE_ID
+      - TCS340037_DEVICE_ID
+    default: TCS340015_DEVICE_ID
+    description: Device ID that is set in the register.
+
+  revision:
+    type: int
+    required: false
+    default: 0
+    description: Wafer die revision level that is set in the register.
+
+  error-on-ro-write:
+    type: boolean
+    description:
+      Flag indicating if error should be generated when read only register
+      is being written.
+
+  error-on-reserved-bit-write:
+    type: boolean
+    description:
+      Flag indicating if error should be generated when reserved bit
+      is being written.
+
+  error-on-msb-first-access:
+    type: boolean
+    description:
+      Flag indicating if error should be generated when MSB register of
+      accelerometer value is accessed before LSB and shadowing is enabled
+      at the same time.
diff --git a/zephyr/dts/bindings/emul/zephyr,tusb1064-emul.yaml b/zephyr/dts/bindings/emul/zephyr,tusb1064-emul.yaml
new file mode 100644
index 0000000000..3cab1dd5a6
--- /dev/null
+++ b/zephyr/dts/bindings/emul/zephyr,tusb1064-emul.yaml
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+description: Zephyr TUSB1064 Emulator
+
+compatible: "zephyr,tusb1064-emul"
+
+include: "ti,tusb1064.yaml"
diff --git a/zephyr/dts/bindings/fan/cros-ec,fan-steps.yaml b/zephyr/dts/bindings/fan/cros-ec,fan-steps.yaml
new file mode 100644
index 0000000000..3befe43868
--- /dev/null
+++ b/zephyr/dts/bindings/fan/cros-ec,fan-steps.yaml
@@ -0,0 +1,27 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+description: Fan steps parent node
+compatible: "cros-ec,fan-steps"
+child-binding:
+  description: Support multiple thermal sensor temperature to trigger different fans speed,
+               each step could have different rpm for each fan
+  properties:
+    temp_on:
+      required: false
+      type: array
+      description:
+        Temperatures for each sensor to trigger next fan level,
+        <sensor 0, sensor 1, sensor 2, ...> mapping to variant overlay
+    temp_off:
+      required: false
+      type: array
+      description:
+        Temperatures for each sensor to trigger previous fan level,
+        <sensor 0, sensor 1, sensor 2, ...> mapping to variant overlay
+    rpm_target:
+      required: false
+      type: array
+      description:
+        Support multiple fan speed target for each level (in RPM),
+        <fan0 rpm target, fan1 rpm target, ...>
diff --git a/zephyr/dts/bindings/fan/cros-ec,fans.yaml b/zephyr/dts/bindings/fan/cros-ec,fans.yaml
new file mode 100644
index 0000000000..a9d198e37c
--- /dev/null
+++ b/zephyr/dts/bindings/fan/cros-ec,fans.yaml
@@ -0,0 +1,63 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Fan parent node
+
+compatible: "cros-ec,fans"
+
+child-binding:
+  description: Fan's child node
+  properties:
+    rpm_min:
+      required: true
+      type: int
+      description:
+        Minimum fan speed (in RPM) to keep turning
+    rpm_start:
+      required: true
+      type: int
+      description:
+        Fan speed (in RPM) to begin turning
+    rpm_max:
+      required: true
+      type: int
+      description:
+        Maximum fan speed (in RPM)
+    rpm_deviation:
+      required: false
+      default: 7
+      type: int
+      description:
+        Percentage of fan rpm deviation
+    pwms:
+      type: phandle-array
+      required: true
+      description:
+        PWM channel to control the fan
+    tach:
+      type: phandle
+      required: false
+      description:
+        Tachometer to measure the fan speed
+    not_use_rpm_mode:
+      required: false
+      type: boolean
+      description:
+        Disable automatic RPM control using tachometer input
+    use_fast_start:
+      required: false
+      type: boolean
+      description:
+        Fan requires a higher duty cycle to start up than to keep
+        running
+    pgood_gpio:
+      required: false
+      type: phandle
+      description:
+        Active high input GPIO which signals the power is good
+    enable_gpio:
+      required: false
+      type: phandle
+      description:
+        Active high output GPIO to enable the power
diff --git a/zephyr/dts/bindings/gpio/cros,ioex-chip.yaml b/zephyr/dts/bindings/gpio/cros,ioex-chip.yaml
new file mode 100644
index 0000000000..1666f5359b
--- /dev/null
+++ b/zephyr/dts/bindings/gpio/cros,ioex-chip.yaml
@@ -0,0 +1,50 @@
+description: IEOX chip definition
+
+compatible: "cros,ioex-chip"
+
+include: [base.yaml]
+
+properties:
+  i2c-port:
+    type: phandle
+    description:
+      Handle to the i2c named-port containing the IO expander chip
+
+  i2c-addr:
+    type: int
+    required: true
+    description:
+      I2C address of chip
+
+  flags:
+    type: int
+    required: true
+    description:
+      Value which represents IOEX_FLAGS_* or other internal flags
+      for IO expander chip.
+
+  drv:
+    type: string
+    required: true
+    description:
+      CrOS EC driver used to communicate with chip
+    enum:
+      - "ccgxxf_ioexpander_drv"
+      - "it8801_ioexpander_drv"
+      - "nct38xx_ioexpander_drv"
+      - "pca9675_ioexpander_drv"
+      - "pcal6408_ioexpander_drv"
+      - "tca64xxa_ioexpander_drv"
+
+  int-gpios:
+    type: phandle-array
+    required: false
+    description:
+      GPIO connected to the interrupt output signal of IO expander chip
+
+  "#address-cells":
+    required: true
+    const: 1
+  "#size-cells":
+    required: true
+    const: 0
diff --git a/zephyr/dts/bindings/gpio/cros,ioex-port.yaml b/zephyr/dts/bindings/gpio/cros,ioex-port.yaml
new file mode 100644
index 0000000000..fbf85e4e06
--- /dev/null
+++ b/zephyr/dts/bindings/gpio/cros,ioex-port.yaml
@@ -0,0 +1,26 @@
+description: IEOX port definition
+
+compatible: "cros,ioex-port"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+  reg:
+    required: true
+    description:
+      Number of port within IO expander
+
+  "#gpio-cells":
+    required: true
+    const: 2
+    description:
+      Number of parameters describing the pin
+
+  ngpios:
+    required: true
+    description:
+      Number of pins per port
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/zephyr/dts/bindings/gpio/cros-ec,gpio-id.yaml b/zephyr/dts/bindings/gpio/cros-ec,gpio-id.yaml
new file mode 100644
index 0000000000..d8e3fe1ff2
--- /dev/null
+++ b/zephyr/dts/bindings/gpio/cros-ec,gpio-id.yaml
@@ -0,0 +1,26 @@
+description: Defines board version and sku id gpios
+
+compatible: "cros-ec,gpio-id"
+
+properties:
+  bits:
+    type: phandles
+    required: true
+    description: GPIO list to read, LSB to MSB
+
+  system:
+    type: string
+    description:
+      Numeral system used to decode values
+      - binary - expects array with values of 0 and 1.
+      - binary_first_base3 - non-standard ternary number system
+          where the first 2^n natural numbers are represented as
+          they would be in a binary system (without any Z digits)
+          and the following 3^n-2^n numbers use the remaining
+          ternary representations in the normal ternary system order
+      - ternary - expects array with values of 0, 1 and 2.
+          It treats 'Z' state as digit '2'.
+    enum:
+      - binary
+      - binary_first_base3
+      - ternary
diff --git a/zephyr/dts/bindings/gpio/cros-ec,gpio-interrupts.yaml b/zephyr/dts/bindings/gpio/cros-ec,gpio-interrupts.yaml
new file mode 100644
index 0000000000..bb6b4001f4
--- /dev/null
+++ b/zephyr/dts/bindings/gpio/cros-ec,gpio-interrupts.yaml
@@ -0,0 +1,44 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+description: |
+  GPIO interrupts list bindings.
+
+  Uses device tree to configure the interrupt handling e.g
+
+    int_wp_l: wp_l {
+      irq-pin = <&gpio_ec_wp_odl>;
+      flags = <GPIO_INT_EDGE_BOTH>;
+      handler = "wp_interrupt";
+    };
+
+  The interrupt can be enabled either using the DTS label:
+
+    gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_wp_l));
+
+  or the legacy:
+
+    gpio_enable_interrupt(GPIO_WP_L);
+
+compatible: "cros-ec,gpio-interrupts"
+
+child-binding:
+  description: GPIO Interrupt definition.
+  properties:
+    #
+    # This is named irq-pin rather than irq-gpio because
+    # anything with a name appended with "gpio" is treated specially,
+    # which causes warnings about missing #gpio-cells.
+    #
+    irq-pin:
+      type: phandle
+      required: true
+      description: The named-gpio GPIO source of the interrupt.
+    flags:
+      type: int
+      required: true
+      description: The zephyr gpio interrupt config flags.
+    handler:
+      type: string
+      description: The C function name attached to this interrupt.
diff --git a/zephyr/dts/bindings/gpio/cros-ec,hibernate-wake-pins.yaml b/zephyr/dts/bindings/gpio/cros-ec,hibernate-wake-pins.yaml
new file mode 100644
index 0000000000..a6cb488c48
--- /dev/null
+++ b/zephyr/dts/bindings/gpio/cros-ec,hibernate-wake-pins.yaml
@@ -0,0 +1,13 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Hibernate Wake-up Pins Configurations
+
+compatible: "cros-ec,hibernate-wake-pins"
+
+properties:
+  wakeup-irqs:
+    type: phandles
+    required: true
+    description: Interrupt list for hibernate wake-up
diff --git a/zephyr/dts/bindings/gpio/cros-ec,usba-port-enable-pins.yaml b/zephyr/dts/bindings/gpio/cros-ec,usba-port-enable-pins.yaml
new file mode 100644
index 0000000000..92532c1893
--- /dev/null
+++ b/zephyr/dts/bindings/gpio/cros-ec,usba-port-enable-pins.yaml
@@ -0,0 +1,13 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: USBA Port Enable Pins Configurations
+
+compatible: "cros-ec,usba-port-enable-pins"
+
+properties:
+  enable-pins:
+    type: phandles
+    required: true
+    description: List of USBA Port Enable Pins
diff --git a/zephyr/dts/bindings/gpio/gpio-enum-name.yaml b/zephyr/dts/bindings/gpio/gpio-enum-name.yaml
new file mode 100644
index 0000000000..aaf40e8edc
--- /dev/null
+++ b/zephyr/dts/bindings/gpio/gpio-enum-name.yaml
@@ -0,0 +1,175 @@
+description: Named GPIOs parent node
+properties:
+  enum-name:
+    type: string
+    description:
+      Enum used in code.
+      These names MUST ONLY be referenced by legacy code that is
+      included with Zephyr projects.
+
+      Some development boards like trogdor, volteer etc. shim in
+      the older baseboard/board headers and code, so they
+      are also using most of these names. When these
+      boards get removed, these names can be removed
+
+      Do not add any more names to this list. Please remove
+      any names that are not referenced by Zephyr projects (or
+      are not in included common legacy code)
+    enum:
+      - GPIO_AC_PRESENT
+      - GPIO_AP_EC_SYSRST_ODL
+      - GPIO_AP_EC_WARM_RST_REQ
+      - GPIO_AP_EC_WATCHDOG_L
+      - GPIO_AP_EC_WDTRST_L
+      - GPIO_AP_IN_SLEEP_L
+      - GPIO_AP_RST_L
+      - GPIO_AP_SUSPEND
+      - GPIO_BATT_PRES_ODL
+      - GPIO_BC12_DET_EN
+      - GPIO_BOARD_VERSION1
+      - GPIO_BOARD_VERSION2
+      - GPIO_BOARD_VERSION3
+      - GPIO_CCD_MODE_ODL
+      - GPIO_CPU_PROCHOT
+      - GPIO_DA9313_GPIO0
+      - GPIO_DC_JACK_PRESENT
+      - GPIO_DEPRECATED_AP_RST_REQ
+      - GPIO_EC_INT_L
+      - GPIO_EC_KB_BL_EN_L
+      - GPIO_EC_PCH_SYS_PWROK
+      - GPIO_EC_PMIC_EN_ODL
+      - GPIO_EC_PMIC_WATCHDOG_L
+      - GPIO_EC_PROCHOT_IN_L
+      - GPIO_ENABLE_BACKLIGHT
+      - GPIO_ENABLE_BACKLIGHT_L
+      - GPIO_ENTERING_RW
+      - GPIO_EN_KEYBOARD_BACKLIGHT
+      - GPIO_EN_PP3300_A
+      - GPIO_EN_PP5000
+      - GPIO_EN_PP5000_A
+      - GPIO_EN_PP5000_USBA
+      - GPIO_EN_PP5000_USBA_R
+      - GPIO_EN_PPVAR_VCCIN
+      - GPIO_EN_PWR_A
+      - GPIO_EN_S5_RAILS
+      - GPIO_EN_USB_A_5V
+      - GPIO_IMVP9_VRRDY_OD
+      - GPIO_KB_DISCRETE_INT
+      - GPIO_KBD_KSO2
+      - GPIO_LID_ACCEL_INT_L
+      - GPIO_LID_OPEN
+      - GPIO_PACKET_MODE_EN
+      - GPIO_PCH_DSW_PWROK
+      - GPIO_PCH_PWRBTN_L
+      - GPIO_PCH_PWROK
+      - GPIO_PCH_RSMRST_L
+      - GPIO_PCH_RTCRST
+      - GPIO_PCH_SLP_S0_L
+      - GPIO_PCH_SLP_S3_L
+      - GPIO_PCH_SLP_S5_L
+      - GPIO_PCH_SLP_SUS_L
+      - GPIO_PCH_SYS_PWROK
+      - GPIO_PG_EC_ALL_SYS_PWRGD
+      - GPIO_PG_EC_DSW_PWROK
+      - GPIO_PG_EC_RSMRST_ODL
+      - GPIO_PG_PP4200_S5_OD
+      - GPIO_PMIC_EC_PWRGD
+      - GPIO_PMIC_EC_RESETB
+      - GPIO_PMIC_KPD_PWR_ODL
+      - GPIO_PMIC_RESIN_L
+      - GPIO_POWER_BUTTON_L
+      - GPIO_POWER_GOOD
+      - GPIO_POWER_GOOD_3VALW
+      - GPIO_POWER_GOOD_VR
+      - GPIO_PS_HOLD
+      - GPIO_S0_PGOOD
+      - GPIO_S5_PGOOD
+      - GPIO_SLP_SUS_L
+      - GPIO_SWITCHCAP_ON
+      - GPIO_SWITCHCAP_ON_L
+      - GPIO_SWITCHCAP_PG
+      - GPIO_SWITCHCAP_PG_INT_L
+      - GPIO_SYS_RESET_L
+      - GPIO_SYS_RST_ODL
+      - GPIO_TABLET_MODE_L
+      - GPIO_TEMP_SENSOR_POWER
+      - GPIO_TEST
+      - GPIO_USB_C0_BC12_INT_ODL
+      - GPIO_USB_C0_C2_TCPC_INT_ODL
+      - GPIO_USB_C0_C2_TCPC_RST_ODL
+      - GPIO_USB_C0_DISCHARGE
+      - GPIO_USB_C0_DP_HPD
+      - GPIO_USB_C0_OC_ODL
+      - GPIO_USB_C0_PD_INT_ODL
+      - GPIO_USB_C0_PPC_INT_ODL
+      - GPIO_USB_C0_SWCTL_INT_ODL
+      - GPIO_USB_C0_TCPC_INT_ODL
+      - GPIO_USB_C0_TCPC_RST_L
+      - GPIO_USB_C1_BC12_INT_ODL
+      - GPIO_USB_C1_DISCHARGE
+      - GPIO_USB_C1_DP_HPD
+      - GPIO_USB_C0_FRS_EN
+      - GPIO_USB_C1_FRS_EN
+      - GPIO_USB_C1_LS_EN
+      - GPIO_USB_C1_OC_ODL
+      - GPIO_USB_C1_PD_INT_ODL
+      - GPIO_USB_C1_PPC_INT_ODL
+      - GPIO_USB_C1_RST_ODL
+      - GPIO_USB_C1_RT_RST_ODL
+      - GPIO_USB_C1_RT_RST_R_ODL
+      - GPIO_USB_C1_SWCTL_INT_ODL
+      - GPIO_USB_C1_TCPC_INT_ODL
+      - GPIO_USB_C1_TCPC_RST_L
+      - GPIO_USB_C2_BC12_INT_ODL
+      - GPIO_USB_C2_DISCHARGE
+      - GPIO_USB_C2_PPC_INT_ODL
+      - GPIO_USB1_CTL1
+      - GPIO_USB1_CTL2
+      - GPIO_USB1_CTL3
+      - GPIO_USB1_ILIM_SEL
+      - GPIO_USB2_CTL1
+      - GPIO_USB2_CTL2
+      - GPIO_USB2_CTL3
+      - GPIO_USB2_ILIM_SEL
+      - GPIO_VBOB_EN
+      - GPIO_VCCST_PWRGD_OD
+      - GPIO_VOLUME_DOWN_L
+      - GPIO_VOLUME_UP_L
+      - GPIO_WARM_RESET_L
+      - GPIO_WP_L
+      - GPIO_EC_PD_INTA_L
+      - GPIO_EC_PD_INTB_L
+      - IOEX_USB_A1_RETIMER_EN
+      - IOEX_USB_C0_BB_RETIMER_LS_EN
+      - IOEX_USB_C0_BB_RETIMER_RST
+      - IOEX_USB_C0_C1_OC
+      - IOEX_USB_C0_FRS_EN
+      - IOEX_USB_C0_HBR_LS_EN
+      - IOEX_USB_C0_HBR_RST
+      - IOEX_USB_C0_MUX_SBU_SEL_0
+      - IOEX_USB_C0_MUX_SBU_SEL_1
+      - IOEX_USB_C0_PPC_ILIM_3A_EN
+      - IOEX_USB_C0_SBU_FLIP
+      - IOEX_USB_C0_TCPC_FASTSW_CTL_EN
+      - IOEX_USB_C0_USB_MUX_CNTRL_0
+      - IOEX_USB_C0_USB_MUX_CNTRL_1
+      - IOEX_USB_C1_BB_RETIMER_LS_EN
+      - IOEX_USB_C1_BB_RETIMER_RST
+      - IOEX_USB_C1_FAULT_ODL
+      - IOEX_USB_C1_HBR_LS_EN
+      - IOEX_USB_C1_HBR_RST
+      - IOEX_USB_C1_HPD
+      - IOEX_USB_C1_HPD_IN_DB
+      - IOEX_USB_C1_PPC_ILIM_3A_EN
+      - IOEX_USB_C1_SBU_FLIP
+      - IOEX_USB_C1_TCPC_FASTSW_CTL_EN
+      - IOEX_USB_C2_BB_RETIMER_LS_EN
+      - IOEX_USB_C2_BB_RETIMER_RST
+      - IOEX_USB_C2_HBR_RST
+      - IOEX_USB_C2_HBR_LS_EN
+      - IOEX_USB_C2_C3_OC
+      - IOEX_USB_C2_FRS_EN
+      - IOEX_USB_C3_BB_RETIMER_LS_EN
+      - IOEX_USB_C3_BB_RETIMER_RST
+      - IOEX_USB_C3_HBR_RST
+      - IOEX_USB_C3_HBR_LS_EN
diff --git a/zephyr/dts/bindings/gpio/named-gpios.yaml b/zephyr/dts/bindings/gpio/named-gpios.yaml
new file mode 100644
index 0000000000..7b92f1a636
--- /dev/null
+++ b/zephyr/dts/bindings/gpio/named-gpios.yaml
@@ -0,0 +1,35 @@
+description: Named GPIOs parent node
+
+compatible: "named-gpios"
+
+child-binding:
+  description: Named GPIOs child node
+  include: gpio-enum-name.yaml
+  properties:
+    #
+    # Must name this property [..-]gpios which
+    # is treated specially (looks for #gpio-cells
+    # in referenced node so that cell properties can
+    # be specified). If this property does not exist, treat
+    # this GPIO as unimplemented.
+    gpios:
+      type: phandle-array
+      required: false
+    no-auto-init:
+      description:
+        When set, the GPIO is not initialised, and can be
+        initialised separately in code, but is still saved so that
+        it appears in the list of GPIOs.
+
+        When not set, the GPIO h/w is configured and initialised at startup
+        according to the flags in the gpios node.
+      type: boolean
+      required: false
+    alias:
+      description:
+        When set, defines an alias for this GPIO's enum-name.
+
+        This is to allow common or generic names in legacy code to map
+        to the particular board's GPIO name.
+      type: string
+      required: false
diff --git a/zephyr/dts/bindings/gpio/unused-gpios.yaml b/zephyr/dts/bindings/gpio/unused-gpios.yaml
new file mode 100644
index 0000000000..99f649e25e
--- /dev/null
+++ b/zephyr/dts/bindings/gpio/unused-gpios.yaml
@@ -0,0 +1,11 @@
+description: Unused GPIOs node
+
+compatible: "unused-gpios"
+
+properties:
+  unused-gpios:
+    type: phandle-array
+    required: true
+    description: |
+      A list contains unused GPIOs. The chip vendor needs to configure them for
+      better power consumption in the lowest power state.
diff --git a/zephyr/dts/bindings/i2c/cros-ec,i2c-target-hid.yaml b/zephyr/dts/bindings/i2c/cros-ec,i2c-target-hid.yaml
new file mode 100644
index 0000000000..461f92f7f7
--- /dev/null
+++ b/zephyr/dts/bindings/i2c/cros-ec,i2c-target-hid.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Zephyr I2C target HID implements the i2c-hid
+  protocol as a i2c slave device.
+
+compatible: "cros-ec,i2c-target-hid"
+
+include: [i2c-device.yaml]
+
+properties:
+  reg:
+    required: true
+
+  max_report_size:
+    type: int
+    required: true
+
+  alert_gpios:
+    required: true
+    type: phandle-array
+    description:
+      Active low GPIO to notify the i2c master to
+      service a request.
+
+  hid_descriptor:
+    type: string
+    description:
+      The C function name that will be called to
+      populate the hid report
+
+  hid_report_descriptor:
+    type: string
+    description:
+      The C function name that will be called to
+      populate the hid report
+
+  get_report_handler:
+    type: string
+    description:
+      The C function name that will be called to
+      populate the hid report
+
+  set_report_handler:
+    type: string
+    description:
+      The C function name that will be called to
+      act on a set report from the host
+
+  power_state_handler:
+    type: string
+    description:
+      The C function name that will be called when
+      the host updates the power state
diff --git a/zephyr/dts/bindings/i2c/cros-ec-i2c-port-base.yaml b/zephyr/dts/bindings/i2c/cros-ec-i2c-port-base.yaml
new file mode 100644
index 0000000000..7d3aad07f7
--- /dev/null
+++ b/zephyr/dts/bindings/i2c/cros-ec-i2c-port-base.yaml
@@ -0,0 +1,25 @@
+# Copyright 2021 The ChromiumOS Authors
+# SPDX-License-Identifier: Apache-2.0
+
+description: I2C port base properties
+
+properties:
+  i2c-port:
+    type: phandle
+    required: true
+  remote-port:
+    type: int
+    required: false
+    description:
+      A port number used by remote components like Kernel via the I2C_PASSTHRU
+      Host Command
+  enum-names:
+    type: string-array
+    required: true
+    description:
+      Enum values used in the source code to refer to the i2c port
+  dynamic-speed:
+    type: boolean
+    required: false
+    description:
+      Enables run-time speed configuration.
diff --git a/zephyr/dts/bindings/i2c/named-i2c-ports.yaml b/zephyr/dts/bindings/i2c/named-i2c-ports.yaml
new file mode 100644
index 0000000000..5aa95e5f65
--- /dev/null
+++ b/zephyr/dts/bindings/i2c/named-i2c-ports.yaml
@@ -0,0 +1,10 @@
+# Copyright 2020 The ChromiumOS Authors
+# SPDX-License-Identifier: Apache-2.0
+
+description: Named I2C ports parent node
+
+compatible: "named-i2c-ports"
+
+child-binding:
+  description: Named I2C ports child node
+  include: [cros-ec-i2c-port-base.yaml]
diff --git a/zephyr/dts/bindings/intel/intel,rvp-board-id.yaml b/zephyr/dts/bindings/intel/intel,rvp-board-id.yaml
new file mode 100644
index 0000000000..c066db1550
--- /dev/null
+++ b/zephyr/dts/bindings/intel/intel,rvp-board-id.yaml
@@ -0,0 +1,26 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Intel RVP Board id
+
+compatible: "intel,rvp-board-id"
+
+properties:
+  bom-gpios:
+    type: phandle-array
+    required: true
+    description: |
+     A list contains GPIO pins corresponding to BOM ID bits.
+
+  fab-gpios:
+    type: phandle-array
+    required: true
+    description: |
+     A list contains GPIO pins corresponding to FAB ID bits.
+
+  board-gpios:
+    type: phandle-array
+    required: true
+    description: |
+     A list contains GPIO pins corresponding to BOARD ID bits.
diff --git a/zephyr/dts/bindings/kb_discrete/ite,it8801.yaml b/zephyr/dts/bindings/kb_discrete/ite,it8801.yaml
new file mode 100644
index 0000000000..036d3d0e69
--- /dev/null
+++ b/zephyr/dts/bindings/kb_discrete/ite,it8801.yaml
@@ -0,0 +1,18 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: IT8801 discrete Keyboard matrix with PWM & GPIO
+
+compatible: "ite,it8801"
+
+include: i2c-device.yaml
+
+#
+# examples:
+#
+# kb_not_raw: ite-it8801@38 {
+#         compatible = "ite,it8801";
+#         reg = <0x38>;
+# };
+#
diff --git a/zephyr/dts/bindings/keyboard/cros-ec,kblight-pwm.yaml b/zephyr/dts/bindings/keyboard/cros-ec,kblight-pwm.yaml
new file mode 100644
index 0000000000..9cf862a555
--- /dev/null
+++ b/zephyr/dts/bindings/keyboard/cros-ec,kblight-pwm.yaml
@@ -0,0 +1,20 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: PWM keyboard backlight configuration
+
+compatible: "cros-ec,kblight-pwm"
+
+include: base.yaml
+
+properties:
+  pwms:
+    type: phandle-array
+    required: true
+    description: PWM controlling the Keyboard backlight level.
+
+  generic-pwm-channel:
+    type: int
+    required: false
+    description: Generic PWM channel number for legacy compatibility.
diff --git a/zephyr/dts/bindings/keyboard/cros-ec,keyscan.yaml b/zephyr/dts/bindings/keyboard/cros-ec,keyscan.yaml
new file mode 100644
index 0000000000..17c0d9b717
--- /dev/null
+++ b/zephyr/dts/bindings/keyboard/cros-ec,keyscan.yaml
@@ -0,0 +1,82 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Keyboard scanning properties
+
+compatible: "cros-ec,keyscan"
+
+properties:
+  output-settle:
+    type: int
+    required: false
+    default: 80
+    description: |
+        Delay time, in microseconds, between setting up output and waiting for
+        it to settle. 80 microseconds is the recommended value when column 2
+        of the keyboard passes through the Google Security Chip. Otherwise 50
+        microseconds is the recommended value.
+
+  debounce-down:
+    type: int
+    required: false
+    default: 9000
+    description: |
+        Time, in microseconds, to debounce key-down.
+
+  debounce-up:
+    type: int
+    required: false
+    default: 30000
+    description: |
+        Time, in microseconds, to debounce key-up.
+
+  scan-period:
+    type: int
+    required: false
+    default: 3000
+    description: |
+        Time between scans when keyboard scan task runs in polling mode.
+
+  min-post-scan-delay:
+    type: int
+    required: false
+    default: 1000
+    description: |
+        Minimum time between end of one scan and start of the next one.
+        This ensures keyboard scanning doesn't starve the rest of the system
+        if the scan period is set too short, or if other higher-priority
+        system activity is starving the keyboard scan task too.
+
+  poll-timeout:
+    type: int
+    required: false
+    default: 100000
+    description: |
+        Revert to interrupt mode after no keyboard activity for this period.
+        Specified in microseconds.
+
+  actual-key-mask:
+    type: array
+    required: false
+    default: [
+      0x1c, # C0
+      0xff, # C1
+      0xff, # C2
+      0xff, # C3
+      0xff, # C4
+      0xf5, # C5
+      0xff, # C6
+      0xa4, # C7
+      0xfe, # C8
+      0x55, # C9
+      0xfa, # C10
+      0xff, # C11
+      0xca, # C12
+      0x00, # C13 for keypad
+      0x00, # C14 for keypad
+    ]
+    description: |
+        Keyboard scanning mask. For each keyboard column, specify which
+        keyboard rows actually exist. Default key mask includes scanning for
+        full Chromebook keyboard, excluding the keypad.
diff --git a/zephyr/dts/bindings/led/cros-ec,pwm-leds.yaml b/zephyr/dts/bindings/led/cros-ec,pwm-leds.yaml
new file mode 100644
index 0000000000..1d94ec1b6f
--- /dev/null
+++ b/zephyr/dts/bindings/led/cros-ec,pwm-leds.yaml
@@ -0,0 +1,121 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: PWM LED configuration
+
+compatible: "cros-ec,pwm-leds"
+
+include: base.yaml
+
+properties:
+  leds:
+    type: phandles
+    required: true
+    description: |
+      List of pwm-leds nodes. These are expected to have a pwms property
+      pointing to the relevant PWMs, up to three PWM devices. The order is
+      matched against the array order of the color-map- properties.
+
+      For example
+        pwmleds {
+                compatible = "pwm-leds";
+                pwm_led0: pwm_led_0 {
+                        pwms = <&pwm1 0 PWM_HZ(4800) PWM_POLARITY_INVERTED
+                                &pwm0 0 PWM_HZ(4800) PWM_POLARITY_INVERTED
+                                &pwm2 0 PWM_HZ(4800) PWM_POLARITY_INVERTED>;
+                };
+        };
+        cros-pwmleds {
+                compatible = "cros-ec,pwm-leds";
+                leds = <&pwm_led0>;
+        };
+
+  sidesel:
+    type: phandle
+    required: false
+    description: |
+      A pwm-leds node for the SIDESEL line, if present.
+
+      For example
+        pwmleds {
+                compatible = "pwm-leds";
+                pwm_sidesel: pwm_sidesel {
+                        pwms = <&pwm7 0 PWM_HZ(2400) PWM_POLARITY_INVERTED>;
+                };
+        };
+        cros-pwmleds {
+                compatible = "cros-ec,pwm-leds";
+                sidesel = <&pwm_sidesel>;
+        };
+
+  color-map-red:
+    type: array
+    required: false
+    description: |
+      A map of PWM duty cycles per color, up to three channels. Unset values
+      default to zero.
+
+      For example
+        color-map-red    = <100   0   0>;
+        color-map-green  = <  0 100   0>;
+        color-map-blue   = <  0   0 100>;
+        color-map-yellow = <100  70   0>;
+        color-map-white  = <100  70 100>;
+        color-map-amber  = <100  20   0>;
+
+  color-map-green:
+    type: array
+    required: false
+
+  color-map-blue:
+    type: array
+    required: false
+
+  color-map-yellow:
+    type: array
+    required: false
+
+  color-map-white:
+    type: array
+    required: false
+
+  color-map-amber:
+    type: array
+    required: false
+
+  brightness-range:
+    type: array
+    required: false
+    description: |
+      A list of brigthness range value for all supported channels in order,
+      Red, Green, Blue, Yellow, White, Amber (0 to 255).
+
+child-binding:
+  description: |
+    LED child binding node for mapping a PWM_LED to a EC_LED_ID.
+
+    For example
+
+    pwm_led_0@0 {
+                reg = <0>;
+                ec-led-name = "EC_LED_ID_LEFT_LED";
+    };
+    pwm_led_1@1 {
+                reg = <1>;
+                ec-led-name = "EC_LED_ID_RIGHT_LED";
+    };
+
+  properties:
+    reg:
+      type: int
+      required: true
+      description: LED ID, can be either 0 or 1 for PWM_LED0 and PWM_LED1
+      enum:
+        - 0 # PWM_LED0
+        - 1 # PWM_LED1
+
+    ec-led-name:
+      type: string
+      required: true
+      description: The EC_LED_ID value to map the LED to.
diff --git a/zephyr/dts/bindings/led/maxim,max695x.yaml b/zephyr/dts/bindings/led/maxim,max695x.yaml
new file mode 100644
index 0000000000..a219512b0d
--- /dev/null
+++ b/zephyr/dts/bindings/led/maxim,max695x.yaml
@@ -0,0 +1,18 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: |
+    MAX6958/MAX6959 7-Segment LED Display
+
+    Example configuration
+
+    max695x@38 {
+            compatible = "maxim,max695x";
+            reg = <0x38>;
+    };
+
+
+compatible: "maxim,max695x"
+
+include: i2c-device.yaml
diff --git a/zephyr/dts/bindings/leds/cros-ec,gpio-led-pins.yaml b/zephyr/dts/bindings/leds/cros-ec,gpio-led-pins.yaml
new file mode 100644
index 0000000000..b0310027f9
--- /dev/null
+++ b/zephyr/dts/bindings/leds/cros-ec,gpio-led-pins.yaml
@@ -0,0 +1,85 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: GPIO LED pins parent node
+
+compatible: "cros-ec,gpio-led-pins"
+
+child-binding:
+  description: |
+    Each child node describes all the GPIO pins that need to be altered to set
+    the color of a specific LED.
+    e.g. For a board with 2 GPIO pins that make up a battery LED, the node looks
+    like:
+    battery_led: battery-led {
+                   led-id = "EC_LED_ID_BATTERY_LED";
+                   led-pins = <&gpio_ec_chg_led_y_c1
+                               &gpio_ec_chg_led_w_c1>;
+                };
+  properties:
+    led-id:
+      type: string
+      required: true
+      description: |
+        This property is required by the EC_CMD_LED_CONTROL host command.
+        It must match the enum names defined in ec_commands.h.
+      enum:
+        - EC_LED_ID_BATTERY_LED
+        - EC_LED_ID_POWER_LED
+        - EC_LED_ID_ADAPTER_LED
+        - EC_LED_ID_LEFT_LED
+        - EC_LED_ID_RIGHT_LED
+        - EC_LED_ID_RECOVERY_HW_REINIT_LED
+        - EC_LED_ID_SYSRQ_DEBUG_LED
+    led-pins:
+      type: phandles
+      required: true
+      description: |
+        This property is used to specify an array of gpio pins to set a
+        particular color.
+
+  child-binding:
+    description: |
+      Each grandchild node describes all the colors supported by the child LED.
+      e.g. For a board supporting Blue and Amber LEDs - to set LED_AMBER color,
+      amber LED will need to be set to 1 and blue LED to 0. 1 always turns on
+      the LED and 0 always turns off the LED. So a node looks like
+      color-amber {
+                   led-color = "LED_AMBER";
+                   led-values = <1 0>;
+                  };
+    properties:
+      led-color:
+        type: string
+        required: true
+        description: |
+          This property is used to identify pin nodes based on color enum.
+          It is required by the EC_CMD_LED_CONTROL host command.
+        enum:
+          - LED_OFF
+          - LED_RED
+          - LED_GREEN
+          - LED_BLUE
+          - LED_YELLOW
+          - LED_WHITE
+          - LED_AMBER
+      br-color:
+        type: string
+        required: false
+        description: |
+          This is used in the ectool brightness range APIs. It must match
+          the enum names defined in ec_commands.h.
+        enum:
+          - EC_LED_COLOR_RED
+          - EC_LED_COLOR_GREEN
+          - EC_LED_COLOR_BLUE
+          - EC_LED_COLOR_YELLOW
+          - EC_LED_COLOR_WHITE
+          - EC_LED_COLOR_AMBER
+      led-values:
+        type: array
+        required: true
+        description: |
+          This property is used to specify an array of values to set on the
+          corresponding led-pins to set a particular color.
diff --git a/zephyr/dts/bindings/leds/cros-ec,led-policy.yaml b/zephyr/dts/bindings/leds/cros-ec,led-policy.yaml
new file mode 100644
index 0000000000..3fb7164db2
--- /dev/null
+++ b/zephyr/dts/bindings/leds/cros-ec,led-policy.yaml
@@ -0,0 +1,118 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: LED policy parent node
+
+compatible: "cros-ec,led-policy"
+
+child-binding:
+  description: |
+    LED policy nodes to describe the policy combination a node depends on, and
+    the color to set to for that combination.
+    e.g. If Blue color needs to be set for charge state discharge in S0, a
+    node looks like
+    power-state-discharge-s0 {
+       charge-state = "LED_PWRS_DISCHARGE";
+       chipset-state = "POWER_S0";
+       charge-port = <0>;
+       color-0 {
+         led-color = <&color_blue>;
+       };
+    };
+
+  properties:
+    charge-state:
+      description: |
+        If the LED color depends on charge state, this property is used
+        to describe it.
+        LED_PWRS_CHARGE - AC is connected, battery is charging.
+        LED_PWRS_DISCHARGE - AC is not connected, battery is discharging.
+        LED_PWRS_ERROR - Battery is in error state.
+        LED_PWRS_IDLE - AC is connected, battery is not charging.
+        LED_PWRS_FORCED_IDLE - AC is connected, battery is not charging.
+                                Used during factory testing.
+        LED_PWRS_CHARGE_NEAR_FULL - AC is connected, battery is charging
+                                     and close to fully charged.
+      type: string
+      required: false
+      enum:
+        - LED_PWRS_CHARGE
+        - LED_PWRS_DISCHARGE
+        - LED_PWRS_ERROR
+        - LED_PWRS_IDLE
+        - LED_PWRS_FORCED_IDLE
+        - LED_PWRS_CHARGE_NEAR_FULL
+
+    charge-port:
+      description: |
+        If the LED color depends on the charging port (left or right).
+      type: int
+      required: false
+
+    chipset-state:
+      description: |
+        If the LED color depends on chipset state, this property is used
+        to describe it.
+      type: string
+      required: false
+      enum:
+        - POWER_S0
+        - POWER_S3
+        - POWER_S5
+
+    batt-state-mask:
+      description: |
+        If the LED color depends on battery state, this property is used
+        to describe the kind of battery state.
+        Use the macros defined in dt-bindings/battery.h.
+        e.g. SB_STATUS_DISCHARGING - Battery is discharging.
+      type: int
+      required: false
+
+    batt-state:
+      description: |
+        If the LED color depends on battery state, this property is used
+        to select the battery state value base on batt-state-mask.
+      type: int
+      required: false
+
+    batt-lvl:
+      description: |
+        If the LED color depends on current battery level, this property
+        is used to describe batt_lvl range using closed interval [x,y].
+        Use the macros defined in dt-bindings/battery.h.
+        e.g. <BATTERY_LEVEL_EMPTY BATTERY_LEVEL_LOW> describes battery level
+             range of BATTERY_LEVEL_EMPTY to BATTERY_LEVEL_LOW inclusive.
+      type: array
+      required: false
+
+  child-binding:
+    description: Color enum
+    properties:
+      led-color:
+        description: |
+          Handle to LED pins node that describes pins to set to enable a
+          particular color.
+        type: phandle
+        required: true
+      period-ms:
+        description: |
+          In case of blinking LEDs, amount of time in msecs the LED
+          color is active. This value must be a multiple of
+          HOOK_TICK_INTERVAL_MS.
+          e.g.
+          power-state-error {
+             charge-state = "LED_PWRS_ERROR";
+             /* One sec Amber, one sec Off */
+             color-0 {
+               led-color = <&color_amber>;
+               period-ms = <1000>;
+             };
+             color-1 {
+               led-color = <&color_off>;
+               period-ms = <1000>;
+             };
+          };
+        type: int
+        required: false
diff --git a/zephyr/dts/bindings/leds/cros-ec,pwm-led-pins.yaml b/zephyr/dts/bindings/leds/cros-ec,pwm-led-pins.yaml
new file mode 100644
index 0000000000..1db1a027d8
--- /dev/null
+++ b/zephyr/dts/bindings/leds/cros-ec,pwm-led-pins.yaml
@@ -0,0 +1,82 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: PWM LED pins parent node
+
+compatible: "cros-ec,pwm-led-pins"
+
+child-binding:
+  description: |
+    Each child node describes all the PWM pins that need to be altered to set
+    the color of a specific LED.
+    e.g. For a battery LED, a node looks like this.
+    battery_led: battery-led {
+                 led-id = "EC_LED_ID_BATTERY_LED";
+                 led-pwms = <&pwm_led_y &pwm_led_b>;
+                };
+  properties:
+    led-id:
+      type: string
+      required: true
+      description: |
+        This property is required by the EC_CMD_LED_CONTROL host command.
+        It must match the enum names defined in ec_commands.h.
+      enum:
+        - EC_LED_ID_BATTERY_LED
+        - EC_LED_ID_POWER_LED
+        - EC_LED_ID_ADAPTER_LED
+        - EC_LED_ID_LEFT_LED
+        - EC_LED_ID_RIGHT_LED
+        - EC_LED_ID_RECOVERY_HW_REINIT_LED
+        - EC_LED_ID_SYSRQ_DEBUG_LED
+    led-pwms:
+      type: phandles
+      required: true
+      description: |
+        This property is used to specify an array of pwms to set a
+        particular color.
+
+  child-binding:
+    description: |
+      Each grandchild node describes all the colors supported by the child LED.
+      e.g. For blue and amber PWM channels, in order to set color amber, a node
+      looks like this where 100 is PWM duty cycle in percentage.
+      color-amber {
+                   led-color = "LED_AMBER";
+                   led-values = <100 0>;
+                  };
+    properties:
+      led-color:
+        type: string
+        required: true
+        description: |
+          This property is used to identify pin nodes based on color enum.
+          It is required by the EC_CMD_LED_CONTROL host command.
+        enum:
+          - LED_OFF
+          - LED_RED
+          - LED_GREEN
+          - LED_BLUE
+          - LED_YELLOW
+          - LED_WHITE
+          - LED_AMBER
+      br-color:
+        type: string
+        required: false
+        description: |
+          This is used in the ectool brightness range APIs. It must match
+          the enum names defined in ec_commands.h.
+        enum:
+          - EC_LED_COLOR_RED
+          - EC_LED_COLOR_GREEN
+          - EC_LED_COLOR_BLUE
+          - EC_LED_COLOR_YELLOW
+          - EC_LED_COLOR_WHITE
+          - EC_LED_COLOR_AMBER
+      led-values:
+        type: array
+        required: true
+        description: |
+          This property is used to specify an array of values to set on the
+          corresponding pwm-pins to set a particular color.
diff --git a/zephyr/dts/bindings/motionsense/cros-ec,motionsense-bodydetect.yaml b/zephyr/dts/bindings/motionsense/cros-ec,motionsense-bodydetect.yaml
new file mode 100644
index 0000000000..4977816c68
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/cros-ec,motionsense-bodydetect.yaml
@@ -0,0 +1,46 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+include: base.yaml
+
+compatible: "cros-ec,motionsense-bodydetect"
+
+description: Body detection configuration parameters
+properties:
+  var_noise_factor:
+    type: int
+    required: false
+    description: |
+      The unit is percentage
+      This is used for mitigate the effect of the noise from sensor.
+      If set to 100%, the average noise is canceled out.
+  var_threshold:
+    type: int
+    required: false
+    description: |
+      The unit is (mm/s^2)^2
+      The motion confidence is calculated if the variance is within
+      variance_threshold +/- confidence_delta. Otherwise, if variance
+      is too high/low, confidence will be 100%/0%
+  confidence_delta:
+    type: int
+    required: false
+    description: |
+      The unit is (mm/s^2)^2
+      The motion confidence is calculated if the variance is within
+      variance_threshold +/- confidence_delta. Otherwise, if variance
+      is too high/low, confidence will be 100%/0%
+
+# example:
+# base_accel: base-accel {
+#    compatible = "cros-ec,lis2dw12";
+#    (...)
+#    bodydetect {
+#         compatible = "cros-ec,motionsense-bodydetect";
+#         status = "okay";
+#         var_noise_factor = <150>;
+#         var_threshold = <3000>;
+#         confidence_delta = <2900>;
+#   };
+# };
diff --git a/zephyr/dts/bindings/motionsense/cros-ec,motionsense-mutex.yaml b/zephyr/dts/bindings/motionsense/cros-ec,motionsense-mutex.yaml
new file mode 100644
index 0000000000..17c60744c8
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/cros-ec,motionsense-mutex.yaml
@@ -0,0 +1,24 @@
+# Copyright 2021 The ChromiumOS Authors
+# SPDX-License-Identifier: Apache-2.0
+
+description: Motion sense mutex parent node
+
+compatible: "cros-ec,motionsense-mutex"
+
+child-binding:
+  description: A mutex node is used to create an instance of mutex_t.
+               A mutex node is referenced by one or more sensor nodes in
+               "/motionsense-sensors" node.
+
+#
+# examples:
+#
+# motionsense-mutex {
+#         compatible = "cros-ec,motionsense-mutex";
+#         mutex_bma255: bma255-mutex {
+#         };
+#
+#         mutex_bmi260: bmi260-mutex {
+#         };
+# };
+#
diff --git a/zephyr/dts/bindings/motionsense/cros-ec,motionsense-rotation-ref.yaml b/zephyr/dts/bindings/motionsense/cros-ec,motionsense-rotation-ref.yaml
new file mode 100644
index 0000000000..da2b99e928
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/cros-ec,motionsense-rotation-ref.yaml
@@ -0,0 +1,55 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: rotation reference parent node
+
+compatible: "cros-ec,motionsense-rotation-ref"
+
+child-binding:
+  description: |
+    A rotation matrix node is used to create
+    an instance of mat33_fp_t which is used by
+    sensor drivers.
+  properties:
+    mat33:
+      required: true
+      type: array
+      description: |
+        3x3 matrix to rotate x, y, and z axes.
+        Applications with the sensor API expects sansor data
+        based on the same defined coordinate system.
+        * X-axis is horizontal and positive toward the right
+        * Y-axis is vertical and positive toward the top
+        * Z-axis points toward the user
+
+        Depending on how the sensor is mounted on board(PCB), we
+        may need to change the direction of a axis and swap X and
+        Y-axis. Using the 3x3 matrix, it generates the correct
+        X,Y, and Z on the defined coordinate system.
+
+        +-        -+   +-        -+   +- -+
+        | v1 v2 v3 |   | sensor_X |   | X |
+        | v4 v5 v6 | * | sensor_Y | = | Y |
+        | v7 v8 v9 |   | sensor_Z |   | Z |
+        +-        -+   +-        -+   +- -+
+
+#
+# examples:
+#
+# motionsense-rotation-ref {
+#        compatible = "cros-ec,motionsense-rotation-ref";
+#        /* change the direction of Y and Z-axis */
+#        lid_rot_ref: lid-rotation-ref {
+#                mat33 = <1 0 0
+#                         0 (-1) 0
+#                         0 0 (-1)>;
+#        };
+#        /* swap X and Y-axis, and then change the direction of Y-axis */
+#        base_rot_ref: base-rotation-ref {
+#                mat33 = <0 1 0
+#                         (-1) 0 0
+#                         0 0 1>;
+#        };
+# };
+#
diff --git a/zephyr/dts/bindings/motionsense/cros-ec,motionsense-sensor-config.yaml b/zephyr/dts/bindings/motionsense/cros-ec,motionsense-sensor-config.yaml
new file mode 100644
index 0000000000..cb0fd96d95
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/cros-ec,motionsense-sensor-config.yaml
@@ -0,0 +1,57 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: |
+    There are 4 configuration parameters to deal with different
+    configuration
+    Power   |         S0        |            S3     |      S5
+    --------+-------------------+-------------------+-----------------
+    From AP | <------- SENSOR_CONFIG_AP ----------> |
+            | Use for normal    | While sleeping    | Always disabled
+            | operation (game,  | For Activity      |
+            | screen rotation)  | Recognition       |
+    --------+-------------------+-------------------+------------------
+    From EC |SENSOR_CONFIG_EC_S0|SENSOR_CONFIG_EC_S3|SENSOR_CONFIG_EC_S5
+            | Background        | Gesture  Recognition (Double tap, ...)
+            | Activity (compass,|
+            | ambient light)    |
+
+compatible: "cros-ec,motionsense-sensor-config"
+
+child-binding:
+  description: |
+    A config node is used to create a motion_data_t instance.
+    Node name can only be either ap, ec-s0, ec-s3, or ec-s5,
+    and it is used to indicate one of the 4 configurations.
+    For example, node name ec-s0 is for SENSOR_CONFIG_EC_S0.
+    ec-s0 {
+       odr = <1000>;
+       ec_rate = <1000>;
+    };
+  properties:
+    odr:
+      type: int
+      required: false
+      description: |
+        Sensor output data rate in mHz.
+        MSB is used to know if we are rounding up.
+    ec-rate:
+      type: int
+      required: false
+      description: Delay between collection by EC, in us.
+
+#
+# examples:
+#
+# configs {
+#         compatible =
+#                 "cros-ec,motionsense-sensor-config";
+#         ec-s0 {
+#                 odr = <(10000 | ROUND_UP_FLAG)>;
+#         };
+#         ec-s3 {
+#                 odr = <(10000 | ROUND_UP_FLAG)>;
+#         };
+# };
+#
diff --git a/zephyr/dts/bindings/motionsense/cros-ec,motionsense-sensor-info.yaml b/zephyr/dts/bindings/motionsense/cros-ec,motionsense-sensor-info.yaml
new file mode 100644
index 0000000000..b0e960e559
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/cros-ec,motionsense-sensor-info.yaml
@@ -0,0 +1,56 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: The node has the information required by motion sense running
+
+compatible: "cros-ec,motionsense-sensor-info"
+
+properties:
+  als-sensors:
+    type: phandles
+    required: false
+    description: |
+        List of ALS sensors to create motion_als_sensors array.
+        The ALS sensors listed in the motion_als_sensors array
+        are managed by motion sense task. The task reads the sensor
+        data from the sensors and put them into the designated part
+        in the ec mmap. For example, als_clear and als_rgb are aliases
+        of ALS sensor noded defined in motionsense-sensor node.
+        als-sensors = <&als_clear, &als_rgb>;
+        This will automatically generate motion_als_sensors array from it.
+  sensor-irqs:
+    type: phandles
+    required: false
+    description: |
+        List of interrupts from sensors GPIOS to be enabled.
+        Interrupts specified here will be enabled before motion sense task starts.
+        sensor-irqs = <&int_imu &int_als_rgb>;
+  accel-force-mode-sensors:
+    type: phandles
+    required: false
+    description: |
+        List of sensors should be handled in force mode. Sensors listed will be
+        used to define CONFIG_ACCEL_FORCE_MODE_MASK so that motion sense task can
+        manage them in force mode.
+        accel-force-mode-sensors = <&lid_accel &als_clear>;
+
+#
+# examples:
+#
+# motionsense-sensor-info {
+#        compatible = "cros-ec,motionsense-sensor-info";
+#
+#        /* list of entries for motion_als_sensors */
+#        als-sensors = <&als_clear>;
+#
+#        /*
+#         * list of GPIO interrupts that have to
+#         * be enabled at initial stage
+#         */
+#        sensor-irqs = <&gpio_ec_imu_int_l &gpio_ec_als_rgb_int_l>;
+#
+#        /* list of sensors in force mode */
+#        accel-force-mode-sensors = <&lid_accel &als_clear>;
+# };
+#
diff --git a/zephyr/dts/bindings/motionsense/driver/bmi160.yaml b/zephyr/dts/bindings/motionsense/driver/bmi160.yaml
new file mode 100644
index 0000000000..e2c4bd6ac7
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/driver/bmi160.yaml
@@ -0,0 +1,16 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# common fields for both BMI160 accel and BMI160 gyro
+
+# every motionsense sensor node should include motionsense-sensor-base.yaml
+include: motionsense-sensor-base.yaml
+
+properties:
+  i2c-spi-addr-flags:
+    type: string
+    description: i2c address or SPI peripheral logic GPIO
+    enum:
+      - "BMI160_ADDR0_FLAGS"
+    default: "BMI160_ADDR0_FLAGS"
diff --git a/zephyr/dts/bindings/motionsense/driver/bmi260.yaml b/zephyr/dts/bindings/motionsense/driver/bmi260.yaml
new file mode 100644
index 0000000000..33fd4356b8
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/driver/bmi260.yaml
@@ -0,0 +1,16 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# common fields for both BMI260 accel and BMI260 gyro
+
+# every motionsense sensor node should include motionsense-sensor-base.yaml
+include: motionsense-sensor-base.yaml
+
+properties:
+  i2c-spi-addr-flags:
+    type: string
+    description: i2c address or SPI slave logic GPIO
+    enum:
+      - "BMI260_ADDR0_FLAGS"
+    default: "BMI260_ADDR0_FLAGS"
diff --git a/zephyr/dts/bindings/motionsense/driver/bmi3xx.yaml b/zephyr/dts/bindings/motionsense/driver/bmi3xx.yaml
new file mode 100644
index 0000000000..e9e603fc96
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/driver/bmi3xx.yaml
@@ -0,0 +1,16 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# common fields for both BMI260 accel and BMI260 gyro
+
+# every motionsense sensor node should include motionsense-sensor-base.yaml
+include: motionsense-sensor-base.yaml
+
+properties:
+  i2c-spi-addr-flags:
+    type: string
+    description: i2c address or SPI slave logic GPIO
+    enum:
+      - "BMI3_ADDR_I2C_PRIM"
+    default: "BMI3_ADDR_I2C_PRIM"
diff --git a/zephyr/dts/bindings/motionsense/driver/cm32183.yaml b/zephyr/dts/bindings/motionsense/driver/cm32183.yaml
new file mode 100644
index 0000000000..ee4588e437
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/driver/cm32183.yaml
@@ -0,0 +1,10 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: >
+  Properties for a CM32183 I2C ambient light sensor
+
+compatible: "nxp,cm32183"
+
+include: i2c-device.yaml
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,bma255.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,bma255.yaml
new file mode 100644
index 0000000000..12a5be2d44
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/driver/cros-ec,bma255.yaml
@@ -0,0 +1,21 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: motionsense sensor node for BMA255
+
+compatible: "cros-ec,bma255"
+
+# every motionsense sensor node should include motionsense-sensor-base.yaml
+include: motionsense-sensor-base.yaml
+
+properties:
+  i2c-spi-addr-flags:
+    type: string
+    description: i2c address or SPI peripheral logic GPIO
+    enum:
+      - "BMA2x2_I2C_ADDR1_FLAGS"
+      - "BMA2x2_I2C_ADDR2_FLAGS"
+      - "BMA2x2_I2C_ADDR3_FLAGS"
+      - "BMA2x2_I2C_ADDR4_FLAGS"
+    default: "BMA2x2_I2C_ADDR1_FLAGS"
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,bma4xx.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,bma4xx.yaml
new file mode 100644
index 0000000000..b17b372af1
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/driver/cros-ec,bma4xx.yaml
@@ -0,0 +1,19 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: motionsense sensor node for BMA4xx
+
+compatible: "cros-ec,bma4xx"
+
+# every motionsense sensor node should include motionsense-sensor-base.yaml
+include: motionsense-sensor-base.yaml
+
+properties:
+  i2c-spi-addr-flags:
+    type: string
+    description: i2c address or SPI peripheral logic GPIO
+    enum:
+      - "BMA4_I2C_ADDR_PRIMARY"
+      - "BMA4_I2C_ADDR_SECONDARY"
+    default: "BMA4_I2C_ADDR_PRIMARY"
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi160-accel.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi160-accel.yaml
new file mode 100644
index 0000000000..cb574c6c0c
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi160-accel.yaml
@@ -0,0 +1,13 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: motion sense sensor node for BMI160 accel
+
+compatible: "cros-ec,bmi160-accel"
+
+include: bmi160.yaml
+
+properties:
+  default-range:
+    default: 4
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi160-gyro.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi160-gyro.yaml
new file mode 100644
index 0000000000..8064549e4a
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi160-gyro.yaml
@@ -0,0 +1,13 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: motion sense sensor node for BMI160 gyro
+
+compatible: "cros-ec,bmi160-gyro"
+
+include: bmi160.yaml
+
+properties:
+  default-range:
+    default: 1000
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi260-accel.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi260-accel.yaml
new file mode 100644
index 0000000000..d18feaa813
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi260-accel.yaml
@@ -0,0 +1,13 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: motion sense sensor node for BMI260 accel
+
+compatible: "cros-ec,bmi260-accel"
+
+include: bmi260.yaml
+
+properties:
+  default-range:
+    default: 4
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi260-gyro.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi260-gyro.yaml
new file mode 100644
index 0000000000..29e87e89ee
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi260-gyro.yaml
@@ -0,0 +1,13 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: motion sense sensor node for BMI260 gyro
+
+compatible: "cros-ec,bmi260-gyro"
+
+include: bmi260.yaml
+
+properties:
+  default-range:
+    default: 1000
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi3xx-accel.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi3xx-accel.yaml
new file mode 100644
index 0000000000..7d0f077226
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi3xx-accel.yaml
@@ -0,0 +1,13 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: motion sense sensor node for BMI3XX accel
+
+compatible: "cros-ec,bmi3xx-accel"
+
+include: bmi3xx.yaml
+
+properties:
+  default-range:
+    default: 4
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi3xx-gyro.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi3xx-gyro.yaml
new file mode 100644
index 0000000000..0085dc5648
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi3xx-gyro.yaml
@@ -0,0 +1,13 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: motion sense sensor node for BMI3XX gyro
+
+compatible: "cros-ec,bmi3xx-gyro"
+
+include: bmi3xx.yaml
+
+properties:
+  default-range:
+    default: 1000
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,icm42607-accel.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,icm42607-accel.yaml
new file mode 100644
index 0000000000..7812870aee
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/driver/cros-ec,icm42607-accel.yaml
@@ -0,0 +1,13 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: motion sense sensor node for ICM42607 accel
+
+compatible: "cros-ec,icm42607-accel"
+
+include: icm42607.yaml
+
+properties:
+  default-range:
+    default: 4
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,icm42607-gyro.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,icm42607-gyro.yaml
new file mode 100644
index 0000000000..fb4739242f
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/driver/cros-ec,icm42607-gyro.yaml
@@ -0,0 +1,13 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: motion sense sensor node for ICM42607 gyro
+
+compatible: "cros-ec,icm42607-gyro"
+
+include: icm42607.yaml
+
+properties:
+  default-range:
+    default: 1000
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,icm426xx-accel.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,icm426xx-accel.yaml
new file mode 100644
index 0000000000..d41275cdd8
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/driver/cros-ec,icm426xx-accel.yaml
@@ -0,0 +1,13 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: motion sense sensor node for ICM426xx accel
+
+compatible: "cros-ec,icm426xx-accel"
+
+include: icm426xx.yaml
+
+properties:
+  default-range:
+    default: 4
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,icm426xx-gyro.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,icm426xx-gyro.yaml
new file mode 100644
index 0000000000..bcad871fc7
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/driver/cros-ec,icm426xx-gyro.yaml
@@ -0,0 +1,13 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: motion sense sensor node for ICM426xx gyro
+
+compatible: "cros-ec,icm426xx-gyro"
+
+include: icm426xx.yaml
+
+properties:
+  default-range:
+    default: 1000
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,kx022.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,kx022.yaml
new file mode 100644
index 0000000000..e66988502a
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/driver/cros-ec,kx022.yaml
@@ -0,0 +1,21 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: motionsense sensor node for KX022
+
+compatible: "cros-ec,kx022"
+
+# every motionsense sensor node should include motionsense-sensor-base.yaml
+include: motionsense-sensor-base.yaml
+
+properties:
+  i2c-spi-addr-flags:
+    type: string
+    description: i2c address or SPI peripheral logic GPIO
+    enum:
+      - "KX022_ADDR0_FLAGS"
+      - "KX022_ADDR1_FLAGS"
+    default: "KX022_ADDR0_FLAGS"
+  default-range:
+    default: 2
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,lis2dw12.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,lis2dw12.yaml
new file mode 100644
index 0000000000..9dd07a7b78
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/driver/cros-ec,lis2dw12.yaml
@@ -0,0 +1,21 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: motionsense sensor node for LIS2DW12 Accelerometer
+
+compatible: "cros-ec,lis2dw12"
+
+# every motionsense sensor node should include motionsense-sensor-base.yaml
+include: motionsense-sensor-base.yaml
+
+properties:
+  i2c-spi-addr-flags:
+    type: string
+    description: i2c address or SPI peripheral logic GPIO
+    enum:
+      - "LIS2DWL_ADDR0_FLAGS"
+      - "LIS2DWL_ADDR1_FLAGS"
+    default: "LIS2DWL_ADDR1_FLAGS"
+  default-range:
+    default: 2
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,lsm6dsm-accel.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,lsm6dsm-accel.yaml
new file mode 100644
index 0000000000..25bd059906
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/driver/cros-ec,lsm6dsm-accel.yaml
@@ -0,0 +1,13 @@
+# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: motionsense sensor node for LSM6DSM Accelerometer
+
+compatible: "cros-ec,lsm6dsm-accel"
+
+include: lsm6dsm.yaml
+
+properties:
+  default-range:
+    default: 4
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,lsm6dsm-gyro.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,lsm6dsm-gyro.yaml
new file mode 100644
index 0000000000..737f3a5105
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/driver/cros-ec,lsm6dsm-gyro.yaml
@@ -0,0 +1,13 @@
+# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: motionsense sensor node for LSM6DSM Gyro
+
+compatible: "cros-ec,lsm6dsm-gyro"
+
+include: lsm6dsm.yaml
+
+properties:
+  default-range:
+    default: 1000
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,lsm6dso-accel.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,lsm6dso-accel.yaml
new file mode 100644
index 0000000000..044c187c50
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/driver/cros-ec,lsm6dso-accel.yaml
@@ -0,0 +1,13 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: motionsense sensor node for LSM6DSO Accelerometer
+
+compatible: "cros-ec,lsm6dso-accel"
+
+include: lsm6dso.yaml
+
+properties:
+  default-range:
+    default: 2
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,lsm6dso-gyro.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,lsm6dso-gyro.yaml
new file mode 100644
index 0000000000..1a946eab98
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/driver/cros-ec,lsm6dso-gyro.yaml
@@ -0,0 +1,13 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: motionsense sensor node for LSM6DSO Gyro
+
+compatible: "cros-ec,lsm6dso-gyro"
+
+include: lsm6dso.yaml
+
+properties:
+  default-range:
+    default: 1000
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,tcs3400-clear.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,tcs3400-clear.yaml
new file mode 100644
index 0000000000..05033de35e
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/driver/cros-ec,tcs3400-clear.yaml
@@ -0,0 +1,9 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: motion sense sensor node for TCS3400 CLEAR
+
+compatible: "cros-ec,tcs3400-clear"
+
+include: tcs3400.yaml
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,tcs3400-rgb.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,tcs3400-rgb.yaml
new file mode 100644
index 0000000000..903574a7f3
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/driver/cros-ec,tcs3400-rgb.yaml
@@ -0,0 +1,9 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: motion sense sensor node for TCS3400 RGB
+
+compatible: "cros-ec,tcs3400-rgb"
+
+include: tcs3400.yaml
diff --git a/zephyr/dts/bindings/motionsense/driver/icm42607.yaml b/zephyr/dts/bindings/motionsense/driver/icm42607.yaml
new file mode 100644
index 0000000000..4052f12fd9
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/driver/icm42607.yaml
@@ -0,0 +1,17 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# common fields for both ICM426xx accel and gyro
+
+# every motionsense sensor node should include motionsense-sensor-base.yaml
+include: motionsense-sensor-base.yaml
+
+properties:
+  i2c-spi-addr-flags:
+    type: string
+    description: i2c address or SPI peripheral logic GPIO
+    enum:
+      - "ICM42607_ADDR0_FLAGS"
+      - "ICM42607_ADDR1_FLAGS"
+    default: "ICM42607_ADDR0_FLAGS"
diff --git a/zephyr/dts/bindings/motionsense/driver/icm426xx.yaml b/zephyr/dts/bindings/motionsense/driver/icm426xx.yaml
new file mode 100644
index 0000000000..7f5e8e164c
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/driver/icm426xx.yaml
@@ -0,0 +1,17 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# common fields for both ICM426xx accel and gyro
+
+# every motionsense sensor node should include motionsense-sensor-base.yaml
+include: motionsense-sensor-base.yaml
+
+properties:
+  i2c-spi-addr-flags:
+    type: string
+    description: i2c address or SPI peripheral logic GPIO
+    enum:
+      - "ICM426XX_ADDR0_FLAGS"
+      - "ICM426XX_ADDR1_FLAGS"
+    default: "ICM426XX_ADDR0_FLAGS"
diff --git a/zephyr/dts/bindings/motionsense/driver/lsm6dsm.yaml b/zephyr/dts/bindings/motionsense/driver/lsm6dsm.yaml
new file mode 100644
index 0000000000..efd71fe181
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/driver/lsm6dsm.yaml
@@ -0,0 +1,19 @@
+# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# common fields for both LSM6DSM accel and gyro
+
+# every motionsense sensor node should include motionsense-sensor-base.yaml
+include: motionsense-sensor-base.yaml
+
+properties:
+  i2c-spi-addr-flags:
+    type: string
+    description: i2c address or SPI peripheral logic GPIO
+    # Address is b'0110101x' where x is determined by the
+    # logic level on SA0
+    enum:
+      - "LSM6DSM_ADDR0_FLAGS"
+      - "LSM6DSM_ADDR1_FLAGS"
+    default: "LSM6DSM_ADDR0_FLAGS"
diff --git a/zephyr/dts/bindings/motionsense/driver/lsm6dso.yaml b/zephyr/dts/bindings/motionsense/driver/lsm6dso.yaml
new file mode 100644
index 0000000000..565c64b1c8
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/driver/lsm6dso.yaml
@@ -0,0 +1,19 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# common fields for both LSM6DSO accel and gyro
+
+# every motionsense sensor node should include motionsense-sensor-base.yaml
+include: motionsense-sensor-base.yaml
+
+properties:
+  i2c-spi-addr-flags:
+    type: string
+    description: i2c address or SPI peripheral logic GPIO
+    # Address is b'0110101x' where x is determined by the
+    # logic level on SA0
+    enum:
+      - "LSM6DSO_ADDR0_FLAGS"
+      - "LSM6DSO_ADDR1_FLAGS"
+    default: "LSM6DSO_ADDR0_FLAGS"
diff --git a/zephyr/dts/bindings/motionsense/driver/tcs3400.yaml b/zephyr/dts/bindings/motionsense/driver/tcs3400.yaml
new file mode 100644
index 0000000000..1c2fbeccbc
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/driver/tcs3400.yaml
@@ -0,0 +1,18 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# common fields for both TCS3400 clear and TCS3400 rgb
+
+# every motionsense sensor node should include motionsense-sensor-base.yaml
+include: motionsense-sensor-base.yaml
+
+properties:
+  i2c-spi-addr-flags:
+    type: string
+    description: i2c address or SPI peripheral logic GPIO
+    enum:
+      - "TCS3400_I2C_ADDR_FLAGS"
+    default: "TCS3400_I2C_ADDR_FLAGS"
+  default-range:
+    default: 0x10000 # scale = 1x, uscale = 0
diff --git a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,accelgyro-als-channel-scale.yaml b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,accelgyro-als-channel-scale.yaml
new file mode 100644
index 0000000000..39f92c7a50
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,accelgyro-als-channel-scale.yaml
@@ -0,0 +1,29 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: |
+  Bindings for als_channel_scale_t in accelgyro.h.
+  Each channel has scaling factor for normalization & cover
+
+compatible: "cros-ec,accelgyro-als-channel-scale"
+
+properties:
+  k-channel-scale:
+    type: int
+    required: true
+    description: Channel scale factor
+  cover-scale:
+    type: int
+    required: true
+    description: Cover compensation scale factor
+
+#
+# examples:
+#
+# als-channel-scale {
+#        compatible = "cros-ec,accelgyro-als-channel-scale";
+#        k-channel-scale = <1>;
+#        cover-scale = <1>;
+# };
+#
diff --git a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,accelgyro-als-drv-data.yaml b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,accelgyro-als-drv-data.yaml
new file mode 100644
index 0000000000..13a64bafb0
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,accelgyro-als-drv-data.yaml
@@ -0,0 +1,44 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: ALS driver data
+
+compatible: "cros-ec,accelgyro-als-drv-data"
+
+child-binding:
+  description: ALS calibration data
+  properties:
+    scale:
+      type: int
+      required: true
+      description: |
+        Scale, uscale, and offset are used to correct the raw 16 bit ALS data
+        and then to convert it to 32 bit using the following equations
+        raw_value += offset;\n
+        adjusted_value = raw_value * scale + raw_value * uscale / 10000;
+    uscale:
+      type: int
+      required: true
+      description: uscale
+    offset:
+      type: int
+      required: true
+      description: offset
+
+#
+# examples:
+# als-drv-data {
+#        compatible = "cros-ec,accelgyro-als-drv-data";
+#        als-cal {
+#                scale = <1>;
+#                uscale = <0>;
+#                offset = <0>;
+#                als-channel-scale {
+#                compatible = "cros-ec,accelgyro-als-channel-scale";
+#                        k-channel-scale = <1>;
+#                        cover-scale = <1>;
+#                };
+#        };
+# };
+#
diff --git a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,accelgyro-rgb-calibration.yaml b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,accelgyro-rgb-calibration.yaml
new file mode 100644
index 0000000000..e0ef479ffd
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,accelgyro-rgb-calibration.yaml
@@ -0,0 +1,63 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: bindings for rgb_calibration_t in accelgyro.h
+
+compatible: "cros-ec,accelgyro-rgb-calibration"
+
+properties:
+  irt:
+    type: int
+    required: true
+    description: incandecent scaling factor
+
+child-binding:
+  description: RGB ALS Calibration Data
+  properties:
+    offset:
+      type: int
+      required: true
+      description: Any offset to add to raw channel data
+    coeff:
+      type: array
+      required: true
+      description: Clear, R, G, and B coefficients for this channel
+
+#
+# examples:
+#
+# rgb_calibration {
+#        compatible = "cros-ec,accelgyro-rgb-calibration";
+#
+#        irt = <1>;
+#
+#        rgb-cal-x {
+#                offset = <0>;
+#                coeff = <0 0 0 0>;
+#                als-channel-scale {
+#                compatible = "cros-ec,accelgyro-als-channel-scale";
+#                        k-channel-scale = <1>;
+#                        cover-scale = <1>;
+#                };
+#        };
+#        rgb-cal-y {
+#                offset = <0>;
+#                coeff = <0 0 0 0>;
+#                als-channel-scale {
+#                compatible = "cros-ec,accelgyro-als-channel-scale";
+#                        k-channel-scale = <1>;
+#                        cover-scale = <1>;
+#                };
+#        };
+#        rgb-cal-z {
+#                offset = <0>;
+#                coeff = <0 0 0 0>;
+#                als-channel-scale {
+#                compatible = "cros-ec,accelgyro-als-channel-scale";
+#                        k-channel-scale = <1>;
+#                        cover-scale = <1>;
+#                };
+#        };
+# };
+#
diff --git a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bma255.yaml b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bma255.yaml
new file mode 100644
index 0000000000..8749d96de6
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bma255.yaml
@@ -0,0 +1,18 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: BMA255 driver data node
+
+compatible: "cros-ec,drvdata-bma255"
+
+include: drvdata-base.yaml
+
+#
+# examples:
+#
+# bma255_data: bma255-drv-data {
+#       compatible = "cros-ec,drvdata-bma255";
+#       status = "okay";
+# };
+#
diff --git a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bma4xx.yaml b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bma4xx.yaml
new file mode 100644
index 0000000000..5504b3642c
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bma4xx.yaml
@@ -0,0 +1,18 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: BMA4XX driver data node
+
+compatible: "cros-ec,drvdata-bma4xx"
+
+include: drvdata-base.yaml
+
+#
+# examples:
+#
+# bma4xx_data: bma4xx-drv-data {
+#       compatible = "cros-ec,drvdata-bma4xx";
+#       status = "okay";
+# };
+#
diff --git a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bmi160.yaml b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bmi160.yaml
new file mode 100644
index 0000000000..c4aea99ea1
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bmi160.yaml
@@ -0,0 +1,18 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: BMI160 driver data node
+
+compatible: "cros-ec,drvdata-bmi160"
+
+include: drvdata-base.yaml
+
+#
+# examples:
+#
+# bmi160_data: bmi160-drv-data {
+#        compatible = "cros-ec,drvdata-bmi160";
+#        status = "okay";
+# };
+#
diff --git a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bmi260.yaml b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bmi260.yaml
new file mode 100644
index 0000000000..a6247c6cd4
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bmi260.yaml
@@ -0,0 +1,18 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: BMI260 driver data node
+
+compatible: "cros-ec,drvdata-bmi260"
+
+include: drvdata-base.yaml
+
+#
+# examples:
+#
+# bmi260_data: bmi260-drv-data {
+#        compatible = "cros-ec,drvdata-bmi260";
+#        status = "okay";
+# };
+#
diff --git a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bmi3xx.yaml b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bmi3xx.yaml
new file mode 100644
index 0000000000..5ca2059b3d
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bmi3xx.yaml
@@ -0,0 +1,18 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: BMI3XX driver data node
+
+compatible: "cros-ec,drvdata-bmi3xx"
+
+include: drvdata-base.yaml
+
+#
+# examples:
+#
+# bmi3xx_data: bmi3xx-drv-data {
+#        compatible = "cros-ec,drvdata-bmi3xx";
+#        status = "okay";
+# };
+#
diff --git a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-icm426xx.yaml b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-icm426xx.yaml
new file mode 100644
index 0000000000..04ba419d69
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-icm426xx.yaml
@@ -0,0 +1,18 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: ICM426xx driver data node
+
+compatible: "cros-ec,drvdata-icm426xx"
+
+include: drvdata-base.yaml
+
+#
+# examples:
+#
+# icm426xx_data: icm426xx-drv-data {
+#       compatible = "cros-ec,drvdata-icm426xx";
+#       status = "okay";
+# };
+#
diff --git a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-kionix.yaml b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-kionix.yaml
new file mode 100644
index 0000000000..0f86616ae2
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-kionix.yaml
@@ -0,0 +1,18 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Kionix driver data node
+
+compatible: "cros-ec,drvdata-kionix"
+
+include: drvdata-base.yaml
+
+#
+# examples:
+#
+# kx022_data: kx022-drv-data {
+#       compatible = "cros-ec,drvdata-kionix";
+#       status = "okay";
+# };
+#
diff --git a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-lis2dw12.yaml b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-lis2dw12.yaml
new file mode 100644
index 0000000000..25f47c7e96
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-lis2dw12.yaml
@@ -0,0 +1,18 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: LIS2DW12 driver data node
+
+compatible: "cros-ec,drvdata-lis2dw12"
+
+include: drvdata-base.yaml
+
+#
+# examples:
+#
+# lis2dw12_data: lis2dw12-drv-data {
+#        compatible = "cros-ec,drvdata-lis2dw12";
+#        status = "okay";
+# };
+#
diff --git a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-lsm6dsm.yaml b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-lsm6dsm.yaml
new file mode 100644
index 0000000000..66e6f32f60
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-lsm6dsm.yaml
@@ -0,0 +1,21 @@
+# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: LSM6DSM driver data node. Note this has to be
+  a separate instance for each sensor instance for this device
+  e.g if the device is used for both accel and gyro, then
+  separate instances of this driver data node must be used for each.
+
+compatible: "cros-ec,drvdata-lsm6dsm"
+
+include: drvdata-base.yaml
+
+#
+# examples:
+#
+# lsm6dsm_data: lsm6dsm-drv-data {
+#       compatible = "cros-ec,drvdata-lsm6dsm";
+#       status = "okay";
+# };
+#
diff --git a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-lsm6dso.yaml b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-lsm6dso.yaml
new file mode 100644
index 0000000000..57f2eedf01
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-lsm6dso.yaml
@@ -0,0 +1,21 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: LSM6DSO driver data node. Note this has to be
+  a separate instance for each sensor instance for this device
+  e.g if the device is used for both accel and gyro, then
+  separate instances of this driver data node must be used for each.
+
+compatible: "cros-ec,drvdata-lsm6dso"
+
+include: drvdata-base.yaml
+
+#
+# examples:
+#
+# lsm6dso_data: lsm6dso-drv-data {
+#       compatible = "cros-ec,drvdata-lsm6dso";
+#       status = "okay";
+# };
+#
diff --git a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-tcs3400-clear.yaml b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-tcs3400-clear.yaml
new file mode 100644
index 0000000000..6b234d4460
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-tcs3400-clear.yaml
@@ -0,0 +1,32 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: TCS3400 CLEAR driver data
+
+compatible: "cros-ec,drvdata-tcs3400-clear"
+
+include: drvdata-base.yaml
+
+#
+# examples:
+#
+# tcs_clear_data: tcs3400-clear-drv-data {
+#        compatible = "cros-ec,drvdata-tcs3400-clear";
+#        status = "okay";
+#
+#        als-drv-data {
+#                compatible = "cros-ec,accelgyro-als-drv-data";
+#                als-cal {
+#                        scale = <1>;
+#                        uscale = <0>;
+#                        offset = <0>;
+#                        als-channel-scale {
+#                        compatible = "cros-ec,accelgyro-als-channel-scale";
+#                                k-channel-scale = <1>;
+#                                cover-scale = <1>;
+#                        };
+#                };
+#        };
+# };
+#
diff --git a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-tcs3400-rgb.yaml b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-tcs3400-rgb.yaml
new file mode 100644
index 0000000000..b81a4d6d49
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-tcs3400-rgb.yaml
@@ -0,0 +1,21 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: TCS3400 RGB driver data
+
+compatible: "cros-ec,drvdata-tcs3400-rgb"
+
+include: drvdata-base.yaml
+
+child-binding:
+  description: saturation auto-adjustment
+  properties:
+    again:
+      type: int
+      required: false
+      description: Gain Scaling; must be value between 0 and 3
+    atime:
+      type: int
+      required: false
+      description: Acquisition Time, controlled by the ATIME register
diff --git a/zephyr/dts/bindings/motionsense/drvdata/drvdata-base.yaml b/zephyr/dts/bindings/motionsense/drvdata/drvdata-base.yaml
new file mode 100644
index 0000000000..b278f26ba3
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/drvdata/drvdata-base.yaml
@@ -0,0 +1,11 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# common fields for driver data
+
+include: base.yaml
+
+properties:
+  status:
+    required: true
diff --git a/zephyr/dts/bindings/motionsense/motionsense-sensor-base.yaml b/zephyr/dts/bindings/motionsense/motionsense-sensor-base.yaml
new file mode 100644
index 0000000000..c5ef4ba192
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/motionsense-sensor-base.yaml
@@ -0,0 +1,80 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Common fields for motion sensors
+
+include: base.yaml
+
+properties:
+  status:
+    required: true
+  active-mask:
+    type: string
+    description: indicates system power state for sensor to be active
+    enum:
+      - "SENSOR_ACTIVE_S5"
+      - "SENSOR_ACTIVE_S3"
+      - "SENSOR_ACTIVE_S0"
+      - "SENSOR_ACTIVE_S0_S3"
+      - "SENSOR_ACTIVE_S0_S3_S5"
+    default: "SENSOR_ACTIVE_S0_S3"
+  location:
+    type: string
+    required: true
+    description: location of the motion sensor
+    enum:
+      - "MOTIONSENSE_LOC_BASE"
+      - "MOTIONSENSE_LOC_LID"
+      - "MOTIONSENSE_LOC_CAMERA"
+  mutex:
+    type: phandle
+    required: false
+    description: mutex used by chip driver
+  port:
+    type: phandle
+    required: false
+    description: phandle to the named i2c port
+  rot-standard-ref:
+    type: phandle
+    required: false
+    description: phandle to 3x3 rotation matrix
+  default-range:
+    type: int
+    required: false
+    description: default range of sensor read
+  drv-data:
+    type: phandle
+    required: false
+    description: phandle to driver data to be used for the motion sensor.
+      Some drivers require this to be a global shared datas structure
+      used by all instances of this device, others require separate
+      data structures for each instance.
+  alternate-for:
+    type: phandle
+    description: phandle to another sensor that can be swapped with this one
+      at runtime.
+  alternate-ssfc-indicator:
+    type: phandle
+    description: phandle to CBI SSFC value indicating that the sensor
+      should be used
+  int-signal:
+    type: phandle
+    description: pin which triggers interrupt for sensor
+
+#
+# examples:
+#
+# lid_accel: lid-accel {
+#           compatible = "cros-ec,bma255";
+#           status = "okay";
+#
+#           active-mask = "SENSOR_ACTIVE_S0_S3";
+#           location = "MOTIONSENSE_LOC_LID";
+#           mutex = <&mutex_bma255>;
+#           port = <&i2c_sensor>;
+#           rot-standard-ref = <&lid_rot_ref>;
+#           default-range = <2>;
+#           drv-data = <&bma255_data>;
+# };
+#
diff --git a/zephyr/dts/bindings/pmic/mps,mp2964.yaml b/zephyr/dts/bindings/pmic/mps,mp2964.yaml
new file mode 100644
index 0000000000..57017992a7
--- /dev/null
+++ b/zephyr/dts/bindings/pmic/mps,mp2964.yaml
@@ -0,0 +1,9 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: MPS MP2964 Power Management IC
+
+compatible: "mps,mp2964"
+
+include: i2c-device.yaml
diff --git a/zephyr/dts/bindings/power/ap-pwrseq-sub-states.yaml b/zephyr/dts/bindings/power/ap-pwrseq-sub-states.yaml
new file mode 100644
index 0000000000..8632b7e7b5
--- /dev/null
+++ b/zephyr/dts/bindings/power/ap-pwrseq-sub-states.yaml
@@ -0,0 +1,21 @@
+# Copyright 2022 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Define additional substates to be included in state machine. Use corresponding
+  macros to provide action handlers.
+compatible: "ap-pwrseq-sub-states"
+
+properties:
+  chipset:
+    type: string-array
+    required: false
+    description: |
+      User defined power subtstates, use AP_POWER_CHIPSET_SUB_STATE_DEFINE, to define
+      substate action handler functions.
+  application:
+    type: string-array
+    required: false
+    description: |
+      User defined power subtstates, use AP_POWER_APP_SUB_STATE_DEFINE, to define
+      substate action handler functions.
diff --git a/zephyr/dts/bindings/power/intel,ap-pwr-signal-base.yaml b/zephyr/dts/bindings/power/intel,ap-pwr-signal-base.yaml
new file mode 100644
index 0000000000..62968e0795
--- /dev/null
+++ b/zephyr/dts/bindings/power/intel,ap-pwr-signal-base.yaml
@@ -0,0 +1,41 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: |
+    The power signals are defined using different compatibles,
+    which configure the source of the signal (GPIO, VW, external etc.).
+    All signals use a common base enum-name so that the core code
+    can use consistent names.
+
+properties:
+  dbg-label:
+    type: string
+    required: true
+    description: Label of power signals used in debug messages
+
+  enum-name:
+    type: string
+    required: true
+    description: |
+      Enumeration values for power signals.
+      Keep in alphebetical order.
+    enum:
+    - PWR_ALL_SYS_PWRGD
+    - PWR_DSW_PWROK
+    - PWR_EC_PCH_RSMRST
+    - PWR_EC_PCH_SYS_PWROK
+    - PWR_EC_SOC_DSW_PWROK
+    - PWR_EN_PP3300_A
+    - PWR_EN_PP5000_A
+    - PWR_IMVP9_VRRDY
+    - PWR_PCH_PWROK
+    - PWR_PG_PP1P05
+    - PWR_RSMRST
+    - PWR_SLP_S0
+    - PWR_SLP_S3
+    - PWR_SLP_S4
+    - PWR_SLP_S5
+    - PWR_SLP_SUS
+    - PWR_SYS_RST
+    - PWR_VCCST_PWRGD
diff --git a/zephyr/dts/bindings/power/intel,ap-pwr-signal-emul.yaml b/zephyr/dts/bindings/power/intel,ap-pwr-signal-emul.yaml
new file mode 100644
index 0000000000..acc8c5698b
--- /dev/null
+++ b/zephyr/dts/bindings/power/intel,ap-pwr-signal-emul.yaml
@@ -0,0 +1,124 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: |
+  Power Signal Emulator Node
+
+  Power signal emulator allows executing AP Power Sequence in a virtual
+  environment by simulating power signals behavior.
+
+  This file defines a node to bind two or more power signals. A node connects
+  one input-signal with one or more output-signals. When a node is loaded and
+  initialized by power signal emulator, its input-signal state will control
+  the value of its children output-signals. Behavior of output-signals are
+  configurable to meet AP power sequence test cases.
+
+  Power Signals direction is determined from emulator node perspective. An input
+  signal in a node, is the one to be monitored by the emulator, while an output
+  signal gets its value altered when corresponding input signal's state changes.
+
+compatible: "intel,ap-pwr-signal-emul"
+
+properties:
+  input-signal:
+    type: phandle
+    required: true
+    description: |
+      Input signal whose value is monitored to control children output-signal`s
+      value.
+
+  assert-value:
+    type: int
+    required: false
+    default: 1
+    description: |
+      Value that indicates `input-signal` must be ASSERTED.
+
+      A power signal state can be ASSERTED or DEASSERTED.`input-signal` is only
+      considered asserted if its new value is equal to `assert-value`, any
+      other value makes it deasserted.
+
+  edge:
+    type: string
+    required: false
+    description: |
+      Controls when to trigger children value change, based on `input-signal`
+      new state.
+
+      EDGE_ACTIVE_ON_ASSERT: Children value changes only when `input-signal`
+        state changes into asserted.
+
+      EDGE_ACTIVE_ON_DEASSERT: Children value changes only when `input-signal`
+        state changes into deasserted.
+
+      EDGE_ACTIVE_ON_DEASSERT: Children value changes everytime `input-signal`
+        state changes.
+
+    default: EDGE_ACTIVE_ON_BOTH
+    enum:
+      - EDGE_ACTIVE_ON_ASSERT
+      - EDGE_ACTIVE_ON_DEASSERT
+      - EDGE_ACTIVE_ON_BOTH
+
+  init-value:
+    type: int
+    required: false
+    description: |
+      Initial value of `input-signal`.
+
+child-binding:
+  description: |
+    Child power signals configuration.
+
+  properties:
+    output-signal:
+      type: phandle
+      required: true
+      description: |
+        Output signal whose value will be controlled by parent `input-signal`
+        state.
+
+    assert-value:
+      type: int
+      required: false
+      default: 1
+      description: |
+        Value that will be assigned to this signal when parent `input-signal`
+        state is asserted.
+
+    assert-delay-ms:
+      type: int
+      required: false
+      default: 10
+      description: |
+        Milliseconds to delay setting this signal to its `assert-value`
+        after `input-signal` is asserted.
+
+    deassert-value:
+      type: int
+      required: false
+      default: 0
+      description: |
+        Value that will be assigned to this signal when parent `input-signal`
+        state is deasserted.
+
+    deassert-delay-ms:
+      type: int
+      required: false
+      default: 10
+      description: |
+        Milliseconds to delay setting this signal to its `deassert-value`
+        after `input-signal` is deasserted.
+
+    init-value:
+      type: int
+      required: false
+      description: |
+        Value set to this power signal when initializing this node.
+
+    invert-value:
+      type: boolean
+      description: |
+        Invert this power signal assertion logic, this applies to both values
+        and delays.
diff --git a/zephyr/dts/bindings/power/intel,ap-pwr-test-platform.yaml b/zephyr/dts/bindings/power/intel,ap-pwr-test-platform.yaml
new file mode 100644
index 0000000000..b1375406dd
--- /dev/null
+++ b/zephyr/dts/bindings/power/intel,ap-pwr-test-platform.yaml
@@ -0,0 +1,18 @@
+# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: |
+  Power Signal Test Platform
+
+  This is a virtual representation of platform comprised of one or more power
+  signal emulator nodes. Test platform is loaded into power signal emulator.
+
+compatible: "intel,ap-pwr-test-platform"
+
+properties:
+  nodes:
+    type: phandles
+    required: true
+    description: |
+       phandle array of power signals nodes to be run by emulator.
diff --git a/zephyr/dts/bindings/power/intel,ap-pwrseq-adc.yaml b/zephyr/dts/bindings/power/intel,ap-pwrseq-adc.yaml
new file mode 100644
index 0000000000..81f2bf9195
--- /dev/null
+++ b/zephyr/dts/bindings/power/intel,ap-pwrseq-adc.yaml
@@ -0,0 +1,20 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Power sequence analog signals container.
+
+compatible: "intel,ap-pwrseq-adc"
+
+include: intel,ap-pwr-signal-base.yaml
+
+properties:
+  trigger-high:
+    description: Rising edge trigger adc comparator
+    type: phandle
+    required: true
+
+  trigger-low:
+    description: Falling edge trigger adc comparator
+    type: phandle
+    required: true
diff --git a/zephyr/dts/bindings/power/intel,ap-pwrseq-external.yaml b/zephyr/dts/bindings/power/intel,ap-pwrseq-external.yaml
new file mode 100644
index 0000000000..e0258b0f7c
--- /dev/null
+++ b/zephyr/dts/bindings/power/intel,ap-pwrseq-external.yaml
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Node for externally supplied power signals
+
+compatible: "intel,ap-pwrseq-external"
+
+include: intel,ap-pwr-signal-base.yaml
diff --git a/zephyr/dts/bindings/power/intel,ap-pwrseq-gpio.yaml b/zephyr/dts/bindings/power/intel,ap-pwrseq-gpio.yaml
new file mode 100644
index 0000000000..c7edb9d2d0
--- /dev/null
+++ b/zephyr/dts/bindings/power/intel,ap-pwrseq-gpio.yaml
@@ -0,0 +1,30 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Node for power signal GPIO
+
+compatible: "intel,ap-pwrseq-gpio"
+
+include: intel,ap-pwr-signal-base.yaml
+properties:
+  gpios:
+    type: phandle-array
+    required: true
+    description: |
+      GPIO to be used for power signal. Input GPIOs can be
+      configured to generate an interrupt if the 'interrupt-flags'
+      property is set with the appropriate interrupt flags.
+
+  output:
+    type: boolean
+    description: Output GPIO. No interrupts used.
+
+  interrupt-flags:
+    type: int
+    required: false
+    description: GPIO interrupt configuration flags.
+
+  no-enable:
+    type: boolean
+    description: Do not enable interrupt on start-up
diff --git a/zephyr/dts/bindings/power/intel,ap-pwrseq-vw.yaml b/zephyr/dts/bindings/power/intel,ap-pwrseq-vw.yaml
new file mode 100644
index 0000000000..099d17cb27
--- /dev/null
+++ b/zephyr/dts/bindings/power/intel,ap-pwrseq-vw.yaml
@@ -0,0 +1,28 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Node for eSPI virtual wire power signal
+
+compatible: "intel,ap-pwrseq-vw"
+
+include: intel,ap-pwr-signal-base.yaml
+properties:
+  virtual-wire:
+    type: string
+    required: true
+    description: |
+      Enumeration value to eSPI signals that can be sent
+      or received through virtual wire channel
+
+    enum:
+    - ESPI_VWIRE_SIGNAL_SLP_S3
+    - ESPI_VWIRE_SIGNAL_SLP_S4
+    - ESPI_VWIRE_SIGNAL_SLP_S5
+
+  vw-invert:
+    type: boolean
+    description: |
+      Only used for virtual wire nodes.
+      If set, the virtual wire signal is inverted before
+      being returned.
diff --git a/zephyr/dts/bindings/power/intel,ap-pwrseq.yaml b/zephyr/dts/bindings/power/intel,ap-pwrseq.yaml
new file mode 100644
index 0000000000..63734e5d40
--- /dev/null
+++ b/zephyr/dts/bindings/power/intel,ap-pwrseq.yaml
@@ -0,0 +1,90 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: |
+    Common fields for AP power sequence configuration
+    The configuration consists of a number of mostly timing
+    related values.
+
+compatible: "intel,ap-pwrseq"
+
+properties:
+  dsw-pwrok-delay:
+    type: int
+    required: false
+    default: 10
+    description: |
+      Delay to set DSW_PWROK high to PCH after 3.3V rail stable,
+      in milliseconds.
+
+  rsmrst-delay:
+    type: int
+    required: false
+    default: 10
+    description: |
+      Delay to set RSMRST from EC to SoC, in milliseconds.
+
+  sys-pwrok-delay:
+    type: int
+    required: false
+    default: 45
+    description: |
+      Delay from PG_EC_ALL_SYS_PWRGD high to set EC_PCH_SYS_PWROK high,
+      in milliseconds.
+
+  pm-pwrbtn-delay:
+    type: int
+    required: false
+    default: 200
+    description: |
+      Power button delay, in milliseconds.
+
+  pch-pwrok-delay:
+    type: int
+    required: false
+    default: 2
+    description: |
+      Delay in ms from IMVP9_VRRDY high to PCH_PWROK high delay.
+
+  vccst-pwrgd-delay:
+    type: int
+    required: false
+    default: 2
+    description: |
+      Delay in ms from PG_EC_ALL_SYS_PWRGD high
+      to VCCST_PWRGD high.
+
+  sys-reset-delay:
+    type: int
+    required: false
+    default: 32
+    description: Debounce time for SYS_RESET_L.
+
+  vrrdy-timeout:
+    type: int
+    required: false
+    default: 50
+    description: |
+      Timeout in ms for IMVP9_VRRDY high.
+
+  all-sys-pwrgd-timeout:
+    type: int
+    required: false
+    default: 0
+    description: |
+      Timeout in ms for ALL_SYS_PWRGD input to EC to be high.
+
+  wait-signal-timeout:
+    type: int
+    required: false
+    default: 1000
+    description: |
+      Timeout in ms for monitoring power signals.
+
+  s5-inactivity-timeout:
+    type: int
+    required: false
+    default: 10
+    description: |
+      Timeout in seconds for dropping back from S5 to G3.
diff --git a/zephyr/dts/bindings/switchcap/cros-ec,switchcap-gpio.yaml b/zephyr/dts/bindings/switchcap/cros-ec,switchcap-gpio.yaml
new file mode 100644
index 0000000000..344738c8c0
--- /dev/null
+++ b/zephyr/dts/bindings/switchcap/cros-ec,switchcap-gpio.yaml
@@ -0,0 +1,22 @@
+description: SwitchCap controlled by gpios
+
+compatible: "cros-ec,switchcap-gpio"
+
+properties:
+  enable-pin:
+    type: phandle
+    required: true
+    description: |
+      GPIO used to enable the switch cap
+
+  power-good-pin:
+    type: phandle
+    required: false
+    description: |
+      GPIO used to read if power is good
+
+  poff-delay-ms:
+    type: int
+    required: false
+    description: |
+      Additional power off delay required for some systems
diff --git a/zephyr/dts/bindings/switchcap/lion,ln9310.yaml b/zephyr/dts/bindings/switchcap/lion,ln9310.yaml
new file mode 100644
index 0000000000..c1c4a99bee
--- /dev/null
+++ b/zephyr/dts/bindings/switchcap/lion,ln9310.yaml
@@ -0,0 +1,28 @@
+description: SwitchCap controlled by Lion Semiconductor LN9310
+
+compatible: "lion,ln9310"
+
+properties:
+  enable-pin:
+    type: phandle
+    required: true
+    description: |
+      GPIO used to enable the switch cap. Relies on
+      GPIO flags to determine active low or high.
+
+  port:
+    type: phandle
+    required: true
+    description: |
+      I2C port used to communicate with controller
+
+  addr-flags:
+    type: string
+    default: "LN9310_I2C_ADDR_0_FLAGS"
+    enum:
+      - "LN9310_I2C_ADDR_0_FLAGS"
+      - "LN9310_I2C_ADDR_1_FLAGS"
+      - "LN9310_I2C_ADDR_2_FLAGS"
+      - "LN9310_I2C_ADDR_3_FLAGS"
+    description: |
+      I2C address of controller
diff --git a/zephyr/dts/bindings/temp/amd,sb-tsi.yaml b/zephyr/dts/bindings/temp/amd,sb-tsi.yaml
new file mode 100644
index 0000000000..f99c01081a
--- /dev/null
+++ b/zephyr/dts/bindings/temp/amd,sb-tsi.yaml
@@ -0,0 +1,10 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: >
+  Properties for an Side Band Temperature Sensor Interface sensor
+
+compatible: "amd,sb-tsi"
+
+include: i2c-device.yaml
diff --git a/zephyr/dts/bindings/temp/cros-ec,temp-sensor-amdr23m.yaml b/zephyr/dts/bindings/temp/cros-ec,temp-sensor-amdr23m.yaml
new file mode 100644
index 0000000000..c64c547027
--- /dev/null
+++ b/zephyr/dts/bindings/temp/cros-ec,temp-sensor-amdr23m.yaml
@@ -0,0 +1,10 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: >
+  Properties for a AMD R23M I2C temperature sensor
+
+compatible: "cros-ec,temp-sensor-amdr23m"
+
+include: i2c-device.yaml
diff --git a/zephyr/dts/bindings/temp/cros-ec,temp-sensor-f75303.yaml b/zephyr/dts/bindings/temp/cros-ec,temp-sensor-f75303.yaml
new file mode 100644
index 0000000000..30a6d9ebc9
--- /dev/null
+++ b/zephyr/dts/bindings/temp/cros-ec,temp-sensor-f75303.yaml
@@ -0,0 +1,24 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: >
+  Properties for a F75303 I2C temperature sensor
+
+compatible: "cros-ec,temp-sensor-f75303"
+
+include: i2c-device.yaml
+
+properties:
+  temperature-type:
+    type: string
+    required: true
+    description:
+      One temperature sensor have three sensor type.
+    enum:
+      - F75303_IDX_LOCAL
+      - F75303_IDX_REMOTE1
+      - F75303_IDX_REMOTE2
+      - F75303_IDX_GPU_LOCAL
+      - F75303_IDX_GPU_REMOTE1
+      - F75303_IDX_GPU_REMOTE2
diff --git a/zephyr/dts/bindings/temp/cros-ec,temp-sensor-thermistor.yaml b/zephyr/dts/bindings/temp/cros-ec,temp-sensor-thermistor.yaml
new file mode 100644
index 0000000000..00575eb6e8
--- /dev/null
+++ b/zephyr/dts/bindings/temp/cros-ec,temp-sensor-thermistor.yaml
@@ -0,0 +1,18 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: >
+  Properties for a thermistor temperature sensor
+
+compatible: "cros-ec,temp-sensor-thermistor"
+
+properties:
+  adc:
+    required: true
+    type: phandle
+    description: The named adc channel
+
+  thermistor:
+    type: phandle
+    description: Underlying thermistor device
diff --git a/zephyr/dts/bindings/temp/cros-ec,temp-sensor-tmp112.yaml b/zephyr/dts/bindings/temp/cros-ec,temp-sensor-tmp112.yaml
new file mode 100644
index 0000000000..43ab9386c9
--- /dev/null
+++ b/zephyr/dts/bindings/temp/cros-ec,temp-sensor-tmp112.yaml
@@ -0,0 +1,10 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: >
+  Properties for a TMP112 I2C temperature sensor
+
+compatible: "cros-ec,temp-sensor-tmp112"
+
+include: i2c-device.yaml
diff --git a/zephyr/dts/bindings/temp/cros-ec,temp-sensors.yaml b/zephyr/dts/bindings/temp/cros-ec,temp-sensors.yaml
new file mode 100644
index 0000000000..66c5bc955a
--- /dev/null
+++ b/zephyr/dts/bindings/temp/cros-ec,temp-sensors.yaml
@@ -0,0 +1,74 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: >
+  Common properties for temperature sensors that are not handled by drivers.
+  Zero values in degrees K(-273 in degrees C)in thermal thresholds will
+  be ignored
+
+compatible: "cros-ec,temp-sensors"
+
+child-binding:
+  description: Named temperature sensor node
+  properties:
+    sensor:
+      type: phandle
+      required: true
+      description:
+        A pointer to a coresponding temperature sensor node.
+
+    power-good-pin:
+      type: phandle
+      description:
+        If this sensor will be unpowered some of the time, provide an input GPIO
+        which can be referenced to detect whether the sensor is powered before
+        reading.
+
+    temp_fan_off:
+      type: int
+      description:
+        Temperature threshold in degrees C when no active cooling
+        is needed
+
+    temp_fan_max:
+      type: int
+      description:
+        Temperature threshold in degrees C when max active cooling
+        is needed
+
+    temp_host_warn:
+      type: int
+      description:
+        Temperature threshold in degrees C of thermal warn.
+        Temperatures above the thermal warn threshold generate a
+        request to the AP to throttle itself.
+
+    temp_host_high:
+      type: int
+      description:
+        Temperature threshold in degrees C of thermal high.
+        Temperatures above the thermal high threshold cause the EC to
+        assert a signal (usually PROCHOT) to the AP and force the AP to
+        throttle.
+
+    temp_host_halt:
+      type: int
+      description:
+        Temperature threshold in degrees C that forces AP to shutdown
+        due to thermal reason
+
+    temp_host_release_warn:
+      type: int
+      description:
+        Temperature release threshold in degrees C of thermal warn
+
+    temp_host_release_high:
+      type: int
+      description:
+        Temperature release threshold in degrees C of thermal high
+
+    temp_host_release_halt:
+      type: int
+      description:
+        Temperature release threshold in degrees C of thermal shutdown
diff --git a/zephyr/dts/bindings/temp/cros-ec,thermistor.yaml b/zephyr/dts/bindings/temp/cros-ec,thermistor.yaml
new file mode 100644
index 0000000000..3121f8a95f
--- /dev/null
+++ b/zephyr/dts/bindings/temp/cros-ec,thermistor.yaml
@@ -0,0 +1,57 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# For more information:
+# https://www.electronics-tutorials.ws/io/thermistors.html
+
+description: Common properties for thermistors
+
+compatible: "cros-ec,thermistor"
+
+properties:
+  scaling-factor:
+    required: true
+    type: int
+    description: Scaling factor for voltage pairs
+
+  num-pairs:
+    required: true
+    type: int
+    description: Number of sample data points for linear interpolation
+
+  steinhart-reference-mv:
+    required: true
+    type: int
+    description: >
+      Used only for testing.
+      Is the reference voltage for temperature 25C.
+
+  steinhart-reference-res:
+    required: true
+    type: int
+    description: >
+      Used only for testing.
+      Is the reference resistance for temperature 25C.
+
+child-binding:
+  description: >
+    Data samples derived from Steinhart-Hart
+    equation in a resistor divider circuit.
+    Used in linear interpolation.
+
+  properties:
+    milivolt:
+      type: int
+      required: true
+      description: Voltage reading for a given temperature sample
+
+    temp:
+      type: int
+      required: true
+      description: Temperature (Celcius) in a sample
+
+    sample-index:
+      type: int
+      required: true
+      description: The index of a datum to maintain sample order to interpolate.
diff --git a/zephyr/dts/bindings/temp/nxp,pct2075.yaml b/zephyr/dts/bindings/temp/nxp,pct2075.yaml
new file mode 100644
index 0000000000..bca7f7125b
--- /dev/null
+++ b/zephyr/dts/bindings/temp/nxp,pct2075.yaml
@@ -0,0 +1,10 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: >
+  Properties for a PCT2075 I2C temperature sensor
+
+compatible: "nxp,pct2075"
+
+include: i2c-device.yaml
diff --git a/zephyr/dts/bindings/touchpad/elan,ekth3000.yaml b/zephyr/dts/bindings/touchpad/elan,ekth3000.yaml
new file mode 100644
index 0000000000..531ae240b6
--- /dev/null
+++ b/zephyr/dts/bindings/touchpad/elan,ekth3000.yaml
@@ -0,0 +1,15 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Elan I2C touchpad
+
+compatible: "elan,ekth3000"
+
+include: i2c-device.yaml
+
+properties:
+  irq:
+    type: phandle
+    required: true
+    description: Interrupt from touchpad
diff --git a/zephyr/dts/bindings/usbc/bc12/pericom,pi3usb9201.yaml b/zephyr/dts/bindings/usbc/bc12/pericom,pi3usb9201.yaml
new file mode 100644
index 0000000000..841c443877
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/bc12/pericom,pi3usb9201.yaml
@@ -0,0 +1,11 @@
+description: USBC BC1.2
+
+compatible: "pericom,pi3usb9201"
+
+include: base.yaml
+
+properties:
+  irq:
+    type: phandles
+    description: |
+        GPIO interrupt from BC1.2
diff --git a/zephyr/dts/bindings/usbc/bc12/richtek,rt1718s-bc12.yaml b/zephyr/dts/bindings/usbc/bc12/richtek,rt1718s-bc12.yaml
new file mode 100644
index 0000000000..6a93e78496
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/bc12/richtek,rt1718s-bc12.yaml
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: USBC RT1718S BC1.2
+
+compatible: "richtek,rt1718s-bc12"
+
+include: base.yaml
diff --git a/zephyr/dts/bindings/usbc/bc12/richtek,rt1739-bc12.yaml b/zephyr/dts/bindings/usbc/bc12/richtek,rt1739-bc12.yaml
new file mode 100644
index 0000000000..aef959bea8
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/bc12/richtek,rt1739-bc12.yaml
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: USBC BC1.2
+
+compatible: "richtek,rt1739-bc12"
+
+include: base.yaml
diff --git a/zephyr/dts/bindings/usbc/cros-ec,usb-mux-chain.yaml b/zephyr/dts/bindings/usbc/cros-ec,usb-mux-chain.yaml
new file mode 100644
index 0000000000..398d7255ac
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/cros-ec,usb-mux-chain.yaml
@@ -0,0 +1,47 @@
+# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: USB-C muxes chain
+
+compatible: "cros-ec,usb-mux-chain"
+
+properties:
+  usb-muxes:
+    type: phandles
+    required: true
+    description: |
+      List of USB-C muxes and retimers for the USB-C port. The USB-C subsystem
+      traverses this list in the order specified. The phandles are references to
+      cros-ec,usbc-mux nodes. Link this mux chain with a specific USB-C port by
+      adding the "cros-ec,usb-mux-chain" as a child of the "named-usbc-port"
+      node.
+
+  alternative-chain:
+    type: boolean
+    description: |
+      Set if this is alternative USB-C muxes chain. It can be selected in
+      runtime using USB_MUX_ENABLE_ALTERNATIVE macro.
+
+# Example DTS defining USB-C port 0 with main and alternative usb mux chains.
+# The main chain has two muxes: BB retimer and virtual mux.
+# The alternative chain has three muxes: BB retimer, SOC side BB retimer and
+# virtual mux.
+#
+#       usbc_port0: port0@0 {
+#               compatible = "named-usbc-port";
+#               reg = <0>;
+#               ...
+#               usb-mux-chain-0 {
+#                       compatible = "cros-ec,usb-mux-chain";
+#                       usb-muxes = <&usb_c0_bb_retimer
+#                                    &virtual_mux_c0>;
+#               };
+#               usb-mux-chain-0 {
+#                       compatible = "cros-ec,usb-mux-chain";
+#                       alternative-chain;
+#                       usb-muxes = <&usb_c0_bb_retimer
+#                                    &usb_c0_soc_side_bb_retimer
+#                                    &virtual_mux_c0>;
+#               };
+#       };
diff --git a/zephyr/dts/bindings/usbc/mux/amd,usbc-mux-amd-fp6.yaml b/zephyr/dts/bindings/usbc/mux/amd,usbc-mux-amd-fp6.yaml
new file mode 100644
index 0000000000..1ce1db82c7
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/mux/amd,usbc-mux-amd-fp6.yaml
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: USB-C AMD-FP6 mux
+
+include: ["i2c-device.yaml", "cros-ec,usbc-mux.yaml"]
+
+compatible: "amd,usbc-mux-amd-fp6"
diff --git a/zephyr/dts/bindings/usbc/mux/analogix,anx7452.yaml b/zephyr/dts/bindings/usbc/mux/analogix,anx7452.yaml
new file mode 100644
index 0000000000..3e36f92286
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/mux/analogix,anx7452.yaml
@@ -0,0 +1,19 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: |
+  Analogix re-timing MUX
+
+include: ["i2c-device.yaml", "cros-ec,usbc-mux.yaml"]
+
+compatible: "analogix,anx7452"
+
+properties:
+  usb-en-pin:
+    type: phandle
+    required: true
+
+  dp-en-pin:
+    type: phandle
+    required: false
diff --git a/zephyr/dts/bindings/usbc/mux/analogix,anx7483.yaml b/zephyr/dts/bindings/usbc/mux/analogix,anx7483.yaml
new file mode 100644
index 0000000000..c4ac7782f0
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/mux/analogix,anx7483.yaml
@@ -0,0 +1,10 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: |
+  Analogix re-timing MUX
+
+include: ["i2c-device.yaml", "cros-ec,usbc-mux.yaml"]
+
+compatible: "analogix,anx7483"
diff --git a/zephyr/dts/bindings/usbc/mux/analogix,usbc-mux-anx7447.yaml b/zephyr/dts/bindings/usbc/mux/analogix,usbc-mux-anx7447.yaml
new file mode 100644
index 0000000000..25b042e28c
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/mux/analogix,usbc-mux-anx7447.yaml
@@ -0,0 +1,15 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: USBC ANX7447 USB MUX
+
+include: cros-ec,usbc-mux.yaml
+
+compatible: "analogix,usbc-mux-anx7447"
+
+properties:
+  hpd-update-enable:
+    type: boolean
+    description: |
+      Enable anx7447 hpd update callback
diff --git a/zephyr/dts/bindings/usbc/mux/cros-ec,usbc-mux-tcpci.yaml b/zephyr/dts/bindings/usbc/mux/cros-ec,usbc-mux-tcpci.yaml
new file mode 100644
index 0000000000..548d510630
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/mux/cros-ec,usbc-mux-tcpci.yaml
@@ -0,0 +1,18 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: USBC TCPC USB MUX
+
+# Include base.yaml instead of i2c-device.yaml because the reg property is not
+# required for this node.
+include: ["base.yaml", "cros-ec,usbc-mux.yaml"]
+
+compatible: "cros-ec,usbc-mux-tcpci"
+
+properties:
+  hpd-update:
+    type: string
+    required: false
+    description: |
+      Name of function used as hpd_update callback
diff --git a/zephyr/dts/bindings/usbc/mux/cros-ec,usbc-mux-virtual.yaml b/zephyr/dts/bindings/usbc/mux/cros-ec,usbc-mux-virtual.yaml
new file mode 100644
index 0000000000..7231bc9e2c
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/mux/cros-ec,usbc-mux-virtual.yaml
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: USB-C Virtual USB MUX
+
+include: cros-ec,usbc-mux.yaml
+
+compatible: "cros-ec,usbc-mux-virtual"
diff --git a/zephyr/dts/bindings/usbc/mux/cros-ec,usbc-mux.yaml b/zephyr/dts/bindings/usbc/mux/cros-ec,usbc-mux.yaml
new file mode 100644
index 0000000000..0e76f548a9
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/mux/cros-ec,usbc-mux.yaml
@@ -0,0 +1,25 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Common properties for USB-C mux
+
+properties:
+  flags:
+    type: int
+    required: false
+    default: 0
+    description: |
+      Mask of flags defined in dt-bindings/usbc_mux.h
+
+  board-init:
+    type: string
+    required: false
+    description: |
+      Name of function used as board_init callback
+
+  board-set:
+    type: string
+    required: false
+    description: |
+      Name of function used as board_set callback
diff --git a/zephyr/dts/bindings/usbc/mux/intel,jhl8040r.yaml b/zephyr/dts/bindings/usbc/mux/intel,jhl8040r.yaml
new file mode 100644
index 0000000000..a16d1d25a7
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/mux/intel,jhl8040r.yaml
@@ -0,0 +1,22 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Intel JHL8040R Thunderbolt 4 Retimer
+
+compatible: "intel,jhl8040r"
+
+include: ["i2c-device.yaml", "cros-ec,usbc-mux.yaml"]
+
+properties:
+  reset-pin:
+    type: phandle
+    required: true
+
+  int-pin:
+    type: phandle
+    required: false
+
+  ls-en-pin:
+    type: phandle
+    required: false
diff --git a/zephyr/dts/bindings/usbc/mux/intel,jhl9040r.yaml b/zephyr/dts/bindings/usbc/mux/intel,jhl9040r.yaml
new file mode 100644
index 0000000000..817897ed94
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/mux/intel,jhl9040r.yaml
@@ -0,0 +1,22 @@
+# Copyright 2022 Google LLC
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Intel JHL9040R Thunderbolt 4 Retimer
+
+compatible: "intel,jhl9040r"
+
+include: ["i2c-device.yaml", "cros-ec,usbc-mux.yaml"]
+
+properties:
+  reset-pin:
+    type: phandle
+    required: true
+
+  int-pin:
+    type: phandle
+    required: false
+
+  ls-en-pin:
+    type: phandle
+    required: false
diff --git a/zephyr/dts/bindings/usbc/mux/ite,it5205.yaml b/zephyr/dts/bindings/usbc/mux/ite,it5205.yaml
new file mode 100644
index 0000000000..3c9381aee1
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/mux/ite,it5205.yaml
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: ITE IT5205 USB Type-C 3:2 alternate mode MUX
+
+include: ["i2c-device.yaml", "cros-ec,usbc-mux.yaml"]
+
+compatible: "ite,it5205"
diff --git a/zephyr/dts/bindings/usbc/mux/kandou,kb8010.yaml b/zephyr/dts/bindings/usbc/mux/kandou,kb8010.yaml
new file mode 100644
index 0000000000..055135f803
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/mux/kandou,kb8010.yaml
@@ -0,0 +1,17 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description:  Kandou re-timing MUX
+
+include: ["i2c-device.yaml", "cros-ec,usbc-mux.yaml"]
+
+compatible: "kandou,kb8010"
+
+properties:
+  reset-pin:
+    type: phandle
+    required: true
+
+  int-pin:
+    type: phandle
diff --git a/zephyr/dts/bindings/usbc/mux/parade,ps8743.yaml b/zephyr/dts/bindings/usbc/mux/parade,ps8743.yaml
new file mode 100644
index 0000000000..1ee0bbaf74
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/mux/parade,ps8743.yaml
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Parade PS8743 USB Type-C alternate mode MUX
+
+include: ["i2c-device.yaml", "cros-ec,usbc-mux.yaml"]
+
+compatible: "parade,ps8743"
diff --git a/zephyr/dts/bindings/usbc/mux/parade,ps8818.yaml b/zephyr/dts/bindings/usbc/mux/parade,ps8818.yaml
new file mode 100644
index 0000000000..aafdf29341
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/mux/parade,ps8818.yaml
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: USBC PS8818 Retimer
+
+include: ["i2c-device.yaml", "cros-ec,usbc-mux.yaml"]
+
+compatible: "parade,ps8818"
diff --git a/zephyr/dts/bindings/usbc/mux/parade,usbc-mux-ps8xxx.yaml b/zephyr/dts/bindings/usbc/mux/parade,usbc-mux-ps8xxx.yaml
new file mode 100644
index 0000000000..4df0b35d76
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/mux/parade,usbc-mux-ps8xxx.yaml
@@ -0,0 +1,17 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: USBC PS8xxx USB MUX
+
+include: cros-ec,usbc-mux-tcpci.yaml
+
+compatible: "parade,usbc-mux-ps8xxx"
+
+properties:
+  hpd-update:
+    description: |
+      PS8xxx USB MUX almost always use this hdp_update callback
+    default: "ps8xxx_tcpc_update_hpd_status"
+    enum:
+      - ps8xxx_tcpc_update_hpd_status
diff --git a/zephyr/dts/bindings/usbc/mux/ti,tusb1064.yaml b/zephyr/dts/bindings/usbc/mux/ti,tusb1064.yaml
new file mode 100644
index 0000000000..d5a0b34e6c
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/mux/ti,tusb1064.yaml
@@ -0,0 +1,11 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: |
+  TI TUSB546, TUSB1044, or TUSB1064 USB-C MUX, device variant depends on
+  CONFIG_PLATFORM_EC_USB_MUX_TUSB_TYPE Kconfig choice
+
+include: ["i2c-device.yaml", "cros-ec,usbc-mux.yaml"]
+
+compatible: "ti,tusb1064"
diff --git a/zephyr/dts/bindings/usbc/named-usbc-port.yaml b/zephyr/dts/bindings/usbc/named-usbc-port.yaml
new file mode 100644
index 0000000000..7a03b92657
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/named-usbc-port.yaml
@@ -0,0 +1,60 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: |
+  Named USB-C port node
+
+  Example:
+        usbc {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                /* Reg property is used to assign a port number */
+                port0@0 {
+                        compatible = "named-usbc-port";
+                        reg = <0>;
+                        bc12 = <&bc12_port0>;
+                };
+                port1@1 {
+                        compatible = "named-usbc-port";
+                        reg = <1>;
+                        bc12 = <&bc12_port1>;
+                };
+                };
+
+compatible: "named-usbc-port"
+
+include: base.yaml
+
+properties:
+  bc12:
+    type: phandle
+    required: false
+    description: |
+      BC1.2 chip for the USB-C port.
+  tcpc:
+    type: phandle
+    required: false
+    description: |
+      TCPC chip for the USB-C port.
+  chg:
+    type: phandle
+    required: false
+    description: |
+      Charger chip for the USB-C port.
+  chg_alt:
+    type: phandle
+    required: false
+    description: |
+      Alternative charger for the USB-C port.
+  ppc:
+    type: phandle
+    required: false
+    description: |
+      PPC for the USB-C port.
+  ppc_alt:
+    type: phandle
+    required: false
+    description: |
+      Alternate PPC for the USB-C port.
diff --git a/zephyr/dts/bindings/usbc/ppc-chip.yaml b/zephyr/dts/bindings/usbc/ppc-chip.yaml
new file mode 100644
index 0000000000..a4e7ad0ec0
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/ppc-chip.yaml
@@ -0,0 +1,25 @@
+# Copyright 2021 The ChromiumOS Authors
+# SPDX-License-Identifier: Apache-2.0
+
+description: Power path chip
+
+properties:
+
+  irq:
+    type: phandles
+    required: false
+    description: |
+      GPIO interrupt from PPC using a named-gpios child node
+
+  is-alt:
+    type: boolean
+    required: false
+    description: |
+      If present, this node refers to an altnerate PPC device. The PPC device
+      is not used by default, and must be manually enabled at runtime.
+
+  irq-gpios:
+    type: phandle-array
+    required: false
+    description: |
+      Interrupt line from the PPC (zephyr standard GPIO format)
diff --git a/zephyr/dts/bindings/usbc/ppc/aoz,aoz1380.yaml b/zephyr/dts/bindings/usbc/ppc/aoz,aoz1380.yaml
new file mode 100644
index 0000000000..52144ffc78
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/ppc/aoz,aoz1380.yaml
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: AOZ1380 USBC PPC binding
+
+compatible: "aoz,aoz1380"
+
+include: ppc-chip.yaml
diff --git a/zephyr/dts/bindings/usbc/ppc/kinetic,ktu1125.yaml b/zephyr/dts/bindings/usbc/ppc/kinetic,ktu1125.yaml
new file mode 100644
index 0000000000..104d81e340
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/ppc/kinetic,ktu1125.yaml
@@ -0,0 +1,5 @@
+description: USBC PPC
+
+compatible: "kinetic,ktu1125"
+
+include: ["i2c-device.yaml", "ppc-chip.yaml"]
diff --git a/zephyr/dts/bindings/usbc/ppc/nxp,nx20p348x.yaml b/zephyr/dts/bindings/usbc/ppc/nxp,nx20p348x.yaml
new file mode 100644
index 0000000000..643a9306e1
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/ppc/nxp,nx20p348x.yaml
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: NXP NX20P348X USBC PPC binding
+
+compatible: "nxp,nx20p348x"
+
+include: ["i2c-device.yaml", "ppc-chip.yaml"]
diff --git a/zephyr/dts/bindings/usbc/ppc/richtek,rt1739-ppc.yaml b/zephyr/dts/bindings/usbc/ppc/richtek,rt1739-ppc.yaml
new file mode 100644
index 0000000000..e79b932979
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/ppc/richtek,rt1739-ppc.yaml
@@ -0,0 +1,15 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: USBC PPC
+
+compatible: "richtek,rt1739-ppc"
+
+include: ["i2c-device.yaml", "ppc-chip.yaml"]
+
+properties:
+  frs_en_gpio:
+    type: phandle
+    description: The GPIO that controls FRS enable on this device
+    required: false
diff --git a/zephyr/dts/bindings/usbc/ppc/silergy,syv682x.yaml b/zephyr/dts/bindings/usbc/ppc/silergy,syv682x.yaml
new file mode 100644
index 0000000000..16c6e4e5b9
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/ppc/silergy,syv682x.yaml
@@ -0,0 +1,11 @@
+description: USBC PPC
+
+compatible: "silergy,syv682x"
+
+include: ["i2c-device.yaml", "ppc-chip.yaml"]
+
+properties:
+  frs_en_gpio:
+    type: phandle
+    description: The GPIO that controls FRS enable on this device
+    required: false
diff --git a/zephyr/dts/bindings/usbc/ppc/ti,sn5s330.yaml b/zephyr/dts/bindings/usbc/ppc/ti,sn5s330.yaml
new file mode 100644
index 0000000000..48e5e9b5ba
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/ppc/ti,sn5s330.yaml
@@ -0,0 +1,5 @@
+description: USBC PPC
+
+compatible: "ti,sn5s330"
+
+include: ["i2c-device.yaml", "ppc-chip.yaml"]
diff --git a/zephyr/dts/bindings/usbc/tcpc/analogix,anx7447-tcpc.yaml b/zephyr/dts/bindings/usbc/tcpc/analogix,anx7447-tcpc.yaml
new file mode 100644
index 0000000000..aac15ad3cf
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/tcpc/analogix,anx7447-tcpc.yaml
@@ -0,0 +1,22 @@
+description: Analogix ANX7447 USBC TCPC binding
+
+compatible: "analogix,anx7447-tcpc"
+
+include: ["i2c-device.yaml", "cros-ec,tcpci.yaml"]
+
+properties:
+  tcpc-flags:
+    type: int
+    default: 0
+    description: |
+      TCPC configuration flags
+  irq-gpios:
+    type: phandle-array
+    required: false
+    description: |
+      Interrupt from TCPC
+  rst-gpios:
+    type: phandle-array
+    required: false
+    description: |
+      TCPC reset line
diff --git a/zephyr/dts/bindings/usbc/tcpc/cros-ec,tcpci.yaml b/zephyr/dts/bindings/usbc/tcpc/cros-ec,tcpci.yaml
new file mode 100644
index 0000000000..29bd02bd2d
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/tcpc/cros-ec,tcpci.yaml
@@ -0,0 +1,13 @@
+description: USBC TCPC
+
+compatible: "cros-ec,tcpci"
+
+include: i2c-device.yaml
+
+properties:
+  is-alt:
+    type: boolean
+    required: false
+    description: |
+      If present, this node refers to an alternate TCPC device. The TCPC device
+      is not used by default, and must be manually enabled at runtime.
diff --git a/zephyr/dts/bindings/usbc/tcpc/cypress,ccgxxf.yaml b/zephyr/dts/bindings/usbc/tcpc/cypress,ccgxxf.yaml
new file mode 100644
index 0000000000..71e3fa4250
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/tcpc/cypress,ccgxxf.yaml
@@ -0,0 +1,34 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: USBC TCPC
+
+compatible: "cypress,ccgxxf"
+
+include: ["i2c-device.yaml", "cros-ec,tcpci.yaml"]
+
+properties:
+  tcpc-flags:
+    type: int
+    default: 0
+    description: |
+      TCPC configuration flags
+  irq-gpios:
+    type: phandle-array
+    required: false
+    description: |
+      Interrupt from TCPC using shim driver
+  rst-gpios:
+    type: phandle-array
+    required: false
+    description: |
+      TCPC reset line while using shim driver
+  int-pin:
+    type: phandles
+    required: false
+    deprecated: true
+    description: |
+      Interrupt from TCPC using gpio-int. This property should only be used when
+      CONFIG_PLATFORM_EC_TCPC_INTERRUPT=n and should be removed when the chip
+      uses the common TCPC driver.
diff --git a/zephyr/dts/bindings/usbc/tcpc/fairchild,fusb302.yaml b/zephyr/dts/bindings/usbc/tcpc/fairchild,fusb302.yaml
new file mode 100644
index 0000000000..51401f6722
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/tcpc/fairchild,fusb302.yaml
@@ -0,0 +1,30 @@
+description: USBC TCPC
+
+compatible: "fairchild,fusb302"
+
+include: ["i2c-device.yaml", "cros-ec,tcpci.yaml"]
+
+properties:
+  tcpc-flags:
+    type: int
+    default: 0
+    description: |
+      TCPC configuration flags
+  irq-gpios:
+    type: phandle-array
+    required: false
+    description: |
+      Interrupt from TCPC using shim driver
+  rst-gpios:
+    type: phandle-array
+    required: false
+    description: |
+      TCPC reset line while using shim driver
+  int-pin:
+    type: phandles
+    required: false
+    deprecated: true
+    description: |
+      Interrupt from TCPC using gpio-int. This property should only be used when
+      CONFIG_PLATFORM_EC_TCPC_INTERRUPT=n and should be removed when the chip
+      uses the common TCPC driver.
diff --git a/zephyr/dts/bindings/usbc/tcpc/nuvoton,nct38xx.yaml b/zephyr/dts/bindings/usbc/tcpc/nuvoton,nct38xx.yaml
new file mode 100644
index 0000000000..14e16c87bb
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/tcpc/nuvoton,nct38xx.yaml
@@ -0,0 +1,43 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Nuvoton NCT38XX USB TCPC binding
+
+compatible: "nuvoton,nct38xx"
+
+include: ["i2c-device.yaml", "cros-ec,tcpci.yaml"]
+
+properties:
+  gpio-dev:
+    type: phandle
+    description: |
+      Pointer to the NCT38XX GPIO device. This is used to binding the Cros TCPC
+      port index to Zephyr NCT38XX GPIO device.
+
+  tcpc-flags:
+    type: int
+    default: 0
+    description: |
+      TCPC configuration flags
+
+  irq-gpios:
+    type: phandle-array
+    required: false
+    description: |
+      Interrupt from TCPC using shim driver
+
+  rst-gpios:
+    type: phandle-array
+    required: false
+    description: |
+      TCPC reset line while using shim driver
+
+  int-pin:
+    type: phandles
+    required: false
+    deprecated: true
+    description: |
+      Interrupt from TCPC using gpio-int. This property should only be used when
+      CONFIG_PLATFORM_EC_TCPC_INTERRUPT=n and should be removed when the chip
+      uses the common TCPC driver.
diff --git a/zephyr/dts/bindings/usbc/tcpc/parade,ps8xxx.yaml b/zephyr/dts/bindings/usbc/tcpc/parade,ps8xxx.yaml
new file mode 100644
index 0000000000..a1122aeb7d
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/tcpc/parade,ps8xxx.yaml
@@ -0,0 +1,22 @@
+description: USBC TCPC
+
+compatible: "parade,ps8xxx"
+
+include: ["i2c-device.yaml", "cros-ec,tcpci.yaml"]
+
+properties:
+  tcpc-flags:
+    type: int
+    default: 0
+    description: |
+      TCPC configuration flags
+  irq-gpios:
+    type: phandle-array
+    required: false
+    description: |
+      Interrupt from TCPC
+  rst-gpios:
+    type: phandle-array
+    required: false
+    description: |
+      TCPC reset line
diff --git a/zephyr/dts/bindings/usbc/tcpc/renesas,raa489000.yaml b/zephyr/dts/bindings/usbc/tcpc/renesas,raa489000.yaml
new file mode 100644
index 0000000000..8f221890c6
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/tcpc/renesas,raa489000.yaml
@@ -0,0 +1,26 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Renesas RAA489000 USB TCPC binding
+
+compatible: "renesas,raa489000"
+
+include: ["i2c-device.yaml", "cros-ec,tcpci.yaml"]
+
+properties:
+  tcpc-flags:
+    type: int
+    default: 0
+    description: |
+      TCPC configuration flags
+  irq-gpios:
+    type: phandle-array
+    required: false
+    description: |
+      Interrupt from TCPC
+  rst-gpios:
+    type: phandle-array
+    required: false
+    description: |
+      TCPC reset line
diff --git a/zephyr/dts/bindings/usbc/tcpc/richtek,rt1715-tcpc.yaml b/zephyr/dts/bindings/usbc/tcpc/richtek,rt1715-tcpc.yaml
new file mode 100644
index 0000000000..f3b934860f
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/tcpc/richtek,rt1715-tcpc.yaml
@@ -0,0 +1,21 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: USBC RT1715 TCPC
+
+compatible: "richtek,rt1715-tcpc"
+
+include: ["i2c-device.yaml", "cros-ec,tcpci.yaml"]
+
+properties:
+  tcpc-flags:
+    type: int
+    default: 0
+    description: |
+      TCPC configuration flags
+  irq-gpios:
+    type: phandle-array
+    required: false
+    description: |
+      Interrupt from TCPC
diff --git a/zephyr/dts/bindings/usbc/tcpc/richtek,rt1718s-tcpc.yaml b/zephyr/dts/bindings/usbc/tcpc/richtek,rt1718s-tcpc.yaml
new file mode 100644
index 0000000000..ce20dc15ad
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/tcpc/richtek,rt1718s-tcpc.yaml
@@ -0,0 +1,21 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: USBC RT1718S TCPC
+
+compatible: "richtek,rt1718s-tcpc"
+
+include: ["i2c-device.yaml", "cros-ec,tcpci.yaml"]
+
+properties:
+  tcpc-flags:
+    type: int
+    default: 0
+    description: |
+      TCPC configuration flags
+  irq-gpios:
+    type: phandle-array
+    required: false
+    description: |
+      Interrupt from TCPC
diff --git a/zephyr/dts/bindings/vendor-prefixes.txt b/zephyr/dts/bindings/vendor-prefixes.txt
new file mode 100644
index 0000000000..9e3f25f285
--- /dev/null
+++ b/zephyr/dts/bindings/vendor-prefixes.txt
@@ -0,0 +1,28 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Valid device-tree compatible string prefixes used in this
+# Zephyr module.  The format is:
+#  vendor-prefix<TAB>vendor name
+aec	Battery vendor
+aoz	Alpha & Omega Semiconductor
+atl	Battery vendor
+bms-gf	Battery vendor
+byd	Battery vendor
+celxpert	Battery vendor
+cosmx	Battery vendor
+cros-ec	The Chromium OS Embedded Controller Project
+cros	The Chromium OS Embedded Controller Project
+dynapack	Battery vendor
+fairchild	Fairchild Semiconductor
+ganfeng	Battery vendor
+getac	Battery vendor
+gfl	Battery vendor
+intersil	Intersil
+kandou		Kandou
+lgc	LG Chem
+powertech	Battery vendor
+pow-tech	Battery vendor
+smp	Battery vendor
+sunwoda	Battery vendor
diff --git a/zephyr/dts/board-overlays/native_posix.dts b/zephyr/dts/board-overlays/native_posix.dts
new file mode 100644
index 0000000000..6b18a0ec6f
--- /dev/null
+++ b/zephyr/dts/board-overlays/native_posix.dts
@@ -0,0 +1,38 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/gpio_defines.h>
+#include <dt-bindings/native-posix-gpio.h>
+
+#define GPIO_VOLTAGE_1P8 NATIVE_POSIX_GPIO_VOLTAGE_1P8
+
+/ {
+	named-gpios {
+		compatible = "named-gpios";
+
+		entering-rw {
+			gpios = <&gpio99 0 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_ENTERING_RW";
+		};
+	};
+
+	/*
+	 * The GPIO_ENTERING_RW signal is used on nearly every board.
+	 * Allocate a dedicated GPIO controller for this signal to avoid
+	 * conflicts with board tests.
+	 */
+	gpio99: gpio@9900 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0x9900 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <1>;
+	};
+};
diff --git a/zephyr/dts/it8xxx2_emul.dts b/zephyr/dts/it8xxx2_emul.dts
new file mode 100644
index 0000000000..5f517b0c1b
--- /dev/null
+++ b/zephyr/dts/it8xxx2_emul.dts
@@ -0,0 +1,195 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Contains emulators for devices normally found on IT8xxx2 chips.
+ * To use, include this file, then the board's gpio definitions.
+ */
+
+#include <dt-bindings/gpio_defines.h>
+#include <dt-bindings/native-posix-gpio.h>
+
+#define GPIO_VOLTAGE_1P8 NATIVE_POSIX_GPIO_VOLTAGE_1P8
+
+/ {
+	gpioa: gpio@f01601 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0xf01601 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpiob: gpio@f01602 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0xf01602 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpioc: gpio@f01603 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0xf01603 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpiod: gpio@f01604 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0xf01604 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpioe: gpio@f01605 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0xf01605 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpiof: gpio@f01606 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0xf01606 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpiog: gpio@f01607 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0xf01607 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpioh: gpio@f01608 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0xf01608 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpioi: gpio@f01609 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0xf01609 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpioj: gpio@f0160a {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0xf0160a 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpiok: gpio@f0160b {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0xf0160b 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpiol: gpio@f0160c {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0xf0160c 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpiom: gpio@f0160d {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0xf0160d 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+
+	i2c_ctrl0: i2c@f01c40 {
+		compatible = "zephyr,i2c-emul-controller";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0xf01c40 0x1000>;
+	};
+
+	i2c_ctrl4: i2c@f03500 {
+		compatible = "zephyr,i2c-emul-controller";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x00f03500 0x0080>;
+	};
+
+	adc0: adc {
+		compatible = "zephyr,adc-emul";
+		nchannels = <6>;
+		ref-internal-mv = <3300>;
+		#io-channel-cells = <1>;
+	};
+};
diff --git a/zephyr/dts/npcx_emul.dts b/zephyr/dts/npcx_emul.dts
new file mode 100644
index 0000000000..20b1a02eeb
--- /dev/null
+++ b/zephyr/dts/npcx_emul.dts
@@ -0,0 +1,266 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Contains emulators for devices normally found on NPCX chips.
+ * To use, include this file, then the board's gpio definitions.
+ */
+
+#include <dt-bindings/gpio_defines.h>
+
+/ {
+	gpio1: gpio@101 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0x101 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpio3: gpio@301 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0x301 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpio4: gpio@400 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0x400 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpio5: gpio@500 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0x500 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpio6: gpio@600 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0x600 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpio7: gpio@700 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0x700 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpio8: gpio@801 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0x801 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpio9: gpio@900 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0x900 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpioa: gpio@a00 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0xa00 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpiob: gpio@b00 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0xb00 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpioc: gpio@c00 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0xc00 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpiod: gpio@d00 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0xd00 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpioe: gpio@e00 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0xe00 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpiof: gpio@f00 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0xf00 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+
+	i2c_ctrl0: i2c@40009000 {
+		status = "okay";
+		compatible = "zephyr,i2c-emul-controller";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x40009000 0x1000>;
+	};
+	i2c_ctrl1: i2c@4000b000 {
+		status = "okay";
+		compatible = "zephyr,i2c-emul-controller";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x4000b000 0x1000>;
+	};
+
+	i2c_ctrl2: i2c@400c0000 {
+		status = "okay";
+		compatible = "zephyr,i2c-emul-controller";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x400c0000 0x1000>;
+	};
+
+	i2c_ctrl3: i2c@400c2000 {
+		status = "okay";
+		compatible = "zephyr,i2c-emul-controller";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x400c2000 0x1000>;
+	};
+
+	i2c_ctrl4: i2c@40008000 {
+		status = "okay";
+		compatible = "zephyr,i2c-emul-controller";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x40008000 0x1000>;
+	};
+
+	i2c_ctrl5: i2c@40017000 {
+		status = "okay";
+		compatible = "zephyr,i2c-emul-controller";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x40017000 0x1000>;
+	};
+
+	i2c_ctrl6: i2c@40018000 {
+		status = "okay";
+		compatible = "zephyr,i2c-emul-controller";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x40018000 0x1000>;
+	};
+
+	i2c_ctrl7: i2c@40019000 {
+		status = "okay";
+		compatible = "zephyr,i2c-emul-controller";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x40019000 0x1000>;
+	};
+	scfg: scfg@400c3000 {
+		compatible = "nuvoton,npcx-scfg";
+		/* First reg region is System Configuration Device */
+		/* Second reg region is System Glue Device */
+		reg = <0x400c3000 0x70
+			0x400a5000 0x2000>;
+		reg-names = "scfg", "glue";
+		#alt-cells = <3>;
+		#lvol-cells = <2>;
+	};
+};
+
+&gpio0 {
+	ngpios = <8>;
+};
diff --git a/zephyr/emul/CMakeLists.txt b/zephyr/emul/CMakeLists.txt
new file mode 100644
index 0000000000..018ac8421f
--- /dev/null
+++ b/zephyr/emul/CMakeLists.txt
@@ -0,0 +1,41 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+add_subdirectory("retimer")
+add_subdirectory("tcpc")
+
+cros_ec_library_include_directories(include)
+
+zephyr_library_sources_ifdef(CONFIG_EMUL_ANX7452	emul_anx7452.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_BB_RETIMER	emul_bb_retimer.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_BC12_DETECT_PI3USB9201	emul_pi3usb9201.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_BMA255		emul_bma255.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_BMA4XX		emul_bma4xx.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_BMI		emul_bmi.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_BMI		emul_bmi160.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_BMI		emul_bmi260.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_CLOCK_CONTROL	emul_clock_control.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_COMMON_I2C	emul_common_i2c.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_CROS_FLASH	emul_flash.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_ICM42607	emul_icm42607.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_ISL923X	emul_isl923x.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_CHARGER_ISL9241 emul_isl9241.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_KB_RAW		emul_kb_raw.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_LIS2DW12	emul_lis2dw12.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_LN9310		emul_ln9310.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_PCT2075	emul_pct2075.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_PPC_NX20P348X	emul_nx20p348x.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_PPC_SYV682X	emul_syv682x.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_PS8743		emul_ps8743.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_RT9490		emul_rt9490.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_RTC		emul_rtc.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_SMART_BATTERY	emul_smart_battery.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_SM5803 	emul_sm5803.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_SN5S330	emul_sn5s330.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_TCS3400	emul_tcs3400.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_TUSB1064	emul_tusb1064.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_USB_MUX_AMD_FP6 emul_amd_fp6.c)
+zephyr_library_sources_ifdef(CONFIG_I2C_MOCK		i2c_mock.c)
+zephyr_library_sources_ifdef(CONFIG_PWM_MOCK            pwm_mock.c)
+zephyr_library_sources_ifdef(CONFIG_VCMP_MOCK           vcmp_mock.c)
diff --git a/zephyr/emul/Kconfig b/zephyr/emul/Kconfig
new file mode 100644
index 0000000000..dbe3428f73
--- /dev/null
+++ b/zephyr/emul/Kconfig
@@ -0,0 +1,227 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+rsource "retimer/Kconfig"
+rsource "tcpc/Kconfig"
+
+config EMUL_COMMON_I2C
+	bool "Common handler for I2C emulator messages"
+	help
+	  Enable common code that is used by many emulators of devices on I2C
+	  bus. It allows to share code for handling I2C messages, locking and
+	  custom user handlers between these emulators.
+
+config EMUL_SMART_BATTERY
+	bool "Smart Battery emulator"
+	default y
+	depends on DT_HAS_ZEPHYR_SMART_BATTERY_EMUL_ENABLED
+	select EMUL_COMMON_I2C
+	help
+	  Enable the Smart Battery emulator. This driver use emulated I2C bus.
+
+config EMUL_BMA255
+	bool "BMA255 emulator"
+	default y
+	depends on DT_HAS_ZEPHYR_BMA255_EMUL_ENABLED
+	select EMUL_COMMON_I2C
+	help
+	  Enable the BMA255 emulator. This driver use emulated I2C bus.
+	  It is used to test bma2x2 driver. Emulators API is available in
+	  zephyr/include/emul/emul_bma255.h
+
+config EMUL_BMA4XX
+	bool "BMA4xx emulator"
+	default y
+	depends on DT_HAS_CROS_BMA4XX_EMUL_ENABLED
+	select EMUL_COMMON_I2C
+	help
+	  Enable the BMA4xx emulator, used to test the bma4xx driver on an
+	  emulated I2C bus; emulator API is in
+	  zephyr/include/emul/emul_bma4xx.h.
+
+config EMUL_BC12_DETECT_PI3USB9201
+	bool "PI3USB9201 emulator"
+	default y if ZTEST
+	depends on DT_HAS_PERICOM_PI3USB9201_ENABLED
+	help
+	  Enable the PI3USB9201 emulator. PI3USB9201 is a BC1.2 charger
+	  detector/advertiser. The emulator supports reading and writing the
+	  4 I2C registers of the PI3USB9201 using the emulated I2C bus.
+
+config EMUL_CHARGER_ISL9241
+	bool "Renesas buck-boost battery charger emulator"
+	default y
+	depends on ZTEST && DT_HAS_INTERSIL_ISL9241_ENABLED
+	select EMUL_COMMON_I2C
+	help
+	  Enable the ISL9241 emulator.  This chip is a configurable buck-boost
+	  battery charger which can communicate over I2C, and utilizes the
+	  emulated I2C bus.
+
+config EMUL_PPC_NX20P348X
+	bool "NXP PPC emulator"
+	default y
+	depends on ZTEST && DT_HAS_NXP_NX20P348X_ENABLED
+	select EMUL_COMMON_I2C
+	help
+	  Enable the NX20P348X emulator, which covers both the NX20P3481 and
+	  NX20P3483.  It is also register compatible with the SM5360A.  This
+	  emulator makes use of the emulated I2C bus.
+
+config EMUL_PPC_SYV682X
+	bool "Silergy SYV682x PPC emulator"
+	default y
+	depends on DT_HAS_ZEPHYR_SYV682X_EMUL_ENABLED
+	select PLATFORM_EC_USBC_PPC_SYV682X
+	help
+	  Enable the SYV682x emulator. SYV682 is a USB Type-C PPC. This driver
+	  uses the emulated I2C bus.
+
+config EMUL_BMI
+	bool "BMI emulator"
+	default y
+	depends on DT_HAS_ZEPHYR_BMI_EMUL_ENABLED
+	select EMUL_COMMON_I2C
+	help
+	  Enable the BMI emulator. This driver use emulated I2C bus.
+	  It is used to test bmi 160 and 260 drivers. Emulators API is
+	  available in zephyr/include/emul/emul_bmi.h
+
+config EMUL_TCS3400
+	bool "TCS3400 emulator"
+	default y
+	depends on DT_HAS_ZEPHYR_TCS3400_EMUL_ENABLED
+	select EMUL_COMMON_I2C
+	help
+	  Enable the TCS3400 light sensor. This driver use emulated I2C bus.
+	  It is used to test als_tcs3400 driver. It supports reading sensor
+	  values which are correctly scaled using current gain and integration
+	  time configuration, switching between IR and clear sensor and
+	  clearing status register using clear interrupt registers. Other
+	  TCS3400 registers support read and write with optional checking
+	  of proper access to reserved bits. Emulators API is available in
+	  zephyr/include/emul/emul_tcs3400.h
+
+config EMUL_TUSB1064
+	bool "TCS3400 emulator"
+	default y
+	depends on DT_HAS_ZEPHYR_TUSB1064_EMUL_ENABLED
+	select EMUL_COMMON_I2C
+	help
+	  Enable the TUSB1064 usb mux. This driver use emulated I2C bus.
+	  Emulator API is available in zephyr/include/emul/emul_tusb1064.h.
+
+config EMUL_USB_MUX_AMD_FP6
+	bool "AMD FP6 USB mux emulator"
+	default y
+	depends on ZTEST && DT_HAS_AMD_USBC_MUX_AMD_FP6_ENABLED
+	select EMUL_COMMON_I2C
+	help
+	  Enable emulator for the AMD FP6 USB mux target.  This is a mux
+	  which, while it resides on the SoC, presents itself to the EC as a
+	  I2C target device
+
+config EMUL_BB_RETIMER
+	bool "BB retimer emulator"
+	default y
+	depends on ZTEST && DT_HAS_INTEL_JHL8040R_ENABLED
+	select EMUL_COMMON_I2C
+	help
+	  Enable the BB (Burnside Bridge) retimer emulator. This driver use
+	  emulated I2C bus. It is used to test bb_retimer driver. It supports
+	  reads and writes to all emulator registers. Emulators API is
+	  available in zephyr/include/emul/emul_bb_retimer.h
+
+config EMUL_KB_RAW
+	bool "Raw keyboard emulator"
+	default y
+	depends on DT_HAS_CROS_EC_KB_RAW_EMUL_ENABLED
+	help
+	  Enable the raw keyboard emulator.
+
+config EMUL_CROS_FLASH
+	bool "Emulated flash driver for the Zephyr shim"
+	default y
+	depends on DT_HAS_CROS_EC_FLASH_EMUL_ENABLED
+	select PLATFORM_EC_FLASH_CROS
+	imply SYSTEM_FAKE
+	help
+	  This option enables the flash emulator for testing.
+
+config EMUL_RTC
+	bool "Emulated RTC driver for Zephyr shim"
+	default y
+	depends on DT_HAS_CROS_EC_RTC_EMUL_ENABLED
+	help
+	  This options enables the RTC emulator for testing.
+
+config EMUL_RT9490
+	bool "Rt9490 charger emulator"
+	default y
+	depends on DT_HAS_ZEPHYR_RT9490_EMUL_ENABLED
+	select EMUL_COMMON_I2C
+	help
+	  Enable the RT9490 light sensor emulator. This driver use emulated I2C
+	  bus. Emulators API is available in zephyr/include/emul/emul_rt9490.h.
+
+config PWM_MOCK
+	bool "Mock implementation of an PWM device"
+	default y
+	depends on DT_HAS_CROS_PWM_MOCK_ENABLED
+	help
+	  Enable the PWM mock. This driver is a pure mock and does nothing by
+	  default.
+
+config VCMP_MOCK
+	bool "Generic voltage comparator device mock implementation"
+	default y
+	depends on DT_HAS_CROS_VCMP_MOCK_ENABLED
+	select ADC
+	help
+	  Enable the generic voltage comparator mock driver.
+
+config EMUL_PCT2075
+	bool "PCT2075 emulator"
+	default y
+	depends on ZTEST && DT_HAS_NXP_PCT2075_ENABLED
+	select EMUL_COMMON_I2C
+	help
+	  Enable the PCT2075 temperature sensor emulator. It uses emulated I2C bus.
+	  Emulator API is available in zephyr/include/emul/emul_pct2075.h.
+
+config EMUL_ANX7452
+	bool "ANX7452 retimer emulator"
+	default y
+	depends on ZTEST && DT_HAS_ANALOGIX_ANX7452_ENABLED
+	select EMUL_COMMON_I2C
+	help
+	  Enable the ANX7452(Analogix) retimer emulator. This driver use
+	  emulated I2C bus. It is used to test anx7452 driver. It supports
+	  reads and writes to all emulator registers. Emulators API is
+	  available in zephyr/include/emul/emul_anx7452.h
+
+config EMUL_PS8743
+	bool "PS8743 emulator"
+	default y
+	depends on DT_HAS_ZEPHYR_PS8743_EMUL_ENABLED
+	select EMUL_COMMON_I2C
+	help
+	  Enable the PS8743 usb mux. This driver use emulated I2C bus.
+	  Emulator API is available in zephyr/include/emul/emul_ps8743.h.
+
+config EMUL_ICM42607
+	bool "icm42607 emulator"
+	default y
+	depends on DT_HAS_ZEPHYR_ICM42607_EMUL_ENABLED
+	select EMUL_COMMON_I2C
+	help
+	  Enable the ICM42607 accelerometer and gyroscope emulator.
+
+rsource "Kconfig.ln9310"
+rsource "Kconfig.lis2dw12"
+rsource "Kconfig.i2c_mock"
+rsource "Kconfig.isl923x"
+rsource "Kconfig.clock_control"
+rsource "Kconfig.sm5803"
+rsource "Kconfig.sn5s330"
diff --git a/zephyr/emul/Kconfig.clock_control b/zephyr/emul/Kconfig.clock_control
new file mode 100644
index 0000000000..29b38333c9
--- /dev/null
+++ b/zephyr/emul/Kconfig.clock_control
@@ -0,0 +1,21 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config EMUL_CLOCK_CONTROL
+	bool "Emulated clock control"
+	default y
+	depends on DT_HAS_CROS_CLOCK_CONTROL_EMUL_ENABLED
+	help
+	  Enable the emulated clock control module. This module introduces a
+	  functioning clock control implementation along with backdoor APIs to
+	  verify and override behavior. Emulator API is available in
+	  zephyr/include/emul/emul_clock_control.h
+
+if EMUL_CLOCK_CONTROL
+
+module = CLOCK_CONTROL_EMUL
+module-str = clock_control_emul
+source "subsys/logging/Kconfig.template.log_config"
+
+endif # EMUL_CLOCK_CONTROL
diff --git a/zephyr/emul/Kconfig.i2c_mock b/zephyr/emul/Kconfig.i2c_mock
new file mode 100644
index 0000000000..9bc75d961c
--- /dev/null
+++ b/zephyr/emul/Kconfig.i2c_mock
@@ -0,0 +1,21 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+menuconfig I2C_MOCK
+	bool "Mock implementation of an I2C device"
+	default y
+	depends on DT_HAS_CROS_I2C_MOCK_ENABLED
+	depends on I2C_EMUL
+	help
+	  Enable the I2C mock. This driver is a pure mock and does nothing by
+	  default. It is used to test common i2c code. Mock API is available in
+	  zephyr/include/emul/i2c_mock.h
+
+if I2C_MOCK
+
+module = I2C_MOCK
+module-str = i2c_mock
+source "subsys/logging/Kconfig.template.log_config"
+
+endif # I2C_MOCK
diff --git a/zephyr/emul/Kconfig.isl923x b/zephyr/emul/Kconfig.isl923x
new file mode 100644
index 0000000000..d1ad526979
--- /dev/null
+++ b/zephyr/emul/Kconfig.isl923x
@@ -0,0 +1,21 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+menuconfig EMUL_ISL923X
+	bool "ISL923X switchcap emulator"
+	default y
+	depends on DT_HAS_CROS_ISL923X_EMUL_ENABLED
+	depends on I2C_EMUL
+	help
+	  Enable the ISL923X emulator. This driver uses the emulated I2C bus. It
+	  is used to test the isl923x driver. Emulator API is available in
+	  zephyr/include/emul/emul_isl923x.h
+
+if EMUL_ISL923X
+
+module = ISL923X_EMUL
+module-str = isl923x_emul
+source "subsys/logging/Kconfig.template.log_config"
+
+endif # EMUL_ISL923X
diff --git a/zephyr/emul/Kconfig.lis2dw12 b/zephyr/emul/Kconfig.lis2dw12
new file mode 100644
index 0000000000..e74f1f8cf4
--- /dev/null
+++ b/zephyr/emul/Kconfig.lis2dw12
@@ -0,0 +1,22 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+menuconfig EMUL_LIS2DW12
+	bool "LIS2DW12 accelerometer emulator"
+	default y
+	depends on DT_HAS_CROS_LIS2DW12_EMUL_ENABLED
+	depends on I2C_EMUL
+	select PLATFORM_EC_ACCEL_LIS2DW12
+	help
+	  Enable the LIS2DW12 emulator. This driver uses the emulated I2C bus.
+	  It is used to test the lis2dw12 driver. Emulator API is available in
+	  zephyr/include/emul/emul_lis2dw12.h
+
+if EMUL_LIS2DW12
+
+module = LIS2DW12_EMUL
+module-str = lis2dw12_emul
+source "subsys/logging/Kconfig.template.log_config"
+
+endif # EMUL_LIS2DW12
diff --git a/zephyr/emul/Kconfig.ln9310 b/zephyr/emul/Kconfig.ln9310
new file mode 100644
index 0000000000..9cacfbd670
--- /dev/null
+++ b/zephyr/emul/Kconfig.ln9310
@@ -0,0 +1,22 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+menuconfig EMUL_LN9310
+	bool "LN9310 switchcap emulator"
+	default y
+	depends on DT_HAS_CROS_LN9310_EMUL_ENABLED
+	depends on I2C_EMUL
+	depends on ASSERT
+	help
+	  Enable the LN9310 emulator. This driver uses the emulated I2C bus. It
+	  is used to test the ln9310 driver. Emulator API is available in
+	  zephyr/include/emul/emul_ln9310.h
+
+if EMUL_LN9310
+
+module = LN9310_EMUL
+module-str = ln9310_emul
+source "subsys/logging/Kconfig.template.log_config"
+
+endif # EMUL_LN9310
diff --git a/zephyr/emul/Kconfig.sm5803 b/zephyr/emul/Kconfig.sm5803
new file mode 100644
index 0000000000..b1ee48a392
--- /dev/null
+++ b/zephyr/emul/Kconfig.sm5803
@@ -0,0 +1,18 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+menuconfig EMUL_SM5803
+	bool "SM5803 charger emulator"
+	default y
+	depends on DT_HAS_CROS_SM5803_EMUL_ENABLED
+	depends on I2C_EMUL
+	help
+	  Enable the SM5803 emulator, used to test the sm5803 driver.
+	  The emulator API is defined in zephyr/include/emul/emul_sm5803.h
+
+if EMUL_SM5803
+module = SM5803_EMUL
+module-str = sm5803_emul
+source "subsys/logging/Kconfig.template.log_config"
+endif
diff --git a/zephyr/emul/Kconfig.sn5s330 b/zephyr/emul/Kconfig.sn5s330
new file mode 100644
index 0000000000..16ce42923e
--- /dev/null
+++ b/zephyr/emul/Kconfig.sn5s330
@@ -0,0 +1,21 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+menuconfig EMUL_SN5S330
+	bool "sn5s330 emulator"
+	default y
+	depends on DT_HAS_CROS_SN5S330_EMUL_ENABLED
+	depends on I2C_EMUL
+	help
+	  Enable the sn5s330 emulator. This driver uses the emulated I2C bus. It
+	  is used to test the sn5s330 driver. Emulator API is available in
+	  zephyr/include/emul/emul_sn5s330.h
+
+if EMUL_SN5S330
+
+module = SN5S330_EMUL
+module-str = sn5s330_emul
+source "subsys/logging/Kconfig.template.log_config"
+
+endif # EMUL_SN5S330
diff --git a/zephyr/emul/emul_amd_fp6.c b/zephyr/emul/emul_amd_fp6.c
new file mode 100644
index 0000000000..b0b618fd6a
--- /dev/null
+++ b/zephyr/emul/emul_amd_fp6.c
@@ -0,0 +1,168 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/usb_mux/amd_fp6.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_stub_device.h"
+#include "usbc/amd_fp6_usb_mux.h"
+#include "util.h"
+
+#include <zephyr/device.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/ztest.h>
+
+#define DT_DRV_COMPAT AMD_FP6_USB_MUX_COMPAT
+
+#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
+LOG_MODULE_REGISTER(emul_amd_fp6);
+
+/* Target supports only 3-byte reads */
+enum amd_fp6_read_bytes {
+	AMD_FP6_STATUS,
+	AMD_FP6_PORT0,
+	AMD_FP6_PORT1,
+	AMD_FP6_MAX_REG,
+};
+
+struct amd_fp6_data {
+	struct i2c_common_emul_data common;
+	int finish_delay; /* How many reads before mux set "completes"? */
+	int waiting_reads; /* How many reads have we waited to complete? */
+	uint8_t last_mux_set; /* Last value of mux set call */
+	uint8_t regs[AMD_FP6_MAX_REG];
+};
+
+/* Helper for setting the mux register with a value and "done" */
+static uint8_t amd_fp6_emul_mux_complete(uint8_t mux_val)
+{
+	return (AMD_FP6_MUX_PORT_CMD_COMPLETE
+		<< AMD_FP6_MUX_PORT_STATUS_OFFSET) |
+	       mux_val;
+}
+
+void amd_fp6_emul_reset_regs(const struct emul *emul)
+{
+	struct amd_fp6_data *data = (struct amd_fp6_data *)emul->data;
+
+	/* Default to easy use (ready and no delay) */
+	data->finish_delay = 0;
+
+	/* Mux starts in low power mode and ready */
+	data->regs[AMD_FP6_STATUS] = AMD_FP6_MUX_PD_STATUS_READY
+				     << AMD_FP6_MUX_PD_STATUS_OFFSET;
+	data->regs[AMD_FP6_PORT0] =
+		amd_fp6_emul_mux_complete(AMD_FP6_MUX_LOW_POWER);
+	/* "Port 1" is unused in current code */
+	data->regs[AMD_FP6_PORT1] = 0;
+}
+
+void amd_fp6_emul_set_delay(const struct emul *emul, int delay_reads)
+{
+	struct amd_fp6_data *data = (struct amd_fp6_data *)emul->data;
+
+	data->finish_delay = delay_reads;
+}
+
+void amd_fp6_emul_set_xbar(const struct emul *emul, bool ready)
+{
+	struct amd_fp6_data *data = (struct amd_fp6_data *)emul->data;
+
+	data->regs[AMD_FP6_STATUS] = ready ? (AMD_FP6_MUX_PD_STATUS_READY
+					      << AMD_FP6_MUX_PD_STATUS_OFFSET) :
+					     0;
+}
+
+static int amd_fp6_emul_read(const struct emul *emul, int reg, uint8_t *val,
+			     int bytes, void *unused_data)
+{
+	struct amd_fp6_data *data = (struct amd_fp6_data *)emul->data;
+	uint8_t *regs = data->regs;
+	int pos = reg + bytes;
+
+	if (!IN_RANGE(pos, 0, AMD_FP6_MAX_REG)) {
+		return -EINVAL;
+	}
+
+	/* Decide if we've finally finished our operation */
+	if (pos == AMD_FP6_PORT0 && data->finish_delay > 0) {
+		data->waiting_reads++;
+
+		if (((regs[pos] >> AMD_FP6_MUX_PORT_STATUS_OFFSET) ==
+		     AMD_FP6_MUX_PORT_CMD_BUSY) &&
+		    (data->waiting_reads >= data->finish_delay))
+			regs[pos] =
+				amd_fp6_emul_mux_complete(data->last_mux_set);
+	}
+
+	*val = regs[pos];
+
+	return 0;
+}
+
+static int amd_fp6_emul_write(const struct emul *emul, int reg, uint8_t val,
+			      int bytes, void *unused_data)
+{
+	struct amd_fp6_data *data = (struct amd_fp6_data *)emul->data;
+	uint8_t *regs = data->regs;
+
+	/* We only support Port 0 */
+	if (reg != 0 || bytes != 1)
+		return -EINVAL;
+
+	data->last_mux_set = val;
+
+	if (data->finish_delay == 0) {
+		regs[AMD_FP6_PORT0] = amd_fp6_emul_mux_complete(val);
+	} else {
+		data->waiting_reads = 0;
+		regs[AMD_FP6_PORT0] = AMD_FP6_MUX_PORT_CMD_BUSY
+				      << AMD_FP6_MUX_PORT_STATUS_OFFSET;
+	}
+
+	return 0;
+}
+
+static int amd_fp6_emul_init(const struct emul *emul,
+			     const struct device *parent)
+{
+	struct amd_fp6_data *data = (struct amd_fp6_data *)emul->data;
+	struct i2c_common_emul_data *common_data = &data->common;
+
+	i2c_common_emul_init(common_data);
+	i2c_common_emul_set_read_func(common_data, amd_fp6_emul_read, NULL);
+	i2c_common_emul_set_write_func(common_data, amd_fp6_emul_write, NULL);
+
+	amd_fp6_emul_reset_regs(emul);
+
+	return 0;
+}
+
+#define INIT_AMD_FP6_EMUL(n)                                         \
+	static struct i2c_common_emul_cfg common_cfg_##n;            \
+	static struct amd_fp6_data amd_fp6_data_##n;                 \
+	static struct i2c_common_emul_cfg common_cfg_##n = {         \
+		.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)),      \
+		.data = &amd_fp6_data_##n.common,                    \
+		.addr = DT_INST_REG_ADDR(n)                          \
+	};                                                           \
+	EMUL_DT_INST_DEFINE(n, amd_fp6_emul_init, &amd_fp6_data_##n, \
+			    &common_cfg_##n, &i2c_common_emul_api, NULL)
+
+DT_INST_FOREACH_STATUS_OKAY(INIT_AMD_FP6_EMUL)
+
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
+
+static void amd_fp6_emul_reset_rule_before(const struct ztest_unit_test *test,
+					   void *data)
+{
+	ARG_UNUSED(test);
+	ARG_UNUSED(data);
+
+#define AMD_FP6_EMUL_RESET_RULE_BEFORE(n) \
+	amd_fp6_emul_reset_regs(EMUL_DT_GET(DT_DRV_INST(n)))
+
+	DT_INST_FOREACH_STATUS_OKAY(AMD_FP6_EMUL_RESET_RULE_BEFORE);
+}
+ZTEST_RULE(amd_fp6_usb_mux_emul_reset, amd_fp6_emul_reset_rule_before, NULL);
diff --git a/zephyr/emul/emul_anx7452.c b/zephyr/emul/emul_anx7452.c
new file mode 100644
index 0000000000..710158861c
--- /dev/null
+++ b/zephyr/emul/emul_anx7452.c
@@ -0,0 +1,262 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/retimer/anx7452.h"
+#include "emul/emul_anx7452.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_stub_device.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/i2c_emul.h>
+#include <zephyr/logging/log.h>
+
+#define DT_DRV_COMPAT analogix_anx7452
+
+#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
+LOG_MODULE_REGISTER(emul_anx7452);
+
+/** Run-time data used by the emulator */
+struct anx7452_emul_data {
+	/** Common I2C data */
+	struct i2c_common_emul_data top_data;
+	struct i2c_common_emul_data ctltop_data;
+
+	/** Configuration information */
+	const struct anx7452_emul_cfg *cfg;
+
+	/** Current state of all emulated ANX7452 retimer registers */
+	uint8_t top_reg;
+
+	uint8_t ctltop_cfg0_reg;
+
+	uint8_t ctltop_cfg1_reg;
+
+	uint8_t ctltop_cfg2_reg;
+};
+
+/** Constant configuration of the emulator */
+struct anx7452_emul_cfg {
+	const struct i2c_common_emul_cfg top_cfg;
+	const struct i2c_common_emul_cfg ctltop_cfg;
+};
+
+/* Workhorse for mapping i2c reg to internal emulator data access */
+static uint8_t *anx7452_emul_get_reg_ptr(struct anx7452_emul_data *data,
+					 int reg)
+{
+	switch (reg) {
+	case ANX7452_TOP_STATUS_REG:
+		return &(data->top_reg);
+	case ANX7452_CTLTOP_CFG0_REG:
+		return &(data->ctltop_cfg0_reg);
+	case ANX7452_CTLTOP_CFG1_REG:
+		return &(data->ctltop_cfg1_reg);
+	case ANX7452_CTLTOP_CFG2_REG:
+		return &(data->ctltop_cfg2_reg);
+	default:
+		__ASSERT(false, "Unimplemented Register Access Error on 0x%x",
+			 reg);
+		/* Statement never reached, required for compiler warnings */
+		return NULL;
+	}
+}
+
+/** Check description in emul_anx7452.h */
+void anx7452_emul_set_reg(const struct emul *emul, int reg, uint8_t val)
+{
+	struct anx7452_emul_data *data = emul->data;
+
+	uint8_t *reg_to_write = anx7452_emul_get_reg_ptr(data, reg);
+	*reg_to_write = val;
+}
+
+/** Check description in emul_anx7452.h */
+uint8_t anx7452_emul_get_reg(const struct emul *emul, int reg)
+{
+	struct anx7452_emul_data *data = emul->data;
+	uint8_t *reg_to_read = anx7452_emul_get_reg_ptr(data, reg);
+
+	return *reg_to_read;
+}
+
+/** Check description in emul_anx7452.h */
+void anx7452_emul_reset(const struct emul *emul)
+{
+	struct anx7452_emul_data *data;
+
+	data = emul->data;
+
+	data->top_reg = 0x01 | ANX7452_TOP_RESERVED_BIT;
+
+	data->ctltop_cfg0_reg = 0x00;
+
+	data->ctltop_cfg1_reg = 0x00;
+
+	data->ctltop_cfg2_reg = 0x00;
+}
+
+static int anx7452_emul_write_byte(const struct emul *emul, int reg,
+				   uint8_t val, int bytes)
+{
+	struct anx7452_emul_data *data = emul->data;
+
+	uint8_t *reg_to_write = anx7452_emul_get_reg_ptr(data, reg);
+	*reg_to_write = val;
+
+	return 0;
+}
+
+static int anx7452_emul_read_byte(const struct emul *emul, int reg,
+				  uint8_t *val, int bytes)
+{
+	struct anx7452_emul_data *data = emul->data;
+	uint8_t *reg_to_read = anx7452_emul_get_reg_ptr(data, reg);
+
+	*val = *reg_to_read;
+
+	return 0;
+}
+
+/**
+ * Emulate an I2C transfer for ANX7452
+ *
+ * This handles simple reads and writes
+ *
+ * @param emul I2C emulation information
+ * @param msgs List of messages to process
+ * @param num_msgs Number of messages to process
+ * @param addr Address of the I2C target device
+ *
+ * @retval 0 If successful
+ * @retval -EIO General input / output error
+ */
+static int anx7452_emul_transfer(const struct emul *emul, struct i2c_msg *msgs,
+				 int num_msgs, int addr)
+{
+	const struct anx7452_emul_cfg *cfg;
+	struct anx7452_emul_data *data;
+	struct i2c_common_emul_data *common_data;
+
+	data = emul->data;
+	cfg = emul->cfg;
+
+	if (addr == cfg->top_cfg.addr) {
+		const struct i2c_common_emul_cfg *common_cfg = &cfg->top_cfg;
+
+		common_data = &data->top_data;
+		return i2c_common_emul_transfer_workhorse(
+			emul, common_data, common_cfg, msgs, num_msgs, addr);
+	} else if (addr == cfg->ctltop_cfg.addr) {
+		const struct i2c_common_emul_cfg *common_cfg = &cfg->ctltop_cfg;
+
+		common_data = &data->ctltop_data;
+		return i2c_common_emul_transfer_workhorse(
+			emul, common_data, common_cfg, msgs, num_msgs, addr);
+	}
+
+	LOG_ERR("Cannot map address %02x", addr);
+	return -EIO;
+}
+
+/* Device instantiation */
+
+static struct i2c_emul_api anx7452_emul_api = {
+	.transfer = anx7452_emul_transfer,
+};
+
+/* Device instantiation */
+
+/**
+ * @brief Set up a new ANX7452 retimer emulator
+ *
+ * This should be called for each ANX7452 retimer device that needs to be
+ * emulated. It registers it with the I2C emulation controller.
+ *
+ * @param emul Emulation information
+ * @param parent Device to emulate
+ *
+ * @return 0 indicating success (always)
+ */
+static int anx7452_emul_init(const struct emul *emul,
+			     const struct device *parent)
+{
+	const struct anx7452_emul_cfg *cfg;
+	struct anx7452_emul_data *data;
+	int ret = 0;
+
+	data = emul->data;
+	cfg = emul->cfg;
+
+	data->top_data.emul.api = &anx7452_emul_api;
+	data->top_data.emul.addr = cfg->top_cfg.addr;
+	data->top_data.emul.target = emul;
+	data->top_data.i2c = parent;
+	data->top_data.cfg = &cfg->top_cfg;
+	i2c_common_emul_init(&data->top_data);
+
+	data->ctltop_data.emul.api = &anx7452_emul_api;
+	data->ctltop_data.emul.addr = cfg->ctltop_cfg.addr;
+	data->ctltop_data.emul.target = emul;
+	data->ctltop_data.i2c = parent;
+	data->ctltop_data.cfg = &cfg->ctltop_cfg;
+	i2c_common_emul_init(&data->ctltop_data);
+
+	ret |= i2c_emul_register(parent, &data->top_data.emul);
+	ret |= i2c_emul_register(parent, &data->ctltop_data.emul);
+
+	anx7452_emul_reset(emul);
+
+	return ret;
+}
+
+#define ANX7452_EMUL(n)                                                   \
+	static struct anx7452_emul_data anx7452_emul_data_##n = {	  \
+		.top_data = {						  \
+			.write_byte = anx7452_emul_write_byte,		  \
+			.read_byte = anx7452_emul_read_byte,		  \
+		},                                                        \
+		.ctltop_data = {					  \
+			.write_byte = anx7452_emul_write_byte,		  \
+			.read_byte = anx7452_emul_read_byte,		  \
+		},							  \
+	};     \
+	static const struct anx7452_emul_cfg anx7452_emul_cfg_##n = {	\
+		.top_cfg = {						\
+			.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)), \
+			.data = &anx7452_emul_data_##n.top_data,	\
+			.addr = DT_INST_REG_ADDR(n),		\
+		},							\
+		.ctltop_cfg = {						\
+			.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)), \
+			.data = &anx7452_emul_data_##n.ctltop_data,	\
+			.addr = ANX7452_I2C_ADDR_CTLTOP_FLAGS,		\
+		},		                                        \
+	};   \
+	EMUL_DT_INST_DEFINE(n, anx7452_emul_init, &anx7452_emul_data_##n, \
+			    &anx7452_emul_cfg_##n, &anx7452_emul_api, NULL)
+
+DT_INST_FOREACH_STATUS_OKAY(ANX7452_EMUL);
+
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
+
+struct i2c_common_emul_data *
+emul_anx7452_get_i2c_common_data(const struct emul *emul,
+				 enum anx7452_emul_port port)
+{
+	struct anx7452_emul_data *data;
+
+	data = emul->data;
+
+	switch (port) {
+	case TOP_EMUL_PORT:
+		return &data->top_data;
+	case CTLTOP_EMUL_PORT:
+		return &data->ctltop_data;
+	default:
+		return NULL;
+	}
+}
diff --git a/zephyr/emul/emul_bb_retimer.c b/zephyr/emul/emul_bb_retimer.c
new file mode 100644
index 0000000000..10f0fa591d
--- /dev/null
+++ b/zephyr/emul/emul_bb_retimer.c
@@ -0,0 +1,341 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/retimer/bb_retimer.h"
+#include "emul/emul_bb_retimer.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_stub_device.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/i2c_emul.h>
+#include <zephyr/logging/log.h>
+
+#define DT_DRV_COMPAT intel_jhl8040r
+
+#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
+LOG_MODULE_REGISTER(emul_bb_retimer);
+
+/** Run-time data used by the emulator */
+struct bb_emul_data {
+	/** Common I2C data */
+	struct i2c_common_emul_data common;
+
+	/** Current state of all emulated BB retimer registers */
+	uint32_t reg[BB_RETIMER_REG_COUNT];
+
+	/** Vendor ID of emulated device */
+	uint32_t vendor_id;
+
+	/** Return error when trying to write to RO register */
+	bool error_on_ro_write;
+	/** Return error when trying to write 1 to reserved bit */
+	bool error_on_rsvd_write;
+
+	/** Value of data dword in ongoing i2c message */
+	uint32_t data_dword;
+};
+
+/** Check description in emul_bb_retimer.h */
+void bb_emul_set_reg(const struct emul *emul, int reg, uint32_t val)
+{
+	struct bb_emul_data *data;
+
+	if (reg < 0 || reg > BB_RETIMER_REG_COUNT) {
+		return;
+	}
+
+	data = emul->data;
+	data->reg[reg] = val;
+}
+
+/** Check description in emul_bb_retimer.h */
+uint32_t bb_emul_get_reg(const struct emul *emul, int reg)
+{
+	struct bb_emul_data *data;
+
+	if (reg < 0 || reg > BB_RETIMER_REG_COUNT) {
+		return 0;
+	}
+
+	data = emul->data;
+
+	return data->reg[reg];
+}
+
+/** Check description in emul_bb_retimer.h */
+void bb_emul_set_err_on_ro_write(const struct emul *emul, bool set)
+{
+	struct bb_emul_data *data;
+
+	data = emul->data;
+	data->error_on_ro_write = set;
+}
+
+/** Check description in emul_bb_retimer.h */
+void bb_emul_set_err_on_rsvd_write(const struct emul *emul, bool set)
+{
+	struct bb_emul_data *data;
+
+	data = emul->data;
+	data->error_on_rsvd_write = set;
+}
+
+/** Mask reserved bits in each register of BB retimer */
+static const uint32_t bb_emul_rsvd_mask[] = {
+	[BB_RETIMER_REG_VENDOR_ID] = 0x00000000,
+	[BB_RETIMER_REG_DEVICE_ID] = 0x00000000,
+	[0x02] = 0xffffffff, /* Reserved */
+	[0x03] = 0xffffffff, /* Reserved */
+	[BB_RETIMER_REG_CONNECTION_STATE] = 0xc0201000,
+	[BB_RETIMER_REG_TBT_CONTROL] = 0xffffdfff,
+	[0x06] = 0xffffffff, /* Reserved */
+	[BB_RETIMER_REG_EXT_CONNECTION_MODE] = 0x08007f00,
+};
+
+/**
+ * @brief Reset registers to default values
+ *
+ * @param emul Pointer to BB retimer emulator
+ */
+static void bb_emul_reset(const struct emul *emul)
+{
+	struct bb_emul_data *data;
+
+	data = emul->data;
+
+	data->reg[BB_RETIMER_REG_VENDOR_ID] = data->vendor_id;
+	data->reg[BB_RETIMER_REG_DEVICE_ID] = BB_RETIMER_DEVICE_ID;
+	data->reg[0x02] = 0x00; /* Reserved */
+	data->reg[0x03] = 0x00; /* Reserved */
+	data->reg[BB_RETIMER_REG_CONNECTION_STATE] = 0x00;
+	data->reg[BB_RETIMER_REG_TBT_CONTROL] = 0x00;
+	data->reg[0x06] = 0x00; /* Reserved */
+	data->reg[BB_RETIMER_REG_EXT_CONNECTION_MODE] = 0x00;
+}
+
+/**
+ * @brief Handle I2C write message. It is checked if accessed register isn't RO
+ *        and reserved bits are set to 0. Write set value of reg field of BB
+ *        retimer emulator data ignoring reserved bits and write only bits.
+ *
+ * @param emul Pointer to BB retimer emulator
+ * @param reg Register which is written
+ * @param msg_len Length of handled I2C message
+ *
+ * @return 0 on success
+ * @return -EIO on error
+ */
+static int bb_emul_handle_write(const struct emul *emul, int reg, int msg_len)
+{
+	struct bb_emul_data *data;
+	uint32_t val;
+
+	data = emul->data;
+
+	/* This write only selected register for I2C read message */
+	if (msg_len < 2) {
+		return 0;
+	}
+
+	val = data->data_dword;
+
+	/*
+	 * BB retimer ignores data bytes above 4 and use zeros if there is less
+	 * then 4 data bytes. Emulator prints warning in that case.
+	 */
+	if (msg_len != 6) {
+		LOG_WRN("Got %d bytes of WR data, expected 4", msg_len - 2);
+	}
+
+	if (reg <= BB_RETIMER_REG_DEVICE_ID || reg >= BB_RETIMER_REG_COUNT ||
+	    reg == BB_RETIMER_REG_TBT_CONTROL) {
+		if (data->error_on_ro_write) {
+			LOG_ERR("Writing to reg 0x%x which is RO", reg);
+			return -EIO;
+		}
+
+		return 0;
+	}
+
+	if (data->error_on_rsvd_write && bb_emul_rsvd_mask[reg] & val) {
+		LOG_ERR("Writing 0x%x to reg 0x%x with rsvd bits mask 0x%x",
+			val, reg, bb_emul_rsvd_mask[reg]);
+		return -EIO;
+	}
+
+	/* Ignore all reserved bits */
+	val &= ~bb_emul_rsvd_mask[reg];
+	val |= data->reg[reg] & bb_emul_rsvd_mask[reg];
+
+	data->reg[reg] = val;
+
+	return 0;
+}
+
+/**
+ * @brief Handle I2C read message. Response is obtained from reg field of bb
+ *        emul data.
+ *
+ * @param emul Pointer to BB retimer emulator
+ * @param reg Register address to read
+ *
+ * @return 0 on success
+ * @return -EIO on error
+ */
+static int bb_emul_handle_read(const struct emul *emul, int reg)
+{
+	struct bb_emul_data *data;
+
+	data = emul->data;
+
+	if (reg >= BB_RETIMER_REG_COUNT) {
+		LOG_ERR("Read unknown register 0x%x", reg);
+
+		return -EIO;
+	}
+
+	data->data_dword = data->reg[reg];
+
+	return 0;
+}
+
+/**
+ * @brief Function called for each byte of write message. Data are stored
+ *        in data_dword field of bb_emul_data
+ *
+ * @param emul Pointer to BB retimer emulator
+ * @param reg First byte of write message
+ * @param val Received byte of write message
+ * @param bytes Number of bytes already received
+ *
+ * @return 0 on success
+ */
+static int bb_emul_write_byte(const struct emul *emul, int reg, uint8_t val,
+			      int bytes)
+{
+	struct bb_emul_data *data;
+
+	data = emul->data;
+
+	if (bytes == 1) {
+		data->data_dword = 0;
+		if (val != 4) {
+			LOG_WRN("Invalid write size");
+		}
+	} else if (bytes < 6) {
+		data->data_dword |= val << (8 * (bytes - 2));
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Function called for each byte of read message. data_dword is converted
+ *        to read message response.
+ *
+ * @param emul Pointer to BB retimer emulator
+ * @param reg First byte of last write message
+ * @param val Pointer where byte to read should be stored
+ * @param bytes Number of bytes already readed
+ *
+ * @return 0 on success
+ */
+static int bb_emul_read_byte(const struct emul *emul, int reg, uint8_t *val,
+			     int bytes)
+{
+	struct bb_emul_data *data;
+
+	data = emul->data;
+
+	/* First byte of read message is read size which is always 4 */
+	if (bytes == 0) {
+		*val = 4;
+		return 0;
+	}
+
+	*val = data->data_dword & 0xff;
+	data->data_dword >>= 8;
+
+	return 0;
+}
+
+/**
+ * @brief Get currently accessed register, which always equals to selected
+ *        register.
+ *
+ * @param emul Pointer to BB retimer emulator
+ * @param reg First byte of last write message
+ * @param bytes Number of bytes already handled from current message
+ * @param read If currently handled is read message
+ *
+ * @return Currently accessed register
+ */
+static int bb_emul_access_reg(const struct emul *emul, int reg, int bytes,
+			      bool read)
+{
+	return reg;
+}
+
+/* Device instantiation */
+
+/**
+ * @brief Set up a new BB retimer emulator
+ *
+ * This should be called for each BB retimer device that needs to be
+ * emulated. It registers it with the I2C emulation controller.
+ *
+ * @param emul Emulation information
+ * @param parent Device to emulate
+ *
+ * @return 0 indicating success (always)
+ */
+static int bb_emul_init(const struct emul *emul, const struct device *parent)
+{
+	struct bb_emul_data *data = emul->data;
+
+	data->common.i2c = parent;
+
+	i2c_common_emul_init(&data->common);
+
+	bb_emul_reset(emul);
+
+	return 0;
+}
+
+#define BB_RETIMER_EMUL(n)                                          \
+	static struct bb_emul_data bb_emul_data_##n = {			\
+		.vendor_id = BB_RETIMER_VENDOR_ID_1,	\
+		.error_on_ro_write = true, \
+		.error_on_rsvd_write = true,	\
+		.common = {						\
+			.start_write = NULL,				\
+			.write_byte = bb_emul_write_byte,		\
+			.finish_write = bb_emul_handle_write,		\
+			.start_read = bb_emul_handle_read,		\
+			.read_byte = bb_emul_read_byte,			\
+			.finish_read = NULL,				\
+			.access_reg = bb_emul_access_reg,		\
+		},							\
+	};         \
+                                                                    \
+	static const struct i2c_common_emul_cfg bb_emul_cfg_##n = { \
+		.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)),     \
+		.data = &bb_emul_data_##n.common,                   \
+		.addr = DT_INST_REG_ADDR(n),                        \
+	};                                                          \
+	EMUL_DT_INST_DEFINE(n, bb_emul_init, &bb_emul_data_##n,     \
+			    &bb_emul_cfg_##n, &i2c_common_emul_api, NULL)
+
+DT_INST_FOREACH_STATUS_OKAY(BB_RETIMER_EMUL)
+
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
+
+struct i2c_common_emul_data *
+emul_bb_retimer_get_i2c_common_data(const struct emul *emul)
+{
+	return emul->data;
+}
diff --git a/zephyr/emul/emul_bma255.c b/zephyr/emul/emul_bma255.c
new file mode 100644
index 0000000000..cd85c74872
--- /dev/null
+++ b/zephyr/emul/emul_bma255.c
@@ -0,0 +1,1018 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/accel_bma2x2.h"
+#include "emul/emul_bma255.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_stub_device.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/i2c_emul.h>
+#include <zephyr/logging/log.h>
+
+#define DT_DRV_COMPAT zephyr_bma255_emul
+
+#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
+LOG_MODULE_REGISTER(emul_bma255);
+
+/** Run-time data used by the emulator */
+struct bma_emul_data {
+	/** Common I2C data */
+	struct i2c_common_emul_data common;
+
+	/** Value of data byte in ongoing write message */
+	uint8_t write_byte;
+
+	/** Current state of all emulated BMA255 registers */
+	uint8_t reg[0x40];
+	/** Current state of NVM where offset and GP0/1 can be saved */
+	uint8_t nvm_x;
+	uint8_t nvm_y;
+	uint8_t nvm_z;
+	uint8_t nvm_gp0;
+	uint8_t nvm_gp1;
+	/** Internal offset values used in calculations */
+	int16_t off_x;
+	int16_t off_y;
+	int16_t off_z;
+	/** Internal values of accelerometr */
+	int16_t acc_x;
+	int16_t acc_y;
+	int16_t acc_z;
+
+	/**
+	 * Return error when trying to start offset compensation when not ready
+	 * flag is set.
+	 */
+	bool error_on_cal_trg_nrdy;
+	/**
+	 * Return error when trying to start offset compensation with range
+	 * set to value different than 2G.
+	 */
+	bool error_on_cal_trg_bad_range;
+	/** Return error when trying to write to RO register */
+	bool error_on_ro_write;
+	/** Return error when trying to write 1 to reserved bit */
+	bool error_on_rsvd_write;
+	/** Return error when trying to access MSB before LSB */
+	bool error_on_msb_first;
+	/**
+	 * Flag set when LSB register is accessed and cleared when MSB is
+	 * accessed. Allows to track order of accessing acc registers
+	 */
+	bool lsb_x_read;
+	bool lsb_y_read;
+	bool lsb_z_read;
+};
+
+/** Check description in emul_bma255.h */
+void bma_emul_set_reg(const struct emul *emul, int reg, uint8_t val)
+{
+	struct bma_emul_data *data;
+
+	if (reg < 0 || reg > BMA2x2_FIFO_DATA_OUTPUT_ADDR) {
+		return;
+	}
+
+	data = emul->data;
+	data->reg[reg] = val;
+}
+
+/** Check description in emul_bma255.h */
+uint8_t bma_emul_get_reg(const struct emul *emul, int reg)
+{
+	struct bma_emul_data *data;
+
+	if (reg < 0 || reg > BMA2x2_FIFO_DATA_OUTPUT_ADDR) {
+		return 0;
+	}
+
+	data = emul->data;
+
+	return data->reg[reg];
+}
+
+/**
+ * @brief Convert @p val to two's complement representation. It makes sure that
+ *        bit representation is correct even on platforms which represent
+ *        signed inteager in different format. Unsigned bit representation
+ *        allows to use well defined bitwise operations on returned value.
+ *
+ * @param val Inteager that is converted
+ *
+ * @return two's complement representation of @p val
+ */
+static uint16_t bma_emul_val_to_twos_comp(int16_t val)
+{
+	uint16_t twos_comp_val;
+
+	/* Make sure that value is converted to twos compliment format */
+	if (val < 0) {
+		twos_comp_val = (uint16_t)(-val);
+		twos_comp_val = ~twos_comp_val + 1;
+	} else {
+		twos_comp_val = (uint16_t)val;
+	}
+
+	return twos_comp_val;
+}
+
+/**
+ * @brief Convert value from NVM format (8bit, 0x01 == 7.8mg) to internal
+ *        offset format (16bit, 0x01 == 0.97mg).
+ *
+ * @param nvm Value in NVM format (8bit, 0x01 == 7.8mg). This is binary
+ *            representation of two's complement signed number.
+ *
+ * @return offset Internal representation of @p nvm (16bit, 0x01 == 0.97mg)
+ */
+static int16_t bma_emul_nvm_to_off(uint8_t nvm)
+{
+	int16_t offset;
+	int8_t sign;
+
+	if (nvm & BIT(7)) {
+		sign = -1;
+		/* NVM value is in two's complement format */
+		nvm = ~nvm + 1;
+	} else {
+		sign = 1;
+	}
+
+	offset = (int16_t)nvm;
+	/* LSB in NVM is 7.8mg, while LSB in internal offset is 0.97mg */
+	offset *= sign * 8;
+
+	return offset;
+}
+
+/**
+ * @brief Convert value from internal offset format (16bit, 0x01 == 0.97mg) to
+ *        NVM format (8bit, 0x01 == 7.8mg). Function makes sure that NVM value
+ *        is representation of two's complement signed number.
+ *
+ * @param val Value in internal offset format (16bit, 0x01 == 0.97mg).
+ *
+ * @return nvm NVM format representation of @p val (8bit, 0x01 == 7.8mg)
+ */
+static uint8_t bma_emul_off_to_nvm(int16_t off)
+{
+	uint16_t twos_comp_val;
+	uint8_t nvm = 0;
+
+	twos_comp_val = bma_emul_val_to_twos_comp(off);
+
+	/*
+	 * LSB in internal representation has value 0.97mg, while in NVM
+	 * LSB is 7.8mg. Skip 0.97mg, 1.9mg and 3.9mg bits.
+	 */
+	nvm |= (twos_comp_val >> 3) & 0x7f;
+	/* Set sign bit */
+	nvm |= (twos_comp_val & BIT(15)) ? BIT(7) : 0x00;
+
+	return nvm;
+}
+
+/** Check description in emul_bma255.h */
+int16_t bma_emul_get_off(const struct emul *emul, int axis)
+{
+	struct bma_emul_data *data;
+
+	data = emul->data;
+
+	switch (axis) {
+	case BMA_EMUL_AXIS_X:
+		return data->off_x;
+	case BMA_EMUL_AXIS_Y:
+		return data->off_y;
+	case BMA_EMUL_AXIS_Z:
+		return data->off_z;
+	}
+
+	return 0;
+}
+
+/** Check description in emul_bma255.h */
+void bma_emul_set_off(const struct emul *emul, int axis, int16_t val)
+{
+	struct bma_emul_data *data;
+
+	data = emul->data;
+
+	switch (axis) {
+	case BMA_EMUL_AXIS_X:
+		data->off_x = val;
+		data->reg[BMA2x2_OFFSET_X_AXIS_ADDR] =
+			bma_emul_off_to_nvm(data->off_x);
+		break;
+	case BMA_EMUL_AXIS_Y:
+		data->off_y = val;
+		data->reg[BMA2x2_OFFSET_Y_AXIS_ADDR] =
+			bma_emul_off_to_nvm(data->off_y);
+		break;
+	case BMA_EMUL_AXIS_Z:
+		data->off_z = val;
+		data->reg[BMA2x2_OFFSET_Z_AXIS_ADDR] =
+			bma_emul_off_to_nvm(data->off_z);
+		break;
+	}
+}
+
+/** Check description in emul_bma255.h */
+int16_t bma_emul_get_acc(const struct emul *emul, int axis)
+{
+	struct bma_emul_data *data;
+
+	data = emul->data;
+
+	switch (axis) {
+	case BMA_EMUL_AXIS_X:
+		return data->acc_x;
+	case BMA_EMUL_AXIS_Y:
+		return data->acc_y;
+	case BMA_EMUL_AXIS_Z:
+		return data->acc_z;
+	}
+
+	return 0;
+}
+
+/** Check description in emul_bma255.h */
+void bma_emul_set_acc(const struct emul *emul, int axis, int16_t val)
+{
+	struct bma_emul_data *data;
+
+	data = emul->data;
+
+	switch (axis) {
+	case BMA_EMUL_AXIS_X:
+		data->acc_x = val;
+		break;
+	case BMA_EMUL_AXIS_Y:
+		data->acc_y = val;
+		break;
+	case BMA_EMUL_AXIS_Z:
+		data->acc_z = val;
+		break;
+	}
+}
+
+/** Check description in emul_bma255.h */
+void bma_emul_set_err_on_cal_nrdy(const struct emul *emul, bool set)
+{
+	struct bma_emul_data *data;
+
+	data = emul->data;
+	data->error_on_cal_trg_nrdy = set;
+}
+
+/** Check description in emul_bma255.h */
+void bma_emul_set_err_on_cal_bad_range(const struct emul *emul, bool set)
+{
+	struct bma_emul_data *data;
+
+	data = emul->data;
+	data->error_on_cal_trg_bad_range = set;
+}
+
+/** Check description in emul_bma255.h */
+void bma_emul_set_err_on_ro_write(const struct emul *emul, bool set)
+{
+	struct bma_emul_data *data;
+
+	data = emul->data;
+	data->error_on_ro_write = set;
+}
+
+/** Check description in emul_bma255.h */
+void bma_emul_set_err_on_rsvd_write(const struct emul *emul, bool set)
+{
+	struct bma_emul_data *data;
+
+	data = emul->data;
+	data->error_on_rsvd_write = set;
+}
+
+/** Check description in emul_bma255.h */
+void bma_emul_set_err_on_msb_first(const struct emul *emul, bool set)
+{
+	struct bma_emul_data *data;
+
+	data = emul->data;
+	data->error_on_msb_first = set;
+}
+
+/** Mask reserved bits in each register of BMA255 */
+static const uint8_t bma_emul_rsvd_mask[] = {
+	[BMA2x2_CHIP_ID_ADDR] = 0x00,
+	[0x01] = 0xff, /* Reserved */
+	[BMA2x2_X_AXIS_LSB_ADDR] = 0x0e,
+	[BMA2x2_X_AXIS_MSB_ADDR] = 0x00,
+	[BMA2x2_Y_AXIS_LSB_ADDR] = 0x0e,
+	[BMA2x2_Y_AXIS_MSB_ADDR] = 0x00,
+	[BMA2x2_Z_AXIS_LSB_ADDR] = 0x0e,
+	[BMA2x2_Z_AXIS_MSB_ADDR] = 0x00,
+	[BMA2x2_TEMP_ADDR] = 0x00,
+	[BMA2x2_STAT1_ADDR] = 0x00,
+	[BMA2x2_STAT2_ADDR] = 0x1f,
+	[BMA2x2_STAT_TAP_SLOPE_ADDR] = 0x00,
+	[BMA2x2_STAT_ORIENT_HIGH_ADDR] = 0x00,
+	[0x0d] = 0xff, /* Reserved */
+	[BMA2x2_STAT_FIFO_ADDR] = 0x00,
+	[BMA2x2_RANGE_SELECT_ADDR] = 0xf0,
+	[BMA2x2_BW_SELECT_ADDR] = 0xe0,
+	[BMA2x2_MODE_CTRL_ADDR] = 0x01,
+	[BMA2x2_LOW_NOISE_CTRL_ADDR] = 0x9f,
+	[BMA2x2_DATA_CTRL_ADDR] = 0x3f,
+	[BMA2x2_RST_ADDR] = 0x00,
+	[0x15] = 0xff, /* Reserved */
+	[BMA2x2_INTR_ENABLE1_ADDR] = 0x08,
+	[BMA2x2_INTR_ENABLE2_ADDR] = 0x80,
+	[BMA2x2_INTR_SLOW_NO_MOTION_ADDR] = 0xf0,
+	[BMA2x2_INTR1_PAD_SELECT_ADDR] = 0x00,
+	[BMA2x2_INTR_DATA_SELECT_ADDR] = 0x18,
+	[BMA2x2_INTR2_PAD_SELECT_ADDR] = 0x00,
+	[0x1c] = 0xff, /* Reserved */
+	[0x1d] = 0xff, /* Reserved */
+	[BMA2x2_INTR_SOURCE_ADDR] = 0xc0,
+	[0x1f] = 0xff, /* Reserved */
+	[BMA2x2_INTR_SET_ADDR] = 0xf0,
+	[BMA2x2_INTR_CTRL_ADDR] = 0x70,
+	[BMA2x2_LOW_DURN_ADDR] = 0x00,
+	[BMA2x2_LOW_THRES_ADDR] = 0x00,
+	[BMA2x2_LOW_HIGH_HYST_ADDR] = 0x38,
+	[BMA2x2_HIGH_DURN_ADDR] = 0x00,
+	[BMA2x2_HIGH_THRES_ADDR] = 0x00,
+	[BMA2x2_SLOPE_DURN_ADDR] = 0x00,
+	[BMA2x2_SLOPE_THRES_ADDR] = 0x00,
+	[BMA2x2_SLOW_NO_MOTION_THRES_ADDR] = 0x00,
+	[BMA2x2_TAP_PARAM_ADDR] = 0x38,
+	[BMA2x2_TAP_THRES_ADDR] = 0x20,
+	[BMA2x2_ORIENT_PARAM_ADDR] = 0x80,
+	[BMA2x2_THETA_BLOCK_ADDR] = 0x80,
+	[BMA2x2_THETA_FLAT_ADDR] = 0xc0,
+	[BMA2x2_FLAT_HOLD_TIME_ADDR] = 0xc8,
+	[BMA2x2_FIFO_WML_TRIG] = 0xc0,
+	[0x31] = 0xff, /* Reserved */
+	[BMA2x2_SELFTEST_ADDR] = 0xf8,
+	[BMA2x2_EEPROM_CTRL_ADDR] = 0x00,
+	[BMA2x2_SERIAL_CTRL_ADDR] = 0xf8,
+	[0x35] = 0xff, /* Reserved */
+	[BMA2x2_OFFSET_CTRL_ADDR] = 0x08,
+	[BMA2x2_OFC_SETTING_ADDR] = 0x80,
+	[BMA2x2_OFFSET_X_AXIS_ADDR] = 0x00,
+	[BMA2x2_OFFSET_Y_AXIS_ADDR] = 0x00,
+	[BMA2x2_OFFSET_Z_AXIS_ADDR] = 0x00,
+	[BMA2x2_GP0_ADDR] = 0x00,
+	[BMA2x2_GP1_ADDR] = 0x00,
+	[0x3d] = 0xff, /* Reserved */
+	[BMA2x2_FIFO_MODE_ADDR] = 0x3c,
+	[BMA2x2_FIFO_DATA_OUTPUT_ADDR] = 0x00,
+};
+
+/**
+ * @brief Reset register values and internal representation of offset and two
+ *        general purpose registers
+ *
+ * @param emul Pointer to BMA255 emulator
+ */
+static void bma_emul_restore_nvm(const struct emul *emul)
+{
+	struct bma_emul_data *data;
+
+	data = emul->data;
+
+	/* Restore registers values */
+	data->reg[BMA2x2_OFFSET_X_AXIS_ADDR] = data->nvm_x;
+	data->reg[BMA2x2_OFFSET_Y_AXIS_ADDR] = data->nvm_y;
+	data->reg[BMA2x2_OFFSET_Z_AXIS_ADDR] = data->nvm_z;
+	data->reg[BMA2x2_GP0_ADDR] = data->nvm_gp0;
+	data->reg[BMA2x2_GP1_ADDR] = data->nvm_gp1;
+
+	/* Restore internal offset values */
+	data->off_x = bma_emul_nvm_to_off(data->nvm_x);
+	data->off_y = bma_emul_nvm_to_off(data->nvm_y);
+	data->off_z = bma_emul_nvm_to_off(data->nvm_z);
+}
+
+/**
+ * @brief Reset registers to default values and restore registers backed by NVM
+ *
+ * @param emul Pointer to BMA255 emulator
+ */
+static void bma_emul_reset(const struct emul *emul)
+{
+	struct bma_emul_data *data;
+
+	data = emul->data;
+
+	data->reg[BMA2x2_CHIP_ID_ADDR] = 0xfa;
+	data->reg[0x01] = 0x00; /* Reserved */
+	data->reg[BMA2x2_X_AXIS_LSB_ADDR] = 0x00;
+	data->reg[BMA2x2_X_AXIS_MSB_ADDR] = 0x00;
+	data->reg[BMA2x2_Y_AXIS_LSB_ADDR] = 0x00;
+	data->reg[BMA2x2_Y_AXIS_MSB_ADDR] = 0x00;
+	data->reg[BMA2x2_Z_AXIS_LSB_ADDR] = 0x00;
+	data->reg[BMA2x2_Z_AXIS_MSB_ADDR] = 0x00;
+	data->reg[BMA2x2_TEMP_ADDR] = 0x00;
+	data->reg[BMA2x2_STAT1_ADDR] = 0x00;
+	data->reg[BMA2x2_STAT2_ADDR] = 0x00;
+	data->reg[BMA2x2_STAT_TAP_SLOPE_ADDR] = 0x00;
+	data->reg[BMA2x2_STAT_ORIENT_HIGH_ADDR] = 0x00;
+	data->reg[0x0d] = 0xff; /* Reserved */
+	data->reg[BMA2x2_STAT_FIFO_ADDR] = 0x00;
+	data->reg[BMA2x2_RANGE_SELECT_ADDR] = 0x03;
+	data->reg[BMA2x2_BW_SELECT_ADDR] = 0x0f;
+	data->reg[BMA2x2_MODE_CTRL_ADDR] = 0x00;
+	data->reg[BMA2x2_LOW_NOISE_CTRL_ADDR] = 0x00;
+	data->reg[BMA2x2_DATA_CTRL_ADDR] = 0x00;
+	data->reg[BMA2x2_RST_ADDR] = 0x00;
+	data->reg[0x15] = 0xff; /* Reserved */
+	data->reg[BMA2x2_INTR_ENABLE1_ADDR] = 0x00;
+	data->reg[BMA2x2_INTR_ENABLE2_ADDR] = 0x00;
+	data->reg[BMA2x2_INTR_SLOW_NO_MOTION_ADDR] = 0x00;
+	data->reg[BMA2x2_INTR1_PAD_SELECT_ADDR] = 0x00;
+	data->reg[BMA2x2_INTR_DATA_SELECT_ADDR] = 0x00;
+	data->reg[BMA2x2_INTR2_PAD_SELECT_ADDR] = 0x00;
+	data->reg[0x1c] = 0xff; /* Reserved */
+	data->reg[0x1d] = 0xff; /* Reserved */
+	data->reg[BMA2x2_INTR_SOURCE_ADDR] = 0x00;
+	data->reg[0x1f] = 0xff; /* Reserved */
+	data->reg[BMA2x2_INTR_SET_ADDR] = 0x05;
+	data->reg[BMA2x2_INTR_CTRL_ADDR] = 0x00;
+	data->reg[BMA2x2_LOW_DURN_ADDR] = 0x09;
+	data->reg[BMA2x2_LOW_THRES_ADDR] = 0x30;
+	data->reg[BMA2x2_LOW_HIGH_HYST_ADDR] = 0x81;
+	data->reg[BMA2x2_HIGH_DURN_ADDR] = 0x0f;
+	data->reg[BMA2x2_HIGH_THRES_ADDR] = 0xc0;
+	data->reg[BMA2x2_SLOPE_DURN_ADDR] = 0x00;
+	data->reg[BMA2x2_SLOPE_THRES_ADDR] = 0x14;
+	data->reg[BMA2x2_SLOW_NO_MOTION_THRES_ADDR] = 0x14;
+	data->reg[BMA2x2_TAP_PARAM_ADDR] = 0x04;
+	data->reg[BMA2x2_TAP_THRES_ADDR] = 0x0a;
+	data->reg[BMA2x2_ORIENT_PARAM_ADDR] = 0x18;
+	data->reg[BMA2x2_THETA_BLOCK_ADDR] = 0x48;
+	data->reg[BMA2x2_THETA_FLAT_ADDR] = 0x08;
+	data->reg[BMA2x2_FLAT_HOLD_TIME_ADDR] = 0x11;
+	data->reg[BMA2x2_FIFO_WML_TRIG] = 0x00;
+	data->reg[0x31] = 0xff; /* Reserved */
+	data->reg[BMA2x2_SELFTEST_ADDR] = 0x00;
+	data->reg[BMA2x2_EEPROM_CTRL_ADDR] = 0xf0;
+	data->reg[BMA2x2_SERIAL_CTRL_ADDR] = 0x00;
+	data->reg[0x35] = 0x00; /* Reserved */
+	data->reg[BMA2x2_OFFSET_CTRL_ADDR] = 0x10;
+	data->reg[BMA2x2_OFC_SETTING_ADDR] = 0x00;
+	data->reg[0x3d] = 0xff; /* Reserved */
+	data->reg[BMA2x2_FIFO_MODE_ADDR] = 0x00;
+	data->reg[BMA2x2_FIFO_DATA_OUTPUT_ADDR] = 0x00;
+
+	/* Restore registers backed in NVM */
+	bma_emul_restore_nvm(emul);
+}
+
+/**
+ * @brief Convert range in format of RANGE_SELECT register to number of bits
+ *        that should be shifted right to obtain 12 bit reported accelerometer
+ *        value from internal 16 bit value
+ *
+ * @param range Value of RANGE_SELECT register
+ *
+ * @return shift Number of LSB that should be ignored from internal
+ *               accelerometer value
+ */
+static int bma_emul_range_to_shift(uint8_t range)
+{
+	switch (range & BMA2x2_RANGE_SELECT_MSK) {
+	case BMA2x2_RANGE_2G:
+		return 0;
+	case BMA2x2_RANGE_4G:
+		return 1;
+	case BMA2x2_RANGE_8G:
+		return 2;
+	case BMA2x2_RANGE_16G:
+		return 3;
+	default:
+		return -1;
+	}
+}
+
+/**
+ * @brief Handle write requests to NVM control register. Allows to load/store
+ *        NVM only when ready in current NVM control register is set. Load and
+ *        stores to NVM are backed in bma_emul_data structure
+ *
+ * @param emul Pointer to BMA255 emulator
+ * @param val Value that is being written to NVM contorl register
+ *
+ * @return 0 on success
+ */
+static int bma_emul_handle_nvm_write(const struct emul *emul, uint8_t val)
+{
+	struct bma_emul_data *data;
+	uint8_t writes_rem;
+
+	data = emul->data;
+
+	/* NVM not ready, ignore write/load requests */
+	if (!(data->reg[BMA2x2_EEPROM_CTRL_ADDR] & BMA2x2_EEPROM_RDY)) {
+		return 0;
+	}
+
+	/* Restore data from NVM */
+	if (val & BMA2x2_EEPROM_LOAD) {
+		bma_emul_restore_nvm(emul);
+	}
+
+	writes_rem = (data->reg[BMA2x2_EEPROM_CTRL_ADDR] &
+		      BMA2x2_EEPROM_REMAIN_MSK) >>
+		     BMA2x2_EEPROM_REMAIN_OFF;
+	/* Trigger write is set, write is unlocked and writes remaining */
+	if (val & BMA2x2_EEPROM_PROG &&
+	    data->reg[BMA2x2_EEPROM_CTRL_ADDR] & BMA2x2_EEPROM_PROG_EN &&
+	    writes_rem > 0) {
+		data->nvm_x = data->reg[BMA2x2_OFFSET_X_AXIS_ADDR];
+		data->nvm_y = data->reg[BMA2x2_OFFSET_Y_AXIS_ADDR];
+		data->nvm_z = data->reg[BMA2x2_OFFSET_Z_AXIS_ADDR];
+		data->nvm_gp0 = data->reg[BMA2x2_GP0_ADDR];
+		data->nvm_gp1 = data->reg[BMA2x2_GP1_ADDR];
+		/* Decrement number of remaining writes and save it in reg */
+		writes_rem--;
+		data->reg[BMA2x2_EEPROM_CTRL_ADDR] &= ~BMA2x2_EEPROM_REMAIN_MSK;
+		data->reg[BMA2x2_EEPROM_CTRL_ADDR] |=
+			writes_rem << BMA2x2_EEPROM_REMAIN_OFF;
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Clear all interrupt registers
+ *
+ * @param emul Pointer to BMA255 emulator
+ */
+static void bma_emul_clear_int(const struct emul *emul)
+{
+	struct bma_emul_data *data;
+
+	data = emul->data;
+
+	data->reg[BMA2x2_STAT1_ADDR] = 0x00;
+	data->reg[BMA2x2_STAT2_ADDR] = 0x00;
+	data->reg[BMA2x2_STAT_TAP_SLOPE_ADDR] = 0x00;
+	data->reg[BMA2x2_STAT_ORIENT_HIGH_ADDR] = 0x00;
+}
+
+/**
+ * @brief Get target value from offset compensation setting register for given
+ *        @p axis
+ *
+ * @param emul Pointer to BMA255 emulator
+ * @param axis Axis to access: 0 - X, 1 - Y, 2 - Z
+ *
+ * @return target Value to which offset compensation should be calculated
+ */
+static int16_t bma_emul_get_target(const struct emul *emul, int axis)
+{
+	struct bma_emul_data *data;
+	uint8_t target;
+
+	data = emul->data;
+
+	target = data->reg[BMA2x2_OFC_SETTING_ADDR] >>
+		 BMA2x2_OFC_TARGET_AXIS(axis);
+	switch (target) {
+	case BMA2x2_OFC_TARGET_0G:
+		return 0;
+	case BMA2x2_OFC_TARGET_PLUS_1G:
+		return BMA_EMUL_1G;
+	case BMA2x2_OFC_TARGET_MINUS_1G:
+		return -((int)BMA_EMUL_1G);
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Handle writes to offset compensation control register. It allows to
+ *        reset offset registers. It check if offset compenstation is ready
+ *        and if range is set to 2G (required for fast compensation according
+ *        to BMA255 documentation). If fast compensation is successfully
+ *        triggered, internal offset value is set to
+ *        (target - internal accelerometer value).
+ *
+ * @param emul Pointer to BMA255 emulator
+ * @param val Value being written to offset compensation control register
+ *
+ * @return 0 on success
+ * @return -EIO when trying to start fast compensation in wrong emulator state
+ */
+static int bma_emul_handle_off_comp(const struct emul *emul, uint8_t val)
+{
+	struct bma_emul_data *data;
+	uint8_t trigger;
+	int16_t target;
+
+	data = emul->data;
+
+	if (val & BMA2x2_OFFSET_RESET) {
+		data->off_x = 0;
+		data->off_y = 0;
+		data->off_z = 0;
+		data->reg[BMA2x2_OFFSET_X_AXIS_ADDR] = 0;
+		data->reg[BMA2x2_OFFSET_Y_AXIS_ADDR] = 0;
+		data->reg[BMA2x2_OFFSET_Z_AXIS_ADDR] = 0;
+	}
+
+	trigger = (val & BMA2x2_OFFSET_TRIGGER_MASK) >>
+		  BMA2x2_OFFSET_TRIGGER_OFF;
+
+	if (!(data->reg[BMA2x2_OFFSET_CTRL_ADDR] & BMA2x2_OFFSET_CAL_READY)) {
+		if (data->error_on_cal_trg_nrdy && trigger) {
+			LOG_ERR("Trying to start offset comp when not ready");
+			return -EIO;
+		}
+
+		return 0;
+	}
+
+	if (bma_emul_range_to_shift(data->reg[BMA2x2_RANGE_SELECT_ADDR]) != 0 &&
+	    trigger && data->error_on_cal_trg_bad_range) {
+		LOG_ERR("Trying to start offset comp with range other than 2G");
+		return -EIO;
+	}
+
+	switch (trigger) {
+	case 1:
+		target = bma_emul_get_target(emul, BMA_EMUL_AXIS_X);
+		bma_emul_set_off(emul, BMA_EMUL_AXIS_X, target - data->acc_x);
+		break;
+	case 2:
+		target = bma_emul_get_target(emul, BMA_EMUL_AXIS_Y);
+		bma_emul_set_off(emul, BMA_EMUL_AXIS_Y, target - data->acc_y);
+		break;
+	case 3:
+		target = bma_emul_get_target(emul, BMA_EMUL_AXIS_Z);
+		bma_emul_set_off(emul, BMA_EMUL_AXIS_Z, target - data->acc_z);
+		break;
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Handle I2C write message. It is checked if accessed register isn't RO
+ *        and reserved bits are set to 0. Write set value of reg field of bma
+ *        emulator data ignoring reserved bits and write only bits. Some
+ *        commands are handled specialy.
+ *
+ * @param emul Pointer to BMA255 emulator
+ * @param reg Register which is written
+ * @param bytes Number of bytes in I2C write message
+ *
+ * @return 0 on success
+ * @return -EIO on error
+ */
+static int bma_emul_handle_write(const struct emul *emul, int reg, int bytes)
+{
+	struct bma_emul_data *data;
+	uint8_t val;
+	int ret;
+
+	data = emul->data;
+
+	val = data->write_byte;
+
+	if (bytes > 2) {
+		LOG_ERR("Too long write command");
+		return -EIO;
+	}
+
+	/* This write only selected register for I2C read message */
+	if (bytes < 2) {
+		return 0;
+	}
+
+	if (reg <= BMA2x2_STAT_FIFO_ADDR ||
+	    reg >= BMA2x2_FIFO_DATA_OUTPUT_ADDR) {
+		if (data->error_on_ro_write) {
+			LOG_ERR("Writing to reg 0x%x which is RO", reg);
+			return -EIO;
+		}
+
+		return 0;
+	}
+
+	if (data->error_on_rsvd_write && bma_emul_rsvd_mask[reg] & val) {
+		LOG_ERR("Writing 0x%x to reg 0x%x with rsvd bits mask 0x%x",
+			val, reg, bma_emul_rsvd_mask[reg]);
+		return -EIO;
+	}
+
+	switch (reg) {
+	case BMA2x2_RST_ADDR:
+		if (val == BMA2x2_CMD_SOFT_RESET) {
+			bma_emul_reset(emul);
+		}
+		return 0;
+	case BMA2x2_INTR_CTRL_ADDR:
+		if (val & BMA2x2_INTR_CTRL_RST_INT) {
+			bma_emul_clear_int(emul);
+		}
+		/* Don't set write only bit in register */
+		val &= ~BMA2x2_INTR_CTRL_RST_INT;
+		break;
+	case BMA2x2_EEPROM_CTRL_ADDR:
+		bma_emul_handle_nvm_write(emul, val);
+		/* Only programing enable bit is RW */
+		val &= BMA2x2_EEPROM_PROG_EN;
+		val |= data->reg[reg] & ~BMA2x2_EEPROM_PROG_EN;
+		break;
+	case BMA2x2_OFFSET_CTRL_ADDR:
+		ret = bma_emul_handle_off_comp(emul, val);
+		if (ret) {
+			return -EIO;
+		}
+		/* Only slow compensation bits are RW */
+		val &= BMA2x2_OFFSET_CAL_SLOW_X | BMA2x2_OFFSET_CAL_SLOW_Y |
+		       BMA2x2_OFFSET_CAL_SLOW_Z;
+		val |= data->reg[reg] &
+		       ~(BMA2x2_OFFSET_CAL_SLOW_X | BMA2x2_OFFSET_CAL_SLOW_Y |
+			 BMA2x2_OFFSET_CAL_SLOW_Z);
+		break;
+	/* Change internal offset to value set in I2C message */
+	case BMA2x2_OFFSET_X_AXIS_ADDR:
+		data->off_x = bma_emul_nvm_to_off(val);
+		break;
+	case BMA2x2_OFFSET_Y_AXIS_ADDR:
+		data->off_y = bma_emul_nvm_to_off(val);
+		break;
+	case BMA2x2_OFFSET_Z_AXIS_ADDR:
+		data->off_z = bma_emul_nvm_to_off(val);
+		break;
+	case BMA2x2_RANGE_SELECT_ADDR:
+		ret = bma_emul_range_to_shift(val);
+		if (ret < 0) {
+			LOG_ERR("Unknown range select value 0x%x", val);
+			return -EIO;
+		}
+		break;
+	}
+
+	/* Ignore all reserved bits */
+	val &= ~bma_emul_rsvd_mask[reg];
+	val |= data->reg[reg] & bma_emul_rsvd_mask[reg];
+
+	data->reg[reg] = val;
+
+	return 0;
+}
+
+/**
+ * @brief Get set accelerometer value for given register using internal axis
+ *        state @p val. In case of accessing MSB with enabled shadowing,
+ *        check if LSB was accessed first.
+ *
+ * @param emul Pointer to BMA255 emulator
+ * @param lsb_reg LSB register address (BMA2x2_X_AXIS_LSB_ADDR,
+ *                BMA2x2_Y_AXIS_LSB_ADDR, BMA2x2_Z_AXIS_LSB_ADDR)
+ * @param lsb_read Pointer to variable which represent if last access to this
+ *                 accelerometer value was through LSB register
+ * @param lsb True if now accessing LSB, Flase if now accessing MSB
+ * @param val Internal value of accessed accelerometer axis
+ *
+ * @return 0 on success
+ * @return -EIO when accessing MSB before LSB with enabled shadowing
+ */
+static int bma_emul_get_acc_val(const struct emul *emul, int lsb_reg,
+				bool *lsb_read, bool lsb, int16_t val)
+{
+	struct bma_emul_data *data;
+	uint16_t twos_comp_val;
+	uint8_t new_data;
+	int msb_reg;
+	int shift;
+
+	data = emul->data;
+
+	if (lsb) {
+		*lsb_read = 1;
+	} else if (!(data->reg[BMA2x2_DATA_CTRL_ADDR] &
+		     BMA2x2_DATA_SHADOW_DIS)) {
+		/*
+		 * If shadowing is enabled, error on first accessing MSB and
+		 * LSB wasn't accessed before, then return error.
+		 */
+		if (data->error_on_msb_first && !(*lsb_read)) {
+			return -EIO;
+		}
+		*lsb_read = 0;
+		/* If shadowing is enabled, LSB read should set correct value */
+		return 0;
+	}
+
+	twos_comp_val = bma_emul_val_to_twos_comp(val);
+	msb_reg = lsb_reg + 1;
+	shift = bma_emul_range_to_shift(data->reg[BMA2x2_RANGE_SELECT_ADDR]);
+
+	/* Save new data bit from register */
+	new_data = data->reg[lsb_reg] & BMA2x2_AXIS_LSB_NEW_DATA;
+	/* Shift 16 bit value to 12 bit set in range register */
+	twos_comp_val >>= shift;
+	/* Set [3:0] bits in first register */
+	data->reg[lsb_reg] = ((twos_comp_val << 4) & 0xf0) | new_data;
+	/* Set [11:4] bits in second register */
+	data->reg[msb_reg] = (twos_comp_val >> 4) & 0xff;
+
+	return 0;
+}
+
+/** Check description in emul_bma255.h */
+int bma_emul_access_reg(const struct emul *emul, int reg, int bytes, bool read)
+{
+	/*
+	 * Exclude first byte (select register) from total number of bytes
+	 * in I2C write message
+	 */
+	if (!read) {
+		bytes--;
+	}
+
+	if (reg <= BMA2x2_FIFO_DATA_OUTPUT_ADDR &&
+	    reg + bytes >= BMA2x2_FIFO_DATA_OUTPUT_ADDR) {
+		return BMA2x2_FIFO_DATA_OUTPUT_ADDR;
+	}
+
+	return reg + bytes;
+}
+
+/**
+ * @brief Handle I2C read message. Response is obtained from reg field of bma
+ *        emul data. When accessing accelerometer value, register data is first
+ *        computed using internal emulator state.
+ *
+ * @param emul Pointer to BMA255 emulator
+ * @param reg Register address to read
+ * @param val Pointer where resultat should be stored
+ * @param bytes Number of bytes in I2C read message
+ *
+ * @return 0 on success
+ * @return -EIO on error
+ */
+static int bma_emul_handle_read(const struct emul *emul, int reg, uint8_t *val,
+				int bytes)
+{
+	struct bma_emul_data *data;
+	int ret;
+
+	data = emul->data;
+
+	reg = bma_emul_access_reg(emul, reg, bytes, true /* = read */);
+
+	switch (reg) {
+	case BMA2x2_X_AXIS_LSB_ADDR:
+		/* Shouldn't fail for LSB */
+		ret = bma_emul_get_acc_val(emul, reg, &data->lsb_x_read, true,
+					   data->acc_x + data->off_x);
+		break;
+	case BMA2x2_X_AXIS_MSB_ADDR:
+		ret = bma_emul_get_acc_val(emul, reg - 1, &data->lsb_x_read,
+					   false, data->acc_x + data->off_x);
+		if (ret) {
+			LOG_ERR("MSB X readed before LSB X");
+			return -EIO;
+		}
+		break;
+	case BMA2x2_Y_AXIS_LSB_ADDR:
+		/* Shouldn't fail for LSB */
+		ret = bma_emul_get_acc_val(emul, reg, &data->lsb_y_read, true,
+					   data->acc_y + data->off_y);
+		break;
+	case BMA2x2_Y_AXIS_MSB_ADDR:
+		ret = bma_emul_get_acc_val(emul, reg - 1, &data->lsb_y_read,
+					   false, data->acc_y + data->off_y);
+		if (ret) {
+			LOG_ERR("MSB Y readed before LSB Y");
+			return -EIO;
+		}
+		break;
+	case BMA2x2_Z_AXIS_LSB_ADDR:
+		/* Shouldn't fail for LSB */
+		ret = bma_emul_get_acc_val(emul, reg, &data->lsb_z_read, true,
+					   data->acc_z + data->off_z);
+		break;
+	case BMA2x2_Z_AXIS_MSB_ADDR:
+		ret = bma_emul_get_acc_val(emul, reg - 1, &data->lsb_z_read,
+					   false, data->acc_z + data->off_z);
+		if (ret) {
+			LOG_ERR("MSB Z readed before LSB Z");
+			return -EIO;
+		}
+		break;
+	}
+
+	*val = data->reg[reg];
+
+	return 0;
+}
+
+/**
+ * @brief Handle I2C write message. Saves data that will be stored in register.
+ *
+ * @param emul Pointer to BMA emulator
+ * @param reg Register address that is accessed
+ * @param val Data to write to the register
+ * @param bytes Number of bytes already handled in this read message
+ *
+ * @return 0 on success
+ * @return -EIO on error
+ */
+static int bma_emul_write_byte(const struct emul *emul, int reg, uint8_t val,
+			       int bytes)
+{
+	struct bma_emul_data *data;
+
+	data = emul->data;
+
+	data->write_byte = val;
+
+	return 0;
+}
+
+/* Device instantiation */
+
+/**
+ * @brief Set up a new BMA255 emulator
+ *
+ * This should be called for each BMA255 device that needs to be
+ * emulated. It registers it with the I2C emulation controller.
+ *
+ * @param emul Emulation information
+ * @param parent Device to emulate
+ *
+ * @return 0 indicating success (always)
+ */
+static int bma_emul_init(const struct emul *emul, const struct device *parent)
+{
+	struct bma_emul_data *data = emul->data;
+
+	data->common.i2c = parent;
+
+	i2c_common_emul_init(&data->common);
+
+	bma_emul_reset(emul);
+
+	return 0;
+}
+
+#define BMA255_EMUL(n)                                               \
+	static struct bma_emul_data bma_emul_data_##n = {		\
+		.nvm_x = DT_INST_PROP(n, nvm_off_x),			\
+		.nvm_y = DT_INST_PROP(n, nvm_off_y),			\
+		.nvm_z = DT_INST_PROP(n, nvm_off_z),			\
+		.nvm_gp0 = DT_INST_PROP(n, nvm_gp0),			\
+		.nvm_gp1 = DT_INST_PROP(n, nvm_gp1),			\
+		.acc_x = DT_INST_PROP(n, nvm_acc_x),			\
+		.acc_y = DT_INST_PROP(n, nvm_acc_y),			\
+		.acc_z = DT_INST_PROP(n, nvm_acc_z),			\
+		.error_on_cal_trg_nrdy = DT_INST_PROP(n,		\
+				error_on_compensation_not_ready),	\
+		.error_on_ro_write = DT_INST_PROP(n, error_on_ro_write),\
+		.error_on_rsvd_write = DT_INST_PROP(n,			\
+					error_on_reserved_bit_write),	\
+		.error_on_msb_first = DT_INST_PROP(n,			\
+					error_on_msb_first_access),	\
+		.lsb_x_read = 0,					\
+		.lsb_y_read = 0,					\
+		.lsb_z_read = 0,					\
+		.common = {						\
+			.start_write = NULL,				\
+			.write_byte = bma_emul_write_byte,		\
+			.finish_write = bma_emul_handle_write,		\
+			.start_read = NULL,				\
+			.read_byte = bma_emul_handle_read,		\
+			.finish_read = NULL,				\
+			.access_reg = bma_emul_access_reg,		\
+		},							\
+	};         \
+                                                                     \
+	static const struct i2c_common_emul_cfg bma_emul_cfg_##n = { \
+		.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)),      \
+		.data = &bma_emul_data_##n.common,                   \
+		.addr = DT_INST_REG_ADDR(n),                         \
+	};                                                           \
+	EMUL_DT_INST_DEFINE(n, bma_emul_init, &bma_emul_data_##n,    \
+			    &bma_emul_cfg_##n, &i2c_common_emul_api, NULL)
+
+DT_INST_FOREACH_STATUS_OKAY(BMA255_EMUL)
+
+struct i2c_common_emul_data *
+emul_bma_get_i2c_common_data(const struct emul *emul)
+{
+	return emul->data;
+}
+
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
diff --git a/zephyr/emul/emul_bma4xx.c b/zephyr/emul/emul_bma4xx.c
new file mode 100644
index 0000000000..7d432bca0c
--- /dev/null
+++ b/zephyr/emul/emul_bma4xx.c
@@ -0,0 +1,445 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "accelgyro.h"
+#include "driver/accel_bma4xx.h"
+#include "emul/emul_bma4xx.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_stub_device.h"
+#include "i2c.h"
+#include "motion_sense.h"
+
+#include <errno.h>
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/i2c_emul.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/math_extras.h>
+#include <zephyr/ztest.h>
+
+#define DT_DRV_COMPAT cros_bma4xx_emul
+
+LOG_MODULE_REGISTER(bma4xx_emul, LOG_LEVEL_INF);
+
+struct bma4xx_emul_data {
+	struct i2c_common_emul_data i2c;
+	/** True if the sensor is currently enabled. */
+	bool accel_enabled;
+	/** Current sensor range, ±2/4/8/16g; value is positive gs. */
+	uint8_t accel_range;
+	/** Raw register value of ACC_CONF:acc_odr. */
+	uint8_t odr_raw;
+	/** Current sensor reading on XYZ axes, in milli-g. */
+	intv3_t acceleration;
+	/** Axis offset register values, XYZ. */
+	uint8_t offset[3];
+	/** NV_CONF register value. */
+	uint8_t nv_config;
+	/**
+	 * True if the sensor FIFO is currently enabled.
+	 *
+	 * Only headerless mode for the accelerometer alone is supported.
+	 */
+	bool fifo_enabled;
+	/** Pointer to data that will be read from the FIFO. */
+	const uint8_t *fifo_data;
+	/** Number of bytes remaining in fifo_data. */
+	uint16_t fifo_available;
+
+	/** True if in latched interrupt mode, otherwise non-latched. */
+	bool interrupt_mode_latched;
+	/** Raw value of INT1_IO_CTRL register. */
+	uint8_t int1_io_ctrl;
+	/** Raw value of INT_MAP_DATA register. */
+	uint8_t int_map_data;
+};
+
+struct bma4xx_emul_cfg {
+	struct i2c_common_emul_cfg i2c;
+	int sensor_id;
+};
+
+void bma4xx_emul_reset(const struct emul *emul)
+{
+	struct bma4xx_emul_data *data = emul->data;
+
+	i2c_common_emul_set_read_fail_reg(&data->i2c,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_func(&data->i2c, NULL, NULL);
+	i2c_common_emul_set_write_fail_reg(&data->i2c,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_func(&data->i2c, NULL, NULL);
+
+	data->accel_enabled = false;
+	data->accel_range = 2;
+	data->odr_raw = 8;
+	memset(data->acceleration, 0, sizeof(data->acceleration));
+	memset(data->offset, 0, sizeof(data->offset));
+	data->nv_config = 0;
+	data->fifo_enabled = false;
+	data->fifo_data = NULL;
+	data->fifo_available = 0;
+	data->interrupt_mode_latched = false;
+}
+
+struct i2c_common_emul_data *bma4xx_emul_get_i2c(const struct emul *emul)
+{
+	struct bma4xx_emul_data *data = emul->data;
+
+	return &data->i2c;
+}
+
+struct motion_sensor_t *bma4xx_emul_get_sensor_data(const struct emul *emul)
+{
+	return &motion_sensors[bma4xx_emul_get_sensor_num(emul)];
+}
+
+int bma4xx_emul_get_sensor_num(const struct emul *emul)
+{
+	const struct bma4xx_emul_cfg *cfg = emul->cfg;
+
+	return cfg->sensor_id;
+}
+
+bool bma4xx_emul_is_accel_enabled(const struct emul *emul)
+{
+	struct bma4xx_emul_data *data = emul->data;
+
+	return data->accel_enabled;
+}
+
+void bma4xx_emul_set_accel_enabled(const struct emul *emul, bool enabled)
+{
+	struct bma4xx_emul_data *data = emul->data;
+
+	data->accel_enabled = enabled;
+}
+
+uint8_t bma4xx_emul_get_accel_range(const struct emul *emul)
+{
+	struct bma4xx_emul_data *data = emul->data;
+
+	return data->accel_range;
+}
+
+uint32_t bma4xx_emul_get_odr(const struct emul *emul)
+{
+	struct bma4xx_emul_data *data = emul->data;
+
+	/*
+	 * This function deliberately differs from bma4_reg_to_odr() to provide
+	 * an obviously-correct reference for tests.
+	 */
+	switch (data->odr_raw) {
+	case 1:
+		return 781; /* 25/32 Hz */
+	case 2:
+		return 1562; /* 25/16 Hz */
+	case 3:
+		return 3125;
+	case 4:
+		return 6250;
+	case 5:
+		return 12500;
+	case 6:
+		return 25000;
+	case 7:
+		return 50000;
+	case 8:
+		return 100000;
+	case 9:
+		return 200000;
+	case 10:
+		return 400000;
+	case 11:
+		return 800000;
+	case 12:
+		return 1600000;
+	default:
+		LOG_ERR("ODR register value %#x is reserved", data->odr_raw);
+		return 0;
+	}
+}
+
+void bma4xx_emul_set_accel_data(const struct emul *emul, int x, int y, int z)
+{
+	struct bma4xx_emul_data *data = emul->data;
+
+	data->acceleration[0] = x;
+	data->acceleration[1] = y;
+	data->acceleration[2] = z;
+}
+
+void bma4xx_emul_get_offset(const struct emul *emul, int8_t (*offset)[3])
+{
+	struct bma4xx_emul_data *data = emul->data;
+
+	memcpy(offset, data->offset, sizeof(*offset));
+}
+
+uint8_t bma4xx_emul_get_nv_conf(const struct emul *emul)
+{
+	struct bma4xx_emul_data *data = emul->data;
+
+	return data->nv_config;
+}
+
+bool bma4xx_emul_is_fifo_enabled(const struct emul *emul)
+{
+	struct bma4xx_emul_data *data = emul->data;
+
+	return data->fifo_enabled;
+}
+
+void bma4xx_emul_set_fifo_data(const struct emul *emul,
+			       const uint8_t *fifo_data, uint16_t data_sz)
+{
+	struct bma4xx_emul_data *data = emul->data;
+
+	__ASSERT(data_sz % 6 == 0,
+		 "FIFO data should be an integer number of frames");
+	data->fifo_data = fifo_data;
+	data->fifo_available = data_sz;
+}
+
+uint8_t bma4xx_emul_get_interrupt_config(const struct emul *emul,
+					 uint8_t *int1_io_ctrl,
+					 bool *latched_mode)
+{
+	struct bma4xx_emul_data *data = emul->data;
+
+	*int1_io_ctrl = data->int1_io_ctrl;
+	*latched_mode = data->interrupt_mode_latched;
+	return data->int_map_data;
+}
+
+static int bma4xx_emul_read_byte(const struct emul *target, int reg,
+				 uint8_t *val, int bytes)
+{
+	struct bma4xx_emul_data *data = target->data;
+
+	if (reg != BMA4_FIFO_DATA_ADDR) {
+		/*
+		 * Burst reads autoincrement register addresses, except for
+		 * FIFO data which reads from the FIFO instead.
+		 */
+		reg += bytes;
+	}
+
+	switch (reg) {
+	case BMA4_CHIP_ID_ADDR:
+		*val = 0x12; /* BMA422_CHIP_ID */
+		return 0;
+	case BMA4_DATA_8_ADDR: /* ACC_X(LSB) */
+		*val = (data->acceleration[0] & GENMASK(3, 0)) << 4;
+		return 0;
+	case BMA4_DATA_8_ADDR + 1: /* ACC_X(MSB) */
+		*val = (data->acceleration[0] >> 4) & GENMASK(7, 0);
+		return 0;
+	case BMA4_DATA_8_ADDR + 2: /* ACC_Y(LSB) */
+		*val = (data->acceleration[1] & GENMASK(3, 0)) << 4;
+		return 0;
+	case BMA4_DATA_8_ADDR + 3: /* ACC_Y(MSB) */
+		*val = (data->acceleration[1] >> 4) & GENMASK(7, 0);
+		return 0;
+	case BMA4_DATA_8_ADDR + 4: /* ACC_Z(LSB) */
+		*val = (data->acceleration[2] & GENMASK(3, 0)) << 4;
+		return 0;
+	case BMA4_DATA_8_ADDR + 5: /* ACC_Z(MSB) */
+		*val = (data->acceleration[2] >> 4) & GENMASK(7, 0);
+		return 0;
+	case BMA4_INT_STAT_1_ADDR:
+		*val = data->fifo_available > 0 ? 0x80 : 0; /* acc_drdy_int */
+		return 0;
+	case BMA4_FIFO_LENGTH_0_ADDR: /* LSB */
+		*val = data->fifo_available & 0xFF;
+		return 0;
+	case BMA4_FIFO_LENGTH_0_ADDR + 1: /* MSB */
+		*val = data->fifo_available >> 8;
+		return 0;
+	case BMA4_FIFO_DATA_ADDR:
+		/*
+		 * Read FIFO data; only supporting headerless mode with accel
+		 * data only.
+		 *
+		 * Partial reads (of less than an entire frame) do not consume
+		 * FIFO data, so we track the amount read in this burst. Reading
+		 * past the end of the FIFO returns 0x8000.
+		 */
+		if (bytes % 6 >= data->fifo_available) {
+			/* Out of data. */
+			if (bytes % 2 == 0) {
+				*val = 0;
+			} else {
+				*val = 0x80;
+			}
+			return 0;
+		}
+		*val = data->fifo_data[bytes % 6];
+		if (bytes % 6 == 5) {
+			/* Consume frame after reading the entire thing. */
+			data->fifo_data += 6;
+			data->fifo_available -= 6;
+		}
+		return 0;
+	case BMA4_ACCEL_CONFIG_ADDR:
+		*val = data->odr_raw | 0xA0;
+		return 0;
+	case BMA4_ACCEL_RANGE_ADDR:
+		*val = u32_count_trailing_zeros(data->accel_range) - 1;
+		__ASSERT_NO_MSG(*val >= 0 && *val <= 3);
+		return 0;
+	case BMA4_NV_CONFIG_ADDR:
+		*val = data->nv_config;
+		return 0;
+	case BMA4_FIFO_CONFIG_1_ADDR:
+		*val = data->fifo_enabled ? BMA4_FIFO_ACC_EN : 0;
+		return 0;
+	case BMA4_INT_LATCH_ADDR:
+		*val = data->interrupt_mode_latched ? 1 : 0;
+		return 0;
+	case BMA4_OFFSET_0_ADDR:
+	case BMA4_OFFSET_1_ADDR:
+	case BMA4_OFFSET_2_ADDR:
+		*val = data->offset[reg - BMA4_OFFSET_0_ADDR];
+		return 0;
+	case BMA4_POWER_CTRL_ADDR:
+		*val = data->accel_enabled ? BMA4_ACCEL_ENABLE_MSK : 0;
+		return 0;
+	}
+
+	LOG_WRN("unhandled I2C read from register %#x", reg);
+	return -ENOTSUP;
+}
+
+static int bma4xx_emul_write_byte(const struct emul *target, int reg,
+				  uint8_t val, int bytes)
+{
+	struct bma4xx_emul_data *data = target->data;
+
+	if (bytes != 1) {
+		LOG_ERR("multi-byte writes are not supported");
+		return -ENOTSUP;
+	}
+
+	switch (reg) {
+	case BMA4_ACCEL_CONFIG_ADDR:
+		if ((val & 0xF0) != 0xA0) {
+			LOG_ERR("unsupported acc_bwp/acc_perf_mode: %#x", val);
+			return -EINVAL;
+		}
+		data->odr_raw = val & BMA4_ACCEL_ODR_MSK;
+		return 0;
+	case BMA4_ACCEL_RANGE_ADDR:
+		if ((val & GENMASK(1, 0)) != val) {
+			LOG_ERR("reserved bits set in ACC_RANGE write: %#x",
+				val);
+			return -EINVAL;
+		}
+		/* 0 => 2, 1 => 4, ... 3 => 16 */
+		data->accel_range = 2 << val;
+		return 0;
+	case BMA4_FIFO_CONFIG_1_ADDR:
+		if (val & ~BMA4_FIFO_ACC_EN) {
+			LOG_ERR("unsupported bits set in FIFO_CONFIG_1"
+				" write: %#x",
+				val);
+			return -EINVAL;
+		}
+		data->fifo_enabled = (val & BMA4_FIFO_ACC_EN) != 0;
+		return 0;
+	case BMA4_INT1_IO_CTRL_ADDR:
+		data->int1_io_ctrl = val;
+		return 0;
+	case BMA4_INT_LATCH_ADDR:
+		if ((val & ~1) != 0) {
+			LOG_ERR("reserved bits set in INT_LATCH: %#x", val);
+			return -EINVAL;
+		}
+		data->interrupt_mode_latched = (val & 1) == 1;
+		return 0;
+	case BMA4_INT_MAP_DATA_ADDR:
+		data->int_map_data = val;
+		return 0;
+	case BMA4_NV_CONFIG_ADDR:
+		if (val & GENMASK(7, 4)) {
+			LOG_ERR("reserved bits set in NV_CONF write: %#x", val);
+			return -EINVAL;
+		}
+		data->nv_config = val;
+		return 0;
+	case BMA4_OFFSET_0_ADDR:
+	case BMA4_OFFSET_1_ADDR:
+	case BMA4_OFFSET_2_ADDR:
+		data->offset[reg - BMA4_OFFSET_0_ADDR] = val;
+		return 0;
+	case BMA4_POWER_CTRL_ADDR:
+		if ((val & ~BMA4_ACCEL_ENABLE_MSK) != 0) {
+			LOG_ERR("unhandled bits in POWER_CTRL write: %#x", val);
+			return -ENOTSUP;
+		}
+		data->accel_enabled = (val & BMA4_ACCEL_ENABLE_MSK) != 0;
+		return 0;
+	case BMA4_CMD_ADDR:
+		if (val == 0xb0) { /* fifo_flush */
+			data->fifo_data = NULL;
+			data->fifo_available = 0;
+			return 0;
+		}
+		break;
+	}
+
+	LOG_WRN("unhandled I2C write to register %#x", reg);
+	return -ENOTSUP;
+}
+
+static int bma4xx_emul_init(const struct emul *emul,
+			    const struct device *parent)
+{
+	struct bma4xx_emul_data *data = emul->data;
+
+	data->i2c.i2c = parent;
+	i2c_common_emul_init(&data->i2c);
+	bma4xx_emul_reset(emul);
+
+	return 0;
+}
+
+#define INIT_BMA4XX(n)                                                    \
+	static struct bma4xx_emul_data bma4xx_emul_data_##n = {         \
+		.i2c = {                                                \
+			.write_byte = bma4xx_emul_write_byte,           \
+			.read_byte = bma4xx_emul_read_byte,             \
+			.i2c = DEVICE_DT_GET(DT_INST_PARENT(n)),        \
+		},                                                      \
+	}; \
+	static const struct bma4xx_emul_cfg bma4xx_emul_cfg_##n = {	\
+		.i2c = {                                                \
+			.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)), \
+			.addr = DT_INST_REG_ADDR(n),                    \
+		},						        \
+		.sensor_id = SENSOR_ID(DT_INST_PHANDLE(n,               \
+						       motionsense_sensor)), \
+	};     \
+	EMUL_DT_INST_DEFINE(n, bma4xx_emul_init, &bma4xx_emul_data_##n,   \
+			    &bma4xx_emul_cfg_##n, &i2c_common_emul_api, NULL)
+
+DT_INST_FOREACH_STATUS_OKAY(INIT_BMA4XX)
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
+
+static void bma4xx_emul_reset_rule_before(const struct ztest_unit_test *test,
+					  void *data)
+{
+	ARG_UNUSED(test);
+	ARG_UNUSED(data);
+
+#define BMA4XX_EMUL_RESET_RULE_BEFORE(n) \
+	bma4xx_emul_reset(EMUL_DT_GET(DT_DRV_INST(n)))
+
+	DT_INST_FOREACH_STATUS_OKAY(BMA4XX_EMUL_RESET_RULE_BEFORE);
+}
+ZTEST_RULE(bma4xx_emul_reset, bma4xx_emul_reset_rule_before, NULL);
diff --git a/zephyr/emul/emul_bmi.c b/zephyr/emul/emul_bmi.c
new file mode 100644
index 0000000000..f80c8202b1
--- /dev/null
+++ b/zephyr/emul/emul_bmi.c
@@ -0,0 +1,1118 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/accelgyro_bmi160.h"
+#include "driver/accelgyro_bmi260.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "emul/emul_bmi.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_stub_device.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/i2c_emul.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/__assert.h>
+
+#define DT_DRV_COMPAT zephyr_bmi_emul
+
+#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
+LOG_MODULE_REGISTER(emul_bmi);
+
+/** Run-time data used by the emulator */
+struct bmi_emul_data {
+	/** Common I2C data */
+	struct i2c_common_emul_data common;
+
+	/** Current state of all emulated BMI registers */
+	uint8_t reg[BMI_EMUL_MAX_REG];
+	/** Internal offset values used in calculations */
+	int16_t off_acc_x;
+	int16_t off_acc_y;
+	int16_t off_acc_z;
+	int16_t off_gyr_x;
+	int16_t off_gyr_y;
+	int16_t off_gyr_z;
+	/** Internal values of sensors */
+	int32_t acc_x;
+	int32_t acc_y;
+	int32_t acc_z;
+	int32_t gyr_x;
+	int32_t gyr_y;
+	int32_t gyr_z;
+	/** Current state of NVM where offset and configuration can be saved */
+	uint8_t nvm[BMI_EMUL_MAX_NVM_REGS];
+
+	/** Return error when trying to write to RO register */
+	bool error_on_ro_write;
+	/** Return error when trying to write 1 to reserved bit */
+	bool error_on_rsvd_write;
+	/**
+	 * If effect of command is vissable after simulated time from issuing
+	 * command
+	 */
+	bool simulate_command_exec_time;
+	/** Return error when trying to read WO register */
+	bool error_on_wo_read;
+
+	/** Value of data byte in ongoing write message */
+	uint8_t write_byte;
+
+	/** List of FIFO frames */
+	struct bmi_emul_frame *fifo_frame;
+	/** First FIFO frame in byte format */
+	uint8_t fifo[21];
+	/** Number of FIFO frames that were skipped */
+	uint8_t fifo_skip;
+	/** Currently accessed byte of first frame */
+	int fifo_frame_byte;
+	/** Length of first frame */
+	int fifo_frame_len;
+
+	/** Last time when emulator was resetted in sensor time units */
+	int64_t zero_time;
+	/** Time when current command should end */
+	uint32_t cmd_end_time;
+
+	/** Emulated model of BMI */
+	int type;
+	/** Pointer to data specific for emulated model of BMI */
+	const struct bmi_emul_type_data *type_data;
+};
+
+/** Check description in emul_bmi.h */
+void bmi_emul_set_reg(const struct emul *emul, int reg, uint8_t val)
+{
+	struct bmi_emul_data *data;
+
+	if (reg < 0 || reg > BMI_EMUL_MAX_REG) {
+		return;
+	}
+
+	data = emul->data;
+	data->reg[reg] = val;
+}
+
+/** Check description in emul_bmi.h */
+uint8_t bmi_emul_get_reg(const struct emul *emul, int reg)
+{
+	struct bmi_emul_data *data;
+
+	if (reg < 0 || reg > BMI_EMUL_MAX_REG) {
+		return 0;
+	}
+
+	data = emul->data;
+
+	return data->reg[reg];
+}
+
+/**
+ * @brief Convert @p val to two's complement representation. It makes sure that
+ *        bit representation is correct even on platforms which represent
+ *        signed inteager in different format. Unsigned bit representation
+ *        allows to use well defined bitwise operations on returned value.
+ *
+ * @param val Inteager that is converted
+ *
+ * @return two's complement representation of @p val
+ */
+static uint32_t bmi_emul_val_to_twos_comp(int32_t val)
+{
+	uint32_t twos_comp_val;
+
+	/* Make sure that value is converted to twos compliment format */
+	if (val < 0) {
+		twos_comp_val = (uint32_t)(-val);
+		twos_comp_val = ~twos_comp_val + 1;
+	} else {
+		twos_comp_val = (uint32_t)val;
+	}
+
+	return twos_comp_val;
+}
+
+/**
+ * @brief Convert accelerometer value from NVM format (8bit, 0x01 == 3.9mg)
+ *        to internal offset format (16bit, 0x01 == 0.061mg).
+ *
+ * @param nvm Value in NVM format (8bit, 0x01 == 3.9mg). This is binary
+ *            representation of two's complement signed number.
+ *
+ * @return offset Internal representation of @p nvm (16bit, 0x01 == 0.061mg)
+ */
+static int16_t bmi_emul_acc_nvm_to_off(uint8_t nvm)
+{
+	int16_t offset;
+	int8_t sign;
+
+	if (nvm & BIT(7)) {
+		sign = -1;
+		/* NVM value is in two's complement format */
+		nvm = ~nvm + 1;
+	} else {
+		sign = 1;
+	}
+
+	offset = (int16_t)nvm;
+	/* LSB in NVM is 3.9mg, while LSB in internal offset is 0.061mg */
+	offset *= sign * 64;
+
+	return offset;
+}
+
+/**
+ * @brief Convert gyroscope value from NVM format (10bit, 0x01 == 0.061 °/s)
+ *        to internal offset format (16bit, 0x01 == 0.0038 °/s)
+ *
+ * @param nvm Value in NVM format (10bit, 0x01 == 0.061 °/s). This is binary
+ *            representation of two's complement signed number.
+ *
+ * @return offset Internal representation of @p nvm (16bit, 0x01 == 0.0038 °/s)
+ */
+static int16_t bmi_emul_gyr_nvm_to_off(uint16_t nvm)
+{
+	int16_t offset;
+	int8_t sign;
+
+	if (nvm & BIT(9)) {
+		sign = -1;
+		/* NVM value is in two's complement format */
+		nvm = ~nvm + 1;
+	} else {
+		sign = 1;
+	}
+
+	/* Mask 10 bits which holds value */
+	nvm &= 0x3ff;
+
+	offset = (int16_t)nvm;
+	/* LSB in NVM is 0.061°/s, while LSB in internal offset is 0.0038°/s */
+	offset *= sign * 16;
+
+	return offset;
+}
+
+/**
+ * @brief Convert accelerometer value from internal offset format
+ *        (16bit, 0x01 == 0.061mg) to NVM format (8bit, 0x01 == 7.8mg).
+ *        Function makes sure that NVM value is representation of two's
+ *        complement signed number.
+ *
+ * @param val Value in internal offset format (16bit, 0x01 == 0.061mg).
+ *
+ * @return nvm NVM format representation of @p val (8bit, 0x01 == 3.9mg)
+ */
+static uint8_t bmi_emul_acc_off_to_nvm(int16_t off)
+{
+	uint32_t twos_comp_val;
+	uint8_t nvm = 0;
+
+	twos_comp_val = bmi_emul_val_to_twos_comp(off);
+
+	/*
+	 * LSB in internal representation has value 0.061mg, while in NVM
+	 * LSB is 3.9mg. Skip 0.06mg, 0.12mg, 0.24mg, 0.48mg, 0.97mg and
+	 * 1.9mg bits.
+	 */
+	nvm |= (twos_comp_val >> 6) & 0x7f;
+	/* Set sign bit */
+	nvm |= (twos_comp_val & BIT(31)) ? BIT(7) : 0x00;
+
+	return nvm;
+}
+
+/**
+ * @brief Convert gyroscope value from internal offset format
+ *        (16bit, 0x01 == 0.0038°/s) to NVM format (10bit, 0x01 == 0.061°/s).
+ *        Function makes sure that NVM value is representation of two's
+ *        complement signed number.
+ *
+ * @param val Value in internal offset format (16bit, 0x01 == 0.0038°/s).
+ *
+ * @return nvm NVM format representation of @p val (10bit, 0x01 == 0.061°/s)
+ */
+static uint16_t bmi_emul_gyr_off_to_nvm(int16_t off)
+{
+	uint32_t twos_comp_val;
+	uint16_t nvm = 0;
+
+	twos_comp_val = bmi_emul_val_to_twos_comp(off);
+
+	/*
+	 * LSB in internal representation has value 0.0038°/s, while in NVM
+	 * LSB is 0.061°/s. Skip 0.0038°/s, 0.0076°/s, 0.015°/s, and
+	 * 0.03°/s bits.
+	 */
+	nvm |= (twos_comp_val >> 4) & 0x1ff;
+	/* Set sign bit */
+	nvm |= (twos_comp_val & BIT(31)) ? BIT(9) : 0x00;
+
+	return nvm;
+}
+
+/** Check description in emul_bmi.h */
+int16_t bmi_emul_get_off(const struct emul *emul, enum bmi_emul_axis axis)
+{
+	struct bmi_emul_data *data;
+
+	data = emul->data;
+
+	switch (axis) {
+	case BMI_EMUL_ACC_X:
+		return data->off_acc_x;
+	case BMI_EMUL_ACC_Y:
+		return data->off_acc_y;
+	case BMI_EMUL_ACC_Z:
+		return data->off_acc_z;
+	case BMI_EMUL_GYR_X:
+		return data->off_gyr_x;
+	case BMI_EMUL_GYR_Y:
+		return data->off_gyr_y;
+	case BMI_EMUL_GYR_Z:
+		return data->off_gyr_z;
+	}
+
+	return 0;
+}
+
+/** Check description in emul_bmi.h */
+void bmi_emul_set_off(const struct emul *emul, enum bmi_emul_axis axis,
+		      int16_t val)
+{
+	struct bmi_emul_data *data;
+	uint16_t gyr_off;
+	uint8_t gyr98_shift;
+
+	data = emul->data;
+
+	switch (axis) {
+	case BMI_EMUL_ACC_X:
+		data->off_acc_x = val;
+		data->reg[data->type_data->acc_off_reg] =
+			bmi_emul_acc_off_to_nvm(data->off_acc_x);
+		break;
+	case BMI_EMUL_ACC_Y:
+		data->off_acc_y = val;
+		data->reg[data->type_data->acc_off_reg + 1] =
+			bmi_emul_acc_off_to_nvm(data->off_acc_y);
+		break;
+	case BMI_EMUL_ACC_Z:
+		data->off_acc_z = val;
+		data->reg[data->type_data->acc_off_reg + 2] =
+			bmi_emul_acc_off_to_nvm(data->off_acc_z);
+		break;
+	case BMI_EMUL_GYR_X:
+		data->off_gyr_x = val;
+		gyr_off = bmi_emul_gyr_off_to_nvm(data->off_gyr_x);
+		data->reg[data->type_data->gyr_off_reg] = gyr_off & 0xff;
+		gyr98_shift = 0;
+		data->reg[data->type_data->gyr98_off_reg] &=
+			~(0x3 << gyr98_shift);
+		data->reg[data->type_data->gyr98_off_reg] |=
+			(gyr_off & 0x300) >> (8 - gyr98_shift);
+		break;
+	case BMI_EMUL_GYR_Y:
+		data->off_gyr_y = val;
+		gyr_off = bmi_emul_gyr_off_to_nvm(data->off_gyr_y);
+		data->reg[data->type_data->gyr_off_reg + 1] = gyr_off & 0xff;
+		gyr98_shift = 2;
+		data->reg[data->type_data->gyr98_off_reg] &=
+			~(0x3 << gyr98_shift);
+		data->reg[data->type_data->gyr98_off_reg] |=
+			(gyr_off & 0x300) >> (8 - gyr98_shift);
+		break;
+	case BMI_EMUL_GYR_Z:
+		data->off_gyr_z = val;
+		gyr_off = bmi_emul_gyr_off_to_nvm(data->off_gyr_z);
+		data->reg[data->type_data->gyr_off_reg + 2] = gyr_off & 0xff;
+		gyr98_shift = 4;
+		data->reg[data->type_data->gyr98_off_reg] &=
+			~(0x3 << gyr98_shift);
+		data->reg[data->type_data->gyr98_off_reg] |=
+			(gyr_off & 0x300) >> (8 - gyr98_shift);
+		break;
+	}
+}
+
+/** Check description in emul_bmi.h */
+int32_t bmi_emul_get_value(const struct emul *emul, enum bmi_emul_axis axis)
+{
+	struct bmi_emul_data *data;
+
+	data = emul->data;
+
+	switch (axis) {
+	case BMI_EMUL_ACC_X:
+		return data->acc_x;
+	case BMI_EMUL_ACC_Y:
+		return data->acc_y;
+	case BMI_EMUL_ACC_Z:
+		return data->acc_z;
+	case BMI_EMUL_GYR_X:
+		return data->gyr_x;
+	case BMI_EMUL_GYR_Y:
+		return data->gyr_y;
+	case BMI_EMUL_GYR_Z:
+		return data->gyr_z;
+	}
+
+	return 0;
+}
+
+/** Check description in emul_bmi.h */
+void bmi_emul_set_value(const struct emul *emul, enum bmi_emul_axis axis,
+			int32_t val)
+{
+	struct bmi_emul_data *data;
+
+	data = emul->data;
+
+	switch (axis) {
+	case BMI_EMUL_ACC_X:
+		data->acc_x = val;
+		break;
+	case BMI_EMUL_ACC_Y:
+		data->acc_y = val;
+		break;
+	case BMI_EMUL_ACC_Z:
+		data->acc_z = val;
+		break;
+	case BMI_EMUL_GYR_X:
+		data->gyr_x = val;
+		break;
+	case BMI_EMUL_GYR_Y:
+		data->gyr_y = val;
+		break;
+	case BMI_EMUL_GYR_Z:
+		data->gyr_z = val;
+		break;
+	}
+}
+
+/** Check description in emul_bmi.h */
+void bmi_emul_set_err_on_ro_write(const struct emul *emul, bool set)
+{
+	struct bmi_emul_data *data;
+
+	data = emul->data;
+	data->error_on_ro_write = set;
+}
+
+/** Check description in emul_bmi.h */
+void bmi_emul_set_err_on_rsvd_write(const struct emul *emul, bool set)
+{
+	struct bmi_emul_data *data;
+
+	data = emul->data;
+	data->error_on_rsvd_write = set;
+}
+
+/** Check description in emul_bmi.h */
+void bmi_emul_set_err_on_wo_read(const struct emul *emul, bool set)
+{
+	struct bmi_emul_data *data;
+
+	data = emul->data;
+	data->error_on_wo_read = set;
+}
+
+/** Check description in emul_bmi.h */
+void bmi_emul_simulate_cmd_exec_time(const struct emul *emul, bool set)
+{
+	struct bmi_emul_data *data;
+
+	data = emul->data;
+	data->simulate_command_exec_time = set;
+}
+
+/** Check description in emul_bmi.h */
+void bmi_emul_set_skipped_frames(const struct emul *emul, uint8_t skip)
+{
+	struct bmi_emul_data *data;
+
+	data = emul->data;
+
+	data->fifo_skip = skip;
+}
+
+/**
+ * @brief Convert current time to sensor time (39 us units)
+ *
+ * @return time in 39 us units
+ */
+static int64_t bmi_emul_get_sensortime(void)
+{
+	return k_uptime_ticks() * 1000000 / 39 / CONFIG_SYS_CLOCK_TICKS_PER_SEC;
+}
+
+/**
+ * @brief Set registers at address @p reg with sensor time that elapsed since
+ *        last reset of emulator
+ *
+ * @param emul Pointer to BMI emulator
+ * @param reg Pointer to 3 byte array, where current sensor time should be
+ *            stored
+ */
+static void bmi_emul_set_sensortime_reg(const struct emul *emul, uint8_t *reg)
+{
+	struct bmi_emul_data *data;
+	uint32_t twos_comp_val;
+	int64_t time;
+
+	data = emul->data;
+
+	time = bmi_emul_get_sensortime();
+
+	twos_comp_val = bmi_emul_val_to_twos_comp(time - data->zero_time);
+
+	*reg = twos_comp_val & 0xff;
+	*(reg + 1) = (twos_comp_val >> 8) & 0xff;
+	*(reg + 2) = (twos_comp_val >> 16) & 0xff;
+}
+
+/**
+ * @brief Convert given sensor axis @p val from internal units to register
+ *        units. It shifts value by @p shift bits to the right to account
+ *        range set in emulator's registers. Result is saved at address @p reg
+ *
+ * @param emul Pointer to BMI emulator
+ * @param val Accelerometer or gyroscope value in internal units
+ * @param reg Pointer to 2 byte array, where sensor value should be stored
+ * @param shift How many bits should be shift to the right
+ */
+static void bmi_emul_set_data_reg(const struct emul *emul, int32_t val,
+				  uint8_t *reg, int shift)
+{
+	struct bmi_emul_data *data;
+	uint32_t twos_comp_val;
+
+	data = emul->data;
+
+	twos_comp_val = bmi_emul_val_to_twos_comp(val);
+
+	/* Shift unused bits because of selected range */
+	twos_comp_val >>= shift;
+
+	*reg = twos_comp_val & 0xff;
+	*(reg + 1) = (twos_comp_val >> 8) & 0xff;
+}
+
+/**
+ * @brief Compute length of given FIFO @p frame. If frame is null then length
+ *        of empty frame is returned.
+ *
+ * @param emul Pointer to BMI emulator
+ * @param frame Pointer to FIFO frame
+ * @param tag_time Indicate if sensor time should be included in empty frame
+ * @param header Indicate if header should be included in frame
+ *
+ * @return length of frame
+ */
+static uint8_t bmi_emul_get_frame_len(const struct emul *emul,
+				      struct bmi_emul_frame *frame,
+				      bool tag_time, bool header)
+{
+	struct bmi_emul_data *data;
+	int len;
+
+	data = emul->data;
+
+	/* Empty FIFO frame */
+	if (frame == NULL) {
+		if (tag_time && header) {
+			/* Header of sensortime + sensortime + empty FIFO */
+			return 5;
+		}
+
+		/* Empty fifo */
+		return 1;
+	}
+
+	/* Config FIFO frame */
+	if (frame->type & BMI_EMUL_FRAME_CONFIG) {
+		if (header) {
+			/* Header + byte of data */
+			len = 2;
+			if (data->type_data->sensortime_follow_config_frame) {
+				/* Sensortime data */
+				len += 3;
+			}
+
+			return len;
+		}
+
+		/* This frame doesn't exist in headerless mode */
+		return 0;
+	}
+
+	/* Sensor data FIFO frame */
+	if (header) {
+		len = 1;
+	} else {
+		len = 0;
+	}
+
+	if (frame->type & BMI_EMUL_FRAME_ACC) {
+		len += 6;
+	}
+	if (frame->type & BMI_EMUL_FRAME_MAG) {
+		len += 8;
+	}
+	if (frame->type & BMI_EMUL_FRAME_GYR) {
+		len += 6;
+	}
+
+	return len;
+}
+
+/**
+ * @brief Set given FIFO @p frame as current frame in fifo field of emulator
+ *        data structure
+ *
+ * @param emul Pointer to BMI emulator
+ * @param frame Pointer to FIFO frame
+ * @param tag_time Indicate if sensor time should be included in empty frame
+ * @param header Indicate if header should be included in frame
+ * @param acc_shift How many bits should be right shifted from accelerometer
+ *                  data
+ * @param gyr_shift How many bits should be right shifted from gyroscope data
+ */
+static void bmi_emul_set_current_frame(const struct emul *emul,
+				       struct bmi_emul_frame *frame,
+				       bool tag_time, bool header,
+				       int acc_shift, int gyr_shift)
+{
+	struct bmi_emul_data *data;
+	int i = 0;
+
+	data = emul->data;
+
+	data->fifo_frame_byte = 0;
+	data->fifo_frame_len =
+		bmi_emul_get_frame_len(emul, frame, tag_time, header);
+	/* Empty FIFO frame */
+	if (frame == NULL) {
+		if (tag_time && header) {
+			/* Header */
+			data->fifo[0] = BMI_EMUL_FIFO_HEAD_TIME;
+			bmi_emul_set_sensortime_reg(emul, &(data->fifo[1]));
+			i = 4;
+		}
+
+		/* Empty header */
+		data->fifo[i] = BMI_EMUL_FIFO_HEAD_EMPTY;
+
+		return;
+	}
+
+	/* Config FIFO frame */
+	if (frame->type & BMI_EMUL_FRAME_CONFIG) {
+		/* Header */
+		data->fifo[0] = BMI_EMUL_FIFO_HEAD_CONFIG;
+		data->fifo[1] = frame->config;
+		if (data->type_data->sensortime_follow_config_frame) {
+			bmi_emul_set_sensortime_reg(emul, &(data->fifo[2]));
+		}
+
+		return;
+	}
+
+	/* Sensor data FIFO frame */
+	if (header) {
+		data->fifo[0] = BMI_EMUL_FIFO_HEAD_DATA;
+		data->fifo[0] |= frame->type & BMI_EMUL_FRAME_MAG ?
+					 BMI_EMUL_FIFO_HEAD_DATA_MAG :
+					 0;
+		data->fifo[0] |= frame->type & BMI_EMUL_FRAME_GYR ?
+					 BMI_EMUL_FIFO_HEAD_DATA_GYR :
+					 0;
+		data->fifo[0] |= frame->type & BMI_EMUL_FRAME_ACC ?
+					 BMI_EMUL_FIFO_HEAD_DATA_ACC :
+					 0;
+		data->fifo[0] |= frame->tag & BMI_EMUL_FIFO_HEAD_DATA_TAG_MASK;
+		i = 1;
+	}
+
+	if (frame->type & BMI_EMUL_FRAME_MAG) {
+		bmi_emul_set_data_reg(emul, frame->mag_x, &(data->fifo[i]), 0);
+		i += 2;
+		bmi_emul_set_data_reg(emul, frame->mag_y, &(data->fifo[i]), 0);
+		i += 2;
+		bmi_emul_set_data_reg(emul, frame->mag_z, &(data->fifo[i]), 0);
+		i += 2;
+		bmi_emul_set_data_reg(emul, frame->rhall, &(data->fifo[i]), 0);
+		i += 2;
+	}
+
+	if (frame->type & BMI_EMUL_FRAME_GYR) {
+		bmi_emul_set_data_reg(emul, frame->gyr_x, &(data->fifo[i]),
+				      gyr_shift);
+		i += 2;
+		bmi_emul_set_data_reg(emul, frame->gyr_y, &(data->fifo[i]),
+				      gyr_shift);
+		i += 2;
+		bmi_emul_set_data_reg(emul, frame->gyr_z, &(data->fifo[i]),
+				      gyr_shift);
+		i += 2;
+	}
+
+	if (frame->type & BMI_EMUL_FRAME_ACC) {
+		bmi_emul_set_data_reg(emul, frame->acc_x, &(data->fifo[i]),
+				      acc_shift);
+		i += 2;
+		bmi_emul_set_data_reg(emul, frame->acc_y, &(data->fifo[i]),
+				      acc_shift);
+		i += 2;
+		bmi_emul_set_data_reg(emul, frame->acc_z, &(data->fifo[i]),
+				      acc_shift);
+		i += 2;
+	}
+}
+
+/**
+ * @brief Update internal sensors offset values using values from emulated
+ *        registers.
+ *
+ * @param emul Pointer to BMI emulator
+ */
+static void bmi_emul_updata_int_off(const struct emul *emul)
+{
+	struct bmi_emul_data *data;
+	uint16_t gyr_nvm;
+	uint8_t gyr98;
+
+	data = emul->data;
+
+	data->off_acc_x = bmi_emul_acc_nvm_to_off(
+		data->reg[data->type_data->acc_off_reg]);
+	data->off_acc_y = bmi_emul_acc_nvm_to_off(
+		data->reg[data->type_data->acc_off_reg + 1]);
+	data->off_acc_z = bmi_emul_acc_nvm_to_off(
+		data->reg[data->type_data->acc_off_reg + 2]);
+
+	gyr98 = data->reg[data->type_data->gyr98_off_reg];
+
+	gyr_nvm = data->reg[data->type_data->gyr_off_reg];
+	gyr_nvm |= (gyr98 & 0x3) << 8;
+	data->off_gyr_x = bmi_emul_gyr_nvm_to_off(gyr_nvm);
+	gyr_nvm = data->reg[data->type_data->gyr_off_reg + 1];
+	gyr_nvm |= (gyr98 & 0xc) << 6;
+	data->off_gyr_y = bmi_emul_gyr_nvm_to_off(gyr_nvm);
+	gyr_nvm = data->reg[data->type_data->gyr_off_reg + 2];
+	gyr_nvm |= (gyr98 & 0x30) << 4;
+	data->off_gyr_z = bmi_emul_gyr_nvm_to_off(gyr_nvm);
+}
+
+/**
+ * @brief Restore registers backed in NVM to emulator's registers. Each model
+ *        of BMI may have different set of NVM backed registers.
+ *
+ * @param emul Pointer to BMI emulator
+ */
+static void bmi_emul_restore_nvm(const struct emul *emul)
+{
+	struct bmi_emul_data *data;
+	int i;
+
+	data = emul->data;
+
+	__ASSERT_NO_MSG(data->type_data->nvm_len <= BMI_EMUL_MAX_NVM_REGS);
+
+	/* Restore registers values */
+	for (i = 0; i < data->type_data->nvm_len; i++) {
+		data->reg[data->type_data->nvm_reg[i]] = data->nvm[i];
+	}
+
+	bmi_emul_updata_int_off(emul);
+}
+
+/** Check description in emul_bmi.h */
+void bmi_emul_flush_fifo(const struct emul *emul, bool tag_time, bool header)
+{
+	struct bmi_emul_data *data;
+
+	data = emul->data;
+
+	data->fifo_skip = 0;
+	data->fifo_frame = NULL;
+	/*
+	 * Gyroscope and accelerometer shift (last two arguments)
+	 * are not important for NULL (empty) FIFO frame.
+	 */
+	bmi_emul_set_current_frame(emul, NULL, tag_time, header, 0, 0);
+}
+
+/** Check description in emul_bmi.h */
+void bmi_emul_reset_common(const struct emul *emul, bool tag_time, bool header)
+{
+	struct bmi_emul_data *data;
+
+	data = emul->data;
+
+	/* Restore registers backed in NVM */
+	bmi_emul_restore_nvm(emul);
+
+	/* Flush FIFO */
+	bmi_emul_flush_fifo(emul, tag_time, header);
+
+	/* Reset sensor timer */
+	data->zero_time = bmi_emul_get_sensortime();
+}
+
+/** Check description in emul_bmi.h */
+void bmi_emul_set_cmd_end_time(const struct emul *emul, int time)
+{
+	struct bmi_emul_data *data;
+
+	data = emul->data;
+
+	data->cmd_end_time = k_uptime_get_32() + time;
+}
+
+/** Check description in emul_bmi.h */
+bool bmi_emul_is_cmd_end(const struct emul *emul)
+{
+	struct bmi_emul_data *data;
+
+	data = emul->data;
+
+	/* We are simulating command execution time and it doesn't expired */
+	if (data->simulate_command_exec_time &&
+	    data->cmd_end_time > k_uptime_get_32()) {
+		return false;
+	}
+
+	return true;
+}
+
+/**
+ * @brief Handle I2C write message. BMI model specific write function is called.
+ *        It is checked if accessed register isn't RO and reserved bits are set
+ *        to 0. Write set value of reg field of bmi emulator data ignoring
+ *        reserved bits. If required internal sensor offset values are updated.
+ *
+ * @param emul Pointer to BMI emulator
+ * @param reg Register which is written
+ * @param val Value being written to @p reg
+ * @param byte Number of handled bytes in this write command
+ *
+ * @return 0 on success
+ * @return -EIO on error
+ */
+static int bmi_emul_handle_write(const struct emul *emul, int reg, uint8_t val,
+				 int byte)
+{
+	struct bmi_emul_data *data;
+	uint8_t rsvd_mask;
+	int ret;
+
+	data = emul->data;
+
+	ret = data->type_data->handle_write(data->reg, emul, reg, byte, val);
+	reg = data->type_data->access_reg(emul, reg, byte, false /* = read */);
+	if (ret != 0) {
+		if (ret == BMI_EMUL_ACCESS_E) {
+			if (!data->error_on_ro_write) {
+				return 0;
+			}
+			LOG_ERR("Writing to reg 0x%x which is RO", reg);
+		}
+
+		return -EIO;
+	}
+
+	rsvd_mask = data->type_data->rsvd_mask[reg];
+
+	if (data->error_on_rsvd_write && rsvd_mask & val) {
+		LOG_ERR("Writing 0x%x to reg 0x%x with rsvd bits mask 0x%x",
+			val, reg, rsvd_mask);
+		return -EIO;
+	}
+
+	/* Ignore all reserved bits */
+	val &= ~rsvd_mask;
+	val |= data->reg[reg] & rsvd_mask;
+
+	data->reg[reg] = val;
+
+	if ((reg >= data->type_data->acc_off_reg &&
+	     reg <= data->type_data->acc_off_reg + 2) ||
+	    (reg >= data->type_data->gyr_off_reg &&
+	     reg <= data->type_data->gyr_off_reg + 2) ||
+	    reg == data->type_data->gyr98_off_reg) {
+		/*
+		 * Internal offset value should be updated to new value of
+		 * offset registers
+		 */
+		bmi_emul_updata_int_off(emul);
+	}
+
+	return 0;
+}
+
+/** Check description in emul_bmi.h */
+void bmi_emul_state_to_reg(const struct emul *emul, int acc_shift,
+			   int gyr_shift, int acc_reg, int gyr_reg,
+			   int sensortime_reg, bool acc_off_en, bool gyr_off_en)
+{
+	struct bmi_emul_data *data;
+	int32_t val[3];
+	int i;
+
+	data = emul->data;
+
+	if (gyr_off_en) {
+		val[0] = data->gyr_x - data->off_gyr_x;
+		val[1] = data->gyr_y - data->off_gyr_y;
+		val[2] = data->gyr_z - data->off_gyr_z;
+	} else {
+		val[0] = data->gyr_x;
+		val[1] = data->gyr_y;
+		val[2] = data->gyr_z;
+	}
+
+	for (i = 0; i < 3; i++) {
+		bmi_emul_set_data_reg(emul, val[i],
+				      &(data->reg[gyr_reg + i * 2]), gyr_shift);
+	}
+
+	if (acc_off_en) {
+		val[0] = data->acc_x - data->off_acc_x;
+		val[1] = data->acc_y - data->off_acc_y;
+		val[2] = data->acc_z - data->off_acc_z;
+	} else {
+		val[0] = data->acc_x;
+		val[1] = data->acc_y;
+		val[2] = data->acc_z;
+	}
+
+	for (i = 0; i < 3; i++) {
+		bmi_emul_set_data_reg(emul, val[i],
+				      &(data->reg[acc_reg + i * 2]), acc_shift);
+	}
+
+	bmi_emul_set_sensortime_reg(emul, &(data->reg[sensortime_reg]));
+}
+
+/** Check description in emul_bmi.h */
+void bmi_emul_append_frame(const struct emul *emul,
+			   struct bmi_emul_frame *frame)
+{
+	struct bmi_emul_data *data;
+	struct bmi_emul_frame *tmp_frame;
+
+	data = emul->data;
+
+	if (data->fifo_frame == NULL) {
+		data->fifo_frame = frame;
+	} else {
+		tmp_frame = data->fifo_frame;
+		while (tmp_frame->next != NULL) {
+			tmp_frame = tmp_frame->next;
+		}
+		tmp_frame->next = frame;
+	}
+}
+
+/** Check description in emul_bmi.h */
+uint16_t bmi_emul_fifo_len(const struct emul *emul, bool tag_time, bool header)
+{
+	struct bmi_emul_frame *frame;
+	struct bmi_emul_data *data;
+	uint16_t len = 0;
+
+	data = emul->data;
+
+	if (data->fifo_skip != 0 && header) {
+		len += 2;
+	}
+
+	frame = data->fifo_frame;
+	while (frame != NULL) {
+		len += bmi_emul_get_frame_len(emul, frame, tag_time, header);
+		frame = frame->next;
+	}
+
+	len += bmi_emul_get_frame_len(emul, NULL, tag_time, header);
+	/* Do not count last empty frame byte */
+	len--;
+
+	return len;
+}
+
+/** Check description in emul_bmi.h */
+uint8_t bmi_emul_get_fifo_data(const struct emul *emul, int byte, bool tag_time,
+			       bool header, int acc_shift, int gyr_shift)
+{
+	struct bmi_emul_data *data;
+	int ret;
+
+	data = emul->data;
+
+	if (byte == 0) {
+		/* Repeat uncompleated read of frame */
+		bmi_emul_set_current_frame(emul, data->fifo_frame, tag_time,
+					   header, acc_shift, gyr_shift);
+
+		/* Return header for skip frame */
+		if (data->fifo_skip != 0 && header) {
+			return BMI_EMUL_FIFO_HEAD_SKIP;
+		}
+	}
+
+	if (data->fifo_skip != 0 && byte == 1 && header) {
+		/* Return number of skipped frames */
+
+		ret = data->fifo_skip;
+		data->fifo_skip = 0;
+
+		return ret;
+	}
+
+	/* Get next valid frame */
+	while (data->fifo_frame_byte >= data->fifo_frame_len) {
+		/* No data */
+		if (data->fifo_frame == NULL) {
+			return 0;
+		}
+		data->fifo_frame = data->fifo_frame->next;
+		bmi_emul_set_current_frame(emul, data->fifo_frame, tag_time,
+					   header, acc_shift, gyr_shift);
+	}
+
+	return data->fifo[data->fifo_frame_byte++];
+}
+
+/**
+ * @brief Handle I2C read message. BMI model specific read function is called.
+ *        It is checked if accessed register isn't WO.
+ *
+ * @param emul Pointer to BMI emulator
+ * @param reg Register address to read
+ * @param buf Pointer where result should be stored
+ * @param byte Byte which is accessed during block read
+ *
+ * @return 0 on success
+ * @return -EIO on error
+ */
+static int bmi_emul_handle_read(const struct emul *emul, int reg, uint8_t *buf,
+				int byte)
+{
+	struct bmi_emul_data *data;
+	int ret;
+
+	data = emul->data;
+
+	ret = data->type_data->handle_read(data->reg, emul, reg, byte, buf);
+	reg = data->type_data->access_reg(emul, reg, byte, true /* = read */);
+	if (ret == BMI_EMUL_ACCESS_E && data->error_on_wo_read) {
+		LOG_ERR("Reading reg 0x%x which is WO", reg);
+	} else if (ret != 0) {
+		return ret;
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Called at the end of I2C read message.
+ *
+ * @param target Pointer to emulator
+ * @param reg Address which is now accessed by read command (first byte of last
+ *            I2C write message)
+ * @param bytes Number of bytes responeded to the I2C read message
+ *
+ * @return 0 on success
+ * @return -EIO on error
+ */
+static int bmi_emul_finish_read(const struct emul *emul, int reg, int bytes)
+{
+	struct bmi_emul_data *data;
+	int ret;
+
+	data = emul->data;
+
+	if (data->type_data->finish_read == NULL) {
+		return 0;
+	}
+	ret = data->type_data->finish_read(data->reg, emul, reg, bytes);
+	return ret;
+}
+
+/* Device instantiation */
+
+/**
+ * @brief Set up a new BMI emulator
+ *
+ * This should be called for each BMI device that needs to be
+ * emulated. It registers it with the I2C emulation controller.
+ *
+ * @param emul Emulation information
+ * @param parent Device to emulate
+ *
+ * @return 0 indicating success (always)
+ */
+static int bmi_emul_init(const struct emul *emul, const struct device *parent)
+{
+	struct bmi_emul_data *data = emul->data;
+
+	data->common.i2c = parent;
+	i2c_common_emul_init(&data->common);
+
+	switch (data->type) {
+	case BMI_EMUL_160:
+		data->type_data = get_bmi160_emul_type_data();
+		break;
+	case BMI_EMUL_260:
+		data->type_data = get_bmi260_emul_type_data();
+		break;
+	}
+
+	/* Set callback access_reg to type specific function */
+	data->common.access_reg = data->type_data->access_reg;
+
+	data->type_data->reset(data->reg, emul);
+
+	return 0;
+}
+
+#define BMI_EMUL(n)                                                  \
+	static struct bmi_emul_data bmi_emul_data_##n = {		\
+		.error_on_ro_write = DT_INST_PROP(n, error_on_ro_write),\
+		.error_on_wo_read = DT_INST_PROP(n, error_on_wo_read),	\
+		.error_on_rsvd_write = DT_INST_PROP(n,			\
+					error_on_reserved_bit_write),	\
+		.simulate_command_exec_time = DT_INST_PROP(n,		\
+					simulate_command_exec_time),	\
+		.type = DT_STRING_TOKEN(DT_DRV_INST(n), device_model),	\
+		.common = {						\
+			.start_write = NULL,				\
+			.write_byte = bmi_emul_handle_write,		\
+			.finish_write = NULL,				\
+			.start_read = NULL,				\
+			.read_byte = bmi_emul_handle_read,		\
+			.finish_read = bmi_emul_finish_read,		\
+			.access_reg = NULL,				\
+		},							\
+	};         \
+	static const struct i2c_common_emul_cfg bmi_emul_cfg_##n = { \
+		.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)),      \
+		.data = &bmi_emul_data_##n.common,                   \
+		.addr = DT_INST_REG_ADDR(n),                         \
+	};                                                           \
+	EMUL_DT_INST_DEFINE(n, bmi_emul_init, &bmi_emul_data_##n,    \
+			    &bmi_emul_cfg_##n, &i2c_common_emul_api, NULL)
+
+DT_INST_FOREACH_STATUS_OKAY(BMI_EMUL)
+
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
+
+struct i2c_common_emul_data *
+emul_bmi_get_i2c_common_data(const struct emul *emul)
+{
+	return emul->data;
+}
diff --git a/zephyr/emul/emul_bmi160.c b/zephyr/emul/emul_bmi160.c
new file mode 100644
index 0000000000..8b3042e2ff
--- /dev/null
+++ b/zephyr/emul/emul_bmi160.c
@@ -0,0 +1,785 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/accelgyro_bmi160.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "emul/emul_bmi.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/i2c_emul.h>
+#include <zephyr/logging/log.h>
+
+#define DT_DRV_COMPAT zephyr_bmi_emul
+
+#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
+LOG_MODULE_REGISTER(emul_bmi160);
+
+/** Mask reserved bits in each register of BMI160 */
+static const uint8_t bmi_emul_160_rsvd_mask[] = {
+	[BMI160_CHIP_ID] = 0x00,
+	[0x01] = 0xff, /* Reserved */
+	[BMI160_ERR_REG] = 0x00,
+	[BMI160_PMU_STATUS] = 0xc0,
+	[BMI160_MAG_X_L_G] = 0x00,
+	[BMI160_MAG_X_H_G] = 0x00,
+	[BMI160_MAG_Y_L_G] = 0x00,
+	[BMI160_MAG_Y_H_G] = 0x00,
+	[BMI160_MAG_Z_L_G] = 0x00,
+	[BMI160_MAG_Z_H_G] = 0x00,
+	[BMI160_RHALL_L_G] = 0x00,
+	[BMI160_RHALL_H_G] = 0x00,
+	[BMI160_GYR_X_L_G] = 0x00,
+	[BMI160_GYR_X_H_G] = 0x00,
+	[BMI160_GYR_Y_L_G] = 0x00,
+	[BMI160_GYR_Y_H_G] = 0x00,
+	[BMI160_GYR_Z_L_G] = 0x00,
+	[BMI160_GYR_Z_H_G] = 0x00,
+	[BMI160_ACC_X_L_G] = 0x00,
+	[BMI160_ACC_X_H_G] = 0x00,
+	[BMI160_ACC_Y_L_G] = 0x00,
+	[BMI160_ACC_Y_H_G] = 0x00,
+	[BMI160_ACC_Z_L_G] = 0x00,
+	[BMI160_ACC_Z_H_G] = 0x00,
+	[BMI160_SENSORTIME_0] = 0x00,
+	[BMI160_SENSORTIME_1] = 0x00,
+	[BMI160_SENSORTIME_2] = 0x00,
+	[BMI160_STATUS] = 0x01,
+	[BMI160_INT_STATUS_0] = 0x00,
+	[BMI160_INT_STATUS_1] = 0x03,
+	[BMI160_INT_STATUS_2] = 0x00,
+	[BMI160_INT_STATUS_3] = 0x00,
+	[BMI160_TEMPERATURE_0] = 0x00,
+	[BMI160_TEMPERATURE_1] = 0x00,
+	[BMI160_FIFO_LENGTH_0] = 0x00,
+	[BMI160_FIFO_LENGTH_1] = 0xf8,
+	[BMI160_FIFO_DATA] = 0x00,
+	[0x25 ... 0x3f] = 0xff, /* Reserved */
+	[BMI160_ACC_CONF] = 0x00,
+	[BMI160_ACC_RANGE] = 0xf0,
+	[BMI160_GYR_CONF] = 0xc0,
+	[BMI160_GYR_RANGE] = 0xf8,
+	[BMI160_MAG_CONF] = 0xf0,
+	[BMI160_FIFO_DOWNS] = 0x00,
+	[BMI160_FIFO_CONFIG_0] = 0x00,
+	[BMI160_FIFO_CONFIG_1] = 0x01,
+	[0x48 ... 0x4a] = 0xff, /* Reserved */
+	[BMI160_MAG_IF_0] = 0x01,
+	[BMI160_MAG_IF_1] = 0x40,
+	[BMI160_MAG_IF_2] = 0x00,
+	[BMI160_MAG_IF_3] = 0x00,
+	[BMI160_MAG_IF_4] = 0x00,
+	[BMI160_INT_EN_0] = 0x08,
+	[BMI160_INT_EN_1] = 0x80,
+	[BMI160_INT_EN_2] = 0xf0,
+	[BMI160_INT_OUT_CTRL] = 0x00,
+	[BMI160_INT_LATCH] = 0xc0,
+	[BMI160_INT_MAP_0] = 0x00,
+	[BMI160_INT_MAP_1] = 0x00,
+	[BMI160_INT_MAP_2] = 0x00,
+	[BMI160_INT_DATA_0] = 0x77,
+	[BMI160_INT_DATA_1] = 0x7f,
+	[BMI160_INT_LOW_HIGH_0] = 0x00,
+	[BMI160_INT_LOW_HIGH_1] = 0x00,
+	[BMI160_INT_LOW_HIGH_2] = 0x3c,
+	[BMI160_INT_LOW_HIGH_3] = 0x00,
+	[BMI160_INT_LOW_HIGH_4] = 0x00,
+	[BMI160_INT_MOTION_0] = 0x00,
+	[BMI160_INT_MOTION_1] = 0x00,
+	[BMI160_INT_MOTION_2] = 0x00,
+	[BMI160_INT_MOTION_3] = 0xc0,
+	[BMI160_INT_TAP_0] = 0x38,
+	[BMI160_INT_TAP_1] = 0xe0,
+	[BMI160_INT_ORIENT_0] = 0x00,
+	[BMI160_INT_ORIENT_1] = 0x00,
+	[BMI160_INT_FLAT_0] = 0xc0,
+	[BMI160_INT_FLAT_1] = 0xc8,
+	[BMI160_FOC_CONF] = 0x80,
+	[BMI160_CONF] = 0xfd,
+	[BMI160_IF_CONF] = 0xce,
+	[BMI160_PMU_TRIGGER] = 0x80,
+	[BMI160_SELF_TEST] = 0xe0,
+	[0x6e] = 0xff, /* Reserved */
+	[0x6f] = 0xff, /* Reserved */
+	[BMI160_NV_CONF] = 0xf0,
+	[BMI160_OFFSET_ACC70] = 0x00,
+	[BMI160_OFFSET_ACC70 + 1] = 0x00,
+	[BMI160_OFFSET_ACC70 + 2] = 0x00,
+	[BMI160_OFFSET_GYR70] = 0x00,
+	[BMI160_OFFSET_GYR70 + 1] = 0x00,
+	[BMI160_OFFSET_GYR70 + 2] = 0x00,
+	[BMI160_OFFSET_EN_GYR98] = 0x00,
+	[BMI160_STEP_CNT_0] = 0x00,
+	[BMI160_STEP_CNT_1] = 0x00,
+	[BMI160_STEP_CONF_0] = 0x00,
+	[BMI160_STEP_CONF_1] = 0xf0,
+	[0x7c] = 0xff, /* Reserved */
+	[0x7d] = 0xff, /* Reserved */
+	[BMI160_CMD_REG] = 0x00,
+};
+
+/**
+ * @brief Convert range in format of ACC_RANGE register to number of bits
+ *        that should be shifted right to obtain 16 bit reported accelerometer
+ *        value from internal 32 bit value
+ *
+ * @param range Value of ACC_RANGE register
+ *
+ * @return shift Number of LSB that should be ignored from internal
+ *               accelerometer value
+ */
+static int bmi160_emul_acc_range_to_shift(uint8_t range)
+{
+	switch (range & 0xf) {
+	case BMI160_GSEL_2G:
+		return 0;
+	case BMI160_GSEL_4G:
+		return 1;
+	case BMI160_GSEL_8G:
+		return 2;
+	case BMI160_GSEL_16G:
+		return 3;
+	default:
+		return 0;
+	}
+}
+
+/**
+ * @brief Convert range in format of GYR_RANGE register to number of bits
+ *        that should be shifted right to obtain 16 bit reported gyroscope
+ *        value from internal 32 bit value
+ *
+ * @param range Value of GYR_RANGE register
+ *
+ * @return shift Number of LSB that should be ignored from internal
+ *               gyroscope value
+ */
+static int bmi160_emul_gyr_range_to_shift(uint8_t range)
+{
+	switch (range & 0x7) {
+	case BMI160_DPS_SEL_2000:
+		return 4;
+	case BMI160_DPS_SEL_1000:
+		return 3;
+	case BMI160_DPS_SEL_500:
+		return 2;
+	case BMI160_DPS_SEL_250:
+		return 1;
+	case BMI160_DPS_SEL_125:
+		return 0;
+	default:
+		return 0;
+	}
+}
+
+/**
+ * @brief Reset registers to default values and restore registers backed by NVM
+ *
+ * @param regs Pointer to array of emulator's registers
+ * @param emul Pointer to BMI emulator
+ */
+static void bmi160_emul_reset(uint8_t *regs, const struct emul *emul)
+{
+	bool tag_time;
+	bool header;
+
+	regs[BMI160_CHIP_ID] = 0xd1;
+	regs[BMI160_ERR_REG] = 0x00;
+	regs[BMI160_PMU_STATUS] = 0x00;
+	regs[BMI160_MAG_X_L_G] = 0x00;
+	regs[BMI160_MAG_X_H_G] = 0x00;
+	regs[BMI160_MAG_Y_L_G] = 0x00;
+	regs[BMI160_MAG_Y_H_G] = 0x00;
+	regs[BMI160_MAG_Z_L_G] = 0x00;
+	regs[BMI160_MAG_Z_H_G] = 0x00;
+	regs[BMI160_RHALL_L_G] = 0x00;
+	regs[BMI160_RHALL_H_G] = 0x00;
+	regs[BMI160_GYR_X_L_G] = 0x00;
+	regs[BMI160_GYR_X_H_G] = 0x00;
+	regs[BMI160_GYR_Y_L_G] = 0x00;
+	regs[BMI160_GYR_Y_H_G] = 0x00;
+	regs[BMI160_GYR_Z_L_G] = 0x00;
+	regs[BMI160_GYR_Z_H_G] = 0x00;
+	regs[BMI160_ACC_X_L_G] = 0x00;
+	regs[BMI160_ACC_X_H_G] = 0x00;
+	regs[BMI160_ACC_Y_L_G] = 0x00;
+	regs[BMI160_ACC_Y_H_G] = 0x00;
+	regs[BMI160_ACC_Z_L_G] = 0x00;
+	regs[BMI160_ACC_Z_H_G] = 0x00;
+	regs[BMI160_SENSORTIME_0] = 0x00;
+	regs[BMI160_SENSORTIME_1] = 0x00;
+	regs[BMI160_SENSORTIME_2] = 0x00;
+	regs[BMI160_STATUS] = 0x01;
+	regs[BMI160_INT_STATUS_0] = 0x00;
+	regs[BMI160_INT_STATUS_1] = 0x00;
+	regs[BMI160_INT_STATUS_2] = 0x00;
+	regs[BMI160_INT_STATUS_3] = 0x00;
+	regs[BMI160_TEMPERATURE_0] = 0x00;
+	regs[BMI160_TEMPERATURE_1] = 0x00;
+	regs[BMI160_FIFO_LENGTH_0] = 0x00;
+	regs[BMI160_FIFO_LENGTH_1] = 0x00;
+	regs[BMI160_FIFO_DATA] = 0x00;
+	regs[BMI160_ACC_CONF] = 0x28;
+	regs[BMI160_ACC_RANGE] = 0x03;
+	regs[BMI160_GYR_CONF] = 0x28;
+	regs[BMI160_GYR_RANGE] = 0x00;
+	regs[BMI160_MAG_CONF] = 0x0b;
+	regs[BMI160_FIFO_DOWNS] = 0x88;
+	regs[BMI160_FIFO_CONFIG_0] = 0x80;
+	regs[BMI160_FIFO_CONFIG_1] = 0x10;
+	regs[BMI160_MAG_IF_0] = 0x20;
+	regs[BMI160_MAG_IF_1] = 0x80;
+	regs[BMI160_MAG_IF_2] = 0x42;
+	regs[BMI160_MAG_IF_3] = 0x4c;
+	regs[BMI160_MAG_IF_4] = 0x00;
+	regs[BMI160_INT_EN_0] = 0x00;
+	regs[BMI160_INT_EN_1] = 0x00;
+	regs[BMI160_INT_EN_2] = 0x00;
+	regs[BMI160_INT_OUT_CTRL] = 0x00;
+	regs[BMI160_INT_LATCH] = 0x00;
+	regs[BMI160_INT_MAP_0] = 0x00;
+	regs[BMI160_INT_MAP_1] = 0x00;
+	regs[BMI160_INT_MAP_2] = 0x00;
+	regs[BMI160_INT_DATA_0] = 0x00;
+	regs[BMI160_INT_DATA_1] = 0x00;
+	regs[BMI160_INT_LOW_HIGH_0] = 0x07;
+	regs[BMI160_INT_LOW_HIGH_1] = 0x30;
+	regs[BMI160_INT_LOW_HIGH_2] = 0x81;
+	regs[BMI160_INT_LOW_HIGH_3] = 0xdb;
+	regs[BMI160_INT_LOW_HIGH_4] = 0xc0;
+	regs[BMI160_INT_MOTION_0] = 0x00;
+	regs[BMI160_INT_MOTION_1] = 0x14;
+	regs[BMI160_INT_MOTION_2] = 0x14;
+	regs[BMI160_INT_MOTION_3] = 0x24;
+	regs[BMI160_INT_TAP_0] = 0x04;
+	regs[BMI160_INT_TAP_1] = 0xda;
+	regs[BMI160_INT_ORIENT_0] = 0x18;
+	regs[BMI160_INT_ORIENT_1] = 0x48;
+	regs[BMI160_INT_FLAT_0] = 0x08;
+	regs[BMI160_INT_FLAT_1] = 0x11;
+	regs[BMI160_FOC_CONF] = 0x00;
+	regs[BMI160_CONF] = 0x00;
+	regs[BMI160_IF_CONF] = 0x00;
+	regs[BMI160_PMU_TRIGGER] = 0x00;
+	regs[BMI160_SELF_TEST] = 0x00;
+	regs[BMI160_STEP_CNT_0] = 0x00;
+	regs[BMI160_STEP_CNT_1] = 0x00;
+	regs[BMI160_STEP_CONF_0] = 0x00;
+	regs[BMI160_STEP_CONF_1] = 0x15;
+	regs[BMI160_CMD_REG] = 0x03;
+
+	/* Call generic reset */
+	tag_time = regs[BMI160_FIFO_CONFIG_1] & BMI160_FIFO_TAG_TIME_EN;
+	header = regs[BMI160_FIFO_CONFIG_1] & BMI160_FIFO_HEADER_EN;
+	bmi_emul_reset_common(emul, tag_time, header);
+}
+
+/**
+ * @brief Clear all interrupt registers
+ *
+ * @param regs Pointer to array of emulator's registers
+ */
+static void bmi160_emul_clear_int(uint8_t *regs)
+{
+	regs[BMI160_INT_STATUS_0] = 0x00;
+	regs[BMI160_INT_STATUS_1] = 0x00;
+	regs[BMI160_INT_STATUS_2] = 0x00;
+	regs[BMI160_INT_STATUS_3] = 0x00;
+}
+
+/**
+ * @brief Get offset value for given gyroscope value. If gyroscope value is
+ *        above maximum (belowe minimum), then minimum -31,25°/s
+ *        (maximum 31,25°/s) offset value is returned.
+ *
+ * @param gyr Gyroscope value
+ */
+static int16_t bmi160_emul_get_gyr_target_off(int32_t gyr)
+{
+	if (gyr > (int32_t)BMI_EMUL_125_DEG_S / 4) {
+		return -((int32_t)BMI_EMUL_125_DEG_S / 4);
+	}
+
+	if (gyr < -((int32_t)BMI_EMUL_125_DEG_S / 4)) {
+		return BMI_EMUL_125_DEG_S / 4;
+	}
+
+	return -gyr;
+}
+
+/**
+ * @brief Get offset value for given accelerometer value. If accelerometer
+ *        value - target is above maximum (belowe minimum), then minimum -0.5g
+ *        (maximum 0.5g) offset value is returned.
+ *
+ * @param acc Accelerometer value
+ * @param target Target value in FOC configuration register format
+ */
+static int16_t bmi160_emul_get_acc_target_off(int32_t acc, uint8_t target)
+{
+	switch (target) {
+	case BMI160_FOC_ACC_PLUS_1G:
+		acc -= BMI_EMUL_1G;
+		break;
+	case BMI160_FOC_ACC_MINUS_1G:
+		acc += BMI_EMUL_1G;
+		break;
+	}
+
+	if (acc > (int32_t)BMI_EMUL_1G / 2) {
+		return -((int32_t)BMI_EMUL_1G / 2);
+	}
+
+	if (acc < -((int32_t)BMI_EMUL_1G / 2)) {
+		return BMI_EMUL_1G / 2;
+	}
+
+	return -acc;
+}
+
+/**
+ * @brief Handle fast offset compensation. Check FOC configuration register
+ *        and sets gyroscope and/or accelerometer offset using current emulator
+ *        state.
+ *
+ * @param regs Pointer to array of emulator's registers
+ * @param emul Pointer to BMI emulator
+ */
+static void bmi160_emul_handle_off_comp(uint8_t *regs, const struct emul *emul)
+{
+	uint8_t target;
+	int16_t off;
+	int32_t val;
+
+	if (regs[BMI160_FOC_CONF] & BMI160_FOC_GYRO_EN) {
+		val = bmi_emul_get_value(emul, BMI_EMUL_GYR_X);
+		off = bmi160_emul_get_gyr_target_off(val);
+		bmi_emul_set_off(emul, BMI_EMUL_GYR_X, off);
+		val = bmi_emul_get_value(emul, BMI_EMUL_GYR_Y);
+		off = bmi160_emul_get_gyr_target_off(val);
+
+		bmi_emul_set_off(emul, BMI_EMUL_GYR_Y, off);
+		val = bmi_emul_get_value(emul, BMI_EMUL_GYR_Z);
+		off = bmi160_emul_get_gyr_target_off(val);
+		bmi_emul_set_off(emul, BMI_EMUL_GYR_Z, off);
+	}
+
+	target = (regs[BMI160_FOC_CONF] >> BMI160_FOC_ACC_X_OFFSET) & 0x3;
+	if (target) {
+		val = bmi_emul_get_value(emul, BMI_EMUL_ACC_X);
+		off = bmi160_emul_get_acc_target_off(val, target);
+		bmi_emul_set_off(emul, BMI_EMUL_ACC_X, off);
+	}
+
+	target = (regs[BMI160_FOC_CONF] >> BMI160_FOC_ACC_Y_OFFSET) & 0x3;
+	if (target) {
+		val = bmi_emul_get_value(emul, BMI_EMUL_ACC_Y);
+		off = bmi160_emul_get_acc_target_off(val, target);
+		bmi_emul_set_off(emul, BMI_EMUL_ACC_Y, off);
+	}
+
+	target = (regs[BMI160_FOC_CONF] >> BMI160_FOC_ACC_Z_OFFSET) & 0x3;
+	if (target) {
+		val = bmi_emul_get_value(emul, BMI_EMUL_ACC_Z);
+		off = bmi160_emul_get_acc_target_off(val, target);
+		bmi_emul_set_off(emul, BMI_EMUL_ACC_Z, off);
+	}
+}
+
+/**
+ * @brief Execute first part of command. Emulate state of device which is
+ *        during handling command (status bits etc). This function save time
+ *        on which command should end.
+ *
+ * @param regs Pointer to array of emulator's registers
+ * @param emul Pointer to BMI emulator
+ * @param cmd Command that is starting
+ *
+ * @return 0 on success
+ * @return -EIO on failure
+ */
+static int bmi160_emul_start_cmd(uint8_t *regs, const struct emul *emul,
+				 int cmd)
+{
+	int time;
+
+	switch (cmd) {
+	case BMI160_CMD_SOFT_RESET:
+		time = 1;
+		break;
+	case BMI160_CMD_START_FOC:
+		if ((regs[BMI160_FOC_CONF] & BMI160_FOC_GYRO_EN) &&
+		    ((regs[BMI160_PMU_STATUS] &
+		      (0x3 << BMI160_PMU_GYR_OFFSET)) !=
+		     BMI160_PMU_NORMAL << BMI160_PMU_GYR_OFFSET)) {
+			LOG_ERR("Starting gyroscope FOC in low power mode");
+			return -EIO;
+		}
+
+		if ((regs[BMI160_FOC_CONF] & ~BMI160_FOC_GYRO_EN) &&
+		    ((regs[BMI160_PMU_STATUS] &
+		      (0x3 << BMI160_PMU_ACC_OFFSET)) !=
+		     BMI160_PMU_NORMAL << BMI160_PMU_ACC_OFFSET)) {
+			LOG_ERR("Starting accelerometer FOC in low power mode");
+			return -EIO;
+		}
+
+		regs[BMI160_STATUS] &= ~BMI160_FOC_RDY;
+		time = 250;
+		break;
+	case BMI160_CMD_ACC_MODE_SUSP:
+	case BMI160_CMD_GYR_MODE_SUSP:
+	case BMI160_CMD_MAG_MODE_SUSP:
+		time = 0;
+		break;
+	/* Real hardware probably switch faster if not in suspend mode */
+	case BMI160_CMD_ACC_MODE_NORMAL:
+	case BMI160_CMD_ACC_MODE_LOWPOWER:
+		time = 4;
+		break;
+	case BMI160_CMD_GYR_MODE_NORMAL:
+	case BMI160_CMD_GYR_MODE_FAST_STARTUP:
+		time = 80;
+		break;
+	case BMI160_CMD_MAG_MODE_NORMAL:
+	case BMI160_CMD_MAG_MODE_LOWPOWER:
+		time = 1;
+		break;
+	case BMI160_CMD_FIFO_FLUSH:
+		time = 0;
+		break;
+	case BMI160_CMD_INT_RESET:
+		time = 0;
+		break;
+	default:
+		LOG_ERR("Unknown command 0x%x", cmd);
+		return -EIO;
+	}
+
+	regs[BMI160_CMD_REG] = cmd;
+	bmi_emul_set_cmd_end_time(emul, time);
+
+	return 0;
+}
+
+/**
+ * @brief Emulate end of ongoing command.
+ *
+ * @param regs Pointer to array of emulator's registers
+ * @param emul Pointer to BMI emulator
+ */
+static void bmi160_emul_end_cmd(uint8_t *regs, const struct emul *emul)
+{
+	uint8_t pmu_status;
+	bool tag_time;
+	bool header;
+	int cmd;
+
+	pmu_status = regs[BMI160_PMU_STATUS];
+	cmd = regs[BMI160_CMD_REG];
+	regs[BMI160_CMD_REG] = BMI160_CMD_NOOP;
+	tag_time = regs[BMI160_FIFO_CONFIG_1] & BMI160_FIFO_TAG_TIME_EN;
+	header = regs[BMI160_FIFO_CONFIG_1] & BMI160_FIFO_HEADER_EN;
+
+	switch (cmd) {
+	case BMI160_CMD_SOFT_RESET:
+		bmi160_emul_reset(regs, emul);
+		break;
+	case BMI160_CMD_START_FOC:
+		bmi160_emul_handle_off_comp(regs, emul);
+		regs[BMI160_STATUS] |= BMI160_FOC_RDY;
+		break;
+	case BMI160_CMD_ACC_MODE_SUSP:
+		pmu_status &= ~(0x3 << BMI160_PMU_ACC_OFFSET);
+		pmu_status |= BMI160_PMU_SUSPEND << BMI160_PMU_ACC_OFFSET;
+		break;
+	case BMI160_CMD_ACC_MODE_NORMAL:
+		pmu_status &= ~(0x3 << BMI160_PMU_ACC_OFFSET);
+		pmu_status |= BMI160_PMU_NORMAL << BMI160_PMU_ACC_OFFSET;
+		break;
+	case BMI160_CMD_ACC_MODE_LOWPOWER:
+		pmu_status &= ~(0x3 << BMI160_PMU_ACC_OFFSET);
+		pmu_status |= BMI160_PMU_LOW_POWER << BMI160_PMU_ACC_OFFSET;
+		break;
+	case BMI160_CMD_GYR_MODE_SUSP:
+		pmu_status &= ~(0x3 << BMI160_PMU_GYR_OFFSET);
+		pmu_status |= BMI160_PMU_SUSPEND << BMI160_PMU_GYR_OFFSET;
+		break;
+	case BMI160_CMD_GYR_MODE_NORMAL:
+		pmu_status &= ~(0x3 << BMI160_PMU_GYR_OFFSET);
+		pmu_status |= BMI160_PMU_NORMAL << BMI160_PMU_GYR_OFFSET;
+		break;
+	case BMI160_CMD_GYR_MODE_FAST_STARTUP:
+		pmu_status &= ~(0x3 << BMI160_PMU_GYR_OFFSET);
+		pmu_status |= BMI160_PMU_FAST_STARTUP << BMI160_PMU_GYR_OFFSET;
+		break;
+	case BMI160_CMD_MAG_MODE_SUSP:
+		pmu_status &= ~(0x3 << BMI160_PMU_MAG_OFFSET);
+		pmu_status |= BMI160_PMU_SUSPEND << BMI160_PMU_MAG_OFFSET;
+		break;
+	case BMI160_CMD_MAG_MODE_NORMAL:
+		pmu_status &= ~(0x3 << BMI160_PMU_MAG_OFFSET);
+		pmu_status |= BMI160_PMU_NORMAL << BMI160_PMU_MAG_OFFSET;
+		break;
+	case BMI160_CMD_MAG_MODE_LOWPOWER:
+		pmu_status &= ~(0x3 << BMI160_PMU_MAG_OFFSET);
+		pmu_status |= BMI160_PMU_LOW_POWER << BMI160_PMU_MAG_OFFSET;
+		break;
+	case BMI160_CMD_FIFO_FLUSH:
+		bmi_emul_flush_fifo(emul, tag_time, header);
+		break;
+	case BMI160_CMD_INT_RESET:
+		bmi160_emul_clear_int(regs);
+		break;
+	}
+
+	/* Clear FIFO on sensor on/off in headerless mode */
+	if (pmu_status != regs[BMI160_PMU_STATUS] && !header) {
+		bmi_emul_flush_fifo(emul, tag_time, header);
+	}
+
+	regs[BMI160_PMU_STATUS] = pmu_status;
+}
+
+/**
+ * @brief BMI160 specific write function. It doesn't handle block writes.
+ *        Check if read only register is not accessed. Before writing value,
+ *        ongoing command is finished if possible. Write to CMD register is
+ *        handled by BMI160 specific function. On changing of FIFO
+ *        header/headerless mode, FIFO is flushed.
+ *
+ * @param regs Pointer to array of emulator's registers
+ * @param emul Pointer to BMI emulator
+ * @param reg Register address that is accessed
+ * @param byte Number of handled bytes in this write command
+ * @param val Value that is being written
+ *
+ * @return 0 on success
+ * @return BMI_EMUL_ACCESS_E on RO register access
+ * @return -EIO on error
+ */
+static int bmi160_emul_handle_write(uint8_t *regs, const struct emul *emul,
+				    int reg, int byte, uint8_t val)
+{
+	bool tag_time;
+	bool header;
+
+	if (byte > 1) {
+		LOG_ERR("Block writes are not allowed");
+		return -EIO;
+	}
+
+	if (reg <= BMI160_FIFO_DATA ||
+	    (reg >= BMI160_STEP_CNT_0 && reg <= BMI160_STEP_CNT_1)) {
+		return BMI_EMUL_ACCESS_E;
+	}
+
+	/* Stop on going command if required */
+	if (regs[BMI160_CMD_REG] != BMI160_CMD_NOOP &&
+	    bmi_emul_is_cmd_end(emul)) {
+		bmi160_emul_end_cmd(regs, emul);
+	}
+
+	switch (reg) {
+	case BMI160_CMD_REG:
+		if (regs[BMI160_CMD_REG] != BMI160_CMD_NOOP) {
+			LOG_ERR("Issued command before previous end");
+			return -EIO;
+		}
+
+		return bmi160_emul_start_cmd(regs, emul, val);
+	case BMI160_FIFO_CONFIG_1:
+		tag_time = regs[BMI160_FIFO_CONFIG_1] & BMI160_FIFO_TAG_TIME_EN;
+		header = regs[BMI160_FIFO_CONFIG_1] & BMI160_FIFO_HEADER_EN;
+		/*
+		 * Clear FIFO on transition between headerless and
+		 * header mode
+		 */
+		if (!!(val & BMI160_FIFO_HEADER_EN) != header) {
+			bmi_emul_flush_fifo(emul, tag_time, header);
+		}
+		break;
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Get currently accessed register. It is first register plus number of
+ *        handled bytes for all registers except BMI160_FIFO_DATA for which
+ *        address incrementation is disabled.
+ *
+ * @param emul Pointer to BMI emulator
+ * @param reg First byte of last write message
+ * @param bytes Number of bytes already handled from current message
+ * @param read If currently handled is read message
+ *
+ * @return Currently accessed register
+ */
+static int bmi160_emul_access_reg(const struct emul *emul, int reg, int byte,
+				  bool read)
+{
+	if (!read) {
+		return reg;
+	}
+
+	/*
+	 * If register is FIFO data, then read data from FIFO.
+	 * Else block read access subsequent registers.
+	 */
+	if (reg <= BMI160_FIFO_DATA && reg + byte >= BMI160_FIFO_DATA) {
+		return BMI160_FIFO_DATA;
+	}
+
+	return reg + byte;
+}
+
+/**
+ * @brief BMI160 specific read function. It handle block reads but only if
+ *        device is not suspended. FIFO data register is trap register, so
+ *        after reaching it, register address is not increased on block reads.
+ *        Before reading value, ongoing command is finished if possible.
+ *        Read of sensor data traps current emulator state in registers.
+ *        Read of FIFO length and FIFO data triggers default BMI functions.
+ *
+ * @param regs Pointer to array of emulator's registers
+ * @param emul Pointer to BMI emulator
+ * @param reg Register address that is accessed
+ * @param byte Byte which is accessed during block read
+ * @param buf Pointer where read byte should be stored
+ *
+ * @return 0 on success
+ * @return BMI_EMUL_ACCESS_E on WO register access
+ * @return -EIO on other error
+ */
+static int bmi160_emul_handle_read(uint8_t *regs, const struct emul *emul,
+				   int reg, int byte, char *buf)
+{
+	uint16_t fifo_len;
+	bool acc_off_en;
+	bool gyr_off_en;
+	bool tag_time;
+	bool header;
+	int gyr_shift;
+	int acc_shift;
+	int fifo_byte;
+
+	/* Get number of bytes readed from FIFO */
+	fifo_byte = byte - (reg - BMI160_FIFO_DATA);
+
+	reg = bmi160_emul_access_reg(emul, reg, byte, true /* = read */);
+
+	/* Stop on going command if required */
+	if (regs[BMI160_CMD_REG] != BMI160_CMD_NOOP &&
+	    bmi_emul_is_cmd_end(emul)) {
+		bmi160_emul_end_cmd(regs, emul);
+	}
+
+	/* Burst reads are not supported if all sensors are in suspend mode */
+	if ((regs[BMI160_PMU_STATUS] & 0x3f) == 0 && byte > 0) {
+		LOG_ERR("Block reads are not supported in suspend mode");
+		return -EIO;
+	}
+
+	tag_time = regs[BMI160_FIFO_CONFIG_1] & BMI160_FIFO_TAG_TIME_EN;
+	header = regs[BMI160_FIFO_CONFIG_1] & BMI160_FIFO_HEADER_EN;
+	acc_off_en = regs[BMI160_OFFSET_EN_GYR98] & BMI160_OFFSET_ACC_EN;
+	gyr_off_en = regs[BMI160_OFFSET_EN_GYR98] & BMI160_OFFSET_GYRO_EN;
+	gyr_shift = bmi160_emul_gyr_range_to_shift(regs[BMI160_GYR_RANGE]);
+	acc_shift = bmi160_emul_acc_range_to_shift(regs[BMI160_ACC_RANGE]);
+
+	switch (reg) {
+	case BMI160_GYR_X_L_G:
+	case BMI160_GYR_X_H_G:
+	case BMI160_GYR_Y_L_G:
+	case BMI160_GYR_Y_H_G:
+	case BMI160_GYR_Z_L_G:
+	case BMI160_GYR_Z_H_G:
+	case BMI160_ACC_X_L_G:
+	case BMI160_ACC_X_H_G:
+	case BMI160_ACC_Y_L_G:
+	case BMI160_ACC_Y_H_G:
+	case BMI160_ACC_Z_L_G:
+	case BMI160_ACC_Z_H_G:
+	case BMI160_SENSORTIME_0:
+	case BMI160_SENSORTIME_1:
+	case BMI160_SENSORTIME_2:
+		/*
+		 * Snapshot of current emulator state is created on data read
+		 * and shouldn't be changed until next I2C operation
+		 */
+		if (byte == 0) {
+			bmi_emul_state_to_reg(emul, acc_shift, gyr_shift,
+					      BMI160_ACC_X_L_G,
+					      BMI160_GYR_X_L_G,
+					      BMI160_SENSORTIME_0, acc_off_en,
+					      gyr_off_en);
+		}
+		break;
+	case BMI160_FIFO_LENGTH_0:
+	case BMI160_FIFO_LENGTH_1:
+		if (byte == 0) {
+			fifo_len = bmi_emul_fifo_len(emul, tag_time, header);
+			regs[BMI160_FIFO_LENGTH_0] = fifo_len & 0xff;
+			regs[BMI160_FIFO_LENGTH_1] = (fifo_len >> 8) & 0x7;
+		}
+		break;
+	case BMI160_FIFO_DATA:
+		regs[reg] = bmi_emul_get_fifo_data(emul, fifo_byte, tag_time,
+						   header, acc_shift,
+						   gyr_shift);
+		break;
+	}
+
+	*buf = regs[reg];
+
+	return 0;
+}
+
+static int bmi160_emul_finish_read(uint8_t *regs, const struct emul *emul,
+				   int reg, int bytes)
+{
+	int i;
+
+	switch (reg) {
+	case BMI160_INT_STATUS_0:
+		/* Clear interrupt status after reading. */
+		for (i = 0; i < bytes; ++i) {
+			regs[BMI160_INT_STATUS_0 + i] = 0;
+		}
+		break;
+	}
+	return 0;
+}
+
+/** Registers backed in NVM by BMI160 */
+const int bmi160_nvm_reg[] = {
+	BMI160_NV_CONF,		 BMI160_OFFSET_ACC70,	BMI160_OFFSET_ACC70 + 1,
+	BMI160_OFFSET_ACC70 + 2, BMI160_OFFSET_GYR70,	BMI160_OFFSET_GYR70 + 1,
+	BMI160_OFFSET_GYR70 + 2, BMI160_OFFSET_EN_GYR98
+};
+
+/** Confguration of BMI160 */
+struct bmi_emul_type_data bmi160_emul = {
+	.sensortime_follow_config_frame = false,
+	.handle_write = bmi160_emul_handle_write,
+	.handle_read = bmi160_emul_handle_read,
+	.finish_read = bmi160_emul_finish_read,
+	.access_reg = bmi160_emul_access_reg,
+	.reset = bmi160_emul_reset,
+	.rsvd_mask = bmi_emul_160_rsvd_mask,
+	.nvm_reg = bmi160_nvm_reg,
+	.nvm_len = ARRAY_SIZE(bmi160_nvm_reg),
+	.gyr_off_reg = BMI160_OFFSET_GYR70,
+	.acc_off_reg = BMI160_OFFSET_ACC70,
+	.gyr98_off_reg = BMI160_OFFSET_EN_GYR98,
+};
+
+/** Check description in emul_bmi.h */
+const struct bmi_emul_type_data *get_bmi160_emul_type_data(void)
+{
+	return &bmi160_emul;
+}
diff --git a/zephyr/emul/emul_bmi260.c b/zephyr/emul/emul_bmi260.c
new file mode 100644
index 0000000000..d62b51ebfa
--- /dev/null
+++ b/zephyr/emul/emul_bmi260.c
@@ -0,0 +1,565 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/accelgyro_bmi260.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "emul/emul_bmi.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/i2c_emul.h>
+#include <zephyr/logging/log.h>
+
+#define DT_DRV_COMPAT zephyr_bmi_emul
+
+#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
+LOG_MODULE_REGISTER(emul_bmi260);
+
+/** Mask reserved bits in each register of BMI260 */
+static const uint8_t bmi_emul_260_rsvd_mask[] = {
+	[BMI260_CHIP_ID] = 0x00,
+	[0x01] = 0xff, /* Reserved */
+	[BMI260_ERR_REG] = 0x20,
+	[BMI260_STATUS] = 0x0b,
+	[BMI260_AUX_X_L_G] = 0x00,
+	[BMI260_AUX_X_H_G] = 0x00,
+	[BMI260_AUX_Y_L_G] = 0x00,
+	[BMI260_AUX_Y_H_G] = 0x00,
+	[BMI260_AUX_Z_L_G] = 0x00,
+	[BMI260_AUX_Z_H_G] = 0x00,
+	[BMI260_AUX_R_L_G] = 0x00,
+	[BMI260_AUX_R_H_G] = 0x00,
+	[BMI260_ACC_X_L_G] = 0x00,
+	[BMI260_ACC_X_H_G] = 0x00,
+	[BMI260_ACC_Y_L_G] = 0x00,
+	[BMI260_ACC_Y_H_G] = 0x00,
+	[BMI260_ACC_Z_L_G] = 0x00,
+	[BMI260_ACC_Z_H_G] = 0x00,
+	[BMI260_GYR_X_L_G] = 0x00,
+	[BMI260_GYR_X_H_G] = 0x00,
+	[BMI260_GYR_Y_L_G] = 0x00,
+	[BMI260_GYR_Y_H_G] = 0x00,
+	[BMI260_GYR_Z_L_G] = 0x00,
+	[BMI260_GYR_Z_H_G] = 0x00,
+	[BMI260_SENSORTIME_0] = 0x00,
+	[BMI260_SENSORTIME_1] = 0x00,
+	[BMI260_SENSORTIME_2] = 0x00,
+	[BMI260_EVENT] = 0xe2,
+	[BMI260_INT_STATUS_0] = 0x00,
+	[BMI260_INT_STATUS_1] = 0x18,
+	[BMI260_SC_OUT_0] = 0x00,
+	[BMI260_SC_OUT_1] = 0x00,
+	[BMI260_ORIENT_ACT] = 0xe0,
+	[BMI260_INTERNAL_STATUS] = 0x00,
+	[BMI260_TEMPERATURE_0] = 0x00,
+	[BMI260_TEMPERATURE_1] = 0x00,
+	[BMI260_FIFO_LENGTH_0] = 0x00,
+	[BMI260_FIFO_LENGTH_1] = 0xc0,
+	[BMI160_FIFO_DATA] = 0x00,
+	[0x27 ... 0x2e] = 0xff, /* Reserved */
+	[BMI260_FEAT_PAGE] = 0xf8,
+	[0x30 ... 0x3f] = 0x00, /* Features */
+	[BMI260_ACC_CONF] = 0x00,
+	[BMI260_ACC_RANGE] = 0xfc,
+	[BMI260_GYR_CONF] = 0x00,
+	[BMI260_GYR_RANGE] = 0xf0,
+	[BMI260_AUX_CONF] = 0x00,
+	[BMI260_FIFO_DOWNS] = 0x00,
+	[BMI260_FIFO_WTM_0] = 0x00,
+	[BMI260_FIFO_WTM_1] = 0xe0,
+	[BMI260_FIFO_CONFIG_0] = 0xfc,
+	[BMI260_FIFO_CONFIG_1] = 0x00,
+	[BMI260_SATURATION] = 0xc0,
+	[BMI260_AUX_DEV_ID] = 0x01,
+	[BMI260_AUX_IF_CONF] = 0x30,
+	[BMI260_AUX_RD_ADDR] = 0x00,
+	[BMI260_AUX_WR_ADDR] = 0x00,
+	[BMI260_AUX_WR_DATA] = 0x00,
+	[0x50 ... 0x51] = 0xff, /* Reserved */
+	[BMI260_ERR_REG_MSK] = 0x20,
+	[BMI260_INT1_IO_CTRL] = 0xe1,
+	[BMI260_INT2_IO_CTRL] = 0xe1,
+	[BMI260_INT_LATCH] = 0xfe,
+	[BMI260_INT1_MAP_FEAT] = 0x00,
+	[BMI260_INT2_MAP_FEAT] = 0x00,
+	[BMI260_INT_MAP_DATA] = 0x00,
+	[BMI260_INIT_CTRL] = 0x00,
+	[0x5a] = 0xff, /* Reserved */
+	[BMI260_INIT_ADDR_0] = 0xf0,
+	[BMI260_INIT_ADDR_1] = 0x00,
+	[0x5d] = 0xff, /* Reserved */
+	[BMI260_INIT_DATA] = 0x00,
+	[BMI260_INTERNAL_ERROR] = 0xe9,
+	[0x60 ... 0x67] = 0xff, /* Reserved */
+	[BMI260_AUX_IF_TRIM] = 0xf8,
+	[BMI260_GYR_CRT_CONF] = 0xf2,
+	[BMI260_NVM_CONF] = 0xfd,
+	[BMI260_IF_CONF] = 0xcc,
+	[BMI260_DRV] = 0x00,
+	[BMI260_ACC_SELF_TEST] = 0xf2,
+	[BMI260_GYR_SELF_TEST_AXES] = 0xf0,
+	[0x6f] = 0xff, /* Reserved */
+	[BMI260_NV_CONF] = 0xf0,
+	[BMI260_OFFSET_ACC70] = 0x00,
+	[BMI260_OFFSET_ACC70 + 1] = 0x00,
+	[BMI260_OFFSET_ACC70 + 2] = 0x00,
+	[BMI260_OFFSET_GYR70] = 0x00,
+	[BMI260_OFFSET_GYR70 + 1] = 0x00,
+	[BMI260_OFFSET_GYR70 + 2] = 0x00,
+	[BMI160_OFFSET_EN_GYR98] = 0x00,
+	[0x78 ... 0x7b] = 0xff, /* Reserved */
+	[BMI260_PWR_CONF] = 0xf8,
+	[BMI260_PWR_CTRL] = 0xf0,
+	[BMI260_CMD_REG] = 0x00,
+};
+
+/**
+ * @brief Reset registers to default values and restore registers backed by NVM
+ *
+ * @param regs Pointer to array of emulator's registers
+ * @param emul Pointer to BMI emulator
+ */
+static void bmi260_emul_reset(uint8_t *regs, const struct emul *emul)
+{
+	bool tag_time;
+	bool header;
+
+	regs[BMI260_CHIP_ID] = 0x27;
+	regs[BMI260_ERR_REG] = 0x00;
+	regs[BMI260_STATUS] = 0x10;
+	regs[BMI260_AUX_X_L_G] = 0x00;
+	regs[BMI260_AUX_X_H_G] = 0x00;
+	regs[BMI260_AUX_Y_L_G] = 0x00;
+	regs[BMI260_AUX_Y_H_G] = 0x00;
+	regs[BMI260_AUX_Z_L_G] = 0x00;
+	regs[BMI260_AUX_Z_H_G] = 0x00;
+	regs[BMI260_AUX_R_L_G] = 0x00;
+	regs[BMI260_AUX_R_H_G] = 0x00;
+	regs[BMI260_ACC_X_L_G] = 0x00;
+	regs[BMI260_ACC_X_H_G] = 0x00;
+	regs[BMI260_ACC_Y_L_G] = 0x00;
+	regs[BMI260_ACC_Y_H_G] = 0x00;
+	regs[BMI260_ACC_Z_L_G] = 0x00;
+	regs[BMI260_ACC_Z_H_G] = 0x00;
+	regs[BMI260_GYR_X_L_G] = 0x00;
+	regs[BMI260_GYR_X_H_G] = 0x00;
+	regs[BMI260_GYR_Y_L_G] = 0x00;
+	regs[BMI260_GYR_Y_H_G] = 0x00;
+	regs[BMI260_GYR_Z_L_G] = 0x00;
+	regs[BMI260_GYR_Z_H_G] = 0x00;
+	regs[BMI260_SENSORTIME_0] = 0x00;
+	regs[BMI260_SENSORTIME_1] = 0x00;
+	regs[BMI260_SENSORTIME_2] = 0x00;
+	regs[BMI260_EVENT] = 0x01;
+	regs[BMI260_INT_STATUS_0] = 0x00;
+	regs[BMI260_INT_STATUS_1] = 0x00;
+	regs[BMI260_SC_OUT_0] = 0x00;
+	regs[BMI260_SC_OUT_1] = 0x00;
+	regs[BMI260_ORIENT_ACT] = 0x00;
+	regs[BMI260_INTERNAL_STATUS] = 0x00;
+	regs[BMI260_TEMPERATURE_0] = 0x00;
+	regs[BMI260_TEMPERATURE_1] = 0x80;
+	regs[BMI260_FIFO_LENGTH_0] = 0x00;
+	regs[BMI260_FIFO_LENGTH_1] = 0x00;
+	regs[BMI160_FIFO_DATA] = 0x00;
+	regs[BMI260_FEAT_PAGE] = 0x00;
+	regs[BMI260_ACC_CONF] = 0xa8;
+	regs[BMI260_ACC_RANGE] = 0x02;
+	regs[BMI260_GYR_CONF] = 0xa9;
+	regs[BMI260_GYR_RANGE] = 0x00;
+	regs[BMI260_AUX_CONF] = 0x46;
+	regs[BMI260_FIFO_DOWNS] = 0x88;
+	regs[BMI260_FIFO_WTM_0] = 0x00;
+	regs[BMI260_FIFO_WTM_1] = 0x02;
+	regs[BMI260_FIFO_CONFIG_0] = 0x02;
+	regs[BMI260_FIFO_CONFIG_1] = 0x10;
+	regs[BMI260_SATURATION] = 0x00;
+	regs[BMI260_AUX_DEV_ID] = 0x20;
+	regs[BMI260_AUX_IF_CONF] = 0x83;
+	regs[BMI260_AUX_RD_ADDR] = 0x42;
+	regs[BMI260_AUX_WR_ADDR] = 0x4c;
+	regs[BMI260_AUX_WR_DATA] = 0x02;
+	regs[BMI260_ERR_REG_MSK] = 0x00;
+	regs[BMI260_INT1_IO_CTRL] = 0x00;
+	regs[BMI260_INT2_IO_CTRL] = 0x00;
+	regs[BMI260_INT_LATCH] = 0x00;
+	regs[BMI260_INT1_MAP_FEAT] = 0x00;
+	regs[BMI260_INT2_MAP_FEAT] = 0x00;
+	regs[BMI260_INT_MAP_DATA] = 0x00;
+	regs[BMI260_INIT_CTRL] = 0x00;
+	regs[BMI260_INIT_ADDR_0] = 0x00;
+	regs[BMI260_INIT_ADDR_1] = 0x00;
+	regs[BMI260_INIT_DATA] = 0x00;
+	regs[BMI260_INTERNAL_ERROR] = 0x00;
+	regs[BMI260_AUX_IF_TRIM] = 0x01;
+	regs[BMI260_GYR_CRT_CONF] = 0x00;
+	regs[BMI260_NVM_CONF] = 0x00;
+	regs[BMI260_IF_CONF] = 0x00;
+	regs[BMI260_DRV] = 0xff;
+	regs[BMI260_ACC_SELF_TEST] = 0x00;
+	regs[BMI260_GYR_SELF_TEST_AXES] = 0x00;
+	regs[BMI260_PWR_CONF] = 0x03;
+	regs[BMI260_PWR_CTRL] = 0x00;
+	regs[BMI260_CMD_REG] = 0x00;
+
+	/* Call generic reset */
+	tag_time = regs[BMI260_FIFO_CONFIG_0] & BMI260_FIFO_TIME_EN;
+	header = regs[BMI260_FIFO_CONFIG_1] & BMI260_FIFO_HEADER_EN;
+	bmi_emul_reset_common(emul, tag_time, header);
+}
+
+/**
+ * @brief Convert range in format of ACC_RANGE register to number of bits
+ *        that should be shifted right to obtain 16 bit reported accelerometer
+ *        value from internal 32 bit value
+ *
+ * @param range Value of ACC_RANGE register
+ *
+ * @return shift Number of LSB that should be ignored from internal
+ *               accelerometer value
+ */
+static int bmi260_emul_acc_range_to_shift(uint8_t range)
+{
+	switch (range & 0xf) {
+	case BMI260_GSEL_2G:
+		return 0;
+	case BMI260_GSEL_4G:
+		return 1;
+	case BMI260_GSEL_8G:
+		return 2;
+	case BMI260_GSEL_16G:
+		return 3;
+	default:
+		return 0;
+	}
+}
+
+/**
+ * @brief Convert range in format of GYR_RANGE register to number of bits
+ *        that should be shifted right to obtain 16 bit reported gyroscope
+ *        value from internal 32 bit value
+ *
+ * @param range Value of GYR_RANGE register
+ *
+ * @return shift Number of LSB that should be ignored from internal
+ *               gyroscope value
+ */
+static int bmi260_emul_gyr_range_to_shift(uint8_t range)
+{
+	switch (range & 0x7) {
+	case BMI260_DPS_SEL_2000:
+		return 4;
+	case BMI260_DPS_SEL_1000:
+		return 3;
+	case BMI260_DPS_SEL_500:
+		return 2;
+	case BMI260_DPS_SEL_250:
+		return 1;
+	case BMI260_DPS_SEL_125:
+		return 0;
+	default:
+		return 0;
+	}
+}
+
+/**
+ * @brief Execute first part of command. Emulate state of device which is
+ *        during handling command (status bits etc). This function save time
+ *        on which command should end.
+ *
+ * @param regs Pointer to array of emulator's registers
+ * @param emul Pointer to BMI emulator
+ * @param cmd Command that is starting
+ *
+ * @return 0 on success
+ * @return -EIO on failure
+ */
+static int bmi260_emul_start_cmd(uint8_t *regs, const struct emul *emul,
+				 int cmd)
+{
+	int time;
+
+	switch (cmd) {
+	case BMI260_CMD_SOFT_RESET:
+		time = 1;
+		break;
+	case BMI260_CMD_FIFO_FLUSH:
+		time = 0;
+		break;
+	default:
+		LOG_ERR("Unknown command 0x%x", cmd);
+		return -EIO;
+	}
+
+	regs[BMI260_CMD_REG] = cmd;
+	bmi_emul_set_cmd_end_time(emul, time);
+
+	return 0;
+}
+
+/**
+ * @brief Emulate end of ongoing command.
+ *
+ * @param regs Pointer to array of emulator's registers
+ * @param emul Pointer to BMI emulator
+ */
+static void bmi260_emul_end_cmd(uint8_t *regs, const struct emul *emul)
+{
+	bool tag_time;
+	bool header;
+	int cmd;
+
+	cmd = regs[BMI260_CMD_REG];
+	regs[BMI260_CMD_REG] = 0;
+	tag_time = regs[BMI260_FIFO_CONFIG_0] & BMI260_FIFO_TIME_EN;
+	header = regs[BMI260_FIFO_CONFIG_1] & BMI260_FIFO_HEADER_EN;
+
+	switch (cmd) {
+	case BMI160_CMD_SOFT_RESET:
+		bmi260_emul_reset(regs, emul);
+		break;
+	case BMI160_CMD_FIFO_FLUSH:
+		bmi_emul_flush_fifo(emul, tag_time, header);
+		break;
+	}
+}
+
+/**
+ * @brief Get currently accessed register. It is first register plus number of
+ *        handled bytes for all registers except BMI260_FIFO_DATA and
+ *        BMI260_INIT_DATA for which address incrementation is disabled.
+ *
+ * @param emul Pointer to BMI emulator
+ * @param reg First byte of last write message
+ * @param bytes Number of bytes already handled from current message
+ * @param read If currently handled is read message
+ *
+ * @return Currently accessed register
+ */
+static int bmi260_emul_access_reg(const struct emul *emul, int reg, int byte,
+				  bool read)
+{
+	/* Ignore first byte which sets starting register */
+	if (!read) {
+		byte -= 1;
+	}
+
+	/*
+	 * If register is FIFO data, then read data from FIFO.
+	 * Init data is also block, but it is not implemented in emulator.
+	 * Else block read access subsequent registers.
+	 */
+	if (reg <= BMI260_FIFO_DATA && reg + byte >= BMI260_FIFO_DATA) {
+		return BMI260_FIFO_DATA;
+	} else if (reg <= BMI260_INIT_DATA && reg + byte >= BMI260_INIT_DATA) {
+		return BMI260_INIT_DATA;
+	}
+
+	return reg + byte;
+}
+
+/**
+ * @brief BMI260 specific write function. It handle block writes. Init data
+ *        register is trap register, so after reaching it, register address
+ *        is not increased on block writes. Check if read only register is not
+ *        accessed. Before writing value, ongoing command is finished if
+ *        possible. Write to CMD register is handled by BMI260 specific
+ *        function. On changing of FIFO header/headerless mode or
+ *        enabling/disabling sensor in headerless mode FIFO is flushed.
+ *
+ * @param regs Pointer to array of emulator's registers
+ * @param emul Pointer to BMI emulator
+ * @param reg Register address that is accessed
+ * @param byte Number of handled bytes in this write command
+ * @param val Value that is being written
+ *
+ * @return 0 on success
+ * @return BMI_EMUL_ACCESS_E on RO register access
+ * @return -EIO on error
+ */
+static int bmi260_emul_handle_write(uint8_t *regs, const struct emul *emul,
+				    int reg, int byte, uint8_t val)
+{
+	uint8_t mask;
+	bool tag_time;
+	bool header;
+
+	reg = bmi260_emul_access_reg(emul, reg, byte, false /* = read */);
+
+	if (reg <= BMI260_FIFO_DATA || reg == BMI260_GYR_SELF_TEST_AXES ||
+	    reg == BMI260_INTERNAL_ERROR || reg == BMI260_SATURATION) {
+		return BMI_EMUL_ACCESS_E;
+	}
+
+	/* Stop on going command if required */
+	if (regs[BMI260_CMD_REG] != 0 && bmi_emul_is_cmd_end(emul)) {
+		bmi260_emul_end_cmd(regs, emul);
+	}
+
+	tag_time = regs[BMI260_FIFO_CONFIG_0] & BMI260_FIFO_TIME_EN;
+	header = regs[BMI260_FIFO_CONFIG_1] & BMI260_FIFO_HEADER_EN;
+
+	switch (reg) {
+	case BMI260_CMD_REG:
+		if (regs[BMI260_CMD_REG] != 0) {
+			LOG_ERR("Issued command before previous end");
+			return -EIO;
+		}
+
+		return bmi260_emul_start_cmd(regs, emul, val);
+	case BMI260_FIFO_CONFIG_1:
+		/*
+		 * Clear FIFO on transition between headerless and
+		 * header mode
+		 */
+		if (!!(val & BMI260_FIFO_HEADER_EN) != header) {
+			bmi_emul_flush_fifo(emul, tag_time, header);
+		}
+		break;
+	case BMI260_PWR_CTRL:
+		/*
+		 * Clear FIFO on enabling/disabling sensors in headerless
+		 * mode
+		 */
+		mask = BMI260_AUX_EN & BMI260_GYR_EN & BMI260_ACC_EN;
+		if ((val & mask) != (regs[BMI260_PWR_CTRL] & mask) && !header) {
+			bmi_emul_flush_fifo(emul, tag_time, header);
+		}
+		break;
+	}
+
+	return 0;
+}
+
+/**
+ * @brief BMI260 specific read function. It handle block reads. FIFO data
+ *        register and init data register are trap registers, so
+ *        after reaching it, register address is not increased on block reads.
+ *        Before reading value, ongoing command is finished if possible.
+ *        Read of sensor data traps current emulator state in registers.
+ *        Read of FIFO length and FIFO data triggers default BMI functions.
+ *
+ * @param regs Pointer to array of emulator's registers
+ * @param emul Pointer to BMI emulator
+ * @param reg Register address that is accessed
+ * @param byte Byte which is accessed during block read
+ * @param buf Pointer where read byte should be stored
+ *
+ * @return 0 on success
+ * @return BMI_EMUL_ACCESS_E on WO register access
+ * @return -EIO on other error
+ */
+static int bmi260_emul_handle_read(uint8_t *regs, const struct emul *emul,
+				   int reg, int byte, char *buf)
+{
+	uint16_t fifo_len;
+	bool acc_off_en;
+	bool gyr_off_en;
+	bool tag_time;
+	bool header;
+	int gyr_shift;
+	int acc_shift;
+	int fifo_byte;
+
+	/* Get number of bytes readed from FIFO */
+	fifo_byte = byte - (reg - BMI260_FIFO_DATA);
+
+	reg = bmi260_emul_access_reg(emul, reg, byte, true /* = read */);
+
+	if (reg == BMI260_CMD_REG) {
+		*buf = 0;
+
+		return BMI_EMUL_ACCESS_E;
+	}
+
+	/* Stop on going command if required */
+	if (regs[BMI260_CMD_REG] != 0 && bmi_emul_is_cmd_end(emul)) {
+		bmi260_emul_end_cmd(regs, emul);
+	}
+
+	tag_time = regs[BMI260_FIFO_CONFIG_0] & BMI260_FIFO_TIME_EN;
+	header = regs[BMI260_FIFO_CONFIG_1] & BMI260_FIFO_HEADER_EN;
+	acc_off_en = regs[BMI260_NV_CONF] & BMI260_ACC_OFFSET_EN;
+	gyr_off_en = regs[BMI260_OFFSET_EN_GYR98] & BMI260_OFFSET_GYRO_EN;
+	gyr_shift = bmi260_emul_gyr_range_to_shift(regs[BMI260_GYR_RANGE]);
+	acc_shift = bmi260_emul_acc_range_to_shift(regs[BMI260_ACC_RANGE]);
+
+	switch (reg) {
+	case BMI260_GYR_X_L_G:
+	case BMI260_GYR_X_H_G:
+	case BMI260_GYR_Y_L_G:
+	case BMI260_GYR_Y_H_G:
+	case BMI260_GYR_Z_L_G:
+	case BMI260_GYR_Z_H_G:
+	case BMI260_ACC_X_L_G:
+	case BMI260_ACC_X_H_G:
+	case BMI260_ACC_Y_L_G:
+	case BMI260_ACC_Y_H_G:
+	case BMI260_ACC_Z_L_G:
+	case BMI260_ACC_Z_H_G:
+	case BMI260_SENSORTIME_0:
+	case BMI260_SENSORTIME_1:
+	case BMI260_SENSORTIME_2:
+		/*
+		 * Snapshot of current emulator state is created on data read
+		 * and shouldn't be changed until next I2C operation
+		 */
+		if (byte == 0) {
+			bmi_emul_state_to_reg(emul, acc_shift, gyr_shift,
+					      BMI260_ACC_X_L_G,
+					      BMI260_GYR_X_L_G,
+					      BMI260_SENSORTIME_0, acc_off_en,
+					      gyr_off_en);
+		}
+		break;
+	case BMI260_FIFO_LENGTH_0:
+	case BMI260_FIFO_LENGTH_1:
+		if (byte == 0) {
+			fifo_len = bmi_emul_fifo_len(emul, tag_time, header);
+			regs[BMI260_FIFO_LENGTH_0] = fifo_len & 0xff;
+			regs[BMI260_FIFO_LENGTH_1] = (fifo_len >> 8) & 0x7;
+		}
+		break;
+	case BMI260_FIFO_DATA:
+		regs[reg] = bmi_emul_get_fifo_data(emul, fifo_byte, tag_time,
+						   header, acc_shift,
+						   gyr_shift);
+		break;
+	}
+
+	*buf = regs[reg];
+
+	return 0;
+}
+
+/** Registers backed in NVM by BMI260 */
+const int bmi260_nvm_reg[] = {
+	BMI260_AUX_IF_TRIM,    BMI260_NV_CONF,		BMI260_DRV,
+	BMI260_OFFSET_ACC70,   BMI260_OFFSET_ACC70 + 1, BMI260_OFFSET_ACC70 + 2,
+	BMI260_OFFSET_GYR70,   BMI260_OFFSET_GYR70 + 1, BMI260_OFFSET_GYR70 + 2,
+	BMI260_OFFSET_EN_GYR98
+};
+
+/** Confguration of BMI260 */
+struct bmi_emul_type_data bmi260_emul = {
+	.sensortime_follow_config_frame = true,
+	.handle_write = bmi260_emul_handle_write,
+	.handle_read = bmi260_emul_handle_read,
+	.access_reg = bmi260_emul_access_reg,
+	.reset = bmi260_emul_reset,
+	.rsvd_mask = bmi_emul_260_rsvd_mask,
+	.nvm_reg = bmi260_nvm_reg,
+	.nvm_len = ARRAY_SIZE(bmi260_nvm_reg),
+	.gyr_off_reg = BMI260_OFFSET_GYR70,
+	.acc_off_reg = BMI260_OFFSET_ACC70,
+	.gyr98_off_reg = BMI260_OFFSET_EN_GYR98,
+};
+
+/** Check description in emul_bmi.h */
+const struct bmi_emul_type_data *get_bmi260_emul_type_data(void)
+{
+	return &bmi260_emul;
+}
diff --git a/zephyr/emul/emul_clock_control.c b/zephyr/emul/emul_clock_control.c
new file mode 100644
index 0000000000..e4223a5b43
--- /dev/null
+++ b/zephyr/emul/emul_clock_control.c
@@ -0,0 +1,186 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "emul/emul_clock_control.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+
+#define DT_DRV_COMPAT cros_clock_control_emul
+
+LOG_MODULE_REGISTER(clock_control_emul, CONFIG_CLOCK_CONTROL_EMUL_LOG_LEVEL);
+
+/** Data needed to maintain the current emulator state */
+struct emul_clock_ctrl_data {
+	/** The current clock rate */
+	uint32_t rate;
+	/** The current clock status */
+	enum clock_control_status status;
+	/** Async k_work structure */
+	struct k_work async_on_work;
+	/** Mutex used to guard the callback values */
+	struct k_mutex cb_mutex;
+	/** Async callback */
+	clock_control_cb_t cb;
+	/** Async user data to pass to the callback */
+	void *cb_user_data;
+	/** Async device to pass to the callback */
+	const struct device *cb_dev;
+	/** Async subsystem to pass to the callback */
+	clock_control_subsys_t cb_subsys;
+};
+
+static int drv_clock_ctrl_on(const struct device *dev,
+			     clock_control_subsys_t sys)
+{
+	struct emul_clock_ctrl_data *data = dev->data;
+	int rc;
+
+	k_mutex_lock(&data->cb_mutex, K_FOREVER);
+	if (data->status == CLOCK_CONTROL_STATUS_OFF) {
+		data->status = CLOCK_CONTROL_STATUS_ON;
+		rc = 0;
+	} else {
+		LOG_ERR("Invalid clock status: %d", data->status);
+		rc = EC_ERROR_UNIMPLEMENTED;
+	}
+	k_mutex_unlock(&data->cb_mutex);
+	return 0;
+}
+
+static int drv_clock_ctrl_off(const struct device *dev,
+			      clock_control_subsys_t sys)
+{
+	struct emul_clock_ctrl_data *data = dev->data;
+	int rc;
+
+	k_mutex_lock(&data->cb_mutex, K_FOREVER);
+	if (data->status == CLOCK_CONTROL_STATUS_ON) {
+		data->status = CLOCK_CONTROL_STATUS_OFF;
+		rc = 0;
+	} else {
+		LOG_ERR("Invalid clock status: %d", data->status);
+		rc = EC_ERROR_UNIMPLEMENTED;
+	}
+	k_mutex_unlock(&data->cb_mutex);
+	return rc;
+}
+
+static void clock_ctrl_on_from_work(struct k_work *work)
+{
+	struct emul_clock_ctrl_data *data =
+		CONTAINER_OF(work, struct emul_clock_ctrl_data, async_on_work);
+
+	k_mutex_lock(&data->cb_mutex, K_FOREVER);
+	if (data->status == CLOCK_CONTROL_STATUS_STARTING) {
+		data->status = CLOCK_CONTROL_STATUS_ON;
+		data->cb(data->cb_dev, data->cb_subsys, data->cb_user_data);
+		data->cb = NULL;
+		data->cb_dev = NULL;
+		data->cb_subsys = NULL;
+		data->cb_user_data = NULL;
+	} else {
+		LOG_ERR("Invalid clock status: %d", data->status);
+	}
+	k_mutex_unlock(&data->cb_mutex);
+}
+
+static int drv_clock_ctrl_async_on(const struct device *dev,
+				   clock_control_subsys_t sys,
+				   clock_control_cb_t cb, void *user_data)
+{
+	struct emul_clock_ctrl_data *data = dev->data;
+	int rc;
+
+	k_mutex_lock(&data->cb_mutex, K_FOREVER);
+	switch (data->status) {
+	case CLOCK_CONTROL_STATUS_ON:
+		rc = 0;
+		break;
+	case CLOCK_CONTROL_STATUS_STARTING:
+		rc = EC_ERROR_BUSY;
+		break;
+	case CLOCK_CONTROL_STATUS_OFF:
+		data->status = CLOCK_CONTROL_STATUS_STARTING;
+		data->cb = cb;
+		data->cb_dev = dev;
+		data->cb_subsys = sys;
+		data->cb_user_data = user_data;
+
+		k_work_init(&data->async_on_work, clock_ctrl_on_from_work);
+		rc = k_work_submit(&data->async_on_work);
+		if (rc > 0) {
+			/*
+			 * Work is already submitted, this should never happen
+			 * because of the above cases.
+			 */
+			rc = EC_ERROR_UNKNOWN;
+		} else if (rc < 0) {
+			rc = EC_ERROR_BUSY;
+		}
+		break;
+	default:
+		LOG_ERR("Invalid clock status: %d", data->status);
+		rc = EC_ERROR_UNIMPLEMENTED;
+	}
+	k_mutex_unlock(&data->cb_mutex);
+
+	return rc;
+}
+
+static int drv_clock_ctrl_get_rate(const struct device *dev,
+				   clock_control_subsys_t sys, uint32_t *rate)
+{
+	struct emul_clock_ctrl_data *data = dev->data;
+
+	*rate = data->rate;
+	return 0;
+}
+
+static enum clock_control_status
+drv_clock_ctrl_get_status(const struct device *dev, clock_control_subsys_t sys)
+{
+	struct emul_clock_ctrl_data *data = dev->data;
+	enum clock_control_status status;
+
+	k_mutex_lock(&data->cb_mutex, K_FOREVER);
+	status = data->status;
+	k_mutex_unlock(&data->cb_mutex);
+
+	return status;
+}
+
+static const struct clock_control_driver_api driver_api = {
+	.on = drv_clock_ctrl_on,
+	.off = drv_clock_ctrl_off,
+	.async_on = drv_clock_ctrl_async_on,
+	.get_rate = drv_clock_ctrl_get_rate,
+	.get_status = drv_clock_ctrl_get_status,
+};
+
+static int drv_clock_ctrl_init(const struct device *dev)
+{
+	struct emul_clock_ctrl_data *data = dev->data;
+
+	k_mutex_init(&data->cb_mutex);
+	return 0;
+}
+
+#define INIT_CLOCK_CTRL(n)                                                   \
+	static struct emul_clock_ctrl_data emul_clock_ctrl_data_##n = {      \
+		.status = COND_CODE_1(DT_INST_PROP(n, clock_frequency) == 0, \
+				      (CLOCK_CONTROL_STATUS_OFF),            \
+				      (CLOCK_CONTROL_STATUS_ON)),            \
+		.rate = DT_INST_PROP(n, clock_frequency),                    \
+	};                                                                   \
+	DEVICE_DT_INST_DEFINE(n, drv_clock_ctrl_init, NULL,                  \
+			      &emul_clock_ctrl_data_##n, NULL, PRE_KERNEL_1, \
+			      CONFIG_KERNEL_INIT_PRIORITY_OBJECTS,           \
+			      &driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(INIT_CLOCK_CTRL)
diff --git a/zephyr/emul/emul_common_i2c.c b/zephyr/emul/emul_common_i2c.c
new file mode 100644
index 0000000000..327188cb48
--- /dev/null
+++ b/zephyr/emul/emul_common_i2c.c
@@ -0,0 +1,449 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "emul/emul_common_i2c.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/i2c_emul.h>
+#include <zephyr/logging/log.h>
+
+#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
+LOG_MODULE_REGISTER(emul_common_i2c);
+
+/** Check description in emul_common_i2c.h */
+int i2c_common_emul_lock_data(struct i2c_common_emul_data *common_data,
+			      k_timeout_t timeout)
+{
+	return k_mutex_lock(&common_data->data_mtx, timeout);
+}
+
+/** Check description in emul_common_i2c.h */
+int i2c_common_emul_unlock_data(struct i2c_common_emul_data *common_data)
+{
+	return k_mutex_unlock(&common_data->data_mtx);
+}
+
+/** Check description in emul_common_i2c.h */
+void i2c_common_emul_set_write_func(struct i2c_common_emul_data *common_data,
+				    i2c_common_emul_write_func func, void *data)
+{
+	common_data->write_func = func;
+	common_data->write_func_data = data;
+}
+
+/** Check description in emul_common_i2c.h */
+void i2c_common_emul_set_read_func(struct i2c_common_emul_data *common_data,
+				   i2c_common_emul_read_func func, void *data)
+{
+	common_data->read_func = func;
+	common_data->read_func_data = data;
+}
+
+/** Check description in emul_common_i2c.h */
+void i2c_common_emul_set_read_fail_reg(struct i2c_common_emul_data *common_data,
+				       int reg)
+{
+	common_data->read_fail_reg = reg;
+}
+
+/** Check description in emul_common_i2c.h */
+void i2c_common_emul_set_write_fail_reg(
+	struct i2c_common_emul_data *common_data, int reg)
+{
+	common_data->write_fail_reg = reg;
+}
+
+/**
+ * @brief Call start_write emulator callback if set. It handles first byte
+ *        of I2C write message.
+ *
+ * @param emul Pointer to emulator
+ * @param data Pointer to emulator data
+ *
+ * @retval start_write emulator callback return code
+ */
+static int i2c_common_emul_start_write(const struct emul *target,
+				       struct i2c_common_emul_data *data)
+{
+	int ret = 0;
+
+	data->msg_byte = 0;
+
+	if (data->start_write) {
+		k_mutex_lock(&data->data_mtx, K_FOREVER);
+		ret = data->start_write(target, data->cur_reg);
+		k_mutex_unlock(&data->data_mtx);
+	}
+
+	return ret;
+}
+
+/**
+ * @brief Call finish_write emulator callback if set. It is called after last
+ *        byte of I2C write message.
+ *
+ * @param emul Pointer to emulator
+ * @param data Pointer to emulator data
+ *
+ * @retval finish_write emulator callback return code
+ */
+static int i2c_common_emul_finish_write(const struct emul *target,
+					struct i2c_common_emul_data *data)
+{
+	int ret = 0;
+
+	if (data->finish_write) {
+		k_mutex_lock(&data->data_mtx, K_FOREVER);
+		ret = data->finish_write(target, data->cur_reg, data->msg_byte);
+		k_mutex_unlock(&data->data_mtx);
+	}
+
+	return ret;
+}
+
+/**
+ * @brief Call start_read emulator callback if set. It prepares emulator at
+ *        the beginning of I2C read message.
+ *
+ * @param emul Pointer to emulator
+ * @param data Pointer to emulator data
+ *
+ * @retval start_read emulator callback return code
+ */
+static int i2c_common_emul_start_read(const struct emul *target,
+				      struct i2c_common_emul_data *data)
+{
+	int ret = 0;
+
+	data->msg_byte = 0;
+
+	if (data->start_read) {
+		k_mutex_lock(&data->data_mtx, K_FOREVER);
+		ret = data->start_read(target, data->cur_reg);
+		k_mutex_unlock(&data->data_mtx);
+	}
+
+	return ret;
+}
+
+/**
+ * @brief Call finish_read emulator callback if set. It is called after last
+ *        byte of I2C read message.
+ *
+ * @param emul Pointer to emulator
+ * @param data Pointer to emulator data
+ *
+ * @retval finish_read emulator callback return code
+ */
+static int i2c_common_emul_finish_read(const struct emul *target,
+				       struct i2c_common_emul_data *data)
+{
+	int ret = 0;
+
+	if (data->finish_read) {
+		k_mutex_lock(&data->data_mtx, K_FOREVER);
+		ret = data->finish_read(target, data->cur_reg, data->msg_byte);
+		k_mutex_unlock(&data->data_mtx);
+	}
+
+	return ret;
+}
+
+/**
+ * @brief Handle byte from I2C write message. First custom user handler is
+ *        called (if set). Next accessed register is compared with selected
+ *        by user fail register. Lastly, specific I2C device emulator handler
+ *        is called.
+ *
+ * @param emul Pointer to emulator
+ * @param data Pointer to emulator data
+ * @param val Value of current byte
+ *
+ * @retval 0 If successful
+ * @retval -EIO General input / output error
+ */
+static int i2c_common_emul_write_byte(const struct emul *target,
+				      struct i2c_common_emul_data *data,
+				      uint8_t val)
+{
+	int reg, ret;
+
+	/* Check if user wants to fail on accessed register */
+	if (data->access_reg) {
+		reg = data->access_reg(target, data->cur_reg, data->msg_byte,
+				       false /* = read */);
+	} else {
+		/* Ignore first (register address) byte */
+		reg = data->cur_reg + data->msg_byte - 1;
+	}
+
+	if (data->write_fail_reg == reg ||
+	    data->write_fail_reg == I2C_COMMON_EMUL_FAIL_ALL_REG) {
+		return -EIO;
+	}
+
+	/* Custom user handler */
+	if (data->write_func) {
+		ret = data->write_func(target, data->cur_reg, val,
+				       data->msg_byte, data->write_func_data);
+		if (ret < 0) {
+			return -EIO;
+		} else if (ret == 0) {
+			return 0;
+		}
+	}
+
+	/* Emulator handler */
+	if (data->write_byte) {
+		k_mutex_lock(&data->data_mtx, K_FOREVER);
+		ret = data->write_byte(target, data->cur_reg, val,
+				       data->msg_byte);
+		k_mutex_unlock(&data->data_mtx);
+		if (ret) {
+			return -EIO;
+		}
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Handle byte from I2C read message. First custom user handler is
+ *        called (if set). Next accessed register is compared with selected
+ *        by user fail register. Lastly, specific I2C device emulator handler
+ *        is called.
+ *
+ * @param emul Pointer to emulator
+ * @param data Pointer to emulator data
+ * @param val Pointer to buffer where current response byte should be stored
+ *
+ * @retval 0 If successful
+ * @retval -EIO General input / output error
+ */
+static int i2c_common_emul_read_byte(const struct emul *target,
+				     struct i2c_common_emul_data *data,
+				     uint8_t *val)
+{
+	int reg, ret;
+
+	/* Check if user wants to fail on accessed register */
+	if (data->access_reg) {
+		reg = data->access_reg(target, data->cur_reg, data->msg_byte,
+				       true /* = read */);
+	} else {
+		reg = data->cur_reg + data->msg_byte;
+	}
+
+	if (data->read_fail_reg == reg ||
+	    data->read_fail_reg == I2C_COMMON_EMUL_FAIL_ALL_REG) {
+		return -EIO;
+	}
+
+	/* Custom user handler */
+	if (data->read_func) {
+		ret = data->read_func(target, data->cur_reg, val,
+				      data->msg_byte, data->read_func_data);
+		if (ret < 0) {
+			return -EIO;
+		} else if (ret == 0) {
+			return 0;
+		}
+	}
+
+	/* Emulator handler */
+	if (data->read_byte) {
+		k_mutex_lock(&data->data_mtx, K_FOREVER);
+		ret = data->read_byte(target, data->cur_reg, val,
+				      data->msg_byte);
+		k_mutex_unlock(&data->data_mtx);
+		if (ret) {
+			return -EIO;
+		}
+	}
+
+	return 0;
+}
+
+/** Check description in emul_common_i2c.h */
+int i2c_common_emul_transfer_workhorse(const struct emul *target,
+				       struct i2c_common_emul_data *data,
+				       const struct i2c_common_emul_cfg *cfg,
+				       struct i2c_msg *msgs, int num_msgs,
+				       int addr)
+{
+	bool read, stop;
+	int ret, i;
+
+	if (cfg->addr != addr) {
+		LOG_ERR("Address mismatch, expected %02x, got %02x", cfg->addr,
+			addr);
+		return -EIO;
+	}
+
+	i2c_dump_msgs(cfg->dev_label, msgs, num_msgs, addr);
+
+	for (; num_msgs > 0; num_msgs--, msgs++) {
+		read = msgs->flags & I2C_MSG_READ;
+		stop = msgs->flags & I2C_MSG_STOP;
+
+		switch (data->msg_state) {
+		case I2C_COMMON_EMUL_IN_WRITE:
+			if (read) {
+				data->msg_state = I2C_COMMON_EMUL_NONE_MSG;
+				ret = i2c_common_emul_finish_write(target,
+								   data);
+				if (ret) {
+					return ret;
+				}
+				ret = i2c_common_emul_start_read(target, data);
+				if (ret) {
+					return ret;
+				}
+			}
+			break;
+		case I2C_COMMON_EMUL_IN_READ:
+			if (!read) {
+				data->msg_state = I2C_COMMON_EMUL_NONE_MSG;
+				ret = i2c_common_emul_finish_read(target, data);
+				if (ret) {
+					return ret;
+				}
+				/* Wait for write message with acctual data */
+				if (msgs->len == 0) {
+					continue;
+				}
+				/* Dispatch command/register address */
+				data->cur_reg = msgs->buf[0];
+				ret = i2c_common_emul_start_write(target, data);
+				if (ret) {
+					return ret;
+				}
+			}
+			break;
+		case I2C_COMMON_EMUL_NONE_MSG:
+			if (read) {
+				ret = i2c_common_emul_start_read(target, data);
+				if (ret) {
+					return ret;
+				}
+			} else {
+				/* Wait for write message with acctual data */
+				if (msgs->len == 0) {
+					continue;
+				}
+				/* Dispatch command/register address */
+				data->cur_reg = msgs->buf[0];
+				ret = i2c_common_emul_start_write(target, data);
+				if (ret) {
+					return ret;
+				}
+			}
+		}
+
+		data->msg_state = read ? I2C_COMMON_EMUL_IN_READ :
+					 I2C_COMMON_EMUL_IN_WRITE;
+
+		if (stop) {
+			data->msg_state = I2C_COMMON_EMUL_NONE_MSG;
+		}
+
+		if (!read) {
+			/*
+			 * All current emulators use first byte of write message
+			 * as command/register address for following write bytes
+			 * or read message. Skip first byte which was dispatched
+			 * already.
+			 */
+			if (data->msg_byte == 0) {
+				data->msg_byte = 1;
+				i = 1;
+			} else {
+				i = 0;
+			}
+			/* Dispatch write command */
+			for (; i < msgs->len; i++, data->msg_byte++) {
+				ret = i2c_common_emul_write_byte(target, data,
+								 msgs->buf[i]);
+				if (ret) {
+					return ret;
+				}
+			}
+			/* Finish write command */
+			if (stop) {
+				ret = i2c_common_emul_finish_write(target,
+								   data);
+				if (ret) {
+					return ret;
+				}
+			}
+		} else {
+			/* Dispatch read command */
+			for (i = 0; i < msgs->len; i++, data->msg_byte++) {
+				ret = i2c_common_emul_read_byte(
+					target, data, &(msgs->buf[i]));
+				if (ret) {
+					return ret;
+				}
+			}
+
+			/* Finish read command */
+			if (stop) {
+				ret = i2c_common_emul_finish_read(target, data);
+				if (ret) {
+					return ret;
+				}
+			}
+		}
+	}
+
+	return 0;
+}
+
+/** Check description in emul_common_i2c.h */
+int i2c_common_emul_transfer(const struct emul *target, struct i2c_msg *msgs,
+			     int num_msgs, int addr)
+{
+	const struct i2c_common_emul_cfg *cfg;
+	struct i2c_common_emul_data *data;
+
+	data = target->data;
+	cfg = target->cfg;
+
+	return i2c_common_emul_transfer_workhorse(target, data, cfg, msgs,
+						  num_msgs, addr);
+}
+
+/** Check description in emul_common_i2c.h */
+void i2c_common_emul_init(struct i2c_common_emul_data *data)
+{
+	data->msg_state = I2C_COMMON_EMUL_NONE_MSG;
+	data->msg_byte = 0;
+	data->cur_reg = 0;
+
+	data->write_func = NULL;
+	data->read_func = NULL;
+
+	data->write_fail_reg = I2C_COMMON_EMUL_NO_FAIL_REG;
+	data->read_fail_reg = I2C_COMMON_EMUL_NO_FAIL_REG;
+
+	k_mutex_init(&data->data_mtx);
+}
+
+struct i2c_emul_api i2c_common_emul_api = {
+	.transfer = i2c_common_emul_transfer,
+};
+
+static int i2c_common_emul_transfer_noop(const struct emul *target,
+					 struct i2c_msg *msgs, int num_msgs,
+					 int addr)
+{
+	return 0;
+}
+
+struct i2c_emul_api i2c_common_emul_noop = {
+	.transfer = i2c_common_emul_transfer_noop,
+};
diff --git a/zephyr/emul/emul_flash.c b/zephyr/emul/emul_flash.c
new file mode 100644
index 0000000000..90433f7902
--- /dev/null
+++ b/zephyr/emul/emul_flash.c
@@ -0,0 +1,245 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "drivers/cros_flash.h"
+#include "ec_commands.h"
+#include "flash.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/flash.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/__assert.h>
+
+#define DT_DRV_COMPAT cros_ec_flash_emul
+
+LOG_MODULE_REGISTER(emul_flash);
+
+struct flash_emul_data {
+	const struct device *flash_dev;
+};
+
+struct flash_emul_cfg {
+	/** Pointer to run-time data */
+	struct flash_emul_data *data;
+};
+
+#define FLASH_DEV DT_CHOSEN(zephyr_flash_controller)
+
+#define DRV_DATA(dev) ((struct flash_emul_data *)(dev)->data)
+
+/* Variables to emulate the protection */
+bool ro_protected, all_protected;
+
+static int cros_flash_emul_init(const struct device *dev)
+{
+	struct flash_emul_data *data = DRV_DATA(dev);
+
+	data->flash_dev = DEVICE_DT_GET(FLASH_DEV);
+	if (!device_is_ready(data->flash_dev)) {
+		LOG_ERR("%s device not ready", data->flash_dev->name);
+		return -ENODEV;
+	}
+
+	return EC_SUCCESS;
+}
+
+static int flash_check_writable_range(int offset, int size)
+{
+	/* Check out of range */
+	if (offset + size > CONFIG_FLASH_SIZE_BYTES) {
+		return EC_ERROR_INVAL;
+	}
+
+	/* Check RO protected and within the RO range */
+	if (ro_protected &&
+	    MAX(CONFIG_WP_STORAGE_OFF, offset) <
+		    MIN(CONFIG_WP_STORAGE_OFF + CONFIG_WP_STORAGE_SIZE,
+			offset + size)) {
+		return EC_ERROR_ACCESS_DENIED;
+	}
+
+	return EC_SUCCESS;
+}
+
+static int cros_flash_emul_write(const struct device *dev, int offset, int size,
+				 const char *src_data)
+{
+	int ret = 0;
+	struct flash_emul_data *data = DRV_DATA(dev);
+
+	/* Check protection */
+	if (all_protected) {
+		return EC_ERROR_ACCESS_DENIED;
+	}
+
+	if (flash_check_writable_range(offset, size)) {
+		return EC_ERROR_ACCESS_DENIED;
+	}
+
+	/* Check invalid data pointer? */
+	if (src_data == 0) {
+		return -EINVAL;
+	}
+
+	/* Lock physical flash operations */
+	crec_flash_lock_mapped_storage(1);
+
+	ret = flash_write(data->flash_dev, offset, src_data, size);
+
+	/* Unlock physical flash operations */
+	crec_flash_lock_mapped_storage(0);
+
+	return ret;
+}
+
+static int cros_flash_emul_erase(const struct device *dev, int offset, int size)
+{
+	int ret = 0;
+	struct flash_emul_data *data = DRV_DATA(dev);
+
+	/* Check protection */
+	if (all_protected) {
+		return EC_ERROR_ACCESS_DENIED;
+	}
+
+	if (flash_check_writable_range(offset, size)) {
+		return EC_ERROR_ACCESS_DENIED;
+	}
+
+	/* Address must be aligned to erase size */
+	if ((offset % CONFIG_FLASH_ERASE_SIZE) != 0) {
+		return -EINVAL;
+	}
+
+	/* Erase size must be a non-zero multiple of sectors */
+	if ((size == 0) || (size % CONFIG_FLASH_ERASE_SIZE) != 0) {
+		return -EINVAL;
+	}
+
+	/* Lock physical flash operations */
+	crec_flash_lock_mapped_storage(1);
+
+	ret = flash_erase(data->flash_dev, offset, size);
+
+	/* Unlock physical flash operations */
+	crec_flash_lock_mapped_storage(0);
+
+	return ret;
+}
+
+static int cros_flash_emul_get_protect(const struct device *dev, int bank)
+{
+	if (all_protected) {
+		return EC_ERROR_ACCESS_DENIED;
+	}
+	if (ro_protected && bank >= WP_BANK_OFFSET &&
+	    bank < WP_BANK_OFFSET + WP_BANK_COUNT) {
+		return EC_ERROR_ACCESS_DENIED;
+	}
+
+	return EC_SUCCESS;
+}
+
+static uint32_t cros_flash_emul_get_protect_flags(const struct device *dev)
+{
+	uint32_t flags = 0;
+
+	if (ro_protected) {
+		flags |= EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW;
+	}
+	if (all_protected) {
+		flags |= EC_FLASH_PROTECT_ALL_NOW;
+	}
+	return flags;
+}
+
+static int cros_flash_emul_protect_at_boot(const struct device *dev,
+					   uint32_t new_flags)
+{
+	if ((new_flags & (EC_FLASH_PROTECT_RO_AT_BOOT |
+			  EC_FLASH_PROTECT_ALL_AT_BOOT)) == 0) {
+		/* Clear protection if allowed */
+		if (crec_flash_get_protect() & EC_FLASH_PROTECT_GPIO_ASSERTED) {
+			return EC_ERROR_ACCESS_DENIED;
+		}
+
+		ro_protected = all_protected = false;
+		return EC_SUCCESS;
+	}
+
+	ro_protected = true;
+
+	if (new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT) {
+		all_protected = true;
+	}
+
+	return EC_SUCCESS;
+}
+
+static int cros_flash_emul_protect_now(const struct device *dev, int all)
+{
+	/* Emulate ALL_NOW only */
+	if (all) {
+		all_protected = true;
+	}
+
+	return EC_SUCCESS;
+}
+
+void cros_flash_emul_protect_reset(void)
+{
+	ro_protected = all_protected = false;
+}
+
+void cros_flash_emul_enable_protect(void)
+{
+	ro_protected = all_protected = true;
+}
+
+static int cros_flash_emul_get_jedec_id(const struct device *dev,
+					uint8_t *manufacturer, uint16_t *device)
+{
+	__ASSERT(false, "Not implemented");
+	return -EINVAL;
+}
+
+static int cros_flash_emul_get_status(const struct device *dev, uint8_t *sr1,
+				      uint8_t *sr2)
+{
+	__ASSERT(false, "Not implemented");
+	return -EINVAL;
+}
+
+static const struct cros_flash_driver_api emul_cros_flash_driver_api = {
+	.init = cros_flash_emul_init,
+	.physical_write = cros_flash_emul_write,
+	.physical_erase = cros_flash_emul_erase,
+	.physical_get_protect = cros_flash_emul_get_protect,
+	.physical_get_protect_flags = cros_flash_emul_get_protect_flags,
+	.physical_protect_at_boot = cros_flash_emul_protect_at_boot,
+	.physical_protect_now = cros_flash_emul_protect_now,
+	.physical_get_jedec_id = cros_flash_emul_get_jedec_id,
+	.physical_get_status = cros_flash_emul_get_status,
+};
+
+static int flash_emul_init(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	return 0;
+}
+
+#define FLASH_EMUL(n)                                                         \
+	static struct flash_emul_data flash_emul_data_##n = {};               \
+                                                                              \
+	static const struct flash_emul_cfg flash_emul_cfg_##n = {             \
+		.data = &flash_emul_data_##n,                                 \
+	};                                                                    \
+	DEVICE_DT_INST_DEFINE(n, flash_emul_init, NULL, &flash_emul_data_##n, \
+			      &flash_emul_cfg_##n, PRE_KERNEL_1,              \
+			      CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,            \
+			      &emul_cros_flash_driver_api)
+DT_INST_FOREACH_STATUS_OKAY(FLASH_EMUL);
diff --git a/zephyr/emul/emul_icm42607.c b/zephyr/emul/emul_icm42607.c
new file mode 100644
index 0000000000..62576d6027
--- /dev/null
+++ b/zephyr/emul/emul_icm42607.c
@@ -0,0 +1,222 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/accelgyro_icm42607.h"
+#include "emul/emul_icm42607.h"
+#include "emul/emul_stub_device.h"
+#include "queue.h"
+#include "util.h"
+
+#include <zephyr/device.h>
+
+#define DT_DRV_COMPAT zephyr_icm42607_emul
+
+#define REG_MAX 255
+
+struct icm42607_data {
+	struct i2c_common_emul_data common;
+	uint8_t user_bank_0[REG_MAX + 1];
+	uint8_t mreg1[REG_MAX + 1];
+	uint8_t mreg2[REG_MAX + 1];
+	struct queue fifo;
+};
+
+static const uint8_t user_bank_0_default_values[REG_MAX + 1] = {
+	[ICM42607_REG_MCLK_RDY] = ICM42607_MCLK_RDY, /* always powered on */
+	[ICM42607_REG_WHO_AM_I] = ICM42607_CHIP_ICM42607P,
+	[ICM42607_REG_INTF_CONFIG0] = 0x30, /* big endian by default */
+};
+static const uint8_t mreg1_default_values[REG_MAX + 1] = {};
+static const uint8_t mreg2_default_values[REG_MAX + 1] = {};
+
+static void icm42607_emul_fifo_flush(const struct emul *emul)
+{
+	struct icm42607_data *data = emul->data;
+	uint8_t unused;
+
+	while (queue_remove_unit(&data->fifo, &unused) == 1)
+		;
+}
+
+void icm42607_emul_reset(const struct emul *emul)
+{
+	struct icm42607_data *data = emul->data;
+
+	memcpy(data->user_bank_0, user_bank_0_default_values, REG_MAX + 1);
+	memcpy(data->mreg1, mreg1_default_values, REG_MAX + 1);
+	memcpy(data->mreg2, mreg2_default_values, REG_MAX + 1);
+	icm42607_emul_fifo_flush(emul);
+}
+
+int icm42607_emul_peek_reg(const struct emul *emul, int reg)
+{
+	struct icm42607_data *data = emul->data;
+	uint8_t *regs = data->user_bank_0;
+
+	if (!IN_RANGE(reg, 0, REG_MAX)) {
+		return -1;
+	}
+	return regs[reg];
+}
+
+int icm42607_emul_write_reg(const struct emul *emul, int reg, int val)
+{
+	struct icm42607_data *data = emul->data;
+	uint8_t *regs = data->user_bank_0;
+
+	if (!IN_RANGE(reg, 0, REG_MAX)) {
+		return -1;
+	}
+
+	regs[reg] = val;
+
+	return 0;
+}
+
+void icm42607_emul_push_fifo(const struct emul *emul, const uint8_t *src,
+			     int size)
+{
+	struct icm42607_data *data = emul->data;
+	struct queue *fifo = &data->fifo;
+
+	queue_add_units(fifo, src, size);
+}
+
+static int icm42607_emul_read(const struct emul *emul, int reg, uint8_t *val,
+			      int bytes, void *unused_data)
+{
+	struct icm42607_data *data = emul->data;
+	uint8_t *regs = data->user_bank_0;
+	int pos = reg + bytes;
+
+	if (!IN_RANGE(pos, 0, REG_MAX)) {
+		return -1;
+	}
+
+	if (reg == ICM42607_REG_FIFO_COUNT) {
+		int fifo_count = queue_count(&data->fifo);
+
+		if (bytes == 0) {
+			*val = fifo_count & 0xff;
+		} else {
+			*val = (fifo_count >> 8) & 0xff;
+		}
+
+		return bytes < 2 ? 0 : -1;
+	}
+
+	if (reg == ICM42607_REG_FIFO_DATA) {
+		return queue_remove_unit(&data->fifo, val) == 1 ? 0 : -1;
+	}
+
+	if (pos == ICM42607_REG_M_R) {
+		int block_sel = regs[ICM42607_REG_BLK_SEL_R];
+		int mreg_addr = regs[ICM42607_REG_MADDR_R];
+
+		if (!IN_RANGE(mreg_addr, 0, REG_MAX)) {
+			return -1;
+		}
+
+		if (block_sel == 0) {
+			*val = data->mreg1[mreg_addr];
+			return 0;
+		}
+		if (block_sel == 0x28) {
+			*val = data->mreg2[mreg_addr];
+			return 0;
+		}
+
+		return -1;
+	}
+
+	*val = regs[pos];
+
+	return 0;
+}
+
+static int icm42607_emul_write(const struct emul *emul, int reg, uint8_t val,
+			       int bytes, void *unused_data)
+{
+	struct icm42607_data *data = emul->data;
+	uint8_t *regs = data->user_bank_0;
+	int pos = reg + bytes - 1;
+
+	if (!IN_RANGE(pos, 0, REG_MAX) || !IN_RANGE(val, 0, UINT8_MAX)) {
+		return -1;
+	}
+
+	if (reg == ICM42607_REG_SIGNAL_PATH_RESET) {
+		if (bytes == 1 && (val & ICM42607_FIFO_FLUSH)) {
+			icm42607_emul_fifo_flush(emul);
+		}
+		return 0;
+	}
+
+	if (pos == ICM42607_REG_M_W) {
+		int block_sel = regs[ICM42607_REG_BLK_SEL_W];
+		int mreg_addr = regs[ICM42607_REG_MADDR_W];
+
+		if (!IN_RANGE(mreg_addr, 0, REG_MAX)) {
+			return -1;
+		}
+
+		if (block_sel == 0) {
+			data->mreg1[mreg_addr] = val;
+			return 0;
+		}
+		if (block_sel == 0x28) {
+			data->mreg2[mreg_addr] = val;
+			return 0;
+		}
+
+		return -1;
+	}
+
+	regs[pos] = val;
+
+	return 0;
+}
+
+static int icm42607_emul_init(const struct emul *emul,
+			      const struct device *parent)
+{
+	struct icm42607_data *data = (struct icm42607_data *)emul->data;
+	struct i2c_common_emul_data *common_data = &data->common;
+
+	i2c_common_emul_init(common_data);
+	i2c_common_emul_set_read_func(common_data, icm42607_emul_read, NULL);
+	i2c_common_emul_set_write_func(common_data, icm42607_emul_write, NULL);
+
+	icm42607_emul_reset(emul);
+
+	return 0;
+}
+
+struct i2c_common_emul_data *
+emul_icm42607_get_i2c_common_data(const struct emul *emul)
+{
+	struct icm42607_data *data = (struct icm42607_data *)emul->data;
+
+	return &data->common;
+}
+
+#define INIT_ICM42607_EMUL(n)                                          \
+	static struct i2c_common_emul_cfg common_cfg_##n;              \
+	static struct icm42607_data icm42607_data_##n;                 \
+	static struct i2c_common_emul_cfg common_cfg_##n = {           \
+		.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)),        \
+		.data = &icm42607_data_##n.common,                     \
+		.addr = DT_INST_REG_ADDR(n)                            \
+	};                                                             \
+	static struct icm42607_data icm42607_data_##n = {              \
+		.common = { .cfg = &common_cfg_##n },                  \
+		.fifo = QUEUE_NULL(1024, uint8_t),                     \
+	};                                                             \
+	EMUL_DT_INST_DEFINE(n, icm42607_emul_init, &icm42607_data_##n, \
+			    &common_cfg_##n, &i2c_common_emul_api, NULL)
+
+DT_INST_FOREACH_STATUS_OKAY(INIT_ICM42607_EMUL)
+
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
diff --git a/zephyr/emul/emul_isl923x.c b/zephyr/emul/emul_isl923x.c
new file mode 100644
index 0000000000..ef52704f4e
--- /dev/null
+++ b/zephyr/emul/emul_isl923x.c
@@ -0,0 +1,525 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/charger/isl923x.h"
+#include "driver/charger/isl923x_public.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_isl923x.h"
+#include "emul/emul_smart_battery.h"
+#include "emul/emul_stub_device.h"
+#include "i2c.h"
+
+#include <errno.h>
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/i2c_emul.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/__assert.h>
+
+#ifdef CONFIG_ZTEST
+#include <zephyr/ztest.h>
+#endif
+
+#define DT_DRV_COMPAT cros_isl923x_emul
+
+LOG_MODULE_REGISTER(isl923x_emul, CONFIG_ISL923X_EMUL_LOG_LEVEL);
+
+/** Mask used for the charge current register */
+#define REG_CHG_CURRENT_MASK GENMASK(12, 2)
+
+/** Mask used for the system voltage min register */
+#define REG_SYS_VOLTAGE_MIN_MASK GENMASK(13, 8)
+
+/** Mask used for the system voltage max register */
+#define REG_SYS_VOLTAGE_MAX_MASK GENMASK(14, 3)
+
+/** Mask used for the adapter current limit 1 register */
+#define REG_ADAPTER_CURRENT_LIMIT1_MASK GENMASK(12, 2)
+
+/** Mask used for the adapter current limit 2 register */
+#define REG_ADAPTER_CURRENT_LIMIT2_MASK GENMASK(12, 2)
+
+/** Mask used for the control 0 register */
+#define REG_CONTROL0_MASK GENMASK(15, 1)
+
+/** Mask used for the control 1 register */
+#define REG_CONTROL1_MASK (GENMASK(15, 8) | GENMASK(6, 0))
+
+/** Mask used for the control 2 register */
+#define REG_CONTROL2_MASK GENMASK(15, 0)
+
+/** Mask used for the control 3 register */
+#define REG_CONTROL3_MASK GENMASK(15, 0)
+
+/** Mask used for the control 4 register */
+#define REG_CONTROL4_MASK GENMASK(15, 0)
+
+/** Mask used for the control 8 register */
+#define REG_CONTROL8_MASK GENMASK(15, 0)
+
+/** Mask used for the control 10 register */
+#define REG_CONTROL10_MASK GENMASK(15, 0)
+
+/** Mask used for the AC PROCHOT register */
+#define REG_PROCHOT_AC_MASK GENMASK(12, 7)
+
+/** Mask used for the DC PROCHOT register */
+#define REG_PROCHOT_DC_MASK GENMASK(13, 8)
+
+/** Mask used for the INPUT VOLTAGE register */
+#define REG_INPUT_VOLTAGE_MASK GENMASK(15, 0)
+
+#define DEFAULT_R_SNS 10
+#define R_SNS CONFIG_CHARGER_SENSE_RESISTOR
+#define REG_TO_CURRENT(REG) ((REG)*DEFAULT_R_SNS / R_SNS)
+
+struct isl923x_emul_data {
+	/** Common I2C data */
+	struct i2c_common_emul_data common;
+	/** Emulated charge current limit register */
+	uint16_t current_limit_reg;
+	/** Emulated adapter current limit 1 register */
+	uint16_t adapter_current_limit1_reg;
+	/** Emulated adapter current limit 2 register */
+	uint16_t adapter_current_limit2_reg;
+	/** Emulated min voltage register */
+	uint16_t min_volt_reg;
+	/** Emulated max voltage register */
+	uint16_t max_volt_reg;
+	/** Emulated manufacturer ID register */
+	uint16_t manufacturer_id_reg;
+	/** Emulated device ID register */
+	uint16_t device_id_reg;
+	/** Emulated control 0 register */
+	uint16_t control_0_reg;
+	/** Emulated control 1 register */
+	uint16_t control_1_reg;
+	/** Emulated control 2 register */
+	uint16_t control_2_reg;
+	/** Emulated control 3 register */
+	uint16_t control_3_reg;
+	/** Emulated control 4 register */
+	uint16_t control_4_reg;
+	/** Emulated control 8 register (RAA489000-only) */
+	uint16_t control_8_reg;
+	/** Emulated control 10 register (RAA48900-only) */
+	uint16_t control_10_reg;
+	/** Emulated info 2 reg */
+	uint16_t info_2_reg;
+	/** Emulated AC PROCHOT register */
+	uint16_t ac_prochot_reg;
+	/** Emulated DC PROCHOT register */
+	uint16_t dc_prochot_reg;
+	/* Emulated RAA489000_REG_ADC_INPUT_CURRENT */
+	uint16_t adc_input_current_reg;
+	/* Emulated RAA489000_REG_ADC_CHARGE_CURRENT */
+	uint16_t adc_charge_current_reg;
+	/* Emulated RAA489000_REG_ADC_VSYS */
+	uint16_t adc_vsys_reg;
+	/** Emulated ADC vbus register */
+	uint16_t adc_vbus_reg;
+	/** Emulated input voltage register */
+	uint16_t input_voltage_reg;
+	/** Pointer to battery emulator. */
+	const struct emul *battery_emul;
+};
+
+struct isl923x_emul_cfg {
+	/** Common I2C config */
+	const struct i2c_common_emul_cfg common;
+};
+
+const struct device *isl923x_emul_get_parent(const struct emul *emulator)
+{
+	struct isl923x_emul_data *data = emulator->data;
+
+	return data->common.i2c;
+}
+
+const struct i2c_common_emul_cfg *
+isl923x_emul_get_cfg(const struct emul *emulator)
+{
+	return emulator->cfg;
+}
+
+#ifdef CONFIG_ZTEST
+static void isl923x_emul_reset(struct isl923x_emul_data *data)
+{
+	data->common.write_fail_reg = I2C_COMMON_EMUL_NO_FAIL_REG;
+	data->common.read_fail_reg = I2C_COMMON_EMUL_NO_FAIL_REG;
+}
+#endif
+
+void isl923x_emul_reset_registers(const struct emul *emulator)
+{
+	struct isl923x_emul_data *data = emulator->data;
+	struct i2c_common_emul_data common_backup = data->common;
+	const struct emul *battery_emul = data->battery_emul;
+
+	memset(data, 0, sizeof(struct isl923x_emul_data));
+	data->common = common_backup;
+	data->battery_emul = battery_emul;
+}
+
+void isl923x_emul_set_manufacturer_id(const struct emul *emulator,
+				      uint16_t manufacturer_id)
+{
+	struct isl923x_emul_data *data = emulator->data;
+
+	data->manufacturer_id_reg = manufacturer_id;
+}
+
+void isl923x_emul_set_device_id(const struct emul *emulator, uint16_t device_id)
+{
+	struct isl923x_emul_data *data = emulator->data;
+
+	data->device_id_reg = device_id;
+}
+
+bool isl923x_emul_is_learn_mode_enabled(const struct emul *emulator)
+{
+	struct isl923x_emul_data *data = emulator->data;
+
+	return (data->control_1_reg & ISL923X_C1_LEARN_MODE_ENABLE) != 0;
+}
+
+void isl923x_emul_set_learn_mode_enabled(const struct emul *emulator,
+					 bool enabled)
+{
+	struct isl923x_emul_data *data = emulator->data;
+
+	if (enabled)
+		data->control_1_reg |= ISL923X_C1_LEARN_MODE_ENABLE;
+	else
+		data->control_1_reg &= ~ISL923X_C1_LEARN_MODE_ENABLE;
+}
+
+void isl923x_emul_set_adc_vbus(const struct emul *emulator, uint16_t vbus_mv)
+{
+	struct isl923x_emul_data *data = emulator->data;
+
+	/* The VBUS voltage is returned in bits 13:6. The LSB is 96mV. */
+	data->adc_vbus_reg = ((vbus_mv / 96) << 6) & GENMASK(13, 6);
+}
+
+void raa489000_emul_set_acok_pin(const struct emul *emulator, uint16_t value)
+{
+	struct isl923x_emul_data *data = emulator->data;
+
+	if (value)
+		data->info_2_reg |= RAA489000_INFO2_ACOK;
+	else
+		data->info_2_reg &= ~RAA489000_INFO2_ACOK;
+}
+
+void raa489000_emul_set_state_machine_state(const struct emul *emulator,
+					    uint16_t value)
+{
+	struct isl923x_emul_data *data = emulator->data;
+
+	data->info_2_reg &=
+		~(RAA489000_INFO2_STATE_MASK << RAA489000_INFO2_STATE_SHIFT);
+	data->info_2_reg |= (value & RAA489000_INFO2_STATE_MASK)
+			    << RAA489000_INFO2_STATE_SHIFT;
+}
+
+/** Convenience macro for reading 16-bit registers */
+#define READ_REG_16(REG, BYTES, OUT)                             \
+	do {                                                     \
+		__ASSERT_NO_MSG((BYTES) == 0 || (BYTES) == 1);   \
+		if ((BYTES) == 0)                                \
+			*(OUT) = (uint8_t)((REG)&0xff);          \
+		else                                             \
+			*(OUT) = (uint8_t)(((REG) >> 8) & 0xff); \
+		break;                                           \
+	} while (0)
+
+static int isl923x_emul_read_byte(const struct emul *emul, int reg,
+				  uint8_t *val, int bytes)
+{
+	struct isl923x_emul_data *data = emul->data;
+
+	switch (reg) {
+	case ISL923X_REG_CHG_CURRENT:
+		READ_REG_16(data->current_limit_reg, bytes, val);
+		break;
+	case ISL923X_REG_SYS_VOLTAGE_MIN:
+		READ_REG_16(data->min_volt_reg, bytes, val);
+		break;
+	case ISL923X_REG_SYS_VOLTAGE_MAX:
+		READ_REG_16(data->max_volt_reg, bytes, val);
+		break;
+	case ISL923X_REG_ADAPTER_CURRENT_LIMIT1:
+		READ_REG_16(data->adapter_current_limit1_reg, bytes, val);
+		break;
+	case ISL923X_REG_ADAPTER_CURRENT_LIMIT2:
+		READ_REG_16(data->adapter_current_limit2_reg, bytes, val);
+		break;
+	case ISL923X_REG_MANUFACTURER_ID:
+		READ_REG_16(data->manufacturer_id_reg, bytes, val);
+		break;
+	case ISL923X_REG_DEVICE_ID:
+		READ_REG_16(data->device_id_reg, bytes, val);
+		break;
+	case ISL923X_REG_CONTROL0:
+		READ_REG_16(data->control_0_reg, bytes, val);
+		break;
+	case ISL923X_REG_CONTROL1:
+		READ_REG_16(data->control_1_reg, bytes, val);
+		break;
+	case ISL923X_REG_CONTROL2:
+		READ_REG_16(data->control_2_reg, bytes, val);
+		break;
+	case ISL9238_REG_CONTROL3:
+		READ_REG_16(data->control_3_reg, bytes, val);
+		break;
+	case ISL9238_REG_CONTROL4:
+		READ_REG_16(data->control_4_reg, bytes, val);
+		break;
+	case RAA489000_REG_CONTROL8:
+		READ_REG_16(data->control_8_reg, bytes, val);
+		break;
+	case RAA489000_REG_CONTROL10:
+		READ_REG_16(data->control_10_reg, bytes, val);
+		break;
+	case ISL9238_REG_INFO2:
+		READ_REG_16(data->info_2_reg, bytes, val);
+		break;
+	case ISL923X_REG_PROCHOT_AC:
+		READ_REG_16(data->ac_prochot_reg, bytes, val);
+		break;
+	case ISL923X_REG_PROCHOT_DC:
+		READ_REG_16(data->dc_prochot_reg, bytes, val);
+		break;
+	case RAA489000_REG_ADC_INPUT_CURRENT:
+		READ_REG_16(data->adc_input_current_reg, bytes, val);
+		break;
+	case RAA489000_REG_ADC_CHARGE_CURRENT:
+		READ_REG_16(data->adc_charge_current_reg, bytes, val);
+		break;
+	case RAA489000_REG_ADC_VSYS:
+		READ_REG_16(data->adc_vsys_reg, bytes, val);
+		break;
+	case RAA489000_REG_ADC_VBUS:
+		READ_REG_16(data->adc_vbus_reg, bytes, val);
+		break;
+	case ISL9238_REG_INPUT_VOLTAGE:
+		READ_REG_16(data->input_voltage_reg, bytes, val);
+		break;
+	default:
+		__ASSERT(false, "Attempt to read unimplemented reg 0x%02x",
+			 reg);
+		return -EINVAL;
+	}
+	return 0;
+}
+
+uint16_t isl923x_emul_peek_reg(const struct emul *emul, int reg)
+{
+	uint8_t bytes[2];
+
+	isl923x_emul_read_byte(emul, reg, &bytes[0], 0);
+	isl923x_emul_read_byte(emul, reg, &bytes[1], 1);
+
+	return bytes[1] << 8 | bytes[0];
+}
+
+/** Convenience macro for writing 16-bit registers */
+#define WRITE_REG_16(REG, BYTES, VAL, MASK)                    \
+	do {                                                   \
+		__ASSERT_NO_MSG((BYTES) == 1 || (BYTES) == 2); \
+		if ((BYTES) == 1)                              \
+			(REG) = (VAL) & (MASK);                \
+		else                                           \
+			(REG) |= ((VAL) << 8) & (MASK);        \
+	} while (0)
+
+static int isl923x_emul_write_byte(const struct emul *emul, int reg,
+				   uint8_t val, int bytes)
+{
+	struct isl923x_emul_data *data = emul->data;
+
+	switch (reg) {
+	case ISL923X_REG_CHG_CURRENT:
+		WRITE_REG_16(data->current_limit_reg, bytes, val,
+			     REG_CHG_CURRENT_MASK);
+		break;
+	case ISL923X_REG_SYS_VOLTAGE_MIN:
+		WRITE_REG_16(data->min_volt_reg, bytes, val,
+			     REG_SYS_VOLTAGE_MIN_MASK);
+		break;
+	case ISL923X_REG_SYS_VOLTAGE_MAX:
+		WRITE_REG_16(data->max_volt_reg, bytes, val,
+			     REG_SYS_VOLTAGE_MAX_MASK);
+		break;
+	case ISL923X_REG_ADAPTER_CURRENT_LIMIT1:
+		WRITE_REG_16(data->adapter_current_limit1_reg, bytes, val,
+			     REG_ADAPTER_CURRENT_LIMIT1_MASK);
+		break;
+	case ISL923X_REG_ADAPTER_CURRENT_LIMIT2:
+		WRITE_REG_16(data->adapter_current_limit2_reg, bytes, val,
+			     REG_ADAPTER_CURRENT_LIMIT2_MASK);
+		break;
+	case ISL923X_REG_CONTROL0:
+		WRITE_REG_16(data->control_0_reg, bytes, val,
+			     REG_CONTROL0_MASK);
+		break;
+	case ISL923X_REG_CONTROL1:
+		WRITE_REG_16(data->control_1_reg, bytes, val,
+			     REG_CONTROL1_MASK);
+		break;
+	case ISL923X_REG_CONTROL2:
+		WRITE_REG_16(data->control_2_reg, bytes, val,
+			     REG_CONTROL2_MASK);
+		break;
+	case ISL9238_REG_CONTROL3:
+		WRITE_REG_16(data->control_3_reg, bytes, val,
+			     REG_CONTROL3_MASK);
+		break;
+	case ISL9238_REG_CONTROL4:
+		WRITE_REG_16(data->control_4_reg, bytes, val,
+			     REG_CONTROL4_MASK);
+		break;
+	case RAA489000_REG_CONTROL8:
+		WRITE_REG_16(data->control_8_reg, bytes, val,
+			     REG_CONTROL8_MASK);
+		break;
+	case RAA489000_REG_CONTROL10:
+		WRITE_REG_16(data->control_10_reg, bytes, val,
+			     REG_CONTROL10_MASK);
+		break;
+	case RAA489000_REG_ADC_INPUT_CURRENT:
+		__ASSERT(
+			false,
+			"Write to read-only reg RAA489000_REG_ADC_INPUT_CURRENT");
+		break;
+	case RAA489000_REG_ADC_CHARGE_CURRENT:
+		__ASSERT(
+			false,
+			"Write to read-only reg RAA489000_REG_ADC_CHARGE_CURRENT");
+		break;
+	case RAA489000_REG_ADC_VSYS:
+		__ASSERT(false,
+			 "Write to read-only reg RAA489000_REG_ADC_VSYS");
+		break;
+	case RAA489000_REG_ADC_VBUS:
+		__ASSERT(false,
+			 "Write to read-only reg RAA489000_REG_ADC_VBUS");
+		break;
+	case ISL9238_REG_INFO2:
+		__ASSERT(false, "Write to read-only reg ISL9238_REG_INFO2");
+		break;
+	case ISL923X_REG_PROCHOT_AC:
+		WRITE_REG_16(data->ac_prochot_reg, bytes, val,
+			     REG_PROCHOT_AC_MASK);
+		break;
+	case ISL923X_REG_PROCHOT_DC:
+		WRITE_REG_16(data->dc_prochot_reg, bytes, val,
+			     REG_PROCHOT_DC_MASK);
+		break;
+	case ISL9238_REG_INPUT_VOLTAGE:
+		WRITE_REG_16(data->input_voltage_reg, bytes, val,
+			     REG_INPUT_VOLTAGE_MASK);
+		break;
+	default:
+		__ASSERT(false, "Attempt to write unimplemented reg 0x%02x",
+			 reg);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int isl923x_emul_finish_write(const struct emul *emul, int reg,
+				     int bytes)
+{
+	struct isl923x_emul_data *data = emul->data;
+	struct sbat_emul_bat_data *bat;
+	int16_t current;
+
+	/* This write only selected register for I2C read message */
+	if (bytes < 2) {
+		return 0;
+	}
+
+	switch (reg) {
+	case ISL923X_REG_CHG_CURRENT:
+		/* Write current to battery. */
+		if (data->battery_emul != NULL) {
+			/* We only have a single battery */
+			bat = sbat_emul_get_bat_data(data->battery_emul);
+			if (bat != NULL) {
+				current =
+					REG_TO_CURRENT(data->current_limit_reg);
+				if (current > 0)
+					bat->cur = current;
+				else
+					bat->cur = -5;
+			}
+		}
+		break;
+	}
+	return 0;
+}
+
+static int emul_isl923x_init(const struct emul *emul,
+			     const struct device *parent)
+{
+	struct isl923x_emul_data *data = emul->data;
+
+	data->common.i2c = parent;
+	i2c_common_emul_init(&data->common);
+
+	return 0;
+}
+
+#define INIT_ISL923X(n)                                                          \
+	static struct isl923x_emul_data isl923x_emul_data_##n = {              \
+		.common = {                                                    \
+			.write_byte = isl923x_emul_write_byte,                 \
+			.read_byte = isl923x_emul_read_byte,                   \
+			.finish_write = isl923x_emul_finish_write,             \
+		},                                                             \
+		.battery_emul = COND_CODE_1(                                   \
+			DT_INST_NODE_HAS_PROP(n, battery),                     \
+			(EMUL_DT_GET(DT_INST_PROP(n, battery))),               \
+			(NULL)),                                               \
+	}; \
+	static struct isl923x_emul_cfg isl923x_emul_cfg_##n = {                \
+	.common = {                                                            \
+		.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)),                \
+		.addr = DT_INST_REG_ADDR(n),                                   \
+		},                                                             \
+	}; \
+	EMUL_DT_INST_DEFINE(n, emul_isl923x_init, &isl923x_emul_data_##n,        \
+			    &isl923x_emul_cfg_##n, &i2c_common_emul_api, NULL)
+
+DT_INST_FOREACH_STATUS_OKAY(INIT_ISL923X)
+
+#ifdef CONFIG_ZTEST_NEW_API
+
+#define ISL923X_EMUL_RESET_RULE_AFTER(n) \
+	isl923x_emul_reset(&isl923x_emul_data_##n);
+
+static void emul_isl923x_reset_before(const struct ztest_unit_test *test,
+				      void *data)
+{
+	ARG_UNUSED(test);
+	ARG_UNUSED(data);
+
+	DT_INST_FOREACH_STATUS_OKAY(ISL923X_EMUL_RESET_RULE_AFTER)
+}
+ZTEST_RULE(emul_isl923x_reset, emul_isl923x_reset_before, NULL);
+#endif /* CONFIG_ZTEST_NEW_API */
+
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
+
+struct i2c_common_emul_data *
+emul_isl923x_get_i2c_common_data(const struct emul *emul)
+{
+	return emul->data;
+}
diff --git a/zephyr/emul/emul_isl9241.c b/zephyr/emul/emul_isl9241.c
new file mode 100644
index 0000000000..2b41230e5b
--- /dev/null
+++ b/zephyr/emul/emul_isl9241.c
@@ -0,0 +1,182 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charger/chg_isl9241.h"
+#include "driver/charger/isl9241.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_stub_device.h"
+#include "util.h"
+
+#include <zephyr/device.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/ztest.h>
+
+#define DT_DRV_COMPAT ISL9241_CHG_COMPAT
+
+#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
+LOG_MODULE_REGISTER(emul_isl9241);
+
+/* Device ID sits at the end of the register space (0xFF) */
+#define ISL9241_MAX_REG ISL9241_REG_DEVICE_ID
+
+struct isl9241_emul_data {
+	struct i2c_common_emul_data common;
+	uint16_t regs[ISL9241_MAX_REG + 1];
+};
+
+/* Note: registers are all 2 bytes */
+struct isl9241_reg_default {
+	uint8_t offset;
+	uint16_t val;
+};
+
+/* Chip defaults for non-zero registers (spec Rev 5.0, Table 1) */
+struct isl9241_reg_default isl9241_defaults[] = {
+	/* Note: 3s default here */
+	{ .offset = ISL9241_REG_MAX_SYSTEM_VOLTAGE, .val = 0x3120 },
+	{ .offset = ISL9241_REG_ADAPTER_CUR_LIMIT2, .val = 0x05DC },
+	{ .offset = ISL9241_REG_CONTROL1, .val = 0x0103 },
+	{ .offset = ISL9241_REG_CONTROL2, .val = 0x6000 },
+	{ .offset = ISL9241_REG_ADAPTER_CUR_LIMIT1, .val = 0x05DC },
+	{ .offset = ISL9241_REG_CONTROL6, .val = 0x1FFF },
+	{ .offset = ISL9241_REG_AC_PROCHOT, .val = 0x0C00 },
+	{ .offset = ISL9241_REG_DC_PROCHOT, .val = 0x1000 },
+	{ .offset = ISL9241_REG_OTG_VOLTAGE, .val = 0x0D08 },
+	{ .offset = ISL9241_REG_OTG_CURRENT, .val = 0x0200 },
+	{ .offset = ISL9241_REG_VIN_VOLTAGE, .val = 0x0C00 },
+	{ .offset = ISL9241_REG_CONTROL3, .val = 0x0300 },
+	{ .offset = ISL9241_REG_MANUFACTURER_ID, .val = 0x0049 },
+	{ .offset = ISL9241_REG_DEVICE_ID, .val = 0x000E },
+};
+
+void isl9241_emul_reset_regs(const struct emul *emul)
+{
+	struct isl9241_emul_data *data = (struct isl9241_emul_data *)emul->data;
+
+	memset(data->regs, 0, sizeof(data->regs));
+
+	for (int i = 0; i < ARRAY_SIZE(isl9241_defaults); i++) {
+		struct isl9241_reg_default def = isl9241_defaults[i];
+
+		data->regs[def.offset] = def.val;
+	}
+}
+
+uint16_t isl9241_emul_peek(const struct emul *emul, int reg)
+{
+	__ASSERT_NO_MSG(IN_RANGE(reg, 0, ISL9241_MAX_REG));
+
+	struct isl9241_emul_data *data = (struct isl9241_emul_data *)emul->data;
+
+	return data->regs[reg];
+}
+
+void isl9241_emul_set_vbus(const struct emul *emul, int vbus_mv)
+{
+	struct isl9241_emul_data *data = (struct isl9241_emul_data *)emul->data;
+	uint16_t adc_reg;
+
+	if (vbus_mv > 0)
+		data->regs[ISL9241_REG_INFORMATION2] |=
+			ISL9241_INFORMATION2_ACOK_PIN;
+	else
+		data->regs[ISL9241_REG_INFORMATION2] &=
+			~ISL9241_INFORMATION2_ACOK_PIN;
+
+	adc_reg = vbus_mv / ISL9241_VIN_ADC_STEP_MV;
+	adc_reg <<= ISL9241_VIN_ADC_BIT_OFFSET;
+	data->regs[ISL9241_REG_VIN_ADC_RESULTS] = adc_reg;
+}
+
+void isl9241_emul_set_vsys(const struct emul *emul, int vsys_mv)
+{
+	struct isl9241_emul_data *data = (struct isl9241_emul_data *)emul->data;
+	uint16_t adc_reg;
+
+	adc_reg = vsys_mv / ISL9241_VIN_ADC_STEP_MV;
+	adc_reg <<= ISL9241_VIN_ADC_BIT_OFFSET;
+	data->regs[ISL9241_REG_VSYS_ADC_RESULTS] = adc_reg;
+}
+
+static int isl9241_emul_read(const struct emul *emul, int reg, uint8_t *val,
+			     int bytes, void *unused_data)
+{
+	struct isl9241_emul_data *data = (struct isl9241_emul_data *)emul->data;
+
+	if (!IN_RANGE(reg, 0, ISL9241_MAX_REG))
+		return -EINVAL;
+
+	if (!IN_RANGE(bytes, 0, 1))
+		return -EINVAL;
+
+	if (bytes == 0)
+		*val = (uint8_t)(data->regs[reg] & 0xFF);
+	else
+		*val = (uint8_t)((data->regs[reg] >> 8) & 0xFF);
+
+	return 0;
+}
+
+static int isl9241_emul_write(const struct emul *emul, int reg, uint8_t val,
+			      int bytes, void *unused_data)
+{
+	struct isl9241_emul_data *data = (struct isl9241_emul_data *)emul->data;
+
+	if (!IN_RANGE(reg, 0, ISL9241_MAX_REG))
+		return -EINVAL;
+
+	if (!IN_RANGE(bytes, 1, 2))
+		return -EINVAL;
+
+	if (bytes == 1)
+		data->regs[reg] = val & 0xFF;
+	else
+		data->regs[reg] |= val << 8;
+
+	return 0;
+}
+
+static int isl9241_emul_init(const struct emul *emul,
+			     const struct device *parent)
+{
+	struct isl9241_emul_data *data = (struct isl9241_emul_data *)emul->data;
+	struct i2c_common_emul_data *common_data = &data->common;
+
+	i2c_common_emul_init(common_data);
+	i2c_common_emul_set_read_func(common_data, isl9241_emul_read, NULL);
+	i2c_common_emul_set_write_func(common_data, isl9241_emul_write, NULL);
+
+	isl9241_emul_reset_regs(emul);
+
+	return 0;
+}
+
+#define INIT_ISL9241_EMUL(n)                                              \
+	static struct i2c_common_emul_cfg common_cfg_##n;                 \
+	static struct isl9241_emul_data isl9241_emul_data_##n;            \
+	static struct i2c_common_emul_cfg common_cfg_##n = {              \
+		.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)),           \
+		.data = &isl9241_emul_data_##n.common,                    \
+		.addr = DT_INST_REG_ADDR(n)                               \
+	};                                                                \
+	EMUL_DT_INST_DEFINE(n, isl9241_emul_init, &isl9241_emul_data_##n, \
+			    &common_cfg_##n, &i2c_common_emul_api, NULL)
+
+DT_INST_FOREACH_STATUS_OKAY(INIT_ISL9241_EMUL)
+
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
+
+static void isl9241_emul_reset_rule_before(const struct ztest_unit_test *test,
+					   void *data)
+{
+	ARG_UNUSED(test);
+	ARG_UNUSED(data);
+
+#define ISL9241_EMUL_RESET_RULE_BEFORE(n) \
+	isl9241_emul_reset_regs(EMUL_DT_GET(DT_DRV_INST(n)))
+
+	DT_INST_FOREACH_STATUS_OKAY(ISL9241_EMUL_RESET_RULE_BEFORE);
+}
+ZTEST_RULE(isl9241_emul_reset, isl9241_emul_reset_rule_before, NULL);
diff --git a/zephyr/emul/emul_kb_raw.c b/zephyr/emul/emul_kb_raw.c
new file mode 100644
index 0000000000..2e8cdbdd7d
--- /dev/null
+++ b/zephyr/emul/emul_kb_raw.c
@@ -0,0 +1,135 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/logging/log.h>
+
+#include <drivers/cros_kb_raw.h>
+#include <keyboard_raw.h>
+
+#define DT_DRV_COMPAT cros_ec_kb_raw_emul
+
+LOG_MODULE_REGISTER(emul_kb_raw);
+
+struct kb_raw_emul_data {
+	int active_column;
+	int *matrix;
+};
+
+struct kb_raw_emul_cfg {
+	/** Label of the I2C device being emulated */
+	const char *dev_label;
+	/** Pointer to run-time data */
+	struct kb_raw_emul_data *data;
+	/** Number of emulated keyboard rows. */
+	int rows;
+	/** Number of emulated keyboard columns. */
+	int cols;
+};
+
+/**
+ * @brief Set up a new kn_raw emulator
+ *
+ * @param device Device node.
+ *
+ * @return 0 indicating success (always)
+ */
+static int kb_raw_emul_init(const struct device *dev)
+{
+	const struct kb_raw_emul_cfg *cfg = dev->config;
+	struct kb_raw_emul_data *data = dev->data;
+
+	memset(data->matrix, 0, sizeof(int) * cfg->cols);
+	return 0;
+}
+
+static int emul_kb_raw_init(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	return 0;
+}
+
+static int emul_kb_raw_enable_interrupt(const struct device *dev, int enable)
+{
+	ARG_UNUSED(dev);
+	ARG_UNUSED(enable);
+
+	return 0;
+}
+
+static int emul_kb_raw_read_rows(const struct device *dev)
+{
+	struct kb_raw_emul_data *data = dev->data;
+
+	if (data->active_column == KEYBOARD_COLUMN_ALL)
+		return 0;
+	if (data->active_column == KEYBOARD_COLUMN_NONE)
+		return 0;
+	return data->matrix[data->active_column];
+}
+
+static int emul_kb_raw_drive_column(const struct device *dev, int col)
+{
+	const struct kb_raw_emul_cfg *cfg = dev->config;
+	struct kb_raw_emul_data *data = dev->data;
+
+	if (col >= cfg->cols)
+		return -EINVAL;
+	data->active_column = col;
+	return 0;
+}
+
+int emul_kb_raw_set_kbstate(const struct device *dev, uint8_t row, uint8_t col,
+			    int pressed)
+{
+	const struct kb_raw_emul_cfg *cfg = dev->config;
+	struct kb_raw_emul_data *data = dev->data;
+
+	if (col >= cfg->cols || row >= cfg->rows)
+		return -EINVAL;
+	if (pressed)
+		data->matrix[col] |= 1 << row;
+	else
+		data->matrix[col] &= ~(1 << row);
+	return 0;
+}
+
+void emul_kb_raw_reset(const struct device *dev)
+{
+	const struct kb_raw_emul_cfg *cfg = dev->config;
+	struct kb_raw_emul_data *data = dev->data;
+
+	for (int col = 0; col < cfg->cols; col++) {
+		data->matrix[col] = 0;
+	}
+}
+
+static const struct cros_kb_raw_driver_api emul_kb_raw_driver_api = {
+	.init = emul_kb_raw_init,
+	.drive_colum = emul_kb_raw_drive_column,
+	.read_rows = emul_kb_raw_read_rows,
+	.enable_interrupt = emul_kb_raw_enable_interrupt,
+};
+
+#define KB_RAW_EMUL(n)                                                     \
+	static int kb_raw_emul_matrix_##n[DT_INST_PROP(n, cols)];          \
+	static struct kb_raw_emul_data kb_raw_emul_data_##n = {            \
+		.matrix = kb_raw_emul_matrix_##n,                          \
+	};                                                                 \
+                                                                           \
+	static const struct kb_raw_emul_cfg kb_raw_emul_cfg_##n = {        \
+		.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)),            \
+		.data = &kb_raw_emul_data_##n,                             \
+		.rows = DT_INST_PROP(n, rows),                             \
+		.cols = DT_INST_PROP(n, cols),                             \
+	};                                                                 \
+	DEVICE_DT_INST_DEFINE(n, kb_raw_emul_init, NULL,                   \
+			      &kb_raw_emul_data_##n, &kb_raw_emul_cfg_##n, \
+			      PRE_KERNEL_1,                                \
+			      CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,         \
+			      &emul_kb_raw_driver_api)
+DT_INST_FOREACH_STATUS_OKAY(KB_RAW_EMUL);
diff --git a/zephyr/emul/emul_lis2dw12.c b/zephyr/emul/emul_lis2dw12.c
new file mode 100644
index 0000000000..cd04cd27b5
--- /dev/null
+++ b/zephyr/emul/emul_lis2dw12.c
@@ -0,0 +1,306 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/accel_lis2dw12.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_lis2dw12.h"
+#include "emul/emul_stub_device.h"
+#include "i2c.h"
+
+#include <errno.h>
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/i2c_emul.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/__assert.h>
+
+#define DT_DRV_COMPAT cros_lis2dw12_emul
+
+LOG_MODULE_REGISTER(lis2dw12_emul, CONFIG_LIS2DW12_EMUL_LOG_LEVEL);
+
+struct lis2dw12_emul_data {
+	/** Common I2C data */
+	struct i2c_common_emul_data common;
+	/** Emulated who-am-i register */
+	uint8_t who_am_i_reg;
+	/** Emulated ctrl1 register */
+	uint8_t ctrl1_reg;
+	/** Emulated ctrl2 register */
+	uint8_t ctrl2_reg;
+	/** Emulated ctrl3 register */
+	uint8_t ctrl3_reg;
+	/** Emulated ctrl6 register */
+	uint8_t ctrl6_reg;
+	/** Emulated status register */
+	uint8_t status_reg;
+	/** Soft reset count */
+	uint32_t soft_reset_count;
+	/** Current X, Y, and Z output data registers */
+	int16_t accel_data[3];
+};
+
+struct lis2dw12_emul_cfg {
+	/** Common I2C config */
+	struct i2c_common_emul_cfg common;
+};
+
+void lis2dw12_emul_reset(const struct emul *emul)
+{
+	struct lis2dw12_emul_data *data = emul->data;
+
+	i2c_common_emul_set_read_fail_reg(&data->common,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(&data->common,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_func(&data->common, NULL, NULL);
+	i2c_common_emul_set_write_func(&data->common, NULL, NULL);
+	data->who_am_i_reg = LIS2DW12_WHO_AM_I;
+	data->ctrl1_reg = 0;
+	data->ctrl2_reg = 0;
+	data->ctrl3_reg = 0;
+	data->ctrl6_reg = 0;
+	data->status_reg = 0;
+	data->soft_reset_count = 0;
+
+	memset(data->accel_data, 0, sizeof(data->accel_data));
+}
+
+void lis2dw12_emul_set_who_am_i(const struct emul *emul, uint8_t who_am_i)
+{
+	struct lis2dw12_emul_data *data = emul->data;
+
+	data->who_am_i_reg = who_am_i;
+}
+
+uint32_t lis2dw12_emul_get_soft_reset_count(const struct emul *emul)
+{
+	struct lis2dw12_emul_data *data = emul->data;
+
+	return data->soft_reset_count;
+}
+
+static int lis2dw12_emul_read_byte(const struct emul *emul, int reg,
+				   uint8_t *val, int bytes)
+{
+	struct lis2dw12_emul_data *data = emul->data;
+
+	switch (reg) {
+	case LIS2DW12_WHO_AM_I_REG:
+		__ASSERT_NO_MSG(bytes == 0);
+		*val = data->who_am_i_reg;
+		break;
+	case LIS2DW12_CTRL1_ADDR:
+		__ASSERT_NO_MSG(bytes == 0);
+		*val = data->ctrl1_reg;
+		break;
+	case LIS2DW12_CTRL2_ADDR:
+		__ASSERT_NO_MSG(bytes == 0);
+		*val = data->ctrl2_reg;
+		break;
+	case LIS2DW12_CTRL3_ADDR:
+		__ASSERT_NO_MSG(bytes == 0);
+		*val = data->ctrl3_reg;
+		break;
+	case LIS2DW12_CTRL6_ADDR:
+		__ASSERT_NO_MSG(bytes == 0);
+		*val = data->ctrl6_reg;
+		break;
+	case LIS2DW12_STATUS_REG:
+		__ASSERT_NO_MSG(bytes == 0);
+		*val = data->status_reg;
+		break;
+	case LIS2DW12_OUT_X_L_ADDR:
+	case LIS2DW12_OUT_X_H_ADDR:
+	case LIS2DW12_OUT_Y_L_ADDR:
+	case LIS2DW12_OUT_Y_H_ADDR:
+	case LIS2DW12_OUT_Z_L_ADDR:
+	case LIS2DW12_OUT_Z_H_ADDR:
+		/* Allow multi-byte reads within this range of registers.
+		 * `bytes` is actually an offset past the starting register
+		 * `reg`.
+		 */
+
+		__ASSERT_NO_MSG(LIS2DW12_OUT_X_L_ADDR + bytes <=
+				LIS2DW12_OUT_Z_H_ADDR);
+
+		/* 0 is OUT_X_L_ADDR .. 5 is OUT_Z_H_ADDR */
+		int offset_into_odrs = reg - LIS2DW12_OUT_X_L_ADDR + bytes;
+
+		/* Which of the 3 channels we're reading. 0 = X, 1 = Y, 2 = Z */
+		int channel = offset_into_odrs / 2;
+
+		if (offset_into_odrs % 2 == 0) {
+			/* Get the LSB (L reg) */
+			*val = data->accel_data[channel] & 0xFF;
+		} else {
+			/* Get the MSB (H reg) */
+			*val = (data->accel_data[channel] >> 8) & 0xFF;
+		}
+		break;
+	default:
+		__ASSERT(false, "No read handler for register 0x%02x", reg);
+		return -EINVAL;
+	}
+	return 0;
+}
+
+uint8_t lis2dw12_emul_peek_reg(const struct emul *emul, int reg)
+{
+	__ASSERT(emul, "emul is NULL");
+
+	uint8_t val;
+	int rv;
+
+	rv = lis2dw12_emul_read_byte(emul, reg, &val, 0);
+	__ASSERT(rv == 0, "Read function returned non-zero: %d", rv);
+
+	return val;
+}
+
+uint8_t lis2dw12_emul_peek_odr(const struct emul *emul)
+{
+	__ASSERT(emul, "emul is NULL");
+
+	uint8_t reg = lis2dw12_emul_peek_reg(emul, LIS2DW12_ACC_ODR_ADDR);
+
+	return (reg & LIS2DW12_ACC_ODR_MASK) >>
+	       __builtin_ctz(LIS2DW12_ACC_ODR_MASK);
+}
+
+uint8_t lis2dw12_emul_peek_mode(const struct emul *emul)
+{
+	__ASSERT(emul, "emul is NULL");
+
+	uint8_t reg = lis2dw12_emul_peek_reg(emul, LIS2DW12_ACC_MODE_ADDR);
+
+	return (reg & LIS2DW12_ACC_MODE_MASK) >>
+	       __builtin_ctz(LIS2DW12_ACC_MODE_MASK);
+}
+
+uint8_t lis2dw12_emul_peek_lpmode(const struct emul *emul)
+{
+	__ASSERT(emul, "emul is NULL");
+
+	uint8_t reg = lis2dw12_emul_peek_reg(emul, LIS2DW12_ACC_LPMODE_ADDR);
+
+	return (reg & LIS2DW12_ACC_LPMODE_MASK);
+}
+
+static int lis2dw12_emul_write_byte(const struct emul *emul, int reg,
+				    uint8_t val, int bytes)
+{
+	struct lis2dw12_emul_data *data = emul->data;
+
+	switch (reg) {
+	case LIS2DW12_WHO_AM_I_REG:
+		LOG_ERR("Can't write to who-am-i register");
+		return -EINVAL;
+	case LIS2DW12_CTRL1_ADDR:
+		data->ctrl1_reg = val;
+		break;
+	case LIS2DW12_CTRL2_ADDR:
+		__ASSERT_NO_MSG(bytes == 1);
+		if ((val & LIS2DW12_SOFT_RESET_MASK) != 0) {
+			/* Soft reset */
+			data->soft_reset_count++;
+		}
+		data->ctrl2_reg = val & ~LIS2DW12_SOFT_RESET_MASK;
+		break;
+	case LIS2DW12_CTRL3_ADDR:
+		data->ctrl3_reg = val;
+		break;
+	case LIS2DW12_CTRL6_ADDR:
+		data->ctrl6_reg = val;
+		break;
+	case LIS2DW12_STATUS_REG:
+		__ASSERT(false,
+			 "Attempt to write to read-only status register");
+		return -EINVAL;
+	case LIS2DW12_OUT_X_L_ADDR:
+	case LIS2DW12_OUT_X_H_ADDR:
+	case LIS2DW12_OUT_Y_L_ADDR:
+	case LIS2DW12_OUT_Y_H_ADDR:
+	case LIS2DW12_OUT_Z_L_ADDR:
+	case LIS2DW12_OUT_Z_H_ADDR:
+		__ASSERT(false,
+			 "Attempt to write to data output register 0x%02x",
+			 reg);
+		return -EINVAL;
+	default:
+		__ASSERT(false, "No write handler for register 0x%02x", reg);
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static int emul_lis2dw12_init(const struct emul *emul,
+			      const struct device *parent)
+{
+	struct lis2dw12_emul_data *data = emul->data;
+
+	data->common.i2c = parent;
+	i2c_common_emul_init(&data->common);
+
+	return 0;
+}
+
+int lis2dw12_emul_set_accel_reading(const struct emul *emul, intv3_t reading)
+{
+	__ASSERT(emul, "emul is NULL");
+	struct lis2dw12_emul_data *data = emul->data;
+
+	for (int i = X; i <= Z; i++) {
+		/* Ensure we fit in a 14-bit signed integer */
+		if (reading[i] < LIS2DW12_SAMPLE_MIN ||
+		    reading[i] > LIS2DW12_SAMPLE_MAX) {
+			return -EINVAL;
+		}
+		/* Readings are left-aligned, so shift over by 2 */
+		data->accel_data[i] = reading[i] * 4;
+	}
+
+	/* Set the DRDY (data ready) bit */
+	data->status_reg |= LIS2DW12_STS_DRDY_UP;
+
+	return 0;
+}
+
+void lis2dw12_emul_clear_accel_reading(const struct emul *emul)
+{
+	__ASSERT(emul, "emul is NULL");
+	struct lis2dw12_emul_data *data = emul->data;
+
+	/* Zero out the registers and reset DRDY bit */
+	memset(data->accel_data, 0, sizeof(data->accel_data));
+	data->status_reg &= ~LIS2DW12_STS_DRDY_UP;
+}
+
+#define INIT_LIS2DW12(n)                                                    \
+	static struct lis2dw12_emul_data lis2dw12_emul_data_##n = {       \
+		.common = {                                               \
+			.write_byte = lis2dw12_emul_write_byte,           \
+			.read_byte = lis2dw12_emul_read_byte,             \
+		},                                                        \
+	}; \
+	static const struct lis2dw12_emul_cfg lis2dw12_emul_cfg_##n = {   \
+		.common = {                                               \
+			.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)),   \
+			.addr = DT_INST_REG_ADDR(n),                      \
+		},                                                        \
+	}; \
+	EMUL_DT_INST_DEFINE(n, emul_lis2dw12_init, &lis2dw12_emul_data_##n, \
+			    &lis2dw12_emul_cfg_##n, &i2c_common_emul_api,   \
+			    NULL)
+
+DT_INST_FOREACH_STATUS_OKAY(INIT_LIS2DW12)
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
+
+struct i2c_common_emul_data *
+emul_lis2dw12_get_i2c_common_data(const struct emul *emul)
+{
+	return emul->data;
+}
diff --git a/zephyr/emul/emul_ln9310.c b/zephyr/emul/emul_ln9310.c
new file mode 100644
index 0000000000..21cfa74a27
--- /dev/null
+++ b/zephyr/emul/emul_ln9310.c
@@ -0,0 +1,517 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/ln9310.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_ln9310.h"
+#include "emul/emul_stub_device.h"
+#include "hooks.h"
+#include "i2c.h"
+
+#include <errno.h>
+
+#include <zephyr/device.h>
+#include <zephyr/devicetree/gpio.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/i2c_emul.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/__assert.h>
+
+#define DT_DRV_COMPAT cros_ln9310_emul
+
+LOG_MODULE_REGISTER(ln9310_emul, CONFIG_LN9310_EMUL_LOG_LEVEL);
+
+enum functional_mode {
+	/* TODO shutdown_mode, */
+	/* TODO bypass, */
+	FUNCTIONAL_MODE_STANDBY = LN9310_SYS_STANDBY,
+	FUNCTIONAL_MODE_SWITCHING_21 = LN9310_SYS_SWITCHING21_ACTIVE,
+	FUNCTIONAL_MODE_SWITCHING_31 = LN9310_SYS_SWITCHING31_ACTIVE
+};
+
+struct ln9310_emul_data {
+	/** Common I2C data */
+	struct i2c_common_emul_data common;
+	/** Emulated int_pin port */
+	const struct device *gpio_int_port;
+	/** Emulated int_pin pin */
+	gpio_pin_t gpio_int_pin;
+	/** The current emulated battery cell type */
+	enum battery_cell_type battery_cell_type;
+	/** Current Functional Mode */
+	enum functional_mode current_mode;
+	/** Emulated TEST MODE CTRL register */
+	uint8_t test_mode_ctrl_reg;
+	/** Emulated FORCE SC21 CTRL 1 register */
+	uint8_t force_sc21_ctrl_1_reg;
+	/** Emulated FORCE SC21 CTRL 2 register */
+	uint8_t force_sc21_ctrl_2_reg;
+	/** Emulated SYS STS register */
+	uint8_t sys_sts_reg;
+	/** Emulated INT1 MSK register */
+	uint8_t int1_msk_reg;
+	/** Emulated INT1 register */
+	uint8_t int1_reg;
+	/** Emulated Lion control register */
+	uint8_t lion_ctrl_reg;
+	/** Emulated startup control register */
+	uint8_t startup_ctrl_reg;
+	/** Emulated BC STST B register */
+	uint8_t bc_sts_b_reg;
+	/** Emulated BC STST C register */
+	uint8_t bc_sts_c_reg;
+	/** Emulated cfg 0 register */
+	uint8_t cfg_0_reg;
+	/** Emulated cfg 4 register */
+	uint8_t cfg_4_reg;
+	/** Emulated cfg 5 register */
+	uint8_t cfg_5_reg;
+	/** Emulated power control register */
+	uint8_t power_ctrl_reg;
+	/** Emulated timer control register */
+	uint8_t timer_ctrl_reg;
+	/** Emulated lower bound (LB) control register */
+	uint8_t lower_bound_ctrl_reg;
+	/** Emulated spare 0 register */
+	uint8_t spare_0_reg;
+	/** Emulated swap control 0 register */
+	uint8_t swap_ctrl_0_reg;
+	/** Emulated swap control 1 register */
+	uint8_t swap_ctrl_1_reg;
+	/** Emulated swap control 2 register */
+	uint8_t swap_ctrl_2_reg;
+	/** Emulated swap control 3 register */
+	uint8_t swap_ctrl_3_reg;
+	/** Emulated track control register */
+	uint8_t track_ctrl_reg;
+	/** Emulated mode change cfg register */
+	uint8_t mode_change_cfg_reg;
+	/** Emulated system control register */
+	uint8_t sys_ctrl_reg;
+};
+
+static const struct emul *singleton;
+
+struct i2c_emul *ln9310_emul_get_i2c_emul(const struct emul *emulator)
+{
+	struct ln9310_emul_data *data = emulator->data;
+
+	return &(data->common.emul);
+}
+
+static void ln9310_emul_set_int_pin(struct ln9310_emul_data *data, bool val)
+{
+	int res = gpio_emul_input_set(data->gpio_int_port, data->gpio_int_pin,
+				      val);
+	__ASSERT_NO_MSG(res == 0);
+}
+
+static void ln9310_emul_assert_interrupt(struct ln9310_emul_data *data)
+{
+	data->int1_reg |= LN9310_INT1_MODE;
+	ln9310_emul_set_int_pin(data, false);
+}
+
+static void ln9310_emul_deassert_interrupt(struct ln9310_emul_data *data)
+{
+	ln9310_emul_set_int_pin(data, true);
+}
+
+static void mode_change(struct ln9310_emul_data *data)
+{
+	bool new_mode_in_standby = data->startup_ctrl_reg &
+				   LN9310_STARTUP_STANDBY_EN;
+	bool new_mode_in_switching_21 =
+		((data->power_ctrl_reg & LN9310_PWR_OP_MODE_MASK) ==
+		 LN9310_PWR_OP_MODE_SWITCH21) &&
+		!new_mode_in_standby;
+	bool new_mode_in_switching_31 =
+		((data->power_ctrl_reg & LN9310_PWR_OP_MODE_MASK) ==
+		 LN9310_PWR_OP_MODE_SWITCH31) &&
+		!new_mode_in_standby;
+
+	__ASSERT_NO_MSG(
+		!(new_mode_in_switching_21 && new_mode_in_switching_31));
+
+	switch (data->current_mode) {
+	case FUNCTIONAL_MODE_STANDBY:
+		if (new_mode_in_switching_21) {
+			data->current_mode = FUNCTIONAL_MODE_SWITCHING_21;
+			data->sys_sts_reg = data->current_mode;
+			ln9310_emul_assert_interrupt(data);
+		} else if (new_mode_in_switching_31) {
+			data->current_mode = FUNCTIONAL_MODE_SWITCHING_31;
+			data->sys_sts_reg = data->current_mode;
+			ln9310_emul_assert_interrupt(data);
+		}
+		break;
+	case FUNCTIONAL_MODE_SWITCHING_21:
+		if (new_mode_in_standby) {
+			data->current_mode = FUNCTIONAL_MODE_STANDBY;
+			data->sys_sts_reg = data->current_mode;
+			ln9310_emul_assert_interrupt(data);
+		} else if (new_mode_in_switching_31) {
+			data->current_mode = FUNCTIONAL_MODE_SWITCHING_31;
+			data->sys_sts_reg = data->current_mode;
+			ln9310_emul_assert_interrupt(data);
+		}
+		break;
+	case FUNCTIONAL_MODE_SWITCHING_31:
+		if (new_mode_in_standby) {
+			data->current_mode = FUNCTIONAL_MODE_STANDBY;
+			data->sys_sts_reg = data->current_mode;
+			ln9310_emul_assert_interrupt(data);
+		} else if (new_mode_in_switching_21) {
+			data->current_mode = FUNCTIONAL_MODE_SWITCHING_21;
+			data->sys_sts_reg = data->current_mode;
+			ln9310_emul_assert_interrupt(data);
+		}
+		break;
+	default:
+		__ASSERT(0, "Unrecognized mode");
+	}
+}
+
+void ln9310_emul_set_context(const struct emul *emulator)
+{
+	singleton = emulator;
+}
+
+void ln9310_emul_reset(const struct emul *emulator)
+{
+	struct ln9310_emul_data *data = emulator->data;
+	struct i2c_common_emul_data common = data->common;
+
+	gpio_pin_t gpio_int_pin = data->gpio_int_pin;
+	const struct device *gpio_int_port = data->gpio_int_port;
+
+	/* Only Reset the LN9310 Register Data */
+	memset(data, 0, sizeof(struct ln9310_emul_data));
+	data->common = common;
+	data->current_mode = LN9310_SYS_STANDBY;
+	data->gpio_int_pin = gpio_int_pin;
+	data->gpio_int_port = gpio_int_port;
+
+	ln9310_emul_deassert_interrupt(data);
+}
+
+void ln9310_emul_set_battery_cell_type(const struct emul *emulator,
+				       enum battery_cell_type type)
+{
+	struct ln9310_emul_data *data = emulator->data;
+
+	data->battery_cell_type = type;
+}
+
+void ln9310_emul_set_version(const struct emul *emulator, int version)
+{
+	struct ln9310_emul_data *data = emulator->data;
+
+	data->bc_sts_c_reg |= version & LN9310_BC_STS_C_CHIP_REV_MASK;
+}
+
+void ln9310_emul_set_vin_gt_10v(const struct emul *emulator, bool is_gt_10v)
+{
+	struct ln9310_emul_data *data = emulator->data;
+
+	if (is_gt_10v)
+		data->bc_sts_b_reg |= LN9310_BC_STS_B_INFET_OUT_SWITCH_OK;
+	else
+		data->bc_sts_b_reg &= ~LN9310_BC_STS_B_INFET_OUT_SWITCH_OK;
+}
+
+bool ln9310_emul_is_init(const struct emul *emulator)
+{
+	struct ln9310_emul_data *data = emulator->data;
+
+	bool interrupts_unmasked = (data->int1_msk_reg & LN9310_INT1_MODE) == 0;
+	bool min_switch_freq_set =
+		(data->spare_0_reg & LN9310_SPARE_0_LB_MIN_FREQ_SEL_ON) != 0;
+	bool functional_mode_switching_21_enabled =
+		(data->power_ctrl_reg & LN9310_PWR_OP_MODE_SWITCH21) != 0;
+	bool functional_mode_switching_31_enabled =
+		(data->power_ctrl_reg & LN9310_PWR_OP_MODE_SWITCH31) != 0;
+
+	return interrupts_unmasked && min_switch_freq_set &&
+	       (functional_mode_switching_21_enabled ||
+		functional_mode_switching_31_enabled);
+}
+
+enum battery_cell_type board_get_battery_cell_type(void)
+{
+	struct ln9310_emul_data *data = singleton->data;
+
+	return data->battery_cell_type;
+}
+
+static int ln9310_emul_start_write(const struct emul *emul, int reg)
+{
+	return 0;
+}
+
+static int ln9310_emul_finish_write(const struct emul *emul, int reg, int bytes)
+{
+	return 0;
+}
+
+static int ln9310_emul_write_byte(const struct emul *emul, int reg, uint8_t val,
+				  int bytes)
+{
+	struct ln9310_emul_data *data = emul->data;
+
+	__ASSERT(bytes == 1, "bytes 0x%x != 0x1 on reg 0x%x", bytes, reg);
+
+	switch (reg) {
+	case LN9310_REG_INT1:
+		data->int1_reg = val;
+		break;
+	case LN9310_REG_SYS_STS:
+		data->sys_sts_reg = val;
+		break;
+	case LN9310_REG_INT1_MSK:
+		data->int1_msk_reg = val;
+		break;
+	case LN9310_REG_STARTUP_CTRL:
+		data->startup_ctrl_reg = val;
+		break;
+	case LN9310_REG_LION_CTRL:
+		data->lion_ctrl_reg = val;
+		break;
+	case LN9310_REG_BC_STS_B:
+		data->bc_sts_b_reg = val;
+		break;
+	case LN9310_REG_BC_STS_C:
+		__ASSERT(false,
+			 "Write to an unverified as safe "
+			 "read-only register on 0x%x",
+			 reg);
+		break;
+	case LN9310_REG_CFG_0:
+		data->cfg_0_reg = val;
+		break;
+	case LN9310_REG_CFG_4:
+		data->cfg_4_reg = val;
+		break;
+	case LN9310_REG_CFG_5:
+		data->cfg_5_reg = val;
+		break;
+	case LN9310_REG_PWR_CTRL:
+		data->power_ctrl_reg = val;
+		break;
+	case LN9310_REG_TIMER_CTRL:
+		data->timer_ctrl_reg = val;
+		break;
+	case LN9310_REG_LB_CTRL:
+		data->lower_bound_ctrl_reg = val;
+		break;
+	case LN9310_REG_SPARE_0:
+		data->spare_0_reg = val;
+		break;
+	case LN9310_REG_SWAP_CTRL_0:
+		data->swap_ctrl_0_reg = val;
+		break;
+	case LN9310_REG_SWAP_CTRL_1:
+		data->swap_ctrl_1_reg = val;
+		break;
+	case LN9310_REG_SWAP_CTRL_2:
+		data->swap_ctrl_2_reg = val;
+		break;
+	case LN9310_REG_SWAP_CTRL_3:
+		data->swap_ctrl_3_reg = val;
+		break;
+	case LN9310_REG_TRACK_CTRL:
+		data->track_ctrl_reg = val;
+		break;
+	case LN9310_REG_MODE_CHANGE_CFG:
+		data->mode_change_cfg_reg = val;
+		break;
+	case LN9310_REG_SYS_CTRL:
+		data->sys_ctrl_reg = val;
+		break;
+	case LN9310_REG_FORCE_SC21_CTRL_1:
+		data->force_sc21_ctrl_1_reg = val;
+		break;
+	case LN9310_REG_FORCE_SC21_CTRL_2:
+		data->force_sc21_ctrl_2_reg = val;
+		break;
+	case LN9310_REG_TEST_MODE_CTRL:
+		data->test_mode_ctrl_reg = val;
+		break;
+	default:
+		__ASSERT(false, "Unimplemented Register Access Error on 0x%x",
+			 reg);
+	}
+	mode_change(data);
+	return 0;
+}
+
+static int ln9310_emul_start_read(const struct emul *emul, int reg)
+{
+	return 0;
+}
+
+static int ln9310_emul_finish_read(const struct emul *emul, int reg, int bytes)
+{
+	struct ln9310_emul_data *data = emul->data;
+
+	switch (reg) {
+	case LN9310_REG_INT1:
+		/* Reading the interrupt clears it. */
+		data->int1_reg = 0;
+		break;
+	}
+	return 0;
+}
+
+static int ln9310_emul_read_byte(const struct emul *emul, int reg, uint8_t *val,
+				 int bytes)
+{
+	struct ln9310_emul_data *data = emul->data;
+
+	__ASSERT(bytes == 0, "bytes 0x%x != 0x0 on reg 0x%x", bytes, reg);
+
+	switch (reg) {
+	case LN9310_REG_INT1:
+		*val = data->int1_reg;
+		/* Reading clears interrupts */
+		data->int1_reg = 0;
+		ln9310_emul_deassert_interrupt(data);
+		break;
+	case LN9310_REG_SYS_STS:
+		*val = data->sys_sts_reg;
+		break;
+	case LN9310_REG_INT1_MSK:
+		*val = data->int1_msk_reg;
+		break;
+	case LN9310_REG_STARTUP_CTRL:
+		*val = data->startup_ctrl_reg;
+		break;
+	case LN9310_REG_LION_CTRL:
+		*val = data->lion_ctrl_reg;
+		break;
+	case LN9310_REG_BC_STS_B:
+		*val = data->bc_sts_b_reg;
+		break;
+	case LN9310_REG_BC_STS_C:
+		*val = data->bc_sts_c_reg;
+		break;
+	case LN9310_REG_CFG_0:
+		*val = data->cfg_0_reg;
+		break;
+	case LN9310_REG_CFG_4:
+		*val = data->cfg_4_reg;
+		break;
+	case LN9310_REG_CFG_5:
+		*val = data->cfg_5_reg;
+		break;
+	case LN9310_REG_PWR_CTRL:
+		*val = data->power_ctrl_reg;
+		break;
+	case LN9310_REG_TIMER_CTRL:
+		*val = data->timer_ctrl_reg;
+		break;
+	case LN9310_REG_LB_CTRL:
+		*val = data->lower_bound_ctrl_reg;
+		break;
+	case LN9310_REG_SPARE_0:
+		*val = data->spare_0_reg;
+		break;
+	case LN9310_REG_SWAP_CTRL_0:
+		*val = data->swap_ctrl_0_reg;
+		break;
+	case LN9310_REG_SWAP_CTRL_1:
+		*val = data->swap_ctrl_1_reg;
+		break;
+	case LN9310_REG_SWAP_CTRL_2:
+		*val = data->swap_ctrl_2_reg;
+		break;
+	case LN9310_REG_SWAP_CTRL_3:
+		*val = data->swap_ctrl_3_reg;
+		break;
+	case LN9310_REG_TRACK_CTRL:
+		*val = data->track_ctrl_reg;
+		break;
+	case LN9310_REG_MODE_CHANGE_CFG:
+		*val = data->mode_change_cfg_reg;
+		break;
+	case LN9310_REG_SYS_CTRL:
+		*val = data->sys_ctrl_reg;
+		break;
+	case LN9310_REG_FORCE_SC21_CTRL_1:
+		*val = data->force_sc21_ctrl_1_reg;
+		break;
+	case LN9310_REG_FORCE_SC21_CTRL_2:
+		*val = data->force_sc21_ctrl_2_reg;
+		break;
+	case LN9310_REG_TEST_MODE_CTRL:
+		*val = data->test_mode_ctrl_reg;
+		break;
+	default:
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static int ln9310_emul_access_reg(const struct emul *emul, int reg, int bytes,
+				  bool read)
+{
+	return reg;
+}
+
+static int emul_ln9310_init(const struct emul *emul,
+			    const struct device *parent)
+{
+	struct ln9310_emul_data *data = emul->data;
+
+	data->common.i2c = parent;
+	i2c_common_emul_init(&data->common);
+
+	singleton = emul;
+
+	return 0;
+}
+
+#define LN9310_GET_GPIO_INT_PORT(n) \
+	DEVICE_DT_GET(DT_GPIO_CTLR(DT_INST_PROP(n, pg_int_pin), gpios))
+
+#define LN9310_GET_GPIO_INT_PIN(n) \
+	DT_GPIO_PIN(DT_INST_PROP(n, pg_int_pin), gpios)
+
+#define INIT_LN9310(n)                                                           \
+	const struct ln9310_config_t ln9310_config = {                           \
+		.i2c_port = I2C_PORT_NODELABEL(i2c0),                            \
+		.i2c_addr_flags = DT_INST_REG_ADDR(n),                           \
+	};                                                                       \
+	static struct ln9310_emul_data ln9310_emul_data_##n = {                \
+		.common = {                                                    \
+			.start_write = ln9310_emul_start_write,                \
+			.write_byte = ln9310_emul_write_byte,                  \
+			.finish_write = ln9310_emul_finish_write,              \
+			.start_read = ln9310_emul_start_read,                  \
+			.read_byte = ln9310_emul_read_byte,                    \
+			.finish_read = ln9310_emul_finish_read,                \
+			.access_reg = ln9310_emul_access_reg,                  \
+		},                                                             \
+		.gpio_int_port = LN9310_GET_GPIO_INT_PORT(n),		       \
+		.gpio_int_pin = LN9310_GET_GPIO_INT_PIN(n),		       \
+	}; \
+	static const struct i2c_common_emul_cfg ln9310_emul_cfg_##n = {          \
+		.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)),                  \
+		.addr = DT_INST_REG_ADDR(n),                                     \
+	};                                                                       \
+	EMUL_DT_INST_DEFINE(n, emul_ln9310_init, &ln9310_emul_data_##n,          \
+			    &ln9310_emul_cfg_##n, &i2c_common_emul_api, NULL)
+
+DT_INST_FOREACH_STATUS_OKAY(INIT_LN9310)
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
+
+struct i2c_common_emul_data *
+emul_ln9310_get_i2c_common_data(const struct emul *emul)
+{
+	return emul->data;
+}
diff --git a/zephyr/emul/emul_nx20p348x.c b/zephyr/emul/emul_nx20p348x.c
new file mode 100644
index 0000000000..3e4b4d7b2d
--- /dev/null
+++ b/zephyr/emul/emul_nx20p348x.c
@@ -0,0 +1,270 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/ppc/nx20p348x.h"
+#include "driver/tcpm/tcpci.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_nx20p348x.h"
+#include "emul/emul_stub_device.h"
+#include "emul/tcpc/emul_tcpci.h"
+#include "emul/utils.h"
+#include "usbc/ppc_nx20p348x.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#include <zephyr/device.h>
+#include <zephyr/devicetree/gpio.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/ztest.h>
+
+#define DT_DRV_COMPAT NX20P348X_COMPAT
+
+#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
+LOG_MODULE_REGISTER(emul_nx20p348x);
+
+/*
+ * Device control reg marks the end of defined regs for the NX20P3483 (0x0B)
+ */
+#define NX20P348X_MAX_REG NX20P348X_DEVICE_CONTROL_REG
+
+struct nx20p348x_emul_data {
+	struct i2c_common_emul_data common;
+	struct gpio_dt_spec irq_gpio;
+	const struct emul *tcpc_emul;
+	uint8_t regs[NX20P348X_MAX_REG + 1];
+	bool tcpc_interact;
+};
+
+struct nx20p348x_reg_default {
+	uint8_t offset;
+	uint8_t val;
+};
+
+/* Chip defaults for non-zero registers (spec Rev 0.4 Table 9) */
+struct nx20p348x_reg_default nx20p348x_defaults[] = {
+	{ .offset = NX20P348X_DEVICE_ID_REG, .val = 0x09 },
+	{ .offset = NX20P348X_OVLO_THRESHOLD_REG, .val = 0x01 },
+	{ .offset = NX20P348X_HV_SRC_OCP_THRESHOLD_REG, .val = 0x0B },
+	{ .offset = NX20P348X_5V_SRC_OCP_THRESHOLD_REG, .val = 0x0B },
+};
+
+static void nx20p348x_emul_interrupt_set(const struct emul *emul, int val)
+{
+	struct nx20p348x_emul_data *data =
+		(struct nx20p348x_emul_data *)emul->data;
+
+	int res = gpio_emul_input_set(data->irq_gpio.port, data->irq_gpio.pin,
+				      val);
+	__ASSERT_NO_MSG(res == 0);
+}
+
+void nx20p348x_emul_reset_regs(const struct emul *emul)
+{
+	struct nx20p348x_emul_data *data =
+		(struct nx20p348x_emul_data *)emul->data;
+
+	memset(data->regs, 0, sizeof(data->regs));
+
+	for (int i = 0; i < ARRAY_SIZE(nx20p348x_defaults); i++) {
+		struct nx20p348x_reg_default def = nx20p348x_defaults[i];
+
+		data->regs[def.offset] = def.val;
+	}
+	nx20p348x_emul_interrupt_set(emul, 1);
+	nx20p348x_emul_set_tcpc_interact(emul, true);
+}
+
+uint8_t nx20p348x_emul_peek(const struct emul *emul, int reg)
+{
+	__ASSERT_NO_MSG(IN_RANGE(reg, 0, NX20P348X_MAX_REG));
+
+	struct nx20p348x_emul_data *data =
+		(struct nx20p348x_emul_data *)emul->data;
+
+	return data->regs[reg];
+}
+
+void nx20p348x_emul_set_tcpc_interact(const struct emul *emul, bool en)
+{
+	struct nx20p348x_emul_data *data =
+		(struct nx20p348x_emul_data *)emul->data;
+	data->tcpc_interact = en;
+}
+
+void nx20p348x_emul_set_interrupt1(const struct emul *emul, uint8_t val)
+{
+	struct nx20p348x_emul_data *data =
+		(struct nx20p348x_emul_data *)emul->data;
+
+	data->regs[NX20P348X_INTERRUPT1_REG] = val;
+
+	nx20p348x_emul_interrupt_set(emul, 0);
+}
+
+static int nx20p348x_emul_read(const struct emul *emul, int reg, uint8_t *val,
+			       int bytes, void *unused_data)
+{
+	struct nx20p348x_emul_data *data =
+		(struct nx20p348x_emul_data *)emul->data;
+
+	if (!IN_RANGE(reg, 0, NX20P348X_MAX_REG))
+		return -EINVAL;
+
+	if (bytes != 0)
+		return -EINVAL;
+
+	if (IS_ENABLED(CONFIG_PLATFORM_EC_USBC_PPC_NX20P3483) &&
+	    data->tcpc_interact) {
+		uint16_t pwr_status;
+		bool src_en, snk_en;
+
+		tcpci_emul_get_reg(data->tcpc_emul, TCPC_REG_POWER_STATUS,
+				   &pwr_status);
+		src_en = pwr_status & TCPC_REG_POWER_STATUS_SOURCING_VBUS;
+		snk_en = pwr_status & TCPC_REG_POWER_STATUS_SINKING_VBUS;
+
+		if (reg == NX20P348X_SWITCH_STATUS_REG) {
+			if (src_en) {
+				data->regs[reg] |=
+					NX20P348X_SWITCH_STATUS_5VSRC;
+			} else {
+				data->regs[reg] &=
+					~(NX20P348X_SWITCH_STATUS_5VSRC |
+					  NX20P348X_SWITCH_STATUS_HVSRC);
+			}
+			if (snk_en) {
+				data->regs[reg] |=
+					NX20P348X_SWITCH_STATUS_HVSNK;
+			} else {
+				data->regs[reg] &=
+					(~NX20P348X_SWITCH_STATUS_HVSNK);
+			}
+		} else if (reg == NX20P348X_DEVICE_STATUS_REG) {
+			int mode = data->regs[reg] &
+				   (~NX20P3483_DEVICE_MODE_MASK);
+			bool db_exit =
+				!!(data->regs[NX20P348X_DEVICE_CONTROL_REG] &
+				   NX20P348X_CTRL_DB_EXIT);
+
+			if (snk_en) {
+				mode = NX20P3483_MODE_HV_SNK;
+			} else if (src_en) {
+				mode = NX20P3483_MODE_5V_SRC;
+			} else if (data->regs[NX20P348X_SWITCH_STATUS_REG] &
+				   NX20P348X_SWITCH_STATUS_HVSRC) {
+				mode = NX20P3483_MODE_HV_SRC;
+			} else if (!db_exit) {
+				mode = NX20P348X_MODE_DEAD_BATTERY;
+			}
+			data->regs[reg] = (data->regs[reg] &
+					   ~NX20P3483_DEVICE_MODE_MASK) |
+					  mode;
+		}
+	}
+
+	*val = data->regs[reg];
+
+	/* Interrupt registers are clear on read and de-assert when serviced */
+	if (reg == NX20P348X_INTERRUPT1_REG ||
+	    reg == NX20P348X_INTERRUPT2_REG) {
+		data->regs[reg] = 0;
+
+		if (data->regs[NX20P348X_INTERRUPT1_REG] == 0 &&
+		    data->regs[NX20P348X_INTERRUPT2_REG] == 0)
+			nx20p348x_emul_interrupt_set(emul, 1);
+	}
+
+	return 0;
+}
+
+static int nx20p348x_emul_write(const struct emul *emul, int reg, uint8_t val,
+				int bytes, void *unused_data)
+{
+	struct nx20p348x_emul_data *data =
+		(struct nx20p348x_emul_data *)emul->data;
+
+	if (!IN_RANGE(reg, 0, NX20P348X_MAX_REG))
+		return -EINVAL;
+
+	if (bytes != 1)
+		return -EINVAL;
+
+	data->regs[reg] = val;
+
+	if (IS_ENABLED(CONFIG_PLATFORM_EC_USBC_PPC_NX20P3481) &&
+	    reg == NX20P348X_SWITCH_CONTROL_REG) {
+		bool enabled = val & NX20P3481_SWITCH_CONTROL_HVSNK;
+
+		/* Update our status as if we turned on/off Vbus sinking */
+		if (enabled)
+			data->regs[NX20P348X_SWITCH_STATUS_REG] |=
+				NX20P348X_SWITCH_STATUS_HVSNK;
+		else
+			data->regs[NX20P348X_SWITCH_STATUS_REG] &=
+				~NX20P348X_SWITCH_STATUS_HVSNK;
+
+		/* Do the same for sourcing */
+		enabled = val & NX20P3481_SWITCH_CONTROL_5VSRC;
+		if (enabled)
+			data->regs[NX20P348X_SWITCH_STATUS_REG] |=
+				NX20P348X_SWITCH_STATUS_5VSRC;
+		else
+			data->regs[NX20P348X_SWITCH_STATUS_REG] &=
+				~NX20P348X_SWITCH_STATUS_5VSRC;
+	}
+
+	return 0;
+}
+
+static int nx20p348x_emul_init(const struct emul *emul,
+			       const struct device *parent)
+{
+	struct nx20p348x_emul_data *data =
+		(struct nx20p348x_emul_data *)emul->data;
+	struct i2c_common_emul_data *common_data = &data->common;
+
+	i2c_common_emul_init(common_data);
+	i2c_common_emul_set_read_func(common_data, nx20p348x_emul_read, NULL);
+	i2c_common_emul_set_write_func(common_data, nx20p348x_emul_write, NULL);
+
+	nx20p348x_emul_reset_regs(emul);
+
+	return 0;
+}
+
+#define INIT_NX20P348X_EMUL(n)                                                 \
+	static struct nx20p348x_emul_data nx20p348x_emul_data_##n;             \
+	static struct i2c_common_emul_cfg common_cfg_##n = {                   \
+		.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)),                \
+		.data = &nx20p348x_emul_data_##n.common,                       \
+		.addr = DT_INST_REG_ADDR(n)                                    \
+	};                                                                     \
+	static struct nx20p348x_emul_data nx20p348x_emul_data_##n = {          \
+		.irq_gpio = GPIO_DT_SPEC_INST_GET_OR(n, irq_gpios, {}),        \
+		.tcpc_emul =                                                   \
+			EMUL_GET_USBC_PROP_BINDING(ppc, DT_DRV_INST(n), tcpc), \
+		.tcpc_interact = true,                                         \
+	};                                                                     \
+	EMUL_DT_INST_DEFINE(n, nx20p348x_emul_init, &nx20p348x_emul_data_##n,  \
+			    &common_cfg_##n, &i2c_common_emul_api, NULL)
+
+DT_INST_FOREACH_STATUS_OKAY(INIT_NX20P348X_EMUL)
+
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
+
+static void nx20p348x_emul_reset_rule_before(const struct ztest_unit_test *test,
+					     void *data)
+{
+	ARG_UNUSED(test);
+	ARG_UNUSED(data);
+
+#define NX20P348X_EMUL_RESET_RULE_BEFORE(n) \
+	nx20p348x_emul_reset_regs(EMUL_DT_GET(DT_DRV_INST(n)));
+
+	DT_INST_FOREACH_STATUS_OKAY(NX20P348X_EMUL_RESET_RULE_BEFORE);
+}
+ZTEST_RULE(nx20p348x_emul_reset, nx20p348x_emul_reset_rule_before, NULL);
diff --git a/zephyr/emul/emul_pct2075.c b/zephyr/emul/emul_pct2075.c
new file mode 100644
index 0000000000..3388db4ad4
--- /dev/null
+++ b/zephyr/emul/emul_pct2075.c
@@ -0,0 +1,107 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/temp_sensor/pct2075.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_pct2075.h"
+#include "emul/emul_stub_device.h"
+#include "util.h"
+
+#include <zephyr/device.h>
+
+/* NOTE: The emulator doesn't support OS pin */
+
+#define DT_DRV_COMPAT nxp_pct2075
+
+#define PCT2075_TEMP_MAX_MC 127000
+#define PCT2075_TEMP_MIN_MC -55000
+#define PCT2075_RESOLUTION_MC 125
+
+static const uint16_t default_values[PCT2075_REG_NUMBER] = {
+	[PCT2075_REG_TEMP] = 0x00,    [PCT2075_REG_CONF] = 0x00,
+	[PCT2075_REG_THYST] = 0x4b00, [PCT2075_REG_TOS] = 0x5000,
+	[PCT2075_REG_TIDLE] = 0x00,
+};
+
+void pct2075_emul_reset_regs(const struct emul *emul)
+{
+	struct pct2075_data *data = (struct pct2075_data *)emul->data;
+
+	memcpy(data->regs, default_values, PCT2075_REG_NUMBER + 1);
+}
+
+int pct2075_emul_set_temp(const struct emul *emul, int mk)
+{
+	struct pct2075_data *data = (struct pct2075_data *)emul->data;
+	int mc = MILLI_KELVIN_TO_MILLI_CELSIUS(mk);
+	int reg;
+
+	if (!IN_RANGE(mc, PCT2075_TEMP_MIN_MC, PCT2075_TEMP_MAX_MC)) {
+		return -1;
+	}
+
+	/* Divide by the sensor resolution to get register value */
+	reg = mc / PCT2075_RESOLUTION_MC;
+
+	/* Use 11 most significant bits. */
+	data->regs[PCT2075_REG_TEMP] = reg << 5;
+
+	return 0;
+}
+
+int pct2075_emul_read_byte(const struct emul *target, int reg, uint8_t *val,
+			   int bytes)
+{
+	struct pct2075_data *data = (struct pct2075_data *)target->data;
+
+	if (!IN_RANGE(reg, 0, PCT2075_REG_NUMBER - 1)) {
+		return -1;
+	}
+
+	if (bytes == 0) {
+		*val = data->regs[reg] >> 8;
+	} else if (bytes == 1) {
+		*val = data->regs[reg] & 0x00FF;
+	} else {
+		/* Support up to 2 bytes read */
+		return -1;
+	}
+
+	return 0;
+}
+
+static int pct2075_emul_init(const struct emul *emul,
+			     const struct device *parent)
+{
+	struct pct2075_data *data = (struct pct2075_data *)emul->data;
+	struct i2c_common_emul_data *common_data = &data->common;
+
+	i2c_common_emul_init(common_data);
+
+	pct2075_emul_reset_regs(emul);
+
+	return 0;
+}
+
+#define INIT_PCT2075_EMUL(n)                                           \
+	static struct i2c_common_emul_cfg common_cfg_##n;              \
+	static struct pct2075_data pct2075_data_##n;                   \
+	static struct i2c_common_emul_cfg common_cfg_##n = {           \
+		.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)),        \
+		.data = &pct2075_data_##n.common,                      \
+		.addr = DT_INST_REG_ADDR(n)                            \
+	};                                                             \
+	static struct pct2075_data pct2075_data_##n = {              \
+		.common = {                                          \
+			.cfg = &common_cfg_##n,                      \
+			.read_byte = pct2075_emul_read_byte,         \
+		},                                                   \
+	}; \
+	EMUL_DT_INST_DEFINE(n, pct2075_emul_init, &pct2075_data_##n,   \
+			    &common_cfg_##n, &i2c_common_emul_api, NULL)
+
+DT_INST_FOREACH_STATUS_OKAY(INIT_PCT2075_EMUL)
+
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
diff --git a/zephyr/emul/emul_pi3usb9201.c b/zephyr/emul/emul_pi3usb9201.c
new file mode 100644
index 0000000000..ca3818a812
--- /dev/null
+++ b/zephyr/emul/emul_pi3usb9201.c
@@ -0,0 +1,182 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_pi3usb9201.h"
+#include "emul/emul_stub_device.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/i2c_emul.h>
+#include <zephyr/logging/log.h>
+
+#define DT_DRV_COMPAT pericom_pi3usb9201
+
+LOG_MODULE_REGISTER(emul_pi3usb9201, LOG_LEVEL_DBG);
+
+#define EMUL_REG_COUNT (PI3USB9201_REG_HOST_STS + 1)
+#define EMUL_REG_IS_VALID(reg) (reg >= 0 && reg < EMUL_REG_COUNT)
+
+/** Run-time data used by the emulator */
+struct pi3usb9201_emul_data {
+	/** Common I2C data */
+	struct i2c_common_emul_data common;
+	/** I2C emulator detail */
+	struct i2c_emul emul;
+	/** pi3usb9201 device being emulated */
+	const struct device *i2c;
+	/** Configuration information */
+	const struct pi3usb9201_emul_cfg *cfg;
+	/** Current state of all emulated pi3usb9201 registers */
+	uint8_t reg[EMUL_REG_COUNT];
+};
+
+/** Static configuration for the emulator */
+struct pi3usb9201_emul_cfg {
+	/** Pointer to run-time data */
+	struct pi3usb9201_emul_data *data;
+	/** Address of pi3usb9201 on i2c bus */
+	uint16_t addr;
+};
+
+int pi3usb9201_emul_set_reg(const struct emul *emul, int reg, uint8_t val)
+{
+	struct pi3usb9201_emul_data *data;
+
+	if (!EMUL_REG_IS_VALID(reg))
+		return -EIO;
+
+	data = emul->data;
+	data->reg[reg] = val;
+
+	return 0;
+}
+
+int pi3usb9201_emul_get_reg(const struct emul *emul, int reg, uint8_t *val)
+{
+	struct pi3usb9201_emul_data *data;
+
+	if (!EMUL_REG_IS_VALID(reg))
+		return -EIO;
+
+	data = emul->data;
+	*val = data->reg[reg];
+
+	return 0;
+}
+
+static void pi3usb9201_emul_reset(const struct emul *emul)
+{
+	struct pi3usb9201_emul_data *data;
+
+	data = emul->data;
+
+	data->reg[PI3USB9201_REG_CTRL_1] = 0;
+	data->reg[PI3USB9201_REG_CTRL_2] = 0;
+	data->reg[PI3USB9201_REG_CLIENT_STS] = 0;
+	data->reg[PI3USB9201_REG_HOST_STS] = 0;
+}
+
+/**
+ * Emulate an I2C transfer to a pi3usb9201
+ *
+ * This handles simple reads and writes
+ *
+ * @param emul I2C emulation information
+ * @param msgs List of messages to process
+ * @param num_msgs Number of messages to process
+ * @param addr Address of the I2C target device
+ *
+ * @retval 0 If successful
+ * @retval -EIO General input / output error
+ */
+static int pi3usb9201_emul_transfer(const struct emul *emul,
+				    struct i2c_msg *msgs, int num_msgs,
+				    int addr)
+{
+	const struct pi3usb9201_emul_cfg *cfg;
+	struct pi3usb9201_emul_data *data;
+
+	data = emul->data;
+	cfg = data->cfg;
+
+	if (cfg->addr != addr) {
+		LOG_ERR("Address mismatch, expected %02x, got %02x", cfg->addr,
+			addr);
+		return -EIO;
+	}
+
+	i2c_dump_msgs("emul", msgs, num_msgs, addr);
+
+	if (num_msgs == 1) {
+		if (!(((msgs[0].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) &&
+		      (msgs[0].len == 2))) {
+			LOG_ERR("Unexpected write msgs");
+			return -EIO;
+		}
+		return pi3usb9201_emul_set_reg(emul, msgs[0].buf[0],
+					       msgs[0].buf[1]);
+	} else if (num_msgs == 2) {
+		if (!(((msgs[0].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) &&
+		      (msgs[0].len == 1) &&
+		      ((msgs[1].flags & I2C_MSG_RW_MASK) == I2C_MSG_READ) &&
+		      (msgs[1].len == 1))) {
+			LOG_ERR("Unexpected read msgs");
+			return -EIO;
+		}
+		return pi3usb9201_emul_get_reg(emul, msgs[0].buf[0],
+					       &(msgs[1].buf[0]));
+	} else {
+		LOG_ERR("Unexpected num_msgs");
+		return -EIO;
+	}
+}
+
+/* Device instantiation */
+
+static struct i2c_emul_api pi3usb9201_emul_api = {
+	.transfer = pi3usb9201_emul_transfer,
+};
+
+/**
+ * @brief Set up a new pi3usb9201 emulator
+ *
+ * This should be called for each pi3usb9201 device that needs to be
+ * emulated. It registers it with the I2C emulation controller.
+ *
+ * @param emul Emulation information
+ * @param parent Device to emulate
+ *
+ * @return 0 indicating success (always)
+ */
+static int pi3usb9201_emul_init(const struct emul *emul,
+				const struct device *parent)
+{
+	const struct pi3usb9201_emul_cfg *cfg = emul->cfg;
+	struct pi3usb9201_emul_data *data = cfg->data;
+
+	data->i2c = parent;
+	data->cfg = cfg;
+
+	pi3usb9201_emul_reset(emul);
+
+	return 0;
+}
+
+#define PI3USB9201_EMUL(n)                                                  \
+	static struct pi3usb9201_emul_data pi3usb9201_emul_data_##n = {};   \
+	static const struct pi3usb9201_emul_cfg pi3usb9201_emul_cfg_##n = { \
+		.data = &pi3usb9201_emul_data_##n,                          \
+		.addr = DT_INST_REG_ADDR(n),                                \
+	};                                                                  \
+	EMUL_DT_INST_DEFINE(n, pi3usb9201_emul_init,                        \
+			    &pi3usb9201_emul_data_##n,                      \
+			    &pi3usb9201_emul_cfg_##n, &pi3usb9201_emul_api, \
+			    NULL)
+
+DT_INST_FOREACH_STATUS_OKAY(PI3USB9201_EMUL)
+
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
diff --git a/zephyr/emul/emul_ps8743.c b/zephyr/emul/emul_ps8743.c
new file mode 100644
index 0000000000..181519644f
--- /dev/null
+++ b/zephyr/emul/emul_ps8743.c
@@ -0,0 +1,105 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/usb_mux/ps8743.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_stub_device.h"
+#include "util.h"
+
+#include <zephyr/device.h>
+
+#define DT_DRV_COMPAT zephyr_ps8743_emul
+
+#define PS8743_REG_MAX 255
+
+struct ps8743_data {
+	struct i2c_common_emul_data common;
+	uint8_t regs[PS8743_REG_MAX + 1];
+};
+
+static const uint8_t default_values[PS8743_REG_MAX + 1] = {
+	[PS8743_REG_USB_EQ_RX] = 0x00,
+};
+
+void ps8743_emul_reset_regs(const struct emul *emul)
+{
+	struct ps8743_data *data = (struct ps8743_data *)emul->data;
+
+	memcpy(data->regs, default_values, PS8743_REG_MAX + 1);
+}
+
+int ps8743_emul_peek_reg(const struct emul *emul, int reg)
+{
+	struct ps8743_data *data = (struct ps8743_data *)emul->data;
+	uint8_t *regs = data->regs;
+
+	if (!IN_RANGE(reg, 0, PS8743_REG_MAX)) {
+		return -1;
+	}
+	return regs[reg];
+}
+
+static int ps8743_emul_read(const struct emul *emul, int reg, uint8_t *val,
+			    int bytes, void *unused_data)
+{
+	struct ps8743_data *data = (struct ps8743_data *)emul->data;
+	uint8_t *regs = data->regs;
+	int pos = reg + bytes;
+
+	if (!IN_RANGE(pos, 0, PS8743_REG_MAX)) {
+		return -1;
+	}
+	*val = regs[pos];
+
+	return 0;
+}
+
+static int ps8743_emul_write(const struct emul *emul, int reg, uint8_t val,
+			     int bytes, void *unused_data)
+{
+	struct ps8743_data *data = (struct ps8743_data *)emul->data;
+	uint8_t *regs = data->regs;
+	int pos = reg + bytes - 1;
+
+	if (!IN_RANGE(pos, 0, PS8743_REG_MAX) || !IN_RANGE(val, 0, UINT8_MAX)) {
+		return -1;
+	}
+	regs[pos] = val;
+
+	return 0;
+}
+
+static int ps8743_emul_init(const struct emul *emul,
+			    const struct device *parent)
+{
+	struct ps8743_data *data = (struct ps8743_data *)emul->data;
+	struct i2c_common_emul_data *common_data = &data->common;
+
+	i2c_common_emul_init(common_data);
+	i2c_common_emul_set_read_func(common_data, ps8743_emul_read, NULL);
+	i2c_common_emul_set_write_func(common_data, ps8743_emul_write, NULL);
+
+	ps8743_emul_reset_regs(emul);
+
+	return 0;
+}
+
+#define INIT_PS8743_EMUL(n)                                       \
+	static struct i2c_common_emul_cfg common_cfg_##n;         \
+	static struct ps8743_data ps8743_data##n;                 \
+	static struct i2c_common_emul_cfg common_cfg_##n = {      \
+		.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)),   \
+		.data = &ps8743_data##n.common,                   \
+		.addr = DT_INST_REG_ADDR(n)                       \
+	};                                                        \
+	static struct ps8743_data ps8743_data##n = {              \
+		.common = { .cfg = &common_cfg_##n }              \
+	};                                                        \
+	EMUL_DT_INST_DEFINE(n, ps8743_emul_init, &ps8743_data##n, \
+			    &common_cfg_##n, &i2c_common_emul_api, NULL)
+
+DT_INST_FOREACH_STATUS_OKAY(INIT_PS8743_EMUL)
+
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
diff --git a/zephyr/emul/emul_rt9490.c b/zephyr/emul/emul_rt9490.c
new file mode 100644
index 0000000000..290ae6c4da
--- /dev/null
+++ b/zephyr/emul/emul_rt9490.c
@@ -0,0 +1,122 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/charger/rt9490.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_rt9490.h"
+#include "emul/emul_stub_device.h"
+#include "util.h"
+
+#include <zephyr/device.h>
+
+#define DT_DRV_COMPAT zephyr_rt9490_emul
+
+#define RT9490_REG_MAX 255
+
+struct rt9490_data {
+	struct i2c_common_emul_data common;
+	uint8_t regs[RT9490_REG_MAX + 1];
+};
+
+static const uint8_t default_values[RT9490_REG_MAX + 1] = {
+	[RT9490_REG_CHG_CTRL0] = 0xA2,
+	[RT9490_REG_SAFETY_TMR_CTRL] = 0x3D,
+	[RT9490_REG_DEVICE_INFO] = 0x60,
+	[RT9490_REG_ADD_CTRL0] = 0x76,
+};
+
+void rt9490_emul_reset_regs(const struct emul *emul)
+{
+	struct rt9490_data *data = emul->data;
+
+	memcpy(data->regs, default_values, RT9490_REG_MAX + 1);
+}
+
+int rt9490_emul_peek_reg(const struct emul *emul, int reg)
+{
+	struct rt9490_data *data = emul->data;
+	uint8_t *regs = data->regs;
+
+	if (!IN_RANGE(reg, 0, RT9490_REG_MAX)) {
+		return -1;
+	}
+	return regs[reg];
+}
+
+int rt9490_emul_write_reg(const struct emul *emul, int reg, int val)
+{
+	struct rt9490_data *data = emul->data;
+	uint8_t *regs = data->regs;
+
+	if (!IN_RANGE(reg, 0, RT9490_REG_MAX)) {
+		return -1;
+	}
+	regs[reg] = val;
+
+	return 0;
+}
+
+static int rt9490_emul_read(const struct emul *emul, int reg, uint8_t *val,
+			    int bytes, void *unused_data)
+{
+	struct rt9490_data *data = emul->data;
+	uint8_t *regs = data->regs;
+	int pos = reg + bytes;
+
+	if (!IN_RANGE(pos, 0, RT9490_REG_MAX)) {
+		return -1;
+	}
+	*val = regs[pos];
+
+	return 0;
+}
+
+static int rt9490_emul_write(const struct emul *emul, int reg, uint8_t val,
+			     int bytes, void *unused_data)
+{
+	struct rt9490_data *data = emul->data;
+	uint8_t *regs = data->regs;
+	int pos = reg + bytes - 1;
+
+	if (!IN_RANGE(pos, 0, RT9490_REG_MAX) || !IN_RANGE(val, 0, UINT8_MAX)) {
+		return -1;
+	}
+	regs[pos] = val;
+
+	return 0;
+}
+
+static int rt9490_emul_init(const struct emul *emul,
+			    const struct device *parent)
+{
+	struct rt9490_data *data = (struct rt9490_data *)emul->data;
+	struct i2c_common_emul_data *common_data = &data->common;
+
+	i2c_common_emul_init(common_data);
+	i2c_common_emul_set_read_func(common_data, rt9490_emul_read, NULL);
+	i2c_common_emul_set_write_func(common_data, rt9490_emul_write, NULL);
+
+	rt9490_emul_reset_regs(emul);
+
+	return 0;
+}
+
+#define INIT_RT9490_EMUL(n)                                        \
+	static struct i2c_common_emul_cfg common_cfg_##n;          \
+	static struct rt9490_data rt9490_data_##n;                 \
+	static struct i2c_common_emul_cfg common_cfg_##n = {       \
+		.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)),    \
+		.data = &rt9490_data_##n.common,                   \
+		.addr = DT_INST_REG_ADDR(n)                        \
+	};                                                         \
+	static struct rt9490_data rt9490_data_##n = {              \
+		.common = { .cfg = &common_cfg_##n }               \
+	};                                                         \
+	EMUL_DT_INST_DEFINE(n, rt9490_emul_init, &rt9490_data_##n, \
+			    &common_cfg_##n, &i2c_common_emul_api, NULL)
+
+DT_INST_FOREACH_STATUS_OKAY(INIT_RT9490_EMUL)
+
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
diff --git a/zephyr/emul/emul_rtc.c b/zephyr/emul/emul_rtc.c
new file mode 100644
index 0000000000..845f0e8d78
--- /dev/null
+++ b/zephyr/emul/emul_rtc.c
@@ -0,0 +1,145 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* This is not a chip emulator, it's a fake driver. */
+
+#include "drivers/cros_rtc.h"
+#include "ec_commands.h"
+#include "flash.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/__assert.h>
+
+#define DT_DRV_COMPAT cros_ec_rtc_emul
+
+LOG_MODULE_REGISTER(emul_rtc);
+
+struct cros_rtc_emul_data {
+	const struct device *rtc_dev;
+	uint32_t alarm_time;
+	cros_rtc_alarm_callback_t alarm_callback;
+	uint32_t value;
+};
+
+struct rtc_emul_cfg {
+	/** Pointer to run-time data */
+	struct cros_rtc_emul_data *data;
+};
+
+#define RTC_DEV DT_CHOSEN(zephyr_rtc_controller)
+
+#define DRV_DATA(dev) ((struct cros_rtc_emul_data *)(dev)->data)
+
+static int cros_rtc_emul_configure(const struct device *dev,
+				   cros_rtc_alarm_callback_t callback)
+{
+	struct cros_rtc_emul_data *data = DRV_DATA(dev);
+
+	if (callback == NULL) {
+		return -EINVAL;
+	}
+
+	data->alarm_callback = callback;
+
+	return EC_SUCCESS;
+}
+
+static int cros_rtc_emul_get_value(const struct device *dev, uint32_t *value)
+{
+	struct cros_rtc_emul_data *data = DRV_DATA(dev);
+
+	*value = data->value;
+
+	return EC_SUCCESS;
+}
+
+static int cros_rtc_emul_set_value(const struct device *dev, uint32_t value)
+{
+	struct cros_rtc_emul_data *data = DRV_DATA(dev);
+
+	data->value = value;
+
+	if (data->value >= data->alarm_time && data->alarm_time) {
+		data->alarm_callback(dev);
+	}
+
+	return EC_SUCCESS;
+}
+
+static int cros_rtc_emul_get_alarm(const struct device *dev, uint32_t *seconds,
+				   uint32_t *microseconds)
+{
+	struct cros_rtc_emul_data *data = DRV_DATA(dev);
+
+	*seconds = data->alarm_time;
+	*microseconds = 0;
+
+	return EC_SUCCESS;
+}
+
+static int cros_rtc_emul_reset_alarm(const struct device *dev)
+{
+	struct cros_rtc_emul_data *data = DRV_DATA(dev);
+
+	data->alarm_time = 0;
+
+	return EC_SUCCESS;
+}
+
+static int cros_rtc_emul_set_alarm(const struct device *dev, uint32_t seconds,
+				   uint32_t microseconds)
+{
+	struct cros_rtc_emul_data *data = DRV_DATA(dev);
+	int ret;
+
+	ARG_UNUSED(microseconds);
+
+	ret = cros_rtc_emul_reset_alarm(dev);
+
+	if (ret < 0) {
+		return ret;
+	}
+
+	data->alarm_time = seconds;
+
+	if (ret < 0) {
+		return ret;
+	}
+
+	return EC_SUCCESS;
+}
+
+static const struct cros_rtc_driver_api emul_cros_rtc_driver_api = {
+	.configure = cros_rtc_emul_configure,
+	.get_value = cros_rtc_emul_get_value,
+	.set_value = cros_rtc_emul_set_value,
+	.get_alarm = cros_rtc_emul_get_alarm,
+	.set_alarm = cros_rtc_emul_set_alarm,
+	.reset_alarm = cros_rtc_emul_reset_alarm,
+};
+
+static int rtc_emul_init(const struct device *dev)
+{
+	struct cros_rtc_emul_data *data = DRV_DATA(dev);
+
+	data->alarm_callback = NULL;
+	data->alarm_time = 0;
+	data->value = 0;
+
+	return EC_SUCCESS;
+}
+
+#define RTC_EMUL(n)                                                            \
+	static struct cros_rtc_emul_data cros_rtc_emul_data_##n = {};          \
+	static const struct rtc_emul_cfg rtc_emul_cfg_##n = {                  \
+		.data = &cros_rtc_emul_data_##n,                               \
+	};                                                                     \
+	DEVICE_DT_INST_DEFINE(n, rtc_emul_init, NULL, &cros_rtc_emul_data_##n, \
+			      &rtc_emul_cfg_##n, PRE_KERNEL_1,                 \
+			      CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,             \
+			      &emul_cros_rtc_driver_api)
+DT_INST_FOREACH_STATUS_OKAY(RTC_EMUL);
diff --git a/zephyr/emul/emul_sm5803.c b/zephyr/emul/emul_sm5803.c
new file mode 100644
index 0000000000..967a6a2ddd
--- /dev/null
+++ b/zephyr/emul/emul_sm5803.c
@@ -0,0 +1,988 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "driver/charger/sm5803.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_sm5803.h"
+#include "emul/emul_stub_device.h"
+
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/ztest.h>
+
+#define DT_DRV_COMPAT cros_sm5803_emul
+
+LOG_MODULE_REGISTER(sm5803_emul, CONFIG_SM5803_EMUL_LOG_LEVEL);
+
+#define VBUS_GPADC_LSB_MV 23.4
+#define ADC_CURRENT_LSB_MA 7.32
+#define ICL_LSB_MA 100
+#define CHG_DET_THRESHOLD_MV 4000
+
+struct sm5803_emul_data {
+	struct i2c_common_emul_data i2c_main;
+	struct i2c_common_emul_data i2c_chg;
+	struct i2c_common_emul_data i2c_meas;
+	struct i2c_common_emul_data i2c_test;
+
+	/** Device ID register value */
+	uint8_t device_id;
+	/** PLATFORM register value */
+	uint8_t pmode;
+	/** Raw value of ISO_CL_REG1 */
+	uint8_t input_current_limit;
+	uint8_t gpadc_conf1, gpadc_conf2;
+	/** Raw values of INT_EN{1..4} */
+	uint8_t int_en[4];
+	/** Raw values of INT_REQ_{1..4} */
+	uint8_t irq1, irq2, irq3, irq4;
+	uint16_t vbus;
+	uint16_t ibus;
+	uint16_t ibat_avg;
+	bool clock_slowed;
+	/** Measured VSYS voltage */
+	uint16_t vsys;
+	uint8_t cc_conf1;
+	/** Raw values of FLOW_REG* */
+	uint8_t flow1, flow2, flow3;
+	/** Raw value of SWITCHER_CONF register */
+	uint8_t switcher_conf;
+	/** Bit 0 (PSYS_DAC_EN) of PSYS_REG1 */
+	bool psys_dac_enabled;
+	/** PHOT_REG1 raw value. */
+	uint8_t phot1;
+	/** Raw values of DISCH_CONF_REG* */
+	uint8_t disch_conf1, disch_conf2, disch_conf5, disch_conf6;
+	/** Raw values of PRE_FAST_CONF_REG{1..6} */
+	uint8_t pre_fast_conf[6];
+	/** Raw value of GPIO0_CTRL register */
+	uint8_t gpio_ctrl;
+	/** Raw values of IR_COMP_REG1 and 2 */
+	uint8_t ir_comp1, ir_comp2;
+	/** Raw value of CHG_MON register */
+	uint8_t chg_mon;
+	/** Raw value of ANA_EN_REG1 register */
+	uint8_t ana_en1;
+	/** Raw value of STATUS_CHG register */
+	uint8_t chg_status;
+	/** Raw value of STATUS_DISCH register */
+	uint8_t disch_status;
+	/** Raw value of PORTS_CTRL register */
+	uint8_t ports_ctrl;
+	/** Raw value of REFERENCE1 register (REG_REFERENCE) */
+	uint8_t reference1;
+	/** Raw value of LOG_REG1 register (REG_LOG1) */
+	uint8_t log1;
+	/** Raw values of PREREG_CONF_REG{1,2} (REG_VSYS_PREREG_{M,L}LB) */
+	uint8_t prereg_conf1, prereg_conf2;
+	/** Voltage to report on the VBAT_SNSP pin, in mV */
+	uint16_t vbat_sns_mv;
+	/** Raw values of thermal threshold registers (TINT_{HIGH,LOW}_TH) */
+	uint8_t tint_high_th, tint_low_th;
+	/** Charger's reported internal temperature, in kelvin. */
+	uint16_t internal_temp_kelvin;
+};
+
+struct sm5803_emul_cfg {
+	const struct i2c_common_emul_cfg i2c_main;
+	const struct i2c_common_emul_cfg i2c_chg;
+	const struct i2c_common_emul_cfg i2c_meas;
+	const struct i2c_common_emul_cfg i2c_test;
+	const struct gpio_dt_spec *interrupt_gpio;
+};
+
+#define SIMPLE_GETTER(func_name, field_name)                         \
+	uint8_t sm5803_emul_get_##func_name(const struct emul *emul) \
+	{                                                            \
+		const struct sm5803_emul_data *data = emul->data;    \
+		return data->field_name;                             \
+	}
+
+const struct gpio_dt_spec *
+sm5803_emul_get_interrupt_gpio(const struct emul *emul)
+{
+	const struct sm5803_emul_cfg *cfg = emul->cfg;
+
+	return cfg->interrupt_gpio;
+}
+
+struct i2c_common_emul_data *sm5803_emul_get_i2c_main(const struct emul *emul)
+{
+	struct sm5803_emul_data *data = emul->data;
+
+	return &data->i2c_main;
+}
+
+struct i2c_common_emul_data *sm5803_emul_get_i2c_chg(const struct emul *emul)
+{
+	struct sm5803_emul_data *data = emul->data;
+
+	return &data->i2c_chg;
+}
+
+struct i2c_common_emul_data *sm5803_emul_get_i2c_meas(const struct emul *emul)
+{
+	struct sm5803_emul_data *data = emul->data;
+
+	return &data->i2c_meas;
+}
+
+struct i2c_common_emul_data *sm5803_emul_get_i2c_test(const struct emul *emul)
+{
+	struct sm5803_emul_data *data = emul->data;
+
+	return &data->i2c_test;
+}
+
+int sm5803_emul_read_chg_reg(const struct emul *emul, uint8_t reg)
+{
+	struct sm5803_emul_data *data = emul->data;
+
+	switch (reg) {
+	case SM5803_REG_CHG_ILIM:
+		return data->input_current_limit;
+	}
+	return -ENOTSUP;
+}
+
+int sm5803_emul_get_fast_charge_current_limit(const struct emul *emul)
+{
+	struct sm5803_emul_data *data = emul->data;
+
+	return data->pre_fast_conf[3] & GENMASK(5, 0);
+}
+
+void sm5803_emul_set_vbus_voltage(const struct emul *emul, uint16_t mv)
+{
+	struct sm5803_emul_data *data = emul->data;
+	uint16_t old = (float)data->vbus * VBUS_GPADC_LSB_MV;
+
+	data->vbus = (uint16_t)((float)mv / VBUS_GPADC_LSB_MV);
+
+	if (MIN(mv, old) <= CHG_DET_THRESHOLD_MV &&
+	    MAX(mv, old) > CHG_DET_THRESHOLD_MV) {
+		/* CHG_DET changes state; trigger an interrupt. */
+		sm5803_emul_set_irqs(emul, SM5803_INT1_CHG, 0, 0, 0);
+	}
+}
+
+void sm5803_emul_set_input_current(const struct emul *emul, uint16_t mv)
+{
+	struct sm5803_emul_data *data = emul->data;
+
+	data->ibus = (uint16_t)((float)mv / ADC_CURRENT_LSB_MA);
+}
+
+void sm5803_emul_set_battery_current(const struct emul *emul, uint16_t ma)
+{
+	struct sm5803_emul_data *data = emul->data;
+
+	data->ibat_avg = (uint16_t)((float)ma / ADC_CURRENT_LSB_MA);
+}
+
+static void update_interrupt_pin(const struct emul *emul)
+{
+	struct sm5803_emul_data *data = emul->data;
+	const struct sm5803_emul_cfg *cfg = emul->cfg;
+
+	bool pending = data->irq1 || data->irq2 || data->irq3 || data->irq4;
+
+	/* Pin goes low if any IRQ is pending. */
+	if (cfg->interrupt_gpio != NULL) {
+		gpio_emul_input_set(cfg->interrupt_gpio->port,
+				    cfg->interrupt_gpio->pin, !pending);
+	}
+}
+
+void sm5803_emul_set_irqs(const struct emul *emul, uint8_t irq1, uint8_t irq2,
+			  uint8_t irq3, uint8_t irq4)
+{
+	struct sm5803_emul_data *data = emul->data;
+
+	data->irq1 |= irq1;
+	data->irq2 |= irq2;
+	data->irq3 |= irq3;
+	data->irq4 |= irq4;
+	update_interrupt_pin(emul);
+}
+
+static bool is_chg_det(struct sm5803_emul_data *data)
+{
+	/* Assume charger presence is cut off at 4V VBUS. */
+	return data->vbus * VBUS_GPADC_LSB_MV > CHG_DET_THRESHOLD_MV;
+}
+
+void sm5803_emul_set_gpadc_conf(const struct emul *emul, uint8_t conf1,
+				uint8_t conf2)
+{
+	struct sm5803_emul_data *data = emul->data;
+
+	data->gpadc_conf1 = conf1;
+	data->gpadc_conf2 = conf2;
+}
+
+void sm5803_emul_get_gpadc_conf(const struct emul *emul, uint8_t *conf1,
+				uint8_t *conf2)
+{
+	struct sm5803_emul_data *data = emul->data;
+
+	*conf1 = data->gpadc_conf1;
+	*conf2 = data->gpadc_conf2;
+}
+
+bool sm5803_emul_is_clock_slowed(const struct emul *emul)
+{
+	struct sm5803_emul_data *data = emul->data;
+
+	return data->clock_slowed;
+}
+
+SIMPLE_GETTER(cc_config, cc_conf1)
+
+void sm5803_emul_get_flow_regs(const struct emul *emul, uint8_t *flow1,
+			       uint8_t *flow2, uint8_t *flow3)
+{
+	struct sm5803_emul_data *data = emul->data;
+
+	if (flow1 != NULL) {
+		*flow1 = data->flow1;
+	}
+	if (flow2 != NULL) {
+		*flow2 = data->flow2;
+	}
+	if (flow3 != NULL) {
+		*flow3 = data->flow3;
+	}
+}
+
+void sm5803_emul_set_pmode(const struct emul *emul, uint8_t pmode)
+{
+	struct sm5803_emul_data *data = emul->data;
+
+	data->pmode = pmode & GENMASK(4, 0);
+}
+
+void sm5803_emul_set_device_id(const struct emul *emul, uint8_t id)
+{
+	struct sm5803_emul_data *data = emul->data;
+
+	data->device_id = id;
+}
+
+SIMPLE_GETTER(gpio_ctrl, gpio_ctrl)
+
+uint16_t sm5803_emul_get_ir_comp(const struct emul *emul)
+{
+	struct sm5803_emul_data *data = emul->data;
+
+	return (data->ir_comp1 << 8) | data->ir_comp2;
+}
+
+SIMPLE_GETTER(chg_mon, chg_mon)
+SIMPLE_GETTER(ana_en1, ana_en1)
+SIMPLE_GETTER(disch_conf1, disch_conf1)
+SIMPLE_GETTER(disch_conf2, disch_conf2)
+SIMPLE_GETTER(disch_conf5, disch_conf5)
+SIMPLE_GETTER(disch_conf6, disch_conf6)
+
+SIMPLE_GETTER(chg_status, chg_status)
+
+void sm5803_emul_set_chg_status(const struct emul *emul, uint8_t value)
+{
+	struct sm5803_emul_data *data = emul->data;
+
+	data->chg_status = value;
+}
+
+SIMPLE_GETTER(disch_status, disch_status)
+
+void sm5803_emul_set_disch_status(const struct emul *emul, uint8_t value)
+{
+	struct sm5803_emul_data *data = emul->data;
+
+	data->disch_status = value;
+}
+
+SIMPLE_GETTER(ports_ctrl, ports_ctrl)
+SIMPLE_GETTER(reference_reg, reference1)
+SIMPLE_GETTER(log1, log1)
+
+bool sm5803_emul_is_psys_dac_enabled(const struct emul *emul)
+{
+	struct sm5803_emul_data *data = emul->data;
+
+	return data->psys_dac_enabled;
+}
+
+SIMPLE_GETTER(phot1, phot1)
+
+void sm5803_emul_set_vbat_sns_mv(const struct emul *emul, uint16_t mv)
+{
+	struct sm5803_emul_data *data = emul->data;
+
+	data->vbat_sns_mv = mv;
+}
+
+uint16_t sm5803_emul_vbat_snsp_regval(const struct emul *emul, uint16_t mv)
+{
+	struct sm5803_emul_data *data = emul->data;
+	double divisor;
+
+	/* Volts per ADC LSb varies with number of battery cells. */
+	if (data->pmode <= 5) { /* 1S */
+		divisor = 5.13;
+	} else if (data->pmode >= 6 && data->pmode <= 0xd) { /* 2S */
+		divisor = 10.2;
+	} else if (data->pmode >= 0xe && data->pmode <= 0x16) { /* 3S */
+		divisor = 15.38;
+	} else { /* 4S */
+		divisor = 20.51;
+	}
+
+	return mv / divisor;
+}
+
+void sm5803_emul_set_internal_temperature(const struct emul *emul,
+					  uint16_t kelvin)
+{
+	struct sm5803_emul_data *data = emul->data;
+
+	data->internal_temp_kelvin = MIN(kelvin, 440);
+}
+
+SIMPLE_GETTER(tint_high_th, tint_high_th);
+SIMPLE_GETTER(tint_low_th, tint_low_th);
+
+void sm5803_emul_set_vsys_measured_mv(const struct emul *emul, uint16_t mv)
+{
+	struct sm5803_emul_data *data = emul->data;
+
+	data->vsys = mv;
+}
+
+static void sm5803_emul_reset(const struct emul *emul)
+{
+	struct sm5803_emul_data *data = emul->data;
+	const struct sm5803_emul_cfg *cfg = emul->cfg;
+
+#define RESET_I2C(page)                                                  \
+	do {                                                             \
+		struct i2c_common_emul_data *common = &data->i2c_##page; \
+                                                                         \
+		i2c_common_emul_set_read_func(common, NULL, NULL);       \
+		i2c_common_emul_set_write_func(common, NULL, NULL);      \
+		i2c_common_emul_set_read_fail_reg(                       \
+			common, I2C_COMMON_EMUL_NO_FAIL_REG);            \
+		i2c_common_emul_set_write_fail_reg(                      \
+			common, I2C_COMMON_EMUL_NO_FAIL_REG);            \
+	} while (0)
+
+	RESET_I2C(main);
+	RESET_I2C(chg);
+	RESET_I2C(meas);
+	RESET_I2C(test);
+
+	/* Registers set to chip reset values */
+	data->device_id = 3;
+	data->pmode = 0x0b;
+	data->input_current_limit = 4;
+	data->gpadc_conf1 = 0xf3;
+	data->gpadc_conf2 = 0x01;
+	memset(data->int_en, 0, sizeof(data->int_en));
+	data->irq1 = data->irq2 = data->irq3 = data->irq4 = 0;
+	data->vbus = 0;
+	data->ibus = 0;
+	data->ibat_avg = 0;
+	data->clock_slowed = false;
+	data->vsys = 0;
+	data->cc_conf1 = 0x09;
+	data->flow1 = 0x01;
+	data->flow2 = 0;
+	data->flow3 = 0;
+	data->switcher_conf = 1;
+	data->psys_dac_enabled = true;
+	data->phot1 = 0x20;
+	data->disch_conf5 = 0;
+	data->disch_conf6 = 0;
+	memset(data->pre_fast_conf, 0, sizeof(data->pre_fast_conf));
+	data->gpio_ctrl = 0x04;
+	data->ir_comp1 = 1;
+	data->ir_comp2 = 1;
+	data->chg_mon = 0;
+	data->ana_en1 = 0x99;
+	data->disch_status = 0;
+	data->reference1 = 0;
+	data->log1 = 0;
+	data->prereg_conf1 = 0;
+	data->prereg_conf2 = 0;
+	data->vbat_sns_mv = 0;
+	data->tint_high_th = 0;
+	data->tint_low_th = 0;
+	data->internal_temp_kelvin = 296;
+
+	/* Interrupt pin deasserted */
+	if (cfg->interrupt_gpio != NULL) {
+		gpio_emul_input_set(cfg->interrupt_gpio->port,
+				    cfg->interrupt_gpio->pin, 1);
+	}
+}
+
+static int sm5803_main_read_byte(const struct emul *target, int reg,
+				 uint8_t *val, int bytes)
+{
+	struct sm5803_emul_data *data = target->data;
+
+	switch (reg) {
+	case SM5803_REG_CHIP_ID:
+		*val = data->device_id;
+		return 0;
+	case SM5803_REG_STATUS1:
+		*val = is_chg_det(data) ? SM5803_STATUS1_CHG_DET : 0;
+		return 0;
+	case SM5803_REG_INT1_REQ:
+		*val = data->irq1;
+		/* register clears on read */
+		data->irq1 = 0;
+		update_interrupt_pin(target);
+		return 0;
+	case SM5803_REG_INT2_REQ:
+		*val = data->irq2;
+		/* register clears on read */
+		data->irq2 = 0;
+		update_interrupt_pin(target);
+		return 0;
+	case SM5803_REG_INT3_REQ:
+		*val = data->irq3;
+		/* register clears on read */
+		data->irq3 = 0;
+		update_interrupt_pin(target);
+		return 0;
+	case SM5803_REG_INT4_REQ:
+		*val = data->irq4;
+		/* register clears on read */
+		data->irq4 = 0;
+		update_interrupt_pin(target);
+		return 0;
+	case SM5803_REG_INT1_EN:
+	case SM5803_REG_INT2_EN:
+	case SM5803_REG_INT3_EN:
+	case SM5803_REG_INT4_EN:
+		*val = data->int_en[reg - SM5803_REG_INT1_EN];
+		return 0;
+	case SM5803_REG_PLATFORM:
+		*val = data->pmode;
+		return 0;
+	case SM5803_REG_REFERENCE:
+		/* Driver never actually uses LDO PGOOD bits. */
+		*val = 0;
+		return 0;
+	case SM5803_REG_CLOCK_SEL:
+		*val = data->clock_slowed ? 1 : 0;
+		return 0;
+	case SM5803_REG_GPIO0_CTRL:
+		*val = data->gpio_ctrl;
+		return 0;
+	case SM5803_REG_PORTS_CTRL:
+		*val = data->ports_ctrl;
+		return 0;
+	}
+	LOG_INF("SM5803 main page read of register %#x unhandled", reg);
+	return -ENOTSUP;
+}
+
+static int sm5803_main_write_byte(const struct emul *target, int reg,
+				  uint8_t val, int bytes)
+{
+	struct sm5803_emul_data *data = target->data;
+
+	switch (reg) {
+	case 0x1f: /* Mystery register used for linear charge enable. */
+		return 0;
+	case SM5803_REG_REFERENCE:
+		data->reference1 = val & GENMASK(3, 0);
+		return 0;
+	case SM5803_REG_CLOCK_SEL:
+		data->clock_slowed = (val & 1) == 1;
+		return 0;
+	case SM5803_REG_GPIO0_CTRL:
+		data->gpio_ctrl = val & (GENMASK(7, 6) | GENMASK(2, 0));
+		return 0;
+	case SM5803_REG_PORTS_CTRL:
+		/* Bits 4-7 always read 0 */
+		data->ports_ctrl = val & GENMASK(3, 0);
+		return 0;
+	}
+	LOG_INF("SM5803 main page write of register %#x unhandled", reg);
+	return -ENOTSUP;
+}
+
+static int sm5803_chg_read_byte(const struct emul *target, int reg,
+				uint8_t *val, int bytes)
+{
+	struct sm5803_emul_data *data = target->data;
+
+	switch (reg) {
+	case SM5803_REG_CC_CONFIG1:
+		*val = data->cc_conf1;
+		return 0;
+	case SM5803_REG_INT1_EN:
+	case SM5803_REG_INT2_EN:
+	case SM5803_REG_INT3_EN:
+	case SM5803_REG_INT4_EN:
+		*val = data->int_en[reg - SM5803_REG_INT1_EN];
+		return 0;
+	case SM5803_REG_FLOW1:
+		*val = data->flow1;
+		return 0;
+	case SM5803_REG_FLOW2:
+		*val = data->flow2;
+		return 0;
+	case SM5803_REG_FLOW3:
+		*val = data->flow3;
+		return 0;
+	case SM5803_REG_SWITCHER_CONF:
+		*val = data->switcher_conf;
+		return 0;
+	case SM5803_REG_ANA_EN1:
+		*val = data->ana_en1;
+		return 0;
+	case SM5803_REG_CHG_ILIM:
+		*val = data->input_current_limit;
+		return 0;
+	case SM5803_REG_VPWR_MSB:
+		*val = data->disch_conf1;
+		return 0;
+	case SM5803_REG_DISCH_CONF2:
+		*val = data->disch_conf2;
+		return 0;
+	case SM5803_REG_DISCH_CONF5:
+		*val = data->disch_conf5;
+		return 0;
+	case SM5803_REG_DISCH_CONF6:
+		*val = data->disch_conf6;
+		return 0;
+	case SM5803_REG_PRE_FAST_CONF_REG1:
+	case SM5803_REG_PRE_FAST_CONF_REG1 + 1: /* VBAT_FAST_MSB */
+	case SM5803_REG_PRE_FAST_CONF_REG1 + 2: /* VBAT_FAST_LSB */
+	case SM5803_REG_PRE_FAST_CONF_REG1 + 3: /* FAST_CONF4 */
+	case SM5803_REG_PRE_FAST_CONF_REG1 + 4: /* FAST_CONF5 */
+	case SM5803_REG_PRE_FAST_CONF_REG1 + 5:
+		*val = data->pre_fast_conf[reg - SM5803_REG_PRE_FAST_CONF_REG1];
+		return 0;
+	case SM5803_REG_IR_COMP1:
+		*val = data->ir_comp1;
+		return 0;
+	case SM5803_REG_IR_COMP2:
+		*val = data->ir_comp2;
+		return 0;
+	case SM5803_REG_LOG1:
+		*val = data->log1;
+		return 0;
+	case SM5803_REG_LOG2:
+		*val = ((data->ibus * ADC_CURRENT_LSB_MA) >
+			(data->input_current_limit * ICL_LSB_MA))
+		       << 1;
+		return 0;
+	case SM5803_REG_STATUS_CHG_REG:
+		*val = data->chg_status;
+		return 0;
+	case SM5803_REG_STATUS_DISCHG:
+		*val = data->disch_status;
+		return 0;
+	case SM5803_REG_CHG_MON_REG:
+		*val = data->chg_mon;
+		return 0;
+	case SM5803_REG_PHOT1:
+		*val = data->phot1;
+		return 0;
+	}
+	LOG_INF("SM5803 charger page read of register %#x unhandled", reg);
+	return -ENOTSUP;
+}
+
+static int sm5803_chg_write_byte(const struct emul *target, int reg,
+				 uint8_t val, int bytes)
+{
+	struct sm5803_emul_data *data = target->data;
+
+	switch (reg) {
+	case SM5803_REG_CC_CONFIG1:
+		data->cc_conf1 = val;
+		return 0;
+	case SM5803_REG_FLOW1:
+		data->flow1 = val & 0x8f;
+		/* Enabling linear charge turns on the BATFET. */
+		if (val & SM5803_FLOW1_LINEAR_CHARGE_EN) {
+			data->log1 |= SM5803_BATFET_ON;
+		}
+		return 0;
+	case SM5803_REG_FLOW2:
+		data->flow2 = val;
+		return 0;
+	case SM5803_REG_FLOW3:
+		data->flow3 = val & GENMASK(6, 0);
+		return 0;
+	case SM5803_REG_SWITCHER_CONF:
+		data->switcher_conf = val & 0xc1;
+		return 0;
+	case SM5803_REG_ANA_EN1:
+		data->ana_en1 = val;
+		return 0;
+	case SM5803_REG_CHG_ILIM:
+		data->input_current_limit = val & GENMASK(4, 0);
+		return 0;
+	case SM5803_REG_VPWR_MSB:
+		data->disch_conf1 = val;
+		return 0;
+	case SM5803_REG_DISCH_CONF2:
+		data->disch_conf2 = val;
+		return 0;
+	case SM5803_REG_DISCH_CONF5:
+		data->disch_conf5 = val;
+		return 0;
+	case SM5803_REG_DISCH_CONF6:
+		data->disch_conf6 = val;
+		return 0;
+	case SM5803_REG_VSYS_PREREG_MSB:
+		data->prereg_conf1 = val;
+		return 0;
+	case SM5803_REG_VSYS_PREREG_LSB:
+		data->prereg_conf2 = val;
+		return 0;
+	case SM5803_REG_PRE_FAST_CONF_REG1:
+	case SM5803_REG_PRE_FAST_CONF_REG1 + 1:
+	case SM5803_REG_PRE_FAST_CONF_REG1 + 2:
+	case SM5803_REG_PRE_FAST_CONF_REG1 + 3:
+	case SM5803_REG_PRE_FAST_CONF_REG1 + 4:
+	case SM5803_REG_PRE_FAST_CONF_REG1 + 5:
+		data->pre_fast_conf[reg - SM5803_REG_PRE_FAST_CONF_REG1] = val;
+		return 0;
+	case SM5803_REG_IR_COMP1:
+		data->ir_comp1 = val;
+		return 0;
+	case SM5803_REG_IR_COMP2:
+		data->ir_comp2 = val;
+		return 0;
+	case SM5803_REG_STATUS_CHG_REG:
+		/* Bits are cleared when written set */
+		data->chg_status &= ~val;
+		return 0;
+	case SM5803_REG_STATUS_DISCHG:
+		/* Bits are cleared when written set */
+		data->disch_status &= ~val;
+		return 0;
+	case SM5803_REG_PHOT1:
+		data->phot1 = val;
+		return 0;
+	case SM5803_REG_CHG_MON_REG:
+		data->chg_mon = val;
+		return 0;
+	}
+	LOG_INF("SM5803 charger page write of register %#x unhandled", reg);
+	return -ENOTSUP;
+}
+
+static int sm5803_meas_read_byte(const struct emul *target, int reg,
+				 uint8_t *val, int bytes)
+{
+	struct sm5803_emul_data *data = target->data;
+
+	switch (reg) {
+	case SM5803_REG_GPADC_CONFIG1:
+		*val = data->gpadc_conf1;
+		return 0;
+	case SM5803_REG_GPADC_CONFIG2:
+		*val = data->gpadc_conf2;
+		return 0;
+	case SM5803_REG_PSYS1:
+		*val = 0x04 | data->psys_dac_enabled;
+		return 0;
+	case SM5803_REG_VBATSNSP_MAX_TH:
+		/* Unimportant; tests don't care what this register reads. */
+		*val = 0;
+		return 0;
+	case SM5803_REG_TINT_HIGH_TH:
+		*val = data->tint_high_th;
+		return 0;
+	case SM5803_REG_TINT_LOW_TH:
+		*val = data->tint_low_th;
+		return 0;
+	case SM5803_REG_VBATSNSP_MEAS_MSB:
+		*val = (sm5803_emul_vbat_snsp_regval(target,
+						     data->vbat_sns_mv) &
+			GENMASK(9, 2)) >>
+		       2;
+		return 0;
+	case SM5803_REG_VBATSNSP_MEAS_LSB:
+		*val = sm5803_emul_vbat_snsp_regval(target, data->vbat_sns_mv) &
+		       GENMASK(1, 0);
+		return 0;
+	case SM5803_REG_IBUS_CHG_MEAS_MSB:
+		*val = (data->ibus & GENMASK(9, 2)) >> 2;
+		return 0;
+	case SM5803_REG_IBUS_CHG_MEAS_LSB:
+		*val = data->ibus & GENMASK(1, 0);
+		return 0;
+	case SM5803_REG_VBUS_MEAS_MSB:
+		*val = (data->vbus & GENMASK(9, 2)) >> 2;
+		return 0;
+	case SM5803_REG_VBUS_MEAS_LSB:
+		*val = (is_chg_det(data) ? SM5803_VBUS_MEAS_CHG_DET : 0) |
+		       (data->vbus & GENMASK(1, 0));
+		return 0;
+	case SM5803_REG_TINT_MEAS_MSB:
+		*val = (uint16_t)(data->internal_temp_kelvin / 0.43) >> 2;
+		return 0;
+		/* Driver doesn't use TINT_MEAS_LSB, so unimplemented. */
+	case SM5803_REG_IBAT_CHG_AVG_MEAS_MSB:
+		*val = (data->ibat_avg & GENMASK(9, 2)) >> 2;
+		return 0;
+	case SM5803_REG_IBAT_CHG_AVG_MEAS_LSB:
+		*val = data->ibat_avg & GENMASK(1, 0);
+		return 0;
+	case SM5803_REG_VSYS_AVG_MEAS_MSB:
+		/* 23.4 mV per LSb */
+		*val = (uint16_t)(data->vsys / 23.4) >> 2;
+		return 0;
+	case SM5803_REG_VSYS_AVG_MEAS_LSB:
+		*val = (uint16_t)(data->vsys / 23.4) & GENMASK(1, 0);
+		return 0;
+	}
+	LOG_INF("SM5803 meas page read of register %#x unhandled", reg);
+	return -ENOTSUP;
+}
+
+static int sm5803_meas_write_byte(const struct emul *target, int reg,
+				  uint8_t val, int bytes)
+{
+	struct sm5803_emul_data *data = target->data;
+
+	switch (reg) {
+	case SM5803_REG_PSYS1:
+		data->psys_dac_enabled = (val & 1) != 0;
+		return 0;
+	case SM5803_REG_GPADC_CONFIG1:
+		data->gpadc_conf1 = val;
+		return 0;
+	case SM5803_REG_GPADC_CONFIG2:
+		data->gpadc_conf2 = val;
+		return 0;
+	case SM5803_REG_TINT_HIGH_TH:
+		data->tint_high_th = val;
+		return 0;
+	case SM5803_REG_TINT_LOW_TH:
+		data->tint_low_th = val;
+		return 0;
+	}
+
+	LOG_INF("SM5803 meas page write of register %#x unhandled", reg);
+	return -ENOTSUP;
+}
+
+static int sm5803_test_read_byte(const struct emul *target, int reg,
+				 uint8_t *val, int bytes)
+{
+	switch (reg) {
+	case 0x8e: /* Mystery register used for init on chip ID 2 */
+		*val = 0;
+		return 0;
+	}
+	LOG_INF("SM5803 test page read of register %#x unhandled", reg);
+	return -ENOTSUP;
+}
+
+static int sm5803_test_write_byte(const struct emul *target, int reg,
+				  uint8_t val, int bytes)
+{
+	switch (reg) {
+	case 0x44: /* Mystery register used for linear charge enable. */
+		return 0;
+	case 0x8e: /* Mystery register used for init on chip ID 2 */
+		return 0;
+	}
+	LOG_INF("SM5803 test page write of register %#x unhandled", reg);
+	return -ENOTSUP;
+}
+
+static int sm5803_emul_i2c_transfer(const struct emul *target,
+				    struct i2c_msg *msgs, int num_msgs,
+				    int addr)
+{
+	struct sm5803_emul_data *data = target->data;
+	const struct sm5803_emul_cfg *cfg = target->cfg;
+
+	if (addr == cfg->i2c_main.addr) {
+		return i2c_common_emul_transfer_workhorse(target,
+							  &data->i2c_main,
+							  &cfg->i2c_main, msgs,
+							  num_msgs, addr);
+	} else if (addr == cfg->i2c_chg.addr) {
+		return i2c_common_emul_transfer_workhorse(target,
+							  &data->i2c_chg,
+							  &cfg->i2c_chg, msgs,
+							  num_msgs, addr);
+	} else if (addr == cfg->i2c_meas.addr) {
+		return i2c_common_emul_transfer_workhorse(target,
+							  &data->i2c_meas,
+							  &cfg->i2c_meas, msgs,
+							  num_msgs, addr);
+	} else if (addr == cfg->i2c_test.addr) {
+		return i2c_common_emul_transfer_workhorse(target,
+							  &data->i2c_test,
+							  &cfg->i2c_test, msgs,
+							  num_msgs, addr);
+	}
+	LOG_ERR("I2C transaction for address %#x not supported by SM5803",
+		addr);
+	return -ENOTSUP;
+}
+
+const static struct i2c_emul_api sm5803_emul_api = {
+	.transfer = sm5803_emul_i2c_transfer,
+};
+
+static int sm5803_emul_init(const struct emul *emul,
+			    const struct device *parent)
+{
+	struct sm5803_emul_data *data = emul->data;
+	struct i2c_common_emul_data *const i2c_pages[] = {
+		&data->i2c_chg,
+		&data->i2c_main,
+		&data->i2c_meas,
+		&data->i2c_test,
+	};
+
+	for (int i = 0; i < ARRAY_SIZE(i2c_pages); i++) {
+		int rv = i2c_emul_register(parent, &i2c_pages[i]->emul);
+
+		if (rv != 0) {
+			k_oops();
+		}
+		i2c_common_emul_init(i2c_pages[i]);
+	}
+
+	sm5803_emul_reset(emul);
+
+	return 0;
+}
+
+#define INST_HAS_IRQ(n) DT_INST_NODE_HAS_PROP(n, interrupt_gpios)
+
+#define INIT_SM5803(n)                                                           \
+	const static struct sm5803_emul_cfg sm5803_emul_cfg_##n;                 \
+	static struct sm5803_emul_data sm5803_emul_data_##n = {                \
+		.i2c_main = {						       \
+			.i2c = DEVICE_DT_GET(DT_INST_PARENT(n)),               \
+			.emul =                                                \
+				(struct i2c_emul){                             \
+					.target = EMUL_DT_GET(                 \
+						DT_DRV_INST(n)),               \
+					.api = &sm5803_emul_api,               \
+					.addr = DT_INST_PROP(                  \
+						n, main_addr),                 \
+				},                                             \
+			.cfg = &sm5803_emul_cfg_##n.i2c_main,                  \
+			.read_byte = &sm5803_main_read_byte,                   \
+			.write_byte = &sm5803_main_write_byte,                 \
+		},                                                             \
+		.i2c_chg = {						       \
+			.i2c = DEVICE_DT_GET(DT_INST_PARENT(n)),               \
+			.emul =                                                \
+				(struct i2c_emul){                             \
+					.target = EMUL_DT_GET(                 \
+						DT_DRV_INST(n)),               \
+					.api = &sm5803_emul_api,               \
+					.addr = DT_INST_REG_ADDR(n),           \
+				},                                             \
+			.cfg = &sm5803_emul_cfg_##n.i2c_chg,                   \
+			.read_byte = &sm5803_chg_read_byte,                    \
+			.write_byte = &sm5803_chg_write_byte,                  \
+		},                                                             \
+		.i2c_meas = {						       \
+			.i2c = DEVICE_DT_GET(DT_INST_PARENT(n)),               \
+			.emul =                                                \
+				(struct i2c_emul){                             \
+					.target = EMUL_DT_GET(                 \
+						DT_DRV_INST(n)),               \
+					.api = &sm5803_emul_api,               \
+					.addr = DT_INST_PROP(                  \
+						n, meas_addr),                 \
+				},                                             \
+			.cfg = &sm5803_emul_cfg_##n.i2c_meas,                  \
+			.read_byte = &sm5803_meas_read_byte,                   \
+			.write_byte = &sm5803_meas_write_byte,                 \
+		},                                                             \
+		.i2c_test = {						       \
+			.i2c = DEVICE_DT_GET(DT_INST_PARENT(n)),               \
+			.emul =                                                \
+				(struct i2c_emul){                             \
+					.target = EMUL_DT_GET(                 \
+						DT_DRV_INST(n)),               \
+					.api = &sm5803_emul_api,               \
+					.addr = DT_INST_PROP(                  \
+						n, test_addr),                 \
+				},                                             \
+			.cfg = &sm5803_emul_cfg_##n.i2c_test,                  \
+			.read_byte = &sm5803_test_read_byte,                   \
+			.write_byte = &sm5803_test_write_byte,                 \
+		},                                                             \
+	}; \
+	IF_ENABLED(INST_HAS_IRQ(n),                                              \
+		   (const static struct gpio_dt_spec sm5803_emul_irq_##n = {     \
+			    .port = DEVICE_DT_GET(DT_GPIO_CTLR(                  \
+				    DT_DRV_INST(n), interrupt_gpios)),           \
+			    .pin = DT_INST_GPIO_PIN(n, interrupt_gpios),         \
+			    .dt_flags = (gpio_dt_flags_t)DT_INST_GPIO_FLAGS(     \
+				    n, interrupt_gpios),                         \
+		    };))                                                         \
+	const static struct sm5803_emul_cfg sm5803_emul_cfg_##n = {              \
+		.i2c_main =                                                      \
+			(struct i2c_common_emul_cfg){                            \
+				.dev_label =                                     \
+					DT_NODE_FULL_NAME(DT_DRV_INST(n)),       \
+				.addr = DT_INST_PROP(n, main_addr),              \
+				.data = &sm5803_emul_data_##n.i2c_main,          \
+			},                                                       \
+		.i2c_chg =                                                       \
+			(struct i2c_common_emul_cfg){                            \
+				.dev_label =                                     \
+					DT_NODE_FULL_NAME(DT_DRV_INST(n)),       \
+				.addr = DT_INST_REG_ADDR(n),                     \
+				.data = &sm5803_emul_data_##n.i2c_chg,           \
+			},                                                       \
+		.i2c_meas =                                                      \
+			(struct i2c_common_emul_cfg){                            \
+				.dev_label =                                     \
+					DT_NODE_FULL_NAME(DT_DRV_INST(n)),       \
+				.addr = DT_INST_PROP(n, meas_addr),              \
+				.data = &sm5803_emul_data_##n.i2c_meas,          \
+			},                                                       \
+		.i2c_test =                                                      \
+			(struct i2c_common_emul_cfg){                            \
+				.dev_label =                                     \
+					DT_NODE_FULL_NAME(DT_DRV_INST(n)),       \
+				.addr = DT_INST_PROP(n, test_addr),              \
+				.data = &sm5803_emul_data_##n.i2c_test,          \
+			},                                                       \
+		.interrupt_gpio = COND_CODE_1(INST_HAS_IRQ(n),                   \
+					      (&sm5803_emul_irq_##n), (NULL)),   \
+	};                                                                       \
+	EMUL_DT_INST_DEFINE(n, sm5803_emul_init, &sm5803_emul_data_##n,          \
+			    &sm5803_emul_cfg_##n, &sm5803_emul_api, NULL);
+
+DT_INST_FOREACH_STATUS_OKAY(INIT_SM5803)
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE)
+
+static void sm5803_emul_reset_before(const struct ztest_unit_test *test,
+				     void *data)
+{
+	ARG_UNUSED(test);
+	ARG_UNUSED(data);
+
+#define SM5803_EMUL_RESET_RULE_BEFORE(n) \
+	sm5803_emul_reset(EMUL_DT_GET(DT_DRV_INST(n)));
+
+	DT_INST_FOREACH_STATUS_OKAY(SM5803_EMUL_RESET_RULE_BEFORE);
+}
+ZTEST_RULE(sm5803_emul_reset, sm5803_emul_reset_before, NULL);
diff --git a/zephyr/emul/emul_smart_battery.c b/zephyr/emul/emul_smart_battery.c
new file mode 100644
index 0000000000..13abc1c4db
--- /dev/null
+++ b/zephyr/emul/emul_smart_battery.c
@@ -0,0 +1,928 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery_smart.h"
+#include "crc8.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_smart_battery.h"
+#include "emul/emul_stub_device.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/i2c_emul.h>
+#include <zephyr/logging/log.h>
+
+#ifdef CONFIG_ZTEST
+#include <zephyr/ztest.h>
+#endif
+
+#define DT_DRV_COMPAT zephyr_smart_battery_emul
+
+#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
+LOG_MODULE_REGISTER(smart_battery);
+
+/** Run-time data used by the emulator */
+struct sbat_emul_data {
+	/** Common I2C data */
+	struct i2c_common_emul_data common;
+
+	/** Data required to simulate battery */
+	struct sbat_emul_bat_data bat;
+	/** Command that should be handled next */
+	int cur_cmd;
+	/** Message buffer which is used to handle smb transactions */
+	uint8_t msg_buf[MSG_BUF_LEN];
+	/** Total bytes that were generated in response to smb read operation */
+	int num_to_read;
+};
+
+/** Check description in emul_smart_battery.h */
+struct sbat_emul_bat_data *sbat_emul_get_bat_data(const struct emul *emul)
+{
+	struct sbat_emul_data *data;
+
+	data = emul->data;
+
+	return &data->bat;
+}
+
+/** Check description in emul_smart_battery.h */
+uint16_t sbat_emul_date_to_word(unsigned int day, unsigned int month,
+				unsigned int year)
+{
+	year -= MANUFACTURE_DATE_YEAR_OFFSET;
+	year <<= MANUFACTURE_DATE_YEAR_SHIFT;
+	year &= MANUFACTURE_DATE_YEAR_MASK;
+	month <<= MANUFACTURE_DATE_MONTH_SHIFT;
+	month &= MANUFACTURE_DATE_MONTH_MASK;
+	day <<= MANUFACTURE_DATE_DAY_SHIFT;
+	day &= MANUFACTURE_DATE_DAY_MASK;
+
+	return day | month | year;
+}
+
+/**
+ * @brief Compute CRC from the beginning of the message
+ *
+ * @param addr Smart battery address on SMBus
+ * @param read If message for which CRC is computed is read. For read message
+ *             byte command and repeated address is added to CRC
+ * @param cmd Command used in read message
+ *
+ * @return pec CRC from first bytes of message
+ */
+static uint8_t sbat_emul_pec_head(uint8_t addr, int read, uint8_t cmd)
+{
+	uint8_t pec;
+
+	addr <<= 1;
+
+	pec = cros_crc8(&addr, 1);
+	if (!read) {
+		return pec;
+	}
+
+	pec = cros_crc8_arg(&cmd, 1, pec);
+	addr |= I2C_MSG_READ;
+	pec = cros_crc8_arg(&addr, 1, pec);
+
+	return pec;
+}
+
+/**
+ * @brief Convert from 10mW power units to mA current under given mV voltage
+ *
+ * @param mw Power in 10mW units
+ * @param mv Voltage in mV units
+ *
+ * @return Current in mA units
+ */
+static uint16_t sbat_emul_10mw_to_ma(int mw, int mv)
+{
+	/* Smart battery use 10mW units, convert to mW */
+	mw *= 10;
+	/* Multiple by 1000 to get mA instead of A */
+	return 1000 * mw / mv;
+}
+
+/**
+ * @brief Convert from mA current to 10mW power under given mV voltage
+ *
+ * @param ma Current in mA units
+ * @param mv Voltage in mV units
+ *
+ * @return Power in 10mW units
+ */
+static uint16_t sbat_emul_ma_to_10mw(int ma, int mv)
+{
+	int mw;
+	/* Divide by 1000 to get mW instead of uW */
+	mw = ma * mv / 1000;
+	/* Smart battery use 10mW units, convert to 10mW */
+	return mw / 10;
+}
+
+/**
+ * @brief Get time in minutes how long it will take to get given amount of
+ *        charge at given current flow
+ *
+ * @param bat Pointer to battery data to set error code in case of
+ *            over/under flow in time calculation
+ * @param rate Rate of current in mAh
+ * @param cap Required amount of charge in mA
+ * @param time Pointer to memory where calculated time will be stored
+ *
+ * @return 0 on success
+ * @return -EINVAL when over or under flow occurred
+ */
+static int sbat_emul_get_time_to_complete(struct sbat_emul_bat_data *bat,
+					  int rate, int cap, uint16_t *ret_time)
+{
+	int time;
+
+	/* At negative rate process never ends, return maximum value */
+	if (rate <= 0) {
+		*ret_time = UINT16_MAX;
+
+		return 0;
+	}
+	/* Convert capacity from mAh to mAmin */
+	time = cap * 60 / rate;
+	/* Check overflow */
+	if (time >= UINT16_MAX) {
+		*ret_time = UINT16_MAX;
+		bat->error_code = STATUS_CODE_OVERUNDERFLOW;
+
+		return -EINVAL;
+	}
+	/* Check underflow */
+	if (time < 0) {
+		*ret_time = 0;
+		bat->error_code = STATUS_CODE_OVERUNDERFLOW;
+
+		return -EINVAL;
+	}
+
+	*ret_time = time;
+
+	return 0;
+}
+
+/**
+ * @brief Get time in minutes how long it will take to charge battery
+ *
+ * @param bat Pointer to battery data
+ * @param rate Rate of charging current in mAh
+ * @param time Pointer to memory where calculated time will be stored
+ *
+ * @return 0 on success
+ * @return -EINVAL when over or under flow occurred
+ */
+static int sbat_emul_time_to_full(struct sbat_emul_bat_data *bat, int rate,
+				  uint16_t *time)
+{
+	int cap;
+
+	cap = bat->full_cap - bat->cap;
+	return sbat_emul_get_time_to_complete(bat, rate, cap, time);
+}
+
+/**
+ * @brief Get time in minutes how long it will take to discharge battery. Note,
+ *        that rate should be negative to indicate discharging.
+ *
+ * @param bat Pointer to battery data
+ * @param rate Rate of charging current in mAh
+ * @param time Pointer to memory where calculated time will be stored
+ *
+ * @return 0 on success
+ * @return -EINVAL when over or under flow occurred
+ */
+static int sbat_emul_time_to_empty(struct sbat_emul_bat_data *bat, int rate,
+				   uint16_t *time)
+{
+	int cap;
+
+	/* Reverse to have discharging rate instead of charging rate */
+	rate = -rate;
+	cap = bat->cap;
+	return sbat_emul_get_time_to_complete(bat, rate, cap, time);
+}
+
+/**
+ * @brief Check if battery can supply for 10 seconds additional power/current
+ *        set in at_rate register.
+ *
+ * @param bat Pointer to battery data
+ * @param rate Rate of charging current in mAh
+ * @param ok Pointer to memory where 0 is written if battery is able to supply
+ *           additional power/curent or 1 is written if battery is unable
+ *           to do so.
+ *
+ * @return 0 on success
+ */
+static int sbat_emul_read_at_rate_ok(struct sbat_emul_bat_data *bat,
+				     uint16_t *ok)
+{
+	int rem_time_s;
+	int rate;
+
+	rate = bat->at_rate;
+	if (bat->mode & MODE_CAPACITY) {
+		rate = sbat_emul_10mw_to_ma(rate, bat->design_mv);
+	}
+
+	/* Add current battery usage */
+	rate += bat->cur;
+	if (rate >= 0) {
+		/* Battery will be charged */
+		*ok = 1;
+
+		return 0;
+	}
+	/* Reverse to have discharging rate instead of charging rate */
+	rate = -rate;
+
+	rem_time_s = bat->cap * 3600 / rate;
+	if (rem_time_s > 10) {
+		/*
+		 * Battery can support 10 seconds of additional at_rate
+		 * current/power
+		 */
+		*ok = 1;
+	} else {
+		*ok = 0;
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Get battery status. This function use emulated status register and
+ *        set or clear some of the flags based on other properties of emulated
+ *        smart battery. Discharge bit, capacity alarm, time alarm, fully
+ *        discharged bit and error code are controlled by battery properties.
+ *        Terminate charge/discharge/overcharge alarms are set only if they are
+ *        set in emulated status register and battery is charging/discharging,
+ *        so they are partialy controlled by emulated status register.
+ *        Other bits are controlled by emulated status register
+ *
+ * @param emul Pointer to smart battery emulator
+ *
+ * @return value which equals to computed status register
+ */
+static uint16_t sbat_emul_read_status(const struct emul *emul)
+{
+	uint16_t status, cap, rem_time, charge_percent;
+	struct sbat_emul_bat_data *bat;
+
+	bat = sbat_emul_get_bat_data(emul);
+
+	status = bat->status;
+
+	/*
+	 * Over charged and terminate charger alarm cannot appear when battery
+	 * is not charged
+	 */
+	if (bat->cur <= 0) {
+		status &= ~(STATUS_TERMINATE_CHARGE_ALARM |
+			    STATUS_OVERCHARGED_ALARM);
+		status |= STATUS_DISCHARGING;
+	}
+	/* Terminate discharge alarm cannot appear when battery is charged */
+	if (bat->cur >= 0) {
+		status &= ~(STATUS_TERMINATE_DISCHARGE_ALARM |
+			    STATUS_DISCHARGING);
+	}
+
+	sbat_emul_get_word_val(emul, SB_REMAINING_CAPACITY, &cap);
+	if (bat->cap_alarm && cap < bat->cap_alarm) {
+		status |= STATUS_REMAINING_CAPACITY_ALARM;
+	} else {
+		status &= ~STATUS_REMAINING_CAPACITY_ALARM;
+	}
+
+	sbat_emul_get_word_val(emul, SB_AVERAGE_TIME_TO_EMPTY, &rem_time);
+	if (bat->time_alarm && rem_time < bat->time_alarm) {
+		status |= STATUS_REMAINING_TIME_ALARM;
+	} else {
+		status &= ~STATUS_REMAINING_TIME_ALARM;
+	}
+
+	/* Unset fully discharged bit when charge is grater than 20% */
+	sbat_emul_get_word_val(emul, SB_RELATIVE_STATE_OF_CHARGE,
+			       &charge_percent);
+	if (charge_percent > 20) {
+		status &= ~STATUS_FULLY_DISCHARGED;
+	} else {
+		status |= STATUS_FULLY_DISCHARGED;
+	}
+
+	status |= bat->error_code & STATUS_ERR_CODE_MASK;
+
+	return status;
+}
+
+/** Check description in emul_smart_battery.h */
+int sbat_emul_get_word_val(const struct emul *emul, int cmd, uint16_t *val)
+{
+	struct sbat_emul_bat_data *bat;
+	int mode_mw;
+	int rate;
+
+	bat = sbat_emul_get_bat_data(emul);
+	mode_mw = bat->mode & MODE_CAPACITY;
+
+	switch (cmd) {
+	case SB_MANUFACTURER_ACCESS:
+		*val = bat->mf_access;
+		return 0;
+	case SB_REMAINING_CAPACITY_ALARM:
+		*val = bat->cap_alarm;
+		return 0;
+	case SB_REMAINING_TIME_ALARM:
+		*val = bat->time_alarm;
+		return 0;
+	case SB_BATTERY_MODE:
+		*val = bat->mode;
+		return 0;
+	case SB_AT_RATE:
+		*val = bat->at_rate;
+		return 0;
+	case SB_AT_RATE_TIME_TO_FULL:
+		/* Support for reporting time to full in mW mode is optional */
+		if (mode_mw && !bat->at_rate_full_mw_support) {
+			bat->error_code = STATUS_CODE_OVERUNDERFLOW;
+			*val = UINT16_MAX;
+
+			return -EINVAL;
+		}
+
+		rate = bat->at_rate;
+		if (mode_mw) {
+			rate = sbat_emul_10mw_to_ma(rate, bat->design_mv);
+		}
+		return sbat_emul_time_to_full(bat, rate, val);
+
+	case SB_AT_RATE_TIME_TO_EMPTY:
+		rate = bat->at_rate;
+		if (mode_mw) {
+			rate = sbat_emul_10mw_to_ma(rate, bat->design_mv);
+		}
+		return sbat_emul_time_to_empty(bat, rate, val);
+
+	case SB_AT_RATE_OK:
+		return sbat_emul_read_at_rate_ok(bat, val);
+	case SB_TEMPERATURE:
+		*val = bat->temp;
+		return 0;
+	case SB_VOLTAGE:
+		*val = bat->volt;
+		return 0;
+	case SB_CURRENT:
+		*val = bat->cur;
+		return 0;
+	case SB_AVERAGE_CURRENT:
+		*val = bat->avg_cur;
+		return 0;
+	case SB_MAX_ERROR:
+		*val = bat->max_error;
+		return 0;
+	case SB_RELATIVE_STATE_OF_CHARGE:
+		/* Percent of charge according to full capacity */
+		*val = 100 * bat->cap / bat->full_cap;
+		return 0;
+	case SB_ABSOLUTE_STATE_OF_CHARGE:
+		/* Percent of charge according to design capacity */
+		*val = 100 * bat->cap / bat->design_cap;
+		return 0;
+	case SB_REMAINING_CAPACITY:
+		if (mode_mw) {
+			*val = sbat_emul_ma_to_10mw(bat->cap, bat->design_mv);
+		} else {
+			*val = bat->cap;
+		}
+		return 0;
+	case SB_FULL_CHARGE_CAPACITY:
+		if (mode_mw) {
+			*val = sbat_emul_ma_to_10mw(bat->full_cap,
+						    bat->design_mv);
+		} else {
+			*val = bat->full_cap;
+		}
+		return 0;
+	case SB_RUN_TIME_TO_EMPTY:
+		rate = bat->cur;
+		return sbat_emul_time_to_empty(bat, rate, val);
+	case SB_AVERAGE_TIME_TO_EMPTY:
+		rate = bat->avg_cur;
+		return sbat_emul_time_to_empty(bat, rate, val);
+	case SB_AVERAGE_TIME_TO_FULL:
+		rate = bat->avg_cur;
+		return sbat_emul_time_to_full(bat, rate, val);
+	case SB_CHARGING_CURRENT:
+		*val = bat->desired_charg_cur;
+		return 0;
+	case SB_CHARGING_VOLTAGE:
+		*val = bat->desired_charg_volt;
+		return 0;
+	case SB_BATTERY_STATUS:
+		*val = sbat_emul_read_status(emul);
+		return 0;
+	case SB_CYCLE_COUNT:
+		*val = bat->cycle_count;
+		return 0;
+	case SB_DESIGN_CAPACITY:
+		if (mode_mw) {
+			*val = sbat_emul_ma_to_10mw(bat->design_cap,
+						    bat->design_mv);
+		} else {
+			*val = bat->design_cap;
+		}
+		return 0;
+	case SB_DESIGN_VOLTAGE:
+		*val = bat->design_mv;
+		return 0;
+	case SB_SPECIFICATION_INFO:
+		*val = bat->spec_info;
+		return 0;
+	case SB_MANUFACTURE_DATE:
+		*val = bat->mf_date;
+		return 0;
+	case SB_SERIAL_NUMBER:
+		*val = bat->sn;
+		return 0;
+	default:
+		/* Unknown command or return value is not word */
+		return 1;
+	}
+}
+
+/** Check description in emul_smart_battery.h */
+int sbat_emul_get_block_data(const struct emul *emul, int cmd, uint8_t **blk,
+			     int *len)
+{
+	struct sbat_emul_bat_data *bat;
+	struct sbat_emul_data *data;
+
+	data = emul->data;
+	bat = &data->bat;
+
+	switch (cmd) {
+	case SB_MANUFACTURER_NAME:
+		*blk = bat->mf_name;
+		*len = bat->mf_name_len;
+		return 0;
+	case SB_DEVICE_NAME:
+		*blk = bat->dev_name;
+		*len = bat->dev_name_len;
+		return 0;
+	case SB_DEVICE_CHEMISTRY:
+		*blk = bat->dev_chem;
+		*len = bat->dev_chem_len;
+		return 0;
+	case SB_MANUFACTURER_DATA:
+		*blk = bat->mf_data;
+		*len = bat->mf_data_len;
+		return 0;
+	case SB_MANUFACTURE_INFO:
+		*blk = bat->mf_info;
+		*len = bat->mf_info_len;
+		return 0;
+	default:
+		/* Unknown command or return value is not word */
+		return 1;
+	}
+}
+
+/**
+ * @brief Append PEC to read command response if battery support it
+ *
+ * @param data Pointer to smart battery emulator data
+ * @param cmd Command for which PEC is calculated
+ */
+static void sbat_emul_append_pec(const struct emul *emul, int cmd)
+{
+	uint8_t pec;
+	struct sbat_emul_data *data = emul->data;
+	const struct i2c_common_emul_cfg *cfg = emul->cfg;
+
+	if (BATTERY_SPEC_VERSION(data->bat.spec_info) ==
+	    BATTERY_SPEC_VER_1_1_WITH_PEC) {
+		pec = sbat_emul_pec_head(cfg->addr, 1, cmd);
+		pec = cros_crc8_arg(data->msg_buf, data->num_to_read, pec);
+		data->msg_buf[data->num_to_read] = pec;
+		data->num_to_read++;
+	}
+}
+
+/** Check description in emul_smart_battery.h */
+void sbat_emul_set_response(const struct emul *emul, int cmd, uint8_t *buf,
+			    int len, bool fail)
+{
+	struct sbat_emul_data *data;
+
+	data = emul->data;
+
+	if (fail) {
+		data->bat.error_code = STATUS_CODE_UNKNOWN_ERROR;
+		data->num_to_read = 0;
+		return;
+	}
+
+	data->num_to_read = MIN(len, MSG_BUF_LEN - 1);
+	memcpy(data->msg_buf, buf, data->num_to_read);
+	data->bat.error_code = STATUS_CODE_OK;
+	sbat_emul_append_pec(emul, cmd);
+}
+
+/**
+ * @brief Function which handles read messages. It expects that data->cur_cmd
+ *        is set to command number which should be handled. It guarantee that
+ *        data->num_to_read is set to number of bytes in data->msg_buf on
+ *        successful handling read request. On error, data->num_to_read is
+ *        always set to 0.
+ *
+ * @param emul Pointer to smart battery emulator
+ * @param reg Command selected by last write message. If data->cur_cmd is
+ *            different than SBAT_EMUL_NO_CMD, then reg should equal to
+ *            data->cur_cmd
+ *
+ * @return 0 on success
+ * @return -EIO on error
+ */
+static int sbat_emul_handle_read_msg(const struct emul *emul, int reg)
+{
+	struct sbat_emul_data *data;
+	uint16_t word;
+	uint8_t *blk;
+	int ret, len;
+
+	data = emul->data;
+
+	if (data->cur_cmd == SBAT_EMUL_NO_CMD) {
+		/* Unexpected read message without preceding command select */
+		data->bat.error_code = STATUS_CODE_UNKNOWN_ERROR;
+		return -EIO;
+	}
+	data->cur_cmd = SBAT_EMUL_NO_CMD;
+	data->num_to_read = 0;
+
+	/* Handle commands which return word */
+	ret = sbat_emul_get_word_val(emul, reg, &word);
+	if (ret < 0) {
+		return -EIO;
+	}
+	if (ret == 0) {
+		data->num_to_read = 2;
+		data->msg_buf[0] = word & 0xff;
+		data->msg_buf[1] = (word >> 8) & 0xff;
+		data->bat.error_code = STATUS_CODE_OK;
+		sbat_emul_append_pec(emul, reg);
+
+		return 0;
+	}
+
+	/* Handle commands which return block */
+	ret = sbat_emul_get_block_data(emul, reg, &blk, &len);
+	if (ret < 0) {
+		return -EIO;
+	}
+	if (ret == 0) {
+		data->num_to_read = len + 1;
+		data->msg_buf[0] = len;
+		memcpy(&data->msg_buf[1], blk, len);
+		data->bat.error_code = STATUS_CODE_OK;
+		sbat_emul_append_pec(emul, reg);
+
+		return 0;
+	}
+
+	/* Command is unknown. Wait for custom handler before failing. */
+	data->num_to_read = 0;
+
+	return 0;
+}
+
+/**
+ * @brief Function which finalize write messages.
+ *
+ * @param emul Pointer to smart battery emulator
+ * @param reg First byte of write message, usually selected command
+ * @param bytes Number of bytes received in data->msg_buf
+ *
+ * @return 0 on success
+ * @return -EIO on error
+ */
+static int sbat_emul_finalize_write_msg(const struct emul *emul, int reg,
+					int bytes)
+{
+	struct sbat_emul_bat_data *bat;
+	struct sbat_emul_data *data;
+	uint16_t word;
+	uint8_t pec;
+
+	data = emul->data;
+	bat = &data->bat;
+
+	/*
+	 * Fail if:
+	 *  - there are no bytes to handle
+	 *  - there are too many bytes
+	 *  - there is command byte and only one data byte
+	 */
+	if (bytes <= 0 || bytes > 4 || bytes == 2) {
+		data->bat.error_code = STATUS_CODE_BADSIZE;
+		LOG_ERR("wrong write message size (%d)", bytes);
+
+		return -EIO;
+	}
+
+	/* There is only command for read */
+	if (bytes == 1) {
+		data->cur_cmd = reg;
+		return 0;
+	}
+
+	/* Handle PEC */
+	data->msg_buf[0] = reg;
+	if (bytes == 4) {
+		if (BATTERY_SPEC_VERSION(data->bat.spec_info) !=
+		    BATTERY_SPEC_VER_1_1_WITH_PEC) {
+			data->bat.error_code = STATUS_CODE_BADSIZE;
+			LOG_ERR("Unexpected PEC; No support in this version");
+
+			return -EIO;
+		}
+		pec = sbat_emul_pec_head(data->common.cfg->addr, 0, 0);
+		pec = cros_crc8_arg(data->msg_buf, 3, pec);
+		if (pec != data->msg_buf[3]) {
+			data->bat.error_code = STATUS_CODE_UNKNOWN_ERROR;
+			LOG_ERR("Wrong PEC 0x%x != 0x%x", pec,
+				data->msg_buf[3]);
+
+			return -EIO;
+		}
+	}
+
+	word = ((int)data->msg_buf[2] << 8) | data->msg_buf[1];
+
+	switch (data->msg_buf[0]) {
+	case SB_MANUFACTURER_ACCESS:
+		bat->mf_access = word;
+		break;
+	case SB_REMAINING_CAPACITY_ALARM:
+		bat->cap_alarm = word;
+		break;
+	case SB_REMAINING_TIME_ALARM:
+		bat->time_alarm = word;
+		break;
+	case SB_BATTERY_MODE:
+		/* Allow to set only upper byte */
+		bat->mode &= 0xff;
+		bat->mode |= word & 0xff00;
+		break;
+	case SB_AT_RATE:
+		bat->at_rate = word;
+		break;
+	default:
+		data->bat.error_code = STATUS_CODE_ACCESS_DENIED;
+		LOG_ERR("Unknown write command (0x%x)", data->msg_buf[0]);
+
+		return -EIO;
+	}
+
+	data->bat.error_code = STATUS_CODE_OK;
+
+	return 0;
+}
+
+/**
+ * @brief Function called for each byte of write message which is saved in
+ *        data->msg_buf
+ *
+ * @param emul Pointer to smart battery emulator
+ * @param reg First byte of write message, usually selected command
+ * @param val Received byte of write message
+ * @param bytes Number of bytes already received
+ *
+ * @return 0 on success
+ */
+static int sbat_emul_write_byte(const struct emul *emul, int reg, uint8_t val,
+				int bytes)
+{
+	struct sbat_emul_data *data;
+
+	data = emul->data;
+
+	if (bytes < MSG_BUF_LEN) {
+		data->msg_buf[bytes] = val;
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Function called for each byte of read message. Byte from data->msg_buf
+ *        is copied to read message response.
+ *
+ * @param emul Pointer to smart battery emulator
+ * @param reg First byte of last write message, usually selected command
+ * @param val Pointer where byte to read should be stored
+ * @param bytes Number of bytes already readed
+ *
+ * @return 0 on success
+ */
+static int sbat_emul_read_byte(const struct emul *emul, int reg, uint8_t *val,
+			       int bytes)
+{
+	struct sbat_emul_data *data;
+
+	data = emul->data;
+
+	if (data->num_to_read == 0) {
+		data->bat.error_code = STATUS_CODE_UNSUPPORTED;
+		LOG_ERR("Unknown read command (0x%x)", reg);
+
+		return -EIO;
+	}
+
+	if (bytes < data->num_to_read) {
+		*val = data->msg_buf[bytes];
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Get currently accessed register, which always equals to selected
+ *        command.
+ *
+ * @param emul Pointer to smart battery emulator
+ * @param reg First byte of last write message, usually selected command
+ * @param bytes Number of bytes already handled from current message
+ * @param read If currently handled is read message
+ *
+ * @return Currently accessed register
+ */
+static int sbat_emul_access_reg(const struct emul *emul, int reg, int bytes,
+				bool read)
+{
+	return reg;
+}
+
+/* Device instantiation */
+
+/**
+ * @brief Set up a new Smart Battery emulator
+ *
+ * This should be called for each Smart Battery device that needs to be
+ * emulated. It registers it with the I2C emulation controller.
+ *
+ * @param emul Emulation information
+ * @param parent Device to emulate
+ *
+ * @return 0 indicating success (always)
+ */
+static int sbat_emul_init(const struct emul *emul, const struct device *parent)
+{
+	struct sbat_emul_data *data = emul->data;
+	const struct i2c_common_emul_cfg *cfg = emul->cfg;
+
+	data->common.i2c = parent;
+	data->common.cfg = cfg;
+
+	i2c_common_emul_init(&data->common);
+
+	return 0;
+}
+
+#define SMART_BATTERY_VALIDATE_STRING_PROPS_SIZE(n)                            \
+	BUILD_ASSERT(sizeof(DT_INST_PROP(n, dev_chem)) - 1 <= MAX_BLOCK_SIZE); \
+	BUILD_ASSERT(sizeof(DT_INST_PROP(n, mf_data)) - 1 <= MAX_BLOCK_SIZE);  \
+	BUILD_ASSERT(sizeof(DT_INST_PROP(n, mf_info)) - 1 <= MAX_BLOCK_SIZE);  \
+	BUILD_ASSERT(sizeof(DT_INST_PROP(n, mf_name)) - 1 <= MAX_BLOCK_SIZE);
+
+DT_INST_FOREACH_STATUS_OKAY(SMART_BATTERY_VALIDATE_STRING_PROPS_SIZE)
+
+#define SMART_BATTERY_EMUL(n)                                         \
+	static struct sbat_emul_data sbat_emul_data_##n = {		\
+		.bat = {						\
+			.mf_access = DT_INST_PROP(n, mf_access),	\
+			.at_rate_full_mw_support = DT_INST_PROP(n,	\
+					at_rate_full_mw_support),	\
+			.spec_info = ((DT_STRING_TOKEN(DT_DRV_INST(n),	\
+						       version) <<	\
+				       BATTERY_SPEC_VERSION_SHIFT) &	\
+				      BATTERY_SPEC_VERSION_MASK) |	\
+				     ((DT_INST_PROP(n, vscale) <<	\
+				       BATTERY_SPEC_VSCALE_SHIFT) &	\
+				      BATTERY_SPEC_VSCALE_MASK) |	\
+				     ((DT_INST_PROP(n, ipscale) <<	\
+				       BATTERY_SPEC_IPSCALE_SHIFT) &	\
+				      BATTERY_SPEC_IPSCALE_MASK) |	\
+				     BATTERY_SPEC_REVISION_1,		\
+			.mode = (DT_INST_PROP(n,			\
+					      int_charge_controller) *	\
+				 MODE_INTERNAL_CHARGE_CONTROLLER) |	\
+				(DT_INST_PROP(n, primary_battery) *	\
+				 MODE_PRIMARY_BATTERY_SUPPORT),		\
+			.design_mv = DT_INST_PROP(n, design_mv),	\
+			.default_design_mv = DT_INST_PROP(n, design_mv),\
+			.design_cap = DT_INST_PROP(n, design_cap),	\
+			.temp = DT_INST_PROP(n, temperature),		\
+			.volt = DT_INST_PROP(n, volt),			\
+			.cur = DT_INST_PROP(n, cur),			\
+			.avg_cur = DT_INST_PROP(n, avg_cur),		\
+			.max_error = DT_INST_PROP(n, max_error),	\
+			.cap = DT_INST_PROP(n, cap),			\
+			.default_cap = DT_INST_PROP(n, cap),		\
+			.full_cap = DT_INST_PROP(n, full_cap),		\
+			.default_full_cap = DT_INST_PROP(n, full_cap),	\
+			.desired_charg_cur = DT_INST_PROP(n,		\
+						desired_charg_cur),	\
+			.desired_charg_volt = DT_INST_PROP(n,		\
+						desired_charg_volt),	\
+			.cycle_count = DT_INST_PROP(n, cycle_count),	\
+			.sn = DT_INST_PROP(n, serial_number),		\
+			.mf_name = DT_INST_PROP(n, mf_name),		\
+			.mf_name_len = sizeof(				\
+					DT_INST_PROP(n, mf_name)) - 1,	\
+			.mf_data = DT_INST_PROP(n, mf_data),		\
+			.mf_data_len = sizeof(				\
+					DT_INST_PROP(n, mf_data)) - 1,	\
+			.dev_name = DT_INST_PROP(n, dev_name),		\
+			.dev_name_len = sizeof(				\
+					DT_INST_PROP(n, dev_name)) - 1,	\
+			.dev_chem = DT_INST_PROP(n, dev_chem),		\
+			.dev_chem_len = sizeof(				\
+					DT_INST_PROP(n, dev_chem)) - 1,	\
+			.mf_info = DT_INST_PROP(n, mf_info),		\
+			.mf_info_len = sizeof(				\
+					DT_INST_PROP(n, mf_info)) - 1,	\
+			.mf_date = 0,					\
+			.cap_alarm = 0,					\
+			.time_alarm = 0,				\
+			.at_rate = 0,					\
+			.status = STATUS_INITIALIZED,			\
+			.error_code = STATUS_CODE_OK,			\
+		},							\
+		.cur_cmd = SBAT_EMUL_NO_CMD,				\
+		.common = {						\
+			.start_write = NULL,				\
+			.write_byte = sbat_emul_write_byte,		\
+			.finish_write = sbat_emul_finalize_write_msg,	\
+			.start_read = sbat_emul_handle_read_msg,	\
+			.read_byte = sbat_emul_read_byte,		\
+			.finish_read = NULL,				\
+			.access_reg = sbat_emul_access_reg,		\
+		},							\
+	};        \
+                                                                      \
+	static const struct i2c_common_emul_cfg sbat_emul_cfg_##n = { \
+		.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)),       \
+		.data = &sbat_emul_data_##n.common,                   \
+		.addr = DT_INST_REG_ADDR(n),                          \
+	};                                                            \
+	EMUL_DT_INST_DEFINE(n, sbat_emul_init, &sbat_emul_data_##n,   \
+			    &sbat_emul_cfg_##n, &i2c_common_emul_api, NULL)
+
+DT_INST_FOREACH_STATUS_OKAY(SMART_BATTERY_EMUL)
+
+#define SMART_BATTERY_EMUL_CASE(n) \
+	case DT_INST_DEP_ORD(n):   \
+		return sbat_emul_data_##n.common.emul.target;
+
+#ifdef CONFIG_ZTEST
+static void emul_smart_battery_reset_capacity(const struct emul *emul)
+{
+	struct sbat_emul_data *bat_data = emul->data;
+	bat_data->bat.cap = bat_data->bat.default_cap;
+	bat_data->bat.full_cap = bat_data->bat.default_full_cap;
+	bat_data->bat.design_mv = bat_data->bat.default_design_mv;
+}
+
+#define SBAT_EMUL_RESET_RULE_AFTER(n) \
+	emul_smart_battery_reset_capacity(EMUL_DT_GET(DT_DRV_INST(n)));
+
+static void emul_sbat_reset(const struct ztest_unit_test *test, void *data)
+{
+	ARG_UNUSED(test);
+	ARG_UNUSED(data);
+
+	DT_INST_FOREACH_STATUS_OKAY(SBAT_EMUL_RESET_RULE_AFTER)
+}
+
+ZTEST_RULE(emul_smart_battery_reset, NULL, emul_sbat_reset);
+#endif /* CONFIG_ZTEST */
+
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
+
+struct i2c_common_emul_data *
+emul_smart_battery_get_i2c_common_data(const struct emul *emul)
+{
+	return emul->data;
+}
diff --git a/zephyr/emul/emul_sn5s330.c b/zephyr/emul/emul_sn5s330.c
new file mode 100644
index 0000000000..5e45733e1d
--- /dev/null
+++ b/zephyr/emul/emul_sn5s330.c
@@ -0,0 +1,361 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/ppc/sn5s330.h"
+#include "driver/ppc/sn5s330_public.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_sn5s330.h"
+#include "emul/emul_stub_device.h"
+#include "i2c.h"
+
+#include <errno.h>
+
+#include <zephyr/device.h>
+#include <zephyr/devicetree/gpio.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/i2c_emul.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/__assert.h>
+
+#define DT_DRV_COMPAT cros_sn5s330_emul
+
+LOG_MODULE_REGISTER(sn5s330_emul, CONFIG_SN5S330_EMUL_LOG_LEVEL);
+
+struct sn5s330_emul_data {
+	/** Common I2C data */
+	struct i2c_common_emul_data common;
+	/** Emulated int-pin port */
+	const struct device *gpio_int_port;
+	/** Emulated int-pin pin */
+	gpio_pin_t gpio_int_pin;
+	/** Emulated FUNC_SET1 register */
+	uint8_t func_set1_reg;
+	/** Emulated FUNC_SET2 register */
+	uint8_t func_set2_reg;
+	/** Emulated FUNC_SET3 register */
+	uint8_t func_set3_reg;
+	/** Emulated FUNC_SET4 register */
+	uint8_t func_set4_reg;
+	/** Emulated FUNC_SET5 register */
+	uint8_t func_set5_reg;
+	/** Emulated FUNC_SET6 register */
+	uint8_t func_set6_reg;
+	/** Emulated FUNC_SET7 register */
+	uint8_t func_set7_reg;
+	/** Emulated FUNC_SET8 register */
+	uint8_t func_set8_reg;
+	/** Emulated FUNC_SET9 register */
+	uint8_t func_set9_reg;
+	/** Emulated FUNC_SET10 register */
+	uint8_t func_set10_reg;
+	/** Emulated FUNC_SET11 register */
+	uint8_t func_set11_reg;
+	/** Emulated FUNC_SET12 register */
+	uint8_t func_set12_reg;
+	/** Emulated INT_STATUS_REG1 register */
+	uint8_t int_status_reg1;
+	/** Emulated INT_STATUS_REG2 register */
+	uint8_t int_status_reg2;
+	/** Emulated INT_STATUS_REG3 register */
+	uint8_t int_status_reg3;
+	/** Emulated INT_STATUS_REG4 register */
+	/*
+	 * TODO(b/205754232): Register name discrepancy
+	 */
+	uint8_t int_status_reg4;
+	/*
+	 * TODO(b/203364783): For all falling edge registers, implement
+	 * interrupt and bit change to correspond to change in interrupt status
+	 * registers.
+	 */
+	/** Emulated INT_MASK_RISE_REG1 register */
+	uint8_t int_mask_rise_reg1;
+	/** Emulated INT_MASK_RISE_REG2 register */
+	uint8_t int_mask_rise_reg2;
+	/** Emulated INT_MASK_RISE_REG3 register */
+	uint8_t int_mask_rise_reg3;
+	/** Emulated INT_MASK_FALL_REG1 register */
+	uint8_t int_mask_fall_reg1;
+	/** Emulated INT_MASK_FALL_REG2 register */
+	uint8_t int_mask_fall_reg2;
+	/** Emulated INT_MASK_FALL_REG3 register */
+	uint8_t int_mask_fall_reg3;
+	/** Emulated INT_TRIP_RISE_REG1 register */
+	uint8_t int_trip_rise_reg1;
+	/** Emulated INT_TRIP_RISE_REG2 register */
+	uint8_t int_trip_rise_reg2;
+	/** Emulated INT_TRIP_RISE_REG3 register */
+	uint8_t int_trip_rise_reg3;
+	/** Emulated INT_TRIP_FALL_REG1 register */
+	uint8_t int_trip_fall_reg1;
+	/** Emulated INT_TRIP_FALL_REG2 register */
+	uint8_t int_trip_fall_reg2;
+	/** Emulated INT_TRIP_FALL_REG3 register */
+	uint8_t int_trip_fall_reg3;
+};
+
+struct sn5s330_emul_cfg {
+	/** Common I2C config */
+	const struct i2c_common_emul_cfg common;
+};
+
+test_mockable_static void sn5s330_emul_interrupt_set_stub(void)
+{
+	/* Stub to be used by fff fakes during test */
+}
+
+/* Workhorse for mapping i2c reg to internal emulator data access */
+static uint8_t *sn5s330_emul_get_reg_ptr(struct sn5s330_emul_data *data,
+					 int reg)
+{
+	switch (reg) {
+	case SN5S330_FUNC_SET1:
+		return &(data->func_set1_reg);
+	case SN5S330_FUNC_SET2:
+		return &(data->func_set2_reg);
+	case SN5S330_FUNC_SET3:
+		return &(data->func_set3_reg);
+	case SN5S330_FUNC_SET4:
+		return &(data->func_set4_reg);
+	case SN5S330_FUNC_SET5:
+		return &(data->func_set5_reg);
+	case SN5S330_FUNC_SET6:
+		return &(data->func_set6_reg);
+	case SN5S330_FUNC_SET7:
+		return &(data->func_set7_reg);
+	case SN5S330_FUNC_SET8:
+		return &(data->func_set8_reg);
+	case SN5S330_FUNC_SET9:
+		return &(data->func_set9_reg);
+	case SN5S330_FUNC_SET10:
+		return &(data->func_set10_reg);
+	case SN5S330_FUNC_SET11:
+		return &(data->func_set11_reg);
+	case SN5S330_FUNC_SET12:
+		return &(data->func_set12_reg);
+	case SN5S330_INT_STATUS_REG1:
+		return &(data->int_status_reg1);
+	case SN5S330_INT_STATUS_REG2:
+		return &(data->int_status_reg2);
+	case SN5S330_INT_STATUS_REG3:
+		return &(data->int_status_reg3);
+	case SN5S330_INT_STATUS_REG4:
+		return &(data->int_status_reg4);
+	case SN5S330_INT_MASK_RISE_REG1:
+		return &(data->int_mask_rise_reg1);
+	case SN5S330_INT_MASK_RISE_REG2:
+		return &(data->int_mask_rise_reg2);
+	case SN5S330_INT_MASK_RISE_REG3:
+		return &(data->int_mask_rise_reg3);
+	case SN5S330_INT_MASK_FALL_REG1:
+		return &(data->int_mask_fall_reg1);
+	case SN5S330_INT_MASK_FALL_REG2:
+		return &(data->int_mask_fall_reg2);
+	case SN5S330_INT_MASK_FALL_REG3:
+		return &(data->int_mask_fall_reg3);
+	case SN5S330_INT_TRIP_RISE_REG1:
+		return &(data->int_trip_rise_reg1);
+	case SN5S330_INT_TRIP_RISE_REG2:
+		return &(data->int_trip_rise_reg2);
+	case SN5S330_INT_TRIP_RISE_REG3:
+		return &(data->int_trip_rise_reg3);
+	case SN5S330_INT_TRIP_FALL_REG1:
+		return &(data->int_trip_fall_reg1);
+	case SN5S330_INT_TRIP_FALL_REG2:
+		return &(data->int_trip_fall_reg2);
+	case SN5S330_INT_TRIP_FALL_REG3:
+		return &(data->int_trip_fall_reg3);
+	default:
+		__ASSERT(false, "Unimplemented Register Access Error on 0x%x",
+			 reg);
+		/* Statement never reached, required for compiler warnings */
+		return NULL;
+	}
+}
+
+void sn5s330_emul_peek_reg(const struct emul *emul, uint32_t reg, uint8_t *val)
+{
+	struct sn5s330_emul_data *data = emul->data;
+	uint8_t *data_reg = sn5s330_emul_get_reg_ptr(data, reg);
+
+	*val = *data_reg;
+}
+
+static void sn5s330_emul_set_int_pin(const struct emul *emul, bool val)
+{
+	struct sn5s330_emul_data *data = emul->data;
+	int res = gpio_emul_input_set(data->gpio_int_port, data->gpio_int_pin,
+				      val);
+	ARG_UNUSED(res);
+	__ASSERT_NO_MSG(res == 0);
+}
+
+static void sn5s330_emul_assert_interrupt(const struct emul *emul)
+{
+	sn5s330_emul_interrupt_set_stub();
+	sn5s330_emul_set_int_pin(emul, false);
+}
+
+static void sn5s330_emul_deassert_interrupt(const struct emul *emul)
+{
+	sn5s330_emul_set_int_pin(emul, true);
+}
+
+static int sn5s330_emul_read_byte(const struct emul *emul, int reg,
+				  uint8_t *val, int bytes)
+{
+	struct sn5s330_emul_data *data = emul->data;
+	uint8_t *reg_to_read = sn5s330_emul_get_reg_ptr(data, reg);
+
+	__ASSERT(bytes == 0, "bytes 0x%x != 0x0 on reg 0x%x", bytes, reg);
+	*val = *reg_to_read;
+
+	return 0;
+}
+
+static int sn5s330_emul_write_byte(const struct emul *emul, int reg,
+				   uint8_t val, int bytes)
+{
+	struct sn5s330_emul_data *data = emul->data;
+	uint8_t *reg_to_write;
+	bool deassert_int = false;
+
+	__ASSERT(bytes == 1, "bytes 0x%x != 0x1 on reg 0x%x", bytes, reg);
+
+	/* Specially check for read-only reg */
+	switch (reg) {
+	case SN5S330_INT_TRIP_RISE_REG1:
+		__fallthrough;
+	case SN5S330_INT_TRIP_RISE_REG2:
+		__fallthrough;
+	case SN5S330_INT_TRIP_RISE_REG3:
+		__fallthrough;
+	case SN5S330_INT_TRIP_FALL_REG1:
+		__fallthrough;
+	case SN5S330_INT_TRIP_FALL_REG2:
+		__fallthrough;
+	case SN5S330_INT_TRIP_FALL_REG3:
+		reg_to_write = sn5s330_emul_get_reg_ptr(data, reg);
+		/* Clearing any bit deasserts /INT interrupt signal */
+		deassert_int = (*reg_to_write & val) != 0;
+		/* Write 0 is noop and 1 clears the bit. */
+		val = (~val & *reg_to_write);
+		*reg_to_write = val;
+		break;
+	case SN5S330_INT_STATUS_REG1:
+		__fallthrough;
+	case SN5S330_INT_STATUS_REG2:
+		__fallthrough;
+	case SN5S330_INT_STATUS_REG3:
+		__ASSERT(false,
+			 "Write to an unverified-as-safe read-only register on "
+			 "0x%x",
+			 reg);
+		__fallthrough;
+	default:
+		reg_to_write = sn5s330_emul_get_reg_ptr(data, reg);
+		*reg_to_write = val;
+	}
+
+	if (deassert_int)
+		sn5s330_emul_deassert_interrupt(emul);
+
+	return 0;
+}
+
+void sn5s330_emul_make_vbus_overcurrent(const struct emul *emul)
+{
+	struct sn5s330_emul_data *data = emul->data;
+
+	data->int_status_reg1 |= SN5S330_ILIM_PP1_MASK;
+	data->int_trip_rise_reg1 |= SN5S330_ILIM_PP1_MASK;
+
+	/* driver disabled this interrupt trigger */
+	if (data->int_mask_rise_reg1 & SN5S330_ILIM_PP1_MASK)
+		return;
+
+	sn5s330_emul_assert_interrupt(emul);
+}
+
+void sn5s330_emul_lower_vbus_below_minv(const struct emul *emul)
+{
+	struct sn5s330_emul_data *data = emul->data;
+
+	data->int_status_reg4 |= SN5S330_VSAFE0V_STAT;
+
+	/* driver disabled this interrupt trigger */
+	if (data->int_status_reg4 & SN5S330_VSAFE0V_MASK)
+		return;
+
+	sn5s330_emul_assert_interrupt(emul);
+}
+
+void sn5s330_emul_reset(const struct emul *emul)
+{
+	struct sn5s330_emul_data *data = emul->data;
+	struct i2c_common_emul_data common = data->common;
+	const struct device *gpio_int_port = data->gpio_int_port;
+	gpio_pin_t gpio_int_pin = data->gpio_int_pin;
+
+	sn5s330_emul_deassert_interrupt(emul);
+
+	/*
+	 * TODO(b/203364783): Some registers reset with set bits; this should be
+	 * reflected in the emul_reset function.
+	 */
+
+	/* Only Reset the sn5s330 Register Data */
+	memset(data, 0, sizeof(struct sn5s330_emul_data));
+	data->common = common;
+	data->gpio_int_port = gpio_int_port;
+	data->gpio_int_pin = gpio_int_pin;
+}
+
+static int emul_sn5s330_init(const struct emul *emul,
+			     const struct device *parent)
+{
+	struct sn5s330_emul_data *data = emul->data;
+
+	sn5s330_emul_deassert_interrupt(emul);
+
+	data->common.i2c = parent;
+	i2c_common_emul_init(&data->common);
+
+	return 0;
+}
+
+#define SN5S330_GET_GPIO_INT_PORT(n) \
+	DEVICE_DT_GET(DT_GPIO_CTLR(DT_INST_PROP(n, int_pin), gpios))
+
+#define SN5S330_GET_GPIO_INT_PIN(n) DT_GPIO_PIN(DT_INST_PROP(n, int_pin), gpios)
+
+#define INIT_SN5S330(n)                                                          \
+	static struct sn5s330_emul_data sn5s330_emul_data_##n = { \
+		.common = {                                                    \
+			.write_byte = sn5s330_emul_write_byte,                 \
+			.read_byte = sn5s330_emul_read_byte,                   \
+		},                                                             \
+		.gpio_int_port = SN5S330_GET_GPIO_INT_PORT(n),		       \
+		.gpio_int_pin = SN5S330_GET_GPIO_INT_PIN(n),		       \
+	};              \
+	static struct sn5s330_emul_cfg sn5s330_emul_cfg_##n = {                \
+		.common = {                                                    \
+			.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)),        \
+			.addr = DT_INST_REG_ADDR(n),                           \
+		},                                                             \
+	}; \
+	EMUL_DT_INST_DEFINE(n, emul_sn5s330_init, &sn5s330_emul_data_##n,        \
+			    &sn5s330_emul_cfg_##n, &i2c_common_emul_api, NULL)
+
+DT_INST_FOREACH_STATUS_OKAY(INIT_SN5S330)
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
+
+struct i2c_common_emul_data *
+emul_sn5s330_get_i2c_common_data(const struct emul *emul)
+{
+	return emul->data;
+}
diff --git a/zephyr/emul/emul_syv682x.c b/zephyr/emul/emul_syv682x.c
new file mode 100644
index 0000000000..712dca2276
--- /dev/null
+++ b/zephyr/emul/emul_syv682x.c
@@ -0,0 +1,298 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_stub_device.h"
+#include "emul/emul_syv682x.h"
+
+#include <stdint.h>
+#include <string.h>
+
+#include <zephyr/device.h>
+#include <zephyr/devicetree/gpio.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/i2c_emul.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/ztest.h>
+
+#define DT_DRV_COMPAT zephyr_syv682x_emul
+
+#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
+LOG_MODULE_REGISTER(syv682x);
+#define EMUL_REG_COUNT (SYV682X_CONTROL_4_REG + 1)
+#define EMUL_REG_IS_VALID(reg) (reg >= 0 && reg < EMUL_REG_COUNT)
+
+struct syv682x_emul_data {
+	struct i2c_common_emul_data common;
+	/** GPIO ports connected to the PPC */
+	const struct device *frs_en_gpio_port;
+	gpio_pin_t frs_en_gpio_pin;
+	const struct device *alert_gpio_port;
+	gpio_pin_t alert_gpio_pin;
+	/** Configuration information */
+	const struct syv682x_emul_cfg *cfg;
+	/** Current state of all emulated SYV682x registers */
+	uint8_t reg[EMUL_REG_COUNT];
+	/**
+	 * Current state of conditions affecting interrupt bits, as distinct
+	 * from the current values of those bits stored in reg.
+	 */
+	uint8_t status_cond;
+	uint8_t control_4_cond;
+	/**
+	 * How many CONTROL_3 reads the busy bit should stay set. 0 means not
+	 * busy.
+	 */
+	int busy_read_count;
+};
+
+/** Static configuration for the emulator */
+struct syv682x_emul_cfg {
+	const struct i2c_common_emul_cfg common;
+};
+
+/* Asserts or deasserts the interrupt signal to the EC. */
+static void syv682x_emul_set_alert(struct syv682x_emul_data *data, bool alert)
+{
+	int res = gpio_emul_input_set(data->alert_gpio_port,
+				      /* The signal is inverted. */
+				      data->alert_gpio_pin, !alert);
+	__ASSERT_NO_MSG(res == 0);
+}
+
+int syv682x_emul_set_reg(const struct emul *emul, int reg, uint8_t val)
+{
+	struct syv682x_emul_data *data = emul->data;
+
+	if (!EMUL_REG_IS_VALID(reg))
+		return -EIO;
+
+	data->reg[reg] = val;
+
+	return 0;
+}
+
+void syv682x_emul_set_condition(const struct emul *emul, uint8_t status,
+				uint8_t control_4)
+{
+	uint8_t control_4_interrupt = control_4 & SYV682X_CONTROL_4_INT_MASK;
+	struct syv682x_emul_data *data = emul->data;
+	int frs_en_gpio = gpio_emul_output_get(data->frs_en_gpio_port,
+					       data->frs_en_gpio_pin);
+
+	__ASSERT_NO_MSG(frs_en_gpio >= 0);
+
+	/* Only assert FRS status if FRS is enabled. */
+	if (!frs_en_gpio)
+		status &= ~SYV682X_STATUS_FRS;
+
+	data->status_cond = status;
+	data->reg[SYV682X_STATUS_REG] |= status;
+
+	data->control_4_cond = control_4_interrupt;
+	/* Only update the interrupting bits of CONTROL_4. */
+	data->reg[SYV682X_CONTROL_4_REG] &= ~SYV682X_CONTROL_4_INT_MASK;
+	data->reg[SYV682X_CONTROL_4_REG] |= control_4_interrupt;
+
+	/* These conditions disable the power path. */
+	if (status &
+	    (SYV682X_STATUS_TSD | SYV682X_STATUS_OVP | SYV682X_STATUS_OC_HV)) {
+		data->reg[SYV682X_CONTROL_1_REG] |= SYV682X_CONTROL_1_PWR_ENB;
+	}
+
+	/*
+	 * Note: The description of CONTROL_4 suggests that setting VCONN_OC
+	 * will turn off the VCONN channel. The "VCONN Channel Over Current
+	 * Response" plot shows that VCONN the device will merely throttle VCONN
+	 * current. The latter behavior is observed in practice, and this
+	 * emulator does not currently model it.
+	 */
+
+	/* VBAT_OVP disconnects CC and VCONN. */
+	if (control_4_interrupt & SYV682X_CONTROL_4_VBAT_OVP) {
+		data->reg[SYV682X_CONTROL_4_REG] &= ~(
+			SYV682X_CONTROL_4_CC1_BPS | SYV682X_CONTROL_4_CC2_BPS |
+			SYV682X_CONTROL_4_VCONN1 | SYV682X_CONTROL_4_VCONN2);
+	}
+
+	syv682x_emul_set_alert(data, status | control_4_interrupt);
+}
+
+void syv682x_emul_set_busy_reads(const struct emul *emul, int reads)
+{
+	struct syv682x_emul_data *data = emul->data;
+	data->busy_read_count = reads;
+	if (reads)
+		data->reg[SYV682X_CONTROL_3_REG] |= SYV682X_BUSY;
+	else
+		data->reg[SYV682X_CONTROL_3_REG] &= ~SYV682X_BUSY;
+}
+
+int syv682x_emul_get_reg(const struct emul *emul, int reg, uint8_t *val)
+{
+	struct syv682x_emul_data *data = emul->data;
+
+	if (!EMUL_REG_IS_VALID(reg))
+		return -EIO;
+
+	*val = data->reg[reg];
+
+	return 0;
+}
+
+static int syv682x_emul_write_byte(const struct emul *emul, int reg,
+				   uint8_t val, int bytes)
+{
+	struct syv682x_emul_data *data = emul->data;
+
+	zassert_equal(bytes, 1, "Write: bytes == %i at offset 0x%x", bytes,
+		      reg);
+
+	switch (reg) {
+	case SYV682X_CONTROL_1_REG:
+		/*
+		 * If OVP or TSD is active, the power path stays
+		 * disabled.
+		 */
+		if (data->status_cond &
+		    (SYV682X_STATUS_TSD | SYV682X_STATUS_OVP))
+			val |= SYV682X_CONTROL_1_PWR_ENB;
+		break;
+	case SYV682X_CONTROL_4_REG:
+		/* Interrupt bits are read-only. */
+		val &= ~SYV682X_CONTROL_4_INT_MASK;
+		break;
+	default:
+		break;
+	}
+
+	return syv682x_emul_set_reg(emul, reg, val);
+}
+
+static int syv682x_emul_read_byte(const struct emul *emul, int reg,
+				  uint8_t *val, int bytes)
+{
+	struct syv682x_emul_data *data = emul->data;
+	int ret = syv682x_emul_get_reg(emul, reg, val);
+
+	zassert_equal(bytes, 0, "Read: bytes == %i at offset 0x%x", bytes, reg);
+
+	switch (reg) {
+	/*
+	 * STATUS and the interrupt bits of CONTROL_4 are clear-on-read
+	 * (if the underlying condition has cleared).
+	 */
+	case SYV682X_STATUS_REG:
+		syv682x_emul_set_reg(emul, reg, data->status_cond);
+		break;
+	case SYV682X_CONTROL_3_REG:
+		/* Update CONTROL_3[BUSY] based on the busy count. */
+		if (data->busy_read_count > 0) {
+			if (--data->busy_read_count == 0) {
+				data->reg[SYV682X_CONTROL_3_REG] &=
+					~SYV682X_BUSY;
+			}
+		}
+		break;
+	case SYV682X_CONTROL_4_REG:
+		syv682x_emul_set_reg(emul, reg,
+				     (*val & ~SYV682X_CONTROL_4_INT_MASK) |
+					     data->control_4_cond);
+		break;
+	default:
+		break;
+	}
+
+	return ret;
+}
+
+static void syv682x_emul_reset(const struct emul *emul)
+{
+	struct syv682x_emul_data *data = emul->data;
+
+	memset(data->reg, 0, sizeof(data->reg));
+
+	syv682x_emul_set_alert(data, false);
+	data->reg[SYV682X_CONTROL_1_REG] =
+		(SYV682X_HV_ILIM_3_30 << SYV682X_HV_ILIM_BIT_SHIFT) |
+		(SYV682X_5V_ILIM_3_30 << SYV682X_5V_ILIM_BIT_SHIFT) |
+		/* HV_DR = 0 */
+		SYV682X_CONTROL_1_CH_SEL;
+}
+
+/**
+ * @brief Set up a new SYV682x emulator
+ *
+ * This should be called for each SYV682x device that needs to be emulated. It
+ * registers it with the I2C emulation controller.
+ *
+ * @param emul Emulation information
+ * @param parent Device to emulate
+ *
+ * @return 0 on success or an error code on failure
+ */
+static int syv682x_emul_init(const struct emul *emul,
+			     const struct device *parent)
+{
+	struct syv682x_emul_data *data = emul->data;
+
+	data->common.i2c = parent;
+	i2c_common_emul_init(&data->common);
+
+	syv682x_emul_reset(emul);
+	return 0;
+}
+
+/* Device instantiation */
+#define SYV682X_EMUL(n)                                                          \
+	static struct syv682x_emul_data syv682x_emul_data_##n = {              \
+		.common = {                                                    \
+			.write_byte = syv682x_emul_write_byte,                 \
+			.read_byte = syv682x_emul_read_byte,                   \
+		},                                                             \
+		.frs_en_gpio_port = DEVICE_DT_GET(DT_GPIO_CTLR(                \
+					DT_INST_PROP(n, frs_en_gpio), gpios)), \
+		.frs_en_gpio_pin = DT_GPIO_PIN(                                \
+				DT_INST_PROP(n, frs_en_gpio), gpios),          \
+		.alert_gpio_port = DEVICE_DT_GET(DT_GPIO_CTLR(                 \
+					DT_INST_PROP(n, alert_gpio), gpios)),  \
+		.alert_gpio_pin = DT_GPIO_PIN(                                 \
+				DT_INST_PROP(n, alert_gpio), gpios),           \
+	}; \
+	static const struct syv682x_emul_cfg syv682x_emul_cfg_##n = {          \
+		.common = {                                                    \
+			.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)),        \
+			.addr = DT_INST_REG_ADDR(n),                           \
+		},                                                             \
+	}; \
+	EMUL_DT_INST_DEFINE(n, syv682x_emul_init, &syv682x_emul_data_##n,        \
+			    &syv682x_emul_cfg_##n, &i2c_common_emul_api, NULL)
+
+DT_INST_FOREACH_STATUS_OKAY(SYV682X_EMUL)
+
+#ifdef CONFIG_ZTEST_NEW_API
+
+#define SYV682X_EMUL_RESET_RULE_BEFORE(n) \
+	syv682x_emul_reset(EMUL_DT_GET(DT_DRV_INST(n)));
+
+static void emul_syv682x_reset_before(const struct ztest_unit_test *test,
+				      void *data)
+{
+	ARG_UNUSED(test);
+	ARG_UNUSED(data);
+	DT_INST_FOREACH_STATUS_OKAY(SYV682X_EMUL_RESET_RULE_BEFORE);
+}
+ZTEST_RULE(emul_syv682x_reset, emul_syv682x_reset_before, NULL);
+#endif /* CONFIG_ZTEST_NEW_API */
+
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
+
+struct i2c_common_emul_data *
+emul_syv682x_get_i2c_common_data(const struct emul *emul)
+{
+	return emul->data;
+}
diff --git a/zephyr/emul/emul_tcs3400.c b/zephyr/emul/emul_tcs3400.c
new file mode 100644
index 0000000000..fe64acf791
--- /dev/null
+++ b/zephyr/emul/emul_tcs3400.c
@@ -0,0 +1,643 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/als_tcs3400.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_stub_device.h"
+#include "emul/emul_tcs3400.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/i2c_emul.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/ztest.h>
+
+#define DT_DRV_COMPAT zephyr_tcs3400_emul
+
+#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
+LOG_MODULE_REGISTER(emul_tcs);
+
+/** Run-time data used by the emulator */
+struct tcs_emul_data {
+	/** Common I2C data */
+	struct i2c_common_emul_data common;
+
+	/** Value of data byte in ongoing write message */
+	uint8_t write_byte;
+
+	/** Current state of emulated TCS3400 registers */
+	uint8_t reg[TCS_EMUL_REG_COUNT];
+	/** Return IR value instead of clear */
+	bool ir_select;
+	/** Internal values of light sensor registers */
+	int red;
+	int green;
+	int blue;
+	int clear;
+	int ir;
+
+	/** ID registers value */
+	uint8_t revision;
+	uint8_t id;
+
+	/** Return error when trying to write to RO register */
+	bool error_on_ro_write;
+	/** Return error when trying to write 1 to reserved bit */
+	bool error_on_rsvd_write;
+	/** Return error when trying to access MSB before LSB */
+	bool error_on_msb_first;
+	/**
+	 * Flag set when LSB register is accessed and cleared when MSB is
+	 * accessed. Allows to track order of accessing data registers
+	 */
+	bool lsb_r_read;
+	bool lsb_g_read;
+	bool lsb_b_read;
+	bool lsb_c_ir_read;
+};
+
+/** Check description in emul_tcs3400.h */
+void tcs_emul_set_reg(const struct emul *emul, int reg, uint8_t val)
+{
+	struct tcs_emul_data *data;
+
+	if (reg < TCS_EMUL_FIRST_REG || reg > TCS_EMUL_LAST_REG) {
+		return;
+	}
+
+	reg -= TCS_EMUL_FIRST_REG;
+	data = emul->data;
+	data->reg[reg] = val;
+}
+
+/** Check description in emul_tcs3400.h */
+uint8_t tcs_emul_get_reg(const struct emul *emul, int reg)
+{
+	struct tcs_emul_data *data;
+
+	if (reg < TCS_EMUL_FIRST_REG || reg > TCS_EMUL_LAST_REG) {
+		return 0;
+	}
+
+	data = emul->data;
+	reg -= TCS_EMUL_FIRST_REG;
+
+	return data->reg[reg];
+}
+
+/** Check description in emul_tcs3400.h */
+int tcs_emul_get_val(const struct emul *emul, enum tcs_emul_axis axis)
+{
+	struct tcs_emul_data *data;
+
+	data = emul->data;
+
+	switch (axis) {
+	case TCS_EMUL_R:
+		return data->red;
+	case TCS_EMUL_G:
+		return data->green;
+	case TCS_EMUL_B:
+		return data->blue;
+	case TCS_EMUL_C:
+		return data->clear;
+	case TCS_EMUL_IR:
+		return data->ir;
+	}
+
+	return 0;
+}
+
+/** Check description in emul_tcs3400.h */
+void tcs_emul_set_val(const struct emul *emul, enum tcs_emul_axis axis, int val)
+{
+	struct tcs_emul_data *data;
+
+	data = emul->data;
+
+	switch (axis) {
+	case TCS_EMUL_R:
+		data->red = val;
+		break;
+	case TCS_EMUL_G:
+		data->green = val;
+		break;
+	case TCS_EMUL_B:
+		data->blue = val;
+		break;
+	case TCS_EMUL_C:
+		data->clear = val;
+		break;
+	case TCS_EMUL_IR:
+		data->ir = val;
+		break;
+	}
+}
+
+/** Check description in emul_tcs3400.h */
+void tcs_emul_set_err_on_ro_write(const struct emul *emul, bool set)
+{
+	struct tcs_emul_data *data;
+
+	data = emul->data;
+	data->error_on_ro_write = set;
+}
+
+/** Check description in emul_tcs3400.h */
+void tcs_emul_set_err_on_rsvd_write(const struct emul *emul, bool set)
+{
+	struct tcs_emul_data *data;
+
+	data = emul->data;
+	data->error_on_rsvd_write = set;
+}
+
+/** Check description in emul_tcs3400.h */
+void tcs_emul_set_err_on_msb_first(const struct emul *emul, bool set)
+{
+	struct tcs_emul_data *data;
+
+	data = emul->data;
+	data->error_on_msb_first = set;
+}
+
+/** Mask reserved bits in registers of TCS3400 */
+static const uint8_t tcs_emul_rsvd_mask[] = {
+	[TCS_I2C_ENABLE - TCS_EMUL_FIRST_REG] = 0xa4,
+	[TCS_I2C_ATIME - TCS_EMUL_FIRST_REG] = 0x00,
+	[0x2] = 0xff, /* Reserved */
+	[TCS_I2C_WTIME - TCS_EMUL_FIRST_REG] = 0x00,
+	[TCS_I2C_AILTL - TCS_EMUL_FIRST_REG] = 0x00,
+	[TCS_I2C_AILTH - TCS_EMUL_FIRST_REG] = 0x00,
+	[TCS_I2C_AIHTL - TCS_EMUL_FIRST_REG] = 0x00,
+	[TCS_I2C_AIHTH - TCS_EMUL_FIRST_REG] = 0x00,
+	[0x8 ... 0xb] = 0xff, /* Reserved */
+	[TCS_I2C_PERS - TCS_EMUL_FIRST_REG] = 0xf0,
+	[TCS_I2C_CONFIG - TCS_EMUL_FIRST_REG] = 0x81,
+	[0xe] = 0xff, /* Reserved */
+	[TCS_I2C_CONTROL - TCS_EMUL_FIRST_REG] = 0xfc,
+	[TCS_I2C_AUX - TCS_EMUL_FIRST_REG] = 0xdf,
+	[TCS_I2C_REVID - TCS_EMUL_FIRST_REG] = 0xf0,
+	[TCS_I2C_ID - TCS_EMUL_FIRST_REG] = 0x00,
+	[TCS_I2C_STATUS - TCS_EMUL_FIRST_REG] = 0x6e,
+	[TCS_I2C_CDATAL - TCS_EMUL_FIRST_REG] = 0x00,
+	[TCS_I2C_CDATAH - TCS_EMUL_FIRST_REG] = 0x00,
+	[TCS_I2C_RDATAL - TCS_EMUL_FIRST_REG] = 0x00,
+	[TCS_I2C_RDATAH - TCS_EMUL_FIRST_REG] = 0x00,
+	[TCS_I2C_GDATAL - TCS_EMUL_FIRST_REG] = 0x00,
+	[TCS_I2C_GDATAH - TCS_EMUL_FIRST_REG] = 0x00,
+	[TCS_I2C_BDATAL - TCS_EMUL_FIRST_REG] = 0x00,
+	[TCS_I2C_BDATAH - TCS_EMUL_FIRST_REG] = 0x00,
+};
+
+/**
+ * @brief Reset registers to default values
+ *
+ * @param emul Pointer to TCS3400 emulator
+ */
+static void tcs_emul_reset(const struct emul *emul)
+{
+	struct tcs_emul_data *data;
+
+	data = emul->data;
+
+	data->reg[TCS_I2C_ENABLE - TCS_EMUL_FIRST_REG] = 0x00;
+	data->reg[TCS_I2C_ATIME - TCS_EMUL_FIRST_REG] = 0xff;
+	data->reg[TCS_I2C_WTIME - TCS_EMUL_FIRST_REG] = 0xff;
+	data->reg[TCS_I2C_AILTL - TCS_EMUL_FIRST_REG] = 0x00;
+	data->reg[TCS_I2C_AILTH - TCS_EMUL_FIRST_REG] = 0x00;
+	data->reg[TCS_I2C_AIHTL - TCS_EMUL_FIRST_REG] = 0x00;
+	data->reg[TCS_I2C_AIHTH - TCS_EMUL_FIRST_REG] = 0x00;
+	data->reg[TCS_I2C_PERS - TCS_EMUL_FIRST_REG] = 0x00;
+	data->reg[TCS_I2C_CONFIG - TCS_EMUL_FIRST_REG] = 0x40;
+	data->reg[TCS_I2C_CONTROL - TCS_EMUL_FIRST_REG] = 0x00;
+	data->reg[TCS_I2C_AUX - TCS_EMUL_FIRST_REG] = 0x00;
+	data->reg[TCS_I2C_REVID - TCS_EMUL_FIRST_REG] = data->revision;
+	data->reg[TCS_I2C_ID - TCS_EMUL_FIRST_REG] = data->id;
+	data->reg[TCS_I2C_STATUS - TCS_EMUL_FIRST_REG] = 0x00;
+	data->reg[TCS_I2C_CDATAL - TCS_EMUL_FIRST_REG] = 0x00;
+	data->reg[TCS_I2C_CDATAH - TCS_EMUL_FIRST_REG] = 0x00;
+	data->reg[TCS_I2C_RDATAL - TCS_EMUL_FIRST_REG] = 0x00;
+	data->reg[TCS_I2C_RDATAH - TCS_EMUL_FIRST_REG] = 0x00;
+	data->reg[TCS_I2C_GDATAL - TCS_EMUL_FIRST_REG] = 0x00;
+	data->reg[TCS_I2C_GDATAH - TCS_EMUL_FIRST_REG] = 0x00;
+	data->reg[TCS_I2C_BDATAL - TCS_EMUL_FIRST_REG] = 0x00;
+	data->reg[TCS_I2C_BDATAH - TCS_EMUL_FIRST_REG] = 0x00;
+
+	data->ir_select = false;
+}
+
+/**
+ * @brief Convert gain in format of CONTROL register to multiplyer
+ *
+ * @param control Value of CONTROL register
+ *
+ * @return gain by which messured value should be multiplied
+ */
+static int tcs_emul_get_gain(uint8_t control)
+{
+	switch (control & TCS_I2C_CONTROL_MASK) {
+	case 0:
+		return 1;
+	case 1:
+		return 4;
+	case 2:
+		return 16;
+	case 3:
+		return 64;
+	default:
+		return -1;
+	}
+}
+
+/**
+ * @brief Convert number of cycles in format of ATIME register
+ *
+ * @param atime Value of ATIME register
+ *
+ * @return cycles count that should be used to obtain light sensor values
+ */
+static int tcs_emul_get_cycles(uint8_t atime)
+{
+	return TCS_EMUL_MAX_CYCLES - (int)atime;
+}
+
+/**
+ * @brief Clear all interrupt registers
+ *
+ * @param emul Pointer to TCS3400 emulator
+ */
+static void tcs_emul_clear_int(const struct emul *emul)
+{
+	struct tcs_emul_data *data;
+
+	data = emul->data;
+
+	data->reg[TCS_I2C_STATUS - TCS_EMUL_FIRST_REG] = 0x00;
+}
+
+/**
+ * @brief Handle I2C write message. It is checked if accessed register isn't RO
+ *        and reserved bits are set to 0. Write set value of reg field of TCS
+ *        emulator data ignoring reserved bits and write only bits. Some
+ *        commands are handled specialy.
+ *
+ * @param emul Pointer to TCS3400 emulator
+ * @param reg Register which is written
+ * @param bytes Number of bytes received in this write message
+ *
+ * @return 0 on success
+ * @return -EIO on error
+ */
+static int tcs_emul_handle_write(const struct emul *emul, int reg, int bytes)
+{
+	struct tcs_emul_data *data;
+	uint8_t val;
+
+	data = emul->data;
+
+	/* This write only selected register for I2C read message */
+	if (bytes < 2) {
+		return 0;
+	}
+
+	val = data->write_byte;
+
+	/* Register is in data->reg */
+	if (reg >= TCS_EMUL_FIRST_REG && reg <= TCS_EMUL_LAST_REG) {
+		if (reg >= TCS_I2C_REVID && reg <= TCS_I2C_BDATAH) {
+			if (data->error_on_ro_write) {
+				LOG_ERR("Writing to reg 0x%x which is RO", reg);
+				return -EIO;
+			}
+
+			return 0;
+		}
+
+		if (reg == TCS_I2C_CONFIG && data->error_on_rsvd_write &&
+		    !(BIT(6) & val)) {
+			LOG_ERR("CONFIG reg bit 6 is write as 6 (writing 0x%x)",
+				val);
+			return -EIO;
+		}
+
+		reg -= TCS_EMUL_FIRST_REG;
+		if (data->error_on_rsvd_write &&
+		    tcs_emul_rsvd_mask[reg] & val) {
+			LOG_ERR("Writing 0x%x to reg 0x%x with rsvd mask 0x%x",
+				val, reg + TCS_EMUL_FIRST_REG,
+				tcs_emul_rsvd_mask[reg]);
+			return -EIO;
+		}
+
+		/* Ignore all reserved bits */
+		val &= ~tcs_emul_rsvd_mask[reg];
+		val |= data->reg[reg] & tcs_emul_rsvd_mask[reg];
+
+		data->reg[reg] = val;
+
+		return 0;
+	}
+
+	switch (reg) {
+	case TCS_I2C_IR:
+		if (data->error_on_rsvd_write && 0x7f & val) {
+			LOG_ERR("Writing 0x%x to reg 0x%x with rsvd mask 0x7f",
+				val, reg);
+			return -EIO;
+		}
+		data->ir_select = !!(val & BIT(7));
+		break;
+	case TCS_I2C_IFORCE:
+		/* Interrupt generate is not supported */
+		break;
+	case TCS_I2C_CICLEAR:
+	case TCS_I2C_AICLEAR:
+		tcs_emul_clear_int(emul);
+		break;
+	default:
+		/* Assume that other registers are RO */
+		if (data->error_on_ro_write) {
+			LOG_ERR("Writing to reg 0x%x which is RO (unknown)",
+				reg);
+			return -EIO;
+		}
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Get set light sensor value for given register using internal
+ *        state @p val. In case of accessing MSB check if LSB was accessed first
+ *
+ * @param emul Pointer to TCS3400 emulator
+ * @param reg LSB or MSB register address. LSB has to be aligned to 2
+ * @param lsb_read Pointer to variable which represent if last access to this
+ *                 accelerometer value was through LSB register
+ * @param lsb True if now accessing LSB, Flase if now accessing MSB
+ * @param val Internal value of accessed light sensor
+ *
+ * @return 0 on success
+ * @return -EIO when accessing MSB before LSB
+ */
+static int tcs_emul_get_reg_val(const struct emul *emul, int reg,
+				bool *lsb_read, bool lsb, unsigned int val)
+{
+	struct tcs_emul_data *data;
+	uint64_t reg_val;
+	int msb_reg;
+	int lsb_reg;
+	int cycles;
+	int gain;
+
+	data = emul->data;
+
+	if (lsb) {
+		*lsb_read = 1;
+	} else {
+		/*
+		 * If error on first accessing MSB is set and LSB wasn't
+		 * accessed before, then return error.
+		 */
+		if (data->error_on_msb_first && !(*lsb_read)) {
+			return -EIO;
+		}
+		*lsb_read = 0;
+		/* LSB read should set correct value */
+		return 0;
+	}
+
+	lsb_reg = (reg - TCS_EMUL_FIRST_REG) & ~(0x1);
+	msb_reg = (reg - TCS_EMUL_FIRST_REG) | 0x1;
+
+	gain = tcs_emul_get_gain(
+		data->reg[TCS_I2C_CONTROL - TCS_EMUL_FIRST_REG]);
+	cycles = tcs_emul_get_cycles(
+		data->reg[TCS_I2C_ATIME - TCS_EMUL_FIRST_REG]);
+	/*
+	 * Internal value is with 256 cycles and x64 gain, so divide it to get
+	 * registers value
+	 */
+	reg_val = (uint64_t)val * cycles * gain / TCS_EMUL_MAX_CYCLES /
+		  TCS_EMUL_MAX_GAIN;
+
+	if (reg_val > UINT16_MAX) {
+		reg_val = UINT16_MAX;
+	}
+
+	data->reg[lsb_reg] = reg_val & 0xff;
+	data->reg[msb_reg] = (reg_val >> 8) & 0xff;
+
+	return 0;
+}
+
+/**
+ * @brief Handle I2C read message. Response is obtained from reg field of TCS
+ *        emul data. When accessing light sensor value, register data is first
+ *        computed using internal emulator state.
+ *
+ * @param emul Pointer to TCS3400 emulator
+ * @param reg First register address that is accessed in this read message
+ * @param buf Pointer where result should be stored
+ * @param bytes Number of bytes already handled in this read message
+ *
+ * @return 0 on success
+ * @return -EIO on error
+ */
+static int tcs_emul_handle_read(const struct emul *emul, int reg, uint8_t *buf,
+				int bytes)
+{
+	struct tcs_emul_data *data;
+	unsigned int c_ir;
+	int ret;
+
+	data = emul->data;
+
+	reg += bytes;
+
+	if ((reg < TCS_EMUL_FIRST_REG || reg > TCS_EMUL_LAST_REG) &&
+	    reg != TCS_I2C_IR) {
+		LOG_ERR("Accessing register 0x%x which cannot be read", reg);
+		return -EIO;
+	}
+
+	switch (reg) {
+	case TCS_I2C_CDATAL:
+		/* Shouldn't fail for LSB */
+		c_ir = data->ir_select ? data->ir : data->clear;
+		ret = tcs_emul_get_reg_val(emul, reg, &data->lsb_c_ir_read,
+					   true, c_ir);
+		break;
+	case TCS_I2C_CDATAH:
+		c_ir = data->ir_select ? data->ir : data->clear;
+		ret = tcs_emul_get_reg_val(emul, reg, &data->lsb_c_ir_read,
+					   false, c_ir);
+		if (ret) {
+			LOG_ERR("MSB C read before LSB C");
+			return -EIO;
+		}
+		break;
+	case TCS_I2C_RDATAL:
+		/* Shouldn't fail for LSB */
+		ret = tcs_emul_get_reg_val(emul, reg, &data->lsb_r_read, true,
+					   data->red);
+		break;
+	case TCS_I2C_RDATAH:
+		ret = tcs_emul_get_reg_val(emul, reg, &data->lsb_r_read, false,
+					   data->red);
+		if (ret) {
+			LOG_ERR("MSB R read before LSB R");
+			return -EIO;
+		}
+		break;
+	case TCS_I2C_GDATAL:
+		/* Shouldn't fail for LSB */
+		ret = tcs_emul_get_reg_val(emul, reg, &data->lsb_g_read, true,
+					   data->green);
+		break;
+	case TCS_I2C_GDATAH:
+		ret = tcs_emul_get_reg_val(emul, reg, &data->lsb_g_read, false,
+					   data->green);
+		if (ret) {
+			LOG_ERR("MSB G read before LSB G");
+			return -EIO;
+		}
+		break;
+	case TCS_I2C_BDATAL:
+		/* Shouldn't fail for LSB */
+		ret = tcs_emul_get_reg_val(emul, reg, &data->lsb_b_read, true,
+					   data->blue);
+		break;
+	case TCS_I2C_BDATAH:
+		ret = tcs_emul_get_reg_val(emul, reg, &data->lsb_b_read, false,
+					   data->blue);
+		if (ret) {
+			LOG_ERR("MSB B read before LSB B");
+			return -EIO;
+		}
+		break;
+	case TCS_I2C_IR:
+		*buf = data->ir_select ? BIT(7) : 0;
+
+		return 0;
+	}
+
+	*buf = data->reg[reg - TCS_EMUL_FIRST_REG];
+
+	return 0;
+}
+
+/**
+ * @brief Handle I2C write message. Check if message is not too long and saves
+ *        data that will be stored in register
+ *
+ * @param emul Pointer to TCS3400 emulator
+ * @param reg Register address that is accessed
+ * @param val Data to write to the register
+ * @param bytes Number of bytes already handled in this read message
+ *
+ * @return 0 on success
+ * @return -EIO on error
+ */
+static int tcs_emul_write_byte(const struct emul *emul, int reg, uint8_t val,
+			       int bytes)
+{
+	struct tcs_emul_data *data;
+
+	data = emul->data;
+
+	if (bytes > 1) {
+		LOG_ERR("Too long write command");
+		return -EIO;
+	}
+
+	data->write_byte = val;
+
+	return 0;
+}
+
+/* Device instantiation */
+
+/**
+ * @brief Set up a new TCS3400 emulator
+ *
+ * This should be called for each TCS3400 device that needs to be
+ * emulated. It registers it with the I2C emulation controller.
+ *
+ * @param emul Emulation information
+ * @param parent Device to emulate
+ *
+ * @return 0 indicating success (always)
+ */
+static int tcs_emul_init(const struct emul *emul, const struct device *parent)
+{
+	struct tcs_emul_data *data = emul->data;
+
+	data->common.i2c = parent;
+
+	i2c_common_emul_init(&data->common);
+
+	tcs_emul_reset(emul);
+
+	return 0;
+}
+
+#define TCS3400_EMUL(n)                                              \
+	static struct tcs_emul_data tcs_emul_data_##n = {		\
+		.revision = DT_INST_PROP(n, revision),			\
+		.id = DT_STRING_TOKEN(DT_DRV_INST(n), device_id),		\
+		.error_on_ro_write = DT_INST_PROP(n, error_on_ro_write),\
+		.error_on_rsvd_write = DT_INST_PROP(n,			\
+					error_on_reserved_bit_write),	\
+		.error_on_msb_first = DT_INST_PROP(n,			\
+					error_on_msb_first_access),	\
+		.lsb_c_ir_read = 0,					\
+		.lsb_r_read = 0,					\
+		.lsb_g_read = 0,					\
+		.lsb_b_read = 0,					\
+		.common = {						\
+			.start_write = NULL,				\
+			.write_byte = tcs_emul_write_byte,		\
+			.finish_write = tcs_emul_handle_write,		\
+			.start_read = NULL,				\
+			.read_byte = tcs_emul_handle_read,		\
+			.finish_read = NULL,				\
+			.access_reg = NULL,				\
+		},							\
+	};         \
+                                                                     \
+	static const struct i2c_common_emul_cfg tcs_emul_cfg_##n = { \
+		.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)),      \
+		.data = &tcs_emul_data_##n.common,                   \
+		.addr = DT_INST_REG_ADDR(n),                         \
+	};                                                           \
+	EMUL_DT_INST_DEFINE(n, tcs_emul_init, &tcs_emul_data_##n,    \
+			    &tcs_emul_cfg_##n, &i2c_common_emul_api, NULL)
+
+DT_INST_FOREACH_STATUS_OKAY(TCS3400_EMUL)
+
+#ifdef CONFIG_ZTEST_NEW_API
+#define TCS3400_EMUL_RESET_RULE_BEFORE(n) \
+	tcs_emul_reset(EMUL_DT_GET(DT_DRV_INST(n)));
+
+static void emul_tcs3400_reset_rule_before(const struct ztest_unit_test *test,
+					   void *data)
+{
+	ARG_UNUSED(test);
+	ARG_UNUSED(data);
+	DT_INST_FOREACH_STATUS_OKAY(TCS3400_EMUL_RESET_RULE_BEFORE);
+}
+ZTEST_RULE(emul_tcs3400_reset, emul_tcs3400_reset_rule_before, NULL);
+#endif /* CONFIG_ZTEST_NEW_API */
+
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
+
+struct i2c_common_emul_data *
+emul_tcs3400_get_i2c_common_data(const struct emul *emul)
+{
+	return emul->data;
+}
diff --git a/zephyr/emul/emul_tusb1064.c b/zephyr/emul/emul_tusb1064.c
new file mode 100644
index 0000000000..292fd8f4c6
--- /dev/null
+++ b/zephyr/emul/emul_tusb1064.c
@@ -0,0 +1,108 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/usb_mux/tusb1064.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_stub_device.h"
+#include "util.h"
+
+#include <zephyr/device.h>
+
+#define DT_DRV_COMPAT zephyr_tusb1064_emul
+
+#define TUSB1064_REG_MAX 255
+
+struct tusb1064_data {
+	struct i2c_common_emul_data common;
+	uint8_t regs[TUSB1064_REG_MAX + 1];
+};
+
+static const uint8_t default_values[TUSB1064_REG_MAX + 1] = {
+	[TUSB1064_REG_GENERAL] = 0x01,
+	[TUSB1064_REG_DP1DP3EQ_SEL] = 0x00,
+	[TUSB1064_REG_DP0DP2EQ_SEL] = 0x00,
+};
+
+void tusb1064_emul_reset_regs(const struct emul *emul)
+{
+	struct tusb1064_data *data = (struct tusb1064_data *)emul->data;
+
+	memcpy(data->regs, default_values, TUSB1064_REG_MAX + 1);
+}
+
+int tusb1064_emul_peek_reg(const struct emul *emul, int reg)
+{
+	struct tusb1064_data *data = (struct tusb1064_data *)emul->data;
+	uint8_t *regs = data->regs;
+
+	if (!IN_RANGE(reg, 0, TUSB1064_REG_MAX)) {
+		return -1;
+	}
+	return regs[reg];
+}
+
+static int tusb1064_emul_read(const struct emul *emul, int reg, uint8_t *val,
+			      int bytes, void *unused_data)
+{
+	struct tusb1064_data *data = (struct tusb1064_data *)emul->data;
+	uint8_t *regs = data->regs;
+	int pos = reg + bytes;
+
+	if (!IN_RANGE(pos, 0, TUSB1064_REG_MAX)) {
+		return -1;
+	}
+	*val = regs[pos];
+
+	return 0;
+}
+
+static int tusb1064_emul_write(const struct emul *emul, int reg, uint8_t val,
+			       int bytes, void *unused_data)
+{
+	struct tusb1064_data *data = (struct tusb1064_data *)emul->data;
+	uint8_t *regs = data->regs;
+	int pos = reg + bytes - 1;
+
+	if (!IN_RANGE(pos, 0, TUSB1064_REG_MAX) ||
+	    !IN_RANGE(val, 0, UINT8_MAX)) {
+		return -1;
+	}
+	regs[pos] = val;
+
+	return 0;
+}
+
+static int tusb1064_emul_init(const struct emul *emul,
+			      const struct device *parent)
+{
+	struct tusb1064_data *data = (struct tusb1064_data *)emul->data;
+	struct i2c_common_emul_data *common_data = &data->common;
+
+	i2c_common_emul_init(common_data);
+	i2c_common_emul_set_read_func(common_data, tusb1064_emul_read, NULL);
+	i2c_common_emul_set_write_func(common_data, tusb1064_emul_write, NULL);
+
+	tusb1064_emul_reset_regs(emul);
+
+	return 0;
+}
+
+#define INIT_TUSB1064_EMUL(n)                                          \
+	static struct i2c_common_emul_cfg common_cfg_##n;              \
+	static struct tusb1064_data tusb1064_data_##n;                 \
+	static struct i2c_common_emul_cfg common_cfg_##n = {           \
+		.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)),        \
+		.data = &tusb1064_data_##n.common,                     \
+		.addr = DT_INST_REG_ADDR(n)                            \
+	};                                                             \
+	static struct tusb1064_data tusb1064_data_##n = {              \
+		.common = { .cfg = &common_cfg_##n }                   \
+	};                                                             \
+	EMUL_DT_INST_DEFINE(n, tusb1064_emul_init, &tusb1064_data_##n, \
+			    &common_cfg_##n, &i2c_common_emul_api, NULL)
+
+DT_INST_FOREACH_STATUS_OKAY(INIT_TUSB1064_EMUL)
+
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
diff --git a/zephyr/emul/i2c_mock.c b/zephyr/emul/i2c_mock.c
new file mode 100644
index 0000000000..cb5d7fc729
--- /dev/null
+++ b/zephyr/emul/i2c_mock.c
@@ -0,0 +1,76 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_stub_device.h"
+
+#include <zephyr/device.h>
+#include <zephyr/logging/log.h>
+
+#define DT_DRV_COMPAT cros_i2c_mock
+
+LOG_MODULE_REGISTER(i2c_mock, CONFIG_I2C_MOCK_LOG_LEVEL);
+
+struct i2c_emul *i2c_mock_to_i2c_emul(const struct emul *emul)
+{
+	struct i2c_common_emul_data *data = emul->data;
+
+	return &(data->emul);
+}
+
+void i2c_mock_reset(const struct emul *emul)
+{
+	i2c_common_emul_set_read_fail_reg(emul->data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(emul->data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_func(emul->data, NULL, NULL);
+	i2c_common_emul_set_write_func(emul->data, NULL, NULL);
+}
+
+uint16_t i2c_mock_get_addr(const struct emul *emul)
+{
+	const struct i2c_common_emul_cfg *cfg = emul->cfg;
+
+	return cfg->addr;
+}
+
+static const struct i2c_emul_api i2c_mock_api = {
+	.transfer = i2c_common_emul_transfer,
+};
+
+static int i2c_mock_init(const struct emul *emul, const struct device *parent)
+{
+	const struct i2c_common_emul_cfg *cfg = emul->cfg;
+	struct i2c_common_emul_data *data = emul->data;
+
+	data->emul.api = &i2c_mock_api;
+	data->emul.addr = cfg->addr;
+	data->emul.target = emul;
+	data->i2c = parent;
+	data->cfg = cfg;
+	i2c_common_emul_init(data);
+
+	return 0;
+}
+
+#define INIT_I2C_MOCK(n)                                             \
+	static const struct i2c_common_emul_cfg i2c_mock_cfg_##n = { \
+		.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)),      \
+		.addr = DT_INST_REG_ADDR(n),                         \
+	};                                                           \
+	static struct i2c_common_emul_data i2c_mock_data_##n;        \
+	EMUL_DT_INST_DEFINE(n, i2c_mock_init, &i2c_mock_data_##n,    \
+			    &i2c_mock_cfg_##n, &i2c_common_emul_api, NULL)
+
+DT_INST_FOREACH_STATUS_OKAY(INIT_I2C_MOCK)
+
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
+
+struct i2c_common_emul_data *
+emul_i2c_mock_get_i2c_common_data(const struct emul *emul)
+{
+	return emul->data;
+}
diff --git a/zephyr/emul/include/flash_chip_native_posix.h b/zephyr/emul/include/flash_chip_native_posix.h
new file mode 100644
index 0000000000..88157f6c29
--- /dev/null
+++ b/zephyr/emul/include/flash_chip_native_posix.h
@@ -0,0 +1,17 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __EMUL_INCLUDE_FLASH_CHIP_H
+#define __EMUL_INCLUDE_FLASH_CHIP_H
+
+#define CONFIG_RO_STORAGE_OFF 0x0
+#define CONFIG_RW_STORAGE_OFF 0x0
+#define CONFIG_FLASH_WRITE_SIZE 0x1 /* minimum write size */
+#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* one page size for write */
+#define CONFIG_FLASH_ERASE_SIZE \
+	DT_PROP(DT_INST(0, soc_nv_flash), erase_block_size)
+#define CONFIG_FLASH_BANK_SIZE CONFIG_FLASH_ERASE_SIZE
+
+#endif /* __EMUL_INCLUDE_FLASH_CHIP_H */
diff --git a/zephyr/emul/include/pwm_mock.h b/zephyr/emul/include/pwm_mock.h
new file mode 100644
index 0000000000..7f5eb9eb89
--- /dev/null
+++ b/zephyr/emul/include/pwm_mock.h
@@ -0,0 +1,33 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __EMUL_INCLUDE_PWM_MOCK_H
+#define __EMUL_INCLUDE_PWM_MOCK_H
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/pwm.h>
+
+/*
+ * Get pwm duty cycle
+ *
+ * @param dev		pointer to hte pwm device
+ * @param channel	channel id
+ *
+ * @return duty		duty cycle in range [0, 100] or negative on error.
+ */
+int pwm_mock_get_duty(const struct device *dev, uint32_t channel);
+
+/**
+ * @brief Get the flags the PWM driver was set with. See the following header
+ *        in upstream Zephyr for possible values:
+ *        `include/zephyr/dt-bindings/pwm/pwm.h`
+ *
+ * @param dev Pointer to PWM device
+ * @param channel Unused
+ * @return pwm_flags_t PWM flags
+ */
+pwm_flags_t pwm_mock_get_flags(const struct device *dev, uint32_t channel);
+
+#endif /*__EMUL_INCLUDE_PWM_MOCK_H */
diff --git a/zephyr/emul/include/vcmp_mock.h b/zephyr/emul/include/vcmp_mock.h
new file mode 100644
index 0000000000..5444b0aeab
--- /dev/null
+++ b/zephyr/emul/include/vcmp_mock.h
@@ -0,0 +1,18 @@
+/* Copyright 2022 Google LLC
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __EMUL_INCLUDE_VCMP_MOCK_H
+#define __EMUL_INCLUDE_VCMP_MOCK_H
+
+#include <zephyr/device.h>
+
+/*
+ * Manually trigger the vcmp handler
+ *
+ * @param dev pointer to the vcmp emulator device
+ */
+void vcmp_mock_trigger(const struct device *dev);
+
+#endif /*__EMUL_INCLUDE_VCMP_MOCK_H */
diff --git a/zephyr/emul/pwm_mock.c b/zephyr/emul/pwm_mock.c
new file mode 100644
index 0000000000..26f7891cb8
--- /dev/null
+++ b/zephyr/emul/pwm_mock.c
@@ -0,0 +1,80 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "pwm_mock.h"
+
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/pwm.h>
+#include <zephyr/kernel.h>
+
+#define DT_DRV_COMPAT cros_pwm_mock
+
+#define CYCLES_PER_SEC 1000000
+
+struct pwm_mock_data {
+	uint32_t period_cycles;
+	uint32_t pulse_cycles;
+	pwm_flags_t pwm_flags;
+};
+
+static int pwm_mock_init(const struct device *dev)
+{
+	return 0;
+}
+
+static int pwm_mock_set_cycles(const struct device *dev, uint32_t channel,
+			       uint32_t period_cycles, uint32_t pulse_cycles,
+			       pwm_flags_t flags)
+{
+	struct pwm_mock_data *const data = dev->data;
+
+	data->period_cycles = period_cycles;
+	data->pulse_cycles = pulse_cycles;
+	data->pwm_flags = flags;
+
+	return 0;
+}
+
+static int pwm_mock_get_cycles_per_sec(const struct device *dev,
+				       uint32_t channel, uint64_t *cycles)
+{
+	*cycles = CYCLES_PER_SEC;
+
+	return 0;
+}
+
+int pwm_mock_get_duty(const struct device *dev, uint32_t channel)
+{
+	struct pwm_mock_data *const data = dev->data;
+
+	if (data->period_cycles == 0) {
+		return -EINVAL;
+	}
+
+	return data->pulse_cycles * 100 / data->period_cycles;
+}
+
+pwm_flags_t pwm_mock_get_flags(const struct device *dev, uint32_t channel)
+{
+	ARG_UNUSED(channel);
+
+	struct pwm_mock_data *const data = dev->data;
+
+	return data->pwm_flags;
+}
+
+static const struct pwm_driver_api pwm_mock_api = {
+	.set_cycles = pwm_mock_set_cycles,
+	.get_cycles_per_sec = pwm_mock_get_cycles_per_sec,
+};
+
+#define INIT_PWM_MOCK(inst)                                             \
+	static struct pwm_mock_data pwm_mock_data##inst;                \
+	DEVICE_DT_INST_DEFINE(inst, &pwm_mock_init, NULL,               \
+			      &pwm_mock_data##inst, NULL, PRE_KERNEL_1, \
+			      CONFIG_KERNEL_INIT_PRIORITY_DEVICE,       \
+			      &pwm_mock_api);
+DT_INST_FOREACH_STATUS_OKAY(INIT_PWM_MOCK)
diff --git a/zephyr/emul/retimer/CMakeLists.txt b/zephyr/emul/retimer/CMakeLists.txt
new file mode 100644
index 0000000000..33af461d1d
--- /dev/null
+++ b/zephyr/emul/retimer/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+zephyr_library_sources_ifdef(CONFIG_EMUL_ANX7483 emul_anx7483.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_PS8811 emul_ps8811.c)
\ No newline at end of file
diff --git a/zephyr/emul/retimer/Kconfig b/zephyr/emul/retimer/Kconfig
new file mode 100644
index 0000000000..e37470771f
--- /dev/null
+++ b/zephyr/emul/retimer/Kconfig
@@ -0,0 +1,21 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config EMUL_ANX7483
+	bool "ANX7483 Emulator"
+	depends on DT_HAS_CROS_ANX7483_EMUL_ENABLED
+	default y
+	help
+	  Enable emulator for ANX7483 retimer.
+
+config EMUL_PS8811
+	bool "Parade PS8811 Emulator"
+	depends on DT_HAS_CROS_PS8811_EMUL_ENABLED
+	default y
+	help
+	  Enable emulator for PS8811 retimer.
+
+config RETIMER_EMUL_LOG_LEVEL
+	int "Retimer emulator log level"
+	default 3 # Log level info
\ No newline at end of file
diff --git a/zephyr/emul/retimer/emul_anx7483.c b/zephyr/emul/retimer/emul_anx7483.c
new file mode 100644
index 0000000000..13c6e39d43
--- /dev/null
+++ b/zephyr/emul/retimer/emul_anx7483.c
@@ -0,0 +1,402 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "driver/retimer/anx7483.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_stub_device.h"
+#include "emul/retimer/emul_anx7483.h"
+
+#include <zephyr/logging/log.h>
+#include <zephyr/ztest.h>
+
+LOG_MODULE_REGISTER(anx7483_emul, CONFIG_RETIMER_EMUL_LOG_LEVEL);
+
+#define DT_DRV_COMPAT cros_anx7483_emul
+
+static const struct anx7483_register default_reg_configs[ANX7483_REG_MAX] = {
+	{
+		.reg = ANX7483_LFPS_TIMER_REG,
+		.def = ANX7483_LFPS_TIMER_REG_DEFAULT,
+		.reserved = ANX7483_LFPS_TIMER_REG_RESERVED_MASK,
+	},
+	{
+		.reg = ANX7483_ANALOG_STATUS_CTRL_REG,
+		.def = ANX7483_ANALOG_STATUS_CTRL_REG_DEFAULT,
+		.reserved = ANX7483_ANALOG_STATUS_CTRL_REG_RESERVED_MASK,
+	},
+	{
+		.reg = ANX7483_ENABLE_EQ_FLAT_SWING_REG,
+		.def = ANX7483_ENABLE_EQ_FLAT_SWING_REG_DEFAULT,
+		.reserved = ANX7483_ENABLE_EQ_FLAT_SWING_REG_RESERVED_MASK,
+	},
+	{
+		.reg = ANX7483_AUX_SNOOPING_CTRL_REG,
+		.def = ANX7483_AUX_SNOOPING_CTRL_REG_DEFAULT,
+		.reserved = ANX7483_AUX_SNOOPING_CTRL_REG_RESERVED_MASK,
+	},
+
+	/* CFG0 */
+	{
+		.reg = ANX7483_UTX1_PORT_CFG0_REG,
+		.def = ANX7483_UTX1_PORT_CFG0_REG_DEFAULT,
+		.reserved = ANX7483_UTX1_PORT_CFG0_REG_RESERVED_MASK,
+	},
+	{
+		.reg = ANX7483_UTX2_PORT_CFG0_REG,
+		.def = ANX7483_UTX2_PORT_CFG0_REG_DEFAULT,
+		.reserved = ANX7483_UTX2_PORT_CFG0_REG_RESERVED_MASK,
+	},
+	{
+		.reg = ANX7483_URX1_PORT_CFG0_REG,
+		.def = ANX7483_URX1_PORT_CFG0_REG_DEFAULT,
+		.reserved = ANX7483_URX1_PORT_CFG0_REG_RESERVED_MASK,
+	},
+	{
+		.reg = ANX7483_URX2_PORT_CFG0_REG,
+		.def = ANX7483_URX2_PORT_CFG0_REG_DEFAULT,
+		.reserved = ANX7483_URX2_PORT_CFG0_REG_RESERVED_MASK,
+	},
+	{
+		.reg = ANX7483_DRX1_PORT_CFG0_REG,
+		.def = ANX7483_DRX1_PORT_CFG0_REG_DEFAULT,
+		.reserved = ANX7483_DRX1_PORT_CFG0_REG_RESERVED_MASK,
+	},
+	{
+		.reg = ANX7483_DRX2_PORT_CFG0_REG,
+		.def = ANX7483_DRX2_PORT_CFG0_REG_DEFAULT,
+		.reserved = ANX7483_DRX2_PORT_CFG0_REG_RESERVED_MASK,
+	},
+
+	/* CFG1 */
+	{
+		.reg = ANX7483_UTX1_PORT_CFG1_REG,
+		.def = ANX7483_UTX1_PORT_CFG1_REG_DEFAULT,
+	},
+	{
+		.reg = ANX7483_UTX2_PORT_CFG1_REG,
+		.def = ANX7483_UTX2_PORT_CFG1_REG_DEFAULT,
+	},
+	{
+		.reg = ANX7483_URX1_PORT_CFG1_REG,
+		.def = ANX7483_URX1_PORT_CFG1_REG_DEFAULT,
+	},
+	{
+		.reg = ANX7483_URX2_PORT_CFG1_REG,
+		.def = ANX7483_URX2_PORT_CFG1_REG_DEFAULT,
+	},
+	{
+		.reg = ANX7483_DRX1_PORT_CFG1_REG,
+		.def = ANX7483_DRX1_PORT_CFG1_REG_DEFAULT,
+	},
+	{
+		.reg = ANX7483_DRX2_PORT_CFG1_REG,
+		.def = ANX7483_DRX2_PORT_CFG1_REG_DEFAULT,
+	},
+
+	/* CFG2 */
+	{
+		.reg = ANX7483_UTX1_PORT_CFG2_REG,
+		.def = ANX7483_UTX1_PORT_CFG2_REG_DEFAULT,
+		.reserved = ANX7483_UTX1_PORT_CFG2_REG_RESERVED_MASK,
+	},
+	{
+		.reg = ANX7483_UTX2_PORT_CFG2_REG,
+		.def = ANX7483_UTX2_PORT_CFG2_REG_DEFAULT,
+		.reserved = ANX7483_UTX2_PORT_CFG2_REG_RESERVED_MASK,
+	},
+	{
+		.reg = ANX7483_URX1_PORT_CFG2_REG,
+		.def = ANX7483_URX1_PORT_CFG2_REG_DEFAULT,
+		.reserved = ANX7483_URX1_PORT_CFG2_REG_RESERVED_MASK,
+	},
+	{
+		.reg = ANX7483_URX2_PORT_CFG2_REG,
+		.def = ANX7483_URX2_PORT_CFG2_REG_DEFAULT,
+		.reserved = ANX7483_URX2_PORT_CFG2_REG_RESERVED_MASK,
+	},
+	{
+		.reg = ANX7483_DRX1_PORT_CFG2_REG,
+		.def = ANX7483_DRX1_PORT_CFG2_REG_DEFAULT,
+		.reserved = ANX7483_DRX1_PORT_CFG2_REG_RESERVED_MASK,
+	},
+	{
+		.reg = ANX7483_DRX2_PORT_CFG2_REG,
+		.def = ANX7483_DRX2_PORT_CFG2_REG_DEFAULT,
+		.reserved = ANX7483_DRX2_PORT_CFG2_REG_RESERVED_MASK,
+	},
+
+	/* CFG3 */
+	{
+		.reg = ANX7483_UTX1_PORT_CFG3_REG,
+		.def = ANX7483_UTX1_PORT_CFG3_REG_DEFAULT,
+	},
+	{
+		.reg = ANX7483_UTX2_PORT_CFG3_REG,
+		.def = ANX7483_UTX2_PORT_CFG3_REG_DEFAULT,
+	},
+	{
+		.reg = ANX7483_URX1_PORT_CFG3_REG,
+		.def = ANX7483_URX1_PORT_CFG3_REG_DEFAULT,
+	},
+	{
+		.reg = ANX7483_URX2_PORT_CFG3_REG,
+		.def = ANX7483_URX2_PORT_CFG3_REG_DEFAULT,
+	},
+	{
+		.reg = ANX7483_DRX1_PORT_CFG3_REG,
+		.def = ANX7483_DRX1_PORT_CFG3_REG_DEFAULT,
+	},
+	{
+		.reg = ANX7483_DRX2_PORT_CFG3_REG,
+		.def = ANX7483_DRX2_PORT_CFG3_REG_DEFAULT,
+	},
+	{
+		.reg = ANX7483_DTX1_PORT_CFG3_REG,
+		.def = ANX7483_DTX1_PORT_CFG3_REG_DEFAULT,
+	},
+	{
+		.reg = ANX7483_DTX2_PORT_CFG3_REG,
+		.def = ANX7483_DTX2_PORT_CFG3_REG_DEFAULT,
+	},
+
+	/* CFG4 */
+	{
+		.reg = ANX7483_UTX1_PORT_CFG4_REG,
+		.def = ANX7483_UTX1_PORT_CFG4_REG_DEFAULT,
+		.reserved = ANX7483_UTX1_PORT_CFG4_REG_RESERVED_MASK,
+	},
+	{
+		.reg = ANX7483_UTX2_PORT_CFG4_REG,
+		.def = ANX7483_UTX2_PORT_CFG4_REG_DEFAULT,
+		.reserved = ANX7483_UTX2_PORT_CFG4_REG_RESERVED_MASK,
+	},
+	{
+		.reg = ANX7483_URX1_PORT_CFG4_REG,
+		.def = ANX7483_URX1_PORT_CFG4_REG_DEFAULT,
+		.reserved = ANX7483_URX1_PORT_CFG4_REG_RESERVED_MASK,
+	},
+	{
+		.reg = ANX7483_URX2_PORT_CFG4_REG,
+		.def = ANX7483_URX2_PORT_CFG4_REG_DEFAULT,
+		.reserved = ANX7483_URX2_PORT_CFG4_REG_RESERVED_MASK,
+	},
+	{
+		.reg = ANX7483_DRX1_PORT_CFG4_REG,
+		.def = ANX7483_DRX1_PORT_CFG4_REG_DEFAULT,
+		.reserved = ANX7483_DRX1_PORT_CFG4_REG_RESERVED_MASK,
+	},
+	{
+		.reg = ANX7483_DRX2_PORT_CFG4_REG,
+		.def = ANX7483_DRX2_PORT_CFG4_REG_DEFAULT,
+		.reserved = ANX7483_DRX2_PORT_CFG4_REG_RESERVED_MASK,
+	},
+	{
+		.reg = ANX7483_DTX1_PORT_CFG4_REG,
+		.def = ANX7483_DTX1_PORT_CFG4_REG_DEFAULT,
+		.reserved = ANX7483_DTX1_PORT_CFG4_REG_RESERVED_MASK,
+	},
+	{
+		.reg = ANX7483_DTX2_PORT_CFG4_REG,
+		.def = ANX7483_DTX2_PORT_CFG4_REG_DEFAULT,
+		.reserved = ANX7483_DTX2_PORT_CFG4_REG_RESERVED_MASK,
+	},
+
+};
+
+static int anx7483_emul_read_byte(const struct emul *emul, int reg,
+				  uint8_t *val, int byte)
+{
+	/* Registers are only one byte. */
+	if (byte != 0)
+		return -EIO;
+
+	return (anx7483_emul_get_reg(emul, reg, val) == 0) ? 0 : -EIO;
+}
+
+static int anx7483_emul_write_byte(const struct emul *emul, int reg,
+				   uint8_t val, int bytes)
+{
+	/* Registers are only one byte. */
+	if (bytes != 1)
+		return -EIO;
+	return (anx7483_emul_set_reg(emul, reg, val) == 0) ? 0 : -EIO;
+}
+
+static struct anx7483_register *get_register_mut(const struct emul *emul,
+						 int reg)
+{
+	struct anx7483_emul_data *anx7483 = emul->data;
+
+	for (size_t i = 0; i < ANX7483_REG_MAX; i++) {
+		if (anx7483->regs[i].reg == reg)
+			return &anx7483->regs[i];
+	}
+
+	return NULL;
+}
+
+static const struct anx7483_register *
+get_register_const(const struct emul *emul, int reg)
+{
+	return get_register_mut(emul, reg);
+}
+
+int anx7483_emul_get_reg(const struct emul *emul, int r, uint8_t *val)
+{
+	const struct anx7483_register *reg = get_register_const(emul, r);
+
+	if (!reg) {
+		LOG_DBG("Unknown register %x", r);
+		return -EINVAL;
+	}
+
+	*val = reg->value;
+	return 0;
+}
+
+int anx7483_emul_set_reg(const struct emul *emul, int r, uint8_t val)
+{
+	struct anx7483_register *reg = get_register_mut(emul, r);
+
+	if (!reg) {
+		LOG_DBG("Unknown register %x", r);
+		return -EINVAL;
+	}
+
+	if ((val & reg->reserved) != (reg->def & reg->reserved)) {
+		LOG_DBG("Reserved bits modified for reg %02x, val: %02x, \
+			default: %02x, reserved: %02x",
+			r, val, reg->def, reg->reserved);
+		return -EINVAL;
+	}
+
+	reg->value = val;
+	return 0;
+}
+
+int anx7483_emul_set_reg_reserved_mask(const struct emul *emul, int r,
+				       uint8_t mask, uint8_t def)
+{
+	struct anx7483_register *reg = get_register_mut(emul, r);
+
+	if (!reg) {
+		LOG_DBG("Unknown register %x", r);
+		return -EINVAL;
+	}
+
+	LOG_DBG("Overwriting reserved mask value for reg: %02x from %x to %x",
+		r, reg->reserved, mask);
+	reg->reserved = mask;
+	reg->def = def;
+	return 0;
+}
+
+int anx7483_emul_get_eq(const struct emul *emul, enum anx7483_tune_pin pin,
+			enum anx7483_eq_setting *eq)
+{
+	int reg;
+	int rv;
+
+	if (pin == ANX7483_PIN_UTX1)
+		reg = ANX7483_UTX1_PORT_CFG0_REG;
+	else if (pin == ANX7483_PIN_UTX2)
+		reg = ANX7483_UTX2_PORT_CFG0_REG;
+	else if (pin == ANX7483_PIN_URX1)
+		reg = ANX7483_URX1_PORT_CFG0_REG;
+	else if (pin == ANX7483_PIN_URX2)
+		reg = ANX7483_URX2_PORT_CFG0_REG;
+	else if (pin == ANX7483_PIN_DRX1)
+		reg = ANX7483_DRX1_PORT_CFG0_REG;
+	else if (pin == ANX7483_PIN_DRX2)
+		reg = ANX7483_DRX2_PORT_CFG0_REG;
+	else
+		return EC_ERROR_INVAL;
+
+	rv = anx7483_emul_get_reg(emul, reg, (uint8_t *)eq);
+	if (rv)
+		return rv;
+
+	*eq &= ANX7483_CFG0_EQ_MASK;
+	*eq >>= ANX7483_CFG0_EQ_SHIFT;
+
+	return EC_SUCCESS;
+}
+
+void anx7483_emul_reset(const struct emul *emul)
+{
+	struct anx7483_emul_data *anx7483 = emul->data;
+
+	/* Initialize our default register config. */
+	memcpy(&anx7483->regs, default_reg_configs,
+	       ANX7483_REG_MAX * sizeof(struct anx7483_register));
+
+	/* Using the setter helps catch any default misconfigs. */
+	for (size_t i = 0; i < ANX7483_REG_MAX; i++)
+		anx7483_emul_set_reg(emul, anx7483->regs[i].reg,
+				     anx7483->regs[i].def);
+}
+
+int anx7483_emul_validate_tuning(const struct emul *emul,
+				 const struct anx7483_tuning_set *tuning,
+				 size_t tuning_count)
+{
+	uint8_t val;
+	int rv;
+
+	for (size_t i = 0; i < tuning_count; i++) {
+		rv = anx7483_emul_get_reg(emul, tuning[i].addr, &val);
+		if (rv)
+			return rv;
+
+		if (val != tuning[i].value)
+			return 1;
+	}
+
+	return 0;
+}
+
+static int anx7483_emul_init(const struct emul *emul,
+			     const struct device *parent)
+{
+	struct anx7483_emul_data *anx7483 = emul->data;
+
+	anx7483_emul_reset(emul);
+	i2c_common_emul_init(&anx7483->common);
+
+	return 0;
+}
+
+#define ANX7483_EMUL_RESET_RULE_AFTER(n) \
+	anx7483_emul_reset(EMUL_DT_GET(DT_DRV_INST(n)));
+
+static void anx7483_emul_test_reset(const struct ztest_unit_test *test,
+				    void *data)
+{
+	ARG_UNUSED(test);
+	ARG_UNUSED(data);
+
+	DT_INST_FOREACH_STATUS_OKAY(ANX7483_EMUL_RESET_RULE_AFTER)
+}
+
+ZTEST_RULE(emul_anx7483_reset, NULL, anx7483_emul_test_reset);
+
+#define ANX7483_EMUL(n)                                                   \
+	static struct anx7483_emul_data anx7483_emul_data_##n = { \
+		.common = { \
+			.read_byte = anx7483_emul_read_byte, \
+			.write_byte = anx7483_emul_write_byte, \
+		}, \
+	};       \
+	static const struct anx7483_emul_cfg anx7483_emul_cfg_##n = { \
+		.common = { \
+			.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)), \
+			.data = &anx7483_emul_data_##n.common, \
+			.addr = DT_INST_REG_ADDR(n), \
+		}, \
+	};   \
+	EMUL_DT_INST_DEFINE(n, anx7483_emul_init, &anx7483_emul_data_##n, \
+			    &anx7483_emul_cfg_##n, &i2c_common_emul_api, NULL)
+
+DT_INST_FOREACH_STATUS_OKAY(ANX7483_EMUL)
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE)
diff --git a/zephyr/emul/retimer/emul_ps8811.c b/zephyr/emul/retimer/emul_ps8811.c
new file mode 100644
index 0000000000..cebb256f66
--- /dev/null
+++ b/zephyr/emul/retimer/emul_ps8811.c
@@ -0,0 +1,271 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/retimer/ps8811.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_stub_device.h"
+#include "emul/retimer/emul_ps8811.h"
+
+#include <zephyr/logging/log.h>
+#include <zephyr/ztest.h>
+
+LOG_MODULE_REGISTER(ps8811_emul, CONFIG_RETIMER_EMUL_LOG_LEVEL);
+
+#define DT_DRV_COMPAT cros_ps8811_emul
+
+struct register_config {
+	uint8_t reg;
+	uint8_t def;
+	uint8_t reserved;
+};
+
+static const struct register_config register_configs[] = {
+	{
+		.reg = PS8811_REG1_USB_AEQ_LEVEL,
+		.def = PS8811_REG1_USB_AEQ_LEVEL_DEFAULT,
+	},
+	{
+		.reg = PS8811_REG1_USB_ADE_CONFIG,
+		.def = PS8811_REG1_USB_ADE_CONFIG_DEFAULT,
+	},
+	{
+		.reg = PS8811_REG1_USB_BEQ_LEVEL,
+		.def = PS8811_REG1_USB_BEQ_LEVEL_DEFAULT,
+	},
+	{
+		.reg = PS8811_REG1_USB_BDE_CONFIG,
+		.def = PS8811_REG1_USB_BDE_CONFIG_DEFAULT,
+	},
+	{
+		.reg = PS8811_REG1_USB_CHAN_A_SWING,
+		.def = PS8811_REG1_USB_CHAN_A_SWING_DEFAULT,
+		.reserved = PS8811_REG1_USB_CHAN_A_SWING_RESERVED_MASK,
+	},
+	{
+		.reg = PS8811_REG1_50OHM_ADJUST_CHAN_B,
+		.def = PS8811_REG1_50OHM_ADJUST_CHAN_B_DEFAULT,
+		.reserved = PS8811_REG1_50OHM_ADJUST_CHAN_B_RESERVED_MASK,
+	},
+	{
+		.reg = PS8811_REG1_USB_CHAN_B_SWING,
+		.def = PS8811_REG1_USB_CHAN_B_SWING_DEFAULT,
+		.reserved = PS8811_REG1_USB_CHAN_B_SWING_RESERVED_MASK,
+	},
+	{
+		.reg = PS8811_REG1_USB_CHAN_B_DE_PS_LSB,
+		.def = PS8811_REG1_USB_CHAN_B_DE_PS_LSB_DEFAULT,
+		.reserved = PS8811_REG1_USB_CHAN_B_DE_PS_LSB_RESERVED_MASK,
+	},
+	{
+		.reg = PS8811_REG1_USB_CHAN_B_DE_PS_MSB,
+		.def = PS8811_REG1_USB_CHAN_B_DE_PS_MSB_DEFAULT,
+		.reserved = PS8811_REG1_USB_CHAN_B_DE_PS_MSB_RESERVED_MASK,
+	},
+};
+
+static int ps8811_emul_p1_read_byte(const struct emul *emul, int reg,
+				    uint8_t *val, int byte)
+{
+	/* register_configs are all one byte. */
+	if (byte != 0)
+		return -EIO;
+
+	return (ps8811_emul_get_reg1(emul, reg, val) == 0) ? 0 : -EIO;
+}
+
+static int ps8811_emul_p1_write_byte(const struct emul *emul, int reg,
+				     uint8_t val, int bytes)
+{
+	/* register_configs are all one byte. */
+	if (bytes != 1)
+		return -EIO;
+
+	return (ps8811_emul_set_reg1(emul, reg, val) == 0) ? 0 : -EIO;
+}
+
+static int ps8811_emul_p0_read_byte(const struct emul *emul, int reg,
+				    uint8_t *val, int byte)
+{
+	return (ps8811_emul_get_reg0(emul, reg, val) == 0) ? 0 : -EIO;
+}
+
+static int ps8811_emul_p0_write_byte(const struct emul *emul, int reg,
+				     uint8_t val, int bytes)
+{
+	return (ps8811_emul_set_reg0(emul, reg, val) == 0) ? 0 : -EIO;
+}
+
+static int i2c_ps8811_emul_transfer(const struct emul *target,
+				    struct i2c_msg *msgs, int num_msgs,
+				    int addr)
+{
+	struct ps8811_emul_data *data = target->data;
+	const struct ps8811_emul_cfg *cfg = target->cfg;
+
+	if (addr == target->bus.i2c->addr) {
+		return i2c_common_emul_transfer_workhorse(target, target->data,
+							  target->cfg, msgs,
+							  num_msgs, addr);
+	} else if (addr == data->p1_data.emul.addr) {
+		return i2c_common_emul_transfer_workhorse(target,
+							  &data->p1_data,
+							  &cfg->p1_cfg, msgs,
+							  num_msgs, addr);
+	}
+
+	LOG_ERR("Cannot map address %02x", addr);
+	return -EIO;
+}
+
+struct i2c_emul_api i2c_ps8811_emul_api = {
+	.transfer = i2c_ps8811_emul_transfer,
+};
+
+static int ps8811_emul_init(const struct emul *emul,
+			    const struct device *parent)
+{
+	struct ps8811_emul_data *data = emul->data;
+	const struct ps8811_emul_cfg *cfg = emul->cfg;
+	int rv = 0;
+
+	ps8811_emul_reset(emul);
+
+	i2c_common_emul_init(&data->p0_data);
+
+	data->p1_data.emul.api = &i2c_ps8811_emul_api;
+	data->p1_data.emul.addr = cfg->p1_cfg.addr;
+	data->p1_data.emul.target = emul;
+	data->p1_data.i2c = parent;
+	data->p1_data.cfg = &cfg->p1_cfg;
+	i2c_common_emul_init(&data->p1_data);
+
+	rv = i2c_emul_register(parent, &data->p1_data.emul);
+	if (rv) {
+		LOG_ERR("Failed to register page 1 register emulator");
+		return rv;
+	}
+
+	return 0;
+}
+
+/*
+ * Page 0 contains hardware revision and similar info. No code currently
+ * accesses these register_configs so just stub them out for future use.
+ */
+int ps8811_emul_get_reg0(const struct emul *emulator, int reg, uint8_t *val)
+{
+	return -EINVAL;
+}
+
+int ps8811_emul_set_reg0(const struct emul *emulator, int reg, uint8_t val)
+{
+	return -EINVAL;
+}
+
+static const struct register_config *get_reg1_config(int reg)
+{
+	for (size_t i = 0; i < ARRAY_SIZE(register_configs); i++) {
+		if (register_configs[i].reg == reg)
+			return &register_configs[i];
+	}
+
+	return NULL;
+}
+
+int ps8811_emul_get_reg1(const struct emul *emulator, int reg, uint8_t *val)
+{
+	struct ps8811_emul_data *ps8811 = emulator->data;
+
+	if (reg >= ARRAY_SIZE(ps8811->p1_regs)) {
+		LOG_DBG("Register %x is out of bounds");
+		return -EINVAL;
+	}
+
+	if (!get_reg1_config(reg)) {
+		LOG_DBG("Unknown register %x", reg);
+		return -EINVAL;
+	}
+
+	*val = ps8811->p1_regs[reg];
+	return 0;
+}
+
+int ps8811_emul_set_reg1(const struct emul *emulator, int reg, uint8_t val)
+{
+	struct ps8811_emul_data *ps8811 = emulator->data;
+	const struct register_config *config = get_reg1_config(reg);
+
+	if (reg >= ARRAY_SIZE(ps8811->p1_regs)) {
+		LOG_DBG("Register %x is out of bounds");
+		return -EINVAL;
+	}
+
+	if (!config) {
+		LOG_DBG("Unknown register %x", reg);
+		return -EINVAL;
+	}
+
+	/* Validate that we're not touching reserved bits. */
+	if ((val & config->reserved) != (config->def & config->reserved)) {
+		LOG_DBG("Reserved bits modified for reg %02x, val: %02x, \
+			default: %02x, reserved: %02x",
+			reg, val, config->def, config->reserved);
+		return -EINVAL;
+	}
+
+	ps8811->p1_regs[reg] = val;
+	return 0;
+}
+
+void ps8811_emul_reset(const struct emul *emul)
+{
+	/* Use the setter helps catch any default misconfigs. */
+	for (size_t i = 0; i < ARRAY_SIZE(register_configs); i++)
+		ps8811_emul_set_reg1(emul, register_configs[i].reg,
+				     register_configs[i].def);
+}
+
+#define PS8811_EMUL_RESET_RULE_AFTER(n) \
+	ps8811_emul_reset(EMUL_DT_GET(DT_DRV_INST(n)));
+
+static void ps8811_emul_test_reset(const struct ztest_unit_test *test,
+				   void *data)
+{
+	ARG_UNUSED(test);
+	ARG_UNUSED(data);
+
+	DT_INST_FOREACH_STATUS_OKAY(PS8811_EMUL_RESET_RULE_AFTER)
+}
+
+ZTEST_RULE(emul_ps8811_reset, NULL, ps8811_emul_test_reset);
+
+#define PS8811_EMUL(n)                                                  \
+	static struct ps8811_emul_data ps8811_emul_data_##n = { \
+		.p0_data = { \
+			.read_byte = ps8811_emul_p0_read_byte, \
+			.write_byte = ps8811_emul_p0_write_byte, \
+		}, \
+		.p1_data = { \
+			.read_byte = ps8811_emul_p1_read_byte, \
+			.write_byte = ps8811_emul_p1_write_byte, \
+		}, \
+	};       \
+	static const struct ps8811_emul_cfg ps8811_emul_cfg_##n = { \
+		.p0_cfg = { \
+			.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)), \
+			.data = &ps8811_emul_data_##n.p0_data, \
+			.addr = DT_INST_REG_ADDR(n), \
+		}, \
+		.p1_cfg = { \
+			.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)), \
+			.data = &ps8811_emul_data_##n.p1_data, \
+			.addr = DT_INST_REG_ADDR(n) + 1, \
+		}, \
+	};   \
+	EMUL_DT_INST_DEFINE(n, ps8811_emul_init, &ps8811_emul_data_##n, \
+			    &ps8811_emul_cfg_##n, &i2c_ps8811_emul_api, NULL)
+
+DT_INST_FOREACH_STATUS_OKAY(PS8811_EMUL);
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE)
diff --git a/zephyr/emul/tcpc/CMakeLists.txt b/zephyr/emul/tcpc/CMakeLists.txt
new file mode 100644
index 0000000000..2a94ebaa93
--- /dev/null
+++ b/zephyr/emul/tcpc/CMakeLists.txt
@@ -0,0 +1,16 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+zephyr_library_sources_ifdef(CONFIG_EMUL_PS8XXX		emul_ps8xxx.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_TCPCI		emul_tcpci.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_TCPCI		emul_tcpci_generic.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_TCPCI_PARTNER_COMMON	emul_tcpci_partner_common.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_TCPCI_PARTNER_DRP	emul_tcpci_partner_drp.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_TCPCI_PARTNER_SNK	emul_tcpci_partner_snk.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_TCPCI_PARTNER_SRC	emul_tcpci_partner_src.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_TCPCI_PARTNER_FAULTY_EXT	emul_tcpci_partner_faulty_ext.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_TCPCI_PARTNER_VPD	emul_tcpci_partner_vpd.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_ANX7447	emul_anx7447.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_RT1718S	emul_rt1718s.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_NCT38XX	emul_nct38xx.c)
\ No newline at end of file
diff --git a/zephyr/emul/tcpc/Kconfig b/zephyr/emul/tcpc/Kconfig
new file mode 100644
index 0000000000..246a8cce39
--- /dev/null
+++ b/zephyr/emul/tcpc/Kconfig
@@ -0,0 +1,114 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+menuconfig EMUL_TCPCI
+	bool "TCPCI common functionality"
+	default y
+	depends on DT_HAS_CROS_TCPCI_GENERIC_EMUL_ENABLED
+	depends on I2C_EMUL
+	select PLATFORM_EC_USB_PD_TCPM_TCPCI
+	select EMUL_COMMON_I2C
+	help
+	  Enable the TCPCI emulator. This driver uses the emulated I2C bus.
+	  It is used to test tcpci code. It supports reads and writes to all
+	  emulator registers. Generic TCPCI emulator can be used as the base
+	  for specific TCPC device emulator that follow TCPCI specification.
+	  TCPCI emulator API is available in
+	  zephyr/include/emul/tcpc/emul_tcpci.h
+
+if EMUL_TCPCI
+
+module = TCPCI_EMUL
+module-str = tcpci_emul
+source "subsys/logging/Kconfig.template.log_config"
+
+config EMUL_ANX7447
+	bool "Analogix ANX7447 emulator"
+	default y
+	depends on DT_HAS_CROS_ANX7447_TCPC_EMUL_ENABLED
+	help
+	  Enable emulator for ANX7447 of TCPM. This emulator is extension for
+	  TCPCI emulator. ANX7447 specific API is available in
+	  zephyr/include/emul/tpcp/emul_anx7447.h
+
+config EMUL_TCPCI_PARTNER_COMMON
+	bool
+	help
+	  This option is selected automatically by specific TCPCI partner
+	  emulators. Enable common code that can be used by TCPCI partner device
+	  emulators. It covers sending delayed messages. API of common functions
+	  is available in zephyr/include/emul/tcpc/emul_common_tcpci_partner.h
+
+config EMUL_NCT38XX
+	bool "Nuvoton NCT38xx emulator"
+	default y
+	depends on DT_HAS_NUVOTON_NCT38XX_ENABLED
+	help
+	  Enable emulator for NCT38XX family of TCPC. This emulator is extension
+	  of the TCPCI emulator.
+
+config EMUL_PS8XXX
+	bool "Parade PS8XXX emulator"
+	default y
+	depends on DT_HAS_CROS_PS8XXX_EMUL_ENABLED
+	help
+	  Enable emulator for PS8XXX family of TCPC. This emulator is extenstion
+	  for TCPCI emulator. PS8XXX specific API is available in
+	  zephyr/include/emul/tcpc/emul_ps8xxx.h
+
+config EMUL_RT1718S
+	bool "Richtek rt1718s emulator"
+	default y
+	depends on DT_HAS_CROS_RT1718S_TCPC_EMUL_ENABLED
+	help
+	  Enable emulator for rt1718s of TCPM. This emulator is extension for
+	  TCPCI emulator. rt1718s specific API is available in
+	  zephyr/include/emul/tcpc/emul_rt1718s.h
+
+config EMUL_TCPCI_PARTNER_SRC
+	bool "USB-C source device emulator"
+	select EMUL_TCPCI_PARTNER_COMMON
+	help
+	  Enable USB-C source device emulator which may be attached to TCPCI
+	  emulator. API of source device emulator is available in
+	  zephyr/include/emul/tcpc/emul_tcpci_partner_src.h
+
+config EMUL_TCPCI_PARTNER_SNK
+	bool "USB-C sink device emulator"
+	select EMUL_TCPCI_PARTNER_COMMON
+	help
+	  Enable USB-C sink device emulator which may be attached to TCPCI
+	  emulator. API of sink device emulator is available in
+	  zephyr/include/emul/tcpc/emul_tcpci_partner_snk.h
+
+config EMUL_TCPCI_PARTNER_DRP
+	bool "USB-C dual role device emulator"
+	select EMUL_TCPCI_PARTNER_COMMON
+	select EMUL_TCPCI_PARTNER_SNK
+	select EMUL_TCPCI_PARTNER_SRC
+	help
+	  Enable USB-C dual role device emulator which may be attached to TCPCI
+	  emulator. API of dual role device emulator is available in
+	  zephyr/include/emul/tcpc/emul_tcpci_partner_drp.h
+
+config EMUL_TCPCI_PARTNER_FAULTY_EXT
+	bool "USB-C malfunctioning device emulator"
+	select EMUL_TCPCI_PARTNER_COMMON
+	select EMUL_TCPCI_PARTNER_SNK
+	help
+	  Enable USB-C malfunctioning device emulator which may be attached
+	  to TCPCI emulator. API of malfunctioning device emulator is
+	  available in zephyr/include/emul/tcpc/emul_tcpci_partner_faulty_ext.h
+
+config EMUL_TCPCI_PARTNER_VPD
+	bool "USB-C VCONN-powered device emulator"
+	select EMUL_TCPCI_PARTNER_COMMON
+	# select EMUL_TCPCI_PARTNER_SRC
+	help
+	  Enable USB-C VCONN-powered device (VPD) emulator, which may be
+	  attached to TCPCI emulator. API of VPD is available in
+	  zephyr/include/emul/tcpc/emul_tcpci_partner_vpd.h. This emulation is
+	  specifically for the host port side of the VPD.
+
+endif # EMUL_TCPCI
diff --git a/zephyr/emul/tcpc/emul_anx7447.c b/zephyr/emul/tcpc/emul_anx7447.c
new file mode 100644
index 0000000000..26d172f90f
--- /dev/null
+++ b/zephyr/emul/tcpc/emul_anx7447.c
@@ -0,0 +1,166 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_stub_device.h"
+#include "emul/tcpc/emul_tcpci.h"
+#include "tcpm/tcpci.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/i2c_emul.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/ztest.h>
+
+#define DT_DRV_COMPAT cros_anx7447_tcpc_emul
+
+LOG_MODULE_REGISTER(anx7447_emul, CONFIG_TCPCI_EMUL_LOG_LEVEL);
+
+/**
+ * @brief Function called for each byte of read message from anx7447 emulator
+ *
+ * @param emul Pointer to I2C anx7447 emulator
+ * @param reg First byte of last write message
+ * @param val Pointer where byte to read should be stored
+ * @param bytes Number of bytes already read
+ *
+ * @return 0 on success
+ * @return -EIO on invalid read request
+ */
+static int anx7447_emul_read_byte(const struct emul *emul, int reg,
+				  uint8_t *val, int bytes)
+{
+	return tcpci_emul_read_byte(emul, reg, val, bytes);
+}
+
+/**
+ * @brief Function called for each byte of write message to anx7447 emulator
+ *
+ * @param emul Pointer to I2C anx7447 emulator
+ * @param reg First byte of write message
+ * @param val Received byte of write message
+ * @param bytes Number of bytes already received
+ *
+ * @return 0 on success
+ * @return -EIO on invalid write request
+ */
+static int anx7447_emul_write_byte(const struct emul *emul, int reg,
+				   uint8_t val, int bytes)
+{
+	return tcpci_emul_write_byte(emul, reg, val, bytes);
+}
+
+/**
+ * @brief Function called on the end of write message to anx7447 emulator
+ *
+ * @param emul Pointer to I2C anx7447 emulator
+ * @param reg Register which is written
+ * @param msg_len Length of handled I2C message
+ *
+ * @return 0 on success
+ * @return -EIO on error
+ */
+static int anx7447_emul_finish_write(const struct emul *emul, int reg,
+				     int msg_len)
+{
+	return tcpci_emul_handle_write(emul, reg, msg_len);
+}
+
+/**
+ * @brief Get currently accessed register, which always equals to selected
+ *        register from anx7447 emulator.
+ *
+ * @param emul Pointer to I2C anx7447 emulator
+ * @param reg First byte of last write message
+ * @param bytes Number of bytes already handled from current message
+ * @param read If currently handled is read message
+ *
+ * @return Currently accessed register
+ */
+static int anx7447_emul_access_reg(const struct emul *emul, int reg, int bytes,
+				   bool read)
+{
+	return reg;
+}
+
+/**
+ * @brief Function called on reset
+ *
+ * @param emul Pointer to anx7447 emulator
+ */
+static void anx7447_emul_reset(const struct emul *emul)
+{
+	tcpci_emul_reset(emul);
+}
+
+/**
+ * @brief Set up a new anx7447 emulator
+ *
+ * This should be called for each anx7447 device that needs to be
+ * emulated.
+ *
+ * @param emul Emulation information
+ * @param parent Device to emulate
+ *
+ * @return 0 indicating success (always)
+ */
+static int anx7447_emul_init(const struct emul *emul,
+			     const struct device *parent)
+{
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *tcpci_ctx = tcpc_data->tcpci_ctx;
+	const struct device *i2c_dev;
+
+	i2c_dev = parent;
+
+	tcpci_ctx->common.write_byte = anx7447_emul_write_byte;
+	tcpci_ctx->common.finish_write = anx7447_emul_finish_write;
+	tcpci_ctx->common.read_byte = anx7447_emul_read_byte;
+	tcpci_ctx->common.access_reg = anx7447_emul_access_reg;
+
+	tcpci_emul_i2c_init(emul, i2c_dev);
+
+	anx7447_emul_reset(emul);
+
+	return 0;
+}
+
+static int i2c_anx7447_emul_transfer(const struct emul *target,
+				     struct i2c_msg *msgs, int num_msgs,
+				     int addr)
+{
+	struct tcpc_emul_data *tcpc_data = target->data;
+	struct tcpci_ctx *tcpci_ctx = tcpc_data->tcpci_ctx;
+
+	return i2c_common_emul_transfer_workhorse(target, &tcpci_ctx->common,
+						  &tcpc_data->i2c_cfg, msgs,
+						  num_msgs, addr);
+}
+
+struct i2c_emul_api i2c_anx7447_emul_api = {
+	.transfer = i2c_anx7447_emul_transfer,
+};
+
+#define ANX7447_EMUL(n)                                     \
+	TCPCI_EMUL_DEFINE(n, anx7447_emul_init, NULL, NULL, \
+			  &i2c_anx7447_emul_api, NULL)
+
+DT_INST_FOREACH_STATUS_OKAY(ANX7447_EMUL)
+
+#ifdef CONFIG_ZTEST_NEW_API
+#define ANX7447_EMUL_RESET_RULE_BEFORE(n) \
+	anx7447_emul_reset(EMUL_DT_GET(DT_DRV_INST(n)))
+static void anx7447_emul_reset_rule_before(const struct ztest_unit_test *test,
+					   void *data)
+{
+	ARG_UNUSED(test);
+	ARG_UNUSED(data);
+	DT_INST_FOREACH_STATUS_OKAY(ANX7447_EMUL_RESET_RULE_BEFORE);
+}
+ZTEST_RULE(ANX7447_emul_reset, anx7447_emul_reset_rule_before, NULL);
+#endif /* CONFIG_ZTEST_NEW_API */
+
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
diff --git a/zephyr/emul/tcpc/emul_nct38xx.c b/zephyr/emul/tcpc/emul_nct38xx.c
new file mode 100644
index 0000000000..0b834b03ce
--- /dev/null
+++ b/zephyr/emul/tcpc/emul_nct38xx.c
@@ -0,0 +1,239 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "common.h"
+#include "driver/tcpm/nct38xx.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_stub_device.h"
+#include "emul/tcpc/emul_nct38xx.h"
+#include "emul/tcpc/emul_tcpci.h"
+#include "tcpm/tcpci.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/i2c_emul.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/ztest.h>
+
+#define DT_DRV_COMPAT nuvoton_nct38xx
+
+#define NCT38XX_VENDOR_REG_START 0xC0
+#define NCT38XX_VENDOR_REG_END 0xDE
+#define NCT38XX_VENDOR_REG_COUNT \
+	(NCT38XX_VENDOR_REG_END - NCT38XX_VENDOR_REG_START)
+
+LOG_MODULE_REGISTER(nct38xx_emul, CONFIG_TCPCI_EMUL_LOG_LEVEL);
+
+/* For vendor specific registers. */
+struct nct38xx_register {
+	uint8_t reg;
+	uint8_t def;
+	uint8_t value;
+	uint8_t reserved;
+};
+
+struct nct38xx_emul_data {
+	struct nct38xx_register regs[NCT38XX_VENDOR_REG_COUNT];
+};
+
+const static struct nct38xx_register
+	default_reg_configs[NCT38XX_VENDOR_REG_COUNT] = {
+		{
+			.reg = NCT38XX_REG_CTRL_OUT_EN,
+			.def = NCT38XX_REG_CTRL_OUT_EN_DEFAULT,
+			.reserved = NCT38XX_REG_CTRL_OUT_EN_RESERVED_MASK,
+		},
+		{
+			.reg = NCT38XX_REG_VBC_FAULT_CTL,
+			.def = NCT38XX_REG_VBC_FAULT_CTL_DEFAULT,
+			.value = NCT38XX_REG_VBC_FAULT_CTL_DEFAULT,
+			.reserved = NCT38XX_REG_VBC_FAULT_CTL_RESERVED_MASK,
+		}
+	};
+
+static struct nct38xx_register *get_register_mut(const struct emul *emul,
+						 int reg)
+{
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct nct38xx_emul_data *nct38xx = tcpc_data->chip_data;
+
+	for (size_t i = 0; i < ARRAY_SIZE(nct38xx->regs); i++) {
+		if (nct38xx->regs[i].reg && nct38xx->regs[i].reg == reg)
+			return &nct38xx->regs[i];
+	}
+
+	return NULL;
+}
+
+static const struct nct38xx_register *
+get_register_const(const struct emul *emul, int reg)
+{
+	return get_register_mut(emul, reg);
+}
+
+int nct38xx_emul_get_reg(const struct emul *emul, int r, uint16_t *val)
+{
+	const struct nct38xx_register *reg = get_register_const(emul, r);
+
+	if (reg) {
+		*val = reg->value;
+		return 0;
+	}
+
+	return tcpci_emul_get_reg(emul, r, val);
+}
+
+static int nct38xx_set_vendor_reg_raw(struct nct38xx_register *reg,
+				      uint16_t val)
+{
+	if ((val & reg->reserved) != (reg->def & reg->reserved)) {
+		LOG_DBG("Reserved bits modified for reg %02x, val: %02x, \
+			default: %02x, reserved: %02x",
+			reg->reg, val, reg->def, reg->reserved);
+		return -EINVAL;
+	}
+
+	reg->value = val;
+	return 0;
+}
+
+int nct38xx_emul_set_reg(const struct emul *emul, int r, uint16_t val)
+{
+	struct nct38xx_register *reg = get_register_mut(emul, r);
+
+	if (reg)
+		return nct38xx_set_vendor_reg_raw(reg, val);
+
+	return tcpci_emul_set_reg(emul, r, val);
+}
+
+static int i2c_nct38xx_emul_transfer(const struct emul *target,
+				     struct i2c_msg *msgs, int num_msgs,
+				     int addr)
+{
+	struct tcpc_emul_data *tcpc_data = target->data;
+	struct tcpci_ctx *tcpci_ctx = tcpc_data->tcpci_ctx;
+
+	return i2c_common_emul_transfer_workhorse(target, &tcpci_ctx->common,
+						  &tcpc_data->i2c_cfg, msgs,
+						  num_msgs, addr);
+}
+
+struct i2c_emul_api i2c_nct38xx_emul_api = {
+	.transfer = i2c_nct38xx_emul_transfer,
+};
+
+static int nct38xx_emul_tcpc_write_byte(const struct emul *emul, int r,
+					uint8_t val, int bytes)
+{
+	struct nct38xx_register *reg = get_register_mut(emul, r);
+
+	if (reg) {
+		/* Process vendor-defined register write. */
+		if (bytes != 1) {
+			LOG_DBG("Write %d bytes to single-byte register %x\n",
+				r);
+			return -EIO;
+		}
+
+		return nct38xx_set_vendor_reg_raw(reg, val);
+	}
+
+	return tcpci_emul_write_byte(emul, r, val, bytes);
+}
+
+static int nct38xx_emul_tcpc_read_byte(const struct emul *emul, int r,
+				       uint8_t *val, int bytes)
+{
+	const struct nct38xx_register *reg = get_register_const(emul, r);
+
+	if (reg) {
+		/* Process vendor-defined register read. */
+		if (bytes != 0) {
+			LOG_DBG("Read %d bytes from single-byte register %x\n",
+				r);
+			return -EIO;
+		}
+
+		*val = reg->value;
+		return 0;
+	}
+
+	return tcpci_emul_read_byte(emul, r, val, bytes);
+}
+
+static int nct38xx_emul_finish_write(const struct emul *emul, int reg,
+				     int msg_len)
+{
+	/* Always report success for our vendor-specific registers. */
+	if (get_register_const(emul, reg))
+		return 0;
+
+	return tcpci_emul_handle_write(emul, reg, msg_len);
+}
+
+static int nct38xx_emul_access_reg(const struct emul *emul, int reg, int bytes,
+				   bool read)
+{
+	return reg;
+}
+
+void nct38xx_emul_reset(const struct emul *emul)
+{
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct nct38xx_emul_data *nct38xx = tcpc_data->chip_data;
+
+	memcpy(&nct38xx->regs, default_reg_configs,
+	       NCT38XX_VENDOR_REG_COUNT * sizeof(struct nct38xx_register));
+	/* Using the setter helps catch any default misconfigs. */
+	for (size_t i = 0; i < ARRAY_SIZE(nct38xx->regs); i++) {
+		if (nct38xx->regs[i].reg == 0)
+			continue;
+
+		nct38xx_emul_set_reg(emul, nct38xx->regs[i].reg,
+				     nct38xx->regs[i].def);
+	}
+
+	tcpci_emul_reset(emul);
+}
+
+static int nct38xx_emul_init(const struct emul *emul,
+			     const struct device *parent)
+{
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *tcpci_ctx = tcpc_data->tcpci_ctx;
+
+	tcpci_ctx->common.access_reg = nct38xx_emul_access_reg;
+	tcpci_ctx->common.read_byte = nct38xx_emul_tcpc_read_byte;
+	tcpci_ctx->common.finish_write = nct38xx_emul_finish_write;
+	tcpci_ctx->common.write_byte = nct38xx_emul_tcpc_write_byte;
+
+	tcpci_emul_i2c_init(emul, parent);
+	nct38xx_emul_reset(emul);
+	return 0;
+}
+
+#define NCT38XX_EMUL(n)                                                       \
+	static struct nct38xx_emul_data nct38xx_emul_data_##n;                \
+	TCPCI_EMUL_DEFINE(n, nct38xx_emul_init, NULL, &nct38xx_emul_data_##n, \
+			  &i2c_nct38xx_emul_api, NULL)
+
+DT_INST_FOREACH_STATUS_OKAY(NCT38XX_EMUL);
+
+#define NCT38XX_EMUL_RESET_RULE_AFTER(n) \
+	nct38xx_emul_reset(EMUL_DT_GET(DT_DRV_INST(n)));
+
+static void nct38xx_emul_test_reset(const struct ztest_unit_test *test,
+				    void *data)
+{
+	ARG_UNUSED(test);
+	ARG_UNUSED(data);
+
+	DT_INST_FOREACH_STATUS_OKAY(NCT38XX_EMUL_RESET_RULE_AFTER)
+}
+
+ZTEST_RULE(emul_nct38xx_reset, NULL, nct38xx_emul_test_reset);
+
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE)
diff --git a/zephyr/emul/tcpc/emul_ps8xxx.c b/zephyr/emul/tcpc/emul_ps8xxx.c
new file mode 100644
index 0000000000..fc94b4f9d6
--- /dev/null
+++ b/zephyr/emul/tcpc/emul_ps8xxx.c
@@ -0,0 +1,696 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/tcpm/ps8xxx.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_stub_device.h"
+#include "emul/tcpc/emul_ps8xxx.h"
+#include "emul/tcpc/emul_tcpci.h"
+#include "tcpm/tcpci.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/i2c_emul.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/ztest.h>
+
+#define DT_DRV_COMPAT cros_ps8xxx_emul
+#define PS8XXX_REG_MUX_IN_HPD_ASSERTION MUX_IN_HPD_ASSERTION_REG
+
+LOG_MODULE_REGISTER(ps8xxx_emul, CONFIG_TCPCI_EMUL_LOG_LEVEL);
+
+/** Run-time data used by the emulator */
+struct ps8xxx_emul_data {
+	/** Common I2C data used by "hidden" ports */
+	struct i2c_common_emul_data p0_data;
+	struct i2c_common_emul_data p1_data;
+	struct i2c_common_emul_data gpio_data;
+
+	/** Product ID of emulated device */
+	int prod_id;
+
+	/** Chip revision used by PS8805 */
+	uint8_t chip_rev;
+	/** Mux usb DCI configuration */
+	uint8_t dci_cfg;
+	/** GPIO control register value */
+	uint8_t gpio_ctrl;
+	/** HW revision used by PS8815 */
+	uint16_t hw_rev;
+	/**
+	 * Register ID to distinguish between the PS8815-A2 and PS8745-A2
+	 * 0: Indicates this is an 8815-A2 chip
+	 * 1: Indicates this is an 8745-A2 chip
+	 */
+	uint8_t reg_id;
+};
+
+/** Constant configuration of the emulator */
+struct ps8xxx_emul_cfg {
+	/** Common I2C configuration used by "hidden" ports */
+	const struct i2c_common_emul_cfg p0_cfg;
+	const struct i2c_common_emul_cfg p1_cfg;
+	const struct i2c_common_emul_cfg gpio_cfg;
+};
+
+/** Check description in emul_ps8xxx.h */
+void ps8xxx_emul_set_chip_rev(const struct emul *emul, uint8_t chip_rev)
+{
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct ps8xxx_emul_data *data = tcpc_data->chip_data;
+
+	data->chip_rev = chip_rev;
+}
+
+/** Check description in emul_ps8xxx.h */
+void ps8xxx_emul_set_reg_id(const struct emul *emul, enum ps8xxx_regid reg_id)
+{
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct ps8xxx_emul_data *data = tcpc_data->chip_data;
+
+	data->reg_id = reg_id;
+}
+
+/** Check description in emul_ps8xxx.h */
+void ps8xxx_emul_set_hw_rev(const struct emul *emul, uint16_t hw_rev)
+{
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct ps8xxx_emul_data *data = tcpc_data->chip_data;
+
+	data->hw_rev = hw_rev;
+}
+
+/** Check description in emul_ps8xxx.h */
+void ps8xxx_emul_set_gpio_ctrl(const struct emul *emul, uint8_t gpio_ctrl)
+{
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct ps8xxx_emul_data *data = tcpc_data->chip_data;
+
+	data->gpio_ctrl = gpio_ctrl;
+}
+
+/** Check description in emul_ps8xxx.h */
+uint8_t ps8xxx_emul_get_gpio_ctrl(const struct emul *emul)
+{
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct ps8xxx_emul_data *data = tcpc_data->chip_data;
+
+	return data->gpio_ctrl;
+}
+
+/** Check description in emul_ps8xxx.h */
+uint8_t ps8xxx_emul_get_dci_cfg(const struct emul *emul)
+{
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct ps8xxx_emul_data *data = tcpc_data->chip_data;
+
+	return data->dci_cfg;
+}
+
+/** Check description in emul_ps8xxx.h */
+int ps8xxx_emul_set_product_id(const struct emul *emul, uint16_t product_id)
+{
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct ps8xxx_emul_data *data = tcpc_data->chip_data;
+
+	if (product_id != PS8805_PRODUCT_ID &&
+	    product_id != PS8815_PRODUCT_ID) {
+		LOG_ERR("Setting invalid product ID 0x%x", product_id);
+		return -EINVAL;
+	}
+
+	data->prod_id = product_id;
+	tcpci_emul_set_reg(emul, TCPC_REG_PRODUCT_ID, product_id);
+
+	return 0;
+}
+
+/** Check description in emul_ps8xxx.h */
+uint16_t ps8xxx_emul_get_product_id(const struct emul *emul)
+{
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct ps8xxx_emul_data *data = tcpc_data->chip_data;
+
+	return data->prod_id;
+}
+
+/** Check description in emul_ps8xxx.h */
+struct i2c_common_emul_data *
+ps8xxx_emul_get_i2c_common_data(const struct emul *emul,
+				enum ps8xxx_emul_port port)
+{
+	const struct ps8xxx_emul_cfg *cfg = emul->cfg;
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct ps8xxx_emul_data *data = tcpc_data->chip_data;
+
+	switch (port) {
+	case PS8XXX_EMUL_PORT_0:
+		return &data->p0_data;
+	case PS8XXX_EMUL_PORT_1:
+		return &data->p1_data;
+	case PS8XXX_EMUL_PORT_GPIO:
+		if (cfg->gpio_cfg.addr != 0) {
+			return &data->gpio_data;
+		} else {
+			return NULL;
+		}
+	default:
+		return NULL;
+	}
+}
+
+/**
+ * @brief Function called for each byte of read message from TCPC chip
+ *
+ * @param i2c_emul Pointer to PS8xxx emulator
+ * @param reg First byte of last write message
+ * @param val Pointer where byte to read should be stored
+ * @param bytes Number of bytes already read
+ *
+ * @return 0 on success
+ * @return -EIO on invalid read request
+ */
+static int ps8xxx_emul_tcpc_read_byte(const struct emul *emul, int reg,
+				      uint8_t *val, int bytes)
+{
+	uint16_t reg_val;
+	const struct i2c_emul *i2c_emul = emul->bus.i2c;
+
+	LOG_DBG("PS8XXX TCPC 0x%x: read reg 0x%x", i2c_emul->addr, reg);
+
+	switch (reg) {
+	case PS8XXX_REG_FW_REV:
+	case PS8XXX_REG_I2C_DEBUGGING_ENABLE:
+	case PS8XXX_REG_MUX_IN_HPD_ASSERTION:
+	case PS8XXX_REG_BIST_CONT_MODE_BYTE0:
+	case PS8XXX_REG_BIST_CONT_MODE_BYTE1:
+	case PS8XXX_REG_BIST_CONT_MODE_BYTE2:
+	case PS8XXX_REG_BIST_CONT_MODE_CTR:
+		if (bytes != 0) {
+			LOG_ERR("Reading byte %d from 1 byte register 0x%x",
+				bytes, reg);
+			return -EIO;
+		}
+
+		tcpci_emul_get_reg(emul, reg, &reg_val);
+		*val = reg_val & 0xff;
+		return 0;
+	default:
+		break;
+	}
+
+	return tcpci_emul_read_byte(emul, reg, val, bytes);
+}
+
+/**
+ * @brief Function called for each byte of write message to TCPC chip
+ *
+ * @param emul Pointer to PS8xxx emulator
+ * @param reg First byte of write message
+ * @param val Received byte of write message
+ * @param bytes Number of bytes already received
+ *
+ * @return 0 on success
+ * @return -EIO on invalid write request
+ */
+static int ps8xxx_emul_tcpc_write_byte(const struct emul *emul, int reg,
+				       uint8_t val, int bytes)
+{
+	uint16_t prod_id;
+	struct i2c_emul *i2c_emul = emul->bus.i2c;
+
+	LOG_DBG("PS8XXX TCPC 0x%x: write reg 0x%x", i2c_emul->addr, reg);
+
+	tcpci_emul_get_reg(emul, TCPC_REG_PRODUCT_ID, &prod_id);
+
+	switch (reg) {
+	case PS8XXX_REG_RP_DETECT_CONTROL:
+		/* This register is present only on PS8815 */
+		if (prod_id != PS8815_PRODUCT_ID) {
+			break;
+		}
+		__fallthrough;
+	case PS8XXX_REG_I2C_DEBUGGING_ENABLE:
+	case PS8XXX_REG_MUX_IN_HPD_ASSERTION:
+	case PS8XXX_REG_BIST_CONT_MODE_BYTE0:
+	case PS8XXX_REG_BIST_CONT_MODE_BYTE1:
+	case PS8XXX_REG_BIST_CONT_MODE_BYTE2:
+	case PS8XXX_REG_BIST_CONT_MODE_CTR:
+		if (bytes != 1) {
+			LOG_ERR("Writing byte %d to 1 byte register 0x%x",
+				bytes, reg);
+			return -EIO;
+		}
+
+		tcpci_emul_set_reg(emul, reg, val);
+		return 0;
+	default:
+		break;
+	}
+
+	return tcpci_emul_write_byte(emul, reg, val, bytes);
+}
+
+/**
+ * @brief Function called on the end of write message to TCPC chip
+ *
+ * @param emul Pointer to PS8xxx emulator
+ * @param reg Register which is written
+ * @param msg_len Length of handled I2C message
+ *
+ * @return 0 on success
+ * @return -EIO on error
+ */
+static int ps8xxx_emul_tcpc_finish_write(const struct emul *emul, int reg,
+					 int msg_len)
+{
+	uint16_t prod_id;
+	struct i2c_emul *i2c_emul = emul->bus.i2c;
+
+	LOG_DBG("PS8XXX TCPC 0x%x: finish write reg 0x%x", i2c_emul->addr, reg);
+
+	tcpci_emul_get_reg(emul, TCPC_REG_PRODUCT_ID, &prod_id);
+
+	switch (reg) {
+	case PS8XXX_REG_RP_DETECT_CONTROL:
+		/* This register is present only on PS8815 */
+		if (prod_id != PS8815_PRODUCT_ID) {
+			break;
+		}
+		__fallthrough;
+	case PS8XXX_REG_I2C_DEBUGGING_ENABLE:
+	case PS8XXX_REG_MUX_IN_HPD_ASSERTION:
+	case PS8XXX_REG_BIST_CONT_MODE_BYTE0:
+	case PS8XXX_REG_BIST_CONT_MODE_BYTE1:
+	case PS8XXX_REG_BIST_CONT_MODE_BYTE2:
+	case PS8XXX_REG_BIST_CONT_MODE_CTR:
+		return 0;
+	default:
+		break;
+	}
+
+	return tcpci_emul_handle_write(emul, reg, msg_len);
+}
+
+/**
+ * @brief Get currently accessed register, which always equals to selected
+ *        register from TCPC chip.
+ *
+ * @param emul Pointer to TCPCI emulator
+ * @param reg First byte of last write message
+ * @param bytes Number of bytes already handled from current message
+ * @param read If currently handled is read message
+ *
+ * @return Currently accessed register
+ */
+static int ps8xxx_emul_tcpc_access_reg(const struct emul *emul, int reg,
+				       int bytes, bool read)
+{
+	return reg;
+}
+
+/**
+ * @brief Function called on reset
+ *
+ * @param emul Pointer to PS8xxx emulator
+ */
+static int ps8xxx_emul_tcpc_reset(const struct emul *emul)
+{
+	tcpci_emul_set_reg(emul, PS8XXX_REG_I2C_DEBUGGING_ENABLE, 0x31);
+	tcpci_emul_set_reg(emul, PS8XXX_REG_MUX_IN_HPD_ASSERTION, 0x00);
+	tcpci_emul_set_reg(emul, PS8XXX_REG_BIST_CONT_MODE_BYTE0, 0xff);
+	tcpci_emul_set_reg(emul, PS8XXX_REG_BIST_CONT_MODE_BYTE1, 0x0f);
+	tcpci_emul_set_reg(emul, PS8XXX_REG_BIST_CONT_MODE_BYTE2, 0x00);
+	tcpci_emul_set_reg(emul, PS8XXX_REG_BIST_CONT_MODE_CTR, 0x00);
+
+	return tcpci_emul_reset(emul);
+}
+
+/**
+ * @brief Function called for each byte of read message
+ *
+ * @param emul Pointer to PS8xxx emulator
+ * @param reg First byte of last write message
+ * @param val Pointer where byte to read should be stored
+ * @param bytes Number of bytes already read
+ *
+ * @return 0 on success
+ * @return -EIO on invalid read request
+ */
+static int ps8xxx_emul_read_byte_workhorse(const struct emul *emul, int reg,
+					   uint8_t *val, int bytes,
+					   enum ps8xxx_emul_port port)
+{
+	struct tcpc_emul_data *tcpc_data;
+	struct ps8xxx_emul_data *data;
+	struct i2c_emul *i2c_emul = emul->bus.i2c;
+	uint16_t i2c_dbg_reg;
+
+	LOG_DBG("PS8XXX 0x%x: read reg 0x%x", i2c_emul->addr, reg);
+
+	tcpc_data = emul->data;
+	data = tcpc_data->chip_data;
+
+	tcpci_emul_get_reg(emul, PS8XXX_REG_I2C_DEBUGGING_ENABLE, &i2c_dbg_reg);
+	/* There is no need to enable I2C debug on PS8815 */
+	if (data->prod_id != PS8815_PRODUCT_ID && i2c_dbg_reg & 0x1) {
+		LOG_ERR("Accessing hidden i2c address without enabling debug");
+		return -EIO;
+	}
+
+	/* This is only 2 bytes register so handle it separately */
+	if (data->prod_id == PS8815_PRODUCT_ID && port == PS8XXX_EMUL_PORT_1 &&
+	    reg == PS8815_P1_REG_HW_REVISION) {
+		if (bytes > 1) {
+			LOG_ERR("Reading more than two bytes from HW rev reg");
+			return -EIO;
+		}
+
+		*val = (data->hw_rev >> (bytes * 8)) & 0xff;
+		return 0;
+	}
+
+	if (bytes != 0) {
+		LOG_ERR("Reading more than one byte at once");
+		return -EIO;
+	}
+
+	switch (port) {
+	case PS8XXX_EMUL_PORT_0:
+		if (data->prod_id == PS8805_PRODUCT_ID &&
+		    reg == PS8805_P0_REG_CHIP_REVISION) {
+			*val = data->chip_rev;
+			return 0;
+		}
+		if (data->prod_id == PS8815_PRODUCT_ID &&
+		    reg == PS8815_P0_REG_ID) {
+			*val = data->chip_rev;
+			return 0;
+		}
+		break;
+	case PS8XXX_EMUL_PORT_1:
+		/* DCI CFG is no available on PS8815 */
+		if (data->prod_id != PS8815_PRODUCT_ID &&
+		    reg == PS8XXX_P1_REG_MUX_USB_DCI_CFG) {
+			*val = data->dci_cfg;
+			return 0;
+		}
+		__fallthrough;
+	case PS8XXX_EMUL_PORT_GPIO:
+		if (reg == PS8805_REG_GPIO_CONTROL) {
+			*val = data->gpio_ctrl;
+			return 0;
+		}
+		__fallthrough;
+	case PS8XXX_EMUL_PORT_INVAL:
+		LOG_ERR("Invalid I2C address");
+		return -EIO;
+	}
+
+	LOG_ERR("Reading from reg 0x%x which is WO or undefined", reg);
+	return -EIO;
+}
+
+static int ps8xxx_emul_p0_read_byte(const struct emul *emul, int reg,
+				    uint8_t *val, int bytes)
+{
+	return ps8xxx_emul_read_byte_workhorse(emul, reg, val, bytes,
+					       PS8XXX_EMUL_PORT_0);
+}
+
+static int ps8xxx_emul_p1_read_byte(const struct emul *emul, int reg,
+				    uint8_t *val, int bytes)
+{
+	return ps8xxx_emul_read_byte_workhorse(emul, reg, val, bytes,
+					       PS8XXX_EMUL_PORT_1);
+}
+
+static int ps8xxx_emul_gpio_read_byte(const struct emul *emul, int reg,
+				      uint8_t *val, int bytes)
+{
+	return ps8xxx_emul_read_byte_workhorse(emul, reg, val, bytes,
+					       PS8XXX_EMUL_PORT_GPIO);
+}
+
+/**
+ * @brief Function called for each byte of write message
+ *
+ * @param emul Pointer to PS8xxx emulator
+ * @param reg First byte of write message
+ * @param val Received byte of write message
+ * @param bytes Number of bytes already received
+ *
+ * @return 0 on success
+ * @return -EIO on invalid write request
+ */
+static int ps8xxx_emul_write_byte_workhorse(const struct emul *emul, int reg,
+					    uint8_t val, int bytes,
+					    enum ps8xxx_emul_port port)
+{
+	struct ps8xxx_emul_data *data;
+	struct tcpc_emul_data *tcpc_data;
+	const struct i2c_emul *i2c_emul = emul->bus.i2c;
+	uint16_t i2c_dbg_reg;
+
+	LOG_DBG("PS8XXX 0x%x: write reg 0x%x", i2c_emul->addr, reg);
+
+	tcpc_data = emul->data;
+	data = tcpc_data->chip_data;
+
+	tcpci_emul_get_reg(emul, PS8XXX_REG_I2C_DEBUGGING_ENABLE, &i2c_dbg_reg);
+	/* There is no need to enable I2C debug on PS8815 */
+	if (data->prod_id != PS8815_PRODUCT_ID && i2c_dbg_reg & 0x1) {
+		LOG_ERR("Accessing hidden i2c address without enabling debug");
+		return -EIO;
+	}
+
+	if (bytes != 1) {
+		LOG_ERR("Writing more than one byte at once");
+		return -EIO;
+	}
+
+	switch (port) {
+	case PS8XXX_EMUL_PORT_0:
+		break;
+	case PS8XXX_EMUL_PORT_1:
+		/* DCI CFG is no available on PS8815 */
+		if (data->prod_id != PS8815_PRODUCT_ID &&
+		    reg == PS8XXX_P1_REG_MUX_USB_DCI_CFG) {
+			data->dci_cfg = val;
+			return 0;
+		}
+		__fallthrough;
+	case PS8XXX_EMUL_PORT_GPIO:
+		if (reg == PS8805_REG_GPIO_CONTROL) {
+			data->gpio_ctrl = val;
+			return 0;
+		}
+		__fallthrough;
+	case PS8XXX_EMUL_PORT_INVAL:
+		LOG_ERR("Invalid I2C address");
+		return -EIO;
+	}
+
+	LOG_ERR("Writing to reg 0x%x which is RO or undefined", reg);
+	return -EIO;
+}
+
+static int ps8xxx_emul_p0_write_byte(const struct emul *emul, int reg,
+				     uint8_t val, int bytes)
+{
+	return ps8xxx_emul_write_byte_workhorse(emul, reg, val, bytes,
+						PS8XXX_EMUL_PORT_0);
+}
+
+static int ps8xxx_emul_p1_write_byte(const struct emul *emul, int reg,
+				     uint8_t val, int bytes)
+{
+	return ps8xxx_emul_write_byte_workhorse(emul, reg, val, bytes,
+						PS8XXX_EMUL_PORT_1);
+}
+
+static int ps8xxx_emul_gpio_write_byte(const struct emul *emul, int reg,
+				       uint8_t val, int bytes)
+{
+	return ps8xxx_emul_write_byte_workhorse(emul, reg, val, bytes,
+						PS8XXX_EMUL_PORT_GPIO);
+}
+
+static int i2c_ps8xxx_emul_transfer(const struct emul *target,
+				    struct i2c_msg *msgs, int num_msgs,
+				    int addr)
+{
+	struct tcpc_emul_data *tcpc_data = target->data;
+	struct ps8xxx_emul_data *ps8_xxx_data = tcpc_data->chip_data;
+	const struct ps8xxx_emul_cfg *ps8_xxx_cfg = target->cfg;
+	struct i2c_common_emul_data *common_data;
+
+	/* The chip itself */
+	if (addr == tcpc_data->i2c_cfg.addr) {
+		const struct i2c_common_emul_cfg *common_cfg =
+			&tcpc_data->i2c_cfg;
+		common_data = &tcpc_data->tcpci_ctx->common;
+
+		return i2c_common_emul_transfer_workhorse(
+			target, common_data, common_cfg, msgs, num_msgs, addr);
+	}
+	/* Subchips */
+	else if (addr == ps8_xxx_cfg->gpio_cfg.addr) {
+		const struct i2c_common_emul_cfg *common_cfg =
+			&ps8_xxx_cfg->gpio_cfg;
+		common_data = &ps8_xxx_data->gpio_data;
+
+		return i2c_common_emul_transfer_workhorse(
+			target, common_data, common_cfg, msgs, num_msgs, addr);
+	} else if (addr == ps8_xxx_cfg->p0_cfg.addr) {
+		const struct i2c_common_emul_cfg *common_cfg =
+			&ps8_xxx_cfg->p0_cfg;
+		common_data = &ps8_xxx_data->p0_data;
+
+		return i2c_common_emul_transfer_workhorse(
+			target, common_data, common_cfg, msgs, num_msgs, addr);
+	} else if (addr == ps8_xxx_cfg->p1_cfg.addr) {
+		const struct i2c_common_emul_cfg *common_cfg =
+			&ps8_xxx_cfg->p1_cfg;
+		common_data = &ps8_xxx_data->p1_data;
+
+		return i2c_common_emul_transfer_workhorse(
+			target, common_data, common_cfg, msgs, num_msgs, addr);
+	}
+
+	LOG_ERR("Cannot map address %02x", addr);
+	return -EIO;
+}
+
+struct i2c_emul_api i2c_ps8xxx_emul_api = {
+	.transfer = i2c_ps8xxx_emul_transfer,
+};
+
+/**
+ * @brief Set up a new PS8xxx emulator
+ *
+ * This should be called for each PS8xxx device that needs to be
+ * emulated. It registers "hidden" I2C devices with the I2C emulation
+ * controller and set PS8xxx device operations to associated TCPCI emulator.
+ *
+ * @param emul Emulation information
+ * @param parent Device to emulate
+ *
+ * @return 0 indicating success (always)
+ */
+static int ps8xxx_emul_init(const struct emul *emul,
+			    const struct device *parent)
+{
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct ps8xxx_emul_data *data = tcpc_data->chip_data;
+	struct tcpci_ctx *tcpci_ctx = tcpc_data->tcpci_ctx;
+	const struct ps8xxx_emul_cfg *cfg = emul->cfg;
+	const struct device *i2c_dev;
+	int ret = 0;
+
+	i2c_dev = parent;
+
+	tcpci_ctx->common.write_byte = ps8xxx_emul_tcpc_write_byte;
+	tcpci_ctx->common.finish_write = ps8xxx_emul_tcpc_finish_write;
+	tcpci_ctx->common.read_byte = ps8xxx_emul_tcpc_read_byte;
+	tcpci_ctx->common.access_reg = ps8xxx_emul_tcpc_access_reg;
+
+	tcpci_emul_i2c_init(emul, i2c_dev);
+
+	data->p0_data.emul.api = &i2c_ps8xxx_emul_api;
+	data->p0_data.emul.addr = cfg->p0_cfg.addr;
+	data->p0_data.emul.target = emul;
+	data->p0_data.i2c = i2c_dev;
+	data->p0_data.cfg = &cfg->p0_cfg;
+	i2c_common_emul_init(&data->p0_data);
+
+	data->p1_data.emul.api = &i2c_ps8xxx_emul_api;
+	data->p1_data.emul.addr = cfg->p1_cfg.addr;
+	data->p1_data.emul.target = emul;
+	data->p1_data.i2c = i2c_dev;
+	data->p1_data.cfg = &cfg->p1_cfg;
+	i2c_common_emul_init(&data->p1_data);
+
+	/* Have to manually register "hidden" addressed chips under overarching
+	 * ps8xxx
+	 * TODO(b/240564574): Call EMUL_DEFINE for each "hidden" sub-chip.
+	 */
+	ret |= i2c_emul_register(i2c_dev, &data->p0_data.emul);
+	ret |= i2c_emul_register(i2c_dev, &data->p1_data.emul);
+
+	if (cfg->gpio_cfg.addr != 0) {
+		data->gpio_data.emul.api = &i2c_ps8xxx_emul_api;
+		data->gpio_data.emul.addr = cfg->gpio_cfg.addr;
+		data->gpio_data.emul.target = emul;
+		data->gpio_data.i2c = i2c_dev;
+		data->gpio_data.cfg = &cfg->gpio_cfg;
+		ret |= i2c_emul_register(i2c_dev, &data->gpio_data.emul);
+		i2c_common_emul_init(&data->gpio_data);
+	}
+
+	ret |= ps8xxx_emul_tcpc_reset(emul);
+
+	tcpci_emul_set_reg(emul, TCPC_REG_VENDOR_ID, PS8XXX_VENDOR_ID);
+	tcpci_emul_set_reg(emul, TCPC_REG_PRODUCT_ID, data->prod_id);
+	/* FW rev is never 0 in a working device. Set arbitrary FW rev. */
+	tcpci_emul_set_reg(emul, PS8XXX_REG_FW_REV, 0x31);
+
+	return ret;
+}
+
+#define PS8XXX_EMUL(n)                                                \
+	static struct ps8xxx_emul_data ps8xxx_emul_data_##n = {		\
+		.prod_id = PS8805_PRODUCT_ID,				\
+		.p0_data = {						\
+			.write_byte = ps8xxx_emul_p0_write_byte,	\
+			.read_byte = ps8xxx_emul_p0_read_byte,		\
+		},							\
+		.p1_data = {						\
+			.write_byte = ps8xxx_emul_p1_write_byte,	\
+			.read_byte = ps8xxx_emul_p1_read_byte,		\
+		},							\
+		.gpio_data = {						\
+			.write_byte = ps8xxx_emul_gpio_write_byte,	\
+			.read_byte = ps8xxx_emul_gpio_read_byte,	\
+		},							\
+	};    \
+                                                                      \
+	static const struct ps8xxx_emul_cfg ps8xxx_emul_cfg_##n = {	\
+		.p0_cfg = {						\
+			.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)), \
+			.data = &ps8xxx_emul_data_##n.p0_data,		\
+			.addr = DT_INST_PROP(n, p0_i2c_addr),		\
+		},							\
+		.p1_cfg = {						\
+			.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)), \
+			.data = &ps8xxx_emul_data_##n.p1_data,		\
+			.addr = DT_INST_PROP(n, p1_i2c_addr),		\
+		},							\
+		.gpio_cfg = {						\
+			.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)), \
+			.data = &ps8xxx_emul_data_##n.gpio_data,	\
+			.addr = DT_INST_PROP(n, gpio_i2c_addr),		\
+		},							\
+	}; \
+	TCPCI_EMUL_DEFINE(n, ps8xxx_emul_init, &ps8xxx_emul_cfg_##n,  \
+			  &ps8xxx_emul_data_##n, &i2c_ps8xxx_emul_api, NULL)
+
+DT_INST_FOREACH_STATUS_OKAY(PS8XXX_EMUL)
+
+#ifdef CONFIG_ZTEST_NEW_API
+#define PS8XXX_EMUL_RESET_RULE_BEFORE(n) \
+	ps8xxx_emul_tcpc_reset(EMUL_DT_GET(DT_DRV_INST(n)));
+static void ps8xxx_emul_reset_rule_before(const struct ztest_unit_test *test,
+					  void *data)
+{
+	ARG_UNUSED(test);
+	ARG_UNUSED(data);
+	DT_INST_FOREACH_STATUS_OKAY(PS8XXX_EMUL_RESET_RULE_BEFORE);
+}
+ZTEST_RULE(PS8XXX_emul_reset, ps8xxx_emul_reset_rule_before, NULL);
+#endif /* CONFIG_ZTEST_NEW_API */
+
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
diff --git a/zephyr/emul/tcpc/emul_rt1718s.c b/zephyr/emul/tcpc/emul_rt1718s.c
new file mode 100644
index 0000000000..bd8d81b767
--- /dev/null
+++ b/zephyr/emul/tcpc/emul_rt1718s.c
@@ -0,0 +1,472 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/tcpm/rt1718s.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_stub_device.h"
+#include "emul/tcpc/emul_rt1718s.h"
+#include "emul/tcpc/emul_tcpci.h"
+#include "tcpm/tcpci.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/i2c_emul.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/slist.h>
+#include <zephyr/ztest.h>
+
+#define DT_DRV_COMPAT cros_rt1718s_tcpc_emul
+
+LOG_MODULE_REGISTER(rt1718s_emul, CONFIG_TCPCI_EMUL_LOG_LEVEL);
+
+static bool is_valid_rt1718s_page1_register(int reg)
+{
+	switch (reg) {
+	case RT1718S_SYS_CTRL1:
+	case RT1718S_SYS_CTRL2:
+	case RT1718S_SYS_CTRL3:
+	case RT1718S_RT_MASK6:
+	case RT1718S_VCON_CTRL3:
+	case 0xCF: /* FOD function */
+	case RT1718S_RT_MASK1:
+	case RT1718S_VCONN_CONTROL_2:
+	case RT1718S_FRS_CTRL2:
+	case RT1718S_VBUS_CTRL_EN:
+	case RT1718S_GPIO_CTRL(RT1718S_GPIO1):
+	case RT1718S_GPIO_CTRL(RT1718S_GPIO2):
+	case RT1718S_GPIO_CTRL(RT1718S_GPIO3):
+		return true;
+	default:
+		return false;
+	}
+}
+
+static bool is_valid_rt1718s_page2_register(int reg)
+{
+	int combined_reg_address = (RT1718S_RT2 << 8) | reg;
+
+	switch (combined_reg_address) {
+	case RT1718S_RT2_SBU_CTRL_01:
+	case RT1718S_RT2_BC12_SNK_FUNC:
+	case RT1718S_RT2_DPDM_CTR1_DPDM_SET:
+	case RT1718S_RT2_VBUS_VOL_CTRL:
+	case RT1718S_VCON_CTRL4:
+		return true;
+	default:
+		return false;
+	}
+}
+
+static void add_access_history_entry(struct rt1718s_emul_data *rt1718s_data,
+				     int reg, uint8_t val)
+{
+	struct set_reg_entry_t *entry;
+
+	entry = malloc(sizeof(struct set_reg_entry_t));
+	entry->reg = reg;
+	entry->val = val;
+	entry->access_time = k_uptime_get();
+	sys_slist_append(&rt1718s_data->set_private_reg_history, &entry->node);
+}
+
+/**
+ * @brief Function called on reset
+ *
+ * @param emul Pointer to rt1718s emulator
+ */
+static void rt1718s_emul_reset(const struct emul *emul)
+{
+	struct rt1718s_emul_data *rt1718s_data = emul->data;
+
+	tcpci_emul_reset(emul);
+	memset(rt1718s_data->reg_page1, 0, sizeof(rt1718s_data->reg_page1));
+	memset(rt1718s_data->reg_page2, 0, sizeof(rt1718s_data->reg_page2));
+}
+
+int rt1718s_emul_get_reg(const struct emul *emul, int reg, uint16_t *val)
+{
+	uint8_t reg_addr;
+	uint8_t *reference_page;
+	struct rt1718s_emul_data *rt1718s_data = emul->data;
+
+	if ((reg >> 8) == RT1718S_RT2) {
+		reg_addr = reg & 0xFF;
+		reference_page = rt1718s_data->reg_page2;
+	} else if (is_valid_rt1718s_page1_register(reg)) {
+		reg_addr = reg;
+		reference_page = rt1718s_data->reg_page1;
+	} else {
+		return tcpci_emul_get_reg(emul, reg, val);
+	}
+
+	if (val == NULL || reg_addr > RT1718S_EMUL_REG_COUNT_PER_PAGE) {
+		return -EINVAL;
+	}
+
+	*val = reference_page[reg_addr];
+	return EC_SUCCESS;
+}
+
+int rt1718s_emul_set_reg(const struct emul *emul, int reg, uint16_t val)
+{
+	uint8_t reg_addr;
+	uint8_t *reference_page;
+	struct rt1718s_emul_data *rt1718s_data = emul->data;
+
+	if ((reg >> 8) == RT1718S_RT2) {
+		reg_addr = reg & 0xFF;
+		reference_page = rt1718s_data->reg_page2;
+	} else if (is_valid_rt1718s_page1_register(reg)) {
+		reg_addr = reg;
+		reference_page = rt1718s_data->reg_page1;
+	} else {
+		return tcpci_emul_set_reg(emul, reg, val);
+	}
+
+	if (reg_addr > RT1718S_EMUL_REG_COUNT_PER_PAGE) {
+		return -EINVAL;
+	}
+
+	reference_page[reg_addr] = val;
+	return EC_SUCCESS;
+}
+
+void rt1718s_emul_reset_set_history(const struct emul *emul)
+{
+	struct _snode *iter_node;
+	struct set_reg_entry_t *iter_entry;
+	struct rt1718s_emul_data *rt1718s_data = emul->data;
+
+	while (!sys_slist_is_empty(&(rt1718s_data->set_private_reg_history))) {
+		iter_node =
+			sys_slist_get(&(rt1718s_data->set_private_reg_history));
+		iter_entry = SYS_SLIST_CONTAINER(iter_node, iter_entry, node);
+		free(iter_entry);
+	}
+}
+
+void rt1718s_emul_set_device_id(const struct emul *emul, uint16_t device_id)
+{
+	switch (device_id) {
+	case RT1718S_DEVICE_ID_ES1:
+	case RT1718S_DEVICE_ID_ES2:
+		tcpci_emul_set_reg(emul, TCPC_REG_BCD_DEV, device_id);
+		break;
+	default:
+		break;
+	}
+}
+
+static int copy_reg_byte(uint8_t *dst, uint8_t src_reg[], int reg,
+			 int read_bytes)
+{
+	if ((reg + read_bytes) > RT1718S_EMUL_REG_COUNT_PER_PAGE ||
+	    dst == NULL) {
+		return -EIO;
+	}
+	*(dst + read_bytes) = src_reg[reg + read_bytes];
+	return EC_SUCCESS;
+}
+
+/**
+ * @brief Function called for each byte of read message from rt1718s emulator
+ *
+ * @param emul Pointer to I2C rt1718s emulator
+ * @param reg First byte of last write message
+ * @param val Pointer where byte to read should be stored
+ * @param bytes Number of bytes already read
+ *
+ * @return 0 on success
+ * @return -EIO on invalid read request
+ */
+static int rt1718s_emul_read_byte(const struct emul *emul, int reg,
+				  uint8_t *val, int read_bytes)
+{
+	struct rt1718s_emul_data *rt1718s_data = emul->data;
+	int current_page = rt1718s_data->current_page;
+
+	rt1718s_data->current_page = 1;
+
+	if (current_page == 2) {
+		if (reg != RT1718S_RT2) {
+			LOG_ERR("The page2 register is selected in previous "
+				"transaction, but the following read is to reg "
+				"%x instead of %x",
+				reg, RT1718S_RT2);
+			return -EIO;
+		}
+		return copy_reg_byte(val, rt1718s_data->reg_page2,
+				     rt1718s_data->current_page2_register,
+				     read_bytes);
+	} else if (is_valid_rt1718s_page1_register(reg)) {
+		return copy_reg_byte(val, rt1718s_data->reg_page1, reg,
+				     read_bytes);
+	} else {
+		return tcpci_emul_read_byte(emul, reg, val, read_bytes);
+	}
+}
+
+/**
+ * @brief Function called for each byte of read message from rt1718s emulator
+ *
+ * @param emul Pointer to I2C rt1718s emulator
+ * @param reg First byte of last write message
+ * @param val Pointer where byte to read should be stored
+ * @param bytes Number of bytes already read
+ *
+ * @return 0 on success
+ * @return -EIO on invalid read request
+ */
+
+static int rt1718s_emul_write_byte_page1(const struct emul *emul, int reg,
+					 uint8_t val, int bytes)
+{
+	struct rt1718s_emul_data *rt1718s_data = emul->data;
+
+	if (bytes == 2) {
+		/*
+		 * All register in page1 only has 1 byte, so the write should
+		 * not more than 2 bytes.
+		 */
+		return -EIO;
+	}
+	rt1718s_data->reg_page1[reg] = val;
+	add_access_history_entry(rt1718s_data, reg, val);
+
+	/* Software reset is triggered */
+	if (reg == RT1718S_SYS_CTRL3 && (val & RT1718S_SWRESET_MASK)) {
+		rt1718s_emul_reset(emul);
+	}
+
+	return EC_SUCCESS;
+}
+
+static int rt1718s_emul_write_byte_page2(const struct emul *emul, int reg,
+					 uint8_t val, int bytes)
+{
+	struct rt1718s_emul_data *rt1718s_data = emul->data;
+
+	if (bytes == 1) {
+		rt1718s_data->current_page = 2;
+
+		if (!is_valid_rt1718s_page2_register(val)) {
+			return -EIO;
+		}
+		rt1718s_data->current_page2_register = val;
+	} else if (bytes == 2) {
+		rt1718s_data->reg_page2[rt1718s_data->current_page2_register] =
+			val;
+		add_access_history_entry(
+			rt1718s_data,
+			(reg << 8) | rt1718s_data->current_page2_register, val);
+	} else {
+		/*
+		 * All register in page2 only has 1 byte, so the write should
+		 * not more than 3 bytes.
+		 */
+		return -EIO;
+	}
+
+	return EC_SUCCESS;
+}
+
+/**
+ * @brief Function called for each byte of write message to rt1718s emulator
+ *
+ * @param emul Pointer to I2C rt1718s emulator
+ * @param reg First byte of write message
+ * @param val Received byte of write message
+ * @param bytes Number of bytes already received
+ *
+ * @return 0 on success
+ * @return -EIO on invalid write request
+ */
+static int rt1718s_emul_write_byte(const struct emul *emul, int reg,
+				   uint8_t val, int bytes)
+{
+	struct rt1718s_emul_data *rt1718s_data = emul->data;
+
+	if (reg == RT1718S_RT2) {
+		return rt1718s_emul_write_byte_page2(emul, reg, val, bytes);
+	}
+
+	if (rt1718s_data->current_page == 2) {
+		return -EIO;
+	}
+
+	if (is_valid_rt1718s_page1_register(reg)) {
+		return rt1718s_emul_write_byte_page1(emul, reg, val, bytes);
+	} else {
+		return tcpci_emul_write_byte(emul, reg, val, bytes);
+	}
+}
+
+/**
+ * @brief Wrapper function of rt1718s_emul_write_byte which reset the current
+ *        register page if encounter error.
+ *
+ * @param emul Pointer to I2C rt1718s emulator
+ * @param reg First byte of write message
+ * @param val Received byte of write message
+ * @param bytes Number of bytes already received
+ *
+ * @return 0 on success
+ * @return -EIO on invalid write request
+ */
+static int rt1718s_emul_write_byte_wrapper(const struct emul *emul, int reg,
+					   uint8_t val, int bytes)
+{
+	int err;
+	struct rt1718s_emul_data *rt1718s_data = emul->data;
+
+	err = rt1718s_emul_write_byte(emul, reg, val, bytes);
+	if (err != EC_SUCCESS) {
+		rt1718s_data->current_page = 1;
+	}
+	return err;
+}
+
+/**
+ * @brief Function called on the end of write message to rt1718s emulator
+ *
+ * @param emul Pointer to I2C rt1718s emulator
+ * @param reg Register which is written
+ * @param msg_len Length of handled I2C message
+ *
+ * @return 0 on success
+ * @return -EIO on error
+ */
+static int rt1718s_emul_finish_write(const struct emul *emul, int reg,
+				     int msg_len)
+{
+	struct rt1718s_emul_data *rt1718s_data = emul->data;
+
+	if (rt1718s_data->current_page == 2) {
+		/* msg_len = 2 is selecting the register in page2. */
+		if (msg_len != 2) {
+			rt1718s_data->current_page = 1;
+		}
+		return EC_SUCCESS;
+	} else if (is_valid_rt1718s_page1_register(reg)) {
+		return EC_SUCCESS;
+	} else {
+		return tcpci_emul_handle_write(emul, reg, msg_len);
+	}
+}
+
+/**
+ * @brief Get currently accessed register.
+ *
+ * @param emul Pointer to I2C rt1718s emulator
+ * @param reg First byte of last write message
+ * @param bytes Number of bytes already handled from current message
+ * @param read If currently handled is read message
+ *
+ * @return Currently accessed register
+ */
+static int rt1718s_emul_access_reg(const struct emul *emul, int reg, int bytes,
+				   bool read)
+{
+	struct rt1718s_emul_data *rt1718s_data = emul->data;
+
+	if (rt1718s_data->current_page == 2) {
+		return rt1718s_data->current_page2_register;
+	} else {
+		return reg;
+	}
+}
+
+/**
+ * @brief Set up a new rt1718s emulator
+ *
+ * This should be called for each rt1718s device that needs to be
+ * emulated.
+ *
+ * @param emul Emulation information
+ * @param parent Device to emulate
+ *
+ * @return 0 indicating success (always)
+ */
+static int rt1718s_emul_init(const struct emul *emul,
+			     const struct device *parent)
+{
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct rt1718s_emul_data *rt1718s_data = emul->data;
+	struct tcpci_ctx *tcpci_ctx = tcpc_data->tcpci_ctx;
+	const struct device *i2c_dev;
+
+	i2c_dev = parent;
+
+	tcpci_ctx->common.write_byte = rt1718s_emul_write_byte_wrapper;
+	tcpci_ctx->common.finish_write = rt1718s_emul_finish_write;
+	tcpci_ctx->common.read_byte = rt1718s_emul_read_byte;
+	tcpci_ctx->common.access_reg = rt1718s_emul_access_reg;
+
+	tcpci_emul_i2c_init(emul, i2c_dev);
+
+	rt1718s_emul_reset(emul);
+	sys_slist_init(&(rt1718s_data->set_private_reg_history));
+
+	return 0;
+}
+
+static int i2c_rt1718s_emul_transfer(const struct emul *target,
+				     struct i2c_msg *msgs, int num_msgs,
+				     int addr)
+{
+	struct tcpc_emul_data *tcpc_data = target->data;
+	struct tcpci_ctx *tcpci_ctx = tcpc_data->tcpci_ctx;
+
+	return i2c_common_emul_transfer_workhorse(target, &tcpci_ctx->common,
+						  &tcpc_data->i2c_cfg, msgs,
+						  num_msgs, addr);
+}
+
+struct i2c_emul_api i2c_rt1718s_emul_api = {
+	.transfer = i2c_rt1718s_emul_transfer,
+};
+
+#define RT1718S_EMUL(n)                                                   \
+	static uint8_t tcpci_emul_tx_buf_##n[128];                        \
+	static struct tcpci_emul_msg tcpci_emul_tx_msg_##n = {            \
+		.buf = tcpci_emul_tx_buf_##n,                             \
+	};                                                                \
+	static struct tcpci_ctx tcpci_ctx##n = {                          \
+		.tx_msg = &tcpci_emul_tx_msg_##n,                         \
+		.error_on_ro_write = true,                                \
+		.error_on_rsvd_write = true,                              \
+		.irq_gpio = GPIO_DT_SPEC_INST_GET_OR(n, irq_gpios, {}),   \
+	};                                                                \
+	static struct rt1718s_emul_data rt1718s_emul_data_##n = {       \
+		.embedded_tcpc_emul_data = {                            \
+			.tcpci_ctx = &tcpci_ctx##n,                     \
+			.i2c_cfg = {                                    \
+				.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)),\
+				.data = &tcpci_ctx##n.common,\
+				.addr = DT_INST_REG_ADDR(n), \
+			}                                    \
+		},                                           \
+		.current_page = 1,                           \
+	}; \
+	EMUL_DT_INST_DEFINE(n, rt1718s_emul_init, &rt1718s_emul_data_##n, \
+			    NULL, &i2c_rt1718s_emul_api, NULL)
+
+DT_INST_FOREACH_STATUS_OKAY(RT1718S_EMUL)
+
+#ifdef CONFIG_ZTEST_NEW_API
+#define RT1718S_EMUL_RESET_RULE_BEFORE(n) \
+	rt1718s_emul_reset(EMUL_DT_GET(DT_DRV_INST(n)))
+static void rt1718s_emul_reset_rule_before(const struct ztest_unit_test *test,
+					   void *data)
+{
+	ARG_UNUSED(test);
+	ARG_UNUSED(data);
+	DT_INST_FOREACH_STATUS_OKAY(RT1718S_EMUL_RESET_RULE_BEFORE);
+}
+ZTEST_RULE(RT1718S_emul_reset, rt1718s_emul_reset_rule_before, NULL);
+#endif /* CONFIG_ZTEST_NEW_API */
+
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
diff --git a/zephyr/emul/tcpc/emul_tcpci.c b/zephyr/emul/tcpc/emul_tcpci.c
new file mode 100644
index 0000000000..0f619991f7
--- /dev/null
+++ b/zephyr/emul/tcpc/emul_tcpci.c
@@ -0,0 +1,1506 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "emul/emul_common_i2c.h"
+#include "emul/tcpc/emul_tcpci.h"
+#include "tcpm/tcpci.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/i2c_emul.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/byteorder.h>
+
+LOG_MODULE_REGISTER(tcpci_emul, CONFIG_TCPCI_EMUL_LOG_LEVEL);
+
+/**
+ * @brief Returns number of bytes in specific register
+ *
+ * @param reg Register address
+ *
+ * @return Number of bytes
+ */
+static int tcpci_emul_reg_bytes(int reg)
+{
+	switch (reg) {
+	case TCPC_REG_VENDOR_ID:
+	case TCPC_REG_PRODUCT_ID:
+	case TCPC_REG_BCD_DEV:
+	case TCPC_REG_TC_REV:
+	case TCPC_REG_PD_REV:
+	case TCPC_REG_PD_INT_REV:
+	case TCPC_REG_ALERT:
+	case TCPC_REG_ALERT_MASK:
+	case TCPC_REG_DEV_CAP_1:
+	case TCPC_REG_DEV_CAP_2:
+	case TCPC_REG_GENERIC_TIMER:
+	case TCPC_REG_VBUS_VOLTAGE:
+	case TCPC_REG_VBUS_SINK_DISCONNECT_THRESH:
+	case TCPC_REG_VBUS_STOP_DISCHARGE_THRESH:
+	case TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG:
+	case TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG:
+	case TCPC_REG_VBUS_NONDEFAULT_TARGET:
+		return 2;
+	}
+
+	/* Assume that other registers are one byte */
+	return 1;
+}
+
+/**
+ * @brief Get value of given register of TCPCI
+ *
+ * @param ctx Pointer to TCPCI context
+ * @param reg Register address
+ * @param val Pointer where value should be stored
+ *
+ * @return 0 on success
+ * @return -EINVAL when register is out of range defined in TCPCI specification
+ *                 or val is NULL
+ */
+static int get_reg(const struct tcpci_ctx *ctx, int reg, uint16_t *val)
+{
+	int byte;
+
+	if (reg < 0 || reg > TCPCI_EMUL_REG_COUNT || val == NULL) {
+		return -EINVAL;
+	}
+
+	*val = 0;
+
+	byte = tcpci_emul_reg_bytes(reg);
+	if (byte == 2) {
+		*val = sys_get_le16(&ctx->reg[reg]);
+	} else {
+		*val = ctx->reg[reg];
+	}
+
+	return 0;
+}
+
+/** Check description in emul_tcpci.h */
+int tcpci_emul_get_reg(const struct emul *emul, int reg, uint16_t *val)
+{
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx;
+
+	return get_reg(ctx, reg, val);
+}
+
+/**
+ * @brief Set value of given register of TCPCI
+ *
+ * @param ctx Pointer to TCPCI context
+ * @param reg Register address which value will be changed
+ * @param val New value of the register
+ *
+ * @return 0 on success
+ * @return -EINVAL when register is out of range defined in TCPCI specification
+ */
+static int set_reg(struct tcpci_ctx *ctx, int reg, uint16_t val)
+{
+	uint16_t update_alert = 0;
+	uint16_t alert;
+	int byte;
+
+	if (reg < 0 || reg > TCPCI_EMUL_REG_COUNT) {
+		return -EINVAL;
+	}
+
+	/* Changing some registers has impact on alert register */
+	switch (reg) {
+	case TCPC_REG_POWER_STATUS:
+		update_alert = TCPC_REG_ALERT_POWER_STATUS;
+		break;
+	case TCPC_REG_FAULT_STATUS:
+		update_alert = TCPC_REG_ALERT_FAULT;
+		break;
+	case TCPC_REG_EXT_STATUS:
+		update_alert = TCPC_REG_ALERT_EXT_STATUS;
+		break;
+	case TCPC_REG_ALERT_EXT:
+		update_alert = TCPC_REG_ALERT_ALERT_EXT;
+		break;
+	}
+
+	if (update_alert != 0) {
+		get_reg(ctx, TCPC_REG_ALERT, &alert);
+		set_reg(ctx, TCPC_REG_ALERT, alert | update_alert);
+	}
+
+	byte = tcpci_emul_reg_bytes(reg);
+	if (byte == 2) {
+		sys_put_le16(val, &ctx->reg[reg]);
+	} else {
+		ctx->reg[reg] = val;
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Update value of given register of TCPCI
+ *
+ * @param ctx Pointer to TCPCI context
+ * @param reg Register address which value will be changed
+ * @param val New value of the register
+ * @param mask Mask to apply with the val
+ *
+ * @return 0 on success
+ * @return -EINVAL when register is out of range defined in TCPCI specification
+ */
+static int update_reg(struct tcpci_ctx *ctx, int reg, uint16_t val,
+		      uint16_t mask)
+{
+	uint16_t v;
+
+	if (get_reg(ctx, reg, &v)) {
+		return -EINVAL;
+	}
+
+	v &= ~mask;
+	v |= (val & mask);
+
+	if (set_reg(ctx, reg, v)) {
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/** Check description in emul_tcpci.h */
+int tcpci_emul_set_reg(const struct emul *emul, int reg, uint16_t val)
+{
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx;
+
+	return set_reg(ctx, reg, val);
+}
+
+/**
+ * @brief Check if alert line should be active based on alert registers and
+ *        masks
+ *
+ * @param ctx Pointer to TCPCI context
+ *
+ * @return State of alert line
+ */
+static bool tcpci_emul_check_int(const struct tcpci_ctx *ctx)
+{
+	uint16_t alert_mask;
+	uint16_t alert;
+
+	get_reg(ctx, TCPC_REG_ALERT, &alert);
+	get_reg(ctx, TCPC_REG_ALERT_MASK, &alert_mask);
+
+	/*
+	 * For nested interrupts alert group bit and alert register bit has to
+	 * be unmasked
+	 */
+	if (alert & alert_mask & TCPC_REG_ALERT_ALERT_EXT &&
+	    ctx->reg[TCPC_REG_ALERT_EXT] &
+		    ctx->reg[TCPC_REG_ALERT_EXTENDED_MASK]) {
+		return true;
+	}
+
+	if (alert & alert_mask & TCPC_REG_ALERT_EXT_STATUS &&
+	    ctx->reg[TCPC_REG_EXT_STATUS] &
+		    ctx->reg[TCPC_REG_EXT_STATUS_MASK]) {
+		return true;
+	}
+
+	if (alert & alert_mask & TCPC_REG_ALERT_FAULT &&
+	    ctx->reg[TCPC_REG_FAULT_STATUS] &
+		    ctx->reg[TCPC_REG_FAULT_STATUS_MASK]) {
+		return true;
+	}
+
+	if (alert & alert_mask & TCPC_REG_ALERT_POWER_STATUS &&
+	    ctx->reg[TCPC_REG_POWER_STATUS] &
+		    ctx->reg[TCPC_REG_POWER_STATUS_MASK]) {
+		return true;
+	}
+
+	/* Nested alerts are handled above */
+	alert &= ~(TCPC_REG_ALERT_ALERT_EXT | TCPC_REG_ALERT_EXT_STATUS |
+		   TCPC_REG_ALERT_FAULT | TCPC_REG_ALERT_POWER_STATUS);
+	if (alert & alert_mask) {
+		return true;
+	}
+
+	return false;
+}
+
+/**
+ * @brief If alert callback is provided, call it with current alert line state
+ *
+ * @param emul Pointer to TCPC emulator
+ *
+ * @return 0 for success, or non-0 for errors.
+ */
+static int tcpci_emul_alert_changed(const struct emul *emul)
+{
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx;
+	int rc;
+	bool alert_is_active = tcpci_emul_check_int(ctx);
+
+	/** Trigger GPIO. */
+	if (ctx->irq_gpio.port != NULL) {
+		/* Triggers on edge falling, so set to 0 when there is an alert.
+		 */
+		rc = gpio_emul_input_set(ctx->irq_gpio.port, ctx->irq_gpio.pin,
+					 alert_is_active ? 0 : 1);
+		if (rc != 0)
+			return rc;
+	}
+
+	/* Nothing to do */
+	if (ctx->alert_callback == NULL) {
+		return 0;
+	}
+
+	ctx->alert_callback(emul, alert_is_active, ctx->alert_callback_data);
+	return 0;
+}
+
+/**
+ * @brief Load next rx message and inform partner which message was consumed
+ *        by TCPC
+ *
+ * @param emul Pointer to TCPC emulator
+ *
+ * @return 0 when there is no new message to load
+ * @return 1 when new rx message is loaded
+ */
+static int tcpci_emul_get_next_rx_msg(const struct emul *emul)
+{
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx;
+	struct tcpci_emul_msg *consumed_msg;
+
+	if (ctx->rx_msg == NULL) {
+		return 0;
+	}
+
+	consumed_msg = ctx->rx_msg;
+	ctx->rx_msg = consumed_msg->next;
+
+	/* Inform partner */
+	if (ctx->partner && ctx->partner->rx_consumed) {
+		ctx->partner->rx_consumed(emul, ctx->partner, consumed_msg);
+	}
+
+	/* Prepare new loaded message */
+	if (ctx->rx_msg) {
+		ctx->rx_msg->idx = 0;
+
+		return 1;
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Reset mask registers that are reset upon receiving or transmitting
+ *        Hard Reset message.
+ *
+ * @param ctx Pointer to TCPCI context
+ */
+static void tcpci_emul_reset_mask_regs(struct tcpci_ctx *ctx)
+{
+	ctx->reg[TCPC_REG_ALERT_MASK] = 0xff;
+	ctx->reg[TCPC_REG_ALERT_MASK + 1] = 0x7f;
+	ctx->reg[TCPC_REG_POWER_STATUS_MASK] = 0xff;
+	ctx->reg[TCPC_REG_EXT_STATUS_MASK] = 0x01;
+	ctx->reg[TCPC_REG_ALERT_EXTENDED_MASK] = 0x07;
+}
+
+/**
+ * @brief Perform actions that are expected by TCPC on disabling PD message
+ *        delivery (clear RECEIVE_DETECT register and clear already received
+ *        messages in buffer)
+ *
+ * @param emul Pointer to TCPC emulator
+ */
+static void tcpci_emul_disable_pd_msg_delivery(const struct emul *emul)
+{
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx;
+
+	set_reg(ctx, TCPC_REG_RX_DETECT, 0);
+	/* Clear received messages */
+	while (tcpci_emul_get_next_rx_msg(emul))
+		;
+}
+
+/** Check description in emul_tcpci.h */
+int tcpci_emul_add_rx_msg(const struct emul *emul,
+			  struct tcpci_emul_msg *rx_msg, bool alert)
+{
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx;
+	uint16_t rx_detect_mask;
+	uint16_t rx_detect;
+	uint16_t dev_cap_2;
+	uint16_t alert_reg;
+	int rc;
+
+	/* Acquire lock to prevent race conditions with TCPM accessing I2C */
+	rc = i2c_common_emul_lock_data(&ctx->common, K_FOREVER);
+	if (rc != 0) {
+		LOG_ERR("Failed to acquire TCPCI lock");
+		return rc;
+	}
+
+	switch (rx_msg->sop_type) {
+	case TCPCI_MSG_SOP:
+		rx_detect_mask = TCPC_REG_RX_DETECT_SOP;
+		break;
+	case TCPCI_MSG_SOP_PRIME:
+		rx_detect_mask = TCPC_REG_RX_DETECT_SOPP;
+		break;
+	case TCPCI_MSG_SOP_PRIME_PRIME:
+		rx_detect_mask = TCPC_REG_RX_DETECT_SOPPP;
+		break;
+	case TCPCI_MSG_SOP_DEBUG_PRIME:
+		rx_detect_mask = TCPC_REG_RX_DETECT_SOPP_DBG;
+		break;
+	case TCPCI_MSG_SOP_DEBUG_PRIME_PRIME:
+		rx_detect_mask = TCPC_REG_RX_DETECT_SOPPP_DBG;
+		break;
+	case TCPCI_MSG_TX_HARD_RESET:
+		rx_detect_mask = TCPC_REG_RX_DETECT_HRST;
+		break;
+	case TCPCI_MSG_CABLE_RESET:
+		rx_detect_mask = TCPC_REG_RX_DETECT_CABLE_RST;
+		break;
+	default:
+		i2c_common_emul_unlock_data(&ctx->common);
+		return -EINVAL;
+	}
+
+	get_reg(ctx, TCPC_REG_RX_DETECT, &rx_detect);
+	if (!(rx_detect & rx_detect_mask)) {
+		/*
+		 * TCPCI will not respond with GoodCRC, so from partner emulator
+		 * point of view it failed to send message
+		 */
+		i2c_common_emul_unlock_data(&ctx->common);
+		return TCPCI_EMUL_TX_FAILED;
+	}
+
+	get_reg(ctx, TCPC_REG_ALERT, &alert_reg);
+
+	/* Handle HardReset */
+	if (rx_msg->sop_type == TCPCI_MSG_TX_HARD_RESET) {
+		tcpci_emul_disable_pd_msg_delivery(emul);
+		tcpci_emul_reset_mask_regs(ctx);
+
+		alert_reg |= TCPC_REG_ALERT_RX_HARD_RST;
+		set_reg(ctx, TCPC_REG_ALERT, alert_reg);
+		rc = tcpci_emul_alert_changed(emul);
+
+		i2c_common_emul_unlock_data(&ctx->common);
+		return rc;
+	}
+
+	/* Handle CableReset */
+	if (rx_msg->sop_type == TCPCI_MSG_CABLE_RESET) {
+		tcpci_emul_disable_pd_msg_delivery(emul);
+		/* Rest of CableReset handling is the same as SOP* message */
+	}
+
+	if (ctx->rx_msg == NULL) {
+		get_reg(ctx, TCPC_REG_DEV_CAP_2, &dev_cap_2);
+		if ((!(dev_cap_2 & TCPC_REG_DEV_CAP_2_LONG_MSG) &&
+		     rx_msg->cnt > 31) ||
+		    rx_msg->cnt > 265) {
+			LOG_ERR("Too long first message (%d)", rx_msg->cnt);
+			i2c_common_emul_unlock_data(&ctx->common);
+			return -EINVAL;
+		}
+
+		ctx->rx_msg = rx_msg;
+	} else if (ctx->rx_msg->next == NULL) {
+		if (rx_msg->cnt > 31) {
+			LOG_ERR("Too long second message (%d)", rx_msg->cnt);
+			i2c_common_emul_unlock_data(&ctx->common);
+			return -EINVAL;
+		}
+
+		ctx->rx_msg->next = rx_msg;
+		if (alert) {
+			alert_reg |= TCPC_REG_ALERT_RX_BUF_OVF;
+		}
+	} else {
+		LOG_ERR("Cannot setup third message");
+		i2c_common_emul_unlock_data(&ctx->common);
+		return -EINVAL;
+	}
+
+	if (alert) {
+		if (rx_msg->cnt > 133) {
+			alert_reg |= TCPC_REG_ALERT_RX_BEGINNING;
+		}
+
+		alert_reg |= TCPC_REG_ALERT_RX_STATUS;
+		set_reg(ctx, TCPC_REG_ALERT, alert_reg);
+
+		rc = tcpci_emul_alert_changed(emul);
+		if (rc != 0) {
+			i2c_common_emul_unlock_data(&ctx->common);
+			return rc;
+		}
+	}
+
+	rx_msg->next = NULL;
+	rx_msg->idx = 0;
+
+	i2c_common_emul_unlock_data(&ctx->common);
+	return TCPCI_EMUL_TX_SUCCESS;
+}
+
+/** Check description in emul_tcpci.h */
+struct tcpci_emul_msg *tcpci_emul_get_tx_msg(const struct emul *emul)
+{
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx;
+
+	return ctx->tx_msg;
+}
+
+/** Check description in emul_tcpci.h */
+void tcpci_emul_set_rev(const struct emul *emul, enum tcpci_emul_rev rev)
+{
+	switch (rev) {
+	case TCPCI_EMUL_REV1_0_VER1_0:
+		tcpci_emul_set_reg(emul, TCPC_REG_PD_INT_REV,
+				   (TCPC_REG_PD_INT_REV_REV_1_0 << 8) |
+					   TCPC_REG_PD_INT_REV_VER_1_0);
+		return;
+	case TCPCI_EMUL_REV2_0_VER1_1:
+		tcpci_emul_set_reg(emul, TCPC_REG_PD_INT_REV,
+				   (TCPC_REG_PD_INT_REV_REV_2_0 << 8) |
+					   TCPC_REG_PD_INT_REV_VER_1_1);
+		return;
+	}
+}
+
+void tcpci_emul_set_vbus_voltage(const struct emul *emul, uint32_t vbus_mv)
+{
+	uint16_t meas;
+	uint16_t scale = 0;
+
+	__ASSERT(!(vbus_mv % TCPC_REG_VBUS_VOLTAGE_LSB),
+		 "vbus_mv must be divisible by %d (%d)",
+		 TCPC_REG_VBUS_VOLTAGE_LSB, vbus_mv);
+
+	meas = vbus_mv / TCPC_REG_VBUS_VOLTAGE_LSB;
+
+	while (meas >= (1 << 10) && scale < 3) {
+		__ASSERT(!(meas & 1), "vbus_mv %d does not fit into the reg.",
+			 vbus_mv);
+		meas >>= 1;
+		scale += 1;
+	}
+	__ASSERT(scale < 3, "scale %d, meas %d doesn't fit into the reg.",
+		 scale, meas);
+
+	tcpci_emul_set_reg(emul, TCPC_REG_VBUS_VOLTAGE, (scale << 10) | meas);
+}
+
+/** Check description in emul_tcpci.h */
+void tcpci_emul_set_alert_callback(const struct emul *emul,
+				   tcpci_emul_alert_state_func alert_callback,
+				   void *alert_callback_data)
+{
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx;
+
+	ctx->alert_callback = alert_callback;
+	ctx->alert_callback_data = alert_callback_data;
+}
+
+/** Check description in emul_tcpci.h */
+void tcpci_emul_set_partner_ops(const struct emul *emul,
+				const struct tcpci_emul_partner_ops *partner)
+{
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx;
+
+	ctx->partner = partner;
+}
+
+/**
+ * @brief Get detected voltage for given CC resistor
+ *
+ * @param res CC pull resistor value
+ * @param volt Voltage applied by port partner
+ *
+ * @return Voltage visible at CC resistor side
+ */
+static enum tcpc_cc_voltage_status
+tcpci_emul_detected_volt_for_res(enum tcpc_cc_pull res,
+				 enum tcpc_cc_voltage_status volt)
+{
+	switch (res) {
+	case TYPEC_CC_RD:
+		switch (volt) {
+		/* As Rd we cannot detect another Rd or Ra */
+		case TYPEC_CC_VOLT_RA:
+		case TYPEC_CC_VOLT_RD:
+			return TYPEC_CC_VOLT_OPEN;
+		default:
+			return volt;
+		}
+	case TYPEC_CC_RP:
+		switch (volt) {
+		/* As Rp we cannot detect another Rp */
+		case TYPEC_CC_VOLT_RP_DEF:
+		case TYPEC_CC_VOLT_RP_1_5:
+		case TYPEC_CC_VOLT_RP_3_0:
+			return TYPEC_CC_VOLT_OPEN;
+		default:
+			return volt;
+		}
+	default:
+		/* As Ra or open we cannot detect anything */
+		return TYPEC_CC_VOLT_OPEN;
+	}
+}
+
+/** Check description in emul_tcpci.h */
+int tcpci_emul_connect_partner(const struct emul *emul,
+			       enum pd_power_role partner_power_role,
+			       enum tcpc_cc_voltage_status partner_cc1,
+			       enum tcpc_cc_voltage_status partner_cc2,
+			       enum tcpc_cc_polarity polarity)
+{
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx;
+	uint16_t cc_status, alert, role_ctrl;
+	enum tcpc_cc_voltage_status cc1_v, cc2_v;
+	enum tcpc_cc_pull cc1_r, cc2_r;
+	int rc;
+
+	if (polarity == POLARITY_CC1) {
+		cc1_v = partner_cc1;
+		cc2_v = partner_cc2;
+	} else {
+		cc1_v = partner_cc2;
+		cc2_v = partner_cc1;
+	}
+
+	get_reg(ctx, TCPC_REG_CC_STATUS, &cc_status);
+	if (TCPC_REG_CC_STATUS_LOOK4CONNECTION(cc_status)) {
+		/* Change resistors values in case of DRP toggling */
+		if (partner_power_role == PD_ROLE_SOURCE) {
+			/* TCPCI is sink */
+			cc1_r = TYPEC_CC_RD;
+			cc2_r = TYPEC_CC_RD;
+		} else {
+			/* TCPCI is src */
+			cc1_r = TYPEC_CC_RP;
+			cc2_r = TYPEC_CC_RP;
+		}
+	} else {
+		/* Use role control resistors values otherwise */
+		get_reg(ctx, TCPC_REG_ROLE_CTRL, &role_ctrl);
+		cc1_r = TCPC_REG_ROLE_CTRL_CC1(role_ctrl);
+		cc2_r = TCPC_REG_ROLE_CTRL_CC2(role_ctrl);
+	}
+
+	cc1_v = tcpci_emul_detected_volt_for_res(cc1_r, cc1_v);
+	cc2_v = tcpci_emul_detected_volt_for_res(cc2_r, cc2_v);
+
+	/* If CC status is TYPEC_CC_VOLT_RP_*, then BIT(2) is ignored */
+	cc_status = TCPC_REG_CC_STATUS_SET(
+		partner_power_role == PD_ROLE_SOURCE ? 1 : 0, cc2_v, cc1_v);
+	set_reg(ctx, TCPC_REG_CC_STATUS, cc_status);
+	get_reg(ctx, TCPC_REG_ALERT, &alert);
+	set_reg(ctx, TCPC_REG_ALERT, alert | TCPC_REG_ALERT_CC_STATUS);
+
+	if (partner_power_role == PD_ROLE_SOURCE) {
+		rc = tcpci_emul_set_vbus_level(emul, VBUS_PRESENT);
+		if (rc)
+			return rc;
+	}
+
+	tcpci_emul_alert_changed(emul);
+
+	return 0;
+}
+
+/** Check description in emul_tcpci.h */
+int tcpci_emul_disconnect_partner(const struct emul *emul)
+{
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx;
+	uint16_t val;
+	uint16_t term;
+	int rc;
+
+	tcpci_emul_disable_pd_msg_delivery(emul);
+	if (ctx->partner && ctx->partner->disconnect) {
+		ctx->partner->disconnect(emul, ctx->partner);
+	}
+	ctx->partner = NULL;
+
+	/* Set both CC lines to open to indicate disconnect. */
+	rc = get_reg(ctx, TCPC_REG_CC_STATUS, &val);
+	if (rc != 0)
+		return rc;
+
+	term = TCPC_REG_CC_STATUS_TERM(val);
+
+	rc = set_reg(ctx, TCPC_REG_CC_STATUS,
+		     TCPC_REG_CC_STATUS_SET(term, TYPEC_CC_VOLT_OPEN,
+					    TYPEC_CC_VOLT_OPEN));
+	if (rc != 0)
+		return rc;
+
+	ctx->reg[TCPC_REG_ALERT] |= TCPC_REG_ALERT_CC_STATUS;
+	rc = tcpci_emul_alert_changed(emul);
+	if (rc != 0)
+		return rc;
+	/* TODO: Wait until DisableSourceVbus (TCPC_REG_COMMAND_SRC_CTRL_LOW?),
+	 * and then set VBUS present = 0 and vSafe0V = 1 after appropriate
+	 * delays.
+	 */
+
+	/* Clear VBUS present in case if source partner is disconnected */
+	rc = tcpci_emul_set_vbus_level(emul, VBUS_REMOVED);
+	if (rc != 0)
+		return rc;
+
+	return 0;
+}
+
+/** Check description in emul_tcpci.h */
+void tcpci_emul_partner_msg_status(const struct emul *emul,
+				   enum tcpci_emul_tx_status status)
+{
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx;
+	uint16_t alert;
+	uint16_t tx_status_alert;
+
+	switch (status) {
+	case TCPCI_EMUL_TX_SUCCESS:
+		tx_status_alert = TCPC_REG_ALERT_TX_SUCCESS;
+		break;
+	case TCPCI_EMUL_TX_DISCARDED:
+		tx_status_alert = TCPC_REG_ALERT_TX_DISCARDED;
+		break;
+	case TCPCI_EMUL_TX_FAILED:
+		tx_status_alert = TCPC_REG_ALERT_TX_FAILED;
+		break;
+	case TCPCI_EMUL_TX_CABLE_HARD_RESET:
+		tx_status_alert = TCPC_REG_ALERT_TX_SUCCESS |
+				  TCPC_REG_ALERT_TX_FAILED;
+		break;
+	default:
+		__ASSERT(0, "Invalid partner TX status 0x%x", status);
+		return;
+	}
+
+	get_reg(ctx, TCPC_REG_ALERT, &alert);
+	set_reg(ctx, TCPC_REG_ALERT, alert | tx_status_alert);
+	tcpci_emul_alert_changed(emul);
+}
+
+/** Mask reserved bits in each register of TCPCI */
+static const uint8_t tcpci_emul_rsvd_mask[] = {
+	[TCPC_REG_VENDOR_ID] = 0x00,
+	[TCPC_REG_VENDOR_ID + 1] = 0x00,
+	[TCPC_REG_PRODUCT_ID] = 0x00,
+	[TCPC_REG_PRODUCT_ID + 1] = 0x00,
+	[TCPC_REG_BCD_DEV] = 0x00,
+	[TCPC_REG_BCD_DEV + 1] = 0xff,
+	[TCPC_REG_TC_REV] = 0x00,
+	[TCPC_REG_TC_REV + 1] = 0x00,
+	[TCPC_REG_PD_REV] = 0x00,
+	[TCPC_REG_PD_REV + 1] = 0x00,
+	[TCPC_REG_PD_INT_REV] = 0x00,
+	[TCPC_REG_PD_INT_REV + 1] = 0x00,
+	[0x0c ... 0x0f] = 0xff, /* Reserved */
+	[TCPC_REG_ALERT] = 0x00,
+	[TCPC_REG_ALERT + 1] = 0x00,
+	[TCPC_REG_ALERT_MASK] = 0x00,
+	[TCPC_REG_ALERT_MASK + 1] = 0x00,
+	[TCPC_REG_POWER_STATUS_MASK] = 0x00,
+	[TCPC_REG_FAULT_STATUS_MASK] = 0x00,
+	[TCPC_REG_EXT_STATUS_MASK] = 0xfe,
+	[TCPC_REG_ALERT_EXTENDED_MASK] = 0xf8,
+	[TCPC_REG_CONFIG_STD_OUTPUT] = 0x00,
+	[TCPC_REG_TCPC_CTRL] = 0x00,
+	[TCPC_REG_ROLE_CTRL] = 0x80,
+	[TCPC_REG_FAULT_CTRL] = 0x80,
+	[TCPC_REG_POWER_CTRL] = 0x00,
+	[TCPC_REG_CC_STATUS] = 0xc0,
+	[TCPC_REG_POWER_STATUS] = 0x00,
+	[TCPC_REG_FAULT_STATUS] = 0x00,
+	[TCPC_REG_EXT_STATUS] = 0xfe,
+	[TCPC_REG_ALERT_EXT] = 0xf8,
+	[0x22] = 0xff, /* Reserved */
+	[TCPC_REG_COMMAND] = 0x00,
+	[TCPC_REG_DEV_CAP_1] = 0x00,
+	[TCPC_REG_DEV_CAP_1 + 1] = 0x00,
+	[TCPC_REG_DEV_CAP_2] = 0x80,
+	[TCPC_REG_DEV_CAP_2 + 1] = 0x00,
+	[TCPC_REG_STD_INPUT_CAP] = 0xe0,
+	[TCPC_REG_STD_OUTPUT_CAP] = 0x00,
+	[TCPC_REG_CONFIG_EXT_1] = 0xfc,
+	[0x2b] = 0xff, /* Reserved */
+	[TCPC_REG_GENERIC_TIMER] = 0x00,
+	[TCPC_REG_GENERIC_TIMER + 1] = 0x00,
+	[TCPC_REG_MSG_HDR_INFO] = 0xe0,
+	[TCPC_REG_RX_DETECT] = 0x00,
+	[TCPC_REG_RX_BUFFER... 0x4f] = 0x00,
+	[TCPC_REG_TRANSMIT... 0x69] = 0x00,
+	[TCPC_REG_VBUS_VOLTAGE] = 0xf0,
+	[TCPC_REG_VBUS_VOLTAGE + 1] = 0x00,
+	[TCPC_REG_VBUS_SINK_DISCONNECT_THRESH] = 0x00,
+	[TCPC_REG_VBUS_SINK_DISCONNECT_THRESH + 1] = 0xfc,
+	[TCPC_REG_VBUS_STOP_DISCHARGE_THRESH] = 0x00,
+	[TCPC_REG_VBUS_STOP_DISCHARGE_THRESH + 1] = 0xfc,
+	[TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG] = 0x00,
+	[TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG + 1] = 0xfc,
+	[TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG] = 0x00,
+	[TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG + 1] = 0xfc,
+	[TCPC_REG_VBUS_NONDEFAULT_TARGET] = 0x00,
+	[TCPC_REG_VBUS_NONDEFAULT_TARGET + 1] = 0x00,
+	[0x7c ... 0x7f] = 0xff, /* Reserved */
+	[0x80 ... TCPCI_EMUL_REG_COUNT - 1] = 0x00,
+};
+
+/**
+ * @brief Reset role control and header info registers to default values.
+ *
+ * @param ctx Pointer to TCPCI context
+ */
+static void tcpci_emul_reset_role_ctrl(struct tcpci_ctx *ctx)
+{
+	uint16_t dev_cap_1;
+
+	get_reg(ctx, TCPC_REG_DEV_CAP_1, &dev_cap_1);
+	switch (dev_cap_1 & TCPC_REG_DEV_CAP_1_PWRROLE_MASK) {
+	case TCPC_REG_DEV_CAP_1_PWRROLE_SRC_OR_SNK:
+	case TCPC_REG_DEV_CAP_1_PWRROLE_SNK:
+	case TCPC_REG_DEV_CAP_1_PWRROLE_SNK_ACC:
+		ctx->reg[TCPC_REG_ROLE_CTRL] = 0x0a;
+		ctx->reg[TCPC_REG_MSG_HDR_INFO] = 0x04;
+		break;
+	case TCPC_REG_DEV_CAP_1_PWRROLE_SRC:
+		/* Dead batter */
+		ctx->reg[TCPC_REG_ROLE_CTRL] = 0x05;
+		ctx->reg[TCPC_REG_MSG_HDR_INFO] = 0x0d;
+		break;
+	case TCPC_REG_DEV_CAP_1_PWRROLE_DRP:
+		/* Dead batter and dbg acc ind */
+		ctx->reg[TCPC_REG_ROLE_CTRL] = 0x4a;
+		ctx->reg[TCPC_REG_MSG_HDR_INFO] = 0x04;
+		break;
+	case TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP_ADPT_CBL:
+	case TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP:
+		/* Dead batter and dbg acc ind */
+		ctx->reg[TCPC_REG_ROLE_CTRL] = 0x4a;
+		ctx->reg[TCPC_REG_MSG_HDR_INFO] = 0x04;
+		break;
+	}
+}
+
+/**
+ * @brief Reset registers to default values. Vendor and reserved registers
+ *        are not changed.
+ *
+ * @param emul Pointer to TCPCI emulator
+ * @return 0 if successful
+ */
+int tcpci_emul_reset(const struct emul *emul)
+{
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx;
+
+	ctx->reg[TCPC_REG_ALERT] = 0x00;
+	ctx->reg[TCPC_REG_ALERT + 1] = 0x00;
+	ctx->reg[TCPC_REG_FAULT_STATUS_MASK] = 0xff;
+	ctx->reg[TCPC_REG_CONFIG_STD_OUTPUT] = 0x60;
+	ctx->reg[TCPC_REG_TCPC_CTRL] = 0x00;
+	ctx->reg[TCPC_REG_FAULT_CTRL] = 0x00;
+	ctx->reg[TCPC_REG_POWER_CTRL] = 0x60;
+	ctx->reg[TCPC_REG_CC_STATUS] = 0x00;
+	ctx->reg[TCPC_REG_POWER_STATUS] = 0x08;
+	ctx->reg[TCPC_REG_FAULT_STATUS] = 0x80;
+	ctx->reg[TCPC_REG_EXT_STATUS] = 0x00;
+	ctx->reg[TCPC_REG_ALERT_EXT] = 0x00;
+	ctx->reg[TCPC_REG_COMMAND] = 0x00;
+	ctx->reg[TCPC_REG_CONFIG_EXT_1] = 0x00;
+	ctx->reg[TCPC_REG_GENERIC_TIMER] = 0x00;
+	ctx->reg[TCPC_REG_GENERIC_TIMER + 1] = 0x00;
+	ctx->reg[TCPC_REG_RX_DETECT] = 0x00;
+	ctx->reg[TCPC_REG_VBUS_VOLTAGE] = 0x00;
+	ctx->reg[TCPC_REG_VBUS_VOLTAGE + 1] = 0x00;
+	ctx->reg[TCPC_REG_VBUS_SINK_DISCONNECT_THRESH] = 0x8c;
+	ctx->reg[TCPC_REG_VBUS_SINK_DISCONNECT_THRESH + 1] = 0x00;
+	ctx->reg[TCPC_REG_VBUS_STOP_DISCHARGE_THRESH] = 0x20;
+	ctx->reg[TCPC_REG_VBUS_STOP_DISCHARGE_THRESH + 1] = 0x00;
+	ctx->reg[TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG] = 0x00;
+	ctx->reg[TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG + 1] = 0x00;
+	ctx->reg[TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG] = 0x00;
+	ctx->reg[TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG + 1] = 0x00;
+	ctx->reg[TCPC_REG_VBUS_NONDEFAULT_TARGET] = 0x00;
+	ctx->reg[TCPC_REG_VBUS_NONDEFAULT_TARGET + 1] = 0x00;
+
+	tcpci_emul_reset_mask_regs(ctx);
+	tcpci_emul_reset_role_ctrl(ctx);
+
+	return tcpci_emul_alert_changed(emul);
+}
+
+/**
+ * @brief Set alert and fault registers to indicate i2c interface fault
+ *
+ * @param emul Pointer to TCPC emulator
+ * @return 0 if successful
+ */
+static int tcpci_emul_set_i2c_interface_err(const struct emul *emul)
+{
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx;
+	uint16_t fault_status;
+
+	get_reg(ctx, TCPC_REG_FAULT_STATUS, &fault_status);
+	fault_status |= TCPC_REG_FAULT_STATUS_I2C_INTERFACE_ERR;
+	set_reg(ctx, TCPC_REG_FAULT_STATUS, fault_status);
+
+	return tcpci_emul_alert_changed(emul);
+}
+
+/**
+ * @brief Handle read from RX buffer registers for TCPCI rev 1.0 and rev 2.0
+ *
+ * @param emul Pointer to TCPC emulator
+ * @param reg First byte of last i2c write message
+ * @param val Pointer where byte to read should be stored
+ * @param bytes Number of bytes already readded
+ *
+ * @return 0 on success
+ * @return -EIO invalid read request
+ */
+static int tcpci_emul_handle_rx_buf(const struct emul *emul, int reg,
+				    uint8_t *val, int bytes)
+{
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx;
+	int is_rev1;
+
+	is_rev1 = ctx->reg[TCPC_REG_PD_INT_REV] == TCPC_REG_PD_INT_REV_REV_1_0;
+
+	if (!is_rev1 && reg != TCPC_REG_RX_BUFFER) {
+		LOG_ERR("Register 0x%x defined only for revision 1.0", reg);
+		tcpci_emul_set_i2c_interface_err(emul);
+		return -EIO;
+	}
+
+	switch (reg) {
+	case TCPC_REG_RX_BUFFER:
+		if (ctx->rx_msg == NULL) {
+			if (bytes < 2) {
+				*val = 0;
+			} else {
+				LOG_ERR("Accessing RX buffer with no msg");
+				tcpci_emul_set_i2c_interface_err(emul);
+				return -EIO;
+			}
+			return 0;
+		}
+		if (bytes == 0) {
+			/* TCPCI message size count include type byte */
+			*val = ctx->rx_msg->cnt + 1;
+		} else if (is_rev1) {
+			LOG_ERR("Revision 1.0 has only byte count at 0x30");
+			tcpci_emul_set_i2c_interface_err(emul);
+			return -EIO;
+		} else if (bytes == 1) {
+			*val = ctx->rx_msg->sop_type;
+		} else if (ctx->rx_msg->idx < ctx->rx_msg->cnt) {
+			*val = ctx->rx_msg->buf[ctx->rx_msg->idx];
+			ctx->rx_msg->idx++;
+		} else {
+			LOG_ERR("Reading past RX buffer");
+			tcpci_emul_set_i2c_interface_err(emul);
+			return -EIO;
+		}
+		break;
+
+	case TCPC_REG_RX_BUF_FRAME_TYPE:
+		if (bytes != 0) {
+			LOG_ERR("Reading byte %d from 1 byte register 0x%x",
+				bytes, reg);
+			tcpci_emul_set_i2c_interface_err(emul);
+			return -EIO;
+		}
+		if (ctx->rx_msg == NULL) {
+			*val = 0;
+		} else {
+			*val = ctx->rx_msg->sop_type;
+		}
+		break;
+
+	case TCPC_REG_RX_HDR:
+		if (bytes > 1) {
+			LOG_ERR("Reading byte %d from 2 byte register 0x%x",
+				bytes, reg);
+			tcpci_emul_set_i2c_interface_err(emul);
+			return -EIO;
+		}
+		if (ctx->rx_msg == NULL) {
+			LOG_ERR("Accessing RX buffer with no msg");
+			tcpci_emul_set_i2c_interface_err(emul);
+			return -EIO;
+		}
+		*val = ctx->rx_msg->buf[bytes];
+		break;
+
+	case TCPC_REG_RX_DATA:
+		if (ctx->rx_msg == NULL) {
+			LOG_ERR("Accessing RX buffer with no msg");
+			tcpci_emul_set_i2c_interface_err(emul);
+			return -EIO;
+		}
+		if (bytes < ctx->rx_msg->cnt - 2) {
+			/* rx_msg cnt include two bytes of header */
+			*val = ctx->rx_msg->buf[bytes + 2];
+			ctx->rx_msg->idx++;
+		} else {
+			LOG_ERR("Reading past RX buffer");
+			tcpci_emul_set_i2c_interface_err(emul);
+			return -EIO;
+		}
+		break;
+	}
+
+	return 0;
+}
+
+/** Check description in emul_tcpci.h */
+int tcpci_emul_read_byte(const struct emul *emul, int reg, uint8_t *val,
+			 int bytes)
+{
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx;
+
+	switch (reg) {
+	/* 16 bits values */
+	case TCPC_REG_VENDOR_ID:
+	case TCPC_REG_PRODUCT_ID:
+	case TCPC_REG_BCD_DEV:
+	case TCPC_REG_TC_REV:
+	case TCPC_REG_PD_REV:
+	case TCPC_REG_PD_INT_REV:
+	case TCPC_REG_ALERT:
+	case TCPC_REG_ALERT_MASK:
+	case TCPC_REG_DEV_CAP_1:
+	case TCPC_REG_DEV_CAP_2:
+	case TCPC_REG_VBUS_VOLTAGE:
+	case TCPC_REG_VBUS_SINK_DISCONNECT_THRESH:
+	case TCPC_REG_VBUS_STOP_DISCHARGE_THRESH:
+	case TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG:
+	case TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG:
+	case TCPC_REG_VBUS_NONDEFAULT_TARGET:
+		if (bytes > 1) {
+			LOG_ERR("Reading byte %d from 2 byte register 0x%x",
+				bytes, reg);
+			tcpci_emul_set_i2c_interface_err(emul);
+			return -EIO;
+		}
+		*val = ctx->reg[reg + bytes];
+		break;
+
+	/* 8 bits values */
+	case TCPC_REG_POWER_STATUS_MASK:
+	case TCPC_REG_FAULT_STATUS_MASK:
+	case TCPC_REG_EXT_STATUS_MASK:
+	case TCPC_REG_ALERT_EXTENDED_MASK:
+	case TCPC_REG_CONFIG_STD_OUTPUT:
+	case TCPC_REG_TCPC_CTRL:
+	case TCPC_REG_ROLE_CTRL:
+	case TCPC_REG_FAULT_CTRL:
+	case TCPC_REG_POWER_CTRL:
+	case TCPC_REG_CC_STATUS:
+	case TCPC_REG_POWER_STATUS:
+	case TCPC_REG_FAULT_STATUS:
+	case TCPC_REG_EXT_STATUS:
+	case TCPC_REG_ALERT_EXT:
+	case TCPC_REG_STD_INPUT_CAP:
+	case TCPC_REG_STD_OUTPUT_CAP:
+	case TCPC_REG_CONFIG_EXT_1:
+	case TCPC_REG_MSG_HDR_INFO:
+	case TCPC_REG_RX_DETECT:
+		if (bytes != 0) {
+			LOG_ERR("Reading byte %d from 1 byte register 0x%x",
+				bytes, reg);
+			tcpci_emul_set_i2c_interface_err(emul);
+			return -EIO;
+		}
+		*val = ctx->reg[reg];
+		break;
+
+	case TCPC_REG_RX_BUFFER:
+	case TCPC_REG_RX_BUF_FRAME_TYPE:
+	case TCPC_REG_RX_HDR:
+	case TCPC_REG_RX_DATA:
+		return tcpci_emul_handle_rx_buf(emul, reg, val, bytes);
+
+	default:
+		LOG_ERR("Reading from reg 0x%x which is WO or undefined", reg);
+		tcpci_emul_set_i2c_interface_err(emul);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+/** Check description in emul_tcpci.h */
+int tcpci_emul_write_byte(const struct emul *emul, int reg, uint8_t val,
+			  int bytes)
+{
+	int is_rev1;
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx;
+
+	is_rev1 = ctx->reg[TCPC_REG_PD_INT_REV] == TCPC_REG_PD_INT_REV_REV_1_0;
+	switch (reg) {
+	case TCPC_REG_TX_BUFFER:
+		if (is_rev1) {
+			if (bytes > 1) {
+				LOG_ERR("Rev 1.0 has only byte count at 0x51");
+				tcpci_emul_set_i2c_interface_err(emul);
+				return -EIO;
+			}
+			ctx->tx_msg->idx = val;
+		}
+
+		if (bytes == 1) {
+			ctx->tx_msg->cnt = val;
+		} else {
+			if (ctx->tx_msg->cnt > 0) {
+				ctx->tx_msg->cnt--;
+				ctx->tx_msg->buf[ctx->tx_msg->idx] = val;
+				ctx->tx_msg->idx++;
+			} else {
+				LOG_ERR("Writing past TX buffer");
+				tcpci_emul_set_i2c_interface_err(emul);
+				return -EIO;
+			}
+		}
+
+		return 0;
+
+	case TCPC_REG_TX_DATA:
+		if (!is_rev1) {
+			LOG_ERR("Register 0x%x defined only for revision 1.0",
+				reg);
+			tcpci_emul_set_i2c_interface_err(emul);
+			return -EIO;
+		}
+
+		/* Skip header and account reg byte */
+		bytes += 2 - 1;
+
+		if (bytes > 29) {
+			LOG_ERR("Writing past TX buffer");
+			tcpci_emul_set_i2c_interface_err(emul);
+			return -EIO;
+		}
+		ctx->tx_msg->buf[bytes] = val;
+		return 0;
+
+	case TCPC_REG_TX_HDR:
+		if (!is_rev1) {
+			LOG_ERR("Register 0x%x defined only for revision 1.0",
+				reg);
+			tcpci_emul_set_i2c_interface_err(emul);
+			return -EIO;
+		}
+
+		/* Account reg byte */
+		bytes -= 1;
+
+		if (bytes > 1) {
+			LOG_ERR("Writing byte %d to 2 byte register 0x%x",
+				bytes, reg);
+			tcpci_emul_set_i2c_interface_err(emul);
+			return -EIO;
+		}
+		ctx->tx_msg->buf[bytes] = val;
+		return 0;
+	}
+
+	if (bytes == 1) {
+		ctx->write_data = val;
+	} else if (bytes == 2) {
+		ctx->write_data |= (uint16_t)val << 8;
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Handle writes to command register
+ *
+ * @param emul Pointer to TCPC emulator
+ *
+ * @return 0 on success
+ * @return -EIO on unknown command value
+ */
+static int tcpci_emul_handle_command(const struct emul *emul)
+{
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx;
+	uint16_t role_ctrl;
+	uint16_t pwr_ctrl;
+
+	switch (ctx->write_data & 0xff) {
+	case TCPC_REG_COMMAND_RESET_TRANSMIT_BUF:
+		ctx->tx_msg->idx = 0;
+		break;
+	case TCPC_REG_COMMAND_RESET_RECEIVE_BUF:
+		if (ctx->rx_msg) {
+			ctx->rx_msg->idx = 0;
+		}
+		break;
+	case TCPC_REG_COMMAND_LOOK4CONNECTION:
+		get_reg(ctx, TCPC_REG_ROLE_CTRL, &role_ctrl);
+		get_reg(ctx, TCPC_REG_POWER_CTRL, &pwr_ctrl);
+
+		/*
+		 * Start DRP toggling only if auto discharge is disabled,
+		 * DRP is enabled and CC1/2 are both Rp or Rd
+		 */
+		if (!(pwr_ctrl &
+		      TCPC_REG_POWER_CTRL_AUTO_DISCHARGE_DISCONNECT) &&
+		    TCPC_REG_ROLE_CTRL_DRP(role_ctrl) &&
+		    (TCPC_REG_ROLE_CTRL_CC1(role_ctrl) ==
+		     TCPC_REG_ROLE_CTRL_CC2(role_ctrl)) &&
+		    (TCPC_REG_ROLE_CTRL_CC1(role_ctrl) == TYPEC_CC_RP ||
+		     TCPC_REG_ROLE_CTRL_CC1(role_ctrl) == TYPEC_CC_RD)) {
+			/* Set Look4Connection and clear CC1/2 state */
+			set_reg(ctx, TCPC_REG_CC_STATUS,
+				TCPC_REG_CC_STATUS_LOOK4CONNECTION_MASK);
+		}
+		break;
+	case TCPC_REG_COMMAND_DISABLE_VBUS_DETECT:
+		update_reg(ctx, TCPC_REG_POWER_STATUS, 0,
+			   TCPC_REG_POWER_STATUS_VBUS_DET);
+		break;
+	case TCPC_REG_COMMAND_ENABLE_VBUS_DETECT:
+		update_reg(ctx, TCPC_REG_POWER_STATUS, 0xFF,
+			   TCPC_REG_POWER_STATUS_VBUS_DET);
+		break;
+	case TCPC_REG_COMMAND_SNK_CTRL_LOW:
+		update_reg(ctx, TCPC_REG_POWER_STATUS, 0,
+			   TCPC_REG_POWER_STATUS_SINKING_VBUS);
+		break;
+	case TCPC_REG_COMMAND_SNK_CTRL_HIGH:
+		update_reg(ctx, TCPC_REG_POWER_STATUS, 0xFF,
+			   TCPC_REG_POWER_STATUS_SINKING_VBUS);
+		break;
+	case TCPC_REG_COMMAND_SRC_CTRL_LOW:
+		update_reg(ctx, TCPC_REG_POWER_STATUS, 0,
+			   TCPC_REG_POWER_STATUS_SOURCING_VBUS);
+		break;
+	case TCPC_REG_COMMAND_SRC_CTRL_HIGH:
+		update_reg(ctx, TCPC_REG_POWER_STATUS, 0xFF,
+			   TCPC_REG_POWER_STATUS_SOURCING_VBUS);
+		break;
+	case TCPC_REG_COMMAND_I2CIDLE:
+		break;
+	default:
+		tcpci_emul_set_i2c_interface_err(emul);
+		return -EIO;
+	}
+
+	/*
+	 * Set command register to allow easier inspection of last
+	 * command sent
+	 */
+	set_reg(ctx, TCPC_REG_COMMAND, ctx->write_data & 0xff);
+	return 0;
+}
+
+/**
+ * @brief Handle write to transmit register
+ *
+ * @param emul Pointer to TCPC emulator
+ *
+ * @return 0 on success
+ * @return -EIO when sending SOP message with less than 2 bytes in TX buffer
+ */
+static int tcpci_emul_handle_transmit(const struct emul *emul)
+{
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx;
+	enum tcpci_msg_type type;
+
+	ctx->tx_msg->cnt = ctx->tx_msg->idx;
+	ctx->tx_msg->sop_type = TCPC_REG_TRANSMIT_TYPE(ctx->write_data);
+	ctx->tx_msg->idx = 0;
+
+	type = TCPC_REG_TRANSMIT_TYPE(ctx->write_data);
+
+	if (type < NUM_SOP_STAR_TYPES && ctx->tx_msg->cnt < 2) {
+		LOG_ERR("Transmitting too short message (%d)",
+			ctx->tx_msg->cnt);
+		tcpci_emul_set_i2c_interface_err(emul);
+		return -EIO;
+	}
+
+	if (ctx->partner && ctx->partner->transmit) {
+		ctx->partner->transmit(
+			emul, ctx->partner, ctx->tx_msg, type,
+			TCPC_REG_TRANSMIT_RETRY(ctx->write_data));
+	}
+
+	switch (type) {
+	case TCPCI_MSG_TX_HARD_RESET:
+		tcpci_emul_disable_pd_msg_delivery(emul);
+		tcpci_emul_reset_mask_regs(ctx);
+		__fallthrough;
+	case TCPCI_MSG_CABLE_RESET:
+		/*
+		 * Cable and Hard reset are special and set success and fail
+		 * in Alert reg regardless of the outcome of the transmission
+		 */
+		tcpci_emul_partner_msg_status(emul,
+					      TCPCI_EMUL_TX_CABLE_HARD_RESET);
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+/** Check description in emul_tcpci.h */
+int tcpci_emul_handle_write(const struct emul *emul, int reg, int msg_len)
+{
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx;
+	uint16_t rsvd_mask = 0;
+	uint16_t alert_val;
+	bool inform_partner = false;
+	bool alert_changed = false;
+	int reg_bytes;
+	int rc;
+
+	/* This write message was setting register before read */
+	if (msg_len == 1) {
+		return 0;
+	}
+
+	/* Exclude register address byte from message length */
+	msg_len--;
+
+	switch (reg) {
+	/* Alert registers */
+	case TCPC_REG_ALERT:
+		/* Overflow is cleared by Receive SOP message status */
+		ctx->write_data &= ~TCPC_REG_ALERT_RX_BUF_OVF;
+		if (ctx->write_data & TCPC_REG_ALERT_RX_STATUS) {
+			ctx->write_data |= TCPC_REG_ALERT_RX_BUF_OVF;
+			/* Do not clear RX status if there is new message */
+			if (tcpci_emul_get_next_rx_msg(emul)) {
+				ctx->write_data &= ~TCPC_REG_ALERT_RX_STATUS;
+			}
+		}
+		__fallthrough;
+	case TCPC_REG_FAULT_STATUS:
+	case TCPC_REG_ALERT_EXT:
+		/* Clear bits where TCPM set 1 */
+		get_reg(ctx, reg, &alert_val);
+		ctx->write_data = alert_val & (~ctx->write_data);
+		__fallthrough;
+	case TCPC_REG_ALERT_MASK:
+	case TCPC_REG_POWER_STATUS_MASK:
+	case TCPC_REG_FAULT_STATUS_MASK:
+	case TCPC_REG_EXT_STATUS_MASK:
+	case TCPC_REG_ALERT_EXTENDED_MASK:
+		alert_changed = true;
+		break;
+
+	/* Control registers */
+	case TCPC_REG_TCPC_CTRL:
+	case TCPC_REG_ROLE_CTRL:
+	case TCPC_REG_FAULT_CTRL:
+	case TCPC_REG_POWER_CTRL:
+		inform_partner = true;
+		break;
+
+	/* Simple write registers */
+	case TCPC_REG_VBUS_SINK_DISCONNECT_THRESH:
+	case TCPC_REG_VBUS_STOP_DISCHARGE_THRESH:
+	case TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG:
+	case TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG:
+	case TCPC_REG_VBUS_NONDEFAULT_TARGET:
+	case TCPC_REG_CONFIG_STD_OUTPUT:
+	case TCPC_REG_MSG_HDR_INFO:
+	case TCPC_REG_RX_DETECT:
+		break;
+
+	case TCPC_REG_CONFIG_EXT_1:
+		if (ctx->write_data & TCPC_REG_CONFIG_EXT_1_FR_SWAP_SNK_DIR &&
+		    ((ctx->reg[TCPC_REG_STD_INPUT_CAP] &
+		      TCPC_REG_STD_INPUT_CAP_SRC_FR_SWAP) == BIT(4)) &&
+		    ctx->reg[TCPC_REG_STD_OUTPUT_CAP] &
+			    TCPC_REG_STD_OUTPUT_CAP_SNK_DISC_DET) {
+			tcpci_emul_set_i2c_interface_err(emul);
+			return 0;
+		}
+		break;
+
+	case TCPC_REG_COMMAND:
+		if (msg_len != 1) {
+			tcpci_emul_set_i2c_interface_err(emul);
+			LOG_ERR("Writing byte %d to 1 byte register 0x%x",
+				msg_len, reg);
+			return -EIO;
+		}
+		return tcpci_emul_handle_command(emul);
+
+	case TCPC_REG_TRANSMIT:
+		if (msg_len != 1) {
+			tcpci_emul_set_i2c_interface_err(emul);
+			LOG_ERR("Writing byte %d to 1 byte register 0x%x",
+				msg_len, reg);
+			return -EIO;
+		}
+		return tcpci_emul_handle_transmit(emul);
+
+	case TCPC_REG_GENERIC_TIMER:
+		/* TODO: Add timer */
+		return 0;
+
+	/* Already handled in tcpci_emul_write_byte() */
+	case TCPC_REG_TX_BUFFER:
+	case TCPC_REG_TX_DATA:
+	case TCPC_REG_TX_HDR:
+		return 0;
+	default:
+		tcpci_emul_set_i2c_interface_err(emul);
+		LOG_ERR("Write to reg 0x%x which is RO, undefined or unaligned",
+			reg);
+		return -EIO;
+	}
+
+	reg_bytes = tcpci_emul_reg_bytes(reg);
+
+	/* Compute reserved bits mask */
+	switch (reg_bytes) {
+	case 2:
+		rsvd_mask = tcpci_emul_rsvd_mask[reg + 1];
+		__fallthrough;
+	case 1:
+		rsvd_mask <<= 8;
+		rsvd_mask |= tcpci_emul_rsvd_mask[reg];
+		break;
+	}
+
+	/* Check reserved bits */
+	if (ctx->error_on_rsvd_write && rsvd_mask & ctx->write_data) {
+		tcpci_emul_set_i2c_interface_err(emul);
+		LOG_ERR("Writing 0x%x to reg 0x%x with rsvd bits mask 0x%x",
+			ctx->write_data, reg, rsvd_mask);
+		return -EIO;
+	}
+
+	/* Check if I2C write message has correct length */
+	if (msg_len != reg_bytes) {
+		tcpci_emul_set_i2c_interface_err(emul);
+		LOG_ERR("Writing byte %d to %d byte register 0x%x", msg_len,
+			reg_bytes, reg);
+		return -EIO;
+	}
+
+	/* Set new value of register */
+	set_reg(ctx, reg, ctx->write_data);
+
+	if (alert_changed) {
+		rc = tcpci_emul_alert_changed(emul);
+		if (rc != 0)
+			return rc;
+	}
+
+	if (inform_partner && ctx->partner && ctx->partner->control_change) {
+		ctx->partner->control_change(emul, ctx->partner);
+	}
+
+	return 0;
+}
+
+/** Check description in emul_tcpci.h */
+void tcpci_emul_i2c_init(const struct emul *emul, const struct device *i2c_dev)
+{
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx;
+
+	ctx->common.emul.addr = tcpc_data->i2c_cfg.addr;
+	ctx->common.i2c = i2c_dev;
+	ctx->common.cfg = &tcpc_data->i2c_cfg;
+
+	i2c_common_emul_init(&ctx->common);
+}
+
+/** Check description in emul_tcpci.h */
+int tcpci_emul_set_vbus_level(const struct emul *emul, enum vbus_level level)
+{
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx;
+	uint16_t revision;
+	int rc;
+	uint16_t power_status;
+	uint16_t ext_status;
+
+	switch (level) {
+	case VBUS_SAFE0V:
+		power_status = TCPC_REG_POWER_STATUS_VBUS_DET;
+		ext_status = TCPC_REG_EXT_STATUS_SAFE0V;
+		break;
+	case VBUS_PRESENT:
+		power_status = TCPC_REG_POWER_STATUS_VBUS_DET |
+			       TCPC_REG_POWER_STATUS_VBUS_PRES;
+		ext_status = 0;
+		break;
+	case VBUS_REMOVED:
+		power_status = TCPC_REG_POWER_STATUS_VBUS_DET;
+		ext_status = 0;
+		break;
+	default:
+		return EC_ERROR_PARAM1;
+	}
+
+	rc = get_reg(ctx, TCPC_REG_PD_INT_REV, &revision);
+	if (rc)
+		return rc;
+	rc = update_reg(ctx, TCPC_REG_POWER_STATUS, power_status,
+			TCPC_REG_POWER_STATUS_VBUS_DET |
+				TCPC_REG_POWER_STATUS_VBUS_PRES);
+	if (rc)
+		return rc;
+	if (TCPC_REG_PD_INT_REV_REV(revision) == TCPC_REG_PD_INT_REV_REV_2_0) {
+		rc = update_reg(ctx, TCPC_REG_EXT_STATUS, ext_status,
+				TCPC_REG_EXT_STATUS_SAFE0V);
+		if (rc)
+			return rc;
+	}
+	rc = tcpci_emul_alert_changed(emul);
+	if (rc)
+		return rc;
+	return EC_SUCCESS;
+}
diff --git a/zephyr/emul/tcpc/emul_tcpci_generic.c b/zephyr/emul/tcpc/emul_tcpci_generic.c
new file mode 100644
index 0000000000..9f7a81f5d5
--- /dev/null
+++ b/zephyr/emul/tcpc/emul_tcpci_generic.c
@@ -0,0 +1,186 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_stub_device.h"
+#include "emul/tcpc/emul_tcpci.h"
+#include "tcpm/tcpci.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/i2c_emul.h>
+#include <zephyr/logging/log.h>
+#ifdef CONFIG_ZTEST
+#include <zephyr/ztest.h>
+#endif
+
+#define DT_DRV_COMPAT cros_tcpci_generic_emul
+
+LOG_MODULE_REGISTER(tcpci_generic_emul, CONFIG_TCPCI_EMUL_LOG_LEVEL);
+
+/**
+ * @brief Function called for each byte of read message from TCPCI emulator
+ *
+ * @param emul Pointer to I2C TCPCI emulator
+ * @param reg First byte of last write message
+ * @param val Pointer where byte to read should be stored
+ * @param bytes Number of bytes already read
+ *
+ * @return 0 on success
+ * @return -EIO on invalid read request
+ */
+static int tcpci_generic_emul_read_byte(const struct emul *emul, int reg,
+					uint8_t *val, int bytes)
+{
+	LOG_DBG("TCPCI Generic 0x%x: read reg 0x%x", emul->bus.i2c->addr, reg);
+
+	return tcpci_emul_read_byte(emul, reg, val, bytes);
+}
+
+/**
+ * @brief Function called for each byte of write message to TCPCI emulator
+ *
+ * @param emul Pointer to I2C TCPCI emulator
+ * @param reg First byte of write message
+ * @param val Received byte of write message
+ * @param bytes Number of bytes already received
+ *
+ * @return 0 on success
+ * @return -EIO on invalid write request
+ */
+static int tcpci_generic_emul_write_byte(const struct emul *emul, int reg,
+					 uint8_t val, int bytes)
+{
+	LOG_DBG("TCPCI Generic 0x%x: write reg 0x%x", emul->bus.i2c->addr, reg);
+
+	return tcpci_emul_write_byte(emul, reg, val, bytes);
+}
+
+/**
+ * @brief Function called on the end of write message to TCPCI emulator
+ *
+ * @param emul Pointer to I2C TCPCI emulator
+ * @param reg Register which is written
+ * @param msg_len Length of handled I2C message
+ *
+ * @return 0 on success
+ * @return -EIO on error
+ */
+static int tcpci_generic_emul_finish_write(const struct emul *emul, int reg,
+					   int msg_len)
+{
+	LOG_DBG("TCPCI Generic 0x%x: finish write reg 0x%x",
+		emul->bus.i2c->addr, reg);
+
+	return tcpci_emul_handle_write(emul, reg, msg_len);
+}
+
+/**
+ * @brief Get currently accessed register, which always equals to selected
+ *        register from TCPCI emulator.
+ *
+ * @param emul Pointer to I2C TCPCI emulator
+ * @param reg First byte of last write message
+ * @param bytes Number of bytes already handled from current message
+ * @param read If currently handled is read message
+ *
+ * @return Currently accessed register
+ */
+static int tcpci_generic_emul_access_reg(const struct emul *emul, int reg,
+					 int bytes, bool read)
+{
+	return reg;
+}
+
+/**
+ * @brief Function called on reset
+ *
+ * @param emul Pointer to TCPC emulator
+ */
+static void tcpci_generic_emul_reset(const struct emul *emul)
+{
+	tcpci_emul_reset(emul);
+}
+
+/**
+ * @brief Set up a new TCPCI generic emulator
+ *
+ * This should be called for each TCPCI Generic device that needs to be
+ * emulated.
+ *
+ * @param emul Emulation information
+ * @param parent Device to emulate
+ *
+ * @return 0 indicating success (always)
+ */
+static int tcpci_generic_emul_init(const struct emul *emul,
+				   const struct device *parent)
+{
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *tcpci_ctx = tcpc_data->tcpci_ctx;
+	const struct device *i2c_dev;
+
+	i2c_dev = parent;
+
+	tcpci_ctx->common.write_byte = tcpci_generic_emul_write_byte;
+	tcpci_ctx->common.finish_write = tcpci_generic_emul_finish_write;
+	tcpci_ctx->common.read_byte = tcpci_generic_emul_read_byte;
+	tcpci_ctx->common.access_reg = tcpci_generic_emul_access_reg;
+
+	tcpci_emul_i2c_init(emul, i2c_dev);
+
+	tcpci_generic_emul_reset(emul);
+
+	return 0;
+}
+
+static int i2c_tcpci_generic_emul_transfer(const struct emul *target,
+					   struct i2c_msg *msgs, int num_msgs,
+					   int addr)
+{
+	struct tcpc_emul_data *tcpc_data = target->data;
+	struct tcpci_ctx *tcpci_ctx = tcpc_data->tcpci_ctx;
+
+	return i2c_common_emul_transfer_workhorse(target, &tcpci_ctx->common,
+						  &tcpc_data->i2c_cfg, msgs,
+						  num_msgs, addr);
+}
+
+struct i2c_emul_api i2c_tcpci_generic_emul_api = {
+	.transfer = i2c_tcpci_generic_emul_transfer,
+};
+
+#define TCPCI_GENERIC_EMUL(n)                                     \
+	TCPCI_EMUL_DEFINE(n, tcpci_generic_emul_init, NULL, NULL, \
+			  &i2c_tcpci_generic_emul_api, NULL)
+
+DT_INST_FOREACH_STATUS_OKAY(TCPCI_GENERIC_EMUL)
+
+#ifdef CONFIG_ZTEST_NEW_API
+#define TCPCI_GENERIC_EMUL_RESET_RULE_BEFORE(n) \
+	tcpci_generic_emul_reset(EMUL_DT_GET(DT_DRV_INST(n)));
+static void
+tcpci_generic_emul_reset_rule_before(const struct ztest_unit_test *test,
+				     void *data)
+{
+	ARG_UNUSED(test);
+	ARG_UNUSED(data);
+	DT_INST_FOREACH_STATUS_OKAY(TCPCI_GENERIC_EMUL_RESET_RULE_BEFORE);
+}
+ZTEST_RULE(tcpci_generic_emul_reset, tcpci_generic_emul_reset_rule_before,
+	   NULL);
+#endif /* CONFIG_ZTEST_NEW_API */
+
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
+
+struct i2c_common_emul_data *
+emul_tcpci_generic_get_i2c_common_data(const struct emul *emul)
+{
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *tcpci_ctx = tcpc_data->tcpci_ctx;
+
+	return &tcpci_ctx->common;
+}
diff --git a/zephyr/emul/tcpc/emul_tcpci_partner_common.c b/zephyr/emul/tcpc/emul_tcpci_partner_common.c
new file mode 100644
index 0000000000..e802917255
--- /dev/null
+++ b/zephyr/emul/tcpc/emul_tcpci_partner_common.c
@@ -0,0 +1,1682 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "driver/tcpm/tcpci.h"
+#include "ec_commands.h"
+#include "emul/tcpc/emul_tcpci.h"
+#include "emul/tcpc/emul_tcpci_partner_common.h"
+#include "usb_pd.h"
+#include "util.h"
+
+#include <stdlib.h>
+
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/ztest.h>
+
+LOG_MODULE_REGISTER(tcpci_partner, CONFIG_TCPCI_EMUL_LOG_LEVEL);
+
+/** Length of PDO, RDO and BIST request object in SOP message in bytes */
+#define TCPCI_MSG_DO_LEN 4
+/** Length of header in SOP message in bytes  */
+#define TCPCI_MSG_HEADER_LEN 2
+/** Length of extended header in bytes  */
+#define TCPCI_MSG_EXT_HEADER_LEN 2
+
+void tcpci_partner_common_hard_reset_as_role(struct tcpci_partner_data *data,
+					     enum pd_power_role power_role)
+{
+	data->power_role = power_role;
+	data->data_role = power_role == PD_ROLE_SOURCE ? PD_ROLE_DFP :
+							 PD_ROLE_UFP;
+	data->vconn_role = power_role == PD_ROLE_SOURCE ? PD_ROLE_VCONN_SRC :
+							  PD_ROLE_VCONN_OFF;
+	data->displayport_configured = false;
+	data->entered_svid = 0;
+	atomic_clear(&data->mode_enter_attempts);
+}
+
+/**
+ * @brief Allocate space for a PD message. Do not call directly; use
+ *        tcpci_partner_alloc_standard_msg() or
+ * tcpci_partner_alloc_extended_msg() depending on the type of message.
+ *
+ * @param size Size of the message in bytes, including header(s)
+ *
+ * @return Pointer to new message on success
+ * @return NULL on error
+ */
+static struct tcpci_partner_msg *tcpci_partner_alloc_msg_helper(size_t size)
+{
+	struct tcpci_partner_msg *new_msg;
+
+	new_msg = calloc(1, sizeof(struct tcpci_partner_msg));
+	if (new_msg == NULL) {
+		return NULL;
+	}
+
+	new_msg->msg.buf = calloc(1, size);
+	if (new_msg->msg.buf == NULL) {
+		free(new_msg);
+		return NULL;
+	}
+
+	/* Set default message type to SOP */
+	new_msg->msg.sop_type = TCPCI_MSG_SOP;
+	new_msg->msg.cnt = size;
+
+	return new_msg;
+}
+
+/**
+ * @brief Allocate space for a standard (non-extended) message, containing the
+ * specified number of data objects.
+ *
+ * @param num_data_objects Number of 32-bit DOs this message contains, if data
+ * message. Pass 0 if control message.
+ * @return struct tcpci_partner_msg* if successful
+ * @return NULL in case of error
+ */
+static struct tcpci_partner_msg *
+tcpci_partner_alloc_standard_msg(int num_data_objects)
+{
+	struct tcpci_partner_msg *msg = tcpci_partner_alloc_msg_helper(
+		TCPCI_MSG_HEADER_LEN + TCPCI_MSG_DO_LEN * num_data_objects);
+
+	if (msg) {
+		msg->data_objects = num_data_objects;
+	}
+
+	return msg;
+}
+
+/**
+ * @brief Allocate space for an extended message, containing a payload of
+ * specified size
+ *
+ * @param payload_size Size of extended message payload. Do not count either
+ * message header.
+ * @return struct tcpci_partner_msg* if successful
+ * @return NULL in case of error
+ */
+static struct tcpci_partner_msg *
+tcpci_partner_alloc_extended_msg(size_t payload_size)
+{
+	/* Currently, the emulators only support extended messages that can fit
+	 * into a single chunk. Enforce that here.
+	 */
+
+	__ASSERT(payload_size <= PD_MAX_EXTENDED_MSG_CHUNK_LEN,
+		 "Message must fit into a single chunk");
+
+	struct tcpci_partner_msg *msg = tcpci_partner_alloc_msg_helper(
+		TCPCI_MSG_HEADER_LEN + TCPCI_MSG_EXT_HEADER_LEN + payload_size);
+
+	if (msg) {
+		msg->extended = true;
+
+		/* Update the number of data objects with the number of 4-byte
+		 * words in the payload, rounding up. This includes the 2-byte
+		 * Extended Message Header (USB-PD spec Rev 3.0, V1.1,
+		 * section 6.2.1.2.1)
+		 */
+
+		msg->data_objects = DIV_ROUND_UP(
+			payload_size + TCPCI_MSG_EXT_HEADER_LEN, 4);
+	}
+
+	return msg;
+}
+
+/**
+ * @brief Alloc and append message to log if collect_msg_log flag is set
+ *
+ * @param data Pointer to TCPCI partner emulator
+ * @param msg The PD message to log
+ * @param sender Who send the message
+ * @param status If message was received/send correctly
+ *
+ * @return Pointer to message status
+ */
+static enum tcpci_emul_tx_status *tcpci_partner_log_msg(
+	struct tcpci_partner_data *data, const struct tcpci_emul_msg *msg,
+	enum tcpci_partner_msg_sender sender, enum tcpci_emul_tx_status status)
+{
+	struct tcpci_partner_log_msg *log_msg;
+	int cnt;
+	int ret;
+
+	if (!data->collect_msg_log) {
+		return NULL;
+	}
+
+	log_msg = malloc(sizeof(struct tcpci_partner_log_msg));
+	if (log_msg == NULL) {
+		return NULL;
+	}
+
+	/* We log length of actual buffer without SOP byte */
+	cnt = msg->cnt;
+	log_msg->buf = malloc(cnt);
+	if (log_msg->buf == NULL) {
+		free(log_msg);
+		return NULL;
+	}
+
+	log_msg->cnt = cnt;
+	log_msg->sop = msg->sop_type;
+	log_msg->time = k_uptime_get();
+	log_msg->sender = sender;
+	log_msg->status = status;
+
+	memcpy(log_msg->buf, msg->buf, cnt);
+
+	ret = k_mutex_lock(&data->msg_log_mutex, K_FOREVER);
+	if (ret) {
+		free(log_msg->buf);
+		free(log_msg);
+		return NULL;
+	}
+
+	sys_slist_append(&data->msg_log, &log_msg->node);
+
+	k_mutex_unlock(&data->msg_log_mutex);
+
+	return &log_msg->status;
+}
+
+void tcpci_partner_free_msg(struct tcpci_partner_msg *msg)
+{
+	free(msg->msg.buf);
+	free(msg);
+}
+
+void tcpci_partner_set_header(struct tcpci_partner_data *data,
+			      struct tcpci_partner_msg *msg)
+{
+	uint16_t msg_id;
+	uint16_t header;
+
+	/* Header msg id has only 3 bits and wraps around after 8 messages */
+	if (msg->msg.sop_type == TCPCI_MSG_SOP) {
+		msg_id = data->sop_msg_id & 0x7;
+		header = PD_HEADER(msg->type, data->power_role, data->data_role,
+				   msg_id, msg->data_objects, data->rev,
+				   msg->extended);
+		data->sop_msg_id++;
+	} else if (msg->msg.sop_type == TCPCI_MSG_SOP_PRIME) {
+		msg_id = data->sop_prime_msg_id & 0x7;
+		header = PD_HEADER(msg->type, PD_PLUG_FROM_CABLE, 0, msg_id,
+				   msg->data_objects, data->rev, msg->extended);
+		data->sop_prime_msg_id++;
+	} else {
+		return;
+	}
+
+	msg->msg.buf[1] = (header >> 8) & 0xff;
+	msg->msg.buf[0] = header & 0xff;
+}
+
+/**
+ * @brief Convert return code from tcpci_emul_add_rx_msg to one of the enum
+ *        tcpci_emul_tx_status value
+ *
+ * @param ret Return code of the tcpci_emul_add_rx_msg function
+ *
+ * @return One ot the enum tcpci_emul_tx_status value
+ */
+static enum tcpci_emul_tx_status tcpci_partner_add_rx_msg_to_status(int ret)
+{
+	switch (ret) {
+	case TCPCI_EMUL_TX_SUCCESS:
+	case TCPCI_EMUL_TX_FAILED:
+		return ret;
+	}
+
+	/* Convert all other error codes to unknown value */
+	return TCPCI_EMUL_TX_UNKNOWN;
+}
+
+/**
+ * @brief Work function which sends delayed messages
+ *
+ * @param work Pointer to work structure
+ */
+static void tcpci_partner_delayed_send(void *fifo_data)
+{
+	struct tcpci_partner_data *data =
+		CONTAINER_OF(fifo_data, struct tcpci_partner_data, fifo_data);
+	enum tcpci_emul_tx_status status;
+	struct tcpci_partner_msg *msg;
+	uint64_t now;
+	int ret;
+
+	do {
+		ret = k_mutex_lock(&data->to_send_mutex, K_FOREVER);
+	} while (ret);
+
+	while (!sys_slist_is_empty(&data->to_send)) {
+		msg = SYS_SLIST_PEEK_HEAD_CONTAINER(&data->to_send, msg, node);
+
+		now = k_uptime_get();
+		if (now >= msg->time) {
+			sys_slist_get_not_empty(&data->to_send);
+			k_mutex_unlock(&data->to_send_mutex);
+
+			tcpci_partner_set_header(data, msg);
+			__ASSERT(data->tcpci_emul,
+				 "Disconnected partner send message");
+			ret = tcpci_emul_add_rx_msg(data->tcpci_emul, &msg->msg,
+						    true /* send alert */);
+			status = tcpci_partner_add_rx_msg_to_status(ret);
+			tcpci_partner_log_msg(data, &msg->msg,
+					      TCPCI_PARTNER_SENDER_PARTNER,
+					      status);
+			if (ret != TCPCI_EMUL_TX_SUCCESS) {
+				tcpci_partner_free_msg(msg);
+			}
+
+			do {
+				ret = k_mutex_lock(&data->to_send_mutex,
+						   K_FOREVER);
+			} while (ret);
+		} else {
+			k_timer_start(&data->delayed_send,
+				      K_MSEC(msg->time - now), K_NO_WAIT);
+			break;
+		}
+	}
+
+	k_mutex_unlock(&data->to_send_mutex);
+}
+
+/** FIFO to schedule TCPCI partners that needs to send message */
+K_FIFO_DEFINE(delayed_send_fifo);
+
+/**
+ * @brief Thread which sends delayed messages for TCPCI partners
+ *
+ * @param a unused
+ * @param b unused
+ * @param c unused
+ */
+static void tcpci_partner_delayed_send_thread(void *a, void *b, void *c)
+{
+	void *fifo_data;
+
+	while (1) {
+		fifo_data = k_fifo_get(&delayed_send_fifo, K_FOREVER);
+		tcpci_partner_delayed_send(fifo_data);
+	}
+}
+
+/** Thread for sending delayed messages */
+K_THREAD_DEFINE(tcpci_partner_delayed_send_tid, 512 /* stack size */,
+		tcpci_partner_delayed_send_thread, NULL, NULL, NULL,
+		0 /* priority */, 0, 0);
+
+/**
+ * @brief Timeout handler which adds TCPCI partner that has pending delayed
+ *        message to send
+ *
+ * @param timer Pointer to timer which triggered timeout
+ */
+static void tcpci_partner_delayed_send_timer(struct k_timer *timer)
+{
+	struct tcpci_partner_data *data =
+		CONTAINER_OF(timer, struct tcpci_partner_data, delayed_send);
+
+	k_fifo_put(&delayed_send_fifo, &data->fifo_data);
+}
+
+int tcpci_partner_send_msg(struct tcpci_partner_data *data,
+			   struct tcpci_partner_msg *msg, uint64_t delay)
+{
+	struct tcpci_partner_msg *next_msg;
+	struct tcpci_partner_msg *prev_msg;
+	uint64_t now;
+	int ret;
+
+	if (delay == 0) {
+		__ASSERT(data->tcpci_emul, "Disconnected partner send message");
+		tcpci_partner_set_header(data, msg);
+		ret = tcpci_emul_add_rx_msg(data->tcpci_emul, &msg->msg, true);
+		tcpci_partner_log_msg(data, &msg->msg,
+				      TCPCI_PARTNER_SENDER_PARTNER,
+				      tcpci_partner_add_rx_msg_to_status(ret));
+		if (ret != TCPCI_EMUL_TX_SUCCESS) {
+			tcpci_partner_free_msg(msg);
+		}
+
+		return ret;
+	}
+
+	now = k_uptime_get();
+	msg->time = now + delay;
+
+	ret = k_mutex_lock(&data->to_send_mutex, K_FOREVER);
+	if (ret) {
+		tcpci_partner_free_msg(msg);
+
+		return ret;
+	}
+
+	prev_msg =
+		SYS_SLIST_PEEK_HEAD_CONTAINER(&data->to_send, prev_msg, node);
+	/* Current message should be sent first */
+	if (prev_msg == NULL || prev_msg->time > msg->time) {
+		sys_slist_prepend(&data->to_send, &msg->node);
+		k_timer_start(&data->delayed_send, K_MSEC(delay), K_NO_WAIT);
+		k_mutex_unlock(&data->to_send_mutex);
+		return 0;
+	}
+
+	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&data->to_send, prev_msg, next_msg,
+					  node)
+	{
+		/*
+		 * If we reach tail or next message should be sent after new
+		 * message, insert new message to the list.
+		 */
+		if (next_msg == NULL || next_msg->time > msg->time) {
+			sys_slist_insert(&data->to_send, &prev_msg->node,
+					 &msg->node);
+			k_mutex_unlock(&data->to_send_mutex);
+			return 0;
+		}
+	}
+
+	__ASSERT(0, "Message should be always inserted to the list");
+
+	return -1;
+}
+
+int tcpci_partner_send_control_msg(struct tcpci_partner_data *data,
+				   enum pd_ctrl_msg_type type, uint64_t delay)
+{
+	struct tcpci_partner_msg *msg;
+
+	msg = tcpci_partner_alloc_standard_msg(0);
+	if (msg == NULL) {
+		return -ENOMEM;
+	}
+
+	msg->type = type;
+
+	switch (msg->type) {
+	case PD_CTRL_DR_SWAP:
+	case PD_CTRL_VCONN_SWAP:
+		/* For supported message types, remember the control request
+		 * initiated, so the partner can handle the responses.
+		 * (Eventually, all messages that can start an AMS should be
+		 * supported.)
+		 */
+		tcpci_partner_common_set_ams_ctrl_msg(data, msg->type);
+		break;
+	default:
+		/* For messages that do not start an AMS, there is nothing to
+		 * record.
+		 */
+		break;
+	}
+
+	return tcpci_partner_send_msg(data, msg, delay);
+}
+
+int tcpci_partner_send_data_msg(struct tcpci_partner_data *data,
+				enum pd_data_msg_type type, uint32_t *data_obj,
+				int data_obj_num, uint64_t delay)
+{
+	struct tcpci_partner_msg *msg;
+	int addr;
+
+	msg = tcpci_partner_alloc_standard_msg(data_obj_num);
+	if (msg == NULL) {
+		return -ENOMEM;
+	}
+
+	for (int i = 0; i < data_obj_num; i++) {
+		/* Address of given data object in message buffer */
+		addr = TCPCI_MSG_HEADER_LEN + i * TCPCI_MSG_DO_LEN;
+		sys_put_le32(data_obj[i], msg->msg.buf + addr);
+	}
+
+	msg->type = type;
+
+	return tcpci_partner_send_msg(data, msg, delay);
+}
+
+/* Note: Cables can send from both SOP' and SOP'', so accept a type argument */
+int tcpci_cable_send_data_msg(struct tcpci_partner_data *data,
+			      enum pd_data_msg_type type, uint32_t *data_obj,
+			      int data_obj_num, enum tcpci_msg_type sop_type,
+			      uint64_t delay)
+{
+	struct tcpci_partner_msg *msg;
+	int addr;
+
+	/* TODO(b/243151272): Add SOP'' support */
+	if (sop_type != TCPCI_MSG_SOP_PRIME)
+		return -EINVAL;
+
+	msg = tcpci_partner_alloc_standard_msg(data_obj_num);
+	if (msg == NULL) {
+		return -ENOMEM;
+	}
+
+	for (int i = 0; i < data_obj_num; i++) {
+		/* Address of given data object in message buffer */
+		addr = TCPCI_MSG_HEADER_LEN + i * TCPCI_MSG_DO_LEN;
+		sys_put_le32(data_obj[i], msg->msg.buf + addr);
+	}
+
+	msg->msg.sop_type = sop_type;
+	msg->type = type;
+
+	return tcpci_partner_send_msg(data, msg, delay);
+}
+
+int tcpci_partner_clear_msg_queue(struct tcpci_partner_data *data)
+{
+	struct tcpci_partner_msg *msg;
+	int ret;
+
+	k_timer_stop(&data->delayed_send);
+
+	ret = k_mutex_lock(&data->to_send_mutex, K_FOREVER);
+	if (ret) {
+		return ret;
+	}
+
+	while (!sys_slist_is_empty(&data->to_send)) {
+		msg = CONTAINER_OF(sys_slist_get_not_empty(&data->to_send),
+				   struct tcpci_partner_msg, node);
+		tcpci_partner_free_msg(msg);
+	}
+
+	k_mutex_unlock(&data->to_send_mutex);
+
+	return 0;
+}
+
+/**
+ * @brief Reset common data to state after hard reset (reset counters, flags,
+ *        clear message queue)
+ *
+ * @param data Pointer to TCPCI partner emulator
+ */
+static void tcpci_partner_common_reset(struct tcpci_partner_data *data)
+{
+	tcpci_partner_clear_msg_queue(data);
+	data->sop_msg_id = 0;
+	data->sop_prime_msg_id = 0;
+	data->sop_recv_msg_id = -1;
+	data->sop_prime_recv_msg_id = -1;
+	data->in_soft_reset = false;
+	tcpci_partner_stop_sender_response_timer(data);
+	tcpci_partner_common_clear_ams_ctrl_msg(data);
+}
+
+/**
+ * @brief Common action on HardReset message send and receive which is calling
+ *        hard_reset callback on all extensions and resetting common data
+ *
+ * @param data Pointer to TCPCI partner emulator
+ */
+static void tcpci_partner_common_hard_reset(struct tcpci_partner_data *data)
+{
+	struct tcpci_partner_extension *ext;
+
+	tcpci_partner_common_reset(data);
+	for (ext = data->extensions; ext != NULL; ext = ext->next) {
+		if (ext->ops->hard_reset) {
+			ext->ops->hard_reset(ext, data);
+		}
+	}
+}
+
+void tcpci_partner_common_send_hard_reset(struct tcpci_partner_data *data)
+{
+	struct tcpci_partner_msg *msg;
+
+	tcpci_partner_common_hard_reset(data);
+
+	msg = tcpci_partner_alloc_standard_msg(0);
+	msg->msg.sop_type = TCPCI_MSG_TX_HARD_RESET;
+
+	tcpci_partner_send_msg(data, msg, 0);
+}
+
+void tcpci_partner_common_send_soft_reset(struct tcpci_partner_data *data)
+{
+	/* Reset counters */
+	data->sop_msg_id = 0;
+	data->sop_prime_msg_id = 0;
+	data->sop_recv_msg_id = -1;
+	data->sop_prime_recv_msg_id = -1;
+
+	tcpci_partner_common_clear_ams_ctrl_msg(data);
+
+	/* Send message */
+	tcpci_partner_send_control_msg(data, PD_CTRL_SOFT_RESET, 0);
+	/* Wait for accept of soft reset */
+	data->in_soft_reset = true;
+	tcpci_partner_start_sender_response_timer(data);
+}
+
+int tcpci_partner_send_extended_msg(struct tcpci_partner_data *data,
+				    enum pd_ext_msg_type type, uint64_t delay,
+				    uint8_t *payload, size_t payload_size)
+{
+	struct tcpci_partner_msg *msg;
+
+	msg = tcpci_partner_alloc_extended_msg(payload_size);
+	if (msg == NULL) {
+		return -ENOMEM;
+	}
+
+	msg->type = type;
+
+	/* Apply extended message header. We currently do not support
+	 * multiple chunks.
+	 */
+
+	sys_put_le16(PD_EXT_HEADER(0, 0, payload_size), &msg->msg.buf[2]);
+
+	/* Copy in payload */
+	memcpy(&msg->msg.buf[4], payload, payload_size);
+
+	return tcpci_partner_send_msg(data, msg, delay);
+}
+
+/** Check description in emul_common_tcpci_partner.h */
+void tcpci_partner_common_send_get_battery_capabilities(
+	struct tcpci_partner_data *data, int battery_index)
+{
+	__ASSERT(battery_index >= 0 && battery_index < PD_BATT_MAX,
+		 "Battery index out of range");
+	__ASSERT(data->battery_capabilities.index < 0,
+		 "Get Battery Capabilities request already in progress");
+
+	LOG_INF("Send battery cap request");
+
+	/* Get_Battery_Cap message payload */
+	uint8_t payload[1] = { [0] = battery_index };
+
+	/* Keep track which battery we requested capabilities for */
+	data->battery_capabilities.index = battery_index;
+	int ret = tcpci_partner_send_extended_msg(data, PD_EXT_GET_BATTERY_CAP,
+						  0, payload, sizeof(payload));
+	if (ret) {
+		LOG_ERR("Send battery capacity result: %d", ret);
+	}
+	tcpci_partner_start_sender_response_timer(data);
+}
+
+/**
+ * @brief Handler for response timeout
+ *
+ * @param timer Pointer to timer which triggered timeout
+ */
+static void tcpci_partner_sender_response_timeout(struct k_work *work)
+{
+	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
+	struct tcpci_partner_data *data = CONTAINER_OF(
+		dwork, struct tcpci_partner_data, sender_response_timeout);
+
+	if (k_mutex_lock(&data->transmit_mutex, K_NO_WAIT) != 0) {
+		/*
+		 * Emulator is probably handling received message,
+		 * try later if timer wasn't stopped.
+		 */
+		k_work_submit(work);
+		return;
+	}
+
+	/* Make sure that timer isn't stopped */
+	if (k_work_busy_get(work) & K_WORK_CANCELING) {
+		k_mutex_unlock(&data->transmit_mutex);
+		return;
+	}
+
+	data->tcpm_timeouts++;
+	tcpci_partner_common_send_hard_reset(data);
+	LOG_ERR("Timeout for TCPM response");
+
+	k_mutex_unlock(&data->transmit_mutex);
+}
+
+void tcpci_partner_start_sender_response_timer(struct tcpci_partner_data *data)
+{
+	k_work_schedule(&data->sender_response_timeout,
+			TCPCI_PARTNER_RESPONSE_TIMEOUT);
+	data->wait_for_response = true;
+}
+
+void tcpci_partner_stop_sender_response_timer(struct tcpci_partner_data *data)
+{
+	k_work_cancel_delayable(&data->sender_response_timeout);
+	data->wait_for_response = false;
+}
+
+static enum tcpci_partner_handler_res
+tcpci_partner_common_vdm_handler(struct tcpci_partner_data *data,
+				 const struct tcpci_emul_msg *message)
+{
+	uint32_t vdm_header = sys_get_le32(message->buf + TCPCI_MSG_HEADER_LEN);
+
+	/* TCPCI r2.0: Ignore unsupported VDMs. Don't handle command types other
+	 * than REQ or unstructured VDMs.
+	 * TODO(b/225397796): Validate VDM fields more thoroughly.
+	 */
+	if (PD_VDO_CMDT(vdm_header) != CMDT_INIT || !PD_VDO_SVDM(vdm_header)) {
+		return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+	}
+
+	switch (PD_VDO_CMD(vdm_header)) {
+	case CMD_DISCOVER_IDENT:
+		if (data->identity_vdos > 0) {
+			tcpci_partner_send_data_msg(data, PD_DATA_VENDOR_DEF,
+						    data->identity_vdm,
+						    data->identity_vdos, 0);
+		}
+		return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+	case CMD_DISCOVER_SVID:
+		if (data->svids_vdos > 0) {
+			tcpci_partner_send_data_msg(data, PD_DATA_VENDOR_DEF,
+						    data->svids_vdm,
+						    data->svids_vdos, 0);
+		}
+		return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+	case CMD_DISCOVER_MODES:
+		if (data->modes_vdos > 0) {
+			tcpci_partner_send_data_msg(data, PD_DATA_VENDOR_DEF,
+						    data->modes_vdm,
+						    data->modes_vdos, 0);
+		}
+		return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+	case CMD_ENTER_MODE:
+		/* Partner emulator only supports entering one mode */
+		if (data->enter_mode_vdos > 0 &&
+		    (PD_VDO_VID(vdm_header) ==
+		     PD_VDO_VID(data->enter_mode_vdm[0]))) {
+			/* Squirrel away the SVID if we're sending ACK */
+			if (PD_VDO_CMDT(data->enter_mode_vdm[0]) ==
+			    CMDT_RSP_ACK)
+				data->entered_svid = PD_VDO_VID(vdm_header);
+
+			tcpci_partner_send_data_msg(data, PD_DATA_VENDOR_DEF,
+						    data->enter_mode_vdm,
+						    data->enter_mode_vdos, 0);
+		}
+		atomic_inc(&data->mode_enter_attempts);
+		return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+	case CMD_EXIT_MODE:
+		/* Only exit a SVID we know we entered */
+		if (PD_VDO_VID(vdm_header) == data->entered_svid) {
+			uint32_t response_vdm_header;
+
+			response_vdm_header =
+				VDO(PD_VDO_VID(vdm_header), true,
+				    VDO_CMDT(CMDT_RSP_ACK) | CMD_EXIT_MODE);
+			tcpci_partner_send_data_msg(data, PD_DATA_VENDOR_DEF,
+						    &response_vdm_header, 1, 0);
+		} else {
+			uint32_t response_vdm_header;
+
+			response_vdm_header =
+				VDO(PD_VDO_VID(vdm_header), true,
+				    VDO_CMDT(CMDT_RSP_NAK) | CMD_EXIT_MODE);
+			tcpci_partner_send_data_msg(data, PD_DATA_VENDOR_DEF,
+						    &response_vdm_header, 1, 0);
+		}
+		data->displayport_configured = false;
+		return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+	case CMD_DP_STATUS:
+		if (data->dp_status_vdos > 0 &&
+		    (PD_VDO_VID(vdm_header) == USB_SID_DISPLAYPORT)) {
+			tcpci_partner_send_data_msg(data, PD_DATA_VENDOR_DEF,
+						    data->dp_status_vdm,
+						    data->dp_status_vdos, 0);
+		}
+		return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+	case CMD_DP_CONFIG:
+		if (data->dp_config_vdos > 0 &&
+		    (PD_VDO_VID(vdm_header) == USB_SID_DISPLAYPORT)) {
+			tcpci_partner_send_data_msg(data, PD_DATA_VENDOR_DEF,
+						    data->dp_config_vdm,
+						    data->dp_config_vdos, 0);
+			data->displayport_configured = true;
+		}
+		return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+	default:
+		/* TCPCI r. 2.0: Ignore unsupported commands. */
+		return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+	}
+}
+
+static enum tcpci_partner_handler_res
+tcpci_partner_enter_usb_handler(struct tcpci_partner_data *data,
+				const struct tcpci_emul_msg *message)
+{
+	/*
+	 * Validate received Enter_USB message against EUDO contents in
+	 * tcpci_partner_data.
+	 *
+	 * TODO(b/260095516): This support needs to be expanded to validate the
+	 * message contents, in a bit field basis. Currently, using this field
+	 * as simple ACCEPT/REJECT criteria. If this value is 0 (default case),
+	 * then ACCEPT this message, else reject it.
+	 */
+	if (data->enter_usb_accept)
+		tcpci_partner_send_control_msg(data, PD_CTRL_ACCEPT, 0);
+	else
+		tcpci_partner_send_control_msg(data, PD_CTRL_REJECT, 0);
+
+	return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+}
+
+static enum tcpci_partner_handler_res
+tcpci_partner_common_cable_handler(struct tcpci_partner_data *data,
+				   const struct tcpci_emul_msg *message,
+				   enum tcpci_msg_type sop_type)
+{
+	uint32_t vdm_header = sys_get_le32(message->buf + TCPCI_MSG_HEADER_LEN);
+	uint32_t response_vdm_header;
+	uint16_t header = sys_get_le16(&message->buf[0]);
+
+	/* TODO(b/243151272): Add soft reset support */
+	/* Ensure we are replying to a VDM */
+	if (PD_HEADER_CNT(header) == 0 ||
+	    PD_HEADER_TYPE(header) != PD_DATA_VENDOR_DEF ||
+	    PD_HEADER_EXT(header) != 0)
+		return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED;
+
+	/*
+	 * Ignore any VDMs which are not sent by an initiator.  As a cable, we
+	 * never expect to be the initiator processing ACKs.
+	 * TODO(b/225397796): Validate VDM fields more thoroughly.
+	 */
+	if (PD_VDO_CMDT(vdm_header) != CMDT_INIT || !PD_VDO_SVDM(vdm_header)) {
+		return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+	}
+
+	/* If we have no cable, we must not GoodCRC */
+	if (data->cable == NULL)
+		return TCPCI_PARTNER_COMMON_MSG_NO_GOODCRC;
+
+	/* TODO(b/243151272): Add SOP'' support */
+	if (sop_type == TCPCI_MSG_SOP_PRIME_PRIME) {
+		return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED;
+	}
+
+	switch (PD_VDO_CMD(vdm_header)) {
+	case CMD_DISCOVER_IDENT:
+		if (data->cable->identity_vdos > 0) {
+			tcpci_cable_send_data_msg(data, PD_DATA_VENDOR_DEF,
+						  data->cable->identity_vdm,
+						  data->cable->identity_vdos,
+						  TCPCI_MSG_SOP_PRIME, 0);
+			return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+		}
+		/* A cable with no identity shouldn't GoodCRC */
+		return TCPCI_PARTNER_COMMON_MSG_NO_GOODCRC;
+	default:
+		/*
+		 * Cable must support VDMs, so generate a NAK on unfamiliar
+		 * commands
+		 */
+		response_vdm_header =
+			VDO(PD_VDO_VID(vdm_header), true,
+			    VDO_CMDT(CMDT_RSP_NAK) | PD_VDO_CMD(vdm_header));
+		tcpci_cable_send_data_msg(data, PD_DATA_VENDOR_DEF,
+					  &response_vdm_header, 1, sop_type, 0);
+
+		return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+	}
+}
+
+/**
+ * @brief Handle a received Battery Capability message from the TCPC. Save the
+ *        contents to the emulator data struct for analysis.
+ *
+ * @param data Emulator state
+ * @param message Received PD message
+ * @return enum tcpci_partner_handler_res
+ */
+static enum tcpci_partner_handler_res
+tcpci_partner_common_battery_capability_handler(
+	struct tcpci_partner_data *data, const struct tcpci_emul_msg *message)
+{
+	uint16_t header = sys_get_le16(&message->buf[0]);
+	uint16_t ext_header = sys_get_le16(&message->buf[2]);
+
+	/* Validate message header */
+	__ASSERT(PD_HEADER_TYPE(header) == PD_EXT_BATTERY_CAP,
+		 "wrong message type");
+	__ASSERT(PD_EXT_HEADER_DATA_SIZE(ext_header) == 9,
+		 "Data size mismatch");
+
+	int index = data->battery_capabilities.index;
+
+	data->battery_capabilities.index = -1;
+
+	if (index < 0) {
+		LOG_ERR("Received a Battery Capability message but it was "
+			"never requested");
+		return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED;
+	}
+
+	__ASSERT(index < PD_BATT_MAX, "Battery index out of range");
+
+	data->battery_capabilities.bcdb[index] = (struct pd_bcdb){
+		.vid = sys_get_le16(&message->buf[4]),
+		.pid = sys_get_le16(&message->buf[6]),
+		.design_cap = sys_get_le16(&message->buf[8]),
+		.last_full_charge_cap = sys_get_le16(&message->buf[10]),
+		.battery_type = message->buf[12],
+	};
+
+	data->battery_capabilities.have_response[index] = true;
+
+	LOG_INF("Saved data for battery index (%d): vid=%04x, pid=%04x, "
+		"cap=%u, last_cap=%u, type=%02x",
+		index, data->battery_capabilities.bcdb[index].vid,
+		data->battery_capabilities.bcdb[index].pid,
+		data->battery_capabilities.bcdb[index].design_cap,
+		data->battery_capabilities.bcdb[index].last_full_charge_cap,
+		data->battery_capabilities.bcdb[index].battery_type);
+
+	return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+}
+
+static void tcpci_partner_common_set_vconn(struct tcpci_partner_data *data,
+					   enum pd_vconn_role role)
+{
+	data->vconn_role = role;
+}
+
+/**
+ * @brief Handle VCONN_SWAP message
+ *
+ * @return enum tcpci_partner_handler_res
+ */
+static enum tcpci_partner_handler_res
+tcpci_partner_common_vconn_swap_handler(struct tcpci_partner_data *data)
+{
+	tcpci_partner_common_set_ams_ctrl_msg(data, PD_CTRL_VCONN_SWAP);
+
+	tcpci_partner_send_control_msg(data, data->vcs_response, 0);
+
+	if (data->vcs_response != PD_CTRL_ACCEPT) {
+		tcpci_partner_common_clear_ams_ctrl_msg(data);
+		return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+	}
+
+	if (data->vconn_role == PD_ROLE_VCONN_OFF) {
+		tcpci_partner_common_set_vconn(data, PD_ROLE_VCONN_SRC);
+	}
+
+	/* PS ready after 15 ms */
+	tcpci_partner_send_control_msg(data, PD_CTRL_PS_RDY, 15);
+	return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+}
+
+static enum tcpci_partner_handler_res
+tcpci_partner_common_ps_rdy_vconn_swap_handler(struct tcpci_partner_data *data)
+{
+	tcpci_partner_common_clear_ams_ctrl_msg(data);
+
+	if (data->vconn_role == PD_ROLE_VCONN_SRC) {
+		tcpci_partner_common_set_vconn(data, PD_ROLE_VCONN_OFF);
+	}
+
+	return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+}
+
+void tcpci_partner_common_swap_data_role(struct tcpci_partner_data *data)
+{
+	if (data->data_role == PD_ROLE_UFP) {
+		data->data_role = PD_ROLE_DFP;
+	} else if (data->data_role == PD_ROLE_DFP) {
+		data->data_role = PD_ROLE_UFP;
+	} else {
+		/* PD_ROLE_DISCONNECTED - do nothing */
+	}
+}
+
+/**
+ * @brief Handle Incoming DR_SWAP request
+ *
+ * @return enum tcpci_partner_handler_res
+ */
+static enum tcpci_partner_handler_res
+tcpci_partner_common_dr_swap_handler(struct tcpci_partner_data *data)
+{
+	enum pd_ctrl_msg_type response = PD_CTRL_REJECT;
+
+	if ((data->data_role == PD_ROLE_DFP && data->drs_to_ufp_supported) ||
+	    (data->data_role == PD_ROLE_UFP && data->drs_to_dfp_supported))
+		response = PD_CTRL_ACCEPT;
+	tcpci_partner_send_control_msg(data, response, 0);
+	if (response == PD_CTRL_ACCEPT)
+		tcpci_partner_common_swap_data_role(data);
+
+	return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+}
+
+static enum tcpci_partner_handler_res
+tcpci_partner_common_accept_dr_swap_handler(struct tcpci_partner_data *data)
+{
+	tcpci_partner_common_clear_ams_ctrl_msg(data);
+
+	tcpci_partner_common_swap_data_role(data);
+
+	return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+}
+
+static enum tcpci_partner_handler_res
+tcpci_partner_common_accept_vconn_swap_handler(struct tcpci_partner_data *data)
+{
+	if (data->vconn_role == PD_ROLE_VCONN_SRC) {
+		/* TODO: Wait for PS_RDY. */
+	} else {
+		/* VCONN Swap from off to VCONN Source means the partner sends
+		 * the first PS_RDY after turning on VCONN.
+		 */
+		tcpci_partner_common_set_vconn(data, PD_ROLE_VCONN_ON);
+		tcpci_partner_send_control_msg(data, PD_CTRL_PS_RDY, 15);
+		tcpci_partner_common_clear_ams_ctrl_msg(data);
+		/* Strictly speaking, the AMS isn't over until the partner
+		 * receives GoodCRC for the PS_RDY.
+		 */
+	}
+
+	return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+}
+
+static enum tcpci_partner_handler_res
+tcpi_drp_emul_ps_rdy_handler(struct tcpci_partner_data *data)
+{
+	switch (data->cur_ams_ctrl_req) {
+	case PD_CTRL_VCONN_SWAP:
+		return tcpci_partner_common_ps_rdy_vconn_swap_handler(data);
+
+	default:
+		LOG_ERR("Unhandled current_req=%u in PS_RDY",
+			data->cur_ams_ctrl_req);
+		return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED;
+	}
+}
+
+static enum tcpci_partner_handler_res
+tcpi_partner_common_handle_accept(struct tcpci_partner_data *data)
+{
+	switch (data->cur_ams_ctrl_req) {
+	case PD_CTRL_VCONN_SWAP:
+		data->cur_ams_ctrl_req = PD_CTRL_INVALID;
+		return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+
+	default:
+		LOG_ERR("Unhandled current_req=%u in ACCEPT",
+			data->cur_ams_ctrl_req);
+		return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED;
+	}
+}
+
+static enum tcpci_partner_handler_res
+tcpci_partner_common_handle_reject(struct tcpci_partner_data *data)
+{
+	switch (data->cur_ams_ctrl_req) {
+	case PD_CTRL_DR_SWAP:
+		return tcpci_partner_common_accept_dr_swap_handler(data);
+	case PD_CTRL_VCONN_SWAP:
+		return tcpci_partner_common_accept_vconn_swap_handler(data);
+
+	default:
+		LOG_ERR("Unhandled current_req=%u in ACCEPT",
+			data->cur_ams_ctrl_req);
+		return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED;
+	}
+}
+
+/**
+ * @brief Common handler for TCPCI SOP messages. Only some messages are handled
+ *        here. It is expected that extensions cover other relevant messages.
+ *
+ * @param data Pointer to TCPCI partner emulator
+ * @param tx_msg Message received by partner emulator
+ *
+ * @param TCPCI_PARTNER_COMMON_MSG_HANDLED Message was handled by common code
+ * @param TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED Message wasn't handled
+ * @param TCPCI_PARTNER_COMMON_MSG_HARD_RESET Message was handled by sending
+ *                                            hard reset
+ */
+static enum tcpci_partner_handler_res
+tcpci_partner_common_sop_msg_handler(struct tcpci_partner_data *data,
+				     const struct tcpci_emul_msg *tx_msg)
+{
+	struct tcpci_partner_extension *ext;
+	uint16_t header;
+	int msg_type;
+
+	LOG_HEXDUMP_DBG(tx_msg->buf, tx_msg->cnt,
+			"USB-C partner emulator received message");
+
+	header = sys_get_le16(tx_msg->buf);
+	msg_type = PD_HEADER_TYPE(header);
+
+	if (PD_HEADER_ID(header) == data->sop_recv_msg_id &&
+	    msg_type != PD_CTRL_SOFT_RESET) {
+		/* Repeated message mark as handled */
+		return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+	}
+	data->sop_recv_msg_id = PD_HEADER_ID(header);
+
+	if (PD_HEADER_EXT(header)) {
+		/* Extended message */
+
+		if (PD_HEADER_REV(header) < PD_REV30) {
+			LOG_ERR("Received extended message but current PD rev "
+				"(0x%x) does not support them.",
+				PD_HEADER_REV(header));
+			return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED;
+		}
+
+		switch (PD_HEADER_TYPE(header)) {
+		case PD_EXT_GET_BATTERY_CAP:
+			/* Not implemented */
+			LOG_INF("Got PD_EXT_GET_BATTERY_CAP");
+			return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED;
+		case PD_EXT_BATTERY_CAP:
+			/* Received a Battery Capabilities response */
+			LOG_INF("Got PD_EXT_BATTERY_CAP");
+
+			return tcpci_partner_common_battery_capability_handler(
+				data, tx_msg);
+		default:
+			return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED;
+		}
+	}
+
+	if (PD_HEADER_CNT(header)) {
+		/* Data message */
+		switch (PD_HEADER_TYPE(header)) {
+		case PD_DATA_VENDOR_DEF:
+			return tcpci_partner_common_vdm_handler(data, tx_msg);
+		case PD_DATA_ENTER_USB:
+			return tcpci_partner_enter_usb_handler(data, tx_msg);
+		default:
+			/* No other common handlers for data messages */
+			return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED;
+		}
+	}
+
+	if (data->common_handler_masked & BIT(msg_type)) {
+		/* This message type is masked from common handler */
+		return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED;
+	}
+
+	/* Handle control message */
+	switch (PD_HEADER_TYPE(header)) {
+	case PD_CTRL_SOFT_RESET:
+		data->sop_msg_id = 0;
+		tcpci_partner_send_control_msg(data, PD_CTRL_ACCEPT, 0);
+
+		for (ext = data->extensions; ext != NULL; ext = ext->next) {
+			if (ext->ops->soft_reset) {
+				ext->ops->soft_reset(ext, data);
+			}
+		}
+
+		return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+
+	case PD_CTRL_VCONN_SWAP:
+		return tcpci_partner_common_vconn_swap_handler(data);
+
+	case PD_CTRL_DR_SWAP:
+		return tcpci_partner_common_dr_swap_handler(data);
+
+	case PD_CTRL_PS_RDY:
+		return tcpi_drp_emul_ps_rdy_handler(data);
+
+	case PD_CTRL_REJECT:
+		if (data->in_soft_reset) {
+			tcpci_partner_stop_sender_response_timer(data);
+			tcpci_partner_common_send_hard_reset(data);
+
+			return TCPCI_PARTNER_COMMON_MSG_HARD_RESET;
+		} else if (data->cur_ams_ctrl_req != PD_CTRL_INVALID) {
+			if (tcpci_partner_common_handle_reject(data) ==
+			    TCPCI_PARTNER_COMMON_MSG_HANDLED)
+				return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+		}
+
+		tcpci_partner_common_clear_ams_ctrl_msg(data);
+
+		__fallthrough;
+	case PD_CTRL_ACCEPT:
+		if (data->wait_for_response) {
+			if (data->in_soft_reset) {
+				/*
+				 * Accept is response to soft reset send by
+				 * common code. It is handled here
+				 */
+				tcpci_partner_stop_sender_response_timer(data);
+				data->in_soft_reset = false;
+
+				return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+			}
+			/*
+			 * Accept/reject is expected message and emulator code
+			 * should handle it
+			 */
+			return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED;
+		}
+
+		if (data->cur_ams_ctrl_req != PD_CTRL_INVALID) {
+			if (tcpi_partner_common_handle_accept(data) ==
+			    TCPCI_PARTNER_COMMON_MSG_HANDLED) {
+				return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+			}
+		}
+
+		/* Unexpected message - trigger soft reset */
+		tcpci_partner_common_send_soft_reset(data);
+
+		return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+	case PD_CTRL_DATA_RESET:
+		/*
+		 * Send Accept/Reject message
+		 * TODO(b/260095516): To fully exercise this code path, there
+		 * needs to be a mechanism (trigger) to either accept or reject
+		 * this message.
+		 */
+		tcpci_partner_send_control_msg(data, PD_CTRL_ACCEPT, 0);
+		return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+	case PD_CTRL_DATA_RESET_COMPLETE:
+		/* There is no expected reply message from the port parter */
+		return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+	}
+
+	return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED;
+}
+
+void tcpci_partner_common_handler_mask_msg(struct tcpci_partner_data *data,
+					   enum pd_ctrl_msg_type type,
+					   bool enable)
+{
+	if (enable) {
+		data->common_handler_masked |= BIT(type);
+	} else {
+		data->common_handler_masked &= ~BIT(type);
+	}
+}
+
+void tcpci_partner_set_discovery_info(struct tcpci_partner_data *data,
+				      int identity_vdos, uint32_t *identity_vdm,
+				      int svids_vdos, uint32_t *svids_vdm,
+				      int modes_vdos, uint32_t *modes_vdm)
+{
+	memset(data->identity_vdm, 0, sizeof(data->identity_vdm));
+	memset(data->svids_vdm, 0, sizeof(data->svids_vdm));
+	memset(data->modes_vdm, 0, sizeof(data->modes_vdm));
+
+	data->identity_vdos = identity_vdos;
+	memcpy(data->identity_vdm, identity_vdm,
+	       identity_vdos * sizeof(*identity_vdm));
+	data->svids_vdos = svids_vdos;
+	memcpy(data->svids_vdm, svids_vdm, svids_vdos * sizeof(*svids_vdm));
+	data->modes_vdos = modes_vdos;
+	memcpy(data->modes_vdm, modes_vdm, modes_vdos * sizeof(*modes_vdm));
+}
+
+static void tcpci_partner_common_control_change(struct tcpci_partner_data *data)
+{
+	const struct emul *tcpci_emul = data->tcpci_emul;
+	uint16_t role_control;
+
+	tcpci_emul_get_reg(tcpci_emul, TCPC_REG_ROLE_CTRL, &role_control);
+	data->tcpm_cc1 = TCPC_REG_ROLE_CTRL_CC1(role_control);
+	data->tcpm_cc1 = TCPC_REG_ROLE_CTRL_CC2(role_control);
+}
+
+void tcpci_partner_common_disconnect(struct tcpci_partner_data *data)
+{
+	tcpci_partner_clear_msg_queue(data);
+	tcpci_partner_stop_sender_response_timer(data);
+	data->tcpci_emul = NULL;
+	data->displayport_configured = false;
+	data->entered_svid = 0;
+	atomic_clear(&data->mode_enter_attempts);
+}
+
+int tcpci_partner_common_enable_pd_logging(struct tcpci_partner_data *data,
+					   bool enable)
+{
+	int ret;
+
+	ret = k_mutex_lock(&data->msg_log_mutex, K_FOREVER);
+	if (ret) {
+		return ret;
+	}
+
+	data->collect_msg_log = enable;
+
+	k_mutex_unlock(&data->msg_log_mutex);
+	return 0;
+}
+
+/** Names of senders used while printing logged PD messages */
+static char *tcpci_partner_sender_names[] = {
+	[TCPCI_PARTNER_SENDER_PARTNER] = "partner emulator",
+	[TCPCI_PARTNER_SENDER_TCPM] = "TCPM"
+};
+
+/**
+ * @brief Write string to the buffer starting from @p start byte.
+ *
+ * @param buf Pointer to the buffer
+ * @param buf_len Total length of the buffer
+ * @param start Byte from which start to write
+ * @param fmt Format strnig
+ * @param ... printf like arguments for format string
+ *
+ * @return Number of written bytes
+ */
+static __printf_like(4, 5) int tcpci_partner_print_to_buf(char *buf,
+							  const int buf_len,
+							  int start,
+							  const char *fmt, ...)
+{
+	va_list ap;
+	int ret;
+
+	va_start(ap, fmt);
+	ret = vsnprintk(buf + start, buf_len - start, fmt, ap);
+	va_end(ap);
+
+	if (ret <= 0) {
+		LOG_ERR("vsnprintk failed %d", ret);
+		ret = 0;
+	}
+
+	return ret;
+}
+
+void tcpci_partner_common_print_logged_msgs(struct tcpci_partner_data *data)
+{
+	struct tcpci_partner_log_msg *msg;
+	const int max_pd_msg_log_len = 200;
+	const int buf_len = 8192;
+	uint16_t header;
+	char buf[buf_len];
+	int chars_in = 0;
+	int ret;
+	int i;
+
+	ret = k_mutex_lock(&data->msg_log_mutex, K_FOREVER);
+	if (ret) {
+		return;
+	}
+
+	chars_in += tcpci_partner_print_to_buf(buf, buf_len, chars_in,
+					       "===PD messages log:\n");
+
+	SYS_SLIST_FOR_EACH_CONTAINER(&data->msg_log, msg, node)
+	{
+		/*
+		 * If there is too many messages to keep them in local buffer,
+		 * accept possibility of lines interleaving on console and print
+		 * buffer to console.
+		 */
+		if (chars_in >= buf_len - max_pd_msg_log_len) {
+			LOG_PRINTK("%s", buf);
+			chars_in = 0;
+		}
+		chars_in += tcpci_partner_print_to_buf(
+			buf, buf_len, chars_in,
+			"\tAt %lld Msg SOP %d from %s (status 0x%x):\n",
+			msg->time, msg->sop,
+			tcpci_partner_sender_names[msg->sender], msg->status);
+		header = sys_get_le16(msg->buf);
+		chars_in += tcpci_partner_print_to_buf(
+			buf, buf_len, chars_in,
+			"\t\text=%d;cnt=%d;id=%d;pr=%d;dr=%d;rev=%d;type=%d\n",
+			PD_HEADER_EXT(header), PD_HEADER_CNT(header),
+			PD_HEADER_ID(header), PD_HEADER_PROLE(header),
+			PD_HEADER_DROLE(header), PD_HEADER_REV(header),
+			PD_HEADER_TYPE(header));
+		chars_in += tcpci_partner_print_to_buf(buf, buf_len, chars_in,
+						       "\t\t");
+		for (i = 0; i < msg->cnt; i++) {
+			chars_in += tcpci_partner_print_to_buf(
+				buf, buf_len, chars_in, "%02x ", msg->buf[i]);
+		}
+		chars_in += tcpci_partner_print_to_buf(buf, buf_len, chars_in,
+						       "\n");
+	}
+	LOG_PRINTK("%s===\n", buf);
+
+	k_mutex_unlock(&data->msg_log_mutex);
+}
+
+void tcpci_partner_common_clear_logged_msgs(struct tcpci_partner_data *data)
+{
+	struct tcpci_partner_log_msg *msg;
+	int ret;
+
+	ret = k_mutex_lock(&data->msg_log_mutex, K_FOREVER);
+	if (ret) {
+		return;
+	}
+
+	while (!sys_slist_is_empty(&data->msg_log)) {
+		msg = CONTAINER_OF(sys_slist_get_not_empty(&data->msg_log),
+				   struct tcpci_partner_log_msg, node);
+		free(msg->buf);
+		free(msg);
+	}
+
+	k_mutex_unlock(&data->msg_log_mutex);
+}
+
+/**
+ * @brief Sets cur_ams_ctrl_req to msg_type to track current request
+ *
+ * @param data          Pointer to TCPCI partner data
+ * @param msg_type      enum pd_ctrl_msg_type
+ */
+void tcpci_partner_common_set_ams_ctrl_msg(struct tcpci_partner_data *data,
+					   enum pd_ctrl_msg_type msg_type)
+{
+	/* Make sure we handle one CTRL request at a time */
+	zassert_equal(data->cur_ams_ctrl_req, PD_CTRL_INVALID,
+		      "More than one CTRL msg handled in parallel"
+		      " cur_ams_ctrl_req=%d, msg_type=%d",
+		      data->cur_ams_ctrl_req, msg_type);
+	data->cur_ams_ctrl_req = msg_type;
+}
+
+/**
+ * @brief Sets cur_ams_ctrl_req to INVALID
+ *
+ * @param data          Pointer to TCPCI partner data
+ */
+void tcpci_partner_common_clear_ams_ctrl_msg(struct tcpci_partner_data *data)
+{
+	data->cur_ams_ctrl_req = PD_CTRL_INVALID;
+}
+
+void tcpci_partner_received_msg_status(struct tcpci_partner_data *data,
+				       enum tcpci_emul_tx_status status)
+{
+	tcpci_emul_partner_msg_status(data->tcpci_emul, status);
+
+	if (data->received_msg_status == NULL) {
+		return;
+	}
+	/*
+	 * Status of each received message should be reported to TCPCI emulator
+	 * only once
+	 */
+	if (*data->received_msg_status != TCPCI_EMUL_TX_UNKNOWN) {
+		LOG_WRN("Changing status of received message more than once");
+	}
+	*data->received_msg_status = status;
+}
+
+/**
+ * @brief Function called when TCPM wants to transmit message. Accept received
+ *        message and generate response.
+ *
+ * @param emul Pointer to TCPCI emulator
+ * @param ops Pointer to partner operations structure
+ * @param tx_msg Pointer to TX message buffer
+ * @param type Type of message
+ * @param retry Count of retries
+ */
+static void tcpci_partner_transmit_op(const struct emul *emul,
+				      const struct tcpci_emul_partner_ops *ops,
+				      const struct tcpci_emul_msg *tx_msg,
+				      enum tcpci_msg_type type, int retry)
+{
+	struct tcpci_partner_data *data =
+		CONTAINER_OF(ops, struct tcpci_partner_data, ops);
+	enum tcpci_partner_handler_res processed;
+	struct tcpci_partner_extension *ext;
+	int ret;
+
+	data->received_msg_status = tcpci_partner_log_msg(
+		data, tx_msg, TCPCI_PARTNER_SENDER_TCPM, TCPCI_EMUL_TX_UNKNOWN);
+
+	ret = k_mutex_lock(&data->transmit_mutex, K_FOREVER);
+	if (ret) {
+		LOG_ERR("Failed to get partner mutex");
+		/* Inform TCPM that message send failed */
+		if (type != TCPCI_MSG_TX_HARD_RESET &&
+		    type != TCPCI_MSG_CABLE_RESET) {
+			tcpci_partner_received_msg_status(data,
+							  TCPCI_EMUL_TX_FAILED);
+		}
+		return;
+	}
+
+	/* Handle hard reset */
+	if (type == TCPCI_MSG_TX_HARD_RESET) {
+		tcpci_partner_common_hard_reset(data);
+		goto message_handled;
+	}
+
+	/* Skip handling of non-SOP/SOP'/SOP'' messages */
+	if (type > TCPCI_MSG_SOP_PRIME_PRIME) {
+		/* Never send GoodCRC for cable reset */
+		if (data->send_goodcrc && type != TCPCI_MSG_CABLE_RESET) {
+			tcpci_partner_received_msg_status(
+				data, TCPCI_EMUL_TX_SUCCESS);
+		}
+		goto message_handled;
+	}
+
+	/* Call common SOP handler */
+	if (type == TCPCI_MSG_SOP) {
+		processed = tcpci_partner_common_sop_msg_handler(data, tx_msg);
+	} else {
+		processed =
+			tcpci_partner_common_cable_handler(data, tx_msg, type);
+	}
+	if (processed == TCPCI_PARTNER_COMMON_MSG_NO_GOODCRC) {
+		/*
+		 * Fail message send if common handler knows message shouldn't
+		 * transit successfully.
+		 */
+		tcpci_partner_received_msg_status(data, TCPCI_EMUL_TX_FAILED);
+		goto message_handled;
+	} else if (data->send_goodcrc ||
+		   processed != TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED) {
+		/* Always send GoodCRC for messages handled by common handler */
+		tcpci_partner_received_msg_status(data, TCPCI_EMUL_TX_SUCCESS);
+	}
+
+	/* Continue only for unhandled messages */
+	if (processed != TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED) {
+		goto message_handled;
+	}
+
+	for (ext = data->extensions; ext != NULL; ext = ext->next) {
+		if (ext->ops->sop_msg_handler == NULL) {
+			continue;
+		}
+		processed = ext->ops->sop_msg_handler(ext, data, tx_msg);
+		if (processed == TCPCI_PARTNER_COMMON_MSG_HANDLED) {
+			goto message_handled;
+		}
+	}
+
+	/* Send reject for not handled messages (PD rev 2.0) */
+	tcpci_partner_send_control_msg(data, PD_CTRL_REJECT, 0);
+
+message_handled:
+	k_mutex_unlock(&data->transmit_mutex);
+}
+
+/**
+ * @brief Function called when TCPM consumes message. Free message that is no
+ *        longer needed.
+ *
+ * @param emul Pointer to TCPCI emulator
+ * @param ops Pointer to partner operations structure
+ * @param rx_msg Message that was consumed by TCPM
+ */
+static void
+tcpci_partner_rx_consumed_op(const struct emul *emul,
+			     const struct tcpci_emul_partner_ops *ops,
+			     const struct tcpci_emul_msg *rx_msg)
+{
+	struct tcpci_partner_msg *msg =
+		CONTAINER_OF(rx_msg, struct tcpci_partner_msg, msg);
+
+	tcpci_partner_free_msg(msg);
+}
+
+static void
+tcpci_partner_control_change_op(const struct emul *emul,
+				const struct tcpci_emul_partner_ops *ops)
+{
+	struct tcpci_partner_data *data =
+		CONTAINER_OF(ops, struct tcpci_partner_data, ops);
+	struct tcpci_partner_extension *ext;
+
+	tcpci_partner_common_control_change(data);
+	for (ext = data->extensions; ext != NULL; ext = ext->next) {
+		if (ext->ops->control_change) {
+			ext->ops->control_change(ext, data);
+		}
+	}
+}
+
+/**
+ * @brief Function called when emulator is disconnected from TCPCI
+ *
+ * @param emul Pointer to TCPCI emulator
+ * @param ops Pointer to partner operations structure
+ */
+static void
+tcpci_partner_disconnect_op(const struct emul *emul,
+			    const struct tcpci_emul_partner_ops *ops)
+{
+	struct tcpci_partner_data *data =
+		CONTAINER_OF(ops, struct tcpci_partner_data, ops);
+	struct tcpci_partner_extension *ext;
+
+	tcpci_partner_common_disconnect(data);
+	for (ext = data->extensions; ext != NULL; ext = ext->next) {
+		if (ext->ops->disconnect) {
+			ext->ops->disconnect(ext, data);
+		}
+	}
+}
+
+int tcpci_partner_connect_to_tcpci(struct tcpci_partner_data *data,
+				   const struct emul *tcpci_emul)
+{
+	struct tcpci_partner_extension *ext;
+	int ret;
+
+	data->tcpci_emul = tcpci_emul;
+
+	for (ext = data->extensions; ext != NULL; ext = ext->next) {
+		if (ext->ops->connect == NULL) {
+			continue;
+		}
+		ret = ext->ops->connect(ext, data);
+		if (ret) {
+			data->tcpci_emul = NULL;
+			return ret;
+		}
+	}
+
+	/* Try to connect using current state of partner emulator */
+	tcpci_emul_set_partner_ops(data->tcpci_emul, &data->ops);
+	ret = tcpci_emul_connect_partner(data->tcpci_emul, data->power_role,
+					 data->cc1, data->cc2, data->polarity);
+	if (ret) {
+		tcpci_emul_set_partner_ops(data->tcpci_emul, NULL);
+		data->tcpci_emul = NULL;
+	}
+
+	/* Clear any received battery capability info */
+	tcpci_partner_reset_battery_capability_state(data);
+
+	return ret;
+}
+
+void tcpci_partner_reset_battery_capability_state(
+	struct tcpci_partner_data *data)
+{
+	memset(&data->battery_capabilities, 0,
+	       sizeof(data->battery_capabilities));
+	data->battery_capabilities.index = -1;
+}
+
+void tcpci_partner_init(struct tcpci_partner_data *data, enum pd_rev_type rev)
+{
+	k_timer_init(&data->delayed_send, tcpci_partner_delayed_send_timer,
+		     NULL);
+	k_work_init_delayable(&data->sender_response_timeout,
+			      tcpci_partner_sender_response_timeout);
+	sys_slist_init(&data->to_send);
+	k_mutex_init(&data->to_send_mutex);
+	k_mutex_init(&data->transmit_mutex);
+	sys_slist_init(&data->msg_log);
+	k_mutex_init(&data->msg_log_mutex);
+	data->collect_msg_log = false;
+	tcpci_partner_common_reset(data);
+	data->tcpm_timeouts = 0;
+	data->identity_vdos = 0;
+	data->svids_vdos = 0;
+	data->modes_vdos = 0;
+	data->rmdo = 0;
+	data->enter_usb_accept = false;
+
+	tcpci_partner_common_clear_ams_ctrl_msg(data);
+
+	data->send_goodcrc = true;
+
+	data->rev = rev;
+	data->drs_to_dfp_supported = true;
+	data->drs_to_ufp_supported = true;
+	data->vcs_response = PD_CTRL_ACCEPT;
+
+	data->ops.transmit = tcpci_partner_transmit_op;
+	data->ops.rx_consumed = tcpci_partner_rx_consumed_op;
+	data->ops.control_change = tcpci_partner_control_change_op;
+	data->ops.disconnect = tcpci_partner_disconnect_op;
+	data->displayport_configured = false;
+	data->entered_svid = 0;
+	atomic_clear(&data->mode_enter_attempts);
+
+	/* Reset the data structure used to store battery capability responses
+	 */
+	tcpci_partner_reset_battery_capability_state(data);
+
+	data->cable = NULL;
+}
+
+void tcpci_partner_set_drs_support(struct tcpci_partner_data *data,
+				   bool drs_to_ufp_supported,
+				   bool drs_to_dfp_supported)
+{
+	data->drs_to_ufp_supported = drs_to_ufp_supported;
+	data->drs_to_dfp_supported = drs_to_dfp_supported;
+}
+
+void tcpci_partner_set_vcs_response(struct tcpci_partner_data *data,
+				    enum pd_ctrl_msg_type vcs_response)
+{
+	data->vcs_response = vcs_response;
+}
diff --git a/zephyr/emul/tcpc/emul_tcpci_partner_drp.c b/zephyr/emul/tcpc/emul_tcpci_partner_drp.c
new file mode 100644
index 0000000000..45fa21d972
--- /dev/null
+++ b/zephyr/emul/tcpc/emul_tcpci_partner_drp.c
@@ -0,0 +1,173 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "emul/tcpc/emul_tcpci.h"
+#include "emul/tcpc/emul_tcpci_partner_common.h"
+#include "emul/tcpc/emul_tcpci_partner_drp.h"
+#include "emul/tcpc/emul_tcpci_partner_snk.h"
+#include "emul/tcpc/emul_tcpci_partner_src.h"
+#include "tcpm/tcpci.h"
+#include "usb_pd.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/byteorder.h>
+
+LOG_MODULE_REGISTER(tcpci_drp_emul, CONFIG_TCPCI_EMUL_LOG_LEVEL);
+
+/**
+ * @brief Handle SOP messages as TCPCI dual role device
+ *
+ * @param ext Pointer to USB-C DRP device emulator extension
+ * @param common_data Pointer to USB-C device emulator common data
+ * @param msg Pointer to received message
+ *
+ * @return TCPCI_PARTNER_COMMON_MSG_HANDLED Message was handled
+ * @return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED Message wasn't handled
+ */
+static enum tcpci_partner_handler_res
+tcpci_drp_emul_handle_sop_msg(struct tcpci_partner_extension *ext,
+			      struct tcpci_partner_data *common_data,
+			      const struct tcpci_emul_msg *msg)
+{
+	struct tcpci_drp_emul_data *data =
+		CONTAINER_OF(ext, struct tcpci_drp_emul_data, ext);
+	uint16_t pwr_status;
+	uint16_t header;
+
+	header = sys_get_le16(msg->buf);
+
+	if (PD_HEADER_CNT(header)) {
+		/* Handle data message */
+		switch (PD_HEADER_TYPE(header)) {
+		case PD_DATA_REQUEST:
+			if (common_data->power_role == PD_ROLE_SINK) {
+				/* As sink we shouldn't accept request */
+				tcpci_partner_send_control_msg(
+					common_data, PD_CTRL_REJECT, 0);
+				return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+			}
+			/* As source, let source handler to handle this */
+			return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED;
+		case PD_DATA_SOURCE_CAP:
+			if (common_data->power_role == PD_ROLE_SOURCE) {
+				/* As source we shouldn't respond */
+				return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+			}
+			/* As sink, let sink handler to handle this */
+			return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED;
+		}
+	} else {
+		/* Handle control message */
+		switch (PD_HEADER_TYPE(header)) {
+		case PD_CTRL_PR_SWAP:
+			tcpci_partner_send_control_msg(common_data,
+						       PD_CTRL_ACCEPT, 0);
+			data->in_pwr_swap = true;
+			return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+		case PD_CTRL_PS_RDY:
+			if (!data->in_pwr_swap) {
+				return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED;
+			}
+			data->in_pwr_swap = false;
+
+			/* Reset counters */
+			common_data->sop_msg_id = 0;
+			common_data->sop_recv_msg_id = -1;
+
+			/* Perform power role swap */
+			if (common_data->power_role == PD_ROLE_SOURCE) {
+				/* Disable VBUS if emulator was source */
+				tcpci_emul_get_reg(common_data->tcpci_emul,
+						   TCPC_REG_POWER_STATUS,
+						   &pwr_status);
+				pwr_status &= ~TCPC_REG_POWER_STATUS_VBUS_PRES;
+				tcpci_emul_set_reg(common_data->tcpci_emul,
+						   TCPC_REG_POWER_STATUS,
+						   pwr_status);
+				/* Reconnect as sink */
+				common_data->power_role = PD_ROLE_SINK;
+			} else {
+				/* Reconnect as source */
+				common_data->power_role = PD_ROLE_SOURCE;
+			}
+			tcpci_partner_send_control_msg(common_data,
+						       PD_CTRL_PS_RDY, 0);
+			/* Reconnect to TCPCI emulator */
+			tcpci_partner_connect_to_tcpci(common_data,
+						       common_data->tcpci_emul);
+
+			return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+		}
+	}
+
+	return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED;
+}
+
+void tcpci_drp_emul_set_dr_in_first_pdo(uint32_t *pdo)
+{
+	*pdo |= PDO_FIXED_DUAL_ROLE;
+}
+
+/**
+ * @brief Perform action required by DRP device on hard reset. Reset role to
+ *        initial values
+ *
+ * @param ext Pointer to USB-C DRP device emulator extension
+ * @param common_data Pointer to USB-C device emulator common data
+ */
+static void tcpci_drp_emul_hard_reset(struct tcpci_partner_extension *ext,
+				      struct tcpci_partner_data *common_data)
+{
+	struct tcpci_drp_emul_data *data =
+		CONTAINER_OF(ext, struct tcpci_drp_emul_data, ext);
+
+	tcpci_partner_common_hard_reset_as_role(common_data,
+						data->initial_power_role);
+}
+
+/** USB-C DRP device extension callbacks */
+struct tcpci_partner_extension_ops tcpci_drp_emul_ops = {
+	.sop_msg_handler = tcpci_drp_emul_handle_sop_msg,
+	.hard_reset = tcpci_drp_emul_hard_reset,
+	.soft_reset = NULL,
+	.disconnect = NULL,
+	.connect = NULL,
+};
+
+struct tcpci_partner_extension *
+tcpci_drp_emul_init(struct tcpci_drp_emul_data *data,
+		    struct tcpci_partner_data *common_data,
+		    enum pd_power_role power_role,
+		    struct tcpci_partner_extension *src_ext,
+		    struct tcpci_partner_extension *snk_ext)
+{
+	struct tcpci_partner_extension *drp_ext = &data->ext;
+	struct tcpci_src_emul_data *src_data =
+		CONTAINER_OF(src_ext, struct tcpci_src_emul_data, ext);
+	struct tcpci_snk_emul_data *snk_data =
+		CONTAINER_OF(snk_ext, struct tcpci_snk_emul_data, ext);
+
+	data->in_pwr_swap = false;
+
+	tcpci_drp_emul_set_dr_in_first_pdo(src_data->pdo);
+	tcpci_drp_emul_set_dr_in_first_pdo(snk_data->pdo);
+
+	/* Use common handler to initialize roles */
+	data->initial_power_role = power_role;
+	tcpci_partner_common_hard_reset_as_role(common_data, power_role);
+
+	drp_ext->ops = &tcpci_drp_emul_ops;
+	/* Put sink as next extension to DRP */
+	drp_ext->next = snk_ext;
+	/* Put source after last extension in sink extensions chain */
+	while (snk_ext->next != NULL) {
+		snk_ext = snk_ext->next;
+	}
+	snk_ext->next = src_ext;
+
+	return drp_ext;
+}
diff --git a/zephyr/emul/tcpc/emul_tcpci_partner_faulty_ext.c b/zephyr/emul/tcpc/emul_tcpci_partner_faulty_ext.c
new file mode 100644
index 0000000000..818de3bff9
--- /dev/null
+++ b/zephyr/emul/tcpc/emul_tcpci_partner_faulty_ext.c
@@ -0,0 +1,155 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "emul/tcpc/emul_tcpci.h"
+#include "emul/tcpc/emul_tcpci_partner_common.h"
+#include "emul/tcpc/emul_tcpci_partner_faulty_ext.h"
+#include "usb_pd.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/byteorder.h>
+
+LOG_MODULE_REGISTER(tcpci_faulty_ext, CONFIG_TCPCI_EMUL_LOG_LEVEL);
+
+/**
+ * @brief Reduce number of times to repeat action. If count reaches zero, action
+ *        is removed from queue.
+ *
+ * @param data Pointer to USB-C malfunctioning device extension data
+ */
+static void
+tcpci_faulty_ext_reduce_action_count(struct tcpci_faulty_ext_data *data)
+{
+	struct tcpci_faulty_ext_action *action;
+	void *buf;
+
+	action = k_fifo_peek_head(&data->action_list);
+
+	if (action->count == TCPCI_FAULTY_EXT_INFINITE_ACTION) {
+		return;
+	}
+
+	action->count--;
+	if (action->count != 0) {
+		return;
+	}
+
+	/* Remove action from queue */
+	buf = k_fifo_get(&data->action_list, K_FOREVER);
+}
+
+void tcpci_faulty_ext_append_action(struct tcpci_faulty_ext_data *data,
+				    struct tcpci_faulty_ext_action *action)
+{
+	k_fifo_put(&data->action_list, action);
+}
+
+void tcpci_faulty_ext_clear_actions_list(struct tcpci_faulty_ext_data *data)
+{
+	void *buf;
+	while (!k_fifo_is_empty(&data->action_list)) {
+		buf = k_fifo_get(&data->action_list, K_FOREVER);
+	}
+}
+
+/**
+ * @brief Handle SOP messages as TCPCI malfunctioning device
+ *
+ * @param ext Pointer to USB-C malfunctioning device emulator extension
+ * @param common_data Pointer to USB-C device emulator common data
+ * @param msg Pointer to received message
+ *
+ * @return TCPCI_PARTNER_COMMON_MSG_HANDLED Message was handled
+ * @return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED Message wasn't handled
+ */
+static enum tcpci_partner_handler_res
+tcpci_faulty_ext_handle_sop_msg(struct tcpci_partner_extension *ext,
+				struct tcpci_partner_data *common_data,
+				const struct tcpci_emul_msg *msg)
+{
+	struct tcpci_faulty_ext_data *data =
+		CONTAINER_OF(ext, struct tcpci_faulty_ext_data, ext);
+	struct tcpci_faulty_ext_action *action;
+	uint16_t header;
+
+	action = k_fifo_peek_head(&data->action_list);
+	header = sys_get_le16(msg->buf);
+
+	if (action == NULL) {
+		/* No faulty action, so send GoodCRC */
+		tcpci_emul_partner_msg_status(common_data->tcpci_emul,
+					      TCPCI_EMUL_TX_SUCCESS);
+
+		return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED;
+	}
+
+	if (PD_HEADER_CNT(header)) {
+		/* Handle data message */
+		switch (PD_HEADER_TYPE(header)) {
+		case PD_DATA_SOURCE_CAP:
+			if (action->action_mask &
+			    TCPCI_FAULTY_EXT_FAIL_SRC_CAP) {
+				/* Fail is not sending GoodCRC from partner */
+				tcpci_partner_received_msg_status(
+					common_data, TCPCI_EMUL_TX_FAILED);
+				tcpci_faulty_ext_reduce_action_count(data);
+				return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+			}
+			if (action->action_mask &
+			    TCPCI_FAULTY_EXT_DISCARD_SRC_CAP) {
+				/* Discard because partner is sending message */
+				tcpci_partner_received_msg_status(
+					common_data, TCPCI_EMUL_TX_DISCARDED);
+				tcpci_partner_send_control_msg(
+					common_data, PD_CTRL_ACCEPT, 0);
+				tcpci_faulty_ext_reduce_action_count(data);
+				return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+			}
+			if (action->action_mask &
+			    TCPCI_FAULTY_EXT_IGNORE_SRC_CAP) {
+				/* Send only GoodCRC */
+				tcpci_partner_received_msg_status(
+					common_data, TCPCI_EMUL_TX_SUCCESS);
+				tcpci_faulty_ext_reduce_action_count(data);
+				return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+			}
+		}
+	}
+
+	/*
+	 * Send GoodCRC for all unhandled messages, since we disabled it in
+	 * common handler
+	 */
+	tcpci_partner_received_msg_status(common_data, TCPCI_EMUL_TX_SUCCESS);
+
+	return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED;
+}
+
+/** USB-C malfunctioning device extension callbacks */
+struct tcpci_partner_extension_ops tcpci_faulty_ext_ops = {
+	.sop_msg_handler = tcpci_faulty_ext_handle_sop_msg,
+	.hard_reset = NULL,
+	.soft_reset = NULL,
+	.disconnect = NULL,
+	.connect = NULL,
+};
+
+struct tcpci_partner_extension *
+tcpci_faulty_ext_init(struct tcpci_faulty_ext_data *data,
+		      struct tcpci_partner_data *common_data,
+		      struct tcpci_partner_extension *ext)
+{
+	struct tcpci_partner_extension *faulty_ext = &data->ext;
+
+	k_fifo_init(&data->action_list);
+	common_data->send_goodcrc = false;
+
+	faulty_ext->next = ext;
+	faulty_ext->ops = &tcpci_faulty_ext_ops;
+
+	return faulty_ext;
+}
diff --git a/zephyr/emul/tcpc/emul_tcpci_partner_snk.c b/zephyr/emul/tcpc/emul_tcpci_partner_snk.c
new file mode 100644
index 0000000000..d14012af41
--- /dev/null
+++ b/zephyr/emul/tcpc/emul_tcpci_partner_snk.c
@@ -0,0 +1,523 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "emul/tcpc/emul_tcpci.h"
+#include "emul/tcpc/emul_tcpci_partner_common.h"
+#include "emul/tcpc/emul_tcpci_partner_snk.h"
+#include "usb_pd.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/byteorder.h>
+
+LOG_MODULE_REGISTER(tcpci_snk_emul, CONFIG_TCPCI_EMUL_LOG_LEVEL);
+
+/** Length of PDO, RDO and BIST request object in SOP message in bytes */
+#define TCPCI_MSG_DO_LEN 4
+/** Length of header in SOP message in bytes  */
+#define TCPCI_MSG_HEADER_LEN 2
+
+/**
+ * @brief Get number of PDOs that will be present in sink capability message
+ *
+ * @param data Pointer to USB-C sink emulator
+ *
+ * @return Number of PDOs that will be present in sink capability message
+ */
+static int tcpci_snk_emul_num_of_pdos(struct tcpci_snk_emul_data *data)
+{
+	for (int pdos = 0; pdos < PDO_MAX_OBJECTS; pdos++) {
+		if (data->pdo[pdos] == 0) {
+			return pdos;
+		}
+	}
+
+	return PDO_MAX_OBJECTS;
+}
+
+/**
+ * @brief Send capability message constructed from USB-C sink emulator PDOs
+ *
+ * @param data Pointer to USB-C sink emulator
+ * @param common_data Pointer to common TCPCI partner data
+ * @param delay Optional delay
+ *
+ * @return TCPCI_EMUL_TX_SUCCESS on success
+ * @return TCPCI_EMUL_TX_FAILED when TCPCI is configured to not handle
+ *                              messages of this type
+ * @return -ENOMEM when there is no free memory for message
+ * @return -EINVAL on TCPCI emulator add RX message error
+ */
+static int
+tcpci_snk_emul_send_capability_msg(struct tcpci_snk_emul_data *data,
+				   struct tcpci_partner_data *common_data,
+				   uint64_t delay)
+{
+	int pdos;
+
+	/* Find number of PDOs */
+	pdos = tcpci_snk_emul_num_of_pdos(data);
+
+	return tcpci_partner_send_data_msg(common_data, PD_DATA_SINK_CAP,
+					   data->pdo, pdos, delay);
+}
+
+/**
+ * @brief Check if given source PDO satisfy given sink PDO
+ *
+ * @param src_pdo PDO presented in source capabilities
+ * @param snk_pdo PDO presented in sink capabilities
+ *
+ * @return 0 on success
+ * @return -1 if PDOs are different types, PDOs type is unknown or source
+ *         voltage not satisfy sink
+ * @return Positive value when voltage is OK, but source cannot provide enough
+ *         current for sink. Amount of missing current is returned value in
+ *         10mA units.
+ */
+static int tcpci_snk_emul_are_pdos_complementary(uint32_t src_pdo,
+						 uint32_t snk_pdo)
+{
+	uint32_t pdo_type = src_pdo & PDO_TYPE_MASK;
+	int missing_current;
+
+	if ((snk_pdo & PDO_TYPE_MASK) != pdo_type) {
+		return -1;
+	}
+
+	switch (pdo_type) {
+	case PDO_TYPE_FIXED:
+		if (PDO_FIXED_VOLTAGE(snk_pdo) != PDO_FIXED_VOLTAGE(src_pdo)) {
+			/* Voltage doesn't match */
+			return -1;
+		}
+		missing_current =
+			PDO_FIXED_CURRENT(snk_pdo) - PDO_FIXED_CURRENT(src_pdo);
+		break;
+	case PDO_TYPE_BATTERY:
+		if ((PDO_BATT_MIN_VOLTAGE(snk_pdo) <
+		     PDO_BATT_MIN_VOLTAGE(src_pdo)) ||
+		    (PDO_BATT_MAX_VOLTAGE(snk_pdo) >
+		     PDO_BATT_MAX_VOLTAGE(src_pdo))) {
+			/* Voltage not in range */
+			return -1;
+		}
+		/*
+		 * Convert to current I * 10[mA] = P * 250[mW] / V * 50[mV]
+		 * = P / V * 5 [A] = P / V * 500 * 10[mA]
+		 */
+		missing_current = (PDO_BATT_MAX_POWER(snk_pdo) -
+				   PDO_BATT_MAX_POWER(src_pdo)) *
+				  500 / PDO_BATT_MAX_VOLTAGE(src_pdo);
+		break;
+	case PDO_TYPE_VARIABLE:
+		if ((PDO_VAR_MIN_VOLTAGE(snk_pdo) <
+		     PDO_VAR_MIN_VOLTAGE(src_pdo)) ||
+		    (PDO_VAR_MAX_VOLTAGE(snk_pdo) >
+		     PDO_VAR_MAX_VOLTAGE(src_pdo))) {
+			/* Voltage not in range */
+			return -1;
+		}
+		missing_current = PDO_VAR_MAX_CURRENT(snk_pdo) -
+				  PDO_VAR_MAX_CURRENT(src_pdo);
+		break;
+	default:
+		/* Unknown PDO type */
+		return -1;
+	}
+
+	if (missing_current > 0) {
+		/* Voltage is correct, but src doesn't offer enough current */
+		return missing_current;
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Get given PDO from source capability message
+ *
+ * @param msg Source capability message
+ * @param pdo_num Number of PDO to get. First PDO is 0.
+ *
+ * @return PDO on success
+ * @return 0 when there is no PDO of given index in message
+ */
+static uint32_t
+tcpci_snk_emul_get_pdo_from_cap(const struct tcpci_emul_msg *msg, int pdo_num)
+{
+	int addr;
+
+	/* Get address of PDO in message */
+	addr = TCPCI_MSG_HEADER_LEN + pdo_num * TCPCI_MSG_DO_LEN;
+
+	if (addr >= msg->cnt) {
+		return 0;
+	}
+
+	return sys_get_le32(msg->buf + addr);
+}
+
+/**
+ * @brief Create RDO for given sink and source PDOs
+ *
+ * @param src_pdo Selected source PDO
+ * @param snk_pdo Matching sink PDO
+ * @param src_pdo_num Index of source PDO in capability message. First PDO is 1.
+ *
+ * @return RDO on success
+ * @return 0 When type of PDOs doesn't match
+ */
+static uint32_t tcpci_snk_emul_create_rdo(uint32_t src_pdo, uint32_t snk_pdo,
+					  int src_pdo_num)
+{
+	uint32_t pdo_type = src_pdo & PDO_TYPE_MASK;
+	int flags;
+	int pow;
+	int cur;
+
+	if ((snk_pdo & PDO_TYPE_MASK) != pdo_type) {
+		return 0;
+	}
+
+	switch (pdo_type) {
+	case PDO_TYPE_FIXED:
+		if (PDO_FIXED_CURRENT(snk_pdo) > PDO_FIXED_CURRENT(src_pdo)) {
+			flags = RDO_CAP_MISMATCH;
+			cur = PDO_FIXED_CURRENT(src_pdo);
+		} else {
+			flags = 0;
+			cur = PDO_FIXED_CURRENT(snk_pdo);
+		}
+
+		/*
+		 * Force mismatch flag if higher capability bit is set. Flags
+		 * should be set only in the first PDO (vSafe5V). This statment
+		 * will only be true for sink which requries higher voltage than
+		 * 5V and doesn't found it in source capabilities.
+		 */
+		if (snk_pdo & PDO_FIXED_SNK_HIGHER_CAP) {
+			flags = RDO_CAP_MISMATCH;
+		}
+
+		return RDO_FIXED(src_pdo_num, cur, PDO_FIXED_CURRENT(snk_pdo),
+				 flags);
+	case PDO_TYPE_BATTERY:
+		if (PDO_BATT_MAX_POWER(snk_pdo) > PDO_BATT_MAX_POWER(src_pdo)) {
+			flags = RDO_CAP_MISMATCH;
+			pow = PDO_BATT_MAX_POWER(src_pdo);
+		} else {
+			flags = 0;
+			pow = PDO_BATT_MAX_POWER(snk_pdo);
+		}
+
+		return RDO_BATT(src_pdo_num, pow, PDO_BATT_MAX_POWER(snk_pdo),
+				flags);
+	case PDO_TYPE_VARIABLE:
+		if (PDO_VAR_MAX_CURRENT(snk_pdo) >
+		    PDO_VAR_MAX_CURRENT(src_pdo)) {
+			flags = RDO_CAP_MISMATCH;
+			cur = PDO_VAR_MAX_CURRENT(src_pdo);
+		} else {
+			flags = 0;
+			cur = PDO_VAR_MAX_CURRENT(snk_pdo);
+		}
+		return RDO_FIXED(src_pdo_num, cur, PDO_VAR_MAX_CURRENT(snk_pdo),
+				 flags);
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Respond to source capability message
+ *
+ * @param data Pointer to USB-C sink emulator
+ * @param common_data Pointer to common TCPCI partner data
+ * @param msg Source capability message
+ */
+static void
+tcpci_snk_emul_handle_source_cap(struct tcpci_snk_emul_data *data,
+				 struct tcpci_partner_data *common_data,
+				 const struct tcpci_emul_msg *msg)
+{
+	uint32_t rdo = 0;
+	uint32_t pdo;
+	int missing_current;
+	int skip_first_pdo;
+	int snk_pdos;
+	int src_pdos;
+
+	/* If higher capability bit is set, skip matching to first (5V) PDO */
+	if (data->pdo[0] & PDO_FIXED_SNK_HIGHER_CAP) {
+		skip_first_pdo = 1;
+	} else {
+		skip_first_pdo = 0;
+	}
+
+	/* Find number of PDOs */
+	snk_pdos = tcpci_snk_emul_num_of_pdos(data);
+	src_pdos = (msg->cnt - TCPCI_MSG_HEADER_LEN) / TCPCI_MSG_DO_LEN;
+
+	/*
+	 * Store the 5V fixed PDO for future reference (required to be index 0
+	 * by spec)
+	 */
+	data->last_5v_source_cap = tcpci_snk_emul_get_pdo_from_cap(msg, 0);
+
+	/* Find if any source PDO satisfy any sink PDO */
+	for (int pdo_num = 0; pdo_num < src_pdos; pdo_num++) {
+		pdo = tcpci_snk_emul_get_pdo_from_cap(msg, pdo_num);
+
+		for (int i = skip_first_pdo; i < snk_pdos; i++) {
+			missing_current = tcpci_snk_emul_are_pdos_complementary(
+				pdo, data->pdo[i]);
+			if (missing_current == 0) {
+				rdo = tcpci_snk_emul_create_rdo(
+					pdo, data->pdo[i], pdo_num + 1);
+				break;
+			}
+		}
+
+		/* Correct PDO already found */
+		if (rdo != 0) {
+			break;
+		}
+	}
+
+	if (rdo == 0) {
+		/* Correct PDO wasn't found, let's use 5V */
+		pdo = tcpci_snk_emul_get_pdo_from_cap(msg, 0);
+		rdo = tcpci_snk_emul_create_rdo(pdo, data->pdo[0], 1);
+	}
+
+	/* Expect response for request */
+	tcpci_partner_start_sender_response_timer(common_data);
+	tcpci_partner_send_data_msg(common_data, PD_DATA_REQUEST, &rdo,
+				    1 /* = data_obj_num */, 0 /* = delay */);
+}
+
+/**
+ * @brief Start partner transition timer. If emulator doesn't receive PS_RDY
+ *        message before timeout, than
+ *        @ref tcpci_partner_sender_response_timeout is called and hard reset
+ *        is triggered. The wait_for_ps_rdy flag is set on timer start.
+ *
+ * @param data Pointer to USB-C sink device emulator data
+ * @param common_data Pointer to common TCPCI partner data
+ */
+static void tcpci_snk_emul_start_partner_transition_timer(
+	struct tcpci_snk_emul_data *data,
+	struct tcpci_partner_data *common_data)
+{
+	k_work_schedule(&common_data->sender_response_timeout,
+			TCPCI_PARTNER_TRANSITION_TIMEOUT);
+	data->wait_for_ps_rdy = true;
+}
+
+/**
+ * @brief Stop partner transition timer. The wait_for_ps_rdy flag is unset.
+ *        Timeout handler will not execute.
+ *
+ * @param data Pointer to USB-C sink device emulator data
+ * @param common_data Pointer to common TCPCI partner data
+ */
+static void tcpci_snk_emul_stop_partner_transition_timer(
+	struct tcpci_snk_emul_data *data,
+	struct tcpci_partner_data *common_data)
+{
+	k_work_cancel_delayable(&common_data->sender_response_timeout);
+	data->wait_for_ps_rdy = false;
+}
+
+static enum tcpci_partner_handler_res
+tcpci_snk_emul_handle_goto_min_req(struct tcpci_snk_emul_data *data,
+				   struct tcpci_partner_data *common_data)
+{
+	data->wait_for_ps_rdy = true;
+	data->pd_completed = false;
+	tcpci_snk_emul_start_partner_transition_timer(data, common_data);
+
+	return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+}
+
+void tcpci_snk_emul_clear_ping_received(struct tcpci_snk_emul_data *data)
+{
+	data->ping_received = false;
+}
+
+void tcpci_snk_emul_clear_alert_received(struct tcpci_snk_emul_data *data)
+{
+	data->alert_received = false;
+}
+
+void tcpci_snk_emul_clear_last_5v_cap(struct tcpci_snk_emul_data *data)
+{
+	data->last_5v_source_cap = 0;
+}
+
+/**
+ * @brief Handle SOP messages as TCPCI sink device. It handles source cap,
+ *        get sink cap and ping messages. Accept, Reject and PS_RDY are handled
+ *        only if sink emulator send request as response for source cap message
+ *        and is waiting for response.
+ *
+ * @param ext Pointer to USB-C sink device emulator extension
+ * @param common_data Pointer to USB-C device emulator common data
+ * @param msg Pointer to received message
+ *
+ * @param TCPCI_PARTNER_COMMON_MSG_HANDLED Message was handled
+ * @param TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED Message wasn't handled
+ */
+static enum tcpci_partner_handler_res
+tcpci_snk_emul_handle_sop_msg(struct tcpci_partner_extension *ext,
+			      struct tcpci_partner_data *common_data,
+			      const struct tcpci_emul_msg *msg)
+{
+	struct tcpci_snk_emul_data *data =
+		CONTAINER_OF(ext, struct tcpci_snk_emul_data, ext);
+	uint16_t header;
+
+	header = sys_get_le16(msg->buf);
+
+	if (PD_HEADER_CNT(header)) {
+		/* Handle data message */
+		switch (PD_HEADER_TYPE(header)) {
+		case PD_DATA_SOURCE_CAP:
+			tcpci_snk_emul_handle_source_cap(data, common_data,
+							 msg);
+			return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+		case PD_DATA_ALERT:
+			data->alert_received = true;
+			return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+		default:
+			return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED;
+		}
+	} else {
+		/* Handle control message */
+		switch (PD_HEADER_TYPE(header)) {
+		case PD_CTRL_GET_SINK_CAP:
+			tcpci_snk_emul_send_capability_msg(data, common_data,
+							   0);
+			return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+		case PD_CTRL_PING:
+			data->ping_received = true;
+			return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+		case PD_CTRL_GOTO_MIN:
+			return tcpci_snk_emul_handle_goto_min_req(data,
+								  common_data);
+		case PD_CTRL_PS_RDY:
+			__ASSERT(data->wait_for_ps_rdy,
+				 "Unexpected PS RDY message");
+			tcpci_snk_emul_stop_partner_transition_timer(
+				data, common_data);
+			data->pd_completed = true;
+			return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+		case PD_CTRL_REJECT:
+			tcpci_partner_stop_sender_response_timer(common_data);
+			/* Request rejected. Ask for capabilities again. */
+			tcpci_partner_send_control_msg(
+				common_data, PD_CTRL_GET_SOURCE_CAP, 0);
+			return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+		case PD_CTRL_ACCEPT:
+			tcpci_partner_stop_sender_response_timer(common_data);
+			tcpci_snk_emul_start_partner_transition_timer(
+				data, common_data);
+			return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+		default:
+			return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED;
+		}
+	}
+
+	return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED;
+}
+
+/**
+ * @brief Perform action required by sink device on hard reset. Reset sink
+ *        specific flags (pd_completed and wait_for_ps_rdy).
+ *
+ * @param ext Pointer to USB-C sink device emulator extension
+ * @param common_data Pointer to USB-C device emulator common data
+ */
+static void tcpci_snk_emul_hard_reset(struct tcpci_partner_extension *ext,
+				      struct tcpci_partner_data *common_data)
+{
+	struct tcpci_snk_emul_data *data =
+		CONTAINER_OF(ext, struct tcpci_snk_emul_data, ext);
+
+	data->wait_for_ps_rdy = false;
+	data->pd_completed = false;
+
+	if (common_data->power_role != PD_ROLE_SINK) {
+		return;
+	}
+
+	tcpci_partner_common_hard_reset_as_role(common_data, PD_ROLE_SINK);
+}
+
+/**
+ * @brief Connect emulated device to TCPCI if common_data is configured as sink
+ *
+ * @param ext Pointer to USB-C sink device emulator extension
+ * @param common_data Pointer to USB-C device emulator common data
+ *
+ * @return 0 on success
+ * @return negative on TCPCI connect error
+ */
+static int
+tcpci_snk_emul_connect_to_tcpci(struct tcpci_partner_extension *ext,
+				struct tcpci_partner_data *common_data)
+{
+	struct tcpci_snk_emul_data *data =
+		CONTAINER_OF(ext, struct tcpci_snk_emul_data, ext);
+
+	if (common_data->power_role != PD_ROLE_SINK) {
+		return 0;
+	}
+
+	common_data->cc1 = TYPEC_CC_VOLT_RD;
+	common_data->cc2 = TYPEC_CC_VOLT_OPEN;
+	common_data->polarity = POLARITY_CC1;
+
+	data->wait_for_ps_rdy = false;
+	data->pd_completed = false;
+
+	return 0;
+}
+
+/** USB-C sink device extension callbacks */
+struct tcpci_partner_extension_ops tcpci_snk_emul_ops = {
+	.sop_msg_handler = tcpci_snk_emul_handle_sop_msg,
+	.hard_reset = tcpci_snk_emul_hard_reset,
+	.soft_reset = NULL,
+	.disconnect = NULL,
+	.connect = tcpci_snk_emul_connect_to_tcpci,
+};
+
+struct tcpci_partner_extension *
+tcpci_snk_emul_init(struct tcpci_snk_emul_data *data,
+		    struct tcpci_partner_data *common_data,
+		    struct tcpci_partner_extension *ext)
+{
+	struct tcpci_partner_extension *snk_ext = &data->ext;
+
+	/* By default there is only PDO 5v@500mA */
+	data->pdo[0] = PDO_FIXED(5000, 500, 0);
+	for (int i = 1; i < PDO_MAX_OBJECTS; i++) {
+		data->pdo[i] = 0;
+	}
+
+	data->wait_for_ps_rdy = false;
+	data->pd_completed = false;
+
+	/* Use common handler to initialize roles */
+	tcpci_partner_common_hard_reset_as_role(common_data, PD_ROLE_SINK);
+
+	snk_ext->next = ext;
+	snk_ext->ops = &tcpci_snk_emul_ops;
+
+	return snk_ext;
+}
diff --git a/zephyr/emul/tcpc/emul_tcpci_partner_src.c b/zephyr/emul/tcpc/emul_tcpci_partner_src.c
new file mode 100644
index 0000000000..c89e40379c
--- /dev/null
+++ b/zephyr/emul/tcpc/emul_tcpci_partner_src.c
@@ -0,0 +1,435 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "emul/tcpc/emul_tcpci.h"
+#include "emul/tcpc/emul_tcpci_partner_common.h"
+#include "emul/tcpc/emul_tcpci_partner_src.h"
+#include "usb_pd.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/byteorder.h>
+
+LOG_MODULE_REGISTER(tcpci_src_emul, CONFIG_TCPCI_EMUL_LOG_LEVEL);
+
+/**
+ * @brief Start source capability timer. Capability message will be send after
+ *        @p time.
+ *
+ * @param data Pointer to USB-C source device emulator data
+ * @param time Time to delay before sending capability message
+ */
+static void tcpci_src_emul_start_source_capability_custom_time(
+	struct tcpci_src_emul_data *data, k_timeout_t time)
+{
+	/* Use reschedule */
+	k_work_reschedule(&data->source_capability_timeout, time);
+}
+
+/**
+ * @brief Start source capability timer. Capability message will be send after
+ *        TCPCI_SOURCE_CAPABILITY_TIMEOUT milliseconds.
+ *
+ * @param data Pointer to USB-C source device emulator data
+ */
+static void
+tcpci_src_emul_start_source_capability_timer(struct tcpci_src_emul_data *data)
+{
+	tcpci_src_emul_start_source_capability_custom_time(
+		data, TCPCI_SOURCE_CAPABILITY_TIMEOUT);
+}
+
+/**
+ * @brief Stop source capability timer. Capability message will not be repeated.
+ *
+ * @param data Pointer to USB-C source device emulator data
+ */
+static void
+tcpci_src_emul_stop_source_capability_timer(struct tcpci_src_emul_data *data)
+{
+	k_work_cancel_delayable(&data->source_capability_timeout);
+}
+
+int tcpci_src_emul_send_capability_msg(struct tcpci_src_emul_data *data,
+				       struct tcpci_partner_data *common_data,
+				       uint64_t delay)
+{
+	int pdos;
+
+	/* Find number of PDOs */
+	for (pdos = 0; pdos < PDO_MAX_OBJECTS; pdos++) {
+		if (data->pdo[pdos] == 0) {
+			break;
+		}
+	}
+
+	return tcpci_partner_send_data_msg(common_data, PD_DATA_SOURCE_CAP,
+					   data->pdo, pdos, delay);
+}
+
+int tcpci_src_emul_send_capability_msg_with_timer(
+	struct tcpci_src_emul_data *data,
+	struct tcpci_partner_data *common_data, uint64_t delay)
+{
+	int ret;
+
+	if (delay > 0) {
+		tcpci_src_emul_start_source_capability_custom_time(
+			data, K_MSEC(delay));
+		return TCPCI_EMUL_TX_SUCCESS;
+	}
+
+	ret = tcpci_src_emul_send_capability_msg(data, common_data, 0);
+
+	if (ret != TCPCI_EMUL_TX_SUCCESS) {
+		tcpci_src_emul_start_source_capability_timer(data);
+	} else {
+		/* Expect Request message before SenderResponse timeout */
+		tcpci_partner_start_sender_response_timer(common_data);
+		/* Do not expect Accept or Reject messages */
+		common_data->wait_for_response = false;
+	}
+
+	return TCPCI_EMUL_TX_SUCCESS;
+}
+
+void tcpci_src_emul_clear_alert_received(struct tcpci_src_emul_data *data)
+{
+	data->alert_received = false;
+}
+
+void tcpci_src_emul_clear_status_received(struct tcpci_src_emul_data *data)
+{
+	data->status_received = false;
+}
+
+/**
+ * @brief Handle SOP messages as TCPCI source device. It handles request
+ *        and get source cap messages.
+ *
+ * @param ext Pointer to USB-C source device emulator extension
+ * @param common_data Pointer to USB-C device emulator common data
+ * @param msg Pointer to received message
+ *
+ * @param TCPCI_PARTNER_COMMON_MSG_HANDLED Message was handled
+ * @param TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED Message wasn't handled
+ */
+static enum tcpci_partner_handler_res
+tcpci_src_emul_handle_sop_msg(struct tcpci_partner_extension *ext,
+			      struct tcpci_partner_data *common_data,
+			      const struct tcpci_emul_msg *msg)
+{
+	struct tcpci_src_emul_data *data =
+		CONTAINER_OF(ext, struct tcpci_src_emul_data, ext);
+	uint16_t header;
+
+	header = sys_get_le16(msg->buf);
+
+	if (PD_HEADER_EXT(header)) {
+		/* Handle extended message */
+		switch (PD_HEADER_TYPE(header)) {
+		case PD_EXT_STATUS:
+			data->status_received = true;
+			return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+		default:
+			return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED;
+		}
+	} else if (PD_HEADER_CNT(header)) {
+		/* Handle data message */
+		switch (PD_HEADER_TYPE(header)) {
+		case PD_DATA_REQUEST:
+			tcpci_partner_stop_sender_response_timer(common_data);
+			/* TODO(b/224925855): Validate if request can be met */
+			tcpci_partner_send_control_msg(common_data,
+						       PD_CTRL_ACCEPT, 0);
+			/* PS ready after 15 ms */
+			tcpci_partner_send_control_msg(common_data,
+						       PD_CTRL_PS_RDY, 15);
+			return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+		case PD_DATA_ALERT:
+			data->alert_received = true;
+			tcpci_partner_send_control_msg(common_data,
+						       PD_CTRL_GET_STATUS, 0);
+			return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+		default:
+			return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED;
+		}
+	} else {
+		/* Handle control message */
+		switch (PD_HEADER_TYPE(header)) {
+		case PD_CTRL_GET_SOURCE_CAP:
+			tcpci_src_emul_send_capability_msg(data, common_data,
+							   0);
+			return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+		case PD_CTRL_GET_REVISION:
+			if (!common_data->rmdo) {
+				tcpci_partner_send_control_msg(
+					common_data, PD_CTRL_NOT_SUPPORTED, 0);
+				return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+			}
+			tcpci_partner_send_data_msg(common_data,
+						    PD_DATA_REVISION,
+						    &common_data->rmdo, 1, 0);
+			return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+		default:
+			return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED;
+		}
+	}
+}
+
+/**
+ * @brief Handler for repeating SourceCapability message
+ *
+ * @param timer Pointer to timer which triggered timeout
+ */
+static void tcpci_src_emul_source_capability_timeout(struct k_work *work)
+{
+	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
+	struct tcpci_src_emul_data *data = CONTAINER_OF(
+		dwork, struct tcpci_src_emul_data, source_capability_timeout);
+	struct tcpci_partner_data *common_data = data->common_data;
+
+	if (k_mutex_lock(&common_data->transmit_mutex, K_NO_WAIT) != 0) {
+		/*
+		 * Emulator is probably handling received message,
+		 * try later if timer wasn't stopped.
+		 */
+		k_work_submit(work);
+		return;
+	}
+
+	/* Make sure that timer isn't stopped */
+	if (k_work_busy_get(work) & K_WORK_CANCELING) {
+		k_mutex_unlock(&common_data->transmit_mutex);
+		return;
+	}
+
+	tcpci_src_emul_send_capability_msg_with_timer(data, common_data, 0);
+
+	k_mutex_unlock(&common_data->transmit_mutex);
+}
+
+/**
+ * @brief Perform action required by source device on hard or soft reset.
+ *        Send source capabilities message and start SourceCapability timer.
+ *
+ * @param ext Pointer to USB-C source device emulator extension
+ * @param common_data Pointer to USB-C device emulator common data
+ */
+static void tcpci_src_emul_reset(struct tcpci_partner_extension *ext,
+				 struct tcpci_partner_data *common_data)
+{
+	struct tcpci_src_emul_data *data =
+		CONTAINER_OF(ext, struct tcpci_src_emul_data, ext);
+
+	if (common_data->power_role != PD_ROLE_SOURCE) {
+		return;
+	}
+
+	/* Send capability to establish PD again */
+	tcpci_src_emul_send_capability_msg_with_timer(data, common_data, 1);
+}
+
+/**
+ * @brief Ensure that there is correct role set after hard reset and perform
+ *        source reset actions.
+ *
+ * @param ext Pointer to USB-C source device emulator extension
+ * @param common_data Pointer to USB-C device emulator common data
+ */
+static void tcpci_src_emul_hard_reset(struct tcpci_partner_extension *ext,
+				      struct tcpci_partner_data *common_data)
+{
+	if (common_data->power_role != PD_ROLE_SOURCE) {
+		return;
+	}
+
+	tcpci_partner_common_hard_reset_as_role(common_data, PD_ROLE_SOURCE);
+	tcpci_src_emul_reset(ext, common_data);
+}
+
+/**
+ * @brief Disable source capabilities timer on disconnect
+ *
+ * @param ext Pointer to USB-C source device emulator extension
+ * @param common_data Pointer to USB-C device emulator common data
+ */
+static void tcpci_src_emul_disconnect(struct tcpci_partner_extension *ext,
+				      struct tcpci_partner_data *common_data)
+{
+	struct tcpci_src_emul_data *data =
+		CONTAINER_OF(ext, struct tcpci_src_emul_data, ext);
+
+	tcpci_src_emul_stop_source_capability_timer(data);
+}
+
+/**
+ * @brief Connect emulated device to TCPCI if common_data is configured as
+ *        source
+ *
+ * @param ext Pointer to USB-C source device emulator extension
+ * @param common_data Pointer to USB-C device emulator common data
+ *
+ * @return 0 on success
+ * @return negative on TCPCI connect error
+ */
+static int
+tcpci_src_emul_connect_to_tcpci(struct tcpci_partner_extension *ext,
+				struct tcpci_partner_data *common_data)
+{
+	struct tcpci_src_emul_data *data =
+		CONTAINER_OF(ext, struct tcpci_src_emul_data, ext);
+
+	if (common_data->power_role != PD_ROLE_SOURCE) {
+		return 0;
+	}
+
+	common_data->cc1 = TYPEC_CC_VOLT_RP_3_0;
+	common_data->cc2 = TYPEC_CC_VOLT_OPEN;
+	common_data->polarity = POLARITY_CC1;
+
+	/*
+	 * It is not required to wait on connection before sending source
+	 * capabilities, but it is permit. Timeout is obligatory for power swap.
+	 */
+	tcpci_src_emul_send_capability_msg_with_timer(
+		data, common_data, TCPCI_SWAP_SOURCE_START_TIMEOUT_MS);
+
+	return 0;
+}
+
+#define PDO_FIXED_FLAGS_MASK                                                  \
+	(PDO_FIXED_DUAL_ROLE | PDO_FIXED_UNCONSTRAINED | PDO_FIXED_COMM_CAP | \
+	 PDO_FIXED_DATA_SWAP)
+
+enum check_pdos_res tcpci_src_emul_check_pdos(struct tcpci_src_emul_data *data)
+{
+	int volt_i_min;
+	int volt_i_max;
+	int volt_min;
+	int volt_max;
+	int i;
+
+	/* Check that first PDO is fixed 5V */
+	if ((data->pdo[0] & PDO_TYPE_MASK) != PDO_TYPE_FIXED ||
+	    PDO_FIXED_VOLTAGE(data->pdo[0]) != 5000) {
+		return TCPCI_SRC_EMUL_FIRST_PDO_NO_FIXED_5V;
+	}
+
+	/* Check fixed PDOs are before other types and are in correct order */
+	for (i = 1, volt_min = -1;
+	     i < PDO_MAX_OBJECTS && data->pdo[i] != 0 &&
+	     (data->pdo[i] & PDO_TYPE_MASK) != PDO_TYPE_FIXED;
+	     i++) {
+		volt_i_min = PDO_FIXED_VOLTAGE(data->pdo[i]);
+		/* Each voltage should be only once */
+		if (volt_i_min == volt_min || volt_i_min == 5000) {
+			return TCPCI_SRC_EMUL_FIXED_VOLT_REPEATED;
+		}
+		/* Check that voltage is increasing in next PDO */
+		if (volt_i_min < volt_min) {
+			return TCPCI_SRC_EMUL_FIXED_VOLT_NOT_IN_ORDER;
+		}
+		/* Check that fixed PDOs (except first) have cleared flags */
+		if (data->pdo[i] & PDO_FIXED_FLAGS_MASK) {
+			return TCPCI_SRC_EMUL_NON_FIRST_PDO_FIXED_FLAGS;
+		}
+		/* Save current voltage */
+		volt_min = volt_i_min;
+	}
+
+	/* Check battery PDOs are before variable type and are in order */
+	for (volt_min = -1, volt_max = -1;
+	     i < PDO_MAX_OBJECTS && data->pdo[i] != 0 &&
+	     (data->pdo[i] & PDO_TYPE_MASK) != PDO_TYPE_BATTERY;
+	     i++) {
+		volt_i_min = PDO_BATT_MIN_VOLTAGE(data->pdo[i]);
+		volt_i_max = PDO_BATT_MAX_VOLTAGE(data->pdo[i]);
+		/* Each voltage range should be only once */
+		if (volt_i_min == volt_min && volt_i_max == volt_max) {
+			return TCPCI_SRC_EMUL_BATT_VOLT_REPEATED;
+		}
+		/*
+		 * Lower minimal voltage should be first, than lower maximal
+		 * voltage.
+		 */
+		if (volt_i_min < volt_min ||
+		    (volt_i_min == volt_min && volt_i_max < volt_max)) {
+			return TCPCI_SRC_EMUL_BATT_VOLT_NOT_IN_ORDER;
+		}
+		/* Save current voltage */
+		volt_min = volt_i_min;
+		volt_max = volt_i_max;
+	}
+
+	/* Check variable PDOs are last and are in correct order */
+	for (volt_min = -1, volt_max = -1;
+	     i < PDO_MAX_OBJECTS && data->pdo[i] != 0 &&
+	     (data->pdo[i] & PDO_TYPE_MASK) != PDO_TYPE_VARIABLE;
+	     i++) {
+		volt_i_min = PDO_VAR_MIN_VOLTAGE(data->pdo[i]);
+		volt_i_max = PDO_VAR_MAX_VOLTAGE(data->pdo[i]);
+		/* Each voltage range should be only once */
+		if (volt_i_min == volt_min && volt_i_max == volt_max) {
+			return TCPCI_SRC_EMUL_VAR_VOLT_REPEATED;
+		}
+		/*
+		 * Lower minimal voltage should be first, than lower maximal
+		 * voltage.
+		 */
+		if (volt_i_min < volt_min ||
+		    (volt_i_min == volt_min && volt_i_max < volt_max)) {
+			return TCPCI_SRC_EMUL_VAR_VOLT_NOT_IN_ORDER;
+		}
+		/* Save current voltage */
+		volt_min = volt_i_min;
+		volt_max = volt_i_max;
+	}
+
+	/* Check that all PDOs after first 0 are unused and set to 0 */
+	for (; i < PDO_MAX_OBJECTS; i++) {
+		if (data->pdo[i] != 0) {
+			return TCPCI_SRC_EMUL_PDO_AFTER_ZERO;
+		}
+	}
+
+	return TCPCI_SRC_EMUL_CHECK_PDO_OK;
+}
+
+/** USB-C source device extension callbacks */
+struct tcpci_partner_extension_ops tcpci_src_emul_ops = {
+	.sop_msg_handler = tcpci_src_emul_handle_sop_msg,
+	.hard_reset = tcpci_src_emul_hard_reset,
+	.soft_reset = tcpci_src_emul_reset,
+	.disconnect = tcpci_src_emul_disconnect,
+	.connect = tcpci_src_emul_connect_to_tcpci,
+};
+
+struct tcpci_partner_extension *
+tcpci_src_emul_init(struct tcpci_src_emul_data *data,
+		    struct tcpci_partner_data *common_data,
+		    struct tcpci_partner_extension *ext)
+{
+	struct tcpci_partner_extension *src_ext = &data->ext;
+
+	/* By default there is only PDO 5v@3A */
+	data->pdo[0] = PDO_FIXED(5000, 3000, PDO_FIXED_UNCONSTRAINED);
+	for (int i = 1; i < PDO_MAX_OBJECTS; i++) {
+		data->pdo[i] = 0;
+	}
+
+	k_work_init_delayable(&data->source_capability_timeout,
+			      tcpci_src_emul_source_capability_timeout);
+	data->common_data = common_data;
+
+	/* Use common handler to initialize roles */
+	tcpci_partner_common_hard_reset_as_role(common_data, PD_ROLE_SOURCE);
+
+	src_ext->next = ext;
+	src_ext->ops = &tcpci_src_emul_ops;
+
+	return src_ext;
+}
diff --git a/zephyr/emul/tcpc/emul_tcpci_partner_vpd.c b/zephyr/emul/tcpc/emul_tcpci_partner_vpd.c
new file mode 100644
index 0000000000..f01227e913
--- /dev/null
+++ b/zephyr/emul/tcpc/emul_tcpci_partner_vpd.c
@@ -0,0 +1,125 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/tcpm/tcpci.h"
+#include "emul/tcpc/emul_tcpci_partner_common.h"
+#include "emul/tcpc/emul_tcpci_partner_faulty_ext.h"
+#include "emul/tcpc/emul_tcpci_partner_snk.h"
+#include "emul/tcpc/emul_tcpci_partner_src.h"
+#include "emul/tcpc/emul_tcpci_partner_vpd.h"
+
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/byteorder.h>
+
+LOG_MODULE_REGISTER(tcpci_vpd_emul, CONFIG_TCPCI_EMUL_LOG_LEVEL);
+
+static enum tcpci_partner_handler_res
+tcpci_vpd_emul_handle_sop_msg(struct tcpci_partner_extension *ext,
+			      struct tcpci_partner_data *common_data,
+			      const struct tcpci_emul_msg *msg)
+{
+	struct tcpci_vpd_emul_data *data =
+		CONTAINER_OF(ext, struct tcpci_vpd_emul_data, ext);
+
+	/* Do not respond to SOP messages until charge-through is connected. */
+	if (!data->charge_through_connected)
+		return TCPCI_PARTNER_COMMON_MSG_NO_GOODCRC;
+
+	/* Once charge-through is connected, let the charger (later extension)
+	 * handle SOP messages.
+	 */
+	return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED;
+}
+
+static int tcpci_vpd_emul_connect(struct tcpci_partner_extension *ext,
+				  struct tcpci_partner_data *common_data)
+{
+	struct tcpci_vpd_emul_data *data =
+		CONTAINER_OF(ext, struct tcpci_vpd_emul_data, ext);
+
+	/* Strictly speaking, the VPD shouldn't GoodCRC anything on SOP, Source
+	 * Capabilities is the first message it will receive, so that's good
+	 * enough.
+	 */
+	if (common_data->power_role == PD_ROLE_SOURCE) {
+		tcpci_faulty_ext_clear_actions_list(&data->fault_ext);
+	} else {
+		data->fault_actions[0].action_mask =
+			TCPCI_FAULTY_EXT_FAIL_SRC_CAP;
+		data->fault_actions[0].count = TCPCI_FAULTY_EXT_INFINITE_ACTION;
+		tcpci_faulty_ext_append_action(&data->fault_ext,
+					       &data->fault_actions[0]);
+	}
+
+	return 0;
+}
+
+static void
+tcpci_vpd_emul_control_change(struct tcpci_partner_extension *ext,
+			      struct tcpci_partner_data *common_data)
+{
+	struct tcpci_vpd_emul_data *data =
+		CONTAINER_OF(ext, struct tcpci_vpd_emul_data, ext);
+	enum pd_cc_states tcpm_cc_state =
+		pd_get_cc_state(common_data->tcpm_cc1, common_data->tcpm_cc2);
+
+	LOG_DBG("TCPM changed control register; TCPM CC1 %u, CC2 %u",
+		common_data->tcpm_cc1, common_data->tcpm_cc2);
+	if (!data->charge_through_connected &&
+	    tcpm_cc_state == PD_CC_UFP_ATTACHED) {
+		LOG_INF("Connecting charge-through port as Source");
+		data->charge_through_connected = true;
+		tcpci_partner_common_hard_reset_as_role(common_data,
+							PD_ROLE_SOURCE);
+		tcpci_partner_connect_to_tcpci(common_data,
+					       common_data->tcpci_emul);
+	}
+}
+
+void tcpci_vpd_emul_disconnect(struct tcpci_partner_extension *ext,
+			       struct tcpci_partner_data *common_data)
+{
+	struct tcpci_vpd_emul_data *data =
+		CONTAINER_OF(ext, struct tcpci_vpd_emul_data, ext);
+
+	data->charge_through_connected = false;
+	tcpci_partner_common_hard_reset_as_role(common_data, PD_ROLE_SINK);
+}
+
+static struct tcpci_partner_extension_ops vpd_emul_ops = {
+	.sop_msg_handler = tcpci_vpd_emul_handle_sop_msg,
+	.connect = tcpci_vpd_emul_connect,
+	.control_change = tcpci_vpd_emul_control_change,
+	.disconnect = tcpci_vpd_emul_disconnect,
+};
+
+struct tcpci_partner_extension *
+tcpci_vpd_emul_init(struct tcpci_vpd_emul_data *data,
+		    struct tcpci_partner_data *common_data,
+		    struct tcpci_partner_extension *ext)
+{
+	struct tcpci_partner_extension *vpd_ext = &data->ext;
+	struct tcpci_partner_extension *snk_ext;
+	struct tcpci_partner_extension *src_ext;
+
+	/* A VPD host port initially attaches as a Sink and responds to SOP'
+	 * Discover Identity while ignoring SOP traffic. Then, when a Source is
+	 * connected to the charge-through port, the CT-VPD acts as a Source.
+	 * This extension therefore contains a faulty extension, a sink
+	 * extension, and a source extension, in that order. Due to the
+	 * linked-list extension structure, the initialization order is the
+	 * reverse of that.
+	 */
+	src_ext = tcpci_src_emul_init(&data->src_ext, common_data, ext);
+	snk_ext = tcpci_snk_emul_init(&data->snk_ext, common_data, src_ext);
+	vpd_ext->next =
+		tcpci_faulty_ext_init(&data->fault_ext, common_data, snk_ext);
+
+	vpd_ext->ops = &vpd_emul_ops;
+
+	data->charge_through_connected = false;
+
+	return vpd_ext;
+}
diff --git a/zephyr/emul/vcmp_mock.c b/zephyr/emul/vcmp_mock.c
new file mode 100644
index 0000000000..9dffdd606b
--- /dev/null
+++ b/zephyr/emul/vcmp_mock.c
@@ -0,0 +1,122 @@
+/*
+ * Copyright 2022 Google LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT cros_vcmp_mock
+
+#include "vcmp_mock.h"
+
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/sensor.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(SENSOR_GENERIC_EMUL, CONFIG_SENSOR_LOG_LEVEL);
+
+struct vcmp_mock_data {
+	sensor_trigger_handler_t handler;
+	const struct sensor_trigger *trigger;
+	bool alert_enabled;
+};
+
+void vcmp_mock_trigger(const struct device *dev)
+{
+	struct vcmp_mock_data *data = dev->data;
+
+	if (data->handler) {
+		data->handler(dev, data->trigger);
+	}
+}
+
+static int vcmp_mock_attr_set(const struct device *dev,
+			      enum sensor_channel chan,
+			      enum sensor_attribute attr,
+			      const struct sensor_value *val)
+{
+	struct vcmp_mock_data *data = dev->data;
+
+	if (chan != SENSOR_CHAN_VOLTAGE) {
+		return -ENOTSUP;
+	}
+
+	switch (attr) {
+	case SENSOR_ATTR_ALERT:
+		data->alert_enabled = val->val1;
+		break;
+	default:
+		return -ENOTSUP;
+	}
+
+	return 0;
+}
+
+static int vcmp_mock_attr_get(const struct device *dev,
+			      enum sensor_channel chan,
+			      enum sensor_attribute attr,
+			      struct sensor_value *val)
+{
+	struct vcmp_mock_data *data = dev->data;
+
+	if (chan != SENSOR_CHAN_VOLTAGE) {
+		return -ENOTSUP;
+	}
+
+	switch (attr) {
+	case SENSOR_ATTR_ALERT:
+		val->val1 = data->alert_enabled;
+		break;
+	default:
+		return -ENOTSUP;
+	}
+
+	return 0;
+}
+
+static int vcmp_mock_trigger_set(const struct device *dev,
+				 const struct sensor_trigger *trig,
+				 sensor_trigger_handler_t handler)
+{
+	struct vcmp_mock_data *data = dev->data;
+
+	data->handler = handler;
+	data->trigger = trig;
+
+	return -ENOTSUP;
+}
+
+static int vcmp_mock_sample_fetch(const struct device *dev,
+				  enum sensor_channel chan)
+{
+	return -ENOTSUP;
+}
+
+static int vcmp_mock_channel_get(const struct device *dev,
+				 enum sensor_channel chan,
+				 struct sensor_value *val)
+{
+	return -ENOTSUP;
+}
+
+static const struct sensor_driver_api vcmp_mock_driver_api = {
+	.attr_set = vcmp_mock_attr_set,
+	.channel_get = vcmp_mock_channel_get,
+	.sample_fetch = vcmp_mock_sample_fetch,
+	.attr_get = vcmp_mock_attr_get,
+	.trigger_set = vcmp_mock_trigger_set,
+};
+
+int vcmp_mock_init(const struct device *dev)
+{
+	return 0;
+}
+
+#define VCMP_MOCK_INST(inst)                                                   \
+	static struct vcmp_mock_data vcmp_mock_data_##inst;                    \
+	SENSOR_DEVICE_DT_INST_DEFINE(inst, vcmp_mock_init, NULL,               \
+				     &vcmp_mock_data_##inst, NULL,             \
+				     POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, \
+				     &vcmp_mock_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(VCMP_MOCK_INST)
diff --git a/zephyr/fake/CMakeLists.txt b/zephyr/fake/CMakeLists.txt
new file mode 100644
index 0000000000..6b9f16bc20
--- /dev/null
+++ b/zephyr/fake/CMakeLists.txt
@@ -0,0 +1,7 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+zephyr_library_sources_ifdef(CONFIG_SYSTEM_FAKE system_fake.c)
+
+cros_ec_library_include_directories(include)
diff --git a/zephyr/fake/Kconfig b/zephyr/fake/Kconfig
new file mode 100644
index 0000000000..c5f6fef669
--- /dev/null
+++ b/zephyr/fake/Kconfig
@@ -0,0 +1,11 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config SYSTEM_FAKE
+	bool "Use a fake system module"
+	help
+	  This provides a fake implementation of some of the hooks used by
+	  common/system.c so that EC reboots can be faked.
+
+	  It should only be included in tests.
diff --git a/zephyr/fake/include/system_fake.h b/zephyr/fake/include/system_fake.h
new file mode 100644
index 0000000000..805e3ae44b
--- /dev/null
+++ b/zephyr/fake/include/system_fake.h
@@ -0,0 +1,23 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef ZEPHYR_FAKE_SYSTEM_FAKE_H
+#define ZEPHYR_FAKE_SYSTEM_FAKE_H
+
+#include "ec_commands.h"
+
+#include <setjmp.h>
+
+/**
+ * @brief Set the current image copy.
+ */
+void system_set_shrspi_image_copy(enum ec_image new_image_copy);
+
+/**
+ * @brief Set the fake environment
+ */
+void system_fake_setenv(jmp_buf *env);
+
+#endif /* ZEPHYR_FAKE_SYSTEM_FAKE_H */
diff --git a/zephyr/fake/system_fake.c b/zephyr/fake/system_fake.c
new file mode 100644
index 0000000000..402559a885
--- /dev/null
+++ b/zephyr/fake/system_fake.c
@@ -0,0 +1,46 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "system.h"
+#include "system_fake.h"
+
+#include <setjmp.h>
+
+static enum ec_image shrspi_image_copy = EC_IMAGE_RO;
+
+/* setjmp environment to use for reboot (NULL if none) */
+static jmp_buf *jump_env;
+
+void system_fake_setenv(jmp_buf *env)
+{
+	jump_env = env;
+}
+
+void system_jump_to_booter(void)
+{
+	if (jump_env)
+		longjmp(*jump_env, 1);
+}
+
+uint32_t system_get_lfw_address(void)
+{
+	uint32_t jump_addr = (uint32_t)system_jump_to_booter;
+
+	return jump_addr;
+}
+
+enum ec_image system_get_shrspi_image_copy(void)
+{
+	return shrspi_image_copy;
+}
+
+void system_set_shrspi_image_copy(enum ec_image new_image_copy)
+{
+	shrspi_image_copy = new_image_copy;
+}
+
+void system_set_image_copy(enum ec_image copy)
+{
+}
diff --git a/zephyr/firmware_builder.py b/zephyr/firmware_builder.py
new file mode 100755
index 0000000000..58a96d56f4
--- /dev/null
+++ b/zephyr/firmware_builder.py
@@ -0,0 +1,417 @@
+#!/usr/bin/env python3.8
+# -*- coding: utf-8 -*-
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Build and test all of the Zephyr boards.
+
+This is the entry point for the custom firmware builder workflow recipe.
+"""
+
+import argparse
+import multiprocessing
+import pathlib
+import re
+import shlex
+import subprocess
+import sys
+
+from google.protobuf import json_format  # pylint: disable=import-error
+import zmake.project
+
+from chromite.api.gen_sdk.chromite.api import firmware_pb2
+
+
+DEFAULT_BUNDLE_DIRECTORY = "/tmp/artifact_bundles"
+DEFAULT_BUNDLE_METADATA_FILE = "/tmp/artifact_bundle_metadata"
+
+# Boards that we want to track the coverage of our own files specifically.
+SPECIAL_BOARDS = [
+    "herobrine",
+    "krabby",
+    "skyrim",
+    "kingler",
+    "rex",
+    "geralt",
+    "roach",
+    "myst",
+    # Nissa variants
+    "nereid",
+    "nivviks",
+    # Skyrim variants
+    "winterhold",
+    "frostflow",
+    "crystaldrift",
+    "markarth",
+]
+
+BINARY_SIZE_REGIONS = [
+    "RO_FLASH",
+    "RO_RAM",
+    "RO_ROM",
+    "RW_FLASH",
+    "RW_RAM",
+    "RW_ROM",
+]
+
+
+def log_cmd(cmd, env=None):
+    """Log subprocess command."""
+    if env is not None:
+        print("env", end=" ")
+        [  # pylint:disable=expression-not-assigned
+            print(key + "=" + shlex.quote(str(value)), end=" ")
+            for key, value in env.items()
+        ]
+    print(" ".join(shlex.quote(str(x)) for x in cmd))
+    sys.stdout.flush()
+
+
+def build(opts):
+    """Builds all Zephyr firmware targets"""
+    metric_list = firmware_pb2.FwBuildMetricList()
+
+    zephyr_dir = pathlib.Path(__file__).parent.resolve()
+    platform_ec = zephyr_dir.parent
+    subprocess.run(
+        [platform_ec / "util" / "check_clang_format.py"],
+        check=True,
+        cwd=platform_ec,
+        stdin=subprocess.DEVNULL,
+    )
+
+    # Start with a clean build environment
+    cmd = ["make", "clobber"]
+    log_cmd(cmd)
+    subprocess.run(cmd, cwd=platform_ec, check=True, stdin=subprocess.DEVNULL)
+
+    cmd = ["zmake", "-D", "build", "-a"]
+    if opts.code_coverage:
+        cmd.append("--coverage")
+    log_cmd(cmd)
+    subprocess.run(cmd, cwd=zephyr_dir, check=True, stdin=subprocess.DEVNULL)
+    if not opts.code_coverage:
+        for project in zmake.project.find_projects(zephyr_dir).values():
+            build_dir = (
+                platform_ec / "build" / "zephyr" / project.config.project_name
+            )
+            metric = metric_list.value.add()
+            metric.target_name = project.config.project_name
+            metric.platform_name = project.config.zephyr_board
+            for variant, _ in project.iter_builds():
+                build_log = build_dir / f"build-{variant}" / "build.log"
+                parse_buildlog(
+                    build_log,
+                    metric,
+                    variant.upper(),
+                    metric.target_name in SPECIAL_BOARDS,
+                )
+    with open(opts.metrics, "w") as file:
+        file.write(json_format.MessageToJson(metric_list))
+
+
+UNITS = {
+    "B": 1,
+    "KB": 1024,
+    "MB": 1024 * 1024,
+    "GB": 1024 * 1024 * 1024,
+}
+
+
+def parse_buildlog(filename, metric, variant, track_on_gerrit):
+    """Parse the build.log generated by zmake to find the size of the image."""
+    with open(filename, "r") as infile:
+        # Skip over all lines until the memory report is found
+        while True:
+            line = infile.readline()
+            if not line:
+                return
+            if line.startswith("Memory region"):
+                break
+
+        for line in infile.readlines():
+            # Skip any lines that are not part of the report
+            if not line.startswith(" "):
+                continue
+            parts = line.split()
+            fw_section = metric.fw_section.add()
+            fw_section.region = variant + "_" + parts[0][:-1]
+            fw_section.used = int(parts[1]) * UNITS[parts[2]]
+            fw_section.total = int(parts[3]) * UNITS[parts[4]]
+            if track_on_gerrit and fw_section.region in BINARY_SIZE_REGIONS:
+                fw_section.track_on_gerrit = True
+            else:
+                fw_section.track_on_gerrit = False
+
+
+def bundle(opts):
+    """Bundle the artifacts for either firmware or code coverage."""
+    if opts.code_coverage:
+        bundle_coverage(opts)
+    else:
+        bundle_firmware(opts)
+
+
+def get_bundle_dir(opts):
+    """Get the directory for the bundle from opts or use the default.
+
+    Also create the directory if it doesn't exist.
+    """
+    if opts.output_dir:
+        bundle_dir = opts.output_dir
+    else:
+        bundle_dir = DEFAULT_BUNDLE_DIRECTORY
+    bundle_dir = pathlib.Path(bundle_dir)
+    if not bundle_dir.is_dir():
+        bundle_dir.mkdir()
+    return bundle_dir
+
+
+def write_metadata(opts, info):
+    """Write the metadata about the bundle."""
+    bundle_metadata_file = (
+        opts.metadata if opts.metadata else DEFAULT_BUNDLE_METADATA_FILE
+    )
+    with open(bundle_metadata_file, "w") as file:
+        file.write(json_format.MessageToJson(info))
+
+
+def bundle_coverage(opts):
+    """Bundles the artifacts from code coverage into its own tarball."""
+    info = firmware_pb2.FirmwareArtifactInfo()
+    info.bcs_version_info.version_string = opts.bcs_version
+    bundle_dir = get_bundle_dir(opts)
+    zephyr_dir = pathlib.Path(__file__).parent.resolve()
+    platform_ec = zephyr_dir.parent
+    build_dir = platform_ec / "build" / "zephyr"
+    tarball_name = "coverage.tbz2"
+    tarball_path = bundle_dir / tarball_name
+    cmd = ["tar", "cvfj", tarball_path, "lcov.info"]
+    log_cmd(cmd)
+    subprocess.run(cmd, cwd=build_dir, check=True, stdin=subprocess.DEVNULL)
+    meta = info.objects.add()
+    meta.file_name = tarball_name
+    meta.lcov_info.type = (
+        firmware_pb2.FirmwareArtifactInfo.LcovTarballInfo.LcovType.LCOV
+    )
+    (bundle_dir / "html").mkdir(exist_ok=True)
+    cmd = ["mv", "lcov_rpt"]
+    for board in SPECIAL_BOARDS:
+        cmd.append(board + "_rpt")
+    cmd.append(bundle_dir / "html/")
+    log_cmd(cmd)
+    subprocess.run(cmd, cwd=build_dir, check=True, stdin=subprocess.DEVNULL)
+    meta = info.objects.add()
+    meta.file_name = "html"
+    meta.coverage_html.SetInParent()
+
+    write_metadata(opts, info)
+
+
+def bundle_firmware(opts):
+    """Bundles the artifacts from each target into its own tarball."""
+    info = firmware_pb2.FirmwareArtifactInfo()
+    info.bcs_version_info.version_string = opts.bcs_version
+    bundle_dir = get_bundle_dir(opts)
+    zephyr_dir = pathlib.Path(__file__).parent.resolve()
+    platform_ec = zephyr_dir.parent
+    for project in zmake.project.find_projects(zephyr_dir).values():
+        build_dir = (
+            platform_ec / "build" / "zephyr" / project.config.project_name
+        )
+        artifacts_dir = build_dir / "output"
+        tarball_name = f"{project.config.project_name}.firmware.tbz2"
+        tarball_path = bundle_dir.joinpath(tarball_name)
+        cmd = ["tar", "cvfj", tarball_path, "."]
+        log_cmd(cmd)
+        subprocess.run(
+            cmd, cwd=artifacts_dir, check=True, stdin=subprocess.DEVNULL
+        )
+        meta = info.objects.add()
+        meta.file_name = tarball_name
+        meta.tarball_info.type = (
+            firmware_pb2.FirmwareArtifactInfo.TarballInfo.FirmwareType.EC
+        )
+        # TODO(kmshelton): Populate the rest of metadata contents as it
+        # gets defined in infra/proto/src/chromite/api/firmware.proto.
+
+    write_metadata(opts, info)
+
+
+def test(opts):
+    """Runs all of the unit tests for Zephyr firmware"""
+    metrics = firmware_pb2.FwTestMetricList()
+
+    zephyr_dir = pathlib.Path(__file__).parent.resolve()
+
+    # Run tests from Makefile.cq because make knows how to run things
+    # in parallel.
+    cmd = ["make", "-f", "Makefile.cq", f"-j{opts.cpus}", "test"]
+    if opts.code_coverage:
+        cmd.append("COVERAGE=1")
+    if SPECIAL_BOARDS:
+        cmd.append(f"SPECIAL_BOARDS={' '.join(SPECIAL_BOARDS)}")
+    log_cmd(cmd)
+    subprocess.run(
+        cmd,
+        check=True,
+        cwd=zephyr_dir,
+        stdin=subprocess.DEVNULL,
+    )
+
+    # Twister-based tests
+    platform_ec = zephyr_dir.parent
+    twister_out_dir = platform_ec / "twister-out-llvm"
+    twister_out_dir_gcc = platform_ec / "twister-out-host"
+
+    if opts.code_coverage:
+        build_dir = platform_ec / "build" / "zephyr"
+        _extract_lcov_summary(
+            "EC_ZEPHYR_TESTS", metrics, twister_out_dir / "coverage.info"
+        )
+        _extract_lcov_summary(
+            "EC_ZEPHYR_TESTS_GCC",
+            metrics,
+            twister_out_dir_gcc / "coverage.info",
+        )
+        _extract_lcov_summary(
+            "EC_LEGACY_TESTS", metrics, platform_ec / "build/coverage/lcov.info"
+        )
+        _extract_lcov_summary(
+            "ALL_TESTS", metrics, build_dir / "all_tests.info"
+        )
+        _extract_lcov_summary(
+            "EC_ZEPHYR_MERGED", metrics, build_dir / "zephyr_merged.info"
+        )
+        _extract_lcov_summary("ALL_MERGED", metrics, build_dir / "lcov.info")
+        _extract_lcov_summary(
+            "ALL_FILTERED", metrics, build_dir / "lcov_no_tests.info"
+        )
+
+        for board in SPECIAL_BOARDS:
+            _extract_lcov_summary(
+                f"BOARD_{board}".upper(),
+                metrics,
+                build_dir / (board + "_final.info"),
+            )
+
+    with open(opts.metrics, "w") as file:
+        file.write(json_format.MessageToJson(metrics))  # type: ignore
+
+
+COVERAGE_RE = re.compile(
+    r"lines\.*: *([0-9\.]+)% \(([0-9]+) of ([0-9]+) lines\)"
+)
+
+
+def _extract_lcov_summary(name, metrics, filename):
+    zephyr_dir = pathlib.Path(__file__).parent.resolve()
+    cmd = [
+        "/usr/bin/lcov",
+        "--summary",
+        filename,
+    ]
+    log_cmd(cmd)
+    output = subprocess.run(
+        cmd,
+        cwd=zephyr_dir,
+        check=True,
+        stdout=subprocess.PIPE,
+        universal_newlines=True,
+        stdin=subprocess.DEVNULL,
+    ).stdout
+    re_match = COVERAGE_RE.search(output)
+    if re_match:
+        metric = metrics.value.add()
+        metric.name = name
+        metric.coverage_percent = float(re_match.group(1))
+        metric.covered_lines = int(re_match.group(2))
+        metric.total_lines = int(re_match.group(3))
+
+
+def main(args):
+    """Builds and tests all of the Zephyr targets and reports build metrics"""
+    opts = parse_args(args)
+
+    if not hasattr(opts, "func"):
+        print("Must select a valid sub command!")
+        return -1
+
+    # Run selected sub command function
+    opts.func(opts)
+    return 0
+
+
+def parse_args(args):
+    """Parse command line args."""
+    parser = argparse.ArgumentParser(description=__doc__)
+
+    parser.add_argument(
+        "--cpus",
+        default=multiprocessing.cpu_count(),
+        help="The number of cores to use.",
+    )
+
+    parser.add_argument(
+        "--metrics",
+        dest="metrics",
+        required=True,
+        help="File to write the json-encoded MetricsList proto message.",
+    )
+
+    parser.add_argument(
+        "--metadata",
+        required=False,
+        help=(
+            "Full pathname for the file in which to write build artifact "
+            "metadata."
+        ),
+    )
+
+    parser.add_argument(
+        "--output-dir",
+        required=False,
+        help=(
+            "Full pathname for the directory in which to bundle build "
+            "artifacts."
+        ),
+    )
+
+    parser.add_argument(
+        "--code-coverage",
+        required=False,
+        action="store_true",
+        help="Build host-based unit tests for code coverage.",
+    )
+
+    parser.add_argument(
+        "--bcs-version",
+        dest="bcs_version",
+        default="",
+        required=False,
+        # TODO(b/180008931): make this required=True.
+        help="BCS version to include in metadata.",
+    )
+
+    # Would make this required=True, but not available until 3.7
+    sub_cmds = parser.add_subparsers()
+
+    build_cmd = sub_cmds.add_parser("build", help="Builds all firmware targets")
+    build_cmd.set_defaults(func=build)
+
+    build_cmd = sub_cmds.add_parser(
+        "bundle",
+        help="Creates a tarball containing build "
+        "artifacts from all firmware targets",
+    )
+    build_cmd.set_defaults(func=bundle)
+
+    test_cmd = sub_cmds.add_parser("test", help="Runs all firmware unit tests")
+    test_cmd.set_defaults(func=test)
+
+    return parser.parse_args(args)
+
+
+if __name__ == "__main__":
+    sys.exit(main(sys.argv[1:]))
diff --git a/zephyr/fpu.cmake b/zephyr/fpu.cmake
new file mode 100644
index 0000000000..4cda364572
--- /dev/null
+++ b/zephyr/fpu.cmake
@@ -0,0 +1,40 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+#[[
+Disclaimer: the following example is pieced together from
+https://lemire.me/blog/2020/06/26/gcc-not-nearest/ along with other information
+found in GCC documentation.
+
+The following flags are needed to to ensure consistent FPU rounding in unit
+tests. For example using GNU GCC 7.5 rounds down. Note that at the time of
+writing, Clang 13.0.0 passes all the FPU unit tests without these flags.
+
+Some of the sensor logic which requires FPU support is susceptible to rounding
+errors. In GCC 7.5, as an example:
+
+  double x = 50178230318.0;
+  double y = 100000000000.0;
+  double ratio = x/y;
+
+In this example, we would expect ratio to be 0.50178230318. Instead, using a
+64-bit float, it falls between:
+* The floating-point number 0.501782303179999944 == 4519653187245114  * 2 ** -53
+* The floating-point number 0.501782303180000055 == 4519653187245115  * 2 ** -53
+
+The real mantissa using the same logic should be:
+0.50178230318 = 4519653187245114.50011795456 * 2 ** -53
+
+Since the mantissa's decimal is just over 0.5, it should stand to reason that
+the correct solution is 0.501782303180000055. To force GCC to round correctly
+we must set the following modes:
+1. 'sse' - Generate SSE instructions.
+2. 'fpmath=sse' - Use scalar floating-point instructions present in the SSE
+   instruction set.
+3. 'arch=pentium4' - Choose the Pentium4 because it's a stable choice that
+   supports SSE and is known to work (there may be other good choices).
+]]
+if(DEFINED CONFIG_SOC_POSIX)
+  zephyr_cc_option(-msse -mfpmath=sse -march=pentium4)
+endif()
diff --git a/zephyr/gcov.tmpl.sh b/zephyr/gcov.tmpl.sh
new file mode 100755
index 0000000000..b9dd0e7865
--- /dev/null
+++ b/zephyr/gcov.tmpl.sh
@@ -0,0 +1,7 @@
+#!/bin/bash
+#
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+exec ${CMAKE_GCOV} "$@"
diff --git a/zephyr/hayato_get_cfg.sh b/zephyr/hayato_get_cfg.sh
new file mode 100755
index 0000000000..1ab1be7a4f
--- /dev/null
+++ b/zephyr/hayato_get_cfg.sh
@@ -0,0 +1,45 @@
+#!/bin/bash
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# This is an example script showing how to compare configs on hayato
+
+# Usage of this script:
+# - set the three variables below
+# - set up the ecos.conf3 file as follows:
+#   $ make print-configs BOARD=hayato >econ.conf
+#   $ grep CONFIG ecos.conf |sort |uniq >ecos.conf2
+#   $ cat ecos.conf2  |awk '{print $1}' >ecos.conf3
+# - configure and build hayato for zephyr
+#   $ zmake configure -B /tmp/z/hay zephyr/projects/asurada/hayato/ -t zephyr -b
+# - run this script to check for CONFIG mismatches
+#   $ zephyr/get_cfg.sh
+
+set -e
+
+dir=/tmp/z/hay
+subdir=build-singleimage
+in=~/cosarm/src/platform/ec/ecos.conf3
+
+cd "${dir}"
+pushd "${subdir}"
+
+# This is created by running:
+#
+#    ninja -v -C /tmp/z/hay/build-singleimage
+#
+# then replacing '-C' by '-E -dM'
+# The idea is to get a list of the #defines used to compile the code
+ccache /opt/zephyr-sdk/riscv64-zephyr-elf/bin/riscv64-zephyr-elf-gcc -DBUILD_VERSION=zephyr-v2.5.0-101-g7a99b4a3ee12 -DCHROMIUM_EC -DCONFIG_ZEPHYR -DKERNEL -D_FORTIFY_SOURCE=2 -D__ZEPHYR__=1 -I/scratch/sglass/cosarm/src/platform/ec/zephyr/include -I/tmp/z/hay/modules/ec/zephyr/shim/include -I/tmp/z/hay/modules/ec/fuzz -I/tmp/z/hay/modules/ec/test -I/tmp/z/hay/modules/ec/include -I/tmp/z/hay/modules/ec/include/driver -I/tmp/z/hay/modules/ec/third_party -I/scratch/sglass/cosarm/src/platform/ec/zephyr/app/ec/include -I/scratch/sglass/cosarm/src/platform/ec/zephyr/shim/chip/it8xxx2/include -I/scratch/sglass/cosarm/src/third_party/zephyr/main/v2.5/include -Izephyr/include/generated -I/scratch/sglass/cosarm/src/third_party/zephyr/main/v2.5/soc/riscv/riscv-ite/it8xxx2 -I/scratch/sglass/cosarm/src/third_party/zephyr/main/v2.5/soc/riscv/riscv-ite/common/. -Iec/include/generated -I/scratch/sglass/cosarm/src/platform/ec/zephyr/projects/asurada/hayato/include -isystem /scratch/sglass/cosarm/src/third_party/zephyr/main/v2.5/lib/libc/minimal/include -isystem /opt/zephyr-sdk/riscv64-zephyr-elf/bin/../lib/gcc/riscv64-zephyr-elf/9.2.0/include -isystem /opt/zephyr-sdk/riscv64-zephyr-elf/bin/../lib/gcc/riscv64-zephyr-elf/9.2.0/include-fixed -Os -imacros /tmp/z/hay/build-singleimage/zephyr/include/generated/autoconf.h -ffreestanding -fno-common -g -mabi=ilp32 -march=rv32imac -imacros /scratch/sglass/cosarm/src/third_party/zephyr/main/v2.5/include/toolchain/zephyr_stdint.h -Wall -Wformat -Wformat-security -Wno-format-zero-length -Wno-main -Wno-pointer-sign -Wpointer-arith -Wno-address-of-packed-member -Wno-unused-but-set-variable -Werror=implicit-int -fno-asynchronous-unwind-tables -fno-pie -fno-pic -fno-strict-overflow -fno-reorder-functions -fno-defer-pop -fmacro-prefix-map=/scratch/sglass/cosarm/src/platform/ec/zephyr/projects/asurada/hayato=CMAKE_SOURCE_DIR -fmacro-prefix-map=/scratch/sglass/cosarm/src/third_party/zephyr/main/v2.5=ZEPHYR_BASE -ffunction-sections -fdata-sections -march=rv32i -std=c99 -nostdinc -MD -MT CMakeFiles/app.dir/tmp/z/hay/modules/ec/common/virtual_battery.c.obj -MF CMakeFiles/app.dir/tmp/z/hay/modules/ec/common/virtual_battery.c.obj.d \
+	-o /tmp/z/hay/zephyr.conf -E -dM \
+	/tmp/z/hay/modules/ec/common/virtual_battery.c
+popd
+
+sort <zephyr.conf >zephyr.conf2
+
+# Only look at CONFIG_xxx where xxx does not start with PLATFORM_EC
+grep <zephyr.conf2 -P 'CONFIG_(?!PLATFORM_EC)[A-Z]+' | \
+	awk '{print $2}' | \
+	sort >zephyr.conf3
+comm -23 "${in}" zephyr.conf3
diff --git a/zephyr/include/ap_power/ap_power.h b/zephyr/include/ap_power/ap_power.h
new file mode 100644
index 0000000000..05387d8431
--- /dev/null
+++ b/zephyr/include/ap_power/ap_power.h
@@ -0,0 +1,222 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ * @brief Public APIs for AP power sequence.
+ *
+ * Defines the API for AP event notification,
+ * the API to register and receive notification callbacks when
+ * application processor (AP) events happen.
+ *
+ * When the Zephyr based AP power sequence config is enabled,
+ * the callbacks are almost all invoked within the context
+ * of the power sequence task, so the state is stable
+ * during the callback. The only exception to this is AP_POWER_RESET, which is
+ * invoked as a result of receiving a PLTRST# virtual wire signal (if enabled).
+ *
+ * When the legacy power sequence config is enabled, the callbacks are invoked
+ * from the HOOK_CHIPSET notifications.
+ */
+
+#ifndef __AP_POWER_AP_POWER_H__
+#define __AP_POWER_AP_POWER_H__
+
+#include <zephyr/kernel.h>
+
+/**
+ * @brief AP power events for callback notification.
+ */
+enum ap_power_events {
+	/**
+	 * Transitioning from hard-off to soft-off.
+	 *
+	 * On x86 this is the transition up from G3 to S5.
+	 */
+	AP_POWER_PRE_INIT = BIT(0),
+	/**
+	 * Transitioning from soft-off to suspend.
+	 *
+	 * On x86 this is going from S5 to S3.
+	 */
+	AP_POWER_STARTUP = BIT(1),
+	/**
+	 * Transitioning from suspend to active.
+	 *
+	 * This event is emitted on all suspend-active transitions, regardless
+	 * of suspend level. In particular, on x86 it is triggered by transition
+	 * from either of S3 or S0ix to S0.
+	 */
+	AP_POWER_RESUME = BIT(2),
+	/**
+	 * Transitioning from active to suspend.
+	 *
+	 * This is the opposite of AP_POWER_RESUME. On x86, it is emitted when
+	 * leaving S0 to either of S3 or S0ix.
+	 */
+	AP_POWER_SUSPEND = BIT(3),
+#if CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK
+	/**
+	 * Early transition from suspend to active.
+	 *
+	 * This event runs under the same conditions as AP_POWER_RESUME, but
+	 * is guaranteed to run before AP_POWER_RESUME.
+	 */
+	AP_POWER_RESUME_INIT = BIT(4),
+	/**
+	 * Late transition from active to suspend.
+	 *
+	 * This event runs under the same conditions as AP_POWER_SUSPEND, but
+	 * is guaranteed to run after AP_POWER_SUSPEND.
+	 */
+	AP_POWER_SUSPEND_COMPLETE = BIT(5),
+#endif
+	/**
+	 * Transitioning from suspend to soft-off.
+	 *
+	 * This is the opposite of AP_POWER_STARTUP. On x86 it is the transition
+	 * from S3 to S5.
+	 */
+	AP_POWER_SHUTDOWN = BIT(6),
+	/**
+	 * Late transition from suspend to soft-off.
+	 *
+	 * This runs under the same conditions as AP_POWER_SHUTDOWN, but runs
+	 * after AP_POWER_SHUTDOWN.
+	 */
+	AP_POWER_SHUTDOWN_COMPLETE = BIT(7),
+	/**
+	 * Transitioning from soft-off to hard-off.
+	 *
+	 * This is the opposite of AP_POWER_PRE_INIT. On x86 it is the
+	 * transition from S5 to G3.
+	 */
+	AP_POWER_HARD_OFF = BIT(8),
+	/** Software reset occurred */
+	AP_POWER_RESET = BIT(9),
+	/**
+	 * AP power state is now known.
+	 *
+	 * Prior to this event, the state of the AP is unknown
+	 * and invalid. When this event is sent, the state is known
+	 * and can be queried. Used by clients when their
+	 * initialization depends upon the initial state of the AP.
+	 */
+	AP_POWER_INITIALIZED = BIT(10),
+
+	/**
+	 * S0ix suspend starts.
+	 */
+	AP_POWER_S0IX_SUSPEND_START = BIT(11),
+	/**
+	 * Transitioning from s0 to s0ix.
+	 */
+	AP_POWER_S0IX_SUSPEND = BIT(12),
+	/**
+	 * Transitioning from s0ix to s0.
+	 */
+	AP_POWER_S0IX_RESUME = BIT(13),
+	/**
+	 * si0x resume complete.
+	 */
+	AP_POWER_S0IX_RESUME_COMPLETE = BIT(14),
+	/**
+	 * Reset s0ix tracking.
+	 */
+	AP_POWER_S0IX_RESET_TRACKING = BIT(15),
+};
+
+/**
+ * @brief AP data for callback argument.
+ */
+struct ap_power_ev_data {
+	enum ap_power_events event;
+	/* May need more data here */
+};
+
+struct ap_power_ev_callback;
+
+/**
+ * @brief Callback handler definition
+ */
+typedef void (*ap_power_ev_callback_handler_t)(struct ap_power_ev_callback *cb,
+					       struct ap_power_ev_data data);
+
+/**
+ * @cond INTERNAL_HIDDEN
+ *
+ * Register a callback for the AP power events requested.
+ * As many callbacks as needed can be added as long as each of them
+ * are unique pointers of struct ap_power_ev_callback.
+ * The storage must be static.
+ *
+ * ap_power_ev_init_callback can be used to initialize this structure.
+ */
+struct ap_power_ev_callback {
+	sys_snode_t node; /* Only usable by AP power event code */
+	ap_power_ev_callback_handler_t handler;
+	enum ap_power_events events; /* Events to listen for */
+};
+/** @endcond */
+
+/**
+ * @brief Initialise a struct ap_power_ev_callback properly.
+ *
+ * @param callback A valid ap_power_ev_callback structure pointer.
+ * @param handler The function pointer to call.
+ * @param events The bitmask of events to be called for.
+ */
+static inline void
+ap_power_ev_init_callback(struct ap_power_ev_callback *cb,
+			  ap_power_ev_callback_handler_t handler,
+			  enum ap_power_events events)
+{
+	__ASSERT(cb, "Callback pointer should not be NULL");
+	__ASSERT(handler, "Callback handler pointer should not be NULL");
+
+	cb->handler = handler;
+	cb->events = events;
+}
+
+/**
+ * @brief Update a callback event mask to listen for new events
+ *
+ * @param callback A valid ap_power_ev_callback structure pointer.
+ * @param events The bitmask of events to add.
+ */
+void ap_power_ev_add_events(struct ap_power_ev_callback *cb,
+			    enum ap_power_events events);
+
+/**
+ * @brief Update a callback event mask to remove events
+ *
+ * @param callback A valid ap_power_ev_callback structure pointer.
+ * @param events The bitmask of events to remove.
+ */
+static inline void ap_power_ev_remove_events(struct ap_power_ev_callback *cb,
+					     enum ap_power_events events)
+{
+	__ASSERT(cb, "Callback pointer should not be NULL");
+
+	cb->events &= ~events;
+}
+
+/**
+ * @brief Add an AP event callback.
+ *
+ * @param callback A valid ap_power_ev_callback structure pointer.
+ * @return 0 on success, negative errno on failure.
+ */
+int ap_power_ev_add_callback(struct ap_power_ev_callback *cb);
+
+/**
+ * @brief Remove an AP event callback.
+ *
+ * @param callback A valid ap_power_ev_callback structure pointer.
+ * @return 0 on success, negative errno on failure.
+ */
+int ap_power_ev_remove_callback(struct ap_power_ev_callback *cb);
+
+#endif /* __AP_POWER_AP_POWER_H__ */
diff --git a/zephyr/include/ap_power/ap_power_espi.h b/zephyr/include/ap_power/ap_power_espi.h
new file mode 100644
index 0000000000..2c295054f3
--- /dev/null
+++ b/zephyr/include/ap_power/ap_power_espi.h
@@ -0,0 +1,35 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ * @brief API for power signal ESPI callback.
+ */
+
+#ifndef __AP_POWER_AP_POWER_ESPI_H__
+#define __AP_POWER_AP_POWER_ESPI_H__
+
+#include <zephyr/drivers/espi.h>
+
+/**
+ * @brief ESPI callback for power signal handling.
+ *
+ * This callback must be registered for the bus events indicated below
+ * as part of the common ESPI initialisation and configuration.
+ *
+ * @param dev ESPI device
+ * @param cb Callback structure
+ * @param event ESPI event data
+ */
+void power_signal_espi_cb(const struct device *dev, struct espi_callback *cb,
+			  struct espi_event event);
+
+/*
+ * The ESPI bus events required for the power signal ESPI callback.
+ */
+#define POWER_SIGNAL_ESPI_BUS_EVENTS \
+	(ESPI_BUS_EVENT_CHANNEL_READY | ESPI_BUS_EVENT_VWIRE_RECEIVED)
+
+#endif /* __AP_POWER_AP_POWER_ESPI_H__ */
diff --git a/zephyr/include/ap_power/ap_power_events.h b/zephyr/include/ap_power/ap_power_events.h
new file mode 100644
index 0000000000..f729c68e9e
--- /dev/null
+++ b/zephyr/include/ap_power/ap_power_events.h
@@ -0,0 +1,23 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ * @brief Internal API for sending AP power related event callbacks.
+ */
+
+#ifndef __AP_POWER_AP_EVENTS_H__
+#define __AP_POWER_AP_EVENTS_H__
+
+#include <ap_power/ap_power.h>
+
+/**
+ * @brief Dispatch callbacks for an event.
+ *
+ * @param event The event to invoke callbacks for.
+ */
+void ap_power_ev_send_callbacks(enum ap_power_events event);
+
+#endif /* __AP_POWER_AP_EVENTS_H__ */
diff --git a/zephyr/include/ap_power/ap_power_interface.h b/zephyr/include/ap_power/ap_power_interface.h
new file mode 100644
index 0000000000..9a36091deb
--- /dev/null
+++ b/zephyr/include/ap_power/ap_power_interface.h
@@ -0,0 +1,227 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ * @brief External API interface to AP power sequence subsystem.
+ *
+ * Defines the interface to the AP power sequence module,
+ * which includes:
+ *  - enums for the power state mask of the AP
+ *  - enums indicating the reason for shutdown
+ *  - enums for providing control values
+ *  - function declarations for getting the state of the AP
+ *  - function declarations for requesting actions
+ *
+ * These definitions are roughly equivalent to the legacy
+ * chipset API, but are separate to ensure there is no
+ * reference to the legacy API. To reflect this,
+ * equivalent functions are prepended with ap_power_ instead
+ * of chipset_.
+ */
+
+#ifndef __AP_POWER_AP_POWER_INTERFACE_H__
+#define __AP_POWER_AP_POWER_INTERFACE_H__
+
+#include <zephyr/sys/util.h>
+
+#ifndef CONFIG_AP_PWRSEQ_DRIVER
+/**
+ * @brief System power states for Non Deep Sleep Well
+ * EC is an always on device in a Non Deep Sx system except when EC
+ * is hibernated or all the VRs are turned off.
+ */
+enum power_states_ndsx {
+	/* Power state machine is not ready; AP state is unknown. */
+	SYS_POWER_STATE_UNINIT,
+	/*
+	 * Actual power states
+	 */
+	/* AP is off & EC is on */
+	SYS_POWER_STATE_G3,
+	/* AP is in soft off state */
+	SYS_POWER_STATE_S5,
+	/* AP is suspended to Non-volatile disk */
+	SYS_POWER_STATE_S4,
+	/* AP is suspended to RAM */
+	SYS_POWER_STATE_S3,
+#if CONFIG_AP_PWRSEQ_S0IX
+	/* AP is in idle standby; cache is flushed to RAM */
+	SYS_POWER_STATE_S0ix,
+#endif
+	/* AP is in active state */
+	SYS_POWER_STATE_S0,
+	/*
+	 * Intermediate power up states
+	 */
+	/* Determine if the AP's power rails are turned on */
+	SYS_POWER_STATE_G3S5,
+	/* Determine if AP is suspended from sleep */
+	SYS_POWER_STATE_S5S4,
+	/* Determine if Suspend to Disk is de-asserted */
+	SYS_POWER_STATE_S4S3,
+	/* Determine if Suspend to RAM is de-asserted */
+	SYS_POWER_STATE_S3S0,
+#if CONFIG_AP_PWRSEQ_S0IX
+	/* Determine if Suspend to idle is de-asserted */
+	SYS_POWER_STATE_S0ixS0,
+#endif
+	/*
+	 * Intermediate power down states
+	 */
+	/* Determine if the AP's power rails are turned off */
+	SYS_POWER_STATE_S5G3,
+	/* Determine if AP is suspended to sleep */
+	SYS_POWER_STATE_S4S5,
+	/* Determine if Suspend to Disk is asserted */
+	SYS_POWER_STATE_S3S4,
+	/* Determine if Suspend to RAM is asserted */
+	SYS_POWER_STATE_S0S3,
+#if CONFIG_AP_PWRSEQ_S0IX
+	/* Determine if Suspend to idle is asserted */
+	SYS_POWER_STATE_S0S0ix,
+#endif
+};
+#endif /* CONFIG_AP_PWRSEQ_DRIVER */
+
+/**
+ * @brief Represents the state of the AP as a mask.
+ */
+enum ap_power_state_mask {
+	AP_POWER_STATE_HARD_OFF = BIT(0), /* Hard off (G3) */
+	AP_POWER_STATE_SOFT_OFF = BIT(1), /* Soft off (S5, S4) */
+	AP_POWER_STATE_SUSPEND = BIT(2), /* Suspend (S3) */
+	AP_POWER_STATE_ON = BIT(3), /* On (S0) */
+	AP_POWER_STATE_STANDBY = BIT(4), /* Standby (S0ix) */
+	/* Common combinations, any off state */
+	AP_POWER_STATE_ANY_OFF =
+		(AP_POWER_STATE_HARD_OFF | AP_POWER_STATE_SOFT_OFF),
+	/* This combination covers any kind of suspend i.e. S3 or S0ix. */
+	AP_POWER_STATE_ANY_SUSPEND =
+		(AP_POWER_STATE_SUSPEND | AP_POWER_STATE_STANDBY),
+};
+
+/**
+ * @brief AP shutdown reason codes
+ *
+ * These enums <em>MUST</em> be kept as the same corresponding values
+ * as the values in
+ * https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/include/ec_commands.h
+ * since they are referenced in external programs.
+ * Before changing any of these values, read the comments
+ * in ec_command.h
+ */
+enum ap_power_shutdown_reason {
+	/*
+	 * Beginning of reset reasons.
+	 */
+	AP_POWER_RESET_BEGIN = 0,
+	AP_POWER_RESET_UNKNOWN = AP_POWER_RESET_BEGIN,
+	/* Custom reason defined by a board.c or baseboard.c file */
+	AP_POWER_RESET_BOARD_CUSTOM,
+	/* Believe that the AP has hung */
+	AP_POWER_RESET_HANG_REBOOT,
+	/* Reset by EC console command */
+	AP_POWER_RESET_CONSOLE_CMD,
+	/* Reset by EC host command */
+	AP_POWER_RESET_HOST_CMD,
+	/* Keyboard module reset key combination */
+	AP_POWER_RESET_KB_SYSRESET,
+	/* Keyboard module warm reboot */
+	AP_POWER_RESET_KB_WARM_REBOOT,
+	/* Debug module warm reboot */
+	AP_POWER_RESET_DBG_WARM_REBOOT,
+	/* I cannot self-terminate.  You must lower me into the steel. */
+	AP_POWER_RESET_AP_REQ,
+	/* Reset as side-effect of startup sequence */
+	AP_POWER_RESET_INIT,
+	/* EC detected an AP watchdog event. */
+	AP_POWER_RESET_AP_WATCHDOG,
+
+	AP_POWER_RESET_COUNT, /* End of reset reasons. */
+
+	/*
+	 * Beginning of shutdown reasons.
+	 */
+	AP_POWER_SHUTDOWN_BEGIN = BIT(15),
+	AP_POWER_SHUTDOWN_POWERFAIL = AP_POWER_SHUTDOWN_BEGIN,
+	/* Forcing a shutdown as part of EC initialization */
+	AP_POWER_SHUTDOWN_INIT,
+	/* Custom reason on a per-board basis. */
+	AP_POWER_SHUTDOWN_BOARD_CUSTOM,
+	/* This is a reason to inhibit startup, not cause shut down. */
+	AP_POWER_SHUTDOWN_BATTERY_INHIBIT,
+	/* A power_wait_signal is being asserted */
+	AP_POWER_SHUTDOWN_WAIT,
+	/* Critical battery level. */
+	AP_POWER_SHUTDOWN_BATTERY_CRIT,
+	/* Because you told me to. */
+	AP_POWER_SHUTDOWN_CONSOLE_CMD,
+	/* Forcing a shutdown to effect entry to G3. */
+	AP_POWER_SHUTDOWN_G3,
+	/* Force shutdown due to over-temperature. */
+	AP_POWER_SHUTDOWN_THERMAL,
+	/* Force a AP shutdown from the power button through EC */
+	AP_POWER_SHUTDOWN_BUTTON,
+
+	AP_POWER_SHUTDOWN_COUNT, /* End of shutdown reasons. */
+};
+
+/**
+ * @brief Check if AP is in a given state.
+ *
+ * @param state_mask Combination of one or more AP_POWER_STATE_* flags.
+ * @return non-zero if the AP is in one of the states specified in the mask.
+ */
+bool ap_power_in_state(enum ap_power_state_mask state_mask);
+
+/**
+ * Check if AP is in a given state or if the AP task is currently
+ * transitioning to that state. For example, G3S5, S5, and S3S5 would all count
+ * as the S5 state.
+ *
+ * @param state_mask Combination of one or more AP_POWER_STATE_* flags.
+ *
+ * @return true if the AP is in one of the states specified in the
+ * mask.
+ */
+bool ap_power_in_or_transitioning_to_state(enum ap_power_state_mask sm);
+
+/**
+ * @brief Ask the AP to exit the hard off state.
+ *
+ * Does nothing if the AP has already left the state, or was not in the
+ * state to begin with.
+ */
+void ap_power_exit_hardoff(void);
+
+/**
+ * @brief Reset the AP
+ *
+ * @param reason The reason why the AP is being reset.
+ */
+void ap_power_reset(enum ap_power_shutdown_reason reason);
+
+/**
+ * @brief Immediately shut off power to the AP.
+ *
+ * This is intended for use when the system is too hot or battery power is
+ * critical.
+ *
+ * @param reason The reason why the AP is being shut down.
+ */
+void ap_power_force_shutdown(enum ap_power_shutdown_reason reason);
+
+/**
+ * @brief Initialise the AP reset log.
+ */
+void ap_power_init_reset_log(void);
+
+/**
+ * @brief Starts the AP power sequence thread.
+ */
+void ap_pwrseq_task_start(void);
+
+#endif /* __AP_POWER_AP_POWER_INTERFACE_H__ */
diff --git a/zephyr/include/ap_power/ap_pwrseq.h b/zephyr/include/ap_power/ap_pwrseq.h
new file mode 100644
index 0000000000..813b4f231b
--- /dev/null
+++ b/zephyr/include/ap_power/ap_pwrseq.h
@@ -0,0 +1,212 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _AP_PWRSEQ_H_
+#define _AP_PWRSEQ_H_
+#include <zephyr/device.h>
+#include <zephyr/kernel.h>
+
+#ifndef CONFIG_AP_PWRSEQ_DRIVER
+void ap_pwrseq_wake(void);
+#else
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define AP_POWER_SUB_STATE_ENUM_DEF_WITH_COMMA(node_id, prop, idx) \
+	DT_CAT6(node_id, _P_, prop, _IDX_, idx, _STRING_UPPER_TOKEN),
+
+#define AP_PWRSEQ_EACH_SUB_STATE_ENUM_DEF(node_id)                              \
+	COND_CODE_1(                                                            \
+		DT_NODE_HAS_PROP(node_id, chipset),                             \
+		(DT_FOREACH_PROP_ELEM(node_id, chipset,                         \
+				      AP_POWER_SUB_STATE_ENUM_DEF_WITH_COMMA)), \
+		(COND_CODE_1(DT_NODE_HAS_PROP(node_id, application),            \
+			     (DT_FOREACH_PROP_ELEM(                             \
+				     node_id, application,                      \
+				     AP_POWER_SUB_STATE_ENUM_DEF_WITH_COMMA)),  \
+			     ())))
+
+/**
+ * @brief AP power sequence valid power states.
+ *
+ * Note: States enum list MUST remain arranged from the lowest to the highest
+ * power state.
+ *
+ **/
+/* clang-format off */
+enum ap_pwrseq_state {
+	AP_POWER_STATE_UNINIT, /* EC and AP are Uninitialized */
+	AP_POWER_STATE_G3, /* AP is OFF */
+	AP_POWER_STATE_S5, /* AP is on soft off state */
+	AP_POWER_STATE_S4, /* AP is suspended to Non-volatile disk */
+	AP_POWER_STATE_S3, /* AP is suspended to RAM */
+	AP_POWER_STATE_S2, /* AP is low wake-latency sleep */
+	AP_POWER_STATE_S1, /* AP is in suspend state */
+	AP_POWER_STATE_S0, /* AP is in active state */
+	DT_FOREACH_STATUS_OKAY(ap_pwrseq_sub_states,
+			       AP_PWRSEQ_EACH_SUB_STATE_ENUM_DEF)
+	AP_POWER_STATE_COUNT,
+	AP_POWER_STATE_UNDEF = 0xFFFE,
+	AP_POWER_STATE_ERROR = 0xFFFF,
+};
+/* clang-format on */
+
+/** @brief AP power sequence events. */
+enum ap_pwrseq_event {
+	AP_PWRSEQ_EVENT_POWER_STARTUP,
+	AP_PWRSEQ_EVENT_POWER_SIGNAL,
+	AP_PWRSEQ_EVENT_POWER_TIMEOUT,
+	AP_PWRSEQ_EVENT_POWER_SHUTDOWN,
+	AP_PWRSEQ_EVENT_HOST,
+	AP_PWRSEQ_EVENT_COUNT,
+};
+
+/** @brief The signature for callback notification from AP power seqeuce driver.
+ *
+ * This function will be invoked by AP power sequence driver as configured by
+ * functions `ap_pwrseq_register_state_entry_callback` or
+ * `ap_pwrseq_register_state_entry_callback` for power state transitions.
+ *
+ * @param dev Pointer of AP power sequence device driver.
+ *
+ * @param entry Entering state in transition.
+ *
+ * @param exit Exiting state in transition.
+ *
+ * @retval None.
+ */
+typedef void (*ap_pwrseq_callback)(const struct device *dev,
+				   enum ap_pwrseq_state entry,
+				   enum ap_pwrseq_state exit);
+
+struct ap_pwrseq_state_callback {
+	/* Node used to link notifications. This is for internal use only */
+	sys_snode_t node;
+	/**
+	 * Callback function, this will be invoked when AP power sequence
+	 * enters or exits states selected by `states_bit_mask`.
+	 **/
+	ap_pwrseq_callback cb;
+	/* Bitfield of states to invoke callback */
+	uint32_t states_bit_mask;
+};
+
+/**
+ * @brief Get AP power sequence device driver pointer.
+ *
+ * @param None.
+ *
+ * @retval AP power sequence device driver pointer.
+ **/
+const struct device *ap_pwrseq_get_instance(void);
+
+/**
+ * @brief Starts AP power sequence driver thread execution.
+ *
+ * @param dev Pointer of AP power sequence device driver.
+ *
+ * @param init_state state that will be executed when staring.
+ *
+ * @retval SUCCESS Driver starts execution.
+ * @retval -EINVAL State provided is invalid.
+ * @retval -EPERM  Driver is already started.
+ **/
+int ap_pwrseq_start(const struct device *dev, enum ap_pwrseq_state init_state);
+
+/**
+ * @brief Post event for AP power sequence driver.
+ *
+ * State machine is executed within AP power sequence thread, this thread goes
+ * to sleep when state machine is idle and state transition is completed.
+ * Events are posted to wake up AP power sequence thread and made available to
+ * state machine only for the following iteration.
+ *
+ * @param dev Pointer of AP power sequence device driver.
+ *
+ * @param event Event posted to AP power seuqence driver.
+ *
+ * @retval None.
+ **/
+void ap_pwrseq_post_event(const struct device *dev, enum ap_pwrseq_event event);
+
+/**
+ * @brief Get enumeration value of current state of AP power sequence driver.
+ *
+ * @param dev Pointer of AP power sequence device driver.
+ *
+ * @retval Valid state enumeration value.
+ * @retval AP_POWER_STATE_UNDEF if error.
+ **/
+enum ap_pwrseq_state ap_pwrseq_get_current_state(const struct device *dev);
+
+/**
+ * @brief Get null terminated string of selected state.
+ *
+ * @param state AP power sequence valid state.
+ *
+ * @retval String showing selected state name.
+ * @retval NULL if state is invalid.
+ **/
+const char *const ap_pwrseq_get_state_str(enum ap_pwrseq_state state);
+
+/**
+ * @brief Lock current AP power sequence state.
+ *
+ * Once state machine is locked, it will not change its state until unlocked.
+ *
+ * @param dev Pointer of AP power sequence device driver.
+ *
+ * @retval SUCCESS Driver has been successfully locked, non-zero otherwise.
+ **/
+int ap_pwrseq_state_lock(const struct device *dev);
+
+/**
+ * @brief Unlock AP power sequence state.
+ *
+ * @param dev Pointer of AP power sequence device driver.
+ *
+ * @retval SUCCESS Driver has been successfully unlocked, non-zero otherwise.
+ **/
+int ap_pwrseq_state_unlock(const struct device *dev);
+
+/**
+ * @brief Register callback into AP power sequence driver.
+ *
+ * Callback function will be called by AP power sequence driver when entering
+ * into selected states.
+ *
+ * @param dev Pointer of AP power sequence device driver.
+ *
+ * @param state_cb Pointer of `ap_pwrseq_state_callback` structure.
+ *
+ * @retval SUCCESS Callback was successfully registered.
+ * @retval -EINVAL On error.
+ **/
+int ap_pwrseq_register_state_entry_callback(
+	const struct device *dev, struct ap_pwrseq_state_callback *state_cb);
+
+/**
+ * @brief Register callback into AP power sequence driver.
+ *
+ * Callback function will be called by AP power sequence driver when exiting
+ * from selected states.
+ *
+ * @param dev Pointer of AP power sequence device driver.
+ *
+ * @param state_cb Pointer of `ap_pwrseq_state_callback` structure.
+ *
+ * @retval SUCCESS Callback was successfully registered.
+ * @retval -EINVAL On error.
+ **/
+int ap_pwrseq_register_state_exit_callback(
+	const struct device *dev, struct ap_pwrseq_state_callback *state_cb);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* CONFIG_AP_PWRSEQ_DRIVER */
+#endif /* _AP_PWRSEQ_H_ */
diff --git a/zephyr/include/ap_power/ap_pwrseq_sm.h b/zephyr/include/ap_power/ap_pwrseq_sm.h
new file mode 100644
index 0000000000..e1558ccd6f
--- /dev/null
+++ b/zephyr/include/ap_power/ap_pwrseq_sm.h
@@ -0,0 +1,390 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _AP_PWRSEQ_SM_H_
+#define _AP_PWRSEQ_SM_H_
+#include "ap_power/ap_pwrseq_sm_defs.h"
+
+/**
+ * AP power sequence state machine API
+ * -----------------------------------
+ *
+ * State machine is integrated into the AP power sequence driver by wrapping
+ * Zephyr State Machine Framework (SMF), each SMF state is represented by three
+ * functions or action handlers that define operations performed on state entry,
+ * run and exit.
+ *
+ * ACPI’s global state (G3) and its six sleep power states (S0, S1, S2, S3, S4,
+ * S5) are present within this state machine domain. All these ACPI states are
+ * are divided in three levels, each level is a SMF state with a hierarchical
+ * relation with others action handlers of the same ACPI state, state handlers
+ * at higher levels performes the most common task of corresponding ACPI power
+ * states.
+ *
+ * Architecture is the highest level of the hierarchy, SMF states this level
+ * must do operations that are specific to AP CPU architecture, example:
+ * X86 (intel), ARM.
+ *
+ * Middle level is the chipset; these SMF action handlers carry out operations
+ * to drive power of components that are required for the AP chip. Any bus
+ * signal or internal power rail that is vital for chip execution is a good fit
+ * to be handled in these action handlers. Examples of chipsets are: Tiger Lake
+ * and Jasper Lake, these are Intel chipsets that use X86 architecture, and
+ * MT8186 and MT8192 are Mediatek chipsets using ARM architecture.
+ *
+ * Application is the bottom level of the hierarchy and these SMF action
+ * handlers are reserved to address board or application specific computations.
+ *
+ * Hierarchical SMF will coordinate execution of entry, run & exit functions
+ * accordingly. Given that implementation is responsible for doing state
+ * transitions, the following considerations should be taken when implementing
+ * action state handlers:
+ *
+ * - Higher level `entry` actions are executed before the lower level `entry`
+ * actions.
+ * - Transitioning from one substate to another with a shared upper level state
+ * does not re-execute the upper level `entry` action or execute the `exit`
+ * action.
+ * - Upper level `exit` actions are executed after the substate `exit` actions.
+ * - Lower level `run` actions are executed before upper level.
+ * - Upper level `run` actions only executes if no state transition has been
+ * made from lower level `run` action.
+ *
+ * Please refer to Zephyr SMF documentation.
+ *
+ * This file exports macros that help to provide action handlers implementation
+ * for all states, and any substate that is declared in devicetree. It also
+ * declares functions to do power state transitions.
+ *
+ * Macros AP_POWER_ACRH_STATE_DEFINE, AP_POWER_CHIPSET_STATE_DEFINE and
+ * AP_POWER_APP_STATE_DEFINE statically declare action handlers for each power
+ * state.
+ *
+ * State Machine Workflow
+ * ----------------------
+ *
+ * State machine execution is done within AP power sequence driver thread
+ * context. Driver sets initial state upon initialization.
+ *
+ * On each driver thread loop ieration, current state `run` action handler is
+ * called following hierarchical order as set in zephyr SMF.
+ *
+ * State machine implements Ultimate Hook pattern, this allows upper level
+ * action handlers to finalize hierarchical execution flow by setting its
+ * returning value to anything different than zero.
+ *
+ * `ap_pwrseq_sm_set_state` must be used to do state transition, this will
+ * execute current state `exit` action handlers followed by next state `entry`
+ * action handlers, completing state transtion on next thread loop iteration
+ * when new state `run` action is called.
+ *
+ * State transitions are only permited to be done by implementation within
+ * corresponding AP power sequence driver context, and only one state transition
+ * is allowed per driver thread loop iteration.
+ *
+ * Example of wrong use of `ap_pwrseq_sm_set_state`:
+ *
+ * @code{.c}
+ * int arch_s0_run(void *data)
+ * {
+ *     // Transition started `entry` and `exit` functions called
+ *     ap_pwrseq_sm_set_state(data, AP_POWER_STATE_S5);
+ *     ...
+ *     // Nothing happens `ap_pwrseq_sm_set_state` returns -EINVAL.
+ *     ap_pwrseq_sm_set_state(data, AP_POWER_STATE_G3);
+ * }
+ * @endcode
+ *
+ * Example of correct use of `ap_pwrseq_sm_set_state`:
+ *
+ * @code{.c}
+ * int arch_s0_run(void *data)
+ * {
+ *     if (...) {
+ *         return ap_pwrseq_sm_set_state(data, AP_POWER_STATE_S5);
+ *     } else if (...) {
+ *         return ap_pwrseq_sm_set_state(data, AP_POWER_STATE_G3);
+ *     }
+ *     return 0;
+ * }
+ * @endcod
+ *
+ * For this same reason, `ap_pwrseq_sm_set_state` should not be called within
+ * `entry` or `exit` action handler.
+ */
+
+/*
+ * This is required to ensure macro AP_POWER_SM_DEF_STATE_HANDLER handles
+ * passing `NULL` properly.
+ */
+#ifdef NULL
+#undef NULL
+#define NULL 0
+#else
+#define NULL 0
+#endif
+
+/* User define action handler, each action handler must follow this type. */
+typedef int (*ap_pwr_state_action_handler)(void *data);
+
+#define AP_POWER_SM_HANDLER_DECL(action)           \
+	void ap_pwrseq_sm_exec_##action##_handler( \
+		void *const data, ap_pwr_state_action_handler handler)
+
+AP_POWER_SM_HANDLER_DECL(entry);
+AP_POWER_SM_HANDLER_DECL(run);
+AP_POWER_SM_HANDLER_DECL(exit);
+
+/**
+ * @brief Macro to define action handler wrapper function.
+ *
+ * @param name Valid enumaration value of state.
+ *
+ * @param level One of the three AP power sequence levels: arch, chipset or app.
+ *
+ * @param action One of the three SMF action handlers: entry, run or exit.
+ *
+ * @param handler Action handler function of type `ap_pwr_state_action_handler`.
+ *
+ * @retval Defines static wrapper function of handler to be called by AP power
+ * sequence state machine.
+ **/
+#define AP_POWER_SM_DEF_STATE_HANDLER(name, level, action, handler)            \
+	static void ap_pwr_##name##_##level##_##action##_##handler(void *data) \
+	{                                                                      \
+		ap_pwrseq_sm_exec_##action##_handler(data, handler);           \
+	}
+
+/**
+ * @brief Macro to define action handler wrapper function for a single level.
+ *
+ * @param name Valid enumaration value of state.
+ *
+ * @param level One of the three AP power sequence levels: arch, chipset or app.
+ *
+ * @param _entry Function called when entering into this state.
+ *
+ * @param _run Action handler function called when run operation is invoked.
+ *
+ * @param _exit Function called when exiting this state.
+ *
+ * @param handler Action handler function of type `ap_pwr_state_action_handler`.
+ *
+ * @retval Defines static wrapper function of handler to be called by AP power
+ * sequence state machine.
+ **/
+#define AP_POWER_SM_DEF_STATE_HANDLERS(name, level, _entry, _run, _exit) \
+	AP_POWER_SM_DEF_STATE_HANDLER(name, level, entry, _entry)        \
+	AP_POWER_SM_DEF_STATE_HANDLER(name, level, run, _run)            \
+	AP_POWER_SM_DEF_STATE_HANDLER(name, level, exit, _exit)
+
+/**
+ * @brief Macro to assemble action handler wrapper function name.
+ *
+ * @param name Valid enumaration value of state.
+ *
+ * @param level One of the three AP power sequence levels: arch, chipset or app.
+ *
+ * @param action One of the three SMF action handlers: entry, run or exit.
+ *
+ * @param handler Action handler function of type `ap_pwr_state_action_handler`.
+ *
+ * @retval Constructs static name of handler wrapper function to be called by
+ * AP power sequence state machine.
+ **/
+#define AP_POWER_SM_ACTION(name, level, action, handler) \
+	ap_pwr_##name##_##level##_##action##_##handler
+
+/**
+ * @brief Macro to create SMF state following AP power sequence.
+ *
+ * @param name Valid enumaration value of state.
+ *
+ * @param level One of the three AP power sequence levels: arch, chipset or app.
+ *
+ * @param _entry Function to be called when entrying state.
+ *
+ * @param _run Function to be called when executing `run` operation.
+ *
+ * @param _exit Function to be called when exiting state.
+ *
+ * @retval Defines global structure with action handlers to be used by AP
+ * power sequence state machine.
+ **/
+#define AP_POWER_SM_CREATE_STATE(name, level, _entry, _run, _exit, parent) \
+	SMF_CREATE_STATE(AP_POWER_SM_ACTION(name, level, entry, _entry),   \
+			 AP_POWER_SM_ACTION(name, level, run, _run),       \
+			 AP_POWER_SM_ACTION(name, level, exit, _exit), parent)
+
+/**
+ * @brief Define architecture level state action handlers.
+ *
+ * @param name Valid enumaration value of state.
+ *
+ * @param entry Function to be called when entrying state.
+ *
+ * @param run Function to be called when executing `run` operation.
+ *
+ * @param exit Function to be called when exiting state.
+ *
+ * @retval Defines global structure with action handlers to be used by AP
+ * power sequence state machine.
+ **/
+#define AP_POWER_ARCH_STATE_DEFINE(name, entry, run, exit)           \
+	AP_POWER_SM_DEF_STATE_HANDLERS(name, arch, entry, run, exit) \
+	const struct smf_state arch_##name##_actions =               \
+		AP_POWER_SM_CREATE_STATE(name, arch, entry, run, exit, NULL)
+
+/**
+ * @brief Define chipset level state action handlers.
+ *
+ * @param name Valid enumaration value of state.
+ *
+ * @param entry Function to be called when entrying state.
+ *
+ * @param run Function to be called when executing `run` operation.
+ *
+ * @param exit Function to be called when exiting state.
+ *
+ * @retval Defines global structure with action handlers to be used by AP
+ * power sequence state machine.
+ **/
+#define AP_POWER_CHIPSET_STATE_DEFINE(name, entry, run, exit)             \
+	AP_POWER_SM_DEF_STATE_HANDLERS(name, chipset, entry, run, exit)   \
+	const struct smf_state chipset_##name##_actions =                 \
+		AP_POWER_SM_CREATE_STATE(name, chipset, entry, run, exit, \
+					 &arch_##name##_actions)
+
+/**
+ * @brief Define application level state action handlers.
+ *
+ * @param name Valid enumaration value of state.
+ *
+ * @param entry Function to be called when entrying state.
+ *
+ * @param run Function to be called when executing `run` operation.
+ *
+ * @param exit Function to be called when exiting state.
+ *
+ * @retval Defines global structure with action handlers to be used by AP
+ * power sequence state machine.
+ **/
+#define AP_POWER_APP_STATE_DEFINE(name, entry, run, exit)                     \
+	AP_POWER_SM_DEF_STATE_HANDLERS(name, app, entry, run, exit)           \
+	const struct ap_pwrseq_smf app_state_##name = {                       \
+		.actions =                                                    \
+			AP_POWER_SM_CREATE_STATE(name, app, entry, run, exit, \
+						 &chipset_##name##_actions),  \
+		.state = name                                                 \
+	}
+
+/**
+ * @brief Define chipset level substate action handlers.
+ *
+ * @param name Valid enumaration value of state, as provided by devicetree
+ * compatible with "ap-pwrseq-sub-states".
+ *
+ * @param entry Function to be called when entrying state.
+ *
+ * @param run Function to be called when executing `run` operation.
+ *
+ * @param exit Function to be called when exiting state.
+ *
+ * @param parent Valid enumaration value of parent state,
+ *
+ * @retval Defines global structure with action handlers to be used by AP
+ * power sequence state machine.
+ **/
+#define AP_POWER_CHIPSET_SUB_STATE_DEFINE(name, entry, run, exit, parent)      \
+	AP_POWER_SM_DEF_STATE_HANDLERS(name, chipset, entry, run, exit)        \
+	const struct ap_pwrseq_smf chipset_##name##_actions = {                \
+		.actions = AP_POWER_SM_CREATE_STATE(name, chipset, entry, run, \
+						    exit,                      \
+						    &arch_##parent##_actions), \
+		.state = name                                                  \
+	}
+
+/**
+ * @brief Define application level substate action handlers.
+ *
+ * @param name Valid enumaration value of state, as provided by devicetree
+ * compatible with "ap-pwrseq-sub-states".
+ *
+ * @param entry Function to be called when entrying state.
+ *
+ * @param run Function to be called when executing `run` operation.
+ *
+ * @param exit Function to be called when exiting state.
+ *
+ * @param parent Valid enumaration value of parent state,
+ *
+ * @retval Defines global structure with action handlers to be used by AP
+ * power sequence state machine.
+ **/
+#define AP_POWER_APP_SUB_STATE_DEFINE(name, entry, run, exit, parent)          \
+	AP_POWER_SM_DEF_STATE_HANDLERS(name, app, entry, run, exit)            \
+	const struct ap_pwrseq_smf app_state_##name = {                        \
+		.actions =                                                     \
+			AP_POWER_SM_CREATE_STATE(name, app, entry, run, exit,  \
+						 &chipset_##parent##_actions), \
+		.state = name                                                  \
+	}
+
+/**
+ * @brief Sets AP power sequence state machine to provided state.
+ *
+ * This function is meant to be executed only within AP power sequence driver
+ * thread context. `tid` was given in `ap_pwrseq_sm_init`.
+ *
+ * Only one state transition is permited within `run` iterations.
+ *
+ * @param data Pointer to AP power sequence state machine instance data.
+ *
+ * @param state Enum value of next state to be executed.
+ *
+ * @retval SUCCESS Upon success, current state `exit` action handler and next
+ * state `entry` action handler will be executed.
+ * @retval -EINVAL State provided is invalid.
+ **/
+int ap_pwrseq_sm_set_state(void *const data, enum ap_pwrseq_state state);
+
+/**
+ * @brief Check if events is set for current AP power sequence state machine
+ * `run` iteration.
+ *
+ * @param data Pointer to AP power sequence state machine instance data.
+ *
+ * @param event Enum of test to be tested.
+ *
+ * @retval True If event is set, False otherwise.
+ **/
+bool ap_pwrseq_sm_is_event_set(void *const data, enum ap_pwrseq_event event);
+
+/**
+ * @brief Get state machine is entering.
+ *
+ * This function is meant to be executed only within AP power sequence driver
+ * thread context. `tid` was given in `ap_pwrseq_sm_init`.
+ *
+ * @param data Pointer to AP power sequence state machine instance data.
+ *
+ * @retval Enum value Upon success.
+ * @retval AP_POWER_STATE_UNDEF If state machine is not doing state transition.
+ **/
+enum ap_pwrseq_state ap_pwrseq_sm_get_entry_state(void *const data);
+
+/**
+ * @brief Get state machine is exiting.
+ *
+ * This function is meant to be executed only within AP power sequence driver
+ * thread context. `tid` was given in `ap_pwrseq_sm_init`.
+ *
+ * @param data Pointer to AP power sequence state machine instance data.
+ *
+ * @retval Enum value Upon success.
+ * @retval AP_POWER_STATE_UNDEF If state machine is not doing state transition.
+ **/
+enum ap_pwrseq_state ap_pwrseq_sm_get_exit_state(void *const data);
+#endif /* _AP_PWRSEQ_SM_H_ */
diff --git a/zephyr/include/ap_power/ap_pwrseq_sm_defs.h b/zephyr/include/ap_power/ap_pwrseq_sm_defs.h
new file mode 100644
index 0000000000..b34a730801
--- /dev/null
+++ b/zephyr/include/ap_power/ap_pwrseq_sm_defs.h
@@ -0,0 +1,78 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _AP_PWRSEQ_SM_DEFS_H_
+#define _AP_PWRSEQ_SM_DEFS_H_
+#include "ap_power/ap_pwrseq.h"
+
+#include <zephyr/smf.h>
+
+struct ap_pwrseq_smf {
+	/* Zephyr SMF state actions */
+	const struct smf_state actions;
+	/* Enumeration value of power state */
+	enum ap_pwrseq_state state;
+};
+
+/**
+ * Makes structures declarations of ACPI states for every level visible
+ * throughout state machine domain, definition will be completed by build system
+ * and appended to array `ap_pwrseq_states`.
+ **/
+#define AP_POWER_STATE_DECL(state)                               \
+	extern const struct smf_state arch_##state##_actions;    \
+	extern const struct smf_state chipset_##state##_actions; \
+	extern const struct ap_pwrseq_smf app_state_##name;
+
+AP_POWER_STATE_DECL(AP_POWER_STATE_G3)
+AP_POWER_STATE_DECL(AP_POWER_STATE_S5)
+AP_POWER_STATE_DECL(AP_POWER_STATE_S4)
+AP_POWER_STATE_DECL(AP_POWER_STATE_S3)
+AP_POWER_STATE_DECL(AP_POWER_STATE_S2)
+AP_POWER_STATE_DECL(AP_POWER_STATE_S1)
+AP_POWER_STATE_DECL(AP_POWER_STATE_S0)
+
+/**
+ * Makes visible `struct ap_pwrseq_smf` declarations for defined substates
+ * throughout the state machine domain, definition will be completed by build
+ * system and appended to array `ap_pwrseq_states`.
+ **/
+#define AP_PWRSEQ_CHIPSET_SUB_STATE_DECL(state, prefix) \
+	extern const struct ap_pwrseq_smf chipset_##state##_actions;
+
+#define AP_PWRSEQ_CHIPSET_SUB_STATE_DECL_(state) \
+	AP_PWRSEQ_CHIPSET_SUB_STATE_DECL(state, prefix)
+
+#define AP_PWRSEQ_CHIPSET_SUB_STATE_DECL__(node_id, prop, idx) \
+	AP_PWRSEQ_CHIPSET_SUB_STATE_DECL_(                     \
+		DT_CAT6(node_id, _P_, prop, _IDX_, idx, _STRING_UPPER_TOKEN))
+
+#define AP_PWRSEQ_EACH_CHIPSET_SUB_STATE_DECL(node_id)                      \
+	COND_CODE_1(                                                        \
+		DT_NODE_HAS_PROP(node_id, chipset),                         \
+		(DT_FOREACH_PROP_ELEM(node_id, chipset,                     \
+				      AP_PWRSEQ_CHIPSET_SUB_STATE_DECL__)), \
+		())
+
+#define AP_PWRSEQ_APP_SUB_STATE_DECL(state) \
+	extern const struct ap_pwrseq_smf app_state_##state;
+
+#define AP_PWRSEQ_APP_SUB_STATE_DECL_(state) AP_PWRSEQ_APP_SUB_STATE_DECL(state)
+
+#define AP_PWRSEQ_APP_SUB_STATE_DECL__(node_id, prop, idx) \
+	AP_PWRSEQ_APP_SUB_STATE_DECL_(                     \
+		DT_CAT6(node_id, _P_, prop, _IDX_, idx, _STRING_UPPER_TOKEN))
+
+#define AP_PWRSEQ_EACH_APP_SUB_STATE_DECL(node_id)                          \
+	COND_CODE_1(DT_NODE_HAS_PROP(node_id, application),                 \
+		    (DT_FOREACH_PROP_ELEM(node_id, application,             \
+					  AP_PWRSEQ_APP_SUB_STATE_DECL__)), \
+		    ())
+
+DT_FOREACH_STATUS_OKAY(ap_pwrseq_sub_states,
+		       AP_PWRSEQ_EACH_CHIPSET_SUB_STATE_DECL)
+DT_FOREACH_STATUS_OKAY(ap_pwrseq_sub_states, AP_PWRSEQ_EACH_APP_SUB_STATE_DECL)
+
+#endif /* _AP_PWRSEQ_SM_DEFS_H_ */
diff --git a/zephyr/include/cros/binman.dtsi b/zephyr/include/cros/binman.dtsi
new file mode 100644
index 0000000000..7fc0ebaf9a
--- /dev/null
+++ b/zephyr/include/cros/binman.dtsi
@@ -0,0 +1,59 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	binman: binman {
+		filename = "ec.bin";
+		pad-byte = <0x1d>;
+		wp-ro {
+			compatible = "cros-ec,flash-layout";
+			type = "section";
+			offset = <0x0>;
+			size = <0x40000>;
+			read-only;
+			ec-ro {
+				type = "section";
+				ro-fw {
+					type = "blob";
+					filename = "zephyr_ro.bin";
+				};
+				fmap {
+				};
+				ro-frid {
+					type = "text";
+					size = <32>;
+					text-label = "version";
+				};
+			};
+		};
+		ec-rw {
+			compatible = "cros-ec,flash-layout";
+			type = "section";
+			offset = <0x40000>;
+			size = <0x40000>;
+			rw-fw {
+				type = "section";
+				zephyr-rw {
+					type = "blob";
+					filename = "zephyr_rw.bin";
+				};
+				rw-fwid {
+					/* Fix the lcoation of the FWID to the
+					 * last 32 bytes of the flash. This
+					 * ensures the RW entries in the FMAP
+					 * stored in the RO section of flash
+					 * are always correct.
+					 */
+					offset = <(0x40000 - 32)>;
+					type = "text";
+					size = <32>;
+					text-label = "version";
+				};
+			};
+		};
+	};
+};
diff --git a/zephyr/include/cros/cbi_flash.dtsi b/zephyr/include/cros/cbi_flash.dtsi
new file mode 100644
index 0000000000..06ab7dbcba
--- /dev/null
+++ b/zephyr/include/cros/cbi_flash.dtsi
@@ -0,0 +1,17 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+&binman {
+	wp-ro {
+		cbi_flash: cbi {
+			compatible = "cros-ec,flash-layout";
+			type = "fill";
+			offset = <0x40000>;
+			size = <0>;
+			fill-byte = [ff];
+			preserve;
+		};
+	};
+};
diff --git a/zephyr/include/cros/ite/it8xxx2.dtsi b/zephyr/include/cros/ite/it8xxx2.dtsi
new file mode 100644
index 0000000000..13a9bf9bb0
--- /dev/null
+++ b/zephyr/include/cros/ite/it8xxx2.dtsi
@@ -0,0 +1,105 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <cros/binman.dtsi>
+
+/ {
+	chosen {
+		cros-ec,bbram = &bbram;
+		cros-ec,espi = &espi0;
+		cros-ec,flash = &flash0;
+		cros-ec,flash-controller = &fiu0;
+		cros-ec,raw-kb = &cros_kb_raw;
+		cros-ec,watchdog = &twd0;
+	};
+
+	named-bbram-regions {
+		compatible = "named-bbram-regions";
+
+		scratchpad {
+			offset = <0x08>;
+			size = <0x04>;
+		};
+		saved-reset-flags {
+			offset = <0x00>;
+			size = <0x04>;
+		};
+		wake {
+			offset = <0x08>;
+			size = <0x04>;
+		};
+		pd0 {
+			offset = <0x04>;
+			size = <0x01>;
+		};
+		pd1 {
+			offset = <0x05>;
+			size = <0x01>;
+		};
+		try_slot {
+			offset = <0x0e>;
+			size = <0x01>;
+		};
+		pd2 {
+			offset = <0x06>;
+			size = <0x01>;
+		};
+	};
+
+	soc {
+		fiu0: cros-flash@80000000 {
+			compatible = "ite,it8xxx2-cros-flash";
+			reg = <0x80000000 0x100000>;
+		};
+
+		cros_kb_raw: cros-kb-raw@f01d00 {
+			compatible = "ite,it8xxx2-cros-kb-raw";
+			reg = <0x00f01d00 0x29>;
+			interrupt-parent = <&intc>;
+			interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
+			wucctrl = <&wuc_wu30   /* KSI[0] */
+				   &wuc_wu31   /* KSI[1] */
+				   &wuc_wu32   /* KSI[2] */
+				   &wuc_wu33   /* KSI[3] */
+				   &wuc_wu34   /* KSI[4] */
+				   &wuc_wu35   /* KSI[5] */
+				   &wuc_wu36   /* KSI[6] */
+				   &wuc_wu37>; /* KSI[7] */
+			status = "disabled";
+		};
+	};
+
+	/* it8xxx2 has 1MB of flash. currently, we use 768KB from flash. */
+};
+
+&binman {
+	wp-ro {
+		offset = <0x0>;
+		size = <0x60000>;
+
+		pstate: pstate {
+			type = "section";
+			offset = <(0x60000 - 4096)>;
+			size = <4096>;
+		};
+	};
+	ec-rw {
+		offset = <0x60000>;
+		size = <0x60000>;
+		rw-fw {
+			rw-fwid {
+				/* Fix the lcoation of the FWID to the
+				 * last 32 bytes of the flash. This
+				 * ensures the RW entries in the FMAP
+				 * stored in the RO section of flash
+				 * are always correct.
+				 */
+				offset = <(0x60000 - 32)>;
+			};
+		};
+	};
+	pad-byte = <0xff>;
+	pad-after = <0x40000>;
+};
diff --git a/zephyr/include/cros/microchip/mec1727.dtsi b/zephyr/include/cros/microchip/mec1727.dtsi
new file mode 100644
index 0000000000..9760853596
--- /dev/null
+++ b/zephyr/include/cros/microchip/mec1727.dtsi
@@ -0,0 +1,77 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <cros/binman.dtsi>
+#include <microchip/mec1727nsz.dtsi>
+
+/ {
+	chosen {
+		cros-ec,adc = &adc0;
+		cros-ec,bbram = &bbram;
+		cros-ec,espi = &espi0;
+		cros-ec,flash = &flash1;
+		cros-ec,flash-controller = &fiu0;
+		cros-ec,raw-kb = &cros_kb_raw;
+		cros-ec,watchdog = &wdog;
+		cros,rtc = &crtc;
+	};
+
+	named-bbram-regions {
+		compatible = "named-bbram-regions";
+
+		scratchpad {
+			offset = <0x00>;
+			size = <0x04>;
+		};
+		saved-reset-flags {
+			offset = <0x04>;
+			size = <0x04>;
+		};
+		wake {
+			offset = <0x08>;
+			size = <0x04>;
+		};
+		pd0 {
+			offset = <0x0c>;
+			size = <0x01>;
+		};
+		pd1 {
+			offset = <0x0d>;
+			size = <0x01>;
+		};
+		try_slot {
+			offset = <0x0e>;
+			size = <0x01>;
+		};
+		pd2 {
+			offset = <0x0f>;
+			size = <0x01>;
+		};
+		ramlog {
+			offset = <0x20>;
+			size = <0x01>;
+		};
+		panic_flags {
+			offset = <0x23>;
+			size = <0x01>;
+		};
+		panic_bkup {
+			offset = <0x24>;
+			size = <0x1c>;
+		};
+		lct_time {
+			offset = <0x40>;
+			size = <0x04>;
+		};
+		ec_img_load {
+			offset = <0x44>;
+			size = <0x01>;
+		};
+	};
+
+	fiu0: cros-flash {
+		compatible = "microchip,xec-cros-flash";
+	};
+};
diff --git a/zephyr/include/cros/microchip/mec172x.dtsi b/zephyr/include/cros/microchip/mec172x.dtsi
new file mode 100644
index 0000000000..d47a98bd48
--- /dev/null
+++ b/zephyr/include/cros/microchip/mec172x.dtsi
@@ -0,0 +1,92 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <cros/binman.dtsi>
+#include <microchip/mec172xnsz.dtsi>
+
+/ {
+	chosen {
+		cros-ec,adc = &adc0;
+		cros-ec,bbram = &bbram;
+		cros-ec,espi = &espi0;
+		cros-ec,flash = &int_flash;
+		cros-ec,flash-controller = &fiu0;
+		cros-ec,raw-kb = &cros_kb_raw;
+		cros-ec,watchdog = &wdog;
+		cros,rtc = &crtc;
+	};
+
+	named-bbram-regions {
+		compatible = "named-bbram-regions";
+
+		scratchpad {
+			offset = <0x00>;
+			size = <0x04>;
+		};
+		saved-reset-flags {
+			offset = <0x04>;
+			size = <0x04>;
+		};
+		wake {
+			offset = <0x08>;
+			size = <0x04>;
+		};
+		pd0 {
+			offset = <0x0c>;
+			size = <0x01>;
+		};
+		pd1 {
+			offset = <0x0d>;
+			size = <0x01>;
+		};
+		try_slot {
+			offset = <0x0e>;
+			size = <0x01>;
+		};
+		pd2 {
+			offset = <0x0f>;
+			size = <0x01>;
+		};
+		ramlog {
+			offset = <0x20>;
+			size = <0x01>;
+		};
+		panic_flags {
+			offset = <0x23>;
+			size = <0x01>;
+		};
+		panic_bkup {
+			offset = <0x24>;
+			size = <0x1c>;
+		};
+		lct_time {
+			offset = <0x40>;
+			size = <0x04>;
+		};
+	};
+
+	fiu0: cros-flash {
+		compatible = "microchip,xec-cros-flash";
+	};
+
+/*
+ *	power-states {
+ *	suspend_to_idle_instant: suspend_to_idle_instant {
+ *	compatible = "zephyr,power-state";
+ *	power-state-name = "suspend-to-idle";
+ *	substate-id = <0>;
+ *	min-residency-us = <500>;
+ *	};
+ *
+ *	suspend_to_idle_normal: suspend_to_idle_normal {
+ *	compatible = "zephyr,power-state";
+ *	power-state-name = "suspend-to-idle";
+ *	substate-id = <1>;
+ *	min-residency-us = <200100>;
+ *	};
+ *	};
+ */
+};
+
diff --git a/zephyr/include/cros/nuvoton/npcx.dtsi b/zephyr/include/cros/nuvoton/npcx.dtsi
new file mode 100644
index 0000000000..017bb3b8bf
--- /dev/null
+++ b/zephyr/include/cros/nuvoton/npcx.dtsi
@@ -0,0 +1,123 @@
+/*
+ * Copyright 2021 The ChromiumOS Authors
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <cros/binman.dtsi>
+#include <nuvoton/npcx/npcx.dtsi>
+
+/ {
+	chosen {
+		cros-ec,bbram = &bbram;
+		cros-ec,espi = &espi0;
+		cros-ec,flash = &flash1;
+		cros-ec,flash-controller = &fiu0;
+		cros-ec,raw-kb = &cros_kb_raw;
+		cros-ec,watchdog = &twd0;
+	};
+
+	bbram_regions: named-bbram-regions {
+		compatible = "named-bbram-regions";
+
+		scratchpad {
+			offset = <0x00>;
+			size = <0x04>;
+		};
+		saved-reset-flags {
+			offset = <0x04>;
+			size = <0x04>;
+		};
+		wake {
+			offset = <0x08>;
+			size = <0x04>;
+		};
+		pd0 {
+			offset = <0x0c>;
+			size = <0x01>;
+		};
+		pd1 {
+			offset = <0x0d>;
+			size = <0x01>;
+		};
+		try_slot {
+			offset = <0x0e>;
+			size = <0x01>;
+		};
+		pd2 {
+			offset = <0x0f>;
+			size = <0x01>;
+		};
+		ramlog {
+			offset = <0x20>;
+			size = <0x01>;
+		};
+		panic_flags {
+			offset = <0x23>;
+			size = <0x01>;
+		};
+		panic_bkup {
+			offset = <0x24>;
+			size = <0x1c>;
+		};
+		lct_time {
+			offset = <0x40>;
+			size = <0x04>;
+		};
+	};
+
+	fiu0: cros-flash {
+		compatible = "nuvoton,npcx-cros-flash";
+	};
+
+	soc {
+
+		cros_kb_raw: cros-kb-raw@400a3000 {
+			compatible = "nuvoton,npcx-cros-kb-raw";
+			reg = <0x400a3000 0x2000>;
+			interrupts = <49 4>;
+			clocks = <&pcc NPCX_CLOCK_BUS_APB1 NPCX_PWDWN_CTL1 0>;
+			wui_maps = <&wui_io31 &wui_io30 &wui_io27 &wui_io26
+				    &wui_io25 &wui_io24 &wui_io23 &wui_io22>;
+			status = "disabled";
+		};
+
+		mtc: mtc@400b7000 {
+			compatible = "nuvoton,npcx-cros-mtc";
+			reg = <0x400b7000 0x2000>;
+			mtc-alarm = <&wui_mtc>;
+		};
+	};
+
+	power-states {
+		suspend_to_idle_instant: suspend_to_idle_instant {
+			compatible = "zephyr,power-state";
+			power-state-name = "suspend-to-idle";
+			substate-id = <0>;
+			min-residency-us = <500>;
+		};
+
+		suspend_to_idle_normal: suspend_to_idle_normal {
+			compatible = "zephyr,power-state";
+			power-state-name = "suspend-to-idle";
+			substate-id = <1>;
+			min-residency-us = <200100>;
+		};
+	};
+};
+
+&cpu0 {
+	cpu-power-states = <&suspend_to_idle_instant &suspend_to_idle_normal>;
+};
+
+&bbram {
+	status = "okay";
+};
+
+&mdc {
+	status = "okay";
+};
+
+&shi0 {
+	shi-cs-wui =<&wui_io53>;
+};
diff --git a/zephyr/include/cros/nuvoton/npcx7.dtsi b/zephyr/include/cros/nuvoton/npcx7.dtsi
new file mode 100644
index 0000000000..b1a5640f22
--- /dev/null
+++ b/zephyr/include/cros/nuvoton/npcx7.dtsi
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2021 The ChromiumOS Authors
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <cros/nuvoton/npcx.dtsi>
+
+&pinctrl {
+	/* TODO - move this upstream */
+	/omit-if-no-ref/ dbg0_gp16_17_20_22: periph-dbg0 {
+		pinmux = <&alt5_njen0_en>;
+		periph-pupd = <0x00 0>;
+	};
+	/omit-if-no-ref/ dbg1_gp16_17_20_22: periph-dbg1 {
+		pinmux = <&alt5_njen1_en>;
+		periph-pupd = <0x00 0>;
+	};
+};
+
+/ {
+
+	soc {
+
+		dbg: dbg@400c3074 {
+			compatible = "nuvoton,npcx-cros-dbg";
+			reg = <0x400c3074 0x0C>;
+			label = "DBG";
+			status = "disabled";
+		};
+	};
+
+};
diff --git a/zephyr/include/cros/nuvoton/npcx9.dtsi b/zephyr/include/cros/nuvoton/npcx9.dtsi
new file mode 100644
index 0000000000..1a993afcbc
--- /dev/null
+++ b/zephyr/include/cros/nuvoton/npcx9.dtsi
@@ -0,0 +1,17 @@
+/*
+ * Copyright 2021 The ChromiumOS Authors
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <cros/nuvoton/npcx.dtsi>
+
+/ {
+	chosen {
+		cros-ec,sha = &sha0;
+	};
+
+	soc {
+
+	};
+};
diff --git a/zephyr/include/cros/st/stm32.dtsi b/zephyr/include/cros/st/stm32.dtsi
new file mode 100644
index 0000000000..860f937caa
--- /dev/null
+++ b/zephyr/include/cros/st/stm32.dtsi
@@ -0,0 +1,51 @@
+/* Copyright 2023 The ChromiumOS Authors.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <cros/binman.dtsi>
+
+/ {
+	chosen {
+		cros-ec,bbram = &bbram;
+		cros-ec,flash = &flash0;
+		cros-ec,flash-controller = &flash_controller;
+		cros-ec,watchdog = &iwdg;
+		cros-ec,watchdog-helper = &wdg_helper;
+	};
+
+	soc {
+		flash_controller: cros-flash {
+			compatible = "cros-ec,cros-flash";
+		};
+	};
+
+	wdg_helper: counter-watchdog {
+		compatible = "zephyr,counter-watchdog";
+		status = "disable";
+	};
+
+	binman {
+		wp-ro {
+			offset = <0x0>;
+			size = <0x20000>;
+		};
+
+		ec-rw {
+			offset = <0x20000>;
+			size = <0x20000>;
+			rw-fw {
+				rw-fwid {
+					/* Fix the location of the FWID to the
+					 * last 32 bytes of the flash. This
+					 * ensures the RW entries in the FMAP
+					 * stored in the RO section of flash
+					 * are always correct.
+					 */
+					offset = <(0x20000 - 32)>;
+				};
+			};
+		};
+		pad-byte = <0xff>;
+	};
+};
diff --git a/zephyr/include/cros/thermistor/thermistor.dtsi b/zephyr/include/cros/thermistor/thermistor.dtsi
new file mode 100644
index 0000000000..42eb07f483
--- /dev/null
+++ b/zephyr/include/cros/thermistor/thermistor.dtsi
@@ -0,0 +1,470 @@
+/ {
+	/omit-if-no-ref/ thermistor_3V3_30K9_47K_4050B: thermistor-3V3-30K9-47K-4050B {
+		status = "disabled";
+		compatible = "cros-ec,thermistor";
+		scaling-factor = <11>;
+		num-pairs = <10>;
+		steinhart-reference-mv = <3300>;
+		steinhart-reference-res = <30900>;
+
+		/*
+		 * Data derived from Steinhart-Hart equation in a resistor
+		 * divider circuit with Vdd=3300mV, R = 30.9Kohm, and thermistor
+		 * (B = 4050, T0 = 298.15 K, nominal resistance (R0) = 47Kohm).
+		 */
+		sample-datum-0 {
+			milivolt = <(2753 / 11)>;
+			temp = <0>;
+			sample-index = <0>;
+		};
+		sample-datum-1 {
+			milivolt = <(2487 / 11)>;
+			temp = <10>;
+			sample-index = <1>;
+		};
+		sample-datum-2 {
+			milivolt = <(2165 / 11)>;
+			temp = <20>;
+			sample-index = <2>;
+		};
+		sample-datum-3 {
+			milivolt = <(1813 / 11)>;
+			temp = <30>;
+			sample-index = <3>;
+		};
+		sample-datum-4 {
+			milivolt = <(1145 / 11)>;
+			temp = <50>;
+			sample-index = <4>;
+		};
+		sample-datum-5 {
+			milivolt = <(878 / 11)>;
+			temp = <60>;
+			sample-index = <5>;
+		};
+		sample-datum-6 {
+			milivolt = <(665 / 11)>;
+			temp = <70>;
+			sample-index = <6>;
+		};
+		sample-datum-7 {
+			milivolt = <(500 / 11)>;
+			temp = <80>;
+			sample-index = <7>;
+		};
+		sample-datum-8 {
+			milivolt = <(375 / 11)>;
+			temp = <90>;
+			sample-index = <8>;
+		};
+		sample-datum-9 {
+			milivolt = <(282 / 11)>;
+			temp = <100>;
+			sample-index = <9>;
+		};
+	};
+
+	/omit-if-no-ref/ thermistor_3V0_22K6_47K_4050B: thermistor-3V0-22K6-47K-4050B {
+		status = "disabled";
+		compatible = "cros-ec,thermistor";
+		scaling-factor = <11>;
+		num-pairs = <13>;
+		steinhart-reference-mv = <3000>;
+		steinhart-reference-res = <22600>;
+
+		/*
+		 * Data derived from Steinhart-Hart equation in a resistor
+		 * divider circuit with Vdd=3000mV, R = 22.6Kohm, and thermistor
+		 * (B = 4050, T0 = 298.15 K, nominal resistance (R0) = 47Kohm).
+		 */
+		sample-datum-0 {
+			milivolt = <( 2619 / 11)>;
+			temp = <0>;
+			sample-index = <0>;
+		};
+		sample-datum-1 {
+			milivolt = <( 2421 / 11)>;
+			temp = <10>;
+			sample-index = <1>;
+		};
+		sample-datum-2 {
+			milivolt = <( 2168 / 11)>;
+			temp = <20>;
+			sample-index = <2>;
+		};
+		sample-datum-3 {
+			milivolt = <( 1875 / 11)>;
+			temp = <30>;
+			sample-index = <3>;
+		};
+		sample-datum-4 {
+			milivolt = <( 1563 / 11)>;
+			temp = <40>;
+			sample-index = <4>;
+		};
+		sample-datum-5 {
+			milivolt = <( 1262 / 11)>;
+			temp = <50>;
+			sample-index = <5>;
+		};
+		sample-datum-6 {
+			milivolt = <(  994 / 11)>;
+			temp = <60>;
+			sample-index = <6>;
+		};
+		sample-datum-7 {
+			milivolt = <(  769 / 11)>;
+			temp = <70>;
+			sample-index = <7>;
+		};
+		sample-datum-8 {
+			milivolt = <(  588 / 11)>;
+			temp = <80>;
+			sample-index = <8>;
+		};
+		sample-datum-9 {
+			milivolt = <(  513 / 11)>;
+			temp = <85>;
+			sample-index = <9>;
+		};
+		sample-datum-10 {
+			milivolt = <(  448 / 11)>;
+			temp = <90>;
+			sample-index = <10>;
+		};
+		sample-datum-11 {
+			milivolt = <(  390 / 11)>;
+			temp = <95>;
+			sample-index = <11>;
+		};
+		sample-datum-12 {
+			milivolt = <(  340 / 11)>;
+			temp = <100>;
+			sample-index = <12>;
+		};
+	};
+
+	/omit-if-no-ref/ thermistor_3V3_13K7_47K_4050B: thermistor-3V3-13K7-47K-4050B {
+		status = "disabled";
+		compatible = "cros-ec,thermistor";
+		scaling-factor = <13>;
+		num-pairs = <13>;
+		steinhart-reference-mv = <3300>;
+		steinhart-reference-res = <13700>;
+
+		/*
+		 * Data derived from Steinhart-Hart equation in a resistor
+		 * divider circuit with Vdd=3300mV, R = 13.7Kohm, and thermistor
+		 * (B = 4050, T0 = 298.15 K, nominal resistance (R0) = 47Kohm).
+		 */
+		sample-datum-0 {
+			milivolt = <(3033 / 13)>;
+			temp = <0>;
+			sample-index = <0>;
+		};
+		sample-datum-1 {
+			milivolt = <(2882 / 13)>;
+			temp = <10>;
+			sample-index = <1>;
+		};
+		sample-datum-2 {
+			milivolt = <(2677 / 13)>;
+			temp = <20>;
+			sample-index = <2>;
+		};
+		sample-datum-3 {
+			milivolt = <(2420 / 13)>;
+			temp = <30>;
+			sample-index = <3>;
+		};
+		sample-datum-4 {
+			milivolt = <(2119 / 13)>;
+			temp = <40>;
+			sample-index = <4>;
+		};
+		sample-datum-5 {
+			milivolt = <(1799 / 13)>;
+			temp = <50>;
+			sample-index = <5>;
+		};
+		sample-datum-6 {
+			milivolt = <(1485 / 13)>;
+			temp = <60>;
+			sample-index = <6>;
+		};
+		sample-datum-7 {
+			milivolt = <(1197 / 13)>;
+			temp = <70>;
+			sample-index = <7>;
+		};
+		sample-datum-8 {
+			milivolt = <( 947 / 13)>;
+			temp = <80>;
+			sample-index = <8>;
+		};
+		sample-datum-9 {
+			milivolt = <( 839 / 13)>;
+			temp = <85>;
+			sample-index = <9>;
+		};
+		sample-datum-10 {
+			milivolt = <( 741 / 13)>;
+			temp = <90>;
+			sample-index = <10>;
+		};
+		sample-datum-11 {
+			milivolt = <( 653 / 13)>;
+			temp = <95>;
+			sample-index = <11>;
+		};
+		sample-datum-12 {
+			milivolt = <( 576 / 13)>;
+			temp = <100>;
+			sample-index = <12>;
+		};
+	};
+
+
+	/omit-if-no-ref/ thermistor_3V3_51K1_47K_4050B: thermistor-3V3-51K1-47K-4050B {
+		status = "disabled";
+		compatible = "cros-ec,thermistor";
+		scaling-factor = <11>;
+		num-pairs = <13>;
+		steinhart-reference-mv = <3300>;
+		steinhart-reference-res = <51100>;
+
+		/*
+		 * Data derived from Steinhart-Hart equation in a resistor
+		 * divider circuit with Vdd=3300mV, R = 51.1Kohm, and thermistor
+		 * (B = 4050, T0 = 298.15 K, nominal resistance (R0) = 47Kohm).
+		 */
+		sample-datum-0 {
+			milivolt = <(2484 / 11)>;
+			temp = <0>;
+			sample-index = <0>;
+		};
+		sample-datum-1 {
+			milivolt = <(2142 / 11)>;
+			temp = <10>;
+			sample-index = <1>;
+		};
+		sample-datum-2 {
+			milivolt = <(1767 / 11)>;
+			temp = <20>;
+			sample-index = <2>;
+		};
+		sample-datum-3 {
+			milivolt = <(1400 / 11)>;
+			temp = <30>;
+			sample-index = <3>;
+		};
+		sample-datum-4 {
+			milivolt = <(1072 / 11)>;
+			temp = <40>;
+			sample-index = <4>;
+		};
+		sample-datum-5 {
+			milivolt = <( 802 / 11)>;
+			temp = <50>;
+			sample-index = <5>;
+		};
+		sample-datum-6 {
+			milivolt = <( 593 / 11)>;
+			temp = <60>;
+			sample-index = <6>;
+		};
+		sample-datum-7 {
+			milivolt = <( 436 / 11)>;
+			temp = <70>;
+			sample-index = <7>;
+		};
+		sample-datum-8 {
+			milivolt = <( 321 / 11)>;
+			temp = <80>;
+			sample-index = <8>;
+		};
+		sample-datum-9 {
+			milivolt = <( 276 / 11)>;
+			temp = <85>;
+			sample-index = <9>;
+		};
+		sample-datum-10 {
+			milivolt = <( 237 / 11)>;
+			temp = <90>;
+			sample-index = <10>;
+		};
+		sample-datum-11 {
+			milivolt = <( 204 / 11)>;
+			temp = <95>;
+			sample-index = <11>;
+		};
+		sample-datum-12 {
+			milivolt = <( 177 / 11)>;
+			temp = <100>;
+			sample-index = <12>;
+		};
+	};
+
+	/omit-if-no-ref/ thermistor_3V3_30K9_47K_NCP15WB:
+				thermistor-3V3-30K9-47K-NCP15WB {
+		status = "disabled";
+		compatible = "cros-ec,thermistor";
+		scaling-factor = <11>;
+		num-pairs = <13>;
+		steinhart-reference-mv = <3300>;
+		steinhart-reference-res = <30900>;
+
+		/*
+		 * Data derived from Steinhart-Hart equation in a resistor
+		 * divider circuit with Vdd=3300mV, R = 30.9Kohm,
+		 * and Murata NCP15WB-series thermistor
+		 * (B = 4050, T0 = 298.15 K, nominal resistance (R0) = 47Kohm).
+		 */
+		sample-datum-0 {
+			milivolt = <(2761 / 11)>;
+			temp = <0>;
+			sample-index = <0>;
+		};
+		sample-datum-1 {
+			milivolt = <(2492 / 11)>;
+			temp = <10>;
+			sample-index = <1>;
+		};
+		sample-datum-2 {
+			milivolt = <(2167 / 11)>;
+			temp = <20>;
+			sample-index = <2>;
+		};
+		sample-datum-3 {
+			milivolt = <(1812 / 11)>;
+			temp = <30>;
+			sample-index = <3>;
+		};
+		sample-datum-4 {
+			milivolt = <(1462 / 11)>;
+			temp = <40>;
+			sample-index = <4>;
+		};
+		sample-datum-5 {
+			milivolt = <(1146 / 11)>;
+			temp = <50>;
+			sample-index = <5>;
+		};
+		sample-datum-6 {
+			milivolt = <(878 / 11)>;
+			temp = <60>;
+			sample-index = <6>;
+		};
+		sample-datum-7 {
+			milivolt = <(665 / 11)>;
+			temp = <70>;
+			sample-index = <7>;
+		};
+		sample-datum-8 {
+			milivolt = <(500 / 11)>;
+			temp = <80>;
+			sample-index = <8>;
+		};
+		sample-datum-9 {
+			milivolt = <(434 / 11)>;
+			temp = <85>;
+			sample-index = <9>;
+		};
+		sample-datum-10 {
+			milivolt = <( 376 / 11)>;
+			temp = <90>;
+			sample-index = <10>;
+		};
+		sample-datum-11 {
+			milivolt = <( 326 / 11)>;
+			temp = <95>;
+			sample-index = <11>;
+		};
+		sample-datum-12 {
+			milivolt = <( 283 / 11)>;
+			temp = <100>;
+			sample-index = <12>;
+		};
+	};
+
+	/omit-if-no-ref/ thermistor_1V8_100K_100K_4250B:
+			thermistor-1V9-100K-100K-4250B {
+		status = "disabled";
+		compatible = "cros-ec,thermistor";
+		scaling-factor = <7>;
+		num-pairs = <13>;
+		steinhart-reference-mv = <1800>;
+		steinhart-reference-res = <100000>;
+
+		/*
+		 * Data derived from Steinhart-Hart equation in a resistor
+		 * divider circuit with Vdd=1800mV, R = 100Kohm, and thermistor
+		 * (B = 4250, T0 = 357 K, nominal resistance (R0) = 100Kohm).
+		 */
+		sample-datum-0 {
+			milivolt = <(1406 / 7)>;
+			temp = <0>;
+			sample-index = <0>;
+		};
+		sample-datum-1 {
+			milivolt = <(1219 / 7)>;
+			temp = <10>;
+			sample-index = <1>;
+		};
+		sample-datum-2 {
+			milivolt = <(1007 / 7)>;
+			temp = <20>;
+			sample-index = <2>;
+		};
+		sample-datum-3 {
+			milivolt = <(796 / 7)>;
+			temp = <30>;
+			sample-index = <3>;
+		};
+		sample-datum-4 {
+			milivolt = <(606 / 7)>;
+			temp = <40>;
+			sample-index = <4>;
+		};
+		sample-datum-5 {
+			milivolt = <( 449 / 7)>;
+			temp = <50>;
+			sample-index = <5>;
+		};
+		sample-datum-6 {
+			milivolt = <( 327 / 7)>;
+			temp = <60>;
+			sample-index = <6>;
+		};
+		sample-datum-7 {
+			milivolt = <( 237 / 7)>;
+			temp = <70>;
+			sample-index = <7>;
+		};
+		sample-datum-8 {
+			milivolt = <( 172 / 7)>;
+			temp = <80>;
+			sample-index = <8>;
+		};
+		sample-datum-9 {
+			milivolt = <( 147 / 7)>;
+			temp = <85>;
+			sample-index = <9>;
+		};
+		sample-datum-10 {
+			milivolt = <( 125 / 7)>;
+			temp = <90>;
+			sample-index = <10>;
+		};
+		sample-datum-11 {
+			milivolt = <( 107 / 7)>;
+			temp = <95>;
+			sample-index = <11>;
+		};
+		sample-datum-12 {
+			milivolt = <( 92 / 7)>;
+			temp = <100>;
+			sample-index = <12>;
+		};
+	};
+};
diff --git a/zephyr/include/drivers/cros_displight.h b/zephyr/include/drivers/cros_displight.h
new file mode 100644
index 0000000000..340d51f60d
--- /dev/null
+++ b/zephyr/include/drivers/cros_displight.h
@@ -0,0 +1,19 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * Set display backlight brightness
+ *
+ * @param percent Brightness in percentage
+ * @return EC_SUCCESS or EC_ERROR_*
+ */
+int displight_set(int percent);
+
+/**
+ * Get display backlight brightness
+ *
+ * @return Brightness in percentage
+ */
+int displight_get(void);
diff --git a/zephyr/include/drivers/cros_flash.h b/zephyr/include/drivers/cros_flash.h
new file mode 100644
index 0000000000..d7078cfb83
--- /dev/null
+++ b/zephyr/include/drivers/cros_flash.h
@@ -0,0 +1,319 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ * @brief Chrome OS-specific API for flash memory access
+ * This exists only support the interface expected by the Chrome OS EC. It seems
+ * better to implement this so we can make use of most of the existing code in
+ * its keyboard_scan.c file and thus make sure we operate the same way.
+ *
+ * It provides raw access to flash memory module.
+ */
+
+#ifndef ZEPHYR_INCLUDE_DRIVERS_CROS_FLASH_H_
+#define ZEPHYR_INCLUDE_DRIVERS_CROS_FLASH_H_
+
+#include <zephyr/device.h>
+#include <zephyr/kernel.h>
+
+/**
+ * @brief CROS Flash Driver APIs
+ * @defgroup cros_flash_interface CROS Flash Driver APIs
+ * @ingroup io_interfaces
+ * @{
+ */
+
+/**
+ * @cond INTERNAL_HIDDEN
+ *
+ * cros keyboard raw driver API definition and system call entry points
+ *
+ * (Internal use only.)
+ */
+typedef int (*cros_flash_api_init)(const struct device *dev);
+
+typedef int (*cros_flash_api_physical_write)(const struct device *dev,
+					     int offset, int size,
+					     const char *data);
+
+typedef int (*cros_flash_api_physical_erase)(const struct device *dev,
+					     int offset, int size);
+
+typedef int (*cros_flash_api_physical_get_protect)(const struct device *dev,
+						   int bank);
+
+typedef uint32_t (*cros_flash_api_physical_get_protect_flags)(
+	const struct device *dev);
+
+typedef int (*cros_flash_api_physical_protect_at_boot)(const struct device *dev,
+						       uint32_t new_flags);
+
+typedef int (*cros_flash_api_physical_protect_now)(const struct device *dev,
+						   int all);
+
+typedef int (*cros_flash_api_physical_get_jedec_id)(const struct device *dev,
+						    uint8_t *manufacturer,
+						    uint16_t *device);
+
+typedef int (*cros_flash_api_physical_get_status)(const struct device *dev,
+						  uint8_t *sr1, uint8_t *sr2);
+
+__subsystem struct cros_flash_driver_api {
+	cros_flash_api_init init;
+	cros_flash_api_physical_write physical_write;
+	cros_flash_api_physical_erase physical_erase;
+	cros_flash_api_physical_get_protect physical_get_protect;
+	cros_flash_api_physical_get_protect_flags physical_get_protect_flags;
+	cros_flash_api_physical_protect_at_boot physical_protect_at_boot;
+	cros_flash_api_physical_protect_now physical_protect_now;
+	cros_flash_api_physical_get_jedec_id physical_get_jedec_id;
+	cros_flash_api_physical_get_status physical_get_status;
+};
+
+/**
+ * @endcond
+ */
+
+/**
+ * @brief Initialize physical flash.
+ *
+ * @param dev Pointer to the device structure for the flash driver instance.
+ *
+ * @return 0 If successful.
+ * @retval -ENOTSUP Not supported api function.
+ */
+__syscall int cros_flash_init(const struct device *dev);
+
+static inline int z_impl_cros_flash_init(const struct device *dev)
+{
+	const struct cros_flash_driver_api *api =
+		(const struct cros_flash_driver_api *)dev->api;
+
+	if (!api->init) {
+		return -ENOTSUP;
+	}
+
+	return api->init(dev);
+}
+
+/**
+ * @brief Write to physical flash.
+ *
+ * Offset and size must be a multiple of CONFIG_FLASH_WRITE_SIZE.
+ *
+ * @param dev Pointer to the device structure for the flash driver instance.
+ * @param offset Flash offset to write.
+ * @param size Number of bytes to write.
+ * @param data Destination buffer for data.  Must be 32-bit aligned.
+ *
+ * @return 0 If successful.
+ * @retval -ENOTSUP Not supported api function.
+ */
+__syscall int cros_flash_physical_write(const struct device *dev, int offset,
+					int size, const char *data);
+
+static inline int z_impl_cros_flash_physical_write(const struct device *dev,
+						   int offset, int size,
+						   const char *data)
+{
+	const struct cros_flash_driver_api *api =
+		(const struct cros_flash_driver_api *)dev->api;
+
+	if (!api->physical_write) {
+		return -ENOTSUP;
+	}
+
+	return api->physical_write(dev, offset, size, data);
+}
+
+/**
+ * @brief Erase physical flash.
+ *
+ * Offset and size must be a multiple of CONFIG_FLASH_ERASE_SIZE.
+ *
+ * @param dev Pointer to the device structure for the flash driver instance.
+ * @param offset	Flash offset to erase.
+ * @param size	        Number of bytes to erase.
+ *
+ * @return 0 If successful.
+ * @retval -ENOTSUP Not supported api function.
+ */
+__syscall int cros_flash_physical_erase(const struct device *dev, int offset,
+					int size);
+
+static inline int z_impl_cros_flash_physical_erase(const struct device *dev,
+						   int offset, int size)
+{
+	const struct cros_flash_driver_api *api =
+		(const struct cros_flash_driver_api *)dev->api;
+
+	if (!api->physical_erase) {
+		return -ENOTSUP;
+	}
+
+	return api->physical_erase(dev, offset, size);
+}
+
+/**
+ * @brief Read physical write protect setting for a flash bank.
+ *
+ * @param dev Pointer to the device structure for the flash driver instance.
+ * @param bank	Bank index to check.
+ *
+ * @return non-zero if bank is protected until reboot.
+ * @retval -ENOTSUP Not supported api function.
+ */
+__syscall int cros_flash_physical_get_protect(const struct device *dev,
+					      int bank);
+
+static inline int
+z_impl_cros_flash_physical_get_protect(const struct device *dev, int bank)
+{
+	const struct cros_flash_driver_api *api =
+		(const struct cros_flash_driver_api *)dev->api;
+
+	if (!api->physical_get_protect) {
+		return -ENOTSUP;
+	}
+
+	return api->physical_get_protect(dev, bank);
+}
+
+/* clang-format off */
+/**
+ * @brief Return flash protect state flags from the physical layer.
+ *
+ * @param dev Pointer to the device structure for the flash driver instance.
+ *
+ * @retval -ENOTSUP Not supported api function.
+ */
+__syscall
+uint32_t cros_flash_physical_get_protect_flags(const struct device *dev);
+/* clang-format on */
+
+static inline uint32_t
+z_impl_cros_flash_physical_get_protect_flags(const struct device *dev)
+{
+	const struct cros_flash_driver_api *api =
+		(const struct cros_flash_driver_api *)dev->api;
+
+	if (!api->physical_get_protect_flags) {
+		return -ENOTSUP;
+	}
+
+	return api->physical_get_protect_flags(dev);
+}
+
+/**
+ * @brief Enable/disable protecting firmware/pstate at boot.
+ *
+ * @param dev Pointer to the device structure for the flash driver instance.
+ * @param new_flags	to protect (only EC_FLASH_PROTECT_*_AT_BOOT are
+ * taken care of)
+ *
+ * @return 0 If successful.
+ * @retval -ENOTSUP Not supported api function.
+ */
+__syscall int cros_flash_physical_protect_at_boot(const struct device *dev,
+						  uint32_t new_flags);
+
+static inline int
+z_impl_cros_flash_physical_protect_at_boot(const struct device *dev,
+					   uint32_t new_flags)
+{
+	const struct cros_flash_driver_api *api =
+		(const struct cros_flash_driver_api *)dev->api;
+
+	if (!api->physical_protect_at_boot) {
+		return -ENOTSUP;
+	}
+
+	return api->physical_protect_at_boot(dev, new_flags);
+}
+
+/**
+ * @brief Protect now physical flash.
+ *
+ * @param dev Pointer to the device structure for the flash driver instance.
+ * @param all	Protect all (=1) or just read-only and pstate (=0).
+ *
+ * @return 0 If successful.
+ * @retval -ENOTSUP Not supported api function.
+ */
+__syscall int cros_flash_physical_protect_now(const struct device *dev,
+					      int all);
+
+static inline int
+z_impl_cros_flash_physical_protect_now(const struct device *dev, int all)
+{
+	const struct cros_flash_driver_api *api =
+		(const struct cros_flash_driver_api *)dev->api;
+
+	if (!api->physical_protect_now) {
+		return -ENOTSUP;
+	}
+
+	return api->physical_protect_now(dev, all);
+}
+
+/**
+ * @brief Get JEDEC manufacturer and device identifiers.
+ *
+ * @param dev Pointer to the device structure for the flash driver instance.
+ * @param manufacturer Pointer to data where manufacturer id will be written.
+ * @param device Pointer to data where device id will be written.
+ *
+ * @return 0 If successful.
+ * @retval -ENOTSUP Not supported api function.
+ */
+__syscall int cros_flash_physical_get_jedec_id(const struct device *dev,
+					       uint8_t *manufacturer,
+					       uint16_t *device);
+
+static inline int
+z_impl_cros_flash_physical_get_jedec_id(const struct device *dev,
+					uint8_t *manufacturer, uint16_t *device)
+{
+	const struct cros_flash_driver_api *api =
+		(const struct cros_flash_driver_api *)dev->api;
+
+	if (!api->physical_get_jedec_id)
+		return -ENOTSUP;
+
+	return api->physical_get_jedec_id(dev, manufacturer, device);
+}
+
+/**
+ * @brief Get status registers.
+ *
+ * @param dev Pointer to the device structure for the flash driver instance.
+ * @param sr1 Pointer to data where status1 register will be written.
+ * @param sr2 Pointer to data where status2 register will be written.
+ *
+ * @return 0 If successful.
+ * @retval -ENOTSUP Not supported api function.
+ */
+__syscall int cros_flash_physical_get_status(const struct device *dev,
+					     uint8_t *sr1, uint8_t *sr2);
+
+static inline int
+z_impl_cros_flash_physical_get_status(const struct device *dev, uint8_t *sr1,
+				      uint8_t *sr2)
+{
+	const struct cros_flash_driver_api *api =
+		(const struct cros_flash_driver_api *)dev->api;
+
+	if (!api->physical_get_status)
+		return -ENOTSUP;
+
+	return api->physical_get_status(dev, sr1, sr2);
+}
+
+/**
+ * @}
+ */
+#include <syscalls/cros_flash.h>
+#endif /* ZEPHYR_INCLUDE_DRIVERS_CROS_FLASH_H_ */
diff --git a/zephyr/include/drivers/cros_kb_raw.h b/zephyr/include/drivers/cros_kb_raw.h
new file mode 100644
index 0000000000..5b090dcb03
--- /dev/null
+++ b/zephyr/include/drivers/cros_kb_raw.h
@@ -0,0 +1,244 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ * @brief Chrome OS-specific API for raw keyboard access
+ * This exists only support the interface expected by the Chrome OS EC. It seems
+ * better to implement this so we can make use of most of the existing code in
+ * its keyboard_scan.c file and thus make sure we operate the same way.
+ *
+ * It provides raw access to keyboard GPIOs.
+ *
+ * The keyboard matrix is read (by the caller, keyboard_scan.c in ECOS) by
+ * driving output signals on the column lines and reading the row lines.
+ *
+ * This API and any drivers should be removed once we can safely move to using
+ * the Zephyr kscan API.
+ */
+
+/*
+ * TODO(b/272518464): Work around coreboot GCC preprocessor bug.
+ * #line marks the *next* line, so it is off by one.
+ */
+#line 27
+
+#ifndef ZEPHYR_INCLUDE_DRIVERS_CROS_KB_RAW_H_
+#define ZEPHYR_INCLUDE_DRIVERS_CROS_KB_RAW_H_
+
+#include "gpio_signal.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/kernel.h>
+
+/*
+ * When CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED is enabled, the keyboard
+ * driver must drive the column 2 output to the opposite state. If the keyboard
+ * driver doesn't support push-pull operation, then the pin is set using the
+ * GPIO module. Use the presence of the alias node "gpio-kbd-kso2" to determine
+ * when this code is needed.
+ */
+#define KBD_KSO2_NODE DT_ALIAS(gpio_kbd_kso2)
+
+/**
+ * @brief CROS Keyboard Raw Driver APIs
+ * @defgroup cros_kb_raw_interface CROS Keyboard Raw Driver APIs
+ * @ingroup io_interfaces
+ * @{
+ */
+
+/**
+ * @cond INTERNAL_HIDDEN
+ *
+ * cros keyboard raw driver API definition and system call entry points
+ *
+ * (Internal use only.)
+ */
+typedef int (*cros_kb_raw_api_init)(const struct device *dev);
+
+typedef int (*cros_kb_raw_api_drive_column)(const struct device *dev, int col);
+
+typedef int (*cros_kb_raw_api_read_rows)(const struct device *dev);
+
+typedef int (*cros_kb_raw_api_enable_interrupt)(const struct device *dev,
+						int enable);
+
+typedef int (*cros_kb_raw_api_config_alt)(const struct device *dev,
+					  bool enable);
+
+__subsystem struct cros_kb_raw_driver_api {
+	cros_kb_raw_api_init init;
+	cros_kb_raw_api_drive_column drive_colum;
+	cros_kb_raw_api_read_rows read_rows;
+	cros_kb_raw_api_enable_interrupt enable_interrupt;
+#ifdef CONFIG_PLATFORM_EC_KEYBOARD_FACTORY_TEST
+	cros_kb_raw_api_config_alt config_alt;
+#endif
+};
+
+/**
+ * @endcond
+ */
+
+/**
+ * @brief Initialize the raw keyboard interface.
+ *
+ * Must be called before any other functions in this interface.
+ *
+ * @param dev Pointer to the device structure for the keyboard driver instance.
+ *
+ * @return 0 If successful.
+ * @retval -ENOTSUP Not supported api function.
+ */
+__syscall int cros_kb_raw_init(const struct device *dev);
+
+static inline int z_impl_cros_kb_raw_init(const struct device *dev)
+{
+	const struct cros_kb_raw_driver_api *api =
+		(const struct cros_kb_raw_driver_api *)dev->api;
+
+	if (!api->init) {
+		return -ENOTSUP;
+	}
+
+	return api->init(dev);
+}
+
+/**
+ * @brief Drive the specified column low.
+ *
+ * Other columns are tristated.  See enum keyboard_column_index for special
+ * values for <col>.
+ *
+ * @param dev Pointer to the device structure for the keyboard driver instance.
+ * @param col Specified column is driven to low.
+ *
+ * @return 0 If successful.
+ * @retval -ENOTSUP Not supported api function.
+ */
+__syscall int cros_kb_raw_drive_column(const struct device *dev, int col);
+static inline int z_impl_cros_kb_raw_drive_column(const struct device *dev,
+						  int col)
+{
+	const struct cros_kb_raw_driver_api *api =
+		(const struct cros_kb_raw_driver_api *)dev->api;
+
+	if (!api->drive_colum) {
+		return -ENOTSUP;
+	}
+
+	return api->drive_colum(dev, col);
+}
+
+/**
+ * @brief Read raw row state.
+ *
+ * Bits are 1 if signal is present, 0 if not present.
+ *
+ * @param dev Pointer to the device structure for the keyboard driver instance.
+ *
+ * @return current raw row state value.
+ */
+__syscall int cros_kb_raw_read_rows(const struct device *dev);
+static inline int z_impl_cros_kb_raw_read_rows(const struct device *dev)
+{
+	const struct cros_kb_raw_driver_api *api =
+		(const struct cros_kb_raw_driver_api *)dev->api;
+
+	if (!api->read_rows) {
+		return 0;
+	}
+
+	return api->read_rows(dev);
+}
+
+/**
+ * @brief Enable or disable keyboard interrupts.
+ *
+ * Enabling interrupts will clear any pending interrupt bits.  To avoid missing
+ * any interrupts that occur between the end of scanning and then, you should
+ * call cros_kb_raw_read_rows() after this.  If it returns non-zero, disable
+ * interrupts and go back to polling mode instead of waiting for an interrupt.
+ *
+ * @param dev Pointer to the device structure for the keyboard driver instance.
+ * @param enable If 1, enable keyboard interrupt. Otherwise, disable it.
+ *
+ * @return 0 If successful.
+ * @retval -ENOTSUP Not supported api function.
+ */
+__syscall int cros_kb_raw_enable_interrupt(const struct device *dev,
+					   int enable);
+
+static inline int z_impl_cros_kb_raw_enable_interrupt(const struct device *dev,
+						      int enable)
+{
+	const struct cros_kb_raw_driver_api *api =
+		(const struct cros_kb_raw_driver_api *)dev->api;
+
+	if (!api->enable_interrupt) {
+		return -ENOTSUP;
+	}
+
+	return api->enable_interrupt(dev, enable);
+}
+
+/**
+ * @brief Enable or disable keyboard alternative function.
+ *
+ * Enabling alternative function.
+ *
+ * @param dev Pointer to the device structure for the keyboard driver instance.
+ * @param enable If 1, enable keyboard function. Otherwise, disable it (as
+ * GPIO).
+ *
+ * @return 0 If successful.
+ * @retval -ENOTSUP Not supported api function.
+ */
+
+#ifdef CONFIG_PLATFORM_EC_KEYBOARD_FACTORY_TEST
+__syscall int cros_kb_raw_config_alt(const struct device *dev, bool enable);
+
+static inline int z_impl_cros_kb_raw_config_alt(const struct device *dev,
+						bool enable)
+{
+	const struct cros_kb_raw_driver_api *api =
+		(const struct cros_kb_raw_driver_api *)dev->api;
+
+	if (!api->config_alt) {
+		return -ENOTSUP;
+	}
+
+	return api->config_alt(dev, enable);
+}
+#endif
+
+/**
+ * @brief Set the logical level of the keyboard column 2 output.
+ *
+ * When CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED is enabled, the column 2
+ * output connects to the Google Security Chip and must use push-pull operation.
+ * Typically the column 2 signal is also inverted in this configuration so the
+ * board devicetree should set the GPIO_ACTIVE_LOW flag on GPIO pointed to by
+ * gpio-kbd-kso2.
+ *
+ * @param value Logical level to set to the pin
+ */
+static inline void cros_kb_raw_set_col2(int level)
+{
+#if defined CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED && \
+	DT_NODE_EXISTS(KBD_KSO2_NODE)
+	const struct gpio_dt_spec *kbd_dt_spec =
+		GPIO_DT_FROM_NODE(KBD_KSO2_NODE);
+
+	gpio_pin_set(kbd_dt_spec->port, kbd_dt_spec->pin, level);
+#endif
+}
+
+/**
+ * @}
+ */
+#include <syscalls/cros_kb_raw.h>
+#endif /* ZEPHYR_INCLUDE_DRIVERS_CROS_KB_RAW_H_ */
diff --git a/zephyr/include/drivers/cros_rtc.h b/zephyr/include/drivers/cros_rtc.h
new file mode 100644
index 0000000000..540391aac6
--- /dev/null
+++ b/zephyr/include/drivers/cros_rtc.h
@@ -0,0 +1,224 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ * @brief Chrome OS-specific API for real-time clock (RTC).
+ * This exists only support the interface expected by the Chrome OS EC. It
+ * provides raw access to RTC module.
+ *
+ * This API and any drivers should be removed once we can safely move to using
+ * the Zephyr rtc API.
+ */
+
+#ifndef ZEPHYR_INCLUDE_DRIVERS_CROS_RTC_H_
+#define ZEPHYR_INCLUDE_DRIVERS_CROS_RTC_H_
+
+#include <zephyr/device.h>
+#include <zephyr/kernel.h>
+
+/**
+ * @brief CROS Real-Time Clock (RTC) Driver APIs
+ * @defgroup cros_rtc_interface CROS RTC Driver APIs
+ * @ingroup io_interfaces
+ * @{
+ */
+
+/**
+ * @brief RTC alarm callback
+ *
+ * @param dev Pointer to the device structure for the RTC driver instance.
+ */
+typedef void (*cros_rtc_alarm_callback_t)(const struct device *dev);
+
+/**
+ * @cond INTERNAL_HIDDEN
+ *
+ * cros real-time clock driver API definition and system call entry points
+ *
+ * (Internal use only.)
+ */
+typedef int (*cros_rtc_api_configure)(const struct device *dev,
+				      cros_rtc_alarm_callback_t callback);
+
+typedef int (*cros_rtc_api_get_value)(const struct device *dev,
+				      uint32_t *value);
+
+typedef int (*cros_rtc_api_set_value)(const struct device *dev, uint32_t value);
+
+typedef int (*cros_rtc_api_get_alarm)(const struct device *dev,
+				      uint32_t *seconds,
+				      uint32_t *microseconds);
+
+typedef int (*cros_rtc_api_set_alarm)(const struct device *dev,
+				      uint32_t seconds, uint32_t microseconds);
+
+typedef int (*cros_rtc_api_reset_alarm)(const struct device *dev);
+
+__subsystem struct cros_rtc_driver_api {
+	cros_rtc_api_configure configure;
+	cros_rtc_api_get_value get_value;
+	cros_rtc_api_set_value set_value;
+	cros_rtc_api_get_alarm get_alarm;
+	cros_rtc_api_set_alarm set_alarm;
+	cros_rtc_api_reset_alarm reset_alarm;
+};
+
+/**
+ * @endcond
+ */
+
+/**
+ * @brief Configure real-time clock callback func.
+ *
+ * @param dev Pointer to the device structure for the RTC driver instance.
+ * @param callback Callback func when RTC alarm issued.
+ *
+ * @return 0 If successful.
+ * @retval -ENOTSUP Not supported api function.
+ * @retval -EINVAL Not valid callback func.
+ */
+__syscall int cros_rtc_configure(const struct device *dev,
+				 cros_rtc_alarm_callback_t callback);
+static inline int z_impl_cros_rtc_configure(const struct device *dev,
+					    cros_rtc_alarm_callback_t callback)
+{
+	const struct cros_rtc_driver_api *api =
+		(const struct cros_rtc_driver_api *)dev->api;
+
+	if (!api->configure) {
+		return -ENOTSUP;
+	}
+
+	return api->configure(dev, callback);
+}
+
+/**
+ * @brief Get the current real-time clock value.
+ *
+ * @param dev Pointer to the device structure for the RTC driver instance.
+ * @param value Pointer to the number of current real-time clock value.
+ *
+ * @return 0 If successful.
+ * @retval -ENOTSUP Not supported api function.
+ */
+__syscall int cros_rtc_get_value(const struct device *dev, uint32_t *value);
+static inline int z_impl_cros_rtc_get_value(const struct device *dev,
+					    uint32_t *value)
+{
+	const struct cros_rtc_driver_api *api =
+		(const struct cros_rtc_driver_api *)dev->api;
+
+	if (!api->get_value) {
+		return -ENOTSUP;
+	}
+
+	return api->get_value(dev, value);
+}
+
+/**
+ * @brief Set a desired value to real-time clock.
+ *
+ * @param dev Pointer to the device structure for the RTC driver instance.
+ * @param value Number of desired real-time clock value.
+ *
+ * @return 0 If successful.
+ * @retval -ENOTSUP Not supported api function.
+ */
+__syscall int cros_rtc_set_value(const struct device *dev, uint32_t value);
+static inline int z_impl_cros_rtc_set_value(const struct device *dev,
+					    uint32_t value)
+{
+	const struct cros_rtc_driver_api *api =
+		(const struct cros_rtc_driver_api *)dev->api;
+
+	if (!api->set_value) {
+		return -ENOTSUP;
+	}
+
+	return api->set_value(dev, value);
+}
+
+/**
+ * @brief Get a given time when an RTC alarm interrupt issued.
+ *
+ * @param dev Pointer to the device structure for the RTC driver instance.
+ * @param seconds Pointer to number of seconds before RTC alarm issued.
+ * @param microseconds Pointer to number of micro-secs before RTC alarm issued.
+ *
+ * @return 0 If successful.
+ * @retval -ENOTSUP Not supported api function.
+ */
+__syscall int cros_rtc_get_alarm(const struct device *dev, uint32_t *seconds,
+				 uint32_t *microseconds);
+
+static inline int z_impl_cros_rtc_get_alarm(const struct device *dev,
+					    uint32_t *seconds,
+					    uint32_t *microseconds)
+{
+	const struct cros_rtc_driver_api *api =
+		(const struct cros_rtc_driver_api *)dev->api;
+
+	if (!api->get_alarm) {
+		return 0;
+	}
+
+	return api->get_alarm(dev, seconds, microseconds);
+}
+
+/**
+ * @brief Set up an RTC alarm interrupt at a given time from now
+ *
+ * @param dev Pointer to the device structure for the RTC driver instance.
+ * @param seconds Number of seconds before RTC alarm issued.
+ * @param microseconds Number of microseconds before alarm RTC issued.
+ *
+ * @return 0 If successful.
+ * @retval -ENOTSUP Not supported api function.
+ */
+__syscall int cros_rtc_set_alarm(const struct device *dev, uint32_t seconds,
+				 uint32_t microseconds);
+
+static inline int z_impl_cros_rtc_set_alarm(const struct device *dev,
+					    uint32_t seconds,
+					    uint32_t microseconds)
+{
+	const struct cros_rtc_driver_api *api =
+		(const struct cros_rtc_driver_api *)dev->api;
+
+	if (!api->set_alarm) {
+		return 0;
+	}
+
+	return api->set_alarm(dev, seconds, microseconds);
+}
+
+/**
+ * @brief Disable and clear the RTC alarm interrupt.
+ *
+ * @param dev Pointer to the device structure for the RTC driver instance.
+ *
+ * @return 0 If successful.
+ * @retval -ENOTSUP Not supported api function.
+ */
+__syscall int cros_rtc_reset_alarm(const struct device *dev);
+
+static inline int z_impl_cros_rtc_reset_alarm(const struct device *dev)
+{
+	const struct cros_rtc_driver_api *api =
+		(const struct cros_rtc_driver_api *)dev->api;
+
+	if (!api->reset_alarm) {
+		return -ENOTSUP;
+	}
+
+	return api->reset_alarm(dev);
+}
+
+/**
+ * @}
+ */
+#include <syscalls/cros_rtc.h>
+#endif /* ZEPHYR_INCLUDE_DRIVERS_CROS_RTC_H_ */
diff --git a/zephyr/include/drivers/cros_shi.h b/zephyr/include/drivers/cros_shi.h
new file mode 100644
index 0000000000..2ec2d2233a
--- /dev/null
+++ b/zephyr/include/drivers/cros_shi.h
@@ -0,0 +1,89 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ * @brief Chrome OS-specific API for Serial Host Interface (SHI)
+ */
+
+#ifndef ZEPHYR_INCLUDE_DRIVERS_CROS_SHI_H_
+#define ZEPHYR_INCLUDE_DRIVERS_CROS_SHI_H_
+
+/**
+ * @brief CROS Serial Host Interface Driver APIs
+ * @defgroup cros_shi_interface CROS Serial Host Interface Driver APIs
+ * @ingroup io_interfaces
+ * @{
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/kernel.h>
+
+/**
+ * @cond INTERNAL_HIDDEN
+ *
+ * cros Serial Host Interface driver API definition and system call entry points
+ *
+ * (Internal use only.)
+ */
+typedef int (*cros_shi_api_enable)(const struct device *dev);
+
+typedef int (*cros_shi_api_disable)(const struct device *dev);
+
+/** @brief Driver API structure. */
+__subsystem struct cros_shi_driver_api {
+	cros_shi_api_enable enable;
+	cros_shi_api_disable disable;
+};
+
+/**
+ * @brief Enable SHI module.
+ *
+ * @param dev Pointer to the device structure for the driver instance.
+ *
+ * @retval non-negative if successful.
+ * @retval Negative errno code if failure.
+ */
+__syscall int cros_shi_enable(const struct device *dev);
+
+static inline int z_impl_cros_shi_enable(const struct device *dev)
+{
+	const struct cros_shi_driver_api *api =
+		(const struct cros_shi_driver_api *)dev->api;
+
+	if (!api->enable) {
+		return -ENOTSUP;
+	}
+
+	return api->enable(dev);
+}
+
+/**
+ * @brief Disable SHI module.
+ *
+ * @param dev Pointer to the device structure for the driver instance.
+ *
+ * @retval no return if successful.
+ * @retval Negative errno code if failure.
+ */
+__syscall int cros_shi_disable(const struct device *dev);
+
+static inline int z_impl_cros_shi_disable(const struct device *dev)
+{
+	const struct cros_shi_driver_api *api =
+		(const struct cros_shi_driver_api *)dev->api;
+
+	if (!api->disable) {
+		return -ENOTSUP;
+	}
+
+	return api->disable(dev);
+}
+
+/**
+ * @}
+ */
+#include <syscalls/cros_shi.h>
+#endif /* ZEPHYR_INCLUDE_DRIVERS_CROS_SHI_H_ */
diff --git a/zephyr/include/drivers/cros_system.h b/zephyr/include/drivers/cros_system.h
new file mode 100644
index 0000000000..c098c2cfcd
--- /dev/null
+++ b/zephyr/include/drivers/cros_system.h
@@ -0,0 +1,272 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ * @brief Public API for cros system drivers
+ */
+
+#ifndef ZEPHYR_INCLUDE_DRIVERS_CROS_SYSTEM_H_
+#define ZEPHYR_INCLUDE_DRIVERS_CROS_SYSTEM_H_
+
+/**
+ * @brief cros system Interface
+ * @defgroup cros_system_interface cros system Interface
+ * @ingroup io_interfaces
+ * @{
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/kernel.h>
+
+/**
+ * @brief system_reset_cause enum
+ * Identify the reset cause.
+ */
+enum system_reset_cause {
+	/* the reset is triggered by VCC power-up */
+	POWERUP = 0,
+	/* the reset is triggered by external VCC1 reset pin */
+	VCC1_RST_PIN = 1,
+	/* the reset is triggered by ICE debug reset request */
+	DEBUG_RST = 2,
+	/* the reset is triggered by watchdog */
+	WATCHDOG_RST = 3,
+	/* unknown reset type */
+	UNKNOWN_RST,
+};
+
+/**
+ * @brief Get a node from path '/hibernate_wakeup_pins' which has a property
+ *        'wakeup-pins' contains GPIO list for hibernate wake-up
+ *
+ * @return node identifier with that path.
+ */
+#define SYSTEM_DT_NODE_HIBERNATE_CONFIG DT_INST(0, cros_ec_hibernate_wake_pins)
+
+/**
+ * @typedef cros_system_get_reset_cause_api
+ * @brief Callback API for getting reset cause instance.
+ * See cros_system_get_reset_cause() for argument descriptions
+ */
+typedef int (*cros_system_get_reset_cause_api)(const struct device *dev);
+
+/**
+ * @typedef cros_system_soc_reset_api
+ * @brief Callback API for soc-reset instance.
+ * See cros_system_soc_reset() for argument descriptions
+ */
+typedef int (*cros_system_soc_reset_api)(const struct device *dev);
+
+/**
+ * @typedef cros_system_hibernate_api
+ * @brief Callback API for entering hibernate state (lowest EC power state).
+ * See cros_system_hibernate() for argument descriptions
+ */
+typedef int (*cros_system_hibernate_api)(const struct device *dev,
+					 uint32_t seconds,
+					 uint32_t microseconds);
+
+/**
+ * @typedef cros_system_chip_vendor_api
+ * @brief Callback API for getting the chip vendor.
+ * See cros_system_chip_vendor() for argument descriptions
+ */
+typedef const char *(*cros_system_chip_vendor_api)(const struct device *dev);
+
+/**
+ * @typedef cros_system_chip_name_api
+ * @brief Callback API for getting the chip name.
+ * See cros_system_chip_name() for argument descriptions
+ */
+typedef const char *(*cros_system_chip_name_api)(const struct device *dev);
+
+/**
+ * @typedef cros_system_chip_revision_api
+ * @brief Callback API for getting the chip revision.
+ * See cros_system_chip_revision() for argument descriptions
+ */
+typedef const char *(*cros_system_chip_revision_api)(const struct device *dev);
+
+/**
+ * @typedef cros_system_get_deep_sleep_ticks_api
+ * @brief Callback API for getting number of ticks spent in deep sleep.
+ * See cros_system_deep_sleep_ticks() for argument descriptions
+ */
+typedef uint64_t (*cros_system_deep_sleep_ticks_api)(const struct device *dev);
+
+/** @brief Driver API structure. */
+__subsystem struct cros_system_driver_api {
+	cros_system_get_reset_cause_api get_reset_cause;
+	cros_system_soc_reset_api soc_reset;
+	cros_system_hibernate_api hibernate;
+	cros_system_chip_vendor_api chip_vendor;
+	cros_system_chip_name_api chip_name;
+	cros_system_chip_revision_api chip_revision;
+	cros_system_deep_sleep_ticks_api deep_sleep_ticks;
+};
+
+/**
+ * @brief Get the chip-reset cause
+ *
+ * @param dev Pointer to the device structure for the driver instance.
+ *
+ * @retval non-negative if successful.
+ * @retval Negative errno code if failure.
+ */
+__syscall int cros_system_get_reset_cause(const struct device *dev);
+
+static inline int z_impl_cros_system_get_reset_cause(const struct device *dev)
+{
+	const struct cros_system_driver_api *api =
+		(const struct cros_system_driver_api *)dev->api;
+
+	if (!api->get_reset_cause) {
+		return -ENOTSUP;
+	}
+
+	return api->get_reset_cause(dev);
+}
+
+/**
+ * @brief reset the soc
+ *
+ * @param dev Pointer to the device structure for the driver instance.
+ *
+ * @retval no return if successful.
+ * @retval Negative errno code if failure.
+ */
+__syscall int cros_system_soc_reset(const struct device *dev);
+
+static inline int z_impl_cros_system_soc_reset(const struct device *dev)
+{
+	const struct cros_system_driver_api *api =
+		(const struct cros_system_driver_api *)dev->api;
+
+	if (!api->soc_reset) {
+		return -ENOTSUP;
+	}
+
+	return api->soc_reset(dev);
+}
+
+/**
+ * @brief put the EC in hibernate (lowest EC power state).
+ *
+ * @param dev Pointer to the device structure for the driver instance.
+ * @param seconds Number of seconds before EC enters hibernate state.
+ * @param microseconds Number of micro-secs before EC enters hibernate state.
+
+ * @retval no return if successful.
+ * @retval Negative errno code if failure.
+ */
+__syscall int cros_system_hibernate(const struct device *dev, uint32_t seconds,
+				    uint32_t microseconds);
+
+static inline int z_impl_cros_system_hibernate(const struct device *dev,
+					       uint32_t seconds,
+					       uint32_t microseconds)
+{
+	const struct cros_system_driver_api *api =
+		(const struct cros_system_driver_api *)dev->api;
+
+	if (!api->hibernate) {
+		return -ENOTSUP;
+	}
+
+	return api->hibernate(dev, seconds, microseconds);
+}
+
+/**
+ * @brief Get the chip vendor.
+ *
+ * @param dev Pointer to the device structure for the driver instance.
+ * @retval Chip vendor string if successful.
+ * @retval Null string if failure.
+ */
+__syscall const char *cros_system_chip_vendor(const struct device *dev);
+
+static inline const char *
+z_impl_cros_system_chip_vendor(const struct device *dev)
+{
+	const struct cros_system_driver_api *api =
+		(const struct cros_system_driver_api *)dev->api;
+
+	if (!api->chip_vendor) {
+		return "";
+	}
+
+	return api->chip_vendor(dev);
+}
+
+/**
+ * @brief Get the chip name.
+ *
+ * @param dev Pointer to the device structure for the driver instance.
+ * @retval Chip name string if successful.
+ * @retval Null string if failure.
+ */
+__syscall const char *cros_system_chip_name(const struct device *dev);
+
+static inline const char *z_impl_cros_system_chip_name(const struct device *dev)
+{
+	const struct cros_system_driver_api *api =
+		(const struct cros_system_driver_api *)dev->api;
+
+	if (!api->chip_name) {
+		return "";
+	}
+
+	return api->chip_name(dev);
+}
+
+/**
+ * @brief Get the chip revision.
+ *
+ * @param dev Pointer to the device structure for the driver instance.
+ * @retval Chip revision string if successful.
+ * @retval Null string if failure.
+ */
+__syscall const char *cros_system_chip_revision(const struct device *dev);
+
+static inline const char *
+z_impl_cros_system_chip_revision(const struct device *dev)
+{
+	const struct cros_system_driver_api *api =
+		(const struct cros_system_driver_api *)dev->api;
+
+	if (!api->chip_revision) {
+		return "";
+	}
+
+	return api->chip_revision(dev);
+}
+
+/**
+ * @brief Get total number of ticks spent in deep sleep.
+ *
+ * @param dev Pointer to the device structure for the driver instance.
+ * @retval Number of ticks spent in deep sleep.
+ */
+__syscall uint64_t cros_system_deep_sleep_ticks(const struct device *dev);
+
+static inline uint64_t
+z_impl_cros_system_deep_sleep_ticks(const struct device *dev)
+{
+	const struct cros_system_driver_api *api =
+		(const struct cros_system_driver_api *)dev->api;
+
+	if (!api->deep_sleep_ticks) {
+		return 0;
+	}
+
+	return api->deep_sleep_ticks(dev);
+}
+
+/**
+ * @}
+ */
+#include <syscalls/cros_system.h>
+#endif /* ZEPHYR_INCLUDE_DRIVERS_CROS_SYSTEM_H_ */
diff --git a/zephyr/include/dt-bindings/battery.h b/zephyr/include/dt-bindings/battery.h
new file mode 100644
index 0000000000..af7ee8aa11
--- /dev/null
+++ b/zephyr/include/dt-bindings/battery.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#ifndef DT_BINDINGS_BATTERY_H_
+#define DT_BINDINGS_BATTERY_H_
+
+/*
+ * Macros used by LED devicetree files (led.dts) to define battery-level
+ * range.
+ */
+#define BATTERY_LEVEL_EMPTY 0
+#define BATTERY_LEVEL_SHUTDOWN 3
+#define BATTERY_LEVEL_CRITICAL 5
+#define BATTERY_LEVEL_LOW 10
+#define BATTERY_LEVEL_FULL 100
+
+/* Battery status */
+#define SB_STATUS_FULLY_DISCHARGED BIT(4)
+#define SB_STATUS_FULLY_CHARGED BIT(5)
+#define SB_STATUS_DISCHARGING BIT(6)
+#define SB_STATUS_INITIALIZED BIT(7)
+#define SB_STATUS_REMAINING_TIME_ALARM BIT(8)
+#define SB_STATUS_REMAINING_CAPACITY_ALARM BIT(9)
+#define SB_STATUS_TERMINATE_DISCHARGE_ALARM BIT(11)
+#define SB_STATUS_OVERTEMP_ALARM BIT(12)
+#define SB_STATUS_TERMINATE_CHARGE_ALARM BIT(14)
+#define SB_STATUS_OVERCHARGED_ALARM BIT(15)
+
+#endif /* DT_BINDINGS_BATTERY_H_ */
diff --git a/zephyr/include/dt-bindings/buttons.h b/zephyr/include/dt-bindings/buttons.h
new file mode 100644
index 0000000000..47756d2284
--- /dev/null
+++ b/zephyr/include/dt-bindings/buttons.h
@@ -0,0 +1,14 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef DT_BINDINGS_BUTTON_H_
+#define DT_BINDINGS_BUTTON_H_
+
+#define BUTTON_POWER 1
+#define BUTTON_VOLUME_DOWN 2
+#define BUTTON_VOLUME_UP 3
+#define BUTTON_RECOVERY 4
+
+#endif /* DT_BINDINGS_BUTTON_H_ */
diff --git a/zephyr/include/dt-bindings/charger/intersil_isl9241.h b/zephyr/include/dt-bindings/charger/intersil_isl9241.h
new file mode 100644
index 0000000000..cbb550a5dd
--- /dev/null
+++ b/zephyr/include/dt-bindings/charger/intersil_isl9241.h
@@ -0,0 +1,18 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CHARGER_INTERSIL_ISL9241_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_CHARGER_INTERSIL_ISL9241_H_
+
+#define SWITCHING_FREQ_1420KHZ 0
+#define SWITCHING_FREQ_1180KHZ 1
+#define SWITCHING_FREQ_1020KHZ 2
+#define SWITCHING_FREQ_890KHZ 3
+#define SWITCHING_FREQ_808KHZ 4
+#define SWITCHING_FREQ_724KHZ 5
+#define SWITCHING_FREQ_656KHZ 6
+#define SWITCHING_FREQ_600KHZ 7
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CHARGER_INTERSIL_ISL9241_H_ */
diff --git a/zephyr/include/dt-bindings/gpio_defines.h b/zephyr/include/dt-bindings/gpio_defines.h
new file mode 100644
index 0000000000..16da598363
--- /dev/null
+++ b/zephyr/include/dt-bindings/gpio_defines.h
@@ -0,0 +1,152 @@
+/*
+ * Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#ifndef DT_BINDINGS_GPIO_DEFINES_H_
+#define DT_BINDINGS_GPIO_DEFINES_H_
+
+#include <zephyr/dt-bindings/gpio/gpio.h>
+
+/*
+ * The GPIO_INPUT and GPIO_OUTPUT defines are normally not available to
+ * the device tree. For GPIOs that are controlled by the platform/ec module, we
+ * allow device tree to set the initial state.
+ *
+ * Note the raw defines (e.g. GPIO_OUTPUT) in this file are copies from
+ * <drivers/gpio.h>
+ *
+ * The combined defined (e.g. GPIO_OUT_LOW) have been renamed to fit with
+ * gpio defined in platform/ec codebase.
+ */
+
+/** Enables pin as input. */
+#define GPIO_INPUT (1U << 16)
+
+/** Enables pin as output, no change to the output state. */
+#define GPIO_OUTPUT (1U << 17)
+
+/* Initializes output to a low state. */
+#define GPIO_OUTPUT_INIT_LOW (1U << 18)
+
+/* Initializes output to a high state. */
+#define GPIO_OUTPUT_INIT_HIGH (1U << 19)
+
+/* Initializes output based on logic level */
+#define GPIO_OUTPUT_INIT_LOGICAL (1U << 20)
+
+/* Configures GPIO pin as output and initializes it to a low state. */
+#define GPIO_OUTPUT_LOW (GPIO_OUTPUT | GPIO_OUTPUT_INIT_LOW)
+
+/* Configures GPIO pin as output and initializes it to a high state. */
+#define GPIO_OUTPUT_HIGH (GPIO_OUTPUT | GPIO_OUTPUT_INIT_HIGH)
+
+/* Configures GPIO pin as input with pull-up. */
+#define GPIO_INPUT_PULL_UP (GPIO_INPUT | GPIO_PULL_UP)
+
+/* Configures GPIO pin as input with pull-down. */
+#define GPIO_INPUT_PULL_DOWN (GPIO_INPUT | GPIO_PULL_DOWN)
+
+/** Configures GPIO pin as ODR output and initializes it to a low state. */
+#define GPIO_ODR_LOW (GPIO_OUTPUT_LOW | GPIO_OPEN_DRAIN)
+
+/** Configures GPIO pin as ODR output and initializes it to a high state. */
+#define GPIO_ODR_HIGH (GPIO_OUTPUT_HIGH | GPIO_OPEN_DRAIN)
+
+/*
+ * GPIO interrupt flags, taken from <drivers/gpio.h>
+ *
+ * TODO: Remove these once upstream changes to make these flags
+ * available lands.
+ */
+
+/** Disables GPIO pin interrupt. */
+#define GPIO_INT_DISABLE (1U << 21)
+
+/* Enables GPIO pin interrupt. */
+#define GPIO_INT_ENABLE (1U << 22)
+
+/* GPIO interrupt is sensitive to logical levels.
+ *
+ * This is a component flag that should be combined with other
+ * `GPIO_INT_*` flags to produce a meaningful configuration.
+ */
+#define GPIO_INT_LEVELS_LOGICAL (1U << 23)
+
+/* GPIO interrupt is edge sensitive.
+ *
+ * Note: by default interrupts are level sensitive.
+ *
+ * This is a component flag that should be combined with other
+ * `GPIO_INT_*` flags to produce a meaningful configuration.
+ */
+#define GPIO_INT_EDGE (1U << 24)
+
+/* Trigger detection when input state is (or transitions to) physical low or
+ * logical 0 level.
+ *
+ * This is a component flag that should be combined with other
+ * `GPIO_INT_*` flags to produce a meaningful configuration.
+ */
+#define GPIO_INT_LOW_0 (1U << 25)
+
+/* Trigger detection on input state is (or transitions to) physical high or
+ * logical 1 level.
+ *
+ * This is a component flag that should be combined with other
+ * `GPIO_INT_*` flags to produce a meaningful configuration.
+ */
+#define GPIO_INT_HIGH_1 (1U << 26)
+
+/** Configures GPIO interrupt to be triggered on pin rising edge and enables it.
+ */
+#define GPIO_INT_EDGE_RISING (GPIO_INT_ENABLE | GPIO_INT_EDGE | GPIO_INT_HIGH_1)
+
+/** Configures GPIO interrupt to be triggered on pin falling edge and enables
+ * it.
+ */
+#define GPIO_INT_EDGE_FALLING (GPIO_INT_ENABLE | GPIO_INT_EDGE | GPIO_INT_LOW_0)
+
+/** Configures GPIO interrupt to be triggered on pin rising or falling edge and
+ * enables it.
+ */
+#define GPIO_INT_EDGE_BOTH \
+	(GPIO_INT_ENABLE | GPIO_INT_EDGE | GPIO_INT_LOW_0 | GPIO_INT_HIGH_1)
+
+/** Configures GPIO interrupt to be triggered on pin physical level low and
+ * enables it.
+ */
+#define GPIO_INT_LEVEL_LOW (GPIO_INT_ENABLE | GPIO_INT_LOW_0)
+
+/** Configures GPIO interrupt to be triggered on pin physical level high and
+ * enables it.
+ */
+#define GPIO_INT_LEVEL_HIGH (GPIO_INT_ENABLE | GPIO_INT_HIGH_1)
+
+/** Configures GPIO interrupt to be triggered on pin state change to logical
+ * level 0 and enables it.
+ */
+#define GPIO_INT_EDGE_TO_INACTIVE                                    \
+	(GPIO_INT_ENABLE | GPIO_INT_LEVELS_LOGICAL | GPIO_INT_EDGE | \
+	 GPIO_INT_LOW_0)
+
+/** Configures GPIO interrupt to be triggered on pin state change to logical
+ * level 1 and enables it.
+ */
+#define GPIO_INT_EDGE_TO_ACTIVE                                      \
+	(GPIO_INT_ENABLE | GPIO_INT_LEVELS_LOGICAL | GPIO_INT_EDGE | \
+	 GPIO_INT_HIGH_1)
+
+/** Configures GPIO interrupt to be triggered on pin logical level 0 and enables
+ * it.
+ */
+#define GPIO_INT_LEVEL_INACTIVE \
+	(GPIO_INT_ENABLE | GPIO_INT_LEVELS_LOGICAL | GPIO_INT_LOW_0)
+
+/** Configures GPIO interrupt to be triggered on pin logical level 1 and enables
+ * it.
+ */
+#define GPIO_INT_LEVEL_ACTIVE \
+	(GPIO_INT_ENABLE | GPIO_INT_LEVELS_LOGICAL | GPIO_INT_HIGH_1)
+
+#endif /* DT_BINDINGS_GPIO_DEFINES_H_ */
diff --git a/zephyr/include/dt-bindings/motionsense/utils.h b/zephyr/include/dt-bindings/motionsense/utils.h
new file mode 100644
index 0000000000..f7a3a31927
--- /dev/null
+++ b/zephyr/include/dt-bindings/motionsense/utils.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright 2021 Google LLC.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef DT_BINDINGS_UTILS_H
+#define DT_BINDINGS_UTILS_H
+
+#define BIT(x) (1U << (x))
+#define ROUND_UP_FLAG BIT(31)
+#define USEC_PER_MSEC 1000
+
+#endif /* DT_BINDINGS_UTILS_H */
diff --git a/zephyr/include/dt-bindings/native-posix-gpio.h b/zephyr/include/dt-bindings/native-posix-gpio.h
new file mode 100644
index 0000000000..c0b8077e3d
--- /dev/null
+++ b/zephyr/include/dt-bindings/native-posix-gpio.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#ifndef DT_BINDINGS_NATIVE_POSIX_GPIO_H_
+#define DT_BINDINGS_NATIVE_POSIX_GPIO_H_
+
+/** Used for testing, bits 8-15 for specific SoC flags. */
+#define NATIVE_POSIX_GPIO_VOLTAGE_1P8 (1 << 8)
+
+#endif /* DT_BINDINGS_NATIVE_POSIX_GPIO_H_ */
diff --git a/zephyr/include/dt-bindings/usb_pd_tcpm.h b/zephyr/include/dt-bindings/usb_pd_tcpm.h
new file mode 100644
index 0000000000..93e5165140
--- /dev/null
+++ b/zephyr/include/dt-bindings/usb_pd_tcpm.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#ifndef DT_BINDINGS_USB_PD_TCPM_H_
+#define DT_BINDINGS_USB_PD_TCPM_H_
+
+#ifndef BIT
+#define BIT(n) (1U << n)
+#endif
+
+/*
+ * Macros for tcpc_config_t flags field.
+ *
+ * Bit 0 --> Polarity for TCPC alert. Set to 1 if alert is active high.
+ * Bit 1 --> Set to 1 if TCPC alert line is open-drain instead of push-pull.
+ * Bit 2 --> Polarity for TCPC reset. Set to 1 if reset line is active high.
+ * Bit 3 --> Set to 1 if TCPC is using TCPCI Revision 2.0
+ * Bit 4 --> Set to 1 if TCPC is using TCPCI Revision 2.0 but does not support
+ *           the vSafe0V bit in the EXTENDED_STATUS_REGISTER
+ * Bit 5 --> Set to 1 to prevent TCPC setting debug accessory control
+ * Bit 6 --> TCPC controls VCONN (even when CONFIG_USB_PD_TCPC_VCONN is off)
+ * Bit 7 --> TCPC controls FRS (even when CONFIG_USB_PD_FRS_TCPC is off)
+ * Bit 8 --> TCPC enable VBUS monitoring
+ */
+#define TCPC_FLAGS_ALERT_ACTIVE_HIGH BIT(0)
+#define TCPC_FLAGS_ALERT_OD BIT(1)
+#define TCPC_FLAGS_RESET_ACTIVE_HIGH BIT(2)
+#define TCPC_FLAGS_TCPCI_REV2_0 BIT(3)
+#define TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V BIT(4)
+#define TCPC_FLAGS_NO_DEBUG_ACC_CONTROL BIT(5)
+#define TCPC_FLAGS_CONTROL_VCONN BIT(6)
+#define TCPC_FLAGS_CONTROL_FRS BIT(7)
+#define TCPC_FLAGS_VBUS_MONITOR BIT(8)
+
+#endif
diff --git a/zephyr/include/dt-bindings/usbc_mux.h b/zephyr/include/dt-bindings/usbc_mux.h
new file mode 100644
index 0000000000..0c0a330fc9
--- /dev/null
+++ b/zephyr/include/dt-bindings/usbc_mux.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#ifndef DT_BINDINGS_USBC_MUX_H_
+#define DT_BINDINGS_USBC_MUX_H_
+
+#ifndef BIT
+#define BIT(n) (1U << n)
+#endif
+
+/* Flags used for cros-ec,usbc-mux flags property / struct usb_mux.flags */
+#define USB_MUX_FLAG_NOT_TCPC BIT(0) /* TCPC/MUX device used only as MUX */
+#define USB_MUX_FLAG_SET_WITHOUT_FLIP BIT(1) /* SET should not flip */
+#define USB_MUX_FLAG_RESETS_IN_G3 BIT(2) /* Mux chip will reset in G3 */
+#define USB_MUX_FLAG_POLARITY_INVERTED BIT(3) /* Mux polarity is inverted */
+#define USB_MUX_FLAG_CAN_IDLE BIT(4) /* MUX supports idle mode */
+
+#endif /* DT_BINDINGS_USBC_MUX_H_ */
diff --git a/zephyr/include/dt-bindings/wake_mask_event_defines.h b/zephyr/include/dt-bindings/wake_mask_event_defines.h
new file mode 100644
index 0000000000..f9df35701e
--- /dev/null
+++ b/zephyr/include/dt-bindings/wake_mask_event_defines.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#ifndef DT_BINDINGS_WAKE_MASK_EVENT_DEFINES_H_
+#define DT_BINDINGS_WAKE_MASK_EVENT_DEFINES_H_
+
+#ifndef BIT
+#define BIT(n) (1U << n)
+#endif
+
+/*
+ * NOTE: The convention in the Zephyr code is to have the public header file
+ * include the dt-binding header file to avoid duplicate definitions.
+ * However, ec_commands.h is shared with the linux kernel so we can't do that.
+ *
+ * Please consult include/ec_commands.h for explanations of the macros
+ * defined in this file.
+ */
+
+#define MKBP_EVENT_KEY_MATRIX BIT(0)
+#define MKBP_EVENT_HOST_EVENT BIT(1)
+#define MKBP_EVENT_SENSOR_FIFO BIT(2)
+#define MKBP_EVENT_BUTTON BIT(3)
+#define MKBP_EVENT_SWITCH BIT(4)
+#define MKBP_EVENT_FINGERPRINT BIT(5)
+#define MKBP_EVENT_SYSRQ BIT(6)
+#define MKBP_EVENT_HOST_EVENT64 BIT(7)
+#define MKBP_EVENT_CEC_EVENT BIT(8)
+#define MKBP_EVENT_CEC_MESSAGE BIT(9)
+#define MKBP_EVENT_DP_ALT_MODE_ENTERED BIT(10)
+#define MKBP_EVENT_ONLINE_CALIBRATION BIT(11)
+#define MKBP_EVENT_PCHG BIT(12)
+
+#define HOST_EVENT_NONE 0
+#define HOST_EVENT_LID_CLOSED BIT(0)
+#define HOST_EVENT_LID_OPEN BIT(1)
+#define HOST_EVENT_POWER_BUTTON BIT(2)
+#define HOST_EVENT_AC_CONNECTED BIT(3)
+#define HOST_EVENT_AC_DISCONNECTED BIT(4)
+#define HOST_EVENT_BATTERY_LOW BIT(5)
+#define HOST_EVENT_BATTERY_CRITICAL BIT(6)
+#define HOST_EVENT_BATTERY BIT(7)
+#define HOST_EVENT_THERMAL_THRESHOLD BIT(8)
+#define HOST_EVENT_DEVICE BIT(9)
+#define HOST_EVENT_THERMAL BIT(10)
+#define HOST_EVENT_USB_CHARGER BIT(11)
+#define HOST_EVENT_KEY_PRESSED BIT(12)
+#define HOST_EVENT_INTERFACE_READY BIT(13)
+#define HOST_EVENT_KEYBOARD_RECOVERY BIT(14)
+#define HOST_EVENT_THERMAL_SHUTDOWN BIT(15)
+#define HOST_EVENT_BATTERY_SHUTDOWN BIT(16)
+#define HOST_EVENT_THROTTLE_START BIT(17)
+#define HOST_EVENT_THROTTLE_STOP BIT(18)
+#define HOST_EVENT_HANG_DETECT BIT(19)
+#define HOST_EVENT_HANG_REBOOT BIT(20)
+#define HOST_EVENT_PD_MCU BIT(21)
+#define HOST_EVENT_BATTERY_STATUS BIT(22)
+#define HOST_EVENT_PANIC BIT(23)
+#define HOST_EVENT_KEYBOARD_FASTBOOT BIT(24)
+#define HOST_EVENT_RTC BIT(25)
+#define HOST_EVENT_MKBP BIT(26)
+#define HOST_EVENT_USB_MUX BIT(27)
+#define HOST_EVENT_MODE_CHANGE BIT(28)
+#define HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT BIT(29)
+#define HOST_EVENT_WOV BIT(30)
+#define HOST_EVENT_INVALID BIT(31)
+
+#endif /* DT_BINDINGS_WAKE_MASK_EVENT_DEFINES_H_ */
diff --git a/zephyr/include/emul/emul_amd_fp6.h b/zephyr/include/emul/emul_amd_fp6.h
new file mode 100644
index 0000000000..04dcd5dd31
--- /dev/null
+++ b/zephyr/include/emul/emul_amd_fp6.h
@@ -0,0 +1,41 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef EMUL_AMD_FP6_USB_MUX_H
+#define EMUL_AMD_FP6_USB_MUX_H
+
+#include <zephyr/drivers/emul.h>
+
+/**
+ * Reset the emulator's registers to their power-on value.
+ *
+ * @param emul - AMD FP6 emulator data
+ */
+void amd_fp6_emul_reset_regs(const struct emul *emul);
+
+/**
+ * Set whether the crossbar is ready to process commands.  On a real
+ * system, it is typically not ready for some time after powering on to S0.
+ *
+ * @param emul - AMD FP6 emulator data
+ * @param ready - whether the xbar should report it's ready
+ *		 (emulator init default is on)
+ */
+void amd_fp6_emul_set_xbar(const struct emul *emul, bool ready);
+
+/**
+ * Set how long a command will take to complete.  On a real system this can be
+ * anywhere from 50-100ms and the datasheet defines it can take up to 250ms.
+ *
+ * Getting timing to sync consistently in unit testing is difficult, so use the
+ * number of reads to wait instead.
+ *
+ * @param emul - AMD FP6 emulator data
+ * @param delay_reads - how long after a mux set to wait before reporting the
+ *		     status of the set as complete (in number of reads)
+ */
+void amd_fp6_emul_set_delay(const struct emul *emul, int delay_reads);
+
+#endif
diff --git a/zephyr/include/emul/emul_anx7452.h b/zephyr/include/emul/emul_anx7452.h
new file mode 100644
index 0000000000..455958f664
--- /dev/null
+++ b/zephyr/include/emul/emul_anx7452.h
@@ -0,0 +1,81 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ *
+ * @brief Backend API for ANX7452 retimer emulator
+ */
+
+#ifndef __EMUL_ANX7452_H
+#define __EMUL_ANX7452_H
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/i2c_emul.h>
+
+/** Types of "hidden" I2C devices */
+enum anx7452_emul_port {
+	TOP_EMUL_PORT,
+	CTLTOP_EMUL_PORT,
+};
+
+/**
+ * @brief ANX7452 retimer emulator backend API
+ * @defgroup anx7452_emul ANX7452 retimer emulator
+ * @{
+ *
+ * ANX7452 retimer emulator supports access to all its registers using I2C
+ * messages. Application may alter emulator state:
+ *
+ * - call @ref anx7452_emul_set_reg and @ref anx7452_emul_get_reg to set and get
+ * value of ANX7452 retimers registers
+ * - call anx7452_emul_set_err_* to change emulator behaviour on inadvisable
+ * driver behaviour
+ * - call functions from emul_common_i2c.h to setup custom handlers for I2C
+ *   messages
+ */
+
+/**
+ * @brief Set value of given register of ANX7452 retimer
+ *
+ * @param emul Pointer to ANX7452 retimer emulator
+ * @param reg Register address which value will be changed
+ * @param val New value of the register
+ */
+void anx7452_emul_set_reg(const struct emul *emul, int reg, uint8_t val);
+
+/**
+ * @brief Get value of given register of ANX7452 retimer
+ *
+ * @param emul Pointer to ANX7452 retimer emulator
+ * @param reg Register address
+ *
+ * @return Value of the register
+ */
+uint8_t anx7452_emul_get_reg(const struct emul *emul, int reg);
+
+/**
+ * @brief Reset the anx7452 emulator
+ *
+ * @param emul The emulator to reset
+ */
+void anx7452_emul_reset(const struct emul *emul);
+
+/**
+ * @brief Returns pointer to i2c_common_emul_data for given emul
+ *
+ * @param emul Pointer to anx7452 retimer emulator
+ * @return Pointer to i2c_common_emul_data for emul argument
+ */
+struct i2c_common_emul_data *
+emul_anx7452_get_i2c_common_data(const struct emul *emul,
+				 enum anx7452_emul_port port);
+
+/**
+ * @}
+ */
+
+#endif /* __EMUL_ANX7452 */
diff --git a/zephyr/include/emul/emul_bb_retimer.h b/zephyr/include/emul/emul_bb_retimer.h
new file mode 100644
index 0000000000..9db2dd565e
--- /dev/null
+++ b/zephyr/include/emul/emul_bb_retimer.h
@@ -0,0 +1,89 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ *
+ * @brief Backend API for BB retimer emulator
+ */
+
+#ifndef __EMUL_BB_RETIMER_H
+#define __EMUL_BB_RETIMER_H
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/i2c_emul.h>
+
+/**
+ * @brief BB retimer emulator backend API
+ * @defgroup bb_emul BB retimer emulator
+ * @{
+ *
+ * BB retimer emulator supports access to all its registers using I2C messages.
+ * It supports not four bytes writes by padding zeros (the same as real
+ * device), but show warning in that case.
+ * Application may alter emulator state:
+ *
+ * - define a Device Tree overlay file to set default vendor ID and which
+ *   inadvisable driver behaviour should be treated as errors
+ * - call @ref bb_emul_set_reg and @ref bb_emul_get_reg to set and get value
+ *   of BB retimers registers
+ * - call bb_emul_set_err_* to change emulator behaviour on inadvisable driver
+ *   behaviour
+ * - call functions from emul_common_i2c.h to setup custom handlers for I2C
+ *   messages
+ */
+
+/**
+ * @brief Set value of given register of BB retimer
+ *
+ * @param emul Pointer to BB retimer emulator
+ * @param reg Register address which value will be changed
+ * @param val New value of the register
+ */
+void bb_emul_set_reg(const struct emul *emul, int reg, uint32_t val);
+
+/**
+ * @brief Get value of given register of BB retimer
+ *
+ * @param emul Pointer to BB retimer emulator
+ * @param reg Register address
+ *
+ * @return Value of the register
+ */
+uint32_t bb_emul_get_reg(const struct emul *emul, int reg);
+
+/**
+ * @brief Set if error should be generated when read only register is being
+ *        written
+ *
+ * @param emul Pointer to BB retimer emulator
+ * @param set Check for this error
+ */
+void bb_emul_set_err_on_ro_write(const struct emul *emul, bool set);
+
+/**
+ * @brief Set if error should be generated when reserved bits of register are
+ *        not set to 0 on write I2C message
+ *
+ * @param emul Pointer to BB retimer emulator
+ * @param set Check for this error
+ */
+void bb_emul_set_err_on_rsvd_write(const struct emul *emul, bool set);
+
+/**
+ * @brief Returns pointer to i2c_common_emul_data for given emul
+ *
+ * @param emul Pointer to bb retimer emulator
+ * @return Pointer to i2c_common_emul_data for emul argument
+ */
+struct i2c_common_emul_data *
+emul_bb_retimer_get_i2c_common_data(const struct emul *emul);
+
+/**
+ * @}
+ */
+
+#endif /* __EMUL_BB_RETIMER */
diff --git a/zephyr/include/emul/emul_bma255.h b/zephyr/include/emul/emul_bma255.h
new file mode 100644
index 0000000000..44a56a86f7
--- /dev/null
+++ b/zephyr/include/emul/emul_bma255.h
@@ -0,0 +1,191 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ *
+ * @brief Backend API for BMA255 emulator
+ */
+
+#ifndef __EMUL_BMA255_H
+#define __EMUL_BMA255_H
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/i2c_emul.h>
+
+/**
+ * @brief BMA255 emulator backend API
+ * @defgroup bma_emul BMA255 emulator
+ * @{
+ *
+ * BMA255 emulator supports responses to all write and read I2C messages.
+ * Accelerometer registers are obtained from internal emulator state, range
+ * register and offset. Only fast compensation is supported by default handler.
+ * Registers backed in NVM are fully supported (GP0, GP1, offset). For proper
+ * support for interrupts and FIFO, user needs to use custom handlers.
+ * Application may alter emulator state:
+ *
+ * - define a Device Tree overlay file to set default NVM content, default
+ *   static accelerometer value and which inadvisable driver behaviour should
+ *   be treated as errors
+ * - call @ref bma_emul_set_reg and @ref bma_emul_get_reg to set and get value
+ *   of BMA255 registers
+ * - call @ref bma_emul_set_off and @ref bma_emul_set_off to set and get
+ *   internal offset value
+ * - call @ref bma_emul_set_acc and @ref bma_emul_set_acc to set and get
+ *   accelerometer value
+ * - call bma_emul_set_err_* to change emulator behaviour on inadvisable driver
+ *   behaviour
+ * - call functions from emul_common_i2c.h to setup custom handlers for I2C
+ *   messages
+ */
+
+/**
+ * Axis argument used in @ref bma_emul_set_acc @ref bma_emul_get_acc
+ * @ref bma_emul_set_off and @ref bma_emul_get_off
+ */
+#define BMA_EMUL_AXIS_X 0
+#define BMA_EMUL_AXIS_Y 1
+#define BMA_EMUL_AXIS_Z 2
+
+/**
+ * Acceleration 1g in internal emulator units. It is helpful for using
+ * functions @ref bma_emul_set_acc @ref bma_emul_get_acc
+ * @ref bma_emul_set_off and @ref bma_emul_get_off
+ */
+#define BMA_EMUL_1G BIT(10)
+
+/**
+ * @brief Set value of given register of BMA255
+ *
+ * @param emul Pointer to BMA255 emulator
+ * @param reg Register address which value will be changed
+ * @param val New value of the register
+ */
+void bma_emul_set_reg(const struct emul *emul, int reg, uint8_t val);
+
+/**
+ * @brief Get value of given register of BMA255
+ *
+ * @param emul Pointer to BMA255 emulator
+ * @param reg Register address
+ *
+ * @return Value of the register
+ */
+uint8_t bma_emul_get_reg(const struct emul *emul, int reg);
+
+/**
+ * @brief Get internal value of offset for given axis
+ *
+ * @param emul Pointer to BMA255 emulator
+ * @param axis Axis to access: 0 - X, 1 - Y, 2 - Z
+ *
+ * @return Offset of given axis. LSB is 0.97mg
+ */
+int16_t bma_emul_get_off(const struct emul *emul, int axis);
+
+/**
+ * @brief Set internal value of offset for given axis
+ *
+ * @param emul Pointer to BMA255 emulator
+ * @param axis Axis to access: 0 - X, 1 - Y, 2 - Z
+ * @param val New value of offset. LSB is 0.97mg
+ */
+void bma_emul_set_off(const struct emul *emul, int axis, int16_t val);
+
+/**
+ * @brief Get internal value of accelerometer for given axis
+ *
+ * @param emul Pointer to BMA255 emulator
+ * @param axis Axis to access: 0 - X, 1 - Y, 2 - Z
+ *
+ * @return Acceleration of given axis. LSB is 0.97mg
+ */
+int16_t bma_emul_get_acc(const struct emul *emul, int axis);
+
+/**
+ * @brief Set internal value of accelerometr for given axis
+ *
+ * @param emul Pointer to BMA255 emulator
+ * @param axis Axis to access: 0 - X, 1 - Y, 2 - Z
+ * @param val New value of accelerometer axis. LSB is 0.97mg
+ */
+void bma_emul_set_acc(const struct emul *emul, int axis, int16_t val);
+
+/**
+ * @brief Set if error should be generated when fast compensation is triggered
+ *        when not ready flag is set
+ *
+ * @param emul Pointer to BMA255 emulator
+ * @param set Check for this error
+ */
+void bma_emul_set_err_on_cal_nrdy(const struct emul *emul, bool set);
+
+/**
+ * @brief Set if error should be generated when fast compensation is triggered
+ *        when range is not 2G
+ *
+ * @param emul Pointer to BMA255 emulator
+ * @param set Check for this error
+ */
+void bma_emul_set_err_on_cal_bad_range(const struct emul *emul, bool set);
+
+/**
+ * @brief Set if error should be generated when read only register is being
+ *        written
+ *
+ * @param emul Pointer to BMA255 emulator
+ * @param set Check for this error
+ */
+void bma_emul_set_err_on_ro_write(const struct emul *emul, bool set);
+
+/**
+ * @brief Set if error should be generated when reserved bits of register are
+ *        not set to 0 on write I2C message
+ *
+ * @param emul Pointer to BMA255 emulator
+ * @param set Check for this error
+ */
+void bma_emul_set_err_on_rsvd_write(const struct emul *emul, bool set);
+
+/**
+ * @brief Set if error should be generated when MSB register is accessed before
+ *        LSB register
+ *
+ * @param emul Pointer to BMA255 emulator
+ * @param set Check for this error
+ */
+void bma_emul_set_err_on_msb_first(const struct emul *emul, bool set);
+
+/**
+ * @brief Function calculate register that should be accessed when I2C message
+ *        started from @p reg register and now byte number @p bytes is handled.
+ *        This function is used in I2C common emulator code and can be used in
+ *        custom user functions.
+ *
+ * @param emul Pointer to BMA255 emulator
+ * @param reg Starting register
+ * @param bytes Number of bytes already processed in the I2C message handler
+ * @param read If current I2C message is read
+ *
+ * @retval Register address that should be accessed
+ */
+int bma_emul_access_reg(const struct emul *emul, int reg, int bytes, bool read);
+
+/**
+ * @brief Returns pointer to i2c_common_emul_data for argument emul
+ *
+ * @param emul Pointer to BMA emulator
+ * @return Pointer to i2c_common_emul_data from argument emul
+ */
+struct i2c_common_emul_data *
+emul_bma_get_i2c_common_data(const struct emul *emul);
+
+/**
+ * @}
+ */
+
+#endif /* __EMUL_BMA255_H */
diff --git a/zephyr/include/emul/emul_bma4xx.h b/zephyr/include/emul/emul_bma4xx.h
new file mode 100644
index 0000000000..34cee36ecc
--- /dev/null
+++ b/zephyr/include/emul/emul_bma4xx.h
@@ -0,0 +1,79 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef ZEPHYR_INCLUDE_EMUL_EMUL_BMA4XX_H_
+#define ZEPHYR_INCLUDE_EMUL_EMUL_BMA4XX_H_
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/i2c_emul.h>
+
+/** Reset the state of the provided bma4xx emulator. */
+void bma4xx_emul_reset(const struct emul *emul);
+
+/** Get the I2C interface emulator used by this emulator. */
+struct i2c_common_emul_data *bma4xx_emul_get_i2c(const struct emul *emul);
+
+/** Get the motion_sensor_t associated with this emulator. */
+struct motion_sensor_t *bma4xx_emul_get_sensor_data(const struct emul *emul);
+
+/**
+ * Get the sensor ID (index into the motion_sensors array) for the
+ * motion_sensor_t associated with this emulator.
+ */
+int bma4xx_emul_get_sensor_num(const struct emul *emul);
+
+/** Return whether the accelerometer is enabled (currently sensing). */
+bool bma4xx_emul_is_accel_enabled(const struct emul *emul);
+
+/** Set whether the accelerometer is enabled (currently sensing). */
+void bma4xx_emul_set_accel_enabled(const struct emul *emul, bool enabled);
+
+/** Get the sensor's current sensing range, as a positive integer in gs. */
+uint8_t bma4xx_emul_get_accel_range(const struct emul *emul);
+
+/** Get the sensor's current output data rate, in milliHz. */
+uint32_t bma4xx_emul_get_odr(const struct emul *emul);
+
+/** Set the sensor's current acceleration reading, in milli-g on each axis. */
+void bma4xx_emul_set_accel_data(const struct emul *emul, int x, int y, int z);
+
+/** Get the current offset register values, XYZ. */
+void bma4xx_emul_get_offset(const struct emul *emul, int8_t (*offset)[3]);
+
+/** Return the current value of the NV_CONF register. */
+uint8_t bma4xx_emul_get_nv_conf(const struct emul *emul);
+
+/**
+ * Return true if the FIFO is enabled.
+ *
+ * Only headerless mode with accel data only is supported, so when this is true
+ * it also implies that bits of FIFO_CONFIG_1 other than fifo_acc_en are clear.
+ */
+bool bma4xx_emul_is_fifo_enabled(const struct emul *emul);
+
+/** Queue data with provided size to be read from the FIFO. */
+void bma4xx_emul_set_fifo_data(const struct emul *emul,
+			       const uint8_t *fifo_data, uint16_t data_sz);
+/**
+ * Return the current interrupt configuration.
+ *
+ * Provided pointers are out-parameters for the INT1_IO_CTRL register and
+ * whether interrupts are in latched mode. The return value is the current value
+ * of the INT_MAP_DATA register.
+ */
+uint8_t bma4xx_emul_get_interrupt_config(const struct emul *emul,
+					 uint8_t *int1_io_ctrl,
+					 bool *latched_mode);
+
+/**
+ * Return a pointer to the i2c_common_emul_data for an emulator instance.
+ *
+ * This allows users to override the I2C behavior, such as to cause
+ * communication errors or inspect the data being passed across the bus.
+ */
+struct i2c_common_emul_data *
+emul_bma4xx_get_i2c_common_data(const struct emul *emul);
+
+#endif /* ZEPHYR_INCLUDE_EMUL_EMUL_BMA4XX_H_ */
diff --git a/zephyr/include/emul/emul_bmi.h b/zephyr/include/emul/emul_bmi.h
new file mode 100644
index 0000000000..c7a07ba4bf
--- /dev/null
+++ b/zephyr/include/emul/emul_bmi.h
@@ -0,0 +1,444 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ *
+ * @brief Backend API for BMI emulator
+ */
+
+#ifndef __EMUL_BMI_H
+#define __EMUL_BMI_H
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/i2c_emul.h>
+
+/**
+ * @brief BMI emulator backend API
+ * @defgroup bmi_emul BMI emulator
+ * @{
+ *
+ * BMI emulator supports responses to all write and read I2C messages.
+ * Accelerometer and gyroscope registers are obtained from internal emulator
+ * state, range register and offset. FIFO is fully simulated. Emulator can be
+ * extended to support more models of BMI.
+ * Application may alter emulator state:
+ *
+ * - define a Device Tree overlay file to set which inadvisable driver behaviour
+ *   should be treated as errors and which model is emulated
+ * - call @ref bmi_emul_set_reg and @ref bmi_emul_get_reg to set and get value
+ *   of BMI registers
+ * - call @ref bmi_emul_set_off and @ref bmi_emul_get_off to set and get
+ *   internal offset value
+ * - call @ref bmi_emul_set_value and @ref bmi_emul_get_value to set and get
+ *   accelerometer or gyroscope value
+ * - call bmi_emul_set_err_* to change emulator behaviour on inadvisable driver
+ *   behaviour
+ * - call @ref bmi_emul_simulate_cmd_exec_time to enable or disable simulation
+ *   of command execution time
+ * - call @ref bmi_emul_append_frame to add frame to FIFO
+ * - call @reg bmi_emul_set_skipped_frames to generate skip frame on next access
+ *   to FIFO
+ * - call functions from emul_common_i2c.h to setup custom handlers for I2C
+ *   messages
+ */
+
+/**
+ * Axis argument used in @ref bmi_emul_set_value @ref bmi_emul_get_value
+ * @ref bmi_emul_set_off and @ref bmi_emul_get_off
+ */
+enum bmi_emul_axis {
+	BMI_EMUL_ACC_X,
+	BMI_EMUL_ACC_Y,
+	BMI_EMUL_ACC_Z,
+	BMI_EMUL_GYR_X,
+	BMI_EMUL_GYR_Y,
+	BMI_EMUL_GYR_Z,
+};
+
+/** BMI emulator models */
+#define BMI_EMUL_160 1
+#define BMI_EMUL_260 2
+
+/** Last register supported by emulator */
+#define BMI_EMUL_MAX_REG 0x80
+/** Maximum number of registers that can be backed in NVM */
+#define BMI_EMUL_MAX_NVM_REGS 10
+
+/** Headers used in FIFO frames */
+#define BMI_EMUL_FIFO_HEAD_SKIP 0x40
+#define BMI_EMUL_FIFO_HEAD_TIME 0x44
+#define BMI_EMUL_FIFO_HEAD_CONFIG 0x48
+#define BMI_EMUL_FIFO_HEAD_EMPTY 0x80
+#define BMI_EMUL_FIFO_HEAD_DATA 0x80
+#define BMI_EMUL_FIFO_HEAD_DATA_MAG BIT(4)
+#define BMI_EMUL_FIFO_HEAD_DATA_GYR BIT(3)
+#define BMI_EMUL_FIFO_HEAD_DATA_ACC BIT(2)
+#define BMI_EMUL_FIFO_HEAD_DATA_TAG_MASK 0x03
+
+/**
+ * Acceleration 1g in internal emulator units. It is helpful for using
+ * functions @ref bmi_emul_set_value @ref bmi_emul_get_value
+ * @ref bmi_emul_set_off and @ref bmi_emul_get_off
+ */
+#define BMI_EMUL_1G BIT(14)
+/**
+ * Gyroscope 125°/s in internal emulator units. It is helpful for using
+ * functions @ref bmi_emul_set_value @ref bmi_emul_get_value
+ * @ref bmi_emul_set_off and @ref bmi_emul_get_off
+ */
+#define BMI_EMUL_125_DEG_S BIT(15)
+
+/** Type of frames that can be added to the emulator frames list */
+#define BMI_EMUL_FRAME_CONFIG BIT(0)
+#define BMI_EMUL_FRAME_ACC BIT(1)
+#define BMI_EMUL_FRAME_MAG BIT(2)
+#define BMI_EMUL_FRAME_GYR BIT(3)
+
+/**
+ * Code returned by model specific handle_read and handle_write functions, when
+ * RO register is accessed on write or WO register is accessed on read
+ */
+#define BMI_EMUL_ACCESS_E 1
+
+/** Structure used to describe single FIFO frame */
+struct bmi_emul_frame {
+	/** Type of frame */
+	uint8_t type;
+	/** Tag added to data frame */
+	uint8_t tag;
+	/** Value used in config frame */
+	uint8_t config;
+	/** Accelerometer sensor values in internal emulator units */
+	int32_t acc_x;
+	int32_t acc_y;
+	int32_t acc_z;
+	/** Gyroscope sensor values in internal emulator units */
+	int32_t gyr_x;
+	int32_t gyr_y;
+	int32_t gyr_z;
+	/** Magnetometer/other sensor values in internal emulator units */
+	int32_t mag_x;
+	int32_t mag_y;
+	int32_t mag_z;
+	int32_t rhall;
+
+	/** Pointer to next frame or NULL */
+	struct bmi_emul_frame *next;
+};
+
+/** Structure describing specific BMI model */
+struct bmi_emul_type_data {
+	/** Indicate if time frame should follow config frame */
+	bool sensortime_follow_config_frame;
+
+	/**
+	 * @brief Compute register address that acctually will be accessed, when
+	 *        selected register is @p reg and there was @p byte handled in
+	 *        the current I2C message
+	 *
+	 * @param emul Pointer to BMI emulator
+	 * @param reg Selected register
+	 * @param byte Number of handled bytes in the current I2C message
+	 * @param read If current I2C message is read
+	 *
+	 * @return Register address that will be accessed
+	 */
+	int (*access_reg)(const struct emul *emul, int reg, int byte,
+			  bool read);
+
+	/**
+	 * @brief Model specific write function. It should modify state of
+	 *        emulator if required.
+	 *
+	 * @param regs Pointer to array of emulator's registers
+	 * @param emul Pointer to BMI emulator
+	 * @param reg Selected register
+	 * @param byte Number of handled bytes in this write command
+	 * @param val Value that is being written
+	 *
+	 * @return 0 on success
+	 * @return BMI_EMUL_ACCESS_E on RO register access
+	 * @return other on error
+	 */
+	int (*handle_write)(uint8_t *regs, const struct emul *emul, int reg,
+			    int byte, uint8_t val);
+	/**
+	 * @brief Model specific read function. It should modify state of
+	 *        emulator if required. @p buf should be set to response value.
+	 *
+	 * @param regs Pointer to array of emulator's registers
+	 * @param emul Pointer to BMI emulator
+	 * @param reg Selected register
+	 * @param byte Byte which is accessed during block read
+	 * @param buf Pointer where read byte should be stored
+	 *
+	 * @return 0 on success
+	 * @return BMI_EMUL_ACCESS_E on WO register access
+	 * @return other on error
+	 */
+	int (*handle_read)(uint8_t *regs, const struct emul *emul, int reg,
+			   int byte, char *buf);
+	/**
+	 * @brief Model specific finish read function. It should modify state of
+	 *        emulator if required.
+	 *
+	 * @param regs Pointer to array of emulator's registers
+	 * @param emul Pointer to BMI emulator
+	 * @param reg Selected register
+	 * @param bytes Number of bytes read
+	 *
+	 * @return 0 on success
+	 */
+	int (*finish_read)(uint8_t *regs, const struct emul *emul, int reg,
+			   int bytes);
+	/**
+	 * @brief Model specific reset function. It should modify state of
+	 *        emulator to imitate after reset conditions.
+	 *
+	 * @param regs Pointer to array of emulator's registers
+	 * @param emul Pointer to BMI emulator
+	 */
+	void (*reset)(uint8_t *regs, const struct emul *emul);
+
+	/** Array of reserved bits mask for each register */
+	const uint8_t *rsvd_mask;
+
+	/** Array of registers that are backed in NVM */
+	const int *nvm_reg;
+	/** Number of registers backed in NVM */
+	int nvm_len;
+
+	/** Gyroscope X axis register */
+	int gyr_off_reg;
+	/** Accelerometer X axis register */
+	int acc_off_reg;
+	/** Gyroscope 9 and 8 bits register */
+	int gyr98_off_reg;
+};
+
+/**
+ * @brief Get BMI160 model specific structure.
+ *
+ * @return Pointer to BMI160 specific structure
+ */
+const struct bmi_emul_type_data *get_bmi160_emul_type_data(void);
+/**
+ * @brief Get BMI260 model specific structure.
+ *
+ * @return Pointer to BMI260 specific structure
+ */
+const struct bmi_emul_type_data *get_bmi260_emul_type_data(void);
+
+/**
+ * @brief Set value of given register of BMI
+ *
+ * @param emul Pointer to BMI emulator
+ * @param reg Register address which value will be changed
+ * @param val New value of the register
+ */
+void bmi_emul_set_reg(const struct emul *emul, int reg, uint8_t val);
+
+/**
+ * @brief Get value of given register of BMI
+ *
+ * @param emul Pointer to BMI emulator
+ * @param reg Register address
+ *
+ * @return Value of the register
+ */
+uint8_t bmi_emul_get_reg(const struct emul *emul, int reg);
+
+/**
+ * @brief Get internal value of offset for given axis and sensor
+ *
+ * @param emul Pointer to BMI emulator
+ * @param axis Axis to access
+ *
+ * @return Offset of given axis. LSB for accelerometer is 0.061mg and for
+ *         gyroscope is 0.0037°/s.
+ */
+int16_t bmi_emul_get_off(const struct emul *emul, enum bmi_emul_axis axis);
+
+/**
+ * @brief Set internal value of offset for given axis and sensor
+ *
+ * @param emul Pointer to BMI emulator
+ * @param axis Axis to access
+ * @param val New value of given axis. LSB for accelerometer is 0.061mg and for
+ *            gyroscope is 0.0037°/s.
+ */
+void bmi_emul_set_off(const struct emul *emul, enum bmi_emul_axis axis,
+		      int16_t val);
+
+/**
+ * @brief Get internal value of sensor for given axis
+ *
+ * @param emul Pointer to BMI emulator
+ * @param axis Axis to access
+ *
+ * @return Sensor value of given axis. LSB for accelerometer is 0.061mg and for
+ *         gyroscope is 0.0037°/s.
+ */
+int32_t bmi_emul_get_value(const struct emul *emul, enum bmi_emul_axis axis);
+
+/**
+ * @brief Set internal value of sensor for given axis
+ *
+ * @param emul Pointer to BMI emulator
+ * @param axis Axis to access
+ * @param val New value of given axis. LSB for accelerometer is 0.061mg and for
+ *            gyroscope is 0.0037°/s.
+ */
+void bmi_emul_set_value(const struct emul *emul, enum bmi_emul_axis axis,
+			int32_t val);
+
+/**
+ * @brief Set if error should be generated when read only register is being
+ *        written
+ *
+ * @param emul Pointer to BMI emulator
+ * @param set Check for this error
+ */
+void bmi_emul_set_err_on_ro_write(const struct emul *emul, bool set);
+
+/**
+ * @brief Set if error should be generated when reserved bits of register are
+ *        not set to 0 on write I2C message
+ *
+ * @param emul Pointer to BMI emulator
+ * @param set Check for this error
+ */
+void bmi_emul_set_err_on_rsvd_write(const struct emul *emul, bool set);
+
+/**
+ * @brief Set if error should be generated when write only register is read
+ *
+ * @param emul Pointer to BMI emulator
+ * @param set Check for this error
+ */
+void bmi_emul_set_err_on_wo_read(const struct emul *emul, bool set);
+
+/**
+ * @brief Set if effect of simulated command should take place after simulated
+ *        time pass from issuing command.
+ *
+ * @param emul Pointer to BMI emulator
+ * @param set Simulate command execution time
+ */
+void bmi_emul_simulate_cmd_exec_time(const struct emul *emul, bool set);
+
+/**
+ * @brief Set number of skipped frames. It will generate skip frame on next
+ *        access to FIFO. After that number of skipped frames is reset to 0.
+ *
+ * @param emul Pointer to BMI emulator
+ * @param skip Number of skipped frames
+ */
+void bmi_emul_set_skipped_frames(const struct emul *emul, uint8_t skip);
+
+/**
+ * @brief Clear all FIFO frames, set current frame to empty and reset fifo_skip
+ *        counter
+ *
+ * @param emul Pointer to BMI emulator
+ * @param tag_time Indicate if sensor time should be included in empty frame
+ * @param header Indicate if header should be included in frame
+ */
+void bmi_emul_flush_fifo(const struct emul *emul, bool tag_time, bool header);
+
+/**
+ * @brief Restore registers backed by NVM, reset sensor time and flush FIFO
+ *
+ * @param emul Pointer to BMI emulator
+ */
+void bmi_emul_reset_common(const struct emul *emul, bool tag_time, bool header);
+
+/**
+ * @brief Set command end time to @p time ms from now
+ *
+ * @param emul Pointer to BMI emulator
+ * @param time After this amount of ms command should end
+ */
+void bmi_emul_set_cmd_end_time(const struct emul *emul, int time);
+
+/**
+ * @brief Check if command should end
+ *
+ * @param emul Pointer to BMI emulator
+ */
+bool bmi_emul_is_cmd_end(const struct emul *emul);
+
+/**
+ * @brief Append FIFO @p frame to the emulator list of frames. It can be read
+ *        using I2C interface.
+ *
+ * @param emul Pointer to BMI emulator
+ * @param frame Pointer to new FIFO frame. Pointed data has to be valid while
+ *              emulator may use this frame (until flush of FIFO or reading
+ *              it out through I2C)
+ */
+void bmi_emul_append_frame(const struct emul *emul,
+			   struct bmi_emul_frame *frame);
+
+/**
+ * @brief Get length of all frames that are on the emulator list of frames.
+ *
+ * @param emul Pointer to BMI emulator
+ * @param tag_time Indicate if sensor time should be included in empty frame
+ * @param header Indicate if header should be included in frame
+ */
+uint16_t bmi_emul_fifo_len(const struct emul *emul, bool tag_time, bool header);
+
+/**
+ * @brief Get next byte that should be returned on FIFO data access.
+ *
+ * @param emul Pointer to BMI emulator
+ * @param byte Which byte of block read command is currently handled
+ * @param tag_time Indicate if sensor time should be included in empty frame
+ * @param header Indicate if header should be included in frame
+ * @param acc_shift How many bits should be right shifted from accelerometer
+ *                  data
+ * @param gyr_shift How many bits should be right shifted from gyroscope data
+ *
+ * @return FIFO data byte
+ */
+uint8_t bmi_emul_get_fifo_data(const struct emul *emul, int byte, bool tag_time,
+			       bool header, int acc_shift, int gyr_shift);
+
+/**
+ * @brief Saves current internal state of sensors to emulator's registers.
+ *
+ * @param emul Pointer to BMI emulator
+ * @param acc_shift How many bits should be right shifted from accelerometer
+ *                  data
+ * @param gyr_shift How many bits should be right shifted from gyroscope data
+ * @param acc_reg Register which holds LSB of accelerometer sensor
+ * @param gyr_reg Register which holds LSB of gyroscope sensor
+ * @param sensortime_reg Register which holds LSB of sensor time
+ * @param acc_off_en Indicate if accelerometer offset should be included to
+ *                   sensor data value
+ * @param gyr_off_en Indicate if gyroscope offset should be included to
+ *                   sensor data value
+ */
+void bmi_emul_state_to_reg(const struct emul *emul, int acc_shift,
+			   int gyr_shift, int acc_reg, int gyr_reg,
+			   int sensortime_reg, bool acc_off_en,
+			   bool gyr_off_en);
+/**
+ * @brief Returns pointer to i2c_common_emul_data for given emul
+ *
+ * @param emul Pointer to BMI emulator
+ * @return Pointer to i2c_common_emul_data for emul argument
+ */
+struct i2c_common_emul_data *
+emul_bmi_get_i2c_common_data(const struct emul *emul);
+
+/**
+ * @}
+ */
+
+#endif /* __EMUL_BMI_H */
diff --git a/zephyr/include/emul/emul_clock_control.h b/zephyr/include/emul/emul_clock_control.h
new file mode 100644
index 0000000000..716bec5655
--- /dev/null
+++ b/zephyr/include/emul/emul_clock_control.h
@@ -0,0 +1,9 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef ZEPHYR_INCLUDE_EMUL_EMUL_CLOCK_CONTROL_H_
+#define ZEPHYR_INCLUDE_EMUL_EMUL_CLOCK_CONTROL_H_
+
+#endif /* ZEPHYR_INCLUDE_EMUL_EMUL_CLOCK_CONTROL_H_ */
diff --git a/zephyr/include/emul/emul_common_i2c.h b/zephyr/include/emul/emul_common_i2c.h
new file mode 100644
index 0000000000..1388e9bbcb
--- /dev/null
+++ b/zephyr/include/emul/emul_common_i2c.h
@@ -0,0 +1,381 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ *
+ * @brief Common code used by devices emulated on I2C bus
+ */
+
+#ifndef __EMUL_COMMON_I2C_H
+#define __EMUL_COMMON_I2C_H
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/i2c_emul.h>
+
+/**
+ * @brief Common I2C API useb by emulators
+ * @defgroup i2c_common_emul common I2C emulator's code
+ * @{
+ *
+ * I2C common emulator functionality is dispatching I2C messages. It supports
+ * setting custom user handler and selecting register on which access emulator
+ * should fail. To use common I2C handling, emulator should call or setup
+ * @ref i2c_common_emul_transfer as transfer callback of i2c_emul_api and
+ * register emulator with @ref i2c_common_emul_data structure as data. In data
+ * structure, emualtor should set callback called before read/write I2C message
+ * (start_read, start_write), for each byte of I2C message (read_byte,
+ * write_byte) and after I2C message (finish_read, finish_byte). If specific
+ * function is not needed by emulator, than it can be set to NULL.
+ *
+ * @ref i2c_common_emul_lock_data and @ref i2c_common_emul_unlock_data functions
+ * may be used to guard emulator data when accessed from multiple threads.
+ *
+ * User of emulator with common I2C code can use following API to define custom
+ * behaviour of emulator:
+ *
+ * - call @ref i2c_common_emul_set_read_func and
+ *   @ref i2c_common_emul_set_write_func to setup custom handlers for I2C
+ *   messages
+ * - call @ref i2c_common_emul_set_read_fail_reg and
+ *   @ref i2c_common_emul_set_write_fail_reg to configure emulator to fail on
+ *   given register read or write
+ */
+
+/**
+ * Special register values used in @ref i2c_common_emul_set_read_fail_reg and
+ * @ref i2c_common_emul_set_write_fail_reg
+ */
+#define I2C_COMMON_EMUL_FAIL_ALL_REG (-1)
+#define I2C_COMMON_EMUL_NO_FAIL_REG (-2)
+
+/**
+ * Describe if there is no ongoing I2C message or if there is message handled
+ * at the moment (last message doesn't ended with stop or write is not followed
+ * by read).
+ */
+enum i2c_common_emul_msg_state {
+	I2C_COMMON_EMUL_NONE_MSG,
+	I2C_COMMON_EMUL_IN_WRITE,
+	I2C_COMMON_EMUL_IN_READ
+};
+
+/**
+ * @brief Function type that is used by I2C device emulator for first byte of
+ *        I2C write message.
+ *
+ * @param target Pointer to emulator
+ * @param reg Address which is now accessed by write command (first byte of I2C
+ *            write message)
+ *
+ * @return 0 on success
+ * @return -EIO on error
+ */
+typedef int (*i2c_common_emul_start_write_func)(const struct emul *target,
+						int reg);
+
+/**
+ * @brief Function type that is used by I2C device emulator at the end of
+ *        I2C write message.
+ *
+ * @param target Pointer to emulator
+ * @param reg Address which is now accessed by write command (first byte of I2C
+ *            write message)
+ * @param bytes Number of bytes received from the I2C write message
+ *
+ * @return 0 on success
+ * @return -EIO on error
+ */
+typedef int (*i2c_common_emul_finish_write_func)(const struct emul *target,
+						 int reg, int bytes);
+
+/**
+ * @brief Function type that is used by I2C device emulator on each byte of
+ *        I2C write message (except first byte).
+ *
+ * @param target Pointer to emulator
+ * @param reg Address which is now accessed by write command (first byte of I2C
+ *            write message)
+ * @param val Value of current byte
+ * @param bytes Number of bytes already received from the I2C write message
+ *              (excluding current byte)
+ *
+ * @return 0 on success
+ * @return -EIO on error
+ */
+typedef int (*i2c_common_emul_write_byte_func)(const struct emul *target,
+					       int reg, uint8_t val, int bytes);
+
+/**
+ * @brief Function type that is used by I2C device emulator before first byte of
+ *        I2C read message.
+ *
+ * @param target Pointer to emulator
+ * @param reg Address which is now accessed by read command (first byte of last
+ *            I2C write message)
+ *
+ * @return 0 on success
+ * @return -EIO on error
+ */
+typedef int (*i2c_common_emul_start_read_func)(const struct emul *target,
+					       int reg);
+
+/**
+ * @brief Function type that is used by I2C device emulator at the end of
+ *        I2C read message.
+ *
+ * @param target Pointer to emulator
+ * @param reg Address which is now accessed by read command (first byte of last
+ *            I2C write message)
+ * @param bytes Number of bytes responeded to the I2C read message
+ *
+ * @return 0 on success
+ * @return -EIO on error
+ */
+typedef int (*i2c_common_emul_finish_read_func)(const struct emul *target,
+						int reg, int bytes);
+
+/**
+ * @brief Function type that is used by I2C device emulator on each byte of
+ *        I2C read message.
+ *
+ * @param target Pointer to emulator
+ * @param reg Address which is now accessed by read command (first byte of last
+ *            I2C write message)
+ * @param val Pointer to buffer where current response byte should be stored
+ * @param bytes Number of bytes already responded to the I2C read message
+ *              (excluding current byte)
+ *
+ * @return 0 on success
+ * @return -EIO on error
+ */
+typedef int (*i2c_common_emul_read_byte_func)(const struct emul *target,
+					      int reg, uint8_t *val, int bytes);
+
+/**
+ * @brief Function type that is used by I2C device emulator to select register
+ *        address that should be compared with fail register set by user using
+ *        @ref i2c_common_emul_set_read_fail_reg and
+ *        @ref i2c_common_emul_set_write_fail_reg
+ *
+ * @param target Pointer to emulator
+ * @param reg Address which is now accessed by read/write command (first byte
+ *            of last I2C write message)
+ * @param bytes Number of bytes already processed in the I2C message handler
+ *              (excluding current byte)
+ * @param read If current I2C message is read
+ *
+ * @return Register address that should be compared with user-defined fail
+ *         register
+ */
+typedef int (*i2c_common_emul_access_reg_func)(const struct emul *target,
+					       int reg, int bytes, bool read);
+
+/**
+ * @brief Custom function type that is used as user-defined callback in read
+ *        I2C messages handling.
+ *
+ * @param target Pointer to emulator
+ * @param reg Address which is now accessed by read command (first byte of last
+ *            I2C write message)
+ * @param val Pointer to buffer where current response byte should be stored
+ * @param bytes Number of bytes already responded to the I2C read message
+ *              (excluding current byte)
+ * @param data Pointer to custom user data
+ *
+ * @return 0 on success
+ * @return 1 continue with normal emulator handler
+ * @return negative on error
+ */
+typedef int (*i2c_common_emul_read_func)(const struct emul *target, int reg,
+					 uint8_t *val, int bytes, void *data);
+
+/**
+ * @brief Custom function type that is used as user-defined callback in write
+ *        I2C messages handling.
+ *
+ * @param target Pointer to emulator
+ * @param reg Address which is now accessed by write command (first byte of I2C
+ *            write message)
+ * @param val Value of current byte
+ * @param bytes Number of bytes already received from the I2C write message
+ *              (excluding current byte)
+ * @param data Pointer to custom user data
+ *
+ * @return 0 on success
+ * @return 1 continue with normal emulator handler
+ * @return negative on error
+ */
+typedef int (*i2c_common_emul_write_func)(const struct emul *target, int reg,
+					  uint8_t val, int bytes, void *data);
+
+/** Static configuration, common for all i2c emulators */
+struct i2c_common_emul_cfg {
+	/** Label of the I2C device being emulated */
+	const char *dev_label;
+	/** Pointer to run-time data */
+	struct i2c_common_emul_data *data;
+	/** Address of emulator on i2c bus */
+	uint16_t addr;
+};
+
+/** Run-time data used by the emulator, common for all i2c emulators */
+struct i2c_common_emul_data {
+	/** I2C emulator detail */
+	struct i2c_emul emul;
+	/** Emulator device */
+	const struct device *i2c;
+	/** Configuration information */
+	const struct i2c_common_emul_cfg *cfg;
+
+	/** Current state of I2C bus (if emulator is handling message) */
+	enum i2c_common_emul_msg_state msg_state;
+	/** Number of already handled bytes in ongoing message */
+	int msg_byte;
+	/** Register selected in last write command */
+	uint8_t cur_reg;
+
+	/** Custom write function called on I2C write opperation */
+	i2c_common_emul_write_func write_func;
+	/** Data passed to custom write function */
+	void *write_func_data;
+	/** Custom read function called on I2C read opperation */
+	i2c_common_emul_read_func read_func;
+	/** Data passed to custom read function */
+	void *read_func_data;
+
+	/** Control if read should fail on given register */
+	int read_fail_reg;
+	/** Control if write should fail on given register */
+	int write_fail_reg;
+
+	/** Emulator function, called for first byte of write message */
+	i2c_common_emul_start_write_func start_write;
+	/** Emulator function, called for each byte of write message */
+	i2c_common_emul_write_byte_func write_byte;
+	/** Emulator function, called at the end of write message */
+	i2c_common_emul_finish_write_func finish_write;
+
+	/** Emulator function, called before first byte of read message */
+	i2c_common_emul_start_read_func start_read;
+	/** Emulator function, called for each byte of read message */
+	i2c_common_emul_read_byte_func read_byte;
+	/** Emulator function, called at the end of read message */
+	i2c_common_emul_finish_read_func finish_read;
+
+	/**
+	 * Emulator function, called to get register that should be checked
+	 * if was selected by user in set_read/write_fail_reg.
+	 */
+	i2c_common_emul_access_reg_func access_reg;
+
+	/** Mutex used to control access to emulator data */
+	struct k_mutex data_mtx;
+};
+
+/** A common API that simply links to the i2c_common_emul_transfer function */
+extern struct i2c_emul_api i2c_common_emul_api;
+
+/**
+ * @brief Lock access to emulator properties. After acquiring lock, user
+ *        may change emulator behaviour in multi-thread setup.
+ *
+ * @param common_data Pointer to emulator common data
+ * @param timeout Timeout in getting lock
+ *
+ * @return k_mutex_lock return code
+ */
+int i2c_common_emul_lock_data(struct i2c_common_emul_data *common_data,
+			      k_timeout_t timeout);
+
+/**
+ * @brief Unlock access to emulator properties.
+ *
+ * @param common_data Pointer to emulator common data
+ *
+ * @return k_mutex_unlock return code
+ */
+int i2c_common_emul_unlock_data(struct i2c_common_emul_data *common_data);
+
+/**
+ * @brief Set write handler for I2C messages. This function is called before
+ *        generic handler.
+ *
+ * @param common_data Pointer to emulator common data
+ * @param func Pointer to custom function
+ * @param data User data passed on call of custom function
+ */
+void i2c_common_emul_set_write_func(struct i2c_common_emul_data *common_data,
+				    i2c_common_emul_write_func func,
+				    void *data);
+
+/**
+ * @brief Set read handler for I2C messages. This function is called before
+ *        generic handler.
+ *
+ * @param common_data Pointer to emulator common data
+ * @param func Pointer to custom function
+ * @param data User data passed on call of custom function
+ */
+void i2c_common_emul_set_read_func(struct i2c_common_emul_data *common_data,
+				   i2c_common_emul_read_func func, void *data);
+
+/**
+ * @brief Setup fail on read of given register of emulator
+ *
+ * @param common_data Pointer to emulator common data
+ * @param reg Register address or one of special values
+ *            (I2C_COMMON_EMUL_FAIL_ALL_REG, I2C_COMMON_EMUL_NO_FAIL_REG)
+ */
+void i2c_common_emul_set_read_fail_reg(struct i2c_common_emul_data *common_data,
+				       int reg);
+
+/**
+ * @brief Setup fail on write of given register of emulator
+ *
+ * @param common_data Pointer to emulator common data
+ * @param reg Register address or one of special values
+ *            (I2C_COMMON_EMUL_FAIL_ALL_REG, I2C_COMMON_EMUL_NO_FAIL_REG)
+ */
+void i2c_common_emul_set_write_fail_reg(
+	struct i2c_common_emul_data *common_data, int reg);
+
+/**
+ * @biref Emulate an I2C transfer to an emulator
+ *
+ * This is common function used by I2C device emulators. It handles dispatching
+ * I2C message, calling user custom functions, failing on reading/writing
+ * registers selected by user and calling device specific functions.
+ *
+ * @param target The target peripheral emulated
+ * @param msgs List of messages to process
+ * @param num_msgs Number of messages to process
+ * @param addr Address of the I2C target device
+ *
+ * @retval 0 If successful
+ * @retval -EIO General input / output error
+ */
+int i2c_common_emul_transfer(const struct emul *target, struct i2c_msg *msgs,
+			     int num_msgs, int addr);
+
+int i2c_common_emul_transfer_workhorse(const struct emul *target,
+				       struct i2c_common_emul_data *data,
+				       const struct i2c_common_emul_cfg *cfg,
+				       struct i2c_msg *msgs, int num_msgs,
+				       int addr);
+
+/**
+ * @brief Initialize common emulator data structure
+ *
+ * @param data Pointer to emulator data
+ */
+void i2c_common_emul_init(struct i2c_common_emul_data *data);
+
+/**
+ * @}
+ */
+
+#endif /* __EMUL_COMMON_I2C_H */
diff --git a/zephyr/include/emul/emul_flash.h b/zephyr/include/emul/emul_flash.h
new file mode 100644
index 0000000000..4bba47c1df
--- /dev/null
+++ b/zephyr/include/emul/emul_flash.h
@@ -0,0 +1,27 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ *
+ * @brief Backend API for Cros flash emulator
+ */
+
+#ifndef ZEPHYR_INCLUDE_EMUL_EMUL_FLASH_H_
+#define ZEPHYR_INCLUDE_EMUL_EMUL_FLASH_H_
+
+#include <ec_commands.h>
+
+/**
+ * @brief Reset the protection.
+ */
+void cros_flash_emul_protect_reset(void);
+
+/**
+ * @brief Enable the protection.
+ */
+void cros_flash_emul_enable_protect(void);
+
+#endif /* ZEPHYR_INCLUDE_EMUL_EMUL_FLASH_H_ */
diff --git a/zephyr/include/emul/emul_icm42607.h b/zephyr/include/emul/emul_icm42607.h
new file mode 100644
index 0000000000..b1c331a58c
--- /dev/null
+++ b/zephyr/include/emul/emul_icm42607.h
@@ -0,0 +1,27 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef EMUL_ICM42607_H
+#define EMUL_ICM42607_H
+
+#include "emul/emul_common_i2c.h"
+
+#include <stdint.h>
+
+#include <zephyr/drivers/emul.h>
+
+void icm42607_emul_reset(const struct emul *emul);
+
+int icm42607_emul_peek_reg(const struct emul *emul, int reg);
+
+int icm42607_emul_write_reg(const struct emul *emul, int reg, int val);
+
+void icm42607_emul_push_fifo(const struct emul *emul, const uint8_t *src,
+			     int size);
+
+struct i2c_common_emul_data *
+emul_icm42607_get_i2c_common_data(const struct emul *emul);
+
+#endif
diff --git a/zephyr/include/emul/emul_isl923x.h b/zephyr/include/emul/emul_isl923x.h
new file mode 100644
index 0000000000..96be6b6773
--- /dev/null
+++ b/zephyr/include/emul/emul_isl923x.h
@@ -0,0 +1,115 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef ZEPHYR_INCLUDE_EMUL_EMUL_ISL923X_H_
+#define ZEPHYR_INCLUDE_EMUL_EMUL_ISL923X_H_
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/i2c_emul.h>
+
+/**
+ * @brief Get the emulator's parent bus device
+ *
+ * @param emulator The emulator to look-up
+ * @return Pointer to the bus connecting to the emulator
+ */
+const struct device *isl923x_emul_get_parent(const struct emul *emulator);
+
+/**
+ * @brief Get pointer to emulator i2c_common_emul_cfg
+ *
+ * @param emulator The emulator to look-up
+ * @return Pointer to the i2c_common_emul_cfg struct
+ */
+const struct i2c_common_emul_cfg *
+isl923x_emul_get_cfg(const struct emul *emulator);
+
+/**
+ * @brief Reset all registers
+ *
+ * @param emulator The emulator to modify
+ */
+void isl923x_emul_reset_registers(const struct emul *emulator);
+
+/**
+ * @brief Set the manufacturer ID
+ *
+ * @param emulator The emulator to modify
+ * @param manufacturer_id The new manufacturer ID
+ */
+void isl923x_emul_set_manufacturer_id(const struct emul *emulator,
+				      uint16_t manufacturer_id);
+
+/**
+ * @brief Set the device ID
+ *
+ * @param emulator The emulator to modify
+ * @param device_id The new device ID
+ */
+void isl923x_emul_set_device_id(const struct emul *emulator,
+				uint16_t device_id);
+
+/**
+ * @brief Check whether or not learn mode is enabled
+ *
+ * @param emulator The emulator to probe
+ * @return True if the emulator is in learn mode
+ */
+bool isl923x_emul_is_learn_mode_enabled(const struct emul *emulator);
+
+/**
+ * @brief Set the emulator's learn mode manually without affecting the driver
+ *
+ * @param emulator The emulator to modify
+ * @param enabled Whether or not learn mode should be enabled
+ */
+void isl923x_emul_set_learn_mode_enabled(const struct emul *emulator,
+					 bool enabled);
+
+/**
+ * @brief Set the emulator's ADC vbus register
+ *
+ * @param emulator The emulator to modify
+ * @param vbus_mv  VBUS voltage in mV
+ */
+void isl923x_emul_set_adc_vbus(const struct emul *emulator, uint16_t vbus_mv);
+
+/**
+ * @brief Set the state of the ACOK pin, which is reflected in the INFO2
+ *        register
+ *
+ * @param value If 1, AC adapter is present. If 0, no adapter is present
+ */
+void raa489000_emul_set_acok_pin(const struct emul *emulator, uint16_t value);
+
+/**
+ * @brief Set the value of the state machine status bits in the INFO2 register.
+ *
+ * @param value State machine state, such as RAA489000_INFO2_STATE_OTG
+ */
+void raa489000_emul_set_state_machine_state(const struct emul *emulator,
+					    uint16_t value);
+
+/**
+ * @brief Peek at a register value. This function will assert if the requested
+ *        register does is unimplemented.
+ *
+ * @param emulator Reference to the I2C emulator being used
+ * @param reg The address of the register to query
+ * @return The 16-bit value of the register
+ */
+uint16_t isl923x_emul_peek_reg(const struct emul *emul, int reg);
+
+/**
+ * @brief Returns pointer to i2c_common_emul_data for argument emul
+ *
+ * @param emul Pointer to ISL923X emulator
+ * @return Pointer to i2c_common_emul_data from argument emul
+ */
+struct i2c_common_emul_data *
+emul_isl923x_get_i2c_common_data(const struct emul *emul);
+
+#endif /* ZEPHYR_INCLUDE_EMUL_EMUL_ISL923X_H_ */
diff --git a/zephyr/include/emul/emul_isl9241.h b/zephyr/include/emul/emul_isl9241.h
new file mode 100644
index 0000000000..2838687731
--- /dev/null
+++ b/zephyr/include/emul/emul_isl9241.h
@@ -0,0 +1,36 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef EMUL_ISL9241_H
+#define EMUL_ISL9241_H
+
+#include <zephyr/drivers/emul.h>
+
+/**
+ * Peek an internal register value
+ *
+ * @param emul - ISL9241 emulator data
+ * @param reg - which register to peek
+ * @return register contents
+ */
+uint16_t isl9241_emul_peek(const struct emul *emul, int reg);
+
+/**
+ * Fake a Vbus voltage presence
+ *
+ * @param emul - ISL9241 emulator data
+ * @param vbus_mv - desired Vbus mV to set
+ */
+void isl9241_emul_set_vbus(const struct emul *emul, int vbus_mv);
+
+/**
+ * Fake a specific Vsys voltage
+ *
+ * @param emul - ISL9241 emulator data
+ * @param vsys_mv - desired Vsys mV to set
+ */
+void isl9241_emul_set_vsys(const struct emul *emul, int vsys_mv);
+
+#endif
diff --git a/zephyr/include/emul/emul_kb_raw.h b/zephyr/include/emul/emul_kb_raw.h
new file mode 100644
index 0000000000..0598eda7ab
--- /dev/null
+++ b/zephyr/include/emul/emul_kb_raw.h
@@ -0,0 +1,51 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <stdint.h>
+
+/**
+ * @file
+ *
+ * @brief Backend API for kb raw emulator
+ */
+
+#ifndef __EMUL_KB_RAW_H
+#define __EMUL_KB_RAW_H
+
+struct device;
+
+/**
+ * @brief Raw keyboard emulator backend API
+ * @defgroup kb_raw_emul raw keyboard emulator
+ * @{
+ *
+ * The raw keyboard emulator allows for emulating a physical keyboard.
+ */
+
+/**
+ * @brief Sets or clears a key.
+ *
+ * @param dev Pointer to kb_raw emulator device.
+ * @param row The keyboard scan row.
+ * @param col The keyboard scan column.
+ * @param pressed If non-zero, set that key row/col as pressed, if zero it is
+ *                unpressed.
+ * @return 0 for success, -EINVAL for an invalid param.
+ */
+int emul_kb_raw_set_kbstate(const struct device *dev, uint8_t row, uint8_t col,
+			    int pressed);
+
+/**
+ * @brief Resets the keyboard to its initial state.
+ *
+ * @param dev Pointer to kb_raw emulator device.
+ */
+void emul_kb_raw_reset(const struct device *dev);
+
+/**
+ * @}
+ */
+
+#endif /* __EMUL_KB_RAW_H */
diff --git a/zephyr/include/emul/emul_lis2dw12.h b/zephyr/include/emul/emul_lis2dw12.h
new file mode 100644
index 0000000000..5410a54cdd
--- /dev/null
+++ b/zephyr/include/emul/emul_lis2dw12.h
@@ -0,0 +1,100 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef ZEPHYR_INCLUDE_EMUL_EMUL_LIS2DW12_H_
+#define ZEPHYR_INCLUDE_EMUL_EMUL_LIS2DW12_H_
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/i2c_emul.h>
+
+/**
+ * @brief Reset the state of the lis2dw12 emulator.
+ *
+ * @param emul The emulator to reset.
+ */
+void lis2dw12_emul_reset(const struct emul *emul);
+
+/**
+ * @brief Set the who-am-i register value.
+ *
+ * By default the who-am-i register holds LIS2DW12_WHO_AM_I, this function
+ * enables overriding that value in order to drive testing.
+ *
+ * @param emul The emulator to modify.
+ * @param who_am_i The new who-am-i register value.
+ */
+void lis2dw12_emul_set_who_am_i(const struct emul *emul, uint8_t who_am_i);
+
+/**
+ * @brief Check the number of times the chip was soft reset.
+ *
+ * This value is reset by a call to lis2dw12_emul_reset().
+ *
+ * @param emul The emulator to query
+ * @return The number of times that the chip was reset.
+ */
+uint32_t lis2dw12_emul_get_soft_reset_count(const struct emul *emul);
+
+/**
+ * @brief Peeks at the value of a register without doing any I2C transaction.
+ *        If the register is unsupported, or `emul` is NULL, this function
+ *        asserts.
+ *
+ * @param emul The emulator to query
+ * @param reg The register to access
+ * @return The value of the register
+ */
+uint8_t lis2dw12_emul_peek_reg(const struct emul *emul, int reg);
+
+/**
+ * @brief Retrieves the ODR[3:0] bits from CRTL1 register
+ *
+ * @param emul The emulator to query
+ * @return The ODR bits, right-aligned
+ */
+uint8_t lis2dw12_emul_peek_odr(const struct emul *emul);
+
+/**
+ * @brief Retrieves the MODE[1:0] bits from CRTL1 register
+ *
+ * @param emul The emulator to query
+ * @return The MODE bits, right-aligned
+ */
+uint8_t lis2dw12_emul_peek_mode(const struct emul *emul);
+
+/**
+ * @brief Retrieves the LPMODE[1:0] bits from CRTL1 register
+ *
+ * @param emul The emulator to query
+ * @return The LPMODE bits, right-aligned
+ */
+uint8_t lis2dw12_emul_peek_lpmode(const struct emul *emul);
+
+/**
+ * @brief Updates the current 3-axis acceleromter reading and
+ *        sets the DRDY (data ready) flag.
+ * @param emul Reference to current LIS2DW12 emulator.
+ * @param reading array of int X, Y, and Z readings.
+ * @return 0 on success, or -EINVAL if readings are out of bounds.
+ */
+int lis2dw12_emul_set_accel_reading(const struct emul *emul, intv3_t reading);
+
+/**
+ * @brief Clears the current accelerometer reading and resets the
+ *        DRDY (data ready) flag.
+ * @param emul Reference to current LIS2DW12 emulator.
+ */
+void lis2dw12_emul_clear_accel_reading(const struct emul *emul);
+
+/**
+ * @brief Returns pointer to i2c_common_emul_data for argument emul
+ *
+ * @param emul Pointer to LIS2DW12 emulator
+ * @return Pointer to i2c_common_emul_data from argument emul
+ */
+struct i2c_common_emul_data *
+emul_lis2dw12_get_i2c_common_data(const struct emul *emul);
+
+#endif /* ZEPHYR_INCLUDE_EMUL_EMUL_LIS2DW12_H_ */
diff --git a/zephyr/include/emul/emul_ln9310.h b/zephyr/include/emul/emul_ln9310.h
new file mode 100644
index 0000000000..5d0cab9c20
--- /dev/null
+++ b/zephyr/include/emul/emul_ln9310.h
@@ -0,0 +1,94 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ *
+ * @brief Backend API for LN9310 emulator
+ */
+
+#ifndef ZEPHYR_INCLUDE_EMUL_EMUL_LN9310_H_
+#define ZEPHYR_INCLUDE_EMUL_EMUL_LN9310_H_
+
+#include "driver/ln9310.h"
+
+#include <stdbool.h>
+
+#include <zephyr/drivers/emul.h>
+
+/**
+ * @brief Select the current emulator to use.
+ *
+ * Currently, only a single ln9310 can be instantiated at any given instance due
+ * to how the driver was written. Once this restriction is removed, there's
+ * still an issue with the board_get_battery_cell_type() function as it doesn't
+ * take a device pointer. This function selects the current LN9310 context which
+ * will serve the data for that board function.
+ *
+ * @param emulator The LN9310 emulator to select.
+ */
+void ln9310_emul_set_context(const struct emul *emulator);
+
+/**
+ * @brief Clear all the emulator data.
+ *
+ * @param emulator The LN9310 emulator to clear.
+ */
+void ln9310_emul_reset(const struct emul *emulator);
+
+/**
+ * @brief Update the emulator's battery cell type.
+ *
+ * @param emulator The LN9310 emulator to update.
+ * @param type The battery type to use.
+ */
+void ln9310_emul_set_battery_cell_type(const struct emul *emulator,
+				       enum battery_cell_type type);
+
+/**
+ * @brief Update the emulator's version number.
+ *
+ * @param emulator The LN9310 emulator to update.
+ * @param version The LN9310 chip version number.
+ */
+void ln9310_emul_set_version(const struct emul *emulator, int version);
+
+/**
+ * @brief Update whether or not the LN9310 is currently getting more than 10V.
+ *
+ * @param emulator The LN9310 emulator to update.
+ * @param is_gt_10v Whether or not the chip is currently getting more than 10V.
+ */
+void ln9310_emul_set_vin_gt_10v(const struct emul *emulator, bool is_gt_10v);
+
+/**
+ * @brief Get whether or not the LN9310 is initialized.
+ *
+ * @param emulator The LN9310 emulator to read.
+ *
+ * @return true if the LN9310 was correctly initialized.
+ */
+bool ln9310_emul_is_init(const struct emul *emulator);
+
+/**
+ * @brief Get the I2C emulator struct
+ *
+ * This is generally coupled with calls to i2c_common_emul_* functions.
+ *
+ * @param emulator The emulator to look-up
+ * @return Pointer to the I2C emulator struct
+ */
+struct i2c_emul *ln9310_emul_get_i2c_emul(const struct emul *emulator);
+
+/**
+ * @brief Returns pointer to i2c_common_emul_data for argument emul
+ *
+ * @param emul Pointer to LN9310 emulator
+ * @return Pointer to i2c_common_emul_data from argument emul
+ */
+struct i2c_common_emul_data *
+emul_ln9310_get_i2c_common_data(const struct emul *emul);
+
+#endif /* ZEPHYR_INCLUDE_EMUL_EMUL_LN9310_H_ */
diff --git a/zephyr/include/emul/emul_nx20p348x.h b/zephyr/include/emul/emul_nx20p348x.h
new file mode 100644
index 0000000000..f01839d325
--- /dev/null
+++ b/zephyr/include/emul/emul_nx20p348x.h
@@ -0,0 +1,39 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef EMUL_NX20P348X_H
+#define EMUL_NX20P348X_H
+
+#include <zephyr/drivers/emul.h>
+
+/**
+ * Peek an internal register value
+ *
+ * @param emul - NX20P383X emulator data
+ * @param reg - which register to peek
+ * @return register contents
+ */
+uint8_t nx20p348x_emul_peek(const struct emul *emul, int reg);
+
+/**
+ * Set an interrupt in the first interrupt register
+ *
+ * @param emul - NX20P383X emulator data
+ * @param val - value for interrupt register
+ */
+void nx20p348x_emul_set_interrupt1(const struct emul *emul, uint8_t val);
+
+/**
+ * Enable/Disable interact with the TCPC
+ *
+ * This is used for pretending no TCPC connected on the port.
+ * Interaction is default enabled.
+ *
+ * @param emul - NX20P383X emulator data
+ * @param val - value for interrupt register
+ */
+void nx20p348x_emul_set_tcpc_interact(const struct emul *emul, bool en);
+
+#endif
diff --git a/zephyr/include/emul/emul_pct2075.h b/zephyr/include/emul/emul_pct2075.h
new file mode 100644
index 0000000000..f9e1ef60b2
--- /dev/null
+++ b/zephyr/include/emul/emul_pct2075.h
@@ -0,0 +1,32 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef EMUL_PCT2075_H
+#define EMUL_PCT2075_H
+
+#include "emul/emul_common_i2c.h"
+
+#include <zephyr/drivers/emul.h>
+
+#define PCT2075_REG_NUMBER 5
+
+struct pct2075_data {
+	struct i2c_common_emul_data common;
+	uint16_t regs[PCT2075_REG_NUMBER];
+};
+
+/**
+ * @brief Set the temperature measurement for the sensor.
+ *
+ * @param emul Pointer to emulator
+ * @param mk Temperature to set in mili-kalvin. The temperature
+ * should me in range of 328150 to 400150, with 150 resolution.
+ *
+ * @return 0 on success
+ * @return negative on error
+ */
+int pct2075_emul_set_temp(const struct emul *emul, int mk);
+
+#endif
diff --git a/zephyr/include/emul/emul_pi3usb9201.h b/zephyr/include/emul/emul_pi3usb9201.h
new file mode 100644
index 0000000000..05feff567f
--- /dev/null
+++ b/zephyr/include/emul/emul_pi3usb9201.h
@@ -0,0 +1,46 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ *
+ * @brief Backend API for pi3usb9201 emulator
+ */
+
+#ifndef __EMUL_PI3USB9201_H
+#define __EMUL_PI3USB9201_H
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/i2c_emul.h>
+
+#define PI3USB9201_REG_CTRL_1 0x0
+#define PI3USB9201_REG_CTRL_2 0x1
+#define PI3USB9201_REG_CLIENT_STS 0x2
+#define PI3USB9201_REG_HOST_STS 0x3
+
+/**
+ * @brief Set value of given register of pi3usb9201
+ *
+ * @param emul Pointer to pi3usb9201 emulator
+ * @param reg Register address
+ * @param val New value of the register
+ *
+ * @return 0 on success or error
+ */
+int pi3usb9201_emul_set_reg(const struct emul *emul, int reg, uint8_t val);
+
+/**
+ * @brief Get value of given register of pi3usb9201
+ *
+ * @param emul Pointer to pi3usb9201 emulator
+ * @param reg Register address
+ * @param val Pointer to write current value of register
+ *
+ * @return 0 on success or error
+ */
+int pi3usb9201_emul_get_reg(const struct emul *emul, int reg, uint8_t *val);
+
+#endif /* __EMUL_PI3USB9201_H */
diff --git a/zephyr/include/emul/emul_power_signals.h b/zephyr/include/emul/emul_power_signals.h
new file mode 100644
index 0000000000..7dea6079f0
--- /dev/null
+++ b/zephyr/include/emul/emul_power_signals.h
@@ -0,0 +1,49 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef EMUL_POWER_SIGNALS_H_
+#define EMUL_POWER_SIGNALS_H_
+
+/**
+ * @brief Test platform definition,
+ *        This structure contains all power signal nodes associated to one
+ *        test.
+ */
+struct power_signal_emul_test_platform {
+	char *name_id;
+	int nodes_count;
+	struct power_signal_emul_node **nodes;
+};
+
+#define EMUL_POWER_SIGNAL_TEST_PLATFORM_DECL(inst) \
+	extern const struct power_signal_emul_test_platform inst;
+
+#define EMUL_POWER_SIGNAL_TEST_PLATFORM(inst) (&DT_CAT(DT_N_S_, inst))
+
+DT_FOREACH_STATUS_OKAY(intel_ap_pwr_test_platform,
+		       EMUL_POWER_SIGNAL_TEST_PLATFORM_DECL)
+/**
+ * @brief Load test platform.
+ *
+ * This initializes each of the test platform nodes.
+ *
+ * @param test_platform Pointer to test platform structure.
+ *
+ * @return 0 indicating success.
+ * @return -EINVAL `test_id` parameter is invalid.
+ * @return -EBUSY `test_id` One test platform is currently loaded.
+ */
+int power_signal_emul_load(
+	const struct power_signal_emul_test_platform *test_platform);
+
+/**
+ * @brief Unload test platform.
+ *
+ * @return 0 indicating success.
+ * @return -EINVAL no test platform has been loaded.
+ */
+int power_signal_emul_unload(void);
+
+#endif /* EMUL_POWER_SIGNALS_H_ */
diff --git a/zephyr/include/emul/emul_ps8743.h b/zephyr/include/emul/emul_ps8743.h
new file mode 100644
index 0000000000..503d014317
--- /dev/null
+++ b/zephyr/include/emul/emul_ps8743.h
@@ -0,0 +1,13 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef EMUL_PS8743_H
+#define EMUL_PS8743_H
+
+#include <zephyr/drivers/emul.h>
+
+int ps8743_emul_peek_reg(const struct emul *emul, int reg);
+
+#endif
diff --git a/zephyr/include/emul/emul_rt9490.h b/zephyr/include/emul/emul_rt9490.h
new file mode 100644
index 0000000000..8f91a0e97b
--- /dev/null
+++ b/zephyr/include/emul/emul_rt9490.h
@@ -0,0 +1,17 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef EMUL_RT9490_H
+#define EMUL_RT9490_H
+
+#include <zephyr/drivers/emul.h>
+
+void rt9490_emul_reset_regs(const struct emul *emul);
+
+int rt9490_emul_peek_reg(const struct emul *emul, int reg);
+
+int rt9490_emul_write_reg(const struct emul *emul, int reg, int val);
+
+#endif
diff --git a/zephyr/include/emul/emul_sm5803.h b/zephyr/include/emul/emul_sm5803.h
new file mode 100644
index 0000000000..7ecbc4c096
--- /dev/null
+++ b/zephyr/include/emul/emul_sm5803.h
@@ -0,0 +1,138 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/gpio.h>
+
+const struct gpio_dt_spec *
+sm5803_emul_get_interrupt_gpio(const struct emul *emul);
+struct i2c_common_emul_data *sm5803_emul_get_i2c_main(const struct emul *emul);
+struct i2c_common_emul_data *sm5803_emul_get_i2c_chg(const struct emul *emul);
+struct i2c_common_emul_data *sm5803_emul_get_i2c_meas(const struct emul *emul);
+struct i2c_common_emul_data *sm5803_emul_get_i2c_test(const struct emul *emul);
+
+/**
+ * Read the value of a charger page register, by address.
+ *
+ * This is useful to verify that a user has written an expected value to a
+ * register, without depending on the user's corresponding getter function.
+ *
+ * @return negative value on error, otherwise 8-bit register value.
+ */
+int sm5803_emul_read_chg_reg(const struct emul *emul, uint8_t reg);
+
+/**
+ * Set the reported VBUS voltage, in mV.
+ *
+ * If the VBUS voltage crosses the charger detection threshold as a result,
+ * a CHG_DET interrupt will automatically be triggered.
+ */
+void sm5803_emul_set_vbus_voltage(const struct emul *emul, uint16_t mv);
+
+/** Set the reported input current (from VBUS), in mA. */
+void sm5803_emul_set_input_current(const struct emul *emul, uint16_t mv);
+
+/** Set the reported battery charge current, in mA. */
+void sm5803_emul_set_battery_current(const struct emul *emul, uint16_t ma);
+
+/** Set the reported device ID (default 3). */
+void sm5803_emul_set_device_id(const struct emul *emul, uint8_t id);
+
+/** Set the platform ID as configured in hardware by the PMODE resistor. */
+void sm5803_emul_set_pmode(const struct emul *emul, uint8_t pmode);
+
+/** Get the register value of ICHG_FAST_SET; the fast charge current limit. */
+int sm5803_emul_get_fast_charge_current_limit(const struct emul *emul);
+
+/** Get the values of the GPADC_CONFIG_1 and GPADC_CONFIG_2 registers. */
+void sm5803_emul_get_gpadc_conf(const struct emul *emul, uint8_t *conf1,
+				uint8_t *conf2);
+
+/** Set the GPADC enable bits in GPADC_CONFIG_1 and GPADC_CONFIG_2 registers. */
+void sm5803_emul_set_gpadc_conf(const struct emul *emul, uint8_t conf1,
+				uint8_t conf2);
+
+/** Return whether the main clock is slowed (CLOCK_SEL:LOW_POWER_CLOCK_EN). */
+bool sm5803_emul_is_clock_slowed(const struct emul *emul);
+
+/** Get the value of the CC_CONFIG_1 register. */
+uint8_t sm5803_emul_get_cc_config(const struct emul *emul);
+
+/** Get the values of the FLOW1..FLOW3 registers. */
+void sm5803_emul_get_flow_regs(const struct emul *emul, uint8_t *flow1,
+			       uint8_t *flow2, uint8_t *flow3);
+
+/**
+ * Set the INT_REQ_* registers to indicate pending interrupts.
+ *
+ * This does not clear pending IRQs; it only asserts them. IRQs are cleared only
+ * when the interrupt status registers are read.
+ */
+void sm5803_emul_set_irqs(const struct emul *emul, uint8_t irq1, uint8_t irq2,
+			  uint8_t irq3, uint8_t irq4);
+
+/** Get the value of the GPIO_CTRL_1 register, which controls GPIO0. */
+uint8_t sm5803_emul_get_gpio_ctrl(const struct emul *emul);
+
+/**
+ * Get the values of the IR_COMP1 and IR_COMP2 registers.
+ *
+ * Register values are concatenated, with COMP1 as MSB and COMP2 as LSB.
+ */
+uint16_t sm5803_emul_get_ir_comp(const struct emul *emul);
+
+/** Get the value of the CHG_MON register. */
+uint8_t sm5803_emul_get_chg_mon(const struct emul *emul);
+
+/** Get the value of the ANA_EN1 (ANA_EN_REG1) register. */
+uint8_t sm5803_emul_get_ana_en1(const struct emul *emul);
+
+/** Get the value of the DISCH_CONF1 register. */
+uint8_t sm5803_emul_get_disch_conf1(const struct emul *emul);
+/** Get the value of the DISCH_CONF2 register. */
+uint8_t sm5803_emul_get_disch_conf2(const struct emul *emul);
+/** Get the value of the DISCH_CONF5 register. */
+uint8_t sm5803_emul_get_disch_conf5(const struct emul *emul);
+/** Get the value of the DISCH_CONF6 register. */
+uint8_t sm5803_emul_get_disch_conf6(const struct emul *emul);
+
+/** Get the value of the STATUS_CHG register. */
+uint8_t sm5803_emul_get_chg_status(const struct emul *emul);
+/** Get a value for the STATUS_CHG register. */
+void sm5803_emul_set_chg_status(const struct emul *emul, uint8_t value);
+
+/** Get the value of the STATUS_DISCH register. */
+uint8_t sm5803_emul_get_disch_status(const struct emul *emul);
+/** Set a value for the STATUS_DISCH register. */
+void sm5803_emul_set_disch_status(const struct emul *emul, uint8_t value);
+
+/** Get the value of the PORTS_CTRL register. */
+uint8_t sm5803_emul_get_ports_ctrl(const struct emul *emul);
+
+/** Get the value of the REFERENCE1 register (REG_REFERENCE) */
+uint8_t sm5803_emul_get_reference_reg(const struct emul *emul);
+
+/** Return true if the PSYS1_DAC_EN bit of REG_PSYS1 is set. */
+bool sm5803_emul_is_psys_dac_enabled(const struct emul *emul);
+
+/** Get the value of the PHOT1 register. */
+uint8_t sm5803_emul_get_phot1(const struct emul *emul);
+
+/** Get the value of the LOG1 register. */
+uint8_t sm5803_emul_get_log1(const struct emul *emul);
+
+/** Set the reported voltage on the VBATSNSP pin, in mV. */
+void sm5803_emul_set_vbat_sns_mv(const struct emul *emul, uint16_t mv);
+
+/** Set the reported internal temperature of the charger, in Kelvin. */
+void sm5803_emul_set_internal_temperature(const struct emul *emul,
+					  uint16_t kelvin);
+/** Get the value of the TINT_HIGH_TH register. */
+uint8_t sm5803_emul_get_tint_high_th(const struct emul *emul);
+/** Get the value of the TINT_LOW_TH register. */
+uint8_t sm5803_emul_get_tint_low_th(const struct emul *emul);
+
+/** Set the reported VSYS voltage (as measured), in mV. */
+void sm5803_emul_set_vsys_measured_mv(const struct emul *emul, uint16_t mv);
diff --git a/zephyr/include/emul/emul_smart_battery.h b/zephyr/include/emul/emul_smart_battery.h
new file mode 100644
index 0000000000..35018f37f7
--- /dev/null
+++ b/zephyr/include/emul/emul_smart_battery.h
@@ -0,0 +1,207 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ *
+ * @brief Backend API for Smart Battery emulator
+ */
+
+#ifndef __EMUL_SMART_BATTERY_H
+#define __EMUL_SMART_BATTERY_H
+
+#include "emul/emul_common_i2c.h"
+
+#include <stdint.h>
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/i2c_emul.h>
+
+/**
+ * @brief Smart Battery emulator backend API
+ * @defgroup sbat_emul Smart Battery emulator
+ * @{
+ *
+ * Smart Battery emulator handle static state of device. E.g. setting charging
+ * current will not charge battery over time. Sending periodic status messages
+ * and alarms to SMBus Host or charging voltage/current to Smart Battery Charger
+ * is not supported. Behaviour of Smart Battery emulator is application-defined.
+ * As-such, each application may
+ *
+ * - define a Device Tree overlay file to set the most of battery properties
+ * - get battery properties calling @ref sbat_emul_get_bat_data Battery
+ *   properties can be changed through obtained pointer. In multithread
+ *   environment access to battery can be guarded by calling
+ *   @ref sbat_emul_lock_bat_data and @ref sbat_emul_unlock_bat_data
+ * - call functions from emul_common_i2c.h to setup custom handlers for SMBus
+ *   messages
+ */
+
+/* Value used to indicate that no command is selected */
+#define SBAT_EMUL_NO_CMD -1
+/* Maximum size of data that can be returned in SMBus block transaction */
+#define MAX_BLOCK_SIZE 32
+/* Maximum length of command to send is maximum size of data + len byte + PEC */
+#define MSG_BUF_LEN (MAX_BLOCK_SIZE + 2)
+
+/** @brief Emulated smart battery properties */
+struct sbat_emul_bat_data {
+	/** Battery mode - bit field configuring some battery behaviours */
+	uint16_t mode;
+	/** Word returned on manufacturer access command */
+	uint16_t mf_access;
+	/** Capacity alarm value */
+	uint16_t cap_alarm;
+	/** Remaing time alarm value */
+	uint16_t time_alarm;
+	/** Rate of charge used in some commands */
+	int16_t at_rate;
+	/**
+	 * Flag indicating if AT_RATE_TIME_TO_FULL command supports mW
+	 * capacity mode
+	 */
+	int at_rate_full_mw_support;
+	/** Error code returned by last command */
+	uint16_t error_code;
+	/** Design battery voltage in mV */
+	uint16_t design_mv;
+	/** Default Design battery voltage in mV */
+	const uint16_t default_design_mv;
+	/** Battery temperature at the moment in Kelvins */
+	uint16_t temp;
+	/** Battery voltage at the moment in mV */
+	uint16_t volt;
+	/** Current charging (> 0) or discharging (< 0) battery in mA */
+	int16_t cur;
+	/** Average current from 1 minute */
+	int16_t avg_cur;
+	/** Maximum error of returned values in percent */
+	uint16_t max_error;
+	/** Capacity of the battery at the moment in mAh */
+	uint16_t cap;
+	/** Default capacity of the battery at the moment in mAh */
+	const uint16_t default_cap;
+	/** Full capacity of the battery in mAh */
+	uint16_t full_cap;
+	/** Default full capacity of the battery at the moment in mAh */
+	const uint16_t default_full_cap;
+	/** Design battery capacity in mAh */
+	uint16_t design_cap;
+	/** Charging current requested by battery */
+	uint16_t desired_charg_cur;
+	/** Charging voltage requested by battery */
+	uint16_t desired_charg_volt;
+	/** Number of cycles */
+	uint16_t cycle_count;
+	/** Specification of battery */
+	uint16_t spec_info;
+	/** Status of battery */
+	uint16_t status;
+	/** Date of manufacturing */
+	uint16_t mf_date;
+	/** Serial number */
+	uint16_t sn;
+	/** Manufacturer name */
+	uint8_t mf_name[MAX_BLOCK_SIZE];
+	/** Manufacturer name length */
+	int mf_name_len;
+	/** Device name */
+	uint8_t dev_name[MAX_BLOCK_SIZE];
+	/** Device name length */
+	int dev_name_len;
+	/** Device chemistry */
+	uint8_t dev_chem[MAX_BLOCK_SIZE];
+	/** Device chemistry length */
+	int dev_chem_len;
+	/** Manufacturer data */
+	uint8_t mf_data[MAX_BLOCK_SIZE];
+	/** Manufacturer data length */
+	int mf_data_len;
+	/** Manufacture info */
+	uint8_t mf_info[MAX_BLOCK_SIZE];
+	/** Manufacture info length */
+	int mf_info_len;
+};
+
+/**
+ * @brief Function which allows to get properties of emulated smart battery
+ *
+ * @param emul Pointer to smart battery emulator
+ *
+ * @return Pointer to smart battery properties
+ */
+struct sbat_emul_bat_data *sbat_emul_get_bat_data(const struct emul *emul);
+
+/**
+ * @brief Convert date to format used by smart battery
+ *
+ * @param day Day
+ * @param month Month
+ * @param year Year
+ *
+ * @return Converted date
+ */
+uint16_t sbat_emul_date_to_word(unsigned int day, unsigned int month,
+				unsigned int year);
+
+/**
+ * @brief Function which gets return value for read commands that returns word.
+ *        This function may be used to obtain battery properties that are
+ *        calculated e.g. time to empty/full.
+ *
+ * @param emul Pointer to smart battery emulator
+ * @param cmd Read command
+ * @param val Pointer to where word should be stored
+ *
+ * @return 0 on success
+ * @return 1 if command is unknown or return type different then word
+ * @return negative on error while reading value
+ */
+int sbat_emul_get_word_val(const struct emul *emul, int cmd, uint16_t *val);
+
+/**
+ * @brief Function which gets return value for read commands that returns block
+ *        data
+ *
+ * @param emul Pointer to smart battery emulator
+ * @param cmd Read command
+ * @param blk Pointer to where data pointer should be stored
+ * @param len Pointer to where data length should be stored
+ *
+ * @return 0 on success
+ * @return 1 if command is unknown or return type different then word
+ * @return negative on error while reading value
+ */
+int sbat_emul_get_block_data(const struct emul *emul, int cmd, uint8_t **blk,
+			     int *len);
+
+/**
+ * @brief Set next response of emulator. This function may be used in user
+ *        custom read callback to setup response with calculated PEC.
+ *
+ * @param emul Pointer to smart battery emulator
+ * @param cmd Read command
+ * @param buf Buffer with the response
+ * @param len Length of the response
+ * @param fail If emulator should fail to send response
+ */
+void sbat_emul_set_response(const struct emul *emul, int cmd, uint8_t *buf,
+			    int len, bool fail);
+
+/**
+ * @brief Returns pointer to i2c_common_emul_data for argument emul
+ *
+ * @param emul Pointer to smart_battery emulator
+ * @return Pointer to i2c_common_emul_data from argument emul
+ */
+struct i2c_common_emul_data *
+emul_smart_battery_get_i2c_common_data(const struct emul *emul);
+
+/**
+ * @}
+ */
+
+#endif /* __EMUL_SMART_BATTERY_H */
diff --git a/zephyr/include/emul/emul_sn5s330.h b/zephyr/include/emul/emul_sn5s330.h
new file mode 100644
index 0000000000..77141e679b
--- /dev/null
+++ b/zephyr/include/emul/emul_sn5s330.h
@@ -0,0 +1,59 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef ZEPHYR_INCLUDE_EMUL_EMUL_SN5S330_H_
+#define ZEPHYR_INCLUDE_EMUL_EMUL_SN5S330_H_
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/i2c_emul.h>
+
+/**
+ * @brief The i2c emulator pointer from the top level emul.
+ *
+ * @param emul The emulator to query
+ * @return Pointer to the i2c emulator struct
+ */
+struct i2c_emul *sn5s330_emul_to_i2c_emul(const struct emul *emul);
+
+/**
+ * @brief Get the register value without incurring any side-effects
+ *
+ * @param emul The emulator to query
+ * @param reg The register to read
+ * @param val Pointer to write the register value to
+ */
+void sn5s330_emul_peek_reg(const struct emul *emul, uint32_t reg, uint8_t *val);
+
+/**
+ * @brief Reset the sn5s330 emulator
+ *
+ * @param emul The emulator to reset
+ */
+void sn5s330_emul_reset(const struct emul *emul);
+
+/**
+ * @brief Emulate vbus overcurrent clamping condition.
+ *
+ * @param emul The sn5s330 chip emulator.
+ */
+void sn5s330_emul_make_vbus_overcurrent(const struct emul *emul);
+
+/**
+ * @brief Emulate vbus voltage is below min 0.6V.
+ *
+ * @param emul The sn5s330 chip emulator.
+ */
+void sn5s330_emul_lower_vbus_below_minv(const struct emul *emul);
+
+/**
+ * @brief Returns pointer to i2c_common_emul_data for argument emul
+ *
+ * @param emul Pointer to SN5S330 emulator
+ * @return Pointer to i2c_common_emul_data from argument emul
+ */
+struct i2c_common_emul_data *
+emul_sn5s330_get_i2c_common_data(const struct emul *emul);
+
+#endif /* ZEPHYR_INCLUDE_EMUL_EMUL_SN5S330_H_ */
diff --git a/zephyr/include/emul/emul_stub_device.h b/zephyr/include/emul/emul_stub_device.h
new file mode 100644
index 0000000000..8eb8a60a28
--- /dev/null
+++ b/zephyr/include/emul/emul_stub_device.h
@@ -0,0 +1,42 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef ZEPHYR_INCLUDE_EMUL_STUB_DEVICE_H_
+#define ZEPHYR_INCLUDE_EMUL_STUB_DEVICE_H_
+
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+
+/*
+ * Needed for emulators without corresponding DEVICE_DT_DEFINE drivers
+ */
+
+struct emul_stub_dev_data {
+	/* Stub */
+};
+struct emul_stub_dev_config {
+	/* Stub */
+};
+struct emul_stub_dev_api {
+	/* Stub */
+};
+
+/* For every instance of a DT_DRV_COMPAT stub out a device for that instance */
+#define EMUL_STUB_DEVICE(n)                                                    \
+	__maybe_unused static int emul_init_stub_##n(const struct device *dev) \
+	{                                                                      \
+		ARG_UNUSED(dev);                                               \
+		return 0;                                                      \
+	}                                                                      \
+                                                                               \
+	/* Since this is only stub, allocate the structs once. */              \
+	static struct emul_stub_dev_data stub_data_##n;                        \
+	static struct emul_stub_dev_config stub_config_##n;                    \
+	static struct emul_stub_dev_api stub_api_##n;                          \
+	DEVICE_DT_INST_DEFINE(n, &emul_init_stub_##n, NULL, &stub_data_##n,    \
+			      &stub_config_##n, POST_KERNEL, 1,                \
+			      &stub_api_##n);
+
+#endif /* ZEPHYR_INCLUDE_EMUL_STUB_DEVICE_H_ */
diff --git a/zephyr/include/emul/emul_syv682x.h b/zephyr/include/emul/emul_syv682x.h
new file mode 100644
index 0000000000..3e4328323e
--- /dev/null
+++ b/zephyr/include/emul/emul_syv682x.h
@@ -0,0 +1,161 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/** @file
+ *
+ * @brief Backend API for SYV682X emulator
+ */
+
+#ifndef __EMUL_SYV682X_H
+#define __EMUL_SYV682X_H
+
+#include <stdint.h>
+
+#include <zephyr/drivers/i2c_emul.h>
+
+/* Register info copied from syv682.h */
+
+/* SYV682x register addresses */
+#define SYV682X_STATUS_REG 0x00
+#define SYV682X_CONTROL_1_REG 0x01
+#define SYV682X_CONTROL_2_REG 0x02
+#define SYV682X_CONTROL_3_REG 0x03
+#define SYV682X_CONTROL_4_REG 0x04
+
+/* Status Register */
+#define SYV682X_STATUS_OC_HV BIT(7)
+#define SYV682X_STATUS_RVS BIT(6)
+#define SYV682X_STATUS_OC_5V BIT(5)
+#define SYV682X_STATUS_OVP BIT(4)
+#define SYV682X_STATUS_FRS BIT(3)
+#define SYV682X_STATUS_TSD BIT(2)
+#define SYV682X_STATUS_VSAFE_5V BIT(1)
+#define SYV682X_STATUS_VSAFE_0V BIT(0)
+#define SYV682X_STATUS_INT_MASK 0xfc
+#define SYV682X_STATUS_NONE 0
+
+/* Control Register 1 */
+#define SYV682X_CONTROL_1_CH_SEL BIT(1)
+#define SYV682X_CONTROL_1_HV_DR BIT(2)
+#define SYV682X_CONTROL_1_PWR_ENB BIT(7)
+
+#define SYV682X_5V_ILIM_MASK 0x18
+#define SYV682X_5V_ILIM_BIT_SHIFT 3
+#define SYV682X_5V_ILIM_1_25 0
+#define SYV682X_5V_ILIM_1_75 1
+#define SYV682X_5V_ILIM_2_25 2
+#define SYV682X_5V_ILIM_3_30 3
+
+#define SYV682X_HV_ILIM_MASK 0x60
+#define SYV682X_HV_ILIM_BIT_SHIFT 5
+#define SYV682X_HV_ILIM_1_25 0
+#define SYV682X_HV_ILIM_1_75 1
+#define SYV682X_HV_ILIM_3_30 2
+#define SYV682X_HV_ILIM_5_50 3
+
+/* Control Register 2 */
+#define SYV682X_OC_DELAY_MASK GENMASK(7, 6)
+#define SYV682X_OC_DELAY_SHIFT 6
+#define SYV682X_OC_DELAY_1MS 0
+#define SYV682X_OC_DELAY_10MS 1
+#define SYV682X_OC_DELAY_50MS 2
+#define SYV682X_OC_DELAY_100MS 3
+#define SYV682X_DSG_TIME_MASK GENMASK(5, 4)
+#define SYV682X_DSG_TIME_SHIFT 4
+#define SYV682X_DSG_TIME_50MS 0
+#define SYV682X_DSG_TIME_100MS 1
+#define SYV682X_DSG_TIME_200MS 2
+#define SYV682X_DSG_TIME_400MS 3
+#define SYV682X_DSG_RON_MASK GENMASK(3, 2)
+#define SYV682X_DSG_RON_SHIFT 2
+#define SYV682X_DSG_RON_200_OHM 0
+#define SYV682X_DSG_RON_400_OHM 1
+#define SYV682X_DSG_RON_800_OHM 2
+#define SYV682X_DSG_RON_1600_OHM 3
+#define SYV682X_CONTROL_2_SDSG BIT(1)
+#define SYV682X_CONTROL_2_FDSG BIT(0)
+
+/* Control Register 3 */
+#define SYV682X_BUSY BIT(7)
+#define SYV682X_RVS_MASK BIT(3)
+#define SYV682X_RST_REG BIT(0)
+#define SYV682X_OVP_MASK 0x70
+#define SYV682X_OVP_BIT_SHIFT 4
+#define SYV682X_OVP_06_0 0
+#define SYV682X_OVP_08_0 1
+#define SYV682X_OVP_11_1 2
+#define SYV682X_OVP_12_1 3
+#define SYV682X_OVP_14_2 4
+#define SYV682X_OVP_17_9 5
+#define SYV682X_OVP_21_6 6
+#define SYV682X_OVP_23_7 7
+#define SYV682X_CONTROL_3_NONE 0
+
+/* Control Register 4 */
+#define SYV682X_CONTROL_4_CC1_BPS BIT(7)
+#define SYV682X_CONTROL_4_CC2_BPS BIT(6)
+#define SYV682X_CONTROL_4_VCONN1 BIT(5)
+#define SYV682X_CONTROL_4_VCONN2 BIT(4)
+#define SYV682X_CONTROL_4_VBAT_OVP BIT(3)
+#define SYV682X_CONTROL_4_VCONN_OCP BIT(2)
+#define SYV682X_CONTROL_4_CC_FRS BIT(1)
+#define SYV682X_CONTROL_4_INT_MASK 0x0c
+#define SYV682X_CONTROL_4_NONE 0
+
+/**
+ * @brief Set the underlying interrupt conditions affecting the SYV682x
+ *
+ * @param emul      SYV682x emulator
+ * @param status    A status register value corresponding to the underlying
+ *                  conditions
+ * @param control_4 A control 4 register value corresponding to the underlying
+ *                  conditions; only the bits in SYV682X_CONTROL_4_INT_MASK have
+ *                  an effect.
+ */
+void syv682x_emul_set_condition(const struct emul *emul, uint8_t status,
+				uint8_t control_4);
+
+/**
+ * @brief Cause CONTROL_3[BUSY] to be set for a number of reads. This bit
+ *        signals that I2C writes will be ignored. Each call overrides any
+ *        previous setting.
+ *
+ * @param emul  SYV682x emulator
+ * @param reads The number of reads of CONTROL_3 to keep BUSY set for
+ */
+void syv682x_emul_set_busy_reads(const struct emul *emul, int reads);
+
+/**
+ * @brief Set value of a register of SYV682x
+ *
+ * @param emul SYV682x emulator
+ * @param reg  Register address
+ * @param val  Value to write to the register
+ *
+ * @return 0 on success, error code on error
+ */
+int syv682x_emul_set_reg(const struct emul *emul, int reg, uint8_t val);
+
+/**
+ * @brief Get value of a register of SYV682x
+ *
+ * @param emul SYV682x emulator
+ * @param reg  Register address
+ * @param val  Pointer at which to store current value of register
+ *
+ * @return 0 on success, error code on error
+ */
+int syv682x_emul_get_reg(const struct emul *emul, int reg, uint8_t *val);
+
+/**
+ * @brief Returns pointer to i2c_common_emul_data for given emul
+ *
+ * @param emul Pointer to SYV682X emulator
+ * @return common_data Pointer to i2c_common_emul_data
+ */
+struct i2c_common_emul_data *
+emul_syv682x_get_i2c_common_data(const struct emul *emul);
+
+#endif /* __EMUL_SYV682X_H */
diff --git a/zephyr/include/emul/emul_tcs3400.h b/zephyr/include/emul/emul_tcs3400.h
new file mode 100644
index 0000000000..9daf8bce16
--- /dev/null
+++ b/zephyr/include/emul/emul_tcs3400.h
@@ -0,0 +1,157 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ *
+ * @brief Backend API for TCS3400 emulator
+ */
+
+#ifndef __EMUL_TCS3400_H
+#define __EMUL_TCS3400_H
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/i2c_emul.h>
+
+/**
+ * @brief TCS3400 emulator backend API
+ * @defgroup tcs_emul TCS3400 emulator
+ * @{
+ *
+ * TCS3400 emulator supports responses to all write and read I2C messages.
+ * Light sensor data registers are obtained from internal emulator state, gain
+ * and acquisition time. Application may alter emulator state:
+ *
+ * - define a devicetree overlay file to set which inadvisable driver behaviour
+ *   should be treated as error and emulated device ID and revision
+ * - call @ref tcs_emul_set_reg and @ref tcs_emul_get_reg to set and get value
+ *   of TCS3400 registers
+ * - call @ref tcs_emul_set_val and @ref tcs_emul_set_val to set and get
+ *   light sensor value
+ * - call tcs_emul_set_err_* to change emulator behaviour on inadvisable driver
+ *   behaviour
+ * - call functions from emul_common_i2c.h to setup custom handlers for I2C
+ *   messages
+ */
+
+/**
+ * Maximum number of integration cycles (when ATIME is zero). Value read from
+ * sensor is proportional to number of integration cycles, e.g. with constant
+ * light, value obtainded with 128 cycles will be two times smaller than value
+ * obtained with 256 cycles.
+ */
+#define TCS_EMUL_MAX_CYCLES 256
+/**
+ * Maximum gain supported by TCS3400. Value read from sensor is multiplied by
+ * gain selected in CONTROL register.
+ */
+#define TCS_EMUL_MAX_GAIN 64
+
+/**
+ * Emulator units are value returned with gain x64 and 256 integration cycles.
+ * Max value is 1024 returned when gain is x1 and 1 integration cycle. Max value
+ * represented in emulator units is 1024 * 64 * 256
+ */
+#define TCS_EMUL_MAX_VALUE (1024 * TCS_EMUL_MAX_GAIN * TCS_EMUL_MAX_CYCLES)
+
+/** Axis argument used in @ref tcs_emul_set_val @ref tcs_emul_get_val */
+enum tcs_emul_axis {
+	TCS_EMUL_R,
+	TCS_EMUL_G,
+	TCS_EMUL_B,
+	TCS_EMUL_C,
+	TCS_EMUL_IR,
+};
+
+/**
+ * Emulator saves only those registers in memory. IR select is stored sparately
+ * and other registers are write only.
+ */
+#define TCS_EMUL_FIRST_REG TCS_I2C_ENABLE
+#define TCS_EMUL_LAST_REG TCS_I2C_BDATAH
+#define TCS_EMUL_REG_COUNT (TCS_EMUL_LAST_REG - TCS_EMUL_FIRST_REG + 1)
+
+/**
+ * @brief Set value of given register of TCS3400
+ *
+ * @param emul Pointer to TCS3400 emulator
+ * @param reg Register address which value will be changed
+ * @param val New value of the register
+ */
+void tcs_emul_set_reg(const struct emul *emul, int reg, uint8_t val);
+
+/**
+ * @brief Get value of given register of TCS3400
+ *
+ * @param emul Pointer to TCS3400 emulator
+ * @param reg Register address
+ *
+ * @return Value of the register
+ */
+uint8_t tcs_emul_get_reg(const struct emul *emul, int reg);
+
+/**
+ * @brief Get internal value of light sensor for given axis
+ *
+ * @param emul Pointer to TCS3400 emulator
+ * @param axis Axis to access
+ *
+ * @return Value of given axis with gain x64 and 256 integration cycles
+ */
+int tcs_emul_get_val(const struct emul *emul, enum tcs_emul_axis axis);
+
+/**
+ * @brief Set internal value of light sensor for given axis
+ *
+ * @param emul Pointer to TCS3400 emulator
+ * @param axis Axis to access
+ * @param val New value of light sensor for given axis with gain x64 and
+ *            256 integration cycles
+ */
+void tcs_emul_set_val(const struct emul *emul, enum tcs_emul_axis axis,
+		      int val);
+
+/**
+ * @brief Set if error should be generated when read only register is being
+ *        written
+ *
+ * @param emul Pointer to TCS3400 emulator
+ * @param set Check for this error
+ */
+void tcs_emul_set_err_on_ro_write(const struct emul *emul, bool set);
+
+/**
+ * @brief Set if error should be generated when reserved bits of register are
+ *        not set to 0 on write I2C message
+ *
+ * @param emul Pointer to TCS3400 emulator
+ * @param set Check for this error
+ */
+void tcs_emul_set_err_on_rsvd_write(const struct emul *emul, bool set);
+
+/**
+ * @brief Set if error should be generated when MSB register is accessed before
+ *        LSB register
+ *
+ * @param emul Pointer to TCS3400 emulator
+ * @param set Check for this error
+ */
+void tcs_emul_set_err_on_msb_first(const struct emul *emul, bool set);
+
+/**
+ * @brief Returns pointer to i2c_common_emul_data for argument emul
+ *
+ * @param emul Pointer to tcs3400 emulator
+ * @return Pointer to i2c_common_emul_data from argument emul
+ */
+struct i2c_common_emul_data *
+emul_tcs3400_get_i2c_common_data(const struct emul *emul);
+
+/**
+ * @}
+ */
+
+#endif /* __EMUL_TCS3400_H */
diff --git a/zephyr/include/emul/emul_tusb1064.h b/zephyr/include/emul/emul_tusb1064.h
new file mode 100644
index 0000000000..99732e36c9
--- /dev/null
+++ b/zephyr/include/emul/emul_tusb1064.h
@@ -0,0 +1,13 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef EMUL_TUSB1064_H
+#define EMUL_TUSB1064_H
+
+#include <zephyr/drivers/emul.h>
+
+int tusb1064_emul_peek_reg(const struct emul *emul, int reg);
+
+#endif
diff --git a/zephyr/include/emul/i2c_mock.h b/zephyr/include/emul/i2c_mock.h
new file mode 100644
index 0000000000..e5c359a3fd
--- /dev/null
+++ b/zephyr/include/emul/i2c_mock.h
@@ -0,0 +1,44 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef ZEPHYR_INCLUDE_EMUL_I2C_MOCK_H_
+#define ZEPHYR_INCLUDE_EMUL_I2C_MOCK_H_
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/i2c_emul.h>
+
+/**
+ * @brief reset the I2C mock.
+ *
+ * @param emul The mock device to reset.
+ */
+void i2c_mock_reset(const struct emul *emul);
+
+/**
+ * @brief Get the i2c emulator pointer from the top level mock.
+ *
+ * @param emul The mock device to query
+ * @return Pointer to the i2c emulator struct
+ */
+struct i2c_emul *i2c_mock_to_i2c_emul(const struct emul *emul);
+
+/**
+ * @brief Get the I2C address of the mock
+ *
+ * @param emul The mock device to query
+ * @return The address on the I2C bus
+ */
+uint16_t i2c_mock_get_addr(const struct emul *emul);
+
+/**
+ * @brief Returns pointer to i2c_common_emul_data for argument emul
+ *
+ * @param emul Pointer to i2c_mock emulator
+ * @return Pointer to i2c_common_emul_data from argument emul
+ */
+struct i2c_common_emul_data *
+emul_i2c_mock_get_i2c_common_data(const struct emul *emul);
+
+#endif /* ZEPHYR_INCLUDE_EMUL_I2C_MOCK_H_ */
diff --git a/zephyr/include/emul/retimer/emul_anx7483.h b/zephyr/include/emul/retimer/emul_anx7483.h
new file mode 100644
index 0000000000..f2b7fe32d4
--- /dev/null
+++ b/zephyr/include/emul/retimer/emul_anx7483.h
@@ -0,0 +1,136 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __EMUL_ANX7483_H
+#define __EMUL_ANX7483_H
+
+#include "driver/retimer/anx7483.h"
+#include "driver/retimer/anx7483_public.h"
+#include "emul/emul_common_i2c.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/i2c_emul.h>
+
+#define ANX7483_LFPS_TIMER_REG_RESERVED_MASK GENMASK(7, 4)
+#define ANX7483_ANALOG_STATUS_CTRL_REG_RESERVED_MASK \
+	(GENMASK(7, 6) | GENMASK(3, 3))
+#define ANX7483_ENABLE_EQ_FLAT_SWING_REG_RESERVED_MASK GENMASK(7, 1)
+#define ANX7483_AUX_SNOOPING_CTRL_REG_RESERVED_MASK GENMASK(7, 3)
+
+#define ANX7483_UTX1_PORT_CFG0_REG_RESERVED_MASK GENMASK(3, 0)
+#define ANX7483_UTX2_PORT_CFG0_REG_RESERVED_MASK GENMASK(3, 0)
+#define ANX7483_URX1_PORT_CFG0_REG_RESERVED_MASK GENMASK(3, 0)
+#define ANX7483_URX2_PORT_CFG0_REG_RESERVED_MASK GENMASK(3, 0)
+#define ANX7483_DRX1_PORT_CFG0_REG_RESERVED_MASK GENMASK(3, 0)
+#define ANX7483_DRX2_PORT_CFG0_REG_RESERVED_MASK GENMASK(3, 0)
+
+#define ANX7483_UTX1_PORT_CFG2_REG_RESERVED_MASK GENMASK(3, 0)
+#define ANX7483_UTX2_PORT_CFG2_REG_RESERVED_MASK GENMASK(3, 0)
+#define ANX7483_URX1_PORT_CFG2_REG_RESERVED_MASK GENMASK(3, 0)
+#define ANX7483_URX2_PORT_CFG2_REG_RESERVED_MASK GENMASK(3, 0)
+#define ANX7483_DRX1_PORT_CFG2_REG_RESERVED_MASK GENMASK(3, 0)
+#define ANX7483_DRX2_PORT_CFG2_REG_RESERVED_MASK GENMASK(3, 0)
+
+/*
+ * See b/230694492#comment12 for why CFG3 doesn't have any reserved bits,
+ * contrary to what the documentation says.
+ */
+
+#define ANX7483_UTX1_PORT_CFG4_REG_RESERVED_MASK (GENMASK(7, 5) | GENMASK(3, 2))
+#define ANX7483_UTX2_PORT_CFG4_REG_RESERVED_MASK (GENMASK(7, 5) | GENMASK(3, 2))
+#define ANX7483_URX1_PORT_CFG4_REG_RESERVED_MASK (GENMASK(7, 5) | GENMASK(3, 2))
+#define ANX7483_URX2_PORT_CFG4_REG_RESERVED_MASK (GENMASK(7, 5) | GENMASK(3, 2))
+#define ANX7483_DRX1_PORT_CFG4_REG_RESERVED_MASK (GENMASK(7, 5) | GENMASK(3, 2))
+#define ANX7483_DRX2_PORT_CFG4_REG_RESERVED_MASK (GENMASK(7, 5) | GENMASK(3, 2))
+#define ANX7483_DTX1_PORT_CFG4_REG_RESERVED_MASK (GENMASK(7, 5) | GENMASK(3, 2))
+#define ANX7483_DTX2_PORT_CFG4_REG_RESERVED_MASK (GENMASK(7, 5) | GENMASK(3, 2))
+
+#define ANX7483_LFPS_TIMER_REG_DEFAULT 0x00
+#define ANX7483_ANALOG_STATUS_CTRL_REG_DEFAULT 0x20
+#define ANX7483_ENABLE_EQ_FLAT_SWING_REG_DEFAULT 0x00
+#define ANX7483_AUX_SNOOPING_CTRL_REG_DEFAULT ANX7483_AUX_SNOOPING_DEF
+
+#define ANX7483_UTX1_PORT_CFG0_REG_DEFAULT ANX7483_CFG0_DEF
+#define ANX7483_UTX2_PORT_CFG0_REG_DEFAULT ANX7483_CFG0_DEF
+#define ANX7483_URX1_PORT_CFG0_REG_DEFAULT ANX7483_CFG0_DEF
+#define ANX7483_URX2_PORT_CFG0_REG_DEFAULT ANX7483_CFG0_DEF
+#define ANX7483_DRX1_PORT_CFG0_REG_DEFAULT ANX7483_CFG0_DEF
+#define ANX7483_DRX2_PORT_CFG0_REG_DEFAULT ANX7483_CFG0_DEF
+
+#define ANX7483_UTX1_PORT_CFG1_REG_DEFAULT ANX7483_CFG1_DEF
+#define ANX7483_UTX2_PORT_CFG1_REG_DEFAULT ANX7483_CFG1_DEF
+#define ANX7483_URX1_PORT_CFG1_REG_DEFAULT ANX7483_CFG1_DEF
+#define ANX7483_URX2_PORT_CFG1_REG_DEFAULT ANX7483_CFG1_DEF
+#define ANX7483_DRX1_PORT_CFG1_REG_DEFAULT ANX7483_CFG1_DEF
+#define ANX7483_DRX2_PORT_CFG1_REG_DEFAULT ANX7483_CFG1_DEF
+
+#define ANX7483_UTX1_PORT_CFG2_REG_DEFAULT ANX7483_CFG2_DEF
+#define ANX7483_UTX2_PORT_CFG2_REG_DEFAULT ANX7483_CFG2_DEF
+#define ANX7483_URX1_PORT_CFG2_REG_DEFAULT ANX7483_CFG2_DEF
+#define ANX7483_URX2_PORT_CFG2_REG_DEFAULT ANX7483_CFG2_DEF
+#define ANX7483_DRX1_PORT_CFG2_REG_DEFAULT ANX7483_CFG2_DEF
+#define ANX7483_DRX2_PORT_CFG2_REG_DEFAULT ANX7483_CFG2_DEF
+
+#define ANX7483_UTX1_PORT_CFG3_REG_DEFAULT 0x02
+#define ANX7483_UTX2_PORT_CFG3_REG_DEFAULT 0x02
+#define ANX7483_URX1_PORT_CFG3_REG_DEFAULT 0x02
+#define ANX7483_URX2_PORT_CFG3_REG_DEFAULT 0x02
+#define ANX7483_DRX1_PORT_CFG3_REG_DEFAULT 0x02
+#define ANX7483_DRX2_PORT_CFG3_REG_DEFAULT 0x02
+#define ANX7483_DTX1_PORT_CFG3_REG_DEFAULT 0x02
+#define ANX7483_DTX2_PORT_CFG3_REG_DEFAULT 0x02
+
+#define ANX7483_UTX1_PORT_CFG4_REG_DEFAULT 0x62
+#define ANX7483_UTX2_PORT_CFG4_REG_DEFAULT 0x62
+#define ANX7483_URX1_PORT_CFG4_REG_DEFAULT 0x62
+#define ANX7483_URX2_PORT_CFG4_REG_DEFAULT 0x62
+#define ANX7483_DRX1_PORT_CFG4_REG_DEFAULT 0x62
+#define ANX7483_DRX2_PORT_CFG4_REG_DEFAULT 0x62
+#define ANX7483_DTX1_PORT_CFG4_REG_DEFAULT 0x62
+#define ANX7483_DTX2_PORT_CFG4_REG_DEFAULT 0x62
+
+#define ANX7483_REG_MAX (ANX7483_DRX1_PORT_CFG4_REG + 1)
+
+/* Constant configuration of the emulator */
+struct anx7483_emul_cfg {
+	const struct i2c_common_emul_cfg common;
+};
+
+struct anx7483_register {
+	uint8_t reg;
+	uint8_t value;
+	uint8_t def;
+	uint8_t reserved;
+};
+
+struct anx7483_emul_data {
+	struct i2c_common_emul_data common;
+
+	struct anx7483_register regs[ANX7483_REG_MAX];
+};
+
+int anx7483_emul_get_reg(const struct emul *emul, int r, uint8_t *val);
+int anx7483_emul_set_reg(const struct emul *emul, int r, uint8_t val);
+
+/*
+ * Some bits that are marked as reserved are used for board-specific tuning.
+ * This function allows board tests to pass by allowing them to update reserved
+ * masks for their use cases.
+ */
+int anx7483_emul_set_reg_reserved_mask(const struct emul *emul, int r,
+				       uint8_t mask, uint8_t def);
+
+int anx7483_emul_get_eq(const struct emul *emul, enum anx7483_tune_pin pin,
+			enum anx7483_eq_setting *eq);
+
+void anx7483_emul_reset(const struct emul *emul);
+
+int anx7483_emul_validate_tuning(const struct emul *emul,
+				 const struct anx7483_tuning_set *tuning,
+				 size_t tuning_count);
+
+#endif /* __EMUL_ANX7483_H */
diff --git a/zephyr/include/emul/retimer/emul_ps8811.h b/zephyr/include/emul/retimer/emul_ps8811.h
new file mode 100644
index 0000000000..f26c4b5e84
--- /dev/null
+++ b/zephyr/include/emul/retimer/emul_ps8811.h
@@ -0,0 +1,64 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __EMUL_PS8811_H
+#define __EMUL_PS8811_H
+
+#include "driver/retimer/ps8811.h"
+#include "emul/emul_common_i2c.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/i2c_emul.h>
+
+#define PS811_REG1_MAX (PS8811_REG1_USB_CHAN_B_DE_PS_MSB + 1)
+
+#define PS8811_REG1_USB_CHAN_A_SWING_RESERVED_MASK \
+	(GENMASK(7, 7) | GENMASK(3, 0))
+#define PS8811_REG1_50OHM_ADJUST_CHAN_B_RESERVED_MASK GENMASK(7, 4)
+#define PS8811_REG1_USB_CHAN_B_SWING_RESERVED_MASK GENMASK(7, 3)
+#define PS8811_REG1_USB_CHAN_B_DE_PS_LSB_RESERVED_MASK GENMASK(7, 3)
+#define PS8811_REG1_USB_CHAN_B_DE_PS_MSB_RESERVED_MASK GENMASK(7, 5)
+
+#define PS8811_REG1_USB_AEQ_LEVEL_DEFAULT 0x37
+#define PS8811_REG1_USB_ADE_CONFIG_DEFAULT 0x80
+#define PS8811_REG1_USB_BEQ_LEVEL_DEFAULT 0x26
+#define PS8811_REG1_USB_BDE_CONFIG_DEFAULT 0x80
+#define PS8811_REG1_USB_CHAN_A_SWING_DEFAULT 0x00
+#define PS8811_REG1_50OHM_ADJUST_CHAN_B_DEFAULT 0x00
+#define PS8811_REG1_USB_CHAN_B_SWING_DEFAULT 0x02
+#define PS8811_REG1_USB_CHAN_B_DE_PS_LSB_DEFAULT 0x82
+#define PS8811_REG1_USB_CHAN_B_DE_PS_MSB_DEFAULT 0x13
+
+/* Constant configuration of the emulator */
+struct ps8811_emul_cfg {
+	/*
+	 * Each page of the PS8811's register map is located at a different I2C
+	 * address.
+	 */
+	const struct i2c_common_emul_cfg p0_cfg;
+	const struct i2c_common_emul_cfg p1_cfg;
+};
+
+/*  Run-time data used by the emulator */
+struct ps8811_emul_data {
+	/* I2C data for each page of the register map. */
+	struct i2c_common_emul_data p0_data;
+	struct i2c_common_emul_data p1_data;
+
+	/* Page 1 registers */
+	uint8_t p1_regs[PS811_REG1_MAX];
+};
+
+int ps8811_emul_get_reg0(const struct emul *emulator, int reg, uint8_t *val);
+int ps8811_emul_set_reg0(const struct emul *emulator, int reg, uint8_t val);
+
+int ps8811_emul_get_reg1(const struct emul *emulator, int reg, uint8_t *val);
+int ps8811_emul_set_reg1(const struct emul *emulator, int reg, uint8_t val);
+
+void ps8811_emul_reset(const struct emul *emul);
+
+#endif /* __EMUL_PS8811_H */
diff --git a/zephyr/include/emul/tcpc/emul_nct38xx.h b/zephyr/include/emul/tcpc/emul_nct38xx.h
new file mode 100644
index 0000000000..be300d9427
--- /dev/null
+++ b/zephyr/include/emul/tcpc/emul_nct38xx.h
@@ -0,0 +1,22 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __EMUL_NCT38XX_H
+#define __EMUL_NCT38XX_H
+
+#include <zephyr/drivers/emul.h>
+
+#define NCT38XX_REG_CTRL_OUT_EN_DEFAULT 0x00
+#define NCT38XX_REG_CTRL_OUT_EN_RESERVED_MASK GENMASK(7, 7)
+
+#define NCT38XX_REG_VBC_FAULT_CTL_DEFAULT 0x01
+#define NCT38XX_REG_VBC_FAULT_CTL_RESERVED_MASK (GENMASK(7, 6) | GENMASK(2, 2))
+
+int nct38xx_emul_get_reg(const struct emul *emul, int r, uint16_t *val);
+int nct38xx_emul_set_reg(const struct emul *emul, int r, uint16_t val);
+
+void nct38xx_emul_reset(const struct emul *emul);
+
+#endif /* __EMUL_NCT38XX_H */
diff --git a/zephyr/include/emul/tcpc/emul_ps8xxx.h b/zephyr/include/emul/tcpc/emul_ps8xxx.h
new file mode 100644
index 0000000000..eb49221fd2
--- /dev/null
+++ b/zephyr/include/emul/tcpc/emul_ps8xxx.h
@@ -0,0 +1,161 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ *
+ * @brief Backend API for PS8xxx emulator
+ */
+
+#ifndef __EMUL_PS8XXX_H
+#define __EMUL_PS8XXX_H
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/i2c_emul.h>
+
+/**
+ * @brief PS8xxx emulator backend API
+ * @defgroup ps8xxx_emul PS8xxx emulator
+ * @{
+ *
+ * PS8xxx emulator is extension for the TCPCI emulator. It is able to emulate
+ * PS8805 and PS8815 devices. It registers "hidden" I2C devices with the I2C
+ * emulation controller.
+ * Application may alter emulator state:
+ *
+ * - call @ref ps8xxx_emul_set_product_id to select which device is emulated
+ *   (PS8805 or PS8815)
+ * - call @ref ps8xxx_emul_get_tcpci to get TCPCI emulator pointer that is used
+ *   as base for PS8xxx emulator. The pointer can be used in tcpci_emul_*
+ *   functions.
+ * - call @ref ps8xxx_emul_get_i2c_emul to get "hidden" I2C device (port 0, 1
+ *   or GPIO)
+ * - call @ref ps8xxx_emul_set_chip_rev to set PS8805 chip revision
+ * - call @ref ps8xxx_emul_set_hw_rev to set PS8815 HW revision
+ * - call @ref ps8xxx_emul_set_gpio_ctrl to set GPIO control register
+ */
+
+/** Types of "hidden" I2C devices */
+enum ps8xxx_emul_port {
+	PS8XXX_EMUL_PORT_0,
+	PS8XXX_EMUL_PORT_1,
+	PS8XXX_EMUL_PORT_GPIO,
+	PS8XXX_EMUL_PORT_INVAL,
+};
+
+/**
+ * Register ID to distinguish between the PS8815-A2 and PS8745-A2
+ * 0: Indicates this is an 8815-A2 chip
+ * 1: Indicates this is an 8745-A2 chip
+ */
+enum ps8xxx_regid {
+	PS8815_REG_ID,
+	PS8745_REG_ID,
+};
+
+/* For now all devices supported by this emulator has the same FW rev reg */
+#define PS8XXX_REG_FW_REV 0x82
+
+/**
+ * @brief Get pointer to i2c_common_data for specific "hidden" I2C device
+ *
+ * @param emul Pointer to PS8xxx emulator
+ * @param port Select which "hidden" I2C device should be obtained
+ *
+ * @return NULL if given "hidden" I2C device cannot be found
+ * @return pointer to "hidden" device i2c_common_emul_data
+ */
+struct i2c_common_emul_data *
+ps8xxx_emul_get_i2c_common_data(const struct emul *emul,
+				enum ps8xxx_emul_port port);
+
+/**
+ * @brief Get pointer to TCPCI emulator that is base for PS8xxx emulator
+ *
+ * @param emul Pointer to PS8xxx emulator
+ *
+ * @return pointer to TCPCI emulator
+ */
+const struct emul *ps8xxx_emul_get_tcpci(const struct emul *emul);
+
+/**
+ * @brief Set value of chip revision register on PS8805
+ *
+ * @param emul Pointer to PS8xxx emulator
+ * @param chip_rev Value to be set
+ */
+void ps8xxx_emul_set_chip_rev(const struct emul *emul, uint8_t chip_rev);
+
+/**
+ * @brief Set value of REG_ID used to distinguish between the
+ *	  PS8815-A2 and PS8745-A2
+ *
+ * @param emul Pointer to PS8xxx emulator
+ * @param reg_id Value to be set
+ */
+void ps8xxx_emul_set_reg_id(const struct emul *emul, enum ps8xxx_regid reg_id);
+
+/**
+ * @brief Set value of HW revision register on PS8815
+ *
+ * @param emul Pointer to PS8xxx emulator
+ * @param hw_rev Value to be set
+ */
+void ps8xxx_emul_set_hw_rev(const struct emul *emul, uint16_t hw_rev);
+
+/**
+ * @brief Set value of GPIO control register
+ *
+ * @param emul Pointer to PS8xxx emulator
+ * @param gpio_ctrl Value to be set
+ */
+void ps8xxx_emul_set_gpio_ctrl(const struct emul *emul, uint8_t gpio_ctrl);
+
+/**
+ * @brief Get value of GPIO control register
+ *
+ * @param emul Pointer to PS8xxx emulator
+ *
+ * @return Value of GPIO control register
+ */
+uint8_t ps8xxx_emul_get_gpio_ctrl(const struct emul *emul);
+
+/**
+ * @brief Get value of mux usb DCI configuration register
+ *
+ * @param emul Pointer to PS8xxx emulator
+ *
+ * @return Value of mux usb DCI configuration register
+ */
+uint8_t ps8xxx_emul_get_dci_cfg(const struct emul *emul);
+
+/**
+ * @brief Set product ID of emulated PS8xxx device. This change behaviour
+ *        of emulator to mimic that device. Currently supported are PS8805 and
+ *        PS8815
+ *
+ * @param emul Pointer to PS8xxx emulator
+ * @param product_id Value to be set
+ *
+ * @return 0 on success
+ * @return -EINVAL when unsupported product ID is selected
+ */
+int ps8xxx_emul_set_product_id(const struct emul *emul, uint16_t product_id);
+
+/**
+ * @brief Get product ID of emulated PS8xxx device
+ *
+ * @param emul Pointer to PS8xxx emulator
+ *
+ * @return Product ID of emulated PS8xxx device
+ */
+uint16_t ps8xxx_emul_get_product_id(const struct emul *emul);
+
+/**
+ * @}
+ */
+
+#endif /* __EMUL_PS8XXX */
diff --git a/zephyr/include/emul/tcpc/emul_rt1718s.h b/zephyr/include/emul/tcpc/emul_rt1718s.h
new file mode 100644
index 0000000000..332ee3d2da
--- /dev/null
+++ b/zephyr/include/emul/tcpc/emul_rt1718s.h
@@ -0,0 +1,77 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __EMUL_RT1718S_H
+#define __EMUL_RT1718S_H
+
+#include "emul/tcpc/emul_tcpci.h"
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/sys/slist.h>
+
+#define RT1718S_EMUL_REG_COUNT_PER_PAGE 0x100
+
+struct set_reg_entry_t {
+	struct _snode node;
+	int reg;
+	uint16_t val;
+	int64_t access_time;
+};
+
+/** Run-time data used by the emulator */
+struct rt1718s_emul_data {
+	/* Composite with the tcpc_emul_data to extend it. */
+	struct tcpc_emul_data embedded_tcpc_emul_data;
+	uint8_t reg_page1[RT1718S_EMUL_REG_COUNT_PER_PAGE];
+	uint8_t reg_page2[RT1718S_EMUL_REG_COUNT_PER_PAGE];
+	uint8_t current_page;
+	uint8_t current_page2_register;
+	struct _slist set_private_reg_history;
+};
+
+/**
+ * @brief Getting each byte of register from rt1718s emulator
+ *
+ * @param emul Pointer to I2C rt1718s emulator
+ * @param reg First byte of last write message
+ * @param val Pointer where byte to read should be stored
+ *
+ * @return 0 on success
+ * @return -EINVAL when register is out of range defined in rt1718s private
+ *                 register or val is NULL
+ */
+int rt1718s_emul_get_reg(const struct emul *emul, int reg, uint16_t *val);
+
+/**
+ * @brief Setting each byte of register from rt1718s emulator
+ *
+ * @param emul Pointer to I2C rt1718s emulator
+ * @param reg First byte of last write message
+ * @param val byte to write to the reg in emulator
+ *
+ * @return 0 on success
+ * @return -EINVAL when register is out of range defined in rt1718s private
+ *                 register or val is NULL
+ */
+int rt1718s_emul_set_reg(const struct emul *emul, int reg, uint16_t val);
+
+/**
+ * @brief Reset the register set history
+ *
+ * @param emul Pointer to I2C rt1718s emulator
+ *
+ */
+void rt1718s_emul_reset_set_history(const struct emul *emul);
+
+/**
+ * @brief Set the device id of
+ *
+ * @param emul Pointer to I2C rt1718s emulator
+ * @param device_id the 16 bits device id
+ *
+ */
+void rt1718s_emul_set_device_id(const struct emul *emul, uint16_t device_id);
+
+#endif /* __EMUL_RT1718S_H */
diff --git a/zephyr/include/emul/tcpc/emul_tcpci.h b/zephyr/include/emul/tcpc/emul_tcpci.h
new file mode 100644
index 0000000000..deaafd925a
--- /dev/null
+++ b/zephyr/include/emul/tcpc/emul_tcpci.h
@@ -0,0 +1,403 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ *
+ * @brief Backend API for TCPCI emulator
+ */
+
+#ifndef __EMUL_TCPCI_H
+#define __EMUL_TCPCI_H
+
+#include "emul/emul_common_i2c.h"
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/i2c_emul.h>
+
+#include <usb_pd_tcpm.h>
+
+/**
+ * Number of emulated register. This include vendor registers defined in TCPCI
+ * specification
+ */
+#define TCPCI_EMUL_REG_COUNT 0x100
+
+/** SOP message structure */
+struct tcpci_emul_msg {
+	/** Pointer to buffer for header and message */
+	uint8_t *buf;
+	/** Number of bytes in buf */
+	int cnt;
+	/** Type of message (SOP, SOP', etc) */
+	uint8_t sop_type;
+	/** Index used to mark accessed byte */
+	int idx;
+	/** Pointer to optional second message */
+	struct tcpci_emul_msg *next;
+};
+
+/**
+ * @brief Function type that is used by TCPCI emulator to provide information
+ *        about alert line state
+ *
+ * @param emul Pointer to emulator
+ * @param alert State of alert line (false - low, true - high)
+ * @param data Pointer to custom function data
+ */
+typedef void (*tcpci_emul_alert_state_func)(const struct emul *emul, bool alert,
+					    void *data);
+
+/** Run-time data used by the emulator */
+struct tcpci_ctx {
+	/** Common I2C data for TCPC */
+	struct i2c_common_emul_data common;
+
+	/** Current state of all emulated TCPCI registers */
+	uint8_t reg[TCPCI_EMUL_REG_COUNT];
+
+	/** Structures representing TX and RX buffers */
+	struct tcpci_emul_msg *rx_msg;
+	struct tcpci_emul_msg *tx_msg;
+
+	/** Data that should be written to register (except TX_BUFFER) */
+	uint16_t write_data;
+
+	/** Return error when trying to write to RO register */
+	bool error_on_ro_write;
+	/** Return error when trying to write 1 to reserved bit */
+	bool error_on_rsvd_write;
+
+	/** User function called when alert line could change */
+	tcpci_emul_alert_state_func alert_callback;
+	/** Data passed to alert_callback */
+	void *alert_callback_data;
+
+	/** Callbacks for TCPCI partner */
+	const struct tcpci_emul_partner_ops *partner;
+
+	/** Reference to Alert# GPIO emulator. */
+	struct gpio_dt_spec irq_gpio;
+};
+
+/** Run-time data used by the emulator */
+struct tcpc_emul_data {
+	/** Pointer to the common TCPCI emulator context */
+	struct tcpci_ctx *tcpci_ctx;
+
+	/** Pointer to chip specific data */
+	void *chip_data;
+
+	const struct i2c_common_emul_cfg i2c_cfg;
+};
+
+#define TCPCI_EMUL_DEFINE(n, init, cfg_ptr, chip_data_ptr, bus_api,          \
+			  backend_api)                                       \
+	static uint8_t tcpci_emul_tx_buf_##n[128];                           \
+	static struct tcpci_emul_msg tcpci_emul_tx_msg_##n = {               \
+		.buf = tcpci_emul_tx_buf_##n,                                \
+	};                                                                   \
+	static struct tcpci_ctx tcpci_ctx##n = {                             \
+		.tx_msg = &tcpci_emul_tx_msg_##n,                            \
+		.error_on_ro_write = true,                                   \
+		.error_on_rsvd_write = true,                                 \
+		.irq_gpio = GPIO_DT_SPEC_INST_GET_OR(n, irq_gpios, {}),      \
+	};                                                                   \
+	static struct tcpc_emul_data tcpc_emul_data_##n = {                \
+		.tcpci_ctx = &tcpci_ctx##n,                                \
+		.chip_data = chip_data_ptr,                                \
+		.i2c_cfg = {                                               \
+			.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)),    \
+			.data = &tcpci_ctx##n.common,                      \
+			.addr = DT_INST_REG_ADDR(n),                       \
+		},                                                         \
+	}; \
+	EMUL_DT_INST_DEFINE(n, init, &tcpc_emul_data_##n, cfg_ptr, bus_api,  \
+			    backend_api)
+
+/** Response from TCPCI specific device operations */
+enum tcpci_emul_ops_resp {
+	TCPCI_EMUL_CONTINUE = 0,
+	TCPCI_EMUL_DONE,
+	TCPCI_EMUL_ERROR
+};
+
+/** Revisions supported by TCPCI emaluator */
+enum tcpci_emul_rev { TCPCI_EMUL_REV1_0_VER1_0 = 0, TCPCI_EMUL_REV2_0_VER1_1 };
+
+/** Status of TX message send to TCPCI emulator partner */
+enum tcpci_emul_tx_status {
+	TCPCI_EMUL_TX_SUCCESS = 0,
+	TCPCI_EMUL_TX_DISCARDED,
+	TCPCI_EMUL_TX_FAILED,
+	TCPCI_EMUL_TX_CABLE_HARD_RESET,
+	/*
+	 * This is not real status. It is used to log unusual situation outside
+	 * the TCPCI spec.
+	 */
+	TCPCI_EMUL_TX_UNKNOWN
+};
+
+/** TCPCI partner operations. Not all of them need to be implemented. */
+struct tcpci_emul_partner_ops {
+	/**
+	 * @brief Function called when TCPM wants to transmit message to partner
+	 *        connected to TCPCI
+	 *
+	 * @param emul Pointer to TCPCI emulator
+	 * @param ops Pointer to partner operations structure
+	 * @param tx_msg Pointer to TX message buffer
+	 * @param type Type of message
+	 * @param retry Count of retries
+	 */
+	void (*transmit)(const struct emul *emul,
+			 const struct tcpci_emul_partner_ops *ops,
+			 const struct tcpci_emul_msg *tx_msg,
+			 enum tcpci_msg_type type, int retry);
+
+	/**
+	 * @brief Function called when control settings change to allow partner
+	 *        to react
+	 *
+	 * @param emul Pointer to TCPCI emulator
+	 * @param ops Pointer to partner operations structure
+	 */
+	void (*control_change)(const struct emul *emul,
+			       const struct tcpci_emul_partner_ops *ops);
+
+	/**
+	 * @brief Function called when TCPM consumes message send by partner
+	 *
+	 * @param emul Pointer to TCPCI emulator
+	 * @param ops Pointer to partner operations structure
+	 * @param rx_msg Message that was consumed by TCPM
+	 */
+	void (*rx_consumed)(const struct emul *emul,
+			    const struct tcpci_emul_partner_ops *ops,
+			    const struct tcpci_emul_msg *rx_msg);
+
+	/**
+	 * @brief Function called when partner is disconnected from TCPCI
+	 *
+	 * @param emul Pointer to TCPCI emulator
+	 * @param ops Pointer to partner operations structure
+	 */
+	void (*disconnect)(const struct emul *emul,
+			   const struct tcpci_emul_partner_ops *ops);
+};
+
+/**
+ * @brief Set value of given register of TCPCI
+ *
+ * @param emul Pointer to TCPC emulator
+ * @param reg Register address which value will be changed
+ * @param val New value of the register
+ *
+ * @return 0 on success
+ * @return -EINVAL when register is out of range defined in TCPCI specification
+ */
+int tcpci_emul_set_reg(const struct emul *emul, int reg, uint16_t val);
+
+/**
+ * @brief Function called for each byte of read message from TCPCI
+ *
+ * @param emul Pointer to TCPC emulator
+ * @param reg First byte of last write message
+ * @param val Pointer where byte to read should be stored
+ * @param bytes Number of bytes already readded
+ *
+ * @return 0 on success
+ */
+int tcpci_emul_read_byte(const struct emul *emul, int reg, uint8_t *val,
+			 int bytes);
+
+/**
+ * @brief Function called for each byte of write message from TCPCI.
+ *        Data are stored in write_data field of tcpci_emul_data or in tx_msg
+ *        in case of writing to TX buffer.
+ *
+ * @param emul Pointer to TCPC emulator
+ * @param reg First byte of write message
+ * @param val Received byte of write message
+ * @param bytes Number of bytes already received
+ *
+ * @return 0 on success
+ * @return -EIO on invalid write to TX buffer
+ */
+int tcpci_emul_write_byte(const struct emul *emul, int reg, uint8_t val,
+			  int bytes);
+
+/**
+ * @brief Handle I2C write message. It is checked if accessed register isn't RO
+ *        and reserved bits are set to 0.
+ *
+ * @param emul Pointer to TCPC emulator
+ * @param reg Register which is written
+ * @param msg_len Length of handled I2C message
+ *
+ * @return 0 on success
+ * @return -EIO on error
+ */
+int tcpci_emul_handle_write(const struct emul *emul, int reg, int msg_len);
+
+/**
+ * @brief Set up a new TCPCI emulator
+ *
+ * This should be called for each TCPC device that needs to be
+ * registered on the I2C bus.
+ *
+ * @param emul Pointer to TCPC emulator
+ * @param parent Pointer to emulated I2C bus
+ */
+void tcpci_emul_i2c_init(const struct emul *emul, const struct device *i2c_dev);
+
+/**
+ * @brief Reset registers to default values. Vendor and reserved registers
+ *        are not changed.
+ *
+ * @param emul Pointer to TCPC emulator
+ * @return 0 if successful
+ */
+int tcpci_emul_reset(const struct emul *emul);
+
+/**
+ * @brief Get value of given register of TCPCI
+ *
+ * @param emul Pointer to TCPCI emulator
+ * @param reg Register address
+ * @param val Pointer where value should be stored
+ *
+ * @return 0 on success
+ * @return -EINVAL when register is out of range defined in TCPCI specification
+ *                 or val is NULL
+ */
+int tcpci_emul_get_reg(const struct emul *emul, int reg, uint16_t *val);
+
+/**
+ * @brief Add up to two SOP RX messages
+ *
+ * @param emul Pointer to TCPC emulator
+ * @param rx_msg Pointer to message that is added
+ * @param alert Select if alert register should be updated
+ *
+ * @return TCPCI_EMUL_TX_SUCCESS on success
+ * @return TCPCI_EMUL_TX_FAILED when TCPCI is configured to not handle
+ *                              messages of this type
+ * @return -EINVAL on error (too long message, adding third message or wrong
+ *                 message type)
+ * @return -EBUSY Failed to lock mutex for TCPCI emulator
+ * @return -EAGAIN Failed to lock mutex for TCPCI emulator
+ */
+int tcpci_emul_add_rx_msg(const struct emul *emul,
+			  struct tcpci_emul_msg *rx_msg, bool alert);
+
+/**
+ * @brief Get SOP TX message to examine what was sended by TCPM
+ *
+ * @param emul Pointer to TCPC emulator
+ *
+ * @return Pointer to TX message
+ */
+struct tcpci_emul_msg *tcpci_emul_get_tx_msg(const struct emul *emul);
+
+/**
+ * @brief Set TCPCI revision in PD_INT_REV register
+ *
+ * @param emul Pointer to TCPC emulator
+ * @param rev Requested revision
+ */
+void tcpci_emul_set_rev(const struct emul *emul, enum tcpci_emul_rev rev);
+
+/**
+ * @brief Set TCPCI VBUS Voltage in VBUS_VOLTAGE register
+ *
+ * @param emul Pointer to TCPC emulator
+ * @param vbus_mv Requested VBUS in mV
+ */
+void tcpci_emul_set_vbus_voltage(const struct emul *emul, uint32_t vbus_mv);
+
+/**
+ * @brief Set callback which is called when alert register is changed
+ *
+ * @param emul Pointer to TCPC emulator
+ * @param alert_callback Pointer to callback
+ * @param alert_callback_data Pointer to data passed to callback as an argument
+ */
+void tcpci_emul_set_alert_callback(const struct emul *emul,
+				   tcpci_emul_alert_state_func alert_callback,
+				   void *alert_callback_data);
+
+/**
+ * @brief Set callbacks for port partner device emulator
+ *
+ * @param emul Pointer to TCPC emulator
+ * @param partner Pointer to callbacks
+ */
+void tcpci_emul_set_partner_ops(const struct emul *emul,
+				const struct tcpci_emul_partner_ops *partner);
+
+/**
+ * @brief Emulate connection of specific device to emulated TCPCI
+ *
+ * @param emul Pointer to TCPC emulator
+ * @param partner_power_role Power role of connected partner (sink or source)
+ * @param partner_cc1 Voltage on partner CC1 line (usually Rd or Rp)
+ * @param partner_cc2 Voltage on partner CC2 line (usually open or Ra if active
+ *                    cable is emulated)
+ * @param polarity Polarity of plug. If POLARITY_CC1 then partner_cc1 is
+ *                 connected to TCPCI CC1 line. Otherwise partner_cc1 is
+ *                 connected to TCPCI CC2 line.
+ *
+ * @return 0 on success
+ * @return negative on error
+ */
+int tcpci_emul_connect_partner(const struct emul *emul,
+			       enum pd_power_role partner_power_role,
+			       enum tcpc_cc_voltage_status partner_cc1,
+			       enum tcpc_cc_voltage_status partner_cc2,
+			       enum tcpc_cc_polarity polarity);
+
+/** @brief Emulate the disconnection of the partner device to emulated TCPCI
+ *
+ * @param emul Pointer to TCPC emulator
+ *
+ * @return 0 on success
+ */
+int tcpci_emul_disconnect_partner(const struct emul *emul);
+
+/**
+ * @brief Allows port partner to select if message was received correctly
+ *
+ * @param emul Pointer to TCPC emulator
+ * @param status Status of sended message
+ */
+void tcpci_emul_partner_msg_status(const struct emul *emul,
+				   enum tcpci_emul_tx_status status);
+
+/**
+ * @brief Gets the common data associated with the tcpci chip overall
+ *
+ * @param emul Pointer to TCPC emulator
+ * @return Pointer to struct i2c_common_emul_data
+ */
+struct i2c_common_emul_data *
+emul_tcpci_generic_get_i2c_common_data(const struct emul *emul);
+
+/**
+ * @brief Set the VBUS level of the emulator, and trigger interrupts as needed.
+ *
+ * @param emul Pointer to TCPC emulator
+ * @param level One of VBUS_PRESENT, VBUS_REMOVED or VBUS_SAFE0V
+ *
+ * @return 0 for success, or non-0 for errors.
+ */
+int tcpci_emul_set_vbus_level(const struct emul *emul, enum vbus_level level);
+
+/**
+ * @}
+ */
+
+#endif /* __EMUL_TCPCI */
diff --git a/zephyr/include/emul/tcpc/emul_tcpci_partner_common.h b/zephyr/include/emul/tcpc/emul_tcpci_partner_common.h
new file mode 100644
index 0000000000..b43da3c86d
--- /dev/null
+++ b/zephyr/include/emul/tcpc/emul_tcpci_partner_common.h
@@ -0,0 +1,664 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ *
+ * @brief Common code used by TCPCI partner device emulators
+ */
+
+#ifndef __EMUL_TCPCI_PARTNER_COMMON_H
+#define __EMUL_TCPCI_PARTNER_COMMON_H
+
+#include "ec_commands.h"
+#include "emul/tcpc/emul_tcpci.h"
+#include "usb_pd.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/kernel.h>
+#include <zephyr/sys/atomic.h>
+
+/**
+ * @brief Common code used by TCPCI partner device emulators
+ * @defgroup tcpci_partner Common code for TCPCI partner device emulators
+ * @{
+ *
+ * Common code for TCPCI partner device emulators allows to send SOP messages
+ * in generic way using optional delay.
+ */
+
+/** Timeout for other side to respond to PD message */
+#define TCPCI_PARTNER_RESPONSE_TIMEOUT_MS 30
+#define TCPCI_PARTNER_RESPONSE_TIMEOUT K_MSEC(TCPCI_PARTNER_RESPONSE_TIMEOUT_MS)
+/** Timeout for source to transition to requested state after accept */
+#define TCPCI_PARTNER_TRANSITION_TIMEOUT_MS 550
+#define TCPCI_PARTNER_TRANSITION_TIMEOUT \
+	K_MSEC(TCPCI_PARTNER_TRANSITION_TIMEOUT_MS)
+/** Timeout for source to send capability again after failure */
+#define TCPCI_SOURCE_CAPABILITY_TIMEOUT_MS 150
+#define TCPCI_SOURCE_CAPABILITY_TIMEOUT \
+	K_MSEC(TCPCI_SOURCE_CAPABILITY_TIMEOUT_MS)
+/** Timeout for source to send capability message after power swap */
+#define TCPCI_SWAP_SOURCE_START_TIMEOUT_MS 20
+#define TCPCI_SWAP_SOURCE_START_TIMEOUT \
+	K_MSEC(TCPCI_SWAP_SOURCE_START_TIMEOUT_MS)
+
+/** Common data for TCPCI partner device emulators */
+struct tcpci_partner_data {
+	/** List of extensions used in TCPCI partner emulator */
+	struct tcpci_partner_extension *extensions;
+	/** Operations used by TCPCI emulator */
+	struct tcpci_emul_partner_ops ops;
+	/** Timer used to send message with delay */
+	struct k_timer delayed_send;
+	/** Reserved for fifo, used for scheduling messages */
+	void *fifo_data;
+	/** Pointer to connected TCPCI emulator */
+	const struct emul *tcpci_emul;
+	/** Queue for delayed messages */
+	sys_slist_t to_send;
+	/** Mutex for to_send queue */
+	struct k_mutex to_send_mutex;
+	/** Next SOP message id */
+	int sop_msg_id;
+	/** Next SOP' message id */
+	int sop_prime_msg_id;
+	/** Last received message id */
+	int sop_recv_msg_id;
+	/** Last received SOP' message id */
+	int sop_prime_recv_msg_id;
+	/** Power role (used in message header) */
+	enum pd_power_role power_role;
+	/** Data role (used in message header) */
+	enum pd_data_role data_role;
+	/** Whether this partner will Accept a Data Role Swap that would switch
+	 * the partner from DFP to UFP.
+	 */
+	bool drs_to_ufp_supported;
+	/** Whether this partner will Accept a Data Role Swap that would switch
+	 * the partner from UFP to DFP.
+	 */
+	bool drs_to_dfp_supported;
+	/** VCONN role */
+	enum pd_vconn_role vconn_role;
+	/** Revision (used in message header) */
+	enum pd_rev_type rev;
+	/** The response message that will be sent in response to VCONN Swap. */
+	enum pd_ctrl_msg_type vcs_response;
+	/** Resistor set at the CC1 line of partner emulator */
+	enum tcpc_cc_voltage_status cc1;
+	/** Resistor set at the CC2 line of partner emulator */
+	enum tcpc_cc_voltage_status cc2;
+	/**
+	 * Polarity of the partner emulator. It controls to which CC line of
+	 * TCPC emulator the partner emulator CC1 line should be connected.
+	 */
+	enum tcpc_cc_polarity polarity;
+	/**
+	 * Mask for control message types that shouldn't be handled
+	 * in common message handler
+	 */
+	uint32_t common_handler_masked;
+	/**
+	 * True if accept and reject messages shouldn't trigger soft reset
+	 * in common message handler
+	 */
+	bool wait_for_response;
+	/**
+	 * If emulator triggers soft reset, it waits for accept. If accept
+	 * doesn't arrive, hard reset is triggered.
+	 */
+	bool in_soft_reset;
+	/** Current AMS Control request being handled */
+	enum pd_ctrl_msg_type cur_ams_ctrl_req;
+	/**
+	 * If common code should send GoodCRC for each message. If false,
+	 * then one of extensions should call tcpci_emul_partner_msg_status().
+	 * If message is handled by common code, than GoodCRC is send regardless
+	 * of send_goodcrc value.
+	 */
+	bool send_goodcrc;
+	/**
+	 * Mutex for TCPCI transmit handler. Should be used to synchronise
+	 * access to partner emulator with TCPCI emulator.
+	 */
+	struct k_mutex transmit_mutex;
+	/** Delayed work which is executed when response timeout occurs */
+	struct k_work_delayable sender_response_timeout;
+	/** Number of TCPM timeouts. Test may chekck if timeout occurs */
+	int tcpm_timeouts;
+	/** List with logged PD messages */
+	sys_slist_t msg_log;
+	/** Flag which controls if messages should be logged */
+	bool collect_msg_log;
+	/** Mutex for msg_log */
+	struct k_mutex msg_log_mutex;
+	/**
+	 * Pointer to last received message status. This pointer is set only
+	 * when message logging is enabled. It used to track if partner set
+	 * any status to received message.
+	 */
+	enum tcpci_emul_tx_status *received_msg_status;
+	/** Whether port partner is configured in DisplayPort mode */
+	bool displayport_configured;
+	/** The number of Enter Mode REQs received since connection
+	 *  or the last Hard Reset, whichever was more recent.
+	 */
+	atomic_t mode_enter_attempts;
+	/* SVID of entered mode (0 if no mode is entered) */
+	uint16_t entered_svid;
+
+	enum tcpc_cc_voltage_status tcpm_cc1;
+	enum tcpc_cc_voltage_status tcpm_cc2;
+
+	/* VDMs with which the partner responds to discovery REQs. The VDM
+	 * buffers include the VDM header, and the VDO counts include 1 for the
+	 * VDM header. This structure has space for the mode response for a
+	 * single supported SVID.
+	 */
+	uint32_t identity_vdm[VDO_MAX_SIZE];
+	int identity_vdos;
+	uint32_t svids_vdm[VDO_MAX_SIZE];
+	int svids_vdos;
+	uint32_t modes_vdm[VDO_MAX_SIZE];
+	int modes_vdos;
+	/* VDMs sent when responding to a mode entry command */
+	uint32_t enter_mode_vdm[VDO_MAX_SIZE];
+	int enter_mode_vdos;
+	/* VDMs sent when responding to DisplayPort status update command */
+	uint32_t dp_status_vdm[VDO_MAX_SIZE];
+	int dp_status_vdos;
+	/* VDMs sent when responding to DisplayPort config command */
+	uint32_t dp_config_vdm[VDO_MAX_SIZE];
+	int dp_config_vdos;
+	struct {
+		/* Index of the last battery we requested capabilities for. The
+		 * BCDB response does not include the index so we need to track
+		 * it manually. -1 indicates no outstanding request.
+		 */
+		int index;
+		/* Stores Battery Capability Data Blocks (BCDBs) requested and
+		 * received from the TCPM for later analysis. See USB-PD spec
+		 * Rev 3.1, Ver 1.3 section 6.5.5
+		 */
+		struct pd_bcdb bcdb[PD_BATT_MAX];
+		/* Stores a boolean status for each battery index indicating
+		 * whether we have received a BCDB response for that battery.
+		 */
+		bool have_response[PD_BATT_MAX];
+	} battery_capabilities;
+	/* RMDO returned by partner in response to a Get_Revision message */
+	uint32_t rmdo;
+	/* Used to control accept/reject for partner port of Enter_USB msg */
+	bool enter_usb_accept;
+
+	/*
+	 * Cable which is "plugged in" to this port partner
+	 * Note: Much as in real life, cable should be attached before the port
+	 * partner can be plugged in to properly discover its information.
+	 * For tests, this means this poitner should be set before connecting
+	 * the source or sink partner.
+	 */
+	struct tcpci_cable_data *cable;
+};
+
+struct tcpci_cable_data {
+	/*
+	 * Identity VDM ACKs which the cable is expected to send
+	 * These include the VDM header
+	 */
+	uint32_t identity_vdm[VDO_MAX_SIZE];
+	int identity_vdos;
+};
+
+/** Structure of message used by TCPCI partner emulator */
+struct tcpci_partner_msg {
+	/** Reserved for sys_slist_* usage */
+	sys_snode_t node;
+	/** TCPCI emulator message */
+	struct tcpci_emul_msg msg;
+	/** Time when message should be sent if message is delayed */
+	uint64_t time;
+	/** Message type that is placed in the Message Header. Its meaning
+	 *  depends on the class of message:
+	 *   - for Control Messages, see `enum pd_ctrl_msg_type`
+	 *   - for Data Messages, see `enum pd_data_msg_type`
+	 *   - for Extended Messages, see `enum pd_ext_msg_type`
+	 */
+	int type;
+	/** Number of data objects */
+	int data_objects;
+	/** True if this is an extended message */
+	bool extended;
+};
+
+/** Identify sender of logged PD message */
+enum tcpci_partner_msg_sender {
+	TCPCI_PARTNER_SENDER_PARTNER,
+	TCPCI_PARTNER_SENDER_TCPM
+};
+
+/** Structure of logged PD message */
+struct tcpci_partner_log_msg {
+	/** Reserved for sys_slist_* usage */
+	sys_snode_t node;
+	/** Pointer to buffer for header and message */
+	uint8_t *buf;
+	/** Number of bytes in buf */
+	int cnt;
+	/** Type of message (SOP, SOP', etc) */
+	uint8_t sop;
+	/** Time when message was send or received by partner emulator */
+	uint64_t time;
+	/** Sender of the message */
+	enum tcpci_partner_msg_sender sender;
+	/** Status of sending this message */
+	enum tcpci_emul_tx_status status;
+};
+
+/** Result of common handler */
+enum tcpci_partner_handler_res {
+	TCPCI_PARTNER_COMMON_MSG_HANDLED,
+	TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED,
+	TCPCI_PARTNER_COMMON_MSG_HARD_RESET,
+	TCPCI_PARTNER_COMMON_MSG_NO_GOODCRC,
+};
+
+/** Structure of TCPCI partner extension */
+struct tcpci_partner_extension {
+	/** Pointer to next extension or NULL */
+	struct tcpci_partner_extension *next;
+	/** Pointer to callbacks of the extension */
+	struct tcpci_partner_extension_ops *ops;
+};
+
+/**
+ * Extension callbacks. They are called after the common partner emulator code
+ * starting from the extension pointed by extensions field in
+ * struct tcpci_partner_data. Rest of extensions are called in order established
+ * by next field in struct tcpci_partner_extension.
+ * If not required, each callback can be NULL. The NULL callback is ignored and
+ * next extension in chain is called.
+ * It may be useful for extension to mask message handling in common code using
+ * @ref tcpci_partner_common_handler_mask_msg to alter emulator behavior in case
+ * of receiving some messages.
+ */
+struct tcpci_partner_extension_ops {
+	/**
+	 * @brief Function called when message from TCPM is handled
+	 *
+	 * @param ext Pointer to partner extension
+	 * @param common_data Pointer to TCPCI partner emulator
+	 * @param msg Pointer to received message
+	 *
+	 * @return TCPCI_PARTNER_COMMON_MSG_HANDLED to indicate that message
+	 *         is handled and ignore other extensions sop_msg_handler
+	 * @return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED to indicate that
+	 *         message wasn't handled
+	 */
+	enum tcpci_partner_handler_res (*sop_msg_handler)(
+		struct tcpci_partner_extension *ext,
+		struct tcpci_partner_data *common_data,
+		const struct tcpci_emul_msg *msg);
+
+	/**
+	 * @brief Function called when HardReset message is received or sent
+	 *
+	 * @param ext Pointer to partner extension
+	 * @param common_data Pointer to TCPCI partner emulator
+	 */
+	void (*hard_reset)(struct tcpci_partner_extension *ext,
+			   struct tcpci_partner_data *common_data);
+
+	/**
+	 * @brief Function called when SoftReset message is received
+	 *
+	 * @param ext Pointer to partner extension
+	 * @param common_data Pointer to TCPCI partner emulator
+	 */
+	void (*soft_reset)(struct tcpci_partner_extension *ext,
+			   struct tcpci_partner_data *common_data);
+
+	void (*control_change)(struct tcpci_partner_extension *ext,
+			       struct tcpci_partner_data *common_data);
+
+	/**
+	 * @brief Function called when partner emulator is disconnected from
+	 *        TCPM
+	 *
+	 * @param ext Pointer to partner extension
+	 * @param common_data Pointer to TCPCI partner emulator
+	 */
+	void (*disconnect)(struct tcpci_partner_extension *ext,
+			   struct tcpci_partner_data *common_data);
+
+	/**
+	 * @brief Function called when partner emulator is connected to TCPM.
+	 *        In connect callback, any message cannot be sent with 0 delay
+	 *
+	 * @param ext Pointer to partner extension
+	 * @param common_data Pointer to TCPCI partner emulator
+	 *
+	 * @return Negative value on error
+	 * @return 0 on success
+	 */
+	int (*connect)(struct tcpci_partner_extension *ext,
+		       struct tcpci_partner_data *common_data);
+};
+
+/**
+ * @brief Initialise common TCPCI partner emulator. Need to be called before
+ *        any other tcpci_partner_* function and init functions of extensions.
+ *
+ * @param data Pointer to USB-C charger emulator
+ * @param rev PD revision of the emulator
+ */
+void tcpci_partner_init(struct tcpci_partner_data *data, enum pd_rev_type rev);
+
+/**
+ * @brief Set the partner emulator to support or not support swapping data roles
+ * to UFP and DFP. If the partner supports a swap, it should respond to DR_Swap
+ * with Accept with that role as the new data role.
+ *
+ * @param data Pointer to USB-C partner emulator
+ * @param drs_to_ufp_supported Whether the partner supports swapping to UFP
+ * @param drs_to_dfp_supported Whether the partner supports swapping to DFP
+ */
+void tcpci_partner_set_drs_support(struct tcpci_partner_data *data,
+				   bool drs_to_ufp_supported,
+				   bool drs_to_dfp_supported);
+
+/**
+ * @brief Set the response message for VCONN Swap.
+ *
+ * A compliant partner should not change the response from Accept/Reject to
+ * Not_Supported or vice versa while attached. However, there are real devices
+ * that pretend to stop supporting VCONN after completing a VCONN Swap.
+ *
+ * The default behavior of the partner is to Accept VCONN Swaps.
+ *
+ * @param data Pointer to USB-C partner emulator
+ * @param vcs_response PD_CTRL_ACCEPT to support sourcing VCONN,
+ *        PD_CTRL_NOT_SUPPORTED to not support it, or other message types
+ *        as needed.
+ */
+void tcpci_partner_set_vcs_response(struct tcpci_partner_data *data,
+				    enum pd_ctrl_msg_type vcs_response);
+/**
+ * @brief Free message's memory
+ *
+ * @param msg Pointer to message
+ */
+void tcpci_partner_free_msg(struct tcpci_partner_msg *msg);
+
+/**
+ * @brief Set header of the message
+ *
+ * @param data Pointer to TCPCI partner emulator
+ * @param msg Pointer to message
+ */
+void tcpci_partner_set_header(struct tcpci_partner_data *data,
+			      struct tcpci_partner_msg *msg);
+
+/**
+ * @brief Send message to TCPCI emulator or schedule message. On error message
+ *        is freed.
+ *
+ * @param data Pointer to TCPCI partner emulator
+ * @param msg Pointer to message to send
+ * @param delay Optional delay
+ *
+ * @return TCPCI_EMUL_TX_SUCCESS on success
+ * @return TCPCI_EMUL_TX_FAILED when TCPCI is configured to not handle
+ *                              messages of this type
+ * @return negative on failure
+ */
+int tcpci_partner_send_msg(struct tcpci_partner_data *data,
+			   struct tcpci_partner_msg *msg, uint64_t delay);
+
+/**
+ * @brief Send control message with optional delay
+ *
+ * @param data Pointer to TCPCI partner emulator
+ * @param type Type of message
+ * @param delay Optional delay
+ *
+ * @return TCPCI_EMUL_TX_SUCCESS on success
+ * @return TCPCI_EMUL_TX_FAILED when TCPCI is configured to not handle
+ *                              messages of this type
+ * @return -ENOMEM when there is no free memory for message
+ * @return negative on failure
+ */
+int tcpci_partner_send_control_msg(struct tcpci_partner_data *data,
+				   enum pd_ctrl_msg_type type, uint64_t delay);
+
+/**
+ * @brief Send data message with optional delay. Data objects are copied to
+ *        message.
+ *
+ * @param data Pointer to TCPCI partner emulator
+ * @param type Type of message
+ * @param data_obj Pointer to array of data objects
+ * @param data_obj_num Number of data objects
+ * @param delay Optional delay in milliseconds
+ *
+ * @return TCPCI_EMUL_TX_SUCCESS on success
+ * @return TCPCI_EMUL_TX_FAILED when TCPCI is configured to not handle
+ *                              messages of this type
+ * @return -ENOMEM when there is no free memory for message
+ * @return negative on failure
+ */
+int tcpci_partner_send_data_msg(struct tcpci_partner_data *data,
+				enum pd_data_msg_type type, uint32_t *data_obj,
+				int data_obj_num, uint64_t delay);
+
+/**
+ * @brief Send an extended PD message to the port partner
+ *
+ * @param data Pointer to TCPCI partner emulator
+ * @param type Extended message type
+ * @param delay Message send delay in milliseconds, or zero for no delay.
+ * @param payload Pointer to data payload. Does not include any headers.
+ * @param payload_size Number of bytes in above payload
+ * @return negative on failure, 0 on success
+ */
+int tcpci_partner_send_extended_msg(struct tcpci_partner_data *data,
+				    enum pd_ext_msg_type type, uint64_t delay,
+				    uint8_t *payload, size_t payload_size);
+
+/**
+ * @brief Remove all messages that are in delayed message queue
+ *
+ * @param data Pointer to TCPCI partner emulator
+ *
+ * @return 0 on success
+ * @return negative on failure
+ */
+int tcpci_partner_clear_msg_queue(struct tcpci_partner_data *data);
+
+/**
+ * @brief Send hard reset and set common data to state after hard reset (reset
+ *        counters, flags, clear message queue)
+ *
+ * @param data Pointer to TCPCI partner emulator
+ */
+void tcpci_partner_common_send_hard_reset(struct tcpci_partner_data *data);
+
+/**
+ * @brief Send hard reset and set common data to state after soft reset (reset
+ *        counters, set flags to wait for accept)
+ *
+ * @param data Pointer to TCPCI partner emulator
+ */
+void tcpci_partner_common_send_soft_reset(struct tcpci_partner_data *data);
+
+/**
+ * @brief Send a Get Battery Capabilities request to the TCPM
+ *
+ * @param data Pointer to TCPCI partner emulator
+ * @param battery_index Request capability info on this battery. Must
+ *        be (0 <= battery_index < PD_BATT_MAX)
+ */
+void tcpci_partner_common_send_get_battery_capabilities(
+	struct tcpci_partner_data *data, int battery_index);
+
+/**
+ * @brief Resets the data structure used for tracking battery capability
+ *        requests and responses.
+ *
+ * @param data Emulator state
+ */
+void tcpci_partner_reset_battery_capability_state(
+	struct tcpci_partner_data *data);
+
+/**
+ * @brief Start sender response timer for TCPCI_PARTNER_RESPONSE_TIMEOUT_MS.
+ *        If @ref tcpci_partner_stop_sender_response_timer wasn't called before
+ *        timeout, @ref tcpci_partner_sender_response_timeout is called.
+ *        The wait_for_response flag is set on timer start.
+ *
+ * @param data Pointer to TCPCI partner emulator
+ */
+void tcpci_partner_start_sender_response_timer(struct tcpci_partner_data *data);
+
+/**
+ * @brief Stop sender response timer. The wait_for_response flag is unset.
+ *        Timeout handler will not execute.
+ *
+ * @param data Pointer to TCPCI partner emulator
+ */
+void tcpci_partner_stop_sender_response_timer(struct tcpci_partner_data *data);
+
+/**
+ * @brief Select if @ref tcpci_partner_common_msg_handler should handle specific
+ *        control message type.
+ *
+ * @param data Pointer to TCPCI partner emulator
+ * @param type Control message to mask/unmask
+ * @param enable If true message of that type is handled, if false common
+ *               handler doesn't handle message of that type
+ */
+void tcpci_partner_common_handler_mask_msg(struct tcpci_partner_data *data,
+					   enum pd_ctrl_msg_type type,
+					   bool enable);
+
+/**
+ * @brief Common disconnect function which clears messages queue, sets
+ *        tcpci_emul field in struct tcpci_partner_data to NULL, and stops
+ *        timers.
+ *
+ * @param data Pointer to TCPCI partner emulator
+ */
+void tcpci_partner_common_disconnect(struct tcpci_partner_data *data);
+
+/**
+ * @brief Select if PD messages should be logged or not.
+ *
+ * @param data Pointer to TCPCI partner emulator
+ * @param enable If true, PD messages are logged, false otherwise
+ *
+ * @return 0 on success
+ * @return non-zero on failure
+ */
+int tcpci_partner_common_enable_pd_logging(struct tcpci_partner_data *data,
+					   bool enable);
+
+/**
+ * @brief Print all logged PD messages
+ *
+ * @param data Pointer to TCPCI partner emulator
+ */
+void tcpci_partner_common_print_logged_msgs(struct tcpci_partner_data *data);
+
+/**
+ * @brief Clear all logged PD messages
+ *
+ * @param data Pointer to TCPCI partner emulator
+ */
+void tcpci_partner_common_clear_logged_msgs(struct tcpci_partner_data *data);
+
+/**
+ * @brief Set the discovery responses (Vendor Defined Messages) for the partner.
+ *
+ * If a response for a command type is not defined, the partner will ignore
+ * requests of that type. To emulate compliant behavior, the discover responses
+ * should be internally consistent, e.g., if there is a DisplayPort VID in
+ * Discover SVIDs ACK, there should be a Discover Modes ACK for DisplayPort.
+ *
+ * @param data          Pointer to TCPCI partner emulator
+ * @param identity_vdos Number of 32-bit Vendor Defined Objects in the Discover
+ *                      Identity response VDM
+ * @param identity_vdm  Pointer to the Discover Identity response VDM, including
+ *                      the VDM header
+ * @param svids_vdos    Number of VDOs in the Discover SVIDs response
+ * @param svids_vdm     Pointer to the Discover SVIDs response
+ * @param modes_vdos    Number of VDOs in the Discover Modes response
+ * @param modes_vdm     Pointer to the Discover Modes response; only currently
+ *                      supports a response for a single SVID
+ */
+void tcpci_partner_set_discovery_info(struct tcpci_partner_data *data,
+				      int identity_vdos, uint32_t *identity_vdm,
+				      int svids_vdos, uint32_t *svids_vdm,
+				      int modes_vdos, uint32_t *modes_vdm);
+
+/**
+ * @brief Sets cur_ams_ctrl_req to msg_type to track current request
+ *
+ * @param data          Pointer to TCPCI partner data
+ * @param msg_type      enum pd_ctrl_msg_type
+ */
+void tcpci_partner_common_set_ams_ctrl_msg(struct tcpci_partner_data *data,
+					   enum pd_ctrl_msg_type msg_type);
+
+/**
+ * @brief Sets cur_ams_ctrl_req to INVALID
+ *
+ * @param data          Pointer to TCPCI partner data
+ */
+void tcpci_partner_common_clear_ams_ctrl_msg(struct tcpci_partner_data *data);
+
+/**
+ * @brief Called by partner emulators internally. Resets the common tcpci
+ * partner data with the provided role.
+ *
+ * @param data          Pointer to TCPCI partner data
+ * @param power_role    USB PD power role
+ */
+void tcpci_partner_common_hard_reset_as_role(struct tcpci_partner_data *data,
+					     enum pd_power_role power_role);
+
+/**
+ * @brief Connect emulated device to TCPCI. The connect callback is executed on
+ *        all extensions.
+ *
+ * @param data Pointer to TCPCI partner emulator
+ * @param tcpci_emul Pointer to TCPCI emulator to connect
+ *
+ * @return 0 on success
+ * @return negative on TCPCI connect error
+ */
+int tcpci_partner_connect_to_tcpci(struct tcpci_partner_data *data,
+				   const struct emul *tcpci_emul);
+
+/**
+ * @brief Inform TCPCI about status of received message (TCPCI_EMUL_TX_SUCCESS
+ *        GoodCRC send to TCPCI, TCPCI_EMUL_TX_DISCARDED partner message send in
+ *        the same time as TCPCI message, TCPCI_EMUL_TX_FAILED GoodCRC doesn't
+ *        send to TCPCI)
+ *
+ * @param data Pointer to TCPCI partner emulator
+ * @param status Status of received message
+ */
+void tcpci_partner_received_msg_status(struct tcpci_partner_data *data,
+				       enum tcpci_emul_tx_status status);
+
+/**
+ * @}
+ */
+
+#endif /* __EMUL_TCPCI_PARTNER_COMMON_H */
diff --git a/zephyr/include/emul/tcpc/emul_tcpci_partner_drp.h b/zephyr/include/emul/tcpc/emul_tcpci_partner_drp.h
new file mode 100644
index 0000000000..cacb4e6270
--- /dev/null
+++ b/zephyr/include/emul/tcpc/emul_tcpci_partner_drp.h
@@ -0,0 +1,78 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ *
+ * @brief Backend API for USB-C dual role device emulator
+ */
+
+#ifndef __EMUL_TCPCI_PARTNER_DRP_H
+#define __EMUL_TCPCI_PARTNER_DRP_H
+
+#include "emul/tcpc/emul_tcpci.h"
+#include "emul/tcpc/emul_tcpci_partner_common.h"
+#include "emul/tcpc/emul_tcpci_partner_snk.h"
+#include "emul/tcpc/emul_tcpci_partner_src.h"
+#include "usb_pd.h"
+
+#include <zephyr/drivers/emul.h>
+
+/**
+ * @brief USB-C dual role device extension backend API
+ * @defgroup tcpci_snk_emul USB-C dual role device extension
+ * @{
+ *
+ * USB-C DRP device emulator can be used with TCPCI partner emulator. It is able
+ * to switch power role on PR SWAP message. It is required to provide sink and
+ * source extensions to initialise the DRP extension. If sink or source
+ * extension first capabilities PDO is changed after initialisation, function
+ * @ref tcpci_drp_emul_set_dr_in_first_pdo should be called to select correct
+ * flag specific for DRP device.
+ */
+
+/** Structure describing dual role device emulator data */
+struct tcpci_drp_emul_data {
+	/** Common extension structure */
+	struct tcpci_partner_extension ext;
+	/** Controls if device is sink or source */
+	bool sink;
+	/** If device is during power swap and is expecting PS_RDY message */
+	bool in_pwr_swap;
+	/** Initial power role that should be restored on hard reset */
+	enum pd_power_role initial_power_role;
+};
+
+/**
+ * @brief Initialise USB-C DRP device data structure
+ *
+ * @param data Pointer to USB-C DRP device emulator data
+ * @param common_data Pointer to USB-C device emulator common data
+ * @param power_role Default power role used by USB-C DRP device on connection
+ * @param src_ext Pointer to source extension
+ * @param sink_ext Pointer to sink extension
+ *
+ * @return Pointer to USB-C DRP extension
+ */
+struct tcpci_partner_extension *
+tcpci_drp_emul_init(struct tcpci_drp_emul_data *data,
+		    struct tcpci_partner_data *common_data,
+		    enum pd_power_role power_role,
+		    struct tcpci_partner_extension *src_ext,
+		    struct tcpci_partner_extension *snk_ext);
+
+/**
+ * @brief Set correct flags for first capabilities PDO to indicate that this
+ *        device is power swap capable.
+ *
+ * @param pdo capability entry to change
+ */
+void tcpci_drp_emul_set_dr_in_first_pdo(uint32_t *pdo);
+
+/**
+ * @}
+ */
+
+#endif /* __EMUL_TCPCI_PARTNER_DRP_H */
diff --git a/zephyr/include/emul/tcpc/emul_tcpci_partner_faulty_ext.h b/zephyr/include/emul/tcpc/emul_tcpci_partner_faulty_ext.h
new file mode 100644
index 0000000000..317e9817d4
--- /dev/null
+++ b/zephyr/include/emul/tcpc/emul_tcpci_partner_faulty_ext.h
@@ -0,0 +1,102 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ *
+ * @brief Backend API for USB-C malfunctioning device emulator
+ */
+
+#ifndef __EMUL_TCPCI_PARTNER_FAULTY_EXT_H
+#define __EMUL_TCPCI_PARTNER_FAULTY_EXT_H
+
+#include "emul/tcpc/emul_tcpci.h"
+#include "emul/tcpc/emul_tcpci_partner_common.h"
+#include "usb_pd.h"
+
+#include <zephyr/drivers/emul.h>
+
+/**
+ * @brief USB-C malfunctioning device extension backend API
+ * @defgroup tcpci_faulty_ext USB-C malfunctioning device extension
+ * @{
+ *
+ * USB-C malfunctioning device extension can be used with TCPCI partner
+ * emulator. It can be configured to not respond to source capability message
+ * (by not sending GoodCRC or Request after GoodCRC).
+ */
+
+/** Structure describing malfunctioning emulator data */
+struct tcpci_faulty_ext_data {
+	struct tcpci_partner_extension ext;
+	/* List of action to perform */
+	struct k_fifo action_list;
+};
+
+/** Actions that can be performed by malfunctioning emulator */
+enum tcpci_faulty_ext_action_type {
+	/**
+	 * Fail to receive SourceCapabilities message. From TCPM point of view,
+	 * GoodCRC message is not received.
+	 */
+	TCPCI_FAULTY_EXT_FAIL_SRC_CAP = BIT(0),
+	/**
+	 * Ignore to respond to SourceCapabilities message with Request message.
+	 * From TCPM point of view, GoodCRC message is received, but Request is
+	 * missing.
+	 */
+	TCPCI_FAULTY_EXT_IGNORE_SRC_CAP = BIT(1),
+	/** Discard SourceCapabilities message and send Accept message */
+	TCPCI_FAULTY_EXT_DISCARD_SRC_CAP = BIT(2),
+};
+
+/** Structure to put in malfunctioning emulator action list */
+struct tcpci_faulty_ext_action {
+	/* Reserved for FIFO */
+	void *fifo_reserved;
+	/* Actions that emulator should perform */
+	uint32_t action_mask;
+	/* Number of times to repeat action */
+	int count;
+};
+
+/* Count of actions which is treated by emulator as infinite */
+#define TCPCI_FAULTY_EXT_INFINITE_ACTION 0
+
+/**
+ * @brief Initialise USB-C malfunctioning device data structure
+ *
+ * @param data Pointer to USB-C malfunctioning device emulator data
+ * @param common_data Pointer to USB-C device emulator common data
+ * @param ext Pointer to next USB-C emulator extension
+ *
+ * @return Pointer to USB-C malfunctioning extension
+ */
+struct tcpci_partner_extension *
+tcpci_faulty_ext_init(struct tcpci_faulty_ext_data *data,
+		      struct tcpci_partner_data *common_data,
+		      struct tcpci_partner_extension *ext);
+
+/**
+ * @brief Add action to perform by USB-C malfunctioning extension
+ *
+ * @param data Pointer to USB-C malfunctioning device extension data
+ * @param action Non standard behavior to perform by emulator
+ */
+void tcpci_faulty_ext_append_action(struct tcpci_faulty_ext_data *data,
+				    struct tcpci_faulty_ext_action *action);
+
+/**
+ * @brief Clear all actions of USB-C malfunctioning extension
+ *
+ * @param data Pointer to USB-C malfunctioning device extension data
+ */
+void tcpci_faulty_ext_clear_actions_list(struct tcpci_faulty_ext_data *data);
+
+/**
+ * @}
+ */
+
+#endif /* __EMUL_TCPCI_PARTNER_FAULTY_EXT_H */
diff --git a/zephyr/include/emul/tcpc/emul_tcpci_partner_snk.h b/zephyr/include/emul/tcpc/emul_tcpci_partner_snk.h
new file mode 100644
index 0000000000..edf09d25eb
--- /dev/null
+++ b/zephyr/include/emul/tcpc/emul_tcpci_partner_snk.h
@@ -0,0 +1,89 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ *
+ * @brief Backend API for USB-C sink device emulator
+ */
+
+#ifndef __EMUL_TCPCI_PARTNER_SNK_H
+#define __EMUL_TCPCI_PARTNER_SNK_H
+
+#include "emul/tcpc/emul_tcpci.h"
+#include "emul/tcpc/emul_tcpci_partner_common.h"
+#include "usb_pd.h"
+
+#include <zephyr/drivers/emul.h>
+
+/**
+ * @brief USB-C sink device extension backend API
+ * @defgroup tcpci_snk_emul USB-C sink device extension
+ * @{
+ *
+ * USB-C sink device extension can be used with TCPCI partner emulator. It is
+ * able to respond to some TCPM messages. It always attach as sink and present
+ * sink capabilities constructed from given PDOs.
+ */
+
+/** Structure describing sink device emulator data */
+struct tcpci_snk_emul_data {
+	/** Common extension structure */
+	struct tcpci_partner_extension ext;
+	/** Power data objects returned in sink capabilities message */
+	uint32_t pdo[PDO_MAX_OBJECTS];
+	/** Emulator is waiting for PS RDY message */
+	bool wait_for_ps_rdy;
+	/** PS RDY was received and PD negotiation is completed */
+	bool pd_completed;
+	/** PD_CTRL_PING message received  */
+	bool ping_received;
+	/** PD_DATA_ALERT message received  */
+	bool alert_received;
+	/** Last received 5V fixed source cap */
+	uint32_t last_5v_source_cap;
+};
+
+/**
+ * @brief Initialise USB-C sink device data structure. Single PDO 5V@500mA is
+ *        created and all flags are cleared.
+ *
+ * @param data Pointer to USB-C sink device emulator data
+ * @param common_data Pointer to USB-C device emulator common data
+ * @param ext Pointer to next USB-C emulator extension
+ *
+ * @return Pointer to USB-C sink extension
+ */
+struct tcpci_partner_extension *
+tcpci_snk_emul_init(struct tcpci_snk_emul_data *data,
+		    struct tcpci_partner_data *common_data,
+		    struct tcpci_partner_extension *ext);
+
+/**
+ * @brief Clear the ping received flag.
+ *
+ * @param sink_data
+ */
+void tcpci_snk_emul_clear_ping_received(struct tcpci_snk_emul_data *sink_data);
+
+/**
+ * @brief Clear the alert received flag.
+ *
+ * @param sink_data
+ */
+void tcpci_snk_emul_clear_alert_received(struct tcpci_snk_emul_data *sink_data);
+
+/**
+ * @brief Clear the last received 5V fixed source cap.
+ *
+ * @param sink_data
+ */
+void tcpci_snk_emul_clear_last_5v_cap(struct tcpci_snk_emul_data *sink_data);
+
+/**
+ * @}
+ */
+
+#endif /* __EMUL_TCPCI_PARTNER_SNK_H */
diff --git a/zephyr/include/emul/tcpc/emul_tcpci_partner_src.h b/zephyr/include/emul/tcpc/emul_tcpci_partner_src.h
new file mode 100644
index 0000000000..7ce14da82a
--- /dev/null
+++ b/zephyr/include/emul/tcpc/emul_tcpci_partner_src.h
@@ -0,0 +1,158 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ *
+ * @brief Backend API for USB-C source device emulator
+ */
+
+#ifndef __EMUL_TCPCI_PARTNER_SRC_H
+#define __EMUL_TCPCI_PARTNER_SRC_H
+
+#include "emul/tcpc/emul_tcpci.h"
+#include "emul/tcpc/emul_tcpci_partner_common.h"
+#include "usb_pd.h"
+
+#include <zephyr/drivers/emul.h>
+
+/**
+ * @brief USB-C source device extension backend API
+ * @defgroup tcpci_src_emul USB-C source device extension
+ * @{
+ *
+ * USB-C source device extension can be used with TCPCI partner emulator. It is
+ * able to respond to some TCPM messages. It always attach as source and present
+ * source capabilities constructed from given PDOs.
+ */
+
+/** Structure describing source device emulator data */
+struct tcpci_src_emul_data {
+	/** Common extension structure */
+	struct tcpci_partner_extension ext;
+	/** Power data objects returned in source capabilities message */
+	uint32_t pdo[PDO_MAX_OBJECTS];
+	/** Pointer to common TCPCI partner data */
+	struct tcpci_partner_data *common_data;
+	/** Delayed work which is executed on SourceCapability timeout */
+	struct k_work_delayable source_capability_timeout;
+	/** Flag tracking if partner has received an Alert message */
+	bool alert_received;
+	/** Flag tracking if partner has received a Status message */
+	bool status_received;
+};
+
+/** Return values of @ref tcpci_src_emul_check_pdos function */
+enum check_pdos_res {
+	TCPCI_SRC_EMUL_CHECK_PDO_OK = 0,
+	TCPCI_SRC_EMUL_FIRST_PDO_NO_FIXED_5V,
+	TCPCI_SRC_EMUL_FIXED_VOLT_REPEATED,
+	TCPCI_SRC_EMUL_FIXED_VOLT_NOT_IN_ORDER,
+	TCPCI_SRC_EMUL_NON_FIRST_PDO_FIXED_FLAGS,
+	TCPCI_SRC_EMUL_BATT_VOLT_REPEATED,
+	TCPCI_SRC_EMUL_BATT_VOLT_NOT_IN_ORDER,
+	TCPCI_SRC_EMUL_VAR_VOLT_REPEATED,
+	TCPCI_SRC_EMUL_VAR_VOLT_NOT_IN_ORDER,
+	TCPCI_SRC_EMUL_PDO_AFTER_ZERO,
+};
+
+/**
+ * @brief Check if PDOs of given source device emulator are in correct order
+ *
+ * @param data Pointer to USB-C source device emulator
+ *
+ * @return TCPCI_SRC_EMUL_CHECK_PDO_OK if PDOs are correct
+ * @return TCPCI_SRC_EMUL_FIRST_PDO_NO_FIXED_5V if first PDO is not
+ *         fixed type 5V
+ * @return TCPCI_SRC_EMUL_FIXED_VOLT_REPEATED if two or more fixed type PDOs
+ *         have the same voltage
+ * @return TCPCI_SRC_EMUL_FIXED_VOLT_NOT_IN_ORDER if fixed PDO with higher
+ *         voltage is before the one with lower voltage
+ * @return TCPCI_SRC_EMUL_NON_FIRST_PDO_FIXED_FLAGS if PDO different than first
+ *         has some flags set
+ * @return TCPCI_SRC_EMUL_BATT_VOLT_REPEATED if two or more battery type PDOs
+ *         have the same min and max voltage
+ * @return TCPCI_SRC_EMUL_BATT_VOLT_NOT_IN_ORDER if battery PDO with higher
+ *         voltage is before the one with lower voltage
+ * @return TCPCI_SRC_EMUL_VAR_VOLT_REPEATED if two or more variable type PDOs
+ *         have the same min and max voltage
+ * @return TCPCI_SRC_EMUL_VAR_VOLT_NOT_IN_ORDER if variable PDO with higher
+ *         voltage is before the one with lower voltage
+ * @return TCPCI_SRC_EMUL_PDO_AFTER_ZERO if PDOs of different types are not in
+ *         correct order (fixed, battery, variable) or non-zero PDO is placed
+ *         after zero PDO
+ */
+enum check_pdos_res tcpci_src_emul_check_pdos(struct tcpci_src_emul_data *data);
+
+/**
+ * @brief Initialise USB-C source device data structure. Single PDO 5V@3A is
+ *        created with fixed unconstrained flag.
+ *
+ * @param data Pointer to USB-C source device emulator data
+ * @param common_data Pointer to USB-C device emulator common data
+ * @param ext Pointer to next USB-C emulator extension
+ *
+ * @return Pointer to USB-C source extension
+ */
+struct tcpci_partner_extension *
+tcpci_src_emul_init(struct tcpci_src_emul_data *data,
+		    struct tcpci_partner_data *common_data,
+		    struct tcpci_partner_extension *ext);
+
+/**
+ * @brief Send capability message constructed from source device emulator PDOs
+ *
+ * @param data Pointer to USB-C source device emulator data
+ * @param common_data Pointer to common TCPCI partner data
+ * @param delay Optional delay
+ *
+ * @return TCPCI_EMUL_TX_SUCCESS on success
+ * @return TCPCI_EMUL_TX_FAILED when TCPCI is configured to not handle
+ *                              messages of this type
+ * @return -ENOMEM when there is no free memory for message
+ * @return -EINVAL on TCPCI emulator add RX message error
+ */
+int tcpci_src_emul_send_capability_msg(struct tcpci_src_emul_data *data,
+				       struct tcpci_partner_data *common_data,
+				       uint64_t delay);
+
+/**
+ * @brief Send capability message constructed from source device emulator PDOs.
+ *        SourceCapability timer is started when message wasn't send
+ *        successfully. Emulator will try to send source capability message
+ *        again on timeout. Otherwise SenderResponse timer is started and
+ *        emulator will wait for Request message.
+ *
+ * @param data Pointer to USB-C source device emulator data
+ * @param common_data Pointer to common TCPCI partner data
+ * @param delay Optional delay
+ *
+ * @return TCPCI_EMUL_TX_SUCCESS on success
+ * @return -ENOMEM when there is no free memory for message
+ * @return -EINVAL on TCPCI emulator add RX message error
+ */
+int tcpci_src_emul_send_capability_msg_with_timer(
+	struct tcpci_src_emul_data *data,
+	struct tcpci_partner_data *common_data, uint64_t delay);
+
+/**
+ * @brief Clear the alert received flag.
+ *
+ * @param data - pointer to source emulator partner data
+ */
+void tcpci_src_emul_clear_alert_received(struct tcpci_src_emul_data *data);
+
+/**
+ * @brief Clear the status received flag.
+ *
+ * @param data - pointer to source emulator partner data
+ */
+void tcpci_src_emul_clear_status_received(struct tcpci_src_emul_data *data);
+
+/**
+ * @}
+ */
+
+#endif /* __EMUL_TCPCI_PARTNER_SRC_H */
diff --git a/zephyr/include/emul/tcpc/emul_tcpci_partner_vpd.h b/zephyr/include/emul/tcpc/emul_tcpci_partner_vpd.h
new file mode 100644
index 0000000000..6de0452b05
--- /dev/null
+++ b/zephyr/include/emul/tcpc/emul_tcpci_partner_vpd.h
@@ -0,0 +1,49 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ *
+ * @brief Backend API for USB-C VCONN-powered device emulator
+ */
+
+#ifndef __EMUL_TCPCI_PARTNER_VPD_H
+#define __EMUL_TCPCI_PARTNER_VPD_H
+
+#include "emul/tcpc/emul_tcpci_partner_common.h"
+#include "emul/tcpc/emul_tcpci_partner_faulty_ext.h"
+#include "emul/tcpc/emul_tcpci_partner_snk.h"
+#include "emul/tcpc/emul_tcpci_partner_src.h"
+
+#include <zephyr/drivers/emul.h>
+
+/**
+ * @brief USB-C VCONN-powered device extension backend API
+ * @defgroup tcpci_src_emul USB-C source device extension
+ * @{
+ */
+
+struct tcpci_vpd_emul_data {
+	/** Common extension structure */
+	struct tcpci_partner_extension ext;
+	/** Pointer to common TCPCI partner data */
+	struct tcpci_partner_data *common_data;
+	struct tcpci_faulty_ext_data fault_ext;
+	struct tcpci_faulty_ext_action fault_actions[1];
+	struct tcpci_snk_emul_data snk_ext;
+	struct tcpci_src_emul_data src_ext;
+	bool charge_through_connected;
+};
+
+struct tcpci_partner_extension *
+tcpci_vpd_emul_init(struct tcpci_vpd_emul_data *data,
+		    struct tcpci_partner_data *common_data,
+		    struct tcpci_partner_extension *ext);
+
+/**
+ * @}
+ */
+
+#endif /* __EMUL_TCPCI_PARTNER_VPD_H */
diff --git a/zephyr/include/emul/utils.h b/zephyr/include/emul/utils.h
new file mode 100644
index 0000000000..1f3a39000e
--- /dev/null
+++ b/zephyr/include/emul/utils.h
@@ -0,0 +1,50 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ *
+ * @brief Utils for emulators.
+ */
+
+#ifndef ZEPHYR_INCLUDE_EMUL_UTILS_H_
+#define ZEPHYR_INCLUDE_EMUL_UTILS_H_
+
+/**
+ * @brief Helper macro for EMUL_GET_USBC_PROP_BINDING.
+ *
+ * If the usbc-port-number @p usbc_id has the same phandle in the @p chip
+ * property as the @p node, then the chip binding of the usbc-port-number is
+ * returned.
+ *
+ * @param usbc_id Named usbc port ID.
+ * @param chip Name of chip phandle property to match.
+ * @param node Emulator node to match the phandle of property @p chip in
+ * named-usbc-port.
+ * @param prop The name of the returned chip binding.
+ *
+ * @return The chip binding of the usbc-port-number, or NULL if no match is
+ * found.
+ */
+#define EMUL_GET_USBC_PROP_BINDING_IF_NODE_MATCH(usbc_id, chip, node, prop) \
+	(DT_DEP_ORD(node) ==                                                \
+	 DT_DEP_ORD(COND_CODE_1(DT_NODE_HAS_PROP(usbc_id, chip),            \
+				(DT_PHANDLE(usbc_id, chip)), (DT_ROOT)))) ? \
+		EMUL_DT_GET(DT_PROP_BY_IDX(usbc_id, prop, 0)):
+
+/**
+ * @brief Get emulator binding from the property of named-usbc-port @p prop if
+ * @p chip and the emulator node @p node matched.
+ *
+ * @param chip Name of chip property that is phandle to required emulator.
+ * @param node Node of the emulator which is the phandle of the prop of the
+ * named-usbc-port.
+ * @param prop The chip binding of the named-usbc-port which matched chip.
+ */
+#define EMUL_GET_USBC_PROP_BINDING(chip, node, prop)                       \
+	(DT_FOREACH_STATUS_OKAY_VARGS(                                     \
+		named_usbc_port, EMUL_GET_USBC_PROP_BINDING_IF_NODE_MATCH, \
+		chip, node, prop) NULL)
+#endif /* ZEPHYR_INCLUDE_EMUL_UTILS_H_ */
diff --git a/zephyr/include/soc/ite_it8xxx2/reg_def_cros.h b/zephyr/include/soc/ite_it8xxx2/reg_def_cros.h
new file mode 100644
index 0000000000..418ae39d3a
--- /dev/null
+++ b/zephyr/include/soc/ite_it8xxx2/reg_def_cros.h
@@ -0,0 +1,54 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * @file
+ * @brief ITE it8xxx2 register structure definitions used by the Chrome OS EC.
+ */
+
+#ifndef _ITE_IT8XXX2_REG_DEF_CROS_H
+#define _ITE_IT8XXX2_REG_DEF_CROS_H
+
+/*
+ * ECPM (EC Clock and Power Management) device registers
+ */
+struct ecpm_reg {
+	/* 0x000: Reserved1 */
+	volatile uint8_t reserved1;
+	/* 0x001: Clock Gating Control 1 */
+	volatile uint8_t ECPM_CGCTRL1;
+	/* 0x002: Clock Gating Control 2 */
+	volatile uint8_t ECPM_CGCTRL2;
+	/* 0x003: PLL Control */
+	volatile uint8_t ECPM_PLLCTRL;
+	/* 0x004: Auto Clock Gating */
+	volatile uint8_t ECPM_AUTOCG;
+	/* 0x005: Clock Gating Control 3 */
+	volatile uint8_t ECPM_CGCTRL3;
+	/* 0x006: PLL Frequency */
+	volatile uint8_t ECPM_PLLFREQ;
+	/* 0x007: Reserved2 */
+	volatile uint8_t reserved2;
+	/* 0x008: PLL Clock Source Status */
+	volatile uint8_t ECPM_PLLCSS;
+	/* 0x009: Clock Gating Control 4 */
+	volatile uint8_t ECPM_CGCTRL4;
+	/* 0x00A: Reserved3 */
+	volatile uint8_t reserved3;
+	/* 0x00B: Reserved4 */
+	volatile uint8_t reserved4;
+	/* 0x00C: System Clock Divide Control 0 */
+	volatile uint8_t ECPM_SCDCR0;
+	/* 0x00D: System Clock Divide Control 1 */
+	volatile uint8_t ECPM_SCDCR1;
+	/* 0x00E: System Clock Divide Control 2 */
+	volatile uint8_t ECPM_SCDCR2;
+	/* 0x00F: System Clock Divide Control 3 */
+	volatile uint8_t ECPM_SCDCR3;
+	/* 0x010: System Clock Divide Control 4 */
+	volatile uint8_t ECPM_SCDCR4;
+};
+
+#endif /* _ITE_IT8XXX2_REG_DEF_CROS_H */
diff --git a/zephyr/include/soc/microchip_xec/reg_def_cros.h b/zephyr/include/soc/microchip_xec/reg_def_cros.h
new file mode 100644
index 0000000000..b4b849a90d
--- /dev/null
+++ b/zephyr/include/soc/microchip_xec/reg_def_cros.h
@@ -0,0 +1,41 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * @file
+ * @brief Microchip XEC register structure definitions used by the Chrome OS EC.
+ */
+
+#ifndef _MICROCHIP_XEC_REG_DEF_CROS_H
+#define _MICROCHIP_XEC_REG_DEF_CROS_H
+
+/* RTC register structure */
+struct rtc_hw {
+	__IOM uint8_t SECV; /*!< (@ 0x0000) RTC seconds value */
+	__IOM uint8_t SECA; /*!< (@ 0x0001) RTC seconds alarm */
+	__IOM uint8_t MINV; /*!< (@ 0x0002) RTC minutes value */
+	__IOM uint8_t MINA; /*!< (@ 0x0003) RTC minutes alarm */
+	__IOM uint8_t HRSV; /*!< (@ 0x0004) RTC hours value, AM/PM indicator */
+	__IOM uint8_t HRSA; /*!< (@ 0x0005) RTC hours alarm */
+	__IOM uint8_t DOWV; /*!< (@ 0x0006) RTC day of week value */
+	__IOM uint8_t DOMV; /*!< (@ 0x0007) RTC day of month value */
+	__IOM uint8_t MONV; /*!< (@ 0x0008) RTC month value */
+	__IOM uint8_t YEARV; /*!< (@ 0x0009) RTC Year value */
+	__IOM uint8_t REGA; /*!< (@ 0x000A) RTC register A */
+	__IOM uint8_t REGB; /*!< (@ 0x000B) RTC register B */
+	__IOM uint8_t REGC; /*!< (@ 0x000C) RTC register C */
+	__IOM uint8_t REGD; /*!< (@ 0x000D) RTC register D */
+	__IM uint16_t RESERVED;
+	__IOM uint8_t CTRL; /*!< (@ 0x0010) RTC control */
+	__IM uint8_t RESERVED1;
+	__IM uint16_t RESERVED2;
+	__IOM uint8_t WKA; /*!< (@ 0x0014) RTC week alarm */
+	__IM uint8_t RESERVED3;
+	__IM uint16_t RESERVED4;
+	__IOM uint32_t DLSF; /*!< (@ 0x0018) RTC daylight savings forward */
+	__IOM uint32_t DLSB; /*!< (@ 0x001C) RTC daylight savings backward */
+};
+
+#endif /* _MICROCHIP_XEC_REG_DEF_CROS_H */
diff --git a/zephyr/include/soc/nuvoton_npcx/reg_def_cros.h b/zephyr/include/soc/nuvoton_npcx/reg_def_cros.h
new file mode 100644
index 0000000000..16012c083e
--- /dev/null
+++ b/zephyr/include/soc/nuvoton_npcx/reg_def_cros.h
@@ -0,0 +1,28 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * @file
+ * @brief Nuvoton NPCX register structure definitions used by the Chrome OS EC.
+ */
+
+#ifndef _NUVOTON_NPCX_REG_DEF_CROS_H
+#define _NUVOTON_NPCX_REG_DEF_CROS_H
+
+/*
+ * Monotonic Counter (MTC) device registers
+ */
+struct mtc_reg {
+	/* 0x000: Timing Ticks Count Register */
+	volatile uint32_t TTC;
+	/* 0x004: Wake-Up Ticks Count Register */
+	volatile uint32_t WTC;
+};
+
+/* MTC register fields */
+#define NPCX_WTC_PTO 30
+#define NPCX_WTC_WIE 31
+
+#endif /* _NUVOTON_NPCX_REG_DEF_CROS_H */
diff --git a/zephyr/linker/CMakeLists.txt b/zephyr/linker/CMakeLists.txt
new file mode 100644
index 0000000000..adffc2246f
--- /dev/null
+++ b/zephyr/linker/CMakeLists.txt
@@ -0,0 +1,27 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Add the fixed sections to the output image.
+zephyr_linker_sources(ROM_START SORT_KEY 1 fixed-sections.ld)
+
+# Support protection of part of the internal RAM
+zephyr_linker_sources(RWDATA SORT_KEY 1 iram_text.ld)
+
+# Compute the image size
+zephyr_linker_sources(RAM_SECTIONS image_size.ld)
+
+# Little FW with specific purposes used by NPCX EC
+zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_NPCX ROM_START SORT_KEY 1
+  npcx-lfw.ld)
+
+# Little FW with specific purposes used by MCHP XEC EC family
+zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_MEC ROM_START SORT_KEY 1
+  mchp-xec-lfw.ld)
+
+zephyr_linker_sources(DATA_SECTIONS iterables-ram.ld)
+zephyr_linker_sources(SECTIONS iterables-rom.ld)
+
+# Ensure there's space for panic and jump data at the end of ram
+# Must be added to "SECTIONS" because this is applied last
+zephyr_linker_sources(SECTIONS end-of-ram.ld)
diff --git a/zephyr/linker/end-of-ram.ld b/zephyr/linker/end-of-ram.ld
new file mode 100644
index 0000000000..91e8385950
--- /dev/null
+++ b/zephyr/linker/end-of-ram.ld
@@ -0,0 +1,29 @@
+/* Copyright 2022 The Chromium OS Authors.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* This section simply ensures there's enough unused space at the end of ram to
+ * hold panic and jump data. This space isn't directly allocated because it
+ * would result in the SRAM utilization always being reported as 100%.
+ */
+#if !defined(CONFIG_BOARD_NATIVE_POSIX)
+SECTION_PROLOGUE(.end_of_ram_info, 0, )
+{
+	ASSERT(DEFINED(_image_ram_end) && _image_ram_end > 0, "Error: _image_ram_end is not defined");
+
+#if defined(RAM_ADDR) && defined(RAM_SIZE) && defined(CONFIG_PLATFORM_EC_PRESERVED_END_OF_RAM_SIZE)
+	PROVIDE(__unused_ram_start = _image_ram_end);
+	PROVIDE(__unused_ram_end = RAM_ADDR + RAM_SIZE);
+	PROVIDE(__unused_ram_size = __unused_ram_end - __unused_ram_start);
+	ASSERT(__unused_ram_size >= CONFIG_PLATFORM_EC_PRESERVED_END_OF_RAM_SIZE,
+	       "ERROR: Not enough space for preserved end of ram data (see PLATFORM_EC_PRESERVED_END_OF_RAM_SIZE)");
+#endif
+
+#if defined(CONFIG_SHAREDMEM_MINIMUM_SIZE)
+	ASSERT(CONFIG_SHAREDMEM_MINIMUM_SIZE >= CONFIG_PLATFORM_EC_PRESERVED_END_OF_RAM_SIZE,
+	       "ERROR: Sharedmem must be at least large enough for preserved end of ram data");
+#endif
+
+}
+#endif
diff --git a/zephyr/linker/fixed-sections.ld b/zephyr/linker/fixed-sections.ld
new file mode 100644
index 0000000000..d4dcadcf0d
--- /dev/null
+++ b/zephyr/linker/fixed-sections.ld
@@ -0,0 +1,8 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#if defined(CONFIG_PLATFORM_EC) && !defined(CONFIG_ARCH_POSIX)
+*(.fixed.*)
+#endif
diff --git a/zephyr/linker/image_size.ld b/zephyr/linker/image_size.ld
new file mode 100644
index 0000000000..efeeafa3d4
--- /dev/null
+++ b/zephyr/linker/image_size.ld
@@ -0,0 +1,14 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#if defined(CONFIG_PLATFORM_EC_RW_TOTAL_IMAGE_SIZE)
+__image_size = CONFIG_PLATFORM_EC_RW_TOTAL_IMAGE_SIZE;
+#else
+/*
+ * Intentionally set to 0. Some components, such as EFS2, need this value.
+ * Having it be 0 will make it easier to find and add new cores.
+ */
+__image_size = 0;
+#endif
diff --git a/zephyr/linker/iram_text.ld b/zephyr/linker/iram_text.ld
new file mode 100644
index 0000000000..f01c3509da
--- /dev/null
+++ b/zephyr/linker/iram_text.ld
@@ -0,0 +1,23 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef CONFIG_ARCH_POSIX
+
+/* This code taken from core/cortex-m/ec.lds.S */
+
+#if defined(CONFIG_MPU)
+/* MPU regions must be aligned to a 32-byte boundary */
+#define _IRAM_ALIGN	32
+#else
+#define _IRAM_ALIGN	4
+#endif
+
+	. = ALIGN(_IRAM_ALIGN);
+	__iram_text_start = .;
+	*(.iram.text)
+	. = ALIGN(_IRAM_ALIGN);
+	__iram_text_end = .;
+
+#endif /* CONFIG_ARCH_POSIX */
diff --git a/zephyr/linker/iterables-ram.ld b/zephyr/linker/iterables-ram.ld
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/zephyr/linker/iterables-rom.ld b/zephyr/linker/iterables-rom.ld
new file mode 100644
index 0000000000..102d0c1dd1
--- /dev/null
+++ b/zephyr/linker/iterables-rom.ld
@@ -0,0 +1,17 @@
+#include <zephyr/linker/iterable_sections.h>
+
+#ifdef CONFIG_PLATFORM_EC_HOSTCMD
+ITERABLE_SECTION_ROM(host_command, 4)
+#endif
+
+#ifdef CONFIG_PLATFORM_EC_MKBP_EVENT
+ITERABLE_SECTION_ROM(mkbp_event_source, 4)
+#endif
+
+#ifdef CONFIG_PLATFORM_EC_HOOKS
+#include "../shim/include/hook_types.h"
+#define HOOK_TYPE_SECTION(type) \
+	ITERABLE_SECTION_ROM(zephyr_shim_hook_##type, 4)
+FOR_EACH(HOOK_TYPE_SECTION, (
+), HOOK_TYPES_LIST)
+#endif
diff --git a/zephyr/linker/mchp-xec-lfw.ld b/zephyr/linker/mchp-xec-lfw.ld
new file mode 100644
index 0000000000..6774c956a5
--- /dev/null
+++ b/zephyr/linker/mchp-xec-lfw.ld
@@ -0,0 +1,19 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+. = ALIGN(4);
+__lfw_text_start = .;
+*(.lfw.*)
+. = ALIGN(4);
+__lfw_text_end = .;
+
+#ifdef CONFIG_PLATFORM_EC_EXTERNAL_STORAGE
+. = ALIGN(4);
+__flash_lplfw_start = .;
+/* QSPI load and jump to EC image */
+KEEP(*(.code_in_sram2))
+. = ALIGN(4);
+__flash_lplfw_end = .;
+#endif /* CONFIG_PLATFORM_EC_EXTERNAL_STORAGE */
diff --git a/zephyr/linker/npcx-lfw.ld b/zephyr/linker/npcx-lfw.ld
new file mode 100644
index 0000000000..e69c4c2aa5
--- /dev/null
+++ b/zephyr/linker/npcx-lfw.ld
@@ -0,0 +1,24 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+. = ALIGN(4);
+__lfw_text_start = .;
+*(.lfw.*)
+. = ALIGN(4);
+__lfw_text_end = .;
+
+#ifdef CONFIG_PLATFORM_EC_EXTERNAL_STORAGE
+. = ALIGN(4);
+__flash_lpfw_start = .;
+/* Entering deep idle FW for better power consumption */
+KEEP(*(.lowpower_ram))
+. = ALIGN(4);
+__flash_lpfw_end = .;
+__flash_lplfw_start = .;
+/* GDMA utilities for better FW download speed */
+KEEP(*(.lowpower_ram2))
+. = ALIGN(4);
+__flash_lplfw_end = .;
+#endif /* CONFIG_PLATFORM_EC_EXTERNAL_STORAGE */
diff --git a/zephyr/mock/CMakeLists.txt b/zephyr/mock/CMakeLists.txt
new file mode 100644
index 0000000000..d8968f7b72
--- /dev/null
+++ b/zephyr/mock/CMakeLists.txt
@@ -0,0 +1,13 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+zephyr_library_sources_ifdef(CONFIG_POWER_SEQUENCE_MOCK power.c)
+zephyr_library_sources_ifdef(CONFIG_AP_POWER_EVENTS_MOCK ap_power_events.c)
+zephyr_library_sources_ifdef(CONFIG_POWER_SIGNALS_MOCK power_signals.c)
+
+cros_ec_library_include_directories(include)
+
+if(DEFINED CONFIG_POWER_SIGNALS_MOCK)
+  zephyr_include_directories("${PLATFORM_EC}/zephyr/subsys/ap_pwrseq/include")
+endif()
diff --git a/zephyr/mock/Kconfig b/zephyr/mock/Kconfig
new file mode 100644
index 0000000000..4bd86d7deb
--- /dev/null
+++ b/zephyr/mock/Kconfig
@@ -0,0 +1,21 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config POWER_SEQUENCE_MOCK
+	bool "Use a mocked power sequence driver."
+	help
+	  A simplified power sequence driver that invokes startup/shutdown
+	  and suspend/resume hooks in appropriate state transitions. Any
+	  request that comes in mid sequence is pended and ran after final
+	  state is reached.
+
+config AP_POWER_EVENTS_MOCK
+	bool "Use a mocked ap power events driver."
+	help
+	  A simplified ap power events driver that provides it's functions fakes.
+
+config POWER_SIGNALS_MOCK
+	bool "Use a mocked power signals driver."
+	help
+	  A simplified power signals driver that provides it's functions fakes.
diff --git a/zephyr/mock/ap_power_events.c b/zephyr/mock/ap_power_events.c
new file mode 100644
index 0000000000..a0b9d95f2c
--- /dev/null
+++ b/zephyr/mock/ap_power_events.c
@@ -0,0 +1,10 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/logging/log.h>
+
+#include <mock/ap_power_events.h>
+
+LOG_MODULE_REGISTER(mock_ap_power_events);
diff --git a/zephyr/mock/include/mock/ap_power_events.h b/zephyr/mock/include/mock/ap_power_events.h
new file mode 100644
index 0000000000..81ea01c4ad
--- /dev/null
+++ b/zephyr/mock/include/mock/ap_power_events.h
@@ -0,0 +1,22 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef ZEPHYR_TEST_MOCK_AP_POWER_EVENTS_H_
+#define ZEPHYR_TEST_MOCK_AP_POWER_EVENTS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include <zephyr/fff.h>
+
+#include <ap_power/ap_power.h>
+
+/* Mocks for ec/zephyr/include/ap_power/ap_power_events.h */
+DECLARE_FAKE_VOID_FUNC(ap_power_ev_send_callbacks, enum ap_power_events);
+
+void ap_power_ev_send_callbacks_custom_fake(enum ap_power_events event);
+
+#endif /* ZEPHYR_TEST_MOCK_AP_POWER_EVENTS_H_ */
diff --git a/zephyr/mock/include/mock/power.h b/zephyr/mock/include/mock/power.h
new file mode 100644
index 0000000000..f2d1460584
--- /dev/null
+++ b/zephyr/mock/include/mock/power.h
@@ -0,0 +1,48 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef ZEPHYR_TEST_MOCK_POWER_H
+#define ZEPHYR_TEST_MOCK_POWER_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include <zephyr/fff.h>
+
+#include <power.h>
+
+/* AP power state transition request types. */
+enum power_request_t {
+	POWER_REQ_NONE,
+	POWER_REQ_OFF,
+	POWER_REQ_ON,
+	POWER_REQ_SOFT_OFF,
+	POWER_REQ_COUNT,
+};
+
+/* Mocks for ec/power/common.c and board specific implementations */
+DECLARE_FAKE_VALUE_FUNC(enum power_state, power_handle_state, enum power_state);
+DECLARE_FAKE_VOID_FUNC(chipset_force_shutdown, enum chipset_shutdown_reason);
+DECLARE_FAKE_VOID_FUNC(chipset_power_on);
+DECLARE_FAKE_VALUE_FUNC(int, command_power, int, const char **);
+
+enum power_state power_handle_state_custom_fake(enum power_state state);
+
+void chipset_force_shutdown_custom_fake(enum chipset_shutdown_reason reason);
+
+void chipset_power_on_custom_fake(void);
+
+int command_power_custom_fake(int argc, const char **argv);
+
+/** @brief Mocks an AP power state change request.
+ *
+ * The mock power state will attempt to complete the request asynchronously.
+ *
+ * @param req The requested power state transition.
+ */
+void mock_power_request(enum power_request_t req);
+
+#endif /* ZEPHYR_TEST_MOCK_POWER_H */
diff --git a/zephyr/mock/include/mock/power_signals.h b/zephyr/mock/include/mock/power_signals.h
new file mode 100644
index 0000000000..f4397ea3ae
--- /dev/null
+++ b/zephyr/mock/include/mock/power_signals.h
@@ -0,0 +1,33 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef ZEPHYR_TEST_MOCK_POWER_SIGNALS_H
+#define ZEPHYR_TEST_MOCK_POWER_SIGNALS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include <stdint.h>
+
+#include <zephyr/fff.h>
+
+#include <power_signals.h>
+
+typedef uint32_t power_signal_mask_t;
+
+/* Mocks for ec/zephyr/subsys/ap_pwrseq/power_signals.c */
+DECLARE_FAKE_VALUE_FUNC(int, power_signal_set, enum power_signal, int);
+DECLARE_FAKE_VALUE_FUNC(int, power_signal_get, enum power_signal);
+DECLARE_FAKE_VALUE_FUNC(int, power_wait_mask_signals_timeout,
+			power_signal_mask_t, power_signal_mask_t, int);
+
+int power_signal_set_custom_fake(enum power_signal signal, int value);
+int power_signal_get_custom_fake(enum power_signal signal);
+int power_wait_mask_signals_timeout_custom_fake(power_signal_mask_t want,
+						power_signal_mask_t mask,
+						int timeout);
+
+#endif /* ZEPHYR_TEST_MOCK_POWER_SIGNALS_H */
diff --git a/zephyr/mock/power.c b/zephyr/mock/power.c
new file mode 100644
index 0000000000..b0de50a30e
--- /dev/null
+++ b/zephyr/mock/power.c
@@ -0,0 +1,268 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "hooks.h"
+#include "lid_switch.h"
+#include "mock/power.h"
+#include "power.h"
+#include "task.h"
+#include "util.h"
+
+#include <zephyr/logging/log.h>
+#include <zephyr/ztest.h>
+
+LOG_MODULE_REGISTER(mock_power);
+
+/* Mocks for ec/power/common.c and board specific implementations */
+DEFINE_FAKE_VALUE_FUNC(enum power_state, power_handle_state, enum power_state);
+DEFINE_FAKE_VOID_FUNC(chipset_force_shutdown, enum chipset_shutdown_reason);
+DEFINE_FAKE_VOID_FUNC(chipset_power_on);
+DEFINE_FAKE_VALUE_FUNC(int, command_power, int, const char **);
+
+#define MOCK_POWER_LIST(FAKE)                 \
+	{                                     \
+		FAKE(power_handle_state);     \
+		FAKE(chipset_force_shutdown); \
+		FAKE(chipset_power_on);       \
+		FAKE(command_power);          \
+	}
+
+/**
+ * @brief Reset all the fakes before each test.
+ */
+static void mock_power_rule_before(const struct ztest_unit_test *test,
+				   void *data)
+{
+	ARG_UNUSED(test);
+	ARG_UNUSED(data);
+
+	MOCK_POWER_LIST(RESET_FAKE);
+
+	FFF_RESET_HISTORY();
+
+	power_handle_state_fake.custom_fake = power_handle_state_custom_fake;
+	chipset_force_shutdown_fake.custom_fake =
+		chipset_force_shutdown_custom_fake;
+	chipset_power_on_fake.custom_fake = chipset_power_on_custom_fake;
+	command_power_fake.custom_fake = command_power_custom_fake;
+}
+
+ZTEST_RULE(mock_power_rule, mock_power_rule_before, NULL);
+
+static const char *power_req_name[POWER_REQ_COUNT] = {
+	"none",
+	"OFF",
+	"ON",
+	"SOFT_OFF",
+};
+
+static enum power_request_t current_power_request = POWER_REQ_NONE;
+static enum power_request_t pending_power_request = POWER_REQ_NONE;
+
+static void handle_power_request(enum power_request_t req)
+{
+	if (current_power_request == POWER_REQ_NONE) {
+		current_power_request = req;
+	} else if (current_power_request != req) {
+		LOG_INF("MOCK: Handling %s, pend %s request",
+			power_req_name[current_power_request],
+			power_req_name[req]);
+		pending_power_request = req;
+	}
+}
+
+void mock_power_request(enum power_request_t req)
+{
+	handle_power_request(req);
+	task_wake(TASK_ID_CHIPSET);
+	k_sleep(K_SECONDS(1));
+}
+
+void power_request_complete(void)
+{
+	current_power_request = pending_power_request;
+	pending_power_request = POWER_REQ_NONE;
+}
+
+void chipset_force_shutdown_custom_fake(enum chipset_shutdown_reason reason)
+{
+	LOG_INF("MOCK %s(%d)", __func__, reason);
+	handle_power_request(POWER_REQ_OFF);
+	task_wake(TASK_ID_CHIPSET);
+}
+
+void chipset_power_on_custom_fake(void)
+{
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
+		handle_power_request(POWER_REQ_ON);
+		task_wake(TASK_ID_CHIPSET);
+	}
+}
+
+/* Power states that we can report */
+enum power_state_t {
+	PSTATE_UNKNOWN,
+	PSTATE_OFF,
+	PSTATE_ON,
+	PSTATE_COUNT,
+};
+
+static const char *const state_name[] = {
+	"unknown",
+	"OFF",
+	"ON",
+};
+
+int command_power_custom_fake(int argc, const char **argv)
+{
+	int v, req;
+
+	if (argc < 2) {
+		enum power_state_t state;
+
+		state = PSTATE_UNKNOWN;
+		if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+			state = PSTATE_OFF;
+		if (chipset_in_state(CHIPSET_STATE_ON))
+			state = PSTATE_ON;
+		ccprintf("%s\n", state_name[state]);
+
+		return EC_SUCCESS;
+	}
+
+	if (!parse_bool(argv[1], &v)) {
+		return EC_ERROR_PARAM1;
+	}
+	req = v ? POWER_REQ_ON : POWER_REQ_OFF;
+	handle_power_request(req);
+	LOG_INF("MOCK: Requesting power %s\n", power_req_name[req]);
+	task_wake(TASK_ID_CHIPSET);
+
+	return EC_SUCCESS;
+}
+
+static void mock_lid_event(void)
+{
+	/* Power task only cares about lid-open events */
+	if (!lid_is_open()) {
+		return;
+	}
+
+	LOG_INF("MOCK: lid opened %s\n", power_req_name[POWER_REQ_ON]);
+	handle_power_request(POWER_REQ_ON);
+	task_wake(TASK_ID_CHIPSET);
+}
+DECLARE_HOOK(HOOK_LID_CHANGE, mock_lid_event, HOOK_PRIO_DEFAULT);
+
+enum power_state power_handle_state_custom_fake(enum power_state state)
+{
+	enum power_state new_state = state;
+	enum power_request_t request = current_power_request;
+
+	switch (state) {
+	/* Steady states */
+	case POWER_G3:
+		if (current_power_request == POWER_REQ_ON) {
+			new_state = POWER_G3S5;
+		} else if (current_power_request == POWER_REQ_OFF) {
+			new_state = state;
+			power_request_complete();
+		}
+		break;
+	case POWER_S5: /* System is soft-off */
+		if (current_power_request == POWER_REQ_ON) {
+			new_state = POWER_S5S3;
+		} else if (current_power_request == POWER_REQ_OFF) {
+			/* S5 timeout should transition to G3 */
+		} else if (current_power_request == POWER_REQ_SOFT_OFF) {
+			power_request_complete();
+		}
+		break;
+	case POWER_S3: /* Suspend; RAM on, processor is asleep */
+		if (current_power_request == POWER_REQ_ON) {
+			new_state = POWER_S3S0;
+		} else if (current_power_request == POWER_REQ_OFF ||
+			   current_power_request == POWER_REQ_SOFT_OFF) {
+			new_state = POWER_S3S5;
+		}
+		break;
+	case POWER_S0: /* System is on */
+		if (current_power_request == POWER_REQ_ON) {
+			new_state = state;
+			power_request_complete();
+
+			sleep_notify_transition(SLEEP_NOTIFY_RESUME,
+						HOOK_CHIPSET_RESUME);
+		} else if (current_power_request == POWER_REQ_OFF ||
+			   current_power_request == POWER_REQ_SOFT_OFF) {
+			new_state = POWER_S0S3;
+		}
+		break;
+	case POWER_S4: /* System is suspended to disk */
+#ifdef CONFIG_POWER_S0IX
+	case POWER_S0ix:
+#endif
+		new_state = state;
+		break;
+	/* Transitions */
+	case POWER_S3S0: /* S3 -> S0 */
+#ifdef CONFIG_CHIPSET_RESUME_INIT_HOOK
+		hook_notify(HOOK_CHIPSET_RESUME_INIT);
+#endif
+		hook_notify(HOOK_CHIPSET_RESUME);
+		sleep_resume_transition();
+		power_request_complete();
+		disable_sleep(SLEEP_MASK_AP_RUN);
+		new_state = POWER_S0;
+		break;
+	case POWER_S0S3: /* S0 -> S3 */
+		sleep_notify_transition(SLEEP_NOTIFY_SUSPEND,
+					HOOK_CHIPSET_SUSPEND);
+		hook_notify(HOOK_CHIPSET_SUSPEND);
+#ifdef CONFIG_CHIPSET_RESUME_INIT_HOOK
+		hook_notify(HOOK_CHIPSET_SUSPEND_COMPLETE);
+#endif
+		sleep_suspend_transition();
+		enable_sleep(SLEEP_MASK_AP_RUN);
+		new_state = POWER_S3;
+		break;
+	case POWER_S5S3: /* S5 -> S3 (skips S4 on non-Intel systems) */
+		hook_notify(HOOK_CHIPSET_PRE_INIT);
+		hook_notify(HOOK_CHIPSET_STARTUP);
+		sleep_reset_tracking();
+		new_state = POWER_S3;
+		break;
+	case POWER_S3S5: /* S3 -> S5 (skips S4 on non-Intel systems) */
+		hook_notify(HOOK_CHIPSET_SHUTDOWN);
+		hook_notify(HOOK_CHIPSET_SHUTDOWN_COMPLETE);
+		new_state = POWER_S5;
+		break;
+	case POWER_G3S5: /* G3 -> S5 (at system init time) */
+		new_state = POWER_S5;
+		break;
+	case POWER_S5G3: /* S5 -> G3 */
+		new_state = POWER_G3;
+		break;
+#ifdef CONFIG_POWER_S0IX
+	case POWER_S0ixS0: /* S0ix -> S0 */
+		new_state = POWER_S0;
+		break;
+	case POWER_S0S0ix: /* S0 -> S0ix */
+		new_state = POWER_S0ix;
+		break;
+#endif
+	case POWER_S5S4: /* S5 -> S4 */
+	case POWER_S4S3: /* S4 -> S3 */
+	case POWER_S3S4: /* S3 -> S4 */
+	case POWER_S4S5: /* S4 -> S5 */
+	default:
+		break;
+	}
+
+	LOG_INF("MOCK: power request=%u, state=%u -> new_state=%u\n", request,
+		state, new_state);
+
+	return new_state;
+}
diff --git a/zephyr/mock/power_signals.c b/zephyr/mock/power_signals.c
new file mode 100644
index 0000000000..6d1f7b759e
--- /dev/null
+++ b/zephyr/mock/power_signals.c
@@ -0,0 +1,10 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/logging/log.h>
+
+#include <mock/power_signals.h>
+
+LOG_MODULE_REGISTER(mock_power_signals);
diff --git a/zephyr/module.yml b/zephyr/module.yml
index a8ea98bece..286c090bbd 100644
--- a/zephyr/module.yml
+++ b/zephyr/module.yml
@@ -1,7 +1,9 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 build:
-  cmake: zephyr/
-  kconfig: zephyr/Kconfig
+  cmake: .
+  kconfig: Kconfig
+  settings:
+    board_root: zephyr/
diff --git a/zephyr/program/.pylintrc b/zephyr/program/.pylintrc
new file mode 100644
index 0000000000..8bdb6378e4
--- /dev/null
+++ b/zephyr/program/.pylintrc
@@ -0,0 +1,28 @@
+[BASIC]
+additional-builtins=
+    here,
+    register_binman_project,
+    register_host_project,
+    register_host_test,
+    register_mchp_project,
+    register_npcx_project,
+    register_raw_project,
+good-names=BUILD
+
+# cros lint doesn't inherit the pylintrc from the parent dir.
+# These settings are copied from platform/ec/pylintrc
+[MESSAGES CONTROL]
+
+disable=
+    bad-continuation,
+    bad-whitespace,
+    # These have nothing to do with black, they are just annoying
+    fixme,
+    too-many-arguments,
+    too-many-statements,
+    too-many-branches,
+    too-many-locals
+
+[format]
+
+string-quote=double
diff --git a/zephyr/program/brya/BUILD.py b/zephyr/program/brya/BUILD.py
new file mode 100644
index 0000000000..6395cbc68b
--- /dev/null
+++ b/zephyr/program/brya/BUILD.py
@@ -0,0 +1,44 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Define zmake projects for brya."""
+
+
+def register_npcx9_variant(
+    project_name, extra_dts_overlays=(), extra_kconfig_files=()
+):
+    """Register a variant of a brya, even though this is not named as such."""
+    return register_npcx_project(
+        project_name=project_name,
+        zephyr_board="npcx9m3f",
+        dts_overlays=[
+            "adc.dts",
+            "battery.dts",
+            "fan.dts",
+            "gpio.dts",
+            "i2c.dts",
+            "interrupts.dts",
+            "keyboard.dts",
+            "motionsense.dts",
+            "pwm_leds.dts",
+            "temp_sensors.dts",
+            "usbc.dts",
+            # Project-specific DTS customization.
+            *extra_dts_overlays,
+        ],
+        kconfig_files=[
+            # Common to all projects.
+            here / "prj.conf",
+            # Project-specific KConfig customization.
+            *extra_kconfig_files,
+        ],
+        inherited_from=["brya"],
+    )
+
+
+brya = register_npcx9_variant(
+    project_name="brya",
+    extra_dts_overlays=[here / "brya.dts"],
+    extra_kconfig_files=[here / "prj_brya.conf"],
+)
diff --git a/zephyr/program/brya/CMakeLists.txt b/zephyr/program/brya/CMakeLists.txt
new file mode 100644
index 0000000000..11c1a8386f
--- /dev/null
+++ b/zephyr/program/brya/CMakeLists.txt
@@ -0,0 +1,39 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(brya)
+
+set(PLATFORM_EC_BOARD "${PLATFORM_EC}/board/brya" CACHE PATH
+    "Path to the platform/ec board directory")
+set(PLATFORM_EC_BASEBOARD "${PLATFORM_EC}/baseboard/brya" CACHE PATH
+    "Path to the platform/ec baseboard directory")
+
+# Include board specific header files
+zephyr_include_directories(
+  include
+  "${PLATFORM_EC}/driver/tcpm"
+  "${PLATFORM_EC_BASEBOARD}"
+  "${PLATFORM_EC_BOARD}")
+
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_BATTERY
+  "${PLATFORM_EC_BASEBOARD}/battery_presence.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CBI_EEPROM
+  "${PLATFORM_EC_BASEBOARD}/cbi.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_PWM_KBLIGHT
+  "kblight_hooks.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_BATTERY
+  "${PLATFORM_EC_BASEBOARD}/battery_presence.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_BATTERY
+  "battery_present.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_POWER_DELIVERY
+  "${PLATFORM_EC_BASEBOARD}/usb_pd_policy.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC
+  "${PLATFORM_EC_BOARD}/usbc_config.c"
+  "${PLATFORM_EC_BOARD}/fw_config.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGE_MANAGER
+  "${PLATFORM_EC_BOARD}/charger.c"
+  "${PLATFORM_EC}/common/math_util.c")
diff --git a/zephyr/program/brya/Kconfig b/zephyr/program/brya/Kconfig
new file mode 100644
index 0000000000..4dd8e23443
--- /dev/null
+++ b/zephyr/program/brya/Kconfig
@@ -0,0 +1,11 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config BOARD_BRYA
+	bool "Google Brya Baseboard"
+	help
+	  Build Google Brya reference board. The board uses the Nuvuton NPCX9
+	  chip as the EC.
+
+source "Kconfig.zephyr"
diff --git a/zephyr/program/brya/adc.dts b/zephyr/program/brya/adc.dts
new file mode 100644
index 0000000000..f3f0d1e064
--- /dev/null
+++ b/zephyr/program/brya/adc.dts
@@ -0,0 +1,36 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		adc_ddr_soc: ddr_soc {
+			enum-name = "ADC_TEMP_SENSOR_1_DDR_SOC";
+			io-channels = <&adc0 0>;
+		};
+		adc_ambient: ambient {
+			enum-name = "ADC_TEMP_SENSOR_2_AMBIENT";
+			io-channels = <&adc0 1>;
+		};
+		adc_charger: charger {
+			enum-name = "ADC_TEMP_SENSOR_3_CHARGER";
+			io-channels = <&adc0 6>;
+		};
+		adc_wwan: wwan {
+			enum-name = "ADC_TEMP_SENSOR_4_WWAN";
+			io-channels = <&adc0 7>;
+		};
+	};
+};
+
+&adc0 {
+	status = "okay";
+	pinctrl-0 = <&adc0_chan0_gp45
+		     &adc0_chan1_gp44
+		     &adc0_chan6_gp34
+		     &adc0_chan7_gpe1>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/brya/battery.dts b/zephyr/program/brya/battery.dts
new file mode 100644
index 0000000000..4844d88d92
--- /dev/null
+++ b/zephyr/program/brya/battery.dts
@@ -0,0 +1,15 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	batteries {
+		default_battery: batgqa05l22 {
+			compatible = "powertech,batgqa05l22", "battery-smart";
+		};
+		lgc_ac17a8m {
+			compatible = "lgc,ac17a8m", "battery-smart";
+		};
+	};
+};
diff --git a/zephyr/program/brya/battery_present.c b/zephyr/program/brya/battery_present.c
new file mode 100644
index 0000000000..b2af448271
--- /dev/null
+++ b/zephyr/program/brya/battery_present.c
@@ -0,0 +1,21 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "battery.h"
+#include "cbi.h"
+
+#include <zephyr/drivers/gpio.h>
+
+enum battery_present battery_hw_present(void)
+{
+	const struct gpio_dt_spec *batt_pres;
+
+	if (get_board_id() == 1)
+		batt_pres = GPIO_DT_FROM_NODELABEL(gpio_id_1_ec_batt_pres_odl);
+	else
+		batt_pres = GPIO_DT_FROM_NODELABEL(gpio_ec_batt_pres_odl);
+
+	/* The GPIO is low when the battery is physically present */
+	return gpio_pin_get_dt(batt_pres) ? BP_NO : BP_YES;
+}
diff --git a/zephyr/program/brya/brya.dts b/zephyr/program/brya/brya.dts
new file mode 100644
index 0000000000..4b0490afa9
--- /dev/null
+++ b/zephyr/program/brya/brya.dts
@@ -0,0 +1,24 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	model = "Google Brya Baseboard";
+
+	chosen {
+		cros,rtc = &mtc;
+	};
+
+	ec-console {
+		compatible = "ec-console";
+		disabled = "events", "lpc", "hostcmd";
+	};
+};
+
+/* host interface */
+&espi0 {
+	status = "okay";
+	pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/brya/fan.dts b/zephyr/program/brya/fan.dts
new file mode 100644
index 0000000000..aa6dcfde7d
--- /dev/null
+++ b/zephyr/program/brya/fan.dts
@@ -0,0 +1,39 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	fans {
+		compatible = "cros-ec,fans";
+
+		fan_0 {
+			pwms = <&pwm5 0 PWM_KHZ(1) PWM_POLARITY_NORMAL>;
+			rpm_min = <2200>;
+			rpm_start = <2200>;
+			rpm_max = <4200>;
+			tach = <&tach1>;
+			enable_gpio = <&gpio_en_pp5000_fan>;
+		};
+	};
+};
+
+/* Tachemeter for fan speed measurement */
+&tach1 {
+	status = "okay";
+	pinctrl-0 = <&ta1_1_in_gp40>;
+	pinctrl-names = "default";
+	port = <NPCX_TACH_PORT_A>; /* port-A is selected */
+	sample-clk = <NPCX_TACH_FREQ_LFCLK>; /* Use LFCLK as sampling clock */
+	pulses-per-round = <2>; /* number of pulses per round of encoder */
+};
+
+&pwm5_gpb7 {
+	drive-open-drain;
+};
+
+&pwm5 {
+	status = "okay";
+	pinctrl-0 = <&pwm5_gpb7>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/brya/gpio.dts b/zephyr/program/brya/gpio.dts
new file mode 100644
index 0000000000..b48077d96a
--- /dev/null
+++ b/zephyr/program/brya/gpio.dts
@@ -0,0 +1,333 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	aliases {
+		gpio-wp = &gpio_ec_wp_l;
+		gpio-kbd-kso2 = &gpio_ec_kso_02_inv;
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		lid_open: lid_open {
+			gpios = <&gpiod 2 GPIO_INPUT>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+		gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl {
+			gpios = <&gpio0 1 GPIO_INPUT>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		gpio_ec_wp_l: ec_wp_odl {
+			gpios = <&gpioa 1 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		charger_vap_otg_en {
+			gpios = <&gpio7 3 GPIO_OUTPUT_LOW>;
+		};
+
+		/*
+		 * Board ID 1 repurposes the gpio_ec_batt_pres_odl pin as
+		 * an output signal.  The board code switches the pin
+		 * pin configuration to an output when board ID 1 is detected.
+		 */
+		gpio_id_1_ec_kb_bl_en: gpio_ec_batt_pres_odl: ec_batt_pres_odl {
+			gpios = <&gpioa 3 GPIO_INPUT>;
+			enum-name = "GPIO_BATT_PRES_ODL";
+		};
+		gpio_id_1_ec_batt_pres_odl: id_1_ec_batt_pres_odl {
+			gpios = <&gpioe 1 GPIO_INPUT>;
+		};
+		ec_i2c_bat_scl {
+			gpios = <&gpio3 3 GPIO_INPUT>;
+		};
+		ec_i2c_bat_sda {
+			gpios = <&gpio3 6 GPIO_INPUT>;
+		};
+		gpio_ec_kb_bl_en_l: ec_kb_bl_en_l {
+			gpios = <&gpio8 6 GPIO_OUTPUT_HIGH>;
+		};
+		ec_i2c_misc_scl_r {
+			gpios = <&gpiob 3 GPIO_INPUT>;
+		};
+		ec_i2c_misc_sda_r {
+			gpios = <&gpiob 2 GPIO_INPUT>;
+		};
+		ec_i2c_sensor_scl {
+			gpios = <&gpiob 5 GPIO_INPUT>;
+		};
+		ec_i2c_sensor_sda {
+			gpios = <&gpiob 4 GPIO_INPUT>;
+		};
+		ec_i2c_usb_c0_c2_ppc_bc_scl {
+			gpios = <&gpio9 2 GPIO_INPUT>;
+		};
+		ec_i2c_usb_c0_c2_ppc_bc_sda {
+			gpios = <&gpio9 1 GPIO_INPUT>;
+		};
+		ec_i2c_usb_c0_c2_rt_scl {
+			gpios = <&gpiod 1 GPIO_INPUT>;
+		};
+		ec_i2c_usb_c0_c2_rt_sda {
+			gpios = <&gpiod 0 GPIO_INPUT>;
+		};
+		ec_i2c_usb_c0_c2_tcpc_scl {
+			gpios = <&gpio9 0 GPIO_INPUT>;
+		};
+		ec_i2c_usb_c0_c2_tcpc_sda {
+			gpios = <&gpio8 7 GPIO_INPUT>;
+		};
+		ec_i2c_usb_c1_mix_scl {
+			gpios = <&gpioe 4 GPIO_INPUT>;
+		};
+		ec_i2c_usb_c1_mix_sda {
+			gpios = <&gpioe 3 GPIO_INPUT>;
+		};
+		ec_i2c_usb_c1_tcpc_scl {
+			gpios = <&gpiof 3 GPIO_INPUT>;
+		};
+		ec_i2c_usb_c1_tcpc_sda {
+			gpios = <&gpiof 2 GPIO_INPUT>;
+		};
+		ec_chg_led_y_c1 {
+			gpios = <&gpioc 3 GPIO_OUTPUT_LOW>;
+		};
+		ec_chg_led_b_c1 {
+			gpios = <&gpioc 4 GPIO_OUTPUT_LOW>;
+		};
+		ec_gsc_packet_mode {
+			gpios = <&gpio7 5 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_PACKET_MODE_EN";
+		};
+		gpio_ec_accel_int_l: ec_accel_int_l {
+			gpios = <&gpio8 1 GPIO_INPUT>;
+		};
+		gpio_ec_imu_int_l: gpio_ec_imu_int_l {
+			gpios = <&gpio5 6 GPIO_INPUT>;
+		};
+		gpio_ec_als_rgb_int_l: gpio_ec_als_rgb_int_l {
+			gpios = <&gpiod 4 GPIO_INPUT>;
+		};
+		gpio_tablet_mode_l: tablet_mode_l {
+			gpios = <&gpio9 5 GPIO_INPUT>;
+			enum-name = "GPIO_TABLET_MODE_L";
+		};
+		acok_od: acok_od {
+			gpios = <&gpio0 0 GPIO_INPUT>;
+			enum-name = "GPIO_AC_PRESENT";
+		};
+		gpio_ec_kso_02_inv: ec_kso_02_inv {
+			gpios = <&gpio1 7 (GPIO_OUTPUT_LOW | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_ec_pch_wake_odl: ec_pch_wake_r_odl {
+			gpios = <&gpioc 0 GPIO_ODR_HIGH>;
+		};
+		ec_pch_int_odl {
+			gpios = <&gpiob 0 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_EC_INT_L";
+		};
+		gpio_pg_ec_dsw_pwrok: pg_ec_dsw_pwrok {
+			gpios = <&gpioc 7 GPIO_INPUT>;
+			enum-name = "GPIO_PG_EC_DSW_PWROK";
+			alias = "GPIO_SEQ_EC_DSW_PWROK";
+		};
+		en_s5_rails {
+			gpios = <&gpiob 6 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_EN_S5_RAILS";
+			alias = "GPIO_TEMP_SENSOR_POWER";
+		};
+		sys_rst_odl {
+			gpios = <&gpioc 5 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_SYS_RESET_L";
+		};
+		gpio_pg_ec_rsmrst_odl: pg_ec_rsmrst_odl {
+			gpios = <&gpioe 2 GPIO_INPUT>;
+			enum-name = "GPIO_PG_EC_RSMRST_ODL";
+		};
+		ec_pch_rsmrst_odl {
+			gpios = <&gpioa 6 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_PCH_RSMRST_L";
+		};
+		gpio_pg_ec_all_sys_pwrgd: pg_ec_all_sys_pwrgd {
+			gpios = <&gpiof 4 GPIO_INPUT>;
+			enum-name = "GPIO_PG_EC_ALL_SYS_PWRGD";
+		};
+		gpio_slp_s0_l: slp_s0_l {
+			gpios = <&gpiod 5 GPIO_INPUT>;
+			enum-name = "GPIO_PCH_SLP_S0_L";
+		};
+		gpio_slp_s3_l: slp_s3_l {
+			gpios = <&gpioa 5 GPIO_INPUT>;
+			enum-name = "GPIO_PCH_SLP_S3_L";
+		};
+		vccst_pwrgd_od {
+			gpios = <&gpioa 4 GPIO_ODR_LOW>;
+			enum-name = "GPIO_VCCST_PWRGD_OD";
+		};
+		ec_prochot_odl {
+			gpios = <&gpio6 3 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_CPU_PROCHOT";
+		};
+		ec_pch_pwr_btn_odl {
+			gpios = <&gpioc 1 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_PCH_PWRBTN_L";
+		};
+		gpio_slp_sus_l: slp_sus_l {
+			gpios = <&gpiof 1 GPIO_INPUT>;
+			enum-name = "GPIO_SLP_SUS_L";
+		};
+		pch_pwrok {
+			gpios = <&gpio7 2 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_PCH_PWROK";
+		};
+		ec_pch_sys_pwrok {
+			gpios = <&gpio3 7 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_EC_PCH_SYS_PWROK";
+		};
+		imvp9_vrrdy_od {
+			gpios = <&gpio4 3 GPIO_INPUT>;
+			enum-name = "GPIO_IMVP9_VRRDY_OD";
+		};
+		ec_edp_bl_en {
+			gpios = <&gpiod 3 GPIO_OUTPUT_HIGH>;
+			enum-name = "GPIO_ENABLE_BACKLIGHT";
+		};
+		gpio_ec_prochot_in_l: ec_prochot_in_l {
+			gpios = <&gpiof 0 GPIO_INPUT>;
+		};
+		gpio_en_pp5000_fan: en_pp5000_fan {
+			gpios = <&gpio6 1 GPIO_OUTPUT_HIGH>;
+		};
+		gpio_ec_voldn_btn_odl: ec_voldn_btn_odl {
+			gpios = <&gpio9 3 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_DOWN_L";
+		};
+		gpio_ec_volup_btn_odl: ec_volup_btn_odl {
+			gpios = <&gpio9 7 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_UP_L";
+		};
+		gpio_usb_c0_c2_tcpc_int_odl: usb_c0_c2_tcpc_int_odl {
+			gpios = <&gpioe 0 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_USB_C0_C2_TCPC_INT_ODL";
+		};
+		gpio_usb_c1_tcpc_int_odl: usb_c1_tcpc_int_odl {
+			gpios = <&gpioa 2 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_USB_C1_TCPC_INT_ODL";
+		};
+		gpio_usb_c0_ppc_int_odl: usb_c0_ppc_int_odl {
+			gpios = <&gpio6 2 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C0_PPC_INT_ODL";
+		};
+		gpio_usb_c1_ppc_int_odl: usb_c1_ppc_int_odl {
+			gpios = <&gpiof 5 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C1_PPC_INT_ODL";
+		};
+		gpio_usb_c2_ppc_int_odl: usb_c2_ppc_int_odl {
+			gpios = <&gpio7 0 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C2_PPC_INT_ODL";
+		};
+		gpio_usb_c0_bc12_int_odl: usb_c0_bc12_int_odl {
+			gpios = <&gpioc 6 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C0_BC12_INT_ODL";
+		};
+		gpio_usb_c1_bc12_int_odl: usb_c1_bc12_int_odl {
+			gpios = <&gpio5 0 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C1_BC12_INT_ODL";
+		};
+		gpio_usb_c2_bc12_int_odl: usb_c2_bc12_int_odl {
+			gpios = <&gpio8 3 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C2_BC12_INT_ODL";
+		};
+		gpio_en_pp5000_usba_r: en_pp5000_usba_r {
+			gpios = <&gpiod 7 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_EN_PP5000_USBA_R";
+		};
+		usb_c1_rt_rst_r_odl {
+			gpios = <&gpio0 2 GPIO_ODR_LOW>;
+			enum-name = "GPIO_USB_C1_RT_RST_R_ODL";
+		};
+		usb_c1_rst_odl {
+			gpios = <&gpio9 6 GPIO_ODR_LOW>;
+			enum-name = "GPIO_USB_C1_RST_ODL";
+		};
+		usb_c0_c2_tcpc_rst_odl {
+			gpios = <&gpioa 7 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_USB_C0_C2_TCPC_RST_ODL";
+		};
+		id_1_usb_c0_c2_tcpc_rst_odl {
+			gpios = <&gpio3 4 GPIO_ODR_LOW>;
+		};
+		usb_c0_rt_int_odl: usb_c0_rt_int_odl {
+			gpios = <&gpiob 1 GPIO_INPUT>;
+		};
+		usb_c2_rt_int_odl: usb_c2_rt_int_odl {
+			gpios = <&gpio4 1 GPIO_INPUT>;
+		};
+		usb_c0_oc_odl {
+			gpios = <&ioex_port1 4 GPIO_ODR_HIGH>;
+			no-auto-init;
+		};
+		usb_c0_frs_en: usb_c0_frs_en {
+			gpios = <&ioex_port1 6 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C0_FRS_EN";
+			no-auto-init;
+		};
+		usb_c0_rt_rst_odl: usb_c0_rt_rst_odl {
+			gpios = <&ioex_port1 7 GPIO_ODR_LOW>;
+			no-auto-init;
+		};
+		usb_c2_rt_rst_odl: usb_c2_rt_rst_odl {
+			gpios = <&ioex_port2 2 GPIO_ODR_LOW>;
+			no-auto-init;
+		};
+		usb_c1_oc_odl {
+			gpios = <&ioex_port2 3 GPIO_ODR_HIGH>;
+			no-auto-init;
+		};
+		usb_c2_oc_odl {
+			gpios = <&ioex_port2 4 GPIO_ODR_HIGH>;
+			no-auto-init;
+		};
+		usb_c2_frs_en: usb_c2_frs_en {
+			gpios = <&ioex_port2 6 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C2_FRS_EN";
+			no-auto-init;
+		};
+		/* unimplemented GPIOs */
+		entering-rw {
+			enum-name = "GPIO_ENTERING_RW";
+		};
+	};
+
+	usba-port-enable-list {
+		compatible = "cros-ec,usba-port-enable-pins";
+		enable-pins = <&gpio_en_pp5000_usba_r>;
+	};
+};
+
+/* Power switch logic input pads */
+/* LID_OPEN_OD */
+&psl_in1_gpd2 {
+	psl-in-mode = "edge";
+	psl-in-pol = "high-rising";
+};
+
+/* ACOK_EC_OD */
+&psl_in2_gp00 {
+	psl-in-mode = "edge";
+	psl-in-pol = "high-rising";
+};
+
+/* GSC_EC_PWR_BTN_ODL */
+&psl_in3_gp01 {
+	psl-in-mode = "edge";
+	psl-in-pol = "high-rising";
+};
+
+/* Power domain device controlled by PSL (Power Switch Logic) IO pads */
+&power_ctrl_psl {
+	status = "okay";
+	pinctrl-names = "sleep";
+	pinctrl-0 = <&psl_in1_gpd2 &psl_in2_gp00 &psl_in3_gp01>;
+};
diff --git a/zephyr/program/brya/i2c.dts b/zephyr/program/brya/i2c.dts
new file mode 100644
index 0000000000..8dbacc2119
--- /dev/null
+++ b/zephyr/program/brya/i2c.dts
@@ -0,0 +1,303 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+ #include <dt-bindings/usb_pd_tcpm.h>
+
+/ {
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+		i2c_sensor: sensor {
+			i2c-port = <&i2c0_0>;
+			enum-names = "I2C_PORT_SENSOR";
+		};
+		tcpc0_2: tcpc0_2 {
+			i2c-port = <&i2c1_0>;
+			enum-names = "I2C_PORT_USB_C0_C2_TCPC";
+		};
+		tcpc1: tcpc1 {
+			i2c-port = <&i2c4_1>;
+			enum-names = "I2C_PORT_USB_C1_TCPC";
+			dynamic-speed;
+		};
+		c0_c2_bc12: c0_c2_bc12 {
+			i2c-port = <&i2c2_0>;
+			enum-names = "I2C_PORT_USB_C0_C2_PPC",
+				"I2C_PORT_USB_C0_C2_BC12";
+		};
+		c1_bc12: c1_bc12 {
+			i2c-port = <&i2c6_1>;
+			enum-names = "I2C_PORT_USB_C1_PPC",
+				"I2C_PORT_USB_C1_BC12";
+			dynamic-speed;
+		};
+		retimer0_2: retimer0_2 {
+			i2c-port = <&i2c3_0>;
+			enum-names = "I2C_PORT_USB_C0_C2_MUX";
+		};
+		battery {
+			i2c-port = <&i2c5_0>;
+			enum-names = "I2C_PORT_BATTERY";
+		};
+		i2c_charger: charger {
+			i2c-port = <&i2c7_0>;
+			enum-names =  "I2C_PORT_CHARGER",
+				"I2C_PORT_EEPROM",
+				"I2C_PORT_MP2964";
+		};
+	};
+};
+
+&i2c0_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>;
+	pinctrl-names = "default";
+};
+
+&i2c_ctrl0 {
+	status = "okay";
+};
+
+&i2c1_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+	pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>;
+	pinctrl-names = "default";
+
+	tcpc_port0: nct38xx@70 {
+		compatible = "nuvoton,nct38xx";
+		reg = <0x70>;
+		gpio-dev = <&nct3808_0_P1>;
+		tcpc-flags = <(
+			TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_NO_DEBUG_ACC_CONTROL)>;
+		/* a duplicate of the <&gpio_usb_c0_c2_tcpc_int_odl> node in
+		 * "named-gpios". This is the Zephyr preferred style,
+		 * the "named-gpios" node will be dealt with at a later date.
+		 */
+		irq-gpios = <&gpioe 0 GPIO_ACTIVE_LOW>;
+	};
+
+	nct3808_0_P1: nct3808_0_P1@70 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nuvoton,nct38xx-gpio";
+		reg = <0x70>;
+		label = "NCT3808_0_P1";
+
+		ioex_port1: gpio@0 {
+			compatible = "nuvoton,nct38xx-gpio-port";
+			reg = <0x0>;
+			label = "NCT3808_0_P1_GPIO0";
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <8>;
+			pin_mask = <0xdc>;
+			pinmux_mask = <0xff>;
+		};
+	};
+
+	tcpc_port2: nct38xx@74 {
+		compatible = "nuvoton,nct38xx";
+		reg = <0x74>;
+		gpio-dev = <&nct3808_0_P2>;
+		tcpc-flags = <(TCPC_FLAGS_TCPCI_REV2_0)>;
+		/* a duplicate of the <&gpio_usb_c0_c2_tcpc_int_odl> node in
+		 * "named-gpios". This is the Zephyr preferred style,
+		 * the "named-gpios" node will be dealt with at a later date.
+		 */
+		irq-gpios = <&gpioe 0 GPIO_ACTIVE_LOW>;
+	};
+
+	nct3808_0_P2: nct3808_0_P2@74 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nuvoton,nct38xx-gpio";
+		reg = <0x74>;
+		label = "NCT3808_0_P2";
+
+		ioex_port2: gpio@0 {
+			compatible = "nuvoton,nct38xx-gpio-port";
+			reg = <0x0>;
+			label = "NCT3808_0_P2_GPIO0";
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <8>;
+			pin_mask = <0xdc>;
+			pinmux_mask = <0xff>;
+		};
+	};
+
+	nct3808_alert_1 {
+		compatible = "nuvoton,nct38xx-gpio-alert";
+		/* a duplicate of the <&gpio_usb_c0_c2_tcpc_int_odl> node in
+		 * "named-gpios". This is the Zephyr preferred style,
+		 * the "named-gpios" node will be dealt with at a later date.
+		 */
+		irq-gpios = <&gpioe 0 GPIO_ACTIVE_LOW>;
+		nct38xx-dev = <&nct3808_0_P1 &nct3808_0_P2>;
+		label = "NCT3808_ALERT_1";
+	};
+};
+
+&i2c_ctrl1 {
+	status = "okay";
+};
+
+&i2c2_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+	pinctrl-0 = <&i2c2_0_sda_scl_gp91_92>;
+	pinctrl-names = "default";
+
+	ppc_port0: syv682x@40 {
+		compatible = "silergy,syv682x";
+		status = "okay";
+		reg = <0x40>;
+		frs_en_gpio = <&usb_c0_frs_en>;
+	};
+
+	bc12_port0: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+		irq = <&int_usb_c0_bc12>;
+	};
+
+	ppc_port2: syv682x@42 {
+		compatible = "silergy,syv682x";
+		status = "okay";
+		reg = <0x42>;
+		frs_en_gpio = <&usb_c2_frs_en>;
+	};
+
+	bc12_port2: pi3usb9201@5d {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5d>;
+		irq = <&int_usb_c2_bc12>;
+	};
+};
+
+&i2c_ctrl2 {
+	status = "okay";
+};
+
+&i2c3_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+	pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>;
+	pinctrl-names = "default";
+
+	usb_c0_bb_retimer: jhl8040r-c0@56 {
+		compatible = "intel,jhl8040r";
+		reg = <0x56>;
+		int-pin = <&usb_c0_rt_int_odl>;
+		reset-pin = <&usb_c0_rt_rst_odl>;
+	};
+
+	usb_c2_bb_retimer: jhl8040r-c2@57 {
+		compatible = "intel,jhl8040r";
+		reg = <0x57>;
+		int-pin = <&usb_c2_rt_int_odl>;
+		reset-pin = <&usb_c2_rt_rst_odl>;
+	};
+};
+
+&i2c_ctrl3 {
+	status = "okay";
+};
+
+&i2c4_1 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c4_1_sda_scl_gpf2_f3>;
+	pinctrl-names = "default";
+
+	tcpc_port1: ps8xxx@b {
+		compatible = "parade,ps8xxx";
+		reg = <0xb>;
+		tcpc-flags = <(
+			TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V |
+			TCPC_FLAGS_CONTROL_VCONN |
+			TCPC_FLAGS_CONTROL_FRS)>;
+		/* a duplicate of the <&gpio_usb_c1_tcpc_int_odl> node in
+		 * "named-gpios". This is the Zephyr preferred style,
+		 * the "named-gpios" node will be dealt with at a later date.
+		 */
+		 irq-gpios = <&gpioa 2 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&i2c_ctrl4 {
+	status = "okay";
+};
+
+&i2c5_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	pinctrl-0 = <&i2c5_0_sda_scl_gp33_36>;
+	pinctrl-names = "default";
+};
+
+&i2c_ctrl5 {
+	status = "okay";
+};
+
+&i2c6_1 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c6_1_sda_scl_gpe3_e4>;
+	pinctrl-names = "default";
+
+	ppc_port1: nx20p348x@72 {
+		compatible = "nxp,nx20p348x";
+		status = "okay";
+		reg = <0x72>;
+	};
+
+	bc12_port1: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+		irq = <&int_usb_c1_bc12>;
+	};
+};
+
+&i2c_ctrl6 {
+	status = "okay";
+};
+
+&i2c7_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>;
+	pinctrl-names = "default";
+
+	pmic_mp2964@20 {
+		compatible = "mps,mp2964";
+		reg = <0x20>;
+	};
+
+	charger: bq25710@9 {
+		compatible = "ti,bq25710";
+		status = "okay";
+		reg = <0x9>;
+	};
+
+	cbi_eeprom: eeprom@50 {
+		compatible = "atmel,at24";
+		reg = <0x50>;
+		size = <2048>;
+		pagesize = <16>;
+		address-width = <8>;
+		timeout = <5>;
+	};
+};
+
+&i2c_ctrl7 {
+	status = "okay";
+};
diff --git a/zephyr/program/brya/interrupts.dts b/zephyr/program/brya/interrupts.dts
new file mode 100644
index 0000000000..ea5bcc542a
--- /dev/null
+++ b/zephyr/program/brya/interrupts.dts
@@ -0,0 +1,140 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	aliases {
+		int-wp = &int_wp;
+	};
+
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_tablet_mode: tablet_mode {
+			irq-pin = <&gpio_tablet_mode_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "gmr_tablet_switch_isr";
+		};
+		int_lid_open: lid_open {
+			irq-pin = <&lid_open>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "lid_interrupt";
+		};
+		int_power_button: power_button {
+			irq-pin = <&gsc_ec_pwr_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_button_interrupt";
+		};
+		int_wp: wp {
+			irq-pin = <&gpio_ec_wp_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "switch_interrupt";
+		};
+		int_ac_present: ac_present {
+			irq-pin = <&acok_od>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "extpower_interrupt";
+		};
+		int_volume_up: volume_up {
+			irq-pin = <&gpio_ec_volup_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+		int_volume_down: volume_down {
+			irq-pin = <&gpio_ec_voldn_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+		int_accel: accel {
+			irq-pin = <&gpio_ec_accel_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "lis2dw12_interrupt";
+		};
+		int_imu: imu {
+			irq-pin = <&gpio_ec_imu_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "lsm6dso_interrupt";
+		};
+		int_slp_s0: slp_s0 {
+			irq-pin = <&gpio_slp_s0_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_slp_s3: slp_s3 {
+			irq-pin = <&gpio_slp_s3_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_slp_sus: slp_sus {
+			irq-pin = <&gpio_slp_sus_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_pg_dsw_pwrok: pg_dsw_pwrok {
+			irq-pin = <&gpio_pg_ec_dsw_pwrok>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_pg_rsmrst_odl: pg_rsmrst_odl {
+			irq-pin = <&gpio_pg_ec_rsmrst_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_pg_all_sys_pwrgd: pg_all_sys_pwrgd {
+			irq-pin = <&gpio_pg_ec_all_sys_pwrgd>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_als_rgb: als_rgb {
+			irq-pin = <&gpio_ec_als_rgb_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "tcs3400_interrupt";
+		};
+		int_prochot: prochot {
+			irq-pin = <&gpio_ec_prochot_in_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "throttle_ap_prochot_input_interrupt";
+		};
+		int_usb_c0_ppc: usb_c0_ppc {
+			irq-pin = <&gpio_usb_c0_ppc_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "ppc_interrupt";
+		};
+		int_usb_c1_ppc: usb_c1_ppc {
+			irq-pin = <&gpio_usb_c1_ppc_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "ppc_interrupt";
+		};
+		int_usb_c2_ppc: usb_c2_ppc {
+			irq-pin = <&gpio_usb_c2_ppc_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "ppc_interrupt";
+		};
+		int_usb_c0_bc12: usb_c0_bc12 {
+			irq-pin = <&gpio_usb_c0_bc12_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "bc12_interrupt";
+		};
+		int_usb_c1_bc12: usb_c1_bc12 {
+			irq-pin = <&gpio_usb_c1_bc12_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "bc12_interrupt";
+		};
+		int_usb_c2_bc12: usb_c2_bc12 {
+			irq-pin = <&gpio_usb_c2_bc12_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "bc12_interrupt";
+		};
+		int_usb_c0_rt: usb_c0_rt {
+			irq-pin = <&usb_c0_rt_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "retimer_interrupt";
+		};
+		int_usb_c2_rt: usb_c2_rt {
+			irq-pin = <&usb_c2_rt_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "retimer_interrupt";
+		};
+	};
+};
diff --git a/zephyr/program/brya/kblight_hooks.c b/zephyr/program/brya/kblight_hooks.c
new file mode 100644
index 0000000000..a9b1b64a5c
--- /dev/null
+++ b/zephyr/program/brya/kblight_hooks.c
@@ -0,0 +1,79 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi.h"
+#include "hooks.h"
+
+#include <stdbool.h>
+
+#include <zephyr/drivers/gpio.h>
+
+#include <ap_power/ap_power.h>
+
+/* Enable/Disable keyboard backlight gpio */
+static inline void kbd_backlight_enable(bool enable)
+{
+	if (get_board_id() == 1)
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_id_1_ec_kb_bl_en),
+				enable);
+	else
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_kb_bl_en_l),
+				!enable);
+}
+
+static void board_backlight_handler(struct ap_power_ev_callback *cb,
+				    struct ap_power_ev_data data)
+{
+	bool enable;
+
+	switch (data.event) {
+	default:
+		return;
+
+	case AP_POWER_RESUME:
+		/* Called on AP S3 -> S0 transition */
+		enable = true;
+		break;
+
+	case AP_POWER_SUSPEND:
+		/* Called on AP S0 -> S3 transition */
+		enable = false;
+		break;
+	}
+	kbd_backlight_enable(enable);
+}
+
+/*
+ * Explicitly apply the board ID 1 *gpio.inc settings to pins that
+ * were reassigned on current boards.
+ */
+static void set_board_id_1_gpios(void)
+{
+	static struct ap_power_ev_callback cb;
+	const struct gpio_dt_spec *ec_kb_bl_en =
+		GPIO_DT_FROM_NODELABEL(gpio_id_1_ec_kb_bl_en);
+	gpio_flags_t flags = ec_kb_bl_en->dt_flags;
+
+	/*
+	 * Add a callback for suspend/resume to
+	 * control the keyboard backlight.
+	 */
+	ap_power_ev_init_callback(&cb, board_backlight_handler,
+				  AP_POWER_RESUME | AP_POWER_SUSPEND);
+	ap_power_ev_add_callback(&cb);
+
+	if (get_board_id() != 1)
+		return;
+
+	/*
+	 * Note, use gpio_pin_configure() instead of gpio_pin_configure_dt()
+	 * because gpio_pin_configure_dt() only sets additional flags, and
+	 * cannot clear flags.
+	 */
+	flags &= ~GPIO_INPUT;
+	flags |= GPIO_OUTPUT_LOW;
+	gpio_pin_configure(ec_kb_bl_en->port, ec_kb_bl_en->pin, flags);
+}
+DECLARE_HOOK(HOOK_INIT, set_board_id_1_gpios, HOOK_PRIO_FIRST);
diff --git a/zephyr/program/brya/keyboard.dts b/zephyr/program/brya/keyboard.dts
new file mode 100644
index 0000000000..91fad2db92
--- /dev/null
+++ b/zephyr/program/brya/keyboard.dts
@@ -0,0 +1,47 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	kblight {
+		compatible = "cros-ec,kblight-pwm";
+		pwms = <&pwm3 0 PWM_HZ(2400) PWM_POLARITY_NORMAL>;
+	};
+};
+
+&pwm3 {
+	status = "okay";
+	pinctrl-0 = <&pwm3_gp80>;
+	pinctrl-names = "default";
+};
+
+&cros_kb_raw {
+	status = "okay";
+	/* No KSO2 (it's inverted and implemented by GPIO) */
+	pinctrl-0 = <
+		&ksi0_gp31
+		&ksi1_gp30
+		&ksi2_gp27
+		&ksi3_gp26
+		&ksi4_gp25
+		&ksi5_gp24
+		&ksi6_gp23
+		&ksi7_gp22
+		&kso00_gp21
+		&kso01_gp20
+		&kso03_gp16
+		&kso04_gp15
+		&kso05_gp14
+		&kso06_gp13
+		&kso07_gp12
+		&kso08_gp11
+		&kso09_gp10
+		&kso10_gp07
+		&kso11_gp06
+		&kso12_gp05
+		&kso13_gp04
+		&kso14_gp82
+	>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/brya/motionsense.dts b/zephyr/program/brya/motionsense.dts
new file mode 100644
index 0000000000..08994e30cc
--- /dev/null
+++ b/zephyr/program/brya/motionsense.dts
@@ -0,0 +1,257 @@
+/*
+ * Copyright 2022 The ChromiumOS Authors
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <dt-bindings/motionsense/utils.h>
+
+
+/ {
+	aliases {
+		/*
+		 * motion sense's <>_INT_EVENT is handled
+		 * by alias. Using the alias, each driver creates
+		 * its own <>_INT_EVENT.
+		 */
+		lsm6dso-int = &base_accel;
+		lis2dw12-int = &lid_accel;
+		tcs3400-int = &als_clear;
+	};
+
+	/*
+	 * Declare mutexes used by sensor drivers.
+	 * A mutex node is used to create an instance of mutex_t.
+	 * A mutex node is referenced by a sensor node if the
+	 * corresponding sensor driver needs to use the
+	 * instance of the mutex.
+	 */
+	motionsense-mutex {
+		compatible = "cros-ec,motionsense-mutex";
+		mutex_lis2dw12: lis2dw12-mutex {
+		};
+
+		mutex_lsm6dso: lsm6dso-mutex {
+		};
+	};
+
+	/* Rotation matrix used by drivers. */
+	motionsense-rotation-ref {
+		compatible = "cros-ec,motionsense-rotation-ref";
+		lid_rot_ref: lid-rotation-ref {
+			mat33 = <0 1 0
+				 1 0 0
+				 0 0 (-1)>;
+		};
+		base_rot_ref: base-rotation-ref {
+			mat33 = <1 0 0
+				 0 (-1) 0
+				 0 0 (-1)>;
+		};
+	};
+
+	/*
+	 * Driver specific data. A driver-specific data can be shared with
+	 * different motion sensors while they are using the same driver.
+	 *
+	 * If a node's compatible starts with "cros-ec,accelgyro-", it is for
+	 * a common structure defined in accelgyro.h.
+	 * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for
+	 * "struct als_drv_data_t" in accelgyro.h
+	 */
+	motionsense-sensor-data {
+		lis2dw12_data: lis2dw12-drv-data {
+			compatible = "cros-ec,drvdata-lis2dw12";
+			status = "okay";
+		};
+
+		lsm6dso_accel_data: lsm6dso-accel-drv-data {
+			compatible = "cros-ec,drvdata-lsm6dso";
+			status = "okay";
+		};
+
+		lsm6dso_gyro_data: lsm6dso-gyro-drv-data {
+			compatible = "cros-ec,drvdata-lsm6dso";
+			status = "okay";
+		};
+
+		tcs_clear_data: tcs3400-clear-drv-data {
+			compatible = "cros-ec,drvdata-tcs3400-clear";
+			status = "okay";
+
+			als-drv-data {
+				compatible = "cros-ec,accelgyro-als-drv-data";
+				als-cal {
+					scale = <1>;
+					uscale = <0>;
+					offset = <0>;
+					als-channel-scale {
+					compatible =
+					"cros-ec,accelgyro-als-channel-scale";
+						k-channel-scale = <1>;
+						cover-scale = <1>;
+					};
+				};
+			};
+		};
+
+		tcs_rgb_data: tcs3400-rgb-drv-data {
+			compatible = "cros-ec,drvdata-tcs3400-rgb";
+			status = "okay";
+
+			/* node for rgb_calibration_t defined in accelgyro.h */
+			rgb_calibration {
+				compatible =
+					"cros-ec,accelgyro-rgb-calibration";
+
+				irt = <1>;
+
+				rgb-cal-x {
+					offset = <0>;
+					coeff = <0 0 0 1>;
+					als-channel-scale {
+					compatible =
+					"cros-ec,accelgyro-als-channel-scale";
+						k-channel-scale = <1>;
+						cover-scale = <1>;
+					};
+				};
+				rgb-cal-y {
+					offset = <0>;
+					coeff = <0 0 0 1>;
+					als-channel-scale {
+					compatible =
+					"cros-ec,accelgyro-als-channel-scale";
+						k-channel-scale = <1>;
+						cover-scale = <1>;
+					};
+				};
+				rgb-cal-z {
+					offset = <0>;
+					coeff = <0 0 0 1>;
+					als-channel-scale {
+					compatible =
+					"cros-ec,accelgyro-als-channel-scale";
+						k-channel-scale = <1>;
+						cover-scale = <1>;
+					};
+				};
+			};
+		};
+	};
+
+	/*
+	 * List of motion sensors that creates motion_sensors array.
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
+	 * motion sensor IDs for lid angle calculation.
+	 */
+	motionsense-sensor {
+		lid_accel: lid-accel {
+			compatible = "cros-ec,lis2dw12";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&mutex_lis2dw12>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&lid_rot_ref>;
+			default-range = <2>;
+			drv-data = <&lis2dw12_data>;
+			i2c-spi-addr-flags = "LIS2DWL_ADDR0_FLAGS";
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_accel: base-accel {
+			compatible = "cros-ec,lsm6dso-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&mutex_lsm6dso>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			default-range = <4>;
+			drv-data = <&lsm6dso_accel_data>;
+			i2c-spi-addr-flags = "LSM6DSO_ADDR0_FLAGS";
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(13000 | ROUND_UP_FLAG)>;
+					ec-rate = <(100 * USEC_PER_MSEC)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+					ec-rate = <(100 * USEC_PER_MSEC)>;
+				};
+			};
+		};
+
+		base-gyro {
+			compatible = "cros-ec,lsm6dso-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&mutex_lsm6dso>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			default-range = <(1000 | ROUND_UP_FLAG)>; /* dps */
+			drv-data = <&lsm6dso_gyro_data>;
+			i2c-spi-addr-flags = "LSM6DSO_ADDR0_FLAGS";
+		};
+
+		als_clear: base-als-clear {
+			compatible = "cros-ec,tcs3400-clear";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_CAMERA";
+			port = <&i2c_sensor>;
+			default-range = <0x10000>;
+			drv-data = <&tcs_clear_data>;
+			i2c-spi-addr-flags = "TCS3400_I2C_ADDR_FLAGS";
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					/* Run ALS sensor in S0 */
+					odr = <1000>;
+				};
+			};
+		};
+
+		base-als-rgb {
+			compatible = "cros-ec,tcs3400-rgb";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_CAMERA";
+			default-range = <0x10000>; /* scale = 1x, uscale = 0 */
+			drv-data = <&tcs_rgb_data>;
+		};
+	};
+
+	motionsense-sensor-info {
+		compatible = "cros-ec,motionsense-sensor-info";
+
+		/* list of entries for motion_als_sensors */
+		als-sensors = <&als_clear>;
+		/*
+		 * list of GPIO interrupts that have to
+		 * be enabled at initial stage
+		 */
+		sensor-irqs = <&int_imu &int_als_rgb &int_accel>;
+		/* list of sensors in force mode */
+		accel-force-mode-sensors = <&lid_accel &als_clear>;
+	};
+};
diff --git a/zephyr/program/brya/prj.conf b/zephyr/program/brya/prj.conf
new file mode 100644
index 0000000000..8af5785112
--- /dev/null
+++ b/zephyr/program/brya/prj.conf
@@ -0,0 +1,164 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_CROS_EC=y
+CONFIG_PLATFORM_EC=y
+CONFIG_PLATFORM_EC_POWER_BUTTON=y
+CONFIG_PLATFORM_EC_LID_SWITCH=y
+CONFIG_PLATFORM_EC_SWITCH=y
+CONFIG_LTO=y
+CONFIG_CROS_SYSTEM_NPCX=y
+CONFIG_PLATFORM_EC_VBOOT_EFS2=y
+CONFIG_PLATFORM_EC_VBOOT_HASH=y
+CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_SYSINFO=y
+
+CONFIG_PLATFORM_EC_ADC_CHANNELS_RUNTIME_CONFIG=y
+
+CONFIG_KERNEL_SHELL=y
+
+# SoC configuration
+CONFIG_AP=y
+CONFIG_AP_X86_INTEL_ADL=y
+CONFIG_FPU=y
+CONFIG_ARM_MPU=y
+
+# CBI
+CONFIG_EEPROM=y
+CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=y
+
+# eSPI
+CONFIG_ESPI=y
+CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S4=y
+CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S5=y
+CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US=150
+
+# Power Sequencing
+CONFIG_PLATFORM_EC_POWERSEQ=y
+CONFIG_PLATFORM_EC_POWERSEQ_RTC_RESET=y
+CONFIG_PLATFORM_EC_POWERSEQ_S0IX=y
+CONFIG_PLATFORM_EC_POWERSEQ_S4=y
+CONFIG_PLATFORM_EC_POWER_SLEEP_FAILURE_DETECTION=y
+CONFIG_PLATFORM_EC_THROTTLE_AP=y
+
+# Host command
+CONFIG_PLATFORM_EC_HOSTCMD=y
+CONFIG_PLATFORM_EC_HOSTCMD_AP_RESET=y
+
+# Console command
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_I2C_SPEED=y
+
+# Sensors
+CONFIG_PLATFORM_EC_ACCEL_FIFO=y
+CONFIG_PLATFORM_EC_ALS=y
+CONFIG_PLATFORM_EC_DYNAMIC_MOTION_SENSOR_COUNT=y
+CONFIG_PLATFORM_EC_GMR_TABLET_MODE=y
+CONFIG_PLATFORM_EC_LID_ANGLE=y
+CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y
+CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=y
+CONFIG_PLATFORM_EC_TABLET_MODE=y
+CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=y
+
+# Sensor Drivers
+CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSO=y
+CONFIG_PLATFORM_EC_ACCEL_LIS2DW12=y
+CONFIG_PLATFORM_EC_ALS_TCS3400=y
+
+# Temperature sensors
+CONFIG_PLATFORM_EC_TEMP_SENSOR_POWER=y
+
+# MKBP event
+CONFIG_PLATFORM_EC_MKBP_EVENT=y
+CONFIG_PLATFORM_EC_MKBP_INPUT_DEVICES=y
+CONFIG_PLATFORM_EC_MKBP_USE_GPIO_AND_HOST_EVENT=y
+
+# PMIC
+CONFIG_PLATFORM_EC_PMIC=y
+
+# Keyboard
+CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_8042=y
+CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED=y
+CONFIG_PLATFORM_EC_KEYBOARD_KEYPAD=y
+CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI3=y
+CONFIG_PLATFORM_EC_VOLUME_BUTTONS=y
+CONFIG_PLATFORM_EC_CMD_BUTTON=n
+
+CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API=y
+
+# Battery
+CONFIG_PLATFORM_EC_BATTERY_PRESENT_CUSTOM=y
+CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y
+CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y
+CONFIG_PLATFORM_EC_BATTERY_HW_PRESENT_CUSTOM=y
+CONFIG_PLATFORM_EC_BATTERY_REVIVE_DISCONNECT=y
+
+# USB-C and charging
+CONFIG_PLATFORM_EC_CHARGER_BQ25720=y
+CONFIG_PLATFORM_EC_CHARGER_BQ25720_VSYS_TH2_CUSTOM=y
+CONFIG_PLATFORM_EC_CHARGER_BQ25720_VSYS_TH2_DV=70
+CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y
+CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC_CHARGER=y
+CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON=3
+CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC=1
+CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT=15000
+CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON=15001
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=10
+CONFIG_PLATFORM_EC_CHARGE_RAMP_SW=y
+CONFIG_PLATFORM_EC_USB_PID=0x504F
+CONFIG_PLATFORM_EC_USB_DRP_ACC_TRYSRC=y
+CONFIG_PLATFORM_EC_USB_MUX_RUNTIME_CONFIG=n
+CONFIG_PLATFORM_EC_USB_MUX_TASK=y
+CONFIG_PLATFORM_EC_USB_PD_DEBUG_FIXED_LEVEL=y
+CONFIG_PLATFORM_EC_USB_PD_DEBUG_LEVEL=2
+CONFIG_PLATFORM_EC_USB_PD_ALT_MODE_UFP=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_CHARGER=y
+CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y
+CONFIG_PLATFORM_EC_USB_PD_PPC=y
+CONFIG_PLATFORM_EC_USB_PD_REV30=y
+CONFIG_PLATFORM_EC_USB_PD_USB32_DRD=y
+CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=y
+CONFIG_PLATFORM_EC_USB_PD_USB4=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8815=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_RT1715=n
+CONFIG_PLATFORM_EC_USB_PD_TCPM_TUSB422=n
+CONFIG_PLATFORM_EC_USB_PD_TCPM_MUX=y
+CONFIG_PLATFORM_EC_USBC_PPC_DEDICATED_INT=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_PPC_DUMP=n
+CONFIG_PLATFORM_EC_CONSOLE_CMD_TCPC_DUMP=n
+CONFIG_PLATFORM_EC_USB_PD_TCPC_RUNTIME_CONFIG=y
+CONFIG_PLATFORM_EC_USB_PD_REQUIRE_AP_MODE_ENTRY=y
+CONFIG_PLATFORM_EC_USB_PD_INT_SHARED=y
+CONFIG_PLATFORM_EC_USB_PD_PORT_0_SHARED=y
+CONFIG_PLATFORM_EC_USB_PD_PORT_2_SHARED=y
+
+CONFIG_SYSCON=y
+
+# LED
+CONFIG_PLATFORM_EC_LED_COMMON=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_LEDTEST=n
+CONFIG_PLATFORM_EC_LED_PWM_NEAR_FULL_COLOR=4
+CONFIG_PLATFORM_EC_LED_PWM_SOC_ON_COLOR=4
+CONFIG_PLATFORM_EC_LED_PWM_SOC_SUSPEND_COLOR=4
+CONFIG_PLATFORM_EC_LED_PWM_LOW_BATT_COLOR=5
+
+# TODO(b/188605676): bring these features up
+CONFIG_PLATFORM_EC_BOARD_VERSION_GPIO=n
+
+# Power Sequencing
+CONFIG_PLATFORM_EC_POWERSEQ=y
+CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n
+CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540=y
+CONFIG_PLATFORM_EC_POWERSEQ_RTC_RESET=n
+CONFIG_PLATFORM_EC_POWERSEQ_S0IX=y
+CONFIG_PLATFORM_EC_POWER_SLEEP_FAILURE_DETECTION=y
+# Treat 2nd reset from H1 as Power-On
+CONFIG_PLATFORM_EC_BOARD_RESET_AFTER_POWER_ON=y
+CONFIG_PLATFORM_EC_THROTTLE_AP=y
+
+# RTC
+CONFIG_PLATFORM_EC_RTC=y
diff --git a/zephyr/program/brya/prj_brya.conf b/zephyr/program/brya/prj_brya.conf
new file mode 100644
index 0000000000..5aaf86a8c9
--- /dev/null
+++ b/zephyr/program/brya/prj_brya.conf
@@ -0,0 +1,6 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# BRYA-NPCX9 reference-board-specific Kconfig settings.
+CONFIG_BOARD_BRYA=y
diff --git a/zephyr/program/brya/pwm_leds.dts b/zephyr/program/brya/pwm_leds.dts
new file mode 100644
index 0000000000..4321b4bd34
--- /dev/null
+++ b/zephyr/program/brya/pwm_leds.dts
@@ -0,0 +1,79 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	pwmleds {
+		compatible = "pwm-leds";
+		pwm_led0: pwm_led_0 {
+			pwms = <&pwm2 0 PWM_HZ(4800) PWM_POLARITY_INVERTED
+				&pwm0 0 PWM_HZ(4800) PWM_POLARITY_INVERTED>;
+		};
+		pwm_led1: pwm_led_1 {
+			pwms = <&pwm1 0 PWM_HZ(4800) PWM_POLARITY_INVERTED
+				&pwm7 0 PWM_HZ(4800) PWM_POLARITY_INVERTED>;
+		};
+	};
+
+	cros-pwmleds {
+		compatible = "cros-ec,pwm-leds";
+
+		leds = <&pwm_led0 &pwm_led1>;
+
+			      /*<amber   white>*/
+		color-map-red    = <0    0>;
+		color-map-green  = <0    0>;
+		color-map-blue   = <0    0>;
+		color-map-yellow = <0    0>;
+		color-map-white  = <0   50>;
+		color-map-amber  = <50   0>;
+
+		brightness-range = <0 0 0 0 100 100>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pwm_led_0@0 {
+			reg = <0>;
+			ec-led-name = "EC_LED_ID_LEFT_LED";
+		};
+
+		pwm_led_1@1 {
+			reg = <1>;
+			ec-led-name = "EC_LED_ID_RIGHT_LED";
+		};
+	};
+};
+
+/* LED2 */
+&pwm0 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm0_gpc3>;
+	pinctrl-names = "default";
+};
+
+/* LED3 */
+&pwm1 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm1_gpc2>;
+	pinctrl-names = "default";
+};
+
+/* LED1 */
+&pwm2 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm2_gpc4>;
+	pinctrl-names = "default";
+};
+
+/* LED4 */
+&pwm7 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm7_gp60>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/brya/temp_sensors.dts b/zephyr/program/brya/temp_sensors.dts
new file mode 100644
index 0000000000..ae436a2c6b
--- /dev/null
+++ b/zephyr/program/brya/temp_sensors.dts
@@ -0,0 +1,75 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <cros/thermistor/thermistor.dtsi>
+
+/ {
+	temp_ddr_soc: ddr_soc {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_30K9_47K_4050B>;
+		adc = <&adc_ddr_soc>;
+	};
+
+	temp_ambient: ambient {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_30K9_47K_4050B>;
+		adc = <&adc_ambient>;
+	};
+
+	temp_charger: charger {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_30K9_47K_4050B>;
+		adc = <&adc_charger>;
+	};
+
+	temp_wwan: wwan {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_30K9_47K_4050B>;
+		adc = <&adc_wwan>;
+	};
+
+	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
+		ddr_soc {
+			temp_fan_off = <35>;
+			temp_fan_max = <60>;
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			sensor = <&temp_ddr_soc>;
+		};
+
+		ambient {
+			temp_fan_off = <35>;
+			temp_fan_max = <60>;
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			sensor = <&temp_ambient>;
+		};
+
+		charger {
+			temp_fan_off = <35>;
+			temp_fan_max = <65>;
+			temp_host_high = <105>;
+			temp_host_halt = <120>;
+			temp_host_release_high = <90>;
+			sensor = <&temp_charger>;
+		};
+
+		wwan {
+			temp_fan_off = <35>;
+			temp_fan_max = <60>;
+			temp_host_high = <130>;
+			temp_host_halt = <130>;
+			temp_host_release_high = <100>;
+			sensor = <&temp_wwan>;
+		};
+	};
+};
+
+&thermistor_3V3_30K9_47K_4050B {
+	status = "okay";
+};
diff --git a/zephyr/program/brya/usbc.dts b/zephyr/program/brya/usbc.dts
new file mode 100644
index 0000000000..1be9ac94ac
--- /dev/null
+++ b/zephyr/program/brya/usbc.dts
@@ -0,0 +1,69 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+			bc12 = <&bc12_port0>;
+			tcpc = <&tcpc_port0>;
+			chg = <&charger>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_c0_bb_retimer
+					     &virtual_mux_c0>;
+			};
+			ppc = <&ppc_port0>;
+		};
+		port0-muxes {
+			virtual_mux_c0: virtual-mux-c0 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+
+		port1@1 {
+			compatible = "named-usbc-port";
+			reg = <1>;
+			bc12 = <&bc12_port1>;
+			tcpc = <&tcpc_port1>;
+			usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_c1 &tcpci_mux_c1>;
+			};
+			ppc = <&ppc_port1>;
+		};
+		port1-muxes {
+			tcpci_mux_c1: tcpci-mux-c1 {
+				compatible = "cros-ec,usbc-mux-tcpci";
+				hpd-update = "ps8xxx_tcpc_update_hpd_status";
+			};
+			virtual_mux_c1: virtual-mux-c1 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+
+		port2@2 {
+			compatible = "named-usbc-port";
+			reg = <2>;
+			bc12 = <&bc12_port2>;
+			tcpc = <&tcpc_port2>;
+			usb-mux-chain-2 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_c2_bb_retimer
+					     &virtual_mux_c2>;
+			};
+			ppc = <&ppc_port2>;
+		};
+		port2-muxes {
+			virtual_mux_c2: virtual-mux-c2 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+	};
+};
diff --git a/zephyr/program/corsola/BUILD.py b/zephyr/program/corsola/BUILD.py
new file mode 100644
index 0000000000..35ebb01b6f
--- /dev/null
+++ b/zephyr/program/corsola/BUILD.py
@@ -0,0 +1,55 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Define zmake projects for corsola."""
+
+# Default chip is it81202bx, some variants will use NPCX9X.
+
+
+def register_corsola_project(
+    project_name,
+    chip="it81202bx",
+):
+    """Register a variant of corsola."""
+    register_func = register_binman_project
+    if chip.startswith("npcx"):
+        register_func = register_npcx_project
+
+    chip_kconfig = {"it81202bx": "ite", "npcx9m3f": "npcx"}[chip]
+
+    register_func(
+        project_name=project_name,
+        zephyr_board=chip,
+        dts_overlays=[here / project_name / "project.overlay"],
+        kconfig_files=[
+            here / "program.conf",
+            here / f"{chip_kconfig}_program.conf",
+            here / project_name / "project.conf",
+        ],
+        inherited_from=["corsola"],
+    )
+
+
+register_corsola_project("krabby")
+
+register_corsola_project(
+    project_name="kingler",
+    chip="npcx9m3f",
+)
+
+register_corsola_project(
+    project_name="steelix",
+    chip="npcx9m3f",
+)
+
+register_corsola_project("starmie")
+
+register_corsola_project("tentacruel")
+
+register_corsola_project("magikarp")
+
+register_corsola_project(
+    project_name="voltorb",
+    chip="npcx9m3f",
+)
diff --git a/zephyr/program/corsola/CMakeLists.txt b/zephyr/program/corsola/CMakeLists.txt
new file mode 100644
index 0000000000..e45e1e954d
--- /dev/null
+++ b/zephyr/program/corsola/CMakeLists.txt
@@ -0,0 +1,44 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+
+cros_ec_library_include_directories(include)
+
+# Include selected EC source from the baseboard
+zephyr_library_sources(
+	"src/board.c"
+	"src/board_chipset.c"
+	"src/hibernate.c"
+)
+
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/usbc.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/usb_pd_policy.c")
+zephyr_library_sources_ifdef(CONFIG_VARIANT_CORSOLA_DB_DETECTION
+			     "src/variant_db_detection.c")
+
+if(DEFINED CONFIG_BOARD_KRABBY)
+	project(krabby)
+	add_subdirectory(krabby)
+elseif(DEFINED CONFIG_BOARD_KINGLER)
+	project(kingler)
+	add_subdirectory(kingler)
+elseif(DEFINED CONFIG_BOARD_STARMIE)
+	project(starmie)
+	add_subdirectory(starmie)
+elseif(DEFINED CONFIG_BOARD_STEELIX)
+	project(steelix)
+	add_subdirectory(steelix)
+elseif(DEFINED CONFIG_BOARD_TENTACRUEL)
+	project(tentacruel)
+	add_subdirectory(tentacruel)
+elseif(DEFINED CONFIG_BOARD_MAGIKARP)
+	project(magikarp)
+	add_subdirectory(magikarp)
+elseif(DEFINED CONFIG_BOARD_VOLTORB)
+	project(voltorb)
+	add_subdirectory(voltorb)
+endif()
diff --git a/zephyr/program/corsola/Kconfig b/zephyr/program/corsola/Kconfig
new file mode 100644
index 0000000000..26e000aedf
--- /dev/null
+++ b/zephyr/program/corsola/Kconfig
@@ -0,0 +1,62 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config BOARD_KRABBY
+	bool "Google Krabby Board"
+	help
+	  Build Google Krabby reference board. Krabby has MediaTek MT8186 SoC
+	  with ITE it81202-bx EC.
+
+config BOARD_KINGLER
+	bool "Google Kingler Board"
+	help
+	  Build Google Kingler reference board. Krabby has MediaTek MT8186 SoC
+	  with NPCX993FA0BX EC.
+
+config BOARD_STARMIE
+	bool "Google Starmie Board"
+	help
+	  Build Google Starmie variant board. Starmie is a variant of Krabby
+	  and has MediaTek MT8186 SoC with ITE it81202-bx EC
+
+config BOARD_STEELIX
+	bool "Google Steelix Board"
+	help
+	  Build Google Steelix variant board. Steelix is a variant of Kingler
+	  and has MediaTek MT8186 SoC with NPCX993FA0BX EC.
+
+config BOARD_TENTACRUEL
+	bool "Google Tentacruel Board"
+	help
+	  Build Google Tentacruel variant board. Tentacruel is a variant of Krabby
+	  and has MediaTek MT8186 SoC with ITE it81202-bx EC.
+
+config BOARD_MAGIKARP
+	bool "Google Magikarp Board"
+	help
+	  Build Google Magikarp variant board. Magikarp is a variant of Krabby
+	  and has MediaTek MT8186 SoC with ITE it81202-bx EC.
+
+config BOARD_VOLTORB
+	bool "Google Voltorb Board"
+	help
+	  Build Google Voltorb variant board. Voltorb is a variant of Kingler
+	  and has MediaTek MT8186/MT8186T SoC with NPCX993FA0BX EC.
+
+config VARIANT_CORSOLA_DB_DETECTION
+	bool "Corsola Platform Runtime Daughter Board Detection"
+	depends on PLATFORM_EC_USB_PD_TCPC_RUNTIME_CONFIG
+	depends on PLATFORM_EC_USB_MUX_RUNTIME_CONFIG
+	help
+	  Daughter board detection for Type-C subboard or HDMI subboard. This
+          includes pin configuration and driver loading.
+	default y
+
+config CORSOLA_HIBERNATE_PRE_OFF_5V
+	bool "Corsola Platform Hibernate Power Sequence Selection"
+	help
+	  Set PP5000_Z2 to deactivate before executing normal corsola hibernate.
+	default n
+
+source "Kconfig.zephyr"
diff --git a/zephyr/program/corsola/common.dtsi b/zephyr/program/corsola/common.dtsi
new file mode 100644
index 0000000000..1f66474af5
--- /dev/null
+++ b/zephyr/program/corsola/common.dtsi
@@ -0,0 +1,25 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/wake_mask_event_defines.h>
+
+/ {
+	ec-mkbp-host-event-wakeup-mask {
+		compatible = "cros-ec,mkbp-host-event-wakeup-mask";
+		wakeup-mask = <(
+			HOST_EVENT_AC_CONNECTED |
+			HOST_EVENT_AC_DISCONNECTED |
+			HOST_EVENT_LID_OPEN |
+			HOST_EVENT_POWER_BUTTON |
+			HOST_EVENT_HANG_DETECT |
+			HOST_EVENT_MODE_CHANGE)>;
+	};
+
+	ec-mkbp-event-wakeup-mask {
+		compatible = "cros-ec,mkbp-event-wakeup-mask";
+		wakeup-mask = <(MKBP_EVENT_KEY_MATRIX |
+				MKBP_EVENT_HOST_EVENT)>;
+	};
+};
diff --git a/zephyr/program/corsola/include/baseboard_usbc_config.h b/zephyr/program/corsola/include/baseboard_usbc_config.h
new file mode 100644
index 0000000000..5d3195ab7f
--- /dev/null
+++ b/zephyr/program/corsola/include/baseboard_usbc_config.h
@@ -0,0 +1,48 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Corsola daughter board detection */
+
+#ifndef __CROS_EC_BASEBOARD_USBC_CONFIG_H
+#define __CROS_EC_BASEBOARD_USBC_CONFIG_H
+
+#include "gpio.h"
+
+#include <zephyr/sys/util_macro.h>
+
+#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_RT1718S
+#define GPIO_EN_USB_C1_SINK RT1718S_GPIO1
+#define GPIO_EN_USB_C1_SOURCE RT1718S_GPIO2
+#define GPIO_EN_USB_C1_FRS RT1718S_GPIO3
+#endif
+
+void ppc_interrupt(enum gpio_signal signal);
+void ccd_interrupt(enum gpio_signal signal);
+void hdmi_hpd_interrupt(enum gpio_signal signal);
+void ps185_hdmi_hpd_mux_set(void);
+int corsola_is_dp_muxable(int port);
+int ps8743_eq_c1_setting(void);
+
+/* USB-A ports */
+enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_COUNT };
+
+/* USB-C ports */
+#define USBC_PORT_N(i, _) USBC_PORT_C##i = i
+enum usbc_port {
+	LISTIFY(CONFIG_USB_PD_PORT_MAX_COUNT, USBC_PORT_N, (, )),
+	USBC_PORT_COUNT
+};
+
+/**
+ * Is the port fine to be muxed its DisplayPort lines?
+ *
+ * Only one port can be muxed to DisplayPort at a time.
+ *
+ * @param port	Port number of TCPC.
+ * @return	1 is fine; 0 is bad as other port is already muxed;
+ */
+int corsola_is_dp_muxable(int port);
+
+#endif /* __CROS_EC_BASEBOARD_USBC_CONFIG_H */
diff --git a/zephyr/program/corsola/include/variant_db_detection.h b/zephyr/program/corsola/include/variant_db_detection.h
new file mode 100644
index 0000000000..fb468126ef
--- /dev/null
+++ b/zephyr/program/corsola/include/variant_db_detection.h
@@ -0,0 +1,42 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Corsola daughter board detection */
+
+#ifndef __CROS_EC_CORSOLA_DB_DETECTION_H
+#define __CROS_EC_CORSOLA_DB_DETECTION_H
+
+#include <stdint.h>
+
+enum corsola_db_type {
+	CORSOLA_DB_UNINIT = -1,
+	/* CORSOLA_DB_NO_DETECTION means there is no detection involved in. */
+	CORSOLA_DB_NO_DETECTION,
+	/* CORSOLA_DB_NONE means there is no DB in the design. */
+	CORSOLA_DB_NONE,
+	CORSOLA_DB_TYPEC,
+	CORSOLA_DB_HDMI,
+	CORSOLA_DB_COUNT,
+};
+
+/*
+ * Get the connected daughterboard type.
+ *
+ * @return		The daughterboard type.
+ */
+#ifdef CONFIG_VARIANT_CORSOLA_DB_DETECTION
+enum corsola_db_type corsola_get_db_type(void);
+#elif !defined(CONFIG_TEST)
+inline enum corsola_db_type corsola_get_db_type(void)
+{
+	return CORSOLA_DB_NO_DETECTION;
+}
+#endif
+
+/* return the adjusted port count for board overridden usbc/charger functions.
+ */
+uint8_t board_get_adjusted_usb_pd_port_count(void);
+
+#endif /* __CROS_EC_CORSOLA_DB_DETECTION_H */
diff --git a/zephyr/program/corsola/ite_adc.dtsi b/zephyr/program/corsola/ite_adc.dtsi
new file mode 100644
index 0000000000..be65e9eea7
--- /dev/null
+++ b/zephyr/program/corsola/ite_adc.dtsi
@@ -0,0 +1,38 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		adc_vbus_c0 {
+			enum-name = "ADC_VBUS_C0";
+			io-channels = <&adc0 0>;
+			mul = <10>;
+		};
+		adc_board_id0 {
+			enum-name = "ADC_BOARD_ID_0";
+			io-channels = <&adc0 1>;
+		};
+		adc_board_id1 {
+			enum-name = "ADC_BOARD_ID_1";
+			io-channels = <&adc0 2>;
+		};
+		adc_vbus_c1 {
+			enum-name = "ADC_VBUS_C1";
+			io-channels = <&adc0 7>;
+			mul = <10>;
+		};
+	};
+};
+
+&adc0 {
+	status = "okay";
+	pinctrl-0 = <&adc0_ch0_gpi0_default
+		     &adc0_ch1_gpi1_default
+		     &adc0_ch2_gpi2_default
+		     &adc0_ch7_gpi7_default>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/corsola/ite_gpio.dtsi b/zephyr/program/corsola/ite_gpio.dtsi
new file mode 100644
index 0000000000..c478852b3b
--- /dev/null
+++ b/zephyr/program/corsola/ite_gpio.dtsi
@@ -0,0 +1,231 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/gpio_defines.h>
+
+/ {
+	aliases {
+		gpio-cbi-wp = &gpio_ec_cbi_wp;
+		gpio-wp = &ec_flash_wp_odl;
+		gpio-en-hdmi-pwr = &gpio_ec_x_gpio1;
+		gpio-usb-c1-frs-en = &gpio_ec_x_gpio1;
+		gpio-usb-c1-ppc-int-odl = &gpio_x_ec_gpio2;
+		gpio-ps185-ec-dp-hpd = &gpio_x_ec_gpio2;
+		gpio-usb-c1-dp-in-hpd = &gpio_ec_x_gpio3;
+		gpio-ps185-pwrdn-odl = &gpio_ec_x_gpio3;
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		power_button_l: power_button_l {
+			gpios = <&gpioe 4 GPIO_INPUT>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		lid_open: lid_open {
+			gpios = <&gpioe 2 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+		tablet_mode_l: tablet_mode_l {
+			gpios = <&gpioj 7 GPIO_INPUT>;
+			enum-name = "GPIO_TABLET_MODE_L";
+		};
+		ap_ec_warm_rst_req: ap_ec_warm_rst_req {
+			gpios = <&gpiod 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8 |
+					   GPIO_ACTIVE_HIGH)>;
+			enum-name = "GPIO_AP_EC_WARM_RST_REQ";
+		};
+		ap_in_sleep_l: ap_in_sleep_l {
+			gpios = <&gpiob 6 (GPIO_INPUT | GPIO_VOLTAGE_1P8 |
+					   GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_AP_IN_SLEEP_L";
+		};
+		base_imu_int_l: base_imu_int_l {
+			gpios = <&gpiom 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		lid_accel_int_l: lid_accel_int_l {
+			gpios = <&gpiom 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		volume_down_l: volume_down_l {
+			gpios = <&gpiod 5 GPIO_INPUT>;
+			enum-name = "GPIO_VOLUME_DOWN_L";
+		};
+		volume_up_l: volume_up_l {
+			gpios = <&gpiod 6 GPIO_INPUT>;
+			enum-name = "GPIO_VOLUME_UP_L";
+		};
+		gpio_ap_xhci_init_done: ap_xhci_init_done {
+			gpios = <&gpioj 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		ac_present: ac_present {
+			gpios = <&gpioe 5 GPIO_INPUT>;
+			enum-name = "GPIO_AC_PRESENT";
+		};
+		gpio_ec_cbi_wp: ec_cbi_wp {
+			gpios = <&gpioc 3 GPIO_OUTPUT_LOW>;
+		};
+		ec_flash_wp_odl: ec_flash_wp_odl {
+			gpios = <&gpioi 4 (GPIO_INPUT | GPIO_VOLTAGE_1P8 |
+					   GPIO_ACTIVE_LOW)>;
+		};
+		spi0_cs: spi0_cs {
+			gpios = <&gpiom 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		gpio_x_ec_gpio2: x_ec_gpio2 {
+			gpios = <&gpiob 2 GPIO_INPUT>;
+		};
+		usb_c0_ppc_bc12_int_odl: usb_c0_ppc_bc12_int_odl {
+			gpios = <&gpiod 1 GPIO_INPUT>;
+		};
+		usb_c1_bc12_charger_int_odl: usb_c1_bc12_charger_int_odl {
+			gpios = <&gpioj 4 GPIO_INPUT>;
+		};
+		ec_pmic_en_odl: ec_pmic_en_odl {
+			gpios = <&gpiod 0 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>;
+			enum-name = "GPIO_EC_PMIC_EN_ODL";
+		};
+		en_pp5000_z2: en_pp5000_z2 {
+			gpios = <&gpioc 6 GPIO_OUTPUT_HIGH>;
+		};
+		gpio_en_ulp: en_ulp {
+			gpios = <&gpioe 3 GPIO_OUTPUT_LOW>;
+		};
+		sys_rst_odl: sys_rst_odl {
+			gpios = <&gpiog 1 GPIO_ODR_LOW>;
+			enum-name = "GPIO_SYS_RST_ODL";
+		};
+		gpio_ec_bl_en_od: ec_bl_en_od {
+			gpios = <&gpiob 5 (GPIO_ODR_LOW | GPIO_VOLTAGE_1P8)>;
+		};
+		ap_sysrst_odl_r: ap_ec_sysrst_odl {
+			gpios = <&gpioj 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8 |
+					   GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_AP_EC_SYSRST_ODL";
+		};
+		ap_ec_wdtrst_l: ap_ec_wdtrst_l {
+			gpios = <&gpioc 7 (GPIO_INPUT | GPIO_VOLTAGE_1P8 |
+					   GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_AP_EC_WDTRST_L";
+		};
+		ec_int_l: ec_int_l {
+			gpios = <&gpioe 6 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>;
+			enum-name = "GPIO_EC_INT_L";
+		};
+		dp_aux_path_sel: dp_aux_path_sel {
+			gpios = <&gpiog 0 GPIO_OUTPUT_HIGH>;
+		};
+		ec_ap_dp_hpd_odl: ec_ap_dp_hpd_odl {
+			gpios = <&gpioj 0 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>;
+		};
+		en_pp5000_usb_a0_vbus: en_pp5000_usb_a0_vbus {
+			gpios = <&gpiob 7 GPIO_OUTPUT_LOW>;
+		};
+		usb_c0_ppc_frsinfo: usb_c0_ppc_frsinfo {
+			gpios = <&gpiof 0 GPIO_INPUT>;
+		};
+		ec_batt_pres_odl: ec_batt_pres_odl {
+			gpios = <&gpioc 0 GPIO_INPUT>;
+			enum-name = "GPIO_BATT_PRES_ODL";
+		};
+		en_ec_id_odl: en_ec_id_odl {
+			gpios = <&gpioh 5 GPIO_ODR_HIGH>;
+		};
+		entering_rw: entering_rw {
+			gpios = <&gpioc 5 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_ENTERING_RW";
+		};
+		gpio_en_5v_usm: en_5v_usm {
+			gpios = <&gpiog 3 GPIO_OUTPUT_LOW>;
+		};
+		usb_a0_fault_odl: usb_a0_fault_odl {
+			gpios = <&gpioj 6 GPIO_INPUT>;
+		};
+		gpio_ec_x_gpio1: ec_x_gpio1 {
+			gpios = <&gpioh 4 GPIO_OUTPUT_LOW>;
+		};
+		gpio_ec_x_gpio3: ec_x_gpio3 {
+			gpios = <&gpioj 1 GPIO_OUTPUT_LOW>;
+		};
+		gpio_hdmi_prsnt_odl: hdmi_prsnt_odl {
+			gpios = <&gpioj 3 GPIO_INPUT>;
+		};
+		gpio_packet_mode_en: packet_mode_en {
+			gpios = <&gpiod 4 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_PACKET_MODE_EN";
+		};
+		gpio_ccd_mode_odl: ccd_mode_odl {
+			gpios = <&gpioc 4 GPIO_INPUT>;
+			enum-name = "GPIO_CCD_MODE_ODL";
+		};
+	};
+
+	hibernate-wake-pins {
+		compatible = "cros-ec,hibernate-wake-pins";
+		wakeup-irqs = <&int_ac_present
+			       &int_power_button
+			       &int_lid_open>;
+	};
+
+	unused-pins {
+		compatible = "unused-gpios";
+
+		unused-gpios =
+			/* pg_pp5000_z2_od */
+			<&gpiod 2 GPIO_INPUT>,
+			/* pg_mt6315_proc_b_odl */
+			<&gpioe 1 GPIO_INPUT>,
+			/* ec_pen_chg_dis_odl */
+			<&gpioh 3 GPIO_ODR_HIGH>,
+			/* unnamed nc pins */
+			<&gpioa 3 GPIO_INPUT_PULL_DOWN>,
+			<&gpioa 6 GPIO_INPUT_PULL_DOWN>,
+			<&gpioa 7 GPIO_INPUT_PULL_DOWN>,
+			<&gpiod 7 GPIO_INPUT_PULL_DOWN>,
+			<&gpiof 1 GPIO_INPUT_PULL_DOWN>,
+			<&gpioh 0 GPIO_INPUT_PULL_DOWN>,
+			<&gpioh 6 GPIO_INPUT_PULL_DOWN>,
+			<&gpioi 3 GPIO_INPUT_PULL_DOWN>,
+			<&gpioi 5 GPIO_INPUT_PULL_DOWN>,
+			<&gpioi 6 GPIO_INPUT_PULL_DOWN>,
+			<&gpiom 6 (GPIO_INPUT_PULL_DOWN | GPIO_VOLTAGE_1P8)>,
+			/* spi_clk_gpg6 */
+			<&gpiog 6 GPIO_INPUT_PULL_UP>,
+			/* spi_mosi_gpg4 */
+			<&gpiog 4 GPIO_OUTPUT_LOW>,
+			/* spi_miso_gpg5 */
+			<&gpiog 5 GPIO_OUTPUT_LOW>,
+			/* spi_cs_gpg7 */
+			<&gpiog 7 GPIO_OUTPUT_LOW>;
+	};
+};
+
+&pinctrl {
+	/* I2C property setting */
+	i2c0_clk_gpb3_default: i2c0_clk_gpb3_default {
+		gpio-voltage = "1v8";
+	};
+	i2c0_data_gpb4_default: i2c0_data_gpb4_default {
+		gpio-voltage = "1v8";
+	};
+	i2c3_clk_gpf2_default: i2c3_clk_gpf2_default {
+		gpio-voltage = "1v8";
+	};
+	i2c3_data_gpf3_default: i2c3_data_gpf3_default {
+		gpio-voltage = "1v8";
+	};
+	/* SHI property setting */
+	shi_mosi_gpm0_default: shi_mosi_gpm0_default {
+		gpio-voltage = "1v8";
+	};
+	shi_miso_gpm1_default: shi_miso_gpm1_default {
+		gpio-voltage = "1v8";
+	};
+	shi_clk_gpm4_default: shi_clk_gpm4_default {
+		gpio-voltage = "1v8";
+	};
+	shi_cs_gpm5_default: shi_cs_gpm5_default {
+		gpio-voltage = "1v8";
+	};
+};
diff --git a/zephyr/program/corsola/ite_i2c.dtsi b/zephyr/program/corsola/ite_i2c.dtsi
new file mode 100644
index 0000000000..1c499ad888
--- /dev/null
+++ b/zephyr/program/corsola/ite_i2c.dtsi
@@ -0,0 +1,145 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		battery {
+			i2c-port = <&i2c1>;
+			remote-port = <1>;
+			enum-names = "I2C_PORT_BATTERY",
+				"I2C_PORT_VIRTUAL_BATTERY";
+		};
+		i2c_charger: charger {
+			i2c-port = <&i2c0>;
+			enum-names = "I2C_PORT_CHARGER",
+				"I2C_PORT_EEPROM";
+		};
+		i2c_sensor: sensor {
+			i2c-port = <&i2c3>;
+			enum-names = "I2C_PORT_SENSOR";
+		};
+		i2c_usb_c0: usb-c0 {
+			i2c-port = <&i2c2>;
+			enum-names = "I2C_PORT_USB_C0",
+				"I2C_PORT_USB_MUX0";
+		};
+		i2c_usb_c1: usb-c1 {
+			i2c-port = <&i2c4>;
+			enum-names = "I2C_PORT_USB_C1",
+				"I2C_PORT_USB_MUX1";
+		};
+	};
+
+};
+
+&pinctrl {
+	i2c3_clk_gpf2_sleep: i2c3_clk_gpf2_sleep {
+		pinmuxs = <&pinctrlf 2 IT8XXX2_ALT_DEFAULT>;
+	};
+	i2c3_data_gpf3_sleep: i2c3_data_gpf3_sleep {
+		pinmuxs = <&pinctrlf 3 IT8XXX2_ALT_DEFAULT>;
+	};
+};
+
+&i2c0 {
+	/* EC_I2C_PWR_CBI */
+	label = "I2C_PWR_CBI";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c0_clk_gpb3_default
+		     &i2c0_data_gpb4_default>;
+	pinctrl-names = "default";
+
+	cbi_eeprom: eeprom@50 {
+		compatible = "atmel,at24";
+		reg = <0x50>;
+		size = <2048>;
+		pagesize = <16>;
+		address-width = <8>;
+		timeout = <5>;
+	};
+
+	charger_bc12_port1: rt9490@53 {
+		compatible = "richtek,rt9490";
+		status = "okay";
+		reg = <0x53>;
+		irq = <&int_usb_c1_bc12_charger>;
+		mivr = <4000>;
+	};
+};
+
+&i2c1 {
+	/* EC_I2C_BATTERY */
+	label = "I2C_BATTERY";
+	status = "okay";
+	clock-frequency = <50000>;
+	pinctrl-0 = <&i2c1_clk_gpc1_default
+		     &i2c1_data_gpc2_default>;
+	pinctrl-names = "default";
+	fifo-enable;
+};
+
+&i2c2 {
+	/* EC_I2C_USB_C0 */
+	label = "I2C_USB_C0";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c2_clk_gpf6_default
+		     &i2c2_data_gpf7_default>;
+	pinctrl-names = "default";
+	/delete-property/ fifo-enable;
+
+	bc12_ppc_port0: rt1739@70 {
+		compatible = "richtek,rt1739-bc12", "richtek,rt1739-ppc";
+		status = "okay";
+		reg = <0x70>;
+	};
+
+	it5205_mux_0: it5205-mux-0@48 {
+		compatible = "ite,it5205";
+		reg = <0x48>;
+	};
+};
+
+&i2c3 {
+	/* EC_I2C_SENSOR */
+	label = "I2C_SENSOR";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	scl-gpios = <&gpiof 2 0>;
+	sda-gpios = <&gpiof 3 0>;
+	pinctrl-0 = <&i2c3_clk_gpf2_default
+		     &i2c3_data_gpf3_default>;
+	pinctrl-1 = <&i2c3_clk_gpf2_sleep
+		     &i2c3_data_gpf3_sleep>;
+	pinctrl-names = "default", "sleep";
+	prescale-scl-low = <1>;
+};
+
+&i2c4 {
+	/* EC_I2C_USB_C1 */
+	label = "I2C_USB_C1";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c4_clk_gpe0_default
+		     &i2c4_data_gpe7_default>;
+	pinctrl-names = "default";
+	prescale-scl-low = <1>;
+
+	ppc_port1: syv682x@40 {
+		compatible = "silergy,syv682x";
+		status = "okay";
+		reg = <0x40>;
+		frs_en_gpio = <&gpio_ec_x_gpio1>;
+	};
+
+	tusb1064_mux_1: tusb1064-mux-1@44 {
+		compatible = "ti,tusb1064";
+		reg = <0x44>;
+		board-init = "tusb1064_mux_1_board_init";
+	};
+};
diff --git a/zephyr/program/corsola/ite_interrupts.dtsi b/zephyr/program/corsola/ite_interrupts.dtsi
new file mode 100644
index 0000000000..8dc6d4eab6
--- /dev/null
+++ b/zephyr/program/corsola/ite_interrupts.dtsi
@@ -0,0 +1,110 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	aliases {
+		int-wp = &int_wp;
+	};
+
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_power_button: power_button {
+			irq-pin = <&power_button_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_button_interrupt";
+		};
+		int_volume_up: volume_up {
+			irq-pin = <&volume_up_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+		int_volume_down: volume_down {
+			irq-pin = <&volume_down_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+		int_lid_open: lid_open {
+			irq-pin = <&lid_open>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "lid_interrupt";
+		};
+		int_warm_rst: warm_rst {
+			irq-pin = <&ap_ec_warm_rst_req>;
+			flags = <GPIO_INT_EDGE_RISING>;
+			handler = "chipset_reset_request_interrupt";
+		};
+		int_ap_in_sleep: ap_in_sleep {
+			irq-pin = <&ap_in_sleep_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_ap_in_rst: ap_in_rst {
+			irq-pin = <&ap_sysrst_odl_r>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "chipset_warm_reset_interrupt";
+		};
+		int_ap_wdtrst: ap_wdtrst {
+			irq-pin = <&ap_ec_wdtrst_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "chipset_watchdog_interrupt";
+		};
+		int_tablet_mode: tablet_mode {
+			irq-pin = <&tablet_mode_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "gmr_tablet_switch_isr";
+		};
+		int_base_imu: base_imu {
+			irq-pin = <&base_imu_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "icm42607_interrupt";
+		};
+		int_lid_imu: lid_imu {
+			irq-pin = <&lid_accel_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "lis2dw12_interrupt";
+		};
+		int_ac_present: ac_present {
+			irq-pin = <&ac_present>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "extpower_interrupt";
+		};
+		int_xhci: xhci_init_done {
+			irq-pin = <&gpio_ap_xhci_init_done>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "xhci_interrupt";
+		};
+		int_wp: wp {
+			irq-pin = <&ec_flash_wp_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "switch_interrupt";
+		};
+		int_spi0_cs: spi0_cs {
+			irq-pin = <&spi0_cs>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "spi_event";
+		};
+		int_x_ec_gpio2: x_ec_gpio2 {
+			irq-pin = <&gpio_x_ec_gpio2>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "x_ec_interrupt";
+		};
+		int_usb_c0_ppc_bc12: usb_c0_ppc_bc12 {
+			irq-pin = <&usb_c0_ppc_bc12_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "c0_bc12_interrupt";
+		};
+		int_usb_c1_bc12_charger: usb_c1_bc12_charger {
+			irq-pin = <&usb_c1_bc12_charger_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "rt9490_bc12_dt_interrupt";
+		};
+		int_ccd_mode_odl: ccd-mode-odl {
+			irq-pin = <&gpio_ccd_mode_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "ccd_interrupt";
+		};
+	};
+};
diff --git a/zephyr/program/corsola/ite_keyboard.dtsi b/zephyr/program/corsola/ite_keyboard.dtsi
new file mode 100644
index 0000000000..0bd6887ddb
--- /dev/null
+++ b/zephyr/program/corsola/ite_keyboard.dtsi
@@ -0,0 +1,54 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	cros-keyscan {
+		compatible = "cros-ec,keyscan";
+
+		scan-period = <10000>;
+
+		actual-key-mask = <
+			0x1c	/* C0 */
+			0xff	/* C1 */
+			0xff	/* C2 */
+			0xff	/* C3 */
+			0xff	/* C4 */
+			0xf5	/* C5 */
+			0xff	/* C6 */
+			0xa4	/* C7 */
+			0xff	/* C8 */
+			0xfe	/* C9 */
+			0x55	/* C10 */
+			0xfa	/* C11 */
+			0xca	/* C12 */
+			>;
+	};
+};
+
+&cros_kb_raw {
+	status = "okay";
+	/* No KSO2 (it's inverted and implemented by GPIO) */
+	pinctrl-0 = <&ksi0_default
+		     &ksi1_default
+		     &ksi2_default
+		     &ksi3_default
+		     &ksi4_default
+		     &ksi5_default
+		     &ksi6_default
+		     &ksi7_default
+		     &kso0_default
+		     &kso1_default
+		     &kso3_default
+		     &kso4_default
+		     &kso5_default
+		     &kso6_default
+		     &kso7_default
+		     &kso8_default
+		     &kso9_default
+		     &kso10_default
+		     &kso11_default
+		     &kso12_default>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/corsola/ite_led.dtsi b/zephyr/program/corsola/ite_led.dtsi
new file mode 100644
index 0000000000..721a4dd8a4
--- /dev/null
+++ b/zephyr/program/corsola/ite_led.dtsi
@@ -0,0 +1,174 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include <dt-bindings/battery.h>
+
+/ {
+	led-colors {
+		compatible = "cros-ec,led-policy";
+
+		bat-power-state-charge {
+			charge-state = "LED_PWRS_CHARGE";
+
+			color-0 {
+				led-color = <&color_battery_amber>;
+			};
+		};
+
+		bat-power-state-near-full {
+			charge-state = "LED_PWRS_CHARGE_NEAR_FULL";
+
+			color-0 {
+				led-color = <&color_battery_white>;
+			};
+		};
+
+		bat-power-state-discharge {
+			charge-state = "LED_PWRS_DISCHARGE";
+
+			color-0 {
+				led-color = <&color_battery_off>;
+			};
+		};
+
+		bat-power-state-discharge-s0-bat-low {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S0";
+			batt-lvl = <BATTERY_LEVEL_EMPTY BATTERY_LEVEL_LOW>;
+
+			color-0 {
+				led-color = <&color_battery_amber>;
+				period-ms = <1000>;
+			};
+
+			color-1 {
+				led-color = <&color_battery_off>;
+				period-ms = <3000>;
+			};
+		};
+
+		bat-power-state-error {
+			charge-state = "LED_PWRS_ERROR";
+
+			color-0 {
+				led-color = <&color_battery_amber>;
+				period-ms = <1000>;
+			};
+
+			color-1 {
+				led-color = <&color_battery_off>;
+				period-ms = <1000>;
+			};
+		};
+
+		pwr-power-state-off {
+			color-0 {
+				led-color = <&color_power_off>;
+			};
+		};
+
+		pwr-power-state-on {
+			chipset-state = "POWER_S0";
+
+			color-0 {
+				led-color = <&color_power_white>;
+			};
+		};
+
+		pwr-power-state-s3 {
+			chipset-state = "POWER_S3";
+
+			color-0 {
+				led-color = <&color_power_white>;
+				period-ms = <1000>;
+			};
+
+			color-1 {
+				led-color = <&color_power_off>;
+				period-ms = <3000>;
+			};
+		};
+	};
+
+	pwmleds {
+		compatible = "pwm-leds";
+
+		/* NOTE: &pwm number needs same with channel number */
+		led_power_white: ec_led1_odl {
+			pwms = <&pwm0 PWM_CHANNEL_0 PWM_HZ(324) PWM_POLARITY_INVERTED>;
+		};
+		led_battery_amber: ec_led2_odl {
+			pwms = <&pwm1 PWM_CHANNEL_1 PWM_HZ(324) PWM_POLARITY_INVERTED>;
+		};
+		led_battery_white: ec_led3_odl {
+			pwms = <&pwm2 PWM_CHANNEL_2 PWM_HZ(324) PWM_POLARITY_INVERTED>;
+		};
+	};
+
+	pwm-led-pins {
+		compatible = "cros-ec,pwm-led-pins";
+
+		power_led: power-led {
+			led-id = "EC_LED_ID_POWER_LED";
+			led-pwms = <&led_power_white>;
+
+			color_power_off: color-power-off {
+				led-color = "LED_OFF";
+				led-values = <0>;
+			};
+
+			color_power_white: color-power-white {
+				led-color = "LED_WHITE";
+				br-color = "EC_LED_COLOR_WHITE";
+				led-values = <100>;
+			};
+		};
+
+		battery_led: battery-led {
+			led-id = "EC_LED_ID_BATTERY_LED";
+			led-pwms = <&led_battery_amber &led_battery_white>;
+
+			color_battery_off: color-battery-off {
+				led-color = "LED_OFF";
+				led-values = <0 0>;
+			};
+
+			color_battery_amber: color-battery-amber {
+				led-color = "LED_AMBER";
+				br-color = "EC_LED_COLOR_AMBER";
+				led-values = <100 0>;
+			};
+
+			color_battery_white: color-battery-white {
+				led-color = "LED_WHITE";
+				br-color = "EC_LED_COLOR_WHITE";
+				led-values = <0 100>;
+			};
+		};
+	};
+};
+
+/* LED1 */
+&pwm0 {
+	status = "okay";
+	prescaler-cx = <PWM_PRESCALER_C4>;
+	pinctrl-0 = <&pwm0_gpa0_default>;
+	pinctrl-names = "default";
+};
+
+/* LED2 */
+&pwm1 {
+	status = "okay";
+	prescaler-cx = <PWM_PRESCALER_C4>;
+	pinctrl-0 = <&pwm1_gpa1_default>;
+	pinctrl-names = "default";
+};
+
+/* LED3 */
+&pwm2 {
+	status = "okay";
+	prescaler-cx = <PWM_PRESCALER_C4>;
+	pinctrl-0 = <&pwm2_gpa2_default>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/corsola/ite_motionsense.dtsi b/zephyr/program/corsola/ite_motionsense.dtsi
new file mode 100644
index 0000000000..1c7d5b2df4
--- /dev/null
+++ b/zephyr/program/corsola/ite_motionsense.dtsi
@@ -0,0 +1,146 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/motionsense/utils.h>
+
+
+/ {
+	aliases {
+		/*
+		 * motion sense's <>_INT_EVENT is handled
+		 * by alias. Using the alias, each driver creates
+		 * its own <>_INT_EVENT.
+		 */
+		icm42607-int = &base_accel;
+		lis2dw12-int = &lid_accel;
+	};
+
+	/*
+	 * Declare mutexes used by sensor drivers.
+	 * A mutex node is used to create an instance of mutex_t.
+	 * A mutex node is referenced by a sensor node if the
+	 * corresponding sensor driver needs to use the
+	 * instance of the mutex.
+	 */
+	motionsense-mutex {
+		compatible = "cros-ec,motionsense-mutex";
+		lid_mutex: lid-mutex {
+		};
+
+		base_mutex: icm42607-mutex {
+		};
+	};
+
+	/* Rotation matrix used by drivers. */
+	motionsense-rotation-ref {
+		compatible = "cros-ec,motionsense-rotation-ref";
+		lid_rot_ref: lid-rotation-ref {
+			mat33 = <1 0 0
+				 0 1 0
+				 0 0 1>;
+		};
+
+		base_rot_ref: base-rotation-ref {
+			mat33 = <1 0 0
+				 0 1 0
+				 0 0 1>;
+		};
+	};
+
+	/*
+	 * Driver specific data. A driver-specific data can be shared with
+	 * different motion sensors while they are using the same driver.
+	 *
+	 * If a node's compatible starts with "cros-ec,accelgyro-", it is for
+	 * a common structure defined in accelgyro.h.
+	 * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for
+	 * "struct als_drv_data_t" in accelgyro.h
+	 */
+	motionsense-sensor-data {
+		icm42607_data: icm42607-drv-data {
+			compatible = "cros-ec,drvdata-icm42607";
+			status = "okay";
+		};
+
+		lis2dw12_data: lis2dw12-drv-data {
+			compatible = "cros-ec,drvdata-lis2dw12";
+			status = "okay";
+		};
+	};
+
+	/*
+	 * List of motion sensors that creates motion_sensors array.
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
+	 * motion sensor IDs for lid angle calculation.
+	 */
+	motionsense-sensor {
+		lid_accel: lid-accel {
+			compatible = "cros-ec,lis2dw12";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&lid_mutex>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&lid_rot_ref>;
+			default-range = <2>;
+			drv-data = <&lis2dw12_data>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_accel: base-accel {
+			compatible = "cros-ec,icm42607-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&icm42607_data>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_gyro: base-gyro {
+			compatible = "cros-ec,icm42607-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&icm42607_data>;
+		};
+	};
+
+	motionsense-sensor-info {
+		compatible = "cros-ec,motionsense-sensor-info";
+
+		/*
+		 * list of GPIO interrupts that have to
+		 * be enabled at initial stage
+		 */
+		sensor-irqs = <&int_base_imu &int_lid_imu>;
+	};
+};
diff --git a/zephyr/program/corsola/ite_program.conf b/zephyr/program/corsola/ite_program.conf
new file mode 100644
index 0000000000..5c3cfd5787
--- /dev/null
+++ b/zephyr/program/corsola/ite_program.conf
@@ -0,0 +1,72 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Bring up options
+CONFIG_SHELL_HISTORY_BUFFER=256
+CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y
+CONFIG_PLATFORM_EC_BRINGUP=y
+
+# Power Sequencing
+CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK=y
+
+# Lid Switch
+CONFIG_PLATFORM_EC_LID_SWITCH=y
+
+# Charger
+CONFIG_PLATFORM_EC_CHARGE_RAMP_HW=y
+CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y
+CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC_CHARGER=y
+CONFIG_PLATFORM_EC_CHARGER_MAINTAIN_VBAT=y
+CONFIG_PLATFORM_EC_CHARGER_PSYS=y
+CONFIG_PLATFORM_EC_CHARGER_PSYS_READ=y
+# BOARD_RS2
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10
+# BOARD_RS1
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=20
+CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_DUMP=y
+
+# Host Commands
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_ADC_AMON_BMON=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_SYSINFO=y
+CONFIG_PLATFORM_EC_HOST_COMMAND_STATUS=y
+
+# Sensors
+CONFIG_PLATFORM_EC_ACCEL_FIFO=y
+CONFIG_PLATFORM_EC_GMR_TABLET_MODE=y
+CONFIG_PLATFORM_EC_LID_ANGLE=y
+CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y
+CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=y
+CONFIG_PLATFORM_EC_TABLET_MODE=y
+CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=y
+CONFIG_PLATFORM_EC_MAX_SENSOR_FREQ_MILLIHZ=100000
+
+# Sensor Drivers
+CONFIG_PLATFORM_EC_ACCEL_LIS2DW12=y
+CONFIG_PLATFORM_EC_ACCELGYRO_ICM42607=y
+CONFIG_PLATFORM_EC_ACCELGYRO_ICM_COMM_I2C=y
+
+# Tasks
+CONFIG_TASK_CHARGER_STACK_SIZE=1024
+CONFIG_TASK_CHIPSET_STACK_SIZE=1440
+CONFIG_TASK_MOTIONSENSE_STACK_SIZE=1280
+CONFIG_TASK_PD_STACK_SIZE=1280
+
+# USB-C
+CONFIG_PLATFORM_EC_BC12_SINGLE_DRIVER=n
+CONFIG_PLATFORM_EC_USBC_PPC_SYV682C=y
+CONFIG_PLATFORM_EC_USB_MUX_TUSB546=y
+CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y
+CONFIG_PLATFORM_EC_USB_PD_FRS_PPC=y
+CONFIG_PLATFORM_EC_USB_PD_LOGGING=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_PPC=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_ADC_EACH_PORT=y
+CONFIG_PLATFORM_EC_USB_PD_DUAL_ROLE_AUTO_TOGGLE=n
+CONFIG_PLATFORM_EC_CONFIG_USB_PD_3A_PORTS=0
+CONFIG_PLATFORM_EC_USB_PD_PULLUP=1
+
+# TODO(b/180980668): bring these features up
+CONFIG_LTO=n
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
diff --git a/zephyr/program/corsola/ite_shi.dtsi b/zephyr/program/corsola/ite_shi.dtsi
new file mode 100644
index 0000000000..1a21a3ffb8
--- /dev/null
+++ b/zephyr/program/corsola/ite_shi.dtsi
@@ -0,0 +1,15 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <ite/it8xxx2-pinctrl-map.dtsi>
+
+&shi0 {
+	status = "okay";
+	pinctrl-0 = <&shi_mosi_gpm0_default &shi_miso_gpm1_default
+		     &shi_clk_gpm4_default &shi_cs_gpm5_default>;
+	pinctrl-names = "default";
+	/* unused but needed by dt binding */
+	cs-gpios = <&gpiom 5 GPIO_VOLTAGE_1P8>;
+};
diff --git a/zephyr/program/corsola/ite_usbc.dtsi b/zephyr/program/corsola/ite_usbc.dtsi
new file mode 100644
index 0000000000..f8881e437c
--- /dev/null
+++ b/zephyr/program/corsola/ite_usbc.dtsi
@@ -0,0 +1,59 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+			bc12 = <&bc12_ppc_port0>;
+			ppc = <&bc12_ppc_port0>;
+			tcpc = <&usbpd0>;
+			chg = <&charger_bc12_port1>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&it5205_mux_0 &virtual_mux_0>;
+			};
+		};
+		port0-muxes {
+			virtual_mux_0: virtual-mux-0 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+
+		port1@1 {
+			compatible = "named-usbc-port";
+			reg = <1>;
+			bc12 = <&charger_bc12_port1>;
+			ppc = <&ppc_port1>;
+			tcpc = <&usbpd1>;
+			usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&tusb1064_mux_1 &virtual_mux_1>;
+			};
+			usb_mux_chain_1_hdmi_db: usb-mux-chain-1-hdmi-db {
+				compatible = "cros-ec,usb-mux-chain";
+				alternative-chain;
+				usb-muxes = <&virtual_mux_1>;
+			};
+		};
+		port1-muxes {
+			virtual_mux_1: virtual-mux-1 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+	};
+};
+
+&usbpd0 {
+	status = "okay";
+};
+
+&usbpd1 {
+	status = "okay";
+};
diff --git a/zephyr/program/corsola/kingler/CMakeLists.txt b/zephyr/program/corsola/kingler/CMakeLists.txt
new file mode 100644
index 0000000000..8f0194e052
--- /dev/null
+++ b/zephyr/program/corsola/kingler/CMakeLists.txt
@@ -0,0 +1,13 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Kingler Makeifile
+
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_I2C "../src/npcx_i2c.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC
+                             "../src/npcx_usb_pd_policy.c" "../src/npcx_usbc.c")
+
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_BUTTONS_RUNTIME_CONFIG
+                             "src/button.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LED_COMMON "src/led.c")
diff --git a/zephyr/program/corsola/kingler/project.conf b/zephyr/program/corsola/kingler/project.conf
new file mode 100644
index 0000000000..cd4a735d71
--- /dev/null
+++ b/zephyr/program/corsola/kingler/project.conf
@@ -0,0 +1,9 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Variant config
+CONFIG_BOARD_KINGLER=y
+
+# Keyboard
+CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI2=y
diff --git a/zephyr/program/corsola/kingler/project.overlay b/zephyr/program/corsola/kingler/project.overlay
new file mode 100644
index 0000000000..93f06d94e2
--- /dev/null
+++ b/zephyr/program/corsola/kingler/project.overlay
@@ -0,0 +1,96 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Corsola program common DTS includes */
+
+#include "../common.dtsi"
+#include "../power_signal.dtsi"
+#include "../usba.dtsi"
+#include "../npcx_adc.dtsi"
+#include "../npcx_host_interface.dtsi"
+#include "../npcx_i2c.dtsi"
+#include "../npcx_interrupts.dtsi"
+#include "../npcx_gpio.dtsi"
+#include "../npcx_keyboard.dtsi"
+#include "../npcx_motionsense.dtsi"
+#include "../npcx_usbc.dtsi"
+#include "../npcx_default_gpio_pinctrl.dtsi"
+
+/* board override */
+/ {
+	batteries {
+		default_battery: smp_l20m3pg2 {
+			compatible = "smp,l20m3pg2", "battery-smart";
+		};
+		lgc_l20l3pg2 {
+			compatible = "lgc,l20l3pg2", "battery-smart";
+		};
+	};
+
+	pwmleds {
+		compatible = "pwm-leds";
+		pwm_led0: pwm_led_0 {
+			pwms = <&pwm0 0 PWM_HZ(100) PWM_POLARITY_INVERTED
+				&pwm1 0 PWM_HZ(100) PWM_POLARITY_INVERTED
+				&pwm2 0 PWM_HZ(100) PWM_POLARITY_INVERTED>;
+		};
+	};
+
+	cros-pwmleds {
+		compatible = "cros-ec,pwm-leds";
+
+		leds = <&pwm_led0>;
+
+		color-map-red    = <100   0   0>;
+		color-map-green  = <  0 100   0>;
+		color-map-amber  = <100  20   0>;
+
+		brightness-range = <255 255 0 0 0 255>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pwm_led_0@0 {
+			reg = <0>;
+			ec-led-name = "EC_LED_ID_BATTERY_LED";
+		};
+	};
+};
+
+/* Red LED */
+&pwm0_gpc3 {
+	drive-open-drain;
+};
+
+&pwm0 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm0_gpc3>;
+	pinctrl-names = "default";
+};
+
+/* Green LED */
+&pwm1_gpc2 {
+	drive-open-drain;
+};
+
+&pwm1 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm1_gpc2>;
+	pinctrl-names = "default";
+};
+
+/* Blue LED */
+&pwm2_gpc4 {
+	drive-open-drain;
+};
+
+&pwm2 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm2_gpc4>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/corsola/kingler/src/button.c b/zephyr/program/corsola/kingler/src/button.c
new file mode 100644
index 0000000000..920069bef6
--- /dev/null
+++ b/zephyr/program/corsola/kingler/src/button.c
@@ -0,0 +1,35 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* kingler button */
+
+#include "button.h"
+#include "cros_board_info.h"
+#include "gpio.h"
+#include "hooks.h"
+
+static void buttons_hook(void)
+{
+	int version;
+
+	if (cbi_get_board_version(&version)) {
+		return;
+	}
+
+	/* b:219891339: drop this workaround when we deprecate rev0 */
+	if (version == 0) {
+		/* swap VOLUP/VOLDN */
+		button_reassign_gpio(BUTTON_VOLUME_DOWN, GPIO_VOLUME_UP_L);
+		button_reassign_gpio(BUTTON_VOLUME_UP, GPIO_VOLUME_DOWN_L);
+		/*
+		 * button_reassign_gpio will disable the old button interrupt
+		 * and then enable the new button interrupt which cause the
+		 * GPIO_VOLUME_UP_L interrupt disabled after we reassign
+		 * BUTTON_VOLUME_UP, so we need to re-enable it here.
+		 */
+		gpio_enable_interrupt(GPIO_VOLUME_UP_L);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, buttons_hook, HOOK_PRIO_DEFAULT);
diff --git a/zephyr/program/corsola/kingler/src/led.c b/zephyr/program/corsola/kingler/src/led.c
new file mode 100644
index 0000000000..2ce240833a
--- /dev/null
+++ b/zephyr/program/corsola/kingler/src/led.c
@@ -0,0 +1,51 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery LED control for Kingler
+ */
+#include "common.h"
+#include "ec_commands.h"
+#include "led_onoff_states.h"
+#include "led_pwm.h"
+
+__override const int led_charge_lvl_1 = 5;
+__override const int led_charge_lvl_2 = 97;
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_RED:
+		set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_RED);
+		break;
+	case EC_LED_COLOR_GREEN:
+		set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_GREEN);
+		break;
+	case EC_LED_COLOR_AMBER:
+		set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_AMBER);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		set_pwm_led_color(EC_LED_ID_BATTERY_LED, -1);
+		break;
+	}
+}
diff --git a/zephyr/program/corsola/krabby/CMakeLists.txt b/zephyr/program/corsola/krabby/CMakeLists.txt
new file mode 100644
index 0000000000..967e6a3091
--- /dev/null
+++ b/zephyr/program/corsola/krabby/CMakeLists.txt
@@ -0,0 +1,12 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a
+# BSD-style license that can be found in the LICENSE file.
+
+# Krabby Makeifile
+
+zephyr_library_sources("../src/ite_hooks.c" "../src/ite_charger_workaround.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_I2C "../src/ite_i2c.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC
+                             "../src/ite_usb_pd_policy.c" "../src/ite_usbc.c")
+
+zephyr_library_sources("src/ppc.c")
diff --git a/zephyr/program/corsola/krabby/project.conf b/zephyr/program/corsola/krabby/project.conf
new file mode 100644
index 0000000000..c4cde05c16
--- /dev/null
+++ b/zephyr/program/corsola/krabby/project.conf
@@ -0,0 +1,9 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Variant config
+CONFIG_BOARD_KRABBY=y
+
+# Keyboard
+CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI2=y
diff --git a/zephyr/program/corsola/krabby/project.overlay b/zephyr/program/corsola/krabby/project.overlay
new file mode 100644
index 0000000000..5a7db69b43
--- /dev/null
+++ b/zephyr/program/corsola/krabby/project.overlay
@@ -0,0 +1,28 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Corsola program common DTS includes */
+
+#include "../common.dtsi"
+#include "../power_signal.dtsi"
+#include "../usba.dtsi"
+#include "../ite_adc.dtsi"
+#include "../ite_gpio.dtsi"
+#include "../ite_keyboard.dtsi"
+#include "../ite_i2c.dtsi"
+#include "../ite_interrupts.dtsi"
+#include "../ite_led.dtsi"
+#include "../ite_motionsense.dtsi"
+#include "../ite_usbc.dtsi"
+#include "../ite_shi.dtsi"
+
+
+/ {
+	batteries {
+		default_battery: c235 {
+			compatible = "celxpert,c235-41", "battery-smart";
+		};
+	};
+};
diff --git a/zephyr/program/corsola/krabby/src/ppc.c b/zephyr/program/corsola/krabby/src/ppc.c
new file mode 100644
index 0000000000..121d5ca279
--- /dev/null
+++ b/zephyr/program/corsola/krabby/src/ppc.c
@@ -0,0 +1,30 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Krabby PPC/BC12 (RT1739) configuration */
+
+#include "baseboard_usbc_config.h"
+#include "driver/ppc/rt1739.h"
+#include "driver/ppc/syv682x.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+
+void c0_bc12_interrupt(enum gpio_signal signal)
+{
+	rt1739_interrupt(0);
+}
+
+static void board_usbc_init(void)
+{
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_ppc_bc12));
+}
+DECLARE_HOOK(HOOK_INIT, board_usbc_init, HOOK_PRIO_POST_DEFAULT);
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	if (signal == GPIO_SIGNAL(DT_ALIAS(gpio_usb_c1_ppc_int_odl))) {
+		syv682x_interrupt(1);
+	}
+}
diff --git a/zephyr/program/corsola/magikarp/CMakeLists.txt b/zephyr/program/corsola/magikarp/CMakeLists.txt
new file mode 100644
index 0000000000..895698a7f3
--- /dev/null
+++ b/zephyr/program/corsola/magikarp/CMakeLists.txt
@@ -0,0 +1,12 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Magikarp Makeifile
+
+zephyr_library_sources("../src/ite_hooks.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_I2C "../src/ite_i2c.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC
+                             "../src/ite_usb_pd_policy.c" "../src/ite_usbc.c")
+
+zephyr_library_sources("src/sensor.c" "src/ppc.c" "src/keyboard.c")
diff --git a/zephyr/program/corsola/magikarp/project.conf b/zephyr/program/corsola/magikarp/project.conf
new file mode 100644
index 0000000000..70e21933b3
--- /dev/null
+++ b/zephyr/program/corsola/magikarp/project.conf
@@ -0,0 +1,21 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Variant config
+CONFIG_BOARD_MAGIKARP=y
+
+# USB-C
+CONFIG_PLATFORM_EC_USB_MUX_TUSB546=n
+CONFIG_PLATFORM_EC_PD_MAX_POWER_MW=45000
+
+# Keyboard
+CONFIG_PLATFORM_EC_KEYBOARD_REFRESH_ROW3=y
+CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI3=y
+
+# Sensor
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y
+
+# Battery
+CONFIG_PLATFORM_EC_BATTERY_REVIVE_DISCONNECT=y
diff --git a/zephyr/program/corsola/magikarp/project.overlay b/zephyr/program/corsola/magikarp/project.overlay
new file mode 100644
index 0000000000..93b40fd7b7
--- /dev/null
+++ b/zephyr/program/corsola/magikarp/project.overlay
@@ -0,0 +1,424 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Corsola program common DTS includes */
+
+#include <cros/thermistor/thermistor.dtsi>
+#include "../common.dtsi"
+#include "../power_signal.dtsi"
+#include "../usba.dtsi"
+#include "../ite_adc.dtsi"
+#include "../ite_gpio.dtsi"
+#include "../ite_keyboard.dtsi"
+#include "../ite_i2c.dtsi"
+#include "../ite_interrupts.dtsi"
+#include "../ite_led.dtsi"
+#include "../ite_motionsense.dtsi"
+#include "../ite_usbc.dtsi"
+#include "../ite_shi.dtsi"
+
+/ {
+	aliases {
+		/*
+		 * motion sense's <>_INT_EVENT is handled
+		 * by alias. Using the alias, each driver creates
+		 * its own <>_INT_EVENT.
+		 */
+		bmi3xx-int = &base_accel;
+	};
+
+	named-gpios {
+		/delete-node/ usb_c0_ppc_bc12_int_odl;
+
+		usb_c0_ppc_int_odl: usb_c0_ppc_int_odl {
+			gpios = <&gpiod 1 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C0_PPC_INT_ODL";
+		};
+
+		usb_c0_bc12_int_odl: usb_c0_bc12_int_odl {
+			gpios = <&gpiof 1 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C0_BC12_INT_ODL";
+		};
+
+		/delete-node/ usb_c0_ppc_frsinfo;
+
+		usb_c0_frs_en: usb_c0_frs_en {
+			gpios = <&gpiof 0 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_USB_C0_FRS_EN";
+		};
+	};
+
+	unused-pins {
+		unused-gpios =
+			/* pg_pp5000_z2_od */
+			<&gpiod 2 GPIO_INPUT>,
+			/* pg_mt6315_proc_b_odl */
+			<&gpioe 1 GPIO_INPUT>,
+			/* ec_pen_chg_dis_odl */
+			<&gpioh 3 GPIO_ODR_HIGH>,
+			/* unnamed nc pins */
+			<&gpioa 3 GPIO_INPUT_PULL_DOWN>,
+			<&gpioa 6 GPIO_INPUT_PULL_DOWN>,
+			<&gpioa 7 GPIO_INPUT_PULL_DOWN>,
+			/* reserved for b:241345809 */
+			<&gpiod 7 GPIO_OUTPUT_LOW>,
+			<&gpiog 2 GPIO_INPUT_PULL_DOWN>,
+			<&gpioh 0 GPIO_INPUT_PULL_DOWN>,
+			<&gpioh 6 GPIO_INPUT_PULL_DOWN>,
+			<&gpioi 3 GPIO_INPUT_PULL_DOWN>,
+			<&gpioi 6 GPIO_INPUT_PULL_DOWN>,
+			<&gpiom 6 (GPIO_INPUT_PULL_DOWN | GPIO_VOLTAGE_1P8)>,
+			/* spi_clk_gpg6 */
+			<&gpiog 6 GPIO_INPUT_PULL_UP>,
+			/* spi_mosi_gpg4 */
+			<&gpiog 4 GPIO_OUTPUT_LOW>,
+			/* spi_miso_gpg5 */
+			<&gpiog 5 GPIO_OUTPUT_LOW>,
+			/* spi_cs_gpg7 */
+			<&gpiog 7 GPIO_OUTPUT_LOW>;
+	};
+
+	gpio-interrupts {
+		int_base_imu: base_imu {
+			handler = "motion_interrupt";
+		};
+
+		/delete-node/ usb_c0_ppc_bc12;
+
+		int_usb_c0_ppc: usb_c0_ppc {
+			irq-pin = <&usb_c0_ppc_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "ppc_interrupt";
+		};
+
+		int_usb_c0_bc12: usb_c0_bc12 {
+			irq-pin = <&usb_c0_bc12_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "bc12_interrupt";
+		};
+	};
+
+
+	usbc {
+		port0@0 {
+			bc12 = <&bc12_port0>;
+			ppc = <&ppc_port0>;
+		};
+
+		port1@1 {
+			usb-mux-chain-1 {
+				usb-muxes = <&ps8743_mux_1 &virtual_mux_1>;
+			};
+		};
+	};
+
+	named-adc-channels {
+		compatible = "named-adc-channels";
+		adc_ambient: ambient {
+			enum-name = "ADC_TEMP_SENSOR_2_AMBIENT";
+			io-channels = <&adc0 5>;
+		};
+	};
+
+
+	temp_ambient: ambient {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_30K9_47K_NCP15WB>;
+		adc = <&adc_ambient>;
+	};
+
+	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
+		ambient {
+			sensor = <&temp_ambient>;
+		};
+	};
+
+	/*
+	 * Declare mutexes used by sensor drivers.
+	 * A mutex node is used to create an instance of mutex_t.
+	 * A mutex node is referenced by a sensor node if the
+	 * corresponding sensor driver needs to use the
+	 * instance of the mutex.
+	 */
+	motionsense-mutex {
+		base_mutex_bmi323: bmi323-mutex {
+		};
+	};
+
+	/* Rotation matrix used by drivers. */
+	motionsense-rotation-ref {
+		lid_rot_ref: lid-rotation-ref {
+			mat33 = <1 0 0
+				 0 1 0
+				 0 0 (-1)>;
+		};
+
+		base_rot_ref_bmi: base-rotation-ref-bmi {
+			mat33 = <0 1 0
+				 (-1) 0 0
+				 0 0 1>;
+		};
+	};
+
+	/*
+	 * Driver specific data. A driver-specific data can be shared with
+	 * different motion sensors while they are using the same driver.
+	 *
+	 * If a node's compatible starts with "cros-ec,accelgyro-", it is for
+	 * a common structure defined in accelgyro.h.
+	 * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for
+	 * "struct als_drv_data_t" in accelgyro.h
+	 */
+	motionsense-sensor-data {
+		bmi323_data: bmi323-drv-data {
+			compatible = "cros-ec,drvdata-bmi3xx";
+			status = "okay";
+		};
+	};
+
+	motionsense-sensor-alt {
+		alt_base_accel: alt-base-accel {
+			compatible = "cros-ec,bmi3xx-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex_bmi323>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref_bmi>;
+			drv-data = <&bmi323_data>;
+			alternate-for = <&base_accel>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		alt_base_gyro: alt-base-gyro {
+			compatible = "cros-ec,bmi3xx-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex_bmi323>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref_bmi>;
+			drv-data = <&bmi323_data>;
+			alternate-for = <&base_gyro>;
+		};
+	};
+
+	led-colors {
+		compatible = "cros-ec,led-policy";
+
+		/* Magikarp LED bat charge */
+		bat-power-state-charge {
+			charge-state = "LED_PWRS_CHARGE";
+			/* Battery percent range (>= Empty, <= 94%) */
+			batt-lvl = <BATTERY_LEVEL_EMPTY 94>;
+			color-0 {
+				led-color = <&color_battery_amber>;
+			};
+		};
+
+		bat-power-state-charge-near-full {
+			charge-state = "LED_PWRS_CHARGE";
+			/* Battery percent range (>= 95%, <= Full) */
+			batt-lvl = <95 BATTERY_LEVEL_FULL>;
+			color-0 {
+				led-color = <&color_battery_white>;
+			};
+		};
+
+		/* Magikarp LED bat discharge */
+		bat-power-state-discharge-s0 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S0";
+			/* Battery percent range (>= 11%, <= Full) */
+			batt-lvl = <(BATTERY_LEVEL_LOW + 1) BATTERY_LEVEL_FULL>;
+
+			color-0 {
+				led-color = <&color_battery_white>;
+			};
+		};
+
+
+		bat-power-state-discharge-s0-bat-low {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S0";
+			/* Battery percent range (>= Empty, <= 10%) */
+			batt-lvl = <BATTERY_LEVEL_EMPTY BATTERY_LEVEL_LOW>;
+
+			color-0 {
+				led-color = <&color_battery_amber>;
+				period-ms = <1000>;
+			};
+
+			color-1 {
+				led-color = <&color_battery_off>;
+				period-ms = <3000>;
+			};
+		};
+
+		bat-power-state-discharge-s3 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S3";
+
+			color-0 {
+				led-color = <&color_battery_white>;
+				period-ms = <1000>;
+			};
+
+			color-1 {
+				led-color = <&color_battery_off>;
+				period-ms = <3000>;
+			};
+		};
+
+		bat-power-state-discharge-s5 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S5";
+			color-0 {
+				led-color = <&color_battery_off>;
+			};
+		};
+
+		/* Magikarp LED bat error */
+		bat-power-state-error {
+			charge-state = "LED_PWRS_ERROR";
+			chipset-state = "POWER_S0";
+
+			color-0 {
+				led-color = <&color_battery_amber>;
+				period-ms = <1000>;
+			};
+
+			color-1 {
+				led-color = <&color_battery_off>;
+				period-ms = <1000>;
+			};
+		};
+
+		bat-power-state-error-s3 {
+			charge-state = "LED_PWRS_ERROR";
+			chipset-state = "POWER_S3";
+
+			color-0 {
+				led-color = <&color_battery_white>;
+				period-ms = <1000>;
+			};
+
+			color-1 {
+				led-color = <&color_battery_off>;
+				period-ms = <3000>;
+			};
+		};
+
+		bat-power-state-error-s5 {
+			charge-state = "LED_PWRS_ERROR";
+			chipset-state = "POWER_S5";
+
+			color-0 {
+				led-color = <&color_battery_off>;
+			};
+		};
+	};
+
+	pwm-led-pins {
+		compatible = "cros-ec,pwm-led-pins";
+
+		power_led: power-led {
+			led-id = "EC_LED_ID_POWER_LED";
+			led-pwms = <&led_power_white>;
+
+			/* Overwrite Power LED white to off */
+			color_power_white: color-power-white {
+				led-color = "LED_WHITE";
+				led-values = <0>;
+			};
+		};
+	};
+
+	batteries {
+		default_battery: smp_c31n1915 {
+			compatible = "smp,c31n1915", "battery-smart";
+		};
+	};
+
+	/* magikarp-specific fw_config fields. */
+	magikarp-fw-config {
+		compatible = "cros-ec,cbi-fw-config";
+		/*
+		 * FW_CONFIG field to describe mainboard orientation in chassis.
+		 */
+		base-gyro {
+			enum-name = "FW_BASE_GYRO";
+			start = <0>;
+			size = <2>;
+
+			None {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_BASE_NONE";
+				value = <0>;
+			};
+			icm42607 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_BASE_ICM42607";
+				value = <1>;
+				default;
+			};
+			bmi323 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_BASE_BMI323";
+				value = <2>;
+			};
+		};
+	};
+};
+
+&adc0 {
+	status = "okay";
+	pinctrl-0 = <&adc0_ch0_gpi0_default
+		     &adc0_ch1_gpi1_default
+		     &adc0_ch2_gpi2_default
+		     &adc0_ch5_gpi5_default
+		     &adc0_ch7_gpi7_default>;
+	pinctrl-names = "default";
+};
+
+&thermistor_3V3_30K9_47K_NCP15WB {
+	status = "okay";
+};
+
+&i2c2 {
+	bc12_port0: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+		irq = <&int_usb_c0_bc12>;
+	};
+	ppc_port0: syv682x@40 {
+		compatible = "silergy,syv682x";
+		status = "okay";
+		reg = <0x40>;
+		frs_en_gpio = <&usb_c0_frs_en>;
+	};
+};
+
+&i2c4 {
+	ps8743_mux_1: ps8743-mux-1@10 {
+		compatible = "parade,ps8743";
+		reg = <0x10>;
+	};
+
+	/delete-node/ tusb1064-mux-1;
+};
diff --git a/zephyr/program/corsola/magikarp/src/keyboard.c b/zephyr/program/corsola/magikarp/src/keyboard.c
new file mode 100644
index 0000000000..bcb706bba3
--- /dev/null
+++ b/zephyr/program/corsola/magikarp/src/keyboard.c
@@ -0,0 +1,29 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+
+static const struct ec_response_keybd_config magikarp_kb_legacy = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &magikarp_kb_legacy;
+}
diff --git a/zephyr/program/corsola/magikarp/src/ppc.c b/zephyr/program/corsola/magikarp/src/ppc.c
new file mode 100644
index 0000000000..9a9f5f1c06
--- /dev/null
+++ b/zephyr/program/corsola/magikarp/src/ppc.c
@@ -0,0 +1,44 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Tentacruel PPC/BC12 (mixed RT1739 or PI3USB9201+SYV682X) configuration */
+
+#include "baseboard_usbc_config.h"
+#include "driver/ppc/syv682x_public.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "usb_charge.h"
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+
+#ifdef CONFIG_PLATFORM_EC_USB_CHARGER
+void bc12_interrupt(enum gpio_signal signal)
+{
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+#endif
+
+static void board_usbc_init(void)
+{
+	/* Enable PPC interrupts. */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_ppc));
+
+#ifdef CONFIG_PLATFORM_EC_USB_CHARGER
+	/* Enable BC1.2 interrupts. */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_bc12));
+#endif
+}
+DECLARE_HOOK(HOOK_INIT, board_usbc_init, HOOK_PRIO_POST_DEFAULT);
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	if (signal == GPIO_SIGNAL(DT_NODELABEL(usb_c0_ppc_int_odl))) {
+		syv682x_interrupt(0);
+	} else if (signal == GPIO_SIGNAL(DT_ALIAS(gpio_usb_c1_ppc_int_odl))) {
+		syv682x_interrupt(1);
+	}
+}
diff --git a/zephyr/program/corsola/magikarp/src/sensor.c b/zephyr/program/corsola/magikarp/src/sensor.c
new file mode 100644
index 0000000000..48e6f6c23c
--- /dev/null
+++ b/zephyr/program/corsola/magikarp/src/sensor.c
@@ -0,0 +1,41 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "accelgyro.h"
+#include "common.h"
+#include "cros_cbi.h"
+#include "driver/accelgyro_bmi323.h"
+#include "driver/accelgyro_icm42607.h"
+#include "hooks.h"
+#include "motionsense_sensors.h"
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	uint32_t val;
+
+	cros_cbi_get_fw_config(FW_BASE_GYRO, &val);
+	if (val == FW_BASE_ICM42607) {
+		icm42607_interrupt(signal);
+	} else if (val == FW_BASE_BMI323) {
+		bmi3xx_interrupt(signal);
+	}
+}
+
+static void motionsense_init(void)
+{
+	uint32_t val;
+
+	cros_cbi_get_fw_config(FW_BASE_GYRO, &val);
+	if (val == FW_BASE_ICM42607) {
+		ccprints("BASE ACCEL is ICM42607");
+	} else if (val == FW_BASE_BMI323) {
+		MOTIONSENSE_ENABLE_ALTERNATE(alt_base_accel);
+		MOTIONSENSE_ENABLE_ALTERNATE(alt_base_gyro);
+		ccprints("BASE ACCEL IS BMI323");
+	} else {
+		ccprints("no motionsense");
+	}
+}
+DECLARE_HOOK(HOOK_INIT, motionsense_init, HOOK_PRIO_DEFAULT);
diff --git a/zephyr/program/corsola/npcx_adc.dtsi b/zephyr/program/corsola/npcx_adc.dtsi
new file mode 100644
index 0000000000..cd6a9c1bef
--- /dev/null
+++ b/zephyr/program/corsola/npcx_adc.dtsi
@@ -0,0 +1,47 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Kingler and Steelix use the same dts, take care of this when modify it.
+ */
+
+
+/ {
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		adc_charger_pmon_r {
+			enum-name = "ADC_PSYS";
+			io-channels = <&adc0 0>;
+			/*
+			 * ISL9238C PSYS output is 1.44 uA/W over 33K resistor.
+			 */
+			mul = <21043>;
+		};
+		adc_ec_id0 {
+			enum-name = "ADC_ID_0";
+			io-channels = <&adc0 1>;
+		};
+		adc_ec_id1 {
+			enum-name = "ADC_ID_1";
+			io-channels = <&adc0 2>;
+		};
+		adc_charger_amon_r {
+			enum-name = "ADC_AMON_BMON";
+			io-channels = <&adc0 3>;
+			mul = <1000>;
+			div = <18>;
+		};
+	};
+};
+
+&adc0 {
+	status = "okay";
+	pinctrl-0 = <&adc0_chan0_gp45
+		     &adc0_chan1_gp44
+		     &adc0_chan2_gp43
+		     &adc0_chan3_gp42>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/corsola/npcx_default_gpio_pinctrl.dtsi b/zephyr/program/corsola/npcx_default_gpio_pinctrl.dtsi
new file mode 100644
index 0000000000..604658a145
--- /dev/null
+++ b/zephyr/program/corsola/npcx_default_gpio_pinctrl.dtsi
@@ -0,0 +1,44 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Adds the &alt1_no_lpc_espi setting over the NPCX9 default setting. */
+&{/def-io-conf-list} {
+	pinmux = <&alt0_gpio_no_spip
+		  &alt0_gpio_no_fpip
+		  &alt1_no_pwrgd
+		  &alt1_no_lpc_espi
+		  &alta_no_peci_en
+		  &altd_npsl_in1_sl
+		  &altd_npsl_in2_sl
+		  &altd_psl_in3_sl
+		  &altd_psl_in4_sl
+		  &alt7_no_ksi0_sl
+		  &alt7_no_ksi1_sl
+		  &alt7_no_ksi2_sl
+		  &alt7_no_ksi3_sl
+		  &alt7_no_ksi4_sl
+		  &alt7_no_ksi5_sl
+		  &alt7_no_ksi6_sl
+		  &alt7_no_ksi7_sl
+		  &alt8_no_kso00_sl
+		  &alt8_no_kso01_sl
+		  &alt8_no_kso02_sl
+		  &alt8_no_kso03_sl
+		  &alt8_no_kso04_sl
+		  &alt8_no_kso05_sl
+		  &alt8_no_kso06_sl
+		  &alt8_no_kso07_sl
+		  &alt9_no_kso08_sl
+		  &alt9_no_kso09_sl
+		  &alt9_no_kso10_sl
+		  &alt9_no_kso11_sl
+		  &alt9_no_kso12_sl
+		  &alt9_no_kso13_sl
+		  &alt9_no_kso14_sl
+		  &alt9_no_kso15_sl
+		  &alta_no_kso16_sl
+		  &alta_no_kso17_sl
+		  &altg_psl_gpo_sl>;
+};
diff --git a/zephyr/program/corsola/npcx_gpio.dtsi b/zephyr/program/corsola/npcx_gpio.dtsi
new file mode 100644
index 0000000000..cd269eeb69
--- /dev/null
+++ b/zephyr/program/corsola/npcx_gpio.dtsi
@@ -0,0 +1,249 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	aliases {
+		gpio-cbi-wp = &gpio_ec_cbi_wp;
+		gpio-wp = &gpio_ec_wp_l;
+		gpio-kbd-kso2 = &gpio_ec_kso_02_inv;
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		/*
+		 * In npcx9 series, gpio46, gpio47, and the whole gpio5 port
+		 * belong to VHIF power well. On kingler, it is connencted to
+		 * 1.8V.
+		 */
+		base_imu_int_l: base_imu_int_l {
+			gpios = <&gpio5 6 GPIO_INPUT>;
+		};
+		spi_ap_clk_ec {
+			gpios = <&gpio5 5 GPIO_INPUT>;
+		};
+		spi_ap_cs_ec_l {
+			gpios = <&gpio5 3 GPIO_INPUT>;
+		};
+		spi_ap_do_ec_di {
+			gpios = <&gpio4 6 GPIO_INPUT>;
+		};
+		spi_ap_di_ec_do {
+			gpios = <&gpio4 7 GPIO_INPUT>;
+		};
+		ap_ec_warm_rst_req: ap_ec_warm_rst_req {
+			gpios = <&gpio5 1 (GPIO_INPUT | GPIO_ACTIVE_HIGH)>;
+			enum-name = "GPIO_AP_EC_WARM_RST_REQ";
+		};
+		ap_ec_wdtrst_l: ap_ec_wdtrst_l {
+			gpios = <&gpio5 2 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_AP_EC_WDTRST_L";
+		};
+		ap_in_sleep_l: ap_in_sleep_l {
+			gpios = <&gpio5 4 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_AP_IN_SLEEP_L";
+		};
+		gpio_en_ulp: en_ulp {
+			gpios = <&gpioc 6 GPIO_OUTPUT_LOW>;
+		};
+		en_ec_id_odl {
+			gpios = <&gpio7 6 GPIO_ODR_HIGH>;
+		};
+		sys_rst_odl {
+			gpios = <&gpioc 5 (GPIO_ODR_LOW | GPIO_VOLTAGE_1P8)>;
+			enum-name = "GPIO_SYS_RST_ODL";
+		};
+		ec_i2c_sensor_scl {
+			gpios = <&gpiob 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		ec_i2c_sensor_sda {
+			gpios = <&gpiob 4 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		ec_i2c_usb_c0_scl {
+			gpios = <&gpio9 0 GPIO_INPUT>;
+		};
+		ec_i2c_usb_c0_sda {
+			gpios = <&gpio8 7 GPIO_INPUT>;
+		};
+		ec_i2c_usb_c1_scl {
+			gpios = <&gpio9 2 GPIO_INPUT>;
+		};
+		ec_i2c_usb_c1_sda {
+			gpios = <&gpio9 1 GPIO_INPUT>;
+		};
+		ec_i2c_pwr_cbi_scl {
+			gpios = <&gpiod 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		ec_i2c_pwr_cbi_sda {
+			gpios = <&gpiod 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		ec_i2c_batt_scl {
+			gpios = <&gpio3 3 GPIO_INPUT>;
+		};
+		ec_i2c_batt_sda {
+			gpios = <&gpio3 6 GPIO_INPUT>;
+		};
+		ec_pen_chg_dis_odl {
+			gpios = <&gpioe 4 GPIO_INPUT>;
+		};
+		gpio_ec_cbi_wp: ec_cbi_wp {
+			gpios = <&gpio8 0 GPIO_OUTPUT_LOW>;
+		};
+		gpio_ec_wp_l: ec_wp_odl {
+			gpios = <&gpioe 3 (GPIO_INPUT | GPIO_ACTIVE_LOW |
+				 GPIO_VOLTAGE_1P8)>;
+		};
+		lid_accel_int_l {
+			gpios = <&gpiob 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		gpio_tablet_mode_l: tablet_mode_l {
+			gpios = <&gpiob 2 GPIO_INPUT>;
+			enum-name = "GPIO_TABLET_MODE_L";
+		};
+		ec_ap_int_odl {
+			gpios = <&gpioc 1 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>;
+			enum-name = "GPIO_EC_INT_L";
+		};
+		gpio_ec_kso_02_inv: ec_kso_02_inv {
+			gpios = <&gpio1 7 (GPIO_OUTPUT_LOW | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_usb_c0_bc12_int_odl: usb_c0_bc12_int_odl {
+			gpios = <&gpio8 3 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C0_BC12_INT_ODL";
+		};
+		ec_entering_rw {
+			gpios = <&gpio0 3 GPIO_OUTPUT_LOW>;
+		};
+		charger_prochot_odl {
+			gpios = <&gpiob 1 GPIO_INPUT>;
+		};
+		ec_rst_odl {
+			gpios = <&gpio7 7 GPIO_INPUT>;
+		};
+		gpio_lid_open: lid_open {
+			gpios = <&gpiod 2 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+		gpio_acok_od: acok_od {
+			gpios = <&gpio0 0 GPIO_INPUT>;
+			enum-name = "GPIO_AC_PRESENT";
+		};
+		gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl {
+			gpios = <&gpio0 1 GPIO_INPUT>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		gpio_en_5v_usm: en_5v_usm {
+			gpios = <&gpio0 2 GPIO_OUTPUT_LOW>;
+		};
+		packet_mode_en {
+			gpios = <&gpio7 5 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_PACKET_MODE_EN";
+		};
+		gpio_x_ec_gpio2: x_ec_gpio2 {
+			gpios = <&gpiod 4 GPIO_INPUT>;
+		};
+		/*
+		 * In npcx9 series, gpio93-97, the whole gpioa port, and gpiob0
+		 * belong to VSPI power rail. On kingler, it is connencted to
+		 * 1.8V.
+		 */
+		ap_sysrst_odl_r: ap_sysrst_odl_r {
+			gpios = <&gpioa 1 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_AP_EC_SYSRST_ODL";
+		};
+		gpio_ap_xhci_init_done: ap_xhci_init_done {
+			gpios = <&gpioa 3 GPIO_INPUT>;
+		};
+		gpio_usb_c0_ppc_int_odl: usb_c0_ppc_int_odl {
+			gpios = <&gpio6 7 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C0_PPC_INT_ODL";
+		};
+		pg_pp5000_z2_od {
+			gpios = <&gpio7 0 GPIO_INPUT>;
+		};
+		gpio_ec_x_gpio1: ec_x_gpio1 {
+			gpios = <&gpio6 2 GPIO_OUTPUT_LOW>;
+		};
+		dp_aux_path_sel: dp_aux_path_sel {
+			gpios = <&gpio6 3 GPIO_OUTPUT_HIGH>;
+		};
+		gpio_ec_bl_en_od: ec_bl_en_od {
+			gpios = <&gpio4 0 (GPIO_ODR_LOW | GPIO_VOLTAGE_1P8)>;
+		};
+		gpio_ec_x_gpio3: ec_x_gpio3 {
+			gpios = <&gpiod 3 GPIO_OUTPUT_LOW>;
+		};
+		gpio_usb_c0_tcpc_int_odl: usb_c0_tcpc_int_odl {
+			gpios = <&gpio7 3 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_USB_C0_TCPC_INT_ODL";
+		};
+		gpio_usb_c0_tcpc_rst: usb_c0_tcpc_rst {
+			gpios = <&gpioc 0 GPIO_OUTPUT_LOW>;
+		};
+		en_pp5000_usb_a0_vbus: en_pp5000_usb_a0_vbus {
+			gpios = <&gpio6 0 GPIO_OUTPUT_LOW>;
+		};
+		gpio_hdmi_prsnt_odl: hdmi_prsnt_odl {
+			gpios = <&gpio3 7 GPIO_INPUT>;
+		};
+		en_pp5000_z2 {
+			gpios = <&gpio3 4 GPIO_OUTPUT_HIGH>;
+		};
+		gpio_usb_c1_tcpc_int_odl: usb_c1_tcpc_int_odl {
+			gpios = <&gpioe 1 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		ec_batt_pres_odl {
+			gpios = <&gpioe 0 GPIO_INPUT>;
+			enum-name = "GPIO_BATT_PRES_ODL";
+		};
+		usb_a0_fault_odl {
+			gpios = <&gpioc 7 GPIO_INPUT>;
+		};
+		ec_ap_dp_hpd_odl: ec_ap_dp_hpd_odl {
+			gpios = <&gpio6 1 GPIO_ODR_HIGH>;
+		};
+		ec_pmic_en_odl {
+			gpios = <&gpio7 4 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>;
+			enum-name = "GPIO_EC_PMIC_EN_ODL";
+		};
+		gpio_ec_volup_btn_odl: ec_volup_btn_odl {
+			gpios = <&gpiod 5 GPIO_INPUT>;
+			enum-name = "GPIO_VOLUME_UP_L";
+		};
+		gpio_ec_voldn_btn_odl: ec_voldn_btn_odl {
+			gpios = <&gpioe 2 GPIO_INPUT>;
+			enum-name = "GPIO_VOLUME_DOWN_L";
+		};
+		gpio_ccd_mode_odl: ccd_mode_odl {
+			gpios = <&gpioe 5 GPIO_INPUT>;
+			enum-name = "GPIO_CCD_MODE_ODL";
+		};
+		/* unimplemented GPIOs */
+		entering-rw {
+			enum-name = "GPIO_ENTERING_RW";
+		};
+	};
+
+	/*
+	 * aliases for sub-board GPIOs
+	 */
+	aliases {
+		gpio-en-hdmi-pwr = &gpio_ec_x_gpio1;
+		gpio-usb-c1-frs-en = &gpio_ec_x_gpio1;
+		gpio-usb-c1-ppc-int-odl = &gpio_x_ec_gpio2;
+		gpio-ps185-ec-dp-hpd = &gpio_x_ec_gpio2;
+		gpio-usb-c1-dp-in-hpd = &gpio_ec_x_gpio3;
+		gpio-ps185-pwrdn-odl = &gpio_ec_x_gpio3;
+	};
+
+	hibernate-wake-pins {
+		compatible = "cros-ec,hibernate-wake-pins";
+		wakeup-irqs = <
+			&int_ac_present
+			&int_power_button
+			&int_lid_open
+		>;
+	};
+};
diff --git a/zephyr/program/corsola/npcx_host_interface.dtsi b/zephyr/program/corsola/npcx_host_interface.dtsi
new file mode 100644
index 0000000000..b691893854
--- /dev/null
+++ b/zephyr/program/corsola/npcx_host_interface.dtsi
@@ -0,0 +1,12 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* host interface */
+&shi0 {
+	status = "okay";
+	pinctrl-0 = <&shi_gp46_47_53_55>;
+	pinctrl-1 = <&shi_gpio_gp46_47_53_55>;
+	pinctrl-names = "default", "sleep";
+};
diff --git a/zephyr/program/corsola/npcx_i2c.dtsi b/zephyr/program/corsola/npcx_i2c.dtsi
new file mode 100644
index 0000000000..f41939fde0
--- /dev/null
+++ b/zephyr/program/corsola/npcx_i2c.dtsi
@@ -0,0 +1,184 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/usb_pd_tcpm.h>
+
+/*
+ * Kingler and Steelix use the same dts, take care of this when modify it.
+ */
+
+/ {
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		i2c_sensor: sensor {
+			i2c-port = <&i2c0_0>;
+			enum-names = "I2C_PORT_SENSOR";
+		};
+		i2c_usb_c0: usb-c0 {
+			i2c-port = <&i2c1_0>;
+			remote-port = <7>;
+			enum-names = "I2C_PORT_USB_C0";
+		};
+		i2c_usb_c1: usb-c1 {
+			i2c-port = <&i2c2_0>;
+			enum-names = "I2C_PORT_USB_C1",
+				"I2C_PORT_USB_C1_TCPC",
+				"I2C_PORT_USB_C1_PPC";
+		};
+		i2c_charger: charger {
+			i2c-port = <&i2c3_0>;
+			enum-names = "I2C_PORT_POWER",
+				"I2C_PORT_EEPROM";
+		};
+		battery {
+			i2c-port = <&i2c5_0>;
+			remote-port = <1>;
+			enum-names = "I2C_PORT_BATTERY",
+				"I2C_PORT_VIRTUAL_BATTERY";
+		};
+	};
+};
+
+&i2c0_0 {
+	label = "I2C_SENSOR";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>;
+	pinctrl-names = "default";
+};
+
+&i2c_ctrl0 {
+	status = "okay";
+};
+
+&i2c1_0 {
+	label = "I2C_USB_C0";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+	pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>;
+	pinctrl-names = "default";
+
+	bc12_port0: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+		irq = <&int_usb_c0_bc12>;
+	};
+
+	tcpc_port0: anx7447-tcpc@2c {
+		compatible = "analogix,anx7447-tcpc";
+		status = "okay";
+		reg = <0x2c>;
+		tcpc-flags = <(
+			TCPC_FLAGS_VBUS_MONITOR |
+			TCPC_FLAGS_ALERT_OD |
+			TCPC_FLAGS_CONTROL_VCONN |
+			TCPC_FLAGS_CONTROL_FRS)>;
+		/* a duplicate of the <&gpio_usb_c0_tcpc_int_odl> node in
+		 * "named-gpios". This is the Zephyr preferred style,
+		 * the "named-gpios" node will be dealt with at a later date.
+		 */
+		irq-gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
+		/* a duplicate of the <&gpio_usb_c0_tcpc_rst> node in
+		 * "named-gpios". This is the Zephyr preferred style,
+		 * the "named-gpios" node will be dealt with at a later date.
+		 */
+		rst-gpios = <&gpioc 0 GPIO_ACTIVE_HIGH>;
+	};
+
+	ppc_port0: nx20p348x@72 {
+		compatible = "nxp,nx20p348x";
+		status = "okay";
+		reg = <0x72>;
+	};
+};
+
+&i2c_ctrl1 {
+	status = "okay";
+};
+
+&i2c2_0 {
+	label = "I2C_USB_C1";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+	pinctrl-0 = <&i2c2_0_sda_scl_gp91_92>;
+	pinctrl-names = "default";
+
+	bc12_port1: rt1718s-bc12@40 {
+		compatible = "richtek,rt1718s-bc12";
+		status = "okay";
+		reg = <0x40>;
+	};
+
+	tcpc_port1: rt1718s-tcpc@40 {
+		compatible = "richtek,rt1718s-tcpc";
+		reg = <0x40>;
+		tcpc-flags = <(
+			TCPC_FLAGS_ALERT_OD |
+			TCPC_FLAGS_CONTROL_VCONN |
+			TCPC_FLAGS_CONTROL_FRS)>;
+		/* a duplicate of the <&gpio_usb_c1_tcpc_int_odl> node in
+		 * "named-gpios". This is the Zephyr preferred style,
+		 * the "named-gpios" node will be dealt with at a later date.
+		 */
+		irq-gpios = <&gpioe 1 GPIO_ACTIVE_LOW>;
+	};
+
+	ppc_port1: nx20p348x@72 {
+		compatible = "nxp,nx20p348x";
+		status = "okay";
+		reg = <0x72>;
+	};
+
+	ps8743_mux_1: ps8743-mux-1@10 {
+		compatible = "parade,ps8743";
+		reg = <0x10>;
+		board-init = "ps8743_mux_1_board_init";
+	};
+};
+
+&i2c_ctrl2 {
+	status = "okay";
+};
+
+&i2c3_0 {
+	label = "I2C_PWR_CBI";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>;
+	pinctrl-names = "default";
+
+	charger: isl923x@9 {
+		compatible = "intersil,isl923x";
+		status = "okay";
+		reg = <0x9>;
+	};
+
+	cbi_eeprom: eeprom@50 {
+		compatible = "atmel,at24";
+		reg = <0x50>;
+		size = <2048>;
+		pagesize = <16>;
+		address-width = <8>;
+		timeout = <5>;
+	};
+};
+
+&i2c_ctrl3 {
+	status = "okay";
+};
+
+&i2c5_0 {
+	label = "I2C_BATTERY";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	pinctrl-0 = <&i2c5_0_sda_scl_gp33_36>;
+	pinctrl-names = "default";
+};
+
+&i2c_ctrl5 {
+	status = "okay";
+};
diff --git a/zephyr/program/corsola/npcx_interrupts.dtsi b/zephyr/program/corsola/npcx_interrupts.dtsi
new file mode 100644
index 0000000000..6262a373d9
--- /dev/null
+++ b/zephyr/program/corsola/npcx_interrupts.dtsi
@@ -0,0 +1,104 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Kingler and Steelix use the same dts, take care of this when modify it.
+ */
+
+/ {
+	aliases {
+		int-wp = &int_wp;
+	};
+
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_power_button: power_button {
+			irq-pin = <&gpio_gsc_ec_pwr_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_button_interrupt";
+		};
+		int_volume_up: volume_up {
+			irq-pin = <&gpio_ec_volup_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+		int_volume_down: volume_down {
+			irq-pin = <&gpio_ec_voldn_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+		int_lid_open: lid_open {
+			irq-pin = <&gpio_lid_open>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "lid_interrupt";
+		};
+		int_warm_rst: warm_rst {
+			irq-pin = <&ap_ec_warm_rst_req>;
+			flags = <GPIO_INT_EDGE_RISING>;
+			handler = "chipset_reset_request_interrupt";
+		};
+		int_ap_in_sleep: ap_in_sleep {
+			irq-pin = <&ap_in_sleep_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_ap_in_rst: ap_in_rst {
+			irq-pin = <&ap_sysrst_odl_r>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "chipset_warm_reset_interrupt";
+		};
+		int_ap_wdtrst: ap_wdtrst {
+			irq-pin = <&ap_ec_wdtrst_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "chipset_watchdog_interrupt";
+		};
+		int_ac_present: ac_present {
+			irq-pin = <&gpio_acok_od>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "extpower_interrupt";
+		};
+		int_xhci: xhci_init_done {
+			irq-pin = <&gpio_ap_xhci_init_done>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "xhci_interrupt";
+		};
+		int_wp: wp {
+			irq-pin = <&gpio_ec_wp_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "switch_interrupt";
+		};
+		int_usb_c0_ppc: usb_c0_ppc {
+			irq-pin = <&gpio_usb_c0_ppc_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "ppc_interrupt";
+		};
+		int_usb_c0_bc12: usb_c0_bc12 {
+			irq-pin = <&gpio_usb_c0_bc12_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "bc12_interrupt";
+		};
+		int_x_ec_gpio2: x_ec_gpio2 {
+			irq-pin = <&gpio_x_ec_gpio2>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "x_ec_interrupt";
+		};
+		int_base_imu: base_imu {
+			irq-pin = <&base_imu_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "bmi3xx_interrupt";
+		};
+		int_tablet_mode: tablet_mode {
+			irq-pin = <&gpio_tablet_mode_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "gmr_tablet_switch_isr";
+		};
+		int_ccd_mode_odl: ccd-mode-odl {
+			irq-pin = <&gpio_ccd_mode_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "ccd_interrupt";
+		};
+	};
+};
diff --git a/zephyr/program/corsola/npcx_keyboard.dtsi b/zephyr/program/corsola/npcx_keyboard.dtsi
new file mode 100644
index 0000000000..5248c4aaff
--- /dev/null
+++ b/zephyr/program/corsola/npcx_keyboard.dtsi
@@ -0,0 +1,34 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+&cros_kb_raw {
+	status = "okay";
+	/* No KSO2 (it's inverted and implemented by GPIO) */
+	pinctrl-0 = <
+		&ksi0_gp31
+		&ksi1_gp30
+		&ksi2_gp27
+		&ksi3_gp26
+		&ksi4_gp25
+		&ksi5_gp24
+		&ksi6_gp23
+		&ksi7_gp22
+		&kso00_gp21
+		&kso01_gp20
+		&kso03_gp16
+		&kso04_gp15
+		&kso05_gp14
+		&kso06_gp13
+		&kso07_gp12
+		&kso08_gp11
+		&kso09_gp10
+		&kso10_gp07
+		&kso11_gp06
+		&kso12_gp05
+		&kso13_gp04
+		&kso14_gp82
+	>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/corsola/npcx_motionsense.dtsi b/zephyr/program/corsola/npcx_motionsense.dtsi
new file mode 100644
index 0000000000..a7f674e01f
--- /dev/null
+++ b/zephyr/program/corsola/npcx_motionsense.dtsi
@@ -0,0 +1,150 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Kingler and Steelix use the same dts, take care of this when modify it.
+ */
+
+#include <dt-bindings/motionsense/utils.h>
+
+/ {
+	aliases {
+		/*
+		 * motion sense's <>_INT_EVENT is handled
+		 * by alias. Using the alias, each driver creates
+		 * its own <>_INT_EVENT.
+		 */
+		bmi3xx-int = &base_accel;
+	};
+
+	/*
+	 * Declare mutexes used by sensor drivers.
+	 * A mutex node is used to create an instance of mutex_t.
+	 * A mutex node is referenced by a sensor node if the
+	 * corresponding sensor driver needs to use the
+	 * instance of the mutex.
+	 */
+	motionsense-mutex {
+		compatible = "cros-ec,motionsense-mutex";
+		lid_mutex: lid-mutex {
+		};
+		base_mutex: base-mutex {
+		};
+	};
+
+	/* Rotation matrix used by drivers. */
+	motionsense-rotation-ref {
+		compatible = "cros-ec,motionsense-rotation-ref";
+		lid_rot_ref: lid-rotation-ref {
+			mat33 = <0 (-1) 0
+				 (-1) 0 0
+				 0 0 (-1)>;
+		};
+		base_rot_ref: base-rotation-ref {
+			mat33 = <0 (-1) 0
+				 1 0 0
+				 0 0 1>;
+		};
+	};
+
+	/*
+	 * Driver specific data. A driver-specific data can be shared with
+	 * different motion sensors while they are using the same driver.
+	 *
+	 * If a node's compatible starts with "cros-ec,accelgyro-", it is for
+	 * a common structure defined in accelgyro.h.
+	 * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for
+	 * "struct als_drv_data_t" in accelgyro.h
+	 */
+	motionsense-sensor-data {
+		bma4xx_data: bma4xx-drv-data {
+			compatible = "cros-ec,drvdata-bma4xx";
+			status = "okay";
+		};
+		bmi3xx_data: bmi3xx-drv-data {
+			compatible = "cros-ec,drvdata-bmi3xx";
+			status = "okay";
+		};
+	};
+
+	/*
+	 * List of motion sensors that creates motion_sensors array.
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
+	 * motion sensor IDs for lid angle calculation.
+	 */
+	motionsense-sensor {
+		lid_accel: lid-accel {
+			compatible = "cros-ec,bma4xx";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&lid_mutex>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&lid_rot_ref>;
+			default-range = <2>;
+			drv-data = <&bma4xx_data>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(12500 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(12500 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_accel: base-accel {
+			compatible = "cros-ec,bmi3xx-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&bmi3xx_data>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(12500 | ROUND_UP_FLAG)>;
+					ec-rate = <(100 * USEC_PER_MSEC)>;
+				};
+				ec-s3 {
+					odr = <(12500 | ROUND_UP_FLAG)>;
+					ec-rate = <0>;
+				};
+			};
+		};
+
+		base_gyro: base-gyro {
+			compatible = "cros-ec,bmi3xx-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&bmi3xx_data>;
+		};
+
+	};
+
+	motionsense-sensor-info {
+		compatible = "cros-ec,motionsense-sensor-info";
+
+		/*
+		 * list of GPIO interrupts that have to
+		 * be enabled at initial stage
+		 */
+		sensor-irqs = <&int_base_imu>;
+		/* list of sensors in force mode */
+		accel-force-mode-sensors = <&lid_accel>;
+	};
+};
diff --git a/zephyr/program/corsola/npcx_program.conf b/zephyr/program/corsola/npcx_program.conf
new file mode 100644
index 0000000000..f19bf5de0a
--- /dev/null
+++ b/zephyr/program/corsola/npcx_program.conf
@@ -0,0 +1,77 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+
+# Bring up options
+CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y
+
+# Debug options and features; can be disabled to save memory or once bringup
+# is complete.
+CONFIG_SHELL_MINIMAL=n
+
+# Charger
+CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y
+CONFIG_PLATFORM_EC_CHARGER_ISL9238C=y
+CONFIG_PLATFORM_EC_CHARGER_PSYS=y
+CONFIG_PLATFORM_EC_CHARGER_PSYS_READ=y
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=20
+CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_ADC_AMON_BMON=y
+
+# PWM
+CONFIG_PWM=y
+
+# LED
+CONFIG_PLATFORM_EC_LED_COMMON=y
+CONFIG_PLATFORM_EC_LED_ONOFF_STATES=y
+
+# Math
+CONFIG_PLATFORM_EC_MATH_UTIL=y
+
+# Power sequencing
+CONFIG_PLATFORM_EC_POWERSEQ_MT8186=y
+CONFIG_PLATFORM_EC_POWERSEQ_S4=n
+
+# Button
+CONFIG_PLATFORM_EC_BUTTONS_RUNTIME_CONFIG=y
+
+# Sensors
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y
+CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y
+CONFIG_PLATFORM_EC_ACCEL_FIFO=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=y
+CONFIG_PLATFORM_EC_GMR_TABLET_MODE=y
+CONFIG_PLATFORM_EC_LID_ANGLE=y
+CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y
+CONFIG_PLATFORM_EC_LID_SWITCH=y
+CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=y
+CONFIG_PLATFORM_EC_TABLET_MODE=y
+CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=y
+
+# USBC
+CONFIG_PLATFORM_EC_BC12_SINGLE_DRIVER=n
+CONFIG_PLATFORM_EC_PD_POWER_SUPPLY_TURN_OFF_DELAY=15000
+CONFIG_PLATFORM_EC_PD_POWER_SUPPLY_TURN_ON_DELAY=15000
+CONFIG_PLATFORM_EC_USBC_PPC=y
+CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y
+CONFIG_PLATFORM_EC_USB_PD_FRS_TCPC=y
+CONFIG_PLATFORM_EC_USB_PD_LOGGING=y
+CONFIG_PLATFORM_EC_USB_PD_DEBUG_FIXED_LEVEL=y
+CONFIG_PLATFORM_EC_USB_PD_DEBUG_LEVEL=2
+CONFIG_PLATFORM_EC_USB_PD_TCPM_ANX7447_AUX_PU_PD=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_SBU=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_BY_BOARD=y
+
+# External power
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
+
+# Keyboard
+CONFIG_CROS_KB_RAW_NPCX_KSO_HIGH_DRIVE=y
+
+CONFIG_SYSCON=y
+
+CONFIG_PLATFORM_EC_BOARD_VERSION_GPIO=n
diff --git a/zephyr/program/corsola/npcx_usbc.dtsi b/zephyr/program/corsola/npcx_usbc.dtsi
new file mode 100644
index 0000000000..18bc6ce303
--- /dev/null
+++ b/zephyr/program/corsola/npcx_usbc.dtsi
@@ -0,0 +1,56 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+			bc12 = <&bc12_port0>;
+			tcpc = <&tcpc_port0>;
+			ppc = <&ppc_port0>;
+			chg = <&charger>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&anx7447_mux_0 &virtual_mux_0>;
+			};
+		};
+
+		port0-muxes {
+			anx7447_mux_0: anx7447-mux-0 {
+				compatible = "analogix,usbc-mux-anx7447";
+			};
+			virtual_mux_0: virtual-mux-0 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+
+		port1@1 {
+			compatible = "named-usbc-port";
+			reg = <1>;
+			bc12 = <&bc12_port1>;
+			tcpc = <&tcpc_port1>;
+			ppc = <&ppc_port1>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&ps8743_mux_1 &virtual_mux_1>;
+			};
+			usb_mux_chain_1_hdmi_db: usb-mux-chain-1-hdmi-db {
+				compatible = "cros-ec,usb-mux-chain";
+				alternative-chain;
+				usb-muxes = <&virtual_mux_1>;
+			};
+		};
+
+		port1-muxes {
+			virtual_mux_1: virtual-mux-1 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+	};
+};
diff --git a/zephyr/program/corsola/power_signal.dtsi b/zephyr/program/corsola/power_signal.dtsi
new file mode 100644
index 0000000000..5037bac228
--- /dev/null
+++ b/zephyr/program/corsola/power_signal.dtsi
@@ -0,0 +1,26 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	power_signal_list: power-signal-list {
+		compatible = "mediatek,mt8186-power-signal-list";
+		ap_in_rst {
+			power-enum-name = "AP_IN_RST";
+			power-gpio-pin = <&ap_sysrst_odl_r>;
+		};
+		ap_in_s3 {
+			power-enum-name = "AP_IN_S3";
+			power-gpio-pin = <&ap_in_sleep_l>;
+		};
+		ap_wdt_asserted {
+			power-enum-name = "AP_WDT_ASSERTED";
+			power-gpio-pin = <&ap_ec_wdtrst_l>;
+		};
+		ap_warm_rst_req {
+			power-enum-name = "AP_WARM_RST_REQ";
+			power-gpio-pin = <&ap_ec_warm_rst_req>;
+		};
+	};
+};
diff --git a/zephyr/program/corsola/program.conf b/zephyr/program/corsola/program.conf
new file mode 100644
index 0000000000..f0af2cfce0
--- /dev/null
+++ b/zephyr/program/corsola/program.conf
@@ -0,0 +1,93 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+
+# http://google3/hardware/standards/usb/
+CONFIG_PLATFORM_EC_USB_PID=0x505C
+
+# CROS EC
+CONFIG_CROS_EC=y
+CONFIG_PLATFORM_EC=y
+CONFIG_PLATFORM_EC_SWITCH=y
+
+# AP SoC configuration
+CONFIG_AP=y
+CONFIG_AP_ARM_MTK_MT8186=y
+
+# Variant config
+CONFIG_VARIANT_CORSOLA_DB_DETECTION=y
+
+# Shell features
+CONFIG_KERNEL_SHELL=y
+CONFIG_SHELL_HELP=y
+CONFIG_SHELL_HISTORY=y
+CONFIG_SHELL_TAB=y
+CONFIG_SHELL_TAB_AUTOCOMPLETION=y
+
+# CBI
+CONFIG_EEPROM=y
+CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=y
+
+# Keyboard
+CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_MKBP=y
+CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED=y
+
+# MKBP
+CONFIG_PLATFORM_EC_MKBP_EVENT=y
+CONFIG_PLATFORM_EC_MKBP_INPUT_DEVICES=y
+CONFIG_PLATFORM_EC_MKBP_USE_GPIO=y
+
+# EFS2
+CONFIG_PLATFORM_EC_VBOOT_EFS2=y
+
+# USB
+CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=n
+CONFIG_PLATFORM_EC_USB_PD_USB32_DRD=n
+CONFIG_PLATFORM_EC_USB_PD_USB4=n
+CONFIG_PLATFORM_EC_USB_PORT_POWER_DUMB_CUSTOM_HOOK=y
+
+# USB-C
+CONFIG_PLATFORM_EC_USBC=y
+CONFIG_PLATFORM_EC_USBC_SS_MUX_DFP_ONLY=y
+CONFIG_PLATFORM_EC_USB_PD_DPS=y
+CONFIG_PLATFORM_EC_USB_PD_DP_HPD_GPIO=y
+CONFIG_PLATFORM_EC_USB_PD_DP_HPD_GPIO_CUSTOM=y
+CONFIG_PLATFORM_EC_USB_PD_FRS=y
+CONFIG_PLATFORM_EC_USB_PD_CLEAR_HARD_RESET_STATUS=y
+
+# Power Seq
+CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK=y
+CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y
+CONFIG_PLATFORM_EC_POWERSEQ=y
+CONFIG_PLATFORM_EC_POWERSEQ_HOST_SLEEP=y
+CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n
+CONFIG_PLATFORM_EC_POWER_SLEEP_FAILURE_DETECTION=y
+
+# Optional features
+CONFIG_FLASH_SHELL=n
+
+# EEPROM
+CONFIG_PLATFORM_EC_EEPROM_CBI_WP=y
+
+# Host Commands
+CONFIG_PLATFORM_EC_HOSTCMD=y
+
+# Battery
+CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y
+CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y
+CONFIG_PLATFORM_EC_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV=9000
+CONFIG_PLATFORM_EC_I2C_PASSTHRU_RESTRICTED=y
+CONFIG_PLATFORM_EC_I2C_VIRTUAL_BATTERY=y
+
+# Charger
+CONFIG_PLATFORM_EC_BC12_CLIENT_MODE_ONLY_PI3USB9201=y
+CONFIG_PLATFORM_EC_CHARGE_MANAGER=y
+# b:257167723: Adapter output current exceeds the spec on heavy-load.
+# Preserve a margin in case of charger overdraw.
+CONFIG_PLATFORM_EC_CHARGER_INPUT_CURRENT_DERATE_PCT=3
+
+# Button
+CONFIG_PLATFORM_EC_CMD_BUTTON=y
+CONFIG_PLATFORM_EC_POWER_BUTTON=y
+CONFIG_PLATFORM_EC_VOLUME_BUTTONS=y
diff --git a/zephyr/program/corsola/src/board.c b/zephyr/program/corsola/src/board.c
new file mode 100644
index 0000000000..45c8bd016c
--- /dev/null
+++ b/zephyr/program/corsola/src/board.c
@@ -0,0 +1,32 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "baseboard_usbc_config.h"
+#include "console.h"
+#include "hooks.h"
+#include "typec_control.h"
+
+#define CPRINTS(format, args...) cprints(CC_USB, format, ##args)
+
+static void ccd_interrupt_deferred(void)
+{
+	/*
+	 * If CCD_MODE_ODL asserts, it means there's a debug accessory connected
+	 * and we should enable the SBU FETs.
+	 */
+	typec_set_sbu(CONFIG_CCD_USBC_PORT_NUMBER, 1);
+
+	/* Mux DP AUX away when CCD enabled to prevent the AUX channel
+	 * interferes the SBU pins.
+	 */
+	CPRINTS("CCD Enabled, mux DP_AUX_PATH_SEL to 1");
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(dp_aux_path_sel), 1);
+}
+DECLARE_DEFERRED(ccd_interrupt_deferred);
+
+void ccd_interrupt(enum gpio_signal signal)
+{
+	hook_call_deferred(&ccd_interrupt_deferred_data, 0);
+}
diff --git a/zephyr/program/corsola/src/board_chipset.c b/zephyr/program/corsola/src/board_chipset.c
new file mode 100644
index 0000000000..6f4585c180
--- /dev/null
+++ b/zephyr/program/corsola/src/board_chipset.c
@@ -0,0 +1,51 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Corsola baseboard-chipset specific configuration */
+
+#include "gpio_signal.h"
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/init.h>
+
+#include <ap_power/ap_power.h>
+
+static void board_backlight_handler(struct ap_power_ev_callback *cb,
+				    struct ap_power_ev_data data)
+{
+	int value;
+
+	switch (data.event) {
+	default:
+		return;
+
+	case AP_POWER_RESUME:
+		/* Called on AP S3 -> S0 transition */
+		value = 1;
+		break;
+
+	case AP_POWER_SUSPEND:
+		/* Called on AP S0 -> S3 transition */
+		value = 0;
+		break;
+	}
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_bl_en_od), value);
+}
+
+static int install_backlight_handler(void)
+{
+	static struct ap_power_ev_callback cb;
+
+	/*
+	 * Add a callback for suspend/resume to
+	 * control the keyboard backlight.
+	 */
+	ap_power_ev_init_callback(&cb, board_backlight_handler,
+				  AP_POWER_RESUME | AP_POWER_SUSPEND);
+	ap_power_ev_add_callback(&cb);
+	return 0;
+}
+
+SYS_INIT(install_backlight_handler, APPLICATION, 1);
diff --git a/zephyr/program/corsola/src/hibernate.c b/zephyr/program/corsola/src/hibernate.c
new file mode 100644
index 0000000000..f0885611cb
--- /dev/null
+++ b/zephyr/program/corsola/src/hibernate.c
@@ -0,0 +1,28 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "charger.h"
+#include "driver/charger/isl923x_public.h"
+#include "system.h"
+
+#include <zephyr/drivers/gpio.h>
+
+/* Corsola board specific hibernate implementation */
+__override void board_hibernate(void)
+{
+#ifdef CONFIG_CHARGER_ISL9238C
+	isl9238c_hibernate(CHARGER_SOLO);
+#endif
+}
+
+__override void board_hibernate_late(void)
+{
+#ifdef CONFIG_CORSOLA_HIBERNATE_PRE_OFF_5V
+	/* b/283037861: Pre-off the 5V power line for hibernate. */
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(en_pp5000_z2), 1);
+	/* It takes around 30ms to release the PP5000 capacitance. */
+	udelay(30 * MSEC);
+#endif
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_en_ulp), 1);
+}
diff --git a/zephyr/program/corsola/src/ite_charger_workaround.c b/zephyr/program/corsola/src/ite_charger_workaround.c
new file mode 100644
index 0000000000..be046a947b
--- /dev/null
+++ b/zephyr/program/corsola/src/ite_charger_workaround.c
@@ -0,0 +1,93 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charger.h"
+#include "driver/charger/rt9490.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "system.h"
+
+#include <zephyr/sys/util.h>
+
+/*
+ * This workaround and the board id checks only apply to krabby and early
+ * tentacruel devices.
+ * Newer project should have all of these fixed.
+ */
+BUILD_ASSERT(IS_ENABLED(CONFIG_BOARD_KRABBY) ||
+	     IS_ENABLED(CONFIG_BOARD_TENTACRUEL) || IS_ENABLED(CONFIG_TEST));
+
+/* b/194967754#comment5: work around for IBUS ADC unstable issue */
+static void ibus_adc_workaround(void)
+{
+	if (system_get_board_version() != 0) {
+		return;
+	}
+
+	i2c_update8(chg_chips[CHARGER_SOLO].i2c_port,
+		    chg_chips[CHARGER_SOLO].i2c_addr_flags,
+		    RT9490_REG_ADC_CHANNEL0, RT9490_VSYS_ADC_DIS, MASK_SET);
+
+	rt9490_enable_hidden_mode(CHARGER_SOLO, true);
+	/* undocumented registers... */
+	i2c_write8(chg_chips[CHARGER_SOLO].i2c_port,
+		   chg_chips[CHARGER_SOLO].i2c_addr_flags, 0x52, 0xC4);
+
+	i2c_update8(chg_chips[CHARGER_SOLO].i2c_port,
+		    chg_chips[CHARGER_SOLO].i2c_addr_flags,
+		    RT9490_REG_ADC_CHANNEL0, RT9490_VSYS_ADC_DIS, MASK_CLR);
+	rt9490_enable_hidden_mode(CHARGER_SOLO, false);
+}
+
+/* b/214880220#comment44: lock i2c at 400khz */
+static void i2c_speed_workaround(void)
+{
+	if (system_get_board_version() >= 3) {
+		return;
+	}
+
+	rt9490_enable_hidden_mode(CHARGER_SOLO, true);
+	/* Set to Auto mode, default run at 400kHz */
+	i2c_write8(chg_chips[CHARGER_SOLO].i2c_port,
+		   chg_chips[CHARGER_SOLO].i2c_addr_flags, 0x71, 0x22);
+	/* Manually select for 400kHz, valid only when 0x71[7] == 1 */
+	i2c_write8(chg_chips[CHARGER_SOLO].i2c_port,
+		   chg_chips[CHARGER_SOLO].i2c_addr_flags, 0xF7, 0x14);
+	rt9490_enable_hidden_mode(CHARGER_SOLO, false);
+}
+
+static void eoc_deglitch_workaround(void)
+{
+	if (system_get_board_version() != 1) {
+		return;
+	}
+
+	/* set end-of-charge deglitch time to 2ms */
+	i2c_update8(chg_chips[CHARGER_SOLO].i2c_port,
+		    chg_chips[CHARGER_SOLO].i2c_addr_flags,
+		    RT9490_REG_ADD_CTRL0, RT9490_TD_EOC, MASK_CLR);
+}
+
+static void disable_safety_timer(void)
+{
+	if (system_get_board_version() >= 2) {
+		return;
+	}
+	/* Disable charge timer */
+	i2c_write8(chg_chips[CHARGER_SOLO].i2c_port,
+		   chg_chips[CHARGER_SOLO].i2c_addr_flags,
+		   RT9490_REG_SAFETY_TMR_CTRL,
+		   RT9490_EN_TRICHG_TMR | RT9490_EN_PRECHG_TMR |
+			   RT9490_EN_FASTCHG_TMR);
+}
+
+static void board_rt9490_workaround(void)
+{
+	ibus_adc_workaround();
+	i2c_speed_workaround();
+	eoc_deglitch_workaround();
+	disable_safety_timer();
+}
+DECLARE_HOOK(HOOK_INIT, board_rt9490_workaround, HOOK_PRIO_DEFAULT);
diff --git a/zephyr/program/corsola/src/ite_hooks.c b/zephyr/program/corsola/src/ite_hooks.c
new file mode 100644
index 0000000000..817c25c0dc
--- /dev/null
+++ b/zephyr/program/corsola/src/ite_hooks.c
@@ -0,0 +1,90 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charger.h"
+#include "driver/charger/rt9490.h"
+#include "extpower.h"
+#include "hooks.h"
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/init.h>
+
+#include <ap_power/ap_power.h>
+
+#define I2C3_NODE DT_NODELABEL(i2c3)
+PINCTRL_DT_DEFINE(I2C3_NODE);
+
+static void board_i2c3_ctrl(bool enable)
+{
+	if (DEVICE_DT_GET(
+		    DT_GPIO_CTLR_BY_IDX(DT_NODELABEL(i2c3), scl_gpios, 0)) ==
+	    DEVICE_DT_GET(DT_NODELABEL(gpiof))) {
+		const struct pinctrl_dev_config *pcfg =
+			PINCTRL_DT_DEV_CONFIG_GET(I2C3_NODE);
+
+		if (enable) {
+			pinctrl_apply_state(pcfg, PINCTRL_STATE_DEFAULT);
+		} else {
+			pinctrl_apply_state(pcfg, PINCTRL_STATE_SLEEP);
+		}
+	}
+}
+
+static void board_enable_i2c3(void)
+{
+	board_i2c3_ctrl(1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_PRE_INIT, board_enable_i2c3, HOOK_PRIO_FIRST);
+
+static void board_disable_i2c3(void)
+{
+	board_i2c3_ctrl(0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_HARD_OFF, board_disable_i2c3, HOOK_PRIO_LAST);
+
+static void board_suspend_handler(struct ap_power_ev_callback *cb,
+				  struct ap_power_ev_data data)
+{
+	int value;
+
+	switch (data.event) {
+	default:
+		return;
+
+	case AP_POWER_RESUME:
+		value = 1;
+		break;
+
+	case AP_POWER_SUSPEND:
+		value = 0;
+		break;
+	}
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_en_5v_usm), value);
+}
+
+static int install_suspend_handler(void)
+{
+	static struct ap_power_ev_callback cb;
+
+	/*
+	 * Add a callback for suspend/resume.
+	 */
+	ap_power_ev_init_callback(&cb, board_suspend_handler,
+				  AP_POWER_RESUME | AP_POWER_SUSPEND);
+	ap_power_ev_add_callback(&cb);
+	return 0;
+}
+
+SYS_INIT(install_suspend_handler, APPLICATION, 1);
+
+static void board_hook_ac_change(void)
+{
+	if (system_get_board_version() >= 1) {
+		rt9490_enable_adc(CHARGER_SOLO, extpower_is_present());
+	}
+}
+DECLARE_HOOK(HOOK_AC_CHANGE, board_hook_ac_change, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_INIT, board_hook_ac_change, HOOK_PRIO_LAST);
diff --git a/zephyr/program/corsola/src/ite_i2c.c b/zephyr/program/corsola/src/ite_i2c.c
new file mode 100644
index 0000000000..66b88b09b0
--- /dev/null
+++ b/zephyr/program/corsola/src/ite_i2c.c
@@ -0,0 +1,19 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "i2c.h"
+#include "i2c/i2c.h"
+
+/* Krabby board specific i2c implementation */
+
+#ifdef CONFIG_PLATFORM_EC_I2C_PASSTHRU_RESTRICTED
+int board_allow_i2c_passthru(const struct i2c_cmd_desc_t *cmd_desc)
+{
+	return (i2c_get_device_for_port(cmd_desc->port) ==
+			i2c_get_device_for_port(I2C_PORT_VIRTUAL_BATTERY) ||
+		i2c_get_device_for_port(cmd_desc->port) ==
+			i2c_get_device_for_port(I2C_PORT_EEPROM));
+}
+#endif
diff --git a/zephyr/program/corsola/src/ite_usb_pd_policy.c b/zephyr/program/corsola/src/ite_usb_pd_policy.c
new file mode 100644
index 0000000000..a15a778672
--- /dev/null
+++ b/zephyr/program/corsola/src/ite_usb_pd_policy.c
@@ -0,0 +1,47 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc.h"
+#include "charge_manager.h"
+#include "usb_charge.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+
+int pd_snk_is_vbus_provided(int port)
+{
+#ifdef CONFIG_PLATFORM_EC_USB_CHARGER
+	static atomic_t vbus_prev[CONFIG_USB_PD_PORT_MAX_COUNT];
+#endif
+	int vbus;
+
+	/*
+	 * (b:181203590#comment20) TODO(yllin): use
+	 *  PD_VSINK_DISCONNECT_PD for non-5V case.
+	 */
+	vbus = adc_read_channel(board_get_vbus_adc(port)) >=
+	       PD_V_SINK_DISCONNECT_MAX;
+
+#ifdef CONFIG_PLATFORM_EC_USB_CHARGER
+	/*
+	 * There's no PPC to inform VBUS change for usb_charger, so inform
+	 * the usb_charger now.
+	 */
+	if (!!(vbus_prev[port] != vbus)) {
+		usb_charger_vbus_change(port, vbus);
+	}
+
+	if (vbus) {
+		atomic_or(&vbus_prev[port], 1);
+	} else {
+		atomic_clear(&vbus_prev[port]);
+	}
+#endif
+	return vbus;
+}
+
+int board_vbus_source_enabled(int port)
+{
+	return ppc_is_sourcing_vbus(port);
+}
diff --git a/zephyr/program/corsola/src/ite_usbc.c b/zephyr/program/corsola/src/ite_usbc.c
new file mode 100644
index 0000000000..395cafcc01
--- /dev/null
+++ b/zephyr/program/corsola/src/ite_usbc.c
@@ -0,0 +1,138 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Krabby board-specific USB-C configuration */
+
+#include "charge_manager.h"
+#include "console.h"
+#include "driver/tcpm/it83xx_pd.h"
+#include "driver/usb_mux/tusb1064.h"
+#include "i2c.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+#include "variant_db_detection.h"
+#include "zephyr_adc.h"
+
+#include <zephyr/sys/util_macro.h>
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+
+#define ITE_CC_PARAMETER(i, _)                                    \
+	{                                                         \
+		.rising_time = IT83XX_TX_PRE_DRIVING_TIME_1_UNIT, \
+		.falling_time = IT83XX_TX_PRE_DRIVING_TIME_2_UNIT \
+	}
+
+int tusb1064_mux_1_board_init(const struct usb_mux *me)
+{
+	int rv;
+
+	rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
+			TUSB1064_REG_DP1DP3EQ_SEL,
+			TUSB1064_DP1EQ(TUSB1064_DP_EQ_RX_8_9_DB) |
+				TUSB1064_DP3EQ(TUSB1064_DP_EQ_RX_5_4_DB));
+	if (rv)
+		return rv;
+
+	/* Enable EQ_OVERRIDE so the gain registers are used */
+	return i2c_update8(me->i2c_port, me->i2c_addr_flags,
+			   TUSB1064_REG_GENERAL, REG_GENERAL_EQ_OVERRIDE,
+			   MASK_SET);
+}
+
+#ifdef CONFIG_USB_PD_TCPM_ITE_ON_CHIP
+const struct cc_para_t *board_get_cc_tuning_parameter(enum usbpd_port port)
+{
+	const static struct cc_para_t
+		cc_parameter[CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT] = { LISTIFY(
+			CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT, ITE_CC_PARAMETER,
+			(, )) };
+
+	return &cc_parameter[port];
+}
+#endif
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * C0 & C1: TCPC is embedded in the EC and processes interrupts in the
+	 * chip code (it83xx/intc.c)
+	 */
+}
+
+int board_set_active_charge_port(int port)
+{
+	int i;
+	int is_valid_port =
+		(port >= 0 && port < board_get_adjusted_usb_pd_port_count());
+	/* adjust the actual port count when not the type-c db connected. */
+
+	if (!is_valid_port && port != CHARGE_PORT_NONE) {
+		return EC_ERROR_INVAL;
+	}
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTS("Disabling all charger ports");
+
+		/* Disable all ports. */
+		for (i = 0; i < board_get_adjusted_usb_pd_port_count(); i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (ppc_vbus_sink_enable(i, 0)) {
+				CPRINTS("Disabling C%d as sink failed.", i);
+			}
+		}
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (ppc_is_sourcing_vbus(port)) {
+		CPRINTS("Skip enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTS("New charge port: C%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < board_get_adjusted_usb_pd_port_count(); i++) {
+		if (i == port) {
+			continue;
+		}
+
+		if (ppc_vbus_sink_enable(i, 0)) {
+			CPRINTS("C%d: sink path disable failed.", i);
+		}
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTS("C%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+#ifdef CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT
+enum adc_channel board_get_vbus_adc(int port)
+{
+	if (port == 0) {
+		return ADC_VBUS_C0;
+	}
+	if (port == 1) {
+		return ADC_VBUS_C1;
+	}
+	CPRINTSUSB("Unknown vbus adc port id: %d", port);
+	return ADC_VBUS_C0;
+}
+#endif /* CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT */
diff --git a/zephyr/program/corsola/src/npcx_i2c.c b/zephyr/program/corsola/src/npcx_i2c.c
new file mode 100644
index 0000000000..5bd8aef7d5
--- /dev/null
+++ b/zephyr/program/corsola/src/npcx_i2c.c
@@ -0,0 +1,21 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "i2c.h"
+#include "i2c/i2c.h"
+
+/* Kingler and Steelix board specific i2c implementation */
+
+#ifdef CONFIG_PLATFORM_EC_I2C_PASSTHRU_RESTRICTED
+int board_allow_i2c_passthru(const struct i2c_cmd_desc_t *cmd_desc)
+{
+	return (i2c_get_device_for_port(cmd_desc->port) ==
+			i2c_get_device_for_port(I2C_PORT_VIRTUAL_BATTERY) ||
+		i2c_get_device_for_port(cmd_desc->port) ==
+			i2c_get_device_for_port(I2C_PORT_EEPROM) ||
+		i2c_get_device_for_port(cmd_desc->port) ==
+			i2c_get_device_for_port(I2C_PORT_USB_C0));
+}
+#endif
diff --git a/zephyr/program/corsola/src/npcx_usb_pd_policy.c b/zephyr/program/corsola/src/npcx_usb_pd_policy.c
new file mode 100644
index 0000000000..39c780bddd
--- /dev/null
+++ b/zephyr/program/corsola/src/npcx_usb_pd_policy.c
@@ -0,0 +1,19 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "baseboard_usbc_config.h"
+#include "driver/tcpm/rt1718s.h"
+#include "driver/tcpm/tcpm.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+int pd_snk_is_vbus_provided(int port)
+{
+	/* TODO: use ADC? */
+	return tcpm_check_vbus_level(port, VBUS_PRESENT);
+}
diff --git a/zephyr/program/corsola/src/npcx_usbc.c b/zephyr/program/corsola/src/npcx_usbc.c
new file mode 100644
index 0000000000..e1fac32a41
--- /dev/null
+++ b/zephyr/program/corsola/src/npcx_usbc.c
@@ -0,0 +1,308 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Kingler board-specific USB-C configuration */
+
+/* TODO(b/220196310): Create GPIO driver for RT17181S TCPC */
+#ifdef __REQUIRE_ZEPHYR_GPIOS__
+#undef __REQUIRE_ZEPHYR_GPIOS__
+#endif
+
+#include "baseboard_usbc_config.h"
+#include "battery.h"
+#include "console.h"
+#include "driver/ppc/nx20p348x.h"
+#include "driver/tcpm/anx7447.h"
+#include "driver/tcpm/rt1718s.h"
+#include "driver/usb_mux/ps8743_public.h"
+#include "gpio.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "timer.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_ppc.h"
+#include "variant_db_detection.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+
+/* USB Mux */
+
+/* USB Mux C1 : board_init of PS8743 */
+int ps8743_mux_1_board_init(const struct usb_mux *me)
+{
+	ps8743_tune_usb_eq(me, PS8743_USB_EQ_TX_3_6_DB,
+			   PS8743_USB_EQ_RX_16_0_DB);
+
+	return EC_SUCCESS;
+}
+
+void board_usb_mux_init(void)
+{
+	if (corsola_get_db_type() == CORSOLA_DB_TYPEC) {
+		/* Disable DCI function. This is not needed for ARM. */
+		ps8743_field_update(usb_muxes[1].mux, PS8743_REG_DCI_CONFIG_2,
+				    PS8743_AUTO_DCI_MODE_MASK,
+				    PS8743_AUTO_DCI_MODE_FORCE_USB);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, board_usb_mux_init, HOOK_PRIO_INIT_I2C + 1);
+
+void board_tcpc_init(void)
+{
+	/* Reset TCPC if we only we have a battery connected, or the SINK
+	 * gpio to the PPC might be reset and cause brown-out.
+	 */
+	if (!system_jumped_late() && battery_is_present() == BP_YES) {
+		/* TODO(crosbug.com/p/61098): How long do we need to wait? */
+		board_reset_pd_mcu();
+	}
+
+#if CONFIG_USB_PD_PORT_MAX_COUNT > 1
+	/* Do not enable TCPC interrupt on port 1 if not type-c */
+	if (corsola_get_db_type() != CORSOLA_DB_TYPEC) {
+		tcpc_config[USBC_PORT_C1].irq_gpio.port = NULL;
+	}
+#endif /* CONFIG_USB_PD_PORT_MAX_COUNT > 1 */
+
+#ifdef CONFIG_PLATFORM_EC_USB_CHARGER
+	/* Enable BC1.2 interrupts. */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_bc12));
+#endif
+
+	/*
+	 * Initialize HPD to low; after sysjump SOC needs to see
+	 * HPD pulse to enable video path
+	 */
+	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) {
+		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_POST_I2C);
+
+__override int board_rt1718s_init(int port)
+{
+	static bool gpio_initialized;
+
+	/* Reset TCPC sink/source control when it's a power-on reset or has a
+	 * battery. Do not alter the carried GPIO status or this might stop PPC
+	 * sinking and brown-out the system when battery disconnected.
+	 */
+	if (!system_jumped_late() && !gpio_initialized &&
+	    (battery_is_present() == BP_YES ||
+	     (system_get_reset_flags() & EC_RESET_FLAG_POWER_ON))) {
+		/* set GPIO 1~3 as push pull, as output, output low. */
+		rt1718s_gpio_set_flags(port, RT1718S_GPIO1, GPIO_OUT_LOW);
+		rt1718s_gpio_set_flags(port, RT1718S_GPIO2, GPIO_OUT_LOW);
+		rt1718s_gpio_set_flags(port, RT1718S_GPIO3, GPIO_OUT_LOW);
+		gpio_initialized = true;
+	}
+
+	/* gpio1 low, gpio2 output high when receiving frs signal */
+	RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_GPIO1_VBUS_CTRL,
+					  RT1718S_GPIO_VBUS_CTRL_FRS_RX_VBUS,
+					  0));
+	/* GPIO1 EN_SNK high when received TCPCI SNK enabled command */
+	RETURN_ERROR(rt1718s_update_bits8(
+		port, RT1718S_GPIO1_VBUS_CTRL,
+		RT1718S_GPIO_VBUS_CTRL_ENA_SNK_VBUS_GPIO, 0xFF));
+	/* GPIO2 EN_SRC high when received TCPCI SRC enabled command */
+	RETURN_ERROR(rt1718s_update_bits8(
+		port, RT1718S_GPIO2_VBUS_CTRL,
+		RT1718S_GPIO_VBUS_CTRL_FRS_RX_VBUS |
+			RT1718S_GPIO_VBUS_CTRL_ENA_SRC_VBUS_GPIO,
+		0xFF));
+
+	/* Trigger GPIO 1/2 change when FRS signal received */
+	RETURN_ERROR(rt1718s_update_bits8(
+		port, RT1718S_FRS_CTRL3,
+		RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO2 |
+			RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO1,
+		RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO2 |
+			RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO1));
+	/* Set FRS signal detect time to 46.875us */
+	RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_FRS_CTRL1,
+					  RT1718S_FRS_CTRL1_FRSWAPRX_MASK,
+					  0xFF));
+
+	/* Disable BC1.2 SRC mode */
+	RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_RT2_BC12_SRC_FUNC,
+					  RT1718S_RT2_BC12_SRC_FUNC_BC12_SRC_EN,
+					  0));
+
+	return EC_SUCCESS;
+}
+
+#if CONFIG_USB_PD_PORT_MAX_COUNT > 1
+__override int board_rt1718s_set_frs_enable(int port, int enable)
+{
+	if (port == USBC_PORT_C1)
+		/*
+		 * Use set_flags (implemented by a single i2c write) instead
+		 * of set_level (= i2c_update) to save one read operation in
+		 * FRS path.
+		 */
+		rt1718s_gpio_set_flags(port, GPIO_EN_USB_C1_FRS,
+				       enable ? GPIO_OUT_HIGH : GPIO_OUT_LOW);
+	return EC_SUCCESS;
+}
+#endif /* CONFIG_USB_PD_PORT_MAX_COUNT > 1 */
+
+void board_reset_pd_mcu(void)
+{
+	CPRINTS("Resetting TCPCs...");
+	/* reset C0 ANX3447 */
+	/* Assert reset */
+	gpio_pin_set_dt(&tcpc_config[0].rst_gpio, 1);
+	msleep(1);
+	gpio_pin_set_dt(&tcpc_config[0].rst_gpio, 0);
+	/* After TEST_R release, anx7447/3447 needs 2ms to finish eFuse
+	 * loading.
+	 */
+	msleep(2);
+
+#if CONFIG_USB_PD_PORT_MAX_COUNT > 1
+	/* reset C1 RT1718s */
+	rt1718s_sw_reset(USBC_PORT_C1);
+#endif /* CONFIG_USB_PD_PORT_MAX_COUNT > 1 */
+}
+
+/* Used by Vbus discharge common code with CONFIG_USB_PD_DISCHARGE */
+int board_vbus_source_enabled(int port)
+{
+	return ppc_is_sourcing_vbus(port);
+}
+
+#if CONFIG_USB_PD_PORT_MAX_COUNT > 1
+__override int board_rt1718s_set_snk_enable(int port, int enable)
+{
+	rt1718s_gpio_set_level(port, GPIO_EN_USB_C1_SINK, enable);
+
+	return EC_SUCCESS;
+}
+__override int board_rt1718s_set_src_enable(int port, int enable)
+{
+	rt1718s_gpio_set_level(port, GPIO_EN_USB_C1_SOURCE, enable);
+
+	return EC_SUCCESS;
+}
+#endif /* CONFIG_USB_PD_PORT_MAX_COUNT > 1 */
+
+int board_set_active_charge_port(int port)
+{
+	int i;
+	bool is_valid_port =
+		(port >= 0 && port < board_get_adjusted_usb_pd_port_count());
+	/* adjust the actual port count when not the type-c db connected. */
+
+	if (!is_valid_port && port != CHARGE_PORT_NONE) {
+		return EC_ERROR_INVAL;
+	}
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTS("Disabling all charger ports");
+
+		/* Disable all ports. */
+		for (i = 0; i < board_get_adjusted_usb_pd_port_count(); i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (ppc_vbus_sink_enable(i, 0)) {
+				CPRINTS("Disabling C%d as sink failed.", i);
+			}
+		}
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (ppc_is_sourcing_vbus(port)) {
+		CPRINTS("Skip enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTS("New charge port: C%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < board_get_adjusted_usb_pd_port_count(); i++) {
+		if (i == port) {
+			continue;
+		}
+
+		if (ppc_vbus_sink_enable(i, 0)) {
+			CPRINTS("C%d: sink path disable failed.", i);
+		}
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTS("C%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_SIGNAL(DT_NODELABEL(gpio_usb_c0_ppc_int_odl)):
+		ppc_chips[0].drv->interrupt(0);
+		break;
+	case GPIO_SIGNAL(DT_ALIAS(gpio_usb_c1_ppc_int_odl)):
+		ppc_chips[1].drv->interrupt(1);
+		break;
+	default:
+		break;
+	}
+}
+
+#ifdef CONFIG_PLATFORM_EC_USB_CHARGER
+void bc12_interrupt(enum gpio_signal signal)
+{
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+#endif
+
+__override int board_get_vbus_voltage(int port)
+{
+	int voltage = 0;
+	int rv;
+
+	switch (port) {
+	case USBC_PORT_C0:
+		rv = tcpc_config[USBC_PORT_C0].drv->get_vbus_voltage(port,
+								     &voltage);
+		if (rv)
+			return 0;
+		break;
+#if CONFIG_USB_PD_PORT_MAX_COUNT > 1
+	case USBC_PORT_C1:
+		rt1718s_get_adc(port, RT1718S_ADC_VBUS1, &voltage);
+		break;
+#endif /* CONFIG_USB_PD_PORT_MAX_COUNT > 1 */
+	default:
+		return 0;
+	}
+	return voltage;
+}
+
+__override int board_nx20p348x_init(int port)
+{
+	int rv;
+
+	rv = i2c_update8(ppc_chips[port].i2c_port,
+			 ppc_chips[port].i2c_addr_flags,
+			 NX20P348X_DEVICE_CONTROL_REG, NX20P348X_CTRL_LDO_SD,
+			 MASK_SET);
+	return rv;
+}
diff --git a/zephyr/program/corsola/src/usb_pd_policy.c b/zephyr/program/corsola/src/usb_pd_policy.c
new file mode 100644
index 0000000000..4b7e46cb74
--- /dev/null
+++ b/zephyr/program/corsola/src/usb_pd_policy.c
@@ -0,0 +1,257 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "baseboard_usbc_config.h"
+#include "chipset.h"
+#include "console.h"
+#include "driver/tcpm/rt1718s.h"
+#include "hooks.h"
+#include "timer.h"
+#include "typec_control.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+
+static int active_aux_port = -1;
+
+int pd_check_vconn_swap(int port)
+{
+	/* Allow Vconn swap if AP is on. */
+	return chipset_in_state(CHIPSET_STATE_SUSPEND | CHIPSET_STATE_ON);
+}
+
+static void set_dp_aux_path_sel(int port)
+{
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(dp_aux_path_sel), port);
+	CPRINTS("Set DP_AUX_PATH_SEL: %d", port);
+}
+
+int svdm_get_hpd_gpio(int port)
+{
+	/* HPD is low active, inverse the result */
+	return !gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(ec_ap_dp_hpd_odl));
+}
+
+static void reset_aux_deferred(void)
+{
+	if (active_aux_port == -1)
+		/* reset to 1 for lower power consumption. */
+		set_dp_aux_path_sel(1);
+}
+DECLARE_DEFERRED(reset_aux_deferred);
+
+void svdm_set_hpd_gpio(int port, int en)
+{
+	/*
+	 * HPD is low active, inverse the en.
+	 *
+	 * Implement FCFS policy:
+	 * 1) Enable hpd if no active port.
+	 * 2) Disable hpd if active port is the given port.
+	 */
+	if (en && active_aux_port < 0) {
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(ec_ap_dp_hpd_odl), 0);
+		active_aux_port = port;
+		hook_call_deferred(&reset_aux_deferred_data, -1);
+	}
+
+	if (!en && active_aux_port == port) {
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(ec_ap_dp_hpd_odl), 1);
+		active_aux_port = -1;
+		/*
+		 * This might be a HPD debounce to send a HPD IRQ (500us), so
+		 * do not reset the aux path immediately. Defer this call and
+		 * re-check if this is a real disable.
+		 */
+		hook_call_deferred(&reset_aux_deferred_data, 1 * MSEC);
+	}
+}
+
+__override int svdm_dp_config(int port, uint32_t *payload)
+{
+	int opos = pd_alt_mode(port, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT);
+	uint8_t pin_mode = get_dp_pin_mode(port);
+	mux_state_t mux_mode = svdm_dp_get_mux_mode(port);
+	int mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]);
+
+	if (!pin_mode) {
+		return 0;
+	}
+
+	CPRINTS("pin_mode: %x, mf: %d, mux: %d", pin_mode, mf_pref, mux_mode);
+	/*
+	 * Defer setting the usb_mux until HPD goes high, svdm_dp_attention().
+	 * The AP only supports one DP phy. An external DP mux switches between
+	 * the two ports. Should switch those muxes when it is really used,
+	 * i.e. HPD high; otherwise, the real use case is preempted, like:
+	 *  (1) plug a dongle without monitor connected to port-0,
+	 *  (2) plug a dongle without monitor connected to port-1,
+	 *  (3) plug a monitor to the port-1 dongle.
+	 */
+
+	payload[0] =
+		VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_CONFIG | VDO_OPOS(opos));
+	payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */
+				1, /* DPv1.3 signaling */
+				2); /* UFP connected */
+	return 2;
+};
+
+__override void svdm_dp_post_config(int port)
+{
+	mux_state_t mux_mode = svdm_dp_get_mux_mode(port);
+
+	typec_set_sbu(port, true);
+
+	/*
+	 * Prior to post-config, the mux will be reset to safe mode, and this
+	 * will break mux config and aux path config we did in the first DP
+	 * status command. Only enable this if the port is the current aux-port.
+	 */
+	if (port == active_aux_port) {
+		usb_mux_set(port, mux_mode, USB_SWITCH_CONNECT,
+			    polarity_rm_dts(pd_get_polarity(port)));
+		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+	}
+
+	dp_flags[port] |= DP_FLAGS_DP_ON;
+}
+
+int corsola_is_dp_muxable(int port)
+{
+	int i;
+
+	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+		if (i != port) {
+			if (usb_mux_get(i) & USB_PD_MUX_DP_ENABLED) {
+				return 0;
+			}
+		}
+	}
+
+	return 1;
+}
+
+__override int svdm_dp_attention(int port, uint32_t *payload)
+{
+	int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]);
+	int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]);
+#ifdef CONFIG_USB_PD_DP_HPD_GPIO
+	int cur_lvl = svdm_get_hpd_gpio(port);
+#endif /* CONFIG_USB_PD_DP_HPD_GPIO */
+	mux_state_t mux_state;
+
+	dp_status[port] = payload[1];
+
+	if (!corsola_is_dp_muxable(port)) {
+		/* TODO(waihong): Info user? */
+		CPRINTS("p%d: The other port is already muxed.", port);
+		return 0; /* nak */
+	}
+
+	if (lvl) {
+		set_dp_aux_path_sel(port);
+
+		usb_mux_set(port, USB_PD_MUX_DOCK, USB_SWITCH_CONNECT,
+			    polarity_rm_dts(pd_get_polarity(port)));
+	} else {
+		usb_mux_set(port, USB_PD_MUX_USB_ENABLED, USB_SWITCH_CONNECT,
+			    polarity_rm_dts(pd_get_polarity(port)));
+	}
+
+	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && (irq || lvl)) {
+		/*
+		 * Wake up the AP.  IRQ or level high indicates a DP sink is now
+		 * present.
+		 */
+		if (IS_ENABLED(CONFIG_MKBP_EVENT)) {
+			pd_notify_dp_alt_mode_entry(port);
+		}
+	}
+
+#ifdef CONFIG_USB_PD_DP_HPD_GPIO
+	if (irq && !lvl) {
+		/*
+		 * IRQ can only be generated when the level is high, because
+		 * the IRQ is signaled by a short low pulse from the high level.
+		 */
+		CPRINTF("ERR:HPD:IRQ&LOW\n");
+		return 0; /* nak */
+	}
+
+	if (irq && cur_lvl) {
+		uint64_t now = get_time().val;
+		/* wait for the minimum spacing between IRQ_HPD if needed */
+		if (now < svdm_hpd_deadline[port]) {
+			usleep(svdm_hpd_deadline[port] - now);
+		}
+
+		/* generate IRQ_HPD pulse */
+		svdm_set_hpd_gpio(port, 0);
+		/*
+		 * b/171172053#comment14: since the HPD_DSTREAM_DEBOUNCE_IRQ is
+		 * very short (500us), we can use udelay instead of usleep for
+		 * more stable pulse period.
+		 */
+		udelay(HPD_DSTREAM_DEBOUNCE_IRQ);
+		svdm_set_hpd_gpio(port, 1);
+	} else {
+		svdm_set_hpd_gpio(port, lvl);
+	}
+
+	/* set the minimum time delay (2ms) for the next HPD IRQ */
+	svdm_hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
+#endif /* CONFIG_USB_PD_DP_HPD_GPIO */
+
+	mux_state = (lvl ? USB_PD_MUX_HPD_LVL : USB_PD_MUX_HPD_LVL_DEASSERTED) |
+		    (irq ? USB_PD_MUX_HPD_IRQ : USB_PD_MUX_HPD_IRQ_DEASSERTED);
+	usb_mux_hpd_update(port, mux_state);
+
+#ifdef USB_PD_PORT_TCPC_MST
+	if (port == USB_PD_PORT_TCPC_MST) {
+		baseboard_mst_enable_control(port, lvl);
+	}
+#endif
+
+	/* ack */
+	return 1;
+}
+
+void pd_power_supply_reset(int port)
+{
+	int prev_en;
+
+	prev_en = ppc_is_sourcing_vbus(port);
+
+	/* Disable VBUS. */
+	ppc_vbus_source_enable(port, 0);
+
+	/* Enable discharge if we were previously sourcing 5V */
+	if (prev_en) {
+		pd_set_vbus_discharge(port, 1);
+	}
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	/* Disable charging. */
+	RETURN_ERROR(ppc_vbus_sink_enable(port, 0));
+
+	pd_set_vbus_discharge(port, 0);
+
+	RETURN_ERROR(ppc_vbus_source_enable(port, 1));
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
diff --git a/zephyr/program/corsola/src/usbc.c b/zephyr/program/corsola/src/usbc.c
new file mode 100644
index 0000000000..bb7ba61f1e
--- /dev/null
+++ b/zephyr/program/corsola/src/usbc.c
@@ -0,0 +1,248 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Corsola baseboard-specific USB-C configuration */
+
+#include "baseboard_usbc_config.h"
+#include "charge_state.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "extpower.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd_tcpm.h"
+#include "usb_tc_sm.h"
+#include "usbc/usb_muxes.h"
+#include "usbc_ppc.h"
+#include "variant_db_detection.h"
+
+#include <zephyr/drivers/gpio.h>
+
+#include <ap_power/ap_power.h>
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+
+/* a flag for indicating the tasks are inited. */
+static bool tasks_inited;
+
+/* Baseboard */
+static void baseboard_init(void)
+{
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_xhci));
+
+	/* If CCD mode has enabled before init, force the ccd_interrupt. */
+	if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_ccd_mode_odl))) {
+		ccd_interrupt(GPIO_CCD_MODE_ODL);
+	}
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_ccd_mode_odl));
+}
+DECLARE_HOOK(HOOK_INIT, baseboard_init, HOOK_PRIO_PRE_DEFAULT);
+
+__override uint8_t board_get_usb_pd_port_count(void)
+{
+	/* This function returns the PORT_COUNT when HDMI db is connected.
+	 * This is a trick to ensure the usb_mux_set being set properley.
+	 * HDMI display functions using the USB virtual mux to * communicate
+	 * with the DP bridge.
+	 */
+	if (corsola_get_db_type() == CORSOLA_DB_HDMI) {
+		if (tasks_inited) {
+			return CONFIG_USB_PD_PORT_MAX_COUNT;
+		} else {
+			return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
+		}
+	} else if (corsola_get_db_type() == CORSOLA_DB_NONE) {
+		return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
+	}
+
+	return CONFIG_USB_PD_PORT_MAX_COUNT;
+}
+
+uint8_t board_get_adjusted_usb_pd_port_count(void)
+{
+	const enum corsola_db_type db = corsola_get_db_type();
+
+	if (db == CORSOLA_DB_TYPEC || db == CORSOLA_DB_NO_DETECTION) {
+		return CONFIG_USB_PD_PORT_MAX_COUNT;
+	} else {
+		return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
+	}
+}
+
+/* USB-A */
+void xhci_interrupt(enum gpio_signal signal)
+{
+	const int xhci_stat = gpio_get_level(signal);
+
+#ifdef USB_PORT_ENABLE_COUNT
+	enum usb_charge_mode mode = gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(
+					    gpio_ap_xhci_init_done)) ?
+					    USB_CHARGE_MODE_ENABLED :
+					    USB_CHARGE_MODE_DISABLED;
+
+	for (int i = 0; i < USB_PORT_COUNT; i++) {
+		usb_charge_set_mode(i, mode, USB_ALLOW_SUSPEND_CHARGE);
+	}
+#endif /* USB_PORT_ENABLE_COUNT */
+
+	for (int i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		/*
+		 * Enable DRP toggle after XHCI inited. This is used to follow
+		 * USB 3.2 spec 10.3.1.1.
+		 */
+		if (xhci_stat) {
+			pd_set_dual_role(i, PD_DRP_TOGGLE_ON);
+		} else if (tc_is_attached_src(i)) {
+			/*
+			 * This is a AP reset S0->S0 transition.
+			 * We should set the role back to sink.
+			 */
+			pd_set_dual_role(i, PD_DRP_FORCE_SINK);
+		}
+	}
+}
+
+__override enum pd_dual_role_states pd_get_drp_state_in_s0(void)
+{
+	if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_ap_xhci_init_done))) {
+		return PD_DRP_TOGGLE_ON;
+	} else {
+		return PD_DRP_FORCE_SINK;
+	}
+}
+
+void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
+{
+	/*
+	 * We ignore the cc_pin and PPC vconn because polarity and PPC vconn
+	 * should already be set correctly in the PPC driver via the pd
+	 * state machine.
+	 */
+}
+
+/* HDMI/TYPE-C function shared subboard interrupt */
+void x_ec_interrupt(enum gpio_signal signal)
+{
+	int sub = corsola_get_db_type();
+
+	if (sub == CORSOLA_DB_TYPEC) {
+		/* C1: PPC interrupt */
+		ppc_interrupt(signal);
+	} else if (sub == CORSOLA_DB_HDMI) {
+		hdmi_hpd_interrupt(signal);
+	} else {
+		CPRINTS("Undetected subboard interrupt.");
+	}
+}
+
+#ifdef CONFIG_VARIANT_CORSOLA_DB_DETECTION
+static void board_hdmi_handler(struct ap_power_ev_callback *cb,
+			       struct ap_power_ev_data data)
+{
+	int value;
+
+	switch (data.event) {
+	default:
+		return;
+
+	case AP_POWER_RESUME:
+		value = 1;
+		break;
+
+	case AP_POWER_SUSPEND:
+		value = 0;
+		break;
+	}
+	gpio_pin_set_dt(GPIO_DT_FROM_ALIAS(gpio_en_hdmi_pwr), value);
+	gpio_pin_set_dt(GPIO_DT_FROM_ALIAS(gpio_ps185_pwrdn_odl), value);
+}
+#endif /* CONFIG_VARIANT_CORSOLA_DB_DETECTION */
+
+static void tasks_init_deferred(void)
+{
+	tasks_inited = true;
+	if (corsola_get_db_type() == CORSOLA_DB_HDMI) {
+		/* If the HDMI port is plugged on-boot, and the usb_mux won't
+		 * be configured before the task inited.  Re-invoke the
+		 * HPD configuration after task inited.
+		 */
+		ps185_hdmi_hpd_mux_set();
+	}
+}
+DECLARE_DEFERRED(tasks_init_deferred);
+
+#ifdef CONFIG_VARIANT_CORSOLA_DB_DETECTION
+static void baseboard_x_ec_gpio2_init(void)
+{
+	static struct ppc_drv virtual_ppc_drv = { 0 };
+	static struct tcpm_drv virtual_tcpc_drv = { 0 };
+#ifdef CONFIG_PLATFORM_EC_USB_CHARGER
+	static struct bc12_drv virtual_bc12_drv = { 0 };
+#endif
+
+	/* no sub board */
+	if (corsola_get_db_type() == CORSOLA_DB_NONE) {
+		return;
+	}
+
+	/* type-c: USB_C1_PPC_INT_ODL / hdmi: PS185_EC_DP_HPD */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_x_ec_gpio2));
+
+	if (corsola_get_db_type() == CORSOLA_DB_TYPEC) {
+		gpio_pin_interrupt_configure_dt(
+			GPIO_DT_FROM_ALIAS(gpio_usb_c1_ppc_int_odl),
+			GPIO_INT_EDGE_FALLING);
+		return;
+	}
+	if (corsola_get_db_type() == CORSOLA_DB_HDMI) {
+		static struct ap_power_ev_callback cb;
+
+		ap_power_ev_init_callback(&cb, board_hdmi_handler,
+					  AP_POWER_RESUME | AP_POWER_SUSPEND);
+		ap_power_ev_add_callback(&cb);
+	}
+
+	/* drop related C1 port drivers when it's a HDMI DB. */
+	ppc_chips[USBC_PORT_C1] =
+		(const struct ppc_config_t){ .drv = &virtual_ppc_drv };
+	tcpc_config[USBC_PORT_C1] =
+		(const struct tcpc_config_t){ .drv = &virtual_tcpc_drv };
+#ifdef CONFIG_PLATFORM_EC_USB_CHARGER
+	bc12_ports[USBC_PORT_C1] =
+		(const struct bc12_config){ .drv = &virtual_bc12_drv };
+#endif
+	/* Use virtual mux to notify AP the mainlink direction. */
+	USB_MUX_ENABLE_ALTERNATIVE(usb_mux_chain_1_hdmi_db);
+
+	/*
+	 * If a HDMI DB is attached, C1 port tasks will be exiting in that
+	 * the port number is larger than board_get_usb_pd_port_count().
+	 * After C1 port tasks finished, we intentionally increase the port
+	 * count by 1 for usb_mux to access the C1 virtual mux for notifying
+	 * mainlink direction.
+	 * The current delay is set to 500 ms. cros-ec-typec module will
+	 * not be getting the fake type-c port count if the deferred call is
+	 * later than the kernel upstarts.
+	 */
+	hook_call_deferred(&tasks_init_deferred_data, 500 * MSEC);
+}
+DECLARE_HOOK(HOOK_INIT, baseboard_x_ec_gpio2_init, HOOK_PRIO_DEFAULT);
+
+__override uint8_t get_dp_pin_mode(int port)
+{
+	if (corsola_get_db_type() == CORSOLA_DB_HDMI && port == USBC_PORT_C1) {
+		if (usb_mux_get(USBC_PORT_C1) & USB_PD_MUX_DP_ENABLED) {
+			return MODE_DP_PIN_E;
+		} else {
+			return 0;
+		}
+	}
+
+	return pd_dfp_dp_get_pin_mode(port, dp_status[port]);
+}
+#endif /* CONFIG_VARIANT_CORSOLA_DB_DETECTION */
diff --git a/zephyr/program/corsola/src/variant_db_detection.c b/zephyr/program/corsola/src/variant_db_detection.c
new file mode 100644
index 0000000000..9ade144513
--- /dev/null
+++ b/zephyr/program/corsola/src/variant_db_detection.c
@@ -0,0 +1,210 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Corsola daughter board detection */
+#include "baseboard_usbc_config.h"
+#include "console.h"
+#include "cros_cbi.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "usb_mux.h"
+#include "variant_db_detection.h"
+
+#include <zephyr/drivers/gpio.h>
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+
+#ifdef TEST_BUILD
+uint32_t dp_status[CONFIG_USB_PD_PORT_MAX_COUNT];
+#endif
+
+static void corsola_db_config(enum corsola_db_type type)
+{
+	switch (type) {
+	case CORSOLA_DB_HDMI:
+		/* EC_X_GPIO1 */
+		gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_en_hdmi_pwr),
+				      GPIO_OUTPUT_HIGH);
+		/* X_EC_GPIO2 */
+		gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_ps185_ec_dp_hpd),
+				      GPIO_INPUT);
+		gpio_enable_dt_interrupt(
+			GPIO_INT_FROM_NODELABEL(int_x_ec_gpio2));
+		/* EC_X_GPIO3 */
+		gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_ps185_pwrdn_odl),
+				      GPIO_OUTPUT_HIGH | GPIO_OPEN_DRAIN);
+		return;
+	case CORSOLA_DB_TYPEC:
+		/* EC_X_GPIO1 */
+		gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_frs_en),
+				      GPIO_OUTPUT_LOW);
+		/* X_EC_GPIO2 */
+		gpio_pin_configure_dt(
+			GPIO_DT_FROM_ALIAS(gpio_usb_c1_ppc_int_odl),
+			GPIO_INPUT | GPIO_PULL_UP);
+		gpio_enable_dt_interrupt(
+			GPIO_INT_FROM_NODELABEL(int_x_ec_gpio2));
+		/* EC_X_GPIO3 */
+		gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_dp_in_hpd),
+				      GPIO_OUTPUT_LOW);
+		return;
+	case CORSOLA_DB_NONE:
+		/* Set floating pins as input with PU to prevent leakage */
+		gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_x_gpio1),
+				      GPIO_INPUT | GPIO_PULL_UP);
+		gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_x_ec_gpio2),
+				      GPIO_INPUT | GPIO_PULL_UP);
+		gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_x_gpio3),
+				      GPIO_INPUT | GPIO_PULL_UP);
+		return;
+	default:
+		break;
+	}
+}
+
+enum corsola_db_type corsola_get_db_type(void)
+{
+#if DT_NODE_EXISTS(DT_NODELABEL(db_config))
+	int ret;
+	uint32_t val;
+#endif
+	static enum corsola_db_type db = CORSOLA_DB_UNINIT;
+
+	if (db != CORSOLA_DB_UNINIT) {
+		return db;
+	}
+
+	if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_hdmi_prsnt_odl))) {
+		db = CORSOLA_DB_HDMI;
+	} else {
+		db = CORSOLA_DB_TYPEC;
+	}
+
+/* Detect for no sub board case by FW_CONFIG */
+#if DT_NODE_EXISTS(DT_NODELABEL(db_config))
+	ret = cros_cbi_get_fw_config(DB, &val);
+	if (ret != 0) {
+		CPRINTS("Error retrieving CBI FW_CONFIG field %d", DB);
+	} else if (val == DB_NONE) {
+		db = CORSOLA_DB_NONE;
+	}
+#endif
+
+	corsola_db_config(db);
+
+	switch (db) {
+	case CORSOLA_DB_NONE:
+		CPRINTS("Detect %s DB", "NONE");
+		break;
+	case CORSOLA_DB_TYPEC:
+		CPRINTS("Detect %s DB", "TYPEC");
+		break;
+	case CORSOLA_DB_HDMI:
+		CPRINTS("Detect %s DB", "HDMI");
+		break;
+	default:
+		CPRINTS("DB UNINIT");
+		break;
+	}
+
+	return db;
+}
+
+static void corsola_db_init(void)
+{
+	corsola_get_db_type();
+}
+DECLARE_HOOK(HOOK_INIT, corsola_db_init, HOOK_PRIO_PRE_I2C);
+
+/**
+ * Handle PS185 HPD changing state.
+ */
+void ps185_hdmi_hpd_mux_set(void)
+{
+	const int hpd =
+		gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_ps185_ec_dp_hpd));
+
+	if (!corsola_is_dp_muxable(USBC_PORT_C1)) {
+		return;
+	}
+
+	if (hpd && !(usb_mux_get(USBC_PORT_C1) & USB_PD_MUX_DP_ENABLED)) {
+		dp_status[USBC_PORT_C1] =
+			VDO_DP_STATUS(0, /* HPD IRQ  ... not applicable */
+				      0, /* HPD level ... not applicable */
+				      0, /* exit DP? ... no */
+				      0, /* usb mode? ... no */
+				      0, /* multi-function ... no */
+				      1, /* DP enabled ... yes */
+				      0, /* power low?  ... no */
+				      (!!DP_FLAGS_DP_ON));
+		/* update C1 virtual mux */
+		usb_mux_set(USBC_PORT_C1, USB_PD_MUX_DP_ENABLED,
+			    USB_SWITCH_DISCONNECT,
+			    0 /* polarity, don't care */);
+		CPRINTS("HDMI plug");
+	}
+}
+
+static void ps185_hdmi_hpd_deferred(void)
+{
+	const int hpd =
+		gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_ps185_ec_dp_hpd));
+
+	if (!hpd && (usb_mux_get(USBC_PORT_C1) & USB_PD_MUX_DP_ENABLED)) {
+		dp_status[USBC_PORT_C1] =
+			VDO_DP_STATUS(0, /* HPD IRQ  ... not applicable */
+				      0, /* HPD level ... not applicable */
+				      0, /* exit DP? ... no */
+				      0, /* usb mode? ... no */
+				      0, /* multi-function ... no */
+				      0, /* DP enabled ... no */
+				      0, /* power low?  ... no */
+				      (!DP_FLAGS_DP_ON));
+		usb_mux_set(USBC_PORT_C1, USB_PD_MUX_NONE,
+			    USB_SWITCH_DISCONNECT,
+			    0 /* polarity, don't care */);
+		CPRINTS("HDMI unplug");
+
+		return;
+	}
+
+	ps185_hdmi_hpd_mux_set();
+}
+DECLARE_DEFERRED(ps185_hdmi_hpd_deferred);
+
+#define HPD_SINK_ABSENCE_DEBOUNCE (2 * MSEC)
+
+void hdmi_hpd_interrupt(enum gpio_signal signal)
+{
+	const int hpd =
+		gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_ps185_ec_dp_hpd));
+
+	if (!hpd) {
+		hook_call_deferred(&ps185_hdmi_hpd_deferred_data,
+				   HPD_SINK_ABSENCE_DEBOUNCE);
+	} else {
+		hook_call_deferred(&ps185_hdmi_hpd_deferred_data, -1);
+	}
+
+	/* C0 DP is muxed, we should not send HPD to the AP */
+	if (!corsola_is_dp_muxable(USBC_PORT_C1)) {
+		if (hpd) {
+			CPRINTS("C0 port is already muxed.");
+		}
+		return;
+	}
+
+	if (hpd && !(usb_mux_get(USBC_PORT_C1) & USB_PD_MUX_DP_ENABLED)) {
+		/* set dp_aux_path_sel first, and configure the usb_mux in the
+		 * deferred hook to prevent from dead locking.
+		 */
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(dp_aux_path_sel), hpd);
+		hook_call_deferred(&ps185_hdmi_hpd_deferred_data, 0);
+	}
+
+	svdm_set_hpd_gpio(USBC_PORT_C1, hpd);
+}
diff --git a/zephyr/program/corsola/starmie/CMakeLists.txt b/zephyr/program/corsola/starmie/CMakeLists.txt
new file mode 100644
index 0000000000..335121dd1b
--- /dev/null
+++ b/zephyr/program/corsola/starmie/CMakeLists.txt
@@ -0,0 +1,15 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a
+# BSD-style license that can be found in the LICENSE file.
+
+# Starmie Makeifile
+
+zephyr_library_sources("../src/ite_hooks.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_I2C "../src/ite_i2c.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC
+                             "../src/ite_usb_pd_policy.c" "../src/ite_usbc.c")
+
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_DETACHABLE_BASE
+			"src/base_detect.c")
+
+zephyr_library_sources("src/lcd.c" "src/ppc.c")
diff --git a/zephyr/program/corsola/starmie/project.conf b/zephyr/program/corsola/starmie/project.conf
new file mode 100644
index 0000000000..27360beed9
--- /dev/null
+++ b/zephyr/program/corsola/starmie/project.conf
@@ -0,0 +1,49 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Variant config
+CONFIG_BOARD_STARMIE=y
+
+# Sensor Drivers
+CONFIG_PLATFORM_EC_ACCEL_LIS2DW12=n
+CONFIG_PLATFORM_EC_ACCELGYRO_ICM42607=n
+CONFIG_PLATFORM_EC_ACCELGYRO_ICM_COMM_I2C=n
+CONFIG_PLATFORM_EC_LID_ANGLE=n
+CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=n
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y
+
+
+CONFIG_PLATFORM_EC_USBC_PPC_SYV682C=n
+CONFIG_PLATFORM_EC_USB_MUX_TUSB546=n
+
+# Button
+CONFIG_PLATFORM_EC_CMD_BUTTON=y
+CONFIG_PLATFORM_EC_POWER_BUTTON=y
+CONFIG_PLATFORM_EC_VOLUME_BUTTONS=y
+CONFIG_PLATFORM_EC_BUTTON_TRIGGERED_RECOVERY=y
+CONFIG_PLATFORM_EC_BUTTONS_RUNTIME_CONFIG=y
+
+# Battery
+CONFIG_PLATFORM_EC_I2C_NACK_RETRY_COUNT=10
+CONFIG_PLATFORM_EC_SMBUS_PEC=y
+CONFIG_PLATFORM_EC_BATT_HOST_FULL_FACTOR=99
+CONFIG_PLATFORM_EC_SMART_BATTERY_OPTIONAL_MFG_FUNC=y
+
+# USBC
+CONFIG_PLATFORM_EC_PD_MAX_POWER_MW=45000
+CONFIG_VARIANT_CORSOLA_DB_DETECTION=n
+
+# On/Off Body Detection
+CONFIG_PLATFORM_EC_BODY_DETECTION=y
+CONFIG_PLATFORM_EC_BODY_DETECTION_ALWAYS_ENABLE_IN_S0=y
+CONFIG_PLATFORM_EC_GESTURE_DETECTION=y
+CONFIG_PLATFORM_EC_GESTURE_HOST_DETECTION=y
+
+# Detachable
+CONFIG_PLATFORM_EC_DETACHABLE_BASE=y
+CONFIG_PLATFORM_EC_BASE_ATTACHED_SWITCH=y
+
+# hibernate power sequence
+CONFIG_CORSOLA_HIBERNATE_PRE_OFF_5V=y
diff --git a/zephyr/program/corsola/starmie/project.overlay b/zephyr/program/corsola/starmie/project.overlay
new file mode 100644
index 0000000000..9ebd5fb5f9
--- /dev/null
+++ b/zephyr/program/corsola/starmie/project.overlay
@@ -0,0 +1,451 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Corsola program common DTS includes */
+
+#include "../common.dtsi"
+#include "../power_signal.dtsi"
+#include "../ite_adc.dtsi"
+#include "../ite_gpio.dtsi"
+#include "../ite_i2c.dtsi"
+#include "../ite_interrupts.dtsi"
+#include "../ite_keyboard.dtsi"
+#include "../ite_led.dtsi"
+#include "../ite_usbc.dtsi"
+#include "../ite_shi.dtsi"
+#include <cros/thermistor/thermistor.dtsi>
+#include <dt-bindings/motionsense/utils.h>
+
+/ {
+	batteries {
+		default_battery: b300049 {
+			compatible = "celxpert,b300049", "battery-smart";
+		};
+	};
+	gpio-interrupts {
+		int_base_imu: base_imu {
+			irq-pin = <&base_imu_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "bmi3xx_interrupt";
+		};
+
+		int_pmic_ec_resetb: pmic-ec-resetb {
+			irq-pin = <&pmic_ec_resetb>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+
+		int_pg_pp4200_s5: pg-pp4200-s5 {
+			irq-pin = <&pg_pp4200_s5_od>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+
+		pogo_prsnt_int: pogo-prsnt-int {
+			irq-pin = <&pogo_prsnt_int_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "base_detect_interrupt";
+		};
+		/delete-node/ lid_imu;
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+		/delete-node/ lid_accel_int_l;
+		/delete-node/ usb_c0_ppc_frsinfo;
+
+		// usb_c0_dp_in_hpd: GPH3
+		ec_pen_chg_dis_odl: ec_pen_chg_dis_odl{
+			gpios = <&gpioh 3 GPIO_OUTPUT_HIGH>;
+		};
+
+		en_pp5000_z2: en_pp5000_z2 {
+			gpios = <&gpioc 6 GPIO_OUTPUT_LOW>;
+		};
+
+		// EN_PP3300_BASE_X  GPD7
+		en_pp3300_base_x: en_pp3300_base_x{
+			gpios = <&gpiod 7 GPIO_OUTPUT_LOW>;
+		};
+
+		// USB_C0_DP_IN_HPD  GPH6
+		usb_c0_dp_in_hpd: usb-c0-dp-in-hpd {
+			gpios = <&gpioh 6 GPIO_OUTPUT_LOW>;
+		};
+
+		// POGO_PRSNT_INT_L  GPI5
+		pogo_prsnt_int_l: pogo_prsnt_int_l {
+			gpios = <&gpioi 5 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+
+		en_pp4200_s5: en-pp4200-s5 {
+			gpios = <&gpiob 7 GPIO_OUTPUT_LOW>;
+		};
+
+		pg_pp4200_s5_od: pg-pp4200-s5-od {
+			gpios = <&gpioc 5 GPIO_INPUT>;
+			enum-name = "GPIO_PG_PP4200_S5_OD";
+		};
+
+		pmic_ec_resetb: pmic-ec-resetb {
+			gpios = <&gpioj 6 (GPIO_INPUT | GPIO_VOLTAGE_1P8 |
+					   GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_PMIC_EC_RESETB";
+		};
+
+		gpio_ac_lcd: gpio-ac-lcd{
+			gpios = <&gpiom 6 GPIO_OUTPUT_LOW>;
+		};
+
+		/delete-node/ entering_rw;
+		/*
+		 * Not used, only to make system.c compilable.
+		 * TODO: find a better way to remove this.
+		 */
+		entering_rw: entering-rw {
+			enum-name = "GPIO_ENTERING_RW";
+		};
+
+		/delete-node/ en_pp5000_usb_a0_vbus;
+		/delete-node/ usb_a0_fault_odl;
+	};
+
+	unused-pins {
+		unused-gpios =
+		<&gpioa 7 GPIO_INPUT_PULL_DOWN>,
+		<&gpioe 0 GPIO_INPUT_PULL_DOWN>,
+		<&gpioe 7 GPIO_INPUT_PULL_DOWN>,
+		<&gpiof 0 GPIO_INPUT_PULL_DOWN>,	//EC_EN_PP3300_WCAM
+		<&gpiof 1 GPIO_INPUT_PULL_DOWN>,
+		<&gpioh 0 GPIO_INPUT_PULL_DOWN>,	//EC_AP_RSVD1_ODL
+		<&gpioh 1 GPIO_INPUT_PULL_DOWN>,
+		<&gpioh 2 GPIO_INPUT_PULL_DOWN>,
+		<&gpioi 3 GPIO_INPUT_PULL_DOWN>,	//EC_AP_RSVD0_ODL
+		<&gpiom 2 GPIO_INPUT_PULL_DOWN>;
+	};
+
+	named-i2c-ports {
+		/delete-node/ usb-c1;			//unused i2c_usb_c1
+	};
+
+	/delete-node/ cros-keyscan;
+
+	aliases {
+		/*
+		 * motion sense's <>_INT_EVENT is handled
+		 * by alias. Using the alias, each driver creates
+		 * its own <>_INT_EVENT.
+		 */
+		bmi3xx-int = &lid_accel;
+
+		/* Use lid accelerometer for body detection */
+		on-body-sensor = &lid_accel;
+	};
+
+	motionsense-mutex {
+		compatible = "cros-ec,motionsense-mutex";
+		lid_mutex_bmi323: bmi323-mutex {
+		};
+	};
+
+	/* Rotation matrix used by drivers. */
+	motionsense-rotation-ref {
+		compatible = "cros-ec,motionsense-rotation-ref";
+		lid_rot_ref_bmi: lid-rotation-ref-bmi {
+			mat33 = <0 1 0
+				 (-1) 0 0
+				 0 0 1>;
+		};
+	};
+
+	motionsense-sensor-data {
+		bmi323_data: bmi323-drv-data {
+			compatible = "cros-ec,drvdata-bmi3xx";
+			status = "okay";
+		};
+	};
+
+	motionsense-sensor {
+		/delete-node/ base-accel;
+		/delete-node/ base-gyro;
+
+		lid_accel: lid-accel {
+			compatible = "cros-ec,bmi3xx-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&lid_mutex_bmi323>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&lid_rot_ref_bmi>;
+			default-range = <2>;
+			drv-data = <&bmi323_data>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		lid_gyro: lid-gyro {
+			compatible = "cros-ec,bmi3xx-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&lid_mutex_bmi323>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&lid_rot_ref_bmi>;
+			drv-data = <&bmi323_data>;
+		};
+	};
+
+	motionsense-sensor-info {
+		compatible = "cros-ec,motionsense-sensor-info";
+
+		/*
+		 * list of GPIO interrupts that have to
+		 * be enabled at initial stage
+		 */
+		sensor-irqs = <&int_base_imu>;
+	};
+
+	usbc {
+		/delete-node/ port1@1;
+		/delete-node/ port1-muxes;
+
+		port0@0{
+			usb-mux-chain-0{
+				usb-muxes = <&ps8743_mux_1 &virtual_mux_0>;
+			};
+		};
+	};
+
+	power_signal_list: power-signal-list {
+		compatible = "mediatek,mt8188-power-signal-list";
+
+		pg_pp4200_s5 {
+			power-enum-name = "PG_PP4200_S5";
+			power-gpio-pin = <&pg_pp4200_s5_od>;
+		};
+		pmic_ap_reset {
+			power-enum-name = "PMIC_AP_RST";
+			power-gpio-pin = <&pmic_ec_resetb>;
+		};
+	};
+
+	named-adc-channels {
+        adc_temp_sensor_1: adc-temp-sensor-1 {
+			enum-name = "ADC_TEMP_SENSOR_1";
+			io-channels = <&adc0 6>;
+		};
+		adc_temp_sensor_2: adc-temp-sensor-2 {
+			enum-name = "ADC_TEMP_SENSOR_2";
+			io-channels = <&adc0 7>;
+		};
+    };
+
+	temp_sensor_1_thermistor: sensor-1-thermistor {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_1V8_100K_100K_4250B>;
+		adc = <&adc_temp_sensor_1>;
+	};
+
+	temp_sensor_2_thermistor: sensor-2-thermistor {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_1V8_100K_100K_4250B>;
+		adc = <&adc_temp_sensor_2>;
+	};
+
+    named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
+		temp_sensor_1 {
+			sensor = <&temp_sensor_1_thermistor>;
+		};
+		temp_sensor_2 {
+			sensor = <&temp_sensor_2_thermistor>;
+		};
+	};
+	/*
+	 * The hardware design sets PWM0 as the amber light,
+	 * PWM1 as the white light and PWM2 as none.
+	 */
+	pwmleds{
+		led_power_white: ec_led1_odl {
+			pwms = <&pwm2 PWM_CHANNEL_2 PWM_HZ(324) PWM_POLARITY_INVERTED>;
+		};
+		led_battery_amber: ec_led2_odl {
+			pwms = <&pwm0 PWM_CHANNEL_0 PWM_HZ(324) PWM_POLARITY_INVERTED>;
+		};
+		led_battery_white: ec_led3_odl {
+			pwms = <&pwm1 PWM_CHANNEL_1 PWM_HZ(324) PWM_POLARITY_INVERTED>;
+		};
+	};
+
+	pwm-led-pins {
+		power_led: power-led {
+			led-id = "EC_LED_ID_POWER_LED";
+			led-pwms = <&led_power_white>;
+
+			/* Overwrite Power LED white to off */
+			color_power_white: color-power-white {
+				led-color = "LED_WHITE";
+				led-values = <0>;
+			};
+		};
+	};
+
+	led-colors {
+		compatible = "cros-ec,led-policy";
+
+		/* STARMIE LED bat charge */
+		bat-power-state-charge-1v1-1 {
+			charge-state = "LED_PWRS_CHARGE";
+			/* Battery percent range (>= Empty, <= 94%) */
+			batt-lvl = <BATTERY_LEVEL_EMPTY 94>;
+			color-0 {
+				led-color = <&color_battery_amber>;
+			};
+		};
+
+		bat-power-state-charge-1v1-2 {
+			charge-state = "LED_PWRS_CHARGE";
+			/* Battery percent range (>= 95) */
+			batt-lvl = <95 100>;
+			color-0 {
+				led-color = <&color_battery_white>;
+			};
+		};
+
+		bat-power-state-charge-near-full {
+			charge-state = "LED_PWRS_CHARGE_NEAR_FULL";
+
+			color-0 {
+				led-color = <&color_battery_white>;
+			};
+		};
+
+		/* STARMIE LED bat discharge */
+		bat-power-state-discharge {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S0";
+			/* Battery percent range (>= 11%, <= Full) */
+			batt-lvl = <(BATTERY_LEVEL_LOW + 1) BATTERY_LEVEL_FULL>;
+
+			color-0 {
+				led-color = <&color_battery_white>;
+			};
+		};
+
+		bat-power-state-discharge-s3 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S3";
+
+			color-0 {
+				led-color = <&color_battery_white>;
+				period-ms = <1000>;
+			};
+
+			color-1 {
+				led-color = <&color_battery_off>;
+				period-ms = <3000>;
+			};
+		};
+
+		bat-power-state-discharge-s5 {
+			charge-state = "LED_PWRS_DISCHARGE";
+
+			chipset-state = "POWER_S5";
+			color-0 {
+				led-color = <&color_battery_off>;
+			};
+		};
+
+		/* STARMIE LED low bat discharge */
+		bat-power-state-discharge-s0-bat-low {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S0";
+			batt-lvl = <BATTERY_LEVEL_EMPTY BATTERY_LEVEL_LOW>;
+
+			color-0 {
+				led-color = <&color_battery_amber>;
+				period-ms = <1000>;
+			};
+
+			color-1 {
+				led-color = <&color_battery_off>;
+				period-ms = <3000>;
+			};
+		};
+
+		/* STARMIE LED bat error */
+		bat-power-state-error {
+			charge-state = "LED_PWRS_ERROR";
+			chipset-state = "POWER_S0";
+
+			color-0 {
+				led-color = <&color_battery_amber>;
+				period-ms = <1000>;
+			};
+
+			color-1 {
+				led-color = <&color_battery_off>;
+				period-ms = <1000>;
+			};
+		};
+
+		bat-power-state-error-s3 {
+			charge-state = "LED_PWRS_ERROR";
+			chipset-state = "POWER_S3";
+
+			color-0 {
+				led-color = <&color_battery_white>;
+				period-ms = <1000>;
+			};
+
+			color-1 {
+				led-color = <&color_battery_off>;
+				period-ms = <3000>;
+			};
+		};
+
+		bat-power-state-error-s5 {
+			charge-state = "LED_PWRS_ERROR";
+			chipset-state = "POWER_S5";
+
+			color-0 {
+				led-color = <&color_battery_off>;
+			};
+		};
+	};
+};
+
+&i2c0{
+	charger_bc12_port1: rt9490@53{
+		compatible = "richtek,rt9490";
+	};
+};
+
+&i2c2 {
+	ps8743_mux_1: ps8743-mux-1@10 {
+		compatible = "parade,ps8743";
+		reg = <0x10>;
+	};
+};
+
+&adc0{
+	status = "okay";
+	pinctrl-0 = <&adc0_ch6_gpi6_default>;
+	pinctrl-names = "default";
+};
+
+&thermistor_1V8_100K_100K_4250B{
+    status = "okay";
+};
diff --git a/zephyr/program/corsola/starmie/src/base_detect.c b/zephyr/program/corsola/starmie/src/base_detect.c
new file mode 100644
index 0000000000..144b26e3be
--- /dev/null
+++ b/zephyr/program/corsola/starmie/src/base_detect.c
@@ -0,0 +1,151 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ap_power/ap_power.h"
+#include "base_state.h"
+#include "chipset.h"
+#include "console.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "tablet_mode.h"
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/kernel.h>
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+
+/* Base detection debouncing */
+#define BASE_DETECT_EN_DEBOUNCE_US (350 * MSEC)
+#define BASE_DETECT_DIS_DEBOUNCE_US (20 * MSEC)
+
+K_MUTEX_DEFINE(modify_base_detection_mutex);
+static bool detect_base_enabled;
+
+static void base_detect_deferred(void);
+DECLARE_DEFERRED(base_detect_deferred);
+
+enum base_status {
+	BASE_UNKNOWN = 0,
+	BASE_DISCONNECTED = 1,
+	BASE_CONNECTED = 2,
+};
+
+static enum base_status current_base_status;
+
+static void base_update(enum base_status specified_status)
+{
+	int connected = (specified_status != BASE_CONNECTED) ? false : true;
+
+	if (current_base_status == specified_status)
+		return;
+
+	current_base_status = specified_status;
+
+	base_set_state(connected);
+	tablet_set_mode(!connected, TABLET_TRIGGER_BASE);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(en_pp3300_base_x), connected);
+}
+
+void base_detect_interrupt(enum gpio_signal signal)
+{
+	gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(pogo_prsnt_int));
+	hook_call_deferred(&base_detect_deferred_data,
+			   (current_base_status == BASE_CONNECTED) ?
+				   BASE_DETECT_DIS_DEBOUNCE_US :
+				   BASE_DETECT_EN_DEBOUNCE_US);
+}
+
+static inline void detect_and_update_base_status(void)
+{
+	if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(pogo_prsnt_int_l))) {
+		base_update(BASE_CONNECTED);
+	} else {
+		base_update(BASE_DISCONNECTED);
+	}
+}
+
+static void base_detect_deferred(void)
+{
+	k_mutex_lock(&modify_base_detection_mutex, K_FOREVER);
+	/*
+	 * If a disable base detection is issued after an ISR, and is before
+	 * executing the deferred hook, then we need to check whether the
+	 * detection is enabled. If disabled, there is no need to re-enable the
+	 * interrupt.
+	 */
+	if (detect_base_enabled) {
+		detect_and_update_base_status();
+		gpio_enable_dt_interrupt(
+			GPIO_INT_FROM_NODELABEL(pogo_prsnt_int));
+	}
+	k_mutex_unlock(&modify_base_detection_mutex);
+}
+
+static void base_detect_enable(bool enable)
+{
+	detect_base_enabled = enable;
+	if (enable) {
+		gpio_enable_dt_interrupt(
+			GPIO_INT_FROM_NODELABEL(pogo_prsnt_int));
+		detect_and_update_base_status();
+	} else {
+		gpio_disable_dt_interrupt(
+			GPIO_INT_FROM_NODELABEL(pogo_prsnt_int));
+		base_update(BASE_UNKNOWN);
+	}
+}
+
+static void base_startup_hook(struct ap_power_ev_callback *cb,
+			      struct ap_power_ev_data data)
+{
+	switch (data.event) {
+	case AP_POWER_STARTUP:
+		base_detect_enable(true);
+		break;
+	case AP_POWER_SHUTDOWN:
+		base_detect_enable(false);
+		break;
+	default:
+		return;
+	}
+}
+
+static int base_init(void)
+{
+	static struct ap_power_ev_callback cb;
+
+	detect_base_enabled = false;
+	ap_power_ev_init_callback(&cb, base_startup_hook,
+				  AP_POWER_STARTUP | AP_POWER_SHUTDOWN);
+	ap_power_ev_add_callback(&cb);
+
+	if (!chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
+		base_detect_enable(true);
+	}
+
+	return 0;
+}
+SYS_INIT(base_init, APPLICATION, 1);
+
+void base_force_state(enum ec_set_base_state_cmd state)
+{
+	k_mutex_lock(&modify_base_detection_mutex, K_FOREVER);
+	switch (state) {
+	case EC_SET_BASE_STATE_ATTACH:
+		base_detect_enable(false);
+		base_update(BASE_CONNECTED);
+		break;
+	case EC_SET_BASE_STATE_DETACH:
+		base_detect_enable(false);
+		base_update(BASE_DISCONNECTED);
+		break;
+	case EC_SET_BASE_STATE_RESET:
+		base_detect_enable(true);
+		break;
+	}
+	k_mutex_unlock(&modify_base_detection_mutex);
+}
diff --git a/zephyr/program/corsola/starmie/src/lcd.c b/zephyr/program/corsola/starmie/src/lcd.c
new file mode 100644
index 0000000000..deb2570f26
--- /dev/null
+++ b/zephyr/program/corsola/starmie/src/lcd.c
@@ -0,0 +1,20 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_state.h"
+#include "console.h"
+#include "extpower.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+
+void ac_feedback_lcd(void)
+{
+	if (extpower_is_present()) {
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ac_lcd), 1);
+	} else {
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ac_lcd), 0);
+	}
+}
+DECLARE_HOOK(HOOK_AC_CHANGE, ac_feedback_lcd, HOOK_PRIO_DEFAULT);
diff --git a/zephyr/program/corsola/starmie/src/ppc.c b/zephyr/program/corsola/starmie/src/ppc.c
new file mode 100644
index 0000000000..4cff7628d2
--- /dev/null
+++ b/zephyr/program/corsola/starmie/src/ppc.c
@@ -0,0 +1,50 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Starmie PPC/BC12 (RT1739) configuration */
+
+#include "baseboard_usbc_config.h"
+#include "driver/ppc/rt1739.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "system.h"
+
+#ifdef CONFIG_PLATFORM_EC_USB_CHARGER
+void c0_bc12_interrupt(enum gpio_signal signal)
+{
+	rt1739_interrupt(0);
+}
+#endif
+
+static void board_usbc_init(void)
+{
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_ppc_bc12));
+}
+DECLARE_HOOK(HOOK_INIT, board_usbc_init, HOOK_PRIO_POST_DEFAULT);
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	if (signal == GPIO_SIGNAL(DT_NODELABEL(usb_c0_ppc_bc12_int_odl))) {
+		ppc_chips[0].drv->interrupt(0);
+	}
+}
+
+static int set_rt1739(void)
+{
+	/*
+	 * (b:286803490#comment12)
+	 * this is a workaround, we initialize rt1739 in an early stage to turn
+	 * on an internal MOS, so the system can boot up with lower voltage. We
+	 * only want to perform this workaround once, so we do it in RO, and not
+	 * do it again in RW, otherwise,re-initialize rt1739 in RW again would
+	 * cause a temporary voltage drop due to switching an internal MOS, and
+	 * EC would have abnormal behaviors due to sensing the wrong voltage.
+	 */
+	if (!system_is_in_rw())
+		rt1739_init(0);
+	return 0;
+}
+
+SYS_INIT(set_rt1739, POST_KERNEL, 61);
diff --git a/zephyr/program/corsola/steelix/CMakeLists.txt b/zephyr/program/corsola/steelix/CMakeLists.txt
new file mode 100644
index 0000000000..d0dce194f9
--- /dev/null
+++ b/zephyr/program/corsola/steelix/CMakeLists.txt
@@ -0,0 +1,12 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Steelix Makeifile
+
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_I2C "../src/npcx_i2c.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC
+                             "../src/npcx_usb_pd_policy.c" "../src/npcx_usbc.c")
+
+zephyr_library_sources("src/board.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LED_COMMON "src/led.c")
diff --git a/zephyr/program/corsola/steelix/cbi.dtsi b/zephyr/program/corsola/steelix/cbi.dtsi
new file mode 100644
index 0000000000..6636b53a96
--- /dev/null
+++ b/zephyr/program/corsola/steelix/cbi.dtsi
@@ -0,0 +1,95 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	steelix-fw-config {
+		compatible = "cros-ec,cbi-fw-config";
+
+		/*
+		 * FW_CONFIG field to indicate the device is clamshell
+		 * or convertible.
+		 */
+		form_factor {
+			enum-name = "FORM_FACTOR";
+			start = <13>;
+			size = <3>;
+
+			convertible {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "CONVERTIBLE";
+				value = <1>;
+			};
+			clamshell {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "CLAMSHELL";
+				value = <0>;
+			};
+		};
+
+		/* FW_CONFIG field to indicate which DB is attached. */
+		db_config: db {
+			enum-name = "DB";
+			start = <0>;
+			size = <4>;
+
+			sub-board-1 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "DB_NONE";
+				value = <0>;
+			};
+			sub-board-2 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "DB_USBA_HDMI";
+				value = <1>;
+			};
+			sub-board-3 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "DB_USBA_HDMI_LTE";
+				value = <2>;
+			};
+		};
+	};
+
+	/* Steelix-specific ssfc fields. */
+	steelix-ssfc {
+		compatible = "cros-ec,cbi-ssfc";
+
+		/* SSFC field to identify BASE motion sensor. */
+		base-sensor {
+			enum-name = "BASE_SENSOR";
+			size = <3>;
+
+			base_sensor_0: bmi323 {
+				compatible = "cros-ec,cbi-ssfc-value";
+				status = "okay";
+				value = <1>;
+				default;
+			};
+			base_sensor_1: lsm6dsm {
+				compatible = "cros-ec,cbi-ssfc-value";
+				status = "okay";
+				value = <2>;
+			};
+		};
+
+		/* SSFC field to identify LID motion sensor. */
+		lid-sensor {
+			enum-name = "LID_SENSOR";
+			size = <3>;
+
+			lid_sensor_0: bma422 {
+				compatible = "cros-ec,cbi-ssfc-value";
+				status = "okay";
+				value = <1>;
+				default;
+			};
+			lid_sensor_1: lis2dw12 {
+				compatible = "cros-ec,cbi-ssfc-value";
+				status = "okay";
+				value = <2>;
+			};
+		};
+	};
+};
diff --git a/zephyr/program/corsola/steelix/interrupts.dtsi b/zephyr/program/corsola/steelix/interrupts.dtsi
new file mode 100644
index 0000000000..b212cd9496
--- /dev/null
+++ b/zephyr/program/corsola/steelix/interrupts.dtsi
@@ -0,0 +1,12 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+ /* This file should only be included in the project.overlay. */
+&int_base_imu {
+	irq-pin = <&base_imu_int_l>;
+	flags = <GPIO_INT_EDGE_FALLING>;
+	handler = "motion_interrupt";
+};
+
diff --git a/zephyr/program/corsola/steelix/project.conf b/zephyr/program/corsola/steelix/project.conf
new file mode 100644
index 0000000000..bf2de72512
--- /dev/null
+++ b/zephyr/program/corsola/steelix/project.conf
@@ -0,0 +1,34 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Variant config
+CONFIG_BOARD_STEELIX=y
+
+# steelix only use D2, drop the workaround config for H1
+CONFIG_PLATFORM_EC_BOARD_RESET_AFTER_POWER_ON=n
+
+# Motion sensor
+CONFIG_PLATFORM_EC_ACCEL_LIS2DW12=y
+CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSM=y
+CONFIG_PLATFORM_EC_DYNAMIC_MOTION_SENSOR_COUNT=y
+
+# Keyboard
+CONFIG_PLATFORM_EC_KEYBOARD_REFRESH_ROW3=y
+CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI3=y
+CONFIG_PLATFORM_EC_KEYBOARD_STRICT_DEBOUNCE=y
+
+# USBC
+CONFIG_PLATFORM_EC_PD_MAX_CURRENT_MA=3250
+CONFIG_PLATFORM_EC_PD_MAX_POWER_MW=65000
+
+# Remove bring up options for FW QUAL
+CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=n
+
+# Remove debug options and features for FW QUAL
+CONFIG_LOG=n
+CONFIG_LOG_MODE_MINIMAL=n
+CONFIG_SHELL_MINIMAL=y
+
+# AC_OK debounce time
+CONFIG_PLATFORM_EC_EXTPOWER_DEBOUNCE_MS=800
diff --git a/zephyr/program/corsola/steelix/project.overlay b/zephyr/program/corsola/steelix/project.overlay
new file mode 100644
index 0000000000..f850a51563
--- /dev/null
+++ b/zephyr/program/corsola/steelix/project.overlay
@@ -0,0 +1,298 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Corsola program common DTS includes */
+
+#include "../common.dtsi"
+#include "../power_signal.dtsi"
+#include "../usba.dtsi"
+#include "../npcx_adc.dtsi"
+#include "../npcx_gpio.dtsi"
+#include "../npcx_host_interface.dtsi"
+#include "../npcx_i2c.dtsi"
+#include "../npcx_interrupts.dtsi"
+#include "../npcx_keyboard.dtsi"
+#include "../npcx_motionsense.dtsi"
+#include "../npcx_usbc.dtsi"
+#include "../npcx_default_gpio_pinctrl.dtsi"
+
+/* Projrect level DTS shared with tests */
+#include "./cbi.dtsi"
+#include "./interrupts.dtsi"
+
+/* board override */
+/ {
+	aliases {
+		/*
+		 * motion sense's <>_INT_EVENT is handled
+		 * by alias. Using the alias, each driver creates
+		 * its own <>_INT_EVENT.
+		 */
+		lsm6dsm-int = &base_accel;
+	};
+
+	named-gpios {
+		en_pp5000_usb_a1_vbus: en_pp5000_usb_a1_vbus_x {
+			gpios = <&gpiof 5 GPIO_OUTPUT_LOW>;
+		};
+		usb_a1_fault_odl {
+			gpios = <&gpiof 4 GPIO_INPUT>;
+		};
+	};
+
+	batteries {
+		default_battery: byd_l22b3pg0 {
+			compatible = "byd,l22b3pg0", "battery-smart";
+		};
+		celxpert_l22c3pg0 {
+			compatible = "celxpert,l22c3pg0", "battery-smart";
+		};
+		cosmx_l22x3pg0 {
+			compatible = "cosmx,l22x3pg0", "battery-smart";
+		};
+		smp_l22m3pg0 {
+			compatible = "smp,l22m3pg0", "battery-smart";
+		};
+		sunwoda_l22d3pg0 {
+			compatible = "sunwoda,l22d3pg0", "battery-smart";
+		};
+	};
+
+
+	/* Steelix-specific ssfc fields. */
+	steelix-ssfc {
+		compatible = "cros-ec,cbi-ssfc";
+
+		/* SSFC field to identify BASE motion sensor. */
+		base-sensor {
+			enum-name = "BASE_SENSOR";
+			size = <3>;
+
+			base_sensor_0: bmi323 {
+				compatible = "cros-ec,cbi-ssfc-value";
+				status = "okay";
+				value = <1>;
+				default;
+			};
+			base_sensor_1: lsm6dsm {
+				compatible = "cros-ec,cbi-ssfc-value";
+				status = "okay";
+				value = <2>;
+			};
+		};
+
+		/* SSFC field to identify LID motion sensor. */
+		lid-sensor {
+			enum-name = "LID_SENSOR";
+			size = <3>;
+
+			lid_sensor_0: bma422 {
+				compatible = "cros-ec,cbi-ssfc-value";
+				status = "okay";
+				value = <1>;
+				default;
+			};
+			lid_sensor_1: lis2dw12 {
+				compatible = "cros-ec,cbi-ssfc-value";
+				status = "okay";
+				value = <2>;
+			};
+		};
+	};
+
+	/* Rotation matrix used by drivers. */
+	motionsense-rotation-ref {
+		compatible = "cros-ec,motionsense-rotation-ref";
+		base_rot_ref_lsm6dsm: base-rotation-ref-lsm6dsm {
+			mat33 = <0 1 0
+				 1 0 0
+				 0 0 (-1)>;
+		};
+	};
+
+	/*
+	 * Driver specific data. A driver-specific data can be shared with
+	 * different motion sensors while they are using the same driver.
+	 *
+	 * If a node's compatible starts with "cros-ec,accelgyro-", it is for
+	 * a common structure defined in accelgyro.h.
+	 * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for
+	 * "struct als_drv_data_t" in accelgyro.h
+	 */
+	motionsense-sensor-data {
+		lis2dw12_data: lis2dw12-drv-data {
+			compatible = "cros-ec,drvdata-lis2dw12";
+			status = "okay";
+		};
+		lsm6dsm_data_accel: lsm6dsm-accel-drv-data {
+			compatible = "cros-ec,drvdata-lsm6dsm";
+			status = "okay";
+		};
+		lsm6dsm_data_gyro: lsm6dsm-gyro-drv-data {
+			compatible = "cros-ec,drvdata-lsm6dsm";
+			status = "okay";
+		};
+	};
+
+	motionsense-sensor-alt {
+		alt_lid_accel: alt-lid-accel {
+			compatible = "cros-ec,lis2dw12";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&lid_mutex>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&lid_rot_ref>;
+			default-range = <2>;
+			drv-data = <&lis2dw12_data>;
+			i2c-spi-addr-flags = "LIS2DWL_ADDR0_FLAGS";
+			alternate-for = <&lid_accel>;
+			alternate-ssfc-indicator = <&lid_sensor_1>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(12500 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(12500 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		alt_base_accel: alt-base-accel {
+			compatible = "cros-ec,lsm6dsm-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref_lsm6dsm>;
+			drv-data = <&lsm6dsm_data_accel>;
+			alternate-for = <&base_accel>;
+			alternate-ssfc-indicator = <&base_sensor_1>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(12500 | ROUND_UP_FLAG)>;
+					ec-rate = <(100 * USEC_PER_MSEC)>;
+				};
+				ec-s3 {
+					odr = <(12500 | ROUND_UP_FLAG)>;
+					ec-rate = <0>;
+				};
+			};
+		};
+
+		alt_base_gyro: alt-base-gyro {
+			compatible = "cros-ec,lsm6dsm-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref_lsm6dsm>;
+			default-range = <(1000 | ROUND_UP_FLAG)>; /* dps */
+			drv-data = <&lsm6dsm_data_gyro>;
+			alternate-for = <&base_gyro>;
+			alternate-ssfc-indicator = <&base_sensor_1>;
+		};
+	};
+
+	cros-keyscan {
+		compatible = "cros-ec,keyscan";
+
+		debounce-down = <15000>;
+		debounce-up = <15000>;
+
+		actual-key-mask = <
+			0x1c	/* C0 */
+			0xff	/* C1 */
+			0xff	/* C2 */
+			0xff	/* C3 */
+			0xff	/* C4 */
+			0xf5	/* C5 */
+			0xff	/* C6 */
+			0xa4	/* C7 */
+			0xff	/* C8 */
+			0xfe	/* C9 */
+			0x55	/* C10 */
+			0xfa	/* C11 */
+			0xca	/* C12 */
+			>;
+	};
+
+	pwmleds {
+		compatible = "pwm-leds";
+		led_battery_red: ec_led1_odl {
+			pwms = <&pwm0 0 PWM_HZ(100) PWM_POLARITY_INVERTED>;
+		};
+		led_battery_green: ec_led2_odl {
+			pwms = <&pwm1 0 PWM_HZ(100) PWM_POLARITY_INVERTED>;
+		};
+		led_power_white: ec_led3_odl {
+			pwms = <&pwm4 0 PWM_HZ(100) PWM_POLARITY_INVERTED>;
+		};
+	};
+};
+
+/* Red LED */
+&pwm0_gpc3 {
+	drive-open-drain;
+};
+
+&pwm0 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm0_gpc3>;
+	pinctrl-names = "default";
+};
+
+/* Green LED */
+&pwm1_gpc2 {
+	drive-open-drain;
+};
+
+&pwm1 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm1_gpc2>;
+	pinctrl-names = "default";
+};
+
+/* White LED */
+&pwm4_gpb6 {
+	drive-open-drain;
+};
+
+&pwm4 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm4_gpb6>;
+	pinctrl-names = "default";
+};
+
+/* inherit the rot_ref from Kingler and overwrite it */
+&lid_rot_ref {
+	mat33 = <0 1 0
+		1 0 0
+		0 0 (-1)>;
+};
+
+&base_rot_ref {
+	mat33 = <1 0 0
+		0 (-1) 0
+		0 0 (-1)>;
+};
+
+/* steelix usba port enable config */
+&usba_port_enable_list {
+	enable-pins = <&en_pp5000_usb_a0_vbus
+		       &en_pp5000_usb_a1_vbus>;
+};
diff --git a/zephyr/program/corsola/steelix/src/board.c b/zephyr/program/corsola/steelix/src/board.c
new file mode 100644
index 0000000000..b4faf5af0c
--- /dev/null
+++ b/zephyr/program/corsola/steelix/src/board.c
@@ -0,0 +1,76 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Board re-init for Rusty board
+ * Rusty shares the firmware with Steelix.
+ * Steelix is convertible but Rusty is clamshell
+ * so some functions should be disabled for clamshell.
+ */
+#include "accelgyro.h"
+#include "common.h"
+#include "cros_cbi.h"
+#include "driver/accelgyro_bmi3xx.h"
+#include "driver/accelgyro_lsm6dsm.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "motion_sense.h"
+#include "motionsense_sensors.h"
+#include "tablet_mode.h"
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(board_init, LOG_LEVEL_ERR);
+
+static bool board_is_clamshell;
+
+static void board_setup_init(void)
+{
+	int ret;
+	uint32_t val;
+
+	ret = cros_cbi_get_fw_config(FORM_FACTOR, &val);
+	if (ret != 0) {
+		LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FORM_FACTOR);
+		return;
+	}
+	if (val == CLAMSHELL) {
+		board_is_clamshell = true;
+		motion_sensor_count = 0;
+		gmr_tablet_switch_disable();
+	}
+}
+DECLARE_HOOK(HOOK_INIT, board_setup_init, HOOK_PRIO_PRE_DEFAULT);
+
+static void disable_base_imu_irq(void)
+{
+	if (board_is_clamshell) {
+		gpio_disable_dt_interrupt(
+			GPIO_INT_FROM_NODELABEL(int_base_imu));
+		gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(base_imu_int_l),
+				      GPIO_INPUT | GPIO_PULL_UP);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, disable_base_imu_irq, HOOK_PRIO_POST_DEFAULT);
+
+static bool base_use_alt_sensor;
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	if (base_use_alt_sensor) {
+		lsm6dsm_interrupt(signal);
+	} else {
+		bmi3xx_interrupt(signal);
+	}
+}
+
+static void alt_sensor_init(void)
+{
+	base_use_alt_sensor = cros_cbi_ssfc_check_match(
+		CBI_SSFC_VALUE_ID(DT_NODELABEL(base_sensor_1)));
+
+	motion_sensors_check_ssfc();
+}
+DECLARE_HOOK(HOOK_INIT, alt_sensor_init, HOOK_PRIO_POST_I2C);
diff --git a/zephyr/program/corsola/steelix/src/led.c b/zephyr/program/corsola/steelix/src/led.c
new file mode 100644
index 0000000000..1188c4f95e
--- /dev/null
+++ b/zephyr/program/corsola/steelix/src/led.c
@@ -0,0 +1,181 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery LED control for Steelix
+ */
+
+#include "board_led.h"
+#include "common.h"
+#include "cros_cbi.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+#include "util.h"
+
+#include <zephyr/drivers/pwm.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(board_led, LOG_LEVEL_ERR);
+
+#define BOARD_LED_PWM_PERIOD_NS BOARD_LED_HZ_TO_PERIOD_NS(100)
+
+static const struct board_led_pwm_dt_channel board_led_battery_red =
+	BOARD_LED_PWM_DT_CHANNEL_INITIALIZER(DT_NODELABEL(led_battery_red));
+static const struct board_led_pwm_dt_channel board_led_battery_green =
+	BOARD_LED_PWM_DT_CHANNEL_INITIALIZER(DT_NODELABEL(led_battery_green));
+static const struct board_led_pwm_dt_channel board_led_power_white =
+	BOARD_LED_PWM_DT_CHANNEL_INITIALIZER(DT_NODELABEL(led_power_white));
+
+__override const int led_charge_lvl_1 = 5;
+__override const int led_charge_lvl_2 = 97;
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
+
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 3 * LED_ONE_SEC },
+					       { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    3 * LED_ONE_SEC },
+						  { LED_OFF,
+						    0.5 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_BATTERY_LED,
+	EC_LED_ID_POWER_LED,
+};
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+static void board_led_pwm_set_duty(const struct board_led_pwm_dt_channel *ch,
+				   int percent)
+{
+	uint32_t pulse_ns;
+	int rv;
+
+	if (!device_is_ready(ch->dev)) {
+		LOG_ERR("PWM device %s not ready", ch->dev->name);
+		return;
+	}
+
+	pulse_ns = DIV_ROUND_NEAREST(BOARD_LED_PWM_PERIOD_NS * percent, 100);
+
+	LOG_DBG("Board LED PWM %s set percent (%d), pulse %d", ch->dev->name,
+		percent, pulse_ns);
+
+	rv = pwm_set(ch->dev, ch->channel, BOARD_LED_PWM_PERIOD_NS, pulse_ns,
+		     ch->flags);
+	if (rv) {
+		LOG_ERR("pwm_set() failed %s (%d)", ch->dev->name, rv);
+	}
+}
+
+static bool device_is_clamshell(void)
+{
+	int ret;
+	uint32_t val;
+
+	ret = cros_cbi_get_fw_config(FORM_FACTOR, &val);
+	if (ret != 0) {
+		LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FORM_FACTOR);
+		return false;
+	}
+
+	return val == CLAMSHELL;
+}
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_RED:
+		board_led_pwm_set_duty(&board_led_battery_red, 100);
+		board_led_pwm_set_duty(&board_led_battery_green, 0);
+		break;
+	case EC_LED_COLOR_GREEN:
+		board_led_pwm_set_duty(&board_led_battery_red, 0);
+		board_led_pwm_set_duty(&board_led_battery_green, 100);
+		break;
+	case EC_LED_COLOR_AMBER:
+		board_led_pwm_set_duty(&board_led_battery_red, 100);
+		board_led_pwm_set_duty(&board_led_battery_green, 20);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		board_led_pwm_set_duty(&board_led_battery_red, 0);
+		board_led_pwm_set_duty(&board_led_battery_green, 0);
+		break;
+	}
+}
+
+__override void led_set_color_power(enum ec_led_colors color)
+{
+	if (device_is_clamshell()) {
+		board_led_pwm_set_duty(&board_led_power_white, 0);
+	} else {
+		switch (color) {
+		case EC_LED_COLOR_WHITE:
+			board_led_pwm_set_duty(&board_led_power_white, 100);
+			break;
+		default:
+			board_led_pwm_set_duty(&board_led_power_white, 0);
+			break;
+		}
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_RED] = 1;
+		brightness_range[EC_LED_COLOR_GREEN] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		if (device_is_clamshell()) {
+			brightness_range[EC_LED_COLOR_WHITE] = 0;
+		} else {
+			brightness_range[EC_LED_COLOR_WHITE] = 1;
+		}
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		if (brightness[EC_LED_COLOR_RED] != 0) {
+			led_set_color_battery(EC_LED_COLOR_RED);
+		} else if (brightness[EC_LED_COLOR_GREEN] != 0) {
+			led_set_color_battery(EC_LED_COLOR_GREEN);
+		} else if (brightness[EC_LED_COLOR_AMBER] != 0) {
+			led_set_color_battery(EC_LED_COLOR_AMBER);
+		} else {
+			led_set_color_battery(LED_OFF);
+		}
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		if (brightness[EC_LED_COLOR_WHITE] != 0) {
+			led_set_color_power(EC_LED_COLOR_WHITE);
+		} else {
+			led_set_color_power(LED_OFF);
+		}
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/zephyr/program/corsola/tentacruel/CMakeLists.txt b/zephyr/program/corsola/tentacruel/CMakeLists.txt
new file mode 100644
index 0000000000..f363dc33a4
--- /dev/null
+++ b/zephyr/program/corsola/tentacruel/CMakeLists.txt
@@ -0,0 +1,12 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Tentacruel Makeifile
+
+zephyr_library_sources("../src/ite_hooks.c" "../src/ite_charger_workaround.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_I2C "../src/ite_i2c.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC
+                             "../src/ite_usb_pd_policy.c" "../src/ite_usbc.c")
+
+zephyr_library_sources("src/sensor.c" "src/temp.c" "src/ppc.c")
diff --git a/zephyr/program/corsola/tentacruel/cbi.dtsi b/zephyr/program/corsola/tentacruel/cbi.dtsi
new file mode 100644
index 0000000000..cce0fff199
--- /dev/null
+++ b/zephyr/program/corsola/tentacruel/cbi.dtsi
@@ -0,0 +1,74 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	/* tentacruel-specific fw_config fields. */
+	tentacruel-fw-config {
+		compatible = "cros-ec,cbi-fw-config";
+		/*
+		 * FW_CONFIG field to describe mainboard orientation in chassis.
+		 */
+		form_factor {
+			enum-name = "FORM_FACTOR";
+			start = <7>;
+			size = <1>;
+
+			clamshell {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "CLAMSHELL";
+				value = <0>;
+			};
+			convertible {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "CONVERTIBLE";
+				value = <1>;
+			};
+		};
+		base-sensor {
+			enum-name = "BASE_SENSOR";
+			start = <8>;
+			size = <2>;
+
+			none {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "BASE_NONE";
+				value = <0>;
+				default;
+			};
+			icm42607 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "BASE_ICM42607";
+				value = <1>;
+			};
+			bmi323 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "BASE_BMI323";
+				value = <2>;
+			};
+		};
+		lid-sensor {
+			enum-name = "LID_SENSOR";
+			start = <10>;
+			size = <2>;
+
+			none {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "LID_NONE";
+				value = <0>;
+				default;
+			};
+			lis2dwltr {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "LID_LIS2DWLTR";
+				value = <1>;
+			};
+			bma422 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "LID_BMA422";
+				value = <2>;
+			};
+		};
+	};
+};
diff --git a/zephyr/program/corsola/tentacruel/project.conf b/zephyr/program/corsola/tentacruel/project.conf
new file mode 100644
index 0000000000..77dc9b8019
--- /dev/null
+++ b/zephyr/program/corsola/tentacruel/project.conf
@@ -0,0 +1,29 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Variant config
+CONFIG_BOARD_TENTACRUEL=y
+
+# USB-C
+CONFIG_PLATFORM_EC_USB_MUX_TUSB546=n
+
+# Keyboard
+CONFIG_PLATFORM_EC_KEYBOARD_REFRESH_ROW3=y
+CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI3=y
+
+# Sensor
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y
+CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y
+CONFIG_PLATFORM_EC_DYNAMIC_MOTION_SENSOR_COUNT=y
+
+# Battery
+CONFIG_PLATFORM_EC_CHARGER_PROFILE_OVERRIDE=y
+CONFIG_PLATFORM_EC_I2C_NACK_RETRY_COUNT=10
+CONFIG_PLATFORM_EC_SMBUS_PEC=y
+CONFIG_PLATFORM_EC_SMART_BATTERY_OPTIONAL_MFG_FUNC=y
+
+# Remove bring up options for FW QUAL
+CONFIG_PLATFORM_EC_BRINGUP=n
+CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=n
diff --git a/zephyr/program/corsola/tentacruel/project.overlay b/zephyr/program/corsola/tentacruel/project.overlay
new file mode 100644
index 0000000000..a73d7b172e
--- /dev/null
+++ b/zephyr/program/corsola/tentacruel/project.overlay
@@ -0,0 +1,430 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Corsola program common DTS includes */
+
+#include <cros/thermistor/thermistor.dtsi>
+#include "../common.dtsi"
+#include "../power_signal.dtsi"
+#include "../usba.dtsi"
+#include "../ite_adc.dtsi"
+#include "../ite_gpio.dtsi"
+#include "../ite_keyboard.dtsi"
+#include "../ite_i2c.dtsi"
+#include "../ite_interrupts.dtsi"
+#include "../ite_led.dtsi"
+#include "../ite_motionsense.dtsi"
+#include "../ite_usbc.dtsi"
+#include "../ite_shi.dtsi"
+#include "./thermistor.dtsi"
+#include "./cbi.dtsi"
+
+/ {
+	aliases {
+		/*
+		 * motion sense's <>_INT_EVENT is handled
+		 * by alias. Using the alias, each driver creates
+		 * its own <>_INT_EVENT.
+		 */
+		bmi3xx-int = &base_accel;
+		bma4xx-int = &lid_accel;
+	};
+
+	named-gpios {
+		/delete-node/ usb_c0_ppc_bc12_int_odl;
+
+		usb_c0_ppc_int_odl: usb_c0_ppc_int_odl {
+			gpios = <&gpiod 1 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C0_PPC_INT_ODL";
+		};
+
+		usb_c0_bc12_int_odl: usb_c0_bc12_int_odl {
+			gpios = <&gpiof 1 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C0_BC12_INT_ODL";
+		};
+
+		/delete-node/ usb_c0_ppc_frsinfo;
+
+		usb_c0_frs_en: usb_c0_frs_en {
+			gpios = <&gpiof 0 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_USB_C0_FRS_EN";
+		};
+	};
+
+	unused-pins {
+		unused-gpios =
+			/* pg_pp5000_z2_od */
+			<&gpiod 2 GPIO_INPUT>,
+			/* pg_mt6315_proc_b_odl */
+			<&gpioe 1 GPIO_INPUT>,
+			/* ec_pen_chg_dis_odl */
+			<&gpioh 3 GPIO_ODR_HIGH>,
+			/* unnamed nc pins */
+			<&gpioa 3 GPIO_INPUT_PULL_DOWN>,
+			<&gpioa 6 GPIO_INPUT_PULL_DOWN>,
+			<&gpioa 7 GPIO_INPUT_PULL_DOWN>,
+			<&gpiod 7 GPIO_INPUT_PULL_DOWN>,
+			<&gpioh 0 GPIO_INPUT_PULL_DOWN>,
+			<&gpioh 6 GPIO_INPUT_PULL_DOWN>,
+			<&gpioi 3 GPIO_INPUT_PULL_DOWN>,
+			<&gpioi 6 GPIO_INPUT_PULL_DOWN>,
+			<&gpiom 6 (GPIO_INPUT_PULL_DOWN | GPIO_VOLTAGE_1P8)>,
+			/* spi_clk_gpg6 */
+			<&gpiog 6 GPIO_INPUT_PULL_UP>,
+			/* spi_mosi_gpg4 */
+			<&gpiog 4 GPIO_OUTPUT_LOW>,
+			/* spi_miso_gpg5 */
+			<&gpiog 5 GPIO_OUTPUT_LOW>,
+			/* spi_cs_gpg7 */
+			<&gpiog 7 GPIO_OUTPUT_LOW>;
+	};
+
+	gpio-interrupts {
+		int_base_imu: base_imu {
+			handler = "base_sensor_interrupt";
+		};
+
+		int_lid_imu: lid_imu {
+			handler = "lid_sensor_interrupt";
+		};
+
+		/delete-node/ usb_c0_ppc_bc12;
+
+		int_usb_c0_ppc: usb_c0_ppc {
+			irq-pin = <&usb_c0_ppc_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "ppc_interrupt";
+		};
+
+		int_usb_c0_bc12: usb_c0_bc12 {
+			irq-pin = <&usb_c0_bc12_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "bc12_interrupt";
+		};
+	};
+
+	usbc {
+
+		port0@0 {
+			bc12 = <&bc12_port0>;
+			ppc_alt = <&ppc_port0>;
+		};
+
+
+		port1@1 {
+			usb-mux-chain-1 {
+				usb-muxes = <&ps8743_mux_1 &virtual_mux_1>;
+			};
+		};
+	};
+
+	named-adc-channels {
+		adc_ambient: ambient {
+			enum-name = "ADC_TEMP_SENSOR_2_AMBIENT";
+			io-channels = <&adc0 5>;
+		};
+	};
+
+	temp_ambient: ambient {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_30K9_47K_NCP15WB>;
+		adc = <&adc_ambient>;
+	};
+
+	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
+		ambient {
+			temp_host_high = <56>;
+			temp_host_halt = <80>;
+			temp_host_release_high = <42>;
+			sensor = <&temp_ambient>;
+		};
+		temp_charger: charger {
+			temp_host_high = <68>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <59>;
+			sensor = <&charger_bc12_port1>;
+		};
+	};
+
+	/*
+	 * Declare mutexes used by sensor drivers.
+	 * A mutex node is used to create an instance of mutex_t.
+	 * A mutex node is referenced by a sensor node if the
+	 * corresponding sensor driver needs to use the
+	 * instance of the mutex.
+	 */
+	motionsense-mutex {
+		base_mutex_bmi323: bmi323-mutex {
+		};
+
+		lid_mutex_bma422: bma422-mutex {
+		};
+	};
+
+	/* Rotation matrix used by drivers. */
+	motionsense-rotation-ref {
+		lid_rot_ref_bma422: lid-rotation-ref-bma422 {
+			mat33 = <1 0 0
+				 0 1 0
+				 0 0 1>;
+		};
+
+		base_rot_ref_bmi323: base-rotation-ref-bmi323 {
+			mat33 = <0 1 0
+				 (-1) 0 0
+				 0 0 1>;
+		};
+	};
+
+	/*
+	 * Driver specific data. A driver-specific data can be shared with
+	 * different motion sensors while they are using the same driver.
+	 *
+	 * If a node's compatible starts with "cros-ec,accelgyro-", it is for
+	 * a common structure defined in accelgyro.h.
+	 * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for
+	 * "struct als_drv_data_t" in accelgyro.h
+	 */
+	motionsense-sensor-data {
+		bmi323_data: bmi323-drv-data {
+			compatible = "cros-ec,drvdata-bmi3xx";
+			status = "okay";
+		};
+
+		bma422_data: bma422-drv-data {
+			compatible = "cros-ec,drvdata-bma4xx";
+			status = "okay";
+		};
+	};
+
+	motionsense-sensor-alt {
+		alt_lid_accel: alt-lid-accel {
+			compatible = "cros-ec,bma4xx";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&lid_mutex_bma422>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&lid_rot_ref_bma422>;
+			default-range = <2>;
+			drv-data = <&bma422_data>;
+			i2c-spi-addr-flags = "BMA4_I2C_ADDR_SECONDARY";
+			alternate-for = <&lid_accel>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		alt_base_accel: alt-base-accel {
+			compatible = "cros-ec,bmi3xx-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex_bmi323>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref_bmi323>;
+			drv-data = <&bmi323_data>;
+			alternate-for = <&base_accel>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		alt_base_gyro: alt-base-gyro {
+			compatible = "cros-ec,bmi3xx-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex_bmi323>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref_bmi323>;
+			drv-data = <&bmi323_data>;
+			alternate-for = <&base_gyro>;
+		};
+	};
+
+	led-colors {
+		compatible = "cros-ec,led-policy";
+
+		/* Tentacruel LED bat charge */
+		bat-power-state-charge {
+			charge-state = "LED_PWRS_CHARGE";
+			/* Battery percent range (>= Empty, <= 94%) */
+			batt-lvl = <BATTERY_LEVEL_EMPTY 94>;
+			color-0 {
+				led-color = <&color_battery_amber>;
+			};
+		};
+
+		bat-power-state-charge-near-full {
+			charge-state = "LED_PWRS_CHARGE";
+			/* Battery percent range (>= 95%, <= Full) */
+			batt-lvl = <95 BATTERY_LEVEL_FULL>;
+			color-0 {
+				led-color = <&color_battery_white>;
+			};
+		};
+
+		/* Tentacruel LED bat discharge */
+		bat-power-state-discharge {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S0";
+			/* Battery percent range (>= 11%, <= Full) */
+			batt-lvl = <(BATTERY_LEVEL_LOW + 1) BATTERY_LEVEL_FULL>;
+
+			color-0 {
+				led-color = <&color_battery_white>;
+			};
+		};
+
+		bat-power-state-discharge-s3 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S3";
+
+			color-0 {
+				led-color = <&color_battery_white>;
+				period-ms = <1000>;
+			};
+
+			color-1 {
+				led-color = <&color_battery_off>;
+				period-ms = <3000>;
+			};
+		};
+
+		bat-power-state-discharge-s5 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S5";
+			color-0 {
+				led-color = <&color_battery_off>;
+			};
+		};
+
+		/* Tentacruel LED bat error */
+		bat-power-state-error {
+			charge-state = "LED_PWRS_ERROR";
+			chipset-state = "POWER_S0";
+
+			color-0 {
+				led-color = <&color_battery_amber>;
+				period-ms = <1000>;
+			};
+
+			color-1 {
+				led-color = <&color_battery_off>;
+				period-ms = <1000>;
+			};
+		};
+
+		bat-power-state-error-s3 {
+			charge-state = "LED_PWRS_ERROR";
+			chipset-state = "POWER_S3";
+
+			color-0 {
+				led-color = <&color_battery_white>;
+				period-ms = <1000>;
+			};
+
+			color-1 {
+				led-color = <&color_battery_off>;
+				period-ms = <3000>;
+			};
+		};
+
+		bat-power-state-error-s5 {
+			charge-state = "LED_PWRS_ERROR";
+			chipset-state = "POWER_S5";
+
+			color-0 {
+				led-color = <&color_battery_off>;
+			};
+		};
+	};
+
+	pwm-led-pins {
+		compatible = "cros-ec,pwm-led-pins";
+
+		power_led: power-led {
+			led-id = "EC_LED_ID_POWER_LED";
+			led-pwms = <&led_power_white>;
+
+			/* Overwrite Power LED white to off */
+			color_power_white: color-power-white {
+				led-color = "LED_WHITE";
+				led-values = <0>;
+			};
+		};
+	};
+
+	batteries {
+		default_battery: dynapack_c140254 {
+			compatible = "dynapack,c140254", "battery-smart";
+		};
+	};
+};
+
+
+&adc0 {
+	pinctrl-0 = <&adc0_ch0_gpi0_default
+		     &adc0_ch1_gpi1_default
+		     &adc0_ch2_gpi2_default
+		     &adc0_ch5_gpi5_default
+		     &adc0_ch7_gpi7_default>;
+};
+
+&thermistor_3V3_30K9_47K_NCP15WB {
+	status = "okay";
+};
+
+
+&i2c0 {
+	charger_bc12_port1: rt9490@53 {
+		thermistor = <&thermistor_rt9490>;
+	};
+};
+
+&i2c2 {
+	bc12_port0: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+		irq = <&int_usb_c0_bc12>;
+	};
+
+	ppc_port0: syv682x@40 {
+		compatible = "silergy,syv682x";
+		status = "okay";
+		reg = <0x40>;
+		frs_en_gpio = <&usb_c0_frs_en>;
+	};
+};
+
+&i2c4 {
+	/delete-node/ tusb1064-mux-1@44;
+
+	ps8743_mux_1: ps8743-mux-1@10 {
+		compatible = "parade,ps8743";
+		reg = <0x10>;
+		board-init = "ps8743_eq_c1_setting";
+	};
+};
diff --git a/zephyr/program/corsola/tentacruel/src/ppc.c b/zephyr/program/corsola/tentacruel/src/ppc.c
new file mode 100644
index 0000000000..85cf7d1b26
--- /dev/null
+++ b/zephyr/program/corsola/tentacruel/src/ppc.c
@@ -0,0 +1,91 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Tentacruel PPC/BC12 (mixed RT1739 or PI3USB9201+SYV682X) configuration */
+
+#include "baseboard_usbc_config.h"
+#include "cros_board_info.h"
+#include "driver/usb_mux/ps8743_public.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "usb_mux.h"
+#include "usbc/ppc.h"
+
+#include <zephyr/logging/log.h>
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+
+LOG_MODULE_REGISTER(alt_dev_replacement);
+
+#define BOARD_VERSION_UNKNOWN 0xffffffff
+
+/* Check board version to decide which ppc/bc12 is used. */
+static bool board_has_syv_ppc(void)
+{
+	static uint32_t board_version = BOARD_VERSION_UNKNOWN;
+
+	if (board_version == BOARD_VERSION_UNKNOWN || IS_ENABLED(CONFIG_TEST)) {
+		if (cbi_get_board_version(&board_version) != EC_SUCCESS) {
+			LOG_ERR("Failed to get board version.");
+			board_version = 0;
+		}
+	}
+
+	return (board_version >= 3);
+}
+
+static void check_alternate_devices(void)
+{
+	/* Configure the PPC driver */
+	if (board_has_syv_ppc())
+		/* Arg is the USB port number */
+		PPC_ENABLE_ALTERNATE(0);
+}
+DECLARE_HOOK(HOOK_INIT, check_alternate_devices, HOOK_PRIO_DEFAULT);
+
+#ifdef CONFIG_PLATFORM_EC_USB_CHARGER
+void bc12_interrupt(enum gpio_signal signal)
+{
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+#endif
+
+/* USB Mux C1 : board_init of PS8743 */
+int ps8743_eq_c1_setting(void)
+{
+	ps8743_write(usb_muxes[1].mux, PS8743_REG_USB_EQ_RX, 0x90);
+	return EC_SUCCESS;
+}
+
+static void board_usbc_init(void)
+{
+	if (board_has_syv_ppc()) {
+		/* Enable PPC interrupts. */
+		gpio_enable_dt_interrupt(
+			GPIO_INT_FROM_NODELABEL(int_usb_c0_ppc));
+
+#ifdef CONFIG_PLATFORM_EC_USB_CHARGER
+		/* Enable BC1.2 interrupts. */
+		gpio_enable_dt_interrupt(
+			GPIO_INT_FROM_NODELABEL(int_usb_c0_bc12));
+#endif
+	} else {
+		gpio_enable_dt_interrupt(
+			GPIO_INT_FROM_NODELABEL(int_usb_c0_ppc));
+	}
+}
+DECLARE_HOOK(HOOK_INIT, board_usbc_init, HOOK_PRIO_POST_DEFAULT);
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	if (signal == GPIO_SIGNAL(DT_NODELABEL(usb_c0_ppc_int_odl))) {
+		ppc_chips[0].drv->interrupt(0);
+	}
+	if (signal == GPIO_SIGNAL(DT_ALIAS(gpio_usb_c1_ppc_int_odl))) {
+		ppc_chips[1].drv->interrupt(1);
+	}
+}
diff --git a/zephyr/program/corsola/tentacruel/src/sensor.c b/zephyr/program/corsola/tentacruel/src/sensor.c
new file mode 100644
index 0000000000..232dd4f5e8
--- /dev/null
+++ b/zephyr/program/corsola/tentacruel/src/sensor.c
@@ -0,0 +1,103 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "accelgyro.h"
+#include "cros_cbi.h"
+#include "driver/accel_bma422.h"
+#include "driver/accel_lis2dw12.h"
+#include "driver/accelgyro_bmi323.h"
+#include "driver/accelgyro_icm42607.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "motion_sense.h"
+#include "motionsense_sensors.h"
+#include "tablet_mode.h"
+
+static bool base_is_none;
+static bool lid_is_none;
+
+void base_sensor_interrupt(enum gpio_signal signal)
+{
+	uint32_t val;
+
+	cros_cbi_get_fw_config(FORM_FACTOR, &val);
+	if (val == CONVERTIBLE) {
+		cros_cbi_get_fw_config(BASE_SENSOR, &val);
+		if (val == BASE_BMI323) {
+			bmi3xx_interrupt(signal);
+		}
+		/* The convertible device gyro sensor default is icm42607 */
+		else {
+			icm42607_interrupt(signal);
+		}
+	} else {
+		base_is_none = true;
+	}
+}
+
+void lid_sensor_interrupt(enum gpio_signal signal)
+{
+	uint32_t val;
+
+	cros_cbi_get_fw_config(FORM_FACTOR, &val);
+	if (val == CONVERTIBLE) {
+		cros_cbi_get_fw_config(LID_SENSOR, &val);
+		if (val == LID_BMA422) {
+			bma4xx_interrupt(signal);
+		}
+		/* The convertible device lid sensor default is lis2dw12 */
+		else {
+			lis2dw12_interrupt(signal);
+		}
+	} else {
+		lid_is_none = true;
+	}
+}
+
+static void disable_base_lid_irq(void)
+{
+	if (base_is_none && lid_is_none) {
+		gpio_disable_dt_interrupt(
+			GPIO_INT_FROM_NODELABEL(int_base_imu));
+		gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(base_imu_int_l),
+				      GPIO_INPUT | GPIO_PULL_UP);
+		gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_lid_imu));
+		gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(lid_accel_int_l),
+				      GPIO_INPUT | GPIO_PULL_UP);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, disable_base_lid_irq, HOOK_PRIO_POST_DEFAULT);
+
+static void board_sensor_init(void)
+{
+	uint32_t val;
+
+	cros_cbi_get_fw_config(FORM_FACTOR, &val);
+	if (val == CLAMSHELL) {
+		motion_sensor_count = 0;
+		gmr_tablet_switch_disable();
+		ccprints("Board is Clamshell");
+	} else if (val == CONVERTIBLE) {
+		ccprints("Board is Convertible");
+
+		cros_cbi_get_fw_config(BASE_SENSOR, &val);
+		if (val == BASE_ICM42607) {
+			ccprints("Base sensor is ICM42607");
+		} else if (val == BASE_BMI323) {
+			MOTIONSENSE_ENABLE_ALTERNATE(alt_base_accel);
+			MOTIONSENSE_ENABLE_ALTERNATE(alt_base_gyro);
+			ccprints("Base sensor is BMI323");
+		}
+
+		cros_cbi_get_fw_config(LID_SENSOR, &val);
+		if (val == LID_LIS2DWLTR) {
+			ccprints("Lid sensnor is LIS2DWLTR");
+		} else if (val == LID_BMA422) {
+			MOTIONSENSE_ENABLE_ALTERNATE(alt_lid_accel);
+			ccprints("Lid sensnor is BMA422");
+		}
+	}
+}
+DECLARE_HOOK(HOOK_INIT, board_sensor_init, HOOK_PRIO_DEFAULT);
diff --git a/zephyr/program/corsola/tentacruel/src/temp.c b/zephyr/program/corsola/tentacruel/src/temp.c
new file mode 100644
index 0000000000..2f6a2d6f0e
--- /dev/null
+++ b/zephyr/program/corsola/tentacruel/src/temp.c
@@ -0,0 +1,124 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_state.h"
+#include "common.h"
+#include "driver/charger/rt9490.h"
+#include "hooks.h"
+#include "temp_sensor/temp_sensor.h"
+
+#define NUM_CURRENT_LEVELS ARRAY_SIZE(current_table)
+#define TEMP_THRESHOLD 50
+#define TEMP_BUFF_SIZE 60
+#define KEEP_TIME 5
+
+BUILD_ASSERT(IS_ENABLED(CONFIG_BOARD_TENTACRUEL) || IS_ENABLED(CONFIG_TEST));
+/* calculate current average temperature */
+static int average_tempature(void)
+{
+	static int temp_history_buffer[TEMP_BUFF_SIZE];
+	static int buff_ptr;
+	static int temp_sum;
+	static int past_temp;
+	static int avg_temp;
+	int cur_temp, t;
+
+	temp_sensor_read(TEMP_SENSOR_ID(DT_NODELABEL(temp_charger)), &t);
+	cur_temp = K_TO_C(t);
+	past_temp = temp_history_buffer[buff_ptr];
+	temp_history_buffer[buff_ptr] = cur_temp;
+	temp_sum = temp_sum + temp_history_buffer[buff_ptr] - past_temp;
+	buff_ptr++;
+	if (buff_ptr >= TEMP_BUFF_SIZE) {
+		buff_ptr = 0;
+	}
+	/* Calculate per minute temperature.
+	 * It's expected low temperature when the first 60 seconds.
+	 */
+	avg_temp = temp_sum / TEMP_BUFF_SIZE;
+	return avg_temp;
+}
+
+static int current_level;
+
+/* Limit charging current table : 3600/3000/2400/1800
+ * note this should be in descending order.
+ */
+static uint16_t current_table[] = {
+	3600,
+	3000,
+	2400,
+	1600,
+};
+
+/* Called by hook task every hook second (1 sec) */
+static void current_update(void)
+{
+	int temp;
+	static uint8_t uptime;
+	static uint8_t dntime;
+
+	temp = average_tempature();
+#ifndef CONFIG_TEST
+	if (led_pwr_get_state() == LED_PWRS_DISCHARGE) {
+		current_level = 0;
+		uptime = 0;
+		dntime = 0;
+		return;
+	}
+#endif
+	if (temp >= TEMP_THRESHOLD) {
+		dntime = 0;
+		if (uptime < KEEP_TIME) {
+			uptime++;
+		} else {
+			uptime = 0;
+			current_level++;
+		}
+	} else if (current_level != 0 && temp < TEMP_THRESHOLD) {
+		uptime = 0;
+		if (dntime < KEEP_TIME) {
+			dntime++;
+		} else {
+			dntime = 0;
+			current_level--;
+		}
+	} else {
+		uptime = 0;
+		dntime = 0;
+	}
+	if (current_level > NUM_CURRENT_LEVELS) {
+		current_level = NUM_CURRENT_LEVELS;
+	}
+}
+DECLARE_HOOK(HOOK_SECOND, current_update, HOOK_PRIO_DEFAULT);
+
+int charger_profile_override(struct charge_state_data *curr)
+{
+	/*
+	 * Precharge must be executed when communication is failed on
+	 * dead battery.
+	 */
+	if (!(curr->batt.flags & BATT_FLAG_RESPONSIVE))
+		return 0;
+	if (current_level != 0) {
+		if (curr->requested_current > current_table[current_level - 1])
+			curr->requested_current =
+				current_table[current_level - 1];
+	}
+	return 0;
+}
+
+enum ec_status charger_profile_override_get_param(uint32_t param,
+						  uint32_t *value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+enum ec_status charger_profile_override_set_param(uint32_t param,
+						  uint32_t value)
+{
+	return EC_RES_INVALID_PARAM;
+}
diff --git a/zephyr/program/corsola/tentacruel/thermistor.dtsi b/zephyr/program/corsola/tentacruel/thermistor.dtsi
new file mode 100644
index 0000000000..f9e5306f24
--- /dev/null
+++ b/zephyr/program/corsola/tentacruel/thermistor.dtsi
@@ -0,0 +1,140 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	thermistor_rt9490: thermistor-rt9490 {
+		status = "okay";
+		compatible = "cros-ec,thermistor";
+		scaling-factor = <3>;
+		num-pairs = <21>;
+		steinhart-reference-mv = <4900>;
+		steinhart-reference-res = <10000>;
+
+		sample-datum-0 {
+			milivolt = <(731 / 3)>;
+			temp = <0>;
+			sample-index = <0>;
+		};
+
+		sample-datum-1 {
+			milivolt = <(708 / 3)>;
+			temp = <5>;
+			sample-index = <1>;
+		};
+
+		sample-datum-2 {
+			milivolt = <(682 / 3)>;
+			temp = <10>;
+			sample-index = <2>;
+		};
+
+		sample-datum-3 {
+			milivolt = <(653 / 3)>;
+			temp = <15>;
+			sample-index = <3>;
+		};
+
+		sample-datum-4 {
+			milivolt = <(622 / 3)>;
+			temp = <20>;
+			sample-index = <4>;
+		};
+
+		sample-datum-5 {
+			milivolt = <(589 / 3)>;
+			temp = <25>;
+			sample-index = <5>;
+		};
+
+		sample-datum-6 {
+			milivolt = <(554 / 3)>;
+			temp = <30>;
+			sample-index = <6>;
+		};
+
+		sample-datum-7 {
+			milivolt = <(519 / 3)>;
+			temp = <35>;
+			sample-index = <7>;
+		};
+
+		sample-datum-8 {
+			milivolt = <(483 / 3)>;
+			temp = <40>;
+			sample-index = <8>;
+		};
+
+		sample-datum-9 {
+			milivolt = <(446 / 3)>;
+			temp = <45>;
+			sample-index = <9>;
+		};
+
+		sample-datum-10 {
+			milivolt = <(411 / 3)>;
+			temp = <50>;
+			sample-index = <10>;
+		};
+		sample-datum-11 {
+			milivolt = <(376 / 3)>;
+			temp = <55>;
+			sample-index = <11>;
+		};
+
+		sample-datum-12 {
+			milivolt = <(343 / 3)>;
+			temp = <60>;
+			sample-index = <12>;
+		};
+
+		sample-datum-13 {
+			milivolt = <(312 / 3)>;
+			temp = <65>;
+			sample-index = <13>;
+		};
+
+		sample-datum-14 {
+			milivolt = <(284 / 3)>;
+			temp = <70>;
+			sample-index = <14>;
+		};
+
+		sample-datum-15 {
+			milivolt = <(257 / 3)>;
+			temp = <75>;
+			sample-index = <15>;
+		};
+
+		sample-datum-16 {
+			milivolt = <(232 / 3)>;
+			temp = <80>;
+			sample-index = <16>;
+		};
+
+		sample-datum-17 {
+			milivolt = <(209 / 3)>;
+			temp = <85>;
+			sample-index = <17>;
+		};
+
+		sample-datum-18 {
+			milivolt = <(188 / 3)>;
+			temp = <90>;
+			sample-index = <18>;
+		};
+
+		sample-datum-19 {
+			milivolt = <(169 / 3)>;
+			temp = <95>;
+			sample-index = <19>;
+		};
+
+		sample-datum-20 {
+			milivolt = <(152 / 3)>;
+			temp = <100>;
+			sample-index = <20>;
+		};
+	};
+};
diff --git a/zephyr/program/corsola/usba.dtsi b/zephyr/program/corsola/usba.dtsi
new file mode 100644
index 0000000000..2ecb3b7d5a
--- /dev/null
+++ b/zephyr/program/corsola/usba.dtsi
@@ -0,0 +1,11 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	usba_port_enable_list: usba-port-enable-list {
+		compatible = "cros-ec,usba-port-enable-pins";
+		enable-pins = <&en_pp5000_usb_a0_vbus>;
+	};
+};
diff --git a/zephyr/program/corsola/voltorb/CMakeLists.txt b/zephyr/program/corsola/voltorb/CMakeLists.txt
new file mode 100644
index 0000000000..82fa262bda
--- /dev/null
+++ b/zephyr/program/corsola/voltorb/CMakeLists.txt
@@ -0,0 +1,12 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Voltorb Makeifile
+
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_I2C "../src/npcx_i2c.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC
+                             "../src/npcx_usb_pd_policy.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC
+                             "../src/npcx_usbc.c" "./src/usbc.c")
+zephyr_library_sources("src/board.c")
diff --git a/zephyr/program/corsola/voltorb/project.conf b/zephyr/program/corsola/voltorb/project.conf
new file mode 100644
index 0000000000..19348b04cd
--- /dev/null
+++ b/zephyr/program/corsola/voltorb/project.conf
@@ -0,0 +1,52 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Variant config
+CONFIG_BOARD_VOLTORB=y
+
+# Voltorb only use D2, drop the workaround config for H1
+CONFIG_PLATFORM_EC_BOARD_RESET_AFTER_POWER_ON=n
+
+# No A+Gsensor
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=n
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=n
+CONFIG_PLATFORM_EC_ACCEL_BMA4XX=n
+CONFIG_PLATFORM_EC_ACCEL_FIFO=n
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=n
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=n
+CONFIG_PLATFORM_EC_GMR_TABLET_MODE=n
+CONFIG_PLATFORM_EC_LID_ANGLE=n
+CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=n
+CONFIG_PLATFORM_EC_MOTIONSENSE=n
+CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=n
+CONFIG_PLATFORM_EC_TABLET_MODE=n
+CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=n
+
+# LED
+CONFIG_PLATFORM_EC_LED_COMMON=n
+CONFIG_PLATFORM_EC_LED_ONOFF_STATES=n
+
+# Keyboard
+CONFIG_PLATFORM_EC_KEYBOARD_REFRESH_ROW3=y
+CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI3=y
+CONFIG_PLATFORM_EC_KEYBOARD_STRICT_DEBOUNCE=y
+
+# USBC
+CONFIG_PLATFORM_EC_PD_MAX_CURRENT_MA=3250
+CONFIG_PLATFORM_EC_PD_MAX_POWER_MW=65000
+
+# AC_OK debounce time
+CONFIG_PLATFORM_EC_EXTPOWER_DEBOUNCE_MS=800
+
+# Battery config
+CONFIG_PLATFORM_EC_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV=15000
+CONFIG_PLATFORM_EC_SMART_BATTERY_OPTIONAL_MFG_FUNC=y
+CONFIG_PLATFORM_EC_BATTERY_STBL_STAT=y
+
+# Remove debug options and features for FW QUAL
+CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=n
+CONFIG_PLATFORM_EC_CMD_POWERINDEBUG=n
+CONFIG_LOG=n
+CONFIG_LOG_MODE_MINIMAL=n
+CONFIG_SHELL_MINIMAL=y
diff --git a/zephyr/program/corsola/voltorb/project.overlay b/zephyr/program/corsola/voltorb/project.overlay
new file mode 100644
index 0000000000..aadee5c134
--- /dev/null
+++ b/zephyr/program/corsola/voltorb/project.overlay
@@ -0,0 +1,287 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Corsola program common DTS includes */
+
+#include "../common.dtsi"
+#include "../power_signal.dtsi"
+#include "../usba.dtsi"
+#include "../npcx_adc.dtsi"
+#include "../npcx_gpio.dtsi"
+#include "../npcx_host_interface.dtsi"
+#include "../npcx_i2c.dtsi"
+#include "../npcx_interrupts.dtsi"
+#include "../npcx_keyboard.dtsi"
+#include "../npcx_usbc.dtsi"
+#include "../npcx_default_gpio_pinctrl.dtsi"
+#include <cros/thermistor/thermistor.dtsi>
+#include <dt-bindings/battery.h>
+
+/ {
+	unused-pins {
+		compatible = "unused-gpios";
+
+		unused-gpios =
+			/* base_imu_int_l */
+			<&gpio5 6 0>,
+			/* ec_pen_chg_dis_odl */
+			<&gpioe 4 0>,
+			/* lid_accel_int_l */
+			<&gpiob 3 0>,
+			/* gpio_tablet_mode_l */
+			<&gpiob 2 0>,
+			/* LED3 */
+			<&gpioc 4 0>;
+	};
+
+	batteries {
+		default_battery: lgc_ap18c8k {
+			compatible = "lgc,ap18c8k", "battery-smart";
+		};
+		cosmx_ap20cbl-2 {
+			compatible = "cosmx,ap20cbl-2", "battery-smart";
+		};
+		lgc_ap19b8k {
+			compatible = "lgc,ap19b8k", "battery-smart";
+		};
+		panasonic_ap19b5k {
+			compatible = "panasonic,ap19b5k", "battery-smart";
+		};
+		smp_ap18c7k {
+			compatible = "smp,ap18c7k", "battery-smart";
+		};
+	};
+
+	cros-keyscan {
+		compatible = "cros-ec,keyscan";
+
+		debounce-down = <20000>;
+		debounce-up = <20000>;
+
+		actual-key-mask = <
+			0x1c	/* C0 */
+			0xff	/* C1 */
+			0xff	/* C2 */
+			0xff	/* C3 */
+			0xff	/* C4 */
+			0xf5	/* C5 */
+			0xff	/* C6 */
+			0xa4	/* C7 */
+			0xff	/* C8 */
+			0xfe	/* C9 */
+			0x55	/* C10 */
+			0xfa	/* C11 */
+			0xca	/* C12 */
+		>;
+	};
+
+	led_colors: led-colors {
+		compatible = "cros-ec,led-policy";
+
+		/* Voltorb LED bat charge */
+		bat-power-state-charge {
+			charge-state = "LED_PWRS_CHARGE";
+			/* Battery display percent range (>= Empty, <= 99%) */
+			batt-lvl = <BATTERY_LEVEL_EMPTY 99>;
+
+			color-0 {
+				led-color = <&color_amber>;
+			};
+		};
+
+		/* Voltorb LED bat charge near full */
+		bat-power-state-charge-near-full {
+			charge-state = "LED_PWRS_CHARGE_NEAR_FULL";
+
+			color-0 {
+				led-color = <&color_blue>;
+			};
+		};
+
+		/* Voltorb LED bat discharge */
+		bat-power-state-discharge-s0 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S0";
+
+			color-0 {
+				led-color = <&color_blue>;
+			};
+		};
+		bat-power-state-discharge-s3 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S3";
+
+			color-0 {
+				led-color = <&color_amber>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <3000>;
+			};
+		};
+		bat-power-state-discharge-s5 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S5";
+
+			color-0 {
+				led-color = <&color_off>;
+			};
+		};
+
+		/* Voltorb LED bat error */
+		bat-power-state-error {
+			charge-state = "LED_PWRS_ERROR";
+
+			color-0 {
+				led-color = <&color_amber>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <1000>;
+			};
+		};
+
+		/* Voltorb LED power idle */
+		power-state-idle {
+			charge-state = "LED_PWRS_IDLE";
+
+			color-0 {
+				led-color = <&color_blue>;
+			};
+		};
+
+		/* Voltorb LED power forced idle */
+		power-state-forced-idle {
+			charge-state = "LED_PWRS_FORCED_IDLE";
+
+			color-0 {
+				led-color = <&color_amber>;
+				period-ms = <2000>;
+			};
+			color-1 {
+				led-color = <&color_blue>;
+				period-ms = <2000>;
+			};
+		};
+	};
+
+	pwmleds {
+		compatible = "pwm-leds";
+
+		led_amber: ec_led1_odl {
+			pwms = <&pwm0 0 PWM_HZ(100) PWM_POLARITY_INVERTED>;
+		};
+
+		led_blue: ec_led2_odl {
+			pwms = <&pwm1 0 PWM_HZ(100) PWM_POLARITY_INVERTED>;
+		};
+	};
+
+	pwm-led-pins {
+		compatible = "cros-ec,pwm-led-pins";
+
+		battery_led: battery-led {
+			led-id = "EC_LED_ID_BATTERY_LED";
+			led-pwms = <&led_amber &led_blue>;
+
+			color_off: color-off {
+				led-color = "LED_OFF";
+				led-values = <0 0>;
+			};
+
+			color_amber: color-amber {
+				led-color = "LED_AMBER";
+				br-color = "EC_LED_COLOR_AMBER";
+				led-values = <100 0>;
+			};
+
+			color_blue: color_blue {
+				led-color = "LED_BLUE";
+				br-color = "EC_LED_COLOR_BLUE";
+				led-values = <0 100>;
+			};
+		};
+	};
+
+	/* temp sensors */
+	named-adc-channels {
+		adc_temp_charger: temp-charger {
+			enum-name = "ADC_TEMP_SENSOR_CHARGER";
+			io-channels = <&adc0 8>;
+		};
+	};
+
+	temp_charger_thermistor: charger-thermistor {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_charger>;
+	};
+
+	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
+		temp_sensor_charger: charger-thermistor {
+			temp_host_halt = <75>;
+			temp_host_release_halt = <65>;
+			sensor = <&temp_charger_thermistor>;
+		};
+	};
+};
+
+/* Amber LED */
+&pwm0_gpc3 {
+	drive-open-drain;
+};
+
+&pwm0 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm0_gpc3>;
+	pinctrl-names = "default";
+};
+
+/* Blue LED */
+&pwm1_gpc2 {
+	drive-open-drain;
+};
+
+&pwm1 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm1_gpc2>;
+	pinctrl-names = "default";
+};
+
+/* gpio overrides */
+/ {
+	named-gpios {
+		/delete-node/ base_imu_int_l;
+		/delete-node/ ec_pen_chg_dis_odl;
+		/delete-node/ lid_accel_int_l;
+		/delete-node/ gpio_tablet_mode_l;
+	};
+};
+
+/* interrupts overrides */
+/ {
+	gpio-interrupts {
+		/delete-node/ base_imu;
+		/delete-node/ tablet_mode;
+	};
+};
+
+&thermistor_3V3_51K1_47K_4050B {
+	status = "okay";
+};
+
+/* adc0 overrides */
+&adc0 {
+	pinctrl-0 = <&adc0_chan0_gp45
+		     &adc0_chan1_gp44
+		     &adc0_chan2_gp43
+		     &adc0_chan3_gp42
+		     &adc0_chan8_gpf1>;
+};
diff --git a/zephyr/program/corsola/voltorb/src/board.c b/zephyr/program/corsola/voltorb/src/board.c
new file mode 100644
index 0000000000..d1d7f0350e
--- /dev/null
+++ b/zephyr/program/corsola/voltorb/src/board.c
@@ -0,0 +1,41 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_state.h"
+#include "common.h"
+#include "dps.h"
+#include "math_util.h"
+
+#include <zephyr/logging/log.h>
+
+#include <dt-bindings/battery.h>
+
+LOG_MODULE_REGISTER(board_init, LOG_LEVEL_ERR);
+
+bool voltorb_is_more_efficient(int curr_mv, int prev_mv, int batt_mv,
+			       int batt_mw, int input_mw)
+{
+	int batt_state;
+
+	battery_status(&batt_state);
+
+	/* Choose 15V PDO or higher when battery is full. */
+	if ((batt_state & SB_STATUS_FULLY_CHARGED) && (curr_mv >= 15000) &&
+	    (prev_mv < 15000 || curr_mv <= prev_mv)) {
+		return true;
+	} else {
+		return ABS(curr_mv - batt_mv) < ABS(prev_mv - batt_mv);
+	}
+}
+
+__override struct dps_config_t dps_config = {
+	.k_less_pwr = 93,
+	.k_more_pwr = 96,
+	.k_sample = 1,
+	.k_window = 3,
+	.t_stable = 10 * SECOND,
+	.t_check = 5 * SECOND,
+	.is_more_efficient = &voltorb_is_more_efficient,
+};
diff --git a/zephyr/program/corsola/voltorb/src/usbc.c b/zephyr/program/corsola/voltorb/src/usbc.c
new file mode 100644
index 0000000000..ef850811f4
--- /dev/null
+++ b/zephyr/program/corsola/voltorb/src/usbc.c
@@ -0,0 +1,108 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_state.h"
+#include "chipset.h"
+#include "console.h"
+#include "hooks.h"
+#include "usb_pd.h"
+#include "usb_tc_sm.h"
+
+#define CPRINTS(format, args...) cprints(CC_USB, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args)
+
+#define BATT_LVL_CURRENT_LIMITED 30 /* Battery percent(%) */
+
+#define PDO_FIXED_FLAGS \
+	(PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP | PDO_FIXED_COMM_CAP)
+
+static bool current_limited;
+
+static const uint32_t pd_src_pdo_1A5[] = {
+	PDO_FIXED(5000, 1500, PDO_FIXED_FLAGS),
+};
+
+static const uint32_t pd_src_pdo_3A[] = {
+	PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS),
+};
+
+int dpm_get_source_pdo(const uint32_t **src_pdo, const int port)
+{
+	if (current_limited) {
+		*src_pdo = pd_src_pdo_1A5;
+		return ARRAY_SIZE(pd_src_pdo_1A5);
+	}
+
+	*src_pdo = pd_src_pdo_3A;
+
+	return ARRAY_SIZE(pd_src_pdo_3A);
+}
+
+static void update_src_pdo_deferred(void);
+DECLARE_DEFERRED(update_src_pdo_deferred);
+static void update_src_pdo_deferred(void)
+{
+	int i;
+	static int check_cnt;
+
+	if (chipset_in_state(CHIPSET_STATE_SUSPEND) &&
+	    (charge_get_percent() < BATT_LVL_CURRENT_LIMITED)) {
+		/* In S3, battery < 30%, set src pdo to 1A5 */
+		current_limited = true;
+
+		for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+			if (tc_is_attached_src(i)) {
+				CPRINTS("Set C%d src pdo 1A5", i);
+				pd_update_contract(i);
+			}
+		}
+
+		hook_call_deferred(&update_src_pdo_deferred_data, -1);
+	} else if (chipset_in_state(CHIPSET_STATE_SUSPEND) &&
+		   (charge_get_percent() >= BATT_LVL_CURRENT_LIMITED)) {
+		/* In S3, battery >= 30%, check the battery every 60s */
+		hook_call_deferred(&update_src_pdo_deferred_data, 60 * SECOND);
+	} else if (chipset_in_state(CHIPSET_STATE_ON)) {
+		/* Resume src pdo to 3A */
+		current_limited = false;
+
+		for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+			if (tc_is_attached_src(i))
+				pd_update_contract(i);
+		}
+
+		hook_call_deferred(&update_src_pdo_deferred_data, -1);
+	} else if (check_cnt < 3) {
+		/* Check 3 times for stable power state */
+		check_cnt++;
+		hook_call_deferred(&update_src_pdo_deferred_data, 10 * SECOND);
+	} else {
+		check_cnt = 0;
+		current_limited = false;
+		hook_call_deferred(&update_src_pdo_deferred_data, -1);
+	}
+}
+
+static void check_src_port(void)
+{
+	int i;
+
+	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+		if (tc_is_attached_src(i)) {
+			/* Deferred 2s to avoid pd state conflict */
+			hook_call_deferred(&update_src_pdo_deferred_data,
+					   2 * SECOND);
+			break;
+		}
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, check_src_port, HOOK_PRIO_DEFAULT);
+
+static void resume_src_port(void)
+{
+	/* Deferred 2s to avoid pd state conflict */
+	hook_call_deferred(&update_src_pdo_deferred_data, 2 * SECOND);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, resume_src_port, HOOK_PRIO_DEFAULT);
diff --git a/zephyr/program/dev/BUILD.py b/zephyr/program/dev/BUILD.py
new file mode 100644
index 0000000000..635b6398e7
--- /dev/null
+++ b/zephyr/program/dev/BUILD.py
@@ -0,0 +1,13 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Project used for Zephyr development."""
+
+register_host_project(
+    project_name="dev-posix",
+    zephyr_board="native_posix",
+    dts_overlays=[
+        "dev.dtsi",
+    ],
+)
diff --git a/zephyr/program/dev/CMakeLists.txt b/zephyr/program/dev/CMakeLists.txt
new file mode 100644
index 0000000000..91ccb8c30d
--- /dev/null
+++ b/zephyr/program/dev/CMakeLists.txt
@@ -0,0 +1,11 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.20.5)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(ec)
+
+target_sources(app PRIVATE src/stubs.c)
+
+zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}/include")
diff --git a/zephyr/program/dev/README.md b/zephyr/program/dev/README.md
new file mode 100644
index 0000000000..6afd553a28
--- /dev/null
+++ b/zephyr/program/dev/README.md
@@ -0,0 +1,21 @@
+# Minimal Example Zephyr EC Project
+
+This directory is intended to be an extremely minimal example of a
+project.  Should you like, you can use it as a bring up a new program,
+or as reference as you require.
+
+If you're bringing up a new variant of a program, you don't need a
+whole project directory with a `BUILD.py` and all, and this example is
+likely not of use to you.  Check out the [project config
+documentation] for instructions on adding a new variant.
+
+[project config documentation]: ../../../docs/zephyr/project_config.md
+
+# Building
+
+To build the `native_posix` example, run:
+
+``` shellsession
+(chroot) $ zmake build dev-posix
+```
+
diff --git a/zephyr/program/dev/dev.dtsi b/zephyr/program/dev/dev.dtsi
new file mode 100644
index 0000000000..affe947bbe
--- /dev/null
+++ b/zephyr/program/dev/dev.dtsi
@@ -0,0 +1,150 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <board-overlays/native_posix.dts>
+
+/ {
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		adc_charger: charger {
+			enum-name = "ADC_TEMP_SENSOR_CHARGER";
+			io-channels = <&adc0 0>;
+		};
+	};
+
+	named-gpios {
+		ec_batt_pres_odl {
+			gpios = <&gpio0 28 GPIO_INPUT>;
+			enum-name = "GPIO_BATT_PRES_ODL";
+		};
+		gpio_usb_c0_bc12_int_l: usb_c0_bc12_int_l {
+			gpios = <&gpio0 10 GPIO_INPUT>;
+		};
+		gpio_usb_c0_ppc_int: usb_c0_ppc_int {
+			gpios = <&gpio0 14 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_acok_od: acok_od {
+			gpios = <&gpio0 0 GPIO_INPUT>;
+			enum-name = "GPIO_AC_PRESENT";
+		};
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+		accel-0 {
+			i2c-port = <&i2c0>;
+			enum-names = "I2C_PORT_ACCEL",  "I2C_PORT_BATTERY";
+		};
+
+	};
+
+	adc0: adc {
+		compatible = "zephyr,adc-emul";
+		nchannels = <6>;
+		ref-internal-mv = <3300>;
+		#io-channel-cells = <1>;
+		status = "okay";
+	};
+
+	batteries {
+		default_battery: lgc_ac17a8m {
+			compatible = "lgc,ac17a8m", "battery-smart";
+			/**
+			 * this has to be strictly lower than the desired
+			 * voltage in smart battery emulator (5000mV).
+			 */
+			voltage_min = <4000>;
+		};
+	};
+
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_usb_c0_bc12: usb_c0_bc12 {
+			irq-pin = <&gpio_usb_c0_bc12_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "usb0_evt";
+		};
+		int_ac_present: ac_present {
+			irq-pin = <&gpio_acok_od>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "extpower_interrupt";
+		};
+	};
+
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+			bc12 = <&pi3usb9201_emul0>;
+			chg = <&isl923x_emul>;
+			tcpc = <&tcpci_emul>;
+			ppc = <&sn5s330_emul>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&tcpci_mux_c0
+					     &virtual_mux_c0>;
+			};
+		};
+		port0-muxes {
+			tcpci_mux_c0: tcpci-mux-c0 {
+				compatible = "cros-ec,usbc-mux-tcpci";
+			};
+			virtual_mux_c0: virtual-mux-c0 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+	};
+};
+
+&i2c0 {
+	battery: sb@b {
+		compatible = "zephyr,smart-battery-emul";
+		reg = <0xb>;
+		cycle-count = <99>;
+		version = "BATTERY_SPEC_VER_1_1_WITH_PEC";
+		/* Real battery voltages are multiples of 4.4V. */
+		desired-charg-volt = <5000>;
+		desired-charg-cur = <1000>;
+		mf-name = "LGC";
+		dev-name = "AC17A8M";
+	};
+
+	bmi_i2c: bmi@68 {
+		compatible = "bosch,bmi160";
+		reg = <0x68>;
+	};
+
+	isl923x_emul: isl923x@9 {
+		compatible = "cros,isl923x-emul";
+		status = "okay";
+		reg = <0x9>;
+		battery = <&battery>;
+	};
+
+	pi3usb9201_emul0: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		reg = <0x5f>;
+		irq = <&int_usb_c0_bc12>;
+	};
+
+	sn5s330_emul: sn5s330@40 {
+		compatible = "cros,sn5s330-emul";
+		reg = <0x40>;
+		int-pin = <&gpio_usb_c0_ppc_int>;
+	};
+
+	tcpci_emul: tcpci_emul@2 {
+		compatible = "cros,tcpci-generic-emul";
+		status = "okay";
+		reg = <0x2>;
+		irq-gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
+		rst-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
+	};
+};
diff --git a/zephyr/program/dev/prj.conf b/zephyr/program/dev/prj.conf
new file mode 100644
index 0000000000..f9aae9a370
--- /dev/null
+++ b/zephyr/program/dev/prj.conf
@@ -0,0 +1,44 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_PLATFORM_EC=y
+CONFIG_CROS_EC=y
+CONFIG_SHIMMED_TASKS=y
+CONFIG_SYSCON=y
+
+# Disable default features we don't want in a minimal example.
+CONFIG_NAMED_ADC_CHANNELS=n
+CONFIG_PWM=n
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
+CONFIG_PLATFORM_EC_KEYBOARD=n
+CONFIG_PLATFORM_EC_POWER_BUTTON=n
+CONFIG_PLATFORM_EC_SWITCH=n
+CONFIG_PLATFORM_EC_VBOOT_EFS2=n
+CONFIG_PLATFORM_EC_VBOOT_HASH=n
+
+CONFIG_PLATFORM_EC=y
+CONFIG_PLATFORM_EC_HOOKS=y
+CONFIG_PLATFORM_EC_HOSTCMD=y
+CONFIG_PLATFORM_EC_CHARGER=y
+CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y
+
+CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y
+
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=10
+CONFIG_PLATFORM_EC_CHARGER_ISL9238=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_CHARGER=y
+CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y
+
+CONFIG_PLATFORM_EC_USB_PD_TCPM_MUX=y
+
+CONFIG_NATIVE_UART_0_ON_STDINOUT=y
+
+CONFIG_SENSOR=y
+CONFIG_I2C=y
+CONFIG_BMI160_TRIGGER_NONE=y
+CONFIG_EMUL_BC12_DETECT_PI3USB9201=y
+
+# Emulators have all the same priority so this can't be used.
+CONFIG_CHECK_INIT_PRIORITIES=n
diff --git a/zephyr/program/dev/src/stubs.c b/zephyr/program/dev/src/stubs.c
new file mode 100644
index 0000000000..488289c7e4
--- /dev/null
+++ b/zephyr/program/dev/src/stubs.c
@@ -0,0 +1,27 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Fakes for dev-posix which will be updated as work progresses
+ */
+
+#include "usb_pd.h"
+
+int board_set_active_charge_port(int port)
+{
+	return 0;
+}
+
+int pd_check_vconn_swap(int port)
+{
+	return 0;
+}
+
+void pd_power_supply_reset(int port)
+{
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	return 0;
+}
diff --git a/zephyr/program/framework/BUILD.py b/zephyr/program/framework/BUILD.py
new file mode 100644
index 0000000000..d491ec83cd
--- /dev/null
+++ b/zephyr/program/framework/BUILD.py
@@ -0,0 +1,30 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+def register_framework_project(
+    project_name,
+    chip="npcx9m3f",
+):
+    """Register a variant of lotus."""
+    register_func = register_npcx_project
+
+    return register_func(
+        project_name=project_name,
+        zephyr_board=chip,
+        dts_overlays=[here / project_name / "project.overlay"],
+        kconfig_files=[
+            here / "program.conf",
+            here / project_name / "project.conf",
+        ],
+    )
+
+lotus = register_framework_project(
+    project_name="lotus",
+    chip="npcx9m3f",
+)
+
+azalea = register_framework_project(
+    project_name="azalea",
+    chip="npcx9m3f",
+)
diff --git a/zephyr/program/framework/CMakeLists.txt b/zephyr/program/framework/CMakeLists.txt
new file mode 100644
index 0000000000..f5848ef5b7
--- /dev/null
+++ b/zephyr/program/framework/CMakeLists.txt
@@ -0,0 +1,75 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.20.5)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+
+zephyr_library_sources("src/adc.c")
+zephyr_library_sources("src/board_function.c")
+zephyr_library_sources("src/board_host_command.c")
+zephyr_library_sources("src/cypress_pd_common.c")
+zephyr_library_sources("src/flash_storage.c")
+zephyr_library_sources("src/factory.c")
+zephyr_library_sources("src/uefi_app_mode.c")
+zephyr_library_sources("src/diagnostics.c")
+zephyr_library_sources("src/ucsi.c")
+zephyr_library_sources("src/als.c")
+zephyr_library_sources("src/hid_device.c")
+zephyr_library_sources("src/common_cpu_power.c")
+
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LED_COMMON
+	"src/led_pwm.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LED_COMMON
+	"src/led.c")
+
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGE_MANAGER
+	"src/battery_extender.c")
+
+
+if(DEFINED CONFIG_BOARD_LOTUS)
+	project(lotus)
+	cros_ec_library_include_directories_ifdef(CONFIG_BOARD_LOTUS include)
+	zephyr_include_directories("include/lotus")
+	zephyr_library_sources(
+			"lotus/src/battery.c"
+			"lotus/src/charger.c"
+			"lotus/src/cpu_power.c"
+			"lotus/src/input_module.c"
+			"lotus/src/gpu.c"
+			"lotus/src/power_sequence.c"
+			"lotus/src/f75303.c"
+			"lotus/src/fan.c"
+			"lotus/src/project_diagnostics.c"
+			"lotus/src/power_button_x86.c"
+			"lotus/src/amd_r23m.c"
+			"lotus/src/ej889i.c"
+			"lotus/src/thermal.c"
+			"lotus/src/gpu_configuration.c"
+			"lotus/src/gpu_f75303.c"
+			"src/temperature_filter.c"
+
+
+
+	)
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_AMD_STT
+	"lotus/src/stt.c")
+
+endif()
+if(DEFINED CONFIG_BOARD_AZALEA)
+	project(azalea)
+	cros_ec_library_include_directories_ifdef(CONFIG_BOARD_AZALEA include)
+	zephyr_include_directories("include/azalea")
+	zephyr_library_sources(
+			"azalea/src/battery.c"
+			"azalea/src/charger.c"
+			"azalea/src/cpu_power.c"
+			"azalea/src/power_sequence.c"
+			"azalea/src/keyboard_customization.c"
+			"azalea/src/project_diagnostics.c"
+			"azalea/src/power_button_x86.c"
+	)
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_AMD_STT
+	"azalea/src/stt.c")
+
+endif()
diff --git a/zephyr/program/framework/Kconfig b/zephyr/program/framework/Kconfig
new file mode 100644
index 0000000000..8301624c07
--- /dev/null
+++ b/zephyr/program/framework/Kconfig
@@ -0,0 +1,21 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config BOARD_LOTUS
+	bool "Framework Lotus Board"
+	help
+	  Build Framework Lotus reference board. Lotus has AMD SoC
+	  with NPCX993FA0BX EC.
+
+config BOARD_AZALEA
+	bool "Framework Azalea Board"
+	help
+	  Build Framework Azalea reference board. Azalea has AMD SoC
+	  with NPCX993FA0BX EC.
+
+module = FRAMEWORK
+module-str = Framework board-specific code
+source "subsys/logging/Kconfig.template.log_config"
+
+source "Kconfig.zephyr"
diff --git a/zephyr/program/framework/README.md b/zephyr/program/framework/README.md
new file mode 100644
index 0000000000..7e5237718e
--- /dev/null
+++ b/zephyr/program/framework/README.md
@@ -0,0 +1,20 @@
+# Minimal Example Zephyr EC Project
+
+This directory is intended to be an extremely minimal example of a
+project.  Should you like, you can use it as a bring up a new program,
+or as reference as you require.
+
+If you're bringing up a new variant of a program, you don't need a
+whole project directory with a `BUILD.py` and all, and this example is
+likely not of use to you.  Check out the [project config
+documentation] for instructions on adding a new variant.
+
+[project config documentation]: ../../../docs/zephyr/project_config.md
+
+# Building
+
+To build the NPCX9 example, run:
+
+``` shellsession
+(chroot) $ zmake build lotus
+```
diff --git a/zephyr/program/framework/azalea/adc.dtsi b/zephyr/program/framework/azalea/adc.dtsi
new file mode 100644
index 0000000000..f944e0d7e1
--- /dev/null
+++ b/zephyr/program/framework/azalea/adc.dtsi
@@ -0,0 +1,48 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <cros/thermistor/thermistor.dtsi>
+
+/ {
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		adc_main_boardid: main-boardid {
+			enum-name = "ADC_MAIN_BOARD_ID";
+			io-channels = <&adc0 0>;
+		};
+		adc_i_sys: i-sys {
+			enum-name = "ADC_PSYS";
+			io-channels = <&adc0 4>;
+		};
+		adc_i_adp: i-adp {
+			enum-name = "ADC_ADAPTER_CURRENT";
+			io-channels = <&adc0 5>;
+		};
+		adc_tp_board_id: tp_board_id {
+			enum-name = "ADC_TOUCHPAD_ID";
+			io-channels = <&adc0 7>;
+		};
+		adc_audio_board_id: audio_board_id {
+			enum-name = "ADC_AUDIO_ID";
+			io-channels = <&adc0 8>;
+		};
+		adc_vcin1_batt_temp: vcin1_batt_temp {
+			enum-name = "ADC_VCIN1_BATT_TEMP";
+			io-channels = <&adc0 9>;
+		};
+	};
+};
+
+&adc0 {
+	status = "okay";
+	pinctrl-0 = <&adc0_chan0_gp45
+		     &adc0_chan4_gp41
+		     &adc0_chan5_gp37
+		     &adc0_chan7_gpe1
+		     &adc0_chan8_gpf1
+		     &adc0_chan9_gpf0>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/framework/azalea/battery.dtsi b/zephyr/program/framework/azalea/battery.dtsi
new file mode 100644
index 0000000000..0d99f791ce
--- /dev/null
+++ b/zephyr/program/framework/azalea/battery.dtsi
@@ -0,0 +1,15 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	batteries {
+		default_battery: atl_framework55w {
+			compatible = "atl,framework55w", "battery-smart";
+		};
+		atl_framework61w {
+			compatible = "atl,framework61w", "battery-smart";
+		};
+	};
+};
diff --git a/zephyr/program/framework/azalea/fan.dtsi b/zephyr/program/framework/azalea/fan.dtsi
new file mode 100644
index 0000000000..a9b97d3bb9
--- /dev/null
+++ b/zephyr/program/framework/azalea/fan.dtsi
@@ -0,0 +1,39 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	fans {
+		compatible = "cros-ec,fans";
+
+		fan0: fan_0 {
+			pwms = <&pwm0 0 PWM_KHZ(25) PWM_POLARITY_NORMAL>;
+			tach = <&tach2>;
+			rpm_min = <2100>;
+			rpm_start = <2100>;
+			rpm_max = <6800>;
+			rpm_deviation = <3>;
+			pgood_gpio = <&gpio_slp_s3_l>;
+		};
+	};
+};
+/* Tachemeter for fan speed measurement */
+&tach2 {
+	status = "okay";
+	pinctrl-0 = <&ta2_1_in_gp73>;
+	pinctrl-names = "default";
+	port = <NPCX_TACH_PORT_A>; /* port-B is selected */
+	sample-clk = <NPCX_TACH_FREQ_LFCLK>; /* Use LFCLK as sampling clock */
+	pulses-per-round = <2>; /* number of pulses per round of encoder */
+};
+
+&pwm0_gpc3 {
+	drive-open-drain;
+};
+
+&pwm0 {
+	status = "okay";
+	pinctrl-0 = <&pwm0_gpc3>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/framework/azalea/gpio.dtsi b/zephyr/program/framework/azalea/gpio.dtsi
new file mode 100644
index 0000000000..31439b0d89
--- /dev/null
+++ b/zephyr/program/framework/azalea/gpio.dtsi
@@ -0,0 +1,238 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	aliases {
+		gpio-check-fp-control = &gpio_fp_control;
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l {
+			gpios = <&gpio5 6 (GPIO_OUTPUT_LOW | GPIO_VOLTAGE_1P8)>;
+		};
+		ec_espi_rst_l {
+			gpios = <&gpio5 4 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		rtc_dis {
+			gpios = <&gpioc 6 GPIO_OUTPUT_LOW>;	/* RTC discharge */
+		};
+		gpio_ec_sci_l: ec_sci_l {
+			gpios = <&gpio7 6 GPIO_ODR_HIGH>;	/* Reserved */
+		};
+		otg_en {
+			gpios = <&gpioc 5 GPIO_OUTPUT_LOW>;
+		};
+		ec_smb_ck0 {
+			gpios = <&gpiob 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		ec_smb_da0 {
+			gpios = <&gpiob 4 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		ec_smb_ck1 {
+			gpios = <&gpio9 0 GPIO_INPUT>;
+		};
+		ec_smb_da1 {
+			gpios = <&gpio8 7 GPIO_INPUT>;
+		};
+		ec_smb_ck2 {
+			gpios = <&gpio9 2 GPIO_INPUT>;
+		};
+		ec_smb_da2 {
+			gpios = <&gpio9 1 GPIO_INPUT>;
+		};
+		ec_smb_ck3 {
+			gpios = <&gpiod 1 GPIO_INPUT>;
+		};
+		ec_smb_da3 {
+			gpios = <&gpiod 0 GPIO_INPUT>;
+		};
+		ec_smb_ck4 {
+			gpios = <&gpiof 3 GPIO_INPUT>;
+		};
+		ec_smb_da4 {
+			gpios = <&gpiof 2 GPIO_INPUT>;
+		};
+		ec_smb_ck7 {
+			gpios = <&gpiob 3 GPIO_INPUT>;
+		};
+		ec_smb_da7 {
+			gpios = <&gpiob 2 GPIO_INPUT>;
+		};
+		gpio_mic_sw: mic_sw {
+			gpios = <&gpioc 1 GPIO_INPUT>;
+		};
+		gpio_on_off_btn_l: on_off_btn_l {
+			gpios = <&gpiod 2 GPIO_INPUT>;		/* PSL in1 signal, power button */
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		gpio_chassis_open_l: chassis_open_l {
+			gpios = <&gpio0 0 GPIO_INPUT>;		/* PSL in2 signal, chassis open */
+		};
+		gpio_hw_acav_in: hw_acav_in {
+			gpios = <&gpio0 1 GPIO_INPUT>;		/* PSL in3 signal, ac present pin */
+			enum-name = "GPIO_AC_PRESENT";
+		};
+		gpio_lid_sw_l: lid_sw_l {
+			gpios = <&gpio0 2 GPIO_INPUT>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+		gpio_0p75_1p8valw_pwren: 0p75_1p8valw_pwren {
+			gpios = <&gpiod 7 GPIO_OUTPUT_LOW>;
+		};
+		gpio_module_pwr_on: moduel_pwr_on {
+			gpios = <&gpio8 6 GPIO_OUTPUT_LOW>;
+		};
+		als_int_l {
+			gpios = <&gpio7 5 GPIO_INPUT>;
+		};
+		gpio_pch_pwr_en: pch_pwr_en {
+			gpios = <&gpiod 4 GPIO_OUTPUT_LOW>;
+		};
+		gpio_h_prochot_l: h_prochot_l {
+			gpios = <&gpioa 1 GPIO_ODR_HIGH>;
+		};
+		gpio_slp_s3_l: slp_s3_l {
+			gpios = <&gpioa 3 GPIO_INPUT>;
+			enum-name = "GPIO_PCH_SLP_S3_L";
+		};
+		gpio_slp_s5_l: slp_s5_l {
+			gpios = <&gpio9 5 GPIO_INPUT>;
+			enum-name = "GPIO_PCH_SLP_S5_L";
+		};
+		gpio_cam_en: cam_en {
+			gpios = <&gpio6 7 GPIO_OUTPUT_LOW>;
+		};
+		gpio_sys_pwrgd_ec: sys_pwrgd_ec {
+			gpios = <&gpio7 0 GPIO_OUTPUT_LOW>;
+		};
+		gpio_vr_on: vr_on {
+			gpios = <&gpio6 2 GPIO_OUTPUT_LOW>;
+		};
+		gpio_susp_l: susp_l {
+			gpios = <&gpio6 3 GPIO_OUTPUT_LOW>;
+		};
+		gpio_left_side: left_side {
+			gpios = <&gpio4 0 GPIO_OUTPUT_LOW>;	/* left side LED follow IFGA3 */
+		};
+		gpio_right_side: right_side {
+			gpios = <&gpiod 3 GPIO_OUTPUT_LOW>;	/* right side LED follow IFGA3 */
+		};
+		gpio_syson: syson {
+			gpios = <&gpioa 6 GPIO_OUTPUT_LOW>;
+		};
+		gpio_cap_led: cap_led {
+			gpios = <&gpiob 1 GPIO_OUTPUT_LOW>;
+		};
+		en_3v_chgrtc {
+			gpios = <&gpio4 4 GPIO_OUTPUT_LOW>;	/* reserved */
+		};
+		ac_present_pd_l {
+			gpios = <&gpio4 3 GPIO_INPUT>;		/* Monitor AC present from PD */
+		};
+		ec_beep {
+			gpios = <&gpio4 2 GPIO_OUTPUT_LOW>;	/* reserved */
+		};
+		gpio_fp_control: fp_control {
+			gpios = <&gpio3 4 GPIO_INPUT>;		/* Finger Printer feature */
+		};
+		enbkl_apu {
+			gpios = <&gpioe 0 GPIO_INPUT>;		/* monitor APU EDP BKL */
+		};
+		gpio_sm_panel_bken_ec: ec_bkoff_l {
+			gpios = <&gpioc 7 GPIO_OUTPUT_LOW>;
+		};
+		gpio_0p75vs_pwr_en: 0p75vs_pwr_en {
+			gpios = <&gpioa 2 GPIO_OUTPUT_LOW>;
+		};
+		gpio_apu_aud_pwr_en: apu_aud_pwr_en {
+			gpios = <&gpioa 0 GPIO_OUTPUT_LOW>;
+		};
+		i2c_int_tp_l {
+			gpios = <&gpioa 4 GPIO_INPUT>;		/* HUB board TP module */
+		};
+		gpio_apu_ec_int_l: apu_ec_int_l {
+			gpios = <&gpio9 6 GPIO_ODR_HIGH>;	/* EC notify host HID interrupt */
+		};
+		gpio_apu_ec_int2_l: apu_ec_int2_l {
+			gpios = <&gpio7 4 GPIO_ODR_HIGH>;	/* EC notify host HID interrupt 2*/
+		};
+		gpio_cam_sw: cam_sw {
+			gpios = <&gpio9 3 GPIO_INPUT>;
+		};
+		gpio_spok: pwr_3v5v_pg {
+			gpios = <&gpio9 4 GPIO_INPUT>;		/* Monitor 3VALW PWR OK */
+			enum-name = "GPIO_POWER_GOOD_3VALW";
+		};
+		gpio_vr_pwrgd: apu_core_pwrgd {
+			gpios = <&gpio9 7 GPIO_INPUT>;
+			enum-name = "GPIO_POWER_GOOD_VR";
+		};
+		gpio_ec_mute_l: ec_mute_l {
+			gpios = <&gpioa 5 GPIO_INPUT>;
+		};
+		gpio_ssd_pwr_en: ssd_pwr_en {
+			gpios = <&gpiob 0 GPIO_OUTPUT_LOW>;
+		};
+		gpio_wl_rst_l: wl_rst_l {
+			gpios = <&gpio6 1 GPIO_OUTPUT_LOW>;
+		};
+		gpio_wlan_en: wlan_en {
+			gpios = <&gpio7 2 GPIO_OUTPUT_LOW>;
+		};
+		ec_acc_int_l {
+			gpios = <&gpiod 5 GPIO_INPUT>;
+		};
+		gpio_pd_chip1_interrupt: pd_b_i2c_int_ec_l {
+			gpios = <&gpioe 2 GPIO_INPUT>;
+			enum-name = "GPIO_EC_PD_INTB_L";
+		};
+		gpio_pd_chip0_interrupt: pd_a_i2c_int_ec_l {
+			gpios = <&gpioe 5 GPIO_INPUT>;
+			enum-name = "GPIO_EC_PD_INTA_L";
+		};
+		gpio_pbtn_out: pbtn_out_l {
+			gpios = <&gpio5 0 (GPIO_ODR_LOW | GPIO_VOLTAGE_1P8)>;
+			enum-name = "GPIO_PCH_PWRBTN_L";
+		};
+		thermtrip {
+			gpios = <&gpio8 1 GPIO_INPUT>;
+		};
+
+		/* unimplemented GPIOs */
+		entering-rw {
+			enum-name = "GPIO_ENTERING_RW";
+		};
+	};
+};
+
+/* PSL input pads*/
+&psl_in1_gpd2 {
+	/* Power button */
+	psl-in-mode = "edge";
+	psl-in-pol = "low-falling";
+};
+
+&psl_in3_gp01 {
+	/* ac present */
+	psl-in-mode = "edge";
+	psl-in-pol = "high-rising";
+};
+
+/* Power domain device controlled by PSL (Power Switch Logic) IO pads */
+/* Ignored the PSL in 2 (chassis open) at proto phase */
+&power_ctrl_psl {
+	status = "okay";
+	pinctrl-names = "sleep";
+	pinctrl-0 = <&psl_in1_gpd2 &psl_in3_gp01>;
+};
+
+/* host interface */
+&espi0 {
+	status = "okay";
+	pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/framework/azalea/i2c.dtsi b/zephyr/program/framework/azalea/i2c.dtsi
new file mode 100644
index 0000000000..580fec2aa0
--- /dev/null
+++ b/zephyr/program/framework/azalea/i2c.dtsi
@@ -0,0 +1,186 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+ #include <dt-bindings/usb_pd_tcpm.h>
+
+/ {
+	aliases {
+		i2c-0 = &i2c0_0;
+		i2c-1 = &i2c1_0;
+		i2c-2 = &i2c2_0;
+		i2c-3 = &i2c3_0;
+		i2c-4 = &i2c4_1;
+		i2c-7 = &i2c7_0;
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+		i2c_hid_slave: hid_slave {
+			/* TODO: how to configure slave mode */
+			i2c-port = <&i2c0_0>;
+			enum-names = "I2C_PORT_HID_SLAVE";
+		};
+		i2c_cypd0: cypd0 {
+			i2c-port = <&i2c1_0>;
+			enum-names = "I2C_PORT_PD_MCU0";
+		};
+		i2c_cypd1: cypd1 {
+			i2c-port = <&i2c2_0>;
+			enum-names = "I2C_PORT_PD_MCU1";
+		};
+		i2c_battery: battery{
+			i2c-port = <&i2c3_0>;
+			enum-names = "I2C_PORT_BATTERY",
+				"I2C_PORT_CHARGER";
+		};
+		i2c_touchpad: touchpad {
+			i2c-port = <&i2c4_1>;
+			enum-names = "I2C_PORT_TOUCHPAD";
+			dynamic-speed;
+		};
+		i2c_sensor: sensor {
+			i2c-port = <&i2c7_0>;
+			enum-names =  "I2C_PORT_SENSOR",
+				"I2C_PORT_THERMAL_AP",
+				"I2C_PORT_ALS";
+		};
+	};
+};
+
+&i2c0_0 {
+	status = "okay";
+	label = "I2C_PORT0";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>;
+	pinctrl-names = "default";
+
+	i2chid0: i2chid@50 {
+		compatible = "cros-ec,i2c-target-hid";
+		reg = <0x50>;
+		alert_gpios = <&gpio9 6 GPIO_OPEN_DRAIN>;
+		max_report_size = <32>;
+		hid_descriptor = "keyboard_hid_desc";
+		hid_report_descriptor = "keyboard_report_desc";
+	};
+
+	i2chid1: i2chid@51 {
+		compatible = "cros-ec,i2c-target-hid";
+		reg = <0x51>;
+		alert_gpios = <&gpio7 4 GPIO_OPEN_DRAIN>;
+		max_report_size = <32>;
+		hid_descriptor = "als_hid_desc";
+		hid_report_descriptor = "als_report_desc";
+	};
+
+};
+
+&i2c_ctrl0 {
+	status = "okay";
+};
+
+&i2c1_0 {
+	status = "okay";
+	label = "I2C_PORT1";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>;
+	pinctrl-names = "default";
+
+	/* TODO: Add the device on this bus */
+};
+
+&i2c_ctrl1 {
+	status = "okay";
+};
+
+&i2c2_0 {
+	status = "okay";
+	label = "I2C_PORT2";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c2_0_sda_scl_gp91_92>;
+	pinctrl-names = "default";
+
+	/* TODO: Add the device on this bus */
+};
+
+&i2c_ctrl2 {
+	status = "okay";
+};
+
+&i2c3_0 {
+	status = "okay";
+	label = "I2C_PORT3";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>;
+	pinctrl-names = "default";
+
+	/* TODO: Add the device on this bus */
+	charger: isl9241@9 {
+		compatible = "intersil,isl9241";
+		status = "okay";
+		reg = <0x9>;
+	};
+};
+
+&i2c_ctrl3 {
+	status = "okay";
+};
+
+&i2c4_1 {
+	status = "okay";
+	label = "I2C_PORT4";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	pinctrl-0 = <&i2c4_1_sda_scl_gpf2_f3>;
+	pinctrl-names = "default";
+
+	/* TODO: Add the device on this bus */
+};
+
+&i2c_ctrl4 {
+	status = "okay";
+};
+
+&i2c7_0 {
+	status = "okay";
+	label = "I2C_PORT7";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>;
+	pinctrl-names = "default";
+
+
+	/* Qth1 */
+	cpu_f75303: cpu_f75303@4d {
+		compatible = "cros-ec,temp-sensor-f75303";
+		temperature-type = "F75303_IDX_REMOTE1";
+		reg = <0x4d>;
+	};
+
+	/* Qth2 */
+	ddr_f75303: ddr_f75303@4d {
+		compatible = "cros-ec,temp-sensor-f75303";
+		temperature-type = "F75303_IDX_REMOTE2";
+		reg = <0x4d>;
+	};
+
+	/* Uth1 */
+	local_f75303: local_f75303@4d {
+		compatible = "cros-ec,temp-sensor-f75303";
+		temperature-type = "F75303_IDX_LOCAL";
+		reg = <0x4d>;
+	};
+
+	temp_cpu: cpu@4c {
+		compatible = "amd,sb-tsi";
+		reg = <0x4c>;
+	};
+
+	als_cm32183: als-cm32183@29 {
+		compatible = "nxp,cm32183";
+		reg = <0x29>;
+	};
+};
+
+&i2c_ctrl7 {
+	status = "okay";
+};
diff --git a/zephyr/program/framework/azalea/interrupts.dtsi b/zephyr/program/framework/azalea/interrupts.dtsi
new file mode 100644
index 0000000000..8e11f78115
--- /dev/null
+++ b/zephyr/program/framework/azalea/interrupts.dtsi
@@ -0,0 +1,61 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_ac_present: ac_present {
+			irq-pin = <&gpio_hw_acav_in>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "extpower_interrupt";
+		};
+		int_powerbtn: powerbtn {
+			irq-pin = <&gpio_on_off_btn_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "board_power_button_interrupt";
+		};
+		int_slp_s3: slp_s3 {
+			irq-pin = <&gpio_slp_s3_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_slp_s5: slp_s5 {
+			irq-pin = <&gpio_slp_s5_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_3valw_pg: 3valw_pg {
+			irq-pin = <&gpio_spok>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_vr_pg: vr_pg {
+			irq-pin = <&gpio_vr_pwrgd>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_pd_chip0_interrupt: pd_chip0_interrupt {
+			irq-pin = <&gpio_pd_chip0_interrupt>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "pd0_chip_interrupt";
+		};
+		int_pd_chip1_interrupt: pd_chip1_interrupt {
+			irq-pin = <&gpio_pd_chip1_interrupt>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "pd1_chip_interrupt";
+		};
+		int_lid_open: lid_open {
+			irq-pin = <&gpio_lid_sw_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "lid_interrupt";
+		};
+		int_chassis_open: chassis_open {
+			irq-pin = <&gpio_chassis_open_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "chassis_interrupt_handler";
+		};
+	};
+};
diff --git a/zephyr/program/framework/azalea/keyboard.dtsi b/zephyr/program/framework/azalea/keyboard.dtsi
new file mode 100644
index 0000000000..75cd45881e
--- /dev/null
+++ b/zephyr/program/framework/azalea/keyboard.dtsi
@@ -0,0 +1,18 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	kblight {
+		compatible = "cros-ec,kblight-pwm";
+		pwms = <&pwm1 0 PWM_HZ(324) PWM_POLARITY_NORMAL>;
+	};
+};
+
+&pwm1 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm1_gpc2>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/framework/azalea/led_pins.dtsi b/zephyr/program/framework/azalea/led_pins.dtsi
new file mode 100644
index 0000000000..018b8c6cc8
--- /dev/null
+++ b/zephyr/program/framework/azalea/led_pins.dtsi
@@ -0,0 +1,126 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	pwmleds {
+		compatible = "pwm-leds";
+
+		pwm_b: pwm_b {
+			pwms = <&pwm2 0 PWM_HZ(324) PWM_POLARITY_NORMAL>;
+		};
+
+		pwm_r: pwm_r {
+			pwms = <&pwm3 0 PWM_HZ(324) PWM_POLARITY_NORMAL>;
+		};
+
+		pwm_g: pwm_g {
+			pwms = <&pwm4 0 PWM_HZ(324) PWM_POLARITY_NORMAL>;
+		};
+
+		pwm_power_w: pwm_power_w {
+			pwms = <&pwm5 0 PWM_HZ(324) PWM_POLARITY_NORMAL>;
+		};
+	};
+
+	pwm-led-pins {
+		compatible = "cros-ec,pwm-led-pins";
+
+		battery_led: battery-led {
+			led-id = "EC_LED_ID_BATTERY_LED";
+			led-pwms = <&pwm_r &pwm_g &pwm_b>;
+
+
+			color_off: color-off {
+				led-color = "LED_OFF";
+				led-values = <0 0 0>;
+			};
+
+			color_red: color-red {
+				led-color = "LED_RED";
+				br-color = "EC_LED_COLOR_RED";
+				led-values = <8 0 0>;
+			};
+
+			color_green: color-green {
+				led-color = "LED_GREEN";
+				br-color = "EC_LED_COLOR_GREEN";
+				led-values = <0 16 0>;
+			};
+
+			color_blue: color-blue {
+				led-color = "LED_BLUE";
+				br-color = "EC_LED_COLOR_BLUE";
+				led-values = <0 0 8>;
+			};
+
+			color_yellow: color-yellow {
+				led-color = "LED_YELLOW";
+				br-color = "EC_LED_COLOR_YELLOW";
+				led-values = <4 5 0>;
+			};
+
+			color_white: color-white {
+				led-color = "LED_WHITE";
+				br-color = "EC_LED_COLOR_WHITE";
+				led-values = <4 10 5>;
+			};
+
+			color_amber: color-amber {
+				led-color = "LED_AMBER";
+				br-color = "EC_LED_COLOR_AMBER";
+				led-values = <9 1 0>;
+			};
+
+		};
+
+		power_led: power-led {
+			led-id = "EC_LED_ID_POWER_LED";
+			led-pwms = <&pwm_power_w>;
+
+			color_power_off: color-power-off {
+				led-color = "LED_OFF";
+				led-values = <0>;
+			};
+
+			color_power_white: color-power-white {
+				led-color = "LED_WHITE";
+				br-color = "EC_LED_COLOR_WHITE";
+				led-values = <55>;
+			};
+		};
+	};
+};
+
+/* Battery charging Blue LED */
+&pwm2 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm2_gpc4>;
+	pinctrl-names = "default";
+};
+
+/* Battery charging Red LED */
+&pwm3 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm3_gp80>;
+	pinctrl-names = "default";
+};
+
+/* Battery charging Green LED */
+&pwm4 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm4_gpb6>;
+	pinctrl-names = "default";
+};
+
+/* Finger Printer White LED */
+&pwm5 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm5_gpb7>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/framework/azalea/led_policy.dtsi b/zephyr/program/framework/azalea/led_policy.dtsi
new file mode 100644
index 0000000000..ece3a2f8b5
--- /dev/null
+++ b/zephyr/program/framework/azalea/led_policy.dtsi
@@ -0,0 +1,91 @@
+#include <dt-bindings/battery.h>
+
+/ {
+	led-colors {
+		compatible = "cros-ec,led-policy";
+
+		power-state-charge {
+			charge-state = "LED_PWRS_CHARGE";
+			/* Battery percent range (>= 0, < 96) */
+			batt-lvl = <BATTERY_LEVEL_EMPTY 95>;
+			color-0 {
+				led-color = <&color_amber>;
+			};
+		};
+
+		power-state-charge-lvl-2 {
+			charge-state = "LED_PWRS_CHARGE";
+			/* Battery percent range (>= 96%, <= 100%) */
+			batt-lvl = <96 100>;
+
+			color-0 {
+				led-color = <&color_white>;
+			};
+		};
+
+		power-state-discharge {
+			charge-state = "LED_PWRS_DISCHARGE";
+
+			color-0 {
+				led-color = <&color_off>;
+			};
+		};
+
+		power-state-near-full {
+			charge-state = "LED_PWRS_CHARGE_NEAR_FULL";
+			/* Battery percent range (>= 97, <= 100) */
+		
+			color-0 {
+				led-color = <&color_white>;
+			};
+		};
+
+		power-state-error_standalone {
+			charge-state = "LED_PWRS_ERROR";
+
+			color-0 {
+				led-color = <&color_white>;
+			};
+		};
+
+		power-state-idle {
+			charge-state = "LED_PWRS_IDLE";
+
+			color-0 {
+				led-color = <&color_white>;
+			};
+		};
+
+		power-state-forced-idle {
+			charge-state = "LED_PWRS_FORCED_IDLE";
+
+			color-0 {
+				led-color = <&color_white>;
+			};
+		};
+
+		power-state-s0 {
+			chipset-state = "POWER_S0";
+
+			color-0 {
+				led-color = <&color_power_white>;
+			};
+		};
+
+		power-state-s3 {
+			chipset-state = "POWER_S3";
+
+			color-0 {
+				led-color = <&color_power_off>;
+			};
+		};
+
+		power-state-s5 {
+			chipset-state = "POWER_S5";
+
+			color-0 {
+				led-color = <&color_power_off>;
+			};
+		};
+	};
+};
diff --git a/zephyr/program/framework/azalea/overlay.dtsi b/zephyr/program/framework/azalea/overlay.dtsi
new file mode 100644
index 0000000000..08520e1c9e
--- /dev/null
+++ b/zephyr/program/framework/azalea/overlay.dtsi
@@ -0,0 +1,182 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <freq.h>
+
+
+/ {
+	named-gpios {
+		/* Lotus-specific GPIO customizations */
+	};
+
+	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
+		local-f75303 {
+			temp_host_warn = <70>;
+			temp_host_high = <80>;
+			temp_host_halt = <120>;
+			temp_host_release_warn = <50>;
+			temp_host_release_high = <55>;
+			temp_host_release_halt = <115>;
+			temp_fan_off = <40>;
+			temp_fan_max = <70>;
+			power-good-pin = <&gpio_slp_s3_l>;
+			sensor = <&local_f75303>;
+		};
+		cpu-f75303 {
+			temp_host_warn = <70>;
+			temp_host_high = <80>;
+			temp_host_halt = <120>;
+			temp_host_release_warn = <53>;
+			temp_host_release_high = <55>;
+			temp_host_release_halt = <115>;
+			temp_fan_off = <46>;
+			temp_fan_max = <54>;
+			power-good-pin = <&gpio_slp_s3_l>;
+			sensor = <&cpu_f75303>;
+		};
+		ddr-f75303 {
+			temp_host_warn = <70>;
+			temp_host_high = <80>;
+			temp_host_halt = <120>;
+			temp_host_release_warn = <50>;
+			temp_host_release_high = <55>;
+			temp_host_release_halt = <115>;
+			temp_fan_off = <128>;
+			temp_fan_max = <128>;
+			power-good-pin = <&gpio_slp_s3_l>;
+			sensor = <&ddr_f75303>;
+		};
+		amd-apu {
+			temp_host_warn = <108>;
+			temp_host_high = <115>;
+			temp_host_halt = <127>;
+			temp_host_release_warn = <103>;
+			temp_host_release_high = <110>;
+			temp_host_release_halt = <122>;
+			temp_fan_off = <103>;
+			temp_fan_max = <105>;
+			power-good-pin = <&gpio_slp_s3_l>;
+			sensor = <&temp_cpu>;
+		};
+	};
+
+	typec-port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		/*
+		 * If the CHARGER_SINGLE_CHIP config is enabled, only
+		 * one charger chip must be defined.
+		 *
+		 * In the Zephyer OS, the CONFIG_USB_PD_PORT_MAX_COUNT will check
+		 * the device tree compatible "named-usbc-port"
+		 */
+		usbc_port0: port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+			chg = <&charger>;
+		};
+		usbc_port1: port1@1 {
+			compatible = "named-usbc-port";
+			reg = <1>;
+		};
+		usbc_port2: port2@2 {
+			compatible = "named-usbc-port";
+			reg = <2>;
+		};
+		usbc_port3: port3@3 {
+			compatible = "named-usbc-port";
+			reg = <3>;
+		};
+	};
+
+	named-bbram-regions {
+		compatible = "named-bbram-regions";
+
+		charge_limit_max {
+			offset = <0x44>;
+			size = <0x01>;
+		};
+		fp_led_level {
+			offset = <0x45>;
+			size = <0x01>;
+		};
+		kb_status {
+			offset = <0x46>;
+			size = <0x01>;
+		};
+		bios_function {
+			offset = <0x47>;
+			size = <0x01>;
+		};
+		chassis_was_open {
+			offset = <0x48>;
+			size = <0x01>;
+		};
+		chassis_magic {
+			offset = <0x49>;
+			size = <0x01>;
+		};
+		chassis_total {
+			offset = <0x4a>;
+			size = <0x01>;
+		};
+		chassis_vtr_open {
+			offset = <0x4b>;
+			size = <0x01>;
+		};
+	};
+};
+
+&cros_kb_raw {
+	status = "okay";
+	pinctrl-0 = <
+		&ksi0_gp31
+		&ksi1_gp30
+		&ksi2_gp27
+		&ksi3_gp26
+		&ksi4_gp25
+		&ksi5_gp24
+		&ksi6_gp23
+		&ksi7_gp22
+		&kso00_gp21
+		&kso01_gp20
+		&kso02_gp17
+		&kso03_gp16
+		&kso04_gp15
+		&kso05_gp14
+		&kso06_gp13
+		&kso07_gp12
+		&kso08_gp11
+		&kso09_gp10
+		&kso10_gp07
+		&kso11_gp06
+		&kso12_gp05
+		&kso13_gp04
+		&kso14_gp82
+		&kso15_gp83
+	>;
+	pinctrl-names = "default";
+};
+
+&binman {
+	ec-rw {
+		/*
+		 * Azalea uses the last 0x1000 bytes of flash for non-volatile settings storage.
+		 * Shrink the RW region by that much so that there is no conflict between RW_FWID
+		 * or RW text and non-volatile settings.
+		 */
+		size = <0x3f000>;
+		rw-fw {
+			rw-fwid {
+				offset = <(0x3f000 - 32)>;
+			};
+		};
+	};
+	/* The remaining 0x1000 bytes will be used for non-volatile settings storage. */
+	pad-after = <0x1000>;
+	pad-byte = <0xFF>;
+};
diff --git a/zephyr/program/framework/azalea/project.conf b/zephyr/program/framework/azalea/project.conf
new file mode 100644
index 0000000000..d1d05d8774
--- /dev/null
+++ b/zephyr/program/framework/azalea/project.conf
@@ -0,0 +1,30 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_BOARD_AZALEA=y
+
+# Customized
+
+# Fan
+CONFIG_PLATFORM_EC_NUM_FANS=1
+
+# Charger
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=20
+CONFIG_PLATFORM_EC_CHARGER_DEFAULT_CURRENT_LIMIT=500
+CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON=15000
+CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_NOT_PRESENT=y
+CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y
+#CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_BY_BOARD=y TODO add INA vbus measurements
+# Thermal
+CONFIG_PLATFORM_EC_TEMP_SENSOR_F75303=y
+
+# Keyboard
+CONFIG_PLATFORM_EC_PWM_KBLIGHT=y
+CONFIG_PLATFORM_EC_KEYBOARD_VIVALDI=n
+CONFIG_PLATFORM_EC_KEYBOARD_CUSTOMIZATION=y
+CONFIG_PLATFORM_KEYBOARD_SCANCODE_CALLBACK=y
+
+# Thrid party change
+CONFIG_THIRD_PARTY_CUSTOMIZED_DESIGN=y
diff --git a/zephyr/program/framework/azalea/project.overlay b/zephyr/program/framework/azalea/project.overlay
new file mode 100644
index 0000000000..4a820cc5ec
--- /dev/null
+++ b/zephyr/program/framework/azalea/project.overlay
@@ -0,0 +1,15 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc.dtsi"
+#include "battery.dtsi"
+#include "fan.dtsi"
+#include "gpio.dtsi"
+#include "i2c.dtsi"
+#include "interrupts.dtsi"
+#include "led_pins.dtsi"
+#include "led_policy.dtsi"
+#include "overlay.dtsi"
+#include "keyboard.dtsi"
diff --git a/zephyr/program/framework/azalea/src/battery.c b/zephyr/program/framework/azalea/src/battery.c
new file mode 100644
index 0000000000..5351d3426b
--- /dev/null
+++ b/zephyr/program/framework/azalea/src/battery.c
@@ -0,0 +1,268 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include <zephyr/drivers/gpio.h>
+
+#include "adc.h"
+#include "battery.h"
+#include "battery_smart.h"
+#include "battery_fuel_gauge.h"
+#include "board_adc.h"
+#include "board_host_command.h"
+#include "charger.h"
+#include "charge_state.h"
+#include "console.h"
+#include "customized_shared_memory.h"
+#include "hooks.h"
+#include "system.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+
+#define CACHE_INVALIDATION_TIME_US (3 * SECOND)
+
+static enum battery_present batt_pres_prev = BP_NOT_SURE;
+static int old_btp;
+
+enum battery_present battery_is_present(void)
+{
+	enum battery_present batt_pres;
+	int mv;
+
+	mv = adc_read_channel(ADC_VCIN1_BATT_TEMP);
+	batt_pres = (mv < 2200 ? BP_YES : BP_NO);
+
+	if (mv == ADC_READ_ERROR)
+		return BP_NO;
+
+	/*
+	 * If the battery is present now and was present last time we checked,
+	 * return early.
+	 */
+	if (batt_pres == BP_YES && batt_pres_prev == batt_pres)
+		return batt_pres;
+
+	batt_pres_prev = batt_pres;
+
+	return batt_pres;
+}
+
+uint32_t get_system_percentage(void)
+{
+	static uint32_t pre_os_percentage;
+	uint32_t memmap_cap = *(uint32_t *)host_get_memmap(EC_MEMMAP_BATT_CAP);
+	uint32_t memmap_lfcc = *(uint32_t *)host_get_memmap(EC_MEMMAP_BATT_LFCC);
+	uint32_t os_percentage = 1000 * memmap_cap / (memmap_lfcc + 1);
+
+	/* ensure this value is valid */
+	if (os_percentage <= 1000 && os_percentage >= 0) {
+		pre_os_percentage = os_percentage;
+		return os_percentage;
+	} else
+		return pre_os_percentage;
+}
+
+enum battery_present board_batt_is_present(void)
+{
+	/*
+	 * Due to adc_read_channel() will clear the task event,
+	 * we should get the battery status without read adc channel again.
+	 */
+	return batt_pres_prev;
+}
+
+void battery_customize(struct charge_state_data *curr_batt)
+{
+	char text[32];
+	char *str = "LION";
+	int value;
+	int new_btp;
+	int rv;
+	static int batt_state;
+	static int read_manuf_date;
+	int day = 0;
+	int month = 0;
+	int year = 0;
+	uint32_t batt_os_percentage = get_system_percentage();
+
+	/* manufacture date is static data */
+	if (!read_manuf_date && battery_is_present() == BP_YES) {
+		rv = battery_manufacture_date(&year, &month, &day);
+		if (rv == EC_SUCCESS) {
+			ccprintf("Batt manufacturer date: %d.%d.%d\n", year, month, day);
+			*host_get_memmap(EC_CUSTOMIZED_MEMMAP_BATT_MANUF_DAY) = day;
+			*host_get_memmap(EC_CUSTOMIZED_MEMMAP_BATT_MANUF_MONTH) = month;
+			*host_get_memmap(EC_CUSTOMIZED_MEMMAP_BATT_MANUF_YEAR) =
+				year & 0xff;
+			*host_get_memmap(EC_CUSTOMIZED_MEMMAP_BATT_MANUF_YEAR + 1) =
+				year >> 8;
+			read_manuf_date = 1;
+		}
+	} else if (!battery_is_present()) {
+		/**
+		 * if battery isn't present, we need to read manufacture
+		 * date after battery is connect
+		 */
+		read_manuf_date = 0;
+	}
+
+	*host_get_memmap(EC_CUSTOMIZED_MEMMAP_BATT_AVER_TEMP) =
+					(curr_batt->batt.temperature - 2731) / 10;
+	*host_get_memmap(EC_CUSTOMIZED_MEMMAP_BATT_PERCENTAGE) =
+					batt_os_percentage / 10;
+
+	if (curr_batt->batt.status & STATUS_FULLY_CHARGED)
+		*host_get_memmap(EC_CUSTOMIZED_MEMMAP_BATT_STATUS) |= EC_BATT_FLAG_FULL;
+	else
+		*host_get_memmap(EC_CUSTOMIZED_MEMMAP_BATT_STATUS) &= ~EC_BATT_FLAG_FULL;
+
+	battery_device_chemistry(text, sizeof(text));
+	if (!strncmp(text, str, 4))
+		*host_get_memmap(EC_CUSTOMIZED_MEMMAP_BATT_STATUS) |= EC_BATT_TYPE;
+	else
+		*host_get_memmap(EC_CUSTOMIZED_MEMMAP_BATT_STATUS) &= ~EC_BATT_TYPE;
+
+	battery_get_mode(&value);
+	/* in framework use smart.c it will force in mAh mode*/
+	if (value & MODE_CAPACITY)
+		*host_get_memmap(EC_CUSTOMIZED_MEMMAP_BATT_STATUS) &= ~EC_BATT_MODE;
+	else
+		*host_get_memmap(EC_CUSTOMIZED_MEMMAP_BATT_STATUS) |= EC_BATT_MODE;
+
+	/* BTP: Notify AP update battery */
+	new_btp = *host_get_memmap(EC_CUSTOMIZED_MEMMAP_BATT_TRIP_POINT) +
+			(*host_get_memmap(EC_CUSTOMIZED_MEMMAP_BATT_TRIP_POINT+1) << 8);
+
+	if (!(curr_batt->batt.flags & BATT_FLAG_BAD_REMAINING_CAPACITY)) {
+
+		if (old_btp == 0)
+			old_btp = curr_batt->batt.remaining_capacity;
+
+		if (new_btp == 0 && batt_os_percentage < 995)
+			host_set_single_event(EC_HOST_EVENT_BATT_BTP);
+
+		if (new_btp > old_btp && !battery_is_cut_off()) {
+			if (curr_batt->batt.remaining_capacity > new_btp) {
+				old_btp = new_btp;
+				host_set_single_event(EC_HOST_EVENT_BATT_BTP);
+			}
+		} else if (new_btp < old_btp && !battery_is_cut_off()) {
+			if (curr_batt->batt.remaining_capacity < new_btp) {
+				old_btp = new_btp;
+				host_set_single_event(EC_HOST_EVENT_BATT_BTP);
+			}
+		}
+	}
+
+	/*
+	 * When the battery present have change notify AP
+	 */
+	if (batt_state != curr_batt->batt.is_present) {
+		host_set_single_event(EC_HOST_EVENT_BATTERY);
+		batt_state = curr_batt->batt.is_present;
+	}
+}
+
+static void fix_single_param(int flag, int *cached, int *curr)
+{
+	if (flag)
+		*curr = *cached;
+	else
+		*cached = *curr;
+}
+
+/*
+ * If any value in batt_params is bad, replace it with a cached
+ * good value, to make sure we never send random numbers to ap
+ * side.
+ */
+__override void board_battery_compensate_params(struct batt_params *batt)
+{
+	static struct batt_params batt_cache = { 0 };
+	static timestamp_t deadline;
+
+	/*
+	 * If battery keeps failing for 3 seconds, stop hiding the error and
+	 * report back to host.
+	 */
+
+	if (batt->flags & BATT_FLAG_RESPONSIVE) {
+		if (batt->flags & BATT_FLAG_BAD_ANY) {
+			if (timestamp_expired(deadline, NULL))
+				return;
+		} else
+			deadline.val = get_time().val + CACHE_INVALIDATION_TIME_US;
+	} else if (!(batt->flags & BATT_FLAG_RESPONSIVE)) {
+		/**
+		 * There are 4 situations for battery is not repsonsed
+		 * 1. Darin battery (first time)
+		 * 2. Dead battery (first time)
+		 * 3. No battery (is preset)
+		 * 4. Others
+		 */
+		/* we don't need to cache the value when battery is not present */
+		if (!batt->is_present) {
+			batt_cache.flags &= ~BATT_FLAG_RESPONSIVE;
+			return;
+		}
+
+		/* we don't need to cache the value when we read the battery first time */
+		if (!(batt_cache.flags & BATT_FLAG_RESPONSIVE))
+			return;
+
+		/**
+		 * If battery keeps no responsing for 3 seconds, stop hiding the error and
+		 * back to host.
+		 */
+		if (timestamp_expired(deadline, NULL)) {
+			batt_cache.flags &= ~BATT_FLAG_RESPONSIVE;
+			return;
+		}
+	}
+
+	/* return cached values for at most CACHE_INVALIDATION_TIME_US */
+	fix_single_param(batt->flags & BATT_FLAG_BAD_STATE_OF_CHARGE,
+			&batt_cache.state_of_charge,
+			&batt->state_of_charge);
+	fix_single_param(batt->flags & BATT_FLAG_BAD_VOLTAGE,
+			&batt_cache.voltage,
+			&batt->voltage);
+	fix_single_param(batt->flags & BATT_FLAG_BAD_CURRENT,
+			&batt_cache.current,
+			&batt->current);
+	fix_single_param(batt->flags & BATT_FLAG_BAD_DESIRED_VOLTAGE,
+			&batt_cache.desired_voltage,
+			&batt->desired_voltage);
+	fix_single_param(batt->flags & BATT_FLAG_BAD_DESIRED_CURRENT,
+			&batt_cache.desired_current,
+			&batt->desired_current);
+	fix_single_param(batt->flags & BATT_FLAG_BAD_REMAINING_CAPACITY,
+			&batt_cache.remaining_capacity,
+			&batt->remaining_capacity);
+	fix_single_param(batt->flags & BATT_FLAG_BAD_FULL_CAPACITY,
+			&batt_cache.full_capacity,
+			&batt->full_capacity);
+	fix_single_param(batt->flags & BATT_FLAG_BAD_STATUS,
+			&batt_cache.status,
+			&batt->status);
+	fix_single_param(batt->flags & BATT_FLAG_BAD_TEMPERATURE,
+			&batt_cache.temperature,
+			&batt->temperature);
+	/*
+	 * If battery_compensate_params() didn't calculate display_charge
+	 * for us, also update it with last good value.
+	 */
+	fix_single_param(batt->display_charge == 0,
+			&batt_cache.display_charge,
+			&batt->display_charge);
+
+	/* remove bad flags after applying cached values */
+	batt->flags &= ~BATT_FLAG_BAD_ANY;
+	batt->flags |= BATT_FLAG_RESPONSIVE;
+	batt_cache.flags |= BATT_FLAG_RESPONSIVE;
+
+	/* override the display charge value for Windows system */
+	batt->display_charge = get_system_percentage();
+}
diff --git a/zephyr/program/framework/azalea/src/charger.c b/zephyr/program/framework/azalea/src/charger.c
new file mode 100644
index 0000000000..935eb1e78d
--- /dev/null
+++ b/zephyr/program/framework/azalea/src/charger.c
@@ -0,0 +1,319 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include <zephyr/drivers/gpio.h>
+
+#include "battery.h"
+#include "battery_smart.h"
+#include "battery_fuel_gauge.h"
+#include "board_charger.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "console.h"
+#include "driver/charger/isl9241.h"
+#include "extpower.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
+
+#ifdef CONFIG_PLATFORM_EC_CHARGER_INIT_CUSTOM
+static void charger_chips_init(void);
+static void charger_chips_init_retry(void)
+{
+	charger_chips_init();
+}
+DECLARE_DEFERRED(charger_chips_init_retry);
+
+static void charger_chips_init(void)
+{
+	/* Battery present need ADC function ready, so change the initail priority
+	 * after ADC
+	 */
+
+	const int no_battery_current_limit_override_ma = 3000;
+	const struct battery_info *bi = battery_get_info();
+	uint16_t val = 0x0000; /*default ac setting */
+	uint32_t data = 0;
+	int value;
+
+	/*
+	 * In our case the EC can boot before the charger has power so
+	 * check if the charger is responsive before we try to init it
+	 */
+
+	if (i2c_read16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+		ISL9241_REG_ACOK_REFERENCE, &data) != EC_SUCCESS) {
+		CPRINTS("Retry Charger init");
+		hook_call_deferred(&charger_chips_init_retry_data, 100*MSEC);
+		return;
+	}
+
+	if (i2c_write16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+		ISL9241_REG_CONTROL4, ISL9241_CONTROL4_WOCP_FUNCTION |
+		ISL9241_CONTROL4_VSYS_SHORT_CHECK |
+		ISL9241_CONTROL4_ACOK_BATGONE_DEBOUNCE_25US))
+		goto init_fail;
+
+	value = battery_is_charge_fet_disabled();
+
+	/*
+	 * Set control3 register to
+	 * [14]: ACLIM Reload (Do not reload)
+	 */
+	if (value == -1) {
+		if (i2c_write16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+			ISL9241_REG_CONTROL3,
+			(ISL9241_CONTROL3_ACLIM_RELOAD | ISL9241_CONTROL3_ENABLE_ADC |
+			ISL9241_CONTROL3_INPUT_CURRENT_LIMIT)))
+			goto init_fail;
+	} else {
+		if (i2c_write16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+			ISL9241_REG_CONTROL3,
+			(ISL9241_CONTROL3_ACLIM_RELOAD | ISL9241_CONTROL3_ENABLE_ADC)))
+			goto init_fail;
+	}
+
+	/* reverse the flag if no error */
+	if (value != -1)
+		value = !value;
+	/*
+	 * When there is no battery, override charger current limit to
+	 * prevent brownout during boot.
+	 */
+	if (value == -1) {
+		ccprints("No Battery Found - Override Current Limit to %dmA",
+			 no_battery_current_limit_override_ma);
+		charger_set_input_current_limit(
+			CHARGER_SOLO, no_battery_current_limit_override_ma);
+	}
+
+	/* According to Power team suggest, Set ACOK reference to 4.544V */
+	if (i2c_write16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+		ISL9241_REG_ACOK_REFERENCE, ISL9241_MV_TO_ACOK_REFERENCE(4207)))
+		goto init_fail;
+
+
+	/*
+	 * Set the MaxSystemVoltage to battery maximum,
+	 * 0x00=disables switching charger states
+	 */
+	if (value == -1) {
+		if (i2c_write16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+			ISL9241_REG_MAX_SYSTEM_VOLTAGE, 15400))
+			goto init_fail;
+	} else {
+		if (i2c_write16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+			ISL9241_REG_MAX_SYSTEM_VOLTAGE, bi->voltage_max))
+			goto init_fail;
+	}
+
+	/*
+	 * Set the MinSystemVoltage to battery minimum,
+	 * 0x00=disables all battery charging
+	 */
+	if (i2c_write16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+		ISL9241_REG_MIN_SYSTEM_VOLTAGE, bi->voltage_min))
+		goto init_fail;
+
+	if (i2c_write16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+		ISL9241_REG_CONTROL2,
+		ISL9241_CONTROL2_TRICKLE_CHG_CURR(bi->precharge_current) |
+		ISL9241_CONTROL2_PROCHOT_DEBOUNCE_1000))
+		goto init_fail;
+
+	if (i2c_write16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+		ISL9241_REG_CONTROL0, 0x0000))
+		goto init_fail;
+
+	val = ISL9241_CONTROL1_PROCHOT_REF_6800;
+	val |= ((ISL9241_CONTROL1_SWITCHING_FREQ_724KHZ << 7) &
+			ISL9241_CONTROL1_SWITCHING_FREQ_MASK);
+
+	/* Make sure battery FET is enabled on EC on */
+	val &= ~ISL9241_CONTROL1_BGATE_OFF;
+
+	if (i2c_write16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+		ISL9241_REG_CONTROL1, val))
+		goto init_fail;
+
+	/* TODO: should we need to talk to PD chip after initial complete ? */
+	CPRINTS("ISL9241 customized initial complete!  3F:%d", value);
+	return;
+
+init_fail:
+	CPRINTF("ISL9241 customer init failed!");
+}
+DECLARE_HOOK(HOOK_INIT, charger_chips_init, HOOK_PRIO_POST_I2C);
+#endif
+
+void charger_update(void)
+{
+	static int pre_ac_state;
+	static int pre_dc_state;
+	int val = 0x0000;
+
+	if (pre_ac_state != extpower_is_present() ||
+		pre_dc_state != battery_is_present()) {
+		CPRINTS("update charger!!");
+
+		if (i2c_read16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+			ISL9241_REG_CONTROL1, &val)) {
+			CPRINTS("read charger control1 fail");
+		}
+
+		val |= ISL9241_CONTROL1_PROCHOT_REF_6800;
+		val |= ((ISL9241_CONTROL1_SWITCHING_FREQ_724KHZ << 7) &
+			ISL9241_CONTROL1_SWITCHING_FREQ_MASK);
+
+		if (i2c_write16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+			ISL9241_REG_CONTROL1, val)) {
+			CPRINTS("Update charger control1 fail");
+		}
+
+		/* TODO: check the battery power to update the DC prochot value */
+		if (i2c_write16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+			ISL9241_REG_DC_PROCHOT, 0x1E00))
+			CPRINTS("Update DC prochot fail");
+
+		pre_ac_state = extpower_is_present();
+		pre_dc_state = battery_is_present();
+	}
+}
+DECLARE_HOOK(HOOK_AC_CHANGE, charger_update, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, charger_update, HOOK_PRIO_DEFAULT);
+
+void board_set_charge_limit(int port, int supplier, int charge_ma,
+			    int max_ma, int charge_mv)
+{
+	int prochot_ma;
+
+	if (charge_ma < CONFIG_PLATFORM_EC_CHARGER_DEFAULT_CURRENT_LIMIT) {
+		charge_ma = CONFIG_PLATFORM_EC_CHARGER_DEFAULT_CURRENT_LIMIT;
+	}
+	/*
+	 * ac prochot should bigger than input current
+	 * And needs to be at least 128mA bigger than the adapter current
+	 */
+	prochot_ma = (DIV_ROUND_UP(charge_ma, 128) * 128);
+	charge_ma = charge_ma * 90 / 100;
+
+	if ((prochot_ma - charge_ma) < 128) {
+		charge_ma = prochot_ma - 128;
+	}
+
+	charge_set_input_current_limit(charge_ma, charge_mv);
+	/* sync-up ac prochot with current change */
+	isl9241_set_ac_prochot(0, prochot_ma);
+}
+
+void charge_gate_onoff(uint8_t enable)
+{
+	int control0 = 0x0000;
+	int control1 = 0x0000;
+
+	if (i2c_read16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+		ISL9241_REG_CONTROL0, &control0)) {
+		CPRINTS("read gate control1 fail");
+	}
+
+	if (i2c_read16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+		ISL9241_REG_CONTROL1, &control1)) {
+		CPRINTS("read gate control1 fail");
+	}
+
+	if (enable) {
+		control0 &= ~ISL9241_CONTROL0_NGATE_OFF;
+		control1 &= ~ISL9241_CONTROL1_BGATE_OFF;
+		CPRINTS("B&N Gate off");
+	} else {
+		control0 |= ISL9241_CONTROL0_NGATE_OFF;
+		control1 |= ISL9241_CONTROL1_BGATE_OFF;
+		CPRINTS("B&N Gate on");
+	}
+
+	if (i2c_write16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+		ISL9241_REG_CONTROL0, control0)) {
+		CPRINTS("Update gate control0 fail");
+	}
+
+	if (i2c_write16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+		ISL9241_REG_CONTROL1, control1)) {
+		CPRINTS("Update gate control1 fail");
+	}
+}
+
+void charger_psys_enable(uint8_t enable)
+{
+	int control1 = 0x0000;
+	int control4 = 0x0000;
+	int data = 0x0000;
+
+	if (i2c_read16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+		ISL9241_REG_CONTROL1, &control1)) {
+		CPRINTS("read psys control1 fail");
+	}
+
+	if (i2c_read16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+		ISL9241_REG_CONTROL4, &control4)) {
+		CPRINTS("read psys control1 fail");
+	}
+
+	if (enable) {
+		control1 &= ~ISL9241_CONTROL1_IMON;
+		control1 |= ISL9241_CONTROL1_PSYS;
+		control4 &= ~ISL9241_CONTROL4_GP_COMPARATOR;
+		data = 0x0B00;		/* Set ACOK reference to 4.544V */
+		CPRINTS("Power saving disable");
+	} else {
+		control1 |= ISL9241_CONTROL1_IMON;
+		control1 &= ~ISL9241_CONTROL1_PSYS;
+		control4 |= ISL9241_CONTROL4_GP_COMPARATOR;
+		data = 0x0000;		/* Set ACOK reference to 0V */
+		CPRINTS("Power saving enable");
+	}
+
+
+	if (i2c_write16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+		ISL9241_REG_ACOK_REFERENCE, data)) {
+		CPRINTS("Update ACOK reference fail");
+	}
+
+	if (i2c_write16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+		ISL9241_REG_CONTROL1, control1)) {
+		CPRINTS("Update psys control1 fail");
+	}
+
+	if (i2c_write16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+		ISL9241_REG_CONTROL4, control4)) {
+		CPRINTS("Update psys control4 fail");
+	}
+}
+
+/* Called on AP S5 -> S3 transition */
+static void board_charger_lpm_disable(void)
+{
+	charger_psys_enable(1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_charger_lpm_disable, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_charger_lpm_disable, HOOK_PRIO_DEFAULT);
+
+static void board_charger_lpm_enable(void)
+{
+	charger_psys_enable(0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_charger_lpm_enable, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_charger_lpm_enable, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_INIT, board_charger_lpm_enable, HOOK_PRIO_DEFAULT);
+
+__override void board_hibernate(void)
+{
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_0p75_1p8valw_pwren), 0);
+	/* Turn off BGATE and NGATE for power saving */
+	charger_psys_enable(0);
+	charge_gate_onoff(0);
+}
diff --git a/zephyr/program/framework/azalea/src/cpu_power.c b/zephyr/program/framework/azalea/src/cpu_power.c
new file mode 100644
index 0000000000..0ad712f82c
--- /dev/null
+++ b/zephyr/program/framework/azalea/src/cpu_power.c
@@ -0,0 +1,341 @@
+
+
+
+#include "charge_state.h"
+#include "charger.h"
+#include "charge_manager.h"
+#include "chipset.h"
+#include "common_cpu_power.h"
+#include "customized_shared_memory.h"
+#include "console.h"
+#include "driver/sb_rmi.h"
+#include "extpower.h"
+#include "hooks.h"
+#include "math_util.h"
+#include "throttle_ap.h"
+#include "util.h"
+
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+
+static int battery_mwatt_type;
+static int battery_current_limit_mA;
+static int powerlimit_restore;
+static int dc_safety_power_limit_level;
+
+static void update_os_power_slider(int mode, int active_mpower)
+{
+	switch (mode) {
+	case EC_DC_BEST_PERFORMANCE:
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPL] = 30000;
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPPT] = 35000;
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_FPPT] = battery_mwatt_type - 15000;
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_P3T] = 80000;
+		CPRINTS("DC BEST PERFORMANCE");
+		break;
+	case EC_DC_BALANCED:
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPL] = 28000;
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPPT] = 33000;
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_FPPT] = battery_mwatt_type - 20000;
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_P3T] = 80000;
+		CPRINTS("DC BALANCED");
+		break;
+	case EC_DC_BEST_EFFICIENCY:
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPL] = 15000;
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPPT] = 25000;
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_FPPT] = 30000;
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_P3T] = 80000;
+		CPRINTS("DC BEST EFFICIENCY");
+		break;
+	case EC_DC_BATTERY_SAVER:
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPL] = 15000;
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPPT] = 15000;
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_FPPT] = 30000;
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_P3T] = battery_mwatt_type;
+		CPRINTS("DC BATTERY SAVER");
+		break;
+	case EC_AC_BEST_PERFORMANCE:
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPL] = 30000;
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPPT] = 35000;
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_FPPT] = 53000;
+		/* AC p3t will limited by adapter_power_limit */
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_P3T] = 80000;
+		CPRINTS("AC BEST PERFORMANCE");
+		break;
+	case EC_AC_BALANCED:
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPL] = 28000;
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPPT] = 33000;
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_FPPT] = 51000;
+		/* AC p3t will limited by adapter_power_limit */
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_P3T] = 80000;
+		CPRINTS("AC BALANCED");
+		break;
+	case EC_AC_BEST_EFFICIENCY:
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPL] = 15000;
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPPT] = 25000;
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_FPPT] = 30000;
+		/* AC p3t will limited by adapter_power_limit */
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_P3T] = 80000;
+		CPRINTS("AC BEST EFFICIENCY");
+		break;
+	default:
+		/* no mode, run power table */
+		break;
+	}
+}
+
+static void update_adapter_power_limit(int battery_percent, int active_mpower, bool with_dc)
+{
+	if (with_dc && (battery_percent < 3) && active_mpower > 0) {
+		power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 15000;
+		power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = 15000;
+		power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = 30000;
+		power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] = active_mpower * 95 / 100;
+		/* CPB enable */
+		*host_get_memmap(EC_CUSTOMIZED_MEMMAP_POWER_LIMIT_EVENT) &= ~CPB_DISABLE;
+		CPRINTS("DRAIN BATTERY");
+		return;
+	}
+
+	if ((!with_dc) && (active_mpower >= 100000)) {
+		/* AC (Without Battery) (ADP >= 100W) */
+		power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 30000;
+		power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = 35000;
+		power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = 53000;
+		power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] = 80000;
+		/* CPB enable */
+		*host_get_memmap(EC_CUSTOMIZED_MEMMAP_POWER_LIMIT_EVENT) &= ~CPB_DISABLE;
+	} else if ((!with_dc) && (active_mpower >= 60000)) {
+		/* AC (Without Battery) (60W <= ADP < 100W) */
+		power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 30000;
+		power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = 33000;
+		power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = 35000;
+		power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] = active_mpower * 95 / 100;
+		/* CPB disable */
+		*host_get_memmap(EC_CUSTOMIZED_MEMMAP_POWER_LIMIT_EVENT) &= ~CPB_DISABLE;
+	} else if ((battery_percent < 30) && (active_mpower >= 55000)) {
+		/* AC (With Battery) (Battery Capacity < 30%, ADP >= 55W) */
+		power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 30000;
+		power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = (active_mpower * 85 / 100) - 20000;
+		power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = (active_mpower * 85 / 100) - 15000;
+		power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] =
+			MIN(176000, (active_mpower * 90 / 100) + 89000);
+		/* CPB enable */
+		*host_get_memmap(EC_CUSTOMIZED_MEMMAP_POWER_LIMIT_EVENT) &= ~CPB_DISABLE;
+	} else if ((battery_percent >= 30) && (active_mpower >= 45000)) {
+		/* AC (With Battery) (Battery Capacity >= 30%, ADP >= 45W) */
+		power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 30000;
+		power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = 35000;
+		power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = 53000;
+		power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] =
+			MIN(176000, (active_mpower * 90 / 100) + 89000);
+		/* CPB enable */
+		*host_get_memmap(EC_CUSTOMIZED_MEMMAP_POWER_LIMIT_EVENT) &= ~CPB_DISABLE;
+	} else {
+		/* otherwise, take as DC only case */
+		power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 30000;
+		power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = 35000;
+		power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = battery_mwatt_type - 15000;
+		/* DC mode p3t should follow os_power_slider */
+		power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] = 89000;
+		/* CPB enable */
+		*host_get_memmap(EC_CUSTOMIZED_MEMMAP_POWER_LIMIT_EVENT) &= ~CPB_DISABLE;
+	}
+}
+
+static void update_dc_safety_power_limit(void)
+{
+	int new_mwatt;
+	int delta;
+	const struct batt_params *batt = charger_current_battery_params();
+	int battery_current = batt->current;
+	int battery_voltage = battery_dynamic[BATT_IDX_MAIN].actual_voltage;
+
+	if (!powerlimit_restore) {
+		/* restore to slider mode */
+		power_limit[FUNCTION_SAFETY].mwatt[TYPE_SPL]
+			= power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPL];
+		power_limit[FUNCTION_SAFETY].mwatt[TYPE_SPPT]
+			= power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPPT];
+		power_limit[FUNCTION_SAFETY].mwatt[TYPE_FPPT]
+			= power_limit[FUNCTION_SLIDER].mwatt[TYPE_FPPT];
+		power_limit[FUNCTION_SAFETY].mwatt[TYPE_P3T]
+			= power_limit[FUNCTION_SLIDER].mwatt[TYPE_P3T];
+		powerlimit_restore = 1;
+	} else {
+		new_mwatt = power_limit[FUNCTION_SAFETY].mwatt[TYPE_SPL];
+		/* start tuning PL by format */
+		/* discharge, value compare based on negative*/
+		if (battery_current < battery_current_limit_mA) {
+			/*
+			 * reduce apu power limit by
+			 * (1.2*((battery current - 3.57)* battery voltage)
+			 * (mA * mV = mW / 1000)
+			 */
+			delta = (ABS(battery_current - battery_current_limit_mA)
+				* battery_voltage) * 12 / 10 / 1000;
+			new_mwatt = new_mwatt - delta;
+			power_limit[FUNCTION_SAFETY].mwatt[TYPE_SPL]
+				= MAX(new_mwatt, 15000);
+			power_limit[FUNCTION_SAFETY].mwatt[TYPE_SPPT]
+				= power_limit[FUNCTION_SAFETY].mwatt[TYPE_SPL];
+			power_limit[FUNCTION_SAFETY].mwatt[TYPE_FPPT]
+				= power_limit[FUNCTION_SAFETY].mwatt[TYPE_SPL];
+			CPRINTF("batt ocp, delta: %d, new PL: %d\n",
+				delta, power_limit[FUNCTION_SAFETY].mwatt[TYPE_SPL]);
+
+			if (new_mwatt < 15000) {
+				throttle_ap(THROTTLE_ON, THROTTLE_HARD,
+					THROTTLE_SRC_BAT_DISCHG_CURRENT);
+				dc_safety_power_limit_level = 1;
+			}
+		} else if (battery_current > (battery_current_limit_mA * 9 / 10)) {
+			/*
+			 * increase apu power limit by
+			 * (1.2*((battery current - 3.57)* battery voltage)
+			 */
+			if (dc_safety_power_limit_level) {
+				throttle_ap(THROTTLE_OFF, THROTTLE_HARD,
+					THROTTLE_SRC_BAT_DISCHG_CURRENT);
+				dc_safety_power_limit_level = 0;
+			} else {
+				if (power_limit[FUNCTION_SAFETY].mwatt[TYPE_SPL]
+					== power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPL]) {
+					powerlimit_restore = 0;
+					return;
+				}
+				delta = (ABS(battery_current - battery_current_limit_mA)
+					* battery_voltage) * 12 / 10 / 1000;
+				new_mwatt = new_mwatt + delta;
+
+				power_limit[FUNCTION_SAFETY].mwatt[TYPE_SPL] = MIN(new_mwatt,
+					power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPL]);
+				power_limit[FUNCTION_SAFETY].mwatt[TYPE_SPPT]
+					= power_limit[FUNCTION_SAFETY].mwatt[TYPE_SPL];
+				power_limit[FUNCTION_SAFETY].mwatt[TYPE_FPPT]
+					= power_limit[FUNCTION_SAFETY].mwatt[TYPE_SPL];
+				CPRINTF("batt ocp recover, delta: %d, new PL: %d\n",
+					delta, power_limit[FUNCTION_SAFETY].mwatt[TYPE_SPL]);
+			}
+		}
+	}
+}
+
+void update_soc_power_limit(bool force_update, bool force_no_adapter)
+{
+	static uint32_t old_sustain_power_limit;
+	static uint32_t old_fast_ppt_limit;
+	static uint32_t old_slow_ppt_limit;
+	static uint32_t old_p3t_limit;
+	static int old_slider_mode;
+	static int set_pl_limit;
+	int mode = *host_get_memmap(EC_MEMMAP_POWER_SLIDE);
+	int active_mpower = charge_manager_get_power_limit_uw() / 1000;
+	bool with_dc = ((battery_is_present() == BP_YES) ? true : false);
+	int battery_percent = charge_get_percent();
+
+	if (!chipset_in_state(CHIPSET_STATE_ON) || !get_apu_ready())
+		return;
+
+	if (mode_ctl)
+		mode = mode_ctl;
+
+	if (force_no_adapter || (!extpower_is_present())) {
+		active_mpower = 0;
+	}
+
+	if (old_slider_mode != mode) {
+		old_slider_mode = mode;
+		if (func_ctl & 0x1)
+			update_os_power_slider(mode, active_mpower);
+	}
+
+	if (func_ctl & 0x2)
+		update_adapter_power_limit(battery_percent, active_mpower, with_dc);
+
+	if (active_mpower == 0) {
+		if (func_ctl & 0x4)
+			update_dc_safety_power_limit();
+	} else {
+		for (int item = TYPE_SPL; item < TYPE_COUNT; item++)
+			power_limit[FUNCTION_SAFETY].mwatt[item] = 0;
+		powerlimit_restore = 0;
+
+		if (dc_safety_power_limit_level) {
+			throttle_ap(THROTTLE_OFF, THROTTLE_HARD,
+					THROTTLE_SRC_BAT_DISCHG_CURRENT);
+			dc_safety_power_limit_level = 0;
+		}
+	}
+
+	/* when trigger thermal warm, reduce SPPT to 15W */
+	if (thermal_warn_trigger())
+		power_limit[FUNCTION_THERMAL].mwatt[TYPE_SPPT] = 15000;
+	else
+		power_limit[FUNCTION_THERMAL].mwatt[TYPE_SPPT] = 0;
+
+	/* choose the lowest one */
+	for (int item = TYPE_SPL; item < TYPE_COUNT; item++) {
+		/* use slider as default */
+		target_func[item] = FUNCTION_SLIDER;
+		for (int func = FUNCTION_DEFAULT; func < FUNCTION_COUNT; func++) {
+			if (power_limit[func].mwatt[item] < 1)
+				continue;
+			if (power_limit[target_func[item]].mwatt[item]
+				> power_limit[func].mwatt[item])
+				target_func[item] = func;
+		}
+	}
+
+	/* p3t follow power table */
+	target_func[TYPE_P3T] = FUNCTION_POWER;
+
+	if (power_limit[target_func[TYPE_SPL]].mwatt[TYPE_SPL] != old_sustain_power_limit
+		|| power_limit[target_func[TYPE_FPPT]].mwatt[TYPE_FPPT] != old_fast_ppt_limit
+		|| power_limit[target_func[TYPE_SPPT]].mwatt[TYPE_SPPT] != old_slow_ppt_limit
+		|| power_limit[target_func[TYPE_P3T]].mwatt[TYPE_P3T] != old_p3t_limit
+		|| set_pl_limit || force_update) {
+		/* only set PL when it is changed */
+		old_sustain_power_limit = power_limit[target_func[TYPE_SPL]].mwatt[TYPE_SPL];
+		old_slow_ppt_limit = power_limit[target_func[TYPE_SPPT]].mwatt[TYPE_SPPT];
+		old_fast_ppt_limit = power_limit[target_func[TYPE_FPPT]].mwatt[TYPE_FPPT];
+		old_p3t_limit = power_limit[target_func[TYPE_P3T]].mwatt[TYPE_P3T];
+
+		CPRINTF("Change SOC Power Limit: SPL %dmW, sPPT %dmW, fPPT %dmW, p3T %dmW\n",
+			old_sustain_power_limit, old_slow_ppt_limit,
+			old_fast_ppt_limit, old_p3t_limit);
+		set_pl_limit = set_pl_limits(old_sustain_power_limit, old_fast_ppt_limit,
+			old_slow_ppt_limit, old_p3t_limit);
+	}
+}
+
+static void initial_soc_power_limit(void)
+{
+	const char *str = "FRANGWAT01";
+	static int pre_battery_type;
+
+	battery_mwatt_type =
+		(!strncmp(battery_static[BATT_IDX_MAIN].model_ext, str, 10) ?
+		BATTERY_61mW : BATTERY_55mW);
+
+	if (pre_battery_type != battery_mwatt_type)
+		pre_battery_type = battery_mwatt_type;
+	else
+		return;
+
+	battery_current_limit_mA =
+		((battery_mwatt_type == BATTERY_61mW) ? -3920 : -3570);
+
+	/* initial slider table to battery balance as default */
+	power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPL] = 28000;
+	power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPPT] = 33000;
+	power_limit[FUNCTION_SLIDER].mwatt[TYPE_FPPT] =
+		((battery_mwatt_type == BATTERY_61mW) ? 41000 : 35000);
+	power_limit[FUNCTION_SLIDER].mwatt[TYPE_P3T] =
+		((battery_mwatt_type == BATTERY_61mW) ? 70000 : 80000);
+	power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] =
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_P3T];
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, initial_soc_power_limit, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, initial_soc_power_limit, HOOK_PRIO_DEFAULT);
diff --git a/zephyr/program/framework/azalea/src/keyboard_customization.c b/zephyr/program/framework/azalea/src/keyboard_customization.c
new file mode 100644
index 0000000000..fc32654abb
--- /dev/null
+++ b/zephyr/program/framework/azalea/src/keyboard_customization.c
@@ -0,0 +1,481 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "board_host_command.h"
+#include "common.h"
+#include "chipset.h"
+#include "customized_shared_memory.h"
+#include "factory.h"
+#include "keyboard_customization.h"
+#include "keyboard_8042.h"
+#include "keyboard_8042_sharedlib.h"
+#include "keyboard_config.h"
+#include "keyboard_protocol.h"
+#include "keyboard_raw.h"
+#include "keyboard_scan.h"
+#include "keyboard_backlight.h"
+#include "pwm.h"
+#include "hooks.h"
+#include "system.h"
+#include "hid_device.h"
+
+/* Console output macros */
+#define CPUTS(outstr) cputs(CC_KEYBOARD, outstr)
+#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_KEYBOARD, format, ## args)
+
+uint16_t scancode_set2[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = {
+		{0x0021, 0x007B, 0x0079, 0x0072, 0x007A, 0x0071, 0x0069, 0xe04A},
+		{0xe071, 0xe070, 0x007D, 0xe01f, 0x006c, 0xe06c, 0xe07d, 0x0077},
+		{0x0015, 0x0070, 0x00ff, 0x000D, 0x000E, 0x0016, 0x0067, 0x001c},
+		{0xe011, 0x0011, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
+		{0xe05a, 0x0029, 0x0024, 0x000c, 0x0058, 0x0026, 0x0004, 0xe07a},
+		{0x0022, 0x001a, 0x0006, 0x0005, 0x001b, 0x001e, 0x001d, 0x0076},
+		{0x002A, 0x0032, 0x0034, 0x002c, 0x002e, 0x0025, 0x002d, 0x002b},
+		{0x003a, 0x0031, 0x0033, 0x0035, 0x0036, 0x003d, 0x003c, 0x003b},
+		{0x0049, 0xe072, 0x005d, 0x0044, 0x0009, 0x0046, 0x0078, 0x004b},
+		{0x0059, 0x0012, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
+		{0x0041, 0x007c, 0x0083, 0x000b, 0x0003, 0x003e, 0x0043, 0x0042},
+		{0x0013, 0x0064, 0x0075, 0x0001, 0x0051, 0x0061, 0xe06b, 0xe02f},
+		{0xe014, 0x0014, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
+		{0x004a, 0xe075, 0x004e, 0x0007, 0x0045, 0x004d, 0x0054, 0x004c},
+		{0x0052, 0x005a, 0xe03c, 0xe069, 0x0055, 0x0066, 0x005b, 0x0023},
+		{0x006a, 0x000a, 0xe074, 0xe054, 0x0000, 0x006b, 0x0073, 0x0074},
+};
+
+
+uint16_t get_scancode_set2(uint8_t row, uint8_t col)
+{
+	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS)
+		return scancode_set2[col][row];
+	return 0;
+}
+
+void set_scancode_set2(uint8_t row, uint8_t col, uint16_t val)
+{
+	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS)
+		scancode_set2[col][row] = val;
+}
+
+#ifdef CONFIG_PLATFORM_EC_KEYBOARD_DEBUG
+static char keycap_label[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = {
+	{KLLI_UNKNO, KLLI_UNKNO, KLLI_L_CTR, KLLI_SEARC,
+			KLLI_R_CTR, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO},
+	{KLLI_F11,   KLLI_ESC,   KLLI_TAB,   '~',
+			'a',        'z',        '1',        'q'},
+	{KLLI_F1,    KLLI_F4,    KLLI_F3,    KLLI_F2,
+			'd',        'c',        '3',        'e'},
+	{'b',        'g',        't',        '5',
+			'f',        'v',        '4',        'r'},
+	{KLLI_F10,   KLLI_F7,    KLLI_F6,    KLLI_F5,
+			's',        'x',        '2',        'w'},
+	{KLLI_UNKNO, KLLI_F12,   ']',        KLLI_F13,
+			'k',        ',',        '8',        'i'},
+	{'n',        'h',        'y',        '6',
+			'j',        'm',        '7',        'u'},
+	{KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+			KLLI_UNKNO, KLLI_L_SHT, KLLI_UNKNO, KLLI_R_SHT},
+	{'=',        '\'',       '[',        '-',
+			';',        '/',        '0',        'p'},
+	{KLLI_F14,   KLLI_F9,    KLLI_F8,    KLLI_UNKNO,
+			'|',        '.',        '9',        'o'},
+	{KLLI_R_ALT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+			KLLI_UNKNO, KLLI_UNKNO, KLLI_L_ALT, KLLI_UNKNO},
+	{KLLI_F15,   KLLI_B_SPC, KLLI_UNKNO, '\\',
+			KLLI_ENTER, KLLI_SPACE, KLLI_DOWN,  KLLI_UP},
+	{KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+			KLLI_UNKNO, KLLI_UNKNO, KLLI_RIGHT, KLLI_LEFT},
+};
+
+uint8_t get_keycap_label(uint8_t row, uint8_t col)
+{
+	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS)
+		return keycap_label[col][row];
+	return KLLI_UNKNO;
+}
+
+void set_keycap_label(uint8_t row, uint8_t col, uint8_t val)
+{
+	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS)
+		keycap_label[col][row] = val;
+}
+#endif
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/*
+	 * F3 key scan cycle completed but scan input is not
+	 * charging to logic high when EC start scan next
+	 * column for "T" key, so we set .output_settle_us
+	 * to 80us from 50us.
+	 */
+	.output_settle_us = 80,
+	.debounce_down_us = 20 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0xff, 0xff, 0xff, 0x03, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0x03, 0xff, 0xff, 0x03, 0xff, 0xff, 0xef  /* full set */
+	},
+};
+
+/*
+ * TODO:
+ * Azalea will change HW design at DVT
+ * KBL will use PWM, for now will use GPIO control first
+ */
+
+enum backlight_brightness {
+	KEYBOARD_BL_BRIGHTNESS_OFF = 0,
+	KEYBOARD_BL_BRIGHTNESS_LOW = 20,
+	KEYBOARD_BL_BRIGHTNESS_MED = 50,
+	KEYBOARD_BL_BRIGHTNESS_HIGH = 100,
+};
+
+uint8_t bl_brightness = KEYBOARD_BL_BRIGHTNESS_OFF;
+
+#define SCROLL_LED BIT(0)
+#define NUM_LED BIT(1)
+#define CAPS_LED BIT(2)
+static uint8_t caps_led_status;
+
+void board_kblight_init(void)
+{
+	uint8_t current_kblight = 0;
+
+	if (system_get_bbram(SYSTEM_BBRAM_IDX_KBSTATE, &current_kblight) == EC_SUCCESS)
+		kblight_set(current_kblight & 0x7F);
+}
+
+int caps_status_check(void)
+{
+	return caps_led_status;
+}
+
+void board_caps_led_control(int data)
+{
+	if (data & CAPS_LED) {
+		caps_led_status = 1;
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_cap_led), 1);
+	} else {
+		caps_led_status = 0;
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_cap_led), 0);
+	}
+}
+
+void caps_suspend(void)
+{
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_cap_led), 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, caps_suspend, HOOK_PRIO_DEFAULT);
+
+void caps_resume(void)
+{
+	if (caps_status_check())
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_cap_led), 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, caps_resume, HOOK_PRIO_DEFAULT);
+
+
+#define FN_PRESSED BIT(0)
+#define FN_LOCKED BIT(1)
+static uint8_t Fn_key;
+static uint32_t fn_key_table_media;
+static uint32_t fn_key_table;
+
+int fn_table_media_set(int8_t pressed, uint32_t fn_bit)
+{
+	if (pressed) {
+		fn_key_table_media |= fn_bit;
+		return true;
+	} else if (!pressed && (fn_key_table_media & fn_bit)) {
+		fn_key_table_media &= ~fn_bit;
+		return true;
+	}
+
+	return false;
+}
+
+int fn_table_set(int8_t pressed, uint32_t fn_bit)
+{
+	if (pressed && (Fn_key & FN_PRESSED)) {
+		fn_key_table |= fn_bit;
+		return true;
+	} else if (!pressed && (fn_key_table & fn_bit)) {
+		fn_key_table &= ~fn_bit;
+		return true;
+	}
+
+	return false;
+}
+
+void fnkey_shutdown(void)
+{
+	uint8_t current_kb = 0;
+
+	current_kb |= kblight_get() & 0x7F;
+
+	if (Fn_key & FN_LOCKED) {
+		current_kb |= 0x80;
+	}
+	system_set_bbram(SYSTEM_BBRAM_IDX_KBSTATE, current_kb);
+
+	Fn_key &= ~FN_LOCKED;
+	Fn_key &= ~FN_PRESSED;
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, fnkey_shutdown, HOOK_PRIO_DEFAULT);
+
+
+void fnkey_startup(void)
+{
+	uint8_t current_kb = 0;
+
+	if (system_get_bbram(SYSTEM_BBRAM_IDX_KBSTATE, &current_kb) == EC_SUCCESS) {
+		if (current_kb & 0x80) {
+			Fn_key |= FN_LOCKED;
+		}
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, fnkey_startup, HOOK_PRIO_DEFAULT);
+
+int hotkey_F1_F12(uint16_t *key_code, uint16_t fn, int8_t pressed)
+{
+	const uint16_t prss_key = *key_code;
+
+	if (!(Fn_key & FN_LOCKED) &&
+		(fn & FN_PRESSED))
+		return EC_SUCCESS;
+	else if (Fn_key & FN_LOCKED &&
+		!(fn & FN_PRESSED) &&
+		!fn_key_table_media)
+		return EC_SUCCESS;
+	else if (!fn_key_table_media && !pressed)
+		return EC_SUCCESS;
+
+	switch (prss_key) {
+	case SCANCODE_F1:  /* SPEAKER_MUTE */
+		if (fn_table_media_set(pressed, KB_FN_F1))
+			*key_code = SCANCODE_VOLUME_MUTE;
+		break;
+	case SCANCODE_F2:  /* VOLUME_DOWN */
+		if (fn_table_media_set(pressed, KB_FN_F2))
+			*key_code = SCANCODE_VOLUME_DOWN;
+		break;
+	case SCANCODE_F3:  /* VOLUME_UP */
+		if (fn_table_media_set(pressed, KB_FN_F3))
+			*key_code = SCANCODE_VOLUME_UP;
+		break;
+	case SCANCODE_F4:  /* PREVIOUS_TRACK */
+		if (fn_table_media_set(pressed, KB_FN_F4))
+			*key_code = SCANCODE_PREV_TRACK;
+		break;
+	case SCANCODE_F5:  /* PLAY_PAUSE */
+		if (fn_table_media_set(pressed, KB_FN_F5))
+			*key_code = 0xe034;
+		break;
+	case SCANCODE_F6:  /* NEXT_TRACK */
+		if (fn_table_media_set(pressed, KB_FN_F6))
+			*key_code = SCANCODE_NEXT_TRACK;
+		break;
+	case SCANCODE_F7:  /* TODO: DIM_SCREEN */
+		if (fn_table_media_set(pressed, KB_FN_F7)) {
+			hid_consumer(BUTTON_ID_BRIGHTNESS_DECREMENT, pressed);
+			return EC_ERROR_UNIMPLEMENTED;
+		}
+		break;
+	case SCANCODE_F8:  /* TODO: BRIGHTEN_SCREEN */
+		if (fn_table_media_set(pressed, KB_FN_F8)) {
+			hid_consumer(BUTTON_ID_BRIGHTNESS_INCREMENT, pressed);
+			return EC_ERROR_UNIMPLEMENTED;
+		}
+		break;
+	case SCANCODE_F9:  /* EXTERNAL_DISPLAY */
+		if (fn_table_media_set(pressed, KB_FN_F9)) {
+			if (pressed) {
+				simulate_keyboard(SCANCODE_LEFT_WIN, 1);
+				simulate_keyboard(SCANCODE_P, 1);
+			} else {
+				simulate_keyboard(SCANCODE_P, 0);
+				simulate_keyboard(SCANCODE_LEFT_WIN, 0);
+			}
+			return EC_ERROR_UNIMPLEMENTED;
+		}
+		break;
+	case SCANCODE_F10:  /* FLIGHT_MODE */
+		if (fn_table_media_set(pressed, KB_FN_F10)) {
+			hid_airplane(pressed);
+			return EC_ERROR_UNIMPLEMENTED;
+		}
+		break;
+	case SCANCODE_F11:
+		/* Print screen / SYSRQ */
+		if (fn_table_media_set(pressed, KB_FN_F11))
+			*key_code = 0xE07C;
+		break;
+	case SCANCODE_F12:  /* TODO: FRAMEWORK */
+		/* Media Select scan code */
+		if (fn_table_media_set(pressed, KB_FN_F12))
+			*key_code = 0xE050;
+		break;
+	default:
+		return EC_SUCCESS;
+	}
+	return EC_SUCCESS;
+}
+
+
+int hotkey_special_key(uint16_t *key_code, int8_t pressed)
+{
+	const uint16_t prss_key = *key_code;
+
+	switch (prss_key) {
+	case SCANCODE_DELETE:  /* TODO: INSERT */
+		if (fn_table_set(pressed, KB_FN_DELETE))
+			*key_code = 0xe070;
+		break;
+	case SCANCODE_K:  /* TODO: SCROLL_LOCK */
+		if (fn_table_set(pressed, KB_FN_K))
+			*key_code = SCANCODE_SCROLL_LOCK;
+		break;
+	case SCANCODE_LEFT:  /* HOME */
+		if (fn_table_set(pressed, KB_FN_LEFT))
+			*key_code = 0xe06c;
+		break;
+	case SCANCODE_RIGHT:  /* END */
+		if (fn_table_set(pressed, KB_FN_RIGHT))
+			*key_code = 0xe069;
+		break;
+	case SCANCODE_UP:  /* PAGE_UP */
+		if (fn_table_set(pressed, KB_FN_UP))
+			*key_code = 0xe07d;
+		break;
+	case SCANCODE_DOWN:  /* PAGE_DOWN */
+		if (fn_table_set(pressed, KB_FN_DOWN))
+			*key_code = 0xe07a;
+		break;
+	default:
+		return EC_SUCCESS;
+	}
+
+	return EC_SUCCESS;
+}
+
+int functional_hotkey(uint16_t *key_code, int8_t pressed)
+{
+	const uint16_t prss_key = *key_code;
+
+	switch (prss_key) {
+	case SCANCODE_ESC: /* TODO: FUNCTION_LOCK */
+		if (fn_table_set(pressed, KB_FN_ESC)) {
+			if (pressed) {
+				if (Fn_key & FN_LOCKED)
+					Fn_key &= ~FN_LOCKED;
+				else
+					Fn_key |= FN_LOCKED;
+			}
+			return EC_ERROR_UNIMPLEMENTED;
+		}
+		break;
+	case SCANCODE_B:
+		/* BREAK_KEY */
+		if (fn_table_set(pressed, KB_FN_B)) {
+			if (pressed) {
+				simulate_keyboard(0xe07e, 1);
+				simulate_keyboard(0xe0, 1);
+				simulate_keyboard(0x7e, 0);
+			}
+			return EC_ERROR_UNIMPLEMENTED;
+		}
+		break;
+	case SCANCODE_P:
+		/* PAUSE_KEY */
+		if (fn_table_set(pressed, KB_FN_P)) {
+			if (pressed) {
+				simulate_keyboard(0xe114, 1);
+				simulate_keyboard(0x77, 1);
+				simulate_keyboard(0xe1, 1);
+				simulate_keyboard(0x14, 0);
+				simulate_keyboard(0x77, 0);
+			}
+			return EC_ERROR_UNIMPLEMENTED;
+		}
+		break;
+	case SCANCODE_SPACE:	/* TODO: TOGGLE_KEYBOARD_BACKLIGHT */
+		if (fn_table_set(pressed, KB_FN_SPACE)) {
+			if (pressed) {
+				bl_brightness = kblight_get();
+				switch (bl_brightness) {
+				case KEYBOARD_BL_BRIGHTNESS_LOW:
+					bl_brightness = KEYBOARD_BL_BRIGHTNESS_MED;
+					break;
+				case KEYBOARD_BL_BRIGHTNESS_MED:
+					bl_brightness = KEYBOARD_BL_BRIGHTNESS_HIGH;
+					break;
+				case KEYBOARD_BL_BRIGHTNESS_HIGH:
+					bl_brightness = KEYBOARD_BL_BRIGHTNESS_OFF;
+					break;
+				default:
+				case KEYBOARD_BL_BRIGHTNESS_OFF:
+					bl_brightness = KEYBOARD_BL_BRIGHTNESS_LOW;
+					break;
+				}
+				kblight_set(bl_brightness);
+			}
+			/* we dont want to pass the space key event to the OS */
+			return EC_ERROR_UNIMPLEMENTED;
+		}
+		break;
+	}
+	return EC_SUCCESS;
+}
+
+enum ec_error_list keyboard_scancode_callback(uint16_t *make_code,
+					      int8_t pressed)
+{
+	const uint16_t pressed_key = *make_code;
+	int r = 0;
+
+	if (factory_status())
+		return EC_SUCCESS;
+
+	if (pressed_key == SCANCODE_FN && pressed) {
+		Fn_key |= FN_PRESSED;
+		return EC_ERROR_UNIMPLEMENTED;
+	} else if (pressed_key == SCANCODE_FN && !pressed) {
+		Fn_key &= ~FN_PRESSED;
+		return EC_ERROR_UNIMPLEMENTED;
+	}
+
+	/*
+	 * If the system still in preOS
+	 * then we pass through all events without modifying them
+	 * will refact BIT after dGPU merged
+	 */
+	if (!*host_get_memmap(EC_CUSTOMIZED_MEMMAP_SYSTEM_FLAGS) & BIT(0))
+		return EC_SUCCESS;
+
+	r = hotkey_F1_F12(make_code, Fn_key, pressed);
+	if (r != EC_SUCCESS)
+		return r;
+	/*
+	 * If the function key is not held then
+	 * we pass through all events without modifying them
+	 * but if last time have press FN still need keep that
+	 */
+	if (!(Fn_key & FN_PRESSED) && !fn_key_table)
+		return EC_SUCCESS;
+
+	r = hotkey_special_key(make_code, pressed);
+	if (r != EC_SUCCESS)
+		return r;
+
+	r = functional_hotkey(make_code, pressed);
+	if (r != EC_SUCCESS)
+		return r;
+
+	return EC_SUCCESS;
+}
diff --git a/zephyr/program/framework/azalea/src/power_button_x86.c b/zephyr/program/framework/azalea/src/power_button_x86.c
new file mode 100644
index 0000000000..ce62f98e75
--- /dev/null
+++ b/zephyr/program/framework/azalea/src/power_button_x86.c
@@ -0,0 +1,597 @@
+/* Copyright 2013 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Power button state machine for x86 platforms */
+
+#include "board_adc.h"
+#include "board_function.h"
+#include "charge_state.h"
+#include "customized_shared_memory.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "extpower.h"
+#include "diagnostics.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "power_button.h"
+#include "power_sequence.h"
+#include "switch.h"
+#include "system.h"
+#include "task.h"
+#include "timer.h"
+#include "util.h"
+
+/* Console output macros */
+#define CPUTS(outstr) cputs(CC_SWITCH, outstr)
+#define CPRINTS(format, args...) cprints(CC_SWITCH, format, ##args)
+
+/*
+ * x86 chipsets have a hardware timer on the power button input which causes
+ * them to reset when the button is pressed for more than 4 seconds.  This is
+ * problematic for Chrome OS, which needs more time than that to transition
+ * through the lock and logout screens.  So when the system is on, we need to
+ * stretch the power button signal so that the chipset will hard-reboot after 8
+ * seconds instead of 4.
+ *
+ * When the button is pressed, we initially send a short pulse (t0); this
+ * allows the chipset to process its initial power button interrupt and do
+ * things like wake from suspend.  We then deassert the power button signal to
+ * the chipset for (t1 = 4 sec - t0), which keeps the chipset from starting its
+ * hard reset timer.  If the power button is still pressed after this period,
+ * we again assert the power button signal for the remainder of the press
+ * duration.  Since (t0+t1) causes a 4-second offset, the hard reset timeout in
+ * the chipset triggers after 8 seconds as desired.
+ *
+ *   PWRBTN#   ---                                          ----
+ *     to EC     |__________________________________________|
+ *
+ *
+ *   PWRBTN#   ---  ---------                               ----
+ *    to PCH     |__|       |_______________________________|
+ *                t0    t1  |    t2    |     t3    |
+ *
+ *   scan code   |                                          |
+ *    to host    v                                          v
+ *     @S0   make code                                 break code
+ */
+#define PWRBTN_DELAY_INIT (5 * MSEC) /* 5ms to wait VALW power rail ready*/
+#define PWRBTN_DELAY_T0 (32 * MSEC) /* 32ms (PCH requires >16ms) */
+#define PWRBTN_DELAY_T1 (4 * SECOND - PWRBTN_DELAY_T0) /* 4 secs - t0 */
+#define PWRBTN_DELAY_T2 (4 * SECOND) /* Force CPU to G3 */
+#define PWRBTN_DELAY_T3 (4 * SECOND) /* EC reset */
+/*
+ * Length of time to stretch initial power button press to give chipset a
+ * chance to wake up (~100ms) and react to the press (~16ms).  Also used as
+ * pulse length for simulated power button presses when the system is off.
+ */
+#define PWRBTN_INITIAL_US (200 * MSEC)
+
+enum power_button_state {
+	/* Button up; state machine idle */
+	PWRBTN_STATE_IDLE = 0,
+	/* Button pressed; debouncing done */
+	PWRBTN_STATE_PRESSED,
+	/* Button down, chipset on; sending initial short pulse */
+	PWRBTN_STATE_T0,
+	/* Button down, chipset on; delaying until we should reassert signal */
+	PWRBTN_STATE_T1,
+	/* Button down, signal asserted to chipset */
+	PWRBTN_STATE_HELD,
+	/* Force pulse due to lid-open event */
+	PWRBTN_STATE_LID_OPEN,
+	/* Button released; debouncing done */
+	PWRBTN_STATE_RELEASED,
+	/* Ignore next button release */
+	PWRBTN_STATE_EAT_RELEASE,
+	/*
+	 * Need to power on system after init, but waiting to find out if
+	 * sufficient battery power.
+	 */
+	PWRBTN_STATE_INIT_ON,
+	/* Forced pulse at EC boot due to keyboard controlled reset */
+	PWRBTN_STATE_BOOT_KB_RESET,
+	/* Power button pressed when chipset was off; stretching pulse */
+	PWRBTN_STATE_WAS_OFF,
+	/* Power button pressed keep long time; reset EC */
+	PWRBTN_STATE_NEED_RESET,
+	/* Power button press keep long time; force shutdown */
+	PWRBTN_STATE_NEED_SHUTDOWN,
+};
+static enum power_button_state pwrbtn_state = PWRBTN_STATE_IDLE;
+
+static const char *const state_names[] = {
+	"idle",	    "pressed",	   "t0",      "t1",	  "held",    "lid-open",
+	"released", "eat-release", "init-on", "recovery", "was-off", "need-reset",
+	"need-shutdown",
+};
+
+/*
+ * Time for next state transition of power button state machine, or 0 if the
+ * state doesn't have a timeout.
+ */
+static uint64_t tnext_state;
+
+/*
+ * Record the time when power button task starts. It can be used by any code
+ * path that needs to compare the current time with power button task start time
+ * to identify any timeouts e.g. PB state machine checks current time to
+ * identify if it should wait more for charger and battery to be initialized. In
+ * case of recovery using buttons (where the user could be holding the buttons
+ * for >30seconds), it is not right to compare current time with the time when
+ * EC was reset since the tasks would not have started. Hence, this variable is
+ * being added to record the time at which power button task starts.
+ */
+static uint64_t tpb_task_start;
+
+/*
+ * Determines whether to execute power button pulse (t0 stage)
+ */
+static int power_button_pulse_enabled = 1;
+
+static void set_pwrbtn_to_pch(int high, int init)
+{
+	/*
+	 * If the battery is discharging and low enough we'd shut down the
+	 * system, don't press the power button. Also, don't press the
+	 * power button if the battery is charging but the battery level
+	 * is too low.
+	 */
+#ifdef CONFIG_CHARGER
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF) && !high &&
+	    (charge_want_shutdown() || charge_prevent_power_on(!init))) {
+		CPRINTS("PB PCH pwrbtn ignored due to battery level");
+		high = 1;
+	}
+#endif
+	gpio_set_level(GPIO_PCH_PWRBTN_L, high);
+}
+
+void power_button_pch_release(void)
+{
+	CPRINTS("PB PCH force release");
+
+	/* Deassert power button signal to PCH */
+	set_pwrbtn_to_pch(1, 0);
+
+	/*
+	 * If power button is actually pressed, eat the next release so we
+	 * don't send an extra release.
+	 */
+	if (power_button_is_pressed())
+		pwrbtn_state = PWRBTN_STATE_EAT_RELEASE;
+	else
+		pwrbtn_state = PWRBTN_STATE_IDLE;
+}
+
+void power_button_pch_pulse(void)
+{
+	CPRINTS("PB PCH pulse");
+
+	chipset_exit_hard_off();
+	set_pwrbtn_to_pch(0, 0);
+	pwrbtn_state = PWRBTN_STATE_LID_OPEN;
+	tnext_state = get_time().val + PWRBTN_INITIAL_US;
+	task_wake(TASK_ID_POWERBTN);
+}
+
+/**
+ * Handle debounced power button down.
+ */
+static void power_button_pressed(uint64_t tnow)
+{
+	CPRINTS("PB pressed");
+	pwrbtn_state = PWRBTN_STATE_PRESSED;
+	tnext_state = tnow;
+}
+
+/**
+ * Handle debounced power button up.
+ */
+static void power_button_released(uint64_t tnow)
+{
+	CPRINTS("PB released");
+	pwrbtn_state = PWRBTN_STATE_RELEASED;
+	tnext_state = tnow;
+}
+
+/**
+ * Set initial power button state.
+ */
+static void set_initial_pwrbtn_state(void)
+{
+	uint32_t reset_flags = system_get_reset_flags();
+
+	if (reset_flags == EC_RESET_FLAG_HARD) {
+		pwrbtn_state = PWRBTN_STATE_INIT_ON;
+		CPRINTS("PB init-on after updating firmware");
+	} else if (((reset_flags & EC_RESET_FLAG_HIBERNATE) == EC_RESET_FLAG_HIBERNATE) &&
+		(gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_hw_acav_in)) == 0)) {
+		/**
+		 * If EC wake from power button and the power button already release.
+		 * check the chassis status and standalone mode status.
+		 */
+		if ((gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_chassis_open_l)) == 0) &&
+			(gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_on_off_btn_l)) == 1) &&
+			!get_standalone_mode()) {
+			pwrbtn_state = PWRBTN_STATE_IDLE;
+			CPRINTS("PB ignore signal");
+			return;
+		}
+
+		/**
+		 * EC needs to auto power on after exiting the hibernate mode w/o external power
+		 */
+		pwrbtn_state = PWRBTN_STATE_INIT_ON;
+		CPRINTS("PB init power on");
+	} else if (ac_boot_status() &&
+		(gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_hw_acav_in)) == 1)) {
+
+		/**
+		 * Only the developer will trigger the reset pin or soft flags.
+		 * We don't want the system to power automatically if we reset
+		 * the EC during development.
+		 */
+		if (!!(reset_flags & EC_RESET_FLAG_SOFT) ||
+			!!(reset_flags & EC_RESET_FLAG_RESET_PIN))
+			return;
+
+		/* BIOS setup AC attach power on */
+		pwrbtn_state = PWRBTN_STATE_INIT_ON;
+		CPRINTS("PB init AC attach on");
+	} else {
+		pwrbtn_state = PWRBTN_STATE_IDLE;
+		CPRINTS("PB idle");
+	}
+}
+
+/**
+ * auto power on system when AC plug-in
+ */
+static void board_extpower(void)
+{
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
+		extpower_is_present() && ac_boot_status()) {
+		CPRINTS("Power on from boot on AC present");
+		power_button_pch_pulse();
+	}
+}
+DECLARE_HOOK(HOOK_AC_CHANGE, board_extpower, HOOK_PRIO_DEFAULT);
+
+/**
+ * Power button state machine.
+ *
+ * @param tnow		Current time from usec counter
+ */
+static void state_machine(uint64_t tnow)
+{
+	/* Not the time to move onto next state */
+	if (tnow < tnext_state)
+		return;
+
+	/* States last forever unless otherwise specified */
+	tnext_state = 0;
+
+	switch (pwrbtn_state) {
+	case PWRBTN_STATE_PRESSED:
+		/* chipset exit hard off function only executes at G3 state */
+		if (chipset_in_state(CHIPSET_STATE_HARD_OFF)) {
+			/*
+			 * Power button out signal implements in power_sequence.c,
+			 * just call the exit hard off start to run the state mechine.
+			 */
+			reset_diagnostics();
+			chipset_exit_hard_off();
+			pwrbtn_state = PWRBTN_STATE_IDLE;
+		} else {
+			/*
+			 * when in preOS still need send power button signal
+			 * until ACPI driver ready
+			 */
+			if (*host_get_memmap(EC_CUSTOMIZED_MEMMAP_SYSTEM_FLAGS)
+				& ACPI_DRIVER_READY) {
+				/*
+				 * When chipset is on and ACPI driver ready,
+				 * we will send the SCI event to trigger modern standby.
+				 */
+				tnext_state = tnow + PWRBTN_DELAY_T1;
+				pwrbtn_state = PWRBTN_STATE_T1;
+			} else {
+				tnext_state = tnow + PWRBTN_DELAY_T0;
+				pwrbtn_state = PWRBTN_STATE_T0;
+				set_pwrbtn_to_pch(0, 0);
+				if (chipset_in_state(CHIPSET_STATE_ON)) {
+					/**
+					 * System in EFI mode (S0), press power button to shutdown
+					 * the system and cancel the diagnostics.
+					 */
+					cancel_diagnostics();
+				} else if (chipset_in_state(CHIPSET_STATE_SOFT_OFF))
+					/**
+					 * System in S5 state, press power button to start up the
+					 * system and reset the diagnostics.
+					 */
+					reset_diagnostics();
+			}
+		}
+		break;
+	case PWRBTN_STATE_T0:
+		tnext_state = tnow + PWRBTN_DELAY_T1;
+		pwrbtn_state = PWRBTN_STATE_T1;
+		set_pwrbtn_to_pch(1, 0);
+		break;
+	case PWRBTN_STATE_T1:
+		/*
+		 * If the chipset is already off, don't tell it the power
+		 * button is down; it'll just cause the chipset to turn on
+		 * again.
+		 */
+		if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+			CPRINTS("PB chipset already off");
+		else
+			set_pwrbtn_to_pch(0, 0);
+		pwrbtn_state = PWRBTN_STATE_HELD;
+		break;
+	case PWRBTN_STATE_RELEASED:
+	case PWRBTN_STATE_LID_OPEN:
+		set_pwrbtn_to_pch(1, 0);
+		pwrbtn_state = PWRBTN_STATE_IDLE;
+		break;
+	case PWRBTN_STATE_INIT_ON:
+
+		/*
+		 * Before attempting to power the system on, we need to allow
+		 * time for charger, battery and USB-C PD initialization to be
+		 * ready to supply sufficient power. Check every 100
+		 * milliseconds, and give up CONFIG_POWER_BUTTON_INIT_TIMEOUT
+		 * seconds after the PB task was started. Here, it is
+		 * important to check the current time against PB task start
+		 * time to prevent unnecessary timeouts happening in recovery
+		 * case where the tasks could start as late as 30 seconds
+		 * after EC reset.
+		 */
+
+		if (!IS_ENABLED(CONFIG_CHARGER) || charge_prevent_power_on(0)) {
+			if (tnow >
+			    (tpb_task_start +
+			     CONFIG_POWER_BUTTON_INIT_TIMEOUT * SECOND)) {
+				pwrbtn_state = PWRBTN_STATE_IDLE;
+				break;
+			}
+
+			if (IS_ENABLED(CONFIG_CHARGER)) {
+				tnext_state = tnow + 100 * MSEC;
+				break;
+			}
+		}
+
+		/*
+		 * Power button out signal implements in power_sequence.c,
+		 * just call the exit hard off start to run the state mechine.
+		 */
+		reset_diagnostics();
+		chipset_exit_hard_off();
+		pwrbtn_state = PWRBTN_STATE_IDLE;
+		break;
+	case PWRBTN_STATE_HELD:
+
+		if (power_button_is_pressed()) {
+			tnext_state = tnow + PWRBTN_DELAY_T2;
+			pwrbtn_state = PWRBTN_STATE_NEED_SHUTDOWN;
+		} else {
+			power_button_released(tnow);
+		}
+
+		break;
+	case PWRBTN_STATE_NEED_SHUTDOWN:
+
+		if (!chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
+			CPRINTS("PB held press 8s execute force shutdown");
+			chipset_force_shutdown(CHIPSET_SHUTDOWN_G3);
+		}
+
+		if (power_button_is_pressed()) {
+			tnext_state = tnow + PWRBTN_DELAY_T3;
+			pwrbtn_state = PWRBTN_STATE_NEED_RESET;
+		} else
+			power_button_released(tnow);
+
+		break;
+	case PWRBTN_STATE_NEED_RESET:
+		if (power_button_is_pressed())
+			system_reset(SYSTEM_RESET_HARD);
+		else
+			power_button_released(tnow);
+		break;
+	case PWRBTN_STATE_BOOT_KB_RESET:
+	case PWRBTN_STATE_WAS_OFF:
+	case PWRBTN_STATE_IDLE:
+	case PWRBTN_STATE_EAT_RELEASE:
+		/* Do nothing */
+		break;
+	}
+}
+
+void power_button_task(void *u)
+{
+	uint64_t t;
+	uint64_t tsleep;
+	enum power_button_state curr_state = PWRBTN_STATE_IDLE;
+
+	/*
+	 * Record the time when the task starts so that the state machine can
+	 * use this to identify any timeouts.
+	 */
+	tpb_task_start = get_time().val;
+
+	while (1) {
+		t = get_time().val;
+
+		/* Update state machine */
+		if (pwrbtn_state != curr_state) {
+			CPRINTS("PB task %d = %s", pwrbtn_state,
+				state_names[pwrbtn_state]);
+			curr_state = pwrbtn_state;
+		}
+
+		state_machine(t);
+
+		/* Sleep until our next timeout */
+		tsleep = -1;
+		if (tnext_state && tnext_state < tsleep)
+			tsleep = tnext_state;
+		t = get_time().val;
+		if (tsleep > t) {
+			uint16_t d = tsleep == -1 ? -1 : (uint16_t)(tsleep - t);
+			/*
+			 * (Yes, the conversion from uint64_t to unsigned could
+			 * theoretically overflow if we wanted to sleep for
+			 * more than 2^32 us, but our timeouts are small enough
+			 * that can't happen - and even if it did, we'd just go
+			 * back to sleep after deciding that we woke up too
+			 * early.)
+			 */
+			if (pwrbtn_state != curr_state) {
+				CPRINTS("PB task %d = %s, wait %d", pwrbtn_state,
+					state_names[pwrbtn_state], d);
+			}
+			task_wait_event(d);
+		}
+	}
+}
+
+/*****************************************************************************/
+/* Hooks */
+
+static void powerbtn_x86_init(void)
+{
+	set_initial_pwrbtn_state();
+}
+DECLARE_HOOK(HOOK_INIT, powerbtn_x86_init, HOOK_PRIO_DEFAULT + 2);
+
+void chipset_power_on(void)
+{
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
+	    pwrbtn_state != PWRBTN_STATE_INIT_ON) {
+		power_button_pch_pulse();
+	}
+}
+
+#ifdef CONFIG_LID_SWITCH
+/**
+ * Handle switch changes based on lid event.
+ */
+static void powerbtn_x86_lid_change(void)
+{
+	/* If chipset in suspend mode, pulse the power button on lid open to wake it. */
+	if (lid_is_open() && chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)
+	    && pwrbtn_state != PWRBTN_STATE_INIT_ON) {
+		chipset_power_on();
+	}
+}
+DECLARE_HOOK(HOOK_LID_CHANGE, powerbtn_x86_lid_change, HOOK_PRIO_DEFAULT);
+#endif
+
+/**
+ * Handle debounced power button changing state.
+ */
+static void powerbtn_x86_changed(void)
+{
+	if (pwrbtn_state == PWRBTN_STATE_BOOT_KB_RESET ||
+	    pwrbtn_state == PWRBTN_STATE_INIT_ON ||
+	    pwrbtn_state == PWRBTN_STATE_LID_OPEN ||
+	    pwrbtn_state == PWRBTN_STATE_WAS_OFF) {
+		/* Ignore all power button changes during an initial pulse */
+		CPRINTS("PB ignoring change");
+		return;
+	}
+
+	if (power_button_is_pressed()) {
+		/* Power button pressed */
+		power_button_pressed(get_time().val);
+	} else {
+		/* Power button released */
+		if (pwrbtn_state == PWRBTN_STATE_EAT_RELEASE) {
+			/*
+			 * Ignore the first power button release if we already
+			 * told the PCH the power button was released.
+			 */
+			CPRINTS("PB ignoring release");
+			pwrbtn_state = PWRBTN_STATE_IDLE;
+			return;
+		}
+
+		power_button_released(get_time().val);
+	}
+
+	/* Wake the power button task */
+	task_wake(TASK_ID_POWERBTN);
+}
+DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, powerbtn_x86_changed, HOOK_PRIO_DEFAULT);
+
+/**
+ * Handle configuring the power button behavior through a host command
+ */
+static enum ec_status hc_config_powerbtn_x86(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_config_power_button *p = args->params;
+
+	power_button_pulse_enabled =
+		!!(p->flags & EC_POWER_BUTTON_ENABLE_PULSE);
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_CONFIG_POWER_BUTTON, hc_config_powerbtn_x86,
+		     EC_VER_MASK(0));
+
+/*
+ * Currently, the only reason why we disable power button pulse is to allow
+ * detachable menu on AP to use power button for selection purpose without
+ * triggering SMI. Thus, re-enable the pulse any time there is a chipset
+ * state transition event.
+ */
+static void power_button_pulse_setting_reset(void)
+{
+	power_button_pulse_enabled = 1;
+}
+
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, power_button_pulse_setting_reset,
+	     HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, power_button_pulse_setting_reset,
+	     HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, power_button_pulse_setting_reset,
+	     HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, power_button_pulse_setting_reset,
+	     HOOK_PRIO_DEFAULT);
+
+#define POWER_BUTTON_SYSJUMP_TAG 0x5042 /* PB */
+#define POWER_BUTTON_HOOK_VERSION 1
+
+static void power_button_pulse_setting_restore_state(void)
+{
+	const int *state;
+	int version, size;
+
+	state = (const int *)system_get_jump_tag(POWER_BUTTON_SYSJUMP_TAG,
+						 &version, &size);
+
+	if (state && (version == POWER_BUTTON_HOOK_VERSION) &&
+	    (size == sizeof(power_button_pulse_enabled)))
+		power_button_pulse_enabled = *state;
+}
+DECLARE_HOOK(HOOK_INIT, power_button_pulse_setting_restore_state,
+	     HOOK_PRIO_POST_POWER_BUTTON);
+
+static void power_button_pulse_setting_preserve_state(void)
+{
+	system_add_jump_tag(POWER_BUTTON_SYSJUMP_TAG, POWER_BUTTON_HOOK_VERSION,
+			    sizeof(power_button_pulse_enabled),
+			    &power_button_pulse_enabled);
+}
+DECLARE_HOOK(HOOK_SYSJUMP, power_button_pulse_setting_preserve_state,
+	     HOOK_PRIO_DEFAULT);
diff --git a/zephyr/program/framework/azalea/src/power_sequence.c b/zephyr/program/framework/azalea/src/power_sequence.c
new file mode 100644
index 0000000000..e34148b070
--- /dev/null
+++ b/zephyr/program/framework/azalea/src/power_sequence.c
@@ -0,0 +1,662 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "board_host_command.h"
+#include "chipset.h"
+#include "config.h"
+#include "console.h"
+#include "customized_shared_memory.h"
+#include "cypress_pd_common.h"
+#include "diagnostics.h"
+#include "espi.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "keyboard_8042_sharedlib.h"
+#include "keyboard_protocol.h"
+#include "lpc.h"
+#include "power.h"
+#include "port80.h"
+#include "power_sequence.h"
+#include "task.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ##args)
+
+#define IN_VR_PGOOD POWER_SIGNAL_MASK(X86_VR_PG)
+
+static int power_s5_up;		/* Chipset is sequencing up or down */
+static int ap_boot_delay = 9;	/* For global reset to wait SLP_S5 signal de-asserts */
+static int s5_exit_tries;	/* For global reset to wait SLP_S5 signal de-asserts */
+static int force_g3_flags;	/* Chipset force to g3 immediately when chipset force shutdown */
+static int stress_test_enable;
+
+/* Power Signal Input List */
+const struct power_signal_info power_signal_list[] = {
+	[X86_3VALW_PG] = {
+		.gpio = GPIO_POWER_GOOD_3VALW,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "3VALW_PG_DEASSERTED",
+	},
+	[X86_SLP_S3_N] = {
+		.gpio = GPIO_PCH_SLP_S3_L,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "SLP_S3_DEASSERTED",
+	},
+	[X86_SLP_S5_N] = {
+		.gpio = GPIO_PCH_SLP_S5_L,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "SLP_S5_DEASSERTED",
+	},
+	[X86_VR_PG] = {
+		.gpio = GPIO_POWER_GOOD_VR,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "VR_PG_DEASSERTED",
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
+
+static int keep_pch_power(void)
+{
+	int wake_source = *host_get_memmap(EC_CUSTOMIZED_MEMMAP_WAKE_EVENT);
+
+	/* This feature only use on the ODM stress test tool */
+	if (wake_source & RTCWAKE)
+		return true;
+	else
+		return false;
+
+}
+
+
+/*
+ * Backup copies of SCI mask to preserve across S0ix suspend/resume
+ * cycle. If the host uses S0ix, BIOS is not involved during suspend and resume
+ * operations and hence SCI masks are programmed only once during boot-up.
+ *
+ * These backup variables are set whenever host expresses its interest to
+ * enter S0ix and then lpc_host_event_mask for SCI are cleared. When
+ * host resumes from S0ix, masks from backup variables are copied over to
+ * lpc_host_event_mask for SCI.
+ */
+static host_event_t backup_sci_mask;
+
+/*
+ * Clear host event masks for SCI when host is entering S0ix. This is
+ * done to prevent any SCI interrupts when the host is in suspend. Since
+ * BIOS is not involved in the suspend path, EC needs to take care of clearing
+ * these masks.
+ */
+static void lpc_s0ix_suspend_clear_masks(void)
+{
+	backup_sci_mask = lpc_get_host_event_mask(LPC_HOST_EVENT_SCI);
+
+	lpc_set_host_event_mask(LPC_HOST_EVENT_SCI, SCI_HOST_WAKE_EVENT_MASK);
+}
+
+/*
+ * Restore host event masks for SCI when host exits S0ix. This is done
+ * because BIOS is not involved in the resume path and so EC needs to restore
+ * the masks from backup variables.
+ */
+static void lpc_s0ix_resume_restore_masks(void)
+{
+	/*
+	 * No need to restore SCI masks if both backup_sci_mask are zero.
+	 * This indicates that there was a failure to enter S0ix
+	 * and hence SCI masks were never backed up.
+	 */
+	if (!backup_sci_mask)
+		return;
+
+	lpc_set_host_event_mask(LPC_HOST_EVENT_SCI, backup_sci_mask);
+
+	backup_sci_mask = 0;
+}
+
+static void clear_rtcwake(void)
+{
+	*host_get_memmap(EC_CUSTOMIZED_MEMMAP_WAKE_EVENT) &= ~BIT(0);
+}
+
+void power_state_clear(int state)
+{
+	*host_get_memmap(EC_CUSTOMIZED_MEMMAP_POWER_STATE) &= ~state;
+}
+
+void power_s5_up_control(int control)
+{
+	CPRINTS("%s power s5 up!", control ? "setup" : "clear");
+	power_s5_up = control;
+}
+
+void clear_power_flags(void)
+{
+	/**
+	 * When system reboot and go into setup menu, we need to set the power_s5_up flag
+	 * to wait SLP_S5 and SLP_S3 signal to boot into OS.
+	 */
+	power_s5_up_control(1);
+
+	power_state_clear(EC_PS_ENTER_S4 | EC_PS_RESUME_S4 |
+		EC_PS_ENTER_S5 | EC_PS_RESUME_S5);
+}
+
+
+#ifdef CONFIG_PLATFORM_EC_POWERSEQ_S0IX
+/*
+ * Backup copies of SCI mask to preserve across S0ix suspend/resume
+ * cycle. If the host uses S0ix, BIOS is not involved during suspend and resume
+ * operations and hence SCI masks are programmed only once during boot-up.
+ *
+ * These backup variables are set whenever host expresses its interest to
+ * enter S0ix and then lpc_host_event_mask for SCI are cleared. When
+ * host resumes from S0ix, masks from backup variables are copied over to
+ * lpc_host_event_mask for SCI.
+ */
+static int enter_ms_flag;
+static int resume_ms_flag;
+static int system_in_s0ix;
+
+static int check_s0ix_statsus(void)
+{
+	int power_status;
+	int clear_flag;
+
+	/* check power state S0ix flags */
+	if (chipset_in_state(CHIPSET_STATE_ON) || chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
+		power_status = *host_get_memmap(EC_CUSTOMIZED_MEMMAP_POWER_STATE);
+
+
+		/**
+		 * Sometimes PCH will set the enter and resume flag continuously
+		 * so clear the EMI when we read the flag.
+		 */
+		if (power_status & EC_PS_ENTER_S0ix)
+			enter_ms_flag++;
+
+		if (power_status & EC_PS_RESUME_S0ix)
+			resume_ms_flag++;
+
+		clear_flag = power_status & (EC_PS_ENTER_S0ix | EC_PS_RESUME_S0ix);
+
+		power_state_clear(clear_flag);
+
+		if (resume_ms_flag)
+			return CS_EXIT_S0ix;
+
+		if (enter_ms_flag)
+			return CS_ENTER_S0ix;
+	}
+	return 0;
+}
+
+void s0ix_status_handle(void)
+{
+	int s0ix_state_change;
+
+	s0ix_state_change = check_s0ix_statsus();
+
+	if ((s0ix_state_change == CS_ENTER_S0ix) && chipset_in_state(CHIPSET_STATE_ON))
+		task_wake(TASK_ID_CHIPSET);
+	else if ((s0ix_state_change == CS_EXIT_S0ix) && chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
+		task_wake(TASK_ID_CHIPSET);
+}
+DECLARE_HOOK(HOOK_TICK, s0ix_status_handle, HOOK_PRIO_DEFAULT);
+
+int check_s0ix_status(void)
+{
+	return system_in_s0ix;
+}
+
+#endif
+
+void chipset_reset(enum chipset_shutdown_reason reason)
+{
+	/* unused function, EC doesn't control GPIO_SYS_RESET_L */
+}
+
+/**
+ * AMD recommended EC needs to check whether the system hangs or not,
+ * If EC detect the system hangs, force reset the system then reboot again.
+ */
+#define VW_NO_READY 0
+void system_hang_detect(void)
+{
+	static int hang_retry_count;
+	int virtual_wire_ready = get_espi_virtual_wire_channel_status();
+
+	if (virtual_wire_ready == VW_NO_READY && hang_retry_count < 4) {
+		hang_retry_count++;
+		board_reboot_ap_on_g3();
+		chipset_force_shutdown(CHIPSET_RESET_HANG_REBOOT);
+	}
+}
+DECLARE_DEFERRED(system_hang_detect);
+
+static void chipset_force_g3(void)
+{
+	hook_call_deferred(&system_hang_detect_data, -1);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_sys_pwrgd_ec), 0);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_vr_on), 0);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_susp_l), 0);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_0p75vs_pwr_en), 0);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_syson), 0);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_soc_rsmrst_l), 0);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_pbtn_out), 0);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_apu_aud_pwr_en), 0);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_pch_pwr_en), 0);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_0p75_1p8valw_pwren), 0);
+}
+
+void chipset_force_shutdown(enum chipset_shutdown_reason reason)
+{
+	CPRINTS("%s(%d)", __func__, reason);
+	if (!chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
+		report_ap_reset(reason);
+		force_g3_flags = 1;
+		chipset_force_g3();
+		clear_rtcwake();
+	}
+}
+
+enum power_state power_chipset_init(void)
+{
+	/* If we don't need to image jump to RW, always start at G3 state */
+	chipset_force_g3();
+	return POWER_G3;
+}
+
+
+
+static int chipset_prepare_S3(uint8_t enable)
+{
+	if (!enable) {
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_sys_pwrgd_ec), 0);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_vr_on), 0);
+		k_msleep(85);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_susp_l), 0);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_0p75vs_pwr_en), 0);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ssd_pwr_en), 0);
+	} else {
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_susp_l), 1);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_0p75vs_pwr_en), 1);
+		k_msleep(20);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_vr_on), 1);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ssd_pwr_en), 1);
+
+		/* wait VR power good */
+		if (power_wait_signals(IN_VR_PGOOD)) {
+			/* something wrong, turn off power and force to g3 */
+			power_chipset_init();
+		}
+
+		k_msleep(10);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_sys_pwrgd_ec), 1);
+	}
+
+	return true;
+}
+
+enum power_state power_handle_state(enum power_state state)
+{
+	switch (state) {
+	case POWER_G3:
+		break;
+
+	case POWER_G3S5:
+		if (power_wait_signals(X86_3VALW_PG)) {
+			/* something wrong, turn off power and force to g3 */
+			chipset_force_g3();
+			return POWER_G3;
+		}
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_0p75_1p8valw_pwren), 1);
+		k_msleep(10);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_apu_aud_pwr_en), 1);
+		k_msleep(10);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_pch_pwr_en), 1);
+		k_msleep(10);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_pbtn_out), 1);
+		k_msleep(10);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_soc_rsmrst_l), 1);
+
+		/* Customizes power button out signal without PB task for powering on. */
+		k_msleep(90);
+		CPRINTS("PCH PBTN LOW");
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_pbtn_out), 0);
+		k_msleep(20);
+		CPRINTS("PCH PBTN HIGH");
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_pbtn_out), 1);
+
+		/* Exit SOC G3 */
+		CPRINTS("Exit SOC G3");
+		power_s5_up_control(1);
+		return POWER_S5;
+
+	case POWER_S5:
+
+		if (force_g3_flags) {
+			force_g3_flags = 0;
+			return POWER_S5G3;
+		}
+
+		if (power_s5_up || stress_test_enable) {
+			while (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_slp_s5_l)) == 0) {
+				if (task_wait_event(SECOND) == TASK_EVENT_TIMER) {
+					if (++s5_exit_tries > ap_boot_delay) {
+						CPRINTS("timeout waiting for S5 exit");
+						/*
+						 * TODO: RTC reset function
+						 */
+						ap_boot_delay = 9;
+						s5_exit_tries = 0;
+						stress_test_enable = 0;
+						set_diagnostic(DIAGNOSTICS_SLP_S4, 1);
+						/* SLP_S5 asserted, power down to G3S5 state */
+						return POWER_S5G3;
+					}
+				}
+			}
+			s5_exit_tries = 0;
+			return POWER_S5S3;
+		}
+
+		if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_slp_s5_l)) == 1) {
+			s5_exit_tries = 0;
+			/* Power up to next state */
+			return POWER_S5S3;
+		}
+
+		break;
+
+	case POWER_S5S3:
+
+		/* Call hooks now that rails are up */
+		hook_call_deferred(&system_hang_detect_data, 5 * SECOND);
+		hook_notify(HOOK_CHIPSET_STARTUP);
+		return POWER_S3;
+
+	case POWER_S3:
+		if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_slp_s3_l)) == 1) {
+
+			/* still in s0ix state */
+			if (system_in_s0ix)
+				return POWER_S3S0ix;
+
+			k_msleep(10);
+			return POWER_S3S0;
+		} else if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_slp_s5_l)) == 0) {
+
+			if (system_in_s0ix) {
+				resume_ms_flag = 0;
+				enter_ms_flag = 0;
+				system_in_s0ix = 0;
+				lpc_s0ix_resume_restore_masks();
+				/* Call hooks now that rails are up */
+				hook_notify(HOOK_CHIPSET_RESUME);
+
+				/* if system drop power return to S0 run sequence shutdown */
+				return POWER_S0;
+			}
+			k_msleep(55);
+			/* Power down to next state */
+			return POWER_S3S5;
+		}
+		break;
+
+	case POWER_S3S0:
+
+		/*
+		 * TODO: distinguish S5 -> S0 and S3 -> S0, the sequences are different
+		 * S5 -> S0: wait 10 - 15 ms then assert the SYSON
+		 * S3 -> S0: wait 10 - 15 ms then assert the SUSP_L
+		 * currently, I will follow the power on sequence to make sure DUT can
+		 * power up from S5.
+		 */
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_syson), 1);
+		k_msleep(20);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_susp_l), 1);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_0p75vs_pwr_en), 1);
+		k_msleep(20);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_vr_on), 1);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ssd_pwr_en), 1);
+
+		/* wait VR power good */
+		if (power_wait_signals(IN_VR_PGOOD)) {
+			/* something wrong, turn off power and force to g3 */
+			set_diagnostic(DIAGNOSTICS_VCCIN_AUX_VR, 1);
+			chipset_force_g3();
+			return POWER_G3;
+		}
+
+		k_msleep(10);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_sys_pwrgd_ec), 1);
+
+		lpc_s0ix_resume_restore_masks();
+		/* Call hooks now that rails are up */
+		hook_notify(HOOK_CHIPSET_RESUME);
+
+		/*
+		 * Disable idle task deep sleep. This means that the low
+		 * power idle task will not go into deep sleep while in S0.
+		 */
+		disable_sleep(SLEEP_MASK_AP_RUN);
+
+		/* set the PD chip system power state "S0" */
+		cypd_set_power_active();
+
+		clear_rtcwake();
+
+		return POWER_S0;
+
+	case POWER_S0:
+
+		if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_slp_s3_l)) == 0) {
+			/* Power down to next state */
+			k_msleep(5);
+			return POWER_S0S3;
+		}
+
+#ifdef CONFIG_PLATFORM_EC_POWERSEQ_S0IX
+		if (check_s0ix_statsus() == CS_ENTER_S0ix)
+			return POWER_S0S0ix;
+#endif
+		break;
+
+#ifdef CONFIG_PLATFORM_EC_POWERSEQ_S0IX
+	case POWER_S0ix:
+		CPRINTS("PH S0ix");
+		if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_slp_s3_l)) == 0) {
+			/*
+			 * If power signal lose, we need to resume to S0 and
+			 * clear the resume ms flag
+			 */
+			if (resume_ms_flag > 0) {
+				resume_ms_flag = 0;
+				enter_ms_flag = 0;
+				system_in_s0ix = 0;
+				return POWER_S0ixS0;
+			}
+			return POWER_S0ixS3;
+		}
+
+		if (check_s0ix_statsus() == CS_EXIT_S0ix)
+			return POWER_S0ixS0;
+
+		break;
+
+	case POWER_S0ixS3:
+		CPRINTS("PH S0ixS3");
+		/* follow power sequence Disable S3 power */
+		chipset_prepare_S3(0);
+		CPRINTS("PH S0ixS0->S3");
+		return POWER_S3;
+
+	case POWER_S3S0ix:
+		CPRINTS("PH S3->S0ix");
+		/* Enable power for CPU check system */
+		chipset_prepare_S3(1);
+		CPRINTS("PH S3S0ix->S0ix");
+		return POWER_S0ix;
+
+	case POWER_S0ixS0:
+		CPRINTS("PH S0ixS0");
+		resume_ms_flag = 0;
+		system_in_s0ix = 0;
+		lpc_s0ix_resume_restore_masks();
+		/* Call hooks now that rails are up */
+		hook_notify(HOOK_CHIPSET_RESUME);
+
+		/*
+		 * Disable idle task deep sleep. This means that the low
+		 * power idle task will not go into deep sleep while in S0.
+		 */
+		disable_sleep(SLEEP_MASK_AP_RUN);
+
+		CPRINTS("PH S0ixS0->S0");
+		return POWER_S0;
+
+		break;
+
+	case POWER_S0S0ix:
+		enter_ms_flag = 0;
+		system_in_s0ix = 1;
+		CPRINTS("PH S0->S0ix");
+		lpc_s0ix_suspend_clear_masks();
+		/* Call hooks before we remove power rails */
+		hook_notify(HOOK_CHIPSET_SUSPEND);
+
+		/*
+		 * Enable idle task deep sleep. Allow the low power idle task
+		 * to go into deep sleep in S3 or lower.
+		 */
+		enable_sleep(SLEEP_MASK_AP_RUN);
+
+		CPRINTS("PH S0S0ix->S0ix");
+		return POWER_S0ix;
+
+		break;
+#endif
+
+	case POWER_S0S3:
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_sys_pwrgd_ec), 0);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_vr_on), 0);
+		k_msleep(85);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_susp_l), 0);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_0p75vs_pwr_en), 0);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ssd_pwr_en), 0);
+
+		lpc_s0ix_suspend_clear_masks();
+		/* Call hooks before we remove power rails */
+		hook_notify(HOOK_CHIPSET_SUSPEND);
+
+		/*
+		 * Enable idle task deep sleep. Allow the low power idle task
+		 * to go into deep sleep in S3 or lower.
+		 */
+		enable_sleep(SLEEP_MASK_AP_RUN);
+
+		/* set the PD chip system power state "S3" */
+		cypd_set_power_active();
+		return POWER_S3;
+
+	case POWER_S3S5:
+		/* Call hooks before we remove power rails */
+		power_s5_up_control(0);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_syson), 0);
+		hook_notify(HOOK_CHIPSET_SHUTDOWN);
+
+		/* set the PD chip system power state "S5" */
+		cypd_set_power_active();
+		return POWER_S5;
+
+	case POWER_S5G3:
+
+		/*
+		 * We need to keep pch power to wait SLP_S5 signal for the below cases:
+		 *
+		 * 1. Customer testing tool
+		 * 2. There is a type-c USB input deck connect on the unit
+		 */
+		if (keep_pch_power())
+			return POWER_S5;
+
+		/* Don't need to keep pch power, turn off the pch power and power down to G3*/
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_soc_rsmrst_l), 0);
+		k_msleep(5);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_pbtn_out), 0);
+		k_msleep(5);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_apu_aud_pwr_en), 0);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_pch_pwr_en), 0);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_0p75_1p8valw_pwren), 0);
+
+		cypd_set_power_active();
+
+
+		return POWER_G3;
+	default:
+		break;
+	}
+	return state;
+}
+
+static void peripheral_power_startup(void)
+{
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_wlan_en), 1);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_h_prochot_l), 1);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_wl_rst_l), 1);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_module_pwr_on), 1);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_cam_en), 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, peripheral_power_startup, HOOK_PRIO_DEFAULT);
+
+static void peripheral_power_resume(void)
+{
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_mute_l), 1);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_sm_panel_bken_ec), 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, peripheral_power_resume, HOOK_PRIO_DEFAULT);
+
+static void peripheral_power_shutdown(void)
+{
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_wlan_en), 0);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_h_prochot_l), 0);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_wl_rst_l), 0);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_module_pwr_on), 0);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_cam_en), 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, peripheral_power_shutdown, HOOK_PRIO_DEFAULT);
+
+static void peripheral_power_suspend(void)
+{
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_mute_l), 0);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_sm_panel_bken_ec), 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, peripheral_power_suspend, HOOK_PRIO_DEFAULT);
+
+void chipset_throttle_cpu(int throttle)
+{
+	if (chipset_in_state(CHIPSET_STATE_ON))
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_h_prochot_l), !throttle);
+}
+
+static enum ec_status set_ap_reboot_delay(struct host_cmd_handler_args *args)
+{
+	const struct ec_response_ap_reboot_delay *p = args->params;
+
+	stress_test_enable = 1;
+	/* don't let AP send zero it will stuck power sequence at S5 */
+	if (p->delay < 181 && p->delay)
+		ap_boot_delay = p->delay;
+	else
+		return EC_ERROR_INVAL;
+
+
+	return EC_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_SET_AP_REBOOT_DELAY, set_ap_reboot_delay,
+			EC_VER_MASK(0));
diff --git a/zephyr/program/framework/azalea/src/project_diagnostics.c b/zephyr/program/framework/azalea/src/project_diagnostics.c
new file mode 100644
index 0000000000..d976c6a8b8
--- /dev/null
+++ b/zephyr/program/framework/azalea/src/project_diagnostics.c
@@ -0,0 +1,74 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "board_host_command.h"
+#include "board_adc.h"
+#include "console.h"
+#include "diagnostics.h"
+#include "dptf.h"
+#include "driver/temp_sensor/f75303.h"
+#include "fan.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "port80.h"
+#include "temp_sensor/temp_sensor.h"
+#include "timer.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+
+#define F75303_I2C_ADDR_FLAGS_4D 0x4D
+#define F75303_PRODUCT_ID 0xFD
+#define F75303_ID	0x21
+
+void start_fan_deferred(void)
+{
+	/* force turn on the fan for diagnostic */
+	dptf_set_fan_duty_target(20);
+}
+DECLARE_DEFERRED(start_fan_deferred);
+
+void check_device_deferred(void)
+{
+	int touchpad = get_hardware_id(ADC_TOUCHPAD_ID);
+	int audio = get_hardware_id(ADC_AUDIO_ID);
+	int product_id;
+
+	/* Clear the DIAGNOSTICS_HW_NO_BATTERY flag if battery is present */
+	if (battery_is_present() == BP_YES || get_standalone_mode())
+		set_diagnostic(DIAGNOSTICS_HW_NO_BATTERY, false);
+
+	if ((touchpad <= BOARD_VERSION_1 || touchpad >= BOARD_VERSION_14) &&
+		!get_standalone_mode())
+		set_diagnostic(DIAGNOSTICS_TOUCHPAD, true);
+
+	if ((audio <= BOARD_VERSION_1 || audio >= BOARD_VERSION_14) &&
+		!get_standalone_mode())
+		set_diagnostic(DIAGNOSTICS_AUDIO_DAUGHTERBOARD, true);
+
+	i2c_read8(I2C_PORT_SENSOR, F75303_I2C_ADDR_FLAGS_4D, F75303_PRODUCT_ID, &product_id);
+
+	if (product_id != F75303_ID)
+		set_diagnostic(DIAGNOSTICS_THERMAL_SENSOR, true);
+
+	if (!(fan_get_rpm_actual(0) > 100))
+		set_diagnostic(DIAGNOSTICS_NOFAN, true);
+
+	/* Exit the duty mode and let thermal to control the fan */
+	dptf_set_fan_duty_target(-1);
+
+	if (amd_ddr_initialized_check())
+		set_bios_diagnostic(CODE_DDR_FAIL);
+
+	set_device_complete(true);
+}
+DECLARE_DEFERRED(check_device_deferred);
+
+void project_diagnostics(void)
+{
+	hook_call_deferred(&start_fan_deferred_data, 500 * MSEC);
+	hook_call_deferred(&check_device_deferred_data, 2000 * MSEC);
+}
diff --git a/zephyr/program/framework/azalea/src/stt.c b/zephyr/program/framework/azalea/src/stt.c
new file mode 100644
index 0000000000..a120d8f3f5
--- /dev/null
+++ b/zephyr/program/framework/azalea/src/stt.c
@@ -0,0 +1,47 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Support code for STT temperature reporting */
+
+#include "chipset.h"
+#include "temp_sensor/f75303.h"
+#include "temp_sensor/pct2075.h"
+#include "temp_sensor/temp_sensor.h"
+
+#define NPCX_ESPI_VWEVSM_ADDR  ((volatile uint32_t *)0x4000a160)
+
+int board_get_soc_temp_mk(int *temp_mk)
+{
+	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	return f75303_get_val_mk(F75303_SENSOR_ID(DT_NODELABEL(cpu_f75303)),
+				 temp_mk);
+}
+
+int board_get_ambient_temp_mk(int *temp_mk)
+{
+	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	return f75303_get_val_mk(
+		F75303_SENSOR_ID(DT_NODELABEL(ddr_f75303)), temp_mk);
+}
+
+__override int chipset_in_low_power_mode(void)
+{
+	volatile uint32_t *address;
+	uint32_t val;
+	bool in_low_power_mode = false;
+
+	address = NPCX_ESPI_VWEVSM_ADDR;
+	/* Get Wire field */
+	val = *address & 0x0F;
+
+	if (val != 0)
+		in_low_power_mode = true;
+
+	return in_low_power_mode;
+}
diff --git a/zephyr/program/framework/include/azalea/keyboard_customization.h b/zephyr/program/framework/include/azalea/keyboard_customization.h
new file mode 100644
index 0000000000..6c088b90d6
--- /dev/null
+++ b/zephyr/program/framework/include/azalea/keyboard_customization.h
@@ -0,0 +1,101 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Keyboard configuration */
+
+#ifndef __KEYBOARD_CUSTOMIZATION_H
+#define __KEYBOARD_CUSTOMIZATION_H
+
+/*
+ * KEYBOARD_COLS_MAX has the build time column size. It's used to allocate
+ * exact spaces for arrays. Actual keyboard scanning is done using
+ * keyboard_cols, which holds a runtime column size.
+ */
+#define KEYBOARD_COLS_MAX 16
+#define KEYBOARD_ROWS 8
+
+/*
+ * WARNING: Do not directly modify it. You should call keyboard_raw_set_cols,
+ * instead. It checks whether you're eligible or not.
+ */
+extern uint8_t keyboard_cols;
+
+#define KEYBOARD_ROW_TO_MASK(r) (1 << (r))
+
+/* TODO FRAMEWORK - VERIFY THESE ARE CORRECT - they dont match our current layout. */
+
+/* Columns and masks for keys we particularly care about */
+#define KEYBOARD_COL_DOWN	11
+#define KEYBOARD_ROW_DOWN	6
+#define KEYBOARD_MASK_DOWN	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_DOWN)
+#define KEYBOARD_COL_ESC	1
+#define KEYBOARD_ROW_ESC	1
+#define KEYBOARD_MASK_ESC	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_ESC)
+#define KEYBOARD_COL_KEY_H	6
+#define KEYBOARD_ROW_KEY_H	1
+#define KEYBOARD_MASK_KEY_H	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_H)
+#define KEYBOARD_COL_KEY_R	3
+#define KEYBOARD_ROW_KEY_R	7
+#define KEYBOARD_MASK_KEY_R	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_R)
+#define KEYBOARD_COL_LEFT_ALT	10
+#define KEYBOARD_ROW_LEFT_ALT	6
+#define KEYBOARD_MASK_LEFT_ALT	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_ALT)
+#define KEYBOARD_COL_REFRESH	2
+#define KEYBOARD_ROW_REFRESH	2
+#define KEYBOARD_MASK_REFRESH	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_REFRESH)
+#define KEYBOARD_COL_RIGHT_ALT	10
+#define KEYBOARD_ROW_RIGHT_ALT	0
+#define KEYBOARD_MASK_RIGHT_ALT	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_ALT)
+#define KEYBOARD_DEFAULT_COL_VOL_UP	4
+#define KEYBOARD_DEFAULT_ROW_VOL_UP	0
+#define KEYBOARD_COL_LEFT_CTRL  0
+#define KEYBOARD_ROW_LEFT_CTRL  2
+#define KEYBOARD_MASK_LEFT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_CTRL)
+#define KEYBOARD_COL_RIGHT_CTRL 0
+#define KEYBOARD_ROW_RIGHT_CTRL 4
+#define KEYBOARD_MASK_RIGHT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_CTRL)
+#define KEYBOARD_COL_SEARCH     1
+#define KEYBOARD_ROW_SEARCH     0
+#define KEYBOARD_MASK_SEARCH    KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_SEARCH)
+#define KEYBOARD_COL_KEY_0      8
+#define KEYBOARD_ROW_KEY_0      6
+#define KEYBOARD_MASK_KEY_0     KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_0)
+#define KEYBOARD_COL_KEY_1      1
+#define KEYBOARD_ROW_KEY_1      6
+#define KEYBOARD_MASK_KEY_1     KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_1)
+#define KEYBOARD_COL_KEY_2      4
+#define KEYBOARD_ROW_KEY_2      6
+#define KEYBOARD_MASK_KEY_2     KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_2)
+#define KEYBOARD_COL_LEFT_SHIFT 7
+#define KEYBOARD_ROW_LEFT_SHIFT 5
+#define KEYBOARD_MASK_LEFT_SHIFT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_SHIFT)
+
+enum kb_fn_table {
+	KB_FN_F1 = BIT(0),
+	KB_FN_F2 = BIT(1),
+	KB_FN_F3 = BIT(2),
+	KB_FN_F4 = BIT(3),
+	KB_FN_F5 =  BIT(4),
+	KB_FN_F6 = BIT(5),
+	KB_FN_F7 = BIT(6),
+	KB_FN_F8 = BIT(7),
+	KB_FN_F9 = BIT(8),
+	KB_FN_F10 = BIT(9),
+	KB_FN_F11 = BIT(10),
+	KB_FN_F12 = BIT(11),
+	KB_FN_DELETE = BIT(12),
+	KB_FN_K = BIT(13),
+	KB_FN_S = BIT(14),
+	KB_FN_LEFT = BIT(15),
+	KB_FN_RIGHT = BIT(16),
+	KB_FN_UP = BIT(17),
+	KB_FN_DOWN = BIT(18),
+	KB_FN_ESC = BIT(19),
+	KB_FN_B = BIT(20),
+	KB_FN_P = BIT(21),
+	KB_FN_SPACE = BIT(22),
+};
+
+#endif /* __KEYBOARD_CUSTOMIZATION_H */
diff --git a/zephyr/program/framework/include/board_adc.h b/zephyr/program/framework/include/board_adc.h
new file mode 100644
index 0000000000..e115348c3e
--- /dev/null
+++ b/zephyr/program/framework/include/board_adc.h
@@ -0,0 +1,34 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __BOARD_ADC_H__
+#define __BOARD_ADC_H__
+
+#include "adc.h"
+
+enum board_version_t {
+	BOARD_VERSION_UNKNOWN = -1,
+	BOARD_VERSION_0,
+	BOARD_VERSION_1,
+	BOARD_VERSION_2,
+	BOARD_VERSION_3,
+	BOARD_VERSION_4,
+	BOARD_VERSION_5,
+	BOARD_VERSION_6,
+	BOARD_VERSION_7,
+	BOARD_VERSION_8,
+	BOARD_VERSION_9,
+	BOARD_VERSION_10,
+	BOARD_VERSION_11,
+	BOARD_VERSION_12,
+	BOARD_VERSION_13,
+	BOARD_VERSION_14,
+	BOARD_VERSION_15,
+	BOARD_VERSION_COUNT,
+};
+
+enum board_version_t get_hardware_id(enum adc_channel channel);
+
+#endif /* __BOARD_LED_H__ */
\ No newline at end of file
diff --git a/zephyr/program/framework/include/board_charger.h b/zephyr/program/framework/include/board_charger.h
new file mode 100644
index 0000000000..c3b7815fe3
--- /dev/null
+++ b/zephyr/program/framework/include/board_charger.h
@@ -0,0 +1,41 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_BOARD_CHARGER_H
+#define __CROS_EC_BOARD_CHARGER_H
+
+
+/* Customer charger defination */
+#define ISL9241_CONTROL1_IMON				BIT(5)
+#define ISL9241_CONTROL1_PROCHOT_REF_6000		(3 << 0)
+#define ISL9241_CONTROL1_PROCHOT_REF_6800               (7 << 0)
+
+#define ISL9241_CONTROL2_GENERAL_PURPOSE_COMPARATOR	BIT(3)
+#define ISL9241_CONTROL2_PROCHOT_DEBOUNCE_100		(1 << 9)
+
+#define ISL9241_CONTROL1_EXIT_LEARN_MODE		BIT(12)
+#define ISL9241_CONTROL3_BATGONE			BIT(4)
+
+#define ISL9241_CONTROL4_GP_COMPARATOR			BIT(12)
+#define ISL9241_CONTROL4_WOCP_FUNCTION			BIT(9)
+#define ISL9241_CONTROL4_VSYS_SHORT_CHECK		BIT(8)
+#define ISL9241_CONTROL4_ACOK_BATGONE_DEBOUNCE_25US	(1 << 2)
+
+#define ISL9241_CONTROL0_BGATE_FORCE_ON		BIT(10)
+
+enum ec_prochot_status {
+	EC_DEASSERTED_PROCHOT = 0,
+	EC_ASSERTED_PROCHOT = 1,
+};
+
+int update_charger_in_cutoff_mode(void);
+
+#ifdef CONFIG_BOARD_LOTUS
+int charger_in_bypass_mode(void);
+void board_charger_lpm_control(int enable);
+void board_disable_bypass_oneshot(void);
+#endif
+
+#endif	/* __CROS_EC_BOARD_CHARGER_H */
diff --git a/zephyr/program/framework/include/board_function.h b/zephyr/program/framework/include/board_function.h
new file mode 100644
index 0000000000..a8b4ba6a1c
--- /dev/null
+++ b/zephyr/program/framework/include/board_function.h
@@ -0,0 +1,29 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_BOARD_FUNCTION_H
+#define __CROS_EC_BOARD_FUNCTION_H
+
+enum function_type {
+	/* type for function switch */
+	TYPE_MEMMAP	= 0,
+	TYPE_BBRAM	= 1,
+	TYPE_FLASH	= 2,
+};
+
+/* set bios function bit to bbram when ACPI_DRIVER_READY */
+void bios_function_detect(void);
+
+/* return BIOS setup AC attach bit status */
+int ac_boot_status(void);
+
+/* for host cmd clear count */
+int chassis_cmd_clear(int type);
+
+__override_proto void project_chassis_function(enum gpio_signal signal);
+
+uint32_t get_system_percentage(void);
+
+#endif	/* __CROS_EC_BOARD_FUNCTION_H */
diff --git a/zephyr/program/framework/include/board_host_command.h b/zephyr/program/framework/include/board_host_command.h
new file mode 100644
index 0000000000..c77c341440
--- /dev/null
+++ b/zephyr/program/framework/include/board_host_command.h
@@ -0,0 +1,461 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __BOARD_HOST_COMMAND_H
+#define __BOARD_HOST_COMMAND_H
+
+#include "host_command.h"
+
+#define SCI_HOST_EVENT_MASK					\
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |		\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |		\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |	\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |	\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |	\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |	\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |	\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY)	|	\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |	\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT) |	\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_REBOOT) |	\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_UCSI) |		\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATT_BTP) |		\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_DGPU_TYPEC_NOTIFY) |	\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_STT_UPDATE))
+
+#define SCI_HOST_WAKE_EVENT_MASK			\
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |			\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |			\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)	|		\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |		\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |	\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY)	|	\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATT_BTP)	|			\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED))
+
+/*****************************************************************************/
+/*
+ * Configure the behavior of the flash notify
+ */
+#define EC_CMD_FLASH_NOTIFIED		0x3E01
+
+enum ec_flash_notified_flags {
+	/* Enable/Disable power button pulses for x86 devices */
+	FLASH_ACCESS_SPI	= 0,
+	FLASH_FIRMWARE_START	= 1,
+	FLASH_FIRMWARE_DONE	= 2,
+	FLASH_ACCESS_SPI_DONE	= 3,
+	FLASH_FLAG_PD		= BIT(4),
+};
+
+struct ec_params_flash_notified {
+	/* See enum ec_flash_notified_flags */
+	uint8_t flags;
+} __ec_align1;
+
+/*****************************************************************************/
+/*
+ * Factory will need change Fnkey and power button
+ * key scancode to test keyboard.
+ */
+#define EC_CMD_FACTORY_MODE	0x3E02
+#define RESET_FOR_SHIP 0x5A
+
+struct ec_params_factory_notified {
+	/* factory mode enable */
+	uint8_t flags;
+} __ec_align1;
+
+/*****************************************************************************/
+/*
+ * Configure the behavior of the charge limit control.
+ */
+#define EC_CMD_CHARGE_LIMIT_CONTROL	0x3E03
+#define EC_CHARGE_LIMIT_RESTORE		0x7F
+
+enum ec_chg_limit_control_modes {
+	/* Disable all setting, charge control by charge_manage */
+	CHG_LIMIT_DISABLE	= BIT(0),
+	/* Set maximum and minimum percentage */
+	CHG_LIMIT_SET_LIMIT	= BIT(1),
+	/* Host read current setting */
+	CHG_LIMIT_GET_LIMIT	= BIT(3),
+	/* Enable override mode, allow charge to full this time */
+	CHG_LIMIT_OVERRIDE	= BIT(7),
+};
+
+struct ec_params_ec_chg_limit_control {
+	/* See enum ec_chg_limit_control_modes */
+	uint8_t modes;
+	uint8_t max_percentage;
+	uint8_t min_percentage;
+} __ec_align1;
+
+struct ec_response_chg_limit_control {
+	uint8_t max_percentage;
+	uint8_t min_percentage;
+} __ec_align1;
+
+/*****************************************************************************/
+/*
+ * Configure the behavior of the charge limit control.
+ */
+
+#define EC_CMD_PWM_GET_FAN_ACTUAL_RPM	0x3E04
+
+struct ec_params_ec_pwm_get_actual_fan_rpm {
+	/* The index of the fan */
+	uint8_t index;
+} __ec_align1;
+
+struct ec_response_pwm_get_actual_fan_rpm {
+	uint16_t rpm;
+} __ec_align2;
+
+
+/*****************************************************************************/
+/*
+ * This command uses to notify the EC needs to keep the pch power in s5.
+ */
+#define EC_CMD_SET_AP_REBOOT_DELAY	0x3E05
+
+struct ec_response_ap_reboot_delay {
+	uint8_t delay;
+} __ec_align1;
+
+/*****************************************************************************/
+/*
+ * This command uses to notify the EC that the system is in non-ACPI mode.
+ */
+#define EC_CMD_NON_ACPI_NOTIFY		0x3E07
+
+/*****************************************************************************/
+/*
+ * This command uses for BIOS check Chassis.
+ */
+#define EC_CMD_CHASSIS_INTRUSION 0x3E09
+#define EC_PARAM_CHASSIS_INTRUSION_MAGIC 0xCE
+#define EC_PARAM_CHASSIS_BBRAM_MAGIC 0xEC
+
+struct ec_params_chassis_intrusion_control {
+	uint8_t clear_magic;
+	uint8_t clear_chassis_status;
+} __ec_align1;
+
+struct ec_response_chassis_intrusion_control {
+	uint8_t chassis_ever_opened;	/* bios used */
+	uint8_t coin_batt_ever_remove;	/* factory used */
+	uint8_t total_open_count;	/* reserved */
+	uint8_t vtr_open_count;		/* reserved */
+} __ec_align1;
+
+/*****************************************************************************/
+/*
+ * This command uses for BIOS boot check.
+ */
+#define EC_CMD_DIAGNOSIS 0x3E0B
+
+enum ec_params_diagnosis_code {
+	/* type: DDR */
+	CODE_DDR_TRAINING_START	= 1,
+	CODE_DDR_TRAINING_FINISH = 2,
+	CODE_DDR_FAIL = 3,
+	CODE_NO_EDP = 4,
+	CODE_PORT80_COMPLETE = 0xFF,
+};
+
+struct ec_params_diagnosis {
+	/* See enum ec_params_diagnosis_code */
+	uint8_t diagnosis_code;
+} __ec_align1;
+
+/*****************************************************************************/
+/*
+ * This command uses to Swap Control Fn key for the system BIOS menu option.
+ */
+#define EC_CMD_UPDATE_KEYBOARD_MATRIX 0x3E0C
+struct keyboard_matrix_map {
+	uint8_t row;
+	uint8_t col;
+	uint16_t scanset;
+} __ec_align1;
+struct ec_params_update_keyboard_matrix {
+	uint32_t num_items;
+	uint32_t write;
+	struct keyboard_matrix_map scan_update[32];
+} __ec_align1;
+
+
+/*****************************************************************************/
+/*
+ * This command uses to change the fingerprint LED level.
+ */
+#define EC_CMD_FP_LED_LEVEL_CONTROL	0x3E0E
+
+struct ec_params_fp_led_control {
+	uint8_t set_led_level;
+	uint8_t get_led_level;
+} __ec_align1;
+
+struct ec_response_fp_led_level {
+	uint8_t level;
+} __ec_align1;
+
+/*****************************************************************************/
+/*
+ * This command return the chassis status
+ */
+#define EC_CMD_CHASSIS_OPEN_CHECK	0x3E0F
+
+struct ec_response_chassis_open_check {
+	uint8_t status;
+} __ec_align1;
+
+/*****************************************************************************/
+/*
+ * This command uses to notify the EC that the system is in ACPI mode.
+ */
+#define EC_CMD_ACPI_NOTIFY		0x3E10
+
+/*****************************************************************************/
+/*
+ * This command returns the PD chip version.
+ */
+#define EC_CMD_READ_PD_VERSION		0x3E11
+
+struct ec_response_read_pd_version {
+	uint8_t pd0_version[8];
+	uint8_t pd1_version[8];
+} __ec_align1;
+
+/*****************************************************************************/
+/*
+ * This command uses to control the standalone mode enable/disable
+ */
+#define EC_CMD_STANDALONE_MODE 0x3E13
+
+struct ec_params_standalone_mode {
+	uint8_t enable;
+} __ec_align1;
+
+/*****************************************************************************/
+/*
+ * This command returns the current state of the camera and microphone privacy switches
+ */
+#define EC_CMD_PRIVACY_SWITCHES_CHECK_MODE 0x3E14
+
+struct ec_response_privacy_switches_check {
+	uint8_t microphone;
+	uint8_t camera;
+} __ec_align1;
+
+/*****************************************************************************/
+/*
+ * This command returns how many times did chassis(sw3) pressed
+ */
+#define EC_CMD_CHASSIS_COUNTER 0x3E15
+
+struct ec_response_chassis_counter {
+	uint8_t press_counter;
+} __ec_align1;
+
+/*****************************************************************************/
+/*
+ * This command returns the input deck state and board id.
+ */
+#define EC_CMD_CHECK_DECK_STATE		0x3E16
+
+struct ec_params_deck_state {
+	uint8_t mode;
+} __ec_align1;
+
+struct ec_response_deck_state {
+	uint8_t input_deck_board_id[8];
+	uint8_t deck_state;
+} __ec_align1;
+
+/*****************************************************************************/
+/*
+ * This command returns the simple ec version.
+ */
+#define EC_CMD_GET_SIMPLE_VERSION	0x3E17
+
+struct ec_response_get_custom_version {
+	char simple_version[9];
+} __ec_align4;
+
+/*****************************************************************************/
+/*
+ * This command returns the active charge pd chip.
+ */
+#define EC_CMD_GET_ACTIVE_CHARGE_PD_CHIP	0x3E18
+
+struct ec_response_get_active_charge_pd_chip {
+	uint8_t pd_chip;
+} __ec_align1;
+
+/*****************************************************************************/
+/*
+ * Enable/disable UEFI App mode
+ *
+ * Enable disables the power button functionality and allows to read it via
+ * EC_CMD_UEFI_APP_BTN_STATUS host command instead.
+ * This makes it possible to use it as a software button in a UEFI app.
+ */
+#define EC_CMD_UEFI_APP_MODE	0x3E19
+
+struct ec_params_uefi_app_mode {
+	/* 0x01 to enable, 0x00 to disable UEFI App mode */
+	uint8_t flags;
+} __ec_align1;
+
+/*****************************************************************************/
+/*
+ * Read power button status
+ */
+#define EC_CMD_UEFI_APP_BTN_STATUS	0x3E1A
+
+struct ec_response_uefi_app_btn_status {
+	/* 0x00 if not pressed, 0x01 if pressed */
+	uint8_t status;
+} __ec_align1;
+
+/*****************************************************************************/
+/*
+ * Check state of the Expansion Bay
+ */
+#define EC_CMD_EXPANSION_BAY_STATUS	0x3E1B
+
+enum ec_expansion_bay_states {
+	/* Valid module present and switch closed */
+	MODULE_ENABLED	= BIT(0),
+	/* Board ID invalid */
+	MODULE_FAULT	= BIT(1),
+	/* Hatch switch open/closed status */
+	HATCH_SWITCH_CLOSED	= BIT(2),
+};
+
+struct ec_response_expansion_bay_status {
+	/* Check ec_expansion_bay_states */
+	uint8_t state;
+	uint8_t board_id_0;
+	uint8_t board_id_1;
+} __ec_align1;
+
+/*****************************************************************************/
+/*
+ * Get hardware diagnostics
+ */
+#define EC_CMD_GET_HW_DIAG 0x3E1C
+
+/* See enum diagnostics_device_idx */
+struct ec_response_get_hw_diag {
+	uint32_t hw_diagnostics;
+	uint8_t bios_complete;
+	uint8_t device_complete;
+} __ec_align1;
+
+/*****************************************************************************/
+/*
+ * This command returns the serial of the GPU module
+ * set params idx to the serial offset you want to query.
+ * if idx == 0, this will query the header serial number.
+ */
+#define EC_CMD_GET_GPU_SERIAL	0x3E1D
+
+struct ec_params_gpu_serial {
+	uint8_t idx;
+} __ec_align1;
+struct ec_response_get_gpu_serial {
+	uint8_t idx;
+	uint8_t valid;
+	char serial[20];
+} __ec_align1;
+
+/*****************************************************************************/
+/*
+ * This command returns the PCIE configuration of the GPU module
+ *   PCIE_8X1 = 0,
+ *   PCIE_4X1 = 1,
+ *   PCIE_4X2 = 2,
+ *   it will also return the GPU vendor type
+ *   GPU_AMD_R23M = 0,
+ *   GPU_PCIE_ACCESSORY = 0xFF
+ */
+#define EC_CMD_GET_GPU_PCIE	0x3E1E
+
+struct ec_response_get_gpu_config {
+	uint8_t gpu_pcie_config;
+	uint8_t gpu_vendor;
+} __ec_align1;
+
+/*****************************************************************************/
+/*
+ * This command programs the GPU serial
+ * set magic = 0x0D for GPU structure
+ * set magic = 0x55 for SSD structure
+ * currently only idx = 0 is supported to program the header serial number.
+ */
+#define EC_CMD_PROGRAM_GPU_EEPROM	0x3E1F
+
+struct ec_params_program_gpu_serial {
+	uint8_t magic;
+	uint8_t idx;
+	char serial[20];
+} __ec_align1;
+struct ec_response_program_gpu_serial {
+	uint8_t valid;
+} __ec_align1;
+
+/*****************************************************************************/
+/*
+ * Used the host command to control the fingerprint power
+ */
+#define EC_CMD_FP_CONTROL	0x3E20
+
+struct ec_params_fingerprint_control {
+	/* 0x01 to enable, 0x00 to disable fingerprint power */
+	uint8_t enable;
+} __ec_align1;
+
+/*****************************************************************************/
+/*
+ * Get cutoff status
+ */
+#define EC_CMD_GET_CUTOFF_STATUS 0x3E21
+
+struct ec_response_get_cutoff_status {
+	uint8_t status;
+} __ec_align1;
+
+/*****************************************************************************/
+/*
+ * Battery extender control
+ */
+#define EC_CMD_BATTERY_EXTENDER	0x3E24
+
+struct ec_params_battery_extender {
+	uint8_t disable;
+	uint8_t trigger_days;
+	uint16_t reset_minutes;
+	uint8_t cmd;
+	uint8_t manual;
+} __ec_align1;
+
+struct ec_response_battery_extender {
+	uint8_t current_stage;
+	uint16_t trigger_days;
+	uint16_t reset_minutes;
+	uint8_t disable;
+	uint64_t trigger_timedelta;
+	uint64_t reset_timedelta;
+} __ec_align1;
+
+enum battery_extender_cmd {
+	BATT_EXTENDER_WRITE_CMD,
+	BATT_EXTENDER_READ_CMD,
+};
+
+#endif /* __BOARD_HOST_COMMAND_H */
diff --git a/zephyr/program/framework/include/common_cpu_power.h b/zephyr/program/framework/include/common_cpu_power.h
new file mode 100644
index 0000000000..3c851b807e
--- /dev/null
+++ b/zephyr/program/framework/include/common_cpu_power.h
@@ -0,0 +1,81 @@
+/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * PECI based cpu power governer
+ */
+
+#ifndef __CROS_EC_CPU_POWER_H
+#define __CROS_EC_CPU_POWER_H
+
+#define SB_RMI_WRITE_SUSTAINED_POWER_LIMIT_CMD  0x30
+#define SB_RMI_WRITE_FAST_PPT_LIMIT_CMD 0x31
+#define SB_RMI_WRITE_SLOW_PPT_LIMIT_CMD 0x32
+#define SB_RMI_WRITE_SLOW_PPT_LIMIT_CMD 0x32
+#define SB_RMI_WRITE_APU_ONLY_SPPT_CMD 0x3B
+#define SB_RMI_WRITE_P3T_LIMIT_CMD 0x3C
+
+enum power_limit_type {
+	TYPE_SPL = 0,
+	TYPE_SPPT,
+	TYPE_FPPT,
+	TYPE_P3T,
+#ifdef CONFIG_BOARD_LOTUS
+	TYPE_APU_ONLY_SPPT,
+#endif
+	TYPE_COUNT,
+};
+
+enum power_limit_function {
+	FUNCTION_DEFAULT = 0,
+	FUNCTION_SLIDER = 0,
+	FUNCTION_THERMAL_PMF,
+	FUNCTION_SAFETY,
+	FUNCTION_POWER,
+	FUNCTION_THERMAL,
+	FUNCTION_COUNT,
+};
+
+enum power_safety_level {
+	LEVEL_NORMAL = 0,
+	LEVEL_STOP_CHARGE,
+	LEVEL_TUNE_PLS,
+	LEVEL_DISABLE_GPU,
+	LEVEL_PROCHOT,
+	LEVEL_TYPEC_1_5A,
+	LEVEL_COUNT,
+};
+
+struct power_limit_details {
+	int mwatt[TYPE_COUNT];
+} __ec_align1;
+
+#define BATTERY_55mW 55000
+#define BATTERY_61mW 61000
+/* ROP: rest of platform */
+#define POWER_ROP 20000
+#define POWER_PORT_COST 5000
+
+extern struct power_limit_details power_limit[FUNCTION_COUNT];
+extern int target_func[TYPE_COUNT];
+extern bool manual_ctl;
+extern bool safety_pwr_logging;
+extern int mode_ctl;
+extern uint8_t func_ctl;
+extern int my_test_current;
+
+void update_apu_ready(int status);
+int get_apu_ready(void);
+
+void update_soc_power_limit(bool force_update, bool force_no_adapter);
+int set_pl_limits(uint32_t spl, uint32_t fppt, uint32_t sppt, uint32_t p3t);
+
+#ifdef CONFIG_BOARD_LOTUS
+int update_apu_only_sppt_limit(uint32_t mwatt);
+void update_pmf_events(uint8_t pd_event, int enable);
+#endif
+
+extern bool thermal_warn_trigger(void);
+extern int cypd_get_ac_power(void);
+
+#endif	/* __CROS_EC_CPU_POWER_H */
diff --git a/zephyr/program/framework/include/customized_shared_memory.h b/zephyr/program/framework/include/customized_shared_memory.h
new file mode 100644
index 0000000000..290632083f
--- /dev/null
+++ b/zephyr/program/framework/include/customized_shared_memory.h
@@ -0,0 +1,115 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __BOARD_CUSTOMIZED_SHARED_MEMORY_H
+#define __BOARD_CUSTOMIZED_SHARED_MEMORY_H
+
+/* Customized memmap start at offset 0xF00 */
+#define EC_CUSTOMIZED_MEMMAP_SYSTEM_FLAGS	0x100
+
+#define ACPI_DRIVER_READY   BIT(0)
+#define PBTN_OVERRRIDE      BIT(1)
+#define UCSI_EVENT          BIT(2)
+
+#define EC_CUSTOMIZED_MEMMAP_POWER_STATE	0x101
+
+#define EC_PS_ENTER_S3			BIT(0)
+#define EC_PS_RESUME_S3			BIT(1)
+#define EC_PS_ENTER_S4			BIT(2)
+#define EC_PS_RESUME_S4			BIT(3)
+#define EC_PS_ENTER_S5			BIT(4)
+#define EC_PS_RESUME_S5			BIT(5)
+#define EC_PS_ENTER_S0ix		BIT(6)
+#define EC_PS_RESUME_S0ix		BIT(7)
+
+#define EC_CUSTOMIZED_MEMMAP_WAKE_EVENT		0x102
+/*
+ * define wake source for keep PCH power
+ * BIT0 for RTCwake
+ * BIT1 for USBwake
+ */
+#define RTCWAKE  BIT(0)
+#define USBWAKE  BIT(1)
+#define JSSD2_POWER_OFF		BIT(2)
+#define EXT_SSD1_POWER_OFF	BIT(3)
+#define EXT_SSD2_POWER_OFF	BIT(4)
+#define JSSD2_POWER_ON		BIT(5)
+#define EXT_SSD1_POWER_ON	BIT(6)
+#define EXT_SSD2_POWER_ON	BIT(7)
+
+/* Battery */
+#define EC_CUSTOMIZED_MEMMAP_BATT_AVER_TEMP	0x103
+#define EC_CUSTOMIZED_MEMMAP_BATT_CHARGE_CURR	0x104 /* Reserved */
+#define EC_CUSTOMIZED_MEMMAP_BATT_PERCENTAGE	0x106
+#define EC_CUSTOMIZED_MEMMAP_BATT_STATUS	0x107
+#define EC_CUSTOMIZED_MEMMAP_BATT_TRIP_POINT	0x108
+#define EC_CUSTOMIZED_MEMMAP_BATT_MANUF_DAY	0x144 /* Manufacturer date - day */
+#define EC_CUSTOMIZED_MEMMAP_BATT_MANUF_MONTH	0x145 /* Manufacturer date - month */
+#define EC_CUSTOMIZED_MEMMAP_BATT_MANUF_YEAR	0x146 /* Manufacturer date - year */
+
+#define EC_BATT_FLAG_FULL			BIT(0) /* Full Charged */
+#define EC_BATT_TYPE				BIT(1) /* (0: NiMh,1: LION) */
+#define EC_BATT_MODE				BIT(2) /* (0=mW, 1=mA) */
+
+#define EC_CUSTOMIZED_MEMMAP_DPTF_EVENT		0x110 /* Reserved */
+#define EC_CUSTOMIZED_MEMMAP_PROJECTID		0x111 /* Reserved */
+
+/* UCSI */
+#define EC_CUSTOMIZED_MEMMAP_UCSI_VERSION	0x112
+#define EC_CUSTOMIZED_MEMMAP_UCSI_CONN_CHANGE	0x114
+#define EC_CUSTOMIZED_MEMMAP_UCSI_DATA_LEN	0x115
+#define EC_CUSTOMIZED_MEMMAP_UCSI_RESERVE	0x116
+#define EC_CUSTOMIZED_MEMMAP_UCSI_CCI		0x117
+#define EC_CUSTOMIZED_MEMMAP_UCSI_COMMAND	0x118
+#define EC_CUSTOMIZED_MEMMAP_UCSI_CTR_DATA_LEN	0x119
+#define EC_CUSTOMIZED_MEMMAP_UCSI_CTR_SPECIFIC	0x11A
+#define EC_CUSTOMIZED_MEMMAP_UCSI_MESSAGE_IN	0x120
+#define EC_CUSTOMIZED_MEMMAP_UCSI_MESSAGE_OUT	0x130
+
+
+#define EC_CUSTOMIZED_MEMMAP_SERIAL_STRCUT_INFO	0x140
+#define EC_CUSTOMIZED_MEMMAP_BIOS_SETUP_FUNC	0x148
+#define EC_AC_ATTACH_BOOT                   BIT(0)
+#define EC_SECURITY_INTRUDER_DETECT         BIT(1)
+
+#define EC_CUSTOMIZED_MEMMAP_PD_VERSION		0x14C
+
+#define EC_CUSTOMIZED_MEMMAP_GPU_CONTROL        0x150
+#define SET_APU_MUX     BIT(0)
+#define SET_GPU_MUX     BIT(1)
+#define GPU_MUX         BIT(2) /* 0:APU; 1:GPU*/
+#define GPU_PRESENT     BIT(3) /* 0:gpu no exist; 1:gpu exist*/
+#define ASSERTED_EDP_RESET      BIT(4)
+#define DEASSERTED_EDP_RESET    BIT(5)
+#define GPU_EDP_MASK			(BIT(4) + BIT(5))
+#define GPU_PCIE_MASK			(BIT(6) + BIT(7))
+#define GPU_PCIE_8X1			(0)
+#define GPU_PCIE_4X2			(BIT(6))
+#define GPU_PCIE_RESERVED		(BIT(7))
+#define GPU_PCIE_DIS			(BIT(6) + BIT(7))
+
+
+#define EC_MEMMAP_POWER_SLIDE               0x151
+enum power_slide_mode {
+	EC_DC_BEST_PERFORMANCE = 1,
+	EC_DC_BALANCED = 2,
+	EC_DC_BEST_EFFICIENCY = 4,
+	EC_DC_BATTERY_SAVER = 8,
+	EC_AC_BEST_PERFORMANCE = 16,
+	EC_AC_BALANCED = 32,
+	EC_AC_BEST_EFFICIENCY = 64,
+};
+
+#define EC_CUSTOMIZED_MEMMAP_DISPLAY_ON		0x153
+
+/* 1~14 indicate #1 to #14 stt table */
+#define EC_MEMMAP_STT_TABLE_NUMBER	0x154
+
+#define EC_CUSTOMIZED_MEMMAP_POWER_LIMIT_EVENT	0x155
+#define CPB_DISABLE	BIT(0) /* 0: enable; 1: disable */
+
+#define EC_CUSTOMIZED_MEMMAP_GPU_TYPE	0x157
+
+#endif /* __BOARD_CUSTOMIZED_SHARED_MEMORY_H */
diff --git a/zephyr/program/framework/include/cypress_pd_common.h b/zephyr/program/framework/include/cypress_pd_common.h
new file mode 100644
index 0000000000..bd7d26e557
--- /dev/null
+++ b/zephyr/program/framework/include/cypress_pd_common.h
@@ -0,0 +1,582 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Cypress PD chip's driver
+ */
+
+#ifndef __CROS_EC_CYPRESS_PD_COMMON_H
+#define __CROS_EC_CYPRESS_PD_COMMON_H
+
+#include "usb_pd.h"
+
+/* 7 bit address  */
+#define CCG_I2C_CHIP0	0x42
+#define CCG_I2C_CHIP1	0x40
+
+#define BB_PWR_DOWN_TIMEOUT (4000*MSEC)
+
+/*
+ * commands
+ */
+#define CCG_RESET_CMD		0x0152 /* Byte[0]:'R', Byte[1]:0x01 */
+#define CCG_RESET_CMD_I2C	0x0052 /* Byte[0]:'R', Byte[1]:0x00 */
+
+/************************************************/
+/*    CCG DEVICE REGISTER ADDRESS DEFINITION    */
+/************************************************/
+#define CCG_DEVICE_MODE			0x0000
+#define CCG_BOOT_MODE_REASON		0x0001
+#define CCG_SILICON_ID			0x0002
+#define CCG_INTR_REG			0x0006
+#define CCG_RESET_REG			0x0008
+#define CCG_READ_ALL_VERSION_REG	0x0010
+#define CCG_FW2_VERSION_REG		0x0020
+#define CCG_PDPORT_ENABLE_REG		0x002C
+#define CCG_POWER_STAT			0x002E
+#define CCG_BATTERY_STAT		0x0031
+
+#define CCG_UCSI_STATUS_REG		0x0038
+#define CCG_UCSI_CONTROL_REG		0x0039
+#define CCG_SYS_PWR_STATE		0x003B
+/* CYPRESS vender add cmd, not common */
+#define CCG_CUST_C_CTRL_CONTROL_REG	0x003B
+#define CCG_HPI_VERSION			0x003C
+/*User registers from 0x40 to 0x48 are used for BB retimer */
+#define CCG_DPM_CMD_REG			0x0040
+#define CCG_MUX_CFG_REG			0x0041
+#define CCG_DEINIT_PORT_REG		0x0042
+#define CCG_ICL_STS_REG			0x0042
+#define CCG_ICL_BB_RETIMER_CMD_REG	0x0046
+#define CCG_ICL_BB_RETIMER_DAT_REG	0x0048
+#define CCG_USER_MAINBOARD_VERSION	0x004F
+#define CCG_USER_BB_POWER_EVT		0x004E
+#define CCG_USER_DISABLE_LOCKOUT	0x004D
+
+#define CCG_RESPONSE_REG		0x007E
+#define CCG_DATA_MEM_REG		0x1404
+#define CCG_VERSION_REG			0xF000
+#define CCG_CCI_REG			0xF004
+#define CCG_CONTROL_REG			0xF008
+#define CCG_MESSAGE_IN_REG		0xF010
+#define CCG_MESSAGE_OUT_REG		0xF020
+
+
+/************************************************/
+/*    CCG PORT REGISTER ADDRESS DEFINITION      */
+/************************************************/
+#define CCG_DM_CONTROL_REG(x) \
+	(0x1000 + ((x) * 0x1000))
+#define CCG_SELECT_SOURCE_PDO_MASK_REG(x) \
+	(0x1002 + ((x) * 0x1000))
+#define CCG_SELECT_SOURCE_PDO_REG(x) \
+	(0x1004 + ((x) * 0x1000))
+#define CCG_SELECT_SINK_PDO_REG(x) \
+	(0x1005 + ((x) * 0x1000))
+#define CCG_PD_CONTROL_REG(x) \
+	(0x1006 + ((x) * 0x1000))
+#define CCG_PD_STATUS_REG(x) \
+	(0x1008 + ((x) * 0x1000))
+#define CCG_TYPE_C_STATUS_REG(x) \
+	(0x100C + ((x) * 0x1000))
+#define CCG_TYPE_C_VOLTAGE_REG(x) \
+	(0x100D + ((x) * 0x1000))
+#define CCG_CURRENT_PDO_REG(x) \
+	(0x1010 + ((x) * 0x1000))
+#define CCG_CURRENT_RDO_REG(x) \
+	(0x1014 + ((x) * 0x1000))
+#define CCG_EVENT_MASK_REG(x) \
+	(0x1024 + ((x) * 0x1000))
+#define CCG_VDM_EC_CONTROL_REG(x) \
+	(0x102A + ((x) * 0x1000))
+#define CCG_DP_ALT_MODE_CONFIG_REG(x) \
+	(0x102B + ((x) * 0x1000))
+#define CCG_PORT_VBUS_FET_CONTROL(x) \
+	(0x1032 + ((x) * 0x1000))
+#define CCG_PORT_INTR_STATUS_REG(x) \
+	(0x1034 + ((x) * 0x1000))
+#define CCG_PORT_CURRENT_REG(x) \
+	(0x1058 + ((x) * 0x1000))
+#define CCG_PORT_HOST_CAP_REG(x) \
+	(0x105C + ((x) * 0x1000))
+#define CCG_ALT_MODE_MASK_REG(x) \
+	(0x1060 + ((x) * 0x1000))
+#define SELECT_SINK_PDO_EPR_MASK(x) \
+	(0x1065 + ((x) * 0x1000))
+#define CCG_SINK_PPS_AVS_CTRL_REG(x) \
+	(0x1066 + ((x) * 0x1000))
+#define CCG_PORT_PD_RESPONSE_REG(x) \
+	(0x1400 + ((x) * 0x1000))
+#define CCG_READ_DATA_MEMORY_REG(x, offset) \
+	((0x1404 + (offset)) + ((x) * 0x1000))
+#define CCG_WRITE_DATA_MEMORY_REG(x, offset) \
+	((0x1800 + (offset)) + ((x) * 0x1000))
+
+
+/************************************************/
+/*          DEVICE MODE DEFINITION              */
+/************************************************/
+#define CCG_BOOT_MODE	0x00
+#define CCG_FW1_MODE	0x01
+#define CCG_FW2_MODE	0x02
+
+/************************************************/
+/*          DEVICE INTERRUPT DEFINITION         */
+/************************************************/
+#define CCG_DEV_INTR	0x01
+#define CCG_PORT0_INTR	0x02
+#define CCG_PORT1_INTR	0x04
+#define CCG_ICLR_INTR	0x08
+#define CCG_UCSI_INTR	0x80
+
+/************************************************/
+/*          PORT INTERRUPT DEFINITION           */
+/************************************************/
+#define CCG_STATUS_TYPEC_ATTACH		0x00000001 /*bit 0 */
+#define CCG_STATUS_TYPEC_DETACH		0x00000002 /*bit 1 */
+#define CCG_STATUS_CONTRACT_DONE	0x00000004 /*bit 2 */
+#define CCG_STATUS_PRSWAP_DONE		0x00000008 /*bit 3 */
+#define CCG_STATUS_DRSWAP_DONE		0x00000010 /*bit 4 */
+#define CCG_STATUS_VCONNSWAP_DONE	0x00000020 /*bit 5 */
+#define CCG_STATUS_RESPONSE_READY	0x00200000 /*bit 21*/
+#define CCG_STATUS_OVP_EVT		0x40000000 /*bit 30*/
+
+/************************************************/
+/*          PD PORT DEFINITION                  */
+/************************************************/
+#define CCG_PDPORT_DISABLE	0x00
+#define CCG_PDPORT_ENABLE	0x01
+
+/************************************************/
+/*          POWER STATE DEFINITION              */
+/************************************************/
+#define CCG_POWERSTATE_S0	0x00
+#define CCG_POWERSTATE_S3	0x01
+#define CCG_POWERSTATE_S4	0x02
+#define CCG_POWERSTATE_S5	0x03
+#define CCG_POWERSTATE_S0ix	0x04
+#define CCG_POWERSTATE_G3	0x05
+
+/************************************************/
+/*  CCG_CUST_C_CTRL_CONTROL_REG DEFINITION      */
+/************************************************/
+#define CCG_P0P1_CONTROL_BY_CY		0xA0
+#define CCG_P0_OFF_P1_CY		0xA1
+#define CCG_P0_CY_P1_OFF		0xA2
+#define CCG_P0P1_TURN_OFF_C_CTRL	0xA3
+
+/************************************************/
+/*  DM CONTROL DEFINATION                       */
+/************************************************/
+#define CCG_DM_CTRL_SOP			0x00
+#define CCG_DM_CTRL_SPO_PRIM		0x01
+#define CCG_DM_CTRL_SPO_PRIM_PRIM	0x02
+
+#define CCG_DM_CTRL_PD3_DATA_REQUEST			BIT(2)
+#define CCG_DM_CTRL_EXTENDED_DATA_REQUEST		BIT(3)
+#define CCG_DM_CTRL_SENDER_RESPONSE_TIMER_DISABLE	BIT(4)
+
+#define CCG_EXTEND_MSG_CTRL_EN	BIT(1)
+
+/*
+ * Retimer control register commands
+ */
+#define RT_EVT_VSYS_REMOVED	0
+#define RT_EVT_VSYS_ADDED	1
+#define RT_EVT_RETRY_STATUS	2
+#define RT_EVT_UPDATE_STATUS	3
+
+
+/************************************************/
+/*  EPR EVENT Response                          */
+/************************************************/
+#define EPR_EVENT_TYPE_MASK 0x7F
+#define EPR_EVENT_POWER_ROLE_MASK 0x80
+#define EPR_EVENT_POWER_ROLE_SINK 0x80
+
+/************************************************/
+/*  VBUS CONSUMER FET CONTROL                   */
+/************************************************/
+#define CCG_EC_VBUS_CTRL_EN BIT(0)
+#define CCG_EC_VBUS_CTRL_ON BIT(1)
+
+/************************************************/
+/*  HELPER FUNCTIONS                            */
+/************************************************/
+#define PORT_TO_CONTROLLER(x) ((x) >> 1)
+#define PORT_TO_CONTROLLER_PORT(x) ((x) & 0x01)
+
+enum epr_event_type {
+	EPR_MODE_ENTERED = 1,
+	EPR_MODE_EXITED,
+	EPR_MODE_ENTER_FAILED,
+};
+
+enum epr_event_failure_type {
+	EPR_FAILURE_UNKNOWN,
+	EPR_FAILURE_EPR_CABLE,
+	EPR_FAILURE_EPR_VCONN,
+	EPR_FAILURE_RDO,
+	EPR_FAILURE_UNABLE_NOW,
+	EPR_FAILURE_PDO
+};
+
+/************************************************/
+/*  CCG Task Events                            */
+/************************************************/
+enum pd_task_evt {
+	CCG_EVT_INT_CTRL_0 = BIT(0),
+	CCG_EVT_INT_CTRL_1 = BIT(1),
+	CCG_EVT_STATE_CTRL_0 = BIT(2),
+	CCG_EVT_STATE_CTRL_1 = BIT(3),
+	CCG_EVT_AC_PRESENT =  BIT(4),
+	CCG_EVT_S_CHANGE = BIT(5),
+	CCG_EVT_PLT_RESET = BIT(6),
+	CCG_EVT_UCSI_POLL_CTRL_0 = BIT(7),
+	CCG_EVT_UCSI_POLL_CTRL_1 = BIT(8),
+	CCG_EVT_RETIMER_PWR = BIT(9),
+	CCG_EVT_UPDATE_PWRSTAT = BIT(10),
+	CCG_EVT_PORT_ENABLE = BIT(11),
+	CCG_EVT_PORT_DISABLE = BIT(12),
+	CCG_EVT_UCSI_PPM_RESET = BIT(13),
+	CCG_EVT_CFET_VBUS_OFF = BIT(14),
+	CCG_EVT_CFET_VBUS_ON = BIT(15),
+	CCG_EVT_DPALT_DISABLE = BIT(16),
+	CCG_EVT_PDO_INIT_0 = BIT(17),
+	CCG_EVT_PDO_INIT_1 = BIT(18),
+	CCG_EVT_PDO_C0P0 = BIT(19),
+	CCG_EVT_PDO_C0P1 = BIT(20),
+	CCG_EVT_PDO_C1P0 = BIT(21),
+	CCG_EVT_PDO_C1P1 = BIT(22),
+	CCG_EVT_PDO_RESET = BIT(23),
+};
+
+/************************************************
+ *	PD COMMAND DEFINITION
+ * See 001-97863_0N_V.pdf from cypress for the HPI
+ * Definition. Specifically Pages around 102
+ * Chapter 4.3.3.6 PD_CONTROL register
+ ************************************************/
+enum ccg_pd_command {
+	CCG_PD_CMD_SET_TYPEC_DEFAULT = 0x00,
+	CCG_PD_CMD_SET_TYPEC_1_5A,
+	CCG_PD_CMD_SET_TYPEC_3A,
+	CCG_PD_CMD_TRG_DATA_ROLE_SWAP = 0x05,
+	CCG_PD_CMD_TRG_POWER_ROLE_SWAP = 0x06,
+	CCG_PD_CMD_VCONN_EN = 0x07,
+	CCG_PD_CMD_VCONN_DIS = 0x08,
+	CCG_PD_CMD_TRG_VCONN_SWAP = 0x09,
+	CCG_PD_CMD_HARD_RESET = 0x0D,
+	CCG_PD_CMD_SOFT_RESET = 0x0E,
+	CCG_PD_CMD_CABLE_RESET = 0x0F,
+	CCG_PD_CMD_EC_INIT_COMPLETE = 0x10,
+	CCG_PD_CMD_PORT_DISABLE = 0x11,
+	CCG_PD_CMD_CHANGE_PD_PORT_PARAMS = 0x14,
+	CCG_PD_CMD_READ_SRC_PDO = 0x20,
+	CCG_PD_CMD_INITIATE_EPR_ENTRY = 0x47,
+	CCG_PD_CMD_INITIATE_EPR_EXIT = 0x48,
+};
+
+/************************************************
+ * USER COMMANDS for register 0x0040
+ ************************************************/
+enum ccg_userreg_command {
+	CCG_PD_USER_CMD_TYPEC_ERR_RECOVERY = 0x04,
+	CCG_PD_USER_CMD_PD_SEND_HARD_RESET = 0x85,
+	CCG_PD_USER_CMD_PD_SEND_SOFT_RESET = 0x86,
+	CCG_PD_USER_CMD_DATA_RECOVERY      = 0xFF
+};
+
+/************************************************
+ * USER MUXCFG for register 0x0041
+ * This allows us to override the PD mux
+ * configuration for a specific port.
+ ************************************************/
+enum ccg_usermux_configuration {
+	CCG_PD_USER_MUX_CONFIG_ISOLATE = 0,
+	CCG_PD_USER_MUX_CONFIG_SAFE,
+	CCG_PD_USER_MUX_CONFIG_SS_ONLY,
+	CCG_PD_USER_MUX_CONFIG_DEBUG_ACCESSORY = 0x0A
+};
+
+
+
+/************************************************
+ *	RESPONSE DEFINITION
+ * See 001-97863_0N_V.pdf from cypress for the HPI
+ * Definition. Specifically Pages around 22
+ * Chapter 4.1.1 HPI Interfaces response codes
+ ************************************************/
+enum ccg_response {
+	CCG_RESPONSE_NONE,
+	CCG_RESPONSE_SUCCESS = 0x02,
+	CCG_RESPONSE_FLASH_DATA_AVALIABLE = 0x03, /* RESPONSE register only */
+	CCG_RESPONSE_INVALID_COMMAND = 0x05,
+	CCG_RESPONSE_INVALID_STATE = 0x06,
+	CCG_RESPONSE_FLASH_UPDATE_FAILED = 0x07, /* RESPONSE register only */
+	CCG_RESPONSE_INVALID_FW = 0x08, /* RESPONSE register only */
+	CCG_RESPONSE_INVALID_ARGUMENTS = 0x09,
+	CCG_RESPONSE_NOT_SUPPORTED = 0x0A,
+	CCG_RESPONSE_TRANSACTION_FAILED = 0x0C,
+	CCG_RESPONSE_PD_COMMAND_FAILED = 0x0D,
+	CCG_RESPONSE_UNDEFINED_ERROR = 0x0F,
+	CCG_RESPONSE_READ_PDO_DATA = 0x10,
+	CCG_RESPONSE_CMD_ABORTED = 0x11,
+	CCG_RESPONSE_PORT_BUSY = 0x12,
+	CCG_RESPONSE_MINMAX_CURRENT = 0x13,
+	CCG_RESPONSE_EXT_SRC_CAP = 0x14,
+	CCG_RESPONSE_DID_RESPONSE = 0x18,
+	CCG_RESPONSE_SVID_RESPONSE = 0x19,
+	CCG_RESPONSE_DISCOVER_MODE_RESPONSE = 0x1A,
+	CCG_RESPONSE_CABLE_COMM_NOT_ALLOWED = 0x1B,
+	CCG_RESPONSE_EXT_SNK_CAP = 0x1C,
+	CCG_RESPONSE_FWCT_IDENT_INVALID = 0x40,
+	CCG_RESPONSE_FWCT_INVALID_GUID = 0x41,
+	CCG_RESPONSE_FWCT_INVALID_VERSION = 0x42,
+	CCG_RESPONSE_HPI_CMD_INVALID_SEQ = 0x43,
+	CCG_RESPONSE_FWCT_AUTH_FAILED = 0x44,
+	CCG_RESPONSE_HASH_FAILED = 0x45,
+	/* Event and Asynchronous Message Codes */
+	CCG_RESPONSE_RESET_COMPLETE = 0x80,
+	CCG_RESPONSE_MESSAGE_QUEUE_OVERFLOW = 0x81,
+	/* Type C Event and Asynchronous Message Codes */
+	CCG_RESPONSE_OVER_CURRENT = 0x82,
+	CCG_RESPONSE_OVER_VOLT = 0x83,
+	CCG_RESPONSE_PORT_CONNECT = 0x84,
+	CCG_RESPONSE_PORT_DISCONNECT = 0x85,
+	CCG_RESPONSE_PD_CONTRACT_NEGOTIATION_COMPLETE = 0x86,
+	CCG_RESPONSE_SWAP_COMPLETE = 0x87,
+	CCG_RESPONSE_PS_RDY_MSG_PENDING = 0x8A,
+	CCG_RESPONSE_GOTO_MIN_PENDING = 0x8B,
+	CCG_RESPONSE_ACCEPT_MSG_RX = 0x8C,
+	CCG_RESPONSE_REJECT_MSG_RX = 0x8D,
+	CCG_RESPONSE_WAIT_MSG_RX = 0x8E,
+	CCG_RESPONSE_HARD_RESET_RX = 0x8F,
+	/* PD Data Message Specific Events */
+	CCG_RESPONSE_VDM_RX = 0x90,
+	/* Capability Message Specific Events */
+	CCG_RESPONSE_SOURCE_CAP_MSG_RX = 0x91,
+	CCG_RESPONSE_SINK_CAP_MSG_RX = 0x92,
+	/* USB4 Events */
+	CCG_RESPONSE_USB4_DATA_RESET_RX = 0x93,
+	CCG_RESPONSE_USB4_DATA_RESET_COMPLETE = 0x94,
+	CCG_RESPONSE_USB4_ENTRY_COMPLETE = 0x95,
+	/* Resets and Errors */
+	CCG_RESPONSE_HARD_RESET_SENT = 0x9A,
+	CCG_RESPONSE_SOFT_RESET_SENT = 0x9B,
+	CCG_RESPONSE_CABLE_RESET_SENT = 0x9C,
+	CCG_RESPONSE_SOURCEDISABLED = 0x9D,
+	CCG_RESPONSE_SENDER_RESPONSE_TIMEOUT = 0x9E,
+	CCG_RESPONSE_NO_VDM_RESPONSE_RX = 0x9F,
+	CCG_RESPONSE_UNEXPECTED_VOLTAGE = 0xA0,
+	CCG_RESPONSE_TYPE_C_ERROR_RECOVERY = 0xA1,
+	CCG_RESPONSE_BATTERY_STATUS_RX = 0xA2,
+	CCG_RESPONSE_ALERT_RX = 0xA3,
+	CCG_RESPONSE_UNSUPPORTED_MSG_RX = 0xA4,
+	CCG_RESPONSE_EMCA_DETECTED = 0xA6,
+	CCG_RESPONSE_CABLE_DISCOVERY_FAILED = 0xA7,
+	CCG_RESPONSE_RP_CHANGE_DETECTED = 0xAA,
+	CCG_RESPONSE_EXT_MSG_SOP_RX = 0xAC,
+	CCG_RESPONSE_ALT_MODE_EVENT = 0xB0,
+	CCG_RESPONSE_ALT_MODE_HW_EVENT = 0xB1,
+	CCG_RESPONSE_EXT_SOP1_RX = 0xB4,
+	CCG_RESPONSE_EXT_SOP2_RX = 0xB5,
+	CCG_RESPONSE_OVER_TEMP = 0xB6,
+	CCG_RESPONSE_HARDWARE_ERROR = 0xB8,
+	CCG_RESPONSE_VCONN_OCP_ERROR = 0xB9,
+	CCG_RESPONSE_CC_OVP_ERROR = 0xBA,
+	CCG_RESPONSE_SBU_OVP_ERROR = 0xBB,
+	CCG_RESPONSE_VBUS_SHORT_ERROR = 0xBC,
+	CCG_RESPONSE_REVERSE_CURRENT_ERROR = 0xBD,
+	CCG_RESPONSE_SINK_STANDBY = 0xBE,
+	CCG_RESPONSE_ACK_TIMEOUT_EVENT = 0xC0,
+	CCG_RESPONSE_BC12_EVENT = 0xC4,
+	CCG_RESPONSE_EPR_EVENT = 0xD9
+};
+
+enum ccg_pd_state {
+	CCG_STATE_ERROR,
+	CCG_STATE_POWER_ON,
+	CCG_STATE_APP_SETUP,
+	CCG_STATE_READY,
+	CCG_STATE_BOOTLOADER,
+	CCG_STATE_COUNT,
+};
+
+enum ccg_port_state {
+	CCG_DEVICE_DETACH,
+	CCG_DEVICE_ATTACH,
+	CCG_DEVICE_ATTACH_WITH_CONTRACT,
+	CCG_DEVICE_COUNT,
+};
+
+/*TYPE_C_STATUS_DEVICE*/
+enum ccg_c_state {
+	CCG_STATUS_NOTHING,
+	CCG_STATUS_SINK,
+	CCG_STATUS_SOURCE,
+	CCG_STATUS_DEBUG,
+	CCG_STATUS_AUDIO,
+	CCG_STATUS_POWERED_ACC,
+	CCG_STATUS_UNSUPPORTED,
+	CCG_STATUS_INVALID,
+};
+
+enum pd_port_role {
+	PORT_SINK,
+	PORT_SOURCE,
+	PORT_DUALROLE
+};
+
+enum pd_chip {
+	PD_CHIP_0,
+	PD_CHIP_1,
+	PD_CHIP_COUNT
+};
+
+enum pd_port {
+	PD_PORT_0,
+	PD_PORT_1,
+	PD_PORT_2,
+	PD_PORT_3,
+	PD_PORT_COUNT
+};
+
+enum pd_progress {
+	PD_PROGRESS_IDLE = 0,
+	PD_PROGRESS_DISCONNECTED,
+	PD_PROGRESS_ENTER_EPR_MODE,
+	PD_PROGRESS_EXIT_EPR_MODE,
+};
+
+struct pd_chip_config_t {
+	uint16_t i2c_port;
+	uint16_t addr_flags;
+	enum ccg_pd_state state;
+	int gpio;
+	uint8_t version[8];
+};
+
+struct pd_port_current_state_t {
+	enum ccg_port_state port_state;
+	int voltage;
+	int current;
+	enum ccg_c_state c_state; /* What device is attached on the other side */
+	uint8_t pd_state;
+	uint8_t cc;
+	uint8_t epr_active;
+	uint8_t epr_support;
+	uint8_t epr_retry_count;
+
+	enum pd_power_role power_role;
+	enum pd_data_role data_role;
+	enum pd_vconn_role vconn;
+};
+
+struct pd_chip_ucsi_info_t {
+	uint16_t version;
+	uint16_t reserved;
+	uint32_t cci;
+	struct ucsi_control_t {
+		uint8_t command;
+		uint8_t data_len;
+		uint8_t data[6];
+	} control;
+	uint8_t message_in[16];
+	uint8_t message_out[16];
+	int read_tunnel_complete;
+	int write_tunnel_complete;
+	int wait_ack;
+};
+
+int cypd_write_reg8(int controller, int reg, int data);
+
+int cypd_write_reg_block(int controller, int reg, void *data, int len);
+
+int cypd_read_reg_block(int controller, int reg, void *data, int len);
+
+int cypd_clear_int(int controller, int mask);
+
+void cypd_usci_ppm_reset(void);
+
+int cypd_wait_for_ack(int controller, int timeout_us);
+
+void cypd_print_buff(const char *msg, void *buff, int len);
+
+int cypd_get_int(int controller, int *intreg);
+
+/**
+ * If PD chip is doing the firmware update, we should disable the PD task
+ *
+ * @param is_update	Firmware update flag.
+ */
+void set_pd_fw_update(bool is_update);
+
+/**
+ * After PD chip firmware update complete, need to reinitialize the PD chip
+ */
+void cypd_reinitialize(void);
+
+/**
+ * Get the pd version object
+ *
+ * @param controller	PD chip controller
+ * @return uint8_t*
+ */
+uint8_t *get_pd_version(int controller);
+
+/**
+ * Get the PDO current
+ *
+ * @param port		The activer charge port
+ * @return int
+ */
+int pd_get_active_current(int port);
+
+/**
+ * Set system power state
+ *
+ */
+void cypd_set_power_active(void);
+
+/**
+ * Get the active charge pd chip
+ *
+ * @return int
+ */
+int active_charge_pd_chip(void);
+
+int get_active_charge_pd_port(void);
+
+/**
+ * Return Power source port state
+ *
+ * @return int
+ */
+int cypd_vbus_state_check(void);
+
+/**
+ * Return ac power, return by mW.
+ *
+ * @return int
+ */
+int cypd_get_ac_power(void);
+
+void exit_epr_mode(void);
+
+void enter_epr_mode(void);
+
+/**
+ * Safety level LEVEL_TYPEC_1_5A trigger, modify sink 3A port to 1.5A
+ *
+ * @param controller	PD chip controller
+ * @param	port		port id
+ * @return int	EC_SUCCESS
+ */
+int cypd_modify_safety_power_1_5A(int controller, int port);
+
+int cypd_port_3a_status(int controller, int port);
+
+uint8_t cypd_get_cfet_status(void);
+
+#endif /* __CROS_EC_CYPRESS_PD_COMMON_H */
diff --git a/zephyr/program/framework/include/diagnostics.h b/zephyr/program/framework/include/diagnostics.h
new file mode 100644
index 0000000000..9a9d5862f2
--- /dev/null
+++ b/zephyr/program/framework/include/diagnostics.h
@@ -0,0 +1,74 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_DIAGNOSTICS_H
+#define __CROS_EC_DIAGNOSTICS_H
+
+enum diagnostics_device_idx {
+	DIAGNOSTICS_START = 0,
+	DIAGNOSTICS_HW_NO_BATTERY,
+	DIAGNOSTICS_HW_PGOOD_3V5V,
+	DIAGNOSTICS_VCCIN_AUX_VR,
+	DIAGNOSTICS_SLP_S4,
+	DIAGNOSTICS_HW_PGOOD_VR,
+
+#ifdef CONFIG_BOARD_LOTUS
+	DIAGNOSTICS_INPUT_MODULE_FAULT,
+	DIAGNOSTICS_NO_LEFT_FAN,
+	DIAGNOSTICS_NO_RIGHT_FAN,
+	DIAGNOSTICS_GPU_MODULE_FAULT,
+#else
+	DIAGNOSTICS_TOUCHPAD,
+	DIAGNOSTICS_AUDIO_DAUGHTERBOARD,
+	DIAGNOSTICS_THERMAL_SENSOR,
+	DIAGNOSTICS_NOFAN,
+#endif
+	DIAGNOSTICS_NO_S0,
+	DIAGNOSTICS_NO_DDR,
+	DIAGNOSTICS_NO_EDP,
+	DIAGNOSTICS_HW_FINISH,
+
+	/*BIOS BITS*/
+	DIAGNOSTICS_BIOS_BIT0,
+	DIAGNOSTICS_BIOS_BIT1,
+	DIAGNOSTICS_BIOS_BIT2,
+	DIAGNOSTICS_BIOS_BIT3,
+	DIAGNOSTICS_BIOS_BIT4,
+	DIAGNOSTICS_BIOS_BIT5,
+	DIAGNOSTICS_BIOS_BIT6,
+	DIAGNOSTICS_BIOS_BIT7,
+	DIAGNOSTICS_MAX
+};
+
+/*
+ * If there is an error with this diagnostic, then set error=true
+ * this is used as a bitmask to flash out any error codes
+ */
+void set_diagnostic(enum diagnostics_device_idx idx, bool error);
+
+/*
+ * Set it to true means ec has done the device detecting
+ */
+void set_device_complete(int done);
+
+uint32_t get_hw_diagnostic(void);
+uint8_t is_bios_complete(void);
+uint8_t is_device_complete(void);
+
+void set_bios_diagnostic(uint8_t code);
+
+void reset_diagnostics(void);
+
+void cancel_diagnostics(void);
+
+void project_diagnostics(void);
+
+bool diagnostics_tick(void);
+
+void set_standalone_mode(int enable);
+
+int get_standalone_mode(void);
+
+#endif	/* __CROS_EC_DIAGNOSTICS_H */
diff --git a/zephyr/program/framework/include/factory.h b/zephyr/program/framework/include/factory.h
new file mode 100644
index 0000000000..0de6687c36
--- /dev/null
+++ b/zephyr/program/framework/include/factory.h
@@ -0,0 +1,13 @@
+/* Copyright 202 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_FACTORY_H
+#define __CROS_EC_FACTORY_H
+
+void factory_setting(uint8_t enable);
+
+int factory_status(void);
+
+#endif	/* __CROS_EC_FACTORY_H */
diff --git a/zephyr/program/framework/include/flash_storage.h b/zephyr/program/framework/include/flash_storage.h
new file mode 100644
index 0000000000..d819656c24
--- /dev/null
+++ b/zephyr/program/framework/include/flash_storage.h
@@ -0,0 +1,72 @@
+/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * flash storage function for seldom updated flash flags
+ */
+
+#ifndef __CROS_EC_FLASHSTORAGE_H
+#define __CROS_EC_FLASHSTORAGE_H
+
+#define SPI_FLAGS_REGION (0x7F000)
+#define SPI_FLAGS_SIZE (0x1000)
+
+enum ec_flash_flags_idx {
+	FLASH_FLAGS_ACPOWERON = 0,
+	FLASH_FLAGS_STANDALONE = 1,
+	FLASH_FLAGS_INPUT_MODULE_POWER = 2,
+	FLASH_FLAGS_ENABLE_GPU_MUX = 3,
+	FLASH_FLAGS_ENABLE_GPU_DETECT = 4,
+	FLASH_FLAGS_MAX = 64
+};
+
+#define FLASH_FLAGS_MAGIC (0xF1A3)
+#define FLASH_FLAGS_VERSION (0x1)
+
+struct ec_flash_flags_info {
+	/* Header */
+	uint32_t magic; /* 0xF1A3 */
+	uint32_t length; /* Length of fields following this */
+	uint32_t version; /* Version=1, update this if field structures below this change */
+	/**
+	 * An incrementing counter that should be incremented
+	 * every time the structure is written to flash
+	 */
+	uint32_t update_number;
+
+	uint8_t flags[FLASH_FLAGS_MAX];
+
+} __ec_align1;
+
+/**
+ * @brief Update flags value at idx, but does not write to flash
+ *
+ * @param idx ec_flash_flags_idx for which flag to update
+ * @param v uint8_t new value
+ * @return int EC_SUCCESS
+ */
+int flash_storage_update(enum ec_flash_flags_idx idx, uint8_t v);
+
+/**
+ * @brief Commits storage if dirty
+ *
+ * @return int EC_SUCCESS
+ */
+int flash_storage_commit(void);
+
+/**
+ * @brief Get flags value
+ *
+ * @param idx index of flag to get
+ * @return int flag value, or -1 on failure
+ */
+int flash_storage_get(enum ec_flash_flags_idx idx);
+
+/**
+ * @brief Initialize structure in memory, does not update flash
+ *
+ * @return int EC_SUCCESS
+ */
+void flash_storage_load_defaults(void);
+
+#endif	/* __CROS_EC_FLASHSTORAGE_H */
diff --git a/zephyr/program/framework/include/hid_device.h b/zephyr/program/framework/include/hid_device.h
new file mode 100644
index 0000000000..13b584cd02
--- /dev/null
+++ b/zephyr/program/framework/include/hid_device.h
@@ -0,0 +1,25 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_I2C_HID_DEVICE_H
+#define __CROS_EC_I2C_HID_DEVICE_H
+
+#include "util.h"
+
+/*
+ * See hid usage tables for consumer page
+ * https://www.usb.org/hid
+ */
+#define BUTTON_ID_BRIGHTNESS_INCREMENT 0x006F
+#define BUTTON_ID_BRIGHTNESS_DECREMENT 0x0070
+
+void hid_consumer(uint16_t  id, bool pressed);
+void hid_airplane(bool pressed);
+
+int hid_target_register(const struct device *dev);
+
+int hid_target_unregister(const struct device *dev);
+
+#endif /* __CROS_EC_I2C_HID_DEVICE_H */
diff --git a/zephyr/program/framework/include/led.h b/zephyr/program/framework/include/led.h
new file mode 100644
index 0000000000..ca7f3eb538
--- /dev/null
+++ b/zephyr/program/framework/include/led.h
@@ -0,0 +1,129 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_LED_H__
+#define __CROS_EC_LED_H__
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/pwm.h>
+
+#define PINS_NODE(id) DT_CAT(PIN_NODE_, id)
+#define PINS_ARRAY(id) DT_CAT(PINS_ARRAY_, id)
+
+/*
+ * Return string-token if the property exists, otherwise return 0
+ */
+#define GET_PROP(id, prop)                      \
+	COND_CODE_1(DT_NODE_HAS_PROP(id, prop), \
+		    (DT_STRING_UPPER_TOKEN(id, prop)), (0))
+
+/*
+ * Return string-token if the property exists, otherwise return
+ * EC_LED_COLOR_INVALID.
+ */
+#define GET_COLOR_PROP_NVE(id, prop)                  \
+	COND_CODE_1(DT_NODE_HAS_PROP(id, prop), \
+		    (DT_STRING_UPPER_TOKEN(id, prop)), (EC_LED_COLOR_INVALID))
+
+#define LED_ENUM(id, enum_name) DT_STRING_TOKEN(id, enum_name)
+#define LED_ENUM_WITH_COMMA(id, enum_name)           \
+	COND_CODE_1(DT_NODE_HAS_PROP(id, enum_name), \
+		    (LED_ENUM(id, enum_name), ), ())
+
+#define FP_LED_HIGH 55
+#define FP_LED_MEDIUM 40
+#define FP_LED_LOW 15
+
+#define BREATH_ON_LENGTH_HIGH	62
+#define BREATH_ON_LENGTH_MID	72
+#define BREATH_ON_LENGTH_LOW	90
+
+#define BREATH_OFF_LENGTH 200
+
+enum led_color {
+	LED_OFF,
+	LED_RED,
+	LED_GREEN,
+	LED_BLUE,
+	LED_YELLOW,
+	LED_WHITE,
+	LED_AMBER,
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
+};
+
+enum fp_led_brightness_level {
+	FP_LED_BRIGHTNESS_HIGH = 0,
+	FP_LED_BRIGHTNESS_MEDIUM = 1,
+	FP_LED_BRIGHTNESS_LOW = 2,
+};
+
+/*
+ * Struct defining LED GPIO pin and value to set.
+ */
+struct gpio_pin_t {
+	enum gpio_signal signal;
+	int val;
+};
+
+/*
+ * Struct defining LED PWM pin and duty cycle to set.
+ */
+struct pwm_pin_t {
+	struct pwm_dt_spec pwm;
+	uint32_t pulse_ns; /* PWM Duty cycle ns */
+};
+
+/*
+ * Pin node contains LED color and array of gpio/pwm pins
+ * to alter in order to enable the given color.
+ */
+struct led_pins_node_t {
+	/*
+	 * Link between color and pins node. Only used to support
+	 * ectool functionality.
+	 */
+	int led_color;
+
+	/*
+	 * Link between color and pins node. Only used to support
+	 * ectool functionality.
+	 */
+	enum ec_led_id led_id;
+
+	/* Brightness Range color, only used to support ectool functionality */
+	enum ec_led_colors br_color;
+
+	/* Array of PWM pins to set to enable particular color */
+	struct pwm_pin_t *pwm_pins;
+
+	/* Number of pins per color */
+	uint8_t pins_count;
+};
+
+/**
+ * Set LED color using color enum
+ *
+ * @param color		LED Color to enable
+ * @param led_id	LED ID to set the color for
+ */
+void led_set_color(enum led_color color, enum ec_led_id led_id);
+
+/**
+ * Set LED color using pins node
+ *
+ * @param *pins_node	Pins node to enable the color corresponding
+ *			to the node.
+ */
+void led_set_color_with_node(const struct led_pins_node_t *pins_node);
+
+#ifdef TEST_BUILD
+const struct led_pins_node_t *led_get_node(enum led_color color,
+					   enum ec_led_id led_id);
+
+enum power_state get_chipset_state(void);
+#endif /* TEST_BUILD */
+
+#endif /* __CROS_EC_LED_H__ */
diff --git a/zephyr/program/framework/include/lotus/amd_r23m.h b/zephyr/program/framework/include/lotus/amd_r23m.h
new file mode 100644
index 0000000000..40f260357e
--- /dev/null
+++ b/zephyr/program/framework/include/lotus/amd_r23m.h
@@ -0,0 +1,36 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* GPU AMD R23M configuration */
+
+#ifndef __CROS_EC_AMD_R23M_H
+#define __CROS_EC_AMD_R23M_H
+
+#include "i2c.h"
+
+/* GPU features */
+#define AMD_R23M_LOCAL 0
+
+struct amdr23m_sensor_t {
+	int i2c_port;
+	int i2c_addr_flags;
+};
+
+extern const struct amdr23m_sensor_t amdr23m_sensors[];
+
+/*
+ * get GPU temperature value and move to *tem_ptr
+ * One second trigger ,Use I2C read GPU's Die temperature.
+ */
+
+int get_temp_amd_R23M(int idx, int *temp_ptr);
+
+#ifdef CONFIG_ZEPHYR
+void amdr23m_update_temperature(int idx);
+#endif
+
+int amdr23m_get_val_k(int idx, int *temp);
+
+#endif /* __CROS_EC_AMD_R23M_H */
diff --git a/zephyr/program/framework/include/lotus/board_battery.h b/zephyr/program/framework/include/lotus/board_battery.h
new file mode 100644
index 0000000000..86b5282fd0
--- /dev/null
+++ b/zephyr/program/framework/include/lotus/board_battery.h
@@ -0,0 +1,11 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_BOARD_BATTERY_H__
+#define __CROS_EC_BOARD_BATTERY_H__
+
+int get_average_battery_current(void);
+
+#endif /* __CROS_EC_BOARD_BATTERY_H__ */
diff --git a/zephyr/program/framework/include/lotus/board_thermal.h b/zephyr/program/framework/include/lotus/board_thermal.h
new file mode 100644
index 0000000000..53d29895b9
--- /dev/null
+++ b/zephyr/program/framework/include/lotus/board_thermal.h
@@ -0,0 +1,15 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_BOARD_THERMAL_H__
+#define __CROS_EC_BOARD_THERMAL_H__
+
+#include "common.h"
+#include "config.h"
+#include "gpu_configuration.h"
+
+void fan_configure_gpu(struct gpu_cfg_fan *fan);
+
+#endif /* __CROS_EC_BOARD_THERMAL_H__ */
diff --git a/zephyr/program/framework/include/lotus/cpu_power.h b/zephyr/program/framework/include/lotus/cpu_power.h
new file mode 100644
index 0000000000..d07208325e
--- /dev/null
+++ b/zephyr/program/framework/include/lotus/cpu_power.h
@@ -0,0 +1,19 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_CPU_POWER_H__
+#define __CROS_EC_CPU_POWER_H__
+
+/**
+ * Check if safety level(LEVEL_TYPEC_1_5A) is triggered.
+ *
+ * @param none
+ * @return true:safety level(LEVEL_TYPEC_1_5A) is triggered
+ *              all sink port need to be forced to 1.5A
+ *         false:safety level(LEVEL_TYPEC_1_5A) is not trigger
+ */
+bool safety_force_typec_1_5A(void);
+
+#endif /* __CROS_EC_CPU_POWER_H__ */
diff --git a/zephyr/program/framework/include/lotus/ej889i.h b/zephyr/program/framework/include/lotus/ej889i.h
new file mode 100644
index 0000000000..7d8de57b3c
--- /dev/null
+++ b/zephyr/program/framework/include/lotus/ej889i.h
@@ -0,0 +1,14 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_EJ889I_H__
+#define __CROS_EC_EJ889I_H__
+
+#include "common.h"
+#include "config.h"
+#include "gpu_configuration.h"
+int ej889i_init(struct gpu_subsys_pd *init);
+
+#endif /* __CROS_EC_EJ889I_H__ */
diff --git a/zephyr/program/framework/include/lotus/gpu.h b/zephyr/program/framework/include/lotus/gpu.h
new file mode 100644
index 0000000000..011e6b5037
--- /dev/null
+++ b/zephyr/program/framework/include/lotus/gpu.h
@@ -0,0 +1,35 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __BOARD_GPU_H__
+#define __BOARD_GPU_H__
+
+#include <gpu_configuration.h>
+#include "common_cpu_power.h"
+
+
+bool gpu_power_enable(void);
+
+bool gpu_is_working(void);
+
+bool gpu_module_fault(void);
+
+void gpu_fan_control(int enable);
+
+void set_host_dp_ready(int ready);
+
+void update_gpu_ac_power_state(void);
+
+void set_gpu_gpio(enum gpu_gpio_purpose gpu_gpio, int level);
+
+int get_gpu_gpio(enum gpu_gpio_purpose gpu_gpio);
+
+int get_gpu_latch(void);
+
+bool gpu_fan_board_present(void);
+
+void update_gpu_ac_mode_deferred(int times);
+
+#endif /* __BOARD_GPU_H__ */
diff --git a/zephyr/program/framework/include/lotus/gpu_configuration.h b/zephyr/program/framework/include/lotus/gpu_configuration.h
new file mode 100644
index 0000000000..88c3f06a3d
--- /dev/null
+++ b/zephyr/program/framework/include/lotus/gpu_configuration.h
@@ -0,0 +1,254 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_GPU_CONFIGURATION_H__
+#define __CROS_EC_GPU_CONFIGURATION_H__
+
+#include "common.h"
+#include "config.h"
+
+/*
+ * The Framework bay descriptor consists of a header and a series of blocks
+ * after the header that describe the function of the card.
+ *
+ * Each block starts with a block header which is 4 bytes, and then block
+ * data.
+ *
+ * -------------
+ *  HEADER
+ * -------------
+ * BLOCK1 Header
+ * -------------
+ * BLOCK1 Data
+ * -------------
+ * BLOCK2 Header
+ * -------------
+ * Block2 Data
+ * -------------
+ */
+
+#define GPU_MAX_BLOCK_LEN (256)
+#define GPU_SERIAL_LEN 20
+
+struct gpu_cfg_descriptor {
+	/* Expansion bay card magic value that is unique */
+	char magic[4];
+	/* Length of header following this field */
+	uint32_t length;
+	/* descriptor version, if EC max version is lower than this, ec cannot parse */
+	uint16_t descriptor_version_major;
+	uint16_t descriptor_version_minor;
+	/* Hardware major version */
+	uint16_t hardware_version;
+	/* Hardware minor revision */
+	uint16_t hardware_revision;
+	/* 18 digit Framework Serial that starts with FRA
+	 * the first 10 digits must be allocated by framework
+	 */
+	char serial[20];
+	/* Length of descriptor following header*/
+	uint32_t descriptor_length;
+	/* CRC of descriptor */
+	uint32_t descriptor_crc32;
+	/* CRC of header before this value */
+	uint32_t crc32;
+} __packed;
+
+struct gpu_config_header {
+	union {
+		struct gpu_cfg_descriptor header;
+		uint8_t bytes[0x2B];
+	};
+} __packed;
+
+struct gpu_block_header {
+	uint8_t block_type;
+	uint8_t block_length;
+} __packed;
+BUILD_ASSERT(sizeof(struct gpu_block_header) == 2);
+
+enum gpucfg_type {
+	GPUCFG_TYPE_UNINITIALIZED = 0,
+	GPUCFG_TYPE_GPIO = 1,
+	GPUCFG_TYPE_THERMAL_SENSOR = 2,
+	GPUCFG_TYPE_FAN = 3,
+	GPUCFG_TYPE_POWER = 4,
+	GPUCFG_TYPE_BATTERY = 5,
+	GPUCFG_TYPE_PCIE = 6,
+	GPUCFG_TYPE_DPMUX = 7,
+	GPUCFG_TYPE_POWEREN = 8,
+	GPUCFG_TYPE_SUBSYS = 9,
+	GPUCFG_TYPE_VENDOR = 10,
+	GPUCFG_TYPE_PD = 11,
+	GPUCFG_TYPE_GPUPWR = 12,
+	GPUCFG_TYPE_CUSTOM_TEMP = 13,
+	GPUCFG_TYPE_MAX = UINT8_MAX, /**< Force enum to be 8 bits */
+} __packed;
+BUILD_ASSERT(sizeof(enum gpucfg_type) == sizeof(uint8_t));
+
+enum gpu_gpio_idx {
+	GPU_GPIO_INVALID = 0,
+	GPU_1G1_GPIO0_EC,
+	GPU_1H1_GPIO1_EC,
+	GPU_2A2_GPIO2_EC,
+	GPU_2L7_GPIO3_EC,
+	GPU_2L5_TH_OVERTn, /* cannot be controlled directly */
+	GPU_1F2_I2C_S5_INT,
+	GPU_1L1_DGPU_PWROK, /* connected to APU */
+	GPU_1C3_ALW_CLK, /* ALW I2C CLOCK PIN to EC */
+	GPU_1D3_ALW_DAT, /* ALW I2C DATA PIN to EC */
+	GPU_1F3_MUX1, /* cannot be controlled directly */
+	GPU_1G3_MUX2, /* cannot be controlled directly */
+	GPU_2B5_ALERTn,
+	GPU_EDP_MUX_SEL, /* Select EDP MUX */
+	GPU_ECPWM_EN, /**/
+	GPU_PCIE_MUX_SEL, /* select between EDP AUX or SSD PCIE2 CLK*/
+	GPU_VSYS_EN,
+	GPU_VADP_EN,
+	GPU_FAN_EN,
+	GPU_3V_5V_EN,
+	GPU_GPIO_MAX
+} __packed;
+
+enum gpu_gpio_purpose {
+	GPIO_FUNC_UNUSED,
+	GPIO_FUNC_HIGH, /* set high */
+	GPIO_FUNC_TEMPFAULT,
+	GPIO_FUNC_ACDC,
+	GPIO_FUNC_HPD,
+	GPIO_FUNC_PD_INT,
+	GPIO_FUNC_SSD1_POWER,
+	GPIO_FUNC_SSD2_POWER,
+	GPIO_FUNC_EC_PWM_EN,
+	GPIO_FUNC_EDP_MUX_SEL,
+	GPIO_FUNC_VSYS_EN,
+	GPIO_FUNC_VADP_EN,
+	GPIO_FUNC_GPU_PWR,
+	GPIO_FUNC_MAX,
+};
+
+enum power_request_source_t {
+	POWER_REQ_INIT,
+	POWER_REQ_POWER_ON,
+	POWER_REQ_GPU_3V_5V,
+	POWER_REQ_COUNT,
+};
+
+struct gpu_cfg_gpio {
+	uint8_t gpio;
+	uint8_t function;
+	uint32_t flags;
+	/* Follow enum power_state, if the system power state is lower than this power state,
+	 * it will be turned off (low)
+	 */
+	uint8_t power_domain;
+} __packed;
+
+enum gpu_thermal_sensor {
+	GPU_THERM_INVALID,
+	GPU_THERM_F75303,
+} __packed;
+struct gpu_cfg_thermal {
+	uint8_t thermal_type;
+	uint8_t address;
+	uint32_t reserved;
+	uint32_t reserved2;
+} __packed;
+
+struct gpu_cfg_custom_temp {
+	uint8_t idx;
+	uint16_t temp_fan_off;
+	uint16_t temp_fan_max;
+} __packed;
+
+struct gpu_cfg_fan {
+	uint8_t idx;
+	uint8_t flags;
+	uint16_t min_rpm;
+	uint16_t min_temp;
+	uint16_t start_rpm;
+	uint16_t max_rpm;
+	uint16_t max_temp;
+} __packed;
+
+struct gpu_cfg_power {
+	uint8_t device_idx;
+	uint8_t battery_power;
+	uint8_t average_power;
+	uint8_t long_term_power;
+	uint8_t short_term_power;
+	uint8_t peak_power;
+} __packed;
+
+struct gpu_cfg_battery {
+	uint16_t max_current;
+	uint16_t max_mv;
+	uint16_t min_mv;
+	uint16_t max_charge_current;
+} __packed;
+
+
+enum gpu_subsys_type {
+	GPU_ASSEMBLY = 0, /* Populated in header, not valid for extended structure */
+	GPU_PCB = 1,
+	GPU_LEFT_FAN = 2,
+	GPU_RIGHT_FAN = 3,
+	GPU_HOUSING = 4,
+	GPU_SUBSYS_MAX = 10,
+};
+struct gpu_subsys_serial {
+	uint8_t gpu_subsys;
+	char serial[GPU_SERIAL_LEN];
+} __packed;
+
+enum gpu_pcie_cfg {
+	PCIE_8X1 = 0,
+	PCIE_4X1 = 1,
+	PCIE_4X2 = 2,
+} __packed;
+BUILD_ASSERT(sizeof(enum gpu_pcie_cfg) == sizeof(uint8_t));
+
+
+enum gpu_vendor {
+	GPU_VENDOR_INITIALIZING = 0,
+	GPU_FAN_ONLY = 1,
+	GPU_AMD_R23M = 2,
+	GPU_SSD = 3,
+	GPU_PCIE_ACCESSORY = 4
+} __packed;
+BUILD_ASSERT(sizeof(enum gpu_vendor) == sizeof(uint8_t));
+
+enum gpu_pd {
+	PD_TYPE_INVALID = 0,
+	PD_TYPE_ETRON_EJ889I = 1,
+	PD_TYPE_MAX = 0xFF
+} __packed;
+struct gpu_subsys_pd {
+	uint8_t gpu_pd_type;
+	uint8_t address;
+	uint32_t flags;
+	uint32_t pdo;
+	uint32_t rdo;
+	uint8_t power_domain;
+	uint8_t gpio_hpd;
+	uint8_t gpio_interrupt;
+} __packed;
+
+void init_gpu_module(void);
+void init_uma_fan(void);
+void deinit_gpu_module(void);
+void gpu_module_gpio_safe(void);
+int parse_gpu_eeprom(void);
+void set_gpu_gpios_powerstate(void);
+void control_5valw_power(enum power_request_source_t pwr, bool enable);
+
+const struct gpio_dt_spec *gpu_gpio_to_dt(enum gpu_gpio_idx gpio_idx);
+const struct gpio_int_config *gpu_gpio_to_dt_int(enum gpu_gpio_idx gpio_idx);
+void set_gpu_gpio(enum gpu_gpio_purpose gpiofn, int level);
+int get_gpu_gpio(enum gpu_gpio_purpose gpiofn);
+
+bool gpu_present(void);
+
+#endif /* __CROS_EC_GPU_CONFIGURATION_H__ */
diff --git a/zephyr/program/framework/include/lotus/gpu_f75303.h b/zephyr/program/framework/include/lotus/gpu_f75303.h
new file mode 100644
index 0000000000..49d94d0088
--- /dev/null
+++ b/zephyr/program/framework/include/lotus/gpu_f75303.h
@@ -0,0 +1,16 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_GPU_F75303_H__
+#define __CROS_EC_GPU_F75303_H__
+
+#include "common.h"
+#include "config.h"
+#include "gpu_configuration.h"
+
+void gpu_f75303_init(struct gpu_cfg_thermal *sensor);
+
+bool gpu_f75303_present(void);
+#endif /* __CROS_EC_GPU_F75303_H__ */
diff --git a/zephyr/program/framework/include/lotus/input_module.h b/zephyr/program/framework/include/lotus/input_module.h
new file mode 100644
index 0000000000..48abf758bb
--- /dev/null
+++ b/zephyr/program/framework/include/lotus/input_module.h
@@ -0,0 +1,61 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __BOARD_INPUT_MODULE_H__
+#define __BOARD_INPUT_MODULE_H__
+
+enum input_modules_t {
+	INPUT_MODULE_SHORT,
+	INPUT_MODULE_RESERVED_1,
+	INPUT_MODULE_RESERVED_2,
+	INPUT_MODULE_RESERVED_3,
+	INPUT_MODULE_RESERVED_4,
+	INPUT_MODULE_RESERVED_5,
+	INPUT_MODULE_FULL_WIDTH,
+	INPUT_MODULE_HUBBOARD,
+	INPUT_MODULE_GENERIC_A,
+	INPUT_MODULE_GENERIC_B,
+	INPUT_MODULE_GENERIC_C,
+	INPUT_MODULE_KEYBOARD_B,
+	INPUT_MODULE_KEYBOARD_A,
+	INPUT_MODULE_TOUCHPAD,
+	INPUT_MODULE_RESERVED_14,
+	INPUT_MODULE_DISCONNECTED,
+};
+
+enum input_deck_state {
+	DECK_OFF,
+	DECK_DISCONNECTED,
+	DECK_TURNING_ON,
+	DECK_ON,
+	DECK_FORCE_OFF,
+	DECK_FORCE_ON,
+	DECK_NO_DETECTION /* input deck will follow power sequence, no present check */
+};
+
+enum input_deck_mux {
+	TOP_ROW_0 = 0,
+	TOP_ROW_1,
+	TOP_ROW_2,
+	TOP_ROW_3,
+	TOP_ROW_4,
+	TOUCHPAD,
+	TOP_ROW_NOT_CONNECTED,
+	HUBBOARD = 7
+};
+
+int get_deck_state(void);
+
+bool input_deck_is_fully_populated(void);
+
+void input_modules_powerdown(void);
+
+void input_modules_reset(void);
+
+void set_detect_mode(int mode);
+
+int get_detect_mode(void);
+
+#endif /*__BOARD_INPUT_MODULE_H__*/
diff --git a/zephyr/program/framework/include/lotus/touchpad_descriptor.h b/zephyr/program/framework/include/lotus/touchpad_descriptor.h
new file mode 100644
index 0000000000..38efae42c1
--- /dev/null
+++ b/zephyr/program/framework/include/lotus/touchpad_descriptor.h
@@ -0,0 +1,369 @@
+/*
+ * Copyright (c) 2023 Framework Computer
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef __CROS_EC_TOUCHPAD_DESCRIPTOR_H
+#define __CROS_EC_TOUCHPAD_DESCRIPTOR_H
+
+#include "hid_device.h"
+
+/* This exactly mimics the touchpad when it is not physically connected */
+static const uint8_t touchpad_report_desc[] = {
+	0x05, 0x01, /* USAGE_PAGE () */
+	0x09, 0x02,
+	0xA1, 0x01,
+	0x85, 0x01,
+	0x05, 0x01,
+	0x09, 0x01,
+	0xA1, 0x00,
+	0x05, 0x09,
+	0x19, 0x01,
+	0x29, 0x02,
+	0x15, 0x00,
+	0x25, 0x01,
+	0x75, 0x01,
+	0x95, 0x02,
+	0x81, 0x02,
+	0x95, 0x06,
+	0x81, 0x03,
+	0x05, 0x01,
+	0x09, 0x30,
+	0x09, 0x31,
+	0x09, 0x38,
+	0x15, 0x81,
+	0x25, 0x7F,
+	0x75, 0x08,
+	0x95, 0x03,
+	0x81, 0x26,
+	0x05, 0x0C,
+	0x0A, 0x38,
+	0x02, 0x95,
+	0x01, 0x81,
+	0x06, 0x75,
+	0x08, 0x95,
+	0x03, 0x81,
+	0x03, 0xC0,
+	0xC0, 0x05,
+	0x0D, 0x09,
+	0x05, 0xA1,
+	0x01, 0x85,
+	0x04, 0x05,
+	0x09, 0x09,
+	0x01, 0x15,
+	0x00, 0x25,
+	0x01, 0x75,
+	0x01, 0x95,
+	0x01, 0x81,
+	0x02, 0x95,
+	0x02, 0x81,
+	0x03, 0x06,
+	0x01, 0xFF,
+	0x09, 0x01,
+	0x95, 0x01,
+	0x81, 0x02,
+	0x05, 0x0D,
+	0x09, 0x54,
+	0x25, 0x05,
+	0x75, 0x04,
+	0x95, 0x01,
+	0x81, 0x02,
+	0x09, 0x56,
+	0x55, 0x0C,
+	0x66, 0x01,
+	0x10, 0x47,
+	0xFF, 0xFF,
+	0x00, 0x00,
+	0x27, 0xFF,
+	0xFF, 0x00,
+	0x00, 0x75,
+	0x10, 0x95,
+	0x01, 0x81,
+	0x02, 0x05,
+	0x0D, 0x09,
+	0x22, 0xA1,
+	0x02, 0x09,
+	0x47, 0x09,
+	0x42, 0x15,
+	0x00, 0x25,
+	0x01, 0x75,
+	0x01, 0x95,
+	0x02, 0x81,
+	0x02, 0x95,
+	0x02, 0x81,
+	0x03, 0x09,
+	0x51, 0x25,
+	0x0A, 0x75,
+	0x04, 0x95,
+	0x01, 0x81,
+	0x02, 0x05,
+	0x01, 0x09,
+	0x30, 0x35,
+	0x00, 0x46,
+	0xC4, 0x04,
+	0x26, 0x01,
+	0x0F, 0x55,
+	0x0E, 0x65,
+	0x11, 0x75,
+	0x10, 0x95,
+	0x01, 0x81,
+	0x02, 0x09,
+	0x31, 0x46,
+	0xF8, 0x02,
+	0x26, 0x58,
+	0x09, 0x81,
+	0x02, 0xC0,
+	0x05, 0x0D,
+	0x09, 0x22,
+	0xA1, 0x02,
+	0x09, 0x47,
+	0x09, 0x42,
+	0x15, 0x00,
+	0x25, 0x01,
+	0x75, 0x01,
+	0x95, 0x02,
+	0x81, 0x02,
+	0x95, 0x02,
+	0x81, 0x03,
+	0x09, 0x51,
+	0x25, 0x0A,
+	0x75, 0x04,
+	0x95, 0x01,
+	0x81, 0x02,
+	0x05, 0x01,
+	0x09, 0x30,
+	0x35, 0x00,
+	0x46, 0xC4,
+	0x04, 0x26,
+	0x01, 0x0F,
+	0x55, 0x0E,
+	0x65, 0x11,
+	0x75, 0x10,
+	0x95, 0x01,
+	0x81, 0x02,
+	0x09, 0x31,
+	0x46, 0xF8,
+	0x02, 0x26,
+	0x58, 0x09,
+	0x81, 0x02,
+	0xC0, 0x05,
+	0x0D, 0x09,
+	0x22, 0xA1,
+	0x02, 0x09,
+	0x47, 0x09,
+	0x42, 0x15,
+	0x00, 0x25,
+	0x01, 0x75,
+	0x01, 0x95,
+	0x02, 0x81,
+	0x02, 0x95,
+	0x02, 0x81,
+	0x03, 0x09,
+	0x51, 0x25,
+	0x0A, 0x75,
+	0x04, 0x95,
+	0x01, 0x81,
+	0x02, 0x05,
+	0x01, 0x09,
+	0x30, 0x35,
+	0x00, 0x46,
+	0xC4, 0x04,
+	0x26, 0x01,
+	0x0F, 0x55,
+	0x0E, 0x65,
+	0x11, 0x75,
+	0x10, 0x95,
+	0x01, 0x81,
+	0x02, 0x09,
+	0x31, 0x46,
+	0xF8, 0x02,
+	0x26, 0x58,
+	0x09, 0x81,
+	0x02, 0xC0,
+	0x05, 0x0D,
+	0x09, 0x22,
+	0xA1, 0x02,
+	0x09, 0x47,
+	0x09, 0x42,
+	0x15, 0x00,
+	0x25, 0x01,
+	0x75, 0x01,
+	0x95, 0x02,
+	0x81, 0x02,
+	0x95, 0x02,
+	0x81, 0x03,
+	0x09, 0x51,
+	0x25, 0x0A,
+	0x75, 0x04,
+	0x95, 0x01,
+	0x81, 0x02,
+	0x05, 0x01,
+	0x09, 0x30,
+	0x35, 0x00,
+	0x46, 0xC4,
+	0x04, 0x26,
+	0x01, 0x0F,
+	0x55, 0x0E,
+	0x65, 0x11,
+	0x75, 0x10,
+	0x95, 0x01,
+	0x81, 0x02,
+	0x09, 0x31,
+	0x46, 0xF8,
+	0x02, 0x26,
+	0x58, 0x09,
+	0x81, 0x02,
+	0xC0, 0x05,
+	0x0D, 0x09,
+	0x22, 0xA1,
+	0x02, 0x09,
+	0x47, 0x09,
+	0x42, 0x15,
+	0x00, 0x25,
+	0x01, 0x75,
+	0x01, 0x95,
+	0x02, 0x81,
+	0x02, 0x95,
+	0x02, 0x81,
+	0x03, 0x09,
+	0x51, 0x25,
+	0x0A, 0x75,
+	0x04, 0x95,
+	0x01, 0x81,
+	0x02, 0x05,
+	0x01, 0x09,
+	0x30, 0x35,
+	0x00, 0x46,
+	0xC4, 0x04,
+	0x26, 0x01,
+	0x0F, 0x55,
+	0x0E, 0x65,
+	0x11, 0x75,
+	0x10, 0x95,
+	0x01, 0x81,
+	0x02, 0x09,
+	0x31, 0x46,
+	0xF8, 0x02,
+	0x26, 0x58,
+	0x09, 0x81,
+	0x02, 0xC0,
+	0x05, 0x0D,
+	0x85, 0x02,
+	0x09, 0x55,
+	0x15, 0x00,
+	0x25, 0x05,
+	0x75, 0x08,
+	0x95, 0x01,
+	0xB1, 0x02,
+	0x05, 0x0D,
+	0x85, 0x06,
+	0x09, 0x59,
+	0x15, 0x00,
+	0x25, 0x0F,
+	0x75, 0x08,
+	0x95, 0x01,
+	0xB1, 0x02,
+	0x05, 0x0D,
+	0x85, 0x07,
+	0x09, 0x60,
+	0x15, 0x00,
+	0x25, 0x01,
+	0x75, 0x01,
+	0x95, 0x01,
+	0xB1, 0x02,
+	0x95, 0x0F,
+	0xB1, 0x03,
+	0x06, 0x00,
+	0xFF, 0x85,
+	0x0B, 0x09,
+	0xC5, 0x15,
+	0x00, 0x26,
+	0xFF, 0x00,
+	0x75, 0x08,
+	0x96, 0x00,
+	0x01, 0xB1,
+	0x02, 0xC0,
+	0x05, 0x0D,
+	0x09, 0x0E,
+	0xA1, 0x01,
+	0x05, 0x0D,
+	0x09, 0x22,
+	0xA1, 0x02,
+	0x85, 0x03,
+	0x09, 0x52,
+	0x15, 0x00,
+	0x25, 0x0A,
+	0x75, 0x08,
+	0x95, 0x01,
+	0xB1, 0x02,
+	0xC0, 0x05,
+	0x0D, 0x09,
+	0x22, 0xA1,
+	0x00, 0x85,
+	0x05, 0x09,
+	0x57, 0x09,
+	0x58, 0x15,
+	0x00, 0x25,
+	0x01, 0x75,
+	0x01, 0x95,
+	0x02, 0xB1,
+	0x02, 0x95,
+	0x06, 0xB1,
+	0x03, 0xC0,
+	0xC0, 0x06,
+	0x00, 0xFF,
+	0x09, 0x01,
+	0xA1, 0x01,
+	0x85, 0x42,
+	0x09, 0x06,
+	0x15, 0x00,
+	0x26, 0xFF,
+	0x00, 0x75,
+	0x08, 0x95,
+	0x03, 0xB1,
+	0x02, 0x85,
+	0x43, 0x09,
+	0x06, 0x15,
+	0x00, 0x26,
+	0xFF, 0x00,
+	0x75, 0x08,
+	0x95, 0x03,
+	0xB1, 0x02,
+	0x06, 0x00,
+	0xFF, 0x85,
+	0x41, 0x09,
+	0x05, 0x15,
+	0x00, 0x26,
+	0xFF, 0x00,
+	0x75, 0x08,
+	0x96, 0x00,
+	0x01, 0xB1,
+	0x02, 
+	0xC0 /* END_COLLECTION */
+};
+#define I2C_TOUCHPAD_HID_DESC_REGISTER 0x0020
+#define I2C_TOUCHPAD_HID_REPORT_DESC_REGISTER 0x0021
+#define I2C_TOUCHPAD_HID_INPUT_REPORT_REGISTER 0x0024
+#define I2C_TOUCHPAD_HID_OUTPUT_REPORT_REGISTER 0x0025
+#define I2C_TOUCHPAD_HID_COMMAND_REGISTER 0x0022
+#define I2C_TOUCHPAD_HID_DATA_REGISTER 0x0023
+static struct i2c_hid_descriptor touchpad_hid_desc = {
+	.wHIDDescLength = I2C_HID_DESC_LENGTH,
+	.bcdVersion = I2C_HID_BCD_VERSION,
+	.wReportDescLength = sizeof(touchpad_report_desc),
+	.wReportDescRegister = I2C_TOUCHPAD_HID_REPORT_DESC_REGISTER,
+	.wInputRegister = I2C_TOUCHPAD_HID_INPUT_REPORT_REGISTER,
+	/*Note if there are multiple reports wMaxInputLength has to be max*/
+	.wMaxInputLength = 0x1F,
+	.wOutputRegister = I2C_TOUCHPAD_HID_OUTPUT_REPORT_REGISTER,
+	.wMaxOutputLength = 0,
+	.wCommandRegister = I2C_TOUCHPAD_HID_COMMAND_REGISTER,
+	.wDataRegister = I2C_TOUCHPAD_HID_DATA_REGISTER,
+	.wVendorID = 0x093A,
+	.wProductID = 0x0274,
+	.wVersionID = 0x0905,
+};
+
+
+
+#endif /* __CROS_EC_TOUCHPAD_DESCRIPTOR_H */
diff --git a/zephyr/program/framework/include/power_sequence.h b/zephyr/program/framework/include/power_sequence.h
new file mode 100644
index 0000000000..f96b1163e3
--- /dev/null
+++ b/zephyr/program/framework/include/power_sequence.h
@@ -0,0 +1,35 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_POWERSEQUENCE_H
+#define __CROS_EC_POWERSEQUENCE_H
+
+/* Power signals list */
+enum power_signal {
+	X86_3VALW_PG,
+	X86_SLP_S3_N,
+	X86_SLP_S5_N,
+	X86_VR_PG,
+	POWER_SIGNAL_COUNT
+};
+
+/* s0ix entry/exit flag state */
+enum s0ix_state {
+	CS_NONE,
+	CS_ENTER_S0ix,
+	CS_EXIT_S0ix,
+};
+
+int get_power_rail_status(void);
+
+void clear_power_flags(void);
+
+void power_s5_up_control(int control);
+
+void power_state_clear(int state);
+
+int check_s0ix_status(void);
+
+#endif	/* __CROS_EC_POWERSEQUENCE_H */
diff --git a/zephyr/program/framework/include/temperature_filter.h b/zephyr/program/framework/include/temperature_filter.h
new file mode 100644
index 0000000000..46496e32e5
--- /dev/null
+++ b/zephyr/program/framework/include/temperature_filter.h
@@ -0,0 +1,29 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Low pass filter for on die temperature
+ */
+#ifndef __CROS_EC_TEMPERATURE_FILTER_H
+#define __CROS_EC_TEMPERATURE_FILTER_H
+
+#include "util.h"
+#include "math_util.h"
+
+#define Q_SCALE 14
+/* scale input up to improve filter performance */
+#define IN_SCALE 7
+
+struct biquad {
+	/* State values x[n-1], x[n-2], y[n-1], y[n-2] */
+	int32_t state[4];
+	const int32_t *coeff;
+};
+
+void thermal_filter_reset(struct biquad *filter);
+
+int thermal_filter_update(struct biquad *filter, int value);
+
+int thermal_filter_get(struct biquad *filter);
+
+#endif /* __CROS_EC_TEMPERATURE_FILTER_H */
diff --git a/zephyr/program/framework/include/ucsi.h b/zephyr/program/framework/include/ucsi.h
new file mode 100644
index 0000000000..2b7d5ef464
--- /dev/null
+++ b/zephyr/program/framework/include/ucsi.h
@@ -0,0 +1,51 @@
+/* Copyright 2023 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * PD chip UCSI
+ */
+
+#ifndef __CROS_EC_UCSI_H
+#define __CROS_EC_UCSI_H
+
+
+/************************************************/
+/*	UCSI CONTROL DEFINITION                 */
+/************************************************/
+enum ucsi_control {
+	CYPD_UCSI_START   = 0x01,
+	CYPD_UCSI_STOP    = 0x02,
+	CYPD_UCSI_SILENCE = 0x03,
+	CYPD_UCSI_SIGNAL_CONNECT_EVENT_TO_OS = 0x04
+};
+
+enum ucsi_command {
+	UCSI_CMD_RESERVE,
+	UCSI_CMD_PPM_RESET,
+	UCSI_CMD_CANCEL,
+	UCSI_CMD_CONNECTOR_RESET,
+	UCSI_CMD_ACK_CC_CI,
+	UCSI_CMD_SET_NOTIFICATION_ENABLE,
+	UCSI_CMD_GET_CAPABILITY,
+	UCSI_CMD_GET_CONNECTOR_CAPABILITY,
+	UCSI_CMD_SET_UOM,
+	UCSI_CMD_SET_UOR,
+	UCSI_CMD_SET_PDM,
+	UCSI_CMD_SET_PDR,
+	UCSI_CMD_GET_ALTERNATE_MODES,
+	UCSI_CMD_GET_CAM_SUPPORTED,
+	UCSI_CMD_GET_CURRENT_CAM,
+	UCSI_CMD_SET_NEW_CAM,
+	UCSI_CMD_GET_PDOS,
+	UCSI_CMD_GET_CABLE_PROPERTY,
+	UCSI_CMD_GET_CONNECTOR_STATUS,
+	UCSI_CMD_GET_ERROR_STATUS,
+};
+
+int ucsi_write_tunnel(void);
+int ucsi_read_tunnel(int controller);
+int ucsi_startup(int controller);
+void ucsi_set_debug(bool enable);
+void check_ucsi_event_from_host(void);
+void record_ucsi_connector_change_event(int controller, int port);
+#endif	/* __CROS_EC_UCSI_H */
diff --git a/zephyr/program/framework/include/uefi_app_mode.h b/zephyr/program/framework/include/uefi_app_mode.h
new file mode 100644
index 0000000000..3c35fa18e9
--- /dev/null
+++ b/zephyr/program/framework/include/uefi_app_mode.h
@@ -0,0 +1,13 @@
+/* Copyright 202 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_UEFI_APP_MODE_H
+#define __CROS_EC_UEFI_APP_MODE_H
+
+void uefi_app_mode_setting(uint8_t enable);
+
+uint8_t uefi_app_btn_status(void);
+
+#endif	/* __CROS_EC_UEFI_APP_MODE_H */
diff --git a/zephyr/program/framework/lotus/adc.dtsi b/zephyr/program/framework/lotus/adc.dtsi
new file mode 100644
index 0000000000..c6cbc9713e
--- /dev/null
+++ b/zephyr/program/framework/lotus/adc.dtsi
@@ -0,0 +1,43 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <cros/thermistor/thermistor.dtsi>
+
+/ {
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		adc_main_boardid: main-boardid {
+			enum-name = "ADC_MAIN_BOARD_ID";
+			io-channels = <&adc0 0>;
+		};
+		adc_hub_boardid: hub-boardid {
+			enum-name = "ADC_HUB_BOARD_ID";
+			io-channels = <&adc0 1>;
+		};
+		adc_gpu_boardid0: gpu-boardid0 {
+			enum-name = "ADC_GPU_BOARD_ID_0";
+			io-channels = <&adc0 2>;
+		};
+		adc_gpu_boardid1: gpu-boardid1 {
+			enum-name = "ADC_GPU_BOARD_ID_1";
+			io-channels = <&adc0 3>;
+		};
+		adc_i_adp: i-adp {
+			enum-name = "ADC_ADAPTER_CURRENT";
+			io-channels = <&adc0 5>;
+		};
+	};
+};
+
+&adc0 {
+	status = "okay";
+	pinctrl-0 = <&adc0_chan0_gp45
+		     &adc0_chan1_gp44
+		     &adc0_chan2_gp43
+		     &adc0_chan3_gp42
+		     &adc0_chan5_gp37>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/framework/lotus/battery.dtsi b/zephyr/program/framework/lotus/battery.dtsi
new file mode 100644
index 0000000000..abc40ff9e0
--- /dev/null
+++ b/zephyr/program/framework/lotus/battery.dtsi
@@ -0,0 +1,12 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	batteries {
+		default_battery: atl_framework85w {
+			compatible = "atl,framework85w", "battery-smart";
+		};
+	};
+};
diff --git a/zephyr/program/framework/lotus/fan.dtsi b/zephyr/program/framework/lotus/fan.dtsi
new file mode 100644
index 0000000000..88d4f471c8
--- /dev/null
+++ b/zephyr/program/framework/lotus/fan.dtsi
@@ -0,0 +1,63 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	fans {
+		compatible = "cros-ec,fans";
+
+		fan0: fan_0 {
+			pwms = <&pwm0 0 PWM_KHZ(25) PWM_POLARITY_NORMAL>;
+			tach = <&tach1>;
+			rpm_min = <1000>;
+			rpm_start = <1000>;
+			rpm_max = <4000>;
+			rpm_deviation = <3>;
+			pgood_gpio = <&gpio_slp_s3_l>;
+		};
+
+		fan1: fan_1 {
+			pwms = <&pwm1 0 PWM_KHZ(25) PWM_POLARITY_NORMAL>;
+			tach = <&tach2>;
+			rpm_min = <1000>;
+			rpm_start = <1000>;
+			rpm_max = <3700>;
+			rpm_deviation = <3>;
+			pgood_gpio = <&gpio_slp_s3_l>;
+		};
+	};
+};
+/* Tachemeter for fan speed measurement */
+&tach1 {
+	status = "okay";
+	/* force to change the register base of the node tach1 */
+	reg = <0x400e3000 0x2000>;
+	clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL1 6>;
+	pinctrl-0 = <&ta2_1_in_gp73>;
+	pinctrl-names = "default";
+	port = <NPCX_TACH_PORT_A>; /* port-A is selected */
+	sample-clk = <NPCX_TACH_FREQ_LFCLK>; /* Use LFCLK as sampling clock */
+	pulses-per-round = <2>; /* number of pulses per round of encoder */
+};
+
+&tach2 {
+	status = "okay";
+	pinctrl-0 = <&tb2_2_in_gpa7>;
+	pinctrl-names = "default";
+	port = <NPCX_TACH_PORT_B>; /* port-B is selected */
+	sample-clk = <NPCX_TACH_FREQ_LFCLK>; /* Use LFCLK as sampling clock */
+	pulses-per-round = <2>; /* number of pulses per round of encoder */
+};
+
+&pwm0 {
+	status = "okay";
+	pinctrl-0 = <&pwm0_gpc3>;
+	pinctrl-names = "default";
+};
+
+&pwm1 {
+	status = "okay";
+	pinctrl-0 = <&pwm1_gpc2>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/framework/lotus/gpio.dtsi b/zephyr/program/framework/lotus/gpio.dtsi
new file mode 100644
index 0000000000..d4882cb269
--- /dev/null
+++ b/zephyr/program/framework/lotus/gpio.dtsi
@@ -0,0 +1,340 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	aliases {
+		gpio-check-fp-control = &gpio_fp_control;
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l {
+			gpios = <&gpio5 6 (GPIO_OUTPUT_LOW | GPIO_VOLTAGE_1P8)>;
+		};
+		ec_espi_rst_l {
+			gpios = <&gpio5 4 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		gpio_edp_mux_pwm_sw: edp_mux_pwm_sw {
+			gpios = <&gpioc 6 GPIO_OUTPUT_LOW>;	/* Reserved */
+		};
+		gpio_ec_sci_l: ec_sci_l {
+			gpios = <&gpio7 6 GPIO_ODR_LOW>;	/* Reserved */
+		};
+		ovp {
+			gpios = <&gpioc 5 GPIO_INPUT>;		/* SYS report Fault even to EC */
+		};
+		ec_smb_ck0 {
+			gpios = <&gpiob 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		ec_smb_da0 {
+			gpios = <&gpiob 4 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		ec_smb_ck1 {
+			gpios = <&gpio9 0 GPIO_INPUT>;
+		};
+		ec_smb_da1 {
+			gpios = <&gpio8 7 GPIO_INPUT>;
+		};
+		ec_smb_ck2 {
+			gpios = <&gpio9 2 GPIO_INPUT>;
+		};
+		ec_smb_da2 {
+			gpios = <&gpio9 1 GPIO_INPUT>;
+		};
+		ec_smb_ck3 {
+			gpios = <&gpiod 1 GPIO_INPUT>;
+		};
+		ec_smb_da3 {
+			gpios = <&gpiod 0 GPIO_INPUT>;
+		};
+		ec_smb_ck4 {
+			gpios = <&gpiof 3 GPIO_ODR_LOW>;
+		};
+		ec_smb_da4 {
+			gpios = <&gpiof 2 GPIO_ODR_LOW>;
+		};
+		ec_smb_s0_ck5 {
+			gpios = <&gpio3 3 GPIO_INPUT>;
+		};
+		ec_smb_s0_da5 {
+			gpios = <&gpio3 6 GPIO_INPUT>;
+		};
+		gpio_ssd2_pwr_en: ssd2_pwr_en {
+			gpios = <&gpiof 5 GPIO_OUTPUT_LOW>; /* control JSSD2 PWR */
+		};
+		gpio_ssd_gpu_sel: ssd_gpu_sel {
+			gpios = <&gpiof 4 GPIO_OUTPUT_HIGH>; /* L:GPU; H:SSD */
+		};
+		ec_smb_ck6 {
+			gpios = <&gpioe 4 GPIO_ODR_LOW>;
+		};
+		ec_smb_da6 {
+			gpios = <&gpioe 3 GPIO_ODR_LOW>;
+		};
+		ec_smb_ck7 {
+			gpios = <&gpiob 3 GPIO_INPUT>;
+		};
+		ec_smb_da7 {
+			gpios = <&gpiob 2 GPIO_INPUT>;
+		};
+		gpio_mic_sw: mic_sw {
+			gpios = <&gpioc 1 GPIO_INPUT>;
+		};
+		gpio_gpu_b_gpio00_ec: gpu_b_gpio00_ec {
+			gpios = <&gpio3 1 GPIO_ODR_HIGH>;	/* Reserved */
+		};
+		gpio_gpu_b_gpio01_ec: gpu_b_gpio01_ec {
+			gpios = <&gpio3 0 GPIO_INPUT>;		/* Control 2nd Batt discharge */
+		};
+		gpio_gpu_b_gpio02_ec: gpu_b_gpio02_ec {
+			gpios = <&gpio2 7 GPIO_OUTPUT_LOW>;	/* PWR switch from AC to DC */
+		};
+		gpio_gpu_b_gpio03_ec: gpu_b_gpio03_ec {
+			gpios = <&gpio2 6 GPIO_ODR_HIGH>;	/* Reserved */
+		};
+		gpio_usb3_ec_p2_cc1: usb3_ec_p2_cc1 {
+			gpios = <&gpio2 5 GPIO_OUTPUT_LOW>;	/* Control GL3590 type-c orientation */
+		};
+		gpio_usb3_ec_p2_cc2: usb3_ec_p2_cc2 {
+			gpios = <&gpio2 4 GPIO_OUTPUT_LOW>;	/* Control GL3590 type-c orientation */
+		};
+		gpio_fp_en: fp_en {
+			gpios = <&gpio2 3 GPIO_OUTPUT_LOW>;
+		};
+		gpio_5valw_c_en: 5valw_c_en {
+			gpios = <&gpio2 2 GPIO_OUTPUT_LOW>;
+		};
+		gpu_b_dp_hpd {
+			gpios = <&gpio2 1 GPIO_OUTPUT_LOW>;	/* From GPU ALWS SMBus detect HPD than output to APU */
+		};
+		gpio_ec_mute_l: ec_mute_l {
+			gpios = <&gpio2 0 GPIO_ODR_LOW>;
+		};
+		gpio_gpu_3v_5v_en: gpu_3v_5v_en {
+			/* Detect GPU/B then enable 3V/5V PWR output H */
+			gpios = <&gpio1 7 GPIO_OUTPUT_LOW>;
+		};
+		gpio_wlan_en: wlan_en {
+			gpios = <&gpio1 6 GPIO_OUTPUT_LOW>;
+		};
+		gpio_gpu_vsys_en: gpu_vsys_en {
+			gpios = <&gpio1 5 GPIO_OUTPUT_LOW>;	/* Enable GPIO Vsys PWR */
+		};
+		gpio_apu_ec_int_l: apu_ec_int_l {
+			gpios = <&gpio1 4 GPIO_ODR_HIGH>;	/* HID over I2C interrupt */
+		};
+		ec_disen2 {
+			gpios = <&gpio1 3 GPIO_OUTPUT_LOW>;	/* Disable LM5143 Ph2 */
+		};
+		rtc_dis {
+			gpios = <&gpio1 2 GPIO_OUTPUT_LOW>;	/* RTC discharge */
+		};
+		gpio_gpu_vdap_en: gpu_vdap_en {
+			gpios = <&gpio1 1 GPIO_OUTPUT_LOW>;	/* Enable GPIO ADP PWR */
+		};
+		gpio_ec_pwm_en_l: ec_pwm_en_l {
+			gpios = <&gpio1 0 GPIO_OUTPUT_LOW>;	/* Enable EDP mux control chip */
+		};
+		ac_present_pd_l {
+			gpios = <&gpio0 7 GPIO_INPUT>;		/* Monitor AC present from PD */
+		};
+		gpio_sm_panel_bken_ec: sm_panel_bken_ec {
+			gpios = <&gpio0 6 GPIO_OUTPUT_LOW>;
+		};
+		ec_b2b_dis {
+			gpios = <&gpio0 5 GPIO_OUTPUT_LOW>;
+		};
+		gpio_gpu_fan_en: gpu_fan_en {
+			gpios = <&gpio0 4 GPIO_OUTPUT_LOW>;	/* 1: enable; 0: disable */
+		};
+		gpio_usb30_hub_en: usb30_hub_en {
+			gpios = <&gpio8 2 GPIO_OUTPUT_LOW>;
+		};
+		gpio_module_oc_interrupt: module_oc_l {
+			gpios = <&gpio8 3 GPIO_INPUT>;		/* Detect Hub/B 3V/5V OCP event */
+		};
+		gpio_ec_edp_reset: ec_edp_reset {
+			gpios = <&gpio0 3 GPIO_OUTPUT_LOW>;
+		};
+		gpio_gpu_alert_l: gpu_alert_l {
+			gpios = <&gpiob 1 GPIO_INPUT>;
+		};
+		gpio_on_off_btn_l: on_off_btn_l {
+			gpios = <&gpiod 2 GPIO_INPUT>;		/* PSL in1 signal, power button */
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		gpio_chassis_open_l: chassis_open_l {
+			gpios = <&gpio0 0 GPIO_INPUT>;		/* PSL in2 signal, chassis open */
+		};
+		gpio_hw_acav_in: hw_acav_in {
+			gpios = <&gpio0 1 GPIO_INPUT>;		/* PSL in3 signal, ac present pin */
+			enum-name = "GPIO_AC_PRESENT";
+		};
+		gpio_lid_sw_l: lid_sw_l {
+			gpios = <&gpio0 2 GPIO_INPUT>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+		gpio_0p75_1p8valw_pwren: 0p75_1p8valw_pwren {
+			gpios = <&gpiod 7 GPIO_OUTPUT_LOW>;
+		};
+		gpio_hub_b_pwr_en: hub_b_pwr_en {
+			gpios = <&gpio8 6 GPIO_OUTPUT_LOW>;
+		};
+		als_int_l {
+			gpios = <&gpio7 5 GPIO_INPUT>;
+		};
+		gpio_pch_pwr_en: pch_pwr_en {
+			gpios = <&gpiod 4 GPIO_OUTPUT_LOW>;
+		};
+		gpio_h_prochot_l: h_prochot_l {
+			gpios = <&gpioa 1 GPIO_ODR_HIGH>;
+		};
+		gpio_slp_s3_l: slp_s3_l {
+			gpios = <&gpioa 3 GPIO_INPUT>;
+			enum-name = "GPIO_PCH_SLP_S3_L";
+		};
+		gpio_slp_s5_l: slp_s5_l {
+			gpios = <&gpio9 5 GPIO_INPUT>;
+			enum-name = "GPIO_PCH_SLP_S5_L";
+		};
+		gpio_cam_en: cam_en {
+			gpios = <&gpio6 7 GPIO_OUTPUT_LOW>;
+		};
+		gpio_sys_pwrgd_ec: sys_pwrgd_ec {
+			gpios = <&gpio7 0 GPIO_OUTPUT_LOW>;
+		};
+		gpio_vr_on: vr_on {
+			gpios = <&gpio6 2 GPIO_OUTPUT_LOW>;
+		};
+		gpio_susp_l: susp_l {
+			gpios = <&gpio6 3 GPIO_OUTPUT_LOW>;
+		};
+		gpio_left_side: left_side {
+			gpios = <&gpio4 0 GPIO_OUTPUT_LOW>;	/* left side LED follow IFGA3 */
+		};
+		gpio_right_side: right_side {
+			gpios = <&gpiod 3 GPIO_OUTPUT_LOW>;	/* right side LED follow IFGA3 */
+		};
+		gpio_syson: syson {
+			gpios = <&gpioa 6 GPIO_OUTPUT_LOW>;
+		};
+		ec_edp_pwm {
+			gpios = <&gpioc 0 GPIO_INPUT>;
+		};
+		gpio_fp_control: fp_control {
+			gpios = <&gpio6 0 GPIO_INPUT>;		/* Finger Printer feature */
+		};
+		gpio_battery_present: battery_present {
+			gpios = <&gpio4 1 GPIO_INPUT>;
+		};
+		gpio_mux_a0: mux_a0 {
+			gpios = <&gpio3 4 GPIO_OUTPUT_LOW>;
+		};
+		gpio_mux_a1: mux_a1 {
+			gpios = <&gpioe 1 GPIO_OUTPUT_LOW>;
+		};
+		gpio_mux_a2: mux_a2 {
+			gpios = <&gpiof 1 GPIO_OUTPUT_LOW>;
+		};
+		gpio_f_beam_open_l: f_beam_open_l {
+			gpios = <&gpiof 0 GPIO_INPUT>;
+		};
+		gpio_enblk_apu: enbkl_apu {
+			gpios = <&gpioe 0 GPIO_INPUT>;		/* monitor APU EDP BKL */
+		};
+		gpio_dgpu_pwr_en: dgpu_pwr_en {
+			gpios = <&gpioc 7 GPIO_INPUT>;
+		};
+		gpio_0p75vs_pwr_en: 0p75vs_pwr_en {
+			gpios = <&gpioa 2 GPIO_OUTPUT_LOW>;
+		};
+		gpio_apu_aud_pwr_en: apu_aud_pwr_en {
+			gpios = <&gpioa 0 GPIO_OUTPUT_LOW>;
+		};
+		gpio_i2c_int_tp_1: i2c_int_tp_1 {
+			gpios = <&gpioa 4 GPIO_ODR_HIGH>;		/* HUB board TP module */
+		};
+		i2c_int_tp_2 {
+			gpios = <&gpio9 6 GPIO_INPUT>;		/* HUB board TP module */
+		};
+		gpio_cam_sw: cam_sw {
+			gpios = <&gpio9 3 GPIO_INPUT>;
+		};
+		gpio_spok: spok {
+			gpios = <&gpio9 4 GPIO_INPUT>;		/* Monitor 3VALW PWR OK */
+			enum-name = "GPIO_POWER_GOOD_3VALW";
+		};
+		gpio_vr_pwrgd: vr_pwrgd {
+			gpios = <&gpio9 7 GPIO_INPUT>;
+			enum-name = "GPIO_POWER_GOOD_VR";
+		};
+		gpio_gpu_i2c_s5_int: gpu_i2c_s5_int {
+			gpios = <&gpioa 5 GPIO_INPUT>;
+		};
+		gpio_usb_hub_re_en: usb_hub_re_en {
+			gpios = <&gpiob 0 GPIO_OUTPUT_LOW>;
+		};
+		gpio_wl_rst_l: wl_rst_l {
+			gpios = <&gpio6 1 GPIO_OUTPUT_LOW>;
+		};
+		gpio_ec_sense_al: ec_sense_al {
+			gpios = <&gpio7 2 GPIO_INPUT>;
+		};
+		gpio_en_invpwr: en_invpwr {
+			gpios = <&gpio7 4 GPIO_OUTPUT_LOW>;
+		};
+		gpio_sleep_l: sleep_l {
+			gpios = <&gpiod 5 GPIO_OUTPUT_LOW>;
+		};
+		gpio_pd_chip1_interrupt: pd_b_i2c_int_ec_l {
+			gpios = <&gpioe 2 GPIO_INPUT>;
+			enum-name = "GPIO_EC_PD_INTB_L";
+		};
+		gpio_pd_chip0_interrupt: pd_a_i2c_int_ec_l {
+			gpios = <&gpioe 5 GPIO_INPUT>;
+			enum-name = "GPIO_EC_PD_INTA_L";
+		};
+		gpio_pbtn_out: pbtn_out_l {
+			gpios = <&gpio5 0 (GPIO_ODR_LOW | GPIO_VOLTAGE_1P8)>;
+			enum-name = "GPIO_PCH_PWRBTN_L";
+		};
+		thermtrip {
+			gpios = <&gpio8 1 GPIO_INPUT>;
+		};
+		/* unimplemented GPIOs */
+		entering-rw {
+			enum-name = "GPIO_ENTERING_RW";
+		};
+	};
+};
+
+/* PSL input pads*/
+&psl_in1_gpd2 {
+	/* Power button */
+	psl-in-mode = "edge";
+	psl-in-pol = "low-falling";
+};
+
+&psl_in3_gp01 {
+	/* ac present */
+	psl-in-mode = "edge";
+	psl-in-pol = "high-rising";
+};
+
+/* Power domain device controlled by PSL (Power Switch Logic) IO pads */
+/* Ignored the PSL in 2 (chassis open) at proto phase */
+&power_ctrl_psl {
+	status = "okay";
+	pinctrl-names = "sleep";
+	pinctrl-0 = <&psl_in1_gpd2 &psl_in3_gp01>;
+};
+
+/* host interface */
+&espi0 {
+	status = "okay";
+	pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/framework/lotus/i2c.dtsi b/zephyr/program/framework/lotus/i2c.dtsi
new file mode 100644
index 0000000000..c2c900e27b
--- /dev/null
+++ b/zephyr/program/framework/lotus/i2c.dtsi
@@ -0,0 +1,241 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+ #include <dt-bindings/usb_pd_tcpm.h>
+
+/ {
+	aliases {
+		i2c-0 = &i2c0_0;
+		i2c-1 = &i2c1_0;
+		i2c-2 = &i2c2_0;
+		i2c-3 = &i2c3_0;
+		i2c-4 = &i2c4_1;
+		i2c-5 = &i2c5_1;
+		i2c-6 = &i2c6_1;
+		i2c-7 = &i2c7_0;
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+		i2c_hid_slave: hid_slave {
+			/* TODO: how to configure slave mode */
+			i2c-port = <&i2c0_0>;
+			enum-names = "I2C_PORT_HID_SLAVE";
+		};
+		i2c_cypd0: cypd0 {
+			i2c-port = <&i2c1_0>;
+			enum-names = "I2C_PORT_PD_MCU0";
+		};
+		i2c_cypd1: cypd1 {
+			i2c-port = <&i2c2_0>;
+			enum-names = "I2C_PORT_PD_MCU1";
+		};
+		i2c_battery: battery{
+			i2c-port = <&i2c3_0>;
+			enum-names = "I2C_PORT_BATTERY",
+				"I2C_PORT_CHARGER",
+				"I2C_PORT_MASTER";
+		};
+		i2c_touchpad: touchpad {
+			i2c-port = <&i2c4_1>;
+			enum-names = "I2C_PORT_TOUCHPAD";
+			dynamic-speed;
+		};
+		i2c_gpu0: gpu0 {
+			i2c-port = <&i2c5_0>;
+			enum-names = "I2C_PORT_GPU0";
+		};
+		i2c_gpu1: gpu1 {
+			i2c-port = <&i2c6_1>;
+			enum-names = "I2C_PORT_GPU1";
+		};
+		i2c_sensor: sensor {
+			i2c-port = <&i2c7_0>;
+			enum-names =  "I2C_PORT_SENSOR",
+				"I2C_PORT_THERMAL_AP",
+				"I2C_PORT_ALS";
+		};
+	};
+};
+
+&i2c0_0 {
+	status = "okay";
+	label = "I2C_PORT0";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>;
+	pinctrl-names = "default";
+
+	i2chid1: i2chid@51 {
+		compatible = "cros-ec,i2c-target-hid";
+		reg = <0x51>;
+		alert_gpios = <&gpio1 4 GPIO_OPEN_DRAIN>;
+		max_report_size = <32>;
+		hid_descriptor = "als_hid_desc";
+		hid_report_descriptor = "als_report_desc";
+	};
+};
+
+&i2c_ctrl0 {
+	status = "okay";
+};
+
+&i2c1_0 {
+	status = "okay";
+	label = "I2C_PORT1";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>;
+	pinctrl-names = "default";
+
+	/* TODO: Add the device on this bus */
+};
+
+&i2c_ctrl1 {
+	status = "okay";
+};
+
+&i2c2_0 {
+	status = "okay";
+	label = "I2C_PORT2";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c2_0_sda_scl_gp91_92>;
+	pinctrl-names = "default";
+
+	/* TODO: Add the device on this bus */
+};
+
+&i2c_ctrl2 {
+	status = "okay";
+};
+
+&i2c3_0 {
+	status = "okay";
+	label = "I2C_PORT3";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>;
+	pinctrl-names = "default";
+
+	/* TODO: Add the device on this bus */
+	charger: isl9241@9 {
+		compatible = "intersil,isl9241";
+		status = "okay";
+		reg = <0x9>;
+	};
+};
+
+&i2c_ctrl3 {
+	status = "okay";
+};
+
+&i2c4_1 {
+	status = "okay";
+	label = "I2C_PORT4";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	pinctrl-0 = <&i2c4_1_sda_scl_gpf2_f3>;
+	pinctrl-names = "default";
+
+	i2chid2: i2chid@2c {
+		compatible = "cros-ec,i2c-target-hid";
+		reg = <0x2c>;
+		alert_gpios = <&gpioa 4 GPIO_OPEN_DRAIN>;
+		max_report_size = <32>;
+		hid_descriptor = "touchpad_hid_desc";
+		hid_report_descriptor = "touchpad_report_desc";
+	};
+};
+
+&i2c_ctrl4 {
+	status = "okay";
+};
+
+&i2c5_0 {
+	status = "okay";
+	label = "I2C_PORT5";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	pinctrl-0 = <&i2c5_0_sda_scl_gp33_36>;
+	pinctrl-names = "default";
+
+	/* TODO: Add the device on this bus */
+	gpu_amb_f75303: gpu_amb_f75303@4d {
+		compatible = "cros-ec,temp-sensor-f75303";
+		temperature-type = "F75303_IDX_GPU_LOCAL";
+		reg = <0x4d>;
+	};
+
+	gpu_vr_f75303: gpu_vr_f75303@4d {
+		compatible = "cros-ec,temp-sensor-f75303";
+		temperature-type = "F75303_IDX_GPU_REMOTE1";
+		reg = <0x4d>;
+	};
+
+	gpu_vram_f75303: gpu_vram_f75303@4d {
+		compatible = "cros-ec,temp-sensor-f75303";
+		temperature-type = "F75303_IDX_GPU_REMOTE2";
+		reg = <0x4d>;
+	};
+	gpu_amdr23m: gpu_amdr23m@40 {
+		compatible = "cros-ec,temp-sensor-amdr23m";
+		reg = <0x40>;
+		status = "okay";
+	};
+};
+
+&i2c_ctrl5 {
+	status = "okay";
+};
+
+&i2c6_1 {
+	status = "okay";
+	label = "I2C_PORT6";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	pinctrl-0 = <&i2c6_1_sda_scl_gpe3_e4>;
+	pinctrl-names = "default";
+
+	/* TODO: Add the device on this bus */
+};
+
+&i2c_ctrl6 {
+	status = "okay";
+};
+
+&i2c7_0 {
+	status = "okay";
+	label = "I2C_PORT7";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>;
+	pinctrl-names = "default";
+
+	/* TODO: Add the device on this bus */
+	ambient_f75303: ambient_f75303@4d {
+		compatible = "cros-ec,temp-sensor-f75303";
+		temperature-type = "F75303_IDX_LOCAL";
+		reg = <0x4d>;
+	};
+
+	charger_f75303: charger_f75303@4d {
+		compatible = "cros-ec,temp-sensor-f75303";
+		temperature-type = "F75303_IDX_REMOTE2";
+		reg = <0x4d>;
+	};
+
+	apu_f75303: apu_f75303@4d {
+		compatible = "cros-ec,temp-sensor-f75303";
+		temperature-type = "F75303_IDX_REMOTE1";
+		reg = <0x4d>;
+	};
+
+	temp_cpu: cpu@4c {
+		compatible = "amd,sb-tsi";
+		reg = <0x4c>;
+	};
+
+	als_cm32183: als-cm32183@29 {
+		compatible = "nxp,cm32183";
+		reg = <0x29>;
+	};
+};
+
+&i2c_ctrl7 {
+	status = "okay";
+};
diff --git a/zephyr/program/framework/lotus/interrupts.dtsi b/zephyr/program/framework/lotus/interrupts.dtsi
new file mode 100644
index 0000000000..4a71a88f19
--- /dev/null
+++ b/zephyr/program/framework/lotus/interrupts.dtsi
@@ -0,0 +1,86 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_powerbtn: powerbtn {
+			irq-pin = <&gpio_on_off_btn_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "board_power_button_interrupt";
+		};
+		int_slp_s3: slp_s3 {
+			irq-pin = <&gpio_slp_s3_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_slp_s5: slp_s5 {
+			irq-pin = <&gpio_slp_s5_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_3valw_pg: 3valw_pg {
+			irq-pin = <&gpio_spok>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_vr_pg: vr_pg {
+			irq-pin = <&gpio_vr_pwrgd>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_pd_chip0_interrupt: pd_chip0_interrupt {
+			irq-pin = <&gpio_pd_chip0_interrupt>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "pd0_chip_interrupt";
+		};
+		int_pd_chip1_interrupt: pd_chip1_interrupt {
+			irq-pin = <&gpio_pd_chip1_interrupt>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "pd1_chip_interrupt";
+		};
+		int_module_oc_interrupt: module_oc_interrupt {
+			irq-pin = <&gpio_module_oc_interrupt>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "module_oc_interrupt";
+		};
+		int_lid_open: lid_open {
+			irq-pin = <&gpio_lid_sw_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "lid_interrupt";
+		};
+		int_chassis_open: chassis_open {
+			irq-pin = <&gpio_chassis_open_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "chassis_interrupt_handler";
+		};
+		int_beam_open: beam_open {
+			irq-pin = <&gpio_f_beam_open_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "beam_open_interrupt";
+		};
+		int_gpu_pd: gpu_pd {
+			irq-pin = <&gpio_gpu_i2c_s5_int>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "gpu_pd_interrupt";
+		};
+		int_dp_hot_plug: dp_hot_plug {
+			irq-pin = <&gpio_gpu_b_gpio01_ec>;
+			flags = <GPIO_INT_EDGE_RISING>;
+			handler = "dp_hot_plug_interrupt";
+		};
+		int_gpu_power_en: gpu_power_en {
+			irq-pin = <&gpio_dgpu_pwr_en>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "gpu_power_enable_handler";
+		};
+		int_ina236_alert: ina236_alert {
+			irq-pin = <&gpio_ec_sense_al>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "ina236_alert_interrupt";
+		};
+	};
+};
diff --git a/zephyr/program/framework/lotus/led_pins.dtsi b/zephyr/program/framework/lotus/led_pins.dtsi
new file mode 100644
index 0000000000..c48618bbe6
--- /dev/null
+++ b/zephyr/program/framework/lotus/led_pins.dtsi
@@ -0,0 +1,126 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	pwmleds {
+		compatible = "pwm-leds";
+
+		pwm_b: pwm_b {
+			pwms = <&pwm2 0 PWM_HZ(324) PWM_POLARITY_NORMAL>;
+		};
+
+		pwm_r: pwm_r {
+			pwms = <&pwm3 0 PWM_HZ(324) PWM_POLARITY_NORMAL>;
+		};
+
+		pwm_g: pwm_g {
+			pwms = <&pwm4 0 PWM_HZ(324) PWM_POLARITY_NORMAL>;
+		};
+
+		pwm_power_w: pwm_power_w {
+			pwms = <&pwm5 0 PWM_HZ(324) PWM_POLARITY_NORMAL>;
+		};
+	};
+
+	pwm-led-pins {
+		compatible = "cros-ec,pwm-led-pins";
+
+		battery_led: battery-led {
+			led-id = "EC_LED_ID_BATTERY_LED";
+			led-pwms = <&pwm_r &pwm_g &pwm_b>;
+
+
+			color_off: color-off {
+				led-color = "LED_OFF";
+				led-values = <0 0 0>;
+			};
+
+			color_red: color-red {
+				led-color = "LED_RED";
+				br-color = "EC_LED_COLOR_RED";
+				led-values = <8 0 0>;
+			};
+
+			color_green: color-green {
+				led-color = "LED_GREEN";
+				br-color = "EC_LED_COLOR_GREEN";
+				led-values = <0 16 0>;
+			};
+
+			color_blue: color-blue {
+				led-color = "LED_BLUE";
+				br-color = "EC_LED_COLOR_BLUE";
+				led-values = <0 0 8>;
+			};
+
+			color_yellow: color-yellow {
+				led-color = "LED_YELLOW";
+				br-color = "EC_LED_COLOR_YELLOW";
+				led-values = <4 5 0>;
+			};
+
+			color_white: color-white {
+				led-color = "LED_WHITE";
+				br-color = "EC_LED_COLOR_WHITE";
+				led-values = <10 10 10>;
+			};
+
+			color_amber: color-amber {
+				led-color = "LED_AMBER";
+				br-color = "EC_LED_COLOR_AMBER";
+				led-values = <9 1 0>;
+			};
+
+		};
+
+		power_led: power-led {
+			led-id = "EC_LED_ID_POWER_LED";
+			led-pwms = <&pwm_power_w>;
+
+			color_power_off: color-power-off {
+				led-color = "LED_OFF";
+				led-values = <0>;
+			};
+
+			color_power_white: color-power-white {
+				led-color = "LED_WHITE";
+				br-color = "EC_LED_COLOR_WHITE";
+				led-values = <55>;
+			};
+		};
+	};
+};
+
+/* Battery charging Blue LED */
+&pwm2 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm2_gpc4>;
+	pinctrl-names = "default";
+};
+
+/* Battery charging Red LED */
+&pwm3 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm3_gp80>;
+	pinctrl-names = "default";
+};
+
+/* Battery charging Green LED */
+&pwm4 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm4_gpb6>;
+	pinctrl-names = "default";
+};
+
+/* Finger Printer White LED */
+&pwm5 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm5_gpb7>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/framework/lotus/led_policy.dtsi b/zephyr/program/framework/lotus/led_policy.dtsi
new file mode 100644
index 0000000000..e3b9129120
--- /dev/null
+++ b/zephyr/program/framework/lotus/led_policy.dtsi
@@ -0,0 +1,97 @@
+#include <dt-bindings/battery.h>
+
+/ {
+	led-colors {
+		compatible = "cros-ec,led-policy";
+
+		power-state-charge {
+			charge-state = "LED_PWRS_CHARGE";
+			/* Battery percent range (>= 0, < 96) */
+			batt-lvl = <BATTERY_LEVEL_EMPTY 95>;
+			color-0 {
+				led-color = <&color_amber>;
+			};
+		};
+
+		power-state-charge-lvl-2 {
+			charge-state = "LED_PWRS_CHARGE";
+			/* Battery percent range (>= 96%, <= 100%) */
+			batt-lvl = <96 100>;
+
+			color-0 {
+				led-color = <&color_white>;
+			};
+		};
+
+		power-state-discharge {
+			charge-state = "LED_PWRS_DISCHARGE";
+
+			color-0 {
+				led-color = <&color_off>;
+			};
+		};
+
+		power-state-near-full {
+			charge-state = "LED_PWRS_CHARGE_NEAR_FULL";
+			/* Battery percent range (>= 97, <= 100) */
+
+			color-0 {
+				led-color = <&color_white>;
+			};
+		};
+
+		power-state-error_standalone {
+			charge-state = "LED_PWRS_ERROR";
+
+			color-0 {
+				led-color = <&color_white>;
+			};
+		};
+
+		power-state-idle {
+			charge-state = "LED_PWRS_IDLE";
+
+			color-0 {
+				led-color = <&color_white>;
+			};
+		};
+
+		power-state-forced-idle {
+			charge-state = "LED_PWRS_FORCED_IDLE";
+
+			color-0 {
+				led-color = <&color_white>;
+			};
+		};
+
+		power-state-s0 {
+			chipset-state = "POWER_S0";
+
+			color-0 {
+				led-color = <&color_power_white>;
+			};
+		};
+
+		power-state-s3 {
+			chipset-state = "POWER_S3";
+
+			color-0 {
+				led-color = <&color_power_off>;
+			};
+		};
+
+		power-state-s5 {
+			chipset-state = "POWER_S5";
+
+			color-0 {
+				led-color = <&color_power_off>;
+			};
+		};
+		
+		pwr-power-state-off {
+			color-0 {
+				led-color = <&color_power_off>;
+			};
+		};
+	};
+};
diff --git a/zephyr/program/framework/lotus/overlay.dtsi b/zephyr/program/framework/lotus/overlay.dtsi
new file mode 100644
index 0000000000..27f731badf
--- /dev/null
+++ b/zephyr/program/framework/lotus/overlay.dtsi
@@ -0,0 +1,163 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	named-gpios {
+		/* Lotus-specific GPIO customizations */
+	};
+
+	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
+		ambient-f75303 {
+			temp_host_warn = <90>;
+			temp_host_high = <90>;
+			temp_host_halt = <105>;
+			temp_host_release_warn = <60>;
+			temp_host_release_high = <60>;
+			power-good-pin = <&gpio_slp_s3_l>;
+			sensor = <&ambient_f75303>;
+		};
+		charger-f75303 {
+			temp_host_warn = <90>;
+			temp_host_high = <90>;
+			temp_host_halt = <105>;
+			temp_host_release_warn = <60>;
+			temp_host_release_high = <60>;
+			power-good-pin = <&gpio_slp_s3_l>;
+			sensor = <&charger_f75303>;
+		};
+		temp_sensor_apu: apu-f75303 {
+			temp_host_warn = <90>;
+			temp_host_high = <90>;
+			temp_host_halt = <105>;
+			temp_host_release_warn = <60>;
+			temp_host_release_high = <60>;
+			temp_fan_off = <47>;
+			temp_fan_max = <62>;
+			power-good-pin = <&gpio_slp_s3_l>;
+			sensor = <&apu_f75303>;
+		};
+		temp_sensor_apu_die: amd-apu {
+			temp_host_warn = <108>;
+			temp_host_high = <108>;
+			temp_host_halt = <127>;
+			temp_host_release_warn = <60>;
+			temp_host_release_high = <60>;
+			temp_fan_off = <65>;
+			temp_fan_max = <97>;
+			power-good-pin = <&gpio_slp_s3_l>;
+			sensor = <&temp_cpu>;
+		};
+		gpu-amb-f75303 {
+			power-good-pin = <&gpio_slp_s3_l>;
+			sensor = <&gpu_amb_f75303>;
+		};
+		temp_sensor_gpu: gpu-vr-f75303 {
+			temp_host_warn = <71>;
+			temp_host_release_warn = <60>;
+			temp_fan_off = <50>;
+			temp_fan_max = <74>;
+			power-good-pin = <&gpio_slp_s3_l>;
+			sensor = <&gpu_vr_f75303>;
+		};
+		gpu-vram-f75303 {
+			power-good-pin = <&gpio_slp_s3_l>;
+			sensor = <&gpu_vram_f75303>;
+		};
+		temp_sensor_gpu_die: gpu-amdr23m {
+			temp_fan_off = <50>;
+			temp_fan_max = <80>;
+			power-good-pin = <&gpio_slp_s3_l>;
+			sensor = <&gpu_amdr23m>;
+		};
+	};
+
+	typec-port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		/*
+		 * If the CHARGER_SINGLE_CHIP config is enabled, only
+		 * one charger chip must be defined.
+		 *
+		 * In the Zephyer OS, the CONFIG_USB_PD_PORT_MAX_COUNT will check
+		 * the device tree compatible "named-usbc-port"
+		 */
+		usbc_port0: port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+			chg = <&charger>;
+		};
+		usbc_port1: port1@1 {
+			compatible = "named-usbc-port";
+			reg = <1>;
+		};
+		usbc_port2: port2@2 {
+			compatible = "named-usbc-port";
+			reg = <2>;
+		};
+		usbc_port3: port3@3 {
+			compatible = "named-usbc-port";
+			reg = <3>;
+		};
+	};
+	named-bbram-regions {
+		compatible = "named-bbram-regions";
+		charge_limit_max {
+			offset = <0x44>;
+			size = <0x01>;
+		};
+		fp_led_level {
+			offset = <0x45>;
+			size = <0x01>;
+		};
+
+		bios_function {
+			offset = <0x47>;
+			size = <0x01>;
+		};
+		chassis_was_open {
+			offset = <0x48>;
+			size = <0x01>;
+		};
+		chassis_magic {
+			offset = <0x49>;
+			size = <0x01>;
+		};
+		chassis_total {
+			offset = <0x4a>;
+			size = <0x01>;
+		};
+		chassis_vtr_open {
+			offset = <0x4b>;
+			size = <0x01>;
+		};
+	};
+};
+
+&cros_kb_raw {
+	status = "okay";
+	pinctrl-0 = <>;
+	pinctrl-names = "default";
+};
+
+&binman {
+	ec-rw {
+		/*
+		 * Lotus uses the last 0x1000 bytes of flash for non-volatile settings storage.
+		 * Shrink the RW region by that much so that there is no conflict between RW_FWID
+		 * or RW text and non-volatile settings.
+		 */
+		size = <0x3f000>;
+		rw-fw {
+			rw-fwid {
+				offset = <(0x3f000 - 32)>;
+			};
+		};
+	};
+	/* The remaining 0x1000 bytes will be used for non-volatile settings storage. */
+	pad-after = <0x1000>;
+	pad-byte = <0xFF>;
+};
diff --git a/zephyr/program/framework/lotus/project.conf b/zephyr/program/framework/lotus/project.conf
new file mode 100644
index 0000000000..eb7016c901
--- /dev/null
+++ b/zephyr/program/framework/lotus/project.conf
@@ -0,0 +1,46 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_BOARD_LOTUS=y
+
+CONFIG_PLATFORM_EC_GPU=y
+
+# Customized
+CONFIG_PLATFORM_EC_CDECK_POWER_CONTROL=y
+CONFIG_PLATFORM_EC_GPU_POWER_CONTROL=y
+
+# Fan
+CONFIG_PLATFORM_EC_NUM_FANS=2
+CONFIG_PLATFORM_EC_CUSTOM_FAN_DUTY_CONTROL=y
+CONFIG_PLATFORM_EC_CUSTOM_FAN_CONTROL=y
+
+#TypeC support
+CONFIG_PLATFORM_EC_USBC=n
+CONFIG_PLATFORM_EC_USB_POWER_DELIVERY=n
+CONFIG_PLATFORM_EC_USB_PD_DISCHARGE=n
+
+# Charger
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=5
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=5
+CONFIG_PLATFORM_EC_CHARGER_DEFAULT_CURRENT_LIMIT=500
+CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON=55000
+CONFIG_PLATFORM_EC_CHARGER_BYPASS_MODE=y
+CONFIG_PLATFORM_EC_CHARGER_BYPASS_REVERSE_TURBO=y
+CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC_CUSTOM=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_NOT_PRESENT=y
+CONFIG_PLATFORM_EC_CHARGER_MAINTAIN_VBAT=y
+#CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_BY_BOARD=y TODO add INA vbus measurements
+# Keyboard
+CONFIG_PLATFORM_EC_KEYBOARD=n
+CONFIG_ESPI_PERIPHERAL_8042_KBC=n
+
+# Thermal
+CONFIG_PLATFORM_EC_TEMP_SENSOR_F75303=n
+CONFIG_PLATFORM_EC_FAN_RPM_CUSTOM=y
+
+
+# INA2XX
+CONFIG_PLATFORM_EC_INA2XX=y
+CONFIG_PLATFORM_EC_INA236=y
+
diff --git a/zephyr/program/framework/lotus/project.overlay b/zephyr/program/framework/lotus/project.overlay
new file mode 100644
index 0000000000..d3b436e935
--- /dev/null
+++ b/zephyr/program/framework/lotus/project.overlay
@@ -0,0 +1,14 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc.dtsi"
+#include "battery.dtsi"
+#include "fan.dtsi"
+#include "gpio.dtsi"
+#include "i2c.dtsi"
+#include "interrupts.dtsi"
+#include "led_pins.dtsi"
+#include "led_policy.dtsi"
+#include "overlay.dtsi"
diff --git a/zephyr/program/framework/lotus/src/amd_r23m.c b/zephyr/program/framework/lotus/src/amd_r23m.c
new file mode 100644
index 0000000000..6bc832b1df
--- /dev/null
+++ b/zephyr/program/framework/lotus/src/amd_r23m.c
@@ -0,0 +1,150 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* AMD R23M temperature sensor module for Chrome EC */
+
+#include "board_host_command.h"
+#include "customized_shared_memory.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "gpu.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "lotus/amd_r23m.h"
+#include "power.h"
+#include "temp_sensor/temp_sensor.h"
+#include "util.h"
+
+
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_THERMAL, format, ##args)
+
+/* GPU I2C address */
+#define GPU_ADDR_FLAGS 0x0040
+
+#define GPU_INIT_OFFSET 0x01
+#define GPU_TEMPERATURE_OFFSET 0x03
+
+static int initialized;
+static int temps[AMDR23M_COUNT];
+/*
+ * Tell SMBus we want to read 4 Byte from register offset(0x01665A)
+ */
+static uint8_t gpu_init_write_value[5] = {
+	0x04, 0x0F, 0x01, 0x66, 0x93,
+};
+
+/**
+ * Read block register from temp sensor.
+ */
+static int raw_writeblock(int sensor, int offset, uint8_t *data, int len)
+{
+	return i2c_write_block(amdr23m_sensors[sensor].i2c_port,
+			 amdr23m_sensors[sensor].i2c_addr_flags, offset, data, len);
+}
+
+static int raw_readblock(int sensor, int offset, uint8_t *data, int len)
+{
+	return i2c_read_block(amdr23m_sensors[sensor].i2c_port,
+			 amdr23m_sensors[sensor].i2c_addr_flags, offset, data, len);
+}
+
+static void gpu_init_temp_sensor(int idx)
+{
+	int rv;
+
+	rv = raw_writeblock(idx, GPU_INIT_OFFSET, gpu_init_write_value,
+				ARRAY_SIZE(gpu_init_write_value));
+
+	if (rv == EC_SUCCESS) {
+		initialized = 1;
+		return;
+	}
+	CPRINTS("init GPU fail: %d", rv);
+}
+
+int amdr23m_get_val_k(int idx, int *temp)
+{
+	if (idx < 0 || AMDR23M_COUNT <= idx)
+		return EC_ERROR_INVAL;
+
+	*temp = temps[idx];
+	return EC_SUCCESS;
+}
+
+int amd_dgpu_delay(void)
+{
+	if (*host_get_memmap(EC_CUSTOMIZED_MEMMAP_SYSTEM_FLAGS) & ACPI_DRIVER_READY)
+		return true;
+	else
+		return false;
+}
+
+/* INIT GPU first before read the GPU's die tmeperature. */
+void amdr23m_update_temperature(int idx)
+{
+	uint8_t reg[5];
+	int rv;
+
+
+	/*
+	 * if not detect GPU should not send I2C.
+	 */
+	if (!gpu_present() || !gpu_power_enable()) {
+		temps[idx] = C_TO_K(0);
+		initialized = 0;
+		return;
+	}
+
+	/*
+	 * We shouldn't read the GPU temperature when the state
+	 * is not in S0, because GPU is enabled in S0.
+	 */
+	if (!chipset_in_state(CHIPSET_STATE_ON)) {
+		temps[idx] = C_TO_K(0);
+		return;
+	}
+
+	if (!amd_dgpu_delay()) {
+		return;
+	}
+
+	if (!initialized) {
+		gpu_init_temp_sensor(idx);
+		temps[idx] = C_TO_K(0);
+		return;
+	}
+
+	rv = raw_readblock(idx, GPU_TEMPERATURE_OFFSET, reg, ARRAY_SIZE(reg));
+
+	if (rv) {
+		CPRINTS("read GPU Temperature fail");
+		temps[idx] = C_TO_K(0);
+		return;
+	}
+	/*
+	 * The register is four bytes, bit[17:9] represents the GPU temperature.
+	 * 0x000 : 0	ﾟC
+	 * 0x001 : 1	ﾟC
+	 * 0x002 : 2	ﾟC
+	 * ...
+	 * 0x1FF : 511	ﾟC
+	 * -------------------------------
+	 * reg[4] = bit0  - bit7
+	 * reg[3] = bit8  - bit15
+	 * reg[2] = bit16 - bit23
+	 * reg[1] = bit24 - bit31
+	 * reg[0] = 0x04
+	 */
+	temps[idx] = C_TO_K(reg[3] >> 1);
+}
+
+void reset_gpu(void)
+{
+	initialized = 0;
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESET, reset_gpu, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, reset_gpu, HOOK_PRIO_DEFAULT);
diff --git a/zephyr/program/framework/lotus/src/battery.c b/zephyr/program/framework/lotus/src/battery.c
new file mode 100644
index 0000000000..b8517e9008
--- /dev/null
+++ b/zephyr/program/framework/lotus/src/battery.c
@@ -0,0 +1,364 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include <zephyr/drivers/gpio.h>
+
+
+#include "battery.h"
+#include "battery_smart.h"
+#include "battery_fuel_gauge.h"
+#include "board_adc.h"
+#include "board_charger.h"
+#include "board_function.h"
+#include "board_host_command.h"
+#include "charger.h"
+#include "charge_state.h"
+#include "charge_manager.h"
+#include "cypress_pd_common.h"
+#include "common_cpu_power.h"
+#include "console.h"
+#include "customized_shared_memory.h"
+#include "hooks.h"
+#include "system.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+
+#define CACHE_INVALIDATION_TIME_US (3 * SECOND)
+
+static int battery_current_array[4];
+static int old_btp;
+static int power_on_check_batt;
+
+/* check battery timer */
+K_TIMER_DEFINE(check_battery_timer, NULL, NULL);
+
+enum battery_present battery_is_present(void)
+{
+	static enum battery_present batt_pres = BP_NOT_SURE;
+	char text[32];
+	static int retry;
+
+	/* timer expired, return no battery */
+	if (k_timer_status_get(&check_battery_timer) > 0) {
+		CPRINTS("check battery timeout, stop precharge!");
+		power_on_check_batt = 0;
+		return BP_NO;
+	}
+
+	/* check the battery present pin first */
+	if (board_get_version() >= BOARD_VERSION_7) {
+		if (board_get_version() == BOARD_VERSION_7) {
+			if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_battery_present)) == 1) {
+				k_timer_stop(&check_battery_timer);
+				power_on_check_batt = 0;
+				return BP_YES;
+			}
+		} else {
+			/* DVT2 changes to low active */
+			if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_battery_present)) == 0) {
+				k_timer_stop(&check_battery_timer);
+				power_on_check_batt = 0;
+				return BP_YES;
+			}
+		}
+	}
+
+	/* try to read the battery information */
+	if (battery_device_name(text, sizeof(text))) {
+		/* add the retry if read the bad respond */
+		if (retry++ > 3 && !power_on_check_batt) {
+			batt_pres = BP_NO;
+			retry = 0;
+		}
+	} else {
+		k_timer_stop(&check_battery_timer);
+		power_on_check_batt = 0;
+		batt_pres = BP_YES;
+		retry = 0;
+	}
+
+	return batt_pres;
+}
+
+static void enable_check_battery_timer(void)
+{
+	/* start the timer */
+	power_on_check_batt = 1;
+	k_timer_start(&check_battery_timer, K_SECONDS(30), K_NO_WAIT);
+}
+DECLARE_HOOK(HOOK_INIT, enable_check_battery_timer, HOOK_PRIO_DEFAULT);
+
+uint32_t get_system_percentage(void)
+{
+	static uint32_t pre_os_percentage;
+	uint32_t memmap_cap = *(uint32_t *)host_get_memmap(EC_MEMMAP_BATT_CAP);
+	uint32_t memmap_lfcc = *(uint32_t *)host_get_memmap(EC_MEMMAP_BATT_LFCC);
+	uint32_t os_percentage = 1000 * memmap_cap / (memmap_lfcc + 1);
+
+	/* ensure this value is valid */
+	if (os_percentage <= 1000 && os_percentage >= 0) {
+		pre_os_percentage = os_percentage;
+		return os_percentage;
+	} else
+		return pre_os_percentage;
+}
+
+int get_average_battery_current(void)
+{
+	int idx;
+	int average_battery_current = 0;
+
+	for (idx = 0; idx < 4; idx++)
+		average_battery_current += battery_current_array[idx];
+
+	return (average_battery_current / 4);
+}
+
+void battery_customize(struct charge_state_data *curr_batt)
+{
+	char text[32];
+	char *str = "LION";
+	int value;
+	int new_btp;
+	int rv;
+	static int batt_state;
+	static int read_manuf_date;
+	static int idx;
+	int day = 0;
+	int month = 0;
+	int year = 0;
+	uint32_t batt_os_percentage = get_system_percentage();
+
+	/* manufacture date is static data */
+	if (!read_manuf_date && battery_is_present() == BP_YES) {
+		rv = battery_manufacture_date(&year, &month, &day);
+		if (rv == EC_SUCCESS) {
+			ccprintf("Batt manufacturer date: %d.%d.%d\n", year, month, day);
+			*host_get_memmap(EC_CUSTOMIZED_MEMMAP_BATT_MANUF_DAY) = day;
+			*host_get_memmap(EC_CUSTOMIZED_MEMMAP_BATT_MANUF_MONTH) = month;
+			*host_get_memmap(EC_CUSTOMIZED_MEMMAP_BATT_MANUF_YEAR) =
+				year & 0xff;
+			*host_get_memmap(EC_CUSTOMIZED_MEMMAP_BATT_MANUF_YEAR + 1) =
+				year >> 8;
+			read_manuf_date = 1;
+		}
+	} else if (!battery_is_present()) {
+		/**
+		 * if battery isn't present, we need to read manufacture
+		 * date after battery is connect
+		 */
+		read_manuf_date = 0;
+	}
+
+	*host_get_memmap(EC_CUSTOMIZED_MEMMAP_BATT_AVER_TEMP) =
+					(curr_batt->batt.temperature - 2731) / 10;
+	*host_get_memmap(EC_CUSTOMIZED_MEMMAP_BATT_PERCENTAGE) =
+					batt_os_percentage / 10;
+
+	if (curr_batt->batt.status & STATUS_FULLY_CHARGED)
+		*host_get_memmap(EC_CUSTOMIZED_MEMMAP_BATT_STATUS) |= EC_BATT_FLAG_FULL;
+	else
+		*host_get_memmap(EC_CUSTOMIZED_MEMMAP_BATT_STATUS) &= ~EC_BATT_FLAG_FULL;
+
+	battery_device_chemistry(text, sizeof(text));
+	if (!strncmp(text, str, 4))
+		*host_get_memmap(EC_CUSTOMIZED_MEMMAP_BATT_STATUS) |= EC_BATT_TYPE;
+	else
+		*host_get_memmap(EC_CUSTOMIZED_MEMMAP_BATT_STATUS) &= ~EC_BATT_TYPE;
+
+	battery_get_mode(&value);
+	/* in framework use smart.c it will force in mAh mode*/
+	if (value & MODE_CAPACITY)
+		*host_get_memmap(EC_CUSTOMIZED_MEMMAP_BATT_STATUS) &= ~EC_BATT_MODE;
+	else
+		*host_get_memmap(EC_CUSTOMIZED_MEMMAP_BATT_STATUS) |= EC_BATT_MODE;
+
+	/* BTP: Notify AP update battery */
+	new_btp = *host_get_memmap(EC_CUSTOMIZED_MEMMAP_BATT_TRIP_POINT) +
+			(*host_get_memmap(EC_CUSTOMIZED_MEMMAP_BATT_TRIP_POINT+1) << 8);
+
+	if (!(curr_batt->batt.flags & BATT_FLAG_BAD_REMAINING_CAPACITY)) {
+
+		if (old_btp == 0 || old_btp == new_btp)
+			old_btp = curr_batt->batt.remaining_capacity;
+
+		if (new_btp == 0 && batt_os_percentage < 995)
+			host_set_single_event(EC_HOST_EVENT_BATT_BTP);
+
+		if (new_btp > old_btp && !battery_is_cut_off()) {
+			if (curr_batt->batt.remaining_capacity > new_btp) {
+				old_btp = new_btp;
+				host_set_single_event(EC_HOST_EVENT_BATT_BTP);
+			}
+		} else if (new_btp < old_btp && !battery_is_cut_off()) {
+			if (curr_batt->batt.remaining_capacity < new_btp) {
+				old_btp = new_btp;
+				host_set_single_event(EC_HOST_EVENT_BATT_BTP);
+			}
+		}
+	}
+
+	/*
+	 * When the battery present have change notify AP
+	 */
+	if (batt_state != curr_batt->batt.is_present) {
+		host_set_single_event(EC_HOST_EVENT_BATTERY);
+		batt_state = curr_batt->batt.is_present;
+	}
+
+	/* Put the battery current in the array for safety funciton */
+	battery_current_array[idx++] = curr_batt->batt.current;
+	if (idx >= 4)
+		idx = 0;
+}
+
+static void fix_single_param(int flag, int *cached, int *curr)
+{
+	if (flag)
+		*curr = *cached;
+	else
+		*cached = *curr;
+}
+
+/*
+ * If any value in batt_params is bad, replace it with a cached
+ * good value, to make sure we never send random numbers to ap
+ * side.
+ */
+__override void board_battery_compensate_params(struct batt_params *batt)
+{
+	static struct batt_params batt_cache = { 0 };
+	static timestamp_t deadline;
+
+	/*
+	 * If battery keeps failing for 3 seconds, stop hiding the error and
+	 * report back to host.
+	 */
+
+	if (batt->flags & BATT_FLAG_RESPONSIVE) {
+		if (batt->flags & BATT_FLAG_BAD_ANY) {
+			if (timestamp_expired(deadline, NULL))
+				return;
+		} else
+			deadline.val = get_time().val + CACHE_INVALIDATION_TIME_US;
+	} else if (!(batt->flags & BATT_FLAG_RESPONSIVE)) {
+		/**
+		 * There are 4 situations for battery is not repsonsed
+		 * 1. Darin battery (first time)
+		 * 2. Dead battery (first time)
+		 * 3. No battery (is preset)
+		 * 4. Others
+		 */
+		/* we don't need to cache the value when battery is not present */
+		if (!batt->is_present) {
+			batt_cache.flags &= ~BATT_FLAG_RESPONSIVE;
+			return;
+		}
+
+		/* we don't need to cache the value when we read the battery first time */
+		if (!(batt_cache.flags & BATT_FLAG_RESPONSIVE))
+			return;
+
+		/**
+		 * If battery keeps no responsing for 3 seconds, stop hiding the error and
+		 * back to host.
+		 */
+		if (timestamp_expired(deadline, NULL)) {
+			batt_cache.flags &= ~BATT_FLAG_RESPONSIVE;
+			return;
+		}
+	}
+
+	/* return cached values for at most CACHE_INVALIDATION_TIME_US */
+	fix_single_param(batt->flags & BATT_FLAG_BAD_STATE_OF_CHARGE,
+			&batt_cache.state_of_charge,
+			&batt->state_of_charge);
+	fix_single_param(batt->flags & BATT_FLAG_BAD_VOLTAGE,
+			&batt_cache.voltage,
+			&batt->voltage);
+	fix_single_param(batt->flags & BATT_FLAG_BAD_CURRENT,
+			&batt_cache.current,
+			&batt->current);
+	fix_single_param(batt->flags & BATT_FLAG_BAD_DESIRED_VOLTAGE,
+			&batt_cache.desired_voltage,
+			&batt->desired_voltage);
+	fix_single_param(batt->flags & BATT_FLAG_BAD_DESIRED_CURRENT,
+			&batt_cache.desired_current,
+			&batt->desired_current);
+	fix_single_param(batt->flags & BATT_FLAG_BAD_REMAINING_CAPACITY,
+			&batt_cache.remaining_capacity,
+			&batt->remaining_capacity);
+	fix_single_param(batt->flags & BATT_FLAG_BAD_FULL_CAPACITY,
+			&batt_cache.full_capacity,
+			&batt->full_capacity);
+	fix_single_param(batt->flags & BATT_FLAG_BAD_STATUS,
+			&batt_cache.status,
+			&batt->status);
+	fix_single_param(batt->flags & BATT_FLAG_BAD_TEMPERATURE,
+			&batt_cache.temperature,
+			&batt->temperature);
+	/*
+	 * If battery_compensate_params() didn't calculate display_charge
+	 * for us, also update it with last good value.
+	 */
+	fix_single_param(batt->display_charge == 0,
+			&batt_cache.display_charge,
+			&batt->display_charge);
+
+	/* remove bad flags after applying cached values */
+	batt->flags &= ~BATT_FLAG_BAD_ANY;
+	batt->flags |= BATT_FLAG_RESPONSIVE;
+	batt_cache.flags |= BATT_FLAG_RESPONSIVE;
+
+	/* override the display charge value for Windows system */
+	batt->display_charge = get_system_percentage();
+}
+
+void board_cut_off(void)
+{
+	const struct board_batt_params *params = get_batt_params();
+	int rv;
+
+	/* If battery is unknown can't send ship mode command */
+	if (!params) {
+		CPRINTS("Battery unknown cutoff failed");
+		return;
+	}
+
+	/* update charger setting to avoid B+ voltage wake up the battery */
+	if (update_charger_in_cutoff_mode()) {
+		CPRINTS("Update chg fail before cutoff");
+		return;
+	}
+
+	/* Ship mode command requires writing 2 data values */
+	rv = sb_write(params->fuel_gauge.ship_mode.reg_addr,
+		params->fuel_gauge.ship_mode.reg_data[0]);
+	rv |= sb_write(params->fuel_gauge.ship_mode.reg_addr,
+		params->fuel_gauge.ship_mode.reg_data[1]);
+
+	if (rv == EC_RES_SUCCESS) {
+		CPRINTS("Battery cutoff is successful");
+		set_battery_in_cut_off();
+	} else {
+		CPRINTS("Battery cutoff has failed");
+	}
+}
+DECLARE_DEFERRED(board_cut_off);
+
+__override int board_cut_off_battery(void)
+{
+	int power_uw = charge_manager_get_power_limit_uw();
+
+	if (power_uw <= 100000000) {
+		hook_call_deferred(&board_cut_off_data, 0);
+	} else {
+		exit_epr_mode();
+		hook_call_deferred(&board_cut_off_data, 700*MSEC);
+	}
+
+	return EC_RES_ERROR;
+}
diff --git a/zephyr/program/framework/lotus/src/board_configuratin.c b/zephyr/program/framework/lotus/src/board_configuratin.c
new file mode 100644
index 0000000000..e3cda58960
--- /dev/null
+++ b/zephyr/program/framework/lotus/src/board_configuratin.c
@@ -0,0 +1,10 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include <zephyr/drivers/gpio.h>
+
+#include "board_adc.h"
+
+
+
diff --git a/zephyr/program/framework/lotus/src/charger.c b/zephyr/program/framework/lotus/src/charger.c
new file mode 100644
index 0000000000..7df6a18db3
--- /dev/null
+++ b/zephyr/program/framework/lotus/src/charger.c
@@ -0,0 +1,629 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include <zephyr/drivers/gpio.h>
+
+#include "battery.h"
+#include "battery_fuel_gauge.h"
+#include "board_adc.h"
+#include "board_charger.h"
+#include "charger.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "chipset.h"
+#include "common.h"
+#include "common_cpu_power.h"
+#include "console.h"
+#include "cypress_pd_common.h"
+#include "driver/charger/isl9241.h"
+#include "driver/ina2xx.h"
+#include "extpower.h"
+#include "gpu.h"
+#include "gpio.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "math_util.h"
+#include "power.h"
+#include "system.h"
+#include "throttle_ap.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
+
+static int last_extpower_present;
+
+#ifdef CONFIG_PLATFORM_EC_CHARGER_INIT_CUSTOM
+static void charger_chips_init(void);
+static void charger_chips_init_retry(void)
+{
+	charger_chips_init();
+}
+DECLARE_DEFERRED(charger_chips_init_retry);
+
+static void board_check_current(void);
+DECLARE_DEFERRED(board_check_current);
+
+void ina236_alert_current(int voltage, int current)
+{
+	int value, rv, watt;
+
+	watt = (int64_t)current * (int64_t)voltage / 1000000;
+
+	if (watt == 180)
+		value = current * 4 * 12 / 10;
+	else
+		value = current * 4;
+
+	rv = ina2xx_write(0, INA2XX_REG_ALERT, value);
+
+	if (rv != EC_SUCCESS)
+		CPRINTS("ina236 write alert fail");
+}
+
+static void board_ina236_init(void)
+{
+	int rv;
+
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_ina236_alert));
+
+	/* TODO(crosbug.com/p/29730): assume 1mA/LSB, revisit later */
+	rv = ina2xx_write(0, INA2XX_REG_CALIB, 0x0831);
+
+	if (rv != EC_SUCCESS)
+		CPRINTS("ina236 write calib fail");
+
+	rv = ina2xx_write(0, INA2XX_REG_CONFIG, 0x4027);
+
+	if (rv != EC_SUCCESS)
+		CPRINTS("ina236 write config fail");
+
+	rv = ina2xx_write(0, INA2XX_REG_ALERT, 0x5DC0);
+
+	if (rv != EC_SUCCESS)
+		CPRINTS("ina236 write alert fail");
+
+	rv = ina2xx_write(0, INA2XX_REG_MASK, 0x8009);
+
+	if (rv != EC_SUCCESS)
+		CPRINTS("ina236 write mask fail");
+
+}
+
+static void ina236_alert_release(void)
+{
+	int rv;
+
+	rv = ina2xx_read(0, INA2XX_REG_MASK);
+
+	if (rv == 0x0bad)
+		CPRINTS("ina236 read mask fail");
+
+}
+DECLARE_DEFERRED(ina236_alert_release);
+
+void ina236_alert_interrupt(void)
+{
+	hook_call_deferred(&ina236_alert_release_data, 6 * MSEC);
+}
+
+static void charge_gate_onoff(bool status)
+{
+	if (status) {
+		/* Clear Control0 register bit 12; NGATE on */
+		i2c_update16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS, ISL9241_REG_CONTROL0,
+			ISL9241_CONTROL0_NGATE_OFF, MASK_CLR);
+
+		/* Clear Control1 register bit 6; BGATE on */
+		i2c_update16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS, ISL9241_REG_CONTROL1,
+			ISL9241_CONTROL1_BGATE_OFF, MASK_CLR);
+
+	} else {
+		/* Set Control0 register bit 12; NGATE off */
+		i2c_update16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS, ISL9241_REG_CONTROL0,
+			ISL9241_CONTROL0_NGATE_OFF, MASK_SET);
+
+		/* Set Control1 register bit 6; BGATE off */
+		i2c_update16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS, ISL9241_REG_CONTROL1,
+			ISL9241_CONTROL1_BGATE_OFF, MASK_SET);
+	}
+}
+
+static  void charger_psys_enable(bool status)
+{
+	if (status) {
+
+		i2c_write16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+			ISL9241_REG_ACOK_REFERENCE, ISL9241_MV_TO_ACOK_REFERENCE(4000));
+
+		/* Clear Control1 register bit 5; Enable IMON */
+		i2c_update16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS, ISL9241_REG_CONTROL1,
+			ISL9241_CONTROL1_IMON, MASK_CLR);
+
+		/* Clear Control4 register bit 12; Enable all mode */
+		i2c_update16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS, ISL9241_REG_CONTROL4,
+			ISL9241_CONTROL4_GP_COMPARATOR, MASK_CLR);
+
+	} else {
+
+		i2c_write16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+			ISL9241_REG_ACOK_REFERENCE, ISL9241_MV_TO_ACOK_REFERENCE(0));
+
+		/* Set Control1 register bit 5; Disable IMON */
+		i2c_update16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS, ISL9241_REG_CONTROL1,
+			ISL9241_CONTROL1_IMON, MASK_SET);
+
+		/* Set Control4 register bit 12; Disable for battery only mode */
+		i2c_update16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS, ISL9241_REG_CONTROL4,
+			ISL9241_CONTROL4_GP_COMPARATOR, MASK_SET);
+	}
+}
+
+void charger_input_current_limit_control(void)
+{
+	int acin = gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_hw_acav_in));
+
+	if (battery_cutoff_in_progress() || battery_is_cut_off())
+		return;
+
+	if (acin && (battery_is_present() != BP_YES)) {
+		/* Set Control3 register bit 5; */
+		i2c_update16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS, ISL9241_REG_CONTROL3,
+			ISL9241_CONTROL3_INPUT_CURRENT_LIMIT, MASK_SET);
+	} else {
+		/* Clear Control3 register bit 5; */
+		i2c_update16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS, ISL9241_REG_CONTROL3,
+			ISL9241_CONTROL3_INPUT_CURRENT_LIMIT, MASK_CLR);
+	}
+}
+
+void board_charger_lpm_control(int enable)
+{
+	if (battery_cutoff_in_progress() || battery_is_cut_off())
+		return;
+
+	charger_psys_enable(enable);
+}
+
+__override void board_hibernate(void)
+{
+	/* for i2c analyze, re-write again */
+	board_charger_lpm_control(0);
+	charge_gate_onoff(false);
+
+}
+
+int update_charger_in_cutoff_mode(void)
+{
+	/* Turn off the charger NGATE */
+	if (i2c_write16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+			ISL9241_REG_CONTROL0, (ISL9241_CONTROL0_NGATE_OFF |
+			ISL9241_CONTROL0_BGATE_FORCE_ON)))
+		return EC_ERROR_UNKNOWN;
+
+	if (i2c_write16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+			ISL9241_REG_CONTROL3, (ISL9241_CONTROL3_ACLIM_RELOAD |
+			ISL9241_CONTROL3_BATGONE)))
+		return EC_ERROR_UNKNOWN;
+
+	return EC_SUCCESS;
+}
+
+static void charger_chips_init(void)
+{
+	uint16_t val = 0x0000; /* default ac setting */
+	uint32_t data = 0;
+	int value;
+
+	const struct battery_info *bi = battery_get_info();
+
+	/*
+	 * In our case the EC can boot before the charger has power so
+	 * check if the charger is responsive before we try to init it
+	 */
+	if (i2c_read16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+		ISL9241_REG_ACOK_REFERENCE, &data) != EC_SUCCESS) {
+		CPRINTS("Retry Charger init");
+		hook_call_deferred(&charger_chips_init_retry_data, 100*MSEC);
+		return;
+	}
+
+	if (i2c_write16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+		ISL9241_REG_CONTROL4, ISL9241_CONTROL4_WOCP_FUNCTION |
+		ISL9241_CONTROL4_VSYS_SHORT_CHECK |
+		ISL9241_CONTROL4_ACOK_BATGONE_DEBOUNCE_25US))
+		goto init_fail;
+
+	if (i2c_write16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+		ISL9241_REG_CONTROL3,
+		(ISL9241_CONTROL3_ACLIM_RELOAD | ISL9241_CONTROL3_BATGONE)))
+		goto init_fail;
+
+	if (i2c_write16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+		ISL9241_REG_OTG_VOLTAGE, 0x0000))
+		goto init_fail;
+
+	if (i2c_write16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+		ISL9241_REG_OTG_CURRENT, 0x0000))
+		goto init_fail;
+
+	value = battery_is_charge_fet_disabled();
+
+	/* reverse the flag if no error */
+	if (value != -1)
+		value = !value;
+
+	/* According to Power team suggest, Set ACOK reference to 4.500V */
+	if (i2c_write16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+		ISL9241_REG_ACOK_REFERENCE, ISL9241_MV_TO_ACOK_REFERENCE(4500)))
+		goto init_fail;
+
+	/*
+	 * Set the MaxSystemVoltage to battery maximum,
+	 * 0x00=disables switching charger states
+	 */
+	if (i2c_write16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+		ISL9241_REG_MAX_SYSTEM_VOLTAGE, bi->voltage_max))
+		goto init_fail;
+
+	/*
+	 * Set the MinSystemVoltage to battery minimum,
+	 * 0x00=disables all battery charging
+	 */
+	if (i2c_write16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+		ISL9241_REG_MIN_SYSTEM_VOLTAGE, bi->voltage_min))
+		goto init_fail;
+
+	if (i2c_write16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+		ISL9241_REG_CONTROL2,
+		ISL9241_CONTROL2_TRICKLE_CHG_CURR(bi->precharge_current) |
+		ISL9241_CONTROL2_GENERAL_PURPOSE_COMPARATOR |
+		ISL9241_CONTROL2_PROCHOT_DEBOUNCE_500))
+		goto init_fail;
+
+	if (i2c_write16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+		ISL9241_REG_CONTROL0, 0x0000))
+		goto init_fail;
+
+	val = ISL9241_CONTROL1_PROCHOT_REF_6000;
+	val |= ((ISL9241_CONTROL1_SWITCHING_FREQ_656KHZ << 7) &
+			ISL9241_CONTROL1_SWITCHING_FREQ_MASK);
+
+	if (i2c_write16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
+		ISL9241_REG_CONTROL1, val))
+		goto init_fail;
+
+	board_charger_lpm_control(0);
+
+	/* TODO: should we need to talk to PD chip after initial complete ? */
+	hook_call_deferred(&board_check_current_data, 10*MSEC);
+	CPRINTS("ISL9241 customized initial complete!");
+
+	/* Initial the INA236 */
+	board_ina236_init();
+
+	return;
+
+init_fail:
+	CPRINTF("ISL9241 customized initial failed!");
+}
+DECLARE_HOOK(HOOK_INIT, charger_chips_init, HOOK_PRIO_POST_I2C + 1);
+#endif
+
+void charger_update(void)
+{
+	static int pre_ac_state;
+	static int pre_dc_state;
+
+	if (pre_ac_state != extpower_is_present() ||
+		pre_dc_state != battery_is_present()) {
+		CPRINTS("update charger!!");
+
+		i2c_update16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS, ISL9241_REG_CONTROL1,
+				(ISL9241_CONTROL1_SWITCHING_FREQ_656KHZ << 7), MASK_SET);
+
+		/**
+		 * Update the DC prochot current limit
+		 * EVT: DC prochot value = 6820 mA / (10 / 3) = 2130 mA (0x800)
+		 * DVT: DC prochot value = 13000 mA / (10 / 5) = 6500 mA (0x1d00)
+		 */
+		if (isl9241_set_dc_prochot(0,
+			(board_get_version() < BOARD_VERSION_7) ? 0x800 : 0x1d00))
+			CPRINTS("Update DC prochot fail");
+
+		pre_ac_state = extpower_is_present();
+		pre_dc_state = battery_is_present();
+
+		charger_input_current_limit_control();
+	}
+}
+DECLARE_HOOK(HOOK_AC_CHANGE, charger_update, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, charger_update, HOOK_PRIO_DEFAULT);
+
+static bool bypass_force_en;
+static bool bypass_force_disable;
+
+static int bypass_force_disable_oneshot;
+void board_disable_bypass_oneshot(void)
+{
+	bypass_force_disable_oneshot = 2;
+}
+__override int board_should_charger_bypass(void)
+{
+	int power_uw = charge_manager_get_power_limit_uw();
+	int voltage_mv = charge_manager_get_charger_voltage();
+	int curr_batt = battery_is_present();
+	int ret;
+	const char * reason = "";
+	if (bypass_force_en) {
+		ret = true;
+		reason = "forcen";
+		goto board_exit;
+	}
+
+	if (bypass_force_disable){
+		ret = false;
+		reason = "forcedis";
+		goto board_exit;
+	}
+
+	if (bypass_force_disable_oneshot) {
+		bypass_force_disable_oneshot--;
+		ret = false;
+		reason = "oneshot";
+		goto board_exit;
+	}
+
+	if (curr_batt == BP_YES) {
+		if (power_uw > 100000000) {
+			ret = true;
+			reason = "power";
+			goto board_exit;
+		} else {
+			ret = false;
+			goto board_exit;
+		}
+	} else {
+		if (voltage_mv > 20000){
+			ret = true;
+			reason = "volt";
+			goto board_exit;
+		} else {
+			ret = false;
+			goto board_exit;
+		}
+	}
+board_exit:
+	/* CPRINTS("board_should_charger_bypass %s %d", reason, ret); */
+
+	return ret;
+}
+
+int board_want_change_mode(void)
+{
+	static int pre_batt = BP_YES;
+	int curr_batt = battery_is_present();
+
+	if (pre_batt != curr_batt) {
+		pre_batt = curr_batt;
+		return true;
+	} else
+		return false;
+}
+
+int board_discharge_on_ac(int enable)
+{
+	int chgnum;
+	int rv = EC_SUCCESS;
+
+	bypass_force_disable = enable;
+	/*
+	 * When discharge on AC is selected, cycle through all chargers to
+	 * enable or disable this feature.
+	 */
+	for (chgnum = 0; chgnum < board_get_charger_chip_count(); chgnum++)
+		if (chg_chips[chgnum].drv->discharge_on_ac)
+			rv = chg_chips[chgnum].drv->discharge_on_ac(chgnum, enable);
+	return rv;
+}
+
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+			    int max_ma, int charge_mv)
+{
+	int prochot_ma;
+	int64_t calculate_ma;
+
+	if (charge_ma < CONFIG_PLATFORM_EC_CHARGER_DEFAULT_CURRENT_LIMIT) {
+		charge_ma = CONFIG_PLATFORM_EC_CHARGER_DEFAULT_CURRENT_LIMIT;
+	}
+
+	/* Handle EPR converstion through the buck switcher */
+	if (charge_mv > 20000) {
+		/**
+		 * (charge_ma * charge_mv / 20000 ) * 0.9 * 0.94
+		 */
+		calculate_ma = (int64_t)charge_ma * (int64_t)charge_mv * 90 * 95 / 200000000;
+	} else {
+		calculate_ma = (int64_t)charge_ma * 88 / 100;
+	}
+
+	CPRINTS("Updating charger with EPR correction: ma %d", (int16_t)calculate_ma);
+
+	prochot_ma = (DIV_ROUND_UP(((int)calculate_ma * 200 / 100), 855) * 855);
+
+	if ((prochot_ma - (int)calculate_ma) < 853) {
+		/* We need prochot to be at least 1 LSB above
+		 * the input current limit. This is not ideal
+		 * due to the low accuracy on prochot.
+		 */
+		prochot_ma += 853;
+	}
+
+	ina236_alert_current(charge_mv, charge_ma);
+
+	charge_set_input_current_limit((int)calculate_ma, charge_mv);
+	/* sync-up ac prochot with current change */
+	isl9241_set_ac_prochot(0, prochot_ma);
+}
+
+bool log_ina236;
+void board_check_current(void)
+{
+	int16_t sv = ina2xx_read(0, INA2XX_REG_SHUNT_VOLT);
+	static int curr_status = EC_DEASSERTED_PROCHOT;
+	static int pre_status = EC_DEASSERTED_PROCHOT;
+	static int active_port;
+	static int active_current;
+	static int pre_active_port;
+	static int shunt_register;
+
+	active_port = charge_manager_get_active_charge_port();
+	active_current = pd_get_active_current(active_port);
+
+	if (active_port == CHARGE_PORT_NONE || !extpower_is_present()) {
+		if (pre_active_port != active_port) {
+			curr_status = EC_DEASSERTED_PROCHOT;
+			throttle_ap(THROTTLE_OFF, THROTTLE_HARD, THROTTLE_SRC_AC);
+
+			pre_status = curr_status;
+			pre_active_port = active_port;
+		}
+		hook_call_deferred(&board_check_current_data, 100 * MSEC);
+		return;
+	}
+
+	if (board_get_version() >= BOARD_VERSION_7)
+		shunt_register = 10;
+	else
+		shunt_register = 5;
+
+	if (log_ina236) {
+		CPRINTS("INA236 %d mA %d mV", INA2XX_SHUNT_UV(sv) / shunt_register,
+				INA2XX_BUS_MV((int)ina2xx_read(0, INA2XX_REG_BUS_VOLT)));
+	}
+
+	if (ABS(INA2XX_SHUNT_UV(sv) / shunt_register) > (active_current * 120 / 100) &&
+		(INA2XX_SHUNT_UV(sv) > 0) && (active_current != 0)) {
+		curr_status = EC_ASSERTED_PROCHOT;
+		hook_call_deferred(&board_check_current_data, 10 * MSEC);
+	} else if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
+		/* Don't need to de-assert the prochot when system in S5/G3 */
+		curr_status = EC_DEASSERTED_PROCHOT;
+		hook_call_deferred(&board_check_current_data, 100 * MSEC);
+	} else {
+		curr_status = EC_DEASSERTED_PROCHOT;
+		hook_call_deferred(&board_check_current_data, 10 * MSEC);
+	}
+
+	if ((curr_status != pre_status) && !chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
+		CPRINTS("EC %sassert prochot!! INA236 current=%d mA",
+			curr_status == EC_DEASSERTED_PROCHOT ? "de-" : "",
+			(INA2XX_SHUNT_UV(sv) / shunt_register));
+
+		throttle_ap((curr_status == EC_ASSERTED_PROCHOT) ? THROTTLE_ON : THROTTLE_OFF,
+				THROTTLE_HARD, THROTTLE_SRC_AC);
+	}
+
+	pre_status = curr_status;
+	pre_active_port = active_port;
+}
+
+__overridable int extpower_is_present(void)
+{
+	return last_extpower_present;
+}
+
+__override void board_check_extpower(void)
+{
+	static int pre_active_port = -1;
+	int pd_active_port = get_active_charge_pd_port();
+	int hw_extpower_status = gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_hw_acav_in));
+	int extpower_present = hw_extpower_status;
+	uint8_t c_fet_status = cypd_get_cfet_status();
+
+	/*
+	 * AC status
+	 *
+	 * +--------------+---------+---------------+------------+--------------------+
+	 * |   extpower   |  C fet  |  active port  |   result   |       status       |
+	 * +--------------+---------+---------------+------------+--------------------+
+	 * |     High     |  Close  |   non-active  |   HW pin   | Leakage            |
+	 * |     High     |  Close  |     active    |   HW pin   | Leakage            |
+	 * |     High     |  Open   |   non-active  |   HW pin   | Leakage            |
+	 * |     High     |  Open   |     active    |  PD state  | Normal             |
+	 * |     Low      |  Close  |   non-active  |  PD state  | Normal             |
+	 * |     Low      |  Close  |     active    |   HW pin   | VBUS control fail  |
+	 * |     Low      |  Open   |   non-active  |   HW pin   | VBUS control fail  |
+	 * |     Low      |  Open   |     active    |   HW pin   | Multi-ports switch |
+	 * |     Low      |  Open   |     active    |  PD state  | EPR mode switch    |
+	 * +--------------+---------+---------------+------------+--------------------+
+	 */
+
+	if ((pre_active_port == pd_active_port) &&
+		(((pd_active_port != -1) && c_fet_status) ||
+		((pd_active_port == -1) && !c_fet_status)))
+		extpower_present = (pd_active_port == -1) ? 0 : 1;
+
+	if (last_extpower_present != extpower_present) {
+		/**
+		 * last extpower present is a return value in function "extpower_is_present()",
+		 * must update the value before extpower_handle_update();
+		 */
+		last_extpower_present = extpower_present;
+		extpower_handle_update(extpower_present);
+	} else
+		last_extpower_present = extpower_present;
+
+	/* we should update the PMF as soon as possible after the typec port state is changed */
+	update_soc_power_limit(false, false);
+
+	/**
+	 * set the GPU to ac mode if the adapter power = 100w,
+	 * more than 100w will be controlled by enter EPR mode.
+	 */
+	if (pd_active_port && cypd_get_ac_power() == 100000)
+		set_gpu_gpio(GPIO_FUNC_ACDC, 1);
+
+	pre_active_port = pd_active_port;
+}
+
+/* EC console command */
+static int ina236_cmd(int argc, const char **argv)
+{
+	if (argc >= 2) {
+		if (!strncmp(argv[1], "en", 2)) {
+			log_ina236 = true;
+		} else if (!strncmp(argv[1], "dis", 3)) {
+			log_ina236 = false;
+		} else {
+			return EC_ERROR_PARAM1;
+		}
+	}
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(ina236, ina236_cmd, "[en/dis]",
+			"Enable or disable ina236 logging");
+
+/* EC console command */
+static int chgbypass_cmd(int argc, const char **argv)
+{
+	if (argc >= 2) {
+		if (!strncmp(argv[1], "en", 2)) {
+			bypass_force_en = true;
+			bypass_force_disable = false;
+		} else if (!strncmp(argv[1], "dis", 3)) {
+			bypass_force_en = false;
+			bypass_force_disable = true;
+		} else if (!strncmp(argv[1], "auto", 4)) {
+			bypass_force_en = false;
+			bypass_force_disable = false;
+		} else {
+			return EC_ERROR_PARAM1;
+		}
+	}
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(chargerbypass, chgbypass_cmd, "[en/dis/auto]",
+			"Force charger bypass enabled");
diff --git a/zephyr/program/framework/lotus/src/cpu_power.c b/zephyr/program/framework/lotus/src/cpu_power.c
new file mode 100644
index 0000000000..c1cbc37f30
--- /dev/null
+++ b/zephyr/program/framework/lotus/src/cpu_power.c
@@ -0,0 +1,1170 @@
+
+
+
+#include "charge_state.h"
+#include "charger.h"
+#include "charge_manager.h"
+#include "board_charger.h"
+#include "board_battery.h"
+#include "board_function.h"
+#include "chipset.h"
+#include "common_cpu_power.h"
+#include "customized_shared_memory.h"
+#include "console.h"
+#include "cypress_pd_common.h"
+#include "cpu_power.h"
+#include "driver/sb_rmi.h"
+#include "extpower.h"
+#include "gpu.h"
+#include "hooks.h"
+#include "math_util.h"
+#include "power.h"
+#include "throttle_ap.h"
+#include "util.h"
+#include "gpu.h"
+#include "driver/charger/isl9241_public.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+
+static int battery_current_limit_mA;
+static int slider_stt_table;
+static int thermal_stt_table;
+static int safety_stt;
+static uint8_t events;
+static bool force_typec_1_5a_flag;
+
+enum clear_reasons {
+	PROCHOT_CLEAR_REASON_SUCCESS,
+	PROCHOT_CLEAR_REASON_NOT_POWER,
+	PROCHOT_CLEAR_REASON_FORCE,
+};
+
+/* Update PL for thermal table pmf sheet : slider default */
+static void update_os_power_slider(int mode, bool with_dc, int active_mpower)
+{
+	switch (mode) {
+	case EC_DC_BEST_PERFORMANCE:
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPL] =
+			(gpu_is_working() ? 60000 : 40000);
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPPT] =
+			(gpu_is_working() ? 60000 : 48000);
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_FPPT] =
+			(gpu_is_working() ? 60000 : 58000);
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_APU_ONLY_SPPT] =
+			(gpu_is_working() ? 30000 : 0);
+		slider_stt_table = (gpu_is_working() ? 21 : 23);
+		CPRINTS("DC BEST PERFORMANCE");
+		break;
+	case EC_DC_BALANCED:
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPL] =
+			(gpu_is_working() ? 50000 : 30000);
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPPT] =
+			(gpu_is_working() ? 50000 : 36000);
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_FPPT] =
+			(gpu_is_working() ? 50000 : 44000);
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_APU_ONLY_SPPT] =
+			(gpu_is_working() ? 20000 : 0);
+		slider_stt_table = (gpu_is_working() ? 22 : 24);
+		CPRINTS("DC BALANCED");
+		break;
+	case EC_DC_BEST_EFFICIENCY:
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPL] =
+			(gpu_is_working() ? 50000 : 20000);
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPPT] =
+			(gpu_is_working() ? 50000 : 24000);
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_FPPT] =
+			(gpu_is_working() ? 50000 : 29000);
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_APU_ONLY_SPPT] =
+			(gpu_is_working() ? 20000 : 0);
+		slider_stt_table = (gpu_is_working() ? 22 : 25);
+		CPRINTS("DC BEST EFFICIENCY");
+		break;
+	case EC_DC_BATTERY_SAVER:
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPL] = 20000;
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPPT] = 20000;
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_FPPT] = 20000;
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_APU_ONLY_SPPT] =
+			(gpu_is_working() ? 20000 : 0);
+		slider_stt_table = (gpu_is_working() ? 7 : 14);
+		CPRINTS("DC BATTERY SAVER");
+		break;
+	case EC_AC_BEST_PERFORMANCE:
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPL] =
+			(gpu_is_working() ? 145000 : 45000);
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPPT] =
+			(gpu_is_working() ? 145000 : 54000);
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_FPPT] =
+			(gpu_is_working() ? 145000 : 65000);
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_APU_ONLY_SPPT] =
+			(gpu_is_working() ? 54000 : 0);
+		slider_stt_table = (gpu_is_working() ? 1 : 8);
+		CPRINTS("AC BEST PERFORMANCE");
+		break;
+	case EC_AC_BALANCED:
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPL] =
+			(gpu_is_working() ? 120000 : 40000);
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPPT] =
+			(gpu_is_working() ? 120000 : 48000);
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_FPPT] =
+			(gpu_is_working() ? 120000 : 58000);
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_APU_ONLY_SPPT] =
+			(gpu_is_working() ? 50000 : 0);
+		slider_stt_table = (gpu_is_working() ? 32 : 9);
+		CPRINTS("AC BALANCED");
+		break;
+	case EC_AC_BEST_EFFICIENCY:
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPL] =
+			(gpu_is_working() ? 85000 : 30000);
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPPT] =
+			(gpu_is_working() ? 85000 : 36000);
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_FPPT] =
+			(gpu_is_working() ? 85000 : 44000);
+		power_limit[FUNCTION_SLIDER].mwatt[TYPE_APU_ONLY_SPPT] =
+			(gpu_is_working() ? 40000 : 0);
+		slider_stt_table = (gpu_is_working() ? 3 : 10);
+		CPRINTS("AC BEST EFFICIENCY");
+		break;
+	default:
+		/* no mode, run power table */
+		break;
+	}
+}
+
+/* Update PL for thermal table pmf sheet : pmf */
+static void update_thermal_power_limit(int battery_percent, int active_mpower,
+				       bool with_dc, int mode)
+{
+	if (gpu_is_working()) {
+		if ((active_mpower >= 240000) && with_dc) {
+			/* limited by update_os_power_slider */
+			power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPL] =
+				power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPL];
+			power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPPT] =
+				power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPPT];
+			power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_FPPT] =
+				power_limit[FUNCTION_SLIDER].mwatt[TYPE_FPPT];
+			power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_APU_ONLY_SPPT] =
+				power_limit[FUNCTION_SLIDER].mwatt[TYPE_APU_ONLY_SPPT];
+			thermal_stt_table = slider_stt_table;
+		} else if (active_mpower >= 180000) {
+			if (mode == EC_AC_BALANCED) {
+				/* limited by update_os_power_slider */
+				power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPL] = 950000;
+				power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPPT] = 950000;
+				power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_FPPT] = 950000;
+				power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_APU_ONLY_SPPT]
+					= 50000;
+				thermal_stt_table = 2;
+			} else {
+				/* limited by update_os_power_slider */
+				power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPL] =
+					power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPL];
+				power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPPT] =
+					power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPPT];
+				power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_FPPT] =
+					power_limit[FUNCTION_SLIDER].mwatt[TYPE_FPPT];
+				power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_APU_ONLY_SPPT] =
+					power_limit[FUNCTION_SLIDER].mwatt[TYPE_APU_ONLY_SPPT];
+				thermal_stt_table = slider_stt_table;
+			}
+		} else if (active_mpower >= 140000) {
+			if (with_dc) {
+				if (mode == EC_AC_BEST_PERFORMANCE) {
+					power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPL] = 95000;
+					power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPPT] = 95000;
+					power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_FPPT] = 95000;
+					power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_APU_ONLY_SPPT]
+						= 50000;
+					thermal_stt_table = 4;
+				} else if (mode == EC_AC_BALANCED) {
+					power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPL] = 85000;
+					power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPPT] = 85000;
+					power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_FPPT] = 85000;
+					power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_APU_ONLY_SPPT]
+						= 40000;
+					thermal_stt_table = 15;
+				} else {
+					power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPL] = 60000;
+					power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPPT] = 60000;
+					power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_FPPT] = 60000;
+					power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_APU_ONLY_SPPT] 
+						= 30000;
+					thermal_stt_table = 17;
+				}
+			} else {
+				if (mode == EC_AC_BEST_PERFORMANCE) {
+					power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPL] = 60000;
+					power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPPT] = 60000;
+					power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_FPPT] = 60000;
+					power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_APU_ONLY_SPPT]
+						= 30000;
+					thermal_stt_table = 26;
+				} else if (mode == EC_AC_BALANCED) {
+					power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPL] = 50000;
+					power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPPT] = 50000;
+					power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_FPPT] = 50000;
+					power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_APU_ONLY_SPPT]
+						= 20000;
+					thermal_stt_table = 27;
+				} else {
+					power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPL] = 30000;
+					power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPPT] = 30000;
+					power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_FPPT] = 30000;
+					power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_APU_ONLY_SPPT]
+						= 30000;
+					thermal_stt_table = 28;
+				}
+			}
+		} else if (active_mpower >= 100000) {
+			if (with_dc) {
+				if (mode == EC_AC_BEST_PERFORMANCE) {
+					power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPL] = 85000;
+					power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPPT] = 85000;
+					power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_FPPT] = 85000;
+					power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_APU_ONLY_SPPT]
+						= 40000;
+					thermal_stt_table = 5;
+				} else {
+					power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPL] = 60000;
+					power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPPT] = 60000;
+					power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_FPPT] = 60000;
+					power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_APU_ONLY_SPPT]
+						= 30000;
+					thermal_stt_table = 16;
+				}
+			} else {
+				if ((mode == EC_AC_BEST_PERFORMANCE) || (mode == EC_AC_BALANCED)) {
+					power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPL] = 50000;
+					power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPPT] = 50000;
+					power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_FPPT] = 50000;
+					power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_APU_ONLY_SPPT]
+						= 20000;
+					thermal_stt_table = 29;
+				} else {
+					power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPL] = 30000;
+					power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPPT] = 30000;
+					power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_FPPT] = 30000;
+					power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_APU_ONLY_SPPT]
+						= 30000;
+					thermal_stt_table = 30;
+				}
+			}
+		} else if ((active_mpower < 100000) && (active_mpower > 0)) {
+			if (with_dc) {
+				power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPL] = 60000;
+				power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPPT] = 60000;
+				power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_FPPT] = 60000;
+				power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_APU_ONLY_SPPT] = 30000;
+				thermal_stt_table = 6;
+			} else {
+				power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPL] = 30000;
+				power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPPT] = 30000;
+				power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_FPPT] = 30000;
+				power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_APU_ONLY_SPPT] = 30000;
+				thermal_stt_table = 31;
+			}
+		} else {
+			/* DC only */
+			/* limited by update_os_power_slider */
+			power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPL] =
+				power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPL];
+			power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPPT] =
+				power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPPT];
+			power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_FPPT] =
+				power_limit[FUNCTION_SLIDER].mwatt[TYPE_FPPT];
+			power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_APU_ONLY_SPPT] =
+				power_limit[FUNCTION_SLIDER].mwatt[TYPE_APU_ONLY_SPPT];
+			thermal_stt_table = slider_stt_table;
+		}
+	} else {
+		/* UMA */
+		if (active_mpower >= 180000) {
+			/* limited by update_os_power_slider */
+			power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPL] =
+				power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPL];
+			power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPPT] =
+				power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPPT];
+			power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_FPPT] =
+				power_limit[FUNCTION_SLIDER].mwatt[TYPE_FPPT];
+			power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_APU_ONLY_SPPT] = 0;
+			thermal_stt_table = slider_stt_table;
+		} else if (active_mpower >= 100000) {
+			if (mode == EC_AC_BEST_PERFORMANCE) {
+				power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPL] = 45000;
+				power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPPT] = 54000;
+				power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_FPPT] = 65000;
+				power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_APU_ONLY_SPPT] = 0;
+				thermal_stt_table = 11;
+			} else if (mode == EC_AC_BALANCED) {
+				power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPL] = 40000;
+				power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPPT] = 48000;
+				power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_FPPT] = 58000;
+				power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_APU_ONLY_SPPT] = 0;
+				thermal_stt_table = 18;
+			} else {
+				power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPL] = 30000;
+				power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPPT] = 36000;
+				power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_FPPT] = 44000;
+				power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_APU_ONLY_SPPT] = 0;
+				thermal_stt_table = 19;
+			}
+		} else if (active_mpower >= 80000) {
+			if (mode == EC_AC_BEST_PERFORMANCE) {
+				power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPL] = 30000;
+				power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPPT] = 36000;
+				power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_FPPT] = 44000;
+				power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_APU_ONLY_SPPT] = 0;
+				thermal_stt_table = 12;
+			} else {
+				power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPL] = 30000;
+				power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPPT] = 36000;
+				power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_FPPT] = 44000;
+				power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_APU_ONLY_SPPT] = 0;
+				thermal_stt_table = 20;
+			}
+		} else if ((active_mpower < 80000) && (active_mpower > 0)) {
+			power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPL] = 30000;
+			power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPPT] = 30000;
+			power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_FPPT] = 30000;
+			power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_APU_ONLY_SPPT] = 0;
+			thermal_stt_table = 13;
+		} else {
+			/* DC only */
+			/* limited by update_os_power_slider */
+			power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPL] =
+				power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPL];
+			power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_SPPT] =
+				power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPPT];
+			power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_FPPT] =
+				power_limit[FUNCTION_SLIDER].mwatt[TYPE_FPPT];
+			power_limit[FUNCTION_THERMAL_PMF].mwatt[TYPE_APU_ONLY_SPPT] = 0;
+			thermal_stt_table = slider_stt_table;
+		}
+	}
+}
+
+static int get_adapter_power_limit_index(int old_index, int battery_percent, int mode)
+{
+	/* at ERS only performance mode need to adjust limit */
+	if (mode == EC_AC_BEST_PERFORMANCE) {
+		if (battery_percent > 60)
+			old_index = 0;
+		else if (battery_percent < 30)
+			old_index = 1;
+	} else
+		old_index = 1;
+
+	return old_index;
+}
+
+static void update_adapter_power_limit(int battery_percent, int active_mpower,
+				       bool with_dc, int mode)
+{
+	static int new_index;
+
+	if (gpu_is_working()) {
+		if (with_dc) {
+			if (active_mpower >= 240000) {
+				new_index =
+					get_adapter_power_limit_index(new_index,
+						battery_percent, mode);
+				switch (new_index) {
+				case 0:
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 145000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = 145000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = 145000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_APU_ONLY_SPPT] =
+						54000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] =
+						MIN(227000, (active_mpower * 918 / 1000) +
+						133740 - 30000 - 125000);
+					break;
+				case 1:
+				default:
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 105000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = 105000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = 105000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_APU_ONLY_SPPT] =
+						50000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] =
+						MIN(150000, (active_mpower * 918 / 1000) +
+						55000 - 30000 - 95000);
+					break;
+				}
+			} else if (active_mpower >= 180000) {
+				new_index =
+					get_adapter_power_limit_index(new_index,
+						battery_percent, mode);
+				switch (new_index) {
+				case 0:
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 120000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = 120000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = 120000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_APU_ONLY_SPPT] =
+						54000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] =
+						MIN(145000, (active_mpower * 918 / 1000) +
+						133740 - 30000 - 125000);
+					break;
+				case 1:
+				default:
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 95000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = 95000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = 95000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_APU_ONLY_SPPT] =
+						50000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] =
+						MIN(95000, (active_mpower * 918 / 1000) +
+						55000 - 30000 - 95000);
+					break;
+				}
+			} else if (active_mpower >= 140000) {
+				new_index =
+					get_adapter_power_limit_index(new_index,
+						battery_percent, mode);
+				switch (new_index) {
+				case 0:
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 95000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = 95000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = 95000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_APU_ONLY_SPPT] =
+						50000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] =
+						MIN(138000, (active_mpower * 918 / 1000) +
+						123000 - 30000 - 120000);
+					break;
+				case 1:
+				default:
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 85000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = 85000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = 85000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_APU_ONLY_SPPT] =
+						40000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] =
+						MIN(120000, (active_mpower * 918 / 1000) +
+						75000 - 30000 - 85000);
+					break;
+				}
+			} else if (active_mpower >= 100000) {
+				new_index =
+					get_adapter_power_limit_index(new_index,
+						battery_percent, mode);
+				switch (new_index) {
+				case 0:
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 60000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = 60000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = 60000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_APU_ONLY_SPPT] =
+						30000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] =
+						MIN(120000, (active_mpower * 918 / 1000) +
+						123000 - 30000 - 100000);
+					break;
+				case 1:
+				default:
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 40000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = 40000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = 40000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_APU_ONLY_SPPT] =
+						30000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] =
+						MIN(100000, (active_mpower * 918 / 1000) +
+						75000 - 30000 - 75000);
+					break;
+				}
+			} else if (active_mpower >= 5000) {
+				/* DC + AC under 100W */
+				new_index =
+					get_adapter_power_limit_index(new_index,
+						battery_percent, mode);
+				switch (new_index) {
+				case 0:
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 60000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = 60000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = 60000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_APU_ONLY_SPPT] =
+						30000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] = 118000;
+					break;
+				case 1:
+				default:
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 40000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = 40000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = 40000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_APU_ONLY_SPPT] =
+						20000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] = 100000;
+					break;
+				}
+			} else {
+				/* DC only */
+				if (battery_percent > 30) {
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 60000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = 60000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = 60000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_APU_ONLY_SPPT] =
+						30000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] = 118000;
+					new_index = 0;
+				} else if (battery_percent > 25) {
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 50000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = 50000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = 50000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_APU_ONLY_SPPT] =
+						20000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] = 100000;
+					new_index = 1;
+				} else if (battery_percent > 20) {
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 40000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = 40000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = 40000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_APU_ONLY_SPPT] =
+						20000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] = 100000;
+					new_index = 1;
+				} else {
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 20000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = 20000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = 20000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_APU_ONLY_SPPT] =
+						20000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] = 65000;
+					new_index = 1;
+				}
+			}
+		} else {
+		/* AC only */
+			if (active_mpower >= 240000) {
+				power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 120000;
+				power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = 120000;
+				power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = 120000;
+				power_limit[FUNCTION_POWER].mwatt[TYPE_APU_ONLY_SPPT] = 54000;
+				power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] =
+					MIN(145000, (active_mpower * 918 / 1000) - 30000 - 60000);
+			} else if (active_mpower >= 180000) {
+				power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 60000;
+				power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = 60000;
+				power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = 60000;
+				power_limit[FUNCTION_POWER].mwatt[TYPE_APU_ONLY_SPPT] = 30000;
+				power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] =
+					MIN(75000, (active_mpower * 918 / 1000) - 30000);
+			} else if (active_mpower >= 140000) {
+				power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 50000;
+				power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = 50000;
+				power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = 50000;
+				power_limit[FUNCTION_POWER].mwatt[TYPE_APU_ONLY_SPPT] = 20000;
+				power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] =
+					75000;
+			} else if (active_mpower >= 100000) {
+				power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 30000;
+				power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = 30000;
+				power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = 30000;
+				power_limit[FUNCTION_POWER].mwatt[TYPE_APU_ONLY_SPPT] = 30000;
+				power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] =
+					75000;
+			} else {
+				power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 0;
+				power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = 0;
+				power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = 0;
+				power_limit[FUNCTION_POWER].mwatt[TYPE_APU_ONLY_SPPT] = 0;
+				power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] = 65000;
+			}
+		}
+	} else {
+		/* UMA */
+		if (with_dc) {
+			if (active_mpower >= 240000) {
+				new_index =
+					get_adapter_power_limit_index(new_index,
+						battery_percent, mode);
+				switch (new_index) {
+				case 0:
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 45000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = 54000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = 65000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_APU_ONLY_SPPT] = 0;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] =
+						MIN(227000, (active_mpower * 918 / 1000)
+							+ 133740 - 30000);
+					break;
+				case 1:
+				default:
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 45000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = 54000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = 65000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_APU_ONLY_SPPT] = 0;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] =
+						MIN(227000, (active_mpower * 918 / 1000)
+							+ 40000 - 30000);
+					break;
+				}
+			} else if (active_mpower >= 180000) {
+				new_index =
+					get_adapter_power_limit_index(new_index,
+						battery_percent, mode);
+				switch (new_index) {
+				case 0:
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 45000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = 54000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = 65000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_APU_ONLY_SPPT] = 0;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] =
+						MIN(227000, (active_mpower * 918 / 1000) + 133740 - 30000);
+					break;
+				case 1:
+				default:
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 45000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = 54000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = 65000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_APU_ONLY_SPPT] = 0;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] =
+						MIN(170000, (active_mpower * 918 / 1000) + 40000 - 30000);
+					break;
+				}
+			} else if (active_mpower >= 140000) {
+				new_index =
+					get_adapter_power_limit_index(new_index,
+						battery_percent, mode);
+				switch (new_index) {
+				case 0:
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 45000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = 54000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = 65000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_APU_ONLY_SPPT] = 0;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] =
+						MIN(227000, (active_mpower * 918 / 1000) + 133740 - 30000);
+					break;
+				case 1:
+				default:
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 40000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = 48000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = 58000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_APU_ONLY_SPPT] = 0;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] =
+						MIN(175000, (active_mpower * 918 / 1000) + 40000 - 30000);
+					break;
+				}
+			} else if (active_mpower >= 65000) {
+				new_index =
+					get_adapter_power_limit_index(new_index,
+						battery_percent, mode);
+				switch (new_index) {
+				case 0:
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 45000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = 54000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = 65000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_APU_ONLY_SPPT] = 0;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] =
+						MIN(187000, (active_mpower * 6885 / 10000) + 148600 - 30000);
+					break;
+				case 1:
+				default:
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 30000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = 36000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = 44000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_APU_ONLY_SPPT] = 0;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] =
+						MIN(175000, (active_mpower * 6885 / 10000) + 45000 - 30000);
+					break;
+				}
+			} else if (active_mpower >= 5000) {
+				/* DC + AC under 65W */
+				new_index =
+					get_adapter_power_limit_index(new_index,
+						battery_percent, mode);
+				switch (new_index) {
+				case 0:
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 45000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = 54000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = 65000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_APU_ONLY_SPPT] = 0;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] = 118000;
+					break;
+				case 1:
+				default:
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 30000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = 36000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = 44000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_APU_ONLY_SPPT] = 0;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] = 65000;
+					break;
+				}
+			} else {
+				/*  DC only */
+				if (battery_percent > 30) {
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 45000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = 54000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = 65000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_APU_ONLY_SPPT] = 0;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] = 118000;
+					new_index = 0;
+				} else if (battery_percent > 25) {
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 30000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = 36000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = 44000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_APU_ONLY_SPPT] = 0;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] = 100000;
+					new_index = 1;
+				} else if (battery_percent > 20) {
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 20000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = 24000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = 29000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_APU_ONLY_SPPT] = 0;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] = 100000;
+					new_index = 1;
+				} else {
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 20000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = 20000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = 20000;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_APU_ONLY_SPPT] = 0;
+					power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] = 65000;
+					new_index = 1;
+				}
+			}
+		} else {
+		/* AC only */
+			if (active_mpower >= 240000) {
+				power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 45000;
+				power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = 54000;
+				power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = 65000;
+				power_limit[FUNCTION_POWER].mwatt[TYPE_APU_ONLY_SPPT] = 0;
+				power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] =
+					MIN(227000, (active_mpower * 918 / 1000) - 30000);
+			} else if (active_mpower >= 180000) {
+				power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 45000;
+				power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = 54000;
+				power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = 65000;
+				power_limit[FUNCTION_POWER].mwatt[TYPE_APU_ONLY_SPPT] = 0;
+				power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] =
+					MIN(135000, (active_mpower * 918 / 1000) - 30000);
+			} else if (active_mpower >= 140000) {
+				power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 45000;
+				power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = 54000;
+				power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = 65000;
+				power_limit[FUNCTION_POWER].mwatt[TYPE_APU_ONLY_SPPT] = 0;
+				power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] =
+					MIN(100000, (active_mpower * 918 / 1000) - 30000);
+			} else if (active_mpower >= 65000) {
+				power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 30000;
+				power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = 36000;
+				power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = 44000;
+				power_limit[FUNCTION_POWER].mwatt[TYPE_APU_ONLY_SPPT] = 0;
+				power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] =
+					MIN(70000, (active_mpower - 30000));
+			} else {
+				power_limit[FUNCTION_POWER].mwatt[TYPE_SPL] = 0;
+				power_limit[FUNCTION_POWER].mwatt[TYPE_SPPT] = 0;
+				power_limit[FUNCTION_POWER].mwatt[TYPE_FPPT] = 0;
+				power_limit[FUNCTION_POWER].mwatt[TYPE_APU_ONLY_SPPT] = 0;
+				power_limit[FUNCTION_POWER].mwatt[TYPE_P3T] = 65000;
+			}
+		}
+	}
+}
+
+static void tune_PLs(int delta)
+{
+	power_limit[FUNCTION_SAFETY].mwatt[TYPE_SPL]
+		= MAX(power_limit[FUNCTION_SAFETY].mwatt[TYPE_SPL] + delta, 20000);
+	power_limit[FUNCTION_SAFETY].mwatt[TYPE_SPPT]
+		= MAX(power_limit[FUNCTION_SAFETY].mwatt[TYPE_SPPT] + delta, 20000);
+	power_limit[FUNCTION_SAFETY].mwatt[TYPE_FPPT]
+		= MAX(power_limit[FUNCTION_SAFETY].mwatt[TYPE_FPPT] + delta, 20000);
+	power_limit[FUNCTION_SAFETY].mwatt[TYPE_P3T]
+		= MAX(power_limit[FUNCTION_SAFETY].mwatt[TYPE_P3T] + delta, 20000);
+	if (gpu_is_working())
+		power_limit[FUNCTION_SAFETY].mwatt[TYPE_APU_ONLY_SPPT]
+			= MAX(power_limit[FUNCTION_SAFETY].mwatt[TYPE_APU_ONLY_SPPT]
+					+ delta, 20000);
+}
+
+static void update_safety_power_limit(int active_mpower)
+{
+	static uint8_t safety_level;
+	static uint8_t level_increase;
+	int delta;
+	int average_current = get_average_battery_current();
+	int battery_voltage = battery_dynamic[BATT_IDX_MAIN].actual_voltage;
+	int rv;
+	int mw_apu = power_limit[FUNCTION_SLIDER].mwatt[TYPE_APU_ONLY_SPPT];
+	static timestamp_t wait_stable_time;
+	static timestamp_t update_safety_timer;
+	timestamp_t now = get_time();
+
+	if (!timestamp_expired(wait_stable_time, &now) ||
+		!timestamp_expired(update_safety_timer, &now))
+		return;
+
+	if (my_test_current != 0)
+		average_current = my_test_current;
+
+	/* discharge, value compare based on negative */
+	if (average_current < battery_current_limit_mA)
+		level_increase = 1;
+	else if (average_current > (battery_current_limit_mA * 75 / 100))
+		level_increase = 0;
+	else
+		return;
+
+	switch (safety_level) {
+	case LEVEL_NORMAL:
+		/* follow thermal table */
+		power_limit[FUNCTION_SAFETY].mwatt[TYPE_SPL]
+			= power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPL];
+		power_limit[FUNCTION_SAFETY].mwatt[TYPE_SPPT]
+			= power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPPT];
+		power_limit[FUNCTION_SAFETY].mwatt[TYPE_FPPT]
+			= power_limit[FUNCTION_SLIDER].mwatt[TYPE_FPPT];
+		power_limit[FUNCTION_SAFETY].mwatt[TYPE_P3T]
+			= power_limit[FUNCTION_POWER].mwatt[TYPE_P3T];
+		if (gpu_is_working())
+			power_limit[FUNCTION_SAFETY].mwatt[TYPE_APU_ONLY_SPPT]
+				= power_limit[FUNCTION_SLIDER].mwatt[TYPE_APU_ONLY_SPPT];
+		else
+			power_limit[FUNCTION_SAFETY].mwatt[TYPE_APU_ONLY_SPPT]
+				= 0;
+		if (level_increase)
+			safety_level++;
+		break;
+	case LEVEL_STOP_CHARGE:
+		/* stop charging */
+		if (level_increase) {
+			set_chg_ctrl_mode(CHARGE_CONTROL_IDLE);
+			safety_level++;
+		} else {
+			set_chg_ctrl_mode(CHARGE_CONTROL_NORMAL);
+			if (safety_level > 0)
+				safety_level--;
+		}
+		break;
+	case LEVEL_TUNE_PLS:
+		/* tuning CPU and GPU PLs */
+		if (gpu_is_working()) {
+			delta = 10000;
+			if (level_increase) {
+				tune_PLs((-1) * delta);
+				if ((power_limit[FUNCTION_SAFETY].mwatt[TYPE_SPL] <= 60000)
+					|| (power_limit[FUNCTION_SAFETY].mwatt[TYPE_APU_ONLY_SPPT]
+						<= 30000)) {
+					power_limit[FUNCTION_SAFETY].mwatt[TYPE_SPL]
+						= 45000;
+					power_limit[FUNCTION_SAFETY].mwatt[TYPE_SPPT]
+						= 54000;
+					power_limit[FUNCTION_SAFETY].mwatt[TYPE_FPPT]
+						= 65000;
+					power_limit[FUNCTION_SAFETY].mwatt[TYPE_APU_ONLY_SPPT]
+						= 54000;
+					safety_level++;
+				}
+			} else {
+				tune_PLs(delta);
+				if ((power_limit[FUNCTION_SAFETY].mwatt[TYPE_SPL]
+					 >= power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPL])
+					 || (power_limit[FUNCTION_SAFETY].mwatt[TYPE_APU_ONLY_SPPT]
+						 >= mw_apu)) {
+					safety_level--;
+				}
+			}
+		} else {
+			delta = (ABS(average_current - battery_current_limit_mA)
+				* battery_voltage) * 8 / 10 / 1000;
+			if (level_increase) {
+				tune_PLs((-1) * delta);
+				if (power_limit[FUNCTION_SAFETY].mwatt[TYPE_SPL] <= 20000)
+					safety_level = LEVEL_PROCHOT;
+			} else {
+				tune_PLs(delta);
+				if (power_limit[FUNCTION_SAFETY].mwatt[TYPE_SPL]
+					>= power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPL])
+					safety_level--;
+			}
+		}
+
+		/* wait the system stable */
+		wait_stable_time.val = get_time().val + (5 * SECOND);
+		break;
+	case LEVEL_DISABLE_GPU:
+		/* disable GPU and tune CPU PLs */
+		if (gpu_is_working()) {
+			if (level_increase) {
+				tune_PLs(-10000);
+				if (power_limit[FUNCTION_SAFETY].mwatt[TYPE_SPL] <= 20000)
+					safety_level++;
+			} else {
+				tune_PLs(10000);
+				if (power_limit[FUNCTION_SAFETY].mwatt[TYPE_SPL] >= 60000)
+					safety_level--;
+			}
+
+			/* wait the system stable */
+			wait_stable_time.val = get_time().val + (5 * SECOND);
+		} else {
+			if (level_increase)
+				safety_level++;
+			else
+				safety_level--;
+		}
+		break;
+	case LEVEL_PROCHOT:
+		/* prochot */
+		if (level_increase) {
+			throttle_ap(THROTTLE_ON, THROTTLE_HARD, THROTTLE_SRC_BAT_DISCHG_CURRENT);
+			thermal_stt_table = (gpu_is_working() ? 7 : 14);
+			safety_stt = 1;
+			safety_level++;
+		} else {
+			throttle_ap(THROTTLE_OFF, THROTTLE_HARD, THROTTLE_SRC_BAT_DISCHG_CURRENT);
+			thermal_stt_table = (gpu_is_working() ? 7 : 14);
+			safety_stt = 1;
+			safety_level--;
+		}
+		break;
+	case LEVEL_TYPEC_1_5A:
+		if (level_increase) {
+			force_typec_1_5a_flag = 1;
+			for (int controller = 0; controller < PD_CHIP_COUNT; controller++) {
+				for (int port = 0; port < 2; port++) {
+					if (cypd_port_3a_status(controller, port)) {
+						/*if device is 3A sink device
+						 * foce current to 1.5A
+						 */
+						rv = cypd_modify_safety_power_1_5A(controller,
+							port);
+					}
+				}
+			}
+			safety_level++;
+		} else {
+			force_typec_1_5a_flag = 0;
+			safety_level--;
+		}
+		break;
+	case LEVEL_COUNT:
+		thermal_stt_table = (gpu_is_working() ? 7 : 14);
+		if (!level_increase)
+			safety_level--;
+		break;
+	default:
+		safety_level = LEVEL_COUNT;
+		break;
+	}
+
+	/* only check safety function per second */
+	update_safety_timer.val = get_time().val + (1 * SECOND);
+
+	if (safety_pwr_logging) {
+		CPRINTS("increase = %d, level = %d, curr = %d", level_increase,
+					safety_level, average_current);
+		CPRINTS("SAFETY, SPL %dmW, fPPT %dmW, sPPT %dmW, p3T %dmW, ao_sppt %dmW",
+					power_limit[FUNCTION_SAFETY].mwatt[TYPE_SPL],
+					power_limit[FUNCTION_SAFETY].mwatt[TYPE_FPPT],
+					power_limit[FUNCTION_SAFETY].mwatt[TYPE_SPPT],
+					power_limit[FUNCTION_SAFETY].mwatt[TYPE_P3T],
+					power_limit[FUNCTION_SAFETY].mwatt[TYPE_APU_ONLY_SPPT]);
+	}
+}
+
+void force_clear_pmf_prochot(void)
+{
+	CPRINTS("pmf update timeout");
+	update_pmf_events(0, 255);
+}
+DECLARE_DEFERRED(force_clear_pmf_prochot);
+
+void update_pmf_events(uint8_t pd_event, int enable)
+{
+	static uint8_t pre_events;
+	int power;
+
+	switch (power_get_state()) {
+	case POWER_S0:
+	case POWER_S3S0:
+	case POWER_S0ixS0: /* S0ix -> S0 */
+		power = 1;
+		break;
+	default:
+		power = 0;
+	}
+
+	/* We should not need to assert the prochot before apu ready to update pmf */
+	if (!power || !get_apu_ready() || (enable == 255)) {
+		pre_events = 0;
+		pd_event = 0;
+		events = 0;
+		throttle_ap(THROTTLE_OFF, THROTTLE_HARD, THROTTLE_SRC_UPDATE_PMF);
+		return;
+	}
+
+	if (enable)
+		events |= pd_event;
+	else
+		events &= ~pd_event;
+
+	if (pre_events != events) {
+		CPRINTS("events = %d, pre_events = %d", events, pre_events);
+		if (events) {
+			throttle_ap(THROTTLE_ON, THROTTLE_HARD, THROTTLE_SRC_UPDATE_PMF);
+			if (pd_event == BIT(PD_PROGRESS_ENTER_EPR_MODE))
+				set_gpu_gpio(GPIO_FUNC_ACDC, 0);
+			hook_call_deferred(&force_clear_pmf_prochot_data, 3 * SECOND);
+		} else {
+			throttle_ap(THROTTLE_OFF, THROTTLE_HARD, THROTTLE_SRC_UPDATE_PMF);
+			if (pd_event == BIT(PD_PROGRESS_ENTER_EPR_MODE))
+				set_gpu_gpio(GPIO_FUNC_ACDC, 1);
+			hook_call_deferred(&force_clear_pmf_prochot_data, -1);
+		}
+
+		pre_events = events;
+	}
+}
+
+void clear_prochot(enum clear_reasons reason)
+{
+	if (events & BIT(PD_PROGRESS_ENTER_EPR_MODE) && (cypd_get_ac_power() > 100000)) {
+		/* wait charger to entry the bypass mode */
+		if (isl9241_is_in_bypass_mode(0))
+			update_pmf_events(BIT(PD_PROGRESS_ENTER_EPR_MODE), 0);
+	}
+
+	if (events & BIT(PD_PROGRESS_EXIT_EPR_MODE))
+		update_pmf_events(BIT(PD_PROGRESS_EXIT_EPR_MODE), 0);
+
+	if (events & BIT(PD_PROGRESS_DISCONNECTED)) {
+		/* if the adapter is disconnected, we should clear all events */
+		update_pmf_events(0xff, 0);
+	}
+}
+
+void update_soc_power_limit(bool force_update, bool force_no_adapter)
+{
+	static uint32_t old_sustain_power_limit;
+	static uint32_t old_fast_ppt_limit;
+	static uint32_t old_slow_ppt_limit;
+	static uint32_t old_p3t_limit;
+	static int old_slider_mode;
+	static int set_pl_limit;
+	static uint32_t old_ao_sppt;
+	static int old_stt_table;
+	int mode = *host_get_memmap(EC_MEMMAP_POWER_SLIDE);
+	int active_mpower = cypd_get_ac_power();
+	bool with_dc = (((battery_is_present() == BP_YES) &&
+			!battery_cutoff_in_progress() && !battery_is_cut_off()) ? true : false);
+	int battery_percent = get_system_percentage() / 10;
+
+	if ((*host_get_memmap(EC_MEMMAP_STT_TABLE_NUMBER)) == 0)
+		old_stt_table = 0;
+
+	if (!chipset_in_state(CHIPSET_STATE_ON) || !get_apu_ready()) {
+		clear_prochot(PROCHOT_CLEAR_REASON_NOT_POWER);
+		return;
+	}
+
+#ifdef CONFIG_BOARD_LOTUS
+	if (force_update && isl9241_is_in_bypass_mode(0) && !get_gpu_gpio(GPIO_FUNC_ACDC))
+		set_gpu_gpio(GPIO_FUNC_ACDC, 1);
+
+#endif
+
+	if (mode_ctl)
+		mode = mode_ctl;
+
+	if (force_no_adapter || (!extpower_is_present())) {
+		active_mpower = 0;
+	}
+
+	if (old_slider_mode != mode) {
+		old_slider_mode = mode;
+		if (func_ctl & 0x1)
+			update_os_power_slider(mode, with_dc, active_mpower);
+	}
+
+	if (func_ctl & 0x1)
+		update_thermal_power_limit(battery_percent, active_mpower, with_dc, mode);
+
+	if (func_ctl & 0x2)
+		update_adapter_power_limit(battery_percent, active_mpower, with_dc, mode);
+
+	if (func_ctl & 0x4) {
+		update_safety_power_limit(active_mpower);
+	}
+
+	if ((mode != 0) && (old_stt_table != thermal_stt_table) && (thermal_stt_table != 0)) {
+		*host_get_memmap(EC_MEMMAP_STT_TABLE_NUMBER) = thermal_stt_table;
+		old_stt_table = thermal_stt_table;
+		host_set_single_event(EC_HOST_EVENT_STT_UPDATE);
+	}
+
+	/* when trigger thermal warm, reduce TYPE_APU_ONLY_SPPT to 45W */
+	if (gpu_is_working()) {
+		if (thermal_warn_trigger())
+			power_limit[FUNCTION_THERMAL].mwatt[TYPE_APU_ONLY_SPPT] = 45000;
+		else
+			power_limit[FUNCTION_THERMAL].mwatt[TYPE_APU_ONLY_SPPT] = 0;
+	}
+
+	for (int item = TYPE_SPL; item < TYPE_COUNT; item++) {
+		/* use slider as default */
+		target_func[item] = FUNCTION_SLIDER;
+		for (int func = FUNCTION_DEFAULT; func < FUNCTION_COUNT; func++) {
+			/* Ignored the zero value */
+			if (power_limit[func].mwatt[item] < 1)
+				continue;
+
+			/* choose the lowest one */
+			if (power_limit[target_func[item]].mwatt[item]
+				> power_limit[func].mwatt[item])
+				target_func[item] = func;
+		}
+	}
+
+	if (power_limit[target_func[TYPE_SPL]].mwatt[TYPE_SPL] != old_sustain_power_limit
+		|| power_limit[target_func[TYPE_FPPT]].mwatt[TYPE_FPPT] != old_fast_ppt_limit
+		|| power_limit[target_func[TYPE_SPPT]].mwatt[TYPE_SPPT] != old_slow_ppt_limit
+		|| power_limit[target_func[TYPE_P3T]].mwatt[TYPE_P3T] != old_p3t_limit
+		|| (power_limit[target_func[TYPE_APU_ONLY_SPPT]].mwatt[TYPE_APU_ONLY_SPPT]
+			!= old_ao_sppt)
+		|| set_pl_limit || force_update || events) {
+		/* only set PL when it is changed */
+		old_sustain_power_limit = power_limit[target_func[TYPE_SPL]].mwatt[TYPE_SPL];
+		old_slow_ppt_limit = power_limit[target_func[TYPE_SPPT]].mwatt[TYPE_SPPT];
+		old_fast_ppt_limit = power_limit[target_func[TYPE_FPPT]].mwatt[TYPE_FPPT];
+		old_p3t_limit = power_limit[target_func[TYPE_P3T]].mwatt[TYPE_P3T];
+
+		set_pl_limit = set_pl_limits(old_sustain_power_limit, old_fast_ppt_limit,
+			old_slow_ppt_limit, old_p3t_limit);
+
+		if (!set_pl_limit) {
+			old_ao_sppt =
+			power_limit[target_func[TYPE_APU_ONLY_SPPT]].mwatt[TYPE_APU_ONLY_SPPT];
+			set_pl_limit = update_apu_only_sppt_limit(old_ao_sppt);
+		}
+
+		if (!set_pl_limit) {
+			/* Update PMF success, print the setting and de-asssert the prochot */
+			CPRINTS("PMF: SPL %dmW, sPPT %dmW, fPPT %dmW, p3T %dmW, ao_sppt %dmW",
+			old_sustain_power_limit, old_slow_ppt_limit,
+			old_fast_ppt_limit, old_p3t_limit, old_ao_sppt);
+
+			clear_prochot(PROCHOT_CLEAR_REASON_SUCCESS);
+		}
+	}
+}
+
+static void initial_soc_power_limit(void)
+{
+	battery_current_limit_mA = -5490;
+
+	/* initial slider table to battery balance as default */
+	power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPL] = 60000;
+	power_limit[FUNCTION_SLIDER].mwatt[TYPE_SPPT] = 60000;
+	power_limit[FUNCTION_SLIDER].mwatt[TYPE_FPPT] = 60000;
+	power_limit[FUNCTION_SLIDER].mwatt[TYPE_P3T] = 227000;
+	power_limit[FUNCTION_SLIDER].mwatt[TYPE_APU_ONLY_SPPT] = 60000;
+}
+DECLARE_HOOK(HOOK_INIT, initial_soc_power_limit, HOOK_PRIO_INIT_I2C);
+
+bool safety_force_typec_1_5A(void)
+{
+	return force_typec_1_5a_flag;
+}
diff --git a/zephyr/program/framework/lotus/src/ej889i.c b/zephyr/program/framework/lotus/src/ej889i.c
new file mode 100644
index 0000000000..3606142372
--- /dev/null
+++ b/zephyr/program/framework/lotus/src/ej889i.c
@@ -0,0 +1,161 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/drivers/gpio.h>
+
+#include "board_host_command.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "gpio.h"
+#include "gpio/gpio_int.h"
+#include "gpu.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "lotus/amd_r23m.h"
+#include "power.h"
+#include "temp_sensor/temp_sensor.h"
+#include "timer.h"
+#include "util.h"
+#include "gpu_configuration.h"
+
+#define EJ899I_ADDR	0x60
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+static int host_dp_ready;
+uint8_t ej889i_address;
+const struct gpio_int_config *ej889i_pd_interrupt;
+const struct gpio_int_config *ej889i_hpd_interrupt;
+
+int ej889i_init(struct gpu_subsys_pd *init)
+{
+	if (init) {
+		ej889i_hpd_interrupt = gpu_gpio_to_dt_int(init->gpio_hpd);
+		ej889i_pd_interrupt = gpu_gpio_to_dt_int(init->gpio_interrupt);
+		ej889i_address = init->address;
+
+	} else {
+		ej889i_address = 0;
+		ej889i_hpd_interrupt = 0;
+		ej889i_pd_interrupt = 0;
+	}
+
+	return EC_SUCCESS;
+}
+
+int ej889i_read_reg8(int reg, int *data)
+{
+	int rv;
+
+	rv = i2c_read_offset16(I2C_PORT_GPU0, ej889i_address, reg, data, 1);
+	if (rv != EC_SUCCESS)
+		CPRINTS("%s failed: reg=0x%02x", __func__, reg);
+	return rv;
+}
+
+int ej889i_write_reg8(int reg, int data)
+{
+	int rv;
+
+	rv = i2c_write_offset16(I2C_PORT_GPU0, ej889i_address, reg, data, 1);
+	if (rv != EC_SUCCESS)
+		CPRINTS("%s failed: reg=0x%02x", __func__, reg);
+	return rv;
+}
+
+void read_gpu_id(void);
+DECLARE_DEFERRED(read_gpu_id);
+
+void read_gpu_id(void)
+{
+	int rv, data;
+
+	/* Read the register */
+	rv = ej889i_read_reg8(0x800E, &data);
+	if (rv == EC_SUCCESS)
+		CPRINTS("reg = 0x0E, result=%d", data);
+
+	k_msleep(5);
+
+	rv = ej889i_read_reg8(0x8010, &data);
+	if (rv == EC_SUCCESS)
+		CPRINTS("reg = 0x10, result=%d", data);
+
+	k_msleep(5);
+
+	rv = ej889i_read_reg8(0x8011, &data);
+	if (rv == EC_SUCCESS)
+		CPRINTS("reg = 0x11, result=%d", data);
+
+	k_msleep(5);
+
+	rv = ej889i_read_reg8(0x80DE, &data);
+	if (rv == EC_SUCCESS)
+		CPRINTS("reg = 0xDE, result=%d", data);
+
+	k_msleep(5);
+
+	rv = ej889i_read_reg8(0x810C, &data);
+	if (rv == EC_SUCCESS)
+		CPRINTS("reg = 0x10C, result=%d", data);
+
+	k_msleep(5);
+
+	rv = ej889i_read_reg8(0x8110, &data);
+	if (rv == EC_SUCCESS)
+		CPRINTS("reg = 0x110, result=%d", data);
+
+	k_msleep(5);
+
+	rv = ej889i_read_reg8(0x8111, &data);
+	if (rv == EC_SUCCESS)
+		CPRINTS("reg = 0x111, result=%d", data);
+
+	k_msleep(5);
+
+	rv = ej889i_read_reg8(0x8112, &data);
+	if (rv == EC_SUCCESS)
+		CPRINTS("reg = 0x112, result=%d", data);
+}
+
+void set_host_dp_ready(int ready)
+{
+	host_dp_ready = ready;
+
+	if (ready && ej889i_address) {
+		CPRINTS("ready to send the Qevent 58!");
+		if (ej889i_hpd_interrupt)
+			gpio_enable_dt_interrupt(ej889i_hpd_interrupt);
+
+		if (get_gpu_gpio(GPIO_FUNC_HPD))
+			host_set_single_event(EC_HOST_EVENT_DGPU_TYPEC_NOTIFY);
+	} else {
+		if (ej889i_hpd_interrupt)
+			gpio_disable_dt_interrupt(ej889i_hpd_interrupt);
+
+	}
+}
+
+void dgpu_hot_plug_deferred(void)
+{
+	if (get_gpu_gpio(GPIO_FUNC_HPD))
+		host_set_single_event(EC_HOST_EVENT_DGPU_TYPEC_NOTIFY);
+}
+DECLARE_DEFERRED(dgpu_hot_plug_deferred);
+
+void dp_hot_plug_interrupt(enum gpio_signal signal)
+{
+	/* add debounce time to avoid EC panic */
+	hook_call_deferred(&dgpu_hot_plug_deferred_data, 100 * MSEC);
+}
+
+/* Currently, the GPU pd interrupt does not function */
+void gpu_pd_interrupt(enum gpio_signal signal)
+{
+	CPRINTS("gpu pd interrupt!");
+	hook_call_deferred(&read_gpu_id_data, 50 * MSEC);
+}
diff --git a/zephyr/program/framework/lotus/src/f75303.c b/zephyr/program/framework/lotus/src/f75303.c
new file mode 100644
index 0000000000..fc2ab48e84
--- /dev/null
+++ b/zephyr/program/framework/lotus/src/f75303.c
@@ -0,0 +1,169 @@
+/* Copyright 2018 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* F75303 temperature sensor module for Chrome EC -Framework only */
+
+#include "board_adc.h"
+#include "common.h"
+#include "console.h"
+#include "i2c.h"
+#include "hooks.h"
+#include "lotus/gpu.h"
+#include "math_util.h"
+#include "system.h"
+#include "temp_sensor/f75303.h"
+#include "temp_sensor/temp_sensor.h"
+#include "util.h"
+#include "gpu_f75303.h"
+
+static int temps[F75303_IDX_COUNT];
+static int8_t fake_temp[F75303_IDX_COUNT] = { -1, -1, -1, -1, -1, -1};
+
+/**
+ * Read 8 bits register from temp sensor.
+ */
+static int raw_read8(int sensor, const int offset, int *data)
+{
+	return i2c_read8(f75303_sensors[sensor].i2c_port,
+			 f75303_sensors[sensor].i2c_addr_flags, offset, data);
+}
+
+static int get_temp(int sensor, const int offset, int *temp)
+{
+	int rv;
+	int data = 0;
+	int temp_raw = 0;
+
+	/* read high byte (1 degree) and low byte (0.125 degree)*/
+	switch (offset) {
+	case F75303_TEMP_LOCAL_REGISTER:
+		rv = raw_read8(sensor, offset, &temp_raw);
+		rv = raw_read8(sensor, F75303_TEMP_LOCAL_LOW_REGISTER, &data);
+		break;
+	case F75303_TEMP_REMOTE1_REGISTER:
+		rv = raw_read8(sensor, offset, &temp_raw);
+		rv = raw_read8(sensor, F75303_TEMP_REMOTE1_LOW_REGISTER, &data);
+		break;
+	case F75303_TEMP_REMOTE2_REGISTER:
+		rv = raw_read8(sensor, offset, &temp_raw);
+		rv = raw_read8(sensor, F75303_TEMP_REMOTE2_LOW_REGISTER, &data);
+		break;
+	default:
+		rv = EC_ERROR_INVAL;
+	}
+
+	if (rv != 0)
+		return rv;
+
+	temp_raw = (temp_raw * 1000) + ((data >> 4) * 125);
+	*temp = MILLI_CELSIUS_TO_MILLI_KELVIN(temp_raw);
+
+	return EC_SUCCESS;
+}
+
+int f75303_get_val(int idx, int *temp)
+{
+	/* unused function */
+	return EC_SUCCESS;
+}
+
+int f75303_get_val_k(int idx, int *temp_k_ptr)
+{
+	if (idx < 0 || idx >= F75303_IDX_COUNT)
+		return EC_ERROR_INVAL;
+
+	if ((!gpu_f75303_present() || !gpu_power_enable()) && idx > 2)
+		*temp_k_ptr = C_TO_K(0);
+	else
+		*temp_k_ptr = MILLI_KELVIN_TO_KELVIN(temps[idx]);
+	return EC_SUCCESS;
+}
+
+int f75303_get_val_mk(int idx, int *temp_mk_ptr)
+{
+	if (idx >= F75303_IDX_COUNT)
+		return EC_ERROR_INVAL;
+
+	*temp_mk_ptr = temps[idx];
+	return EC_SUCCESS;
+}
+
+void f75303_update_temperature(int idx)
+{
+	int temp_reg = 0;
+	int rv = 0;
+
+	if (idx >= F75303_IDX_COUNT)
+		return;
+	switch (idx) {
+	/* ambient_f75303 */
+	case 0:
+		rv = get_temp(idx, F75303_TEMP_LOCAL_REGISTER, &temp_reg);
+		break;
+	/* apu_f75303 */
+	case 1:
+		rv = get_temp(idx, F75303_TEMP_REMOTE1_REGISTER, &temp_reg);
+		break;
+	/* charger_f75303 */
+	case 2:
+		rv = get_temp(idx, F75303_TEMP_REMOTE2_REGISTER, &temp_reg);
+		break;
+	/* gpu_amb_f75303 */
+	case 3:
+		if (gpu_f75303_present() && gpu_power_enable())
+			rv = get_temp(idx, F75303_TEMP_LOCAL_REGISTER, &temp_reg);
+		else
+			rv = EC_ERROR_NOT_POWERED;
+		break;
+	/* gpu_vr_f75303 */
+	case 4:
+		if (gpu_f75303_present() && gpu_power_enable())
+			rv = get_temp(idx, F75303_TEMP_REMOTE1_REGISTER, &temp_reg);
+		else
+			rv = EC_ERROR_NOT_POWERED;
+		break;
+	/* gpu_vram_f75303 */
+	case 5:
+		if (gpu_f75303_present() && gpu_power_enable())
+			rv = get_temp(idx, F75303_TEMP_REMOTE2_REGISTER, &temp_reg);
+		else
+			rv = EC_ERROR_NOT_POWERED;
+		break;
+	}
+	if (rv == EC_SUCCESS)
+		temps[idx] = temp_reg;
+}
+
+static int f75303_set_fake_temp(int argc, const char **argv)
+{
+	int index;
+	int value;
+	char *e;
+
+	if (argc != 3)
+		return EC_ERROR_PARAM_COUNT;
+
+	index = strtoi(argv[1], &e, 0);
+	if ((*e) || (index < 0) || (index >= F75303_IDX_COUNT))
+		return EC_ERROR_PARAM1;
+
+	if (!strcasecmp(argv[2], "off")) {
+		fake_temp[index] = -1;
+		ccprintf("Turn off fake temp mode for sensor %u.\n", index);
+		return EC_SUCCESS;
+	}
+
+	value = strtoi(argv[2], &e, 0);
+
+	if ((*e) || (value < 0) || (value > 100))
+		return EC_ERROR_PARAM2;
+
+	fake_temp[index] = value;
+	ccprintf("Force sensor %u = %uC.\n", index, value);
+
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(f75303, f75303_set_fake_temp, "<index> <value>|off",
+			"Set fake temperature of sensor f75303.");
diff --git a/zephyr/program/framework/lotus/src/fan.c b/zephyr/program/framework/lotus/src/fan.c
new file mode 100644
index 0000000000..a5bae06803
--- /dev/null
+++ b/zephyr/program/framework/lotus/src/fan.c
@@ -0,0 +1,103 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "fan.h"
+#include "math_util.h"
+#include "thermal.h"
+#include "amd_stt.h"
+
+#include <zephyr/kernel.h>
+
+#define CONFIG_FAN_START_DUTY 15
+
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_THERMAL, format, ##args)
+
+
+enum fan_status board_override_fan_control_duty(int ch)
+{
+	struct fan_data *data = &fan_data[ch];
+	int duty, new_duty, rpm_diff, duty_step;
+	int rpm_actual = data->rpm_actual;
+	int rpm_target = data->rpm_target;
+	int deviation = fans[ch].rpm->rpm_deviation;
+
+	duty = fan_get_duty(ch);
+	if (duty == 0 && rpm_target == 0) {
+		return FAN_STATUS_STOPPED;
+	}
+
+	if (duty > 0) {
+		if (duty < 20) {
+			deviation = 10;
+		} else if (duty < 35) {
+			deviation = 7;
+		}
+	}
+
+	/* wait rpm is stable */
+	if (ABS(rpm_actual - data->rpm_pre) > (rpm_target * deviation / 100)) {
+		data->rpm_pre = rpm_actual;
+		return FAN_STATUS_CHANGING;
+	}
+
+	/* Record previous rpm */
+	data->rpm_pre = rpm_actual;
+
+	/*
+	 * A specific type of fan needs a longer time to output the TACH
+	 * signal to EC after EC outputs the PWM signal to the fan.
+	 * During this period, the driver will read two consecutive RPM = 0.
+	 * In this case, don't step the PWM duty too aggressively.
+	 * We subtract 200 from the start RPM as margin.
+	 */
+	if (rpm_actual < (fans[ch].rpm->rpm_min  - 200)) {
+		fan_set_duty(ch, CONFIG_FAN_START_DUTY);
+		return FAN_STATUS_CHANGING;
+	}
+
+	rpm_diff = rpm_target - rpm_actual;
+
+	if (rpm_diff > (rpm_target * deviation / 100)) {
+		/* Can't set duty higher than 100%... */
+		if (duty == 100)
+			return FAN_STATUS_FRUSTRATED;
+	} else if (rpm_diff < -(rpm_target * deviation / 100)) {
+		/* Can't set duty lower than 1%... */
+		if (duty == 1 && rpm_target != 0)
+			return FAN_STATUS_FRUSTRATED;
+	} else {
+		return FAN_STATUS_LOCKED;
+	}
+
+	/*
+	 * The rpm_diff -> duty_step conversion is specific to a specific
+	 * whiterun fan.
+	 * It has been determined empirically.
+	 */
+	if (ABS(rpm_diff) >= 2100) {
+		duty_step = 28;
+	} else if (ABS(rpm_diff) >= 1100) {
+		duty_step = 14;
+	} else if (ABS(rpm_diff) >= 550) {
+		duty_step = 6;
+	} else if (ABS(rpm_diff) >= 300) {
+		duty_step = 3;
+	} else if (ABS(rpm_diff) >= 150) {
+		duty_step = 2;
+	} else {
+		duty_step = 1;
+	}
+
+	if (rpm_diff > 0)
+		new_duty = MIN(duty + duty_step, 100);
+	else
+		new_duty = MAX(duty - duty_step, 1);
+
+	fan_set_duty(ch, new_duty);
+
+	return FAN_STATUS_CHANGING;
+}
diff --git a/zephyr/program/framework/lotus/src/gpu.c b/zephyr/program/framework/lotus/src/gpu.c
new file mode 100644
index 0000000000..a3060c4d4c
--- /dev/null
+++ b/zephyr/program/framework/lotus/src/gpu.c
@@ -0,0 +1,294 @@
+
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * ADC for checking BOARD ID.
+ */
+
+#include "adc.h"
+#include "battery.h"
+#include "chipset.h"
+#include "customized_shared_memory.h"
+#include "extpower.h"
+#include "gpio/gpio_int.h"
+#include "gpio.h"
+#include "gpu.h"
+#include "board_adc.h"
+#include "board_function.h"
+#include "board_host_command.h"
+#include "console.h"
+#include "driver/temp_sensor/f75303.h"
+#include "extpower.h"
+#include "flash_storage.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "system.h"
+#include "thermal.h"
+#include "gpu_configuration.h"
+
+LOG_MODULE_REGISTER(gpu, LOG_LEVEL_DBG);
+
+#define VALID_BOARDID(ID1, ID0) ((ID1 << 8) + ID0)
+static int fan_present;
+static int module_present;
+static int module_fault;
+static int gpu_id_0;
+static int gpu_id_1;
+static int switch_status;
+
+bool gpu_power_enable(void)
+{
+	/* dgpu pwr enable pin will be high at s5 state*/
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return 0;
+	else
+		return gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_dgpu_pwr_en));
+}
+
+bool gpu_is_working(void)
+{
+	if (gpu_present() && gpu_power_enable())
+		return true;
+
+	return false;
+}
+
+bool gpu_module_fault(void)
+{
+	return module_fault;
+}
+
+bool gpu_fan_board_present(void)
+{
+	return fan_present;
+}
+
+void update_gpu_ac_power_state(void)
+{
+	int level = extpower_is_present();
+
+	/**
+	 * The chagrer ACOK status will be off -> on -> off after the adapter is removed.
+	 * We need to use the customized extpower_is_present to get the correct status.
+	 */
+	set_gpu_gpio(GPIO_FUNC_ACDC, level);
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, update_gpu_ac_power_state, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, update_gpu_ac_power_state, HOOK_PRIO_DEFAULT);
+DECLARE_DEFERRED(update_gpu_ac_power_state);
+
+void update_gpu_ac_mode_deferred(int times)
+{
+	hook_call_deferred(&update_gpu_ac_power_state_data, times);
+}
+
+/* After GPU detect, update the thermal configuration */
+void init_gpu_latch(void)
+{
+	if (board_get_version() >= BOARD_VERSION_7) {
+		gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_beam_open));
+	} else {
+		gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_chassis_open));
+	}
+}
+DECLARE_HOOK(HOOK_INIT, init_gpu_latch, HOOK_PRIO_DEFAULT + 2);
+
+int get_gpu_latch(void)
+{
+	if (board_get_version() >= BOARD_VERSION_7) {
+		return gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_f_beam_open_l));
+	} else {
+		return gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_chassis_open_l));
+	}
+}
+
+void gpu_interposer_toggle_deferred(void)
+{
+	int rv;
+
+	rv = board_cut_off_battery();
+	if (rv == EC_RES_SUCCESS) {
+		LOG_DBG("board cut off succeeded.");
+		set_battery_in_cut_off();
+	} else
+		LOG_DBG("board cut off failed!");
+}
+DECLARE_DEFERRED(gpu_interposer_toggle_deferred);
+
+void beam_function(void)
+{
+	static int cutoff;
+	static int gpu_interposer_toggle_count;
+
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
+		gpu_interposer_toggle_count++;
+		if (!cutoff && gpu_interposer_toggle_count >= 10) {
+			hook_call_deferred(&gpu_interposer_toggle_deferred_data,
+				100 * MSEC);
+			cutoff = 1;
+		}
+	} else
+		gpu_interposer_toggle_count = 0;
+}
+
+void check_gpu_module(void)
+{
+
+	gpu_id_0 = get_hardware_id(ADC_GPU_BOARD_ID_0);
+	gpu_id_1 = get_hardware_id(ADC_GPU_BOARD_ID_1);
+	switch_status = get_gpu_latch();
+	fan_present = 0;
+	switch (VALID_BOARDID(gpu_id_0, gpu_id_1)) {
+	case VALID_BOARDID(BOARD_VERSION_12, BOARD_VERSION_12):
+		LOG_DBG("Detected dual interposer device");
+		module_present = 1;
+		module_fault = 0;
+		break;
+	case VALID_BOARDID(BOARD_VERSION_11, BOARD_VERSION_15):
+		LOG_DBG("Detected single interposer device");
+		module_present = 1;
+		module_fault = 0;
+		break;
+	case VALID_BOARDID(BOARD_VERSION_13, BOARD_VERSION_15):
+		LOG_DBG("Detected UMA fan board");
+		fan_present = 1;
+		module_present = 0;
+		module_fault = 0;
+		break;
+	case VALID_BOARDID(BOARD_VERSION_15, BOARD_VERSION_15):
+		LOG_DBG("No gpu module detected %d %d", gpu_id_0, gpu_id_1);
+		module_present = 0;
+		module_fault = 0;
+		if (board_get_version() < BOARD_VERSION_8) {
+			fan_present = 1;
+		}
+		break;
+	default:
+		LOG_DBG("GPU module Fault");
+		module_present = 0;
+		module_fault = 1;
+	break;
+	}
+
+	/* The chassis or f_beam is opened, turn off the power */
+	if (!switch_status)
+		module_present = 0;
+
+	if (module_present) {
+		init_gpu_module();
+	} else {
+		deinit_gpu_module();
+	}
+	if (fan_present) {
+		init_uma_fan();
+	}
+	update_gpu_ac_power_state();
+
+	beam_function();
+}
+DECLARE_DEFERRED(check_gpu_module);
+DECLARE_HOOK(HOOK_INIT, check_gpu_module, HOOK_PRIO_INIT_ADC + 1);
+
+__override void project_chassis_function(enum gpio_signal signal)
+{
+}
+
+void beam_open_interrupt(enum gpio_signal signal)
+{
+	int open_state = gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_f_beam_open_l));
+
+	/* The dGPU SW is SW4 at DVT phase */
+	if (board_get_version() < BOARD_VERSION_7)
+		return;
+
+	if (!open_state) {
+		/* Make sure the module is off as fast as possible! */
+		LOG_DBG("Powering off GPU");
+		deinit_gpu_module();
+		switch_status = 0;
+	} else {
+		hook_call_deferred(&check_gpu_module_data, 200 * MSEC);
+	}
+}
+
+void gpu_smart_access_graphic(void);
+DECLARE_DEFERRED(gpu_smart_access_graphic);
+
+void gpu_smart_access_graphic(void)
+{
+	uint8_t gpu_status = *host_get_memmap(EC_CUSTOMIZED_MEMMAP_GPU_CONTROL);
+
+	/**
+	 * Host updated the shared memory to control the mux,
+	 * after switching the mux, clear the shared memory BIT(0) and BIT(1).
+	 */
+	if ((gpu_status & 0x03) == SET_GPU_MUX) {
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_edp_mux_pwm_sw), 1);
+		gpu_status &= 0xFC;
+		gpu_status |= GPU_MUX;
+	}
+
+	if ((gpu_status & 0x03) == SET_APU_MUX) {
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_edp_mux_pwm_sw), 0);
+		gpu_status &= 0xFC;
+		gpu_status &= ~GPU_MUX;
+	}
+
+	/**
+	 * Host updated the shared memory to reset the edp,
+	 * after controlling the reset pin, clear the shared memory BIT(4) and BIT(5).
+	 */
+	if ((gpu_status & GPU_EDP_MASK) == ASSERTED_EDP_RESET) {
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_edp_reset), 0);
+		gpu_status &= ~GPU_EDP_MASK;
+	}
+
+	if ((gpu_status & GPU_EDP_MASK) == DEASSERTED_EDP_RESET) {
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_edp_reset), 1);
+		gpu_status &= ~GPU_EDP_MASK;
+	}
+
+	*host_get_memmap(EC_CUSTOMIZED_MEMMAP_GPU_CONTROL) = gpu_status;
+
+	/* Polling to check the shared memory of the GPU */
+	if (!chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) ||
+	    !chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		hook_call_deferred(&gpu_smart_access_graphic_data, 10 * MSEC);
+}
+/* TODO FIXME ON GPU LATE CONNECT */
+static void start_smart_access_graphic(void)
+{
+	/* Check GPU is present then polling the namespace to do the smart access graphic */
+	if (gpu_present())
+		hook_call_deferred(&gpu_smart_access_graphic_data, 10 * MSEC);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, start_smart_access_graphic, HOOK_PRIO_DEFAULT);
+
+
+
+
+
+static enum ec_status host_command_expansion_bay_status(struct host_cmd_handler_args *args)
+{
+	struct ec_response_expansion_bay_status *r = args->response;
+
+	r->state = 0;
+	if (module_present) {
+		r->state |= MODULE_ENABLED;
+	}
+	if (module_fault) {
+		r->state |= MODULE_FAULT;
+	}
+	if (switch_status) {
+		r->state |= HATCH_SWITCH_CLOSED;
+	}
+	r->board_id_0 = gpu_id_0;
+	r->board_id_1 = gpu_id_1;
+
+	args->response_size = sizeof(*r);
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_EXPANSION_BAY_STATUS, host_command_expansion_bay_status,
+		EC_VER_MASK(0));
diff --git a/zephyr/program/framework/lotus/src/gpu_configuration.c b/zephyr/program/framework/lotus/src/gpu_configuration.c
new file mode 100644
index 0000000000..6722af0a71
--- /dev/null
+++ b/zephyr/program/framework/lotus/src/gpu_configuration.c
@@ -0,0 +1,1168 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * ADC for checking BOARD ID.
+ */
+
+#include "gpu_configuration.h"
+#include "i2c.h"
+#include "util.h"
+#include "console.h"
+#include "zephyr_console_shim.h"
+
+#include "power.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "gpio/gpio_int.h"
+
+#include "board_host_command.h"
+#include "customized_shared_memory.h"
+#include "hooks.h"
+
+#include "ej889i.h"
+#include "gpu_f75303.h"
+#include "board_adc.h"
+#include "thermal.h"
+#include "fan.h"
+#include "board_thermal.h"
+
+#include "gpu.h"
+
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args)
+
+
+#define SUPPORTED_DESCRIPTOR_MAJOR 0
+#define SUPPORTED_DESCRIPTOR_MINOR 1
+
+/**
+ * The type of the CRC values.
+ *
+ * This type must be big enough to contain at least 32 bits.
+ */
+typedef uint_fast32_t crc_t;
+
+/**
+ * Calculate the initial crc value.
+ *
+ * \return     The initial crc value.
+ */
+static inline crc_t crc_init(void)
+{
+	return 0xffffffff;
+}
+
+/**
+ * Static table used for the table_driven implementation.
+ */
+static const crc_t crc_table[256] = {
+	0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f,
+	0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
+	0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2,
+	0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
+	0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9,
+	0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
+	0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, 0x35b5a8fa, 0x42b2986c,
+	0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
+	0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423,
+	0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
+	0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, 0x01db7106,
+	0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
+	0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d,
+	0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
+	0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950,
+	0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
+	0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7,
+	0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
+	0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa,
+	0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
+	0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81,
+	0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
+	0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, 0xe3630b12, 0x94643b84,
+	0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
+	0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb,
+	0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
+	0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e,
+	0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
+	0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55,
+	0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
+	0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28,
+	0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
+	0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f,
+	0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
+	0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242,
+	0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
+	0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69,
+	0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
+	0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc,
+	0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
+	0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693,
+	0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
+	0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d
+};
+
+crc_t crc_update(crc_t crc, const void *data, size_t data_len)
+{
+	const unsigned char *d = (const unsigned char *)data;
+	unsigned int tbl_idx;
+
+	while (data_len--) {
+		tbl_idx = (crc ^ *d) & 0xff;
+		crc = (crc_table[tbl_idx] ^ (crc >> 8)) & 0xffffffff;
+		d++;
+	}
+	return crc & 0xffffffff;
+}
+
+/**
+ * Calculate the final crc value.
+ *
+ * \param[in] crc  The current crc value.
+ * \return     The final crc value.
+ */
+static inline crc_t crc_finalize(crc_t crc)
+{
+	return crc ^ 0xffffffff;
+}
+
+
+bool gpu_cfg_descriptor_valid;
+bool gpu_verbose;
+struct gpu_cfg_descriptor gpu_descriptor;
+uint8_t gpu_read_buff[GPU_MAX_BLOCK_LEN];
+uint8_t gpu_subsys_serials[GPU_SUBSYS_MAX][20];
+enum gpu_pcie_cfg gpu_pcie_configuration;
+enum gpu_vendor  gpu_vendor;
+static int power_enable;
+
+uint8_t address = 0x50;
+
+struct gpu_cfg_gpio gpu_gpio_cfgs[GPU_GPIO_MAX];
+
+
+struct default_gpu_cfg {
+	struct gpu_cfg_descriptor descriptor;
+
+	struct gpu_block_header hdr0;
+	enum gpu_pcie_cfg pcie_cfg;
+
+	struct gpu_block_header hdr1;
+	struct gpu_cfg_fan fan0_cfg;
+
+	struct gpu_block_header hdr2;
+	struct gpu_cfg_fan fan1_cfg;
+
+	struct gpu_block_header hdr3;
+	enum gpu_vendor vendor;
+
+	struct gpu_block_header hdr4;
+	struct gpu_cfg_gpio     gpio0;
+	struct gpu_cfg_gpio     gpio1;
+	struct gpu_cfg_gpio     gpio2;
+	struct gpu_cfg_gpio     gpio3;
+	struct gpu_cfg_gpio     gpio_vsys;
+	struct gpu_cfg_gpio     gpio_fan;
+	struct gpu_cfg_gpio     gpu_3v_5v_en;
+
+	struct gpu_block_header hdr5;
+	struct gpu_subsys_pd    pd;
+
+	struct gpu_block_header hdr6;
+	struct gpu_cfg_thermal therm;
+
+	struct gpu_block_header hdr7;
+	struct gpu_cfg_custom_temp custom_temp;
+
+	struct gpu_block_header hdr8;
+	struct gpu_subsys_serial pcba_serial;
+
+
+} __packed;
+
+static struct default_gpu_cfg gpu_cfg = {
+	.descriptor = {
+		.magic = {0x32, 0xac, 0x00, 0x00},
+		.length = sizeof(struct gpu_cfg_descriptor),
+		.descriptor_version_major = 0,
+		.descriptor_version_minor = 1,
+		.hardware_version = 0x0008,
+		.hardware_revision = 0,
+		.serial = {'F', 'R', 'A', 'K', 'M', 'B', 'C', 'P', '8', '1',
+					'3', '3', '1', 'A', 'S', 'S', 'Y', '0', '\0', '\0'},
+		.descriptor_length = sizeof(struct default_gpu_cfg) - sizeof(struct gpu_cfg_descriptor),
+		.descriptor_crc32 = 0,
+		.crc32 = 0
+	},
+	.hdr0 = {.block_type = GPUCFG_TYPE_PCIE, .block_length = sizeof(uint8_t)},
+	.pcie_cfg = PCIE_8X1,
+
+	.hdr1 = {.block_type = GPUCFG_TYPE_FAN, .block_length = sizeof(struct gpu_cfg_fan)},
+	.fan0_cfg = {.idx = 0, .flags = 0, .min_rpm = 1000, .start_rpm = 1000, .max_rpm = 4700},
+
+	.hdr2 = {.block_type = GPUCFG_TYPE_FAN, .block_length = sizeof(struct gpu_cfg_fan)},
+	.fan1_cfg = {.idx = 1, .flags = 0, .min_rpm = 1000, .start_rpm = 1000, .max_rpm = 4500},
+
+	.hdr3 = {.block_type = GPUCFG_TYPE_VENDOR, .block_length = sizeof(gpu_vendor)},
+	.vendor = GPU_AMD_R23M,
+
+	.hdr4 = {.block_type = GPUCFG_TYPE_GPIO, .block_length = (sizeof(struct gpu_cfg_gpio) * 7)},
+	/* Critical temperature fault input */
+	.gpio0 = {.gpio = GPU_1G1_GPIO0_EC, .function = GPIO_FUNC_TEMPFAULT, .flags = GPIO_INPUT, .power_domain = POWER_S3},
+	/* DP HPD status from PD */
+	.gpio1 = {.gpio = GPU_1H1_GPIO1_EC, .function = GPIO_FUNC_HPD, .flags = GPIO_INPUT, .power_domain = POWER_S5},
+	/* AC/DC mode setting */
+	.gpio2 = {.gpio = GPU_2A2_GPIO2_EC, .function = GPIO_FUNC_ACDC, .flags = GPIO_OUTPUT_LOW, .power_domain = POWER_S3},
+	/* UNUSED */
+	.gpio3 = {.gpio = GPU_2L7_GPIO3_EC, .function = GPIO_FUNC_UNUSED, .flags = GPIO_OUTPUT_LOW, .power_domain = POWER_G3},
+	/* GPU_VSYS_EN */
+	.gpio_vsys = {.gpio = GPU_VSYS_EN, .function = GPIO_FUNC_GPU_PWR, .flags = GPIO_OUTPUT_LOW, .power_domain = POWER_S3},
+
+	.gpio_fan = {.gpio = GPU_FAN_EN, .function = GPIO_FUNC_HIGH, .flags = GPIO_OUTPUT_LOW, .power_domain = POWER_S0},
+
+	.gpu_3v_5v_en = {.gpio = GPU_3V_5V_EN, .function = GPIO_FUNC_HIGH, .flags = GPIO_OUTPUT_LOW, .power_domain = POWER_S5},
+
+	.hdr5 = {.block_type = GPUCFG_TYPE_PD, .block_length = sizeof(struct gpu_subsys_pd)},
+	.pd = {.gpu_pd_type = PD_TYPE_ETRON_EJ889I, .address = 0x60,
+			.flags = 0, .pdo = 0, .rdo = 0, .power_domain = POWER_S5,
+			.gpio_hpd = GPU_1H1_GPIO1_EC, .gpio_interrupt = GPU_1F2_I2C_S5_INT
+	},
+
+	.hdr6 = {.block_type = GPUCFG_TYPE_THERMAL_SENSOR, .block_length = sizeof(struct gpu_cfg_thermal)},
+	.therm = {.thermal_type = GPU_THERM_F75303, .address = 0x4D},
+
+	.hdr7 = {.block_type = GPUCFG_TYPE_CUSTOM_TEMP, .block_length = sizeof(struct gpu_cfg_custom_temp)},
+	.custom_temp = {.idx = 2, .temp_fan_off = C_TO_K(47), .temp_fan_max = C_TO_K(62)},
+
+	.hdr8 = {.block_type = GPUCFG_TYPE_SUBSYS, .block_length = sizeof(struct gpu_subsys_serial)},
+	.pcba_serial = {.gpu_subsys = GPU_PCB, .serial = {'F', 'R', 'A', 'G', 'M', 'A', 'S', 'P', '8', '1',
+					'3', '3', '1', 'P', 'C', 'B', '0', '0', '\0', '\0'},}
+};
+
+struct default_ssd_cfg {
+	struct gpu_cfg_descriptor descriptor;
+
+	struct gpu_block_header hdr0;
+	enum gpu_pcie_cfg pcie_cfg;
+
+	struct gpu_block_header hdr1;
+	struct gpu_cfg_fan fan0_cfg;
+
+	struct gpu_block_header hdr2;
+	struct gpu_cfg_fan fan1_cfg;
+
+	struct gpu_block_header hdr3;
+	enum gpu_vendor vendor;
+
+	struct gpu_block_header hdr4;
+	struct gpu_cfg_gpio     gpio0;
+	struct gpu_cfg_gpio     gpio1;
+	struct gpu_cfg_gpio     gpio2;
+	struct gpu_cfg_gpio     gpio3;
+	struct gpu_cfg_gpio     gpio_edpaux;
+	struct gpu_cfg_gpio     gpio_vsys;
+	struct gpu_cfg_gpio     gpio_fan;
+	struct gpu_cfg_gpio     gpu_3v_5v_en;
+
+} __packed;
+
+static struct default_ssd_cfg ssd_cfg = {
+	.descriptor = {
+		.magic = {0x32, 0xac, 0x00, 0x00},
+		.length = sizeof(struct gpu_cfg_descriptor),
+		.descriptor_version_major = 0,
+		.descriptor_version_minor = 1,
+		.hardware_version = 0x0008,
+		.hardware_revision = 0,
+		.serial = {'F', 'R', 'A', 'G', 'M', 'B', 'S', 'P', '8', '1',
+					'3', '3', '1', 'D', 'U', 'M', 'M', 'Y', '\0', '\0'},
+		.descriptor_length = sizeof(struct default_ssd_cfg) - sizeof(struct gpu_cfg_descriptor),
+		.descriptor_crc32 = 0,
+		.crc32 = 0
+	},
+	.hdr0 = {.block_type = GPUCFG_TYPE_PCIE, .block_length = sizeof(uint8_t)},
+	.pcie_cfg = PCIE_4X2,
+
+	.hdr1 = {.block_type = GPUCFG_TYPE_FAN, .block_length = sizeof(struct gpu_cfg_fan)},
+	.fan0_cfg = {.idx = 0, .flags = 0, .min_rpm = 1000, .start_rpm = 1000, .max_rpm = 3700},
+
+	.hdr2 = {.block_type = GPUCFG_TYPE_FAN, .block_length = sizeof(struct gpu_cfg_fan)},
+	.fan1_cfg = {.idx = 1, .flags = 0, .min_rpm = 1000, .start_rpm = 1000, .max_rpm = 3700},
+
+	.hdr3 = {.block_type = GPUCFG_TYPE_VENDOR, .block_length = sizeof(gpu_vendor)},
+	.vendor = GPU_SSD,
+
+	/* Power enable for SSD1 */
+	.hdr4 = {.block_type = GPUCFG_TYPE_GPIO, .block_length = sizeof(struct gpu_cfg_gpio) * 8},
+	.gpio0 = {.gpio = GPU_1G1_GPIO0_EC, .function = GPIO_FUNC_SSD1_POWER, .flags = GPIO_OUTPUT_LOW, .power_domain = POWER_S3},
+	/* Power enable for SSD2 */
+	.gpio1 = {.gpio = GPU_1H1_GPIO1_EC, .function = GPIO_FUNC_SSD2_POWER, .flags = GPIO_OUTPUT_LOW, .power_domain = POWER_S3},
+	/* UNUSED */
+	.gpio2 = {.gpio = GPU_2A2_GPIO2_EC, .function = GPIO_FUNC_UNUSED, .flags = GPIO_OUTPUT_LOW, .power_domain = POWER_G3},
+	/* UNUSED */
+	.gpio3 = {.gpio = GPU_2L7_GPIO3_EC, .function = GPIO_FUNC_UNUSED, .flags = GPIO_OUTPUT_LOW, .power_domain = POWER_G3},
+	/* set mux configuration on mainboard for SSD */
+	.gpio_edpaux = {.gpio = GPU_PCIE_MUX_SEL, .function = GPIO_FUNC_HIGH, .flags = GPIO_OUTPUT_LOW, .power_domain = POWER_S3},
+	/* GPU_VSYS_EN */
+	.gpio_vsys = {.gpio = GPU_VSYS_EN, .function = GPIO_FUNC_HIGH, .flags = GPIO_OUTPUT_LOW, .power_domain = POWER_S3},
+
+	.gpio_fan = {.gpio = GPU_FAN_EN, .function = GPIO_FUNC_HIGH, .flags = GPIO_OUTPUT_LOW, .power_domain = POWER_S0},
+
+	.gpu_3v_5v_en = {.gpio = GPU_3V_5V_EN, .function = GPIO_FUNC_HIGH, .flags = GPIO_OUTPUT_LOW, .power_domain = POWER_S5},
+};
+
+const struct gpio_dt_spec * gpu_gpio_to_dt(enum gpu_gpio_idx gpio_idx)
+{
+	switch (gpio_idx) {
+	case GPU_1G1_GPIO0_EC:
+		return GPIO_DT_FROM_NODELABEL(gpio_gpu_b_gpio00_ec);
+	case GPU_1H1_GPIO1_EC:
+		return GPIO_DT_FROM_NODELABEL(gpio_gpu_b_gpio01_ec);
+	case GPU_2A2_GPIO2_EC:
+		return GPIO_DT_FROM_NODELABEL(gpio_gpu_b_gpio02_ec);
+	case GPU_2L7_GPIO3_EC:
+		return GPIO_DT_FROM_NODELABEL(gpio_gpu_b_gpio03_ec);
+	case GPU_1F2_I2C_S5_INT:
+		return GPIO_DT_FROM_NODELABEL(gpio_gpu_i2c_s5_int);
+	case GPU_2B5_ALERTn:
+		return GPIO_DT_FROM_NODELABEL(gpio_gpu_alert_l);
+	case GPU_ECPWM_EN:
+		return GPIO_DT_FROM_NODELABEL(gpio_ec_pwm_en_l);
+	case GPU_EDP_MUX_SEL:
+		return GPIO_DT_FROM_NODELABEL(gpio_edp_mux_pwm_sw);
+	case GPU_PCIE_MUX_SEL: /* select between EDP AUX or SSD PCIE2 CLK*/
+		if (board_get_version() >= BOARD_VERSION_7)
+			return GPIO_DT_FROM_NODELABEL(gpio_ssd_gpu_sel);
+		return NULL;
+	case GPU_VSYS_EN:
+		return GPIO_DT_FROM_NODELABEL(gpio_gpu_vsys_en);
+	case GPU_VADP_EN:
+		return GPIO_DT_FROM_NODELABEL(gpio_gpu_vdap_en);
+	case GPU_3V_5V_EN:
+		return GPIO_DT_FROM_NODELABEL(gpio_gpu_3v_5v_en);
+	case GPU_FAN_EN:
+		if (board_get_version() >= BOARD_VERSION_8)
+			return GPIO_DT_FROM_NODELABEL(gpio_gpu_fan_en);
+		__fallthrough;
+	/* the following GPIOs cannot be controlled directly */
+	case GPU_1F3_MUX1:
+	case GPU_1G3_MUX2:
+	case GPU_1L1_DGPU_PWROK:
+	case GPU_1C3_ALW_CLK: /* ALW I2C CLOCK PIN to EC */
+	case GPU_1D3_ALW_DAT: /* ALW I2C DATA PIN to EC */
+	default:
+		return NULL;
+	}
+	return NULL;
+}
+
+const char * gpu_gpio_idx_to_name(enum gpu_gpio_idx idx)
+{
+	switch (idx) {
+	case GPU_GPIO_INVALID:
+		return "INVALID";
+	case GPU_1G1_GPIO0_EC:
+		return "GPIO0";
+	case GPU_1H1_GPIO1_EC:
+		return "GPIO1";
+	case GPU_2A2_GPIO2_EC:
+		return "GPIO2";
+	case GPU_2L7_GPIO3_EC:
+		return "GPIO3";
+	case GPU_2L5_TH_OVERTn:
+		return "OVERTn";
+	case GPU_1F2_I2C_S5_INT:
+		return "S5_INT";
+	case GPU_1L1_DGPU_PWROK:
+		return "PWROK";
+	case GPU_1C3_ALW_CLK:
+		return "CLK";
+	case GPU_1D3_ALW_DAT:
+		return "DAT";
+	case GPU_1F3_MUX1:
+		return "MUX1";
+	case GPU_1G3_MUX2:
+		return "MUX2";
+	case GPU_2B5_ALERTn:
+		return "ALERTn";
+	case GPU_ECPWM_EN:
+		return "ECPWM_EN";
+	case GPU_EDP_MUX_SEL:
+		return "EDP_MUX_SEL";
+	case GPU_PCIE_MUX_SEL:
+		return "PCIE_MUX_SEL";
+	case GPU_VSYS_EN:
+		return "VSYS_EN";
+	case GPU_VADP_EN:
+		return "VADP_EN";
+	case GPU_FAN_EN:
+		return "FAN_EN";
+	case GPU_3V_5V_EN:
+		return "GPU_3V_5V_EN";
+	default:
+		return "UNKNOWN IDX";
+	}
+}
+
+const char * gpu_gpio_fn_to_name(enum gpu_gpio_purpose p)
+{
+	switch (p) {
+	case GPIO_FUNC_UNUSED:
+	return "UNUSED";
+	case GPIO_FUNC_HIGH:
+		return "HIGH";
+	case GPIO_FUNC_TEMPFAULT:
+		return "TEMPFAULT";
+	case GPIO_FUNC_ACDC:
+		return "ACDC";
+	case GPIO_FUNC_HPD:
+		return "HPD";
+	case GPIO_FUNC_PD_INT:
+		return "PD_INT";
+	case GPIO_FUNC_SSD1_POWER:
+		return "SSD1_POWER";
+	case GPIO_FUNC_SSD2_POWER:
+		return "SSD2_POWER";
+	case GPIO_FUNC_EC_PWM_EN:
+		return "ECPWM_EN";
+	case GPIO_FUNC_EDP_MUX_SEL:
+		return "EDP_MUX_SEL";
+	case GPIO_FUNC_VSYS_EN:
+		return "VSYS_EN";
+	case GPIO_FUNC_VADP_EN:
+		return "VADP_EN";
+	case GPIO_FUNC_GPU_PWR:
+		return "GPUPWR";
+	default: 
+		return "UNKNOWN IDX";
+	}
+}
+
+
+bool gpu_present(void)
+{
+	switch (gpu_vendor) {
+		case GPU_AMD_R23M:
+			return true;
+		default:
+			return false;
+	}
+}
+
+void control_5valw_power(enum power_request_source_t pwr, bool enable)
+{
+	if (enable)
+		power_enable |= BIT(pwr);
+	else
+		power_enable &= ~BIT(pwr);
+
+	if (power_enable)
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_5valw_c_en), 1);
+	else
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_5valw_c_en), 0);
+}
+
+const struct gpio_int_config * gpu_gpio_to_dt_int(enum gpu_gpio_idx gpio_idx)
+{
+	switch (gpio_idx) {
+	/* case GPU_1G1_GPIO0_EC:
+		return GPIO_INT_FROM_NODELABEL(gpio_gpu_b_gpio00_ec); */
+	case GPU_1H1_GPIO1_EC:
+		return GPIO_INT_FROM_NODELABEL(int_dp_hot_plug);
+	/* case GPU_2A2_GPIO2_EC:
+		return GPIO_INT_FROM_NODELABEL(gpio_gpu_b_gpio02_ec);
+	case GPU_2L7_GPIO3_EC:
+		return GPIO_INT_FROM_NODELABEL(gpio_gpu_b_gpio03_ec); */
+	case GPU_1F2_I2C_S5_INT:
+		return GPIO_INT_FROM_NODELABEL(int_gpu_pd);
+	/* case GPU_2B5_ALERTn:
+		return GPIO_INT_FROM_NODELABEL(gpio_gpu_alert_l); */
+	default:
+		return NULL;
+	} 
+}
+
+
+void set_gpu_gpio(enum gpu_gpio_purpose gpiofn, int level)
+{
+	int i;
+	const struct gpio_dt_spec * dt_gpio;
+	enum power_state ps = power_get_state();
+
+	switch (ps) {
+	case POWER_G3S5:
+	case POWER_S3S5:
+		ps = POWER_S5;
+		break;
+	case POWER_S5S3:
+	case POWER_S0S3:
+	case POWER_S0ixS3:
+		ps = POWER_S3;
+		break;
+	case POWER_S3S0:
+	case POWER_S0ixS0:
+	case POWER_S3S0ix:
+		ps = POWER_S0;
+		break;
+	case POWER_S5G3:
+	case POWER_G3:
+		ps = POWER_G3;
+		break;
+	default:
+		break;
+	}
+
+	if (gpiofn >= GPIO_FUNC_MAX) {
+		CPRINTS("Unsupported GPIO %d", gpiofn);
+		return;
+	}
+	for(i = 0; i < GPU_GPIO_MAX; i++) {
+		if (gpu_gpio_cfgs[i].function == gpiofn) {
+			dt_gpio = gpu_gpio_to_dt(gpu_gpio_cfgs[i].gpio);
+			if (dt_gpio == NULL)
+				continue;
+			if (ps >= gpu_gpio_cfgs[i].power_domain) {
+				if (gpu_verbose)
+					CPRINTS("GPUGPIO %s %s=%d", gpu_gpio_idx_to_name(gpu_gpio_cfgs[i].gpio),
+						gpu_gpio_fn_to_name(gpu_gpio_cfgs[i].function), level);
+				gpio_pin_set_dt(dt_gpio, level);
+			} else {
+				gpio_pin_set_dt(dt_gpio, 0);
+			}
+		}
+	}
+}
+
+int get_gpu_gpio(enum gpu_gpio_purpose gpiofn)
+{
+	int i;
+	const struct gpio_dt_spec * dt_gpio;
+
+	if (gpiofn >= GPIO_FUNC_MAX) {
+		CPRINTS("Unsupported GPIO %d", gpiofn);
+		return -1;
+	}
+	for(i = 0; i < GPU_GPIO_MAX; i++) {
+		if (gpu_gpio_cfgs[i].function == gpiofn) {
+			dt_gpio = gpu_gpio_to_dt(gpu_gpio_cfgs[i].gpio);
+			if (dt_gpio == NULL)
+				continue;
+			return gpio_pin_get_dt(dt_gpio);
+		}
+	}
+	return -1;
+}
+void set_gpu_gpios_configuration(void)
+{
+	int i;
+	const struct gpio_dt_spec * dt_gpio;
+
+	for(i = 0; i < GPU_GPIO_MAX; i++) {
+		dt_gpio = gpu_gpio_to_dt(gpu_gpio_cfgs[i].gpio);
+		if (dt_gpio == NULL)
+			continue;
+		if (gpu_verbose)
+			CPRINTS("GPUGPIO CFG:%s %s=0x%X",
+						gpu_gpio_idx_to_name(gpu_gpio_cfgs[i].gpio),
+						gpu_gpio_fn_to_name(gpu_gpio_cfgs[i].function),
+						gpu_gpio_cfgs[i].flags);
+		gpio_pin_configure_dt(dt_gpio, gpu_gpio_cfgs[i].flags);
+	}
+}
+
+void set_gpu_gpio_powerstate(enum gpu_gpio_idx idx, enum power_state ps)
+{
+	const struct gpio_dt_spec * dt_gpio;
+
+	dt_gpio = gpu_gpio_to_dt(gpu_gpio_cfgs[idx].gpio);
+
+	if (dt_gpio == NULL)
+		return;
+
+	if (ps >= gpu_gpio_cfgs[idx].power_domain) {
+		if (gpu_gpio_cfgs[idx].function ==GPIO_FUNC_HIGH) {
+			if (gpio_pin_get_dt(dt_gpio) == 0) {
+				if (gpu_verbose)
+					CPRINTS("GPU %s=HIGH", gpu_gpio_idx_to_name(gpu_gpio_cfgs[idx].gpio));
+				if (idx == GPU_3V_5V_EN)
+					control_5valw_power(POWER_REQ_GPU_3V_5V, 1);
+				gpio_pin_set_dt(dt_gpio, 1);
+			}
+		}
+	} else {
+		if (gpio_pin_get_dt(dt_gpio) == 1) {
+			if (gpu_verbose)
+				CPRINTS("GPU %s=LOW", gpu_gpio_idx_to_name(gpu_gpio_cfgs[idx].gpio));
+			gpio_pin_set_dt(dt_gpio, 0);
+			if (idx == GPU_3V_5V_EN)
+				control_5valw_power(POWER_REQ_GPU_3V_5V, 0);
+		}
+	}
+}
+
+void set_gpu_gpios_powerstate(void)
+{
+	int i;
+	enum power_state ps = power_get_state();
+
+	switch (ps) {
+	case POWER_G3S5:
+	case POWER_S3S5:
+		ps = POWER_S5;
+		break;
+	case POWER_S5S3:
+	case POWER_S0S3:
+	case POWER_S0ixS3:
+		ps = POWER_S3;
+		break;
+	case POWER_S3S0:
+	case POWER_S0ixS0:
+	case POWER_S3S0ix:
+		ps = POWER_S0;
+		break;
+	case POWER_S5G3:
+	case POWER_G3:
+		ps = POWER_G3;
+		break;
+	default:
+		break;
+	}
+
+	/* Workaround: ensure gpu_3v_5v_en turn on first */
+	set_gpu_gpio_powerstate(GPU_3V_5V_EN, ps);
+
+	for(i = 0; i < GPU_GPIO_MAX; i++) {
+		set_gpu_gpio_powerstate(i, ps);
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, set_gpu_gpios_powerstate, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, set_gpu_gpios_powerstate, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, set_gpu_gpios_powerstate, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, set_gpu_gpios_powerstate, HOOK_PRIO_DEFAULT);
+
+void reset_mux_status(void)
+{
+	uint8_t gpu_status = *host_get_memmap(EC_CUSTOMIZED_MEMMAP_GPU_CONTROL);
+
+	/* When the system shuts down, the gpu mux needs to switch to iGPU */
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_edp_mux_pwm_sw), 0);
+	gpu_status &= 0xFC;
+	gpu_status &= ~GPU_MUX;
+	*host_get_memmap(EC_CUSTOMIZED_MEMMAP_GPU_CONTROL) = gpu_status;
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, reset_mux_status, HOOK_PRIO_DEFAULT);
+
+static void reset_smart_access_graphic(void)
+{
+	/* smart access graphic default should be hybrid mode */
+	if (chipset_in_state(CHIPSET_STATE_ON))
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_edp_mux_pwm_sw), 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESET, reset_smart_access_graphic, HOOK_PRIO_DEFAULT);
+
+int parse_gpu_header(void)
+{
+	uint32_t i;
+	int rv = EC_SUCCESS;
+	crc_t crc = crc_init();
+
+	address = 0x50;
+	rv = i2c_read_offset16_block(I2C_PORT_GPU0, address,
+								0,
+								(void *)&gpu_descriptor, sizeof(gpu_descriptor));
+	if (rv != EC_SUCCESS) {
+		CPRINTS("%s trying address 0x52", __func__);
+		address = 0x52;
+		rv = i2c_read_offset16_block(I2C_PORT_GPU0, address,
+									0,
+									(void *)&gpu_descriptor, sizeof(gpu_descriptor));
+
+		if (rv != EC_SUCCESS) {
+			CPRINTS("%s hdr read failed", __func__);
+			return EC_ERROR_INVAL;
+		}
+	}
+
+	crc = crc_update(crc, &gpu_descriptor, sizeof(struct gpu_cfg_descriptor) - sizeof(uint32_t));
+
+	for (i = 0; i < 4; i++) {
+		if (gpu_descriptor.magic[i] == 0xff) {
+			CPRINTS("magic invalid");
+			return EC_ERROR_CRC;
+		}
+	}
+
+	if (crc_finalize(crc) != gpu_descriptor.crc32) {
+		CPRINTS("GPU header crc fail!: %X != %X", crc_finalize(crc), gpu_descriptor.crc32);
+		return EC_ERROR_CRC;
+	}
+
+	if (gpu_descriptor.descriptor_version_major > SUPPORTED_DESCRIPTOR_MAJOR) {
+		CPRINTS("unsupported gpu major version %d", gpu_descriptor.descriptor_version_major);
+		return EC_ERROR_INVAL;
+	}
+
+	if (gpu_descriptor.descriptor_version_minor > SUPPORTED_DESCRIPTOR_MINOR &&
+		gpu_descriptor.descriptor_version_major <= SUPPORTED_DESCRIPTOR_MAJOR) {
+		CPRINTS("unsupported gpu minor version %d", gpu_descriptor.descriptor_version_minor);
+		return EC_ERROR_INVAL;
+	}
+
+	return EC_SUCCESS;
+
+}
+
+uint8_t load_from;
+int load_configuration_block(uint16_t offset, uint8_t *data, int len)
+{
+	int rv = EC_SUCCESS;
+	if (load_from == 0) {
+		rv = i2c_read_offset16_block(I2C_PORT_GPU0, address,
+									offset, data, len);
+	} else if (load_from == 1) {
+		memcpy(data, ((uint8_t *)&gpu_cfg) + offset, len);
+	} else if (load_from == 2) {
+		memcpy(data, ((uint8_t *)&ssd_cfg) + offset, len);
+	} else {
+		rv = EC_ERROR_INVAL;
+	}
+	return rv;
+}
+int parse_gpu_eeprom(void)
+{
+
+	int rv;
+	uint32_t i;
+	uint8_t * v;
+	int offset = 0;
+	crc_t crc = crc_init();
+	struct gpu_block_header hdr;
+	load_from = 0;
+	gpu_cfg_descriptor_valid = false;
+
+	rv = parse_gpu_header();
+
+	if (rv != EC_SUCCESS) {
+		/* run device detection */
+		/* check if GPU PD is present */
+		rv = i2c_read_offset16(I2C_PORT_GPU0, 0x60, 0x800E, &i, 1);
+		if (rv == EC_SUCCESS) {
+			/* assume R23M GPU */
+			CPRINTS("Detected EEPROM and PD: Defaulting to R23M");
+			memcpy(&gpu_descriptor, &gpu_cfg.descriptor, sizeof(struct gpu_cfg_descriptor));
+			load_from = 1;
+			rv = EC_SUCCESS;
+		} else {
+			rv = i2c_read8(I2C_PORT_GPU0, 0x50, 0x00, &i);
+			if (rv == EC_SUCCESS) {
+				CPRINTS("Detected blank EEPROM only: defaulting to dual ssd");
+				memcpy(&gpu_descriptor, &ssd_cfg.descriptor, sizeof(struct gpu_cfg_descriptor));
+
+				load_from = 2;
+				rv = EC_SUCCESS;
+			}
+		}
+	}
+
+	if (rv != EC_SUCCESS) {
+		return rv;
+	}
+
+	crc = crc_init();
+
+	offset = sizeof(gpu_descriptor);
+	while (offset < (gpu_descriptor.descriptor_length + sizeof(struct gpu_cfg_descriptor))) {
+		rv = load_configuration_block(offset,
+									(void *)&hdr, sizeof(hdr));
+		if (rv != EC_SUCCESS) {
+			CPRINTS("block read failed");
+			control_5valw_power(POWER_REQ_INIT, 0);
+			return EC_ERROR_INVAL;
+		}
+		crc = crc_update(crc, &hdr, sizeof(hdr));
+		offset += sizeof(hdr);
+
+		if (hdr.block_length > GPU_MAX_BLOCK_LEN) {
+			CPRINTS("ERR:block %d over length!",hdr.block_type);
+			offset += hdr.block_length;
+			continue;
+		}
+
+		if (gpu_verbose)
+			CPRINTS("GPUCFG Block:%d Len:%d", hdr.block_type, hdr.block_length);
+
+		rv = load_configuration_block(offset,
+									gpu_read_buff,
+									hdr.block_length);
+
+		crc = crc_update(crc, gpu_read_buff, hdr.block_length);
+
+		if (rv != EC_SUCCESS) {
+			CPRINTS("block read failed");
+			control_5valw_power(POWER_REQ_INIT, 0);
+			return EC_ERROR_INVAL;
+		}
+		switch (hdr.block_type) {
+		case GPUCFG_TYPE_GPIO:
+			{
+				for(v = gpu_read_buff; v < gpu_read_buff + hdr.block_length; v += sizeof(struct gpu_cfg_gpio)) {
+					struct gpu_cfg_gpio *gpiocfg = (struct gpu_cfg_gpio *)v;
+					if (gpiocfg->gpio < GPU_GPIO_MAX) {
+						memcpy(&gpu_gpio_cfgs[gpiocfg->gpio], gpiocfg, sizeof(struct gpu_cfg_gpio));
+					}
+				}
+			}
+			break;
+		case GPUCFG_TYPE_THERMAL_SENSOR:
+			struct gpu_cfg_thermal *tm = (struct gpu_cfg_thermal *)gpu_read_buff;
+			if (tm->thermal_type == GPU_THERM_F75303)
+			{
+				gpu_f75303_init(tm);
+			}
+			break;
+		case GPUCFG_TYPE_CUSTOM_TEMP:
+			struct gpu_cfg_custom_temp *tc = (struct gpu_cfg_custom_temp *)gpu_read_buff;
+			/* TODO dont hard code index here */
+			if (tc->idx < 8) {
+				thermal_params[tc->idx].temp_fan_max = tc->temp_fan_max;
+				thermal_params[tc->idx].temp_fan_off = tc->temp_fan_off;
+			}
+			break;
+		case GPUCFG_TYPE_FAN:
+			struct gpu_cfg_fan *fan = (struct gpu_cfg_fan *)gpu_read_buff;
+			if (fan->idx < 2) {
+				fan_configure_gpu(fan);
+			}
+			break;
+		case GPUCFG_TYPE_POWER:
+			break;
+		case GPUCFG_TYPE_BATTERY:
+			break;
+		case GPUCFG_TYPE_PCIE:
+			gpu_pcie_configuration = gpu_read_buff[0];
+			*host_get_memmap(EC_CUSTOMIZED_MEMMAP_GPU_CONTROL) =
+				(*host_get_memmap(EC_CUSTOMIZED_MEMMAP_GPU_CONTROL) & (~GPU_PCIE_MASK)) +
+				((gpu_pcie_configuration << 6) & GPU_PCIE_MASK);
+			break;
+		case GPUCFG_TYPE_VENDOR:
+			gpu_vendor = gpu_read_buff[0];
+			*host_get_memmap(EC_CUSTOMIZED_MEMMAP_GPU_TYPE) = gpu_read_buff[0];
+			if (gpu_vendor == GPU_AMD_R23M) {
+				*host_get_memmap(EC_CUSTOMIZED_MEMMAP_GPU_CONTROL) |= GPU_PRESENT;
+			}
+			
+		case GPUCFG_TYPE_DPMUX:
+			break;
+		case GPUCFG_TYPE_SUBSYS:
+			{
+				struct gpu_subsys_serial *subsys = (struct gpu_subsys_serial *)gpu_read_buff;
+				if (subsys->gpu_subsys && subsys->gpu_subsys < GPU_SUBSYS_MAX) {
+					memcpy(gpu_subsys_serials[subsys->gpu_subsys-1], subsys->serial, sizeof(subsys->serial));
+				}
+			}
+			break;
+		case GPUCFG_TYPE_PD:
+			{
+				struct gpu_subsys_pd *pd = (struct gpu_subsys_pd *)gpu_read_buff;
+				if (pd->gpu_pd_type == PD_TYPE_ETRON_EJ889I) {
+					ej889i_init(pd);
+				}
+			}
+			break;
+		default:
+			CPRINTS("descriptor block unknown type: %d", hdr.block_type);
+			control_5valw_power(POWER_REQ_INIT, 0);
+			return EC_ERROR_UNIMPLEMENTED;
+			break;
+		}
+		offset += hdr.block_length;
+	}
+	crc = crc_finalize(crc);
+	if (crc != gpu_descriptor.descriptor_crc32 && load_from == 0) {
+		CPRINTS("CRC fail!: %X != %X", crc, gpu_descriptor.descriptor_crc32);
+		control_5valw_power(POWER_REQ_INIT, 0);
+		return EC_ERROR_CRC;
+	}
+	gpu_cfg_descriptor_valid = true;
+	CPRINTS("GPU descriptor read complete");
+
+	return EC_SUCCESS;
+}
+
+int init_parse_gpu_eeprom(void)
+{
+	parse_gpu_eeprom();
+
+	set_gpu_gpios_configuration();
+
+	set_gpu_gpios_powerstate();
+
+	control_5valw_power(POWER_REQ_INIT, 0);
+
+	return EC_SUCCESS;
+}
+DECLARE_DEFERRED(init_parse_gpu_eeprom);
+
+void gpu_module_gpio_safe(void)
+{
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_gpu_b_gpio00_ec), 0);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_gpu_b_gpio01_ec), 0);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_gpu_b_gpio02_ec), 0);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_gpu_b_gpio03_ec), 0);
+
+	/* tristate all EC general purpose GPIOs */
+	gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_gpu_b_gpio00_ec), GPIO_INPUT);
+	gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_gpu_b_gpio01_ec), GPIO_INPUT);
+	gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_gpu_b_gpio02_ec), GPIO_INPUT);
+	gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_gpu_b_gpio03_ec), GPIO_INPUT);
+
+	if (board_get_version() >= BOARD_VERSION_7)
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ssd_gpu_sel), 0);
+	if (board_get_version() >= BOARD_VERSION_8)
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_gpu_fan_en), 0);
+
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_gpu_vsys_en), 0);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_gpu_3v_5v_en), 0);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_edp_mux_pwm_sw), 0);
+
+}
+void deinit_gpu_module(void)
+{
+	gpu_cfg_descriptor_valid = 0;
+	gpu_vendor = GPU_VENDOR_INITIALIZING;
+	address = 0x50;
+	memset(&gpu_descriptor, 0x00, sizeof(struct gpu_cfg_descriptor));
+	memset(gpu_subsys_serials, 0x00, sizeof(gpu_subsys_serials));
+	memset(gpu_gpio_cfgs, 0x00, sizeof(gpu_gpio_cfgs));
+
+	*host_get_memmap(EC_CUSTOMIZED_MEMMAP_GPU_CONTROL) =
+		(*host_get_memmap(EC_CUSTOMIZED_MEMMAP_GPU_CONTROL) & (~GPU_PCIE_MASK));
+	*host_get_memmap(EC_CUSTOMIZED_MEMMAP_GPU_TYPE) = GPU_VENDOR_INITIALIZING;
+	*host_get_memmap(EC_CUSTOMIZED_MEMMAP_GPU_CONTROL) &= ~GPU_PRESENT;
+
+	reset_mux_status();
+
+	gpu_f75303_init(NULL);
+
+	ej889i_init(NULL);
+
+	gpu_module_gpio_safe();
+
+	fan_configure_gpu(NULL);
+
+	/* reset to APU only defaults */
+	thermal_params[2].temp_fan_max = C_TO_K(62); /* QTH1 */
+	thermal_params[2].temp_fan_off = C_TO_K(47); /* QTH1 */
+
+}
+
+void init_gpu_module(void)
+{
+	deinit_gpu_module();
+
+	control_5valw_power(POWER_REQ_INIT, 1);
+
+	/* do not turn on the 5valw_c_en and gpu_3v_5v_en at the same time */
+	k_msleep(10);
+
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_gpu_3v_5v_en), 1);
+	/* wait for power to come up to GPU PD and EEPROM */
+	hook_call_deferred(&init_parse_gpu_eeprom_data, 150*MSEC);
+
+}
+
+void init_uma_fan(void)
+{
+	gpu_gpio_cfgs[0].gpio = GPU_FAN_EN;
+	gpu_gpio_cfgs[0].function = GPIO_FUNC_HIGH;
+	gpu_gpio_cfgs[0].flags = GPIO_OUTPUT_LOW;
+	gpu_gpio_cfgs[0].power_domain = POWER_S0;
+
+	set_gpu_gpios_configuration();
+	set_gpu_gpios_powerstate();
+}
+
+static enum ec_status get_gpu_serial(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_gpu_serial *p = args->params;
+	struct ec_response_get_gpu_serial *r = args->response;
+
+	parse_gpu_eeprom();
+
+	memset(r->serial, 0x00, GPU_SERIAL_LEN);
+	if (gpu_cfg_descriptor_valid) {
+		r->idx = p->idx;
+		r->valid = true;
+		if (p->idx == 0) {
+			memcpy(r->serial, gpu_descriptor.serial, sizeof(r->serial));
+		} else if (p->idx < GPU_SUBSYS_MAX) {
+			memcpy(r->serial, gpu_subsys_serials[p->idx-1], sizeof(r->serial));
+		}
+	} else if (gpu_fan_board_present()) {
+		r->idx  = 0;
+		r->valid = true;
+		memcpy(r->serial, "UMA FAN", sizeof("UMA FAN"));
+	} else {
+		r->idx  = 0;
+		r->valid = true;
+		memcpy(r->serial, "Not detected", sizeof("Not detected"));
+	}
+	args->response_size = sizeof(*r);
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_GET_GPU_SERIAL, get_gpu_serial, EC_VER_MASK(0));
+
+
+static enum ec_status ec_response_get_gpu_config(struct host_cmd_handler_args *args)
+{
+	struct ec_response_get_gpu_config *r = args->response;
+	if (!gpu_cfg_descriptor_valid) {
+		return EC_RES_UNAVAILABLE;
+	}
+
+	r->gpu_pcie_config = gpu_pcie_configuration;
+	r->gpu_vendor = gpu_vendor;
+
+	args->response_size = sizeof(*r);
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_GET_GPU_PCIE, ec_response_get_gpu_config, EC_VER_MASK(0));
+
+static int program_eeprom(const char * serial, struct gpu_cfg_descriptor * descriptor, size_t len)
+{
+	int rv;
+	crc_t crc;
+	size_t addr = 0;
+	int d, i;
+	CPRINTS("Programming EEPROM");
+	memset(descriptor->serial, 0x00, GPU_SERIAL_LEN);
+	strncpy(descriptor->serial, serial, GPU_SERIAL_LEN);
+
+	crc = crc_init();
+	crc = crc_update(crc, (uint8_t *)descriptor + sizeof(struct gpu_cfg_descriptor), len - sizeof(struct gpu_cfg_descriptor));
+	descriptor->descriptor_crc32 = crc_finalize(crc);
+
+	crc = crc_init();
+	crc = crc_update(crc, descriptor, sizeof(struct gpu_cfg_descriptor)-sizeof(uint32_t));
+	descriptor->crc32 = crc_finalize(crc);
+
+	for(addr = 0; addr < len; addr += 32) {
+		rv = i2c_write_offset16_block(I2C_PORT_GPU0, 0x50,
+									addr, (uint8_t *)descriptor + addr, MIN(len - addr, 32));
+		i = 0;
+		do {
+			k_msleep(5);
+			rv = i2c_read8(I2C_PORT_GPU0, 0x50, 0x00, &d);   
+		} while(++i < 32 && rv != EC_SUCCESS);
+	}
+	return rv;
+}
+
+static enum ec_status hc_program_gpu_eeprom(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_program_gpu_serial *p = args->params;
+	struct ec_response_program_gpu_serial *r = args->response;
+
+	if (p->magic == 0x0D) {
+		r->valid = 1;
+		/* copy PCBA serial to output struct */
+		if (gpu_cfg_descriptor_valid) {
+			memcpy(gpu_cfg.pcba_serial.serial, gpu_subsys_serials[0], GPU_SERIAL_LEN);
+		}
+		program_eeprom(p->serial, (void *)&gpu_cfg, sizeof(gpu_cfg));
+	} else if (p->magic == 0x55) {
+		r->valid = 1;
+		program_eeprom(p->serial, (void *)&ssd_cfg, sizeof(ssd_cfg));
+	} else {
+		r->valid = 0;
+	}
+	
+	args->response_size = sizeof(*r);
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_PROGRAM_GPU_EEPROM, hc_program_gpu_eeprom, EC_VER_MASK(0));
+
+/*******************************************************************************/
+/*                       EC console command debug writing GPU EEPROM           */
+/*******************************************************************************/
+static int cmd_gpucfg(int argc, const char **argv)
+{
+	struct gpu_cfg_descriptor descriptor; 
+	int i;
+	if (argc > 1) {
+		if (!strncmp(argv[1], "read", 4)) {
+			parse_gpu_eeprom();
+		} else if (!strncmp(argv[1], "write", 4)) {
+			/* write gpu SERIAL_NUMBER */
+			if (argc > 3) {
+				if (!strncmp(argv[2], "gpu", 3)) {
+					program_eeprom(argv[3], (void *)&gpu_cfg, sizeof(gpu_cfg));
+				} else if (!strncmp(argv[2], "ssd", 3)) {
+					program_eeprom(argv[3], (void *)&ssd_cfg, sizeof(ssd_cfg));
+				}
+			}
+		} else if (!strncmp(argv[1], "erase", 4)) {
+			memset(&descriptor, 0xFF, sizeof(struct gpu_cfg_descriptor));
+			i2c_write_offset16_block(I2C_PORT_GPU0, 0x50,
+									0x0000, (void *)&descriptor, sizeof(struct gpu_cfg_descriptor));
+			CPRINTS("ERASE");
+		} else if (!strncmp(argv[1], "verbose", 7)) {
+			CPRINTS("GPU VERBOSE");
+			gpu_verbose = 1;
+		}
+
+	} else {
+			CPRINTS("GPU Descriptor %s", gpu_cfg_descriptor_valid ? "Valid": "Invalid");
+			CPRINTS("  From %s", load_from == 0 ? "EEPROM" : load_from == 1 ? "GPUCFG" : "SSDCFG");
+			CPRINTS("  Header: V:%d.%d HW:0x%X SN:%s CRC:0x%X",
+					gpu_descriptor.descriptor_version_major,
+					gpu_descriptor.descriptor_version_minor,
+					gpu_descriptor.hardware_version,
+					gpu_descriptor.serial,
+					gpu_descriptor.crc32);
+			CPRINTS("    Len: %d Dcrc32:0x%X",
+					gpu_descriptor.descriptor_length,
+					gpu_descriptor.descriptor_crc32);
+
+			CPRINTS(" SN: %s", gpu_descriptor.serial);
+			for (i = 0; i < GPU_SUBSYS_MAX; i++) {
+				if (gpu_subsys_serials[i][0])
+					CPRINTS(" SubsysSN%d: %s", i, &gpu_subsys_serials[i][0]);
+			}
+
+			CPRINTS(" MMIO GPU_CONTROL=0x%X", *host_get_memmap(EC_CUSTOMIZED_MEMMAP_GPU_CONTROL));
+			CPRINTS(" MMIO GPU_TYPE   =0x%X", *host_get_memmap(EC_CUSTOMIZED_MEMMAP_GPU_TYPE));
+			CPRINTS(" Interposer");
+			CPRINTS("   LEFT: %d, RIGHT %d RAW %d, %d",
+				get_hardware_id(ADC_GPU_BOARD_ID_0),
+				get_hardware_id(ADC_GPU_BOARD_ID_1),
+				adc_read_channel(ADC_GPU_BOARD_ID_0),
+				adc_read_channel(ADC_GPU_BOARD_ID_1));
+
+			CPRINTS(" GPIOS");
+			CPRINTS("   GPIO0     %d", gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_gpu_b_gpio00_ec)));
+			CPRINTS("   GPIO1     %d", gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_gpu_b_gpio01_ec)));
+			CPRINTS("   GPIO2     %d", gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_gpu_b_gpio02_ec)));
+			CPRINTS("   GPIO3     %d", gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_gpu_b_gpio03_ec)));
+			CPRINTS("   S5_INT    %d", gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_gpu_i2c_s5_int)));
+			CPRINTS("   ALERTn    %d", gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_gpu_alert_l)));
+			CPRINTS("   EDPMUX    %d", gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_edp_mux_pwm_sw)));
+			CPRINTS("   SSDMUX    %d", gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_ssd_gpu_sel)));
+			CPRINTS("   VSYSEN    %d", gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_gpu_vsys_en)));
+			CPRINTS("   VADP_EN   %d", gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_gpu_vdap_en)));
+			CPRINTS("   FAN_EN    %d", gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_gpu_fan_en)));
+			CPRINTS("   GPUPWR_EN %d", gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_dgpu_pwr_en)));
+			CPRINTS("   ECPWM_EN  %d", gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_pwm_en_l)));
+			CPRINTS("   ALW_EN    %d", gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_gpu_3v_5v_en)));
+			CPRINTS("   BAY DOOR  %s", get_gpu_latch() ? "Closed" : "Open");
+			CPRINTS("   5VALW_REQ 0x%02x", power_enable);
+	}
+
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(gpucfg, cmd_gpucfg,
+			"[gpucfg read/write/erase/verbose]",
+			"read and write gpu descriptor");
diff --git a/zephyr/program/framework/lotus/src/gpu_f75303.c b/zephyr/program/framework/lotus/src/gpu_f75303.c
new file mode 100644
index 0000000000..9eb92f0c68
--- /dev/null
+++ b/zephyr/program/framework/lotus/src/gpu_f75303.c
@@ -0,0 +1,81 @@
+#include "gpio/gpio_int.h"
+#include "gpio.h"
+#include "gpu.h"
+#include "i2c.h"
+#include "system.h"
+#include "thermal.h"
+#include "gpu_configuration.h"
+#include "console.h"
+#include "hooks.h"
+#include "chipset.h"
+
+
+LOG_MODULE_REGISTER(gpu_f75303, LOG_LEVEL_DBG);
+
+
+#define GPU_F75303_I2C_ADDR_FLAGS 0x4D
+
+#define GPU_F75303_REG_LOCAL_ALERT   0x05
+#define GPU_F75303_REG_REMOTE1_ALERT 0x07
+#define GPU_F75303_REG_REMOTE2_ALERT 0x15
+
+#define GPU_F75303_REG_REMOTE1_THERM 0x19
+#define GPU_F75303_REG_REMOTE2_THERM 0x1A
+#define GPU_F75303_REG_LOCAL_THERM   0x21
+
+
+uint8_t gpu_f75303_address;
+
+void gpu_f75303_init(struct gpu_cfg_thermal * sensor)
+{
+    if (sensor) {
+        gpu_f75303_address = sensor->address;
+        gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_gpu_power_en));
+    } else {
+        if (gpu_f75303_address) {
+            gpu_f75303_address = 0;
+            gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_gpu_power_en));
+        }
+    }
+}
+
+bool gpu_f75303_present(void) {
+	return gpu_f75303_address != 0;
+}
+
+
+static void gpu_board_f75303_poweron_config(void)
+{
+	int idx, rv;
+	static const uint8_t temp[6] = {105, 105, 105, 110, 110, 110};
+	static const uint8_t reg_arr[6] = {
+		GPU_F75303_REG_LOCAL_ALERT,
+		GPU_F75303_REG_REMOTE1_ALERT,
+		GPU_F75303_REG_REMOTE2_ALERT,
+		GPU_F75303_REG_REMOTE1_THERM,
+		GPU_F75303_REG_REMOTE2_THERM,
+		GPU_F75303_REG_LOCAL_THERM,
+	};
+
+	if (gpu_f75303_present() && chipset_in_state(CHIPSET_STATE_ON)) {
+		for (idx = 0; idx < sizeof(reg_arr); idx++) {
+			rv = i2c_write8(I2C_PORT_GPU0, GPU_F75303_I2C_ADDR_FLAGS,
+					reg_arr[idx], temp[idx]);
+
+			if (rv != EC_SUCCESS)
+				LOG_INF("gpu f75303 init reg 0x%02x failed", reg_arr[idx]);
+
+			k_msleep(1);
+		}
+		LOG_INF("GPU BOCO Exit");
+	}
+}
+DECLARE_DEFERRED(gpu_board_f75303_poweron_config);
+
+void gpu_power_enable_handler(void)
+{
+	/* we needs to re-initial the thermal sensor and gpu when gpu power enable */
+	if (gpu_f75303_address && gpu_power_enable())
+		hook_call_deferred(&gpu_board_f75303_poweron_config_data, 500 * MSEC);
+
+}
\ No newline at end of file
diff --git a/zephyr/program/framework/lotus/src/input_module.c b/zephyr/program/framework/lotus/src/input_module.c
new file mode 100644
index 0000000000..eaaa3fda4e
--- /dev/null
+++ b/zephyr/program/framework/lotus/src/input_module.c
@@ -0,0 +1,417 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <atomic.h>
+#include <zephyr/init.h>
+#include "gpio/gpio_int.h"
+#include "board_host_command.h"
+#include "chipset.h"
+#include "console.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "input_module.h"
+#include "task.h"
+#include "util.h"
+#include "zephyr_console_shim.h"
+#include <zephyr/devicetree.h>
+#include <zephyr/logging/log.h>
+
+#include "board_adc.h"
+#include "flash_storage.h"
+#include "lid_switch.h"
+#include "hid_device.h"
+
+LOG_MODULE_REGISTER(inputmodule, LOG_LEVEL_INF);
+#define INPUT_MODULE_POLL_INTERVAL 10*MSEC
+#define INPUT_MODULE_POWER_ON_DELAY (300*MSEC)
+#define INPUT_MODULE_MUX_DELAY_US 2
+
+int oc_count;
+int force_on;
+int detect_mode;
+int hub_board_id[8];	/* EC console Debug use */
+enum input_deck_state deck_state;
+
+void module_oc_interrupt(enum gpio_signal signal)
+{
+    oc_count++;
+}
+
+void set_detect_mode(int mode)
+{
+	detect_mode = mode;
+}
+
+int get_detect_mode(void)
+{
+	return detect_mode;
+}
+
+
+static void set_hub_mux(uint8_t input)
+{
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_mux_a0),
+		((input & BIT(0)) >> 0));
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_mux_a1),
+		((input & BIT(1)) >> 1));
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_mux_a2),
+		((input & BIT(2)) >> 2));
+}
+
+static void scan_c_deck(bool full_scan)
+{
+    int i;
+	if (full_scan) {
+		for (i = 0; i < 8; i++) {
+			/* Switch the mux */
+			set_hub_mux(i);
+			/*
+			 * In the specification table Switching Characteristics over Operating
+			 * range the maximum Bus Select Time needs 6.6 ns, so delay a little
+			 */
+			usleep(INPUT_MODULE_MUX_DELAY_US);
+
+			hub_board_id[i] = get_hardware_id(ADC_HUB_BOARD_ID);
+		}
+	} else {
+		set_hub_mux(TOUCHPAD);
+		usleep(INPUT_MODULE_MUX_DELAY_US);
+		hub_board_id[TOUCHPAD] = get_hardware_id(ADC_HUB_BOARD_ID);
+	}
+	/* Turn off hub mux pins*/
+	set_hub_mux(TOP_ROW_NOT_CONNECTED);
+}
+
+static void enable_touchpad_emulate(int enable)
+{
+	static int is_emulate = 1; /* will register the hid target in hid_device.c */
+	int rv;
+
+	/**
+	 * TODO: if register/unregister fail, need to retry the register
+	 */
+	if (is_emulate != enable) {
+		if (enable) {
+			rv = hid_target_register(DEVICE_DT_GET(DT_NODELABEL(i2chid2)));
+			LOG_INF("hid target register:%d", rv);
+		} else {
+			rv = hid_target_unregister(DEVICE_DT_GET(DT_NODELABEL(i2chid2)));
+			LOG_INF("hid target unregister:%d", rv);
+		}
+		is_emulate = enable;
+	}
+}
+
+static void board_input_module_init(void)
+{
+	/* need to wait bios_function_init() to update detect mode */
+	if (detect_mode == 0x02)
+		deck_state = DECK_FORCE_ON;
+	else if (detect_mode == 0x04)
+		deck_state = DECK_FORCE_OFF;
+	else {
+		deck_state = DECK_OFF;
+	}
+}
+DECLARE_HOOK(HOOK_INIT, board_input_module_init, HOOK_PRIO_DEFAULT + 2);
+
+
+bool input_deck_is_fully_populated(void)
+{
+	int i;
+
+	if (hub_board_id[HUBBOARD] == INPUT_MODULE_SHORT ||
+		hub_board_id[HUBBOARD] == INPUT_MODULE_DISCONNECTED) {
+		return false;
+	}
+	for (i = 0; i <= TOP_ROW_4;) {
+		switch (hub_board_id[i]) {
+		case INPUT_MODULE_FULL_WIDTH:
+			i += 5;
+			break;
+		case INPUT_MODULE_GENERIC_A:
+		case INPUT_MODULE_KEYBOARD_A:
+			i += 3;
+			break;
+		case INPUT_MODULE_GENERIC_B:
+		case INPUT_MODULE_KEYBOARD_B:
+			i += 2;
+			break;
+		case INPUT_MODULE_GENERIC_C:
+			i++;
+			break;
+		default:
+			return false;
+		}
+	}
+
+	if (hub_board_id[TOUCHPAD] != INPUT_MODULE_TOUCHPAD) {
+		return false;
+	}
+
+	return true;
+}
+
+/* Make sure the inputdeck is sleeping when lid is closed */
+static void inputdeck_lid_change(void)
+{
+	/* If suspend or off we don't want to turn on input module LEDs even if the lid is open */
+	if (!chipset_in_state(CHIPSET_STATE_ON))
+		return;
+
+	if (lid_is_open()) {
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_sleep_l), 1);
+	} else {
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_sleep_l), 0);
+	}
+
+}
+DECLARE_HOOK(HOOK_LID_CHANGE, inputdeck_lid_change, HOOK_PRIO_DEFAULT);
+
+
+static void poll_c_deck(void);
+DECLARE_DEFERRED(poll_c_deck);
+static void poll_c_deck(void)
+{
+	static int turning_on_count;
+	static int current_adc_ch = 0;
+
+	hub_board_id[current_adc_ch] = get_hardware_id(ADC_HUB_BOARD_ID);
+	current_adc_ch = (current_adc_ch + 1) % 8;
+	set_hub_mux(current_adc_ch);
+
+	if (current_adc_ch != 0) {
+		hook_call_deferred(&poll_c_deck_data, INPUT_MODULE_POLL_INTERVAL);
+		return;
+	}
+	switch (deck_state) {
+	case DECK_OFF:
+		break;
+	case DECK_DISCONNECTED:
+		/* TODO only poll touchpad and currently connected B1/C1 modules
+		 * if c deck state is ON as these must be removed first
+		 */
+		if (input_deck_is_fully_populated()) {
+			turning_on_count = 0;
+			deck_state = DECK_TURNING_ON;
+		} else {
+			enable_touchpad_emulate(1);
+		}
+		break;
+	case DECK_TURNING_ON:
+		turning_on_count++;
+		if (input_deck_is_fully_populated() &&
+			turning_on_count > (INPUT_MODULE_POWER_ON_DELAY / (INPUT_MODULE_POLL_INTERVAL*8))) {
+			enable_touchpad_emulate(0);
+			gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_hub_b_pwr_en), 1);
+			deck_state = DECK_ON;
+			LOG_INF("Input modules on");
+		} else if (hub_board_id[TOUCHPAD] != INPUT_MODULE_TOUCHPAD) {
+			enable_touchpad_emulate(1);
+			deck_state = DECK_DISCONNECTED;
+		}
+		break;
+	case DECK_ON:
+		/* TODO Add lid detection,
+		 * if lid is closed input modules cannot be removed
+		 */
+		if (!input_deck_is_fully_populated()) {
+			gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_hub_b_pwr_en), 0);
+			/* enable TP emulation */
+			enable_touchpad_emulate(1);
+			deck_state = DECK_DISCONNECTED;
+			LOG_INF("Input modules off");
+		}
+		break;
+	case DECK_FORCE_ON:
+		enable_touchpad_emulate(0);
+		break;
+	case DECK_FORCE_OFF:
+		enable_touchpad_emulate(1);
+		break;
+	default:
+		break;
+	}
+
+	hook_call_deferred(&poll_c_deck_data, INPUT_MODULE_POLL_INTERVAL);
+}
+
+static void input_modules_powerup(void)
+{
+	if (deck_state == DECK_FORCE_ON)
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_hub_b_pwr_en), 1);
+	else if (deck_state != DECK_FORCE_ON && deck_state != DECK_FORCE_OFF)
+		deck_state = DECK_DISCONNECTED;
+
+	hook_call_deferred(&poll_c_deck_data, INPUT_MODULE_POLL_INTERVAL);
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, input_modules_powerup, HOOK_PRIO_DEFAULT);
+
+void input_modules_reset(void)
+{
+	input_modules_powerdown();
+	input_modules_powerup();
+}
+
+void input_modules_powerdown(void)
+{
+	if (deck_state == DECK_FORCE_ON)
+		 gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_hub_b_pwr_en), 0);
+	else if (deck_state != DECK_FORCE_ON && deck_state != DECK_FORCE_OFF) {
+		deck_state = DECK_OFF;
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_hub_b_pwr_en), 0);
+		/* Hub mux input 6 is NC, so lower power draw  by disconnecting all PD */
+		set_hub_mux(TOP_ROW_NOT_CONNECTED);
+	}
+
+	hook_call_deferred(&poll_c_deck_data, -1);
+}
+
+int get_deck_state(void)
+{
+	return deck_state;
+}
+
+/* Host command */
+static enum ec_status check_deck_state(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_deck_state *p = args->params;
+	struct ec_response_deck_state *r = args->response;
+	int idx;
+
+	if ((get_detect_mode() != p->mode) && (p->mode != 0x00)) {
+		/* set mode */
+		if (p->mode == 0x01) {
+			deck_state = DECK_DISCONNECTED;
+			gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_hub_b_pwr_en), 0);
+		} else if (p->mode == 0x02) {
+			deck_state = DECK_FORCE_ON;
+			gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_hub_b_pwr_en), 1);
+		} else if (p->mode == 0x04) {
+			deck_state = DECK_FORCE_OFF;
+			gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_hub_b_pwr_en), 0);
+		}
+
+		set_detect_mode(p->mode);
+	}
+
+	/* return deck status */
+	for (idx = 0; idx < 8; idx++)
+		r->input_deck_board_id[idx] = (uint8_t)hub_board_id[idx];
+
+	r->deck_state = deck_state;
+
+	args->response_size = sizeof(*r);
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_CHECK_DECK_STATE, check_deck_state, EC_VER_MASK(0));
+
+/* EC console command */
+static int inputdeck_cmd(int argc, const char **argv)
+{
+	int i, mv, id;
+	static const char * const deck_states[] = {
+		"OFF", "DISCONNECTED", "TURNING_ON", "ON", "FORCE_OFF", "FORCE_ON", "NO_DETECTION"
+	};
+
+	if (argc >= 2) {
+		if (!strncmp(argv[1], "on", 2)) {
+			gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_hub_b_pwr_en), 1);
+			ccprintf("Forcing Input modules on\n");
+			deck_state = DECK_FORCE_ON;
+		} else if (!strncmp(argv[1], "off", 3)) {
+			gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_hub_b_pwr_en), 0);
+			deck_state = DECK_FORCE_OFF;
+		} else if (!strncmp(argv[1], "auto", 4)) {
+			gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_hub_b_pwr_en), 0);
+			deck_state = DECK_DISCONNECTED;
+		} else if (!strncmp(argv[1], "nodetection", 4)) {
+			deck_state = DECK_NO_DETECTION;
+		}
+	}
+	scan_c_deck(true);
+	ccprintf("Deck state: %s\n", deck_states[deck_state]);
+	for (i = 0; i < 8; i++) {
+			/* Switch the mux */
+			set_hub_mux(i);
+			/*
+			 * In the specification table Switching Characteristics over Operating
+			 * range the maximum Bus Select Time needs 6.6 ns, so delay a little
+			 */
+			usleep(INPUT_MODULE_MUX_DELAY_US);
+
+			id = get_hardware_id(ADC_HUB_BOARD_ID);
+			mv = adc_read_channel(ADC_HUB_BOARD_ID);
+			ccprintf("    C-Deck status %d = %d %d mV", i, id, mv);
+			switch (i) {
+			case TOP_ROW_0:
+				ccprintf(" [X - -    - -]");
+				break;
+			case TOP_ROW_1:
+				ccprintf(" [- X -    - -]");
+				break;
+			case TOP_ROW_2:
+				ccprintf(" [- - X    - -]");
+				break;
+			case TOP_ROW_3:
+				ccprintf(" [- - -    X -]");
+				break;
+			case TOP_ROW_4:
+				ccprintf(" [- - -    - X]");
+				break;
+			case TOUCHPAD:
+				ccprintf(" [Touchpad    ]");
+				break;
+			case TOP_ROW_NOT_CONNECTED:
+				ccprintf(" [Toprow disc.]");
+				break;
+			case HUBBOARD:
+				ccprintf("  [Hubboard    ]");
+				break;
+			default:
+				break;
+			}
+			switch (id) {
+			case INPUT_MODULE_SHORT:
+				ccprintf(" [Short]\n");
+				break;
+			case INPUT_MODULE_FULL_WIDTH:
+				ccprintf(" [Generic Full Width]\n");
+				break;
+			case INPUT_MODULE_GENERIC_A:
+				ccprintf(" [Generic A]\n");
+				break;
+			case INPUT_MODULE_GENERIC_B:
+				ccprintf(" [Generic B]\n");
+				break;
+			case INPUT_MODULE_GENERIC_C:
+				ccprintf(" [Generic C]\n");
+				break;
+			case INPUT_MODULE_KEYBOARD_B:
+				ccprintf(" [Keyboard B]\n");
+				break;
+			case INPUT_MODULE_KEYBOARD_A:
+				ccprintf(" [Keyboard A]\n");
+				break;
+			case INPUT_MODULE_DISCONNECTED:
+				ccprintf(" [Disconnected]\n");
+				break;
+			case INPUT_MODULE_TOUCHPAD:
+				ccprintf(" [Touchpad]\n");
+				break;
+			default:
+				ccprintf(" [Reserved]\n");
+				break;
+			}
+		}
+
+	ccprintf("Input module Overcurrent Events: %d\n", oc_count);
+	return EC_SUCCESS;
+}
+
+DECLARE_CONSOLE_COMMAND(inputdeck, inputdeck_cmd, "[on/off/auto/nodetection]",
+			"Input modules power sequence control");
diff --git a/zephyr/program/framework/lotus/src/power_button_x86.c b/zephyr/program/framework/lotus/src/power_button_x86.c
new file mode 100644
index 0000000000..e18b267116
--- /dev/null
+++ b/zephyr/program/framework/lotus/src/power_button_x86.c
@@ -0,0 +1,586 @@
+/* Copyright 2013 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Power button state machine for x86 platforms */
+
+#include "board_adc.h"
+#include "board_function.h"
+#include "charge_state.h"
+#include "customized_shared_memory.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "extpower.h"
+#include "diagnostics.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "power_button.h"
+#include "power_sequence.h"
+#include "switch.h"
+#include "system.h"
+#include "task.h"
+#include "timer.h"
+#include "util.h"
+
+/* Console output macros */
+#define CPUTS(outstr) cputs(CC_SWITCH, outstr)
+#define CPRINTS(format, args...) cprints(CC_SWITCH, format, ##args)
+
+/*
+ * x86 chipsets have a hardware timer on the power button input which causes
+ * them to reset when the button is pressed for more than 4 seconds.  This is
+ * problematic for Chrome OS, which needs more time than that to transition
+ * through the lock and logout screens.  So when the system is on, we need to
+ * stretch the power button signal so that the chipset will hard-reboot after 8
+ * seconds instead of 4.
+ *
+ * When the button is pressed, we initially send a short pulse (t0); this
+ * allows the chipset to process its initial power button interrupt and do
+ * things like wake from suspend.  We then deassert the power button signal to
+ * the chipset for (t1 = 4 sec - t0), which keeps the chipset from starting its
+ * hard reset timer.  If the power button is still pressed after this period,
+ * we again assert the power button signal for the remainder of the press
+ * duration.  Since (t0+t1) causes a 4-second offset, the hard reset timeout in
+ * the chipset triggers after 8 seconds as desired.
+ *
+ *   PWRBTN#   ---                                          ----
+ *     to EC     |__________________________________________|
+ *
+ *
+ *   PWRBTN#   ---  ---------                               ----
+ *    to PCH     |__|       |_______________________________|
+ *                t0    t1  |    t2    |     t3    |
+ *
+ *   scan code   |                                          |
+ *    to host    v                                          v
+ *     @S0   make code                                 break code
+ */
+#define PWRBTN_DELAY_INIT (5 * MSEC) /* 5ms to wait VALW power rail ready*/
+#define PWRBTN_DELAY_T0 (32 * MSEC) /* 32ms (PCH requires >16ms) */
+#define PWRBTN_DELAY_T1 (4 * SECOND - PWRBTN_DELAY_T0) /* 4 secs - t0 */
+#define PWRBTN_DELAY_T2 (4 * SECOND) /* Force CPU to G3 */
+#define PWRBTN_DELAY_T3 (4 * SECOND) /* EC reset */
+/*
+ * Length of time to stretch initial power button press to give chipset a
+ * chance to wake up (~100ms) and react to the press (~16ms).  Also used as
+ * pulse length for simulated power button presses when the system is off.
+ */
+#define PWRBTN_INITIAL_US (200 * MSEC)
+
+enum power_button_state {
+	/* Button up; state machine idle */
+	PWRBTN_STATE_IDLE = 0,
+	/* Button pressed; debouncing done */
+	PWRBTN_STATE_PRESSED,
+	/* Button down, chipset on; sending initial short pulse */
+	PWRBTN_STATE_T0,
+	/* Button down, chipset on; delaying until we should reassert signal */
+	PWRBTN_STATE_T1,
+	/* Button down, signal asserted to chipset */
+	PWRBTN_STATE_HELD,
+	/* Force pulse due to lid-open event */
+	PWRBTN_STATE_LID_OPEN,
+	/* Button released; debouncing done */
+	PWRBTN_STATE_RELEASED,
+	/* Ignore next button release */
+	PWRBTN_STATE_EAT_RELEASE,
+	/*
+	 * Need to power on system after init, but waiting to find out if
+	 * sufficient battery power.
+	 */
+	PWRBTN_STATE_INIT_ON,
+	/* Forced pulse at EC boot due to keyboard controlled reset */
+	PWRBTN_STATE_BOOT_KB_RESET,
+	/* Power button pressed when chipset was off; stretching pulse */
+	PWRBTN_STATE_WAS_OFF,
+	/* Power button pressed keep long time; reset EC */
+	PWRBTN_STATE_NEED_RESET,
+	/* Power button press keep long time; force shutdown */
+	PWRBTN_STATE_NEED_SHUTDOWN,
+};
+static enum power_button_state pwrbtn_state = PWRBTN_STATE_IDLE;
+
+static const char *const state_names[] = {
+	"idle",	    "pressed",	   "t0",      "t1",	  "held",    "lid-open",
+	"released", "eat-release", "init-on", "recovery", "was-off", "need-reset",
+	"need-shutdown",
+};
+
+/*
+ * Time for next state transition of power button state machine, or 0 if the
+ * state doesn't have a timeout.
+ */
+static uint64_t tnext_state;
+
+/*
+ * Record the time when power button task starts. It can be used by any code
+ * path that needs to compare the current time with power button task start time
+ * to identify any timeouts e.g. PB state machine checks current time to
+ * identify if it should wait more for charger and battery to be initialized. In
+ * case of recovery using buttons (where the user could be holding the buttons
+ * for >30seconds), it is not right to compare current time with the time when
+ * EC was reset since the tasks would not have started. Hence, this variable is
+ * being added to record the time at which power button task starts.
+ */
+static uint64_t tpb_task_start;
+
+/*
+ * Determines whether to execute power button pulse (t0 stage)
+ */
+static int power_button_pulse_enabled = 1;
+
+static void set_pwrbtn_to_pch(int high, int init)
+{
+	/*
+	 * If the battery is discharging and low enough we'd shut down the
+	 * system, don't press the power button. Also, don't press the
+	 * power button if the battery is charging but the battery level
+	 * is too low.
+	 */
+#ifdef CONFIG_CHARGER
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF) && !high &&
+	    (charge_want_shutdown() || charge_prevent_power_on(!init))) {
+		CPRINTS("PB PCH pwrbtn ignored due to battery level");
+		high = 1;
+	}
+#endif
+	gpio_set_level(GPIO_PCH_PWRBTN_L, high);
+}
+
+void power_button_pch_release(void)
+{
+	CPRINTS("PB PCH force release");
+
+	/* Deassert power button signal to PCH */
+	set_pwrbtn_to_pch(1, 0);
+
+	/*
+	 * If power button is actually pressed, eat the next release so we
+	 * don't send an extra release.
+	 */
+	if (power_button_is_pressed())
+		pwrbtn_state = PWRBTN_STATE_EAT_RELEASE;
+	else
+		pwrbtn_state = PWRBTN_STATE_IDLE;
+}
+
+void power_button_pch_pulse(void)
+{
+	CPRINTS("PB PCH pulse");
+
+	chipset_exit_hard_off();
+	set_pwrbtn_to_pch(0, 0);
+	pwrbtn_state = PWRBTN_STATE_LID_OPEN;
+	tnext_state = get_time().val + PWRBTN_INITIAL_US;
+	task_wake(TASK_ID_POWERBTN);
+}
+
+/**
+ * Handle debounced power button down.
+ */
+static void power_button_pressed(uint64_t tnow)
+{
+	CPRINTS("PB pressed");
+	pwrbtn_state = PWRBTN_STATE_PRESSED;
+	tnext_state = tnow;
+}
+
+/**
+ * Handle debounced power button up.
+ */
+static void power_button_released(uint64_t tnow)
+{
+	CPRINTS("PB released");
+	pwrbtn_state = PWRBTN_STATE_RELEASED;
+	tnext_state = tnow;
+}
+
+/**
+ * Set initial power button state.
+ */
+static void set_initial_pwrbtn_state(void)
+{
+	uint32_t reset_flags = system_get_reset_flags();
+
+	if (reset_flags == EC_RESET_FLAG_HARD) {
+		pwrbtn_state = PWRBTN_STATE_INIT_ON;
+		CPRINTS("PB init-on after updating firmware");
+	} else if (((reset_flags & EC_RESET_FLAG_HIBERNATE) == EC_RESET_FLAG_HIBERNATE) &&
+		(gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_hw_acav_in)) == 0)) {
+		/**
+		 * EC needs to auto power on after exiting the hibernate mode w/o external power
+		 */
+		pwrbtn_state = PWRBTN_STATE_INIT_ON;
+		CPRINTS("PB init power on");
+	} else if (ac_boot_status() &&
+		(gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_hw_acav_in)) == 1)) {
+
+		/**
+		 * Only the developer will trigger the reset pin or soft flags.
+		 * We don't want the system to power automatically if we reset
+		 * the EC during development.
+		 */
+		if (!!(reset_flags & EC_RESET_FLAG_SOFT) ||
+			!!(reset_flags & EC_RESET_FLAG_RESET_PIN))
+			return;
+
+		/* BIOS setup AC attach power on */
+		pwrbtn_state = PWRBTN_STATE_INIT_ON;
+		CPRINTS("PB init AC attach on");
+	} else {
+		pwrbtn_state = PWRBTN_STATE_IDLE;
+		CPRINTS("PB idle");
+	}
+}
+
+/**
+ * auto power on system when AC plug-in
+ */
+static void board_extpower(void)
+{
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
+		extpower_is_present() && ac_boot_status()) {
+		CPRINTS("Power on from boot on AC present");
+		power_button_pch_pulse();
+	}
+}
+DECLARE_HOOK(HOOK_AC_CHANGE, board_extpower, HOOK_PRIO_DEFAULT);
+
+/**
+ * Power button state machine.
+ *
+ * @param tnow		Current time from usec counter
+ */
+static void state_machine(uint64_t tnow)
+{
+	/* Not the time to move onto next state */
+	if (tnow < tnext_state)
+		return;
+
+	/* States last forever unless otherwise specified */
+	tnext_state = 0;
+
+	switch (pwrbtn_state) {
+	case PWRBTN_STATE_PRESSED:
+		/* chipset exit hard off function only executes at G3 state */
+		if (chipset_in_state(CHIPSET_STATE_HARD_OFF)) {
+			/*
+			 * Power button out signal implements in power_sequence.c,
+			 * just call the exit hard off start to run the state mechine.
+			 */
+			reset_diagnostics();
+			chipset_exit_hard_off();
+			pwrbtn_state = PWRBTN_STATE_IDLE;
+		} else {
+			/*
+			 * when in preOS still need send power button signal
+			 * until ACPI driver ready
+			 */
+			if (*host_get_memmap(EC_CUSTOMIZED_MEMMAP_SYSTEM_FLAGS)
+				& ACPI_DRIVER_READY) {
+				/*
+				 * When chipset is on and ACPI driver ready,
+				 * we will send the SCI event to trigger modern standby.
+				 */
+				tnext_state = tnow + PWRBTN_DELAY_T1;
+				pwrbtn_state = PWRBTN_STATE_T1;
+			} else {
+				tnext_state = tnow + PWRBTN_DELAY_T0;
+				pwrbtn_state = PWRBTN_STATE_T0;
+				set_pwrbtn_to_pch(0, 0);
+				if (chipset_in_state(CHIPSET_STATE_ON)) {
+					/**
+					 * System in EFI mode (S0), press power button to shutdown
+					 * the system and cancel the diagnostics.
+					 */
+					cancel_diagnostics();
+				} else if (chipset_in_state(CHIPSET_STATE_SOFT_OFF))
+					/**
+					 * System in S5 state, press power button to start up the
+					 * system and reset the diagnostics.
+					 */
+					reset_diagnostics();
+
+			}
+		}
+		break;
+	case PWRBTN_STATE_T0:
+		tnext_state = tnow + PWRBTN_DELAY_T1;
+		pwrbtn_state = PWRBTN_STATE_T1;
+		set_pwrbtn_to_pch(1, 0);
+		break;
+	case PWRBTN_STATE_T1:
+		/*
+		 * If the chipset is already off, don't tell it the power
+		 * button is down; it'll just cause the chipset to turn on
+		 * again.
+		 */
+		if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+			CPRINTS("PB chipset already off");
+		else
+			set_pwrbtn_to_pch(0, 0);
+		pwrbtn_state = PWRBTN_STATE_HELD;
+		break;
+	case PWRBTN_STATE_RELEASED:
+	case PWRBTN_STATE_LID_OPEN:
+		set_pwrbtn_to_pch(1, 0);
+		pwrbtn_state = PWRBTN_STATE_IDLE;
+		break;
+	case PWRBTN_STATE_INIT_ON:
+
+		/*
+		 * Before attempting to power the system on, we need to allow
+		 * time for charger, battery and USB-C PD initialization to be
+		 * ready to supply sufficient power. Check every 100
+		 * milliseconds, and give up CONFIG_POWER_BUTTON_INIT_TIMEOUT
+		 * seconds after the PB task was started. Here, it is
+		 * important to check the current time against PB task start
+		 * time to prevent unnecessary timeouts happening in recovery
+		 * case where the tasks could start as late as 30 seconds
+		 * after EC reset.
+		 */
+
+		if (!IS_ENABLED(CONFIG_CHARGER) || charge_prevent_power_on(0)) {
+			if (tnow >
+			    (tpb_task_start +
+			     CONFIG_POWER_BUTTON_INIT_TIMEOUT * SECOND)) {
+				pwrbtn_state = PWRBTN_STATE_IDLE;
+				break;
+			}
+
+			if (IS_ENABLED(CONFIG_CHARGER)) {
+				tnext_state = tnow + 100 * MSEC;
+				break;
+			}
+		}
+
+		/*
+		 * Power button out signal implements in power_sequence.c,
+		 * just call the exit hard off start to run the state mechine.
+		 */
+		reset_diagnostics();
+		chipset_exit_hard_off();
+		pwrbtn_state = PWRBTN_STATE_IDLE;
+		break;
+	case PWRBTN_STATE_HELD:
+
+		if (power_button_is_pressed()) {
+			tnext_state = tnow + PWRBTN_DELAY_T2;
+			pwrbtn_state = PWRBTN_STATE_NEED_SHUTDOWN;
+		} else {
+			power_button_released(tnow);
+		}
+
+		break;
+	case PWRBTN_STATE_NEED_SHUTDOWN:
+
+		if (!chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
+			CPRINTS("PB held press 8s execute force shutdown");
+			chipset_force_shutdown(CHIPSET_SHUTDOWN_G3);
+		}
+
+		if (power_button_is_pressed()) {
+			tnext_state = tnow + PWRBTN_DELAY_T3;
+			pwrbtn_state = PWRBTN_STATE_NEED_RESET;
+		} else
+			power_button_released(tnow);
+
+		break;
+	case PWRBTN_STATE_NEED_RESET:
+		if (power_button_is_pressed())
+			system_reset(SYSTEM_RESET_HARD);
+		else
+			power_button_released(tnow);
+		break;
+	case PWRBTN_STATE_BOOT_KB_RESET:
+	case PWRBTN_STATE_WAS_OFF:
+	case PWRBTN_STATE_IDLE:
+	case PWRBTN_STATE_EAT_RELEASE:
+		/* Do nothing */
+		break;
+	}
+}
+
+void power_button_task(void *u)
+{
+	uint64_t t;
+	uint64_t tsleep;
+	enum power_button_state curr_state = PWRBTN_STATE_IDLE;
+
+	/*
+	 * Record the time when the task starts so that the state machine can
+	 * use this to identify any timeouts.
+	 */
+	tpb_task_start = get_time().val;
+
+	while (1) {
+		t = get_time().val;
+
+		/* Update state machine */
+		if (pwrbtn_state != curr_state) {
+			CPRINTS("PB task %d = %s", pwrbtn_state,
+				state_names[pwrbtn_state]);
+			curr_state = pwrbtn_state;
+		}
+
+		state_machine(t);
+
+		/* Sleep until our next timeout */
+		tsleep = -1;
+		if (tnext_state && tnext_state < tsleep)
+			tsleep = tnext_state;
+		t = get_time().val;
+		if (tsleep > t) {
+			uint16_t d = tsleep == -1 ? -1 : (uint16_t)(tsleep - t);
+			/*
+			 * (Yes, the conversion from uint64_t to unsigned could
+			 * theoretically overflow if we wanted to sleep for
+			 * more than 2^32 us, but our timeouts are small enough
+			 * that can't happen - and even if it did, we'd just go
+			 * back to sleep after deciding that we woke up too
+			 * early.)
+			 */
+			if (pwrbtn_state != curr_state) {
+				CPRINTS("PB task %d = %s, wait %d", pwrbtn_state,
+					state_names[pwrbtn_state], d);
+			}
+			task_wait_event(d);
+		}
+	}
+}
+
+/*****************************************************************************/
+/* Hooks */
+
+static void powerbtn_x86_init(void)
+{
+	set_initial_pwrbtn_state();
+}
+DECLARE_HOOK(HOOK_INIT, powerbtn_x86_init, HOOK_PRIO_DEFAULT + 1);
+
+void chipset_power_on(void)
+{
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
+	    pwrbtn_state != PWRBTN_STATE_INIT_ON) {
+		power_button_pch_pulse();
+	}
+}
+
+#ifdef CONFIG_LID_SWITCH
+/**
+ * Handle switch changes based on lid event.
+ */
+static void powerbtn_x86_lid_change(void)
+{
+	/* If chipset in suspend mode, pulse the power button on lid open to wake it. */
+	if (lid_is_open() && chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)
+	    && pwrbtn_state != PWRBTN_STATE_INIT_ON) {
+		chipset_power_on();
+	}
+}
+DECLARE_HOOK(HOOK_LID_CHANGE, powerbtn_x86_lid_change, HOOK_PRIO_DEFAULT);
+#endif
+
+/**
+ * Handle debounced power button changing state.
+ */
+static void powerbtn_x86_changed(void)
+{
+	if (pwrbtn_state == PWRBTN_STATE_BOOT_KB_RESET ||
+	    pwrbtn_state == PWRBTN_STATE_INIT_ON ||
+	    pwrbtn_state == PWRBTN_STATE_LID_OPEN ||
+	    pwrbtn_state == PWRBTN_STATE_WAS_OFF) {
+		/* Ignore all power button changes during an initial pulse */
+		CPRINTS("PB ignoring change");
+		return;
+	}
+
+	if (power_button_is_pressed()) {
+		/* Power button pressed */
+		power_button_pressed(get_time().val);
+	} else {
+		/* Power button released */
+		if (pwrbtn_state == PWRBTN_STATE_EAT_RELEASE) {
+			/*
+			 * Ignore the first power button release if we already
+			 * told the PCH the power button was released.
+			 */
+			CPRINTS("PB ignoring release");
+			pwrbtn_state = PWRBTN_STATE_IDLE;
+			return;
+		}
+
+		power_button_released(get_time().val);
+	}
+
+	/* Wake the power button task */
+	task_wake(TASK_ID_POWERBTN);
+}
+DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, powerbtn_x86_changed, HOOK_PRIO_DEFAULT);
+
+/**
+ * Handle configuring the power button behavior through a host command
+ */
+static enum ec_status hc_config_powerbtn_x86(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_config_power_button *p = args->params;
+
+	power_button_pulse_enabled =
+		!!(p->flags & EC_POWER_BUTTON_ENABLE_PULSE);
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_CONFIG_POWER_BUTTON, hc_config_powerbtn_x86,
+		     EC_VER_MASK(0));
+
+/*
+ * Currently, the only reason why we disable power button pulse is to allow
+ * detachable menu on AP to use power button for selection purpose without
+ * triggering SMI. Thus, re-enable the pulse any time there is a chipset
+ * state transition event.
+ */
+static void power_button_pulse_setting_reset(void)
+{
+	power_button_pulse_enabled = 1;
+}
+
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, power_button_pulse_setting_reset,
+	     HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, power_button_pulse_setting_reset,
+	     HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, power_button_pulse_setting_reset,
+	     HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, power_button_pulse_setting_reset,
+	     HOOK_PRIO_DEFAULT);
+
+#define POWER_BUTTON_SYSJUMP_TAG 0x5042 /* PB */
+#define POWER_BUTTON_HOOK_VERSION 1
+
+static void power_button_pulse_setting_restore_state(void)
+{
+	const int *state;
+	int version, size;
+
+	state = (const int *)system_get_jump_tag(POWER_BUTTON_SYSJUMP_TAG,
+						 &version, &size);
+
+	if (state && (version == POWER_BUTTON_HOOK_VERSION) &&
+	    (size == sizeof(power_button_pulse_enabled)))
+		power_button_pulse_enabled = *state;
+}
+DECLARE_HOOK(HOOK_INIT, power_button_pulse_setting_restore_state,
+	     HOOK_PRIO_POST_POWER_BUTTON);
+
+static void power_button_pulse_setting_preserve_state(void)
+{
+	system_add_jump_tag(POWER_BUTTON_SYSJUMP_TAG, POWER_BUTTON_HOOK_VERSION,
+			    sizeof(power_button_pulse_enabled),
+			    &power_button_pulse_enabled);
+}
+DECLARE_HOOK(HOOK_SYSJUMP, power_button_pulse_setting_preserve_state,
+	     HOOK_PRIO_DEFAULT);
diff --git a/zephyr/program/framework/lotus/src/power_sequence.c b/zephyr/program/framework/lotus/src/power_sequence.c
new file mode 100644
index 0000000000..9734ca0932
--- /dev/null
+++ b/zephyr/program/framework/lotus/src/power_sequence.c
@@ -0,0 +1,787 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "board_adc.h"
+#include "board_host_command.h"
+#include "board_charger.h"
+#include "chipset.h"
+#include "config.h"
+#include "console.h"
+#include "customized_shared_memory.h"
+#include "cypress_pd_common.h"
+#include "diagnostics.h"
+#include "espi.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "input_module.h"
+#include "lpc.h"
+#include "power.h"
+#include "power_sequence.h"
+#include "port80.h"
+#include "task.h"
+#include "timer.h"
+#include "util.h"
+#include "gpu.h"
+#include "gpu_configuration.h"
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ##args)
+
+#define IN_VR_PGOOD POWER_SIGNAL_MASK(X86_VR_PG)
+
+static int power_s5_up;		/* Chipset is sequencing up or down */
+static int ap_boot_delay = 9;	/* For global reset to wait SLP_S5 signal de-asserts */
+static int s5_exit_tries;	/* For global reset to wait SLP_S5 signal de-asserts */
+static int force_shoutdown_flags;
+static int stress_test_enable;
+static int d3cold_is_entry;	/* check the d3cold status */
+
+/* Power Signal Input List */
+const struct power_signal_info power_signal_list[] = {
+	[X86_3VALW_PG] = {
+		.gpio = GPIO_POWER_GOOD_3VALW,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "3VALW_PG_DEASSERTED",
+	},
+	[X86_SLP_S3_N] = {
+		.gpio = GPIO_PCH_SLP_S3_L,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "SLP_S3_DEASSERTED",
+	},
+	[X86_SLP_S5_N] = {
+		.gpio = GPIO_PCH_SLP_S5_L,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "SLP_S5_DEASSERTED",
+	},
+	[X86_VR_PG] = {
+		.gpio = GPIO_POWER_GOOD_VR,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "VR_PG_DEASSERTED",
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
+
+
+static void inputdeck_resume(void)
+{
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_sleep_l), 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, inputdeck_resume, HOOK_PRIO_DEFAULT);
+
+
+static void inputdeck_suspend(void)
+{
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_sleep_l), 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, inputdeck_suspend, HOOK_PRIO_DEFAULT);
+
+static void peripheral_power_startup(void)
+{
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_wlan_en), 1);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_h_prochot_l), 1);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_wl_rst_l), 1);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_cam_en), 1);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_edp_reset), 1);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_sm_panel_bken_ec), 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, peripheral_power_startup, HOOK_PRIO_DEFAULT);
+
+static void peripheral_power_resume(void)
+{
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_mute_l), 1);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_en_invpwr), 1);
+}
+
+static void peripheral_power_shutdown(void)
+{
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_wlan_en), 0);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_h_prochot_l), 0);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_wl_rst_l), 0);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_cam_en), 0);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_edp_reset), 0);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_sm_panel_bken_ec), 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, peripheral_power_shutdown, HOOK_PRIO_DEFAULT);
+
+static void peripheral_power_suspend(void)
+{
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_mute_l), 0);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_en_invpwr), 0);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ssd2_pwr_en), 0);
+	set_gpu_gpio(GPIO_FUNC_SSD1_POWER, 0);
+	set_gpu_gpio(GPIO_FUNC_SSD2_POWER, 0);
+}
+
+static int keep_pch_power(void)
+{
+	int wake_source = *host_get_memmap(EC_CUSTOMIZED_MEMMAP_WAKE_EVENT);
+
+	/* This feature only use on the ODM stress test tool */
+	if (wake_source & RTCWAKE)
+		return true;
+	else
+		return false;
+
+}
+
+/*
+ * Backup copies of SCI mask to preserve across S0ix suspend/resume
+ * cycle. If the host uses S0ix, BIOS is not involved during suspend and resume
+ * operations and hence SCI masks are programmed only once during boot-up.
+ *
+ * These backup variables are set whenever host expresses its interest to
+ * enter S0ix and then lpc_host_event_mask for SCI are cleared. When
+ * host resumes from S0ix, masks from backup variables are copied over to
+ * lpc_host_event_mask for SCI.
+ */
+static host_event_t backup_sci_mask;
+
+/*
+ * Clear host event masks for SCI when host is entering S0ix. This is
+ * done to prevent any SCI interrupts when the host is in suspend. Since
+ * BIOS is not involved in the suspend path, EC needs to take care of clearing
+ * these masks.
+ */
+static void lpc_s0ix_suspend_clear_masks(void)
+{
+	backup_sci_mask = lpc_get_host_event_mask(LPC_HOST_EVENT_SCI);
+
+	lpc_set_host_event_mask(LPC_HOST_EVENT_SCI, SCI_HOST_WAKE_EVENT_MASK);
+}
+
+/*
+ * Restore host event masks for SCI when host exits S0ix. This is done
+ * because BIOS is not involved in the resume path and so EC needs to restore
+ * the masks from backup variables.
+ */
+static void lpc_s0ix_resume_restore_masks(void)
+{
+	/*
+	 * No need to restore SCI masks if both backup_sci_mask are zero.
+	 * This indicates that there was a failure to enter S0ix
+	 * and hence SCI masks were never backed up.
+	 */
+	if (!backup_sci_mask)
+		return;
+
+	lpc_set_host_event_mask(LPC_HOST_EVENT_SCI, backup_sci_mask);
+
+	backup_sci_mask = 0;
+}
+
+static void clear_rtcwake(void)
+{
+	*host_get_memmap(EC_CUSTOMIZED_MEMMAP_WAKE_EVENT) &= ~BIT(0);
+}
+
+void power_state_clear(int state)
+{
+	*host_get_memmap(EC_CUSTOMIZED_MEMMAP_POWER_STATE) &= ~state;
+}
+
+void power_s5_up_control(int control)
+{
+	CPRINTS("%s power s5 up!", control ? "setup" : "clear");
+	power_s5_up = control;
+}
+
+void clear_power_flags(void)
+{
+	/**
+	 * When system reboot and go into setup menu, we need to set the power_s5_up flag
+	 * to wait SLP_S5 and SLP_S3 signal to boot into OS.
+	 */
+	power_s5_up_control(1);
+
+	input_modules_reset();
+
+	power_state_clear(EC_PS_ENTER_S4 | EC_PS_RESUME_S4 |
+		EC_PS_ENTER_S5 | EC_PS_RESUME_S5);
+
+	d3cold_is_entry = 0;
+}
+
+void chipset_g3_deferred(void)
+{
+	set_gpu_gpios_powerstate();
+}
+DECLARE_DEFERRED(chipset_g3_deferred);
+
+#ifdef CONFIG_PLATFORM_EC_POWERSEQ_S0IX
+/*
+ * Backup copies of SCI mask to preserve across S0ix suspend/resume
+ * cycle. If the host uses S0ix, BIOS is not involved during suspend and resume
+ * operations and hence SCI masks are programmed only once during boot-up.
+ *
+ * These backup variables are set whenever host expresses its interest to
+ * enter S0ix and then lpc_host_event_mask for SCI are cleared. When
+ * host resumes from S0ix, masks from backup variables are copied over to
+ * lpc_host_event_mask for SCI.
+ */
+static int enter_ms_flag;
+static int resume_ms_flag;
+static int system_in_s0ix;
+
+static int check_s0ix_statsus(void)
+{
+	int power_status;
+	int clear_flag;
+
+	/* check power state S0ix flags */
+	if (chipset_in_state(CHIPSET_STATE_ON) || chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
+		power_status = *host_get_memmap(EC_CUSTOMIZED_MEMMAP_POWER_STATE);
+
+
+		/**
+		 * Sometimes PCH will set the enter and resume flag continuously
+		 * so clear the EMI when we read the flag.
+		 */
+		if (power_status & EC_PS_ENTER_S0ix)
+			enter_ms_flag++;
+
+		if (power_status & EC_PS_RESUME_S0ix)
+			resume_ms_flag++;
+
+		clear_flag = power_status & (EC_PS_ENTER_S0ix | EC_PS_RESUME_S0ix);
+
+		power_state_clear(clear_flag);
+
+		if (resume_ms_flag)
+			return CS_EXIT_S0ix;
+
+		if (enter_ms_flag)
+			return CS_ENTER_S0ix;
+	}
+	return 0;
+}
+
+void s0ix_status_handle(void)
+{
+	int s0ix_state_change;
+
+	s0ix_state_change = check_s0ix_statsus();
+
+	if ((s0ix_state_change == CS_ENTER_S0ix) && chipset_in_state(CHIPSET_STATE_ON))
+		task_wake(TASK_ID_CHIPSET);
+	else if ((s0ix_state_change == CS_EXIT_S0ix) && chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
+		task_wake(TASK_ID_CHIPSET);
+}
+DECLARE_HOOK(HOOK_TICK, s0ix_status_handle, HOOK_PRIO_DEFAULT);
+
+int check_s0ix_status(void)
+{
+	return system_in_s0ix;
+}
+
+#endif
+
+void chipset_reset(enum chipset_shutdown_reason reason)
+{
+	/* unused function, EC doesn't control GPIO_SYS_RESET_L */
+}
+
+static void chipset_force_g3(void)
+{
+	input_modules_powerdown();
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_sleep_l), 0);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_hub_b_pwr_en), 0);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_sys_pwrgd_ec), 0);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_vr_on), 0);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_susp_l), 0);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_0p75vs_pwr_en), 0);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_syson), 0);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_fp_en), 0);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_soc_rsmrst_l), 0);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_pbtn_out), 0);
+	control_5valw_power(POWER_REQ_POWER_ON, 0);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_apu_aud_pwr_en), 0);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_pch_pwr_en), 0);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_edp_reset), 0);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_sm_panel_bken_ec), 0);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_hub_re_en), 0);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_0p75_1p8valw_pwren), 0);
+}
+
+void chipset_force_shutdown(enum chipset_shutdown_reason reason)
+{
+	if (!chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
+		CPRINTS("%s(%d)", __func__, reason);
+		report_ap_reset(reason);
+		force_shoutdown_flags = 1;
+		task_wake(TASK_ID_CHIPSET);
+		clear_rtcwake();
+	}
+}
+
+enum power_state power_chipset_init(void)
+{
+	/* If we don't need to image jump to RW, always start at G3 state */
+	chipset_force_g3();
+	return POWER_G3;
+}
+
+/**
+ * AMD recommended EC needs to check whether the system hangs or not,
+ * If EC detect the system hangs, force reset the system then reboot again.
+ */
+#define VW_NO_READY 0
+void system_hang_detect(void)
+{
+	int virtual_wire_ready = get_espi_virtual_wire_channel_status();
+
+	if (virtual_wire_ready == VW_NO_READY) {
+		board_reboot_ap_on_g3();
+		chipset_force_shutdown(CHIPSET_RESET_HANG_REBOOT);
+	}
+}
+DECLARE_DEFERRED(system_hang_detect);
+
+static int chipset_prepare_S3(uint8_t enable)
+{
+	if (!enable) {
+		k_msleep(5);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_sys_pwrgd_ec), 0);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_vr_on), 0);
+		k_msleep(85);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_susp_l), 0);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_0p75vs_pwr_en), 0);
+		peripheral_power_suspend();
+		/* only exit epr when battery connect */
+		if (battery_get_disconnect_state() == BATTERY_NOT_DISCONNECTED)
+			exit_epr_mode();
+	} else {
+		k_msleep(10);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_susp_l), 1);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_0p75vs_pwr_en), 1);
+		k_msleep(20);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_vr_on), 1);
+
+		/* wait VR power good. if something wrong, turn off power and force to g3 */
+		if (power_wait_signals(IN_VR_PGOOD))
+			force_shoutdown_flags = 1;
+
+		k_msleep(10);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_sys_pwrgd_ec), 1);
+		peripheral_power_resume();
+	}
+
+	return true;
+}
+
+enum power_state power_handle_state(enum power_state state)
+{
+	switch (state) {
+	case POWER_G3:
+		break;
+
+	case POWER_G3S5:
+
+		control_5valw_power(POWER_REQ_POWER_ON, 1);
+
+		if (power_wait_signals(X86_3VALW_PG)) {
+			/* something wrong, turn off power and force to g3 */
+			chipset_force_g3();
+			return POWER_G3;
+		}
+		k_msleep(20);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_0p75_1p8valw_pwren), 1);
+		k_msleep(10);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_apu_aud_pwr_en), 1);
+		k_msleep(10);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_pch_pwr_en), 1);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_hub_re_en), 1);
+		k_msleep(10);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_pbtn_out), 1);
+		k_msleep(10);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_soc_rsmrst_l), 1);
+
+		/* Customizes power button out signal without PB task for powering on. */
+		k_msleep(90);
+		CPRINTS("PCH PBTN LOW");
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_pbtn_out), 0);
+		k_msleep(20);
+		CPRINTS("PCH PBTN HIGH");
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_pbtn_out), 1);
+		input_modules_reset();
+
+		/* Exit SOC G3 */
+		CPRINTS("Exit SOC G3");
+		power_s5_up_control(1);
+		return POWER_S5;
+
+	case POWER_S5:
+
+		if (force_shoutdown_flags) {
+			force_shoutdown_flags = 0;
+			return POWER_S5G3;
+		}
+
+		if (power_s5_up || stress_test_enable) {
+			while (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_slp_s5_l)) == 0) {
+				if (task_wait_event(SECOND) == TASK_EVENT_TIMER) {
+					if (++s5_exit_tries > ap_boot_delay) {
+						CPRINTS("timeout waiting for S5 exit");
+						/*
+						 * TODO: RTC reset function
+						 */
+						ap_boot_delay = 9;
+						s5_exit_tries = 0;
+						stress_test_enable = 0;
+						clear_rtcwake();
+						set_diagnostic(DIAGNOSTICS_SLP_S4, 1);
+						/* SLP_S5 asserted, power down to G3S5 state */
+						return POWER_S5G3;
+					}
+				}
+			}
+			/* Power up to next state */
+			gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_usb30_hub_en), 1);
+			s5_exit_tries = 0;
+			return POWER_S5S3;
+		}
+
+		if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_slp_s5_l)) == 1) {
+			gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_usb30_hub_en), 1);
+			s5_exit_tries = 0;
+			/* Power up to next state */
+			return POWER_S5S3;
+		}
+
+		break;
+
+	case POWER_S5S3:
+
+		/* Call hooks now that rails are up */
+		hook_call_deferred(&system_hang_detect_data, 3 * SECOND);
+
+		/* enable the psys to resume from low power mode */
+		board_charger_lpm_control(1);
+		hook_notify(HOOK_CHIPSET_STARTUP);
+		return POWER_S3;
+
+	case POWER_S3:
+		if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_slp_s3_l)) == 1 &&
+			!force_shoutdown_flags) {
+
+			/* still in s0ix state */
+			if (system_in_s0ix)
+				return POWER_S3S0ix;
+
+			/* enable the ssd2 power when the system power on from S5 */
+			gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ssd2_pwr_en), 1);
+			set_gpu_gpio(GPIO_FUNC_SSD1_POWER, 1);
+			set_gpu_gpio(GPIO_FUNC_SSD2_POWER, 1);
+
+			/* Power up to next state */
+			k_msleep(10);
+			return POWER_S3S0;
+		} else if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_slp_s5_l)) == 0
+			|| force_shoutdown_flags) {
+
+			if (system_in_s0ix) {
+				resume_ms_flag = 0;
+				enter_ms_flag = 0;
+				system_in_s0ix = 0;
+				lpc_s0ix_resume_restore_masks();
+				/* Call hooks now that rails are up */
+				hook_notify(HOOK_CHIPSET_RESUME);
+				peripheral_power_resume();
+
+				/* if system drop power return to S0 run sequence shutdown */
+				return POWER_S0;
+			}
+
+			gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_usb30_hub_en), 0);
+
+			/* disable the ssd2 power when the system shutdown to S5 */
+			gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ssd2_pwr_en), 0);
+			set_gpu_gpio(GPIO_FUNC_SSD1_POWER, 0);
+			set_gpu_gpio(GPIO_FUNC_SSD2_POWER, 0);
+			k_msleep(55);
+			/* Power down to next state */
+			return POWER_S3S5;
+		}
+		break;
+
+	case POWER_S3S0:
+
+		/*
+		 * TODO: distinguish S5 -> S0 and S3 -> S0, the sequences are different
+		 * S5 -> S0: wait 10 - 15 ms then assert the SYSON
+		 * S3 -> S0: wait 10 - 15 ms then assert the SUSP_L
+		 * currently, I will follow the power on sequence to make sure DUT can
+		 * power up from S5.
+		 */
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_syson), 1);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_fp_en), 1);
+		set_gpu_gpio(GPIO_FUNC_GPU_PWR, 1);
+
+		k_msleep(20);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_susp_l), 1);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_0p75vs_pwr_en), 1);
+		k_msleep(20);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_vr_on), 1);
+
+		/* wait VR power good */
+		if (power_wait_signals(IN_VR_PGOOD)) {
+			/* something wrong, turn off power and force to g3 */
+			set_diagnostic(DIAGNOSTICS_VCCIN_AUX_VR, 1);
+			gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_vr_on), 0);
+			gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_susp_l), 0);
+			gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_0p75vs_pwr_en), 0);
+			force_shoutdown_flags = 1;
+			return POWER_S3;
+		}
+
+		k_msleep(10);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_sys_pwrgd_ec), 1);
+
+		lpc_s0ix_resume_restore_masks();
+		/* Call hooks now that rails are up */
+		hook_notify(HOOK_CHIPSET_RESUME);
+		peripheral_power_resume();
+
+		/*
+		 * Disable idle task deep sleep. This means that the low
+		 * power idle task will not go into deep sleep while in S0.
+		 */
+		disable_sleep(SLEEP_MASK_AP_RUN);
+
+		/* set the PD chip system power state "S0" */
+		cypd_set_power_active();
+
+		clear_rtcwake();
+
+		return POWER_S0;
+
+	case POWER_S0:
+
+		if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_slp_s3_l)) == 0 ||
+			force_shoutdown_flags) {
+			/* Power down to next state */
+			k_msleep(5);
+			return POWER_S0S3;
+		}
+
+#ifdef CONFIG_PLATFORM_EC_POWERSEQ_S0IX
+		if (check_s0ix_statsus() == CS_ENTER_S0ix)
+			return POWER_S0S0ix;
+#endif
+		break;
+
+#ifdef CONFIG_PLATFORM_EC_POWERSEQ_S0IX
+	case POWER_S0ix:
+		if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_slp_s3_l)) == 0 ||
+			force_shoutdown_flags) {
+			/*
+			 * If power signal lose, we need to resume to S0 and
+			 * clear the all s0ix flags
+			 */
+			if (resume_ms_flag > 0) {
+				resume_ms_flag = 0;
+				enter_ms_flag = 0;
+				system_in_s0ix = 0;
+				return POWER_S0ixS0;
+			}
+
+			return POWER_S0ixS3;
+		}
+
+		if (check_s0ix_statsus() == CS_EXIT_S0ix)
+			return POWER_S0ixS0;
+
+		break;
+
+	case POWER_S0ixS3:
+		/* follow power sequence Disable S3 power */
+		chipset_prepare_S3(0);
+		set_gpu_gpios_powerstate();
+		return POWER_S3;
+
+	case POWER_S3S0ix:
+		/* Enable power for CPU check system */
+		chipset_prepare_S3(1);
+		set_gpu_gpios_powerstate();
+		return POWER_S0ix;
+
+	case POWER_S0ixS0:
+		resume_ms_flag = 0;
+		system_in_s0ix = 0;
+
+		/* We should enter EPR mode when the system actually resume to S0 state */
+		enter_epr_mode();
+
+		lpc_s0ix_resume_restore_masks();
+		hook_notify(HOOK_CHIPSET_RESUME);
+
+		/*
+		 * Disable idle task deep sleep. This means that the low
+		 * power idle task will not go into deep sleep while in S0.
+		 */
+		disable_sleep(SLEEP_MASK_AP_RUN);
+
+		return POWER_S0;
+
+		break;
+
+	case POWER_S0S0ix:
+		enter_ms_flag = 0;
+		system_in_s0ix = 1;
+		lpc_s0ix_suspend_clear_masks();
+		hook_notify(HOOK_CHIPSET_SUSPEND);
+
+		/*
+		 * Enable idle task deep sleep. Allow the low power idle task
+		 * to go into deep sleep in S3 or lower.
+		 */
+		enable_sleep(SLEEP_MASK_AP_RUN);
+
+		return POWER_S0ix;
+
+		break;
+#endif
+
+	case POWER_S0S3:
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_sys_pwrgd_ec), 0);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_vr_on), 0);
+		k_msleep(85);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_susp_l), 0);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_0p75vs_pwr_en), 0);
+
+		lpc_s0ix_suspend_clear_masks();
+		/* Call hooks before we remove power rails */
+		hook_notify(HOOK_CHIPSET_SUSPEND);
+		peripheral_power_suspend();
+
+		/*
+		 * Enable idle task deep sleep. Allow the low power idle task
+		 * to go into deep sleep in S3 or lower.
+		 */
+		enable_sleep(SLEEP_MASK_AP_RUN);
+
+		/* set the PD chip system power state "S3" */
+		cypd_set_power_active();
+		return POWER_S3;
+
+	case POWER_S3S5:
+		/* Call hooks before we remove power rails */
+		power_s5_up_control(0);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_syson), 0);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_fp_en), 0);
+		/*set_gpu_gpio(GPIO_FUNC_GPU_PWR, 0);*/
+		hook_notify(HOOK_CHIPSET_SHUTDOWN);
+
+		input_modules_powerdown();
+
+		/* set the PD chip system power state "S5" */
+		cypd_set_power_active();
+		return POWER_S5;
+
+	case POWER_S5G3:
+
+		/*
+		 * We need to keep pch power to wait SLP_S5 signal for the below cases:
+		 *
+		 * 1. Customer testing tool
+		 * 2. There is a type-c USB input deck connect on the unit
+		 */
+		if (keep_pch_power())
+			return POWER_S5;
+
+		hook_call_deferred(&chipset_g3_deferred_data, 5 * MSEC);
+
+		/* Don't need to keep pch power, turn off the pch power and power down to G3*/
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_soc_rsmrst_l), 0);
+		k_msleep(5);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_pbtn_out), 0);
+		control_5valw_power(POWER_REQ_POWER_ON, 0);
+		k_msleep(5);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_apu_aud_pwr_en), 0);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_pch_pwr_en), 0);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_hub_re_en), 0);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_0p75_1p8valw_pwren), 0);
+		input_modules_powerdown();
+
+		/* clear suspend flag when system shutdown */
+		power_state_clear(EC_PS_ENTER_S0ix |
+			EC_PS_RESUME_S0ix | EC_PS_RESUME_S3 | EC_PS_ENTER_S3);
+
+		cypd_set_power_active();
+
+		/* disable psys to let charger enter low power mode*/
+		board_charger_lpm_control(0);
+		return POWER_G3;
+	default:
+		break;
+	}
+	return state;
+}
+
+void system_check_ssd_status(void)
+{
+	int ssd_power_states = *host_get_memmap(EC_CUSTOMIZED_MEMMAP_WAKE_EVENT);
+
+	if (ssd_power_states & JSSD2_POWER_ON) {
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ssd2_pwr_en), 1);
+		*host_get_memmap(EC_CUSTOMIZED_MEMMAP_WAKE_EVENT) &= ~JSSD2_POWER_ON;
+	}
+
+	if (ssd_power_states & EXT_SSD1_POWER_ON) {
+		set_gpu_gpio(GPIO_FUNC_SSD1_POWER, 1);
+		*host_get_memmap(EC_CUSTOMIZED_MEMMAP_WAKE_EVENT) &= ~EXT_SSD1_POWER_ON;
+	}
+
+	if (ssd_power_states & EXT_SSD2_POWER_ON) {
+		set_gpu_gpio(GPIO_FUNC_SSD2_POWER, 1);
+		*host_get_memmap(EC_CUSTOMIZED_MEMMAP_WAKE_EVENT) &= ~EXT_SSD2_POWER_ON;
+	}
+}
+DECLARE_HOOK(HOOK_TICK, system_check_ssd_status, HOOK_PRIO_DEFAULT);
+
+void chipset_throttle_cpu(int throttle)
+{
+	if (chipset_in_state(CHIPSET_STATE_ON))
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_h_prochot_l), !throttle);
+}
+
+static void usb30_hub_reset(void)
+{
+	/**
+	 * This hook is called when the system warm boots or cold boots,
+	 * adding the delay time to filter the cold boot condition.
+	 */
+	if (chipset_in_state(CHIPSET_STATE_ON)) {
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ssd2_pwr_en), 1);
+		set_gpu_gpio(GPIO_FUNC_SSD1_POWER, 1);
+		set_gpu_gpio(GPIO_FUNC_SSD2_POWER, 1);
+		usleep(200 * MSEC);
+		/* do not reset the hub when the system shutdown */
+		if (!chipset_in_state(CHIPSET_STATE_ON))
+			return;
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_usb30_hub_en), 0);
+		usleep(10 * MSEC);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_usb30_hub_en), 1);
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESET, usb30_hub_reset, HOOK_PRIO_DEFAULT);
+
+static enum ec_status set_ap_reboot_delay(struct host_cmd_handler_args *args)
+{
+	const struct ec_response_ap_reboot_delay *p = args->params;
+
+	stress_test_enable = 1;
+	/* don't let AP send zero it will stuck power sequence at S5 */
+	if (p->delay < 181 && p->delay)
+		ap_boot_delay = p->delay;
+	else
+		return EC_ERROR_INVAL;
+
+
+	return EC_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_SET_AP_REBOOT_DELAY, set_ap_reboot_delay,
+			EC_VER_MASK(0));
diff --git a/zephyr/program/framework/lotus/src/project_diagnostics.c b/zephyr/program/framework/lotus/src/project_diagnostics.c
new file mode 100644
index 0000000000..4bfb5c7fca
--- /dev/null
+++ b/zephyr/program/framework/lotus/src/project_diagnostics.c
@@ -0,0 +1,93 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "board_host_command.h"
+#include "console.h"
+#include "diagnostics.h"
+#include "dptf.h"
+#include "fan.h"
+#include "gpu.h"
+#include "hooks.h"
+#include "input_module.h"
+#include "port80.h"
+#include "timer.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+
+static void check_fan_ready_deferred(void);
+DECLARE_DEFERRED(check_fan_ready_deferred);
+
+static void check_fan_ready_deferred(void)
+{
+	static bool flag_right_fan_ready;
+	static bool flag_left_fan_ready;
+	static int count;
+
+	if ((fan_get_rpm_actual(0) > 100) && !flag_right_fan_ready) {
+		flag_right_fan_ready = true;
+		set_diagnostic(DIAGNOSTICS_NO_RIGHT_FAN, false);
+	}
+	if ((fan_get_rpm_actual(1) > 100) && !flag_left_fan_ready) {
+		flag_left_fan_ready = true;
+		set_diagnostic(DIAGNOSTICS_NO_LEFT_FAN, false);
+	}
+
+	if (flag_right_fan_ready && flag_left_fan_ready) {
+		/* Exit the duty mode and let thermal to control the fan */
+		dptf_set_fan_duty_target(-1);
+		count = 0;
+		flag_right_fan_ready = 0;
+		flag_left_fan_ready = 0;
+		set_device_complete(true);
+	} else if (count < 15) {
+		count++;
+		hook_call_deferred(&check_fan_ready_deferred_data, 500 * MSEC);
+	} else {
+		dptf_set_fan_duty_target(-1);
+		count = 0;
+		flag_right_fan_ready = 0;
+		flag_left_fan_ready = 0;
+		set_device_complete(true);
+	}
+}
+
+void start_fan_deferred(void)
+{
+	/* force turn on the fan for diagnostic */
+	dptf_set_fan_duty_target(20);
+}
+DECLARE_DEFERRED(start_fan_deferred);
+
+void check_device_deferred(void)
+{
+	/* Clear the DIAGNOSTICS_HW_NO_BATTERY flag if battery is present */
+	if (battery_is_present() == BP_YES || get_standalone_mode())
+		set_diagnostic(DIAGNOSTICS_HW_NO_BATTERY, false);
+
+	if (gpu_module_fault())
+		set_diagnostic(DIAGNOSTICS_GPU_MODULE_FAULT, true);
+
+	if (get_deck_state() != DECK_ON && !get_standalone_mode())
+		set_diagnostic(DIAGNOSTICS_INPUT_MODULE_FAULT, true);
+
+	if (amd_ddr_initialized_check())
+		set_bios_diagnostic(CODE_DDR_FAIL);
+
+	if (!get_standalone_mode())
+		hook_call_deferred(&check_fan_ready_deferred_data, 0);
+	else {
+		set_device_complete(true);
+		dptf_set_fan_duty_target(-1);
+	}
+}
+DECLARE_DEFERRED(check_device_deferred);
+
+void project_diagnostics(void)
+{
+	hook_call_deferred(&start_fan_deferred_data, 500 * MSEC);
+	hook_call_deferred(&check_device_deferred_data, 2000 * MSEC);
+}
diff --git a/zephyr/program/framework/lotus/src/stt.c b/zephyr/program/framework/lotus/src/stt.c
new file mode 100644
index 0000000000..8022f915d7
--- /dev/null
+++ b/zephyr/program/framework/lotus/src/stt.c
@@ -0,0 +1,41 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Support code for STT temperature reporting */
+
+#include "amd_stt.h"
+#include "chipset.h"
+#include "temp_sensor/f75303.h"
+#include "temp_sensor/pct2075.h"
+#include "temp_sensor/temp_sensor.h"
+
+int board_get_soc_temp_mk(int *temp_mk)
+{
+	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	return f75303_get_val_mk(F75303_SENSOR_ID(DT_NODELABEL(apu_f75303)),
+				 temp_mk);
+}
+
+int board_get_ambient_temp_mk(int *temp_mk)
+{
+	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	return f75303_get_val_mk(
+		F75303_SENSOR_ID(DT_NODELABEL(ambient_f75303)), temp_mk);
+}
+
+#ifdef CONFIG_PLATFORM_EC_GPU
+int board_get_gpu_temp_mk(int *temp_mk)
+{
+	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	return f75303_get_val_mk(
+		F75303_SENSOR_ID(DT_NODELABEL(gpu_vr_f75303)), temp_mk);
+}
+#endif
diff --git a/zephyr/program/framework/lotus/src/thermal.c b/zephyr/program/framework/lotus/src/thermal.c
new file mode 100644
index 0000000000..73ef4131c1
--- /dev/null
+++ b/zephyr/program/framework/lotus/src/thermal.c
@@ -0,0 +1,307 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "amd_stt.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "fan.h"
+#include "gpu.h"
+#include "hooks.h"
+#include "system.h"
+#include "thermal.h"
+#include "temp_sensor/temp_sensor.h"
+#include "util.h"
+#include "gpu_configuration.h"
+#include "temperature_filter.h"
+
+#include "temp_sensor/f75303.h"
+
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_THERMAL, format, ##args)
+
+uint16_t board_fan_max[2];
+uint16_t board_fan_min[2];
+
+#define FAN_STOP_DELAY_S (5 * SECOND)
+
+
+/*coeff in the form b0, b1, b2, A0, a1, a2 note: drop a0*/
+/* 1590,-3130,1590,-31527,15193,14 */
+/* */
+const int32_t gpu_coeff[6] = {
+	59, 119,  59, 16384, -29863, 13716
+};
+const int32_t apu_coeff[6] = {
+	34, 68, 34, 16384, -30587, 14340
+};
+struct biquad gpu_filtered = {
+	.coeff = gpu_coeff,
+};
+struct biquad apu_filtered = {
+	.coeff = apu_coeff,
+};
+
+static void board_temperature_reset(void)
+{
+	thermal_filter_reset(&gpu_filtered);
+	thermal_filter_reset(&apu_filtered);
+}
+
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_temperature_reset, HOOK_PRIO_DEFAULT);
+
+void fan_configure_gpu(struct gpu_cfg_fan *fan) {
+	if (fan == NULL) {
+		board_fan_max[0] = 0;
+		board_fan_max[1] = 0;
+		board_fan_min[0] = 0;
+		board_fan_min[1] = 0;
+	} else {
+		if (fan->idx < 2) {
+			board_fan_max[fan->idx] = fan->max_rpm;
+			board_fan_min[fan->idx] = fan->min_rpm;
+		}
+	}
+}
+
+void fan_set_rpm_target(int ch, int rpm)
+{
+	int board_rpm_max = fans[ch].rpm->rpm_max;
+	int board_rpm_min = fans[ch].rpm->rpm_min;
+
+	if (rpm == 0) {
+		/* If rpm = 0, wait 10s for make sure temp is cold-down */
+		fan_set_duty(ch, 0);
+	} else {
+		/* This is the counterpart of disabling PWM above. */
+		if (!fan_get_enabled(ch)) {
+			fan_set_enabled(ch, 1);
+		}
+
+		/* Switch the fan configuration when gpu is present else use default */
+		if (board_fan_max[ch]) {
+			board_rpm_max = board_fan_max[ch];
+		}
+		if (board_fan_min[ch]) {
+			board_rpm_min = board_fan_min[ch];
+		}
+		if (rpm > board_rpm_max) {
+			rpm = board_rpm_max;
+		} else if (rpm < board_rpm_min) {
+			rpm = board_rpm_min;
+		}
+	}
+
+	/* Set target rpm */
+	fan_data[ch].rpm_target = rpm;
+}
+
+int fan_percent_to_rpm(int fan_index, int temp_ratio)
+{
+	int rpm;
+	int max = fans[fan_index].rpm->rpm_max;
+	int min = fans[fan_index].rpm->rpm_min;
+
+	if (temp_ratio <= 0) {
+		rpm = 0;
+	} else {
+		/* Switch the fan configuration when gpu is present */
+		if (board_fan_max[fan_index]) {
+			max = board_fan_max[fan_index];
+		}
+		if (board_fan_min[fan_index]) {
+			min = board_fan_min[fan_index];
+		}
+		rpm = ((temp_ratio - 1) * max + (100 - temp_ratio) * min) / 99;
+	}
+
+	return rpm;
+}
+
+bool log_thermal;
+#define TEMP_APU TEMP_SENSOR_ID(DT_NODELABEL(temp_sensor_apu))
+#define TEMP_GPU TEMP_SENSOR_ID(DT_NODELABEL(temp_sensor_gpu))
+#define TEMP_GPU_DIE TEMP_SENSOR_ID(DT_NODELABEL(temp_sensor_gpu_die))
+#define TEMP_APU_DIE TEMP_SENSOR_ID(DT_NODELABEL(temp_sensor_apu_die))
+void board_override_fan_control(int fan, int *temp)
+{
+	int actual_rpm, new_rpm;
+	int apu_temp_mk = 0;
+	int gpu_temp_mk = 0;
+
+#ifdef CONFIG_GPU
+	int gpu_pct = 0;
+	int gpu_selected_pct = 0;
+	int gpu_filtered_temp = 0;
+	int gpu_filtered_pct = 0;
+
+#endif
+	int apu_pct = 0;
+	int apu_selected_pct = 0;
+	int pct = 0;
+	int current_max_temp_idx = TEMP_APU;
+	int apu_filtered_temp = 0;
+	int apu_filtered_pct = 0;
+	int temps_mk[5];
+
+	static timestamp_t deadline;
+	timestamp_t now = get_time();
+
+	if (!is_thermal_control_enabled(fan))
+		return;
+
+	/*
+	 * In common/fan.c pwm_fan_stop() will turn off fan
+	 * when chipset suspend or shutdown.
+	 */
+	if (chipset_in_state(CHIPSET_STATE_ON)) {
+
+#ifdef CONFIG_GPU
+
+		board_get_gpu_temp_mk(&gpu_temp_mk);
+		if (thermal_params[TEMP_GPU].temp_fan_off &&
+			thermal_params[TEMP_GPU].temp_fan_max) {
+			gpu_pct = thermal_fan_percent(thermal_params[TEMP_GPU].temp_fan_off * 1000,
+						thermal_params[TEMP_GPU].temp_fan_max * 1000,
+						gpu_temp_mk);
+		}
+
+		board_get_soc_temp_mk(&apu_temp_mk);
+		if (thermal_params[TEMP_APU].temp_fan_off &&
+			thermal_params[TEMP_APU].temp_fan_max) {
+			apu_pct = thermal_fan_percent(thermal_params[TEMP_APU].temp_fan_off * 1000,
+						thermal_params[TEMP_APU].temp_fan_max * 1000,
+						apu_temp_mk);
+		}
+
+		if (fan == 0) {
+			thermal_filter_update(&gpu_filtered, temp[TEMP_GPU_DIE]);
+			thermal_filter_update(&apu_filtered, temp[TEMP_APU_DIE]);
+		}
+
+		apu_filtered_temp = thermal_filter_get(&apu_filtered);
+		if (thermal_params[TEMP_APU_DIE].temp_fan_off &&
+			thermal_params[TEMP_APU_DIE].temp_fan_max) {
+			apu_filtered_pct = thermal_fan_percent(thermal_params[TEMP_APU_DIE].temp_fan_off*1000,
+						thermal_params[TEMP_APU_DIE].temp_fan_max*1000,
+						C_TO_K(apu_filtered_temp)*1000);
+		}
+
+		gpu_filtered_temp = thermal_filter_get(&gpu_filtered);
+		if (thermal_params[TEMP_GPU_DIE].temp_fan_off &&
+			thermal_params[TEMP_GPU_DIE].temp_fan_max) {
+			gpu_filtered_pct = thermal_fan_percent(thermal_params[TEMP_GPU_DIE].temp_fan_off*1000,
+						thermal_params[TEMP_GPU_DIE].temp_fan_max*1000,
+						C_TO_K(gpu_filtered_temp)*1000);
+		}
+
+		gpu_selected_pct = gpu_filtered_pct;
+		/* Remove this for now, because during a transition from
+		 * high to mid loading on the GPU, we will oscillate between
+		 * two fan speeds during the cooldown period
+		 */
+
+		/*if (gpu_temp_mk > C_TO_K(gpu_filtered_temp)*1000 + 5000) {*/
+			/*GPU Cooldown, there is a lot of thermal restance between VR
+			 *and GPU die/heatpipe. So run the fan at a low value to keep
+			 *cooling the gpu after a workload has finished.
+			 *this reduces the long fan rampdown time when GPU stops a workload.
+			 *where the fans are running at a high speed.
+			 */
+		/*	gpu_selected_pct = MIN(15, gpu_pct);*/
+		/*}*/
+
+		apu_selected_pct = MAX(apu_pct, apu_filtered_pct);
+
+		if (apu_selected_pct > gpu_selected_pct || !gpu_power_enable())
+			pct = apu_selected_pct;
+		else {
+			current_max_temp_idx = TEMP_GPU;
+			pct = gpu_selected_pct;
+		}
+#else
+		board_get_soc_temp_mk(&temp_mk);
+
+		if (thermal_params[TEMP_APU].temp_fan_off &&
+			thermal_params[TEMP_APU].temp_fan_max) {
+			pct = thermal_fan_percent(thermal_params[TEMP_APU].temp_fan_off * 1000,
+						thermal_params[TEMP_APU].temp_fan_max * 1000,
+						temp_mk);
+		}
+#endif
+
+		new_rpm = fan_percent_to_rpm(fan, pct);
+		actual_rpm = fan_get_rpm_actual(FAN_CH(fan));
+
+		/*
+		 * If we want to turn and the fans are currently significantly below
+		 * the minimum turning speed, we should turn at least as fast as the
+		 * necessary start speed instead.
+		 */
+		if (new_rpm && actual_rpm < fans[fan].rpm->rpm_min * 9 / 10 &&
+			new_rpm < fans[fan].rpm->rpm_start)
+			new_rpm = fans[fan].rpm->rpm_start;
+
+		if (!new_rpm) {
+			/* add temperature histeresis so the fan does not turn off
+			 * unless the system has cooled 0.5C below the fan turn on temperature
+			 */
+			if (thermal_params[TEMP_APU].temp_fan_off &&
+				apu_temp_mk > (thermal_params[TEMP_APU].temp_fan_off
+					* 1000 - 500)) {
+				deadline.val = get_time().val + FAN_STOP_DELAY_S;
+			}
+			if (!timestamp_expired(deadline, &now))
+				return;
+		} else {
+			deadline.val = get_time().val + FAN_STOP_DELAY_S;
+		}
+
+		if (log_thermal && fan == 0) {
+			f75303_get_val_mk(
+				F75303_SENSOR_ID(DT_NODELABEL(gpu_vr_f75303)),
+				&temps_mk[0]);
+			f75303_get_val_mk(
+				F75303_SENSOR_ID(DT_NODELABEL(gpu_vram_f75303)),
+				&temps_mk[1]);
+			f75303_get_val_mk(
+				F75303_SENSOR_ID(DT_NODELABEL(apu_f75303)),
+				&temps_mk[2]);
+			CPRINTS("\tThrm\t%d\t%d\t%d\t\t%d\t%d\t\t%d\t%d\t\t%d\t%d\t%d\t%d\t%d\t%d\t%d",
+				temps_mk[0], temps_mk[1], temps_mk[2],
+				temp[TEMP_GPU_DIE], temp[TEMP_APU_DIE],
+				thermal_filter_get(&gpu_filtered),
+				thermal_filter_get(&apu_filtered),
+				pct, gpu_pct, gpu_filtered_pct, apu_pct, apu_filtered_pct,
+				new_rpm, actual_rpm);
+		}
+		fan_set_rpm_mode(fan, 1);
+		fan_set_rpm_target(FAN_CH(fan), new_rpm);
+	} else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
+		/* Stop fan when enter S0ix */
+		fan_set_rpm_mode(fan, 1);
+		fan_set_rpm_target(fan, 0);
+	}
+}
+
+
+
+/* EC console command */
+static int thermallog_cmd(int argc, const char **argv)
+{
+	if (argc >= 2) {
+		if (!strncmp(argv[1], "en", 2)) {
+			log_thermal = true;
+			CPRINTS("\tThrm\tG_VR\tG_RM\tAPU\t\tG_D\tA_D\t\tG_f\tA_f\t\tPCT\tGpct\tGfilt\tApct\tAfilt\tRPM\tFAN");
+		} else if (!strncmp(argv[1], "dis", 3)) {
+			log_thermal = false;
+		} else {
+			return EC_ERROR_PARAM1;
+		}
+	}
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(thermallog, thermallog_cmd, "[en/dis]",
+			"Enable or disable thermal logging");
diff --git a/zephyr/program/framework/program.conf b/zephyr/program/framework/program.conf
new file mode 100644
index 0000000000..6079b9b263
--- /dev/null
+++ b/zephyr/program/framework/program.conf
@@ -0,0 +1,91 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_PLATFORM_EC=y
+CONFIG_CROS_EC=y
+CONFIG_SHIMMED_TASKS=y
+CONFIG_SYSCON=y
+CONFIG_ADC=y
+CONFIG_PWM=y
+CONFIG_PLATFORM_EC_CUSTOMIZED_DESIGN=y
+CONFIG_PLATFORM_EC_HOST_EVENT64=y
+CONFIG_PLATFORM_EC_NPCX_FLASH_ERASE_SIZE=0x1000
+CONFIG_PLATFORM_EC_SWITCH=y
+CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y
+CONFIG_PLATFORM_EC_WP_DISABLE=y
+CONFIG_PLATFORM_EC_UNIMPLEMENTED_GPIO=y
+CONFIG_PLATFORM_EC_I2C_DEBUG=y
+CONFIG_CROS_EC_RW_SIZE=0x3F000
+
+# Port80
+CONFIG_PLATFORM_EC_PORT80_4_BYTE=y
+CONFIG_ESPI_NPCX_PERIPHERAL_DEBUG_PORT_80_MULTI_BYTE=y
+
+# Host interface
+CONFIG_ESPI=y
+CONFIG_ESPI_NPCX_PERIPHERAL_ACPI_SHD_MEM_SIZE=512
+CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION_WRITE_PROTECT_ENABLE=n
+CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION_PORT_NUM=0xe00
+CONFIG_ESPI_VWIRE_INDEX_33H=y
+CONFIG_PLATFORM_EC_AMD_SB_RMI=y
+CONFIG_PLATFORM_EC_PORT80_CUSTOM_FORMAT=y
+CONFIG_PLATFORM_EC_SCI_GPIO=y
+
+# Power button and power sequencing feature.
+CONFIG_AP=y
+CONFIG_AP_X86_AMD=y
+CONFIG_PLATFORM_EC_POWERSEQ=y
+CONFIG_PLATFORM_EC_POWERSEQ_S0IX=y
+CONFIG_PLATFORM_EC_POWERSEQ_AMD=n
+CONFIG_PLATFORM_EC_POWERSEQ_CUSTOMER=y
+
+CONFIG_PLATFORM_EC_POWER_BUTTON=y
+CONFIG_PLATFORM_EC_LID_SWITCH=y
+
+CONFIG_PLATFORM_EC_HIBERNATE_DELAY_SEC=30
+
+# Charger
+CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y
+CONFIG_PLATFORM_EC_CHARGER_ISL9241=y
+CONFIG_PLATFORM_EC_CHARGER_INIT_CUSTOM=y
+CONFIG_PLATFORM_EC_CHARGER_INPUT_CURRENT_DERATE_PCT=0
+CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_DUMP=y
+
+# Battery
+CONFIG_PLATFORM_EC_BATTERY_CHECK_CHARGE_TEMP_LIMITS=y
+CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y
+CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y
+CONFIG_PLATFORM_EC_BATTERY_REVIVE_DISCONNECT=y
+
+# USBC
+CONFIG_PLATFORM_EC_USBC=n
+CONFIG_PLATFORM_EC_STANDALONE_PD_CHIP=y
+
+# Thermal
+CONFIG_PLATFORM_EC_TEMP_SENSOR=y
+CONFIG_PLATFORM_EC_THERMISTOR=n
+CONFIG_PLATFORM_EC_THROTTLE_AP=y
+CONFIG_PLATFORM_EC_TEMP_SENSOR_SB_TSI=y
+CONFIG_PLATFORM_EC_AMD_STT=y
+
+# Fan
+CONFIG_SENSOR=y
+CONFIG_PLATFORM_EC_FAN=y
+CONFIG_LTO=n
+
+# ALS
+CONFIG_PLATFORM_EC_MOTIONSENSE=n
+CONFIG_PLATFORM_EC_DEDICATED_ALS=y
+
+# LED
+CONFIG_PLATFORM_EC_LED_COMMON=y
+CONFIG_PLATFORM_EC_LED_DT=n
+
+# Disable default features we don't want in a minimal example.
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
+CONFIG_PLATFORM_EC_VBOOT_EFS2=n
+CONFIG_PLATFORM_EC_CBI=n
+
+#i2c hid
+CONFIG_I2C_TARGET=y
diff --git a/zephyr/program/framework/src/adc.c b/zephyr/program/framework/src/adc.c
new file mode 100644
index 0000000000..a4e6704ec2
--- /dev/null
+++ b/zephyr/program/framework/src/adc.c
@@ -0,0 +1,98 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * ADC for checking BOARD ID.
+ */
+
+#include "adc.h"
+#include "board_adc.h"
+#include "console.h"
+#include "system.h"
+#include "hooks.h"
+
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_GPIO, format, ## args)
+
+/*
+ * PLATFORM_EC_ADC_RESOLUTION default 10 bit
+ *
+ * +------------------+-----------+--------------+---------+----------------------+
+ * |  BOARD VERSION   |  voltage  |  main board  |   GPU   |     Input module     |
+ * +------------------+-----------+--------------+---------+----------------------+
+ * | BOARD_VERSION_0  |  0    mv  |    Unused    |         |       Reserved       |
+ * | BOARD_VERSION_1  |  173  mv  |    Unused    |         |       Reserved       |
+ * | BOARD_VERSION_2  |  300  mv  |    Unused    |         |       Reserved       |
+ * | BOARD_VERSION_3  |  430  mv  |    Unused    |         |       Reserved       |
+ * | BOARD_VERSION_4  |  588  mv  |    EVT1      |         |       Reserved       |
+ * | BOARD_VERSION_5  |  783  mv  |    Unused    |         |       Reserved       |
+ * | BOARD_VERSION_6  |  905  mv  |    Unused    |         |       Reserved       |
+ * | BOARD_VERSION_7  |  1033 mv  |    DVT1      |         |       Reserved       |
+ * | BOARD_VERSION_8  |  1320 mv  |    DVT2      |         |    Generic A size    |
+ * | BOARD_VERSION_9  |  1500 mv  |    PVT       |         |    Generic B size    |
+ * | BOARD_VERSION_10 |  1650 mv  |    MP        |         |    Generic C size    |
+ * | BOARD_VERSION_11 |  1980 mv  |    Unused    | RID_0   |    10 Key B size     |
+ * | BOARD_VERSION_12 |  2135 mv  |    Unused    | RID_0,1 |       Keyboard       |
+ * | BOARD_VERSION_13 |  2500 mv  |    Unused    | RID_0   |       Touchpad       |
+ * | BOARD_VERSION_14 |  2706 mv  |    Unused    |         |       Reserved       |
+ * | BOARD_VERSION_15 |  2813 mv  |    Unused    |         |    Not installed     |
+ * +------------------+-----------+--------------+---------+----------------------+
+ */
+
+struct {
+	enum board_version_t version;
+	int thresh_mv;
+} const board_versions[] = {
+	{ BOARD_VERSION_0, 85  },
+	{ BOARD_VERSION_1, 233 },
+	{ BOARD_VERSION_2, 360 },
+	{ BOARD_VERSION_3, 492 },
+	{ BOARD_VERSION_4, 649 },
+	{ BOARD_VERSION_5, 844 },
+	{ BOARD_VERSION_6, 965 },
+	{ BOARD_VERSION_7, 1094 },
+	{ BOARD_VERSION_8, 1380 },
+	{ BOARD_VERSION_9, 1562 },
+	{ BOARD_VERSION_10, 1710 },
+	{ BOARD_VERSION_11, 2040 },
+	{ BOARD_VERSION_12, 2197 },
+	{ BOARD_VERSION_13, 2557 },
+	{ BOARD_VERSION_14, 2766 },
+	{ BOARD_VERSION_15, 2814 },
+};
+BUILD_ASSERT(ARRAY_SIZE(board_versions) == BOARD_VERSION_COUNT);
+
+enum board_version_t get_hardware_id(enum adc_channel channel)
+{
+	int version = BOARD_VERSION_UNKNOWN;
+	int mv;
+	int i;
+
+	mv = adc_read_channel(channel);
+
+	if (mv < 0) {
+		CPRINTS("ADC could not read (%d)", mv);
+		return BOARD_VERSION_UNKNOWN;
+	}
+
+	for (i = 0; i < BOARD_VERSION_COUNT; i++)
+		if (mv < board_versions[i].thresh_mv) {
+			version = board_versions[i].version;
+			return version;
+		}
+
+	return version;
+}
+
+__override int board_get_version(void)
+{
+	static int version = BOARD_VERSION_UNKNOWN;
+
+	if (version != BOARD_VERSION_UNKNOWN)
+		return version;
+
+	version = get_hardware_id(ADC_MAIN_BOARD_ID);
+
+	return version;
+}
+
diff --git a/zephyr/program/framework/src/als.c b/zephyr/program/framework/src/als.c
new file mode 100644
index 0000000000..aa4d9cd664
--- /dev/null
+++ b/zephyr/program/framework/src/als.c
@@ -0,0 +1,66 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "als.h"
+#include "cros_als.h"
+#include "common.h"
+#include "driver/als_cm32183.h"
+#include "ec_commands.h"
+#include "i2c.h"
+#include "timer.h"
+
+/*
+ * Read CM32183 light sensor data.
+ */
+int cm32183_read_lux(int *lux, int af)
+{
+	int ret;
+	int data;
+
+	ret = i2c_read16(I2C_PORT_ALS, CM32183_I2C_ADDR,
+		CM32183_REG_ALS_RESULT, &data);
+
+	if (ret)
+		return ret;
+
+	/*
+	 * lux = data * 0.016
+	 * lux = (data * 16 / 1000) * af / 10;
+	 */
+	*lux = data * af * 16 / 10000;
+
+	return EC_SUCCESS;
+}
+
+/**
+ * Initialise CM32183 light sensor.
+ */
+int cm32183_init(void)
+{
+	int retry_count;
+
+	for (retry_count = 0; retry_count < 3; retry_count++) {
+
+		/**
+		 * The resume hook does not match the sensor power on sequence,
+		 * it will cause the sensor initial fail and disable the als task.
+		 * Add the delay time 10ms to retry again if sensor enable fail,
+		 * make sure the sensor and als task are enable.
+		 */
+		if (i2c_write16(I2C_PORT_ALS, CM32183_I2C_ADDR,
+			CM32183_REG_CONFIGURE, CM32183_REG_CONFIGURE_CH_EN))
+			k_msleep(10);
+		else
+			return EC_SUCCESS;
+	}
+
+	return EC_ERROR_OVERFLOW;
+
+}
+
+struct als_t als[] = {
+	{"CAPELLA", cm32183_init, cm32183_read_lux, 32},
+};
+BUILD_ASSERT(ARRAY_SIZE(als) == ALS_COUNT);
diff --git a/zephyr/program/framework/src/battery_extender.c b/zephyr/program/framework/src/battery_extender.c
new file mode 100644
index 0000000000..3b20169368
--- /dev/null
+++ b/zephyr/program/framework/src/battery_extender.c
@@ -0,0 +1,411 @@
+/*
+ * Copyright 2024 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "battery_smart.h"
+#include "board_host_command.h"
+#include "board_charger.h"
+#include "battery_fuel_gauge.h"
+#include "board_function.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "console.h"
+#include "customized_shared_memory.h"
+#include "ec_commands.h"
+#include "extpower.h"
+#include "factory.h"
+#include "host_command.h"
+#include "system.h"
+#include "timer.h"
+#include "util.h"
+#include "hooks.h"
+
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+
+#define DAY (24 * HOUR)
+#define TIMES2DAYS(d) (d / DAY)
+#define TIMES2MINUTES(m) (m / MINUTE)
+#define TIMES2SECOND(s) (s / SECOND)
+
+#define BATTERY_EXTENDER_STAGE1_VOLTAGE(v) (v * 97 / 100)
+#define BATTERY_EXTENDER_STAGE2_VOLTAGE(v) (v * 96 / 100)
+
+enum battery_extender_stage_t {
+	BATT_EXTENDER_STAGE_0,
+	BATT_EXTENDER_STAGE_1,
+	BATT_EXTENDER_STAGE_2,
+};
+
+static bool batt_extender_disable;
+static uint64_t battery_extender_trigger = 5*DAY;
+static uint64_t battery_extender_reset = 30*MINUTE;
+static int stage;
+static timestamp_t batt_extender_deadline;
+static timestamp_t batt_extender_deadline_stage2;
+
+static timestamp_t reset_deadline;
+static int sustainer_lower = 100;
+static int sustainer_upper = 100;
+
+static uint8_t charging_maximum_level = EC_CHARGE_LIMIT_RESTORE;
+static uint8_t old_charger_limit;
+
+static void extender_init(void)
+{
+	timestamp_t now = get_time();
+
+	batt_extender_deadline.val =
+			now.val + battery_extender_trigger;
+	batt_extender_deadline_stage2.val =
+			now.val + battery_extender_trigger + 2*DAY;
+	reset_deadline.val = 0; /* not active */
+}
+DECLARE_HOOK(HOOK_INIT, extender_init, HOOK_PRIO_DEFAULT);
+
+int charger_sustainer_percentage(void)
+{
+	if (!charging_maximum_level)
+		return 100;
+	return charging_maximum_level;
+}
+
+void charger_sustainer_reset(void)
+{
+	old_charger_limit = 0;
+	battery_sustainer_set(-1, -1);
+	set_chg_ctrl_mode(CHARGE_CONTROL_NORMAL);
+}
+
+static void battery_percentage_control(void)
+{
+	if (charging_maximum_level == EC_CHARGE_LIMIT_RESTORE) {
+		system_get_bbram(SYSTEM_BBRAM_IDX_CHARGE_LIMIT_MAX, &charging_maximum_level);
+		if (charging_maximum_level & CHG_LIMIT_OVERRIDE)
+			charging_maximum_level = charging_maximum_level & 0x64;
+	}
+
+	if (charging_maximum_level & CHG_LIMIT_OVERRIDE ||
+		!charging_maximum_level ||
+		charging_maximum_level == 100) {
+		charger_sustainer_reset();
+		return;
+	}
+
+	if (old_charger_limit != charging_maximum_level) {
+		old_charger_limit = charging_maximum_level;
+		battery_sustainer_set(MAX(20, (charging_maximum_level - 5)),
+			MAX(20, charging_maximum_level));
+	}
+}
+
+void battery_extender(void)
+{
+	timestamp_t now = get_time();
+
+	if (stage == BATT_EXTENDER_STAGE_0)
+		battery_percentage_control();
+
+	/* don't runnig extender when unit in factory mode */
+	if (batt_extender_disable || factory_status()) {
+		stage = BATT_EXTENDER_STAGE_0;
+		reset_deadline.val = 0;
+		batt_extender_deadline.val = 0;
+		batt_extender_deadline_stage2.val = 0;
+		return;
+	}
+
+	if (extpower_is_present()) {
+		/* just keep pushing the reset timer into the future if we are on AC */
+		reset_deadline.val = now.val + battery_extender_reset;
+	}
+
+	if (sustainer_upper != charger_sustainer_percentage()) {
+		sustainer_upper = charger_sustainer_percentage();
+		sustainer_lower = sustainer_upper - 5;
+		/* if we already trigger stage, set 5 SECOND to update the sustainer again */
+		if (stage == BATT_EXTENDER_STAGE_1) {
+			batt_extender_deadline.val = now.val + 5 * SECOND;
+		} else if (stage == BATT_EXTENDER_STAGE_2)
+			batt_extender_deadline_stage2.val = now.val + 5 * SECOND;
+	}
+
+	if (reset_deadline.val &&
+			timestamp_expired(reset_deadline, &now)) {
+		reset_deadline.val = 0;
+
+		stage = BATT_EXTENDER_STAGE_0;
+		batt_extender_deadline.val =
+			now.val + battery_extender_trigger;
+		batt_extender_deadline_stage2.val =
+				now.val + battery_extender_trigger + 2*DAY;
+		/* if charger limit has been set don't clear sustainer and charger mode */
+		if (charger_sustainer_percentage() == 100) {
+			charger_sustainer_reset();
+		}
+	}
+
+	if (batt_extender_deadline_stage2.val &&
+			timestamp_expired(batt_extender_deadline_stage2, &now)) {
+		batt_extender_deadline_stage2.val = 0;
+		stage = BATT_EXTENDER_STAGE_2;
+		battery_sustainer_set(MIN(85, sustainer_lower), MIN(87, sustainer_upper));
+	} else if (batt_extender_deadline.val &&
+			timestamp_expired(batt_extender_deadline, &now)) {
+		batt_extender_deadline.val = 0;
+		stage = BATT_EXTENDER_STAGE_1;
+		battery_sustainer_set(MIN(90, sustainer_lower), MIN(95, sustainer_upper));
+	}
+}
+DECLARE_HOOK(HOOK_SECOND, battery_extender, HOOK_PRIO_DEFAULT);
+
+
+/* Host command for battery extender feature */
+static enum ec_status battery_extender_hc(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_battery_extender *p = args->params;
+	struct ec_response_battery_extender *r = args->response;
+	timestamp_t now = get_time();
+
+	if (p->cmd == BATT_EXTENDER_WRITE_CMD) {
+
+		if ((p->trigger_days != TIMES2DAYS(battery_extender_trigger)) &&
+			(p->trigger_days >= 1 && p->trigger_days <= 99)) {
+			battery_extender_trigger = p->trigger_days * DAY;
+			if (battery_extender_trigger != 0) {
+				batt_extender_deadline.val =
+						now.val + battery_extender_trigger;
+				batt_extender_deadline_stage2.val =
+						now.val + battery_extender_trigger + 2*DAY;
+			} else {
+				batt_extender_deadline.val = 0;
+				batt_extender_deadline_stage2.val = 0;
+			}
+		}
+
+		if ((p->reset_minutes != TIMES2MINUTES(battery_extender_reset)) &&
+			(p->reset_minutes >= 1 && p->reset_minutes <= 9999)) {
+			battery_extender_reset = p->reset_minutes * MINUTE;
+			if (battery_extender_reset) {
+				reset_deadline.val =
+					now.val + battery_extender_reset;
+			} else {
+				reset_deadline.val = 0;
+			}
+		}
+
+		if (batt_extender_disable != p->disable) {
+			batt_extender_disable = p->disable;
+			if (batt_extender_disable) {
+				/* if charger limit has been set don't control sustainer again */
+				if (charger_sustainer_percentage() == 100) {
+					charger_sustainer_reset();
+				}
+				stage = BATT_EXTENDER_STAGE_0;
+			}
+		}
+		return EC_SUCCESS;
+	} else if (p->cmd == BATT_EXTENDER_READ_CMD) {
+		/* return the current stage for debugging */
+		r->current_stage = stage;
+		r->disable = batt_extender_disable;
+
+		if (!timestamp_expired(batt_extender_deadline, &now)) {
+			r->trigger_timedelta = batt_extender_deadline.val - now.val;
+		} else
+			r->trigger_timedelta = 0;
+
+		r->trigger_days = (uint16_t)(battery_extender_trigger/DAY);
+
+
+		if (!timestamp_expired(reset_deadline, &now)) {
+			r->reset_timedelta = reset_deadline.val - now.val;
+		} else
+			r->reset_timedelta = 0;
+
+		r->reset_minutes = (uint16_t)(battery_extender_reset/MINUTE);
+
+		args->response_size = sizeof(*r);
+		return EC_SUCCESS;
+	} else
+		return EC_ERROR_PARAM1;
+}
+DECLARE_HOST_COMMAND(EC_CMD_BATTERY_EXTENDER, battery_extender_hc, EC_VER_MASK(0));
+
+/*****************************************************************************/
+/* Host command */
+
+static enum ec_status cmd_charging_limit_control(struct host_cmd_handler_args *args)
+{
+
+	const struct ec_params_ec_chg_limit_control *p = args->params;
+	struct ec_response_chg_limit_control *r = args->response;
+
+	if (p->modes & CHG_LIMIT_DISABLE) {
+		charging_maximum_level = 0;
+		system_set_bbram(SYSTEM_BBRAM_IDX_CHARGE_LIMIT_MAX, 0);
+	}
+
+	if (p->modes & CHG_LIMIT_SET_LIMIT) {
+		if (p->max_percentage < 20)
+			return EC_RES_ERROR;
+
+		charging_maximum_level = p->max_percentage;
+		system_set_bbram(SYSTEM_BBRAM_IDX_CHARGE_LIMIT_MAX, charging_maximum_level);
+	}
+
+	if (p->modes & CHG_LIMIT_OVERRIDE)
+		charging_maximum_level = charging_maximum_level | CHG_LIMIT_OVERRIDE;
+
+	if (p->modes & CHG_LIMIT_GET_LIMIT) {
+		system_get_bbram(SYSTEM_BBRAM_IDX_CHARGE_LIMIT_MAX, &charging_maximum_level);
+		r->max_percentage = charging_maximum_level;
+		args->response_size = sizeof(*r);
+	}
+
+	battery_percentage_control();
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_CHARGE_LIMIT_CONTROL, cmd_charging_limit_control,
+			EC_VER_MASK(0));
+
+static uint64_t cmd_parse_timestamp(int argc, const char **argv)
+{
+	uint64_t time_val = 0;
+	char *e;
+
+	if (argc >= 3) {
+		time_val = strtoi(argv[2], &e, 0);
+		if (!strncmp(argv[3], "s", 1)) {
+			time_val *= SECOND;
+		} else	if (!strncmp(argv[3], "m", 1)) {
+			time_val *= MINUTE;
+		} else	if (!strncmp(argv[3], "h", 1)) {
+			time_val *= HOUR;
+		} else if (!strncmp(argv[3], "d", 1)) {
+			time_val *= DAY;
+		} else {
+			CPRINTF("invalid option for time scale: %s. Valid options: [s,h,d]\n",
+				argv[3]);
+			return EC_ERROR_PARAM3;
+		}
+		return time_val;
+	}
+
+	CPRINTF("invalid parameters:\n");
+	return 0;
+}
+
+static void print_time_offset(uint64_t t_end, uint64_t t_start)
+{
+	uint64_t t = t_end - t_start;
+	uint64_t d = TIMES2DAYS(t);
+	uint64_t h = (t % DAY) / HOUR;
+	uint64_t m = (t % HOUR) / MINUTE;
+	uint64_t s = (t % MINUTE) / SECOND;
+
+	if (t_end < t_start) {
+		CPRINTF("Expired\n");
+	} else {
+		CPRINTF("%lldD:%lldH:%lldM:%lldS\n", d, h, m, s);
+	}
+}
+
+/* Console command for battery extender manual control */
+static int cmd_batt_extender(int argc, const char **argv)
+{
+	int disable;
+	timestamp_t now = get_time();
+
+	if (argc >= 2) {
+		if (!strncmp(argv[1], "en", 2) || !strncmp(argv[1], "dis", 3)) {
+			if (!parse_bool(argv[1], &disable))
+				return EC_ERROR_PARAM1;
+
+			batt_extender_disable = !disable;
+			CPRINTS("battery extender %s",
+				disable ? "enabled" : "disabled");
+			if (batt_extender_disable) {
+				charger_sustainer_reset();
+				stage = BATT_EXTENDER_STAGE_0;
+			} else {
+				if (battery_extender_reset) {
+					reset_deadline.val =
+						now.val + battery_extender_reset;
+				}
+				if (battery_extender_trigger != 0) {
+					batt_extender_deadline.val =
+							now.val + battery_extender_trigger;
+					batt_extender_deadline_stage2.val =
+							now.val + battery_extender_trigger + 2*DAY;
+				}
+			}
+		} else if (!strncmp(argv[1], "timeext2", 8)) {
+			batt_extender_deadline_stage2.val =
+				now.val + cmd_parse_timestamp(argc, argv);
+		} else if (!strncmp(argv[1], "timeext", 7)) {
+			batt_extender_deadline.val = now.val + cmd_parse_timestamp(argc, argv);
+		} else if (!strncmp(argv[1], "timerst", 7)) {
+			reset_deadline.val = now.val + cmd_parse_timestamp(argc, argv);
+		} else if (!strncmp(argv[1], "trigger", 7)) {
+			if (argc < 3)
+				return EC_ERROR_PARAM2;
+
+			battery_extender_trigger = cmd_parse_timestamp(argc, argv);
+			CPRINTF("update battery extender trigger ");
+			print_time_offset(battery_extender_trigger, 0);
+		} else if (!strncmp(argv[1], "reset", 5)) {
+			if (argc < 3)
+				return EC_ERROR_PARAM2;
+
+			battery_extender_reset =  cmd_parse_timestamp(argc, argv);
+			CPRINTF("update battery extender reset ");
+			print_time_offset(battery_extender_reset, 0);
+		} else
+			return EC_ERROR_PARAM_COUNT;
+	} else {
+		CPRINTF("Battery extender %sabled\n", batt_extender_disable ? "dis" : "en");
+		CPRINTF("\tTrigger:");
+		print_time_offset(battery_extender_trigger, 0);
+		CPRINTF("\tReset:");
+		print_time_offset(battery_extender_reset, 0);
+
+		CPRINTF("\tCurrent stage:%d\n", stage);
+		CPRINTF("\tBattery extender timer\n");
+		if (batt_extender_deadline.val) {
+			CPRINTF("\t - Stage 1 expires in: ");
+			print_time_offset(batt_extender_deadline.val, now.val);
+		}
+		if (batt_extender_deadline_stage2.val) {
+			CPRINTF("\t - Stage 2 expires in: ");
+			print_time_offset(batt_extender_deadline_stage2.val, now.val);
+		}
+		CPRINTF("\tBattery extender reset timer %sable\n",
+			reset_deadline.val ? "en" : "dis");
+		if (reset_deadline.val) {
+			CPRINTF("\t - expires in: ");
+			print_time_offset(reset_deadline.val, now.val);
+		}
+		CPRINTF("\tsustainer percentage:\n");
+		if (stage == BATT_EXTENDER_STAGE_1) {
+			sustainer_lower = MIN(90, sustainer_lower);
+			sustainer_upper = MIN(95, sustainer_upper);
+		} else if (stage == BATT_EXTENDER_STAGE_2) {
+			sustainer_lower = MIN(85, sustainer_lower);
+			sustainer_upper = MIN(87, sustainer_upper);
+		}
+
+		CPRINTF("\tlower: %d, upper: %d\n", sustainer_lower, sustainer_upper);
+		CPRINTF("\tUser charge limit:%d\n", charging_maximum_level);
+	}
+
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(battextender, cmd_batt_extender,
+			"[enable/disable/days/reset/manual][days:1-99][reset:1-9999][manual:1/0]",
+			"battery extender control");
diff --git a/zephyr/program/framework/src/board_function.c b/zephyr/program/framework/src/board_function.c
new file mode 100644
index 0000000000..89fd01c7b4
--- /dev/null
+++ b/zephyr/program/framework/src/board_function.c
@@ -0,0 +1,267 @@
+/*
+ * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/drivers/gpio.h>
+
+#include "board_host_command.h"
+#include "board_function.h"
+#include "chipset.h"
+#include "console.h"
+#include "customized_shared_memory.h"
+#include "diagnostics.h"
+#include "ec_commands.h"
+#include "extpower.h"
+#include "flash_storage.h"
+#include "gpio/gpio_int.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "power_button.h"
+#include "system.h"
+#include "temp_sensor.h"
+#include "util.h"
+#include "zephyr_console_shim.h"
+
+#ifdef CONFIG_BOARD_LOTUS
+#include "input_module.h"
+#endif
+
+/* Console output macros */
+#define CPRINTS(format, args...) cprints(CC_HOSTCMD, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_HOSTCMD, format, ##args)
+
+/* counter for chassis open while ec no power, only rtc power */
+static uint8_t chassis_vtr_open_count;
+/* counter for chassis open while ec has power */
+static uint8_t chassis_open_count;
+/* counter for chassis press while ec has power, clear when enter S0 */
+static uint8_t chassis_press_counter;
+/* make sure only trigger once */
+static uint8_t chassis_once_flag;
+
+static uint64_t chassis_open_hibernate_time;
+
+static uint8_t init = 1;
+
+int bios_function_status(uint16_t type, uint16_t addr, uint8_t flag)
+{
+	uint8_t status;
+
+	switch (type) {
+	case TYPE_MEMMAP:
+		status = (*host_get_memmap(addr) & flag) ? true : false;
+		break;
+	case TYPE_BBRAM:
+		system_get_bbram(addr, &status);
+		break;
+	case TYPE_FLASH:
+		status = flash_storage_get(addr);
+		break;
+	}
+	return status;
+}
+
+/*
+ * Configure the AP boot up function
+ */
+int ac_boot_status(void)
+{
+	return bios_function_status(TYPE_MEMMAP, EC_CUSTOMIZED_MEMMAP_BIOS_SETUP_FUNC,
+		EC_AC_ATTACH_BOOT);
+}
+
+void bios_function_detect(void)
+{
+	flash_storage_update(FLASH_FLAGS_ACPOWERON, ac_boot_status());
+
+	flash_storage_update(FLASH_FLAGS_STANDALONE, get_standalone_mode() ? 1 : 0);
+#ifdef CONFIG_BOARD_LOTUS
+	flash_storage_update(FLASH_FLAGS_INPUT_MODULE_POWER, get_detect_mode());
+#endif
+	flash_storage_commit();
+}
+
+int chassis_cmd_clear(int type)
+{
+	int press;
+
+	if (type) {
+		/* clear when host cmd send magic value */
+		chassis_vtr_open_count = 0;
+		chassis_open_count = 0;
+	} else {
+		/* clear when bios get, bios will get this data while post */
+		press = chassis_press_counter;
+		chassis_press_counter = 0;
+		return press;
+	}
+	return -1;
+}
+
+static int power_button_state;
+static void power_button_signal_deferred(void);
+DECLARE_DEFERRED(power_button_signal_deferred);
+
+static void power_button_signal_deferred(void)
+{
+#if DT_NODE_EXISTS(DT_ALIAS(gpio_check_fp_control))
+
+	static timestamp_t stime;
+
+	if (!stime.val)
+		stime = get_time();
+
+	/**
+	 * Ignore the power button signal when fp control enable
+	 *
+	 * If user removes the fingerprint module, the fp control signal is always high.
+	 * Only enable this feature when the system does not enable the standalone mode,
+	 * and system state in S0.
+	 */
+	if (gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_check_fp_control)) &&
+		chipset_in_state(CHIPSET_STATE_ON) && !get_standalone_mode()) {
+		if ((get_time().val < stime.val + 4 * SECOND) && !power_button_state) {
+			hook_call_deferred(&power_button_signal_deferred_data, 100 * MSEC);
+			return;
+		} else if ((get_time().val > stime.val + 4 * SECOND) && !power_button_state)
+			chipset_force_shutdown(CHIPSET_SHUTDOWN_BOARD_CUSTOM);
+		else
+			stime.val = 0;
+	}
+
+	stime.val = 0;
+#endif
+	/* power_button_interrupt may not use the signal variant, so always set 0 */
+	power_button_interrupt(0);
+}
+
+void board_power_button_interrupt(enum gpio_signal signal)
+{
+	power_button_state = gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_on_off_btn_l));
+	hook_call_deferred(&power_button_signal_deferred_data, 50);
+}
+
+static void chassis_open_hibernate(void)
+{
+	uint64_t now;
+	int chassis_status = gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_chassis_open_l));
+
+	/* We don't need to hibernate EC when extpower is present or chassis is closed */
+	if (extpower_is_present() || chassis_status || !chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return;
+
+	/* EC does not update the chassis open hibernate timer, ignore it */
+	if (!chassis_open_hibernate_time)
+		return;
+
+	now = get_time().val;
+	CPRINTS("chassis_open_hibernate_time:%lld, now:%lld", chassis_open_hibernate_time, now);
+	if (now > chassis_open_hibernate_time) {
+		CPRINTS("Chassis open hibernate");
+		system_hibernate(0, 0);
+	}
+}
+DECLARE_HOOK(HOOK_AC_CHANGE, chassis_open_hibernate, HOOK_PRIO_DEFAULT);
+DECLARE_DEFERRED(chassis_open_hibernate);
+
+__override enum critical_shutdown
+board_system_is_idle(uint64_t last_shutdown_time, uint64_t *target,
+		     uint64_t now)
+{
+	/* update the chassis open target time = 30s - 28s*/
+	chassis_open_hibernate_time = *target - 28000000;
+
+	/* After setting the chassis open hibernate timer, delay 2.5s to check the chassis status */
+	hook_call_deferred(&chassis_open_hibernate_data, 2500 * MSEC);
+
+	if (now < *target)
+		return CRITICAL_SHUTDOWN_IGNORE;
+
+	CPRINTS("SDC Safe");
+	return CRITICAL_SHUTDOWN_HIBERNATE;
+}
+
+__overridable void project_chassis_function(enum gpio_signal signal)
+{
+}
+
+static void check_chassis_open(void)
+{
+	if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_chassis_open_l)) == 0) {
+		CPRINTS("Chassis was opened");
+		/* Record the chassis was open status in bbram */
+		if (!chassis_once_flag)
+			system_set_bbram(SYSTEM_BBRAM_IDX_CHASSIS_WAS_OPEN, 1);
+
+		chassis_once_flag = 1;
+
+		if (init) {
+			system_get_bbram(SYSTEM_BBRAM_IDX_CHASSIS_VTR_OPEN,
+				&chassis_vtr_open_count);
+			if (chassis_vtr_open_count < 0xFF)
+				chassis_vtr_open_count++;
+			system_set_bbram(SYSTEM_BBRAM_IDX_CHASSIS_VTR_OPEN, chassis_vtr_open_count);
+		} else {
+			system_get_bbram(SYSTEM_BBRAM_IDX_CHASSIS_TOTAL,
+				&chassis_open_count);
+			if (chassis_open_count < 0xFF)
+				chassis_open_count++;
+			system_set_bbram(SYSTEM_BBRAM_IDX_CHASSIS_TOTAL, chassis_open_count);
+		}
+
+		/* Counter for chassis pin */
+		if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+			if (chassis_press_counter < 0xFF)
+				chassis_press_counter++;
+	} else if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_chassis_open_l)) == 1
+			&& chassis_once_flag) {
+
+		CPRINTS("Chassis was closed");
+		chassis_once_flag = 0;
+	}
+
+	hook_call_deferred(&chassis_open_hibernate_data, 0);
+}
+DECLARE_DEFERRED(check_chassis_open);
+
+void chassis_interrupt_handler(enum gpio_signal signal)
+{
+	project_chassis_function(signal);
+	hook_call_deferred(&check_chassis_open_data, 50 * MSEC);
+}
+
+static void bios_function_init(void)
+{
+	/* restore the bios setup menu setting */
+	*host_get_memmap(EC_CUSTOMIZED_MEMMAP_BIOS_SETUP_FUNC) =
+		flash_storage_get(FLASH_FLAGS_ACPOWERON);
+
+	if (flash_storage_get(FLASH_FLAGS_STANDALONE))
+		set_standalone_mode(1);
+#ifdef CONFIG_BOARD_LOTUS
+	set_detect_mode(flash_storage_get(FLASH_FLAGS_INPUT_MODULE_POWER));
+#endif
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_chassis_open));
+
+	init = 1;
+	check_chassis_open();
+	init = 0;
+}
+DECLARE_HOOK(HOOK_INIT, bios_function_init, HOOK_PRIO_DEFAULT + 1);
+
+/*
+ * at Lotus and azalea all temps sensor power source reference SLP_S3
+ * so don't read any temps sensor when power not ready.
+ */
+__override int board_temp_smi_evet(void)
+{
+	/*
+	 * we don't send thermal smi event to host, if need any
+	 * printing, add log and condition in here, don't need
+	 * return true.
+	 */
+
+	return false;
+}
diff --git a/zephyr/program/framework/src/board_host_command.c b/zephyr/program/framework/src/board_host_command.c
new file mode 100644
index 0000000000..22a0adef85
--- /dev/null
+++ b/zephyr/program/framework/src/board_host_command.c
@@ -0,0 +1,505 @@
+/*
+ * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/drivers/gpio.h>
+
+#include "board_host_command.h"
+#include "board_function.h"
+#include "chipset.h"
+#include "console.h"
+#include "common_cpu_power.h"
+#include "customized_shared_memory.h"
+#include "cypress_pd_common.h"
+#include "diagnostics.h"
+#include "ec_commands.h"
+#include "factory.h"
+#include "fan.h"
+#include "flash_storage.h"
+#include "gpio.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "keyboard_8042_sharedlib.h"
+#include "keyboard_8042.h"
+#include "led.h"
+#include "lpc.h"
+#include "power_sequence.h"
+#include "system.h"
+#include "uefi_app_mode.h"
+#include "util.h"
+#include "zephyr_console_shim.h"
+
+#ifdef CONFIG_BOARD_LOTUS
+#include "gpu.h"
+#include "input_module.h"
+#endif
+
+/* Console output macros */
+#define CPRINTS(format, args...) cprints(CC_HOSTCMD, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_HOSTCMD, format, ##args)
+
+static void sci_enable(void);
+DECLARE_DEFERRED(sci_enable);
+
+#ifdef CONFIG_BOARD_LOTUS
+static void gpu_typec_detect(void)
+{
+	set_host_dp_ready(1);
+}
+DECLARE_DEFERRED(gpu_typec_detect);
+#endif
+
+static void sci_enable(void)
+{
+	if (*host_get_memmap(EC_CUSTOMIZED_MEMMAP_SYSTEM_FLAGS) & ACPI_DRIVER_READY) {
+		/* when host set EC driver ready flag, EC need to enable SCI */
+		lpc_set_host_event_mask(LPC_HOST_EVENT_SCI, SCI_HOST_EVENT_MASK);
+		bios_function_detect();
+#ifdef CONFIG_BOARD_LOTUS
+		/* hook_call_deferred(&gpu_typec_detect_data, 500 * MSEC); */
+		gpu_typec_detect();
+#endif
+	} else
+		hook_call_deferred(&sci_enable_data, 250 * MSEC);
+}
+
+static void sci_disable(void)
+{
+	lpc_set_host_event_mask(LPC_HOST_EVENT_SCI, 0);
+#ifdef CONFIG_BOARD_LOTUS
+	set_host_dp_ready(0);
+#endif
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, sci_disable, HOOK_PRIO_DEFAULT);
+
+static enum ec_status flash_notified(struct host_cmd_handler_args *args)
+{
+
+	const struct ec_params_flash_notified *p = args->params;
+
+	switch (p->flags & 0x03) {
+	case FLASH_FIRMWARE_START:
+		CPRINTS("Start flashing firmware, flags:0x%02x", p->flags);
+		gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_powerbtn));
+		gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_lid_open));
+
+		if ((p->flags & FLASH_FLAG_PD) == FLASH_FLAG_PD) {
+			gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pd_chip0_interrupt));
+			gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pd_chip1_interrupt));
+			set_pd_fw_update(true);
+		}
+	case FLASH_ACCESS_SPI:
+		break;
+
+	case FLASH_FIRMWARE_DONE:
+		CPRINTS("Flash done, flags:0x%02x", p->flags);
+		gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_powerbtn));
+		gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pd_chip0_interrupt));
+		gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pd_chip1_interrupt));
+		gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_lid_open));
+
+		set_pd_fw_update(false);
+		/* resetup PD controllers */
+		if ((p->flags & FLASH_FLAG_PD) == FLASH_FLAG_PD)
+			cypd_reinitialize();
+
+	case FLASH_ACCESS_SPI_DONE:
+		break;
+	default:
+		return EC_ERROR_INVAL;
+	}
+
+	return EC_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_FLASH_NOTIFIED, flash_notified,
+			EC_VER_MASK(0));
+
+static enum ec_status factory_mode(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_factory_notified *p = args->params;
+	int enable = 1;
+
+
+	if (p->flags)
+		factory_setting(enable);
+	else
+		factory_setting(!enable);
+
+	if (p->flags == RESET_FOR_SHIP) {
+		/* clear bbram for shipping */
+		system_set_bbram(SYSTEM_BBRAM_IDX_CHARGE_LIMIT_MAX, 0);
+		flash_storage_load_defaults();
+		flash_storage_commit();
+	}
+
+	return EC_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_FACTORY_MODE, factory_mode,
+			EC_VER_MASK(0));
+
+static enum ec_status hc_pwm_get_fan_actual_rpm(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_ec_pwm_get_actual_fan_rpm *p = args->params;
+	struct ec_response_pwm_get_actual_fan_rpm *r = args->response;
+
+	if (FAN_CH_COUNT == 0 || p->index >= FAN_CH_COUNT)
+		return EC_ERROR_INVAL;
+
+	r->rpm = fan_get_rpm_actual(FAN_CH(p->index));
+	args->response_size = sizeof(*r);
+
+	return EC_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_FAN_ACTUAL_RPM,
+		     hc_pwm_get_fan_actual_rpm,
+		     EC_VER_MASK(0));
+
+static enum ec_status enter_non_acpi_mode(struct host_cmd_handler_args *args)
+{
+	/**
+	 * TODO:
+	 * When system boot into OS, host will call this command to verify,
+	 * It means system should in S0 state, and we need to set the resume
+	 * S0ix flag to avoid the wrong state when unknown reason warm boot.
+	 */
+	if (chipset_in_state(CHIPSET_STATE_STANDBY))
+		*host_get_memmap(EC_CUSTOMIZED_MEMMAP_POWER_STATE) |= EC_PS_RESUME_S0ix;
+
+	clear_power_flags();
+
+	*host_get_memmap(EC_CUSTOMIZED_MEMMAP_SYSTEM_FLAGS) &= ~ACPI_DRIVER_READY;
+	*host_get_memmap(EC_MEMMAP_POWER_SLIDE) = 0x0;
+	*host_get_memmap(EC_MEMMAP_STT_TABLE_NUMBER) = 0x0;
+
+	update_apu_ready(1);
+
+	/**
+	 * Even though the protocol returns EC_SUCCESS,
+	 * the system still does not update the power limit.
+	 * So move the update process at here.
+	 */
+	update_soc_power_limit(true, false);
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_NON_ACPI_NOTIFY, enter_non_acpi_mode, EC_VER_MASK(0));
+
+static enum ec_status host_chassis_intrusion_control(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_chassis_intrusion_control *p = args->params;
+	struct ec_response_chassis_intrusion_control *r = args->response;
+
+	if (p->clear_magic == EC_PARAM_CHASSIS_INTRUSION_MAGIC) {
+		chassis_cmd_clear(1);
+		system_set_bbram(SYSTEM_BBRAM_IDX_CHASSIS_TOTAL, 0);
+		system_set_bbram(SYSTEM_BBRAM_IDX_CHASSIS_VTR_OPEN, 0);
+		system_set_bbram(SYSTEM_BBRAM_IDX_CHASSIS_MAGIC, EC_PARAM_CHASSIS_BBRAM_MAGIC);
+		return EC_SUCCESS;
+	}
+
+	if (p->clear_chassis_status) {
+		system_set_bbram(SYSTEM_BBRAM_IDX_CHASSIS_WAS_OPEN, 0);
+		return EC_SUCCESS;
+	}
+
+	system_get_bbram(SYSTEM_BBRAM_IDX_CHASSIS_WAS_OPEN, &r->chassis_ever_opened);
+	system_get_bbram(SYSTEM_BBRAM_IDX_CHASSIS_MAGIC, &r->coin_batt_ever_remove);
+	system_get_bbram(SYSTEM_BBRAM_IDX_CHASSIS_TOTAL, &r->total_open_count);
+	system_get_bbram(SYSTEM_BBRAM_IDX_CHASSIS_VTR_OPEN, &r->vtr_open_count);
+
+	args->response_size = sizeof(*r);
+
+	return EC_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_CHASSIS_INTRUSION, host_chassis_intrusion_control,
+			EC_VER_MASK(0));
+
+static enum ec_status cmd_diagnosis(struct host_cmd_handler_args *args)
+{
+
+	const struct ec_params_diagnosis *p = args->params;
+
+	set_bios_diagnostic(p->diagnosis_code);
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_DIAGNOSIS, cmd_diagnosis,
+			EC_VER_MASK(0));
+
+static enum ec_status cmd_get_hw_diag(struct host_cmd_handler_args *args)
+{
+	struct ec_response_get_hw_diag *r = args->response;
+
+	r->hw_diagnostics = get_hw_diagnostic();
+	r->bios_complete = is_bios_complete();
+	r->device_complete = is_device_complete();
+
+	args->response_size = sizeof(*r);
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_GET_HW_DIAG, cmd_get_hw_diag,
+			EC_VER_MASK(0));
+
+#ifdef CONFIG_BOARD_AZALEA
+static enum ec_status update_keyboard_matrix(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_update_keyboard_matrix *p = args->params;
+	struct ec_params_update_keyboard_matrix *r = args->response;
+
+	int i;
+
+	if (p->num_items > 32) {
+		return EC_ERROR_INVAL;
+	}
+	if (p->write) {
+		for (i = 0; i < p->num_items; i++) {
+			set_scancode_set2(p->scan_update[i].row, p->scan_update[i].col
+					, p->scan_update[i].scanset);
+		}
+	}
+	r->num_items = p->num_items;
+	for (i = 0; i < p->num_items; i++) {
+		r->scan_update[i].row = p->scan_update[i].row;
+		r->scan_update[i].col = p->scan_update[i].col;
+		r->scan_update[i].scanset = get_scancode_set2(p->scan_update[i].row
+			, p->scan_update[i].col);
+	}
+	args->response_size = sizeof(struct ec_params_update_keyboard_matrix);
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_UPDATE_KEYBOARD_MATRIX, update_keyboard_matrix, EC_VER_MASK(0));
+#endif
+
+static enum ec_status fp_led_level_control(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_fp_led_control *p = args->params;
+	struct ec_response_fp_led_level *r = args->response;
+	uint8_t led_level = FP_LED_HIGH;
+
+	if (p->get_led_level) {
+		system_get_bbram(SYSTEM_BBRAM_IDX_FP_LED_LEVEL, &r->level);
+		args->response_size = sizeof(*r);
+		return EC_RES_SUCCESS;
+	}
+
+	switch (p->set_led_level) {
+	case FP_LED_BRIGHTNESS_HIGH:
+		led_level = FP_LED_HIGH;
+		break;
+	case FP_LED_BRIGHTNESS_MEDIUM:
+		led_level = FP_LED_MEDIUM;
+		break;
+	case FP_LED_BRIGHTNESS_LOW:
+		led_level = FP_LED_LOW;
+		break;
+	default:
+		return EC_RES_INVALID_PARAM;
+	}
+
+	system_set_bbram(SYSTEM_BBRAM_IDX_FP_LED_LEVEL, led_level);
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_FP_LED_LEVEL_CONTROL, fp_led_level_control, EC_VER_MASK(0));
+
+static enum ec_status chassis_open_check(struct host_cmd_handler_args *args)
+{
+	struct ec_response_chassis_open_check *r = args->response;
+	int status = gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_chassis_open_l));
+
+	r->status = !status & 0x01;
+	args->response_size = sizeof(*r);
+
+	return EC_RES_SUCCESS;
+
+}
+DECLARE_HOST_COMMAND(EC_CMD_CHASSIS_OPEN_CHECK, chassis_open_check, EC_VER_MASK(0));
+
+static enum ec_status enter_acpi_mode(struct host_cmd_handler_args *args)
+{
+	hook_call_deferred(&sci_enable_data, 250 * MSEC);
+
+#ifdef CONFIG_BOARD_LOTUS
+	/* Need to cleanly enumerate keyboard in OS, otherwise NKRO won't work without hotplug */
+	/* So we reset the input modules right on entry to OS */
+	input_modules_reset();
+#endif
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_ACPI_NOTIFY, enter_acpi_mode, EC_VER_MASK(0));
+
+static enum ec_status read_pd_versoin(struct host_cmd_handler_args *args)
+{
+	struct ec_response_read_pd_version *r = args->response;
+
+	memcpy(r->pd0_version, get_pd_version(0), sizeof(r->pd0_version));
+	memcpy(r->pd1_version, get_pd_version(1), sizeof(r->pd1_version));
+
+	args->response_size = sizeof(*r);
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_READ_PD_VERSION, read_pd_versoin, EC_VER_MASK(0));
+
+static enum ec_status standalone_mode(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_standalone_mode *p = args->params;
+
+	set_standalone_mode((int)p->enable);
+	return EC_RES_SUCCESS;
+
+}
+DECLARE_HOST_COMMAND(EC_CMD_STANDALONE_MODE, standalone_mode, EC_VER_MASK(0));
+
+static enum ec_status chassis_counter(struct host_cmd_handler_args *args)
+{
+	struct ec_response_chassis_counter *r = args->response;
+
+	r->press_counter = chassis_cmd_clear(0);
+	CPRINTS("Read chassis counter: %d", r->press_counter);
+
+	args->response_size = sizeof(*r);
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_CHASSIS_COUNTER, chassis_counter, EC_VER_MASK(0));
+
+static enum ec_status  host_command_get_simple_version(struct host_cmd_handler_args *args)
+{
+	struct ec_response_get_custom_version *r = args->response;
+	char temp_version[32];
+	int idx;
+
+	strzcpy(temp_version, system_get_version(EC_IMAGE_RO),
+		sizeof(temp_version));
+
+	for (idx = 0; idx < sizeof(r->simple_version); idx++) {
+		r->simple_version[idx] = temp_version[idx + 18];
+	}
+
+	args->response_size = sizeof(*r);
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_GET_SIMPLE_VERSION, host_command_get_simple_version, EC_VER_MASK(0));
+
+static enum ec_status get_active_charge_pd_chip(struct host_cmd_handler_args *args)
+{
+	struct ec_response_get_active_charge_pd_chip *r = args->response;
+
+	r->pd_chip = active_charge_pd_chip();
+	args->response_size = sizeof(*r);
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_GET_ACTIVE_CHARGE_PD_CHIP, get_active_charge_pd_chip, EC_VER_MASK(0));
+
+#ifdef CONFIG_BOARD_LOTUS
+static enum ec_status host_command_uefi_app_mode(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_uefi_app_mode *p = args->params;
+	int enable = 1;
+
+	if (p->flags)
+		uefi_app_mode_setting(enable);
+	else
+		uefi_app_mode_setting(!enable);
+
+	return EC_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_UEFI_APP_MODE, host_command_uefi_app_mode, EC_VER_MASK(0));
+
+static enum ec_status host_command_uefi_app_btn_status(struct host_cmd_handler_args *args)
+{
+	struct ec_response_uefi_app_btn_status *r = args->response;
+
+	r->status = uefi_app_btn_status();
+
+	args->response_size = sizeof(*r);
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_UEFI_APP_BTN_STATUS, host_command_uefi_app_btn_status, EC_VER_MASK(0));
+
+static enum ec_status hc_fingerprint_control(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_fingerprint_control *p = args->params;
+	int enable = 1;
+
+	if (p->enable)
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_fp_en), enable);
+	else
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_fp_en), !enable);
+
+	return EC_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_FP_CONTROL, hc_fingerprint_control, EC_VER_MASK(0));
+#endif /* CONFIG_BOARD_LOTUS */
+
+static enum ec_status privacy_switches_check(struct host_cmd_handler_args *args)
+{
+	struct ec_response_privacy_switches_check *r = args->response;
+
+	/*
+	 * Camera is low when off, microphone is high when off
+	 * Return 0 when off/close and 1 when high/open
+	 */
+	r->microphone = !gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_mic_sw));
+	r->camera = gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_cam_sw));
+
+	CPRINTS("Microphone switch open: %d", r->microphone);
+	CPRINTS("Camera switch open: %d", r->camera);
+
+	args->response_size = sizeof(*r);
+
+	return EC_RES_SUCCESS;
+
+}
+DECLARE_HOST_COMMAND(EC_CMD_PRIVACY_SWITCHES_CHECK_MODE, privacy_switches_check, EC_VER_MASK(0));
+
+/*******************************************************************************/
+/*                       EC console command for Project                        */
+/*******************************************************************************/
+static int cmd_bbram(int argc, const char **argv)
+{
+	uint8_t bbram;
+	uint8_t ram_addr;
+	char *e;
+
+	if (argc > 1) {
+		ram_addr = strtoi(argv[1], &e, 0);
+		system_get_bbram(ram_addr, &bbram);
+		CPRINTF("BBram%d: %d", ram_addr, bbram);
+	}
+
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(bbram, cmd_bbram,
+			"[bbram address]",
+			"get bbram data with hibdata_index");
+
+static int cmd_memmap(int argc, const char **argv)
+{
+	int data;
+	int offset;
+	char *e;
+
+	if (argc > 3) {
+		offset = strtoi(argv[2], &e, 0);
+		data = strtoi(argv[3], &e, 0);
+		*host_get_memmap(offset) = data;
+		CPRINTS("EC_MEMMAP offset:%d, set data:%d", offset, data);
+	} else {
+		offset = strtoi(argv[2], &e, 0);
+		data = *host_get_memmap(offset);
+		CPRINTS("EC_MEMMAP offset:%d, get data:%d", offset, data);
+	}
+
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(memmap, cmd_memmap,
+			"[memmap get/set offset [value]]",
+			"get/set memmap data");
diff --git a/zephyr/program/framework/src/common_cpu_power.c b/zephyr/program/framework/src/common_cpu_power.c
new file mode 100644
index 0000000000..6522cb21c8
--- /dev/null
+++ b/zephyr/program/framework/src/common_cpu_power.c
@@ -0,0 +1,211 @@
+
+
+
+#include "charge_state.h"
+#include "charger.h"
+#include "charge_manager.h"
+#include "chipset.h"
+#include "common_cpu_power.h"
+#include "customized_shared_memory.h"
+#include "console.h"
+#include "driver/sb_rmi.h"
+#include "extpower.h"
+#include "hooks.h"
+#include "math_util.h"
+#include "util.h"
+
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+
+struct power_limit_details power_limit[FUNCTION_COUNT];
+static int apu_ready;
+int target_func[TYPE_COUNT];
+bool manual_ctl;
+bool safety_pwr_logging;
+int mode_ctl;
+/* disable b[1:1] to disable power table */
+uint8_t func_ctl = 0xff;
+int my_test_current;
+
+static int update_sustained_power_limit(uint32_t mwatt)
+{
+	uint32_t msgIn = 0;
+	uint32_t msgOut;
+
+	msgIn = mwatt;
+
+	return sb_rmi_mailbox_xfer(SB_RMI_WRITE_SUSTAINED_POWER_LIMIT_CMD, msgIn, &msgOut);
+}
+
+static int update_fast_ppt_limit(uint32_t mwatt)
+{
+	uint32_t msgIn = 0;
+	uint32_t msgOut;
+
+	msgIn = mwatt;
+
+	return sb_rmi_mailbox_xfer(SB_RMI_WRITE_FAST_PPT_LIMIT_CMD, msgIn, &msgOut);
+}
+
+static int update_slow_ppt_limit(uint32_t mwatt)
+{
+	uint32_t msgIn = 0;
+	uint32_t msgOut;
+
+	msgIn = mwatt;
+
+	return sb_rmi_mailbox_xfer(SB_RMI_WRITE_SLOW_PPT_LIMIT_CMD, msgIn, &msgOut);
+}
+
+static int update_peak_package_power_limit(uint32_t mwatt)
+{
+	uint32_t msgIn = 0;
+	uint32_t msgOut;
+
+	msgIn = mwatt;
+
+	return sb_rmi_mailbox_xfer(SB_RMI_WRITE_P3T_LIMIT_CMD, msgIn, &msgOut);
+}
+
+void update_apu_ready(int status)
+{
+	apu_ready = status;
+}
+
+int get_apu_ready(void)
+{
+	return apu_ready;
+}
+
+static void clear_apu_ready(void)
+{
+	update_apu_ready(0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, clear_apu_ready, HOOK_PRIO_DEFAULT);
+
+static void warmboot_clear_api_ready(void)
+{
+	if (chipset_in_state(CHIPSET_STATE_ON))
+		clear_apu_ready();
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESET, warmboot_clear_api_ready, HOOK_PRIO_DEFAULT);
+
+int set_pl_limits(uint32_t spl, uint32_t fppt, uint32_t sppt, uint32_t p3t)
+{
+	RETURN_ERROR(update_sustained_power_limit(spl));
+	RETURN_ERROR(update_fast_ppt_limit(fppt));
+	RETURN_ERROR(update_slow_ppt_limit(sppt));
+	RETURN_ERROR(update_peak_package_power_limit(p3t));
+	return EC_SUCCESS;
+}
+
+#ifdef CONFIG_BOARD_LOTUS
+int update_apu_only_sppt_limit(uint32_t mwatt)
+{
+	uint32_t msgIn = 0;
+	uint32_t msgOut;
+
+	msgIn = mwatt;
+
+	return sb_rmi_mailbox_xfer(SB_RMI_WRITE_APU_ONLY_SPPT_CMD, msgIn, &msgOut);
+}
+#endif
+
+void update_soc_power_limit_hook(void)
+{
+	if (!manual_ctl)
+		update_soc_power_limit(false, false);
+}
+DECLARE_HOOK(HOOK_SECOND, update_soc_power_limit_hook, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_AC_CHANGE, update_soc_power_limit_hook, HOOK_PRIO_DEFAULT);
+
+static int cmd_cpupower(int argc, const char **argv)
+{
+	uint32_t spl, fppt, sppt, p3t;
+	char *e;
+
+	CPRINTF("Now SOC Power Limit:\n FUNC = %d, SPL %dmW,\n",
+		target_func[TYPE_SPL], power_limit[target_func[TYPE_SPL]].mwatt[TYPE_SPL]);
+	CPRINTF("FUNC = %d, fPPT %dmW,\n FUNC = %d, sPPT %dmW,\n FUNC = %d, p3T %dmW,\n",
+		target_func[TYPE_SPPT], power_limit[target_func[TYPE_SPPT]].mwatt[TYPE_SPPT],
+		target_func[TYPE_FPPT], power_limit[target_func[TYPE_FPPT]].mwatt[TYPE_FPPT],
+		target_func[TYPE_P3T], power_limit[target_func[TYPE_P3T]].mwatt[TYPE_P3T]);
+
+#ifdef CONFIG_BOARD_LOTUS
+	CPRINTF("FUNC = %d, ao_sppt %dmW\n",
+		target_func[TYPE_APU_ONLY_SPPT],
+		power_limit[target_func[TYPE_APU_ONLY_SPPT]].mwatt[TYPE_APU_ONLY_SPPT]);
+
+	CPRINTF("stt_table = %d\n", (*host_get_memmap(EC_MEMMAP_STT_TABLE_NUMBER)));
+#endif
+
+	if (argc >= 2) {
+		if (!strncmp(argv[1], "auto", 4)) {
+			manual_ctl = false;
+			CPRINTF("Auto Control");
+			update_soc_power_limit(false, false);
+		}
+		if (!strncmp(argv[1], "manual", 6)) {
+			manual_ctl = true;
+			CPRINTF("Manual Control");
+		}
+
+		if (!strncmp(argv[1], "table", 5)) {
+			CPRINTF("Table Power Limit:\n");
+			for (int i = FUNCTION_DEFAULT; i < FUNCTION_COUNT; i++) {
+				CPRINTF("function %d, SPL %dmW, fPPT %dmW, sPPT %dmW, p3T %dmW, ",
+					i, power_limit[i].mwatt[TYPE_SPL],
+					power_limit[i].mwatt[TYPE_FPPT],
+					power_limit[i].mwatt[TYPE_SPPT],
+					power_limit[i].mwatt[TYPE_P3T]);
+#ifdef CONFIG_BOARD_LOTUS
+				CPRINTF("ao_sppt %dmW\n",
+					power_limit[i].mwatt[TYPE_APU_ONLY_SPPT]);
+#endif
+			}
+		}
+
+		if (!strncmp(argv[1], "mode", 4)) {
+			mode_ctl = strtoi(argv[2], &e, 0);
+			CPRINTF("Mode Control");
+		}
+		if (!strncmp(argv[1], "function", 8)) {
+			func_ctl = strtoi(argv[2], &e, 0);
+			CPRINTF("func Control");
+		}
+		if (!strncmp(argv[1], "test_current", 8)) {
+			my_test_current = strtoi(argv[2], &e, 0);
+			CPRINTF("current Control");
+		}
+		if (!strncmp(argv[1], "logging", 8)) {
+			safety_pwr_logging = strtoi(argv[2], &e, 0);
+			CPRINTF("safety logging=%d", safety_pwr_logging);
+		}
+
+	}
+
+	if (argc >= 5) {
+		spl = strtoi(argv[1], &e, 0);
+		if (*e)
+			return EC_ERROR_PARAM1;
+		fppt = strtoi(argv[2], &e, 0);
+		if (*e)
+			return EC_ERROR_PARAM2;
+
+		sppt = strtoi(argv[2], &e, 0);
+		if (*e)
+			return EC_ERROR_PARAM3;
+
+		p3t = strtoi(argv[2], &e, 0);
+		if (*e)
+			return EC_ERROR_PARAM4;
+
+		set_pl_limits(spl, fppt, sppt, p3t);
+	}
+	return EC_SUCCESS;
+
+}
+DECLARE_CONSOLE_COMMAND(cpupower, cmd_cpupower,
+			"cpupower spl fppt sppt p3t (unit mW)",
+			"Set/Get the cpupower limit");
diff --git a/zephyr/program/framework/src/cypress_pd_common.c b/zephyr/program/framework/src/cypress_pd_common.c
new file mode 100644
index 0000000000..ef17edc257
--- /dev/null
+++ b/zephyr/program/framework/src/cypress_pd_common.c
@@ -0,0 +1,2562 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <atomic.h>
+#include <zephyr/init.h>
+#include "gpio/gpio_int.h"
+
+#include "battery.h"
+#include "board_function.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "console.h"
+#include "cypress_pd_common.h"
+#include "common_cpu_power.h"
+#include "driver/charger/isl9241.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "power.h"
+#include "task.h"
+#include "ucsi.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usb_emsg.h"
+#include "usb_tc_sm.h"
+#include "util.h"
+#include "throttle_ap.h"
+#include "zephyr_console_shim.h"
+
+#ifdef CONFIG_BOARD_LOTUS
+#include "gpu.h"
+#include "cpu_power.h"
+#include "board_charger.h"
+#endif
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+
+#define PRODUCT_ID	0x0001
+#define VENDOR_ID	0x32ac
+
+/*
+ * Unimplemented functions:
+ * 1. Control port current 3A/1.5A for GRL test.
+ * 2. Control port VBUS enable/disable.
+ * 3. Update system power state to PD chip. (Avoid PD chip does the error recovery)
+ * 4. Control PD chip compliance mode
+ * 5. Flash PD flow
+ * 6. Extended message handler
+ * 7. UCSI handler
+ */
+
+static struct pd_chip_config_t pd_chip_config[] = {
+	[PD_CHIP_0] = {
+		.i2c_port = I2C_PORT_PD_MCU0,
+		.addr_flags = CCG_I2C_CHIP0 | I2C_FLAG_ADDR16_LITTLE_ENDIAN,
+		.state = CCG_STATE_POWER_ON,
+		.gpio = GPIO_EC_PD_INTA_L,
+	},
+	[PD_CHIP_1] = {
+		.i2c_port = I2C_PORT_PD_MCU1,
+		.addr_flags = CCG_I2C_CHIP1 | I2C_FLAG_ADDR16_LITTLE_ENDIAN,
+		.state = CCG_STATE_POWER_ON,
+		.gpio = GPIO_EC_PD_INTB_L,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pd_chip_config) == PD_CHIP_COUNT);
+
+static struct pd_port_current_state_t pd_port_states[] = {
+	[PD_PORT_0] = {
+
+	},
+	[PD_PORT_1] = {
+
+	},
+	[PD_PORT_2] = {
+
+	},
+	[PD_PORT_3] = {
+
+	}
+};
+
+struct extended_msg rx_emsg[CONFIG_USB_PD_PORT_MAX_COUNT];
+struct extended_msg tx_emsg[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+static int prev_charge_port = -1;
+static uint8_t pd_c_fet_active_port;
+static bool verbose_msg_logging;
+static bool firmware_update;
+static uint8_t pd_epr_in_progress;
+
+/*****************************************************************************/
+/* Internal functions */
+
+static void cypd_update_port_state(int controller, int port);
+static void cypd_pdo_reset_deferred(void);
+static void cypd_set_prepare_pdo(int controller, int port);
+
+int cypd_write_reg_block(int controller, int reg, void *data, int len)
+{
+	int rv;
+	uint16_t i2c_port = pd_chip_config[controller].i2c_port;
+	uint16_t addr_flags = pd_chip_config[controller].addr_flags;
+
+	rv = i2c_write_offset16_block(i2c_port, addr_flags, reg, data, len);
+	if (rv != EC_SUCCESS)
+		CPRINTS("%s failed: ctrl=0x%x, reg=0x%02x", __func__, controller, reg);
+	return rv;
+}
+
+static int cypd_write_reg16(int controller, int reg, int data)
+{
+	int rv;
+	uint16_t i2c_port = pd_chip_config[controller].i2c_port;
+	uint16_t addr_flags = pd_chip_config[controller].addr_flags;
+
+	rv = i2c_write_offset16(i2c_port, addr_flags, reg, data, 2);
+	if (rv != EC_SUCCESS)
+		CPRINTS("%s failed: ctrl=0x%x, reg=0x%02x", __func__, controller, reg);
+	return rv;
+}
+
+int cypd_write_reg8(int controller, int reg, int data)
+{
+	int rv;
+	uint16_t i2c_port = pd_chip_config[controller].i2c_port;
+	uint16_t addr_flags = pd_chip_config[controller].addr_flags;
+
+	rv = i2c_write_offset16(i2c_port, addr_flags, reg, data, 1);
+	if (rv != EC_SUCCESS)
+		CPRINTS("%s failed: ctrl=0x%x, reg=0x%02x", __func__, controller, reg);
+	return rv;
+}
+
+int cypd_read_reg_block(int controller, int reg, void *data, int len)
+{
+	int rv;
+	uint16_t i2c_port = pd_chip_config[controller].i2c_port;
+	uint16_t addr_flags = pd_chip_config[controller].addr_flags;
+
+	rv = i2c_read_offset16_block(i2c_port, addr_flags, reg, data, len);
+	if (rv != EC_SUCCESS)
+		CPRINTS("%s failed: ctrl=0x%x, reg=0x%02x", __func__, controller, reg);
+	return rv;
+}
+
+static int cypd_read_reg16(int controller, int reg, int *data)
+{
+	int rv;
+	uint16_t i2c_port = pd_chip_config[controller].i2c_port;
+	uint16_t addr_flags = pd_chip_config[controller].addr_flags;
+
+	rv = i2c_read_offset16(i2c_port, addr_flags, reg, data, 2);
+	if (rv != EC_SUCCESS)
+		CPRINTS("%s failed: ctrl=0x%x, reg=0x%02x", __func__, controller, reg);
+	return rv;
+}
+
+static int cypd_read_reg8(int controller, int reg, int *data)
+{
+	int rv;
+	uint16_t i2c_port = pd_chip_config[controller].i2c_port;
+	uint16_t addr_flags = pd_chip_config[controller].addr_flags;
+
+	rv = i2c_read_offset16(i2c_port, addr_flags, reg, data, 1);
+	if (rv != EC_SUCCESS)
+		CPRINTS("%s failed: ctrl=0x%x, reg=0x%02x", __func__, controller, reg);
+	return rv;
+}
+
+static int cypd_reset(int controller)
+{
+	/*
+	 * Device Reset: This command is used to request the CCG device to perform a soft reset
+	 * and start at the boot-loader stage again
+	 * Note: need barrel AC or battery
+	 */
+	return cypd_write_reg16(controller, CCG_RESET_REG, CCG_RESET_CMD);
+}
+
+int cypd_get_int(int controller, int *intreg)
+{
+	int rv;
+
+	rv = cypd_read_reg8(controller, CCG_INTR_REG, intreg);
+	if (rv != EC_SUCCESS)
+		CPRINTS("%s failed: ctrl=0x%x, rv=0x%02x", __func__, controller, rv);
+	return rv;
+}
+
+int cypd_clear_int(int controller, int mask)
+{
+	int rv;
+
+	rv = cypd_write_reg8(controller, CCG_INTR_REG, mask);
+	if (rv != EC_SUCCESS)
+		CPRINTS("%s failed: ctrl=0x%x, mask=0x%02x", __func__, controller, mask);
+	return rv;
+}
+
+int cypd_wait_for_ack(int controller, int timeout_ms)
+{
+	const struct gpio_dt_spec *intr = gpio_get_dt_spec(pd_chip_config[controller].gpio);
+	timestamp_t start = get_time();
+
+	/* wait for interrupt ack to be asserted */
+	do {
+		if (gpio_pin_get_dt(intr) == 0)
+			break;
+		usleep(100);
+	} while (time_since32(start) < (timeout_ms * MSEC));
+
+	/* make sure response is ok */
+	if (gpio_pin_get_dt(intr) != 0) {
+		CPRINTS("%s timeout on interrupt", __func__);
+		return EC_ERROR_INVAL;
+	}
+	return EC_SUCCESS;
+}
+
+static int cypd_write_reg8_wait_ack(int controller, int reg, int data)
+{
+	int rv = EC_SUCCESS;
+	int intr_status;
+	int event;
+	int cmd_port = -1;
+	int ack_mask = 0;
+	int expected_ack_mask = 0;
+	const struct gpio_dt_spec *intr = gpio_get_dt_spec(pd_chip_config[controller].gpio);
+
+	if (reg < 0x1000) {
+		expected_ack_mask = CCG_DEV_INTR;
+		cmd_port = -1;
+	} else if (reg < 0x2000) {
+		expected_ack_mask = CCG_PORT0_INTR;
+		cmd_port = 0;
+	} else {
+		expected_ack_mask = CCG_PORT1_INTR;
+		cmd_port = 1;
+	}
+
+	if (gpio_pin_get_dt(intr) == 0) {
+		/* we may have a pending interrupt */
+		rv = cypd_get_int(controller, &intr_status);
+		CPRINTS("%s pre 0x%x ", __func__, intr_status);
+		if (intr_status & CCG_DEV_INTR) {
+			rv = cypd_read_reg16(controller, CCG_RESPONSE_REG, &event);
+			if (event < 0x80) {
+				cypd_clear_int(controller, CCG_DEV_INTR);
+			}
+			usleep(50);
+		}
+	}
+
+
+	rv = cypd_write_reg8(controller, reg, data);
+	if (rv != EC_SUCCESS)
+		CPRINTS("Write Reg8 0x%x fail!", reg);
+
+	if (cypd_wait_for_ack(controller, 100) != EC_SUCCESS) {
+		CPRINTS("%s timeout on interrupt", __func__);
+		return EC_ERROR_INVAL;
+	}
+	rv = cypd_get_int(controller, &intr_status);
+	if (rv != EC_SUCCESS)
+		CPRINTS("Get INT Fail");
+
+	if (intr_status & CCG_DEV_INTR && cmd_port == -1) {
+		rv = cypd_read_reg16(controller, CCG_RESPONSE_REG, &event);
+		if (rv != EC_SUCCESS)
+			CPRINTS("fail to read DEV response");
+		ack_mask = CCG_DEV_INTR;
+	} else if (intr_status & CCG_PORT0_INTR && cmd_port == 0) {
+		rv = cypd_read_reg16(controller, CCG_PORT_PD_RESPONSE_REG(0), &event);
+		if (rv != EC_SUCCESS)
+			CPRINTS("fail to read P0 response");
+		ack_mask = CCG_PORT0_INTR;
+	} else if (intr_status & CCG_PORT1_INTR && cmd_port == 1) {
+		rv = cypd_read_reg16(controller, CCG_PORT_PD_RESPONSE_REG(1), &event);
+		if (rv != EC_SUCCESS)
+			CPRINTS("fail to read P1 response");
+		ack_mask = CCG_PORT1_INTR;
+	} else {
+		CPRINTS("%s C:%d Unexpected response 0x%x to reg 0x%x",
+			__func__, controller, intr_status, reg);
+		rv = cypd_read_reg16(controller, CCG_RESPONSE_REG, &event);
+		CPRINTS("Dev 0x%x", event);
+		rv = cypd_read_reg16(controller, CCG_PORT_PD_RESPONSE_REG(0), &event);
+		CPRINTS("P0 0x%x", event);
+		rv = cypd_read_reg16(controller, CCG_PORT_PD_RESPONSE_REG(1), &event);
+		CPRINTS("P1 0x%x", event);
+	}
+
+	/* only clear response code let main task handle event code */
+	if (event < 0x80) {
+		cypd_clear_int(controller, ack_mask);
+		if (event != CCG_RESPONSE_SUCCESS) {
+			CPRINTS("%s C:%d 0x%x response 0x%x",
+				__func__, controller, reg, event);
+		}
+		rv = (event == CCG_RESPONSE_SUCCESS) ? EC_SUCCESS : EC_ERROR_INVAL;
+	}
+
+	usleep(50);
+	return rv;
+}
+
+void cypd_print_buff(const char *msg, void *buff, int len)
+{
+	int i;
+	uint8_t *data = (uint8_t *)buff;
+
+	CPRINTF("%s 0x", msg);
+	for (i = len-1; i >= 0; i--) {
+		CPRINTF("%02x", data[i]);
+	}
+	CPRINTF("\n");
+}
+
+#ifdef CONFIG_BOARD_LOTUS
+static void update_external_cc_mux(int port, int cc)
+{
+	if (port == 1) {
+		switch(cc) {
+			case POLARITY_CC1:
+				gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_usb3_ec_p2_cc1), 1);
+				gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_usb3_ec_p2_cc2), 0);
+				break;
+
+			case POLARITY_CC2:
+				gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_usb3_ec_p2_cc1), 0);
+				gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_usb3_ec_p2_cc2), 1);
+				break;
+
+			default:
+				gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_usb3_ec_p2_cc1), 0);
+				gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_usb3_ec_p2_cc2), 0);
+		}
+	}
+}
+
+#define EXIT_EPR BIT(4)
+#define ENTER_EPR BIT(5)
+#define EPR_PROCESS_MASK (EXIT_EPR + ENTER_EPR)
+
+static void epr_flow_pending_deferred(void)
+{
+	int port_idx;
+	/**
+	 * Sometimes, EC does not receive the EPR event/NOT support event from PD chip.
+	 * Retry the last action.
+	 */
+	for (port_idx = 0; port_idx < PD_PORT_COUNT; port_idx++) {
+		if (pd_epr_in_progress & BIT(port_idx)) {
+			if (pd_port_states[port_idx].epr_retry_count > 4) {
+				/* restore the input current limit if we retry 4 times */
+				pd_port_states[port_idx].epr_retry_count = 0;
+				pd_port_states[port_idx].epr_support = 0;
+				pd_epr_in_progress &= EPR_PROCESS_MASK;
+				if (prev_charge_port != -1)
+					cypd_update_port_state((prev_charge_port & 0x02) >> 1,
+						prev_charge_port & BIT(0));
+			}
+			/**
+			 * There is a low risk situation.
+			 * If both the EXIT EPR and ENTER EPR flags are set simultaneously,
+			 * it will cause epr_retry_count to be incremented twice.
+			 */
+			if (pd_epr_in_progress & EXIT_EPR) {
+				CPRINTS("C%d exit EPR stuck, retry!", port_idx);
+				exit_epr_mode();
+				pd_port_states[port_idx].epr_retry_count++;
+			}
+
+			if (pd_epr_in_progress & ENTER_EPR) {
+				CPRINTS("C%d enter EPR stuck, retry!", port_idx);
+				enter_epr_mode();
+				pd_port_states[port_idx].epr_retry_count++;
+			}
+
+		} else
+			pd_port_states[port_idx].epr_retry_count = 0;
+	}
+}
+DECLARE_DEFERRED(epr_flow_pending_deferred);
+
+void enter_epr_mode(void)
+{
+	int port_idx;
+
+	/**
+	 * Only enter EPR mode when the system in S0 state.
+	 * 1. Resume from S0i3 mode
+	 * 2. Power up from S5/G3 state (after error recovery, will enter EPR mode automatically)
+	 * 3. battery in normal mode
+	 */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF) ||
+		battery_is_cut_off() || battery_cutoff_in_progress())
+		return;
+
+	/**
+	 * PD negotiation completed and in Sink Role,
+	 * execute the CCG command to enter the EPR mode
+	 */
+	for (port_idx = 0; port_idx < PD_PORT_COUNT; port_idx++) {
+		if ((pd_port_states[port_idx].pd_state) &&
+			(pd_port_states[port_idx].power_role == PD_ROLE_SINK) &&
+			(pd_port_states[port_idx].epr_active == 0) &&
+			(pd_port_states[port_idx].epr_support == 1)) {
+
+			/* BIT(4): epr in progress, BIT(1) - BIT(3) which port */
+			pd_epr_in_progress |= (BIT(port_idx) + ENTER_EPR);
+
+			/* avoid the pmf is higher when the system resume from S0ix */
+			update_pmf_events(BIT(PD_PROGRESS_ENTER_EPR_MODE),
+				!!(pd_epr_in_progress & ~EPR_PROCESS_MASK));
+
+			if (battery_get_disconnect_state() == BATTERY_NOT_DISCONNECTED) {
+				/* Enable learn mode to discharge on AC */
+				board_discharge_on_ac(1);
+
+				/* Set input current to 0mA */
+				charger_set_input_current_limit(0, 0);
+			}
+
+			cypd_write_reg8((port_idx & 0x2) >> 1,
+					CCG_PD_CONTROL_REG(port_idx & 0x1),
+					CCG_PD_CMD_INITIATE_EPR_ENTRY);
+
+			hook_call_deferred(&epr_flow_pending_deferred_data, 200 * MSEC);
+		}
+	}
+}
+DECLARE_DEFERRED(enter_epr_mode);
+
+void enter_epr_mode_without_battery(void)
+{
+	if ((battery_get_disconnect_state() == BATTERY_DISCONNECTED) ||
+	    (battery_is_present() != BP_YES))
+		enter_epr_mode();
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, enter_epr_mode_without_battery, HOOK_PRIO_DEFAULT);
+
+void exit_epr_mode(void)
+{
+	int port_idx;
+
+	for (port_idx = 0; port_idx < PD_PORT_COUNT; port_idx++) {
+		if (pd_port_states[port_idx].epr_active == 1) {
+
+			/* BIT(4): epr in progress, BIT(1) - BIT(3) which port */
+			pd_epr_in_progress |= (BIT(port_idx) + EXIT_EPR);
+
+			/* do not set learn mode when battery is cut off */
+			if (!battery_cutoff_in_progress() && !battery_is_cut_off() &&
+				(battery_get_disconnect_state() == BATTERY_NOT_DISCONNECTED)) {
+				/* Enable learn mode to discharge on AC */
+				board_discharge_on_ac(1);
+
+				/* Set input current to 0mA */
+				charger_set_input_current_limit(0, 0);
+			} else {
+				update_pmf_events(BIT(PD_PROGRESS_EXIT_EPR_MODE),
+						!!(pd_epr_in_progress & ~EPR_PROCESS_MASK));
+			}
+
+			cypd_write_reg8((port_idx & 0x2) >> 1,
+					CCG_PD_CONTROL_REG(port_idx & 0x1),
+					CCG_PD_CMD_INITIATE_EPR_EXIT);
+
+			hook_call_deferred(&epr_flow_pending_deferred_data, 1000 * MSEC);
+		}
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, exit_epr_mode, HOOK_PRIO_FIRST);
+#endif
+
+static void pd0_update_state_deferred(void)
+{
+	task_set_event(TASK_ID_CYPD, CCG_EVT_STATE_CTRL_0);
+}
+DECLARE_DEFERRED(pd0_update_state_deferred);
+
+static void pd1_update_state_deferred(void)
+{
+	task_set_event(TASK_ID_CYPD, CCG_EVT_STATE_CTRL_1);
+
+}
+DECLARE_DEFERRED(pd1_update_state_deferred);
+
+static void update_power_state_deferred(void)
+{
+	task_set_event(TASK_ID_CYPD, CCG_EVT_UPDATE_PWRSTAT);
+}
+DECLARE_DEFERRED(update_power_state_deferred);
+
+static void cypd_enable_interrupt(int controller, int enable_ndisable)
+{
+	if (controller) {
+			if (enable_ndisable)
+				gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pd_chip1_interrupt));
+			else
+				gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pd_chip1_interrupt));
+	}else {
+			if (enable_ndisable)
+				gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pd_chip0_interrupt));
+			else
+				gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pd_chip0_interrupt));
+	}
+}
+
+static void cypd_print_version(int controller, const char *vtype, uint8_t *data)
+{
+	/*
+	 * Base version: Cypress release version
+	 * Application version: FAE release version
+	 */
+	CPRINTS("Controller %d  %s version B:%X.%X.%X.%X , AP:%X.%X.%X",
+		controller, vtype,
+		(data[3]>>4) & 0xF, (data[3]) & 0xF, data[2], data[0] + (data[1]<<8),
+		(data[7]>>4) & 0xF, (data[7]) & 0xF, data[6]);
+}
+
+static void cypd_get_version(int controller)
+{
+	int rv;
+	int i;
+	uint8_t data[24];
+	uint16_t i2c_port = pd_chip_config[controller].i2c_port;
+	uint16_t addr_flags = pd_chip_config[controller].addr_flags;
+
+	rv = i2c_read_offset16_block(i2c_port, addr_flags, CCG_READ_ALL_VERSION_REG, data, 24);
+	if (rv != EC_SUCCESS)
+		CPRINTS("READ_ALL_VERSION_REG failed");
+
+	cypd_print_version(controller, "App1", data+8);
+	cypd_print_version(controller, "App2", data+16);
+
+	/* store the FW2 version into pd_chip_info struct */
+	for (i = 0; i < 8; i++)
+		pd_chip_config[controller].version[i] = data[16+i];
+}
+
+static void pdo_init_deferred(void)
+{
+	task_set_event(TASK_ID_CYPD, CCG_EVT_PDO_INIT_0);
+}
+DECLARE_DEFERRED(pdo_init_deferred);
+
+static void cypd_pdo_init(int controller, int port, uint8_t profile)
+{
+	int rv;
+
+	/*
+	 * EC needs to provide the data for all Source PDOs when doing a dynamic update of the PDOs.
+	 * If less than 7 PDOs are required, the remaining PDO values should be set to 0.
+	 */
+	uint8_t pdos_reg[32] = {
+			0x50, 0x43, 0x52, 0x53,	/* “SRCP”		*/
+			0x96, 0x90, 0x01, 0x27,	/* PDO0 - 1.5A	*/
+			0x2c, 0x91, 0x01, 0x27,	/* PDO1 - 3A	*/
+			0x00, 0x00, 0x00, 0x00,	/* PDO2			*/
+			0x00, 0x00, 0x00, 0x00,	/* PDO3			*/
+			0x00, 0x00, 0x00, 0x00,	/* PDO4			*/
+			0x00, 0x00, 0x00, 0x00,	/* PDO5			*/
+			0x00, 0x00, 0x00, 0x00	/* PDO6			*/
+		};
+
+	rv = cypd_write_reg_block(controller, CCG_WRITE_DATA_MEMORY_REG(port, 0),
+		pdos_reg, sizeof(pdos_reg));
+	if (rv != EC_SUCCESS)
+		CPRINTS("SET CCG_MEMORY failed");
+
+	rv = cypd_write_reg8_wait_ack(controller, CCG_SELECT_SOURCE_PDO_REG(port), profile);
+	if (rv != EC_SUCCESS)
+		CPRINTS("SET CCG_SELECT_REG failed");
+
+	memset(pdos_reg, 0, sizeof(pdos_reg));
+
+	/* Clear Signature “SRCP” for PDO update finish */
+	rv = cypd_write_reg_block(controller, CCG_WRITE_DATA_MEMORY_REG(port, 0),
+		pdos_reg, sizeof(pdos_reg));
+	if (rv != EC_SUCCESS)
+		CPRINTS("CLEAR CCG_MEMORY failed");
+}
+
+static int cypd_select_rp(int port, uint8_t profile)
+{
+	int rv;
+	CPRINTF("P:%d SET TYPEC RP=%d", port, profile);
+
+	rv = cypd_write_reg8_wait_ack(PORT_TO_CONTROLLER(port),
+			CCG_PD_CONTROL_REG(PORT_TO_CONTROLLER_PORT(port)),
+			profile);
+	if (rv != EC_SUCCESS)
+		CPRINTS("SET TYPEC RP failed");
+
+	return rv;
+}
+
+static int cypd_select_pdo(int controller, int port, uint8_t profile)
+{
+	int rv;
+
+	rv = cypd_write_reg8_wait_ack(controller, CCG_SELECT_SOURCE_PDO_REG(port), profile);
+	if (rv != EC_SUCCESS)
+		CPRINTS("SET CCG_SELECT_REG failed");
+
+	return rv;
+}
+
+static int pd_3a_flag;
+static int pd_3a_set;
+static int pd_3a_controller;
+static int pd_3a_port;
+static int pd_ports_1_5A_flag[PD_PORT_COUNT];
+
+int cypd_port_3a_status(int controller, int port)
+{
+	int port_idx = (controller << 1) + port;
+
+	if (pd_3a_flag &&
+		controller == pd_3a_controller &&
+		port_idx == pd_3a_port)
+		return true;
+	return false;
+}
+
+int cypd_port_3a_set(int controller, int port)
+{
+	int port_idx = (controller << 1) + port;
+
+	if (pd_3a_set)
+		return false;
+
+	pd_3a_set = 1;
+	pd_3a_flag = 1;
+	pd_3a_controller = controller;
+	pd_3a_port = port_idx;
+
+	return true;
+}
+
+void cypd_port_1_5a_set(int controller, int port)
+{
+	int port_idx = (controller << 1) + port;
+	pd_ports_1_5A_flag[port_idx] = 1;
+}
+
+int cypd_port_force_3A(int controller, int port)
+{
+	int port_idx = (controller << 1) + port;
+	int port_1_5A_idx = 0;
+	int i;
+	for (i = 0; i < PD_PORT_COUNT; i++) {
+		port_1_5A_idx += pd_ports_1_5A_flag[i];
+	}
+
+	if (port_1_5A_idx >= 3) {
+		if (!pd_ports_1_5A_flag[port_idx])
+			return true;
+	}
+	return false;
+}
+
+void cypd_release_port(int controller, int port)
+{
+	int port_idx = (controller << 1) + port;
+
+	/* if port disconnect should set RP and PDO to default */
+
+	cypd_select_rp(port_idx, CCG_PD_CMD_SET_TYPEC_1_5A);
+	cypd_select_pdo(controller, port, CCG_PD_CMD_SET_TYPEC_3A);
+
+	if (cypd_port_3a_status(controller, port)) {
+		pd_3a_set = 0;
+		pd_3a_flag = 0;
+	}
+	pd_ports_1_5A_flag[port_idx] = 0;
+}
+
+void cypd_clear_port(int controller, int port)
+{
+	int port_idx = (controller << 1) + port;
+
+	if (cypd_port_3a_status(controller, port)) {
+		pd_3a_set = 0;
+		pd_3a_flag = 0;
+	}
+	pd_ports_1_5A_flag[port_idx] = 0;
+}
+
+/*
+ * function for profile check, if profile not change
+ * don't send again.
+ */
+int cypd_profile_check(int controller, int port)
+{
+	int port_idx = (controller << 1) + port;
+
+	return pd_ports_1_5A_flag[port_idx] != 0;
+}
+
+static void pdo_c0p0_deferred(void)
+{
+	task_set_event(TASK_ID_CYPD, CCG_EVT_PDO_C0P0);
+}
+DECLARE_DEFERRED(pdo_c0p0_deferred);
+
+static void pdo_c0p1_deferred(void)
+{
+	task_set_event(TASK_ID_CYPD, CCG_EVT_PDO_C0P1);
+}
+DECLARE_DEFERRED(pdo_c0p1_deferred);
+
+static void pdo_c1p0_deferred(void)
+{
+	task_set_event(TASK_ID_CYPD, CCG_EVT_PDO_C1P0);
+}
+DECLARE_DEFERRED(pdo_c1p0_deferred);
+
+static void pdo_c1p1_deferred(void)
+{
+	task_set_event(TASK_ID_CYPD, CCG_EVT_PDO_C1P1);
+}
+DECLARE_DEFERRED(pdo_c1p1_deferred);
+
+static void cypd_set_prepare_pdo(int controller, int port)
+{
+	switch (controller) {
+	case 0:
+		if (!port)
+			hook_call_deferred(&pdo_c0p0_deferred_data, 2000 * MSEC);
+		else
+			hook_call_deferred(&pdo_c0p1_deferred_data, 2100 * MSEC);
+		break;
+	case 1:
+		if (!port)
+			hook_call_deferred(&pdo_c1p0_deferred_data, 2000 * MSEC);
+		else
+			hook_call_deferred(&pdo_c1p1_deferred_data, 2100 * MSEC);
+		break;
+	}
+}
+
+static int cypd_modify_profile(int controller, int port, int profile)
+{
+	int rv;
+	int port_idx = (controller << 1) + port;
+
+	if (verbose_msg_logging)
+		CPRINTS("PD Select PDO %s ", profile & 0x02 ? "3A" : "1.5A");
+
+	if (profile == CCG_PD_CMD_SET_TYPEC_3A) {
+		rv = cypd_select_rp(port_idx, profile);
+		if (rv != EC_SUCCESS)
+			return rv;
+	}
+
+	rv = cypd_select_pdo(controller, port, profile);
+	if (rv != EC_SUCCESS) {
+		CPRINTS("PD Select PDO %s failed", profile & 0x02 ? "3A" : "1.5A");
+		cypd_clear_port(controller, port);
+		cypd_set_prepare_pdo(controller, port);
+		return rv;
+	}
+
+	/* Lock 1.5A port  */
+	if (profile == CCG_PD_CMD_SET_TYPEC_1_5A)
+		cypd_port_1_5a_set(controller, port);
+
+	return EC_SUCCESS;
+}
+
+int cypd_modify_safety_power_1_5A(int controller, int port)
+{
+	int rv;
+	int port_idx = (controller << 1) + port;
+
+	if (verbose_msg_logging)
+		CPRINTS("Safety level trigger force PDO 1.5A");
+
+	rv = cypd_select_rp(port_idx, CCG_PD_CMD_SET_TYPEC_1_5A);
+	rv = cypd_select_pdo(controller, port, CCG_PD_CMD_SET_TYPEC_1_5A);
+	if (rv != EC_SUCCESS) {
+		cypd_clear_port(controller, port);
+		cypd_set_prepare_pdo(controller, port);
+		return rv;
+	}
+
+	pd_3a_set = 0;
+	pd_3a_flag = 0;
+	pd_ports_1_5A_flag[port_idx] = 1;
+
+	return EC_SUCCESS;
+}
+
+void cypd_set_typec_profile(int controller, int port)
+{
+	int rv;
+	uint8_t pd_status_reg[4];
+	uint8_t rdo_reg[4];
+
+	int rdo_max_current = 0;
+	int port_idx = (controller << 1) + port;
+
+	rv = cypd_read_reg_block(controller, CCG_PD_STATUS_REG(port), pd_status_reg, 4);
+	if (rv != EC_SUCCESS)
+		CPRINTS("CYP5525_PD_STATUS_REG failed");
+
+	/*do we have a valid PD contract*/
+	pd_port_states[port_idx].pd_state = pd_status_reg[1] & BIT(2) ? 1 : 0;
+	pd_port_states[port_idx].power_role =
+			pd_status_reg[1] & BIT(0) ? PD_ROLE_SOURCE : PD_ROLE_SINK;
+
+	if (pd_port_states[port_idx].power_role == PD_ROLE_SOURCE) {
+		if (pd_port_states[port_idx].pd_state) {
+
+#ifdef CONFIG_BOARD_LOTUS
+			/*
+			 * If safety level(LEVEL_TYPEC_1_5A) is triggered,
+			 * force 1.5A pdo to device.
+			 */
+			if (safety_force_typec_1_5A()) {
+				rv = cypd_modify_profile(controller, port,
+							CCG_PD_CMD_SET_TYPEC_1_5A);
+				return;
+			}
+#endif
+			/*
+			 * first time set 3A PDO to device
+			 * when device request RDO <= 1.5A
+			 * resend 1.5A pdo to device
+			 */
+
+			cypd_read_reg_block(controller, CCG_CURRENT_RDO_REG(port), rdo_reg, 4);
+			rdo_max_current = (((rdo_reg[1]>>2) + (rdo_reg[2]<<6)) & 0x3FF)*10;
+
+			if ((cypd_port_force_3A(controller, port) && !pd_3a_flag) ||
+				cypd_port_3a_status(controller, port)) {
+				if (!cypd_port_3a_set(controller, port))
+					return;
+				rv = cypd_modify_profile(controller, port,
+						CCG_PD_CMD_SET_TYPEC_3A);
+			} else if (rdo_max_current <= 1500) {
+				if (cypd_profile_check(controller, port))
+					return;
+				rv = cypd_modify_profile(controller, port,
+						CCG_PD_CMD_SET_TYPEC_1_5A);
+			} else if (!pd_3a_flag && cypd_port_3a_set(controller, port))
+				rv = cypd_modify_profile(controller, port,
+						CCG_PD_CMD_SET_TYPEC_3A);
+			else if (!cypd_profile_check(controller, port))
+				rv = cypd_modify_profile(controller, port,
+						CCG_PD_CMD_SET_TYPEC_1_5A);
+
+		} else {
+			cypd_write_reg8(controller, CCG_PD_CONTROL_REG(port),
+				CCG_PD_CMD_SET_TYPEC_1_5A);
+		}
+	}
+
+	cypd_update_port_state(controller, port);
+}
+
+void cypd_port_current_setting(void)
+{
+	for (int i = 0; i < PD_CHIP_COUNT; i++) {
+		cypd_set_prepare_pdo(i, 0);
+		cypd_set_prepare_pdo(i, 1);
+	}
+}
+
+static void cypd_pdo_reset_deferred(void)
+{
+	task_set_event(TASK_ID_CYPD, CCG_EVT_PDO_RESET);
+}
+DECLARE_DEFERRED(cypd_pdo_reset_deferred);
+
+static void cypd_ppm_port_clear(void)
+{
+	memset(pd_ports_1_5A_flag, 0, sizeof(pd_ports_1_5A_flag));
+	pd_3a_set = 0;
+
+	/* need init PDO again because PD chip will clear PDO data */
+	hook_call_deferred(&pdo_init_deferred_data, 1);
+}
+
+/*
+ * send a message using DM_CONTROL to port partner
+ * pd_header is using chromium PD header with upper bits defining SOP type
+ * pd30 is set for batttery status messages
+ * response timer is set to false for messages that are a response
+ * data includes
+ * pd header bytes 0 -1
+ * message, or extmessage header - then data
+ * length should include length of all data after pd header
+ */
+void cypd_send_msg(int controller, int port, uint32_t pd_header, uint16_t ext_hdr,
+	bool pd30, bool response_timer, void *data, uint32_t data_size)
+{
+	uint16_t header[2] = {0};
+	uint16_t dm_control_data;
+
+	/**
+	 * The extended message data should be written to the write data memory
+	 * in the following format:
+	 * Byte 0 : Message type [4:0]
+	 * Byte 1 : Reserved
+	 * Byte 3 - 2 : Extended message header
+	 * Byte N - 4 : data
+	 */
+
+	header[0] = pd_header;
+	header[1] = ext_hdr;
+
+	cypd_write_reg_block(controller, CCG_WRITE_DATA_MEMORY_REG(port, 0),
+		(void *)header, 4);
+
+	cypd_write_reg_block(controller, CCG_WRITE_DATA_MEMORY_REG(port, 4),
+		data, data_size);
+
+	/**
+	 * The DM_CONTROL register should then be written to in the following format:
+	 * Byte 0
+	 *	- BIT 1 - 0 : Packet type should be set to SOP(0), SOP'(1), or SOP''(2).
+	 *	- BIT 2 : PD 3.0 Message bit (Bit 2) should be clear.
+	 *	- BIT 3 : Extended message bit (Bit 3) should be set.
+	 *	- BIT 4 : Respoonse timer disable bit should be set as desired.
+	 * Byte 1 : The data length specified here will be the actual length of data
+	 *			written into the write data memory, inclusive of the 4 byte header
+	 *
+	 * TODO: Need to process chunk extended message [4:32]
+	 */
+	dm_control_data = PD_HEADER_GET_SOP(pd_header);
+	if (ext_hdr)
+		dm_control_data |= CCG_DM_CTRL_EXTENDED_DATA_REQUEST;
+	if (pd30)
+		dm_control_data |= CCG_DM_CTRL_PD3_DATA_REQUEST;
+	if (!response_timer)
+		dm_control_data |= CCG_DM_CTRL_SENDER_RESPONSE_TIMER_DISABLE;
+	dm_control_data += ((data_size + 4) << 8);
+
+	cypd_write_reg16(controller, CCG_DM_CONTROL_REG(port), dm_control_data);
+}
+
+void cypd_response_get_battery_capability(int controller, int port,
+	uint32_t pd_header, enum tcpci_msg_type sop_type)
+{
+	int port_idx = (controller << 1) + port;
+	int ext_header = 0;
+	bool chunked = PD_EXT_HEADER_CHUNKED(rx_emsg[port_idx].header);
+	uint16_t msg[5] = {0, 0, 0, 0, 0};
+	uint32_t header = PD_EXT_BATTERY_CAP + PD_HEADER_SOP(sop_type);
+
+	ext_header = 9;
+	/* Set extended header */
+	if (chunked) {
+		ext_header |= BIT(15);
+	}
+	/* Set VID */
+	msg[0] = VENDOR_ID;
+
+	/* Set PID */
+	msg[1] = PRODUCT_ID;
+
+	if (battery_is_present() == BP_YES) {
+		/*
+		 * We only have one fixed battery,
+		 * so make sure batt cap ref is 0.
+		 */
+		if (rx_emsg[port_idx].buf[0] != 0) {
+			/* Invalid battery reference */
+			msg[4] = 1;
+		} else {
+			uint32_t v;
+			uint32_t c;
+
+			/*
+			 * The Battery Design Capacity field shall return the
+			 * Battery’s design capacity in tenths of Wh. If the
+			 * Battery is Hot Swappable and is not present, the
+			 * Battery Design Capacity field shall be set to 0. If
+			 * the Battery is unable to report its Design Capacity,
+			 * it shall return 0xFFFF
+			 */
+			msg[2] = 0xffff;
+
+			/*
+			 * The Battery Last Full Charge Capacity field shall
+			 * return the Battery’s last full charge capacity in
+			 * tenths of Wh. If the Battery is Hot Swappable and
+			 * is not present, the Battery Last Full Charge Capacity
+			 * field shall be set to 0. If the Battery is unable to
+			 * report its Design Capacity, the Battery Last Full
+			 * Charge Capacity field shall be set to 0xFFFF.
+			 */
+			msg[3] = 0xffff;
+
+			if (battery_design_voltage(&v) == 0) {
+				if (battery_design_capacity(&c) == 0) {
+					/*
+					 * Wh = (c * v) / 1000000
+					 * 10th of a Wh = Wh * 10
+					 */
+					msg[2] = DIV_ROUND_NEAREST((c * v),
+								100000);
+				}
+
+				if (battery_full_charge_capacity(&c) == 0) {
+					/*
+					 * Wh = (c * v) / 1000000
+					 * 10th of a Wh = Wh * 10
+					 */
+					msg[3] = DIV_ROUND_NEAREST((c * v),
+								100000);
+				}
+			}
+		}
+	}
+	cypd_send_msg(controller, port, header, ext_header,  false, false,
+		(void *)msg, ARRAY_SIZE(msg)*sizeof(uint16_t));
+
+}
+
+int cypd_response_get_battery_status(int controller, int port,
+	uint32_t pd_header, enum tcpci_msg_type sop_type)
+{
+	int rv = 0;
+	uint32_t msg = 0;
+	uint32_t header = PD_DATA_BATTERY_STATUS + PD_HEADER_SOP(sop_type);
+	int port_idx = (controller << 1) + port;
+
+	if (battery_is_present() == BP_YES) {
+		/*
+		 * We only have one fixed battery,
+		 * so make sure batt cap ref is 0.
+		 */
+		if (rx_emsg[port_idx].buf[0] != 0) {
+			/* Invalid battery reference */
+			msg |= BSDO_INVALID;
+		} else {
+			uint32_t v;
+			uint32_t c;
+
+			if (battery_design_voltage(&v) != 0 ||
+					battery_remaining_capacity(&c) != 0) {
+				msg |= BSDO_CAP(BSDO_CAP_UNKNOWN);
+			} else {
+				/*
+				 * Wh = (c * v) / 1000000
+				 * 10th of a Wh = Wh * 10
+				 */
+				msg |= BSDO_CAP(DIV_ROUND_NEAREST((c * v),
+								100000));
+			}
+
+			/* Battery is present */
+			msg |= BSDO_PRESENT;
+
+			/*
+			 * For drivers that are not smart battery compliant,
+			 * battery_status() returns EC_ERROR_UNIMPLEMENTED and
+			 * the battery is assumed to be idle.
+			 */
+			if (battery_status(&c) != 0) {
+				msg |= BSDO_IDLE; /* assume idle */
+			} else {
+				if (c & STATUS_FULLY_CHARGED)
+					/* Fully charged */
+					msg |= BSDO_IDLE;
+				else if (c & STATUS_DISCHARGING)
+					/* Discharging */
+					msg |= BSDO_DISCHARGING;
+				/* else battery is charging.*/
+			}
+		}
+	} else {
+		msg = BSDO_CAP(BSDO_CAP_UNKNOWN);
+	}
+
+	cypd_send_msg(controller, port, header, 0,  true, false, &msg, 4);
+
+	return rv;
+}
+
+int cypd_handle_extend_msg(int controller, int port, int len, enum tcpci_msg_type sop_type)
+{
+	/**
+	 * Extended Message Received Events
+	 * Event Code = 0xAC(SOP), 0xB4(SOP'), 0xB5(SOP'')
+	 * Event length = 4 + Extended message length
+	 */
+
+	/*Todo handle full length Extended messages up to 260 bytes*/
+	int type;
+	int rv;
+	int i;
+	int port_idx = (controller << 1) + port;
+	int pd_header;
+
+	if (len > 260) {
+		CPRINTS("ExtMsg Too Long");
+		return EC_ERROR_INVAL;
+	}
+
+	/* Read the extended message packet */
+	rv = cypd_read_reg_block(controller,
+		CCG_READ_DATA_MEMORY_REG(port, 0), (void *)&(rx_emsg[port_idx].len), len);
+		/*
+		 * avoid a memcopy so direct copy into the buffer and then swap header and len
+		 * look at the memory layout for the rx_emsg structure to see why we do this
+		 */
+	rx_emsg[port_idx].header = rx_emsg[port_idx].len >> 16;
+	pd_header = (rx_emsg[port_idx].len & 0xFFFF) + PD_HEADER_SOP(sop_type);
+	rx_emsg[port_idx].len = len-4;
+
+	/* Extended field shall be set to 1*/
+	if (!PD_HEADER_EXT(pd_header))
+		return EC_ERROR_INVAL;
+
+	type = PD_HEADER_TYPE(pd_header);
+
+	switch (type) {
+	case PD_EXT_GET_BATTERY_CAP:
+		cypd_response_get_battery_capability(controller, port, pd_header, sop_type);
+		break;
+	case PD_EXT_GET_BATTERY_STATUS:
+		rv = cypd_response_get_battery_status(controller, port, pd_header, sop_type);
+		break;
+	default:
+		CPRINTF("Port:%d Unknown data type: 0x%02x Hdr:0x%04x ExtHdr:0x%04x Data:0x",
+				port_idx, type, pd_header, rx_emsg[port_idx].header);
+		for (i = 0; i < rx_emsg[port_idx].len; i++) {
+			CPRINTF("%02x", rx_emsg[port_idx].buf[i]);
+		}
+		CPRINTF("\n");
+		rv = EC_ERROR_INVAL;
+		break;
+	}
+
+	return rv;
+}
+
+uint8_t cypd_get_cfet_status(void)
+{
+	return pd_c_fet_active_port;
+}
+
+int cypd_cfet_vbus_control(int port, bool enable, bool ec_control)
+{
+	int rv;
+	int pd_controller = PORT_TO_CONTROLLER(port);
+	int pd_port = PORT_TO_CONTROLLER_PORT(port);
+	int regval = (ec_control ? CCG_EC_VBUS_CTRL_EN : 0) |
+				(enable ? CCG_EC_VBUS_CTRL_ON : 0);
+
+	if (port < 0 || port >= PD_PORT_COUNT) {
+		return EC_ERROR_INVAL;
+	}
+
+	rv = cypd_write_reg8_wait_ack(pd_controller, CCG_PORT_VBUS_FET_CONTROL(pd_port),
+		regval);
+	if (rv != EC_SUCCESS)
+		CPRINTS("%s:%d fail:%d", __func__, port, rv);
+
+	if (enable)
+		pd_c_fet_active_port |= BIT(port);
+	else
+		pd_c_fet_active_port &= ~BIT(port);
+
+	return rv;
+}
+
+static void clear_port_state(int controller, int port)
+{
+	int port_idx = (controller << 1) + port;
+	pd_port_states[port_idx].pd_state = 0; /*do we have a valid PD contract*/
+	pd_port_states[port_idx].power_role = PD_ROLE_SINK;
+	pd_port_states[port_idx].data_role = PD_ROLE_UFP;
+	pd_port_states[port_idx].vconn = PD_ROLE_VCONN_OFF;
+	pd_port_states[port_idx].epr_active = 0;
+	pd_port_states[port_idx].epr_support = 0;
+	pd_port_states[port_idx].epr_retry_count = 0;
+	pd_port_states[port_idx].cc = POLARITY_CC1;
+	pd_port_states[port_idx].c_state = 0;
+	pd_port_states[port_idx].current = 0;
+	pd_port_states[port_idx].voltage = 0;
+}
+static void cypd_update_port_state(int controller, int port)
+{
+	int rv;
+	uint8_t pd_status_reg[4];
+	uint32_t pdo_reg;
+	uint8_t rdo_reg[4];
+	int typec_status_reg;
+	int pd_current = 0;
+	int pd_voltage = 0;
+	int rdo_max_current = 0;
+	int type_c_current = 0;
+	int port_idx = (controller << 1) + port;
+#ifdef CONFIG_BOARD_LOTUS
+	int64_t calculate_ma;
+#endif
+
+	rv = cypd_read_reg_block(controller, CCG_PD_STATUS_REG(port), pd_status_reg, 4);
+	if (rv != EC_SUCCESS)
+		CPRINTS("CCG_PD_STATUS_REG failed");
+	pd_port_states[port_idx].pd_state =
+		pd_status_reg[1] & BIT(2) ? 1 : 0; /*do we have a valid PD contract*/
+	pd_port_states[port_idx].power_role =
+		pd_status_reg[1] & BIT(0) ? PD_ROLE_SOURCE : PD_ROLE_SINK;
+	pd_port_states[port_idx].data_role =
+		pd_status_reg[0] & BIT(6) ? PD_ROLE_DFP : PD_ROLE_UFP;
+	pd_port_states[port_idx].vconn =
+		pd_status_reg[1] & BIT(5) ? PD_ROLE_VCONN_SRC : PD_ROLE_VCONN_OFF;
+	if (pd_port_states[port_idx].epr_active != 0xff)
+		pd_port_states[port_idx].epr_active = pd_status_reg[2] & BIT(7) ? 1 : 0;
+
+	rv = cypd_read_reg8(controller, CCG_TYPE_C_STATUS_REG(port), &typec_status_reg);
+	if (rv != EC_SUCCESS)
+		CPRINTS("CCG_TYPE_C_STATUS_REG failed");
+
+	pd_port_states[port_idx].cc = typec_status_reg & BIT(1) ? POLARITY_CC2 : POLARITY_CC1;
+	pd_port_states[port_idx].c_state = (typec_status_reg >> 2) & 0x7;
+	switch ((typec_status_reg >> 6) & 0x03) {
+	case 0:
+		type_c_current = 900;
+		break;
+	case 1:
+		type_c_current = 1500;
+		break;
+	case 2:
+		type_c_current = 3000;
+		break;
+	}
+#ifdef CONFIG_BOARD_LOTUS
+	update_external_cc_mux(port_idx,pd_port_states[port_idx].c_state == CCG_STATUS_NOTHING ? 0xFF : pd_port_states[port_idx].cc);
+#endif
+
+	rv = cypd_read_reg_block(controller, CCG_CURRENT_PDO_REG(port), &pdo_reg, 4);
+	switch (pdo_reg & PDO_TYPE_MASK) {
+		case PDO_TYPE_FIXED:
+			pd_current = PDO_FIXED_CURRENT(pdo_reg);
+			pd_voltage = PDO_FIXED_VOLTAGE(pdo_reg);
+			break;
+		case PDO_TYPE_BATTERY:
+			pd_current = PDO_BATT_MAX_POWER(pdo_reg)/PDO_BATT_MAX_VOLTAGE(pdo_reg);
+			pd_voltage = PDO_BATT_MIN_VOLTAGE(pdo_reg);
+		break;
+		case PDO_TYPE_VARIABLE:
+			pd_current = PDO_VAR_MAX_CURRENT(pdo_reg);
+			pd_voltage = PDO_VAR_MAX_VOLTAGE(pdo_reg);
+		break;
+		case PDO_TYPE_AUGMENTED:
+			pd_current = PDO_AUG_MAX_CURRENT(pdo_reg);
+			pd_voltage = PDO_AUG_MAX_VOLTAGE(pdo_reg);
+		break;
+	}
+
+	cypd_read_reg_block(controller, CCG_CURRENT_RDO_REG(port), rdo_reg, 4);
+	rdo_max_current = (((rdo_reg[1]>>2) + (rdo_reg[2]<<6)) & 0x3FF)*10;
+
+	/*
+	 * The port can have several states active:
+	 * 1. Type C active (with no PD contract) CC resistor negociation only
+	 * 2. Type C active with PD contract
+	 * 3. Not active
+	 * Each of 1 and 2 can be either source or sink
+	 */
+
+	if (pd_port_states[port_idx].c_state == CCG_STATUS_SOURCE) {
+		typec_set_input_current_limit(port_idx, type_c_current, TYPE_C_VOLTAGE);
+		charge_manager_set_ceil(port_idx, CEIL_REQUESTOR_PD,
+							type_c_current);
+	} else {
+		typec_set_input_current_limit(port_idx, 0, 0);
+		charge_manager_set_ceil(port,
+			CEIL_REQUESTOR_PD,
+			CHARGE_CEIL_NONE);
+	}
+	if (pd_port_states[port_idx].c_state == CCG_STATUS_SINK) {
+		pd_port_states[port_idx].current = type_c_current;
+		pd_port_states[port_idx].voltage = TYPE_C_VOLTAGE;
+	}
+
+	if (pd_port_states[port_idx].c_state == CCG_STATUS_NOTHING) {
+		pd_port_states[port_idx].current = 0;
+		pd_port_states[port_idx].voltage = 0;
+	}
+
+	if (pd_port_states[port_idx].pd_state) {
+		if (pd_port_states[port_idx].power_role == PD_ROLE_SINK) {
+			pd_set_input_current_limit(port_idx, pd_current, pd_voltage);
+			charge_manager_set_ceil(port_idx, CEIL_REQUESTOR_PD, pd_current);
+			pd_port_states[port_idx].current = pd_current;
+			pd_port_states[port_idx].voltage = pd_voltage;
+		} else {
+			pd_set_input_current_limit(port_idx, 0, 0);
+			/*Source*/
+			pd_port_states[port_idx].current = rdo_max_current;
+			pd_port_states[port_idx].voltage = TYPE_C_VOLTAGE;
+
+		}
+	} else {
+		pd_set_input_current_limit(port_idx, 0, 0);
+	}
+
+	if (IS_ENABLED(CONFIG_PLATFORM_EC_CHARGE_MANAGER)) {
+		charge_manager_update_dualrole(port_idx, CAP_DEDICATED);
+	}
+
+#ifdef CONFIG_BOARD_LOTUS
+	if (!!(pd_epr_in_progress & EPR_PROCESS_MASK) &&
+	    !(pd_epr_in_progress & ~EPR_PROCESS_MASK)) {
+
+		/* Handle EPR converstion through the buck switcher */
+		if (pd_voltage > 20000) {
+			/**
+			 * (charge_ma * charge_mv / 20000 ) * 0.9 * 0.94
+			 */
+			calculate_ma =
+				(int64_t)pd_current * (int64_t)pd_voltage * 90 * 95 / 200000000;
+		} else {
+			calculate_ma = (int64_t)pd_current * 88 / 100;
+		}
+
+		board_discharge_on_ac(0);
+		charger_set_input_current_limit(0, (int)calculate_ma);
+		pd_epr_in_progress &= ~EPR_PROCESS_MASK;
+	}
+#endif
+
+	charge_wakeup();
+}
+
+int cypd_set_power_state(int power_state, int controller)
+{
+	int i;
+	int rv = EC_SUCCESS;
+
+	CPRINTS("C%d, %s pwr state %d", controller, __func__, power_state);
+
+	if (controller < 2)
+		rv = cypd_write_reg8_wait_ack(controller, CCG_SYS_PWR_STATE, power_state);
+	else {
+		for (i = 0; i < PD_CHIP_COUNT; i++) {
+
+			rv = cypd_write_reg8_wait_ack(i, CCG_SYS_PWR_STATE, power_state);
+			if (rv != EC_SUCCESS)
+				break;
+		}
+	}
+	return rv;
+}
+
+static void cypd_update_epr_state(int controller, int port, int response_len)
+{
+	int rv;
+	uint8_t data[16];
+	uint16_t i2c_port = pd_chip_config[controller].i2c_port;
+	uint16_t addr_flags = pd_chip_config[controller].addr_flags;
+	int port_idx = (controller << 1) + port;
+
+	rv = i2c_read_offset16_block(i2c_port, addr_flags,
+		CCG_READ_DATA_MEMORY_REG(port, 0), data, MIN(response_len, 16));
+
+	if (rv != EC_SUCCESS)
+		CPRINTS("CCG_READ_DATA_MEMORY_REG failed");
+
+	if ((data[0] & EPR_EVENT_POWER_ROLE_MASK) == EPR_EVENT_POWER_ROLE_SINK) {
+		switch (data[0] & EPR_EVENT_TYPE_MASK) {
+		case EPR_MODE_ENTERED:
+			CPRINTS("Entered EPR");
+			break;
+		case EPR_MODE_EXITED:
+			CPRINTS("Exited EPR");
+			break;
+		case EPR_MODE_ENTER_FAILED:
+		default:
+			/* see epr_event_failure_type*/
+			CPRINTS("EPR failed %d", data[1]);
+			/* EPR fail, do not retry */
+			pd_port_states[port_idx].epr_active = 0xff;
+		}
+	}
+
+	pd_epr_in_progress &= ~BIT((controller << 1) + port);
+}
+
+static int cypd_update_power_status(int controller)
+{
+	int i;
+	int rv = EC_SUCCESS;
+	int power_stat = 0;
+	int pd_controller_is_sink = (prev_charge_port & 0x02) >> 1;
+	bool battery_can_discharge = (battery_is_present() == BP_YES) &
+		battery_get_disconnect_state();
+
+	if (controller < PD_CHIP_COUNT) {
+		if (battery_can_discharge)
+			power_stat |= BIT(3);
+		if ((extpower_is_present() && battery_can_discharge) ||
+			(extpower_is_present() && controller != pd_controller_is_sink && prev_charge_port >=0))
+			power_stat |= BIT(1) + BIT(2);
+
+		CPRINTS("%s:%d=0x%x", __func__,controller, power_stat);
+		rv = cypd_write_reg8_wait_ack(controller, CCG_POWER_STAT, power_stat);
+	} else {
+		for (i = 0; i < PD_CHIP_COUNT; i++) {
+			power_stat = 0;
+			if (battery_can_discharge)
+				power_stat |= BIT(3);
+			if ((extpower_is_present() && battery_can_discharge) ||
+				(extpower_is_present() && i != pd_controller_is_sink && prev_charge_port >=0))
+				power_stat |= BIT(1) + BIT(2);
+			CPRINTS("%s:%d=0x%x", __func__,i, power_stat);
+			rv = cypd_write_reg8_wait_ack(i, CCG_POWER_STAT, power_stat);
+			if (rv != EC_SUCCESS)
+				break;
+		}
+	}
+	return rv;
+}
+
+static void perform_error_recovery(int controller)
+{
+	int i;
+	uint8_t data[2] = {0x00, CCG_PD_USER_CMD_TYPEC_ERR_RECOVERY};
+	uint32_t batt_os_percentage = get_system_percentage();
+
+	if (controller < 2)
+		for (i = 0; i < 2; i++) {
+			if (!((controller*2 + i) == prev_charge_port &&
+				battery_get_disconnect_state() != BATTERY_NOT_DISCONNECTED)) {
+
+				data[0] = PORT_TO_CONTROLLER_PORT(i);
+				cypd_write_reg_block(PORT_TO_CONTROLLER(i),
+									CCG_DPM_CMD_REG,
+									data, 2);
+			}
+		}
+	else {
+		/* Hard reset all ports that are not supplying power in dead battery mode */
+		for (i = 0; i < PD_PORT_COUNT; i++) {
+			if (!(i == prev_charge_port &&
+			    battery_get_disconnect_state() != BATTERY_NOT_DISCONNECTED)) {
+
+				if ((pd_port_states[i].c_state == CCG_STATUS_SOURCE) &&
+				   (batt_os_percentage < 3) && (i == prev_charge_port))
+					continue;
+
+				CPRINTS("Hard reset %d", i);
+				data[0] = PORT_TO_CONTROLLER_PORT(i);
+				cypd_write_reg_block(PORT_TO_CONTROLLER(i),
+									CCG_DPM_CMD_REG,
+									data, 2);
+			}
+		}
+	}
+	return ;
+}
+
+static void port_to_safe_mode(int port)
+{
+	uint8_t data[2] = {0x00, CCG_PD_USER_MUX_CONFIG_SAFE};
+
+	data[0] = PORT_TO_CONTROLLER_PORT(port);
+	cypd_write_reg_block(PORT_TO_CONTROLLER(port), CCG_MUX_CFG_REG, data, 2);
+	cypd_write_reg_block(PORT_TO_CONTROLLER(port), CCG_DEINIT_PORT_REG, data, 1);
+	CPRINTS("P%d: Safe", port);
+
+}
+enum power_state pd_prev_power_state = POWER_G3;
+void update_system_power_state(int controller)
+{
+	enum power_state ps = power_get_state();
+
+	switch (ps) {
+	case POWER_G3:
+	case POWER_S5G3:
+		pd_prev_power_state = POWER_G3;
+		cypd_set_power_state(CCG_POWERSTATE_G3, controller);
+		break;
+	case POWER_S5:
+	case POWER_S3S5:
+	case POWER_S4S5:
+		pd_prev_power_state = POWER_S5;
+		cypd_set_power_state(CCG_POWERSTATE_S5, controller);
+		break;
+	case POWER_S3:
+	case POWER_S4S3:
+	case POWER_S5S3:
+	case POWER_S0S3:
+	case POWER_S0ixS3: /* S0ix -> S3 */
+		cypd_set_power_state(CCG_POWERSTATE_S3, controller);
+		if (pd_prev_power_state < POWER_S3) {
+			perform_error_recovery(controller);
+			pd_prev_power_state = ps;
+		}
+		break;
+	case POWER_S0:
+	case POWER_S3S0:
+	case POWER_S0ixS0: /* S0ix -> S0 */
+		cypd_set_power_state(CCG_POWERSTATE_S0, controller);
+		if (pd_prev_power_state < POWER_S3) {
+			perform_error_recovery(controller);
+			pd_prev_power_state = ps;
+		}
+		break;
+	case POWER_S0ix:
+	case POWER_S3S0ix: /* S3 -> S0ix */
+	case POWER_S0S0ix: /* S0 -> S0ix */
+		cypd_set_power_state(CCG_POWERSTATE_S0ix, controller);
+		break;
+
+	default:
+		break;
+	}
+
+}
+
+void cypd_set_power_active(void)
+{
+	task_set_event(TASK_ID_CYPD, CCG_EVT_S_CHANGE);
+}
+
+
+
+#define CYPD_SETUP_CMDS_LEN 2
+static int cypd_setup(int controller)
+{
+	/*
+	 * 1. CCG notifies EC with "RESET Complete event after Reset/Power up/JUMP_TO_BOOT
+	 * 2. EC Reads DEVICE_MODE register does not in Boot Mode
+	 * 3. CCG will enters 100ms timeout window and waits for "EC Init Complete" command
+	 * 4. EC sets Source and Sink PDO mask if required
+	 * 5. EC sets Event mask if required
+	 * 6. EC sends EC Init Complete Command
+	 */
+
+	int rv, data, i;
+	const struct gpio_dt_spec *intr = gpio_get_dt_spec(pd_chip_config[controller].gpio);
+	struct {
+		int reg;
+		int value;
+		int length;
+		int status_reg;
+	} const cypd_setup_cmds[] = {
+		/* Set the port event mask */
+		{ CCG_EVENT_MASK_REG(0), 0x27ffff, 4, CCG_PORT0_INTR},
+		{ CCG_EVENT_MASK_REG(1), 0x27ffff, 4, CCG_PORT1_INTR },
+	};
+	BUILD_ASSERT(ARRAY_SIZE(cypd_setup_cmds) == CYPD_SETUP_CMDS_LEN);
+
+	/* Make sure the interrupt is not asserted before we start */
+	if (gpio_pin_get_dt(intr) == 0) {
+		rv = cypd_get_int(controller, &data);
+		CPRINTS("%s int already pending 0x%04x", __func__, data);
+		cypd_clear_int(controller,
+			CCG_DEV_INTR + CCG_PORT0_INTR + CCG_PORT1_INTR + CCG_UCSI_INTR);
+	}
+	for (i = 0; i < CYPD_SETUP_CMDS_LEN; i++) {
+		rv = cypd_write_reg_block(controller, cypd_setup_cmds[i].reg,
+		(void *)&cypd_setup_cmds[i].value, cypd_setup_cmds[i].length);
+		if (rv != EC_SUCCESS) {
+			CPRINTS("%s command: 0x%04x failed", __func__, cypd_setup_cmds[i].reg);
+			return EC_ERROR_INVAL;
+		}
+		/* wait for interrupt ack to be asserted */
+		if (cypd_wait_for_ack(controller, 5) != EC_SUCCESS) {
+			CPRINTS("%s timeout on interrupt", __func__);
+			return EC_ERROR_INVAL;
+		}
+
+		/* clear cmd ack */
+		cypd_clear_int(controller, cypd_setup_cmds[i].status_reg);
+	}
+
+	/* Make sure the vbus fet control is configured before the PD controller
+	 * auto enables one or more ports
+	 */
+	if (prev_charge_port != -1) {
+		for (i = 0; i < PD_PORT_COUNT; i++) {
+			if (PORT_TO_CONTROLLER(i) == controller) {
+				cypd_cfet_vbus_control(i, i == prev_charge_port, true);
+			}
+		}
+	}
+
+	/*Notify the PD controller we are done and it can continue init*/
+	rv = cypd_write_reg8_wait_ack(controller,
+								CCG_PD_CONTROL_REG(0),
+								CCG_PD_CMD_EC_INIT_COMPLETE);
+	return EC_SUCCESS;
+}
+
+static void cypd_handle_state(int controller)
+{
+	int data;
+	int delay = 0;
+
+	switch (pd_chip_config[controller].state) {
+	case CCG_STATE_POWER_ON:
+		/* poll to see if the controller has booted yet */
+		if (cypd_read_reg8(controller, CCG_DEVICE_MODE, &data) == EC_SUCCESS) {
+			if ((data & 0x03) == 0x00) {
+				CPRINTS("CYPD %d is in bootloader 0x%04x", controller, data);
+				delay = 25*MSEC;
+				if (cypd_read_reg16(controller, CCG_BOOT_MODE_REASON, &data)
+						== EC_SUCCESS) {
+					CPRINTS("CYPD bootloader reason 0x%02x", data);
+				}
+
+			} else
+				pd_chip_config[controller].state = CCG_STATE_APP_SETUP;
+		}
+		/*try again in a while*/
+		if (delay) {
+			if (controller == 0)
+				hook_call_deferred(&pd0_update_state_deferred_data, delay);
+			else
+				hook_call_deferred(&pd1_update_state_deferred_data, delay);
+		} else
+			task_set_event(TASK_ID_CYPD, CCG_EVT_STATE_CTRL_0 << controller);
+		break;
+
+	case CCG_STATE_APP_SETUP:
+			gpio_disable_interrupt(pd_chip_config[controller].gpio);
+			cypd_get_version(controller);
+			cypd_update_power_status(controller);
+
+			update_system_power_state(controller);
+			cypd_setup(controller);
+
+			/* After initial complete, update the type-c port state */
+			cypd_update_port_state(controller, 0);
+			cypd_update_port_state(controller, 1);
+
+			ucsi_startup(controller);
+
+			gpio_enable_interrupt(pd_chip_config[controller].gpio);
+
+			/* Update PDO format after init complete */
+			if (controller)
+				hook_call_deferred(&pdo_init_deferred_data, 25 * MSEC);
+
+			CPRINTS("CYPD %d Ready!", controller);
+			pd_chip_config[controller].state = CCG_STATE_READY;
+		break;
+	default:
+		CPRINTS("PD handle_state but in 0x%02x state!", pd_chip_config[controller].state);
+		break;
+	}
+
+}
+
+static void print_pd_response_code(uint8_t controller, uint8_t port, uint8_t id, int len)
+{
+	if (verbose_msg_logging) {
+		CPRINTS("PD Controller %d Port %d  Code 0x%02x %s Len: 0x%02x",
+		controller,
+		port,
+		id,
+		id & 0x80 ? "Response" : "Event",
+		len);
+	}
+}
+
+
+
+
+/*****************************************************************************/
+/* Project */
+int cypd_get_ac_power(void)
+{
+	int ac_power_mW = 0;
+
+	/* -1 means no ac */
+	if (prev_charge_port == -1)
+		return 0;
+
+	ac_power_mW = (pd_port_states[prev_charge_port].current
+		* pd_port_states[prev_charge_port].voltage);
+
+	if (!isl9241_is_in_bypass_mode(0)) {
+		/* limit to 100W if not in bypass mode */
+		ac_power_mW = MIN(100000000, ac_power_mW);
+	}
+
+	return (ac_power_mW / 1000);
+}
+
+/*****************************************************************************/
+/* Interrupt handler */
+
+int cypd_device_int(int controller)
+{
+	int data;
+
+	if (cypd_read_reg16(controller, CCG_RESPONSE_REG, &data) == EC_SUCCESS) {
+
+		print_pd_response_code(controller, -1, data & 0xff, data>>8);
+
+		switch (data & 0xFF) {
+		case CCG_RESPONSE_RESET_COMPLETE:
+			CPRINTS("PD%d Reset Complete", controller);
+
+			pd_chip_config[controller].state = CCG_STATE_POWER_ON;
+			/* Run state handler to set up controller */
+			task_set_event(TASK_ID_CYPD, 4 << controller);
+			break;
+		case CCG_RESPONSE_MESSAGE_QUEUE_OVERFLOW:
+			CPRINTS("PD%d Message Overflow", controller);
+			break;
+		default:
+			CPRINTS("INTR_REG CTRL:%d TODO Device 0x%x", controller, data & 0xFF);
+		}
+	} else
+		return EC_ERROR_INVAL;
+
+
+	return EC_SUCCESS;
+}
+static bool pending_dp_poweroff[PD_PORT_COUNT];
+static void poweroff_dp_check(void)
+{
+	int i;
+	int alt_active = 0;
+
+	for (i = 0; i < PD_PORT_COUNT; i++) {
+		if (pending_dp_poweroff[i]) {
+			/* see if alt mode is active */
+			cypd_read_reg8(PORT_TO_CONTROLLER(i),
+				CCG_DP_ALT_MODE_CONFIG_REG(PORT_TO_CONTROLLER_PORT(i)),
+				&alt_active);
+			/* DP_ALT should be on bit 1 always, but there is a bug
+			 * in the PD stack that if a port does not have TBT mode
+			 * enabled, it will shift the DP alt mode enable bit to
+			 * bit 0. Since we only whitelist DP alt mode cards, just
+			 * mask on both as a workaround.
+			 */
+			if ((alt_active & (BIT(1) + BIT(0))) == 0) {
+				port_to_safe_mode(i);
+			}
+			pending_dp_poweroff[i] = 0;
+		}
+	}
+}
+static void poweroff_dp_deferred(void)
+{
+	task_set_event(TASK_ID_CYPD, CCG_EVT_DPALT_DISABLE);
+
+}
+DECLARE_DEFERRED(poweroff_dp_deferred);
+
+struct framework_dp_ids {
+	uint16_t vid;
+	uint16_t pid;
+} const cypd_altmode_ids[] = {
+	{0x32AC, 0x0002},
+	{0x32AC, 0x0003},
+	{0x32AC, 0x000E},
+};
+struct match_vdm_header {
+	uint8_t idx;
+	uint8_t val;
+} const framework_vdm_hdr_match[] = {
+	{0, 0x8f},
+	/*{1, 0x52},*/
+	{2, 0},
+	{4, 0x41},
+	/*{5, 0xa0},*/
+	{6, 0x00},
+	{7, 0xFF},
+	/*{8, 0xAC}, Framework VID */
+	/*{9, 0x32}, */
+	/*{10, 0x00},*/
+	/*{11, 0x6C}*/
+};
+
+void cypd_handle_vdm(int controller, int port, uint8_t *data, int len)
+{
+	/* parse vdm
+	 * if we get a DP alt mode VDM that matches our
+	 * HDMI or DP VID/PID we will start a timer
+	 * to set the port mux to safe/isolate
+	 * if we get a enter alt mode later on,
+	 * we will cancel the timer so that PD can
+	 * properly enter the alt mode
+	 *
+	 *                       ID HDR            ProductVDO
+	 *   hdr  SOP R VDMHDR   VDO      VDO      VDO
+	 * HDMI
+	 * 0x8f52 00 00 41a000ff ac32006c 00000000 00000200 18000000
+	 * DP
+	 * 0x8f52 00 00 41a000ff ac32006c 00000000 00000300 18000000
+	 *   0 1  2  3  4        8        12       16
+	 * 180W Power Adapter
+	 * 0x8f59 00 00 41a800ff ac32c001 00000000 00000e00 01008020
+	 */
+	int i;
+	uint16_t vid, pid;
+	bool trigger_deferred_update = false;
+
+	for (i = 0; i < sizeof(framework_vdm_hdr_match)/sizeof(struct match_vdm_header); i++) {
+		if (framework_vdm_hdr_match[i].idx >= len) {
+			continue;
+		}
+		if (data[framework_vdm_hdr_match[i].idx] !=
+			framework_vdm_hdr_match[i].val) {
+			return;
+			}
+	}
+
+	for (i = 0; i < sizeof(cypd_altmode_ids)/sizeof(struct framework_dp_ids); i++) {
+		vid = cypd_altmode_ids[i].vid;
+		pid = cypd_altmode_ids[i].pid;
+		if ((vid & 0xFF) == data[8] &&
+			((vid>>8) & 0xFF) == data[9] &&
+			(pid & 0xFF) == data[18] &&
+			((pid>>8) & 0xFF) == data[19]
+			) {
+			pending_dp_poweroff[port + (controller<<1)] = true;
+			trigger_deferred_update = true;
+				CPRINTS(" vdm vidpid match");
+
+		}
+
+	}
+	if (trigger_deferred_update) {
+		hook_call_deferred(&poweroff_dp_deferred_data, 30000 * MSEC);
+	}
+
+}
+
+void cypd_port_int(int controller, int port)
+{
+	int i, rv, response_len;
+	uint8_t data2[32];
+	uint16_t i2c_port = pd_chip_config[controller].i2c_port;
+	uint16_t addr_flags = pd_chip_config[controller].addr_flags;
+	int port_idx = (controller << 1) + port;
+	enum tcpci_msg_type sop_type;
+	static int snk_transition_flags;
+
+	/* enum pd_msg_type sop_type; */
+	rv = i2c_read_offset16_block(i2c_port, addr_flags,
+		CCG_PORT_PD_RESPONSE_REG(port), data2, 4);
+	if (rv != EC_SUCCESS)
+		CPRINTS("PORT_PD_RESPONSE_REG failed");
+
+	print_pd_response_code(controller, port, data2[0], data2[1]);
+
+	response_len = data2[1];
+	switch (data2[0]) {
+	case CCG_RESPONSE_PORT_DISCONNECT:
+		record_ucsi_connector_change_event(controller, port);
+		cypd_release_port(controller, port);
+		CPRINTS("PORT_DISCONNECT");
+		__fallthrough;
+	case CCG_RESPONSE_HARD_RESET_RX:
+	case CCG_RESPONSE_TYPE_C_ERROR_RECOVERY:
+	case CCG_RESPONSE_HARD_RESET_SENT:
+		if (data2[0] == CCG_RESPONSE_HARD_RESET_RX)
+			CPRINTS("HARD_RESET_RX");
+		if (data2[0] == CCG_RESPONSE_TYPE_C_ERROR_RECOVERY)
+			CPRINTS("TYPE_C_ERROR_RECOVERY");
+		if (data2[0] == CCG_RESPONSE_HARD_RESET_SENT)
+			CPRINTS("CCG_RESPONSE_HARD_RESET_SENT");
+
+#ifdef CONFIG_BOARD_LOTUS
+		/* Assert prochot until the PMF is updated (Only sink role needs to do this) */
+		if (pd_port_states[(controller << 1) + port].power_role == PD_ROLE_SINK &&
+		   (prev_charge_port == (controller << 1) + port)) {
+			update_pmf_events(BIT(PD_PROGRESS_DISCONNECTED), 1);
+
+			/* clear the EPR progress when the adapter is removed */
+			pd_epr_in_progress &= EPR_PROCESS_MASK;
+			set_gpu_gpio(GPIO_FUNC_ACDC, 0);
+		}
+#endif
+
+		cypd_update_port_state(controller, port);
+		/* make sure the type-c state is cleared */
+		clear_port_state(controller, port);
+
+		if (IS_ENABLED(CONFIG_CHARGE_MANAGER))
+			charge_manager_update_dualrole(port_idx, CAP_UNKNOWN);
+
+		break;
+	case CCG_RESPONSE_PD_CONTRACT_NEGOTIATION_COMPLETE:
+		CPRINTS("CYPD_RESPONSE_PD_CONTRACT_NEGOTIATION_COMPLETE %d", port_idx);
+		cypd_update_port_state(controller, port);
+		cypd_set_prepare_pdo(controller, port);
+#ifdef CONFIG_BOARD_LOTUS
+		/* make sure enter EPR mode only process in S0 state */
+		if (chipset_in_state(CHIPSET_STATE_ON))
+			hook_call_deferred(&enter_epr_mode_data, 100 * MSEC);
+
+#endif
+		break;
+	case CCG_RESPONSE_PORT_CONNECT:
+		CPRINTS("CYPD_RESPONSE_PORT_CONNECT %d", port_idx);
+		record_ucsi_connector_change_event(controller, port);
+		cypd_set_typec_profile(controller, port);
+		break;
+	case CCG_RESPONSE_SOURCE_CAP_MSG_RX:
+		i2c_read_offset16_block(i2c_port, addr_flags,
+				CCG_READ_DATA_MEMORY_REG(port, 0), data2, MIN(response_len, 32));
+
+		if (data2[6] & BIT(7)) {
+			pd_port_states[port_idx].epr_support = 1;
+			CPRINTS("P%d EPR mode capable", port_idx);
+		}
+		if (!battery_is_cut_off() && !battery_cutoff_in_progress())
+			snk_transition_flags = 1;
+
+		break;
+	case CCG_RESPONSE_EPR_EVENT:
+		CPRINTS("CCG_RESPONSE_EPR_EVENT %d", port_idx);
+		cypd_update_epr_state(controller, port, response_len);
+		cypd_update_port_state(controller, port);
+		break;
+	case CCG_RESPONSE_ACCEPT_MSG_RX:
+		CPRINTS("CCG_RESPONSE_ACCEPT_MSG_RX %d", port_idx);
+		if (snk_transition_flags) {
+			charge_manager_force_ceil(port_idx, 500);
+			snk_transition_flags = 0;
+		}
+		break;
+	case CCG_RESPONSE_EXT_MSG_SOP_RX:
+	case CCG_RESPONSE_EXT_SOP1_RX:
+	case CCG_RESPONSE_EXT_SOP2_RX:
+		if (data2[0] == CCG_RESPONSE_EXT_MSG_SOP_RX)
+			sop_type = TCPCI_MSG_SOP;
+		else if (data2[0] == CCG_RESPONSE_EXT_MSG_SOP_RX)
+			sop_type = TCPCI_MSG_SOP_PRIME;
+		else if (data2[0] == CCG_RESPONSE_EXT_MSG_SOP_RX)
+			sop_type = TCPCI_MSG_SOP_PRIME_PRIME;
+		cypd_handle_extend_msg(controller, port, response_len, sop_type);
+		CPRINTS("CYP_RESPONSE_RX_EXT_MSG");
+		break;
+	case CCG_RESPONSE_VDM_RX:
+		i2c_read_offset16_block(i2c_port, addr_flags,
+			CCG_READ_DATA_MEMORY_REG(port, 0), data2, MIN(response_len, 32));
+		cypd_handle_vdm(controller, port, data2, response_len);
+		CPRINTS("CCG_RESPONSE_VDM_RX");
+		__fallthrough;
+	default:
+		if (response_len && verbose_msg_logging) {
+			CPRINTF("Port:%d Data:0x", port_idx);
+			i2c_read_offset16_block(i2c_port, addr_flags,
+				CCG_READ_DATA_MEMORY_REG(port, 0), data2, MIN(response_len, 32));
+			for (i = 0; i < response_len; i++)
+				CPRINTF("%02x", data2[i]);
+			CPRINTF("\n");
+		}
+		break;
+	}
+}
+
+void cypd_interrupt(int controller)
+{
+	int data;
+	int rv;
+	int clear_mask = 0;
+
+	rv = cypd_get_int(controller, &data);
+	if (rv != EC_SUCCESS) {
+		return;
+	}
+
+	if (data & CCG_DEV_INTR) {
+		cypd_device_int(controller);
+		clear_mask |= CCG_DEV_INTR;
+	}
+
+	if (data & CCG_PORT0_INTR) {
+		cypd_port_int(controller, 0);
+		clear_mask |= CCG_PORT0_INTR;
+	}
+
+	if (data & CCG_PORT1_INTR) {
+		cypd_port_int(controller, 1);
+		clear_mask |= CCG_PORT1_INTR;
+	}
+
+	if (data & CCG_ICLR_INTR)
+		clear_mask |= CCG_ICLR_INTR;
+
+	if (clear_mask)
+		cypd_clear_int(controller, clear_mask);
+
+	if (data & CCG_UCSI_INTR) {
+		ucsi_read_tunnel(controller);
+		cypd_clear_int(controller, CCG_UCSI_INTR);
+	}
+}
+
+void pd0_chip_interrupt(enum gpio_signal signal)
+{
+	if (gpio_pin_get_dt(gpio_get_dt_spec(pd_chip_config[PD_CHIP_0].gpio)) == 0)
+		task_set_event(TASK_ID_CYPD, CCG_EVT_INT_CTRL_0);
+}
+
+void pd1_chip_interrupt(enum gpio_signal signal)
+{
+	if (gpio_pin_get_dt(gpio_get_dt_spec(pd_chip_config[PD_CHIP_1].gpio)) == 0)
+		task_set_event(TASK_ID_CYPD, CCG_EVT_INT_CTRL_1);
+}
+
+static void cypd_ucsi_wait_delay_deferred(void)
+{
+	task_set_event(TASK_ID_CYPD, CCG_EVT_UCSI_PPM_RESET);
+}
+DECLARE_DEFERRED(cypd_ucsi_wait_delay_deferred);
+
+void cypd_usci_ppm_reset(void)
+{
+	/* wait PD chip finish UCSI process */
+	hook_call_deferred(&cypd_ucsi_wait_delay_deferred_data, 500 * MSEC);
+}
+
+/*****************************************************************************/
+/* CYPD task */
+
+static int ucsi_tunnel_disabled;
+
+void cypd_interrupt_handler_task(void *p)
+{
+	int i, j, evt;
+
+	/* Initialize all charge suppliers to 0 */
+	for (i = 0; i < CHARGE_PORT_COUNT; i++) {
+		for (j = 0; j < CHARGE_SUPPLIER_COUNT; j++)
+			charge_manager_update_charge(j, i, NULL);
+	}
+
+	/* trigger the handle_state to start setup in task */
+	task_set_event(TASK_ID_CYPD, (CCG_EVT_STATE_CTRL_0 | CCG_EVT_STATE_CTRL_1));
+
+	for (i = 0; i < PD_CHIP_COUNT; i++) {
+		cypd_enable_interrupt(i, true);
+		task_set_event(TASK_ID_CYPD, CCG_EVT_STATE_CTRL_0<<i);
+	}
+
+
+	while (1) {
+		evt = task_wait_event(10*MSEC);
+
+		if (firmware_update)
+			continue;
+
+		/*
+		 * USCI PPM RESET will make PD current setting to default
+		 * need setting port current again
+		 */
+		if (evt & CCG_EVT_UCSI_PPM_RESET)
+			cypd_ppm_port_clear();
+
+		if (evt & CCG_EVT_PDO_RESET)
+			cypd_port_current_setting();
+
+		if (evt & CCG_EVT_S_CHANGE)
+			update_system_power_state(2);
+
+		if (evt & CCG_EVT_INT_CTRL_0)
+			cypd_interrupt(0);
+
+		if (evt & CCG_EVT_INT_CTRL_1)
+			cypd_interrupt(1);
+
+		if (evt & CCG_EVT_STATE_CTRL_0) {
+			cypd_handle_state(0);
+			task_wait_event_mask(TASK_EVENT_TIMER,10);
+		}
+
+		if (evt & CCG_EVT_STATE_CTRL_1) {
+			cypd_handle_state(1);
+			task_wait_event_mask(TASK_EVENT_TIMER,10);
+		}
+
+		if (evt & CCG_EVT_PDO_INIT_0) {
+			/* update new PDO format to select pdo register */
+			cypd_pdo_init(0, 0, CCG_PD_CMD_SET_TYPEC_3A);
+			cypd_pdo_init(1, 0, CCG_PD_CMD_SET_TYPEC_3A);
+			task_wait_event_mask(TASK_EVENT_TIMER, 10);
+			task_set_event(TASK_ID_CYPD, CCG_EVT_PDO_INIT_1);
+		}
+
+		if (evt & CCG_EVT_PDO_INIT_1) {
+			/* update new PDO format to select pdo register */
+			cypd_pdo_init(0, 1, CCG_PD_CMD_SET_TYPEC_3A);
+			cypd_pdo_init(1, 1, CCG_PD_CMD_SET_TYPEC_3A);
+			task_wait_event_mask(TASK_EVENT_TIMER, 10);
+		}
+
+		if (evt & CCG_EVT_DPALT_DISABLE) {
+			poweroff_dp_check();
+		}
+
+		if (evt & CCG_EVT_PDO_C0P0)
+			cypd_set_typec_profile(0, 0);
+
+		if (evt & CCG_EVT_PDO_C0P1)
+			cypd_set_typec_profile(0, 1);
+
+		if (evt & CCG_EVT_PDO_C1P0)
+			cypd_set_typec_profile(1, 0);
+
+		if (evt & CCG_EVT_PDO_C1P1)
+			cypd_set_typec_profile(1, 1);
+
+		if (evt & CCG_EVT_UPDATE_PWRSTAT)
+			cypd_update_power_status(2);
+
+
+		if (evt & (CCG_EVT_INT_CTRL_0 | CCG_EVT_INT_CTRL_1 |
+					CCG_EVT_STATE_CTRL_0 | CCG_EVT_STATE_CTRL_1)) {
+			/*
+			 * If we just processed an event or sent some commands
+			 * wait a bit for the pd controller to clear any pending
+			 * interrupt requests
+			 */
+			usleep(50);
+		}
+		if (!ucsi_tunnel_disabled)
+			check_ucsi_event_from_host();
+
+		for (i = 0; i < PD_CHIP_COUNT; i++) {
+			const struct gpio_dt_spec *intr = gpio_get_dt_spec(pd_chip_config[i].gpio);
+			if (gpio_pin_get_dt(intr) == 0) {
+				task_set_event(TASK_ID_CYPD, 1<<i);
+			}
+		}
+	}
+}
+
+/*****************************************************************************/
+/* Commmon functions */
+
+enum pd_power_role pd_get_power_role(int port)
+{
+	return pd_port_states[port].power_role;
+}
+
+void pd_request_power_swap(int port)
+{
+	CPRINTS("TODO Implement %s port %d", __func__, port);
+}
+
+void pd_set_new_power_request(int port)
+{
+	/* We probably dont need to do this since we will always request max. */
+	CPRINTS("TODO Implement %s port %d", __func__, port);
+}
+
+int pd_is_connected(int port)
+{
+	return pd_port_states[port].c_state != CCG_STATUS_NOTHING;
+}
+
+int pd_get_active_current(int port)
+{
+	return pd_port_states[port].current;
+}
+
+__override uint8_t board_get_usb_pd_port_count(void)
+{
+	return CONFIG_USB_PD_PORT_MAX_COUNT;
+}
+
+/**
+ * Set active charge port -- only one port can be active at a time.
+ *
+ * @param charge_port   Charge port to enable.
+ *
+ * Returns EC_SUCCESS if charge port is accepted and made active,
+ * EC_ERROR_* otherwise.
+ */
+int board_set_active_charge_port(int charge_port)
+{
+	int i;
+	CPRINTS("%s port %d, prev:%d", __func__, charge_port, prev_charge_port);
+
+
+	if (prev_charge_port == charge_port) {
+		/* in the case of hard reset, we do not turn off the old
+		 * port, but the PD will implicitly clear the port
+		 * so we need to turn on the vbus control again.
+		 */
+		cypd_cfet_vbus_control(charge_port, true, true);
+#ifdef CONFIG_BOARD_LOTUS
+		board_disable_bypass_oneshot();
+#endif
+		return EC_SUCCESS;
+	}
+
+
+	if (prev_charge_port != -1 &&
+		prev_charge_port != charge_port) {
+		/* Turn off the previous charge port before turning on the next port */
+		cypd_cfet_vbus_control(prev_charge_port, false, true);
+#ifdef CONFIG_BOARD_LOTUS
+		board_disable_bypass_oneshot();
+#endif
+		if (isl9241_is_in_bypass_mode(0)) {
+			CPRINTS("Force exit bypass mode for port switch");
+			if (chg_chips[0].drv->enable_bypass_mode)
+			chg_chips[0].drv->enable_bypass_mode(0, false);
+			/* ACOK threshold has been lowered, give the charger some time to
+			 * discharge the input caps before switching to the new port
+			 */
+			usleep(8*MSEC);
+		}
+
+
+	}
+
+	for (i = 0; i < PD_PORT_COUNT; i++) {
+		/* Just brute force all ports, we want to make sure
+		 * we always update all ports in case a PD controller rebooted or some
+		 * other error happens that we are not tracking state with.
+		 */
+		cypd_cfet_vbus_control(i, i == charge_port, true);
+	}
+	prev_charge_port = charge_port;
+	hook_call_deferred(&update_power_state_deferred_data, 100 * MSEC);
+
+	return EC_SUCCESS;
+}
+
+uint8_t *get_pd_version(int controller)
+{
+	return pd_chip_config[controller].version;
+}
+
+int active_charge_pd_chip(void)
+{
+	if (prev_charge_port == -1)
+		return 0xff;
+
+	return (prev_charge_port < 2) ? 0 : 1;
+}
+
+int get_active_charge_pd_port(void)
+{
+	/**
+	 * charge_manager_get_active_charge_port() return the charger port too late,
+	 * we need to get the active port status immediately.
+	 */
+
+	return prev_charge_port;
+}
+
+void set_pd_fw_update(bool is_update)
+{
+	firmware_update = is_update;
+}
+
+void cypd_reinitialize(void)
+{
+	int i;
+
+	for (i = 0; i < PD_CHIP_COUNT; i++) {
+		pd_chip_config[i].state = CCG_STATE_POWER_ON;
+		/* Run state handler to set up controller */
+		task_set_event(TASK_ID_CYPD, 4<<i);
+	}
+}
+
+/*****************************************************************************/
+/* Host command */
+
+/*****************************************************************************/
+/* EC console command */
+
+static int cmd_cypd_get_status(int argc, const char **argv)
+{
+	int i, p, data;
+	uint8_t data16[16];
+	char *e;
+
+	static const char * const mode[] = {"Boot", "FW1", "FW2", "Invald"};
+	static const char * const current_level[] = {"DefaultA", "1.5A", "3A", "InvA"};
+	static const char * const port_status[] = {
+		"Nothing", "Sink", "Source", "Debug", "Audio", "Powered Acc",
+		"Unsupported", "Invalid"
+	};
+	static const char * const state[] = {
+		"ERR", "POWER_ON", "APP_SETUP", "READY", "BOOTLOADER"
+	};
+	const struct gpio_dt_spec *intr;
+
+	for (i = 0; i < PD_CHIP_COUNT; i++) {
+		intr = gpio_get_dt_spec(pd_chip_config[i].gpio);
+		CPRINTS("PD%d INT value: %d", i, gpio_pin_get_dt(intr));
+	}
+
+	/* If a signal is specified, print only that one */
+	if (argc == 2) {
+		i = strtoi(argv[1], &e, 0);
+		if (*e)
+			return EC_ERROR_PARAM1;
+
+		if (i < PD_CHIP_COUNT) {
+			CPRINTS("State: %s", state[pd_chip_config[i].state]);
+			cypd_read_reg16(i, CCG_SILICON_ID, &data);
+			CPRINTS("CYPD_SILICON_ID: 0x%04x", data);
+			cypd_get_version(i);
+			cypd_read_reg8(i, CCG_DEVICE_MODE, &data);
+			CPRINTS("CYPD_DEVICE_MODE: 0x%02x %s", data, mode[data & 0x03]);
+			cypd_read_reg_block(i, CCG_HPI_VERSION, data16, 4);
+			CPRINTS("HPI_VERSION: 0x%02x%02x%02x%02x",
+						data16[3], data16[2], data16[1], data16[0]);
+			cypd_read_reg8(i, CCG_INTR_REG, &data);
+			CPRINTS("CYPD_INTR_REG: 0x%02x %s %s %s %s",
+						data,
+						data & CCG_DEV_INTR ? "DEV" : "",
+						data & CCG_PORT0_INTR ? "PORT0" : "",
+						data & CCG_PORT1_INTR ? "PORT1" : "",
+						data & CCG_UCSI_INTR ? "UCSI" : "");
+			cypd_read_reg16(i, CCG_RESPONSE_REG, &data);
+			CPRINTS("CYPD_RESPONSE_REG: 0x%02x", data);
+			cypd_read_reg16(i, CCG_PORT_PD_RESPONSE_REG(0), &data);
+			CPRINTS("CYPD_PORT0_PD_RESPONSE_REG: 0x%02x", data);
+			cypd_read_reg16(i, CCG_PORT_PD_RESPONSE_REG(1), &data);
+			CPRINTS("CYPD_PORT1_PD_RESPONSE_REG: 0x%02x", data);
+			cypd_read_reg8(i, CCG_BOOT_MODE_REASON, &data);
+			CPRINTS("CYPD_BOOT_MODE_REASON: 0x%02x", data);
+			cypd_read_reg8(i, CCG_PDPORT_ENABLE_REG, &data);
+			CPRINTS("CYPD_PDPORT_ENABLE_REG: 0x%04x", data);
+			cypd_read_reg8(i, CCG_POWER_STAT, &data);
+			CPRINTS("CYPD_POWER_STAT: 0x%02x", data);
+			cypd_read_reg8(i, CCG_ICL_STS_REG, &data);
+			CPRINTS("CCG_ICL_STS_REG: 0x%04x", data);
+			cypd_read_reg8(i, CCG_SYS_PWR_STATE, &data);
+			CPRINTS("CYPD_SYS_PWR_STATE: 0x%02x", data);
+			for (p = 0; p < 2; p++) {
+				CPRINTS("=====Port %d======", p);
+				cypd_read_reg_block(i, CCG_PD_STATUS_REG(p), data16, 4);
+				CPRINTS("PD_STATUS %s DataRole:%s PowerRole:%s Vconn:%s Partner:%s EPR:%s %sCable:%s",
+						data16[1] & BIT(2) ? "Contract" : "NoContract",
+						data16[0] & BIT(6) ? "DFP" : "UFP",
+						data16[1] & BIT(0) ? "Source" : "Sink",
+						data16[1] & BIT(5) ? "En" : "Dis",
+						data16[2] & BIT(3) ? "Un-chunked" : "Chunked",
+						data16[2] & BIT(7) ? "EPR" : "Non EPR",
+						data16[1] & BIT(3) ? "EMCA " : "",
+						data16[2] & BIT(6) ? "Active" : "Passive");
+				cypd_read_reg8(i, CCG_TYPE_C_STATUS_REG(p), &data);
+				CPRINTS("   TYPE_C_STATUS : %s %s %s %s %s",
+							data & 0x1 ? "Connected" : "Not Connected",
+							data & 0x2 ? "CC2" : "CC1",
+							port_status[(data >> 2) & 0x7],
+							data & 0x20 ? "Ra" : "NoRa",
+							current_level[(data >> 6) & 0x03]);
+				cypd_read_reg8(i, CCG_PORT_VBUS_FET_CONTROL(p), &data);
+				CPRINTS("        VBUS_FET : %s %s",
+						data & 0x1 ? "EC" : "Auto",
+						data & 0x2 ? "On" : "Off");
+				cypd_read_reg_block(i, CCG_CURRENT_RDO_REG(p), data16, 4);
+				CPRINTS("             RDO : Current:%dmA MaxCurrent%dmA 0x%08x",
+						((data16[0] + (data16[1]<<8)) & 0x3FF)*10,
+						(((data16[1]>>2) + (data16[2]<<6)) & 0x3FF)*10,
+						*(uint32_t *)data16);
+
+				cypd_read_reg_block(i, CCG_CURRENT_PDO_REG(p), data16, 4);
+				CPRINTS("             PDO : MaxCurrent:%dmA Voltage%dmA 0x%08x",
+						((data16[0] + (data16[1]<<8)) & 0x3FF)*10,
+						(((data16[1]>>2) + (data16[2]<<6)) & 0x3FF)*50,
+						*(uint32_t *)data16);
+				cypd_read_reg8(i, CCG_TYPE_C_VOLTAGE_REG(p), &data);
+				CPRINTS("  TYPE_C_VOLTAGE : %dmV", data*100);
+				cypd_read_reg8(i, CCG_PORT_CURRENT_REG(p), &data);
+				CPRINTS("  TYPE_C_CURRENT : %dmA", data*50);
+				cypd_read_reg_block(i, CCG_PORT_INTR_STATUS_REG(p), data16, 4);
+				cypd_print_buff("      INTR_STATUS:", data16, 4);
+				cypd_read_reg16(i, SELECT_SINK_PDO_EPR_MASK(p), &data);
+				CPRINTS(" SINK PDO EPR MASK: 0x%02x", data);
+				/* Flush console to avoid truncating output */
+				cflush();
+			}
+			CPRINTS("=====UCSI======");
+			cypd_read_reg16(i, CCG_VERSION_REG, &data);
+			CPRINTS(" Version: 0x%02x", data);
+			cypd_read_reg_block(i, CCG_CCI_REG, data16, 4);
+			cypd_print_buff("     CCI:", data16, 4);
+			cypd_read_reg_block(i, CCG_CONTROL_REG, data16, 8);
+			cypd_print_buff(" Control:", data16, 8);
+			cypd_read_reg_block(i, CCG_MESSAGE_IN_REG, data16, 16);
+			cypd_print_buff(" Msg  In:", data16, 16);
+			cypd_read_reg_block(i, CCG_MESSAGE_OUT_REG, data16, 16);
+			cypd_print_buff(" Msg Out:", data16, 16);
+		}
+
+	}
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(cypdstatus, cmd_cypd_get_status, "[number]",
+			"Get Cypress PD controller status");
+
+static int cmd_cypd_control(int argc, const char **argv)
+{
+	int i, enable;
+	char *e;
+
+	if (argc >= 3) {
+		i = strtoi(argv[2], &e, 0);
+		if (*e || i >= PD_CHIP_COUNT)
+			return EC_ERROR_PARAM2;
+
+		if (!strncmp(argv[1], "en", 2) || !strncmp(argv[1], "dis", 3)) {
+			if (!parse_bool(argv[1], &enable))
+				return EC_ERROR_PARAM1;
+			if (enable)
+				cypd_enable_interrupt(i, true);
+			else
+				cypd_enable_interrupt(i, false);
+		} else if (!strncmp(argv[1], "reset", 5)) {
+			cypd_write_reg8(i, CCG_PDPORT_ENABLE_REG, 0);
+			/*can take up to 650ms to discharge port for disable*/
+			cypd_wait_for_ack(i, 65);
+			cypd_clear_int(i, CCG_DEV_INTR +
+					  CCG_PORT0_INTR +
+					  CCG_PORT1_INTR +
+					  CCG_UCSI_INTR);
+			usleep(50);
+			CPRINTS("Full reset PD controller %d", i);
+			/*
+			 * see if we can talk to the PD chip yet - issue a reset command
+			 * Note that we cannot issue a full reset command if the PD controller
+			 * has a device attached - as it will return with an invalid command
+			 * due to needing to disable all ports first.
+			 */
+			if (cypd_reset(i) == EC_SUCCESS) {
+				CPRINTS("reset ok %d", i);
+			}
+		} else if (!strncmp(argv[1], "clearint", 8)) {
+			cypd_clear_int(i, CCG_DEV_INTR +
+					  CCG_PORT0_INTR +
+					  CCG_PORT1_INTR +
+					  CCG_UCSI_INTR);
+		} else if (!strncmp(argv[1], "verbose", 7)) {
+			verbose_msg_logging = (i != 0);
+			CPRINTS("verbose=%d", verbose_msg_logging);
+		} else if (!strncmp(argv[1], "ucsitun", 7)) {
+			ucsi_tunnel_disabled = !i;
+			CPRINTS("ucsi tun=%d", i);
+		} else if (!strncmp(argv[1], "ucsi", 4)) {
+			ucsi_set_debug(i != 0);
+			CPRINTS("ucsi verbose=%d", i);
+		} else if (!strncmp(argv[1], "powerstate", 10)) {
+			int pwrstate;
+
+			if (argc < 4)
+				return EC_ERROR_PARAM3;
+			pwrstate = strtoul(argv[3], &e, 0);
+			if (*e)
+				return EC_ERROR_PARAM3;
+			cypd_set_power_state(pwrstate, 2);
+		} else if (!strncmp(argv[1], "write16", 3)) {
+			int r;
+			int regval;
+			if (argc < 5) {
+				return EC_ERROR_PARAM4;
+			}
+			r = strtoul(argv[3], &e, 0);
+			regval = strtoul(argv[4], &e, 0);
+			cypd_write_reg16(i, r,  regval);
+		} else if (!strncmp(argv[1], "write8", 3)) {
+			int r;
+			int regval;
+
+			if (argc < 5)
+				return EC_ERROR_PARAM4;
+			r = strtoul(argv[3], &e, 0);
+			regval = strtoul(argv[4], &e, 0);
+			cypd_write_reg8(i, r,  regval);
+		} else if (!strncmp(argv[1], "read16", 2)) {
+			int r;
+			int regval;
+
+			if (argc < 4)
+				return EC_ERROR_PARAM3;
+			r = strtoul(argv[3], &e, 0);
+			cypd_read_reg16(i, r,  &regval);
+			CPRINTS("data=%d", regval);
+		} else if (!strncmp(argv[1], "read8", 2)) {
+			int r;
+			int regval;
+
+			if (argc < 4)
+				return EC_ERROR_PARAM3;
+			r = strtoul(argv[3], &e, 0);
+			cypd_read_reg8(i, r,  &regval);
+			CPRINTS("data=%d", regval);
+		} else {
+			return EC_ERROR_PARAM1;
+		}
+	} else {
+		return EC_ERROR_PARAM_COUNT;
+	}
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(cypdctl, cmd_cypd_control,
+			"[enable/disable/reset/clearint/verbose/ucsi] [controller]",
+			"Set if handling is active for controller");
+
+
+static int cmd_pdwrite(int argc, const char **argv)
+{
+	int controller, addr, data, rv;
+	char *e;
+
+	controller = strtoi(argv[1], &e, 0);
+	addr = strtoi(argv[2], &e, 0);
+	data = strtoi(argv[3], &e, 0);
+
+	if (controller > 1)
+		return EC_ERROR_PARAM1;
+
+	CPRINTS("controller:%d ,addr:%x ,data:%d", controller, addr, data);
+
+	rv = cypd_write_reg8_wait_ack(controller, addr, data);
+	if (rv != EC_SUCCESS)
+		CPRINTS("Write data fail");
+
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(pdwrite, cmd_pdwrite,
+			"[controller] [addr] [data]",
+			"write data to PD");
+
+static int cmd_pdread(int argc, const char **argv)
+{
+	int controller, addr, data, rv;
+	char *e;
+
+	controller = strtoi(argv[1], &e, 0);
+	addr = strtoi(argv[2], &e, 0);
+
+	if (controller > 1)
+		return EC_ERROR_PARAM1;
+
+	rv = cypd_read_reg16(controller, addr, &data);
+	if (rv != EC_SUCCESS)
+		CPRINTS("Write data fail");
+
+	CPRINTS("controller:%d ,addr:%x ,data:%d", controller, addr, data);
+
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(pdread, cmd_pdread,
+			"[controller] [addr]",
+			"read data from PD");
diff --git a/zephyr/program/framework/src/diagnostics.c b/zephyr/program/framework/src/diagnostics.c
new file mode 100644
index 0000000000..3be8d60f82
--- /dev/null
+++ b/zephyr/program/framework/src/diagnostics.c
@@ -0,0 +1,190 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc.h"
+#include "battery.h"
+#include "board_host_command.h"
+#include "charge_state.h"
+#include "chipset.h"
+#include "diagnostics.h"
+#include "driver/temp_sensor/f75303.h"
+#include "ec_commands.h"
+#include "fan.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "led.h"
+#include "power.h"
+#include "port80.h"
+#include "timer.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+
+/**
+ * CROS_EC_HOOK_TICK_INTERVAL = 200 ms
+ * TICK_PER_SEC = 1000 ms / 200 ms = 5
+ */
+#define TICK_PER_SEC	5
+
+uint32_t hw_diagnostics;
+uint32_t diagnostic_tick;
+uint32_t diagnostics_ctr;
+uint32_t bios_code;
+
+uint8_t bios_complete;
+uint8_t fan_seen; /* TODO: Unused so far */
+uint8_t run_diagnostics;
+uint8_t device_complete;
+
+int standalone_mode;
+
+void set_standalone_mode(int enable)
+{
+	CPRINTS("set standalone = %d", enable);
+	standalone_mode = enable;
+}
+
+int get_standalone_mode(void)
+{
+	return standalone_mode;
+}
+
+
+void reset_diagnostics(void)
+{
+	/* Diagnostic always reset at G3/S5 */
+#ifdef CONFIG_BOARD_LOTUS
+	hw_diagnostics =
+		BIT(DIAGNOSTICS_NO_RIGHT_FAN) | BIT(DIAGNOSTICS_NO_LEFT_FAN) |
+		BIT(DIAGNOSTICS_NO_S0) | BIT(DIAGNOSTICS_HW_NO_BATTERY);
+#else
+	hw_diagnostics = BIT(DIAGNOSTICS_NO_S0) | BIT(DIAGNOSTICS_HW_NO_BATTERY);
+#endif
+
+	run_diagnostics = 1;
+
+	diagnostics_ctr = 0;
+	bios_complete = 0;
+	bios_code = 0;
+	diagnostic_tick = 0;
+	fan_seen = 0;
+	device_complete = 0;
+}
+
+void cancel_diagnostics(void)
+{
+	/**
+	 * We need to cancel the diagnostics if the user presses the power
+	 * button to power off the system during the diagnostic.
+	 */
+	run_diagnostics = 0;
+}
+
+static void set_diagnostic_leds(int color)
+{
+	led_set_color(color, EC_LED_ID_BATTERY_LED);
+}
+
+void set_diagnostic(enum diagnostics_device_idx idx, bool error)
+{
+	if (error)
+		hw_diagnostics |= 1 << idx;
+	else
+		hw_diagnostics &= ~(1 << idx);
+}
+
+void set_bios_diagnostic(uint8_t code)
+{
+	if (code == CODE_PORT80_COMPLETE) {
+		bios_complete = true;
+		CPRINTS("BIOS COMPLETE");
+	}
+
+	if (code == CODE_DDR_FAIL)
+		set_diagnostic(DIAGNOSTICS_NO_DDR, true);
+	if (code == CODE_NO_EDP && !get_standalone_mode())
+		set_diagnostic(DIAGNOSTICS_NO_EDP, true);
+}
+
+void set_device_complete(int done)
+{
+	device_complete = done;
+}
+
+bool diagnostics_tick(void)
+{
+	/* Don't need to run the diagnostic */
+	if (run_diagnostics == 0)
+		return false;
+
+	/* Diagnostic complete */
+	if (diagnostics_ctr >= DIAGNOSTICS_MAX) {
+		run_diagnostics = 0;
+		return false;
+	}
+
+	/* Wait 15 seconds for checks to complete */
+	if (++diagnostic_tick < 60 * TICK_PER_SEC)
+		return false;
+
+	/* Everything is ok after minimum 15 seconds of checking */
+	if (bios_complete && hw_diagnostics == 0)
+		return false;
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_right_side), 1);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_left_side), 1);
+
+	/* If something is wrong, display the diagnostic via the LED */
+	if (diagnostic_tick & 0x01)
+		set_diagnostic_leds(LED_OFF);
+	else {
+		if (diagnostics_ctr == DIAGNOSTICS_START) {
+			set_diagnostic_leds(LED_WHITE);
+			bios_code = port_80_last();
+			CPRINTS("Boot issue: HW 0x%08x BIOS: 0x%04x", hw_diagnostics, bios_code);
+		} else if (diagnostics_ctr  < DIAGNOSTICS_HW_FINISH) {
+			set_diagnostic_leds((hw_diagnostics & (1 << diagnostics_ctr))
+				? LED_RED : LED_GREEN);
+		} else if (diagnostics_ctr == DIAGNOSTICS_HW_FINISH)
+			set_diagnostic_leds(LED_AMBER);
+		else if (diagnostics_ctr < DIAGNOSTICS_MAX) {
+			set_diagnostic_leds((bios_code &
+				(1 << (diagnostics_ctr - DIAGNOSTICS_BIOS_BIT0)))
+				? LED_BLUE : LED_GREEN);
+		}
+		diagnostics_ctr++;
+	}
+
+	return true;
+
+}
+
+static void diagnostics_check(void)
+{
+	if (device_complete)
+		return;
+	/* Clear the DIAGNOSTIC_NO_S0 flag if chipset is resume */
+	set_diagnostic(DIAGNOSTICS_NO_S0, false);
+
+	/* Call deferred hook to check the device */
+	project_diagnostics();
+
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, diagnostics_check, HOOK_PRIO_DEFAULT);
+
+uint32_t get_hw_diagnostic(void)
+{
+	return hw_diagnostics;
+}
+
+uint8_t is_bios_complete(void)
+{
+	return bios_complete;
+}
+
+uint8_t is_device_complete(void)
+{
+	return device_complete;
+}
diff --git a/zephyr/program/framework/src/factory.c b/zephyr/program/framework/src/factory.c
new file mode 100644
index 0000000000..3b70e04b70
--- /dev/null
+++ b/zephyr/program/framework/src/factory.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright 2023 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/drivers/gpio.h>
+
+#include "ec_commands.h"
+#include "factory.h"
+#include "gpio.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "keyboard_protocol.h"
+
+static uint8_t factory_enable;
+
+static void fake_power_button(void);
+DECLARE_DEFERRED(fake_power_button);
+
+void factory_setting(uint8_t enable)
+{
+	factory_enable = enable;
+
+	/* Ignored the power button signal if we are in the factory mode */
+	if (factory_enable) {
+		hook_call_deferred(&fake_power_button_data, 250 * MSEC);
+		gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_powerbtn));
+	} else {
+		hook_call_deferred(&fake_power_button_data, -1);
+		gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_powerbtn));
+	}
+}
+
+int fake_pwr_press;
+
+int factory_status(void)
+{
+	return factory_enable;
+}
+
+static void fake_power_button(void)
+{
+#ifdef CONFIG_PLATFORM_EC_KEYBOARD
+	if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_on_off_btn_l)) == 0 &&
+		!fake_pwr_press) {
+		fake_pwr_press = 1;
+		keyboard_update_button(KEYBOARD_BUTTON_POWER_FAKE,
+			fake_pwr_press);
+	} else if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_on_off_btn_l)) == 1 &&
+		fake_pwr_press) {
+		fake_pwr_press = 0;
+		keyboard_update_button(KEYBOARD_BUTTON_POWER_FAKE,
+			fake_pwr_press);
+	}
+	hook_call_deferred(&fake_power_button_data, 100 * MSEC);
+#endif
+}
diff --git a/zephyr/program/framework/src/flash_storage.c b/zephyr/program/framework/src/flash_storage.c
new file mode 100644
index 0000000000..05538b99f8
--- /dev/null
+++ b/zephyr/program/framework/src/flash_storage.c
@@ -0,0 +1,164 @@
+/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <atomic.h>
+#include <zephyr/init.h>
+#include "gpio/gpio_int.h"
+#include "console.h"
+#include "task.h"
+#include "util.h"
+#include "zephyr_console_shim.h"
+#include <zephyr/devicetree.h>
+#include <zephyr/logging/log.h>
+#include <flash.h>
+
+#include "flash_storage.h"
+
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_GPIO, format, ## args)
+
+LOG_MODULE_REGISTER(flashstorage, LOG_LEVEL_ERR);
+
+static struct ec_flash_flags_info current_flags;
+bool flash_storage_dirty;
+
+bool check_flags_valid_header(void)
+{
+	if (current_flags.magic != FLASH_FLAGS_MAGIC ||
+		current_flags.length != (sizeof(current_flags) - 8) ||
+		current_flags.version != FLASH_FLAGS_VERSION) {
+		return false;
+	} else {
+		return true;
+	}
+}
+
+void flash_storage_load_defaults(void)
+{
+		CPRINTS("Init flash storage to defaults");
+		memset(&current_flags, 0x00, sizeof(current_flags));
+		current_flags.magic = FLASH_FLAGS_MAGIC;
+		current_flags.length = (sizeof(current_flags) - 8);
+		current_flags.version = FLASH_FLAGS_VERSION;
+		flash_storage_dirty = true;
+}
+
+int flash_storage_initialize(void)
+{
+
+	int rv;
+
+	rv = crec_flash_physical_read(SPI_FLAGS_REGION,
+									sizeof(current_flags),
+									(void *)&current_flags);
+	if (rv != EC_SUCCESS)
+		CPRINTS("Could not load flash storage");
+
+	/*Check structure is valid*/
+	if (check_flags_valid_header() == false) {
+		CPRINTS("loading flash default flags");
+		flash_storage_load_defaults();
+	}
+
+	return rv;
+}
+
+int flash_storage_update(enum ec_flash_flags_idx idx, uint8_t v)
+{
+	if (idx >= FLASH_FLAGS_MAX)
+		return EC_ERROR_PARAM1;
+
+	if (check_flags_valid_header() == false)
+		flash_storage_initialize();
+
+	if (current_flags.flags[idx] != v) {
+		current_flags.flags[idx] = v;
+		flash_storage_dirty = true;
+	}
+	return EC_SUCCESS;
+}
+
+int flash_storage_commit(void)
+{
+	int rv = EC_SUCCESS;
+
+	if (check_flags_valid_header() == false)
+		flash_storage_initialize();
+
+	if (flash_storage_dirty) {
+
+
+		rv = crec_flash_physical_erase(SPI_FLAGS_REGION, SPI_FLAGS_SIZE);
+
+		if (rv != EC_SUCCESS) {
+			CPRINTS("SPI fail to erase");
+			return rv;
+		}
+
+		current_flags.update_number += 1;
+
+		rv = crec_flash_physical_write(SPI_FLAGS_REGION,
+								sizeof(current_flags),
+								(void *)&current_flags);
+
+		if (rv != EC_SUCCESS) {
+			CPRINTS("SPI fail to write");
+			return rv;
+		}
+
+		CPRINTS("%s, update:%d", __func__, current_flags.update_number);
+
+		flash_storage_dirty = false;
+	}
+
+	return rv;
+}
+
+int flash_storage_get(enum ec_flash_flags_idx idx)
+{
+	if (idx >= FLASH_FLAGS_MAX)
+		return -1;
+
+	if (check_flags_valid_header() == false)
+		flash_storage_initialize();
+
+	return current_flags.flags[idx];
+}
+
+static int cmd_flash_flags(int argc, const char **argv)
+{
+	int data;
+	int i, d;
+	char *e;
+
+
+	if (argc >= 3) {
+
+		i = strtoi(argv[2], &e, 0);
+
+		if (*e)
+			return EC_ERROR_PARAM2;
+
+		if (!strcasecmp(argv[1], "read")) {
+			data = flash_storage_get(i);
+			CPRINTS("Flash data:%d", data);
+		} else if (argc >= 4 && !strcasecmp(argv[1], "write")) {
+
+			d = strtoi(argv[3], &e, 0);
+			if (*e)
+				return EC_ERROR_PARAM3;
+			flash_storage_update(i, d);
+			flash_storage_commit();
+		} else {
+			return EC_ERROR_PARAM3;
+		}
+		return EC_SUCCESS;
+	}
+
+	return EC_ERROR_PARAM2;
+}
+DECLARE_CONSOLE_COMMAND(flashflag, cmd_flash_flags,
+			"[read/write] i [d]",
+			"read or write bytes from flags structure");
diff --git a/zephyr/program/framework/src/hid_device.c b/zephyr/program/framework/src/hid_device.c
new file mode 100644
index 0000000000..6acaf92aa9
--- /dev/null
+++ b/zephyr/program/framework/src/hid_device.c
@@ -0,0 +1,953 @@
+/*
+ * Copyright (c) 2023 Framework Computer
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+#include "hid_device.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/i2c_emul.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/slist.h>
+#include <zephyr/sys/util.h>
+
+
+
+#include <zephyr/sys/util.h>
+#include <zephyr/kernel.h>
+#include <errno.h>
+#include <string.h>
+#include <zephyr/drivers/gpio.h>
+
+
+#include "console.h"
+#include "zephyr_console_shim.h"
+#include "i2c_hid.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "util.h"
+#include "math_util.h"
+
+
+#ifdef CONFIG_BOARD_LOTUS
+#include "touchpad_descriptor.h"
+#endif
+
+#define DT_DRV_COMPAT cros_ec_i2c_target_hid
+
+#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
+
+LOG_MODULE_REGISTER(hid_target);
+
+/* Framework HID fields */
+#define I2C_HID_MEDIAKEYS_VENDOR_ID 0x32AC
+#define I2C_HID_MEDIAKEYS_PRODUCT_ID 0x0006
+#define I2C_HID_ALS_PRODUCT_ID 0x001B
+
+#define I2C_HID_MEDIAKEYS_FW_VERSION 0x0001
+#define I2C_HID_MEDIAKEYS_HID_DESC_REGISTER	0x0055
+
+#define I2C_HID_HEADER_SIZE 3
+
+#define REPORT_ID_RADIO		0x01
+#define REPORT_ID_CONSUMER	0x02
+#define REPORT_ID_SENSOR	0x03
+
+#define ALS_REPORT_STOP		0x00
+#define ALS_REPORT_POLLING	0x01
+#define ALS_REPORT_THRES	0x02
+
+
+
+#define EVENT_HID_HOST_IRQ	0x8000
+#define EVENT_REPORT_ILLUMINANCE_VALUE	0x4000
+
+/**
+ * ALS HID Unit Exponent
+ * 0x00 = 1	(Default)
+ * 0x0C = 0.0001
+ * 0x0D = 0.001
+ * 0x0E = 0.01
+ * 0x0F = 0.1
+ */
+#define ALS_HID_UNIT	0x00
+
+#define HID_ALS_MAX 10000
+#define HID_ALS_MIN 0
+/* Note sensitivity is scaled by exponent 0.01*/
+#define HID_ALS_SENSITIVITY 100
+
+#define HID_ALS_REPORT_INTERVAL 1000
+
+/* HID_USAGE_SENSOR_PROPERTY_SENSOR_CONNECTION_TYPE */
+#define HID_INTEGRATED			1
+#define HID_ATTACHED			2
+#define HID_EXTERNAL			3
+
+/* HID_USAGE_SENSOR_PROPERTY_REPORTING_STATE */
+#define HID_NO_EVENTS			1
+#define HID_ALL_EVENTS			2
+#define HID_THRESHOLD_EVENTS		3
+#define HID_NO_EVENTS_WAKE		4
+#define HID_ALL_EVENTS_WAKE		5
+#define HID_THRESHOLD_EVENTS_WAKE	6
+
+/* HID_USAGE_SENSOR_PROPERTY_POWER_STATE */
+#define HID_UNDEFINED			1
+#define HID_D0_FULL_POWER		2
+#define HID_D1_LOW_POWER		3
+#define HID_D2_STANDBY_WITH_WAKE	4
+#define HID_D3_SLEEP_WITH_WAKE		5
+#define HID_D4_POWER_OFF		6
+
+/* HID_USAGE_SENSOR_STATE */
+#define HID_UNKNOWN			1
+#define HID_READY			2
+#define HID_NOT_AVAILABLE		3
+#define HID_NO_DATA			4
+#define HID_INITIALIZING		5
+#define HID_ACCESS_DENIED		6
+#define HID_ERROR			7
+
+/* HID_USAGE_SENSOR_EVENT */
+#define HID_UNKNOWN			1
+#define HID_STATE_CHANGED		2
+#define HID_PROPERTY_CHANGED		3
+#define HID_DATA_UPDATED		4
+#define HID_POLL_RESPONSE		5
+#define HID_CHANGE_SENSITIVITY		6
+
+
+struct radio_report {
+	uint8_t state;
+} __packed;
+
+struct consumer_button_report {
+	uint16_t button_id;
+} __packed;
+
+struct als_input_report {
+	uint8_t sensor_state;
+	uint8_t event_type;
+	uint16_t illuminanceValue;
+} __packed;
+
+struct als_feature_report {
+	/* Common properties */
+	uint8_t connection_type;
+	uint8_t reporting_state;
+	uint8_t power_state;
+	uint8_t sensor_state;
+	uint32_t report_interval;
+
+	/* Properties specific to this sensor */
+	uint16_t sensitivity;
+	uint16_t maximum;
+	uint16_t minimum;
+} __packed;
+
+
+#ifdef CONFIG_BOARD_AZALEA
+
+static struct radio_report radio_button;
+static struct consumer_button_report consumer_button;
+/* HID input report descriptor
+ *
+ * For a complete reference, please see the following docs on usb.org
+ *
+ * 1. Device Class Definition for HID
+ * 2. HID Usage Tables
+ */
+
+static const uint8_t keyboard_report_desc[] = {
+	/* Airplane Radio Collection */
+	0x05, 0x01,		/* USAGE_PAGE (Generic Desktop) */
+	0x09, 0x0C,		/* USAGE (Wireless Radio Controls) */
+	0xA1, 0x01,		/* COLLECTION (Application) */
+	0x85, REPORT_ID_RADIO,	/* Report ID (Radio) */
+	0x15, 0x00,		/* LOGICAL_MINIMUM (0) */
+	0x25, 0x01,		/* LOGICAL_MAXIMUM (1) */
+	0x09, 0xC6,		/* USAGE (Wireless Radio Button) */
+	0x95, 0x01,		/* REPORT_COUNT (1) */
+	0x75, 0x01,		/* REPORT_SIZE (1) */
+	0x81, 0x06,		/* INPUT (Data,Var,Rel) */
+	0x75, 0x07,		/* REPORT_SIZE (7) */
+	0x81, 0x03,		/* INPUT (Cnst,Var,Abs) */
+	0xC0,			/* END_COLLECTION */
+
+	/* Consumer controls collection */
+	0x05, 0x0C,		/* USAGE_PAGE (Consumer Devices) */
+	0x09, 0x01,		/* USAGE (Consumer Control) */
+	0xA1, 0x01,		/* COLLECTION (Application) */
+	0x85, REPORT_ID_CONSUMER,	/* Report ID (Consumer) */
+	0x15, 0x00,		/* LOGICAL_MINIMUM (0x0) */
+	0x26, 0xFF, 0x03,	/* LOGICAL_MAXIMUM (0x3FF) */
+	0x19, 0x00,		/* Usage Minimum (0) */
+	0x2A, 0xFF, 0x03,	/* Usage Maximum (0) */
+	0x75, 0x10,		/* Report Size (16) */
+	0x95, 0x01,		/* Report Count (1) */
+	0x81, 0x00,		/* Input (Data,Arr,Abs) */
+	0xC0,			/* END_COLLECTION */
+};
+
+static struct i2c_hid_descriptor keyboard_hid_desc = {
+	.wHIDDescLength = I2C_HID_DESC_LENGTH,
+	.bcdVersion = I2C_HID_BCD_VERSION,
+	.wReportDescLength = sizeof(keyboard_report_desc),
+	.wReportDescRegister = I2C_HID_REPORT_DESC_REGISTER,
+	.wInputRegister = I2C_HID_INPUT_REPORT_REGISTER,
+	/*Note if there are multiple reports wMaxInputLength has to be max*/
+	.wMaxInputLength = I2C_HID_HEADER_SIZE +
+			   sizeof(struct consumer_button_report),
+	.wOutputRegister = 0,
+	.wMaxOutputLength = 0,
+	.wCommandRegister = I2C_HID_COMMAND_REGISTER,
+	.wDataRegister = I2C_HID_DATA_REGISTER,
+	.wVendorID = I2C_HID_MEDIAKEYS_VENDOR_ID,
+	.wProductID = I2C_HID_MEDIAKEYS_PRODUCT_ID,
+	.wVersionID = I2C_HID_MEDIAKEYS_FW_VERSION,
+};
+
+#endif
+
+
+static struct als_input_report als_sensor;
+static struct als_feature_report als_feature;
+
+static const uint8_t als_report_desc[] = {
+
+	/* Sensor controls collection */
+	0x05, 0x20,		/* USAGE_PAGE (sensor) */
+	0x09, 0x41,		/* USAGE ID (Light: Ambient Light) */
+	0xA1, 0x00,		/* COLLECTION (Physical) */
+	0x85, REPORT_ID_SENSOR,	/* Report ID (Sensor) */
+
+	0x05, 0x20,		/* USAGE PAGE (Sensor) */
+	0x0A, 0x09, 0x03,	/* USAGE ID (Property: Sensor Connection Type) */
+	0x15, 0x00,		/* LOGICAL_MINIMUN (0x00) */
+	0x25, 0x02,		/* LOGICAL_MAXIMUM (0x02) */
+	0x75, 0x08,		/* Report Size (8) */
+	0x95, 0x01,		/* Report Count (1) */
+	0xA1, 0x02,		/* COLLECTION (logical) */
+	0x0A, 0x30, 0x08,	/* Connection Type: PC Integrated */
+	0x0A, 0x31, 0x08,	/* Connection Type: PC Attached */
+	0x0A, 0x32, 0x08,	/* Connection Type: PC External */
+	0xB1, 0x00,		/* Feature (Data,Arr,Abs) */
+	0xC0,			/* END_COLLECTION */
+
+	0x0A, 0x16, 0x03,	/* USAGE ID (Property: Reporting State) */
+	0x15, 0x00,		/* LOGICAL_MINIMUN (0x00) */
+	0x25, 0x05,		/* LOGICAL_MAXIMUM (0x05) */
+	0x75, 0x08,		/* Report Size (8) */
+	0x95, 0x01,		/* Report Count (1) */
+	0xA1, 0x02,		/* COLLECTION (logical) */
+	0x0A, 0x40, 0x08,	/* Reporting State: Report No Events */
+	0x0A, 0x41, 0x08,	/* Reporting State: Report All Events */
+	0x0A, 0x42, 0x08,	/* Reporting State: Report Threshold Events */
+	0x0A, 0x43, 0x08,	/* Reporting State: Wake On No Events */
+	0x0A, 0x44, 0x08,	/* Reporting State: Wake On All Events */
+	0x0A, 0x45, 0x08,	/* Reporting State: Wake On Threshold Events */
+	0xB1, 0x00,		/* Feature (Data,Arr,Abs) */
+	0xC0,			/* END_COLLECTION */
+
+	0x0A, 0x19, 0x03,	/* USAGE ID (Property: Power State Undefined Select) */
+	0x15, 0x00,		/* LOGICAL_MINIMUN (0x00) */
+	0x25, 0x05,		/* LOGICAL_MAXIMUM (0x05) */
+	0x75, 0x08,		/* Report Size (8) */
+	0x95, 0x01,		/* Report Count (1) */
+	0xA1, 0x02,		/* COLLECTION (logical) */
+	0x0A, 0x50, 0x08,	/* Power State: Undefined */
+	0x0A, 0x51, 0x08,	/* Power State: D0 Full Power */
+	0x0A, 0x52, 0x08,	/* Power State: D1 Low Power */
+	0x0A, 0x53, 0x08,	/* Power State: D2 Standby Power with Wakeup */
+	0x0A, 0x54, 0x08,	/* Power State: D3 sleep with Wakeup */
+	0x0A, 0x55, 0x08,	/* Power State: D4 Power Off */
+	0xB1, 0x00,		/* Feature (Data,Arr,Abs) */
+	0xC0,			/* END_COLLECTION */
+
+	0x0A, 0x01, 0x02,	/* USAGE ID (Event: Sensor State) */
+	0x15, 0x00,		/* LOGICAL_MINIMUN (0x00) */
+	0x25, 0x06,		/* LOGICAL_MAXIMUM (0x06) */
+	0x75, 0x08,		/* Report Size (8) */
+	0x95, 0x01,		/* Report Count (1) */
+	0xA1, 0x02,		/* COLLECTION (logical) */
+	0x0A, 0x00, 0x08,	/* Sensor State: Undefined */
+	0x0A, 0x01, 0x08,	/* Sensor State: Ready */
+	0x0A, 0x02, 0x08,	/* Sensor State: Not Available */
+	0x0A, 0x03, 0x08,	/* Sensor State: No Data */
+	0x0A, 0x04, 0x08,	/* Sensor State: Initializing */
+	0x0A, 0x05, 0x08,	/* Sensor State: Access Denied */
+	0x0A, 0x06, 0x08,	/* Sensor State: Error */
+	0xB1, 0x00,		/* Feature (Data,Arr,Abs) */
+	0xC0,			/* END_COLLECTION */
+
+	0x0A, 0x0E, 0x03,	/* USAGE ID (Property: Report Interval) */
+	0x15, 0x00,		/* LOGICAL_MINIMUN (0x00) */
+	0x27, 0xFF, 0xFF, 0xFF, 0XFF,	/* LOGICAL_MAXIMUM (0xFFFFFFFF) */
+	0x75, 0x20,		/* Report Size (32) */
+	0x95, 0x01,		/* Report Count (1) */
+	0x55, 0x00,		/* UNIT EXPONENT (0x00) */
+	0xB1, 0x02,		/* Feature (Data,Var,Abs) */
+
+	0x0A, 0xD1, 0xE4,	/* USAGE ID (Modified Change Sensitivity Percent of Range) */
+	0x15, 0x00,		/* LOGICAL_MINIMUN (0x00) */
+	0x26, 0x10, 0x27,	/* LOGICAL_MAXIMUM (0x2710) */
+	0x75, 0x10,		/* Report Size (16) */
+	0x95, 0x01,		/* Report Count (1) */
+	0x55, 0x0E,		/* UNIT EXPONENT (0x0E 0.01) */
+	0xB1, 0x02,		/* Feature (Data,Var,Abs) */
+
+	0x0A, 0xD1, 0x24,	/* USAGE ID (Modified Maximum) */
+	0x15, 0x00,		/* LOGICAL_MINIMUN (0x00) */
+	0x26, 0xFF, 0xFF,	/* LOGICAL_MAXIMUM (0xFFFF) */
+	0x75, 0x10,		/* Report Size (16) */
+	0x95, 0x01,		/* Report Count (1) */
+	0x55, 0x00,		/* UNIT EXPONENT (0x00) */
+	0xB1, 0x02,		/* Feature (Data,Var,Abs) */
+
+	0x0A, 0xD1, 0x34,	/* USAGE ID (Modified Minimum) */
+	0x15, 0x00,		/* LOGICAL_MINIMUN (0x00) */
+	0x26, 0xFF, 0xFF,	/* LOGICAL_MAXIMUM (0xFFFF) */
+	0x75, 0x10,		/* Report Size (16) */
+	0x95, 0x01,		/* Report Count (1) */
+	0x55, 0x00,		/* UNIT EXPONENT (0x00) */
+	0xB1, 0x02,		/* Feature (Data,Var,Abs) */
+
+	0x05, 0x20,		/* USAGE PAGE (Sensor) */
+	0x0A, 0x01, 0x02,	/* USAGE ID (Event: Sensor State) */
+	0x15, 0x00,		/* LOGICAL_MINIMUN (0x00) */
+	0x25, 0x06,		/* LOGICAL_MAXIMUM (0x06) */
+	0x75, 0x08,		/* Report Size (8) */
+	0x95, 0x01,		/* Report Count (1) */
+	0xA1, 0x02,		/* COLLECTION (logical) */
+	0x0A, 0x00, 0x08,	/* Sensor State: Undefined */
+	0x0A, 0x01, 0x08,	/* Sensor State: Ready */
+	0x0A, 0x02, 0x08,	/* Sensor State: Not Available */
+	0x0A, 0x03, 0x08,	/* Sensor State: No Data */
+	0x0A, 0x04, 0x08,	/* Sensor State: Initializing */
+	0x0A, 0x05, 0x08,	/* Sensor State: Access Denied */
+	0x0A, 0x06, 0x08,	/* Sensor State: Error */
+	0x81, 0x00,		/* Input (Data,Arr,Abs) */
+	0xC0,			/* END_COLLECTION */
+
+	0x0A, 0x02, 0x02,	/* USAGE (Sensor event) */
+	0x15, 0x00,		/* LOGICAL_MINIMUN (0x00) */
+	0x25, 0x05,		/* LOGICAL_MAXIMUM (0x05) */
+	0x75, 0x08,		/* Report Size (8) */
+	0x95, 0x01,		/* Report Count (1) */
+	0xA1, 0x02,		/* COLLECTION (logical) */
+	0x0A, 0x10, 0x08,	/* Sensor Event: Unknown */
+	0x0A, 0x11, 0x08,	/* Sensor Event: State Changed */
+	0x0A, 0x12, 0x08,	/* Sensor Event: Property Changed */
+	0x0A, 0x13, 0x08,	/* Sensor Event: Data Updated */
+	0x0A, 0x14, 0x08,	/* Sensor Event: Poll Response */
+	0x0A, 0x15, 0x08,	/* Sensor Event: Change Sensitivity */
+	0x81, 0x00,		/* Input (Data,Arr,Abs) */
+	0xC0,			/* END_COLLECTION */
+
+	0x0A, 0xD1, 0x04,	/* USAGE (Data Field: Illuminance) */
+	0x15, 0x00,		/* LOGICAL_MINIMUN (0x00) */
+	0x26, 0xFF, 0xFF,	/* LOGICAL_MAXIMUM (0XFFFF) */
+	0x55, ALS_HID_UNIT,		/* UNIT EXPONENT (0x00) */
+	0x75, 0x10,		/* Report Size (16) */
+	0x95, 0x01,		/* Report Count (1) */
+	0x81, 0x02,		/* Input (Data,Arr,Abs) */
+	0xC0,			/* END_COLLECTION */
+};
+
+
+
+
+static struct i2c_hid_descriptor als_hid_desc = {
+	.wHIDDescLength = I2C_HID_DESC_LENGTH,
+	.bcdVersion = I2C_HID_BCD_VERSION,
+	.wReportDescLength = sizeof(als_report_desc),
+	.wReportDescRegister = I2C_HID_REPORT_DESC_REGISTER,
+	.wInputRegister = I2C_HID_INPUT_REPORT_REGISTER,
+	/*Note if there are multiple reports wMaxInputLength has to be max*/
+	.wMaxInputLength = I2C_HID_HEADER_SIZE +
+			   sizeof(struct als_input_report),
+	.wOutputRegister = 0,
+	.wMaxOutputLength = 0,
+	.wCommandRegister = I2C_HID_COMMAND_REGISTER,
+	.wDataRegister = I2C_HID_DATA_REGISTER,
+	.wVendorID = I2C_HID_MEDIAKEYS_VENDOR_ID,
+	.wProductID = I2C_HID_ALS_PRODUCT_ID,
+	.wVersionID = I2C_HID_MEDIAKEYS_FW_VERSION,
+};
+
+struct i2c_hid_target_data {
+	struct i2c_target_config config;
+	uint32_t buffer_size;
+	uint8_t *buffer;
+	uint32_t buffer_idx;
+	size_t write_idx;
+	uint16_t target_register;
+	uint8_t command;
+	uint8_t power_state;
+	uint8_t report_id;
+	uint8_t report_type;
+	const struct gpio_dt_spec *alert_gpio;
+	const uint8_t *report_descriptor;
+	size_t report_descriptor_size;
+	const struct i2c_hid_descriptor *descriptor;
+	size_t descriptor_size;
+};
+
+struct i2c_hid_target_config {
+	struct i2c_dt_spec bus;
+	uint32_t buffer_size;
+	uint8_t *buffer;
+	struct gpio_dt_spec alert_gpio;
+	const uint8_t *report_descriptor;
+	size_t report_descriptor_size;
+	const struct i2c_hid_descriptor *descriptor;
+	size_t descriptor_size;
+
+
+};
+#ifdef CONFIG_BOARD_AZALEA
+void irq_keyboard(void)
+{
+	const struct device *dev = DEVICE_DT_GET(DT_NODELABEL(i2chid0));
+	struct i2c_hid_target_data *data = dev->data;
+
+	gpio_pin_set_dt(data->alert_gpio, 0);
+}
+
+void hid_consumer(uint16_t  id, bool pressed)
+{
+	const struct device *dev = DEVICE_DT_GET(DT_NODELABEL(i2chid0));
+	struct i2c_hid_target_data *data = dev->data;
+
+	data->report_id = REPORT_ID_CONSUMER;
+	if (pressed) {
+		consumer_button.button_id = id;
+	} else {
+		consumer_button.button_id = 0;
+	}
+
+	irq_keyboard();
+}
+void hid_airplane(bool pressed)
+{
+	const struct device *dev = DEVICE_DT_GET(DT_NODELABEL(i2chid0));
+	struct i2c_hid_target_data *data = dev->data;
+
+	data->report_id = REPORT_ID_RADIO;
+	radio_button.state = pressed;
+	if (pressed)
+		irq_keyboard();
+}
+#endif
+
+
+static void hid_target_als_irq(void)
+{
+	const struct device *dev = DEVICE_DT_GET(DT_NODELABEL(i2chid1));
+	struct i2c_hid_target_data *data = dev->data;
+
+	data->report_id = REPORT_ID_SENSOR;
+	gpio_pin_set_dt(data->alert_gpio, 0);
+}
+
+void i2c_hid_als_init(void)
+{
+	als_feature.connection_type = HID_INTEGRATED;
+	als_feature.reporting_state = HID_NO_EVENTS;
+	als_feature.power_state = HID_D0_FULL_POWER;
+	als_feature.sensor_state = HID_READY;
+	als_feature.report_interval = HID_ALS_REPORT_INTERVAL;
+	als_feature.sensitivity = HID_ALS_SENSITIVITY;
+	als_feature.maximum = HID_ALS_MAX;
+	als_feature.minimum = HID_ALS_MIN;
+
+	als_sensor.event_type = HID_DATA_UPDATED;
+	als_sensor.sensor_state = HID_READY;
+	als_sensor.illuminanceValue = 0x0000;
+}
+DECLARE_HOOK(HOOK_INIT, i2c_hid_als_init, HOOK_PRIO_DEFAULT);
+
+void report_illuminance_value(void);
+DECLARE_DEFERRED(report_illuminance_value);
+void report_illuminance_value(void)
+{
+	uint16_t newIlluminaceValue = *(uint16_t *)host_get_memmap(EC_MEMMAP_ALS);
+	int granularity = als_feature.sensitivity * als_sensor.illuminanceValue / 10000;
+	uint32_t report_interval = als_feature.report_interval;
+	switch (als_feature.reporting_state) {
+	/* we did not implement threshold reporting in our HID descriptor */
+	case HID_THRESHOLD_EVENTS:
+	case HID_THRESHOLD_EVENTS_WAKE:
+	case HID_ALL_EVENTS:
+	case HID_ALL_EVENTS_WAKE:
+		if (ABS(als_sensor.illuminanceValue - newIlluminaceValue) > granularity) {
+			als_sensor.illuminanceValue = newIlluminaceValue;
+			als_sensor.event_type = HID_DATA_UPDATED;
+			hid_target_als_irq();
+		}
+		break;
+	default:
+		break;
+	}
+
+	if (report_interval == 0) {
+		/* per hid spec report interval should be sensor default when 0 */
+		report_interval = HID_ALS_REPORT_INTERVAL;
+	}
+	hook_call_deferred(&report_illuminance_value_data,
+		report_interval * MSEC);
+
+}
+
+
+static void als_report_control(uint8_t report_mode)
+{
+	if (report_mode) {
+		hook_call_deferred(&report_illuminance_value_data,
+			((int) als_feature.report_interval) * MSEC);
+	} else {
+		/* stop report als value */
+		hook_call_deferred(&report_illuminance_value_data, -1);
+	}
+}
+
+
+
+static void als_shutdown(void)
+{
+	const struct device *dev = DEVICE_DT_GET(DT_NODELABEL(i2chid1));
+	struct i2c_hid_target_data *data = dev->data;
+
+	als_feature.power_state = HID_D4_POWER_OFF;
+
+	als_report_control(ALS_REPORT_STOP);
+
+	gpio_pin_set_dt(data->alert_gpio, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, als_shutdown, HOOK_PRIO_DEFAULT);
+
+static void extract_report(size_t len, const uint8_t *buffer, void *data,
+			   size_t data_len)
+{
+	if (len != 7 + data_len) {
+		return;
+	}
+	memcpy(data, buffer + 7, data_len);
+}
+
+static size_t fill_report(uint8_t *buffer, uint8_t report_id, const void *data,
+			  size_t data_len)
+{
+	size_t response_len = I2C_HID_HEADER_SIZE + data_len;
+
+	buffer[0] = response_len & 0xFF;
+	buffer[1] = (response_len >> 8) & 0xFF;
+	buffer[2] = report_id;
+	memcpy(buffer + I2C_HID_HEADER_SIZE, data, data_len);
+	return response_len;
+}
+
+static int hid_target_write_requested(struct i2c_target_config *config)
+{
+	struct i2c_hid_target_data *data = CONTAINER_OF(config,
+						struct i2c_hid_target_data,
+						config);
+
+	data->write_idx = 0;
+	data->target_register = 0;
+	data->buffer_idx = 0;
+
+	return 0;
+}
+
+static int hid_target_write_received(struct i2c_target_config *config,
+				       uint8_t val)
+{
+	struct i2c_hid_target_data *data = CONTAINER_OF(config,
+						struct i2c_hid_target_data,
+						config);
+	int ret = 0;
+
+	/* In case hid wants to be R/O, return !0 here could trigger
+	 * a NACK to the I2C controller, support depends on the
+	 * I2C controller support
+	 */
+
+	if (data->write_idx < 2) {
+		data->target_register |= val << (data->write_idx * 8);
+		data->write_idx++;
+	} else {
+		if (data->buffer_idx < data->buffer_size)
+			data->buffer[data->buffer_idx++] = val;
+		else {
+			ret = -ENOBUFS;
+		}
+	}
+
+	return ret;
+}
+
+static int hid_target_process_write(struct i2c_target_config *config)
+{
+	struct i2c_hid_target_data *data = CONTAINER_OF(config,
+						struct i2c_hid_target_data,
+						config);
+
+	uint8_t command = data->buffer[1] & 0x0F;
+	uint8_t power_state = data->buffer[0] & 0x03;
+	uint8_t report_id = data->buffer[0] & 0x0F;
+	uint8_t report_type = (data->buffer[0] & 0x30) >> 4;
+	size_t response_size = 0;
+
+	switch (command) {
+	case I2C_HID_CMD_RESET:
+		data->report_id = 0;
+		gpio_pin_set_dt(data->alert_gpio, 0);
+		break;
+	case I2C_HID_CMD_GET_REPORT:
+		data->report_id = report_id;
+#ifdef CONFIG_BOARD_LOTUS
+		if (data->descriptor->wCommandRegister == I2C_TOUCHPAD_HID_COMMAND_REGISTER) {
+			switch (report_id) {
+			case 2:
+				static const uint8_t touchpad_feature_2[] = {0x04, 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x00};
+				memcpy(data->buffer, touchpad_feature_2, sizeof(touchpad_feature_2));
+				break;
+			default:
+				memset(data->buffer, 0, data->buffer_size);
+				break;
+			}
+		} else
+#endif /* CONFIG_BOARD_LOTUS */
+		{
+			switch (report_id) {
+	#ifdef CONFIG_BOARD_AZALEA
+			case REPORT_ID_RADIO:
+					response_size = fill_report(data->buffer, report_id,
+							&radio_button,
+							sizeof(struct radio_report));
+				break;
+			case REPORT_ID_CONSUMER:
+					response_size = fill_report(data->buffer, report_id,
+							&consumer_button,
+							sizeof(struct consumer_button_report));
+				break;
+	#endif
+			case REPORT_ID_SENSOR:
+				if (report_type == 0x01) {
+					als_sensor.event_type = HID_POLL_RESPONSE;
+					response_size = fill_report(data->buffer, report_id,
+						&als_sensor,
+						sizeof(struct als_input_report));
+				} else if (report_type == 0x03) {
+					response_size = fill_report(data->buffer, report_id,
+						&als_feature,
+						sizeof(struct als_feature_report));
+				}
+				break;
+			default:
+				response_size = fill_report(data->buffer, 0,
+					NULL,
+					0);
+				break;
+			}
+		}
+		break;
+	case I2C_HID_CMD_SET_REPORT:
+		switch (report_id) {
+		case REPORT_ID_SENSOR:
+			extract_report(data->buffer_idx,
+						data->buffer,
+						&als_feature,
+						sizeof(struct als_feature_report));
+			if (als_feature.power_state == HID_D4_POWER_OFF) {
+				als_shutdown();
+			} else {
+				als_report_control(ALS_REPORT_POLLING);
+			}
+			break;
+		default:
+			break;
+		}
+		break;
+	case I2C_HID_CMD_SET_POWER:
+		/*
+		 * Return the power setting so the user can actually set the
+		 * touch controller's power state in board level.
+		 */
+		*data->buffer = power_state;
+
+		if (power_state == 0x00) {
+			i2c_hid_als_init();
+			als_report_control(ALS_REPORT_POLLING);
+		} else
+			als_shutdown();
+
+		break;
+	default:
+
+	}
+	return 0;
+}
+
+
+static int hid_target_read_processed(struct i2c_target_config *config,
+				       uint8_t *val)
+{
+	struct i2c_hid_target_data *data = CONTAINER_OF(config,
+						struct i2c_hid_target_data,
+						config);
+	uint16_t target_register = 0;
+	int ret = 0;
+
+	if (data->write_idx) {
+		target_register = data->target_register;
+	}
+
+	switch (target_register) {
+#ifdef CONFIG_BOARD_LOTUS
+	case I2C_TOUCHPAD_HID_DESC_REGISTER:
+#endif
+	case I2C_HID_MEDIAKEYS_HID_DESC_REGISTER:
+		if (data->buffer_idx < data->descriptor_size) {
+			*val = ((uint8_t *)data->descriptor)[data->buffer_idx++];
+		} else {
+			ret = -ENOBUFS;
+		}
+		break;
+#ifdef CONFIG_BOARD_LOTUS
+	case I2C_TOUCHPAD_HID_REPORT_DESC_REGISTER:
+#endif
+	case I2C_HID_REPORT_DESC_REGISTER:
+		if (data->buffer_idx < data->report_descriptor_size) {
+			*val = data->report_descriptor[data->buffer_idx++];
+		} else {
+			ret = -ENOBUFS;
+		}
+		break;
+
+	default:
+		/* Other registers are populated in the write rx*/
+		if (data->buffer_idx < data->buffer_size)
+			*val = data->buffer[data->buffer_idx++];
+		else {
+			*val = 0;
+		}
+	}
+	/* Increment will be done in the next read_processed callback
+	 * In case of STOP, the byte won't be taken in account
+	 */
+
+	return ret;
+}
+
+
+
+
+/* Called on first read */
+static int hid_target_read_requested(struct i2c_target_config *config,
+				       uint8_t *val)
+{
+	struct i2c_hid_target_data *data = CONTAINER_OF(config,
+						struct i2c_hid_target_data,
+						config);
+	uint16_t target_register;
+
+	gpio_pin_set_dt(data->alert_gpio, 1);
+
+	if (data->write_idx) {
+		target_register = data->target_register;
+
+	} else {
+		target_register = I2C_HID_INPUT_REPORT_REGISTER;
+	}
+
+	if (target_register == I2C_HID_COMMAND_REGISTER
+#ifdef CONFIG_BOARD_LOTUS
+		|| target_register == I2C_TOUCHPAD_HID_COMMAND_REGISTER
+#endif
+		)
+	{
+		if (data->buffer_idx) {
+			hid_target_process_write(config);
+			data->buffer_idx = 0;
+		}
+	} else if (target_register == I2C_HID_INPUT_REPORT_REGISTER) {
+		/* Common input report requests. */
+		switch (data->report_id) {
+#ifdef CONFIG_BOARD_AZALEA
+		case REPORT_ID_RADIO:
+			fill_report(data->buffer, REPORT_ID_RADIO,
+					&radio_button,
+					sizeof(struct radio_report));
+			radio_button.state = 0;
+			break;
+		case REPORT_ID_CONSUMER:
+			fill_report(data->buffer, REPORT_ID_CONSUMER,
+					&consumer_button,
+					sizeof(struct consumer_button_report));
+			break;
+#endif
+		case REPORT_ID_SENSOR:
+			fill_report(data->buffer, REPORT_ID_SENSOR,
+					&als_sensor,
+					sizeof(struct als_input_report));
+			break;
+		default:
+			/* issue reset protocol */
+			data->report_id = 0;
+			memset(data->buffer, 0, data->descriptor->wMaxInputLength);
+			break;
+		}
+	}
+
+	return hid_target_read_processed(config, val);
+}
+
+
+static int cmd_hidals_status(int argc, const char **argv)
+{
+	int i;
+	char *e;
+
+	if (argc == 2) {
+		i = strtoi(argv[1], &e, 0);
+		if (*e)
+			return EC_ERROR_PARAM1;
+		als_sensor.illuminanceValue = i;
+		als_sensor.event_type = HID_DATA_UPDATED;
+		hid_target_als_irq();
+	}
+
+	ccprintf("ALS Feature\n");
+	ccprintf(" report_state:%d\n", als_feature.reporting_state);
+	ccprintf(" Power:%d\n", als_feature.power_state);
+	ccprintf(" Sensor:%d\n", als_feature.sensor_state);
+	ccprintf(" Interval:%dms\n", als_feature.report_interval);
+	ccprintf(" sensitivity:%d\n", als_feature.sensitivity);
+	ccprintf(" illuminance:%d\n", als_sensor.illuminanceValue);
+
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(hidals, cmd_hidals_status, "[lux]",
+			"Get als device status");
+
+static int hid_target_stop(struct i2c_target_config *config)
+{
+	struct i2c_hid_target_data *data = CONTAINER_OF(config,
+						struct i2c_hid_target_data,
+						config);
+
+	/* Clear the interrupt when we have processed the packet */
+	gpio_pin_set_dt(data->alert_gpio, 1);
+
+	if (data->target_register == I2C_HID_COMMAND_REGISTER
+#ifdef CONFIG_BOARD_LOTUS
+		|| data->target_register == I2C_TOUCHPAD_HID_COMMAND_REGISTER
+#endif
+	) {
+		if (data->buffer_idx) {
+			hid_target_process_write(config);
+		}
+	}
+
+	data->write_idx = 0;
+	data->target_register = 0;
+	data->buffer_idx = 0;
+
+	return 0;
+}
+
+int hid_target_register(const struct device *dev)
+{
+	const struct i2c_hid_target_config *cfg = dev->config;
+	struct i2c_hid_target_data *data = dev->data;
+
+	return i2c_target_register(cfg->bus.bus, &data->config);
+}
+
+int hid_target_unregister(const struct device *dev)
+{
+	const struct i2c_hid_target_config *cfg = dev->config;
+	struct i2c_hid_target_data *data = dev->data;
+
+	return i2c_target_unregister(cfg->bus.bus, &data->config);
+}
+
+static const struct i2c_target_driver_api api_funcs = {
+	.driver_register = hid_target_register,
+	.driver_unregister = hid_target_unregister,
+};
+
+static const struct i2c_target_callbacks hid_callbacks = {
+	.write_requested = hid_target_write_requested,
+	.read_requested = hid_target_read_requested,
+	.write_received = hid_target_write_received,
+	.read_processed = hid_target_read_processed,
+	.stop = hid_target_stop,
+};
+
+static int i2c_hid_target_init(const struct device *dev)
+{
+	struct i2c_hid_target_data *data = dev->data;
+	const struct i2c_hid_target_config *cfg = dev->config;
+
+	if (!device_is_ready(cfg->bus.bus)) {
+		return -ENODEV;
+	}
+
+	data->buffer_size = cfg->buffer_size;
+	data->buffer = cfg->buffer;
+	data->config.address = cfg->bus.addr;
+	data->config.callbacks = &hid_callbacks;
+	data->alert_gpio = &cfg->alert_gpio;
+	data->report_descriptor = cfg->report_descriptor;
+	data->report_descriptor_size = cfg->report_descriptor_size;
+	data->descriptor = cfg->descriptor;
+	data->descriptor_size = cfg->descriptor_size;
+	data->report_id = 0;
+
+	als_report_control(ALS_REPORT_STOP);
+	return 0;
+}
+
+
+#define I2C_HID_INIT(inst)						\
+	static struct i2c_hid_target_data				\
+		i2c_hid_target_##inst##_dev_data;			\
+									\
+	static uint8_t							\
+	i2c_hid_target_##inst##_buffer[(DT_INST_PROP(inst, max_report_size))];	\
+									\
+	static const struct i2c_hid_target_config			\
+		i2c_hid_target_##inst##_cfg = {			\
+		.bus = I2C_DT_SPEC_INST_GET(inst),			\
+		.buffer_size = DT_INST_PROP(inst, max_report_size),		\
+		.buffer = i2c_hid_target_##inst##_buffer,		\
+		.alert_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, alert_gpios, {}),		\
+		.report_descriptor = DT_INST_STRING_TOKEN(inst, hid_report_descriptor),		\
+		.report_descriptor_size = sizeof(DT_INST_STRING_TOKEN(inst, hid_report_descriptor)),		\
+		.descriptor = &DT_INST_STRING_TOKEN(inst, hid_descriptor),		\
+		.descriptor_size = sizeof(DT_INST_STRING_TOKEN(inst, hid_descriptor))		\
+	};								\
+	static void i2c_hid_##inst##_init(void) \
+	{	\
+			i2c_target_driver_register(DEVICE_DT_INST_GET(inst));	\
+	}	\
+	DECLARE_HOOK(HOOK_INIT, i2c_hid_##inst##_init, HOOK_PRIO_DEFAULT);	\
+									\
+	DEVICE_DT_INST_DEFINE(inst,					\
+			    &i2c_hid_target_init,			\
+			    NULL,			\
+			    &i2c_hid_target_##inst##_dev_data,	\
+			    &i2c_hid_target_##inst##_cfg,		\
+			    POST_KERNEL,				\
+			    CONFIG_I2C_TARGET_INIT_PRIORITY,		\
+			    &api_funcs);
+
+DT_INST_FOREACH_STATUS_OKAY(I2C_HID_INIT)
diff --git a/zephyr/program/framework/src/led.c b/zephyr/program/framework/src/led.c
new file mode 100644
index 0000000000..86c9605ab1
--- /dev/null
+++ b/zephyr/program/framework/src/led.c
@@ -0,0 +1,629 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power and battery LED control.
+ */
+
+#define DT_DRV_COMPAT cros_ec_led_policy
+
+#include <stdint.h>
+
+#include "battery.h"
+#include "board_led.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "chipset.h"
+#include "ec_commands.h"
+#include "extpower.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "led.h"
+#include "led_common.h"
+#include "power.h"
+#include "power_sequence.h"
+#include "system.h"
+#include "util.h"
+
+#include "board_function.h"
+#include "cypress_pd_common.h"
+#include "diagnostics.h"
+#include "lid_switch.h"
+
+#ifdef CONFIG_BOARD_LOTUS
+#include "gpu.h"
+#include "input_module.h"
+#endif
+
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(led, LOG_LEVEL_ERR);
+
+BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
+	     "Exactly one instance of cros-ec,led-policy should be defined.");
+
+#define LED_COLOR_NODE DT_PATH(led_colors)
+
+#define BOARD_LED_PWM_PERIOD_NS BOARD_LED_HZ_TO_PERIOD_NS(324)
+
+struct led_color_node_t {
+	struct led_pins_node_t *pins_node;
+	int acc_period;
+};
+
+enum breath_status {
+	BREATH_LIGHT_UP = 0,
+	BREATH_LIGHT_DOWN,
+	BREATH_HOLD,
+	BREATH_OFF,
+};
+
+#define DECLARE_PINS_NODE(id) extern struct led_pins_node_t PINS_NODE(id);
+
+DT_FOREACH_CHILD_STATUS_OKAY_VARGS(
+	DT_COMPAT_GET_ANY_STATUS_OKAY(cros_ec_pwm_led_pins), DT_FOREACH_CHILD,
+	DECLARE_PINS_NODE)
+
+/*
+ * Currently 4 different colors are supported for blinking LED, each of which
+ * can have different periods. Each period slot is the accumulation of previous
+ * periods as described below. Last slot is the total accumulation which is
+ * used as a dividing factor to calculate ticks to switch color
+ * Eg LED_COLOR_1 1 sec, LED_COLOR_2 2 sec, LED_COLOR_3 3 sec, LED_COLOR_4 3 sec
+ * period_1 = 1, period_2 = 1 + 2, period_3 = 1 + 2 + 3, period_4 =1 + 2 + 3 + 3
+ * ticks -> 0, 1, 2, 3, 4, 5, 6, 7, 8, 0, 1, 2 and so on (ticks % 9)
+ * 0 < period_1 -> LED_COLOR_1 for 1 sec
+ * 1, 2 < period_2 -> LED_COLOR_2 for 2 secs
+ * 3, 4, 5 < period_3 -> LED_COLOR_3 for 3 secs
+ * 6, 7, 8 < period_4 -> LED_COLOR_4 for 3 secs
+ */
+#define MAX_COLOR 4
+
+struct node_prop_t {
+	enum led_pwr_state pwr_state;
+	enum power_state chipset_state;
+	int batt_state_mask;
+	int batt_state;
+	int8_t batt_lvl[2];
+	int8_t charge_port;
+	struct led_color_node_t led_colors[MAX_COLOR];
+};
+
+/*
+ * acc_period is the accumulated period value of all color-x children
+ * led_colors[0].acc_period = period value of color-0 node
+ * led_colors[1].acc_period = period value of color-0 + color-1 nodes
+ * led_colors[2].acc_period = period value of color-0 + color-1 + color-2 nodes
+ * and so on. If period prop or color node doesn't exist, period val is 0
+ * It is stored in terms of number of ticks by dividing it with
+ * HOOT_TICK_INTERVAL_MS
+ */
+
+#define PERIOD_VAL(id)                               \
+	COND_CODE_1(DT_NODE_HAS_PROP(id, period_ms), \
+		    (DT_PROP(id, period_ms) / HOOK_TICK_INTERVAL_MS), (0))
+
+#define LED_PERIOD(color_num, state_id) \
+	PERIOD_VAL(DT_CHILD(state_id, color_##color_num))
+
+#define LED_PLUS_PERIOD(color_num, state_id) +LED_PERIOD(color_num, state_id)
+
+#define ACC_PERIOD(color_num, state_id) \
+	(0 LISTIFY(color_num, LED_PLUS_PERIOD, (), state_id))
+
+#define PINS_NODE_ADDR(id) DT_PHANDLE(id, led_color)
+#define LED_COLOR_INIT(color_num, color_num_plus_one, state_id)                \
+	{                                                                      \
+		.pins_node = COND_CODE_1(                                      \
+			DT_NODE_EXISTS(DT_CHILD(state_id, color_##color_num)), \
+			(&PINS_NODE(PINS_NODE_ADDR(                            \
+				DT_CHILD(state_id, color_##color_num)))),      \
+			(NULL)),                                               \
+		.acc_period = ACC_PERIOD(color_num_plus_one, state_id)         \
+	}
+
+/*
+ * Initialize node_array struct with prop listed in dts
+ */
+#define SET_LED_VALUES(state_id)                                              \
+	{ .pwr_state = GET_PROP(state_id, charge_state),                      \
+	  .chipset_state = GET_PROP(state_id, chipset_state),                 \
+	  .batt_state_mask =                                                  \
+		  COND_CODE_1(DT_NODE_HAS_PROP(state_id, batt_state_mask),    \
+			      (DT_PROP(state_id, batt_state_mask)), (-1)),    \
+	  .batt_state = COND_CODE_1(DT_NODE_HAS_PROP(state_id, batt_state),   \
+				    (DT_PROP(state_id, batt_state)), (-1)),   \
+	  .batt_lvl = COND_CODE_1(DT_NODE_HAS_PROP(state_id, batt_lvl),       \
+				  (DT_PROP(state_id, batt_lvl)),              \
+				  ({ -1, -1 })),                              \
+	  .charge_port = COND_CODE_1(DT_NODE_HAS_PROP(state_id, charge_port), \
+				     (DT_PROP(state_id, charge_port)), (-1)), \
+	  .led_colors = {                                                     \
+		  LED_COLOR_INIT(0, 1, state_id),                             \
+		  LED_COLOR_INIT(1, 2, state_id),                             \
+		  LED_COLOR_INIT(2, 3, state_id),                             \
+		  LED_COLOR_INIT(3, 4, state_id),                             \
+	  } },
+
+static const struct node_prop_t node_array[] = { DT_INST_FOREACH_CHILD(
+	0, SET_LED_VALUES) };
+
+test_export_static enum power_state get_chipset_state(void)
+{
+	enum power_state chipset_state = 0;
+
+	/*
+	 * Only covers subset of power states as other states don't
+	 * alter LED behavior
+	 */
+	if (chipset_in_state(CHIPSET_STATE_ON))
+		/* S0 */
+		chipset_state = POWER_S0;
+	else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
+		/* S3 */
+		chipset_state = POWER_S3;
+	else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		/* S5 */
+		chipset_state = POWER_S5;
+
+	return chipset_state;
+}
+
+#define GET_PERIOD(n_idx, c_idx) node_array[n_idx].led_colors[c_idx].acc_period
+#define GET_PIN_NODE(n_idx, c_idx) node_array[n_idx].led_colors[c_idx].pins_node
+
+static void set_color(int node_idx, uint32_t ticks)
+{
+	int color_idx = 0;
+
+	/* If accumulated period value is not 0, it's a blinking LED */
+	if (GET_PERIOD(node_idx, MAX_COLOR - 1) != 0) {
+		/*  Period is accumulated at the last index */
+		ticks = ticks % GET_PERIOD(node_idx, MAX_COLOR - 1);
+	}
+
+	/*
+	 * Period value of 0 indicates solid LED color (non-blinking)
+	 * In case of dual port battery LEDs, period value of 0 is
+	 * also used to turn-off non-active port LED
+	 * Nodes with period value of 0 strictly need to be listed before
+	 * nodes with non-zero period values as we are accumulating the
+	 * period at each node.
+	 *
+	 * TODO: Remove the strict sequence requirement for listing the
+	 * zero-period value nodes.
+	 */
+	for (color_idx = 0; color_idx < MAX_COLOR; color_idx++) {
+		struct led_pins_node_t *pins_node =
+			GET_PIN_NODE(node_idx, color_idx);
+		int period = GET_PERIOD(node_idx, color_idx);
+
+		if (pins_node == NULL)
+			break; /* No more valid color nodes, break here */
+
+		if (!led_auto_control_is_enabled(pins_node->led_id))
+			break; /* Auto control is disabled */
+
+		if (pins_node->led_id == EC_LED_ID_POWER_LED)
+			break; /* Avoid power led control */
+
+		/*
+		 * Period value that we use here is in terms of number
+		 * of ticks stored during initialization of the struct
+		 */
+		if (period == 0)
+			led_set_color_with_node(pins_node);
+		else if (ticks < period) {
+			led_set_color_with_node(pins_node);
+			break;
+		}
+	}
+}
+
+static int match_node(int node_idx)
+{
+	/* Check if this node depends on power state */
+	if (node_array[node_idx].pwr_state != LED_PWRS_UNCHANGE) {
+		enum led_pwr_state pwr_state = led_pwr_get_state();
+		int port = charge_manager_get_active_charge_port();
+
+		if (pwr_state == LED_PWRS_DISCHARGE || pwr_state == LED_PWRS_DISCHARGE_FULL) {
+			gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_right_side), 0);
+			gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_left_side), 0);
+		} else {
+			if (port < 0) {
+				LOG_ERR("Illegal condition, port:%d, pwr:%d", port, pwr_state);
+				return -1;
+			}
+			gpio_pin_set_dt(
+				GPIO_DT_FROM_NODELABEL(gpio_right_side), (port < 2) ? 1 : 0);
+			gpio_pin_set_dt(
+				GPIO_DT_FROM_NODELABEL(gpio_left_side), (port >= 2) ? 1 : 0);
+		}
+
+		if (node_array[node_idx].pwr_state != pwr_state)
+			return -1;
+
+		/* Check if this node depends on charge port */
+		if (node_array[node_idx].charge_port != -1) {
+
+			if (node_array[node_idx].charge_port != port)
+				return -1;
+		}
+	}
+
+	/* Check if this node depends on chipset state */
+	if (node_array[node_idx].chipset_state != 0) {
+		enum power_state chipset_state = get_chipset_state();
+
+		if (node_array[node_idx].chipset_state != chipset_state)
+			return -1;
+	}
+
+	/* check if this node depends on battery status */
+	if (node_array[node_idx].batt_state_mask != -1) {
+		int batt_state;
+
+		battery_status(&batt_state);
+		if ((node_array[node_idx].batt_state_mask & batt_state) !=
+		    (node_array[node_idx].batt_state_mask &
+		     node_array[node_idx].batt_state))
+			return -1;
+	}
+
+	/* Check if this node depends on battery level */
+	if (node_array[node_idx].batt_lvl[0] != -1) {
+		int curr_batt_lvl =
+			DIV_ROUND_NEAREST(get_system_percentage(), 10);
+
+		if ((curr_batt_lvl < node_array[node_idx].batt_lvl[0]) ||
+		    (curr_batt_lvl > node_array[node_idx].batt_lvl[1]))
+			return -1;
+	}
+
+	/* We found the node that matches the current system state */
+	return node_idx;
+}
+
+/* =========== Breath API =========== */
+
+uint8_t breath_led_light_up;
+uint8_t breath_led_light_down;
+uint8_t breath_led_hold;
+uint8_t breath_led_off;
+
+int breath_pwm_enable;
+int breath_led_status;
+static void breath_led_pwm_deferred(void);
+DECLARE_DEFERRED(breath_led_pwm_deferred);
+
+static void multifunction_pwr_leds_control(int *colors, int num_color, int period)
+{
+	static uint32_t ticks;
+	static int idx;
+
+	ticks++;
+
+	if ((ticks * 200) >= period) {
+		ticks = 0;
+		idx++;
+
+		if (idx >= num_color)
+			idx = 0;
+	}
+
+	led_set_color(colors[idx], EC_LED_ID_POWER_LED);
+}
+
+void pwm_set_breath_dt(const struct led_pins_node_t *pins_node, int percent)
+{
+	struct pwm_pin_t *pwm_pins = pins_node->pwm_pins;
+	uint32_t pulse_ns;
+
+	/*
+	 * pulse_ns = (period_ns*duty_cycle_in_perct)/100
+	 * freq = 100 Hz, period_ns = 1000000000/100 = 10000000ns
+	 * duty_cycle = 50 %, pulse_ns  = (10000000*50)/100 = 5000000ns
+	 */
+
+	pulse_ns = DIV_ROUND_NEAREST(BOARD_LED_PWM_PERIOD_NS * percent, 100);
+
+	pwm_set_pulse_dt(&pwm_pins->pwm, pulse_ns);
+}
+
+/*
+ *	Breath LED API
+ *	Max duty (percentage) = BREATH_LIGHT_LENGTH (100%)
+ *	Fade time (second) = 1000ms(In) / 1000ms(Out)
+ *	Duration time (second) = BREATH_HOLD_LENGTH(500ms)
+ *	Interval time (second) = BREATH_OFF_LENGTH(2000ms)
+ */
+static void breath_led_pwm_deferred(void)
+{
+	uint8_t led_hold_length;
+	uint8_t led_duty_percentage;
+	uint8_t bbram_led_level;
+
+#ifdef CONFIG_BOARD_LOTUS
+	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
+		bbram_led_level = FP_LED_LOW;
+	else
+#endif
+		system_get_bbram(SYSTEM_BBRAM_IDX_FP_LED_LEVEL, &bbram_led_level);
+
+	switch (bbram_led_level) {
+	case FP_LED_LOW:
+		led_duty_percentage = FP_LED_LOW;
+		led_hold_length = BREATH_ON_LENGTH_LOW;
+		break;
+	case FP_LED_MEDIUM:
+		led_duty_percentage = FP_LED_MEDIUM;
+		led_hold_length = BREATH_ON_LENGTH_MID;
+		break;
+	case FP_LED_HIGH:
+	default:
+		led_duty_percentage = FP_LED_HIGH;
+		led_hold_length = BREATH_ON_LENGTH_HIGH;
+		break;
+	}
+
+	switch (breath_led_status) {
+	case BREATH_LIGHT_UP:
+
+		if (breath_led_light_up <= led_duty_percentage)
+			pwm_set_breath_dt(GET_PIN_NODE(7, 0), breath_led_light_up++);
+		else {
+			breath_led_light_up = 0;
+			breath_led_light_down = led_duty_percentage;
+			breath_led_status = BREATH_HOLD;
+		}
+
+		break;
+	case BREATH_HOLD:
+
+		if (breath_led_hold <= led_hold_length)
+			breath_led_hold++;
+		else {
+			breath_led_hold = 0;
+			breath_led_status = BREATH_LIGHT_DOWN;
+		}
+
+		break;
+	case BREATH_LIGHT_DOWN:
+
+		if (breath_led_light_down != 0)
+			pwm_set_breath_dt(GET_PIN_NODE(7, 0),
+				     --breath_led_light_down);
+		else {
+			breath_led_light_down = led_duty_percentage;
+			breath_led_status = BREATH_OFF;
+		}
+
+		break;
+	case BREATH_OFF:
+
+		if (breath_led_off <= BREATH_OFF_LENGTH)
+			breath_led_off++;
+		else {
+			breath_led_off = 0;
+			breath_led_status = BREATH_LIGHT_UP;
+		}
+
+		break;
+	}
+
+	if (breath_pwm_enable)
+		hook_call_deferred(&breath_led_pwm_deferred_data, 10 * MSEC);
+}
+
+void breath_led_run(uint8_t enable)
+{
+	if (enable && !breath_pwm_enable) {
+		breath_pwm_enable = true;
+		breath_led_status = BREATH_LIGHT_UP;
+		hook_call_deferred(&breath_led_pwm_deferred_data, 10 * MSEC);
+	} else if (!enable && breath_pwm_enable) {
+		breath_pwm_enable = false;
+		breath_led_light_up = 0;
+		breath_led_light_down = 0;
+		breath_led_hold = 0;
+		breath_led_off = 0;
+		breath_led_status = BREATH_OFF;
+		hook_call_deferred(&breath_led_pwm_deferred_data, -1);
+	}
+}
+
+static void board_led_set_power(void)
+{
+	uint8_t bbram_led_level;
+	int colors[3] = {LED_OFF, LED_OFF, LED_OFF};
+
+	system_get_bbram(SYSTEM_BBRAM_IDX_FP_LED_LEVEL, &bbram_led_level);
+
+	/* turn off led when lid is close*/
+	if (!lid_is_open()) {
+		breath_led_run(0);
+		led_set_color(LED_OFF, EC_LED_ID_POWER_LED);
+		return;
+	}
+
+	if (check_s0ix_status()) {
+		breath_led_run(1);
+		return;
+	}
+
+	breath_led_run(0);
+
+	if (chipset_in_state(CHIPSET_STATE_ON)) {
+		if (charge_get_percent() < 3 && !extpower_is_present()) {
+			colors[0] = LED_WHITE;
+			colors[1] = LED_OFF;
+			colors[2] = LED_OFF;
+			multifunction_pwr_leds_control(colors, 2, 500);
+		} else
+			pwm_set_breath_dt(GET_PIN_NODE(7, 0),
+				bbram_led_level ? bbram_led_level : FP_LED_HIGH);
+	} else
+		led_set_color(LED_OFF, EC_LED_ID_POWER_LED);
+}
+
+static void multifunction_leds_control(int *colors, int num_color, int period)
+{
+	static uint32_t ticks;
+	static int idx;
+
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_right_side), 1);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_left_side), 1);
+
+	ticks++;
+
+	if ((ticks * 200) >= period) {
+		ticks = 0;
+		idx++;
+
+		if (idx >= num_color)
+			idx = 0;
+	}
+
+	led_set_color(colors[idx], EC_LED_ID_BATTERY_LED);
+}
+
+/* =============================== */
+
+static void board_led_set_color(void)
+{
+	static uint32_t ticks;
+	bool found_node = false;
+
+	ticks++;
+
+	/*
+	 * Find all the nodes that match the current state of the system and
+	 * set color for these nodes. Depending on the policy defined in
+	 * led.dts, a node could depend on power-state, chipset-state, extra
+	 * flags like battery percentage etc.
+	 * We must find at least one node that indicates the LED Behavior for
+	 * current system state.
+	 */
+	for (int i = 0; i < ARRAY_SIZE(node_array); i++) {
+		if (match_node(i) != -1) {
+			found_node = true;
+			set_color(i, ticks);
+		}
+	}
+
+	if (!found_node)
+		LOG_ERR("Node with matching prop not found");
+}
+
+/* Called by hook task every HOOK_TICK_INTERVAL_MS */
+static void led_tick(void)
+{
+	int colors[3] = {LED_OFF, LED_OFF, LED_OFF};
+
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		board_led_set_power();
+
+	if (!led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_right_side), 1);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_left_side), 1);
+		return;
+	}
+
+	/* Debug Active */
+	if (diagnostics_tick())
+		return;
+
+	/* Battery disconnect active signal */
+	if (battery_is_cut_off()) {
+		colors[0] = LED_RED;
+		colors[1] = LED_BLUE;
+		colors[2] = LED_OFF;
+#ifdef CONFIG_BOARD_LOTUS
+		multifunction_leds_control(colors, 2, 1000);
+#else
+		multifunction_leds_control(colors, 2, 500);
+#endif
+		return;
+	}
+
+	/* Battery is not present, ignored if in standalone mode */
+	if ((battery_is_present() != BP_YES) && !get_standalone_mode()) {
+		colors[0] = LED_RED;
+		colors[1] = LED_BLUE;
+		colors[2] = LED_OFF;
+#ifdef CONFIG_BOARD_LOTUS
+		multifunction_leds_control(colors, 2, 1000);
+#else
+		multifunction_leds_control(colors, 2, 500);
+#endif
+		return;
+	}
+
+	/* C cover detect switch open */
+	if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_chassis_open_l)) == 0 &&
+		!get_standalone_mode()) {
+		colors[0] = LED_RED;
+		colors[1] = LED_OFF;
+		colors[2] = LED_OFF;
+		multifunction_leds_control(colors, 2, 1000);
+		return;
+	}
+
+#ifdef CONFIG_BOARD_LOTUS
+	/* GPU bay cover detect switch open */
+	if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_f_beam_open_l)) == 0 &&
+		!get_standalone_mode()) {
+		colors[0] = LED_RED;
+		colors[1] = LED_AMBER;
+		colors[2] = LED_OFF;
+		multifunction_leds_control(colors, 3, 1000);
+		return;
+	}
+
+	/* GPU Bay Module Fault */
+	if (gpu_module_fault() && extpower_is_present()) {
+		colors[0] = LED_RED;
+		colors[1] = LED_AMBER;
+		colors[2] = LED_OFF;
+		multifunction_leds_control(colors, 3, 1000);
+		return;
+	}
+
+	/* Input Deck not fully populated */
+	if (!input_deck_is_fully_populated() && !get_standalone_mode() &&
+		!chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
+		colors[0] = LED_RED;
+		colors[1] = LED_BLUE;
+		colors[2] = LED_OFF;
+		multifunction_leds_control(colors, 3, 500);
+		return;
+	}
+#endif
+
+	board_led_set_color();
+}
+DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
+
+void led_control(enum ec_led_id led_id, enum ec_led_state state)
+{
+	enum led_color color;
+
+	if ((led_id != EC_LED_ID_RECOVERY_HW_REINIT_LED) &&
+	    (led_id != EC_LED_ID_SYSRQ_DEBUG_LED))
+		return;
+
+	if (state == LED_STATE_RESET) {
+		led_auto_control(EC_LED_ID_BATTERY_LED, 1);
+		board_led_set_color();
+		return;
+	}
+
+	color = state ? LED_BLUE : LED_OFF;
+
+	led_auto_control(EC_LED_ID_BATTERY_LED, 0);
+
+	led_set_color(color, led_id);
+}
diff --git a/zephyr/program/framework/src/led_pwm.c b/zephyr/program/framework/src/led_pwm.c
new file mode 100644
index 0000000000..a747c3d3b9
--- /dev/null
+++ b/zephyr/program/framework/src/led_pwm.c
@@ -0,0 +1,158 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * PWM LED control.
+ */
+
+#define DT_DRV_COMPAT cros_ec_pwm_led_pins
+
+#include "ec_commands.h"
+#include "led.h"
+#include "util.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/pwm.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(pwm_led, LOG_LEVEL_ERR);
+
+BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
+	     "Exactly one instance of cros-ec,pwm-led-pins should be defined.");
+
+/*
+ * Period in ns from frequency(Hz) defined in pins node
+ * period in sec = 1/freq
+ * period in nsec = (1*nsec_per_sec)/freq
+ * This value is also used calculate duty_cycle in ns (pulse_ns below).
+ * Duty cycle in perct defined in pin node is used to calculate pulse_ns
+ * pulse_ns = (period_ns*duty_cycle_in_perct)/100
+ * e.g. freq = 500 Hz, period_ns = 1000000000/500 = 2000000ns
+ * duty_cycle = 50 %, pulse_ns  = (2000000*50)/100 = 1000000ns
+ */
+
+#define SET_PIN(node_id, prop, i)                                            \
+	{                                                                    \
+		.pwm = PWM_DT_SPEC_GET(                                      \
+			DT_PHANDLE_BY_IDX(DT_PARENT(node_id), led_pwms, i)), \
+		.pulse_ns = DIV_ROUND_NEAREST(                               \
+			DT_PWMS_PERIOD(DT_PHANDLE_BY_IDX(DT_PARENT(node_id), \
+							 led_pwms, i)) *     \
+				DT_PROP_BY_IDX(node_id, prop, i),            \
+			100),                                                \
+	},
+
+#define SET_PWM_PIN(node_id) \
+	{ DT_FOREACH_PROP_ELEM(node_id, led_values, SET_PIN) };
+
+#define GEN_PINS_ARRAY(id) struct pwm_pin_t PINS_ARRAY(id)[] = SET_PWM_PIN(id)
+
+DT_INST_FOREACH_CHILD_STATUS_OKAY_VARGS(0, DT_FOREACH_CHILD, GEN_PINS_ARRAY)
+
+#define SET_PIN_NODE(node_id)                                \
+	{ .led_color = GET_PROP(node_id, led_color),         \
+	  .led_id = GET_PROP(DT_PARENT(node_id), led_id),    \
+	  .br_color = GET_COLOR_PROP_NVE(node_id, br_color), \
+	  .pwm_pins = PINS_ARRAY(node_id),                   \
+	  .pins_count = DT_PROP_LEN(node_id, led_values) };
+
+/*
+ * Initialize led_pins_node_t struct for each pin node defined
+ */
+#define GEN_PINS_NODES(id) \
+	const struct led_pins_node_t PINS_NODE(id) = SET_PIN_NODE(id)
+
+DT_INST_FOREACH_CHILD_STATUS_OKAY_VARGS(0, DT_FOREACH_CHILD, GEN_PINS_NODES)
+
+/*
+ * Array of pointers to each pin node
+ */
+#define PINS_NODE_PTR(id) &PINS_NODE(id),
+
+const struct led_pins_node_t *pins_node[] = {
+	DT_INST_FOREACH_CHILD_STATUS_OKAY_VARGS(0, DT_FOREACH_CHILD,
+						PINS_NODE_PTR)
+};
+
+/*
+ * Set all the PWM channels defined in the node to the defined value,
+ * to enable the color. Defined value is duty cycle in percentage
+ * converted to duty cycle in ns (pulse_ns)
+ */
+void led_set_color_with_node(const struct led_pins_node_t *pins_node)
+{
+	struct pwm_pin_t *pwm_pins = pins_node->pwm_pins;
+	for (int j = 0; j < pins_node->pins_count; j++) {
+		pwm_set_pulse_dt(&pwm_pins[j].pwm, pwm_pins[j].pulse_ns);
+	}
+}
+
+/*
+ * Iterate through LED pins nodes to find the color matching node.
+ */
+void led_set_color(enum led_color color, enum ec_led_id led_id)
+{
+	for (int i = 0; i < ARRAY_SIZE(pins_node); i++) {
+		if ((pins_node[i]->led_color == color) &&
+		    (pins_node[i]->led_id == led_id)) {
+			led_set_color_with_node(pins_node[i]);
+			break;
+		}
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	memset(brightness_range, 0, EC_LED_COLOR_COUNT);
+
+	for (int i = 0; i < ARRAY_SIZE(pins_node); i++) {
+		int br_color = pins_node[i]->br_color;
+
+		if (pins_node[i]->led_id != led_id) {
+			continue;
+		}
+
+		if (br_color != EC_LED_COLOR_INVALID) {
+			brightness_range[br_color] = 100;
+		}
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	bool color_set = false;
+
+	for (int i = 0; i < ARRAY_SIZE(pins_node); i++) {
+		int br_color = pins_node[i]->br_color;
+
+		if (pins_node[i]->led_id != led_id) {
+			continue;
+		}
+
+		if (br_color != EC_LED_COLOR_INVALID &&
+		    brightness[br_color] != 0) {
+			color_set = true;
+			led_set_color(pins_node[i]->led_color, led_id);
+		}
+	}
+
+	/* If no color was set, turn off the LED */
+	if (!color_set)
+		led_set_color(LED_OFF, led_id);
+
+	return EC_SUCCESS;
+}
+
+__override int led_is_supported(enum ec_led_id led_id)
+{
+	static int supported_leds = -1;
+
+	if (supported_leds == -1) {
+		supported_leds = 0;
+
+		for (int i = 0; i < ARRAY_SIZE(pins_node); i++)
+			supported_leds |= (1 << pins_node[i]->led_id);
+	}
+
+	return ((1 << (int)led_id) & supported_leds);
+}
diff --git a/zephyr/program/framework/src/temperature_filter.c b/zephyr/program/framework/src/temperature_filter.c
new file mode 100644
index 0000000000..ceda098b49
--- /dev/null
+++ b/zephyr/program/framework/src/temperature_filter.c
@@ -0,0 +1,56 @@
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/i2c_emul.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/slist.h>
+#include <zephyr/sys/util.h>
+
+
+
+#include <zephyr/sys/util.h>
+#include <zephyr/kernel.h>
+#include <errno.h>
+#include <string.h>
+#include <zephyr/drivers/gpio.h>
+
+
+#include "console.h"
+#include "zephyr_console_shim.h"
+#include "i2c_hid.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "util.h"
+#include "math_util.h"
+
+#include "temperature_filter.h"
+
+
+
+void thermal_filter_reset(struct biquad *filter)
+{
+	memset(&filter->state, 30 << IN_SCALE, sizeof(filter->state));
+}
+
+int thermal_filter_update(struct biquad *filter, int value)
+{
+	int out_scaled =
+		filter->coeff[0] * (value << IN_SCALE) +
+		filter->coeff[1] * filter->state[0] +
+		filter->coeff[2] * filter->state[1] -
+		filter->coeff[4] * filter->state[2] -
+		filter->coeff[5] * filter->state[3];
+	int out = out_scaled >> Q_SCALE;
+	/* update delay line */
+	filter->state[1] = filter->state[0];
+	filter->state[3] = filter->state[2];
+	filter->state[0] = value << IN_SCALE;
+	filter->state[2] = out;
+	return out >> IN_SCALE;
+}
+
+int thermal_filter_get(struct biquad *filter)
+{
+	return filter->state[2] >> IN_SCALE;
+}
diff --git a/zephyr/program/framework/src/ucsi.c b/zephyr/program/framework/src/ucsi.c
new file mode 100644
index 0000000000..f572e5ccce
--- /dev/null
+++ b/zephyr/program/framework/src/ucsi.c
@@ -0,0 +1,530 @@
+/* Copyright 2023 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * PD chip UCSI
+ * See https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/usb-type-c-ucsi-spec.pdf
+ *
+ */
+
+#include <atomic.h>
+#include "chipset.h"
+#include "config.h"
+#include "customized_shared_memory.h"
+#include "cypress_pd_common.h"
+#include "timer.h"
+#include "ucsi.h"
+#include "hooks.h"
+#include "string.h"
+#include "console.h"
+#include "task.h"
+#include "util.h"
+#include "zephyr_console_shim.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+#define CCI_NOT_SUPPORTED_FLAG BIT(25)
+#define CCI_CANCELED_FLAG BIT(26)
+#define CCI_RESET_FLAG BIT(27)
+#define CCI_BUSY_FLAG BIT(28)
+#define CCI_ACKNOWLEDGE_FLAG BIT(29)
+#define CCI_ERROR_FLAG BIT(30)
+#define CCI_COMPLETE_FLAG BIT(31)
+
+static struct pd_chip_ucsi_info_t pd_chip_ucsi_info[] = {
+	[PD_CHIP_0] = {
+
+	},
+	[PD_CHIP_1] = {
+
+	}
+};
+
+static int ucsi_debug_enable;
+static uint8_t s0ix_connector_change_indicator;
+static bool read_complete;
+
+void ucsi_set_debug(bool enable)
+{
+	ucsi_debug_enable = enable;
+}
+
+timestamp_t ucsi_wait_time;
+
+void ucsi_set_next_poll(uint32_t from_now_us)
+{
+	timestamp_t now = get_time();
+
+	ucsi_wait_time.val = now.val + from_now_us;
+}
+
+const char *command_names(uint8_t command)
+{
+	static const char *response_codes[0x14] = {
+		"RESERVE",
+		"PPM_RESET",
+		"CANCEL",
+		"CONNECTOR_RESET",
+		"ACK_CC_CI",
+		"SET_NOTIFICATION_ENABLE",
+		"GET_CAPABILITY",
+		"GET_CONNECTOR_CAPABILITY",
+		"SET_UOM",
+		"SET_UOR",
+		"SET_PDM",
+		"SET_PDR",
+		"GET_ALTERNATE_MODES",
+		"GET_CAM_SUPPORTED",
+		"GET_CURRENT_CAM",
+		"SET_NEW_CAM",
+		"GET_PDOS",
+		"GET_CABLE_PROPERTY",
+		"GET_CONNECTOR_STATUS",
+		"GET_ERROR_STATUS"
+	};
+	if (command < 0x14) {
+		return response_codes[command];
+	}
+	return "";
+}
+
+int ucsi_write_tunnel(void)
+{
+	uint8_t *message_out = host_get_memmap(EC_CUSTOMIZED_MEMMAP_UCSI_MESSAGE_OUT);
+	uint8_t *command = host_get_memmap(EC_CUSTOMIZED_MEMMAP_UCSI_COMMAND);
+	uint8_t change_connector_indicator = 0;
+	int i;
+	int offset = 0;
+	int rv = EC_SUCCESS;
+
+	/**
+	 * Note that CONTROL data has always to be written after MESSAGE_OUT data is written
+	 * A write to CONTROL (in CCGX) triggers processing of that command.
+	 * Hence MESSAGE_OUT must be available before CONTROL is written to CCGX.
+	 */
+
+	if (*command == UCSI_CMD_PPM_RESET) {
+		cypd_usci_ppm_reset();
+		CPRINTS("UCSI PPM_RESET");
+	}
+
+	pd_chip_ucsi_info[0].read_tunnel_complete = 0;
+	pd_chip_ucsi_info[1].read_tunnel_complete = 0;
+
+	switch (*command) {
+	case UCSI_CMD_GET_CONNECTOR_STATUS:
+	case UCSI_CMD_GET_CONNECTOR_CAPABILITY:
+	case UCSI_CMD_CONNECTOR_RESET:
+	case UCSI_CMD_SET_UOM:
+	case UCSI_CMD_SET_UOR:
+	case UCSI_CMD_SET_PDR:
+	case UCSI_CMD_GET_CAM_SUPPORTED:
+	case UCSI_CMD_SET_NEW_CAM:
+	case UCSI_CMD_GET_PDOS:
+	case UCSI_CMD_GET_CABLE_PROPERTY:
+	case UCSI_CMD_GET_ALTERNATE_MODES:
+	case UCSI_CMD_GET_CURRENT_CAM:
+
+		if (*command == UCSI_CMD_GET_ALTERNATE_MODES) {
+			/**
+			 * Workaround: PD chip cannot process the SOP/SOP'/SOP'' alternate mode
+			 * event, ignore the recipient field.
+			 */
+			*host_get_memmap(EC_CUSTOMIZED_MEMMAP_UCSI_CTR_SPECIFIC) =
+				(*host_get_memmap(EC_CUSTOMIZED_MEMMAP_UCSI_CTR_SPECIFIC) & 0xFC);
+			offset = 1;
+		}
+
+		/**
+		 * those command will control specific pd port,
+		 * so we need to check the command connector number.
+		 */
+		change_connector_indicator =
+			*host_get_memmap(EC_CUSTOMIZED_MEMMAP_UCSI_CTR_SPECIFIC + offset) & 0x7f;
+
+		if (change_connector_indicator > 0x02) {
+			/*
+			 * Port 3 (b011) should be controller 1 UCSI port 1
+			 * Port 4 (b100) should be controller 1 UCSI port 2
+			 */
+			*host_get_memmap(EC_CUSTOMIZED_MEMMAP_UCSI_CTR_SPECIFIC + offset) =
+				((*host_get_memmap(EC_CUSTOMIZED_MEMMAP_UCSI_CTR_SPECIFIC + offset)
+				& 0x80) | (change_connector_indicator >> 1));
+			i = 1;
+		} else
+			i = 0;
+
+		pd_chip_ucsi_info[i].wait_ack = 1;
+		rv = cypd_write_reg_block(i, CCG_MESSAGE_OUT_REG, message_out, 16);
+		rv = cypd_write_reg_block(i, CCG_CONTROL_REG, command, 8);
+		break;
+	default:
+		for (i = 0; i < PD_CHIP_COUNT; i++) {
+
+			/**
+			 * If the controller does not needs to respond ACK,
+			 * set the read tunnel complete flag.
+			 * Because ec will not write the command to PD chips.
+			 */
+			if (*command == UCSI_CMD_ACK_CC_CI &&
+			    pd_chip_ucsi_info[i].wait_ack == 0) {
+				pd_chip_ucsi_info[i].read_tunnel_complete = 1;
+				continue;
+			}
+
+			rv = cypd_write_reg_block(i, CCG_MESSAGE_OUT_REG, message_out, 16);
+			if (rv != EC_SUCCESS)
+				break;
+
+			rv = cypd_write_reg_block(i, CCG_CONTROL_REG, command, 8);
+			if (rv != EC_SUCCESS)
+				break;
+
+			/**
+			 * ACK_CC_CI command is the end of the UCSI command,
+			 * does not need to wait ack.
+			 */
+			if (*command == UCSI_CMD_ACK_CC_CI)
+				pd_chip_ucsi_info[i].wait_ack = 0;
+			else
+				pd_chip_ucsi_info[i].wait_ack = 1;
+		}
+		break;
+	}
+
+	if (ucsi_debug_enable) {
+		CPRINTS("UCSI Write P:%d Cmd 0x%016llx %s",
+			change_connector_indicator,
+			*(uint64_t *)command,
+			command_names(*command));
+		if (command[1])
+			cypd_print_buff("UCSI Msg Out: ", message_out, 6);
+	}
+
+	usleep(50);
+	return rv;
+}
+
+void record_ucsi_connector_change_event(int controller, int port)
+{
+	int cci_port = (controller << 1) + port + 1;
+
+	if (!chipset_in_state(CHIPSET_STATE_ON) && !chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		s0ix_connector_change_indicator |= BIT(cci_port);
+}
+
+static void clear_ucsi_connector_change_event(void)
+{
+	/* UCSI driver will reset PPM, so clear the indicator */
+	if (chipset_in_state(CHIPSET_STATE_ON))
+		s0ix_connector_change_indicator = 0;
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESET, clear_ucsi_connector_change_event, HOOK_PRIO_DEFAULT);
+
+static void resend_ucsi_connector_change_event(void);
+DECLARE_DEFERRED(resend_ucsi_connector_change_event);
+
+static void resend_ucsi_connector_change_event(void)
+{
+	static int process_port = 1;
+	static int resume_flag;
+
+	if (s0ix_connector_change_indicator == 0) {
+		process_port = 1;
+		resume_flag = 0;
+	} else {
+		if (!resume_flag) {
+			/* Wait host driver ready */
+			hook_call_deferred(&resend_ucsi_connector_change_event_data, 500 * MSEC);
+			resume_flag = 1;
+			return;
+		}
+
+		if (s0ix_connector_change_indicator & BIT(process_port)) {
+			pd_chip_ucsi_info[(process_port - 1) >> 1].cci =
+				(BIT(29) | process_port << 1);
+
+			if (ucsi_debug_enable) {
+				uint32_t cci_reg =
+					pd_chip_ucsi_info[(process_port - 1) >> 1].cci;
+
+				CPRINTS("Resend: P%d CCI: 0x%08x Port%d, %s%s%s%s%s%s%s",
+				(process_port - 1) >> 1,
+				cci_reg,
+				(cci_reg >> 1) & 0x07F,
+				cci_reg & CCI_NOT_SUPPORTED_FLAG ? "Not Support " : "",
+				cci_reg & CCI_CANCELED_FLAG ? "Canceled " : "",
+				cci_reg & CCI_RESET_FLAG ? "Reset " : "",
+				cci_reg & CCI_BUSY_FLAG ? "Busy " : "",
+				cci_reg & CCI_ACKNOWLEDGE_FLAG ? "Acknowledge " : "",
+				cci_reg & CCI_ERROR_FLAG ? "Error " : "",
+				cci_reg & CCI_COMPLETE_FLAG ? "Complete " : ""
+				);
+			}
+
+			pd_chip_ucsi_info[(process_port - 1) >> 1].read_tunnel_complete = 1;
+			read_complete = 1;
+
+			s0ix_connector_change_indicator &= ~BIT(process_port);
+		}
+		process_port++;
+		hook_call_deferred(&resend_ucsi_connector_change_event_data, 150 * MSEC);
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, resend_ucsi_connector_change_event, HOOK_PRIO_DEFAULT);
+
+int ucsi_read_tunnel(int controller)
+{
+	int rv;
+
+	if (ucsi_debug_enable && pd_chip_ucsi_info[controller].read_tunnel_complete == 1 &&
+		(pd_chip_ucsi_info[controller].cci & CCI_BUSY_FLAG) == 0) {
+		CPRINTS("UCSI Read tunnel but previous read still pending");
+	}
+
+	rv = cypd_read_reg_block(controller, CCG_CCI_REG,
+		&pd_chip_ucsi_info[controller].cci, 4);
+
+	if (rv != EC_SUCCESS)
+		CPRINTS("CCI_REG failed");
+	/* we need to offset the pd connector number to correct number */
+	if (controller == 1 && (pd_chip_ucsi_info[controller].cci & 0xFE))
+		/*
+		 * Port 3 (b011) should be controller 1 UCSI port 1 (b001)
+		 * Port 4 (b100) should be controller 1 UCSI port 2 (b010)
+		 * CCI connector change indicate offset bit 1, so need to add 0x04 (0x2 << 1)
+		 */
+		pd_chip_ucsi_info[controller].cci += 0x04;
+
+	/* If data length is non zero, then get data */
+	if (pd_chip_ucsi_info[controller].cci & 0xFF00) {
+		rv = cypd_read_reg_block(controller, CCG_MESSAGE_IN_REG,
+			pd_chip_ucsi_info[controller].message_in, 16);
+
+		if (rv != EC_SUCCESS)
+			CPRINTS("MESSAGE_IN_REG failed");
+	} else {
+		memset(pd_chip_ucsi_info[controller].message_in, 0, 16);
+	}
+
+	if (ucsi_debug_enable) {
+		uint32_t cci_reg = pd_chip_ucsi_info[controller].cci;
+
+		CPRINTS("P%d CCI: 0x%08x Port%d, %s%s%s%s%s%s%s",
+			controller,
+			cci_reg,
+			(cci_reg >> 1) & 0x07F,
+			cci_reg & CCI_NOT_SUPPORTED_FLAG ? "Not Support " : "",
+			cci_reg & CCI_CANCELED_FLAG ? "Canceled " : "",
+			cci_reg & CCI_RESET_FLAG ? "Reset " : "",
+			cci_reg & CCI_BUSY_FLAG ? "Busy " : "",
+			cci_reg & CCI_ACKNOWLEDGE_FLAG ? "Acknowledge " : "",
+			cci_reg & CCI_ERROR_FLAG ? "Error " : "",
+			cci_reg & CCI_COMPLETE_FLAG ? "Complete " : ""
+			);
+		if (cci_reg & 0xFF00) {
+			cypd_print_buff("Message ", pd_chip_ucsi_info[controller].message_in, 16);
+		}
+	}
+
+	/**
+	 * When the system enter sleep mode, EC should record the change indicator then resend when
+	 * the system resume.
+	 */
+	if (!chipset_in_state(CHIPSET_STATE_ON) && !chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return EC_SUCCESS;
+
+	/**
+	 * 1. Ignore the same CCI indicator without any command
+	 * 2. Ignore the same CCI indicator with busy flags
+	 */
+	if (!(memcmp(host_get_memmap(EC_CUSTOMIZED_MEMMAP_UCSI_CONN_CHANGE),
+		&pd_chip_ucsi_info[controller].cci, 4)) &&
+		((*host_get_memmap(EC_CUSTOMIZED_MEMMAP_UCSI_COMMAND) == 0) ||
+		*(uint32_t *)host_get_memmap(EC_CUSTOMIZED_MEMMAP_UCSI_CONN_CHANGE)&CCI_BUSY_FLAG))
+		return EC_ERROR_UNKNOWN;
+
+	pd_chip_ucsi_info[controller].read_tunnel_complete = 1;
+
+	switch (*host_get_memmap(EC_CUSTOMIZED_MEMMAP_UCSI_COMMAND)) {
+	case UCSI_CMD_PPM_RESET:
+	case UCSI_CMD_CANCEL:
+	case UCSI_CMD_SET_NOTIFICATION_ENABLE:
+	case UCSI_CMD_GET_CAPABILITY:
+	case UCSI_CMD_GET_ERROR_STATUS:
+		/* Those command need to wait two pd chip to response completed */
+		if (pd_chip_ucsi_info[0].read_tunnel_complete &&
+		    pd_chip_ucsi_info[1].read_tunnel_complete)
+			read_complete = 1;
+		else
+			read_complete = 0;
+		break;
+	case UCSI_CMD_ACK_CC_CI:
+		if (pd_chip_ucsi_info[0].read_tunnel_complete &&
+		    pd_chip_ucsi_info[1].read_tunnel_complete) {
+			read_complete = 1;
+
+			/* workaround for linux driver */
+			if ((pd_chip_ucsi_info[controller].cci & CCI_ACKNOWLEDGE_FLAG) !=
+				pd_chip_ucsi_info[controller].cci)
+				pd_chip_ucsi_info[controller].wait_ack = 1;
+		} else
+			read_complete = 0;
+		break;
+	default:
+		if (pd_chip_ucsi_info[0].read_tunnel_complete ||
+		    pd_chip_ucsi_info[1].read_tunnel_complete)
+			read_complete = 1;
+		else
+			read_complete = 0;
+		break;
+	}
+
+	return EC_SUCCESS;
+}
+
+int ucsi_startup(int controller)
+{
+	int rv = EC_SUCCESS;
+	int data;
+
+	ucsi_set_next_poll(0);
+	rv = cypd_write_reg8(controller, CCG_UCSI_CONTROL_REG, CYPD_UCSI_START);
+	if (rv != EC_SUCCESS)
+		CPRINTS("UCSI start command fail!");
+
+	if (cypd_wait_for_ack(controller, 100) != EC_SUCCESS) {
+		CPRINTS("%s timeout on interrupt", __func__);
+		return EC_ERROR_INVAL;
+	}
+
+	rv = cypd_get_int(controller, &data);
+
+	if (data & CCG_DEV_INTR) {
+		rv = cypd_read_reg_block(controller, CCG_VERSION_REG,
+			&pd_chip_ucsi_info[controller].version, 2);
+
+		if (rv != EC_SUCCESS)
+			CPRINTS("UCSI start command fail!");
+
+		memcpy(host_get_memmap(EC_CUSTOMIZED_MEMMAP_UCSI_VERSION),
+			&pd_chip_ucsi_info[controller].version, 2);
+
+		cypd_clear_int(controller, CCG_DEV_INTR);
+	}
+	return rv;
+}
+
+/**
+ * Suggested by bios team, we don't use host command frequenctly.
+ * So we need to polling the flags to get the ucsi event form host.
+ */
+
+void check_ucsi_event_from_host(void)
+{
+	void *message_in;
+	uint32_t *cci;
+	int i;
+	int rv;
+
+	if (read_complete == 0 && !timestamp_expired(ucsi_wait_time, NULL)) {
+		if (ucsi_debug_enable)
+			CPRINTS("UCSI waiting for time expired");
+		return;
+	}
+
+	/* If the UCSI interface previously was busy then
+	 * poll to see if the busy bit cleared
+	 */
+	for (i = 0; i < PD_CHIP_COUNT; i++) {
+		if (pd_chip_ucsi_info[i].cci & CCI_BUSY_FLAG) {
+			ucsi_read_tunnel(i);
+		}
+	}
+
+	if (!chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
+	    !chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
+	    (*host_get_memmap(EC_CUSTOMIZED_MEMMAP_SYSTEM_FLAGS) & UCSI_EVENT)) {
+
+		/**
+		 * Following the specification, until the EC reads the VERSION register
+		 * from CCGX's UCSI interface, it ignores all writes from the BIOS
+		 */
+		rv = ucsi_write_tunnel();
+
+		ucsi_set_next_poll(10*MSEC);
+
+		if (rv == EC_ERROR_BUSY)
+			return;
+
+		*host_get_memmap(EC_CUSTOMIZED_MEMMAP_SYSTEM_FLAGS) &= ~UCSI_EVENT;
+		return;
+	}
+
+	if (read_complete) {
+		if (ucsi_debug_enable) {
+			CPRINTS("%s Complete",
+				command_names(*host_get_memmap(EC_CUSTOMIZED_MEMMAP_UCSI_COMMAND)));
+		}
+		if (pd_chip_ucsi_info[0].read_tunnel_complete) {
+			message_in = pd_chip_ucsi_info[0].message_in;
+			cci = &pd_chip_ucsi_info[0].cci;
+		}
+
+		if (pd_chip_ucsi_info[1].read_tunnel_complete) {
+			message_in = pd_chip_ucsi_info[1].message_in;
+			cci = &pd_chip_ucsi_info[1].cci;
+		}
+		read_complete = false;
+
+		/* Fix UCSI stopping responding to right side ports
+		 * the standard says the CCI connector change indicator field
+		 * should be 0 for ACK_CC_CI, however our controller responds with
+		 * the port number populated for the port with the valid response
+		 * so choose this response as a priority when we get an ack from
+		 * both controllers
+		 */
+		if (pd_chip_ucsi_info[1].read_tunnel_complete &&
+			pd_chip_ucsi_info[0].read_tunnel_complete) {
+			if (pd_chip_ucsi_info[0].cci & 0xFE) {
+				message_in = pd_chip_ucsi_info[0].message_in;
+				cci = &pd_chip_ucsi_info[0].cci;
+			} else if (pd_chip_ucsi_info[1].cci & 0xFE) {
+				message_in = pd_chip_ucsi_info[1].message_in;
+				cci = &pd_chip_ucsi_info[1].cci;
+			}
+		}
+
+		if (*host_get_memmap(EC_CUSTOMIZED_MEMMAP_UCSI_COMMAND) ==
+		    UCSI_CMD_GET_CONNECTOR_STATUS &&
+		    (((uint8_t *)message_in)[8] & 0x03) > 1) {
+			CPRINTS("Overriding Slow charger status");
+			/* Override not charging value with nominal charging */
+			((uint8_t *)message_in)[8] = (((uint8_t *)message_in)[8] & 0xFC) + 1;
+		}
+
+		usleep(2 * MSEC);
+
+		memcpy(host_get_memmap(EC_CUSTOMIZED_MEMMAP_UCSI_MESSAGE_IN), message_in, 16);
+		memcpy(host_get_memmap(EC_CUSTOMIZED_MEMMAP_UCSI_CONN_CHANGE), cci, 4);
+
+		/**
+		 * TODO: process the two pd results for one response.
+		 */
+
+		/* override bNumConnectors to the total number of connectors on the system */
+		if (*host_get_memmap(EC_CUSTOMIZED_MEMMAP_UCSI_COMMAND) == UCSI_CMD_GET_CAPABILITY)
+			*host_get_memmap(EC_CUSTOMIZED_MEMMAP_UCSI_MESSAGE_IN + 4) = PD_PORT_COUNT;
+
+		pd_chip_ucsi_info[0].read_tunnel_complete = 0;
+		pd_chip_ucsi_info[1].read_tunnel_complete = 0;
+
+		/* clear the UCSI command if busy flag is not set */
+		if (0 == (*cci & CCI_BUSY_FLAG)) {
+			if (!(*host_get_memmap(EC_CUSTOMIZED_MEMMAP_SYSTEM_FLAGS) & UCSI_EVENT))
+				*host_get_memmap(EC_CUSTOMIZED_MEMMAP_UCSI_COMMAND) = 0;
+		}
+		host_set_single_event(EC_HOST_EVENT_UCSI);
+	}
+}
diff --git a/zephyr/program/framework/src/uefi_app_mode.c b/zephyr/program/framework/src/uefi_app_mode.c
new file mode 100644
index 0000000000..641dbafb7e
--- /dev/null
+++ b/zephyr/program/framework/src/uefi_app_mode.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2023 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/drivers/gpio.h>
+
+#include "ec_commands.h"
+#include "uefi_app_mode.h"
+#include "gpio.h"
+#include "gpio/gpio_int.h"
+
+static uint8_t uefi_app_enable;
+
+void uefi_app_mode_setting(uint8_t enable)
+{
+	uefi_app_enable = enable;
+
+	/* Ignored the power button signal if we are in UEFI app mode */
+	/* TODO: Maybe add a hook when OS boots to enable the interrupt again, */
+	/* if the app forgets to do it. */
+	if (uefi_app_enable) {
+		gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_powerbtn));
+	} else {
+		gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_powerbtn));
+	}
+}
+
+uint8_t uefi_app_btn_status(void)
+{
+	return gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_on_off_btn_l)) == 1;
+}
diff --git a/zephyr/program/geralt/BUILD.py b/zephyr/program/geralt/BUILD.py
new file mode 100644
index 0000000000..cc4c2b1946
--- /dev/null
+++ b/zephyr/program/geralt/BUILD.py
@@ -0,0 +1,24 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Define zmake projects for geralt."""
+
+
+def register_geralt_project(
+    project_name,
+):
+    """Register a variant of geralt."""
+    return register_binman_project(
+        project_name=project_name,
+        zephyr_board="it81202cx",
+        dts_overlays=[here / project_name / "project.overlay"],
+        kconfig_files=[
+            here / "program.conf",
+            here / project_name / "project.conf",
+        ],
+        inherited_from=["geralt"],
+    )
+
+
+geralt = register_geralt_project(project_name="geralt")
diff --git a/zephyr/program/geralt/CMakeLists.txt b/zephyr/program/geralt/CMakeLists.txt
new file mode 100644
index 0000000000..fff33c7108
--- /dev/null
+++ b/zephyr/program/geralt/CMakeLists.txt
@@ -0,0 +1,32 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+
+cros_ec_library_include_directories(include)
+
+# Include selected EC source from the baseboard
+zephyr_library_sources(
+	"src/ccd_mode.c"
+	"src/backlight.c"
+	"src/hibernate.c"
+	"src/hooks.c"
+	"src/ppc.c"
+)
+
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_I2C "src/i2c.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC
+			"src/dp_alt_mode.c"
+			"src/usbc_config.c"
+			"src/usb_pd_policy.c"
+)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_DETACHABLE_BASE
+			"src/base_detect.c"
+)
+
+if(DEFINED CONFIG_BOARD_GERALT)
+	project(geralt)
+endif()
diff --git a/zephyr/program/geralt/Kconfig b/zephyr/program/geralt/Kconfig
new file mode 100644
index 0000000000..c5f6876bda
--- /dev/null
+++ b/zephyr/program/geralt/Kconfig
@@ -0,0 +1,20 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+choice GERALT_VARIANT
+	prompt "Pick a variant of Geralt"
+	help
+	  Geralt is the reference device that has MediaTek MT8188G SoC with
+	  ITE it81202-cx EC.
+	  Pick one of the variants below.
+
+config BOARD_GERALT
+	bool "Google Geralt Reference Board"
+	help
+	  Build the Geralt reference board. The board is the reference design
+	  of Geralt family.
+
+endchoice
+
+source "Kconfig.zephyr"
diff --git a/zephyr/program/geralt/adc.dtsi b/zephyr/program/geralt/adc.dtsi
new file mode 100644
index 0000000000..2c62408cf9
--- /dev/null
+++ b/zephyr/program/geralt/adc.dtsi
@@ -0,0 +1,47 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	named-adc-channels {
+		compatible = "named-adc-channels";
+		adc-vbus-c0 {
+			enum-name = "ADC_VBUS_C0";
+			io-channels = <&adc0 0>;
+			mul = <10>;
+		};
+		adc-board-id0 {
+			enum-name = "ADC_BOARD_ID_0";
+			io-channels = <&adc0 1>;
+		};
+		adc-board-id1 {
+			enum-name = "ADC_BOARD_ID_1";
+			io-channels = <&adc0 2>;
+		};
+		adc-base-det {
+			enum-name = "ADC_BASE_DET";
+			io-channels = <&adc0 5>;
+		};
+		adc-temp-sensor-charger {
+			enum-name = "ADC_TEMP_SENSOR_CHARGER";
+			io-channels = <&adc0 6>;
+		};
+		adc-vbus-c1 {
+			enum-name = "ADC_VBUS_C1";
+			io-channels = <&adc0 7>;
+			mul = <10>;
+		};
+	};
+};
+
+&adc0 {
+	status = "okay";
+	pinctrl-0 = <&adc0_ch0_gpi0_default
+		     &adc0_ch1_gpi1_default
+		     &adc0_ch2_gpi2_default
+		     &adc0_ch5_gpi5_default
+		     &adc0_ch6_gpi6_default
+		     &adc0_ch7_gpi7_default>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/geralt/geralt/battery.dtsi b/zephyr/program/geralt/geralt/battery.dtsi
new file mode 100644
index 0000000000..7c194ca918
--- /dev/null
+++ b/zephyr/program/geralt/geralt/battery.dtsi
@@ -0,0 +1,12 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	batteries {
+		default_battery: smp_l21m4pg0 {
+			compatible = "smp,l21m4pg0", "battery-smart";
+		};
+	};
+};
diff --git a/zephyr/program/geralt/geralt/led.dtsi b/zephyr/program/geralt/geralt/led.dtsi
new file mode 100644
index 0000000000..f88fd99d76
--- /dev/null
+++ b/zephyr/program/geralt/geralt/led.dtsi
@@ -0,0 +1,119 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include <dt-bindings/battery.h>
+
+/ {
+	led-colors {
+		compatible = "cros-ec,led-policy";
+
+		pwr-power-state-off {
+			color-0 {
+				led-color = <&color_power_off>;
+			};
+		};
+
+		pwr-power-state-on {
+			chipset-state = "POWER_S0";
+
+			color-0 {
+				led-color = <&color_power_green>;
+			};
+		};
+
+		pwr-power-state-s3 {
+			chipset-state = "POWER_S3";
+
+			color-0 {
+				led-color = <&color_power_green>;
+				period-ms = <1000>;
+			};
+
+			color-1 {
+				led-color = <&color_power_off>;
+				period-ms = <3000>;
+			};
+		};
+	};
+
+	pwmleds {
+		compatible = "pwm-leds";
+
+		/* NOTE: &pwm number needs same with channel number */
+		led_power_red: ec_led1_odl {
+			pwms = <&pwm0
+				PWM_CHANNEL_0
+				PWM_HZ(324)
+				PWM_POLARITY_INVERTED>;
+		};
+
+		led_power_green: ec_led2_odl {
+			pwms = <&pwm1
+				PWM_CHANNEL_1
+				PWM_HZ(324)
+				PWM_POLARITY_INVERTED>;
+		};
+
+		led_power_blue: ec_led3_odl {
+			pwms = <&pwm2
+				PWM_CHANNEL_2
+				PWM_HZ(324)
+				PWM_POLARITY_INVERTED>;
+		};
+	};
+
+	pwm-led-pins {
+		compatible = "cros-ec,pwm-led-pins";
+
+		power_led: power-led {
+			led-id = "EC_LED_ID_POWER_LED";
+			led-pwms = <&led_power_red &led_power_green
+				    &led_power_blue>;
+
+			color_power_off: color-power-off {
+				led-color = "LED_OFF";
+				led-values = <0 0 0>;
+			};
+
+			color_power_green: color-power-green {
+				led-color = "LED_GREEN";
+				br-color = "EC_LED_COLOR_GREEN";
+				led-values = <0 100 0>;
+			};
+
+			color_power_blue: color-power-blue {
+				led-color = "LED_BLUE";
+				br-color = "EC_LED_COLOR_BLUE";
+				led-values = <0 0 100>;
+			};
+		};
+	};
+};
+
+/*
+ * LED1
+ * Broken, see b/269706760#comment4
+ */
+&pwm0 {
+	status = "okay";
+	prescaler-cx = <PWM_PRESCALER_C4>;
+	pinctrl-0 = <&pwm0_gpa0_default>;
+	pinctrl-names = "default";
+};
+
+/* LED2 */
+&pwm1 {
+	status = "okay";
+	prescaler-cx = <PWM_PRESCALER_C4>;
+	pinctrl-0 = <&pwm1_gpa1_default>;
+	pinctrl-names = "default";
+};
+
+/* LED3 */
+&pwm2 {
+	status = "okay";
+	prescaler-cx = <PWM_PRESCALER_C4>;
+	pinctrl-0 = <&pwm2_gpa2_default>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/geralt/geralt/project.conf b/zephyr/program/geralt/geralt/project.conf
new file mode 100644
index 0000000000..624cafe3fa
--- /dev/null
+++ b/zephyr/program/geralt/geralt/project.conf
@@ -0,0 +1,6 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Variant config
+CONFIG_BOARD_GERALT=y
diff --git a/zephyr/program/geralt/geralt/project.overlay b/zephyr/program/geralt/geralt/project.overlay
new file mode 100644
index 0000000000..76ed8c0a6a
--- /dev/null
+++ b/zephyr/program/geralt/geralt/project.overlay
@@ -0,0 +1,19 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Geralt program common DTS includes */
+
+#include "../adc.dtsi"
+#include "../gpio.dtsi"
+#include "../i2c.dtsi"
+#include "../interrupts.dtsi"
+#include "../keyboard.dtsi"
+#include "../mkbp.dtsi"
+#include "../motionsense.dtsi"
+#include "../power_signal.dtsi"
+#include "../usbc.dtsi"
+#include "../shi.dtsi"
+#include "battery.dtsi"
+#include "led.dtsi"
diff --git a/zephyr/program/geralt/gpio.dtsi b/zephyr/program/geralt/gpio.dtsi
new file mode 100644
index 0000000000..b27291f5bf
--- /dev/null
+++ b/zephyr/program/geralt/gpio.dtsi
@@ -0,0 +1,240 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/gpio_defines.h>
+
+/ {
+	aliases {
+		gpio-cbi-wp = &ec_cbi_wp;
+		gpio-wp = &ec_flash_wp_odl;
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		lid_360_l: lid-360-l {
+			gpios = <&gpioj 7 GPIO_INPUT>;
+			enum-name = "GPIO_TABLET_MODE_L";
+		};
+		ap_in_sleep_l: ap-in-sleep-l {
+			gpios = <&gpiob 6 (GPIO_INPUT | GPIO_VOLTAGE_1P8 |
+					   GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_AP_IN_SLEEP_L";
+		};
+		spi0_cs: spi0-cs {
+			gpios = <&gpiom 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		lid_imu_int_l: lid-imu-int-l {
+			gpios = <&gpiom 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		gpio_packet_mode_en: packet-mode-en {
+			gpios = <&gpiod 4 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_PACKET_MODE_EN";
+		};
+		ap_ec_wdtrst_l: ap-ec-wdtrst-l {
+			gpios = <&gpioc 7 (GPIO_INPUT | GPIO_VOLTAGE_1P8 |
+					   GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_AP_EC_WDTRST_L";
+		};
+		ec_ap_int_l: ec-ap-int-l {
+			gpios = <&gpioe 6 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>;
+			enum-name = "GPIO_EC_INT_L";
+		};
+		ec_pmic_en_odl: ec-pmic-en-odl {
+			gpios = <&gpiod 0 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>;
+			enum-name = "GPIO_EC_PMIC_EN_ODL";
+		};
+		usb_c0_ppc_bc12_int_odl: usb-c0-ppc-bc12-int-odl {
+			gpios = <&gpiod 1 GPIO_INPUT>;
+		};
+		ap_ec_warm_rst_req: ap-ec-warm-rst-req {
+			gpios = <&gpiod 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8 |
+					   GPIO_ACTIVE_HIGH)>;
+			enum-name = "GPIO_AP_EC_WARM_RST_REQ";
+		};
+		volume_down_l: volume-down-l {
+			gpios = <&gpiod 5 GPIO_INPUT>;
+			enum-name = "GPIO_VOLUME_DOWN_L";
+		};
+		volume_up_l: volume-up-l {
+			gpios = <&gpiod 6 GPIO_INPUT>;
+			enum-name = "GPIO_VOLUME_UP_L";
+		};
+		ac_present: ac-present {
+			gpios = <&gpioe 5 GPIO_INPUT>;
+			enum-name = "GPIO_AC_PRESENT";
+		};
+		en_ppvar_base_x: en-ppvar-base-x {
+			gpios = <&gpiod 7 GPIO_OUTPUT_LOW>;
+		};
+		ec_cbi_wp: ec-cbi-wp {
+			gpios = <&gpioc 3 GPIO_OUTPUT_LOW>;
+		};
+		ec_ap_hid_int_odl: ec-ap-hid-int-odl {
+			gpios = <&gpioi 3 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8 |
+					   GPIO_ACTIVE_LOW)>;
+		};
+		ec_flash_wp_odl: ec-flash-wp-odl {
+			gpios = <&gpioi 4 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		ec_ap_dp_hpd_odl: ec-ap-dp-hpd-odl {
+			gpios = <&gpioj 0 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>;
+		};
+		usb_c1_dp_in_hpd: usb-c1-dp-in-hpd {
+			gpios = <&gpioj 1 GPIO_OUTPUT_LOW>;
+		};
+		ap_sysrst_odl_r: ap-ec-sysrst-odl {
+			gpios = <&gpioj 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8 |
+					   GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_AP_EC_SYSRST_ODL";
+		};
+		en_cc_lid_base_pu: en-cc-lid-base-pu {
+			gpios = <&gpioj 3 GPIO_INPUT>;
+		};
+		usb_c1_bc12_charger_int_odl: usb-c1-bc12-charger-int-odl {
+			gpios = <&gpioj 4 GPIO_INPUT>;
+		};
+		ap_xhci_init_done: ap-xhci-init-done {
+			gpios = <&gpioj 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		lid_open: lid-open {
+			gpios = <&gpioe 2 GPIO_INPUT>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+		en_ulp: en-ulp {
+			gpios = <&gpioe 3 GPIO_OUTPUT_LOW>;
+		};
+		usb_c1_frs_en: usb-c1-frs-en {
+			gpios = <&gpiof 0 GPIO_OUTPUT_LOW>;
+		};
+		als_rgb_int_odl: als-rgb-int-odl {
+			gpios = <&gpiof 1 GPIO_INPUT>;
+		};
+		usb_c0_dp_in_hpd: usb-c0-dp-in-hpd {
+			gpios = <&gpioh 3 GPIO_OUTPUT_LOW>;
+		};
+		en_ec_id_odl: en-ec-id-odl {
+			gpios = <&gpioh 4 GPIO_ODR_HIGH>;
+		};
+		gpio_en_5v_usm: en-5v-usm {
+			gpios = <&gpiog 3 GPIO_OUTPUT_LOW>;
+		};
+		dp_path_sel: dp-path-sel {
+			gpios = <&gpiog 0 GPIO_OUTPUT_HIGH>;
+		};
+		en_pp4200_s5: en-pp4200-s5 {
+			gpios = <&gpiob 7 GPIO_OUTPUT_LOW>;
+		};
+		pg_pp4200_s5_od: pg-pp4200-s5-od {
+			gpios = <&gpioc 5 GPIO_INPUT>;
+			enum-name = "GPIO_PG_PP4200_S5_OD";
+		};
+		sys_rst_odl: sys-rst-odl {
+			gpios = <&gpiog 1 GPIO_ODR_LOW>;
+			enum-name = "GPIO_SYS_RST_ODL";
+		};
+		ec_batt_pres_odl: ec-batt-pres-odl {
+			gpios = <&gpioc 0 GPIO_INPUT>;
+			enum-name = "GPIO_BATT_PRES_ODL";
+		};
+		gpio_ccd_mode_odl: ccd-mode-odl {
+			gpios = <&gpioc 4 GPIO_INPUT>;
+			enum-name = "GPIO_CCD_MODE_ODL";
+		};
+		usb_c1_ppc_int_odl: usb-c1-ppc-int-odl {
+			gpios = <&gpiob 2 GPIO_INPUT>;
+		};
+		en_pp5000_z1_l: en-pp5000-z1-l {
+			gpios = <&gpioc 6 GPIO_OUTPUT_LOW>;
+		};
+		power_button_l: power-button-l {
+			gpios = <&gpioe 4 GPIO_INPUT>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		gpio_ec_bl_en_od: ec-bl-en-od {
+			gpios = <&gpiob 5 (GPIO_ODR_LOW | GPIO_VOLTAGE_1P8)>;
+		};
+		pmic_ec_resetb: pmic-ec-resetb {
+			gpios = <&gpioj 6 (GPIO_INPUT | GPIO_VOLTAGE_1P8 |
+					   GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_PMIC_EC_RESETB";
+		};
+
+		/*
+		 * Not used, only to make system.c compilable.
+		 * TODO: find a better way to remove this.
+		 */
+		entering_rw: entering-rw {
+			enum-name = "GPIO_ENTERING_RW";
+		};
+	};
+
+	hibernate-wake-pins {
+		compatible = "cros-ec,hibernate-wake-pins";
+		wakeup-irqs = <&int_ac_present
+			       &int_power_button
+			       &int_lid_open>;
+	};
+
+	unused-pins {
+		compatible = "unused-gpios";
+
+		unused-gpios =
+			/* unnamed nc pins */
+			<&gpioa 3 GPIO_INPUT_PULL_DOWN>,
+			<&gpioa 6 GPIO_INPUT_PULL_DOWN>,
+			<&gpioa 7 GPIO_INPUT_PULL_DOWN>,
+			/* pg_pp5000_z1_od */
+			<&gpiod 2 GPIO_INPUT>,
+			/* CHARGE_EN DNS */
+			<&gpioe 1 GPIO_INPUT_PULL_DOWN>,
+			/* spi_clk_gpg6 */
+			<&gpiog 6 GPIO_INPUT_PULL_UP>,
+			/* spi_mosi_gpg4 */
+			<&gpiog 4 GPIO_OUTPUT_LOW>,
+			/* spi_miso_gpg5 */
+			<&gpiog 5 GPIO_OUTPUT_LOW>,
+			/* spi_cs_gpg7 */
+			<&gpiog 7 GPIO_OUTPUT_LOW>,
+			/* Input w/o I-PULL for unused GPIO w/ Ex-PU
+			 * EC_AP_RSVD0_ODL
+			 */
+			<&gpioh 0 GPIO_INPUT>,
+			/* h5,h6: uart base tx/rx */
+			<&gpioh 5 GPIO_INPUT>,
+			<&gpioh 6 GPIO_INPUT>,
+			<&gpiom 2 (GPIO_INPUT_PULL_DOWN | GPIO_VOLTAGE_1P8)>,
+			<&gpiom 6 (GPIO_INPUT_PULL_DOWN | GPIO_VOLTAGE_1P8)>;
+	};
+};
+
+&pinctrl {
+	/* I2C property setting */
+	i2c0_clk_gpb3_default: i2c0_clk_gpb3_default {
+		gpio-voltage = "1v8";
+	};
+	i2c0_data_gpb4_default: i2c0_data_gpb4_default {
+		gpio-voltage = "1v8";
+	};
+	i2c3_clk_gpf2_default: i2c3_clk_gpf2_default {
+		gpio-voltage = "1v8";
+	};
+	i2c3_data_gpf3_default: i2c3_data_gpf3_default {
+		gpio-voltage = "1v8";
+	};
+	/* SHI property setting */
+	shi_mosi_gpm0_default: shi_mosi_gpm0_default {
+		gpio-voltage = "1v8";
+	};
+	shi_miso_gpm1_default: shi_miso_gpm1_default {
+		gpio-voltage = "1v8";
+	};
+	shi_clk_gpm4_default: shi_clk_gpm4_default {
+		gpio-voltage = "1v8";
+	};
+	shi_cs_gpm5_default: shi_cs_gpm5_default {
+		gpio-voltage = "1v8";
+	};
+};
diff --git a/zephyr/program/geralt/i2c.dtsi b/zephyr/program/geralt/i2c.dtsi
new file mode 100644
index 0000000000..30e74af78f
--- /dev/null
+++ b/zephyr/program/geralt/i2c.dtsi
@@ -0,0 +1,136 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		battery {
+			i2c-port = <&i2c1>;
+			remote-port = <1>;
+			enum-names = "I2C_PORT_BATTERY",
+				"I2C_PORT_VIRTUAL_BATTERY";
+		};
+		i2c_charger: charger {
+			i2c-port = <&i2c0>;
+			enum-names = "I2C_PORT_CHARGER",
+				"I2C_PORT_EEPROM";
+		};
+		i2c_sensor: sensor {
+			i2c-port = <&i2c3>;
+			enum-names = "I2C_PORT_SENSOR";
+		};
+		i2c_usb_c: usb-c {
+			i2c-port = <&i2c2>;
+			enum-names = "I2C_PORT_USB_C";
+		};
+		i2c_detachable_base: detachable-base {
+			i2c-port = <&i2c4>;
+			enum-names = "I2C_PORT_DETACHABLE_BASE";
+		};
+	};
+
+};
+
+&pinctrl {
+	i2c3_clk_gpf2_sleep: i2c3_clk_gpf2_sleep {
+		pinmuxs = <&pinctrlf 2 IT8XXX2_ALT_DEFAULT>;
+	};
+	i2c3_data_gpf3_sleep: i2c3_data_gpf3_sleep {
+		pinmuxs = <&pinctrlf 3 IT8XXX2_ALT_DEFAULT>;
+	};
+};
+
+&i2c0 {
+	/* I2C_PWR_CBI */
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c0_clk_gpb3_default
+		     &i2c0_data_gpb4_default>;
+	pinctrl-names = "default";
+
+	cbi_eeprom: eeprom@50 {
+		compatible = "atmel,at24";
+		reg = <0x50>;
+		size = <2048>;
+		pagesize = <16>;
+		address-width = <8>;
+		timeout = <5>;
+	};
+
+	charger: rt9490@53 {
+		compatible = "richtek,rt9490";
+		status = "okay";
+		reg = <0x53>;
+	};
+};
+
+&i2c1 {
+	/* I2C_BATTERY */
+	status = "okay";
+	clock-frequency = <50000>;
+	pinctrl-0 = <&i2c1_clk_gpc1_default
+		     &i2c1_data_gpc2_default>;
+	pinctrl-names = "default";
+	fifo-enable;
+};
+
+&i2c2 {
+	/* I2C_USB_C */
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c2_clk_gpf6_default
+		     &i2c2_data_gpf7_default>;
+	pinctrl-names = "default";
+	/delete-property/ fifo-enable;
+
+	ppc_port0: rt1739@70 {
+		compatible = "richtek,rt1739-ppc";
+		status = "okay";
+		reg = <0x70>;
+	};
+
+	tusb546_mux_0: tusb546-mux-0@44 {
+		compatible = "ti,tusb1064";
+		reg = <0x44>;
+	};
+
+	ppc_port1: syv682x@40 {
+		compatible = "silergy,syv682x";
+		status = "okay";
+		reg = <0x40>;
+		frs_en_gpio = <&usb_c1_frs_en>;
+	};
+
+	ps8743_mux_1: ps8743-mux-1@10 {
+		compatible = "parade,ps8743";
+		reg = <0x10>;
+	};
+};
+
+&i2c3 {
+	/* I2C_SENSOR */
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	scl-gpios = <&gpiof 2 0>;
+	sda-gpios = <&gpiof 3 0>;
+	pinctrl-0 = <&i2c3_clk_gpf2_default
+		     &i2c3_data_gpf3_default>;
+	pinctrl-1 = <&i2c3_clk_gpf2_sleep
+		     &i2c3_data_gpf3_sleep>;
+	pinctrl-names = "default", "sleep";
+	prescale-scl-low = <1>;
+};
+
+/* TODO(b/260377762): peripheral mode */
+&i2c4 {
+	/* I2C_DETACHABLE_BASE */
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c4_clk_gpe0_default
+		     &i2c4_data_gpe7_default>;
+	pinctrl-names = "default";
+	prescale-scl-low = <1>;
+};
diff --git a/zephyr/program/geralt/interrupts.dtsi b/zephyr/program/geralt/interrupts.dtsi
new file mode 100644
index 0000000000..8841eb6e1a
--- /dev/null
+++ b/zephyr/program/geralt/interrupts.dtsi
@@ -0,0 +1,110 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	aliases {
+		int-wp = &int_wp;
+	};
+
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_lid_360: lid-360-l {
+			irq-pin = <&lid_360_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "gmr_tablet_switch_isr";
+		};
+		int_ap_in_sleep: ap-in-sleep {
+			irq-pin = <&ap_in_sleep_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_lid_imu: lid-imu {
+			irq-pin = <&lid_imu_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "bmi3xx_interrupt";
+		};
+		int_ap_wdtrst: ap-wdtrst {
+			irq-pin = <&ap_ec_wdtrst_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "chipset_watchdog_interrupt";
+		};
+		int_usb_c0_ppc_bc12: usb-c0-ppc-bc12 {
+			irq-pin = <&usb_c0_ppc_bc12_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "ppc_interrupt";
+		};
+		int_volume_up: volume-up {
+			irq-pin = <&volume_up_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+		int_volume_down: volume-down {
+			irq-pin = <&volume_down_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+		int_ac_present: ac-present {
+			irq-pin = <&ac_present>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "extpower_interrupt";
+		};
+		int_lid_open: lid-open {
+			irq-pin = <&lid_open>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "lid_interrupt";
+		};
+		int_power_button: power-button {
+			irq-pin = <&power_button_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_button_interrupt";
+		};
+		int_pg_pp4200_s5: pg-pp4200-s5 {
+			irq-pin = <&pg_pp4200_s5_od>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_warm_rst: warm-rst {
+			irq-pin = <&ap_ec_warm_rst_req>;
+			flags = <GPIO_INT_EDGE_RISING>;
+			handler = "chipset_reset_request_interrupt";
+		};
+		int_pmic_ec_resetb: pmic-ec-resetb {
+			irq-pin = <&pmic_ec_resetb>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_ap_in_rst: ap-in-rst {
+			irq-pin = <&ap_sysrst_odl_r>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_wp: wp {
+			irq-pin = <&ec_flash_wp_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "switch_interrupt";
+		};
+		int_spi0_cs: spi0-cs {
+			irq-pin = <&spi0_cs>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "spi_event";
+		};
+		int_usb_c1_ppc: usb-c1-ppc {
+			irq-pin = <&usb_c1_ppc_int_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "ppc_interrupt";
+		};
+		int_ccd_mode_odl: ccd-mode-odl {
+			irq-pin = <&gpio_ccd_mode_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "ccd_interrupt";
+		};
+		int_ap_xhci_init_done: ap-xhci-init-done {
+			irq-pin = <&ap_xhci_init_done>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "xhci_interrupt";
+		};
+	};
+};
diff --git a/zephyr/program/geralt/keyboard.dtsi b/zephyr/program/geralt/keyboard.dtsi
new file mode 100644
index 0000000000..9541c4aa81
--- /dev/null
+++ b/zephyr/program/geralt/keyboard.dtsi
@@ -0,0 +1,30 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+&cros_kb_raw {
+	status = "okay";
+	/* No KSO2 (it's inverted and implemented by GPIO) */
+	pinctrl-0 = <&ksi0_default
+		     &ksi1_default
+		     &ksi2_default
+		     &ksi3_default
+		     &ksi4_default
+		     &ksi5_default
+		     &ksi6_default
+		     &ksi7_default
+		     &kso0_default
+		     &kso1_default
+		     &kso3_default
+		     &kso4_default
+		     &kso5_default
+		     &kso6_default
+		     &kso7_default
+		     &kso8_default
+		     &kso9_default
+		     &kso10_default
+		     &kso11_default
+		     &kso12_default>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/geralt/mkbp.dtsi b/zephyr/program/geralt/mkbp.dtsi
new file mode 100644
index 0000000000..1f66474af5
--- /dev/null
+++ b/zephyr/program/geralt/mkbp.dtsi
@@ -0,0 +1,25 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/wake_mask_event_defines.h>
+
+/ {
+	ec-mkbp-host-event-wakeup-mask {
+		compatible = "cros-ec,mkbp-host-event-wakeup-mask";
+		wakeup-mask = <(
+			HOST_EVENT_AC_CONNECTED |
+			HOST_EVENT_AC_DISCONNECTED |
+			HOST_EVENT_LID_OPEN |
+			HOST_EVENT_POWER_BUTTON |
+			HOST_EVENT_HANG_DETECT |
+			HOST_EVENT_MODE_CHANGE)>;
+	};
+
+	ec-mkbp-event-wakeup-mask {
+		compatible = "cros-ec,mkbp-event-wakeup-mask";
+		wakeup-mask = <(MKBP_EVENT_KEY_MATRIX |
+				MKBP_EVENT_HOST_EVENT)>;
+	};
+};
diff --git a/zephyr/program/geralt/motionsense.dtsi b/zephyr/program/geralt/motionsense.dtsi
new file mode 100644
index 0000000000..1446d1cb22
--- /dev/null
+++ b/zephyr/program/geralt/motionsense.dtsi
@@ -0,0 +1,109 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/motionsense/utils.h>
+
+
+/ {
+	aliases {
+		/*
+		 * motion sense's <>_INT_EVENT is handled
+		 * by alias. Using the alias, each driver creates
+		 * its own <>_INT_EVENT.
+		 */
+		bmi3xx-int = &lid_accel;
+	};
+
+	/*
+	 * Declare mutexes used by sensor drivers.
+	 * A mutex node is used to create an instance of mutex_t.
+	 * A mutex node is referenced by a sensor node if the
+	 * corresponding sensor driver needs to use the
+	 * instance of the mutex.
+	 */
+	motionsense-mutex {
+		compatible = "cros-ec,motionsense-mutex";
+		lid_mutex: lid-mutex {
+		};
+	};
+
+	/* Rotation matrix used by drivers. */
+	motionsense-rotation-ref {
+		compatible = "cros-ec,motionsense-rotation-ref";
+		lid_rot_ref: lid-rotation-ref {
+			mat33 = <1 0 0
+				 0 1 0
+				 0 0 1>;
+		};
+	};
+
+	/*
+	 * Driver specific data. A driver-specific data can be shared with
+	 * different motion sensors while they are using the same driver.
+	 *
+	 * If a node's compatible starts with "cros-ec,accelgyro-", it is for
+	 * a common structure defined in accelgyro.h.
+	 * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for
+	 * "struct als_drv_data_t" in accelgyro.h
+	 */
+	motionsense-sensor-data {
+		bmi323_data: bmi323-drv-data {
+			compatible = "cros-ec,drvdata-bmi3xx";
+			status = "okay";
+		};
+	};
+
+	/*
+	 * List of motion sensors that creates motion_sensors array.
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
+	 * motion sensor IDs for lid angle calculation.
+	 */
+	motionsense-sensor {
+		lid_accel: lid-accel {
+			compatible = "cros-ec,bmi3xx-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&lid_mutex>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&lid_rot_ref>;
+			default-range = <2>;
+			drv-data = <&bmi323_data>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		lid_gyro: lid-gyro {
+			compatible = "cros-ec,bmi3xx-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&lid_mutex>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&lid_rot_ref>;
+			drv-data = <&bmi323_data>;
+		};
+	};
+
+	motionsense-sensor-info {
+		compatible = "cros-ec,motionsense-sensor-info";
+
+		/*
+		 * list of GPIO interrupts that have to
+		 * be enabled at initial stage
+		 */
+		sensor-irqs = <&int_lid_imu>;
+	};
+};
diff --git a/zephyr/program/geralt/power_signal.dtsi b/zephyr/program/geralt/power_signal.dtsi
new file mode 100644
index 0000000000..5adeb682fb
--- /dev/null
+++ b/zephyr/program/geralt/power_signal.dtsi
@@ -0,0 +1,35 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	power_signal_list: power-signal-list {
+		compatible = "mediatek,mt8188-power-signal-list";
+
+		ap_in_rst {
+			power-enum-name = "AP_IN_RST";
+			power-gpio-pin = <&ap_sysrst_odl_r>;
+		};
+		ap_in_s3 {
+			power-enum-name = "AP_IN_S3";
+			power-gpio-pin = <&ap_in_sleep_l>;
+		};
+		ap_wdt_asserted {
+			power-enum-name = "AP_WDT_ASSERTED";
+			power-gpio-pin = <&ap_ec_wdtrst_l>;
+		};
+		ap_warm_rst_req {
+			power-enum-name = "AP_WARM_RST_REQ";
+			power-gpio-pin = <&ap_ec_warm_rst_req>;
+		};
+		pg_pp4200_s5 {
+			power-enum-name = "PG_PP4200_S5";
+			power-gpio-pin = <&pg_pp4200_s5_od>;
+		};
+		pmic_ap_reset {
+			power-enum-name = "PMIC_AP_RST";
+			power-gpio-pin = <&pmic_ec_resetb>;
+		};
+	};
+};
diff --git a/zephyr/program/geralt/program.conf b/zephyr/program/geralt/program.conf
new file mode 100644
index 0000000000..724b261ae6
--- /dev/null
+++ b/zephyr/program/geralt/program.conf
@@ -0,0 +1,166 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+
+# TODO(b:251747125) allocate a new PID
+# http://google3/hardware/standards/usb/
+CONFIG_PLATFORM_EC_USB_PID=0x5566
+
+# Bring up options
+CONFIG_SHELL_HISTORY_BUFFER=256
+CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y
+CONFIG_PLATFORM_EC_BRINGUP=y
+
+# CROS EC
+CONFIG_CROS_EC=y
+CONFIG_PLATFORM_EC=y
+CONFIG_PLATFORM_EC_SWITCH=y
+CONFIG_SHIMMED_TASKS=y
+
+# AP SoC configuration
+CONFIG_AP=y
+CONFIG_AP_ARM_MTK_MT8188=y
+
+# Shell features
+CONFIG_KERNEL_SHELL=y
+CONFIG_SHELL_HELP=y
+CONFIG_SHELL_HISTORY=y
+CONFIG_SHELL_TAB=y
+CONFIG_SHELL_TAB_AUTOCOMPLETION=y
+
+# CBI
+CONFIG_EEPROM=y
+CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=y
+
+# Keyboard
+CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_MKBP=y
+CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED=y
+
+# MKBP
+CONFIG_PLATFORM_EC_MKBP_EVENT=y
+CONFIG_PLATFORM_EC_MKBP_INPUT_DEVICES=y
+CONFIG_PLATFORM_EC_MKBP_USE_GPIO=y
+
+# EFS2
+CONFIG_PLATFORM_EC_VBOOT_EFS2=y
+
+# USB
+CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=n
+CONFIG_PLATFORM_EC_USB_PD_USB32_DRD=n
+CONFIG_PLATFORM_EC_USB_PD_USB4=n
+
+# USB-C
+CONFIG_PLATFORM_EC_USBC=y
+CONFIG_PLATFORM_EC_USBC_SS_MUX_DFP_ONLY=y
+CONFIG_PLATFORM_EC_USB_PD_DPS=y
+CONFIG_PLATFORM_EC_USB_PD_DP_HPD_GPIO=y
+CONFIG_PLATFORM_EC_USB_PD_DP_HPD_GPIO_CUSTOM=y
+CONFIG_PLATFORM_EC_USB_PD_FRS=y
+CONFIG_PLATFORM_EC_USB_PD_CLEAR_HARD_RESET_STATUS=y
+
+# Power Seq
+CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK=y
+CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK=y
+CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y
+CONFIG_PLATFORM_EC_POWERSEQ=y
+CONFIG_PLATFORM_EC_POWERSEQ_HOST_SLEEP=y
+CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n
+CONFIG_PLATFORM_EC_POWER_SLEEP_FAILURE_DETECTION=y
+
+# Optional features
+CONFIG_FLASH_SHELL=n
+CONFIG_LTO=n
+
+# EEPROM
+CONFIG_PLATFORM_EC_EEPROM_CBI_WP=y
+
+# Host Commands
+CONFIG_PLATFORM_EC_HOSTCMD=y
+
+# Battery
+CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y
+CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y
+CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO=y
+CONFIG_PLATFORM_EC_BATTERY_SMART=y
+CONFIG_PLATFORM_EC_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV=9000
+CONFIG_PLATFORM_EC_I2C_PASSTHRU_RESTRICTED=y
+CONFIG_PLATFORM_EC_I2C_VIRTUAL_BATTERY=y
+CONFIG_PLATFORM_EC_I2C_NACK_RETRY_COUNT=5
+CONFIG_PLATFORM_EC_SMBUS_PEC=y
+
+# Charger
+CONFIG_PLATFORM_EC_CHARGE_MANAGER=y
+# b:257167723: Adapter output current exceeds the spec on heavy-load.
+# Preserve a margin in case of charger overdraw.
+CONFIG_PLATFORM_EC_CHARGER_INPUT_CURRENT_DERATE_PCT=3
+CONFIG_PLATFORM_EC_CHARGE_RAMP_HW=y
+CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y
+CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC_CHARGER=y
+CONFIG_PLATFORM_EC_CHARGER_MAINTAIN_VBAT=y
+CONFIG_PLATFORM_EC_CHARGER_PSYS=y
+CONFIG_PLATFORM_EC_CHARGER_PSYS_READ=y
+# BOARD_RS2
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10
+# BOARD_RS1
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=20
+CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_DUMP=y
+
+# Button
+CONFIG_PLATFORM_EC_CMD_BUTTON=y
+CONFIG_PLATFORM_EC_POWER_BUTTON=y
+CONFIG_PLATFORM_EC_VOLUME_BUTTONS=y
+CONFIG_PLATFORM_EC_BUTTON_TRIGGERED_RECOVERY=y
+
+# Lid Switch
+CONFIG_PLATFORM_EC_LID_SWITCH=y
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
+
+# Host Commands
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_ADC_AMON_BMON=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_SYSINFO=y
+CONFIG_PLATFORM_EC_HOST_COMMAND_STATUS=y
+
+# PWM
+CONFIG_PWM=y
+
+# Sensors
+CONFIG_PLATFORM_EC_ACCEL_FIFO=y
+CONFIG_PLATFORM_EC_GMR_TABLET_MODE=y
+CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=y
+CONFIG_PLATFORM_EC_TABLET_MODE=y
+CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=y
+CONFIG_PLATFORM_EC_MAX_SENSOR_FREQ_MILLIHZ=100000
+
+# Sensor Drivers
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y
+
+# Tasks
+CONFIG_TASK_CHARGER_STACK_SIZE=1024
+CONFIG_TASK_CHIPSET_STACK_SIZE=1440
+CONFIG_TASK_MOTIONSENSE_STACK_SIZE=1024
+CONFIG_TASK_PD_STACK_SIZE=1280
+
+# USB-C
+CONFIG_PLATFORM_EC_USB_CHARGER=n
+CONFIG_PLATFORM_EC_USBC_PPC_SYV682C=y
+CONFIG_PLATFORM_EC_USB_MUX_TUSB546=y
+CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y
+CONFIG_PLATFORM_EC_USB_PD_FRS_PPC=y
+CONFIG_PLATFORM_EC_USB_PD_LOGGING=y
+CONFIG_PLATFORM_EC_IT83XX_TUNE_CC_PHY=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_PPC=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_ADC_EACH_PORT=y
+CONFIG_PLATFORM_EC_USB_PD_DUAL_ROLE_AUTO_TOGGLE=n
+CONFIG_PLATFORM_EC_CONFIG_USB_PD_3A_PORTS=0
+CONFIG_PLATFORM_EC_CONSOLE_CMD_TCPC_DUMP=n
+
+# ADC
+CONFIG_ADC_IT8XXX2_VOL_FULL_SCALE=y
+
+# Detachable
+CONFIG_PLATFORM_EC_DETACHABLE_BASE=y
+CONFIG_PLATFORM_EC_BASE_ATTACHED_SWITCH=y
diff --git a/zephyr/program/geralt/shi.dtsi b/zephyr/program/geralt/shi.dtsi
new file mode 100644
index 0000000000..1a21a3ffb8
--- /dev/null
+++ b/zephyr/program/geralt/shi.dtsi
@@ -0,0 +1,15 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <ite/it8xxx2-pinctrl-map.dtsi>
+
+&shi0 {
+	status = "okay";
+	pinctrl-0 = <&shi_mosi_gpm0_default &shi_miso_gpm1_default
+		     &shi_clk_gpm4_default &shi_cs_gpm5_default>;
+	pinctrl-names = "default";
+	/* unused but needed by dt binding */
+	cs-gpios = <&gpiom 5 GPIO_VOLTAGE_1P8>;
+};
diff --git a/zephyr/program/geralt/src/backlight.c b/zephyr/program/geralt/src/backlight.c
new file mode 100644
index 0000000000..cf03df4cd2
--- /dev/null
+++ b/zephyr/program/geralt/src/backlight.c
@@ -0,0 +1,49 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "gpio_signal.h"
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/init.h>
+
+#include <ap_power/ap_power.h>
+
+static void board_backlight_handler(struct ap_power_ev_callback *cb,
+				    struct ap_power_ev_data data)
+{
+	int value;
+
+	switch (data.event) {
+	default:
+		return;
+
+	case AP_POWER_RESUME:
+		/* Called on AP S3 -> S0 transition */
+		value = 1;
+		break;
+
+	case AP_POWER_SUSPEND:
+		/* Called on AP S0 -> S3 transition */
+		value = 0;
+		break;
+	}
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_bl_en_od), value);
+}
+
+static int install_backlight_handler(void)
+{
+	static struct ap_power_ev_callback cb;
+
+	/*
+	 * Add a callback for suspend/resume to
+	 * control the keyboard backlight.
+	 */
+	ap_power_ev_init_callback(&cb, board_backlight_handler,
+				  AP_POWER_RESUME | AP_POWER_SUSPEND);
+	ap_power_ev_add_callback(&cb);
+	return 0;
+}
+
+SYS_INIT(install_backlight_handler, APPLICATION, 1);
diff --git a/zephyr/program/geralt/src/base_detect.c b/zephyr/program/geralt/src/base_detect.c
new file mode 100644
index 0000000000..58527e5ab2
--- /dev/null
+++ b/zephyr/program/geralt/src/base_detect.c
@@ -0,0 +1,124 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc.h"
+#include "ap_power/ap_power.h"
+#include "base_state.h"
+#include "chipset.h"
+#include "console.h"
+#include "hooks.h"
+#include "tablet_mode.h"
+
+#include <zephyr/drivers/gpio.h>
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+
+#define BASE_DETECT_INTERVAL (200 * MSEC)
+#define ATTACH_MAX_THRESHOLD_MV 300
+#define DETACH_MIN_THRESHOLD_MV 3000
+
+static void base_update(bool attached)
+{
+	const struct gpio_dt_spec *en_cc_lid_base_pu =
+		GPIO_DT_FROM_NODELABEL(en_cc_lid_base_pu);
+
+	base_set_state(attached);
+	tablet_set_mode(!attached, TABLET_TRIGGER_BASE);
+
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(en_ppvar_base_x), attached);
+	gpio_pin_configure(en_cc_lid_base_pu->port, en_cc_lid_base_pu->pin,
+			   attached ? GPIO_OUTPUT_HIGH : GPIO_INPUT);
+}
+
+static void base_detect_tick(void);
+DECLARE_DEFERRED(base_detect_tick);
+
+static void base_detect_tick(void)
+{
+	static bool debouncing;
+	int mv = adc_read_channel(ADC_BASE_DET);
+
+	if (mv >= DETACH_MIN_THRESHOLD_MV && base_get_state()) {
+		if (!debouncing) {
+			debouncing = true;
+		} else {
+			debouncing = false;
+			base_update(false);
+		}
+	} else if (mv <= ATTACH_MAX_THRESHOLD_MV && !base_get_state()) {
+		if (!debouncing) {
+			debouncing = true;
+		} else {
+			debouncing = false;
+			base_update(true);
+		}
+	} else {
+		debouncing = false;
+	}
+	hook_call_deferred(&base_detect_tick_data, BASE_DETECT_INTERVAL);
+}
+
+static void base_detect_enable(bool enable)
+{
+	if (enable) {
+		hook_call_deferred(&base_detect_tick_data,
+				   BASE_DETECT_INTERVAL);
+	} else {
+		hook_call_deferred(&base_detect_tick_data, -1);
+		base_update(false);
+	}
+}
+
+static void base_startup_hook(struct ap_power_ev_callback *cb,
+			      struct ap_power_ev_data data)
+{
+	switch (data.event) {
+	case AP_POWER_STARTUP:
+		base_detect_enable(true);
+		break;
+	case AP_POWER_SHUTDOWN:
+		base_detect_enable(false);
+		break;
+	default:
+		return;
+	}
+}
+
+static int base_init(void)
+{
+	static struct ap_power_ev_callback cb;
+
+	base_update(false);
+
+	ap_power_ev_init_callback(&cb, base_startup_hook,
+				  AP_POWER_STARTUP | AP_POWER_SHUTDOWN);
+	ap_power_ev_add_callback(&cb);
+
+	if (!chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
+		base_detect_enable(true);
+	}
+
+	return 0;
+}
+
+SYS_INIT(base_init, APPLICATION, 1);
+
+void base_force_state(enum ec_set_base_state_cmd state)
+{
+	switch (state) {
+	case EC_SET_BASE_STATE_ATTACH:
+		base_detect_enable(false);
+		base_update(true);
+		break;
+	case EC_SET_BASE_STATE_DETACH:
+		base_detect_enable(false);
+		base_update(false);
+		break;
+	case EC_SET_BASE_STATE_RESET:
+		base_detect_enable(true);
+		break;
+	}
+}
diff --git a/zephyr/program/geralt/src/ccd_mode.c b/zephyr/program/geralt/src/ccd_mode.c
new file mode 100644
index 0000000000..ec94899561
--- /dev/null
+++ b/zephyr/program/geralt/src/ccd_mode.c
@@ -0,0 +1,48 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "system.h"
+#include "typec_control.h"
+
+#define CPRINTS(format, args...) cprints(CC_USB, format, ##args)
+
+static void ccd_interrupt_deferred(void)
+{
+	/*
+	 * If CCD_MODE_ODL asserts, it means there's a debug accessory connected
+	 * and we should enable the SBU FETs.
+	 */
+	typec_set_sbu(CONFIG_CCD_USBC_PORT_NUMBER, 1);
+
+	/* Mux DP AUX away when CCD enabled to prevent the AUX channel
+	 * interferes the SBU pins.
+	 */
+	CPRINTS("CCD Enabled, mux DP_PATH_SEL to 1");
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(dp_path_sel), 1);
+}
+DECLARE_DEFERRED(ccd_interrupt_deferred);
+
+void ccd_interrupt(enum gpio_signal signal)
+{
+	hook_call_deferred(&ccd_interrupt_deferred_data, 0);
+}
+
+static void ccd_mode_init(void)
+{
+	/* If CCD mode has enabled before init, force the ccd_interrupt. */
+	if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_ccd_mode_odl))) {
+		ccd_interrupt(GPIO_CCD_MODE_ODL);
+	}
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_ccd_mode_odl));
+}
+DECLARE_HOOK(HOOK_INIT, ccd_mode_init, HOOK_PRIO_PRE_DEFAULT);
+
+__override void board_pulse_entering_rw(void)
+{
+	/* no-op for dauntless */
+}
diff --git a/zephyr/program/geralt/src/dp_alt_mode.c b/zephyr/program/geralt/src/dp_alt_mode.c
new file mode 100644
index 0000000000..a8bf0db6d3
--- /dev/null
+++ b/zephyr/program/geralt/src/dp_alt_mode.c
@@ -0,0 +1,216 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "chipset.h"
+#include "console.h"
+#include "hooks.h"
+#include "timer.h"
+#include "typec_control.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+
+static int active_aux_port = -1;
+
+static void set_dp_path_sel(int port)
+{
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(dp_path_sel), port);
+	CPRINTS("Set DP_AUX_PATH_SEL: %d", port);
+}
+
+int svdm_get_hpd_gpio(int port)
+{
+	/* HPD is low active, inverse the result */
+	return !gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(ec_ap_dp_hpd_odl));
+}
+
+static void reset_aux_deferred(void)
+{
+	if (active_aux_port == -1)
+		/* reset to 1 for lower power consumption. */
+		set_dp_path_sel(1);
+}
+DECLARE_DEFERRED(reset_aux_deferred);
+
+void svdm_set_hpd_gpio(int port, int en)
+{
+	/*
+	 * HPD is low active, inverse the en.
+	 *
+	 * Implement FCFS policy:
+	 * 1) Enable hpd if no active port.
+	 * 2) Disable hpd if active port is the given port.
+	 */
+	if (en && active_aux_port < 0) {
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(ec_ap_dp_hpd_odl), 0);
+		active_aux_port = port;
+		hook_call_deferred(&reset_aux_deferred_data, -1);
+	}
+
+	if (!en && active_aux_port == port) {
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(ec_ap_dp_hpd_odl), 1);
+		active_aux_port = -1;
+		/*
+		 * This might be a HPD debounce to send a HPD IRQ (500us), so
+		 * do not reset the aux path immediately. Defer this call and
+		 * re-check if this is a real disable.
+		 */
+		hook_call_deferred(&reset_aux_deferred_data, 1 * MSEC);
+	}
+}
+
+__override int svdm_dp_config(int port, uint32_t *payload)
+{
+	int opos = pd_alt_mode(port, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT);
+	uint8_t pin_mode = get_dp_pin_mode(port);
+	mux_state_t mux_mode = svdm_dp_get_mux_mode(port);
+	int mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]);
+
+	if (!pin_mode) {
+		return 0;
+	}
+
+	CPRINTS("pin_mode: %x, mf: %d, mux: %d", pin_mode, mf_pref, mux_mode);
+	/*
+	 * Defer setting the usb_mux until HPD goes high, svdm_dp_attention().
+	 * The AP only supports one DP phy. An external DP mux switches between
+	 * the two ports. Should switch those muxes when it is really used,
+	 * i.e. HPD high; otherwise, the real use case is preempted, like:
+	 *  (1) plug a dongle without monitor connected to port-0,
+	 *  (2) plug a dongle without monitor connected to port-1,
+	 *  (3) plug a monitor to the port-1 dongle.
+	 */
+
+	payload[0] =
+		VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_CONFIG | VDO_OPOS(opos));
+	payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */
+				1, /* DPv1.3 signaling */
+				2); /* UFP connected */
+	return 2;
+};
+
+__override void svdm_dp_post_config(int port)
+{
+	mux_state_t mux_mode = svdm_dp_get_mux_mode(port);
+
+	typec_set_sbu(port, true);
+
+	/*
+	 * Prior to post-config, the mux will be reset to safe mode, and this
+	 * will break mux config and aux path config we did in the first DP
+	 * status command. Only enable this if the port is the current aux-port.
+	 */
+	if (port == active_aux_port) {
+		usb_mux_set(port, mux_mode, USB_SWITCH_CONNECT,
+			    polarity_rm_dts(pd_get_polarity(port)));
+		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+	}
+
+	dp_flags[port] |= DP_FLAGS_DP_ON;
+}
+
+static int is_dp_muxable(int port)
+{
+	int i;
+
+	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+		if (i != port) {
+			if (usb_mux_get(i) & USB_PD_MUX_DP_ENABLED) {
+				return 0;
+			}
+		}
+	}
+
+	return 1;
+}
+
+__override int svdm_dp_attention(int port, uint32_t *payload)
+{
+	int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]);
+	int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]);
+#ifdef CONFIG_USB_PD_DP_HPD_GPIO
+	int cur_lvl = svdm_get_hpd_gpio(port);
+#endif /* CONFIG_USB_PD_DP_HPD_GPIO */
+	mux_state_t mux_state, mux_mode;
+
+	mux_mode = svdm_dp_get_mux_mode(port);
+	dp_status[port] = payload[1];
+
+	if (!is_dp_muxable(port)) {
+		/* TODO(waihong): Info user? */
+		CPRINTS("p%d: The other port is already muxed.", port);
+		return 0; /* nak */
+	}
+
+	if (lvl) {
+		set_dp_path_sel(port);
+
+		usb_mux_set(port, mux_mode, USB_SWITCH_CONNECT,
+			    polarity_rm_dts(pd_get_polarity(port)));
+	} else {
+		usb_mux_set(port, USB_PD_MUX_USB_ENABLED, USB_SWITCH_CONNECT,
+			    polarity_rm_dts(pd_get_polarity(port)));
+	}
+
+	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && (irq || lvl)) {
+		/*
+		 * Wake up the AP.  IRQ or level high indicates a DP sink is now
+		 * present.
+		 */
+		if (IS_ENABLED(CONFIG_MKBP_EVENT)) {
+			pd_notify_dp_alt_mode_entry(port);
+		}
+	}
+
+#ifdef CONFIG_USB_PD_DP_HPD_GPIO
+	if (irq && !lvl) {
+		/*
+		 * IRQ can only be generated when the level is high, because
+		 * the IRQ is signaled by a short low pulse from the high level.
+		 */
+		CPRINTF("ERR:HPD:IRQ&LOW\n");
+		return 0; /* nak */
+	}
+
+	if (irq && cur_lvl) {
+		uint64_t now = get_time().val;
+		/* wait for the minimum spacing between IRQ_HPD if needed */
+		if (now < svdm_hpd_deadline[port]) {
+			usleep(svdm_hpd_deadline[port] - now);
+		}
+
+		/* generate IRQ_HPD pulse */
+		svdm_set_hpd_gpio(port, 0);
+		/*
+		 * b/171172053#comment14: since the HPD_DSTREAM_DEBOUNCE_IRQ is
+		 * very short (500us), we can use udelay instead of usleep for
+		 * more stable pulse period.
+		 */
+		udelay(HPD_DSTREAM_DEBOUNCE_IRQ);
+		svdm_set_hpd_gpio(port, 1);
+	} else {
+		svdm_set_hpd_gpio(port, lvl);
+	}
+
+	/* set the minimum time delay (2ms) for the next HPD IRQ */
+	svdm_hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
+#endif /* CONFIG_USB_PD_DP_HPD_GPIO */
+
+	mux_state = (lvl ? USB_PD_MUX_HPD_LVL : USB_PD_MUX_HPD_LVL_DEASSERTED) |
+		    (irq ? USB_PD_MUX_HPD_IRQ : USB_PD_MUX_HPD_IRQ_DEASSERTED);
+	usb_mux_hpd_update(port, mux_state);
+
+#ifdef USB_PD_PORT_TCPC_MST
+	if (port == USB_PD_PORT_TCPC_MST) {
+		baseboard_mst_enable_control(port, lvl);
+	}
+#endif
+
+	/* ack */
+	return 1;
+}
diff --git a/zephyr/program/geralt/src/hibernate.c b/zephyr/program/geralt/src/hibernate.c
new file mode 100644
index 0000000000..fb70248338
--- /dev/null
+++ b/zephyr/program/geralt/src/hibernate.c
@@ -0,0 +1,16 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "system.h"
+
+#include <zephyr/drivers/gpio.h>
+
+/* Geralt board specific hibernate implementation */
+__override void board_hibernate_late(void)
+{
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(en_pp5000_z1_l), 1);
+	/* It takes around 30ms to release the PP5000 capacitance. */
+	udelay(30 * MSEC);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(en_ulp), 1);
+}
diff --git a/zephyr/program/geralt/src/hooks.c b/zephyr/program/geralt/src/hooks.c
new file mode 100644
index 0000000000..c5c769e8f9
--- /dev/null
+++ b/zephyr/program/geralt/src/hooks.c
@@ -0,0 +1,97 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charger.h"
+#include "driver/charger/rt9490.h"
+#include "extpower.h"
+#include "gpio/gpio_int.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/init.h>
+
+#include <ap_power/ap_power.h>
+
+#define I2C3_NODE DT_NODELABEL(i2c3)
+PINCTRL_DT_DEFINE(I2C3_NODE);
+
+static void board_i2c3_ctrl(bool enable)
+{
+	if (DEVICE_DT_GET(
+		    DT_GPIO_CTLR_BY_IDX(DT_NODELABEL(i2c3), scl_gpios, 0)) ==
+	    DEVICE_DT_GET(DT_NODELABEL(gpiof))) {
+		const struct pinctrl_dev_config *pcfg =
+			PINCTRL_DT_DEV_CONFIG_GET(I2C3_NODE);
+
+		if (enable) {
+			pinctrl_apply_state(pcfg, PINCTRL_STATE_DEFAULT);
+		} else {
+			pinctrl_apply_state(pcfg, PINCTRL_STATE_SLEEP);
+		}
+	}
+}
+
+static void geralt_common_init(void)
+{
+	gpio_enable_dt_interrupt(
+		GPIO_INT_FROM_NODELABEL(int_ap_xhci_init_done));
+}
+DECLARE_HOOK(HOOK_INIT, geralt_common_init, HOOK_PRIO_PRE_DEFAULT);
+
+static void board_enable_i2c3(void)
+{
+	board_i2c3_ctrl(1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_PRE_INIT, board_enable_i2c3, HOOK_PRIO_FIRST);
+
+static void board_disable_i2c3(void)
+{
+	board_i2c3_ctrl(0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_HARD_OFF, board_disable_i2c3, HOOK_PRIO_LAST);
+
+static void board_suspend_handler(struct ap_power_ev_callback *cb,
+				  struct ap_power_ev_data data)
+{
+	int value;
+
+	switch (data.event) {
+	default:
+		return;
+
+	case AP_POWER_RESUME:
+		value = 1;
+		break;
+
+	case AP_POWER_SUSPEND:
+		value = 0;
+		break;
+	}
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_en_5v_usm), value);
+}
+
+static int install_suspend_handler(void)
+{
+	static struct ap_power_ev_callback cb;
+
+	/*
+	 * Add a callback for suspend/resume.
+	 */
+	ap_power_ev_init_callback(&cb, board_suspend_handler,
+				  AP_POWER_RESUME | AP_POWER_SUSPEND);
+	ap_power_ev_add_callback(&cb);
+	return 0;
+}
+
+SYS_INIT(install_suspend_handler, APPLICATION, 1);
+
+static void board_hook_ac_change(void)
+{
+	rt9490_enable_adc(CHARGER_SOLO, extpower_is_present());
+}
+DECLARE_HOOK(HOOK_AC_CHANGE, board_hook_ac_change, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_INIT, board_hook_ac_change, HOOK_PRIO_LAST);
diff --git a/zephyr/program/geralt/src/i2c.c b/zephyr/program/geralt/src/i2c.c
new file mode 100644
index 0000000000..fe08b603ce
--- /dev/null
+++ b/zephyr/program/geralt/src/i2c.c
@@ -0,0 +1,19 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "i2c.h"
+#include "i2c/i2c.h"
+
+/* Geralt board specific i2c implementation */
+
+#ifdef CONFIG_PLATFORM_EC_I2C_PASSTHRU_RESTRICTED
+int board_allow_i2c_passthru(const struct i2c_cmd_desc_t *cmd_desc)
+{
+	return (i2c_get_device_for_port(cmd_desc->port) ==
+			i2c_get_device_for_port(I2C_PORT_VIRTUAL_BATTERY) ||
+		i2c_get_device_for_port(cmd_desc->port) ==
+			i2c_get_device_for_port(I2C_PORT_EEPROM));
+}
+#endif
diff --git a/zephyr/program/geralt/src/ppc.c b/zephyr/program/geralt/src/ppc.c
new file mode 100644
index 0000000000..00efa23976
--- /dev/null
+++ b/zephyr/program/geralt/src/ppc.c
@@ -0,0 +1,29 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "gpio/gpio_int.h"
+#include "usbc_ppc.h"
+
+#include <zephyr/init.h>
+
+static int board_usbc_init(void)
+{
+	/* Enable PPC interrupts. */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_ppc_bc12));
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_ppc));
+
+	return 0;
+}
+SYS_INIT(board_usbc_init, APPLICATION, 1);
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	if (signal == GPIO_SIGNAL(DT_NODELABEL(usb_c0_ppc_bc12_int_odl))) {
+		ppc_chips[0].drv->interrupt(0);
+	}
+	if (signal == GPIO_SIGNAL(DT_NODELABEL(usb_c1_ppc_int_odl))) {
+		ppc_chips[1].drv->interrupt(1);
+	}
+}
diff --git a/zephyr/program/geralt/src/usb_pd_policy.c b/zephyr/program/geralt/src/usb_pd_policy.c
new file mode 100644
index 0000000000..72558b50d6
--- /dev/null
+++ b/zephyr/program/geralt/src/usb_pd_policy.c
@@ -0,0 +1,94 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc.h"
+#include "charge_manager.h"
+#include "chipset.h"
+#include "usb_charge.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+
+int pd_check_vconn_swap(int port)
+{
+	/* Allow Vconn swap if AP is on. */
+	return chipset_in_state(CHIPSET_STATE_SUSPEND | CHIPSET_STATE_ON);
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	__maybe_unused static atomic_t vbus_prev[CONFIG_USB_PD_PORT_MAX_COUNT];
+	int vbus;
+
+	/*
+	 * (b:181203590#comment20) TODO(yllin): use
+	 *  PD_VSINK_DISCONNECT_PD for non-5V case.
+	 */
+	vbus = adc_read_channel(board_get_vbus_adc(port)) >=
+	       PD_V_SINK_DISCONNECT_MAX;
+
+#ifdef CONFIG_USB_CHARGER
+	/*
+	 * There's no PPC to inform VBUS change for usb_charger, so inform
+	 * the usb_charger now.
+	 */
+	if (!!(vbus_prev[port] != vbus)) {
+		usb_charger_vbus_change(port, vbus);
+	}
+
+	if (vbus) {
+		atomic_or(&vbus_prev[port], 1);
+	} else {
+		atomic_clear(&vbus_prev[port]);
+	}
+#endif
+	return vbus;
+}
+
+void pd_power_supply_reset(int port)
+{
+	int prev_en;
+
+	prev_en = ppc_is_sourcing_vbus(port);
+
+	/* Disable VBUS. */
+	ppc_vbus_source_enable(port, 0);
+
+	/* Enable discharge if we were previously sourcing 5V */
+	if (prev_en) {
+		pd_set_vbus_discharge(port, 1);
+	}
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	/* Disable charging. */
+	rv = ppc_vbus_sink_enable(port, 0);
+	if (rv) {
+		return rv;
+	}
+
+	pd_set_vbus_discharge(port, 0);
+
+	/* Provide Vbus. */
+	rv = ppc_vbus_source_enable(port, 1);
+	if (rv) {
+		return rv;
+	}
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+int board_vbus_source_enabled(int port)
+{
+	return ppc_is_sourcing_vbus(port);
+}
diff --git a/zephyr/program/geralt/src/usbc_config.c b/zephyr/program/geralt/src/usbc_config.c
new file mode 100644
index 0000000000..f0c56c5a8b
--- /dev/null
+++ b/zephyr/program/geralt/src/usbc_config.c
@@ -0,0 +1,179 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Geralt baseboard-specific USB-C configuration */
+
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "console.h"
+#include "driver/tcpm/it83xx_pd.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "usb_charge.h"
+#include "usb_pd.h"
+#include "usb_tc_sm.h"
+#include "usbc_ppc.h"
+#include "zephyr_adc.h"
+
+#include <zephyr/drivers/gpio.h>
+
+#include <ap_power/ap_power.h>
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+
+void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
+{
+	/*
+	 * We ignore the cc_pin and PPC vconn because polarity and PPC vconn
+	 * should already be set correctly in the PPC driver via the pd
+	 * state machine.
+	 */
+}
+
+#ifdef CONFIG_USB_PD_TCPM_ITE_ON_CHIP
+const struct cc_para_t *board_get_cc_tuning_parameter(enum usbpd_port port)
+{
+	const static struct cc_para_t
+		cc_parameter[CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT] = {
+			{
+				.rising_time =
+					IT83XX_TX_PRE_DRIVING_TIME_1_UNIT,
+				.falling_time =
+					IT83XX_TX_PRE_DRIVING_TIME_2_UNIT,
+			},
+			{
+				.rising_time =
+					IT83XX_TX_PRE_DRIVING_TIME_1_UNIT,
+				.falling_time =
+					IT83XX_TX_PRE_DRIVING_TIME_2_UNIT,
+			},
+		};
+
+	return &cc_parameter[port];
+}
+#endif
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * C0 & C1: TCPC is embedded in the EC and processes interrupts in the
+	 * chip code (it83xx/intc.c)
+	 */
+}
+
+int board_set_active_charge_port(int port)
+{
+	int i;
+	int is_valid_port = (port >= 0 && port < board_get_usb_pd_port_count());
+	/* adjust the actual port count when not the type-c db connected. */
+
+	if (!is_valid_port && port != CHARGE_PORT_NONE) {
+		return EC_ERROR_INVAL;
+	}
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTS("Disabling all charger ports");
+
+		/* Disable all ports. */
+		for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (ppc_vbus_sink_enable(i, 0)) {
+				CPRINTS("Disabling C%d as sink failed.", i);
+			}
+		}
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (ppc_is_sourcing_vbus(port)) {
+		CPRINTS("Skip enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTS("New charge port: C%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+		if (i == port) {
+			continue;
+		}
+
+		if (ppc_vbus_sink_enable(i, 0)) {
+			CPRINTS("C%d: sink path disable failed.", i);
+		}
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTS("C%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+#ifdef CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT
+enum adc_channel board_get_vbus_adc(int port)
+{
+	if (port == 0) {
+		return ADC_VBUS_C0;
+	}
+	if (port == 1) {
+		return ADC_VBUS_C1;
+	}
+	CPRINTS("Unknown vbus adc port id: %d", port);
+	return ADC_VBUS_C0;
+}
+#endif /* CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT */
+
+/* USB-A */
+void xhci_interrupt(enum gpio_signal signal)
+{
+	const int xhci_stat = gpio_get_level(signal);
+
+#ifdef USB_PORT_ENABLE_COUNT
+	enum usb_charge_mode mode =
+		gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(ap_xhci_init_done)) ?
+			USB_CHARGE_MODE_ENABLED :
+			USB_CHARGE_MODE_DISABLED;
+
+	for (int i = 0; i < USB_PORT_ENABLE_COUNT; i++) {
+		usb_charge_set_mode(i, mode, USB_ALLOW_SUSPEND_CHARGE);
+	}
+#endif
+
+	for (int i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		/*
+		 * Enable DRP toggle after XHCI inited. This is used to follow
+		 * USB 3.2 spec 10.3.1.1.
+		 */
+		if (xhci_stat) {
+			pd_set_dual_role(i, PD_DRP_TOGGLE_ON);
+		} else if (tc_is_attached_src(i)) {
+			/*
+			 * This is a AP reset S0->S0 transition.
+			 * We should set the role back to sink.
+			 */
+			pd_set_dual_role(i, PD_DRP_FORCE_SINK);
+		}
+	}
+}
+
+__override enum pd_dual_role_states pd_get_drp_state_in_s0(void)
+{
+	if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(ap_xhci_init_done))) {
+		return PD_DRP_TOGGLE_ON;
+	} else {
+		return PD_DRP_FORCE_SINK;
+	}
+}
diff --git a/zephyr/program/geralt/usbc.dtsi b/zephyr/program/geralt/usbc.dtsi
new file mode 100644
index 0000000000..da3a3fd65d
--- /dev/null
+++ b/zephyr/program/geralt/usbc.dtsi
@@ -0,0 +1,57 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+			ppc = <&ppc_port0>;
+			tcpc = <&usbpd0>;
+			chg = <&charger>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&tusb546_mux_0 &virtual_mux_0>;
+			};
+		};
+		port0-muxes {
+			virtual_mux_0: virtual-mux-0 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+
+		port1@1 {
+			compatible = "named-usbc-port";
+			reg = <1>;
+			ppc = <&ppc_port1>;
+			tcpc = <&usbpd1>;
+			usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&ps8743_mux_1 &virtual_mux_1>;
+			};
+			usb_mux_chain_1_hdmi_db: usb-mux-chain-1-hdmi-db {
+				compatible = "cros-ec,usb-mux-chain";
+				alternative-chain;
+				usb-muxes = <&virtual_mux_1>;
+			};
+		};
+		port1-muxes {
+			virtual_mux_1: virtual-mux-1 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+	};
+};
+
+&usbpd0 {
+	status = "okay";
+};
+
+&usbpd1 {
+	status = "okay";
+};
diff --git a/zephyr/program/herobrine/BUILD.py b/zephyr/program/herobrine/BUILD.py
new file mode 100644
index 0000000000..302262fc21
--- /dev/null
+++ b/zephyr/program/herobrine/BUILD.py
@@ -0,0 +1,50 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Define zmake projects for herobrine."""
+
+
+def register_variant(
+    project_name,
+):
+    """Register a variant of herobrine."""
+    register_npcx_project(
+        project_name=project_name,
+        zephyr_board="npcx9m3f",
+        dts_overlays=[
+            here / project_name / "project.overlay",
+        ],
+        kconfig_files=[
+            # Common to all projects.
+            here / "program.conf",
+            # Project-specific KConfig customization.
+            here / project_name / "project.conf",
+        ],
+        inherited_from=["herobrine"],
+    )
+
+
+register_variant(
+    project_name="evoker",
+)
+
+register_variant(
+    project_name="herobrine",
+)
+
+register_variant(
+    project_name="hoglin",
+)
+
+register_variant(
+    project_name="villager",
+)
+
+register_variant(
+    project_name="zoglin",
+)
+
+register_variant(
+    project_name="zombie",
+)
diff --git a/zephyr/program/herobrine/CMakeLists.txt b/zephyr/program/herobrine/CMakeLists.txt
new file mode 100644
index 0000000000..53f642d7e6
--- /dev/null
+++ b/zephyr/program/herobrine/CMakeLists.txt
@@ -0,0 +1,42 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+
+cros_ec_library_include_directories(include)
+
+# Common Herobrine implementation
+zephyr_library_sources(
+  "src/board_chipset.c"
+)
+
+# Board specific implementation
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC
+  "src/usbc_config.c"
+  "src/usb_pd_policy.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_I2C
+  "src/i2c.c")
+
+if(DEFINED CONFIG_BOARD_EVOKER)
+	project(evoker)
+	zephyr_library_sources(
+		"evoker/src/charger_override.c"
+	)
+elseif(DEFINED CONFIG_BOARD_HEROBRINE)
+	project(herobrine)
+	add_subdirectory(herobrine)
+elseif(DEFINED CONFIG_BOARD_HOGLIN)
+	project(hoglin)
+elseif(DEFINED CONFIG_BOARD_VILLAGER)
+	zephyr_library_sources(
+		"villager/src/keyboard.c"
+	)
+	project(villager)
+elseif(DEFINED CONFIG_BOARD_ZOGLIN)
+	project(zoglin)
+elseif(DEFINED CONFIG_BOARD_ZOMBIE)
+	project(zombie)
+endif()
diff --git a/zephyr/program/herobrine/Kconfig b/zephyr/program/herobrine/Kconfig
new file mode 100644
index 0000000000..d0056288d5
--- /dev/null
+++ b/zephyr/program/herobrine/Kconfig
@@ -0,0 +1,41 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config BOARD_EVOKER
+	bool "Evoker Board"
+	help
+	  Build the Evoker board. The board is based on the Herobrine
+	  reference design.
+
+config BOARD_HEROBRINE
+	bool "Google Herobrine Baseboard"
+	help
+	  Build Google Herobrine reference board.  The board uses Nuvoton
+	  NPCX9 chip as the EC.
+
+config BOARD_HOGLIN
+	bool "Qualcomm Hoglin Baseboard"
+	help
+	  Build Qualcomm Hoglin reference board.  The board uses Nuvoton
+	  NPCX9 chip as the EC.
+
+config BOARD_VILLAGER
+	bool "Villager Board"
+	help
+	  Build the Villager board. The board is based on the Herobrine
+	  reference design.
+
+config BOARD_ZOGLIN
+	bool "Qualcomm Zoglin Baseboard"
+	help
+	  Build Qualcomm Zoglin reference board.  The board uses Nuvoton
+	  NPCX9 chip as the EC.
+
+config BOARD_ZOMBIE
+	bool "Zombie Board"
+	help
+	  Build the Zombie board. The board is based on the Herobrine
+	  reference design.
+
+source "Kconfig.zephyr"
diff --git a/zephyr/program/herobrine/adc.dtsi b/zephyr/program/herobrine/adc.dtsi
new file mode 100644
index 0000000000..16a5434e9d
--- /dev/null
+++ b/zephyr/program/herobrine/adc.dtsi
@@ -0,0 +1,47 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/dt-bindings/adc/adc.h>
+
+/ {
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		vbus {
+			enum-name = "ADC_VBUS";
+			io-channels = <&adc0 1>;
+			/* Measure VBUS through a 1/10 voltage divider */
+			mul = <10>;
+		};
+		amon_bmon {
+			enum-name = "ADC_AMON_BMON";
+			io-channels = <&adc0 2>;
+			/*
+			 * Adapter current output or battery charging/
+			 * discharging current (uV) 18x amplification on
+			 * charger side.
+			 */
+			mul = <1000>;
+			div = <18>;
+		};
+		psys {
+			enum-name = "ADC_PSYS";
+			io-channels = <&adc0 3>;
+			/*
+			 * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor,
+			 * to read 0.8V @ 99 W, i.e. 124000 uW/mV.
+			 */
+			mul = <124000>;
+		};
+	};
+};
+
+&adc0 {
+	status = "okay";
+	pinctrl-0 = <&adc0_chan1_gp44
+		     &adc0_chan2_gp43
+		     &adc0_chan3_gp42>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/herobrine/common.dtsi b/zephyr/program/herobrine/common.dtsi
new file mode 100644
index 0000000000..0fbde24a54
--- /dev/null
+++ b/zephyr/program/herobrine/common.dtsi
@@ -0,0 +1,44 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/wake_mask_event_defines.h>
+
+/ {
+	chosen {
+		cros,rtc = &pcf85063a;
+	};
+
+	ec-console {
+		compatible = "ec-console";
+		disabled = "hostcmd";
+	};
+
+	ec-mkbp-host-event-wakeup-mask {
+		compatible = "cros-ec,mkbp-host-event-wakeup-mask";
+		wakeup-mask = <(
+			HOST_EVENT_LID_OPEN |
+			HOST_EVENT_POWER_BUTTON |
+			HOST_EVENT_AC_CONNECTED |
+			HOST_EVENT_AC_DISCONNECTED |
+			HOST_EVENT_HANG_DETECT |
+			HOST_EVENT_RTC |
+			HOST_EVENT_MODE_CHANGE |
+			HOST_EVENT_DEVICE)>;
+	};
+
+	ec-mkbp-event-wakeup-mask {
+		compatible = "cros-ec,mkbp-event-wakeup-mask";
+		wakeup-mask = <(MKBP_EVENT_KEY_MATRIX | \
+				MKBP_EVENT_HOST_EVENT | \
+				MKBP_EVENT_SENSOR_FIFO)>;
+	};
+};
+
+&shi0 {
+	status = "okay";
+	pinctrl-0 = <&shi_gp46_47_53_55>;
+	pinctrl-1 = <&shi_gpio_gp46_47_53_55>;
+	pinctrl-names = "default", "sleep";
+};
diff --git a/zephyr/program/herobrine/default_gpio_pinctrl.dtsi b/zephyr/program/herobrine/default_gpio_pinctrl.dtsi
new file mode 100644
index 0000000000..604658a145
--- /dev/null
+++ b/zephyr/program/herobrine/default_gpio_pinctrl.dtsi
@@ -0,0 +1,44 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Adds the &alt1_no_lpc_espi setting over the NPCX9 default setting. */
+&{/def-io-conf-list} {
+	pinmux = <&alt0_gpio_no_spip
+		  &alt0_gpio_no_fpip
+		  &alt1_no_pwrgd
+		  &alt1_no_lpc_espi
+		  &alta_no_peci_en
+		  &altd_npsl_in1_sl
+		  &altd_npsl_in2_sl
+		  &altd_psl_in3_sl
+		  &altd_psl_in4_sl
+		  &alt7_no_ksi0_sl
+		  &alt7_no_ksi1_sl
+		  &alt7_no_ksi2_sl
+		  &alt7_no_ksi3_sl
+		  &alt7_no_ksi4_sl
+		  &alt7_no_ksi5_sl
+		  &alt7_no_ksi6_sl
+		  &alt7_no_ksi7_sl
+		  &alt8_no_kso00_sl
+		  &alt8_no_kso01_sl
+		  &alt8_no_kso02_sl
+		  &alt8_no_kso03_sl
+		  &alt8_no_kso04_sl
+		  &alt8_no_kso05_sl
+		  &alt8_no_kso06_sl
+		  &alt8_no_kso07_sl
+		  &alt9_no_kso08_sl
+		  &alt9_no_kso09_sl
+		  &alt9_no_kso10_sl
+		  &alt9_no_kso11_sl
+		  &alt9_no_kso12_sl
+		  &alt9_no_kso13_sl
+		  &alt9_no_kso14_sl
+		  &alt9_no_kso15_sl
+		  &alta_no_kso16_sl
+		  &alta_no_kso17_sl
+		  &altg_psl_gpo_sl>;
+};
diff --git a/zephyr/program/herobrine/display.dtsi b/zephyr/program/herobrine/display.dtsi
new file mode 100644
index 0000000000..65d3a2d91b
--- /dev/null
+++ b/zephyr/program/herobrine/display.dtsi
@@ -0,0 +1,18 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	displight {
+		compatible = "cros-ec,displight";
+		pwms = <&pwm5 0 PWM_HZ(4800) PWM_POLARITY_NORMAL>;
+		generic-pwm-channel = <1>;
+	};
+};
+
+&pwm5 {
+	status = "okay";
+	pinctrl-0 = <&pwm5_gpb7>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/herobrine/evoker/gpio.dtsi b/zephyr/program/herobrine/evoker/gpio.dtsi
new file mode 100644
index 0000000000..65aa63ffec
--- /dev/null
+++ b/zephyr/program/herobrine/evoker/gpio.dtsi
@@ -0,0 +1,309 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	aliases {
+		gpio-wp = &gpio_ec_wp_odl;
+		gpio-kbd-kso2 = &gpio_ec_kso_02_inv;
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		gpio_usb_c0_pd_int_odl: usb_c0_pd_int_odl {
+			gpios = <&gpioe 0 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_USB_C0_PD_INT_ODL";
+		};
+		gpio_usb_c1_pd_int_odl: usb_c1_pd_int_odl {
+			gpios = <&gpiof 5 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_USB_C1_PD_INT_ODL";
+		};
+		gpio_usb_c0_swctl_int_odl: usb_c0_swctl_int_odl {
+			gpios = <&gpio0 3 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C0_SWCTL_INT_ODL";
+		};
+		gpio_usb_c1_swctl_int_odl: usb_c1_swctl_int_odl {
+			gpios = <&gpio4 0 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C1_SWCTL_INT_ODL";
+		};
+		gpio_usb_c0_bc12_int_l: usb_c0_bc12_int_l {
+			gpios = <&gpio6 1 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_usb_c1_bc12_int_l: usb_c1_bc12_int_l {
+			gpios = <&gpio8 2 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_chg_acok_od: chg_acok_od {
+			gpios = <&gpiod 2 GPIO_INPUT>;
+			enum-name = "GPIO_AC_PRESENT";
+		};
+		gpio_ec_pwr_btn_odl: ec_pwr_btn_odl {
+			gpios = <&gpio0 0 GPIO_INPUT>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		gpio_ec_voldn_btn_odl: ec_voldn_btn_odl {
+			gpios = <&gpio6 2 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_DOWN_L";
+		};
+		gpio_ec_volup_btn_odl: ec_volup_btn_odl {
+			gpios = <&gpioc 2 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_UP_L";
+		};
+		gpio_ec_wp_odl: ec_wp_odl {
+			gpios = <&gpiod 3 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_lid_open_ec: lid_open_ec {
+			gpios = <&gpio0 1 GPIO_INPUT>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+		gpio_ap_rst_l: ap_rst_l {
+			gpios = <&gpio5 1 GPIO_INPUT>;
+			enum-name = "GPIO_AP_RST_L";
+		};
+		gpio_ps_hold: ps_hold {
+			gpios = <&gpioa 6 GPIO_INPUT_PULL_DOWN>;
+			enum-name = "GPIO_PS_HOLD";
+		};
+		gpio_ap_suspend: ap_suspend {
+			gpios = <&gpio5 7 GPIO_INPUT>;
+			enum-name = "GPIO_AP_SUSPEND";
+		};
+		gpio_mb_power_good: mb_power_good {
+			gpios = <&gpio3 7 GPIO_INPUT_PULL_DOWN>;
+			enum-name = "GPIO_POWER_GOOD";
+		};
+		gpio_warm_reset_l: warm_reset_l {
+			gpios = <&gpiob 0 GPIO_INPUT>;
+			enum-name = "GPIO_WARM_RESET_L";
+		};
+		ap_ec_spi_cs_l {
+			gpios = <&gpio5 3 GPIO_INPUT_PULL_DOWN>;
+		};
+		gpio_tablet_mode_l: tablet_mode_l {
+			gpios = <&gpioc 6 GPIO_INPUT>;
+			enum-name = "GPIO_TABLET_MODE_L";
+		};
+		gpio_accel_gyro_int_l: accel_gyro_int_l {
+			gpios = <&gpioa 3 GPIO_INPUT>;
+		};
+		gpio_rtc_ec_wake_odl: rtc_ec_wake_odl {
+			gpios = <&gpio0 2 GPIO_INPUT>;
+		};
+		ec_entering_rw {
+			gpios = <&gpio7 2 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_ENTERING_RW";
+		};
+		ccd_mode_odl {
+			gpios = <&gpio6 3 GPIO_INPUT>;
+			enum-name = "GPIO_CCD_MODE_ODL";
+		};
+		ec_batt_pres_odl {
+			gpios = <&gpioe 5 GPIO_INPUT>;
+			enum-name = "GPIO_BATT_PRES_ODL";
+		};
+		ec_gsc_packet_mode {
+			gpios = <&gpio8 3 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_PACKET_MODE_EN";
+		};
+		pmic_resin_l {
+			gpios = <&gpioa 0 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_PMIC_RESIN_L";
+		};
+		pmic_kpd_pwr_odl {
+			gpios = <&gpioa 2 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_PMIC_KPD_PWR_ODL";
+		};
+		ap_ec_int_l {
+			gpios = <&gpio5 6 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_EC_INT_L";
+		};
+		gpio_switchcap_on: switchcap_on {
+			gpios = <&gpiod 5 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_SWITCHCAP_ON";
+		};
+		gpio_en_pp5000_s5: en_pp5000_s5 {
+			gpios = <&gpio7 3 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_EN_PP5000";
+		};
+		ec_bl_disable_l {
+			/* The PMIC controls backlight enable and this pin must
+			 * be HiZ for normal operation. The EC is allowed to
+			 * drive low to abruptly removes power from the eDP
+			 * panel in cases like lid close. So the signal is open
+			 * drain (allowed to drive low, never drive high).
+			 */
+			gpios = <&gpiob 6 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_ENABLE_BACKLIGHT";
+		};
+		lid_accel_int_l {
+			gpios = <&gpioa 1 GPIO_INPUT>;
+		};
+		tp_int_gate {
+			gpios = <&gpio7 4 GPIO_OUTPUT_LOW>;
+		};
+		gpio_usb_c0_pd_rst_l: usb_c0_pd_rst_l {
+			gpios = <&gpiof 1 (GPIO_OUTPUT_HIGH | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_usb_c1_pd_rst_l: usb_c1_pd_rst_l {
+			gpios = <&gpioe 4 (GPIO_OUTPUT_HIGH | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_dp_mux_oe_l: dp_mux_oe_l {
+			gpios = <&gpiob 1 GPIO_ODR_HIGH>;
+		};
+		gpio_dp_mux_sel: dp_mux_sel {
+			gpios = <&gpio4 5 GPIO_OUTPUT_LOW>;
+		};
+		gpio_dp_hot_plug_det_r: dp_hot_plug_det_r {
+			gpios = <&gpio9 5 GPIO_OUTPUT_LOW>;
+		};
+		gpio_usb_c0_frs_en: usb_c0_frs_en {
+			gpios = <&gpioc 5 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_USB_C0_FRS_EN";
+		};
+		gpio_usb_c1_frs_en: usb_c1_frs_en {
+			gpios = <&gpioc 1 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_USB_C1_FRS_EN";
+		};
+		gpio_ec_chg_led_y_c0: ec_chg_led_y_c0 {
+			gpios = <&gpio6 0 GPIO_OUTPUT_LOW>;
+		};
+		gpio_ec_chg_led_w_c0: ec_chg_led_w_c0 {
+			gpios = <&gpioc 0 GPIO_OUTPUT_LOW>;
+		};
+		gpio_ec_chg_led_w_c1: ec_chg_led_w_c1 {
+			gpios = <&gpioc 3 GPIO_OUTPUT_LOW>;
+		};
+		gpio_ec_chg_led_r_c0: ec_chg_led_r_c0 {
+			gpios = <&gpioc 4 GPIO_OUTPUT_LOW>;
+		};
+		ap_ec_spi_mosi {
+			gpios = <&gpio4 6 GPIO_INPUT_PULL_DOWN>;
+		};
+		ap_ec_spi_miso {
+			gpios = <&gpio4 7 GPIO_INPUT_PULL_DOWN>;
+		};
+		ap_ec_spi_clk {
+			gpios = <&gpio5 5 GPIO_INPUT_PULL_DOWN>;
+		};
+		gpio_brd_id0: brd_id0 {
+			gpios = <&gpio9 4 GPIO_INPUT>;
+			enum-name = "GPIO_BOARD_VERSION1";
+		};
+		gpio_brd_id1: brd_id1 {
+			gpios = <&gpio9 7 GPIO_INPUT>;
+			enum-name = "GPIO_BOARD_VERSION2";
+		};
+		gpio_brd_id2: brd_id2 {
+			gpios = <&gpioa 5 GPIO_INPUT>;
+			enum-name = "GPIO_BOARD_VERSION3";
+		};
+		gpio_sku_id0: sku_id0 {
+			gpios = <&gpio6 7 GPIO_INPUT>;
+		};
+		gpio_sku_id1: sku_id1 {
+			gpios = <&gpio7 0 GPIO_INPUT>;
+		};
+		gpio_sku_id2: sku_id2 {
+			gpios = <&gpioe 1 GPIO_INPUT>;
+		};
+		gpio_switchcap_pg: src_vph_pwr_pg {
+			gpios = <&gpioe 2 GPIO_INPUT_PULL_DOWN>;
+			enum-name = "GPIO_SWITCHCAP_PG";
+		};
+		arm_x86 {
+			gpios = <&gpio6 6 GPIO_OUTPUT_LOW>;
+		};
+		ec-i2c-sensor-scl {
+			gpios = <&gpiob 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		ec-i2c-sensor-sda {
+			gpios = <&gpiob 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		gpio_ec_kso_02_inv: ec_kso_02_inv {
+			gpios = <&gpio1 7 (GPIO_OUTPUT_LOW | GPIO_ACTIVE_LOW)>;
+		};
+	};
+
+	gpio_id_sku: sku {
+		compatible = "cros-ec,gpio-id";
+		bits  = <
+			&gpio_sku_id0
+			&gpio_sku_id1
+			&gpio_sku_id2
+		>;
+		system = "ternary";
+	};
+
+	gpio_id_board: board {
+		compatible = "cros-ec,gpio-id";
+		bits  = <
+			&gpio_brd_id0
+			&gpio_brd_id1
+			&gpio_brd_id2
+		>;
+		system = "ternary";
+	};
+
+	unused-pins {
+		compatible = "unused-gpios";
+		unused-gpios =
+			<&gpio5 2 0>,
+			<&gpio5 4 0>,
+			<&gpio7 6 0>,
+			<&gpiod 1 0>,
+			<&gpiod 0 0>,
+			<&gpioe 3 0>,
+			<&gpio0 4 0>,
+			<&gpiod 6 0>,
+			<&gpio3 2 0>,
+			<&gpio3 5 0>,
+			<&gpiod 7 0>,
+			<&gpio8 6 0>,
+			<&gpiod 4 0>,
+			<&gpio3 4 0>,
+			<&gpioc 7 0>,
+			<&gpioa 4 0>,
+			<&gpio9 6 0>,
+			<&gpio9 3 0>,
+			<&gpioa 7 0>,
+			<&gpio5 0 0>,
+			<&gpio8 1 0>,
+			<&gpiof 0 0>,
+			<&gpio7 5 0>,
+			<&gpiof 4 0>,
+			<&gpiob 7 0>;
+	};
+};
+
+/* Power switch logic input pads */
+&psl_in1_gpd2 {
+	/* ACOK_OD */
+	psl-in-mode = "edge";
+	psl-in-pol = "high-rising";
+};
+
+&psl_in2_gp00 {
+	/* EC_PWR_BTN_ODL */
+	psl-in-mode = "edge";
+	psl-in-pol = "low-falling";
+};
+
+&psl_in3_gp01 {
+	/* LID_OPEN_EC */
+	psl-in-mode = "edge";
+	psl-in-pol = "high-rising";
+};
+
+&psl_in4_gp02 {
+	/* RTC_EC_WAKE_ODL */
+	psl-in-mode = "edge";
+	psl-in-pol = "low-falling";
+};
+
+/* Power domain device controlled by PSL (Power Switch Logic) IO pads */
+&power_ctrl_psl {
+	status = "okay";
+	pinctrl-names = "sleep";
+	pinctrl-0 = <&psl_in1_gpd2 &psl_in2_gp00 &psl_in3_gp01 &psl_in4_gp02>;
+};
diff --git a/zephyr/program/herobrine/evoker/led_pins.dtsi b/zephyr/program/herobrine/evoker/led_pins.dtsi
new file mode 100644
index 0000000000..3b739c4ce3
--- /dev/null
+++ b/zephyr/program/herobrine/evoker/led_pins.dtsi
@@ -0,0 +1,56 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	gpio-led-pins {
+		compatible = "cros-ec,gpio-led-pins";
+
+		power_led: power-led {
+			led-id = "EC_LED_ID_POWER_LED";
+			led-pins = <&gpio_ec_chg_led_w_c1>;
+
+			color_power_off: color-power-off {
+				led-color = "LED_OFF";
+				led-values = <0>;
+			};
+
+			color_power_white: color-power-white {
+				led-color = "LED_WHITE";
+				br-color = "EC_LED_COLOR_WHITE";
+				led-values = <1>;
+			};
+		};
+
+		battery_led: battery-led {
+			led-id = "EC_LED_ID_BATTERY_LED";
+			led-pins = <&gpio_ec_chg_led_y_c0
+				    &gpio_ec_chg_led_w_c0
+				    &gpio_ec_chg_led_r_c0>;
+
+			color_battery_off: color-battery-off {
+				led-color = "LED_OFF";
+				led-values = <0 0 0>;
+			};
+
+			color_battery_amber: color-battery-amber {
+				led-color = "LED_AMBER";
+				br-color = "EC_LED_COLOR_AMBER";
+				led-values = <1 0 0>;
+			};
+
+			color_battery_white: color-battery-white {
+				led-color = "LED_WHITE";
+				br-color = "EC_LED_COLOR_WHITE";
+				led-values = <0 1 0>;
+			};
+
+			color_battery_red: color-battery-red {
+				led-color = "LED_RED";
+				br-color = "EC_LED_COLOR_RED";
+				led-values = <0 0 1>;
+			};
+		};
+	};
+};
diff --git a/zephyr/program/herobrine/evoker/led_policy.dtsi b/zephyr/program/herobrine/evoker/led_policy.dtsi
new file mode 100644
index 0000000000..ecd4affaaf
--- /dev/null
+++ b/zephyr/program/herobrine/evoker/led_policy.dtsi
@@ -0,0 +1,86 @@
+#include <dt-bindings/battery.h>
+
+/ {
+	led-colors {
+		compatible = "cros-ec,led-policy";
+
+		battery-state-charge {
+			charge-state = "LED_PWRS_CHARGE";
+
+			color-0 {
+				led-color = <&color_battery_amber>;
+			};
+		};
+
+		battery-state-near-full {
+			charge-state = "LED_PWRS_CHARGE_NEAR_FULL";
+
+			color-0 {
+				led-color = <&color_battery_white>;
+			};
+		};
+
+		battery-state-discharge {
+			charge-state = "LED_PWRS_DISCHARGE";
+
+			color-0 {
+				led-color = <&color_battery_off>;
+			};
+		};
+
+		battery-state-error {
+			charge-state = "LED_PWRS_ERROR";
+
+			color-0 {
+				led-color = <&color_battery_red>;
+			};
+		};
+
+		/* force idle mode */
+		battery-state-forced-idle {
+			charge-state = "LED_PWRS_FORCED_IDLE";
+
+			/* Red 1 sec, White 1 sec */
+			color-0 {
+				led-color = <&color_battery_red>;
+				period-ms = <1000>;
+			};
+
+			color-1 {
+				led-color = <&color_battery_white>;
+				period-ms = <1000>;
+			};
+		};
+
+		pwr-power-state-s0 {
+			chipset-state = "POWER_S0";
+
+			color-0 {
+				led-color = <&color_power_white>;
+			};
+		};
+
+		power-state-s3 {
+			chipset-state = "POWER_S3";
+
+			/* white LED - on 1 sec, off 1 sec */
+			color-0 {
+				led-color = <&color_power_white>;
+				period-ms = <1000>;
+			};
+
+			color-1 {
+				led-color = <&color_power_off>;
+				period-ms = <1000>;
+			};
+		};
+
+		power-state-s5 {
+			chipset-state = "POWER_S5";
+
+			color-0 {
+				led-color = <&color_power_off>;
+			};
+		};
+	};
+};
diff --git a/zephyr/program/herobrine/evoker/motionsense.dtsi b/zephyr/program/herobrine/evoker/motionsense.dtsi
new file mode 100644
index 0000000000..aa7646e0b3
--- /dev/null
+++ b/zephyr/program/herobrine/evoker/motionsense.dtsi
@@ -0,0 +1,148 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/motionsense/utils.h>
+
+
+/ {
+	aliases {
+		/*
+		 * motion sense's <>_INT_EVENT is handled
+		 * by alias. Using the alias, each driver creates
+		 * its own <>_INT_EVENT.
+		 */
+		bmi260-int = &base_accel;
+	};
+
+	/*
+	 * Declare mutexes used by sensor drivers.
+	 * A mutex node is used to create an instance of mutex_t.
+	 * A mutex node is referenced by a sensor node if the
+	 * corresponding sensor driver needs to use the
+	 * instance of the mutex.
+	 */
+	motionsense-mutex {
+		compatible = "cros-ec,motionsense-mutex";
+		lid_mutex: lid-mutex {
+		};
+
+		mutex_bmi260: bmi260-mutex {
+		};
+	};
+
+	/* Rotation matrix used by drivers. */
+	motionsense-rotation-ref {
+		compatible = "cros-ec,motionsense-rotation-ref";
+		lid_rot_ref: lid-rotation-ref {
+			mat33 = <(-1) 0 0
+				 0 (-1) 0
+				 0 0 1>;
+		};
+
+		base_rot_ref: base-rotation-ref {
+			mat33 = <0 1 0
+				 (-1) 0 0
+				 0 0 1>;
+		};
+	};
+
+	/*
+	 * Driver specific data. A driver-specific data can be shared with
+	 * different motion sensors while they are using the same driver.
+	 *
+	 * If a node's compatible starts with "cros-ec,accelgyro-", it is for
+	 * a common structure defined in accelgyro.h.
+	 * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for
+	 * "struct als_drv_data_t" in accelgyro.h
+	 */
+	motionsense-sensor-data {
+		bma4xx_data: bma4xx-drv-data {
+			compatible = "cros-ec,drvdata-bma4xx";
+			status = "okay";
+		};
+
+		bmi260_data: bmi260-drv-data {
+			compatible = "cros-ec,drvdata-bmi260";
+			status = "okay";
+		};
+	};
+
+	/*
+	 * List of motion sensors that creates motion_sensors array.
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
+	 * motion sensor IDs for lid angle calculation.
+	 */
+	motionsense-sensor {
+		lid_accel: lid-accel {
+			compatible = "cros-ec,bma4xx";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&lid_mutex>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&lid_rot_ref>;
+			default-range = <2>;
+			drv-data = <&bma4xx_data>;
+			i2c-spi-addr-flags = "BMA4_I2C_ADDR_PRIMARY";
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_accel: base-accel {
+			compatible = "cros-ec,bmi260-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&mutex_bmi260>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&bmi260_data>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base-gyro {
+			compatible = "cros-ec,bmi260-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&mutex_bmi260>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&bmi260_data>;
+		};
+	};
+
+	motionsense-sensor-info {
+		compatible = "cros-ec,motionsense-sensor-info";
+
+		/*
+		 * list of GPIO interrupts that have to
+		 * be enabled at initial stage
+		 */
+		sensor-irqs = <&int_accel_gyro>;
+		/* list of sensors in force mode */
+		accel-force-mode-sensors = <&lid_accel>;
+	};
+};
diff --git a/zephyr/program/herobrine/evoker/project.conf b/zephyr/program/herobrine/evoker/project.conf
new file mode 100644
index 0000000000..0e70563c73
--- /dev/null
+++ b/zephyr/program/herobrine/evoker/project.conf
@@ -0,0 +1,25 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Evoker board-specific Kconfig settings.
+CONFIG_BOARD_EVOKER=y
+
+# Disable type-c port sourcing 3A
+CONFIG_PLATFORM_EC_CONFIG_USB_PD_3A_PORTS=0
+
+CONFIG_PLATFORM_EC_ACCEL_BMA255=n
+CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y
+
+# ISL9238C disable the CMOUT latch function.
+CONFIG_PLATFORM_EC_ISL9238C_DISABLE_CMOUT_LATCH=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_DUMP=y
+
+# Disable USB-A
+CONFIG_PLATFORM_EC_USBA=n
+
+# Set PCF85063A CAP_SEL
+CONFIG_PLATFORM_EC_PCF85063A_CAP_SEL=y
+
+# Temperature sensor support
+CONFIG_PLATFORM_EC_TEMP_SENSOR_FIRST_READ_DELAY=y
diff --git a/zephyr/program/herobrine/evoker/project.overlay b/zephyr/program/herobrine/evoker/project.overlay
new file mode 100644
index 0000000000..a4331b5dab
--- /dev/null
+++ b/zephyr/program/herobrine/evoker/project.overlay
@@ -0,0 +1,98 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Herobrine program common DTS includes */
+#include "../adc.dtsi"
+#include "../common.dtsi"
+#include "../i2c.dtsi"
+#include "../interrupts.dtsi"
+#include "../keyboard.dtsi"
+#include "../default_gpio_pinctrl.dtsi"
+#include "../display.dtsi"
+#include "../switchcap.dtsi"
+#include "../usbc.dtsi"
+
+/* Evoker project DTS includes*/
+#include "gpio.dtsi"
+#include "led_pins.dtsi"
+#include "led_policy.dtsi"
+#include "motionsense.dtsi"
+#include <cros/thermistor/thermistor.dtsi>
+
+/* evoker overrides follow... */
+/* battery overrides */
+/ {
+	batteries {
+		default_battery: pc_vp_bp153 {
+			compatible = "smp,pc-vp-bp153", "battery-smart";
+		};
+		ap16l5j {
+			compatible = "panasonic,ap16l5j", "battery-smart";
+		};
+	};
+
+};
+
+/* i2c overrides */
+&i2c1_0 {
+	ppc_port0_alt: sn5s330@40 {
+		compatible = "ti,sn5s330";
+		status = "okay";
+		reg = <0x40>;
+	};
+};
+
+&i2c2_0 {
+	ppc_port1_alt: sn5s330@40 {
+		compatible = "ti,sn5s330";
+		status = "okay";
+		reg = <0x40>;
+	};
+};
+
+/* interrupts overrides */
+/ {
+	gpio-interrupts {
+		/delete-node/ usb_a0_oc;
+	};
+};
+
+/* adc0 overrides */
+&adc0 {
+	status = "okay";
+	pinctrl-0 = <&adc0_chan1_gp44
+		     &adc0_chan2_gp43
+		     &adc0_chan3_gp42
+		     &adc0_chan4_gp41>;
+	pinctrl-names = "default";
+};
+
+/* temp sensors */
+/ {
+	named-adc-channels {
+		adc_temp_sensor_1: temp_sensor_1 {
+			enum-name = "ADC_TEMP_SENSOR_1";
+			io-channels = <&adc0 4>;
+		};
+	};
+
+	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
+		charger {
+			power-good-pin = <&gpio_en_pp5000_s5>;
+			sensor = <&temp_charger>;
+		};
+	};
+
+	temp_charger: charger {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_1>;
+	};
+};
+
+&thermistor_3V3_51K1_47K_4050B {
+	status = "okay";
+};
diff --git a/zephyr/program/herobrine/evoker/src/charger_override.c b/zephyr/program/herobrine/evoker/src/charger_override.c
new file mode 100644
index 0000000000..daefa240a9
--- /dev/null
+++ b/zephyr/program/herobrine/evoker/src/charger_override.c
@@ -0,0 +1,105 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "console.h"
+#include "extpower.h"
+#include "temp_sensor/temp_sensor.h"
+#include "util.h"
+
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(smart_battery);
+
+/*
+ * Dynamic changing charge current.
+ */
+
+struct temp_chg_step {
+	int low; /* temp thershold ('C) to lower level*/
+	int high; /* temp thershold ('C) to higher level */
+	int current; /* charging limitation (mA) */
+};
+
+static const struct temp_chg_step temp_chg_table[] = {
+	{ .low = 0, .high = 56, .current = __INT32_MAX__ },
+	{ .low = 50, .high = 100, .current = 2000 },
+};
+#define NUM_TEMP_CHG_LEVELS ARRAY_SIZE(temp_chg_table)
+
+#undef BOARD_TEMP_TEST
+
+#ifdef BOARD_TEMP_TEST
+static int manual_temp = -1;
+#endif
+
+__override int board_charger_profile_override(struct charge_state_data *curr)
+{
+	static int current_level;
+	int charger_temp, charger_temp_c;
+
+	if (curr->state != ST_CHARGE)
+		return 0;
+
+	temp_sensor_read(TEMP_SENSOR_ID_BY_DEV(DT_NODELABEL(temp_charger)),
+			 &charger_temp);
+
+	charger_temp_c = K_TO_C(charger_temp);
+
+#ifdef BOARD_TEMP_TEST
+	if (manual_temp != -1)
+		charger_temp_c = manual_temp;
+	LOG_WRN("chg_temp_c: %d", charger_temp_c);
+#endif
+
+	if (charger_temp_c <= temp_chg_table[current_level].low)
+		current_level--;
+	else if (charger_temp_c >= temp_chg_table[current_level].high)
+		current_level++;
+
+	if (current_level < 0)
+		current_level = 0;
+
+	if (current_level >= NUM_TEMP_CHG_LEVELS)
+		current_level = NUM_TEMP_CHG_LEVELS - 1;
+
+	curr->requested_current = MIN(curr->requested_current,
+				      temp_chg_table[current_level].current);
+
+#ifdef BOARD_TEMP_TEST
+	LOG_WRN("level: %d, batt_current: %d, limit_current: %d", current_level,
+		curr->requested_current, temp_chg_table[current_level].current);
+#endif
+
+	return EC_SUCCESS;
+}
+
+#ifdef BOARD_TEMP_TEST
+static int command_temp_test(int argc, const char **argv)
+{
+	char *e;
+	int t;
+
+	if (argc > 1) {
+		t = strtoi(argv[1], &e, 0);
+		if (*e) {
+			LOG_WRN("Invalid test temp");
+			return EC_ERROR_INVAL;
+		}
+		manual_temp = t;
+		LOG_WRN("manual temp is %d", manual_temp);
+		return EC_SUCCESS;
+	}
+
+	manual_temp = -1;
+	LOG_WRN("manual temp reset");
+
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(tt, command_temp_test, "[temperature]",
+			"set manual temperature for test");
+#endif
diff --git a/zephyr/program/herobrine/gpio.dtsi b/zephyr/program/herobrine/gpio.dtsi
new file mode 100644
index 0000000000..b4befe82ce
--- /dev/null
+++ b/zephyr/program/herobrine/gpio.dtsi
@@ -0,0 +1,322 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	aliases {
+		gpio-wp = &gpio_ec_wp_odl;
+		gpio-kbd-kso2 = &gpio_ec_kso_02_inv;
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		gpio_usb_c0_pd_int_odl: usb_c0_pd_int_odl {
+			gpios = <&gpioe 0 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_USB_C0_PD_INT_ODL";
+		};
+		gpio_usb_c1_pd_int_odl: usb_c1_pd_int_odl {
+			gpios = <&gpiof 5 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_USB_C1_PD_INT_ODL";
+		};
+		gpio_usb_c0_swctl_int_odl: usb_c0_swctl_int_odl {
+			gpios = <&gpio0 3 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C0_SWCTL_INT_ODL";
+		};
+		gpio_usb_c1_swctl_int_odl: usb_c1_swctl_int_odl {
+			gpios = <&gpio4 0 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C1_SWCTL_INT_ODL";
+		};
+		gpio_usb_c0_bc12_int_l: usb_c0_bc12_int_l {
+			gpios = <&gpio6 1 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_usb_c1_bc12_int_l: usb_c1_bc12_int_l {
+			gpios = <&gpio8 2 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_usb_a0_oc_odl: usb_a0_oc_odl {
+			gpios = <&gpiof 4 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_chg_acok_od: chg_acok_od {
+			gpios = <&gpiod 2 GPIO_INPUT>;
+			enum-name = "GPIO_AC_PRESENT";
+		};
+		gpio_ec_pwr_btn_odl: ec_pwr_btn_odl {
+			gpios = <&gpio0 0 GPIO_INPUT>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		gpio_ec_voldn_btn_odl: ec_voldn_btn_odl {
+			gpios = <&gpio6 2 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_DOWN_L";
+		};
+		gpio_ec_volup_btn_odl: ec_volup_btn_odl {
+			gpios = <&gpioc 2 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_UP_L";
+		};
+		gpio_ec_wp_odl: ec_wp_odl {
+			gpios = <&gpiod 3 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_lid_open_ec: lid_open_ec {
+			gpios = <&gpio0 1 GPIO_INPUT>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+		gpio_ap_rst_l: ap_rst_l {
+			gpios = <&gpio5 1 GPIO_INPUT>;
+			enum-name = "GPIO_AP_RST_L";
+		};
+		gpio_ps_hold: ps_hold {
+			gpios = <&gpioa 6 GPIO_INPUT_PULL_DOWN>;
+			enum-name = "GPIO_PS_HOLD";
+		};
+		gpio_ap_suspend: ap_suspend {
+			gpios = <&gpio5 7 GPIO_INPUT>;
+			enum-name = "GPIO_AP_SUSPEND";
+		};
+		gpio_mb_power_good: mb_power_good {
+			gpios = <&gpio3 7 GPIO_INPUT_PULL_DOWN>;
+			enum-name = "GPIO_POWER_GOOD";
+		};
+		gpio_warm_reset_l: warm_reset_l {
+			gpios = <&gpiob 0 GPIO_INPUT>;
+			enum-name = "GPIO_WARM_RESET_L";
+		};
+		ap_ec_spi_cs_l {
+			gpios = <&gpio5 3 GPIO_INPUT_PULL_DOWN>;
+		};
+		gpio_tablet_mode_l: tablet_mode_l {
+			gpios = <&gpioc 6 GPIO_INPUT>;
+			enum-name = "GPIO_TABLET_MODE_L";
+		};
+		gpio_accel_gyro_int_l: accel_gyro_int_l {
+			gpios = <&gpioa 3 GPIO_INPUT>;
+		};
+		gpio_rtc_ec_wake_odl: rtc_ec_wake_odl {
+			gpios = <&gpio0 2 GPIO_INPUT>;
+		};
+		ec_entering_rw {
+			gpios = <&gpio7 2 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_ENTERING_RW";
+		};
+		ccd_mode_odl {
+			gpios = <&gpio6 3 GPIO_INPUT>;
+			enum-name = "GPIO_CCD_MODE_ODL";
+		};
+		ec_batt_pres_odl {
+			gpios = <&gpioe 5 GPIO_INPUT>;
+			enum-name = "GPIO_BATT_PRES_ODL";
+		};
+		ec_gsc_packet_mode {
+			gpios = <&gpio8 3 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_PACKET_MODE_EN";
+		};
+		pmic_resin_l {
+			gpios = <&gpioa 0 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_PMIC_RESIN_L";
+		};
+		pmic_kpd_pwr_odl {
+			gpios = <&gpioa 2 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_PMIC_KPD_PWR_ODL";
+		};
+		ap_ec_int_l {
+			gpios = <&gpio5 6 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_EC_INT_L";
+		};
+		gpio_switchcap_on: switchcap_on {
+			gpios = <&gpiod 5 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_SWITCHCAP_ON";
+		};
+		gpio_en_pp5000_s5: en_pp5000_s5 {
+			gpios = <&gpio7 3 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_EN_PP5000";
+		};
+		ec_bl_disable_l {
+			/* The PMIC controls backlight enable and this pin must
+			 * be HiZ for normal operation. The EC is allowed to
+			 * drive low to abruptly removes power from the eDP
+			 * panel in cases like lid close. So the signal is open
+			 * drain (allowed to drive low, never drive high).
+			 */
+			gpios = <&gpiob 6 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_ENABLE_BACKLIGHT";
+		};
+		lid_accel_int_l {
+			gpios = <&gpioa 1 GPIO_INPUT>;
+		};
+		tp_int_gate {
+			gpios = <&gpio7 4 GPIO_OUTPUT_LOW>;
+		};
+		gpio_usb_c0_pd_rst_l: usb_c0_pd_rst_l {
+			gpios = <&gpiof 1 (GPIO_OUTPUT_HIGH | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_usb_c1_pd_rst_l: usb_c1_pd_rst_l {
+			gpios = <&gpioe 4 (GPIO_OUTPUT_HIGH | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_dp_mux_oe_l: dp_mux_oe_l {
+			gpios = <&gpiob 1 GPIO_ODR_HIGH>;
+		};
+		gpio_dp_mux_sel: dp_mux_sel {
+			gpios = <&gpio4 5 GPIO_OUTPUT_LOW>;
+		};
+		gpio_dp_hot_plug_det_r: dp_hot_plug_det_r {
+			gpios = <&gpio9 5 GPIO_OUTPUT_LOW>;
+		};
+		gpio_en_usb_a_5v: en_usb_a_5v {
+			gpios = <&gpiof 0 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_EN_USB_A_5V";
+		};
+		usb_a_cdp_ilim_en_l {
+			gpios = <&gpio7 5 GPIO_OUTPUT_HIGH>;
+		};
+		gpio_usb_c0_frs_en: usb_c0_frs_en {
+			gpios = <&gpioc 5 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_USB_C0_FRS_EN";
+		};
+		gpio_usb_c1_frs_en: usb_c1_frs_en {
+			gpios = <&gpioc 1 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_USB_C1_FRS_EN";
+		};
+		gpio_ec_chg_led_y_c0: ec_chg_led_y_c0 {
+			gpios = <&gpio6 0 GPIO_OUTPUT_LOW>;
+		};
+		gpio_ec_chg_led_w_c0: ec_chg_led_w_c0 {
+			gpios = <&gpioc 0 GPIO_OUTPUT_LOW>;
+		};
+		gpio_ec_chg_led_y_c1: ec_chg_led_y_c1 {
+			gpios = <&gpioc 3 GPIO_OUTPUT_LOW>;
+		};
+		gpio_ec_chg_led_w_c1: ec_chg_led_w_c1 {
+			gpios = <&gpioc 4 GPIO_OUTPUT_LOW>;
+		};
+		ap_ec_spi_mosi {
+			gpios = <&gpio4 6 GPIO_INPUT_PULL_DOWN>;
+		};
+		ap_ec_spi_miso {
+			gpios = <&gpio4 7 GPIO_INPUT_PULL_DOWN>;
+		};
+		ap_ec_spi_clk {
+			gpios = <&gpio5 5 GPIO_INPUT_PULL_DOWN>;
+		};
+		gpio_brd_id0: brd_id0 {
+			gpios = <&gpio9 4 GPIO_INPUT>;
+			enum-name = "GPIO_BOARD_VERSION1";
+		};
+		gpio_brd_id1: brd_id1 {
+			gpios = <&gpio9 7 GPIO_INPUT>;
+			enum-name = "GPIO_BOARD_VERSION2";
+		};
+		gpio_brd_id2: brd_id2 {
+			gpios = <&gpioa 5 GPIO_INPUT>;
+			enum-name = "GPIO_BOARD_VERSION3";
+		};
+		gpio_sku_id0: sku_id0 {
+			gpios = <&gpio6 7 GPIO_INPUT>;
+		};
+		gpio_sku_id1: sku_id1 {
+			gpios = <&gpio7 0 GPIO_INPUT>;
+		};
+		gpio_sku_id2: sku_id2 {
+			gpios = <&gpioe 1 GPIO_INPUT>;
+		};
+		gpio_switchcap_pg: src_vph_pwr_pg {
+			gpios = <&gpioe 2 GPIO_INPUT_PULL_DOWN>;
+			enum-name = "GPIO_SWITCHCAP_PG";
+		};
+		arm_x86 {
+			gpios = <&gpio6 6 GPIO_OUTPUT_LOW>;
+		};
+		ec-i2c-sensor-scl {
+			gpios = <&gpiob 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		ec-i2c-sensor-sda {
+			gpios = <&gpiob 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		gpio_ec_kso_02_inv: ec_kso_02_inv {
+			gpios = <&gpio1 7 (GPIO_OUTPUT_LOW | GPIO_ACTIVE_LOW)>;
+		};
+	};
+
+	usba-port-enable-list {
+		compatible = "cros-ec,usba-port-enable-pins";
+		enable-pins = <&gpio_en_usb_a_5v>;
+	};
+
+	gpio_id_sku: sku {
+		compatible = "cros-ec,gpio-id";
+		bits  = <
+			&gpio_sku_id0
+			&gpio_sku_id1
+			&gpio_sku_id2
+		>;
+		system = "ternary";
+	};
+
+	gpio_id_board: board {
+		compatible = "cros-ec,gpio-id";
+		bits  = <
+			&gpio_brd_id0
+			&gpio_brd_id1
+			&gpio_brd_id2
+		>;
+		system = "ternary";
+	};
+
+	unused-pins {
+		compatible = "unused-gpios";
+		unused-gpios =
+			<&gpio5 2 0>,
+			<&gpio5 4 0>,
+			<&gpio7 6 0>,
+			<&gpiod 1 0>,
+			<&gpiod 0 0>,
+			<&gpioe 3 0>,
+			<&gpio0 4 0>,
+			<&gpiod 6 0>,
+			<&gpio3 2 0>,
+			<&gpio3 5 0>,
+			<&gpiod 7 0>,
+			<&gpio8 6 0>,
+			<&gpiod 4 0>,
+			<&gpio4 1 0>,
+			<&gpio3 4 0>,
+			<&gpioc 7 0>,
+			<&gpioa 4 0>,
+			<&gpio9 6 0>,
+			<&gpio9 3 0>,
+			<&gpioa 7 0>,
+			<&gpio5 0 0>,
+			<&gpio8 1 0>,
+			<&gpiob 7 0>;
+	};
+};
+
+/* Power switch logic input pads */
+&psl_in1_gpd2 {
+	/* ACOK_OD */
+	psl-in-mode = "edge";
+	psl-in-pol = "high-rising";
+};
+
+&psl_in2_gp00 {
+	/* EC_PWR_BTN_ODL */
+	psl-in-mode = "edge";
+	psl-in-pol = "low-falling";
+};
+
+&psl_in3_gp01 {
+	/* LID_OPEN_EC */
+	psl-in-mode = "edge";
+	psl-in-pol = "high-rising";
+};
+
+&psl_in4_gp02 {
+	/* RTC_EC_WAKE_ODL */
+	psl-in-mode = "edge";
+	psl-in-pol = "low-falling";
+};
+
+/* Power domain device controlled by PSL (Power Switch Logic) IO pads */
+&power_ctrl_psl {
+	status = "okay";
+	pinctrl-names = "sleep";
+	pinctrl-0 = <&psl_in1_gpd2 &psl_in2_gp00 &psl_in3_gp01 &psl_in4_gp02>;
+};
diff --git a/zephyr/program/herobrine/herobrine/CMakeLists.txt b/zephyr/program/herobrine/herobrine/CMakeLists.txt
new file mode 100644
index 0000000000..5524db7215
--- /dev/null
+++ b/zephyr/program/herobrine/herobrine/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC
+  "src/alt_dev_replacement.c")
diff --git a/zephyr/program/herobrine/herobrine/led_pins.dtsi b/zephyr/program/herobrine/herobrine/led_pins.dtsi
new file mode 100644
index 0000000000..f3580fc491
--- /dev/null
+++ b/zephyr/program/herobrine/herobrine/led_pins.dtsi
@@ -0,0 +1,58 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	gpio-led-pins {
+		compatible = "cros-ec,gpio-led-pins";
+
+		left_led: left-led {
+			led-id = "EC_LED_ID_LEFT_LED";
+			led-pins = <&gpio_ec_chg_led_y_c1
+				    &gpio_ec_chg_led_w_c1>;
+
+			color_off_left: color-off-left {
+				led-color = "LED_OFF";
+				led-values = <0 0>;
+			};
+
+			color_amber_left: color-amber-left {
+				led-color = "LED_AMBER";
+				br-color = "EC_LED_COLOR_AMBER";
+				led-values = <1 0>;
+			};
+
+			color_white_left: color-white-left {
+				led-color = "LED_WHITE";
+				br-color = "EC_LED_COLOR_WHITE";
+				led-values = <0 1>;
+			};
+		};
+
+		right_led: right-led {
+			led-id = "EC_LED_ID_RIGHT_LED";
+			led-pins = <&gpio_ec_chg_led_y_c0
+				    &gpio_ec_chg_led_w_c0>;
+
+			color_off_right: color-off-right {
+				led-color = "LED_OFF";
+				led-values = <0 0>;
+			};
+
+
+			color_amber_right: color-amber-right {
+				led-color = "LED_AMBER";
+				br-color = "EC_LED_COLOR_AMBER";
+				led-values = <1 0>;
+			};
+
+
+			color_white_right: color-white-right {
+				led-color = "LED_WHITE";
+				br-color = "EC_LED_COLOR_WHITE";
+				led-values = <0 1>;
+			};
+		};
+	};
+};
diff --git a/zephyr/program/herobrine/herobrine/led_policy.dtsi b/zephyr/program/herobrine/herobrine/led_policy.dtsi
new file mode 100644
index 0000000000..01a6cbb960
--- /dev/null
+++ b/zephyr/program/herobrine/herobrine/led_policy.dtsi
@@ -0,0 +1,202 @@
+#include <dt-bindings/battery.h>
+
+/ {
+	led-colors {
+		compatible = "cros-ec,led-policy";
+
+		power-state-charge-left {
+			charge-state = "LED_PWRS_CHARGE";
+			charge-port = <1>; /* Left port */
+
+			/* Turn off the right LED */
+			color-0 {
+				led-color = <&color_off_right>;
+			};
+			/* Left LED to Amber */
+			color-1 {
+				led-color = <&color_amber_left>;
+			};
+		};
+
+		power-state-charge-right {
+			charge-state = "LED_PWRS_CHARGE";
+			charge-port = <0>; /* Right port */
+
+			/* Turn off the left LED */
+			color-0 {
+				led-color = <&color_off_left>;
+			};
+			/* Right LED to Amber */
+			color-1 {
+				led-color = <&color_amber_right>;
+			};
+		};
+
+		power-state-discharge-right-low {
+			charge-state = "LED_PWRS_DISCHARGE";
+			/* Battery percent range (>= Empty, <= Low) */
+			batt-lvl = <BATTERY_LEVEL_EMPTY BATTERY_LEVEL_LOW>;
+
+			/* Turn off the left LED */
+			color-0 {
+				led-color = <&color_off_left>;
+			};
+			/* Right LED - White 1 sec, off 3 sec */
+			color-1 {
+				led-color = <&color_white_right>;
+				period-ms = <1000>;
+			};
+			color-2 {
+				led-color = <&color_off_right>;
+				period-ms = <3000>;
+			};
+		};
+
+		power-state-discharge-right {
+			charge-state = "LED_PWRS_DISCHARGE";
+			/* Battery percent range (> Low, <= Full) */
+			batt-lvl = <(BATTERY_LEVEL_LOW + 1) BATTERY_LEVEL_FULL>;
+
+			/* Turn off the left LED */
+			color-0 {
+				led-color = <&color_off_left>;
+			};
+			/* Turn off the right LED */
+			color-1 {
+				led-color = <&color_off_right>;
+			};
+		};
+
+		power-state-error-left {
+			charge-state = "LED_PWRS_ERROR";
+			charge-port = <1>; /* Left port */
+
+			/* Turn off the right LED */
+			color-0 {
+				led-color = <&color_off_right>;
+			};
+			/* Left LED - White 2 sec, off 2 sec */
+			color-1 {
+				led-color = <&color_white_left>;
+				period-ms = <2000>;
+			};
+			color-2 {
+				led-color = <&color_off_right>;
+				period-ms = <2000>;
+			};
+		};
+
+		power-state-error-right {
+			charge-state = "LED_PWRS_ERROR";
+			charge-port = <0>; /* Right port */
+
+			/* Turn off the left LED */
+			color-0 {
+				led-color = <&color_off_left>;
+			};
+			/* Right LED - White 2 sec, off 2 sec */
+			color-1 {
+				led-color = <&color_white_right>;
+				period-ms = <2000>;
+			};
+			color-2 {
+				led-color = <&color_off_right>;
+				period-ms = <2000>;
+			};
+		};
+
+		power-state-near-full-left {
+			charge-state = "LED_PWRS_CHARGE_NEAR_FULL";
+			charge-port = <1>; /* Left port */
+
+			/* Turn off the right LED */
+			color-0 {
+				led-color = <&color_off_right>;
+			};
+			/* Left LED to White */
+			color-1 {
+				led-color = <&color_white_left>;
+			};
+		};
+
+		power-state-near-full-right {
+			charge-state = "LED_PWRS_CHARGE_NEAR_FULL";
+			charge-port = <0>; /* Right port */
+
+			/* Turn off the left LED */
+			color-0 {
+				led-color = <&color_off_left>;
+			};
+			/* Right LED to White */
+			color-1 {
+				led-color = <&color_white_right>;
+			};
+		};
+
+		power-state-forced-idle-left {
+			charge-state = "LED_PWRS_FORCED_IDLE";
+			charge-port = <1>; /* Left port */
+
+			/* Turn off the right LED */
+			color-0 {
+				led-color = <&color_off_right>;
+			};
+			/* Left LED - Amber 3 sec, Off 1 sec */
+			color-1 {
+				led-color = <&color_amber_left>;
+				period-ms = <3000>;
+			};
+			color-2 {
+				led-color = <&color_off_left>;
+				period-ms = <1000>;
+			};
+		};
+
+		power-state-forced-idle-right {
+			charge-state = "LED_PWRS_FORCED_IDLE";
+			charge-port = <0>; /* Right port */
+
+			/* Turn off the left LED */
+			color-0 {
+				led-color = <&color_off_left>;
+			};
+			/* Right LED - Amber 3 sec, Off 1 sec */
+			color-1 {
+				led-color = <&color_amber_right>;
+				period-ms = <3000>;
+			};
+			color-2 {
+				led-color = <&color_off_right>;
+				period-ms = <1000>;
+			};
+		};
+
+		power-state-idle-left {
+			charge-state = "LED_PWRS_IDLE";
+			charge-port = <1>; /* Left port */
+
+			/* Turn off the right LED */
+			color-0 {
+				led-color = <&color_off_right>;
+			};
+			/* Left LED to White */
+			color-1 {
+				led-color = <&color_white_left>;
+			};
+		};
+
+		power-state-idle-right {
+			charge-state = "LED_PWRS_IDLE";
+			charge-port = <0>; /* Right port */
+
+			/* Turn off the left LED */
+			color-0 {
+				led-color = <&color_off_left>;
+			};
+			/* Right LED to White */
+			color-1 {
+				led-color = <&color_white_right>;
+			};
+		};
+	};
+};
diff --git a/zephyr/program/herobrine/herobrine/project.conf b/zephyr/program/herobrine/herobrine/project.conf
new file mode 100644
index 0000000000..bf39f65692
--- /dev/null
+++ b/zephyr/program/herobrine/herobrine/project.conf
@@ -0,0 +1,13 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Herobrine-NPCX9 reference-board-specific Kconfig settings.
+CONFIG_BOARD_HEROBRINE=y
+
+# Sensors
+CONFIG_PLATFORM_EC_ALS=y
+
+# Sensor Drivers
+CONFIG_PLATFORM_EC_ALS_TCS3400=y
+CONFIG_PLATFORM_EC_ALS_TCS3400_EMULATED_IRQ_EVENT=y
diff --git a/zephyr/program/herobrine/herobrine/project.overlay b/zephyr/program/herobrine/herobrine/project.overlay
new file mode 100644
index 0000000000..6ee53f67f0
--- /dev/null
+++ b/zephyr/program/herobrine/herobrine/project.overlay
@@ -0,0 +1,64 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Herobrine program common DTS includes */
+#include "../adc.dtsi"
+#include "../common.dtsi"
+#include "../i2c.dtsi"
+#include "../interrupts.dtsi"
+#include "../keyboard.dtsi"
+#include "../default_gpio_pinctrl.dtsi"
+#include "../display.dtsi"
+#include "../gpio.dtsi"
+#include "../motionsense.dtsi"
+#include "../switchcap.dtsi"
+#include "../usbc.dtsi"
+
+/* Herobrine project DTS includes*/
+#include "led_pins.dtsi"
+#include "led_policy.dtsi"
+
+/* herobrine overrides follow... */
+/* battery overrides */
+/ {
+	batteries {
+		default_battery: ap16l5j {
+			compatible = "panasonic,ap16l5j", "battery-smart";
+		};
+	};
+};
+
+/* i2c overrides */
+&i2c1_0 {
+
+	/delete-node/ syv682x@41;
+	ppc_port0: sn5s330@40 {
+		compatible = "ti,sn5s330";
+		status = "okay";
+		reg = <0x40>;
+	};
+
+	ppc_port0_alt: syv682x@41 {
+		compatible = "silergy,syv682x";
+		status = "okay";
+		reg = <0x41>;
+		frs_en_gpio = <&gpio_usb_c0_frs_en>;
+	};
+};
+
+&i2c2_0 {
+
+	/delete-node/ syv682x@41;
+	ppc_port1: sn5s330@40 {
+		compatible = "ti,sn5s330";
+		status = "okay";
+		reg = <0x40>;
+	};
+};
+
+/* usbc overrides */
+&port0 {
+	ppc_alt = <&ppc_port0_alt>;
+};
diff --git a/zephyr/program/herobrine/herobrine/src/alt_dev_replacement.c b/zephyr/program/herobrine/herobrine/src/alt_dev_replacement.c
new file mode 100644
index 0000000000..e1e9250ec4
--- /dev/null
+++ b/zephyr/program/herobrine/herobrine/src/alt_dev_replacement.c
@@ -0,0 +1,37 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "cros_board_info.h"
+#include "hooks.h"
+#include "usbc/ppc.h"
+
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(alt_dev_replacement);
+
+#define BOARD_VERSION_UNKNOWN 0xffffffff
+
+/* Check board version to decide which ppc is used. */
+static bool board_has_alt_ppc(void)
+{
+	static uint32_t board_version = BOARD_VERSION_UNKNOWN;
+
+	if (board_version == BOARD_VERSION_UNKNOWN) {
+		if (cbi_get_board_version(&board_version) != EC_SUCCESS) {
+			LOG_ERR("Failed to get board version.");
+			board_version = 0;
+		}
+	}
+
+	return (board_version >= 1);
+}
+
+static void check_alternate_devices(void)
+{
+	/* Configure the PPC driver */
+	if (board_has_alt_ppc())
+		/* Arg is the USB port number */
+		PPC_ENABLE_ALTERNATE(0);
+}
+DECLARE_HOOK(HOOK_INIT, check_alternate_devices, HOOK_PRIO_DEFAULT);
diff --git a/zephyr/program/herobrine/hoglin/gpio.dtsi b/zephyr/program/herobrine/hoglin/gpio.dtsi
new file mode 100644
index 0000000000..cf5a894730
--- /dev/null
+++ b/zephyr/program/herobrine/hoglin/gpio.dtsi
@@ -0,0 +1,322 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	aliases {
+		gpio-wp = &gpio_ec_wp_odl;
+		gpio-kbd-kso2 = &gpio_ec_kso_02_inv;
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		gpio_usb_c0_pd_int_odl: usb_c0_pd_int_odl {
+			gpios = <&gpioe 0 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_USB_C0_PD_INT_ODL";
+		};
+		gpio_usb_c1_pd_int_odl: usb_c1_pd_int_odl {
+			gpios = <&gpiof 5 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_USB_C1_PD_INT_ODL";
+		};
+		gpio_usb_c0_swctl_int_odl: usb_c0_swctl_int_odl {
+			gpios = <&gpio0 3 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C0_SWCTL_INT_ODL";
+		};
+		gpio_usb_c1_swctl_int_odl: usb_c1_swctl_int_odl {
+			gpios = <&gpio4 0 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C1_SWCTL_INT_ODL";
+		};
+		gpio_usb_c0_bc12_int_l: usb_c0_bc12_int_l {
+			gpios = <&gpio6 1 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_usb_c1_bc12_int_l: usb_c1_bc12_int_l {
+			gpios = <&gpio8 2 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_usb_a0_oc_odl: usb_a0_oc_odl {
+			gpios = <&gpiof 4 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_chg_acok_od: chg_acok_od {
+			gpios = <&gpiod 2 GPIO_INPUT>;
+			enum-name = "GPIO_AC_PRESENT";
+		};
+		gpio_ec_pwr_btn_odl: ec_pwr_btn_odl {
+			gpios = <&gpio0 0 GPIO_INPUT>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		gpio_ec_voldn_btn_odl: ec_voldn_btn_odl {
+			gpios = <&gpio6 2 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_DOWN_L";
+		};
+		gpio_ec_volup_btn_odl: ec_volup_btn_odl {
+			gpios = <&gpioc 2 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_UP_L";
+		};
+		gpio_ec_wp_odl: ec_wp_odl {
+			gpios = <&gpiod 3 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_lid_open_ec: lid_open_ec {
+			gpios = <&gpio0 1 GPIO_INPUT>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+		gpio_ap_rst_l: ap_rst_l {
+			gpios = <&gpio5 1 GPIO_INPUT>;
+			enum-name = "GPIO_AP_RST_L";
+		};
+		gpio_ps_hold: ps_hold {
+			gpios = <&gpioa 6 GPIO_INPUT_PULL_DOWN>;
+			enum-name = "GPIO_PS_HOLD";
+		};
+		gpio_ap_suspend: ap_suspend {
+			gpios = <&gpio5 7 GPIO_INPUT>;
+			enum-name = "GPIO_AP_SUSPEND";
+		};
+		gpio_mb_power_good: mb_power_good {
+			gpios = <&gpio3 7 GPIO_INPUT_PULL_DOWN>;
+			enum-name = "GPIO_POWER_GOOD";
+		};
+		gpio_warm_reset_l: warm_reset_l {
+			gpios = <&gpiob 0 GPIO_INPUT>;
+			enum-name = "GPIO_WARM_RESET_L";
+		};
+		ap_ec_spi_cs_l {
+			gpios = <&gpio5 3 GPIO_INPUT_PULL_DOWN>;
+		};
+		gpio_tablet_mode_l: tablet_mode_l {
+			gpios = <&gpioc 6 GPIO_INPUT>;
+			enum-name = "GPIO_TABLET_MODE_L";
+		};
+		gpio_accel_gyro_int_l: accel_gyro_int_l {
+			gpios = <&gpioa 3 GPIO_INPUT>;
+		};
+		gpio_rtc_ec_wake_odl: rtc_ec_wake_odl {
+			gpios = <&gpio0 2 GPIO_INPUT>;
+		};
+		ec_entering_rw {
+			gpios = <&gpio7 2 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_ENTERING_RW";
+		};
+		ccd_mode_odl {
+			gpios = <&gpio6 3 GPIO_INPUT>;
+			enum-name = "GPIO_CCD_MODE_ODL";
+		};
+		ec_batt_pres_odl {
+			gpios = <&gpioe 5 GPIO_INPUT>;
+			enum-name = "GPIO_BATT_PRES_ODL";
+		};
+		ec_gsc_packet_mode {
+			gpios = <&gpio8 3 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_PACKET_MODE_EN";
+		};
+		pmic_resin_l {
+			gpios = <&gpioa 0 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_PMIC_RESIN_L";
+		};
+		pmic_kpd_pwr_odl {
+			gpios = <&gpioa 2 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_PMIC_KPD_PWR_ODL";
+		};
+		ap_ec_int_l {
+			gpios = <&gpio5 6 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_EC_INT_L";
+		};
+		gpio_switchcap_on: switchcap_on {
+			gpios = <&gpio5 0 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_SWITCHCAP_ON";
+		};
+		gpio_en_pp5000_s5: en_pp5000_s5 {
+			gpios = <&gpio7 3 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_EN_PP5000";
+		};
+		ec_bl_disable_l {
+			/* The PMIC controls backlight enable and this pin must
+			 * be HiZ for normal operation. The EC is allowed to
+			 * drive low to abruptly removes power from the eDP
+			 * panel in cases like lid close. So the signal is open
+			 * drain (allowed to drive low, never drive high).
+			 */
+			gpios = <&gpiob 6 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_ENABLE_BACKLIGHT";
+		};
+		lid_accel_int_l {
+			gpios = <&gpioa 1 GPIO_INPUT>;
+		};
+		tp_int_gate {
+			gpios = <&gpio7 4 GPIO_OUTPUT_LOW>;
+		};
+		gpio_usb_c0_pd_rst_l: usb_c0_pd_rst_l {
+			gpios = <&gpiof 1 (GPIO_OUTPUT_HIGH | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_usb_c1_pd_rst_l: usb_c1_pd_rst_l {
+			gpios = <&gpioe 4 (GPIO_OUTPUT_HIGH | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_dp_mux_oe_l: dp_mux_oe_l {
+			gpios = <&gpiob 1 GPIO_ODR_HIGH>;
+		};
+		gpio_dp_mux_sel: dp_mux_sel {
+			gpios = <&gpio4 5 GPIO_OUTPUT_LOW>;
+		};
+		gpio_dp_hot_plug_det_r: dp_hot_plug_det_r {
+			gpios = <&gpio9 5 GPIO_OUTPUT_LOW>;
+		};
+		gpio_en_usb_a_5v: en_usb_a_5v {
+			gpios = <&gpiof 0 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_EN_USB_A_5V";
+		};
+		usb_a_cdp_ilim_en_l {
+			gpios = <&gpio7 5 GPIO_OUTPUT_HIGH>;
+		};
+		gpio_usb_c0_frs_en: usb_c0_frs_en {
+			gpios = <&gpioc 5 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_USB_C0_FRS_EN";
+		};
+		gpio_usb_c1_frs_en: usb_c1_frs_en {
+			gpios = <&gpioc 1 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_USB_C1_FRS_EN";
+		};
+		gpio_ec_chg_led_b_c0: ec_chg_led_b_c0 {
+			gpios = <&gpio6 0 GPIO_OUTPUT_LOW>;
+		};
+		gpio_ec_chg_led_r_c0: ec_chg_led_r_c0 {
+			gpios = <&gpioc 0 GPIO_OUTPUT_LOW>;
+		};
+		gpio_ec_chg_led_y_c1: ec_chg_led_b_c1 {
+			gpios = <&gpioc 3 GPIO_OUTPUT_LOW>;
+		};
+		gpio_ec_chg_led_w_c1: ec_chg_led_r_c1 {
+			gpios = <&gpioc 4 GPIO_OUTPUT_LOW>;
+		};
+		ap_ec_spi_mosi {
+			gpios = <&gpio4 6 GPIO_INPUT_PULL_DOWN>;
+		};
+		ap_ec_spi_miso {
+			gpios = <&gpio4 7 GPIO_INPUT_PULL_DOWN>;
+		};
+		ap_ec_spi_clk {
+			gpios = <&gpio5 5 GPIO_INPUT_PULL_DOWN>;
+		};
+		gpio_brd_id0: brd_id0 {
+			gpios = <&gpio9 4 GPIO_INPUT>;
+			enum-name = "GPIO_BOARD_VERSION1";
+		};
+		gpio_brd_id1: brd_id1 {
+			gpios = <&gpio9 7 GPIO_INPUT>;
+			enum-name = "GPIO_BOARD_VERSION2";
+		};
+		gpio_brd_id2: brd_id2 {
+			gpios = <&gpioa 5 GPIO_INPUT>;
+			enum-name = "GPIO_BOARD_VERSION3";
+		};
+		gpio_sku_id0: sku_id0 {
+			gpios = <&gpio6 7 GPIO_INPUT>;
+		};
+		gpio_sku_id1: sku_id1 {
+			gpios = <&gpio7 0 GPIO_INPUT>;
+		};
+		gpio_sku_id2: sku_id2 {
+			gpios = <&gpioe 1 GPIO_INPUT>;
+		};
+		gpio_switchcap_pg: src_vph_pwr_pg {
+			gpios = <&gpioe 2 GPIO_INPUT_PULL_DOWN>;
+			enum-name = "GPIO_SWITCHCAP_PG";
+		};
+		arm_x86 {
+			gpios = <&gpio6 6 GPIO_OUTPUT_LOW>;
+		};
+		ec-i2c-sensor-scl {
+			gpios = <&gpiob 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		ec-i2c-sensor-sda {
+			gpios = <&gpiob 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		gpio_ec_kso_02_inv: ec_kso_02_inv {
+			gpios = <&gpio1 7 (GPIO_OUTPUT_LOW | GPIO_ACTIVE_LOW)>;
+		};
+	};
+
+	usba-port-enable-list {
+		compatible = "cros-ec,usba-port-enable-pins";
+		enable-pins = <&gpio_en_usb_a_5v>;
+	};
+
+	gpio_id_sku: sku {
+		compatible = "cros-ec,gpio-id";
+		bits  = <
+			&gpio_sku_id0
+			&gpio_sku_id1
+			&gpio_sku_id2
+		>;
+		system = "ternary";
+	};
+
+	gpio_id_board: board {
+		compatible = "cros-ec,gpio-id";
+		bits  = <
+			&gpio_brd_id0
+			&gpio_brd_id1
+			&gpio_brd_id2
+		>;
+		system = "ternary";
+	};
+
+	unused-pins {
+		compatible = "unused-gpios";
+		unused-gpios =
+			<&gpio5 2 0>,
+			<&gpio5 4 0>,
+			<&gpio7 6 0>,
+			<&gpiod 1 0>,
+			<&gpiod 0 0>,
+			<&gpioe 3 0>,
+			<&gpio0 4 0>,
+			<&gpiod 6 0>,
+			<&gpio3 2 0>,
+			<&gpio3 5 0>,
+			<&gpiod 7 0>,
+			<&gpio8 6 0>,
+			<&gpiod 4 0>,
+			<&gpio4 1 0>,
+			<&gpio3 4 0>,
+			<&gpioc 7 0>,
+			<&gpioa 4 0>,
+			<&gpio9 6 0>,
+			<&gpio9 3 0>,
+			<&gpioa 7 0>,
+			<&gpiod 5 0>,
+			<&gpio8 1 0>,
+			<&gpiob 7 0>;
+	};
+};
+
+/* Power switch logic input pads */
+&psl_in1_gpd2 {
+	/* ACOK_OD */
+	psl-in-mode = "edge";
+	psl-in-pol = "high-rising";
+};
+
+&psl_in2_gp00 {
+	/* EC_PWR_BTN_ODL */
+	psl-in-mode = "edge";
+	psl-in-pol = "low-falling";
+};
+
+&psl_in3_gp01 {
+	/* LID_OPEN_EC */
+	psl-in-mode = "edge";
+	psl-in-pol = "high-rising";
+};
+
+&psl_in4_gp02 {
+	/* RTC_EC_WAKE_ODL */
+	psl-in-mode = "edge";
+	psl-in-pol = "low-falling";
+};
+
+/* Power domain device controlled by PSL (Power Switch Logic) IO pads */
+&power_ctrl_psl {
+	status = "okay";
+	pinctrl-names = "sleep";
+	pinctrl-0 = <&psl_in1_gpd2 &psl_in2_gp00 &psl_in3_gp01 &psl_in4_gp02>;
+};
diff --git a/zephyr/program/herobrine/hoglin/led_pins.dtsi b/zephyr/program/herobrine/hoglin/led_pins.dtsi
new file mode 100644
index 0000000000..1f5d649215
--- /dev/null
+++ b/zephyr/program/herobrine/hoglin/led_pins.dtsi
@@ -0,0 +1,33 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	gpio-led-pins {
+		compatible = "cros-ec,gpio-led-pins";
+
+		battery_led: battery-led {
+			led-id = "EC_LED_ID_BATTERY_LED";
+			led-pins = <&gpio_ec_chg_led_b_c0
+				    &gpio_ec_chg_led_r_c0>;
+
+			color_off: color-off {
+				led-color = "LED_OFF";
+				led-values = <0 0>;
+			};
+
+			color_blue: color-blue {
+				led-color = "LED_BLUE";
+				br-color = "EC_LED_COLOR_BLUE";
+				led-values = <1 0>;
+			};
+
+			color_red: color-red {
+				led-color = "LED_RED";
+				br-color = "EC_LED_COLOR_RED";
+				led-values = <0 1>;
+			};
+		};
+	};
+};
diff --git a/zephyr/program/herobrine/hoglin/led_policy.dtsi b/zephyr/program/herobrine/hoglin/led_policy.dtsi
new file mode 100644
index 0000000000..93edd82fb3
--- /dev/null
+++ b/zephyr/program/herobrine/hoglin/led_policy.dtsi
@@ -0,0 +1,95 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	led-colors {
+		compatible = "cros-ec,led-policy";
+
+		power-state-charge {
+			charge-state = "LED_PWRS_CHARGE";
+
+			color-0 {
+				led-color = <&color_blue>;
+			};
+		};
+
+		power-state-discharge-s0 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S0";
+
+			color-0 {
+				led-color = <&color_off>;
+			};
+		};
+
+		power-state-discharge-s3 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S3";
+
+			/* Blue 1 sec, off 3 sec */
+			color-0 {
+				led-color = <&color_blue>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <3000>;
+			};
+		};
+
+		power-state-discharge-s5 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S5";
+
+			color-0 {
+				led-color = <&color_off>;
+			};
+		};
+
+		power-state-error {
+			charge-state = "LED_PWRS_ERROR";
+
+			/* Red 1 sec, off 1 sec */
+			color-0 {
+				led-color = <&color_red>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <1000>;
+			};
+		};
+
+		power-state-near-full {
+			charge-state = "LED_PWRS_CHARGE_NEAR_FULL";
+
+			color-0 {
+				led-color = <&color_red>;
+			};
+		};
+
+		power-state-forced-idle {
+			charge-state = "LED_PWRS_FORCED_IDLE";
+
+			/* Red 2 sec, Blue 2 sec */
+			color-0 {
+				led-color = <&color_red>;
+				period-ms = <2000>;
+			};
+			color-1 {
+				led-color = <&color_blue>;
+				period-ms = <2000>;
+			};
+		};
+
+		power-state-idle-default {
+			charge-state = "LED_PWRS_IDLE";
+
+			color-0 {
+				led-color = <&color_red>;
+			};
+		};
+	};
+};
diff --git a/zephyr/program/herobrine/hoglin/motionsense.dtsi b/zephyr/program/herobrine/hoglin/motionsense.dtsi
new file mode 100644
index 0000000000..c3935178ff
--- /dev/null
+++ b/zephyr/program/herobrine/hoglin/motionsense.dtsi
@@ -0,0 +1,241 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/motionsense/utils.h>
+
+
+/ {
+	aliases {
+		/*
+		 * motion sense's <>_INT_EVENT is handled
+		 * by alias. Using the alias, each driver creates
+		 * its own <>_INT_EVENT.
+		 */
+		bmi260-int = &base_accel;
+		tcs3400-int = &als_clear;
+	};
+
+	/*
+	 * Declare mutexes used by sensor drivers.
+	 * A mutex node is used to create an instance of mutex_t.
+	 * A mutex node is referenced by a sensor node if the
+	 * corresponding sensor driver needs to use the
+	 * instance of the mutex.
+	 */
+	motionsense-mutex {
+		compatible = "cros-ec,motionsense-mutex";
+		lid_mutex: lid-mutex {
+		};
+
+		mutex_bmi260: bmi260-mutex {
+		};
+	};
+
+	/* Rotation matrix used by drivers. */
+	motionsense-rotation-ref {
+		compatible = "cros-ec,motionsense-rotation-ref";
+		lid_rot_ref: lid-rotation-ref {
+			mat33 = <(-1) 0 0
+				 0 (-1) 0
+				 0 0 1>;
+		};
+
+		base_rot_ref: base-rotation-ref {
+			mat33 = <1 0 0
+				 0 (-1) 0
+				 0 0 (-1)>;
+		};
+	};
+
+	/*
+	 * Driver specific data. A driver-specific data can be shared with
+	 * different motion sensors while they are using the same driver.
+	 *
+	 * If a node's compatible starts with "cros-ec,accelgyro-", it is for
+	 * a common structure defined in accelgyro.h.
+	 * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for
+	 * "struct als_drv_data_t" in accelgyro.h
+	 */
+	motionsense-sensor-data {
+		bma4xx_data: bma4xx-drv-data {
+			compatible = "cros-ec,drvdata-bma4xx";
+			status = "okay";
+		};
+
+		bmi260_data: bmi260-drv-data {
+			compatible = "cros-ec,drvdata-bmi260";
+			status = "okay";
+		};
+
+		tcs_clear_data: tcs3400-clear-drv-data {
+			compatible = "cros-ec,drvdata-tcs3400-clear";
+			status = "okay";
+
+			als-drv-data {
+				compatible = "cros-ec,accelgyro-als-drv-data";
+				als-cal {
+					scale = <1>;
+					uscale = <0>;
+					offset = <0>;
+					als-channel-scale {
+						compatible = "cros-ec,accelgyro-als-channel-scale";
+						k-channel-scale = <1>;
+						cover-scale = <1>;
+					};
+				};
+			};
+		};
+
+		tcs_rgb_data: tcs3400-rgb-drv-data {
+			compatible = "cros-ec,drvdata-tcs3400-rgb";
+			status = "okay";
+
+			/* node for rgb_calibration_t defined in accelgyro.h */
+			rgb_calibration {
+				compatible =
+					"cros-ec,accelgyro-rgb-calibration";
+
+				irt = <1>;
+
+				rgb-cal-x {
+					offset = <0>;
+					coeff = <0 0 0 1>;
+					als-channel-scale {
+						compatible = "cros-ec,accelgyro-als-channel-scale";
+						k-channel-scale = <1>;
+						cover-scale = <1>;
+					};
+				};
+				rgb-cal-y {
+					offset = <0>;
+					coeff = <0 0 0 1>;
+					als-channel-scale {
+						compatible = "cros-ec,accelgyro-als-channel-scale";
+						k-channel-scale = <1>;
+						cover-scale = <1>;
+					};
+				};
+				rgb-cal-z {
+					offset = <0>;
+					coeff = <0 0 0 1>;
+					als-channel-scale {
+						compatible = "cros-ec,accelgyro-als-channel-scale";
+						k-channel-scale = <1>;
+						cover-scale = <1>;
+					};
+				};
+			};
+		};
+	};
+
+	/*
+	 * List of motion sensors that creates motion_sensors array.
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
+	 * motion sensor IDs for lid angle calculation.
+	 */
+	motionsense-sensor {
+		lid_accel: lid-accel {
+			compatible = "cros-ec,bma4xx";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&lid_mutex>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&lid_rot_ref>;
+			default-range = <2>;
+			drv-data = <&bma4xx_data>;
+			i2c-spi-addr-flags = "BMA4_I2C_ADDR_PRIMARY";
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_accel: base-accel {
+			compatible = "cros-ec,bmi260-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&mutex_bmi260>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&bmi260_data>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base-gyro {
+			compatible = "cros-ec,bmi260-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&mutex_bmi260>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&bmi260_data>;
+		};
+
+		als_clear: base-als-clear {
+			compatible = "cros-ec,tcs3400-clear";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_CAMERA";
+			port = <&i2c_sensor>;
+			default-range = <0x10000>;
+			drv-data = <&tcs_clear_data>;
+			i2c-spi-addr-flags = "TCS3400_I2C_ADDR_FLAGS";
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					/* Run ALS sensor in S0 */
+					odr = <1000>;
+				};
+			};
+		};
+
+		base-als-rgb {
+			compatible = "cros-ec,tcs3400-rgb";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_CAMERA";
+			default-range = <0x10000>; /* scale = 1x, uscale = 0 */
+			drv-data = <&tcs_rgb_data>;
+		};
+	};
+
+	motionsense-sensor-info {
+		compatible = "cros-ec,motionsense-sensor-info";
+
+		/* list of entries for motion_als_sensors */
+		als-sensors = <&als_clear>;
+		/*
+		 * list of GPIO interrupts that have to
+		 * be enabled at initial stage
+		 */
+		sensor-irqs = <&int_accel_gyro>;
+		/* list of sensors in force mode */
+		accel-force-mode-sensors = <&lid_accel &als_clear>;
+	};
+};
diff --git a/zephyr/program/herobrine/hoglin/project.conf b/zephyr/program/herobrine/hoglin/project.conf
new file mode 100644
index 0000000000..c6e20937c0
--- /dev/null
+++ b/zephyr/program/herobrine/hoglin/project.conf
@@ -0,0 +1,15 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Hoglin reference-board-specific Kconfig settings.
+CONFIG_BOARD_HOGLIN=y
+CONFIG_PLATFORM_EC_ACCEL_BMA255=n
+CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y
+
+# Sensors
+CONFIG_PLATFORM_EC_ALS=y
+
+# Sensor Drivers
+CONFIG_PLATFORM_EC_ALS_TCS3400=y
+CONFIG_PLATFORM_EC_ALS_TCS3400_EMULATED_IRQ_EVENT=y
diff --git a/zephyr/program/herobrine/hoglin/project.overlay b/zephyr/program/herobrine/hoglin/project.overlay
new file mode 100644
index 0000000000..fb2101d07f
--- /dev/null
+++ b/zephyr/program/herobrine/hoglin/project.overlay
@@ -0,0 +1,74 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Herobrine program common DTS includes */
+#include "../adc.dtsi"
+#include "../common.dtsi"
+#include "../i2c.dtsi"
+#include "../interrupts.dtsi"
+#include "../keyboard.dtsi"
+#include "../default_gpio_pinctrl.dtsi"
+#include "../usbc.dtsi"
+#include "../switchcap.dtsi"
+
+/* Hoglin project DTS includes*/
+#include "gpio.dtsi"
+#include "led_pins.dtsi"
+#include "led_policy.dtsi"
+#include "motionsense.dtsi"
+
+/* hoglin overrides follow... */
+/* battery overrides */
+/ {
+	batteries {
+		default_battery: 7c01 {
+			compatible = "ganfeng,7c01", "battery-smart";
+		};
+	};
+
+};
+
+/* switchcap overrides */
+&{/switchcap} {
+	/delete-property/ power-good-pin;
+	poff-delay-ms = <550>;
+};
+
+/* i2c overrides */
+&i2c1_0 {
+	/delete-node/ ps8xxx@b;
+	tcpc_port0: ps8xxx@1b {
+		compatible = "parade,ps8xxx";
+		reg = <0x1b>;
+		/* a duplicate of the <&gpio_usb_c0_pd_int_odl> node in
+		 * "named-gpios". This is the Zephyr preferred style,
+		 * the "named-gpios" node will be dealt with at a later date.
+		 */
+		irq-gpios = <&gpioe 0 GPIO_ACTIVE_LOW>;
+		/* a duplicate of the <&gpio_usb_c0_pd_rst_l> node in
+		 * "named-gpios". This is the Zephyr preferred style,
+		 * the "named-gpios" node will be dealt with at a later date.
+		 */
+		rst-gpios = <&gpiof 1 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&i2c2_0 {
+	/delete-node/ ps8xxx@b;
+	tcpc_port1: ps8xxx@1b {
+		compatible = "parade,ps8xxx";
+		reg = <0x1b>;
+		/* a duplicate of the <&gpio_usb_c1_pd_int_odl> node in
+		 * "named-gpios". This is the Zephyr preferred style,
+		 * the "named-gpios" node will be dealt with at a later date.
+		 */
+		irq-gpios = <&gpiof 5 GPIO_ACTIVE_LOW>;
+		/* a duplicate of the <&gpio_usb_c1_pd_rst_l> node in
+		 * "named-gpios". This is the Zephyr preferred style,
+		 * the "named-gpios" node will be dealt with at a later date.
+		 */
+		rst-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
+	};
+};
diff --git a/zephyr/program/herobrine/i2c.dtsi b/zephyr/program/herobrine/i2c.dtsi
new file mode 100644
index 0000000000..c0c904b2c9
--- /dev/null
+++ b/zephyr/program/herobrine/i2c.dtsi
@@ -0,0 +1,201 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	aliases {
+		i2c-0 = &i2c0_0;
+		i2c-1 = &i2c1_0;
+		i2c-2 = &i2c2_0;
+		i2c-3 = &i2c3_0;
+		i2c-4 = &i2c4_1;
+		i2c-5 = &i2c5_0;
+		i2c-7 = &i2c7_0;
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		i2c_power: power {
+			i2c-port = <&i2c0_0>;
+			remote-port = <0>;
+			enum-names = "I2C_PORT_POWER",
+				"I2C_PORT_BATTERY",
+				"I2C_PORT_VIRTUAL_BATTERY",
+				"I2C_PORT_CHARGER";
+		};
+		i2c_tcpc0: tcpc0 {
+			i2c-port = <&i2c1_0>;
+			dynamic-speed;
+			enum-names = "I2C_PORT_TCPC0";
+		};
+		i2c_tcpc1: tcpc1 {
+			i2c-port = <&i2c2_0>;
+			dynamic-speed;
+			enum-names = "I2C_PORT_TCPC1";
+		};
+		rtc {
+			i2c-port = <&i2c4_1>;
+			enum-names = "I2C_PORT_RTC";
+		};
+		i2c_eeprom: eeprom {
+			i2c-port = <&i2c5_0>;
+			enum-names = "I2C_PORT_EEPROM";
+		};
+		i2c_sensor: sensor {
+			i2c-port = <&i2c7_0>;
+			enum-names = "I2C_PORT_SENSOR",
+				"I2C_PORT_ACCEL";
+		};
+	};
+
+
+};
+
+&i2c0_0 {
+	label = "I2C_POWER";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>;
+	pinctrl-names = "default";
+
+	bc12_port0: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+		irq = <&int_usb_c0_bc12>;
+	};
+
+	charger: isl923x@9 {
+		compatible = "intersil,isl923x";
+		status = "okay";
+		reg = <0x9>;
+	};
+};
+
+&i2c_ctrl0 {
+	status = "okay";
+};
+
+&i2c1_0 {
+	label = "I2C_USB_C0_PD";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+	pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>;
+	pinctrl-names = "default";
+
+	ppc_port0: syv682x@41 {
+		compatible = "silergy,syv682x";
+		status = "okay";
+		reg = <0x41>;
+		frs_en_gpio = <&gpio_usb_c0_frs_en>;
+	};
+
+	tcpc_port0: ps8xxx@b {
+		compatible = "parade,ps8xxx";
+		reg = <0xb>;
+		/* a duplicate of the <&gpio_usb_c0_pd_int_odl> node in
+		 * "named-gpios". This is the Zephyr preferred style,
+		 * the "named-gpios" node will be dealt with at a later date.
+		 */
+		irq-gpios = <&gpioe 0 GPIO_ACTIVE_LOW>;
+		/* a duplicate of the <&gpio_usb_c0_pd_rst_l> node in
+		 * "named-gpios". This is the Zephyr preferred style,
+		 * the "named-gpios" node will be dealt with at a later date.
+		 */
+		rst-gpios = <&gpiof 1 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&i2c_ctrl1 {
+	status = "okay";
+};
+
+&i2c2_0 {
+	label = "I2C_USB_C1_PD";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+	pinctrl-0 = <&i2c2_0_sda_scl_gp91_92>;
+	pinctrl-names = "default";
+
+	ppc_port1: syv682x@41 {
+		compatible = "silergy,syv682x";
+		status = "okay";
+		reg = <0x41>;
+		frs_en_gpio = <&gpio_usb_c1_frs_en>;
+	};
+
+	tcpc_port1: ps8xxx@b {
+		compatible = "parade,ps8xxx";
+		reg = <0xb>;
+		/* a duplicate of the <&gpio_usb_c1_pd_int_odl> node in
+		 * "named-gpios". This is the Zephyr preferred style,
+		 * the "named-gpios" node will be dealt with at a later date.
+		 */
+		irq-gpios = <&gpiof 5 GPIO_ACTIVE_LOW>;
+		/* a duplicate of the <&gpio_usb_c1_pd_rst_l> node in
+		 * "named-gpios". This is the Zephyr preferred style,
+		 * the "named-gpios" node will be dealt with at a later date.
+		 */
+		rst-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&i2c_ctrl2 {
+	status = "okay";
+};
+
+&i2c3_0 {
+	/* Not used as no WLC connected */
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&i2c4_1 {
+	label = "I2C_RTC";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c4_1_sda_scl_gpf2_f3>;
+	pinctrl-names = "default";
+
+	pcf85063a: pcf85063a@51 {
+		compatible = "nxp,rtc-pcf85063a";
+		reg = <0x51>;
+		int-pin = <&gpio_rtc_ec_wake_odl>;
+	};
+};
+
+&i2c_ctrl4 {
+	status = "okay";
+};
+
+&i2c5_0 {
+	label = "I2C_EEPROM";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c5_0_sda_scl_gp33_36>;
+	pinctrl-names = "default";
+
+	bc12_port1: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+		irq = <&int_usb_c1_bc12>;
+	};
+};
+
+&i2c_ctrl5 {
+	status = "okay";
+};
+
+&i2c7_0 {
+	label = "I2C_SENSOR";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>;
+	pinctrl-names = "default";
+};
+
+&i2c_ctrl7 {
+	status = "okay";
+};
diff --git a/zephyr/program/herobrine/include/board_chipset.h b/zephyr/program/herobrine/include/board_chipset.h
new file mode 100644
index 0000000000..000bc06654
--- /dev/null
+++ b/zephyr/program/herobrine/include/board_chipset.h
@@ -0,0 +1,13 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_HEROBRINE_BOARD_CHIPSET_H
+#define __CROS_EC_HEROBRINE_BOARD_CHIPSET_H
+
+#include "common.h"
+
+__test_only void reset_pp5000_inited(void);
+
+#endif /* __CROS_EC_HEROBRINE_BOARD_CHIPSET_H */
diff --git a/zephyr/program/herobrine/interrupts.dtsi b/zephyr/program/herobrine/interrupts.dtsi
new file mode 100644
index 0000000000..36d31cfffe
--- /dev/null
+++ b/zephyr/program/herobrine/interrupts.dtsi
@@ -0,0 +1,105 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	aliases {
+		int-wp = &int_wp_l;
+	};
+
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_ac_present: ac_present {
+			irq-pin = <&gpio_chg_acok_od>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "extpower_interrupt";
+		};
+		int_lid_open: lid_open {
+			irq-pin = <&gpio_lid_open_ec>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "lid_interrupt";
+		};
+		int_wp_l: wp_l {
+			irq-pin = <&gpio_ec_wp_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "switch_interrupt";
+		};
+		int_power_button: power_button {
+			irq-pin = <&gpio_ec_pwr_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_button_interrupt";
+		};
+		int_volume_up: volume_up {
+			irq-pin = <&gpio_ec_volup_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+		int_volume_down: volume_down {
+			irq-pin = <&gpio_ec_voldn_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+		int_ap_rst: ap_rst {
+			irq-pin = <&gpio_ap_rst_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "chipset_ap_rst_interrupt";
+		};
+		int_ap_suspend: ap_suspend {
+			irq-pin = <&gpio_ap_suspend>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_power_good: power_good {
+			irq-pin = <&gpio_mb_power_good>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_ps_hold: ps_hold {
+			irq-pin = <&gpio_ps_hold>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_warm_reset: warm_reset {
+			irq-pin = <&gpio_warm_reset_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_usb_c0_swctl: usb_c0_swctl {
+			irq-pin = <&gpio_usb_c0_swctl_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "ppc_interrupt";
+		};
+		int_usb_c1_swctl: usb_c1_swctl {
+			irq-pin = <&gpio_usb_c1_swctl_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "ppc_interrupt";
+		};
+		int_usb_c0_bc12: usb_c0_bc12 {
+			irq-pin = <&gpio_usb_c0_bc12_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "usb0_evt";
+		};
+		int_usb_c1_bc12: usb_c1_bc12 {
+			irq-pin = <&gpio_usb_c1_bc12_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "usb1_evt";
+		};
+		int_usb_a0_oc: usb_a0_oc {
+			irq-pin = <&gpio_usb_a0_oc_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "usba_oc_interrupt";
+		};
+		int_accel_gyro: accel_gyro {
+			irq-pin = <&gpio_accel_gyro_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "bmi260_interrupt";
+		};
+		int_tablet_mode: tablet_mode {
+			irq-pin = <&gpio_tablet_mode_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "gmr_tablet_switch_isr";
+		};
+	};
+};
diff --git a/zephyr/program/herobrine/keyboard.dtsi b/zephyr/program/herobrine/keyboard.dtsi
new file mode 100644
index 0000000000..3b7e830f2f
--- /dev/null
+++ b/zephyr/program/herobrine/keyboard.dtsi
@@ -0,0 +1,46 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	kblight {
+		compatible = "cros-ec,kblight-pwm";
+		pwms = <&pwm3 0 PWM_KHZ(10) PWM_POLARITY_NORMAL>;
+		generic-pwm-channel = <0>;
+	};
+};
+
+&pwm3 {
+	status = "okay";
+	pinctrl-0 = <&pwm3_gp80>;
+	pinctrl-names = "default";
+};
+
+&cros_kb_raw {
+	status = "okay";
+	/* No KSO2 (it's inverted and implemented by GPIO) */
+	pinctrl-0 = <
+		&ksi0_gp31
+		&ksi1_gp30
+		&ksi2_gp27
+		&ksi3_gp26
+		&ksi4_gp25
+		&ksi5_gp24
+		&ksi6_gp23
+		&ksi7_gp22
+		&kso00_gp21
+		&kso01_gp20
+		&kso03_gp16
+		&kso04_gp15
+		&kso05_gp14
+		&kso06_gp13
+		&kso07_gp12
+		&kso08_gp11
+		&kso09_gp10
+		&kso10_gp07
+		&kso11_gp06
+		&kso12_gp05
+	>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/herobrine/motionsense.dtsi b/zephyr/program/herobrine/motionsense.dtsi
new file mode 100644
index 0000000000..1955f43284
--- /dev/null
+++ b/zephyr/program/herobrine/motionsense.dtsi
@@ -0,0 +1,241 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/motionsense/utils.h>
+
+
+/ {
+	aliases {
+		/*
+		 * motion sense's <>_INT_EVENT is handled
+		 * by alias. Using the alias, each driver creates
+		 * its own <>_INT_EVENT.
+		 */
+		bmi260-int = &base_accel;
+		tcs3400-int = &als_clear;
+	};
+
+	/*
+	 * Declare mutexes used by sensor drivers.
+	 * A mutex node is used to create an instance of mutex_t.
+	 * A mutex node is referenced by a sensor node if the
+	 * corresponding sensor driver needs to use the
+	 * instance of the mutex.
+	 */
+	motionsense-mutex {
+		compatible = "cros-ec,motionsense-mutex";
+		lid_mutex: lid-mutex {
+		};
+
+		mutex_bmi260: bmi260-mutex {
+		};
+	};
+
+	/* Rotation matrix used by drivers. */
+	motionsense-rotation-ref {
+		compatible = "cros-ec,motionsense-rotation-ref";
+		lid_rot_ref: lid-rotation-ref {
+			mat33 = <0 1 0
+				 1 0 0
+				 0 0 (-1)>;
+		};
+
+		base_rot_ref: base-rotation-ref {
+			mat33 = <1 0 0
+				 0 (-1) 0
+				 0 0 (-1)>;
+		};
+	};
+
+	/*
+	 * Driver specific data. A driver-specific data can be shared with
+	 * different motion sensors while they are using the same driver.
+	 *
+	 * If a node's compatible starts with "cros-ec,accelgyro-", it is for
+	 * a common structure defined in accelgyro.h.
+	 * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for
+	 * "struct als_drv_data_t" in accelgyro.h
+	 */
+	motionsense-sensor-data {
+		bma255_data: bma255-drv-data {
+			compatible = "cros-ec,drvdata-bma255";
+			status = "okay";
+		};
+
+		bmi260_data: bmi260-drv-data {
+			compatible = "cros-ec,drvdata-bmi260";
+			status = "okay";
+		};
+
+		tcs_clear_data: tcs3400-clear-drv-data {
+			compatible = "cros-ec,drvdata-tcs3400-clear";
+			status = "okay";
+
+			als-drv-data {
+				compatible = "cros-ec,accelgyro-als-drv-data";
+				als-cal {
+					scale = <1>;
+					uscale = <0>;
+					offset = <0>;
+					als-channel-scale {
+						compatible = "cros-ec,accelgyro-als-channel-scale";
+						k-channel-scale = <1>;
+						cover-scale = <1>;
+					};
+				};
+			};
+		};
+
+		tcs_rgb_data: tcs3400-rgb-drv-data {
+			compatible = "cros-ec,drvdata-tcs3400-rgb";
+			status = "okay";
+
+			/* node for rgb_calibration_t defined in accelgyro.h */
+			rgb_calibration {
+				compatible =
+					"cros-ec,accelgyro-rgb-calibration";
+
+				irt = <1>;
+
+				rgb-cal-x {
+					offset = <0>;
+					coeff = <0 0 0 1>;
+					als-channel-scale {
+						compatible = "cros-ec,accelgyro-als-channel-scale";
+						k-channel-scale = <1>;
+						cover-scale = <1>;
+					};
+				};
+				rgb-cal-y {
+					offset = <0>;
+					coeff = <0 0 0 1>;
+					als-channel-scale {
+						compatible = "cros-ec,accelgyro-als-channel-scale";
+						k-channel-scale = <1>;
+						cover-scale = <1>;
+					};
+				};
+				rgb-cal-z {
+					offset = <0>;
+					coeff = <0 0 0 1>;
+					als-channel-scale {
+						compatible = "cros-ec,accelgyro-als-channel-scale";
+						k-channel-scale = <1>;
+						cover-scale = <1>;
+					};
+				};
+			};
+		};
+	};
+
+	/*
+	 * List of motion sensors that creates motion_sensors array.
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
+	 * motion sensor IDs for lid angle calculation.
+	 */
+	motionsense-sensor {
+		lid_accel: lid-accel {
+			compatible = "cros-ec,bma255";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&lid_mutex>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&lid_rot_ref>;
+			default-range = <2>;
+			drv-data = <&bma255_data>;
+			i2c-spi-addr-flags = "BMA2x2_I2C_ADDR1_FLAGS";
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_accel: base-accel {
+			compatible = "cros-ec,bmi260-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&mutex_bmi260>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&bmi260_data>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base-gyro {
+			compatible = "cros-ec,bmi260-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&mutex_bmi260>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&bmi260_data>;
+		};
+
+		als_clear: base-als-clear {
+			compatible = "cros-ec,tcs3400-clear";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_CAMERA";
+			port = <&i2c_sensor>;
+			default-range = <0x10000>;
+			drv-data = <&tcs_clear_data>;
+			i2c-spi-addr-flags = "TCS3400_I2C_ADDR_FLAGS";
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					/* Run ALS sensor in S0 */
+					odr = <1000>;
+				};
+			};
+		};
+
+		base-als-rgb {
+			compatible = "cros-ec,tcs3400-rgb";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_CAMERA";
+			default-range = <0x10000>; /* scale = 1x, uscale = 0 */
+			drv-data = <&tcs_rgb_data>;
+		};
+	};
+
+	motionsense-sensor-info {
+		compatible = "cros-ec,motionsense-sensor-info";
+
+		/* list of entries for motion_als_sensors */
+		als-sensors = <&als_clear>;
+		/*
+		 * list of GPIO interrupts that have to
+		 * be enabled at initial stage
+		 */
+		sensor-irqs = <&int_accel_gyro>;
+		/* list of sensors in force mode */
+		accel-force-mode-sensors = <&lid_accel &als_clear>;
+	};
+};
diff --git a/zephyr/program/herobrine/program.conf b/zephyr/program/herobrine/program.conf
new file mode 100644
index 0000000000..d020570762
--- /dev/null
+++ b/zephyr/program/herobrine/program.conf
@@ -0,0 +1,129 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_CROS_EC=y
+CONFIG_PLATFORM_EC=y
+CONFIG_PLATFORM_EC_BRINGUP=y
+CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y
+CONFIG_PLATFORM_EC_SWITCH=y
+CONFIG_PLATFORM_EC_LID_SWITCH=y
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=y
+CONFIG_PLATFORM_EC_POWER_BUTTON=y
+CONFIG_KERNEL_SHELL=y
+CONFIG_PLATFORM_EC_BOARD_RESET_AFTER_POWER_ON=y
+
+# I2C options
+CONFIG_PLATFORM_EC_CONSOLE_CMD_I2C_SPEED=y
+CONFIG_PLATFORM_EC_HOSTCMD_I2C_CONTROL=y
+
+# Shell history and tab autocompletion (for convenience)
+CONFIG_SHELL_HELP=y
+CONFIG_SHELL_HISTORY=y
+CONFIG_SHELL_TAB=y
+CONFIG_SHELL_TAB_AUTOCOMPLETION=y
+
+# Application Processor is Qualcomm SC7280
+CONFIG_AP_ARM_QUALCOMM_SC7280=y
+
+# Board version is selected over GPIO board ID pins.
+CONFIG_PLATFORM_EC_BOARD_VERSION_GPIO=y
+
+# Power Sequencing
+CONFIG_PLATFORM_EC_POWERSEQ=y
+CONFIG_PLATFORM_EC_POWERSEQ_HOST_SLEEP=y
+CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n
+CONFIG_PLATFORM_EC_POWER_SLEEP_FAILURE_DETECTION=y
+CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK=y
+CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK=y
+
+# MKBP event
+CONFIG_PLATFORM_EC_MKBP_EVENT=y
+CONFIG_PLATFORM_EC_MKBP_USE_GPIO=y
+
+# Keyboard
+CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_MKBP=y
+CONFIG_PLATFORM_EC_MKBP_INPUT_DEVICES=y
+CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED=y
+CONFIG_PLATFORM_EC_KEYBOARD_REFRESH_ROW3=y
+CONFIG_PLATFORM_EC_VOLUME_BUTTONS=y
+CONFIG_PLATFORM_EC_CMD_BUTTON=y
+
+# Battery
+CONFIG_PLATFORM_EC_I2C_VIRTUAL_BATTERY=y
+CONFIG_PLATFORM_EC_I2C_PASSTHRU_RESTRICTED=y
+CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y
+CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y
+CONFIG_PLATFORM_EC_CHARGER_ISL9238C=y
+CONFIG_PLATFORM_EC_CHARGE_RAMP_HW=y
+CONFIG_PLATFORM_EC_USE_BATTERY_DEVICE_CHEMISTRY=y
+CONFIG_PLATFORM_EC_BATTERY_DEVICE_CHEMISTRY="LION"
+CONFIG_PLATFORM_EC_BATTERY_REVIVE_DISCONNECT=y
+CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y
+CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC_CHARGER=y
+CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON=2
+CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON=12500
+CONFIG_PLATFORM_EC_CHARGER_MIN_INPUT_CURRENT_LIMIT=512
+CONFIG_PLATFORM_EC_CHARGER_PROFILE_OVERRIDE=y
+CONFIG_PLATFORM_EC_CHARGER_PSYS=y
+CONFIG_PLATFORM_EC_CHARGER_PSYS_READ=y
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=20
+CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_ADC_AMON_BMON=y
+
+# USB-C
+CONFIG_PLATFORM_EC_USB_PD_FRS=y
+CONFIG_PLATFORM_EC_USB_PD_USB32_DRD=n
+CONFIG_PLATFORM_EC_USBC_PPC_SYV682C=y
+CONFIG_PLATFORM_EC_USB_PD_FRS_PPC=y
+CONFIG_PLATFORM_EC_USBC_SS_MUX_DFP_ONLY=y
+CONFIG_PLATFORM_EC_USB_DRP_ACC_TRYSRC=y
+CONFIG_PLATFORM_EC_USB_PD_5V_EN_CUSTOM=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y
+CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y
+CONFIG_PLATFORM_EC_USB_PD_DPS=y
+CONFIG_PLATFORM_EC_USB_PD_REV30=y
+CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=n
+CONFIG_PLATFORM_EC_USB_PD_USB4=n
+CONFIG_PLATFORM_EC_USB_PD_TCPC_LOW_POWER=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8805=y
+CONFIG_PLATFORM_EC_USB_PD_TCPC_RUNTIME_CONFIG=n
+CONFIG_PLATFORM_EC_USB_MUX_RUNTIME_CONFIG=n
+CONFIG_PLATFORM_EC_USB_PD_LOGGING=y
+CONFIG_PLATFORM_EC_CONFIG_USB_PD_3A_PORTS=2
+
+# USB ID
+# This is allocated specifically for Herobrine
+# http://google3/hardware/standards/usb/
+# TODO(b/183608112): Move to device tree
+CONFIG_PLATFORM_EC_USB_PID=0x5055
+
+# RTC
+CONFIG_PLATFORM_EC_RTC=y
+CONFIG_PLATFORM_EC_HOSTCMD_RTC=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_RTC=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_RTC_ALARM=y
+
+# EC software sync
+CONFIG_PLATFORM_EC_VBOOT_HASH=y
+
+# Sensors
+CONFIG_PLATFORM_EC_ACCEL_FIFO=y
+CONFIG_PLATFORM_EC_ACCEL_SPOOF_MODE=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=y
+CONFIG_PLATFORM_EC_GMR_TABLET_MODE=y
+CONFIG_PLATFORM_EC_LID_ANGLE=y
+CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y
+CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=y
+CONFIG_PLATFORM_EC_TABLET_MODE=y
+CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=y
+CONFIG_PLATFORM_EC_MAX_SENSOR_FREQ_MILLIHZ=100000
+
+# Sensor Drivers
+CONFIG_PLATFORM_EC_ACCEL_BMA255=y
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI260=y
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y
+
+CONFIG_SYSCON=y
+CONFIG_PLATFORM_EC_EMULATED_SYSRQ=y
diff --git a/zephyr/program/herobrine/src/board_chipset.c b/zephyr/program/herobrine/src/board_chipset.c
new file mode 100644
index 0000000000..c2269a0c7c
--- /dev/null
+++ b/zephyr/program/herobrine/src/board_chipset.c
@@ -0,0 +1,117 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Herobrine chipset-specific configuration */
+
+#include "battery.h"
+#include "board_chipset.h"
+#include "charger.h"
+#include "common.h"
+#include "console.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "timer.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+
+#define CPRINTS(format, args...) cprints(CC_HOOK, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_HOOK, format, ##args)
+
+/*
+ * A window of PD negotiation. It starts from the Type-C state reaching
+ * Attached.SNK, and ends when the PD contract is created. The VBUS may be
+ * raised anytime in this window.
+ *
+ * The current implementation is the worst case scenario: every message the PD
+ * negotiation is received at the last moment before timeout. More extra time
+ * is added to compensate the delay internally, like the decision of the DPM.
+ *
+ * TODO(waihong): Cancel this timer when the PD contract is negotiated.
+ */
+#define PD_READY_TIMEOUT                                                    \
+	(PD_T_SINK_WAIT_CAP + PD_T_SENDER_RESPONSE + PD_T_SINK_TRANSITION + \
+	 20 * MSEC)
+
+#define PD_READY_POLL_DELAY (10 * MSEC)
+
+static timestamp_t pd_ready_timeout;
+
+static bool pp5000_inited;
+
+__test_only void reset_pp5000_inited(void)
+{
+	pp5000_inited = false;
+}
+
+/* First boot, battery unattached, disconnected or low SOC */
+static void check_delay_5v(void)
+{
+	int soc = -1;
+
+	if (pp5000_inited)
+		return;
+
+	if (battery_get_disconnect_state() != BATTERY_NOT_DISCONNECTED) {
+		CPRINTS("Delay 5V due to battery disconnect");
+	} else if (battery_state_of_charge_abs(&soc) != EC_SUCCESS ||
+		   soc < charger_get_min_bat_pct_for_power_on()) {
+		CPRINTS("Delay 5V due to low battery");
+	} else {
+		return;
+	}
+
+	pd_ready_timeout = get_time();
+	pd_ready_timeout.val += PD_READY_TIMEOUT;
+}
+
+/* Called on USB PD connected */
+static void board_usb_pd_connect(void)
+{
+	check_delay_5v();
+}
+DECLARE_HOOK(HOOK_USB_PD_CONNECT, board_usb_pd_connect, HOOK_PRIO_DEFAULT);
+
+static void wait_pd_ready(void)
+{
+	CPRINTS("Wait PD negotiated VBUS transition %u",
+		pd_ready_timeout.le.lo);
+	while (pd_ready_timeout.val && get_time().val < pd_ready_timeout.val)
+		usleep(PD_READY_POLL_DELAY);
+}
+
+#define PPC_WAIT_5V_DELAY_MS 5
+
+/* Called on AP S5 -> S3 transition */
+static void board_chipset_pre_init(void)
+{
+	int port;
+
+	if (pp5000_inited)
+		return;
+
+	check_delay_5v();
+
+	if (pd_ready_timeout.val) {
+		wait_pd_ready();
+	}
+
+	CPRINTS("Enable 5V rail");
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pp5000_s5), 1);
+	pp5000_inited = true;
+
+	/*
+	 * Due to the delay of the 5V rail enabling until 5V@3A is
+	 * ready, the ppc_init may run when the PPC is not powered
+	 * yet. So here rerunning the ppc_init function after the 5V
+	 * rail enables to prevent Type-C port no function.
+	 */
+	msleep(PPC_WAIT_5V_DELAY_MS);
+	for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++) {
+		if (pd_get_task_cc_state(port) != PD_CC_NONE)
+			continue;
+		ppc_init(port);
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_PRE_INIT, board_chipset_pre_init, HOOK_PRIO_DEFAULT);
diff --git a/zephyr/program/herobrine/src/i2c.c b/zephyr/program/herobrine/src/i2c.c
new file mode 100644
index 0000000000..8cf2cfc232
--- /dev/null
+++ b/zephyr/program/herobrine/src/i2c.c
@@ -0,0 +1,17 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "i2c.h"
+#include "i2c/i2c.h"
+
+/* Herobrine-NPCX9 board specific i2c implementation */
+
+#ifdef CONFIG_PLATFORM_EC_I2C_PASSTHRU_RESTRICTED
+int board_allow_i2c_passthru(const struct i2c_cmd_desc_t *cmd_desc)
+{
+	return (i2c_get_device_for_port(cmd_desc->port) ==
+		i2c_get_device_for_port(I2C_PORT_VIRTUAL_BATTERY));
+}
+#endif
diff --git a/zephyr/program/herobrine/src/usb_pd_policy.c b/zephyr/program/herobrine/src/usb_pd_policy.c
new file mode 100644
index 0000000000..512bc489f3
--- /dev/null
+++ b/zephyr/program/herobrine/src/usb_pd_policy.c
@@ -0,0 +1,268 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "chipset.h"
+#include "console.h"
+#include "system.h"
+#include "usb_mux.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#include <zephyr/drivers/gpio.h>
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+int pd_check_vconn_swap(int port)
+{
+	/* In G3, do not allow vconn swap since PP5000 rail is off */
+	return gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pp5000_s5));
+}
+
+static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+static void board_vbus_update_source_current(int port)
+{
+	ppc_vbus_source_enable(port, vbus_en[port]);
+}
+
+void pd_power_supply_reset(int port)
+{
+	int prev_en;
+
+	prev_en = vbus_en[port];
+
+	/* Disable VBUS */
+	vbus_en[port] = 0;
+	board_vbus_update_source_current(port);
+
+	/* Enable discharge if we were previously sourcing 5V */
+	if (prev_en)
+		pd_set_vbus_discharge(port, 1);
+
+	/* notify host of power info change */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	/* Disable charging */
+	board_vbus_sink_enable(port, 0);
+
+	pd_set_vbus_discharge(port, 0);
+
+	/* Provide VBUS */
+	vbus_en[port] = 1;
+	board_vbus_update_source_current(port);
+
+	/* notify host of power info change */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS; /* we are ready */
+}
+
+int board_vbus_source_enabled(int port)
+{
+	return vbus_en[port];
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	return tcpm_check_vbus_level(port, VBUS_PRESENT);
+}
+
+/* ----------------- Vendor Defined Messages ------------------ */
+#ifdef CONFIG_USB_PD_ALT_MODE_DFP
+__override int svdm_dp_config(int port, uint32_t *payload)
+{
+	int opos = pd_alt_mode(port, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT);
+	uint8_t pin_mode = get_dp_pin_mode(port);
+
+	if (!pin_mode)
+		return 0;
+
+	/*
+	 * Defer setting the DP mux until HPD goes high, svdm_dp_attention().
+	 * The AP only supports one DP phy. An external DP mux switches between
+	 * the two ports. Should switch those muxes when it is really used,
+	 * i.e. HPD high; otherwise, the real use case is preempted, like:
+	 *  (1) plug a dongle without monitor connected to port-0,
+	 *  (2) plug a dongle without monitor connected to port-1,
+	 *  (3) plug a monitor to the port-1 dongle.
+	 */
+
+	payload[0] =
+		VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_CONFIG | VDO_OPOS(opos));
+	payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */
+				1, /* DPv1.3 signaling */
+				2); /* UFP connected */
+	return 2;
+};
+
+__override void svdm_dp_post_config(int port)
+{
+	/*
+	 * Connect the SBU lines in PPC chip such that the AUX termination
+	 * can be passed through.
+	 */
+	if (IS_ENABLED(CONFIG_USBC_PPC_SBU))
+		ppc_set_sbu(port, 1);
+
+	/*
+	 * Connect the USB SS/DP lines in TCPC chip.
+	 *
+	 * When mf_pref not true, still use the dock muxing
+	 * because of the board USB-C topology (limited to 2
+	 * lanes DP).
+	 */
+	usb_mux_set(port, USB_PD_MUX_DOCK, USB_SWITCH_CONNECT,
+		    polarity_rm_dts(pd_get_polarity(port)));
+
+	dp_flags[port] |= DP_FLAGS_DP_ON;
+	if (!(dp_flags[port] & DP_FLAGS_HPD_HI_PENDING))
+		return;
+
+	CPRINTS("C%d: Pending HPD. HPD->1", port);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_dp_hot_plug_det_r), 1);
+
+	/* set the minimum time delay (2ms) for the next HPD IRQ */
+	svdm_hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
+
+	usb_mux_hpd_update(port,
+			   USB_PD_MUX_HPD_LVL | USB_PD_MUX_HPD_IRQ_DEASSERTED);
+}
+
+/**
+ * Is the port fine to be muxed its DisplayPort lines?
+ *
+ * Only one port can be muxed to DisplayPort at a time.
+ *
+ * @param port	Port number of TCPC.
+ * @return	1 is fine; 0 is bad as other port is already muxed;
+ */
+static int is_dp_muxable(int port)
+{
+	/*
+	 * Check the DP port selection mux, positive either:
+	 *  - no port is muxed, OE_L deasserted, HIGH, or
+	 *  - already muxed to the same port.
+	 */
+	return gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_dp_mux_oe_l)) ||
+	       (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_dp_mux_sel)) ==
+		port);
+}
+
+__override int svdm_dp_attention(int port, uint32_t *payload)
+{
+	const struct gpio_dt_spec *hpd =
+		GPIO_DT_FROM_NODELABEL(gpio_dp_hot_plug_det_r);
+	int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]);
+	int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]);
+	int cur_lvl = gpio_pin_get_dt(hpd);
+	mux_state_t mux_state;
+
+	dp_status[port] = payload[1];
+
+	if (!is_dp_muxable(port)) {
+		/* TODO(waihong): Info user? */
+		CPRINTS("p%d: The other port is already muxed.", port);
+		return 0;
+	}
+
+	/*
+	 * Initial implementation to handle HPD. Only the first-plugged port
+	 * works, i.e. sending HPD signal to AP. The second-plugged port
+	 * will be ignored.
+	 *
+	 * TODO(waihong): Continue the above case, if the first-plugged port
+	 * is then unplugged, switch to the second-plugged port and signal AP?
+	 */
+	if (lvl) {
+		/*
+		 * Enable and switch the DP port selection mux to the
+		 * correct port.
+		 *
+		 * TODO(waihong): Better to move switching DP mux to
+		 * the usb_mux abstraction.
+		 */
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_dp_mux_sel),
+				port == 1);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_dp_mux_oe_l), 0);
+	} else {
+		/* Disconnect the DP port selection mux. */
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_dp_mux_oe_l), 1);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_dp_mux_sel), 0);
+	}
+
+	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && (irq || lvl))
+		/*
+		 * Wake up the AP.  IRQ or level high indicates a DP sink is now
+		 * present.
+		 */
+		pd_notify_dp_alt_mode_entry(port);
+
+	/* Its initial DP status message prior to config */
+	if (!(dp_flags[port] & DP_FLAGS_DP_ON)) {
+		if (lvl)
+			dp_flags[port] |= DP_FLAGS_HPD_HI_PENDING;
+		return 1;
+	}
+
+	/* Configure TCPC for the HPD event, for proper muxing */
+	mux_state = (lvl ? USB_PD_MUX_HPD_LVL : USB_PD_MUX_HPD_LVL_DEASSERTED) |
+		    (irq ? USB_PD_MUX_HPD_IRQ : USB_PD_MUX_HPD_IRQ_DEASSERTED);
+	usb_mux_hpd_update(port, mux_state);
+
+	/* Signal AP for the HPD event, through GPIO to AP */
+	if (irq & cur_lvl) {
+		uint64_t now = get_time().val;
+		/* Wait for the minimum spacing between IRQ_HPD if needed */
+		if (now < svdm_hpd_deadline[port])
+			usleep(svdm_hpd_deadline[port] - now);
+
+		/* Generate IRQ_HPD pulse */
+		CPRINTS("C%d: Recv IRQ. HPD->0", port);
+		gpio_pin_set_dt(hpd, 0);
+		usleep(HPD_DSTREAM_DEBOUNCE_IRQ);
+		gpio_pin_set_dt(hpd, 1);
+		CPRINTS("C%d: Recv IRQ. HPD->1", port);
+
+		/* Set the minimum time delay (2ms) for the next HPD IRQ */
+		svdm_hpd_deadline[port] =
+			get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
+	} else if (irq & !lvl) {
+		CPRINTF("ERR:HPD:IRQ&LOW\n");
+		return 0;
+	} else {
+		CPRINTS("C%d: Recv lvl. HPD->%d", port, lvl);
+		gpio_pin_set_dt(hpd, lvl);
+		/* Set the minimum time delay (2ms) for the next HPD IRQ */
+		svdm_hpd_deadline[port] =
+			get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
+	}
+
+	return 1;
+}
+
+__override void svdm_exit_dp_mode(int port)
+{
+	CPRINTS("%s(%d)", __func__, port);
+	dp_flags[port] = 0;
+	dp_status[port] = 0;
+	if (is_dp_muxable(port)) {
+		/* Disconnect the DP port selection mux. */
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_dp_mux_oe_l), 1);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_dp_mux_sel), 0);
+
+		/* Signal AP for the HPD low event */
+		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+		CPRINTS("C%d: DP exit. HPD->0", port);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_dp_hot_plug_det_r),
+				0);
+	}
+}
+#endif /* CONFIG_USB_PD_ALT_MODE_DFP */
diff --git a/zephyr/program/herobrine/src/usbc_config.c b/zephyr/program/herobrine/src/usbc_config.c
new file mode 100644
index 0000000000..5928d88d3d
--- /dev/null
+++ b/zephyr/program/herobrine/src/usbc_config.c
@@ -0,0 +1,250 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Herobrine board-specific USB-C configuration */
+
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "charger/isl923x_public.h"
+#include "common.h"
+#include "config.h"
+#include "cros_board_info.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "ppc/sn5s330_public.h"
+#include "ppc/syv682x_public.h"
+#include "system.h"
+#include "tcpm/ps8xxx_public.h"
+#include "tcpm/tcpci.h"
+#include "timer.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usbc/ppc.h"
+#include "usbc_ocp.h"
+#include "usbc_ppc.h"
+
+#include <zephyr/drivers/gpio.h>
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+#ifdef CONFIG_PLATFORM_EC_USBA
+static void usba_oc_deferred(void)
+{
+	/* Use next number after all USB-C ports to indicate the USB-A port */
+	board_overcurrent_event(
+		CONFIG_USB_PD_PORT_MAX_COUNT,
+		!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_a0_oc_odl)));
+}
+DECLARE_DEFERRED(usba_oc_deferred);
+
+void usba_oc_interrupt(enum gpio_signal signal)
+{
+	hook_call_deferred(&usba_oc_deferred_data, 0);
+}
+#endif
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_SWCTL_INT_ODL:
+		ppc_chips[0].drv->interrupt(0);
+		break;
+
+	case GPIO_USB_C1_SWCTL_INT_ODL:
+		ppc_chips[1].drv->interrupt(1);
+		break;
+
+	default:
+		break;
+	}
+}
+
+__overridable int board_charger_profile_override(struct charge_state_data *curr)
+{
+	return EC_SUCCESS;
+}
+
+int charger_profile_override(struct charge_state_data *curr)
+{
+	int usb_mv;
+	int port;
+
+	if (curr->state != ST_CHARGE)
+		return 0;
+
+	/* Lower the max requested voltage to 5V when battery is full. */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
+	    !(curr->batt.flags & BATT_FLAG_BAD_STATUS) &&
+	    !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
+	    (curr->batt.status & STATUS_FULLY_CHARGED))
+		usb_mv = 5000;
+	else
+		usb_mv = PD_MAX_VOLTAGE_MV;
+
+	if (pd_get_max_voltage() != usb_mv) {
+		CPRINTS("VBUS limited to %dmV", usb_mv);
+		for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++)
+			pd_set_external_voltage_limit(port, usb_mv);
+	}
+
+	board_charger_profile_override(curr);
+
+	return 0;
+}
+
+enum ec_status charger_profile_override_get_param(uint32_t param,
+						  uint32_t *value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+enum ec_status charger_profile_override_set_param(uint32_t param,
+						  uint32_t value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+#ifdef CONFIG_PLATFORM_EC_USBA
+/* Initialize board USC-C things */
+static void board_init_usbc(void)
+{
+	/* Enable USB-A overcurrent interrupt */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_a0_oc));
+}
+DECLARE_HOOK(HOOK_INIT, board_init_usbc, HOOK_PRIO_DEFAULT);
+#endif
+
+void board_tcpc_init(void)
+{
+	/* Only reset TCPC if not sysjump */
+	if (!system_jumped_late()) {
+		/* TODO(crosbug.com/p/61098): How long do we need to wait? */
+		board_reset_pd_mcu();
+	}
+
+	/* Enable PPC interrupts */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_swctl));
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_swctl));
+
+	/*
+	 * Initialize HPD to low; after sysjump SOC needs to see
+	 * HPD pulse to enable video path
+	 */
+	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
+		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_POST_I2C);
+
+void board_reset_pd_mcu(void)
+{
+	cprints(CC_USB, "Resetting TCPCs...");
+	cflush();
+
+	gpio_pin_set_dt(&tcpc_config[0].rst_gpio, 1);
+	gpio_pin_set_dt(&tcpc_config[1].rst_gpio, 1);
+	msleep(PS8XXX_RESET_DELAY_MS);
+	gpio_pin_set_dt(&tcpc_config[0].rst_gpio, 0);
+	gpio_pin_set_dt(&tcpc_config[1].rst_gpio, 0);
+	msleep(PS8805_FW_INIT_DELAY_MS);
+}
+
+void board_set_tcpc_power_mode(int port, int mode)
+{
+	/* Ignore the "mode" to turn the chip on.  We can only do a reset. */
+	if (mode)
+		return;
+
+	board_reset_pd_mcu();
+}
+
+int board_vbus_sink_enable(int port, int enable)
+{
+	/* Both ports are controlled by PPC SN5S330 */
+	return ppc_vbus_sink_enable(port, enable);
+}
+
+int board_is_sourcing_vbus(int port)
+{
+	/* Both ports are controlled by PPC SN5S330 */
+	return ppc_is_sourcing_vbus(port);
+}
+
+void board_overcurrent_event(int port, int is_overcurrented)
+{
+	/* TODO(b/120231371): Notify AP */
+	CPRINTS("p%d: overcurrent!", port);
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int i;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTS("Disabling all charging port");
+
+		/* Disable all ports. */
+		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (board_vbus_sink_enable(i, 0))
+				CPRINTS("Disabling p%d sink path failed.", i);
+		}
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (board_is_sourcing_vbus(port)) {
+		CPRINTS("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTS("New charge port: p%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		if (i == port)
+			continue;
+
+		if (board_vbus_sink_enable(i, 0))
+			CPRINTS("p%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (board_vbus_sink_enable(port, 1)) {
+		CPRINTS("p%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
+{
+	/*
+	 * Ignore lower charge ceiling on PD transition if our battery is
+	 * critical, as we may brownout.
+	 */
+	if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 &&
+	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
+		CPRINTS("Using max ilim %d", max_ma);
+		charge_ma = max_ma;
+	}
+
+	charge_set_input_current_limit(charge_ma, charge_mv);
+}
diff --git a/zephyr/program/herobrine/switchcap.dtsi b/zephyr/program/herobrine/switchcap.dtsi
new file mode 100644
index 0000000000..fb2db35d1a
--- /dev/null
+++ b/zephyr/program/herobrine/switchcap.dtsi
@@ -0,0 +1,12 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	switchcap {
+		compatible = "cros-ec,switchcap-gpio";
+		enable-pin = <&gpio_switchcap_on>;
+		power-good-pin = <&gpio_switchcap_pg>;
+	};
+};
diff --git a/zephyr/program/herobrine/usbc.dtsi b/zephyr/program/herobrine/usbc.dtsi
new file mode 100644
index 0000000000..bed94800dd
--- /dev/null
+++ b/zephyr/program/herobrine/usbc.dtsi
@@ -0,0 +1,42 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port0: port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+			bc12 = <&bc12_port0>;
+			ppc = <&ppc_port0>;
+			tcpc = <&tcpc_port0>;
+			chg = <&charger>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_mux_0>;
+			};
+		};
+		usb_mux_0: usb-mux-0 {
+			compatible = "parade,usbc-mux-ps8xxx";
+		};
+
+		port1: port1@1 {
+			compatible = "named-usbc-port";
+			reg = <1>;
+			bc12 = <&bc12_port1>;
+			ppc = <&ppc_port1>;
+			tcpc = <&tcpc_port1>;
+			usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_mux_1>;
+			};
+		};
+		usb_mux_1: usb-mux-1 {
+			compatible = "parade,usbc-mux-ps8xxx";
+		};
+	};
+};
diff --git a/zephyr/program/herobrine/villager/gpio.dtsi b/zephyr/program/herobrine/villager/gpio.dtsi
new file mode 100644
index 0000000000..bf124d8013
--- /dev/null
+++ b/zephyr/program/herobrine/villager/gpio.dtsi
@@ -0,0 +1,319 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	aliases {
+		gpio-wp = &gpio_ec_wp_odl;
+		gpio-kbd-kso2 = &gpio_ec_kso_02_inv;
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		gpio_usb_c0_pd_int_odl: usb_c0_pd_int_odl {
+			gpios = <&gpioe 0 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_USB_C0_PD_INT_ODL";
+		};
+		gpio_usb_c1_pd_int_odl: usb_c1_pd_int_odl {
+			gpios = <&gpiof 5 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_USB_C1_PD_INT_ODL";
+		};
+		gpio_usb_c0_swctl_int_odl: usb_c0_swctl_int_odl {
+			gpios = <&gpio0 3 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C0_SWCTL_INT_ODL";
+		};
+		gpio_usb_c1_swctl_int_odl: usb_c1_swctl_int_odl {
+			gpios = <&gpio4 0 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C1_SWCTL_INT_ODL";
+		};
+		gpio_usb_c0_bc12_int_l: usb_c0_bc12_int_l {
+			gpios = <&gpio6 1 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_usb_c1_bc12_int_l: usb_c1_bc12_int_l {
+			gpios = <&gpio8 2 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_usb_a0_oc_odl: usb_a0_oc_odl {
+			gpios = <&gpiof 4 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_chg_acok_od: chg_acok_od {
+			gpios = <&gpiod 2 GPIO_INPUT>;
+			enum-name = "GPIO_AC_PRESENT";
+		};
+		gpio_ec_pwr_btn_odl: ec_pwr_btn_odl {
+			gpios = <&gpio0 0 GPIO_INPUT>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		gpio_ec_voldn_btn_odl: ec_voldn_btn_odl {
+			gpios = <&gpio6 2 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_DOWN_L";
+		};
+		gpio_ec_volup_btn_odl: ec_volup_btn_odl {
+			gpios = <&gpioc 2 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_UP_L";
+		};
+		gpio_ec_wp_odl: ec_wp_odl {
+			gpios = <&gpiod 3 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_lid_open_ec: lid_open_ec {
+			gpios = <&gpio0 1 GPIO_INPUT>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+		gpio_ap_rst_l: ap_rst_l {
+			gpios = <&gpio5 1 GPIO_INPUT>;
+			enum-name = "GPIO_AP_RST_L";
+		};
+		gpio_ps_hold: ps_hold {
+			gpios = <&gpioa 6 GPIO_INPUT_PULL_DOWN>;
+			enum-name = "GPIO_PS_HOLD";
+		};
+		gpio_ap_suspend: ap_suspend {
+			gpios = <&gpio5 7 GPIO_INPUT>;
+			enum-name = "GPIO_AP_SUSPEND";
+		};
+		gpio_mb_power_good: mb_power_good {
+			gpios = <&gpio3 7 GPIO_INPUT_PULL_DOWN>;
+			enum-name = "GPIO_POWER_GOOD";
+		};
+		gpio_warm_reset_l: warm_reset_l {
+			gpios = <&gpiob 0 GPIO_INPUT>;
+			enum-name = "GPIO_WARM_RESET_L";
+		};
+		ap_ec_spi_cs_l {
+			gpios = <&gpio5 3 GPIO_INPUT_PULL_DOWN>;
+		};
+		gpio_tablet_mode_l: tablet_mode_l {
+			gpios = <&gpioc 6 GPIO_INPUT>;
+			enum-name = "GPIO_TABLET_MODE_L";
+		};
+		gpio_accel_gyro_int_l: accel_gyro_int_l {
+			gpios = <&gpioa 3 GPIO_INPUT>;
+		};
+		gpio_rtc_ec_wake_odl: rtc_ec_wake_odl {
+			gpios = <&gpio0 2 GPIO_INPUT>;
+		};
+		ec_entering_rw {
+			gpios = <&gpio7 2 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_ENTERING_RW";
+		};
+		ccd_mode_odl {
+			gpios = <&gpio6 3 GPIO_INPUT>;
+			enum-name = "GPIO_CCD_MODE_ODL";
+		};
+		ec_batt_pres_odl {
+			gpios = <&gpioe 5 GPIO_INPUT>;
+			enum-name = "GPIO_BATT_PRES_ODL";
+		};
+		ec_gsc_packet_mode {
+			gpios = <&gpio8 3 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_PACKET_MODE_EN";
+		};
+		pmic_resin_l {
+			gpios = <&gpioa 0 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_PMIC_RESIN_L";
+		};
+		pmic_kpd_pwr_odl {
+			gpios = <&gpioa 2 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_PMIC_KPD_PWR_ODL";
+		};
+		ap_ec_int_l {
+			gpios = <&gpio5 6 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_EC_INT_L";
+		};
+		gpio_switchcap_on: switchcap_on {
+			gpios = <&gpiod 5 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_SWITCHCAP_ON";
+		};
+		gpio_en_pp5000_s5: en_pp5000_s5 {
+			gpios = <&gpio7 3 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_EN_PP5000";
+		};
+		ec_bl_disable_l {
+			/* The PMIC controls backlight enable and this pin must
+			 * be HiZ for normal operation. The EC is allowed to
+			 * drive low to abruptly removes power from the eDP
+			 * panel in cases like lid close. So the signal is open
+			 * drain (allowed to drive low, never drive high).
+			 */
+			gpios = <&gpiob 6 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_ENABLE_BACKLIGHT";
+		};
+		lid_accel_int_l {
+			gpios = <&gpioa 1 GPIO_INPUT>;
+		};
+		tp_int_gate {
+			gpios = <&gpio7 4 GPIO_OUTPUT_LOW>;
+		};
+		gpio_usb_c0_pd_rst_l: usb_c0_pd_rst_l {
+			gpios = <&gpiof 1 (GPIO_OUTPUT_HIGH | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_usb_c1_pd_rst_l: usb_c1_pd_rst_l {
+			gpios = <&gpioe 4 (GPIO_OUTPUT_HIGH | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_dp_mux_oe_l: dp_mux_oe_l {
+			gpios = <&gpiob 1 GPIO_ODR_HIGH>;
+		};
+		gpio_dp_mux_sel: dp_mux_sel {
+			gpios = <&gpio4 5 GPIO_OUTPUT_LOW>;
+		};
+		gpio_dp_hot_plug_det_r: dp_hot_plug_det_r {
+			gpios = <&gpio9 5 GPIO_OUTPUT_LOW>;
+		};
+		gpio_en_usb_a_5v: en_usb_a_5v {
+			gpios = <&gpiof 0 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_EN_USB_A_5V";
+		};
+		usb_a_cdp_ilim_en_l {
+			gpios = <&gpio7 5 GPIO_OUTPUT_HIGH>;
+		};
+		gpio_usb_c0_frs_en: usb_c0_frs_en {
+			gpios = <&gpioc 5 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_USB_C0_FRS_EN";
+		};
+		gpio_usb_c1_frs_en: usb_c1_frs_en {
+			gpios = <&gpioc 1 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_USB_C1_FRS_EN";
+		};
+		gpio_ec_chg_led_y_c0: ec_chg_led_y_c0 {
+			gpios = <&gpio6 0 GPIO_OUTPUT_LOW>;
+		};
+		gpio_ec_chg_led_b_c0: ec_chg_led_b_c0 {
+			gpios = <&gpioc 0 GPIO_OUTPUT_LOW>;
+		};
+		ap_ec_spi_mosi {
+			gpios = <&gpio4 6 GPIO_INPUT_PULL_DOWN>;
+		};
+		ap_ec_spi_miso {
+			gpios = <&gpio4 7 GPIO_INPUT_PULL_DOWN>;
+		};
+		ap_ec_spi_clk {
+			gpios = <&gpio5 5 GPIO_INPUT_PULL_DOWN>;
+		};
+		gpio_brd_id0: brd_id0 {
+			gpios = <&gpio9 4 GPIO_INPUT>;
+			enum-name = "GPIO_BOARD_VERSION1";
+		};
+		gpio_brd_id1: brd_id1 {
+			gpios = <&gpio9 7 GPIO_INPUT>;
+			enum-name = "GPIO_BOARD_VERSION2";
+		};
+		gpio_brd_id2: brd_id2 {
+			gpios = <&gpioa 5 GPIO_INPUT>;
+			enum-name = "GPIO_BOARD_VERSION3";
+		};
+		gpio_sku_id0: sku_id0 {
+			gpios = <&gpio6 7 GPIO_INPUT>;
+		};
+		gpio_sku_id1: sku_id1 {
+			gpios = <&gpio7 0 GPIO_INPUT>;
+		};
+		gpio_sku_id2: sku_id2 {
+			gpios = <&gpioe 1 GPIO_INPUT>;
+		};
+		gpio_switchcap_pg: src_vph_pwr_pg {
+			gpios = <&gpioe 2 GPIO_INPUT_PULL_DOWN>;
+			enum-name = "GPIO_SWITCHCAP_PG";
+		};
+		arm_x86 {
+			gpios = <&gpio6 6 GPIO_OUTPUT_LOW>;
+		};
+		ec-i2c-sensor-scl {
+			gpios = <&gpiob 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		ec-i2c-sensor-sda {
+			gpios = <&gpiob 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		gpio_ec_kso_02_inv: ec_kso_02_inv {
+			gpios = <&gpio1 7 (GPIO_OUTPUT_LOW | GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_KBD_KSO2";
+		};
+	};
+
+	usba-port-enable-list {
+		compatible = "cros-ec,usba-port-enable-pins";
+		enable-pins = <&gpio_en_usb_a_5v>;
+	};
+
+	gpio_id_sku: sku {
+		compatible = "cros-ec,gpio-id";
+		bits  = <
+			&gpio_sku_id0
+			&gpio_sku_id1
+			&gpio_sku_id2
+		>;
+		system = "ternary";
+	};
+
+	gpio_id_board: board {
+		compatible = "cros-ec,gpio-id";
+		bits  = <
+			&gpio_brd_id0
+			&gpio_brd_id1
+			&gpio_brd_id2
+		>;
+		system = "ternary";
+	};
+
+	unused-pins {
+		compatible = "unused-gpios";
+		unused-gpios =
+			<&gpio5 2 0>,
+			<&gpio5 4 0>,
+			<&gpio7 6 0>,
+			<&gpiod 1 0>,
+			<&gpiod 0 0>,
+			<&gpioe 3 0>,
+			<&gpio0 4 0>,
+			<&gpiod 6 0>,
+			<&gpio3 2 0>,
+			<&gpio3 5 0>,
+			<&gpiod 7 0>,
+			<&gpio8 6 0>,
+			<&gpiod 4 0>,
+			<&gpio4 1 0>,
+			<&gpio3 4 0>,
+			<&gpioc 3 0>,
+			<&gpioc 4 0>,
+			<&gpioc 7 0>,
+			<&gpioa 4 0>,
+			<&gpio9 6 0>,
+			<&gpio9 3 0>,
+			<&gpioa 7 0>,
+			<&gpio5 0 0>,
+			<&gpio8 1 0>,
+			<&gpiob 7 0>;
+	};
+};
+
+/* Power switch logic input pads */
+&psl_in1_gpd2 {
+	/* ACOK_OD */
+	psl-in-mode = "edge";
+	psl-in-pol = "high-rising";
+};
+
+&psl_in2_gp00 {
+	/* EC_PWR_BTN_ODL */
+	psl-in-mode = "edge";
+	psl-in-pol = "low-falling";
+};
+
+&psl_in3_gp01 {
+	/* LID_OPEN_EC */
+	psl-in-mode = "edge";
+	psl-in-pol = "high-rising";
+};
+
+&psl_in4_gp02 {
+	/* RTC_EC_WAKE_ODL */
+	psl-in-mode = "edge";
+	psl-in-pol = "low-falling";
+};
+
+/* Power domain device controlled by PSL (Power Switch Logic) IO pads */
+&power_ctrl_psl {
+	status = "okay";
+	pinctrl-names = "sleep";
+	pinctrl-0 = <&psl_in1_gpd2 &psl_in2_gp00 &psl_in3_gp01 &psl_in4_gp02>;
+};
diff --git a/zephyr/program/herobrine/villager/led_pins.dtsi b/zephyr/program/herobrine/villager/led_pins.dtsi
new file mode 100644
index 0000000000..f171b6f656
--- /dev/null
+++ b/zephyr/program/herobrine/villager/led_pins.dtsi
@@ -0,0 +1,33 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	gpio-led-pins {
+		compatible = "cros-ec,gpio-led-pins";
+
+		battery_led: battery-led {
+			led-id = "EC_LED_ID_BATTERY_LED";
+			led-pins = <&gpio_ec_chg_led_y_c0
+				    &gpio_ec_chg_led_b_c0>;
+
+			color_off: color-off {
+				led-color = "LED_OFF";
+				led-values = <0 0>;
+			};
+
+			color_amber: color-amber {
+				led-color = "LED_AMBER";
+				br-color = "EC_LED_COLOR_AMBER";
+				led-values = <1 0>;
+			};
+
+			color_blue: color-blue {
+				led-color = "LED_BLUE";
+				br-color = "EC_LED_COLOR_BLUE";
+				led-values = <0 1>;
+			};
+		};
+	};
+};
diff --git a/zephyr/program/herobrine/villager/led_policy.dtsi b/zephyr/program/herobrine/villager/led_policy.dtsi
new file mode 100644
index 0000000000..ce9c5a27f3
--- /dev/null
+++ b/zephyr/program/herobrine/villager/led_policy.dtsi
@@ -0,0 +1,95 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	led-colors {
+		compatible = "cros-ec,led-policy";
+
+		power-state-charge {
+			charge-state = "LED_PWRS_CHARGE";
+
+			color-0 {
+				led-color = <&color_amber>;
+			};
+		};
+
+		power-state-discharge-s0 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S0";
+
+			color-0 {
+				led-color = <&color_blue>;
+			};
+		};
+
+		power-state-discharge-s3 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S3";
+
+			/* Amber 1 sec, off 3 sec */
+			color-0 {
+				led-color = <&color_amber>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <3000>;
+			};
+		};
+
+		power-state-discharge-s5 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S5";
+
+			color-0 {
+				led-color = <&color_off>;
+			};
+		};
+
+		power-state-error {
+			charge-state = "LED_PWRS_ERROR";
+
+			/* Amber 1 sec, off 1 sec */
+			color-0 {
+				led-color = <&color_amber>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <1000>;
+			};
+		};
+
+		power-state-near-full {
+			charge-state = "LED_PWRS_CHARGE_NEAR_FULL";
+
+			color-0 {
+				led-color = <&color_blue>;
+			};
+		};
+
+		power-state-forced-idle {
+			charge-state = "LED_PWRS_FORCED_IDLE";
+
+			/* Blue 2 sec, Amber 2 sec */
+			color-0 {
+				led-color = <&color_blue>;
+				period-ms = <2000>;
+			};
+			color-1 {
+				led-color = <&color_amber>;
+				period-ms = <2000>;
+			};
+		};
+
+		power-state-idle {
+			charge-state = "LED_PWRS_IDLE";
+
+			color-0 {
+				led-color = <&color_blue>;
+			};
+		};
+	};
+};
diff --git a/zephyr/program/herobrine/villager/motionsense.dtsi b/zephyr/program/herobrine/villager/motionsense.dtsi
new file mode 100644
index 0000000000..31d00e04a5
--- /dev/null
+++ b/zephyr/program/herobrine/villager/motionsense.dtsi
@@ -0,0 +1,148 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/motionsense/utils.h>
+
+
+/ {
+	aliases {
+		/*
+		 * motion sense's <>_INT_EVENT is handled
+		 * by alias. Using the alias, each driver creates
+		 * its own <>_INT_EVENT.
+		 */
+		bmi260-int = &base_accel;
+	};
+
+	/*
+	 * Declare mutexes used by sensor drivers.
+	 * A mutex node is used to create an instance of mutex_t.
+	 * A mutex node is referenced by a sensor node if the
+	 * corresponding sensor driver needs to use the
+	 * instance of the mutex.
+	 */
+	motionsense-mutex {
+		compatible = "cros-ec,motionsense-mutex";
+		lid_mutex: lid-mutex {
+		};
+
+		mutex_bmi260: bmi260-mutex {
+		};
+	};
+
+	/* Rotation matrix used by drivers. */
+	motionsense-rotation-ref {
+		compatible = "cros-ec,motionsense-rotation-ref";
+		lid_rot_ref: lid-rotation-ref {
+			mat33 = <0 1 0
+				 (-1) 0 0
+				 0 0 1>;
+		};
+
+		base_rot_ref: base-rotation-ref {
+			mat33 = <1 0 0
+				 0 (-1) 0
+				 0 0 (-1)>;
+		};
+	};
+
+	/*
+	 * Driver specific data. A driver-specific data can be shared with
+	 * different motion sensors while they are using the same driver.
+	 *
+	 * If a node's compatible starts with "cros-ec,accelgyro-", it is for
+	 * a common structure defined in accelgyro.h.
+	 * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for
+	 * "struct als_drv_data_t" in accelgyro.h
+	 */
+	motionsense-sensor-data {
+		kx022_data: kx022-drv-data {
+			compatible = "cros-ec,drvdata-kionix";
+			status = "okay";
+		};
+
+		bmi260_data: bmi260-drv-data {
+			compatible = "cros-ec,drvdata-bmi260";
+			status = "okay";
+		};
+	};
+
+	/*
+	 * List of motion sensors that creates motion_sensors array.
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
+	 * motion sensor IDs for lid angle calculation.
+	 */
+	motionsense-sensor {
+		lid_accel: lid-accel {
+			compatible = "cros-ec,kx022";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&lid_mutex>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&lid_rot_ref>;
+			default-range = <2>;
+			drv-data = <&kx022_data>;
+			i2c-spi-addr-flags = "KX022_ADDR0_FLAGS";
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_accel: base-accel {
+			compatible = "cros-ec,bmi260-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&mutex_bmi260>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&bmi260_data>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base-gyro {
+			compatible = "cros-ec,bmi260-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&mutex_bmi260>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&bmi260_data>;
+		};
+	};
+
+	motionsense-sensor-info {
+		compatible = "cros-ec,motionsense-sensor-info";
+
+		/*
+		 * list of GPIO interrupts that have to
+		 * be enabled at initial stage
+		 */
+		sensor-irqs = <&int_accel_gyro>;
+		/* list of sensors in force mode */
+		accel-force-mode-sensors = <&lid_accel>;
+	};
+};
diff --git a/zephyr/program/herobrine/villager/project.conf b/zephyr/program/herobrine/villager/project.conf
new file mode 100644
index 0000000000..59f909a0fa
--- /dev/null
+++ b/zephyr/program/herobrine/villager/project.conf
@@ -0,0 +1,14 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Villager board-specific Kconfig settings.
+CONFIG_BOARD_VILLAGER=y
+
+CONFIG_PLATFORM_EC_ACCEL_KX022=y
+
+# Set PCF85063A CAP_SEL
+CONFIG_PLATFORM_EC_PCF85063A_CAP_SEL=y
+
+#keyboard
+CONFIG_PLATFORM_EC_KEYBOARD_FACTORY_TEST=y
diff --git a/zephyr/program/herobrine/villager/project.overlay b/zephyr/program/herobrine/villager/project.overlay
new file mode 100644
index 0000000000..5351f442b0
--- /dev/null
+++ b/zephyr/program/herobrine/villager/project.overlay
@@ -0,0 +1,61 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Herobrine program common DTS includes */
+#include "../adc.dtsi"
+#include "../common.dtsi"
+#include "../i2c.dtsi"
+#include "../interrupts.dtsi"
+#include "../keyboard.dtsi"
+#include "../default_gpio_pinctrl.dtsi"
+#include "../switchcap.dtsi"
+#include "../usbc.dtsi"
+
+/* Villager project DTS includes*/
+#include "gpio.dtsi"
+#include "led_pins.dtsi"
+#include "led_policy.dtsi"
+#include "motionsense.dtsi"
+
+/* villager overrides follow... */
+/* battery overrides */
+/ {
+	batteries {
+		default_battery: ap19a5k {
+			compatible = "panasonic,ap19a5k", "battery-smart";
+		};
+		ap19a8k {
+			compatible = "lgc,ap19a8k", "battery-smart";
+		};
+	};
+};
+
+/* keyboard overrides */
+&cros_kb_raw {
+	status = "okay";
+	pinctrl-1 = <
+		&ksi0_gpio_gp31
+		&ksi1_gpio_gp30
+		&ksi2_gpio_gp27
+		&ksi3_gpio_gp26
+		&ksi4_gpio_gp25
+		&ksi5_gpio_gp24
+		&ksi6_gpio_gp23
+		&ksi7_gpio_gp22
+		&kso00_gpio_gp21
+		&kso01_gpio_gp20
+		&kso03_gpio_gp16
+		&kso04_gpio_gp15
+		&kso05_gpio_gp14
+		&kso06_gpio_gp13
+		&kso07_gpio_gp12
+		&kso08_gpio_gp11
+		&kso09_gpio_gp10
+		&kso10_gpio_gp07
+		&kso11_gpio_gp06
+		&kso12_gpio_gp05
+	>;
+	pinctrl-names = "default", "sleep";
+};
diff --git a/zephyr/program/herobrine/villager/src/keyboard.c b/zephyr/program/herobrine/villager/src/keyboard.c
new file mode 100644
index 0000000000..00cf98415e
--- /dev/null
+++ b/zephyr/program/herobrine/villager/src/keyboard.c
@@ -0,0 +1,22 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "keyboard_raw.h"
+#include "keyboard_scan.h"
+
+/*
+ * We have total 30 pins for keyboard connecter {-1, -1} mean
+ * the N/A pin that don't consider it and reserve index 0 area
+ * that we don't have pin 0.
+ */
+const int keyboard_factory_scan_pins[][2] = {
+	{ -1, -1 }, { 0, 5 },	{ 1, 1 },   { 1, 0 },	{ 0, 6 },   { 0, 7 },
+	{ -1, -1 }, { -1, -1 }, { 1, 4 },   { 1, 3 },	{ -1, -1 }, { 1, 6 },
+	{ 1, 7 },   { 3, 1 },	{ 2, 0 },   { 1, 5 },	{ 2, 6 },   { 2, 7 },
+	{ 2, 1 },   { 2, 4 },	{ 2, 5 },   { 1, 2 },	{ 2, 3 },   { 2, 2 },
+	{ 3, 0 },   { -1, -1 }, { -1, -1 }, { -1, -1 },
+};
+const int keyboard_factory_scan_pins_used =
+	ARRAY_SIZE(keyboard_factory_scan_pins);
diff --git a/zephyr/program/herobrine/zoglin/project.conf b/zephyr/program/herobrine/zoglin/project.conf
new file mode 100644
index 0000000000..7f96cf6c79
--- /dev/null
+++ b/zephyr/program/herobrine/zoglin/project.conf
@@ -0,0 +1,15 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Zoglin reference-board-specific Kconfig settings.
+CONFIG_BOARD_ZOGLIN=y
+CONFIG_PLATFORM_EC_ACCEL_BMA255=n
+CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y
+
+# Sensors
+CONFIG_PLATFORM_EC_ALS=y
+
+# Sensor Drivers
+CONFIG_PLATFORM_EC_ALS_TCS3400=y
+CONFIG_PLATFORM_EC_ALS_TCS3400_EMULATED_IRQ_EVENT=y
diff --git a/zephyr/program/herobrine/zoglin/project.overlay b/zephyr/program/herobrine/zoglin/project.overlay
new file mode 100644
index 0000000000..b631d4b490
--- /dev/null
+++ b/zephyr/program/herobrine/zoglin/project.overlay
@@ -0,0 +1,6 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "../hoglin/project.overlay"
diff --git a/zephyr/program/herobrine/zombie/gpio.dtsi b/zephyr/program/herobrine/zombie/gpio.dtsi
new file mode 100644
index 0000000000..8ec3a192b1
--- /dev/null
+++ b/zephyr/program/herobrine/zombie/gpio.dtsi
@@ -0,0 +1,318 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	aliases {
+		gpio-wp = &gpio_ec_wp_odl;
+		gpio-kbd-kso2 = &gpio_ec_kso_02_inv;
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		gpio_usb_c0_pd_int_odl: usb_c0_pd_int_odl {
+			gpios = <&gpioe 0 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_USB_C0_PD_INT_ODL";
+		};
+		gpio_usb_c1_pd_int_odl: usb_c1_pd_int_odl {
+			gpios = <&gpiof 5 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_USB_C1_PD_INT_ODL";
+		};
+		gpio_usb_c0_swctl_int_odl: usb_c0_swctl_int_odl {
+			gpios = <&gpio0 3 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C0_SWCTL_INT_ODL";
+		};
+		gpio_usb_c1_swctl_int_odl: usb_c1_swctl_int_odl {
+			gpios = <&gpio4 0 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C1_SWCTL_INT_ODL";
+		};
+		gpio_usb_c0_bc12_int_l: usb_c0_bc12_int_l {
+			gpios = <&gpio6 1 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_usb_c1_bc12_int_l: usb_c1_bc12_int_l {
+			gpios = <&gpio8 2 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_usb_a0_oc_odl: usb_a0_oc_odl {
+			gpios = <&gpiof 4 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_chg_acok_od: chg_acok_od {
+			gpios = <&gpiod 2 GPIO_INPUT>;
+			enum-name = "GPIO_AC_PRESENT";
+		};
+		gpio_ec_pwr_btn_odl: ec_pwr_btn_odl {
+			gpios = <&gpio0 0 GPIO_INPUT>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		gpio_ec_voldn_btn_odl: ec_voldn_btn_odl {
+			gpios = <&gpio6 2 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_DOWN_L";
+		};
+		gpio_ec_volup_btn_odl: ec_volup_btn_odl {
+			gpios = <&gpioc 2 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_UP_L";
+		};
+		gpio_ec_wp_odl: ec_wp_odl {
+			gpios = <&gpiod 3 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_lid_open_ec: lid_open_ec {
+			gpios = <&gpio0 1 GPIO_INPUT>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+		gpio_ap_rst_l: ap_rst_l {
+			gpios = <&gpio5 1 GPIO_INPUT>;
+			enum-name = "GPIO_AP_RST_L";
+		};
+		gpio_ps_hold: ps_hold {
+			gpios = <&gpioa 6 GPIO_INPUT_PULL_DOWN>;
+			enum-name = "GPIO_PS_HOLD";
+		};
+		gpio_ap_suspend: ap_suspend {
+			gpios = <&gpio5 7 GPIO_INPUT>;
+			enum-name = "GPIO_AP_SUSPEND";
+		};
+		gpio_mb_power_good: mb_power_good {
+			gpios = <&gpio3 7 GPIO_INPUT_PULL_DOWN>;
+			enum-name = "GPIO_POWER_GOOD";
+		};
+		gpio_warm_reset_l: warm_reset_l {
+			gpios = <&gpiob 0 GPIO_INPUT>;
+			enum-name = "GPIO_WARM_RESET_L";
+		};
+		ap_ec_spi_cs_l {
+			gpios = <&gpio5 3 GPIO_INPUT_PULL_DOWN>;
+		};
+		gpio_tablet_mode_l: tablet_mode_l {
+			gpios = <&gpioc 6 GPIO_INPUT>;
+			enum-name = "GPIO_TABLET_MODE_L";
+		};
+		gpio_accel_gyro_int_l: accel_gyro_int_l {
+			gpios = <&gpioa 3 GPIO_INPUT>;
+		};
+		gpio_rtc_ec_wake_odl: rtc_ec_wake_odl {
+			gpios = <&gpio0 2 GPIO_INPUT>;
+		};
+		ec_entering_rw {
+			gpios = <&gpio7 2 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_ENTERING_RW";
+		};
+		ccd_mode_odl {
+			gpios = <&gpio6 3 GPIO_INPUT>;
+			enum-name = "GPIO_CCD_MODE_ODL";
+		};
+		ec_batt_pres_odl {
+			gpios = <&gpioe 5 GPIO_INPUT>;
+			enum-name = "GPIO_BATT_PRES_ODL";
+		};
+		ec_gsc_packet_mode {
+			gpios = <&gpio8 3 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_PACKET_MODE_EN";
+		};
+		pmic_resin_l {
+			gpios = <&gpioa 0 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_PMIC_RESIN_L";
+		};
+		pmic_kpd_pwr_odl {
+			gpios = <&gpioa 2 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_PMIC_KPD_PWR_ODL";
+		};
+		ap_ec_int_l {
+			gpios = <&gpio5 6 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_EC_INT_L";
+		};
+		gpio_switchcap_on: switchcap_on {
+			gpios = <&gpiod 5 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_SWITCHCAP_ON";
+		};
+		gpio_en_pp5000_s5: en_pp5000_s5 {
+			gpios = <&gpio7 3 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_EN_PP5000";
+		};
+		ec_bl_disable_l {
+			/* The PMIC controls backlight enable and this pin must
+			 * be HiZ for normal operation. The EC is allowed to
+			 * drive low to abruptly removes power from the eDP
+			 * panel in cases like lid close. So the signal is open
+			 * drain (allowed to drive low, never drive high).
+			 */
+			gpios = <&gpiob 6 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_ENABLE_BACKLIGHT";
+		};
+		lid_accel_int_l {
+			gpios = <&gpioa 1 GPIO_INPUT>;
+		};
+		tp_int_gate {
+			gpios = <&gpio7 4 GPIO_OUTPUT_LOW>;
+		};
+		gpio_usb_c0_pd_rst_l: usb_c0_pd_rst_l {
+			gpios = <&gpiof 1 (GPIO_OUTPUT_HIGH | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_usb_c1_pd_rst_l: usb_c1_pd_rst_l {
+			gpios = <&gpioe 4 (GPIO_OUTPUT_HIGH | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_dp_mux_oe_l: dp_mux_oe_l {
+			gpios = <&gpiob 1 GPIO_ODR_HIGH>;
+		};
+		gpio_dp_mux_sel: dp_mux_sel {
+			gpios = <&gpio4 5 GPIO_OUTPUT_LOW>;
+		};
+		gpio_dp_hot_plug_det_r: dp_hot_plug_det_r {
+			gpios = <&gpio9 5 GPIO_OUTPUT_LOW>;
+		};
+		gpio_en_usb_a_5v: en_usb_a_5v {
+			gpios = <&gpiof 0 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_EN_USB_A_5V";
+		};
+		usb_a_cdp_ilim_en_l {
+			gpios = <&gpio7 5 GPIO_OUTPUT_HIGH>;
+		};
+		gpio_usb_c0_frs_en: usb_c0_frs_en {
+			gpios = <&gpioc 5 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_USB_C0_FRS_EN";
+		};
+		gpio_usb_c1_frs_en: usb_c1_frs_en {
+			gpios = <&gpioc 1 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_USB_C1_FRS_EN";
+		};
+		gpio_ec_chg_led_y_c0: ec_chg_led_y_c0 {
+			gpios = <&gpio6 0 GPIO_OUTPUT_LOW>;
+		};
+		gpio_ec_chg_led_b_c0: ec_chg_led_b_c0 {
+			gpios = <&gpioc 0 GPIO_OUTPUT_LOW>;
+		};
+		ap_ec_spi_mosi {
+			gpios = <&gpio4 6 GPIO_INPUT_PULL_DOWN>;
+		};
+		ap_ec_spi_miso {
+			gpios = <&gpio4 7 GPIO_INPUT_PULL_DOWN>;
+		};
+		ap_ec_spi_clk {
+			gpios = <&gpio5 5 GPIO_INPUT_PULL_DOWN>;
+		};
+		gpio_brd_id0: brd_id0 {
+			gpios = <&gpio9 4 GPIO_INPUT>;
+			enum-name = "GPIO_BOARD_VERSION1";
+		};
+		gpio_brd_id1: brd_id1 {
+			gpios = <&gpio9 7 GPIO_INPUT>;
+			enum-name = "GPIO_BOARD_VERSION2";
+		};
+		gpio_brd_id2: brd_id2 {
+			gpios = <&gpioa 5 GPIO_INPUT>;
+			enum-name = "GPIO_BOARD_VERSION3";
+		};
+		gpio_sku_id0: sku_id0 {
+			gpios = <&gpio6 7 GPIO_INPUT>;
+		};
+		gpio_sku_id1: sku_id1 {
+			gpios = <&gpio7 0 GPIO_INPUT>;
+		};
+		gpio_sku_id2: sku_id2 {
+			gpios = <&gpioe 1 GPIO_INPUT>;
+		};
+		gpio_switchcap_pg: src_vph_pwr_pg {
+			gpios = <&gpioe 2 GPIO_INPUT_PULL_DOWN>;
+			enum-name = "GPIO_SWITCHCAP_PG";
+		};
+		arm_x86 {
+			gpios = <&gpio6 6 GPIO_OUTPUT_LOW>;
+		};
+		ec-i2c-sensor-scl {
+			gpios = <&gpiob 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		ec-i2c-sensor-sda {
+			gpios = <&gpiob 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		gpio_ec_kso_02_inv: ec_kso_02_inv {
+			gpios = <&gpio1 7 (GPIO_OUTPUT_LOW | GPIO_ACTIVE_LOW)>;
+		};
+	};
+
+	usba-port-enable-list {
+		compatible = "cros-ec,usba-port-enable-pins";
+		enable-pins = <&gpio_en_usb_a_5v>;
+	};
+
+	gpio_id_sku: sku {
+		compatible = "cros-ec,gpio-id";
+		bits  = <
+			&gpio_sku_id0
+			&gpio_sku_id1
+			&gpio_sku_id2
+		>;
+		system = "ternary";
+	};
+
+	gpio_id_board: board {
+		compatible = "cros-ec,gpio-id";
+		bits  = <
+			&gpio_brd_id0
+			&gpio_brd_id1
+			&gpio_brd_id2
+		>;
+		system = "ternary";
+	};
+
+	unused-pins {
+		compatible = "unused-gpios";
+		unused-gpios =
+			<&gpio5 2 0>,
+			<&gpio5 4 0>,
+			<&gpio7 6 0>,
+			<&gpiod 1 0>,
+			<&gpiod 0 0>,
+			<&gpioe 3 0>,
+			<&gpio0 4 0>,
+			<&gpiod 6 0>,
+			<&gpio3 2 0>,
+			<&gpio3 5 0>,
+			<&gpiod 7 0>,
+			<&gpio8 6 0>,
+			<&gpiod 4 0>,
+			<&gpio4 1 0>,
+			<&gpio3 4 0>,
+			<&gpioc 3 0>,
+			<&gpioc 4 0>,
+			<&gpioc 7 0>,
+			<&gpioa 4 0>,
+			<&gpio9 6 0>,
+			<&gpio9 3 0>,
+			<&gpioa 7 0>,
+			<&gpio5 0 0>,
+			<&gpio8 1 0>,
+			<&gpiob 7 0>;
+	};
+};
+
+/* Power switch logic input pads */
+&psl_in1_gpd2 {
+	/* ACOK_OD */
+	psl-in-mode = "edge";
+	psl-in-pol = "high-rising";
+};
+
+&psl_in2_gp00 {
+	/* EC_PWR_BTN_ODL */
+	psl-in-mode = "edge";
+	psl-in-pol = "low-falling";
+};
+
+&psl_in3_gp01 {
+	/* LID_OPEN_EC */
+	psl-in-mode = "edge";
+	psl-in-pol = "high-rising";
+};
+
+&psl_in4_gp02 {
+	/* RTC_EC_WAKE_ODL */
+	psl-in-mode = "edge";
+	psl-in-pol = "low-falling";
+};
+
+/* Power domain device controlled by PSL (Power Switch Logic) IO pads */
+&power_ctrl_psl {
+	status = "okay";
+	pinctrl-names = "sleep";
+	pinctrl-0 = <&psl_in1_gpd2 &psl_in2_gp00 &psl_in3_gp01 &psl_in4_gp02>;
+};
diff --git a/zephyr/program/herobrine/zombie/led_pins.dtsi b/zephyr/program/herobrine/zombie/led_pins.dtsi
new file mode 100644
index 0000000000..f171b6f656
--- /dev/null
+++ b/zephyr/program/herobrine/zombie/led_pins.dtsi
@@ -0,0 +1,33 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	gpio-led-pins {
+		compatible = "cros-ec,gpio-led-pins";
+
+		battery_led: battery-led {
+			led-id = "EC_LED_ID_BATTERY_LED";
+			led-pins = <&gpio_ec_chg_led_y_c0
+				    &gpio_ec_chg_led_b_c0>;
+
+			color_off: color-off {
+				led-color = "LED_OFF";
+				led-values = <0 0>;
+			};
+
+			color_amber: color-amber {
+				led-color = "LED_AMBER";
+				br-color = "EC_LED_COLOR_AMBER";
+				led-values = <1 0>;
+			};
+
+			color_blue: color-blue {
+				led-color = "LED_BLUE";
+				br-color = "EC_LED_COLOR_BLUE";
+				led-values = <0 1>;
+			};
+		};
+	};
+};
diff --git a/zephyr/program/herobrine/zombie/led_policy.dtsi b/zephyr/program/herobrine/zombie/led_policy.dtsi
new file mode 100644
index 0000000000..ce9c5a27f3
--- /dev/null
+++ b/zephyr/program/herobrine/zombie/led_policy.dtsi
@@ -0,0 +1,95 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	led-colors {
+		compatible = "cros-ec,led-policy";
+
+		power-state-charge {
+			charge-state = "LED_PWRS_CHARGE";
+
+			color-0 {
+				led-color = <&color_amber>;
+			};
+		};
+
+		power-state-discharge-s0 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S0";
+
+			color-0 {
+				led-color = <&color_blue>;
+			};
+		};
+
+		power-state-discharge-s3 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S3";
+
+			/* Amber 1 sec, off 3 sec */
+			color-0 {
+				led-color = <&color_amber>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <3000>;
+			};
+		};
+
+		power-state-discharge-s5 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S5";
+
+			color-0 {
+				led-color = <&color_off>;
+			};
+		};
+
+		power-state-error {
+			charge-state = "LED_PWRS_ERROR";
+
+			/* Amber 1 sec, off 1 sec */
+			color-0 {
+				led-color = <&color_amber>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <1000>;
+			};
+		};
+
+		power-state-near-full {
+			charge-state = "LED_PWRS_CHARGE_NEAR_FULL";
+
+			color-0 {
+				led-color = <&color_blue>;
+			};
+		};
+
+		power-state-forced-idle {
+			charge-state = "LED_PWRS_FORCED_IDLE";
+
+			/* Blue 2 sec, Amber 2 sec */
+			color-0 {
+				led-color = <&color_blue>;
+				period-ms = <2000>;
+			};
+			color-1 {
+				led-color = <&color_amber>;
+				period-ms = <2000>;
+			};
+		};
+
+		power-state-idle {
+			charge-state = "LED_PWRS_IDLE";
+
+			color-0 {
+				led-color = <&color_blue>;
+			};
+		};
+	};
+};
diff --git a/zephyr/program/herobrine/zombie/project.conf b/zephyr/program/herobrine/zombie/project.conf
new file mode 100644
index 0000000000..e2065b6d15
--- /dev/null
+++ b/zephyr/program/herobrine/zombie/project.conf
@@ -0,0 +1,28 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Zombie board-specific Kconfig settings.
+CONFIG_BOARD_ZOMBIE=y
+
+# Disable system unlock (b/249401128)
+CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=n
+
+# Sensors
+CONFIG_PLATFORM_EC_MOTIONSENSE=n
+CONFIG_PLATFORM_EC_ACCEL_FIFO=n
+CONFIG_PLATFORM_EC_ACCEL_SPOOF_MODE=n
+CONFIG_PLATFORM_EC_GMR_TABLET_MODE=n
+CONFIG_PLATFORM_EC_LID_ANGLE=n
+CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=n
+CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=n
+CONFIG_PLATFORM_EC_TABLET_MODE=n
+CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=n
+
+# Sensor Drivers
+CONFIG_PLATFORM_EC_ACCEL_BMA255=n
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI260=n
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=n
+
+# Set PCF85063A CAP_SEL
+CONFIG_PLATFORM_EC_PCF85063A_CAP_SEL=y
diff --git a/zephyr/program/herobrine/zombie/project.overlay b/zephyr/program/herobrine/zombie/project.overlay
new file mode 100644
index 0000000000..f07bccd3e6
--- /dev/null
+++ b/zephyr/program/herobrine/zombie/project.overlay
@@ -0,0 +1,40 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* zombie program common DTS includes */
+#include "../adc.dtsi"
+#include "../common.dtsi"
+#include "../default_gpio_pinctrl.dtsi"
+#include "../i2c.dtsi"
+#include "../interrupts.dtsi"
+#include "../keyboard.dtsi"
+#include "../switchcap.dtsi"
+#include "../usbc.dtsi"
+
+/* Zombie project DTS includes*/
+#include "gpio.dtsi"
+#include "led_pins.dtsi"
+#include "led_policy.dtsi"
+
+/* zombie overrides follow... */
+/* battery overrides */
+/ {
+	batteries {
+		default_battery: sg20 {
+			compatible = "ganfeng,sg20", "battery-smart";
+		};
+		sg20qt1c {
+			compatible = "pow-tech,sg20qt1c", "battery-smart";
+		};
+	};
+};
+
+/* interrupt overrides */
+/ {
+	gpio-interrupts {
+		/delete-node/ accel_gyro;
+		/delete-node/ tablet_mode;
+	};
+};
diff --git a/zephyr/program/intelrvp/BUILD.py b/zephyr/program/intelrvp/BUILD.py
new file mode 100644
index 0000000000..32a2eb5e97
--- /dev/null
+++ b/zephyr/program/intelrvp/BUILD.py
@@ -0,0 +1,120 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Define zmake projects for intelrvp."""
+
+# intelrvp has adlrvp_npcx, adlrvpp_ite, adlrvpp_mchp etc
+
+
+def register_intelrvp_project(
+    project_name,
+    chip="npcx9m3f",
+    extra_dts_overlays=(),
+    extra_kconfig_files=(),
+):
+    """Register a variant of intelrvp."""
+    register_func = register_binman_project
+    if chip.startswith("mec1727"):
+        register_func = register_mchp_project
+    elif chip.startswith("npcx"):
+        register_func = register_npcx_project
+
+    kconfig_files = [here / "prj.conf"]
+    dts_overlays = []
+    if project_name.startswith("adlrvp"):
+        kconfig_files.append(here / "adlrvp/prj.conf")
+        dts_overlays.append(here / "adlrvp/battery.dts")
+        dts_overlays.append(here / "adlrvp/ioex.dts")
+    if project_name.startswith("mtlrvp"):
+        kconfig_files.append(here / "mtlrvp/prj.conf")
+        dts_overlays.append(here / "adlrvp/battery.dts")
+    kconfig_files.extend(extra_kconfig_files)
+    dts_overlays.extend(extra_dts_overlays)
+
+    register_func(
+        project_name=project_name,
+        zephyr_board=chip,
+        dts_overlays=dts_overlays,
+        kconfig_files=kconfig_files,
+        inherited_from=["intelrvp"],
+    )
+
+
+register_intelrvp_project(
+    project_name="adlrvp_mchp",
+    chip="mec1727",
+    extra_dts_overlays=[
+        here / "adlrvp/adlrvp_mchp/adlrvp_mchp.dts",
+        here / "adlrvp/adlrvp_mchp/gpio.dts",
+        here / "adlrvp/adlrvp_mchp/interrupts.dts",
+        here / "adlrvp/adlrvp_mchp/keyboard.dts",
+        here / "adlrvp/adlrvp_mchp/usbc.dts",
+    ],
+    extra_kconfig_files=[
+        here / "legacy_ec_pwrseq.conf",
+        here / "adlrvp/adlrvp_mchp/prj.conf",
+    ],
+)
+
+
+register_intelrvp_project(
+    project_name="adlrvp_npcx",
+    chip="npcx9m7f",
+    extra_dts_overlays=[
+        here / "adlrvp/adlrvp_npcx/adlrvp_npcx.dts",
+        here / "adlrvp/adlrvp_npcx/fan.dts",
+        here / "adlrvp/adlrvp_npcx/gpio.dts",
+        here / "adlrvp/adlrvp_npcx/interrupts.dts",
+        here / "adlrvp/adlrvp_npcx/keyboard.dts",
+        here / "adlrvp/adlrvp_npcx/temp_sensor.dts",
+        here / "adlrvp/adlrvp_npcx/usbc.dts",
+        here / "adlrvp/adlrvp_npcx/pwm_leds.dts",
+    ],
+    extra_kconfig_files=[
+        here / "legacy_ec_pwrseq.conf",
+        here / "adlrvp/adlrvp_npcx/prj.conf",
+    ],
+)
+
+
+register_intelrvp_project(
+    project_name="mtlrvpp_mchp",
+    chip="mec1727",
+    extra_dts_overlays=[
+        here / "mtlrvp/mtlrvpp_mchp/fan.dts",
+        here / "mtlrvp/mtlrvpp_mchp/gpio.dts",
+        here / "mtlrvp/mtlrvpp_mchp/keyboard.dts",
+        here / "mtlrvp/mtlrvpp_npcx/interrupts.dts",
+        here / "mtlrvp/ioex.dts",
+        here / "mtlrvp/mtlrvpp_mchp/mtlrvp_mchp.dts",
+        here / "mtlrvp/mtlrvpp_mchp/mtlrvp_mchp_power_signals.dts",
+        here / "adlrvp/adlrvp_npcx/temp_sensor.dts",
+        here / "mtlrvp/usbc.dts",
+    ],
+    extra_kconfig_files=[
+        here / "zephyr_ap_pwrseq.conf",
+        here / "mtlrvp/mtlrvpp_mchp/prj.conf",
+    ],
+)
+
+
+register_intelrvp_project(
+    project_name="mtlrvpp_npcx",
+    chip="npcx9m3f",
+    extra_dts_overlays=[
+        here / "mtlrvp/mtlrvpp_npcx/fan.dts",
+        here / "mtlrvp/mtlrvpp_npcx/gpio.dts",
+        here / "mtlrvp/mtlrvpp_npcx/keyboard.dts",
+        here / "mtlrvp/mtlrvpp_npcx/interrupts.dts",
+        here / "mtlrvp/ioex.dts",
+        here / "mtlrvp/mtlrvpp_npcx/mtlrvp_npcx.dts",
+        here / "mtlrvp/mtlrvpp_npcx/mtlrvp_npcx_power_signals.dts",
+        here / "adlrvp/adlrvp_npcx/temp_sensor.dts",
+        here / "mtlrvp/usbc.dts",
+    ],
+    extra_kconfig_files=[
+        here / "zephyr_ap_pwrseq.conf",
+        here / "mtlrvp/mtlrvpp_npcx/prj.conf",
+    ],
+)
diff --git a/zephyr/program/intelrvp/CMakeLists.txt b/zephyr/program/intelrvp/CMakeLists.txt
new file mode 100644
index 0000000000..077e14fa1a
--- /dev/null
+++ b/zephyr/program/intelrvp/CMakeLists.txt
@@ -0,0 +1,32 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(intelrvp)
+
+cros_ec_library_include_directories(include)
+cros_ec_library_include_directories("${PLATFORM_EC}/driver/charger")
+cros_ec_library_include_directories("${PLATFORM_EC}/driver/ppc")
+cros_ec_library_include_directories("${PLATFORM_EC}/driver/tcpm")
+cros_ec_library_include_directories("${PLATFORM_EC}/driver/usb_mux")
+zephyr_library_sources("src/intel_rvp_board_id.c")
+
+if((DEFINED CONFIG_BOARD_ADLRVP_MCHP) OR (DEFINED CONFIG_BOARD_ADLRVP_NPCX))
+  add_subdirectory(adlrvp)
+  zephyr_library_sources("src/intelrvp.c")
+  zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "${PLATFORM_EC}/baseboard/intelrvp/usb_pd_policy_mecc_1_0.c")
+  zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "${PLATFORM_EC}/baseboard/intelrvp/chg_usb_pd_mecc_1_0.c")
+  zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "${PLATFORM_EC}/baseboard/intelrvp/chg_usb_pd.c")
+  zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LED_PWM "src/intel_rvp_led.c")
+endif()
+
+if((DEFINED CONFIG_BOARD_MTLRVP_MCHP) OR (DEFINED CONFIG_BOARD_MTLRVP_NPCX))
+  add_subdirectory(mtlrvp)
+  zephyr_library_sources("src/intelrvp.c")
+  zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/usb_pd_policy_mecc_1_1.c")
+  zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/chg_usb_pd_mecc_1_1.c")
+  zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/chg_usb_pd.c")
+endif()
diff --git a/zephyr/program/intelrvp/Kconfig b/zephyr/program/intelrvp/Kconfig
new file mode 100644
index 0000000000..9a7ec165c7
--- /dev/null
+++ b/zephyr/program/intelrvp/Kconfig
@@ -0,0 +1,33 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config BOARD_ADLRVP_MCHP
+	bool "Intel ADLRVP_MCHP board"
+	depends on SOC_MEC172X_NSZ
+	help
+	  Build Intel ADLRVP_MCHP reference board. This board has Intel ADL RVP
+	  SoC with MEC1727 EC.
+
+config BOARD_ADLRVP_NPCX
+	bool "Intel ADLRVP_NPCX board"
+	depends on SOC_NPCX9M7F
+	help
+	  Build Intel ADLRVP_NPCX reference board. This board has Intel ADL RVP
+	  SoC with NPCX9M37F EC.
+
+config BOARD_MTLRVP_MCHP
+	bool "Intel MTLRVP_MCHP board"
+	depends on SOC_MEC172X_NSZ
+	help
+	  Build Intel MTLRVP_MCHP reference board. This board has Intel MTL RVP
+	  SoC with MEC1727 EC
+
+config BOARD_MTLRVP_NPCX
+	bool "Intel MTLRVP_NPCX board"
+	depends on SOC_NPCX9M3F
+	help
+	  Build Intel MTLRVP_NPCX reference board. This board is Intel MTL RVP
+	  SOC with NPCX_NPCX9M3F
+
+source "Kconfig.zephyr"
diff --git a/zephyr/program/intelrvp/adlrvp/CMakeLists.txt b/zephyr/program/intelrvp/adlrvp/CMakeLists.txt
new file mode 100644
index 0000000000..71dee29552
--- /dev/null
+++ b/zephyr/program/intelrvp/adlrvp/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cros_ec_library_include_directories("include")
+zephyr_library_sources("src/adlrvp.c")
diff --git a/zephyr/program/intelrvp/adlrvp/adlrvp_mchp/adlrvp_mchp.dts b/zephyr/program/intelrvp/adlrvp/adlrvp_mchp/adlrvp_mchp.dts
new file mode 100644
index 0000000000..6603ba2309
--- /dev/null
+++ b/zephyr/program/intelrvp/adlrvp/adlrvp_mchp/adlrvp_mchp.dts
@@ -0,0 +1,228 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	hibernate-wake-pins {
+		compatible = "cros-ec,hibernate-wake-pins";
+		wakeup-irqs = <
+			&int_ac_present
+			&int_lid_open
+			&int_power_button
+		>;
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		i2c_charger: charger {
+			i2c-port = <&i2c_smb_0>;
+			enum-names = "I2C_PORT_BATTERY",
+				"I2C_PORT_CHARGER",
+				"I2C_PORT_EEPROM",
+				"I2C_PORT_PORT80";
+		};
+		typec_0: typec-0 {
+			i2c-port = <&i2c_smb_1>;
+			enum-names = "I2C_PORT_TYPEC_0";
+		};
+		typec_1: typec-1 {
+			i2c-port = <&i2c_smb_2>;
+			enum-names = "I2C_PORT_TYPEC_1";
+		};
+		typec_2: typec-2 {
+			i2c-port = <&i2c_smb_3>;
+			enum-names = "I2C_PORT_TYPEC_2";
+		};
+		typec_3: typec-3 {
+			i2c-port = <&i2c_smb_4>;
+			enum-names = "I2C_PORT_TYPEC_3";
+		};
+	};
+};
+
+/* charger */
+&i2c_smb_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	port_sel = <0>;
+	pinctrl-0 = <&i2c00_scl_gpio004 &i2c00_sda_gpio003>;
+	pinctrl-names = "default";
+
+	pca95xx: pca95xx@22 {
+		compatible = "nxp,pca95xx";
+		label = "PCA95XX";
+		reg = <0x22>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <16>;
+	};
+
+	rvp_board_id: rvp-board-id {
+		compatible = "intel,rvp-board-id";
+
+		/*
+		 * BOM ID [2]   : IOEX[0]
+		 * BOM ID [1:0] : IOEX[15:14]
+		 */
+		bom-gpios = <&pca95xx 0 0>, <&pca95xx 15 0>, <&pca95xx 14 0>;
+
+		/*
+		 * FAB ID [1:0] : IOEX[2:1]
+		 */
+		fab-gpios = <&pca95xx 2 0>, <&pca95xx 1 0>;
+
+		/*
+		 * BOARD ID[5:0] : IOEX[13:8]
+		 */
+		board-gpios = <&pca95xx 13 0>, <&pca95xx 12 0>, <&pca95xx 11 0>,
+			      <&pca95xx 10 0>, <&pca95xx 9 0>, <&pca95xx 8 0>;
+	};
+
+	max695x@38 {
+		compatible = "maxim,max695x";
+		reg = <0x38>;
+	};
+
+	charger: isl9241@9 {
+		compatible = "intersil,isl9241";
+		status = "okay";
+		reg = <0x9>;
+	};
+
+	cbi_eeprom: eeprom@50 {
+		compatible = "atmel,at24";
+		reg = <0x50>;
+		size = <2048>;
+		pagesize = <16>;
+		address-width = <8>;
+		timeout = <5>;
+	};
+};
+
+/* typec_0 */
+&i2c_smb_1 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	port_sel = <6>;
+	pinctrl-0 = <&i2c06_scl_gpio140 &i2c06_sda_gpio132>;
+	pinctrl-names = "default";
+
+	tcpc_port0: fusb302@22 {
+		compatible = "fairchild,fusb302";
+		reg = <0x22>;
+		int-pin = <&usbc_tcpc_alrt_p0>;
+	};
+
+	ppc_port0: sn5s330@40 {
+		compatible = "ti,sn5s330";
+		status = "okay";
+		reg = <0x40>;
+	};
+
+	usb_c0_soc_side_bb_retimer: jhl8040r-c0-soc-side@54 {
+		compatible = "intel,jhl8040r";
+		reg = <0x54>;
+		reset-pin = <&usb_c0_bb_retimer_rst>;
+		ls-en-pin = <&usb_c0_bb_retimer_ls_en>;
+	};
+
+	usb_c0_bb_retimer: jhl8040r-c0@56 {
+		compatible = "intel,jhl8040r";
+		reg = <0x56>;
+		reset-pin = <&usb_c0_bb_retimer_rst>;
+		ls-en-pin = <&usb_c0_bb_retimer_ls_en>;
+	};
+};
+
+/* typec_1 */
+&i2c_smb_2 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	port_sel = <3>;
+	pinctrl-0 = <&i2c03_scl_gpio010 &i2c03_sda_gpio007>;
+	pinctrl-names = "default";
+
+	tcpc_port1: fusb302@22 {
+		compatible = "fairchild,fusb302";
+		reg = <0x22>;
+		int-pin = <&usbc_tcpc_alrt_p1>;
+	};
+
+	ppc_port1: sn5s330@40 {
+		compatible = "ti,sn5s330";
+		status = "okay";
+		reg = <0x40>;
+	};
+
+	usb_c1_soc_side_bb_retimer: jhl8040r-c1-soc-side@55 {
+		compatible = "intel,jhl8040r";
+		reg = <0x55>;
+		reset-pin = <&usb_c1_bb_retimer_rst>;
+		ls-en-pin = <&usb_c1_bb_retimer_ls_en>;
+	};
+
+	usb_c1_bb_retimer: jhl8040r-c1@57 {
+		compatible = "intel,jhl8040r";
+		reg = <0x57>;
+		reset-pin = <&usb_c1_bb_retimer_rst>;
+		ls-en-pin = <&usb_c1_bb_retimer_ls_en>;
+	};
+};
+
+/* typec_2 */
+&i2c_smb_3 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	port_sel = <7>;
+	pinctrl-0 = <&i2c07_scl_gpio013 &i2c07_sda_gpio012>;
+	pinctrl-names = "default";
+
+	tcpc_port2: fusb302@22 {
+		compatible = "fairchild,fusb302";
+		reg = <0x22>;
+		int-pin = <&usbc_tcpc_alrt_p2>;
+	};
+
+	ppc_port2: sn5s330@40 {
+		compatible = "ti,sn5s330";
+		status = "okay";
+		reg = <0x40>;
+	};
+
+	usb_c2_bb_retimer: jhl8040r-c2@58 {
+		compatible = "intel,jhl8040r";
+		reg = <0x58>;
+		reset-pin = <&usb_c2_bb_retimer_rst>;
+		ls-en-pin = <&usb_c2_bb_retimer_ls_en>;
+	};
+};
+
+/* typec_3 */
+&i2c_smb_4 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	port_sel = <2>;
+	pinctrl-0 = <&i2c02_scl_gpio155 &i2c02_sda_gpio154>;
+	pinctrl-names = "default";
+
+	tcpc_port3: fusb302@22 {
+		compatible = "fairchild,fusb302";
+		reg = <0x22>;
+		int-pin = <&usbc_tcpc_alrt_p3>;
+	};
+
+	ppc_port3: sn5s330@40 {
+		compatible = "ti,sn5s330";
+		status = "okay";
+		reg = <0x40>;
+	};
+
+	usb_c3_bb_retimer: jhl8040r-c3@59 {
+		compatible = "intel,jhl8040r";
+		reg = <0x59>;
+		reset-pin = <&usb_c3_bb_retimer_rst>;
+		ls-en-pin = <&usb_c3_bb_retimer_ls_en>;
+	};
+};
diff --git a/zephyr/program/intelrvp/adlrvp/adlrvp_mchp/bb_retimer.dts b/zephyr/program/intelrvp/adlrvp/adlrvp_mchp/bb_retimer.dts
new file mode 100644
index 0000000000..1c760120f1
--- /dev/null
+++ b/zephyr/program/intelrvp/adlrvp/adlrvp_mchp/bb_retimer.dts
@@ -0,0 +1,28 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+&i2c_smb_1 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+
+	usb_c0_bb_retimer: jhl8040r@56 {
+		compatible = "intel,jhl8040r";
+		reg = <0x56>;
+		label = "USB_C0_BB_RETIMER";
+		reset-pin = <&usb_c0_bb_retimer_rst>;
+	};
+};
+
+&i2c_smb_2 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+
+	usb_c1_bb_retimer: jhl8040r@57 {
+		compatible = "intel,jhl8040r";
+		reg = <0x57>;
+		label = "USB_C1_BB_RETIMER";
+		reset-pin = <&usb_c1_bb_retimer_rst>;
+	};
+};
diff --git a/zephyr/program/intelrvp/adlrvp/adlrvp_mchp/gpio.dts b/zephyr/program/intelrvp/adlrvp/adlrvp_mchp/gpio.dts
new file mode 100644
index 0000000000..d526fdcb3b
--- /dev/null
+++ b/zephyr/program/intelrvp/adlrvp/adlrvp_mchp/gpio.dts
@@ -0,0 +1,299 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	aliases {
+		gpio-wp = &gpio_wp;
+		gpio-kbd-kso2 = &gpio_ec_kso_02_inv;
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		all_sys_pwrgd: all-sys-pwrgd {
+			gpios = <&gpio_040_076 15 GPIO_INPUT>;
+			enum-name = "GPIO_PG_EC_ALL_SYS_PWRGD";
+		}; /* GPIO057 */
+		rsmrst_pwrgd: rsmrst-pwrgd {
+			gpios = <&gpio_200_236 17 GPIO_INPUT>;
+			enum-name = "GPIO_PG_EC_RSMRST_ODL";
+		}; /* GPIO221 */
+		pch_slp_s0_n: pch-slp-s0-n {
+			gpios = <&gpio_240_276 3 GPIO_INPUT>;
+			enum-name = "GPIO_PCH_SLP_S0_L";
+		}; /* GPIO243 */
+		vccpdsw_3p3: vccpdsw-3p3 {
+			gpios = <&gpio_200_236 1 GPIO_INPUT>;
+			enum-name = "GPIO_PG_EC_DSW_PWROK";
+		}; /* GPIO201 */
+		pm_slp_sus_ec_n: pm-slp-sus-ec-n {
+			gpios = <&gpio_200_236 23 GPIO_INPUT>;
+			enum-name = "GPIO_SLP_SUS_L";
+		}; /* GPIO227 */
+		pm_slp_s3_n: pm-slp-s3-n {
+			gpios = <&gpio_140_176 17 GPIO_INPUT>;
+			enum-name = "GPIO_PCH_SLP_S3_L";
+		}; /* GPIO161 */
+		pm_slp_s4_n: pm-slp-s4-n {
+			gpios = <&gpio_140_176 18 GPIO_INPUT>;
+		}; /* GPIO162 */
+		volume_up {
+			gpios = <&gpio_000_036 30 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_UP_L";
+		}; /* GPIO036 */
+		vol_dn_ec {
+			gpios = <&gpio_240_276 12 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_DOWN_L";
+		}; /* GPIO254 */
+		smc_lid: smc-lid {
+			gpios = <&gpio_200_236 22 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_LID_OPEN";
+		}; /* GPIO226 */
+		mech_pwr_btn_odl: mech-pwr-btn-odl {
+			gpios = <&gpio_100_136 13 GPIO_INPUT>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		}; /* GPIO115 */
+		std_adp_prsnt: std-adp-prsnt {
+			gpios = <&gpio_040_076 3 GPIO_INPUT>;
+			enum-name= "GPIO_DC_JACK_PRESENT";
+		}; /* GPIO043 */
+		bc_acok: bc-acok {
+			gpios = <&gpio_140_176 14 GPIO_INPUT>;
+			enum-name = "GPIO_AC_PRESENT";
+		}; /* GPIO156 */
+		usbc_tcpc_alrt_p0: usbc-tcpc-alrt-p0 {
+			gpios = <&gpio_140_176 3 GPIO_INPUT>;
+		}; /* GPIO143 */
+		usbc_tcpc_alrt_p1: usbc-tcpc-alrt-p1 {
+			gpios = <&gpio_240_276 1 GPIO_INPUT>;
+		}; /* GPIO241 */
+		usbc_tcpc_alrt_p2: usbc-tcpc-alrt-p2 {
+			gpios = <&gpio_100_136 24 GPIO_INPUT>;
+		}; /* GPIO130 */
+		usbc_tcpc_alrt_p3: usbc-tcpc-alrt-p3 {
+			gpios = <&gpio_240_276 2 GPIO_INPUT>;
+		}; /* GPIO242 */
+		usbc_tcpc_ppc_alrt_p0: usbc-tcpc-ppc-alrt-p0 {
+			gpios = <&gpio_240_276 0 GPIO_INPUT>;
+		}; /* GPIO240 */
+		usbc_tcpc_ppc_alrt_p1: usbc-tcpc-ppc-alrt-p1 {
+			gpios = <&gpio_100_136 1 GPIO_INPUT>;
+		}; /* GPIO101 */
+		usbc_tcpc_ppc_alrt_p2: usbc-tcpc-ppc-alrt-p2 {
+			gpios = <&gpio_140_176 4 GPIO_INPUT>;
+		}; /* GPIO144 */
+		usbc_tcpc_ppc_alrt_p3: usbc-tcpc-ppc-alrt-p3 {
+			gpios = <&gpio_140_176 2 GPIO_INPUT>;
+		}; /* GPIO142 */
+		gpio_ec_pch_wake_odl: smc-wake-sci-n-mecc {
+			gpios = <&gpio_040_076 9 GPIO_ODR_HIGH>;
+		}; /* GPIO051 */
+		ec_pch_mkbp_int_odl {
+			gpios = <&gpio_100_136 23 GPIO_ODR_HIGH>;
+		}; /* GPIO127 */
+		lpc_espi_rst_n {
+			gpios = <&gpio_040_076 17 GPIO_INPUT>;
+		}; /* GPIO061 NANA */
+		plt_rst_l {
+			gpios = <&gpio_040_076 10 GPIO_INPUT>;
+		}; /* GPIO052 NANA */
+		slate_mode_indication {
+			gpios = <&gpio_200_236 18 GPIO_INPUT>;
+		}; /* GPIO222 */
+		prochot_ec_n {
+			gpios = <&gpio_000_036 2 GPIO_INPUT>;
+			enum-name = "GPIO_CPU_PROCHOT";
+		}; /* GPIO002 ???? */
+		sys_rst_odl {
+			gpios = <&gpio_040_076 16 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_SYS_RESET_L";
+		}; /* GPIO060 */
+		pm_rsmrst_n {
+			gpios = <&gpio_040_076 12 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_PCH_RSMRST_L";
+		}; /* GPIO054 */
+		pm_pwrbtn_n {
+			gpios = <&gpio_000_036 14 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_PCH_PWRBTN_L";
+		}; /* GPIO016 */
+		ec_spi_oe_mecc: ec-spi-oe-mecc {
+			gpios = <&gpio_040_076 2 GPIO_OUTPUT_LOW>;
+		}; /* GPIO042 */
+		ec_ds3 {
+			gpios = <&gpio_000_036 21 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_EN_PP3300_A";
+		}; /* GPIO025 */
+		pch_pwrok_ec {
+			gpios = <&gpio_100_136 6 GPIO_INPUT>;
+			enum-name = "GPIO_PCH_PWROK";
+		}; /* GPIO106 */
+		sys_pwrok {
+			gpios = <&gpio_200_236 2 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_PCH_SYS_PWROK";
+		}; /* GPIO202 */
+		ec_dsw_pwrok {
+			gpios = <&gpio_000_036 28 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_PCH_DSW_PWROK";
+		}; /* GPIO034 */
+		gpio_wp: ec-flash-wp-odl {
+			gpios = <&gpio_000_036 12 GPIO_INPUT>;
+		}; /* GPIO014 */
+		ec_h1_packet_mode {
+			gpios = <&gpio_000_036 29 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_PACKET_MODE_EN";
+		}; /* GPIO035 */
+		ec_entering_rw {
+			gpios = <&gpio_100_136 2 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_ENTERING_RW";
+		}; /* GPIO102 */
+		ccd_mode_odl: ccd-mode-odl {
+			gpios = <&gpio_140_176 29 GPIO_INPUT>;
+			enum-name  = "GPIO_CCD_MODE_ODL";
+		}; /* GPIO175 */
+		bat_det {
+			gpios = <&gpio_200_236 6 GPIO_INPUT>;
+			enum-name = "GPIO_BATT_PRES_ODL";
+		}; /* GPIO206 */
+		edp_bklt_en_mecc {
+			gpios = <&gpio_000_036 18 GPIO_OUTPUT_HIGH>;
+		}; /* GPIO022 */
+		led_1_l {
+			gpios = <&gpio_140_176 15 GPIO_OUTPUT_HIGH>;
+		}; /* GPIO157 */
+		led_2_l {
+			gpios = <&gpio_140_176 11 GPIO_OUTPUT_HIGH>;
+		}; /* GPIO153 */
+		therm_sen_mecc {
+			gpios = <&gpio_140_176 1 GPIO_OUTPUT_LOW>;
+		}; /* GPIO141 */
+		smb_bs_clk {
+			gpios = <&gpio_000_036 4 GPIO_INPUT>;
+		}; /* GPIO004 */
+		smb_bs_data {
+			gpios = <&gpio_000_036 3 GPIO_INPUT>;
+		}; /* GPIO003 */
+		usbc_tcpc_i2c_clk_p0 {
+			gpios = <&gpio_140_176 0 GPIO_INPUT>;
+		}; /* GPIO140 */
+		usbc_tcpc_i2c_data_p0 {
+			gpios = <&gpio_100_136 26 GPIO_INPUT>;
+		}; /* GPIO132 */
+		usbc_tcpc_i2c_clk_p2 {
+			gpios = <&gpio_000_036 8 GPIO_INPUT>;
+		}; /* GPIO010 */
+		usbc_tcpc_i2c_data_p2 {
+			gpios = <&gpio_000_036 7 GPIO_INPUT>;
+		}; /* GPIO007 */
+		usbc_tcpc_i2c_clk_p1 {
+			gpios = <&gpio_000_036 11 GPIO_INPUT>;
+		}; /* GPIO013 */
+		usbc_tcpc_i2c_data_p1 {
+			gpios = <&gpio_000_036 10 GPIO_INPUT>;
+		}; /* GPIO012 */
+		usbc_tcpc_i2c_clk_p3 {
+			gpios = <&gpio_140_176 13 GPIO_INPUT>;
+		}; /* GPIO155 */
+		usbc_tcpc_i2c_data_p3 {
+			gpios = <&gpio_140_176 12 GPIO_INPUT>;
+		}; /* GPIO154 */
+		sml1_clk_mecc {
+			gpios = <&gpio_100_136 25 GPIO_INPUT>;
+		}; /* GPIO131 */
+		cpu_cat_err_mecc {
+			gpios = <&gpio_000_036 0 GPIO_INPUT>;
+		}; /* GPIO000 */
+		espi_alert0_n {
+			gpios = <&gpio_040_076 19 GPIO_INPUT>;
+		}; /* GPIO063 NANA */
+		batt_disable_ec {
+			gpios = <&gpio_040_076 23 GPIO_INPUT>;
+		}; /* GPIO067 */
+		cpu_c10_gate_mecc {
+			gpios = <&gpio_000_036 19 GPIO_INPUT>;
+		}; /* GPIO023 */
+		smc_sdown_mecc {
+			gpios = <&gpio_240_276 13 GPIO_INPUT>;
+		}; /* GPIO255 */
+		std_adpt_cntrl_gpio {
+			gpios = <&gpio_240_276 4 GPIO_INPUT>;
+		}; /* GPIO244 */
+		smc_onoff_n {
+			gpios = <&gpio_100_136 12 GPIO_INPUT>;
+		}; /* GPIO114 */
+		suswarn {
+			gpios = <&gpio_000_036 20 GPIO_INPUT>;
+		}; /* GPIO024 */
+		me_g3_to_m3_ec {
+			gpios = <&gpio_000_036 27 GPIO_INPUT>;
+		}; /* GPIO033 */
+		gpio_ec_kso_02_inv: ec-kso-02-inv {
+			gpios = <&gpio_040_076 6 (GPIO_OUTPUT_LOW
+				| GPIO_ACTIVE_LOW)>;
+		}; /* GPIO046 */
+
+		usb_c0_bb_retimer_rst: usb-c0-bb-retimer-rst {
+			gpios = <&ioex_c0_port 0 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C0_BB_RETIMER_RST";
+		};
+		usb_c0_bb_retimer_ls_en: usb-c0-bb-retimer-ls-en {
+			gpios = <&ioex_c0_port 1 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C0_BB_RETIMER_LS_EN";
+		};
+		usb-c0-usb-mux-cntrl-1 {
+			gpios = <&ioex_c0_port 4 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C0_USB_MUX_CNTRL_1";
+		};
+		usb-c0-usb-mux-cntrl-0 {
+			gpios = <&ioex_c0_port 5 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C0_USB_MUX_CNTRL_0";
+		};
+		usb_c1_bb_retimer_rst: usb-c1-bb-retimer-rst {
+			gpios = <&ioex_c1_port 0 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C1_BB_RETIMER_RST";
+		};
+		usb_c1_bb_retimer_ls_en: usb-c1-bb-retimer-ls-en {
+			gpios = <&ioex_c1_port 1 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C1_BB_RETIMER_LS_EN";
+		};
+		usb-c1-hpd {
+			gpios = <&ioex_c1_port 2 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C1_HPD";
+		};
+		usb-c0-c1-oc {
+			gpios = <&ioex_c1_port 8 GPIO_OUTPUT_HIGH>;
+			enum-name = "IOEX_USB_C0_C1_OC";
+		};
+		usb_c2_bb_retimer_rst: usb-c2-bb-retimer-rst {
+			gpios = <&ioex_c2_port 0 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C2_BB_RETIMER_RST";
+		};
+		usb_c2_bb_retimer_ls_en: usb-c2-bb-retimer-ls-en {
+			gpios = <&ioex_c2_port 1 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C2_BB_RETIMER_LS_EN";
+		};
+		usb-c2-usb-mux-cntrl-1 {
+			gpios = <&ioex_c2_port 4 GPIO_OUTPUT_LOW>;
+		};
+		usb-c2-usb-mux-cntrl-0 {
+			gpios = <&ioex_c2_port 5 GPIO_OUTPUT_LOW>;
+		};
+		usb_c3_bb_retimer_rst: usb-c3-bb-retimer-rst {
+			gpios = <&ioex_c3_port 0 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C3_BB_RETIMER_RST";
+		};
+		usb_c3_bb_retimer_ls_en: usb-c3-bb-retimer-ls-en {
+			gpios = <&ioex_c3_port 1 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C3_BB_RETIMER_LS_EN";
+		};
+		usb-c2-c3-oc {
+			gpios = <&ioex_c3_port 8 GPIO_OUTPUT_HIGH>;
+			enum-name = "IOEX_USB_C2_C3_OC";
+		};
+		/* unimplemented GPIOs */
+		en-pp5000 {
+			enum-name = "GPIO_EN_PP5000";
+		};
+	};
+};
diff --git a/zephyr/program/intelrvp/adlrvp/adlrvp_mchp/interrupts.dts b/zephyr/program/intelrvp/adlrvp/adlrvp_mchp/interrupts.dts
new file mode 100644
index 0000000000..17986fe2c7
--- /dev/null
+++ b/zephyr/program/intelrvp/adlrvp/adlrvp_mchp/interrupts.dts
@@ -0,0 +1,80 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/ {
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_lid_open: lid-open {
+			irq-pin = <&smc_lid>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "lid_interrupt";
+		};
+		int_power_button: power-button {
+			irq-pin = <&mech_pwr_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_button_interrupt";
+		};
+		int_ac_present: ac-present {
+			irq-pin = <&bc_acok>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "extpower_interrupt";
+		};
+		int_slp_s0: slp-s0 {
+			irq-pin = <&pch_slp_s0_n>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_slp_sus: slp-sus {
+			irq-pin = <&pm_slp_sus_ec_n>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_pg_dsw_pwrok: pg-dsw-pwrok {
+			irq-pin = <&vccpdsw_3p3>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_rsmrst_pwrgd: rsmrst-pwrgd {
+			irq-pin = <&rsmrst_pwrgd>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_all_sys_pwrgd: all-sys-pwrgd {
+			irq-pin = <&all_sys_pwrgd>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_usbc_tcpc_alrt_p0: usbc-tcpc-alrt-p0 {
+			irq-pin = <&usbc_tcpc_alrt_p0>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "tcpc_alert_event";
+		};
+		int_usbc_tcpc_alrt_p1: usbc-tcpc-alrt-p1 {
+			irq-pin = <&usbc_tcpc_alrt_p1>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "tcpc_alert_event";
+		};
+		int_usbc_tcpc_ppc_alrt_p0: usbc-tcpc-ppc-alrt-p0 {
+			irq-pin = <&usbc_tcpc_ppc_alrt_p0>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "ppc_interrupt";
+		};
+		int_usbc_tcpc_ppc_alrt_p1: usbc-tcpc-ppc-alrt-p1 {
+			irq-pin = <&usbc_tcpc_ppc_alrt_p1>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "ppc_interrupt";
+		};
+		int_std_adp_prsnt: std-adp-prsnt {
+			irq-pin = <&std_adp_prsnt>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "board_dc_jack_interrupt";
+		};
+		int_ccd_mode_odl: ccd-mode-odl {
+			irq-pin = <&ccd_mode_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "board_connect_c0_sbu";
+		};
+	};
+};
diff --git a/zephyr/program/intelrvp/adlrvp/adlrvp_mchp/keyboard.dts b/zephyr/program/intelrvp/adlrvp/adlrvp_mchp/keyboard.dts
new file mode 100644
index 0000000000..2601da793d
--- /dev/null
+++ b/zephyr/program/intelrvp/adlrvp/adlrvp_mchp/keyboard.dts
@@ -0,0 +1,31 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	cros-keyscan {
+		compatible = "cros-ec,keyscan";
+
+		output-settle = <80>;
+		debounce-down = <9000>;
+		debounce-up = <30000>;
+		poll-timeout = <100000>;
+
+		actual-key-mask = <
+			0x14	/* C0 */
+			0xff	/* C1 */
+			0xff	/* C2 */
+			0xff	/* C3 */
+			0xff	/* C4 */
+			0xf5	/* C5 */
+			0xff	/* C6 */
+			0xa4	/* C7 */
+			0xff	/* C8 */
+			0xfe	/* C9 */
+			0x55	/* C10 */
+			0xfa	/* C11 */
+			0xca	/* C12 */
+			>;
+	};
+};
diff --git a/zephyr/program/intelrvp/adlrvp/adlrvp_mchp/prj.conf b/zephyr/program/intelrvp/adlrvp/adlrvp_mchp/prj.conf
new file mode 100644
index 0000000000..858f174bfb
--- /dev/null
+++ b/zephyr/program/intelrvp/adlrvp/adlrvp_mchp/prj.conf
@@ -0,0 +1,69 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_BOARD_ADLRVP_MCHP=y
+CONFIG_CROS_SYSTEM_XEC=y
+
+# For MCHP ESPI Drivers
+CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD=y
+CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION=y
+CONFIG_ESPI_PERIPHERAL_CUSTOM_OPCODE=y
+CONFIG_ESPI_PERIPHERAL_XEC_EMI0=y
+CONFIG_ESPI_PERIPHERAL_ACPI_EC_IBF_EVT_DATA=y
+CONFIG_ESPI_PERIPHERAL_KBC_OBE_CBK=y
+CONFIG_ESPI_PERIPHERAL_KBC_IBF_EVT_DATA=y
+
+# Invoke SoC Python script to create zephyr.mchp.bin which
+# is zephyr.bin processed for Boot-ROM loading.
+CONFIG_MCHP_MEC_UNSIGNED_HEADER=y
+CONFIG_MCHP_MEC_HEADER_FLASH_SIZE_256K=y
+
+# Sensors - MCHP TACH driver under sensor
+CONFIG_SENSOR=n
+
+# Debug option
+# Enable flash console commands
+CONFIG_PLATFORM_EC_CONSOLE_CMD_FLASH=y
+
+
+## TODO - support following features next
+# Fan
+CONFIG_PLATFORM_EC_FAN=n
+
+# RTC
+CONFIG_PLATFORM_EC_RTC=n
+
+# PWM
+CONFIG_PWM=n
+
+## INTEL RVP
+# Host command
+CONFIG_PLATFORM_EC_HOSTCMD_AP_RESET=n
+
+# Power Sequencing
+CONFIG_PLATFORM_EC_THROTTLE_AP=n
+
+## ADL RVP
+# CBI
+CONFIG_EEPROM=n
+
+# LED
+CONFIG_PLATFORM_EC_LED_COMMON=n
+CONFIG_PLATFORM_EC_LED_PWM=n
+CONFIG_PLATFORM_EC_LED_PWM_TASK_DISABLED=n
+
+# Temperature sensors
+CONFIG_PLATFORM_EC_THERMISTOR=n
+CONFIG_PLATFORM_EC_TEMP_SENSOR_POWER=n
+
+# Charger
+CONFIG_PLATFORM_EC_DEDICATED_CHARGE_PORT=y
+
+# H1 issues second reset
+CONFIG_PLATFORM_EC_BOARD_RESET_AFTER_POWER_ON=n
+
+# Debug options
+# Enable flash console commands
+CONFIG_PLATFORM_EC_CONSOLE_CMD_FLASH=y
+CONFIG_WDT_DISABLE_AT_BOOT=y
diff --git a/zephyr/program/intelrvp/adlrvp/adlrvp_mchp/usbc.dts b/zephyr/program/intelrvp/adlrvp/adlrvp_mchp/usbc.dts
new file mode 100644
index 0000000000..615364b9c9
--- /dev/null
+++ b/zephyr/program/intelrvp/adlrvp/adlrvp_mchp/usbc.dts
@@ -0,0 +1,93 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		usbc_port0: port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+			tcpc = <&tcpc_port0>;
+			ppc = <&ppc_port0>;
+			chg = <&charger>;
+			usb_mux_chain_0: usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_c0_bb_retimer
+					     &virtual_mux_c0>;
+			};
+			usb_mux_alt_chain_0: usb-mux-alt-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				alternative-chain;
+				usb-muxes = <&usb_c0_bb_retimer
+					     &usb_c0_soc_side_bb_retimer
+					     &virtual_mux_c0>;
+			};
+		};
+		port0-muxes {
+			virtual_mux_c0: virtual-mux-c0 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+
+		usbc_port1: port1@1 {
+			compatible = "named-usbc-port";
+			reg = <1>;
+			tcpc = <&tcpc_port1>;
+			ppc = <&ppc_port1>;
+			usb_mux_chain_1: usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_c1_bb_retimer
+					     &virtual_mux_c1>;
+			};
+			usb_mux_alt_chain_1: usb-mux-alt-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				alternative-chain;
+				usb-muxes = <&usb_c1_bb_retimer
+					     &usb_c1_soc_side_bb_retimer
+					     &virtual_mux_c1>;
+			};
+		};
+		port1-muxes {
+			virtual_mux_c1: virtual-mux-c1 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+
+		port2@2 {
+			compatible = "named-usbc-port";
+			reg = <2>;
+			tcpc = <&tcpc_port2>;
+			ppc = <&ppc_port2>;
+			usb_mux_chain_2: usb-mux-chain-2 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_c2_bb_retimer
+					     &virtual_mux_c2>;
+			};
+		};
+		port2-muxes {
+			virtual_mux_c2: virtual-mux-c2 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+
+		port3@3 {
+			compatible = "named-usbc-port";
+			reg = <3>;
+			tcpc = <&tcpc_port3>;
+			ppc = <&ppc_port3>;
+			usb_mux_chain_3: usb-mux-chain-3 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_c3_bb_retimer
+					     &virtual_mux_c3>;
+			};
+		};
+		port3-muxes {
+			virtual_mux_c3: virtual-mux-c3 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+	};
+};
diff --git a/zephyr/program/intelrvp/adlrvp/adlrvp_npcx/adlrvp_npcx.dts b/zephyr/program/intelrvp/adlrvp/adlrvp_npcx/adlrvp_npcx.dts
new file mode 100644
index 0000000000..56acf9e3dc
--- /dev/null
+++ b/zephyr/program/intelrvp/adlrvp/adlrvp_npcx/adlrvp_npcx.dts
@@ -0,0 +1,285 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	chosen {
+		cros,rtc = &mtc;
+	};
+
+	hibernate-wake-pins {
+		compatible = "cros-ec,hibernate-wake-pins";
+		wakeup-irqs = <
+			&int_ac_present
+			&int_lid_open
+			&int_power_button
+		>;
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		i2c_charger: charger {
+			i2c-port = <&i2c7_0>;
+			enum-names = "I2C_PORT_BATTERY",
+				"I2C_PORT_CHARGER",
+				"I2C_PORT_EEPROM",
+				"I2C_PORT_PORT80";
+		};
+		typec_0: typec-0 {
+			i2c-port = <&i2c0_0>;
+			enum-names = "I2C_PORT_TYPEC_0";
+		};
+		typec_1: typec-1 {
+			i2c-port = <&i2c2_0>;
+			enum-names = "I2C_PORT_TYPEC_1";
+		};
+		typec_2: typec-2 {
+			i2c-port = <&i2c1_0>;
+			enum-names = "I2C_PORT_TYPEC_2";
+		};
+		typec_3: typec-3 {
+			i2c-port = <&i2c3_0>;
+			enum-names = "I2C_PORT_TYPEC_3";
+		};
+	};
+
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		adc_ambient: ambient {
+			enum-name = "ADC_TEMP_SENSOR_1";
+			io-channels = <&adc0 3>;
+		};
+		adc_ddr: ddr {
+			enum-name = "ADC_TEMP_SENSOR_2";
+			io-channels = <&adc0 4>;
+		};
+		adc_skin: skin {
+			enum-name = "ADC_TEMP_SENSOR_3";
+			io-channels = <&adc0 2>;
+		};
+		adc_vr: vr {
+			enum-name = "ADC_TEMP_SENSOR_4";
+			io-channels = <&adc0 1>;
+		};
+	};
+
+};
+
+/* host interface */
+&espi0 {
+	status = "okay";
+	pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>;
+	pinctrl-names = "default";
+};
+
+/* charger */
+&i2c7_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>;
+	pinctrl-names = "default";
+
+	pca95xx: pca95xx@22 {
+		compatible = "nxp,pca95xx";
+		label = "PCA95XX";
+		reg = <0x22>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <16>;
+	};
+
+	rvp_board_id: rvp-board-id {
+		compatible = "intel,rvp-board-id";
+
+		/*
+		 * BOM ID [2]   : IOEX[0]
+		 * BOM ID [1:0] : IOEX[15:14]
+		 */
+		bom-gpios = <&pca95xx 0 0>, <&pca95xx 15 0>, <&pca95xx 14 0>;
+
+		/*
+		 * FAB ID [1:0] : IOEX[2:1]
+		 */
+		fab-gpios = <&pca95xx 2 0>, <&pca95xx 1 0>;
+
+		/*
+		 * BOARD ID[5:0] : IOEX[13:8]
+		 */
+		board-gpios = <&pca95xx 13 0>, <&pca95xx 12 0>, <&pca95xx 11 0>,
+			      <&pca95xx 10 0>, <&pca95xx 9 0>, <&pca95xx 8 0>;
+	};
+
+	max695x@38 {
+		compatible = "maxim,max695x";
+		reg = <0x38>;
+	};
+
+	charger: isl9241@9 {
+		compatible = "intersil,isl9241";
+		status = "okay";
+		reg = <0x9>;
+	};
+
+	cbi_eeprom: eeprom@50 {
+		compatible = "atmel,at24";
+		reg = <0x50>;
+		size = <2048>;
+		pagesize = <16>;
+		address-width = <8>;
+		timeout = <5>;
+	};
+};
+
+&i2c_ctrl7 {
+	status = "okay";
+};
+
+/* typec_0 */
+&i2c0_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>;
+	pinctrl-names = "default";
+
+	tcpc_port0: fusb302@22 {
+		compatible = "fairchild,fusb302";
+		reg = <0x22>;
+		int-pin = <&usbc_tcpc_alrt_p0>;
+	};
+
+	ppc_port0: sn5s330@40 {
+		compatible = "ti,sn5s330";
+		status = "okay";
+		reg = <0x40>;
+	};
+
+	usb_c0_soc_side_bb_retimer: jhl8040r-c0-soc-side@54 {
+		compatible = "intel,jhl8040r";
+		reg = <0x54>;
+		reset-pin = <&usb_c0_bb_retimer_rst>;
+		ls-en-pin = <&usb_c0_bb_retimer_ls_en>;
+	};
+
+	usb_c0_bb_retimer: jhl8040r-c0@56 {
+		compatible = "intel,jhl8040r";
+		reg = <0x56>;
+		reset-pin = <&usb_c0_bb_retimer_rst>;
+		ls-en-pin = <&usb_c0_bb_retimer_ls_en>;
+	};
+};
+
+&i2c_ctrl0 {
+	status = "okay";
+};
+
+/* typec_1 */
+&i2c2_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c2_0_sda_scl_gp91_92>;
+	pinctrl-names = "default";
+
+	tcpc_port1: fusb302@22 {
+		compatible = "fairchild,fusb302";
+		reg = <0x22>;
+		int-pin = <&usbc_tcpc_alrt_p1>;
+	};
+
+	ppc_port1: sn5s330@40 {
+		compatible = "ti,sn5s330";
+		status = "okay";
+		reg = <0x40>;
+	};
+
+	usb_c1_soc_side_bb_retimer: jhl8040r-c1-soc-side@55 {
+		compatible = "intel,jhl8040r";
+		reg = <0x55>;
+		reset-pin = <&usb_c1_bb_retimer_rst>;
+		ls-en-pin = <&usb_c1_bb_retimer_ls_en>;
+	};
+
+	usb_c1_bb_retimer: jhl8040r-c1@57 {
+		compatible = "intel,jhl8040r";
+		reg = <0x57>;
+		reset-pin = <&usb_c1_bb_retimer_rst>;
+		ls-en-pin = <&usb_c1_bb_retimer_ls_en>;
+	};
+};
+
+&i2c_ctrl2 {
+	status = "okay";
+};
+
+/* typec_2 */
+&i2c1_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>;
+	pinctrl-names = "default";
+
+	tcpc_port2: fusb302@22 {
+		compatible = "fairchild,fusb302";
+		reg = <0x22>;
+		int-pin = <&usbc_tcpc_alrt_p2>;
+	};
+
+	ppc_port2: sn5s330@40 {
+		compatible = "ti,sn5s330";
+		status = "okay";
+		reg = <0x40>;
+	};
+
+	usb_c2_bb_retimer: jhl8040r-c2@58 {
+		compatible = "intel,jhl8040r";
+		reg = <0x58>;
+		reset-pin = <&usb_c2_bb_retimer_rst>;
+		ls-en-pin = <&usb_c2_bb_retimer_ls_en>;
+	};
+};
+
+&i2c_ctrl1 {
+	status = "okay";
+};
+
+/* typec_3 */
+&i2c3_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>;
+	pinctrl-names = "default";
+
+	tcpc_port3: fusb302@22 {
+		compatible = "fairchild,fusb302";
+		reg = <0x22>;
+		int-pin = <&usbc_tcpc_alrt_p3>;
+	};
+
+	ppc_port3: sn5s330@40 {
+		compatible = "ti,sn5s330";
+		status = "okay";
+		reg = <0x40>;
+	};
+
+	usb_c3_bb_retimer: jhl8040r-c3@59 {
+		compatible = "intel,jhl8040r";
+		reg = <0x59>;
+		reset-pin = <&usb_c3_bb_retimer_rst>;
+		ls-en-pin = <&usb_c3_bb_retimer_ls_en>;
+	};
+};
+
+&i2c_ctrl3 {
+	status = "okay";
+};
+
+&adc0 {
+	status = "okay";
+	pinctrl-0 = <&adc0_chan1_gp44
+		     &adc0_chan2_gp43
+		     &adc0_chan3_gp42
+		     &adc0_chan4_gp41>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/intelrvp/adlrvp/adlrvp_npcx/fan.dts b/zephyr/program/intelrvp/adlrvp/adlrvp_npcx/fan.dts
new file mode 100644
index 0000000000..8babe53903
--- /dev/null
+++ b/zephyr/program/intelrvp/adlrvp/adlrvp_npcx/fan.dts
@@ -0,0 +1,36 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	fans {
+		compatible = "cros-ec,fans";
+
+		fan_0 {
+			pwms = <&pwm3 0 PWM_KHZ(30) PWM_POLARITY_NORMAL>;
+			rpm_min = <3000>;
+			rpm_start = <3000>;
+			rpm_max = <10000>;
+			tach = <&tach2>;
+			pgood_gpio = <&all_sys_pwrgd>;
+			enable_gpio = <&gpio_fan_control>;
+		};
+	};
+};
+
+/* Tachemeter for fan speed measurement */
+&tach2 {
+	status = "okay";
+	pinctrl-0 = <&ta2_2_in_gpa6>;
+	pinctrl-names = "default";
+	port = <NPCX_TACH_PORT_A>; /* port-A is selected */
+	sample-clk = <NPCX_TACH_FREQ_LFCLK>; /* Use LFCLK as sampling clock */
+	pulses-per-round = <2>; /* number of pulses per round of encoder */
+};
+
+&pwm3 {
+	status = "okay";
+	pinctrl-0 = <&pwm3_gp80>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/intelrvp/adlrvp/adlrvp_npcx/gpio.dts b/zephyr/program/intelrvp/adlrvp/adlrvp_npcx/gpio.dts
new file mode 100644
index 0000000000..1d38fc877c
--- /dev/null
+++ b/zephyr/program/intelrvp/adlrvp/adlrvp_npcx/gpio.dts
@@ -0,0 +1,344 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	aliases {
+		gpio-wp = &gpio_wp;
+		gpio-kbd-kso2 = &gpio_ec_kso_02_inv;
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		all_sys_pwrgd: all-sys-pwrgd {
+			gpios = <&gpio7 0 GPIO_INPUT>;
+			enum-name = "GPIO_PG_EC_ALL_SYS_PWRGD";
+		};
+		rsmrst_pwrgd: rsmrst-pwrgd {
+			gpios = <&gpio3 7 GPIO_INPUT>;
+			enum-name = "GPIO_PG_EC_RSMRST_ODL";
+		};
+		pch_slp_s0_n: pch-slp-s0-n {
+			gpios = <&gpioa 1 GPIO_INPUT>;
+			enum-name = "GPIO_PCH_SLP_S0_L";
+		};
+		vccpdsw_3p3: vccpdsw-3p3 {
+			gpios = <&gpio4 5 GPIO_INPUT>;
+			enum-name = "GPIO_PG_EC_DSW_PWROK";
+		};
+		pm_slp_sus_ec_n: pm-slp-sus-ec-n {
+			gpios = <&gpio8 6 GPIO_INPUT>;
+			enum-name = "GPIO_SLP_SUS_L";
+		};
+		pm-slp-s3-n {
+			gpios = <&gpiob 0 GPIO_INPUT>;
+			enum-name = "GPIO_PCH_SLP_S3_L";
+		};
+		pm-slp-s4-n {
+			gpios = <&gpioa 5 GPIO_INPUT>;
+		};
+		volume-up {
+			gpios = <&gpio6 1 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_UP_L";
+		};
+		vol-dn-ec {
+			gpios = <&gpio0 3 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_DOWN_L";
+		};
+		smc_lid: smc-lid {
+			gpios = <&gpio0 1 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+		mech_pwr_btn_odl: mech-pwr-btn-odl {
+			gpios = <&gpio0 0 GPIO_INPUT>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		std_adp_prsnt: std-adp-prsnt {
+			gpios = <&gpio0 2 GPIO_INPUT>;
+			enum-name= "GPIO_DC_JACK_PRESENT";
+		};
+		bc_acok: bc-acok {
+			gpios = <&gpioc 6 GPIO_INPUT>;
+			enum-name = "GPIO_AC_PRESENT";
+		};
+		usbc_tcpc_alrt_p0: usbc-tcpc-alrt-p0 {
+			gpios = <&gpio4 0 GPIO_INPUT>;
+		};
+		usbc_tcpc_alrt_p1: usbc-tcpc-alrt-p1 {
+			gpios = <&gpio6 2 GPIO_INPUT>;
+		};
+		usbc_tcpc_alrt_p2: usbc-tcpc-alrt-p2 {
+			gpios = <&gpio6 3 GPIO_INPUT>;
+		};
+		usbc_tcpc_alrt_p3: usbc-tcpc-alrt-p3 {
+			gpios = <&gpio6 7 GPIO_INPUT>;
+		};
+		usbc_tcpc_ppc_alrt_p0: usbc-tcpc-ppc-alrt-p0 {
+			gpios = <&gpiof 0 GPIO_INPUT>;
+		};
+		usbc_tcpc_ppc_alrt_p1: usbc-tcpc-ppc-alrt-p1 {
+			gpios = <&gpiof 1 GPIO_INPUT>;
+		};
+		usbc_tcpc_ppc_alrt_p2: usbc-tcpc-ppc-alrt-p2 {
+			gpios = <&gpiof 2 GPIO_INPUT>;
+		};
+		usbc_tcpc_ppc_alrt_p3: usbc-tcpc-ppc-alrt-p3 {
+			gpios = <&gpiof 3 GPIO_INPUT>;
+		};
+		gpio_ec_pch_wake_odl: smc-wake-sci-n-mecc {
+			gpios = <&gpioa 4 GPIO_ODR_HIGH>;
+		};
+		ec-pch-mkbp-int-odl {
+			gpios = <&gpiof 5 GPIO_ODR_HIGH>;
+		};
+		lpc-espi-rst-n {
+			gpios = <&gpio5 4 GPIO_INPUT>;
+		};
+		plt-rst-l {
+			gpios = <&gpioa 2 GPIO_INPUT>;
+		};
+		slate-mode-indication {
+			gpios = <&gpioe 5 GPIO_INPUT>;
+		};
+		prochot-ec-n {
+			gpios = <&gpioa 7 GPIO_INPUT>;
+			enum-name = "GPIO_CPU_PROCHOT";
+		};
+		sys-rst-odl {
+			gpios = <&gpioc 5 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_SYS_RESET_L";
+		};
+		pm-rsmrst-n {
+			gpios = <&gpiod 3 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_PCH_RSMRST_L";
+		};
+		pm-pwrbtn-n {
+			gpios = <&gpio9 7 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_PCH_PWRBTN_L";
+		};
+		ec_spi_oe_mecc: ec-spi-oe-mecc {
+			gpios = <&gpio6 0 GPIO_OUTPUT_LOW>;
+		};
+		ec-ds3 {
+			gpios = <&gpioc 4 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_EN_PP3300_A";
+			alias = "GPIO_TEMP_SENSOR_POWER";
+		};
+		pch-pwrok-ec {
+			gpios = <&gpioa 0 GPIO_INPUT>;
+			enum-name = "GPIO_PCH_PWROK";
+		};
+		sys-pwrok {
+			gpios = <&gpio9 3 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_PCH_SYS_PWROK";
+		};
+		ec-dsw-pwrok {
+			gpios = <&gpio9 5 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_PCH_DSW_PWROK";
+		};
+		gpio_wp: ec-flash-wp-odl {
+			gpios = <&gpio9 4 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		ec-h1-packet-mode {
+			gpios = <&gpioe 2 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_PACKET_MODE_EN";
+		};
+		ec-entering-rw {
+			gpios = <&gpiod 4 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_ENTERING_RW";
+		};
+		ccd_mode_odl: ccd-mode-odl {
+			gpios = <&gpiof 4 GPIO_INPUT>;
+			enum-name  = "GPIO_CCD_MODE_ODL";
+		};
+		bat-det {
+			gpios = <&gpio7 6 GPIO_INPUT>;
+			enum-name = "GPIO_BATT_PRES_ODL";
+		};
+		edp-bklt-en-mecc {
+			gpios = <&gpioe 1 GPIO_OUTPUT_HIGH>;
+		};
+		led_red_l: led-1-l {
+			gpios = <&gpiob 6 GPIO_OUTPUT_HIGH>;
+		};
+		led_white_l: led-2-l {
+			gpios = <&gpiob 7 GPIO_OUTPUT_HIGH>;
+		};
+		gpio_fan_control: therm-sen-mecc {
+			gpios = <&gpioc 0 GPIO_OUTPUT_LOW>;
+		};
+		smb-bs-clk {
+			gpios = <&gpiob 3 GPIO_INPUT>;
+		};
+		smb-bs-data {
+			gpios = <&gpiob 2 GPIO_INPUT>;
+		};
+		usbc-tcpc-i2c-clk-p0 {
+			gpios = <&gpiob 5 GPIO_INPUT>;
+		};
+		usbc-tcpc-i2c-data-p0 {
+			gpios = <&gpiob 4 GPIO_INPUT>;
+		};
+		usbc-tcpc-i2c-clk-p2 {
+			gpios = <&gpio9 2 GPIO_INPUT>;
+		};
+		usbc-tcpc-i2c-data-p2 {
+			gpios = <&gpio9 1 GPIO_INPUT>;
+		};
+		usbc-tcpc-i2c-clk-p1 {
+			gpios = <&gpio9 0 GPIO_INPUT>;
+		};
+		usbc-tcpc-i2c-data-p1 {
+			gpios = <&gpio8 7 GPIO_INPUT>;
+		};
+		usbc-tcpc-i2c-clk-p3 {
+			gpios = <&gpiod 1 GPIO_INPUT>;
+		};
+		usbc-tcpc-i2c-data-p3 {
+			gpios = <&gpiod 0 GPIO_INPUT>;
+		};
+		sml1-clk-mecc {
+			gpios = <&gpio3 3 GPIO_INPUT>;
+		};
+		sml1-data-mecc {
+			gpios = <&gpio3 6 GPIO_INPUT>;
+		};
+		smb-pch-clk {
+			gpios = <&gpioc 2 GPIO_INPUT>;
+		};
+		smb-pch-data {
+			gpios = <&gpioc 1 GPIO_INPUT>;
+		};
+		i3c-0-scl {
+			gpios = <&gpioe 4 GPIO_INPUT>;
+		};
+		i3c-0-sda {
+			gpios = <&gpioe 3 GPIO_INPUT>;
+		};
+		cpu-cat-err-mecc {
+			gpios = <&gpio3 4 GPIO_INPUT>;
+		};
+		tp29 {
+			gpios = <&gpio5 0 GPIO_INPUT>;
+		};
+		tp28 {
+			gpios = <&gpio5 6 GPIO_INPUT>;
+		};
+		espi-alert0-n {
+			gpios = <&gpio5 7 GPIO_INPUT>;
+		};
+		batt-disable-ec {
+			gpios = <&gpio6 6 GPIO_INPUT>;
+		};
+		tp33 {
+			gpios = <&gpio7 2 GPIO_INPUT>;
+		};
+		tp26 {
+			gpios = <&gpio7 3 GPIO_INPUT>;
+		};
+		slp-s0-cs-n {
+			gpios = <&gpio7 4 GPIO_INPUT>;
+		};
+		ec-peci {
+			gpios = <&gpio8 1 GPIO_INPUT>;
+		};
+		cpu-c10-gate-mecc {
+			gpios = <&gpio9 6 GPIO_INPUT>;
+		};
+		smb-pch-alrt {
+			gpios = <&gpioa 3 GPIO_INPUT>;
+		};
+		smc-sdown-mecc {
+			gpios = <&gpiob 1 GPIO_INPUT>;
+		};
+		std-adpt-cntrl-gpio {
+			gpios = <&gpioc 3 GPIO_INPUT>;
+		};
+		sml1-alert {
+			gpios = <&gpioc 7 GPIO_INPUT>;
+		};
+		smc-onoff-n {
+			gpios = <&gpiod 2 GPIO_INPUT>;
+		};
+		suswarn {
+			gpios = <&gpiod 5 GPIO_INPUT>;
+		};
+		tp-gpiod6-ec {
+			gpios = <&gpiod 6 GPIO_INPUT>;
+		};
+		tp-gpiod7-ec {
+			gpios = <&gpiod 7 GPIO_INPUT>;
+		};
+		me-g3-to-m3-ec {
+			gpios = <&gpioe 0 GPIO_INPUT>;
+		};
+		gpio_ec_kso_02_inv: ec-kso-02-inv {
+			gpios = <&gpio1 7 (GPIO_OUTPUT_LOW | GPIO_ACTIVE_LOW)>;
+		};
+
+		usb_c0_bb_retimer_rst: usb-c0-bb-retimer-rst {
+			gpios = <&ioex_c0_port 0 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C0_BB_RETIMER_RST";
+		};
+		usb_c0_bb_retimer_ls_en: usb-c0-bb-retimer-ls-en {
+			gpios = <&ioex_c0_port 1 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C0_BB_RETIMER_LS_EN";
+		};
+		usb-c0-usb-mux-cntrl-1 {
+			gpios = <&ioex_c0_port 4 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C0_USB_MUX_CNTRL_1";
+		};
+		usb-c0-usb-mux-cntrl-0 {
+			gpios = <&ioex_c0_port 5 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C0_USB_MUX_CNTRL_0";
+		};
+		usb_c1_bb_retimer_rst: usb-c1-bb-retimer-rst {
+			gpios = <&ioex_c1_port 0 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C1_BB_RETIMER_RST";
+		};
+		usb_c1_bb_retimer_ls_en: usb-c1-bb-retimer-ls-en {
+			gpios = <&ioex_c1_port 1 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C1_BB_RETIMER_LS_EN";
+		};
+		usb-c1-hpd {
+			gpios = <&ioex_c1_port 2 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C1_HPD";
+		};
+		usb-c0-c1-oc {
+			gpios = <&ioex_c1_port 8 GPIO_OUTPUT_HIGH>;
+			enum-name = "IOEX_USB_C0_C1_OC";
+		};
+		usb_c2_bb_retimer_rst: usb-c2-bb-retimer-rst {
+			gpios = <&ioex_c2_port 0 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C2_BB_RETIMER_RST";
+		};
+		usb_c2_bb_retimer_ls_en: usb-c2-bb-retimer-ls-en {
+			gpios = <&ioex_c2_port 1 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C2_BB_RETIMER_LS_EN";
+		};
+		usb-c2-usb-mux-cntrl-1 {
+			gpios = <&ioex_c2_port 4 GPIO_OUTPUT_LOW>;
+		};
+		usb-c2-usb-mux-cntrl-0 {
+			gpios = <&ioex_c2_port 5 GPIO_OUTPUT_LOW>;
+		};
+		usb_c3_bb_retimer_rst: usb-c3-bb-retimer-rst {
+			gpios = <&ioex_c3_port 0 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C3_BB_RETIMER_RST";
+		};
+		usb_c3_bb_retimer_ls_en: usb-c3-bb-retimer-ls-en {
+			gpios = <&ioex_c3_port 1 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C3_BB_RETIMER_LS_EN";
+		};
+		usb-c2-c3-oc {
+			gpios = <&ioex_c3_port 8 GPIO_OUTPUT_HIGH>;
+			enum-name = "IOEX_USB_C2_C3_OC";
+		};
+		/* unimplemented GPIOs */
+		en-pp5000 {
+			enum-name = "GPIO_EN_PP5000";
+		};
+	};
+};
diff --git a/zephyr/program/intelrvp/adlrvp/adlrvp_npcx/interrupts.dts b/zephyr/program/intelrvp/adlrvp/adlrvp_npcx/interrupts.dts
new file mode 100644
index 0000000000..d7bb40fad2
--- /dev/null
+++ b/zephyr/program/intelrvp/adlrvp/adlrvp_npcx/interrupts.dts
@@ -0,0 +1,100 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/ {
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_lid_open: lid-open {
+			irq-pin = <&smc_lid>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "lid_interrupt";
+		};
+		int_power_button: power-button {
+			irq-pin = <&mech_pwr_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_button_interrupt";
+		};
+		int_ac_present: ac-present {
+			irq-pin = <&bc_acok>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "extpower_interrupt";
+		};
+		int_slp_s0: slp-s0 {
+			irq-pin = <&pch_slp_s0_n>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_slp_sus: slp-sus {
+			irq-pin = <&pm_slp_sus_ec_n>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_pg_dsw_pwrok: pg-dsw-pwrok {
+			irq-pin = <&vccpdsw_3p3>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_rsmrst_pwrgd: rsmrst-pwrgd {
+			irq-pin = <&rsmrst_pwrgd>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_all_sys_pwrgd: all-sys-pwrgd {
+			irq-pin = <&all_sys_pwrgd>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_usbc_tcpc_alrt_p0: usbc-tcpc-alrt-p0 {
+			irq-pin = <&usbc_tcpc_alrt_p0>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "tcpc_alert_event";
+		};
+		int_usbc_tcpc_alrt_p1: usbc-tcpc-alrt-p1 {
+			irq-pin = <&usbc_tcpc_alrt_p1>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "tcpc_alert_event";
+		};
+		int_usbc_tcpc_alrt_p2: usbc-tcpc-alrt-p2 {
+			irq-pin = <&usbc_tcpc_alrt_p2>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "tcpc_alert_event";
+		};
+		int_usbc_tcpc_alrt_p3: usbc-tcpc-alrt-p3 {
+			irq-pin = <&usbc_tcpc_alrt_p3>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "tcpc_alert_event";
+		};
+		int_usbc_tcpc_ppc_alrt_p0: usbc-tcpc-ppc-alrt-p0 {
+			irq-pin = <&usbc_tcpc_ppc_alrt_p0>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "ppc_interrupt";
+		};
+		int_usbc_tcpc_ppc_alrt_p1: usbc-tcpc-ppc-alrt-p1 {
+			irq-pin = <&usbc_tcpc_ppc_alrt_p1>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "ppc_interrupt";
+		};
+		int_usbc_tcpc_ppc_alrt_p2: usbc-tcpc-ppc-alrt-p2 {
+			irq-pin = <&usbc_tcpc_ppc_alrt_p2>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "ppc_interrupt";
+		};
+		int_usbc_tcpc_ppc_alrt_p3: usbc-tcpc-ppc-alrt-p3 {
+			irq-pin = <&usbc_tcpc_ppc_alrt_p3>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "ppc_interrupt";
+		};
+		int_std_adp_prsnt: std-adp-prsnt {
+			irq-pin = <&std_adp_prsnt>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "board_dc_jack_interrupt";
+		};
+		int_ccd_mode_odl: ccd-mode-odl {
+			irq-pin = <&ccd_mode_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "board_connect_c0_sbu";
+		};
+	};
+};
diff --git a/zephyr/program/intelrvp/adlrvp/adlrvp_npcx/keyboard.dts b/zephyr/program/intelrvp/adlrvp/adlrvp_npcx/keyboard.dts
new file mode 100644
index 0000000000..be0a570e95
--- /dev/null
+++ b/zephyr/program/intelrvp/adlrvp/adlrvp_npcx/keyboard.dts
@@ -0,0 +1,59 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	cros-keyscan {
+		compatible = "cros-ec,keyscan";
+
+		output-settle = <35>;
+		debounce-down = <5000>;
+		debounce-up = <40000>;
+		poll-timeout = <100000>;
+
+		actual-key-mask = <
+			0x14	/* C0 */
+			0xff	/* C1 */
+			0xff	/* C2 */
+			0xff	/* C3 */
+			0xff	/* C4 */
+			0xf5	/* C5 */
+			0xff	/* C6 */
+			0xa4	/* C7 */
+			0xff	/* C8 */
+			0xfe	/* C9 */
+			0x55	/* C10 */
+			0xfa	/* C11 */
+			0xca	/* C12 */
+			>;
+	};
+};
+
+&cros_kb_raw {
+	status = "okay";
+	/* No KSO2 (it's inverted and implemented by GPIO) */
+	pinctrl-0 = <
+		&ksi0_gp31
+		&ksi1_gp30
+		&ksi2_gp27
+		&ksi3_gp26
+		&ksi4_gp25
+		&ksi5_gp24
+		&ksi6_gp23
+		&ksi7_gp22
+		&kso00_gp21
+		&kso01_gp20
+		&kso03_gp16
+		&kso04_gp15
+		&kso05_gp14
+		&kso06_gp13
+		&kso07_gp12
+		&kso08_gp11
+		&kso09_gp10
+		&kso10_gp07
+		&kso11_gp06
+		&kso12_gp05
+	>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/intelrvp/adlrvp/adlrvp_npcx/prj.conf b/zephyr/program/intelrvp/adlrvp/adlrvp_npcx/prj.conf
new file mode 100644
index 0000000000..d04abada31
--- /dev/null
+++ b/zephyr/program/intelrvp/adlrvp/adlrvp_npcx/prj.conf
@@ -0,0 +1,13 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_BOARD_ADLRVP_NPCX=y
+CONFIG_CROS_SYSTEM_NPCX=y
+CONFIG_SYSCON=y
+
+# Charger
+CONFIG_PLATFORM_EC_DEDICATED_CHARGE_PORT=y
+
+# RTC
+CONFIG_PLATFORM_EC_RTC=y
diff --git a/zephyr/program/intelrvp/adlrvp/adlrvp_npcx/pwm_leds.dts b/zephyr/program/intelrvp/adlrvp/adlrvp_npcx/pwm_leds.dts
new file mode 100644
index 0000000000..eb1576dbff
--- /dev/null
+++ b/zephyr/program/intelrvp/adlrvp/adlrvp_npcx/pwm_leds.dts
@@ -0,0 +1,57 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	pwmleds {
+		compatible = "pwm-leds";
+		pwm_led0: pwm_led_0 {
+			pwms = <&pwm4 0 PWM_HZ(4800) PWM_POLARITY_INVERTED>;
+		};
+		pwm_led1: pwm_led_1 {
+			pwms = <&pwm5 0 PWM_HZ(4800) PWM_POLARITY_INVERTED>;
+		};
+	};
+
+	cros-pwmleds {
+		compatible = "cros-ec,pwm-leds";
+
+		leds = <&pwm_led0 &pwm_led1>;
+
+		color-map-green  = <100>;
+
+		/* brightness-range = <red green blue yellow white amber> */
+		brightness-range = <0 100 0 0 0 0>;
+
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pwm_led_0@0 {
+			reg = <0>;
+			ec-led-name = "EC_LED_ID_BATTERY_LED";
+		};
+
+		pwm_led_1@1 {
+			reg = <1>;
+			ec-led-name = "EC_LED_ID_POWER_LED";
+		};
+	};
+};
+
+/* LED1 */
+&pwm4 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm4_gpb6>;
+	pinctrl-names = "default";
+};
+
+/* LED2 */
+&pwm5 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm5_gpb7>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/intelrvp/adlrvp/adlrvp_npcx/temp_sensor.dts b/zephyr/program/intelrvp/adlrvp/adlrvp_npcx/temp_sensor.dts
new file mode 100644
index 0000000000..93ecaa02f6
--- /dev/null
+++ b/zephyr/program/intelrvp/adlrvp/adlrvp_npcx/temp_sensor.dts
@@ -0,0 +1,89 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <cros/thermistor/thermistor.dtsi>
+
+/ {
+	temp_ambient: ambient {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V0_22K6_47K_4050B>;
+		adc = <&adc_ambient>;
+	};
+	temp_ddr: ddr {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V0_22K6_47K_4050B>;
+		adc = <&adc_ddr>;
+	};
+	temp_skin: skin {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V0_22K6_47K_4050B>;
+		adc = <&adc_skin>;
+	};
+	temp_vr: vr {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V0_22K6_47K_4050B>;
+		adc = <&adc_vr>;
+	};
+
+	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
+		ambient {
+			temp_fan_off = <15>;
+			temp_fan_max = <50>;
+			temp_host_high = <75>;
+			temp_host_halt = <80>;
+			temp_host_release_high = <65>;
+			sensor = <&temp_ambient>;
+		};
+
+		/*
+		 * TDB: battery temp read api is not using thermistor and
+		 * zephyr shim layer doesn't support to configure custom read
+		 * function.
+		 *
+		 * battery {
+		 *	compatible = "cros-ec,temp-sensor-thermistor",
+		 *		     "cros-ec,temp-sensor";
+		 *	thermistor = < >;
+		 *	enum-name = "";
+		 *	temp_fan_off = <15>;
+		 *	temp_fan_max = <50>;
+		 *	temp_host_high = <75>;
+		 *	temp_host_halt = <80>;
+		 *	temp_host_release_high = <65>;
+		 *	adc = <&adc_battery>;
+		 * };
+		 */
+
+		ddr {
+			temp_fan_off = <15>;
+			temp_fan_max = <50>;
+			temp_host_high = <75>;
+			temp_host_halt = <80>;
+			temp_host_release_high = <65>;
+			sensor = <&temp_ddr>;
+		};
+		skin {
+			temp_fan_off = <15>;
+			temp_fan_max = <50>;
+			temp_host_high = <75>;
+			temp_host_halt = <80>;
+			temp_host_release_high = <65>;
+			sensor = <&temp_skin>;
+		};
+		vr {
+			temp_fan_off = <15>;
+			temp_fan_max = <50>;
+			temp_host_high = <75>;
+			temp_host_halt = <80>;
+			temp_host_release_high = <65>;
+			sensor = <&temp_vr>;
+		};
+	};
+};
+
+&thermistor_3V0_22K6_47K_4050B {
+	status = "okay";
+};
diff --git a/zephyr/program/intelrvp/adlrvp/adlrvp_npcx/usbc.dts b/zephyr/program/intelrvp/adlrvp/adlrvp_npcx/usbc.dts
new file mode 100644
index 0000000000..615364b9c9
--- /dev/null
+++ b/zephyr/program/intelrvp/adlrvp/adlrvp_npcx/usbc.dts
@@ -0,0 +1,93 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		usbc_port0: port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+			tcpc = <&tcpc_port0>;
+			ppc = <&ppc_port0>;
+			chg = <&charger>;
+			usb_mux_chain_0: usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_c0_bb_retimer
+					     &virtual_mux_c0>;
+			};
+			usb_mux_alt_chain_0: usb-mux-alt-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				alternative-chain;
+				usb-muxes = <&usb_c0_bb_retimer
+					     &usb_c0_soc_side_bb_retimer
+					     &virtual_mux_c0>;
+			};
+		};
+		port0-muxes {
+			virtual_mux_c0: virtual-mux-c0 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+
+		usbc_port1: port1@1 {
+			compatible = "named-usbc-port";
+			reg = <1>;
+			tcpc = <&tcpc_port1>;
+			ppc = <&ppc_port1>;
+			usb_mux_chain_1: usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_c1_bb_retimer
+					     &virtual_mux_c1>;
+			};
+			usb_mux_alt_chain_1: usb-mux-alt-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				alternative-chain;
+				usb-muxes = <&usb_c1_bb_retimer
+					     &usb_c1_soc_side_bb_retimer
+					     &virtual_mux_c1>;
+			};
+		};
+		port1-muxes {
+			virtual_mux_c1: virtual-mux-c1 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+
+		port2@2 {
+			compatible = "named-usbc-port";
+			reg = <2>;
+			tcpc = <&tcpc_port2>;
+			ppc = <&ppc_port2>;
+			usb_mux_chain_2: usb-mux-chain-2 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_c2_bb_retimer
+					     &virtual_mux_c2>;
+			};
+		};
+		port2-muxes {
+			virtual_mux_c2: virtual-mux-c2 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+
+		port3@3 {
+			compatible = "named-usbc-port";
+			reg = <3>;
+			tcpc = <&tcpc_port3>;
+			ppc = <&ppc_port3>;
+			usb_mux_chain_3: usb-mux-chain-3 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_c3_bb_retimer
+					     &virtual_mux_c3>;
+			};
+		};
+		port3-muxes {
+			virtual_mux_c3: virtual-mux-c3 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+	};
+};
diff --git a/zephyr/program/intelrvp/adlrvp/battery.dts b/zephyr/program/intelrvp/adlrvp/battery.dts
new file mode 100644
index 0000000000..1de4111791
--- /dev/null
+++ b/zephyr/program/intelrvp/adlrvp/battery.dts
@@ -0,0 +1,20 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	aliases {
+		getac-3s = &default_battery;
+		getac-2s = &getac_smp_hhp_408_2s;
+	};
+
+	batteries {
+		default_battery: getac-smp-hhp-408-3s {
+			compatible = "getac,bq40z50-R3-S3", "battery-smart";
+		};
+		getac_smp_hhp_408_2s: getac-smp-hhp-408-2s {
+			compatible = "getac,bq40z50-R3-S2", "battery-smart";
+		};
+	};
+};
diff --git a/zephyr/program/intelrvp/adlrvp/include/adlrvp_zephyr.h b/zephyr/program/intelrvp/adlrvp/include/adlrvp_zephyr.h
new file mode 100644
index 0000000000..135fd4ef4f
--- /dev/null
+++ b/zephyr/program/intelrvp/adlrvp/include/adlrvp_zephyr.h
@@ -0,0 +1,58 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel ADL-RVP specific configuration */
+
+#ifndef __ADLRVP_BOARD_H
+#define __ADLRVP_BOARD_H
+
+#include "config.h"
+
+#define I2C_ADDR_FUSB302_TCPC_AIC 0x22
+#define I2C_ADDR_SN5S330_TCPC_AIC_PPC 0x40
+
+#define I2C_ADDR_PCA9675_TCPC_AIC_IOEX 0x21
+
+/* SOC side BB retimers (dual retimer config) */
+#define I2C_PORT0_BB_RETIMER_SOC_ADDR 0x54
+#if defined(HAS_TASK_PD_C1)
+#define I2C_PORT1_BB_RETIMER_SOC_ADDR 0x55
+#endif
+
+#define ADLM_LP4_RVP1_SKU_BOARD_ID 0x01
+#define ADLM_LP5_RVP2_SKU_BOARD_ID 0x02
+#define ADLM_LP5_RVP3_SKU_BOARD_ID 0x03
+#define ADLN_LP5_ERB_SKU_BOARD_ID 0x06
+#define ADLN_LP5_RVP_SKU_BOARD_ID 0x07
+#define ADLP_DDR5_RVP_SKU_BOARD_ID 0x12
+#define ADLP_LP5_T4_RVP_SKU_BOARD_ID 0x13
+#define ADL_RVP_BOARD_ID(id) ((id)&0x3F)
+
+#define CONFIG_BATTERY_TYPE_NO_AUTO_DETECT
+
+enum adlrvp_charge_ports {
+	TYPE_C_PORT_0,
+#if defined(HAS_TASK_PD_C1)
+	TYPE_C_PORT_1,
+#endif
+#if defined(HAS_TASK_PD_C2)
+	TYPE_C_PORT_2,
+#endif
+#if defined(HAS_TASK_PD_C3)
+	TYPE_C_PORT_3,
+#endif
+};
+
+enum ioex_port {
+	IOEX_C0_PCA9675,
+	IOEX_C1_PCA9675,
+#if defined(HAS_TASK_PD_C2)
+	IOEX_C2_PCA9675,
+	IOEX_C3_PCA9675,
+#endif
+	IOEX_PORT_COUNT
+};
+
+#endif /* __ADLRVP_BOARD_H */
diff --git a/zephyr/program/intelrvp/adlrvp/ioex.dts b/zephyr/program/intelrvp/adlrvp/ioex.dts
new file mode 100644
index 0000000000..3e2227dacb
--- /dev/null
+++ b/zephyr/program/intelrvp/adlrvp/ioex.dts
@@ -0,0 +1,78 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	/* IOEX_C0_PCA9675 */
+	ioex-c0 {
+		compatible = "cros,ioex-chip";
+		i2c-port = <&typec_0>;
+		i2c-addr = <0x21>;
+		drv = "pca9675_ioexpander_drv";
+		flags = <0x00>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		ioex_c0_port: ioex-c0-port@0 {
+			compatible = "cros,ioex-port";
+			reg = <0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <16>;
+		};
+	};
+
+	/* IOEX_C1_PCA9675 */
+	ioex-c1 {
+		compatible = "cros,ioex-chip";
+		i2c-port = <&typec_1>;
+		i2c-addr = <0x21>;
+		drv = "pca9675_ioexpander_drv";
+		flags = <0x00>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		ioex_c1_port: ioex-c1-port@0 {
+			compatible = "cros,ioex-port";
+			reg = <0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <16>;
+		};
+	};
+
+	/* IOEX_C2_PCA9675 */
+	ioex-c2 {
+		compatible = "cros,ioex-chip";
+		i2c-port = <&typec_2>;
+		i2c-addr = <0x21>;
+		drv = "pca9675_ioexpander_drv";
+		flags = <0x00>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		ioex_c2_port: ioex-c2-port@0 {
+			compatible = "cros,ioex-port";
+			reg = <0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <16>;
+		};
+	};
+
+	/* IOEX_C3_PCA9675 */
+	ioex-c3 {
+		compatible = "cros,ioex-chip";
+		i2c-port = <&typec_3>;
+		i2c-addr = <0x21>;
+		drv = "pca9675_ioexpander_drv";
+		flags = <0x00>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		ioex_c3_port: ioex-c3-port@0 {
+			compatible = "cros,ioex-port";
+			reg = <0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <16>;
+		};
+	};
+};
diff --git a/zephyr/program/intelrvp/adlrvp/prj.conf b/zephyr/program/intelrvp/adlrvp/prj.conf
new file mode 100644
index 0000000000..c09beb8da5
--- /dev/null
+++ b/zephyr/program/intelrvp/adlrvp/prj.conf
@@ -0,0 +1,59 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Power Sequencing
+CONFIG_AP_X86_INTEL_TGL=y
+CONFIG_PLATFORM_EC_POWERSEQ_SLP_S3_L_OVERRIDE=n
+CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n
+CONFIG_PLATFORM_EC_POWERSEQ_ICELAKE=y
+
+# Battery
+CONFIG_PLATFORM_EC_BATTERY_TYPE_NO_AUTO_DETECT=y
+CONFIG_PLATFORM_EC_BATTERY_V2=y
+
+# BC1.2
+CONFIG_PLATFORM_EC_USB_CHARGER=n
+
+# CBI
+CONFIG_EEPROM=y
+
+# Charger
+CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=5
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=10
+CONFIG_PLATFORM_EC_CHARGE_RAMP_HW=n
+CONFIG_PLATFORM_EC_CHARGER_BQ25720=y
+CONFIG_PLATFORM_EC_CHARGER_BQ25720_VSYS_TH2_CUSTOM=y
+CONFIG_PLATFORM_EC_CHARGER_BQ25720_VSYS_TH2_DV=70
+CONFIG_PLATFORM_EC_CHARGER_ISL9241=y
+CONFIG_PLATFORM_EC_CHARGER_RUNTIME_CONFIG=y
+
+# LED
+CONFIG_PLATFORM_EC_LED_COMMON=y
+CONFIG_PLATFORM_EC_LED_PWM_TASK_DISABLED=y
+
+# Temperature sensors
+CONFIG_PLATFORM_EC_TEMP_SENSOR_POWER=y
+
+# USB-C and PD
+CONFIG_PLATFORM_EC_USB_DRP_ACC_TRYSRC=y
+CONFIG_PLATFORM_EC_USB_PD_DUAL_ROLE_AUTO_TOGGLE=n
+CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_CHARGER=y
+CONFIG_PLATFORM_EC_USB_PD_TCPC_RUNTIME_CONFIG=n
+CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_BB_RUNTIME_CONFIG=n
+CONFIG_PLATFORM_EC_USB_MUX_TUSB1044=y
+CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y
+CONFIG_PLATFORM_EC_USB_PD_REV30=y
+CONFIG_PLATFORM_EC_USB_PD_USB32_DRD=y
+CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=y
+CONFIG_PLATFORM_EC_USB_PD_USB4=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_MUX=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_PPC=y
+CONFIG_PLATFORM_EC_USBC_PPC_SN5S330=y
+
+# IOEX
+CONFIG_PLATFORM_EC_IOEX_PCA9675=y
+
+# eSPI
+CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US=150
diff --git a/zephyr/program/intelrvp/adlrvp/src/adlrvp.c b/zephyr/program/intelrvp/adlrvp/src/adlrvp.c
new file mode 100644
index 0000000000..e53dbf560a
--- /dev/null
+++ b/zephyr/program/intelrvp/adlrvp/src/adlrvp.c
@@ -0,0 +1,396 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* TODO: b/218904113: Convert to using Zephyr GPIOs */
+#include "adlrvp_zephyr.h"
+#include "battery.h"
+#include "battery_fuel_gauge.h"
+#include "bq25710.h"
+#include "charger.h"
+#include "common.h"
+#include "console.h"
+#include "driver/retimer/bb_retimer_public.h"
+#include "extpower.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "intel_rvp_board_id.h"
+#include "intelrvp.h"
+#include "ioexpander.h"
+#include "isl9241.h"
+#include "power/icelake.h"
+#include "sn5s330.h"
+#include "system.h"
+#include "task.h"
+#include "tusb1064.h"
+#include "usb_mux.h"
+#include "usbc/usb_muxes.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ##args)
+
+/* TCPC AIC GPIO Configuration */
+const struct tcpc_aic_gpio_config_t tcpc_aic_gpios[] = {
+	[TYPE_C_PORT_0] = {
+		.tcpc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_alrt_p0)),
+		.ppc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_ppc_alrt_p0)),
+		.ppc_intr_handler = sn5s330_interrupt,
+	},
+#if defined(HAS_TASK_PD_C1)
+	[TYPE_C_PORT_1] = {
+		.tcpc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_alrt_p1)),
+		.ppc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_ppc_alrt_p1)),
+		.ppc_intr_handler = sn5s330_interrupt,
+	},
+#endif
+#if defined(HAS_TASK_PD_C2)
+	[TYPE_C_PORT_2] = {
+		.tcpc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_alrt_p2)),
+		.ppc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_ppc_alrt_p2)),
+		.ppc_intr_handler = sn5s330_interrupt,
+	},
+#endif
+#if defined(HAS_TASK_PD_C3)
+	[TYPE_C_PORT_3] = {
+		.tcpc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_alrt_p3)),
+		.ppc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_ppc_alrt_p3)),
+		.ppc_intr_handler = sn5s330_interrupt,
+	},
+#endif
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_aic_gpios) == CONFIG_USB_PD_PORT_MAX_COUNT);
+
+/* Cache BB retimer power state */
+static bool cache_bb_enable[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+void board_overcurrent_event(int port, int is_overcurrented)
+{
+	/* Port 0 & 1 and 2 & 3 share same line for over current indication */
+#if defined(HAS_TASK_PD_C2)
+	enum ioex_signal oc_signal = port < TYPE_C_PORT_2 ? IOEX_USB_C0_C1_OC :
+							    IOEX_USB_C2_C3_OC;
+#else
+	enum ioex_signal oc_signal = IOEX_USB_C0_C1_OC;
+#endif
+
+	/* Overcurrent indication is active low signal */
+	ioex_set_level(oc_signal, is_overcurrented ? 0 : 1);
+}
+
+__override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
+{
+	/*
+	 * ADL-P-DDR5 RVP SKU has cascaded retimer topology.
+	 * Ports with cascaded retimers share common load switch and reset pin
+	 * hence no need to set the power state again if the 1st retimer's power
+	 * status has already changed.
+	 */
+	if (cache_bb_enable[me->usb_port] == enable)
+		return EC_SUCCESS;
+
+	cache_bb_enable[me->usb_port] = enable;
+
+	/* Handle retimer's power domain.*/
+	if (enable) {
+		ioex_set_level(bb_controls[me->usb_port].usb_ls_en_gpio, 1);
+
+		/*
+		 * minimum time from VCC to RESET_N de-assertion is 100us
+		 * For boards that don't provide a load switch control, the
+		 * retimer_init() function ensures power is up before calling
+		 * this function.
+		 */
+		msleep(1);
+		ioex_set_level(bb_controls[me->usb_port].retimer_rst_gpio, 1);
+
+		/*
+		 * Allow 1ms time for the retimer to power up lc_domain
+		 * which powers I2C controller within retimer
+		 */
+		msleep(1);
+
+	} else {
+		ioex_set_level(bb_controls[me->usb_port].retimer_rst_gpio, 0);
+		msleep(1);
+		ioex_set_level(bb_controls[me->usb_port].usb_ls_en_gpio, 0);
+	}
+	return EC_SUCCESS;
+}
+
+static void board_connect_c0_sbu_deferred(void)
+{
+	int ccd_intr_level = gpio_get_level(GPIO_CCD_MODE_ODL);
+
+	if (ccd_intr_level) {
+		/* Default set the SBU lines to AUX mode on TCPC-AIC */
+		ioex_set_level(IOEX_USB_C0_USB_MUX_CNTRL_1, 0);
+		ioex_set_level(IOEX_USB_C0_USB_MUX_CNTRL_0, 0);
+	} else {
+		/* Set the SBU lines to CCD mode on TCPC-AIC */
+		ioex_set_level(IOEX_USB_C0_USB_MUX_CNTRL_1, 1);
+		ioex_set_level(IOEX_USB_C0_USB_MUX_CNTRL_0, 0);
+	}
+}
+DECLARE_DEFERRED(board_connect_c0_sbu_deferred);
+
+void board_connect_c0_sbu(enum gpio_signal s)
+{
+	hook_call_deferred(&board_connect_c0_sbu_deferred_data, 0);
+}
+
+static void enable_h1_irq(void)
+{
+	gpio_enable_interrupt(GPIO_CCD_MODE_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, enable_h1_irq, HOOK_PRIO_LAST);
+
+void set_charger_system_voltage(void)
+{
+	switch (ADL_RVP_BOARD_ID(board_get_version())) {
+	case ADLN_LP5_ERB_SKU_BOARD_ID:
+	case ADLN_LP5_RVP_SKU_BOARD_ID:
+		/*
+		 * As per b:196184163 configure the PPVAR_SYS depend
+		 * on AC or AC+battery
+		 */
+		if (extpower_is_present() && battery_is_present()) {
+			bq25710_set_min_system_voltage(
+				CHARGER_SOLO, battery_get_info()->voltage_min);
+		} else {
+			bq25710_set_min_system_voltage(
+				CHARGER_SOLO, battery_get_info()->voltage_max);
+		}
+		break;
+
+	/* Add additional board SKUs */
+	default:
+		break;
+	}
+}
+DECLARE_HOOK(HOOK_AC_CHANGE, set_charger_system_voltage, HOOK_PRIO_DEFAULT);
+
+static void configure_charger(void)
+{
+	switch (ADL_RVP_BOARD_ID(board_get_version())) {
+	case ADLN_LP5_ERB_SKU_BOARD_ID:
+	case ADLN_LP5_RVP_SKU_BOARD_ID:
+		/* charger chip BQ25720 support */
+		chg_chips[0].i2c_addr_flags = BQ25710_SMBUS_ADDR1_FLAGS;
+		chg_chips[0].drv = &bq25710_drv;
+		set_charger_system_voltage();
+		break;
+
+	/* Add additional board SKUs */
+	default:
+		break;
+	}
+}
+
+static void configure_retimer_usbmux(void)
+{
+	struct usb_mux *mux;
+
+	switch (ADL_RVP_BOARD_ID(board_get_version())) {
+	case ADLN_LP5_ERB_SKU_BOARD_ID:
+	case ADLN_LP5_RVP_SKU_BOARD_ID:
+		/* enable TUSB1044RNQR redriver on Port0  */
+		mux = USB_MUX_POINTER(DT_NODELABEL(usb_mux_chain_0), 0);
+		mux->i2c_addr_flags = TUSB1064_I2C_ADDR14_FLAGS;
+		mux->driver = &tusb1064_usb_mux_driver;
+		mux->hpd_update = tusb1044_hpd_update;
+
+#if defined(HAS_TASK_PD_C1)
+		mux = USB_MUX_POINTER(DT_NODELABEL(usb_mux_chain_1), 0);
+		mux->driver = NULL;
+		mux->hpd_update = NULL;
+#endif
+		break;
+
+	case ADLP_LP5_T4_RVP_SKU_BOARD_ID:
+		/* No retimer on Port-2 */
+#if defined(HAS_TASK_PD_C2)
+		mux = USB_MUX_POINTER(DT_NODELABEL(usb_mux_chain_2), 0);
+		mux->driver = NULL;
+#endif
+		break;
+
+	case ADLP_DDR5_RVP_SKU_BOARD_ID:
+		/*
+		 * ADL-P-DDR5 RVP has dual BB-retimers for port0 & port1.
+		 * Change the default usb mux config on runtime to support
+		 * dual retimer topology.
+		 */
+		USB_MUX_ENABLE_ALTERNATIVE(usb_mux_alt_chain_0);
+#if defined(HAS_TASK_PD_C1)
+		USB_MUX_ENABLE_ALTERNATIVE(usb_mux_alt_chain_1);
+#endif
+		break;
+
+		/* Add additional board SKUs */
+
+	default:
+		break;
+	}
+}
+
+static void configure_battery_type(void)
+{
+	int bat_cell_type;
+
+	switch (ADL_RVP_BOARD_ID(board_get_version())) {
+	case ADLM_LP4_RVP1_SKU_BOARD_ID:
+	case ADLM_LP5_RVP2_SKU_BOARD_ID:
+	case ADLM_LP5_RVP3_SKU_BOARD_ID:
+	case ADLN_LP5_ERB_SKU_BOARD_ID:
+	case ADLN_LP5_RVP_SKU_BOARD_ID:
+		/* configure Battery to 2S based */
+		bat_cell_type = BATTERY_TYPE(DT_ALIAS(getac_2s));
+		break;
+	default:
+		/* configure Battery to 3S based */
+		bat_cell_type = BATTERY_TYPE(DT_ALIAS(getac_3s));
+		break;
+	}
+
+	/* Set the fixed battery type */
+	battery_set_fixed_battery_type(bat_cell_type);
+}
+/******************************************************************************/
+/* PWROK signal configuration */
+/*
+ * On ADLRVP, SYS_PWROK_EC is an output controlled by EC and uses ALL_SYS_PWRGD
+ * as input.
+ */
+const struct intel_x86_pwrok_signal pwrok_signal_assert_list[] = {
+	{
+		.gpio = GPIO_PCH_SYS_PWROK,
+		.delay_ms = 3,
+	},
+};
+const int pwrok_signal_assert_count = ARRAY_SIZE(pwrok_signal_assert_list);
+
+const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[] = {
+	{
+		.gpio = GPIO_PCH_SYS_PWROK,
+	},
+};
+const int pwrok_signal_deassert_count = ARRAY_SIZE(pwrok_signal_deassert_list);
+
+/*
+ * Returns board information (board id[7:0] and Fab id[15:8]) on success
+ * -1 on error.
+ */
+__override int board_get_version(void)
+{
+	/* Cache the board ID */
+	static int adlrvp_board_id;
+
+	int i;
+	int rv = EC_ERROR_UNKNOWN;
+
+	int fab_id, board_id, bom_id;
+
+	/* Board ID is already read */
+	if (adlrvp_board_id)
+		return adlrvp_board_id;
+
+	/*
+	 * IOExpander that has Board ID information is on DSW-VAL rail on
+	 * ADL RVP. On cold boot cycles, DSW-VAL rail is taking time to settle.
+	 * This loop retries to ensure rail is settled and read is successful
+	 */
+	for (i = 0; i < RVP_VERSION_READ_RETRY_CNT; i++) {
+		rv = gpio_pin_get_dt(&bom_id_config[0]);
+
+		if (rv >= 0)
+			break;
+
+		k_msleep(1);
+	}
+
+	/* retrun -1 if failed to read board id */
+	if (rv < 0)
+		return -1;
+
+	/*
+	 * BOM ID [2]   : IOEX[0]
+	 * BOM ID [1:0] : IOEX[15:14]
+	 */
+	bom_id = gpio_pin_get_dt(&bom_id_config[0]) << 2;
+	bom_id |= gpio_pin_get_dt(&bom_id_config[1]) << 1;
+	bom_id |= gpio_pin_get_dt(&bom_id_config[2]);
+
+	/*
+	 * FAB ID [1:0] : IOEX[2:1] + 1
+	 */
+	fab_id = gpio_pin_get_dt(&fab_id_config[0]) << 1;
+	fab_id |= gpio_pin_get_dt(&fab_id_config[1]);
+	fab_id += 1;
+
+	/*
+	 * BOARD ID[5:0] : IOEX[13:8]
+	 */
+	board_id = gpio_pin_get_dt(&board_id_config[0]) << 5;
+	board_id |= gpio_pin_get_dt(&board_id_config[1]) << 4;
+	board_id |= gpio_pin_get_dt(&board_id_config[2]) << 3;
+	board_id |= gpio_pin_get_dt(&board_id_config[3]) << 2;
+	board_id |= gpio_pin_get_dt(&board_id_config[4]) << 1;
+	board_id |= gpio_pin_get_dt(&board_id_config[5]);
+
+	CPRINTF("BID:0x%x, FID:0x%x, BOM:0x%x", board_id, fab_id, bom_id);
+
+	adlrvp_board_id = board_id | (fab_id << 8);
+	return adlrvp_board_id;
+}
+
+__override bool board_is_tbt_usb4_port(int port)
+{
+	bool tbt_usb4 = true;
+
+	switch (ADL_RVP_BOARD_ID(board_get_version())) {
+	case ADLN_LP5_ERB_SKU_BOARD_ID:
+	case ADLN_LP5_RVP_SKU_BOARD_ID:
+		/* No retimer on both ports */
+		tbt_usb4 = false;
+		break;
+
+	case ADLP_LP5_T4_RVP_SKU_BOARD_ID:
+		/* No retimer on Port-2 hence no platform level AUX & LSx mux */
+#if defined(HAS_TASK_PD_C2)
+		if (port == TYPE_C_PORT_2)
+			tbt_usb4 = false;
+#endif
+		break;
+
+	/* Add additional board SKUs */
+	default:
+		break;
+	}
+
+	return tbt_usb4;
+}
+
+static int board_pre_task_peripheral_init(void)
+{
+	/* Initialized IOEX-0 to access IOEX-GPIOs needed pre-task */
+	ioex_init(IOEX_C0_PCA9675);
+
+	/* Make sure SBU are routed to CCD or AUX based on CCD status at init */
+	board_connect_c0_sbu_deferred();
+
+	/* Configure battery type */
+	configure_battery_type();
+
+	/* Reconfigure board specific charger drivers */
+	configure_charger();
+
+	/* Configure board specific retimer & mux */
+	configure_retimer_usbmux();
+
+	return 0;
+}
+SYS_INIT(board_pre_task_peripheral_init, APPLICATION,
+	 CONFIG_APPLICATION_INIT_PRIORITY);
diff --git a/zephyr/program/intelrvp/include/intel_rvp_board_id.h b/zephyr/program/intelrvp/include/intel_rvp_board_id.h
new file mode 100644
index 0000000000..7825b272e3
--- /dev/null
+++ b/zephyr/program/intelrvp/include/intel_rvp_board_id.h
@@ -0,0 +1,17 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __INTEL_RVP_BOARD_ID_H
+#define __INTEL_RVP_BOARD_ID_H
+
+#include <zephyr/drivers/gpio.h>
+
+extern const struct gpio_dt_spec bom_id_config[];
+
+extern const struct gpio_dt_spec fab_id_config[];
+
+extern const struct gpio_dt_spec board_id_config[];
+
+#endif /* __INTEL_RVP_BOARD_ID_H */
diff --git a/zephyr/program/intelrvp/include/intelrvp.h b/zephyr/program/intelrvp/include/intelrvp.h
new file mode 100644
index 0000000000..b4ec65900c
--- /dev/null
+++ b/zephyr/program/intelrvp/include/intelrvp.h
@@ -0,0 +1,34 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#ifndef __INTELRVP_BOARD_H
+#define __INTELRVP_BOARD_H
+
+#include "compiler.h"
+#include "gpio_signal.h"
+#include "stdbool.h"
+
+/* RVP ID read retry count */
+#define RVP_VERSION_READ_RETRY_CNT 2
+
+#define DC_JACK_MAX_VOLTAGE_MV 19000
+
+FORWARD_DECLARE_ENUM(tcpc_rp_value);
+
+struct tcpc_aic_gpio_config_t {
+	/* TCPC interrupt */
+	enum gpio_signal tcpc_alert;
+	/* PPC interrupt */
+	enum gpio_signal ppc_alert;
+	/* PPC interrupt handler */
+	void (*ppc_intr_handler)(int port);
+};
+extern const struct tcpc_aic_gpio_config_t tcpc_aic_gpios[];
+
+void board_charging_enable(int port, int enable);
+void board_vbus_enable(int port, int enable);
+void board_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp);
+void board_dc_jack_interrupt(enum gpio_signal signal);
+bool is_typec_port(int port);
+#endif /* __INTELRVP_BOARD_H */
diff --git a/zephyr/program/intelrvp/led.md b/zephyr/program/intelrvp/led.md
new file mode 100644
index 0000000000..c36bc6b36c
--- /dev/null
+++ b/zephyr/program/intelrvp/led.md
@@ -0,0 +1,44 @@
+## LED behavior on Intel RVP
+
+There are two LEDs on RVP, they represent battery and charger status
+respectively.
+
+LED         | Description
+------------|------------------------
+CHARGER_LED | Represent charger state
+BATTERY_LED | Represent battery state
+
+LEDs on RVP emit a single color (green). Rather than just using the on and off
+state of the LED, PWM is used to blink the LED to represent multiple states and
+the below table represents the multiple LED states.
+
+LED State      | Description
+---------------|------------------------------
+LED_ON         | Switch On using gpio/pwmduty
+LED_OFF        | Switch Off using gpio/pwmduty
+LED_FLASH_SLOW | Flashing with 2 sec period
+LED_FLASH_FAST | Flashing with 250ms period
+
+### LED Behavior : Charger
+
+CHARGER_LED is dedicated to represent Charger status and the below table
+represents the LED states for the Charger.
+
+Charger Status       | LED States
+---------------------|---------------
+Charging             | LED_ON
+Discharging          | LED_FLASH_SLOW
+Charging error       | LED_FLASH_FAST
+No Charger Connected | LED_OFF
+
+### LED Behavior : Battery
+
+BATTERY_LED is dedicated to represent Battery status and the below table
+represents the LED states for the Battery.
+
+Battery Status              | LED States
+----------------------------|---------------
+Battery Low (<10%)          | LED_FLASH_FAST
+Battery Normal (10% to 90%) | LED_FLASH_SLOW
+Battery Full (>90%)         | LED_ON
+Battery Not Present         | LED_OFF
diff --git a/zephyr/program/intelrvp/legacy_ec_pwrseq.conf b/zephyr/program/intelrvp/legacy_ec_pwrseq.conf
new file mode 100644
index 0000000000..331afb637d
--- /dev/null
+++ b/zephyr/program/intelrvp/legacy_ec_pwrseq.conf
@@ -0,0 +1,12 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Legacy EC Power Sequencing Common Config
+CONFIG_PLATFORM_EC_POWERSEQ=y
+CONFIG_PLATFORM_EC_POWERSEQ_HOST_SLEEP=y
+CONFIG_PLATFORM_EC_POWERSEQ_INTEL=y
+CONFIG_PLATFORM_EC_POWERSEQ_RSMRST_DELAY=y
+CONFIG_PLATFORM_EC_POWERSEQ_S0IX=y
+CONFIG_PLATFORM_EC_POWERSEQ_S4=y
+CONFIG_PLATFORM_EC_THROTTLE_AP=y
diff --git a/zephyr/program/intelrvp/mtlrvp/CMakeLists.txt b/zephyr/program/intelrvp/mtlrvp/CMakeLists.txt
new file mode 100644
index 0000000000..c6729af776
--- /dev/null
+++ b/zephyr/program/intelrvp/mtlrvp/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+zephyr_library_sources("src/mtlrvp.c")
+zephyr_library_sources("src/board_power.c")
diff --git a/zephyr/program/intelrvp/mtlrvp/ioex.dts b/zephyr/program/intelrvp/mtlrvp/ioex.dts
new file mode 100644
index 0000000000..7d2f4b5820
--- /dev/null
+++ b/zephyr/program/intelrvp/mtlrvp/ioex.dts
@@ -0,0 +1,71 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	/* IOEX_KBD_GPIO IT8801 */
+	ioex-kbd-gpio {
+		compatible = "cros,ioex-chip";
+		i2c-port = <&i2c_charger>;
+		i2c-addr = <0x39>;
+		drv = "it8801_ioexpander_drv";
+		flags = <0x00>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ioex_it8801_port0: it8801_port@0 {
+			compatible = "cros,ioex-port";
+			reg = <0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <8>;
+		};
+
+		ioex_it8801_port1: it8801_port@1 {
+			compatible = "cros,ioex-port";
+			reg = <1>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <8>;
+		};
+	};
+	/* IOEX_C2_CCGXXF */
+	ioex-c2 {
+		compatible = "cros,ioex-chip";
+		i2c-port = <&typec_aic2>;
+		i2c-addr = <0x0B>;
+		drv = "ccgxxf_ioexpander_drv";
+		flags = <0x00>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		ioex_c2_port0: ioex-c2-port@0 {
+			compatible = "cros,ioex-port";
+			reg = <0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <8>;
+		};
+		ioex_c2_port1: ioex-c2-port@1 {
+			compatible = "cros,ioex-port";
+			reg = <1>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <8>;
+		};
+		ioex_c2_port2: ioex-c2-port@2 {
+			compatible = "cros,ioex-port";
+			reg = <2>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <8>;
+		};
+		ioex_c2_port3: ioex-c2-port@3 {
+			compatible = "cros,ioex-port";
+			reg = <3>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <8>;
+		};
+	};
+};
diff --git a/zephyr/program/intelrvp/mtlrvp/mtlrvpp_mchp/fan.dts b/zephyr/program/intelrvp/mtlrvp/mtlrvpp_mchp/fan.dts
new file mode 100644
index 0000000000..5ec3b53413
--- /dev/null
+++ b/zephyr/program/intelrvp/mtlrvp/mtlrvpp_mchp/fan.dts
@@ -0,0 +1,36 @@
+/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	fans {
+		compatible = "cros-ec,fans";
+
+		fan_0 {
+			pwms = <&pwm8 0 PWM_KHZ(30) PWM_POLARITY_NORMAL>;
+			rpm_min = <3200>;
+			rpm_start = <2200>;
+			rpm_max = <6600>;
+			tach = <&tach0>;
+			pgood_gpio = <&all_sys_pwrgd>;
+			enable_gpio = <&gpio_fan_control>;
+		};
+	};
+};
+
+/* Tachemeter for fan speed measurement */
+&tach0 {
+	status = "okay";
+	pinctrl-0 = <&tach0_gpio050>; /* TACH0 input on GPI050 */
+	pinctrl-names = "default";
+	/* port = <NPCX_TACH_PORT_A>; port-A is selected */
+	/* sample-clk = <NPCX_TACH_FREQ_LFCLK>; Use LFCLK as sampling clock */
+	/* pulses-per-round = <2>; number of pulses per round of encoder */
+};
+
+&pwm8 {
+	status = "okay";
+	pinctrl-0 = <&pwm8_gpio035>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/intelrvp/mtlrvp/mtlrvpp_mchp/gpio.dts b/zephyr/program/intelrvp/mtlrvp/mtlrvpp_mchp/gpio.dts
new file mode 100644
index 0000000000..d351bb87f3
--- /dev/null
+++ b/zephyr/program/intelrvp/mtlrvp/mtlrvpp_mchp/gpio.dts
@@ -0,0 +1,306 @@
+/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	aliases {
+		gpio-wp = &gpio_wp;
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		ioex_kbd_intr_n: ioex-kbd-intr-n {
+			gpios = <&gpio_140_176 29 GPIO_INPUT>;
+			enum-name = "GPIO_KB_DISCRETE_INT";
+		}; /* GPIO175 */
+		all_sys_pwrgd: all-sys-pwrgd {
+			gpios = <&gpio_040_076 15 GPIO_INPUT>;
+			enum-name = "GPIO_PG_EC_ALL_SYS_PWRGD";
+		}; /* GPIO057 */
+		rsmrst_pwrgd: rsmrst-pwrgd {
+			gpios = <&gpio_000_036 9 GPIO_INPUT>;
+			enum-name = "GPIO_PG_EC_RSMRST_ODL";
+		}; /* GPIO011 */
+		pch_slp_s0_n: pch-slp-s0-n-ec {
+			gpios = <&gpio_000_036 2 GPIO_INPUT>;
+			enum-name = "GPIO_PCH_SLP_S0_L"; /* 1.8V */
+		}; /* GPIO002 */
+		pm-slp-s3-n-ec {
+			gpios = <&gpio_000_036 12 GPIO_INPUT>; /* 1.8V */
+			enum-name = "GPIO_PCH_SLP_S3_L";
+		}; /* GPIO014 */
+		pm-slp-s4-n-ec {
+			gpios = <&gpio_000_036 13 GPIO_INPUT>; /* 1.8V */
+		}; /* GPIO015 */
+		volume-up {
+			gpios = <&gpio_000_036 30 (GPIO_INPUT | GPIO_PULL_UP)>;
+			enum-name = "GPIO_VOLUME_UP_L";
+		}; /* GPIO036 */
+		vol-dn-ec-r {
+			gpios = <&gpio_240_276 12 (GPIO_INPUT | GPIO_PULL_UP)>;
+			enum-name = "GPIO_VOLUME_DOWN_L";
+		}; /* GPIO254 */
+		smc_lid: smc-lid {
+			gpios = <&gpio_200_236 22 (GPIO_INPUT | GPIO_PULL_UP)>;
+			enum-name = "GPIO_LID_OPEN";
+		}; /* GPIO226 */
+		smc_onoff_n: smc-onoff-n {
+			gpios = <&gpio_240_276 6 GPIO_INPUT>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		}; /* GPIO246 */
+		/* NOTE: Netname is SUSWARN */
+		gpio_wp: wp-l {
+			gpios = <&gpio_000_036 20 GPIO_INPUT>;
+		}; /* GPIO024 */
+		std_adp_prsnt: std-adp-prsnt {
+			gpios = <&gpio_040_076 3 GPIO_INPUT>;
+			enum-name = "GPIO_DC_JACK_PRESENT";
+		}; /* GPIO043 */
+		bc_acok: bc-acok-ec {
+			gpios = <&gpio_140_176 14 GPIO_INPUT>;
+			enum-name = "GPIO_AC_PRESENT";
+		}; /* GPIO156 */
+
+		/*
+		 * Note - the Intel boards implement their own handlers
+		 * for tcpc_get_alert_status().  These handlers use
+		 * gpio_get_level(), which returns the raw state of the pin,
+		 * ignoring the GPIO_ACTIVE_LOW flag.
+		 *
+		 * However, the interrupt pin is shared with the upstream
+		 * driver gpio_nct38xx_alert.c, which does use the logical
+		 * level of the pin and requires that the signal is active low.
+		 *
+		 * Mark the signal active low here as well which ensures there
+		 * is no conflict between the gpio_pin_configure_dt() run by
+		 * the named-gpios driver and the gpio_nct38xx_alert.c driver.
+		 */
+		usbc_tcpc_alrt_p0: usbc-tcpc-alrt-p0 {
+			gpios = <&gpio_140_176 3 (GPIO_INPUT | \
+				GPIO_ACTIVE_LOW)>;
+		}; /* GPIO143 */
+		/* NOTE: Netname is USBC_TCPC_PPC_ALRT_P0 */
+		usb_c0_c1_tcpc_rst_odl: usb-c0-c1-tcpc-rst-odl {
+			gpios = <&gpio_240_276 0 GPIO_ODR_HIGH>;
+		}; /* GPIO240 */
+		/* NOTE: Netname is USBC_TCPC_ALRT_P1 */
+		usbc_tcpc_ppc_alrt_p0: usbc-tcpc-ppc-alrt-p0 {
+			gpios = <&gpio_240_276 1 GPIO_INPUT>;
+		}; /* GPIO241 */
+		usbc_tcpc_ppc_alrt_p1: usbc-tcpc-ppc-alrt-p1 {
+			gpios = <&gpio_140_176 13 GPIO_INPUT>;
+		}; /* GPIO155 */
+		usbc_tcpc_alrt_p2: usbc-tcpc-alrt-p2 {
+			gpios = <&gpio_200_236 17 GPIO_INPUT>;
+		}; /* GPIO221 */
+		/* NOTE: Netname is USBC_TCPC_PPC_ALRT_P3 */
+		usbc_tcpc_alrt_p3: usbc-tcpc-alrt-p3 {
+			gpios = <&gpio_000_036 28 GPIO_INPUT>;
+		}; /* GPIO034 */
+		gpio_ec_pch_wake_odl: pch-wake-n {
+			gpios = <&gpio_040_076 9 GPIO_ODR_HIGH>;
+		}; /* GPIO051 */
+		plt-rst-l {
+			gpios = <&gpio_040_076 10 GPIO_INPUT>; /* 1.8V */
+		}; /* GPIO052 */
+		slate-mode-indication {
+			gpios = <&gpio_200_236 18 GPIO_INPUT>; /* 1.8V */
+		}; /* GPIO222 */
+		prochot-ec {
+			gpios = <&gpio_240_276 3 GPIO_INPUT>;
+			enum-name = "GPIO_CPU_PROCHOT";
+		}; /* GPIO243 */
+		sys_rst_odl: sys-rst-odl-ec {
+			gpios = <&gpio_140_176 21 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_SYS_RESET_L";
+		}; /* GPIO165 */
+		ec_pch_rsmrst_l: pm-rsmrst-r-n {
+			gpios = <&gpio_040_076 12 GPIO_OUTPUT_LOW>; /* 1.8V */
+			enum-name = "GPIO_PCH_RSMRST_L";
+		}; /* GPIO054 */
+		pm-pwrbtn-n-ec {
+			gpios = <&gpio_240_276 5 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_PCH_PWRBTN_L";
+		}; /* GPIO245 */
+		ec_spi_oe_mecc: ec-spi-oe-mecc-r {
+			gpios = <&gpio_040_076 11 GPIO_OUTPUT_LOW>; /* 1.8V */
+		}; /* GPIO053 */
+		en_pp3300_a: ec-ds3-r {
+			gpios = <&gpio_000_036 21 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_EN_PP3300_A";
+			alias = "GPIO_TEMP_SENSOR_POWER";
+		}; /* GPIO025 */
+		ec_pch_pwrok_od: pch-pwrok-ec-r {
+			gpios = <&gpio_100_136 6 GPIO_ODR_LOW>;
+			enum-name = "GPIO_PCH_PWROK";
+		}; /* GPIO106 */
+		sys_pwrok_ec: sys-pwrok-ec {
+			gpios = <&gpio_200_236 2 GPIO_ODR_LOW>;
+			enum-name = "GPIO_PCH_SYS_PWROK";
+		}; /* GPIO202 */
+		bat-det-ec {
+			gpios = <&gpio_200_236 6 GPIO_INPUT>;
+			enum-name = "GPIO_BATT_PRES_ODL";
+		}; /* GPIO206 */
+		edp-bklt-en {
+			gpios = <&gpio_000_036 18 GPIO_OUTPUT_HIGH>;
+		}; /* GPIO022 */
+		/* TODO: move both LEDs to PWM */
+		led-1-l-ec {
+			gpios = <&gpio_140_176 15 GPIO_OUTPUT_HIGH>;
+		}; /* GPIO157 */
+		led-2-l-ec {
+			gpios = <&gpio_140_176 11 GPIO_OUTPUT_HIGH>;
+		}; /* GPIO153 */
+		gpio_fan_control: therm-sen-mecc-r {
+			gpios = <&gpio_200_236 1 GPIO_OUTPUT_LOW>;
+		}; /* GPIO201 */
+		/* NOTE: Netname is USBC_TCPC_ALRT_P3 */
+		ccd_mode_odl: ccd-mode-odl {
+			gpios = <&gpio_240_276 2 GPIO_INPUT>;
+			enum-name = "GPIO_CCD_MODE_ODL";
+		}; /* GPIO242 */
+		smb-bs-clk {
+			gpios = <&gpio_000_036 4 GPIO_INPUT>;
+		}; /* GPIO004 */
+		smb-bs-data {
+			gpios = <&gpio_000_036 3 GPIO_INPUT>;
+		}; /* GPIO003 */
+		usbc-tcpc-i2c-clk-aic1 {
+			gpios = <&gpio_140_176 0 GPIO_INPUT>;
+		}; /* GPIO140 */
+		usbc-tcpc-i2c-data-aic1 {
+			gpios = <&gpio_100_136 26 GPIO_INPUT>;
+		}; /* GPIO132 */
+		usbc-tcpc-i2c-clk-aic2 {
+			gpios = <&gpio_000_036 11 GPIO_INPUT>;
+		}; /* GPIO013 */
+		usbc-tcpc-i2c-data-aic2 {
+			gpios = <&gpio_000_036 10 GPIO_INPUT>;
+		}; /* GPIO012 */
+		espi-alert0-n-r {
+			gpios = <&gpio_040_076 19 GPIO_INPUT>;
+		}; /* GPIO063 */
+		slp-s0-cs-n-ec {
+			gpios = <&gpio_140_176 12 GPIO_INPUT>;
+		}; /* GPIO154 */
+		rtc-rst-n-r {
+			gpios = <&gpio_240_276 13 GPIO_INPUT>;
+		}; /* GPIO255 */
+		cpu-cat-err-mecc {
+			gpios = <&gpio_000_036 0 GPIO_INPUT>;
+		}; /* GPIO000 */
+		ec-peci-ec {
+			gpios = <&gpio_040_076 2 GPIO_INPUT>;
+		}; /* GPIO042 */
+		std-adpt-cntrl-GPIO_r {
+			gpios = <&gpio_240_276 4 GPIO_INPUT>;
+		}; /* GPIO244 */
+		boot-stall-r {
+			gpios = <&gpio_040_076 18 GPIO_INPUT>;
+		}; /* GPIO062 */
+		usbc_tcpc_ppc_alrt_p2: usbc-tcpc-ppc-alrt-p2 {
+			gpios = <&gpio_140_176 4 GPIO_INPUT>;
+		}; /* GPIO144 */
+
+		/* KBD IOEX configuration */
+		srtc-rst {
+			gpios = <&ioex_it8801_port0 3 GPIO_OUTPUT_LOW>;
+		};
+		ec-h1-packet-mode {
+			gpios = <&ioex_it8801_port0 4 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_PACKET_MODE_EN";
+		};
+		rtc-rst {
+			gpios = <&ioex_it8801_port0 6 GPIO_OUTPUT_LOW>;
+		};
+		ec-entering-rw {
+			gpios = <&ioex_it8801_port0 7 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_ENTERING_RW";
+		};
+		ioex-sys-rst-odl-ec {
+			gpios = <&ioex_it8801_port1 0 GPIO_INPUT>;
+		};
+		ioex-slate-mode-indication {
+			gpios = <&ioex_it8801_port1 2 GPIO_INPUT>;
+		};
+
+		/* USB C IOEX configuration */
+		usb_c0_hb_retimer_ls_en: usb-c0-hbr-ls-en {
+			gpios = <&ioex_c0 2 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C0_HBR_LS_EN";
+			no-auto-init;
+		};
+		usb_c0_hb_retimer_rst: usb-c0-hbr-rst {
+			gpios = <&ioex_c0 3 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C0_HBR_RST";
+			no-auto-init;
+		};
+		usb_c1_hb_retimer_ls_en: usb-c1-hbr-ls-en {
+			gpios = <&ioex_c1 2 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C1_HBR_LS_EN";
+			no-auto-init;
+		};
+		usb_c1_hb_retimer_rst: usb-c1-hbr-rst {
+			gpios = <&ioex_c1 3 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C1_HBR_RST";
+			no-auto-init;
+		};
+		usb-c0-mux-oe-n {
+			gpios = <&ioex_c0 4 GPIO_OUTPUT_LOW>;
+			no-auto-init;
+		};
+		usb-c0-mux-sbu-sel-0 {
+			gpios = <&ioex_c0 6 GPIO_OUTPUT_HIGH>;
+			enum-name = "IOEX_USB_C0_MUX_SBU_SEL_0";
+			no-auto-init;
+		};
+		usb-c0-mux-sbu-sel-1 {
+			gpios = <&ioex_c1 4 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C0_MUX_SBU_SEL_1";
+			no-auto-init;
+		};
+		usb-c0-c1-prochot-n {
+			gpios = <&ioex_c1 6 GPIO_INPUT>;
+			no-auto-init;
+		};
+		dg-bssb-sbu-sel {
+			gpios = <&ioex_c2_port1 4 GPIO_INPUT>;
+			no-auto-init;
+		};
+		usb_c2_hb_retimer_rst: usb-c2-hbr-rst {
+			gpios = <&ioex_c2_port1 1 (GPIO_ODR_LOW | \
+				GPIO_VOLTAGE_1P8)>;
+			enum-name = "IOEX_USB_C2_HBR_RST";
+			no-auto-init;
+		};
+		usb_c2_hb_retimer_ls_en: usb-c2-hbr-ls-en {
+			gpios = <&ioex_c2_port2 0 (GPIO_ODR_LOW | \
+				GPIO_VOLTAGE_1P8)>;
+			enum-name = "IOEX_USB_C2_HBR_LS_EN";
+			no-auto-init;
+		};
+		usb_c3_hb_retimer_rst: usb-c3-hbr-rst {
+			gpios = <&ioex_c2_port1 3 (GPIO_ODR_LOW | \
+				GPIO_VOLTAGE_1P8)>;
+			enum-name = "IOEX_USB_C3_HBR_RST";
+			no-auto-init;
+		};
+		usb_c3_hb_retimer_ls_en: usb-c3-hbr-ls-en {
+			gpios = <&ioex_c2_port3 3 (GPIO_ODR_LOW | \
+				GPIO_VOLTAGE_1P8)>;
+			enum-name = "IOEX_USB_C3_HBR_LS_EN";
+			no-auto-init;
+		};
+		usb-c2-c3-prochot-n {
+			gpios = <&ioex_c2_port0 0 GPIO_INPUT>;
+			no-auto-init;
+		};
+		/* unimplemented GPIOs */
+		en-pp5000 {
+			enum-name = "GPIO_EN_PP5000";
+		};
+	};
+};
diff --git a/zephyr/program/intelrvp/mtlrvp/mtlrvpp_mchp/keyboard.dts b/zephyr/program/intelrvp/mtlrvp/mtlrvpp_mchp/keyboard.dts
new file mode 100644
index 0000000000..3f939fc7f7
--- /dev/null
+++ b/zephyr/program/intelrvp/mtlrvp/mtlrvpp_mchp/keyboard.dts
@@ -0,0 +1,31 @@
+/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	cros-keyscan {
+		compatible = "cros-keyscan";
+
+		output-settle = <80>;
+		debounce-down = <9000>;
+		debounce-up = <30000>;
+		poll-timeout = <100000>;
+
+		actual-key-mask = <
+			0x14	/* C0 */
+			0xff	/* C1 */
+			0xff	/* C2 */
+			0xff	/* C3 */
+			0xff	/* C4 */
+			0xf5	/* C5 */
+			0xff	/* C6 */
+			0xa4	/* C7 */
+			0xff	/* C8 */
+			0xfe	/* C9 */
+			0x55	/* C10 */
+			0xfa	/* C11 */
+			0xca	/* C12 */
+			>;
+	};
+};
diff --git a/zephyr/program/intelrvp/mtlrvp/mtlrvpp_mchp/mtlrvp_mchp.dts b/zephyr/program/intelrvp/mtlrvp/mtlrvpp_mchp/mtlrvp_mchp.dts
new file mode 100644
index 0000000000..9fd5480f8c
--- /dev/null
+++ b/zephyr/program/intelrvp/mtlrvp/mtlrvpp_mchp/mtlrvp_mchp.dts
@@ -0,0 +1,280 @@
+/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+ #include <dt-bindings/usb_pd_tcpm.h>
+
+/ {
+	hibernate-wake-pins {
+		compatible = "cros-ec,hibernate-wake-pins";
+		wakeup-irqs = <
+			&int_ac_present
+			&int_lid_open
+			&int_power_button
+		>;
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		i2c_charger: charger {
+			i2c-port = <&i2c_smb_0>;
+			enum-names = "I2C_PORT_CHARGER",
+				"I2C_PORT_BATTERY",
+				"I2C_PORT_EEPROM",
+				"I2C_PORT_KB_DISCRETE",
+				"I2C_PORT_PORT80";
+		};
+		typec_aic1: typec-aic1{
+			i2c-port = <&i2c_smb_1>;
+			enum-names = "I2C_PORT_TYPEC_AIC_1";
+		};
+		typec_aic2: typec-aic2{
+			i2c-port = <&i2c_smb_2>;
+			enum-names = "I2C_PORT_TYPEC_AIC_2";
+		};
+	};
+
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		adc_ambient: ambient {
+			enum-name = "ADC_TEMP_SENSOR_1";
+			io-channels = <&adc0 3>;
+		};
+		adc_ddr: ddr {
+			enum-name = "ADC_TEMP_SENSOR_2";
+			io-channels = <&adc0 5>;
+		};
+		adc_skin: skin {
+			enum-name = "ADC_TEMP_SENSOR_3";
+			io-channels = <&adc0 4>;
+		};
+		adc_vr: vr {
+			enum-name = "ADC_TEMP_SENSOR_4";
+			io-channels = <&adc0 0>;
+		};
+	};
+};
+
+/* charger */
+&i2c_smb_0 {
+	label = "I2C_CHARGER";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	port_sel = <0>;
+	pinctrl-0 = <&i2c00_scl_gpio004 &i2c00_sda_gpio003>;
+	pinctrl-names = "default";
+
+	pca95xx: pca95xx@22 {
+		compatible = "nxp,pca95xx";
+		label = "PCA95XX";
+		reg = <0x22>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <16>;
+	};
+
+	rvp_board_id: rvp-board-id {
+		compatible = "intel,rvp-board-id";
+
+		/*
+		 * BOM ID [2]   : IOEX[0]
+		 * BOM ID [1:0] : IOEX[15:14]
+		 */
+		bom-gpios = <&pca95xx 0 0>, <&pca95xx 15 0>, <&pca95xx 14 0>;
+
+		/*
+		 * FAB ID [1:0] : IOEX[2:1]
+		 */
+		fab-gpios = <&pca95xx 2 0>, <&pca95xx 1 0>;
+
+		/*
+		 * BOARD ID[5:0] : IOEX[13:8]
+		 */
+		board-gpios = <&pca95xx 13 0>, <&pca95xx 12 0>, <&pca95xx 11 0>,
+			      <&pca95xx 10 0>, <&pca95xx 9 0>, <&pca95xx 8 0>;
+	};
+
+	kb_discrete: ite-it8801@39 {
+		compatible = "ite,it8801";
+		reg = <0x39>;
+	};
+
+	seven_seg_display: max695x-seven-seg-display@38 {
+		compatible = "maxim,seven-seg-display";
+		reg = <0x38>;
+		label = "MAX695X_SEVEN_SEG_DISPLAY";
+	};
+
+	charger: isl9241@9 {
+		compatible = "intersil,isl9241";
+		status = "okay";
+		reg = <0x9>;
+	};
+
+	cbi_eeprom: eeprom@50 {
+		compatible = "atmel,at24";
+		reg = <0x50>;
+		size = <2048>;
+		pagesize = <16>;
+		address-width = <8>;
+		timeout = <5>;
+	};
+};
+
+/* typec_aic1 */
+&i2c_smb_1 {
+	label = "I2C_USB_C0_C1_TCPC";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	port_sel = <6>;
+	pinctrl-0 = <&i2c06_scl_gpio140 &i2c06_sda_gpio132>;
+	pinctrl-names = "default";
+
+	tcpc_port0: nct38xx@73 {
+		compatible = "nuvoton,nct38xx";
+		reg = <0x73>;
+		gpio-dev = <&nct38xx_c0>;
+		tcpc-flags = <(
+			TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_NO_DEBUG_ACC_CONTROL)>;
+	};
+
+	nct38xx_c0: nct38xx_c0@73 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nuvoton,nct38xx-gpio";
+		reg = <0x73>;
+		label = "NCT38XX_C0";
+
+		ioex_c0:gpio@0 {
+			compatible = "nuvoton,nct38xx-gpio-port";
+			reg = <0x0>;
+			label = "NCT38XX_C0_GPIO0";
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <8>;
+			pin_mask = <0xdc>;
+			pinmux_mask = <0xff>;
+		};
+	};
+
+	tcpc_port1: nct38xx@77 {
+		compatible = "nuvoton,nct38xx";
+		reg = <0x77>;
+		gpio-dev = <&nct38xx_c1>;
+		tcpc-flags = <(TCPC_FLAGS_TCPCI_REV2_0)>;
+	};
+
+	nct38xx_c1: nct38xx_c1@77 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nuvoton,nct38xx-gpio";
+		reg = <0x77>;
+		label = "NCT38XX_C1";
+
+		ioex_c1:gpio@0 {
+			compatible = "nuvoton,nct38xx-gpio-port";
+			reg = <0x0>;
+			label = "NCT38XX_C1_GPIO0";
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <8>;
+			pin_mask = <0xdc>;
+			pinmux_mask = <0xff>;
+		};
+	};
+
+	nct38xx_alert_0 {
+		compatible = "nuvoton,nct38xx-gpio-alert";
+		/* irq-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; */
+		irq-gpios = <&gpio_140_176 3 GPIO_ACTIVE_LOW>;
+		nct38xx-dev = <&nct38xx_c0 &nct38xx_c1>;
+		label = "NCT38XX_ALERT_1";
+	}; /* GPIO143 */
+
+	ppc_port0: sn5s330@40 {
+		compatible = "ti,sn5s330";
+		status = "okay";
+		reg = <0x40>;
+	};
+
+	ppc_port1: sn5s330@41 {
+		compatible = "ti,sn5s330";
+		status = "okay";
+		reg = <0x41>;
+	};
+
+	usb_c0_hb_retimer: jhl9040r-c0@56 {
+		compatible = "intel,jhl9040r";
+		reg = <0x56>;
+		reset-pin = <&usb_c0_hb_retimer_rst>;
+		ls-en-pin = <&usb_c0_hb_retimer_ls_en>;
+	};
+
+	usb_c1_hb_retimer: jhl9040r-c1@57 {
+		compatible = "intel,jhl9040r";
+		reg = <0x57>;
+		reset-pin = <&usb_c1_hb_retimer_rst>;
+		ls-en-pin = <&usb_c1_hb_retimer_ls_en>;
+	};
+};
+
+/* typec_aic2 */
+&i2c_smb_2 {
+	label = "I2C_USB_C2_C3_TCPC";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	port_sel = <7>;
+	pinctrl-0 = <&i2c07_scl_gpio013 &i2c07_sda_gpio012>;
+	pinctrl-names = "default";
+
+	tcpc_port2: ccgxxf@b {
+		compatible = "cypress,ccgxxf";
+		reg = <0xb>;
+	};
+
+	tcpc_port3: ccgxxf@1b {
+		compatible = "cypress,ccgxxf";
+		reg = <0x1b>;
+	};
+
+	usb_c2_hb_retimer: jhl9040r-c2@58 {
+		compatible = "intel,jhl9040r";
+		reg = <0x58>;
+		reset-pin = <&usb_c2_hb_retimer_rst>;
+		ls-en-pin = <&usb_c2_hb_retimer_ls_en>;
+	};
+
+	usb_c2_alt_hb_retimer: jhl9040r-c2@56 {
+		compatible = "intel,jhl9040r";
+		reg = <0x56>;
+		reset-pin = <&usb_c2_hb_retimer_rst>;
+		ls-en-pin = <&usb_c2_hb_retimer_ls_en>;
+	};
+
+	usb_c3_hb_retimer: jhl9040r-c3@59 {
+		compatible = "intel,jhl9040r";
+		reg = <0x59>;
+		reset-pin = <&usb_c3_hb_retimer_rst>;
+		ls-en-pin = <&usb_c3_hb_retimer_ls_en>;
+	};
+
+	usb_c3_alt_hb_retimer: jhl9040r-c3@57 {
+		compatible = "intel,jhl9040r";
+		reg = <0x57>;
+		reset-pin = <&usb_c3_hb_retimer_rst>;
+		ls-en-pin = <&usb_c3_hb_retimer_ls_en>;
+	};
+};
+
+&adc0 {
+	status = "okay";
+	pinctrl-0 = <&adc00_gpio200
+		     &adc03_gpio203
+		     &adc04_gpio204
+		     &adc05_gpio205>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/intelrvp/mtlrvp/mtlrvpp_mchp/mtlrvp_mchp_power_signals.dts b/zephyr/program/intelrvp/mtlrvp/mtlrvpp_mchp/mtlrvp_mchp_power_signals.dts
new file mode 100644
index 0000000000..94d4a21087
--- /dev/null
+++ b/zephyr/program/intelrvp/mtlrvp/mtlrvpp_mchp/mtlrvp_mchp_power_signals.dts
@@ -0,0 +1,132 @@
+/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	chosen {
+		intel-ap-pwrseq,espi = &espi0;
+	};
+
+	common-pwrseq {
+		compatible = "intel,ap-pwrseq";
+
+		sys-pwrok-delay = <3>;
+		all-sys-pwrgd-timeout = <20>;
+	};
+
+	pwr-en-pp3300-s5 {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PP3300_S5 enable output to LS";
+		enum-name = "PWR_EN_PP3300_A";
+		/* gpios = <&gpioc 4 0>; */
+		gpios = <&gpio_000_036 21 0>;
+		output;
+	}; /* GPIO025 */
+	pwr-pg-ec-rsmrst-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST power good from regulator";
+		enum-name = "PWR_RSMRST";
+		/* gpios = <&gpio6 6 0>; */
+		gpios = <&gpio_000_036 9 0>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	}; /* GPIO011 */
+	pwr-ec-pch-rsmrst-odl {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST output to PCH";
+		enum-name = "PWR_EC_PCH_RSMRST";
+		/* gpios = <&gpioa 4 0>; */
+		gpios = <&gpio_040_076 12 0>;
+		output;
+	}; /* GPIO054 */
+	pwr-slp-s0-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_S0_L input from PCH";
+		enum-name = "PWR_SLP_S0";
+		/* gpios = <&gpioa 1 GPIO_ACTIVE_LOW>; */
+		gpios = <&gpio_000_036 2 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	}; /* GPIO002 */
+	pwr-pch-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PCH_PWROK output to PCH";
+		enum-name = "PWR_PCH_PWROK";
+		/* gpios = <&gpiod 3 GPIO_OPEN_DRAIN>; */
+		gpios = <&gpio_100_136 6 GPIO_OPEN_DRAIN>;
+		output;
+	}; /* GPIO106 */
+	pwr-ec-pch-sys-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_PWROK output to PCH";
+		enum-name = "PWR_EC_PCH_SYS_PWROK";
+		/* gpios = <&gpiof 5 GPIO_OPEN_DRAIN>; */
+		gpios = <&gpio_200_236 2 GPIO_OPEN_DRAIN>;
+		output;
+	}; /* GPIO202 */
+	pwr-sys-rst-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_RESET# output to PCH";
+		enum-name = "PWR_SYS_RST";
+		/* gpios = <&gpioc 5 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>; */
+		gpios = <&gpio_140_176 21 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>;
+		output;
+	}; /* GPIO165 */
+	pwr-slp-s3 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S3 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S3";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S3";
+		vw-invert;
+	};
+	pwr-slp-s4 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S4 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S4";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4";
+		vw-invert;
+	};
+	pwr-slp-s5 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S5 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S5";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5";
+		vw-invert;
+	};
+	pwr-all-sys-pwrgd {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "all power good";
+		enum-name = "PWR_ALL_SYS_PWRGD";
+		/* gpios = <&gpio7 0 0>; */
+		gpios = <&gpio_040_076 15 0>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	}; /* GPIO057 */
+};
+
+/*
+ * Because the power signals directly reference the GPIOs,
+ * the correspinding named-gpios need to have no-auto-init set.
+ */
+&en_pp3300_a {
+	no-auto-init;
+};
+&rsmrst_pwrgd {
+	no-auto-init;
+};
+&ec_pch_rsmrst_l {
+	no-auto-init;
+};
+&pch_slp_s0_n {
+	no-auto-init;
+};
+&ec_pch_pwrok_od {
+	no-auto-init;
+};
+&sys_pwrok_ec {
+	no-auto-init;
+};
+&sys_rst_odl {
+	no-auto-init;
+};
+&all_sys_pwrgd {
+	no-auto-init;
+};
diff --git a/zephyr/program/intelrvp/mtlrvp/mtlrvpp_mchp/prj.conf b/zephyr/program/intelrvp/mtlrvp/mtlrvpp_mchp/prj.conf
new file mode 100644
index 0000000000..51cf7212b5
--- /dev/null
+++ b/zephyr/program/intelrvp/mtlrvp/mtlrvpp_mchp/prj.conf
@@ -0,0 +1,41 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_BOARD_MTLRVP_MCHP=y
+CONFIG_CROS_SYSTEM_XEC=y
+CONFIG_CROS_KB_RAW_XEC=n
+CONFIG_SYSCON=n
+
+# For MCHP ESPI Drivers
+CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD=y
+CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION=y
+CONFIG_ESPI_PERIPHERAL_CUSTOM_OPCODE=y
+CONFIG_ESPI_PERIPHERAL_XEC_EMI0=y
+CONFIG_ESPI_PERIPHERAL_ACPI_EC_IBF_EVT_DATA=y
+CONFIG_ESPI_PERIPHERAL_KBC_OBE_CBK=y
+CONFIG_ESPI_PERIPHERAL_KBC_IBF_EVT_DATA=y
+
+# Invoke SoC Python script to create zephyr.mchp.bin which
+# is zephyr.bin processed for Boot-ROM loading.
+CONFIG_MCHP_MEC_UNSIGNED_HEADER=y
+CONFIG_MCHP_MEC_HEADER_FLASH_SIZE_256K=y
+
+# PWM
+CONFIG_PWM=y
+CONFIG_PWM_SHELL=n
+
+# RTC
+CONFIG_PLATFORM_EC_RTC=n
+
+# Zephyr debug options
+CONFIG_LOG=y
+# Enable flash console commands
+CONFIG_PLATFORM_EC_CONSOLE_CMD_FLASH=y
+# app_ec_main will not call wdt enable if this is set
+CONFIG_WDT_DISABLE_AT_BOOT=y
+
+# Enable power debug log
+CONFIG_AP_PWRSEQ_LOG_LEVEL_DBG=y
+# I2C driver init pri
+CONFIG_I2C_INIT_PRIORITY=29
diff --git a/zephyr/program/intelrvp/mtlrvp/mtlrvpp_npcx/fan.dts b/zephyr/program/intelrvp/mtlrvp/mtlrvpp_npcx/fan.dts
new file mode 100644
index 0000000000..cf85dd3413
--- /dev/null
+++ b/zephyr/program/intelrvp/mtlrvp/mtlrvpp_npcx/fan.dts
@@ -0,0 +1,36 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	fans {
+		compatible = "cros-ec,fans";
+
+		fan_0 {
+			pwms = <&pwm3 0 PWM_KHZ(30) PWM_POLARITY_NORMAL>;
+			rpm_min = <3200>;
+			rpm_start = <2200>;
+			rpm_max = <6600>;
+			tach = <&tach2>;
+			pgood_gpio = <&all_sys_pwrgd>;
+			enable_gpio = <&gpio_fan_control>;
+		};
+	};
+};
+
+/* Tachemeter for fan speed measurement */
+&tach2 {
+	status = "okay";
+	pinctrl-0 = <&ta2_1_in_gp73>; /* TA2 input on GPIO73 */
+	pinctrl-names = "default";
+	port = <NPCX_TACH_PORT_A>; /* port-A is selected */
+	sample-clk = <NPCX_TACH_FREQ_LFCLK>; /* Use LFCLK as sampling clock */
+	pulses-per-round = <2>; /* number of pulses per round of encoder */
+};
+
+&pwm3 {
+	status = "okay";
+	pinctrl-0 = <&pwm3_gp80>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/intelrvp/mtlrvp/mtlrvpp_npcx/gpio.dts b/zephyr/program/intelrvp/mtlrvp/mtlrvpp_npcx/gpio.dts
new file mode 100644
index 0000000000..8dbb684b56
--- /dev/null
+++ b/zephyr/program/intelrvp/mtlrvp/mtlrvpp_npcx/gpio.dts
@@ -0,0 +1,380 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	aliases {
+		gpio-wp = &gpio_wp;
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		ioex_kbd_intr_n: ioex-kbd-intr-n {
+			gpios = <&gpio0 0 GPIO_INPUT>;
+			enum-name = "GPIO_KB_DISCRETE_INT";
+		};
+		all_sys_pwrgd: all-sys-pwrgd {
+			gpios = <&gpio7 0 GPIO_INPUT>;
+			enum-name = "GPIO_PG_EC_ALL_SYS_PWRGD";
+		};
+		rsmrst_pwrgd: rsmrst-pwrgd {
+			gpios = <&gpio6 6 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+			enum-name = "GPIO_PG_EC_RSMRST_ODL";
+		};
+		pch_slp_s0_n: pch-slp-s0-n-ec {
+			gpios = <&gpioa 1 GPIO_INPUT>;
+			enum-name = "GPIO_PCH_SLP_S0_L"; /* 1.8V */
+		};
+		pm-slp-s3-n-ec {
+			gpios = <&gpiob 0 GPIO_INPUT>; /* 1.8V */
+			enum-name = "GPIO_PCH_SLP_S3_L";
+		};
+		pm-slp-s4-n-ec {
+			gpios = <&gpioa 5 GPIO_INPUT>; /* 1.8V */
+		};
+		volume-up {
+			gpios = <&gpio6 1 (GPIO_INPUT | GPIO_PULL_UP)>;
+			enum-name = "GPIO_VOLUME_UP_L";
+		};
+		vol-dn-ec-r {
+			gpios = <&gpio0 3 (GPIO_INPUT | GPIO_PULL_UP)>;
+			enum-name = "GPIO_VOLUME_DOWN_L";
+		};
+		smc_lid: smc-lid {
+			gpios = <&gpio0 1 (GPIO_INPUT | GPIO_PULL_UP)>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+		smc_onoff_n: smc-onoff-n {
+			gpios = <&gpiod 2 GPIO_INPUT>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		gpio_wp: wp-l {
+			gpios = <&gpiod 5 GPIO_INPUT>;
+		};
+		std_adp_prsnt: std-adp-prsnt {
+			gpios = <&gpioc 6 GPIO_INPUT>;
+			enum-name = "GPIO_DC_JACK_PRESENT";
+		};
+		bc_acok: bc-acok-ec {
+			gpios = <&gpio0 2 GPIO_INPUT>;
+			enum-name = "GPIO_AC_PRESENT";
+		};
+		/*
+		 * Note - the Intel boards implement their own handlers
+		 * for tcpc_get_alert_status().  These handlers use
+		 * gpio_get_level(), which returns the raw state of the pin,
+		 * ignoring the GPIO_ACTIVE_LOW flag.
+		 *
+		 * However, the interrupt pin is shared with the upstream
+		 * driver gpio_nct38xx_alert.c, which does use the logical
+		 * level of the pin and requires that the signal is active low.
+		 *
+		 * Mark the signal active low here as well which ensures there
+		 * is no conflict between the gpio_pin_configure_dt() run by
+		 * the named-gpios driver and the gpio_nct38xx_alert.c driver.
+		 */
+		 usbc_tcpc_alrt_p0: usbc-tcpc-alrt-p0 {
+			gpios = <&gpio4 0 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		/* NOTE: Netname is USBC_TCPC_PPC_ALRT_P0 */
+		usb_c0_c1_tcpc_rst_odl: usb-c0-c1-tcpc-rst-odl {
+			gpios = <&gpiod 0 GPIO_ODR_HIGH>;
+		};
+		/* NOTE: Netname is USBC_TCPC_ALRT_P1 */
+		usbc_tcpc_ppc_alrt_p0: usbc-tcpc-ppc-alrt-p0 {
+			gpios = <&gpiod 1 GPIO_INPUT>;
+		};
+		usbc_tcpc_ppc_alrt_p1: usbc-tcpc-ppc-alrt-p1 {
+			gpios = <&gpioe 4 GPIO_INPUT>;
+		};
+		usbc_tcpc_alrt_p2: usbc-tcpc-alrt-p2 {
+			gpios = <&gpio9 1 GPIO_INPUT>;
+		};
+		/* NOTE: Netname is USBC_TCPC_PPC_ALRT_P3 */
+		usbc_tcpc_alrt_p3: usbc-tcpc-alrt-p3 {
+			gpios = <&gpiof 3 GPIO_INPUT>;
+		};
+		gpio_ec_pch_wake_odl: pch-wake-n {
+			gpios = <&gpio7 4 GPIO_ODR_HIGH>;
+		};
+		espi-rst-n {
+			gpios = <&gpio5 4 GPIO_INPUT>; /* 1.8V */
+		};
+		plt-rst-l {
+			gpios = <&gpioa 2 GPIO_INPUT>; /* 1.8V */
+		};
+		slate-mode-indication {
+			gpios = <&gpio9 4 GPIO_INPUT>; /* 1.8V */
+		};
+		prochot-ec {
+			gpios = <&gpio6 0 GPIO_INPUT>;
+			enum-name = "GPIO_CPU_PROCHOT";
+		};
+		sys_rst_odl: sys-rst-odl-ec {
+			gpios = <&gpioc 5 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_SYS_RESET_L";
+		};
+		ec_pch_rsmrst_l: pm-rsmrst-r-n {
+			gpios = <&gpioa 4 GPIO_OUTPUT_LOW>; /* 1.8V */
+			enum-name = "GPIO_PCH_RSMRST_L";
+		};
+		pm-pwrbtn-n-ec {
+			gpios = <&gpiod 4 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_PCH_PWRBTN_L";
+		};
+		ec_spi_oe_mecc: ec-spi-oe-mecc-r {
+			gpios = <&gpioa 7 GPIO_OUTPUT_LOW>; /* 1.8V */
+		};
+		en_pp3300_a: ec-ds3-r {
+			gpios = <&gpioc 4 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_EN_PP3300_A";
+			alias = "GPIO_TEMP_SENSOR_POWER";
+		};
+		ec_pch_pwrok_od: pch-pwrok-ec-r {
+			gpios = <&gpiod 3 GPIO_ODR_LOW>;
+			enum-name = "GPIO_PCH_PWROK";
+		};
+		sys_pwrok_ec: sys-pwrok-ec {
+			gpios = <&gpiof 5 GPIO_ODR_LOW>;
+			enum-name = "GPIO_PCH_SYS_PWROK";
+		};
+		bat-det-ec {
+			gpios = <&gpio7 6 GPIO_INPUT>;
+			enum-name = "GPIO_BATT_PRES_ODL";
+		};
+		edp-bklt-en {
+			gpios = <&gpioe 1 GPIO_OUTPUT_HIGH>;
+		};
+		/* TODO: move both LEDs to PWM */
+		led-1-l-ec {
+			gpios = <&gpiob 6 GPIO_OUTPUT_HIGH>;
+		};
+		led-2-l-ec {
+			gpios = <&gpiob 7 GPIO_OUTPUT_HIGH>;
+		};
+		gpio_fan_control: therm-sen-mecc-r {
+			gpios = <&gpioc 0 GPIO_OUTPUT_LOW>;
+		};
+		/* NOTE: Netname is USBC_TCPC_ALRT_P3 */
+		ccd_mode_odl: ccd-mode-odl {
+			gpios = <&gpio9 2 GPIO_INPUT>;
+			enum-name = "GPIO_CCD_MODE_ODL";
+		};
+		smb-bs-clk {
+			gpios = <&gpiob 3 GPIO_INPUT>;
+		};
+		smb-bs-data {
+			gpios = <&gpiob 2 GPIO_INPUT>;
+		};
+		usbc-tcpc-i2c-clk-aic1 {
+			gpios = <&gpiob 5 GPIO_INPUT>;
+		};
+		usbc-tcpc-i2c-data-aic1 {
+			gpios = <&gpiob 4 GPIO_INPUT>;
+		};
+		usbc-tcpc-i2c-clk-aic2 {
+			gpios = <&gpio9 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		usbc-tcpc-i2c-data-aic2 {
+			gpios = <&gpio8 7 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		/* Unused 1.8V pins */
+		i3c-1-sda-r {
+			gpios = <&gpio5 0 GPIO_INPUT>;
+		};
+		i3c-1-scl-r {
+			gpios = <&gpio5 6 GPIO_INPUT>;
+		};
+		espi-alert0-n-r {
+			gpios = <&gpio5 7 GPIO_INPUT>;
+		};
+		tp-gpio95 {
+			gpios = <&gpio9 5 GPIO_INPUT>;
+		};
+		cpu-c10-gate {
+			gpios = <&gpio9 6 GPIO_INPUT>;
+		};
+		slp-s0-cs-n-ec {
+			gpios = <&gpio9 7 GPIO_INPUT>;
+		};
+		rtc-rst-n-r {
+			gpios = <&gpioa 0 GPIO_INPUT>;
+		};
+		tp-gpioa6 {
+			gpios = <&gpioa 6 GPIO_INPUT>;
+		};
+		sml1-clk-mecc {
+			gpios = <&gpio3 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		sml1-data-mecc {
+			gpios = <&gpio3 6 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		sml1-alert {
+			gpios = <&gpioc 7 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		smb-pch-alrt {
+			gpios = <&gpioa 3 GPIO_INPUT>;
+		};
+		smb-pch-data {
+			gpios = <&gpioc 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		smb-pch-clk {
+			gpios = <&gpioc 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		/* Unused 3.3V pins */
+		cpu-cat-err-mecc {
+			gpios = <&gpio3 4 GPIO_INPUT>;
+		};
+		tp-gpio37 {
+			gpios = <&gpio3 7 GPIO_INPUT>;
+		};
+		tp-vccpdsw-3p3-ec {
+			gpios = <&gpio4 5 GPIO_INPUT>;
+		};
+		mech-pwr-btn-in-odl {
+			gpios = <&gpio6 2 GPIO_INPUT>;
+		};
+		tp-gpio63 {
+			gpios = <&gpio6 3 GPIO_INPUT>;
+		};
+		tp-gpio67 {
+			gpios = <&gpio6 7 GPIO_INPUT>;
+		};
+		tp-gpio72 {
+			gpios = <&gpio7 2 GPIO_INPUT>;
+		};
+		tp-gpio75 {
+			gpios = <&gpio7 5 GPIO_INPUT>;
+		};
+		ec-peci-ec {
+			gpios = <&gpio8 1 GPIO_INPUT>;
+		};
+		tp-gpiob1 {
+			gpios = <&gpiob 1 GPIO_INPUT>;
+		};
+		std-adpt-cntrl-GPIO_r {
+			gpios = <&gpioc 3 GPIO_INPUT>;
+		};
+		ec-packet-mode-ec {
+			gpios = <&gpioe 2 GPIO_INPUT>;
+		};
+		tp-gpioe3 {
+			gpios = <&gpioe 3 GPIO_INPUT>;
+		};
+		boot-stall-r {
+			gpios = <&gpioe 5 GPIO_INPUT>;
+		};
+		tp-gpiof0 {
+			gpios = <&gpiof 0 GPIO_INPUT>;
+		};
+		tp-gpiof1 {
+			gpios = <&gpiof 1 GPIO_INPUT>;
+		};
+		usbc_tcpc_ppc_alrt_p2: usbc-tcpc-ppc-alrt-p2 {
+			gpios = <&gpiof 2 GPIO_INPUT>;
+		};
+		tp-gpiof4 {
+			gpios = <&gpiof 4 GPIO_INPUT>;
+		};
+
+		/* KBD IOEX configuration */
+		srtc-rst {
+			gpios = <&ioex_it8801_port0 3 GPIO_OUTPUT_LOW>;
+		};
+		ec-h1-packet-mode {
+			gpios = <&ioex_it8801_port0 4 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_PACKET_MODE_EN";
+		};
+		rtc-rst {
+			gpios = <&ioex_it8801_port0 6 GPIO_OUTPUT_LOW>;
+		};
+		ec-entering-rw {
+			gpios = <&ioex_it8801_port0 7 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_ENTERING_RW";
+		};
+		ioex-sys-rst-odl-ec {
+			gpios = <&ioex_it8801_port1 0 GPIO_INPUT>;
+		};
+		ioex-slate-mode-indication {
+			gpios = <&ioex_it8801_port1 2 GPIO_INPUT>;
+		};
+
+		/* USB C IOEX configuration */
+		usb_c0_hb_retimer_ls_en: usb-c0-hbr-ls-en {
+			gpios = <&ioex_c0 2 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C0_HBR_LS_EN";
+			no-auto-init;
+		};
+		usb_c0_hb_retimer_rst: usb-c0-hbr-rst {
+			gpios = <&ioex_c0 3 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C0_HBR_RST";
+			no-auto-init;
+		};
+		usb_c1_hb_retimer_ls_en: usb-c1-hbr-ls-en {
+			gpios = <&ioex_c1 2 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C1_HBR_LS_EN";
+			no-auto-init;
+		};
+		usb_c1_hb_retimer_rst: usb-c1-hbr-rst {
+			gpios = <&ioex_c1 3 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C1_HBR_RST";
+			no-auto-init;
+		};
+		usb-c0-mux-oe-n {
+			gpios = <&ioex_c0 4 GPIO_OUTPUT_LOW>;
+			no-auto-init;
+		};
+		usb-c0-mux-sbu-sel-0 {
+			gpios = <&ioex_c0 6 GPIO_OUTPUT_HIGH>;
+			enum-name = "IOEX_USB_C0_MUX_SBU_SEL_0";
+			no-auto-init;
+		};
+		usb-c0-mux-sbu-sel-1 {
+			gpios = <&ioex_c1 4 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C0_MUX_SBU_SEL_1";
+			no-auto-init;
+		};
+		usb-c0-c1-prochot-n {
+			gpios = <&ioex_c1 6 GPIO_INPUT>;
+			no-auto-init;
+		};
+		dg-bssb-sbu-sel {
+			gpios = <&ioex_c2_port1 4 GPIO_INPUT>;
+			no-auto-init;
+		};
+		usb_c2_hb_retimer_rst: usb-c2-hbr-rst {
+			gpios = <&ioex_c2_port1 1 (GPIO_ODR_LOW | \
+				GPIO_VOLTAGE_1P8)>;
+			enum-name = "IOEX_USB_C2_HBR_RST";
+			no-auto-init;
+		};
+		usb_c2_hb_retimer_ls_en: usb-c2-hbr-ls-en {
+			gpios = <&ioex_c2_port2 0 (GPIO_ODR_LOW | \
+				GPIO_VOLTAGE_1P8)>;
+			enum-name = "IOEX_USB_C2_HBR_LS_EN";
+			no-auto-init;
+		};
+		usb_c3_hb_retimer_rst: usb-c3-hbr-rst {
+			gpios = <&ioex_c2_port1 3 (GPIO_ODR_LOW | \
+				GPIO_VOLTAGE_1P8)>;
+			enum-name = "IOEX_USB_C3_HBR_RST";
+			no-auto-init;
+		};
+		usb_c3_hb_retimer_ls_en: usb-c3-hbr-ls-en {
+			gpios = <&ioex_c2_port3 3 (GPIO_ODR_LOW | \
+				GPIO_VOLTAGE_1P8)>;
+			enum-name = "IOEX_USB_C3_HBR_LS_EN";
+			no-auto-init;
+		};
+		usb-c2-c3-prochot-n {
+			gpios = <&ioex_c2_port0 0 GPIO_INPUT>;
+			no-auto-init;
+		};
+		/* unimplemented GPIOs */
+		en-pp5000 {
+			enum-name = "GPIO_EN_PP5000";
+		};
+	};
+};
diff --git a/zephyr/program/intelrvp/mtlrvp/mtlrvpp_npcx/interrupts.dts b/zephyr/program/intelrvp/mtlrvp/mtlrvpp_npcx/interrupts.dts
new file mode 100644
index 0000000000..ad928fd593
--- /dev/null
+++ b/zephyr/program/intelrvp/mtlrvp/mtlrvpp_npcx/interrupts.dts
@@ -0,0 +1,65 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/ {
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_lid_open: lid_open {
+			irq-pin = <&smc_lid>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "lid_interrupt";
+		};
+		int_power_button: power_button {
+			irq-pin = <&smc_onoff_n>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_button_interrupt";
+		};
+		int_ac_present: ac_present {
+			irq-pin = <&bc_acok>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "extpower_interrupt";
+		};
+		int_ioex_kbd_intr_n: ioex_kbd_intr_n {
+			irq-pin = <&ioex_kbd_intr_n>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "io_expander_it8801_interrupt";
+		};
+		int_usb_c0_c1_tcpc: usb_c0_tcpc {
+			irq-pin = <&usbc_tcpc_alrt_p0>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "tcpc_alert_event";
+		};
+		int_usb_c0_ppc: usb_c0_ppc {
+			irq-pin = <&usbc_tcpc_ppc_alrt_p0>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "ppc_interrupt";
+		};
+		int_usb_c1_ppc: usb_c1_ppc {
+			irq-pin = <&usbc_tcpc_ppc_alrt_p1>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "ppc_interrupt";
+		};
+		int_usb_c2_tcpc: usb_c2_tcpc {
+			irq-pin = <&usbc_tcpc_alrt_p2>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "tcpc_alert_event";
+		};
+		int_usb_c3_tcpc: usb_c3_tcpc {
+			irq-pin = <&usbc_tcpc_alrt_p3>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "tcpc_alert_event";
+		};
+		int_ccd_mode: ccd_mode {
+			irq-pin = <&ccd_mode_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "board_connect_c0_sbu";
+		};
+		int_dc_jack_present: dc_jack_present {
+			irq-pin = <&std_adp_prsnt>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "board_dc_jack_interrupt";
+		};
+	};
+};
diff --git a/zephyr/program/intelrvp/mtlrvp/mtlrvpp_npcx/keyboard.dts b/zephyr/program/intelrvp/mtlrvp/mtlrvpp_npcx/keyboard.dts
new file mode 100644
index 0000000000..be0a570e95
--- /dev/null
+++ b/zephyr/program/intelrvp/mtlrvp/mtlrvpp_npcx/keyboard.dts
@@ -0,0 +1,59 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	cros-keyscan {
+		compatible = "cros-ec,keyscan";
+
+		output-settle = <35>;
+		debounce-down = <5000>;
+		debounce-up = <40000>;
+		poll-timeout = <100000>;
+
+		actual-key-mask = <
+			0x14	/* C0 */
+			0xff	/* C1 */
+			0xff	/* C2 */
+			0xff	/* C3 */
+			0xff	/* C4 */
+			0xf5	/* C5 */
+			0xff	/* C6 */
+			0xa4	/* C7 */
+			0xff	/* C8 */
+			0xfe	/* C9 */
+			0x55	/* C10 */
+			0xfa	/* C11 */
+			0xca	/* C12 */
+			>;
+	};
+};
+
+&cros_kb_raw {
+	status = "okay";
+	/* No KSO2 (it's inverted and implemented by GPIO) */
+	pinctrl-0 = <
+		&ksi0_gp31
+		&ksi1_gp30
+		&ksi2_gp27
+		&ksi3_gp26
+		&ksi4_gp25
+		&ksi5_gp24
+		&ksi6_gp23
+		&ksi7_gp22
+		&kso00_gp21
+		&kso01_gp20
+		&kso03_gp16
+		&kso04_gp15
+		&kso05_gp14
+		&kso06_gp13
+		&kso07_gp12
+		&kso08_gp11
+		&kso09_gp10
+		&kso10_gp07
+		&kso11_gp06
+		&kso12_gp05
+	>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx.dts b/zephyr/program/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx.dts
new file mode 100644
index 0000000000..586ef9e2d3
--- /dev/null
+++ b/zephyr/program/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx.dts
@@ -0,0 +1,305 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+ #include <dt-bindings/usb_pd_tcpm.h>
+
+/ {
+	chosen {
+		cros,rtc = &mtc;
+	};
+
+	hibernate-wake-pins {
+		compatible = "cros-ec,hibernate-wake-pins";
+		wakeup-irqs = <
+			&int_ac_present
+			&int_lid_open
+			&int_power_button
+			&int_usb_c0_c1_tcpc
+			&int_usb_c2_tcpc
+			&int_usb_c3_tcpc
+		>;
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		i2c_charger: charger {
+			i2c-port = <&i2c7_0>;
+			enum-names = "I2C_PORT_CHARGER",
+				"I2C_PORT_BATTERY",
+				"I2C_PORT_EEPROM",
+				"I2C_PORT_KB_DISCRETE",
+				"I2C_PORT_PORT80";
+		};
+		typec_aic1: typec-aic1{
+			i2c-port = <&i2c0_0>;
+			enum-names = "I2C_PORT_TYPEC_AIC_1";
+		};
+		typec_aic2: typec-aic2{
+			i2c-port = <&i2c1_0>;
+			enum-names = "I2C_PORT_TYPEC_AIC_2";
+		};
+	};
+
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		adc_ambient: ambient {
+			enum-name = "ADC_TEMP_SENSOR_1";
+			io-channels = <&adc0 3>;
+		};
+		adc_ddr: ddr {
+			enum-name = "ADC_TEMP_SENSOR_2";
+			io-channels = <&adc0 4>;
+		};
+		adc_skin: skin {
+			enum-name = "ADC_TEMP_SENSOR_3";
+			io-channels = <&adc0 2>;
+		};
+		adc_vr: vr {
+			enum-name = "ADC_TEMP_SENSOR_4";
+			io-channels = <&adc0 1>;
+		};
+	};
+};
+
+/* charger */
+&i2c7_0 {
+	label = "I2C_CHARGER";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>;
+	pinctrl-names = "default";
+
+	pca95xx: pca95xx@22 {
+		compatible = "nxp,pca95xx";
+		label = "PCA95XX";
+		reg = <0x22>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <16>;
+	};
+
+	rvp_board_id: rvp-board-id {
+		compatible = "intel,rvp-board-id";
+
+		/*
+		 * BOM ID [2]   : IOEX[0]
+		 * BOM ID [1:0] : IOEX[15:14]
+		 */
+		bom-gpios = <&pca95xx 0 0>, <&pca95xx 15 0>, <&pca95xx 14 0>;
+
+		/*
+		 * FAB ID [1:0] : IOEX[2:1]
+		 */
+		fab-gpios = <&pca95xx 2 0>, <&pca95xx 1 0>;
+
+		/*
+		 * BOARD ID[5:0] : IOEX[13:8]
+		 */
+		board-gpios = <&pca95xx 13 0>, <&pca95xx 12 0>, <&pca95xx 11 0>,
+			      <&pca95xx 10 0>, <&pca95xx 9 0>, <&pca95xx 8 0>;
+	};
+
+	kb_discrete: ite-it8801@39 {
+		compatible = "ite,it8801";
+		reg = <0x39>;
+	};
+
+	max695x@38 {
+		compatible = "maxim,max695x";
+		reg = <0x38>;
+	};
+
+	charger: isl9241@9 {
+		compatible = "intersil,isl9241";
+		status = "okay";
+		reg = <0x9>;
+	};
+
+	cbi_eeprom: eeprom@50 {
+		compatible = "atmel,at24";
+		reg = <0x50>;
+		size = <2048>;
+		pagesize = <16>;
+		address-width = <8>;
+		timeout = <5>;
+	};
+};
+
+/* host interface */
+&espi0 {
+	status = "okay";
+	pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>;
+	pinctrl-names = "default";
+};
+
+&i2c_ctrl7 {
+	status = "okay";
+};
+
+/* typec_aic1 */
+&i2c0_0 {
+	label = "I2C_USB_C0_C1_TCPC";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>;
+	pinctrl-names = "default";
+
+	tcpc_port0: nct38xx@73 {
+		compatible = "nuvoton,nct38xx";
+		reg = <0x73>;
+		gpio-dev = <&nct38xx_c0>;
+		tcpc-flags = <(
+			TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_NO_DEBUG_ACC_CONTROL)>;
+		int-pin = <&usbc_tcpc_alrt_p0>;
+	};
+
+	nct38xx_c0: nct38xx_c0@73 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nuvoton,nct38xx-gpio";
+		reg = <0x73>;
+		label = "NCT38XX_C0";
+
+		ioex_c0: gpio@0 {
+			compatible = "nuvoton,nct38xx-gpio-port";
+			reg = <0x0>;
+			label = "NCT38XX_C0_GPIO0";
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <8>;
+			pin_mask = <0xdc>;
+			pinmux_mask = <0xff>;
+		};
+	};
+
+	tcpc_port1: nct38xx@77 {
+		compatible = "nuvoton,nct38xx";
+		reg = <0x77>;
+		gpio-dev = <&nct38xx_c1>;
+		tcpc-flags = <(TCPC_FLAGS_TCPCI_REV2_0)>;
+		int-pin = <&usbc_tcpc_alrt_p0>;
+	};
+
+	nct38xx_c1: nct38xx_c1@77 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nuvoton,nct38xx-gpio";
+		reg = <0x77>;
+		label = "NCT38XX_C1";
+
+		ioex_c1: gpio@0 {
+			compatible = "nuvoton,nct38xx-gpio-port";
+			reg = <0x0>;
+			label = "NCT38XX_C1_GPIO0";
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <8>;
+			pin_mask = <0xdc>;
+			pinmux_mask = <0xff>;
+		};
+	};
+
+	nct38xx_alert_0 {
+		compatible = "nuvoton,nct38xx-gpio-alert";
+		irq-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
+		nct38xx-dev = <&nct38xx_c0 &nct38xx_c1>;
+		label = "NCT38XX_ALERT_1";
+	};
+
+	ppc_port0: sn5s330@40 {
+		compatible = "ti,sn5s330";
+		status = "okay";
+		reg = <0x40>;
+	};
+
+	ppc_port1: sn5s330@41 {
+		compatible = "ti,sn5s330";
+		status = "okay";
+		reg = <0x41>;
+	};
+
+	usb_c0_hb_retimer: jhl9040r-c0@56 {
+		compatible = "intel,jhl9040r";
+		reg = <0x56>;
+		reset-pin = <&usb_c0_hb_retimer_rst>;
+		ls-en-pin = <&usb_c0_hb_retimer_ls_en>;
+	};
+
+	usb_c1_hb_retimer: jhl9040r-c1@57 {
+		compatible = "intel,jhl9040r";
+		reg = <0x57>;
+		reset-pin = <&usb_c1_hb_retimer_rst>;
+		ls-en-pin = <&usb_c1_hb_retimer_ls_en>;
+	};
+};
+
+&i2c_ctrl0 {
+	status = "okay";
+};
+
+/* typec_aic2 */
+&i2c1_0 {
+	label = "I2C_USB_C2_C3_TCPC";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>;
+	pinctrl-names = "default";
+
+	tcpc_port2: ccgxxf@b {
+		compatible = "cypress,ccgxxf";
+		reg = <0xb>;
+		int-pin = <&usbc_tcpc_alrt_p2>;
+	};
+
+	tcpc_port3: ccgxxf@1b {
+		compatible = "cypress,ccgxxf";
+		reg = <0x1b>;
+		int-pin = <&usbc_tcpc_alrt_p3>;
+	};
+
+	usb_c2_hb_retimer: jhl9040r-c2@58 {
+		compatible = "intel,jhl9040r";
+		reg = <0x58>;
+		reset-pin = <&usb_c2_hb_retimer_rst>;
+		ls-en-pin = <&usb_c2_hb_retimer_ls_en>;
+	};
+
+	usb_c2_alt_hb_retimer: jhl9040r-c2@56 {
+		compatible = "intel,jhl9040r";
+		reg = <0x56>;
+		reset-pin = <&usb_c2_hb_retimer_rst>;
+		ls-en-pin = <&usb_c2_hb_retimer_ls_en>;
+	};
+
+	usb_c3_hb_retimer: jhl9040r-c3@59 {
+		compatible = "intel,jhl9040r";
+		reg = <0x59>;
+		reset-pin = <&usb_c3_hb_retimer_rst>;
+		ls-en-pin = <&usb_c3_hb_retimer_ls_en>;
+	};
+
+	usb_c3_alt_hb_retimer: jhl9040r-c3@57 {
+		compatible = "intel,jhl9040r";
+		reg = <0x57>;
+		reset-pin = <&usb_c3_hb_retimer_rst>;
+		ls-en-pin = <&usb_c3_hb_retimer_ls_en>;
+	};
+};
+
+&i2c_ctrl1 {
+	status = "okay";
+};
+
+&adc0 {
+	status = "okay";
+	pinctrl-0 = <&adc0_chan1_gp44
+		     &adc0_chan2_gp43
+		     &adc0_chan3_gp42
+		     &adc0_chan4_gp41>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx_power_signals.dts b/zephyr/program/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx_power_signals.dts
new file mode 100644
index 0000000000..3c270d296f
--- /dev/null
+++ b/zephyr/program/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx_power_signals.dts
@@ -0,0 +1,125 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	chosen {
+		intel-ap-pwrseq,espi = &espi0;
+	};
+
+	common-pwrseq {
+		compatible = "intel,ap-pwrseq";
+
+		sys-pwrok-delay = <3>;
+		all-sys-pwrgd-timeout = <20>;
+		sys-reset-delay = <60>;
+	};
+
+	pwr-en-pp3300-s5 {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PP3300_S5 enable output to LS";
+		enum-name = "PWR_EN_PP3300_A";
+		gpios = <&gpioc 4 0>;
+		output;
+	};
+	pwr-pg-ec-rsmrst-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST power good from regulator";
+		enum-name = "PWR_RSMRST";
+		gpios = <&gpio6 6 0>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-ec-pch-rsmrst-odl {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST output to PCH";
+		enum-name = "PWR_EC_PCH_RSMRST";
+		gpios = <&gpioa 4 0>;
+		output;
+	};
+	pwr-slp-s0-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_S0_L input from PCH";
+		enum-name = "PWR_SLP_S0";
+		gpios = <&gpioa 1 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-pch-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PCH_PWROK output to PCH";
+		enum-name = "PWR_PCH_PWROK";
+		gpios = <&gpiod 3 GPIO_OPEN_DRAIN>;
+		output;
+	};
+	pwr-ec-pch-sys-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_PWROK output to PCH";
+		enum-name = "PWR_EC_PCH_SYS_PWROK";
+		gpios = <&gpiof 5 GPIO_OPEN_DRAIN>;
+		output;
+	};
+	pwr-sys-rst-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_RESET# output to PCH";
+		enum-name = "PWR_SYS_RST";
+		gpios = <&gpioc 5 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>;
+		output;
+	};
+	pwr-slp-s3 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S3 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S3";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S3";
+		vw-invert;
+	};
+	pwr-slp-s4 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S4 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S4";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4";
+		vw-invert;
+	};
+	pwr-slp-s5 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S5 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S5";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5";
+		vw-invert;
+	};
+	pwr-all-sys-pwrgd {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "all power good";
+		enum-name = "PWR_ALL_SYS_PWRGD";
+		gpios = <&gpio7 0 0>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+};
+
+/*
+ * Because the power signals directly reference the GPIOs,
+ * the correspinding named-gpios need to have no-auto-init set.
+ */
+&en_pp3300_a {
+	no-auto-init;
+};
+&rsmrst_pwrgd {
+	no-auto-init;
+};
+&ec_pch_rsmrst_l {
+	no-auto-init;
+};
+&pch_slp_s0_n {
+	no-auto-init;
+};
+&ec_pch_pwrok_od {
+	no-auto-init;
+};
+&sys_pwrok_ec {
+	no-auto-init;
+};
+&sys_rst_odl {
+	no-auto-init;
+};
+&all_sys_pwrgd {
+	no-auto-init;
+};
diff --git a/zephyr/program/intelrvp/mtlrvp/mtlrvpp_npcx/prj.conf b/zephyr/program/intelrvp/mtlrvp/mtlrvpp_npcx/prj.conf
new file mode 100644
index 0000000000..23be2c01c4
--- /dev/null
+++ b/zephyr/program/intelrvp/mtlrvp/mtlrvpp_npcx/prj.conf
@@ -0,0 +1,12 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_BOARD_MTLRVP_NPCX=y
+CONFIG_CROS_SYSTEM_NPCX=y
+CONFIG_SYSCON=y
+
+# RTC
+CONFIG_PLATFORM_EC_RTC=y
+
+CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API=y
diff --git a/zephyr/program/intelrvp/mtlrvp/prj.conf b/zephyr/program/intelrvp/mtlrvp/prj.conf
new file mode 100644
index 0000000000..710da12e8a
--- /dev/null
+++ b/zephyr/program/intelrvp/mtlrvp/prj.conf
@@ -0,0 +1,63 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Power Sequencing
+CONFIG_AP_X86_INTEL_MTL=y
+CONFIG_X86_NON_DSX_PWRSEQ_MTL=y
+CONFIG_PLATFORM_EC_POWERSEQ_SLP_S3_L_OVERRIDE=n
+CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n
+
+# Battery
+CONFIG_PLATFORM_EC_BATTERY_TYPE_NO_AUTO_DETECT=y
+CONFIG_PLATFORM_EC_BATTERY_V2=y
+
+# CBI
+CONFIG_EEPROM=y
+CONFIG_PLATFORM_EC_BYPASS_CBI_EEPROM_WP_CHECK=y
+CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y
+
+# Disable BC1.2
+CONFIG_PLATFORM_EC_USB_CHARGER=n
+
+# Charger
+CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=5
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=10
+CONFIG_PLATFORM_EC_CHARGE_RAMP_HW=n
+CONFIG_PLATFORM_EC_CHARGER_ISL9241=y
+CONFIG_PLATFORM_EC_DEDICATED_CHARGE_PORT=y
+
+# IOEX
+CONFIG_PLATFORM_EC_IOEX_CCGXXF=y
+CONFIG_PLATFORM_EC_IOEX_IT8801=y
+
+#Keyboard from I/O expander
+CONFIG_CROS_KB_RAW_NPCX=n
+
+# Temperature sensors
+CONFIG_PLATFORM_EC_TEMP_SENSOR_POWER=y
+
+# USB CONFIG
+CONFIG_PLATFORM_EC_USB_DRP_ACC_TRYSRC=y
+CONFIG_PLATFORM_EC_USB_MUX_TASK=y
+CONFIG_PLATFORM_EC_USBC_PPC_SN5S330=y
+CONFIG_PLATFORM_EC_USBC_PPC=y
+CONFIG_PLATFORM_EC_USB_PD_PPC=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_PPC=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_CHARGER=y
+CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y
+CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_TCPC=y
+CONFIG_PLATFORM_EC_USB_PD_TCPC_LOW_POWER=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_MUX=y
+CONFIG_PLATFORM_EC_USB_PD_TRY_SRC=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_SBU=y
+CONFIG_PLATFORM_EC_USB_PD_DUAL_ROLE_AUTO_TOGGLE=y
+CONFIG_PLATFORM_EC_USBC_VCONN=y
+CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=y
+CONFIG_PLATFORM_EC_USB_PD_USB32_DRD=y
+CONFIG_PLATFORM_EC_USB_PD_USB4=y
+CONFIG_PLATFORM_EC_USB_PD_INT_SHARED=y
+CONFIG_PLATFORM_EC_USB_PD_PORT_0_SHARED=y
+CONFIG_PLATFORM_EC_USB_PD_PORT_1_SHARED=y
diff --git a/zephyr/program/intelrvp/mtlrvp/src/board_power.c b/zephyr/program/intelrvp/mtlrvp/src/board_power.c
new file mode 100644
index 0000000000..888efd3485
--- /dev/null
+++ b/zephyr/program/intelrvp/mtlrvp/src/board_power.c
@@ -0,0 +1,63 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "gpio/gpio.h"
+#include "gpio_signal.h"
+#include "system_boot_time.h"
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/atomic.h>
+
+#include <ap_power/ap_power.h>
+#include <ap_power/ap_power_events.h>
+#include <ap_power/ap_power_interface.h>
+#include <ap_power_override_functions.h>
+#include <power_signals.h>
+#include <x86_power_signals.h>
+
+LOG_MODULE_DECLARE(ap_pwrseq, LOG_LEVEL_INF);
+
+#if CONFIG_X86_NON_DSX_PWRSEQ_MTL
+#define X86_NON_DSX_MTL_FORCE_SHUTDOWN_TO_MS 50
+
+void board_ap_power_force_shutdown(void)
+{
+	int timeout_ms = X86_NON_DSX_MTL_FORCE_SHUTDOWN_TO_MS;
+
+	/* Turn off PCH_RMSRST to meet tPCH12 */
+	power_signal_set(PWR_EC_PCH_RSMRST, 0);
+
+	/* Turn off PRIM load switch. */
+	power_signal_set(PWR_EN_PP3300_A, 0);
+
+	/* Wait RSMRST to be off. */
+	while (power_signal_get(PWR_RSMRST) && (timeout_ms > 0)) {
+		k_msleep(1);
+		timeout_ms--;
+	};
+
+	if (power_signal_get(PWR_RSMRST))
+		LOG_WRN("RSMRST_ODL didn't go low!  Assuming G3.");
+}
+
+void board_ap_power_action_g3_s5(void)
+{
+	/* Turn on the PP3300_PRIM rail. */
+	power_signal_set(PWR_EN_PP3300_A, 1);
+
+	update_ap_boot_time(ARAIL);
+	if (!power_wait_signals_timeout(
+		    IN_PGOOD_ALL_CORE,
+		    AP_PWRSEQ_DT_VALUE(wait_signal_timeout))) {
+		ap_power_ev_send_callbacks(AP_POWER_PRE_INIT);
+	}
+}
+
+bool board_ap_power_check_power_rails_enabled(void)
+{
+	return power_signal_get(PWR_EN_PP3300_A);
+}
+#endif /* CONFIG_X86_NON_DSX_PWRSEQ_MTL */
diff --git a/zephyr/program/intelrvp/mtlrvp/src/mtlrvp.c b/zephyr/program/intelrvp/mtlrvp/src/mtlrvp.c
new file mode 100644
index 0000000000..d9c0de42f0
--- /dev/null
+++ b/zephyr/program/intelrvp/mtlrvp/src/mtlrvp.c
@@ -0,0 +1,382 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "battery_fuel_gauge.h"
+#include "charger.h"
+#include "common.h"
+#include "console.h"
+#include "driver/retimer/bb_retimer_public.h"
+#include "driver/tcpm/ccgxxf.h"
+#include "driver/tcpm/nct38xx.h"
+#include "driver/tcpm/tcpci.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "intel_rvp_board_id.h"
+#include "intelrvp.h"
+#include "ioexpander.h"
+#include "isl9241.h"
+#include "keyboard_raw.h"
+#include "power/meteorlake.h"
+#include "sn5s330.h"
+#include "system.h"
+#include "task.h"
+#include "tusb1064.h"
+#include "usb_mux.h"
+#include "usbc/usb_muxes.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#include <zephyr/drivers/espi.h>
+
+#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ##args)
+
+/* eSPI device */
+#define espi_dev DEVICE_DT_GET(DT_CHOSEN(cros_ec_espi))
+
+/*******************************************************************/
+/* USB-C Configuration Start */
+
+/* PPC */
+#define I2C_ADDR_SN5S330_P0 0x40
+#define I2C_ADDR_SN5S330_P1 0x41
+
+#define MTLP_DDR5_RVP_SKU_BOARD_ID 0x01
+#define MTLP_LP5_RVP_SKU_BOARD_ID 0x02
+#define MTL_RVP_BOARD_ID(id) ((id)&0x3F)
+
+/* IOEX ports */
+enum ioex_port {
+	IOEX_KBD = 0,
+#if defined(HAS_TASK_PD_C2)
+	IOEX_C2_CCGXXF,
+#endif
+	IOEX_COUNT
+};
+
+/* USB-C ports */
+enum usbc_port {
+	USBC_PORT_C0 = 0,
+	USBC_PORT_C1,
+#if defined(HAS_TASK_PD_C2)
+	USBC_PORT_C2,
+	USBC_PORT_C3,
+#endif
+	USBC_PORT_COUNT
+};
+BUILD_ASSERT(USBC_PORT_COUNT == CONFIG_USB_PD_PORT_MAX_COUNT);
+
+/* TCPC AIC GPIO Configuration */
+const struct tcpc_aic_gpio_config_t tcpc_aic_gpios[] = {
+	[USBC_PORT_C0] = {
+		.tcpc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_alrt_p0)),
+		.ppc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_ppc_alrt_p0)),
+		.ppc_intr_handler = sn5s330_interrupt,
+	},
+	[USBC_PORT_C1] = {
+		.tcpc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_alrt_p0)),
+		.ppc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_ppc_alrt_p1)),
+		.ppc_intr_handler = sn5s330_interrupt,
+	},
+#if defined(HAS_TASK_PD_C2)
+	[USBC_PORT_C2] = {
+		.tcpc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_alrt_p2)),
+		/* No PPC alert for CCGXXF */
+	},
+	[USBC_PORT_C3] = {
+		.tcpc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_alrt_p3)),
+		/* No PPC alert for CCGXXF */
+	},
+#endif
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_aic_gpios) == CONFIG_USB_PD_PORT_MAX_COUNT);
+
+static void board_connect_c0_sbu_deferred(void)
+{
+	enum pd_power_role prole;
+
+	if (gpio_get_level(GPIO_CCD_MODE_ODL)) {
+		CPRINTS("Default AUX line connected");
+		/* Default set the SBU lines to AUX mode */
+		ioex_set_level(IOEX_USB_C0_MUX_SBU_SEL_1, 0);
+		ioex_set_level(IOEX_USB_C0_MUX_SBU_SEL_0, 1);
+	} else {
+		prole = pd_get_power_role(USBC_PORT_C0);
+		CPRINTS("%s debug device is attached",
+			prole == PD_ROLE_SINK ? "Servo V4C/SuzyQ" : "Intel");
+
+		if (prole == PD_ROLE_SINK) {
+			/* Set the SBU lines to Google CCD mode */
+			ioex_set_level(IOEX_USB_C0_MUX_SBU_SEL_1, 1);
+			ioex_set_level(IOEX_USB_C0_MUX_SBU_SEL_0, 1);
+		} else {
+			/* Set the SBU lines to Intel CCD mode */
+			ioex_set_level(IOEX_USB_C0_MUX_SBU_SEL_1, 0);
+			ioex_set_level(IOEX_USB_C0_MUX_SBU_SEL_0, 0);
+		}
+	}
+}
+DECLARE_DEFERRED(board_connect_c0_sbu_deferred);
+
+__override void board_overcurrent_event(int port, int is_overcurrented)
+{
+	/*
+	 * Meteorlake PCH uses Virtual Wire for over current error,
+	 * hence Send 'Over Current Virtual Wire' eSPI signal.
+	 */
+	espi_send_vwire(espi_dev, port + ESPI_VWIRE_SIGNAL_SLV_GPIO_0,
+			!is_overcurrented);
+}
+
+void board_reset_pd_mcu(void)
+{
+	/* Reset NCT38XX TCPC */
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(usb_c0_c1_tcpc_rst_odl), 0);
+	msleep(NCT38XX_RESET_HOLD_DELAY_MS);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(usb_c0_c1_tcpc_rst_odl), 1);
+	nct38xx_reset_notify(0);
+	nct38xx_reset_notify(1);
+
+	if (NCT3807_RESET_POST_DELAY_MS != 0) {
+		msleep(NCT3807_RESET_POST_DELAY_MS);
+	}
+
+	/* NCT38XX chip uses gpio ioex */
+	gpio_reset_port(DEVICE_DT_GET(DT_NODELABEL(ioex_c0)));
+	gpio_reset_port(DEVICE_DT_GET(DT_NODELABEL(ioex_c1)));
+
+#if defined(HAS_TASK_PD_C2)
+	/* Reset the ccgxxf ports only resetting 1 is required */
+	ccgxxf_reset(USBC_PORT_C2);
+
+	/* CCGXXF has ioex on port 2 */
+	ioex_init(IOEX_C2_CCGXXF);
+#endif
+}
+
+void board_connect_c0_sbu(enum gpio_signal signal)
+{
+	hook_call_deferred(&board_connect_c0_sbu_deferred_data, 0);
+}
+
+/******************************************************************************/
+/* KSO mapping for discrete keyboard */
+__override const uint8_t it8801_kso_mapping[] = {
+	0, 1, 20, 3, 4, 5, 6, 11, 12, 13, 14, 15, 16,
+};
+BUILD_ASSERT(ARRAY_SIZE(it8801_kso_mapping) == KEYBOARD_COLS_MAX);
+
+/* PWROK signal configuration */
+/*
+ * On MTLRVP, SYS_PWROK_EC is an output controlled by EC and uses ALL_SYS_PWRGD
+ * as input.
+ */
+const struct intel_x86_pwrok_signal pwrok_signal_assert_list[] = {
+	{
+		.gpio = GPIO_PCH_SYS_PWROK,
+		.delay_ms = 3,
+	},
+};
+const int pwrok_signal_assert_count = ARRAY_SIZE(pwrok_signal_assert_list);
+
+const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[] = {
+	{
+		.gpio = GPIO_PCH_SYS_PWROK,
+	},
+};
+const int pwrok_signal_deassert_count = ARRAY_SIZE(pwrok_signal_deassert_list);
+
+/*
+ * Returns board information (board id[7:0] and Fab id[15:8]) on success
+ * -1 on error.
+ */
+__override int board_get_version(void)
+{
+	/* Cache the MTLRVP board ID */
+	static int mtlrvp_board_id;
+
+	int i;
+	int rv = EC_ERROR_UNKNOWN;
+	int fab_id, board_id, bom_id;
+
+	/* Board ID is already read */
+	if (mtlrvp_board_id)
+		return mtlrvp_board_id;
+
+	/*
+	 * IOExpander that has Board ID information is on DSW-VAL rail on
+	 * MTL RVP. On cold boot cycles, DSW-VAL rail is taking time to settle.
+	 * This loop retries to ensure rail is settled and read is successful
+	 */
+	for (i = 0; i < RVP_VERSION_READ_RETRY_CNT; i++) {
+		rv = gpio_pin_get_dt(&bom_id_config[0]);
+
+		if (rv >= 0)
+			break;
+
+		k_msleep(1);
+	}
+
+	/* return -1 if failed to read board id */
+	if (rv)
+		return -1;
+
+	/*
+	 * BOM ID [2]   : IOEX[0]
+	 * BOM ID [1:0] : IOEX[15:14]
+	 */
+	bom_id = gpio_pin_get_dt(&bom_id_config[0]) << 2;
+	bom_id |= gpio_pin_get_dt(&bom_id_config[1]) << 1;
+	bom_id |= gpio_pin_get_dt(&bom_id_config[2]);
+	/*
+	 * FAB ID [1:0] : IOEX[2:1] + 1
+	 */
+	fab_id = gpio_pin_get_dt(&fab_id_config[0]) << 1;
+	fab_id |= gpio_pin_get_dt(&fab_id_config[1]);
+	fab_id += 1;
+
+	/*
+	 * BOARD ID[5:0] : IOEX[13:8]
+	 */
+	board_id = gpio_pin_get_dt(&board_id_config[0]) << 5;
+	board_id |= gpio_pin_get_dt(&board_id_config[1]) << 4;
+	board_id |= gpio_pin_get_dt(&board_id_config[2]) << 3;
+	board_id |= gpio_pin_get_dt(&board_id_config[3]) << 2;
+	board_id |= gpio_pin_get_dt(&board_id_config[4]) << 1;
+	board_id |= gpio_pin_get_dt(&board_id_config[5]);
+
+	CPRINTF("BID:0x%x, FID:0x%x, BOM:0x%x", board_id, fab_id, bom_id);
+
+	mtlrvp_board_id = board_id | (fab_id << 8);
+	return mtlrvp_board_id;
+}
+
+static void board_int_init(void)
+{
+	/* Enable PPC interrupts. */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_ppc));
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_ppc));
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_c1_tcpc));
+#if defined(HAS_TASK_PD_C2)
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c2_tcpc));
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c3_tcpc));
+#endif
+
+	/* Enable CCD Mode interrupt */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_ccd_mode));
+
+	/* Enable DC jack interrupt */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_dc_jack_present));
+}
+
+static void configure_retimer_usbmux(void)
+{
+	switch (MTL_RVP_BOARD_ID(board_get_version())) {
+	case MTLP_LP5_RVP_SKU_BOARD_ID:
+		/* No retimer on Port 0 */
+		USB_MUX_ENABLE_ALTERNATIVE(usb_mux_alt_chain_0);
+		USB_MUX_ENABLE_ALTERNATIVE(usb_mux_alt_chain_1);
+#if defined(HAS_TASK_PD_C2)
+		USB_MUX_ENABLE_ALTERNATIVE(usb_mux_alt_chain_2);
+		USB_MUX_ENABLE_ALTERNATIVE(usb_mux_alt_chain_3);
+#endif
+		break;
+		/* Add additional board SKUs */
+	default:
+		break;
+	}
+}
+
+__override bool board_is_tbt_usb4_port(int port)
+{
+	bool tbt_usb4 = true;
+
+	switch (MTL_RVP_BOARD_ID(board_get_version())) {
+	case MTLP_LP5_RVP_SKU_BOARD_ID:
+		/* No retimer on port 0; and port 1 is not available */
+		if ((port == USBC_PORT_C0) || (port == USBC_PORT_C1))
+			tbt_usb4 = false;
+		break;
+	default:
+		break;
+	}
+	return tbt_usb4;
+}
+
+__override enum tbt_compat_cable_speed board_get_max_tbt_speed(int port)
+{
+	enum tbt_compat_cable_speed max_speed = TBT_SS_TBT_GEN3;
+
+	switch (MTL_RVP_BOARD_ID(board_get_version())) {
+	case MTLP_LP5_RVP_SKU_BOARD_ID:
+		if (port == USBC_PORT_C2)
+			max_speed = TBT_SS_U32_GEN1_GEN2;
+		break;
+	default:
+		break;
+	}
+
+	return max_speed;
+}
+
+static int board_pre_task_peripheral_init(void)
+{
+	/* Only reset tcpc/pd if not sysjump */
+	if (!system_jumped_late()) {
+		/* Initialize tcpc and all ioex */
+		board_reset_pd_mcu();
+	}
+
+	/* Initialize all interrupts */
+	board_int_init();
+
+	/* Make sure SBU are routed to CCD or AUX based on CCD status at init */
+	board_connect_c0_sbu_deferred();
+
+	/* Configure board specific retimer & mux */
+	configure_retimer_usbmux();
+
+	return 0;
+}
+SYS_INIT(board_pre_task_peripheral_init, APPLICATION,
+	 CONFIG_APPLICATION_INIT_PRIORITY);
+
+/*
+ * Since MTLRVP has both PPC and TCPC ports override to check if the port
+ * is a PPC or non PPC port
+ */
+__override bool pd_check_vbus_level(int port, enum vbus_level level)
+{
+	if (!board_port_has_ppc(port)) {
+		return tcpm_check_vbus_level(port, level);
+	} else if (level == VBUS_PRESENT) {
+		return pd_snk_is_vbus_provided(port);
+	} else {
+		return !pd_snk_is_vbus_provided(port);
+	}
+}
+
+__override bool board_port_has_ppc(int port)
+{
+	bool ppc_port;
+
+	switch (port) {
+	case USBC_PORT_C0:
+	case USBC_PORT_C1:
+		ppc_port = true;
+		break;
+	default:
+		ppc_port = false;
+		break;
+	}
+
+	return ppc_port;
+}
diff --git a/zephyr/program/intelrvp/mtlrvp/usbc.dts b/zephyr/program/intelrvp/mtlrvp/usbc.dts
new file mode 100644
index 0000000000..4821eedd48
--- /dev/null
+++ b/zephyr/program/intelrvp/mtlrvp/usbc.dts
@@ -0,0 +1,105 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		usbc_port0: port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+			tcpc = <&tcpc_port0>;
+			ppc = <&ppc_port0>;
+			chg = <&charger>;
+			usb_mux_chain_0: usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_c0_hb_retimer
+					     &virtual_mux_c0>;
+			};
+			usb_mux_alt_chain_0: usb-mux-atl-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				alternative-chain;
+				usb-muxes = <&virtual_mux_c0>;
+			};
+		};
+		port0-muxes {
+			virtual_mux_c0: virtual-mux-c0 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+
+		usbc_port1: port1@1 {
+			compatible = "named-usbc-port";
+			reg = <1>;
+			tcpc = <&tcpc_port1>;
+			ppc = <&ppc_port1>;
+			usb_mux_chain_1: usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_c1_hb_retimer
+					     &virtual_mux_c1>;
+			};
+
+			/* TODO:
+			 * LP5 doesn't have port 1; should remove PD_C1
+			 * task.
+			 */
+			usb_mux_alt_chain_1: usb-mux-alt-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				alternative-chain;
+				usb-muxes = <&virtual_mux_c1>;
+			};
+		};
+		port1-muxes {
+			virtual_mux_c1: virtual-mux-c1 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+
+		usbc_port2: port2@2 {
+			compatible = "named-usbc-port";
+			reg = <2>;
+			tcpc = <&tcpc_port2>;
+			usb_mux_chain_2: usb-mux-chain-2 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_c2_hb_retimer
+					     &virtual_mux_c2>;
+			};
+			usb_mux_alt_chain_2: usb-mux-alt-chain-2 {
+				compatible = "cros-ec,usb-mux-chain";
+				alternative-chain;
+				usb-muxes = <&usb_c2_alt_hb_retimer
+					     &virtual_mux_c2>;
+			};
+		};
+		port2-muxes {
+			virtual_mux_c2: virtual-mux-c2 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+
+		usbc_port3: port3@3 {
+			compatible = "named-usbc-port";
+			reg = <3>;
+			tcpc = <&tcpc_port3>;
+			usb_mux_chain_3: usb-mux-chain-3 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_c3_hb_retimer
+					     &virtual_mux_c3>;
+			};
+			usb_mux_alt_chain_3: usb-mux-alt-chain-3 {
+				compatible = "cros-ec,usb-mux-chain";
+				alternative-chain;
+				usb-muxes = <&usb_c3_alt_hb_retimer
+					     &virtual_mux_c3>;
+			};
+		};
+		port3-muxes {
+			virtual_mux_c3: virtual-mux-c3 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+	};
+};
diff --git a/zephyr/program/intelrvp/prj.conf b/zephyr/program/intelrvp/prj.conf
new file mode 100644
index 0000000000..1035256d95
--- /dev/null
+++ b/zephyr/program/intelrvp/prj.conf
@@ -0,0 +1,61 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+
+CONFIG_CROS_EC=y
+CONFIG_LTO=y
+CONFIG_PLATFORM_EC=y
+CONFIG_PLATFORM_EC_POWER_BUTTON=y
+CONFIG_PLATFORM_EC_LID_SWITCH=y
+CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y
+
+# Battery
+CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y
+CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y
+CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO=y
+CONFIG_PLATFORM_EC_BATTERY_REVIVE_DISCONNECT=y
+CONFIG_PLATFORM_EC_BATTERY_TYPE_NO_AUTO_DETECT=y
+CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT=15000
+CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON=15001
+CONFIG_PLATFORM_EC_CHARGER_MIN_INPUT_CURRENT_LIMIT=512
+
+#Power Sequencing
+CONFIG_PLATFORM_EC_BOARD_RESET_AFTER_POWER_ON=y
+
+# Host command
+CONFIG_PLATFORM_EC_HOSTCMD_AP_RESET=y
+CONFIG_PLATFORM_EC_PORT80=y
+
+# USB-C and PD
+CONFIG_PLATFORM_EC_USB_VID=0x18d1
+CONFIG_PLATFORM_EC_USB_PID=0x8086
+CONFIG_PLATFORM_EC_USB_PD_REQUIRE_AP_MODE_ENTRY=y
+CONFIG_PLATFORM_EC_TCPC_INTERRUPT=n
+
+# eSPI
+CONFIG_ESPI=y
+CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S3=y
+CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S4=y
+CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S5=y
+
+# Keyboard
+CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_8042=y
+CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED=y
+CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI2=y
+CONFIG_PLATFORM_EC_VOLUME_BUTTONS=y
+CONFIG_PLATFORM_EC_CMD_BUTTON=n
+
+# Shell Commands
+CONFIG_SHELL_HELP=y
+CONFIG_SHELL_HISTORY=y
+CONFIG_SHELL_TAB=y
+CONFIG_SHELL_TAB_AUTOCOMPLETION=y
+CONFIG_KERNEL_SHELL=y
+
+CONFIG_SYSTEM_BOOT_TIME_LOGGING=y
+
+# TODO
+# Below conf are disabled to compile successfully
+# These will be enabled in upcoming CLs
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
diff --git a/zephyr/program/intelrvp/src/chg_usb_pd.c b/zephyr/program/intelrvp/src/chg_usb_pd.c
new file mode 100644
index 0000000000..1b2c1a8736
--- /dev/null
+++ b/zephyr/program/intelrvp/src/chg_usb_pd.c
@@ -0,0 +1,122 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Common USB PD charge configuration */
+
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "intelrvp.h"
+#include "tcpm/tcpci.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+bool is_typec_port(int port)
+{
+#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
+	return !(port == DEDICATED_CHARGE_PORT || port == CHARGE_PORT_NONE);
+#else
+	return !(port == CHARGE_PORT_NONE);
+#endif /* CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 */
+}
+
+static inline int board_dc_jack_present(void)
+{
+#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
+	return gpio_get_level(GPIO_DC_JACK_PRESENT);
+#else
+	return 0;
+#endif /* CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 */
+}
+
+static void board_dc_jack_handle(void)
+{
+#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
+	struct charge_port_info charge_dc_jack;
+
+	/* System is booted from DC Jack */
+	if (board_dc_jack_present()) {
+		charge_dc_jack.current =
+			(PD_MAX_POWER_MW * 1000) / DC_JACK_MAX_VOLTAGE_MV;
+		charge_dc_jack.voltage = DC_JACK_MAX_VOLTAGE_MV;
+	} else {
+		charge_dc_jack.current = 0;
+		charge_dc_jack.voltage = USB_CHARGER_VOLTAGE_MV;
+	}
+
+	charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED,
+				     DEDICATED_CHARGE_PORT, &charge_dc_jack);
+#endif /* CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 */
+}
+
+void board_dc_jack_interrupt(enum gpio_signal signal)
+{
+	board_dc_jack_handle();
+}
+
+static void board_charge_init(void)
+{
+	int port, supplier;
+	struct charge_port_info charge_init = {
+		.current = 0,
+		.voltage = USB_CHARGER_VOLTAGE_MV,
+	};
+
+	/* Initialize all charge suppliers to seed the charge manager */
+	for (port = 0; port < CHARGE_PORT_COUNT; port++) {
+		for (supplier = 0; supplier < CHARGE_SUPPLIER_COUNT;
+		     supplier++) {
+			charge_manager_update_charge(supplier, port,
+						     &charge_init);
+		}
+	}
+
+	board_dc_jack_handle();
+}
+DECLARE_HOOK(HOOK_INIT, board_charge_init, HOOK_PRIO_DEFAULT);
+
+int board_set_active_charge_port(int port)
+{
+	int i;
+	/* charge port is a realy physical port */
+	int is_real_port = (port >= 0 && port < CHARGE_PORT_COUNT);
+	/* check if we are source vbus on that port */
+	int source = board_vbus_source_enabled(port);
+
+	if (is_real_port && source) {
+		CPRINTS("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
+	/*
+	 * Do not enable Type-C port if the DC Jack is present.
+	 * When the Type-C is active port, hardware circuit will
+	 * block DC jack from enabling +VADP_OUT.
+	 */
+	if (port != DEDICATED_CHARGE_PORT && board_dc_jack_present()) {
+		CPRINTS("DC Jack present, Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+#endif /* CONFIG_DEDICATED_CHARGE_PORT_COUNT */
+
+	/* Make sure non-charging ports are disabled */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		if (i != port) {
+			board_charging_enable(i, 0);
+		}
+	}
+
+	/* Enable charging port */
+	if (is_typec_port(port)) {
+		board_charging_enable(port, 1);
+	}
+
+	CPRINTS("New chg p%d", port);
+
+	return EC_SUCCESS;
+}
diff --git a/zephyr/program/intelrvp/src/chg_usb_pd_mecc_1_1.c b/zephyr/program/intelrvp/src/chg_usb_pd_mecc_1_1.c
new file mode 100644
index 0000000000..f05dc2e837
--- /dev/null
+++ b/zephyr/program/intelrvp/src/chg_usb_pd_mecc_1_1.c
@@ -0,0 +1,75 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel-RVP family-specific configuration */
+
+#include "console.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "include/gpio.h"
+#include "intelrvp.h"
+#include "ioexpander.h"
+#include "system.h"
+#include "tcpm/tcpci.h"
+#include "usbc_ppc.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+	int i;
+
+	/* Check which port has the ALERT line set */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		/* No alerts for embdeded TCPC */
+		if (tcpc_config[i].bus_type == EC_BUS_TYPE_EMBEDDED) {
+			continue;
+		}
+
+		if (!gpio_get_level(tcpc_aic_gpios[i].tcpc_alert)) {
+			status |= PD_STATUS_TCPC_ALERT_0 << i;
+		}
+	}
+
+	return status;
+}
+
+int ppc_get_alert_status(int port)
+{
+	return tcpc_aic_gpios[port].ppc_intr_handler &&
+	       !gpio_get_level(tcpc_aic_gpios[port].ppc_alert);
+}
+
+/* PPC support routines */
+void ppc_interrupt(enum gpio_signal signal)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		if (tcpc_aic_gpios[i].ppc_intr_handler &&
+		    signal == tcpc_aic_gpios[i].ppc_alert) {
+			tcpc_aic_gpios[i].ppc_intr_handler(i);
+			break;
+		}
+	}
+}
+
+void board_charging_enable(int port, int enable)
+{
+	int rv;
+
+	if (tcpc_aic_gpios[port].ppc_intr_handler) {
+		rv = ppc_vbus_sink_enable(port, enable);
+	} else {
+		rv = tcpc_config[port].drv->set_snk_ctrl(port, enable);
+	}
+
+	if (rv) {
+		CPRINTS("C%d: sink path %s failed", port,
+			enable ? "en" : "dis");
+	}
+}
diff --git a/zephyr/program/intelrvp/src/intel_rvp_board_id.c b/zephyr/program/intelrvp/src/intel_rvp_board_id.c
new file mode 100644
index 0000000000..7062cb74b9
--- /dev/null
+++ b/zephyr/program/intelrvp/src/intel_rvp_board_id.c
@@ -0,0 +1,31 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "intel_rvp_board_id.h"
+
+#include <zephyr/devicetree.h>
+
+#define DT_DRV_COMPAT intel_rvp_board_id
+
+BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) <= 1,
+	     "Unsupported RVP Board ID instance");
+
+#define RVP_ID_GPIO_DT_SPEC_GET(idx, node_id, prop) \
+	GPIO_DT_SPEC_GET_BY_IDX(node_id, prop, idx),
+
+#define RVP_ID_CONFIG_LIST(node_id, prop)                                \
+	LISTIFY(DT_PROP_LEN(node_id, prop), RVP_ID_GPIO_DT_SPEC_GET, (), \
+		node_id, prop)
+
+#if DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT)
+const struct gpio_dt_spec bom_id_config[] = { RVP_ID_CONFIG_LIST(DT_DRV_INST(0),
+								 bom_gpios) };
+
+const struct gpio_dt_spec fab_id_config[] = { RVP_ID_CONFIG_LIST(DT_DRV_INST(0),
+								 fab_gpios) };
+
+const struct gpio_dt_spec board_id_config[] = { RVP_ID_CONFIG_LIST(
+	DT_DRV_INST(0), board_gpios) };
+#endif /* #if DT_HAS_COMPAT_STATUS_OKAY */
diff --git a/zephyr/program/intelrvp/src/intel_rvp_led.c b/zephyr/program/intelrvp/src/intel_rvp_led.c
new file mode 100644
index 0000000000..e9a8eff4ba
--- /dev/null
+++ b/zephyr/program/intelrvp/src/intel_rvp_led.c
@@ -0,0 +1,167 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "extpower.h"
+#include "hooks.h"
+#include "led_common.h"
+#include "led_pwm.h"
+#include "pwm.h"
+#include "timer.h"
+#include "util.h"
+
+/* Battery percentage thresholds to blink at different rates. */
+#define LOW_BATTERY_PERCENTAGE 10
+#define NORMAL_BATTERY_PERCENTAGE 90
+
+#define LED_OFF -1
+
+#define LED_PULSE_TICK (125 * MSEC)
+
+#define LED_FAST_PULSE_PERIOD (250 / 125) /* 250 ms */
+#define LED_SLOW_PULSE_PERIOD ((2 * MSEC) / 125) /* 2 sec  */
+
+struct led_pulse_data {
+	bool led_is_pulsing;
+	uint8_t led_pulse_period;
+	uint8_t led_tick_count;
+};
+
+static struct led_pulse_data rvp_led[CONFIG_LED_PWM_COUNT];
+
+static void pulse_led_deferred(void);
+DECLARE_DEFERRED(pulse_led_deferred);
+
+static void pulse_led_deferred(void)
+{
+	int i = 0;
+	bool call_deferred = false;
+
+	for (i = 0; i < CONFIG_LED_PWM_COUNT; i++) {
+		if (!rvp_led[i].led_is_pulsing) {
+			rvp_led[i].led_tick_count = 0;
+			continue;
+		}
+
+		/*
+		 * LED will be in ON state first half of the pulse period
+		 * and in OFF state in second half of the pulse period.
+		 */
+		if (rvp_led[i].led_tick_count <
+		    (rvp_led[i].led_pulse_period >> 1))
+			set_pwm_led_color(i, EC_LED_COLOR_GREEN);
+		else
+			set_pwm_led_color(i, LED_OFF);
+
+		rvp_led[i].led_tick_count = (rvp_led[i].led_tick_count + 1) %
+					    rvp_led[i].led_pulse_period;
+		call_deferred = true;
+	}
+
+	if (call_deferred)
+		hook_call_deferred(&pulse_led_deferred_data, LED_PULSE_TICK);
+}
+
+static void pulse_leds(enum pwm_led_id id, int period)
+{
+	rvp_led[id].led_pulse_period = period;
+	rvp_led[id].led_is_pulsing = true;
+
+	pulse_led_deferred();
+}
+
+static void update_charger_led(enum pwm_led_id id)
+{
+	enum led_pwr_state chg_st = led_pwr_get_state();
+
+	/*
+	 * The colors listed below are the default, but can be overridden.
+	 *
+	 * Fast Flash = Charging error
+	 * Slow Flash = Discharging
+	 * LED on     = Charging
+	 * LED off    = No Charger connected
+	 */
+	if (chg_st == LED_PWRS_CHARGE || chg_st == LED_PWRS_CHARGE_NEAR_FULL) {
+		/* Charging: LED ON */
+		rvp_led[id].led_is_pulsing = false;
+		set_pwm_led_color(id, EC_LED_COLOR_GREEN);
+	} else if (chg_st == LED_PWRS_DISCHARGE ||
+		   chg_st == LED_PWRS_DISCHARGE_FULL) {
+		if (extpower_is_present()) {
+			/* Discharging:
+			 * Flash slower (2 second period, 100% duty cycle)
+			 */
+			pulse_leds(id, LED_SLOW_PULSE_PERIOD);
+		} else {
+			/* No Charger connected: LED OFF */
+			rvp_led[id].led_is_pulsing = false;
+			set_pwm_led_color(id, LED_OFF);
+		}
+	} else if (chg_st == LED_PWRS_ERROR) {
+		/* Charging error:
+		 * Flash faster (250 ms period, 100% duty cycle)
+		 */
+		pulse_leds(id, LED_FAST_PULSE_PERIOD);
+	} else {
+		/* LED OFF */
+		rvp_led[id].led_is_pulsing = false;
+		set_pwm_led_color(id, LED_OFF);
+	}
+}
+
+static void update_battery_led(enum pwm_led_id id)
+{
+	/*
+	 * Fast Flash = Low Battery
+	 * Slow Flash = Normal Battery
+	 * LED on     = Full Battery
+	 * LED off    = No Battery
+	 */
+	if (battery_is_present() == BP_YES) {
+		int batt_percentage = charge_get_percent();
+
+		if (batt_percentage < LOW_BATTERY_PERCENTAGE) {
+			/* Low Battery:
+			 * Flash faster (250 ms period, 100% duty cycle)
+			 */
+			pulse_leds(id, LED_FAST_PULSE_PERIOD);
+		} else if (batt_percentage < NORMAL_BATTERY_PERCENTAGE) {
+			/* Normal Battery:
+			 * Flash slower (2 second period, 100% duty cycle)
+			 */
+			pulse_leds(id, LED_SLOW_PULSE_PERIOD);
+		} else {
+			/* Full Battery: LED ON */
+			rvp_led[id].led_is_pulsing = false;
+			set_pwm_led_color(id, EC_LED_COLOR_GREEN);
+		}
+	} else {
+		/* No Battery: LED OFF */
+		rvp_led[id].led_is_pulsing = false;
+		set_pwm_led_color(id, LED_OFF);
+	}
+}
+
+static void init_rvp_leds_off(void)
+{
+	/* Turn off LEDs such that they are in a known state with zero duty. */
+	set_pwm_led_color(PWM_LED0, LED_OFF);
+	set_pwm_led_color(PWM_LED1, LED_OFF);
+}
+DECLARE_HOOK(HOOK_INIT, init_rvp_leds_off, HOOK_PRIO_POST_PWM);
+
+static void update_led(void)
+{
+	update_battery_led(PWM_LED0);
+	update_charger_led(PWM_LED1);
+}
+DECLARE_HOOK(HOOK_SECOND, update_led, HOOK_PRIO_DEFAULT);
diff --git a/zephyr/program/intelrvp/src/intelrvp.c b/zephyr/program/intelrvp/src/intelrvp.c
new file mode 100644
index 0000000000..7098f26cbf
--- /dev/null
+++ b/zephyr/program/intelrvp/src/intelrvp.c
@@ -0,0 +1,25 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* TODO: b/218904113: Convert to using Zephyr GPIOs */
+#include "gpio.h"
+#include "hooks.h"
+
+static void board_init(void)
+{
+	/* Enable SOC SPI */
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(ec_spi_oe_mecc), 1);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_LAST);
+
+__override void intel_x86_sys_reset_delay(void)
+{
+	/*
+	 * From MAX6818 Data sheet, Range of 'Debounce Duaration' is
+	 * Minimum - 20 ms, Typical - 40 ms, Maximum - 80 ms.
+	 * See b/153128296.
+	 */
+	udelay(60 * MSEC);
+}
diff --git a/zephyr/program/intelrvp/src/usb_pd_policy_mecc_1_1.c b/zephyr/program/intelrvp/src/usb_pd_policy_mecc_1_1.c
new file mode 100644
index 0000000000..a194b358f1
--- /dev/null
+++ b/zephyr/program/intelrvp/src/usb_pd_policy_mecc_1_1.c
@@ -0,0 +1,106 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "gpio.h"
+#include "intelrvp.h"
+#include "usb_mux.h"
+#include "usbc_ppc.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+static inline void board_pd_set_vbus_discharge(int port, bool enable)
+{
+	if (tcpc_aic_gpios[port].ppc_intr_handler) {
+		ppc_discharge_vbus(port, enable);
+	} else {
+		tcpc_discharge_vbus(port, enable);
+	}
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	/* Disable charging. */
+	if (tcpc_aic_gpios[port].ppc_intr_handler) {
+		rv = ppc_vbus_sink_enable(port, 0);
+	} else {
+		rv = tcpc_config[port].drv->set_snk_ctrl(port, 0);
+	}
+
+	if (rv) {
+		return rv;
+	}
+
+	board_pd_set_vbus_discharge(port, false);
+
+	/* Provide Vbus. */
+	if (tcpc_aic_gpios[port].ppc_intr_handler) {
+		rv = ppc_vbus_source_enable(port, 1);
+	} else {
+		tcpc_config[port].drv->set_src_ctrl(port, 1);
+	}
+
+	if (rv) {
+		return rv;
+	}
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+void pd_power_supply_reset(int port)
+{
+	int prev_en;
+
+	prev_en = board_vbus_source_enabled(port);
+
+	/* Disable VBUS. */
+	if (tcpc_aic_gpios[port].ppc_intr_handler) {
+		ppc_vbus_source_enable(port, 0);
+	} else {
+		tcpc_config[port].drv->set_src_ctrl(port, 0);
+	}
+
+	/* Enable discharge if we were previously sourcing 5V */
+	if (prev_en) {
+		board_pd_set_vbus_discharge(port, true);
+	}
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_check_vconn_swap(int port)
+{
+	/* Only allow vconn swap if PP3300 rail is enabled */
+	return gpio_get_level(GPIO_EN_PP3300_A);
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	if (tcpc_aic_gpios[port].ppc_intr_handler) {
+		return ppc_is_vbus_present(port);
+	} else {
+		return tcpc_config[port].drv->check_vbus_level(port,
+							       VBUS_PRESENT);
+	}
+}
+
+int board_vbus_source_enabled(int port)
+{
+	if (is_typec_port(port)) {
+		if (tcpc_aic_gpios[port].ppc_intr_handler) {
+			return ppc_is_sourcing_vbus(port);
+		} else {
+			return tcpc_config[port].drv->get_src_ctrl(port);
+		}
+	}
+	return 0;
+}
diff --git a/zephyr/program/intelrvp/zephyr_ap_pwrseq.conf b/zephyr/program/intelrvp/zephyr_ap_pwrseq.conf
new file mode 100644
index 0000000000..888106e738
--- /dev/null
+++ b/zephyr/program/intelrvp/zephyr_ap_pwrseq.conf
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Zephyr Inbuilt AP Power Sequencing Config
+CONFIG_X86_NON_DSX_PWRSEQ_CONSOLE=y
+CONFIG_X86_NON_DSX_PWRSEQ_HOST_CMD=y
+CONFIG_AP_PWRSEQ_S0IX=y
+CONFIG_AP_PWRSEQ_S0IX_ERROR_RECOVERY=y
diff --git a/zephyr/program/it8xxx2_evb/BUILD.py b/zephyr/program/it8xxx2_evb/BUILD.py
new file mode 100644
index 0000000000..86538ec96e
--- /dev/null
+++ b/zephyr/program/it8xxx2_evb/BUILD.py
@@ -0,0 +1,19 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Define zmake projects for it8xxx2_evb."""
+
+register_raw_project(
+    project_name="it8xxx2_evb",
+    zephyr_board="it81302bx",
+    dts_overlays=[
+        "adc.dts",
+        "fan.dts",
+        "gpio.dts",
+        "i2c.dts",
+        "interrupts.dts",
+        "pwm.dts",
+        "shi.dts",
+    ],
+)
diff --git a/zephyr/program/it8xxx2_evb/CMakeLists.txt b/zephyr/program/it8xxx2_evb/CMakeLists.txt
new file mode 100644
index 0000000000..170606a52d
--- /dev/null
+++ b/zephyr/program/it8xxx2_evb/CMakeLists.txt
@@ -0,0 +1,11 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(it8xxx2_evb)
+
+# Include board specific header files
+zephyr_include_directories(include)
diff --git a/zephyr/program/it8xxx2_evb/adc.dts b/zephyr/program/it8xxx2_evb/adc.dts
new file mode 100644
index 0000000000..509c9b9daf
--- /dev/null
+++ b/zephyr/program/it8xxx2_evb/adc.dts
@@ -0,0 +1,41 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		adc_vbussa: vbussa {
+			enum-name = "ADC_VBUS";
+			io-channels = <&adc0 0>;
+		};
+		adc_vbussb: vbussb {
+			enum-name = "ADC_PSYS";
+			io-channels = <&adc0 1>;
+		};
+		adc_evb_ch_13: evb_ch_13 {
+			enum-name = "ADC_AMON_BMON";
+			io-channels = <&adc0 2>;
+		};
+		adc_evb_ch_14: evb_ch_14 {
+			enum-name = "ADC_TEMP_SENSOR_FAN";
+			io-channels = <&adc0 3>;
+		};
+		adc_evb_ch_15: evb_ch_15 {
+			enum-name = "ADC_TEMP_SENSOR_DDR_SOC";
+			io-channels = <&adc0 4>;
+		};
+		adc_evb_ch_16: evb_ch_16 {
+			enum-name = "ADC_TEMP_SENSOR_CHARGER";
+			io-channels = <&adc0 5>;
+		};
+	};
+};
+
+&adc0 {
+	status = "okay";
+	pinctrl-0 = <&adc0_ch3_gpi3_default>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/it8xxx2_evb/fan.dts b/zephyr/program/it8xxx2_evb/fan.dts
new file mode 100644
index 0000000000..2551507ec3
--- /dev/null
+++ b/zephyr/program/it8xxx2_evb/fan.dts
@@ -0,0 +1,27 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	fans {
+		compatible = "cros-ec,fans";
+
+		fan_0 {
+			pwms = <&pwm7 PWM_CHANNEL_7 PWM_KHZ(30) PWM_POLARITY_NORMAL>;
+			tach = <&tach0>;
+			rpm_min = <1500>;
+			rpm_start = <1500>;
+			rpm_max = <6500>;
+		};
+	};
+};
+
+/* fan tachometer sensor */
+&tach0 {
+	status = "okay";
+	channel = <IT8XXX2_TACH_CHANNEL_A>;
+	pulses-per-round = <2>;
+	pinctrl-0 = <&tach0a_gpd6_default>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/it8xxx2_evb/gpio.dts b/zephyr/program/it8xxx2_evb/gpio.dts
new file mode 100644
index 0000000000..85bb45d7a0
--- /dev/null
+++ b/zephyr/program/it8xxx2_evb/gpio.dts
@@ -0,0 +1,169 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/gpio_defines.h>
+
+/ {
+	aliases {
+		gpio-wp = &gpio_wp;
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		power_button_l: power_button_l {
+			gpios = <&gpioe 4 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		lid_open: lid_open {
+			gpios = <&gpioe 2 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+		gpio_wp: wp_l {
+			gpios = <&gpioi 4 (GPIO_INPUT_PULL_UP |
+					   GPIO_ACTIVE_LOW)>;
+		};
+		pch_pltrst_l {
+			gpios = <&gpioe 3 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_PCH_RSMRST_L";
+		};
+		sys_reset_l {
+			gpios = <&gpiob 6 GPIO_OUTPUT_HIGH>;
+			enum-name = "GPIO_SYS_RESET_L";
+		};
+		gpio_ec_pch_wake_odl: pch_wake_l {
+			gpios = <&gpiob 7 GPIO_OUTPUT_HIGH>;
+		};
+		spi0_cs: spi0_cs {
+			gpios = <&gpiom 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		/* unimplemented GPIOs */
+		entering-rw {
+			enum-name = "GPIO_ENTERING_RW";
+		};
+	};
+
+	hibernate-wake-pins {
+		compatible = "cros-ec,hibernate-wake-pins";
+		wakeup-irqs = <&int_power_button
+			       &int_lid_open>;
+	};
+
+	unused-pins {
+		compatible = "unused-gpios";
+
+		unused-gpios =
+			/* gpioa1 */
+			<&gpioa 1 GPIO_INPUT_PULL_DOWN>,
+			/* gpioa2 */
+			<&gpioa 2 GPIO_INPUT_PULL_DOWN>,
+			/* gpioa3 */
+			<&gpioa 3 GPIO_INPUT_PULL_DOWN>,
+			/* gpioa4 */
+			<&gpioa 4 GPIO_INPUT_PULL_DOWN>,
+			/* gpioa5 */
+			<&gpioa 5 GPIO_INPUT_PULL_DOWN>,
+
+			/* gpiob2 */
+			<&gpiob 2 GPIO_INPUT_PULL_DOWN>,
+			/* gpiob5 */
+			<&gpiob 5 GPIO_INPUT_PULL_DOWN>,
+
+			/* gpioc0 */
+			<&gpioc 0 GPIO_INPUT_PULL_DOWN>,
+			/* gpioc4 */
+			<&gpioc 4 GPIO_INPUT_PULL_DOWN>,
+			/* gpioc6 */
+			<&gpioc 6 GPIO_INPUT_PULL_DOWN>,
+			/* gpioc7 */
+			<&gpioc 7 GPIO_INPUT_PULL_DOWN>,
+
+			/* gpiod0 */
+			<&gpiod 0 GPIO_INPUT_PULL_DOWN>,
+			/* gpiod1 */
+			<&gpiod 1 GPIO_INPUT_PULL_DOWN>,
+			/* gpiod2 */
+			<&gpiod 2 GPIO_INPUT_PULL_DOWN>,
+			/* gpiod3 */
+			<&gpiod 3 GPIO_INPUT_PULL_DOWN>,
+			/* gpiod4 */
+			<&gpiod 4 GPIO_INPUT_PULL_DOWN>,
+			/* gpiod5 */
+			<&gpiod 5 GPIO_INPUT_PULL_DOWN>,
+			/* gpiod7 */
+			<&gpiod 7 GPIO_INPUT_PULL_DOWN>,
+
+			/* gpioe1 */
+			<&gpioe 1 GPIO_INPUT_PULL_DOWN>,
+			/* gpioe5 */
+			<&gpioe 5 GPIO_INPUT_PULL_DOWN>,
+			/* gpioe6 */
+			<&gpioe 6 GPIO_INPUT_PULL_DOWN>,
+
+			/* gpiof0 */
+			<&gpiof 0 GPIO_INPUT_PULL_DOWN>,
+			/* gpiof1 */
+			<&gpiof 1 GPIO_INPUT_PULL_DOWN>,
+			/* gpiof2 */
+			<&gpiof 2 GPIO_INPUT_PULL_DOWN>,
+			/* gpiof3 */
+			<&gpiof 3 GPIO_INPUT_PULL_DOWN>,
+			/* gpiof4 */
+			<&gpiof 4 GPIO_INPUT_PULL_DOWN>,
+			/* gpiof5 */
+			<&gpiof 5 GPIO_INPUT_PULL_DOWN>,
+
+			/* gpiog1 */
+			<&gpiog 1 GPIO_INPUT_PULL_DOWN>,
+			/* gpiog6 */
+			<&gpiog 6 GPIO_INPUT_PULL_UP>,
+
+			/* gpioh0 */
+			<&gpioh 0 GPIO_INPUT_PULL_DOWN>,
+			/* gpioh3 */
+			<&gpioh 3 GPIO_INPUT_PULL_DOWN>,
+			/* gpioh4 */
+			<&gpioh 4 GPIO_INPUT_PULL_DOWN>,
+			/* gpioh5 */
+			<&gpioh 5 GPIO_INPUT_PULL_DOWN>,
+			/* gpioh6 */
+			<&gpioh 6 GPIO_INPUT_PULL_DOWN>,
+
+			/* gpioi6 */
+			<&gpioi 6 GPIO_INPUT_PULL_DOWN>,
+			/* gpioi7 */
+			<&gpioi 7 GPIO_INPUT_PULL_DOWN>,
+
+			/* gpioj0 */
+			<&gpioj 0 GPIO_INPUT_PULL_DOWN>,
+			/* gpioj1 */
+			<&gpioj 1 GPIO_INPUT_PULL_DOWN>,
+			/* gpioj2 */
+			<&gpioj 2 GPIO_INPUT_PULL_DOWN>,
+			/* gpioj3 */
+			<&gpioj 3 GPIO_INPUT_PULL_DOWN>,
+			/* gpioj4 */
+			<&gpioj 4 GPIO_INPUT_PULL_DOWN>,
+			/* gpioj5 */
+			<&gpioj 5 GPIO_INPUT_PULL_DOWN>,
+			/* gpioj6 */
+			<&gpioj 6 GPIO_OUTPUT_LOW>,
+			/* gpioj7 */
+			<&gpioj 7 GPIO_OUTPUT_LOW>,
+
+			/* gpiom0 */
+			<&gpiom 0 GPIO_INPUT_PULL_DOWN>,
+			/* gpiom1 */
+			<&gpiom 1 GPIO_INPUT_PULL_DOWN>,
+			/* gpiom2 */
+			<&gpiom 2 GPIO_INPUT_PULL_DOWN>,
+			/* gpiom3 */
+			<&gpiom 3 GPIO_INPUT_PULL_DOWN>,
+			/* gpiom4 */
+			<&gpiom 4 GPIO_INPUT_PULL_DOWN>,
+			/* gpiom6 */
+			<&gpiom 6 GPIO_INPUT_PULL_DOWN>;
+	};
+};
diff --git a/zephyr/program/it8xxx2_evb/i2c.dts b/zephyr/program/it8xxx2_evb/i2c.dts
new file mode 100644
index 0000000000..c08c543e44
--- /dev/null
+++ b/zephyr/program/it8xxx2_evb/i2c.dts
@@ -0,0 +1,59 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		battery {
+			i2c-port = <&i2c2>;
+			enum-names = "I2C_PORT_BATTERY";
+		};
+		evb-1 {
+			i2c-port = <&i2c0>;
+			enum-names = "I2C_PORT_EVB_1";
+		};
+		evb-2 {
+			i2c-port = <&i2c1>;
+			enum-names = "I2C_PORT_EVB_2";
+		};
+		opt-4 {
+			i2c-port = <&i2c4>;
+			enum-names = "I2C_PORT_OPT_4";
+		};
+	};
+};
+
+&i2c0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	pinctrl-0 = <&i2c0_clk_gpb3_default
+		     &i2c0_data_gpb4_default>;
+	pinctrl-names = "default";
+};
+
+&i2c1 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	pinctrl-0 = <&i2c1_clk_gpc1_default
+		     &i2c1_data_gpc2_default>;
+	pinctrl-names = "default";
+};
+
+&i2c2 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	pinctrl-0 = <&i2c2_clk_gpf6_default
+		     &i2c2_data_gpf7_default>;
+	pinctrl-names = "default";
+};
+
+&i2c4 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	pinctrl-0 = <&i2c4_clk_gpe0_default
+		     &i2c4_data_gpe7_default>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/it8xxx2_evb/include/i2c_map.h b/zephyr/program/it8xxx2_evb/include/i2c_map.h
new file mode 100644
index 0000000000..a6878e8bae
--- /dev/null
+++ b/zephyr/program/it8xxx2_evb/include/i2c_map.h
@@ -0,0 +1,16 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __ZEPHYR_CHROME_I2C_MAP_H
+#define __ZEPHYR_CHROME_I2C_MAP_H
+
+#include "config.h"
+
+#include <zephyr/devicetree.h>
+
+/* We need registers.h to get the chip specific defines for now */
+#include "i2c/i2c.h"
+
+#endif /* __ZEPHYR_CHROME_I2C_MAP_H */
diff --git a/zephyr/program/it8xxx2_evb/interrupts.dts b/zephyr/program/it8xxx2_evb/interrupts.dts
new file mode 100644
index 0000000000..07fc0ed339
--- /dev/null
+++ b/zephyr/program/it8xxx2_evb/interrupts.dts
@@ -0,0 +1,26 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_power_button: power_button {
+			irq-pin = <&power_button_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_button_interrupt";
+		};
+		int_lid_open: lid_open {
+			irq-pin = <&lid_open>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "lid_interrupt";
+		};
+		int_spi0_cs: spi0_cs {
+			irq-pin = <&spi0_cs>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "spi_event";
+		};
+	};
+};
diff --git a/zephyr/program/it8xxx2_evb/prj.conf b/zephyr/program/it8xxx2_evb/prj.conf
new file mode 100644
index 0000000000..cf696c80fa
--- /dev/null
+++ b/zephyr/program/it8xxx2_evb/prj.conf
@@ -0,0 +1,29 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_CROS_EC=y
+CONFIG_PLATFORM_EC=y
+
+# SoC configuration
+CONFIG_AP=y
+CONFIG_AP_ARM_MTK_MT8192=y
+
+# Lid switch
+CONFIG_PLATFORM_EC_LID_SWITCH=y
+
+# Power Button
+CONFIG_PLATFORM_EC_POWER_BUTTON=y
+
+# TODO(b:185202623): bring these features up
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
+CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=n
+CONFIG_PLATFORM_EC_BOARD_VERSION_GPIO=n
+CONFIG_PLATFORM_EC_KEYBOARD=n
+CONFIG_PLATFORM_EC_SWITCH=n
+CONFIG_PLATFORM_EC_VBOOT_EFS2=n
+CONFIG_PLATFORM_EC_VBOOT_HASH=n
+
+# USB-C
+CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=n
+CONFIG_PLATFORM_EC_USB_PD_USB4=n
diff --git a/zephyr/program/it8xxx2_evb/pwm.dts b/zephyr/program/it8xxx2_evb/pwm.dts
new file mode 100644
index 0000000000..c566e5c029
--- /dev/null
+++ b/zephyr/program/it8xxx2_evb/pwm.dts
@@ -0,0 +1,31 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	pwmleds {
+		compatible = "pwm-leds";
+
+		/* NOTE: &pwm number needs same with channel number */
+		pwm_led_test: pwm_led_test {
+			pwms = <&pwm0 PWM_CHANNEL_0 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
+		};
+	};
+};
+
+/* pwm for test */
+&pwm0 {
+	status = "okay";
+	prescaler-cx = <PWM_PRESCALER_C6>;
+	pinctrl-0 = <&pwm0_gpa0_default>;
+	pinctrl-names = "default";
+};
+
+/* pwm for fan */
+&pwm7 {
+	status = "okay";
+	prescaler-cx = <PWM_PRESCALER_C4>;
+	pinctrl-0 = <&pwm7_gpa7_default>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/it8xxx2_evb/shi.dts b/zephyr/program/it8xxx2_evb/shi.dts
new file mode 100644
index 0000000000..1a21a3ffb8
--- /dev/null
+++ b/zephyr/program/it8xxx2_evb/shi.dts
@@ -0,0 +1,15 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <ite/it8xxx2-pinctrl-map.dtsi>
+
+&shi0 {
+	status = "okay";
+	pinctrl-0 = <&shi_mosi_gpm0_default &shi_miso_gpm1_default
+		     &shi_clk_gpm4_default &shi_cs_gpm5_default>;
+	pinctrl-names = "default";
+	/* unused but needed by dt binding */
+	cs-gpios = <&gpiom 5 GPIO_VOLTAGE_1P8>;
+};
diff --git a/zephyr/program/minimal/BUILD.py b/zephyr/program/minimal/BUILD.py
new file mode 100644
index 0000000000..5e892aa2d7
--- /dev/null
+++ b/zephyr/program/minimal/BUILD.py
@@ -0,0 +1,22 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Minimal example project."""
+
+register_host_project(
+    project_name="minimal-posix",
+    zephyr_board="native_posix",
+)
+
+register_npcx_project(
+    project_name="minimal-npcx9",
+    zephyr_board="npcx9m3f",
+    dts_overlays=[here / "npcx9.dts"],
+)
+
+register_binman_project(
+    project_name="minimal-it8xxx2",
+    zephyr_board="it81302bx",
+    dts_overlays=[here / "it8xxx2.dts"],
+)
diff --git a/zephyr/program/minimal/CMakeLists.txt b/zephyr/program/minimal/CMakeLists.txt
new file mode 100644
index 0000000000..de3bec9428
--- /dev/null
+++ b/zephyr/program/minimal/CMakeLists.txt
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.20.5)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(ec)
+
+zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}/include")
diff --git a/zephyr/program/minimal/README.md b/zephyr/program/minimal/README.md
new file mode 100644
index 0000000000..72c092dfce
--- /dev/null
+++ b/zephyr/program/minimal/README.md
@@ -0,0 +1,32 @@
+# Minimal Example Zephyr EC Project
+
+This directory is intended to be an extremely minimal example of a
+project.  Should you like, you can use it as a bring up a new program,
+or as reference as you require.
+
+If you're bringing up a new variant of a program, you don't need a
+whole project directory with a `BUILD.py` and all, and this example is
+likely not of use to you.  Check out the [project config
+documentation] for instructions on adding a new variant.
+
+[project config documentation]: ../../../docs/zephyr/project_config.md
+
+# Building
+
+To build the `native_posix` example, run:
+
+``` shellsession
+(chroot) $ zmake build minimal-posix
+```
+
+To build the NPCX9 example, run:
+
+``` shellsession
+(chroot) $ zmake build minimal-npcx9
+```
+
+For the IT8XXX2 example, run:
+
+``` shellsession
+(chroot) $ zmake build minimal-it8xxx2
+```
diff --git a/zephyr/program/minimal/it8xxx2.dts b/zephyr/program/minimal/it8xxx2.dts
new file mode 100644
index 0000000000..3d2028afb2
--- /dev/null
+++ b/zephyr/program/minimal/it8xxx2.dts
@@ -0,0 +1,22 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	aliases {
+		gpio-wp = &ec_wp_l;
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		ec_wp_l: write-protect {
+			gpios = <&gpioa 0 GPIO_INPUT>;
+		};
+		/* unimplemented GPIOs */
+		entering-rw {
+			enum-name = "GPIO_ENTERING_RW";
+		};
+	};
+};
diff --git a/zephyr/program/minimal/npcx9.dts b/zephyr/program/minimal/npcx9.dts
new file mode 100644
index 0000000000..3a9f3b26e4
--- /dev/null
+++ b/zephyr/program/minimal/npcx9.dts
@@ -0,0 +1,28 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	aliases {
+		gpio-wp = &ec_wp_l;
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		ec_wp_l: write-protect {
+			gpios = <&gpioa 0 GPIO_INPUT>;
+		};
+		/* unimplemented GPIOs */
+		entering-rw {
+			enum-name = "GPIO_ENTERING_RW";
+		};
+	};
+};
+
+&cros_kb_raw {
+	status = "okay";
+	pinctrl-0 = <>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/minimal/prj.conf b/zephyr/program/minimal/prj.conf
new file mode 100644
index 0000000000..159fe58f44
--- /dev/null
+++ b/zephyr/program/minimal/prj.conf
@@ -0,0 +1,18 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_PLATFORM_EC=y
+CONFIG_CROS_EC=y
+CONFIG_SHIMMED_TASKS=y
+CONFIG_SYSCON=y
+
+# Disable default features we don't want in a minimal example.
+CONFIG_NAMED_ADC_CHANNELS=n
+CONFIG_PWM=n
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
+CONFIG_PLATFORM_EC_KEYBOARD=n
+CONFIG_PLATFORM_EC_POWER_BUTTON=n
+CONFIG_PLATFORM_EC_SWITCH=n
+CONFIG_PLATFORM_EC_VBOOT_EFS2=n
+CONFIG_PLATFORM_EC_I2C=n
diff --git a/zephyr/program/myst/BUILD.py b/zephyr/program/myst/BUILD.py
new file mode 100644
index 0000000000..27e4009c1c
--- /dev/null
+++ b/zephyr/program/myst/BUILD.py
@@ -0,0 +1,30 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Define zmake projects for myst."""
+
+
+def register_myst_project(
+    project_name,
+):
+    """Register a variant of myst."""
+    register_npcx_project(
+        project_name=project_name,
+        zephyr_board="npcx9m7f",
+        dts_overlays=[
+            here / project_name / "project.overlay",
+        ],
+        kconfig_files=[
+            # Common to all projects.
+            here / "program.conf",
+            # Project-specific KConfig customization.
+            here / project_name / "project.conf",
+        ],
+        inherited_from=["myst"],
+    )
+
+
+register_myst_project(
+    project_name="myst",
+)
diff --git a/zephyr/program/myst/CMakeLists.txt b/zephyr/program/myst/CMakeLists.txt
new file mode 100644
index 0000000000..ece440da75
--- /dev/null
+++ b/zephyr/program/myst/CMakeLists.txt
@@ -0,0 +1,22 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.20.5)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+
+cros_ec_library_include_directories(include)
+
+zephyr_library_sources("src/common.c")
+zephyr_library_sources("src/power_signals.c")
+
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC
+	"src/usb_pd_policy.c"
+	"src/usbc_config.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LED_COMMON "src/led.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_AMD_STT "src/stt.c")
+
+if(DEFINED CONFIG_BOARD_MYST)
+	project(myst)
+	add_subdirectory(myst)
+endif()
diff --git a/zephyr/program/myst/Kconfig b/zephyr/program/myst/Kconfig
new file mode 100644
index 0000000000..db33f73668
--- /dev/null
+++ b/zephyr/program/myst/Kconfig
@@ -0,0 +1,15 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config BOARD_MYST
+	bool "Google Myst Board"
+	help
+	  Build Google Myst reference board.  This board uses an AMD SoC
+	  and NPCX9 EC
+
+module = MYST
+module-str = Myst board-specific code
+source "subsys/logging/Kconfig.template.log_config"
+
+source "Kconfig.zephyr"
diff --git a/zephyr/program/myst/adc.dtsi b/zephyr/program/myst/adc.dtsi
new file mode 100644
index 0000000000..613d57e8ab
--- /dev/null
+++ b/zephyr/program/myst/adc.dtsi
@@ -0,0 +1,60 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <cros/thermistor/thermistor.dtsi>
+
+/ {
+	temp_charger_thermistor: charger-thermistor {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_30K9_47K_4050B>;
+		adc = <&adc_temp_chg>;
+	};
+
+	temp_memory_thermistor: memory-thermistor {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_30K9_47K_4050B>;
+		adc = <&adc_temp_mem>;
+	};
+
+	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
+		temp_sensor_charger: charger-thermistor {
+			temp_host_high = <100>;
+			temp_host_halt = <105>;
+			temp_host_release_high = <80>;
+			sensor = <&temp_charger_thermistor>;
+		};
+
+		temp_sensor_memory: memory-thermistor {
+			temp_host_high = <100>;
+			temp_host_halt = <105>;
+			temp_host_release_high = <80>;
+			power-good-pin = <&gpio_pg_pwr_s5>;
+			sensor = <&temp_memory_thermistor>;
+		};
+
+		temp_sensor_cpu: cpu {
+			temp_host_high = <100>;
+			temp_host_halt = <105>;
+			temp_host_release_high = <80>;
+			temp_fan_off = <60>;
+			temp_fan_max = <90>;
+			power-good-pin = <&gpio_pg_pcore_s0_r_od>;
+			sensor = <&temp_cpu>;
+		};
+
+	};
+};
+
+&adc0 {
+	status = "okay";
+	pinctrl-0 = <&adc0_chan0_gp45
+		     &adc0_chan1_gp44>;
+	pinctrl-names = "default";
+};
+
+&thermistor_3V3_30K9_47K_4050B {
+	status = "okay";
+};
diff --git a/zephyr/program/myst/fan.dtsi b/zephyr/program/myst/fan.dtsi
new file mode 100644
index 0000000000..b6685b1b11
--- /dev/null
+++ b/zephyr/program/myst/fan.dtsi
@@ -0,0 +1,39 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	fans {
+		compatible = "cros-ec,fans";
+
+		fan0: fan_0 {
+			pwms = <&pwm0 0 PWM_KHZ(1) PWM_POLARITY_NORMAL>;
+			rpm_min = <3000>;
+			rpm_start = <3000>;
+			rpm_max = <5000>;
+			tach = <&tach1>;
+			pgood_gpio = <&gpio_en_pwr_s0>;
+		};
+	};
+};
+
+/* Tachometer for fan speed measurement */
+&tach1 {
+	status = "okay";
+	pinctrl-0 = <&ta1_1_in_gp40>;
+	pinctrl-names = "default";
+	port = <NPCX_TACH_PORT_A>; /* port-A is selected */
+	sample-clk = <NPCX_TACH_FREQ_LFCLK>; /* Use LFCLK as sampling clock */
+	pulses-per-round = <2>; /* number of pulses per round of encoder */
+};
+
+&pwm0_gpc3 {
+	drive-open-drain;
+};
+
+&pwm0 {
+	status = "okay";
+	pinctrl-0 = <&pwm0_gpc3>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/myst/generated.dtsi b/zephyr/program/myst/generated.dtsi
new file mode 100644
index 0000000000..5bab287a2d
--- /dev/null
+++ b/zephyr/program/myst/generated.dtsi
@@ -0,0 +1,241 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * This file is auto-generated - do not edit!
+ */
+
+/ {
+
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		adc_temp_chg: temp_chg {
+			enum-name = "ADC_TEMP_SENSOR_CHARGER";
+			io-channels = <&adc0 0>;
+		};
+		adc_temp_mem: temp_mem {
+			enum-name = "ADC_TEMP_SENSOR_MEMORY";
+			io-channels = <&adc0 1>;
+		};
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		gpio_3axis_int_l: 3axis_int_l {
+			gpios = <&gpioa 2 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_6axis_int_l: 6axis_int_l {
+			gpios = <&gpioa 0 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_acok_od: acok_od {
+			gpios = <&gpio0 0 GPIO_INPUT>;
+			enum-name = "GPIO_AC_PRESENT";
+		};
+		gpio_ccd_mode_odl: ccd_mode_odl {
+			gpios = <&gpiob 7 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_CCD_MODE_ODL";
+		};
+		gpio_ec_bat_pres_odl: ec_bat_pres_odl {
+			gpios = <&gpio9 3 GPIO_INPUT>;
+			enum-name = "GPIO_BATT_PRES_ODL";
+		};
+		gpio_ec_c0_retimer_int_odl: ec_c0_retimer_int_odl {
+			gpios = <&gpio9 6 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_ec_c0_retimer_rst_l: ec_c0_retimer_rst_l {
+			gpios = <&gpiof 4 GPIO_ODR_HIGH>;
+		};
+		gpio_ec_c1_retimer_int_odl: ec_c1_retimer_int_odl {
+			gpios = <&gpiof 5 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_ec_c1_retimer_rst_odl: ec_c1_retimer_rst_odl {
+			gpios = <&gpio0 3 GPIO_ODR_HIGH>;
+		};
+		gpio_ec_disable_disp_bl: ec_disable_disp_bl {
+			gpios = <&gpiob 1 GPIO_OUTPUT_HIGH>;
+			enum-name = "GPIO_ENABLE_BACKLIGHT_L";
+		};
+		gpio_ec_fan1_speed: ec_fan1_speed {
+			gpios = <&gpio4 0 GPIO_INPUT>;
+		};
+		gpio_ec_fan2_speed: ec_fan2_speed {
+			gpios = <&gpio7 3 GPIO_INPUT>;
+		};
+		gpio_ec_gsc_packet_mode_odl: ec_gsc_packet_mode_odl {
+			gpios = <&gpioc 0 GPIO_ODR_LOW>;
+			enum-name = "GPIO_PACKET_MODE_EN";
+		};
+		gpio_ec_kso_02_inv: ec_kso_02_inv {
+			gpios = <&gpio1 7 (GPIO_OUTPUT_LOW | GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_KBD_KSO2";
+		};
+		gpio_ec_mech_pwr_btn_odl: ec_mech_pwr_btn_odl {
+			gpios = <&gpiod 2 GPIO_INPUT>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		gpio_ec_prochot_odl: ec_prochot_odl {
+			gpios = <&gpiod 4 GPIO_ODR_LOW>;
+			enum-name = "GPIO_CPU_PROCHOT";
+		};
+		gpio_ec_soc_int: ec_soc_int {
+			gpios = <&gpio6 0 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_EC_INT_L";
+		};
+		gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl {
+			gpios = <&gpiob 0 GPIO_ODR_LOW>;
+			enum-name = "GPIO_PCH_PWRBTN_L";
+		};
+		gpio_ec_soc_pwr_good: ec_soc_pwr_good {
+			gpios = <&gpio9 4 GPIO_ODR_LOW>;
+		};
+		gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l {
+			gpios = <&gpioa 5 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_PCH_RSMRST_L";
+		};
+		gpio_ec_soc_wake_odl: ec_soc_wake_odl {
+			gpios = <&gpiof 0 GPIO_ODR_LOW>;
+		};
+		gpio_ec_sys_rst_l: ec_sys_rst_l {
+			gpios = <&gpio7 5 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_SYS_RESET_L";
+		};
+		gpio_ec_wp_l: ec_wp_l {
+			gpios = <&gpioa 7 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_en_kb_bl: en_kb_bl {
+			gpios = <&gpio7 4 GPIO_OUTPUT_HIGH>;
+			enum-name = "GPIO_EN_KEYBOARD_BACKLIGHT";
+		};
+		gpio_en_pp5000_usb_a0_vbus: en_pp5000_usb_a0_vbus {
+			gpios = <&gpio6 6 GPIO_OUTPUT_LOW>;
+		};
+		gpio_en_pp5000_usb_a1_vbus: en_pp5000_usb_a1_vbus {
+			gpios = <&gpio8 3 GPIO_OUTPUT_LOW>;
+		};
+		gpio_en_pwr_pcore_s0: en_pwr_pcore_s0 {
+			gpios = <&gpioe 2 GPIO_OUTPUT_LOW>;
+		};
+		gpio_en_pwr_s0: en_pwr_s0 {
+			gpios = <&gpioe 5 GPIO_OUTPUT_LOW>;
+		};
+		gpio_en_pwr_s5: en_pwr_s5 {
+			gpios = <&gpiod 7 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_EN_PWR_A";
+		};
+		gpio_en_pwr_z1: en_pwr_z1 {
+			gpios = <&gpio8 5 GPIO_OUTPUT_LOW>;
+		};
+		gpio_en_usb_a1_retimer: en_usb_a1_retimer {
+			gpios = <&gpio3 5 GPIO_OUTPUT_LOW>;
+		};
+		gpio_en_usb_c0_tcpc_vbsnk_l: en_usb_c0_tcpc_vbsnk_l {
+			gpios = <&gpioc 5 GPIO_INPUT>;
+		};
+		gpio_lid_open: lid_open {
+			gpios = <&gpio0 1 GPIO_INPUT>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+		gpio_pg_groupc_s0_od: pg_groupc_s0_od {
+			gpios = <&gpio9 7 GPIO_INPUT>;
+		};
+		gpio_pg_lpddr5_s3_od: pg_lpddr5_s3_od {
+			gpios = <&gpioe 1 GPIO_INPUT>;
+		};
+		gpio_pg_pcore_s0_r_od: pg_pcore_s0_r_od {
+			gpios = <&gpiof 1 GPIO_INPUT>;
+			enum-name = "GPIO_S0_PGOOD";
+		};
+		gpio_pg_ppvar_mem_od: pg_ppvar_mem_od {
+			gpios = <&gpio7 6 GPIO_INPUT>;
+		};
+		gpio_pg_pwr_s5: pg_pwr_s5 {
+			gpios = <&gpiod 5 GPIO_INPUT>;
+			enum-name = "GPIO_S5_PGOOD";
+		};
+		gpio_pg_vddq_mem_od: pg_vddq_mem_od {
+			gpios = <&gpioa 4 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_slp_s3_l: slp_s3_l {
+			gpios = <&gpio6 1 GPIO_INPUT>;
+			enum-name = "GPIO_PCH_SLP_S3_L";
+		};
+		gpio_slp_s5_l: slp_s5_l {
+			gpios = <&gpio7 2 GPIO_INPUT>;
+			enum-name = "GPIO_PCH_SLP_S5_L";
+		};
+		gpio_soc_alert_ec_odl: soc_alert_ec_odl {
+			gpios = <&gpiod 3 GPIO_INPUT>;
+		};
+		gpio_soc_thermtrip_r_odl: soc_thermtrip_r_odl {
+			gpios = <&gpio9 5 GPIO_INPUT>;
+		};
+		gpio_soc_usbc_pd_int: soc_usbc_pd_int {
+			gpios = <&gpioa 3 GPIO_INPUT>;
+		};
+		gpio_tablet_mode: tablet_mode {
+			gpios = <&gpioc 1 GPIO_INPUT>;
+			enum-name = "GPIO_TABLET_MODE_L";
+		};
+		gpio_usb_a1_retimer_rst_l: usb_a1_retimer_rst_l {
+			gpios = <&gpio3 2 GPIO_OUTPUT_HIGH>;
+		};
+		gpio_usb_c0_c1_fault_odl: usb_c0_c1_fault_odl {
+			gpios = <&gpioa 1 GPIO_ODR_HIGH>;
+		};
+		gpio_usb_c0_frs_alert_od: usb_c0_frs_alert_od {
+			gpios = <&gpioc 6 GPIO_INPUT>;
+		};
+		gpio_usb_c0_hpd: usb_c0_hpd {
+			gpios = <&gpio6 2 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_USB_C0_DP_HPD";
+		};
+		gpio_usb_c0_ppc_int_odl: usb_c0_ppc_int_odl {
+			gpios = <&gpio6 7 (GPIO_INPUT_PULL_UP | GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_USB_C0_PPC_INT_ODL";
+		};
+		gpio_usb_c0_ppc_rst_l: usb_c0_ppc_rst_l {
+			gpios = <&gpioe 0 GPIO_ODR_HIGH>;
+		};
+		gpio_usb_c0_sbu_flip: usb_c0_sbu_flip {
+			gpios = <&gpio0 2 GPIO_ODR_LOW>;
+		};
+		gpio_usb_c0_tcpc_int_odl: usb_c0_tcpc_int_odl {
+			gpios = <&gpio3 7 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_USB_C0_TCPC_INT_ODL";
+		};
+		gpio_usb_c1_frs_alert_od: usb_c1_frs_alert_od {
+			gpios = <&gpioc 7 GPIO_INPUT>;
+		};
+		gpio_usb_c1_hpd: usb_c1_hpd {
+			gpios = <&gpio6 3 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_USB_C1_DP_HPD";
+		};
+		gpio_usb_c1_ppc_int_odl: usb_c1_ppc_int_odl {
+			gpios = <&gpio7 0 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_USB_C1_PPC_INT_ODL";
+		};
+		gpio_usb_c1_tcpc_int_odl: usb_c1_tcpc_int_odl {
+			gpios = <&gpio3 4 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_USB_C1_TCPC_INT_ODL";
+		};
+		gpio_voldn_btn_odl: voldn_btn_odl {
+			gpios = <&gpio4 2 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_DOWN_L";
+		};
+		gpio_volup_btn_odl: volup_btn_odl {
+			gpios = <&gpio4 3 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_UP_L";
+		};
+	};
+	usba-port-enable-list {
+		compatible = "cros-ec,usba-port-enable-pins";
+		enable-pins = <&gpio_en_pp5000_usb_a0_vbus
+			       &gpio_en_pp5000_usb_a1_vbus>;
+	};
+};
+
+&adc0 {
+	status = "okay";
+};
diff --git a/zephyr/program/myst/gpio.dtsi b/zephyr/program/myst/gpio.dtsi
new file mode 100644
index 0000000000..e55cfa8ae1
--- /dev/null
+++ b/zephyr/program/myst/gpio.dtsi
@@ -0,0 +1,52 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	aliases {
+		gpio-wp = &gpio_ec_wp_l;
+		/* There is no CBI WP on myst... remove this ASAP */
+		gpio-cbi-wp = &gpio_usb_c0_sbu_flip;
+		gpio-kbd-kso2 = &gpio_ec_kso_02_inv;
+	};
+};
+
+/* PSL input pads */
+&psl_in1_gpd2 {
+	/* MECH_PWR_BTN_ODL */
+	psl-in-mode = "edge";
+	psl-in-pol = "low-falling";
+};
+
+&psl_in2_gp00 {
+	/* ACOK_OD */
+	psl-in-mode = "edge";
+	psl-in-pol = "high-rising";
+};
+
+&psl_in3_gp01 {
+	/* LID_OPEN */
+	psl-in-mode = "edge";
+	psl-in-pol = "high-rising";
+};
+
+/* Power domain device controlled by PSL (Power Switch Logic) IO pads */
+&power_ctrl_psl {
+	status = "okay";
+	pinctrl-names = "sleep";
+	pinctrl-0 = <&psl_in1_gpd2 &psl_in2_gp00 &psl_in3_gp01>;
+};
+
+/* host interface */
+&espi0 {
+	status = "okay";
+	pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>;
+	pinctrl-names = "default";
+};
+
+/* Required node label that is named differently on Myst */
+gpio_ec_pch_wake_odl: &gpio_ec_soc_wake_odl {};
+gpio_slp_s0_l: &gpio_slp_s3_l {
+	alias = "GPIO_PCH_SLP_S0_L";
+};
diff --git a/zephyr/program/myst/i2c.dtsi b/zephyr/program/myst/i2c.dtsi
new file mode 100644
index 0000000000..60793ea9dd
--- /dev/null
+++ b/zephyr/program/myst/i2c.dtsi
@@ -0,0 +1,260 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+ #include <dt-bindings/usb_pd_tcpm.h>
+ #include <dt-bindings/usbc_mux.h>
+
+/ {
+	aliases {
+		i2c-0 = &i2c0_0;
+		i2c-1 = &i2c1_0;
+		i2c-2 = &i2c2_0;
+		i2c-3 = &i2c3_0;
+		i2c-4 = &i2c4_1;
+		i2c-5 = &i2c5_0;
+		i2c-6 = &i2c6_0;
+		i2c-7 = &i2c7_0;
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		i2c_tcpc0: tcpc0 {
+			i2c-port = <&i2c0_0>;
+			enum-names = "I2C_PORT_TCPC0";
+		};
+
+		i2c_tcpc1: tcpc1 {
+			i2c-port = <&i2c1_0>;
+			enum-names = "I2C_PORT_TCPC1";
+		};
+
+		battery {
+			i2c-port = <&i2c2_0>;
+			remote-port = <0>;
+			enum-names = "I2C_PORT_BATTERY";
+		};
+
+		usb-mux {
+			i2c-port = <&i2c3_0>;
+			enum-names = "I2C_PORT_USB_MUX";
+		};
+
+		i2c_charger: charger {
+			i2c-port = <&i2c4_1>;
+			enum-names = "I2C_PORT_CHARGER";
+		};
+
+		eeprom {
+			i2c-port = <&i2c5_0>;
+			enum-names = "I2C_PORT_EEPROM";
+		};
+
+		i2c_sensor: sensor {
+			i2c-port = <&i2c6_1>;
+			enum-names = "I2C_PORT_SENSOR";
+		};
+
+		i2c_soc_thermal: soc-thermal {
+			i2c-port = <&i2c7_0>;
+			enum-names = "I2C_PORT_THERMAL_AP";
+		};
+	};
+
+
+};
+
+&i2c0_0 {
+	status = "okay";
+	label = "I2C_TCPC0";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>;
+	pinctrl-names = "default";
+
+	tcpc_port0: rt1715@4e {
+		compatible = "richtek,rt1715-tcpc";
+		reg = <0x4e>;
+		tcpc-flags = <(
+			TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V)>;
+		irq-gpios = <&gpio3 7 GPIO_ACTIVE_LOW>;
+	};
+
+	ppc_port0: ktu1125@38 {
+		compatible = "kinetic,ktu1125";
+		status = "okay";
+		reg = <0x38>;
+	};
+};
+
+&i2c_ctrl0 {
+	status = "okay";
+};
+
+&i2c1_0 {
+	status = "okay";
+	label = "I2C_TCPC1";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>;
+	pinctrl-names = "default";
+
+	tcpc_rt1718_port1: rt1718s-tcpc@40 {
+		compatible = "richtek,rt1718s-tcpc";
+		reg = <0x40>;
+		tcpc-flags = <(
+			TCPC_FLAGS_ALERT_OD |
+			TCPC_FLAGS_CONTROL_VCONN |
+			TCPC_FLAGS_CONTROL_FRS)>;
+		/* a duplicate of the <&gpio_usb_c1_tcpc_int_odl> node in
+		 * "named-gpios". This is the Zephyr preferred style,
+		 * the "named-gpios" node will be dealt with at a later date.
+		 */
+		irq-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
+		is-alt;
+	};
+
+	ppc_nx20p_port1: nx20p348x@71 {
+		compatible = "nxp,nx20p348x";
+		status = "okay";
+		reg = <0x71>;
+		is-alt;
+	};
+
+	tcpc_ps8815_port1: ps8xxx@b {
+		compatible = "parade,ps8xxx";
+		reg = <0xb>;
+		tcpc-flags = <(
+			TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V |
+			TCPC_FLAGS_CONTROL_VCONN |
+			TCPC_FLAGS_CONTROL_FRS)>;
+		irq-gpios = <&gpiof 5 GPIO_ACTIVE_LOW>;
+		is-alt;
+	};
+
+	ppc_ktu1125_port1: ktu1125@38 {
+		compatible = "kinetic,ktu1125";
+		status = "okay";
+		reg = <0x38>;
+		is-alt;
+	};
+};
+
+&i2c_ctrl1 {
+	status = "okay";
+};
+
+&i2c2_0 {
+	status = "okay";
+	label = "I2C_BATTERY";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	pinctrl-0 = <&i2c2_0_sda_scl_gp91_92>;
+	pinctrl-names = "default";
+};
+
+&i2c_ctrl2 {
+	status = "okay";
+};
+
+&i2c3_0 {
+	status = "okay";
+	label = "I2C_USB_MUX";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>;
+	pinctrl-names = "default";
+
+	amd_fp6_port0: amd_fp6@5c {
+		compatible = "amd,usbc-mux-amd-fp6";
+		status = "okay";
+		reg = <0x5c>;
+	};
+	amd_fp6_port1: amd_fp6@58 {
+		compatible = "amd,usbc-mux-amd-fp6";
+		status = "okay";
+		reg = <0x58>;
+	};
+};
+
+&i2c_ctrl3 {
+	status = "okay";
+};
+
+&i2c4_1 {
+	status = "okay";
+	label = "I2C_CHARGER";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c4_1_sda_scl_gpf2_f3>;
+	pinctrl-names = "default";
+
+	charger: isl9241@9 {
+		compatible = "intersil,isl9241";
+		status = "okay";
+		reg = <0x9>;
+	};
+};
+
+&i2c_ctrl4 {
+	status = "okay";
+};
+
+&i2c5_0 {
+	status = "okay";
+	label = "I2C_EEPROM";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c5_0_sda_scl_gp33_36>;
+	pinctrl-names = "default";
+
+	cbi_eeprom: eeprom@50 {
+		compatible = "atmel,at24";
+		reg = <0x50>;
+		size = <2048>;
+		pagesize = <16>;
+		address-width = <8>;
+		timeout = <5>;
+	};
+};
+
+&i2c_ctrl5 {
+	status = "okay";
+};
+
+&i2c6_1 {
+	status = "okay";
+	label = "I2C_SENSOR";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c6_1_sda_scl_gpe3_e4>;
+	pinctrl-names = "default";
+
+	soc_pct2075: soc-pct2075@48 {
+		compatible = "nxp,pct2075";
+		reg = <0x48>;
+	};
+
+	amb_pct2075: amb-pct2075@4f {
+		compatible = "nxp,pct2075";
+		reg = <0x4f>;
+	};
+};
+
+&i2c_ctrl6 {
+	status = "okay";
+};
+
+&i2c7_0 {
+	status = "okay";
+	label = "I2C_THERMAL_AP";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>;
+	pinctrl-names = "default";
+
+	temp_cpu: cpu@4c {
+		compatible = "amd,sb-tsi";
+		reg = <0x4c>;
+	};
+};
+
+&i2c_ctrl7 {
+	status = "okay";
+};
diff --git a/zephyr/program/myst/include/usbc_config.h b/zephyr/program/myst/include/usbc_config.h
new file mode 100644
index 0000000000..1c983ba8e9
--- /dev/null
+++ b/zephyr/program/myst/include/usbc_config.h
@@ -0,0 +1,20 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Myst type-c definitions */
+
+#ifndef __CROS_EC_USBC_CONFIG_H
+#define __CROS_EC_USBC_CONFIG_H
+
+void ppc_interrupt(enum gpio_signal signal);
+
+/* USB-A ports */
+enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT };
+
+/* USB-C ports */
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
+BUILD_ASSERT(USBC_PORT_COUNT == CONFIG_USB_PD_PORT_MAX_COUNT);
+
+#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/zephyr/program/myst/interrupts.dtsi b/zephyr/program/myst/interrupts.dtsi
new file mode 100644
index 0000000000..f80c9d4cd9
--- /dev/null
+++ b/zephyr/program/myst/interrupts.dtsi
@@ -0,0 +1,106 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_lid_open: lid_open {
+			irq-pin = <&gpio_lid_open>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "lid_interrupt";
+		};
+		int_ac_present: ac_present {
+			irq-pin = <&gpio_acok_od>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "extpower_interrupt";
+		};
+		int_power_button: power_button {
+			irq-pin = <&gpio_ec_mech_pwr_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_button_interrupt";
+		};
+		int_slp_s3: slp_s3 {
+			irq-pin = <&gpio_slp_s3_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "baseboard_en_pwr_s0";
+		};
+		int_slp_s5: slp_s5 {
+			irq-pin = <&gpio_slp_s5_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "baseboard_set_en_pwr_s3";
+		};
+		int_s5_pgood: s5_pgood {
+			irq-pin = <&gpio_pg_pwr_s5>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "baseboard_s5_pgood";
+		};
+		int_pg_groupc_s0: pg_groupc_s0 {
+			irq-pin = <&gpio_pg_groupc_s0_od>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "baseboard_set_en_pwr_pcore";
+		};
+		int_pg_lpddr_s3: pg_lpddr_s3 {
+			irq-pin = <&gpio_pg_lpddr5_s3_od>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "baseboard_set_en_pwr_pcore";
+		};
+		int_pg_vddq_mem_od: pg_vddq_mem_od {
+			irq-pin = <&gpio_pg_vddq_mem_od>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "baseboard_set_soc_pwr_pgood";
+		};
+		int_s0_pgood: s0_pgood {
+			irq-pin = <&gpio_pg_pcore_s0_r_od>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "baseboard_s0_pgood";
+		};
+		int_soc_thermtrip: soc_thermtrip {
+			irq-pin = <&gpio_soc_thermtrip_r_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "baseboard_soc_thermtrip";
+		};
+		int_volume_up: volume_up {
+			irq-pin = <&gpio_volup_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+		int_volume_down: volume_down {
+			irq-pin = <&gpio_voldn_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+		int_usb_c0_ppc: usb_c0_ppc {
+			irq-pin = <&gpio_usb_c0_ppc_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "ppc_interrupt";
+		};
+		int_usb_c1_ppc: usb_c1_ppc {
+			irq-pin = <&gpio_usb_c1_ppc_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "ppc_interrupt";
+		};
+		int_usb_pd_soc: usb_pd_soc {
+			irq-pin = <&gpio_ec_c0_retimer_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "usb_pd_soc_interrupt";
+		};
+		int_lid_accel: lid_accel {
+			irq-pin = <&gpio_3axis_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "bma4xx_interrupt";
+		};
+		int_accel_gyro: accel_gyro {
+			irq-pin = <&gpio_6axis_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "bmi3xx_interrupt";
+		};
+		int_prochot: prochot {
+			irq-pin = <&gpio_ec_prochot_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "throttle_ap_prochot_input_interrupt";
+		};
+	};
+};
diff --git a/zephyr/program/myst/keyboard.dtsi b/zephyr/program/myst/keyboard.dtsi
new file mode 100644
index 0000000000..cd4d0413cb
--- /dev/null
+++ b/zephyr/program/myst/keyboard.dtsi
@@ -0,0 +1,48 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	kblight {
+		compatible = "cros-ec,kblight-pwm";
+		pwms = <&pwm2 0 PWM_HZ(100) PWM_POLARITY_NORMAL>;
+	};
+};
+
+&pwm2 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm2_gpc4>;
+	pinctrl-names = "default";
+};
+
+&cros_kb_raw {
+	status = "okay";
+	/* No KSO2 (it's inverted and implemented by GPIO) */
+	pinctrl-0 = <
+		&ksi0_gp31
+		&ksi1_gp30
+		&ksi2_gp27
+		&ksi3_gp26
+		&ksi4_gp25
+		&ksi5_gp24
+		&ksi6_gp23
+		&ksi7_gp22
+		&kso00_gp21
+		&kso01_gp20
+		&kso03_gp16
+		&kso04_gp15
+		&kso05_gp14
+		&kso06_gp13
+		&kso07_gp12
+		&kso08_gp11
+		&kso09_gp10
+		&kso10_gp07
+		&kso11_gp06
+		&kso12_gp05
+		&kso13_gp04
+		&kso14_gp82
+	>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/myst/myst.csv b/zephyr/program/myst/myst.csv
new file mode 100644
index 0000000000..26dd634bf9
--- /dev/null
+++ b/zephyr/program/myst/myst.csv
@@ -0,0 +1,69 @@
+Signal Name,Pin Number,Type,Enum
+USB_C0_PPC_RST_L,F4,OUTPUT,
+USB_C0_TCPC_INT_ODL,C1,INPUT_L,GPIO_USB_C0_TCPC_INT_ODL
+USB_C0_PPC_INT_ODL,J3,INPUT_L,GPIO_USB_C0_PPC_INT_ODL
+USB_C0_C1_FAULT_ODL,L12,INPUT_PU,
+USB_C0_HPD,H2,OUTPUT,GPIO_USB_C0_DP_HPD
+SOC_USBC_PD_INT,K12,INPUT,
+USB_C1_TCPC_INT_ODL,B2,INPUT_L,GPIO_USB_C1_TCPC_INT_ODL
+USB_C1_PPC_INT_ODL,J4,INPUT_L,GPIO_USB_C1_PPC_INT_ODL
+USB_C1_HPD,J2,OUTPUT,GPIO_USB_C1_DP_HPD
+EC_FAN1_PWM,G9,PWM,
+EC_FAN1_SPEED,E5,INPUT,
+EC_FAN2_PWM,H10,PWM,
+EC_FAN2_SPEED,G5,INPUT,
+EC_PWM_KB_BL,G8,PWM,
+EC_PWM_LED_CHRG_L,K5,PWM_INVERT,
+EC_PWM_LED_FULL_L,L9,PWM_INVERT,
+EC_BAT_PRES_ODL,E11,INPUT,GPIO_BATT_PRES_ODL
+CCD_MODE_ODL,J7,OUTPUT_ODL,GPIO_CCD_MODE_ODL
+EC_GSC_PACKET_MODE_ODL,H8,OUTPUT_ODL,GPIO_PACKET_MODE_EN
+3AXIS_INT_L,F12,INPUT_PU,
+6AXIS_INT_L,G11,INPUT_PU,
+TABLET_MODE,H9,INPUT,GPIO_TABLET_MODE_L
+VOLUP_BTN_ODL,E2,INPUT_PU,GPIO_VOLUME_UP_L
+VOLDN_BTN_ODL,D3,INPUT_PU,GPIO_VOLUME_DOWN_L
+EN_KB_BL,H5,OUTPUT,GPIO_EN_KEYBOARD_BACKLIGHT
+EC_SOC_PWR_GOOD,M11,OUTPUT_ODR,
+PG_GROUPC_S0_OD,L10,INPUT,
+PG_LPDDR5_S3_OD,F3,INPUT,
+PG_VDDQ_MEM_OD,H11,INPUT_PU,
+PG_PWR_S5,D5,INPUT,
+PG_PCORE_S0_R_OD,G3,INPUT,GPIO_S0_PGOOD
+EN_PWR_PCORE_S0,A11,OUTPUT,
+EN_PWR_S0,A12,OUTPUT,
+EN_PWR_S5,H6,OUTPUT,GPIO_EN_PWR_A
+SLP_S3_L,K4,INPUT,GPIO_PCH_SLP_S3_L
+SLP_S5_L,M4,INPUT,GPIO_PCH_SLP_S5_L
+EC_PROCHOT_ODL,A9,OUTPUT_ODL,GPIO_CPU_PROCHOT
+SOC_ALERT_EC_ODL,E10,INPUT,
+SOC_THERMTRIP_R_ODL,M12,INPUT,
+EC_SYS_RST_L,J6,OUTPUT,GPIO_SYS_RESET_L
+EC_SOC_RSMRST_L,K11,OUTPUT,GPIO_PCH_RSMRST_L
+EC_SOC_INT,G6,OUTPUT,GPIO_EC_INT_L
+EC_SOC_WAKE_ODL,D2,OUTPUT_ODL,
+EC_SOC_PWR_BTN_ODL,L11,OUTPUT_ODL,GPIO_PCH_PWRBTN_L
+EC_DISABLE_DISP_BL,D8,OUTPUT,GPIO_ENABLE_BACKLIGHT
+EC_WP_L,J11,INPUT_L,
+TEMP_CHG,F2,ADC,ADC_TEMP_SENSOR_CHARGER
+TEMP_MEM,E3,ADC,ADC_TEMP_SENSOR_MEMORY
+UART_EC_TX_DBG_RX_R,H4,OTHER,
+UART_EC_RX_DBG_TX_R,G4,OTHER,
+EC_C1_RETIMER_INT_ODL,E8,INPUT,
+EC_C1_RETIMER_RST_ODL,D9,OUTPUT_ODL,
+EC_C0_RETIMER_INT_ODL,G12,INPUT_PU,
+EC_C0_RETIMER_RST_L,E9,OUTPUT,
+USB_C0_FRS_ALERT_OD,D10,INPUT,
+EN_PP5000_USB_A0_VBUS,G2,OUTPUT,
+EN_PP5000_USB_A1_VBUS,D7,OUTPUT,
+USB_C0_SBU_FLIP,F7,OUTPUT_ODL,
+EN_USB_A1_RETIMER,K2,OUTPUT,
+USB_A1_RETIMER_RST_L,E4,OUTPUT,
+USB_C1_FRS_ALERT_OD,F10,INPUT,
+EN_USB_C0_TCPC_VBSNK_L,H7,OUTPUT_ODL,
+ACOK_OD,E7,INPUT,GPIO_AC_PRESENT
+LID_OPEN,E6,INPUT,GPIO_LID_OPEN
+EC_MECH_PWR_BTN_ODL,G7,INPUT,GPIO_POWER_BUTTON_L
+PG_PPVAR_MEM_OD,J5,INPUT,
+EN_PWR_Z1,J8,OUTPUT,
+EC_KSO_02_INV,B7,OUTPUT_L,GPIO_KBD_KSO2
diff --git a/zephyr/program/myst/myst/CMakeLists.txt b/zephyr/program/myst/myst/CMakeLists.txt
new file mode 100644
index 0000000000..09e319e8c4
--- /dev/null
+++ b/zephyr/program/myst/myst/CMakeLists.txt
@@ -0,0 +1,9 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cros_ec_library_include_directories_ifdef(CONFIG_BOARD_MYST include)
+zephyr_library_sources(
+		"src/keyboard.c"
+		"src/usb_mux_config.c"
+)
diff --git a/zephyr/program/myst/myst/led_pins.dtsi b/zephyr/program/myst/myst/led_pins.dtsi
new file mode 100644
index 0000000000..d7a8b7e96f
--- /dev/null
+++ b/zephyr/program/myst/myst/led_pins.dtsi
@@ -0,0 +1,58 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	pwmleds {
+		compatible = "pwm-leds";
+		pwm_amber: pwm_amber {
+			pwms = <&pwm3 0 PWM_HZ(100) PWM_POLARITY_INVERTED>;
+		};
+		pwm_blue: pwm_blue {
+			pwms = <&pwm4 0 PWM_HZ(100) PWM_POLARITY_INVERTED>;
+		};
+	};
+
+	pwm-led-pins {
+		compatible = "cros-ec,pwm-led-pins";
+
+		battery_led: battery-led {
+			led-id = "EC_LED_ID_BATTERY_LED";
+			led-pwms = <&pwm_amber &pwm_blue>;
+
+			color_off: color-off {
+				led-color = "LED_OFF";
+				led-values = <0 0>;
+			};
+
+			color_amber: color-amber {
+				led-color = "LED_AMBER";
+				br-color = "EC_LED_COLOR_AMBER";
+				led-values = <100 0>;
+			};
+
+			color_blue: color-blue {
+				led-color = "LED_BLUE";
+				br-color = "EC_LED_COLOR_BLUE";
+				led-values = <0 100>;
+			};
+		};
+	};
+};
+
+/* Amber "battery charging" LED */
+&pwm3 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm3_gp80>;
+	pinctrl-names = "default";
+};
+
+/* Blue "battery full" LED */
+&pwm4 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm4_gpb6>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/myst/myst/led_policy.dtsi b/zephyr/program/myst/myst/led_policy.dtsi
new file mode 100644
index 0000000000..f6e826ae53
--- /dev/null
+++ b/zephyr/program/myst/myst/led_policy.dtsi
@@ -0,0 +1,108 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/battery.h>
+
+/ {
+	led-colors {
+		compatible = "cros-ec,led-policy";
+
+		power-state-charge {
+			charge-state = "LED_PWRS_CHARGE";
+
+			color-0 {
+				led-color = <&color_amber>;
+			};
+		};
+
+		power-state-discharge-s0 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S0";
+			/* Battery percent range (> Low, <= Full) */
+			batt-lvl = <(BATTERY_LEVEL_LOW + 1) BATTERY_LEVEL_FULL>;
+
+			color-0 {
+				led-color = <&color_blue>;
+			};
+		};
+
+		power-state-discharge-s0-batt-low {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S0";
+			/* Battery percent range (>= Empty, <= Low) */
+			batt-lvl = <BATTERY_LEVEL_EMPTY BATTERY_LEVEL_LOW>;
+
+			/* Blue 2 sec, off 1 sec */
+			color-0 {
+				led-color = <&color_blue>;
+				period-ms = <2000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <1000>;
+			};
+		};
+
+		power-state-discharge-s3 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S3";
+
+			/* Blue 1 sec, off 1 sec */
+			color-0 {
+				led-color = <&color_blue>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <1000>;
+			};
+		};
+
+		power-state-discharge-s5 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S5";
+
+			color-0 {
+				led-color = <&color_off>;
+			};
+		};
+
+		power-state-error {
+			charge-state = "LED_PWRS_ERROR";
+
+			/* Amber 1 sec, off 1 sec */
+			color-0 {
+				led-color = <&color_amber>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <1000>;
+			};
+		};
+
+		power-state-near-full {
+			charge-state = "LED_PWRS_CHARGE_NEAR_FULL";
+
+			color-0 {
+				led-color = <&color_blue>;
+			};
+		};
+
+		power-state-forced-idle {
+			charge-state = "LED_PWRS_FORCED_IDLE";
+
+			/* Amber 2 sec, Blue 2 sec */
+			color-0 {
+				led-color = <&color_amber>;
+				period-ms = <2000>;
+			};
+			color-1 {
+				led-color = <&color_blue>;
+				period-ms = <2000>;
+			};
+		};
+	};
+};
diff --git a/zephyr/program/myst/myst/motionsense.dtsi b/zephyr/program/myst/myst/motionsense.dtsi
new file mode 100644
index 0000000000..d2119f4942
--- /dev/null
+++ b/zephyr/program/myst/myst/motionsense.dtsi
@@ -0,0 +1,136 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/motionsense/utils.h>
+
+
+/ {
+	aliases {
+		/*
+		 * motion sense's <>_INT_EVENT is handled
+		 * by alias. Using the alias, each driver creates
+		 * its own <>_INT_EVENT.
+		 */
+		bmi3xx-int = &base_accel;
+		bma4xx-int = &lid_accel;
+	};
+
+	/*
+	 * Declare mutexes used by sensor drivers.
+	 * A mutex node is used to create an instance of mutex_t.
+	 * A mutex node is referenced by a sensor node if the
+	 * corresponding sensor driver needs to use the
+	 * instance of the mutex.
+	 */
+	motionsense-mutex {
+		compatible = "cros-ec,motionsense-mutex";
+		lid_mutex: lid-mutex {
+		};
+
+		mutex_bmi3xx: bmi3xx-mutex {
+		};
+	};
+
+	/*
+	 * Driver specific data. A driver-specific data can be shared with
+	 * different motion sensors while they are using the same driver.
+	 *
+	 * If a node's compatible starts with "cros-ec,accelgyro-", it is for
+	 * a common structure defined in accelgyro.h.
+	 * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for
+	 * "struct als_drv_data_t" in accelgyro.h
+	 */
+	motionsense-sensor-data {
+		bma4xx_data: bma4xx-drv-data {
+			compatible = "cros-ec,drvdata-bma4xx";
+			status = "okay";
+		};
+
+		bmi3xx_data: bmi3xx-drv-data {
+			compatible = "cros-ec,drvdata-bmi3xx";
+			status = "okay";
+		};
+	};
+
+	/*
+	 * List of motion sensors that creates motion_sensors array.
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
+	 * motion sensor IDs for lid angle calculation.
+	 */
+	motionsense-sensor {
+		lid_accel: lid-accel {
+			compatible = "cros-ec,bma4xx";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&lid_mutex>;
+			port = <&i2c_sensor>;
+			drv-data = <&bma4xx_data>;
+			rot-standard-ref = <&lid_rot_ref>;
+			default-range = <2>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(12500 | ROUND_UP_FLAG)>;
+					ec-rate = <100>;
+				};
+				ec-s3 {
+					odr = <(12500 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_accel: base-accel {
+			compatible = "cros-ec,bmi3xx-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&mutex_bmi3xx>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&bmi3xx_data>;
+
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(12500 | ROUND_UP_FLAG)>;
+					ec-rate = <100>;
+				};
+				ec-s3 {
+					odr = <(12500 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base-gyro {
+			compatible = "cros-ec,bmi3xx-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&mutex_bmi3xx>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&bmi3xx_data>;
+		};
+	};
+
+	motionsense-sensor-info {
+		compatible = "cros-ec,motionsense-sensor-info";
+
+		/*
+		 * list of GPIO interrupts that have to
+		 * be enabled at initial stage
+		 */
+		sensor-irqs = <&int_accel_gyro>;
+
+		/* list of sensors in force mode */
+		accel-force-mode-sensors = <&lid_accel>;
+	};
+};
diff --git a/zephyr/program/myst/myst/project.conf b/zephyr/program/myst/myst/project.conf
new file mode 100644
index 0000000000..ed367910ec
--- /dev/null
+++ b/zephyr/program/myst/myst/project.conf
@@ -0,0 +1,25 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Myst reference-board-specific Kconfig settings.
+CONFIG_BOARD_MYST=y
+
+# Myst is capable of sinking 100W
+CONFIG_PLATFORM_EC_PD_MAX_POWER_MW=100000
+CONFIG_PLATFORM_EC_PD_MAX_CURRENT_MA=5000
+CONFIG_PLATFORM_EC_PD_MAX_VOLTAGE_MV=20000
+
+# Enable alternative charger chip
+CONFIG_PLATFORM_EC_CHARGER_RUNTIME_CONFIG=y
+CONFIG_PLATFORM_EC_CHARGER_ISL9241=y
+
+# Battery
+CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO=y
+
+# EC Host Commands
+CONFIG_PLATFORM_EC_HOSTCMD_AP_RESET=y
+
+# Allow configurable S5 timeout
+# TODO(b/285201949): Remove before product launch
+CONFIG_PLATFORM_EC_CONSOLE_CMD_S5_TIMEOUT=y
diff --git a/zephyr/program/myst/myst/project.overlay b/zephyr/program/myst/myst/project.overlay
new file mode 100644
index 0000000000..a7ee29ad77
--- /dev/null
+++ b/zephyr/program/myst/myst/project.overlay
@@ -0,0 +1,227 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Myst program common DTS includes */
+#include "../adc.dtsi"
+#include "../fan.dtsi"
+#include "../generated.dtsi"
+#include "../gpio.dtsi"
+#include "../i2c.dtsi"
+#include "../interrupts.dtsi"
+#include "../keyboard.dtsi"
+#include "../usbc.dtsi"
+
+/* Myst project DTS includes*/
+#include "led_pins.dtsi"
+#include "led_policy.dtsi"
+#include "motionsense.dtsi"
+
+/* Myst overrides follow... */
+/ {
+	/* battery overrides */
+	batteries {
+		default_battery: lgc_ap19b8m {
+			compatible = "lgc,ap19b8m", "battery-smart";
+		};
+		cosmx-2 {
+			compatible = "cosmx,ap20cbl-2", "battery-smart";
+		};
+	};
+
+	named-gpios {
+		/* Unimplemented */
+		gpio_ec_entering_rw: ec_entering_rw {
+			enum-name = "GPIO_ENTERING_RW";
+		};
+		pch-sys-prwok {
+			enum-name = "GPIO_PCH_SYS_PWROK";
+		};
+	};
+
+	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
+		soc-pct2075 {
+			temp_host_high = <100>;
+			temp_host_halt = <105>;
+			temp_host_release_high = <80>;
+			temp_host_release_halt = <80>;
+			temp_fan_off = <35>;
+			temp_fan_max = <70>;
+			power-good-pin = <&gpio_pg_pwr_s5>;
+			sensor = <&soc_pct2075>;
+		};
+		amb-pct2075 {
+			power-good-pin = <&gpio_pg_pwr_s5>;
+			sensor = <&amb_pct2075>;
+		};
+	};
+
+	/*
+	 * Note this is expected to vary per-board, so we keep it in the overlay
+	 * files.
+	 */
+	myst-fw-config {
+		compatible = "cros-ec,cbi-fw-config";
+
+		form-factor {
+			enum-name = "FW_FORM_FACTOR";
+			start = <0>;
+			size = <1>;
+
+			ff-clamshell {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FF_CLAMSHELL";
+				value = <0>;
+			};
+			ff-convertible {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FF_CONVERTIBLE";
+				value = <1>;
+				default;
+			};
+		};
+
+		fingerprint {
+			enum-name = "FW_FINGERPRINT";
+			start = <1>;
+			size = <2>;
+
+			fp-disabled {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FP_DISABLED";
+				value = <0>;
+				default;
+			};
+			fp-uart {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FP_UART";
+				value = <1>;
+			};
+			fp-spi {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FP_SPI";
+				value = <2>;
+			};
+		};
+
+		wlan {
+			enum-name = "FW_WLAN";
+			start = <3>;
+			size = <2>;
+
+			wlan-mt7922 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_WLAN_MT7922";
+				value = <0>;
+				default;
+			};
+			wlan-mt7925 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_WLAN_MT7925";
+				value = <1>;
+			};
+		};
+
+		wwan {
+			enum-name = "FW_WWAN";
+			start = <5>;
+			size = <2>;
+
+			wwan-disabled {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_WWAN_DISABLED";
+				value = <0>;
+				default;
+			};
+			wwan-fm101-gl {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_WWAN_FM101_GL";
+				value = <1>;
+			};
+		};
+
+		io-db {
+			enum-name = "FW_IO_DB";
+			start = <7>;
+			size = <3>;
+
+			io-db-none {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_IO_DB_NONE";
+				value = <0>;
+				default;
+			};
+			io-db-sku-a {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_IO_DB_SKU_A";
+				value = <1>;
+			};
+			io-db-sku-b {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_IO_DB_SKU_B";
+				value = <2>;
+			};
+		};
+
+		kb-bl {
+			enum-name = "FW_KB_BL";
+			start = <10>;
+			size = <1>;
+
+			kb-bl-disabled {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_KB_BL_DISABLED";
+				value = <0>;
+				default;
+			};
+			kb-bl-enabled {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_KB_BL_ENABLED";
+				value = <1>;
+			};
+		};
+
+		storage {
+			enum-name = "STORAGE_TYPE";
+			start = <11>;
+			size = <1>;
+
+			storage-mmc {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "STORAGE_TYPE_MMC";
+				value = <0>;
+			};
+			storage-nvme {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "STORAGE_TYPE_NVME";
+				value = <1>;
+				default;
+			};
+		};
+	};
+
+	/* Rotation matrices for motion sensors. */
+	motionsense-rotation-ref {
+		compatible = "cros-ec,motionsense-rotation-ref";
+		lid_rot_ref: lid-rotation-ref {
+			mat33 = <0 (-1) 0
+				 1 0 0
+				 0 0 1>;
+		};
+
+		lid_rot_ref1: lid-rotation-ref1 {
+			mat33 = <0 1 0
+				 (-1) 0 0
+				 0 0 1>;
+		};
+
+		base_rot_ref: base-rotation-ref {
+			mat33 = <0 1 0
+				 (-1) 0 0
+				 0 0 1>;
+		};
+	};
+
+};
diff --git a/zephyr/program/myst/myst/src/keyboard.c b/zephyr/program/myst/myst/src/keyboard.c
new file mode 100644
index 0000000000..90e60fb0d7
--- /dev/null
+++ b/zephyr/program/myst/myst/src/keyboard.c
@@ -0,0 +1,29 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+
+static const struct ec_response_keybd_config myst_kb = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &myst_kb;
+}
diff --git a/zephyr/program/myst/myst/src/usb_mux_config.c b/zephyr/program/myst/myst/src/usb_mux_config.c
new file mode 100644
index 0000000000..561202fd23
--- /dev/null
+++ b/zephyr/program/myst/myst/src/usb_mux_config.c
@@ -0,0 +1,92 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Myst board-specific USB-C mux configuration */
+
+#include "console.h"
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+#include "hooks.h"
+#include "usb_mux.h"
+#include "usbc/ppc.h"
+#include "usbc/tcpci.h"
+#include "usbc/usb_muxes.h"
+#include "usbc_config.h"
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(myst, CONFIG_MYST_LOG_LEVEL);
+
+uint32_t get_io_db_type_from_cached_cbi(void)
+{
+	uint32_t io_db_type;
+	int ret = cros_cbi_get_fw_config(FW_IO_DB, &io_db_type);
+
+	if (ret != 0) {
+		io_db_type = FW_IO_DB_NONE;
+		LOG_ERR("Failed to get IO_DB value: %d", ret);
+	}
+
+	return io_db_type;
+}
+
+__override uint8_t board_get_usb_pd_port_count(void)
+{
+	if (get_io_db_type_from_cached_cbi() == FW_IO_DB_NONE)
+		return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
+	else
+		return CONFIG_USB_PD_PORT_MAX_COUNT;
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	uint32_t io_db_type = get_io_db_type_from_cached_cbi();
+
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		ktu1125_interrupt(USBC_PORT_C0);
+		break;
+
+	case GPIO_USB_C1_PPC_INT_ODL:
+		if (io_db_type == FW_IO_DB_SKU_A) {
+			nx20p348x_interrupt(USBC_PORT_C1);
+		}
+		if (io_db_type == FW_IO_DB_SKU_B) {
+			ktu1125_interrupt(USBC_PORT_C1);
+		}
+		break;
+
+	default:
+		break;
+	}
+}
+
+static void setup_mux(void)
+{
+	switch (get_io_db_type_from_cached_cbi()) {
+	default:
+	case FW_IO_DB_NONE:
+		LOG_INF("USB DB: not connected");
+		break;
+
+	case FW_IO_DB_SKU_A:
+		LOG_INF("USB DB: Setting SKU_A DB");
+		TCPC_ENABLE_ALTERNATE_BY_NODELABEL(USBC_PORT_C1,
+						   tcpc_rt1718_port1);
+		PPC_ENABLE_ALTERNATE_BY_NODELABEL(USBC_PORT_C1,
+						  ppc_nx20p_port1);
+		break;
+
+	case FW_IO_DB_SKU_B:
+		LOG_INF("USB DB: Setting SKU_B DB");
+		TCPC_ENABLE_ALTERNATE_BY_NODELABEL(USBC_PORT_C1,
+						   tcpc_ps8815_port1);
+		PPC_ENABLE_ALTERNATE_BY_NODELABEL(USBC_PORT_C1,
+						  ppc_ktu1125_port1);
+		break;
+	}
+}
+DECLARE_HOOK(HOOK_INIT, setup_mux, HOOK_PRIO_INIT_I2C);
diff --git a/zephyr/program/myst/program.conf b/zephyr/program/myst/program.conf
new file mode 100644
index 0000000000..7ce65103f0
--- /dev/null
+++ b/zephyr/program/myst/program.conf
@@ -0,0 +1,160 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_CROS_EC=y
+CONFIG_PLATFORM_EC=y
+CONFIG_SHIMMED_TASKS=y
+CONFIG_ESPI=y
+
+# Shell features
+CONFIG_SHELL_HISTORY=y
+CONFIG_SHELL_TAB=y
+CONFIG_SHELL_TAB_AUTOCOMPLETION=y
+CONFIG_KERNEL_SHELL=y
+CONFIG_PWM_SHELL=y
+
+# Power sequencing
+CONFIG_AP=y
+CONFIG_AP_X86_AMD=y
+CONFIG_PLATFORM_EC_POWERSEQ=y
+CONFIG_PLATFORM_EC_POWER_BUTTON_TO_PCH_CUSTOM=y
+CONFIG_PLATFORM_EC_POWER_SLEEP_FAILURE_DETECTION=y
+CONFIG_PLATFORM_EC_POWERSEQ_RSMRST_DELAY=y
+CONFIG_PLATFORM_EC_POWERSEQ_S0IX=y
+CONFIG_PLATFORM_EC_POWERSEQ_CPU_PROCHOT_ACTIVE_LOW=y
+CONFIG_PLATFORM_EC_PORT80=y
+
+# Power button
+CONFIG_PLATFORM_EC_POWER_BUTTON=y
+
+# CBI EEPROM support - to be removed in favor of CBI in EC
+CONFIG_EEPROM=y
+CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=y
+CONFIG_PLATFORM_EC_BYPASS_CBI_EEPROM_WP_CHECK=y
+
+# Temperature Sensors
+CONFIG_PLATFORM_EC_AMD_SB_RMI=y
+CONFIG_PLATFORM_EC_AMD_STT=y
+CONFIG_PLATFORM_EC_THROTTLE_AP=y
+# An external prochot can only be triggered by the charger
+# and during on the fan would increase current draw and make it worse.
+CONFIG_PLATFORM_EC_THROTTLE_AP_NO_FAN=y
+CONFIG_PLATFORM_EC_THROTTLE_AP_SINGLE_PIN=y
+
+# External power
+CONFIG_PLATFORM_EC_HOSTCMD=y
+CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=y
+CONFIG_PLATFORM_EC_BACKLIGHT_LID_ACTIVE_LOW=y
+
+# Lid switch
+CONFIG_PLATFORM_EC_LID_ANGLE=y
+CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y
+CONFIG_PLATFORM_EC_LID_SWITCH=y
+
+# Keyboard
+CONFIG_PLATFORM_EC_KBLIGHT_ENABLE_PIN=y
+CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED=y
+CONFIG_PLATFORM_EC_VOLUME_BUTTONS=y
+CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI3=y
+CONFIG_PLATFORM_EC_KEYBOARD_REFRESH_ROW3=y
+
+# Syscon
+CONFIG_SYSCON=y
+
+# Battery
+CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y
+CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y
+CONFIG_PLATFORM_EC_BATTERY_REVIVE_DISCONNECT=y
+CONFIG_PLATFORM_EC_SMBUS_PEC=y
+
+# Disable BC12
+CONFIG_PLATFORM_EC_USB_CHARGER=n
+
+# Charger
+CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y
+CONFIG_PLATFORM_EC_CHARGER_DEFAULT_CURRENT_LIMIT=512
+CONFIG_PLATFORM_EC_CHARGER_ISL9241=y
+CONFIG_PLATFORM_EC_CHARGER_DUMP_PROCHOT=y
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=20
+CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON=50000
+
+# USB-C
+CONFIG_PLATFORM_EC_ASSERT_CCD_MODE_ON_DTS_CONNECT=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8815=y
+CONFIG_PLATFORM_EC_USBC_PPC=y
+CONFIG_PLATFORM_EC_USBC_PPC_DEDICATED_INT=y
+CONFIG_PLATFORM_EC_USBC_SS_MUX_DFP_ONLY=y
+CONFIG_PLATFORM_EC_USB_MUX_RUNTIME_CONFIG=y
+CONFIG_PLATFORM_EC_USB_DRP_ACC_TRYSRC=y
+CONFIG_PLATFORM_EC_USB_PID=0x5064
+CONFIG_PLATFORM_EC_USB_PD_5V_EN_CUSTOM=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y
+CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_TCPC=y
+CONFIG_PLATFORM_EC_USB_PD_DP_HPD_GPIO=y
+CONFIG_PLATFORM_EC_USB_PD_LOGGING=y
+CONFIG_PLATFORM_EC_USB_PD_REV30=y
+CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=n
+CONFIG_PLATFORM_EC_USB_PD_TCPC_LOW_POWER=y
+CONFIG_PLATFORM_EC_USB_PD_TCPC_RUNTIME_CONFIG=y
+CONFIG_PLATFORM_EC_USB_PD_USB4=n
+CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_CHARGER=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_BY_BOARD=y
+
+# Bring up configs
+CONFIG_SHELL_HISTORY_BUFFER=256
+CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y
+
+# Disable FRS for bringup
+CONFIG_PLATFORM_EC_USB_PD_FRS=n
+CONFIG_PLATFORM_EC_USB_PD_FRS_TCPC=n
+
+# Temporary hack to enable bc12 driver
+CONFIG_PLATFORM_EC_BC12_SINGLE_DRIVER=n
+
+# Give ourselves enough task space to use i2ctrace
+CONFIG_TASK_PD_STACK_SIZE=1280
+
+# Motion sense
+CONFIG_PLATFORM_EC_ACCEL_FIFO=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=y
+CONFIG_PLATFORM_EC_LID_ANGLE=y
+CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y
+CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=y
+
+CONFIG_PLATFORM_EC_MKBP_EVENT=y
+CONFIG_PLATFORM_EC_MKBP_INPUT_DEVICES=y
+CONFIG_PLATFORM_EC_MKBP_USE_GPIO=y
+CONFIG_PLATFORM_EC_MKBP_USE_GPIO_ACTIVE_HIGH=y
+
+CONFIG_PLATFORM_EC_TABLET_MODE=y
+CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=y
+CONFIG_PLATFORM_EC_GMR_TABLET_MODE=y
+
+CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y
+
+# Misc.
+CONFIG_PLATFORM_EC_AMD_STB_DUMP=y
+CONFIG_PLATFORM_EC_EMULATED_SYSRQ=y
+CONFIG_PLATFORM_EC_I2C_DEBUG=y
+CONFIG_PLATFORM_EC_PORT80_4_BYTE=y
+
+# System safe mode for improved panic debugging
+CONFIG_PLATFORM_EC_SYSTEM_SAFE_MODE=y # 576 bytes + 56 bytes RAM
+
+# These are debug options that happen to be expensive in terms of flash space.
+# Turn off as needed based on demand.
+CONFIG_FLASH_PAGE_LAYOUT=y # 1876 bytes
+CONFIG_FLASH_SHELL=y # 1852 bytes
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=y # 656 bytes
+CONFIG_PLATFORM_EC_CONSOLE_CMD_MEM=y # 896 bytes
+CONFIG_PLATFORM_EC_CONSOLE_CMD_TCPC_DUMP=y # 1180 bytes
+CONFIG_PLATFORM_EC_CONSOLE_CMD_PPC_DUMP=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_USB_PD_CABLE=y # 1104 bytes
+CONFIG_SHELL_HELP=y # 3432 bytes
+CONFIG_THREAD_MONITOR=y # 1548 bytes
diff --git a/zephyr/program/myst/src/common.c b/zephyr/program/myst/src/common.c
new file mode 100644
index 0000000000..c78d28bdaa
--- /dev/null
+++ b/zephyr/program/myst/src/common.c
@@ -0,0 +1,8 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(myst, CONFIG_MYST_LOG_LEVEL);
diff --git a/zephyr/program/myst/src/power_signals.c b/zephyr/program/myst/src/power_signals.c
new file mode 100644
index 0000000000..825fdde06a
--- /dev/null
+++ b/zephyr/program/myst/src/power_signals.c
@@ -0,0 +1,234 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ap_power/ap_power.h"
+#include "charger.h"
+#include "chipset.h"
+#include "config.h"
+#include "driver/amd_stb.h"
+#include "gpio/gpio_int.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "ioexpander.h"
+#include "power.h"
+#include "power/amd_x86.h"
+#include "throttle_ap.h"
+#include "timer.h"
+
+/* Power Signal Input List */
+/* TODO: b/218904113: Convert to using Zephyr GPIOs */
+const struct power_signal_info power_signal_list[] = {
+	[X86_SLP_S3_N] = {
+		.gpio = GPIO_PCH_SLP_S3_L,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "SLP_S3_DEASSERTED",
+	},
+	[X86_SLP_S5_N] = {
+		.gpio = GPIO_PCH_SLP_S5_L,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "SLP_S5_DEASSERTED",
+	},
+	[X86_S0_PGOOD] = {
+		.gpio = GPIO_S0_PGOOD,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "S0_PGOOD",
+	},
+/* looks like we don't have this on Myst.. but POWER_SIGNAL_COUNT is needed */
+	[X86_S5_PGOOD] = {
+		.gpio = GPIO_S5_PGOOD,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "S5_PGOOD",
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
+
+static void handle_prochot(bool asserted, void *data);
+
+const struct prochot_cfg prochot_cfg = {
+	.gpio_prochot_in = GPIO_CPU_PROCHOT,
+	.callback = handle_prochot,
+};
+
+/* Chipset hooks */
+static void baseboard_suspend_change(struct ap_power_ev_callback *cb,
+				     struct ap_power_ev_data data)
+{
+	switch (data.event) {
+	default:
+		return;
+
+	case AP_POWER_SUSPEND:
+		/* Disable display backlight and retimer */
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_disable_disp_bl),
+				1);
+		break;
+
+	case AP_POWER_RESUME:
+		/* Enable retimer and display backlight */
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_disable_disp_bl),
+				0);
+		/* Any retimer tuning can be done after the retimer turns on */
+		break;
+	}
+}
+
+static void check_charger_prochot(void)
+{
+	print_charger_prochot(CHARGER_SOLO);
+}
+DECLARE_DEFERRED(check_charger_prochot);
+
+static void handle_prochot(bool asserted, void *data)
+{
+	if (asserted) {
+		ccprints("Prochot asserted externally");
+		hook_call_deferred(&check_charger_prochot_data, 0);
+	} else
+		ccprints("Prochot deasserted externally");
+}
+
+static void baseboard_init(void)
+{
+	static struct ap_power_ev_callback cb;
+
+	/* Setup a suspend/resume callback */
+	ap_power_ev_init_callback(&cb, baseboard_suspend_change,
+				  AP_POWER_RESUME | AP_POWER_SUSPEND);
+	ap_power_ev_add_callback(&cb);
+	/* Enable Power Group interrupts. */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pg_groupc_s0));
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pg_lpddr_s3));
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pg_vddq_mem_od));
+
+	/* Enable prochot interrupt */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_prochot));
+	throttle_ap_config_prochot(&prochot_cfg);
+}
+DECLARE_HOOK(HOOK_INIT, baseboard_init, HOOK_PRIO_POST_I2C);
+
+/**
+ * b/275949288: On G3->S5, wait for RSMRST_L to be deasserted before asserting
+ * PCH_PWRBTN_L.  This can be as long as ~65ms after cold boot.  Then wait an
+ * additional delay of T1a defined in the EDS before changing the power button.
+ */
+#define RSMRST_WAIT_DELAY 65
+#define EDS_PWR_BTN_RSMRST_T1A_DELAY 16
+void board_pwrbtn_to_pch(int level)
+{
+	timestamp_t start;
+
+	/* Add delay for G3 exit if asserting PWRBTN_L and RSMRST_L is low. */
+	if (!level &&
+	    !gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_soc_rsmrst_l))) {
+		start = get_time();
+		do {
+			usleep(500);
+			if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(
+				    gpio_ec_soc_rsmrst_l)))
+				break;
+		} while (time_since32(start) < (RSMRST_WAIT_DELAY * MSEC));
+
+		if (!gpio_pin_get_dt(
+			    GPIO_DT_FROM_NODELABEL(gpio_ec_soc_rsmrst_l)))
+			ccprints("Error pwrbtn: RSMRST_L still low");
+
+		msleep(EDS_PWR_BTN_RSMRST_T1A_DELAY);
+	}
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_soc_pwr_btn_odl), level);
+}
+
+/* Note: signal parameter unused */
+void baseboard_set_soc_pwr_pgood(enum gpio_signal unused)
+{
+	/*
+	 * EC must AND signals PG_VDDQ_MEM_OD, PG_GROUPC_S0_OD, and
+	 * EN_PWR_S0_R. AND PG_LPDDR5_S3_OD for good measure since it
+	 * should be enabled in S0 anyway.
+	 */
+	gpio_pin_set_dt(
+		GPIO_DT_FROM_NODELABEL(gpio_ec_soc_pwr_good),
+		gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_pg_vddq_mem_od)) &&
+			gpio_pin_get_dt(
+				GPIO_DT_FROM_NODELABEL(gpio_pg_groupc_s0_od)) &&
+			gpio_pin_get_dt(
+				GPIO_DT_FROM_NODELABEL(gpio_pg_lpddr5_s3_od)) &&
+			gpio_pin_get_dt(
+				GPIO_DT_FROM_NODELABEL(gpio_en_pwr_s0)) &&
+			gpio_pin_get_dt(
+				GPIO_DT_FROM_NODELABEL(gpio_pg_pcore_s0_r_od)));
+}
+
+void baseboard_s0_pgood(enum gpio_signal signal)
+{
+	baseboard_set_soc_pwr_pgood(signal);
+
+	/* Chain off power signal interrupt handler for PG_PCORE_S0_R_OD */
+	power_signal_interrupt(signal);
+}
+
+/* Note: signal parameter unused */
+void baseboard_set_en_pwr_pcore(enum gpio_signal unused)
+{
+	/*
+	 * EC must AND signals PG_LPDDR5_S3_OD, PG_GROUPC_S0_OD, and
+	 * EN_PWR_S0_R
+	 */
+	gpio_pin_set_dt(
+		GPIO_DT_FROM_NODELABEL(gpio_en_pwr_pcore_s0),
+		gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_pg_lpddr5_s3_od)) &&
+			gpio_pin_get_dt(
+				GPIO_DT_FROM_NODELABEL(gpio_pg_groupc_s0_od)) &&
+			gpio_pin_get_dt(
+				GPIO_DT_FROM_NODELABEL(gpio_en_pwr_s0)));
+
+	/* Update EC_SOC_PWR_GOOD based on our results */
+	baseboard_set_soc_pwr_pgood(unused);
+}
+
+void baseboard_en_pwr_s0(enum gpio_signal signal)
+{
+	/* EC must AND signals SLP_S3_L and PG_PWR_S5 */
+	gpio_pin_set_dt(
+		GPIO_DT_FROM_NODELABEL(gpio_en_pwr_s0),
+		gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_slp_s3_l)) &&
+			gpio_pin_get_dt(
+				GPIO_DT_FROM_NODELABEL(gpio_pg_pwr_s5)));
+
+	/*
+	 * Thermaltrip interrupt has a pull-up to the S0 domain, enable/disable
+	 * so that we don't get spurious interrupts when S0 goes down.
+	 */
+	if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pwr_s0)))
+		gpio_enable_dt_interrupt(
+			GPIO_INT_FROM_NODELABEL(int_soc_thermtrip));
+	else
+		gpio_disable_dt_interrupt(
+			GPIO_INT_FROM_NODELABEL(int_soc_thermtrip));
+
+	/* Change EN_PWR_PCORE_S0_R if needed*/
+	baseboard_set_en_pwr_pcore(signal);
+
+	/* Now chain off to the normal power signal interrupt handler. */
+	power_signal_interrupt(signal);
+}
+
+void baseboard_s5_pgood(enum gpio_signal signal)
+{
+	/* Continue to our signal AND-ing and power interrupt */
+	baseboard_en_pwr_s0(signal);
+}
+
+void baseboard_set_en_pwr_s3(enum gpio_signal signal)
+{
+	/* Chain off the normal power signal interrupt handler */
+	power_signal_interrupt(signal);
+}
+
+void baseboard_soc_thermtrip(enum gpio_signal signal)
+{
+	ccprints("SoC thermtrip reported, shutting down");
+	chipset_force_shutdown(CHIPSET_SHUTDOWN_THERMAL);
+}
diff --git a/zephyr/program/myst/src/stt.c b/zephyr/program/myst/src/stt.c
new file mode 100644
index 0000000000..f739155ee6
--- /dev/null
+++ b/zephyr/program/myst/src/stt.c
@@ -0,0 +1,39 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Support code for STT temperature reporting */
+
+#include "chipset.h"
+#include "driver/temp_sensor/f75303.h"
+#include "temp_sensor/pct2075.h"
+#include "temp_sensor/temp_sensor.h"
+
+int board_get_soc_temp_mk(int *temp_mk)
+{
+	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+#ifdef CONFIG_TEMP_SENSOR_PCT2075
+	return pct2075_get_val_mk(PCT2075_SENSOR_ID(DT_NODELABEL(soc_pct2075)),
+				  temp_mk);
+#else
+	return f75303_get_val_mk(F75303_SENSOR_ID(DT_NODELABEL(soc_f75303)),
+				 temp_mk);
+#endif
+}
+
+int board_get_ambient_temp_mk(int *temp_mk)
+{
+	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+#ifdef CONFIG_TEMP_SENSOR_PCT2075
+	return pct2075_get_val_mk(PCT2075_SENSOR_ID(DT_NODELABEL(amb_pct2075)),
+				  temp_mk);
+#else
+	return f75303_get_val_mk(F75303_SENSOR_ID(DT_NODELABEL(amb_f75303)),
+				 temp_mk);
+#endif
+}
diff --git a/zephyr/program/myst/src/usb_pd_policy.c b/zephyr/program/myst/src/usb_pd_policy.c
new file mode 100644
index 0000000000..9e656e815f
--- /dev/null
+++ b/zephyr/program/myst/src/usb_pd_policy.c
@@ -0,0 +1,79 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Shared USB-C policy for Myst boards */
+
+#include "charge_manager.h"
+#include "chipset.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "ioexpander.h"
+#include "system.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#include <zephyr/drivers/gpio.h>
+
+int pd_check_vconn_swap(int port)
+{
+	/*
+	 * Do not allow vconn swap 5V rail is off
+	 * S5_PGOOD depends on PG_PP5000_S5 being asserted,
+	 * so GPIO_S5_PGOOD is a reasonable proxy for PP5000_S5
+	 */
+	return gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_pg_pwr_s5));
+}
+
+void pd_power_supply_reset(int port)
+{
+	/* Disable VBUS. */
+	ppc_vbus_source_enable(port, 0);
+
+	/* Enable discharge if we were previously sourcing 5V */
+	if (IS_ENABLED(CONFIG_USB_PD_DISCHARGE))
+		pd_set_vbus_discharge(port, 1);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	/* Disable charging. */
+	rv = ppc_vbus_sink_enable(port, 0);
+	if (rv)
+		return rv;
+
+	if (IS_ENABLED(CONFIG_USB_PD_DISCHARGE))
+		pd_set_vbus_discharge(port, 0);
+
+	/* Provide Vbus. */
+	rv = ppc_vbus_source_enable(port, 1);
+	if (rv)
+		return rv;
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+/* Used by Vbus discharge common code with CONFIG_USB_PD_DISCHARGE */
+int board_vbus_source_enabled(int port)
+{
+	return tcpm_get_src_ctrl(port);
+}
+
+/* Used by USB charger task with CONFIG_USB_PD_5V_EN_CUSTOM */
+int board_is_sourcing_vbus(int port)
+{
+	return board_vbus_source_enabled(port);
+}
diff --git a/zephyr/program/myst/src/usbc_config.c b/zephyr/program/myst/src/usbc_config.c
new file mode 100644
index 0000000000..985553edcd
--- /dev/null
+++ b/zephyr/program/myst/src/usbc_config.c
@@ -0,0 +1,286 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Myst family-specific USB-C configuration */
+
+#include "battery_fuel_gauge.h"
+#include "charge_manager.h"
+#include "charge_ramp.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+#include "driver/charger/isl9241.h"
+#include "driver/ppc/ktu1125_public.h"
+#include "driver/ppc/nx20p348x.h"
+#include "driver/tcpm/rt1718s.h"
+#include "driver/usb_mux/amd_fp6.h"
+#include "gpio.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "power.h"
+#include "usb_mux.h"
+#include "usb_pd_tcpm.h"
+#include "usbc/usb_muxes.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+#include <zephyr/drivers/gpio.h>
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_RT1718S
+#define GPIO_EN_USB_C1_SINK RT1718S_GPIO1
+#define GPIO_EN_USB_C1_SOURCE RT1718S_GPIO2
+#define GPIO_EN_USB_C1_FRS RT1718S_GPIO3
+#endif
+
+static uint32_t get_io_db_type_from_cached_cbi(void)
+{
+	uint32_t io_db_type;
+	int ret = cros_cbi_get_fw_config(FW_IO_DB, &io_db_type);
+
+	if (ret != 0) {
+		io_db_type = FW_IO_DB_NONE;
+	}
+
+	return io_db_type;
+}
+
+static void usbc_interrupt_init(void)
+{
+	/* Enable PPC interrupts. */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_ppc));
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_ppc));
+
+	/* Process any interrupts that are already present */
+	if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_ppc_int_odl)))
+		ppc_interrupt(GPIO_USB_C0_PPC_INT_ODL);
+	if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_ppc_int_odl)))
+		ppc_interrupt(GPIO_USB_C1_PPC_INT_ODL);
+
+	/* Reset TCPC if we only have a battery connected, or the SINK
+	 * gpio to the PPC might be reset and cause brown-out.
+	 */
+	if (!system_jumped_late() && battery_is_present() == BP_YES) {
+		/* TODO(crosbug.com/p/61098): How long do we need to wait? */
+		board_reset_pd_mcu();
+	}
+}
+DECLARE_HOOK(HOOK_INIT, usbc_interrupt_init, HOOK_PRIO_POST_I2C);
+
+int ppc_get_alert_status(int port)
+{
+	if (port == USBC_PORT_C0)
+		return gpio_pin_get_dt(
+			GPIO_DT_FROM_NODELABEL(gpio_usb_c0_ppc_int_odl));
+	else if (port == USBC_PORT_C1)
+		return gpio_pin_get_dt(
+			GPIO_DT_FROM_NODELABEL(gpio_usb_c1_ppc_int_odl));
+	return 0;
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int i;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTSUSB("Disabling all charger ports");
+		/* Disable all ports. */
+		for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (ppc_vbus_sink_enable(i, 0))
+				CPRINTSUSB("Disabling C%d as sink failed.", i);
+		}
+		return EC_SUCCESS;
+	} else if (!is_valid_port) {
+		return EC_ERROR_INVAL;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (tcpm_get_src_ctrl(port)) {
+		CPRINTSUSB("Skip enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTSUSB("New charge port: C%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+		if (i == port)
+			continue;
+
+		if (ppc_vbus_sink_enable(i, 0))
+			CPRINTSUSB("C%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTSUSB("C%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+void usb_pd_soc_interrupt(enum gpio_signal signal)
+{
+	/*
+	 * This interrupt is unexpected with our use of the SoC mux, so just log
+	 * it as a point of interest.
+	 */
+	CPRINTSUSB("SOC PD Interrupt");
+}
+
+/* Round up 3250 max current to multiple of 128mA for ISL9241 AC prochot. */
+static void charger_prochot_init_isl9241(void)
+{
+	isl9241_set_ac_prochot(CHARGER_SOLO, CONFIG_AC_PROCHOT_CURRENT_MA);
+}
+DECLARE_HOOK(HOOK_INIT, charger_prochot_init_isl9241, HOOK_PRIO_DEFAULT);
+
+void board_reset_pd_mcu(void)
+{
+	uint32_t io_db_type = get_io_db_type_from_cached_cbi();
+	/* reset C1 RT1718s */
+	if (io_db_type == FW_IO_DB_SKU_A)
+		rt1718s_sw_reset(USBC_PORT_C1);
+}
+
+__override int board_rt1718s_init(int port)
+{
+	static bool gpio_initialized;
+
+	/* Reset TCPC sink/source control when it's a power-on reset or has a
+	 * battery. Do not alter the carried GPIO status or this might stop PPC
+	 * sinking and brown-out the system when battery disconnected.
+	 */
+	if (!system_jumped_late() && !gpio_initialized &&
+	    (battery_is_present() == BP_YES ||
+	     (system_get_reset_flags() & EC_RESET_FLAG_POWER_ON))) {
+		/* set GPIO 1~3 as push pull, as output, output low. */
+		rt1718s_gpio_set_flags(port, RT1718S_GPIO1, GPIO_OUT_LOW);
+		rt1718s_gpio_set_flags(port, RT1718S_GPIO2, GPIO_OUT_LOW);
+		rt1718s_gpio_set_flags(port, RT1718S_GPIO3, GPIO_OUT_LOW);
+		gpio_initialized = true;
+	}
+
+	/* gpio1 low, gpio2 output high when receiving frs signal */
+	RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_GPIO1_VBUS_CTRL,
+					  RT1718S_GPIO_VBUS_CTRL_FRS_RX_VBUS,
+					  0));
+	/* GPIO1 EN_SNK high when received TCPCI SNK enabled command */
+	RETURN_ERROR(rt1718s_update_bits8(
+		port, RT1718S_GPIO1_VBUS_CTRL,
+		RT1718S_GPIO_VBUS_CTRL_ENA_SNK_VBUS_GPIO, 0xFF));
+	/* GPIO2 EN_SRC high when received TCPCI SRC enabled command */
+	RETURN_ERROR(rt1718s_update_bits8(
+		port, RT1718S_GPIO2_VBUS_CTRL,
+		RT1718S_GPIO_VBUS_CTRL_FRS_RX_VBUS |
+			RT1718S_GPIO_VBUS_CTRL_ENA_SRC_VBUS_GPIO,
+		0xFF));
+
+	/* Trigger GPIO 1/2 change when FRS signal received */
+	RETURN_ERROR(rt1718s_update_bits8(
+		port, RT1718S_FRS_CTRL3,
+		RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO2 |
+			RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO1,
+		RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO2 |
+			RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO1));
+	/* Set FRS signal detect time to 46.875us */
+	RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_FRS_CTRL1,
+					  RT1718S_FRS_CTRL1_FRSWAPRX_MASK,
+					  0xFF));
+
+	/* Disable BC1.2 SRC mode */
+	RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_RT2_BC12_SRC_FUNC,
+					  RT1718S_RT2_BC12_SRC_FUNC_BC12_SRC_EN,
+					  0));
+	/* Disable BC1.2 SNK mode */
+	RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_RT2_BC12_SNK_FUNC,
+					  RT1718S_RT2_BC12_SNK_FUNC_BC12_SNK_EN,
+					  0));
+
+	return EC_SUCCESS;
+}
+
+__override int board_rt1718s_set_frs_enable(int port, int enable)
+{
+	if (port == USBC_PORT_C1)
+		/*
+		 * Use set_flags (implemented by a single i2c write) instead
+		 * of set_level (= i2c_update) to save one read operation in
+		 * FRS path.
+		 */
+		rt1718s_gpio_set_flags(port, GPIO_EN_USB_C1_FRS,
+				       enable ? GPIO_OUT_HIGH : GPIO_OUT_LOW);
+	else {
+		CPRINTSUSB("Skip rt1718 FRS enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	return EC_SUCCESS;
+}
+
+__override int board_rt1718s_set_snk_enable(int port, int enable)
+{
+	rt1718s_gpio_set_level(port, GPIO_EN_USB_C1_SINK, enable);
+
+	return EC_SUCCESS;
+}
+__override int board_rt1718s_set_src_enable(int port, int enable)
+{
+	rt1718s_gpio_set_level(port, GPIO_EN_USB_C1_SOURCE, enable);
+
+	return EC_SUCCESS;
+}
+
+__override int board_get_vbus_voltage(int port)
+{
+	int voltage = 0;
+	uint32_t io_db_type = get_io_db_type_from_cached_cbi();
+
+	if (io_db_type == FW_IO_DB_SKU_A)
+		rt1718s_get_adc(port, RT1718S_ADC_VBUS1, &voltage);
+	else if (charger_get_vbus_voltage(port, &voltage))
+		voltage = 0;
+
+	return voltage;
+}
+
+#define SAFE_RESET_VBUS_DELAY_MS 900
+#define SAFE_RESET_VBUS_MV 5000
+void board_hibernate(void)
+{
+	int port;
+	enum ec_error_list ret;
+
+	/*
+	 * If we are charging, then drop the Vbus level down to 5V to ensure
+	 * that we don't get locked out of the 6.8V OVLO for our PPCs in
+	 * dead-battery mode. This is needed when the TCPC/PPC rails go away.
+	 * (b/79218851, b/143778351, b/147007265)
+	 */
+	port = charge_manager_get_active_charge_port();
+	if (port != CHARGE_PORT_NONE) {
+		pd_request_source_voltage(port, SAFE_RESET_VBUS_MV);
+
+		/* Give PD task and PPC chip time to get to 5V */
+		msleep(SAFE_RESET_VBUS_DELAY_MS);
+	}
+
+	/* Try to put our battery fuel gauge into sleep mode */
+	ret = battery_sleep_fuel_gauge();
+	if ((ret != EC_SUCCESS) && (ret != EC_ERROR_UNIMPLEMENTED))
+		cprints(CC_SYSTEM, "Failed to send battery sleep command");
+}
diff --git a/zephyr/program/myst/usbc.dtsi b/zephyr/program/myst/usbc.dtsi
new file mode 100644
index 0000000000..9996f6a134
--- /dev/null
+++ b/zephyr/program/myst/usbc.dtsi
@@ -0,0 +1,32 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		usbc_port0: port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+			tcpc = <&tcpc_port0>;
+			chg = <&charger>;
+			ppc = <&ppc_port0>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&amd_fp6_port0>;
+			};
+		};
+
+		usbc_port1: port1@1 {
+			compatible = "named-usbc-port";
+			reg = <1>;
+			usb-mux-chain-1-anx {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&amd_fp6_port1>;
+			};
+		};
+	};
+};
diff --git a/zephyr/program/nissa/BUILD.py b/zephyr/program/nissa/BUILD.py
new file mode 100644
index 0000000000..fce86e7c71
--- /dev/null
+++ b/zephyr/program/nissa/BUILD.py
@@ -0,0 +1,119 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Define zmake projects for nissa."""
+
+# Nivviks and Craask, Pujjo, Xivu, Xivur, Uldren has NPCX993F, Nereid
+# and Joxer, Yaviks, Yavilla has ITE81302
+
+
+def register_nissa_project(
+    project_name,
+    chip="it81302bx",
+):
+    """Register a variant of nissa."""
+    register_func = register_binman_project
+    if chip.startswith("npcx"):
+        register_func = register_npcx_project
+
+    chip_kconfig = {"it81302bx": "it8xxx2", "npcx9m3f": "npcx"}[chip]
+
+    return register_func(
+        project_name=project_name,
+        zephyr_board=chip,
+        dts_overlays=[here / project_name / "project.overlay"],
+        kconfig_files=[
+            here / "program.conf",
+            here / f"{chip_kconfig}_program.conf",
+            here / project_name / "project.conf",
+        ],
+        inherited_from=["nissa"],
+    )
+
+
+def register_nivviks_project(
+    project_name,
+):
+    """Wrapper function for registering a variant of nivviks."""
+    return register_nissa_project(
+        project_name=project_name,
+        chip="npcx9m3f",
+    )
+
+
+def register_nereid_project(
+    project_name,
+):
+    """Wrapper function for registering a variant of nereid."""
+    return register_nissa_project(
+        project_name=project_name,
+        chip="it81302bx",
+    )
+
+
+nivviks = register_nissa_project(
+    project_name="nivviks",
+    chip="npcx9m3f",
+)
+
+nereid = register_nissa_project(
+    project_name="nereid",
+    chip="it81302bx",
+)
+
+nereid_cx = register_binman_project(
+    project_name="nereid_cx",
+    zephyr_board="it81302cx",
+    dts_overlays=[here / "nereid" / "project.overlay"],
+    kconfig_files=[
+        here / "program.conf",
+        here / "it8xxx2_program.conf",
+        here / "it8xxx2cx_program.conf",
+        here / "nereid" / "project.conf",
+    ],
+)
+
+craask = register_nissa_project(
+    project_name="craask",
+    chip="npcx9m3f",
+)
+
+pujjo = register_nissa_project(
+    project_name="pujjo",
+    chip="npcx9m3f",
+)
+
+xivu = register_nissa_project(
+    project_name="xivu",
+    chip="npcx9m3f",
+)
+
+xivur = register_nissa_project(
+    project_name="xivur",
+    chip="npcx9m3f",
+)
+
+joxer = register_nissa_project(
+    project_name="joxer",
+    chip="it81302bx",
+)
+
+yaviks = register_nissa_project(
+    project_name="yaviks",
+    chip="it81302bx",
+)
+
+yavilla = register_nissa_project(
+    project_name="yavilla",
+    chip="it81302bx",
+)
+
+uldren = register_nissa_project(
+    project_name="uldren",
+    chip="npcx9m3f",
+)
+gothrax = register_nissa_project(
+    project_name="gothrax",
+    chip="it81302bx",
+)
diff --git a/zephyr/program/nissa/CMakeLists.txt b/zephyr/program/nissa/CMakeLists.txt
new file mode 100644
index 0000000000..09b5d5db31
--- /dev/null
+++ b/zephyr/program/nissa/CMakeLists.txt
@@ -0,0 +1,136 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+
+zephyr_include_directories(include)
+zephyr_library_sources("src/common.c")
+zephyr_library_sources_ifdef(CONFIG_NISSA_SUB_BOARD "src/sub_board.c")
+zephyr_library_sources_ifdef(CONFIG_AP_PWRSEQ "src/board_power.c")
+
+if(DEFINED CONFIG_BOARD_NIVVIKS)
+	project(nivviks)
+	zephyr_library_sources(
+			"nivviks/src/led.c"
+			"nivviks/src/form_factor.c"
+			"nivviks/src/keyboard.c"
+	)
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FAN "nivviks/src/fan.c")
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "nivviks/src/usbc.c")
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "nivviks/src/charger.c")
+endif()
+if(DEFINED CONFIG_BOARD_NEREID OR DEFINED CONFIG_BOARD_NEREID_CX)
+	project(nereid)
+	zephyr_library_sources(
+			"src/led.c"
+			"nereid/src/keyboard.c"
+			"nereid/src/hdmi.c"
+	)
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "nereid/src/usbc.c")
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "nereid/src/charger.c")
+endif()
+if(DEFINED CONFIG_BOARD_CRAASK)
+	zephyr_library_sources(
+			"craask/src/fan.c"
+			"craask/src/form_factor.c"
+			"craask/src/keyboard.c"
+			"craask/src/kb_backlight.c"
+			"craask/src/led.c"
+			"craask/src/thermal.c"
+	)
+	project(craask)
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "craask/src/usbc.c")
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "craask/src/charger.c")
+endif()
+if(DEFINED CONFIG_BOARD_PUJJO)
+	project(pujjo)
+	zephyr_library_sources(
+			"pujjo/src/led.c"
+			"pujjo/src/keyboard.c"
+			"pujjo/src/hdmi.c"
+			"pujjo/src/form_factor.c"
+	)
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FAN "pujjo/src/fan.c")
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "pujjo/src/usbc.c")
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "pujjo/src/charger.c")
+endif()
+if(DEFINED CONFIG_BOARD_XIVU)
+	project(xivu)
+	zephyr_library_sources(
+			"xivu/src/form_factor.c"
+			"xivu/src/keyboard.c"
+	)
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "xivu/src/usbc.c")
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "xivu/src/charger.c")
+endif()
+if(DEFINED CONFIG_BOARD_JOXER)
+	project(joxer)
+	zephyr_library_sources(
+			"joxer/src/led.c"
+			"joxer/src/keyboard.c"
+			"joxer/src/form_factor.c"
+			"joxer/src/board.c"
+	)
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "joxer/src/usbc.c")
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "joxer/src/charger.c")
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FAN "joxer/src/fan.c")
+endif()
+if(DEFINED CONFIG_BOARD_YAVIKS)
+	project(yaviks)
+	zephyr_library_sources(
+			"yaviks/src/led.c"
+			"yaviks/src/keyboard.c"
+			"yaviks/src/board.c"
+			"yaviks/src/thermal.c"
+	)
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "yaviks/src/usbc.c")
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "yaviks/src/charger.c")
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FAN "yaviks/src/fan.c")
+endif()
+if(DEFINED CONFIG_BOARD_YAVILLA)
+	project(yavilla)
+	zephyr_library_sources(
+			"yavilla/src/led.c"
+			"yavilla/src/keyboard.c"
+			"yavilla/src/board.c"
+			"yavilla/src/thermal.c"
+	)
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "yavilla/src/usbc.c")
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "yavilla/src/charger.c")
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FAN "yavilla/src/fan.c")
+endif()
+if(DEFINED CONFIG_BOARD_XIVUR)
+	project(xivur)
+	zephyr_library_sources(
+			"xivur/src/led.c"
+			"xivur/src/board.c"
+			"xivur/src/keyboard.c"
+	)
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FAN "xivur/src/fan.c")
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "xivur/src/usbc.c")
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "xivur/src/charger.c")
+endif()
+if(DEFINED CONFIG_BOARD_ULDREN)
+	project(uldren)
+	zephyr_library_sources(
+			"uldren/src/form_factor.c"
+			"uldren/src/kb_backlight.c"
+			"uldren/src/sub_board.c"
+	)
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "uldren/src/usbc.c")
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "uldren/src/charger.c")
+endif()
+if(DEFINED CONFIG_BOARD_GOTHRAX)
+	project(gothrax)
+	zephyr_library_sources(
+			"src/led.c"
+			"gothrax/src/keyboard.c"
+			"gothrax/src/hdmi.c"
+	)
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "gothrax/src/usbc.c")
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "gothrax/src/charger.c")
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FAN "gothrax/src/fan.c")
+endif()
diff --git a/zephyr/program/nissa/Kconfig b/zephyr/program/nissa/Kconfig
new file mode 100644
index 0000000000..d31f420c76
--- /dev/null
+++ b/zephyr/program/nissa/Kconfig
@@ -0,0 +1,90 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config NISSA_SUB_BOARD
+	bool "Nissa sub-board support"
+	default y
+	help
+	  Enable the sub-board support for Nissa boards.
+	  This uses a common fw_config bitfield to select
+	  one of a number of option sub-boards with different
+	  hardware configurations.
+
+config BOARD_NIVVIKS
+	bool "Google Nivviks Board"
+	help
+	  Build Google Nivviks reference board. Nivviks has Intel ADL-N SoC
+	  with NPCX993FA0BX EC.
+
+config BOARD_NEREID
+	bool "Google Nereid Board"
+	help
+	  Build Google Nereid reference board. Nereid has Intel ADL-N SoC
+	  with IT81302 EC.
+
+config BOARD_NEREID_CX
+	bool "Google Nereid Board with IT81302 CX"
+	help
+	  Build Google Nereid reference board, but with IT81302 CX EC rather
+	  than IT81302 BX.
+
+config BOARD_CRAASK
+	bool "Google Craask Board"
+	help
+	  Build Google Craask board. Craask has Intel ADL-N SoC
+	  with NPCX993FA0BX EC.
+
+config BOARD_PUJJO
+	bool "Google Pujjo Board"
+	help
+	  Build Google Pujjo board. Pujjo has Intel ADL-N SoC
+	  with NPCX993FA0BX EC.
+
+config BOARD_XIVU
+        bool "Google Xivu Board"
+        help
+          Build Google Xivu board. Xivu has Intel ADL-N SoC
+          with NPCX993FA0BX EC.
+
+config BOARD_XIVUR
+        bool "Google Xivur Board"
+        help
+          Build Google Xivur board. Xivur has Intel ADL-N SoC
+          with NPCX993FA0BX EC.
+
+config BOARD_JOXER
+	bool "Google Joxer Board"
+	help
+	  Build Google Joxer reference board. Joxer has Intel ADL-N SoC
+	  with IT81302 EC.
+
+config BOARD_YAVIKS
+	bool "Google Yaviks Board"
+	help
+	  Build Google Yaviks board. Yaviks has Intel ADL-N SoC
+	  with IT81302 EC.
+
+config BOARD_YAVILLA
+	bool "Google Yavilla Board"
+	help
+	  Build Google Yavilla board. Yavilla has Intel ADL-N SoC
+	  with IT81302 EC.
+
+config BOARD_ULDREN
+	bool "Google Uldren Board"
+	help
+	  Build Google Uldren reference board. Uldren has Intel ADL-N SoC
+	  with NPCX993FA0BX EC.
+
+config BOARD_GOTHRAX
+	bool "Google Gothrax Board"
+	help
+	  Build Google Gothrax reference board. Gothrax has Intel ADL-N SoC
+	  with IT81302 EC.
+
+module = NISSA
+module-str = Nissa board-specific code
+source "subsys/logging/Kconfig.template.log_config"
+
+source "Kconfig.zephyr"
diff --git a/zephyr/program/nissa/cbi.dtsi b/zephyr/program/nissa/cbi.dtsi
new file mode 100644
index 0000000000..d841be1624
--- /dev/null
+++ b/zephyr/program/nissa/cbi.dtsi
@@ -0,0 +1,61 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	nissa-fw-config {
+		compatible = "cros-ec,cbi-fw-config";
+
+		/*
+		 * FW_CONFIG field to indicate which sub-board
+		 * is attached.
+		 */
+		sub-board {
+			enum-name = "FW_SUB_BOARD";
+			start = <0>;
+			size = <2>;
+
+			sub-board-1 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_SUB_BOARD_1";
+				value = <1>;
+			};
+			sub-board-2 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_SUB_BOARD_2";
+				value = <2>;
+			};
+			sub-board-3 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_SUB_BOARD_3";
+				value = <3>;
+			};
+		};
+
+		/*
+		 * FW_CONFIG field to enable fan or not.
+		 */
+		fan {
+			enum-name = "FW_FAN";
+			start = <2>;
+			size = <1>;
+
+			no-fan {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FAN_NOT_PRESENT";
+				value = <0>;
+			};
+			fan-present {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FAN_PRESENT";
+				value = <1>;
+				/*
+				 * Set as default so that unprovisioned
+				 * configs will run the fan regardless.
+				 */
+				default;
+			};
+		};
+	};
+};
diff --git a/zephyr/program/nissa/craask/cbi.dtsi b/zephyr/program/nissa/craask/cbi.dtsi
new file mode 100644
index 0000000000..e381f57f1b
--- /dev/null
+++ b/zephyr/program/nissa/craask/cbi.dtsi
@@ -0,0 +1,195 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	/* Craask-specific fw_config fields. */
+	nissa-fw-config {
+		/*
+		 * FW_CONFIG field to describe Lid sensor orientation.
+		 */
+		lid-inversion {
+			enum-name = "FW_LID_INVERSION";
+			start = <8>;
+			size = <1>;
+
+			/*
+			 * 0: regular placement of the lid sensor
+			 * 1: rotate 180' of xy plane.
+			 */
+			regular {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_LID_REGULAR";
+				value = <0>;
+				default;
+			};
+			xy_rotate_180 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_LID_XY_ROT_180";
+				value = <1>;
+			};
+		};
+		/*
+		 * FW_CONFIG field to describe Clamshell/Convertible.
+		 */
+		form_factor {
+			enum-name = "FORM_FACTOR";
+			start = <9>;
+			size = <1>;
+
+			/*
+			 * 0: convertible, 1: clamshell
+			 */
+			convertible {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "CONVERTIBLE";
+				value = <0>;
+			};
+			clamshell {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "CLAMSHELL";
+				value = <1>;
+			};
+		};
+
+		/*
+		 * FW_CONFIG field to select thermal solution.
+		 */
+		thermal_solution {
+			enum-name = "FW_THERMAL";
+			start = <10>;
+			size = <3>;
+
+			6w-thermal {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_THERMAL_6W";
+				value = <0>;
+				default;
+			};
+			15w-thermal {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_THERMAL_15W";
+				value = <1>;
+			};
+		};
+
+		/*
+		 * FW_CONFIG field to indicate which keyboard numeric
+		 * pad should be used.
+		 */
+		kb-numeric-pad {
+			enum-name = "FW_KB_NUMERIC_PAD";
+			start = <16>;
+			size = <1>;
+
+			no-kb-numpad {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_KB_NUMERIC_PAD_ABSENT";
+				value = <0>;
+				default;
+			};
+			kb-numpad-present {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_KB_NUMERIC_PAD_PRESENT";
+				value = <1>;
+			};
+		};
+
+		/*
+		 * FW_CONFIG field to enable fan or not.
+		 */
+		fan {
+			enum-name = "FW_FAN";
+			start = <17>;
+			size = <1>;
+
+			no-fan {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FAN_NOT_PRESENT";
+				value = <0>;
+			};
+			fan-present {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FAN_PRESENT";
+				value = <1>;
+				/*
+				 * Set as default so that unprovisioned
+				 * configs will run the fan regardless.
+				 */
+				default;
+			};
+		};
+
+		/*
+		 * FW_CONFIG field to enable KB back light or not.
+		 */
+		kb-bl {
+			enum-name = "FW_KB_BL";
+			start = <18>;
+			size = <1>;
+
+			no-kb-bl {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_KB_BL_NOT_PRESENT";
+				value = <0>;
+			};
+			kb-bl-present {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_KB_BL_PRESENT";
+				value = <1>;
+			};
+		};
+	};
+	/* Craask-specific ssfc fields. */
+	cbi-ssfc {
+		compatible = "cros-ec,cbi-ssfc";
+		/*
+		 * SSFC bit0-1 was defined for AUDIO CODEC.
+		 * 0: ALC5682I_VS
+		 * 1: NAU8825
+		 */
+		audio_codec {
+			enum-name = "AUDIO_CODEC";
+			size = <2>;
+		};
+		/*
+		 * SSFC field to identify LID motion sensor.
+		 */
+		lid-sensor {
+			enum-name = "LID_SENSOR";
+			size = <2>;
+
+			lid_sensor_0: lis2dw12 {
+				compatible = "cros-ec,cbi-ssfc-value";
+				status = "okay";
+				value = <0>;
+				default;
+			};
+			lid_sensor_1: bma422 {
+				compatible = "cros-ec,cbi-ssfc-value";
+				status = "okay";
+				value = <1>;
+			};
+		};
+		/*
+		 * SSFC field to identify BASE motion sensor.
+		 */
+		base-sensor {
+			enum-name = "BASE_SENSOR";
+			size = <2>;
+
+			base_sensor_0: lsm6dso {
+				compatible = "cros-ec,cbi-ssfc-value";
+				status = "okay";
+				value = <0>;
+				default;
+			};
+			base_sensor_1: bmi323 {
+				compatible = "cros-ec,cbi-ssfc-value";
+				status = "okay";
+				value = <1>;
+			};
+		};
+	};
+};
diff --git a/zephyr/program/nissa/craask/fan.dtsi b/zephyr/program/nissa/craask/fan.dtsi
new file mode 100644
index 0000000000..dda572c0de
--- /dev/null
+++ b/zephyr/program/nissa/craask/fan.dtsi
@@ -0,0 +1,146 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/ {
+	fans {
+		compatible = "cros-ec,fans";
+		fan_0 {
+			pwms = <&pwm5 5 PWM_KHZ(25) PWM_POLARITY_NORMAL>;
+			tach = <&tach2>;
+			rpm_min = <2500>;
+			rpm_start = <2500>;
+			rpm_max = <6000>;
+			enable_gpio = <&gpio_fan_enable>;
+		};
+	};
+
+	fan_steps_6w: fan-steps-6w {
+		compatible = "cros-ec,fan-steps";
+		level_0 {
+			temp_on = <25>;
+			temp_off = <99>;
+			rpm_target = <0>;
+		};
+		level_1 {
+			temp_on = <40>;
+			temp_off = <35>;
+			rpm_target = <2500>;
+		};
+		level_2 {
+			temp_on = <44>;
+			temp_off = <41>;
+			rpm_target = <2800>;
+		};
+		level_3 {
+			temp_on = <48>;
+			temp_off = <45>;
+			rpm_target = <3000>;
+		};
+		level_4 {
+			temp_on = <52>;
+			temp_off = <49>;
+			rpm_target = <3200>;
+		};
+		level_5 {
+			temp_on = <60>;
+			temp_off = <54>;
+			rpm_target = <3600>;
+		};
+		level_6 {
+			temp_on = <64>;
+			temp_off = <58>;
+			rpm_target = <4000>;
+		};
+		level_7 {
+			temp_on = <67>;
+			temp_off = <62>;
+			rpm_target = <4600>;
+		};
+		level_8 {
+			temp_on = <71>;
+			temp_off = <66>;
+			rpm_target = <5000>;
+		};
+		level_9 {
+			temp_on = <74>;
+			temp_off = <70>;
+			rpm_target = <5500>;
+		};
+	};
+
+	fan_steps_15w: fan-steps-15w {
+		compatible = "cros-ec,fan-steps";
+		level_0 {
+			temp_on = <25>;
+			temp_off = <99>;
+			rpm_target = <0>;
+		};
+		level_1 {
+			temp_on = <37>;
+			temp_off = <34>;
+			rpm_target = <2500>;
+		};
+		level_2 {
+			temp_on = <42>;
+			temp_off = <39>;
+			rpm_target = <2800>;
+		};
+		level_3 {
+			temp_on = <46>;
+			temp_off = <43>;
+			rpm_target = <3000>;
+		};
+		level_4 {
+			temp_on = <51>;
+			temp_off = <48>;
+			rpm_target = <3200>;
+		};
+		level_5 {
+			temp_on = <55>;
+			temp_off = <52>;
+			rpm_target = <3600>;
+		};
+		level_6 {
+			temp_on = <59>;
+			temp_off = <56>;
+			rpm_target = <4000>;
+		};
+		level_7 {
+			temp_on = <66>;
+			temp_off = <63>;
+			rpm_target = <4600>;
+		};
+		level_8 {
+			temp_on = <72>;
+			temp_off = <69>;
+			rpm_target = <5000>;
+		};
+		level_9 {
+			temp_on = <74>;
+			temp_off = <71>;
+			rpm_target = <5500>;
+		};
+	};
+};
+
+&pwm5_gpb7 {
+	drive-open-drain;
+};
+
+/* pwm for fan */
+&pwm5 {
+	status = "okay";
+	pinctrl-0 = <&pwm5_gpb7>;
+	pinctrl-names = "default";
+};
+
+/* Tachometer for fan speed measurement */
+&tach2 {
+	status = "okay";
+	pinctrl-0 = <&ta2_1_in_gp73>;
+	pinctrl-names = "default";
+	port = <NPCX_TACH_PORT_A>; /* port-A is selected */
+	sample-clk = <NPCX_TACH_FREQ_LFCLK>; /* Use LFCLK as sampling clock */
+	pulses-per-round = <2>; /* number of pulses per round of encoder */
+};
diff --git a/zephyr/program/nissa/craask/generated.dtsi b/zephyr/program/nissa/craask/generated.dtsi
new file mode 100644
index 0000000000..062890f7c3
--- /dev/null
+++ b/zephyr/program/nissa/craask/generated.dtsi
@@ -0,0 +1,289 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc {
+			enum-name = "ADC_PP1050_PROC";
+			io-channels = <&adc0 4>;
+		};
+		adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 {
+			enum-name = "ADC_PP3300_S5";
+			io-channels = <&adc0 6>;
+		};
+		adc_temp_sensor_1: temp_sensor_1 {
+			enum-name = "ADC_TEMP_SENSOR_1";
+			io-channels = <&adc0 0>;
+		};
+		adc_temp_sensor_2: temp_sensor_2 {
+			enum-name = "ADC_TEMP_SENSOR_2";
+			io-channels = <&adc0 1>;
+		};
+		adc_temp_sensor_3: temp_sensor_3 {
+			enum-name = "ADC_TEMP_SENSOR_3";
+			io-channels = <&adc0 10>;
+		};
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		gpio_acc_int_l: acc_int_l {
+			gpios = <&gpio5 0 GPIO_INPUT>;
+		};
+		gpio_all_sys_pwrgd: all_sys_pwrgd {
+			gpios = <&gpioa 7 GPIO_INPUT>;
+		};
+		gpio_ccd_mode_odl: ccd_mode_odl {
+			gpios = <&gpioe 5 GPIO_INPUT>;
+			enum-name = "GPIO_CCD_MODE_ODL";
+		};
+		gpio_cpu_c10_gate_l: cpu_c10_gate_l {
+			gpios = <&gpio6 7 GPIO_INPUT>;
+		};
+		gpio_ec_battery_pres_odl: ec_battery_pres_odl {
+			gpios = <&gpioa 3 GPIO_INPUT>;
+			enum-name = "GPIO_BATT_PRES_ODL";
+		};
+		gpio_ec_cbi_wp: ec_cbi_wp {
+			gpios = <&gpio7 4 GPIO_OUTPUT>;
+		};
+		gpio_ec_edp_bl_en_od: ec_edp_bl_en_od {
+			gpios = <&gpiod 3 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_ENABLE_BACKLIGHT";
+		};
+		gpio_ec_entering_rw: ec_entering_rw {
+			gpios = <&gpio0 3 GPIO_OUTPUT>;
+			enum-name = "GPIO_ENTERING_RW";
+		};
+		gpio_ec_gsc_packet_mode: ec_gsc_packet_mode {
+			gpios = <&gpio7 5 GPIO_OUTPUT>;
+			enum-name = "GPIO_PACKET_MODE_EN";
+		};
+		gpio_ec_kso_02_inv: ec_kso_02_inv {
+			gpios = <&gpio1 7 (GPIO_OUTPUT | GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_KBD_KSO2";
+		};
+		gpio_ec_pch_wake_odl: ec_pch_wake_odl {
+			gpios = <&gpiob 0 GPIO_ODR_LOW>;
+		};
+		gpio_ec_prochot_odl: ec_prochot_odl {
+			gpios = <&gpiof 1 GPIO_ODR_HIGH>;
+		};
+		gpio_ec_soc_dsw_pwrok: ec_soc_dsw_pwrok {
+			gpios = <&gpio6 1 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_hdmi_hpd: ec_soc_hdmi_hpd {
+			gpios = <&gpioe 4 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_int_odl: ec_soc_int_odl {
+			gpios = <&gpio8 0 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_EC_INT_L";
+		};
+		gpio_ec_soc_pch_pwrok_od: ec_soc_pch_pwrok_od {
+			gpios = <&gpio7 2 GPIO_ODR_HIGH>;
+		};
+		gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl {
+			gpios = <&gpioc 1 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_PCH_PWRBTN_L";
+		};
+		gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l {
+			gpios = <&gpioa 6 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_rtcrst: ec_soc_rtcrst {
+			gpios = <&gpio7 6 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_sys_pwrok: ec_soc_sys_pwrok {
+			gpios = <&gpio3 7 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_vccst_pwrgd_od: ec_soc_vccst_pwrgd_od {
+			gpios = <&gpioa 4 GPIO_ODR_HIGH>;
+		};
+		gpio_ec_wp_odl: ec_wp_odl {
+			gpios = <&gpioa 1 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_en_kb_bl: en_kb_bl {
+			gpios = <&gpioa 0 GPIO_OUTPUT>;
+			enum-name = "GPIO_EN_KEYBOARD_BACKLIGHT";
+		};
+		gpio_en_pp3300_s5: en_pp3300_s5 {
+			gpios = <&gpiob 6 GPIO_OUTPUT>;
+			enum-name = "GPIO_TEMP_SENSOR_POWER";
+		};
+		gpio_en_pp5000_pen_x: en_pp5000_pen_x {
+			gpios = <&gpioe 2 GPIO_OUTPUT>;
+		};
+		gpio_en_pp5000_s5: en_pp5000_s5 {
+			gpios = <&gpio4 0 GPIO_OUTPUT>;
+		};
+		gpio_en_slp_z: en_slp_z {
+			gpios = <&gpioe 1 GPIO_OUTPUT>;
+		};
+		gpio_en_usb_a0_vbus: en_usb_a0_vbus {
+			gpios = <&gpio9 1 GPIO_OUTPUT>;
+		};
+		gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl {
+			gpios = <&gpio0 0 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		gpio_hdmi_sel: hdmi_sel {
+			gpios = <&gpioc 6 GPIO_OUTPUT>;
+		};
+		gpio_imu_int_l: imu_int_l {
+			gpios = <&gpio5 6 GPIO_INPUT>;
+		};
+		gpio_imvp91_vrrdy_od: imvp91_vrrdy_od {
+			gpios = <&gpio4 3 GPIO_INPUT>;
+		};
+		gpio_lid_open: lid_open {
+			gpios = <&gpiod 2 GPIO_INPUT>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+		gpio_pen_detect_odl: pen_detect_odl {
+			gpios = <&gpio9 6 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_pg_pp1050_mem_s3_od: pg_pp1050_mem_s3_od {
+			gpios = <&gpiof 0 GPIO_INPUT>;
+		};
+		gpio_pg_pp5000_s5_od: pg_pp5000_s5_od {
+			gpios = <&gpio4 2 GPIO_INPUT>;
+		};
+		gpio_rsmrst_pwrgd_l: rsmrst_pwrgd_l {
+			gpios = <&gpio9 4 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_slp_s0_l: slp_s0_l {
+			gpios = <&gpio9 7 GPIO_INPUT>;
+		};
+		gpio_slp_s3_l: slp_s3_l {
+			gpios = <&gpioa 5 GPIO_INPUT>;
+		};
+		gpio_slp_s4_l: slp_s4_l {
+			gpios = <&gpio7 0 GPIO_INPUT>;
+		};
+		gpio_slp_sus_l: slp_sus_l {
+			gpios = <&gpio6 2 GPIO_INPUT>;
+		};
+		gpio_sub_usb_a1_ilimit_sdp: sub_usb_a1_ilimit_sdp {
+			gpios = <&gpiod 5 GPIO_OUTPUT>;
+			enum-name = "GPIO_USB2_ILIM_SEL";
+		};
+		gpio_sys_rst_odl: sys_rst_odl {
+			gpios = <&gpioc 5 GPIO_ODR_HIGH>;
+		};
+		gpio_tablet_mode_l: tablet_mode_l {
+			gpios = <&gpio9 5 GPIO_INPUT>;
+			enum-name = "GPIO_TABLET_MODE_L";
+		};
+		gpio_usb_a0_ilimit_sdp: usb_a0_ilimit_sdp {
+			gpios = <&gpio3 3 GPIO_OUTPUT>;
+			enum-name = "GPIO_USB1_ILIM_SEL";
+		};
+		gpio_usb_c0_int_odl: usb_c0_int_odl {
+			gpios = <&gpio0 1 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_vccin_aux_vid0: vccin_aux_vid0 {
+			gpios = <&gpio9 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		gpio_vccin_aux_vid1: vccin_aux_vid1 {
+			gpios = <&gpioe 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		gpio_voldn_btn_odl: voldn_btn_odl {
+			gpios = <&gpio9 3 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_DOWN_L";
+		};
+		gpio_volup_btn_odl: volup_btn_odl {
+			gpios = <&gpioa 2 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_UP_L";
+		};
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		i2c_ec_i2c_eeprom: ec_i2c_eeprom {
+			i2c-port = <&i2c0_0>;
+			enum-names = "I2C_PORT_EEPROM";
+		};
+		i2c_ec_i2c_sensor: ec_i2c_sensor {
+			i2c-port = <&i2c1_0>;
+			enum-names = "I2C_PORT_SENSOR";
+		};
+		i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 {
+			i2c-port = <&i2c3_0>;
+			enum-names = "I2C_PORT_USB_C0_TCPC";
+		};
+		i2c_ec_i2c_sub_usb_c1: ec_i2c_sub_usb_c1 {
+			i2c-port = <&i2c5_1>;
+			enum-names = "I2C_PORT_USB_C1_TCPC";
+		};
+		i2c_ec_i2c_batt: ec_i2c_batt {
+			i2c-port = <&i2c7_0>;
+			enum-names = "I2C_PORT_BATTERY";
+		};
+	};
+};
+
+&adc0 {
+	status = "okay";
+	pinctrl-0 = <&adc0_chan0_gp45
+		     &adc0_chan1_gp44
+		     &adc0_chan4_gp41
+		     &adc0_chan6_gp34
+		     &adc0_chan10_gpe0>;
+	pinctrl-names = "default";
+};
+
+&i2c0_0 {
+	status = "okay";
+	pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>;
+	pinctrl-names = "default";
+};
+
+&i2c1_0 {
+	status = "okay";
+	pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>;
+	pinctrl-names = "default";
+};
+
+&i2c3_0 {
+	status = "okay";
+	pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>;
+	pinctrl-names = "default";
+};
+
+&i2c5_1 {
+	status = "okay";
+	pinctrl-0 = <&i2c5_1_sda_scl_gpf4_f5>;
+	pinctrl-names = "default";
+};
+
+&i2c7_0 {
+	status = "okay";
+	pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>;
+	pinctrl-names = "default";
+};
+
+&i2c_ctrl0 {
+	status = "okay";
+};
+
+&i2c_ctrl1 {
+	status = "okay";
+};
+
+&i2c_ctrl3 {
+	status = "okay";
+};
+
+&i2c_ctrl5 {
+	status = "okay";
+};
+
+&i2c_ctrl7 {
+	status = "okay";
+};
diff --git a/zephyr/program/nissa/craask/keyboard.dtsi b/zephyr/program/nissa/craask/keyboard.dtsi
new file mode 100644
index 0000000000..4b2fd8f9c2
--- /dev/null
+++ b/zephyr/program/nissa/craask/keyboard.dtsi
@@ -0,0 +1,58 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+&cros_kb_raw {
+	status = "okay";
+	/* No KSO2 (it's inverted and implemented by GPIO) */
+	pinctrl-0 = <
+		&ksi0_gp31
+		&ksi1_gp30
+		&ksi2_gp27
+		&ksi3_gp26
+		&ksi4_gp25
+		&ksi5_gp24
+		&ksi6_gp23
+		&ksi7_gp22
+		&kso00_gp21
+		&kso01_gp20
+		&kso03_gp16
+		&kso04_gp15
+		&kso05_gp14
+		&kso06_gp13
+		&kso07_gp12
+		&kso08_gp11
+		&kso09_gp10
+		&kso10_gp07
+		&kso11_gp06
+		&kso12_gp05
+		&kso13_gp04
+		&kso14_gp82
+	>;
+	pinctrl-1 = <
+		&ksi0_gpio_gp31
+		&ksi1_gpio_gp30
+		&ksi2_gpio_gp27
+		&ksi3_gpio_gp26
+		&ksi4_gpio_gp25
+		&ksi5_gpio_gp24
+		&ksi6_gpio_gp23
+		&ksi7_gpio_gp22
+		&kso00_gpio_gp21
+		&kso01_gpio_gp20
+		&kso03_gpio_gp16
+		&kso04_gpio_gp15
+		&kso05_gpio_gp14
+		&kso06_gpio_gp13
+		&kso07_gpio_gp12
+		&kso08_gpio_gp11
+		&kso09_gpio_gp10
+		&kso10_gpio_gp07
+		&kso11_gpio_gp06
+		&kso12_gpio_gp05
+		&kso13_gpio_gp04
+		&kso14_gpio_gp82
+	>;
+	pinctrl-names = "default", "sleep";
+};
diff --git a/zephyr/program/nissa/craask/motionsense.dtsi b/zephyr/program/nissa/craask/motionsense.dtsi
new file mode 100644
index 0000000000..941dfa2240
--- /dev/null
+++ b/zephyr/program/nissa/craask/motionsense.dtsi
@@ -0,0 +1,256 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/motionsense/utils.h>
+
+
+/ {
+	aliases {
+		/*
+		 * Interrupt bindings for sensor devices.
+		 */
+		lsm6dso-int = &base_accel;
+		lis2dw12-int = &lid_accel;
+		bmi3xx-int = &base_accel;
+		bma4xx-int = &lid_accel;
+	};
+
+	/*
+	 * Declare mutexes used by sensor drivers.
+	 * A mutex node is used to create an instance of mutex_t.
+	 * A mutex node is referenced by a sensor node if the
+	 * corresponding sensor driver needs to use the
+	 * instance of the mutex.
+	 */
+	motionsense-mutex {
+		compatible = "cros-ec,motionsense-mutex";
+		lid_mutex: lis2dw12-mutex {
+		};
+
+		lid_mutex_bma422: bma422-mutex {
+		};
+
+		base_mutex: base-mutex {
+		};
+
+		base_mutex_bmi323: bmi323-mutex {
+		};
+	};
+
+	/* Rotation matrix used by drivers. */
+	motionsense-rotation-ref {
+		compatible = "cros-ec,motionsense-rotation-ref";
+		lid_rot_ref: lid-rotation-ref {
+			mat33 = <(-1) 0 0
+				 0 1 0
+				 0 0 (-1)>;
+		};
+
+		base_rot_ref: base-rotation-ref {
+			mat33 = <1 0 0
+				 0 (-1) 0
+				 0 0 (-1)>;
+		};
+
+		base_rot_ver1: base-rotation-ver1 {
+			mat33 = <(-1) 0 0
+				 0 (-1) 0
+				 0 0 1>;
+		};
+
+		lid_rot_bma422: lid-rotation-bma {
+			mat33 = <1 0 0
+				 0 (-1) 0
+				 0 0 (-1)>;
+		};
+
+		base_rot_bmi323: base-rotation-bmi323 {
+			mat33 = <0 (-1) 0
+				 (-1) 0 0
+				 0 0 (-1)>;
+		};
+	};
+
+	/*
+	 * Driver specific data. A driver-specific data can be shared with
+	 * different motion sensors while they are using the same driver.
+	 *
+	 * If a node's compatible starts with "cros-ec,accelgyro-", it is for
+	 * a common structure defined in accelgyro.h.
+	 * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for
+	 * "struct als_drv_data_t" in accelgyro.h
+	 */
+	motionsense-sensor-data {
+		lsm6dso_accel_data: lsm6dso-accel-drv-data {
+			compatible = "cros-ec,drvdata-lsm6dso";
+			status = "okay";
+		};
+
+		lsm6dso_gyro_data: lsm6dso-gyro-drv-data {
+			compatible = "cros-ec,drvdata-lsm6dso";
+			status = "okay";
+		};
+
+		lis2dw12_data: lis2dw12-drv-data {
+			compatible = "cros-ec,drvdata-lis2dw12";
+			status = "okay";
+		};
+
+		bma422_data: bma4xx-drv-data {
+			compatible = "cros-ec,drvdata-bma4xx";
+			status = "okay";
+		};
+
+		bmi323_data: bmi323-drv-data {
+			compatible = "cros-ec,drvdata-bmi3xx";
+			status = "okay";
+		};
+	};
+
+	/*
+	 * List of motion sensors that creates motion_sensors array.
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
+	 * motion sensor IDs for lid angle calculation.
+	 * TODO(b/238139272): The first entries of the array must be
+	 * accelerometers,then gyroscope. Fix this dependency in the DTS
+	 * processing which makes the devicetree entries independent.
+	 */
+	motionsense-sensor {
+		lid_accel: lid-accel {
+			compatible = "cros-ec,lis2dw12";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&lid_mutex>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&lid_rot_ref>;
+			default-range = <2>;
+			drv-data = <&lis2dw12_data>;
+			i2c-spi-addr-flags = "LIS2DWL_ADDR0_FLAGS";
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_accel: base-accel {
+			compatible = "cros-ec,lsm6dso-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&lsm6dso_accel_data>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_gyro: base-gyro {
+			compatible = "cros-ec,lsm6dso-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			default-range = <(1000 | ROUND_UP_FLAG)>; /* dps */
+			drv-data = <&lsm6dso_gyro_data>;
+		};
+	};
+
+	motionsense-sensor-alt {
+		alt_lid_accel: alt-lid-accel {
+			compatible = "cros-ec,bma4xx";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&lid_mutex_bma422>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&lid_rot_bma422>;
+			default-range = <2>;
+			drv-data = <&bma422_data>;
+			i2c-spi-addr-flags = "BMA4_I2C_ADDR_PRIMARY";
+			alternate-for = <&lid_accel>;
+			alternate-ssfc-indicator = <&lid_sensor_1>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		alt_base_accel: alt-base-accel {
+			compatible = "cros-ec,bmi3xx-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex_bmi323>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&base_rot_bmi323>;
+			drv-data = <&bmi323_data>;
+			alternate-for = <&base_accel>;
+			alternate-ssfc-indicator = <&base_sensor_1>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		alt_base_gyro: alt-base-gyro {
+			compatible = "cros-ec,bmi3xx-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex_bmi323>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&base_rot_bmi323>;
+			drv-data = <&bmi323_data>;
+			alternate-for = <&base_gyro>;
+			alternate-ssfc-indicator = <&base_sensor_1>;
+		};
+	};
+
+	motionsense-sensor-info {
+		compatible = "cros-ec,motionsense-sensor-info";
+
+		/*
+		 * list of GPIO interrupts that have to
+		 * be enabled at initial stage
+		 */
+		sensor-irqs = <&int_imu &int_lid_accel>;
+	};
+};
diff --git a/zephyr/program/nissa/craask/overlay.dtsi b/zephyr/program/nissa/craask/overlay.dtsi
new file mode 100644
index 0000000000..caeecf9a78
--- /dev/null
+++ b/zephyr/program/nissa/craask/overlay.dtsi
@@ -0,0 +1,415 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <cros/thermistor/thermistor.dtsi>
+#include <dt-bindings/usbc_mux.h>
+#include <dt-bindings/usb_pd_tcpm.h>
+
+/ {
+	aliases {
+		gpio-cbi-wp = &gpio_ec_cbi_wp;
+		gpio-wp = &gpio_ec_wp_odl;
+		int-wp = &int_wp_l;
+		gpio-kbd-kso2 = &gpio_ec_kso_02_inv;
+	};
+
+	ec-console {
+		compatible = "ec-console";
+		disabled = "events", "lpc", "hostcmd";
+	};
+
+	batteries {
+		default_battery: lgc {
+			compatible = "lgc,ap18c8k", "battery-smart";
+		};
+		lgc_ap19b8m {
+			compatible = "lgc,ap19b8m", "battery-smart";
+		};
+		cosmx {
+			compatible = "cosmx,ap20cbl", "battery-smart";
+		};
+		cosmx-2 {
+			compatible = "cosmx,ap20cbl-2", "battery-smart";
+		};
+	};
+
+	hibernate-wake-pins {
+		compatible = "cros-ec,hibernate-wake-pins";
+		wakeup-irqs = <
+			&int_power_button
+			&int_lid_open
+		>;
+	};
+
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_power_button: power_button {
+			irq-pin = <&gpio_gsc_ec_pwr_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_button_interrupt";
+		};
+		int_wp_l: wp_l {
+			irq-pin = <&gpio_ec_wp_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "switch_interrupt";
+		};
+		int_lid_open: lid_open {
+			irq-pin = <&gpio_lid_open>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "lid_interrupt";
+		};
+		int_tablet_mode: tablet_mode {
+			irq-pin = <&gpio_tablet_mode_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "gmr_tablet_switch_isr";
+		};
+		int_imu: ec_imu {
+			irq-pin = <&gpio_imu_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "motion_interrupt";
+		};
+		int_lid_accel: ec_lid_accel {
+			irq-pin = <&gpio_acc_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "lid_accel_interrupt";
+		};
+		int_vol_down: vol_down {
+			irq-pin = <&gpio_voldn_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+		int_vol_up: vol_up {
+			irq-pin = <&gpio_volup_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+		int_usb_c0: usb_c0 {
+			irq-pin = <&gpio_usb_c0_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "usb_interrupt";
+		};
+		int_usb_c1: usb_c1 {
+			irq-pin = <&gpio_sb_1>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "usb_interrupt";
+		};
+	};
+
+	named-gpios {
+		gpio_sb_1: sb-1 {
+			gpios = <&gpio0 2 GPIO_PULL_UP>;
+			no-auto-init;
+		};
+
+		gpio_sb_2: sb-2 {
+			gpios = <&gpiod 4 GPIO_OUTPUT>;
+			no-auto-init;
+		};
+
+		/*
+		 * Set I2C pins for type C sub-board to be low voltage (I2C5_1).
+		 * We do this for all boards, since the pins are 3.3V tolerant,
+		 * and the only 2 types of sub-boards used on nivviks both have
+		 * type-C ports on them.
+		 */
+		gpio_sb_3: sb-3 {
+			gpios = <&gpiof 4 (GPIO_OPEN_DRAIN | GPIO_VOLTAGE_1P8)>;
+			no-auto-init;
+		};
+		gpio_sb_4: sb-4 {
+			gpios = <&gpiof 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+			no-auto-init;
+		};
+		gpio_fan_enable: fan-enable {
+			gpios = <&gpio6 3 GPIO_OUTPUT>;
+			no-auto-init;
+		};
+		ec-i2c-sensor-scl {
+			gpios = <&gpio9 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		ec-i2c-sensor-sda {
+			gpios = <&gpio8 7 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+	};
+
+	/*
+	 * Aliases used for sub-board GPIOs.
+	 */
+	aliases {
+		/*
+		 * Input GPIO when used with type-C port 1
+		 * Output when used with HDMI sub-board
+		 */
+		gpio-usb-c1-int-odl = &gpio_sb_1;
+		gpio-en-rails-odl = &gpio_sb_1;
+		/*
+		 * Sub-board with type A USB, enable.
+		 */
+		gpio-en-usb-a1-vbus = &gpio_sb_2;
+		/*
+		 * HPD pins for HDMI sub-board.
+		 */
+		gpio-hdmi-en-odl = &gpio_sb_3;
+		gpio-hpd-odl = &gpio_sb_4;
+		/*
+		 * Enable S5 rails for LTE sub-board
+		 */
+		gpio-en-sub-s5-rails = &gpio_sb_2;
+	};
+
+	temp_memory_thermistor: memory {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_1>;
+	};
+	temp_charger_thermistor: charger {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_2>;
+	};
+	temp_ambient_thermistor: ambient {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_3>;
+	};
+
+	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
+		temp_memory: memory {
+			temp_host_high = <78>;
+			temp_host_halt = <80>;
+			temp_host_release_high = <0>;
+			temp_host_release_halt = <75>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_memory_thermistor>;
+		};
+		temp_charger: charger {
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_charger_thermistor>;
+		};
+		temp_ambient: ambient {
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_ambient_thermistor>;
+		};
+	};
+
+	usba {
+		compatible = "cros-ec,usba-port-enable-pins";
+		/*
+		 * sb_2 is only configured as GPIO when USB-A1 is present,
+		 * but it's still safe to control when disabled.
+		 *
+		 * ILIM_SEL pins are referred to by legacy enum name,
+		 * GPIO_USB*_ILIM_SEL. The one for port A1 is unused on
+		 * sub-boards that don't have USB-A so is safe to control
+		 * regardless of system configuration.
+		 */
+		enable-pins = <&gpio_en_usb_a0_vbus &gpio_sb_2>;
+		status = "okay";
+	};
+
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+			bc12 = <&bc12_port0>;
+			chg = <&chg_port0>;
+			tcpc = <&tcpc_port0>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_0>;
+			};
+		};
+		port0-muxes {
+			virtual_mux_0: virtual-mux-0 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+		/*
+		 * TODO(b:211693800): port1 may not be present on some
+		 * sub-boards.
+		 */
+		port1@1 {
+			compatible = "named-usbc-port";
+			reg = <1>;
+			bc12 = <&bc12_port1>;
+			chg = <&chg_port1>;
+			tcpc = <&tcpc_port1>;
+			usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_1 &anx7483_mux_1>;
+			};
+			usb_mux_chain_1_no_mux: usb-mux-chain-1-no-mux {
+				compatible = "cros-ec,usb-mux-chain";
+				alternative-chain;
+				usb-muxes = <&virtual_mux_1>;
+			};
+		};
+		port1-muxes {
+			virtual_mux_1: virtual-mux-1 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+	};
+
+	kblight {
+		compatible = "cros-ec,kblight-pwm";
+		pwms = <&pwm6 6 PWM_KHZ(10) PWM_POLARITY_NORMAL>;
+	};
+
+	 /*
+	  * Declare unused GPIOs so that they are shut down
+	  * and use minimal power
+	  */
+	  unused-pins {
+		compatible = "unused-gpios";
+		unused-gpios =
+			<&gpio3 2 0>,
+			<&gpio3 5 0>,
+			<&gpio3 6 0>,
+			<&gpio5 7 0>,
+			<&gpio6 0 0>,
+			<&gpio6 3 0>,
+			<&gpio6 6 0>,
+			<&gpio7 3 0>,
+			<&gpio8 3 0>,
+			<&gpio8 6 0>,
+			<&gpiob 1 0>,
+			<&gpiob 7 0>,
+			<&gpioc 7 0>,
+			<&gpiof 2 0>,
+			<&gpiof 3 0>;
+	 };
+};
+
+&thermistor_3V3_51K1_47K_4050B {
+	status = "okay";
+};
+
+&adc_ec_vsense_pp3300_s5 {
+	/*
+	 * Voltage divider on input has 47k upper and 220k lower legs with
+	 * 2714 mV full-scale reading on the ADC. Apply the largest possible
+	 * multiplier (without overflowing int32) to get the best possible
+	 * approximation of the actual ratio, but derate by a factor of two to
+	 * ensure unexpectedly high values won't overflow.
+	 */
+	mul = <(791261 / 2)>;
+	div = <(651975 / 2)>;
+};
+
+/* Set bus speeds for I2C */
+&i2c0_0 {
+	label = "I2C_EEPROM";
+	clock-frequency = <I2C_BITRATE_FAST>;
+
+	cbi_eeprom: eeprom@50 {
+		compatible = "atmel,at24";
+		reg = <0x50>;
+		size = <2048>;
+		pagesize = <16>;
+		address-width = <8>;
+		timeout = <5>;
+	};
+};
+
+&i2c1_0 {
+	label = "I2C_SENSOR";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&i2c3_0 {
+	label = "I2C_USB_C0_TCPC";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+
+	bc12_port0: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+		/*
+		 * BC1.2 interrupt is shared with TCPC, so
+		 * IRQ is not specified here and handled by
+		 * usb_c0_interrupt.
+		 */
+	};
+
+	chg_port0: isl923x@9 {
+		compatible = "intersil,isl923x";
+		status = "okay";
+		reg = <0x9>;
+	};
+
+	tcpc_port0: raa489000@22 {
+		compatible = "renesas,raa489000";
+		reg = <0x22>;
+		tcpc-flags = <(
+			TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_VBUS_MONITOR)>;
+	};
+};
+
+&i2c5_1 {
+	label = "I2C_SUB_C1_TCPC";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+
+	bc12_port1: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+	};
+
+	chg_port1: isl923x@9 {
+		compatible = "intersil,isl923x";
+		status = "okay";
+		reg = <0x9>;
+	};
+
+	tcpc_port1: raa489000@22 {
+		compatible = "renesas,raa489000";
+		reg = <0x22>;
+		tcpc-flags = <(
+			TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_VBUS_MONITOR)>;
+	};
+
+	anx7483_mux_1: anx7483-mux-1@3e {
+		compatible = "analogix,anx7483";
+		reg = <0x3e>;
+		board-set = "anx7483_set_default_tuning";
+		flags = <USB_MUX_FLAG_RESETS_IN_G3>;
+	};
+};
+
+&i2c7_0 {
+	label = "I2C_BATTERY";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+};
+
+&pwm6 {
+	status = "okay";
+	pinctrl-0 = <&pwm6_gpc0>;
+	pinctrl-names = "default";
+};
+
+/* host interface */
+&espi0 {
+	status = "okay";
+	pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>;
+	pinctrl-names = "default";
+};
+
+/*
+ * Declare GPIOs that have leakage current caused by board issues here. NPCX ec
+ * will disable their input buffers before entering deep sleep and restore them
+ * after waking up automatically for better power consumption.
+ */
+&power_leakage_io {
+	leak-gpios = <&gpioa 4 GPIO_OPEN_DRAIN
+		      &gpiof 1 GPIO_OPEN_DRAIN>;
+};
diff --git a/zephyr/program/nissa/craask/power_signals.dtsi b/zephyr/program/nissa/craask/power_signals.dtsi
new file mode 100644
index 0000000000..1d2b23069d
--- /dev/null
+++ b/zephyr/program/nissa/craask/power_signals.dtsi
@@ -0,0 +1,220 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	chosen {
+		intel-ap-pwrseq,espi = &espi0;
+	};
+
+	common-pwrseq {
+		compatible = "intel,ap-pwrseq";
+
+		sys-pwrok-delay = <10>;
+		all-sys-pwrgd-timeout = <20>;
+	};
+
+	pwr-en-pp5000-s5 {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PP5000_S5 enable output to regulator";
+		enum-name = "PWR_EN_PP5000_A";
+		gpios = <&gpio4 0 0>;
+		output;
+	};
+	pwr-en-pp3300-s5 {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PP3300_S5 enable output to LS";
+		enum-name = "PWR_EN_PP3300_A";
+		gpios = <&gpiob 6 0>;
+		output;
+	};
+	pwr-pg-ec-rsmrst-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST power good from regulator";
+		enum-name = "PWR_RSMRST";
+		gpios = <&gpio9 4 0>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-ec-pch-rsmrst-odl {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST output to PCH";
+		enum-name = "PWR_EC_PCH_RSMRST";
+		gpios = <&gpioa 6 0>;
+		output;
+	};
+	pwr-slp-s0-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_S0_L input from PCH";
+		enum-name = "PWR_SLP_S0";
+		gpios = <&gpio9 7 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-slp-s3-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_S3_L input from PCH";
+		enum-name = "PWR_SLP_S3";
+		gpios = <&gpioa 5 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-slp-sus-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_SUS_L input from PCH";
+		enum-name = "PWR_SLP_SUS";
+		gpios = <&gpio6 2 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-ec-soc-dsw-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "DSW_PWROK output to PCH";
+		enum-name = "PWR_EC_SOC_DSW_PWROK";
+		gpios = <&gpio6 1 0>;
+		output;
+	};
+	pwr-vccst-pwrgd-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "VCCST_PWRGD output to PCH";
+		enum-name = "PWR_VCCST_PWRGD";
+		gpios = <&gpioa 4 GPIO_OPEN_DRAIN>;
+		output;
+	};
+	pwr-imvp9-vrrdy-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "VRRDY input from IMVP9";
+		enum-name = "PWR_IMVP9_VRRDY";
+		gpios = <&gpio4 3 0>;
+	};
+	pwr-pch-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PCH_PWROK output to PCH";
+		enum-name = "PWR_PCH_PWROK";
+		gpios = <&gpio7 2 GPIO_OPEN_DRAIN>;
+		output;
+	};
+	pwr-ec-pch-sys-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_PWROK output to PCH";
+		enum-name = "PWR_EC_PCH_SYS_PWROK";
+		gpios = <&gpio3 7 0>;
+		output;
+	};
+	pwr-sys-rst-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_RESET# output to PCH";
+		enum-name = "PWR_SYS_RST";
+		gpios = <&gpioc 5 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>;
+		output;
+	};
+	pwr-slp-s4 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S4 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S4";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4";
+		vw-invert;
+	};
+	pwr-slp-s5 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S5 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S5";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5";
+		vw-invert;
+	};
+	pwr-all-sys-pwrgd {
+		compatible = "intel,ap-pwrseq-external";
+		dbg-label = "Combined all power good";
+		enum-name = "PWR_ALL_SYS_PWRGD";
+	};
+	pwr-adc-pp3300 {
+		compatible = "intel,ap-pwrseq-adc";
+		dbg-label = "PP3300 PWROK (from ADC)";
+		enum-name = "PWR_DSW_PWROK";
+		trigger-high = <&cmp_pp3300_s5_high>;
+		trigger-low = <&cmp_pp3300_s5_low>;
+	};
+	pwr-adc-pp1p05 {
+		compatible = "intel,ap-pwrseq-adc";
+		dbg-label = "PP1P05 PWROK (from ADC)";
+		enum-name = "PWR_PG_PP1P05";
+		trigger-high = <&cmp_pp1p05_high>;
+		trigger-low = <&cmp_pp1p05_low>;
+	};
+
+	adc-cmp {
+		cmp_pp3300_s5_high: pp3300_high {
+			compatible = "nuvoton,adc-cmp";
+			io-channels = <&adc0 6>;
+			comparison = "ADC_CMP_NPCX_GREATER";
+			/*
+			 * This is 90% of nominal voltage considering voltage
+			 * divider on ADC input.
+			 */
+			threshold-mv = <2448>;
+		};
+		cmp_pp3300_s5_low: pp3300_low {
+			compatible = "nuvoton,adc-cmp";
+			io-channels = <&adc0 6>;
+			comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL";
+			threshold-mv = <2448>;
+		};
+		cmp_pp1p05_high: pp1p05_high {
+			compatible = "nuvoton,adc-cmp";
+			io-channels = <&adc0 4>;
+			comparison = "ADC_CMP_NPCX_GREATER";
+			/* Setting at 90% of nominal voltage */
+			threshold-mv = <945>;
+		};
+		cmp_pp1p05_low: pp1p05_low {
+			compatible = "nuvoton,adc-cmp";
+			io-channels = <&adc0 4>;
+			comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL";
+			threshold-mv = <945>;
+		};
+	};
+};
+
+/*
+ * Because the power signals directly reference the GPIOs,
+ * the correspinding named-gpios need to have no-auto-init set.
+ */
+&gpio_ec_soc_dsw_pwrok {
+	no-auto-init;
+};
+&gpio_ec_soc_pch_pwrok_od {
+	no-auto-init;
+};
+&gpio_ec_soc_rsmrst_l {
+	no-auto-init;
+};
+&gpio_ec_soc_sys_pwrok {
+	no-auto-init;
+};
+&gpio_ec_soc_vccst_pwrgd_od {
+	no-auto-init;
+};
+&gpio_en_pp3300_s5 {
+	no-auto-init;
+};
+&gpio_en_pp5000_s5 {
+	no-auto-init;
+};
+&gpio_imvp91_vrrdy_od {
+	no-auto-init;
+};
+&gpio_rsmrst_pwrgd_l {
+	no-auto-init;
+};
+&gpio_slp_s0_l {
+	no-auto-init;
+};
+&gpio_slp_s3_l {
+	no-auto-init;
+};
+&gpio_slp_s4_l {
+	no-auto-init;
+};
+&gpio_slp_sus_l {
+	no-auto-init;
+};
+&gpio_sys_rst_odl {
+	no-auto-init;
+};
diff --git a/zephyr/program/nissa/craask/project.conf b/zephyr/program/nissa/craask/project.conf
new file mode 100644
index 0000000000..7bcc64e6a5
--- /dev/null
+++ b/zephyr/program/nissa/craask/project.conf
@@ -0,0 +1,38 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_BOARD_CRAASK=y
+CONFIG_PLATFORM_EC_OCPC=y
+
+# Sensor drivers
+CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSO=y
+CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y
+CONFIG_PLATFORM_EC_DYNAMIC_MOTION_SENSOR_COUNT=y
+
+CONFIG_PLATFORM_EC_BUTTONS_RUNTIME_CONFIG=y
+
+# Increase PD max power from default
+CONFIG_PLATFORM_EC_PD_MAX_POWER_MW=65000
+CONFIG_PLATFORM_EC_PD_MAX_VOLTAGE_MV=20000
+CONFIG_PLATFORM_EC_PD_MAX_CURRENT_MA=3250
+
+# Flash space saving
+# Turning off extended console help saves ~3500 bytes
+CONFIG_SHELL_HELP=n
+
+# Keyboard
+CONFIG_PLATFORM_EC_KEYBOARD_KEYPAD=y
+CONFIG_PLATFORM_EC_KEYBOARD_FACTORY_TEST=y
+
+# Both ports use a SLGC55545 smart switch with CTL1..3 fixed high,
+# for SDP2 or CDP only.
+CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART=y
+CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_CDP_SDP_ONLY=y
+CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_DEFAULT_CDP=y
+CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_INVERTED=y
+
+# Fan
+CONFIG_PLATFORM_EC_CUSTOM_FAN_CONTROL=y
diff --git a/zephyr/program/nissa/craask/project.overlay b/zephyr/program/nissa/craask/project.overlay
new file mode 100644
index 0000000000..6107b6ef15
--- /dev/null
+++ b/zephyr/program/nissa/craask/project.overlay
@@ -0,0 +1,15 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "../cbi.dtsi"
+
+#include "cbi.dtsi"
+#include "fan.dtsi"
+#include "generated.dtsi"
+#include "keyboard.dtsi"
+#include "motionsense.dtsi"
+#include "overlay.dtsi"
+#include "power_signals.dtsi"
+#include "pwm_leds.dtsi"
diff --git a/zephyr/program/nissa/craask/pwm_leds.dtsi b/zephyr/program/nissa/craask/pwm_leds.dtsi
new file mode 100644
index 0000000000..0a3c2a3400
--- /dev/null
+++ b/zephyr/program/nissa/craask/pwm_leds.dtsi
@@ -0,0 +1,62 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	pwmleds {
+		compatible = "pwm-leds";
+		pwm_led0: pwm_led_0 {
+			pwms = <&pwm2 2 PWM_HZ(324) PWM_POLARITY_INVERTED>,
+			       <&pwm0 0 PWM_HZ(324) PWM_POLARITY_INVERTED>,
+			       <&pwm1 1 PWM_HZ(324) PWM_POLARITY_INVERTED>;
+		};
+	};
+
+	cros-pwmleds {
+		compatible = "cros-ec,pwm-leds";
+
+		leds = <&pwm_led0>;
+
+				/*<red green blue>*/
+		color-map-red    = <100   0    0>;
+		color-map-green  = <  0 100    0>;
+		color-map-blue   = <  0   0  100>;
+		color-map-yellow = <  0  50   50>;
+		color-map-white  = <100 100  100>;
+		color-map-amber  = < 90  10    0>;
+
+		brightness-range = <100 100 100 0 0 100>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pwm_led_0@0 {
+			reg = <0>;
+			ec-led-name = "EC_LED_ID_BATTERY_LED";
+		};
+	};
+};
+
+/* Enable LEDs to work while CPU suspended */
+
+&pwm0 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm0_gpc3>;
+	pinctrl-names = "default";
+};
+
+&pwm1 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm1_gpc2>;
+	pinctrl-names = "default";
+};
+
+&pwm2 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm2_gpc4>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/nissa/craask/src/charger.c b/zephyr/program/nissa/craask/src/charger.c
new file mode 100644
index 0000000000..01e849a881
--- /dev/null
+++ b/zephyr/program/nissa/craask/src/charger.c
@@ -0,0 +1,71 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "battery_fuel_gauge.h"
+#include "charge_manager.h"
+#include "charger.h"
+#include "charger/isl923x_public.h"
+#include "console.h"
+#include "extpower.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+int extpower_is_present(void)
+{
+	int port;
+	int rv;
+	bool acok;
+
+	for (port = 0; port < board_get_usb_pd_port_count(); port++) {
+		rv = raa489000_is_acok(port, &acok);
+		if ((rv == EC_SUCCESS) && acok)
+			return 1;
+	}
+
+	return 0;
+}
+
+/*
+ * Craask does not have a GPIO indicating whether extpower is present,
+ * so detect using the charger(s).
+ */
+__override void board_check_extpower(void)
+{
+	static int last_extpower_present;
+	int extpower_present = extpower_is_present();
+
+	if (last_extpower_present ^ extpower_present)
+		extpower_handle_update(extpower_present);
+
+	last_extpower_present = extpower_present;
+}
+
+__override void board_hibernate(void)
+{
+	/* Shut down the chargers */
+	if (board_get_usb_pd_port_count() == 2)
+		raa489000_hibernate(CHARGER_SECONDARY, true);
+	raa489000_hibernate(CHARGER_PRIMARY, true);
+	LOG_INF("Charger(s) hibernated");
+	cflush();
+}
+
+__override int board_get_leave_safe_mode_delay_ms(void)
+{
+	const struct fuel_gauge_info *const fuel_gauge =
+		&get_batt_params()->fuel_gauge;
+
+	/* If it's COSMX battery, there's need more delay time. */
+	if (!strcasecmp(fuel_gauge->manuf_name, "COSMX KT0030B002") ||
+	    !strcasecmp(fuel_gauge->manuf_name, "COSMX KT0030B004"))
+		return 2000;
+	else
+		return 500;
+}
diff --git a/zephyr/program/nissa/craask/src/fan.c b/zephyr/program/nissa/craask/src/fan.c
new file mode 100644
index 0000000000..07517abbe9
--- /dev/null
+++ b/zephyr/program/nissa/craask/src/fan.c
@@ -0,0 +1,36 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "cros_cbi.h"
+#include "fan.h"
+#include "gpio/gpio.h"
+#include "hooks.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/logging/log.h>
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+static void fan_init(void)
+{
+	int ret;
+	uint32_t val;
+	/*
+	 * Retrieve the fan config.
+	 */
+	ret = cros_cbi_get_fw_config(FW_FAN, &val);
+	if (ret != 0) {
+		LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_FAN);
+		return;
+	}
+	if (val != FW_FAN_PRESENT) {
+		/* Disable the fan */
+		fan_set_count(0);
+	} else {
+		/* Configure the fan enable GPIO */
+		gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_fan_enable),
+				      GPIO_OUTPUT);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, fan_init, HOOK_PRIO_POST_FIRST);
diff --git a/zephyr/program/nissa/craask/src/form_factor.c b/zephyr/program/nissa/craask/src/form_factor.c
new file mode 100644
index 0000000000..4592676a7d
--- /dev/null
+++ b/zephyr/program/nissa/craask/src/form_factor.c
@@ -0,0 +1,133 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "accelgyro.h"
+#include "button.h"
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+#include "driver/accel_bma4xx.h"
+#include "driver/accel_lis2dw12_public.h"
+#include "driver/accelgyro_bmi323.h"
+#include "driver/accelgyro_lsm6dso.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "motion_sense.h"
+#include "motionsense_sensors.h"
+#include "nissa_sub_board.h"
+#include "tablet_mode.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+/*
+ * Mainboard orientation support.
+ */
+
+#define LIS_ALT_MAT SENSOR_ROT_STD_REF_NAME(DT_NODELABEL(lid_rot_bma422))
+#define BMA_ALT_MAT SENSOR_ROT_STD_REF_NAME(DT_NODELABEL(lid_rot_ref))
+#define ALT_MAT SENSOR_ROT_STD_REF_NAME(DT_NODELABEL(base_rot_ver1))
+#define LID_SENSOR SENSOR_ID(DT_NODELABEL(lid_accel))
+#define BASE_SENSOR SENSOR_ID(DT_NODELABEL(base_accel))
+#define BASE_GYRO SENSOR_ID(DT_NODELABEL(base_gyro))
+#define ALT_LID_S SENSOR_ID(DT_NODELABEL(alt_lid_accel))
+
+static bool use_alt_sensor;
+static bool use_alt_lid_accel;
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	if (use_alt_sensor)
+		bmi3xx_interrupt(signal);
+	else
+		lsm6dso_interrupt(signal);
+}
+
+void lid_accel_interrupt(enum gpio_signal signal)
+{
+	if (use_alt_lid_accel)
+		bma4xx_interrupt(signal);
+	else
+		lis2dw12_interrupt(signal);
+}
+
+static void form_factor_init(void)
+{
+	int ret;
+	uint32_t val;
+	enum nissa_sub_board_type sb = nissa_get_sb_type();
+
+	ret = cbi_get_board_version(&val);
+	if (ret != EC_SUCCESS) {
+		LOG_ERR("Error retrieving CBI BOARD_VER.");
+		return;
+	}
+	/*
+	 * The volume up/down button are exchanged on ver3 USB
+	 * sub board.
+	 *
+	 * LTE:
+	 *   volup -> gpioa2, voldn -> gpio93
+	 * USB:
+	 *   volup -> gpio93, voldn -> gpioa2
+	 */
+	if (val == 3 && sb == NISSA_SB_C_A) {
+		LOG_INF("Volume up/down btn exchanged on ver3 USB sku");
+		buttons[BUTTON_VOLUME_UP].gpio = GPIO_VOLUME_DOWN_L;
+		buttons[BUTTON_VOLUME_DOWN].gpio = GPIO_VOLUME_UP_L;
+	}
+
+	/*
+	 * If the board version is 1
+	 * use ver1 rotation matrix.
+	 */
+	if (val == 1) {
+		LOG_INF("Switching to ver1 base");
+		motion_sensors[BASE_SENSOR].rot_standard_ref = &ALT_MAT;
+		motion_sensors[BASE_GYRO].rot_standard_ref = &ALT_MAT;
+	}
+
+	/*
+	 * If the firmware config indicates
+	 * an craaskbowl form factor, use the alternative
+	 * rotation matrix.
+	 */
+	ret = cros_cbi_get_fw_config(FW_LID_INVERSION, &val);
+	if (ret != 0) {
+		LOG_ERR("Error retrieving CBI FW_CONFIG field %d",
+			FW_LID_INVERSION);
+		return;
+	}
+	if (val == FW_LID_XY_ROT_180) {
+		LOG_INF("Lid sensor placement rotate 180 on xy plane");
+		motion_sensors[LID_SENSOR].rot_standard_ref = &LIS_ALT_MAT;
+		motion_sensors_alt[ALT_LID_S].rot_standard_ref = &BMA_ALT_MAT;
+	}
+
+	/* check which motion sensors are used */
+	use_alt_sensor = cros_cbi_ssfc_check_match(
+		CBI_SSFC_VALUE_ID(DT_NODELABEL(base_sensor_1)));
+	use_alt_lid_accel = cros_cbi_ssfc_check_match(
+		CBI_SSFC_VALUE_ID(DT_NODELABEL(lid_sensor_1)));
+
+	motion_sensors_check_ssfc();
+
+	/* Check if it's clamshell or convertible */
+	ret = cros_cbi_get_fw_config(FORM_FACTOR, &val);
+	if (ret != 0) {
+		LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FORM_FACTOR);
+		return;
+	}
+	if (val == CLAMSHELL) {
+		LOG_INF("Clamshell: disable motionsense function.");
+		motion_sensor_count = 0;
+		gmr_tablet_switch_disable();
+		gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_imu));
+		gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_imu_int_l),
+				      GPIO_DISCONNECTED);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, form_factor_init, HOOK_PRIO_POST_I2C);
diff --git a/zephyr/program/nissa/craask/src/kb_backlight.c b/zephyr/program/nissa/craask/src/kb_backlight.c
new file mode 100644
index 0000000000..108cbb3abd
--- /dev/null
+++ b/zephyr/program/nissa/craask/src/kb_backlight.c
@@ -0,0 +1,34 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "board_config.h"
+#include "common.h"
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+__override uint32_t board_override_feature_flags0(uint32_t flags0)
+{
+	int ret;
+	uint32_t val;
+
+	/*
+	 * Remove keyboard backlight feature for devices that don't support it.
+	 */
+	ret = cros_cbi_get_fw_config(FW_KB_BL, &val);
+	if (ret != 0) {
+		LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_KB_BL);
+		return flags0;
+	}
+
+	if (val == FW_KB_BL_NOT_PRESENT)
+		return (flags0 & ~EC_FEATURE_MASK_0(EC_FEATURE_PWM_KEYB));
+	else
+		return flags0;
+}
diff --git a/zephyr/program/nissa/craask/src/keyboard.c b/zephyr/program/nissa/craask/src/keyboard.c
new file mode 100644
index 0000000000..93e9950bcf
--- /dev/null
+++ b/zephyr/program/nissa/craask/src/keyboard.c
@@ -0,0 +1,102 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cros_cbi.h"
+#include "ec_commands.h"
+#include "hooks.h"
+#include "keyboard_raw.h"
+#include "keyboard_scan.h"
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+static bool key_pad = FW_KB_NUMERIC_PAD_ABSENT;
+static const struct ec_response_keybd_config craask_kb = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+static const struct ec_response_keybd_config craask_kb_w_kb_numpad = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY | KEYBD_CAP_NUMERIC_KEYPAD,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	if (key_pad == FW_KB_NUMERIC_PAD_ABSENT)
+		return &craask_kb;
+	else
+		return &craask_kb_w_kb_numpad;
+}
+
+/*
+ * Keyboard function decided by FW config.
+ */
+static void kb_init(void)
+{
+	int ret;
+	uint32_t val;
+
+	ret = cros_cbi_get_fw_config(FW_KB_NUMERIC_PAD, &val);
+
+	if (ret != 0) {
+		LOG_ERR("Error retrieving CBI FW_CONFIG field %d",
+			FW_KB_NUMERIC_PAD);
+	}
+
+	if (val == FW_KB_NUMERIC_PAD_ABSENT) {
+		/* Disable scanning KSO13 & 14 if keypad isn't present. */
+		keyboard_raw_set_cols(KEYBOARD_COLS_NO_KEYPAD);
+		key_pad = FW_KB_NUMERIC_PAD_ABSENT;
+	} else {
+		key_pad = FW_KB_NUMERIC_PAD_PRESENT;
+		/* Setting scan mask KSO11, KSO12, KSO13 and KSO14 */
+		keyscan_config.actual_key_mask[11] = 0xfe;
+		keyscan_config.actual_key_mask[12] = 0xff;
+		keyscan_config.actual_key_mask[13] = 0xff;
+		keyscan_config.actual_key_mask[14] = 0xff;
+	}
+}
+DECLARE_HOOK(HOOK_INIT, kb_init, HOOK_PRIO_POST_FIRST);
+
+/*
+ * We have total 30 pins for keyboard connecter {-1, -1} mean
+ * the N/A pin that don't consider it and reserve index 0 area
+ * that we don't have pin 0.
+ */
+const int keyboard_factory_scan_pins[][2] = {
+	{ -1, -1 }, { 0, 5 },	{ 1, 1 }, { 1, 0 },   { 0, 6 },	  { 0, 7 },
+	{ -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 },   { -1, -1 }, { 1, 6 },
+	{ 1, 7 },   { 3, 1 },	{ 2, 0 }, { 1, 5 },   { 2, 6 },	  { 2, 7 },
+	{ 2, 1 },   { 2, 4 },	{ 2, 5 }, { 1, 2 },   { 2, 3 },	  { 2, 2 },
+	{ 3, 0 },   { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 },	  { -1, -1 },
+	{ -1, -1 },
+};
+const int keyboard_factory_scan_pins_used =
+	ARRAY_SIZE(keyboard_factory_scan_pins);
diff --git a/zephyr/program/nissa/craask/src/led.c b/zephyr/program/nissa/craask/src/led.c
new file mode 100644
index 0000000000..b3aefa3ab2
--- /dev/null
+++ b/zephyr/program/nissa/craask/src/led.c
@@ -0,0 +1,56 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery LED control for nissa
+ */
+#include "common.h"
+#include "ec_commands.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+#include "led_pwm.h"
+
+__override const int led_charge_lvl_1 = 5;
+__override const int led_charge_lvl_2 = 97;
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_BLUE,
+					   2 * LED_ONE_SEC } },
+	};
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_RED:
+		set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_RED);
+		break;
+	case EC_LED_COLOR_BLUE:
+		set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_BLUE);
+		break;
+	case EC_LED_COLOR_AMBER:
+		set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_AMBER);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		set_pwm_led_color(EC_LED_ID_BATTERY_LED, -1);
+		break;
+	}
+}
diff --git a/zephyr/program/nissa/craask/src/thermal.c b/zephyr/program/nissa/craask/src/thermal.c
new file mode 100644
index 0000000000..e2ab21a9db
--- /dev/null
+++ b/zephyr/program/nissa/craask/src/thermal.c
@@ -0,0 +1,140 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "chipset.h"
+#include "common.h"
+#include "cros_cbi.h"
+#include "fan.h"
+#include "hooks.h"
+#include "temp_sensor/temp_sensor.h"
+#include "thermal.h"
+#include "util.h"
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+#define THERMAL_SOLUTION_COUNT 1
+#define TEMP_MEMORY TEMP_SENSOR_ID(DT_NODELABEL(temp_memory))
+BUILD_ASSERT(TEMP_MEMORY == 0 || TEMP_MEMORY <= THERMAL_SOLUTION_COUNT);
+
+struct fan_step {
+	/*
+	 * The only sensor temp_memory trigger point
+	 */
+	int8_t on[THERMAL_SOLUTION_COUNT];
+	/*
+	 * The only sensor temp_memory trigger point
+	 */
+	int8_t off[THERMAL_SOLUTION_COUNT];
+	/* Fan rpm */
+	uint16_t rpm[FAN_CH_COUNT];
+};
+
+#define FAN_TABLE_ENTRY(nd)                     \
+	{                                       \
+		.on = DT_PROP(nd, temp_on),     \
+		.off = DT_PROP(nd, temp_off),   \
+		.rpm = DT_PROP(nd, rpm_target), \
+	},
+
+static const struct fan_step fan_step_table_6w[] = { DT_FOREACH_CHILD(
+	DT_NODELABEL(fan_steps_6w), FAN_TABLE_ENTRY) };
+static const struct fan_step fan_step_table_15w[] = { DT_FOREACH_CHILD(
+	DT_NODELABEL(fan_steps_15w), FAN_TABLE_ENTRY) };
+
+static uint8_t thermal_solution;
+
+int fan_table_to_rpm(int fan, int *temp)
+{
+	const struct fan_step *fan_step_table;
+	/* current fan level */
+	static int current_level;
+	/* previous sensor temperature */
+	static int prev_tmp[THERMAL_SOLUTION_COUNT];
+
+	int i;
+	uint8_t fan_table_size;
+
+	/*
+	 * thermal table decides the FW_THERMAL flag of fw_config
+	 * unset (0): 6W, 1: 6W, 2: 15W table
+	 */
+	if (thermal_solution == FW_THERMAL_15W) {
+		fan_step_table = fan_step_table_15w;
+		fan_table_size = ARRAY_SIZE(fan_step_table_15w);
+	} else {
+		fan_step_table = fan_step_table_6w;
+		fan_table_size = ARRAY_SIZE(fan_step_table_6w);
+	}
+
+	/*
+	 * Compare the current and previous temperature, we have
+	 * the three paths :
+	 *  1. decreasing path. (check the release point)
+	 *  2. increasing path. (check the trigger point)
+	 *  3. invariant path. (return the current RPM)
+	 */
+
+	if (temp[TEMP_MEMORY] < prev_tmp[TEMP_MEMORY]) {
+		for (i = current_level; i > 0; i--) {
+			if (temp[TEMP_MEMORY] <=
+			    fan_step_table[i].off[TEMP_MEMORY])
+				current_level = i - 1;
+			else
+				break;
+		}
+	} else if (temp[TEMP_MEMORY] > prev_tmp[TEMP_MEMORY]) {
+		for (i = current_level; i < fan_table_size; i++) {
+			if (temp[TEMP_MEMORY] >=
+			    fan_step_table[i].on[TEMP_MEMORY])
+				current_level = i;
+			else
+				break;
+		}
+	}
+
+	if (current_level < 0)
+		current_level = 0;
+
+	if (current_level >= fan_table_size)
+		current_level = fan_table_size - 1;
+
+	prev_tmp[TEMP_MEMORY] = temp[TEMP_MEMORY];
+
+	return fan_step_table[current_level].rpm[fan];
+}
+
+void board_override_fan_control(int fan, int *temp)
+{
+	/*
+	 * In common/fan.c pwm_fan_stop() will turn off fan
+	 * when chipset suspend or shutdown.
+	 */
+	if (chipset_in_state(CHIPSET_STATE_ON)) {
+		fan_set_rpm_mode(fan, 1);
+		fan_set_rpm_target(fan, fan_table_to_rpm(fan, temp));
+	} else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
+		/* Stop fan when enter S0ix */
+		fan_set_rpm_mode(fan, 1);
+		fan_set_rpm_target(fan, 0);
+	}
+}
+
+static void thermal_init(void)
+{
+	int ret;
+	uint32_t val;
+	/*
+	 * Retrieve the fan config.
+	 */
+	ret = cros_cbi_get_fw_config(FW_THERMAL, &val);
+	if (ret != 0) {
+		LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_THERMAL);
+		return;
+	}
+
+	thermal_solution = val;
+}
+DECLARE_HOOK(HOOK_INIT, thermal_init, HOOK_PRIO_POST_FIRST);
diff --git a/zephyr/program/nissa/craask/src/usbc.c b/zephyr/program/nissa/craask/src/usbc.c
new file mode 100644
index 0000000000..5df3a09bb8
--- /dev/null
+++ b/zephyr/program/nissa/craask/src/usbc.c
@@ -0,0 +1,228 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_state.h"
+#include "chipset.h"
+#include "driver/charger/isl923x_public.h"
+#include "driver/retimer/anx7483_public.h"
+#include "driver/tcpm/raa489000.h"
+#include "driver/tcpm/tcpci.h"
+#include "hooks.h"
+#include "system.h"
+#include "usb_mux.h"
+
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+int board_is_sourcing_vbus(int port)
+{
+	int regval;
+
+	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
+	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int i;
+	int old_port;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	old_port = charge_manager_get_active_charge_port();
+
+	LOG_INF("New chg p%d", port);
+
+	/* Disable all ports. */
+	if (port == CHARGE_PORT_NONE) {
+		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+			tcpc_write(i, TCPC_REG_COMMAND,
+				   TCPC_REG_COMMAND_SNK_CTRL_LOW);
+			raa489000_enable_asgate(i, false);
+		}
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if port is sourcing VBUS. */
+	if (board_is_sourcing_vbus(port)) {
+		LOG_WRN("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		if (i == port)
+			continue;
+
+		if (tcpc_write(i, TCPC_REG_COMMAND,
+			       TCPC_REG_COMMAND_SNK_CTRL_LOW))
+			LOG_WRN("p%d: sink path disable failed.", i);
+		raa489000_enable_asgate(i, false);
+	}
+
+	/*
+	 * Stop the charger IC from switching while changing ports.  Otherwise,
+	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
+	 */
+	if (old_port != CHARGE_PORT_NONE)
+		charger_discharge_on_ac(1);
+
+	/* Enable requested charge port. */
+	if (raa489000_enable_asgate(port, true) ||
+	    tcpc_write(port, TCPC_REG_COMMAND,
+		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
+		LOG_WRN("p%d: sink path enable failed.", port);
+		charger_discharge_on_ac(0);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	/* Allow the charger IC to begin/continue switching. */
+	charger_discharge_on_ac(0);
+
+	return EC_SUCCESS;
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+	int regval;
+
+	/*
+	 * The interrupt line is shared between the TCPC and BC1.2 detector IC.
+	 * Therefore, go out and actually read the alert registers to report the
+	 * alert status.
+	 */
+	if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl))) {
+		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
+			/* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */
+			if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0))
+				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
+
+			if (regval)
+				status |= PD_STATUS_TCPC_ALERT_0;
+		}
+	}
+
+	if (board_get_usb_pd_port_count() == 2 &&
+	    !gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) {
+		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
+			/* TCPCI spec Rev 1.0 says to ignore bits 14:12. */
+			if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0))
+				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
+
+			if (regval)
+				status |= PD_STATUS_TCPC_ALERT_1;
+		}
+	}
+
+	return status;
+}
+
+void pd_power_supply_reset(int port)
+{
+	/* Disable VBUS */
+	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	if (port < 0 || port >= CONFIG_USB_PD_PORT_MAX_COUNT)
+		return;
+
+	raa489000_set_output_current(port, rp);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	if (port >= CONFIG_USB_PD_PORT_MAX_COUNT)
+		return EC_ERROR_INVAL;
+
+	/* Disable charging. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
+	if (rv)
+		return rv;
+
+	/* Our policy is not to source VBUS when the AP is off. */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	/* Provide Vbus. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
+	if (rv)
+		return rv;
+
+	rv = raa489000_enable_asgate(port, true);
+	if (rv)
+		return rv;
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * TODO(b:147316511): could send a reset command to the TCPC here
+	 * if needed.
+	 */
+}
+
+/*
+ * Because the TCPCs and BC1.2 chips share interrupt lines, it's possible
+ * for an interrupt to be lost if one asserts the IRQ, the other does the same
+ * then the first releases it: there will only be one falling edge to trigger
+ * the interrupt, and the line will be held low. We handle this by polling the
+ * IRQ GPIO on the USB-PD task after processing TCPC interrupts, synchronously
+ * running the BC1.2 interrupt handler to ensure we continue processing
+ * interrupts as long as either source is asserting the IRQ.
+ */
+void board_process_pd_alert(int port)
+{
+	const struct gpio_dt_spec *gpio;
+
+	if (port == 0) {
+		gpio = GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl);
+	} else {
+		gpio = GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl);
+	}
+
+	if (!gpio_pin_get_dt(gpio)) {
+		usb_charger_task_set_event_sync(port, USB_CHG_EVENT_BC12);
+	}
+
+	/*
+	 * Immediately schedule another TCPC interrupt if it seems we haven't
+	 * cleared all pending interrupts.
+	 */
+	if (!gpio_pin_get_dt(gpio))
+		schedule_deferred_pd_interrupt(port);
+}
+
+void usb_interrupt(enum gpio_signal signal)
+{
+	int port;
+
+	if (signal == GPIO_SIGNAL(DT_NODELABEL(gpio_usb_c0_int_odl))) {
+		port = 0;
+	} else {
+		port = 1;
+	}
+	/* Trigger polling of TCPC and BC1.2 in USB-PD task */
+	schedule_deferred_pd_interrupt(port);
+}
diff --git a/zephyr/program/nissa/gothrax/generated.dtsi b/zephyr/program/nissa/gothrax/generated.dtsi
new file mode 100644
index 0000000000..bca58c478e
--- /dev/null
+++ b/zephyr/program/nissa/gothrax/generated.dtsi
@@ -0,0 +1,260 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * This file is auto-generated - do not edit!
+ */
+
+/ {
+
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc {
+			enum-name = "ADC_PP1050_PROC";
+			io-channels = <&adc0 14>;
+		};
+		adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 {
+			enum-name = "ADC_PP3300_S5";
+			io-channels = <&adc0 0>;
+		};
+		adc_temp_sensor_1: temp_sensor_1 {
+			enum-name = "ADC_TEMP_SENSOR_1";
+			io-channels = <&adc0 2>;
+		};
+		adc_temp_sensor_2: temp_sensor_2 {
+			enum-name = "ADC_TEMP_SENSOR_2";
+			io-channels = <&adc0 3>;
+		};
+		adc_temp_sensor_3: temp_sensor_3 {
+			enum-name = "ADC_TEMP_SENSOR_3";
+			io-channels = <&adc0 13>;
+		};
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		gpio_acc_int_l: acc_int_l {
+			gpios = <&gpioc 0 GPIO_INPUT>;
+		};
+		gpio_all_sys_pwrgd: all_sys_pwrgd {
+			gpios = <&gpiob 7 GPIO_INPUT>;
+		};
+		gpio_ccd_mode_odl: ccd_mode_odl {
+			gpios = <&gpioh 5 GPIO_INPUT>;
+			enum-name = "GPIO_CCD_MODE_ODL";
+		};
+		gpio_cpu_c10_gate_l: cpu_c10_gate_l {
+			gpios = <&gpiog 1 GPIO_INPUT>;
+		};
+		gpio_ec_battery_pres_odl: ec_battery_pres_odl {
+			gpios = <&gpioi 4 GPIO_INPUT>;
+			enum-name = "GPIO_BATT_PRES_ODL";
+		};
+		gpio_ec_cbi_wp: ec_cbi_wp {
+			gpios = <&gpioj 5 GPIO_OUTPUT>;
+		};
+		gpio_ec_edp_bl_en_od: ec_edp_bl_en_od {
+			gpios = <&gpiok 4 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_ENABLE_BACKLIGHT";
+		};
+		gpio_ec_entering_rw: ec_entering_rw {
+			gpios = <&gpioc 7 GPIO_OUTPUT>;
+			enum-name = "GPIO_ENTERING_RW";
+		};
+		gpio_ec_gsc_packet_mode: ec_gsc_packet_mode {
+			gpios = <&gpioh 1 GPIO_OUTPUT>;
+			enum-name = "GPIO_PACKET_MODE_EN";
+		};
+		gpio_ec_pch_wake_odl: ec_pch_wake_odl {
+			gpios = <&gpiob 2 GPIO_ODR_LOW>;
+		};
+		gpio_ec_prochot_odl: ec_prochot_odl {
+			gpios = <&gpioi 1 GPIO_ODR_HIGH>;
+		};
+		gpio_ec_soc_dsw_pwrok: ec_soc_dsw_pwrok {
+			gpios = <&gpiol 7 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_hdmi_hpd: ec_soc_hdmi_hpd {
+			gpios = <&gpiok 7 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_int_odl: ec_soc_int_odl {
+			gpios = <&gpiod 5 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_EC_INT_L";
+		};
+		gpio_ec_soc_pch_pwrok_od: ec_soc_pch_pwrok_od {
+			gpios = <&gpiod 6 GPIO_ODR_HIGH>;
+		};
+		gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl {
+			gpios = <&gpiob 6 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_PCH_PWRBTN_L";
+		};
+		gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l {
+			gpios = <&gpioh 0 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_rtcrst: ec_soc_rtcrst {
+			gpios = <&gpiok 2 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_sys_pwrok: ec_soc_sys_pwrok {
+			gpios = <&gpiof 2 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_vccst_pwrgd_od: ec_soc_vccst_pwrgd_od {
+			gpios = <&gpioe 5 GPIO_ODR_HIGH>;
+		};
+		gpio_ec_wp_odl: ec_wp_odl {
+			gpios = <&gpioa 6 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_en_kb_bl: en_kb_bl {
+			gpios = <&gpioj 3 GPIO_OUTPUT>;
+			enum-name = "GPIO_EN_KEYBOARD_BACKLIGHT";
+		};
+		gpio_en_pp3300_s5: en_pp3300_s5 {
+			gpios = <&gpioc 5 GPIO_OUTPUT>;
+			enum-name = "GPIO_TEMP_SENSOR_POWER";
+		};
+		gpio_en_pp5000_pen_x: en_pp5000_pen_x {
+			gpios = <&gpiob 5 GPIO_OUTPUT>;
+		};
+		gpio_en_pp5000_s5: en_pp5000_s5 {
+			gpios = <&gpiok 5 GPIO_OUTPUT>;
+		};
+		gpio_en_slp_z: en_slp_z {
+			gpios = <&gpiok 3 GPIO_OUTPUT>;
+		};
+		gpio_en_usb_a0_vbus: en_usb_a0_vbus {
+			gpios = <&gpiol 6 GPIO_OUTPUT>;
+		};
+		gpio_en_usb_c0_cc1_vconn: en_usb_c0_cc1_vconn {
+			gpios = <&gpioh 4 GPIO_OUTPUT>;
+		};
+		gpio_en_usb_c0_cc2_vconn: en_usb_c0_cc2_vconn {
+			gpios = <&gpioh 6 GPIO_OUTPUT>;
+		};
+		gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl {
+			gpios = <&gpioe 2 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		gpio_hdmi_sel: hdmi_sel {
+			gpios = <&gpioc 6 GPIO_OUTPUT>;
+		};
+		gpio_imu_int_l: imu_int_l {
+			gpios = <&gpioj 0 GPIO_INPUT>;
+		};
+		gpio_imvp91_vrrdy_od: imvp91_vrrdy_od {
+			gpios = <&gpioj 4 GPIO_INPUT>;
+		};
+		gpio_lid_open: lid_open {
+			gpios = <&gpiof 3 GPIO_INPUT>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+		gpio_pen_detect_odl: pen_detect_odl {
+			gpios = <&gpioj 1 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_pg_pp1050_mem_s3_od: pg_pp1050_mem_s3_od {
+			gpios = <&gpiod 3 GPIO_INPUT>;
+		};
+		gpio_pg_pp5000_s5_od: pg_pp5000_s5_od {
+			gpios = <&gpioe 3 GPIO_INPUT>;
+		};
+		gpio_rsmrst_pwrgd_l: rsmrst_pwrgd_l {
+			gpios = <&gpioe 1 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_slp_s0_l: slp_s0_l {
+			gpios = <&gpioe 4 GPIO_INPUT>;
+		};
+		gpio_slp_s3_l: slp_s3_l {
+			gpios = <&gpioh 3 GPIO_INPUT>;
+		};
+		gpio_slp_s4_l: slp_s4_l {
+			gpios = <&gpioi 5 GPIO_INPUT>;
+		};
+		gpio_slp_sus_l: slp_sus_l {
+			gpios = <&gpiog 2 GPIO_INPUT>;
+		};
+		gpio_sub_usb_a1_ilimit_sdp: sub_usb_a1_ilimit_sdp {
+			gpios = <&gpiof 1 GPIO_OUTPUT>;
+			enum-name = "GPIO_USB2_ILIM_SEL";
+		};
+		gpio_sys_rst_odl: sys_rst_odl {
+			gpios = <&gpiod 1 GPIO_ODR_HIGH>;
+		};
+		gpio_tablet_mode_l: tablet_mode_l {
+			gpios = <&gpioa 7 GPIO_INPUT>;
+			enum-name = "GPIO_TABLET_MODE_L";
+		};
+		gpio_usb_a0_ilimit_sdp: usb_a0_ilimit_sdp {
+			gpios = <&gpiol 5 GPIO_OUTPUT>;
+			enum-name = "GPIO_USB1_ILIM_SEL";
+		};
+		gpio_usb_c0_frs: usb_c0_frs {
+			gpios = <&gpioc 4 GPIO_OUTPUT>;
+		};
+		gpio_usb_c0_int_odl: usb_c0_int_odl {
+			gpios = <&gpiok 0 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_vccin_aux_vid0: vccin_aux_vid0 {
+			gpios = <&gpiod 0 GPIO_INPUT>;
+		};
+		gpio_vccin_aux_vid1: vccin_aux_vid1 {
+			gpios = <&gpiok 1 GPIO_INPUT>;
+		};
+		gpio_voldn_btn_odl: voldn_btn_odl {
+			gpios = <&gpioi 6 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_DOWN_L";
+		};
+		gpio_volup_btn_odl: volup_btn_odl {
+			gpios = <&gpioi 7 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_UP_L";
+		};
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		i2c_ec_i2c_eeprom: ec_i2c_eeprom {
+			i2c-port = <&i2c0>;
+			enum-names = "I2C_PORT_EEPROM";
+		};
+		i2c_ec_i2c_batt: ec_i2c_batt {
+			i2c-port = <&i2c1>;
+			enum-names = "I2C_PORT_BATTERY";
+		};
+		i2c_ec_i2c_sensor: ec_i2c_sensor {
+			i2c-port = <&i2c2>;
+			enum-names = "I2C_PORT_SENSOR";
+		};
+		i2c_ec_i2c_sub_usb_c1: ec_i2c_sub_usb_c1 {
+			i2c-port = <&i2c4>;
+			enum-names = "I2C_PORT_USB_C1_TCPC";
+		};
+		i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 {
+			i2c-port = <&i2c5>;
+			enum-names = "I2C_PORT_USB_C0_TCPC";
+		};
+	};
+};
+
+&adc0 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+};
+
+&i2c2 {
+	status = "okay";
+};
+
+&i2c4 {
+	status = "okay";
+};
+
+&i2c5 {
+	status = "okay";
+};
diff --git a/zephyr/program/nissa/gothrax/gothrax_vif.xml b/zephyr/program/nissa/gothrax/gothrax_vif.xml
new file mode 100644
index 0000000000..1fd17e50c9
--- /dev/null
+++ b/zephyr/program/nissa/gothrax/gothrax_vif.xml
@@ -0,0 +1,350 @@
+<?xml version="1.0" encoding="utf-8"?>
+<vif:VIF xmlns:opt="http://usb.org/VendorInfoFileOptionalContent.xsd" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:vif="http://usb.org/VendorInfoFile.xsd">
+  <vif:VIF_Specification>3.19</vif:VIF_Specification>
+  <vif:VIF_App>
+    <vif:Vendor>USB-IF</vif:Vendor>
+    <vif:Name>VIF Editor</vif:Name>
+    <vif:Version>3.2.4.0</vif:Version>
+  </vif:VIF_App>
+  <vif:Vendor_Name>Google</vif:Vendor_Name>
+  <vif:Model_Part_Number>Gothrax</vif:Model_Part_Number>
+  <vif:Product_Revision>1</vif:Product_Revision>
+  <vif:TID>0</vif:TID>
+  <vif:VIF_Product_Type value="0">Port Product</vif:VIF_Product_Type>
+  <vif:Certification_Type value="1">Reference Platform</vif:Certification_Type>
+  <vif:Product>
+    <!--Product Level Content:-->
+  </vif:Product>
+  <vif:Component>
+    <!--Component 0: Port 0-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Component-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Port_Label>0</vif:Port_Label>
+    <vif:Connector_Type value="2">Type-C®</vif:Connector_Type>
+    <vif:USB4_Supported value="false" />
+    <vif:USB_PD_Support value="true" />
+    <vif:PD_Port_Type value="4">DRP</vif:PD_Port_Type>
+    <vif:Type_C_State_Machine value="2">DRP</vif:Type_C_State_Machine>
+    <vif:Port_Battery_Powered value="true" />
+    <vif:BC_1_2_Support value="2">Charging Port</vif:BC_1_2_Support>
+    <vif:Captive_Cable value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;General PD-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Spec_Revision_Major value="3" />
+    <vif:PD_Spec_Revision_Minor value="1" />
+    <vif:PD_Spec_Version_Major value="1" />
+    <vif:PD_Spec_Version_Minor value="3" />
+    <vif:PD_Specification_Revision value="2">Revision 3</vif:PD_Specification_Revision>
+    <vif:SOP_Capable value="true" />
+    <vif:SOP_P_Capable value="true" />
+    <vif:SOP_PP_Capable value="true" />
+    <vif:SOP_P_Debug_Capable value="false" />
+    <vif:SOP_PP_Debug_Capable value="false" />
+    <vif:Manufacturer_Info_Supported_Port value="true" />
+    <vif:Manufacturer_Info_VID_Port value="6353">18D1</vif:Manufacturer_Info_VID_Port>
+    <vif:Manufacturer_Info_PID_Port value="20570">505A</vif:Manufacturer_Info_PID_Port>
+    <vif:Chunking_Implemented_SOP value="true" />
+    <vif:Unchunked_Extended_Messages_Supported value="false" />
+    <vif:Security_Msgs_Supported_SOP value="false" />
+    <vif:Unconstrained_Power value="false" />
+    <vif:Num_Fixed_Batteries value="1" />
+    <vif:Num_Swappable_Battery_Slots value="0" />
+    <vif:ID_Header_Connector_Type_SOP value="2">USB Type-C® Receptacle</vif:ID_Header_Connector_Type_SOP>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Capabilities-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:USB_Comms_Capable value="true" />
+    <vif:DR_Swap_To_DFP_Supported value="true" />
+    <vif:DR_Swap_To_UFP_Supported value="false" />
+    <vif:VCONN_Swap_To_On_Supported value="true" />
+    <vif:VCONN_Swap_To_Off_Supported value="true" />
+    <vif:Responds_To_Discov_SOP_UFP value="false" />
+    <vif:Responds_To_Discov_SOP_DFP value="true" />
+    <vif:Attempts_Discov_SOP value="true" />
+    <vif:Power_Interruption_Available value="0">No Interruption Possible</vif:Power_Interruption_Available>
+    <vif:Data_Reset_Supported value="false" />
+    <vif:Enter_USB_Supported value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;USB Type-C®-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Type_C_Can_Act_As_Host value="true" />
+    <vif:Type_C_Can_Act_As_Device value="false" />
+    <vif:Type_C_Implements_Try_SRC value="true" />
+    <vif:Type_C_Implements_Try_SNK value="false" />
+    <vif:Type_C_Supports_Audio_Accessory value="false" />
+    <vif:Type_C_Is_VCONN_Powered_Accessory value="false" />
+    <vif:Type_C_Is_Debug_Target_SRC value="true" />
+    <vif:Type_C_Is_Debug_Target_SNK value="true" />
+    <vif:RP_Value value="1">1.5A</vif:RP_Value>
+    <vif:Type_C_Port_On_Hub value="false" />
+    <vif:Type_C_Power_Source value="2">Both</vif:Type_C_Power_Source>
+    <vif:Type_C_Sources_VCONN value="true" />
+    <vif:Type_C_Is_Alt_Mode_Controller value="true" />
+    <vif:Type_C_Is_Alt_Mode_Adapter value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Product Power-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Product_Total_Source_Power_mW value="15000">15000 mW</vif:Product_Total_Source_Power_mW>
+    <vif:Port_Source_Power_Type value="0">Assured</vif:Port_Source_Power_Type>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;USB Host-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Host_Supports_USB_Data value="true" />
+    <vif:Host_Speed value="1">USB 3.2 Gen 1x1</vif:Host_Speed>
+    <vif:Host_Contains_Captive_Retimer value="false" />
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:Host_Is_Embedded value="false" />
+    <vif:Host_Suspend_Supported value="true" />
+    <vif:Is_DFP_On_Hub value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Battery Charging 1.2-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:BC_1_2_Charging_Port_Type value="1">CDP</vif:BC_1_2_Charging_Port_Type>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Source-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Power_As_Source value="15000">15000 mW</vif:PD_Power_As_Source>
+    <vif:EPR_Supported_As_Src value="false" />
+    <vif:USB_Suspend_May_Be_Cleared value="false" />
+    <vif:Sends_Pings value="false" />
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="0">FR_Swap not supported</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <vif:Master_Port value="false" />
+    <vif:Num_Src_PDOs value="1" />
+    <vif:PD_OC_Protection value="true" />
+    <vif:PD_OCP_Method value="0">Over-Current Response</vif:PD_OCP_Method>
+    <!--Bundle: SrcPdoList-->
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!--Source PDO 1-->
+        <vif:Src_PDO_Supply_Type value="0">Fixed</vif:Src_PDO_Supply_Type>
+        <vif:Src_PDO_Peak_Current value="0">100% IOC</vif:Src_PDO_Peak_Current>
+        <vif:Src_PDO_Voltage value="100">5000 mV</vif:Src_PDO_Voltage>
+        <vif:Src_PDO_Max_Current value="300">3000 mA</vif:Src_PDO_Max_Current>
+        <vif:Src_PD_OCP_OC_Debounce value="0">0 msec</vif:Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="300">3000 mA</vif:Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Sink-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Power_As_Sink value="45000">45000 mW</vif:PD_Power_As_Sink>
+    <vif:EPR_Supported_As_Snk value="false" />
+    <vif:No_USB_Suspend_May_Be_Set value="true" />
+    <vif:GiveBack_May_Be_Set value="false" />
+    <vif:Higher_Capability_Set value="false" />
+    <vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source value="0">FR_Swap not supported</vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source>
+    <vif:Num_Snk_PDOs value="3" />
+    <!--Bundle: SnkPdoList-->
+    <vif:SnkPdoList>
+      <vif:SnkPDO>
+        <!--Sink PDO 1-->
+        <vif:Snk_PDO_Supply_Type value="0">Fixed</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Voltage value="100">5000 mV</vif:Snk_PDO_Voltage>
+        <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>
+      </vif:SnkPDO>
+      <vif:SnkPDO>
+        <!--Sink PDO 2-->
+        <vif:Snk_PDO_Supply_Type value="1">Battery</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Op_Power value="60">15000 mW</vif:Snk_PDO_Op_Power>
+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>
+        <vif:Snk_PDO_Max_Voltage value="300">15000 mV</vif:Snk_PDO_Max_Voltage>
+      </vif:SnkPDO>
+      <vif:SnkPDO>
+        <!--Sink PDO 3-->
+        <vif:Snk_PDO_Supply_Type value="2">Variable</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>
+        <vif:Snk_PDO_Max_Voltage value="300">15000 mV</vif:Snk_PDO_Max_Voltage>
+        <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>
+      </vif:SnkPDO>
+    </vif:SnkPdoList>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Dual Role-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Accepts_PR_Swap_As_Src value="true" />
+    <vif:Accepts_PR_Swap_As_Snk value="true" />
+    <vif:Requests_PR_Swap_As_Src value="true" />
+    <vif:Requests_PR_Swap_As_Snk value="true" />
+    <vif:FR_Swap_Supported_As_Initial_Sink value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;SOP Discover ID-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:XID_SOP value="0" />
+    <vif:Data_Capable_As_USB_Host_SOP value="true" />
+    <vif:Data_Capable_As_USB_Device_SOP value="false" />
+    <vif:Product_Type_UFP_SOP value="0">Undefined</vif:Product_Type_UFP_SOP>
+    <vif:Product_Type_DFP_SOP value="2">PDUSB Host</vif:Product_Type_DFP_SOP>
+    <vif:DFP_VDO_Port_Number value="0" />
+    <vif:Modal_Operation_Supported_SOP value="false" />
+    <vif:USB_VID_SOP value="6353">18D1</vif:USB_VID_SOP>
+    <vif:PID_SOP value="20570">505A</vif:PID_SOP>
+    <vif:bcdDevice_SOP value="0">0000</vif:bcdDevice_SOP>
+  </vif:Component>
+  <vif:Component>
+    <!--Component 1: Port 1-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Component-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Port_Label>1</vif:Port_Label>
+    <vif:Connector_Type value="2">Type-C®</vif:Connector_Type>
+    <vif:USB4_Supported value="false" />
+    <vif:USB_PD_Support value="true" />
+    <vif:PD_Port_Type value="4">DRP</vif:PD_Port_Type>
+    <vif:Type_C_State_Machine value="2">DRP</vif:Type_C_State_Machine>
+    <vif:Port_Battery_Powered value="true" />
+    <vif:BC_1_2_Support value="2">Charging Port</vif:BC_1_2_Support>
+    <vif:Captive_Cable value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;General PD-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Spec_Revision_Major value="3" />
+    <vif:PD_Spec_Revision_Minor value="1" />
+    <vif:PD_Spec_Version_Major value="1" />
+    <vif:PD_Spec_Version_Minor value="3" />
+    <vif:PD_Specification_Revision value="2">Revision 3</vif:PD_Specification_Revision>
+    <vif:SOP_Capable value="true" />
+    <vif:SOP_P_Capable value="true" />
+    <vif:SOP_PP_Capable value="true" />
+    <vif:SOP_P_Debug_Capable value="false" />
+    <vif:SOP_PP_Debug_Capable value="false" />
+    <vif:Manufacturer_Info_Supported_Port value="true" />
+    <vif:Manufacturer_Info_VID_Port value="6353">18D1</vif:Manufacturer_Info_VID_Port>
+    <vif:Manufacturer_Info_PID_Port value="20570">505A</vif:Manufacturer_Info_PID_Port>
+    <vif:Chunking_Implemented_SOP value="true" />
+    <vif:Unchunked_Extended_Messages_Supported value="false" />
+    <vif:Security_Msgs_Supported_SOP value="false" />
+    <vif:Unconstrained_Power value="false" />
+    <vif:Num_Fixed_Batteries value="1" />
+    <vif:Num_Swappable_Battery_Slots value="0" />
+    <vif:ID_Header_Connector_Type_SOP value="2">USB Type-C® Receptacle</vif:ID_Header_Connector_Type_SOP>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Capabilities-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:USB_Comms_Capable value="true" />
+    <vif:DR_Swap_To_DFP_Supported value="true" />
+    <vif:DR_Swap_To_UFP_Supported value="false" />
+    <vif:VCONN_Swap_To_On_Supported value="true" />
+    <vif:VCONN_Swap_To_Off_Supported value="true" />
+    <vif:Responds_To_Discov_SOP_UFP value="false" />
+    <vif:Responds_To_Discov_SOP_DFP value="true" />
+    <vif:Attempts_Discov_SOP value="true" />
+    <vif:Power_Interruption_Available value="0">No Interruption Possible</vif:Power_Interruption_Available>
+    <vif:Data_Reset_Supported value="false" />
+    <vif:Enter_USB_Supported value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;USB Type-C®-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Type_C_Can_Act_As_Host value="true" />
+    <vif:Type_C_Can_Act_As_Device value="false" />
+    <vif:Type_C_Implements_Try_SRC value="true" />
+    <vif:Type_C_Implements_Try_SNK value="false" />
+    <vif:Type_C_Supports_Audio_Accessory value="false" />
+    <vif:Type_C_Is_VCONN_Powered_Accessory value="false" />
+    <vif:Type_C_Is_Debug_Target_SRC value="true" />
+    <vif:Type_C_Is_Debug_Target_SNK value="true" />
+    <vif:RP_Value value="1">1.5A</vif:RP_Value>
+    <vif:Type_C_Port_On_Hub value="false" />
+    <vif:Type_C_Power_Source value="2">Both</vif:Type_C_Power_Source>
+    <vif:Type_C_Sources_VCONN value="true" />
+    <vif:Type_C_Is_Alt_Mode_Controller value="true" />
+    <vif:Type_C_Is_Alt_Mode_Adapter value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Product Power-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Product_Total_Source_Power_mW value="15000">15000 mW</vif:Product_Total_Source_Power_mW>
+    <vif:Port_Source_Power_Type value="0">Assured</vif:Port_Source_Power_Type>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;USB Host-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Host_Supports_USB_Data value="true" />
+    <vif:Host_Speed value="1">USB 3.2 Gen 1x1</vif:Host_Speed>
+    <vif:Host_Contains_Captive_Retimer value="true" />
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:Host_Is_Embedded value="false" />
+    <vif:Host_Suspend_Supported value="true" />
+    <vif:Is_DFP_On_Hub value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Battery Charging 1.2-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:BC_1_2_Charging_Port_Type value="1">CDP</vif:BC_1_2_Charging_Port_Type>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Source-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Power_As_Source value="15000">15000 mW</vif:PD_Power_As_Source>
+    <vif:EPR_Supported_As_Src value="false" />
+    <vif:USB_Suspend_May_Be_Cleared value="false" />
+    <vif:Sends_Pings value="false" />
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="0">FR_Swap not supported</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <vif:Master_Port value="false" />
+    <vif:Num_Src_PDOs value="1" />
+    <vif:PD_OC_Protection value="true" />
+    <vif:PD_OCP_Method value="0">Over-Current Response</vif:PD_OCP_Method>
+    <!--Bundle: SrcPdoList-->
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!--Source PDO 1-->
+        <vif:Src_PDO_Supply_Type value="0">Fixed</vif:Src_PDO_Supply_Type>
+        <vif:Src_PDO_Peak_Current value="0">100% IOC</vif:Src_PDO_Peak_Current>
+        <vif:Src_PDO_Voltage value="100">5000 mV</vif:Src_PDO_Voltage>
+        <vif:Src_PDO_Max_Current value="300">3000 mA</vif:Src_PDO_Max_Current>
+        <vif:Src_PD_OCP_OC_Debounce value="0">0 msec</vif:Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="300">3000 mA</vif:Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Sink-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Power_As_Sink value="45000">45000 mW</vif:PD_Power_As_Sink>
+    <vif:EPR_Supported_As_Snk value="false" />
+    <vif:No_USB_Suspend_May_Be_Set value="true" />
+    <vif:GiveBack_May_Be_Set value="false" />
+    <vif:Higher_Capability_Set value="false" />
+    <vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source value="0">FR_Swap not supported</vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source>
+    <vif:Num_Snk_PDOs value="3" />
+    <!--Bundle: SnkPdoList-->
+    <vif:SnkPdoList>
+      <vif:SnkPDO>
+        <!--Sink PDO 1-->
+        <vif:Snk_PDO_Supply_Type value="0">Fixed</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Voltage value="100">5000 mV</vif:Snk_PDO_Voltage>
+        <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>
+      </vif:SnkPDO>
+      <vif:SnkPDO>
+        <!--Sink PDO 2-->
+        <vif:Snk_PDO_Supply_Type value="1">Battery</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Op_Power value="60">15000 mW</vif:Snk_PDO_Op_Power>
+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>
+        <vif:Snk_PDO_Max_Voltage value="300">15000 mV</vif:Snk_PDO_Max_Voltage>
+      </vif:SnkPDO>
+      <vif:SnkPDO>
+        <!--Sink PDO 3-->
+        <vif:Snk_PDO_Supply_Type value="2">Variable</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>
+        <vif:Snk_PDO_Max_Voltage value="300">15000 mV</vif:Snk_PDO_Max_Voltage>
+        <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>
+      </vif:SnkPDO>
+    </vif:SnkPdoList>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Dual Role-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Accepts_PR_Swap_As_Src value="true" />
+    <vif:Accepts_PR_Swap_As_Snk value="true" />
+    <vif:Requests_PR_Swap_As_Src value="true" />
+    <vif:Requests_PR_Swap_As_Snk value="true" />
+    <vif:FR_Swap_Supported_As_Initial_Sink value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;SOP Discover ID-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:XID_SOP value="0" />
+    <vif:Data_Capable_As_USB_Host_SOP value="true" />
+    <vif:Data_Capable_As_USB_Device_SOP value="false" />
+    <vif:Product_Type_UFP_SOP value="0">Undefined</vif:Product_Type_UFP_SOP>
+    <vif:Product_Type_DFP_SOP value="2">PDUSB Host</vif:Product_Type_DFP_SOP>
+    <vif:DFP_VDO_Port_Number value="1" />
+    <vif:Modal_Operation_Supported_SOP value="false" />
+    <vif:USB_VID_SOP value="6353">18D1</vif:USB_VID_SOP>
+    <vif:PID_SOP value="20570">505A</vif:PID_SOP>
+    <vif:bcdDevice_SOP value="0">0000</vif:bcdDevice_SOP>
+  </vif:Component>
+</vif:VIF>
\ No newline at end of file
diff --git a/zephyr/program/nissa/gothrax/keyboard.dtsi b/zephyr/program/nissa/gothrax/keyboard.dtsi
new file mode 100644
index 0000000000..eab435b743
--- /dev/null
+++ b/zephyr/program/nissa/gothrax/keyboard.dtsi
@@ -0,0 +1,30 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+&cros_kb_raw {
+	status = "okay";
+	/* No KSO2 (it's inverted and implemented by GPIO) */
+	pinctrl-0 = <&ksi0_default
+		     &ksi1_default
+		     &ksi2_default
+		     &ksi3_default
+		     &ksi4_default
+		     &ksi5_default
+		     &ksi6_default
+		     &ksi7_default
+		     &kso0_default
+		     &kso1_default
+		     &kso3_default
+		     &kso4_default
+		     &kso5_default
+		     &kso6_default
+		     &kso7_default
+		     &kso8_default
+		     &kso9_default
+		     &kso10_default
+		     &kso11_default
+		     &kso12_default>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/nissa/gothrax/motionsense.dtsi b/zephyr/program/nissa/gothrax/motionsense.dtsi
new file mode 100644
index 0000000000..a65bb48fbd
--- /dev/null
+++ b/zephyr/program/nissa/gothrax/motionsense.dtsi
@@ -0,0 +1,147 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/motionsense/utils.h>
+
+
+/ {
+	aliases {
+		/*
+		 * Interrupt bindings for sensor devices.
+		 */
+		bmi3xx-int = &base_accel;
+		bma4xx-int = &lid_accel;
+	};
+
+	/*
+	 * Declare mutexes used by sensor drivers.
+	 * A mutex node is used to create an instance of mutex_t.
+	 * A mutex node is referenced by a sensor node if the
+	 * corresponding sensor driver needs to use the
+	 * instance of the mutex.
+	 */
+	motionsense-mutex {
+		compatible = "cros-ec,motionsense-mutex";
+		lid_mutex: lid-mutex {
+		};
+
+		base_mutex: base-mutex {
+		};
+	};
+
+	/* Rotation matrix used by drivers. */
+	motionsense-rotation-ref {
+		compatible = "cros-ec,motionsense-rotation-ref";
+		lid_rot_ref: lid-rotation-ref {
+			mat33 = <0 (-1) 0
+				 (-1) 0 0
+				 0 0 (-1)>;
+		};
+
+		base_rot_ref: base-rotation-ref {
+			mat33 = <0 1 0
+				 (-1) 0 0
+				 0 0 1>;
+		};
+	};
+
+	/*
+	 * Driver specific data. A driver-specific data can be shared with
+	 * different motion sensors while they are using the same driver.
+	 *
+	 * If a node's compatible starts with "cros-ec,accelgyro-", it is for
+	 * a common structure defined in accelgyro.h.
+	 * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for
+	 * "struct als_drv_data_t" in accelgyro.h
+	 */
+	motionsense-sensor-data {
+		bmi323_data: bmi323-drv-data {
+			compatible = "cros-ec,drvdata-bmi3xx";
+			status = "okay";
+		};
+
+		bma422_data: bma422-drv-data {
+			compatible = "cros-ec,drvdata-bma4xx";
+			status = "okay";
+		};
+	};
+
+	/*
+	 * List of motion sensors that creates motion_sensors array.
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
+	 * motion sensor IDs for lid angle calculation.
+	 * TODO(b/238139272): The first entries of the array must be
+	 * accelerometers,then gyroscope. Fix this dependency in the DTS
+	 * processing which makes the devicetree entries independent.
+	 */
+	motionsense-sensor {
+		lid_accel: lid-accel {
+			compatible = "cros-ec,bma4xx";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&lid_mutex>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&lid_rot_ref>;
+			default-range = <2>;
+			drv-data = <&bma422_data>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_accel: base-accel {
+			compatible = "cros-ec,bmi3xx-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&bmi323_data>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_gyro: base-gyro {
+			compatible = "cros-ec,bmi3xx-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&bmi323_data>;
+		};
+	};
+
+	motionsense-sensor-info {
+		compatible = "cros-ec,motionsense-sensor-info";
+
+		/*
+		 * list of GPIO interrupts that have to
+		 * be enabled at initial stage
+		 */
+		sensor-irqs = <&int_imu &int_lid_imu>;
+	};
+};
diff --git a/zephyr/program/nissa/gothrax/overlay.dtsi b/zephyr/program/nissa/gothrax/overlay.dtsi
new file mode 100644
index 0000000000..abba76e55d
--- /dev/null
+++ b/zephyr/program/nissa/gothrax/overlay.dtsi
@@ -0,0 +1,457 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <cros/thermistor/thermistor.dtsi>
+#include <dt-bindings/usbc_mux.h>
+#include <dt-bindings/usb_pd_tcpm.h>
+
+/ {
+	aliases {
+		gpio-cbi-wp = &gpio_ec_cbi_wp;
+		gpio-wp = &gpio_ec_wp_odl;
+		int-wp = &int_wp_l;
+		/*
+		 * USB-C: interrupt input.
+		 * I2C pins are on i2c_ec_i2c_sub_usb_c1
+		 */
+		gpio-usb-c1-int-odl = &gpio_sb_1;
+		/*
+		 * USB-A: VBUS enable output
+		 * LTE: power enable output
+		 */
+		gpio-en-usb-a1-vbus = &gpio_sb_2;
+		/*
+		 * HDMI: power enable output, HDMI enable output,
+		 * and HPD input
+		 */
+		gpio-en-rails-odl = &gpio_sb_1;
+		gpio-hdmi-en-odl = &gpio_sb_4;
+		gpio-hpd-odl = &gpio_sb_3;
+		/*
+		 * Enable S5 rails for LTE sub-board
+		 */
+		gpio-en-sub-s5-rails = &gpio_sb_2;
+	};
+
+
+	ec-console {
+		compatible = "ec-console";
+		disabled = "events", "lpc", "hostcmd";
+	};
+
+	batteries {
+		default_battery: smp {
+			compatible = "smp,l20m3pg0", "battery-smart";
+		};
+	};
+
+	hibernate-wake-pins {
+		compatible = "cros-ec,hibernate-wake-pins";
+		wakeup-irqs = <
+			&int_power_button
+			&int_lid_open
+		>;
+	};
+
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_power_button: power_button {
+			irq-pin = <&gpio_gsc_ec_pwr_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_button_interrupt";
+		};
+		int_vol_down: vol_down {
+			irq-pin = <&gpio_voldn_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+		int_vol_up: vol_up {
+			irq-pin = <&gpio_volup_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+		int_wp_l: wp_l {
+			irq-pin = <&gpio_ec_wp_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "switch_interrupt";
+		};
+		int_lid_open: lid_open {
+			irq-pin = <&gpio_lid_open>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "lid_interrupt";
+		};
+		int_tablet_mode: tablet_mode {
+			irq-pin = <&gpio_tablet_mode_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "gmr_tablet_switch_isr";
+		};
+		int_imu: ec_imu {
+			irq-pin = <&gpio_imu_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "bmi3xx_interrupt";
+		};
+		int_lid_imu: lid_imu {
+			irq-pin = <&gpio_acc_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "bma4xx_interrupt";
+		};
+		int_usb_c0: usb_c0 {
+			irq-pin = <&gpio_usb_c0_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "usb_interrupt";
+		};
+		int_usb_c1: usb_c1 {
+			irq-pin = <&gpio_sb_1>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "usb_interrupt";
+		};
+	};
+
+	unused-pins {
+		compatible = "unused-gpios";
+		unused-gpios = <&gpioa 3 0>,
+			       <&gpioc 3 0>,
+			       <&gpioc 4 0>,
+			       <&gpioc 6 0>,
+			       <&gpioc 7 0>,
+			       <&gpiod 4 0>,
+			       <&gpiof 4 0>,
+			       <&gpiof 5 0>,
+			       <&gpioh 2 0>,
+			       <&gpioh 4 0>,
+			       <&gpioh 6 0>,
+			       <&gpioj 3 0>,
+			       <&gpioj 7 0>,
+			       <&gpiok 6 0>,
+			       <&gpiol 4 0>;
+	};
+
+	named-gpios {
+		/*
+		 * EC doesn't take any specific action on CC/SBU disconnect due to
+		 * fault, but this definition is useful for hardware testing.
+		 */
+		gpio_sb_1: sb_1 {
+			gpios = <&gpioe 6 0>;
+			no-auto-init;
+		};
+		gpio_sb_2: sb_2 {
+			gpios = <&gpiof 0 0>;
+			no-auto-init;
+		};
+
+		gpio_sb_3: sb_3 {
+			gpios = <&gpioe 7 0>;
+			no-auto-init;
+		};
+		gpio_sb_4: sb_4 {
+			gpios = <&gpioe 0 0>;
+			no-auto-init;
+		};
+		gpio_fan_enable: fan-enable {
+			gpios = <&gpiog 3 GPIO_OUTPUT>;
+			no-auto-init;
+		};
+	};
+
+	temp_memory: memory {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_1>;
+	};
+	temp_charger: charger {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_2>;
+	};
+	temp_ambient: ambient {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_3>;
+	};
+
+	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
+		memory {
+			temp_fan_off = <35>;
+			temp_fan_max = <60>;
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_memory>;
+		};
+		charger {
+			temp_fan_off = <35>;
+			temp_fan_max = <60>;
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_charger>;
+		};
+		ambient {
+			temp_fan_off = <35>;
+			temp_fan_max = <60>;
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_ambient>;
+		};
+	};
+
+	usba {
+		compatible = "cros-ec,usba-port-enable-pins";
+		/*
+		 * sb_2 is only configured as GPIO when USB-A1 is present,
+		 * but it's still safe to control when disabled.
+		 *
+		 * ILIM_SEL pins are referred to by legacy enum name,
+		 * GPIO_USB*_ILIM_SEL. The one for port A1 is unused on
+		 * sub-boards that don't have USB-A so is safe to control
+		 * regardless of system configuration.
+		 */
+		enable-pins = <&gpio_en_usb_a0_vbus &gpio_sb_2>;
+		status = "okay";
+	};
+
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+			bc12 = <&bc12_port0>;
+			chg = <&chg_port0>;
+			tcpc = <&tcpc_port0>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_0>;
+			};
+		};
+		port0-muxes {
+			virtual_mux_0: virtual-mux-0 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+		port1@1 {
+			compatible = "named-usbc-port";
+			reg = <1>;
+			bc12 = <&bc12_port1>;
+			chg = <&chg_port1>;
+			tcpc = <&tcpc_port1>;
+			usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_1 &anx7483_mux_1>;
+			};
+			usb_mux_chain_1_no_mux: usb-mux-chain-1-no-mux {
+				compatible = "cros-ec,usb-mux-chain";
+				alternative-chain;
+				usb-muxes = <&virtual_mux_1>;
+			};
+		};
+		port1-muxes {
+			virtual_mux_1: virtual-mux-1 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+	};
+	fans {
+		compatible = "cros-ec,fans";
+
+		fan_0 {
+			pwms = <&pwm0 0 PWM_KHZ(30) PWM_POLARITY_NORMAL>;
+			tach = <&tach1>;
+			rpm_min = <1500>;
+			rpm_start = <1500>;
+			rpm_max = <6500>;
+			enable_gpio = <&gpio_fan_enable>;
+		};
+	};
+};
+
+&gpio_acc_int_l {
+	gpios = <&gpioc 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+};
+&gpio_imu_int_l {
+	gpios = <&gpioj 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+};
+&gpio_vccin_aux_vid0 {
+	gpios = <&gpiod 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+};
+&gpio_vccin_aux_vid1 {
+	gpios = <&gpiok 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+};
+
+&gpio_ec_prochot_odl {
+	gpios = <&gpioi 1 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>;
+};
+
+&thermistor_3V3_51K1_47K_4050B {
+	status = "okay";
+};
+
+&adc_ec_vsense_pp3300_s5 {
+	/*
+	 * Voltage divider on input has 47k upper and 220k lower legs with 3 V
+	 * full-scale reading on the ADC. Apply the largest possible multiplier
+	 * (without overflowing int32) to get the best possible approximation
+	 * of the actual ratio, but derate by a factor of two to ensure
+	 * unexpectedly high values won't overflow.
+	 */
+	mul = <(715828 / 2)>;
+	div = <(589820 / 2)>;
+};
+
+&adc0 {
+	pinctrl-0 = <&adc0_ch0_gpi0_default
+		     &adc0_ch2_gpi2_default
+		     &adc0_ch3_gpi3_default
+		     &adc0_ch13_gpl0_default
+		     &adc0_ch14_gpl1_default>;
+	pinctrl-names = "default";
+};
+
+&pinctrl {
+	i2c4_clk_gpe0_sleep: i2c4_clk_gpe0_sleep {
+		pinmuxs = <&pinctrle 0 IT8XXX2_ALT_DEFAULT>;
+	};
+	i2c4_data_gpe7_sleep: i2c4_data_gpe7_sleep {
+		pinmuxs = <&pinctrle 7 IT8XXX2_ALT_DEFAULT>;
+	};
+	i2c2_clk_gpf6_default: i2c2_clk_gpf6_default {
+		gpio-voltage = "1v8";
+	};
+	i2c2_data_gpf7_default: i2c2_data_gpf7_default {
+		gpio-voltage = "1v8";
+	};
+};
+
+&i2c0 {
+	label = "I2C_EEPROM";
+	clock-frequency = <I2C_BITRATE_FAST>;
+
+	cbi_eeprom: eeprom@50 {
+		compatible = "atmel,at24";
+		reg = <0x50>;
+		size = <2048>;
+		pagesize = <16>;
+		address-width = <8>;
+		timeout = <5>;
+	};
+	pinctrl-0 = <&i2c0_clk_gpb3_default
+		     &i2c0_data_gpb4_default>;
+	pinctrl-names = "default";
+};
+
+&i2c1 {
+	label = "I2C_BATTERY";
+	clock-frequency = <50000>;
+	pinctrl-0 = <&i2c1_clk_gpc1_default
+		     &i2c1_data_gpc2_default>;
+	pinctrl-names = "default";
+};
+
+&i2c2 {
+	label = "I2C_SENSOR";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c2_clk_gpf6_default
+		     &i2c2_data_gpf7_default>;
+	pinctrl-names = "default";
+};
+
+&i2c4 {
+	label = "I2C_SUB_C1_TCPC";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+	pinctrl-0 = <&i2c4_clk_gpe0_default
+		     &i2c4_data_gpe7_default>;
+	pinctrl-1 = <&i2c4_clk_gpe0_sleep
+		     &i2c4_data_gpe7_sleep>;
+	pinctrl-names = "default", "sleep";
+
+	bc12_port1: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+	};
+
+	chg_port1: isl923x@9 {
+		compatible = "intersil,isl923x";
+		status = "okay";
+		reg = <0x9>;
+	};
+
+	tcpc_port1: raa489000@22 {
+		compatible = "renesas,raa489000";
+		reg = <0x22>;
+		tcpc-flags = <(
+			TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_VBUS_MONITOR)>;
+	};
+	anx7483_mux_1: anx7483-mux-1@3e {
+		compatible = "analogix,anx7483";
+		reg = <0x3e>;
+		board-set = "anx7483_set_default_tuning";
+		flags = <USB_MUX_FLAG_RESETS_IN_G3>;
+	};
+};
+
+&i2c_ec_i2c_sub_usb_c1 {
+	/*
+	 * Dynamic speed setting is used for AP-controlled firmware update
+	 * of PS8745 TCPC/redriver: the AP lowers speed to 400 kHz in order
+	 * to use more efficient window programming, then sets it back when
+	 * done.
+	 */
+	dynamic-speed;
+};
+
+&i2c5 {
+	label = "I2C_USB_C0_TCPC";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+	pinctrl-0 = <&i2c5_clk_gpa4_default
+		     &i2c5_data_gpa5_default>;
+	pinctrl-names = "default";
+
+	bc12_port0: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+	};
+
+	chg_port0: isl923x@9 {
+		compatible = "intersil,isl923x";
+		status = "okay";
+		reg = <0x9>;
+	};
+	tcpc_port0: raa489000@22 {
+		compatible = "renesas,raa489000";
+		reg = <0x22>;
+		tcpc-flags = <(
+			TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_VBUS_MONITOR)>;
+	};
+};
+
+/* pwm for fan */
+&pwm0 {
+	status = "okay";
+	prescaler-cx = <PWM_PRESCALER_C6>;
+	pinctrl-0 = <&pwm0_gpa0_default>;
+	pinctrl-names = "default";
+};
+
+/* fan tachometer sensor */
+&tach1 {
+	status = "okay";
+	channel = <IT8XXX2_TACH_CHANNEL_A>;
+	pulses-per-round = <2>;
+	pinctrl-0 = <&tach1a_gpd7_default>;
+	pinctrl-names = "default";
+};
+
diff --git a/zephyr/program/nissa/gothrax/power_signals.dtsi b/zephyr/program/nissa/gothrax/power_signals.dtsi
new file mode 100644
index 0000000000..8affae03b1
--- /dev/null
+++ b/zephyr/program/nissa/gothrax/power_signals.dtsi
@@ -0,0 +1,223 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	chosen {
+		intel-ap-pwrseq,espi = &espi0;
+	};
+
+	common-pwrseq {
+		compatible = "intel,ap-pwrseq";
+
+		sys-pwrok-delay = <10>;
+		all-sys-pwrgd-timeout = <20>;
+	};
+
+	pwr-en-pp5000-s5 {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PP5000_S5 enable output to regulator";
+		enum-name = "PWR_EN_PP5000_A";
+		gpios = <&gpiok 5 0>;
+		output;
+	};
+	pwr-en-pp3300-s5 {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PP3300_S5 enable output to LS";
+		enum-name = "PWR_EN_PP3300_A";
+		gpios = <&gpioc 5 0>;
+		output;
+	};
+	pwr-pg-ec-rsmrst-odl {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST power good from regulator";
+		enum-name = "PWR_RSMRST";
+		gpios = <&gpioe 1 0>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-ec-pch-rsmrst-odl {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST output to PCH";
+		enum-name = "PWR_EC_PCH_RSMRST";
+		gpios = <&gpioh 0 0>;
+		output;
+	};
+	pwr-slp-s0-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_S0_L input from PCH";
+		enum-name = "PWR_SLP_S0";
+		gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-slp-s3-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_S3_L input from PCH";
+		enum-name = "PWR_SLP_S3";
+		gpios = <&gpioh 3 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-slp-sus-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_SUS_L input from PCH";
+		enum-name = "PWR_SLP_SUS";
+		gpios = <&gpiog 2 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-ec-soc-dsw-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "DSW_PWROK output to PCH";
+		enum-name = "PWR_EC_SOC_DSW_PWROK";
+		gpios = <&gpiol 7 0>;
+		output;
+	};
+	pwr-vccst-pwrgd-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "VCCST_PWRGD output to PCH";
+		enum-name = "PWR_VCCST_PWRGD";
+		gpios = <&gpioe 5 (GPIO_OPEN_DRAIN | GPIO_VOLTAGE_1P8)>;
+		output;
+	};
+	pwr-imvp9-vrrdy-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "VRRDY input from IMVP9";
+		enum-name = "PWR_IMVP9_VRRDY";
+		gpios = <&gpioj 4 0>;
+	};
+	pwr-pch-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PCH_PWROK output to PCH";
+		enum-name = "PWR_PCH_PWROK";
+		gpios = <&gpiod 6 GPIO_OPEN_DRAIN>;
+		output;
+	};
+	pwr-ec-pch-sys-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_PWROK output to PCH";
+		enum-name = "PWR_EC_PCH_SYS_PWROK";
+		gpios = <&gpiof 2 0>;
+		output;
+	};
+	pwr-sys-rst-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_RESET# output to PCH";
+		enum-name = "PWR_SYS_RST";
+		gpios = <&gpiod 1 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>;
+		output;
+	};
+	pwr-slp-s4 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S4 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S4";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4";
+		vw-invert;
+	};
+	pwr-slp-s5 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S5 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S5";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5";
+		vw-invert;
+	};
+	pwr-all-sys-pwrgd {
+		/*
+		 * This is a board level signal, since this
+		 * signal needs some special processing.
+		 */
+		compatible = "intel,ap-pwrseq-external";
+		dbg-label = "Combined all power good";
+		enum-name = "PWR_ALL_SYS_PWRGD";
+	};
+	pwr-adc-pp3300 {
+		compatible = "intel,ap-pwrseq-adc";
+		dbg-label = "PP3300_PROC";
+		enum-name = "PWR_DSW_PWROK";
+		trigger-high = <&vcmp0>;
+		trigger-low = <&vcmp1>;
+	};
+	pwr-adc-pp1p05 {
+		compatible = "intel,ap-pwrseq-adc";
+		dbg-label = "PP1P05_PROC";
+		enum-name = "PWR_PG_PP1P05";
+		trigger-high = <&vcmp2>;
+		trigger-low = <&vcmp3>;
+	};
+
+};
+
+/*
+ * Because the power signals directly reference the GPIOs,
+ * the correspinding named-gpios need to have no-auto-init set.
+ */
+&gpio_ec_soc_dsw_pwrok {
+	no-auto-init;
+};
+&gpio_ec_soc_pch_pwrok_od {
+	no-auto-init;
+};
+&gpio_ec_soc_rsmrst_l {
+	no-auto-init;
+};
+&gpio_ec_soc_sys_pwrok {
+	no-auto-init;
+};
+&gpio_ec_soc_vccst_pwrgd_od {
+	no-auto-init;
+};
+&gpio_en_pp3300_s5 {
+	no-auto-init;
+};
+&gpio_en_pp5000_s5 {
+	no-auto-init;
+};
+&gpio_imvp91_vrrdy_od {
+	no-auto-init;
+};
+&gpio_rsmrst_pwrgd_l {
+	no-auto-init;
+};
+&gpio_slp_s0_l {
+	no-auto-init;
+};
+&gpio_slp_s3_l {
+	no-auto-init;
+};
+&gpio_slp_sus_l {
+	no-auto-init;
+};
+&gpio_sys_rst_odl {
+	no-auto-init;
+};
+&vcmp0 {
+	status = "okay";
+	scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>;
+	comparison = <IT8XXX2_VCMP_GREATER>;
+	/*
+	 * This is 90% of nominal voltage considering voltage
+	 * divider on ADC input.
+	 */
+	threshold-mv = <2448>;
+	io-channels = <&adc0 0>;
+};
+&vcmp1 {
+	status = "okay";
+	scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>;
+	comparison = <IT8XXX2_VCMP_LESS_OR_EQUAL>;
+	threshold-mv = <2448>;
+	io-channels = <&adc0 0>;
+};
+&vcmp2 {
+	status = "okay";
+	scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>;
+	comparison = <IT8XXX2_VCMP_GREATER>;
+	/* Setting at 90% of nominal voltage */
+	threshold-mv = <945>;
+	io-channels = <&adc0 14>;
+};
+&vcmp3 {
+	status = "okay";
+	scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>;
+	comparison = <IT8XXX2_VCMP_LESS_OR_EQUAL>;
+	threshold-mv = <945>;
+	io-channels = <&adc0 14>;
+};
diff --git a/zephyr/program/nissa/gothrax/project.conf b/zephyr/program/nissa/gothrax/project.conf
new file mode 100644
index 0000000000..d7e20eed7e
--- /dev/null
+++ b/zephyr/program/nissa/gothrax/project.conf
@@ -0,0 +1,45 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_BOARD_GOTHRAX=y
+
+# Ensure recovery key combination (esc+refresh+power) is reliable: b/236580049
+CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI2=y
+
+# Sensor drivers
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y
+CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y
+CONFIG_PLATFORM_EC_MAX_SENSOR_FREQ_MILLIHZ=100000
+
+# Both ports use a PI5USB2546 smart switch with CTL1..3 fixed high,
+# for SDP2 or CDP only.
+CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART=y
+CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_CDP_SDP_ONLY=y
+CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_DEFAULT_CDP=y
+CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_INVERTED=y
+
+# Charger driver and configuration
+CONFIG_PLATFORM_EC_CHARGER_SM5803=n
+CONFIG_PLATFORM_EC_CHARGER_RAA489000=y
+CONFIG_PLATFORM_EC_OCPC_DEF_RBATT_MOHMS=22
+CONFIG_PLATFORM_EC_RAA489000_AC_PRESENT_CONTROL=y
+
+# TCPC+PPC: ITE on-chip no for C0, PS8745 no for optional C1
+CONFIG_PLATFORM_EC_USB_PD_TCPM_DRIVER_IT8XXX2=n
+CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8745=n
+CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_CHARGER=n
+# SM5803 controls power path on both ports
+CONFIG_PLATFORM_EC_USB_PD_5V_CHARGER_CTRL=n
+
+# TCPC+PPC: both C0 and C1 (if present) are RAA489000
+CONFIG_PLATFORM_EC_USB_PD_TCPM_RAA489000=y
+CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_TCPC=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y
+CONFIG_PLATFORM_EC_USB_PD_TCPC_LPM_EXIT_DEBOUNCE_US=100000
+# RAA489000 uses TCPCI but not a separate PPC, so custom function is required
+CONFIG_PLATFORM_EC_USB_PD_5V_EN_CUSTOM=y
+
+# save RAM, fix `RAM' overflowed by 428 bytes
+CONFIG_TASK_PD_INT_STACK_SIZE=1024
\ No newline at end of file
diff --git a/zephyr/program/nissa/gothrax/project.overlay b/zephyr/program/nissa/gothrax/project.overlay
new file mode 100644
index 0000000000..ee367b9c28
--- /dev/null
+++ b/zephyr/program/nissa/gothrax/project.overlay
@@ -0,0 +1,14 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "../cbi.dtsi"
+#include "../shi.dtsi"
+
+#include "generated.dtsi"
+#include "keyboard.dtsi"
+#include "motionsense.dtsi"
+#include "overlay.dtsi"
+#include "power_signals.dtsi"
+#include "pwm_leds.dtsi"
diff --git a/zephyr/program/nissa/gothrax/pwm_leds.dtsi b/zephyr/program/nissa/gothrax/pwm_leds.dtsi
new file mode 100644
index 0000000000..aa4a76b271
--- /dev/null
+++ b/zephyr/program/nissa/gothrax/pwm_leds.dtsi
@@ -0,0 +1,60 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	pwmleds {
+		compatible = "pwm-leds";
+		pwm_led0: pwm_led_0 {
+			pwms = <&pwm1 1 PWM_HZ(1296) PWM_POLARITY_INVERTED>,
+			       <&pwm2 2 PWM_HZ(1296) PWM_POLARITY_INVERTED>,
+			       <&pwm3 3 PWM_HZ(1296) PWM_POLARITY_INVERTED>;
+		};
+	};
+
+	cros-pwmleds {
+		compatible = "cros-ec,pwm-leds";
+
+		leds = <&pwm_led0>;
+
+				/*<red green blue>*/
+		color-map-red    = <100   0    0>;
+		color-map-green  = <  0 100    0>;
+		color-map-blue   = <  0   0  100>;
+		color-map-yellow = <  0  50   50>;
+		color-map-white  = <100 100  100>;
+		color-map-amber  = <100  15    0>;
+
+		brightness-range = <100 100 100 0 0 0>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pwm_led_0@0 {
+			reg = <0>;
+			ec-led-name = "EC_LED_ID_BATTERY_LED";
+		};
+	};
+};
+
+&pwm1 {
+	status = "okay";
+	prescaler-cx = <PWM_PRESCALER_C4>;
+	pinctrl-0 = <&pwm1_gpa1_default>;
+	pinctrl-names = "default";
+};
+
+&pwm2 {
+	status = "okay";
+	prescaler-cx = <PWM_PRESCALER_C4>;
+	pinctrl-0 = <&pwm2_gpa2_default>;
+	pinctrl-names = "default";
+};
+
+&pwm3 {
+	status = "okay";
+	prescaler-cx = <PWM_PRESCALER_C4>;
+	pinctrl-0 = <&pwm3_gpa3_default>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/nissa/gothrax/src/charger.c b/zephyr/program/nissa/gothrax/src/charger.c
new file mode 100644
index 0000000000..41931ee36f
--- /dev/null
+++ b/zephyr/program/nissa/gothrax/src/charger.c
@@ -0,0 +1,55 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "charger.h"
+#include "charger/isl923x_public.h"
+#include "console.h"
+#include "extpower.h"
+#include "usb_pd.h"
+
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+int extpower_is_present(void)
+{
+	int port;
+	int rv;
+	bool acok;
+
+	for (port = 0; port < board_get_usb_pd_port_count(); port++) {
+		rv = raa489000_is_acok(port, &acok);
+		if ((rv == EC_SUCCESS) && acok)
+			return 1;
+	}
+
+	return 0;
+}
+
+/*
+ * Nereid does not have a GPIO indicating whether extpower is present,
+ * so detect using the charger(s).
+ */
+__override void board_check_extpower(void)
+{
+	static int last_extpower_present;
+	int extpower_present = extpower_is_present();
+
+	if (last_extpower_present ^ extpower_present)
+		extpower_handle_update(extpower_present);
+
+	last_extpower_present = extpower_present;
+}
+
+__override void board_hibernate(void)
+{
+	/* Shut down the chargers */
+	if (board_get_usb_pd_port_count() == 2)
+		raa489000_hibernate(CHARGER_SECONDARY, true);
+	raa489000_hibernate(CHARGER_PRIMARY, true);
+	LOG_INF("Charger(s) hibernated");
+	cflush();
+}
diff --git a/zephyr/program/nissa/gothrax/src/fan.c b/zephyr/program/nissa/gothrax/src/fan.c
new file mode 100644
index 0000000000..bcdacf070c
--- /dev/null
+++ b/zephyr/program/nissa/gothrax/src/fan.c
@@ -0,0 +1,41 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cros_cbi.h"
+#include "fan.h"
+#include "gpio/gpio.h"
+#include "hooks.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+/*
+ * Joxer fan support
+ */
+static void fan_init(void)
+{
+	int ret;
+	uint32_t val;
+	/*
+	 * Retrieve the fan config.
+	 */
+	ret = cros_cbi_get_fw_config(FW_FAN, &val);
+	if (ret != 0) {
+		LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_FAN);
+		return;
+	}
+	if (val != FW_FAN_PRESENT) {
+		/* Disable the fan */
+		fan_set_count(0);
+	} else {
+		/* Configure the fan enable GPIO */
+		gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_fan_enable),
+				      GPIO_OUTPUT);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, fan_init, HOOK_PRIO_POST_FIRST);
diff --git a/zephyr/program/nissa/gothrax/src/hdmi.c b/zephyr/program/nissa/gothrax/src/hdmi.c
new file mode 100644
index 0000000000..5025472c6d
--- /dev/null
+++ b/zephyr/program/nissa/gothrax/src/hdmi.c
@@ -0,0 +1,29 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "nissa_hdmi.h"
+
+#include <cros_board_info.h>
+
+__override void nissa_configure_hdmi_power_gpios(void)
+{
+	/*
+	 * Nereid versions before 2 need hdmi-en-odl to be
+	 * pulled down to enable VCC on the HDMI port, but later
+	 * versions (and other boards) disconnect this so
+	 * the port's VCC directly follows en-rails-odl. Only
+	 * configure the GPIO if needed, to save power.
+	 */
+	uint32_t board_version = 0;
+
+	/* CBI errors ignored, will configure the pin */
+	cbi_get_board_version(&board_version);
+	if (board_version < 2) {
+		nissa_configure_hdmi_vcc();
+	}
+
+	/* Still always need core rails controlled */
+	nissa_configure_hdmi_rails();
+}
diff --git a/zephyr/program/nissa/gothrax/src/keyboard.c b/zephyr/program/nissa/gothrax/src/keyboard.c
new file mode 100644
index 0000000000..b453c9ea27
--- /dev/null
+++ b/zephyr/program/nissa/gothrax/src/keyboard.c
@@ -0,0 +1,29 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+
+static const struct ec_response_keybd_config gothrax_kb_legacy = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_FORWARD,		/* T2 */
+		TK_REFRESH,		/* T3 */
+		TK_FULLSCREEN,		/* T4 */
+		TK_OVERVIEW,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &gothrax_kb_legacy;
+}
diff --git a/zephyr/program/nissa/gothrax/src/usbc.c b/zephyr/program/nissa/gothrax/src/usbc.c
new file mode 100644
index 0000000000..5df3a09bb8
--- /dev/null
+++ b/zephyr/program/nissa/gothrax/src/usbc.c
@@ -0,0 +1,228 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_state.h"
+#include "chipset.h"
+#include "driver/charger/isl923x_public.h"
+#include "driver/retimer/anx7483_public.h"
+#include "driver/tcpm/raa489000.h"
+#include "driver/tcpm/tcpci.h"
+#include "hooks.h"
+#include "system.h"
+#include "usb_mux.h"
+
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+int board_is_sourcing_vbus(int port)
+{
+	int regval;
+
+	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
+	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int i;
+	int old_port;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	old_port = charge_manager_get_active_charge_port();
+
+	LOG_INF("New chg p%d", port);
+
+	/* Disable all ports. */
+	if (port == CHARGE_PORT_NONE) {
+		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+			tcpc_write(i, TCPC_REG_COMMAND,
+				   TCPC_REG_COMMAND_SNK_CTRL_LOW);
+			raa489000_enable_asgate(i, false);
+		}
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if port is sourcing VBUS. */
+	if (board_is_sourcing_vbus(port)) {
+		LOG_WRN("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		if (i == port)
+			continue;
+
+		if (tcpc_write(i, TCPC_REG_COMMAND,
+			       TCPC_REG_COMMAND_SNK_CTRL_LOW))
+			LOG_WRN("p%d: sink path disable failed.", i);
+		raa489000_enable_asgate(i, false);
+	}
+
+	/*
+	 * Stop the charger IC from switching while changing ports.  Otherwise,
+	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
+	 */
+	if (old_port != CHARGE_PORT_NONE)
+		charger_discharge_on_ac(1);
+
+	/* Enable requested charge port. */
+	if (raa489000_enable_asgate(port, true) ||
+	    tcpc_write(port, TCPC_REG_COMMAND,
+		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
+		LOG_WRN("p%d: sink path enable failed.", port);
+		charger_discharge_on_ac(0);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	/* Allow the charger IC to begin/continue switching. */
+	charger_discharge_on_ac(0);
+
+	return EC_SUCCESS;
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+	int regval;
+
+	/*
+	 * The interrupt line is shared between the TCPC and BC1.2 detector IC.
+	 * Therefore, go out and actually read the alert registers to report the
+	 * alert status.
+	 */
+	if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl))) {
+		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
+			/* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */
+			if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0))
+				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
+
+			if (regval)
+				status |= PD_STATUS_TCPC_ALERT_0;
+		}
+	}
+
+	if (board_get_usb_pd_port_count() == 2 &&
+	    !gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) {
+		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
+			/* TCPCI spec Rev 1.0 says to ignore bits 14:12. */
+			if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0))
+				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
+
+			if (regval)
+				status |= PD_STATUS_TCPC_ALERT_1;
+		}
+	}
+
+	return status;
+}
+
+void pd_power_supply_reset(int port)
+{
+	/* Disable VBUS */
+	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	if (port < 0 || port >= CONFIG_USB_PD_PORT_MAX_COUNT)
+		return;
+
+	raa489000_set_output_current(port, rp);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	if (port >= CONFIG_USB_PD_PORT_MAX_COUNT)
+		return EC_ERROR_INVAL;
+
+	/* Disable charging. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
+	if (rv)
+		return rv;
+
+	/* Our policy is not to source VBUS when the AP is off. */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	/* Provide Vbus. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
+	if (rv)
+		return rv;
+
+	rv = raa489000_enable_asgate(port, true);
+	if (rv)
+		return rv;
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * TODO(b:147316511): could send a reset command to the TCPC here
+	 * if needed.
+	 */
+}
+
+/*
+ * Because the TCPCs and BC1.2 chips share interrupt lines, it's possible
+ * for an interrupt to be lost if one asserts the IRQ, the other does the same
+ * then the first releases it: there will only be one falling edge to trigger
+ * the interrupt, and the line will be held low. We handle this by polling the
+ * IRQ GPIO on the USB-PD task after processing TCPC interrupts, synchronously
+ * running the BC1.2 interrupt handler to ensure we continue processing
+ * interrupts as long as either source is asserting the IRQ.
+ */
+void board_process_pd_alert(int port)
+{
+	const struct gpio_dt_spec *gpio;
+
+	if (port == 0) {
+		gpio = GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl);
+	} else {
+		gpio = GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl);
+	}
+
+	if (!gpio_pin_get_dt(gpio)) {
+		usb_charger_task_set_event_sync(port, USB_CHG_EVENT_BC12);
+	}
+
+	/*
+	 * Immediately schedule another TCPC interrupt if it seems we haven't
+	 * cleared all pending interrupts.
+	 */
+	if (!gpio_pin_get_dt(gpio))
+		schedule_deferred_pd_interrupt(port);
+}
+
+void usb_interrupt(enum gpio_signal signal)
+{
+	int port;
+
+	if (signal == GPIO_SIGNAL(DT_NODELABEL(gpio_usb_c0_int_odl))) {
+		port = 0;
+	} else {
+		port = 1;
+	}
+	/* Trigger polling of TCPC and BC1.2 in USB-PD task */
+	schedule_deferred_pd_interrupt(port);
+}
diff --git a/zephyr/program/nissa/include/nissa_common.h b/zephyr/program/nissa/include/nissa_common.h
new file mode 100644
index 0000000000..6dc59ba7f3
--- /dev/null
+++ b/zephyr/program/nissa/include/nissa_common.h
@@ -0,0 +1,24 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Nissa shared common functionality */
+
+#ifndef __CROS_EC_NISSA_NISSA_COMMON_H__
+#define __CROS_EC_NISSA_NISSA_COMMON_H__
+
+#include <ap_power/ap_power.h>
+
+/**
+ * Functions executed when AP power change.
+ *
+ * This function is called from shared common code of nissa.
+ *
+ * A board should override this function if it has different functions
+ * need to be executed when AP power change.
+ */
+__override_proto void board_power_change(struct ap_power_ev_callback *,
+					 struct ap_power_ev_data);
+
+#endif /* __CROS_EC_NISSA_NISSA_COMMON_H__ */
diff --git a/zephyr/program/nissa/include/nissa_hdmi.h b/zephyr/program/nissa/include/nissa_hdmi.h
new file mode 100644
index 0000000000..9f2f533ba7
--- /dev/null
+++ b/zephyr/program/nissa/include/nissa_hdmi.h
@@ -0,0 +1,55 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Nissa shared HDMI sub-board functionality */
+
+#ifndef __CROS_EC_NISSA_NISSA_HDMI_H__
+#define __CROS_EC_NISSA_NISSA_HDMI_H__
+
+#include "common.h"
+
+/** True if the board supports an HDMI sub-board. */
+#define NISSA_BOARD_HAS_HDMI_SUPPORT DT_NODE_EXISTS(DT_NODELABEL(gpio_hdmi_sel))
+
+/**
+ * Configure the GPIO that controls core rails on the HDMI sub-board.
+ *
+ * This is the gpio_en_rails_odl pin, which is configured as active-low
+ * open-drain output to enable power to the HDMI sub-board (typically when the
+ * AP is in S5 or above).
+ *
+ * This function must be called if the pin is connected to the HDMI board and
+ * power is not enabled by default.
+ */
+void nissa_configure_hdmi_rails(void);
+
+/**
+ * Configure the GPIO that controls the HDMI VCC pin on the HDMI sub-board.
+ *
+ * This is the gpio_hdmi_en_odl pin, which is configured as active-low
+ * open-drain output to enable the VCC pin on the HDMI connector (typically when
+ * the AP is on, in S0 or S0ix).
+ *
+ * This function must be called if the pin is connected to the HDMI board and
+ * VCC is not enabled by default.
+ */
+void nissa_configure_hdmi_vcc(void);
+
+/**
+ * Configure the GPIOS controlling HDMI sub-board power (core rails and VCC).
+ *
+ * This function is called from shared code while configuring sub-boards, and
+ * used if an HDMI sub-board is present. The default implementation enables the
+ * core rails control pin (nissa_configure_hdmi_rails) but not VCC
+ * (nissa_configure_hdmi_vcc), assuming that the pin for VCC is not connected
+ * connected on most boards (and that VCC will be turned on whenever the core
+ * rails are turned on).
+ *
+ * A board should override this function if it needs to enable more IOs for
+ * HDMI, or if some pins need to be conditionally enabled.
+ */
+__override_proto void nissa_configure_hdmi_power_gpios(void);
+
+#endif /* __CROS_EC_NISSA_NISSA_HDMI_H__ */
diff --git a/zephyr/program/nissa/include/nissa_sub_board.h b/zephyr/program/nissa/include/nissa_sub_board.h
new file mode 100644
index 0000000000..572bf7fc69
--- /dev/null
+++ b/zephyr/program/nissa/include/nissa_sub_board.h
@@ -0,0 +1,21 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Nissa sub-board declarations */
+
+#ifndef __CROS_EC_NISSA_NISSA_SUB_BOARD_H__
+#define __CROS_EC_NISSA_NISSA_SUB_BOARD_H__
+
+enum nissa_sub_board_type {
+	NISSA_SB_UNKNOWN = -1, /* Uninitialised */
+	NISSA_SB_NONE = 0, /* No board defined */
+	NISSA_SB_C_A = 1, /* USB type C, USB type A */
+	NISSA_SB_C_LTE = 2, /* USB type C, WWAN LTE */
+	NISSA_SB_HDMI_A = 3, /* HDMI, USB type A */
+};
+
+enum nissa_sub_board_type nissa_get_sb_type(void);
+
+#endif /* __CROS_EC_NISSA_NISSA_SUB_BOARD_H__ */
diff --git a/zephyr/program/nissa/include/uldren_sub_board.h b/zephyr/program/nissa/include/uldren_sub_board.h
new file mode 100644
index 0000000000..e15e5aabe5
--- /dev/null
+++ b/zephyr/program/nissa/include/uldren_sub_board.h
@@ -0,0 +1,20 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Uldren sub-board declarations */
+
+#ifndef __CROS_EC_NISSA_NISSA_SUB_BOARD_H__
+#define __CROS_EC_NISSA_NISSA_SUB_BOARD_H__
+
+enum uldren_sub_board_type {
+	ULDREN_SB_UNKNOWN = -1, /* Uninitialised */
+	ULDREN_SB_NONE = 0, /* No board defined */
+	ULDREN_SB_C = 1, /* USB type C only */
+	ULDREN_SB_C_LTE = 2, /* USB type C, WWAN LTE */
+};
+
+enum uldren_sub_board_type uldren_get_sb_type(void);
+
+#endif /* __CROS_EC_NISSA_NISSA_SUB_BOARD_H__ */
diff --git a/zephyr/program/nissa/it8xxx2_program.conf b/zephyr/program/nissa/it8xxx2_program.conf
new file mode 100644
index 0000000000..e49c7595ac
--- /dev/null
+++ b/zephyr/program/nissa/it8xxx2_program.conf
@@ -0,0 +1,56 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_CROS_FLASH_IT8XXX2=y
+CONFIG_CROS_SYSTEM_IT8XXX2=y
+CONFIG_ESPI_IT8XXX2=y
+CONFIG_FPU=y
+# rv32iafc/ilp32f is not supported by the toolchain, so use soft-float
+CONFIG_FLOAT_HARD=n
+
+# EC performance is bad; limiting sensor data rate helps keep it from degrading
+# so much that it causes problems. b/240485526, b/230818312
+CONFIG_PLATFORM_EC_MAX_SENSOR_FREQ_MILLIHZ=100000
+
+# Allow more time for the charger to stabilise
+CONFIG_PLATFORM_EC_POWER_BUTTON_INIT_TIMEOUT=5
+
+# ITE has more space, so don't restrict shell
+CONFIG_SHELL_MINIMAL=n
+
+# RAM savings, since this chip is tight on available RAM.
+# It's useful to store a lot of logs for the host to request, but the default 4k
+# is pretty large.
+CONFIG_PLATFORM_EC_HOSTCMD_CONSOLE_BUF_SIZE=2048
+# Our threads have short names, save 20 bytes per thread
+CONFIG_THREAD_MAX_NAME_LEN=12
+# Task stacks, tuned by experiment. Most expanded to prevent overflow, and a few
+# shrunk to save RAM.
+CONFIG_AP_PWRSEQ_STACK_SIZE=1408
+CONFIG_TASK_HOSTCMD_STACK_SIZE=1280
+CONFIG_TASK_MOTIONSENSE_STACK_SIZE=1280
+CONFIG_TASK_PD_INT_STACK_SIZE=1280
+
+# TCPC+PPC: ITE on-chip for C0, PS8745 for optional C1
+CONFIG_PLATFORM_EC_USB_PD_TCPM_DRIVER_IT8XXX2=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8745=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_CHARGER=y
+# SM5803 controls power path on both ports
+CONFIG_PLATFORM_EC_USB_PD_5V_CHARGER_CTRL=y
+# SM5803 can discharge VBUS, but not via one of the available options;
+# pd_power_supply_reset() does discharge.
+CONFIG_PLATFORM_EC_USB_PD_DISCHARGE=n
+
+# Charger driver and configuration
+CONFIG_PLATFORM_EC_OCPC=y
+CONFIG_PLATFORM_EC_CHARGER_SM5803=y
+CONFIG_PLATFORM_EC_OCPC_DEF_RBATT_MOHMS=21
+CONFIG_PLATFORM_EC_PD_MAX_VOLTAGE_MV=15000
+# SM5803 is very inefficient in buck-boost operation, so DPS doesn't help and
+# might actually contribute to charger failures.
+CONFIG_PLATFORM_EC_USB_PD_DPS=n
+
+# VSENSE
+CONFIG_VCMP_IT8XXX2_WORKQUEUE=y
+CONFIG_VCMP_IT8XXX2_WORKQUEUE_PRIORITY=12
diff --git a/zephyr/program/nissa/it8xxx2cx_program.conf b/zephyr/program/nissa/it8xxx2cx_program.conf
new file mode 100644
index 0000000000..4e2e811729
--- /dev/null
+++ b/zephyr/program/nissa/it8xxx2cx_program.conf
@@ -0,0 +1,15 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# IT8xxx2 CX targets rv32imafc whereas BX needs to target rv32iafc due to a CPU
+# bug. The toolchain provides library support for these targets:
+#
+#  * rv32iac/ilp32
+#  * rv32iafc/ilp32 (alias to iac/ilp32)
+#  * rv32imafc/ilp32f
+#
+# ..so when targeting -imafc for the CX chip, we need to use the hard-float ABI
+# to prevent ABI mismatches against libgcc whereas BX must use soft-float for
+# the same reason.
+CONFIG_FLOAT_HARD=y
diff --git a/zephyr/program/nissa/joxer/cbi.dtsi b/zephyr/program/nissa/joxer/cbi.dtsi
new file mode 100644
index 0000000000..71424ed681
--- /dev/null
+++ b/zephyr/program/nissa/joxer/cbi.dtsi
@@ -0,0 +1,53 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	nissa-fw-config {
+		compatible = "cros-ec,cbi-fw-config";
+
+		/*
+		 * FW_CONFIG field to indicate which keyboard layout
+		 * should be used.
+		 */
+		keyboard {
+			enum-name = "FW_KB_LAYOUT";
+			start = <3>;
+			size = <2>;
+
+			layout-1 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_KB_LAYOUT_DEFAULT";
+				value = <0>;
+				default;
+			};
+			layout-2 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_KB_LAYOUT_US2";
+				value = <1>;
+			};
+		};
+
+		/*
+		 * FW_CONFIG field to describe lid accelerometer orientation.
+		 */
+		lid-inversion {
+			enum-name = "FW_LID_INVERSION";
+			start = <5>;
+			size = <1>;
+
+			default {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "SENSOR_DEFAULT";
+				value = <0>;
+				default;
+			};
+			inverted {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "SENSOR_INVERTED";
+				value = <1>;
+			};
+		};
+	};
+};
diff --git a/zephyr/program/nissa/joxer/generated.dtsi b/zephyr/program/nissa/joxer/generated.dtsi
new file mode 100644
index 0000000000..a1283850c6
--- /dev/null
+++ b/zephyr/program/nissa/joxer/generated.dtsi
@@ -0,0 +1,253 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * This file is auto-generated - do not edit!
+ */
+
+/ {
+
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc {
+			enum-name = "ADC_PP1050_PROC";
+			io-channels = <&adc0 14>;
+		};
+		adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 {
+			enum-name = "ADC_PP3300_S5";
+			io-channels = <&adc0 0>;
+		};
+		adc_temp_sensor_1: temp_sensor_1 {
+			enum-name = "ADC_TEMP_SENSOR_1";
+			io-channels = <&adc0 2>;
+		};
+		adc_temp_sensor_2: temp_sensor_2 {
+			enum-name = "ADC_TEMP_SENSOR_2";
+			io-channels = <&adc0 3>;
+		};
+		adc_temp_sensor_3: temp_sensor_3 {
+			enum-name = "ADC_TEMP_SENSOR_3";
+			io-channels = <&adc0 13>;
+		};
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		gpio_acc_int_l: acc_int_l {
+			gpios = <&gpioc 0 GPIO_INPUT>;
+		};
+		gpio_all_sys_pwrgd: all_sys_pwrgd {
+			gpios = <&gpiob 7 GPIO_INPUT>;
+		};
+		gpio_ccd_mode_odl: ccd_mode_odl {
+			gpios = <&gpioh 5 GPIO_INPUT>;
+			enum-name = "GPIO_CCD_MODE_ODL";
+		};
+		gpio_cpu_c10_gate_l: cpu_c10_gate_l {
+			gpios = <&gpiog 1 GPIO_INPUT>;
+		};
+		gpio_ec_battery_pres_odl: ec_battery_pres_odl {
+			gpios = <&gpioi 4 GPIO_INPUT>;
+			enum-name = "GPIO_BATT_PRES_ODL";
+		};
+		gpio_ec_cbi_wp: ec_cbi_wp {
+			gpios = <&gpioj 5 GPIO_OUTPUT>;
+		};
+		gpio_ec_edp_bl_en_od: ec_edp_bl_en_od {
+			gpios = <&gpiok 4 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_ENABLE_BACKLIGHT";
+		};
+		gpio_ec_entering_rw: ec_entering_rw {
+			gpios = <&gpioc 7 GPIO_OUTPUT>;
+			enum-name = "GPIO_ENTERING_RW";
+		};
+		gpio_ec_gsc_packet_mode: ec_gsc_packet_mode {
+			gpios = <&gpioh 1 GPIO_OUTPUT>;
+			enum-name = "GPIO_PACKET_MODE_EN";
+		};
+		gpio_ec_pch_wake_odl: ec_pch_wake_odl {
+			gpios = <&gpiob 2 GPIO_ODR_LOW>;
+		};
+		gpio_ec_prochot_odl: ec_prochot_odl {
+			gpios = <&gpioi 1 GPIO_ODR_HIGH>;
+		};
+		gpio_ec_soc_dsw_pwrok: ec_soc_dsw_pwrok {
+			gpios = <&gpiol 7 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_int_odl: ec_soc_int_odl {
+			gpios = <&gpiod 5 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_EC_INT_L";
+		};
+		gpio_ec_soc_pch_pwrok_od: ec_soc_pch_pwrok_od {
+			gpios = <&gpiod 6 GPIO_ODR_HIGH>;
+		};
+		gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl {
+			gpios = <&gpiob 6 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_PCH_PWRBTN_L";
+		};
+		gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l {
+			gpios = <&gpioh 0 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_rtcrst: ec_soc_rtcrst {
+			gpios = <&gpiok 2 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_sys_pwrok: ec_soc_sys_pwrok {
+			gpios = <&gpiof 2 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_vccst_pwrgd_od: ec_soc_vccst_pwrgd_od {
+			gpios = <&gpioe 5 GPIO_ODR_HIGH>;
+		};
+		gpio_ec_wp_odl: ec_wp_odl {
+			gpios = <&gpioa 6 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_en_kb_bl: en_kb_bl {
+			gpios = <&gpioj 3 GPIO_OUTPUT>;
+			enum-name = "GPIO_EN_KEYBOARD_BACKLIGHT";
+		};
+		gpio_en_pp3300_s5: en_pp3300_s5 {
+			gpios = <&gpioc 5 GPIO_OUTPUT>;
+			enum-name = "GPIO_TEMP_SENSOR_POWER";
+		};
+		gpio_en_pp5000_pen_x: en_pp5000_pen_x {
+			gpios = <&gpiob 5 GPIO_OUTPUT>;
+		};
+		gpio_en_pp5000_s5: en_pp5000_s5 {
+			gpios = <&gpiok 5 GPIO_OUTPUT>;
+		};
+		gpio_en_slp_z: en_slp_z {
+			gpios = <&gpiok 3 GPIO_OUTPUT>;
+		};
+		gpio_en_usb_a0_vbus: en_usb_a0_vbus {
+			gpios = <&gpiol 6 GPIO_OUTPUT>;
+		};
+		gpio_en_usb_c0_cc1_vconn: en_usb_c0_cc1_vconn {
+			gpios = <&gpioh 4 GPIO_OUTPUT>;
+		};
+		gpio_en_usb_c0_cc2_vconn: en_usb_c0_cc2_vconn {
+			gpios = <&gpioh 6 GPIO_OUTPUT>;
+		};
+		gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl {
+			gpios = <&gpioe 2 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		gpio_imu_int_l: imu_int_l {
+			gpios = <&gpioj 0 GPIO_INPUT>;
+		};
+		gpio_imvp91_vrrdy_od: imvp91_vrrdy_od {
+			gpios = <&gpioj 4 GPIO_INPUT>;
+		};
+		gpio_lid_open: lid_open {
+			gpios = <&gpiof 3 GPIO_INPUT>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+		gpio_pen_detect_odl: pen_detect_odl {
+			gpios = <&gpioj 1 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_pg_pp1050_mem_s3_od: pg_pp1050_mem_s3_od {
+			gpios = <&gpiod 3 GPIO_INPUT>;
+		};
+		gpio_pg_pp5000_s5_od: pg_pp5000_s5_od {
+			gpios = <&gpioe 3 GPIO_INPUT>;
+		};
+		gpio_rsmrst_pwrgd_l: rsmrst_pwrgd_l {
+			gpios = <&gpioe 1 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_slp_s0_l: slp_s0_l {
+			gpios = <&gpioe 4 GPIO_INPUT>;
+		};
+		gpio_slp_s3_l: slp_s3_l {
+			gpios = <&gpioh 3 GPIO_INPUT>;
+		};
+		gpio_slp_s4_l: slp_s4_l {
+			gpios = <&gpioi 5 GPIO_INPUT>;
+		};
+		gpio_slp_sus_l: slp_sus_l {
+			gpios = <&gpiog 2 GPIO_INPUT>;
+		};
+		gpio_sys_rst_odl: sys_rst_odl {
+			gpios = <&gpiod 1 GPIO_ODR_HIGH>;
+		};
+		gpio_tablet_mode_l: tablet_mode_l {
+			gpios = <&gpioj 7 GPIO_INPUT>;
+			enum-name = "GPIO_TABLET_MODE_L";
+		};
+		gpio_usb_a0_ilimit_sdp: usb_a0_ilimit_sdp {
+			gpios = <&gpiol 5 GPIO_OUTPUT>;
+			enum-name = "GPIO_USB1_ILIM_SEL";
+		};
+		gpio_usb_c0_frs: usb_c0_frs {
+			gpios = <&gpioc 4 GPIO_OUTPUT>;
+		};
+		gpio_usb_c0_int_odl: usb_c0_int_odl {
+			gpios = <&gpiok 0 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_vccin_aux_vid0: vccin_aux_vid0 {
+			gpios = <&gpiod 0 GPIO_INPUT>;
+		};
+		gpio_vccin_aux_vid1: vccin_aux_vid1 {
+			gpios = <&gpiok 1 GPIO_INPUT>;
+		};
+		gpio_voldn_btn_odl: voldn_btn_odl {
+			gpios = <&gpioi 6 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_DOWN_L";
+		};
+		gpio_volup_btn_odl: volup_btn_odl {
+			gpios = <&gpioi 7 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_UP_L";
+		};
+		gpio_usb_c1_int_odl: usb_c1_int_odl {
+			gpios = <&gpioe 6 GPIO_INPUT_PULL_UP>;
+		};
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		i2c_ec_i2c_eeprom: ec_i2c_eeprom {
+			i2c-port = <&i2c0>;
+			enum-names = "I2C_PORT_EEPROM";
+		};
+		i2c_ec_i2c_batt: ec_i2c_batt {
+			i2c-port = <&i2c1>;
+			enum-names = "I2C_PORT_BATTERY";
+		};
+		i2c_ec_i2c_sensor: ec_i2c_sensor {
+			i2c-port = <&i2c2>;
+			enum-names = "I2C_PORT_SENSOR";
+		};
+		i2c_ec_i2c_sub_usb_c1: ec_i2c_sub_usb_c1 {
+			i2c-port = <&i2c4>;
+			enum-names = "I2C_PORT_USB_C1_TCPC";
+		};
+		i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 {
+			i2c-port = <&i2c5>;
+			enum-names = "I2C_PORT_USB_C0_TCPC";
+		};
+	};
+};
+
+&adc0 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+};
+
+&i2c2 {
+	status = "okay";
+};
+
+&i2c4 {
+	status = "okay";
+};
+
+&i2c5 {
+	status = "okay";
+};
diff --git a/zephyr/program/nissa/joxer/joxer_vif.xml b/zephyr/program/nissa/joxer/joxer_vif.xml
new file mode 100644
index 0000000000..09a9ae56ba
--- /dev/null
+++ b/zephyr/program/nissa/joxer/joxer_vif.xml
@@ -0,0 +1,338 @@
+<?xml version="1.0" encoding="utf-8"?>
+<vif:VIF xmlns:opt="http://usb.org/VendorInfoFileOptionalContent.xsd" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:vif="http://usb.org/VendorInfoFile.xsd">
+  <vif:VIF_Specification>3.26</vif:VIF_Specification>
+  <vif:VIF_App>
+    <vif:Vendor>USB-IF</vif:Vendor>
+    <vif:Name>VIF Editor</vif:Name>
+    <vif:Version>3.4.6.0</vif:Version>
+  </vif:VIF_App>
+  <vif:Vendor_Name>Google</vif:Vendor_Name>
+  <vif:Model_Part_Number>Joxer</vif:Model_Part_Number>
+  <vif:Product_Revision>1</vif:Product_Revision>
+  <vif:TID>0</vif:TID>
+  <vif:VIF_Product_Type value="0">Port Product</vif:VIF_Product_Type>
+  <vif:Certification_Type value="1">Reference Platform</vif:Certification_Type>
+  <vif:Product>
+    <!--Product Level Content:-->
+  </vif:Product>
+  <vif:Component>
+    <!--Component 0: Port 0-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Component-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Port_Label>0</vif:Port_Label>
+    <vif:Connector_Type value="2">Type-C®</vif:Connector_Type>
+    <vif:USB4_Supported value="false" />
+    <vif:USB_PD_Support value="true" />
+    <vif:PD_Port_Type value="4">DRP</vif:PD_Port_Type>
+    <vif:Type_C_State_Machine value="2">DRP</vif:Type_C_State_Machine>
+    <vif:Port_Battery_Powered value="true" />
+    <vif:BC_1_2_Support value="0">None</vif:BC_1_2_Support>
+    <vif:Captive_Cable value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;General PD-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Spec_Revision_Major value="3">3</vif:PD_Spec_Revision_Major>
+    <vif:PD_Spec_Revision_Minor value="1">1</vif:PD_Spec_Revision_Minor>
+    <vif:PD_Spec_Version_Major value="1">1</vif:PD_Spec_Version_Major>
+    <vif:PD_Spec_Version_Minor value="3">3</vif:PD_Spec_Version_Minor>
+    <vif:PD_Specification_Revision value="2">Revision 3</vif:PD_Specification_Revision>
+    <vif:SOP_Capable value="true" />
+    <vif:SOP_P_Capable value="true" />
+    <vif:SOP_PP_Capable value="true" />
+    <vif:SOP_P_Debug_Capable value="false" />
+    <vif:SOP_PP_Debug_Capable value="false" />
+    <vif:Manufacturer_Info_Supported_Port value="false" />
+    <vif:Chunking_Implemented_SOP value="true" />
+    <vif:Unchunked_Extended_Messages_Supported value="false" />
+    <vif:Security_Msgs_Supported_SOP value="false" />
+    <vif:Unconstrained_Power value="false" />
+    <vif:Num_Fixed_Batteries value="1">1</vif:Num_Fixed_Batteries>
+    <vif:Num_Swappable_Battery_Slots value="1">1</vif:Num_Swappable_Battery_Slots>
+    <vif:ID_Header_Connector_Type_SOP value="2">USB Type-C® Receptacle</vif:ID_Header_Connector_Type_SOP>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Capabilities-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:USB_Comms_Capable value="true" />
+    <vif:DR_Swap_To_DFP_Supported value="true" />
+    <vif:DR_Swap_To_UFP_Supported value="false" />
+    <vif:VCONN_Swap_To_On_Supported value="true" />
+    <vif:VCONN_Swap_To_Off_Supported value="true" />
+    <vif:Responds_To_Discov_SOP_UFP value="false" />
+    <vif:Responds_To_Discov_SOP_DFP value="true" />
+    <vif:Attempts_Discov_SOP value="true" />
+    <vif:Power_Interruption_Available value="0">No Interruption Possible</vif:Power_Interruption_Available>
+    <vif:Data_Reset_Supported value="false" />
+    <vif:Enter_USB_Supported value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;USB Type-C®-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Type_C_Can_Act_As_Host value="true" />
+    <vif:Type_C_Can_Act_As_Device value="false" />
+    <vif:Type_C_Implements_Try_SRC value="true" />
+    <vif:Type_C_Implements_Try_SNK value="false" />
+    <vif:Type_C_Supports_Audio_Accessory value="false" />
+    <vif:Type_C_Is_VCONN_Powered_Accessory value="false" />
+    <vif:Type_C_Is_Debug_Target_SRC value="true" />
+    <vif:Type_C_Is_Debug_Target_SNK value="true" />
+    <vif:RP_Value value="1">1.5A</vif:RP_Value>
+    <vif:Type_C_Port_On_Hub value="false" />
+    <vif:Type_C_Power_Source value="2">Both</vif:Type_C_Power_Source>
+    <vif:Type_C_Sources_VCONN value="true" />
+    <vif:Type_C_Is_Alt_Mode_Controller value="true" />
+    <vif:Type_C_Is_Alt_Mode_Adapter value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Product Power-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Product_Total_Source_Power_mW value="15000">15000 mW</vif:Product_Total_Source_Power_mW>
+    <vif:Port_Source_Power_Type value="0">Assured</vif:Port_Source_Power_Type>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;USB Host-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Host_Supports_USB_Data value="true" />
+    <vif:Host_Speed value="1">USB 3.2 Gen 1x1</vif:Host_Speed>
+    <vif:Host_Contains_Captive_Retimer value="false" />
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:Host_Is_Embedded value="false" />
+    <vif:Host_Suspend_Supported value="true" />
+    <vif:Is_DFP_On_Hub value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Source-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Power_As_Source value="15000">15000 mW</vif:PD_Power_As_Source>
+    <vif:EPR_Supported_As_Src value="false" />
+    <vif:USB_Suspend_May_Be_Cleared value="false" />
+    <vif:Sends_Pings value="false" />
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="0">FR_Swap not supported</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <vif:Master_Port value="false" />
+    <vif:Num_Src_PDOs value="1">1 Src PDO</vif:Num_Src_PDOs>
+    <vif:PD_OC_Protection value="true" />
+    <vif:PD_OCP_Method value="0">Over-Current Response</vif:PD_OCP_Method>
+    <!--Bundle: SrcPdoList-->
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!--Source PDO 1-->
+        <vif:Src_PDO_Supply_Type value="0">Fixed</vif:Src_PDO_Supply_Type>
+        <vif:Src_PDO_Peak_Current value="0">100% IOC</vif:Src_PDO_Peak_Current>
+        <vif:Src_PDO_Voltage value="100">5000 mV (Factor = 50, saved to 100)</vif:Src_PDO_Voltage>
+        <vif:Src_PDO_Max_Current value="300">3000 mA (Factor = 10, saved to 300)</vif:Src_PDO_Max_Current>
+        <vif:Src_PD_OCP_OC_Debounce value="0">0 msec</vif:Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="300">3000 mA (Factor = 10, saved to 300)</vif:Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Sink-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Power_As_Sink value="45000">45000 mW</vif:PD_Power_As_Sink>
+    <vif:EPR_Supported_As_Snk value="false" />
+    <vif:No_USB_Suspend_May_Be_Set value="true" />
+    <vif:GiveBack_May_Be_Set value="false" />
+    <vif:Higher_Capability_Set value="false" />
+    <vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source value="0">FR_Swap not supported</vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source>
+    <vif:Num_Snk_PDOs value="3">3 Snk PDOs</vif:Num_Snk_PDOs>
+    <!--Bundle: SnkPdoList-->
+    <vif:SnkPdoList>
+      <vif:SnkPDO>
+        <!--Sink PDO 1-->
+        <vif:Snk_PDO_Supply_Type value="0">Fixed</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Voltage value="100">5000 mV (Factor = 50, saved to 100)</vif:Snk_PDO_Voltage>
+        <vif:Snk_PDO_Op_Current value="300">3000 mA (Factor = 10, saved to 300)</vif:Snk_PDO_Op_Current>
+      </vif:SnkPDO>
+      <vif:SnkPDO>
+        <!--Sink PDO 2-->
+        <vif:Snk_PDO_Supply_Type value="1">Battery</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Op_Power value="60">15000 mW (Factor = 250, saved to 60)</vif:Snk_PDO_Op_Power>
+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV (Factor = 50, saved to 95)</vif:Snk_PDO_Min_Voltage>
+        <vif:Snk_PDO_Max_Voltage value="300">15000 mV (Factor = 50, saved to 300)</vif:Snk_PDO_Max_Voltage>
+      </vif:SnkPDO>
+      <vif:SnkPDO>
+        <!--Sink PDO 3-->
+        <vif:Snk_PDO_Supply_Type value="2">Variable</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV (Factor = 50, saved to 95)</vif:Snk_PDO_Min_Voltage>
+        <vif:Snk_PDO_Max_Voltage value="300">15000 mV (Factor = 50, saved to 300)</vif:Snk_PDO_Max_Voltage>
+        <vif:Snk_PDO_Op_Current value="300">3000 mA (Factor = 10, saved to 300)</vif:Snk_PDO_Op_Current>
+      </vif:SnkPDO>
+    </vif:SnkPdoList>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Dual Role-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Accepts_PR_Swap_As_Src value="true" />
+    <vif:Accepts_PR_Swap_As_Snk value="true" />
+    <vif:Requests_PR_Swap_As_Src value="true" />
+    <vif:Requests_PR_Swap_As_Snk value="true" />
+    <vif:FR_Swap_Supported_As_Initial_Sink value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;SOP Discover ID-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:XID_SOP value="0">0</vif:XID_SOP>
+    <vif:Data_Capable_As_USB_Host_SOP value="true" />
+    <vif:Data_Capable_As_USB_Device_SOP value="false" />
+    <vif:Product_Type_UFP_SOP value="0">Undefined</vif:Product_Type_UFP_SOP>
+    <vif:Product_Type_DFP_SOP value="2">PDUSB Host</vif:Product_Type_DFP_SOP>
+    <vif:DFP_VDO_Port_Number value="0">0</vif:DFP_VDO_Port_Number>
+    <vif:Modal_Operation_Supported_SOP value="false" />
+    <vif:USB_VID_SOP value="6353">18D1</vif:USB_VID_SOP>
+    <vif:PID_SOP value="20570">505A</vif:PID_SOP>
+    <vif:bcdDevice_SOP value="0">0000</vif:bcdDevice_SOP>
+  </vif:Component>
+  <vif:Component>
+    <!--Component 1: Port 1-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Component-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Port_Label>1</vif:Port_Label>
+    <vif:Connector_Type value="2">Type-C®</vif:Connector_Type>
+    <vif:USB4_Supported value="false" />
+    <vif:USB_PD_Support value="true" />
+    <vif:PD_Port_Type value="4">DRP</vif:PD_Port_Type>
+    <vif:Type_C_State_Machine value="2">DRP</vif:Type_C_State_Machine>
+    <vif:Port_Battery_Powered value="true" />
+    <vif:BC_1_2_Support value="0">None</vif:BC_1_2_Support>
+    <vif:Captive_Cable value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;General PD-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Spec_Revision_Major value="3">3</vif:PD_Spec_Revision_Major>
+    <vif:PD_Spec_Revision_Minor value="1">1</vif:PD_Spec_Revision_Minor>
+    <vif:PD_Spec_Version_Major value="1">1</vif:PD_Spec_Version_Major>
+    <vif:PD_Spec_Version_Minor value="3">3</vif:PD_Spec_Version_Minor>
+    <vif:PD_Specification_Revision value="2">Revision 3</vif:PD_Specification_Revision>
+    <vif:SOP_Capable value="true" />
+    <vif:SOP_P_Capable value="true" />
+    <vif:SOP_PP_Capable value="true" />
+    <vif:SOP_P_Debug_Capable value="false" />
+    <vif:SOP_PP_Debug_Capable value="false" />
+    <vif:Manufacturer_Info_Supported_Port value="false" />
+    <vif:Chunking_Implemented_SOP value="true" />
+    <vif:Unchunked_Extended_Messages_Supported value="false" />
+    <vif:Security_Msgs_Supported_SOP value="false" />
+    <vif:Unconstrained_Power value="false" />
+    <vif:Num_Fixed_Batteries value="1">1</vif:Num_Fixed_Batteries>
+    <vif:Num_Swappable_Battery_Slots value="1">1</vif:Num_Swappable_Battery_Slots>
+    <vif:ID_Header_Connector_Type_SOP value="2">USB Type-C® Receptacle</vif:ID_Header_Connector_Type_SOP>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Capabilities-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:USB_Comms_Capable value="true" />
+    <vif:DR_Swap_To_DFP_Supported value="true" />
+    <vif:DR_Swap_To_UFP_Supported value="false" />
+    <vif:VCONN_Swap_To_On_Supported value="true" />
+    <vif:VCONN_Swap_To_Off_Supported value="true" />
+    <vif:Responds_To_Discov_SOP_UFP value="false" />
+    <vif:Responds_To_Discov_SOP_DFP value="true" />
+    <vif:Attempts_Discov_SOP value="true" />
+    <vif:Power_Interruption_Available value="0">No Interruption Possible</vif:Power_Interruption_Available>
+    <vif:Data_Reset_Supported value="false" />
+    <vif:Enter_USB_Supported value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;USB Type-C®-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Type_C_Can_Act_As_Host value="true" />
+    <vif:Type_C_Can_Act_As_Device value="false" />
+    <vif:Type_C_Implements_Try_SRC value="true" />
+    <vif:Type_C_Implements_Try_SNK value="false" />
+    <vif:Type_C_Supports_Audio_Accessory value="false" />
+    <vif:Type_C_Is_VCONN_Powered_Accessory value="false" />
+    <vif:Type_C_Is_Debug_Target_SRC value="true" />
+    <vif:Type_C_Is_Debug_Target_SNK value="true" />
+    <vif:RP_Value value="1">1.5A</vif:RP_Value>
+    <vif:Type_C_Port_On_Hub value="false" />
+    <vif:Type_C_Power_Source value="2">Both</vif:Type_C_Power_Source>
+    <vif:Type_C_Sources_VCONN value="true" />
+    <vif:Type_C_Is_Alt_Mode_Controller value="true" />
+    <vif:Type_C_Is_Alt_Mode_Adapter value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Product Power-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Product_Total_Source_Power_mW value="15000">15000 mW</vif:Product_Total_Source_Power_mW>
+    <vif:Port_Source_Power_Type value="0">Assured</vif:Port_Source_Power_Type>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;USB Host-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Host_Supports_USB_Data value="true" />
+    <vif:Host_Speed value="1">USB 3.2 Gen 1x1</vif:Host_Speed>
+    <vif:Host_Contains_Captive_Retimer value="true" />
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:Host_Is_Embedded value="false" />
+    <vif:Host_Suspend_Supported value="true" />
+    <vif:Is_DFP_On_Hub value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Source-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Power_As_Source value="15000">15000 mW</vif:PD_Power_As_Source>
+    <vif:EPR_Supported_As_Src value="false" />
+    <vif:USB_Suspend_May_Be_Cleared value="false" />
+    <vif:Sends_Pings value="false" />
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="0">FR_Swap not supported</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <vif:Master_Port value="false" />
+    <vif:Num_Src_PDOs value="1">1 Src PDO</vif:Num_Src_PDOs>
+    <vif:PD_OC_Protection value="true" />
+    <vif:PD_OCP_Method value="0">Over-Current Response</vif:PD_OCP_Method>
+    <!--Bundle: SrcPdoList-->
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!--Source PDO 1-->
+        <vif:Src_PDO_Supply_Type value="0">Fixed</vif:Src_PDO_Supply_Type>
+        <vif:Src_PDO_Peak_Current value="0">100% IOC</vif:Src_PDO_Peak_Current>
+        <vif:Src_PDO_Voltage value="100">5000 mV (Factor = 50, saved to 100)</vif:Src_PDO_Voltage>
+        <vif:Src_PDO_Max_Current value="300">3000 mA (Factor = 10, saved to 300)</vif:Src_PDO_Max_Current>
+        <vif:Src_PD_OCP_OC_Debounce value="0">0 msec</vif:Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="300">3000 mA (Factor = 10, saved to 300)</vif:Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Sink-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Power_As_Sink value="45000">45000 mW</vif:PD_Power_As_Sink>
+    <vif:EPR_Supported_As_Snk value="false" />
+    <vif:No_USB_Suspend_May_Be_Set value="true" />
+    <vif:GiveBack_May_Be_Set value="false" />
+    <vif:Higher_Capability_Set value="false" />
+    <vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source value="0">FR_Swap not supported</vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source>
+    <vif:Num_Snk_PDOs value="3">3 Snk PDOs</vif:Num_Snk_PDOs>
+    <!--Bundle: SnkPdoList-->
+    <vif:SnkPdoList>
+      <vif:SnkPDO>
+        <!--Sink PDO 1-->
+        <vif:Snk_PDO_Supply_Type value="0">Fixed</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Voltage value="100">5000 mV (Factor = 50, saved to 100)</vif:Snk_PDO_Voltage>
+        <vif:Snk_PDO_Op_Current value="300">3000 mA (Factor = 10, saved to 300)</vif:Snk_PDO_Op_Current>
+      </vif:SnkPDO>
+      <vif:SnkPDO>
+        <!--Sink PDO 2-->
+        <vif:Snk_PDO_Supply_Type value="1">Battery</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Op_Power value="60">15000 mW (Factor = 250, saved to 60)</vif:Snk_PDO_Op_Power>
+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV (Factor = 50, saved to 95)</vif:Snk_PDO_Min_Voltage>
+        <vif:Snk_PDO_Max_Voltage value="300">15000 mV (Factor = 50, saved to 300)</vif:Snk_PDO_Max_Voltage>
+      </vif:SnkPDO>
+      <vif:SnkPDO>
+        <!--Sink PDO 3-->
+        <vif:Snk_PDO_Supply_Type value="2">Variable</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV (Factor = 50, saved to 95)</vif:Snk_PDO_Min_Voltage>
+        <vif:Snk_PDO_Max_Voltage value="300">15000 mV (Factor = 50, saved to 300)</vif:Snk_PDO_Max_Voltage>
+        <vif:Snk_PDO_Op_Current value="300">3000 mA (Factor = 10, saved to 300)</vif:Snk_PDO_Op_Current>
+      </vif:SnkPDO>
+    </vif:SnkPdoList>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Dual Role-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Accepts_PR_Swap_As_Src value="true" />
+    <vif:Accepts_PR_Swap_As_Snk value="true" />
+    <vif:Requests_PR_Swap_As_Src value="true" />
+    <vif:Requests_PR_Swap_As_Snk value="true" />
+    <vif:FR_Swap_Supported_As_Initial_Sink value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;SOP Discover ID-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:XID_SOP value="0">0</vif:XID_SOP>
+    <vif:Data_Capable_As_USB_Host_SOP value="true" />
+    <vif:Data_Capable_As_USB_Device_SOP value="false" />
+    <vif:Product_Type_UFP_SOP value="0">Undefined</vif:Product_Type_UFP_SOP>
+    <vif:Product_Type_DFP_SOP value="2">PDUSB Host</vif:Product_Type_DFP_SOP>
+    <vif:DFP_VDO_Port_Number value="1">1</vif:DFP_VDO_Port_Number>
+    <vif:Modal_Operation_Supported_SOP value="false" />
+    <vif:USB_VID_SOP value="6353">18D1</vif:USB_VID_SOP>
+    <vif:PID_SOP value="20570">505A</vif:PID_SOP>
+    <vif:bcdDevice_SOP value="0">0000</vif:bcdDevice_SOP>
+  </vif:Component>
+</vif:VIF>
\ No newline at end of file
diff --git a/zephyr/program/nissa/joxer/keyboard.dtsi b/zephyr/program/nissa/joxer/keyboard.dtsi
new file mode 100644
index 0000000000..1742e1a50f
--- /dev/null
+++ b/zephyr/program/nissa/joxer/keyboard.dtsi
@@ -0,0 +1,48 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	kblight {
+		compatible = "cros-ec,kblight-pwm";
+		/*
+		 * Use 324 Hz so that 32Khz clock source is used,
+		 * which is not gated in power saving mode.
+		 */
+		pwms = <&pwm0 0 PWM_HZ(324) PWM_POLARITY_NORMAL>;
+	};
+};
+
+&pwm0 {
+	status = "okay";
+	prescaler-cx = <PWM_PRESCALER_C4>;
+	pinctrl-0 = <&pwm0_gpa0_default>;
+	pinctrl-names = "default";
+};
+
+&cros_kb_raw {
+	status = "okay";
+	/* No KSO2 (it's inverted and implemented by GPIO) */
+	pinctrl-0 = <&ksi0_default
+		     &ksi1_default
+		     &ksi2_default
+		     &ksi3_default
+		     &ksi4_default
+		     &ksi5_default
+		     &ksi6_default
+		     &ksi7_default
+		     &kso0_default
+		     &kso1_default
+		     &kso3_default
+		     &kso4_default
+		     &kso5_default
+		     &kso6_default
+		     &kso7_default
+		     &kso8_default
+		     &kso9_default
+		     &kso10_default
+		     &kso11_default
+		     &kso12_default>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/nissa/joxer/motionsense.dtsi b/zephyr/program/nissa/joxer/motionsense.dtsi
new file mode 100644
index 0000000000..fbac470660
--- /dev/null
+++ b/zephyr/program/nissa/joxer/motionsense.dtsi
@@ -0,0 +1,154 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/motionsense/utils.h>
+
+
+/ {
+	aliases {
+		/*
+		 * Interrupt bindings for sensor devices.
+		 */
+		bmi3xx-int = &base_accel;
+		bma4xx-int = &lid_accel;
+	};
+
+	/*
+	 * Declare mutexes used by sensor drivers.
+	 * A mutex node is used to create an instance of mutex_t.
+	 * A mutex node is referenced by a sensor node if the
+	 * corresponding sensor driver needs to use the
+	 * instance of the mutex.
+	 */
+	motionsense-mutex {
+		compatible = "cros-ec,motionsense-mutex";
+		lid_mutex: lid-mutex {
+		};
+
+		base_mutex: base-mutex {
+		};
+	};
+
+	/* Rotation matrix used by drivers. */
+	motionsense-rotation-ref {
+		compatible = "cros-ec,motionsense-rotation-ref";
+		lid_rot_ref: lid-rotation-ref {
+			mat33 = <0 (-1) 0
+				 (-1) 0 0
+				 0 0 (-1)>;
+		};
+
+		lid_rot_inverted: lid-rotation-inverted {
+			mat33 = <0 1 0
+				 (-1) 0 0
+				 0 0 1>;
+		};
+
+		base_rot_ref: base-rotation-ref {
+			mat33 = <1 0 0
+				 0 1 0
+				 0 0 1>;
+		};
+	};
+
+	/*
+	 * Driver specific data. A driver-specific data can be shared with
+	 * different motion sensors while they are using the same driver.
+	 *
+	 * If a node's compatible starts with "cros-ec,accelgyro-", it is for
+	 * a common structure defined in accelgyro.h.
+	 * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for
+	 * "struct als_drv_data_t" in accelgyro.h
+	 */
+	motionsense-sensor-data {
+		bmi323_data: bmi323-drv-data {
+			compatible = "cros-ec,drvdata-bmi3xx";
+			status = "okay";
+		};
+
+		bma422_data: bma422-drv-data {
+			compatible = "cros-ec,drvdata-bma4xx";
+			status = "okay";
+		};
+	};
+
+	/*
+	 * List of motion sensors that creates motion_sensors array.
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
+	 * motion sensor IDs for lid angle calculation.
+	 * TODO(b/238139272): The first entries of the array must be
+	 * accelerometers,then gyroscope. Fix this dependency in the DTS
+	 * processing which makes the devicetree entries independent.
+	 */
+	motionsense-sensor {
+		lid_accel: lid-accel {
+			compatible = "cros-ec,bma4xx";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&lid_mutex>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&lid_rot_ref>;
+			default-range = <2>;
+			drv-data = <&bma422_data>;
+			i2c-spi-addr-flags = "BMA4_I2C_ADDR_SECONDARY";
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_accel: base-accel {
+			compatible = "cros-ec,bmi3xx-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&bmi323_data>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_gyro: base-gyro {
+			compatible = "cros-ec,bmi3xx-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&bmi323_data>;
+		};
+	};
+
+	motionsense-sensor-info {
+		compatible = "cros-ec,motionsense-sensor-info";
+
+		/*
+		 * list of GPIO interrupts that have to
+		 * be enabled at initial stage
+		 */
+		sensor-irqs = <&int_imu &int_lid_accel>;
+	};
+};
diff --git a/zephyr/program/nissa/joxer/overlay.dtsi b/zephyr/program/nissa/joxer/overlay.dtsi
new file mode 100644
index 0000000000..d583ba5a59
--- /dev/null
+++ b/zephyr/program/nissa/joxer/overlay.dtsi
@@ -0,0 +1,403 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <cros/thermistor/thermistor.dtsi>
+#include <dt-bindings/usb_pd_tcpm.h>
+
+/ {
+	aliases {
+		gpio-cbi-wp = &gpio_ec_cbi_wp;
+		gpio-wp = &gpio_ec_wp_odl;
+		int-wp = &int_wp_l;
+	};
+
+	ec-console {
+		compatible = "ec-console";
+		disabled = "events", "lpc", "hostcmd";
+	};
+
+	batteries {
+		default_battery: cosmx {
+			compatible = "cosmx,gh02047xl", "battery-smart";
+		};
+		dynapack_atl_gh02047xl {
+			compatible = "dynapack,atl_gh02047xl", "battery-smart";
+		};
+		dynapack_cosmx_gh02047xl {
+			compatible = "dynapack,cosmx_gh02047xl", "battery-smart";
+		};
+		smp_coslight_gh02047xl {
+			compatible = "smp,coslight_gh02047xl", "battery-smart";
+		};
+		smp_highpower_gh02047xl {
+			compatible = "smp,highpower_gh02047xl", "battery-smart";
+		};
+	};
+
+	hibernate-wake-pins {
+		compatible = "cros-ec,hibernate-wake-pins";
+		wakeup-irqs = <
+			&int_power_button
+			&int_lid_open
+		>;
+	};
+
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_power_button: power_button {
+			irq-pin = <&gpio_gsc_ec_pwr_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_button_interrupt";
+		};
+		int_vol_down: vol_down {
+			irq-pin = <&gpio_voldn_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+		int_vol_up: vol_up {
+			irq-pin = <&gpio_volup_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+		int_wp_l: wp_l {
+			irq-pin = <&gpio_ec_wp_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "switch_interrupt";
+		};
+		int_lid_open: lid_open {
+			irq-pin = <&gpio_lid_open>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "lid_interrupt";
+		};
+		int_tablet_mode: tablet_mode {
+			irq-pin = <&gpio_tablet_mode_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "gmr_tablet_switch_isr";
+		};
+		int_imu: ec_imu {
+			irq-pin = <&gpio_imu_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "bmi3xx_interrupt";
+		};
+		int_lid_accel: ec_lid_accel {
+			irq-pin = <&gpio_acc_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "bma4xx_interrupt";
+		};
+		int_usb_c0: usb_c0 {
+			irq-pin = <&gpio_usb_c0_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "usb_c0_interrupt";
+		};
+		int_usb_c1: usb_c1 {
+			irq-pin = <&gpio_usb_c1_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "usb_c1_interrupt";
+		};
+	};
+
+	unused-pins {
+		compatible = "unused-gpios";
+		unused-gpios = <&gpioc 3 0>,
+			       <&gpiod 4 0>,
+			       <&gpioh 2 0>,
+			       <&gpiok 7 0>,
+			       <&gpioc 6 0>,
+			       <&gpiof 0 0>;
+	};
+
+	named-gpios {
+		/*
+		 * EC doesn't take any specific action on CC/SBU disconnect due to
+		 * fault, but this definition is useful for hardware testing.
+		 */
+		gpio_usb_c0_prot_fault_odl: usb_c0_prot_fault_odl {
+			gpios = <&gpiok 6 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_fan_enable: fan-enable {
+			gpios = <&gpiol 4 GPIO_OUTPUT>;
+			no-auto-init;
+		};
+		gpio_power_led_gate: power_led_gate {
+			gpios = <&gpiof 1 GPIO_OUTPUT_LOW>;
+		};
+		gpio_led_1_odl: led_1_odl {
+			gpios = <&gpioa 1 GPIO_OUTPUT_HIGH>;
+		};
+		gpio_led_2_odl: led_2_odl {
+			gpios = <&gpioa 2 GPIO_OUTPUT_HIGH>;
+		};
+		gpio_led_3_l: led_3_l {
+			gpios = <&gpiol 2 GPIO_OUTPUT_HIGH>;
+		};
+		gpio_led_4_l: led_4_l {
+			gpios = <&gpiol 3 GPIO_OUTPUT_HIGH>;
+		};
+	};
+
+	temp_memory: memory {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_1>;
+	};
+	temp_charger: charger {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_2>;
+	};
+	temp_ambient: ambient {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_3>;
+	};
+
+	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
+		memory {
+			temp_fan_off = <35>;
+			temp_fan_max = <60>;
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_memory>;
+		};
+		charger {
+			temp_fan_off = <35>;
+			temp_fan_max = <60>;
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_charger>;
+		};
+		ambient {
+			temp_fan_off = <35>;
+			temp_fan_max = <60>;
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_ambient>;
+		};
+	};
+
+	usba {
+		compatible = "cros-ec,usba-port-enable-pins";
+		/*
+		 * Unlike other Nissa boards, Joxer doesn't support USB-A1
+		 * and uses that pin to control a power LED on sub-boards.
+		 */
+		enable-pins = <&gpio_en_usb_a0_vbus>;
+		status = "okay";
+	};
+
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+			chg = <&chg_port0>;
+			tcpc = <&usbpd0>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_0>;
+			};
+		};
+		port0-muxes {
+			virtual_mux_0: virtual-mux-0 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+		port1@1 {
+			compatible = "named-usbc-port";
+			reg = <1>;
+			chg = <&chg_port1>;
+			tcpc = <&tcpc_port1>;
+			usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_1 &tcpci_mux_1>;
+			};
+			usb_mux_chain_1_no_mux: usb-mux-chain-1-no-mux {
+				compatible = "cros-ec,usb-mux-chain";
+				alternative-chain;
+				usb-muxes = <&virtual_mux_1>;
+			};
+		};
+		port1-muxes {
+			virtual_mux_1: virtual-mux-1 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+			tcpci_mux_1: tcpci-mux-1 {
+				compatible = "parade,usbc-mux-ps8xxx";
+			};
+		};
+	};
+	fans {
+		compatible = "cros-ec,fans";
+
+		fan_0 {
+			pwms = <&pwm7 PWM_CHANNEL_7 PWM_KHZ(30) PWM_POLARITY_NORMAL>;
+			tach = <&tach1>;
+			rpm_min = <1500>;
+			rpm_start = <1500>;
+			rpm_max = <6500>;
+			enable_gpio = <&gpio_fan_enable>;
+		};
+	};
+};
+
+&gpio_acc_int_l {
+	gpios = <&gpioc 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+};
+&gpio_imu_int_l {
+	gpios = <&gpioj 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+};
+&gpio_vccin_aux_vid0 {
+	gpios = <&gpiod 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+};
+&gpio_vccin_aux_vid1 {
+	gpios = <&gpiok 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+};
+
+&gpio_ec_prochot_odl {
+	gpios = <&gpioi 1 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>;
+};
+
+&thermistor_3V3_51K1_47K_4050B {
+	status = "okay";
+};
+
+&adc_ec_vsense_pp3300_s5 {
+	/*
+	 * Voltage divider on input has 47k upper and 220k lower legs with 3 V
+	 * full-scale reading on the ADC. Apply the largest possible multiplier
+	 * (without overflowing int32) to get the best possible approximation
+	 * of the actual ratio, but derate by a factor of two to ensure
+	 * unexpectedly high values won't overflow.
+	 */
+	mul = <(715828 / 2)>;
+	div = <(589820 / 2)>;
+};
+
+&adc0 {
+	pinctrl-0 = <&adc0_ch0_gpi0_default
+		     &adc0_ch2_gpi2_default
+		     &adc0_ch3_gpi3_default
+		     &adc0_ch13_gpl0_default
+		     &adc0_ch14_gpl1_default>;
+	pinctrl-names = "default";
+};
+
+&pinctrl {
+	i2c2_clk_gpf6_default: i2c2_clk_gpf6_default {
+		gpio-voltage = "1v8";
+	};
+	i2c2_data_gpf7_default: i2c2_data_gpf7_default {
+		gpio-voltage = "1v8";
+	};
+};
+
+
+&i2c0 {
+	label = "I2C_EEPROM";
+	clock-frequency = <I2C_BITRATE_FAST>;
+
+	cbi_eeprom: eeprom@50 {
+		compatible = "atmel,at24";
+		reg = <0x50>;
+		size = <2048>;
+		pagesize = <16>;
+		address-width = <8>;
+		timeout = <5>;
+	};
+	pinctrl-0 = <&i2c0_clk_gpb3_default
+		     &i2c0_data_gpb4_default>;
+	pinctrl-names = "default";
+};
+
+&i2c1 {
+	label = "I2C_BATTERY";
+	clock-frequency = <50000>;
+	pinctrl-0 = <&i2c1_clk_gpc1_default
+		     &i2c1_data_gpc2_default>;
+	pinctrl-names = "default";
+};
+
+&i2c2 {
+	label = "I2C_SENSOR";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c2_clk_gpf6_default
+		     &i2c2_data_gpf7_default>;
+	pinctrl-names = "default";
+};
+
+&i2c4 {
+	label = "I2C_SUB_C1_TCPC";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+	pinctrl-0 = <&i2c4_clk_gpe0_default
+		     &i2c4_data_gpe7_default>;
+	pinctrl-names = "default";
+
+	chg_port1: sm5803@32 {
+		compatible = "siliconmitus,sm5803";
+		status = "okay";
+		reg = <0x32>;
+	};
+
+	tcpc_port1: ps8745@b {
+		compatible = "parade,ps8xxx";
+		reg = <0xb>;
+		tcpc-flags = <(TCPC_FLAGS_TCPCI_REV2_0)>;
+	};
+};
+
+&i2c_ec_i2c_sub_usb_c1 {
+	/*
+	 * Dynamic speed setting is used for AP-controlled firmware update
+	 * of PS8745 TCPC/redriver: the AP lowers speed to 400 kHz in order
+	 * to use more efficient window programming, then sets it back when
+	 * done.
+	 */
+	dynamic-speed;
+};
+
+&i2c5 {
+	label = "I2C_USB_C0_TCPC";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+	pinctrl-0 = <&i2c5_clk_gpa4_default
+		     &i2c5_data_gpa5_default>;
+	pinctrl-names = "default";
+
+	chg_port0: sm5803@32 {
+		compatible = "siliconmitus,sm5803";
+		status = "okay";
+		reg = <0x32>;
+	};
+};
+
+/* pwm for fan */
+&pwm7 {
+	status = "okay";
+	prescaler-cx = <PWM_PRESCALER_C6>;
+	pinctrl-0 = <&pwm7_gpa7_default>;
+	pinctrl-names = "default";
+};
+
+/* fan tachometer sensor */
+&tach1 {
+	status = "okay";
+	channel = <IT8XXX2_TACH_CHANNEL_A>;
+	pulses-per-round = <2>;
+	pinctrl-0 = <&tach1a_gpd7_default>;
+	pinctrl-names = "default";
+};
+
+&usbpd0 {
+	status = "okay";
+};
diff --git a/zephyr/program/nissa/joxer/power_signals.dtsi b/zephyr/program/nissa/joxer/power_signals.dtsi
new file mode 100644
index 0000000000..8affae03b1
--- /dev/null
+++ b/zephyr/program/nissa/joxer/power_signals.dtsi
@@ -0,0 +1,223 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	chosen {
+		intel-ap-pwrseq,espi = &espi0;
+	};
+
+	common-pwrseq {
+		compatible = "intel,ap-pwrseq";
+
+		sys-pwrok-delay = <10>;
+		all-sys-pwrgd-timeout = <20>;
+	};
+
+	pwr-en-pp5000-s5 {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PP5000_S5 enable output to regulator";
+		enum-name = "PWR_EN_PP5000_A";
+		gpios = <&gpiok 5 0>;
+		output;
+	};
+	pwr-en-pp3300-s5 {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PP3300_S5 enable output to LS";
+		enum-name = "PWR_EN_PP3300_A";
+		gpios = <&gpioc 5 0>;
+		output;
+	};
+	pwr-pg-ec-rsmrst-odl {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST power good from regulator";
+		enum-name = "PWR_RSMRST";
+		gpios = <&gpioe 1 0>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-ec-pch-rsmrst-odl {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST output to PCH";
+		enum-name = "PWR_EC_PCH_RSMRST";
+		gpios = <&gpioh 0 0>;
+		output;
+	};
+	pwr-slp-s0-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_S0_L input from PCH";
+		enum-name = "PWR_SLP_S0";
+		gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-slp-s3-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_S3_L input from PCH";
+		enum-name = "PWR_SLP_S3";
+		gpios = <&gpioh 3 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-slp-sus-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_SUS_L input from PCH";
+		enum-name = "PWR_SLP_SUS";
+		gpios = <&gpiog 2 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-ec-soc-dsw-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "DSW_PWROK output to PCH";
+		enum-name = "PWR_EC_SOC_DSW_PWROK";
+		gpios = <&gpiol 7 0>;
+		output;
+	};
+	pwr-vccst-pwrgd-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "VCCST_PWRGD output to PCH";
+		enum-name = "PWR_VCCST_PWRGD";
+		gpios = <&gpioe 5 (GPIO_OPEN_DRAIN | GPIO_VOLTAGE_1P8)>;
+		output;
+	};
+	pwr-imvp9-vrrdy-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "VRRDY input from IMVP9";
+		enum-name = "PWR_IMVP9_VRRDY";
+		gpios = <&gpioj 4 0>;
+	};
+	pwr-pch-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PCH_PWROK output to PCH";
+		enum-name = "PWR_PCH_PWROK";
+		gpios = <&gpiod 6 GPIO_OPEN_DRAIN>;
+		output;
+	};
+	pwr-ec-pch-sys-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_PWROK output to PCH";
+		enum-name = "PWR_EC_PCH_SYS_PWROK";
+		gpios = <&gpiof 2 0>;
+		output;
+	};
+	pwr-sys-rst-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_RESET# output to PCH";
+		enum-name = "PWR_SYS_RST";
+		gpios = <&gpiod 1 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>;
+		output;
+	};
+	pwr-slp-s4 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S4 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S4";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4";
+		vw-invert;
+	};
+	pwr-slp-s5 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S5 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S5";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5";
+		vw-invert;
+	};
+	pwr-all-sys-pwrgd {
+		/*
+		 * This is a board level signal, since this
+		 * signal needs some special processing.
+		 */
+		compatible = "intel,ap-pwrseq-external";
+		dbg-label = "Combined all power good";
+		enum-name = "PWR_ALL_SYS_PWRGD";
+	};
+	pwr-adc-pp3300 {
+		compatible = "intel,ap-pwrseq-adc";
+		dbg-label = "PP3300_PROC";
+		enum-name = "PWR_DSW_PWROK";
+		trigger-high = <&vcmp0>;
+		trigger-low = <&vcmp1>;
+	};
+	pwr-adc-pp1p05 {
+		compatible = "intel,ap-pwrseq-adc";
+		dbg-label = "PP1P05_PROC";
+		enum-name = "PWR_PG_PP1P05";
+		trigger-high = <&vcmp2>;
+		trigger-low = <&vcmp3>;
+	};
+
+};
+
+/*
+ * Because the power signals directly reference the GPIOs,
+ * the correspinding named-gpios need to have no-auto-init set.
+ */
+&gpio_ec_soc_dsw_pwrok {
+	no-auto-init;
+};
+&gpio_ec_soc_pch_pwrok_od {
+	no-auto-init;
+};
+&gpio_ec_soc_rsmrst_l {
+	no-auto-init;
+};
+&gpio_ec_soc_sys_pwrok {
+	no-auto-init;
+};
+&gpio_ec_soc_vccst_pwrgd_od {
+	no-auto-init;
+};
+&gpio_en_pp3300_s5 {
+	no-auto-init;
+};
+&gpio_en_pp5000_s5 {
+	no-auto-init;
+};
+&gpio_imvp91_vrrdy_od {
+	no-auto-init;
+};
+&gpio_rsmrst_pwrgd_l {
+	no-auto-init;
+};
+&gpio_slp_s0_l {
+	no-auto-init;
+};
+&gpio_slp_s3_l {
+	no-auto-init;
+};
+&gpio_slp_sus_l {
+	no-auto-init;
+};
+&gpio_sys_rst_odl {
+	no-auto-init;
+};
+&vcmp0 {
+	status = "okay";
+	scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>;
+	comparison = <IT8XXX2_VCMP_GREATER>;
+	/*
+	 * This is 90% of nominal voltage considering voltage
+	 * divider on ADC input.
+	 */
+	threshold-mv = <2448>;
+	io-channels = <&adc0 0>;
+};
+&vcmp1 {
+	status = "okay";
+	scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>;
+	comparison = <IT8XXX2_VCMP_LESS_OR_EQUAL>;
+	threshold-mv = <2448>;
+	io-channels = <&adc0 0>;
+};
+&vcmp2 {
+	status = "okay";
+	scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>;
+	comparison = <IT8XXX2_VCMP_GREATER>;
+	/* Setting at 90% of nominal voltage */
+	threshold-mv = <945>;
+	io-channels = <&adc0 14>;
+};
+&vcmp3 {
+	status = "okay";
+	scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>;
+	comparison = <IT8XXX2_VCMP_LESS_OR_EQUAL>;
+	threshold-mv = <945>;
+	io-channels = <&adc0 14>;
+};
diff --git a/zephyr/program/nissa/joxer/project.conf b/zephyr/program/nissa/joxer/project.conf
new file mode 100644
index 0000000000..db96d8e875
--- /dev/null
+++ b/zephyr/program/nissa/joxer/project.conf
@@ -0,0 +1,32 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_BOARD_JOXER=y
+
+# Ensure recovery key combination (esc+refresh+power) is reliable: b/236580049
+CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI3=y
+CONFIG_PLATFORM_EC_KEYBOARD_REFRESH_ROW3=y
+
+# Sensor drivers
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y
+CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y
+CONFIG_PLATFORM_EC_MAX_SENSOR_FREQ_MILLIHZ=100000
+
+# LED
+CONFIG_PLATFORM_EC_LED_PWM=n
+CONFIG_PLATFORM_EC_LED_COMMON=y
+
+# Both ports use a SLGC55545 smart switch with CTL1..3 fixed high,
+# for SDP2 or CDP only.
+CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART=y
+CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_CDP_SDP_ONLY=y
+CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_DEFAULT_CDP=y
+CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_INVERTED=y
+
+# Disable USBC BC12
+CONFIG_PLATFORM_EC_USB_CHARGER=n
+
+# Disable sub board configurations
+CONFIG_NISSA_SUB_BOARD=n
diff --git a/zephyr/program/nissa/joxer/project.overlay b/zephyr/program/nissa/joxer/project.overlay
new file mode 100644
index 0000000000..a7c551b7cc
--- /dev/null
+++ b/zephyr/program/nissa/joxer/project.overlay
@@ -0,0 +1,15 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "../cbi.dtsi"
+#include "../shi.dtsi"
+
+#include "cbi.dtsi"
+#include "generated.dtsi"
+#include "keyboard.dtsi"
+#include "motionsense.dtsi"
+#include "overlay.dtsi"
+#include "power_signals.dtsi"
+#include "pwm_leds.dtsi"
diff --git a/zephyr/program/nissa/joxer/pwm_leds.dtsi b/zephyr/program/nissa/joxer/pwm_leds.dtsi
new file mode 100644
index 0000000000..aa4a76b271
--- /dev/null
+++ b/zephyr/program/nissa/joxer/pwm_leds.dtsi
@@ -0,0 +1,60 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	pwmleds {
+		compatible = "pwm-leds";
+		pwm_led0: pwm_led_0 {
+			pwms = <&pwm1 1 PWM_HZ(1296) PWM_POLARITY_INVERTED>,
+			       <&pwm2 2 PWM_HZ(1296) PWM_POLARITY_INVERTED>,
+			       <&pwm3 3 PWM_HZ(1296) PWM_POLARITY_INVERTED>;
+		};
+	};
+
+	cros-pwmleds {
+		compatible = "cros-ec,pwm-leds";
+
+		leds = <&pwm_led0>;
+
+				/*<red green blue>*/
+		color-map-red    = <100   0    0>;
+		color-map-green  = <  0 100    0>;
+		color-map-blue   = <  0   0  100>;
+		color-map-yellow = <  0  50   50>;
+		color-map-white  = <100 100  100>;
+		color-map-amber  = <100  15    0>;
+
+		brightness-range = <100 100 100 0 0 0>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pwm_led_0@0 {
+			reg = <0>;
+			ec-led-name = "EC_LED_ID_BATTERY_LED";
+		};
+	};
+};
+
+&pwm1 {
+	status = "okay";
+	prescaler-cx = <PWM_PRESCALER_C4>;
+	pinctrl-0 = <&pwm1_gpa1_default>;
+	pinctrl-names = "default";
+};
+
+&pwm2 {
+	status = "okay";
+	prescaler-cx = <PWM_PRESCALER_C4>;
+	pinctrl-0 = <&pwm2_gpa2_default>;
+	pinctrl-names = "default";
+};
+
+&pwm3 {
+	status = "okay";
+	prescaler-cx = <PWM_PRESCALER_C4>;
+	pinctrl-0 = <&pwm3_gpa3_default>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/nissa/joxer/src/board.c b/zephyr/program/nissa/joxer/src/board.c
new file mode 100644
index 0000000000..5e2d258d80
--- /dev/null
+++ b/zephyr/program/nissa/joxer/src/board.c
@@ -0,0 +1,33 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* joxer hardware configuration */
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "task.h"
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/sys/printk.h>
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+__override uint8_t board_get_usb_pd_port_count(void)
+{
+	return 2;
+}
+/*
+ * Enable interrupts
+ */
+static void board_init(void)
+{
+	/*
+	 * Enable USB-C interrupts.
+	 */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0));
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1));
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/zephyr/program/nissa/joxer/src/charger.c b/zephyr/program/nissa/joxer/src/charger.c
new file mode 100644
index 0000000000..4bdf75c38b
--- /dev/null
+++ b/zephyr/program/nissa/joxer/src/charger.c
@@ -0,0 +1,55 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "charger.h"
+#include "console.h"
+#include "driver/charger/sm5803.h"
+#include "extpower.h"
+#include "usb_pd.h"
+
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+int extpower_is_present(void)
+{
+	int port;
+	int rv;
+	bool acok;
+
+	for (port = 0; port < board_get_usb_pd_port_count(); port++) {
+		rv = sm5803_is_acok(port, &acok);
+		if ((rv == EC_SUCCESS) && acok)
+			return 1;
+	}
+
+	return 0;
+}
+
+/*
+ * Joxer not have a GPIO indicating whether extpower is present,
+ * so detect using the charger(s).
+ */
+__override void board_check_extpower(void)
+{
+	static int last_extpower_present;
+	int extpower_present = extpower_is_present();
+
+	if (last_extpower_present ^ extpower_present)
+		extpower_handle_update(extpower_present);
+
+	last_extpower_present = extpower_present;
+}
+
+__override void board_hibernate(void)
+{
+	/* Shut down the chargers */
+	if (board_get_usb_pd_port_count() == 2)
+		sm5803_hibernate(CHARGER_SECONDARY);
+	sm5803_hibernate(CHARGER_PRIMARY);
+	LOG_INF("Charger(s) hibernated");
+	cflush();
+}
diff --git a/zephyr/program/nissa/joxer/src/fan.c b/zephyr/program/nissa/joxer/src/fan.c
new file mode 100644
index 0000000000..5df26126b0
--- /dev/null
+++ b/zephyr/program/nissa/joxer/src/fan.c
@@ -0,0 +1,41 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cros_cbi.h"
+#include "fan.h"
+#include "gpio/gpio.h"
+#include "hooks.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+/*
+ * Joxer fan support
+ */
+static void fan_init(void)
+{
+	int ret;
+	uint32_t val;
+	/*
+	 * Retrieve the fan config.
+	 */
+	ret = cros_cbi_get_fw_config(FW_FAN, &val);
+	if (ret != 0) {
+		LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_FAN);
+		return;
+	}
+	if (val != FW_FAN_PRESENT) {
+		/* Disable the fan */
+		fan_set_count(0);
+	} else {
+		/* Configure the fan enable GPIO */
+		gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_fan_enable),
+				      GPIO_OUTPUT);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, fan_init, HOOK_PRIO_POST_FIRST);
diff --git a/zephyr/program/nissa/joxer/src/form_factor.c b/zephyr/program/nissa/joxer/src/form_factor.c
new file mode 100644
index 0000000000..1087d7ddca
--- /dev/null
+++ b/zephyr/program/nissa/joxer/src/form_factor.c
@@ -0,0 +1,39 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "accelgyro.h"
+#include "cros_cbi.h"
+#include "hooks.h"
+#include "motionsense_sensors.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+#define ALT_MAT SENSOR_ROT_STD_REF_NAME(DT_NODELABEL(lid_rot_inverted))
+#define LID_ACCEL SENSOR_ID(DT_NODELABEL(lid_accel))
+
+static void form_factor_init(void)
+{
+	int ret;
+	uint32_t val;
+	/*
+	 * If the firmware config indicates
+	 * an inverted form factor, use the alternative
+	 * rotation matrix.
+	 */
+	ret = cros_cbi_get_fw_config(FW_LID_INVERSION, &val);
+	if (ret != 0) {
+		LOG_ERR("Error retrieving CBI FW_CONFIG field %d",
+			FW_LID_INVERSION);
+		return;
+	}
+	if (val == SENSOR_INVERTED) {
+		LOG_INF("Switching to inverted lid");
+		motion_sensors[LID_ACCEL].rot_standard_ref = &ALT_MAT;
+	}
+}
+DECLARE_HOOK(HOOK_INIT, form_factor_init, HOOK_PRIO_POST_I2C);
diff --git a/zephyr/program/nissa/joxer/src/keyboard.c b/zephyr/program/nissa/joxer/src/keyboard.c
new file mode 100644
index 0000000000..be6ed09d56
--- /dev/null
+++ b/zephyr/program/nissa/joxer/src/keyboard.c
@@ -0,0 +1,67 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cros_cbi.h"
+#include "ec_commands.h"
+#include "gpio/gpio.h"
+#include "hooks.h"
+#include "keyboard_8042_sharedlib.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+static const struct ec_response_keybd_config joxer_kb_legacy = {
+	.num_top_row_keys = 13,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_KBD_BKLIGHT_TOGGLE,	/* T8 */
+		TK_PLAY_PAUSE,		/* T9 */
+		TK_MICMUTE,		/* T10 */
+		TK_VOL_MUTE,		/* T11 */
+		TK_VOL_DOWN,		/* T12 */
+		TK_VOL_UP,		/* T13 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &joxer_kb_legacy;
+}
+
+/*
+ * Keyboard layout decided by FW config.
+ */
+static void kb_layout_init(void)
+{
+	int ret;
+	uint32_t val;
+	/*
+	 * Retrieve the kb layout config.
+	 */
+	ret = cros_cbi_get_fw_config(FW_KB_LAYOUT, &val);
+	if (ret != 0) {
+		LOG_ERR("Error retrieving CBI FW_CONFIG field %d",
+			FW_KB_LAYOUT);
+		return;
+	}
+	/*
+	 * If keyboard is US2(FW_KB_LAYOUT_US2), we need translate right ctrl
+	 * to backslash(\|) key.
+	 */
+	if (val == FW_KB_LAYOUT_US2)
+		set_scancode_set2(4, 0, get_scancode_set2(2, 7));
+}
+DECLARE_HOOK(HOOK_INIT, kb_layout_init, HOOK_PRIO_POST_FIRST);
diff --git a/zephyr/program/nissa/joxer/src/led.c b/zephyr/program/nissa/joxer/src/led.c
new file mode 100644
index 0000000000..8a7afe8cee
--- /dev/null
+++ b/zephyr/program/nissa/joxer/src/led.c
@@ -0,0 +1,176 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery LED control for nissa
+ */
+#include "charge_manager.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+#include "pwm.h"
+#include "util.h"
+
+#include <stdint.h>
+
+#define BAT_LED_ON_LVL 0
+#define BAT_LED_OFF_LVL 1
+
+#define PWR_LED_ON_LVL 1
+#define PWR_LED_OFF_LVL 0
+
+#define LED_SIDESEL_MB_PORT 0
+#define LED_SIDESEL_DB_PORT 1
+
+__override const int led_charge_lvl_1 = 5;
+__override const int led_charge_lvl_2 = 95;
+
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    0.5 * LED_ONE_SEC },
+					  { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 1 * LED_ONE_SEC } },
+	};
+
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_BATTERY_LED,
+	EC_LED_ID_POWER_LED,
+};
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	int port;
+
+	/* There are four battery leds, LED1/LED2 are on MB side and
+	 * LED3/LED4 are on DB side. All leds are OFF by default.
+	 */
+	int led1, led2, led3, led4;
+
+	led1 = led2 = led3 = led4 = BAT_LED_OFF_LVL;
+
+	/* Check which port is the charging port,
+	 * and turn on the corresponding led.
+	 */
+	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
+		port = charge_manager_get_active_charge_port();
+		switch (port) {
+		case LED_SIDESEL_MB_PORT:
+			switch (color) {
+			case EC_LED_COLOR_AMBER:
+				led1 = BAT_LED_ON_LVL;
+				break;
+			case EC_LED_COLOR_WHITE:
+				led2 = BAT_LED_ON_LVL;
+				break;
+			default: /* LED_OFF and other unsupported colors */
+				break;
+			}
+			break;
+		case LED_SIDESEL_DB_PORT:
+			switch (color) {
+			case EC_LED_COLOR_AMBER:
+				led3 = BAT_LED_ON_LVL;
+				break;
+			case EC_LED_COLOR_WHITE:
+				led4 = BAT_LED_ON_LVL;
+				break;
+			default: /* LED_OFF and other unsupported colors */
+				break;
+			}
+			break;
+		default: /* Unknown charging port */
+			break;
+		}
+	} else {
+		switch (color) {
+		case EC_LED_COLOR_AMBER:
+			led1 = BAT_LED_ON_LVL;
+			led3 = BAT_LED_ON_LVL;
+			break;
+		case EC_LED_COLOR_WHITE:
+			led2 = BAT_LED_ON_LVL;
+			led4 = BAT_LED_ON_LVL;
+			break;
+		default: /* LED_OFF and other unsupported colors */
+			break;
+		}
+	}
+
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_led_1_odl), led1);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_led_2_odl), led2);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_led_3_l), led3);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_led_4_l), led4);
+}
+
+__override void led_set_color_power(enum ec_led_colors color)
+{
+	if (color == EC_LED_COLOR_WHITE)
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_power_led_gate),
+				PWR_LED_ON_LVL);
+	else
+		/* LED_OFF and unsupported colors */
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_power_led_gate),
+				PWR_LED_OFF_LVL);
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		led_auto_control(led_id, 0);
+		if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(EC_LED_COLOR_AMBER);
+		else if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_battery(EC_LED_COLOR_WHITE);
+		else if (brightness[LED_OFF] != 0)
+			led_set_color_battery(LED_OFF);
+		else {
+			led_auto_control(led_id, 1);
+			led_set_color_battery(LED_OFF);
+		}
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_power(EC_LED_COLOR_WHITE);
+		else
+			led_set_color_power(LED_OFF);
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/zephyr/program/nissa/joxer/src/usbc.c b/zephyr/program/nissa/joxer/src/usbc.c
new file mode 100644
index 0000000000..5b8f585b3a
--- /dev/null
+++ b/zephyr/program/nissa/joxer/src/usbc.c
@@ -0,0 +1,297 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_state.h"
+#include "chipset.h"
+#include "driver/charger/sm5803.h"
+#include "driver/tcpm/it83xx_pd.h"
+#include "driver/tcpm/ps8xxx_public.h"
+#include "driver/tcpm/tcpci.h"
+#include "hooks.h"
+#include "system.h"
+#include "usb_mux.h"
+
+#include <zephyr/logging/log.h>
+
+#include <ap_power/ap_power.h>
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+/* Vconn control for integrated ITE TCPC */
+void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
+{
+	/* Vconn control is only for port 0 */
+	if (port)
+		return;
+
+	if (cc_pin == USBPD_CC_PIN_1)
+		gpio_pin_set_dt(
+			GPIO_DT_FROM_NODELABEL(gpio_en_usb_c0_cc1_vconn),
+			!!enabled);
+	else
+		gpio_pin_set_dt(
+			GPIO_DT_FROM_NODELABEL(gpio_en_usb_c0_cc2_vconn),
+			!!enabled);
+}
+
+__override bool pd_check_vbus_level(int port, enum vbus_level level)
+{
+	return sm5803_check_vbus_level(port, level);
+}
+
+/*
+ * Putting chargers into LPM when in suspend reduces power draw by about 8mW
+ * per charger, but also seems critical to correct operation in source mode:
+ * if chargers are not in LPM when a sink is first connected, VBUS sourcing
+ * works even if the partner is later removed (causing LPM entry) and
+ * reconnected (causing LPM exit). If in LPM initially, sourcing VBUS
+ * consistently causes the charger to report (apparently spurious) overcurrent
+ * failures.
+ *
+ * In short, this is important to making things work correctly but we don't
+ * understand why.
+ */
+static void board_chargers_suspend(struct ap_power_ev_callback *const cb,
+				   const struct ap_power_ev_data data)
+{
+	void (*fn)(int chgnum);
+
+	switch (data.event) {
+	case AP_POWER_SUSPEND:
+		fn = sm5803_enable_low_power_mode;
+		break;
+	case AP_POWER_RESUME:
+		fn = sm5803_disable_low_power_mode;
+		break;
+	default:
+		LOG_WRN("%s: power event %d is not recognized", __func__,
+			data.event);
+		return;
+	}
+
+	fn(CHARGER_PRIMARY);
+	if (board_get_charger_chip_count() > 1)
+		fn(CHARGER_SECONDARY);
+}
+
+static int board_chargers_suspend_init(void)
+{
+	static struct ap_power_ev_callback cb = {
+		.handler = board_chargers_suspend,
+		.events = AP_POWER_SUSPEND | AP_POWER_RESUME,
+	};
+	ap_power_ev_add_callback(&cb);
+	return 0;
+}
+SYS_INIT(board_chargers_suspend_init, APPLICATION, 0);
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count());
+	int i;
+	int old_port;
+	int rv;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	old_port = charge_manager_get_active_charge_port();
+	LOG_INF("Charge update: p%d -> p%d", old_port, port);
+
+	/* Check if port is sourcing VBUS. */
+	if (port != CHARGE_PORT_NONE && charger_is_sourcing_otg_power(port)) {
+		LOG_WRN("Skip enable p%d: already sourcing", port);
+		return EC_ERROR_INVAL;
+	}
+
+	/* Disable sinking on all ports except the desired one */
+	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+		if (i == port)
+			continue;
+
+		if (sm5803_vbus_sink_enable(i, 0))
+			/*
+			 * Do not early-return because this can fail during
+			 * power-on which would put us into a loop.
+			 */
+			LOG_WRN("p%d: sink path disable failed.", i);
+	}
+
+	/* Don't enable anything (stop here) if no ports were requested */
+	if ((port == CHARGE_PORT_NONE) || (old_port == port))
+		return EC_SUCCESS;
+
+	/*
+	 * Stop the charger IC from switching while changing ports.  Otherwise,
+	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
+	 */
+	if (old_port != CHARGE_PORT_NONE)
+		charger_discharge_on_ac(1);
+
+	/* Enable requested charge port. */
+	rv = sm5803_vbus_sink_enable(port, 1);
+	if (rv)
+		LOG_WRN("p%d: sink path enable failed: code %d", port, rv);
+
+	/* Allow the charger IC to begin/continue switching. */
+	charger_discharge_on_ac(0);
+
+	return rv;
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	/*
+	 * TCPC 0 is embedded in the EC and processes interrupts in the chip
+	 * code (it83xx/intc.c). This function only needs to poll port C1 if
+	 * present.
+	 */
+	uint16_t status = 0;
+	int regval;
+
+	/* Is the C1 port present and its IRQ line asserted? */
+	if (board_get_usb_pd_port_count() == 2 &&
+	    !gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_int_odl))) {
+		/*
+		 * C1 IRQ is shared between and TCPC; poll TCPC to see if
+		 * it asserted the IRQ.
+		 */
+		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
+			if (regval)
+				status = PD_STATUS_TCPC_ALERT_1;
+		}
+	}
+
+	return status;
+}
+
+void pd_power_supply_reset(int port)
+{
+	int prev_en;
+
+	if (port < 0 || port >= board_get_usb_pd_port_count())
+		return;
+
+	prev_en = charger_is_sourcing_otg_power(port);
+
+	/* Disable Vbus */
+	charger_enable_otg_power(port, 0);
+
+	/* Discharge Vbus if previously enabled */
+	if (prev_en)
+		sm5803_set_vbus_disch(port, 1);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	enum ec_error_list rv;
+
+	if (port < 0 || port > board_get_usb_pd_port_count()) {
+		LOG_WRN("Port C%d does not exist, cannot enable VBUS", port);
+		return EC_ERROR_INVAL;
+	}
+
+	/* Disable sinking */
+	rv = sm5803_vbus_sink_enable(port, 0);
+	if (rv) {
+		LOG_WRN("C%d failed to disable sinking: %d", port, rv);
+		return rv;
+	}
+
+	/* Disable Vbus discharge */
+	rv = sm5803_set_vbus_disch(port, 0);
+	if (rv) {
+		LOG_WRN("C%d failed to clear VBUS discharge: %d", port, rv);
+		return rv;
+	}
+
+	/* Provide Vbus */
+	rv = charger_enable_otg_power(port, 1);
+	if (rv) {
+		LOG_WRN("C%d failed to enable VBUS sourcing: %d", port, rv);
+		return rv;
+	}
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	int rv;
+	const int current = rp == TYPEC_RP_3A0 ? 3000 : 1500;
+
+	rv = charger_set_otg_current_voltage(port, current, 5000);
+	if (rv != EC_SUCCESS) {
+		LOG_WRN("Failed to set source ilimit on port %d to %d: %d",
+			port, current, rv);
+	}
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * Do nothing. The integrated TCPC for C0 lacks a dedicated reset
+	 * command, and C1 (if present) doesn't have a reset pin connected
+	 * to the EC.
+	 */
+}
+
+/* C0 interrupt can only be triggered by the charger */
+void usb_c0_interrupt(enum gpio_signal s)
+{
+	sm5803_interrupt(0);
+}
+
+/* C1 interrupt line shared by TCPC, and charger */
+void usb_c1_interrupt(enum gpio_signal s)
+{
+	/* Charger is handled in board_process_pd_alert */
+	schedule_deferred_pd_interrupt(1);
+}
+
+/*
+ * Handle charger interrupts in the PD task. Not doing so can lead to a priority
+ * inversion where we fail to respond to TCPC alerts quickly enough because we
+ * don't get another edge on a shared IRQ until the other interrupt is cleared
+ * (or the IRQ is polled again), which happens in lower-priority tasks: the
+ * high-priority type-C handler is thus blocked on the lower-priority one(s).
+ *
+ * To avoid that, we run charger interrupt synchronously alongside
+ * PD interrupts so they have the same priority.
+ */
+void board_process_pd_alert(int port)
+{
+	/*
+	 * Port 0 doesn't use an external TCPC, so its interrupts don't need
+	 * this special handling.
+	 */
+	if (port != 1)
+		return;
+
+	if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_int_odl)))
+		sm5803_handle_interrupt(port);
+
+	/*
+	 * Immediately schedule another TCPC interrupt if it seems we haven't
+	 * cleared all pending interrupts.
+	 */
+	if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_int_odl)))
+		schedule_deferred_pd_interrupt(port);
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	int chg_det = 0;
+
+	sm5803_get_chg_det(port, &chg_det);
+
+	return chg_det;
+}
diff --git a/zephyr/program/nissa/nereid/generated.dtsi b/zephyr/program/nissa/nereid/generated.dtsi
new file mode 100644
index 0000000000..bca58c478e
--- /dev/null
+++ b/zephyr/program/nissa/nereid/generated.dtsi
@@ -0,0 +1,260 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * This file is auto-generated - do not edit!
+ */
+
+/ {
+
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc {
+			enum-name = "ADC_PP1050_PROC";
+			io-channels = <&adc0 14>;
+		};
+		adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 {
+			enum-name = "ADC_PP3300_S5";
+			io-channels = <&adc0 0>;
+		};
+		adc_temp_sensor_1: temp_sensor_1 {
+			enum-name = "ADC_TEMP_SENSOR_1";
+			io-channels = <&adc0 2>;
+		};
+		adc_temp_sensor_2: temp_sensor_2 {
+			enum-name = "ADC_TEMP_SENSOR_2";
+			io-channels = <&adc0 3>;
+		};
+		adc_temp_sensor_3: temp_sensor_3 {
+			enum-name = "ADC_TEMP_SENSOR_3";
+			io-channels = <&adc0 13>;
+		};
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		gpio_acc_int_l: acc_int_l {
+			gpios = <&gpioc 0 GPIO_INPUT>;
+		};
+		gpio_all_sys_pwrgd: all_sys_pwrgd {
+			gpios = <&gpiob 7 GPIO_INPUT>;
+		};
+		gpio_ccd_mode_odl: ccd_mode_odl {
+			gpios = <&gpioh 5 GPIO_INPUT>;
+			enum-name = "GPIO_CCD_MODE_ODL";
+		};
+		gpio_cpu_c10_gate_l: cpu_c10_gate_l {
+			gpios = <&gpiog 1 GPIO_INPUT>;
+		};
+		gpio_ec_battery_pres_odl: ec_battery_pres_odl {
+			gpios = <&gpioi 4 GPIO_INPUT>;
+			enum-name = "GPIO_BATT_PRES_ODL";
+		};
+		gpio_ec_cbi_wp: ec_cbi_wp {
+			gpios = <&gpioj 5 GPIO_OUTPUT>;
+		};
+		gpio_ec_edp_bl_en_od: ec_edp_bl_en_od {
+			gpios = <&gpiok 4 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_ENABLE_BACKLIGHT";
+		};
+		gpio_ec_entering_rw: ec_entering_rw {
+			gpios = <&gpioc 7 GPIO_OUTPUT>;
+			enum-name = "GPIO_ENTERING_RW";
+		};
+		gpio_ec_gsc_packet_mode: ec_gsc_packet_mode {
+			gpios = <&gpioh 1 GPIO_OUTPUT>;
+			enum-name = "GPIO_PACKET_MODE_EN";
+		};
+		gpio_ec_pch_wake_odl: ec_pch_wake_odl {
+			gpios = <&gpiob 2 GPIO_ODR_LOW>;
+		};
+		gpio_ec_prochot_odl: ec_prochot_odl {
+			gpios = <&gpioi 1 GPIO_ODR_HIGH>;
+		};
+		gpio_ec_soc_dsw_pwrok: ec_soc_dsw_pwrok {
+			gpios = <&gpiol 7 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_hdmi_hpd: ec_soc_hdmi_hpd {
+			gpios = <&gpiok 7 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_int_odl: ec_soc_int_odl {
+			gpios = <&gpiod 5 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_EC_INT_L";
+		};
+		gpio_ec_soc_pch_pwrok_od: ec_soc_pch_pwrok_od {
+			gpios = <&gpiod 6 GPIO_ODR_HIGH>;
+		};
+		gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl {
+			gpios = <&gpiob 6 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_PCH_PWRBTN_L";
+		};
+		gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l {
+			gpios = <&gpioh 0 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_rtcrst: ec_soc_rtcrst {
+			gpios = <&gpiok 2 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_sys_pwrok: ec_soc_sys_pwrok {
+			gpios = <&gpiof 2 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_vccst_pwrgd_od: ec_soc_vccst_pwrgd_od {
+			gpios = <&gpioe 5 GPIO_ODR_HIGH>;
+		};
+		gpio_ec_wp_odl: ec_wp_odl {
+			gpios = <&gpioa 6 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_en_kb_bl: en_kb_bl {
+			gpios = <&gpioj 3 GPIO_OUTPUT>;
+			enum-name = "GPIO_EN_KEYBOARD_BACKLIGHT";
+		};
+		gpio_en_pp3300_s5: en_pp3300_s5 {
+			gpios = <&gpioc 5 GPIO_OUTPUT>;
+			enum-name = "GPIO_TEMP_SENSOR_POWER";
+		};
+		gpio_en_pp5000_pen_x: en_pp5000_pen_x {
+			gpios = <&gpiob 5 GPIO_OUTPUT>;
+		};
+		gpio_en_pp5000_s5: en_pp5000_s5 {
+			gpios = <&gpiok 5 GPIO_OUTPUT>;
+		};
+		gpio_en_slp_z: en_slp_z {
+			gpios = <&gpiok 3 GPIO_OUTPUT>;
+		};
+		gpio_en_usb_a0_vbus: en_usb_a0_vbus {
+			gpios = <&gpiol 6 GPIO_OUTPUT>;
+		};
+		gpio_en_usb_c0_cc1_vconn: en_usb_c0_cc1_vconn {
+			gpios = <&gpioh 4 GPIO_OUTPUT>;
+		};
+		gpio_en_usb_c0_cc2_vconn: en_usb_c0_cc2_vconn {
+			gpios = <&gpioh 6 GPIO_OUTPUT>;
+		};
+		gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl {
+			gpios = <&gpioe 2 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		gpio_hdmi_sel: hdmi_sel {
+			gpios = <&gpioc 6 GPIO_OUTPUT>;
+		};
+		gpio_imu_int_l: imu_int_l {
+			gpios = <&gpioj 0 GPIO_INPUT>;
+		};
+		gpio_imvp91_vrrdy_od: imvp91_vrrdy_od {
+			gpios = <&gpioj 4 GPIO_INPUT>;
+		};
+		gpio_lid_open: lid_open {
+			gpios = <&gpiof 3 GPIO_INPUT>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+		gpio_pen_detect_odl: pen_detect_odl {
+			gpios = <&gpioj 1 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_pg_pp1050_mem_s3_od: pg_pp1050_mem_s3_od {
+			gpios = <&gpiod 3 GPIO_INPUT>;
+		};
+		gpio_pg_pp5000_s5_od: pg_pp5000_s5_od {
+			gpios = <&gpioe 3 GPIO_INPUT>;
+		};
+		gpio_rsmrst_pwrgd_l: rsmrst_pwrgd_l {
+			gpios = <&gpioe 1 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_slp_s0_l: slp_s0_l {
+			gpios = <&gpioe 4 GPIO_INPUT>;
+		};
+		gpio_slp_s3_l: slp_s3_l {
+			gpios = <&gpioh 3 GPIO_INPUT>;
+		};
+		gpio_slp_s4_l: slp_s4_l {
+			gpios = <&gpioi 5 GPIO_INPUT>;
+		};
+		gpio_slp_sus_l: slp_sus_l {
+			gpios = <&gpiog 2 GPIO_INPUT>;
+		};
+		gpio_sub_usb_a1_ilimit_sdp: sub_usb_a1_ilimit_sdp {
+			gpios = <&gpiof 1 GPIO_OUTPUT>;
+			enum-name = "GPIO_USB2_ILIM_SEL";
+		};
+		gpio_sys_rst_odl: sys_rst_odl {
+			gpios = <&gpiod 1 GPIO_ODR_HIGH>;
+		};
+		gpio_tablet_mode_l: tablet_mode_l {
+			gpios = <&gpioa 7 GPIO_INPUT>;
+			enum-name = "GPIO_TABLET_MODE_L";
+		};
+		gpio_usb_a0_ilimit_sdp: usb_a0_ilimit_sdp {
+			gpios = <&gpiol 5 GPIO_OUTPUT>;
+			enum-name = "GPIO_USB1_ILIM_SEL";
+		};
+		gpio_usb_c0_frs: usb_c0_frs {
+			gpios = <&gpioc 4 GPIO_OUTPUT>;
+		};
+		gpio_usb_c0_int_odl: usb_c0_int_odl {
+			gpios = <&gpiok 0 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_vccin_aux_vid0: vccin_aux_vid0 {
+			gpios = <&gpiod 0 GPIO_INPUT>;
+		};
+		gpio_vccin_aux_vid1: vccin_aux_vid1 {
+			gpios = <&gpiok 1 GPIO_INPUT>;
+		};
+		gpio_voldn_btn_odl: voldn_btn_odl {
+			gpios = <&gpioi 6 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_DOWN_L";
+		};
+		gpio_volup_btn_odl: volup_btn_odl {
+			gpios = <&gpioi 7 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_UP_L";
+		};
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		i2c_ec_i2c_eeprom: ec_i2c_eeprom {
+			i2c-port = <&i2c0>;
+			enum-names = "I2C_PORT_EEPROM";
+		};
+		i2c_ec_i2c_batt: ec_i2c_batt {
+			i2c-port = <&i2c1>;
+			enum-names = "I2C_PORT_BATTERY";
+		};
+		i2c_ec_i2c_sensor: ec_i2c_sensor {
+			i2c-port = <&i2c2>;
+			enum-names = "I2C_PORT_SENSOR";
+		};
+		i2c_ec_i2c_sub_usb_c1: ec_i2c_sub_usb_c1 {
+			i2c-port = <&i2c4>;
+			enum-names = "I2C_PORT_USB_C1_TCPC";
+		};
+		i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 {
+			i2c-port = <&i2c5>;
+			enum-names = "I2C_PORT_USB_C0_TCPC";
+		};
+	};
+};
+
+&adc0 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+};
+
+&i2c2 {
+	status = "okay";
+};
+
+&i2c4 {
+	status = "okay";
+};
+
+&i2c5 {
+	status = "okay";
+};
diff --git a/zephyr/program/nissa/nereid/keyboard.dtsi b/zephyr/program/nissa/nereid/keyboard.dtsi
new file mode 100644
index 0000000000..1742e1a50f
--- /dev/null
+++ b/zephyr/program/nissa/nereid/keyboard.dtsi
@@ -0,0 +1,48 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	kblight {
+		compatible = "cros-ec,kblight-pwm";
+		/*
+		 * Use 324 Hz so that 32Khz clock source is used,
+		 * which is not gated in power saving mode.
+		 */
+		pwms = <&pwm0 0 PWM_HZ(324) PWM_POLARITY_NORMAL>;
+	};
+};
+
+&pwm0 {
+	status = "okay";
+	prescaler-cx = <PWM_PRESCALER_C4>;
+	pinctrl-0 = <&pwm0_gpa0_default>;
+	pinctrl-names = "default";
+};
+
+&cros_kb_raw {
+	status = "okay";
+	/* No KSO2 (it's inverted and implemented by GPIO) */
+	pinctrl-0 = <&ksi0_default
+		     &ksi1_default
+		     &ksi2_default
+		     &ksi3_default
+		     &ksi4_default
+		     &ksi5_default
+		     &ksi6_default
+		     &ksi7_default
+		     &kso0_default
+		     &kso1_default
+		     &kso3_default
+		     &kso4_default
+		     &kso5_default
+		     &kso6_default
+		     &kso7_default
+		     &kso8_default
+		     &kso9_default
+		     &kso10_default
+		     &kso11_default
+		     &kso12_default>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/nissa/nereid/motionsense.dtsi b/zephyr/program/nissa/nereid/motionsense.dtsi
new file mode 100644
index 0000000000..a65bb48fbd
--- /dev/null
+++ b/zephyr/program/nissa/nereid/motionsense.dtsi
@@ -0,0 +1,147 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/motionsense/utils.h>
+
+
+/ {
+	aliases {
+		/*
+		 * Interrupt bindings for sensor devices.
+		 */
+		bmi3xx-int = &base_accel;
+		bma4xx-int = &lid_accel;
+	};
+
+	/*
+	 * Declare mutexes used by sensor drivers.
+	 * A mutex node is used to create an instance of mutex_t.
+	 * A mutex node is referenced by a sensor node if the
+	 * corresponding sensor driver needs to use the
+	 * instance of the mutex.
+	 */
+	motionsense-mutex {
+		compatible = "cros-ec,motionsense-mutex";
+		lid_mutex: lid-mutex {
+		};
+
+		base_mutex: base-mutex {
+		};
+	};
+
+	/* Rotation matrix used by drivers. */
+	motionsense-rotation-ref {
+		compatible = "cros-ec,motionsense-rotation-ref";
+		lid_rot_ref: lid-rotation-ref {
+			mat33 = <0 (-1) 0
+				 (-1) 0 0
+				 0 0 (-1)>;
+		};
+
+		base_rot_ref: base-rotation-ref {
+			mat33 = <0 1 0
+				 (-1) 0 0
+				 0 0 1>;
+		};
+	};
+
+	/*
+	 * Driver specific data. A driver-specific data can be shared with
+	 * different motion sensors while they are using the same driver.
+	 *
+	 * If a node's compatible starts with "cros-ec,accelgyro-", it is for
+	 * a common structure defined in accelgyro.h.
+	 * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for
+	 * "struct als_drv_data_t" in accelgyro.h
+	 */
+	motionsense-sensor-data {
+		bmi323_data: bmi323-drv-data {
+			compatible = "cros-ec,drvdata-bmi3xx";
+			status = "okay";
+		};
+
+		bma422_data: bma422-drv-data {
+			compatible = "cros-ec,drvdata-bma4xx";
+			status = "okay";
+		};
+	};
+
+	/*
+	 * List of motion sensors that creates motion_sensors array.
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
+	 * motion sensor IDs for lid angle calculation.
+	 * TODO(b/238139272): The first entries of the array must be
+	 * accelerometers,then gyroscope. Fix this dependency in the DTS
+	 * processing which makes the devicetree entries independent.
+	 */
+	motionsense-sensor {
+		lid_accel: lid-accel {
+			compatible = "cros-ec,bma4xx";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&lid_mutex>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&lid_rot_ref>;
+			default-range = <2>;
+			drv-data = <&bma422_data>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_accel: base-accel {
+			compatible = "cros-ec,bmi3xx-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&bmi323_data>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_gyro: base-gyro {
+			compatible = "cros-ec,bmi3xx-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&bmi323_data>;
+		};
+	};
+
+	motionsense-sensor-info {
+		compatible = "cros-ec,motionsense-sensor-info";
+
+		/*
+		 * list of GPIO interrupts that have to
+		 * be enabled at initial stage
+		 */
+		sensor-irqs = <&int_imu &int_lid_imu>;
+	};
+};
diff --git a/zephyr/program/nissa/nereid/nereid_vif.xml b/zephyr/program/nissa/nereid/nereid_vif.xml
new file mode 100644
index 0000000000..91c8dbe68b
--- /dev/null
+++ b/zephyr/program/nissa/nereid/nereid_vif.xml
@@ -0,0 +1,350 @@
+<?xml version="1.0" encoding="utf-8"?>
+<vif:VIF xmlns:opt="http://usb.org/VendorInfoFileOptionalContent.xsd" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:vif="http://usb.org/VendorInfoFile.xsd">
+  <vif:VIF_Specification>3.19</vif:VIF_Specification>
+  <vif:VIF_App>
+    <vif:Vendor>USB-IF</vif:Vendor>
+    <vif:Name>VIF Editor</vif:Name>
+    <vif:Version>3.2.4.0</vif:Version>
+  </vif:VIF_App>
+  <vif:Vendor_Name>Google</vif:Vendor_Name>
+  <vif:Model_Part_Number>Nereid</vif:Model_Part_Number>
+  <vif:Product_Revision>1</vif:Product_Revision>
+  <vif:TID>0</vif:TID>
+  <vif:VIF_Product_Type value="0">Port Product</vif:VIF_Product_Type>
+  <vif:Certification_Type value="1">Reference Platform</vif:Certification_Type>
+  <vif:Product>
+    <!--Product Level Content:-->
+  </vif:Product>
+  <vif:Component>
+    <!--Component 0: Port 0-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Component-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Port_Label>0</vif:Port_Label>
+    <vif:Connector_Type value="2">Type-C®</vif:Connector_Type>
+    <vif:USB4_Supported value="false" />
+    <vif:USB_PD_Support value="true" />
+    <vif:PD_Port_Type value="4">DRP</vif:PD_Port_Type>
+    <vif:Type_C_State_Machine value="2">DRP</vif:Type_C_State_Machine>
+    <vif:Port_Battery_Powered value="true" />
+    <vif:BC_1_2_Support value="2">Charging Port</vif:BC_1_2_Support>
+    <vif:Captive_Cable value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;General PD-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Spec_Revision_Major value="3" />
+    <vif:PD_Spec_Revision_Minor value="1" />
+    <vif:PD_Spec_Version_Major value="1" />
+    <vif:PD_Spec_Version_Minor value="3" />
+    <vif:PD_Specification_Revision value="2">Revision 3</vif:PD_Specification_Revision>
+    <vif:SOP_Capable value="true" />
+    <vif:SOP_P_Capable value="true" />
+    <vif:SOP_PP_Capable value="true" />
+    <vif:SOP_P_Debug_Capable value="false" />
+    <vif:SOP_PP_Debug_Capable value="false" />
+    <vif:Manufacturer_Info_Supported_Port value="true" />
+    <vif:Manufacturer_Info_VID_Port value="6353">18D1</vif:Manufacturer_Info_VID_Port>
+    <vif:Manufacturer_Info_PID_Port value="20570">505A</vif:Manufacturer_Info_PID_Port>
+    <vif:Chunking_Implemented_SOP value="true" />
+    <vif:Unchunked_Extended_Messages_Supported value="false" />
+    <vif:Security_Msgs_Supported_SOP value="false" />
+    <vif:Unconstrained_Power value="false" />
+    <vif:Num_Fixed_Batteries value="1" />
+    <vif:Num_Swappable_Battery_Slots value="0" />
+    <vif:ID_Header_Connector_Type_SOP value="2">USB Type-C® Receptacle</vif:ID_Header_Connector_Type_SOP>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Capabilities-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:USB_Comms_Capable value="true" />
+    <vif:DR_Swap_To_DFP_Supported value="true" />
+    <vif:DR_Swap_To_UFP_Supported value="false" />
+    <vif:VCONN_Swap_To_On_Supported value="true" />
+    <vif:VCONN_Swap_To_Off_Supported value="true" />
+    <vif:Responds_To_Discov_SOP_UFP value="false" />
+    <vif:Responds_To_Discov_SOP_DFP value="true" />
+    <vif:Attempts_Discov_SOP value="true" />
+    <vif:Power_Interruption_Available value="0">No Interruption Possible</vif:Power_Interruption_Available>
+    <vif:Data_Reset_Supported value="false" />
+    <vif:Enter_USB_Supported value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;USB Type-C®-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Type_C_Can_Act_As_Host value="true" />
+    <vif:Type_C_Can_Act_As_Device value="false" />
+    <vif:Type_C_Implements_Try_SRC value="true" />
+    <vif:Type_C_Implements_Try_SNK value="false" />
+    <vif:Type_C_Supports_Audio_Accessory value="false" />
+    <vif:Type_C_Is_VCONN_Powered_Accessory value="false" />
+    <vif:Type_C_Is_Debug_Target_SRC value="true" />
+    <vif:Type_C_Is_Debug_Target_SNK value="true" />
+    <vif:RP_Value value="1">1.5A</vif:RP_Value>
+    <vif:Type_C_Port_On_Hub value="false" />
+    <vif:Type_C_Power_Source value="2">Both</vif:Type_C_Power_Source>
+    <vif:Type_C_Sources_VCONN value="true" />
+    <vif:Type_C_Is_Alt_Mode_Controller value="true" />
+    <vif:Type_C_Is_Alt_Mode_Adapter value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Product Power-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Product_Total_Source_Power_mW value="15000">15000 mW</vif:Product_Total_Source_Power_mW>
+    <vif:Port_Source_Power_Type value="0">Assured</vif:Port_Source_Power_Type>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;USB Host-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Host_Supports_USB_Data value="true" />
+    <vif:Host_Speed value="1">USB 3.2 Gen 1x1</vif:Host_Speed>
+    <vif:Host_Contains_Captive_Retimer value="false" />
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:Host_Is_Embedded value="false" />
+    <vif:Host_Suspend_Supported value="true" />
+    <vif:Is_DFP_On_Hub value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Battery Charging 1.2-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:BC_1_2_Charging_Port_Type value="1">CDP</vif:BC_1_2_Charging_Port_Type>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Source-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Power_As_Source value="15000">15000 mW</vif:PD_Power_As_Source>
+    <vif:EPR_Supported_As_Src value="false" />
+    <vif:USB_Suspend_May_Be_Cleared value="false" />
+    <vif:Sends_Pings value="false" />
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="0">FR_Swap not supported</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <vif:Master_Port value="false" />
+    <vif:Num_Src_PDOs value="1" />
+    <vif:PD_OC_Protection value="true" />
+    <vif:PD_OCP_Method value="0">Over-Current Response</vif:PD_OCP_Method>
+    <!--Bundle: SrcPdoList-->
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!--Source PDO 1-->
+        <vif:Src_PDO_Supply_Type value="0">Fixed</vif:Src_PDO_Supply_Type>
+        <vif:Src_PDO_Peak_Current value="0">100% IOC</vif:Src_PDO_Peak_Current>
+        <vif:Src_PDO_Voltage value="100">5000 mV</vif:Src_PDO_Voltage>
+        <vif:Src_PDO_Max_Current value="300">3000 mA</vif:Src_PDO_Max_Current>
+        <vif:Src_PD_OCP_OC_Debounce value="0">0 msec</vif:Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="300">3000 mA</vif:Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Sink-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Power_As_Sink value="45000">45000 mW</vif:PD_Power_As_Sink>
+    <vif:EPR_Supported_As_Snk value="false" />
+    <vif:No_USB_Suspend_May_Be_Set value="true" />
+    <vif:GiveBack_May_Be_Set value="false" />
+    <vif:Higher_Capability_Set value="false" />
+    <vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source value="0">FR_Swap not supported</vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source>
+    <vif:Num_Snk_PDOs value="3" />
+    <!--Bundle: SnkPdoList-->
+    <vif:SnkPdoList>
+      <vif:SnkPDO>
+        <!--Sink PDO 1-->
+        <vif:Snk_PDO_Supply_Type value="0">Fixed</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Voltage value="100">5000 mV</vif:Snk_PDO_Voltage>
+        <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>
+      </vif:SnkPDO>
+      <vif:SnkPDO>
+        <!--Sink PDO 2-->
+        <vif:Snk_PDO_Supply_Type value="1">Battery</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Op_Power value="60">15000 mW</vif:Snk_PDO_Op_Power>
+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>
+        <vif:Snk_PDO_Max_Voltage value="300">15000 mV</vif:Snk_PDO_Max_Voltage>
+      </vif:SnkPDO>
+      <vif:SnkPDO>
+        <!--Sink PDO 3-->
+        <vif:Snk_PDO_Supply_Type value="2">Variable</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>
+        <vif:Snk_PDO_Max_Voltage value="300">15000 mV</vif:Snk_PDO_Max_Voltage>
+        <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>
+      </vif:SnkPDO>
+    </vif:SnkPdoList>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Dual Role-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Accepts_PR_Swap_As_Src value="true" />
+    <vif:Accepts_PR_Swap_As_Snk value="true" />
+    <vif:Requests_PR_Swap_As_Src value="true" />
+    <vif:Requests_PR_Swap_As_Snk value="true" />
+    <vif:FR_Swap_Supported_As_Initial_Sink value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;SOP Discover ID-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:XID_SOP value="0" />
+    <vif:Data_Capable_As_USB_Host_SOP value="true" />
+    <vif:Data_Capable_As_USB_Device_SOP value="false" />
+    <vif:Product_Type_UFP_SOP value="0">Undefined</vif:Product_Type_UFP_SOP>
+    <vif:Product_Type_DFP_SOP value="2">PDUSB Host</vif:Product_Type_DFP_SOP>
+    <vif:DFP_VDO_Port_Number value="0" />
+    <vif:Modal_Operation_Supported_SOP value="false" />
+    <vif:USB_VID_SOP value="6353">18D1</vif:USB_VID_SOP>
+    <vif:PID_SOP value="20570">505A</vif:PID_SOP>
+    <vif:bcdDevice_SOP value="0">0000</vif:bcdDevice_SOP>
+  </vif:Component>
+  <vif:Component>
+    <!--Component 1: Port 1-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Component-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Port_Label>1</vif:Port_Label>
+    <vif:Connector_Type value="2">Type-C®</vif:Connector_Type>
+    <vif:USB4_Supported value="false" />
+    <vif:USB_PD_Support value="true" />
+    <vif:PD_Port_Type value="4">DRP</vif:PD_Port_Type>
+    <vif:Type_C_State_Machine value="2">DRP</vif:Type_C_State_Machine>
+    <vif:Port_Battery_Powered value="true" />
+    <vif:BC_1_2_Support value="2">Charging Port</vif:BC_1_2_Support>
+    <vif:Captive_Cable value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;General PD-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Spec_Revision_Major value="3" />
+    <vif:PD_Spec_Revision_Minor value="1" />
+    <vif:PD_Spec_Version_Major value="1" />
+    <vif:PD_Spec_Version_Minor value="3" />
+    <vif:PD_Specification_Revision value="2">Revision 3</vif:PD_Specification_Revision>
+    <vif:SOP_Capable value="true" />
+    <vif:SOP_P_Capable value="true" />
+    <vif:SOP_PP_Capable value="true" />
+    <vif:SOP_P_Debug_Capable value="false" />
+    <vif:SOP_PP_Debug_Capable value="false" />
+    <vif:Manufacturer_Info_Supported_Port value="true" />
+    <vif:Manufacturer_Info_VID_Port value="6353">18D1</vif:Manufacturer_Info_VID_Port>
+    <vif:Manufacturer_Info_PID_Port value="20570">505A</vif:Manufacturer_Info_PID_Port>
+    <vif:Chunking_Implemented_SOP value="true" />
+    <vif:Unchunked_Extended_Messages_Supported value="false" />
+    <vif:Security_Msgs_Supported_SOP value="false" />
+    <vif:Unconstrained_Power value="false" />
+    <vif:Num_Fixed_Batteries value="1" />
+    <vif:Num_Swappable_Battery_Slots value="0" />
+    <vif:ID_Header_Connector_Type_SOP value="2">USB Type-C® Receptacle</vif:ID_Header_Connector_Type_SOP>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Capabilities-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:USB_Comms_Capable value="true" />
+    <vif:DR_Swap_To_DFP_Supported value="true" />
+    <vif:DR_Swap_To_UFP_Supported value="false" />
+    <vif:VCONN_Swap_To_On_Supported value="true" />
+    <vif:VCONN_Swap_To_Off_Supported value="true" />
+    <vif:Responds_To_Discov_SOP_UFP value="false" />
+    <vif:Responds_To_Discov_SOP_DFP value="true" />
+    <vif:Attempts_Discov_SOP value="true" />
+    <vif:Power_Interruption_Available value="0">No Interruption Possible</vif:Power_Interruption_Available>
+    <vif:Data_Reset_Supported value="false" />
+    <vif:Enter_USB_Supported value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;USB Type-C®-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Type_C_Can_Act_As_Host value="true" />
+    <vif:Type_C_Can_Act_As_Device value="false" />
+    <vif:Type_C_Implements_Try_SRC value="true" />
+    <vif:Type_C_Implements_Try_SNK value="false" />
+    <vif:Type_C_Supports_Audio_Accessory value="false" />
+    <vif:Type_C_Is_VCONN_Powered_Accessory value="false" />
+    <vif:Type_C_Is_Debug_Target_SRC value="true" />
+    <vif:Type_C_Is_Debug_Target_SNK value="true" />
+    <vif:RP_Value value="1">1.5A</vif:RP_Value>
+    <vif:Type_C_Port_On_Hub value="false" />
+    <vif:Type_C_Power_Source value="2">Both</vif:Type_C_Power_Source>
+    <vif:Type_C_Sources_VCONN value="true" />
+    <vif:Type_C_Is_Alt_Mode_Controller value="true" />
+    <vif:Type_C_Is_Alt_Mode_Adapter value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Product Power-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Product_Total_Source_Power_mW value="15000">15000 mW</vif:Product_Total_Source_Power_mW>
+    <vif:Port_Source_Power_Type value="0">Assured</vif:Port_Source_Power_Type>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;USB Host-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Host_Supports_USB_Data value="true" />
+    <vif:Host_Speed value="1">USB 3.2 Gen 1x1</vif:Host_Speed>
+    <vif:Host_Contains_Captive_Retimer value="true" />
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:Host_Is_Embedded value="false" />
+    <vif:Host_Suspend_Supported value="true" />
+    <vif:Is_DFP_On_Hub value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Battery Charging 1.2-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:BC_1_2_Charging_Port_Type value="1">CDP</vif:BC_1_2_Charging_Port_Type>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Source-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Power_As_Source value="15000">15000 mW</vif:PD_Power_As_Source>
+    <vif:EPR_Supported_As_Src value="false" />
+    <vif:USB_Suspend_May_Be_Cleared value="false" />
+    <vif:Sends_Pings value="false" />
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="0">FR_Swap not supported</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <vif:Master_Port value="false" />
+    <vif:Num_Src_PDOs value="1" />
+    <vif:PD_OC_Protection value="true" />
+    <vif:PD_OCP_Method value="0">Over-Current Response</vif:PD_OCP_Method>
+    <!--Bundle: SrcPdoList-->
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!--Source PDO 1-->
+        <vif:Src_PDO_Supply_Type value="0">Fixed</vif:Src_PDO_Supply_Type>
+        <vif:Src_PDO_Peak_Current value="0">100% IOC</vif:Src_PDO_Peak_Current>
+        <vif:Src_PDO_Voltage value="100">5000 mV</vif:Src_PDO_Voltage>
+        <vif:Src_PDO_Max_Current value="300">3000 mA</vif:Src_PDO_Max_Current>
+        <vif:Src_PD_OCP_OC_Debounce value="0">0 msec</vif:Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="300">3000 mA</vif:Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Sink-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Power_As_Sink value="45000">45000 mW</vif:PD_Power_As_Sink>
+    <vif:EPR_Supported_As_Snk value="false" />
+    <vif:No_USB_Suspend_May_Be_Set value="true" />
+    <vif:GiveBack_May_Be_Set value="false" />
+    <vif:Higher_Capability_Set value="false" />
+    <vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source value="0">FR_Swap not supported</vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source>
+    <vif:Num_Snk_PDOs value="3" />
+    <!--Bundle: SnkPdoList-->
+    <vif:SnkPdoList>
+      <vif:SnkPDO>
+        <!--Sink PDO 1-->
+        <vif:Snk_PDO_Supply_Type value="0">Fixed</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Voltage value="100">5000 mV</vif:Snk_PDO_Voltage>
+        <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>
+      </vif:SnkPDO>
+      <vif:SnkPDO>
+        <!--Sink PDO 2-->
+        <vif:Snk_PDO_Supply_Type value="1">Battery</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Op_Power value="60">15000 mW</vif:Snk_PDO_Op_Power>
+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>
+        <vif:Snk_PDO_Max_Voltage value="300">15000 mV</vif:Snk_PDO_Max_Voltage>
+      </vif:SnkPDO>
+      <vif:SnkPDO>
+        <!--Sink PDO 3-->
+        <vif:Snk_PDO_Supply_Type value="2">Variable</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>
+        <vif:Snk_PDO_Max_Voltage value="300">15000 mV</vif:Snk_PDO_Max_Voltage>
+        <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>
+      </vif:SnkPDO>
+    </vif:SnkPdoList>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Dual Role-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Accepts_PR_Swap_As_Src value="true" />
+    <vif:Accepts_PR_Swap_As_Snk value="true" />
+    <vif:Requests_PR_Swap_As_Src value="true" />
+    <vif:Requests_PR_Swap_As_Snk value="true" />
+    <vif:FR_Swap_Supported_As_Initial_Sink value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;SOP Discover ID-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:XID_SOP value="0" />
+    <vif:Data_Capable_As_USB_Host_SOP value="true" />
+    <vif:Data_Capable_As_USB_Device_SOP value="false" />
+    <vif:Product_Type_UFP_SOP value="0">Undefined</vif:Product_Type_UFP_SOP>
+    <vif:Product_Type_DFP_SOP value="2">PDUSB Host</vif:Product_Type_DFP_SOP>
+    <vif:DFP_VDO_Port_Number value="1" />
+    <vif:Modal_Operation_Supported_SOP value="false" />
+    <vif:USB_VID_SOP value="6353">18D1</vif:USB_VID_SOP>
+    <vif:PID_SOP value="20570">505A</vif:PID_SOP>
+    <vif:bcdDevice_SOP value="0">0000</vif:bcdDevice_SOP>
+  </vif:Component>
+</vif:VIF>
\ No newline at end of file
diff --git a/zephyr/program/nissa/nereid/overlay.dtsi b/zephyr/program/nissa/nereid/overlay.dtsi
new file mode 100644
index 0000000000..36d30a0fce
--- /dev/null
+++ b/zephyr/program/nissa/nereid/overlay.dtsi
@@ -0,0 +1,409 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <cros/thermistor/thermistor.dtsi>
+#include <dt-bindings/usb_pd_tcpm.h>
+
+/ {
+	aliases {
+		gpio-cbi-wp = &gpio_ec_cbi_wp;
+		gpio-wp = &gpio_ec_wp_odl;
+		int-wp = &int_wp_l;
+		/*
+		 * USB-C: interrupt input.
+		 * I2C pins are on i2c_ec_i2c_sub_usb_c1
+		 */
+		gpio-usb-c1-int-odl = &gpio_sb_1;
+		/*
+		 * USB-A: VBUS enable output
+		 * LTE: power enable output
+		 */
+		gpio-en-usb-a1-vbus = &gpio_sb_2;
+		/*
+		 * HDMI: power enable output, HDMI enable output,
+		 * and HPD input
+		 */
+		gpio-en-rails-odl = &gpio_sb_1;
+		gpio-hdmi-en-odl = &gpio_sb_4;
+		gpio-hpd-odl = &gpio_sb_3;
+		/*
+		 * Enable S5 rails for LTE sub-board
+		 */
+		gpio-en-sub-s5-rails = &gpio_sb_2;
+	};
+
+
+	ec-console {
+		compatible = "ec-console";
+		disabled = "events", "lpc", "hostcmd";
+	};
+
+	batteries {
+		default_battery: smp {
+			compatible = "smp,l20m3pg0", "battery-smart";
+		};
+	};
+
+	hibernate-wake-pins {
+		compatible = "cros-ec,hibernate-wake-pins";
+		wakeup-irqs = <
+			&int_power_button
+			&int_lid_open
+		>;
+	};
+
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_power_button: power_button {
+			irq-pin = <&gpio_gsc_ec_pwr_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_button_interrupt";
+		};
+		int_vol_down: vol_down {
+			irq-pin = <&gpio_voldn_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+		int_vol_up: vol_up {
+			irq-pin = <&gpio_volup_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+		int_wp_l: wp_l {
+			irq-pin = <&gpio_ec_wp_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "switch_interrupt";
+		};
+		int_lid_open: lid_open {
+			irq-pin = <&gpio_lid_open>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "lid_interrupt";
+		};
+		int_tablet_mode: tablet_mode {
+			irq-pin = <&gpio_tablet_mode_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "gmr_tablet_switch_isr";
+		};
+		int_imu: ec_imu {
+			irq-pin = <&gpio_imu_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "bmi3xx_interrupt";
+		};
+		int_lid_imu: lid_imu {
+			irq-pin = <&gpio_acc_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "bma4xx_interrupt";
+		};
+		int_usb_c0: usb_c0 {
+			irq-pin = <&gpio_usb_c0_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "usb_c0_interrupt";
+		};
+		int_usb_c1: usb_c1 {
+			irq-pin = <&gpio_sb_1>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "usb_c1_interrupt";
+		};
+	};
+
+	unused-pins {
+		compatible = "unused-gpios";
+		unused-gpios = <&gpioc 3 0>,
+			       <&gpiod 4 0>,
+			       <&gpiod 7 0>,
+			       <&gpioh 2 0>,
+			       <&gpioj 7 0>,
+			       <&gpiol 4 0>;
+	};
+
+	named-gpios {
+		/*
+		 * EC doesn't take any specific action on CC/SBU disconnect due to
+		 * fault, but this definition is useful for hardware testing.
+		 */
+		gpio_usb_c0_prot_fault_odl: usb_c0_prot_fault_odl {
+			gpios = <&gpiok 6 GPIO_INPUT_PULL_UP>;
+		};
+
+		gpio_sb_1: sb_1 {
+			gpios = <&gpioe 6 0>;
+			no-auto-init;
+		};
+		gpio_sb_2: sb_2 {
+			gpios = <&gpiof 0 0>;
+			no-auto-init;
+		};
+
+		gpio_sb_3: sb_3 {
+			gpios = <&gpioe 7 0>;
+			no-auto-init;
+		};
+		gpio_sb_4: sb_4 {
+			gpios = <&gpioe 0 0>;
+			no-auto-init;
+		};
+	};
+
+	temp_memory: memory {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_1>;
+	};
+	temp_charger: charger {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_2>;
+	};
+	temp_ambient: ambient {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_3>;
+	};
+
+	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
+		memory {
+			temp_fan_off = <35>;
+			temp_fan_max = <60>;
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_memory>;
+		};
+		charger {
+			temp_fan_off = <35>;
+			temp_fan_max = <60>;
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_charger>;
+		};
+		ambient {
+			temp_fan_off = <35>;
+			temp_fan_max = <60>;
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_ambient>;
+		};
+	};
+
+	usba {
+		compatible = "cros-ec,usba-port-enable-pins";
+		/*
+		 * sb_2 is only configured as GPIO when USB-A1 is present,
+		 * but it's still safe to control when disabled.
+		 *
+		 * ILIM_SEL pins are referred to by legacy enum name,
+		 * GPIO_USB*_ILIM_SEL. The one for port A1 is unused on
+		 * sub-boards that don't have USB-A so is safe to control
+		 * regardless of system configuration.
+		 */
+		enable-pins = <&gpio_en_usb_a0_vbus &gpio_sb_2>;
+		status = "okay";
+	};
+
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+			bc12 = <&bc12_port0>;
+			chg = <&chg_port0>;
+			tcpc = <&usbpd0>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_0>;
+			};
+		};
+		port0-muxes {
+			virtual_mux_0: virtual-mux-0 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+		port1@1 {
+			compatible = "named-usbc-port";
+			reg = <1>;
+			bc12 = <&bc12_port1>;
+			chg = <&chg_port1>;
+			tcpc = <&tcpc_port1>;
+			usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_1 &tcpci_mux_1>;
+			};
+			usb_mux_chain_1_no_mux: usb-mux-chain-1-no-mux {
+				compatible = "cros-ec,usb-mux-chain";
+				alternative-chain;
+				usb-muxes = <&virtual_mux_1>;
+			};
+		};
+		port1-muxes {
+			virtual_mux_1: virtual-mux-1 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+			tcpci_mux_1: tcpci-mux-1 {
+				compatible = "parade,usbc-mux-ps8xxx";
+			};
+		};
+	};
+};
+
+&gpio_acc_int_l {
+	gpios = <&gpioc 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+};
+&gpio_imu_int_l {
+	gpios = <&gpioj 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+};
+&gpio_vccin_aux_vid0 {
+	gpios = <&gpiod 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+};
+&gpio_vccin_aux_vid1 {
+	gpios = <&gpiok 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+};
+
+&gpio_ec_prochot_odl {
+	gpios = <&gpioi 1 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>;
+};
+
+&thermistor_3V3_51K1_47K_4050B {
+	status = "okay";
+};
+
+&adc_ec_vsense_pp3300_s5 {
+	/*
+	 * Voltage divider on input has 47k upper and 220k lower legs with 3 V
+	 * full-scale reading on the ADC. Apply the largest possible multiplier
+	 * (without overflowing int32) to get the best possible approximation
+	 * of the actual ratio, but derate by a factor of two to ensure
+	 * unexpectedly high values won't overflow.
+	 */
+	mul = <(715828 / 2)>;
+	div = <(589820 / 2)>;
+};
+
+&adc0 {
+	pinctrl-0 = <&adc0_ch0_gpi0_default
+		     &adc0_ch2_gpi2_default
+		     &adc0_ch3_gpi3_default
+		     &adc0_ch13_gpl0_default
+		     &adc0_ch14_gpl1_default>;
+	pinctrl-names = "default";
+};
+
+&pinctrl {
+	i2c4_clk_gpe0_sleep: i2c4_clk_gpe0_sleep {
+		pinmuxs = <&pinctrle 0 IT8XXX2_ALT_DEFAULT>;
+	};
+	i2c4_data_gpe7_sleep: i2c4_data_gpe7_sleep {
+		pinmuxs = <&pinctrle 7 IT8XXX2_ALT_DEFAULT>;
+	};
+	i2c2_clk_gpf6_default: i2c2_clk_gpf6_default {
+		gpio-voltage = "1v8";
+	};
+	i2c2_data_gpf7_default: i2c2_data_gpf7_default {
+		gpio-voltage = "1v8";
+	};
+};
+
+&i2c0 {
+	label = "I2C_EEPROM";
+	clock-frequency = <I2C_BITRATE_FAST>;
+
+	cbi_eeprom: eeprom@50 {
+		compatible = "atmel,at24";
+		reg = <0x50>;
+		size = <2048>;
+		pagesize = <16>;
+		address-width = <8>;
+		timeout = <5>;
+	};
+	pinctrl-0 = <&i2c0_clk_gpb3_default
+		     &i2c0_data_gpb4_default>;
+	pinctrl-names = "default";
+};
+
+&i2c1 {
+	label = "I2C_BATTERY";
+	clock-frequency = <50000>;
+	pinctrl-0 = <&i2c1_clk_gpc1_default
+		     &i2c1_data_gpc2_default>;
+	pinctrl-names = "default";
+};
+
+&i2c2 {
+	label = "I2C_SENSOR";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c2_clk_gpf6_default
+		     &i2c2_data_gpf7_default>;
+	pinctrl-names = "default";
+};
+
+&i2c4 {
+	label = "I2C_SUB_C1_TCPC";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+	pinctrl-0 = <&i2c4_clk_gpe0_default
+		     &i2c4_data_gpe7_default>;
+	pinctrl-1 = <&i2c4_clk_gpe0_sleep
+		     &i2c4_data_gpe7_sleep>;
+	pinctrl-names = "default", "sleep";
+
+	bc12_port1: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+	};
+
+	chg_port1: sm5803@32 {
+		compatible = "siliconmitus,sm5803";
+		status = "okay";
+		reg = <0x32>;
+	};
+
+	tcpc_port1: ps8745@b {
+		compatible = "parade,ps8xxx";
+		reg = <0xb>;
+		tcpc-flags = <(TCPC_FLAGS_TCPCI_REV2_0)>;
+	};
+};
+
+&i2c_ec_i2c_sub_usb_c1 {
+	/*
+	 * Dynamic speed setting is used for AP-controlled firmware update
+	 * of PS8745 TCPC/redriver: the AP lowers speed to 400 kHz in order
+	 * to use more efficient window programming, then sets it back when
+	 * done.
+	 */
+	dynamic-speed;
+};
+
+&i2c5 {
+	label = "I2C_USB_C0_TCPC";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+	pinctrl-0 = <&i2c5_clk_gpa4_default
+		     &i2c5_data_gpa5_default>;
+	pinctrl-names = "default";
+
+	bc12_port0: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+	};
+
+	chg_port0: sm5803@32 {
+		compatible = "siliconmitus,sm5803";
+		status = "okay";
+		reg = <0x32>;
+	};
+};
+
+&usbpd0 {
+	status = "okay";
+};
diff --git a/zephyr/program/nissa/nereid/power_signals.dtsi b/zephyr/program/nissa/nereid/power_signals.dtsi
new file mode 100644
index 0000000000..8affae03b1
--- /dev/null
+++ b/zephyr/program/nissa/nereid/power_signals.dtsi
@@ -0,0 +1,223 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	chosen {
+		intel-ap-pwrseq,espi = &espi0;
+	};
+
+	common-pwrseq {
+		compatible = "intel,ap-pwrseq";
+
+		sys-pwrok-delay = <10>;
+		all-sys-pwrgd-timeout = <20>;
+	};
+
+	pwr-en-pp5000-s5 {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PP5000_S5 enable output to regulator";
+		enum-name = "PWR_EN_PP5000_A";
+		gpios = <&gpiok 5 0>;
+		output;
+	};
+	pwr-en-pp3300-s5 {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PP3300_S5 enable output to LS";
+		enum-name = "PWR_EN_PP3300_A";
+		gpios = <&gpioc 5 0>;
+		output;
+	};
+	pwr-pg-ec-rsmrst-odl {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST power good from regulator";
+		enum-name = "PWR_RSMRST";
+		gpios = <&gpioe 1 0>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-ec-pch-rsmrst-odl {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST output to PCH";
+		enum-name = "PWR_EC_PCH_RSMRST";
+		gpios = <&gpioh 0 0>;
+		output;
+	};
+	pwr-slp-s0-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_S0_L input from PCH";
+		enum-name = "PWR_SLP_S0";
+		gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-slp-s3-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_S3_L input from PCH";
+		enum-name = "PWR_SLP_S3";
+		gpios = <&gpioh 3 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-slp-sus-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_SUS_L input from PCH";
+		enum-name = "PWR_SLP_SUS";
+		gpios = <&gpiog 2 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-ec-soc-dsw-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "DSW_PWROK output to PCH";
+		enum-name = "PWR_EC_SOC_DSW_PWROK";
+		gpios = <&gpiol 7 0>;
+		output;
+	};
+	pwr-vccst-pwrgd-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "VCCST_PWRGD output to PCH";
+		enum-name = "PWR_VCCST_PWRGD";
+		gpios = <&gpioe 5 (GPIO_OPEN_DRAIN | GPIO_VOLTAGE_1P8)>;
+		output;
+	};
+	pwr-imvp9-vrrdy-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "VRRDY input from IMVP9";
+		enum-name = "PWR_IMVP9_VRRDY";
+		gpios = <&gpioj 4 0>;
+	};
+	pwr-pch-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PCH_PWROK output to PCH";
+		enum-name = "PWR_PCH_PWROK";
+		gpios = <&gpiod 6 GPIO_OPEN_DRAIN>;
+		output;
+	};
+	pwr-ec-pch-sys-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_PWROK output to PCH";
+		enum-name = "PWR_EC_PCH_SYS_PWROK";
+		gpios = <&gpiof 2 0>;
+		output;
+	};
+	pwr-sys-rst-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_RESET# output to PCH";
+		enum-name = "PWR_SYS_RST";
+		gpios = <&gpiod 1 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>;
+		output;
+	};
+	pwr-slp-s4 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S4 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S4";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4";
+		vw-invert;
+	};
+	pwr-slp-s5 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S5 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S5";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5";
+		vw-invert;
+	};
+	pwr-all-sys-pwrgd {
+		/*
+		 * This is a board level signal, since this
+		 * signal needs some special processing.
+		 */
+		compatible = "intel,ap-pwrseq-external";
+		dbg-label = "Combined all power good";
+		enum-name = "PWR_ALL_SYS_PWRGD";
+	};
+	pwr-adc-pp3300 {
+		compatible = "intel,ap-pwrseq-adc";
+		dbg-label = "PP3300_PROC";
+		enum-name = "PWR_DSW_PWROK";
+		trigger-high = <&vcmp0>;
+		trigger-low = <&vcmp1>;
+	};
+	pwr-adc-pp1p05 {
+		compatible = "intel,ap-pwrseq-adc";
+		dbg-label = "PP1P05_PROC";
+		enum-name = "PWR_PG_PP1P05";
+		trigger-high = <&vcmp2>;
+		trigger-low = <&vcmp3>;
+	};
+
+};
+
+/*
+ * Because the power signals directly reference the GPIOs,
+ * the correspinding named-gpios need to have no-auto-init set.
+ */
+&gpio_ec_soc_dsw_pwrok {
+	no-auto-init;
+};
+&gpio_ec_soc_pch_pwrok_od {
+	no-auto-init;
+};
+&gpio_ec_soc_rsmrst_l {
+	no-auto-init;
+};
+&gpio_ec_soc_sys_pwrok {
+	no-auto-init;
+};
+&gpio_ec_soc_vccst_pwrgd_od {
+	no-auto-init;
+};
+&gpio_en_pp3300_s5 {
+	no-auto-init;
+};
+&gpio_en_pp5000_s5 {
+	no-auto-init;
+};
+&gpio_imvp91_vrrdy_od {
+	no-auto-init;
+};
+&gpio_rsmrst_pwrgd_l {
+	no-auto-init;
+};
+&gpio_slp_s0_l {
+	no-auto-init;
+};
+&gpio_slp_s3_l {
+	no-auto-init;
+};
+&gpio_slp_sus_l {
+	no-auto-init;
+};
+&gpio_sys_rst_odl {
+	no-auto-init;
+};
+&vcmp0 {
+	status = "okay";
+	scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>;
+	comparison = <IT8XXX2_VCMP_GREATER>;
+	/*
+	 * This is 90% of nominal voltage considering voltage
+	 * divider on ADC input.
+	 */
+	threshold-mv = <2448>;
+	io-channels = <&adc0 0>;
+};
+&vcmp1 {
+	status = "okay";
+	scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>;
+	comparison = <IT8XXX2_VCMP_LESS_OR_EQUAL>;
+	threshold-mv = <2448>;
+	io-channels = <&adc0 0>;
+};
+&vcmp2 {
+	status = "okay";
+	scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>;
+	comparison = <IT8XXX2_VCMP_GREATER>;
+	/* Setting at 90% of nominal voltage */
+	threshold-mv = <945>;
+	io-channels = <&adc0 14>;
+};
+&vcmp3 {
+	status = "okay";
+	scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>;
+	comparison = <IT8XXX2_VCMP_LESS_OR_EQUAL>;
+	threshold-mv = <945>;
+	io-channels = <&adc0 14>;
+};
diff --git a/zephyr/program/nissa/nereid/project.conf b/zephyr/program/nissa/nereid/project.conf
new file mode 100644
index 0000000000..ff87f6e591
--- /dev/null
+++ b/zephyr/program/nissa/nereid/project.conf
@@ -0,0 +1,24 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_BOARD_NEREID=y
+
+# Ensure recovery key combination (esc+refresh+power) is reliable: b/236580049
+CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI2=y
+
+# Sensor drivers
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y
+CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y
+CONFIG_PLATFORM_EC_MAX_SENSOR_FREQ_MILLIHZ=100000
+
+# No fan supported, and tach is default-enabled
+CONFIG_TACH_IT8XXX2=n
+
+# Both ports use a PI5USB2546 smart switch with CTL1..3 fixed high,
+# for SDP2 or CDP only.
+CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART=y
+CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_CDP_SDP_ONLY=y
+CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_DEFAULT_CDP=y
+CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_INVERTED=y
diff --git a/zephyr/program/nissa/nereid/project.overlay b/zephyr/program/nissa/nereid/project.overlay
new file mode 100644
index 0000000000..ee367b9c28
--- /dev/null
+++ b/zephyr/program/nissa/nereid/project.overlay
@@ -0,0 +1,14 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "../cbi.dtsi"
+#include "../shi.dtsi"
+
+#include "generated.dtsi"
+#include "keyboard.dtsi"
+#include "motionsense.dtsi"
+#include "overlay.dtsi"
+#include "power_signals.dtsi"
+#include "pwm_leds.dtsi"
diff --git a/zephyr/program/nissa/nereid/pwm_leds.dtsi b/zephyr/program/nissa/nereid/pwm_leds.dtsi
new file mode 100644
index 0000000000..aa4a76b271
--- /dev/null
+++ b/zephyr/program/nissa/nereid/pwm_leds.dtsi
@@ -0,0 +1,60 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	pwmleds {
+		compatible = "pwm-leds";
+		pwm_led0: pwm_led_0 {
+			pwms = <&pwm1 1 PWM_HZ(1296) PWM_POLARITY_INVERTED>,
+			       <&pwm2 2 PWM_HZ(1296) PWM_POLARITY_INVERTED>,
+			       <&pwm3 3 PWM_HZ(1296) PWM_POLARITY_INVERTED>;
+		};
+	};
+
+	cros-pwmleds {
+		compatible = "cros-ec,pwm-leds";
+
+		leds = <&pwm_led0>;
+
+				/*<red green blue>*/
+		color-map-red    = <100   0    0>;
+		color-map-green  = <  0 100    0>;
+		color-map-blue   = <  0   0  100>;
+		color-map-yellow = <  0  50   50>;
+		color-map-white  = <100 100  100>;
+		color-map-amber  = <100  15    0>;
+
+		brightness-range = <100 100 100 0 0 0>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pwm_led_0@0 {
+			reg = <0>;
+			ec-led-name = "EC_LED_ID_BATTERY_LED";
+		};
+	};
+};
+
+&pwm1 {
+	status = "okay";
+	prescaler-cx = <PWM_PRESCALER_C4>;
+	pinctrl-0 = <&pwm1_gpa1_default>;
+	pinctrl-names = "default";
+};
+
+&pwm2 {
+	status = "okay";
+	prescaler-cx = <PWM_PRESCALER_C4>;
+	pinctrl-0 = <&pwm2_gpa2_default>;
+	pinctrl-names = "default";
+};
+
+&pwm3 {
+	status = "okay";
+	prescaler-cx = <PWM_PRESCALER_C4>;
+	pinctrl-0 = <&pwm3_gpa3_default>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/nissa/nereid/src/charger.c b/zephyr/program/nissa/nereid/src/charger.c
new file mode 100644
index 0000000000..c8b09bd82c
--- /dev/null
+++ b/zephyr/program/nissa/nereid/src/charger.c
@@ -0,0 +1,55 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "charger.h"
+#include "console.h"
+#include "driver/charger/sm5803.h"
+#include "extpower.h"
+#include "usb_pd.h"
+
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+int extpower_is_present(void)
+{
+	int port;
+	int rv;
+	bool acok;
+
+	for (port = 0; port < board_get_usb_pd_port_count(); port++) {
+		rv = sm5803_is_acok(port, &acok);
+		if ((rv == EC_SUCCESS) && acok)
+			return 1;
+	}
+
+	return 0;
+}
+
+/*
+ * Nereid does not have a GPIO indicating whether extpower is present,
+ * so detect using the charger(s).
+ */
+__override void board_check_extpower(void)
+{
+	static int last_extpower_present;
+	int extpower_present = extpower_is_present();
+
+	if (last_extpower_present ^ extpower_present)
+		extpower_handle_update(extpower_present);
+
+	last_extpower_present = extpower_present;
+}
+
+__override void board_hibernate(void)
+{
+	/* Shut down the chargers */
+	if (board_get_usb_pd_port_count() == 2)
+		sm5803_hibernate(CHARGER_SECONDARY);
+	sm5803_hibernate(CHARGER_PRIMARY);
+	LOG_INF("Charger(s) hibernated");
+	cflush();
+}
diff --git a/zephyr/program/nissa/nereid/src/hdmi.c b/zephyr/program/nissa/nereid/src/hdmi.c
new file mode 100644
index 0000000000..5025472c6d
--- /dev/null
+++ b/zephyr/program/nissa/nereid/src/hdmi.c
@@ -0,0 +1,29 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "nissa_hdmi.h"
+
+#include <cros_board_info.h>
+
+__override void nissa_configure_hdmi_power_gpios(void)
+{
+	/*
+	 * Nereid versions before 2 need hdmi-en-odl to be
+	 * pulled down to enable VCC on the HDMI port, but later
+	 * versions (and other boards) disconnect this so
+	 * the port's VCC directly follows en-rails-odl. Only
+	 * configure the GPIO if needed, to save power.
+	 */
+	uint32_t board_version = 0;
+
+	/* CBI errors ignored, will configure the pin */
+	cbi_get_board_version(&board_version);
+	if (board_version < 2) {
+		nissa_configure_hdmi_vcc();
+	}
+
+	/* Still always need core rails controlled */
+	nissa_configure_hdmi_rails();
+}
diff --git a/zephyr/program/nissa/nereid/src/keyboard.c b/zephyr/program/nissa/nereid/src/keyboard.c
new file mode 100644
index 0000000000..322f7d8a54
--- /dev/null
+++ b/zephyr/program/nissa/nereid/src/keyboard.c
@@ -0,0 +1,29 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+
+test_export_static const struct ec_response_keybd_config nereid_kb_legacy = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_FORWARD,		/* T2 */
+		TK_REFRESH,		/* T3 */
+		TK_FULLSCREEN,		/* T4 */
+		TK_OVERVIEW,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &nereid_kb_legacy;
+}
diff --git a/zephyr/program/nissa/nereid/src/usbc.c b/zephyr/program/nissa/nereid/src/usbc.c
new file mode 100644
index 0000000000..cb695f2d5d
--- /dev/null
+++ b/zephyr/program/nissa/nereid/src/usbc.c
@@ -0,0 +1,335 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_state.h"
+#include "chipset.h"
+#include "driver/charger/sm5803.h"
+#include "driver/tcpm/it83xx_pd.h"
+#include "driver/tcpm/ps8xxx_public.h"
+#include "driver/tcpm/tcpci.h"
+#include "hooks.h"
+#include "system.h"
+#include "usb_mux.h"
+
+#include <zephyr/logging/log.h>
+
+#include <ap_power/ap_power.h>
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+/* Vconn control for integrated ITE TCPC */
+void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
+{
+	/* Vconn control is only for port 0 */
+	if (port)
+		return;
+
+	if (cc_pin == USBPD_CC_PIN_1)
+		gpio_pin_set_dt(
+			GPIO_DT_FROM_NODELABEL(gpio_en_usb_c0_cc1_vconn),
+			!!enabled);
+	else
+		gpio_pin_set_dt(
+			GPIO_DT_FROM_NODELABEL(gpio_en_usb_c0_cc2_vconn),
+			!!enabled);
+}
+
+__override bool pd_check_vbus_level(int port, enum vbus_level level)
+{
+	return sm5803_check_vbus_level(port, level);
+}
+
+/*
+ * Putting chargers into LPM when in suspend reduces power draw by about 8mW
+ * per charger, but also seems critical to correct operation in source mode:
+ * if chargers are not in LPM when a sink is first connected, VBUS sourcing
+ * works even if the partner is later removed (causing LPM entry) and
+ * reconnected (causing LPM exit). If in LPM initially, sourcing VBUS
+ * consistently causes the charger to report (apparently spurious) overcurrent
+ * failures.
+ *
+ * In short, this is important to making things work correctly but we don't
+ * understand why.
+ */
+static void board_chargers_suspend(struct ap_power_ev_callback *const cb,
+				   const struct ap_power_ev_data data)
+{
+	void (*fn)(int chgnum);
+
+	switch (data.event) {
+	case AP_POWER_SUSPEND:
+		fn = sm5803_enable_low_power_mode;
+		break;
+	case AP_POWER_RESUME:
+		fn = sm5803_disable_low_power_mode;
+		break;
+	/* LCOV_EXCL_START can only happen if init doesn't match these cases */
+	default:
+		LOG_WRN("%s: power event %d is not recognized", __func__,
+			data.event);
+		return;
+		/* LCOV_EXCL_STOP */
+	}
+
+	fn(CHARGER_PRIMARY);
+	if (board_get_charger_chip_count() > 1)
+		fn(CHARGER_SECONDARY);
+}
+
+static int board_chargers_suspend_init(void)
+{
+	static struct ap_power_ev_callback cb = {
+		.handler = board_chargers_suspend,
+		.events = AP_POWER_SUSPEND | AP_POWER_RESUME,
+	};
+	ap_power_ev_add_callback(&cb);
+	return 0;
+}
+SYS_INIT(board_chargers_suspend_init, APPLICATION, 0);
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count());
+	int i;
+	int old_port;
+	int rv;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	old_port = charge_manager_get_active_charge_port();
+	LOG_INF("Charge update: p%d -> p%d", old_port, port);
+
+	/* Check if port is sourcing VBUS. */
+	if (port != CHARGE_PORT_NONE && charger_is_sourcing_otg_power(port)) {
+		LOG_WRN("Skip enable p%d: already sourcing", port);
+		return EC_ERROR_INVAL;
+	}
+
+	/* Disable sinking on all ports except the desired one */
+	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+		if (i == port)
+			continue;
+
+		if (sm5803_vbus_sink_enable(i, 0))
+			/*
+			 * Do not early-return because this can fail during
+			 * power-on which would put us into a loop.
+			 */
+			LOG_WRN("p%d: sink path disable failed.", i);
+	}
+
+	/* Don't enable anything (stop here) if no ports were requested */
+	if ((port == CHARGE_PORT_NONE) || (old_port == port))
+		return EC_SUCCESS;
+
+	/*
+	 * Stop the charger IC from switching while changing ports.  Otherwise,
+	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
+	 */
+	if (old_port != CHARGE_PORT_NONE)
+		charger_discharge_on_ac(1);
+
+	/* Enable requested charge port. */
+	rv = sm5803_vbus_sink_enable(port, 1);
+	if (rv)
+		LOG_WRN("p%d: sink path enable failed: code %d", port, rv);
+
+	/* Allow the charger IC to begin/continue switching. */
+	charger_discharge_on_ac(0);
+
+	return rv;
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	/*
+	 * TCPC 0 is embedded in the EC and processes interrupts in the chip
+	 * code (it83xx/intc.c). This function only needs to poll port C1 if
+	 * present.
+	 */
+	uint16_t status = 0;
+	int regval;
+
+	/* Is the C1 port present and its IRQ line asserted? */
+	if (board_get_usb_pd_port_count() == 2 &&
+	    !gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) {
+		/*
+		 * C1 IRQ is shared between BC1.2 and TCPC; poll TCPC to see if
+		 * it asserted the IRQ.
+		 */
+		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
+			if (regval)
+				status = PD_STATUS_TCPC_ALERT_1;
+		}
+	}
+
+	return status;
+}
+
+void pd_power_supply_reset(int port)
+{
+	int prev_en;
+
+	if (port < 0 || port >= board_get_usb_pd_port_count())
+		return;
+
+	prev_en = charger_is_sourcing_otg_power(port);
+
+	/* Disable Vbus */
+	charger_enable_otg_power(port, 0);
+
+	/* Discharge Vbus if previously enabled */
+	if (prev_en)
+		sm5803_set_vbus_disch(port, 1);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	enum ec_error_list rv;
+
+	if (port < 0 || port > board_get_usb_pd_port_count()) {
+		LOG_WRN("Port C%d does not exist, cannot enable VBUS", port);
+		return EC_ERROR_INVAL;
+	}
+
+	/* Disable sinking */
+	rv = sm5803_vbus_sink_enable(port, 0);
+	if (rv) {
+		LOG_WRN("C%d failed to disable sinking: %d", port, rv);
+		return rv;
+	}
+
+	/* Disable Vbus discharge */
+	rv = sm5803_set_vbus_disch(port, 0);
+	if (rv) {
+		LOG_WRN("C%d failed to clear VBUS discharge: %d", port, rv);
+		return rv;
+	}
+
+	/* Provide Vbus */
+	rv = charger_enable_otg_power(port, 1);
+	if (rv) {
+		LOG_WRN("C%d failed to enable VBUS sourcing: %d", port, rv);
+		return rv;
+	}
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	int rv;
+	const int current = rp == TYPEC_RP_3A0 ? 3000 : 1500;
+
+	rv = charger_set_otg_current_voltage(port, current, 5000);
+	if (rv != EC_SUCCESS) {
+		LOG_WRN("Failed to set source ilimit on port %d to %d: %d",
+			port, current, rv);
+	}
+}
+
+/* LCOV_EXCL_START function does nothing, but is required for build */
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * Do nothing. The integrated TCPC for C0 lacks a dedicated reset
+	 * command, and C1 (if present) doesn't have a reset pin connected
+	 * to the EC.
+	 */
+}
+/* LCOV_EXCL_STOP */
+
+#define INT_RECHECK_US 5000
+
+/* C0 interrupt line shared by BC 1.2 and charger */
+
+static void check_c0_line(void);
+DECLARE_DEFERRED(check_c0_line);
+
+static void notify_c0_chips(void)
+{
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+	sm5803_interrupt(0);
+}
+
+static void check_c0_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips
+	 */
+	if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl))) {
+		notify_c0_chips();
+		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+	}
+}
+
+void usb_c0_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c0_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c0_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+}
+
+/* C1 interrupt line shared by BC 1.2, TCPC, and charger */
+/* LCOV_EXCL_START schedule_deferred_pd_interrupt() is untestable */
+void usb_c1_interrupt(enum gpio_signal s)
+{
+	/* Charger and BC1.2 are handled in board_process_pd_alert */
+	schedule_deferred_pd_interrupt(1);
+}
+/* LCOV_EXCL_STOP */
+
+/*
+ * Handle charger interrupts in the PD task. Not doing so can lead to a priority
+ * inversion where we fail to respond to TCPC alerts quickly enough because we
+ * don't get another edge on a shared IRQ until the other interrupt is cleared
+ * (or the IRQ is polled again), which happens in lower-priority tasks: the
+ * high-priority type-C handler is thus blocked on the lower-priority one(s).
+ *
+ * To avoid that, we run charger and BC1.2 interrupts synchronously alongside
+ * PD interrupts so they have the same priority.
+ */
+void board_process_pd_alert(int port)
+{
+	/*
+	 * Port 0 doesn't use an external TCPC, so its interrupts don't need
+	 * this special handling.
+	 */
+	if (port != 1)
+		return;
+
+	if (!gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) {
+		sm5803_handle_interrupt(port);
+		usb_charger_task_set_event_sync(1, USB_CHG_EVENT_BC12);
+	}
+	/*
+	 * Immediately schedule another TCPC interrupt if it seems we haven't
+	 * cleared all pending interrupts.
+	 */
+	if (!gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl)))
+		schedule_deferred_pd_interrupt(port);
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	int chg_det = 0;
+
+	sm5803_get_chg_det(port, &chg_det);
+
+	return chg_det;
+}
diff --git a/zephyr/program/nissa/nissa.csv b/zephyr/program/nissa/nissa.csv
new file mode 100644
index 0000000000..45b73ea229
--- /dev/null
+++ b/zephyr/program/nissa/nissa.csv
@@ -0,0 +1,122 @@
+Signal Name,Subsystem,Description,DIR,Int,I/O Type,Internal PU,I/O Voltage,ICs attached,NPCX993 (Nivviks),NPCX993 (Nirwen),IT81302 (Nereid),Type,Enum,SW Notes,HW Notes
+ESPI_SOC_CLK,ESPI,ESPI clock,IN,no,--,N,1.80 V,,M1,M1,L1,OTHER,,,
+ESPI_SOC_CS_EC_L,ESPI,ESPI chip select,IN,F,--,N,1.80 V,,L2,L2,J2,OTHER,,,
+ESPI_SOC_D0_EC,ESPI,ESPI DATA0,I/O,,TTL,N,1.80 V,,H1,H1,L2,OTHER,,,
+ESPI_SOC_D1_EC,ESPI,ESPI DATA1,I/O,,TTL,N,1.80 V,,J1,J1,K1,OTHER,,,
+ESPI_SOC_D2_EC,ESPI,ESPI DATA2,I/O,,TTL,N,1.80 V,,K1,K1,K2,OTHER,,,
+ESPI_SOC_D3_EC,ESPI,ESPI DATA3,I/O,,TTL,N,1.80 V,,L1,L1,J1,OTHER,,,
+ESPI_SOC_RST_EC_L,ESPI,ESPI reset,IN,F,,N,1.80 V,,K3,K3,R5,OTHER,,,
+ESPI_EC_ALERT_SOC_L,ESPI,ESPI Alert,OUT,,TTL,N,1.80 V,,L3,L3,H1,OTHER,,,
+GSC_EC_PWR_BTN_ODL,GSC,Power Button input from GSC,IN,both,--,Y,3.30 V,,E7,E7,B13,INPUT_PU,GPIO_POWER_BUTTON_L,GPIO00,
+EC_RST_ODL,GSC,Reset signal for EC from GSC,IN,no,--,N,3.30 V,GSC,K6,K6,M2,OTHER,,,
+EC_GSC_PACKET_MODE,GSC,Wakes/interrupts GSC and (maybe) vice-versa,I/O,both,--,N,3.30 V,,J6,J6,F9,OUTPUT,GPIO_PACKET_MODE_EN,,
+EC_I2C_EEPROM_SCL,I2C,"I2C clock for CBI, reading INAs, programming EC (ITE only)",I/O,,OD,N,3.30 V,"EEPROMs, INAs",C12,C12,A5,I2C_CLOCK,I2C_PORT_EEPROM,,
+EC_I2C_EEPROM_SDA,I2C,"I2C data for CBI, reading INAs, programming EC (ITE only)",I/O,,OD,N,3.30 V,"EEPROMs, INAs",B12,B12,B3,I2C_DATA,,,
+EC_I2C_BATT_SDA,I2C,I2C data for battery pack,I/O,,OD,N,3.30 V,Battery Pack,K10,K10,A3,I2C_DATA,,,
+EC_I2C_BATT_SCL,I2C,I2C clock for battery pack,I/O,,OD,N,3.30 V,Battery Pack,J10,J10,A4,I2C_CLOCK,I2C_PORT_BATTERY,,
+EC_I2C_SENSOR_SCL,I2C,I2C clock for sensors,I/O,,OD,N,3.30 V,"IMU, accel, lid accel, kb bl",K8,K8,C2,I2C_CLOCK,I2C_PORT_SENSOR,,
+EC_I2C_SENSOR_SDA,I2C,I2C data for sensors,I/O,,OD,N,3.30 V,"IMU, accel, lid accel, kb bl",K7,K7,D2,I2C_DATA,,,
+EC_I2C_USB_C0_SDA,I2C,I2C clock for USB-C C0 and USB-A A0 port ICs,I/O,,OD,N,3.30 V,"TCPC, BC1.2, Charger",F9,F9,K7,I2C_DATA,,,
+EC_I2C_USB_C0_SCL,I2C,I2C data for USB-C C0 and USB-A A0 port ICs,I/O,,OD,N,3.30 V,"TCPC, BC1.2, Charger",F8,F8,L7,I2C_CLOCK,I2C_PORT_USB_C0_TCPC,,
+EC_I2C_SUB_USB_C1_SDA,I2C,I2C clock for USB-C C1 and USB-A A1 port ICs (HDMI: HDMI_EN_SUB_ODL - enable HDMI retimer/output/active low),I/O,,OD,N,3.30 V,"TCPC, BC1.2, Charger",E9,E9,R4,I2C_DATA,,,
+EC_I2C_SUB_USB_C1_SCL,I2C,"I2C data for USB-C C1 and USB-A A1 port ICs (HDMI_HPD_SUB_ODL, hot-plug detection/input (interrupt)/active low)",I/O,,OD,N,3.30 V,"TCPC, BC1.2, Charger",E8,E8,P3,I2C_CLOCK,I2C_PORT_USB_C1_TCPC,,
+EC_KSI_00,Keyboard,Keyboard Input,IN,no,--,Y,3.30 V,,A2,A2,K15,OTHER,,,
+KSI_01,Keyboard,Keyboard Input,IN,no,--,Y,3.30 V,,A3,A3,K14,OTHER,,,
+EC_KSI_02,Keyboard,Keyboard Input,IN,no,--,Y,3.30 V,,A4,A4,K10,OTHER,,,
+EC_KSI_03,Keyboard,Keyboard Input,IN,no,--,Y,3.30 V,,B3,B3,J15,OTHER,,,Vivaldi Support
+KSI_04,Keyboard,Keyboard Input,IN,no,--,Y,3.30 V,,B4,B4,J10,OTHER,,,
+KSI_05,Keyboard,Keyboard Input,IN,no,--,Y,3.30 V,,C3,C3,J11,OTHER,,,
+KSI_06,Keyboard,Keyboard Input,IN,no,--,Y,3.30 V,,C4,C4,J14,OTHER,,,
+KSI_07,Keyboard,Keyboard Input,IN,no,--,Y,3.30 V,,C5,C5,H10,OTHER,,,
+KSO_00,Keyboard,Keyboard Output,OUT,,OD,N,3.30 V,,B5,B5,R9,OTHER,,,
+KSO_01,Keyboard,Keyboard Output,OUT,,OD,N,3.30 V,,B6,B6,K8,OTHER,,,
+EC_KSO_02_INV,Keyboard,Keyboard Output,OUT,,TTL,N,3.30 V,,B7,B7,P10,OUTPUT_L,,KEYBOARD_COL2_INVERTED,
+KSO_03,Keyboard,Keyboard Output,OUT,,OD,N,3.30 V,,B8,B8,R10,OTHER,,,
+KSO_04,Keyboard,Keyboard Output,OUT,,OD,N,3.30 V,,C7,C7,L9,OTHER,,,
+KSO_05,Keyboard,Keyboard Output,OUT,,OD,N,3.30 V,,C6,C6,K9,OTHER,,,
+KSO_06,Keyboard,Keyboard Output,OUT,,OD,N,3.30 V,,C8,C8,P11,OTHER,,,
+KSO_07,Keyboard,Keyboard Output,OUT,,OD,N,3.30 V,,B9,B9,R11,OTHER,,,
+KSO_08,Keyboard,Keyboard Output,OUT,,OD,N,3.30 V,,C9,C9,P12,OTHER,,,
+KSO_09,Keyboard,Keyboard Output,OUT,,OD,N,3.30 V,,C10,C10,L10,OTHER,,,
+KSO_10,Keyboard,Keyboard Output,OUT,,OD,N,3.30 V,,B11,B11,P13,OTHER,,,
+KSO_11,Keyboard,Keyboard Output,OUT,,OD,N,3.30 V,,B10,B10,P14,OTHER,,,
+KSO_12,Keyboard,Keyboard Output,OUT,,OD,N,3.30 V,,C11,C11,N14,OTHER,,,
+KSO_13,Keyboard,Keyboard Output,OUT,,OD,N,3.30 V,,D11,D11,M15,OTHER,,,Required only for NUM PAD
+KSO_14,Keyboard,Keyboard Output,OUT,,OD,N,3.30 V,,D6,D6,M14,OTHER,,,Required only for NUM PAD
+EN_KB_BL,MISC,Enable Keyboard backlight,OUT,,TTL,N,3.30 V,,G11,G11,D14,OUTPUT,GPIO_EN_KEYBOARD_BACKLIGHT,,
+VOLDN_BTN_ODL,MISC,Volume down signal,IN,both,--,Y,3.30 V,Button,F12,E11,G15,INPUT_PU,GPIO_VOLUME_DOWN_L,,
+VOLUP_BTN_ODL,MISC,Volume up signal,IN,both,--,Y,3.30 V,Button,E11,F12,F14,INPUT_PU,GPIO_VOLUME_UP_L,,
+LID_OPEN,MISC,Indicator from lid switch that lid is open,IN,both,--,N,3.30 V,,G7,G7,A11,INPUT,GPIO_LID_OPEN,,
+TABLET_MODE_L,MISC,Indicator from lid switch that lid is flipped all the way around,IN,both,--,N,3.30 V,,M12,M12,L8,INPUT,GPIO_TABLET_MODE_L,,Not required to connect to EC?
+IMU_INT_L,MISC,Interrupt from base intertial measurement unit,IN,falling,,N,1.80 V,IMU,M2,M2,F15,INPUT,,,
+ACC_INT_L,MISC,Interrupt from lid accel (only in convertibles),IN,falling,,N,1.80 V,ACC,G10,G10,E2,INPUT,,,Not required from Dedede?
+EC_WP_ODL,MISC,Write protection status from GSC,IN,no,--,N,3.30 V,GSC,L12,L12,R8,INPUT_L,,,
+EC_EDP_BL_EN_OD,MISC,EC override of backlight enable,OUT,,OD,N,3.30 V,,E10,E10,R15,OUTPUT_ODR,GPIO_ENABLE_BACKLIGHT,,
+TEMP_SENSOR_1,MISC,NTC 1 - near memory,IN,no,ADC,N,ANA,,F2,F2,H15,ADC,ADC_TEMP_SENSOR_1,,
+TEMP_SENSOR_2,MISC,NTC 2 - near chassis hot spot,IN,no,ADC,N,ANA,,E3,E3,G10,ADC,ADC_TEMP_SENSOR_2,,
+TEMP_SENSOR_3,MISC,NTC 3 - Ambient/skin temp,IN,no,ADC,N,ANA,,,F4,A13,ADC,ADC_TEMP_SENSOR_3,,
+USB_C0_INT_ODL,MISC,Interrupt for all ICs for Type-C port 0,IN,,--,Y,3.30 V,,E6,E6,P1,INPUT_PU,,,
+USB_C0_PROT_FAULT_ODL,MISC,Fault out of the USB C0 protection IC,IN,falling,OD,Y,3.30 V,,,#N/A,,,,,
+"SUB_USB_C1_INT_ODL
+(HDMI: EN_SUB_RAILS_ODL)",MISC,"Interrupt for all ICs for Type-C port 1 or the sub-board
+HDMI: Enable 5V power rail/output/active low",IN,,--,Y,3.30 V,,F7,F7,N2,OTHER,,,
+HDMI_SEL,MISC,Configures AUX to be HDMI DDC,OUT,,TTL,N,3.30 V,,D10,D10,F2,OUTPUT,,,
+CCD_MODE_ODL,MISC,Indicates whether H1 is using SBU lines for debug. Also can trigger CCD if the EC decides to.,I/O,falling,--/OD,N,3.30 V,GSC,A12,A12,B9,INPUT,GPIO_CCD_MODE_ODL,,
+EC_BATTERY_PRES_ODL,MISC,or BATT_TEMP - indication of battery presence,IN,,--,N,3.30 V,Battery pack,K12,K12,G14,INPUT,GPIO_BATT_PRES_ODL,,
+EC_ENTERING_RW,MISC,Indicate when EC is transitioning to RW code,OUT,,TTL,N,3.30 V,GSC,D9,D9,N1,OUTPUT,GPIO_ENTERING_RW,,
+EN_USB_A0_VBUS,MISC,,OUT,,TTL,N,3.30 V,,K9,K9,B1,OUTPUT,,,
+USB_A0_ILIMIT_SDP,MISC,,OUT,,TTL,N,3.30 V,,J8,J8,A1,OUTPUT,GPIO_USB1_ILIM_SEL,??,
+EN_SUB_USB_A1_VBUS,MISC,,OUT,,TTL,N,3.30 V,,A9,A9,B12,OTHER,,??,
+SUB_USB_A1_ILIMIT_SDP,MISC,,OUT,,TTL,N,3.30 V,,A10,A10,A12,OUTPUT,GPIO_USB2_ILIM_SEL,??,
+PWM_FAN,MISC,,OUT,,PWM,N,3.30 V,,,J7,,PWM,,,
+EC_FAN_TACH,MISC,,IN,,,,5.00 V,,,G5,,TACH,,,
+EN_PP5000_FAN_X,MISC,,OUT,,TTL,N,3.30 V,,,J2,,OUTPUT,,,
+EC_CBI_WP,MISC,Updated EC WP method,OUT,,TTL,N,3.30 V,,H5,H5,D15,OUTPUT,,cbi_latch_eeprom_wp,
+IMVP91_VRRDY_OD,POWER SEQUENCE,,IN,,,,,,E2,E2,C14,INPUT,,,
+EC_SOC_SYS_PWROK,POWER SEQUENCE,"Generic power good input to PCH (platform specific), system ready to exit reset.",OUT,,TTL,N,3.30 V,SOC,C1,C1,B11,OUTPUT,,PCH_PWROK,
+EN_SLP_Z,POWER SEQUENCE,Enable Sleep State (Active high). For ITE only.,OUT,,TTL,N,3.30 V,,F3,F3,R3,OUTPUT,,,
+EN_PP5000_S5,POWER SEQUENCE,"Enable PP5000_S5. Figure 523, states this has to come after 3.3V , why?",OUT,,TTL,N,3.30 V,,E5,E5,R14,OUTPUT,,,
+EN_PP3300_S5,POWER SEQUENCE,Enable PP3300_S5.,OUT,,TTL,N,3.30 V,,L9,L9,K11,OUTPUT,GPIO_TEMP_SENSOR_POWER,,
+EC_SOC_DSW_PWROK,POWER SEQUENCE,DSW Power is OK to AP (diode logic with PP3300_PG),OUT,,TTL,N,3.30 V,SOC,K4,K4,C1,OUTPUT,,,
+EC_SOC_RSMRST_L,POWER SEQUENCE,"Asserted after S5-rails are stable, buffered to SOC from EC",OUT,,TTL,N,3.30 V,SOC,F11,F11,E9,OUTPUT,,,
+RSMRST_PWRGD_L,POWER SEQUENCE,,IN,both,--,Y,3.30 V,,M11,M11,B14,INPUT_PU,,,
+SLP_SUS_L,POWER SEQUENCE,"If high, EC must keep S5 on, used in both DSx and non-DSx platforms.",IN,both,--,N,3.30 V,,H2,H2,F8,INPUT,,,No virtual wire over eSPI
+SLP_S4_L,POWER SEQUENCE,"PCH S4 Sleep control. When low, shut-off power to all non critical systems in S4 and lower.",IN,both,--,N,3.30 V,,J4,J4,G11,INPUT,,,This signal is also virtual wire on the eSPI interface.
+SLP_S3_L,POWER SEQUENCE,"PCH S3 Sleep control. When low, shut-off power to all non critical systems in S3 and lower.",IN,both,--,N,3.30 V,,K11,K11,B10,INPUT,,,This signal is also virtual wire on the eSPI interface.
+SLP_S0_L,POWER SEQUENCE,"PCH S0 Sleep control, asserted when PCH = idle & CPU = C10",IN,both,--,N,3.30 V,,L10,L10,F1,INPUT,,,No virtual wire over eSPI
+CPU_C10_GATE_L,POWER SEQUENCE,Asserted low when going into CPU_C10,IN,both,--,N,3.30 V,"SOC, VRs, LS",J3,J3,B6,INPUT,,??,
+EC_VSENSE_PP3300_S5,POWER SEQUENCE,Voltage sense (or PGOOD) for PP3300_S5,IN,no,ADC,N,ANA,,B2,B2,H11,ADC,ADC_PP3300_S5,??,"Nuvoton VREF=2.816V, ITE VREF = AVCC or AVCC/1.1 (3V)"
+PG_PP5000_S5_OD,POWER SEQUENCE,PP5000_S5 power good signal.,IN,,--,N,3.30 V,,D3,D3,C15,INPUT,,,
+EC_SOC_VCCST_PWRGD_OD,POWER SEQUENCE,,OUT,,OD,N,1.05 V,,H11,H11,P9,OUTPUT_ODR,,,
+EC_SOC_PCH_PWROK_OD,POWER SEQUENCE,,OUT,,OD,N,3.30 V,,M4,M4,R12,OUTPUT_ODR,,,
+ALL_SYS_PWRGD,POWER SEQUENCE,,IN,both,,N,3.30 V,,J11,J11,B2,INPUT,,,Figure 398 PDG 0.5
+PG_PP1050_MEM_S3_OD,POWER SEQUENCE,,IN,both,--,N,3.30 V,,D2,D2,P5,INPUT,,??,
+EC_VSENSE_PP1050_PROC,POWER SEQUENCE,,IN,no,ADC,N,ANA,SOC,C2,C2,A14,ADC,ADC_PP1050_PROC,PP1050_PROC monitoring from FIVR output,
+SYS_RST_ODL,POWER SEQUENCE,Reset for SOC,OUT,,OD,N,3.30 V,SOC,H7,H7,P4,OUTPUT_ODR,,,
+EC_PCH_WAKE_ODL,POWER SEQUENCE,"Allows EC to wake AP (e.g., keyboard out of S0ix)",OUT,,OD,N,3.30 V,SOC,L11,L11,E1,OUTPUT_ODL,,EC_SOC_WAKE_ODL on schematic; software uses PCH_WAKE name,
+EC_SOC_RTCRST,POWER SEQUENCE,Allows EC to reset logic on the AP's RTC well,OUT,,TTL,N,3.30 V,SOC,J5,J5,R2,OUTPUT,,,
+VCCIN_AUX_VID0,POWER SEQUENCE,Debug purposes,IN,both,,N,1.80 V,,L8,L8,P2,INPUT,,,
+VCCIN_AUX_VID1,POWER SEQUENCE,Debug purposes,IN,both,,N,1.80 V,,L7,L7,R1,INPUT,,,
+PWM_KB_BL,PWM,Keyboard backlight PWM control signal,OUT,,PWM,N,3.30 V,,H8,H8,R6,PWM,,,
+PWM_LED_1_ODL,PWM,LED 1,OUT,,PWM,N,3.30 V,,G8,G8,P6,PWM_INVERT,,,
+PWM_LED_2_ODL,PWM,LED 2,OUT,,PWM,N,3.30 V,,G9,G9,R7,PWM_INVERT,,,
+PWM_LED_3_ODL,PWM,LED 3,OUT,,PWM,N,3.30 V,,H10,H10,P7,PWM_INVERT,,,
+EC_PSYS,PWM,System power monitoring output,OUT,,PWM,N,ANA,"Charger, IMVP9.1",G6,G6,E15,OTHER,,,
+EC_SOC_PWR_BTN_ODL,SOC,Buffered power button signal from EC to SOC,OUT,,OD,N,3.30 V,SOC,H9,H9,J5,OUTPUT_ODR,GPIO_PCH_PWRBTN_L,,
+EC_SOC_HDMI_HPD,SOC,HPD buffer output for HDMI,OUT,,TTL,N,3.30 V,,L6,L6,P15,OUTPUT,,,
+EC_PROCHOT_ODL,SOC,Allows us to send/read PROCHOT,I/O,both,OD,N,1.05 V,SOC,G3,G3,H14,OUTPUT_ODR,,,
+EC_PCHHOT_ODL,SOC,Allows us to send/read PCHHOT,,,,,,,#N/A,#N/A,#N/A,OTHER,,,Intel confirmed that this feature is not used.
+EC_SOC_INT_ODL,SOC,EC interrupt to SOC,OUT,,OD,N,,,K5,K5,P8,OUTPUT_ODR,GPIO_EC_INT_L,,Is this needed?
+UART_GSC_DBG_RX_EC_TX,UART,UART signal from EC to debugger,OUT,,TTL,N,3.30 V,,H4,H4,B4,OTHER,,,
+UART_GSC_DBG_TX_EC_RX,UART,UART signal from debugger to EC,IN,,--,N,3.30 V,,G4,G4,B5,OTHER,,,
+EN_PP5000_PEN_X,MISC,Enable signal for 5V PEN charging rail,OUT,,TTL,N,3.30 V,,A11,A11,G2,OUTPUT,,,
+PEN_DETECT_ODL,MISC,"PEN detect signal. Internal debouncing, if required.",IN,both,--,Y,3.30 V,,G12,G12,E14,INPUT_PU,,,
+USB_C0_CC1,USB-PD,CC1 for IT81302 only,I/O,,CC,PD,ANA,,#N/A,#N/A,E10,OTHER,,,
+USB_C0_CC2,USB-PD,CC2 for IT81302 only,I/O,,CC,PD,ANA,,#N/A,#N/A,A10,OTHER,,,
+USB_C0_FRS,USB-PD,FRS for IT81302 only,OUT,,TTL,N,3.30 V,,#N/A,#N/A,D1,OUTPUT,,,
+EN_USB_C0_CC1_VCONN,USB-PD,CC1 vconn en for IT81302 only,OUT,,TTL,N,3.30 V,,#N/A,#N/A,A9,OUTPUT,,,
+EN_USB_C0_CC2_VCONN,USB-PD,CC2 vconn en for IT81302 only,OUT,,TTL,N,3.30 V,,#N/A,#N/A,A8,OUTPUT,,,
+EC_TRIS_L,DEBUG,Debug for NPCX993,,,,,,,E4,E4,#N/A,OTHER,,,
+EC_TEST_L,DEBUG,Debug for NPCX994,,,,,,,K2,K2,#N/A,OTHER,,,
+EC_32KXOUT,DEBUG,Debug for NPCX995,,,,,,,M5,M5,#N/A,OTHER,,,
+EC_SHDF_ESPI_L,DEBUG,Debug for NPCX996,,,,,,,H3,H3,#N/A,OTHER,,,
\ No newline at end of file
diff --git a/zephyr/program/nissa/nivviks/cbi.dtsi b/zephyr/program/nissa/nivviks/cbi.dtsi
new file mode 100644
index 0000000000..112a2a885c
--- /dev/null
+++ b/zephyr/program/nissa/nivviks/cbi.dtsi
@@ -0,0 +1,30 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+  /* Nivviks-specific fw_config fields. */
+	nissa-fw-config {
+		/*
+		 * FW_CONFIG field to describe mainboard orientation in chassis.
+		 */
+		base-inversion {
+			enum-name = "FW_BASE_INVERSION";
+			start = <3>;
+			size = <1>;
+
+			inverted {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_BASE_INVERTED";
+				value = <0>;
+			};
+			regular {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_BASE_REGULAR";
+				value = <1>;
+				default;
+			};
+		};
+	};
+};
diff --git a/zephyr/program/nissa/nivviks/generated.dtsi b/zephyr/program/nissa/nivviks/generated.dtsi
new file mode 100644
index 0000000000..91718302b4
--- /dev/null
+++ b/zephyr/program/nissa/nivviks/generated.dtsi
@@ -0,0 +1,291 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * This file is auto-generated - do not edit!
+ */
+
+/ {
+
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc {
+			enum-name = "ADC_PP1050_PROC";
+			io-channels = <&adc0 4>;
+		};
+		adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 {
+			enum-name = "ADC_PP3300_S5";
+			io-channels = <&adc0 6>;
+		};
+		adc_temp_sensor_1: temp_sensor_1 {
+			enum-name = "ADC_TEMP_SENSOR_1";
+			io-channels = <&adc0 0>;
+		};
+		adc_temp_sensor_2: temp_sensor_2 {
+			enum-name = "ADC_TEMP_SENSOR_2";
+			io-channels = <&adc0 1>;
+		};
+		adc_temp_sensor_3: temp_sensor_3 {
+			enum-name = "ADC_TEMP_SENSOR_3";
+			io-channels = <&adc0 10>;
+		};
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		gpio_acc_int_l: acc_int_l {
+			gpios = <&gpio5 0 GPIO_INPUT>;
+		};
+		gpio_all_sys_pwrgd: all_sys_pwrgd {
+			gpios = <&gpioa 7 GPIO_INPUT>;
+		};
+		gpio_ccd_mode_odl: ccd_mode_odl {
+			gpios = <&gpioe 5 GPIO_INPUT>;
+			enum-name = "GPIO_CCD_MODE_ODL";
+		};
+		gpio_cpu_c10_gate_l: cpu_c10_gate_l {
+			gpios = <&gpio6 7 GPIO_INPUT>;
+		};
+		gpio_ec_battery_pres_odl: ec_battery_pres_odl {
+			gpios = <&gpioa 3 GPIO_INPUT>;
+			enum-name = "GPIO_BATT_PRES_ODL";
+		};
+		gpio_ec_cbi_wp: ec_cbi_wp {
+			gpios = <&gpio7 4 GPIO_OUTPUT>;
+		};
+		gpio_ec_edp_bl_en_od: ec_edp_bl_en_od {
+			gpios = <&gpiod 3 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_ENABLE_BACKLIGHT";
+		};
+		gpio_ec_entering_rw: ec_entering_rw {
+			gpios = <&gpio0 3 GPIO_OUTPUT>;
+			enum-name = "GPIO_ENTERING_RW";
+		};
+		gpio_ec_gsc_packet_mode: ec_gsc_packet_mode {
+			gpios = <&gpio7 5 GPIO_OUTPUT>;
+			enum-name = "GPIO_PACKET_MODE_EN";
+		};
+		gpio_ec_kso_02_inv: ec_kso_02_inv {
+			gpios = <&gpio1 7 (GPIO_OUTPUT_LOW | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_ec_pch_wake_odl: ec_pch_wake_odl {
+			gpios = <&gpiob 0 GPIO_ODR_LOW>;
+		};
+		gpio_ec_prochot_odl: ec_prochot_odl {
+			gpios = <&gpiof 1 GPIO_ODR_HIGH>;
+		};
+		gpio_ec_soc_dsw_pwrok: ec_soc_dsw_pwrok {
+			gpios = <&gpio6 1 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_hdmi_hpd: ec_soc_hdmi_hpd {
+			gpios = <&gpioe 4 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_int_odl: ec_soc_int_odl {
+			gpios = <&gpio8 0 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_EC_INT_L";
+		};
+		gpio_ec_soc_pch_pwrok_od: ec_soc_pch_pwrok_od {
+			gpios = <&gpio7 2 GPIO_ODR_HIGH>;
+		};
+		gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl {
+			gpios = <&gpioc 1 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_PCH_PWRBTN_L";
+		};
+		gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l {
+			gpios = <&gpioa 6 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_rtcrst: ec_soc_rtcrst {
+			gpios = <&gpio7 6 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_sys_pwrok: ec_soc_sys_pwrok {
+			gpios = <&gpio3 7 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_vccst_pwrgd_od: ec_soc_vccst_pwrgd_od {
+			gpios = <&gpioa 4 GPIO_ODR_HIGH>;
+		};
+		gpio_ec_wp_odl: ec_wp_odl {
+			gpios = <&gpioa 1 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_en_kb_bl: en_kb_bl {
+			gpios = <&gpioa 0 GPIO_OUTPUT>;
+			enum-name = "GPIO_EN_KEYBOARD_BACKLIGHT";
+		};
+		gpio_en_pp3300_s5: en_pp3300_s5 {
+			gpios = <&gpiob 6 GPIO_OUTPUT>;
+			enum-name = "GPIO_TEMP_SENSOR_POWER";
+		};
+		gpio_en_pp5000_pen_x: en_pp5000_pen_x {
+			gpios = <&gpioe 2 GPIO_OUTPUT>;
+		};
+		gpio_en_pp5000_s5: en_pp5000_s5 {
+			gpios = <&gpio4 0 GPIO_OUTPUT>;
+		};
+		gpio_en_slp_z: en_slp_z {
+			gpios = <&gpioe 1 GPIO_OUTPUT>;
+		};
+		gpio_en_usb_a0_vbus: en_usb_a0_vbus {
+			gpios = <&gpio9 1 GPIO_OUTPUT>;
+		};
+		gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl {
+			gpios = <&gpio0 0 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		gpio_hdmi_sel: hdmi_sel {
+			gpios = <&gpioc 6 GPIO_OUTPUT>;
+		};
+		gpio_imu_int_l: imu_int_l {
+			gpios = <&gpio5 6 GPIO_INPUT>;
+		};
+		gpio_imvp91_vrrdy_od: imvp91_vrrdy_od {
+			gpios = <&gpio4 3 GPIO_INPUT>;
+		};
+		gpio_lid_open: lid_open {
+			gpios = <&gpiod 2 GPIO_INPUT>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+		gpio_pen_detect_odl: pen_detect_odl {
+			gpios = <&gpio9 6 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_pg_pp1050_mem_s3_od: pg_pp1050_mem_s3_od {
+			gpios = <&gpiof 0 GPIO_INPUT>;
+		};
+		gpio_pg_pp5000_s5_od: pg_pp5000_s5_od {
+			gpios = <&gpio4 2 GPIO_INPUT>;
+		};
+		gpio_rsmrst_pwrgd_l: rsmrst_pwrgd_l {
+			gpios = <&gpio9 4 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_slp_s0_l: slp_s0_l {
+			gpios = <&gpio9 7 GPIO_INPUT>;
+		};
+		gpio_slp_s3_l: slp_s3_l {
+			gpios = <&gpioa 5 GPIO_INPUT>;
+		};
+		gpio_slp_s4_l: slp_s4_l {
+			gpios = <&gpio7 0 GPIO_INPUT>;
+		};
+		gpio_slp_sus_l: slp_sus_l {
+			gpios = <&gpio6 2 GPIO_INPUT>;
+		};
+		gpio_sub_usb_a1_ilimit_sdp: sub_usb_a1_ilimit_sdp {
+			gpios = <&gpiod 5 GPIO_OUTPUT>;
+			enum-name = "GPIO_USB2_ILIM_SEL";
+		};
+		gpio_sys_rst_odl: sys_rst_odl {
+			gpios = <&gpioc 5 GPIO_ODR_HIGH>;
+		};
+		gpio_tablet_mode_l: tablet_mode_l {
+			gpios = <&gpio9 5 GPIO_INPUT>;
+			enum-name = "GPIO_TABLET_MODE_L";
+		};
+		gpio_usb_a0_ilimit_sdp: usb_a0_ilimit_sdp {
+			gpios = <&gpio8 5 GPIO_OUTPUT>;
+			enum-name = "GPIO_USB1_ILIM_SEL";
+		};
+		gpio_usb_c0_int_odl: usb_c0_int_odl {
+			gpios = <&gpio0 1 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_vccin_aux_vid0: vccin_aux_vid0 {
+			gpios = <&gpio9 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		gpio_vccin_aux_vid1: vccin_aux_vid1 {
+			gpios = <&gpioe 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		gpio_voldn_btn_odl: voldn_btn_odl {
+			gpios = <&gpioa 2 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_DOWN_L";
+		};
+		gpio_volup_btn_odl: volup_btn_odl {
+			gpios = <&gpio9 3 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_UP_L";
+		};
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		i2c_ec_i2c_eeprom: ec_i2c_eeprom {
+			i2c-port = <&i2c0_0>;
+			enum-names = "I2C_PORT_EEPROM";
+		};
+		i2c_ec_i2c_sensor: ec_i2c_sensor {
+			i2c-port = <&i2c1_0>;
+			enum-names = "I2C_PORT_SENSOR";
+		};
+		i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 {
+			i2c-port = <&i2c3_0>;
+			enum-names = "I2C_PORT_USB_C0_TCPC";
+		};
+		i2c_ec_i2c_sub_usb_c1: ec_i2c_sub_usb_c1 {
+			i2c-port = <&i2c5_1>;
+			enum-names = "I2C_PORT_USB_C1_TCPC";
+		};
+		i2c_ec_i2c_batt: ec_i2c_batt {
+			i2c-port = <&i2c7_0>;
+			enum-names = "I2C_PORT_BATTERY";
+		};
+	};
+};
+
+&adc0 {
+	status = "okay";
+	pinctrl-0 = <&adc0_chan0_gp45
+		     &adc0_chan1_gp44
+		     &adc0_chan4_gp41
+		     &adc0_chan6_gp34
+		     &adc0_chan10_gpe0>;
+	pinctrl-names = "default";
+};
+
+
+&i2c0_0 {
+	status = "okay";
+	pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>;
+	pinctrl-names = "default";
+};
+
+&i2c1_0 {
+	status = "okay";
+	pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>;
+	pinctrl-names = "default";
+};
+
+&i2c3_0 {
+	status = "okay";
+	pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>;
+	pinctrl-names = "default";
+};
+
+&i2c5_1 {
+	status = "okay";
+	pinctrl-0 = <&i2c5_1_sda_scl_gpf4_f5>;
+	pinctrl-names = "default";
+};
+
+&i2c7_0 {
+	status = "okay";
+	pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>;
+	pinctrl-names = "default";
+};
+
+&i2c_ctrl0 {
+	status = "okay";
+};
+
+&i2c_ctrl1 {
+	status = "okay";
+};
+
+&i2c_ctrl3 {
+	status = "okay";
+};
+
+&i2c_ctrl5 {
+	status = "okay";
+};
+
+&i2c_ctrl7 {
+	status = "okay";
+};
diff --git a/zephyr/program/nissa/nivviks/keyboard.dtsi b/zephyr/program/nissa/nivviks/keyboard.dtsi
new file mode 100644
index 0000000000..117f5630fe
--- /dev/null
+++ b/zephyr/program/nissa/nivviks/keyboard.dtsi
@@ -0,0 +1,47 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	kblight {
+		compatible = "cros-ec,kblight-pwm";
+		pwms = <&pwm6 6 PWM_KHZ(10) PWM_POLARITY_NORMAL>;
+	};
+};
+
+&pwm6 {
+	status = "okay";
+	pinctrl-0 = <&pwm6_gpc0>;
+	pinctrl-names = "default";
+};
+
+&cros_kb_raw {
+	status = "okay";
+	/* No KSO2 (it's inverted and implemented by GPIO) */
+	pinctrl-0 = <
+		&ksi0_gp31
+		&ksi1_gp30
+		&ksi2_gp27
+		&ksi3_gp26
+		&ksi4_gp25
+		&ksi5_gp24
+		&ksi6_gp23
+		&ksi7_gp22
+		&kso00_gp21
+		&kso01_gp20
+		&kso03_gp16
+		&kso04_gp15
+		&kso05_gp14
+		&kso06_gp13
+		&kso07_gp12
+		&kso08_gp11
+		&kso09_gp10
+		&kso10_gp07
+		&kso11_gp06
+		&kso12_gp05
+		&kso13_gp04
+		&kso14_gp82
+	>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/nissa/nivviks/motionsense.dtsi b/zephyr/program/nissa/nivviks/motionsense.dtsi
new file mode 100644
index 0000000000..6297a07bf5
--- /dev/null
+++ b/zephyr/program/nissa/nivviks/motionsense.dtsi
@@ -0,0 +1,166 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/motionsense/utils.h>
+
+
+/ {
+	aliases {
+		/*
+		 * Interrupt bindings for sensor devices.
+		 */
+		lsm6dso-int = &base_accel;
+		lis2dw12-int = &lid_accel;
+	};
+
+	/*
+	 * Declare mutexes used by sensor drivers.
+	 * A mutex node is used to create an instance of mutex_t.
+	 * A mutex node is referenced by a sensor node if the
+	 * corresponding sensor driver needs to use the
+	 * instance of the mutex.
+	 */
+	motionsense-mutex {
+		compatible = "cros-ec,motionsense-mutex";
+		lid_mutex: lid-mutex {
+		};
+
+		base_mutex: base-mutex {
+		};
+	};
+
+	/* Rotation matrix used by drivers. */
+	motionsense-rotation-ref {
+		compatible = "cros-ec,motionsense-rotation-ref";
+		lid_rot_ref: lid-rotation-ref {
+			mat33 = <(-1) 0 0
+				 0 1 0
+				 0 0 (-1)>;
+		};
+
+		base_rot_ref: base-rot-ref {
+			mat33 = <(-1) 0 0
+				 0 (-1) 0
+				 0 0 1>;
+		};
+
+		base_rot_inverted: base-rotation-inverted {
+			mat33 = <1 0 0
+				 0 (-1) 0
+				 0 0 (-1)>;
+		};
+	};
+
+	/*
+	 * Driver specific data. A driver-specific data can be shared with
+	 * different motion sensors while they are using the same driver.
+	 *
+	 * If a node's compatible starts with "cros-ec,accelgyro-", it is for
+	 * a common structure defined in accelgyro.h.
+	 * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for
+	 * "struct als_drv_data_t" in accelgyro.h
+	 */
+	motionsense-sensor-data {
+		lsm6dso_accel_data: lsm6dso-accel-drv-data {
+			compatible = "cros-ec,drvdata-lsm6dso";
+			status = "okay";
+		};
+
+		lsm6dso_gyro_data: lsm6dso-gyro-drv-data {
+			compatible = "cros-ec,drvdata-lsm6dso";
+			status = "okay";
+		};
+
+		lis2dw12_data: lis2dw12-drv-data {
+			compatible = "cros-ec,drvdata-lis2dw12";
+			status = "okay";
+		};
+	};
+
+	/*
+	 * List of motion sensors that creates motion_sensors array.
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
+	 * motion sensor IDs for lid angle calculation.
+	 * TODO(b/238139272): The first entries of the array must be
+	 * accelerometers,then gyroscope. Fix this dependency in the DTS
+	 * processing which makes the devicetree entries independent.
+	 */
+	motionsense-sensor {
+		lid_accel: lid-accel {
+			compatible = "cros-ec,lis2dw12";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&lid_mutex>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&lid_rot_ref>;
+			default-range = <2>;
+			drv-data = <&lis2dw12_data>;
+			i2c-spi-addr-flags = "LIS2DWL_ADDR0_FLAGS";
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_accel: base-accel {
+			compatible = "cros-ec,lsm6dso-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex>;
+			port = <&i2c_ec_i2c_sensor>;
+			/*
+			 * May be replaced by alternate depending
+			 * on board config.
+			 */
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&lsm6dso_accel_data>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_gyro: base-gyro {
+			compatible = "cros-ec,lsm6dso-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			default-range = <(1000 | ROUND_UP_FLAG)>; /* dps */
+			drv-data = <&lsm6dso_gyro_data>;
+		};
+	};
+
+	motionsense-sensor-info {
+		compatible = "cros-ec,motionsense-sensor-info";
+
+		/*
+		 * list of GPIO interrupts that have to
+		 * be enabled at initial stage
+		 */
+		sensor-irqs = <&int_imu>;
+		/* list of sensors in force mode */
+		accel-force-mode-sensors = <&lid_accel>;
+	};
+};
diff --git a/zephyr/program/nissa/nivviks/overlay.dtsi b/zephyr/program/nissa/nivviks/overlay.dtsi
new file mode 100644
index 0000000000..5d81f428d2
--- /dev/null
+++ b/zephyr/program/nissa/nivviks/overlay.dtsi
@@ -0,0 +1,439 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <cros/thermistor/thermistor.dtsi>
+#include <dt-bindings/usbc_mux.h>
+#include <dt-bindings/usb_pd_tcpm.h>
+
+/ {
+	aliases {
+		gpio-cbi-wp = &gpio_ec_cbi_wp;
+		gpio-wp = &gpio_ec_wp_odl;
+		int-wp = &int_wp_l;
+		gpio-kbd-kso2 = &gpio_ec_kso_02_inv;
+	};
+
+	ec-console {
+		compatible = "ec-console";
+		disabled = "events", "lpc", "hostcmd";
+	};
+
+	batteries {
+		default_battery: lgc {
+			compatible = "lgc,ap18c8k", "battery-smart";
+		};
+		lgc_ap19b8m {
+			compatible = "lgc,ap19b8m", "battery-smart";
+		};
+	};
+
+	hibernate-wake-pins {
+		compatible = "cros-ec,hibernate-wake-pins";
+		wakeup-irqs = <
+			&int_power_button
+			&int_lid_open
+		>;
+	};
+
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_power_button: power_button {
+			irq-pin = <&gpio_gsc_ec_pwr_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_button_interrupt";
+		};
+		int_wp_l: wp_l {
+			irq-pin = <&gpio_ec_wp_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "switch_interrupt";
+		};
+		int_lid_open: lid_open {
+			irq-pin = <&gpio_lid_open>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "lid_interrupt";
+		};
+		int_tablet_mode: tablet_mode {
+			irq-pin = <&gpio_tablet_mode_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "gmr_tablet_switch_isr";
+		};
+		int_imu: ec_imu {
+			irq-pin = <&gpio_imu_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "lsm6dso_interrupt";
+		};
+		int_vol_down: vol_down {
+			irq-pin = <&gpio_voldn_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+		int_vol_up: vol_up {
+			irq-pin = <&gpio_volup_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+		int_usb_c0: usb_c0 {
+			irq-pin = <&gpio_usb_c0_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "usb_interrupt";
+		};
+		int_usb_c1: usb_c1 {
+			irq-pin = <&gpio_sb_1>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "usb_interrupt";
+		};
+	};
+
+	named-gpios {
+		gpio_sb_1: sb-1 {
+			gpios = <&gpio0 2 GPIO_PULL_UP>;
+			no-auto-init;
+		};
+
+		gpio_sb_2: sb-2 {
+			gpios = <&gpiod 4 GPIO_OUTPUT>;
+			no-auto-init;
+		};
+
+		/*
+		 * Set I2C pins for type C sub-board to be low voltage (I2C5_1).
+		 * We do this for all boards, since the pins are 3.3V tolerant,
+		 * and the only 2 types of sub-boards used on nivviks both have
+		 * type-C ports on them.
+		 */
+		gpio_sb_3: sb-3 {
+			gpios = <&gpiof 4 (GPIO_OPEN_DRAIN | GPIO_VOLTAGE_1P8)>;
+			no-auto-init;
+		};
+		gpio_sb_4: sb-4 {
+			gpios = <&gpiof 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+			no-auto-init;
+		};
+		gpio_fan_enable: fan-enable {
+			gpios = <&gpio6 3 GPIO_OUTPUT>;
+			no-auto-init;
+		};
+		ec-i2c-sensor-scl {
+			gpios = <&gpio9 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		ec-i2c-sensor-sda {
+			gpios = <&gpio8 7 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+	};
+
+	/*
+	 * Aliases used for sub-board GPIOs.
+	 */
+	aliases {
+		/*
+		 * Input GPIO when used with type-C port 1
+		 * Output when used with HDMI sub-board
+		 */
+		gpio-usb-c1-int-odl = &gpio_sb_1;
+		gpio-en-rails-odl = &gpio_sb_1;
+		/*
+		 * Sub-board with type A USB, enable.
+		 */
+		gpio-en-usb-a1-vbus = &gpio_sb_2;
+		/*
+		 * HPD pins for HDMI sub-board.
+		 */
+		gpio-hdmi-en-odl = &gpio_sb_3;
+		gpio-hpd-odl = &gpio_sb_4;
+		/*
+		 * Enable S5 rails for LTE sub-board
+		 */
+		gpio-en-sub-s5-rails = &gpio_sb_2;
+	};
+
+	temp_memory: memory {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_1>;
+	};
+	temp_charger: charger {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_2>;
+	};
+	temp_ambient: ambient {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_3>;
+	};
+
+	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
+		memory {
+			temp_fan_off = <35>;
+			temp_fan_max = <60>;
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_memory>;
+		};
+		charger {
+			temp_fan_off = <35>;
+			temp_fan_max = <60>;
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_charger>;
+		};
+		ambient {
+			temp_fan_off = <35>;
+			temp_fan_max = <60>;
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_ambient>;
+		};
+	};
+
+	usba {
+		compatible = "cros-ec,usba-port-enable-pins";
+		/*
+		 * sb_2 is only configured as GPIO when USB-A1 is present,
+		 * but it's still safe to control when disabled.
+		 *
+		 * ILIM_SEL pins are referred to by legacy enum name,
+		 * GPIO_USB*_ILIM_SEL. The one for port A1 is unused on
+		 * sub-boards that don't have USB-A so is safe to control
+		 * regardless of system configuration.
+		 */
+		enable-pins = <&gpio_en_usb_a0_vbus &gpio_sb_2>;
+		status = "okay";
+	};
+
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+			bc12 = <&bc12_port0>;
+			chg = <&chg_port0>;
+			tcpc = <&tcpc_port0>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_0>;
+			};
+		};
+		port0-muxes {
+			virtual_mux_0: virtual-mux-0 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+		/*
+		 * TODO(b:211693800): port1 may not be present on some
+		 * sub-boards.
+		 */
+		port1@1 {
+			compatible = "named-usbc-port";
+			reg = <1>;
+			bc12 = <&bc12_port1>;
+			chg = <&chg_port1>;
+			tcpc = <&tcpc_port1>;
+			usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_1 &anx7483_mux_1>;
+			};
+			usb_mux_chain_1_no_mux: usb-mux-chain-1-no-mux {
+				compatible = "cros-ec,usb-mux-chain";
+				alternative-chain;
+				usb-muxes = <&virtual_mux_1>;
+			};
+		};
+		port1-muxes {
+			virtual_mux_1: virtual-mux-1 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+	};
+
+	fans {
+		compatible = "cros-ec,fans";
+
+		fan_0 {
+			pwms = <&pwm5 5 PWM_KHZ(1) PWM_POLARITY_NORMAL>;
+			rpm_min = <2200>;
+			rpm_start = <2200>;
+			rpm_max = <4200>;
+			tach = <&tach2>;
+			enable_gpio = <&gpio_fan_enable>;
+		};
+	};
+
+	 /*
+	  * Declare unused GPIOs so that they are shut down
+	  * and use minimal power
+	  */
+	  unused-pins {
+		compatible = "unused-gpios";
+		unused-gpios =
+			<&gpio3 2 0>,
+			<&gpio3 3 0>,
+			<&gpio3 5 0>,
+			<&gpio3 6 0>,
+			<&gpio5 7 0>,
+			<&gpio6 0 0>,
+			<&gpio6 3 0>,
+			<&gpio6 6 0>,
+			<&gpio7 3 0>,
+			<&gpio8 3 0>,
+			<&gpio8 6 0>,
+			<&gpiob 1 0>,
+			<&gpiob 7 0>,
+			<&gpioc 7 0>,
+			<&gpiof 2 0>,
+			<&gpiof 3 0>;
+	 };
+};
+
+&thermistor_3V3_51K1_47K_4050B {
+	status = "okay";
+};
+
+&adc_ec_vsense_pp3300_s5 {
+	/*
+	 * Voltage divider on input has 47k upper and 220k lower legs with
+	 * 2714 mV full-scale reading on the ADC. Apply the largest possible
+	 * multiplier (without overflowing int32) to get the best possible
+	 * approximation of the actual ratio, but derate by a factor of two to
+	 * ensure unexpectedly high values won't overflow.
+	 */
+	mul = <(791261 / 2)>;
+	div = <(651975 / 2)>;
+};
+
+/* Set bus speeds for I2C */
+&i2c0_0 {
+	label = "I2C_EEPROM";
+	clock-frequency = <I2C_BITRATE_FAST>;
+
+	cbi_eeprom: eeprom@50 {
+		compatible = "atmel,at24";
+		reg = <0x50>;
+		size = <2048>;
+		pagesize = <16>;
+		address-width = <8>;
+		timeout = <5>;
+	};
+};
+
+&i2c1_0 {
+	label = "I2C_SENSOR";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&i2c3_0 {
+	label = "I2C_USB_C0_TCPC";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+
+	bc12_port0: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+		/*
+		 * BC1.2 interrupt is shared with TCPC, so
+		 * IRQ is not specified here and handled by
+		 * usb_c0_interrupt.
+		 */
+	};
+
+	chg_port0: isl923x@9 {
+		compatible = "intersil,isl923x";
+		status = "okay";
+		reg = <0x9>;
+	};
+
+	tcpc_port0: raa489000@22 {
+		compatible = "renesas,raa489000";
+		reg = <0x22>;
+		tcpc-flags = <(
+			TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_VBUS_MONITOR)>;
+	};
+};
+
+&i2c5_1 {
+	label = "I2C_SUB_C1_TCPC";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+
+	bc12_port1: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+	};
+
+	chg_port1: isl923x@9 {
+		compatible = "intersil,isl923x";
+		status = "okay";
+		reg = <0x9>;
+	};
+
+	tcpc_port1: raa489000@22 {
+		compatible = "renesas,raa489000";
+		reg = <0x22>;
+		tcpc-flags = <(
+			TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_VBUS_MONITOR)>;
+	};
+
+	anx7483_mux_1: anx7483-mux-1@3e {
+		compatible = "analogix,anx7483";
+		reg = <0x3e>;
+		board-set = "anx7483_set_default_tuning";
+		flags = <USB_MUX_FLAG_RESETS_IN_G3>;
+	};
+};
+
+&i2c7_0 {
+	label = "I2C_BATTERY";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+};
+
+&pwm5_gpb7 {
+	drive-open-drain;
+};
+
+&pwm5 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm5_gpb7>;
+	pinctrl-names = "default";
+};
+
+/* Tachometer for fan speed measurement */
+&tach2 {
+	status = "okay";
+	pinctrl-0 = <&ta2_1_in_gp73>;
+	pinctrl-names = "default";
+	port = <NPCX_TACH_PORT_A>; /* port-A is selected */
+	sample-clk = <NPCX_TACH_FREQ_LFCLK>; /* Use LFCLK as sampling clock */
+	pulses-per-round = <2>; /* number of pulses per round of encoder */
+};
+
+/* host interface */
+&espi0 {
+	status = "okay";
+	pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>;
+	pinctrl-names = "default";
+};
+
+/*
+ * Declare GPIOs that have leakage current caused by board issues here. NPCX ec
+ * will disable their input buffers before entering deep sleep and restore them
+ * after waking up automatically for better power consumption.
+ */
+&power_leakage_io {
+	leak-gpios = <&gpioa 4 GPIO_OPEN_DRAIN
+		      &gpiof 1 GPIO_OPEN_DRAIN>;
+};
diff --git a/zephyr/program/nissa/nivviks/power_signals.dtsi b/zephyr/program/nissa/nivviks/power_signals.dtsi
new file mode 100644
index 0000000000..1d2b23069d
--- /dev/null
+++ b/zephyr/program/nissa/nivviks/power_signals.dtsi
@@ -0,0 +1,220 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	chosen {
+		intel-ap-pwrseq,espi = &espi0;
+	};
+
+	common-pwrseq {
+		compatible = "intel,ap-pwrseq";
+
+		sys-pwrok-delay = <10>;
+		all-sys-pwrgd-timeout = <20>;
+	};
+
+	pwr-en-pp5000-s5 {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PP5000_S5 enable output to regulator";
+		enum-name = "PWR_EN_PP5000_A";
+		gpios = <&gpio4 0 0>;
+		output;
+	};
+	pwr-en-pp3300-s5 {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PP3300_S5 enable output to LS";
+		enum-name = "PWR_EN_PP3300_A";
+		gpios = <&gpiob 6 0>;
+		output;
+	};
+	pwr-pg-ec-rsmrst-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST power good from regulator";
+		enum-name = "PWR_RSMRST";
+		gpios = <&gpio9 4 0>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-ec-pch-rsmrst-odl {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST output to PCH";
+		enum-name = "PWR_EC_PCH_RSMRST";
+		gpios = <&gpioa 6 0>;
+		output;
+	};
+	pwr-slp-s0-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_S0_L input from PCH";
+		enum-name = "PWR_SLP_S0";
+		gpios = <&gpio9 7 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-slp-s3-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_S3_L input from PCH";
+		enum-name = "PWR_SLP_S3";
+		gpios = <&gpioa 5 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-slp-sus-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_SUS_L input from PCH";
+		enum-name = "PWR_SLP_SUS";
+		gpios = <&gpio6 2 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-ec-soc-dsw-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "DSW_PWROK output to PCH";
+		enum-name = "PWR_EC_SOC_DSW_PWROK";
+		gpios = <&gpio6 1 0>;
+		output;
+	};
+	pwr-vccst-pwrgd-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "VCCST_PWRGD output to PCH";
+		enum-name = "PWR_VCCST_PWRGD";
+		gpios = <&gpioa 4 GPIO_OPEN_DRAIN>;
+		output;
+	};
+	pwr-imvp9-vrrdy-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "VRRDY input from IMVP9";
+		enum-name = "PWR_IMVP9_VRRDY";
+		gpios = <&gpio4 3 0>;
+	};
+	pwr-pch-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PCH_PWROK output to PCH";
+		enum-name = "PWR_PCH_PWROK";
+		gpios = <&gpio7 2 GPIO_OPEN_DRAIN>;
+		output;
+	};
+	pwr-ec-pch-sys-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_PWROK output to PCH";
+		enum-name = "PWR_EC_PCH_SYS_PWROK";
+		gpios = <&gpio3 7 0>;
+		output;
+	};
+	pwr-sys-rst-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_RESET# output to PCH";
+		enum-name = "PWR_SYS_RST";
+		gpios = <&gpioc 5 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>;
+		output;
+	};
+	pwr-slp-s4 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S4 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S4";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4";
+		vw-invert;
+	};
+	pwr-slp-s5 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S5 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S5";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5";
+		vw-invert;
+	};
+	pwr-all-sys-pwrgd {
+		compatible = "intel,ap-pwrseq-external";
+		dbg-label = "Combined all power good";
+		enum-name = "PWR_ALL_SYS_PWRGD";
+	};
+	pwr-adc-pp3300 {
+		compatible = "intel,ap-pwrseq-adc";
+		dbg-label = "PP3300 PWROK (from ADC)";
+		enum-name = "PWR_DSW_PWROK";
+		trigger-high = <&cmp_pp3300_s5_high>;
+		trigger-low = <&cmp_pp3300_s5_low>;
+	};
+	pwr-adc-pp1p05 {
+		compatible = "intel,ap-pwrseq-adc";
+		dbg-label = "PP1P05 PWROK (from ADC)";
+		enum-name = "PWR_PG_PP1P05";
+		trigger-high = <&cmp_pp1p05_high>;
+		trigger-low = <&cmp_pp1p05_low>;
+	};
+
+	adc-cmp {
+		cmp_pp3300_s5_high: pp3300_high {
+			compatible = "nuvoton,adc-cmp";
+			io-channels = <&adc0 6>;
+			comparison = "ADC_CMP_NPCX_GREATER";
+			/*
+			 * This is 90% of nominal voltage considering voltage
+			 * divider on ADC input.
+			 */
+			threshold-mv = <2448>;
+		};
+		cmp_pp3300_s5_low: pp3300_low {
+			compatible = "nuvoton,adc-cmp";
+			io-channels = <&adc0 6>;
+			comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL";
+			threshold-mv = <2448>;
+		};
+		cmp_pp1p05_high: pp1p05_high {
+			compatible = "nuvoton,adc-cmp";
+			io-channels = <&adc0 4>;
+			comparison = "ADC_CMP_NPCX_GREATER";
+			/* Setting at 90% of nominal voltage */
+			threshold-mv = <945>;
+		};
+		cmp_pp1p05_low: pp1p05_low {
+			compatible = "nuvoton,adc-cmp";
+			io-channels = <&adc0 4>;
+			comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL";
+			threshold-mv = <945>;
+		};
+	};
+};
+
+/*
+ * Because the power signals directly reference the GPIOs,
+ * the correspinding named-gpios need to have no-auto-init set.
+ */
+&gpio_ec_soc_dsw_pwrok {
+	no-auto-init;
+};
+&gpio_ec_soc_pch_pwrok_od {
+	no-auto-init;
+};
+&gpio_ec_soc_rsmrst_l {
+	no-auto-init;
+};
+&gpio_ec_soc_sys_pwrok {
+	no-auto-init;
+};
+&gpio_ec_soc_vccst_pwrgd_od {
+	no-auto-init;
+};
+&gpio_en_pp3300_s5 {
+	no-auto-init;
+};
+&gpio_en_pp5000_s5 {
+	no-auto-init;
+};
+&gpio_imvp91_vrrdy_od {
+	no-auto-init;
+};
+&gpio_rsmrst_pwrgd_l {
+	no-auto-init;
+};
+&gpio_slp_s0_l {
+	no-auto-init;
+};
+&gpio_slp_s3_l {
+	no-auto-init;
+};
+&gpio_slp_s4_l {
+	no-auto-init;
+};
+&gpio_slp_sus_l {
+	no-auto-init;
+};
+&gpio_sys_rst_odl {
+	no-auto-init;
+};
diff --git a/zephyr/program/nissa/nivviks/project.conf b/zephyr/program/nissa/nivviks/project.conf
new file mode 100644
index 0000000000..f43dc256fa
--- /dev/null
+++ b/zephyr/program/nissa/nivviks/project.conf
@@ -0,0 +1,15 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_BOARD_NIVVIKS=y
+CONFIG_PLATFORM_EC_OCPC=y
+
+CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSO=y
+
+# Both ports use a SLGC55545 smart switch with CTL1..3 fixed high,
+# for SDP2 or CDP only.
+CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART=y
+CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_CDP_SDP_ONLY=y
+CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_DEFAULT_CDP=y
+CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_INVERTED=y
diff --git a/zephyr/program/nissa/nivviks/project.overlay b/zephyr/program/nissa/nivviks/project.overlay
new file mode 100644
index 0000000000..9ca681d979
--- /dev/null
+++ b/zephyr/program/nissa/nivviks/project.overlay
@@ -0,0 +1,14 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "../cbi.dtsi"
+
+#include "cbi.dtsi"
+#include "generated.dtsi"
+#include "keyboard.dtsi"
+#include "motionsense.dtsi"
+#include "overlay.dtsi"
+#include "power_signals.dtsi"
+#include "pwm_leds.dtsi"
diff --git a/zephyr/program/nissa/nivviks/pwm_leds.dtsi b/zephyr/program/nissa/nivviks/pwm_leds.dtsi
new file mode 100644
index 0000000000..a265a5929e
--- /dev/null
+++ b/zephyr/program/nissa/nivviks/pwm_leds.dtsi
@@ -0,0 +1,62 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	pwmleds {
+		compatible = "pwm-leds";
+		pwm_led0: pwm_led_0 {
+			pwms = <&pwm2 2 PWM_HZ(324) PWM_POLARITY_INVERTED>,
+			       <&pwm0 0 PWM_HZ(324) PWM_POLARITY_INVERTED>,
+			       <&pwm1 1 PWM_HZ(324) PWM_POLARITY_INVERTED>;
+		};
+	};
+
+	cros-pwmleds {
+		compatible = "cros-ec,pwm-leds";
+
+		leds = <&pwm_led0>;
+
+				/*<red green blue>*/
+		color-map-red    = <100   0    0>;
+		color-map-green  = <  0 100    0>;
+		color-map-blue   = <  0   0  100>;
+		color-map-yellow = <  0  50   50>;
+		color-map-white  = <100 100  100>;
+		color-map-amber  = <100   0    0>;
+
+		brightness-range = <0 0 100 0 0 100>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pwm_led_0@0 {
+			reg = <0>;
+			ec-led-name = "EC_LED_ID_BATTERY_LED";
+		};
+	};
+};
+
+/* Enable LEDs to work while CPU suspended */
+
+&pwm0 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm0_gpc3>;
+	pinctrl-names = "default";
+};
+
+&pwm1 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm1_gpc2>;
+	pinctrl-names = "default";
+};
+
+&pwm2 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm2_gpc4>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/nissa/nivviks/src/charger.c b/zephyr/program/nissa/nivviks/src/charger.c
new file mode 100644
index 0000000000..d7ae1f1c56
--- /dev/null
+++ b/zephyr/program/nissa/nivviks/src/charger.c
@@ -0,0 +1,55 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "charger.h"
+#include "charger/isl923x_public.h"
+#include "console.h"
+#include "extpower.h"
+#include "usb_pd.h"
+
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+int extpower_is_present(void)
+{
+	int port;
+	int rv;
+	bool acok;
+
+	for (port = 0; port < board_get_usb_pd_port_count(); port++) {
+		rv = raa489000_is_acok(port, &acok);
+		if ((rv == EC_SUCCESS) && acok)
+			return 1;
+	}
+
+	return 0;
+}
+
+/*
+ * Nivviks does not have a GPIO indicating whether extpower is present,
+ * so detect using the charger(s).
+ */
+__override void board_check_extpower(void)
+{
+	static int last_extpower_present;
+	int extpower_present = extpower_is_present();
+
+	if (last_extpower_present ^ extpower_present)
+		extpower_handle_update(extpower_present);
+
+	last_extpower_present = extpower_present;
+}
+
+__override void board_hibernate(void)
+{
+	/* Shut down the chargers */
+	if (board_get_usb_pd_port_count() == 2)
+		raa489000_hibernate(CHARGER_SECONDARY, true);
+	raa489000_hibernate(CHARGER_PRIMARY, true);
+	LOG_INF("Charger(s) hibernated");
+	cflush();
+}
diff --git a/zephyr/program/nissa/nivviks/src/fan.c b/zephyr/program/nissa/nivviks/src/fan.c
new file mode 100644
index 0000000000..ae05e9263e
--- /dev/null
+++ b/zephyr/program/nissa/nivviks/src/fan.c
@@ -0,0 +1,41 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cros_cbi.h"
+#include "fan.h"
+#include "gpio/gpio.h"
+#include "hooks.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+/*
+ * Nirwen fan support
+ */
+test_export_static void fan_init(void)
+{
+	int ret;
+	uint32_t val;
+	/*
+	 * Retrieve the fan config.
+	 */
+	ret = cros_cbi_get_fw_config(FW_FAN, &val);
+	if (ret != 0) {
+		LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_FAN);
+		return;
+	}
+	if (val != FW_FAN_PRESENT) {
+		/* Disable the fan */
+		fan_set_count(0);
+	} else {
+		/* Configure the fan enable GPIO */
+		gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_fan_enable),
+				      GPIO_OUTPUT);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, fan_init, HOOK_PRIO_POST_FIRST);
diff --git a/zephyr/program/nissa/nivviks/src/form_factor.c b/zephyr/program/nissa/nivviks/src/form_factor.c
new file mode 100644
index 0000000000..cc0f39b892
--- /dev/null
+++ b/zephyr/program/nissa/nivviks/src/form_factor.c
@@ -0,0 +1,45 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "accelgyro.h"
+#include "cros_cbi.h"
+#include "hooks.h"
+#include "motionsense_sensors.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+/*
+ * Mainboard orientation support.
+ */
+
+#define ALT_MAT SENSOR_ROT_STD_REF_NAME(DT_NODELABEL(base_rot_inverted))
+#define BASE_SENSOR SENSOR_ID(DT_NODELABEL(base_accel))
+#define BASE_GYRO SENSOR_ID(DT_NODELABEL(base_gyro))
+
+test_export_static void form_factor_init(void)
+{
+	int ret;
+	uint32_t val;
+	/*
+	 * If the firmware config indicates
+	 * an inverted form factor, use the alternative
+	 * rotation matrix.
+	 */
+	ret = cros_cbi_get_fw_config(FW_BASE_INVERSION, &val);
+	if (ret != 0) {
+		LOG_ERR("Error retrieving CBI FW_CONFIG field %d",
+			FW_BASE_INVERSION);
+		return;
+	}
+	if (val == FW_BASE_INVERTED) {
+		LOG_INF("Switching to inverted base");
+		motion_sensors[BASE_SENSOR].rot_standard_ref = &ALT_MAT;
+		motion_sensors[BASE_GYRO].rot_standard_ref = &ALT_MAT;
+	}
+}
+DECLARE_HOOK(HOOK_INIT, form_factor_init, HOOK_PRIO_POST_I2C);
diff --git a/zephyr/program/nissa/nivviks/src/keyboard.c b/zephyr/program/nissa/nivviks/src/keyboard.c
new file mode 100644
index 0000000000..55668a207a
--- /dev/null
+++ b/zephyr/program/nissa/nivviks/src/keyboard.c
@@ -0,0 +1,29 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+
+test_export_static const struct ec_response_keybd_config nivviks_kb = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &nivviks_kb;
+}
diff --git a/zephyr/program/nissa/nivviks/src/led.c b/zephyr/program/nissa/nivviks/src/led.c
new file mode 100644
index 0000000000..a967fbf8a3
--- /dev/null
+++ b/zephyr/program/nissa/nivviks/src/led.c
@@ -0,0 +1,51 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery LED control for nissa
+ */
+#include "common.h"
+#include "ec_commands.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+#include "led_pwm.h"
+
+__override const int led_charge_lvl_1 = 5;
+__override const int led_charge_lvl_2 = 97;
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_BLUE,
+					   2 * LED_ONE_SEC } },
+	};
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_BLUE:
+		set_pwm_led_color(PWM_LED0, EC_LED_COLOR_BLUE);
+		break;
+	case EC_LED_COLOR_AMBER:
+		set_pwm_led_color(PWM_LED0, EC_LED_COLOR_AMBER);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		set_pwm_led_color(PWM_LED0, -1);
+		break;
+	}
+}
diff --git a/zephyr/program/nissa/nivviks/src/usbc.c b/zephyr/program/nissa/nivviks/src/usbc.c
new file mode 100644
index 0000000000..938114785a
--- /dev/null
+++ b/zephyr/program/nissa/nivviks/src/usbc.c
@@ -0,0 +1,233 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_state.h"
+#include "chipset.h"
+#include "driver/charger/isl923x_public.h"
+#include "driver/retimer/anx7483_public.h"
+#include "driver/tcpm/raa489000.h"
+#include "driver/tcpm/tcpci.h"
+#include "hooks.h"
+#include "system.h"
+#include "usb_mux.h"
+
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+int board_is_sourcing_vbus(int port)
+{
+	int regval;
+
+	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
+	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int i;
+	int old_port;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	old_port = charge_manager_get_active_charge_port();
+
+	LOG_INF("New chg p%d", port);
+
+	/* Disable all ports. */
+	if (port == CHARGE_PORT_NONE) {
+		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+			tcpc_write(i, TCPC_REG_COMMAND,
+				   TCPC_REG_COMMAND_SNK_CTRL_LOW);
+			raa489000_enable_asgate(i, false);
+		}
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if port is sourcing VBUS. */
+	if (board_is_sourcing_vbus(port)) {
+		LOG_WRN("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		if (i == port)
+			continue;
+
+		if (tcpc_write(i, TCPC_REG_COMMAND,
+			       TCPC_REG_COMMAND_SNK_CTRL_LOW))
+			LOG_WRN("p%d: sink path disable failed.", i);
+		raa489000_enable_asgate(i, false);
+	}
+
+	/*
+	 * Stop the charger IC from switching while changing ports.  Otherwise,
+	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
+	 */
+	if (old_port != CHARGE_PORT_NONE)
+		charger_discharge_on_ac(1);
+
+	/* Enable requested charge port. */
+	if (raa489000_enable_asgate(port, true) ||
+	    tcpc_write(port, TCPC_REG_COMMAND,
+		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
+		LOG_WRN("p%d: sink path enable failed.", port);
+		charger_discharge_on_ac(0);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	/* Allow the charger IC to begin/continue switching. */
+	charger_discharge_on_ac(0);
+
+	return EC_SUCCESS;
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+	int regval;
+
+	/*
+	 * The interrupt line is shared between the TCPC and BC1.2 detector IC.
+	 * Therefore, go out and actually read the alert registers to report the
+	 * alert status.
+	 */
+	if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl))) {
+		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
+			/* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */
+			if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0))
+				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
+
+			if (regval)
+				status |= PD_STATUS_TCPC_ALERT_0;
+		}
+	}
+
+	if (board_get_usb_pd_port_count() == 2 &&
+	    !gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) {
+		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
+			/* TCPCI spec Rev 1.0 says to ignore bits 14:12. */
+			if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0))
+				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
+
+			if (regval)
+				status |= PD_STATUS_TCPC_ALERT_1;
+		}
+	}
+
+	return status;
+}
+
+void pd_power_supply_reset(int port)
+{
+	/* Disable VBUS */
+	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	if (port < 0 || port >= CONFIG_USB_PD_PORT_MAX_COUNT)
+		return;
+
+	raa489000_set_output_current(port, rp);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	if (port >= CONFIG_USB_PD_PORT_MAX_COUNT)
+		return EC_ERROR_INVAL;
+
+	/* Disable charging. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
+	if (rv)
+		return rv;
+
+	/* Our policy is not to source VBUS when the AP is off. */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	/* Provide Vbus. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
+	if (rv)
+		return rv;
+
+	rv = raa489000_enable_asgate(port, true);
+	if (rv)
+		return rv;
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * TODO(b:147316511): could send a reset command to the TCPC here
+	 * if needed.
+	 */
+}
+
+/*
+ * Because the TCPCs and BC1.2 chips share interrupt lines, it's possible
+ * for an interrupt to be lost if one asserts the IRQ, the other does the same
+ * then the first releases it: there will only be one falling edge to trigger
+ * the interrupt, and the line will be held low. We handle this by polling the
+ * IRQ GPIO on the USB-PD task after processing TCPC interrupts, synchronously
+ * running the BC1.2 interrupt handler to ensure we continue processing
+ * interrupts as long as either source is asserting the IRQ.
+ */
+void board_process_pd_alert(int port)
+{
+	const struct gpio_dt_spec *gpio;
+
+	if (port == 0) {
+		gpio = GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl);
+	} else {
+		gpio = GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl);
+	}
+
+	if (!gpio_pin_get_dt(gpio)) {
+		usb_charger_task_set_event_sync(port, USB_CHG_EVENT_BC12);
+	}
+
+	/*
+	 * Immediately schedule another TCPC interrupt if it seems we haven't
+	 * cleared all pending interrupts.
+	 */
+	if (!gpio_pin_get_dt(gpio))
+		schedule_deferred_pd_interrupt(port);
+}
+
+/*
+ * LCOV_EXCL_START schedule_deferred_pd_interrupt() can't be verified in tests,
+ * but type-C will be obviously broken if this function doesn't work.
+ */
+void usb_interrupt(enum gpio_signal signal)
+{
+	int port;
+
+	if (signal == GPIO_SIGNAL(DT_NODELABEL(gpio_usb_c0_int_odl))) {
+		port = 0;
+	} else {
+		port = 1;
+	}
+	/* Trigger polling of TCPC and BC1.2 in USB-PD task */
+	schedule_deferred_pd_interrupt(port);
+}
+/* LCOV_EXCL_STOP */
diff --git a/zephyr/program/nissa/npcx_program.conf b/zephyr/program/nissa/npcx_program.conf
new file mode 100644
index 0000000000..7c81342d24
--- /dev/null
+++ b/zephyr/program/nissa/npcx_program.conf
@@ -0,0 +1,44 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# EC chip configuration: NPCX993
+CONFIG_CROS_SYSTEM_NPCX=y
+CONFIG_SOC_SERIES_NPCX9=y
+CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API=y
+CONFIG_SYSCON=y
+CONFIG_SHELL_BACKEND_SERIAL_RX_RING_BUFFER_SIZE=256
+
+# Common sensor drivers
+CONFIG_PLATFORM_EC_ACCEL_LIS2DW12=y
+
+# Keyboard
+CONFIG_PLATFORM_EC_KBLIGHT_ENABLE_PIN=y
+# Ensure recovery key combination (esc+refresh+power) is reliable
+CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI3=y
+CONFIG_PLATFORM_EC_KEYBOARD_REFRESH_ROW3=y
+
+# TCPC+PPC: both C0 and C1 (if present) are RAA489000
+CONFIG_PLATFORM_EC_USB_PD_TCPM_RAA489000=y
+CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_TCPC=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y
+CONFIG_PLATFORM_EC_USB_PD_TCPC_LPM_EXIT_DEBOUNCE_US=100000
+# RAA489000 uses TCPCI but not a separate PPC, so custom function is required
+CONFIG_PLATFORM_EC_USB_PD_5V_EN_CUSTOM=y
+
+# Save some flash space by turning off features we don't care much about
+# (EC Kconfig.console turns the ones we do care about on by default)
+CONFIG_SHELL_MINIMAL=y
+
+# FRS enable
+CONFIG_PLATFORM_EC_USB_PD_FRS=y
+CONFIG_PLATFORM_EC_USB_PD_FRS_TCPC=y
+
+# Charger driver and configuration
+CONFIG_PLATFORM_EC_CHARGER_RAA489000=y
+CONFIG_PLATFORM_EC_OCPC_DEF_RBATT_MOHMS=22
+CONFIG_PLATFORM_EC_RAA489000_AC_PRESENT_CONTROL=y
+
+# VSENSE: PP3300_S5 & PP1050_PROC
+CONFIG_ADC_CMP_NPCX_WORKQUEUE=y
+CONFIG_ADC_CMP_NPCX_WORKQUEUE_PRIORITY=12
diff --git a/zephyr/program/nissa/program.conf b/zephyr/program/nissa/program.conf
new file mode 100644
index 0000000000..190388a0e7
--- /dev/null
+++ b/zephyr/program/nissa/program.conf
@@ -0,0 +1,138 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Core EC configuration: build the EC application, using ECOS shims
+# (which are currently required for a number of features).
+CONFIG_CROS_EC=y
+CONFIG_PLATFORM_EC=y
+CONFIG_LTO=y
+
+# RAM-saving options
+# flash shell command is unused, allocated a 4kB buffer for flash test
+CONFIG_FLASH_SHELL=n
+# EC default 1kB buffer seems unnecessarily large, Zephyr default is 8 bytes
+CONFIG_SHELL_BACKEND_SERIAL_TX_RING_BUFFER_SIZE=128
+# Don't allow console output during ISRs
+CONFIG_PLATFORM_EC_ISR_CONSOLE_OUTPUT=n
+
+# Standard shimmed features
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_SYSINFO=y
+CONFIG_PLATFORM_EC_EEPROM_CBI_WP=y
+CONFIG_PLATFORM_EC_LID_SWITCH=y
+CONFIG_PLATFORM_EC_POWER_BUTTON=y
+CONFIG_PLATFORM_EC_SWITCH=y
+CONFIG_PLATFORM_EC_GMR_TABLET_MODE=y
+CONFIG_PLATFORM_EC_TABLET_MODE=y
+CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=y
+CONFIG_PLATFORM_EC_VBOOT_EFS2=y
+CONFIG_PLATFORM_EC_VBOOT_HASH=y
+
+# Application processor; communicates with EC via eSPI
+CONFIG_AP=y
+CONFIG_AP_X86_INTEL_ADL=y
+CONFIG_ESPI=y
+CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S4=y
+CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S5=y
+CONFIG_PLATFORM_EC_HOSTCMD=y
+CONFIG_HCDEBUG_OFF=y
+CONFIG_PLATFORM_EC_THROTTLE_AP=y
+CONFIG_PLATFORM_EC_PORT80=y
+CONFIG_PLATFORM_EC_PORT80_QUIET=y
+
+# AP Power Sequencing
+CONFIG_X86_NON_DSX_PWRSEQ_ADL=y
+CONFIG_X86_NON_DSX_PWRSEQ_CONSOLE=y
+CONFIG_X86_NON_DSX_PWRSEQ_HOST_CMD=y
+CONFIG_AP_PWRSEQ_S0IX=y
+CONFIG_AP_PWRSEQ_S0IX_ERROR_RECOVERY=y
+
+# Keyboard support
+CONFIG_PLATFORM_EC_KBLIGHT_ENABLE_PIN=y
+CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_8042=y
+CONFIG_PLATFORM_EC_VOLUME_BUTTONS=y
+CONFIG_PLATFORM_EC_CMD_BUTTON=n
+# Column 2 is driven through the GSC, which inverts the signal going through it
+CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED=y
+
+# LED
+CONFIG_PLATFORM_EC_LED_COMMON=y
+CONFIG_PLATFORM_EC_LED_ONOFF_STATES=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_LEDTEST=n
+
+# MKBP event
+CONFIG_PLATFORM_EC_MKBP_EVENT=y
+CONFIG_PLATFORM_EC_MKBP_INPUT_DEVICES=y
+CONFIG_PLATFORM_EC_MKBP_USE_GPIO_AND_HOST_EVENT=y
+
+# Temperature sensor support
+CONFIG_PLATFORM_EC_TEMP_SENSOR_FIRST_READ_DELAY=y
+
+# CBI EEPROM support
+CONFIG_EEPROM=y
+CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=y
+
+# PWM support
+CONFIG_PWM_SHELL=y
+
+# Sensors support
+CONFIG_PLATFORM_EC_LID_ANGLE=y
+CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=y
+CONFIG_PLATFORM_EC_ACCEL_FIFO=y
+CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=y
+
+# USB-C: enable PD on up to two ports
+CONFIG_PLATFORM_EC_USBC=y
+CONFIG_PLATFORM_EC_USBC_PPC=n
+CONFIG_PLATFORM_EC_USB_VID=0x18d1
+CONFIG_PLATFORM_EC_USB_PID=0x505a
+# USB4 and TBT are unsupported
+CONFIG_PLATFORM_EC_USB_PD_USB4=n
+CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=n
+CONFIG_PLATFORM_EC_USB_PD_REQUIRE_AP_MODE_ENTRY=n
+# TCPC interrupts are shared with BC1.2 and require additional processing
+# to ensure interrupts can't be lost due to shared use.
+CONFIG_PLATFORM_EC_TCPC_INTERRUPT=n
+
+CONFIG_PLATFORM_EC_USB_MUX_RUNTIME_CONFIG=y
+# ADL integrated muxes are slow: unblock PD
+CONFIG_PLATFORM_EC_USB_MUX_TASK=y
+
+# USB-C TCPC and PPC standard options
+CONFIG_PLATFORM_EC_USB_PD_TCPC_LOW_POWER=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_CHARGER=y
+
+# USB-A host ports
+CONFIG_PLATFORM_EC_USB_PORT_ENABLE_DYNAMIC=y
+
+# Battery support
+CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y
+CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO=y
+CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y
+CONFIG_PLATFORM_EC_BATTERY_REVIVE_DISCONNECT=y
+
+# Charger support
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=10
+CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y
+CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC_CHARGER=y
+CONFIG_PLATFORM_EC_OCPC_DEF_DRIVELIMIT_MILLIVOLTS=200
+# Assume 4% overdraw, which could be changed with actual characterization
+CONFIG_PLATFORM_EC_CHARGER_INPUT_CURRENT_DERATE_PCT=4
+
+# Reduce logging so that state transitions do not cause protocol issues
+# pd dump [1-3] can be used to increase the debugging level
+CONFIG_PLATFORM_EC_USB_PD_INITIAL_DEBUG_LEVEL=0
+
+# System-side power distribution is designed to be robust up to about 45W, and
+# higher input power may have negative reliability implications (especially for
+# systems with 2S batteries). Most devices can't exceed 45W sinking anyway, so
+# limit charger power to keep system input current within the design range.
+CONFIG_PLATFORM_EC_PD_MAX_POWER_MW=45000
+# 15V input is slightly more efficient than 20V for all supported chargers, and
+# because power is limited to 45W for other reasons (see above) limiting input
+# voltage like this does not compromise the total power capacity of the system.
+CONFIG_PLATFORM_EC_PD_MAX_VOLTAGE_MV=15000
diff --git a/zephyr/program/nissa/pujjo/cbi.dtsi b/zephyr/program/nissa/pujjo/cbi.dtsi
new file mode 100644
index 0000000000..02057140a5
--- /dev/null
+++ b/zephyr/program/nissa/pujjo/cbi.dtsi
@@ -0,0 +1,190 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	/* Pujjo-specific fw_config fields. */
+	nissa-fw-config {
+		/*
+		 * FW_CONFIG field to enable KB back light or not.
+		 */
+		kb-bl {
+			enum-name = "FW_KB_BL";
+			start = <3>;
+			size = <1>;
+
+			no-kb-bl {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_KB_BL_NOT_PRESENT";
+				value = <0>;
+			};
+			kb-bl-present {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_KB_BL_PRESENT";
+				value = <1>;
+			};
+		};
+
+		/*
+		 * FW_CONFIG field for KB PWB present or not.
+		 */
+		kb-pwb {
+			enum-name = "FW_KB_PWB";
+			start = <4>;
+			size = <1>;
+
+			no-kb-pwb {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_KB_PWB_NOT_PRESENT";
+				value = <0>;
+			};
+			kb-pwb-present {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_KB_PWB_PRESENT";
+				value = <1>;
+			};
+		};
+
+		/*
+		 * FW_CONFIG field for tablet present or not.
+		 */
+		tablet {
+			enum-name = "FW_TABLET";
+			start = <5>;
+			size = <1>;
+
+			no-tablet {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_TABLET_NOT_PRESENT";
+				value = <0>;
+			};
+			tablet-present {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_TABLET_PRESENT";
+				value = <1>;
+			};
+		};
+
+		/*
+		 * FW_CONFIG field for LTE board present or not.
+		 *
+		 *	start = <6>;
+		 *	size = <1>;
+		 */
+
+		/*
+		 * FW_CONFIG field for SD card present or not.
+		 *
+		 *	start = <7>;
+		 *	size = <1>;
+		 */
+
+		/*
+		 * FW_CONFIG field for pen present or not.
+		 */
+		pen {
+			enum-name = "FW_PEN";
+			start = <8>;
+			size = <1>;
+
+			no-pen {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_PEN_NOT_PRESENT";
+				value = <0>;
+			};
+			pen-present {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_PEN_PRESENT";
+				value = <1>;
+			};
+		};
+
+		/*
+		 * FW_CONFIG field for WF camera present or not.
+		 *
+		 *	start = <9>;
+		 *	size = <1>;
+		 */
+
+		/*
+		 * FW_CONFIG field for multiple thermal table.
+		 */
+		therm-table {
+			enum-name = "THERM_TABLE";
+			start = <10>;
+			size = <2>;
+
+			therm-table-1 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "THERM_TABLE_1";
+				value = <1>;
+			};
+		};
+
+		/*
+		 * FW_CONFIG field for multiple audio module.
+		 *
+		 *	start = <12>;
+		 *	size = <3>;
+		 */
+
+		/*
+		 * FW_CONFIG field for EXT_VR.
+		 *
+		 *	start = <15>;
+		 *	size = <1>;
+		 */
+
+		/*
+		 * FW_CONFIG field for multiple wi-fi SAR.
+		 *
+		 *	start = <16>;
+		 *	size = <2>;
+		 */
+	};
+
+	/* Pujjo-specific ssfc fields. */
+	cbi-ssfc {
+		compatible = "cros-ec,cbi-ssfc";
+		/*
+		 * SSFC field to identify BASE motion sensor.
+		 */
+		base-sensor {
+			enum-name = "BASE_SENSOR";
+			size = <2>;
+
+			base_sensor_0: bmi323 {
+				compatible = "cros-ec,cbi-ssfc-value";
+				status = "okay";
+				value = <0>;
+				default;
+			};
+			base_sensor_1: lsm6dsm {
+				compatible = "cros-ec,cbi-ssfc-value";
+				status = "okay";
+				value = <1>;
+			};
+		};
+
+		/*
+		 * SSFC field to identify LID motion sensor.
+		 */
+		lid-sensor {
+			enum-name = "LID_SENSOR";
+			size = <2>;
+
+			lid_sensor_0: bma422 {
+				compatible = "cros-ec,cbi-ssfc-value";
+				status = "okay";
+				value = <0>;
+				default;
+			};
+			lid_sensor_1: lis2dw12 {
+				compatible = "cros-ec,cbi-ssfc-value";
+				status = "okay";
+				value = <1>;
+			};
+		};
+	};
+};
diff --git a/zephyr/program/nissa/pujjo/generated.dtsi b/zephyr/program/nissa/pujjo/generated.dtsi
new file mode 100644
index 0000000000..46da0e4a02
--- /dev/null
+++ b/zephyr/program/nissa/pujjo/generated.dtsi
@@ -0,0 +1,277 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * This file is auto-generated - do not edit!
+ */
+
+/ {
+
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc {
+			enum-name = "ADC_PP1050_PROC";
+			io-channels = <&adc0 4>;
+		};
+		adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 {
+			enum-name = "ADC_PP3300_S5";
+			io-channels = <&adc0 6>;
+		};
+		adc_temp_sensor_1: temp_sensor_1 {
+			enum-name = "ADC_TEMP_SENSOR_1";
+			io-channels = <&adc0 0>;
+		};
+		adc_temp_sensor_2: temp_sensor_2 {
+			enum-name = "ADC_TEMP_SENSOR_2";
+			io-channels = <&adc0 1>;
+		};
+		adc_temp_sensor_3: temp_sensor_3 {
+			enum-name = "ADC_TEMP_SENSOR_3";
+			io-channels = <&adc0 10>;
+		};
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		gpio_acc_int_l: acc_int_l {
+			gpios = <&gpio5 0 GPIO_INPUT>;
+		};
+		gpio_all_sys_pwrgd: all_sys_pwrgd {
+			gpios = <&gpioa 7 GPIO_INPUT>;
+		};
+		gpio_ccd_mode_odl: ccd_mode_odl {
+			gpios = <&gpioe 5 GPIO_INPUT>;
+			enum-name = "GPIO_CCD_MODE_ODL";
+		};
+		gpio_cpu_c10_gate_l: cpu_c10_gate_l {
+			gpios = <&gpio6 7 GPIO_INPUT>;
+		};
+		gpio_ec_battery_pres_odl: ec_battery_pres_odl {
+			gpios = <&gpioa 3 GPIO_INPUT>;
+			enum-name = "GPIO_BATT_PRES_ODL";
+		};
+		gpio_ec_cbi_wp: ec_cbi_wp {
+			gpios = <&gpio7 4 GPIO_OUTPUT>;
+		};
+		gpio_ec_edp_bl_en_od: ec_edp_bl_en_od {
+			gpios = <&gpiod 3 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_ENABLE_BACKLIGHT";
+		};
+		gpio_ec_entering_rw: ec_entering_rw {
+			gpios = <&gpio0 3 GPIO_OUTPUT>;
+			enum-name = "GPIO_ENTERING_RW";
+		};
+		gpio_ec_gsc_packet_mode: ec_gsc_packet_mode {
+			gpios = <&gpio7 5 GPIO_OUTPUT>;
+			enum-name = "GPIO_PACKET_MODE_EN";
+		};
+		gpio_ec_kso_02_inv: ec_kso_02_inv {
+			gpios = <&gpio1 7 (GPIO_OUTPUT_LOW | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_ec_pch_wake_odl: ec_pch_wake_odl {
+			gpios = <&gpiob 0 GPIO_ODR_LOW>;
+		};
+		gpio_ec_prochot_odl: ec_prochot_odl {
+			gpios = <&gpiof 1 GPIO_ODR_HIGH>;
+		};
+		gpio_ec_soc_dsw_pwrok: ec_soc_dsw_pwrok {
+			gpios = <&gpio6 1 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_hdmi_hpd: ec_soc_hdmi_hpd {
+			gpios = <&gpioe 4 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_int_odl: ec_soc_int_odl {
+			gpios = <&gpio8 0 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_EC_INT_L";
+		};
+		gpio_ec_soc_pch_pwrok_od: ec_soc_pch_pwrok_od {
+			gpios = <&gpio7 2 GPIO_ODR_HIGH>;
+		};
+		gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl {
+			gpios = <&gpioc 1 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_PCH_PWRBTN_L";
+		};
+		gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l {
+			gpios = <&gpioa 6 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_rtcrst: ec_soc_rtcrst {
+			gpios = <&gpio7 6 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_sys_pwrok: ec_soc_sys_pwrok {
+			gpios = <&gpio3 7 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_vccst_pwrgd_od: ec_soc_vccst_pwrgd_od {
+			gpios = <&gpioa 4 GPIO_ODR_HIGH>;
+		};
+		gpio_ec_wp_odl: ec_wp_odl {
+			gpios = <&gpioa 1 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_en_kb_bl: en_kb_bl {
+			gpios = <&gpioa 0 GPIO_OUTPUT>;
+			enum-name = "GPIO_EN_KEYBOARD_BACKLIGHT";
+		};
+		gpio_en_pp3300_s5: en_pp3300_s5 {
+			gpios = <&gpiob 6 GPIO_OUTPUT>;
+			enum-name = "GPIO_TEMP_SENSOR_POWER";
+		};
+		gpio_en_pp5000_pen_x: en_pp5000_pen_x {
+			gpios = <&gpioe 2 GPIO_OUTPUT>;
+		};
+		gpio_en_pp5000_s5: en_pp5000_s5 {
+			gpios = <&gpio4 0 GPIO_OUTPUT>;
+		};
+		gpio_en_slp_z: en_slp_z {
+			gpios = <&gpioe 1 GPIO_OUTPUT>;
+		};
+		gpio_en_usb_a0_vbus: en_usb_a0_vbus {
+			gpios = <&gpio9 1 GPIO_OUTPUT>;
+		};
+		gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl {
+			gpios = <&gpio0 0 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		gpio_hdmi_sel: hdmi_sel {
+			gpios = <&gpioc 6 GPIO_OUTPUT>;
+		};
+		gpio_imu_int_l: imu_int_l {
+			gpios = <&gpio5 6 GPIO_INPUT>;
+		};
+		gpio_imvp91_vrrdy_od: imvp91_vrrdy_od {
+			gpios = <&gpio4 3 GPIO_INPUT>;
+		};
+		gpio_lid_open: lid_open {
+			gpios = <&gpiod 2 GPIO_INPUT>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+		gpio_pen_detect_odl: pen_detect_odl {
+			gpios = <&gpio9 6 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_pg_pp1050_mem_s3_od: pg_pp1050_mem_s3_od {
+			gpios = <&gpiof 0 GPIO_INPUT>;
+		};
+		gpio_pg_pp5000_s5_od: pg_pp5000_s5_od {
+			gpios = <&gpio4 2 GPIO_INPUT>;
+		};
+		gpio_rsmrst_pwrgd_l: rsmrst_pwrgd_l {
+			gpios = <&gpio9 4 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_slp_s0_l: slp_s0_l {
+			gpios = <&gpio9 7 GPIO_INPUT>;
+		};
+		gpio_slp_s3_l: slp_s3_l {
+			gpios = <&gpioa 5 GPIO_INPUT>;
+		};
+		gpio_slp_s4_l: slp_s4_l {
+			gpios = <&gpio7 0 GPIO_INPUT>;
+		};
+		gpio_slp_sus_l: slp_sus_l {
+			gpios = <&gpio6 2 GPIO_INPUT>;
+		};
+		gpio_sub_usb_a1_ilimit_sdp: sub_usb_a1_ilimit_sdp {
+			gpios = <&gpiod 5 GPIO_OUTPUT>;
+			enum-name = "GPIO_USB2_ILIM_SEL";
+		};
+		gpio_sys_rst_odl: sys_rst_odl {
+			gpios = <&gpioc 5 GPIO_ODR_HIGH>;
+		};
+		gpio_tablet_mode_l: tablet_mode_l {
+			gpios = <&gpio9 5 GPIO_INPUT>;
+			enum-name = "GPIO_TABLET_MODE_L";
+		};
+		gpio_usb_a0_ilimit_sdp: usb_a0_ilimit_sdp {
+			gpios = <&gpio8 5 GPIO_OUTPUT>;
+			enum-name = "GPIO_USB1_ILIM_SEL";
+		};
+		gpio_usb_c0_int_odl: usb_c0_int_odl {
+			gpios = <&gpio0 1 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_vccin_aux_vid0: vccin_aux_vid0 {
+			gpios = <&gpio9 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		gpio_vccin_aux_vid1: vccin_aux_vid1 {
+			gpios = <&gpioe 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		gpio_voldn_btn_odl: voldn_btn_odl {
+			gpios = <&gpio9 3 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_DOWN_L";
+		};
+		gpio_volup_btn_odl: volup_btn_odl {
+			gpios = <&gpioa 2 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_UP_L";
+		};
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		i2c_ec_i2c_eeprom: ec_i2c_eeprom {
+			i2c-port = <&i2c0_0>;
+			enum-names = "I2C_PORT_EEPROM";
+		};
+		i2c_ec_i2c_sensor: ec_i2c_sensor {
+			i2c-port = <&i2c1_0>;
+			enum-names = "I2C_PORT_SENSOR";
+		};
+		i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 {
+			i2c-port = <&i2c3_0>;
+			enum-names = "I2C_PORT_USB_C0_TCPC";
+		};
+		i2c_ec_i2c_batt: ec_i2c_batt {
+			i2c-port = <&i2c7_0>;
+			enum-names = "I2C_PORT_BATTERY";
+		};
+	};
+};
+
+&adc0 {
+	status = "okay";
+	pinctrl-0 = <&adc0_chan0_gp45
+		     &adc0_chan1_gp44
+		     &adc0_chan4_gp41
+		     &adc0_chan6_gp34
+		     &adc0_chan10_gpe0>;
+	pinctrl-names = "default";
+};
+
+
+&i2c0_0 {
+	status = "okay";
+	pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>;
+	pinctrl-names = "default";
+};
+
+&i2c1_0 {
+	status = "okay";
+	pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>;
+	pinctrl-names = "default";
+};
+
+&i2c3_0 {
+	status = "okay";
+	pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>;
+	pinctrl-names = "default";
+};
+
+&i2c7_0 {
+	status = "okay";
+	pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>;
+	pinctrl-names = "default";
+};
+
+&i2c_ctrl0 {
+	status = "okay";
+};
+
+&i2c_ctrl1 {
+	status = "okay";
+};
+
+&i2c_ctrl3 {
+	status = "okay";
+};
+
+&i2c_ctrl7 {
+	status = "okay";
+};
diff --git a/zephyr/program/nissa/pujjo/keyboard.dtsi b/zephyr/program/nissa/pujjo/keyboard.dtsi
new file mode 100644
index 0000000000..5121779674
--- /dev/null
+++ b/zephyr/program/nissa/pujjo/keyboard.dtsi
@@ -0,0 +1,47 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	kblight {
+		compatible = "cros-ec,kblight-pwm";
+		pwms = <&pwm6 6 PWM_KHZ(20) PWM_POLARITY_NORMAL>;
+	};
+};
+
+&pwm6 {
+	status = "okay";
+	pinctrl-0 = <&pwm6_gpc0>;
+	pinctrl-names = "default";
+};
+
+&cros_kb_raw {
+	status = "okay";
+	/* No KSO2 (it's inverted and implemented by GPIO) */
+	pinctrl-0 = <
+		&ksi0_gp31
+		&ksi1_gp30
+		&ksi2_gp27
+		&ksi3_gp26
+		&ksi4_gp25
+		&ksi5_gp24
+		&ksi6_gp23
+		&ksi7_gp22
+		&kso00_gp21
+		&kso01_gp20
+		&kso03_gp16
+		&kso04_gp15
+		&kso05_gp14
+		&kso06_gp13
+		&kso07_gp12
+		&kso08_gp11
+		&kso09_gp10
+		&kso10_gp07
+		&kso11_gp06
+		&kso12_gp05
+		&kso13_gp04
+		&kso14_gp82
+	>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/nissa/pujjo/motionsense.dtsi b/zephyr/program/nissa/pujjo/motionsense.dtsi
new file mode 100644
index 0000000000..af21e0509e
--- /dev/null
+++ b/zephyr/program/nissa/pujjo/motionsense.dtsi
@@ -0,0 +1,245 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/motionsense/utils.h>
+
+
+/ {
+	aliases {
+		/*
+		 * Interrupt bindings for sensor devices.
+		 */
+		bmi3xx-int = &base_accel;
+		lsm6dsm-int = &base_accel;
+		lis2dw12-int = &lid_accel;
+		bma4xx-int = &lid_accel;
+	};
+
+	/*
+	 * Declare mutexes used by sensor drivers.
+	 * A mutex node is used to create an instance of mutex_t.
+	 * A mutex node is referenced by a sensor node if the
+	 * corresponding sensor driver needs to use the
+	 * instance of the mutex.
+	 */
+	motionsense-mutex {
+		compatible = "cros-ec,motionsense-mutex";
+		lid_mutex: lid-mutex {
+		};
+
+		base_mutex: base-mutex {
+		};
+	};
+
+	/* Rotation matrix used by drivers. */
+	motionsense-rotation-ref {
+		compatible = "cros-ec,motionsense-rotation-ref";
+		lid_rot_ref: lid-rotation-ref {
+			mat33 = <0 (-1) 0
+				 (-1) 0 0
+				 0 0 (-1)>;
+		};
+
+		lid_rot_lis2dw12: lid-rotation-lis2dw12 {
+			mat33 = <0 (-1) 0
+				 (-1) 0 0
+				 0 0 (-1)>;
+		};
+
+		base_rot_ref: base-rotation-ref {
+			mat33 = <0 1 0
+				 (-1) 0 0
+				 0 0 1>;
+		};
+
+		base_rot_lsm6dsm: base-rotation-lsm6dsm {
+			mat33 = <1 0 0
+				 0 1 0
+				 0 0 1>;
+		};
+	};
+
+	/*
+	 * Driver specific data. A driver-specific data can be shared with
+	 * different motion sensors while they are using the same driver.
+	 *
+	 * If a node's compatible starts with "cros-ec,accelgyro-", it is for
+	 * a common structure defined in accelgyro.h.
+	 * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for
+	 * "struct als_drv_data_t" in accelgyro.h
+	 */
+	motionsense-sensor-data {
+		bmi323_data: bmi323-drv-data {
+			compatible = "cros-ec,drvdata-bmi3xx";
+			status = "okay";
+		};
+
+		lsm6dsm_data_accel: lsm6dsm-accel-drv-data {
+			compatible = "cros-ec,drvdata-lsm6dsm";
+			status = "okay";
+		};
+
+		lsm6dsm_data_gyro: lsm6dsm-gyro-drv-data {
+			compatible = "cros-ec,drvdata-lsm6dsm";
+			status = "okay";
+		};
+
+		bma422_data: bma422-drv-data {
+			compatible = "cros-ec,drvdata-bma4xx";
+			status = "okay";
+		};
+
+		lis2dw12_data: lis2dw12-drv-data {
+			compatible = "cros-ec,drvdata-lis2dw12";
+			status = "okay";
+		};
+	};
+
+	/*
+	 * List of motion sensors that creates motion_sensors array.
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
+	 * motion sensor IDs for lid angle calculation.
+	 * TODO(b/238139272): The first entries of the array must be
+	 * accelerometers,then gyroscope. Fix this dependency in the DTS
+	 * processing which makes the devicetree entries independent.
+	 */
+	motionsense-sensor {
+		lid_accel: lid-accel {
+			compatible = "cros-ec,bma4xx";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&lid_mutex>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&lid_rot_ref>;
+			default-range = <2>;
+			drv-data = <&bma422_data>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_accel: base-accel {
+			compatible = "cros-ec,bmi3xx-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&bmi323_data>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_gyro: base-gyro {
+			compatible = "cros-ec,bmi3xx-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&bmi323_data>;
+		};
+	};
+
+	motionsense-sensor-alt {
+		alt_lid_accel: alt-lid-accel {
+			compatible = "cros-ec,lis2dw12";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&lid_mutex>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&lid_rot_lis2dw12>;
+			default-range = <2>;
+			drv-data = <&lis2dw12_data>;
+			i2c-spi-addr-flags = "LIS2DWL_ADDR1_FLAGS";
+			alternate-for = <&lid_accel>;
+			alternate-ssfc-indicator = <&lid_sensor_1>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		alt_base_accel: alt-base-accel {
+			compatible = "cros-ec,lsm6dsm-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&base_rot_lsm6dsm>;
+			drv-data = <&lsm6dsm_data_accel>;
+			alternate-for = <&base_accel>;
+			alternate-ssfc-indicator = <&base_sensor_1>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+					ec-rate = <(100 * USEC_PER_MSEC)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+					ec-rate = <0>;
+				};
+			};
+		};
+
+		alt_base_gyro: alt-base-gyro {
+			compatible = "cros-ec,lsm6dsm-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&base_rot_lsm6dsm>;
+			drv-data = <&lsm6dsm_data_gyro>;
+			default-range = <(1000 | ROUND_UP_FLAG)>; /* dps */
+			alternate-for = <&base_gyro>;
+			alternate-ssfc-indicator = <&base_sensor_1>;
+		};
+	};
+
+	motionsense-sensor-info {
+		compatible = "cros-ec,motionsense-sensor-info";
+
+		/*
+		 * list of GPIO interrupts that have to
+		 * be enabled at initial stage
+		 */
+		sensor-irqs = <&int_imu &int_lid_accel>;
+	};
+};
diff --git a/zephyr/program/nissa/pujjo/overlay.dtsi b/zephyr/program/nissa/pujjo/overlay.dtsi
new file mode 100644
index 0000000000..b2f42cf02d
--- /dev/null
+++ b/zephyr/program/nissa/pujjo/overlay.dtsi
@@ -0,0 +1,380 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <cros/thermistor/thermistor.dtsi>
+#include <dt-bindings/usb_pd_tcpm.h>
+
+/ {
+	aliases {
+		gpio-cbi-wp = &gpio_ec_cbi_wp;
+		gpio-wp = &gpio_ec_wp_odl;
+		int-wp = &int_wp_l;
+		gpio-kbd-kso2 = &gpio_ec_kso_02_inv;
+	};
+
+	ec-console {
+		compatible = "ec-console";
+		disabled = "events", "lpc", "hostcmd";
+	};
+
+	batteries {
+		default_battery: smp {
+			compatible = "smp,l22m3pg0", "battery-smart";
+		};
+		smp_l22m3pg1 {
+			compatible = "smp,l22m3pg1", "battery-smart";
+		};
+		sunwoda_l22d3pg0 {
+			compatible = "sunwoda,l22d3pg0", "battery-smart";
+		};
+		sunwoda_l22d3pg1 {
+			compatible = "sunwoda,l22d3pg1", "battery-smart";
+		};
+		celxpert_l22c3pg0 {
+			compatible = "celxpert,l22c3pg0", "battery-smart";
+		};
+	};
+
+	hibernate-wake-pins {
+		compatible = "cros-ec,hibernate-wake-pins";
+		wakeup-irqs = <
+			&int_power_button
+			&int_lid_open
+		>;
+	};
+
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_power_button: power_button {
+			irq-pin = <&gpio_gsc_ec_pwr_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_button_interrupt";
+		};
+		int_wp_l: wp_l {
+			irq-pin = <&gpio_ec_wp_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "switch_interrupt";
+		};
+		int_lid_open: lid_open {
+			irq-pin = <&gpio_lid_open>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "lid_interrupt";
+		};
+		int_tablet_mode: tablet_mode {
+			irq-pin = <&gpio_tablet_mode_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "gmr_tablet_switch_isr";
+		};
+		int_imu: ec_imu {
+			irq-pin = <&gpio_imu_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "motion_interrupt";
+		};
+		int_lid_accel: lid_accel {
+			irq-pin = <&gpio_acc_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "lid_accel_interrupt";
+		};
+		int_vol_down: vol_down {
+			irq-pin = <&gpio_voldn_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+		int_vol_up: vol_up {
+			irq-pin = <&gpio_volup_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+		int_usb_c0: usb_c0 {
+			irq-pin = <&gpio_usb_c0_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "usb_interrupt";
+		};
+	};
+
+	named-gpios {
+		gpio_sb_2: sb_2 {
+			gpios = <&gpiod 4 GPIO_OUTPUT>;
+			no-auto-init;
+		};
+
+		gpio_sb_3: sb_3 {
+			gpios = <&gpiof 5 (GPIO_OPEN_DRAIN | GPIO_VOLTAGE_1P8)>;
+			no-auto-init;
+		};
+		gpio_sb_4: sb_4 {
+			gpios = <&gpiof 4 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+			no-auto-init;
+		};
+		gpio_fan_enable: fan-enable {
+			gpios = <&gpio6 3 GPIO_OUTPUT>;
+			no-auto-init;
+		};
+		ec-i2c-sensor-scl {
+			gpios = <&gpio9 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		ec-i2c-sensor-sda {
+			gpios = <&gpio8 7 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		gpio_power_led: power_led {
+			gpios = <&gpioc 2 GPIO_OUTPUT_LOW>;
+		};
+		gpio_led_1_odl: led_1_odl {
+			gpios = <&gpioc 4 GPIO_OUTPUT_LOW>;
+		};
+		gpio_led_2_odl: led_2_odl {
+			gpios = <&gpioc 3 GPIO_OUTPUT_LOW>;
+		};
+	};
+
+	/*
+	 * Aliases used for sub-board GPIOs.
+	 */
+	aliases {
+		/*
+		 * Sub-board with type A USB, enable.
+		 */
+		gpio-en-usb-a1-vbus = &gpio_sb_2;
+		/*
+		 * HPD pins for HDMI sub-board.
+		 */
+		gpio-hdmi-en-odl = &gpio_sb_3;
+		gpio-hpd-odl = &gpio_sb_4;
+		/*
+		 * Enable S5 rails for LTE sub-board
+		 */
+		gpio-en-sub-s5-rails = &gpio_sb_2;
+	};
+
+	temp_cpu: cpu {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_1>;
+	};
+	temp_ddr: ddr {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_2>;
+	};
+	temp_ambient: ambient {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_3>;
+	};
+
+	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
+		cpu {
+			temp_fan_off = <35>;
+			temp_fan_max = <60>;
+			temp_host_high = <90>;
+			temp_host_halt = <100>;
+			temp_host_release_high = <85>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_cpu>;
+		};
+		ddr {
+			temp_fan_off = <35>;
+			temp_fan_max = <60>;
+			temp_host_high = <90>;
+			temp_host_halt = <100>;
+			temp_host_release_high = <85>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_ddr>;
+		};
+		ambient {
+			temp_fan_off = <35>;
+			temp_fan_max = <60>;
+			temp_host_high = <90>;
+			temp_host_halt = <100>;
+			temp_host_release_high = <85>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_ambient>;
+		};
+	};
+
+	usba {
+		compatible = "cros-ec,usba-port-enable-pins";
+		/*
+		 * sb_2 is only configured as GPIO when USB-A1 is present,
+		 * but it's still safe to control when disabled.
+		 *
+		 * ILIM_SEL pins are referred to by legacy enum name,
+		 * GPIO_USB*_ILIM_SEL. The one for port A1 is unused on
+		 * sub-boards that don't have USB-A so is safe to control
+		 * regardless of system configuration.
+		 */
+		enable-pins = <&gpio_en_usb_a0_vbus &gpio_sb_2>;
+		status = "okay";
+	};
+
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+			bc12 = <&bc12_port0>;
+			chg = <&chg_port0>;
+			tcpc = <&tcpc_port0>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_0>;
+			};
+		};
+		port0-muxes {
+			virtual_mux_0: virtual-mux-0 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+	};
+
+	fans {
+		compatible = "cros-ec,fans";
+
+		fan_0 {
+			pwms = <&pwm5 5 PWM_KHZ(1) PWM_POLARITY_NORMAL>;
+			rpm_min = <2200>;
+			rpm_start = <2200>;
+			rpm_max = <4200>;
+			tach = <&tach2>;
+			enable_gpio = <&gpio_fan_enable>;
+		};
+	};
+
+	 /*
+	  * Declare unused GPIOs so that they are shut down
+	  * and use minimal power
+	  */
+	  unused-pins {
+		compatible = "unused-gpios";
+		unused-gpios =
+			<&gpio3 2 0>,
+			<&gpio3 3 0>,
+			<&gpio3 5 0>,
+			<&gpio3 6 0>,
+			<&gpio5 7 0>,
+			<&gpio6 0 0>,
+			<&gpio6 6 0>,
+			<&gpio8 3 0>,
+			<&gpio8 6 0>,
+			<&gpiob 1 0>,
+			<&gpioc 7 0>,
+			<&gpiod 7 0>,
+			<&gpiof 2 0>,
+			<&gpiof 3 0>;
+	 };
+};
+
+&thermistor_3V3_51K1_47K_4050B {
+	status = "okay";
+};
+
+&adc_ec_vsense_pp3300_s5 {
+	/*
+	 * Voltage divider on input has 47k upper and 220k lower legs with
+	 * 2714 mV full-scale reading on the ADC. Apply the largest possible
+	 * multiplier (without overflowing int32) to get the best possible
+	 * approximation of the actual ratio, but derate by a factor of two to
+	 * ensure unexpectedly high values won't overflow.
+	 */
+	mul = <(791261 / 2)>;
+	div = <(651975 / 2)>;
+};
+
+/* Set bus speeds for I2C */
+&i2c0_0 {
+	label = "I2C_EEPROM";
+	clock-frequency = <I2C_BITRATE_FAST>;
+
+	cbi_eeprom: eeprom@50 {
+		compatible = "atmel,at24";
+		reg = <0x50>;
+		size = <2048>;
+		pagesize = <16>;
+		address-width = <8>;
+		timeout = <5>;
+	};
+};
+
+&i2c1_0 {
+	label = "I2C_SENSOR";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&i2c3_0 {
+	label = "I2C_USB_C0_TCPC";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+
+	bc12_port0: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+		/*
+		 * BC1.2 interrupt is shared with TCPC, so
+		 * IRQ is not specified here and handled by
+		 * usb_c0_interrupt.
+		 */
+	};
+
+	chg_port0: isl923x@9 {
+		compatible = "intersil,isl923x";
+		status = "okay";
+		reg = <0x9>;
+	};
+
+	tcpc_port0: raa489000@22 {
+		compatible = "renesas,raa489000";
+		reg = <0x22>;
+		tcpc-flags = <(
+			TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_VBUS_MONITOR)>;
+	};
+};
+
+&i2c7_0 {
+	label = "I2C_BATTERY";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+};
+
+&pwm5_gpb7 {
+	drive-open-drain;
+};
+
+&pwm5 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm5_gpb7>;
+	pinctrl-names = "default";
+};
+
+/* Tachometer for fan speed measurement */
+&tach2 {
+	status = "okay";
+	pinctrl-0 = <&ta2_1_in_gp73>;
+	pinctrl-names = "default";
+	port = <NPCX_TACH_PORT_A>; /* port-A is selected */
+	sample-clk = <NPCX_TACH_FREQ_LFCLK>; /* Use LFCLK as sampling clock */
+	pulses-per-round = <2>; /* number of pulses per round of encoder */
+};
+
+/* host interface */
+&espi0 {
+	status = "okay";
+	pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>;
+	pinctrl-names = "default";
+};
+
+/*
+ * Declare GPIOs that have leakage current caused by board issues here. NPCX ec
+ * will disable their input buffers before entering deep sleep and restore them
+ * after waking up automatically for better power consumption.
+ */
+&power_leakage_io {
+	leak-gpios = <&gpioa 4 GPIO_OPEN_DRAIN
+		      &gpiof 1 GPIO_OPEN_DRAIN>;
+};
diff --git a/zephyr/program/nissa/pujjo/power_signals.dtsi b/zephyr/program/nissa/pujjo/power_signals.dtsi
new file mode 100644
index 0000000000..1d2b23069d
--- /dev/null
+++ b/zephyr/program/nissa/pujjo/power_signals.dtsi
@@ -0,0 +1,220 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	chosen {
+		intel-ap-pwrseq,espi = &espi0;
+	};
+
+	common-pwrseq {
+		compatible = "intel,ap-pwrseq";
+
+		sys-pwrok-delay = <10>;
+		all-sys-pwrgd-timeout = <20>;
+	};
+
+	pwr-en-pp5000-s5 {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PP5000_S5 enable output to regulator";
+		enum-name = "PWR_EN_PP5000_A";
+		gpios = <&gpio4 0 0>;
+		output;
+	};
+	pwr-en-pp3300-s5 {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PP3300_S5 enable output to LS";
+		enum-name = "PWR_EN_PP3300_A";
+		gpios = <&gpiob 6 0>;
+		output;
+	};
+	pwr-pg-ec-rsmrst-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST power good from regulator";
+		enum-name = "PWR_RSMRST";
+		gpios = <&gpio9 4 0>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-ec-pch-rsmrst-odl {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST output to PCH";
+		enum-name = "PWR_EC_PCH_RSMRST";
+		gpios = <&gpioa 6 0>;
+		output;
+	};
+	pwr-slp-s0-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_S0_L input from PCH";
+		enum-name = "PWR_SLP_S0";
+		gpios = <&gpio9 7 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-slp-s3-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_S3_L input from PCH";
+		enum-name = "PWR_SLP_S3";
+		gpios = <&gpioa 5 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-slp-sus-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_SUS_L input from PCH";
+		enum-name = "PWR_SLP_SUS";
+		gpios = <&gpio6 2 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-ec-soc-dsw-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "DSW_PWROK output to PCH";
+		enum-name = "PWR_EC_SOC_DSW_PWROK";
+		gpios = <&gpio6 1 0>;
+		output;
+	};
+	pwr-vccst-pwrgd-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "VCCST_PWRGD output to PCH";
+		enum-name = "PWR_VCCST_PWRGD";
+		gpios = <&gpioa 4 GPIO_OPEN_DRAIN>;
+		output;
+	};
+	pwr-imvp9-vrrdy-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "VRRDY input from IMVP9";
+		enum-name = "PWR_IMVP9_VRRDY";
+		gpios = <&gpio4 3 0>;
+	};
+	pwr-pch-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PCH_PWROK output to PCH";
+		enum-name = "PWR_PCH_PWROK";
+		gpios = <&gpio7 2 GPIO_OPEN_DRAIN>;
+		output;
+	};
+	pwr-ec-pch-sys-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_PWROK output to PCH";
+		enum-name = "PWR_EC_PCH_SYS_PWROK";
+		gpios = <&gpio3 7 0>;
+		output;
+	};
+	pwr-sys-rst-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_RESET# output to PCH";
+		enum-name = "PWR_SYS_RST";
+		gpios = <&gpioc 5 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>;
+		output;
+	};
+	pwr-slp-s4 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S4 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S4";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4";
+		vw-invert;
+	};
+	pwr-slp-s5 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S5 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S5";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5";
+		vw-invert;
+	};
+	pwr-all-sys-pwrgd {
+		compatible = "intel,ap-pwrseq-external";
+		dbg-label = "Combined all power good";
+		enum-name = "PWR_ALL_SYS_PWRGD";
+	};
+	pwr-adc-pp3300 {
+		compatible = "intel,ap-pwrseq-adc";
+		dbg-label = "PP3300 PWROK (from ADC)";
+		enum-name = "PWR_DSW_PWROK";
+		trigger-high = <&cmp_pp3300_s5_high>;
+		trigger-low = <&cmp_pp3300_s5_low>;
+	};
+	pwr-adc-pp1p05 {
+		compatible = "intel,ap-pwrseq-adc";
+		dbg-label = "PP1P05 PWROK (from ADC)";
+		enum-name = "PWR_PG_PP1P05";
+		trigger-high = <&cmp_pp1p05_high>;
+		trigger-low = <&cmp_pp1p05_low>;
+	};
+
+	adc-cmp {
+		cmp_pp3300_s5_high: pp3300_high {
+			compatible = "nuvoton,adc-cmp";
+			io-channels = <&adc0 6>;
+			comparison = "ADC_CMP_NPCX_GREATER";
+			/*
+			 * This is 90% of nominal voltage considering voltage
+			 * divider on ADC input.
+			 */
+			threshold-mv = <2448>;
+		};
+		cmp_pp3300_s5_low: pp3300_low {
+			compatible = "nuvoton,adc-cmp";
+			io-channels = <&adc0 6>;
+			comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL";
+			threshold-mv = <2448>;
+		};
+		cmp_pp1p05_high: pp1p05_high {
+			compatible = "nuvoton,adc-cmp";
+			io-channels = <&adc0 4>;
+			comparison = "ADC_CMP_NPCX_GREATER";
+			/* Setting at 90% of nominal voltage */
+			threshold-mv = <945>;
+		};
+		cmp_pp1p05_low: pp1p05_low {
+			compatible = "nuvoton,adc-cmp";
+			io-channels = <&adc0 4>;
+			comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL";
+			threshold-mv = <945>;
+		};
+	};
+};
+
+/*
+ * Because the power signals directly reference the GPIOs,
+ * the correspinding named-gpios need to have no-auto-init set.
+ */
+&gpio_ec_soc_dsw_pwrok {
+	no-auto-init;
+};
+&gpio_ec_soc_pch_pwrok_od {
+	no-auto-init;
+};
+&gpio_ec_soc_rsmrst_l {
+	no-auto-init;
+};
+&gpio_ec_soc_sys_pwrok {
+	no-auto-init;
+};
+&gpio_ec_soc_vccst_pwrgd_od {
+	no-auto-init;
+};
+&gpio_en_pp3300_s5 {
+	no-auto-init;
+};
+&gpio_en_pp5000_s5 {
+	no-auto-init;
+};
+&gpio_imvp91_vrrdy_od {
+	no-auto-init;
+};
+&gpio_rsmrst_pwrgd_l {
+	no-auto-init;
+};
+&gpio_slp_s0_l {
+	no-auto-init;
+};
+&gpio_slp_s3_l {
+	no-auto-init;
+};
+&gpio_slp_s4_l {
+	no-auto-init;
+};
+&gpio_slp_sus_l {
+	no-auto-init;
+};
+&gpio_sys_rst_odl {
+	no-auto-init;
+};
diff --git a/zephyr/program/nissa/pujjo/project.conf b/zephyr/program/nissa/pujjo/project.conf
new file mode 100644
index 0000000000..7bc035a7cd
--- /dev/null
+++ b/zephyr/program/nissa/pujjo/project.conf
@@ -0,0 +1,40 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_BOARD_PUJJO=y
+
+# Sensor drivers
+CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSM=y
+CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y
+CONFIG_PLATFORM_EC_DYNAMIC_MOTION_SENSOR_COUNT=y
+
+# Increase PD max power from default
+CONFIG_PLATFORM_EC_PD_MAX_POWER_MW=65000
+CONFIG_PLATFORM_EC_PD_MAX_VOLTAGE_MV=20000
+CONFIG_PLATFORM_EC_PD_MAX_CURRENT_MA=3250
+
+# LED
+CONFIG_PLATFORM_EC_LED_PWM=n
+CONFIG_PLATFORM_EC_LED_COMMON=y
+
+# DPS
+CONFIG_PLATFORM_EC_USB_PD_DPS=n
+
+# BTN
+CONFIG_PLATFORM_EC_BUTTONS_RUNTIME_CONFIG=y
+
+# Charger
+CONFIG_PLATFORM_EC_RAA489000_TRICKLE_CHARGE_CURRENT_256MA=y
+
+# Both ports use a smart switch with CTL1..3 fixed high, for SDP2 or CDP only:
+# either SLGC55545 or PI5USB2546.
+CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART=y
+CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_CDP_SDP_ONLY=y
+CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_DEFAULT_CDP=y
+CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_INVERTED=y
+
+#OCP
+CONFIG_PLATFORM_EC_RAA489000_OCP_UV_THRESHOLD_MV=4000
\ No newline at end of file
diff --git a/zephyr/program/nissa/pujjo/project.overlay b/zephyr/program/nissa/pujjo/project.overlay
new file mode 100644
index 0000000000..e498775714
--- /dev/null
+++ b/zephyr/program/nissa/pujjo/project.overlay
@@ -0,0 +1,13 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "../cbi.dtsi"
+
+#include "cbi.dtsi"
+#include "generated.dtsi"
+#include "keyboard.dtsi"
+#include "motionsense.dtsi"
+#include "overlay.dtsi"
+#include "power_signals.dtsi"
diff --git a/zephyr/program/nissa/pujjo/pujjo_vif.xml b/zephyr/program/nissa/pujjo/pujjo_vif.xml
new file mode 100644
index 0000000000..b7d462584a
--- /dev/null
+++ b/zephyr/program/nissa/pujjo/pujjo_vif.xml
@@ -0,0 +1,350 @@
+<?xml version="1.0" encoding="utf-8"?>
+<vif:VIF xmlns:opt="http://usb.org/VendorInfoFileOptionalContent.xsd" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:vif="http://usb.org/VendorInfoFile.xsd">
+  <vif:VIF_Specification>3.19</vif:VIF_Specification>
+  <vif:VIF_App>
+    <vif:Vendor>USB-IF</vif:Vendor>
+    <vif:Name>VIF Editor</vif:Name>
+    <vif:Version>3.2.4.0</vif:Version>
+  </vif:VIF_App>
+  <vif:Vendor_Name>Google</vif:Vendor_Name>
+  <vif:Model_Part_Number>Pujjo</vif:Model_Part_Number>
+  <vif:Product_Revision>1</vif:Product_Revision>
+  <vif:TID>0</vif:TID>
+  <vif:VIF_Product_Type value="0">Port Product</vif:VIF_Product_Type>
+  <vif:Certification_Type value="0">End Product</vif:Certification_Type>
+  <vif:Product>
+    <!--Product Level Content:-->
+  </vif:Product>
+  <vif:Component>
+    <!--Component 0: Port 0-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Component-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Port_Label>0</vif:Port_Label>
+    <vif:Connector_Type value="2">Type-C®</vif:Connector_Type>
+    <vif:USB4_Supported value="false" />
+    <vif:USB_PD_Support value="true" />
+    <vif:PD_Port_Type value="4">DRP</vif:PD_Port_Type>
+    <vif:Type_C_State_Machine value="2">DRP</vif:Type_C_State_Machine>
+    <vif:Port_Battery_Powered value="true" />
+    <vif:BC_1_2_Support value="2">Charging Port</vif:BC_1_2_Support>
+    <vif:Captive_Cable value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;General PD-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Spec_Revision_Major value="3" />
+    <vif:PD_Spec_Revision_Minor value="1" />
+    <vif:PD_Spec_Version_Major value="1" />
+    <vif:PD_Spec_Version_Minor value="3" />
+    <vif:PD_Specification_Revision value="2">Revision 3</vif:PD_Specification_Revision>
+    <vif:SOP_Capable value="true" />
+    <vif:SOP_P_Capable value="true" />
+    <vif:SOP_PP_Capable value="true" />
+    <vif:SOP_P_Debug_Capable value="false" />
+    <vif:SOP_PP_Debug_Capable value="false" />
+    <vif:Manufacturer_Info_Supported_Port value="true" />
+    <vif:Manufacturer_Info_VID_Port value="6353">18D1</vif:Manufacturer_Info_VID_Port>
+    <vif:Manufacturer_Info_PID_Port value="20570">505A</vif:Manufacturer_Info_PID_Port>
+    <vif:Chunking_Implemented_SOP value="true" />
+    <vif:Unchunked_Extended_Messages_Supported value="false" />
+    <vif:Security_Msgs_Supported_SOP value="false" />
+    <vif:Unconstrained_Power value="false" />
+    <vif:Num_Fixed_Batteries value="1" />
+    <vif:Num_Swappable_Battery_Slots value="0" />
+    <vif:ID_Header_Connector_Type_SOP value="2">USB Type-C® Receptacle</vif:ID_Header_Connector_Type_SOP>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Capabilities-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:USB_Comms_Capable value="true" />
+    <vif:DR_Swap_To_DFP_Supported value="true" />
+    <vif:DR_Swap_To_UFP_Supported value="false" />
+    <vif:VCONN_Swap_To_On_Supported value="true" />
+    <vif:VCONN_Swap_To_Off_Supported value="true" />
+    <vif:Responds_To_Discov_SOP_UFP value="false" />
+    <vif:Responds_To_Discov_SOP_DFP value="true" />
+    <vif:Attempts_Discov_SOP value="true" />
+    <vif:Power_Interruption_Available value="0">No Interruption Possible</vif:Power_Interruption_Available>
+    <vif:Data_Reset_Supported value="false" />
+    <vif:Enter_USB_Supported value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;USB Type-C®-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Type_C_Can_Act_As_Host value="true" />
+    <vif:Type_C_Can_Act_As_Device value="false" />
+    <vif:Type_C_Implements_Try_SRC value="true" />
+    <vif:Type_C_Implements_Try_SNK value="false" />
+    <vif:Type_C_Supports_Audio_Accessory value="false" />
+    <vif:Type_C_Is_VCONN_Powered_Accessory value="false" />
+    <vif:Type_C_Is_Debug_Target_SRC value="true" />
+    <vif:Type_C_Is_Debug_Target_SNK value="true" />
+    <vif:RP_Value value="1">1.5A</vif:RP_Value>
+    <vif:Type_C_Port_On_Hub value="false" />
+    <vif:Type_C_Power_Source value="2">Both</vif:Type_C_Power_Source>
+    <vif:Type_C_Sources_VCONN value="true" />
+    <vif:Type_C_Is_Alt_Mode_Controller value="true" />
+    <vif:Type_C_Is_Alt_Mode_Adapter value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Product Power-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Product_Total_Source_Power_mW value="15000">15000 mW</vif:Product_Total_Source_Power_mW>
+    <vif:Port_Source_Power_Type value="0">Assured</vif:Port_Source_Power_Type>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;USB Host-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Host_Supports_USB_Data value="true" />
+    <vif:Host_Speed value="1">USB 3.2 Gen 1x1</vif:Host_Speed>
+    <vif:Host_Contains_Captive_Retimer value="false" />
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:Host_Is_Embedded value="false" />
+    <vif:Host_Suspend_Supported value="true" />
+    <vif:Is_DFP_On_Hub value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Battery Charging 1.2-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:BC_1_2_Charging_Port_Type value="1">CDP</vif:BC_1_2_Charging_Port_Type>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Source-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Power_As_Source value="15000">15000 mW</vif:PD_Power_As_Source>
+    <vif:EPR_Supported_As_Src value="false" />
+    <vif:USB_Suspend_May_Be_Cleared value="false" />
+    <vif:Sends_Pings value="false" />
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="0">FR_Swap not supported</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <vif:Master_Port value="false" />
+    <vif:Num_Src_PDOs value="1" />
+    <vif:PD_OC_Protection value="true" />
+    <vif:PD_OCP_Method value="0">Over-Current Response</vif:PD_OCP_Method>
+    <!--Bundle: SrcPdoList-->
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!--Source PDO 1-->
+        <vif:Src_PDO_Supply_Type value="0">Fixed</vif:Src_PDO_Supply_Type>
+        <vif:Src_PDO_Peak_Current value="0">100% IOC</vif:Src_PDO_Peak_Current>
+        <vif:Src_PDO_Voltage value="100">5000 mV</vif:Src_PDO_Voltage>
+        <vif:Src_PDO_Max_Current value="300">3000 mA</vif:Src_PDO_Max_Current>
+        <vif:Src_PD_OCP_OC_Debounce value="0">0 msec</vif:Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="300">3000 mA</vif:Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Sink-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Power_As_Sink value="60000">60000 mW</vif:PD_Power_As_Sink>
+    <vif:EPR_Supported_As_Snk value="false" />
+    <vif:No_USB_Suspend_May_Be_Set value="true" />
+    <vif:GiveBack_May_Be_Set value="false" />
+    <vif:Higher_Capability_Set value="false" />
+    <vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source value="0">FR_Swap not supported</vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source>
+    <vif:Num_Snk_PDOs value="3" />
+    <!--Bundle: SnkPdoList-->
+    <vif:SnkPdoList>
+      <vif:SnkPDO>
+        <!--Sink PDO 1-->
+        <vif:Snk_PDO_Supply_Type value="0">Fixed</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Voltage value="100">5000 mV</vif:Snk_PDO_Voltage>
+        <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>
+      </vif:SnkPDO>
+      <vif:SnkPDO>
+        <!--Sink PDO 2-->
+        <vif:Snk_PDO_Supply_Type value="1">Battery</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Op_Power value="60">15000 mW</vif:Snk_PDO_Op_Power>
+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>
+        <vif:Snk_PDO_Max_Voltage value="400">20000 mV</vif:Snk_PDO_Max_Voltage>
+      </vif:SnkPDO>
+      <vif:SnkPDO>
+        <!--Sink PDO 3-->
+        <vif:Snk_PDO_Supply_Type value="2">Variable</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>
+        <vif:Snk_PDO_Max_Voltage value="400">20000 mV</vif:Snk_PDO_Max_Voltage>
+        <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>
+      </vif:SnkPDO>
+    </vif:SnkPdoList>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Dual Role-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Accepts_PR_Swap_As_Src value="true" />
+    <vif:Accepts_PR_Swap_As_Snk value="true" />
+    <vif:Requests_PR_Swap_As_Src value="true" />
+    <vif:Requests_PR_Swap_As_Snk value="true" />
+    <vif:FR_Swap_Supported_As_Initial_Sink value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;SOP Discover ID-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:XID_SOP value="0" />
+    <vif:Data_Capable_As_USB_Host_SOP value="true" />
+    <vif:Data_Capable_As_USB_Device_SOP value="false" />
+    <vif:Product_Type_UFP_SOP value="0">Undefined</vif:Product_Type_UFP_SOP>
+    <vif:Product_Type_DFP_SOP value="2">PDUSB Host</vif:Product_Type_DFP_SOP>
+    <vif:DFP_VDO_Port_Number value="0" />
+    <vif:Modal_Operation_Supported_SOP value="false" />
+    <vif:USB_VID_SOP value="6353">18D1</vif:USB_VID_SOP>
+    <vif:PID_SOP value="20570">505A</vif:PID_SOP>
+    <vif:bcdDevice_SOP value="0">0000</vif:bcdDevice_SOP>
+  </vif:Component>
+  <vif:Component>
+    <!--Component 1: Port 1-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Component-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Port_Label>1</vif:Port_Label>
+    <vif:Connector_Type value="2">Type-C®</vif:Connector_Type>
+    <vif:USB4_Supported value="false" />
+    <vif:USB_PD_Support value="true" />
+    <vif:PD_Port_Type value="4">DRP</vif:PD_Port_Type>
+    <vif:Type_C_State_Machine value="2">DRP</vif:Type_C_State_Machine>
+    <vif:Port_Battery_Powered value="true" />
+    <vif:BC_1_2_Support value="2">Charging Port</vif:BC_1_2_Support>
+    <vif:Captive_Cable value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;General PD-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Spec_Revision_Major value="3" />
+    <vif:PD_Spec_Revision_Minor value="1" />
+    <vif:PD_Spec_Version_Major value="1" />
+    <vif:PD_Spec_Version_Minor value="3" />
+    <vif:PD_Specification_Revision value="2">Revision 3</vif:PD_Specification_Revision>
+    <vif:SOP_Capable value="true" />
+    <vif:SOP_P_Capable value="true" />
+    <vif:SOP_PP_Capable value="true" />
+    <vif:SOP_P_Debug_Capable value="false" />
+    <vif:SOP_PP_Debug_Capable value="false" />
+    <vif:Manufacturer_Info_Supported_Port value="true" />
+    <vif:Manufacturer_Info_VID_Port value="6353">18D1</vif:Manufacturer_Info_VID_Port>
+    <vif:Manufacturer_Info_PID_Port value="20570">505A</vif:Manufacturer_Info_PID_Port>
+    <vif:Chunking_Implemented_SOP value="true" />
+    <vif:Unchunked_Extended_Messages_Supported value="false" />
+    <vif:Security_Msgs_Supported_SOP value="false" />
+    <vif:Unconstrained_Power value="false" />
+    <vif:Num_Fixed_Batteries value="1" />
+    <vif:Num_Swappable_Battery_Slots value="0" />
+    <vif:ID_Header_Connector_Type_SOP value="2">USB Type-C® Receptacle</vif:ID_Header_Connector_Type_SOP>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Capabilities-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:USB_Comms_Capable value="true" />
+    <vif:DR_Swap_To_DFP_Supported value="true" />
+    <vif:DR_Swap_To_UFP_Supported value="false" />
+    <vif:VCONN_Swap_To_On_Supported value="true" />
+    <vif:VCONN_Swap_To_Off_Supported value="true" />
+    <vif:Responds_To_Discov_SOP_UFP value="false" />
+    <vif:Responds_To_Discov_SOP_DFP value="true" />
+    <vif:Attempts_Discov_SOP value="true" />
+    <vif:Power_Interruption_Available value="0">No Interruption Possible</vif:Power_Interruption_Available>
+    <vif:Data_Reset_Supported value="false" />
+    <vif:Enter_USB_Supported value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;USB Type-C®-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Type_C_Can_Act_As_Host value="true" />
+    <vif:Type_C_Can_Act_As_Device value="false" />
+    <vif:Type_C_Implements_Try_SRC value="true" />
+    <vif:Type_C_Implements_Try_SNK value="false" />
+    <vif:Type_C_Supports_Audio_Accessory value="false" />
+    <vif:Type_C_Is_VCONN_Powered_Accessory value="false" />
+    <vif:Type_C_Is_Debug_Target_SRC value="true" />
+    <vif:Type_C_Is_Debug_Target_SNK value="true" />
+    <vif:RP_Value value="1">1.5A</vif:RP_Value>
+    <vif:Type_C_Port_On_Hub value="false" />
+    <vif:Type_C_Power_Source value="2">Both</vif:Type_C_Power_Source>
+    <vif:Type_C_Sources_VCONN value="true" />
+    <vif:Type_C_Is_Alt_Mode_Controller value="true" />
+    <vif:Type_C_Is_Alt_Mode_Adapter value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Product Power-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Product_Total_Source_Power_mW value="15000">15000 mW</vif:Product_Total_Source_Power_mW>
+    <vif:Port_Source_Power_Type value="0">Assured</vif:Port_Source_Power_Type>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;USB Host-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Host_Supports_USB_Data value="true" />
+    <vif:Host_Speed value="1">USB 3.2 Gen 1x1</vif:Host_Speed>
+    <vif:Host_Contains_Captive_Retimer value="true" />
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:Host_Is_Embedded value="false" />
+    <vif:Host_Suspend_Supported value="true" />
+    <vif:Is_DFP_On_Hub value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Battery Charging 1.2-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:BC_1_2_Charging_Port_Type value="1">CDP</vif:BC_1_2_Charging_Port_Type>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Source-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Power_As_Source value="15000">15000 mW</vif:PD_Power_As_Source>
+    <vif:EPR_Supported_As_Src value="false" />
+    <vif:USB_Suspend_May_Be_Cleared value="false" />
+    <vif:Sends_Pings value="false" />
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="0">FR_Swap not supported</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <vif:Master_Port value="false" />
+    <vif:Num_Src_PDOs value="1" />
+    <vif:PD_OC_Protection value="true" />
+    <vif:PD_OCP_Method value="0">Over-Current Response</vif:PD_OCP_Method>
+    <!--Bundle: SrcPdoList-->
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!--Source PDO 1-->
+        <vif:Src_PDO_Supply_Type value="0">Fixed</vif:Src_PDO_Supply_Type>
+        <vif:Src_PDO_Peak_Current value="0">100% IOC</vif:Src_PDO_Peak_Current>
+        <vif:Src_PDO_Voltage value="100">5000 mV</vif:Src_PDO_Voltage>
+        <vif:Src_PDO_Max_Current value="300">3000 mA</vif:Src_PDO_Max_Current>
+        <vif:Src_PD_OCP_OC_Debounce value="0">0 msec</vif:Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="300">3000 mA</vif:Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Sink-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Power_As_Sink value="60000">60000 mW</vif:PD_Power_As_Sink>
+    <vif:EPR_Supported_As_Snk value="false" />
+    <vif:No_USB_Suspend_May_Be_Set value="true" />
+    <vif:GiveBack_May_Be_Set value="false" />
+    <vif:Higher_Capability_Set value="false" />
+    <vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source value="0">FR_Swap not supported</vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source>
+    <vif:Num_Snk_PDOs value="3" />
+    <!--Bundle: SnkPdoList-->
+    <vif:SnkPdoList>
+      <vif:SnkPDO>
+        <!--Sink PDO 1-->
+        <vif:Snk_PDO_Supply_Type value="0">Fixed</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Voltage value="100">5000 mV</vif:Snk_PDO_Voltage>
+        <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>
+      </vif:SnkPDO>
+      <vif:SnkPDO>
+        <!--Sink PDO 2-->
+        <vif:Snk_PDO_Supply_Type value="1">Battery</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Op_Power value="60">15000 mW</vif:Snk_PDO_Op_Power>
+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>
+        <vif:Snk_PDO_Max_Voltage value="400">20000 mV</vif:Snk_PDO_Max_Voltage>
+      </vif:SnkPDO>
+      <vif:SnkPDO>
+        <!--Sink PDO 3-->
+        <vif:Snk_PDO_Supply_Type value="2">Variable</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>
+        <vif:Snk_PDO_Max_Voltage value="400">20000 mV</vif:Snk_PDO_Max_Voltage>
+        <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>
+      </vif:SnkPDO>
+    </vif:SnkPdoList>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Dual Role-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Accepts_PR_Swap_As_Src value="true" />
+    <vif:Accepts_PR_Swap_As_Snk value="true" />
+    <vif:Requests_PR_Swap_As_Src value="true" />
+    <vif:Requests_PR_Swap_As_Snk value="true" />
+    <vif:FR_Swap_Supported_As_Initial_Sink value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;SOP Discover ID-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:XID_SOP value="0" />
+    <vif:Data_Capable_As_USB_Host_SOP value="true" />
+    <vif:Data_Capable_As_USB_Device_SOP value="false" />
+    <vif:Product_Type_UFP_SOP value="0">Undefined</vif:Product_Type_UFP_SOP>
+    <vif:Product_Type_DFP_SOP value="2">PDUSB Host</vif:Product_Type_DFP_SOP>
+    <vif:DFP_VDO_Port_Number value="1" />
+    <vif:Modal_Operation_Supported_SOP value="false" />
+    <vif:USB_VID_SOP value="6353">18D1</vif:USB_VID_SOP>
+    <vif:PID_SOP value="20570">505A</vif:PID_SOP>
+    <vif:bcdDevice_SOP value="0">0000</vif:bcdDevice_SOP>
+  </vif:Component>
+</vif:VIF>
\ No newline at end of file
diff --git a/zephyr/program/nissa/pujjo/src/charger.c b/zephyr/program/nissa/pujjo/src/charger.c
new file mode 100644
index 0000000000..97aedd75ed
--- /dev/null
+++ b/zephyr/program/nissa/pujjo/src/charger.c
@@ -0,0 +1,63 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "charger.h"
+#include "charger/isl923x_public.h"
+#include "console.h"
+#include "driver/charger/isl923x.h"
+#include "driver/tcpm/raa489000.h"
+#include "extpower.h"
+#include "hooks.h"
+#include "usb_pd.h"
+
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+int extpower_is_present(void)
+{
+	int port;
+	int rv;
+	bool acok;
+
+	for (port = 0; port < board_get_usb_pd_port_count(); port++) {
+		rv = raa489000_is_acok(port, &acok);
+		if ((rv == EC_SUCCESS) && acok)
+			return 1;
+	}
+
+	return 0;
+}
+
+/*
+ * Pujjo does not have a GPIO indicating whether extpower is present,
+ * so detect using the charger(s).
+ */
+__override void board_check_extpower(void)
+{
+	static int last_extpower_present;
+	int extpower_present = extpower_is_present();
+
+	if (last_extpower_present ^ extpower_present)
+		extpower_handle_update(extpower_present);
+
+	last_extpower_present = extpower_present;
+}
+
+__override void board_hibernate(void)
+{
+	/* Shut down the chargers */
+	raa489000_hibernate(0, true);
+	LOG_INF("Charger(s) hibernated");
+	cflush();
+}
+
+static void charger_prochot_init(void)
+{
+	isl923x_set_ac_prochot(CHARGER_SOLO, 3500);
+	isl923x_set_dc_prochot(CHARGER_SOLO, 6528);
+}
+DECLARE_HOOK(HOOK_INIT, charger_prochot_init, HOOK_PRIO_POST_FIRST);
diff --git a/zephyr/program/nissa/pujjo/src/fan.c b/zephyr/program/nissa/pujjo/src/fan.c
new file mode 100644
index 0000000000..d42828fe9c
--- /dev/null
+++ b/zephyr/program/nissa/pujjo/src/fan.c
@@ -0,0 +1,41 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cros_cbi.h"
+#include "fan.h"
+#include "gpio/gpio.h"
+#include "hooks.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+/*
+ * Pujjo fan support
+ */
+static void fan_init(void)
+{
+	int ret;
+	uint32_t val;
+	/*
+	 * Retrieve the fan config.
+	 */
+	ret = cros_cbi_get_fw_config(FW_FAN, &val);
+	if (ret != 0) {
+		LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_FAN);
+		return;
+	}
+	if (val != FW_FAN_PRESENT) {
+		/* Disable the fan */
+		fan_set_count(0);
+	} else {
+		/* Configure the fan enable GPIO */
+		gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_fan_enable),
+				      GPIO_OUTPUT);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, fan_init, HOOK_PRIO_POST_FIRST);
diff --git a/zephyr/program/nissa/pujjo/src/form_factor.c b/zephyr/program/nissa/pujjo/src/form_factor.c
new file mode 100644
index 0000000000..2c447cba74
--- /dev/null
+++ b/zephyr/program/nissa/pujjo/src/form_factor.c
@@ -0,0 +1,77 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "accelgyro.h"
+#include "button.h"
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+#include "driver/accel_bma4xx.h"
+#include "driver/accel_lis2dw12_public.h"
+#include "driver/accelgyro_bmi323.h"
+#include "driver/accelgyro_lsm6dsm.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "motion_sense.h"
+#include "motionsense_sensors.h"
+#include "tablet_mode.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+static bool use_alt_sensor;
+static bool use_alt_lid_accel;
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	if (use_alt_sensor)
+		lsm6dsm_interrupt(signal);
+	else
+		bmi3xx_interrupt(signal);
+}
+
+void lid_accel_interrupt(enum gpio_signal signal)
+{
+	if (use_alt_lid_accel)
+		lis2dw12_interrupt(signal);
+	else
+		bma4xx_interrupt(signal);
+}
+
+static void sensor_init(void)
+{
+	int ret;
+	uint32_t val;
+	/* check which sensors are installed */
+	use_alt_sensor = cros_cbi_ssfc_check_match(
+		CBI_SSFC_VALUE_ID(DT_NODELABEL(base_sensor_1)));
+	use_alt_lid_accel = cros_cbi_ssfc_check_match(
+		CBI_SSFC_VALUE_ID(DT_NODELABEL(lid_sensor_1)));
+
+	motion_sensors_check_ssfc();
+
+	/* Check if it's tablet or not */
+	ret = cros_cbi_get_fw_config(FW_TABLET, &val);
+	if (ret != 0) {
+		LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_TABLET);
+		return;
+	}
+	if (val == FW_TABLET_NOT_PRESENT) {
+		LOG_INF("Clamshell: disable motionsense function.");
+		motion_sensor_count = 0;
+		gmr_tablet_switch_disable();
+		gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_imu));
+		gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_imu_int_l),
+				      GPIO_DISCONNECTED);
+
+		LOG_INF("Clamshell: disable volume button function.");
+		button_disable_gpio(BUTTON_VOLUME_UP);
+		button_disable_gpio(BUTTON_VOLUME_DOWN);
+	} else {
+		LOG_INF("Tablet: Enable motionsense function.");
+	}
+}
+DECLARE_HOOK(HOOK_INIT, sensor_init, HOOK_PRIO_POST_I2C);
diff --git a/zephyr/program/nissa/pujjo/src/hdmi.c b/zephyr/program/nissa/pujjo/src/hdmi.c
new file mode 100644
index 0000000000..9461e7c53e
--- /dev/null
+++ b/zephyr/program/nissa/pujjo/src/hdmi.c
@@ -0,0 +1,12 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "nissa_hdmi.h"
+
+__override void nissa_configure_hdmi_power_gpios(void)
+{
+	/* Pujjo needs to drive VCC enable but not core rails */
+	nissa_configure_hdmi_vcc();
+}
diff --git a/zephyr/program/nissa/pujjo/src/keyboard.c b/zephyr/program/nissa/pujjo/src/keyboard.c
new file mode 100644
index 0000000000..1587030080
--- /dev/null
+++ b/zephyr/program/nissa/pujjo/src/keyboard.c
@@ -0,0 +1,29 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+
+static const struct ec_response_keybd_config pujjo_kb = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_BRIGHTNESS_DOWN,	/* T5 */
+		TK_BRIGHTNESS_UP,	/* T6 */
+		TK_MICMUTE,		/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &pujjo_kb;
+}
diff --git a/zephyr/program/nissa/pujjo/src/led.c b/zephyr/program/nissa/pujjo/src/led.c
new file mode 100644
index 0000000000..4d859f2764
--- /dev/null
+++ b/zephyr/program/nissa/pujjo/src/led.c
@@ -0,0 +1,134 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Pujjo specific PWM LED settings: there are 2 LEDs on each side of the board,
+ * each one can be controlled separately. The LED colors are white or amber,
+ * and the default behavior is tied to the charging process: both sides are
+ * amber while charging the battery and white when the battery is charged.
+ */
+
+#include "common.h"
+#include "gpio.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
+
+__override const int led_charge_lvl_1 = 5;
+
+__override const int led_charge_lvl_2 = 97;
+
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
+
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 3 * LED_ONE_SEC },
+					       { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    3 * LED_ONE_SEC },
+						  { LED_OFF,
+						    0.5 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_power(enum ec_led_colors color)
+{
+	if (color == EC_LED_COLOR_WHITE)
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_power_led),
+				LED_ON_LVL);
+	else
+		/* LED_OFF and unsupported colors */
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_power_led),
+				LED_OFF_LVL);
+}
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_AMBER:
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_led_1_odl),
+				LED_ON_LVL);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_led_2_odl),
+				LED_ON_LVL);
+		break;
+	case EC_LED_COLOR_RED:
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_led_1_odl),
+				LED_ON_LVL);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_led_2_odl),
+				LED_OFF_LVL);
+		break;
+	case EC_LED_COLOR_GREEN:
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_led_1_odl),
+				LED_OFF_LVL);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_led_2_odl),
+				LED_ON_LVL);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_led_1_odl),
+				LED_OFF_LVL);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_led_2_odl),
+				LED_OFF_LVL);
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_RED] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		brightness_range[EC_LED_COLOR_GREEN] = 1;
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		if (brightness[EC_LED_COLOR_RED] != 0)
+			led_set_color_battery(EC_LED_COLOR_RED);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(EC_LED_COLOR_AMBER);
+		else if (brightness[EC_LED_COLOR_GREEN] != 0)
+			led_set_color_battery(EC_LED_COLOR_GREEN);
+		else
+			led_set_color_battery(LED_OFF);
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_power(EC_LED_COLOR_WHITE);
+		else
+			led_set_color_power(LED_OFF);
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/zephyr/program/nissa/pujjo/src/usbc.c b/zephyr/program/nissa/pujjo/src/usbc.c
new file mode 100644
index 0000000000..0b5fe3b809
--- /dev/null
+++ b/zephyr/program/nissa/pujjo/src/usbc.c
@@ -0,0 +1,209 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_state.h"
+#include "chipset.h"
+#include "driver/charger/isl923x_public.h"
+#include "driver/retimer/anx7483_public.h"
+#include "driver/tcpm/raa489000.h"
+#include "driver/tcpm/tcpci.h"
+#include "hooks.h"
+#include "system.h"
+#include "usb_mux.h"
+
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+int board_is_sourcing_vbus(int port)
+{
+	int regval;
+
+	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
+	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int i;
+	int old_port;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	old_port = charge_manager_get_active_charge_port();
+
+	LOG_INF("New chg p%d", port);
+
+	/* Disable all ports. */
+	if (port == CHARGE_PORT_NONE) {
+		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+			tcpc_write(i, TCPC_REG_COMMAND,
+				   TCPC_REG_COMMAND_SNK_CTRL_LOW);
+			raa489000_enable_asgate(i, false);
+		}
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if port is sourcing VBUS. */
+	if (board_is_sourcing_vbus(port)) {
+		LOG_WRN("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		if (i == port)
+			continue;
+
+		if (tcpc_write(i, TCPC_REG_COMMAND,
+			       TCPC_REG_COMMAND_SNK_CTRL_LOW))
+			LOG_WRN("p%d: sink path disable failed.", i);
+		raa489000_enable_asgate(i, false);
+	}
+
+	/*
+	 * Stop the charger IC from switching while changing ports.  Otherwise,
+	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
+	 */
+	if (old_port != CHARGE_PORT_NONE)
+		charger_discharge_on_ac(1);
+
+	/* Enable requested charge port. */
+	if (raa489000_enable_asgate(port, true) ||
+	    tcpc_write(port, TCPC_REG_COMMAND,
+		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
+		LOG_WRN("p%d: sink path enable failed.", port);
+		charger_discharge_on_ac(0);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	/* Allow the charger IC to begin/continue switching. */
+	charger_discharge_on_ac(0);
+
+	return EC_SUCCESS;
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+	int regval;
+
+	/*
+	 * The interrupt line is shared between the TCPC and BC1.2 detector IC.
+	 * Therefore, go out and actually read the alert registers to report the
+	 * alert status.
+	 */
+	if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl))) {
+		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
+			/* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */
+			if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0))
+				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
+
+			if (regval)
+				status |= PD_STATUS_TCPC_ALERT_0;
+		}
+	}
+	return status;
+}
+
+void pd_power_supply_reset(int port)
+{
+	/* Disable VBUS */
+	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	if (port < 0 || port >= CONFIG_USB_PD_PORT_MAX_COUNT)
+		return;
+
+	raa489000_set_output_current(port, rp);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	if (port >= CONFIG_USB_PD_PORT_MAX_COUNT)
+		return EC_ERROR_INVAL;
+
+	/* Disable charging. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
+	if (rv)
+		return rv;
+
+	/* Our policy is not to source VBUS when the AP is off. */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	/* Provide Vbus. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
+	if (rv)
+		return rv;
+
+	rv = raa489000_enable_asgate(port, true);
+	if (rv)
+		return rv;
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * TODO(b:147316511): could send a reset command to the TCPC here
+	 * if needed.
+	 */
+}
+
+/*
+ * Because the TCPCs and BC1.2 chips share interrupt lines, it's possible
+ * for an interrupt to be lost if one asserts the IRQ, the other does the same
+ * then the first releases it: there will only be one falling edge to trigger
+ * the interrupt, and the line will be held low. We handle this by polling the
+ * IRQ GPIO on the USB-PD task after processing TCPC interrupts, synchronously
+ * running the BC1.2 interrupt handler to ensure we continue processing
+ * interrupts as long as either source is asserting the IRQ.
+ */
+void board_process_pd_alert(int port)
+{
+	const struct gpio_dt_spec *gpio =
+		GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl);
+
+	if (port != 0)
+		return;
+
+	if (!gpio_pin_get_dt(gpio)) {
+		usb_charger_task_set_event_sync(port, USB_CHG_EVENT_BC12);
+	}
+
+	/*
+	 * Immediately schedule another TCPC interrupt if it seems we haven't
+	 * cleared all pending interrupts.
+	 */
+	if (!gpio_pin_get_dt(gpio))
+		schedule_deferred_pd_interrupt(port);
+}
+
+void usb_interrupt(enum gpio_signal signal)
+{
+	if (signal != GPIO_SIGNAL(DT_NODELABEL(gpio_usb_c0_int_odl)))
+		return;
+
+	/* Trigger polling of TCPC and BC1.2 in USB-PD task */
+	schedule_deferred_pd_interrupt(0);
+}
diff --git a/zephyr/program/nissa/shi.dtsi b/zephyr/program/nissa/shi.dtsi
new file mode 100644
index 0000000000..1a21a3ffb8
--- /dev/null
+++ b/zephyr/program/nissa/shi.dtsi
@@ -0,0 +1,15 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <ite/it8xxx2-pinctrl-map.dtsi>
+
+&shi0 {
+	status = "okay";
+	pinctrl-0 = <&shi_mosi_gpm0_default &shi_miso_gpm1_default
+		     &shi_clk_gpm4_default &shi_cs_gpm5_default>;
+	pinctrl-names = "default";
+	/* unused but needed by dt binding */
+	cs-gpios = <&gpiom 5 GPIO_VOLTAGE_1P8>;
+};
diff --git a/zephyr/program/nissa/src/board_power.c b/zephyr/program/nissa/src/board_power.c
new file mode 100644
index 0000000000..380e9d8e49
--- /dev/null
+++ b/zephyr/program/nissa/src/board_power.c
@@ -0,0 +1,171 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "gpio/gpio.h"
+#include "gpio_signal.h"
+#include "system_boot_time.h"
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/atomic.h>
+
+#include <ap_power/ap_power.h>
+#include <ap_power/ap_power_events.h>
+#include <ap_power/ap_power_interface.h>
+#include <ap_power_override_functions.h>
+#include <power_signals.h>
+#include <x86_power_signals.h>
+
+LOG_MODULE_DECLARE(ap_pwrseq, LOG_LEVEL_INF);
+
+#define X86_NON_DSX_ADLP_NONPWRSEQ_FORCE_SHUTDOWN_TO_MS 5
+
+static bool s0_stable;
+
+static void generate_ec_soc_dsw_pwrok_handler(int delay)
+{
+	int in_sig_val = power_signal_get(PWR_DSW_PWROK);
+
+	if (in_sig_val != power_signal_get(PWR_EC_SOC_DSW_PWROK)) {
+		if (in_sig_val)
+			k_msleep(delay);
+		power_signal_set(PWR_EC_SOC_DSW_PWROK, 1);
+	}
+}
+
+void board_ap_power_force_shutdown(void)
+{
+	int timeout_ms = X86_NON_DSX_ADLP_NONPWRSEQ_FORCE_SHUTDOWN_TO_MS;
+
+	if (s0_stable) {
+		/* Enable these power signals in case of sudden shutdown */
+		power_signal_enable(PWR_DSW_PWROK);
+		power_signal_enable(PWR_PG_PP1P05);
+	}
+
+	power_signal_set(PWR_EC_SOC_DSW_PWROK, 0);
+	power_signal_set(PWR_EC_PCH_RSMRST, 0);
+
+	while (power_signal_get(PWR_RSMRST) == 0 &&
+	       power_signal_get(PWR_SLP_SUS) == 0 && timeout_ms > 0) {
+		k_msleep(1);
+		timeout_ms--;
+	}
+	if (power_signal_get(PWR_SLP_SUS) == 0) {
+		LOG_WRN("SLP_SUS is not deasserted! Assuming G3");
+	}
+
+	if (power_signal_get(PWR_RSMRST) == 1) {
+		LOG_WRN("RSMRST is not deasserted! Assuming G3");
+	}
+
+	power_signal_set(PWR_EN_PP3300_A, 0);
+
+	power_signal_set(PWR_EN_PP5000_A, 0);
+
+	timeout_ms = X86_NON_DSX_ADLP_NONPWRSEQ_FORCE_SHUTDOWN_TO_MS;
+	while (power_signal_get(PWR_DSW_PWROK) && timeout_ms > 0) {
+		k_msleep(1);
+		timeout_ms--;
+	};
+
+	if (power_signal_get(PWR_DSW_PWROK))
+		LOG_WRN("DSW_PWROK didn't go low!  Assuming G3.");
+
+	power_signal_disable(PWR_DSW_PWROK);
+	power_signal_disable(PWR_PG_PP1P05);
+	s0_stable = false;
+}
+
+void board_ap_power_action_g3_s5(void)
+{
+	power_signal_enable(PWR_DSW_PWROK);
+	power_signal_enable(PWR_PG_PP1P05);
+
+	LOG_DBG("Turning on PWR_EN_PP5000_A and PWR_EN_PP3300_A");
+	power_signal_set(PWR_EN_PP5000_A, 1);
+	power_signal_set(PWR_EN_PP3300_A, 1);
+
+	update_ap_boot_time(ARAIL);
+	power_wait_signals_timeout(IN_PGOOD_ALL_CORE,
+				   AP_PWRSEQ_DT_VALUE(wait_signal_timeout));
+
+	generate_ec_soc_dsw_pwrok_handler(AP_PWRSEQ_DT_VALUE(dsw_pwrok_delay));
+	s0_stable = false;
+}
+
+void board_ap_power_action_s3_s0(void)
+{
+	s0_stable = false;
+}
+
+void board_ap_power_action_s0_s3(void)
+{
+	power_signal_enable(PWR_DSW_PWROK);
+	power_signal_enable(PWR_PG_PP1P05);
+	s0_stable = false;
+}
+
+void board_ap_power_action_s0(void)
+{
+	if (s0_stable) {
+		return;
+	}
+	LOG_INF("Reaching S0");
+	power_signal_disable(PWR_DSW_PWROK);
+	power_signal_disable(PWR_PG_PP1P05);
+	s0_stable = true;
+}
+
+int board_ap_power_assert_pch_power_ok(void)
+{
+	/* Pass though PCH_PWROK */
+	if (power_signal_get(PWR_PCH_PWROK) == 0) {
+		k_msleep(AP_PWRSEQ_DT_VALUE(pch_pwrok_delay));
+		power_signal_set(PWR_PCH_PWROK, 1);
+	}
+
+	return 0;
+}
+
+bool board_ap_power_check_power_rails_enabled(void)
+{
+	return power_signal_get(PWR_EN_PP3300_A) &&
+	       power_signal_get(PWR_EN_PP5000_A) &&
+	       power_signal_get(PWR_EC_SOC_DSW_PWROK);
+}
+
+int board_power_signal_get(enum power_signal signal)
+{
+	switch (signal) {
+	default:
+		LOG_ERR("Unknown signal for board get: %d", signal);
+		return -EINVAL;
+
+	case PWR_ALL_SYS_PWRGD:
+		/*
+		 * All system power is good.
+		 * Checks that PWR_SLP_S3 is off, and
+		 * the GPIO signal for all power good is set,
+		 * and that the 1.05 volt line is ready.
+		 */
+		if (power_signal_get(PWR_SLP_S3)) {
+			return 0;
+		}
+		if (!gpio_pin_get_dt(
+			    GPIO_DT_FROM_NODELABEL(gpio_all_sys_pwrgd))) {
+			return 0;
+		}
+		if (!power_signal_get(PWR_PG_PP1P05)) {
+			return 0;
+		}
+		return 1;
+	}
+}
+
+int board_power_signal_set(enum power_signal signal, int value)
+{
+	return -EINVAL;
+}
diff --git a/zephyr/program/nissa/src/common.c b/zephyr/program/nissa/src/common.c
new file mode 100644
index 0000000000..26a6cf272c
--- /dev/null
+++ b/zephyr/program/nissa/src/common.c
@@ -0,0 +1,145 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "chipset.h"
+#include "hooks.h"
+#include "nissa_common.h"
+#include "system.h"
+#include "usb_mux.h"
+
+#include <zephyr/device.h>
+#include <zephyr/logging/log.h>
+
+#include <ap_power/ap_power.h>
+LOG_MODULE_REGISTER(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+__overridable void board_power_change(struct ap_power_ev_callback *cb,
+				      struct ap_power_ev_data data)
+{
+	/*
+	 * Enable power to pen garage when system is active (safe even if no
+	 * pen is present).
+	 */
+	const struct gpio_dt_spec *const pen_power_gpio =
+		GPIO_DT_FROM_NODELABEL(gpio_en_pp5000_pen_x);
+
+	switch (data.event) {
+	case AP_POWER_STARTUP:
+		gpio_pin_set_dt(pen_power_gpio, 1);
+		break;
+	case AP_POWER_SHUTDOWN:
+		gpio_pin_set_dt(pen_power_gpio, 0);
+		break;
+	default:
+		break;
+	}
+}
+
+static void board_setup_init(void)
+{
+	static struct ap_power_ev_callback cb;
+
+	ap_power_ev_init_callback(&cb, board_power_change,
+				  AP_POWER_STARTUP | AP_POWER_SHUTDOWN);
+	ap_power_ev_add_callback(&cb);
+}
+DECLARE_HOOK(HOOK_INIT, board_setup_init, HOOK_PRIO_INIT_I2C);
+
+int pd_check_vconn_swap(int port)
+{
+	/* Do not allow vconn swap if 5V rail is off. */
+	const struct gpio_dt_spec *const ec_soc_dsw_pwrok_gpio =
+		GPIO_DT_FROM_NODELABEL(gpio_ec_soc_dsw_pwrok);
+
+	return gpio_pin_get_dt(ec_soc_dsw_pwrok_gpio);
+}
+
+/*
+ * Count of chargers depends on sub board presence.
+ */
+__override uint8_t board_get_charger_chip_count(void)
+{
+	return board_get_usb_pd_port_count();
+}
+
+__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+				       int *ki_div, int *kd, int *kd_div)
+{
+	*kp = 1;
+	*kp_div = 32;
+	*ki = 0;
+	*ki_div = 1;
+	*kd = 0;
+	*kd_div = 1;
+}
+
+#ifdef CONFIG_PLATFORM_EC_CHARGER_SM5803
+
+static int battery_cells;
+
+test_export_static void board_get_battery_cells(void)
+{
+	if (charger_get_battery_cells(CHARGER_PRIMARY, &battery_cells) ==
+	    EC_SUCCESS) {
+		LOG_INF("battery_cells:%d", battery_cells);
+	} else {
+		LOG_ERR("Failed to get default battery type");
+	}
+}
+DECLARE_HOOK(HOOK_INIT, board_get_battery_cells, HOOK_PRIO_DEFAULT);
+
+/*
+ * Called by USB-PD code to determine whether a given input voltage is
+ * acceptable.
+ */
+__override int pd_is_valid_input_voltage(int mv)
+{
+	/*
+	 * SM5803 is extremely inefficient in buck-boost mode, when
+	 * VBUS ~= VSYS: very high temperatures on the chip and associated
+	 * inductor have been observed when sinking normal charge current in
+	 * buck-boost mode (but not in buck or boost mode) so we choose to
+	 * completely exclude some voltages that are likely to be problematic.
+	 *
+	 * Nissa devices use either 2S or 3S batteries, for which VBUS will
+	 * usually only be near VSYS with a 3S battery and 12V input (picked
+	 * from among common supported PD voltages)- 2S can get close to
+	 * 9V, but we expect charge current to be low when a 2S battery is
+	 * charged to that voltage (because it will be nearly full).
+	 *
+	 * We assume that any battery with a design 3S, and
+	 * that other problematic PD voltages (near to, but not exactly 12V)
+	 * will rarely occur.
+	 */
+	if (battery_cells == 3 && mv == 12000) {
+		return false;
+	}
+	return true;
+}
+#endif
+
+/* Trigger shutdown by enabling the Z-sleep circuit */
+__override void board_hibernate_late(void)
+{
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_en_slp_z), 1);
+	/*
+	 * The system should hibernate, but there may be
+	 * a small delay, so return.
+	 */
+}
+
+#ifdef CONFIG_OCPC
+__override void board_ocpc_init(struct ocpc_data *ocpc)
+{
+	/* Ensure board has at least 2 charger chips. */
+	if (board_get_charger_chip_count() > 1) {
+		/* There's no provision to measure Isys */
+		ocpc->chg_flags[CHARGER_SECONDARY] |= OCPC_NO_ISYS_MEAS_CAP;
+	}
+}
+#endif
diff --git a/zephyr/program/nissa/src/led.c b/zephyr/program/nissa/src/led.c
new file mode 100644
index 0000000000..2617d0092d
--- /dev/null
+++ b/zephyr/program/nissa/src/led.c
@@ -0,0 +1,52 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery LED control for nissa
+ */
+#include "common.h"
+#include "ec_commands.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+#include "led_pwm.h"
+
+__override const int led_charge_lvl_1 = 5;
+__override const int led_charge_lvl_2 = 97;
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_RED:
+		set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_RED);
+		break;
+	case EC_LED_COLOR_GREEN:
+		set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_GREEN);
+		break;
+	case EC_LED_COLOR_AMBER:
+		set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_AMBER);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		set_pwm_led_color(EC_LED_ID_BATTERY_LED, -1);
+		break;
+	}
+}
diff --git a/zephyr/program/nissa/src/sub_board.c b/zephyr/program/nissa/src/sub_board.c
new file mode 100644
index 0000000000..db6788de96
--- /dev/null
+++ b/zephyr/program/nissa/src/sub_board.c
@@ -0,0 +1,370 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Nissa sub-board hardware configuration */
+
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+#include "driver/tcpm/tcpci.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "nissa_hdmi.h"
+#include "nissa_sub_board.h"
+#include "task.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usbc/usb_muxes.h"
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/sys/printk.h>
+
+#include <ap_power/ap_power.h>
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+static uint8_t cached_usb_pd_port_count;
+
+__override uint8_t board_get_usb_pd_port_count(void)
+{
+	__ASSERT(cached_usb_pd_port_count != 0,
+		 "sub-board detection did not run before a port count request");
+	if (cached_usb_pd_port_count == 0)
+		LOG_WRN("USB PD Port count not initialized!");
+	return cached_usb_pd_port_count;
+}
+
+test_export_static enum nissa_sub_board_type nissa_cached_sub_board =
+	NISSA_SB_UNKNOWN;
+/*
+ * Retrieve sub-board type from FW_CONFIG.
+ */
+enum nissa_sub_board_type nissa_get_sb_type(void)
+{
+	int ret;
+	uint32_t val;
+
+	/*
+	 * Return cached value.
+	 */
+	if (nissa_cached_sub_board != NISSA_SB_UNKNOWN)
+		return nissa_cached_sub_board;
+
+	nissa_cached_sub_board = NISSA_SB_NONE; /* Defaults to none */
+	ret = cros_cbi_get_fw_config(FW_SUB_BOARD, &val);
+	if (ret != 0) {
+		LOG_WRN("Error retrieving CBI FW_CONFIG field %d",
+			FW_SUB_BOARD);
+		return nissa_cached_sub_board;
+	}
+	switch (val) {
+	default:
+		LOG_WRN("No sub-board defined");
+		break;
+	case FW_SUB_BOARD_1:
+		nissa_cached_sub_board = NISSA_SB_C_A;
+		LOG_INF("SB: USB type C, USB type A");
+		break;
+
+	case FW_SUB_BOARD_2:
+		nissa_cached_sub_board = NISSA_SB_C_LTE;
+		LOG_INF("SB: USB type C, WWAN LTE");
+		break;
+
+	case FW_SUB_BOARD_3:
+		nissa_cached_sub_board = NISSA_SB_HDMI_A;
+		LOG_INF("SB: HDMI, USB type A");
+		break;
+	}
+	return nissa_cached_sub_board;
+}
+
+/*
+ * Initialise the USB PD port count, which
+ * depends on which sub-board is attached.
+ */
+test_export_static void board_usb_pd_count_init(void)
+{
+	switch (nissa_get_sb_type()) {
+	default:
+		cached_usb_pd_port_count = 1;
+		break;
+
+	case NISSA_SB_C_A:
+	case NISSA_SB_C_LTE:
+		cached_usb_pd_port_count = 2;
+		break;
+	}
+}
+/*
+ * Make sure setup is done after EEPROM is readable.
+ */
+DECLARE_HOOK(HOOK_INIT, board_usb_pd_count_init, HOOK_PRIO_INIT_I2C);
+
+#if NISSA_BOARD_HAS_HDMI_SUPPORT
+static void hdmi_power_handler(struct ap_power_ev_callback *cb,
+			       struct ap_power_ev_data data)
+{
+	/* Enable VCC on the HDMI port. */
+	const struct gpio_dt_spec *s3_rail =
+		GPIO_DT_FROM_ALIAS(gpio_hdmi_en_odl);
+	/* Connect AP's DDC to sub-board (default is USB-C aux) */
+	const struct gpio_dt_spec *ddc_select =
+		GPIO_DT_FROM_NODELABEL(gpio_hdmi_sel);
+
+	switch (data.event) {
+	case AP_POWER_PRE_INIT:
+		LOG_DBG("Connecting HDMI DDC to sub-board");
+		gpio_pin_set_dt(ddc_select, 1);
+		break;
+	case AP_POWER_STARTUP:
+		LOG_DBG("Enabling HDMI VCC");
+		gpio_pin_set_dt(s3_rail, 1);
+		break;
+	case AP_POWER_SHUTDOWN:
+		LOG_DBG("Disabling HDMI VCC");
+		gpio_pin_set_dt(s3_rail, 0);
+		break;
+	case AP_POWER_HARD_OFF:
+		LOG_DBG("Disconnecting HDMI sub-board DDC");
+		gpio_pin_set_dt(ddc_select, 0);
+		break;
+	default:
+		LOG_ERR("Unhandled HDMI power event %d", data.event);
+		break;
+	}
+}
+
+static void hdmi_hpd_interrupt(const struct device *device,
+			       struct gpio_callback *callback,
+			       gpio_port_pins_t pins)
+{
+	int state = gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_hpd_odl));
+
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_soc_hdmi_hpd), state);
+	LOG_DBG("HDMI HPD changed state to %d", state);
+}
+
+void nissa_configure_hdmi_rails(void)
+{
+#if DT_NODE_EXISTS(GPIO_DT_FROM_ALIAS(gpio_en_rails_odl))
+	gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_en_rails_odl),
+			      GPIO_OUTPUT_INACTIVE | GPIO_OPEN_DRAIN |
+				      GPIO_PULL_UP | GPIO_ACTIVE_LOW);
+#endif
+}
+
+void nissa_configure_hdmi_vcc(void)
+{
+	gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_hdmi_en_odl),
+			      GPIO_OUTPUT_INACTIVE | GPIO_OPEN_DRAIN |
+				      GPIO_ACTIVE_LOW);
+}
+
+__overridable void nissa_configure_hdmi_power_gpios(void)
+{
+	nissa_configure_hdmi_rails();
+}
+
+#ifdef CONFIG_SOC_IT8XXX2
+/*
+ * On it8xxx2, the below condition will break the EC to enter deep doze mode
+ * (b:237717730):
+ * Enhance i2c (GPE0/E7, GPH1/GPH2 or GPA4/GPA5) is enabled and its clock and
+ * data pins aren't both at high level.
+ *
+ * Since HDMI+type A SKU doesn't use i2c4, disable it for better power number.
+ */
+#define I2C4_NODE DT_NODELABEL(i2c4)
+#if DT_NODE_EXISTS(I2C4_NODE)
+#include <zephyr/drivers/pinctrl.h>
+PINCTRL_DT_DEFINE(I2C4_NODE);
+
+/* disable i2c4 alternate function  */
+static void soc_it8xxx2_disable_i2c4_alt(void)
+{
+	const struct pinctrl_dev_config *pcfg =
+		PINCTRL_DT_DEV_CONFIG_GET(I2C4_NODE);
+
+	pinctrl_apply_state(pcfg, PINCTRL_STATE_SLEEP);
+}
+#endif /* DT_NODE_EXISTS(I2C4_NODE) */
+#endif /* CONFIG_SOC_IT8XXX2 */
+#endif /* NISSA_BOARD_HAS_HDMI_SUPPORT */
+
+static void lte_power_handler(struct ap_power_ev_callback *cb,
+			      struct ap_power_ev_data data)
+{
+	/* Enable rails for S5 */
+	const struct gpio_dt_spec *s5_rail =
+		GPIO_DT_FROM_ALIAS(gpio_en_sub_s5_rails);
+	switch (data.event) {
+	case AP_POWER_PRE_INIT:
+		LOG_DBG("Enabling LTE sub-board power rails");
+		gpio_pin_set_dt(s5_rail, 1);
+		break;
+	case AP_POWER_HARD_OFF:
+		LOG_DBG("Disabling LTE sub-board power rails");
+		gpio_pin_set_dt(s5_rail, 0);
+		break;
+	default:
+		LOG_ERR("Unhandled LTE power event %d", data.event);
+		break;
+	}
+}
+
+/**
+ * Configure GPIOs (and other pin functions) that vary with present sub-board.
+ *
+ * The functions of some pins vary according to which sub-board is present
+ * (indicated by CBI fw_config); this function configures them according to the
+ * needs of the present sub-board.
+ */
+static void nereid_subboard_config(void)
+{
+	enum nissa_sub_board_type sb = nissa_get_sb_type();
+	static struct ap_power_ev_callback power_cb;
+
+#if USB_PORT_ENABLE_COUNT > 1
+	BUILD_ASSERT(USB_PORT_ENABLE_COUNT == 2,
+		     "Nissa assumes no more than 2 USB-A ports");
+	/*
+	 * USB-A port: current limit output is configured by default and unused
+	 * if this port is not present. VBUS enable must be configured if
+	 * needed and is controlled by the usba-port-enable-pins driver.
+	 */
+	if (sb == NISSA_SB_C_A || sb == NISSA_SB_HDMI_A ||
+	    sb == NISSA_SB_NONE) {
+		/*
+		 * Configure VBUS enable, retaining current value.
+		 * SB_NONE indicates missing fw_config; it's safe to enable VBUS
+		 * control in this case since all that will happen is we turn
+		 * off power to LTE, and it's useful to allow USB-A to work in
+		 * such a configuration.
+		 */
+		gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_en_usb_a1_vbus),
+				      GPIO_OUTPUT);
+	} else {
+		/* Turn off unused pins */
+		gpio_pin_configure_dt(
+			GPIO_DT_FROM_NODELABEL(gpio_sub_usb_a1_ilimit_sdp),
+			GPIO_DISCONNECTED);
+		gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_en_usb_a1_vbus),
+				      GPIO_DISCONNECTED);
+		/* Disable second USB-A port enable GPIO */
+		usb_port_enable[1] = -1;
+	}
+#endif
+	/*
+	 * USB-C port: the default configuration has I2C on the I2C pins,
+	 * but the interrupt line needs to be configured.
+	 */
+#if CONFIG_USB_PD_PORT_MAX_COUNT > 1
+	if (sb == NISSA_SB_C_A || sb == NISSA_SB_C_LTE) {
+		/* Configure interrupt input */
+		gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl),
+				      GPIO_INPUT | GPIO_PULL_UP);
+	} else {
+		/* Port doesn't exist, doesn't need muxing */
+		USB_MUX_ENABLE_ALTERNATIVE(usb_mux_chain_1_no_mux);
+	}
+#endif
+
+	switch (sb) {
+#if NISSA_BOARD_HAS_HDMI_SUPPORT
+	case NISSA_SB_HDMI_A: {
+		/*
+		 * HDMI: two outputs control power which must be configured to
+		 * non-default settings, and HPD must be forwarded to the AP
+		 * on another output pin.
+		 */
+		const struct gpio_dt_spec *hpd_gpio =
+			GPIO_DT_FROM_ALIAS(gpio_hpd_odl);
+		static struct gpio_callback hdmi_hpd_cb;
+		int rv, irq_key;
+
+		nissa_configure_hdmi_power_gpios();
+
+#if CONFIG_SOC_IT8XXX2 && DT_NODE_EXISTS(I2C4_NODE)
+		/* disable i2c4 alternate function for better power number */
+		soc_it8xxx2_disable_i2c4_alt();
+#endif
+
+		/*
+		 * Control HDMI power according to AP power state. Some events
+		 * won't do anything if the corresponding pin isn't configured,
+		 * but that's okay.
+		 */
+		ap_power_ev_init_callback(
+			&power_cb, hdmi_power_handler,
+			AP_POWER_PRE_INIT | AP_POWER_HARD_OFF |
+				AP_POWER_STARTUP | AP_POWER_SHUTDOWN);
+		ap_power_ev_add_callback(&power_cb);
+
+		/*
+		 * Configure HPD input from sub-board; it's inverted by a buffer
+		 * on the sub-board.
+		 */
+		gpio_pin_configure_dt(hpd_gpio, GPIO_INPUT | GPIO_ACTIVE_LOW);
+		/* Register interrupt handler for HPD changes */
+		gpio_init_callback(&hdmi_hpd_cb, hdmi_hpd_interrupt,
+				   BIT(hpd_gpio->pin));
+		gpio_add_callback(hpd_gpio->port, &hdmi_hpd_cb);
+		rv = gpio_pin_interrupt_configure_dt(hpd_gpio,
+						     GPIO_INT_EDGE_BOTH);
+		__ASSERT(rv == 0,
+			 "HPD interrupt configuration returned error %d", rv);
+		/*
+		 * Run the HPD handler once to ensure output is in sync.
+		 * Lock interrupts to ensure that we don't cause desync if an
+		 * HPD interrupt comes in between the internal read of the input
+		 * and write to the output.
+		 */
+		irq_key = irq_lock();
+		hdmi_hpd_interrupt(hpd_gpio->port, &hdmi_hpd_cb,
+				   BIT(hpd_gpio->pin));
+		irq_unlock(irq_key);
+		break;
+	}
+#endif
+	case NISSA_SB_C_LTE:
+		/*
+		 * LTE: Set up callbacks for enabling/disabling
+		 * sub-board power on S5 state.
+		 */
+		gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_en_sub_s5_rails),
+				      GPIO_OUTPUT_INACTIVE);
+		/* Control LTE power when CPU entering or
+		 * exiting S5 state.
+		 */
+		ap_power_ev_init_callback(&power_cb, lte_power_handler,
+					  AP_POWER_HARD_OFF |
+						  AP_POWER_PRE_INIT);
+		ap_power_ev_add_callback(&power_cb);
+		break;
+
+	default:
+		break;
+	}
+}
+DECLARE_HOOK(HOOK_INIT, nereid_subboard_config, HOOK_PRIO_POST_FIRST);
+
+/*
+ * Enable interrupts
+ */
+static void board_init(void)
+{
+	/*
+	 * Enable USB-C interrupts.
+	 */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0));
+#if CONFIG_USB_PD_PORT_MAX_COUNT > 1
+	if (board_get_usb_pd_port_count() == 2)
+		gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1));
+#endif
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/zephyr/program/nissa/uldren/cbi.dtsi b/zephyr/program/nissa/uldren/cbi.dtsi
new file mode 100644
index 0000000000..40750beb7f
--- /dev/null
+++ b/zephyr/program/nissa/uldren/cbi.dtsi
@@ -0,0 +1,75 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+  /* Uldren-specific fw_config fields. */
+	nissa-fw-config {
+		/*
+		 * FW_CONFIG field to enable USB DB.
+		 */
+		sub-board {
+			enum-name = "FW_SUB_BOARD";
+			start = <1>;
+			size = <2>;
+
+			sub-board-1 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_SUB_BOARD_1";
+				value = <0>;
+			};
+			sub-board-2 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_SUB_BOARD_2";
+				value = <2>;
+			};
+			sub-board-3 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_SUB_BOARD_3";
+				value = <3>;
+			};
+		};
+		/*
+		 * FW_CONFIG field to enable KB back light or not.
+		 */
+		kb-bl {
+			enum-name = "FW_KB_BL";
+			start = <5>;
+			size = <1>;
+
+			no-kb-bl {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_KB_BL_NOT_PRESENT";
+				value = <0>;
+				default;
+			};
+			kb-bl-present {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_KB_BL_PRESENT";
+				value = <1>;
+			};
+		};
+
+		/*
+		 * FW_CONFIG field for tablet present or not.
+		 */
+		 tablet {
+			enum-name = "FW_TABLET";
+			start = <7>;
+			size = <1>;
+
+			no-tablet {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_TABLET_NOT_PRESENT";
+				value = <0>;
+			};
+			tablet-present {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_TABLET_PRESENT";
+				value = <1>;
+			};
+		};
+/delete-node/ fan;
+	};
+};
diff --git a/zephyr/program/nissa/uldren/generated.dtsi b/zephyr/program/nissa/uldren/generated.dtsi
new file mode 100644
index 0000000000..ab3b5264ae
--- /dev/null
+++ b/zephyr/program/nissa/uldren/generated.dtsi
@@ -0,0 +1,285 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * This file is auto-generated - do not edit!
+ */
+
+/ {
+
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc {
+			enum-name = "ADC_PP1050_PROC";
+			io-channels = <&adc0 4>;
+		};
+		adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 {
+			enum-name = "ADC_PP3300_S5";
+			io-channels = <&adc0 6>;
+		};
+		adc_temp_sensor_1: temp_sensor_1 {
+			enum-name = "ADC_TEMP_SENSOR_1";
+			io-channels = <&adc0 0>;
+		};
+		adc_temp_sensor_2: temp_sensor_2 {
+			enum-name = "ADC_TEMP_SENSOR_2";
+			io-channels = <&adc0 1>;
+		};
+		adc_temp_sensor_3: temp_sensor_3 {
+			enum-name = "ADC_TEMP_SENSOR_3";
+			io-channels = <&adc0 10>;
+		};
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		gpio_acc_int_l: acc_int_l {
+			gpios = <&gpio5 0 GPIO_INPUT>;
+		};
+		gpio_all_sys_pwrgd: all_sys_pwrgd {
+			gpios = <&gpioa 7 GPIO_INPUT>;
+		};
+		gpio_ccd_mode_odl: ccd_mode_odl {
+			gpios = <&gpioe 5 GPIO_INPUT>;
+			enum-name = "GPIO_CCD_MODE_ODL";
+		};
+		gpio_cpu_c10_gate_l: cpu_c10_gate_l {
+			gpios = <&gpio6 7 GPIO_INPUT>;
+		};
+		gpio_ec_battery_pres_odl: ec_battery_pres_odl {
+			gpios = <&gpioa 3 GPIO_INPUT>;
+			enum-name = "GPIO_BATT_PRES_ODL";
+		};
+		gpio_ec_cbi_wp: ec_cbi_wp {
+			gpios = <&gpio7 4 GPIO_OUTPUT>;
+		};
+		gpio_ec_edp_bl_en_od: ec_edp_bl_en_od {
+			gpios = <&gpiod 3 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_ENABLE_BACKLIGHT";
+		};
+		gpio_ec_entering_rw: ec_entering_rw {
+			gpios = <&gpio0 3 GPIO_OUTPUT>;
+			enum-name = "GPIO_ENTERING_RW";
+		};
+		gpio_ec_gsc_packet_mode: ec_gsc_packet_mode {
+			gpios = <&gpio7 5 GPIO_OUTPUT>;
+			enum-name = "GPIO_PACKET_MODE_EN";
+		};
+		gpio_ec_kso_02_inv: ec_kso_02_inv {
+			gpios = <&gpio1 7 (GPIO_OUTPUT_LOW | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_ec_pch_wake_odl: ec_pch_wake_odl {
+			gpios = <&gpiob 0 GPIO_ODR_LOW>;
+		};
+		gpio_ec_prochot_odl: ec_prochot_odl {
+			gpios = <&gpiof 1 GPIO_ODR_HIGH>;
+		};
+		gpio_ec_soc_dsw_pwrok: ec_soc_dsw_pwrok {
+			gpios = <&gpio6 1 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_int_odl: ec_soc_int_odl {
+			gpios = <&gpio8 0 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_EC_INT_L";
+		};
+		gpio_ec_soc_pch_pwrok_od: ec_soc_pch_pwrok_od {
+			gpios = <&gpio7 2 GPIO_ODR_HIGH>;
+		};
+		gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl {
+			gpios = <&gpioc 1 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_PCH_PWRBTN_L";
+		};
+		gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l {
+			gpios = <&gpioa 6 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_rtcrst: ec_soc_rtcrst {
+			gpios = <&gpio7 6 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_sys_pwrok: ec_soc_sys_pwrok {
+			gpios = <&gpio3 7 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_vccst_pwrgd_od: ec_soc_vccst_pwrgd_od {
+			gpios = <&gpioa 4 GPIO_ODR_HIGH>;
+		};
+		gpio_ec_wp_odl: ec_wp_odl {
+			gpios = <&gpioa 1 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_en_kb_bl: en_kb_bl {
+			gpios = <&gpioa 0 GPIO_OUTPUT>;
+			enum-name = "GPIO_EN_KEYBOARD_BACKLIGHT";
+		};
+		gpio_en_pp3300_s5: en_pp3300_s5 {
+			gpios = <&gpiob 6 GPIO_OUTPUT>;
+			enum-name = "GPIO_TEMP_SENSOR_POWER";
+		};
+		gpio_en_pp5000_pen_x: en_pp5000_pen_x {
+			gpios = <&gpioe 2 GPIO_OUTPUT>;
+		};
+		gpio_en_pp5000_s5: en_pp5000_s5 {
+			gpios = <&gpio4 0 GPIO_OUTPUT>;
+		};
+		gpio_en_slp_z: en_slp_z {
+			gpios = <&gpioe 1 GPIO_OUTPUT>;
+		};
+		gpio_en_usb_a0_vbus: en_usb_a0_vbus {
+			gpios = <&gpio9 1 GPIO_OUTPUT>;
+		};
+		gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl {
+			gpios = <&gpio0 0 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		gpio_imu_int_l: imu_int_l {
+			gpios = <&gpio5 6 GPIO_INPUT>;
+		};
+		gpio_imvp91_vrrdy_od: imvp91_vrrdy_od {
+			gpios = <&gpio4 3 GPIO_INPUT>;
+		};
+		gpio_lid_open: lid_open {
+			gpios = <&gpiod 2 GPIO_INPUT>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+		gpio_pen_detect_odl: pen_detect_odl {
+			gpios = <&gpio9 6 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_pg_pp1050_mem_s3_od: pg_pp1050_mem_s3_od {
+			gpios = <&gpiof 0 GPIO_INPUT>;
+		};
+		gpio_pg_pp5000_s5_od: pg_pp5000_s5_od {
+			gpios = <&gpio4 2 GPIO_INPUT>;
+		};
+		gpio_rsmrst_pwrgd_l: rsmrst_pwrgd_l {
+			gpios = <&gpio9 4 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_slp_s0_l: slp_s0_l {
+			gpios = <&gpio9 7 GPIO_INPUT>;
+		};
+		gpio_slp_s3_l: slp_s3_l {
+			gpios = <&gpioa 5 GPIO_INPUT>;
+		};
+		gpio_slp_s4_l: slp_s4_l {
+			gpios = <&gpio7 0 GPIO_INPUT>;
+		};
+		gpio_slp_sus_l: slp_sus_l {
+			gpios = <&gpio6 2 GPIO_INPUT>;
+		};
+		gpio_sub_usb_a1_ilimit_sdp: sub_usb_a1_ilimit_sdp {
+			gpios = <&gpiod 5 GPIO_OUTPUT>;
+			enum-name = "GPIO_USB2_ILIM_SEL";
+		};
+		gpio_sys_rst_odl: sys_rst_odl {
+			gpios = <&gpioc 5 GPIO_ODR_HIGH>;
+		};
+		gpio_tablet_mode_l: tablet_mode_l {
+			gpios = <&gpio9 5 GPIO_INPUT>;
+			enum-name = "GPIO_TABLET_MODE_L";
+		};
+		gpio_usb_a0_ilimit_sdp: usb_a0_ilimit_sdp {
+			gpios = <&gpio3 3 GPIO_OUTPUT>;
+			enum-name = "GPIO_USB1_ILIM_SEL";
+		};
+		gpio_usb_c0_int_odl: usb_c0_int_odl {
+			gpios = <&gpio0 1 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_vccin_aux_vid0: vccin_aux_vid0 {
+			gpios = <&gpio9 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		gpio_vccin_aux_vid1: vccin_aux_vid1 {
+			gpios = <&gpioe 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		gpio_voldn_btn_odl: voldn_btn_odl {
+			gpios = <&gpioa 2 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_DOWN_L";
+		};
+		gpio_volup_btn_odl: volup_btn_odl {
+			gpios = <&gpio9 3 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_UP_L";
+		};
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		i2c_ec_i2c_eeprom: ec_i2c_eeprom {
+			i2c-port = <&i2c0_0>;
+			enum-names = "I2C_PORT_EEPROM";
+		};
+		i2c_ec_i2c_sensor: ec_i2c_sensor {
+			i2c-port = <&i2c1_0>;
+			enum-names = "I2C_PORT_SENSOR";
+		};
+		i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 {
+			i2c-port = <&i2c3_0>;
+			enum-names = "I2C_PORT_USB_C0_TCPC";
+		};
+		i2c_ec_i2c_sub_usb_c1: ec_i2c_sub_usb_c1 {
+			i2c-port = <&i2c5_1>;
+			enum-names = "I2C_PORT_USB_C1_TCPC";
+		};
+		i2c_ec_i2c_batt: ec_i2c_batt {
+			i2c-port = <&i2c7_0>;
+			enum-names = "I2C_PORT_BATTERY";
+		};
+	};
+};
+
+&adc0 {
+	status = "okay";
+	pinctrl-0 = <&adc0_chan0_gp45
+		     &adc0_chan1_gp44
+		     &adc0_chan4_gp41
+		     &adc0_chan6_gp34
+		     &adc0_chan10_gpe0>;
+	pinctrl-names = "default";
+};
+
+
+&i2c0_0 {
+	status = "okay";
+	pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>;
+	pinctrl-names = "default";
+};
+
+&i2c1_0 {
+	status = "okay";
+	pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>;
+	pinctrl-names = "default";
+};
+
+&i2c3_0 {
+	status = "okay";
+	pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>;
+	pinctrl-names = "default";
+};
+
+&i2c5_1 {
+	status = "okay";
+	pinctrl-0 = <&i2c5_1_sda_scl_gpf4_f5>;
+	pinctrl-names = "default";
+};
+
+&i2c7_0 {
+	status = "okay";
+	pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>;
+	pinctrl-names = "default";
+};
+
+&i2c_ctrl0 {
+	status = "okay";
+};
+
+&i2c_ctrl1 {
+	status = "okay";
+};
+
+&i2c_ctrl3 {
+	status = "okay";
+};
+
+&i2c_ctrl5 {
+	status = "okay";
+};
+
+&i2c_ctrl7 {
+	status = "okay";
+};
diff --git a/zephyr/program/nissa/uldren/keyboard.dtsi b/zephyr/program/nissa/uldren/keyboard.dtsi
new file mode 100644
index 0000000000..f958ed9cea
--- /dev/null
+++ b/zephyr/program/nissa/uldren/keyboard.dtsi
@@ -0,0 +1,47 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	kblight {
+		compatible = "cros-ec,kblight-pwm";
+		pwms = <&pwm6 6 PWM_KHZ(10) PWM_POLARITY_NORMAL>;
+	};
+};
+
+&pwm6 {
+	status = "okay";
+	pinctrl-0 = <&pwm6_gpc0>;
+	pinctrl-names = "default";
+};
+
+&cros_kb_raw {
+	status = "okay";
+	/* No KSO2 (it's inverted and implemented by GPIO) */
+	pinctrl-0 = <
+		&ksi0_gp31
+		&ksi1_gp30
+		&ksi2_gp27
+		&ksi3_gp26
+		&ksi4_gp25
+		&ksi5_gp24
+		&ksi6_gp23
+		&ksi7_gp22
+		&kso00_gp21
+		&kso01_gp20
+		&kso03_gp16
+		&kso04_gp15
+		&kso05_gp14
+		&kso06_gp13
+		&kso07_gp12
+		&kso08_gp11
+		&kso09_gp10
+		&kso10_gp07
+		&kso11_gp06
+		&kso12_gp05
+		&kso13_gp04
+		&kso14_gp82
+	>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/nissa/uldren/led_pins.dtsi b/zephyr/program/nissa/uldren/led_pins.dtsi
new file mode 100644
index 0000000000..03f9d61df0
--- /dev/null
+++ b/zephyr/program/nissa/uldren/led_pins.dtsi
@@ -0,0 +1,59 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	pwmleds {
+		compatible = "pwm-leds";
+		pwm_led_y_c0: pwm_led_y_c0 {
+			pwms = <&pwm2 2 PWM_HZ(324) PWM_POLARITY_INVERTED>;
+		};
+		pwm_led_w_c0: pwm_led_w_c0 {
+			pwms = <&pwm0 0 PWM_HZ(324) PWM_POLARITY_INVERTED>;
+		};
+		/* reserve to use */
+		pwms = <&pwm1 1 PWM_HZ(324) PWM_POLARITY_INVERTED>;
+	};
+
+	pwm-led-pins {
+		compatible = "cros-ec,pwm-led-pins";
+
+		battery_led: battery-led {
+			led-id = "EC_LED_ID_BATTERY_LED";
+			led-pwms = <&pwm_led_y_c0 &pwm_led_w_c0>;
+			color_off: color-off {
+				led-color = "LED_OFF";
+				led-values = <0 0>;
+			};
+
+			color_amber: color-amber {
+				led-color = "LED_AMBER";
+				br-color = "EC_LED_COLOR_AMBER";
+				led-values = <100 0>;
+			};
+
+			color_white: color-white {
+				led-color = "LED_WHITE";
+				br-color = "EC_LED_COLOR_WHITE";
+				led-values = <0 100>;
+			};
+		};
+	};
+};
+
+/* LED2 */
+&pwm0 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm0_gpc3>;
+	pinctrl-names = "default";
+};
+
+/* LED1 */
+&pwm2 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm2_gpc4>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/nissa/uldren/led_policy.dtsi b/zephyr/program/nissa/uldren/led_policy.dtsi
new file mode 100644
index 0000000000..addbde1692
--- /dev/null
+++ b/zephyr/program/nissa/uldren/led_policy.dtsi
@@ -0,0 +1,115 @@
+#include <dt-bindings/battery.h>
+
+/ {
+	led-colors {
+		compatible = "cros-ec,led-policy";
+
+		power-state-charge {
+			charge-state = "LED_PWRS_CHARGE";
+			batt-lvl = <BATTERY_LEVEL_EMPTY
+						BATTERY_LEVEL_FULL>;
+
+			color-0 {
+				led-color = <&color_white>;
+			};
+		};
+
+		power-state-near-full {
+			charge-state = "LED_PWRS_CHARGE_NEAR_FULL";
+
+			color-0 {
+				led-color = <&color_off>;
+			};
+		};
+
+		power-state-discharge-s0 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S0";
+			batt-lvl = <BATTERY_LEVEL_LOW BATTERY_LEVEL_FULL>;
+
+			color-0 {
+				led-color = <&color_off>;
+			};
+		};
+
+		power-state-discharge-s3 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S3";
+
+			color-0 {
+				led-color = <&color_off>;
+			};
+		};
+
+		power-state-discharge-s5 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S5";
+
+			color-0 {
+				led-color = <&color_off>;
+			};
+		};
+
+		power-state-discharge-s0-batt-low {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S0";
+			batt-lvl = <BATTERY_LEVEL_EMPTY BATTERY_LEVEL_LOW>;
+
+			color-0 {
+				led-color = <&color_amber>;
+			};
+		};
+
+		power-state-discharge-s3-batt-low {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S3";
+			batt-lvl = <BATTERY_LEVEL_EMPTY BATTERY_LEVEL_LOW>;
+
+			color-0 {
+				led-color = <&color_amber>;
+			};
+		};
+
+		power-state-error-s0 {
+			charge-state = "LED_PWRS_ERROR";
+			chipset-state = "POWER_S0";
+			/* Amber 1 sec, off 1 sec */
+			color-0 {
+				led-color = <&color_amber>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <1000>;
+			};
+		};
+
+		power-state-error-s3 {
+			charge-state = "LED_PWRS_ERROR";
+			chipset-state = "POWER_S3";
+			/* Amber 1 sec, off 3 sec */
+			color-0 {
+				led-color = <&color_amber>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <3000>;
+			};
+		};
+
+		power-state-error-s5 {
+			charge-state = "LED_PWRS_ERROR";
+			chipset-state = "POWER_S5";
+			/* Amber 1 sec, off 3 sec */
+			color-0 {
+				led-color = <&color_amber>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <3000>;
+			};
+		};
+	};
+};
diff --git a/zephyr/program/nissa/uldren/motionsense.dtsi b/zephyr/program/nissa/uldren/motionsense.dtsi
new file mode 100644
index 0000000000..baaec61e5e
--- /dev/null
+++ b/zephyr/program/nissa/uldren/motionsense.dtsi
@@ -0,0 +1,147 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+ #include <dt-bindings/motionsense/utils.h>
+
+
+/ {
+	aliases {
+		/*
+		 * Interrupt bindings for sensor devices.
+		 */
+		bmi3xx-int = &base_accel;
+		bma4xx-int = &lid_accel;
+	};
+
+	/*
+	 * Declare mutexes used by sensor drivers.
+	 * A mutex node is used to create an instance of mutex_t.
+	 * A mutex node is referenced by a sensor node if the
+	 * corresponding sensor driver needs to use the
+	 * instance of the mutex.
+	 */
+	motionsense-mutex {
+		compatible = "cros-ec,motionsense-mutex";
+		lid_mutex: lid-mutex {
+		};
+
+		base_mutex: base-mutex {
+		};
+	};
+
+	/* Rotation matrix used by drivers. */
+	motionsense-rotation-ref {
+		compatible = "cros-ec,motionsense-rotation-ref";
+		lid_rot_ref: lid-rotation-ref {
+			mat33 = <0 1 0
+				 (-1) 0 0
+				 0 0 1>;
+		};
+
+		base_rot_ref: base-rotation-ref {
+			mat33 = <1 0 0
+				 0 1 0
+				 0 0 1>;
+		};
+	};
+
+	/*
+	 * Driver specific data. A driver-specific data can be shared with
+	 * different motion sensors while they are using the same driver.
+	 *
+	 * If a node's compatible starts with "cros-ec,accelgyro-", it is for
+	 * a common structure defined in accelgyro.h.
+	 * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for
+	 * "struct als_drv_data_t" in accelgyro.h
+	 */
+	motionsense-sensor-data {
+		bmi323_data: bmi323-drv-data {
+			compatible = "cros-ec,drvdata-bmi3xx";
+			status = "okay";
+		};
+
+		bma422_data: bma422-drv-data {
+			compatible = "cros-ec,drvdata-bma4xx";
+			status = "okay";
+		};
+	};
+
+	/*
+	 * List of motion sensors that creates motion_sensors array.
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
+	 * motion sensor IDs for lid angle calculation.
+	 * TODO(b/238139272): The first entries of the array must be
+	 * accelerometers,then gyroscope. Fix this dependency in the DTS
+	 * processing which makes the devicetree entries independent.
+	 */
+	motionsense-sensor {
+		lid_accel: lid-accel {
+			compatible = "cros-ec,bma4xx";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&lid_mutex>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&lid_rot_ref>;
+			default-range = <2>;
+			drv-data = <&bma422_data>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_accel: base-accel {
+			compatible = "cros-ec,bmi3xx-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&bmi323_data>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_gyro: base-gyro {
+			compatible = "cros-ec,bmi3xx-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&bmi323_data>;
+		};
+	};
+
+	motionsense-sensor-info {
+		compatible = "cros-ec,motionsense-sensor-info";
+
+		/*
+		 * list of GPIO interrupts that have to
+		 * be enabled at initial stage
+		 */
+		sensor-irqs = <&int_imu &int_lid_imu>;
+	};
+};
diff --git a/zephyr/program/nissa/uldren/overlay.dtsi b/zephyr/program/nissa/uldren/overlay.dtsi
new file mode 100644
index 0000000000..d32f4908a7
--- /dev/null
+++ b/zephyr/program/nissa/uldren/overlay.dtsi
@@ -0,0 +1,430 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <cros/thermistor/thermistor.dtsi>
+#include <dt-bindings/usbc_mux.h>
+#include <dt-bindings/usb_pd_tcpm.h>
+
+/ {
+	aliases {
+		gpio-cbi-wp = &gpio_ec_cbi_wp;
+		gpio-wp = &gpio_ec_wp_odl;
+		int-wp = &int_wp_l;
+		gpio-kbd-kso2 = &gpio_ec_kso_02_inv;
+	};
+
+	ec-console {
+		compatible = "ec-console";
+		disabled = "events", "lpc", "hostcmd";
+	};
+
+	batteries {
+		default_battery: byd_yt39x {
+			compatible = "byd,yt39x", "battery-smart";
+		};
+		byd_x0y5m {
+			compatible = "byd,x0y5m", "battery-smart";
+		};
+		lgc_8ghcx {
+			compatible = "lgc,8ghcx", "battery-smart";
+		};
+		sunwoda_ctgkt {
+			compatible = "sunwoda,ctgkt", "battery-smart";
+		};
+		sunwoda_cosctgkt {
+			compatible = "sunwoda,cosctgkt", "battery-smart";
+		};
+		smp_atl26jgk {
+			compatible = "smp,atl26jgk", "battery-smart";
+		};
+		smp_atlrf9h3 {
+			compatible = "smp,atlrf9h3", "battery-smart";
+		};
+		smp_cos26jgk {
+			compatible = "smp,cos26jgk", "battery-smart";
+		};
+		smp_cosrf9h3 {
+			compatible = "smp,cosrf9h3", "battery-smart";
+		};
+	};
+
+	hibernate-wake-pins {
+		compatible = "cros-ec,hibernate-wake-pins";
+		wakeup-irqs = <
+			&int_power_button
+			&int_lid_open
+		>;
+	};
+
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_power_button: power_button {
+			irq-pin = <&gpio_gsc_ec_pwr_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_button_interrupt";
+		};
+		int_wp_l: wp_l {
+			irq-pin = <&gpio_ec_wp_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "switch_interrupt";
+		};
+		int_lid_open: lid_open {
+			irq-pin = <&gpio_lid_open>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "lid_interrupt";
+		};
+		int_tablet_mode: tablet_mode {
+			irq-pin = <&gpio_tablet_mode_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "gmr_tablet_switch_isr";
+		};
+		int_imu: ec_imu {
+			irq-pin = <&gpio_imu_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "bmi3xx_interrupt";
+		};
+		int_lid_imu: lid_imu {
+			irq-pin = <&gpio_acc_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "bma4xx_interrupt";
+		};
+		int_vol_down: vol_down {
+			irq-pin = <&gpio_voldn_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+		int_vol_up: vol_up {
+			irq-pin = <&gpio_volup_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+		int_usb_c0: usb_c0 {
+			irq-pin = <&gpio_usb_c0_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "usb_interrupt";
+		};
+		int_usb_c1: usb_c1 {
+			irq-pin = <&gpio_sb_1>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "usb_interrupt";
+		};
+	};
+
+	named-gpios {
+		gpio_sb_1: sb-1 {
+			gpios = <&gpio0 2 GPIO_PULL_UP>;
+			no-auto-init;
+		};
+
+		gpio_sb_2: sb-2 {
+			gpios = <&gpiod 4 GPIO_OUTPUT>;
+			no-auto-init;
+		};
+
+		/*
+		 * Set I2C pins for type C sub-board to be low voltage (I2C5_1).
+		 * We do this for all boards, since the pins are 3.3V tolerant,
+		 * and the only 2 types of sub-boards used on uldren both have
+		 * type-C ports on them.
+		 */
+		gpio_sb_3: sb-3 {
+			gpios = <&gpiof 4 (GPIO_OPEN_DRAIN | GPIO_VOLTAGE_1P8)>;
+			no-auto-init;
+		};
+		gpio_sb_4: sb-4 {
+			gpios = <&gpiof 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+			no-auto-init;
+		};
+		ec-i2c-sensor-scl {
+			gpios = <&gpio9 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		ec-i2c-sensor-sda {
+			gpios = <&gpio8 7 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+	};
+
+	/*
+	 * Aliases used for sub-board GPIOs.
+	 */
+	aliases {
+		/*
+		 * Input GPIO when used with type-C port 1
+		 */
+		gpio-usb-c1-int-odl = &gpio_sb_1;
+		gpio-en-rails-odl = &gpio_sb_1;
+		/*
+		 * Sub-board with type A USB, enable.
+		 */
+		gpio-en-usb-a1-vbus = &gpio_sb_2;
+		/*
+		 * Enable S5 rails for LTE sub-board
+		 */
+		gpio-en-sub-s5-rails = &gpio_sb_2;
+	};
+
+	temp_memory: memory {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_1>;
+	};
+	temp_charger: charger {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_2>;
+	};
+	temp_ambient: ambient {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_3>;
+	};
+
+	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
+		memory {
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_memory>;
+		};
+		charger {
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_charger>;
+		};
+		ambient {
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_ambient>;
+		};
+	};
+
+	usba {
+		compatible = "cros-ec,usba-port-enable-pins";
+		/*
+		 * sb_2 is only configured as GPIO when USB-A1 is present,
+		 * but it's still safe to control when disabled.
+		 *
+		 * ILIM_SEL pins are referred to by legacy enum name,
+		 * GPIO_USB*_ILIM_SEL. The one for port A1 is unused on
+		 * sub-boards that don't have USB-A so is safe to control
+		 * regardless of system configuration.
+		 */
+		enable-pins = <&gpio_en_usb_a0_vbus &gpio_sb_2>;
+		status = "okay";
+	};
+
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+			bc12 = <&bc12_port0>;
+			chg = <&chg_port0>;
+			tcpc = <&tcpc_port0>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_0>;
+			};
+		};
+		port0-muxes {
+			virtual_mux_0: virtual-mux-0 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+		/*
+		 * TODO(b:211693800): port1 may not be present on some
+		 * sub-boards.
+		 */
+		port1@1 {
+			compatible = "named-usbc-port";
+			reg = <1>;
+			bc12 = <&bc12_port1>;
+			chg = <&chg_port1>;
+			tcpc = <&tcpc_port1>;
+			usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_1 &anx7483_mux_1>;
+			};
+			usb_mux_chain_1_no_mux: usb-mux-chain-1-no-mux {
+				compatible = "cros-ec,usb-mux-chain";
+				alternative-chain;
+				usb-muxes = <&virtual_mux_1>;
+			};
+		};
+		port1-muxes {
+			virtual_mux_1: virtual-mux-1 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+	};
+
+	 /*
+	  * Declare unused GPIOs so that they are shut down
+	  * and use minimal power
+	  */
+	  unused-pins {
+		compatible = "unused-gpios";
+		unused-gpios =
+			<&gpio3 2 0>,
+			<&gpio3 5 0>,
+			<&gpio3 6 0>,
+			<&gpio5 7 0>,
+			<&gpio6 0 0>,
+			<&gpio6 3 0>,
+			<&gpio6 6 0>,
+			<&gpio7 3 0>,
+			<&gpio8 1 0>,
+			<&gpio8 3 0>,
+			<&gpio8 5 0>,
+			<&gpio8 6 0>,
+			<&gpiob 1 0>,
+			<&gpiob 7 0>,
+			<&gpioc 0 0>,
+			<&gpioc 6 0>,
+			<&gpioc 7 0>,
+			<&gpioe 4 0>,
+			<&gpiof 2 0>,
+			<&gpiof 3 0>;
+	 };
+};
+
+&thermistor_3V3_51K1_47K_4050B {
+	status = "okay";
+};
+
+&adc_ec_vsense_pp3300_s5 {
+	/*
+	 * Voltage divider on input has 47k upper and 220k lower legs with
+	 * 2714 mV full-scale reading on the ADC. Apply the largest possible
+	 * multiplier (without overflowing int32) to get the best possible
+	 * approximation of the actual ratio, but derate by a factor of two to
+	 * ensure unexpectedly high values won't overflow.
+	 */
+	mul = <(791261 / 2)>;
+	div = <(651975 / 2)>;
+};
+
+/* Set bus speeds for I2C */
+&i2c0_0 {
+	label = "I2C_EEPROM";
+	clock-frequency = <I2C_BITRATE_FAST>;
+
+	cbi_eeprom: eeprom@50 {
+		compatible = "atmel,at24";
+		reg = <0x50>;
+		size = <2048>;
+		pagesize = <16>;
+		address-width = <8>;
+		timeout = <5>;
+	};
+};
+
+&i2c1_0 {
+	label = "I2C_SENSOR";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&i2c3_0 {
+	label = "I2C_USB_C0_TCPC";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+
+	bc12_port0: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+		/*
+		 * BC1.2 interrupt is shared with TCPC, so
+		 * IRQ is not specified here and handled by
+		 * usb_c0_interrupt.
+		 */
+	};
+
+	chg_port0: isl923x@9 {
+		compatible = "intersil,isl923x";
+		status = "okay";
+		reg = <0x9>;
+	};
+
+	tcpc_port0: raa489000@22 {
+		compatible = "renesas,raa489000";
+		reg = <0x22>;
+		tcpc-flags = <(
+			TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_VBUS_MONITOR)>;
+	};
+};
+
+&i2c5_1 {
+	label = "I2C_SUB_C1_TCPC";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+
+	bc12_port1: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+	};
+
+	chg_port1: isl923x@9 {
+		compatible = "intersil,isl923x";
+		status = "okay";
+		reg = <0x9>;
+	};
+
+	tcpc_port1: raa489000@22 {
+		compatible = "renesas,raa489000";
+		reg = <0x22>;
+		tcpc-flags = <(
+			TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_VBUS_MONITOR)>;
+	};
+
+	anx7483_mux_1: anx7483-mux-1@3e {
+		compatible = "analogix,anx7483";
+		reg = <0x3e>;
+		board-set = "anx7483_set_default_tuning";
+		flags = <USB_MUX_FLAG_RESETS_IN_G3>;
+	};
+};
+
+&i2c7_0 {
+	label = "I2C_BATTERY";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+};
+
+&pwm5_gpb7 {
+	drive-open-drain;
+};
+
+&pwm5 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm5_gpb7>;
+	pinctrl-names = "default";
+};
+
+/* host interface */
+&espi0 {
+	status = "okay";
+	pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>;
+	pinctrl-names = "default";
+};
+
+/*
+ * Declare GPIOs that have leakage current caused by board issues here. NPCX ec
+ * will disable their input buffers before entering deep sleep and restore them
+ * after waking up automatically for better power consumption.
+ */
+&power_leakage_io {
+	leak-gpios = <&gpioa 4 GPIO_OPEN_DRAIN
+		      &gpiof 1 GPIO_OPEN_DRAIN>;
+};
diff --git a/zephyr/program/nissa/uldren/power_signals.dtsi b/zephyr/program/nissa/uldren/power_signals.dtsi
new file mode 100644
index 0000000000..99e64cc52f
--- /dev/null
+++ b/zephyr/program/nissa/uldren/power_signals.dtsi
@@ -0,0 +1,220 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	chosen {
+		intel-ap-pwrseq,espi = &espi0;
+	};
+
+	common-pwrseq {
+		compatible = "intel,ap-pwrseq";
+
+		sys-pwrok-delay = <10>;
+		all-sys-pwrgd-timeout = <20>;
+	};
+
+	pwr-en-pp5000-s5 {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PP5000_S5 enable output to regulator";
+		enum-name = "PWR_EN_PP5000_A";
+		gpios = <&gpio4 0 0>;
+		output;
+	};
+	pwr-en-pp3300-s5 {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PP3300_S5 enable output to LS";
+		enum-name = "PWR_EN_PP3300_A";
+		gpios = <&gpiob 6 0>;
+		output;
+	};
+	pwr-pg-ec-rsmrst-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST power good from regulator";
+		enum-name = "PWR_RSMRST";
+		gpios = <&gpio9 4 0>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-ec-pch-rsmrst-odl {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST output to PCH";
+		enum-name = "PWR_EC_PCH_RSMRST";
+		gpios = <&gpioa 6 0>;
+		output;
+	};
+	pwr-slp-s0-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_S0_L input from PCH";
+		enum-name = "PWR_SLP_S0";
+		gpios = <&gpio9 7 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-slp-s3-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_S3_L input from PCH";
+		enum-name = "PWR_SLP_S3";
+		gpios = <&gpioa 5 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-slp-sus-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_SUS_L input from PCH";
+		enum-name = "PWR_SLP_SUS";
+		gpios = <&gpio6 2 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-ec-soc-dsw-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "DSW_PWROK output to PCH";
+		enum-name = "PWR_EC_SOC_DSW_PWROK";
+		gpios = <&gpio6 1 0>;
+		output;
+	};
+	pwr-vccst-pwrgd-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "VCCST_PWRGD output to PCH";
+		enum-name = "PWR_VCCST_PWRGD";
+		gpios = <&gpioa 4 GPIO_OPEN_DRAIN>;
+		output;
+	};
+	pwr-imvp9-vrrdy-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "VRRDY input from IMVP9";
+		enum-name = "PWR_IMVP9_VRRDY";
+		gpios = <&gpio4 3 0>;
+	};
+	pwr-pch-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PCH_PWROK output to PCH";
+		enum-name = "PWR_PCH_PWROK";
+		gpios = <&gpio7 2 GPIO_OPEN_DRAIN>;
+		output;
+	};
+	pwr-ec-pch-sys-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_PWROK output to PCH";
+		enum-name = "PWR_EC_PCH_SYS_PWROK";
+		gpios = <&gpio3 7 0>;
+		output;
+	};
+	pwr-sys-rst-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_RESET# output to PCH";
+		enum-name = "PWR_SYS_RST";
+		gpios = <&gpioc 5 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>;
+		output;
+	};
+	pwr-slp-s4 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S4 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S4";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4";
+		vw-invert;
+	};
+	pwr-slp-s5 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S5 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S5";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5";
+		vw-invert;
+	};
+	pwr-all-sys-pwrgd {
+		compatible = "intel,ap-pwrseq-external";
+		dbg-label = "Combined all power good";
+		enum-name = "PWR_ALL_SYS_PWRGD";
+	};
+	pwr-adc-pp3300 {
+		compatible = "intel,ap-pwrseq-adc";
+		dbg-label = "PP3300 PWROK (from ADC)";
+		enum-name = "PWR_DSW_PWROK";
+		trigger-high = <&cmp_pp3300_s5_high>;
+		trigger-low = <&cmp_pp3300_s5_low>;
+	};
+	pwr-adc-pp1p05 {
+		compatible = "intel,ap-pwrseq-adc";
+		dbg-label = "PP1P05 PWROK (from ADC)";
+		enum-name = "PWR_PG_PP1P05";
+		trigger-high = <&cmp_pp1p05_high>;
+		trigger-low = <&cmp_pp1p05_low>;
+	};
+
+	adc-cmp {
+		cmp_pp3300_s5_high: pp3300_high {
+			compatible = "nuvoton,adc-cmp";
+			io-channels = <&adc0 6>;
+			comparison = "ADC_CMP_NPCX_GREATER";
+			/*
+			 * This is 90% of nominal voltage considering voltage
+			 * divider on ADC input.
+			 */
+			threshold-mv = <2448>;
+		};
+		cmp_pp3300_s5_low: pp3300_low {
+			compatible = "nuvoton,adc-cmp";
+			io-channels = <&adc0 6>;
+			comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL";
+			threshold-mv = <2448>;
+		};
+		cmp_pp1p05_high: pp1p05_high {
+			compatible = "nuvoton,adc-cmp";
+			io-channels = <&adc0 4>;
+			comparison = "ADC_CMP_NPCX_GREATER";
+			/* Setting at 90% of nominal voltage */
+			threshold-mv = <945>;
+		};
+		cmp_pp1p05_low: pp1p05_low {
+			compatible = "nuvoton,adc-cmp";
+			io-channels = <&adc0 4>;
+			comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL";
+			threshold-mv = <945>;
+		};
+	};
+};
+
+/*
+ * Because the power signals directly reference the GPIOs,
+ * the correspinding named-gpios need to have no-auto-init set.
+ */
+&gpio_ec_soc_dsw_pwrok {
+	no-auto-init;
+};
+&gpio_ec_soc_pch_pwrok_od {
+	no-auto-init;
+};
+&gpio_ec_soc_rsmrst_l {
+	no-auto-init;
+};
+&gpio_ec_soc_sys_pwrok {
+	no-auto-init;
+};
+&gpio_ec_soc_vccst_pwrgd_od {
+	no-auto-init;
+};
+&gpio_en_pp3300_s5 {
+	no-auto-init;
+};
+&gpio_en_pp5000_s5 {
+	no-auto-init;
+};
+&gpio_imvp91_vrrdy_od {
+	no-auto-init;
+};
+&gpio_rsmrst_pwrgd_l {
+	no-auto-init;
+};
+&gpio_slp_s0_l {
+	no-auto-init;
+};
+&gpio_slp_s3_l {
+	no-auto-init;
+};
+&gpio_slp_s4_l {
+	no-auto-init;
+};
+&gpio_slp_sus_l {
+	no-auto-init;
+};
+&gpio_sys_rst_odl {
+	no-auto-init;
+};
diff --git a/zephyr/program/nissa/uldren/project.conf b/zephyr/program/nissa/uldren/project.conf
new file mode 100644
index 0000000000..3ad1c0322f
--- /dev/null
+++ b/zephyr/program/nissa/uldren/project.conf
@@ -0,0 +1,23 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_BOARD_ULDREN=y
+CONFIG_PLATFORM_EC_OCPC=y
+CONFIG_NISSA_SUB_BOARD=n
+
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y
+CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y
+CONFIG_PLATFORM_EC_MAX_SENSOR_FREQ_MILLIHZ=100000
+CONFIG_PLATFORM_EC_DYNAMIC_MOTION_SENSOR_COUNT=y
+
+# Both ports use a SLGC55545 smart switch with CTL1..3 fixed high,
+# for SDP2 or CDP only.
+CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART=y
+CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_CDP_SDP_ONLY=y
+CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_DEFAULT_CDP=y
+CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_INVERTED=y
+
+# BTN
+CONFIG_PLATFORM_EC_BUTTONS_RUNTIME_CONFIG=y
diff --git a/zephyr/program/nissa/uldren/project.overlay b/zephyr/program/nissa/uldren/project.overlay
new file mode 100644
index 0000000000..f56a20e235
--- /dev/null
+++ b/zephyr/program/nissa/uldren/project.overlay
@@ -0,0 +1,15 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+ #include "../cbi.dtsi"
+
+ #include "cbi.dtsi"
+ #include "generated.dtsi"
+ #include "keyboard.dtsi"
+ #include "led_pins.dtsi"
+ #include "led_policy.dtsi"
+ #include "motionsense.dtsi"
+ #include "overlay.dtsi"
+ #include "power_signals.dtsi"
diff --git a/zephyr/program/nissa/uldren/src/charger.c b/zephyr/program/nissa/uldren/src/charger.c
new file mode 100644
index 0000000000..2b1c285a27
--- /dev/null
+++ b/zephyr/program/nissa/uldren/src/charger.c
@@ -0,0 +1,55 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "charger.h"
+#include "charger/isl923x_public.h"
+#include "console.h"
+#include "extpower.h"
+#include "usb_pd.h"
+
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+int extpower_is_present(void)
+{
+	int port;
+	int rv;
+	bool acok;
+
+	for (port = 0; port < board_get_usb_pd_port_count(); port++) {
+		rv = raa489000_is_acok(port, &acok);
+		if ((rv == EC_SUCCESS) && acok)
+			return 1;
+	}
+
+	return 0;
+}
+
+/*
+ * Uldren does not have a GPIO indicating whether extpower is present,
+ * so detect using the charger(s).
+ */
+__override void board_check_extpower(void)
+{
+	static int last_extpower_present;
+	int extpower_present = extpower_is_present();
+
+	if (last_extpower_present ^ extpower_present)
+		extpower_handle_update(extpower_present);
+
+	last_extpower_present = extpower_present;
+}
+
+__override void board_hibernate(void)
+{
+	/* Shut down the chargers */
+	if (board_get_usb_pd_port_count() == 2)
+		raa489000_hibernate(CHARGER_SECONDARY, true);
+	raa489000_hibernate(CHARGER_PRIMARY, true);
+	LOG_INF("Charger(s) hibernated");
+	cflush();
+}
diff --git a/zephyr/program/nissa/uldren/src/form_factor.c b/zephyr/program/nissa/uldren/src/form_factor.c
new file mode 100644
index 0000000000..2dcc61c590
--- /dev/null
+++ b/zephyr/program/nissa/uldren/src/form_factor.c
@@ -0,0 +1,49 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "accelgyro.h"
+#include "button.h"
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+#include "driver/accel_bma4xx.h"
+#include "driver/accelgyro_bmi323.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "motion_sense.h"
+#include "motionsense_sensors.h"
+#include "tablet_mode.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+static void form_factor_init(void)
+{
+	int ret;
+	uint32_t val;
+
+	/*check tabletmode*/
+	ret = cros_cbi_get_fw_config(FW_TABLET, &val);
+	if (ret != 0) {
+		LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_TABLET);
+		return;
+	}
+	if (val == FW_TABLET_NOT_PRESENT) {
+		LOG_INF("Clamshell: disable motionsense function.");
+		motion_sensor_count = 0;
+		gmr_tablet_switch_disable();
+		gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_imu));
+		gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_imu_int_l),
+				      GPIO_DISCONNECTED);
+
+		LOG_INF("Clamshell: disable volume button function.");
+		button_disable_gpio(BUTTON_VOLUME_UP);
+		button_disable_gpio(BUTTON_VOLUME_DOWN);
+	} else {
+		LOG_INF("Tablet: Enable motionsense function.");
+	}
+}
+DECLARE_HOOK(HOOK_INIT, form_factor_init, HOOK_PRIO_POST_I2C);
diff --git a/zephyr/program/nissa/uldren/src/kb_backlight.c b/zephyr/program/nissa/uldren/src/kb_backlight.c
new file mode 100644
index 0000000000..1f73d3e8be
--- /dev/null
+++ b/zephyr/program/nissa/uldren/src/kb_backlight.c
@@ -0,0 +1,34 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "board_config.h"
+#include "common.h"
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(uldren, CONFIG_NISSA_LOG_LEVEL);
+
+__override uint32_t board_override_feature_flags0(uint32_t flags0)
+{
+	int ret;
+	uint32_t val;
+
+	/*
+	 * Remove keyboard backlight feature for devices that don't support it.
+	 */
+	ret = cros_cbi_get_fw_config(FW_KB_BL, &val);
+	if (ret != 0) {
+		LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_KB_BL);
+		return flags0;
+	}
+
+	if (val == FW_KB_BL_NOT_PRESENT)
+		return (flags0 & ~EC_FEATURE_MASK_0(EC_FEATURE_PWM_KEYB));
+	else
+		return flags0;
+}
diff --git a/zephyr/program/nissa/uldren/src/sub_board.c b/zephyr/program/nissa/uldren/src/sub_board.c
new file mode 100644
index 0000000000..0597fe1f89
--- /dev/null
+++ b/zephyr/program/nissa/uldren/src/sub_board.c
@@ -0,0 +1,196 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Uldren sub-board hardware configuration */
+
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+#include "driver/tcpm/tcpci.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "task.h"
+#include "uldren_sub_board.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usbc/usb_muxes.h"
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/sys/printk.h>
+
+#include <ap_power/ap_power.h>
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+static uint8_t cached_usb_pd_port_count;
+
+__override uint8_t board_get_usb_pd_port_count(void)
+{
+	__ASSERT(cached_usb_pd_port_count != 0,
+		 "sub-board detection did not run before a port count request");
+	if (cached_usb_pd_port_count == 0)
+		LOG_WRN("USB PD Port count not initialized!");
+	return cached_usb_pd_port_count;
+}
+
+test_export_static enum uldren_sub_board_type uldren_cached_sub_board =
+	ULDREN_SB_UNKNOWN;
+/*
+ * Retrieve sub-board type from FW_CONFIG.
+ */
+enum uldren_sub_board_type uldren_get_sb_type(void)
+{
+	int ret;
+	uint32_t val;
+
+	/*
+	 * Return cached value.
+	 */
+	if (uldren_cached_sub_board != ULDREN_SB_UNKNOWN)
+		return uldren_cached_sub_board;
+
+	uldren_cached_sub_board = ULDREN_SB_NONE; /* Defaults to none */
+	ret = cros_cbi_get_fw_config(FW_SUB_BOARD, &val);
+	if (ret != 0) {
+		LOG_WRN("Error retrieving CBI FW_CONFIG field %d",
+			FW_SUB_BOARD);
+		return uldren_cached_sub_board;
+	}
+	switch (val) {
+	default:
+		LOG_WRN("No sub-board defined");
+		break;
+	case FW_SUB_BOARD_2:
+		uldren_cached_sub_board = ULDREN_SB_C;
+		LOG_INF("SB: USB type C only");
+		break;
+
+	case FW_SUB_BOARD_3:
+		uldren_cached_sub_board = ULDREN_SB_C_LTE;
+		LOG_INF("SB: USB type C, WWAN LTE");
+		break;
+	}
+	return uldren_cached_sub_board;
+}
+
+/*
+ * Initialise the USB PD port count, which
+ * depends on which sub-board is attached.
+ */
+test_export_static void board_usb_pd_count_init(void)
+{
+	switch (uldren_get_sb_type()) {
+	default:
+		cached_usb_pd_port_count = 1;
+		break;
+
+	case ULDREN_SB_C:
+	case ULDREN_SB_C_LTE:
+		cached_usb_pd_port_count = 2;
+		break;
+	}
+}
+/*
+ * Make sure setup is done after EEPROM is readable.
+ */
+DECLARE_HOOK(HOOK_INIT, board_usb_pd_count_init, HOOK_PRIO_INIT_I2C);
+
+static void lte_power_handler(struct ap_power_ev_callback *cb,
+			      struct ap_power_ev_data data)
+{
+	/* Enable rails for S5 */
+	const struct gpio_dt_spec *s5_rail =
+		GPIO_DT_FROM_ALIAS(gpio_en_sub_s5_rails);
+	switch (data.event) {
+	case AP_POWER_PRE_INIT:
+		LOG_DBG("Enabling LTE sub-board power rails");
+		gpio_pin_set_dt(s5_rail, 1);
+		break;
+	case AP_POWER_HARD_OFF:
+		LOG_DBG("Disabling LTE sub-board power rails");
+		gpio_pin_set_dt(s5_rail, 0);
+		break;
+	default:
+		LOG_ERR("Unhandled LTE power event %d", data.event);
+		break;
+	}
+}
+
+/**
+ * Configure GPIOs (and other pin functions) that vary with present sub-board.
+ *
+ * The functions of some pins vary according to which sub-board is present
+ * (indicated by CBI fw_config); this function configures them according to the
+ * needs of the present sub-board.
+ */
+static void uldren_subboard_config(void)
+{
+	enum uldren_sub_board_type sb = uldren_get_sb_type();
+	static struct ap_power_ev_callback power_cb;
+
+	/* Turn off unused pins */
+	gpio_pin_configure_dt(
+		GPIO_DT_FROM_NODELABEL(gpio_sub_usb_a1_ilimit_sdp),
+		GPIO_DISCONNECTED);
+	gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_en_usb_a1_vbus),
+			      GPIO_DISCONNECTED);
+	/* Disable second USB-A port enable GPIO */
+	usb_port_enable[1] = -1;
+
+#if CONFIG_USB_PD_PORT_MAX_COUNT > 1
+	if (sb == ULDREN_SB_C_LTE || sb == ULDREN_SB_C) {
+		/* Configure interrupt input */
+		gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl),
+				      GPIO_INPUT | GPIO_PULL_UP);
+	} else {
+		/* Port doesn't exist, doesn't need muxing */
+		USB_MUX_ENABLE_ALTERNATIVE(usb_mux_chain_1_no_mux);
+	}
+#endif
+
+	switch (sb) {
+	case ULDREN_SB_C:
+		gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_en_sub_s5_rails),
+				      GPIO_OUTPUT_INACTIVE);
+		break;
+	case ULDREN_SB_C_LTE:
+		/*
+		 * LTE: Set up callbacks for enabling/disabling
+		 * sub-board power on S5 state.
+		 */
+		gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_en_sub_s5_rails),
+				      GPIO_OUTPUT_INACTIVE);
+		/* Control LTE power when CPU entering or
+		 * exiting S5 state.
+		 */
+		ap_power_ev_init_callback(&power_cb, lte_power_handler,
+					  AP_POWER_HARD_OFF |
+						  AP_POWER_PRE_INIT);
+		ap_power_ev_add_callback(&power_cb);
+		break;
+
+	default:
+		break;
+	}
+}
+DECLARE_HOOK(HOOK_INIT, uldren_subboard_config, HOOK_PRIO_POST_FIRST);
+
+/*
+ * Enable interrupts
+ */
+static void board_init(void)
+{
+	/*
+	 * Enable USB-C interrupts.
+	 */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0));
+#if CONFIG_USB_PD_PORT_MAX_COUNT > 1
+	if (board_get_usb_pd_port_count() == 2)
+		gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1));
+#endif
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/zephyr/program/nissa/uldren/src/usbc.c b/zephyr/program/nissa/uldren/src/usbc.c
new file mode 100644
index 0000000000..fdd13de04d
--- /dev/null
+++ b/zephyr/program/nissa/uldren/src/usbc.c
@@ -0,0 +1,228 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_state.h"
+#include "chipset.h"
+#include "driver/charger/isl923x_public.h"
+#include "driver/retimer/anx7483_public.h"
+#include "driver/tcpm/raa489000.h"
+#include "driver/tcpm/tcpci.h"
+#include "hooks.h"
+#include "system.h"
+#include "usb_mux.h"
+
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+int board_is_sourcing_vbus(int port)
+{
+	int regval;
+
+	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
+	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int i;
+	int old_port;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	old_port = charge_manager_get_active_charge_port();
+
+	LOG_INF("New chg p%d", port);
+
+	/* Disable all ports. */
+	if (port == CHARGE_PORT_NONE) {
+		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+			tcpc_write(i, TCPC_REG_COMMAND,
+				   TCPC_REG_COMMAND_SNK_CTRL_LOW);
+			raa489000_enable_asgate(i, false);
+		}
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if port is sourcing VBUS. */
+	if (board_is_sourcing_vbus(port)) {
+		LOG_WRN("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		if (i == port)
+			continue;
+
+		if (tcpc_write(i, TCPC_REG_COMMAND,
+			       TCPC_REG_COMMAND_SNK_CTRL_LOW))
+			LOG_WRN("p%d: sink path disable failed.", i);
+		raa489000_enable_asgate(i, false);
+	}
+
+	/*
+	 * Stop the charger IC from switching while changing ports.  Otherwise,
+	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
+	 */
+	if (old_port != CHARGE_PORT_NONE)
+		charger_discharge_on_ac(1);
+
+	/* Enable requested charge port. */
+	if (raa489000_enable_asgate(port, true) ||
+	    tcpc_write(port, TCPC_REG_COMMAND,
+		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
+		LOG_WRN("p%d: sink path enable failed.", port);
+		charger_discharge_on_ac(0);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	/* Allow the charger IC to begin/continue switching. */
+	charger_discharge_on_ac(0);
+
+	return EC_SUCCESS;
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+	int regval;
+
+	/*
+	 * The interrupt line is shared between the TCPC and BC1.2 detector IC.
+	 * Therefore, go out and actually read the alert registers to report the
+	 * alert status.
+	 */
+	if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl))) {
+		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
+			/* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */
+			if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0))
+				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
+
+			if (regval)
+				status |= PD_STATUS_TCPC_ALERT_0;
+		}
+	}
+
+	if (board_get_usb_pd_port_count() == 2 &&
+	    !gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) {
+		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
+			/* TCPCI spec Rev 1.0 says to ignore bits 14:12. */
+			if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0))
+				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
+
+			if (regval)
+				status |= PD_STATUS_TCPC_ALERT_1;
+		}
+	}
+
+	return status;
+}
+
+void pd_power_supply_reset(int port)
+{
+	/* Disable VBUS */
+	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	if (port < 0 || port >= CONFIG_USB_PD_PORT_MAX_COUNT)
+		return;
+
+	raa489000_set_output_current(port, rp);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	if (port >= CONFIG_USB_PD_PORT_MAX_COUNT)
+		return EC_ERROR_INVAL;
+
+	/* Disable charging. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
+	if (rv)
+		return rv;
+
+	/* Our policy is not to source VBUS when the AP is off. */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	/* Provide Vbus. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
+	if (rv)
+		return rv;
+
+	rv = raa489000_enable_asgate(port, true);
+	if (rv)
+		return rv;
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * TODO(b:147316511): could send a reset command to the TCPC here
+	 * if needed.
+	 */
+}
+
+/*
+ * Because the TCPCs and BC1.2 chips share interrupt lines, it's possible
+ * for an interrupt to be lost if one asserts the IRQ, the other does the same
+ * then the first releases it: there will only be one falling edge to trigger
+ * the interrupt, and the line will be held low. We handle this by polling the
+ * IRQ GPIO on the USB-PD task after processing TCPC interrupts, synchronously
+ * running the BC1.2 interrupt handler to ensure we continue processing
+ * interrupts as long as either source is asserting the IRQ.
+ */
+void board_process_pd_alert(int port)
+{
+	const struct gpio_dt_spec *gpio;
+
+	if (port == 0) {
+		gpio = GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl);
+	} else {
+		gpio = GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl);
+	}
+
+	if (!gpio_pin_get_dt(gpio)) {
+		usb_charger_task_set_event_sync(port, USB_CHG_EVENT_BC12);
+	}
+
+	/*
+	 * Immediately schedule another TCPC interrupt if it seems we haven't
+	 * cleared all pending interrupts.
+	 */
+	if (!gpio_pin_get_dt(gpio))
+		schedule_deferred_pd_interrupt(port);
+}
+
+void usb_interrupt(enum gpio_signal signal)
+{
+	int port;
+
+	if (signal == GPIO_SIGNAL(DT_NODELABEL(gpio_usb_c0_int_odl))) {
+		port = 0;
+	} else {
+		port = 1;
+	}
+	/* Trigger polling of TCPC and BC1.2 in USB-PD task */
+	schedule_deferred_pd_interrupt(port);
+}
diff --git a/zephyr/program/nissa/xivu/cbi.dtsi b/zephyr/program/nissa/xivu/cbi.dtsi
new file mode 100644
index 0000000000..798176ddd1
--- /dev/null
+++ b/zephyr/program/nissa/xivu/cbi.dtsi
@@ -0,0 +1,153 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	/* Xivu-specific fw_config fields. */
+	nissa-fw-config {
+		/*
+		 * FW_CONFIG field to enable WFC or not.
+		 */
+		 wfc {
+			enum-name = "FW_WFC";
+			start = <0>;
+			size = <1>;
+
+			wfc-mipi {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_WFC_MIPI";
+				value = <0>;
+			};
+			wfc-absent {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_WFC_ABSENT";
+				value = <1>;
+			};
+		 };
+
+		/*
+		 * FW_CONFIG field to enable stylus or not.
+		 */
+		 stylus {
+			enum-name = "FW_STYLUS";
+			start = <1>;
+			size = <1>;
+
+			stylus-present {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_STYLUS_PRESENT";
+				value = <0>;
+			};
+			stylus-absent {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_STYLUS_ABSENT";
+				value = <1>;
+			};
+		 };
+		/*
+		 * FW_CONFIG field to indicate which sub-board
+		 * is attached.
+		 */
+		sub-board {
+			enum-name = "FW_SUB_BOARD";
+			start = <2>;
+			size = <2>;
+
+			sub-board-1 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_SUB_BOARD_1";
+				value = <0>;
+			};
+			sub-board-2 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_SUB_BOARD_2";
+				value = <1>;
+			};
+			sub-board-3 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_SUB_BOARD_3";
+				value = <2>;
+			};
+		};
+
+		/*
+		 * FW_CONFIG field to defined for AUDIO CODEC.
+		 */
+		audio {
+			enum-name = "FW_AUDIO";
+			start = <8>;
+			size = <1>;
+
+			alc5682_vs {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_AUDIO_CODEC_ALC5682_VS";
+				value = <0>;
+			};
+			alc5682_vd {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_AUDIO_CODEC_ALC5682_VD";
+				value = <1>;
+			};
+		};
+
+/delete-node/ fan;
+	};
+
+	/* Xivu-specific ssfc fields. */
+	cbi-ssfc {
+		compatible = "cros-ec,cbi-ssfc";
+		/*
+		 * SSFC field to identify LID motion sensor.
+		 */
+		lid-sensor {
+			enum-name = "LID_SENSOR";
+			size = <2>;
+
+			lid_sensor_none: none {
+				compatible = "cros-ec,cbi-ssfc-value";
+				status = "okay";
+				value = <0>;
+				default;
+			};
+
+			lid_sensor_lis2dw12: lis2dw12 {
+				compatible = "cros-ec,cbi-ssfc-value";
+				status = "okay";
+				value = <1>;
+				default;
+			};
+			lid_sensor_bma422: bma422 {
+				compatible = "cros-ec,cbi-ssfc-value";
+				status = "okay";
+				value = <2>;
+			};
+		};
+		/*
+		 * SSFC field to identify BASE motion sensor.
+		 */
+		base-sensor {
+			enum-name = "BASE_SENSOR";
+			size = <2>;
+
+			base_sensor_none: none {
+				compatible = "cros-ec,cbi-ssfc-value";
+				status = "okay";
+				value = <0>;
+				default;
+			};
+			base_sensor_lsm6dso: lsm6dso {
+				compatible = "cros-ec,cbi-ssfc-value";
+				status = "okay";
+				value = <1>;
+				default;
+			};
+			base_sensor_bmi323: bmi323 {
+				compatible = "cros-ec,cbi-ssfc-value";
+				status = "okay";
+				value = <2>;
+			};
+		};
+	};
+
+};
diff --git a/zephyr/program/nissa/xivu/generated.dtsi b/zephyr/program/nissa/xivu/generated.dtsi
new file mode 100644
index 0000000000..383054adf8
--- /dev/null
+++ b/zephyr/program/nissa/xivu/generated.dtsi
@@ -0,0 +1,291 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * This file is auto-generated - do not edit!
+ */
+
+/ {
+
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc {
+			enum-name = "ADC_PP1050_PROC";
+			io-channels = <&adc0 4>;
+		};
+		adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 {
+			enum-name = "ADC_PP3300_S5";
+			io-channels = <&adc0 6>;
+		};
+		adc_temp_sensor_1: temp_sensor_1 {
+			enum-name = "ADC_TEMP_SENSOR_1";
+			io-channels = <&adc0 0>;
+		};
+		adc_temp_sensor_2: temp_sensor_2 {
+			enum-name = "ADC_TEMP_SENSOR_2";
+			io-channels = <&adc0 1>;
+		};
+		adc_temp_sensor_3: temp_sensor_3 {
+			enum-name = "ADC_TEMP_SENSOR_3";
+			io-channels = <&adc0 10>;
+		};
+		adc_temp_sensor_4: temp_sensor_4 {
+			enum-name = "ADC_TEMP_SENSOR_4";
+			io-channels = <&adc0 11>;
+		};
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		gpio_acc_int_l: acc_int_l {
+			gpios = <&gpio5 0 GPIO_INPUT>;
+		};
+		gpio_all_sys_pwrgd: all_sys_pwrgd {
+			gpios = <&gpioa 7 GPIO_INPUT>;
+		};
+		gpio_ccd_mode_odl: ccd_mode_odl {
+			gpios = <&gpioe 5 GPIO_INPUT>;
+			enum-name = "GPIO_CCD_MODE_ODL";
+		};
+		gpio_cpu_c10_gate_l: cpu_c10_gate_l {
+			gpios = <&gpio6 7 GPIO_INPUT>;
+		};
+		gpio_ec_battery_pres_odl: ec_battery_pres_odl {
+			gpios = <&gpioa 3 GPIO_INPUT>;
+			enum-name = "GPIO_BATT_PRES_ODL";
+		};
+		gpio_ec_cbi_wp: ec_cbi_wp {
+			gpios = <&gpio7 4 GPIO_OUTPUT>;
+		};
+		gpio_ec_edp_bl_en_od: ec_edp_bl_en_od {
+			gpios = <&gpiod 3 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_ENABLE_BACKLIGHT";
+		};
+		gpio_ec_entering_rw: ec_entering_rw {
+			gpios = <&gpio0 3 GPIO_OUTPUT>;
+			enum-name = "GPIO_ENTERING_RW";
+		};
+		gpio_ec_gsc_packet_mode: ec_gsc_packet_mode {
+			gpios = <&gpio7 5 GPIO_OUTPUT>;
+			enum-name = "GPIO_PACKET_MODE_EN";
+		};
+		gpio_ec_kso_02_inv: ec_kso_02_inv {
+			gpios = <&gpio1 7 (GPIO_OUTPUT | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_ec_pch_wake_odl: ec_pch_wake_odl {
+			gpios = <&gpiob 0 GPIO_ODR_LOW>;
+		};
+		gpio_ec_prochot_odl: ec_prochot_odl {
+			gpios = <&gpiof 1 GPIO_ODR_HIGH>;
+		};
+		gpio_ec_soc_dsw_pwrok: ec_soc_dsw_pwrok {
+			gpios = <&gpio6 1 GPIO_OUTPUT>;
+		};
+		gpio_ec_acok_otg_c1: ec_acok_otg_c1 {
+			gpios = <&gpioe 4 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_int_odl: ec_soc_int_odl {
+			gpios = <&gpio8 0 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_EC_INT_L";
+		};
+		gpio_ec_soc_pch_pwrok_od: ec_soc_pch_pwrok_od {
+			gpios = <&gpio7 2 GPIO_ODR_HIGH>;
+		};
+		gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl {
+			gpios = <&gpioc 1 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_PCH_PWRBTN_L";
+		};
+		gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l {
+			gpios = <&gpioa 6 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_rtcrst: ec_soc_rtcrst {
+			gpios = <&gpio7 6 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_sys_pwrok: ec_soc_sys_pwrok {
+			gpios = <&gpio3 7 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_vccst_pwrgd_od: ec_soc_vccst_pwrgd_od {
+			gpios = <&gpioa 4 GPIO_ODR_HIGH>;
+		};
+		gpio_ec_wp_odl: ec_wp_odl {
+			gpios = <&gpioa 1 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_en_pp3300_s5: en_pp3300_s5 {
+			gpios = <&gpiob 6 GPIO_OUTPUT>;
+			enum-name = "GPIO_TEMP_SENSOR_POWER";
+		};
+		gpio_en_pp5000_pen_x: en_pp5000_pen_x {
+			gpios = <&gpioe 2 GPIO_OUTPUT>;
+		};
+		gpio_en_pp5000_s5: en_pp5000_s5 {
+			gpios = <&gpio4 0 GPIO_OUTPUT>;
+		};
+		gpio_en_slp_z: en_slp_z {
+			gpios = <&gpioe 1 GPIO_OUTPUT>;
+		};
+		gpio_en_usb_a0_vbus: en_usb_a0_vbus {
+			gpios = <&gpio9 1 GPIO_OUTPUT>;
+		};
+		gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl {
+			gpios = <&gpio0 0 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		gpio_ec_acok_otg_c0: ec_acok_otg_c0 {
+			gpios = <&gpioc 6 GPIO_OUTPUT>;
+		};
+		gpio_imu_int_l: imu_int_l {
+			gpios = <&gpio5 6 GPIO_INPUT>;
+		};
+		gpio_imvp91_vrrdy_od: imvp91_vrrdy_od {
+			gpios = <&gpio4 3 GPIO_INPUT>;
+		};
+		gpio_lid_open: lid_open {
+			gpios = <&gpiod 2 GPIO_INPUT>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+		gpio_pen_detect_odl: pen_detect_odl {
+			gpios = <&gpio9 6 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_pg_pp1050_mem_s3_od: pg_pp1050_mem_s3_od {
+			gpios = <&gpiof 0 GPIO_INPUT>;
+		};
+		gpio_pg_pp5000_s5_od: pg_pp5000_s5_od {
+			gpios = <&gpio4 2 GPIO_INPUT>;
+		};
+		gpio_rsmrst_pwrgd_l: rsmrst_pwrgd_l {
+			gpios = <&gpio9 4 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_slp_s0_l: slp_s0_l {
+			gpios = <&gpio9 7 GPIO_INPUT>;
+		};
+		gpio_slp_s3_l: slp_s3_l {
+			gpios = <&gpioa 5 GPIO_INPUT>;
+		};
+		gpio_slp_s4_l: slp_s4_l {
+			gpios = <&gpio7 0 GPIO_INPUT>;
+		};
+		gpio_slp_sus_l: slp_sus_l {
+			gpios = <&gpio6 2 GPIO_INPUT>;
+		};
+		gpio_sub_usb_a1_ilimit_sdp: sub_usb_a1_ilimit_sdp {
+			gpios = <&gpiod 5 GPIO_OUTPUT>;
+			enum-name = "GPIO_USB2_ILIM_SEL";
+		};
+		gpio_sys_rst_odl: sys_rst_odl {
+			gpios = <&gpioc 5 GPIO_ODR_HIGH>;
+		};
+		gpio_tablet_mode_l: tablet_mode_l {
+			gpios = <&gpio9 5 GPIO_INPUT>;
+			enum-name = "GPIO_TABLET_MODE_L";
+		};
+		gpio_usb_a0_ilimit_sdp: usb_a0_ilimit_sdp {
+			gpios = <&gpio3 3 GPIO_OUTPUT>;
+			enum-name = "GPIO_USB1_ILIM_SEL";
+		};
+		gpio_usb_c0_int_odl: usb_c0_int_odl {
+			gpios = <&gpio0 1 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_vccin_aux_vid0: vccin_aux_vid0 {
+			gpios = <&gpio9 2 GPIO_INPUT>;
+		};
+		gpio_vccin_aux_vid1: vccin_aux_vid1 {
+			gpios = <&gpioe 3 GPIO_INPUT>;
+		};
+		gpio_voldn_btn_odl: voldn_btn_odl {
+			gpios = <&gpioa 2 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_DOWN_L";
+		};
+		gpio_volup_btn_odl: volup_btn_odl {
+			gpios = <&gpio9 3 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_UP_L";
+		};
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		i2c_ec_i2c_eeprom: ec_i2c_eeprom {
+			i2c-port = <&i2c0_0>;
+			enum-names = "I2C_PORT_EEPROM";
+		};
+		i2c_ec_i2c_sensor: ec_i2c_sensor {
+			i2c-port = <&i2c1_0>;
+			enum-names = "I2C_PORT_SENSOR";
+		};
+		i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 {
+			i2c-port = <&i2c3_0>;
+			enum-names = "I2C_PORT_USB_C0_TCPC";
+		};
+		i2c_ec_i2c_sub_usb_c1: ec_i2c_sub_usb_c1 {
+			i2c-port = <&i2c5_1>;
+			enum-names = "I2C_PORT_USB_C1_TCPC";
+		};
+		i2c_ec_i2c_batt: ec_i2c_batt {
+			i2c-port = <&i2c7_0>;
+			enum-names = "I2C_PORT_BATTERY";
+		};
+	};
+};
+
+&adc0 {
+	status = "okay";
+	pinctrl-0 = <&adc0_chan0_gp45
+		     &adc0_chan1_gp44
+		     &adc0_chan4_gp41
+		     &adc0_chan6_gp34
+		     &adc0_chan10_gpe0
+		     &adc0_chan11_gpc7>;
+	pinctrl-names = "default";
+};
+
+&i2c0_0 {
+	status = "okay";
+	pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>;
+	pinctrl-names = "default";
+};
+
+&i2c1_0 {
+	status = "okay";
+	pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>;
+	pinctrl-names = "default";
+};
+
+&i2c3_0 {
+	status = "okay";
+	pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>;
+	pinctrl-names = "default";
+};
+
+&i2c5_1 {
+	status = "okay";
+	pinctrl-0 = <&i2c5_1_sda_scl_gpf4_f5>;
+	pinctrl-names = "default";
+};
+
+&i2c7_0 {
+	status = "okay";
+	pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>;
+	pinctrl-names = "default";
+};
+
+&i2c_ctrl0 {
+	status = "okay";
+};
+
+&i2c_ctrl1 {
+	status = "okay";
+};
+
+&i2c_ctrl3 {
+	status = "okay";
+};
+
+&i2c_ctrl5 {
+	status = "okay";
+};
+
+&i2c_ctrl7 {
+	status = "okay";
+};
diff --git a/zephyr/program/nissa/xivu/keyboard.dtsi b/zephyr/program/nissa/xivu/keyboard.dtsi
new file mode 100644
index 0000000000..5248c4aaff
--- /dev/null
+++ b/zephyr/program/nissa/xivu/keyboard.dtsi
@@ -0,0 +1,34 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+&cros_kb_raw {
+	status = "okay";
+	/* No KSO2 (it's inverted and implemented by GPIO) */
+	pinctrl-0 = <
+		&ksi0_gp31
+		&ksi1_gp30
+		&ksi2_gp27
+		&ksi3_gp26
+		&ksi4_gp25
+		&ksi5_gp24
+		&ksi6_gp23
+		&ksi7_gp22
+		&kso00_gp21
+		&kso01_gp20
+		&kso03_gp16
+		&kso04_gp15
+		&kso05_gp14
+		&kso06_gp13
+		&kso07_gp12
+		&kso08_gp11
+		&kso09_gp10
+		&kso10_gp07
+		&kso11_gp06
+		&kso12_gp05
+		&kso13_gp04
+		&kso14_gp82
+	>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/nissa/xivu/led_pins.dtsi b/zephyr/program/nissa/xivu/led_pins.dtsi
new file mode 100644
index 0000000000..40817eada7
--- /dev/null
+++ b/zephyr/program/nissa/xivu/led_pins.dtsi
@@ -0,0 +1,81 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	pwmleds {
+		compatible = "pwm-leds";
+		pwm_led_y_c0: pwm_led_y_c0 {
+			pwms = <&pwm2 0 PWM_HZ(324) PWM_POLARITY_INVERTED>;
+		};
+		pwm_led_w_c0: pwm_led_w_c0 {
+			pwms = <&pwm0 0 PWM_HZ(324) PWM_POLARITY_INVERTED>;
+		};
+		pwm_led_y_c1: pwm_led_y_c1 {
+			pwms = <&pwm6 0 PWM_HZ(324) PWM_POLARITY_INVERTED>;
+		};
+		pwm_led_w_c1: pwm_led_w_c1 {
+			pwms = <&pwm1 0 PWM_HZ(324) PWM_POLARITY_INVERTED>;
+		};
+	};
+
+	pwm-led-pins {
+		compatible = "cros-ec,pwm-led-pins";
+
+		battery_led: battery-led {
+			led-id = "EC_LED_ID_BATTERY_LED";
+			led-pwms = <&pwm_led_y_c0 &pwm_led_y_c1
+				    &pwm_led_w_c0 &pwm_led_w_c1>;
+
+			color_off: color-off {
+				led-color = "LED_OFF";
+				led-values = <0 0 0 0>;
+			};
+
+			color_amber: color-amber {
+				led-color = "LED_AMBER";
+				br-color = "EC_LED_COLOR_AMBER";
+				led-values = <50 50 0 0>;
+			};
+
+			color_white: color-white {
+				led-color = "LED_WHITE";
+				br-color = "EC_LED_COLOR_WHITE";
+				led-values = <0 0 50 50>;
+			};
+		};
+	};
+};
+
+/* LED2 */
+&pwm0 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm0_gpc3>;
+	pinctrl-names = "default";
+};
+
+/* LED3 */
+&pwm1 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm1_gpc2>;
+	pinctrl-names = "default";
+};
+
+/* LED1 */
+&pwm2 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm2_gpc4>;
+	pinctrl-names = "default";
+};
+
+/* LED0 */
+&pwm6 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm6_gpc0>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/nissa/xivu/led_policy.dtsi b/zephyr/program/nissa/xivu/led_policy.dtsi
new file mode 100644
index 0000000000..9f66e38d57
--- /dev/null
+++ b/zephyr/program/nissa/xivu/led_policy.dtsi
@@ -0,0 +1,122 @@
+/ {
+	led-colors {
+		compatible = "cros-ec,led-policy";
+
+		power-state-charge {
+			charge-state = "LED_PWRS_CHARGE";
+			/* Battery percent range (>= Empty, <= 94%) */
+			batt-lvl = <0 94>;
+
+			color-0 {
+				led-color = <&color_amber>;
+			};
+		};
+
+		power-state-charge-lvl-2 {
+			charge-state = "LED_PWRS_CHARGE";
+			/* Battery percent range (>= 95%, <= 100%) */
+			batt-lvl = <95 100>;
+
+			color-0 {
+				led-color = <&color_white>;
+			};
+		};
+
+		power-state-near-full {
+			charge-state = "LED_PWRS_CHARGE_NEAR_FULL";
+
+			color-0 {
+				led-color = <&color_white>;
+			};
+		};
+
+		power-state-discharge-s0 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S0";
+			/* Battery percent range (>= 11%, <= Full) */
+			batt-lvl = <11 100>;
+
+			color-0 {
+				led-color = <&color_white>;
+			};
+		};
+
+		power-state-discharge-s3 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S3";
+
+			/* White 1 sec, off 3 sec */
+			color-0 {
+				led-color = <&color_white>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <3000>;
+			};
+		};
+
+		power-state-discharge-s5 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S5";
+
+			color-0 {
+				led-color = <&color_off>;
+			};
+		};
+
+		power-state-discharge-s0-batt-low {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S0";
+			/* Battery percent range (>= Empty, <= 10%) */
+			batt-lvl = <0 10>;
+
+			/* Amber 1 sec, off 3 sec */
+			color-0 {
+				led-color = <&color_amber>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <3000>;
+			};
+		};
+
+		power-state-error-s0 {
+			charge-state = "LED_PWRS_ERROR";
+			chipset-state = "POWER_S0";
+			/* Amber 1 sec, off 1 sec */
+			color-0 {
+				led-color = <&color_amber>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <1000>;
+			};
+		};
+
+		power-state-error-s3 {
+			charge-state = "LED_PWRS_ERROR";
+			chipset-state = "POWER_S3";
+			/* White 1 sec, off 3 sec */
+			color-0 {
+				led-color = <&color_white>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <3000>;
+			};
+		};
+
+		power-state-error-s5 {
+			charge-state = "LED_PWRS_ERROR";
+			chipset-state = "POWER_S5";
+
+			color-0 {
+				led-color = <&color_off>;
+			};
+		};
+	};
+};
diff --git a/zephyr/program/nissa/xivu/motionsense.dtsi b/zephyr/program/nissa/xivu/motionsense.dtsi
new file mode 100644
index 0000000000..055bc545ca
--- /dev/null
+++ b/zephyr/program/nissa/xivu/motionsense.dtsi
@@ -0,0 +1,252 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/motionsense/utils.h>
+
+
+/ {
+	aliases {
+		/*
+		 * Interrupt bindings for sensor devices.
+		 */
+		lsm6dso-int = &base_accel;
+		lis2dw12-int = &lid_accel;
+		bmi3xx-int = &base_accel;
+		bma4xx-int = &lid_accel;
+	};
+
+	/*
+	 * Declare mutexes used by sensor drivers.
+	 * A mutex node is used to create an instance of mutex_t.
+	 * A mutex node is referenced by a sensor node if the
+	 * corresponding sensor driver needs to use the
+	 * instance of the mutex.
+	 */
+	motionsense-mutex {
+		compatible = "cros-ec,motionsense-mutex";
+		lid_mutex: lid-mutex {
+		};
+
+		lid_mutex_bma422: bma422-mutex {
+		};
+
+		base_mutex: base-mutex {
+		};
+
+		base_mutex_bmi323: bmi323-mutex {
+		};
+	};
+
+	/* Rotation matrix used by drivers. */
+	motionsense-rotation-ref {
+		compatible = "cros-ec,motionsense-rotation-ref";
+		lid_rot_ref: lid-rotation-ref {
+			mat33 = <0 1 0
+				 1 0 0
+				 0 0 (-1)>;
+		};
+
+		base_rot_ref: base-rotation-ref {
+			mat33 = <0 1 0
+				 (-1) 0 0
+				 0 0 1>;
+		};
+
+		lid_rot_bma422: lid-rotation-bma {
+			mat33 = <0 (-1) 0
+				 (-1) 0 0
+				 0 0 (-1)>;
+		};
+
+		base_rot_ref_bmi: base-rotation-ref-bmi {
+			mat33 = <(-1) 0 0
+				 0 (-1) 0
+				 0 0 1>;
+		};
+	};
+
+	/*
+	 * Driver specific data. A driver-specific data can be shared with
+	 * different motion sensors while they are using the same driver.
+	 *
+	 * If a node's compatible starts with "cros-ec,accelgyro-", it is for
+	 * a common structure defined in accelgyro.h.
+	 * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for
+	 * "struct als_drv_data_t" in accelgyro.h
+	 */
+	motionsense-sensor-data {
+		lsm6dso_accel_data: lsm6dso-accel-drv-data {
+			compatible = "cros-ec,drvdata-lsm6dso";
+			status = "okay";
+		};
+
+		lsm6dso_gyro_data: lsm6dso-gyro-drv-data {
+			compatible = "cros-ec,drvdata-lsm6dso";
+			status = "okay";
+		};
+
+		lis2dw12_data: lis2dw12-drv-data {
+			compatible = "cros-ec,drvdata-lis2dw12";
+			status = "okay";
+		};
+
+		bma422_data: bma4xx-drv-data {
+			compatible = "cros-ec,drvdata-bma4xx";
+			status = "okay";
+		};
+
+		bmi323_data: bmi323-drv-data {
+			compatible = "cros-ec,drvdata-bmi3xx";
+			status = "okay";
+		};
+	};
+
+	/*
+	 * List of motion sensors that creates motion_sensors array.
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
+	 * motion sensor IDs for lid angle calculation.
+	 * TODO(b/238139272): The first entries of the array must be
+	 * accelerometers,then gyroscope. Fix this dependency in the DTS
+	 * processing which makes the devicetree entries independent.
+	 */
+	motionsense-sensor {
+		lid_accel: lid-accel {
+			compatible = "cros-ec,lis2dw12";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&lid_mutex>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&lid_rot_ref>;
+			default-range = <2>;
+			drv-data = <&lis2dw12_data>;
+			i2c-spi-addr-flags = "LIS2DWL_ADDR0_FLAGS";
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_accel: base-accel {
+			compatible = "cros-ec,lsm6dso-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&lsm6dso_accel_data>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_gyro: base-gyro {
+			compatible = "cros-ec,lsm6dso-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			default-range = <(1000 | ROUND_UP_FLAG)>; /* dps */
+			drv-data = <&lsm6dso_gyro_data>;
+		};
+	};
+
+	motionsense-sensor-alt {
+		alt_lid_accel: alt-lid-accel {
+			compatible = "cros-ec,bma4xx";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&lid_mutex_bma422>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&lid_rot_bma422>;
+			default-range = <2>;
+			drv-data = <&bma422_data>;
+			i2c-spi-addr-flags = "BMA4_I2C_ADDR_PRIMARY";
+			alternate-for = <&lid_accel>;
+			alternate-ssfc-indicator = <&lid_sensor_bma422>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		alt_base_accel: alt-base-accel {
+			compatible = "cros-ec,bmi3xx-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex_bmi323>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref_bmi>;
+			drv-data = <&bmi323_data>;
+			alternate-for = <&base_accel>;
+			alternate-ssfc-indicator = <&base_sensor_bmi323>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		alt_base_gyro: alt-base-gyro {
+			compatible = "cros-ec,bmi3xx-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex_bmi323>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref_bmi>;
+			drv-data = <&bmi323_data>;
+			alternate-for = <&base_gyro>;
+			alternate-ssfc-indicator = <&base_sensor_bmi323>;
+		};
+	};
+
+	motionsense-sensor-info {
+		compatible = "cros-ec,motionsense-sensor-info";
+
+		/*
+		 * list of GPIO interrupts that have to
+		 * be enabled at initial stage
+		 */
+		sensor-irqs = <&int_imu>;
+		/* list of sensors in force mode */
+		accel-force-mode-sensors = <&lid_accel>;
+	};
+};
diff --git a/zephyr/program/nissa/xivu/overlay.dtsi b/zephyr/program/nissa/xivu/overlay.dtsi
new file mode 100644
index 0000000000..bd5f84a72a
--- /dev/null
+++ b/zephyr/program/nissa/xivu/overlay.dtsi
@@ -0,0 +1,405 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <cros/thermistor/thermistor.dtsi>
+#include <dt-bindings/usbc_mux.h>
+#include <dt-bindings/usb_pd_tcpm.h>
+
+/ {
+	aliases {
+		gpio-cbi-wp = &gpio_ec_cbi_wp;
+		gpio-wp = &gpio_ec_wp_odl;
+		int-wp = &int_wp_l;
+		gpio-kbd-kso2 = &gpio_ec_kso_02_inv;
+	};
+
+	ec-console {
+		compatible = "ec-console";
+		disabled = "events", "lpc", "hostcmd";
+	};
+
+	batteries {
+		default_battery: smp_c31n2005 {
+			compatible = "smp,c31n2005", "battery-smart";
+		};
+	};
+
+	hibernate-wake-pins {
+		compatible = "cros-ec,hibernate-wake-pins";
+		wakeup-irqs = <
+			&int_power_button
+			&int_lid_open
+		>;
+	};
+
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_power_button: power_button {
+			irq-pin = <&gpio_gsc_ec_pwr_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_button_interrupt";
+		};
+		int_wp_l: wp_l {
+			irq-pin = <&gpio_ec_wp_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "switch_interrupt";
+		};
+		int_lid_open: lid_open {
+			irq-pin = <&gpio_lid_open>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "lid_interrupt";
+		};
+		int_tablet_mode: tablet_mode {
+			irq-pin = <&gpio_tablet_mode_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "gmr_tablet_switch_isr";
+		};
+		int_imu: ec_imu {
+			irq-pin = <&gpio_imu_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "motion_interrupt";
+		};
+		int_lid_accel: ec_lid_accel {
+			irq-pin = <&gpio_acc_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "lid_accel_interrupt";
+		};
+		int_vol_down: vol_down {
+			irq-pin = <&gpio_voldn_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+		int_vol_up: vol_up {
+			irq-pin = <&gpio_volup_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+		int_usb_c0: usb_c0 {
+			irq-pin = <&gpio_usb_c0_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "usb_interrupt";
+		};
+		int_usb_c1: usb_c1 {
+			irq-pin = <&gpio_sb_1>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "usb_interrupt";
+		};
+	};
+
+	named-gpios {
+		gpio_sb_1: sb-1 {
+			gpios = <&gpio0 2 GPIO_PULL_UP>;
+			no-auto-init;
+		};
+
+		gpio_sb_2: sb-2 {
+			gpios = <&gpiod 4 GPIO_OUTPUT>;
+			no-auto-init;
+		};
+
+		/*
+		 * Set I2C pins for type C sub-board to be low voltage (I2C5_1).
+		 * We do this for all boards, since the pins are 3.3V tolerant,
+		 * and the only 2 types of sub-boards used on nivviks both have
+		 * type-C ports on them.
+		 */
+		gpio_sb_3: sb-3 {
+			gpios = <&gpiof 4 (GPIO_OPEN_DRAIN | GPIO_VOLTAGE_1P8)>;
+			no-auto-init;
+		};
+		gpio_sb_4: sb-4 {
+			gpios = <&gpiof 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+			no-auto-init;
+		};
+	};
+
+	/*
+	 * Aliases used for sub-board GPIOs.
+	 */
+	aliases {
+		/*
+		 * Input GPIO when used with type-C port 1
+		 */
+		gpio-usb-c1-int-odl = &gpio_sb_1;
+		gpio-en-rails-odl = &gpio_sb_1;
+		/*
+		 * Sub-board with type A USB, enable.
+		 */
+		gpio-en-usb-a1-vbus = &gpio_sb_2;
+		/*
+		 * Enable S5 rails for LTE sub-board
+		 */
+		gpio-en-sub-s5-rails = &gpio_sb_2;
+	};
+
+	temp_memory: memory {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_1>;
+	};
+	temp_ambient: ambient {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_2>;
+	};
+	temp_charger1: charger1 {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_3>;
+	};
+	temp_charger2: charger2 {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_4>;
+	};
+
+	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
+		memory {
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			temp_host_release_halt = <80>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_memory>;
+		};
+		ambient {
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			temp_host_release_halt = <80>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_ambient>;
+		};
+		charger1 {
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			temp_host_release_halt = <80>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_charger1>;
+		};
+		charger2 {
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			temp_host_release_halt = <80>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_charger2>;
+		};
+	};
+
+	usba {
+		compatible = "cros-ec,usba-port-enable-pins";
+		/*
+		 * sb_2 is only configured as GPIO when USB-A1 is present,
+		 * but it's still safe to control when disabled.
+		 *
+		 * ILIM_SEL pins are referred to by legacy enum name,
+		 * GPIO_USB*_ILIM_SEL. The one for port A1 is unused on
+		 * sub-boards that don't have USB-A so is safe to control
+		 * regardless of system configuration.
+		 */
+		enable-pins = <&gpio_en_usb_a0_vbus &gpio_sb_2>;
+		status = "okay";
+	};
+
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+			bc12 = <&bc12_port0>;
+			chg = <&chg_port0>;
+			tcpc = <&tcpc_port0>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_0>;
+			};
+		};
+		port0-muxes {
+			virtual_mux_0: virtual-mux-0 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+		/*
+		 * TODO(b:211693800): port1 may not be present on some
+		 * sub-boards.
+		 */
+		port1@1 {
+			compatible = "named-usbc-port";
+			reg = <1>;
+			bc12 = <&bc12_port1>;
+			chg = <&chg_port1>;
+			tcpc = <&tcpc_port1>;
+			usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_1 &anx7483_mux_1>;
+			};
+			usb_mux_chain_1_no_mux: usb-mux-chain-1-no-mux {
+				compatible = "cros-ec,usb-mux-chain";
+				alternative-chain;
+				usb-muxes = <&virtual_mux_1>;
+			};
+		};
+		port1-muxes {
+			virtual_mux_1: virtual-mux-1 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+	};
+
+	unused-pins {
+		compatible = "unused-gpios";
+		unused-gpios =
+			<&gpio3 2 0>,
+			<&gpio3 5 0>,
+			<&gpio3 6 0>,
+			<&gpio5 7 0>,
+			<&gpio6 0 0>,
+			<&gpio6 3 0>,
+			<&gpio7 3 0>,
+			<&gpio8 1 0>,
+			<&gpio8 3 0>,
+			<&gpio8 5 0>,
+			<&gpio8 6 0>,
+			<&gpioa 0 0>,
+			<&gpiob 1 0>,
+			<&gpiob 7 0>,
+			<&gpiod 7 0>,
+			<&gpioc 7 0>,
+			<&gpiof 2 0>,
+			<&gpiof 3 0>;
+	 };
+};
+
+&thermistor_3V3_51K1_47K_4050B {
+	status = "okay";
+};
+
+&adc_ec_vsense_pp3300_s5 {
+	/*
+	 * Voltage divider on input has 47k upper and 220k lower legs with
+	 * 2714 mV full-scale reading on the ADC. Apply the largest possible
+	 * multiplier (without overflowing int32) to get the best possible
+	 * approximation of the actual ratio, but derate by a factor of two to
+	 * ensure unexpectedly high values won't overflow.
+	 */
+	mul = <(791261 / 2)>;
+	div = <(651975 / 2)>;
+};
+
+/* Set bus speeds for I2C */
+&i2c0_0 {
+	label = "I2C_EEPROM";
+	clock-frequency = <I2C_BITRATE_FAST>;
+
+	cbi_eeprom: eeprom@50 {
+		compatible = "atmel,at24";
+		reg = <0x50>;
+		size = <2048>;
+		pagesize = <16>;
+		address-width = <8>;
+		timeout = <5>;
+	};
+};
+
+&i2c1_0 {
+	label = "I2C_SENSOR";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&i2c3_0 {
+	label = "I2C_USB_C0_TCPC";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+
+	bc12_port0: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+		/*
+		 * BC1.2 interrupt is shared with TCPC, so
+		 * IRQ is not specified here and handled by
+		 * usb_c0_interrupt.
+		 */
+	};
+
+	chg_port0: isl923x@9 {
+		compatible = "intersil,isl923x";
+		status = "okay";
+		reg = <0x9>;
+	};
+
+	tcpc_port0: raa489000@22 {
+		compatible = "renesas,raa489000";
+		reg = <0x22>;
+		tcpc-flags = <(
+			TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_VBUS_MONITOR)>;
+	};
+};
+
+&i2c5_1 {
+	label = "I2C_SUB_C1_TCPC";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+
+	bc12_port1: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+	};
+
+	chg_port1: isl923x@9 {
+		compatible = "intersil,isl923x";
+		status = "okay";
+		reg = <0x9>;
+	};
+
+	tcpc_port1: raa489000@22 {
+		compatible = "renesas,raa489000";
+		reg = <0x22>;
+		tcpc-flags = <(
+			TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_VBUS_MONITOR)>;
+	};
+
+	anx7483_mux_1: anx7483-mux-1@3e {
+		compatible = "analogix,anx7483";
+		reg = <0x3e>;
+		board-set = "anx7483_set_default_tuning";
+		flags = <USB_MUX_FLAG_RESETS_IN_G3>;
+	};
+};
+
+&i2c7_0 {
+	label = "I2C_BATTERY";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+};
+
+&pwm6 {
+	status = "okay";
+	pinctrl-0 = <&pwm6_gpc0>;
+	pinctrl-names = "default";
+};
+
+/* host interface */
+&espi0 {
+	status = "okay";
+	pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>;
+	pinctrl-names = "default";
+};
+
+/*
+ * Declare GPIOs that have leakage current caused by board issues here. NPCX ec
+ * will disable their input buffers before entering deep sleep and restore them
+ * after waking up automatically for better power consumption.
+ */
+&power_leakage_io {
+	leak-gpios = <&gpioa 4 GPIO_OPEN_DRAIN
+		      &gpiof 1 GPIO_OPEN_DRAIN>;
+};
diff --git a/zephyr/program/nissa/xivu/power_signals.dtsi b/zephyr/program/nissa/xivu/power_signals.dtsi
new file mode 100644
index 0000000000..1d2b23069d
--- /dev/null
+++ b/zephyr/program/nissa/xivu/power_signals.dtsi
@@ -0,0 +1,220 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	chosen {
+		intel-ap-pwrseq,espi = &espi0;
+	};
+
+	common-pwrseq {
+		compatible = "intel,ap-pwrseq";
+
+		sys-pwrok-delay = <10>;
+		all-sys-pwrgd-timeout = <20>;
+	};
+
+	pwr-en-pp5000-s5 {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PP5000_S5 enable output to regulator";
+		enum-name = "PWR_EN_PP5000_A";
+		gpios = <&gpio4 0 0>;
+		output;
+	};
+	pwr-en-pp3300-s5 {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PP3300_S5 enable output to LS";
+		enum-name = "PWR_EN_PP3300_A";
+		gpios = <&gpiob 6 0>;
+		output;
+	};
+	pwr-pg-ec-rsmrst-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST power good from regulator";
+		enum-name = "PWR_RSMRST";
+		gpios = <&gpio9 4 0>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-ec-pch-rsmrst-odl {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST output to PCH";
+		enum-name = "PWR_EC_PCH_RSMRST";
+		gpios = <&gpioa 6 0>;
+		output;
+	};
+	pwr-slp-s0-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_S0_L input from PCH";
+		enum-name = "PWR_SLP_S0";
+		gpios = <&gpio9 7 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-slp-s3-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_S3_L input from PCH";
+		enum-name = "PWR_SLP_S3";
+		gpios = <&gpioa 5 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-slp-sus-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_SUS_L input from PCH";
+		enum-name = "PWR_SLP_SUS";
+		gpios = <&gpio6 2 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-ec-soc-dsw-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "DSW_PWROK output to PCH";
+		enum-name = "PWR_EC_SOC_DSW_PWROK";
+		gpios = <&gpio6 1 0>;
+		output;
+	};
+	pwr-vccst-pwrgd-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "VCCST_PWRGD output to PCH";
+		enum-name = "PWR_VCCST_PWRGD";
+		gpios = <&gpioa 4 GPIO_OPEN_DRAIN>;
+		output;
+	};
+	pwr-imvp9-vrrdy-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "VRRDY input from IMVP9";
+		enum-name = "PWR_IMVP9_VRRDY";
+		gpios = <&gpio4 3 0>;
+	};
+	pwr-pch-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PCH_PWROK output to PCH";
+		enum-name = "PWR_PCH_PWROK";
+		gpios = <&gpio7 2 GPIO_OPEN_DRAIN>;
+		output;
+	};
+	pwr-ec-pch-sys-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_PWROK output to PCH";
+		enum-name = "PWR_EC_PCH_SYS_PWROK";
+		gpios = <&gpio3 7 0>;
+		output;
+	};
+	pwr-sys-rst-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_RESET# output to PCH";
+		enum-name = "PWR_SYS_RST";
+		gpios = <&gpioc 5 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>;
+		output;
+	};
+	pwr-slp-s4 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S4 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S4";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4";
+		vw-invert;
+	};
+	pwr-slp-s5 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S5 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S5";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5";
+		vw-invert;
+	};
+	pwr-all-sys-pwrgd {
+		compatible = "intel,ap-pwrseq-external";
+		dbg-label = "Combined all power good";
+		enum-name = "PWR_ALL_SYS_PWRGD";
+	};
+	pwr-adc-pp3300 {
+		compatible = "intel,ap-pwrseq-adc";
+		dbg-label = "PP3300 PWROK (from ADC)";
+		enum-name = "PWR_DSW_PWROK";
+		trigger-high = <&cmp_pp3300_s5_high>;
+		trigger-low = <&cmp_pp3300_s5_low>;
+	};
+	pwr-adc-pp1p05 {
+		compatible = "intel,ap-pwrseq-adc";
+		dbg-label = "PP1P05 PWROK (from ADC)";
+		enum-name = "PWR_PG_PP1P05";
+		trigger-high = <&cmp_pp1p05_high>;
+		trigger-low = <&cmp_pp1p05_low>;
+	};
+
+	adc-cmp {
+		cmp_pp3300_s5_high: pp3300_high {
+			compatible = "nuvoton,adc-cmp";
+			io-channels = <&adc0 6>;
+			comparison = "ADC_CMP_NPCX_GREATER";
+			/*
+			 * This is 90% of nominal voltage considering voltage
+			 * divider on ADC input.
+			 */
+			threshold-mv = <2448>;
+		};
+		cmp_pp3300_s5_low: pp3300_low {
+			compatible = "nuvoton,adc-cmp";
+			io-channels = <&adc0 6>;
+			comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL";
+			threshold-mv = <2448>;
+		};
+		cmp_pp1p05_high: pp1p05_high {
+			compatible = "nuvoton,adc-cmp";
+			io-channels = <&adc0 4>;
+			comparison = "ADC_CMP_NPCX_GREATER";
+			/* Setting at 90% of nominal voltage */
+			threshold-mv = <945>;
+		};
+		cmp_pp1p05_low: pp1p05_low {
+			compatible = "nuvoton,adc-cmp";
+			io-channels = <&adc0 4>;
+			comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL";
+			threshold-mv = <945>;
+		};
+	};
+};
+
+/*
+ * Because the power signals directly reference the GPIOs,
+ * the correspinding named-gpios need to have no-auto-init set.
+ */
+&gpio_ec_soc_dsw_pwrok {
+	no-auto-init;
+};
+&gpio_ec_soc_pch_pwrok_od {
+	no-auto-init;
+};
+&gpio_ec_soc_rsmrst_l {
+	no-auto-init;
+};
+&gpio_ec_soc_sys_pwrok {
+	no-auto-init;
+};
+&gpio_ec_soc_vccst_pwrgd_od {
+	no-auto-init;
+};
+&gpio_en_pp3300_s5 {
+	no-auto-init;
+};
+&gpio_en_pp5000_s5 {
+	no-auto-init;
+};
+&gpio_imvp91_vrrdy_od {
+	no-auto-init;
+};
+&gpio_rsmrst_pwrgd_l {
+	no-auto-init;
+};
+&gpio_slp_s0_l {
+	no-auto-init;
+};
+&gpio_slp_s3_l {
+	no-auto-init;
+};
+&gpio_slp_s4_l {
+	no-auto-init;
+};
+&gpio_slp_sus_l {
+	no-auto-init;
+};
+&gpio_sys_rst_odl {
+	no-auto-init;
+};
diff --git a/zephyr/program/nissa/xivu/project.conf b/zephyr/program/nissa/xivu/project.conf
new file mode 100644
index 0000000000..0c5aeb7b4d
--- /dev/null
+++ b/zephyr/program/nissa/xivu/project.conf
@@ -0,0 +1,28 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_BOARD_XIVU=y
+CONFIG_PLATFORM_EC_OCPC=y
+
+CONFIG_PLATFORM_EC_CHARGER_INPUT_CURRENT_DERATE_PCT=10
+
+# USBC
+CONFIG_PLATFORM_EC_PD_MAX_POWER_MW=45000
+
+# Battery
+CONFIG_PLATFORM_EC_CHARGER_PROFILE_OVERRIDE=y
+
+# Montionsense
+CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y
+CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSO=y
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y
+CONFIG_PLATFORM_EC_DYNAMIC_MOTION_SENSOR_COUNT=y
+
+# Both ports use a SLGC55545 smart switch with CTL1..3 fixed high,
+# for SDP2 or CDP only.
+CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART=y
+CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_CDP_SDP_ONLY=y
+CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_DEFAULT_CDP=y
+CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_INVERTED=y
diff --git a/zephyr/program/nissa/xivu/project.overlay b/zephyr/program/nissa/xivu/project.overlay
new file mode 100644
index 0000000000..a7c5b7e9e7
--- /dev/null
+++ b/zephyr/program/nissa/xivu/project.overlay
@@ -0,0 +1,15 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "../cbi.dtsi"
+
+#include "cbi.dtsi"
+#include "generated.dtsi"
+#include "keyboard.dtsi"
+#include "led_pins.dtsi"
+#include "led_policy.dtsi"
+#include "motionsense.dtsi"
+#include "overlay.dtsi"
+#include "power_signals.dtsi"
diff --git a/zephyr/program/nissa/xivu/src/charger.c b/zephyr/program/nissa/xivu/src/charger.c
new file mode 100644
index 0000000000..50facd4709
--- /dev/null
+++ b/zephyr/program/nissa/xivu/src/charger.c
@@ -0,0 +1,68 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "charger.h"
+#include "charger/isl923x_public.h"
+#include "console.h"
+#include "extpower.h"
+#include "usb_pd.h"
+
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+int extpower_is_present(void)
+{
+	int port;
+	int rv;
+	bool acok;
+
+	for (port = 0; port < board_get_usb_pd_port_count(); port++) {
+		rv = raa489000_is_acok(port, &acok);
+		if ((rv == EC_SUCCESS) && acok)
+			return 1;
+	}
+
+	return 0;
+}
+
+/*
+ * Xivu does not have a GPIO indicating whether extpower is present,
+ * so detect using the charger(s).
+ */
+__override void board_check_extpower(void)
+{
+	static int last_extpower_present;
+	int extpower_present_p0 = 0;
+	int extpower_present_p1 = 0;
+
+	int extpower_present = extpower_is_present();
+
+	if (last_extpower_present ^ extpower_present)
+		extpower_handle_update(extpower_present);
+
+	last_extpower_present = extpower_present;
+
+	if (pd_is_connected(0))
+		extpower_present_p0 = extpower_is_present();
+	else if (pd_is_connected(1))
+		extpower_present_p1 = extpower_is_present();
+
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_acok_otg_c0),
+			extpower_present_p0);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_acok_otg_c1),
+			extpower_present_p1);
+}
+
+__override void board_hibernate(void)
+{
+	/* Shut down the chargers */
+	if (board_get_usb_pd_port_count() == 2)
+		raa489000_hibernate(CHARGER_SECONDARY, true);
+	raa489000_hibernate(CHARGER_PRIMARY, true);
+	LOG_INF("Charger(s) hibernated");
+	cflush();
+}
diff --git a/zephyr/program/nissa/xivu/src/form_factor.c b/zephyr/program/nissa/xivu/src/form_factor.c
new file mode 100644
index 0000000000..bfb3eee466
--- /dev/null
+++ b/zephyr/program/nissa/xivu/src/form_factor.c
@@ -0,0 +1,98 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "accelgyro.h"
+#include "button.h"
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+#include "driver/accel_bma4xx.h"
+#include "driver/accel_lis2dw12_public.h"
+#include "driver/accelgyro_bmi323.h"
+#include "driver/accelgyro_lsm6dso.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "motion_sense.h"
+#include "motionsense_sensors.h"
+#include "tablet_mode.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+enum motionsense_type {
+	motion_none = 0,
+	motion_bmi323,
+	motion_lsm6dso,
+};
+
+enum lid_accel_type {
+	lid_none = 0,
+	lid_bma422,
+	lid_lis2dw12,
+};
+
+static int use_sensor = motion_bmi323;
+static int use_lid_accel = lid_bma422;
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	if (use_sensor == motion_bmi323)
+		bmi3xx_interrupt(signal);
+	else if (use_sensor == motion_lsm6dso)
+		lsm6dso_interrupt(signal);
+}
+
+void lid_accel_interrupt(enum gpio_signal signal)
+{
+	if (use_lid_accel == lid_bma422)
+		bma4xx_interrupt(signal);
+	else if (use_lid_accel == lid_lis2dw12)
+		lis2dw12_interrupt(signal);
+}
+
+static void form_factor_init(void)
+{
+	if (cros_cbi_ssfc_check_match(
+		    CBI_SSFC_VALUE_ID(DT_NODELABEL(base_sensor_bmi323)))) {
+		use_sensor = motion_bmi323;
+		MOTIONSENSE_ENABLE_ALTERNATE(alt_base_accel);
+		MOTIONSENSE_ENABLE_ALTERNATE(alt_base_gyro);
+		ccprints("BASE ACCEL IS BMI323");
+	} else if (cros_cbi_ssfc_check_match(CBI_SSFC_VALUE_ID(
+			   DT_NODELABEL(base_sensor_lsm6dso)))) {
+		use_sensor = motion_lsm6dso;
+		ccprints("BASE ACCEL IS LSM6DSO");
+	} else {
+		use_sensor = motion_none;
+		ccprints("no motionsense");
+	}
+
+	if (cros_cbi_ssfc_check_match(
+		    CBI_SSFC_VALUE_ID(DT_NODELABEL(lid_sensor_bma422)))) {
+		use_lid_accel = lid_bma422;
+		MOTIONSENSE_ENABLE_ALTERNATE(alt_lid_accel);
+		ccprints("LID SENSOR IS BMA422");
+	} else if (cros_cbi_ssfc_check_match(CBI_SSFC_VALUE_ID(
+			   DT_NODELABEL(lid_sensor_lis2dw12)))) {
+		use_lid_accel = lid_lis2dw12;
+		ccprints("LID SENSOR IS LIS2DW12");
+	} else {
+		use_lid_accel = lid_none;
+		ccprints("no lid sensor");
+	}
+
+	if (use_sensor && use_lid_accel) {
+		motion_sensors_check_ssfc();
+	} else {
+		motion_sensor_count = 0;
+		gmr_tablet_switch_disable();
+		gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_imu));
+		gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_imu_int_l),
+				      GPIO_DISCONNECTED);
+		ccprints("Clamshell: disable motionsense function.");
+	}
+}
+DECLARE_HOOK(HOOK_INIT, form_factor_init, HOOK_PRIO_POST_I2C);
diff --git a/zephyr/program/nissa/xivu/src/keyboard.c b/zephyr/program/nissa/xivu/src/keyboard.c
new file mode 100644
index 0000000000..ef799fb1d2
--- /dev/null
+++ b/zephyr/program/nissa/xivu/src/keyboard.c
@@ -0,0 +1,29 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+
+static const struct ec_response_keybd_config xivu_kb_legacy = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* 8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &xivu_kb_legacy;
+}
diff --git a/zephyr/program/nissa/xivu/src/usbc.c b/zephyr/program/nissa/xivu/src/usbc.c
new file mode 100644
index 0000000000..d77abf37db
--- /dev/null
+++ b/zephyr/program/nissa/xivu/src/usbc.c
@@ -0,0 +1,320 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_state.h"
+#include "chipset.h"
+#include "driver/charger/isl923x_public.h"
+#include "driver/retimer/anx7483_public.h"
+#include "driver/tcpm/raa489000.h"
+#include "driver/tcpm/tcpci.h"
+#include "hooks.h"
+#include "system.h"
+#include "temp_sensor/temp_sensor.h"
+#include "usb_mux.h"
+
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+int board_is_sourcing_vbus(int port)
+{
+	int regval;
+
+	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
+	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int i;
+	int old_port;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	old_port = charge_manager_get_active_charge_port();
+
+	LOG_INF("New chg p%d", port);
+
+	/* Disable all ports. */
+	if (port == CHARGE_PORT_NONE) {
+		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+			tcpc_write(i, TCPC_REG_COMMAND,
+				   TCPC_REG_COMMAND_SNK_CTRL_LOW);
+			raa489000_enable_asgate(i, false);
+		}
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if port is sourcing VBUS. */
+	if (board_is_sourcing_vbus(port)) {
+		LOG_WRN("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		if (i == port)
+			continue;
+
+		if (tcpc_write(i, TCPC_REG_COMMAND,
+			       TCPC_REG_COMMAND_SNK_CTRL_LOW))
+			LOG_WRN("p%d: sink path disable failed.", i);
+		raa489000_enable_asgate(i, false);
+	}
+
+	/*
+	 * Stop the charger IC from switching while changing ports.  Otherwise,
+	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
+	 */
+	if (old_port != CHARGE_PORT_NONE)
+		charger_discharge_on_ac(1);
+
+	/* Enable requested charge port. */
+	if (raa489000_enable_asgate(port, true) ||
+	    tcpc_write(port, TCPC_REG_COMMAND,
+		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
+		LOG_WRN("p%d: sink path enable failed.", port);
+		charger_discharge_on_ac(0);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	/* Allow the charger IC to begin/continue switching. */
+	charger_discharge_on_ac(0);
+
+	return EC_SUCCESS;
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+	int regval;
+
+	/*
+	 * The interrupt line is shared between the TCPC and BC1.2 detector IC.
+	 * Therefore, go out and actually read the alert registers to report the
+	 * alert status.
+	 */
+	if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl))) {
+		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
+			/* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */
+			if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0))
+				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
+
+			if (regval)
+				status |= PD_STATUS_TCPC_ALERT_0;
+		}
+	}
+
+	if (board_get_usb_pd_port_count() == 2 &&
+	    !gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) {
+		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
+			/* TCPCI spec Rev 1.0 says to ignore bits 14:12. */
+			if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0))
+				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
+
+			if (regval)
+				status |= PD_STATUS_TCPC_ALERT_1;
+		}
+	}
+
+	return status;
+}
+
+void pd_power_supply_reset(int port)
+{
+	/* Disable VBUS */
+	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+/* VBUS_CURRENT_TARGET */
+#define RAA489000_VBUS_CURRENT_TARGET_3_3A 0x68 /* 3.3A */
+
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	int rv;
+
+	if (port < 0 || port >= CONFIG_USB_PD_PORT_MAX_COUNT)
+		return;
+
+	int selected_cur = rp == TYPEC_RP_3A0 ?
+				   RAA489000_VBUS_CURRENT_TARGET_3_3A :
+				   RAA489000_VBUS_CURRENT_TARGET_1_5A;
+
+	rv = tcpc_write16(port, RAA489000_VBUS_CURRENT_TARGET, selected_cur);
+
+	if (rv != EC_SUCCESS) {
+		LOG_WRN("Failed to set source ilimit on port %d to %d: %d",
+			port, selected_cur, rv);
+	}
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	if (port >= CONFIG_USB_PD_PORT_MAX_COUNT)
+		return EC_ERROR_INVAL;
+
+	/* Disable charging. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
+	if (rv)
+		return rv;
+
+	/* Our policy is not to source VBUS when the AP is off. */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	/* Provide Vbus. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
+	if (rv)
+		return rv;
+
+	rv = raa489000_enable_asgate(port, true);
+	if (rv)
+		return rv;
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * TODO(b:147316511): could send a reset command to the TCPC here
+	 * if needed.
+	 */
+}
+
+/*
+ * Because the TCPCs and BC1.2 chips share interrupt lines, it's possible
+ * for an interrupt to be lost if one asserts the IRQ, the other does the same
+ * then the first releases it: there will only be one falling edge to trigger
+ * the interrupt, and the line will be held low. We handle this by polling the
+ * IRQ GPIO on the USB-PD task after processing TCPC interrupts, synchronously
+ * running the BC1.2 interrupt handler to ensure we continue processing
+ * interrupts as long as either source is asserting the IRQ.
+ */
+void board_process_pd_alert(int port)
+{
+	const struct gpio_dt_spec *gpio;
+
+	if (port == 0) {
+		gpio = GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl);
+	} else {
+		gpio = GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl);
+	}
+
+	if (!gpio_pin_get_dt(gpio)) {
+		usb_charger_task_set_event_sync(port, USB_CHG_EVENT_BC12);
+	}
+
+	/*
+	 * Immediately schedule another TCPC interrupt if it seems we haven't
+	 * cleared all pending interrupts.
+	 */
+	if (!gpio_pin_get_dt(gpio))
+		schedule_deferred_pd_interrupt(port);
+}
+
+void usb_interrupt(enum gpio_signal signal)
+{
+	int port;
+
+	if (signal == GPIO_SIGNAL(DT_NODELABEL(gpio_usb_c0_int_odl))) {
+		port = 0;
+	} else {
+		port = 1;
+	}
+	/* Trigger polling of TCPC and BC1.2 in USB-PD task */
+	schedule_deferred_pd_interrupt(port);
+}
+
+struct chg_curr_step {
+	int on;
+	int off;
+	int curr_ma;
+};
+
+static const struct chg_curr_step chg_curr_table[] = {
+	{ .on = 0, .off = 36, .curr_ma = 2800 },
+	{ .on = 46, .off = 36, .curr_ma = 1500 },
+	{ .on = 48, .off = 38, .curr_ma = 1000 },
+};
+
+/* All charge current tables must have the same number of levels */
+#define NUM_CHG_CURRENT_LEVELS ARRAY_SIZE(chg_curr_table)
+
+int charger_profile_override(struct charge_state_data *curr)
+{
+	int rv;
+	int chg_temp_c;
+	int current;
+	int thermal_sensor0;
+	static int current_level;
+	static int prev_tmp;
+
+	/*
+	 * Precharge must be executed when communication is failed on
+	 * dead battery.
+	 */
+	if (!(curr->batt.flags & BATT_FLAG_RESPONSIVE))
+		return 0;
+
+	current = curr->requested_current;
+
+	rv = temp_sensor_read(
+		TEMP_SENSOR_ID_BY_DEV(DT_NODELABEL(temp_charger1)),
+		&thermal_sensor0);
+	chg_temp_c = K_TO_C(thermal_sensor0);
+
+	if (rv != EC_SUCCESS)
+		return 0;
+
+	if (chipset_in_state(CHIPSET_STATE_ON)) {
+		if (chg_temp_c < prev_tmp) {
+			if (chg_temp_c <= chg_curr_table[current_level].off)
+				current_level = current_level - 1;
+		} else if (chg_temp_c > prev_tmp) {
+			if (chg_temp_c >= chg_curr_table[current_level + 1].on)
+				current_level = current_level + 1;
+		}
+		/*
+		 * Prevent level always minus 0 or over table steps.
+		 */
+		if (current_level < 0)
+			current_level = 0;
+		else if (current_level >= NUM_CHG_CURRENT_LEVELS)
+			current_level = NUM_CHG_CURRENT_LEVELS - 1;
+
+		prev_tmp = chg_temp_c;
+		current = chg_curr_table[current_level].curr_ma;
+
+		curr->requested_current = MIN(curr->requested_current, current);
+	}
+	return 0;
+}
+
+enum ec_status charger_profile_override_get_param(uint32_t param,
+						  uint32_t *value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+enum ec_status charger_profile_override_set_param(uint32_t param,
+						  uint32_t value)
+{
+	return EC_RES_INVALID_PARAM;
+}
diff --git a/zephyr/program/nissa/xivur/cbi.dtsi b/zephyr/program/nissa/xivur/cbi.dtsi
new file mode 100644
index 0000000000..d1834285b6
--- /dev/null
+++ b/zephyr/program/nissa/xivur/cbi.dtsi
@@ -0,0 +1,35 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	nissa-fw-config {
+		compatible = "cros-ec,cbi-fw-config";
+
+		/*
+		 * FW_CONFIG field to enable fan or not.
+		 */
+		fan {
+			enum-name = "FW_FAN";
+			start = <1>;
+			size = <1>;
+
+			no-fan {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FAN_NOT_PRESENT";
+				value = <1>;
+			};
+			fan-present {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FAN_PRESENT";
+				value = <0>;
+				/*
+				 * Set as default so that unprovisioned
+				 * configs will run the fan regardless.
+				 */
+				default;
+			};
+		};
+	};
+};
diff --git a/zephyr/program/nissa/xivur/generated.dtsi b/zephyr/program/nissa/xivur/generated.dtsi
new file mode 100644
index 0000000000..eda2880685
--- /dev/null
+++ b/zephyr/program/nissa/xivur/generated.dtsi
@@ -0,0 +1,261 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * This file is auto-generated - do not edit!
+ */
+
+/ {
+
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc {
+			enum-name = "ADC_PP1050_PROC";
+			io-channels = <&adc0 4>;
+		};
+		adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 {
+			enum-name = "ADC_PP3300_S5";
+			io-channels = <&adc0 6>;
+		};
+		adc_temp_sensor_1: temp_sensor_1 {
+			enum-name = "ADC_TEMP_SENSOR_1";
+			io-channels = <&adc0 0>;
+		};
+		adc_temp_sensor_2: temp_sensor_2 {
+			enum-name = "ADC_TEMP_SENSOR_2";
+			io-channels = <&adc0 1>;
+		};
+		adc_temp_sensor_3: temp_sensor_3 {
+			enum-name = "ADC_TEMP_SENSOR_3";
+			io-channels = <&adc0 10>;
+		};
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		gpio_all_sys_pwrgd: all_sys_pwrgd {
+			gpios = <&gpioa 7 GPIO_INPUT>;
+		};
+		gpio_ccd_mode_odl: ccd_mode_odl {
+			gpios = <&gpioe 5 GPIO_INPUT>;
+			enum-name = "GPIO_CCD_MODE_ODL";
+		};
+		gpio_cpu_c10_gate_l: cpu_c10_gate_l {
+			gpios = <&gpio6 7 GPIO_INPUT>;
+		};
+		gpio_ec_battery_pres_odl: ec_battery_pres_odl {
+			gpios = <&gpioa 3 GPIO_INPUT>;
+			enum-name = "GPIO_BATT_PRES_ODL";
+		};
+		gpio_ec_cbi_wp: ec_cbi_wp {
+			gpios = <&gpio7 4 GPIO_OUTPUT>;
+		};
+		gpio_ec_edp_bl_en_od: ec_edp_bl_en_od {
+			gpios = <&gpiod 3 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_ENABLE_BACKLIGHT";
+		};
+		gpio_ec_entering_rw: ec_entering_rw {
+			gpios = <&gpio0 3 GPIO_OUTPUT>;
+			enum-name = "GPIO_ENTERING_RW";
+		};
+		gpio_ec_gsc_packet_mode: ec_gsc_packet_mode {
+			gpios = <&gpio7 5 GPIO_OUTPUT>;
+			enum-name = "GPIO_PACKET_MODE_EN";
+		};
+		gpio_ec_kso_02_inv: ec_kso_02_inv {
+			gpios = <&gpio1 7 (GPIO_OUTPUT_LOW | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_ec_pch_wake_odl: ec_pch_wake_odl {
+			gpios = <&gpiob 0 GPIO_ODR_LOW>;
+		};
+		gpio_ec_prochot_odl: ec_prochot_odl {
+			gpios = <&gpiof 1 GPIO_ODR_HIGH>;
+		};
+		gpio_ec_soc_dsw_pwrok: ec_soc_dsw_pwrok {
+			gpios = <&gpio6 1 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_int_odl: ec_soc_int_odl {
+			gpios = <&gpio8 0 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_EC_INT_L";
+		};
+		gpio_ec_soc_pch_pwrok_od: ec_soc_pch_pwrok_od {
+			gpios = <&gpio7 2 GPIO_ODR_HIGH>;
+		};
+		gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl {
+			gpios = <&gpioc 1 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_PCH_PWRBTN_L";
+		};
+		gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l {
+			gpios = <&gpioa 6 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_rtcrst: ec_soc_rtcrst {
+			gpios = <&gpio7 6 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_sys_pwrok: ec_soc_sys_pwrok {
+			gpios = <&gpio3 7 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_vccst_pwrgd_od: ec_soc_vccst_pwrgd_od {
+			gpios = <&gpioa 4 GPIO_ODR_HIGH>;
+		};
+		gpio_ec_wp_odl: ec_wp_odl {
+			gpios = <&gpioa 1 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_en_pp3300_s5: en_pp3300_s5 {
+			gpios = <&gpiob 6 GPIO_OUTPUT>;
+			enum-name = "GPIO_TEMP_SENSOR_POWER";
+		};
+		gpio_en_pp5000_pen_x: en_pp5000_pen_x {
+			gpios = <&gpioe 2 GPIO_OUTPUT>;
+		};
+		gpio_en_pp5000_s5: en_pp5000_s5 {
+			gpios = <&gpio4 0 GPIO_OUTPUT>;
+		};
+		gpio_en_slp_z: en_slp_z {
+			gpios = <&gpioe 1 GPIO_OUTPUT>;
+		};
+		gpio_en_usb_a0_vbus: en_usb_a0_vbus {
+			gpios = <&gpio9 1 GPIO_OUTPUT>;
+		};
+		gpio_en_usb_a1_vbus: en_usb_a1_vbus {
+			gpios = <&gpiod 4 GPIO_OUTPUT>;
+		};
+		gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl {
+			gpios = <&gpio0 0 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		gpio_imvp91_vrrdy_od: imvp91_vrrdy_od {
+			gpios = <&gpio4 3 GPIO_INPUT>;
+		};
+		gpio_lid_open: lid_open {
+			gpios = <&gpiod 2 GPIO_INPUT>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+		gpio_pen_detect_odl: pen_detect_odl {
+			gpios = <&gpio9 6 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_pg_pp1050_mem_s3_od: pg_pp1050_mem_s3_od {
+			gpios = <&gpiof 0 GPIO_INPUT>;
+		};
+		gpio_pg_pp5000_s5_od: pg_pp5000_s5_od {
+			gpios = <&gpio4 2 GPIO_INPUT>;
+		};
+		gpio_rsmrst_pwrgd_l: rsmrst_pwrgd_l {
+			gpios = <&gpio9 4 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_slp_s0_l: slp_s0_l {
+			gpios = <&gpio9 7 GPIO_INPUT>;
+		};
+		gpio_slp_s3_l: slp_s3_l {
+			gpios = <&gpioa 5 GPIO_INPUT>;
+		};
+		gpio_slp_s4_l: slp_s4_l {
+			gpios = <&gpio7 0 GPIO_INPUT>;
+		};
+		gpio_slp_sus_l: slp_sus_l {
+			gpios = <&gpio6 2 GPIO_INPUT>;
+		};
+		gpio_sys_rst_odl: sys_rst_odl {
+			gpios = <&gpioc 5 GPIO_ODR_HIGH>;
+		};
+		gpio_usb_c0_int_odl: usb_c0_int_odl {
+			gpios = <&gpio0 1 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_usb_c1_int_odl: usb_c1_int_odl {
+			gpios = <&gpio0 2 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_vccin_aux_vid0: vccin_aux_vid0 {
+			gpios = <&gpio9 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		gpio_vccin_aux_vid1: vccin_aux_vid1 {
+			gpios = <&gpioe 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		i2c_ec_i2c_eeprom: ec_i2c_eeprom {
+			i2c-port = <&i2c0_0>;
+			enum-names = "I2C_PORT_EEPROM";
+		};
+		i2c_ec_i2c_sensor: ec_i2c_sensor {
+			i2c-port = <&i2c1_0>;
+			enum-names = "I2C_PORT_SENSOR";
+		};
+		i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 {
+			i2c-port = <&i2c3_0>;
+			enum-names = "I2C_PORT_USB_C0_TCPC";
+		};
+		i2c_ec_i2c_sub_usb_c1: ec_i2c_sub_usb_c1 {
+			i2c-port = <&i2c5_1>;
+			enum-names = "I2C_PORT_USB_C1_TCPC";
+		};
+		i2c_ec_i2c_batt: ec_i2c_batt {
+			i2c-port = <&i2c7_0>;
+			enum-names = "I2C_PORT_BATTERY";
+		};
+	};
+};
+
+&adc0 {
+	status = "okay";
+	pinctrl-0 = <&adc0_chan0_gp45
+		     &adc0_chan1_gp44
+		     &adc0_chan4_gp41
+		     &adc0_chan6_gp34
+		     &adc0_chan10_gpe0>;
+	pinctrl-names = "default";
+};
+
+
+&i2c0_0 {
+	status = "okay";
+	pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>;
+	pinctrl-names = "default";
+};
+
+&i2c1_0 {
+	status = "okay";
+	pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>;
+	pinctrl-names = "default";
+};
+
+&i2c3_0 {
+	status = "okay";
+	pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>;
+	pinctrl-names = "default";
+};
+
+&i2c5_1 {
+	status = "okay";
+	pinctrl-0 = <&i2c5_1_sda_scl_gpf4_f5>;
+	pinctrl-names = "default";
+};
+
+&i2c7_0 {
+	status = "okay";
+	pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>;
+	pinctrl-names = "default";
+};
+
+&i2c_ctrl0 {
+	status = "okay";
+};
+
+&i2c_ctrl1 {
+	status = "okay";
+};
+
+&i2c_ctrl3 {
+	status = "okay";
+};
+
+&i2c_ctrl5 {
+	status = "okay";
+};
+
+&i2c_ctrl7 {
+	status = "okay";
+};
diff --git a/zephyr/program/nissa/xivur/keyboard.dtsi b/zephyr/program/nissa/xivur/keyboard.dtsi
new file mode 100644
index 0000000000..5248c4aaff
--- /dev/null
+++ b/zephyr/program/nissa/xivur/keyboard.dtsi
@@ -0,0 +1,34 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+&cros_kb_raw {
+	status = "okay";
+	/* No KSO2 (it's inverted and implemented by GPIO) */
+	pinctrl-0 = <
+		&ksi0_gp31
+		&ksi1_gp30
+		&ksi2_gp27
+		&ksi3_gp26
+		&ksi4_gp25
+		&ksi5_gp24
+		&ksi6_gp23
+		&ksi7_gp22
+		&kso00_gp21
+		&kso01_gp20
+		&kso03_gp16
+		&kso04_gp15
+		&kso05_gp14
+		&kso06_gp13
+		&kso07_gp12
+		&kso08_gp11
+		&kso09_gp10
+		&kso10_gp07
+		&kso11_gp06
+		&kso12_gp05
+		&kso13_gp04
+		&kso14_gp82
+	>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/nissa/xivur/overlay.dtsi b/zephyr/program/nissa/xivur/overlay.dtsi
new file mode 100644
index 0000000000..1d083ed01b
--- /dev/null
+++ b/zephyr/program/nissa/xivur/overlay.dtsi
@@ -0,0 +1,328 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <cros/thermistor/thermistor.dtsi>
+
+/ {
+	aliases {
+		gpio-cbi-wp = &gpio_ec_cbi_wp;
+		gpio-wp = &gpio_ec_wp_odl;
+		int-wp = &int_wp_l;
+		gpio-kbd-kso2 = &gpio_ec_kso_02_inv;
+	};
+
+	ec-console {
+		compatible = "ec-console";
+		disabled = "events", "lpc", "hostcmd";
+	};
+
+	batteries {
+		default_battery: smp {
+			compatible = "smp,c31n2005", "battery-smart";
+		};
+	};
+
+	hibernate-wake-pins {
+		compatible = "cros-ec,hibernate-wake-pins";
+		wakeup-irqs = <
+			&int_power_button
+			&int_lid_open
+		>;
+	};
+
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_power_button: power_button {
+			irq-pin = <&gpio_gsc_ec_pwr_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_button_interrupt";
+		};
+		int_wp_l: wp_l {
+			irq-pin = <&gpio_ec_wp_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "switch_interrupt";
+		};
+		int_lid_open: lid_open {
+			irq-pin = <&gpio_lid_open>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "lid_interrupt";
+		};
+		int_usb_c0: usb_c0 {
+			irq-pin = <&gpio_usb_c0_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "usb_interrupt";
+		};
+		int_usb_c1: usb_c1 {
+			irq-pin = <&gpio_usb_c1_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "usb_interrupt";
+		};
+	};
+
+	named-gpios {
+		gpio_fan_enable: fan-enable {
+			gpios = <&gpio6 3 GPIO_OUTPUT>;
+			no-auto-init;
+		};
+		ec-i2c-sensor-scl {
+			gpios = <&gpio9 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		ec-i2c-sensor-sda {
+			gpios = <&gpio8 7 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+	};
+
+	temp_memory: memory {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_1>;
+	};
+	temp_charger: charger {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_2>;
+	};
+	temp_ambient: ambient {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_3>;
+	};
+
+	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
+		memory {
+			temp_fan_off = <35>;
+			temp_fan_max = <60>;
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_memory>;
+		};
+		charger {
+			temp_fan_off = <35>;
+			temp_fan_max = <60>;
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_charger>;
+		};
+		ambient {
+			temp_fan_off = <35>;
+			temp_fan_max = <60>;
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_ambient>;
+		};
+	};
+
+	usba {
+		compatible = "cros-ec,usba-port-enable-pins";
+		enable-pins = <&gpio_en_usb_a0_vbus &gpio_en_usb_a1_vbus>;
+		status = "okay";
+	};
+
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+			chg = <&chg_port0>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_0>;
+			};
+		};
+		port0-muxes {
+			virtual_mux_0: virtual-mux-0 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+		/*
+		 * TODO(b:211693800): port1 may not be present on some
+		 * sub-boards.
+		 */
+		port1@1 {
+			compatible = "named-usbc-port";
+			reg = <1>;
+			chg = <&chg_port1>;
+			usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_1 &anx7483_mux_1>;
+			};
+			usb_mux_chain_1_no_mux: usb-mux-chain-1-no-mux {
+				compatible = "cros-ec,usb-mux-chain";
+				alternative-chain;
+				usb-muxes = <&virtual_mux_1>;
+			};
+		};
+		port1-muxes {
+			virtual_mux_1: virtual-mux-1 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+	};
+
+	fans {
+		compatible = "cros-ec,fans";
+
+		fan_0 {
+			pwms = <&pwm5 5 PWM_KHZ(1) PWM_POLARITY_NORMAL>;
+			rpm_min = <2200>;
+			rpm_start = <2200>;
+			rpm_max = <4200>;
+			tach = <&tach2>;
+			enable_gpio = <&gpio_fan_enable>;
+		};
+	};
+
+	 /*
+	  * Declare unused GPIOs so that they are shut down
+	  * and use minimal power
+	  */
+	  unused-pins {
+		compatible = "unused-gpios";
+		unused-gpios =
+			<&gpio3 2 0>,
+			<&gpio3 3 0>,
+			<&gpio3 5 0>,
+			<&gpio3 6 0>,
+			<&gpio5 0 0>,
+			<&gpio5 6 0>,
+			<&gpio5 7 0>,
+			<&gpio6 0 0>,
+			<&gpio6 3 0>,
+			<&gpio6 6 0>,
+			<&gpio7 3 0>,
+			<&gpio8 3 0>,
+			<&gpio8 5 0>,
+			<&gpio8 6 0>,
+			<&gpio9 3 0>,
+			<&gpio9 5 0>,
+			<&gpioa 0 0>,
+			<&gpioa 2 0>,
+			<&gpiob 1 0>,
+			<&gpiob 7 0>,
+			<&gpioc 6 0>,
+			<&gpioc 7 0>,
+			<&gpiod 5 0>,
+			<&gpioe 4 0>,
+			<&gpiof 2 0>,
+			<&gpiof 3 0>;
+	 };
+};
+
+&thermistor_3V3_51K1_47K_4050B {
+	status = "okay";
+};
+
+&adc_ec_vsense_pp3300_s5 {
+	/*
+	 * Voltage divider on input has 47k upper and 220k lower legs with
+	 * 2714 mV full-scale reading on the ADC. Apply the largest possible
+	 * multiplier (without overflowing int32) to get the best possible
+	 * approximation of the actual ratio, but derate by a factor of two to
+	 * ensure unexpectedly high values won't overflow.
+	 */
+	mul = <(791261 / 2)>;
+	div = <(651975 / 2)>;
+};
+
+/* Set bus speeds for I2C */
+&i2c0_0 {
+	label = "I2C_EEPROM";
+	clock-frequency = <I2C_BITRATE_FAST>;
+
+	cbi_eeprom: eeprom@50 {
+		compatible = "atmel,at24";
+		reg = <0x50>;
+		size = <2048>;
+		pagesize = <16>;
+		address-width = <8>;
+		timeout = <5>;
+	};
+};
+
+&i2c1_0 {
+	label = "I2C_SENSOR";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&i2c3_0 {
+	label = "I2C_USB_C0_TCPC";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+
+	chg_port0: isl923x@9 {
+		compatible = "intersil,isl923x";
+		status = "okay";
+		reg = <0x9>;
+	};
+};
+
+&i2c5_1 {
+	label = "I2C_SUB_C1_TCPC";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+
+	chg_port1: isl923x@9 {
+		compatible = "intersil,isl923x";
+		status = "okay";
+		reg = <0x9>;
+	};
+
+	anx7483_mux_1: anx7483-mux-1@3e {
+		compatible = "analogix,anx7483";
+		reg = <0x3e>;
+		board-set = "anx7483_set_default_tuning";
+	};
+};
+
+&i2c7_0 {
+	label = "I2C_BATTERY";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+};
+
+&pwm5_gpb7 {
+	drive-open-drain;
+};
+
+&pwm5 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm5_gpb7>;
+	pinctrl-names = "default";
+};
+
+/* Tachometer for fan speed measurement */
+&tach2 {
+	status = "okay";
+	pinctrl-0 = <&ta2_1_in_gp73>;
+	pinctrl-names = "default";
+	port = <NPCX_TACH_PORT_A>; /* port-A is selected */
+	sample-clk = <NPCX_TACH_FREQ_LFCLK>; /* Use LFCLK as sampling clock */
+	pulses-per-round = <2>; /* number of pulses per round of encoder */
+};
+
+/* host interface */
+&espi0 {
+	status = "okay";
+	pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>;
+	pinctrl-names = "default";
+};
+
+/*
+ * Declare GPIOs that have leakage current caused by board issues here. NPCX ec
+ * will disable their input buffers before entering deep sleep and restore them
+ * after waking up automatically for better power consumption.
+ */
+&power_leakage_io {
+	leak-gpios = <&gpioa 4 GPIO_OPEN_DRAIN
+		      &gpiof 1 GPIO_OPEN_DRAIN>;
+};
diff --git a/zephyr/program/nissa/xivur/power_signals.dtsi b/zephyr/program/nissa/xivur/power_signals.dtsi
new file mode 100644
index 0000000000..1d2b23069d
--- /dev/null
+++ b/zephyr/program/nissa/xivur/power_signals.dtsi
@@ -0,0 +1,220 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	chosen {
+		intel-ap-pwrseq,espi = &espi0;
+	};
+
+	common-pwrseq {
+		compatible = "intel,ap-pwrseq";
+
+		sys-pwrok-delay = <10>;
+		all-sys-pwrgd-timeout = <20>;
+	};
+
+	pwr-en-pp5000-s5 {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PP5000_S5 enable output to regulator";
+		enum-name = "PWR_EN_PP5000_A";
+		gpios = <&gpio4 0 0>;
+		output;
+	};
+	pwr-en-pp3300-s5 {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PP3300_S5 enable output to LS";
+		enum-name = "PWR_EN_PP3300_A";
+		gpios = <&gpiob 6 0>;
+		output;
+	};
+	pwr-pg-ec-rsmrst-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST power good from regulator";
+		enum-name = "PWR_RSMRST";
+		gpios = <&gpio9 4 0>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-ec-pch-rsmrst-odl {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST output to PCH";
+		enum-name = "PWR_EC_PCH_RSMRST";
+		gpios = <&gpioa 6 0>;
+		output;
+	};
+	pwr-slp-s0-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_S0_L input from PCH";
+		enum-name = "PWR_SLP_S0";
+		gpios = <&gpio9 7 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-slp-s3-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_S3_L input from PCH";
+		enum-name = "PWR_SLP_S3";
+		gpios = <&gpioa 5 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-slp-sus-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_SUS_L input from PCH";
+		enum-name = "PWR_SLP_SUS";
+		gpios = <&gpio6 2 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-ec-soc-dsw-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "DSW_PWROK output to PCH";
+		enum-name = "PWR_EC_SOC_DSW_PWROK";
+		gpios = <&gpio6 1 0>;
+		output;
+	};
+	pwr-vccst-pwrgd-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "VCCST_PWRGD output to PCH";
+		enum-name = "PWR_VCCST_PWRGD";
+		gpios = <&gpioa 4 GPIO_OPEN_DRAIN>;
+		output;
+	};
+	pwr-imvp9-vrrdy-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "VRRDY input from IMVP9";
+		enum-name = "PWR_IMVP9_VRRDY";
+		gpios = <&gpio4 3 0>;
+	};
+	pwr-pch-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PCH_PWROK output to PCH";
+		enum-name = "PWR_PCH_PWROK";
+		gpios = <&gpio7 2 GPIO_OPEN_DRAIN>;
+		output;
+	};
+	pwr-ec-pch-sys-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_PWROK output to PCH";
+		enum-name = "PWR_EC_PCH_SYS_PWROK";
+		gpios = <&gpio3 7 0>;
+		output;
+	};
+	pwr-sys-rst-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_RESET# output to PCH";
+		enum-name = "PWR_SYS_RST";
+		gpios = <&gpioc 5 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>;
+		output;
+	};
+	pwr-slp-s4 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S4 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S4";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4";
+		vw-invert;
+	};
+	pwr-slp-s5 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S5 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S5";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5";
+		vw-invert;
+	};
+	pwr-all-sys-pwrgd {
+		compatible = "intel,ap-pwrseq-external";
+		dbg-label = "Combined all power good";
+		enum-name = "PWR_ALL_SYS_PWRGD";
+	};
+	pwr-adc-pp3300 {
+		compatible = "intel,ap-pwrseq-adc";
+		dbg-label = "PP3300 PWROK (from ADC)";
+		enum-name = "PWR_DSW_PWROK";
+		trigger-high = <&cmp_pp3300_s5_high>;
+		trigger-low = <&cmp_pp3300_s5_low>;
+	};
+	pwr-adc-pp1p05 {
+		compatible = "intel,ap-pwrseq-adc";
+		dbg-label = "PP1P05 PWROK (from ADC)";
+		enum-name = "PWR_PG_PP1P05";
+		trigger-high = <&cmp_pp1p05_high>;
+		trigger-low = <&cmp_pp1p05_low>;
+	};
+
+	adc-cmp {
+		cmp_pp3300_s5_high: pp3300_high {
+			compatible = "nuvoton,adc-cmp";
+			io-channels = <&adc0 6>;
+			comparison = "ADC_CMP_NPCX_GREATER";
+			/*
+			 * This is 90% of nominal voltage considering voltage
+			 * divider on ADC input.
+			 */
+			threshold-mv = <2448>;
+		};
+		cmp_pp3300_s5_low: pp3300_low {
+			compatible = "nuvoton,adc-cmp";
+			io-channels = <&adc0 6>;
+			comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL";
+			threshold-mv = <2448>;
+		};
+		cmp_pp1p05_high: pp1p05_high {
+			compatible = "nuvoton,adc-cmp";
+			io-channels = <&adc0 4>;
+			comparison = "ADC_CMP_NPCX_GREATER";
+			/* Setting at 90% of nominal voltage */
+			threshold-mv = <945>;
+		};
+		cmp_pp1p05_low: pp1p05_low {
+			compatible = "nuvoton,adc-cmp";
+			io-channels = <&adc0 4>;
+			comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL";
+			threshold-mv = <945>;
+		};
+	};
+};
+
+/*
+ * Because the power signals directly reference the GPIOs,
+ * the correspinding named-gpios need to have no-auto-init set.
+ */
+&gpio_ec_soc_dsw_pwrok {
+	no-auto-init;
+};
+&gpio_ec_soc_pch_pwrok_od {
+	no-auto-init;
+};
+&gpio_ec_soc_rsmrst_l {
+	no-auto-init;
+};
+&gpio_ec_soc_sys_pwrok {
+	no-auto-init;
+};
+&gpio_ec_soc_vccst_pwrgd_od {
+	no-auto-init;
+};
+&gpio_en_pp3300_s5 {
+	no-auto-init;
+};
+&gpio_en_pp5000_s5 {
+	no-auto-init;
+};
+&gpio_imvp91_vrrdy_od {
+	no-auto-init;
+};
+&gpio_rsmrst_pwrgd_l {
+	no-auto-init;
+};
+&gpio_slp_s0_l {
+	no-auto-init;
+};
+&gpio_slp_s3_l {
+	no-auto-init;
+};
+&gpio_slp_s4_l {
+	no-auto-init;
+};
+&gpio_slp_sus_l {
+	no-auto-init;
+};
+&gpio_sys_rst_odl {
+	no-auto-init;
+};
diff --git a/zephyr/program/nissa/xivur/project.conf b/zephyr/program/nissa/xivur/project.conf
new file mode 100644
index 0000000000..f6e1adf93c
--- /dev/null
+++ b/zephyr/program/nissa/xivur/project.conf
@@ -0,0 +1,31 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_BOARD_XIVUR=y
+CONFIG_PLATFORM_EC_OCPC=y
+CONFIG_NISSA_SUB_BOARD=n
+
+# Battery Configuration
+CONFIG_PLATFORM_EC_SMBUS_PEC=y
+CONFIG_PLATFORM_EC_BATT_HOST_FULL_FACTOR=99
+
+# Sensors: disabled; xivur is clamshell-only
+CONFIG_PLATFORM_EC_ACCEL_LIS2DW12=n
+CONFIG_PLATFORM_EC_LID_ANGLE=n
+CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=n
+CONFIG_PLATFORM_EC_MOTIONSENSE=n
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=n
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=n
+CONFIG_PLATFORM_EC_ACCEL_FIFO=n
+CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=n
+CONFIG_PLATFORM_EC_GMR_TABLET_MODE=n
+CONFIG_PLATFORM_EC_TABLET_MODE=n
+CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=n
+CONFIG_PLATFORM_EC_VOLUME_BUTTONS=n
+
+#Disable keyboard backlight
+CONFIG_PLATFORM_EC_KBLIGHT_ENABLE_PIN=n
+
+#Disable BC12
+CONFIG_PLATFORM_EC_USB_CHARGER=n
diff --git a/zephyr/program/nissa/xivur/project.overlay b/zephyr/program/nissa/xivur/project.overlay
new file mode 100644
index 0000000000..ba6f6205bf
--- /dev/null
+++ b/zephyr/program/nissa/xivur/project.overlay
@@ -0,0 +1,11 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi.dtsi"
+#include "generated.dtsi"
+#include "keyboard.dtsi"
+#include "overlay.dtsi"
+#include "power_signals.dtsi"
+#include "pwm_leds.dtsi"
diff --git a/zephyr/program/nissa/xivur/pwm_leds.dtsi b/zephyr/program/nissa/xivur/pwm_leds.dtsi
new file mode 100644
index 0000000000..535a0646ec
--- /dev/null
+++ b/zephyr/program/nissa/xivur/pwm_leds.dtsi
@@ -0,0 +1,61 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	pwmleds {
+		compatible = "pwm-leds";
+		pwm_led0: pwm_led_0 {
+			pwms = <&pwm2 2 PWM_HZ(324) PWM_POLARITY_INVERTED>,
+			       <&pwm0 0 PWM_HZ(324) PWM_POLARITY_INVERTED>,
+			       <&pwm1 1 PWM_HZ(324) PWM_POLARITY_INVERTED>;
+		};
+	};
+
+	cros-pwmleds {
+		compatible = "cros-ec,pwm-leds";
+
+		leds = <&pwm_led0>;
+
+		color-map-red    = <  0   0    0>;
+		color-map-green  = <  0   0    0>;
+		color-map-blue   = <  0   0    0>;
+		color-map-yellow = <  0   0    0>;
+		color-map-white  = <  0   0  100>;
+		color-map-amber  = <  0 100    0>;
+
+		brightness-range = <0 0 0 0 100 100>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pwm_led_0@0 {
+			reg = <0>;
+			ec-led-name = "EC_LED_ID_BATTERY_LED";
+		};
+	};
+};
+
+/* Enable LEDs to work while CPU suspended */
+
+&pwm0 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm0_gpc3>;
+	pinctrl-names = "default";
+};
+
+&pwm1 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm1_gpc2>;
+	pinctrl-names = "default";
+};
+
+&pwm2 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm2_gpc4>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/nissa/xivur/src/board.c b/zephyr/program/nissa/xivur/src/board.c
new file mode 100644
index 0000000000..7fe60c8f84
--- /dev/null
+++ b/zephyr/program/nissa/xivur/src/board.c
@@ -0,0 +1,33 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "task.h"
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/sys/printk.h>
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+__override uint8_t board_get_usb_pd_port_count(void)
+{
+	return 2;
+}
+/*
+ * Enable interrupts
+ */
+static void board_init(void)
+{
+	/*
+	 * Enable USB-C interrupts.
+	 */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0));
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1));
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/zephyr/program/nissa/xivur/src/charger.c b/zephyr/program/nissa/xivur/src/charger.c
new file mode 100644
index 0000000000..37e51fda09
--- /dev/null
+++ b/zephyr/program/nissa/xivur/src/charger.c
@@ -0,0 +1,55 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "charger.h"
+#include "charger/isl923x_public.h"
+#include "console.h"
+#include "extpower.h"
+#include "usb_pd.h"
+
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+int extpower_is_present(void)
+{
+	int port;
+	int rv;
+	bool acok;
+
+	for (port = 0; port < board_get_usb_pd_port_count(); port++) {
+		rv = raa489000_is_acok(port, &acok);
+		if ((rv == EC_SUCCESS) && acok)
+			return 1;
+	}
+
+	return 0;
+}
+
+/*
+ * Nivviks does not have a GPIO indicating whether extpower is present,
+ * so detect using the charger(s).
+ */
+__override void board_check_extpower(void)
+{
+	static int last_extpower_present;
+	int extpower_present = extpower_is_present();
+
+	if (last_extpower_present ^ extpower_present)
+		extpower_handle_update(extpower_present);
+
+	last_extpower_present = extpower_present;
+}
+
+__override void board_hibernate(void)
+{
+	/* Shut down the chargers */
+	if (board_get_usb_pd_port_count() == 2)
+		raa489000_hibernate(CHARGER_SECONDARY, true);
+	raa489000_hibernate(CHARGER_PRIMARY, true);
+	LOG_INF("Charger(s) hibernated");
+	cflush();
+}
diff --git a/zephyr/program/nissa/xivur/src/fan.c b/zephyr/program/nissa/xivur/src/fan.c
new file mode 100644
index 0000000000..3223a28919
--- /dev/null
+++ b/zephyr/program/nissa/xivur/src/fan.c
@@ -0,0 +1,42 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cros_cbi.h"
+#include "fan.h"
+#include "gpio/gpio.h"
+#include "hooks.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+static void fan_init(void)
+{
+	int ret;
+	uint32_t val;
+	/*
+	 * Retrieve the fan config.
+	 */
+	ret = cros_cbi_get_fw_config(FW_FAN, &val);
+	if (ret != 0) {
+		LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_FAN);
+		return;
+	}
+	if (val == FW_FAN_NOT_PRESENT) {
+		/* Disable the fan */
+		LOG_INF("Fan not present");
+		fan_set_count(0);
+		gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_fan_enable),
+				      GPIO_OUTPUT_LOW);
+	} else if (val == FW_FAN_PRESENT) {
+		/* Configure the fan enable GPIO */
+		LOG_INF("Fan present");
+		gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_fan_enable),
+				      GPIO_OUTPUT);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, fan_init, HOOK_PRIO_POST_FIRST);
diff --git a/zephyr/program/nissa/xivur/src/keyboard.c b/zephyr/program/nissa/xivur/src/keyboard.c
new file mode 100644
index 0000000000..b7e6c2b482
--- /dev/null
+++ b/zephyr/program/nissa/xivur/src/keyboard.c
@@ -0,0 +1,47 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+#include "keyboard_scan.h"
+#include "timer.h"
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/* Increase from 50 us, because KSO_02 passes through the H1. */
+	.output_settle_us = 80,
+	/* Other values should be the same as the default configuration. */
+	.debounce_down_us = 9 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x1c, 0xfe, 0xff, 0xff, 0xff, 0xf5, 0xff,
+		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
+	},
+};
+
+static const struct ec_response_keybd_config xivur_kb = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &xivur_kb;
+}
diff --git a/zephyr/program/nissa/xivur/src/led.c b/zephyr/program/nissa/xivur/src/led.c
new file mode 100644
index 0000000000..64f1be5096
--- /dev/null
+++ b/zephyr/program/nissa/xivur/src/led.c
@@ -0,0 +1,68 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery LED control for nissa
+ */
+#include "chipset.h"
+#include "common.h"
+#include "ec_commands.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+#include "led_pwm.h"
+
+__override const int led_charge_lvl_1 = 5;
+__override const int led_charge_lvl_2 = 95;
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_WHITE,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_WHITE:
+		set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_WHITE);
+		break;
+	case EC_LED_COLOR_AMBER:
+		set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_AMBER);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		set_pwm_led_color(EC_LED_ID_BATTERY_LED, -1);
+		break;
+	}
+}
+
+__override enum led_states board_led_get_state(enum led_states desired_state)
+{
+	if (desired_state == STATE_BATTERY_ERROR) {
+		if (chipset_in_state(CHIPSET_STATE_ON))
+			return desired_state;
+		else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
+			return STATE_DISCHARGE_S3;
+		else
+			return STATE_DISCHARGE_S5;
+	}
+	return desired_state;
+}
diff --git a/zephyr/program/nissa/xivur/src/usbc.c b/zephyr/program/nissa/xivur/src/usbc.c
new file mode 100644
index 0000000000..a0bd74b3a6
--- /dev/null
+++ b/zephyr/program/nissa/xivur/src/usbc.c
@@ -0,0 +1,224 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_state.h"
+#include "chipset.h"
+#include "driver/charger/isl923x_public.h"
+#include "driver/retimer/anx7483_public.h"
+#include "driver/tcpm/raa489000.h"
+#include "driver/tcpm/tcpci.h"
+#include "hooks.h"
+#include "system.h"
+#include "usb_mux.h"
+
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0_TCPC,
+			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
+		},
+		.drv = &raa489000_tcpm_drv,
+		/* RAA489000 implements TCPCI 2.0 */
+		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_VBUS_MONITOR,
+	},
+	{ /* sub-board */
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C1_TCPC,
+			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
+		},
+		.drv = &raa489000_tcpm_drv,
+		/* RAA489000 implements TCPCI 2.0 */
+		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_VBUS_MONITOR,
+	},
+};
+
+int board_is_sourcing_vbus(int port)
+{
+	int regval;
+
+	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
+	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int i;
+	int old_port;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	old_port = charge_manager_get_active_charge_port();
+
+	LOG_INF("New chg p%d", port);
+
+	/* Disable all ports. */
+	if (port == CHARGE_PORT_NONE) {
+		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+			tcpc_write(i, TCPC_REG_COMMAND,
+				   TCPC_REG_COMMAND_SNK_CTRL_LOW);
+			raa489000_enable_asgate(i, false);
+		}
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if port is sourcing VBUS. */
+	if (board_is_sourcing_vbus(port)) {
+		LOG_WRN("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		if (i == port)
+			continue;
+
+		if (tcpc_write(i, TCPC_REG_COMMAND,
+			       TCPC_REG_COMMAND_SNK_CTRL_LOW))
+			LOG_WRN("p%d: sink path disable failed.", i);
+		raa489000_enable_asgate(i, false);
+	}
+
+	/*
+	 * Stop the charger IC from switching while changing ports.  Otherwise,
+	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
+	 */
+	if (old_port != CHARGE_PORT_NONE)
+		charger_discharge_on_ac(1);
+
+	/* Enable requested charge port. */
+	if (raa489000_enable_asgate(port, true) ||
+	    tcpc_write(port, TCPC_REG_COMMAND,
+		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
+		LOG_WRN("p%d: sink path enable failed.", port);
+		charger_discharge_on_ac(0);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	/* Allow the charger IC to begin/continue switching. */
+	charger_discharge_on_ac(0);
+
+	return EC_SUCCESS;
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+	int regval;
+
+	/*
+	 * The interrupt line is shared between the TCPC and BC1.2 detector IC.
+	 * Therefore, go out and actually read the alert registers to report the
+	 * alert status.
+	 */
+	if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl))) {
+		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
+			/* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */
+			if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0))
+				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
+
+			if (regval)
+				status |= PD_STATUS_TCPC_ALERT_0;
+		}
+	}
+
+	if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_int_odl))) {
+		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
+			/* TCPCI spec Rev 1.0 says to ignore bits 14:12. */
+			if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0))
+				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
+
+			if (regval)
+				status |= PD_STATUS_TCPC_ALERT_1;
+		}
+	}
+
+	return status;
+}
+
+void pd_power_supply_reset(int port)
+{
+	/* Disable VBUS */
+	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	if (port < 0 || port >= CONFIG_USB_PD_PORT_MAX_COUNT)
+		return;
+
+	raa489000_set_output_current(port, rp);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	if (port >= CONFIG_USB_PD_PORT_MAX_COUNT)
+		return EC_ERROR_INVAL;
+
+	/* Disable charging. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
+	if (rv)
+		return rv;
+
+	/* Our policy is not to source VBUS when the AP is off. */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	/* Provide Vbus. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
+	if (rv)
+		return rv;
+
+	rv = raa489000_enable_asgate(port, true);
+	if (rv)
+		return rv;
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * TODO(b:147316511): could send a reset command to the TCPC here
+	 * if needed.
+	 */
+}
+
+/*
+ * xivur doesn't support BC1.2 like other nissa devices, so the USB-C interrupt
+ * signals aren't shared and don't need any special handling.
+ */
+void usb_interrupt(enum gpio_signal signal)
+{
+	int port;
+
+	if (signal == GPIO_SIGNAL(DT_NODELABEL(gpio_usb_c0_int_odl))) {
+		port = 0;
+	} else {
+		port = 1;
+	}
+	schedule_deferred_pd_interrupt(port);
+}
diff --git a/zephyr/program/nissa/yaviks/cbi.dtsi b/zephyr/program/nissa/yaviks/cbi.dtsi
new file mode 100644
index 0000000000..0a0975d359
--- /dev/null
+++ b/zephyr/program/nissa/yaviks/cbi.dtsi
@@ -0,0 +1,100 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	/* Yaviks-specific fw_config fields. */
+	nissa-fw-config {
+		compatible = "cros-ec,cbi-fw-config";
+		/*
+		 * FW_CONFIG field for multiple wi-fi SAR.
+		 *
+		 *	start = <2>;
+		 *	size = <2>;
+		 */
+
+		/*
+		 * FW_CONFIG field to enable fan or not.
+		 */
+		fan {
+			enum-name = "FW_FAN";
+			start = <4>;
+			size = <1>;
+
+			no-fan {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FAN_NOT_PRESENT";
+				value = <0>;
+			};
+			fan-present {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FAN_PRESENT";
+				value = <1>;
+				/*
+				 * Set as default so that unprovisioned
+				 * configs will run the fan regardless.
+				 */
+				default;
+			};
+		};
+
+		/*
+		 * FW_CONFIG field to indicate which keyboard layout
+		 * should be used.
+		 */
+		keyboard {
+			enum-name = "FW_KB_LAYOUT";
+			start = <5>;
+			size = <1>;
+
+			layout-1 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_KB_LAYOUT_DEFAULT";
+				value = <0>;
+				default;
+			};
+			layout-2 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_KB_LAYOUT_US2";
+				value = <1>;
+			};
+		};
+
+		/*
+		 * FW_CONFIG field to indicate which keyboard layout
+		 * should be used.
+		 */
+		keyboard-backlight {
+			enum-name = "FW_KB_BACKLIGHT";
+			start = <6>;
+			size = <1>;
+
+			without-keyboard-backlight {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_KB_BACKLIGHT_OFF";
+				value = <1>;
+			};
+			with-keyboard-backlight {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_KB_BACKLIGHT_ON";
+				value = <0>;
+				default;
+			};
+		};
+
+		/*
+		 * FW_CONFIG field for multiple touch panel.
+		 *
+		 *	start = <7>;
+		 *	size = <2>;
+		 */
+
+		/*
+		 * FW_CONFIG field for multiple storage.
+		 *
+		 *	start = <31>;
+		 *	size = <1>;
+		 */
+	};
+};
diff --git a/zephyr/program/nissa/yaviks/fan.dtsi b/zephyr/program/nissa/yaviks/fan.dtsi
new file mode 100644
index 0000000000..6a3fc0288a
--- /dev/null
+++ b/zephyr/program/nissa/yaviks/fan.dtsi
@@ -0,0 +1,71 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/ {
+	fans {
+		compatible = "cros-ec,fans";
+		fan_0 {
+			pwms = <&pwm2 PWM_CHANNEL_2 PWM_KHZ(25) PWM_POLARITY_NORMAL>;
+			tach = <&tach1>;
+			rpm_min = <2500>;
+			rpm_start = <2500>;
+			rpm_max = <4100>;
+			rpm_deviation = <1>;
+			enable_gpio = <&gpio_fan_enable>;
+		};
+	};
+	fan_steps {
+		compatible = "cros-ec,fan-steps";
+		level_0 {
+			temp_on = <43 47 0>;
+			temp_off = <99 99 99>;
+			rpm_target = <0>;
+		};
+		level_1 {
+			temp_on = <46 48 0>;
+			temp_off = <40 45 99>;
+			rpm_target = <2600>;
+		};
+		level_2 {
+			temp_on = <49 49 0>;
+			temp_off = <44 46 99>;
+			rpm_target = <2800>;
+		};
+		level_3 {
+			temp_on = <53 50 54>;
+			temp_off = <47 47 51>;
+			rpm_target = <3100>;
+		};
+		level_4 {
+			temp_on = <56 56 60>;
+			temp_off = <51 48 52>;
+			rpm_target = <3300>;
+		};
+		level_5 {
+			temp_on = <60 60 64>;
+			temp_off = <54 52 56>;
+			rpm_target = <3600>;
+		};
+		level_6 {
+			temp_on = <100 100 100>;
+			temp_off = <58 54 58>;
+			rpm_target = <4000>;
+		};
+	};
+};
+/* pwm for fan */
+&pwm2 {
+	status = "okay";
+	prescaler-cx = <PWM_PRESCALER_C6>;
+	pinctrl-0 = <&pwm2_gpa2_default>;
+	pinctrl-names = "default";
+};
+/* fan tachometer sensor */
+&tach1 {
+	status = "okay";
+	channel = <IT8XXX2_TACH_CHANNEL_A>;
+	pulses-per-round = <2>;
+	pinctrl-0 = <&tach1a_gpd7_default>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/nissa/yaviks/gpio.dtsi b/zephyr/program/nissa/yaviks/gpio.dtsi
new file mode 100644
index 0000000000..d063b897d9
--- /dev/null
+++ b/zephyr/program/nissa/yaviks/gpio.dtsi
@@ -0,0 +1,242 @@
+/*
+ * Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc {
+			enum-name = "ADC_PP1050_PROC";
+			io-channels = <&adc0 14>;
+		};
+		adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 {
+			enum-name = "ADC_PP3300_S5";
+			io-channels = <&adc0 0>;
+		};
+		adc_temp_sensor_1: temp_sensor_1 {
+			enum-name = "ADC_TEMP_SENSOR_1";
+			io-channels = <&adc0 2>;
+		};
+		adc_temp_sensor_2: temp_sensor_2 {
+			enum-name = "ADC_TEMP_SENSOR_2";
+			io-channels = <&adc0 3>;
+		};
+		adc_temp_sensor_3: temp_sensor_3 {
+			enum-name = "ADC_TEMP_SENSOR_3";
+			io-channels = <&adc0 13>;
+		};
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		gpio_all_sys_pwrgd: all_sys_pwrgd {
+			gpios = <&gpiob 7 GPIO_INPUT>;
+		};
+		gpio_ccd_mode_odl: ccd_mode_odl {
+			gpios = <&gpioh 5 GPIO_INPUT>;
+			enum-name = "GPIO_CCD_MODE_ODL";
+		};
+		gpio_cpu_c10_gate_l: cpu_c10_gate_l {
+			gpios = <&gpiog 1 GPIO_INPUT>;
+		};
+		gpio_ec_battery_pres_odl: ec_battery_pres_odl {
+			gpios = <&gpioi 4 GPIO_INPUT>;
+			enum-name = "GPIO_BATT_PRES_ODL";
+		};
+		gpio_ec_cbi_wp: ec_cbi_wp {
+			gpios = <&gpioj 5 GPIO_OUTPUT>;
+		};
+		gpio_ec_edp_bl_en_od: ec_edp_bl_en_od {
+			gpios = <&gpiok 4 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_ENABLE_BACKLIGHT";
+		};
+		gpio_ec_entering_rw: ec_entering_rw {
+			gpios = <&gpioc 7 GPIO_OUTPUT>;
+			enum-name = "GPIO_ENTERING_RW";
+		};
+		gpio_ec_gsc_packet_mode: ec_gsc_packet_mode {
+			gpios = <&gpioh 1 GPIO_OUTPUT>;
+			enum-name = "GPIO_PACKET_MODE_EN";
+		};
+		gpio_ec_pch_wake_odl: ec_pch_wake_odl {
+			gpios = <&gpiob 2 GPIO_ODR_LOW>;
+		};
+		gpio_ec_prochot_odl: ec_prochot_odl {
+			gpios = <&gpioi 1 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>;
+		};
+		gpio_ec_soc_dsw_pwrok: ec_soc_dsw_pwrok {
+			gpios = <&gpiol 7 GPIO_OUTPUT>;
+			no-auto-init;
+		};
+		gpio_ec_soc_int_odl: ec_soc_int_odl {
+			gpios = <&gpiod 5 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_EC_INT_L";
+		};
+		gpio_ec_soc_pch_pwrok_od: ec_soc_pch_pwrok_od {
+			gpios = <&gpiod 6 GPIO_ODR_HIGH>;
+			no-auto-init;
+		};
+		gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl {
+			gpios = <&gpiob 6 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_PCH_PWRBTN_L";
+		};
+		gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l {
+			gpios = <&gpioh 0 GPIO_OUTPUT>;
+			no-auto-init;
+		};
+		gpio_ec_soc_rtcrst: ec_soc_rtcrst {
+			gpios = <&gpiok 2 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_sys_pwrok: ec_soc_sys_pwrok {
+			gpios = <&gpiof 2 GPIO_OUTPUT>;
+			no-auto-init;
+		};
+		gpio_ec_soc_vccst_pwrgd_od: ec_soc_vccst_pwrgd_od {
+			gpios = <&gpioe 5 GPIO_ODR_HIGH>;
+			no-auto-init;
+		};
+		gpio_ec_wp_odl: ec_wp_odl {
+			gpios = <&gpioa 6 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_en_pp3300_s5: en_pp3300_s5 {
+			gpios = <&gpioc 5 GPIO_OUTPUT>;
+			enum-name = "GPIO_TEMP_SENSOR_POWER";
+			no-auto-init;
+		};
+		gpio_en_pp5000_pen_x: en_pp5000_pen_x {
+			gpios = <&gpiob 5 GPIO_OUTPUT>;
+		};
+		gpio_en_pp5000_s5: en_pp5000_s5 {
+			gpios = <&gpiok 5 GPIO_OUTPUT>;
+			no-auto-init;
+		};
+		gpio_en_slp_z: en_slp_z {
+			gpios = <&gpiok 3 GPIO_OUTPUT>;
+		};
+		gpio_en_usb_a0_vbus: en_usb_a0_vbus {
+			gpios = <&gpiol 6 GPIO_OUTPUT>;
+		};
+		gpio_en_usb_a1_vbus: en_usb_a1_vbus {
+			gpios = <&gpiof 0 GPIO_OUTPUT>;
+		};
+		gpio_en_usb_c0_cc1_vconn: en_usb_c0_cc1_vconn {
+			gpios = <&gpioh 4 GPIO_OUTPUT>;
+		};
+		gpio_en_usb_c0_cc2_vconn: en_usb_c0_cc2_vconn {
+			gpios = <&gpioh 6 GPIO_OUTPUT>;
+		};
+		gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl {
+			gpios = <&gpioe 2 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		gpio_imvp91_vrrdy_od: imvp91_vrrdy_od {
+			gpios = <&gpioj 4 GPIO_INPUT>;
+			no-auto-init;
+		};
+		gpio_lid_open: lid_open {
+			gpios = <&gpiof 3 GPIO_INPUT>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+		gpio_pen_detect_odl: pen_detect_odl {
+			gpios = <&gpioj 1 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_pg_pp1050_mem_s3_od: pg_pp1050_mem_s3_od {
+			gpios = <&gpiod 3 GPIO_INPUT>;
+		};
+		gpio_pg_pp5000_s5_od: pg_pp5000_s5_od {
+			gpios = <&gpioe 3 GPIO_INPUT>;
+		};
+		gpio_rsmrst_pwrgd_l: rsmrst_pwrgd_l {
+			gpios = <&gpioe 1 GPIO_INPUT_PULL_UP>;
+			no-auto-init;
+		};
+		gpio_slp_s0_l: slp_s0_l {
+			gpios = <&gpioe 4 GPIO_INPUT>;
+			no-auto-init;
+		};
+		gpio_slp_s3_l: slp_s3_l {
+			gpios = <&gpioh 3 GPIO_INPUT>;
+			no-auto-init;
+		};
+		gpio_slp_s4_l: slp_s4_l {
+			gpios = <&gpioi 5 GPIO_INPUT>;
+		};
+		gpio_slp_sus_l: slp_sus_l {
+			gpios = <&gpiog 2 GPIO_INPUT>;
+			no-auto-init;
+		};
+		gpio_sub_usb_a1_ilimit_sdp: sub_usb_a1_ilimit_sdp {
+			gpios = <&gpiof 1 GPIO_OUTPUT>;
+			enum-name = "GPIO_USB2_ILIM_SEL";
+		};
+		gpio_sys_rst_odl: sys_rst_odl {
+			gpios = <&gpiod 1 GPIO_ODR_HIGH>;
+			no-auto-init;
+		};
+		gpio_usb_a0_ilimit_sdp: usb_a0_ilimit_sdp {
+			gpios = <&gpiol 5 GPIO_OUTPUT>;
+			enum-name = "GPIO_USB1_ILIM_SEL";
+		};
+		gpio_usb_c0_frs: usb_c0_frs {
+			gpios = <&gpioc 4 GPIO_OUTPUT>;
+		};
+		gpio_usb_c0_int_odl: usb_c0_int_odl {
+			gpios = <&gpiok 0 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_usb_c1_int_odl: usb_c1_int_odl {
+			gpios = <&gpioe 6 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_vccin_aux_vid0: vccin_aux_vid0 {
+			gpios = <&gpiod 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		gpio_vccin_aux_vid1: vccin_aux_vid1 {
+			gpios = <&gpiok 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		gpio_c1_charger_led_white_l: c1_charger_led_white_l {
+			gpios = <&gpiol 4 GPIO_OUTPUT_HIGH>;
+		};
+		gpio_c1_charger_led_amber_l: c1_charger_led_amber_l {
+			gpios = <&gpiod 4 GPIO_OUTPUT_HIGH>;
+		};
+		gpio_c0_charger_led_white_l: c0_charger_led_white_l {
+			gpios = <&gpioc 3 GPIO_OUTPUT_HIGH>;
+		};
+		gpio_c0_charger_led_amber_l: c0_charger_led_amber_l {
+			gpios = <&gpioj 7 GPIO_OUTPUT_HIGH>;
+		};
+		gpio_ec_kso_02_inv: ec_kso_02_inv {
+			gpios = <&gpioksol 2 GPIO_OUTPUT_HIGH>;
+			enum-name = "GPIO_KBD_KSO2";
+		};
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		i2c_ec_i2c_eeprom: ec_i2c_eeprom {
+			i2c-port = <&i2c0>;
+			enum-names = "I2C_PORT_EEPROM";
+		};
+		i2c_ec_i2c_batt: ec_i2c_batt {
+			i2c-port = <&i2c1>;
+			enum-names = "I2C_PORT_BATTERY";
+		};
+		i2c_ec_i2c_sensor: ec_i2c_sensor {
+			i2c-port = <&i2c2>;
+			enum-names = "I2C_PORT_SENSOR";
+		};
+		i2c_ec_i2c_sub_usb_c1: ec_i2c_sub_usb_c1 {
+			i2c-port = <&i2c4>;
+			enum-names = "I2C_PORT_USB_C1_TCPC";
+		};
+		i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 {
+			i2c-port = <&i2c5>;
+			enum-names = "I2C_PORT_USB_C0_TCPC";
+		};
+	};
+};
diff --git a/zephyr/program/nissa/yaviks/keyboard.dtsi b/zephyr/program/nissa/yaviks/keyboard.dtsi
new file mode 100644
index 0000000000..87d7d718fa
--- /dev/null
+++ b/zephyr/program/nissa/yaviks/keyboard.dtsi
@@ -0,0 +1,72 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	kblight {
+		compatible = "cros-ec,kblight-pwm";
+		/*
+		 * Use 324 Hz so that 32Khz clock source is used,
+		 * which is not gated in power saving mode.
+		 */
+		pwms = <&pwm0 0 PWM_HZ(324) PWM_POLARITY_NORMAL>;
+	};
+};
+
+&pwm0 {
+	status = "okay";
+	prescaler-cx = <PWM_PRESCALER_C4>;
+	pinctrl-0 = <&pwm0_gpa0_default>;
+	pinctrl-names = "default";
+};
+
+&cros_kb_raw {
+	status = "okay";
+	/* No KSO2 (it's inverted and implemented by GPIO) */
+	pinctrl-0 = <&ksi0_default
+		     &ksi1_default
+		     &ksi2_default
+		     &ksi3_default
+		     &ksi4_default
+		     &ksi5_default
+		     &ksi6_default
+		     &ksi7_default
+		     &kso0_default
+		     &kso1_default
+		     &kso3_default
+		     &kso4_default
+		     &kso5_default
+		     &kso6_default
+		     &kso7_default
+		     &kso8_default
+		     &kso9_default
+		     &kso10_default
+		     &kso11_default
+		     &kso12_default
+		     &kso13_default
+		     &kso14_default>;
+	pinctrl-1 = <&ksi0_sleep
+		     &ksi1_sleep
+		     &ksi2_sleep
+		     &ksi3_sleep
+		     &ksi4_sleep
+		     &ksi5_sleep
+		     &ksi6_sleep
+		     &ksi7_sleep
+		     &kso0_sleep
+		     &kso1_sleep
+		     &kso3_sleep
+		     &kso4_sleep
+		     &kso5_sleep
+		     &kso6_sleep
+		     &kso7_sleep
+		     &kso8_sleep
+		     &kso9_sleep
+		     &kso10_sleep
+		     &kso11_sleep
+		     &kso12_sleep
+		     &kso13_sleep
+		     &kso14_sleep>;
+	pinctrl-names = "default", "sleep";
+};
diff --git a/zephyr/program/nissa/yaviks/overlay.dtsi b/zephyr/program/nissa/yaviks/overlay.dtsi
new file mode 100644
index 0000000000..a93b02c51c
--- /dev/null
+++ b/zephyr/program/nissa/yaviks/overlay.dtsi
@@ -0,0 +1,376 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <cros/thermistor/thermistor.dtsi>
+#include <dt-bindings/usb_pd_tcpm.h>
+
+/ {
+	aliases {
+		gpio-cbi-wp = &gpio_ec_cbi_wp;
+		gpio-wp = &gpio_ec_wp_odl;
+		int-wp = &int_wp_l;
+	};
+
+	ec-console {
+		compatible = "ec-console";
+		disabled = "events", "lpc", "hostcmd";
+	};
+
+	batteries {
+		default_battery: cosmx {
+			compatible = "cosmx,gh02047xl", "battery-smart";
+		};
+		dynapack_atl_gh02047xl {
+			compatible = "dynapack,atl_gh02047xl", "battery-smart";
+		};
+		dynapack_cosmx_gh02047xl {
+			compatible = "dynapack,cosmx_gh02047xl", "battery-smart";
+		};
+		smp_coslight_gh02047xl {
+			compatible = "smp,coslight_gh02047xl", "battery-smart";
+		};
+		smp_highpower_gh02047xl {
+			compatible = "smp,highpower_gh02047xl", "battery-smart";
+		};
+		default_battery_3s:cosmx_si03058xl {
+			compatible = "cosmx,si03058xl", "battery-smart";
+		};
+		smp_highpower_si03058xl {
+			compatible = "smp,highpower_si03058xl", "battery-smart";
+		};
+		smp_si03054xl {
+			compatible = "smp,si03054xl", "battery-smart";
+		};
+	};
+
+	hibernate-wake-pins {
+		compatible = "cros-ec,hibernate-wake-pins";
+		wakeup-irqs = <
+			&int_power_button
+			&int_lid_open
+		>;
+	};
+
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_power_button: power_button {
+			irq-pin = <&gpio_gsc_ec_pwr_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_button_interrupt";
+		};
+		int_wp_l: wp_l {
+			irq-pin = <&gpio_ec_wp_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "switch_interrupt";
+		};
+		int_lid_open: lid_open {
+			irq-pin = <&gpio_lid_open>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "lid_interrupt";
+		};
+		int_usb_c0: usb_c0 {
+			irq-pin = <&gpio_usb_c0_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "usb_c0_interrupt";
+		};
+		int_usb_c1: usb_c1 {
+			irq-pin = <&gpio_usb_c1_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "usb_c1_interrupt";
+		};
+	};
+
+	unused-pins {
+		compatible = "unused-gpios";
+		unused-gpios = <&gpioa 7 0>,
+			       <&gpioc 0 0>,
+			       <&gpioc 6 0>,
+			       <&gpiod 7 0>,
+			       <&gpioh 2 0>,
+			       <&gpioi 6 0>,
+			       <&gpioi 7 0>,
+			       <&gpioj 0 0>,
+			       <&gpioj 3 0>,
+			       <&gpiok 7 GPIO_OUTPUT>;
+	};
+
+	named-gpios {
+		/*
+		 * EC doesn't take any specific action on CC/SBU disconnect due to
+		 * fault, but this definition is useful for hardware testing.
+		 */
+		gpio_usb_c0_prot_fault_odl: usb_c0_prot_fault_odl {
+			gpios = <&gpiok 6 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_fan_enable: fan-enable {
+			gpios = <&gpioa 1 GPIO_OUTPUT>;
+			no-auto-init;
+		};
+	};
+
+	temp_cpu_thermistor: cpu {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_1>;
+	};
+	temp_5v_regulator_thermistor: 5v-regulator {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_2>;
+	};
+	temp_charger_thermistor: charger {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_3>;
+	};
+
+	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
+		temp_cpu: cpu {
+			temp_fan_off = <45>;
+			temp_fan_max = <60>;
+			temp_host_high = <75>;
+			temp_host_halt = <85>;
+			temp_host_release_high = <65>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_cpu_thermistor>;
+		};
+		temp_5v_regulator: 5v-regulator {
+			temp_fan_off = <50>;
+			temp_fan_max = <65>;
+			temp_host_high = <75>;
+			temp_host_halt = <85>;
+			temp_host_release_high = <65>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_5v_regulator_thermistor>;
+		};
+		temp_charger: charger {
+			temp_fan_off = <50>;
+			temp_fan_max = <65>;
+			temp_host_high = <80>;
+			temp_host_halt = <85>;
+			temp_host_release_high = <75>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_charger_thermistor>;
+		};
+	};
+
+	usba {
+		compatible = "cros-ec,usba-port-enable-pins";
+		/*
+		 * ILIM_SEL pins are referred to by legacy enum name,
+		 * GPIO_USB*_ILIM_SEL.
+		 */
+		enable-pins = <&gpio_en_usb_a0_vbus &gpio_en_usb_a1_vbus>;
+		status = "okay";
+	};
+
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+			bc12 = <&bc12_port0>;
+			chg = <&chg_port0>;
+			tcpc = <&usbpd0>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_0>;
+			};
+		};
+		port0-muxes {
+			virtual_mux_0: virtual-mux-0 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+		port1@1 {
+			compatible = "named-usbc-port";
+			reg = <1>;
+			bc12 = <&bc12_port1>;
+			chg = <&chg_port1>;
+			tcpc = <&tcpc_port1>;
+			usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_1 &tcpci_mux_1>;
+			};
+			usb_mux_chain_1_no_mux: usb-mux-chain-1-no-mux {
+				compatible = "cros-ec,usb-mux-chain";
+				alternative-chain;
+				usb-muxes = <&virtual_mux_1>;
+			};
+		};
+		port1-muxes {
+			virtual_mux_1: virtual-mux-1 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+			tcpci_mux_1: tcpci-mux-1 {
+				compatible = "parade,usbc-mux-ps8xxx";
+			};
+		};
+	};
+};
+
+&binman {
+	ec-rw {
+		size = <0x50000>;
+		rw-fw {
+			rw-fwid {
+				/* Fix the lcoation of the FWID to the
+				 * last 32 bytes of the flash. This
+				 * ensures the RW entries in the FMAP
+				 * stored in the RO section of flash
+				 * are always correct.
+				 */
+				offset = <(0x50000 - 32)>;
+			};
+		};
+	};
+	pad-after = <0x50000>;
+};
+
+&thermistor_3V3_51K1_47K_4050B {
+	status = "okay";
+};
+
+&adc_ec_vsense_pp3300_s5 {
+	/*
+	 * Voltage divider on input has 47k upper and 220k lower legs with 3 V
+	 * full-scale reading on the ADC. Apply the largest possible multiplier
+	 * (without overflowing int32) to get the best possible approximation
+	 * of the actual ratio, but derate by a factor of two to ensure
+	 * unexpectedly high values won't overflow.
+	 */
+	mul = <(715828 / 2)>;
+	div = <(589820 / 2)>;
+};
+
+&adc0 {
+	pinctrl-0 = <&adc0_ch0_gpi0_default
+		     &adc0_ch2_gpi2_default
+		     &adc0_ch3_gpi3_default
+		     &adc0_ch13_gpl0_default
+		     &adc0_ch14_gpl1_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&pinctrl {
+	i2c4_clk_gpe0_sleep: i2c4_clk_gpe0_sleep {
+		pinmuxs = <&pinctrle 0 IT8XXX2_ALT_DEFAULT>;
+	};
+	i2c4_data_gpe7_sleep: i2c4_data_gpe7_sleep {
+		pinmuxs = <&pinctrle 7 IT8XXX2_ALT_DEFAULT>;
+	};
+	i2c2_clk_gpf6_default: i2c2_clk_gpf6_default {
+		gpio-voltage = "1v8";
+	};
+	i2c2_data_gpf7_default: i2c2_data_gpf7_default {
+		gpio-voltage = "1v8";
+	};
+};
+
+&i2c0 {
+	label = "I2C_EEPROM";
+	clock-frequency = <I2C_BITRATE_FAST>;
+
+	cbi_eeprom: eeprom@50 {
+		compatible = "atmel,at24";
+		reg = <0x50>;
+		label = "EEPROM_CBI";
+		size = <2048>;
+		pagesize = <16>;
+		address-width = <8>;
+		timeout = <5>;
+	};
+	pinctrl-0 = <&i2c0_clk_gpb3_default
+		     &i2c0_data_gpb4_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&i2c1 {
+	label = "I2C_BATTERY";
+	clock-frequency = <50000>;
+	pinctrl-0 = <&i2c1_clk_gpc1_default
+		     &i2c1_data_gpc2_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&i2c2 {
+	label = "I2C_SENSOR";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c2_clk_gpf6_default
+		     &i2c2_data_gpf7_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&i2c4 {
+	label = "I2C_SUB_C1_TCPC";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+	pinctrl-0 = <&i2c4_clk_gpe0_default
+		     &i2c4_data_gpe7_default>;
+	pinctrl-1 = <&i2c4_clk_gpe0_sleep
+		     &i2c4_data_gpe7_sleep>;
+	pinctrl-names = "default", "sleep";
+	status = "okay";
+
+	bc12_port1: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+	};
+
+	chg_port1: sm5803@32 {
+		compatible = "siliconmitus,sm5803";
+		status = "okay";
+		reg = <0x32>;
+	};
+
+	tcpc_port1: ps8745@b {
+		compatible = "parade,ps8xxx";
+		reg = <0xb>;
+		tcpc-flags = <(TCPC_FLAGS_TCPCI_REV2_0)>;
+	};
+};
+
+&i2c_ec_i2c_sub_usb_c1 {
+	/*
+	 * Dynamic speed setting is used for AP-controlled firmware update
+	 * of PS8745 TCPC/redriver: the AP lowers speed to 400 kHz in order
+	 * to use more efficient window programming, then sets it back when
+	 * done.
+	 */
+	dynamic-speed;
+};
+
+&i2c5 {
+	label = "I2C_USB_C0_TCPC";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+	pinctrl-0 = <&i2c5_clk_gpa4_default
+		     &i2c5_data_gpa5_default>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	bc12_port0: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+	};
+
+	chg_port0: sm5803@32 {
+		compatible = "siliconmitus,sm5803";
+		status = "okay";
+		reg = <0x32>;
+	};
+};
+
+&usbpd0 {
+	status = "okay";
+};
diff --git a/zephyr/program/nissa/yaviks/power_signals.dtsi b/zephyr/program/nissa/yaviks/power_signals.dtsi
new file mode 100644
index 0000000000..d64ac83150
--- /dev/null
+++ b/zephyr/program/nissa/yaviks/power_signals.dtsi
@@ -0,0 +1,180 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	chosen {
+		intel-ap-pwrseq,espi = &espi0;
+	};
+
+	common-pwrseq {
+		compatible = "intel,ap-pwrseq";
+
+		sys-pwrok-delay = <10>;
+		all-sys-pwrgd-timeout = <20>;
+	};
+
+	pwr-en-pp5000-s5 {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PP5000_S5 enable output to regulator";
+		enum-name = "PWR_EN_PP5000_A";
+		gpios = <&gpiok 5 0>;
+		output;
+	};
+	pwr-en-pp3300-s5 {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PP3300_S5 enable output to LS";
+		enum-name = "PWR_EN_PP3300_A";
+		gpios = <&gpioc 5 0>;
+		output;
+	};
+	pwr-pg-ec-rsmrst-odl {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST power good from regulator";
+		enum-name = "PWR_RSMRST";
+		gpios = <&gpioe 1 0>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-ec-pch-rsmrst-odl {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST output to PCH";
+		enum-name = "PWR_EC_PCH_RSMRST";
+		gpios = <&gpioh 0 0>;
+		output;
+	};
+	pwr-slp-s0-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_S0_L input from PCH";
+		enum-name = "PWR_SLP_S0";
+		gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-slp-s3-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_S3_L input from PCH";
+		enum-name = "PWR_SLP_S3";
+		gpios = <&gpioh 3 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-slp-sus-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_SUS_L input from PCH";
+		enum-name = "PWR_SLP_SUS";
+		gpios = <&gpiog 2 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-ec-soc-dsw-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "DSW_PWROK output to PCH";
+		enum-name = "PWR_EC_SOC_DSW_PWROK";
+		gpios = <&gpiol 7 0>;
+		output;
+	};
+	pwr-vccst-pwrgd-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "VCCST_PWRGD output to PCH";
+		enum-name = "PWR_VCCST_PWRGD";
+		gpios = <&gpioe 5 (GPIO_OPEN_DRAIN | GPIO_VOLTAGE_1P8)>;
+		output;
+	};
+	pwr-imvp9-vrrdy-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "VRRDY input from IMVP9";
+		enum-name = "PWR_IMVP9_VRRDY";
+		gpios = <&gpioj 4 0>;
+	};
+	pwr-pch-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PCH_PWROK output to PCH";
+		enum-name = "PWR_PCH_PWROK";
+		gpios = <&gpiod 6 GPIO_OPEN_DRAIN>;
+		output;
+	};
+	pwr-ec-pch-sys-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_PWROK output to PCH";
+		enum-name = "PWR_EC_PCH_SYS_PWROK";
+		gpios = <&gpiof 2 0>;
+		output;
+	};
+	pwr-sys-rst-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_RESET# output to PCH";
+		enum-name = "PWR_SYS_RST";
+		gpios = <&gpiod 1 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>;
+		output;
+	};
+	pwr-slp-s4 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S4 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S4";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4";
+		vw-invert;
+	};
+	pwr-slp-s5 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S5 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S5";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5";
+		vw-invert;
+	};
+	pwr-all-sys-pwrgd {
+		/*
+		 * This is a board level signal, since this
+		 * signal needs some special processing.
+		 */
+		compatible = "intel,ap-pwrseq-external";
+		dbg-label = "Combined all power good";
+		enum-name = "PWR_ALL_SYS_PWRGD";
+	};
+	pwr-adc-pp3300 {
+		compatible = "intel,ap-pwrseq-adc";
+		dbg-label = "PP3300_PROC";
+		enum-name = "PWR_DSW_PWROK";
+		trigger-high = <&vcmp0>;
+		trigger-low = <&vcmp1>;
+	};
+	pwr-adc-pp1p05 {
+		compatible = "intel,ap-pwrseq-adc";
+		dbg-label = "PP1P05_PROC";
+		enum-name = "PWR_PG_PP1P05";
+		trigger-high = <&vcmp2>;
+		trigger-low = <&vcmp3>;
+	};
+
+};
+
+&vcmp0 {
+	status = "okay";
+	scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>;
+	comparison = <IT8XXX2_VCMP_GREATER>;
+	/*
+	 * This is 90% of nominal voltage considering voltage
+	 * divider on ADC input.
+	 */
+	threshold-mv = <2448>;
+	io-channels = <&adc0 0>;
+};
+&vcmp1 {
+	status = "okay";
+	scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>;
+	comparison = <IT8XXX2_VCMP_LESS_OR_EQUAL>;
+	threshold-mv = <2448>;
+	io-channels = <&adc0 0>;
+};
+&vcmp2 {
+	status = "okay";
+	scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>;
+	comparison = <IT8XXX2_VCMP_GREATER>;
+	/* Setting at 90% of nominal voltage */
+	threshold-mv = <945>;
+	io-channels = <&adc0 14>;
+};
+&vcmp3 {
+	status = "okay";
+	scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>;
+	comparison = <IT8XXX2_VCMP_LESS_OR_EQUAL>;
+	threshold-mv = <945>;
+	io-channels = <&adc0 14>;
+};
diff --git a/zephyr/program/nissa/yaviks/project.conf b/zephyr/program/nissa/yaviks/project.conf
new file mode 100644
index 0000000000..06c63967c6
--- /dev/null
+++ b/zephyr/program/nissa/yaviks/project.conf
@@ -0,0 +1,50 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_BOARD_YAVIKS=y
+
+# FW image
+# TODO: Once this configuration is configured with binman's size property
+# by default, it can be removed.
+CONFIG_CROS_EC_RW_SIZE=0x50000
+
+# Ensure recovery key combination (esc+refresh+power) is reliable: b/236580049
+CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI3=y
+CONFIG_PLATFORM_EC_KEYBOARD_REFRESH_ROW3=y
+
+# Sensors: disabled; yaviks is clamshell-only
+CONFIG_PLATFORM_EC_LID_ANGLE=n
+CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=n
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=n
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=n
+CONFIG_PLATFORM_EC_ACCEL_FIFO=n
+CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=n
+CONFIG_PLATFORM_EC_GMR_TABLET_MODE=n
+CONFIG_PLATFORM_EC_TABLET_MODE=n
+CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=n
+CONFIG_PLATFORM_EC_VOLUME_BUTTONS=n
+CONFIG_PLATFORM_EC_MAX_SENSOR_FREQ_MILLIHZ=100000
+
+# Keyboard
+CONFIG_PLATFORM_EC_KEYBOARD_KEYPAD=y
+CONFIG_PLATFORM_EC_KBLIGHT_ENABLE_PIN=n
+CONFIG_PLATFORM_EC_KEYBOARD_FACTORY_TEST=y
+
+# Fan
+CONFIG_PLATFORM_EC_CUSTOM_FAN_CONTROL=y
+
+# LED
+CONFIG_PLATFORM_EC_LED_PWM=n
+
+CONFIG_NISSA_SUB_BOARD=n
+
+# Both ports use a SLGC55545 smart switch with CTL1..3 fixed high,
+# for SDP2 or CDP only.
+CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART=y
+CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_CDP_SDP_ONLY=y
+CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_DEFAULT_CDP=y
+CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_INVERTED=y
+
+# Charger
+CONFIG_PLATFORM_EC_CHARGER_INPUT_CURRENT_DERATE_PCT=0
diff --git a/zephyr/program/nissa/yaviks/project.overlay b/zephyr/program/nissa/yaviks/project.overlay
new file mode 100644
index 0000000000..97f431022c
--- /dev/null
+++ b/zephyr/program/nissa/yaviks/project.overlay
@@ -0,0 +1,13 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "../shi.dtsi"
+
+#include "cbi.dtsi"
+#include "fan.dtsi"
+#include "gpio.dtsi"
+#include "keyboard.dtsi"
+#include "overlay.dtsi"
+#include "power_signals.dtsi"
diff --git a/zephyr/program/nissa/yaviks/src/board.c b/zephyr/program/nissa/yaviks/src/board.c
new file mode 100644
index 0000000000..f8f946fa32
--- /dev/null
+++ b/zephyr/program/nissa/yaviks/src/board.c
@@ -0,0 +1,31 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* yaviks hardware configuration */
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "task.h"
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/sys/printk.h>
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+__override uint8_t board_get_usb_pd_port_count(void)
+{
+	return 2;
+}
+/*
+ * Enable interrupts
+ */
+static void board_init(void)
+{
+	/*
+	 * Enable USB-C interrupts.
+	 */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0));
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1));
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/zephyr/program/nissa/yaviks/src/charger.c b/zephyr/program/nissa/yaviks/src/charger.c
new file mode 100644
index 0000000000..70a1f77bf3
--- /dev/null
+++ b/zephyr/program/nissa/yaviks/src/charger.c
@@ -0,0 +1,73 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "battery_fuel_gauge.h"
+#include "charger.h"
+#include "console.h"
+#include "driver/charger/sm5803.h"
+#include "extpower.h"
+#include "usb_pd.h"
+
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+int extpower_is_present(void)
+{
+	int port;
+	int rv;
+	bool acok;
+
+	for (port = 0; port < board_get_usb_pd_port_count(); port++) {
+		rv = sm5803_is_acok(port, &acok);
+		if ((rv == EC_SUCCESS) && acok)
+			return 1;
+	}
+
+	return 0;
+}
+
+/*
+ * Yaviks does not have a GPIO indicating whether extpower is present,
+ * so detect using the charger(s).
+ */
+__override void board_check_extpower(void)
+{
+	static int last_extpower_present;
+	int extpower_present = extpower_is_present();
+
+	if (last_extpower_present ^ extpower_present)
+		extpower_handle_update(extpower_present);
+
+	last_extpower_present = extpower_present;
+}
+
+__override void board_hibernate(void)
+{
+	/* Shut down the chargers */
+	if (board_get_usb_pd_port_count() == 2)
+		sm5803_hibernate(CHARGER_SECONDARY);
+	sm5803_hibernate(CHARGER_PRIMARY);
+	LOG_INF("Charger(s) hibernated");
+	cflush();
+}
+
+__override int board_get_default_battery_type(void)
+{
+	int type = DEFAULT_BATTERY_TYPE;
+	int cells;
+
+	if (charger_get_battery_cells(CHARGER_PRIMARY, &cells) == EC_SUCCESS) {
+		if (cells == 3)
+			type = DEFAULT_BATTERY_TYPE_3S;
+		if (cells != 2 && cells != 3)
+			LOG_ERR("Unexpected number of cells");
+	} else {
+		LOG_ERR("Failed to get default battery type");
+	}
+
+	return type;
+}
diff --git a/zephyr/program/nissa/yaviks/src/fan.c b/zephyr/program/nissa/yaviks/src/fan.c
new file mode 100644
index 0000000000..07517abbe9
--- /dev/null
+++ b/zephyr/program/nissa/yaviks/src/fan.c
@@ -0,0 +1,36 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "cros_cbi.h"
+#include "fan.h"
+#include "gpio/gpio.h"
+#include "hooks.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/logging/log.h>
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+static void fan_init(void)
+{
+	int ret;
+	uint32_t val;
+	/*
+	 * Retrieve the fan config.
+	 */
+	ret = cros_cbi_get_fw_config(FW_FAN, &val);
+	if (ret != 0) {
+		LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_FAN);
+		return;
+	}
+	if (val != FW_FAN_PRESENT) {
+		/* Disable the fan */
+		fan_set_count(0);
+	} else {
+		/* Configure the fan enable GPIO */
+		gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_fan_enable),
+				      GPIO_OUTPUT);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, fan_init, HOOK_PRIO_POST_FIRST);
diff --git a/zephyr/program/nissa/yaviks/src/keyboard.c b/zephyr/program/nissa/yaviks/src/keyboard.c
new file mode 100644
index 0000000000..22fa2df996
--- /dev/null
+++ b/zephyr/program/nissa/yaviks/src/keyboard.c
@@ -0,0 +1,125 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "cros_cbi.h"
+#include "ec_commands.h"
+#include "gpio_it8xxx2.h"
+#include "hooks.h"
+#include "keyboard_8042_sharedlib.h"
+#include "keyboard_scan.h"
+#include "timer.h"
+
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/* Increase from 50 us, because KSO_02 passes through the H1. */
+	.output_settle_us = 80,
+	/* Other values should be the same as the default configuration. */
+	.debounce_down_us = 9 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x1c, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xa4, 0xff, 0xf6, 0x55, 0xfe, 0xff, 0xff, 0xff, /* full set */
+	},
+};
+
+static const struct ec_response_keybd_config yaviks_kb_w_kb_light = {
+	.num_top_row_keys = 13,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_KBD_BKLIGHT_TOGGLE,	/* T8 */
+		TK_PLAY_PAUSE,		/* T9 */
+		TK_MICMUTE,		/* T10 */
+		TK_VOL_MUTE,		/* T11 */
+		TK_VOL_DOWN,		/* T12 */
+		TK_VOL_UP,		/* T13 */
+	},
+	.capabilities = KEYBD_CAP_NUMERIC_KEYPAD,
+};
+
+static const struct ec_response_keybd_config yaviks_kb_wo_kb_light = {
+	.num_top_row_keys = 13,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_PLAY_PAUSE,		/* T8 */
+		TK_MICMUTE,		/* T9 */
+		TK_VOL_MUTE,		/* T10 */
+		TK_VOL_DOWN,		/* T11 */
+		TK_VOL_UP,		/* T12 */
+		TK_MENU,		/* T13 */
+	},
+	.capabilities = KEYBD_CAP_NUMERIC_KEYPAD,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	uint32_t val;
+
+	cros_cbi_get_fw_config(FW_KB_BACKLIGHT, &val);
+
+	if (val == FW_KB_BACKLIGHT_OFF)
+		return &yaviks_kb_wo_kb_light;
+	else
+		return &yaviks_kb_w_kb_light;
+}
+
+/*
+ * Keyboard layout decided by FW config.
+ */
+static void kb_layout_init(void)
+{
+	int ret;
+	uint32_t val;
+
+	ret = cros_cbi_get_fw_config(FW_KB_LAYOUT, &val);
+	if (ret != 0) {
+		LOG_ERR("Error retrieving CBI FW_CONFIG field %d",
+			FW_KB_LAYOUT);
+		return;
+	}
+	/*
+	 * If keyboard is US2(FW_KB_LAYOUT_US2), we need translate right ctrl
+	 * to backslash(\|) key.
+	 */
+	if (val == FW_KB_LAYOUT_US2)
+		set_scancode_set2(4, 0, get_scancode_set2(2, 7));
+}
+DECLARE_HOOK(HOOK_INIT, kb_layout_init, HOOK_PRIO_POST_FIRST);
+
+/*
+ * Map keyboard connector pins to EC GPIO pins for factory test.
+ * Pins mapped to {-1, -1} are skipped.
+ * The connector has 30 pins total, and there is no pin 0.
+ */
+const int keyboard_factory_scan_pins[][2] = {
+	{ -1, -1 },	  { GPIO_KSOH, 4 }, { GPIO_KSOH, 0 }, { GPIO_KSOH, 1 },
+	{ GPIO_KSOH, 3 }, { GPIO_KSOH, 2 }, { -1, -1 },	      { -1, -1 },
+	{ GPIO_KSOL, 5 }, { GPIO_KSOL, 6 }, { -1, -1 },	      { GPIO_KSOL, 3 },
+	{ GPIO_KSOL, 2 }, { GPIO_KSI, 0 },  { GPIO_KSOL, 1 }, { GPIO_KSOL, 4 },
+	{ GPIO_KSI, 3 },  { GPIO_KSI, 2 },  { GPIO_KSOL, 0 }, { GPIO_KSI, 5 },
+	{ GPIO_KSI, 4 },  { GPIO_KSOL, 7 }, { GPIO_KSI, 6 },  { GPIO_KSI, 7 },
+	{ GPIO_KSI, 1 },  { -1, -1 },	    { GPIO_KSOH, 5 }, { -1, -1 },
+	{ GPIO_KSOH, 6 }, { -1, -1 },	    { -1, -1 },
+};
+const int keyboard_factory_scan_pins_used =
+	ARRAY_SIZE(keyboard_factory_scan_pins);
diff --git a/zephyr/program/nissa/yaviks/src/led.c b/zephyr/program/nissa/yaviks/src/led.c
new file mode 100644
index 0000000000..a6aa50009e
--- /dev/null
+++ b/zephyr/program/nissa/yaviks/src/led.c
@@ -0,0 +1,231 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "chipset.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "led_common.h"
+
+#include <stdint.h>
+
+#define BAT_LED_ON 0
+#define BAT_LED_OFF 1
+
+#define BATT_LOW_BCT 10
+
+#define LED_TICKS_PER_CYCLE 4
+#define LED_TICKS_PER_CYCLE_S3 4
+#define LED_ON_TICKS 2
+#define POWER_LED_ON_S3_TICKS 2
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_LEFT_LED,
+					     EC_LED_ID_RIGHT_LED };
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+enum led_color {
+	LED_OFF = 0,
+	LED_AMBER,
+	LED_WHITE,
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
+};
+
+enum led_port { LEFT_PORT = 0, RIGHT_PORT };
+
+static void led_set_color_battery(int port, enum led_color color)
+{
+	const struct gpio_dt_spec *amber_led, *white_led;
+
+	if (port == LEFT_PORT) {
+		amber_led = GPIO_DT_FROM_NODELABEL(gpio_c0_charger_led_amber_l);
+		white_led = GPIO_DT_FROM_NODELABEL(gpio_c0_charger_led_white_l);
+	} else if (port == RIGHT_PORT) {
+		amber_led = GPIO_DT_FROM_NODELABEL(gpio_c1_charger_led_amber_l);
+		white_led = GPIO_DT_FROM_NODELABEL(gpio_c1_charger_led_white_l);
+	}
+
+	switch (color) {
+	case LED_WHITE:
+		gpio_pin_set_dt(white_led, BAT_LED_ON);
+		gpio_pin_set_dt(amber_led, BAT_LED_OFF);
+		break;
+	case LED_AMBER:
+		gpio_pin_set_dt(white_led, BAT_LED_OFF);
+		gpio_pin_set_dt(amber_led, BAT_LED_ON);
+		break;
+	case LED_OFF:
+		gpio_pin_set_dt(white_led, BAT_LED_OFF);
+		gpio_pin_set_dt(amber_led, BAT_LED_OFF);
+		break;
+	default:
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	switch (led_id) {
+	case EC_LED_ID_LEFT_LED:
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		break;
+	case EC_LED_ID_RIGHT_LED:
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		break;
+	default:
+		break;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	switch (led_id) {
+	case EC_LED_ID_LEFT_LED:
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_battery(LEFT_PORT, LED_WHITE);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(LEFT_PORT, LED_AMBER);
+		else
+			led_set_color_battery(LEFT_PORT, LED_OFF);
+		break;
+	case EC_LED_ID_RIGHT_LED:
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_battery(RIGHT_PORT, LED_WHITE);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(RIGHT_PORT, LED_AMBER);
+		else
+			led_set_color_battery(RIGHT_PORT, LED_OFF);
+		break;
+	default:
+		return EC_ERROR_PARAM1;
+	}
+
+	return EC_SUCCESS;
+}
+
+/*
+ * Set active charge port color to the parameter, turn off all others.
+ * If no port is active (-1), turn off all LEDs.
+ */
+static void set_active_port_color(enum led_color color)
+{
+	int port = charge_manager_get_active_charge_port();
+
+	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
+		led_set_color_battery(RIGHT_PORT,
+				      (port == RIGHT_PORT) ? color : LED_OFF);
+	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
+		led_set_color_battery(LEFT_PORT,
+				      (port == LEFT_PORT) ? color : LED_OFF);
+}
+
+static void led_set_battery(void)
+{
+	static unsigned int battery_ticks;
+	static int suspend_ticks;
+
+	battery_ticks++;
+
+	/*
+	 * Override battery LEDs for Yaviks, Yaviks is non-power LED
+	 * design, blinking both two side battery white LEDs to indicate
+	 * system suspend with non-charging state.
+	 */
+	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
+	    led_pwr_get_state() != LED_PWRS_CHARGE) {
+		suspend_ticks++;
+
+		led_set_color_battery(RIGHT_PORT,
+				      suspend_ticks % LED_TICKS_PER_CYCLE_S3 <
+						      POWER_LED_ON_S3_TICKS ?
+					      LED_WHITE :
+					      LED_OFF);
+		led_set_color_battery(LEFT_PORT,
+				      suspend_ticks % LED_TICKS_PER_CYCLE_S3 <
+						      POWER_LED_ON_S3_TICKS ?
+					      LED_WHITE :
+					      LED_OFF);
+		return;
+	}
+
+	suspend_ticks = 0;
+
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
+		/* Always indicate when charging, even in suspend. */
+		set_active_port_color(LED_AMBER);
+		break;
+	case LED_PWRS_DISCHARGE:
+		/*
+		 * Blinking amber LEDs slowly if battery is lower 10
+		 * percentage.
+		 */
+		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
+			if (charge_get_percent() < BATT_LOW_BCT)
+				led_set_color_battery(
+					RIGHT_PORT,
+					(battery_ticks % LED_TICKS_PER_CYCLE <
+					 LED_ON_TICKS) ?
+						LED_AMBER :
+						LED_OFF);
+			else
+				led_set_color_battery(RIGHT_PORT, LED_OFF);
+		}
+
+		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) {
+			if (charge_get_percent() < BATT_LOW_BCT)
+				led_set_color_battery(
+					LEFT_PORT,
+					(battery_ticks % LED_TICKS_PER_CYCLE <
+					 LED_ON_TICKS) ?
+						LED_AMBER :
+						LED_OFF);
+			else
+				led_set_color_battery(LEFT_PORT, LED_OFF);
+		}
+		break;
+	case LED_PWRS_ERROR:
+		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
+			led_set_color_battery(
+				RIGHT_PORT,
+				(battery_ticks & 0x1) ? LED_AMBER : LED_OFF);
+		}
+
+		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) {
+			led_set_color_battery(LEFT_PORT, (battery_ticks & 0x1) ?
+								 LED_AMBER :
+								 LED_OFF);
+		}
+		break;
+	case LED_PWRS_CHARGE_NEAR_FULL:
+		set_active_port_color(LED_WHITE);
+		break;
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		set_active_port_color(LED_WHITE);
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		set_active_port_color(
+			(battery_ticks % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
+				LED_AMBER :
+				LED_OFF);
+		break;
+	default:
+		/* Other states don't alter LED behavior */
+		break;
+	}
+}
+
+/* Called by hook task every TICK(IT83xx 500ms) */
+static void led_tick(void)
+{
+	led_set_battery();
+}
+DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
diff --git a/zephyr/program/nissa/yaviks/src/thermal.c b/zephyr/program/nissa/yaviks/src/thermal.c
new file mode 100644
index 0000000000..a22a9a74c0
--- /dev/null
+++ b/zephyr/program/nissa/yaviks/src/thermal.c
@@ -0,0 +1,108 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "fan.h"
+#include "temp_sensor/temp_sensor.h"
+#include "thermal.h"
+#include "util.h"
+
+#include <ap_power/ap_power_interface.h>
+
+#define TEMP_CPU TEMP_SENSOR_ID(DT_NODELABEL(temp_cpu))
+#define TEMP_5V TEMP_SENSOR_ID(DT_NODELABEL(temp_5v_regulator))
+#define TEMP_CHARGER TEMP_SENSOR_ID(DT_NODELABEL(temp_charger))
+
+struct fan_step {
+	/*
+	 * Sensor 1~3 trigger point, set -1 if we're not using this
+	 * sensor to determine fan speed.
+	 */
+	int8_t on[TEMP_SENSOR_COUNT];
+	/*
+	 * Sensor 1~3 trigger point, set -1 if we're not using this
+	 * sensor to determine fan speed.
+	 */
+	int8_t off[TEMP_SENSOR_COUNT];
+	/* Fan rpm */
+	uint16_t rpm[FAN_CH_COUNT];
+};
+
+#define FAN_TABLE_ENTRY(nd)                     \
+	{                                       \
+		.on = DT_PROP(nd, temp_on),     \
+		.off = DT_PROP(nd, temp_off),   \
+		.rpm = DT_PROP(nd, rpm_target), \
+	},
+
+static const struct fan_step fan_step_table[] = { DT_FOREACH_CHILD(
+	DT_INST(0, cros_ec_fan_steps), FAN_TABLE_ENTRY) };
+
+int fan_table_to_rpm(int fan, int *temp)
+{
+	/* current fan level */
+	static int current_level;
+	/* previous sensor temperature */
+	static int prev_tmp[TEMP_SENSOR_COUNT];
+	int i;
+	/*
+	 * Compare the current and previous temperature, we have
+	 * the three paths :
+	 *  1. decreasing path. (check the release point)
+	 *  2. increasing path. (check the trigger point)
+	 *  3. invariant path. (return the current RPM)
+	 *
+	 * Yaviks thermal table V1-1
+	 * Increase path judgment: CPU || (5V && Charger)
+	 * Decrease path judgment: CPU && 5V && Charger
+	 */
+	if (temp[TEMP_CPU] < prev_tmp[TEMP_CPU] ||
+	    temp[TEMP_5V] < prev_tmp[TEMP_5V] ||
+	    temp[TEMP_CHARGER] < prev_tmp[TEMP_CHARGER]) {
+		for (i = current_level; i > 0; i--) {
+			if (temp[TEMP_CPU] < fan_step_table[i].off[TEMP_CPU] &&
+			    temp[TEMP_5V] < fan_step_table[i].off[TEMP_5V] &&
+			    temp[TEMP_CHARGER] <
+				    fan_step_table[i].off[TEMP_CHARGER]) {
+				current_level = i - 1;
+			} else
+				break;
+		}
+	} else if (temp[TEMP_CPU] > prev_tmp[TEMP_CPU] ||
+		   temp[TEMP_5V] > prev_tmp[TEMP_5V] ||
+		   temp[TEMP_CHARGER] > prev_tmp[TEMP_CHARGER]) {
+		for (i = current_level; i < ARRAY_SIZE(fan_step_table); i++) {
+			if (temp[TEMP_CPU] > fan_step_table[i].on[TEMP_CPU] ||
+			    (temp[TEMP_5V] > fan_step_table[i].on[TEMP_5V] &&
+			     temp[TEMP_CHARGER] >
+				     fan_step_table[i].on[TEMP_CHARGER])) {
+				current_level = i + 1;
+			} else
+				break;
+		}
+	}
+	if (current_level < 0)
+		current_level = 0;
+
+	if (current_level >= ARRAY_SIZE(fan_step_table))
+		current_level = ARRAY_SIZE(fan_step_table) - 1;
+
+	for (i = 0; i < TEMP_SENSOR_COUNT; ++i)
+		prev_tmp[i] = temp[i];
+
+	return fan_step_table[current_level].rpm[fan];
+}
+
+void board_override_fan_control(int fan, int *temp)
+{
+	/*
+	 * In common/fan.c pwm_fan_stop() will turn off fan
+	 * when chipset suspend or shutdown.
+	 */
+	if (ap_power_in_state(AP_POWER_STATE_ON)) {
+		fan_set_rpm_mode(fan, 1);
+		fan_set_rpm_target(fan, fan_table_to_rpm(fan, temp));
+	}
+}
diff --git a/zephyr/program/nissa/yaviks/src/usbc.c b/zephyr/program/nissa/yaviks/src/usbc.c
new file mode 100644
index 0000000000..bacf631fb7
--- /dev/null
+++ b/zephyr/program/nissa/yaviks/src/usbc.c
@@ -0,0 +1,379 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_state.h"
+#include "chipset.h"
+#include "driver/charger/sm5803.h"
+#include "driver/tcpm/it83xx_pd.h"
+#include "driver/tcpm/ps8xxx_public.h"
+#include "driver/tcpm/tcpci.h"
+#include "hooks.h"
+#include "system.h"
+#include "usb_mux.h"
+#include "watchdog.h"
+
+#include <zephyr/logging/log.h>
+
+#include <ap_power/ap_power.h>
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+/* Vconn control for integrated ITE TCPC */
+void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
+{
+	/* Vconn control is only for port 0 */
+	if (port)
+		return;
+
+	if (cc_pin == USBPD_CC_PIN_1)
+		gpio_pin_set_dt(
+			GPIO_DT_FROM_NODELABEL(gpio_en_usb_c0_cc1_vconn),
+			!!enabled);
+	else
+		gpio_pin_set_dt(
+			GPIO_DT_FROM_NODELABEL(gpio_en_usb_c0_cc2_vconn),
+			!!enabled);
+}
+
+__override bool pd_check_vbus_level(int port, enum vbus_level level)
+{
+	return sm5803_check_vbus_level(port, level);
+}
+
+/*
+ * Putting chargers into LPM when in suspend reduces power draw by about 8mW
+ * per charger, but also seems critical to correct operation in source mode:
+ * if chargers are not in LPM when a sink is first connected, VBUS sourcing
+ * works even if the partner is later removed (causing LPM entry) and
+ * reconnected (causing LPM exit). If in LPM initially, sourcing VBUS
+ * consistently causes the charger to report (apparently spurious) overcurrent
+ * failures.
+ *
+ * In short, this is important to making things work correctly but we don't
+ * understand why.
+ */
+static void board_chargers_suspend(struct ap_power_ev_callback *const cb,
+				   const struct ap_power_ev_data data)
+{
+	void (*fn)(int chgnum);
+
+	switch (data.event) {
+	case AP_POWER_SUSPEND:
+		fn = sm5803_enable_low_power_mode;
+		break;
+	case AP_POWER_RESUME:
+		fn = sm5803_disable_low_power_mode;
+		break;
+	default:
+		LOG_WRN("%s: power event %d is not recognized", __func__,
+			data.event);
+		return;
+	}
+
+	fn(CHARGER_PRIMARY);
+	if (board_get_charger_chip_count() > 1)
+		fn(CHARGER_SECONDARY);
+}
+
+static int board_chargers_suspend_init(void)
+{
+	static struct ap_power_ev_callback cb = {
+		.handler = board_chargers_suspend,
+		.events = AP_POWER_SUSPEND | AP_POWER_RESUME,
+	};
+	ap_power_ev_add_callback(&cb);
+	return 0;
+}
+SYS_INIT(board_chargers_suspend_init, APPLICATION, 0);
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count());
+	int i;
+	int old_port;
+	int rv;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	old_port = charge_manager_get_active_charge_port();
+	LOG_INF("Charge update: p%d -> p%d", old_port, port);
+
+	/* Check if port is sourcing VBUS. */
+	if (port != CHARGE_PORT_NONE && charger_is_sourcing_otg_power(port)) {
+		LOG_WRN("Skip enable p%d: already sourcing", port);
+		return EC_ERROR_INVAL;
+	}
+
+	/* Disable sinking on all ports except the desired one */
+	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+		if (i == port)
+			continue;
+
+		if (sm5803_vbus_sink_enable(i, 0))
+			/*
+			 * Do not early-return because this can fail during
+			 * power-on which would put us into a loop.
+			 */
+			LOG_WRN("p%d: sink path disable failed.", i);
+	}
+
+	/* Don't enable anything (stop here) if no ports were requested */
+	if ((port == CHARGE_PORT_NONE) || (old_port == port))
+		return EC_SUCCESS;
+
+	/*
+	 * Stop the charger IC from switching while changing ports.  Otherwise,
+	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
+	 */
+	if (old_port != CHARGE_PORT_NONE)
+		charger_discharge_on_ac(1);
+
+	/* Enable requested charge port. */
+	rv = sm5803_vbus_sink_enable(port, 1);
+	if (rv)
+		LOG_WRN("p%d: sink path enable failed: code %d", port, rv);
+
+	/* Allow the charger IC to begin/continue switching. */
+	charger_discharge_on_ac(0);
+
+	return rv;
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	/*
+	 * TCPC 0 is embedded in the EC and processes interrupts in the chip
+	 * code (it83xx/intc.c). This function only needs to poll port C1 if
+	 * present.
+	 */
+	uint16_t status = 0;
+	int regval;
+
+	/* Is the C1 port IRQ line asserted? */
+	if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_int_odl))) {
+		/*
+		 * C1 IRQ is shared between BC1.2 and TCPC; poll TCPC to see if
+		 * it asserted the IRQ.
+		 */
+		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
+			if (regval)
+				status = PD_STATUS_TCPC_ALERT_1;
+		}
+	}
+
+	return status;
+}
+
+void pd_power_supply_reset(int port)
+{
+	int prev_en;
+
+	if (port < 0 || port >= board_get_usb_pd_port_count())
+		return;
+
+	prev_en = charger_is_sourcing_otg_power(port);
+
+	/* Disable Vbus */
+	charger_enable_otg_power(port, 0);
+
+	/* Discharge Vbus if previously enabled */
+	if (prev_en)
+		sm5803_set_vbus_disch(port, 1);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	enum ec_error_list rv;
+
+	if (port < 0 || port > board_get_usb_pd_port_count()) {
+		LOG_WRN("Port C%d does not exist, cannot enable VBUS", port);
+		return EC_ERROR_INVAL;
+	}
+
+	/* Disable sinking */
+	rv = sm5803_vbus_sink_enable(port, 0);
+	if (rv) {
+		LOG_WRN("C%d failed to disable sinking: %d", port, rv);
+		return rv;
+	}
+
+	/* Disable Vbus discharge */
+	rv = sm5803_set_vbus_disch(port, 0);
+	if (rv) {
+		LOG_WRN("C%d failed to clear VBUS discharge: %d", port, rv);
+		return rv;
+	}
+
+	/* Provide Vbus */
+	rv = charger_enable_otg_power(port, 1);
+	if (rv) {
+		LOG_WRN("C%d failed to enable VBUS sourcing: %d", port, rv);
+		return rv;
+	}
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	int rv;
+	const int current = rp == TYPEC_RP_3A0 ? 3000 : 1500;
+
+	rv = charger_set_otg_current_voltage(port, current, 5000);
+	if (rv != EC_SUCCESS) {
+		LOG_WRN("Failed to set source ilimit on port %d to %d: %d",
+			port, current, rv);
+	}
+}
+
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
+{
+	/*
+	 * b:213937755: Yaviks C1 port is OCPC (One Charger IC Per Type-C)
+	 * architecture, The charging current is controlled by increasing Vsys.
+	 * However, the charger SM5803 is not limit current while Vsys
+	 * increasing, we can see the current overshoot to ~3.6A to cause
+	 * C1 port brownout with low power charger (5V). To avoid C1 port
+	 * brownout at low power charger connected. Limit charge current to 2A.
+	 */
+	if (charge_mv <= 5000 && port == 1)
+		charge_ma = MIN(charge_ma, 2000);
+	else
+		charge_ma = charge_ma * 96 / 100;
+
+	charge_set_input_current_limit(charge_ma, charge_mv);
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * Do nothing. The integrated TCPC for C0 lacks a dedicated reset
+	 * command, and C1 (if present) doesn't have a reset pin connected
+	 * to the EC.
+	 */
+}
+
+#define INT_RECHECK_US 5000
+
+/* C0 interrupt line shared by BC 1.2 and charger */
+
+static void check_c0_line(void);
+DECLARE_DEFERRED(check_c0_line);
+
+static void notify_c0_chips(void)
+{
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+	sm5803_interrupt(0);
+}
+
+static void check_c0_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips
+	 */
+	if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl))) {
+		notify_c0_chips();
+		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+	}
+}
+
+void usb_c0_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c0_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c0_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+}
+
+/* C1 interrupt line shared by BC 1.2, TCPC, and charger */
+void usb_c1_interrupt(enum gpio_signal s)
+{
+	/* Charger and BC1.2 are handled in board_process_pd_alert */
+	schedule_deferred_pd_interrupt(1);
+}
+
+/*
+ * Check state of IRQ lines at startup, ensuring an IRQ that happened before
+ * the EC started up won't get lost (leaving the IRQ line asserted and blocking
+ * any further interrupts on the port).
+ *
+ * Although the PD task will check for pending TCPC interrupts on startup,
+ * the charger sharing the IRQ will not be polled automatically.
+ */
+void board_handle_initial_typec_irq(void)
+{
+	check_c0_line();
+	/*
+	 * C1 port IRQ already handled by board_process_pd_alert(), we don't
+	 * need check IRQ here at initial.
+	 */
+}
+/*
+ * This must run after sub-board detection (which happens in EC main()),
+ * but isn't depended on by anything else either.
+ */
+DECLARE_HOOK(HOOK_INIT, board_handle_initial_typec_irq, HOOK_PRIO_LAST);
+
+/*
+ * Handle charger interrupts in the PD task. Not doing so can lead to a priority
+ * inversion where we fail to respond to TCPC alerts quickly enough because we
+ * don't get another edge on a shared IRQ until the other interrupt is cleared
+ * (or the IRQ is polled again), which happens in lower-priority tasks: the
+ * high-priority type-C handler is thus blocked on the lower-priority one(s).
+ *
+ * To avoid that, we run charger and BC1.2 interrupts synchronously alongside
+ * PD interrupts so they have the same priority.
+ */
+void board_process_pd_alert(int port)
+{
+	/*
+	 * Port 0 doesn't use an external TCPC, so its interrupts don't need
+	 * this special handling.
+	 */
+	if (port != 1)
+		return;
+
+	if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_int_odl))) {
+		sm5803_handle_interrupt(port);
+		usb_charger_task_set_event_sync(1, USB_CHG_EVENT_BC12);
+	}
+	/*
+	 * Immediately schedule another TCPC interrupt if it seems we haven't
+	 * cleared all pending interrupts.
+	 */
+	if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_int_odl)))
+		schedule_deferred_pd_interrupt(port);
+
+	/*
+	 * b:273208597: There are some peripheral display docks will
+	 * issue HPDs in the short time. TCPM must wake up pd_task
+	 * continually to service the events. They may cause the
+	 * watchdog to reset. This patch placates watchdog after
+	 * receiving dp_attention.
+	 */
+	watchdog_reload();
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	int chg_det = 0;
+
+	sm5803_get_chg_det(port, &chg_det);
+
+	return chg_det;
+}
diff --git a/zephyr/program/nissa/yaviks/yaviks_vif.xml b/zephyr/program/nissa/yaviks/yaviks_vif.xml
new file mode 100644
index 0000000000..edc6299c58
--- /dev/null
+++ b/zephyr/program/nissa/yaviks/yaviks_vif.xml
@@ -0,0 +1,350 @@
+<?xml version="1.0" encoding="utf-8"?>
+<vif:VIF xmlns:opt="http://usb.org/VendorInfoFileOptionalContent.xsd" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:vif="http://usb.org/VendorInfoFile.xsd">
+  <vif:VIF_Specification>3.19</vif:VIF_Specification>
+  <vif:VIF_App>
+    <vif:Vendor>USB-IF</vif:Vendor>
+    <vif:Name>VIF Editor</vif:Name>
+    <vif:Version>3.2.4.0</vif:Version>
+  </vif:VIF_App>
+  <vif:Vendor_Name>Google</vif:Vendor_Name>
+  <vif:Model_Part_Number>Yaviks</vif:Model_Part_Number>
+  <vif:Product_Revision>1</vif:Product_Revision>
+  <vif:TID>0</vif:TID>
+  <vif:VIF_Product_Type value="0">Port Product</vif:VIF_Product_Type>
+  <vif:Certification_Type value="1">Reference Platform</vif:Certification_Type>
+  <vif:Product>
+    <!--Product Level Content:-->
+  </vif:Product>
+  <vif:Component>
+    <!--Component 0: Port 0-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Component-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Port_Label>0</vif:Port_Label>
+    <vif:Connector_Type value="2">Type-C®</vif:Connector_Type>
+    <vif:USB4_Supported value="false" />
+    <vif:USB_PD_Support value="true" />
+    <vif:PD_Port_Type value="4">DRP</vif:PD_Port_Type>
+    <vif:Type_C_State_Machine value="2">DRP</vif:Type_C_State_Machine>
+    <vif:Port_Battery_Powered value="true" />
+    <vif:BC_1_2_Support value="2">Charging Port</vif:BC_1_2_Support>
+    <vif:Captive_Cable value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;General PD-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Spec_Revision_Major value="3" />
+    <vif:PD_Spec_Revision_Minor value="1" />
+    <vif:PD_Spec_Version_Major value="1" />
+    <vif:PD_Spec_Version_Minor value="3" />
+    <vif:PD_Specification_Revision value="2">Revision 3</vif:PD_Specification_Revision>
+    <vif:SOP_Capable value="true" />
+    <vif:SOP_P_Capable value="true" />
+    <vif:SOP_PP_Capable value="true" />
+    <vif:SOP_P_Debug_Capable value="false" />
+    <vif:SOP_PP_Debug_Capable value="false" />
+    <vif:Manufacturer_Info_Supported_Port value="true" />
+    <vif:Manufacturer_Info_VID_Port value="6353">18D1</vif:Manufacturer_Info_VID_Port>
+    <vif:Manufacturer_Info_PID_Port value="20570">505A</vif:Manufacturer_Info_PID_Port>
+    <vif:Chunking_Implemented_SOP value="true" />
+    <vif:Unchunked_Extended_Messages_Supported value="false" />
+    <vif:Security_Msgs_Supported_SOP value="false" />
+    <vif:Unconstrained_Power value="false" />
+    <vif:Num_Fixed_Batteries value="1" />
+    <vif:Num_Swappable_Battery_Slots value="0" />
+    <vif:ID_Header_Connector_Type_SOP value="2">USB Type-C® Receptacle</vif:ID_Header_Connector_Type_SOP>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Capabilities-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:USB_Comms_Capable value="true" />
+    <vif:DR_Swap_To_DFP_Supported value="true" />
+    <vif:DR_Swap_To_UFP_Supported value="false" />
+    <vif:VCONN_Swap_To_On_Supported value="true" />
+    <vif:VCONN_Swap_To_Off_Supported value="true" />
+    <vif:Responds_To_Discov_SOP_UFP value="false" />
+    <vif:Responds_To_Discov_SOP_DFP value="true" />
+    <vif:Attempts_Discov_SOP value="true" />
+    <vif:Power_Interruption_Available value="0">No Interruption Possible</vif:Power_Interruption_Available>
+    <vif:Data_Reset_Supported value="false" />
+    <vif:Enter_USB_Supported value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;USB Type-C®-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Type_C_Can_Act_As_Host value="true" />
+    <vif:Type_C_Can_Act_As_Device value="false" />
+    <vif:Type_C_Implements_Try_SRC value="true" />
+    <vif:Type_C_Implements_Try_SNK value="false" />
+    <vif:Type_C_Supports_Audio_Accessory value="false" />
+    <vif:Type_C_Is_VCONN_Powered_Accessory value="false" />
+    <vif:Type_C_Is_Debug_Target_SRC value="true" />
+    <vif:Type_C_Is_Debug_Target_SNK value="true" />
+    <vif:RP_Value value="1">1.5A</vif:RP_Value>
+    <vif:Type_C_Port_On_Hub value="false" />
+    <vif:Type_C_Power_Source value="2">Both</vif:Type_C_Power_Source>
+    <vif:Type_C_Sources_VCONN value="true" />
+    <vif:Type_C_Is_Alt_Mode_Controller value="true" />
+    <vif:Type_C_Is_Alt_Mode_Adapter value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Product Power-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Product_Total_Source_Power_mW value="15000">15000 mW</vif:Product_Total_Source_Power_mW>
+    <vif:Port_Source_Power_Type value="0">Assured</vif:Port_Source_Power_Type>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;USB Host-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Host_Supports_USB_Data value="true" />
+    <vif:Host_Speed value="1">USB 3.2 Gen 1x1</vif:Host_Speed>
+    <vif:Host_Contains_Captive_Retimer value="false" />
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:Host_Is_Embedded value="false" />
+    <vif:Host_Suspend_Supported value="true" />
+    <vif:Is_DFP_On_Hub value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Battery Charging 1.2-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:BC_1_2_Charging_Port_Type value="1">CDP</vif:BC_1_2_Charging_Port_Type>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Source-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Power_As_Source value="15000">15000 mW</vif:PD_Power_As_Source>
+    <vif:EPR_Supported_As_Src value="false" />
+    <vif:USB_Suspend_May_Be_Cleared value="false" />
+    <vif:Sends_Pings value="false" />
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="0">FR_Swap not supported</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <vif:Master_Port value="false" />
+    <vif:Num_Src_PDOs value="1" />
+    <vif:PD_OC_Protection value="true" />
+    <vif:PD_OCP_Method value="0">Over-Current Response</vif:PD_OCP_Method>
+    <!--Bundle: SrcPdoList-->
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!--Source PDO 1-->
+        <vif:Src_PDO_Supply_Type value="0">Fixed</vif:Src_PDO_Supply_Type>
+        <vif:Src_PDO_Peak_Current value="0">100% IOC</vif:Src_PDO_Peak_Current>
+        <vif:Src_PDO_Voltage value="100">5000 mV</vif:Src_PDO_Voltage>
+        <vif:Src_PDO_Max_Current value="300">3000 mA</vif:Src_PDO_Max_Current>
+        <vif:Src_PD_OCP_OC_Debounce value="0">0 msec</vif:Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="300">3000 mA</vif:Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Sink-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Power_As_Sink value="45000">45000 mW</vif:PD_Power_As_Sink>
+    <vif:EPR_Supported_As_Snk value="false" />
+    <vif:No_USB_Suspend_May_Be_Set value="true" />
+    <vif:GiveBack_May_Be_Set value="false" />
+    <vif:Higher_Capability_Set value="false" />
+    <vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source value="0">FR_Swap not supported</vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source>
+    <vif:Num_Snk_PDOs value="3" />
+    <!--Bundle: SnkPdoList-->
+    <vif:SnkPdoList>
+      <vif:SnkPDO>
+        <!--Sink PDO 1-->
+        <vif:Snk_PDO_Supply_Type value="0">Fixed</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Voltage value="100">5000 mV</vif:Snk_PDO_Voltage>
+        <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>
+      </vif:SnkPDO>
+      <vif:SnkPDO>
+        <!--Sink PDO 2-->
+        <vif:Snk_PDO_Supply_Type value="1">Battery</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Op_Power value="60">15000 mW</vif:Snk_PDO_Op_Power>
+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>
+        <vif:Snk_PDO_Max_Voltage value="300">15000 mV</vif:Snk_PDO_Max_Voltage>
+      </vif:SnkPDO>
+      <vif:SnkPDO>
+        <!--Sink PDO 3-->
+        <vif:Snk_PDO_Supply_Type value="2">Variable</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>
+        <vif:Snk_PDO_Max_Voltage value="300">15000 mV</vif:Snk_PDO_Max_Voltage>
+        <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>
+      </vif:SnkPDO>
+    </vif:SnkPdoList>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Dual Role-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Accepts_PR_Swap_As_Src value="true" />
+    <vif:Accepts_PR_Swap_As_Snk value="true" />
+    <vif:Requests_PR_Swap_As_Src value="true" />
+    <vif:Requests_PR_Swap_As_Snk value="true" />
+    <vif:FR_Swap_Supported_As_Initial_Sink value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;SOP Discover ID-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:XID_SOP value="0" />
+    <vif:Data_Capable_As_USB_Host_SOP value="true" />
+    <vif:Data_Capable_As_USB_Device_SOP value="false" />
+    <vif:Product_Type_UFP_SOP value="0">Undefined</vif:Product_Type_UFP_SOP>
+    <vif:Product_Type_DFP_SOP value="2">PDUSB Host</vif:Product_Type_DFP_SOP>
+    <vif:DFP_VDO_Port_Number value="0" />
+    <vif:Modal_Operation_Supported_SOP value="false" />
+    <vif:USB_VID_SOP value="6353">18D1</vif:USB_VID_SOP>
+    <vif:PID_SOP value="20570">505A</vif:PID_SOP>
+    <vif:bcdDevice_SOP value="0">0000</vif:bcdDevice_SOP>
+  </vif:Component>
+  <vif:Component>
+    <!--Component 1: Port 1-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Component-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Port_Label>1</vif:Port_Label>
+    <vif:Connector_Type value="2">Type-C®</vif:Connector_Type>
+    <vif:USB4_Supported value="false" />
+    <vif:USB_PD_Support value="true" />
+    <vif:PD_Port_Type value="4">DRP</vif:PD_Port_Type>
+    <vif:Type_C_State_Machine value="2">DRP</vif:Type_C_State_Machine>
+    <vif:Port_Battery_Powered value="true" />
+    <vif:BC_1_2_Support value="2">Charging Port</vif:BC_1_2_Support>
+    <vif:Captive_Cable value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;General PD-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Spec_Revision_Major value="3" />
+    <vif:PD_Spec_Revision_Minor value="1" />
+    <vif:PD_Spec_Version_Major value="1" />
+    <vif:PD_Spec_Version_Minor value="3" />
+    <vif:PD_Specification_Revision value="2">Revision 3</vif:PD_Specification_Revision>
+    <vif:SOP_Capable value="true" />
+    <vif:SOP_P_Capable value="true" />
+    <vif:SOP_PP_Capable value="true" />
+    <vif:SOP_P_Debug_Capable value="false" />
+    <vif:SOP_PP_Debug_Capable value="false" />
+    <vif:Manufacturer_Info_Supported_Port value="true" />
+    <vif:Manufacturer_Info_VID_Port value="6353">18D1</vif:Manufacturer_Info_VID_Port>
+    <vif:Manufacturer_Info_PID_Port value="20570">505A</vif:Manufacturer_Info_PID_Port>
+    <vif:Chunking_Implemented_SOP value="true" />
+    <vif:Unchunked_Extended_Messages_Supported value="false" />
+    <vif:Security_Msgs_Supported_SOP value="false" />
+    <vif:Unconstrained_Power value="false" />
+    <vif:Num_Fixed_Batteries value="1" />
+    <vif:Num_Swappable_Battery_Slots value="0" />
+    <vif:ID_Header_Connector_Type_SOP value="2">USB Type-C® Receptacle</vif:ID_Header_Connector_Type_SOP>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Capabilities-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:USB_Comms_Capable value="true" />
+    <vif:DR_Swap_To_DFP_Supported value="true" />
+    <vif:DR_Swap_To_UFP_Supported value="false" />
+    <vif:VCONN_Swap_To_On_Supported value="true" />
+    <vif:VCONN_Swap_To_Off_Supported value="true" />
+    <vif:Responds_To_Discov_SOP_UFP value="false" />
+    <vif:Responds_To_Discov_SOP_DFP value="true" />
+    <vif:Attempts_Discov_SOP value="true" />
+    <vif:Power_Interruption_Available value="0">No Interruption Possible</vif:Power_Interruption_Available>
+    <vif:Data_Reset_Supported value="false" />
+    <vif:Enter_USB_Supported value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;USB Type-C®-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Type_C_Can_Act_As_Host value="true" />
+    <vif:Type_C_Can_Act_As_Device value="false" />
+    <vif:Type_C_Implements_Try_SRC value="true" />
+    <vif:Type_C_Implements_Try_SNK value="false" />
+    <vif:Type_C_Supports_Audio_Accessory value="false" />
+    <vif:Type_C_Is_VCONN_Powered_Accessory value="false" />
+    <vif:Type_C_Is_Debug_Target_SRC value="true" />
+    <vif:Type_C_Is_Debug_Target_SNK value="true" />
+    <vif:RP_Value value="1">1.5A</vif:RP_Value>
+    <vif:Type_C_Port_On_Hub value="false" />
+    <vif:Type_C_Power_Source value="2">Both</vif:Type_C_Power_Source>
+    <vif:Type_C_Sources_VCONN value="true" />
+    <vif:Type_C_Is_Alt_Mode_Controller value="true" />
+    <vif:Type_C_Is_Alt_Mode_Adapter value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Product Power-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Product_Total_Source_Power_mW value="15000">15000 mW</vif:Product_Total_Source_Power_mW>
+    <vif:Port_Source_Power_Type value="0">Assured</vif:Port_Source_Power_Type>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;USB Host-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Host_Supports_USB_Data value="true" />
+    <vif:Host_Speed value="1">USB 3.2 Gen 1x1</vif:Host_Speed>
+    <vif:Host_Contains_Captive_Retimer value="true" />
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:Host_Is_Embedded value="false" />
+    <vif:Host_Suspend_Supported value="true" />
+    <vif:Is_DFP_On_Hub value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Battery Charging 1.2-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:BC_1_2_Charging_Port_Type value="1">CDP</vif:BC_1_2_Charging_Port_Type>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Source-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Power_As_Source value="15000">15000 mW</vif:PD_Power_As_Source>
+    <vif:EPR_Supported_As_Src value="false" />
+    <vif:USB_Suspend_May_Be_Cleared value="false" />
+    <vif:Sends_Pings value="false" />
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="0">FR_Swap not supported</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <vif:Master_Port value="false" />
+    <vif:Num_Src_PDOs value="1" />
+    <vif:PD_OC_Protection value="true" />
+    <vif:PD_OCP_Method value="0">Over-Current Response</vif:PD_OCP_Method>
+    <!--Bundle: SrcPdoList-->
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!--Source PDO 1-->
+        <vif:Src_PDO_Supply_Type value="0">Fixed</vif:Src_PDO_Supply_Type>
+        <vif:Src_PDO_Peak_Current value="0">100% IOC</vif:Src_PDO_Peak_Current>
+        <vif:Src_PDO_Voltage value="100">5000 mV</vif:Src_PDO_Voltage>
+        <vif:Src_PDO_Max_Current value="300">3000 mA</vif:Src_PDO_Max_Current>
+        <vif:Src_PD_OCP_OC_Debounce value="0">0 msec</vif:Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="300">3000 mA</vif:Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Sink-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Power_As_Sink value="45000">45000 mW</vif:PD_Power_As_Sink>
+    <vif:EPR_Supported_As_Snk value="false" />
+    <vif:No_USB_Suspend_May_Be_Set value="true" />
+    <vif:GiveBack_May_Be_Set value="false" />
+    <vif:Higher_Capability_Set value="false" />
+    <vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source value="0">FR_Swap not supported</vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source>
+    <vif:Num_Snk_PDOs value="3" />
+    <!--Bundle: SnkPdoList-->
+    <vif:SnkPdoList>
+      <vif:SnkPDO>
+        <!--Sink PDO 1-->
+        <vif:Snk_PDO_Supply_Type value="0">Fixed</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Voltage value="100">5000 mV</vif:Snk_PDO_Voltage>
+        <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>
+      </vif:SnkPDO>
+      <vif:SnkPDO>
+        <!--Sink PDO 2-->
+        <vif:Snk_PDO_Supply_Type value="1">Battery</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Op_Power value="60">15000 mW</vif:Snk_PDO_Op_Power>
+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>
+        <vif:Snk_PDO_Max_Voltage value="300">15000 mV</vif:Snk_PDO_Max_Voltage>
+      </vif:SnkPDO>
+      <vif:SnkPDO>
+        <!--Sink PDO 3-->
+        <vif:Snk_PDO_Supply_Type value="2">Variable</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>
+        <vif:Snk_PDO_Max_Voltage value="300">15000 mV</vif:Snk_PDO_Max_Voltage>
+        <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>
+      </vif:SnkPDO>
+    </vif:SnkPdoList>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Dual Role-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Accepts_PR_Swap_As_Src value="true" />
+    <vif:Accepts_PR_Swap_As_Snk value="true" />
+    <vif:Requests_PR_Swap_As_Src value="true" />
+    <vif:Requests_PR_Swap_As_Snk value="true" />
+    <vif:FR_Swap_Supported_As_Initial_Sink value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;SOP Discover ID-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:XID_SOP value="0" />
+    <vif:Data_Capable_As_USB_Host_SOP value="true" />
+    <vif:Data_Capable_As_USB_Device_SOP value="false" />
+    <vif:Product_Type_UFP_SOP value="0">Undefined</vif:Product_Type_UFP_SOP>
+    <vif:Product_Type_DFP_SOP value="2">PDUSB Host</vif:Product_Type_DFP_SOP>
+    <vif:DFP_VDO_Port_Number value="1" />
+    <vif:Modal_Operation_Supported_SOP value="false" />
+    <vif:USB_VID_SOP value="6353">18D1</vif:USB_VID_SOP>
+    <vif:PID_SOP value="20570">505A</vif:PID_SOP>
+    <vif:bcdDevice_SOP value="0">0000</vif:bcdDevice_SOP>
+  </vif:Component>
+</vif:VIF>
\ No newline at end of file
diff --git a/zephyr/program/nissa/yavilla/cbi.dtsi b/zephyr/program/nissa/yavilla/cbi.dtsi
new file mode 100644
index 0000000000..73ee946de4
--- /dev/null
+++ b/zephyr/program/nissa/yavilla/cbi.dtsi
@@ -0,0 +1,121 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	/* Yavilla-specific fw_config fields. */
+	nissa-fw-config {
+		compatible = "cros-ec,cbi-fw-config";
+		/*
+		 * FW_CONFIG field for multiple wi-fi SAR.
+		 *
+		 *	start = <2>;
+		 *	size = <2>;
+		 */
+
+		/*
+		 * FW_CONFIG field to enable fan or not.
+		 */
+		fan {
+			enum-name = "FW_FAN";
+			start = <4>;
+			size = <1>;
+
+			no-fan {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FAN_NOT_PRESENT";
+				value = <0>;
+			};
+			fan-present {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FAN_PRESENT";
+				value = <1>;
+				/*
+				 * Set as default so that unprovisioned
+				 * configs will run the fan regardless.
+				 */
+				default;
+			};
+		};
+
+		/*
+		 * FW_CONFIG field to indicate which keyboard layout
+		 * should be used.
+		 */
+		keyboard {
+			enum-name = "FW_KB_LAYOUT";
+			start = <5>;
+			size = <1>;
+
+			layout-1 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_KB_LAYOUT_DEFAULT";
+				value = <0>;
+				default;
+			};
+			layout-2 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_KB_LAYOUT_US2";
+				value = <1>;
+			};
+		};
+
+		/*
+		 * FW_CONFIG field to indicate which keyboard layout
+		 * should be used.
+		 */
+		keyboard-backlight {
+			enum-name = "FW_KB_BACKLIGHT";
+			start = <6>;
+			size = <1>;
+
+			without-keyboard-backlight {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_KB_BACKLIGHT_OFF";
+				value = <1>;
+			};
+			with-keyboard-backlight {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_KB_BACKLIGHT_ON";
+				value = <0>;
+				default;
+			};
+		};
+
+		/*
+		 * FW_CONFIG field for multiple touch panel.
+		 *
+		 *	start = <7>;
+		 *	size = <2>;
+		 */
+
+		/*
+		 * FW_CONFIG field to indicate tablet mode present
+		 * or absent.
+		 */
+		tablet {
+			enum-name = "FW_TABLET";
+			start = <13>;
+			size = <1>;
+
+			tablet-present {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_TABLET_PRESENT";
+				value = <1>;
+			};
+			tablet-absent {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_TABLET_ABSENT";
+				value = <0>;
+			};
+		};
+
+		/*
+		 * FW_CONFIG field for multiple storage.
+		 *
+		 *	start = <31>;
+		 *	size = <1>;
+		 */
+	};
+};
diff --git a/zephyr/program/nissa/yavilla/fan.dtsi b/zephyr/program/nissa/yavilla/fan.dtsi
new file mode 100644
index 0000000000..6a3fc0288a
--- /dev/null
+++ b/zephyr/program/nissa/yavilla/fan.dtsi
@@ -0,0 +1,71 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/ {
+	fans {
+		compatible = "cros-ec,fans";
+		fan_0 {
+			pwms = <&pwm2 PWM_CHANNEL_2 PWM_KHZ(25) PWM_POLARITY_NORMAL>;
+			tach = <&tach1>;
+			rpm_min = <2500>;
+			rpm_start = <2500>;
+			rpm_max = <4100>;
+			rpm_deviation = <1>;
+			enable_gpio = <&gpio_fan_enable>;
+		};
+	};
+	fan_steps {
+		compatible = "cros-ec,fan-steps";
+		level_0 {
+			temp_on = <43 47 0>;
+			temp_off = <99 99 99>;
+			rpm_target = <0>;
+		};
+		level_1 {
+			temp_on = <46 48 0>;
+			temp_off = <40 45 99>;
+			rpm_target = <2600>;
+		};
+		level_2 {
+			temp_on = <49 49 0>;
+			temp_off = <44 46 99>;
+			rpm_target = <2800>;
+		};
+		level_3 {
+			temp_on = <53 50 54>;
+			temp_off = <47 47 51>;
+			rpm_target = <3100>;
+		};
+		level_4 {
+			temp_on = <56 56 60>;
+			temp_off = <51 48 52>;
+			rpm_target = <3300>;
+		};
+		level_5 {
+			temp_on = <60 60 64>;
+			temp_off = <54 52 56>;
+			rpm_target = <3600>;
+		};
+		level_6 {
+			temp_on = <100 100 100>;
+			temp_off = <58 54 58>;
+			rpm_target = <4000>;
+		};
+	};
+};
+/* pwm for fan */
+&pwm2 {
+	status = "okay";
+	prescaler-cx = <PWM_PRESCALER_C6>;
+	pinctrl-0 = <&pwm2_gpa2_default>;
+	pinctrl-names = "default";
+};
+/* fan tachometer sensor */
+&tach1 {
+	status = "okay";
+	channel = <IT8XXX2_TACH_CHANNEL_A>;
+	pulses-per-round = <2>;
+	pinctrl-0 = <&tach1a_gpd7_default>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/nissa/yavilla/gpio.dtsi b/zephyr/program/nissa/yavilla/gpio.dtsi
new file mode 100644
index 0000000000..a39d5ff709
--- /dev/null
+++ b/zephyr/program/nissa/yavilla/gpio.dtsi
@@ -0,0 +1,263 @@
+/*
+ * Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc {
+			enum-name = "ADC_PP1050_PROC";
+			io-channels = <&adc0 14>;
+		};
+		adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 {
+			enum-name = "ADC_PP3300_S5";
+			io-channels = <&adc0 0>;
+		};
+		adc_temp_sensor_1: temp_sensor_1 {
+			enum-name = "ADC_TEMP_SENSOR_1";
+			io-channels = <&adc0 2>;
+		};
+		adc_temp_sensor_2: temp_sensor_2 {
+			enum-name = "ADC_TEMP_SENSOR_2";
+			io-channels = <&adc0 3>;
+		};
+		adc_temp_sensor_3: temp_sensor_3 {
+			enum-name = "ADC_TEMP_SENSOR_3";
+			io-channels = <&adc0 13>;
+		};
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		gpio_acc_int_l: acc_int_l {
+			gpios = <&gpioc 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		gpio_all_sys_pwrgd: all_sys_pwrgd {
+			gpios = <&gpiob 7 GPIO_INPUT>;
+		};
+		gpio_ccd_mode_odl: ccd_mode_odl {
+			gpios = <&gpioh 5 GPIO_INPUT>;
+			enum-name = "GPIO_CCD_MODE_ODL";
+		};
+		gpio_cpu_c10_gate_l: cpu_c10_gate_l {
+			gpios = <&gpiog 1 GPIO_INPUT>;
+		};
+		gpio_ec_battery_pres_odl: ec_battery_pres_odl {
+			gpios = <&gpioi 4 GPIO_INPUT>;
+			enum-name = "GPIO_BATT_PRES_ODL";
+		};
+		gpio_ec_cbi_wp: ec_cbi_wp {
+			gpios = <&gpioj 5 GPIO_OUTPUT>;
+		};
+		gpio_ec_edp_bl_en_od: ec_edp_bl_en_od {
+			gpios = <&gpiok 4 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_ENABLE_BACKLIGHT";
+		};
+		gpio_ec_entering_rw: ec_entering_rw {
+			gpios = <&gpioc 7 GPIO_OUTPUT>;
+			enum-name = "GPIO_ENTERING_RW";
+		};
+		gpio_ec_gsc_packet_mode: ec_gsc_packet_mode {
+			gpios = <&gpioh 1 GPIO_OUTPUT>;
+			enum-name = "GPIO_PACKET_MODE_EN";
+		};
+		gpio_ec_pch_wake_odl: ec_pch_wake_odl {
+			gpios = <&gpiob 2 GPIO_ODR_LOW>;
+		};
+		gpio_ec_prochot_odl: ec_prochot_odl {
+			gpios = <&gpioi 1 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>;
+		};
+		gpio_ec_soc_dsw_pwrok: ec_soc_dsw_pwrok {
+			gpios = <&gpiol 7 GPIO_OUTPUT>;
+			no-auto-init;
+		};
+		gpio_ec_soc_int_odl: ec_soc_int_odl {
+			gpios = <&gpiod 5 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_EC_INT_L";
+		};
+		gpio_ec_soc_pch_pwrok_od: ec_soc_pch_pwrok_od {
+			gpios = <&gpiod 6 GPIO_ODR_HIGH>;
+			no-auto-init;
+		};
+		gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl {
+			gpios = <&gpiob 6 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_PCH_PWRBTN_L";
+		};
+		gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l {
+			gpios = <&gpioh 0 GPIO_OUTPUT>;
+			no-auto-init;
+		};
+		gpio_ec_soc_rtcrst: ec_soc_rtcrst {
+			gpios = <&gpiok 2 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_sys_pwrok: ec_soc_sys_pwrok {
+			gpios = <&gpiof 2 GPIO_OUTPUT>;
+			no-auto-init;
+		};
+		gpio_ec_soc_vccst_pwrgd_od: ec_soc_vccst_pwrgd_od {
+			gpios = <&gpioe 5 GPIO_ODR_HIGH>;
+			no-auto-init;
+		};
+		gpio_ec_wp_odl: ec_wp_odl {
+			gpios = <&gpioa 6 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_en_pp3300_s5: en_pp3300_s5 {
+			gpios = <&gpioc 5 GPIO_OUTPUT>;
+			enum-name = "GPIO_TEMP_SENSOR_POWER";
+			no-auto-init;
+		};
+		gpio_en_pp5000_pen_x: en_pp5000_pen_x {
+			gpios = <&gpiob 5 GPIO_OUTPUT>;
+		};
+		gpio_en_pp5000_s5: en_pp5000_s5 {
+			gpios = <&gpiok 5 GPIO_OUTPUT>;
+			no-auto-init;
+		};
+		gpio_en_slp_z: en_slp_z {
+			gpios = <&gpiok 3 GPIO_OUTPUT>;
+		};
+		gpio_en_usb_a0_vbus: en_usb_a0_vbus {
+			gpios = <&gpiol 6 GPIO_OUTPUT>;
+		};
+		gpio_en_usb_a1_vbus: en_usb_a1_vbus {
+			gpios = <&gpiof 0 GPIO_OUTPUT>;
+		};
+		gpio_en_usb_c0_cc1_vconn: en_usb_c0_cc1_vconn {
+			gpios = <&gpioh 4 GPIO_OUTPUT>;
+		};
+		gpio_en_usb_c0_cc2_vconn: en_usb_c0_cc2_vconn {
+			gpios = <&gpioh 6 GPIO_OUTPUT>;
+		};
+		gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl {
+			gpios = <&gpioe 2 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		gpio_imu_int_l: imu_int_l {
+			gpios = <&gpioj 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		gpio_imvp91_vrrdy_od: imvp91_vrrdy_od {
+			gpios = <&gpioj 4 GPIO_INPUT>;
+			no-auto-init;
+		};
+		gpio_lid_open: lid_open {
+			gpios = <&gpiof 3 GPIO_INPUT>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+		gpio_pen_detect_odl: pen_detect_odl {
+			gpios = <&gpioj 1 GPIO_INPUT>;
+		};
+		gpio_pg_pp1050_mem_s3_od: pg_pp1050_mem_s3_od {
+			gpios = <&gpiod 3 GPIO_INPUT>;
+		};
+		gpio_pg_pp5000_s5_od: pg_pp5000_s5_od {
+			gpios = <&gpioe 3 GPIO_INPUT>;
+		};
+		gpio_rsmrst_pwrgd_l: rsmrst_pwrgd_l {
+			gpios = <&gpioe 1 GPIO_INPUT_PULL_UP>;
+			no-auto-init;
+		};
+		gpio_slp_s0_l: slp_s0_l {
+			gpios = <&gpioe 4 GPIO_INPUT>;
+			no-auto-init;
+		};
+		gpio_slp_s3_l: slp_s3_l {
+			gpios = <&gpioh 3 GPIO_INPUT>;
+			no-auto-init;
+		};
+		gpio_slp_s4_l: slp_s4_l {
+			gpios = <&gpioi 5 GPIO_INPUT>;
+		};
+		gpio_slp_sus_l: slp_sus_l {
+			gpios = <&gpiog 2 GPIO_INPUT>;
+			no-auto-init;
+		};
+		gpio_sub_usb_a1_ilimit_sdp: sub_usb_a1_ilimit_sdp {
+			gpios = <&gpiof 1 GPIO_OUTPUT>;
+			enum-name = "GPIO_USB2_ILIM_SEL";
+		};
+		gpio_sys_rst_odl: sys_rst_odl {
+			gpios = <&gpiod 1 GPIO_ODR_HIGH>;
+			no-auto-init;
+		};
+		gpio_tablet_mode_l: tablet_mode_l {
+			gpios = <&gpioa 7 GPIO_INPUT>;
+			enum-name = "GPIO_TABLET_MODE_L";
+		};
+		gpio_usb_a0_ilimit_sdp: usb_a0_ilimit_sdp {
+			gpios = <&gpiol 5 GPIO_OUTPUT>;
+			enum-name = "GPIO_USB1_ILIM_SEL";
+		};
+		gpio_usb_c0_frs: usb_c0_frs {
+			gpios = <&gpioc 4 GPIO_OUTPUT>;
+		};
+		gpio_usb_c0_int_odl: usb_c0_int_odl {
+			gpios = <&gpiok 0 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_usb_c1_int_odl: usb_c1_int_odl {
+			gpios = <&gpioe 6 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_vccin_aux_vid0: vccin_aux_vid0 {
+			gpios = <&gpiod 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		gpio_vccin_aux_vid1: vccin_aux_vid1 {
+			gpios = <&gpiok 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		gpio_c1_charger_led_white_l: c1_charger_led_white_l {
+			gpios = <&gpiol 4 GPIO_OUTPUT_HIGH>;
+		};
+		gpio_c1_charger_led_amber_l: c1_charger_led_amber_l {
+			gpios = <&gpiod 4 GPIO_OUTPUT_HIGH>;
+		};
+		gpio_c0_charger_led_white_l: c0_charger_led_white_l {
+			gpios = <&gpioc 3 GPIO_OUTPUT_HIGH>;
+		};
+		gpio_c0_charger_led_amber_l: c0_charger_led_amber_l {
+			gpios = <&gpioj 7 GPIO_OUTPUT_HIGH>;
+		};
+		gpio_power_led_white_l: power_led_white_l {
+			gpios = <&gpioa 3 GPIO_OUTPUT_HIGH>;
+		};
+		gpio_ec_kso_02_inv: ec_kso_02_inv {
+			gpios = <&gpioksol 2 GPIO_OUTPUT_HIGH>;
+			enum-name = "GPIO_KBD_KSO2";
+		};
+		gpio_voldn_btn_odl: voldn_btn_odl {
+			gpios = <&gpioi 6 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_DOWN_L";
+		};
+		gpio_volup_btn_odl: volup_btn_odl {
+			gpios = <&gpioi 7 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_UP_L";
+		};
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		i2c_ec_i2c_eeprom: ec_i2c_eeprom {
+			i2c-port = <&i2c0>;
+			enum-names = "I2C_PORT_EEPROM";
+		};
+		i2c_ec_i2c_batt: ec_i2c_batt {
+			i2c-port = <&i2c1>;
+			enum-names = "I2C_PORT_BATTERY";
+		};
+		i2c_ec_i2c_sensor: ec_i2c_sensor {
+			i2c-port = <&i2c2>;
+			enum-names = "I2C_PORT_SENSOR";
+		};
+		i2c_ec_i2c_sub_usb_c1: ec_i2c_sub_usb_c1 {
+			i2c-port = <&i2c4>;
+			enum-names = "I2C_PORT_USB_C1_TCPC";
+		};
+		i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 {
+			i2c-port = <&i2c5>;
+			enum-names = "I2C_PORT_USB_C0_TCPC";
+		};
+	};
+};
diff --git a/zephyr/program/nissa/yavilla/keyboard.dtsi b/zephyr/program/nissa/yavilla/keyboard.dtsi
new file mode 100644
index 0000000000..87d7d718fa
--- /dev/null
+++ b/zephyr/program/nissa/yavilla/keyboard.dtsi
@@ -0,0 +1,72 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	kblight {
+		compatible = "cros-ec,kblight-pwm";
+		/*
+		 * Use 324 Hz so that 32Khz clock source is used,
+		 * which is not gated in power saving mode.
+		 */
+		pwms = <&pwm0 0 PWM_HZ(324) PWM_POLARITY_NORMAL>;
+	};
+};
+
+&pwm0 {
+	status = "okay";
+	prescaler-cx = <PWM_PRESCALER_C4>;
+	pinctrl-0 = <&pwm0_gpa0_default>;
+	pinctrl-names = "default";
+};
+
+&cros_kb_raw {
+	status = "okay";
+	/* No KSO2 (it's inverted and implemented by GPIO) */
+	pinctrl-0 = <&ksi0_default
+		     &ksi1_default
+		     &ksi2_default
+		     &ksi3_default
+		     &ksi4_default
+		     &ksi5_default
+		     &ksi6_default
+		     &ksi7_default
+		     &kso0_default
+		     &kso1_default
+		     &kso3_default
+		     &kso4_default
+		     &kso5_default
+		     &kso6_default
+		     &kso7_default
+		     &kso8_default
+		     &kso9_default
+		     &kso10_default
+		     &kso11_default
+		     &kso12_default
+		     &kso13_default
+		     &kso14_default>;
+	pinctrl-1 = <&ksi0_sleep
+		     &ksi1_sleep
+		     &ksi2_sleep
+		     &ksi3_sleep
+		     &ksi4_sleep
+		     &ksi5_sleep
+		     &ksi6_sleep
+		     &ksi7_sleep
+		     &kso0_sleep
+		     &kso1_sleep
+		     &kso3_sleep
+		     &kso4_sleep
+		     &kso5_sleep
+		     &kso6_sleep
+		     &kso7_sleep
+		     &kso8_sleep
+		     &kso9_sleep
+		     &kso10_sleep
+		     &kso11_sleep
+		     &kso12_sleep
+		     &kso13_sleep
+		     &kso14_sleep>;
+	pinctrl-names = "default", "sleep";
+};
diff --git a/zephyr/program/nissa/yavilla/motionsense.dtsi b/zephyr/program/nissa/yavilla/motionsense.dtsi
new file mode 100644
index 0000000000..df84c36471
--- /dev/null
+++ b/zephyr/program/nissa/yavilla/motionsense.dtsi
@@ -0,0 +1,148 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/motionsense/utils.h>
+
+
+/ {
+	aliases {
+		/*
+		 * Interrupt bindings for sensor devices.
+		 */
+		bmi3xx-int = &base_accel;
+		bma4xx-int = &lid_accel;
+	};
+
+	/*
+	 * Declare mutexes used by sensor drivers.
+	 * A mutex node is used to create an instance of mutex_t.
+	 * A mutex node is referenced by a sensor node if the
+	 * corresponding sensor driver needs to use the
+	 * instance of the mutex.
+	 */
+	motionsense-mutex {
+		compatible = "cros-ec,motionsense-mutex";
+		lid_mutex: lid-mutex {
+		};
+
+		base_mutex: base-mutex {
+		};
+	};
+
+	/* Rotation matrix used by drivers. */
+	motionsense-rotation-ref {
+		compatible = "cros-ec,motionsense-rotation-ref";
+		lid_rot_ref: lid-rotation-ref {
+			mat33 = <1 0 0
+				 0 (-1) 0
+				 0 0 (-1)>;
+		};
+
+		base_rot_ref: base-rotation-ref {
+			mat33 = <0 1 0
+				 1 0 0
+				 0 0 (-1)>;
+		};
+	};
+
+	/*
+	 * Driver specific data. A driver-specific data can be shared with
+	 * different motion sensors while they are using the same driver.
+	 *
+	 * If a node's compatible starts with "cros-ec,accelgyro-", it is for
+	 * a common structure defined in accelgyro.h.
+	 * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for
+	 * "struct als_drv_data_t" in accelgyro.h
+	 */
+	motionsense-sensor-data {
+		bmi323_data: bmi323-drv-data {
+			compatible = "cros-ec,drvdata-bmi3xx";
+			status = "okay";
+		};
+
+		bma422_data: bma4xx-drv-data {
+			compatible = "cros-ec,drvdata-bma4xx";
+			status = "okay";
+		};
+	};
+
+	/*
+	 * List of motion sensors that creates motion_sensors array.
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
+	 * motion sensor IDs for lid angle calculation.
+	 * TODO(b/238139272): The first entries of the array must be
+	 * accelerometers,then gyroscope. Fix this dependency in the DTS
+	 * processing which makes the devicetree entries independent.
+	 */
+	motionsense-sensor {
+		lid_accel: lid-accel {
+			compatible = "cros-ec,bma4xx";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&lid_mutex>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&lid_rot_ref>;
+			default-range = <2>;
+			drv-data = <&bma422_data>;
+			i2c-spi-addr-flags = "BMA4_I2C_ADDR_PRIMARY";
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_accel: base-accel {
+			compatible = "cros-ec,bmi3xx-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&bmi323_data>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_gyro: base-gyro {
+			compatible = "cros-ec,bmi3xx-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&bmi323_data>;
+		};
+	};
+
+	motionsense-sensor-info {
+		compatible = "cros-ec,motionsense-sensor-info";
+
+		/*
+		 * list of GPIO interrupts that have to
+		 * be enabled at initial stage
+		 */
+		sensor-irqs = <&int_imu &int_acc>;
+	};
+};
diff --git a/zephyr/program/nissa/yavilla/overlay.dtsi b/zephyr/program/nissa/yavilla/overlay.dtsi
new file mode 100644
index 0000000000..f3c1b7139d
--- /dev/null
+++ b/zephyr/program/nissa/yavilla/overlay.dtsi
@@ -0,0 +1,375 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <cros/thermistor/thermistor.dtsi>
+#include <dt-bindings/usb_pd_tcpm.h>
+
+/ {
+	aliases {
+		gpio-cbi-wp = &gpio_ec_cbi_wp;
+		gpio-wp = &gpio_ec_wp_odl;
+		int-wp = &int_wp_l;
+	};
+
+	ec-console {
+		compatible = "ec-console";
+		disabled = "events", "lpc", "hostcmd";
+	};
+
+	batteries {
+		default_battery: cosmx {
+			compatible = "cosmx,gg02047xl", "battery-smart";
+		};
+		dynapack_byd_gg02047xl {
+			compatible = "dynapack,byd_gg02047xl", "battery-smart";
+		};
+		dynapack_hpp_gg02047xl {
+			compatible = "dynapack,hpp_gg02047xl", "battery-smart";
+		};
+		atl_gb-s20-4473a9 {
+			compatible = "atl,gb-s20-4473a9", "battery-smart";
+		};
+	};
+
+	hibernate-wake-pins {
+		compatible = "cros-ec,hibernate-wake-pins";
+		wakeup-irqs = <
+			&int_power_button
+			&int_lid_open
+		>;
+	};
+
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_power_button: power_button {
+			irq-pin = <&gpio_gsc_ec_pwr_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_button_interrupt";
+		};
+		int_vol_down: vol_down {
+			irq-pin = <&gpio_voldn_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+		int_vol_up: vol_up {
+			irq-pin = <&gpio_volup_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+		int_wp_l: wp_l {
+			irq-pin = <&gpio_ec_wp_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "switch_interrupt";
+		};
+		int_lid_open: lid_open {
+			irq-pin = <&gpio_lid_open>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "lid_interrupt";
+		};
+		int_tablet_mode: tablet_mode {
+			irq-pin = <&gpio_tablet_mode_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "gmr_tablet_switch_isr";
+		};
+		int_acc: lid_imu {
+		  irq-pin = <&gpio_acc_int_l>;
+		  flags = <GPIO_INT_EDGE_FALLING>;
+		  handler = "bma4xx_interrupt";
+		};
+		int_imu: ec_imu {
+		  irq-pin = <&gpio_imu_int_l>;
+		  flags = <GPIO_INT_EDGE_FALLING>;
+		  handler = "bmi3xx_interrupt";
+		};
+		int_pen_det_l: pen_det_l {
+			irq-pin = <&gpio_pen_detect_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "pen_detect_interrupt";
+		};
+		int_usb_c0: usb_c0 {
+			irq-pin = <&gpio_usb_c0_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "usb_c0_interrupt";
+		};
+		int_usb_c1: usb_c1 {
+			irq-pin = <&gpio_usb_c1_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "usb_c1_interrupt";
+		};
+	};
+
+	unused-pins {
+		compatible = "unused-gpios";
+		unused-gpios = <&gpioc 6 0>,
+			       <&gpiod 7 0>,
+			       <&gpioh 2 0>,
+			       <&gpioj 3 0>,
+			       <&gpiok 7 GPIO_OUTPUT>;
+	};
+
+	named-gpios {
+		/*
+		 * EC doesn't take any specific action on CC/SBU disconnect due to
+		 * fault, but this definition is useful for hardware testing.
+		 */
+		gpio_usb_c0_prot_fault_odl: usb_c0_prot_fault_odl {
+			gpios = <&gpiok 6 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_fan_enable: fan-enable {
+			gpios = <&gpioa 1 GPIO_OUTPUT>;
+			no-auto-init;
+		};
+	};
+
+	temp_cpu_thermistor: cpu {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_1>;
+	};
+	temp_5v_regulator_thermistor: 5v-regulator {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_2>;
+	};
+	temp_charger_thermistor: charger {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_3>;
+	};
+
+	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
+		temp_cpu: cpu {
+			temp_fan_off = <45>;
+			temp_fan_max = <60>;
+			temp_host_high = <75>;
+			temp_host_halt = <85>;
+			temp_host_release_high = <65>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_cpu_thermistor>;
+		};
+		temp_5v_regulator: 5v-regulator {
+			temp_fan_off = <50>;
+			temp_fan_max = <65>;
+			temp_host_high = <75>;
+			temp_host_halt = <85>;
+			temp_host_release_high = <65>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_5v_regulator_thermistor>;
+		};
+		temp_charger: charger {
+			temp_fan_off = <50>;
+			temp_fan_max = <65>;
+			temp_host_high = <80>;
+			temp_host_halt = <85>;
+			temp_host_release_high = <75>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_charger_thermistor>;
+		};
+	};
+
+	usba {
+		compatible = "cros-ec,usba-port-enable-pins";
+		/*
+		 * ILIM_SEL pins are referred to by legacy enum name,
+		 * GPIO_USB*_ILIM_SEL.
+		 */
+		enable-pins = <&gpio_en_usb_a0_vbus &gpio_en_usb_a1_vbus>;
+		status = "okay";
+	};
+
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+			chg = <&chg_port0>;
+			tcpc = <&usbpd0>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_0>;
+			};
+		};
+		port0-muxes {
+			virtual_mux_0: virtual-mux-0 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+		port1@1 {
+			compatible = "named-usbc-port";
+			reg = <1>;
+			chg = <&chg_port1>;
+			tcpc = <&tcpc_port1>;
+			usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_1 &tcpci_mux_1>;
+			};
+			usb_mux_chain_1_no_mux: usb-mux-chain-1-no-mux {
+				compatible = "cros-ec,usb-mux-chain";
+				alternative-chain;
+				usb-muxes = <&virtual_mux_1>;
+			};
+		};
+		port1-muxes {
+			virtual_mux_1: virtual-mux-1 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+			tcpci_mux_1: tcpci-mux-1 {
+				compatible = "parade,usbc-mux-ps8xxx";
+			};
+		};
+	};
+};
+
+&binman {
+	ec-rw {
+		size = <0x58000>;
+		rw-fw {
+			rw-fwid {
+				/* Fix the lcoation of the FWID to the
+				 * last 32 bytes of the flash. This
+				 * ensures the RW entries in the FMAP
+				 * stored in the RO section of flash
+				 * are always correct.
+				 */
+				offset = <(0x58000 - 32)>;
+			};
+		};
+	};
+	pad-after = <0x48000>;
+};
+
+&thermistor_3V3_51K1_47K_4050B {
+	status = "okay";
+};
+
+&adc_ec_vsense_pp3300_s5 {
+	/*
+	 * Voltage divider on input has 47k upper and 220k lower legs with 3 V
+	 * full-scale reading on the ADC. Apply the largest possible multiplier
+	 * (without overflowing int32) to get the best possible approximation
+	 * of the actual ratio, but derate by a factor of two to ensure
+	 * unexpectedly high values won't overflow.
+	 */
+	mul = <(715828 / 2)>;
+	div = <(589820 / 2)>;
+};
+
+&adc0 {
+	pinctrl-0 = <&adc0_ch0_gpi0_default
+		     &adc0_ch2_gpi2_default
+		     &adc0_ch3_gpi3_default
+		     &adc0_ch13_gpl0_default
+		     &adc0_ch14_gpl1_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&pinctrl {
+	i2c4_clk_gpe0_sleep: i2c4_clk_gpe0_sleep {
+		pinmuxs = <&pinctrle 0 IT8XXX2_ALT_DEFAULT>;
+	};
+	i2c4_data_gpe7_sleep: i2c4_data_gpe7_sleep {
+		pinmuxs = <&pinctrle 7 IT8XXX2_ALT_DEFAULT>;
+	};
+	i2c2_clk_gpf6_default: i2c2_clk_gpf6_default {
+		gpio-voltage = "1v8";
+	};
+	i2c2_data_gpf7_default: i2c2_data_gpf7_default {
+		gpio-voltage = "1v8";
+	};
+};
+
+&i2c0 {
+	label = "I2C_EEPROM";
+	clock-frequency = <I2C_BITRATE_FAST>;
+
+	cbi_eeprom: eeprom@50 {
+		compatible = "atmel,at24";
+		reg = <0x50>;
+		label = "EEPROM_CBI";
+		size = <2048>;
+		pagesize = <16>;
+		address-width = <8>;
+		timeout = <5>;
+	};
+	pinctrl-0 = <&i2c0_clk_gpb3_default
+		     &i2c0_data_gpb4_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&i2c1 {
+	label = "I2C_BATTERY";
+	clock-frequency = <50000>;
+	pinctrl-0 = <&i2c1_clk_gpc1_default
+		     &i2c1_data_gpc2_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&i2c2 {
+	label = "I2C_SENSOR";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c2_clk_gpf6_default
+		     &i2c2_data_gpf7_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&i2c4 {
+	label = "I2C_SUB_C1_TCPC";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+	pinctrl-0 = <&i2c4_clk_gpe0_default
+		     &i2c4_data_gpe7_default>;
+	pinctrl-1 = <&i2c4_clk_gpe0_sleep
+		     &i2c4_data_gpe7_sleep>;
+	pinctrl-names = "default", "sleep";
+	status = "okay";
+
+	chg_port1: sm5803@32 {
+		compatible = "siliconmitus,sm5803";
+		status = "okay";
+		reg = <0x32>;
+	};
+
+	tcpc_port1: ps8745@b {
+		compatible = "parade,ps8xxx";
+		reg = <0xb>;
+		tcpc-flags = <(TCPC_FLAGS_TCPCI_REV2_0)>;
+	};
+};
+
+&i2c_ec_i2c_sub_usb_c1 {
+	/*
+	 * Dynamic speed setting is used for AP-controlled firmware update
+	 * of PS8745 TCPC/redriver: the AP lowers speed to 400 kHz in order
+	 * to use more efficient window programming, then sets it back when
+	 * done.
+	 */
+	dynamic-speed;
+};
+
+&i2c5 {
+	label = "I2C_USB_C0_TCPC";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+	pinctrl-0 = <&i2c5_clk_gpa4_default
+		     &i2c5_data_gpa5_default>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	chg_port0: sm5803@32 {
+		compatible = "siliconmitus,sm5803";
+		status = "okay";
+		reg = <0x32>;
+	};
+};
+
+&usbpd0 {
+	status = "okay";
+};
diff --git a/zephyr/program/nissa/yavilla/power_signals.dtsi b/zephyr/program/nissa/yavilla/power_signals.dtsi
new file mode 100644
index 0000000000..d64ac83150
--- /dev/null
+++ b/zephyr/program/nissa/yavilla/power_signals.dtsi
@@ -0,0 +1,180 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	chosen {
+		intel-ap-pwrseq,espi = &espi0;
+	};
+
+	common-pwrseq {
+		compatible = "intel,ap-pwrseq";
+
+		sys-pwrok-delay = <10>;
+		all-sys-pwrgd-timeout = <20>;
+	};
+
+	pwr-en-pp5000-s5 {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PP5000_S5 enable output to regulator";
+		enum-name = "PWR_EN_PP5000_A";
+		gpios = <&gpiok 5 0>;
+		output;
+	};
+	pwr-en-pp3300-s5 {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PP3300_S5 enable output to LS";
+		enum-name = "PWR_EN_PP3300_A";
+		gpios = <&gpioc 5 0>;
+		output;
+	};
+	pwr-pg-ec-rsmrst-odl {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST power good from regulator";
+		enum-name = "PWR_RSMRST";
+		gpios = <&gpioe 1 0>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-ec-pch-rsmrst-odl {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST output to PCH";
+		enum-name = "PWR_EC_PCH_RSMRST";
+		gpios = <&gpioh 0 0>;
+		output;
+	};
+	pwr-slp-s0-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_S0_L input from PCH";
+		enum-name = "PWR_SLP_S0";
+		gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-slp-s3-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_S3_L input from PCH";
+		enum-name = "PWR_SLP_S3";
+		gpios = <&gpioh 3 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-slp-sus-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_SUS_L input from PCH";
+		enum-name = "PWR_SLP_SUS";
+		gpios = <&gpiog 2 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-ec-soc-dsw-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "DSW_PWROK output to PCH";
+		enum-name = "PWR_EC_SOC_DSW_PWROK";
+		gpios = <&gpiol 7 0>;
+		output;
+	};
+	pwr-vccst-pwrgd-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "VCCST_PWRGD output to PCH";
+		enum-name = "PWR_VCCST_PWRGD";
+		gpios = <&gpioe 5 (GPIO_OPEN_DRAIN | GPIO_VOLTAGE_1P8)>;
+		output;
+	};
+	pwr-imvp9-vrrdy-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "VRRDY input from IMVP9";
+		enum-name = "PWR_IMVP9_VRRDY";
+		gpios = <&gpioj 4 0>;
+	};
+	pwr-pch-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PCH_PWROK output to PCH";
+		enum-name = "PWR_PCH_PWROK";
+		gpios = <&gpiod 6 GPIO_OPEN_DRAIN>;
+		output;
+	};
+	pwr-ec-pch-sys-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_PWROK output to PCH";
+		enum-name = "PWR_EC_PCH_SYS_PWROK";
+		gpios = <&gpiof 2 0>;
+		output;
+	};
+	pwr-sys-rst-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_RESET# output to PCH";
+		enum-name = "PWR_SYS_RST";
+		gpios = <&gpiod 1 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>;
+		output;
+	};
+	pwr-slp-s4 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S4 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S4";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4";
+		vw-invert;
+	};
+	pwr-slp-s5 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S5 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S5";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5";
+		vw-invert;
+	};
+	pwr-all-sys-pwrgd {
+		/*
+		 * This is a board level signal, since this
+		 * signal needs some special processing.
+		 */
+		compatible = "intel,ap-pwrseq-external";
+		dbg-label = "Combined all power good";
+		enum-name = "PWR_ALL_SYS_PWRGD";
+	};
+	pwr-adc-pp3300 {
+		compatible = "intel,ap-pwrseq-adc";
+		dbg-label = "PP3300_PROC";
+		enum-name = "PWR_DSW_PWROK";
+		trigger-high = <&vcmp0>;
+		trigger-low = <&vcmp1>;
+	};
+	pwr-adc-pp1p05 {
+		compatible = "intel,ap-pwrseq-adc";
+		dbg-label = "PP1P05_PROC";
+		enum-name = "PWR_PG_PP1P05";
+		trigger-high = <&vcmp2>;
+		trigger-low = <&vcmp3>;
+	};
+
+};
+
+&vcmp0 {
+	status = "okay";
+	scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>;
+	comparison = <IT8XXX2_VCMP_GREATER>;
+	/*
+	 * This is 90% of nominal voltage considering voltage
+	 * divider on ADC input.
+	 */
+	threshold-mv = <2448>;
+	io-channels = <&adc0 0>;
+};
+&vcmp1 {
+	status = "okay";
+	scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>;
+	comparison = <IT8XXX2_VCMP_LESS_OR_EQUAL>;
+	threshold-mv = <2448>;
+	io-channels = <&adc0 0>;
+};
+&vcmp2 {
+	status = "okay";
+	scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>;
+	comparison = <IT8XXX2_VCMP_GREATER>;
+	/* Setting at 90% of nominal voltage */
+	threshold-mv = <945>;
+	io-channels = <&adc0 14>;
+};
+&vcmp3 {
+	status = "okay";
+	scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>;
+	comparison = <IT8XXX2_VCMP_LESS_OR_EQUAL>;
+	threshold-mv = <945>;
+	io-channels = <&adc0 14>;
+};
diff --git a/zephyr/program/nissa/yavilla/project.conf b/zephyr/program/nissa/yavilla/project.conf
new file mode 100644
index 0000000000..a36bcb798c
--- /dev/null
+++ b/zephyr/program/nissa/yavilla/project.conf
@@ -0,0 +1,43 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_BOARD_YAVILLA=y
+
+# Ensure recovery key combination (esc+refresh+power) is reliable: b/236580049
+CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI3=y
+CONFIG_PLATFORM_EC_KEYBOARD_REFRESH_ROW3=y
+
+# Sensors
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y
+CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y
+CONFIG_PLATFORM_EC_DYNAMIC_MOTION_SENSOR_COUNT=y
+CONFIG_PLATFORM_EC_MAX_SENSOR_FREQ_MILLIHZ=100000
+
+# Keyboard
+CONFIG_PLATFORM_EC_KEYBOARD_KEYPAD=y
+CONFIG_PLATFORM_EC_KBLIGHT_ENABLE_PIN=n
+CONFIG_PLATFORM_EC_KEYBOARD_FACTORY_TEST=y
+
+# Fan
+CONFIG_PLATFORM_EC_CUSTOM_FAN_CONTROL=y
+
+# LED
+CONFIG_PLATFORM_EC_LED_PWM=n
+CONFIG_PLATFORM_EC_LED_ONOFF_STATES=n
+
+CONFIG_NISSA_SUB_BOARD=n
+
+# Both ports use a SLGC55545 smart switch with CTL1..3 fixed high,
+# for SDP2 or CDP only.
+CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART=y
+CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_CDP_SDP_ONLY=y
+CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_DEFAULT_CDP=y
+CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_INVERTED=y
+
+# Charger
+CONFIG_PLATFORM_EC_CHARGER_INPUT_CURRENT_DERATE_PCT=0
+
+#Disable USBC BC12
+CONFIG_PLATFORM_EC_USB_CHARGER=n
diff --git a/zephyr/program/nissa/yavilla/project.overlay b/zephyr/program/nissa/yavilla/project.overlay
new file mode 100644
index 0000000000..40bbaec4bb
--- /dev/null
+++ b/zephyr/program/nissa/yavilla/project.overlay
@@ -0,0 +1,14 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "../shi.dtsi"
+
+#include "cbi.dtsi"
+#include "fan.dtsi"
+#include "gpio.dtsi"
+#include "keyboard.dtsi"
+#include "motionsense.dtsi"
+#include "overlay.dtsi"
+#include "power_signals.dtsi"
diff --git a/zephyr/program/nissa/yavilla/src/board.c b/zephyr/program/nissa/yavilla/src/board.c
new file mode 100644
index 0000000000..2ded723ab7
--- /dev/null
+++ b/zephyr/program/nissa/yavilla/src/board.c
@@ -0,0 +1,112 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* yavilla hardware configuration */
+#include "cros_cbi.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "motion_sense.h"
+#include "nissa_common.h"
+#include "tablet_mode.h"
+#include "task.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/printk.h>
+
+#include <ap_power/ap_power.h>
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+__override uint8_t board_get_usb_pd_port_count(void)
+{
+	return 2;
+}
+/*
+ * Enable interrupts
+ */
+static void board_init(void)
+{
+	int ret;
+	uint32_t val;
+
+	/*
+	 * Retrieve the tablet config.
+	 */
+	ret = cros_cbi_get_fw_config(FW_TABLET, &val);
+	if (ret != 0) {
+		LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_TABLET);
+		return;
+	}
+
+	/*
+	 * Enable USB-C interrupts.
+	 */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0));
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1));
+
+	/*
+	 * Disable tablet related interrupts for tablet absent DUT.
+	 */
+	if (val == FW_TABLET_ABSENT) {
+		motion_sensor_count = 0;
+		gmr_tablet_switch_disable();
+		gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_imu));
+		/* Base accel is not stuffed, don't allow line to float */
+		gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_imu_int_l),
+				      GPIO_INPUT | GPIO_PULL_DOWN);
+		/* Lid accel is not stuffed, don't allow line to float */
+		gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_acc_int_l),
+				      GPIO_INPUT | GPIO_PULL_DOWN);
+		LOG_INF("Clameshell: Disable motion sensors and gmr sensor!");
+	} else
+		LOG_INF("Convertible!!!");
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_POST_I2C);
+
+void pen_detect_interrupt(enum gpio_signal s)
+{
+	int pen_detect =
+		!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_pen_detect_odl));
+
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pp5000_pen_x),
+			pen_detect);
+}
+
+__override void board_power_change(struct ap_power_ev_callback *cb,
+				   struct ap_power_ev_data data)
+{
+	const struct gpio_dt_spec *const pen_power_gpio =
+		GPIO_DT_FROM_NODELABEL(gpio_en_pp5000_pen_x);
+	const struct gpio_dt_spec *const pen_detect_gpio =
+		GPIO_DT_FROM_NODELABEL(gpio_pen_detect_odl);
+	const struct gpio_int_config *const pen_detect_int =
+		GPIO_INT_FROM_NODELABEL(int_pen_det_l);
+
+	switch (data.event) {
+	case AP_POWER_STARTUP:
+		/* Enable Pen Detect interrupt */
+		gpio_enable_dt_interrupt(pen_detect_int);
+		/*
+		 * Make sure pen detection is triggered or not when AP power on
+		 */
+		if (!gpio_pin_get_dt(pen_detect_gpio))
+			gpio_pin_set_dt(pen_power_gpio, 1);
+		break;
+	case AP_POWER_SHUTDOWN:
+		/*
+		 * Disable pen detect INT and turn off pen power when AP
+		 * shutdown
+		 */
+		gpio_disable_dt_interrupt(pen_detect_int);
+		gpio_pin_set_dt(pen_power_gpio, 0);
+		break;
+	default:
+		break;
+	}
+}
diff --git a/zephyr/program/nissa/yavilla/src/charger.c b/zephyr/program/nissa/yavilla/src/charger.c
new file mode 100644
index 0000000000..18aa1068d0
--- /dev/null
+++ b/zephyr/program/nissa/yavilla/src/charger.c
@@ -0,0 +1,55 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "charger.h"
+#include "console.h"
+#include "driver/charger/sm5803.h"
+#include "extpower.h"
+#include "usb_pd.h"
+
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+int extpower_is_present(void)
+{
+	int port;
+	int rv;
+	bool acok;
+
+	for (port = 0; port < board_get_usb_pd_port_count(); port++) {
+		rv = sm5803_is_acok(port, &acok);
+		if ((rv == EC_SUCCESS) && acok)
+			return 1;
+	}
+
+	return 0;
+}
+
+/*
+ * Yavilla does not have a GPIO indicating whether extpower is present,
+ * so detect using the charger(s).
+ */
+__override void board_check_extpower(void)
+{
+	static int last_extpower_present;
+	int extpower_present = extpower_is_present();
+
+	if (last_extpower_present ^ extpower_present)
+		extpower_handle_update(extpower_present);
+
+	last_extpower_present = extpower_present;
+}
+
+__override void board_hibernate(void)
+{
+	/* Shut down the chargers */
+	if (board_get_usb_pd_port_count() == 2)
+		sm5803_hibernate(CHARGER_SECONDARY);
+	sm5803_hibernate(CHARGER_PRIMARY);
+	LOG_INF("Charger(s) hibernated");
+	cflush();
+}
diff --git a/zephyr/program/nissa/yavilla/src/fan.c b/zephyr/program/nissa/yavilla/src/fan.c
new file mode 100644
index 0000000000..07517abbe9
--- /dev/null
+++ b/zephyr/program/nissa/yavilla/src/fan.c
@@ -0,0 +1,36 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "cros_cbi.h"
+#include "fan.h"
+#include "gpio/gpio.h"
+#include "hooks.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/logging/log.h>
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+static void fan_init(void)
+{
+	int ret;
+	uint32_t val;
+	/*
+	 * Retrieve the fan config.
+	 */
+	ret = cros_cbi_get_fw_config(FW_FAN, &val);
+	if (ret != 0) {
+		LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_FAN);
+		return;
+	}
+	if (val != FW_FAN_PRESENT) {
+		/* Disable the fan */
+		fan_set_count(0);
+	} else {
+		/* Configure the fan enable GPIO */
+		gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_fan_enable),
+				      GPIO_OUTPUT);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, fan_init, HOOK_PRIO_POST_FIRST);
diff --git a/zephyr/program/nissa/yavilla/src/keyboard.c b/zephyr/program/nissa/yavilla/src/keyboard.c
new file mode 100644
index 0000000000..d942405faa
--- /dev/null
+++ b/zephyr/program/nissa/yavilla/src/keyboard.c
@@ -0,0 +1,103 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "cros_cbi.h"
+#include "ec_commands.h"
+#include "gpio_it8xxx2.h"
+#include "hooks.h"
+#include "keyboard_8042_sharedlib.h"
+#include "keyboard_scan.h"
+#include "timer.h"
+
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+static const struct ec_response_keybd_config kb_tablet_present = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+	/* No function keys, no numeric keypad */
+};
+
+static const struct ec_response_keybd_config kb_tablet_absent = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	/* No function keys, no numeric keypad and no screenlock key */
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	uint32_t val;
+
+	cros_cbi_get_fw_config(FW_TABLET, &val);
+
+	if (val == FW_TABLET_PRESENT)
+		return &kb_tablet_present;
+	else
+		return &kb_tablet_absent;
+}
+
+/*
+ * Keyboard layout decided by FW config.
+ */
+static void kb_layout_init(void)
+{
+	int ret;
+	uint32_t val;
+
+	ret = cros_cbi_get_fw_config(FW_KB_LAYOUT, &val);
+	if (ret != 0) {
+		LOG_ERR("Error retrieving CBI FW_CONFIG field %d",
+			FW_KB_LAYOUT);
+		return;
+	}
+	/*
+	 * If keyboard is US2(FW_KB_LAYOUT_US2), we need translate right ctrl
+	 * to backslash(\|) key.
+	 */
+	if (val == FW_KB_LAYOUT_US2)
+		set_scancode_set2(4, 0, get_scancode_set2(2, 7));
+}
+DECLARE_HOOK(HOOK_INIT, kb_layout_init, HOOK_PRIO_POST_FIRST);
+
+/*
+ * Map keyboard connector pins to EC GPIO pins for factory test.
+ * Pins mapped to {-1, -1} are skipped.
+ * The connector has 24 pins total, and there is no pin 0.
+ */
+const int keyboard_factory_scan_pins[][2] = {
+	{ -1, -1 },	  { GPIO_KSOH, 4 }, { GPIO_KSOH, 0 }, { GPIO_KSOH, 1 },
+	{ GPIO_KSOH, 3 }, { GPIO_KSOH, 2 }, { GPIO_KSOL, 5 }, { GPIO_KSOL, 6 },
+	{ GPIO_KSOL, 3 }, { GPIO_KSOL, 2 }, { GPIO_KSI, 0 },  { GPIO_KSOL, 1 },
+	{ GPIO_KSOL, 4 }, { GPIO_KSI, 3 },  { GPIO_KSI, 2 },  { GPIO_KSOL, 0 },
+	{ GPIO_KSI, 5 },  { GPIO_KSI, 4 },  { GPIO_KSOL, 7 }, { GPIO_KSI, 6 },
+	{ GPIO_KSI, 7 },  { GPIO_KSI, 1 },  { -1, -1 },	      { -1, -1 },
+	{ -1, -1 },
+};
+const int keyboard_factory_scan_pins_used =
+	ARRAY_SIZE(keyboard_factory_scan_pins);
diff --git a/zephyr/program/nissa/yavilla/src/led.c b/zephyr/program/nissa/yavilla/src/led.c
new file mode 100644
index 0000000000..8a2756691f
--- /dev/null
+++ b/zephyr/program/nissa/yavilla/src/led.c
@@ -0,0 +1,309 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "chipset.h"
+#include "cros_cbi.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "led_common.h"
+
+#include <stdint.h>
+
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+#define BAT_LED_ON 0
+#define BAT_LED_OFF 1
+
+#define PWR_LED_ON 0
+#define PWR_LED_OFF 1
+
+#define BATT_LOW_BCT 10
+
+#define LED_TICKS_PER_CYCLE 4
+#define LED_TICKS_PER_CYCLE_S3 4
+#define LED_ON_TICKS 2
+#define POWER_LED_ON_S3_TICKS 2
+
+static bool power_led_support;
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_RIGHT_LED,
+					     EC_LED_ID_LEFT_LED,
+					     EC_LED_ID_POWER_LED };
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+enum led_color {
+	LED_OFF = 0,
+	LED_AMBER,
+	LED_WHITE,
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
+};
+
+enum led_port { RIGHT_PORT = 0, LEFT_PORT };
+
+static void led_set_color_battery(int port, enum led_color color)
+{
+	const struct gpio_dt_spec *amber_led, *white_led;
+
+	if (port == RIGHT_PORT) {
+		amber_led = GPIO_DT_FROM_NODELABEL(gpio_c0_charger_led_amber_l);
+		white_led = GPIO_DT_FROM_NODELABEL(gpio_c0_charger_led_white_l);
+	} else if (port == LEFT_PORT) {
+		amber_led = GPIO_DT_FROM_NODELABEL(gpio_c1_charger_led_amber_l);
+		white_led = GPIO_DT_FROM_NODELABEL(gpio_c1_charger_led_white_l);
+	}
+
+	switch (color) {
+	case LED_WHITE:
+		gpio_pin_set_dt(white_led, BAT_LED_ON);
+		gpio_pin_set_dt(amber_led, BAT_LED_OFF);
+		break;
+	case LED_AMBER:
+		gpio_pin_set_dt(white_led, BAT_LED_OFF);
+		gpio_pin_set_dt(amber_led, BAT_LED_ON);
+		break;
+	case LED_OFF:
+		gpio_pin_set_dt(white_led, BAT_LED_OFF);
+		gpio_pin_set_dt(amber_led, BAT_LED_OFF);
+		break;
+	default:
+		break;
+	}
+}
+
+static void led_set_color_power(enum led_color color)
+{
+	switch (color) {
+	case LED_OFF:
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_power_led_white_l),
+				PWR_LED_OFF);
+		break;
+	case LED_WHITE:
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_power_led_white_l),
+				PWR_LED_ON);
+		break;
+	default:
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	switch (led_id) {
+	case EC_LED_ID_LEFT_LED:
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		break;
+	case EC_LED_ID_RIGHT_LED:
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		break;
+	case EC_LED_ID_POWER_LED:
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		break;
+	default:
+		break;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	switch (led_id) {
+	case EC_LED_ID_LEFT_LED:
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_battery(LEFT_PORT, LED_WHITE);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(LEFT_PORT, LED_AMBER);
+		else
+			led_set_color_battery(LEFT_PORT, LED_OFF);
+		break;
+	case EC_LED_ID_RIGHT_LED:
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_battery(RIGHT_PORT, LED_WHITE);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(RIGHT_PORT, LED_AMBER);
+		else
+			led_set_color_battery(RIGHT_PORT, LED_OFF);
+		break;
+	case EC_LED_ID_POWER_LED:
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_power(LED_WHITE);
+		else
+			led_set_color_power(LED_OFF);
+		break;
+	default:
+		return EC_ERROR_PARAM1;
+	}
+
+	return EC_SUCCESS;
+}
+
+/*
+ * Set active charge port color to the parameter, turn off all others.
+ * If no port is active (-1), turn off all LEDs.
+ */
+static void set_active_port_color(enum led_color color)
+{
+	int port = charge_manager_get_active_charge_port();
+
+	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
+		led_set_color_battery(RIGHT_PORT,
+				      (port == RIGHT_PORT) ? color : LED_OFF);
+	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
+		led_set_color_battery(LEFT_PORT,
+				      (port == LEFT_PORT) ? color : LED_OFF);
+}
+
+static void led_set_battery(void)
+{
+	static unsigned int battery_ticks;
+	static int suspend_ticks;
+
+	battery_ticks++;
+
+	/*
+	 * Override battery LEDs for Yavilla without power led support,
+	 * blinking both two side battery white LEDs to indicate
+	 * system suspend with non-charging state.
+	 */
+	if (!power_led_support && chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
+	    led_pwr_get_state() != LED_PWRS_CHARGE) {
+		suspend_ticks++;
+
+		led_set_color_battery(RIGHT_PORT,
+				      suspend_ticks % LED_TICKS_PER_CYCLE_S3 <
+						      POWER_LED_ON_S3_TICKS ?
+					      LED_WHITE :
+					      LED_OFF);
+		led_set_color_battery(LEFT_PORT,
+				      suspend_ticks % LED_TICKS_PER_CYCLE_S3 <
+						      POWER_LED_ON_S3_TICKS ?
+					      LED_WHITE :
+					      LED_OFF);
+		return;
+	}
+
+	suspend_ticks = 0;
+
+	switch (led_pwr_get_state()) {
+	case LED_PWRS_CHARGE:
+		/* Always indicate when charging, even in suspend. */
+		set_active_port_color(LED_AMBER);
+		break;
+	case LED_PWRS_DISCHARGE:
+		/*
+		 * Blinking amber LEDs slowly if battery is lower 10
+		 * percentage.
+		 */
+		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
+			if (charge_get_percent() < BATT_LOW_BCT)
+				led_set_color_battery(
+					RIGHT_PORT,
+					(battery_ticks % LED_TICKS_PER_CYCLE <
+					 LED_ON_TICKS) ?
+						LED_AMBER :
+						LED_OFF);
+			else
+				led_set_color_battery(RIGHT_PORT, LED_OFF);
+		}
+
+		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) {
+			if (charge_get_percent() < BATT_LOW_BCT)
+				led_set_color_battery(
+					LEFT_PORT,
+					(battery_ticks % LED_TICKS_PER_CYCLE <
+					 LED_ON_TICKS) ?
+						LED_AMBER :
+						LED_OFF);
+			else
+				led_set_color_battery(LEFT_PORT, LED_OFF);
+		}
+		break;
+	case LED_PWRS_ERROR:
+		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
+			led_set_color_battery(
+				RIGHT_PORT,
+				(battery_ticks & 0x1) ? LED_AMBER : LED_OFF);
+		}
+
+		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) {
+			led_set_color_battery(LEFT_PORT, (battery_ticks & 0x1) ?
+								 LED_AMBER :
+								 LED_OFF);
+		}
+		break;
+	case LED_PWRS_CHARGE_NEAR_FULL:
+		set_active_port_color(LED_WHITE);
+		break;
+	case LED_PWRS_IDLE: /* External power connected in IDLE */
+		set_active_port_color(LED_WHITE);
+		break;
+	case LED_PWRS_FORCED_IDLE:
+		set_active_port_color(
+			(battery_ticks % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
+				LED_AMBER :
+				LED_OFF);
+		break;
+	default:
+		/* Other states don't alter LED behavior */
+		break;
+	}
+}
+
+static void led_set_power(void)
+{
+	static int power_ticks;
+
+	power_ticks++;
+
+	if (chipset_in_state(CHIPSET_STATE_ON))
+		led_set_color_power(LED_WHITE);
+	else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
+		led_set_color_power((power_ticks % LED_TICKS_PER_CYCLE_S3 <
+				     POWER_LED_ON_S3_TICKS) ?
+					    LED_WHITE :
+					    LED_OFF);
+	else
+		led_set_color_power(LED_OFF);
+}
+
+static void power_led_check(void)
+{
+	int ret;
+	uint32_t val;
+
+	/*
+	 * Retrieve the tablet config.
+	 */
+	ret = cros_cbi_get_fw_config(FW_TABLET, &val);
+	if (ret != 0) {
+		LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_TABLET);
+		return;
+	}
+
+	if (val == FW_TABLET_PRESENT)
+		power_led_support = true;
+	else /* Clameshell */
+		power_led_support = false;
+}
+DECLARE_HOOK(HOOK_INIT, power_led_check, HOOK_PRIO_DEFAULT);
+
+/* Called by hook task every TICK(IT83xx 500ms) */
+static void led_tick(void)
+{
+	led_set_battery();
+
+	if (power_led_support &&
+	    led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		led_set_power();
+}
+DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
diff --git a/zephyr/program/nissa/yavilla/src/thermal.c b/zephyr/program/nissa/yavilla/src/thermal.c
new file mode 100644
index 0000000000..b2e4796837
--- /dev/null
+++ b/zephyr/program/nissa/yavilla/src/thermal.c
@@ -0,0 +1,108 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "fan.h"
+#include "temp_sensor/temp_sensor.h"
+#include "thermal.h"
+#include "util.h"
+
+#include <ap_power/ap_power_interface.h>
+
+#define TEMP_CPU TEMP_SENSOR_ID(DT_NODELABEL(temp_cpu))
+#define TEMP_5V TEMP_SENSOR_ID(DT_NODELABEL(temp_5v_regulator))
+#define TEMP_CHARGER TEMP_SENSOR_ID(DT_NODELABEL(temp_charger))
+
+struct fan_step {
+	/*
+	 * Sensor 1~3 trigger point, set -1 if we're not using this
+	 * sensor to determine fan speed.
+	 */
+	int8_t on[TEMP_SENSOR_COUNT];
+	/*
+	 * Sensor 1~3 trigger point, set -1 if we're not using this
+	 * sensor to determine fan speed.
+	 */
+	int8_t off[TEMP_SENSOR_COUNT];
+	/* Fan rpm */
+	uint16_t rpm[FAN_CH_COUNT];
+};
+
+#define FAN_TABLE_ENTRY(nd)                     \
+	{                                       \
+		.on = DT_PROP(nd, temp_on),     \
+		.off = DT_PROP(nd, temp_off),   \
+		.rpm = DT_PROP(nd, rpm_target), \
+	},
+
+static const struct fan_step fan_step_table[] = { DT_FOREACH_CHILD(
+	DT_INST(0, cros_ec_fan_steps), FAN_TABLE_ENTRY) };
+
+int fan_table_to_rpm(int fan, int *temp)
+{
+	/* current fan level */
+	static int current_level;
+	/* previous sensor temperature */
+	static int prev_tmp[TEMP_SENSOR_COUNT];
+	int i;
+	/*
+	 * Compare the current and previous temperature, we have
+	 * the three paths :
+	 *  1. decreasing path. (check the release point)
+	 *  2. increasing path. (check the trigger point)
+	 *  3. invariant path. (return the current RPM)
+	 *
+	 * Yavilla thermal table V1-1
+	 * Increase path judgment: CPU || (5V && Charger)
+	 * Decrease path judgment: CPU && 5V && Charger
+	 */
+	if (temp[TEMP_CPU] < prev_tmp[TEMP_CPU] ||
+	    temp[TEMP_5V] < prev_tmp[TEMP_5V] ||
+	    temp[TEMP_CHARGER] < prev_tmp[TEMP_CHARGER]) {
+		for (i = current_level; i > 0; i--) {
+			if (temp[TEMP_CPU] < fan_step_table[i].off[TEMP_CPU] &&
+			    temp[TEMP_5V] < fan_step_table[i].off[TEMP_5V] &&
+			    temp[TEMP_CHARGER] <
+				    fan_step_table[i].off[TEMP_CHARGER]) {
+				current_level = i - 1;
+			} else
+				break;
+		}
+	} else if (temp[TEMP_CPU] > prev_tmp[TEMP_CPU] ||
+		   temp[TEMP_5V] > prev_tmp[TEMP_5V] ||
+		   temp[TEMP_CHARGER] > prev_tmp[TEMP_CHARGER]) {
+		for (i = current_level; i < ARRAY_SIZE(fan_step_table); i++) {
+			if (temp[TEMP_CPU] > fan_step_table[i].on[TEMP_CPU] ||
+			    (temp[TEMP_5V] > fan_step_table[i].on[TEMP_5V] &&
+			     temp[TEMP_CHARGER] >
+				     fan_step_table[i].on[TEMP_CHARGER])) {
+				current_level = i + 1;
+			} else
+				break;
+		}
+	}
+	if (current_level < 0)
+		current_level = 0;
+
+	if (current_level >= ARRAY_SIZE(fan_step_table))
+		current_level = ARRAY_SIZE(fan_step_table) - 1;
+
+	for (i = 0; i < TEMP_SENSOR_COUNT; ++i)
+		prev_tmp[i] = temp[i];
+
+	return fan_step_table[current_level].rpm[fan];
+}
+
+void board_override_fan_control(int fan, int *temp)
+{
+	/*
+	 * In common/fan.c pwm_fan_stop() will turn off fan
+	 * when chipset suspend or shutdown.
+	 */
+	if (ap_power_in_state(AP_POWER_STATE_ON)) {
+		fan_set_rpm_mode(fan, 1);
+		fan_set_rpm_target(fan, fan_table_to_rpm(fan, temp));
+	}
+}
diff --git a/zephyr/program/nissa/yavilla/src/usbc.c b/zephyr/program/nissa/yavilla/src/usbc.c
new file mode 100644
index 0000000000..3fca1b16df
--- /dev/null
+++ b/zephyr/program/nissa/yavilla/src/usbc.c
@@ -0,0 +1,351 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_state.h"
+#include "chipset.h"
+#include "driver/charger/sm5803.h"
+#include "driver/tcpm/it83xx_pd.h"
+#include "driver/tcpm/ps8xxx_public.h"
+#include "driver/tcpm/tcpci.h"
+#include "hooks.h"
+#include "system.h"
+#include "usb_mux.h"
+#include "watchdog.h"
+
+#include <zephyr/logging/log.h>
+
+#include <ap_power/ap_power.h>
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+/* Vconn control for integrated ITE TCPC */
+void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
+{
+	/* Vconn control is only for port 0 */
+	if (port)
+		return;
+
+	if (cc_pin == USBPD_CC_PIN_1)
+		gpio_pin_set_dt(
+			GPIO_DT_FROM_NODELABEL(gpio_en_usb_c0_cc1_vconn),
+			!!enabled);
+	else
+		gpio_pin_set_dt(
+			GPIO_DT_FROM_NODELABEL(gpio_en_usb_c0_cc2_vconn),
+			!!enabled);
+}
+
+__override bool pd_check_vbus_level(int port, enum vbus_level level)
+{
+	return sm5803_check_vbus_level(port, level);
+}
+
+/*
+ * Putting chargers into LPM when in suspend reduces power draw by about 8mW
+ * per charger, but also seems critical to correct operation in source mode:
+ * if chargers are not in LPM when a sink is first connected, VBUS sourcing
+ * works even if the partner is later removed (causing LPM entry) and
+ * reconnected (causing LPM exit). If in LPM initially, sourcing VBUS
+ * consistently causes the charger to report (apparently spurious) overcurrent
+ * failures.
+ *
+ * In short, this is important to making things work correctly but we don't
+ * understand why.
+ */
+static void board_chargers_suspend(struct ap_power_ev_callback *const cb,
+				   const struct ap_power_ev_data data)
+{
+	void (*fn)(int chgnum);
+
+	switch (data.event) {
+	case AP_POWER_SUSPEND:
+		fn = sm5803_enable_low_power_mode;
+		break;
+	case AP_POWER_RESUME:
+		fn = sm5803_disable_low_power_mode;
+		break;
+	default:
+		LOG_WRN("%s: power event %d is not recognized", __func__,
+			data.event);
+		return;
+	}
+
+	fn(CHARGER_PRIMARY);
+	if (board_get_charger_chip_count() > 1)
+		fn(CHARGER_SECONDARY);
+}
+
+static int board_chargers_suspend_init(void)
+{
+	static struct ap_power_ev_callback cb = {
+		.handler = board_chargers_suspend,
+		.events = AP_POWER_SUSPEND | AP_POWER_RESUME,
+	};
+	ap_power_ev_add_callback(&cb);
+	return 0;
+}
+SYS_INIT(board_chargers_suspend_init, APPLICATION, 0);
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count());
+	int i;
+	int old_port;
+	int rv;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	old_port = charge_manager_get_active_charge_port();
+	LOG_INF("Charge update: p%d -> p%d", old_port, port);
+
+	/* Check if port is sourcing VBUS. */
+	if (port != CHARGE_PORT_NONE && charger_is_sourcing_otg_power(port)) {
+		LOG_WRN("Skip enable p%d: already sourcing", port);
+		return EC_ERROR_INVAL;
+	}
+
+	/* Disable sinking on all ports except the desired one */
+	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+		if (i == port)
+			continue;
+
+		if (sm5803_vbus_sink_enable(i, 0))
+			/*
+			 * Do not early-return because this can fail during
+			 * power-on which would put us into a loop.
+			 */
+			LOG_WRN("p%d: sink path disable failed.", i);
+	}
+
+	/* Don't enable anything (stop here) if no ports were requested */
+	if ((port == CHARGE_PORT_NONE) || (old_port == port))
+		return EC_SUCCESS;
+
+	/*
+	 * Stop the charger IC from switching while changing ports.  Otherwise,
+	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
+	 */
+	if (old_port != CHARGE_PORT_NONE)
+		charger_discharge_on_ac(1);
+
+	/* Enable requested charge port. */
+	rv = sm5803_vbus_sink_enable(port, 1);
+	if (rv)
+		LOG_WRN("p%d: sink path enable failed: code %d", port, rv);
+
+	/* Allow the charger IC to begin/continue switching. */
+	charger_discharge_on_ac(0);
+
+	return rv;
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	/*
+	 * TCPC 0 is embedded in the EC and processes interrupts in the chip
+	 * code (it83xx/intc.c). This function only needs to poll port C1 if
+	 * present.
+	 */
+	uint16_t status = 0;
+	int regval;
+
+	/* Is the C1 port IRQ line asserted? */
+	if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_int_odl))) {
+		/*
+		 * C1 IRQ is shared between charger and TCPC; poll TCPC to see
+		 * if it asserted the IRQ.
+		 */
+		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
+			if (regval)
+				status = PD_STATUS_TCPC_ALERT_1;
+		}
+	}
+
+	return status;
+}
+
+void pd_power_supply_reset(int port)
+{
+	int prev_en;
+
+	if (port < 0 || port >= board_get_usb_pd_port_count())
+		return;
+
+	prev_en = charger_is_sourcing_otg_power(port);
+
+	/* Disable Vbus */
+	charger_enable_otg_power(port, 0);
+
+	/* Discharge Vbus if previously enabled */
+	if (prev_en)
+		sm5803_set_vbus_disch(port, 1);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	enum ec_error_list rv;
+
+	if (port < 0 || port > board_get_usb_pd_port_count()) {
+		LOG_WRN("Port C%d does not exist, cannot enable VBUS", port);
+		return EC_ERROR_INVAL;
+	}
+
+	/* Disable sinking */
+	rv = sm5803_vbus_sink_enable(port, 0);
+	if (rv) {
+		LOG_WRN("C%d failed to disable sinking: %d", port, rv);
+		return rv;
+	}
+
+	/* Disable Vbus discharge */
+	rv = sm5803_set_vbus_disch(port, 0);
+	if (rv) {
+		LOG_WRN("C%d failed to clear VBUS discharge: %d", port, rv);
+		return rv;
+	}
+
+	/* Provide Vbus */
+	rv = charger_enable_otg_power(port, 1);
+	if (rv) {
+		LOG_WRN("C%d failed to enable VBUS sourcing: %d", port, rv);
+		return rv;
+	}
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	int rv;
+	const int current = rp == TYPEC_RP_3A0 ? 3000 : 1500;
+
+	rv = charger_set_otg_current_voltage(port, current, 5000);
+	if (rv != EC_SUCCESS) {
+		LOG_WRN("Failed to set source ilimit on port %d to %d: %d",
+			port, current, rv);
+	}
+}
+
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
+{
+	/*
+	 * b:213937755: Yavilla C1 port is OCPC (One Charger IC Per Type-C)
+	 * architecture, The charging current is controlled by increasing Vsys.
+	 * However, the charger SM5803 is not limit current while Vsys
+	 * increasing, we can see the current overshoot to ~3.6A to cause
+	 * C1 port brownout with low power charger (5V). To avoid C1 port
+	 * brownout at low power charger connected. Limit charge current to 2A.
+	 */
+	if (charge_mv <= 5000 && port == 1)
+		charge_ma = MIN(charge_ma, 2000);
+	else
+		charge_ma = charge_ma * 96 / 100;
+
+	charge_set_input_current_limit(charge_ma, charge_mv);
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * Do nothing. The integrated TCPC for C0 lacks a dedicated reset
+	 * command, and C1 (if present) doesn't have a reset pin connected
+	 * to the EC.
+	 */
+}
+
+/* C0 interrupt can only be triggered by the charger */
+void usb_c0_interrupt(enum gpio_signal s)
+{
+	sm5803_interrupt(0);
+}
+
+/* C1 interrupt line shared by TCPC and charger */
+void usb_c1_interrupt(enum gpio_signal s)
+{
+	/* Charger is handled in board_process_pd_alert */
+	schedule_deferred_pd_interrupt(1);
+}
+
+/*
+ * Check state of IRQ lines at startup, ensuring an IRQ that happened before
+ * the EC started up won't get lost (leaving the IRQ line asserted and blocking
+ * any further interrupts on the port).
+ *
+ * Although the PD task will check for pending TCPC interrupts on startup,
+ * the charger sharing the IRQ will not be polled automatically.
+ */
+void board_handle_initial_typec_irq(void)
+{
+	if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl))) {
+		/* Only charger IRQ has to be checked on C0 interrupt */
+		sm5803_interrupt(0);
+	}
+
+	/*
+	 * C1 port IRQ already handled by board_process_pd_alert(), we don't
+	 * need check IRQ here at initial.
+	 */
+}
+/*
+ * This must run after sub-board detection (which happens in EC main()),
+ * but isn't depended on by anything else either.
+ */
+DECLARE_HOOK(HOOK_INIT, board_handle_initial_typec_irq, HOOK_PRIO_LAST);
+
+/*
+ * Handle charger interrupts in the PD task. Not doing so can lead to a priority
+ * inversion where we fail to respond to TCPC alerts quickly enough because we
+ * don't get another edge on a shared IRQ until the other interrupt is cleared
+ * (or the IRQ is polled again), which happens in lower-priority tasks: the
+ * high-priority type-C handler is thus blocked on the lower-priority one(s).
+ *
+ * To avoid that, we run charger interrupt synchronously alongside PD interrupts
+ * so they have the same priority.
+ */
+void board_process_pd_alert(int port)
+{
+	/*
+	 * Port 0 doesn't use an external TCPC, so its interrupts don't need
+	 * this special handling.
+	 */
+	if (port != 1)
+		return;
+
+	if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_int_odl))) {
+		sm5803_handle_interrupt(port);
+	}
+	/*
+	 * Immediately schedule another TCPC interrupt if it seems we haven't
+	 * cleared all pending interrupts.
+	 */
+	if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_int_odl)))
+		schedule_deferred_pd_interrupt(port);
+
+	/*
+	 * b:273208597: There are some peripheral display docks will
+	 * issue HPDs in the short time. TCPM must wake up pd_task
+	 * continually to service the events. They may cause the
+	 * watchdog to reset. This patch placates watchdog after
+	 * receiving dp_attention.
+	 */
+	watchdog_reload();
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	int chg_det = 0;
+
+	sm5803_get_chg_det(port, &chg_det);
+
+	return chg_det;
+}
diff --git a/zephyr/program/nissa/yavilla/yavilla_vif.xml b/zephyr/program/nissa/yavilla/yavilla_vif.xml
new file mode 100644
index 0000000000..0df6a844b7
--- /dev/null
+++ b/zephyr/program/nissa/yavilla/yavilla_vif.xml
@@ -0,0 +1,350 @@
+<?xml version="1.0" encoding="utf-8"?>
+<vif:VIF xmlns:opt="http://usb.org/VendorInfoFileOptionalContent.xsd" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:vif="http://usb.org/VendorInfoFile.xsd">
+  <vif:VIF_Specification>3.19</vif:VIF_Specification>
+  <vif:VIF_App>
+    <vif:Vendor>USB-IF</vif:Vendor>
+    <vif:Name>VIF Editor</vif:Name>
+    <vif:Version>3.2.4.0</vif:Version>
+  </vif:VIF_App>
+  <vif:Vendor_Name>Google</vif:Vendor_Name>
+  <vif:Model_Part_Number>Yavilla</vif:Model_Part_Number>
+  <vif:Product_Revision>1</vif:Product_Revision>
+  <vif:TID>0</vif:TID>
+  <vif:VIF_Product_Type value="0">Port Product</vif:VIF_Product_Type>
+  <vif:Certification_Type value="1">Reference Platform</vif:Certification_Type>
+  <vif:Product>
+    <!--Product Level Content:-->
+  </vif:Product>
+  <vif:Component>
+    <!--Component 0: Port 0-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Component-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Port_Label>0</vif:Port_Label>
+    <vif:Connector_Type value="2">Type-C®</vif:Connector_Type>
+    <vif:USB4_Supported value="false" />
+    <vif:USB_PD_Support value="true" />
+    <vif:PD_Port_Type value="4">DRP</vif:PD_Port_Type>
+    <vif:Type_C_State_Machine value="2">DRP</vif:Type_C_State_Machine>
+    <vif:Port_Battery_Powered value="true" />
+    <vif:BC_1_2_Support value="2">Charging Port</vif:BC_1_2_Support>
+    <vif:Captive_Cable value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;General PD-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Spec_Revision_Major value="3" />
+    <vif:PD_Spec_Revision_Minor value="1" />
+    <vif:PD_Spec_Version_Major value="1" />
+    <vif:PD_Spec_Version_Minor value="3" />
+    <vif:PD_Specification_Revision value="2">Revision 3</vif:PD_Specification_Revision>
+    <vif:SOP_Capable value="true" />
+    <vif:SOP_P_Capable value="true" />
+    <vif:SOP_PP_Capable value="true" />
+    <vif:SOP_P_Debug_Capable value="false" />
+    <vif:SOP_PP_Debug_Capable value="false" />
+    <vif:Manufacturer_Info_Supported_Port value="true" />
+    <vif:Manufacturer_Info_VID_Port value="6353">18D1</vif:Manufacturer_Info_VID_Port>
+    <vif:Manufacturer_Info_PID_Port value="20570">505A</vif:Manufacturer_Info_PID_Port>
+    <vif:Chunking_Implemented_SOP value="true" />
+    <vif:Unchunked_Extended_Messages_Supported value="false" />
+    <vif:Security_Msgs_Supported_SOP value="false" />
+    <vif:Unconstrained_Power value="false" />
+    <vif:Num_Fixed_Batteries value="1" />
+    <vif:Num_Swappable_Battery_Slots value="0" />
+    <vif:ID_Header_Connector_Type_SOP value="2">USB Type-C® Receptacle</vif:ID_Header_Connector_Type_SOP>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Capabilities-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:USB_Comms_Capable value="true" />
+    <vif:DR_Swap_To_DFP_Supported value="true" />
+    <vif:DR_Swap_To_UFP_Supported value="false" />
+    <vif:VCONN_Swap_To_On_Supported value="true" />
+    <vif:VCONN_Swap_To_Off_Supported value="true" />
+    <vif:Responds_To_Discov_SOP_UFP value="false" />
+    <vif:Responds_To_Discov_SOP_DFP value="true" />
+    <vif:Attempts_Discov_SOP value="true" />
+    <vif:Power_Interruption_Available value="0">No Interruption Possible</vif:Power_Interruption_Available>
+    <vif:Data_Reset_Supported value="false" />
+    <vif:Enter_USB_Supported value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;USB Type-C®-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Type_C_Can_Act_As_Host value="true" />
+    <vif:Type_C_Can_Act_As_Device value="false" />
+    <vif:Type_C_Implements_Try_SRC value="true" />
+    <vif:Type_C_Implements_Try_SNK value="false" />
+    <vif:Type_C_Supports_Audio_Accessory value="false" />
+    <vif:Type_C_Is_VCONN_Powered_Accessory value="false" />
+    <vif:Type_C_Is_Debug_Target_SRC value="true" />
+    <vif:Type_C_Is_Debug_Target_SNK value="true" />
+    <vif:RP_Value value="1">1.5A</vif:RP_Value>
+    <vif:Type_C_Port_On_Hub value="false" />
+    <vif:Type_C_Power_Source value="2">Both</vif:Type_C_Power_Source>
+    <vif:Type_C_Sources_VCONN value="true" />
+    <vif:Type_C_Is_Alt_Mode_Controller value="true" />
+    <vif:Type_C_Is_Alt_Mode_Adapter value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Product Power-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Product_Total_Source_Power_mW value="15000">15000 mW</vif:Product_Total_Source_Power_mW>
+    <vif:Port_Source_Power_Type value="0">Assured</vif:Port_Source_Power_Type>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;USB Host-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Host_Supports_USB_Data value="true" />
+    <vif:Host_Speed value="1">USB 3.2 Gen 1x1</vif:Host_Speed>
+    <vif:Host_Contains_Captive_Retimer value="false" />
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:Host_Is_Embedded value="false" />
+    <vif:Host_Suspend_Supported value="true" />
+    <vif:Is_DFP_On_Hub value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Battery Charging 1.2-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:BC_1_2_Charging_Port_Type value="1">CDP</vif:BC_1_2_Charging_Port_Type>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Source-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Power_As_Source value="15000">15000 mW</vif:PD_Power_As_Source>
+    <vif:EPR_Supported_As_Src value="false" />
+    <vif:USB_Suspend_May_Be_Cleared value="false" />
+    <vif:Sends_Pings value="false" />
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="0">FR_Swap not supported</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <vif:Master_Port value="false" />
+    <vif:Num_Src_PDOs value="1" />
+    <vif:PD_OC_Protection value="true" />
+    <vif:PD_OCP_Method value="0">Over-Current Response</vif:PD_OCP_Method>
+    <!--Bundle: SrcPdoList-->
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!--Source PDO 1-->
+        <vif:Src_PDO_Supply_Type value="0">Fixed</vif:Src_PDO_Supply_Type>
+        <vif:Src_PDO_Peak_Current value="0">100% IOC</vif:Src_PDO_Peak_Current>
+        <vif:Src_PDO_Voltage value="100">5000 mV</vif:Src_PDO_Voltage>
+        <vif:Src_PDO_Max_Current value="300">3000 mA</vif:Src_PDO_Max_Current>
+        <vif:Src_PD_OCP_OC_Debounce value="0">0 msec</vif:Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="300">3000 mA</vif:Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Sink-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Power_As_Sink value="45000">45000 mW</vif:PD_Power_As_Sink>
+    <vif:EPR_Supported_As_Snk value="false" />
+    <vif:No_USB_Suspend_May_Be_Set value="true" />
+    <vif:GiveBack_May_Be_Set value="false" />
+    <vif:Higher_Capability_Set value="false" />
+    <vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source value="0">FR_Swap not supported</vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source>
+    <vif:Num_Snk_PDOs value="3" />
+    <!--Bundle: SnkPdoList-->
+    <vif:SnkPdoList>
+      <vif:SnkPDO>
+        <!--Sink PDO 1-->
+        <vif:Snk_PDO_Supply_Type value="0">Fixed</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Voltage value="100">5000 mV</vif:Snk_PDO_Voltage>
+        <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>
+      </vif:SnkPDO>
+      <vif:SnkPDO>
+        <!--Sink PDO 2-->
+        <vif:Snk_PDO_Supply_Type value="1">Battery</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Op_Power value="60">15000 mW</vif:Snk_PDO_Op_Power>
+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>
+        <vif:Snk_PDO_Max_Voltage value="300">15000 mV</vif:Snk_PDO_Max_Voltage>
+      </vif:SnkPDO>
+      <vif:SnkPDO>
+        <!--Sink PDO 3-->
+        <vif:Snk_PDO_Supply_Type value="2">Variable</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>
+        <vif:Snk_PDO_Max_Voltage value="300">15000 mV</vif:Snk_PDO_Max_Voltage>
+        <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>
+      </vif:SnkPDO>
+    </vif:SnkPdoList>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Dual Role-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Accepts_PR_Swap_As_Src value="true" />
+    <vif:Accepts_PR_Swap_As_Snk value="true" />
+    <vif:Requests_PR_Swap_As_Src value="true" />
+    <vif:Requests_PR_Swap_As_Snk value="true" />
+    <vif:FR_Swap_Supported_As_Initial_Sink value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;SOP Discover ID-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:XID_SOP value="0" />
+    <vif:Data_Capable_As_USB_Host_SOP value="true" />
+    <vif:Data_Capable_As_USB_Device_SOP value="false" />
+    <vif:Product_Type_UFP_SOP value="0">Undefined</vif:Product_Type_UFP_SOP>
+    <vif:Product_Type_DFP_SOP value="2">PDUSB Host</vif:Product_Type_DFP_SOP>
+    <vif:DFP_VDO_Port_Number value="0" />
+    <vif:Modal_Operation_Supported_SOP value="false" />
+    <vif:USB_VID_SOP value="6353">18D1</vif:USB_VID_SOP>
+    <vif:PID_SOP value="20570">505A</vif:PID_SOP>
+    <vif:bcdDevice_SOP value="0">0000</vif:bcdDevice_SOP>
+  </vif:Component>
+  <vif:Component>
+    <!--Component 1: Port 1-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Component-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Port_Label>1</vif:Port_Label>
+    <vif:Connector_Type value="2">Type-C®</vif:Connector_Type>
+    <vif:USB4_Supported value="false" />
+    <vif:USB_PD_Support value="true" />
+    <vif:PD_Port_Type value="4">DRP</vif:PD_Port_Type>
+    <vif:Type_C_State_Machine value="2">DRP</vif:Type_C_State_Machine>
+    <vif:Port_Battery_Powered value="true" />
+    <vif:BC_1_2_Support value="2">Charging Port</vif:BC_1_2_Support>
+    <vif:Captive_Cable value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;General PD-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Spec_Revision_Major value="3" />
+    <vif:PD_Spec_Revision_Minor value="1" />
+    <vif:PD_Spec_Version_Major value="1" />
+    <vif:PD_Spec_Version_Minor value="3" />
+    <vif:PD_Specification_Revision value="2">Revision 3</vif:PD_Specification_Revision>
+    <vif:SOP_Capable value="true" />
+    <vif:SOP_P_Capable value="true" />
+    <vif:SOP_PP_Capable value="true" />
+    <vif:SOP_P_Debug_Capable value="false" />
+    <vif:SOP_PP_Debug_Capable value="false" />
+    <vif:Manufacturer_Info_Supported_Port value="true" />
+    <vif:Manufacturer_Info_VID_Port value="6353">18D1</vif:Manufacturer_Info_VID_Port>
+    <vif:Manufacturer_Info_PID_Port value="20570">505A</vif:Manufacturer_Info_PID_Port>
+    <vif:Chunking_Implemented_SOP value="true" />
+    <vif:Unchunked_Extended_Messages_Supported value="false" />
+    <vif:Security_Msgs_Supported_SOP value="false" />
+    <vif:Unconstrained_Power value="false" />
+    <vif:Num_Fixed_Batteries value="1" />
+    <vif:Num_Swappable_Battery_Slots value="0" />
+    <vif:ID_Header_Connector_Type_SOP value="2">USB Type-C® Receptacle</vif:ID_Header_Connector_Type_SOP>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Capabilities-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:USB_Comms_Capable value="true" />
+    <vif:DR_Swap_To_DFP_Supported value="true" />
+    <vif:DR_Swap_To_UFP_Supported value="false" />
+    <vif:VCONN_Swap_To_On_Supported value="true" />
+    <vif:VCONN_Swap_To_Off_Supported value="true" />
+    <vif:Responds_To_Discov_SOP_UFP value="false" />
+    <vif:Responds_To_Discov_SOP_DFP value="true" />
+    <vif:Attempts_Discov_SOP value="true" />
+    <vif:Power_Interruption_Available value="0">No Interruption Possible</vif:Power_Interruption_Available>
+    <vif:Data_Reset_Supported value="false" />
+    <vif:Enter_USB_Supported value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;USB Type-C®-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Type_C_Can_Act_As_Host value="true" />
+    <vif:Type_C_Can_Act_As_Device value="false" />
+    <vif:Type_C_Implements_Try_SRC value="true" />
+    <vif:Type_C_Implements_Try_SNK value="false" />
+    <vif:Type_C_Supports_Audio_Accessory value="false" />
+    <vif:Type_C_Is_VCONN_Powered_Accessory value="false" />
+    <vif:Type_C_Is_Debug_Target_SRC value="true" />
+    <vif:Type_C_Is_Debug_Target_SNK value="true" />
+    <vif:RP_Value value="1">1.5A</vif:RP_Value>
+    <vif:Type_C_Port_On_Hub value="false" />
+    <vif:Type_C_Power_Source value="2">Both</vif:Type_C_Power_Source>
+    <vif:Type_C_Sources_VCONN value="true" />
+    <vif:Type_C_Is_Alt_Mode_Controller value="true" />
+    <vif:Type_C_Is_Alt_Mode_Adapter value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Product Power-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Product_Total_Source_Power_mW value="15000">15000 mW</vif:Product_Total_Source_Power_mW>
+    <vif:Port_Source_Power_Type value="0">Assured</vif:Port_Source_Power_Type>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;USB Host-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Host_Supports_USB_Data value="true" />
+    <vif:Host_Speed value="1">USB 3.2 Gen 1x1</vif:Host_Speed>
+    <vif:Host_Contains_Captive_Retimer value="true" />
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:Host_Is_Embedded value="false" />
+    <vif:Host_Suspend_Supported value="true" />
+    <vif:Is_DFP_On_Hub value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Battery Charging 1.2-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:BC_1_2_Charging_Port_Type value="1">CDP</vif:BC_1_2_Charging_Port_Type>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Source-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Power_As_Source value="15000">15000 mW</vif:PD_Power_As_Source>
+    <vif:EPR_Supported_As_Src value="false" />
+    <vif:USB_Suspend_May_Be_Cleared value="false" />
+    <vif:Sends_Pings value="false" />
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="0">FR_Swap not supported</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <vif:Master_Port value="false" />
+    <vif:Num_Src_PDOs value="1" />
+    <vif:PD_OC_Protection value="true" />
+    <vif:PD_OCP_Method value="0">Over-Current Response</vif:PD_OCP_Method>
+    <!--Bundle: SrcPdoList-->
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!--Source PDO 1-->
+        <vif:Src_PDO_Supply_Type value="0">Fixed</vif:Src_PDO_Supply_Type>
+        <vif:Src_PDO_Peak_Current value="0">100% IOC</vif:Src_PDO_Peak_Current>
+        <vif:Src_PDO_Voltage value="100">5000 mV</vif:Src_PDO_Voltage>
+        <vif:Src_PDO_Max_Current value="300">3000 mA</vif:Src_PDO_Max_Current>
+        <vif:Src_PD_OCP_OC_Debounce value="0">0 msec</vif:Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="300">3000 mA</vif:Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Sink-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Power_As_Sink value="45000">45000 mW</vif:PD_Power_As_Sink>
+    <vif:EPR_Supported_As_Snk value="false" />
+    <vif:No_USB_Suspend_May_Be_Set value="true" />
+    <vif:GiveBack_May_Be_Set value="false" />
+    <vif:Higher_Capability_Set value="false" />
+    <vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source value="0">FR_Swap not supported</vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source>
+    <vif:Num_Snk_PDOs value="3" />
+    <!--Bundle: SnkPdoList-->
+    <vif:SnkPdoList>
+      <vif:SnkPDO>
+        <!--Sink PDO 1-->
+        <vif:Snk_PDO_Supply_Type value="0">Fixed</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Voltage value="100">5000 mV</vif:Snk_PDO_Voltage>
+        <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>
+      </vif:SnkPDO>
+      <vif:SnkPDO>
+        <!--Sink PDO 2-->
+        <vif:Snk_PDO_Supply_Type value="1">Battery</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Op_Power value="60">15000 mW</vif:Snk_PDO_Op_Power>
+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>
+        <vif:Snk_PDO_Max_Voltage value="300">15000 mV</vif:Snk_PDO_Max_Voltage>
+      </vif:SnkPDO>
+      <vif:SnkPDO>
+        <!--Sink PDO 3-->
+        <vif:Snk_PDO_Supply_Type value="2">Variable</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>
+        <vif:Snk_PDO_Max_Voltage value="300">15000 mV</vif:Snk_PDO_Max_Voltage>
+        <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>
+      </vif:SnkPDO>
+    </vif:SnkPdoList>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Dual Role-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Accepts_PR_Swap_As_Src value="true" />
+    <vif:Accepts_PR_Swap_As_Snk value="true" />
+    <vif:Requests_PR_Swap_As_Src value="true" />
+    <vif:Requests_PR_Swap_As_Snk value="true" />
+    <vif:FR_Swap_Supported_As_Initial_Sink value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;SOP Discover ID-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:XID_SOP value="0" />
+    <vif:Data_Capable_As_USB_Host_SOP value="true" />
+    <vif:Data_Capable_As_USB_Device_SOP value="false" />
+    <vif:Product_Type_UFP_SOP value="0">Undefined</vif:Product_Type_UFP_SOP>
+    <vif:Product_Type_DFP_SOP value="2">PDUSB Host</vif:Product_Type_DFP_SOP>
+    <vif:DFP_VDO_Port_Number value="1" />
+    <vif:Modal_Operation_Supported_SOP value="false" />
+    <vif:USB_VID_SOP value="6353">18D1</vif:USB_VID_SOP>
+    <vif:PID_SOP value="20570">505A</vif:PID_SOP>
+    <vif:bcdDevice_SOP value="0">0000</vif:bcdDevice_SOP>
+  </vif:Component>
+</vif:VIF>
diff --git a/zephyr/program/npcx_evb/npcx7/BUILD.py b/zephyr/program/npcx_evb/npcx7/BUILD.py
new file mode 100644
index 0000000000..baa6774595
--- /dev/null
+++ b/zephyr/program/npcx_evb/npcx7/BUILD.py
@@ -0,0 +1,11 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Define zmake projects for npcx7_evb."""
+
+register_npcx_project(
+    project_name="npcx7",
+    zephyr_board="npcx7_evb",
+    dts_overlays=["gpio.dts", "interrupts.dts", "fan.dts", "keyboard.dts"],
+)
diff --git a/zephyr/program/npcx_evb/npcx7/CMakeLists.txt b/zephyr/program/npcx_evb/npcx7/CMakeLists.txt
new file mode 100644
index 0000000000..64429d586e
--- /dev/null
+++ b/zephyr/program/npcx_evb/npcx7/CMakeLists.txt
@@ -0,0 +1,10 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(npcx7)
+
+zephyr_include_directories(include)
diff --git a/zephyr/program/npcx_evb/npcx7/fan.dts b/zephyr/program/npcx_evb/npcx7/fan.dts
new file mode 100644
index 0000000000..dc4debdcb9
--- /dev/null
+++ b/zephyr/program/npcx_evb/npcx7/fan.dts
@@ -0,0 +1,39 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	fans {
+		compatible = "cros-ec,fans";
+
+		fan_0 {
+			pwms = <&pwm0 0 PWM_KHZ(25) PWM_POLARITY_NORMAL>;
+			rpm_min = <1000>;
+			rpm_start = <1000>;
+			rpm_max = <5200>;
+			tach = <&tach1>;
+			pgood_gpio = <&gpio_pgood_fan>;
+		};
+	};
+};
+
+/* Tachometer for fan speed measurement */
+&tach1 {
+	status = "okay";
+	pinctrl-0 = <&ta1_1_in_gp40>;
+	pinctrl-names = "default";
+	port = <NPCX_TACH_PORT_A>; /* port-A is selected */
+	sample-clk = <NPCX_TACH_FREQ_LFCLK>; /* Use LFCLK as sampling clock */
+	pulses-per-round = <2>; /* number of pulses per round of encoder */
+};
+
+&pwm0_gpc3 {
+	drive-open-drain;
+};
+
+&pwm0 {
+	status = "okay";
+	pinctrl-0 = <&pwm0_gpc3>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/npcx_evb/npcx7/gpio.dts b/zephyr/program/npcx_evb/npcx7/gpio.dts
new file mode 100644
index 0000000000..d44927609d
--- /dev/null
+++ b/zephyr/program/npcx_evb/npcx7/gpio.dts
@@ -0,0 +1,68 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	aliases {
+		gpio-wp = &gpio_wp;
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		recovery_l {
+			gpios = <&gpio0 3 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_wp: wp_l {
+			gpios = <&gpio9 3 (GPIO_INPUT_PULL_UP |
+					   GPIO_ACTIVE_LOW)>;
+		};
+		gpio_ac_present: ac_present {
+			gpios = <&gpiod 2 GPIO_INPUT>;
+			enum-name = "GPIO_AC_PRESENT";
+		};
+		gpio_power_button_l: power_button_l {
+			gpios = <&gpio0 0 GPIO_INPUT>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		gpio_lid_open: lid_open {
+			gpios = <&gpio0 1 GPIO_INPUT>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+		entering_rw {
+			gpios = <&gpio3 6 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_ENTERING_RW";
+		};
+		gpio_ec_pch_wake_odl: pch_wake_l {
+			gpios = <&gpio5 0 GPIO_OUTPUT_HIGH>;
+		};
+		gpio_pgood_fan: pgood_fan {
+			gpios = <&gpioc 7 GPIO_INPUT_PULL_UP>;
+		};
+		spi_cs_l {
+			gpios = <&gpioa 5 GPIO_OUTPUT_HIGH>;
+		};
+		board_version1 {
+			gpios = <&gpio6 4 GPIO_INPUT>;
+			enum-name = "GPIO_BOARD_VERSION1";
+		};
+		board_version2 {
+			gpios = <&gpio6 5 GPIO_INPUT>;
+			enum-name = "GPIO_BOARD_VERSION2";
+		};
+		board_version3 {
+			gpios = <&gpio6 6 GPIO_INPUT>;
+			enum-name = "GPIO_BOARD_VERSION3";
+		};
+	};
+
+	hibernate-wake-pins {
+		compatible = "cros-ec,hibernate-wake-pins";
+		wakeup-irqs = <
+			&int_ac_present
+			&int_power_button
+			&int_lid_open
+		>;
+	};
+};
diff --git a/zephyr/program/npcx_evb/npcx7/interrupts.dts b/zephyr/program/npcx_evb/npcx7/interrupts.dts
new file mode 100644
index 0000000000..3e92428ef4
--- /dev/null
+++ b/zephyr/program/npcx_evb/npcx7/interrupts.dts
@@ -0,0 +1,26 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_ac_present: ac_present {
+			irq-pin = <&gpio_ac_present>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "extpower_interrupt";
+		};
+		int_lid_open: lid_open {
+			irq-pin = <&gpio_lid_open>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "lid_interrupt";
+		};
+		int_power_button: power_button {
+			irq-pin = <&gpio_power_button_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_button_interrupt";
+		};
+	};
+};
diff --git a/zephyr/program/npcx_evb/npcx7/keyboard.dts b/zephyr/program/npcx_evb/npcx7/keyboard.dts
new file mode 100644
index 0000000000..e7e35d1493
--- /dev/null
+++ b/zephyr/program/npcx_evb/npcx7/keyboard.dts
@@ -0,0 +1,42 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	cros-keyscan {
+		compatible = "cros-ec,keyscan";
+
+		output-settle = <40>;
+		debounce-down = <6000>;
+		scan-period = <1500>;
+		poll-timeout = <1000000>;
+
+		actual-key-mask = <
+			0x14	/* C0 */
+			0xff	/* C1 */
+			0xff	/* C2 */
+			0xff	/* C3 */
+			0xff	/* C4 */
+			0xf5	/* C5 */
+			0xff	/* C6 */
+			0xa4	/* C7 */
+			0xff	/* C8 */
+			0xf6	/* C9 */
+			0x55	/* C10 */
+			0xfa	/* C11 */
+			0xc8	/* C12 */
+			>;
+	};
+
+	kblight {
+		compatible = "cros-ec,kblight-pwm";
+		pwms = <&pwm2 0 PWM_KHZ(10) PWM_POLARITY_NORMAL>;
+	};
+};
+
+&pwm2 {
+	status = "okay";
+	pinctrl-0 = <&pwm2_gpc4>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/npcx_evb/npcx7/prj.conf b/zephyr/program/npcx_evb/npcx7/prj.conf
new file mode 100644
index 0000000000..f88fe735fa
--- /dev/null
+++ b/zephyr/program/npcx_evb/npcx7/prj.conf
@@ -0,0 +1,51 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_CROS_EC=y
+CONFIG_PLATFORM_EC=y
+CONFIG_PLATFORM_EC_BRINGUP=y
+CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y
+CONFIG_PLATFORM_EC_LID_SWITCH=y
+CONFIG_PLATFORM_EC_POWER_BUTTON=y
+
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
+CONFIG_PLATFORM_EC_SWITCH=n
+CONFIG_PLATFORM_EC_VBOOT_EFS2=n
+CONFIG_PLATFORM_EC_VSTORE=n
+
+# Board version is selected over GPIO board ID pins.
+CONFIG_PLATFORM_EC_BOARD_VERSION_GPIO=y
+
+# Console command
+CONFIG_PLATFORM_EC_CONSOLE_CMD_SCRATCHPAD=y
+
+CONFIG_TRACING=y
+CONFIG_TRACING_ISR=y
+CONFIG_TRACING_USER=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_IRQ=y
+
+# eSPI
+CONFIG_ESPI=y
+CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S3=y
+CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S4=y
+
+# Keyboard
+CONFIG_CROS_KB_RAW_NPCX_KSO_HIGH_DRIVE=y
+
+# RTC
+CONFIG_PLATFORM_EC_RTC=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_RTC=y
+
+# USB-C
+CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=n
+CONFIG_PLATFORM_EC_USB_PD_USB4=n
+
+# Zephyr feature
+CONFIG_ASSERT=y
+CONFIG_SHELL_MINIMAL=n
+
+# Avoid underflow info from tachometer
+CONFIG_SENSOR_LOG_LEVEL_ERR=y
+
+CONFIG_SYSCON=y
diff --git a/zephyr/program/npcx_evb/npcx9/BUILD.py b/zephyr/program/npcx_evb/npcx9/BUILD.py
new file mode 100644
index 0000000000..335f410d9b
--- /dev/null
+++ b/zephyr/program/npcx_evb/npcx9/BUILD.py
@@ -0,0 +1,16 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Define zmake projects for npcx9_evb."""
+
+register_npcx_project(
+    project_name="npcx9",
+    zephyr_board="npcx9_evb",
+    dts_overlays=[
+        "gpio.dts",
+        "interrupts.dts",
+        "fan.dts",
+        "keyboard.dts",
+    ],
+)
diff --git a/zephyr/program/npcx_evb/npcx9/CMakeLists.txt b/zephyr/program/npcx_evb/npcx9/CMakeLists.txt
new file mode 100644
index 0000000000..ef734c06f6
--- /dev/null
+++ b/zephyr/program/npcx_evb/npcx9/CMakeLists.txt
@@ -0,0 +1,10 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(npcx9)
+
+zephyr_include_directories(include)
diff --git a/zephyr/program/npcx_evb/npcx9/fan.dts b/zephyr/program/npcx_evb/npcx9/fan.dts
new file mode 100644
index 0000000000..dc4debdcb9
--- /dev/null
+++ b/zephyr/program/npcx_evb/npcx9/fan.dts
@@ -0,0 +1,39 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	fans {
+		compatible = "cros-ec,fans";
+
+		fan_0 {
+			pwms = <&pwm0 0 PWM_KHZ(25) PWM_POLARITY_NORMAL>;
+			rpm_min = <1000>;
+			rpm_start = <1000>;
+			rpm_max = <5200>;
+			tach = <&tach1>;
+			pgood_gpio = <&gpio_pgood_fan>;
+		};
+	};
+};
+
+/* Tachometer for fan speed measurement */
+&tach1 {
+	status = "okay";
+	pinctrl-0 = <&ta1_1_in_gp40>;
+	pinctrl-names = "default";
+	port = <NPCX_TACH_PORT_A>; /* port-A is selected */
+	sample-clk = <NPCX_TACH_FREQ_LFCLK>; /* Use LFCLK as sampling clock */
+	pulses-per-round = <2>; /* number of pulses per round of encoder */
+};
+
+&pwm0_gpc3 {
+	drive-open-drain;
+};
+
+&pwm0 {
+	status = "okay";
+	pinctrl-0 = <&pwm0_gpc3>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/npcx_evb/npcx9/gpio.dts b/zephyr/program/npcx_evb/npcx9/gpio.dts
new file mode 100644
index 0000000000..9a32112471
--- /dev/null
+++ b/zephyr/program/npcx_evb/npcx9/gpio.dts
@@ -0,0 +1,72 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	aliases {
+		gpio-wp = &gpio_wp;
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		recovery_l {
+			gpios = <&gpio0 3 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_wp: wp_l {
+			gpios = <&gpio9 3 (GPIO_INPUT_PULL_UP |
+					   GPIO_ACTIVE_LOW)>;
+		};
+		gpio_ac_present: ac_present {
+			gpios = <&gpiod 2 GPIO_INPUT>;
+			enum-name = "GPIO_AC_PRESENT";
+		};
+		gpio_power_button_l: power_button_l {
+			gpios = <&gpio0 0 GPIO_INPUT>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		gpio_lid_open: lid_open {
+			gpios = <&gpio0 1 GPIO_INPUT>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+		entering_rw {
+			gpios = <&gpio3 6 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_ENTERING_RW";
+		};
+		gpio_ec_pch_wake_odl: pch_wake_l {
+			gpios = <&gpio5 0 GPIO_OUTPUT_HIGH>;
+		};
+		gpio_pgood_fan: pgood_fan {
+			gpios = <&gpioc 7 GPIO_INPUT_PULL_UP>;
+		};
+		spi_cs_l {
+			gpios = <&gpioa 5 GPIO_OUTPUT_HIGH>;
+		};
+		board_version1 {
+			gpios = <&gpio6 4 GPIO_INPUT>;
+			enum-name = "GPIO_BOARD_VERSION1";
+		};
+		board_version2 {
+			gpios = <&gpio6 5 GPIO_INPUT>;
+			enum-name = "GPIO_BOARD_VERSION2";
+		};
+		board_version3 {
+			gpios = <&gpio6 6 GPIO_INPUT>;
+			enum-name = "GPIO_BOARD_VERSION3";
+		};
+	};
+};
+
+/* A falling edge detection type for PSL_IN2 */
+&psl_in2_gp00 {
+	psl-in-mode = "edge";
+	psl-in-pol = "low-falling";
+};
+
+/* Power domain device controlled by PSL (Power Switch Logic) IO pads */
+&power_ctrl_psl {
+	status = "okay";
+	pinctrl-names = "sleep";
+	pinctrl-0 = <&psl_in2_gp00>;
+};
diff --git a/zephyr/program/npcx_evb/npcx9/interrupts.dts b/zephyr/program/npcx_evb/npcx9/interrupts.dts
new file mode 100644
index 0000000000..3e92428ef4
--- /dev/null
+++ b/zephyr/program/npcx_evb/npcx9/interrupts.dts
@@ -0,0 +1,26 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_ac_present: ac_present {
+			irq-pin = <&gpio_ac_present>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "extpower_interrupt";
+		};
+		int_lid_open: lid_open {
+			irq-pin = <&gpio_lid_open>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "lid_interrupt";
+		};
+		int_power_button: power_button {
+			irq-pin = <&gpio_power_button_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_button_interrupt";
+		};
+	};
+};
diff --git a/zephyr/program/npcx_evb/npcx9/keyboard.dts b/zephyr/program/npcx_evb/npcx9/keyboard.dts
new file mode 100644
index 0000000000..e7e35d1493
--- /dev/null
+++ b/zephyr/program/npcx_evb/npcx9/keyboard.dts
@@ -0,0 +1,42 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	cros-keyscan {
+		compatible = "cros-ec,keyscan";
+
+		output-settle = <40>;
+		debounce-down = <6000>;
+		scan-period = <1500>;
+		poll-timeout = <1000000>;
+
+		actual-key-mask = <
+			0x14	/* C0 */
+			0xff	/* C1 */
+			0xff	/* C2 */
+			0xff	/* C3 */
+			0xff	/* C4 */
+			0xf5	/* C5 */
+			0xff	/* C6 */
+			0xa4	/* C7 */
+			0xff	/* C8 */
+			0xf6	/* C9 */
+			0x55	/* C10 */
+			0xfa	/* C11 */
+			0xc8	/* C12 */
+			>;
+	};
+
+	kblight {
+		compatible = "cros-ec,kblight-pwm";
+		pwms = <&pwm2 0 PWM_KHZ(10) PWM_POLARITY_NORMAL>;
+	};
+};
+
+&pwm2 {
+	status = "okay";
+	pinctrl-0 = <&pwm2_gpc4>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/npcx_evb/npcx9/prj.conf b/zephyr/program/npcx_evb/npcx9/prj.conf
new file mode 100644
index 0000000000..6656212d2a
--- /dev/null
+++ b/zephyr/program/npcx_evb/npcx9/prj.conf
@@ -0,0 +1,55 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_CROS_EC=y
+CONFIG_PLATFORM_EC=y
+CONFIG_PLATFORM_EC_BRINGUP=y
+CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y
+CONFIG_PLATFORM_EC_LID_SWITCH=y
+CONFIG_PLATFORM_EC_POWER_BUTTON=y
+
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
+CONFIG_PLATFORM_EC_SWITCH=n
+CONFIG_PLATFORM_EC_VBOOT_EFS2=n
+CONFIG_PLATFORM_EC_VSTORE=n
+
+# Workaround npcx9 A1 chip's bug for download_from_flash API in th booter.
+# This can be removed when A2 chip is available.
+CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API=y
+
+# Board version is selected over GPIO board ID pins.
+CONFIG_PLATFORM_EC_BOARD_VERSION_GPIO=y
+
+# Console command
+CONFIG_PLATFORM_EC_CONSOLE_CMD_SCRATCHPAD=y
+
+CONFIG_TRACING=y
+CONFIG_TRACING_ISR=y
+CONFIG_TRACING_USER=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_IRQ=y
+
+# eSPI
+CONFIG_ESPI=y
+CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S3=y
+CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S4=y
+
+# Keyboard
+CONFIG_CROS_KB_RAW_NPCX_KSO_HIGH_DRIVE=y
+
+# RTC
+CONFIG_PLATFORM_EC_RTC=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_RTC=y
+
+# USB-C
+CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=n
+CONFIG_PLATFORM_EC_USB_PD_USB4=n
+
+# Zephyr feature
+CONFIG_ASSERT=y
+CONFIG_SHELL_MINIMAL=n
+
+# Avoid underflow info from tachometer
+CONFIG_SENSOR_LOG_LEVEL_ERR=y
+
+CONFIG_SYSCON=y
diff --git a/zephyr/program/ovis/BUILD.py b/zephyr/program/ovis/BUILD.py
new file mode 100644
index 0000000000..71dd202460
--- /dev/null
+++ b/zephyr/program/ovis/BUILD.py
@@ -0,0 +1,34 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Define zmake projects for Ovis."""
+
+
+def register_ovis_project(
+    project_name,
+    kconfig_files=None,
+):
+    """Register a variant of Ovis."""
+    if kconfig_files is None:
+        kconfig_files = [
+            # Common to all projects.
+            here / "program.conf",
+            # Project-specific KConfig customization.
+            here / project_name / "project.conf",
+        ]
+
+    register_npcx_project(
+        project_name=project_name,
+        zephyr_board="npcx9m3f",
+        dts_overlays=[
+            here / project_name / "project.overlay",
+        ],
+        kconfig_files=kconfig_files,
+        inherited_from=["ovis"],
+    )
+
+
+register_ovis_project(
+    project_name="ovis",
+)
diff --git a/zephyr/program/ovis/CMakeLists.txt b/zephyr/program/ovis/CMakeLists.txt
new file mode 100644
index 0000000000..cf9d1b559d
--- /dev/null
+++ b/zephyr/program/ovis/CMakeLists.txt
@@ -0,0 +1,16 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.20.5)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+
+zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}/include")
+zephyr_library_sources_ifdef(CONFIG_AP_PWRSEQ "src/board_power.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/usbc_config.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/usb_pd_policy.c")
+
+if(DEFINED CONFIG_BOARD_OVIS)
+	project(ovis)
+	add_subdirectory(ovis)
+endif()
diff --git a/zephyr/program/ovis/Kconfig b/zephyr/program/ovis/Kconfig
new file mode 100644
index 0000000000..7611d8d291
--- /dev/null
+++ b/zephyr/program/ovis/Kconfig
@@ -0,0 +1,15 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config BOARD_OVIS
+	bool "Google Ovis Baseboard"
+	help
+	  Build Google Ovis reference board.  The board uses Nuvoton
+	  NPCX9 chip as the EC.
+
+module = OVIS
+module-str = Ovis board-specific code
+source "subsys/logging/Kconfig.template.log_config"
+
+source "Kconfig.zephyr"
diff --git a/zephyr/program/ovis/fan.dtsi b/zephyr/program/ovis/fan.dtsi
new file mode 100644
index 0000000000..28868d1c77
--- /dev/null
+++ b/zephyr/program/ovis/fan.dtsi
@@ -0,0 +1,39 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	fans {
+		compatible = "cros-ec,fans";
+
+		fan_0 {
+			pwms = <&pwm5 0 PWM_KHZ(1) PWM_POLARITY_NORMAL>;
+			rpm_min = <2200>;
+			rpm_start = <2200>;
+			rpm_max = <4200>;
+			tach = <&tach1>;
+			enable_gpio = <&gpio_en_pp5000_fan>;
+		};
+	};
+};
+
+/* Tachemeter for fan speed measurement */
+&tach1 {
+	status = "okay";
+	pinctrl-0 = <&ta1_1_in_gp40>;
+	pinctrl-names = "default";
+	port = <NPCX_TACH_PORT_A>; /* port-A is selected */
+	sample-clk = <NPCX_TACH_FREQ_LFCLK>; /* Use LFCLK as sampling clock */
+	pulses-per-round = <2>; /* number of pulses per round of encoder */
+};
+
+&pwm5_gpb7 {
+	drive-open-drain;
+};
+
+&pwm5 {
+	status = "okay";
+	pinctrl-0 = <&pwm5_gpb7>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/ovis/generated.dtsi b/zephyr/program/ovis/generated.dtsi
new file mode 100644
index 0000000000..ee1f028949
--- /dev/null
+++ b/zephyr/program/ovis/generated.dtsi
@@ -0,0 +1,393 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ */
+
+/ {
+
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		adc_temp_sensor_1: temp_sensor_1 {
+			enum-name = "ADC_TEMP_SENSOR_1_DDR_SOC";
+			io-channels = <&adc0 0>;
+		};
+		adc_temp_sensor_2: temp_sensor_2 {
+			enum-name = "ADC_TEMP_SENSOR_2_AMBIENT";
+			io-channels = <&adc0 1>;
+		};
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		gpio_ccd_mode_odl: ccd_mode_odl {
+			gpios = <&gpiof 2 GPIO_INPUT>;
+			enum-name = "GPIO_CCD_MODE_ODL";
+		};
+		gpio_cpu_c10_gate_l: cpu_c10_gate_l {
+			gpios = <&gpioa 7 GPIO_INPUT>;
+		};
+		gpio_ec_cbi_wp: ec_cbi_wp {
+			gpios = <&gpioe 5 GPIO_OUTPUT>;
+		};
+		gpio_ec_gsc_packet_mode: ec_gsc_packet_mode {
+			gpios = <&gpio7 5 GPIO_OUTPUT>;
+			enum-name = "GPIO_PACKET_MODE_EN";
+		};
+		gpio_ec_prochot_in_l: ec_prochot_in_l {
+			gpios = <&gpio5 6 GPIO_INPUT>;
+		};
+		gpio_ec_rst_r_odl: ec_rst_r_odl {
+			gpios = <&gpio7 7 GPIO_INPUT>;
+		};
+		gpio_ec_soc_int_odl: ec_soc_int_odl {
+			gpios = <&gpio7 0 GPIO_ODR_LOW>;
+			enum-name = "GPIO_EC_INT_L";
+		};
+		gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl {
+			gpios = <&gpioc 1 GPIO_ODR_LOW>;
+			enum-name = "GPIO_PCH_PWRBTN_L";
+		};
+		gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l {
+			gpios = <&gpioa 6 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_rtcrst: ec_soc_rtcrst {
+			gpios = <&gpio7 6 GPIO_ODR_HIGH>;
+		};
+		gpio_ec_soc_wake_r_odl: ec_soc_wake_r_odl {
+			gpios = <&gpioc 0 GPIO_ODR_LOW>;
+		};
+		gpio_ec_spare_gpio01: ec_spare_gpio01 {
+			gpios = <&gpio0 1 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpio14: ec_spare_gpio14 {
+			gpios = <&gpio1 4 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpio15: ec_spare_gpio15 {
+			gpios = <&gpio1 5 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpio16: ec_spare_gpio16 {
+			gpios = <&gpio1 6 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpio33: ec_spare_gpio33 {
+			gpios = <&gpio3 3 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpio50: ec_spare_gpio50 {
+			gpios = <&gpio5 0 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpio63: ec_spare_gpio63 {
+			gpios = <&gpio6 3 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpio66: ec_spare_gpio66 {
+			gpios = <&gpio6 6 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpio73: ec_spare_gpio73 {
+			gpios = <&gpio7 3 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpio80: ec_spare_gpio80 {
+			gpios = <&gpio8 0 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpio81: ec_spare_gpio81 {
+			gpios = <&gpio8 1 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpio83: ec_spare_gpio83 {
+			gpios = <&gpio8 3 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpio93: ec_spare_gpio93 {
+			gpios = <&gpio9 3 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpio94: ec_spare_gpio94 {
+			gpios = <&gpio9 4 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpio95: ec_spare_gpio95 {
+			gpios = <&gpio9 5 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpioa1: ec_spare_gpioa1 {
+			gpios = <&gpioa 1 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpioa2: ec_spare_gpioa2 {
+			gpios = <&gpioa 2 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpioa4: ec_spare_gpioa4 {
+			gpios = <&gpioa 4 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpiob1: ec_spare_gpiob1 {
+			gpios = <&gpiob 1 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpiob4: ec_spare_gpiob4 {
+			gpios = <&gpiob 4 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpiob5: ec_spare_gpiob5 {
+			gpios = <&gpiob 5 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpioc2: ec_spare_gpioc2 {
+			gpios = <&gpioc 2 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpioc7: ec_spare_gpioc7 {
+			gpios = <&gpioc 7 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpiod2: ec_spare_gpiod2 {
+			gpios = <&gpiod 2 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpioe1: ec_spare_gpioe1 {
+			gpios = <&gpioe 1 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpioe3: ec_spare_gpioe3 {
+			gpios = <&gpioe 3 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpioe4: ec_spare_gpioe4 {
+			gpios = <&gpioe 4 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpiof0: ec_spare_gpiof0 {
+			gpios = <&gpiof 0 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpiof3: ec_spare_gpiof3 {
+			gpios = <&gpiof 3 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpo12: ec_spare_gpo12 {
+			gpios = <&gpio1 2 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpo13: ec_spare_gpo13 {
+			gpios = <&gpio1 3 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpo32: ec_spare_gpo32 {
+			gpios = <&gpio3 2 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpo35: ec_spare_gpo35 {
+			gpios = <&gpio3 5 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpo86: ec_spare_gpo86 {
+			gpios = <&gpio8 6 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_psl_gpo: ec_spare_psl_gpo {
+			gpios = <&gpiod 7 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_psl_in_3: ec_spare_psl_in_3 {
+			gpios = <&gpio0 2 GPIO_OUTPUT>;
+		};
+		gpio_en_pp5000_fan: en_pp5000_fan {
+			gpios = <&gpio6 1 GPIO_OUTPUT_LOW>;
+		};
+		gpio_en_s5_rails: en_s5_rails {
+			gpios = <&gpiob 6 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_TEMP_SENSOR_POWER";
+		};
+		gpio_en_z1_rails: en_z1_rails {
+			gpios = <&gpio8 5 GPIO_OUTPUT>;
+		};
+		gpio_en_usb_a_vbus: en_usb_a_vbus {
+			gpios = <&gpio8 2 GPIO_OUTPUT>;
+		};
+		gpio_gsc_ec_rec_btn_odl:  gsc_ec_rec_btn_odl {
+			gpios = <&gpio2 2 GPIO_INPUT>;
+		};
+		gpio_gsc_flash_wp_odl: gsc_flash_wp_odl {
+			gpios = <&gpio6 0 GPIO_ODR_HIGH>;
+		};
+		gpio_imvp92_vrrdy_od: imvp92_vrrdy_od {
+			gpios = <&gpio4 3 GPIO_INPUT>;
+		};
+		gpio_led_1_l: led_1_l {
+			gpios = <&gpioc 4 GPIO_OUTPUT>;
+		};
+		gpio_led_2_l: led_2_l {
+			gpios = <&gpioc 3 GPIO_OUTPUT>;
+		};
+		gpio_mech_pwr_btn_odl: mech_pwr_btn_odl {
+			gpios = <&gpio0 0 GPIO_INPUT>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		gpio_pg_mem_vdd: pg_mem_vdd {
+			gpios = <&gpiod 3 GPIO_INPUT>;
+		};
+		gpio_pg_pp1250_soc: pg_pp1250_soc {
+			gpios = <&gpio7 4 GPIO_INPUT>;
+		};
+		gpio_seq_ec_all_sys_pg_od: seq_ec_all_sys_pg_od {
+			gpios = <&gpiof 4 GPIO_INPUT>;
+		};
+		gpio_seq_ec_rsmrst_odl: seq_ec_rsmrst_odl {
+			gpios = <&gpioe 2 GPIO_INPUT>;
+		};
+		gpio_slp_s3_ls_l: slp_s3_ls_l {
+			gpios = <&gpio4 1 GPIO_INPUT>;
+		};
+		gpio_sns_ppvar_pwr_in: sns_ppvar_pwr_in {
+			gpios = <&gpio4 2 GPIO_INPUT>;
+			enum-name = "GPIO_AC_PRESENT";
+		};
+		gpio_soc_pwrok: soc_pwrok {
+			gpios = <&gpioa 5 GPIO_OUTPUT>;
+		};
+		gpio_sochot_odl: sochot_odl {
+			gpios = <&gpio9 6 GPIO_INPUT>;
+		};
+		gpio_sys_pwrok: sys_pwrok {
+			gpios = <&gpiob 0 GPIO_OUTPUT>;
+		};
+		gpio_sys_rst_odl: sys_rst_odl {
+			gpios = <&gpioc 5 GPIO_INPUT>;
+		};
+		gpio_sys_slp_s0ix_l: sys_slp_s0ix_l {
+			gpios = <&gpiod 5 GPIO_INPUT>;
+		};
+		gpio_usb_a0_low_pwr_l: usb_a0_low_pwr_l {
+			gpios = <&gpio1 7 GPIO_OUTPUT>;
+		};
+		gpio_usb_a0_oc_odl: usb_a0_oc_odl {
+			gpios = <&gpio2 7 GPIO_INPUT>;
+		};
+		gpio_usb_a0_status_odl: usb_a0_status_odl {
+			gpios = <&gpio2 3 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_usb_a1_low_pwr_l: usb_a1_low_pwr_l {
+			gpios = <&gpio2 0 GPIO_OUTPUT>;
+		};
+		gpio_usb_a1_oc_odl: usb_a1_oc_odl {
+			gpios = <&gpio3 0 GPIO_INPUT>;
+		};
+		gpio_usb_a1_status_odl: usb_a1_status_odl {
+			gpios = <&gpio2 4 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_usb_a2_low_pwr_l: usb_a2_low_pwr_l {
+			gpios = <&gpio2 1 GPIO_OUTPUT>;
+		};
+		gpio_usb_a2_oc_odl: usb_a2_oc_odl {
+			gpios = <&gpio3 1 GPIO_INPUT>;
+		};
+		gpio_usb_a2_status_odl: usb_a2_status_odl {
+			gpios = <&gpio2 5 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_usb_a3_low_pwr_l: usb_a3_low_pwr_l {
+			gpios = <&gpio6 7 GPIO_OUTPUT>;
+		};
+		gpio_usb_a3_oc_odl: usb_a3_oc_odl {
+			gpios = <&gpiof 1 GPIO_INPUT>;
+		};
+		gpio_usb_a3_status_odl: usb_a3_status_odl {
+			gpios = <&gpio2 6 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_usb_c_oc_odl: usb_c_oc_odl {
+			gpios = <&gpioa 3 GPIO_INPUT>;
+		};
+		gpio_usb_c0_frs_en: usb_c0_frs_en {
+			gpios = <&gpio3 6 GPIO_OUTPUT>;
+		};
+		gpio_usb_c0_ppc_int_odl: usb_c0_ppc_int_odl {
+			gpios = <&gpio6 2 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C0_PPC_INT_ODL";
+		};
+		gpio_usb_c0_rt_3p3_sx_en: usb_c0_rt_3p3_sx_en {
+			gpios = <&gpio0 3 GPIO_ODR_LOW>;
+		};
+		gpio_usb_c0_rt_int_odl: usb_c0_rt_int_odl {
+			gpios = <&gpioa 0 GPIO_INPUT>;
+		};
+		gpio_usb_c0_rt_rst_l: usb_c0_rt_rst_l {
+			gpios = <&gpio1 0 GPIO_OUTPUT>;
+		};
+		gpio_usb_c0_tcpc_int_odl: usb_c0_tcpc_int_odl {
+			gpios = <&gpioe 0 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_USB_C0_TCPC_INT_ODL";
+		};
+
+		gpio_usb_c1_frs_en: usb_c1_frs_en {
+			gpios = <&gpio0 6 GPIO_OUTPUT>;
+		};
+		gpio_usb_c1_ppc_int_odl: usb_c1_ppc_int_odl {
+			gpios = <&gpiof 5 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C1_PPC_INT_ODL";
+		};
+		gpio_usb_c1_rt_3p3_sx_en: usb_c1_rt_3p3_sx_en {
+			gpios = <&gpio0 4 GPIO_ODR_LOW>;
+		};
+		gpio_usb_c1_rt_int_odl: usb_c1_rt_int_odl {
+			gpios = <&gpio7 2 GPIO_INPUT>;
+		};
+		gpio_usb_c1_rt_rst_l: usb_c1_rt_rst_l {
+			gpios = <&gpio3 7 GPIO_OUTPUT>;
+		};
+		gpio_usb_c1_tcpc_int_odl: usb_c1_tcpc_int_odl {
+			gpios = <&gpio3 4 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_USB_C1_TCPC_INT_ODL";
+		};
+		gpio_usb_c2_frs_en: usb_c2_frs_en {
+			gpios = <&gpio0 7 GPIO_OUTPUT>;
+		};
+		gpio_usb_c2_ppc_int_odl: usb_c2_ppc_int_odl {
+			gpios = <&gpioc 6 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C2_PPC_INT_ODL";
+		};
+		gpio_usb_c2_rt_3p3_sx_en: usb_c2_rt_3p3_sx_en {
+			gpios = <&gpio0 5 GPIO_ODR_LOW>;
+		};
+		gpio_usb_c2_rt_int_odl: usb_c2_rt_int_odl {
+			gpios = <&gpio9 7 GPIO_INPUT>;
+		};
+		gpio_usb_c2_rt_rst_l: usb_c2_rt_rst_l {
+			gpios = <&gpio1 1 GPIO_OUTPUT>;
+		};
+		gpio_usb_c2_tcpc_int_odl: usb_c2_tcpc_int_odl {
+			gpios = <&gpiod 4 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 {
+			i2c-port = <&i2c1_0>;
+			enum-names = "I2C_USB_C0";
+		};
+		i2c_ec_i2c_usb_c1: ec_i2c_usb_c1 {
+			i2c-port = <&i2c2_0>;
+			enum-names = "I2C_USB_C1";
+		};
+		i2c_ec_i2c_usb_c2: ec_i2c_usb_c2 {
+			i2c-port = <&i2c3_0>;
+			enum-names = "I2C_USB_C2";
+		};
+		i2c_ec_i2c_misc: ec_i2c_misc {
+			i2c-port = <&i2c7_0>;
+			enum-names = "I2C_PORT_EEPROM";
+		};
+	};
+};
+
+&adc0 {
+	status = "okay";
+};
+
+&i2c1_0 {
+	status = "okay";
+};
+
+&i2c2_0 {
+	status = "okay";
+};
+
+&i2c3_0 {
+	status = "okay";
+};
+
+&i2c7_0 {
+	status = "okay";
+};
+
+&i2c_ctrl1 {
+	status = "okay";
+};
+
+&i2c_ctrl2 {
+	status = "okay";
+};
+
+&i2c_ctrl3 {
+	status = "okay";
+};
+
+&i2c_ctrl7 {
+	status = "okay";
+};
diff --git a/zephyr/program/ovis/gpio.csv b/zephyr/program/ovis/gpio.csv
new file mode 100644
index 0000000000..26f09181ee
--- /dev/null
+++ b/zephyr/program/ovis/gpio.csv
@@ -0,0 +1,125 @@
+Signal Name,Pin Number,Type,Enum
+ESPI_SOC_IO0,H1,OTHER,
+ESPI_SOC_IO1,J1,OTHER,
+ESPI_SOC_IO2,K1,OTHER,
+ESPI_SOC_IO3,L1,OTHER,
+ESPI_SOC_CS0_L,L2,OTHER,
+ESPI_SOC_RESET_L,K3,OTHER,
+ESPI_SOC_CLK,M1,OTHER,
+ESPI_SOC_ALERT_L_R,L3,OTHER,
+USB_C1_BC12_INT_ODL,G10,INPUT,GPIO_USB_C1_BC12_INT_ODL
+EC_IMU_INT_R_L,M2,INPUT_PU,
+EC_VOLDN_BTN_ODL,E11,INPUT_PU,GPIO_VOLUME_DOWN_L
+TABLET_MODE_L,M12,INPUT_PU,GPIO_TABLET_MODE_L
+SOCHOT_ODL,G12,INPUT,
+EC_VOLUP_BTN_ODL,L10,INPUT_PU,GPIO_VOLUME_UP_L
+USB_C0_RT_INT_ODL,G11,INPUT,
+EC_WP_L,L12,INPUT_L,
+EC_BATT_PRES_ODL,K12,INPUT,GPIO_BATT_PRES_ODL
+SOC_PWROK,K11,OUTPUT,
+EC_SOC_RSMRST_L,F11,OUTPUT,
+CPU_C10_GATE_L,J11,INPUT,
+SYS_PWROK,L11,OUTPUT,
+EC_SPARE_GPIO94,M11,OUTPUT,
+EC_SPARE_GPIOA2,F12,OUTPUT,
+EC_SPARE_GPIOA4,H11,OUTPUT,
+EC_ACCEL_INT_R_L,M7,INPUT,
+TEMP_SENSOR_2,E3,ADC,ADC_TEMP_SENSOR_2_AMBIENT
+TEMP_SENSOR_1,F2,ADC,ADC_TEMP_SENSOR_1_DDR_SOC
+TEMP_SENSOR_4,F3,ADC,ADC_TEMP_SENSOR_4_WWAN
+TEMP_SENSOR_3,G3,ADC,ADC_TEMP_SENSOR_3_CHARGER
+SLP_S3_LS_L,C2,INPUT,
+IMVP92_VRRDY_OD,E2,INPUT,
+EC_PROCHOT_IN_L,D2,INPUT,
+EC_SPARE_GPIO42,D3,OUTPUT,
+USB_C0_RT_3P3_SX_EN,D9,OUTPUT_ODL,
+USB_C1_RST_ODL,C1,OUTPUT_ODL,
+EN_PP5000_FAN,K4,OUTPUT,
+EC_PROCHOT_ODL,J2,OUTPUT_ODR,
+USB_C0_TCPC_RST_ODL,J3,OUTPUT_ODR,
+EC_SOC_INT_ODL,J4,OUTPUT_ODL,GPIO_EC_INT_L
+USB_C1_RT_RST_R_ODL,H5,OUTPUT_ODR,
+EC_GSC_PACKET_MODE,J6,OUTPUT,GPIO_PACKET_MODE_EN
+EC_SOC_RTCRST,J5,OUTPUT_ODR,
+USB_C1_FRS_EN,D7,OUTPUT_ODR,
+EN_S5_RAILS,L9,OUTPUT_ODR,GPIO_TEMP_SENSOR_POWER
+EC_SOC_WAKE_R_ODL,H8,OUTPUT_ODL,
+EC_SOC_PWR_BTN_ODL,H9,OUTPUT_ODL,GPIO_PCH_PWRBTN_L
+SYS_RST_ODL,H7,INPUT,
+EC_EDP_BL_EN,E10,OUTPUT,GPIO_ENABLE_BACKLIGHT
+SYS_SLP_S0IX_3V3_L,A10,INPUT,
+SEQ_EC_RSMRST_ODL,A11,INPUT,
+CCD_MODE_ODL,A12,INPUT,GPIO_CCD_MODE_ODL
+EC_KB_BL_EN_L,J9,OUTPUT,
+EC_SHDF_ESPI_L,H3,OTHER,
+USB_C1_TCPC_INT_ODL,B2,INPUT_L,GPIO_USB_C1_TCPC_INT_ODL
+EC_FAN_TACH,E5,TACH,
+USB_C0_PPC_INT_ODL,H2,INPUT,GPIO_USB_C0_PPC_INT_ODL
+USB_C1_RT_INT_ODL,M4,INPUT_PU,
+USB_C0_BC12_INT_ODL,D10,INPUT,GPIO_USB_C0_BC12_INT_ODL
+EC_ALS_RGB_INT_R_L,A9,INPUT_PU,
+USB_C0_TCPC_INT_ODL,F4,INPUT_L,GPIO_USB_C0_TCPC_INT_ODL
+SEQ_EC_ALL_SYS_PG_OD,E9,INPUT,
+USB_C1_PPC_INT_ODL,E8,INPUT,GPIO_USB_C1_PPC_INT_ODL
+EC_I2C_SENSOR_SDA_R,B12,I2C_DATA,
+EC_I2C_SENSOR_SCL_R,C12,I2C_CLOCK,I2C_PORT_SENSOR
+EC_I2C_USB_C0_TCPC_SDA,K7,I2C_DATA,
+EC_I2C_USB_C0_TCPC_SCL,K8,I2C_CLOCK,I2C_PORT_USB_C0_TCPC
+EC_I2C_USB_C0_PPC_BC_SDA,K9,I2C_DATA,
+EC_I2C_USB_C0_PPC_BC_SCL,L8,I2C_CLOCK,I2C_PORT_PPC0
+EC_I2C_USB_C0_RT_SDA,F9,I2C_DATA,
+EC_I2C_USB_C0_RT_SCL,F8,I2C_CLOCK,I2C_PORT_USB_C0_RT
+EC_I2C_USB_C1_TCPC_SDA,F6,I2C_DATA,
+EC_I2C_USB_C1_TCPC_SCL,F5,I2C_CLOCK,I2C_PORT_USB_C1_TCPC
+EC_I2C_BAT_SCL,D5,I2C_CLOCK,I2C_PORT_BATTERY
+EC_I2C_BAT_SDA,D4,I2C_DATA,
+EC_I2C_USB_C1_MIX_SDA,L7,I2C_DATA,
+EC_I2C_USB_C1_MIX_SCL,L6,I2C_CLOCK,I2C_PORT_USB_1_MIX
+EC_I2C_MISC_SDA,K10,I2C_DATA,
+EC_I2C_MISC_SCL,J10,I2C_CLOCK,I2C_PORT_EEPROM
+KSI_07,C5,OTHER,
+KSI_06,C4,OTHER,
+KSI_05,C3,OTHER,
+KSI_04,B4,OTHER,
+EC_KSI_03,B3,OTHER,
+EC_KSI_02,A4,OTHER,
+KSI_01,A3,OTHER,
+EC_KSI_00,A2,OTHER,
+KSO_13,D11,OTHER,
+KSO_12,C11,OTHER,
+KSO_11,B10,OTHER,
+KSO_10,B11,OTHER,
+KSO_09,C10,OTHER,
+KSO_08,C9,OTHER,
+KSO_05,C6,OTHER,
+KSO_04,C7,OTHER,
+KSO_03,B8,OTHER,
+EC_KSO_02_INV,B7,OUTPUT_L,
+KSO_01,B6,OTHER,
+KSO_00,B5,OTHER,
+KSO_14,D6,OTHER,
+EC_KSO_07_JEN_L,B9,OTHER,
+EC_KSO_06_GP_SEL_L,C8,OTHER,
+LED_4_L,G6,OUTPUT,
+EC_KB_BL_PWM,K5,PWM,GPIO_EN_KEYBOARD_BACKLIGHT
+FAN_PWM,J7,PWM,
+LED_3_L,H10,OUTPUT,
+LED_2_L,G9,OUTPUT,
+LED_1_L,G8,OUTPUT,
+EC_RST_R_ODL,K6,INPUT,
+UART_GSC_DBG_TX_EC_RX_R,G4,OTHER,
+UART_GSC_DBG_RX_EC_TX_R,H4,OTHER,
+EC_SPARE_GPIO66,G2,OUTPUT,
+EC_CBI_WP,G5,OUTPUT,
+EC_SPARE_GPIOB1,D8,OUTPUT,
+EC_SPARE_GPIOC7,F10,OUTPUT,
+EC_SPARE_GPO32,E4,OUTPUT,
+EC_SPARE_GPO35,K2,OUTPUT,
+EC_32KXIN,L5,INPUT,
+EC_32KXOUT,M5,OUTPUT,
+ACOK_OD,E7,INPUT,GPIO_AC_PRESENT
+EC_SPARE_GPIO01,E6,INPUT_PU,
+EC_MECH_PWR_BTN_L,F7,INPUT,GPIO_POWER_BUTTON_L
+LID_OPEN,G7,INPUT,GPIO_LID_OPEN
+EN_Z1_RAILS,J8,OUTPUT,
+EN_PP5000_USBA_R,H6,OUTPUT,
diff --git a/zephyr/program/ovis/include/gpio_map.h b/zephyr/program/ovis/include/gpio_map.h
new file mode 100644
index 0000000000..9228aad61b
--- /dev/null
+++ b/zephyr/program/ovis/include/gpio_map.h
@@ -0,0 +1,9 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __ZEPHYR_GPIO_MAP_H
+#define __ZEPHYR_GPIO_MAP_H
+
+#endif /* __ZEPHYR_GPIO_MAP_H */
diff --git a/zephyr/program/ovis/include/usbc_config.h b/zephyr/program/ovis/include/usbc_config.h
new file mode 100644
index 0000000000..62fb348376
--- /dev/null
+++ b/zephyr/program/ovis/include/usbc_config.h
@@ -0,0 +1,22 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __ZEPHYR_USBC_CONFIG_H
+#define __ZEPHYR_USBC_CONFIG_H
+
+#include "usb_mux.h"
+
+/* USB-C ports */
+enum usbc_port {
+	USBC_PORT_C0 = 0,
+	USBC_PORT_C1,
+	USBC_PORT_C2,
+	USBC_PORT_COUNT
+};
+BUILD_ASSERT(USBC_PORT_COUNT == CONFIG_USB_PD_PORT_MAX_COUNT);
+
+void reset_nct38xx_port(int port);
+
+#endif /* __ZEPHYR_USBC_CONFIG_H */
diff --git a/zephyr/program/ovis/interrupts.dtsi b/zephyr/program/ovis/interrupts.dtsi
new file mode 100644
index 0000000000..bf1d8c3d98
--- /dev/null
+++ b/zephyr/program/ovis/interrupts.dtsi
@@ -0,0 +1,34 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_power_button: power_button {
+			irq-pin = <&gpio_mech_pwr_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_button_interrupt";
+		};
+		int_usb_c0_ppc: usb_c0_ppc {
+			irq-pin = <&gpio_usb_c0_ppc_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "ppc_interrupt";
+		};
+		int_usb_c1_ppc: usb_c1_ppc {
+			irq-pin = <&gpio_usb_c1_ppc_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "ppc_interrupt";
+		};
+		int_usb_c2_ppc: usb_c2_ppc {
+			irq-pin = <&gpio_usb_c2_ppc_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "ppc_interrupt";
+		};
+	};
+};
+
+/* Required node label that doesn't is named differently on Ovis */
+gpio_ec_pch_wake_odl: &gpio_ec_soc_wake_r_odl {};
diff --git a/zephyr/program/ovis/ovis.dtsi b/zephyr/program/ovis/ovis.dtsi
new file mode 100644
index 0000000000..17c6388a16
--- /dev/null
+++ b/zephyr/program/ovis/ovis.dtsi
@@ -0,0 +1,188 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/usb_pd_tcpm.h>
+
+/ {
+	aliases {
+		gpio-wp = &gpio_gsc_flash_wp_odl;
+		gpio-cbi-wp = &gpio_ec_cbi_wp;
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		gpio_ec_entering_rw: ec_entering_rw {
+			enum-name = "GPIO_ENTERING_RW";
+		};
+	};
+
+	usba-port-enable-list {
+		compatible = "cros-ec,usba-port-enable-pins";
+		enable-pins = <&gpio_en_usb_a_vbus>;
+	};
+};
+
+/* host interface */
+&espi0 {
+	status = "okay";
+	pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>;
+	pinctrl-names = "default";
+};
+
+/* Power switch logic input pads */
+&psl_in1_gpd2 {
+	/* LID_OPEN */
+	psl-in-mode = "edge";
+	psl-in-pol = "high-rising";
+};
+
+&psl_in2_gp00 {
+	/* ACOK_OD */
+	psl-in-mode = "edge";
+	psl-in-pol = "high-rising";
+};
+
+&psl_in4_gp02 {
+	/* MECH_PWR_BTN_ODL */
+	psl-in-mode = "edge";
+	psl-in-pol = "low-falling";
+};
+
+/* Power domain device controlled by PSL (Power Switch Logic) IO pads */
+&power_ctrl_psl {
+	status = "okay";
+	pinctrl-names = "sleep";
+	pinctrl-0 = <&psl_in1_gpd2 &psl_in2_gp00 &psl_in4_gp02>;
+};
+
+/* ADC and GPIO alt-function specifications */
+&adc0 {
+	pinctrl-0 = <&adc0_chan0_gp45
+		     &adc0_chan1_gp44>;
+	pinctrl-names = "default";
+};
+
+&i2c1_0 {
+	label = "I2C_USB_C0";
+	clock-frequency = <I2C_BITRATE_FAST>;
+
+	pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>;
+	pinctrl-names = "default";
+
+	tcpc_port0: rt1716@4e {
+		compatible = "richtek,rt1715-tcpc";
+		reg = <0x4e>;
+		tcpc-flags = <(TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V)>;
+		/* a duplicate of the <&gpio_usb_c1_tcpc_int_odl> node in
+		 * "named-gpios". This is the Zephyr preferred style,
+		 * the "named-gpios" node will be dealt with at a later date.
+		 */
+		irq-gpios = <&gpioe 0 GPIO_ACTIVE_LOW>;
+	};
+
+	ppc_port0_syv: ppc_syv@40 {
+		compatible = "silergy,syv682x";
+		status = "okay";
+		reg = <0x40>;
+		frs_en_gpio = <&gpio_usb_c0_frs_en>;
+	};
+
+	usb_c0_hb_retimer: jhl9040r-c0@56 {
+		compatible = "intel,jhl9040r";
+		reg = <0x56>;
+		ls-en-pin = <&gpio_usb_c0_rt_3p3_sx_en>;
+		int-pin = <&gpio_usb_c0_rt_int_odl>;
+		reset-pin = <&gpio_usb_c0_rt_rst_l>;
+	};
+};
+
+&i2c2_0 {
+	label = "I2C_USB_C1";
+	clock-frequency = <I2C_BITRATE_FAST>;
+
+	pinctrl-0 = <&i2c2_0_sda_scl_gp91_92>;
+	pinctrl-names = "default";
+
+	tcpc_port1: rt1716@4e {
+		compatible = "richtek,rt1715-tcpc";
+		reg = <0x4e>;
+		tcpc-flags = <(TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V)>;
+		/* a duplicate of the <&gpio_usb_c1_tcpc_int_odl> node in
+		 * "named-gpios". This is the Zephyr preferred style,
+		 * the "named-gpios" node will be dealt with at a later date.
+		 */
+		irq-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
+	};
+
+	ppc_port1_syv: ppc_syv@40 {
+		compatible = "silergy,syv682x";
+		status = "okay";
+		reg = <0x40>;
+		frs_en_gpio = <&gpio_usb_c1_frs_en>;
+	};
+
+	usb_c1_hb_retimer: jhl9040r-c0@56 {
+		compatible = "intel,jhl9040r";
+		reg = <0x56>;
+		ls-en-pin = <&gpio_usb_c1_rt_3p3_sx_en>;
+		int-pin = <&gpio_usb_c1_rt_int_odl>;
+		reset-pin = <&gpio_usb_c1_rt_rst_l>;
+	};
+};
+
+&i2c3_0 {
+	label = "I2C_USB_C2";
+	clock-frequency = <I2C_BITRATE_FAST>;
+
+	pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>;
+	pinctrl-names = "default";
+
+	tcpc_port2: rt1716@4e {
+		compatible = "richtek,rt1715-tcpc";
+		reg = <0x4e>;
+		tcpc-flags = <(TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V)>;
+		/* a duplicate of the <&gpio_usb_c1_tcpc_int_odl> node in
+		 * "named-gpios". This is the Zephyr preferred style,
+		 * the "named-gpios" node will be dealt with at a later date.
+		 */
+		irq-gpios = <&gpiod 4 GPIO_ACTIVE_LOW>;
+	};
+
+	ppc_port2_syv: ppc_syv@40 {
+		compatible = "silergy,syv682x";
+		status = "okay";
+		reg = <0x40>;
+		frs_en_gpio = <&gpio_usb_c2_frs_en>;
+	};
+
+	usb_c2_hb_retimer: jhl9040r-c0@56 {
+		compatible = "intel,jhl9040r";
+		reg = <0x56>;
+		ls-en-pin = <&gpio_usb_c2_rt_3p3_sx_en>;
+		int-pin = <&gpio_usb_c2_rt_int_odl>;
+		reset-pin = <&gpio_usb_c2_rt_rst_l>;
+	};
+};
+
+&i2c7_0 {
+	label = "I2C_MISC";
+	clock-frequency = <I2C_BITRATE_FAST>;
+
+	pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>;
+	pinctrl-names = "default";
+
+	cbi_eeprom: eeprom@50 {
+		compatible = "atmel,at24";
+		reg = <0x50>;
+		size = <2048>;
+		pagesize = <16>;
+		address-width = <8>;
+		timeout = <5>;
+	};
+};
diff --git a/zephyr/program/ovis/ovis/CMakeLists.txt b/zephyr/program/ovis/ovis/CMakeLists.txt
new file mode 100644
index 0000000000..20607e379e
--- /dev/null
+++ b/zephyr/program/ovis/ovis/CMakeLists.txt
@@ -0,0 +1,7 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cros_ec_library_include_directories_ifdef(CONFIG_BOARD_OVIS include)
+zephyr_include_directories("include")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/usbc_config.c")
diff --git a/zephyr/program/ovis/ovis/include/usb_mux_config.h b/zephyr/program/ovis/ovis/include/usb_mux_config.h
new file mode 100644
index 0000000000..b43d96f209
--- /dev/null
+++ b/zephyr/program/ovis/ovis/include/usb_mux_config.h
@@ -0,0 +1,11 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __ZEPHYR_USB_MUX_CONFIG_H
+#define __ZEPHYR_USB_MUX_CONFIG_H
+
+extern uint32_t usb_db_type;
+
+#endif /* __ZEPHYR_USB_MUX_CONFIG_H */
diff --git a/zephyr/program/ovis/ovis/led_pins.dtsi b/zephyr/program/ovis/ovis/led_pins.dtsi
new file mode 100644
index 0000000000..0eab076ddd
--- /dev/null
+++ b/zephyr/program/ovis/ovis/led_pins.dtsi
@@ -0,0 +1,31 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	gpio-led-pins {
+		compatible = "cros-ec,gpio-led-pins";
+
+		left_led: left-led {
+			led-id = "EC_LED_ID_LEFT_LED";
+			led-pins = <&gpio_led_1_l &gpio_led_2_l>;
+			color_off_left: color-off-left {
+				led-color = "LED_OFF";
+				led-values = <1 1>;
+			};
+
+			color_amber_left: color-amber-left {
+				led-color = "LED_AMBER";
+				br-color = "EC_LED_COLOR_AMBER";
+				led-values = <0 1>;
+			};
+
+			color_white_left: color-white-left {
+				led-color = "LED_WHITE";
+				br-color = "EC_LED_COLOR_WHITE";
+				led-values = <1 0>;
+			};
+		};
+	};
+};
diff --git a/zephyr/program/ovis/ovis/project.conf b/zephyr/program/ovis/ovis/project.conf
new file mode 100644
index 0000000000..4a862d73bb
--- /dev/null
+++ b/zephyr/program/ovis/ovis/project.conf
@@ -0,0 +1,6 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Ovis-NPCX9 reference-board-specific Kconfig settings.
+CONFIG_BOARD_OVIS=y
diff --git a/zephyr/program/ovis/ovis/project.overlay b/zephyr/program/ovis/ovis/project.overlay
new file mode 100644
index 0000000000..7be2911b16
--- /dev/null
+++ b/zephyr/program/ovis/ovis/project.overlay
@@ -0,0 +1,20 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Ovis program common DTSI includes */
+#include "../fan.dtsi"
+#include "../generated.dtsi"
+#include "../interrupts.dtsi"
+#include "../power_signals.dtsi"
+#include "../ovis.dtsi"
+#include "../temp_sensors.dtsi"
+#include "../usbc.dtsi"
+
+/* Ovis project DTS includes */
+#include "led_pins.dtsi"
+/*
+ * TODO(b/285166688): need led_policy.dtsi once that has been
+ * implemented to match Ovis requirements
+ */
diff --git a/zephyr/program/ovis/ovis/src/usbc_config.c b/zephyr/program/ovis/ovis/src/usbc_config.c
new file mode 100644
index 0000000000..81d1a469bc
--- /dev/null
+++ b/zephyr/program/ovis/ovis/src/usbc_config.c
@@ -0,0 +1,35 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cros_cbi.h"
+#include "driver/ppc/ktu1125_public.h"
+#include "driver/ppc/nx20p348x.h"
+#include "driver/tcpm/ps8xxx_public.h"
+#include "ppc/syv682x_public.h"
+#include "system.h"
+#include "usb_mux_config.h"
+#include "usbc_config.h"
+
+void board_reset_pd_mcu(void)
+{
+	/* Required for build */
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C1);
+		break;
+	case GPIO_USB_C2_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C2);
+		break;
+	default:
+		break;
+	}
+}
diff --git a/zephyr/program/ovis/power_signals.dtsi b/zephyr/program/ovis/power_signals.dtsi
new file mode 100644
index 0000000000..863c4912f9
--- /dev/null
+++ b/zephyr/program/ovis/power_signals.dtsi
@@ -0,0 +1,152 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	chosen {
+		intel-ap-pwrseq,espi = &espi0;
+	};
+
+	common-pwrseq {
+		compatible = "intel,ap-pwrseq";
+
+		sys-pwrok-delay = <3>;
+		all-sys-pwrgd-timeout = <20>;
+	};
+
+	pwr-en-pp3300-s5 {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PP1800_S5/PP3300_S5 enable output to LS";
+		enum-name = "PWR_EN_PP3300_A";
+		gpios = <&gpiob 6 GPIO_ACTIVE_HIGH>;
+		output;
+	};
+	pwr-pg-ec-rsmrst-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST power good from regulator";
+		enum-name = "PWR_RSMRST";
+		gpios = <&gpioe 2 GPIO_ACTIVE_HIGH>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-ec-pch-rsmrst-odl {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST output to PCH";
+		enum-name = "PWR_EC_PCH_RSMRST";
+		gpios = <&gpioa 6 GPIO_ACTIVE_HIGH>;
+		output;
+	};
+	pwr-pch-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PCH_PWROK output to PCH";
+		enum-name = "PWR_PCH_PWROK";
+		gpios = <&gpioa 5 GPIO_ACTIVE_HIGH>;
+		output;
+	};
+	pwr-ec-pch-sys-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_PWROK output to PCH";
+		enum-name = "PWR_EC_PCH_SYS_PWROK";
+		gpios = <&gpiob 0 GPIO_ACTIVE_HIGH>;
+		output;
+	};
+	pwr-sys-rst-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_RESET# output to PCH";
+		enum-name = "PWR_SYS_RST";
+		gpios = <&gpioc 5 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+		output;
+	};
+	pwr-slp-s0-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_S0_L input from PCH";
+		enum-name = "PWR_SLP_S0";
+		gpios = <&gpiod 5 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-slp-s3-l {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S3_L input from PCH";
+		enum-name = "PWR_SLP_S3";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4";
+		vw-invert;
+/*
+ * TODO: Initially, use virtual wire for sleep S3 signal instead of
+ * of the GPIO signal which also exists.
+ *		compatible = "intel,ap-pwrseq-gpio";
+ *		gpios = <&gpio4 1 GPIO_ACTIVE_LOW>;
+ *		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+ */
+	};
+	pwr-slp-s4 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S4 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S4";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4";
+		vw-invert;
+	};
+	pwr-slp-s5 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S5 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S5";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5";
+		vw-invert;
+	};
+	pwr-all-sys-pwrgd {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "all power good";
+		enum-name = "PWR_ALL_SYS_PWRGD";
+		gpios = <&gpiof 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+};
+
+/*
+ * Because the power signals directly reference the GPIOs,
+ * the corresponding named-gpios need to have no-auto-init set.
+ */
+ /* pwr-en-pp3300-s5 */
+&gpio_en_s5_rails {
+	no-auto-init;
+};
+
+/* pwr-pg-ec-rsmrst-od */
+&gpio_seq_ec_rsmrst_odl {
+	no-auto-init;
+};
+
+/* pwr-ec-pch-rsmrst-odl */
+&gpio_ec_soc_rsmrst_l {
+	no-auto-init;
+};
+
+/* pwr-pch-pwrok */
+&gpio_soc_pwrok {
+	no-auto-init;
+};
+
+/* pwr-ec-pch-sys-pwrok */
+&gpio_sys_pwrok {
+	no-auto-init;
+};
+
+/* pwr-sys-rst-l */
+&gpio_sys_rst_odl {
+	no-auto-init;
+};
+
+/* pwr-slp-s0-l */
+&gpio_sys_slp_s0ix_l {
+	no-auto-init;
+};
+
+/* pwr-slp-s3-l */
+&gpio_slp_s3_ls_l {
+	no-auto-init;
+};
+
+/* pwr-all-sys-pwrgd */
+&gpio_seq_ec_all_sys_pg_od {
+	no-auto-init;
+};
+
diff --git a/zephyr/program/ovis/program.conf b/zephyr/program/ovis/program.conf
new file mode 100644
index 0000000000..a8869b2e9b
--- /dev/null
+++ b/zephyr/program/ovis/program.conf
@@ -0,0 +1,106 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_PLATFORM_EC=y
+CONFIG_CROS_EC=y
+CONFIG_SHIMMED_TASKS=y
+CONFIG_SYSCON=y
+
+# Shell Commands
+CONFIG_SHELL_HELP=n
+CONFIG_SHELL_HISTORY=y
+CONFIG_SHELL_TAB=y
+CONFIG_SHELL_TAB_AUTOCOMPLETION=y
+CONFIG_KERNEL_SHELL=y
+
+CONFIG_PLATFORM_EC_SWITCH=y
+CONFIG_PLATFORM_EC_VBOOT_EFS2=y
+
+# Application processor; communicates with EC via eSPI
+CONFIG_AP=y
+CONFIG_ESPI=y
+CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S3=y
+CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S4=y
+CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S5=y
+CONFIG_PLATFORM_EC_HOSTCMD=y
+CONFIG_HCDEBUG_OFF=y
+# Disabling this until temp sensor support is in
+CONFIG_PLATFORM_EC_THROTTLE_AP=n
+CONFIG_PLATFORM_EC_PORT80=y
+
+# Power Sequecing
+CONFIG_AP_X86_INTEL_MTL=y
+CONFIG_X86_NON_DSX_PWRSEQ_MTL=y
+CONFIG_X86_NON_DSX_PWRSEQ_HOST_CMD=y
+# TODO (b/240434243): This may be needed, but using eSPI VW for now
+CONFIG_PLATFORM_EC_POWERSEQ_SLP_S3_L_OVERRIDE=n
+CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n
+
+# Zephyr Inbuilt AP Power Sequencing Config
+CONFIG_X86_NON_DSX_PWRSEQ_CONSOLE=y
+CONFIG_AP_PWRSEQ_S0IX=y
+CONFIG_AP_PWRSEQ_S0IX_ERROR_RECOVERY=y
+
+# I2C
+CONFIG_PLATFORM_EC_HOSTCMD_I2C_CONTROL=y
+
+# Temperature sensors
+CONFIG_PLATFORM_EC_TEMP_SENSOR_POWER=y
+
+# CBI EEPROM support
+CONFIG_EEPROM=y
+CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=y
+CONFIG_PLATFORM_EC_EEPROM_CBI_WP=y
+
+# Charger
+# Both of these options neeed to be explicity disabled
+CONFIG_PLATFORM_EC_USB_CHARGER=n
+CONFIG_PLATFORM_EC_CHARGE_MANAGER=n
+
+# USBC
+CONFIG_PLATFORM_EC_USBC=y
+CONFIG_PLATFORM_EC_USBC_PPC=y
+CONFIG_PLATFORM_EC_USBC_PPC_SYV682C=y
+# TODO(b/241340453): after FRS fixed, enable this config
+CONFIG_PLATFORM_EC_USBC_PPC_SYV682X_SMART_DISCHARGE=n
+CONFIG_PLATFORM_EC_USBC_VCONN=y
+
+CONFIG_PLATFORM_EC_USB_DRP_ACC_TRYSRC=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y
+CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y
+CONFIG_PLATFORM_EC_USB_PD_FRS=y
+CONFIG_PLATFORM_EC_USB_PD_FRS_PPC=y
+CONFIG_PLATFORM_EC_USB_PD_LOGGING=y
+CONFIG_PLATFORM_EC_USB_PD_REV30=y
+CONFIG_PLATFORM_EC_USB_PD_TCPC_LOW_POWER=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_TCPCI=y
+CONFIG_PLATFORM_EC_USB_PD_TRY_SRC=y
+CONFIG_PLATFORM_EC_USB_PD_DUAL_ROLE_AUTO_TOGGLE=y
+CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=y
+CONFIG_PLATFORM_EC_USB_PD_USB32_DRD=y
+CONFIG_PLATFORM_EC_USB_PD_USB4=y
+CONFIG_PLATFORM_EC_USB_PD_REQUIRE_AP_MODE_ENTRY=y
+CONFIG_PLATFORM_EC_USB_PD_DATA_RESET_MSG=y
+CONFIG_PLATFORM_EC_USB_PID=0x504D
+
+# USB Mux
+CONFIG_PLATFORM_EC_USB_MUX_TASK=y
+
+# Standard shimmed features
+CONFIG_PLATFORM_EC_POWER_BUTTON=y
+
+# Required to make Ovis build
+CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y
+CONFIG_PLATFORM_EC_POWER_BUTTON_IGNORE_LID=y
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
+CONFIG_PLATFORM_EC_LID_SWITCH=n
+CONFIG_PLATFORM_EC_HIBERNATE_PSL=n
+
+# MKBP event
+CONFIG_PLATFORM_EC_MKBP_EVENT=y
+CONFIG_PLATFORM_EC_MKBP_INPUT_DEVICES=y
+CONFIG_PLATFORM_EC_MKBP_USE_GPIO_AND_HOST_EVENT=y
+
+# System Boot Time
+CONFIG_SYSTEM_BOOT_TIME_LOGGING=y
diff --git a/zephyr/program/ovis/src/board_power.c b/zephyr/program/ovis/src/board_power.c
new file mode 100644
index 0000000000..f9547fd150
--- /dev/null
+++ b/zephyr/program/ovis/src/board_power.c
@@ -0,0 +1,65 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "gpio/gpio.h"
+#include "gpio_signal.h"
+#include "system_boot_time.h"
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/logging/log.h>
+
+#include <ap_power/ap_power.h>
+#include <ap_power/ap_power_events.h>
+#include <ap_power/ap_power_interface.h>
+#include <ap_power_override_functions.h>
+#include <power_signals.h>
+#include <x86_power_signals.h>
+
+LOG_MODULE_DECLARE(ap_pwrseq, LOG_LEVEL_INF);
+
+#if defined(CONFIG_X86_NON_DSX_PWRSEQ_MTL) || \
+	defined(CONFIG_TEST_X86_NON_DSX_PWRSEQ_MTL)
+#define X86_NON_DSX_MTL_FORCE_SHUTDOWN_TO_MS 50
+
+void board_ap_power_force_shutdown(void)
+{
+	int timeout_ms = X86_NON_DSX_MTL_FORCE_SHUTDOWN_TO_MS;
+
+	/* Turn off PCH_RMSRST to meet tPCH12 */
+	power_signal_set(PWR_EC_PCH_RSMRST, 0);
+
+	/* Turn off PRIM load switch. */
+	power_signal_set(PWR_EN_PP3300_A, 0);
+
+	/* Wait RSMRST to be off. */
+	while (power_signal_get(PWR_RSMRST) && (timeout_ms > 0)) {
+		k_msleep(1);
+		timeout_ms--;
+	};
+
+	if (power_signal_get(PWR_RSMRST)) {
+		LOG_WRN("RSMRST_ODL didn't go low!  Assuming G3.");
+	}
+}
+
+void board_ap_power_action_g3_s5(void)
+{
+	/* Turn on the PP3300_PRIM rail. */
+	power_signal_set(PWR_EN_PP3300_A, 1);
+
+	update_ap_boot_time(ARAIL);
+
+	if (!power_wait_signals_timeout(
+		    IN_PGOOD_ALL_CORE,
+		    AP_PWRSEQ_DT_VALUE(wait_signal_timeout))) {
+		ap_power_ev_send_callbacks(AP_POWER_PRE_INIT);
+	}
+}
+
+bool board_ap_power_check_power_rails_enabled(void)
+{
+	return power_signal_get(PWR_EN_PP3300_A);
+}
+#endif /* CONFIG_X86_NON_DSX_PWRSEQ_MTL */
diff --git a/zephyr/program/ovis/src/usb_pd_policy.c b/zephyr/program/ovis/src/usb_pd_policy.c
new file mode 100644
index 0000000000..049162e782
--- /dev/null
+++ b/zephyr/program/ovis/src/usb_pd_policy.c
@@ -0,0 +1,84 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Shared USB-C policy for Ovis boards */
+
+#include "charge_manager.h"
+#include "chipset.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "ioexpander.h"
+#include "power_signals.h"
+#include "system.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#include <zephyr/drivers/gpio.h>
+
+int pd_check_vconn_swap(int port)
+{
+	/* Allow VCONN swaps when PWR_ALL_SYS_PWRGD is set. */
+	return power_signal_get(PWR_ALL_SYS_PWRGD);
+}
+
+void pd_power_supply_reset(int port)
+{
+	/* Disable VBUS. */
+	ppc_vbus_source_enable(port, 0);
+
+	/* Enable discharge if we were previously sourcing 5V */
+	if (IS_ENABLED(CONFIG_USB_PD_DISCHARGE))
+		pd_set_vbus_discharge(port, 1);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	/* Disable charging. */
+	rv = ppc_vbus_sink_enable(port, 0);
+	if (rv)
+		return rv;
+
+	if (IS_ENABLED(CONFIG_USB_PD_DISCHARGE)) {
+		pd_set_vbus_discharge(port, 0);
+	}
+
+	/* Provide Vbus. */
+	rv = ppc_vbus_source_enable(port, 1);
+	if (rv) {
+		return rv;
+	}
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+void pd_set_input_current_limit(int port, uint32_t max_ma,
+				uint32_t supply_voltage)
+{
+	/* TODO(b/285166049): Need this to build, does this apply to Ovis */
+}
+
+/* Used by Vbus discharge common code with CONFIG_USB_PD_DISCHARGE */
+int board_vbus_source_enabled(int port)
+{
+	return ppc_is_sourcing_vbus(port);
+}
+
+/* Used by USB charger task with CONFIG_USB_PD_5V_EN_CUSTOM */
+int board_is_sourcing_vbus(int port)
+{
+	return board_vbus_source_enabled(port);
+}
diff --git a/zephyr/program/ovis/src/usbc_config.c b/zephyr/program/ovis/src/usbc_config.c
new file mode 100644
index 0000000000..60ba10eec4
--- /dev/null
+++ b/zephyr/program/ovis/src/usbc_config.c
@@ -0,0 +1,66 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery_fuel_gauge.h"
+#include "charge_manager.h"
+#include "charge_ramp.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "driver/charger/isl9241.h"
+#include "driver/ppc/nx20p348x.h"
+#include "driver/retimer/bb_retimer_public.h"
+#include "driver/tcpm/nct38xx.h"
+#include "driver/tcpm/tcpci.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "ioexpander.h"
+#include "ppc/syv682x_public.h"
+#include "system.h"
+#include "task.h"
+#include "usb_mux.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+#include <stdbool.h>
+
+#include <zephyr/drivers/espi.h>
+#include <zephyr/drivers/gpio.h>
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/* eSPI device */
+#define espi_dev DEVICE_DT_GET(DT_CHOSEN(cros_ec_espi))
+
+/*******************************************************************/
+/* USB-C Configuration Start */
+
+static void usbc_interrupt_init(void)
+{
+	/* Enable PPC interrupts. */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_ppc));
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_ppc));
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c2_ppc));
+}
+DECLARE_HOOK(HOOK_INIT, usbc_interrupt_init, HOOK_PRIO_POST_I2C);
+
+__override void board_overcurrent_event(int port, int is_overcurrented)
+{
+	/*
+	 * Meteorlake PCH uses Virtual Wire for over current error,
+	 * hence Send 'Over Current Virtual Wire' eSPI signal.
+	 */
+	espi_send_vwire(espi_dev, port + ESPI_VWIRE_SIGNAL_SLV_GPIO_0,
+			!is_overcurrented);
+}
+
+void sbu_fault_interrupt(enum gpio_signal signal)
+{
+	int port = USBC_PORT_C0;
+
+	CPRINTSUSB("C%d: SBU fault", port);
+	pd_handle_overcurrent(port);
+}
diff --git a/zephyr/program/ovis/temp_sensors.dtsi b/zephyr/program/ovis/temp_sensors.dtsi
new file mode 100644
index 0000000000..d3bd405f15
--- /dev/null
+++ b/zephyr/program/ovis/temp_sensors.dtsi
@@ -0,0 +1,43 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <cros/thermistor/thermistor.dtsi>
+
+/ {
+	temp_ddr_soc: ddr_soc {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_30K9_47K_4050B>;
+		adc = <&adc_temp_sensor_1>;
+	};
+	temp_ambient: ambient {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_30K9_47K_4050B>;
+		adc = <&adc_temp_sensor_2>;
+	};
+
+	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
+		ddr_soc {
+			temp_fan_off = <35>;
+			temp_fan_max = <60>;
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			sensor = <&temp_ddr_soc>;
+		};
+		ambient {
+			temp_fan_off = <35>;
+			temp_fan_max = <60>;
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			sensor = <&temp_ambient>;
+		};
+	};
+};
+
+&thermistor_3V3_30K9_47K_4050B {
+	status = "okay";
+};
diff --git a/zephyr/program/ovis/usbc.dtsi b/zephyr/program/ovis/usbc.dtsi
new file mode 100644
index 0000000000..3a64dbf354
--- /dev/null
+++ b/zephyr/program/ovis/usbc.dtsi
@@ -0,0 +1,62 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		usbc_port0: port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+			ppc = <&ppc_port0_syv>;
+			tcpc = <&tcpc_port0>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_c0_hb_retimer
+					     &virtual_mux_c0>;
+			};
+		};
+		port0-muxes {
+			virtual_mux_c0: virtual-mux-c0 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+
+		usbc_port1: port1@1 {
+			compatible = "named-usbc-port";
+			reg = <1>;
+			ppc = <&ppc_port1_syv>;
+			tcpc = <&tcpc_port1>;
+			usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_c1_hb_retimer
+					     &virtual_mux_c1>;
+			};
+		};
+		port1-muxes {
+			virtual_mux_c1: virtual-mux-c1 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+
+		usbc_port2: port2@2 {
+			compatible = "named-usbc-port";
+			reg = <2>;
+			ppc = <&ppc_port2_syv>;
+			tcpc = <&tcpc_port2>;
+			usb-mux-chain-2 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_c2_hb_retimer
+					     &virtual_mux_c2>;
+			};
+		};
+		port2-muxes {
+			virtual_mux_c2: virtual-mux-c2 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+	};
+};
diff --git a/zephyr/program/rex/BUILD.py b/zephyr/program/rex/BUILD.py
new file mode 100644
index 0000000000..2caae122b8
--- /dev/null
+++ b/zephyr/program/rex/BUILD.py
@@ -0,0 +1,53 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Define zmake projects for Rex."""
+
+
+def register_rex_project(
+    project_name,
+    kconfig_files=None,
+):
+    """Register a variant of Rex."""
+    if kconfig_files is None:
+        kconfig_files = [
+            # Common to all projects.
+            here / "program.conf",
+            # Project-specific KConfig customization.
+            here / project_name / "project.conf",
+        ]
+
+    register_npcx_project(
+        project_name=project_name,
+        zephyr_board="npcx9m7f",
+        dts_overlays=[
+            here / project_name / "project.overlay",
+        ],
+        kconfig_files=kconfig_files,
+        inherited_from=["rex"],
+    )
+
+
+register_rex_project(
+    project_name="rex",
+)
+
+register_rex_project(
+    project_name="rex-ish-ec",
+    kconfig_files=[
+        # Common to all projects.
+        here / "program.conf",
+        # Parent project's config
+        here / "rex" / "project.conf",
+        # Project-specific KConfig customization.
+        here / "rex-ish-ec" / "project.conf",
+    ],
+)
+
+register_rex_project(
+    project_name="screebo",
+)
+register_rex_project(
+    project_name="karis",
+)
diff --git a/zephyr/program/rex/CMakeLists.txt b/zephyr/program/rex/CMakeLists.txt
new file mode 100644
index 0000000000..2790a99146
--- /dev/null
+++ b/zephyr/program/rex/CMakeLists.txt
@@ -0,0 +1,19 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.20.5)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+
+zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}/include")
+zephyr_library_sources_ifdef(CONFIG_AP_PWRSEQ "src/board_power.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/usbc_config.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/usb_pd_policy.c")
+
+if(DEFINED CONFIG_BOARD_REX)
+	project(rex)
+	add_subdirectory(rex)
+elseif(DEFINED CONFIG_BOARD_SCREEBO)
+	project(screebo)
+	add_subdirectory(screebo)
+endif()
diff --git a/zephyr/program/rex/Kconfig b/zephyr/program/rex/Kconfig
new file mode 100644
index 0000000000..723febc6d4
--- /dev/null
+++ b/zephyr/program/rex/Kconfig
@@ -0,0 +1,21 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config BOARD_REX
+	bool "Google Rex Baseboard"
+	help
+	  Build Google Rex reference board.  The board uses Nuvoton
+	  NPCX9 chip as the EC.
+
+config BOARD_SCREEBO
+	bool "Google Screebo Board"
+	help
+	  Build Google Screebo variant board. The board uses Nuvoton
+	  NPCX9 chip as the EC.
+
+module = REX
+module-str = Rex board-specific code
+source "subsys/logging/Kconfig.template.log_config"
+
+source "Kconfig.zephyr"
diff --git a/zephyr/program/rex/battery.dtsi b/zephyr/program/rex/battery.dtsi
new file mode 100644
index 0000000000..e11346f48d
--- /dev/null
+++ b/zephyr/program/rex/battery.dtsi
@@ -0,0 +1,12 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	batteries {
+		default_battery: batgqa05l22 {
+			compatible = "powertech,batgqa05l22", "battery-smart";
+		};
+	};
+};
diff --git a/zephyr/program/rex/fan.dtsi b/zephyr/program/rex/fan.dtsi
new file mode 100644
index 0000000000..aa6dcfde7d
--- /dev/null
+++ b/zephyr/program/rex/fan.dtsi
@@ -0,0 +1,39 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	fans {
+		compatible = "cros-ec,fans";
+
+		fan_0 {
+			pwms = <&pwm5 0 PWM_KHZ(1) PWM_POLARITY_NORMAL>;
+			rpm_min = <2200>;
+			rpm_start = <2200>;
+			rpm_max = <4200>;
+			tach = <&tach1>;
+			enable_gpio = <&gpio_en_pp5000_fan>;
+		};
+	};
+};
+
+/* Tachemeter for fan speed measurement */
+&tach1 {
+	status = "okay";
+	pinctrl-0 = <&ta1_1_in_gp40>;
+	pinctrl-names = "default";
+	port = <NPCX_TACH_PORT_A>; /* port-A is selected */
+	sample-clk = <NPCX_TACH_FREQ_LFCLK>; /* Use LFCLK as sampling clock */
+	pulses-per-round = <2>; /* number of pulses per round of encoder */
+};
+
+&pwm5_gpb7 {
+	drive-open-drain;
+};
+
+&pwm5 {
+	status = "okay";
+	pinctrl-0 = <&pwm5_gpb7>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/rex/generated.dtsi b/zephyr/program/rex/generated.dtsi
new file mode 100644
index 0000000000..3a878f9bc7
--- /dev/null
+++ b/zephyr/program/rex/generated.dtsi
@@ -0,0 +1,357 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * This file is auto-generated - do not edit!
+ */
+
+/ {
+
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		adc_temp_sensor_1: temp_sensor_1 {
+			enum-name = "ADC_TEMP_SENSOR_1_DDR_SOC";
+			io-channels = <&adc0 0>;
+		};
+		adc_temp_sensor_2: temp_sensor_2 {
+			enum-name = "ADC_TEMP_SENSOR_2_AMBIENT";
+			io-channels = <&adc0 1>;
+		};
+		adc_temp_sensor_3: temp_sensor_3 {
+			enum-name = "ADC_TEMP_SENSOR_3_CHARGER";
+			io-channels = <&adc0 8>;
+		};
+		adc_temp_sensor_4: temp_sensor_4 {
+			enum-name = "ADC_TEMP_SENSOR_4_WWAN";
+			io-channels = <&adc0 7>;
+		};
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		gpio_acok_od: acok_od {
+			gpios = <&gpio0 0 GPIO_INPUT>;
+			enum-name = "GPIO_AC_PRESENT";
+		};
+		gpio_ccd_mode_odl: ccd_mode_odl {
+			gpios = <&gpioe 5 GPIO_INPUT>;
+			enum-name = "GPIO_CCD_MODE_ODL";
+		};
+		gpio_cpu_c10_gate_l: cpu_c10_gate_l {
+			gpios = <&gpioa 7 GPIO_INPUT>;
+		};
+		gpio_ec_accel_int_r_l: ec_accel_int_r_l {
+			gpios = <&gpio8 1 GPIO_INPUT>;
+		};
+		gpio_ec_als_rgb_int_r_l: ec_als_rgb_int_r_l {
+			gpios = <&gpiod 4 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_ec_batt_pres_odl: ec_batt_pres_odl {
+			gpios = <&gpioa 3 GPIO_INPUT>;
+			enum-name = "GPIO_BATT_PRES_ODL";
+		};
+		gpio_ec_cbi_wp: ec_cbi_wp {
+			gpios = <&gpio7 3 GPIO_OUTPUT>;
+		};
+		gpio_ec_edp_bl_en: ec_edp_bl_en {
+			gpios = <&gpiod 3 GPIO_OUTPUT>;
+			enum-name = "GPIO_ENABLE_BACKLIGHT";
+		};
+		gpio_ec_gsc_packet_mode: ec_gsc_packet_mode {
+			gpios = <&gpio7 5 GPIO_OUTPUT>;
+			enum-name = "GPIO_PACKET_MODE_EN";
+		};
+		gpio_ec_imu_int_r_l: ec_imu_int_r_l {
+			gpios = <&gpio5 6 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_ec_kb_bl_en_l: ec_kb_bl_en_l {
+			gpios = <&gpio8 6 GPIO_OUTPUT>;
+		};
+		gpio_ec_kso_02_inv: ec_kso_02_inv {
+			gpios = <&gpio1 7 (GPIO_OUTPUT | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_ec_mech_pwr_btn_l: ec_mech_pwr_btn_l {
+			gpios = <&gpio0 2 GPIO_INPUT>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		gpio_ec_prochot_in_l: ec_prochot_in_l {
+			gpios = <&gpiof 0 GPIO_INPUT>;
+		};
+		gpio_ec_prochot_odl: ec_prochot_odl {
+			gpios = <&gpio6 3 GPIO_ODR_HIGH>;
+		};
+		gpio_ec_rst_r_odl: ec_rst_r_odl {
+			gpios = <&gpio7 7 GPIO_INPUT>;
+		};
+		gpio_ec_soc_int_odl: ec_soc_int_odl {
+			gpios = <&gpio7 0 GPIO_ODR_LOW>;
+			enum-name = "GPIO_EC_INT_L";
+		};
+		gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl {
+			gpios = <&gpioc 1 GPIO_ODR_LOW>;
+			enum-name = "GPIO_PCH_PWRBTN_L";
+		};
+		gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l {
+			gpios = <&gpioa 6 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_rtcrst: ec_soc_rtcrst {
+			gpios = <&gpio7 6 GPIO_ODR_HIGH>;
+		};
+		gpio_ec_soc_wake_r_odl: ec_soc_wake_r_odl {
+			gpios = <&gpioc 0 GPIO_ODR_LOW>;
+		};
+		gpio_ec_spare_gpio01: ec_spare_gpio01 {
+			gpios = <&gpio0 1 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_ec_spare_gpio42: ec_spare_gpio42 {
+			gpios = <&gpio4 2 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpio66: ec_spare_gpio66 {
+			gpios = <&gpio6 6 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpio94: ec_spare_gpio94 {
+			gpios = <&gpio9 4 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpioa2: ec_spare_gpioa2 {
+			gpios = <&gpioa 2 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpioa4: ec_spare_gpioa4 {
+			gpios = <&gpioa 4 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpiob1: ec_spare_gpiob1 {
+			gpios = <&gpiob 1 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpioc7: ec_spare_gpioc7 {
+			gpios = <&gpioc 7 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpo32: ec_spare_gpo32 {
+			gpios = <&gpio3 2 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpo35: ec_spare_gpo35 {
+			gpios = <&gpio3 5 GPIO_OUTPUT>;
+		};
+		gpio_ec_voldn_btn_odl: ec_voldn_btn_odl {
+			gpios = <&gpio9 3 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_DOWN_L";
+		};
+		gpio_ec_volup_btn_odl: ec_volup_btn_odl {
+			gpios = <&gpio9 7 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_UP_L";
+		};
+		gpio_ec_wp_l: ec_wp_l {
+			gpios = <&gpioa 1 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_en_pp5000_fan: en_pp5000_fan {
+			gpios = <&gpio6 1 GPIO_OUTPUT>;
+		};
+		gpio_en_pp5000_usba_r: en_pp5000_usba_r {
+			gpios = <&gpiod 7 GPIO_OUTPUT>;
+		};
+		gpio_en_s5_rails: en_s5_rails {
+			gpios = <&gpiob 6 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_TEMP_SENSOR_POWER";
+		};
+		gpio_en_z1_rails: en_z1_rails {
+			gpios = <&gpio8 5 GPIO_OUTPUT>;
+		};
+		gpio_imvp92_vrrdy_od: imvp92_vrrdy_od {
+			gpios = <&gpio4 3 GPIO_INPUT>;
+		};
+		gpio_led_1_l: led_1_l {
+			gpios = <&gpioc 4 GPIO_OUTPUT>;
+		};
+		gpio_led_2_l: led_2_l {
+			gpios = <&gpioc 3 GPIO_OUTPUT>;
+		};
+		gpio_led_3_l: led_3_l {
+			gpios = <&gpioc 2 GPIO_OUTPUT>;
+		};
+		gpio_led_4_l: led_4_l {
+			gpios = <&gpio6 0 GPIO_OUTPUT>;
+		};
+		gpio_lid_open: lid_open {
+			gpios = <&gpiod 2 GPIO_INPUT>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+		gpio_seq_ec_all_sys_pg_od: seq_ec_all_sys_pg_od {
+			gpios = <&gpiof 4 GPIO_INPUT>;
+		};
+		gpio_seq_ec_rsmrst_odl: seq_ec_rsmrst_odl {
+			gpios = <&gpioe 2 GPIO_INPUT>;
+		};
+		gpio_slp_s3_ls_l: slp_s3_ls_l {
+			gpios = <&gpio4 1 GPIO_INPUT>;
+		};
+		gpio_sochot_odl: sochot_odl {
+			gpios = <&gpio9 6 GPIO_INPUT>;
+		};
+		gpio_soc_pwrok: soc_pwrok {
+			gpios = <&gpioa 5 GPIO_OUTPUT>;
+		};
+		gpio_sys_pwrok: sys_pwrok {
+			gpios = <&gpiob 0 GPIO_OUTPUT>;
+		};
+		gpio_sys_rst_odl: sys_rst_odl {
+			gpios = <&gpioc 5 GPIO_INPUT>;
+		};
+		gpio_sys_slp_s0ix_3v3_l: sys_slp_s0ix_3v3_l {
+			gpios = <&gpiod 5 GPIO_INPUT>;
+		};
+		gpio_tablet_mode_l: tablet_mode_l {
+			gpios = <&gpio9 5 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_TABLET_MODE_L";
+		};
+		gpio_usb_c0_bc12_int_odl: usb_c0_bc12_int_odl {
+			gpios = <&gpioc 6 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C0_BC12_INT_ODL";
+		};
+		gpio_usb_c0_ppc_int_odl: usb_c0_ppc_int_odl {
+			gpios = <&gpio6 2 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C0_PPC_INT_ODL";
+		};
+		gpio_usb_c0_rt_3p3_sx_en: usb_c0_rt_3p3_sx_en {
+			gpios = <&gpio0 3 GPIO_ODR_LOW>;
+		};
+		gpio_usb_c0_rt_int_odl: usb_c0_rt_int_odl {
+			gpios = <&gpioa 0 GPIO_INPUT>;
+		};
+		gpio_usb_c0_tcpc_int_odl: usb_c0_tcpc_int_odl {
+			gpios = <&gpioe 0 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_USB_C0_TCPC_INT_ODL";
+		};
+		gpio_usb_c0_tcpc_rst_odl: usb_c0_tcpc_rst_odl {
+			gpios = <&gpio6 7 GPIO_ODR_HIGH>;
+		};
+		gpio_usb_c1_bc12_int_odl: usb_c1_bc12_int_odl {
+			gpios = <&gpio5 0 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C1_BC12_INT_ODL";
+		};
+		gpio_usb_c1_frs_en: usb_c1_frs_en {
+			gpios = <&gpio8 3 GPIO_ODR_HIGH>;
+		};
+		gpio_usb_c1_ppc_int_odl: usb_c1_ppc_int_odl {
+			gpios = <&gpiof 5 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C1_PPC_INT_ODL";
+		};
+		gpio_usb_c1_rst_odl: usb_c1_rst_odl {
+			gpios = <&gpio3 7 GPIO_ODR_LOW>;
+		};
+		gpio_usb_c1_rt_int_odl: usb_c1_rt_int_odl {
+			gpios = <&gpio7 2 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_usb_c1_rt_rst_r_odl: usb_c1_rt_rst_r_odl {
+			gpios = <&gpio7 4 GPIO_ODR_HIGH>;
+		};
+		gpio_usb_c1_tcpc_int_odl: usb_c1_tcpc_int_odl {
+			gpios = <&gpio3 4 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_USB_C1_TCPC_INT_ODL";
+		};
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		i2c_ec_i2c_sensor_scl_r: ec_i2c_sensor_scl_r {
+			i2c-port = <&i2c0_0>;
+			enum-names = "I2C_PORT_SENSOR";
+		};
+		i2c_ec_i2c_usb_c0_tcp: ec_i2c_usb_c0_tcp {
+			i2c-port = <&i2c1_0>;
+			enum-names = "I2C_PORT_USB_C0_TCPC";
+		};
+		i2c_ec_i2c_usb_c0_ppc_b: ec_i2c_usb_c0_ppc_b {
+			i2c-port = <&i2c2_0>;
+			enum-names = "I2C_PORT_PPC0";
+		};
+		i2c_ec_i2c_usb_c0_rt: ec_i2c_usb_c0_rt {
+			i2c-port = <&i2c3_0>;
+			enum-names = "I2C_PORT_USB_C0_RT";
+		};
+		i2c_ec_i2c_usb_c1_tcp: ec_i2c_usb_c1_tcp {
+			i2c-port = <&i2c4_1>;
+			enum-names = "I2C_PORT_USB_C1_TCPC";
+		};
+		i2c_ec_i2c_bat: ec_i2c_bat {
+			i2c-port = <&i2c5_0>;
+			enum-names = "I2C_PORT_BATTERY";
+		};
+		i2c_ec_i2c_usb_c1_mix: ec_i2c_usb_c1_mix {
+			i2c-port = <&i2c6_1>;
+			enum-names = "I2C_PORT_USB_1_MIX";
+		};
+		i2c_ec_i2c_mi: ec_i2c_mi {
+			i2c-port = <&i2c7_0>;
+			enum-names = "I2C_PORT_EEPROM";
+		};
+	};
+};
+
+&adc0 {
+	status = "okay";
+};
+
+&i2c0_0 {
+	status = "okay";
+};
+
+&i2c1_0 {
+	status = "okay";
+};
+
+&i2c2_0 {
+	status = "okay";
+};
+
+&i2c3_0 {
+	status = "okay";
+};
+
+&i2c4_1 {
+	status = "okay";
+};
+
+&i2c5_0 {
+	status = "okay";
+};
+
+&i2c6_1 {
+	status = "okay";
+};
+
+&i2c7_0 {
+	status = "okay";
+};
+
+&i2c_ctrl0 {
+	status = "okay";
+};
+
+&i2c_ctrl1 {
+	status = "okay";
+};
+
+&i2c_ctrl2 {
+	status = "okay";
+};
+
+&i2c_ctrl3 {
+	status = "okay";
+};
+
+&i2c_ctrl4 {
+	status = "okay";
+};
+
+&i2c_ctrl5 {
+	status = "okay";
+};
+
+&i2c_ctrl6 {
+	status = "okay";
+};
+
+&i2c_ctrl7 {
+	status = "okay";
+};
diff --git a/zephyr/program/rex/gpio.csv b/zephyr/program/rex/gpio.csv
new file mode 100644
index 0000000000..26f09181ee
--- /dev/null
+++ b/zephyr/program/rex/gpio.csv
@@ -0,0 +1,125 @@
+Signal Name,Pin Number,Type,Enum
+ESPI_SOC_IO0,H1,OTHER,
+ESPI_SOC_IO1,J1,OTHER,
+ESPI_SOC_IO2,K1,OTHER,
+ESPI_SOC_IO3,L1,OTHER,
+ESPI_SOC_CS0_L,L2,OTHER,
+ESPI_SOC_RESET_L,K3,OTHER,
+ESPI_SOC_CLK,M1,OTHER,
+ESPI_SOC_ALERT_L_R,L3,OTHER,
+USB_C1_BC12_INT_ODL,G10,INPUT,GPIO_USB_C1_BC12_INT_ODL
+EC_IMU_INT_R_L,M2,INPUT_PU,
+EC_VOLDN_BTN_ODL,E11,INPUT_PU,GPIO_VOLUME_DOWN_L
+TABLET_MODE_L,M12,INPUT_PU,GPIO_TABLET_MODE_L
+SOCHOT_ODL,G12,INPUT,
+EC_VOLUP_BTN_ODL,L10,INPUT_PU,GPIO_VOLUME_UP_L
+USB_C0_RT_INT_ODL,G11,INPUT,
+EC_WP_L,L12,INPUT_L,
+EC_BATT_PRES_ODL,K12,INPUT,GPIO_BATT_PRES_ODL
+SOC_PWROK,K11,OUTPUT,
+EC_SOC_RSMRST_L,F11,OUTPUT,
+CPU_C10_GATE_L,J11,INPUT,
+SYS_PWROK,L11,OUTPUT,
+EC_SPARE_GPIO94,M11,OUTPUT,
+EC_SPARE_GPIOA2,F12,OUTPUT,
+EC_SPARE_GPIOA4,H11,OUTPUT,
+EC_ACCEL_INT_R_L,M7,INPUT,
+TEMP_SENSOR_2,E3,ADC,ADC_TEMP_SENSOR_2_AMBIENT
+TEMP_SENSOR_1,F2,ADC,ADC_TEMP_SENSOR_1_DDR_SOC
+TEMP_SENSOR_4,F3,ADC,ADC_TEMP_SENSOR_4_WWAN
+TEMP_SENSOR_3,G3,ADC,ADC_TEMP_SENSOR_3_CHARGER
+SLP_S3_LS_L,C2,INPUT,
+IMVP92_VRRDY_OD,E2,INPUT,
+EC_PROCHOT_IN_L,D2,INPUT,
+EC_SPARE_GPIO42,D3,OUTPUT,
+USB_C0_RT_3P3_SX_EN,D9,OUTPUT_ODL,
+USB_C1_RST_ODL,C1,OUTPUT_ODL,
+EN_PP5000_FAN,K4,OUTPUT,
+EC_PROCHOT_ODL,J2,OUTPUT_ODR,
+USB_C0_TCPC_RST_ODL,J3,OUTPUT_ODR,
+EC_SOC_INT_ODL,J4,OUTPUT_ODL,GPIO_EC_INT_L
+USB_C1_RT_RST_R_ODL,H5,OUTPUT_ODR,
+EC_GSC_PACKET_MODE,J6,OUTPUT,GPIO_PACKET_MODE_EN
+EC_SOC_RTCRST,J5,OUTPUT_ODR,
+USB_C1_FRS_EN,D7,OUTPUT_ODR,
+EN_S5_RAILS,L9,OUTPUT_ODR,GPIO_TEMP_SENSOR_POWER
+EC_SOC_WAKE_R_ODL,H8,OUTPUT_ODL,
+EC_SOC_PWR_BTN_ODL,H9,OUTPUT_ODL,GPIO_PCH_PWRBTN_L
+SYS_RST_ODL,H7,INPUT,
+EC_EDP_BL_EN,E10,OUTPUT,GPIO_ENABLE_BACKLIGHT
+SYS_SLP_S0IX_3V3_L,A10,INPUT,
+SEQ_EC_RSMRST_ODL,A11,INPUT,
+CCD_MODE_ODL,A12,INPUT,GPIO_CCD_MODE_ODL
+EC_KB_BL_EN_L,J9,OUTPUT,
+EC_SHDF_ESPI_L,H3,OTHER,
+USB_C1_TCPC_INT_ODL,B2,INPUT_L,GPIO_USB_C1_TCPC_INT_ODL
+EC_FAN_TACH,E5,TACH,
+USB_C0_PPC_INT_ODL,H2,INPUT,GPIO_USB_C0_PPC_INT_ODL
+USB_C1_RT_INT_ODL,M4,INPUT_PU,
+USB_C0_BC12_INT_ODL,D10,INPUT,GPIO_USB_C0_BC12_INT_ODL
+EC_ALS_RGB_INT_R_L,A9,INPUT_PU,
+USB_C0_TCPC_INT_ODL,F4,INPUT_L,GPIO_USB_C0_TCPC_INT_ODL
+SEQ_EC_ALL_SYS_PG_OD,E9,INPUT,
+USB_C1_PPC_INT_ODL,E8,INPUT,GPIO_USB_C1_PPC_INT_ODL
+EC_I2C_SENSOR_SDA_R,B12,I2C_DATA,
+EC_I2C_SENSOR_SCL_R,C12,I2C_CLOCK,I2C_PORT_SENSOR
+EC_I2C_USB_C0_TCPC_SDA,K7,I2C_DATA,
+EC_I2C_USB_C0_TCPC_SCL,K8,I2C_CLOCK,I2C_PORT_USB_C0_TCPC
+EC_I2C_USB_C0_PPC_BC_SDA,K9,I2C_DATA,
+EC_I2C_USB_C0_PPC_BC_SCL,L8,I2C_CLOCK,I2C_PORT_PPC0
+EC_I2C_USB_C0_RT_SDA,F9,I2C_DATA,
+EC_I2C_USB_C0_RT_SCL,F8,I2C_CLOCK,I2C_PORT_USB_C0_RT
+EC_I2C_USB_C1_TCPC_SDA,F6,I2C_DATA,
+EC_I2C_USB_C1_TCPC_SCL,F5,I2C_CLOCK,I2C_PORT_USB_C1_TCPC
+EC_I2C_BAT_SCL,D5,I2C_CLOCK,I2C_PORT_BATTERY
+EC_I2C_BAT_SDA,D4,I2C_DATA,
+EC_I2C_USB_C1_MIX_SDA,L7,I2C_DATA,
+EC_I2C_USB_C1_MIX_SCL,L6,I2C_CLOCK,I2C_PORT_USB_1_MIX
+EC_I2C_MISC_SDA,K10,I2C_DATA,
+EC_I2C_MISC_SCL,J10,I2C_CLOCK,I2C_PORT_EEPROM
+KSI_07,C5,OTHER,
+KSI_06,C4,OTHER,
+KSI_05,C3,OTHER,
+KSI_04,B4,OTHER,
+EC_KSI_03,B3,OTHER,
+EC_KSI_02,A4,OTHER,
+KSI_01,A3,OTHER,
+EC_KSI_00,A2,OTHER,
+KSO_13,D11,OTHER,
+KSO_12,C11,OTHER,
+KSO_11,B10,OTHER,
+KSO_10,B11,OTHER,
+KSO_09,C10,OTHER,
+KSO_08,C9,OTHER,
+KSO_05,C6,OTHER,
+KSO_04,C7,OTHER,
+KSO_03,B8,OTHER,
+EC_KSO_02_INV,B7,OUTPUT_L,
+KSO_01,B6,OTHER,
+KSO_00,B5,OTHER,
+KSO_14,D6,OTHER,
+EC_KSO_07_JEN_L,B9,OTHER,
+EC_KSO_06_GP_SEL_L,C8,OTHER,
+LED_4_L,G6,OUTPUT,
+EC_KB_BL_PWM,K5,PWM,GPIO_EN_KEYBOARD_BACKLIGHT
+FAN_PWM,J7,PWM,
+LED_3_L,H10,OUTPUT,
+LED_2_L,G9,OUTPUT,
+LED_1_L,G8,OUTPUT,
+EC_RST_R_ODL,K6,INPUT,
+UART_GSC_DBG_TX_EC_RX_R,G4,OTHER,
+UART_GSC_DBG_RX_EC_TX_R,H4,OTHER,
+EC_SPARE_GPIO66,G2,OUTPUT,
+EC_CBI_WP,G5,OUTPUT,
+EC_SPARE_GPIOB1,D8,OUTPUT,
+EC_SPARE_GPIOC7,F10,OUTPUT,
+EC_SPARE_GPO32,E4,OUTPUT,
+EC_SPARE_GPO35,K2,OUTPUT,
+EC_32KXIN,L5,INPUT,
+EC_32KXOUT,M5,OUTPUT,
+ACOK_OD,E7,INPUT,GPIO_AC_PRESENT
+EC_SPARE_GPIO01,E6,INPUT_PU,
+EC_MECH_PWR_BTN_L,F7,INPUT,GPIO_POWER_BUTTON_L
+LID_OPEN,G7,INPUT,GPIO_LID_OPEN
+EN_Z1_RAILS,J8,OUTPUT,
+EN_PP5000_USBA_R,H6,OUTPUT,
diff --git a/zephyr/program/rex/include/gpio_map.h b/zephyr/program/rex/include/gpio_map.h
new file mode 100644
index 0000000000..01cbc44396
--- /dev/null
+++ b/zephyr/program/rex/include/gpio_map.h
@@ -0,0 +1,9 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __ZEPHYR_GPIO_MAP_H
+#define __ZEPHYR_GPIO_MAP_H
+
+#endif /* __ZEPHYR_GPIO_MAP_H */
diff --git a/zephyr/program/rex/include/usbc_config.h b/zephyr/program/rex/include/usbc_config.h
new file mode 100644
index 0000000000..5e5fe6c708
--- /dev/null
+++ b/zephyr/program/rex/include/usbc_config.h
@@ -0,0 +1,17 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __ZEPHYR_USBC_CONFIG_H
+#define __ZEPHYR_USBC_CONFIG_H
+
+#include "usb_mux.h"
+
+/* USB-C ports */
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
+BUILD_ASSERT(USBC_PORT_COUNT == CONFIG_USB_PD_PORT_MAX_COUNT);
+
+void reset_nct38xx_port(int port);
+
+#endif /* __ZEPHYR_USBC_CONFIG_H */
diff --git a/zephyr/program/rex/interrupts.dtsi b/zephyr/program/rex/interrupts.dtsi
new file mode 100644
index 0000000000..0f1100b18d
--- /dev/null
+++ b/zephyr/program/rex/interrupts.dtsi
@@ -0,0 +1,79 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_ac_present: ac_present {
+			irq-pin = <&gpio_acok_od>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "extpower_interrupt";
+		};
+		int_power_button: power_button {
+			irq-pin = <&gpio_ec_mech_pwr_btn_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_button_interrupt";
+		};
+		int_lid_open: lid_open {
+			irq-pin = <&gpio_lid_open>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "lid_interrupt";
+		};
+		int_usb_c0_sbu_fault: c0_sbu_fault {
+			irq-pin = <&ioex_usb_c0_sbu_fault_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "sbu_fault_interrupt";
+		};
+		int_usb_c0_ppc: usb_c0_ppc {
+			irq-pin = <&gpio_usb_c0_ppc_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "ppc_interrupt";
+		};
+		int_usb_c0_bc12: usb_c0_bc12 {
+			irq-pin = <&gpio_usb_c0_bc12_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "bc12_interrupt";
+		};
+		int_usb_c1_ppc: usb_c1_ppc {
+			irq-pin = <&gpio_usb_c1_ppc_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "ppc_interrupt";
+		};
+		int_usb_c1_bc12: usb_c1_bc12 {
+			irq-pin = <&gpio_usb_c1_bc12_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "bc12_interrupt";
+		};
+		int_imu: ec_imu {
+			irq-pin = <&gpio_ec_imu_int_r_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "lsm6dso_interrupt";
+		};
+		int_als_rgb: ec_als_rgb {
+			irq-pin = <&gpio_ec_als_rgb_int_r_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "tcs3400_interrupt";
+		};
+		int_accel: ec_accel {
+			irq-pin = <&gpio_ec_accel_int_r_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "lis2dw12_interrupt";
+		};
+		int_volume_up: volume_up {
+			irq-pin = <&gpio_ec_volup_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+		int_volume_down: volume_down {
+			irq-pin = <&gpio_ec_voldn_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+	};
+};
+
+/* Required node label that doesn't is named differently on Rex */
+gpio_ec_pch_wake_odl: &gpio_ec_soc_wake_r_odl {};
diff --git a/zephyr/program/rex/karis/CMakeLists.txt b/zephyr/program/rex/karis/CMakeLists.txt
new file mode 100644
index 0000000000..4822b7c74c
--- /dev/null
+++ b/zephyr/program/rex/karis/CMakeLists.txt
@@ -0,0 +1,8 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cros_ec_library_include_directories_ifdef(CONFIG_BOARD_REX include)
+zephyr_include_directories("include")
+zephyr_library_sources("src/usb_mux_config.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/usbc_config.c")
diff --git a/zephyr/program/rex/karis/cbi.dtsi b/zephyr/program/rex/karis/cbi.dtsi
new file mode 100644
index 0000000000..6e9e35cf48
--- /dev/null
+++ b/zephyr/program/rex/karis/cbi.dtsi
@@ -0,0 +1,51 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	rex-fw-config {
+		compatible = "cros-ec,cbi-fw-config";
+
+		/*
+		 * FW_CONFIG field to enable USB DB.
+		 */
+		usb-db {
+			enum-name = "FW_USB_DB";
+			start = <12>;
+			size = <3>;
+
+			io-db-unknown {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_USB_DB_NOT_CONNECTED";
+				value = <0>;
+			};
+			io-db-usb3 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_USB_DB_USB3";
+				value = <1>;
+				default;
+			};
+			io-db-usb4-kb8010 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_USB_DB_USB4_KB8010";
+				value = <2>;
+			};
+			io-db-usb4-anx7452 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_USB_DB_USB4_ANX7452";
+				value = <3>;
+			};
+			io-db-usb4-hayden {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_USB_DB_USB4_HB";
+				value = <4>;
+			};
+			io-db-usb4-anx7452v2 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_USB_DB_USB4_ANX7452_V2";
+				value = <5>;
+			};
+		};
+	};
+};
diff --git a/zephyr/program/rex/karis/i2c.dtsi b/zephyr/program/rex/karis/i2c.dtsi
new file mode 100644
index 0000000000..c6b9db71ea
--- /dev/null
+++ b/zephyr/program/rex/karis/i2c.dtsi
@@ -0,0 +1,22 @@
+&i2c4_1 {
+	tcpc_ps8815_port1: ps8xxx@b {
+		compatible = "parade,ps8xxx";
+		reg = <0xb>;
+		tcpc-flags = <(
+			TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V |
+			TCPC_FLAGS_CONTROL_VCONN |
+			TCPC_FLAGS_CONTROL_FRS)>;
+		/* a duplicate of the <&gpio_usb_c1_tcpc_int_odl> node in
+		 * "named-gpios". This is the Zephyr preferred style,
+		 * the "named-gpios" node will be dealt with at a later date.
+		 */
+		irq-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
+		/* a duplicate of the <&gpio_usb_c1_rt_rst_r_odl> node in
+		 * "named-gpios". This is the Zephyr preferred style,
+		 * the "named-gpios" node will be dealt with at a later date.
+		 */
+		rst-gpios = <&gpio7 4 0>;
+		is-alt;
+	};
+};
diff --git a/zephyr/program/rex/karis/include/usb_mux_config.h b/zephyr/program/rex/karis/include/usb_mux_config.h
new file mode 100644
index 0000000000..b43d96f209
--- /dev/null
+++ b/zephyr/program/rex/karis/include/usb_mux_config.h
@@ -0,0 +1,11 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __ZEPHYR_USB_MUX_CONFIG_H
+#define __ZEPHYR_USB_MUX_CONFIG_H
+
+extern uint32_t usb_db_type;
+
+#endif /* __ZEPHYR_USB_MUX_CONFIG_H */
diff --git a/zephyr/program/rex/karis/led_pins.dtsi b/zephyr/program/rex/karis/led_pins.dtsi
new file mode 100644
index 0000000000..7a4ff16273
--- /dev/null
+++ b/zephyr/program/rex/karis/led_pins.dtsi
@@ -0,0 +1,55 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	gpio-led-pins {
+		compatible = "cros-ec,gpio-led-pins";
+
+		left_led: left-led {
+			led-id = "EC_LED_ID_LEFT_LED";
+			led-pins = <&gpio_led_1_l &gpio_led_2_l>;
+			color_off_left: color-off-left {
+				led-color = "LED_OFF";
+				led-values = <1 1>;
+			};
+
+			color_amber_left: color-amber-left {
+				led-color = "LED_AMBER";
+				br-color = "EC_LED_COLOR_AMBER";
+				led-values = <0 1>;
+			};
+
+			color_white_left: color-white-left {
+				led-color = "LED_WHITE";
+				br-color = "EC_LED_COLOR_WHITE";
+				led-values = <1 0>;
+			};
+		};
+
+		right_led: right-led {
+			led-id = "EC_LED_ID_RIGHT_LED";
+			led-pins = <&gpio_led_3_l &gpio_led_4_l>;
+
+			color_off_right: color-off-right {
+				led-color = "LED_OFF";
+				led-values = <1 1>;
+			};
+
+
+			color_amber_right: color-amber-right {
+				led-color = "LED_AMBER";
+				br-color = "EC_LED_COLOR_AMBER";
+				led-values = <0 1>;
+			};
+
+
+			color_white_right: color-white-right {
+				led-color = "LED_WHITE";
+				br-color = "EC_LED_COLOR_WHITE";
+				led-values = <1 0>;
+			};
+		};
+	};
+};
diff --git a/zephyr/program/rex/karis/led_policy.dtsi b/zephyr/program/rex/karis/led_policy.dtsi
new file mode 100644
index 0000000000..ef34d23e3c
--- /dev/null
+++ b/zephyr/program/rex/karis/led_policy.dtsi
@@ -0,0 +1,205 @@
+#include <dt-bindings/battery.h>
+
+/ {
+	led-colors {
+		compatible = "cros-ec,led-policy";
+
+		power-state-near-full-left {
+			charge-state = "LED_PWRS_CHARGE_NEAR_FULL";
+			charge-port = <0>; /* Left port */
+
+			/* Turn off the right LED */
+			color-0 {
+				led-color = <&color_off_right>;
+			};
+			/* Left LED to White */
+			color-1 {
+				led-color = <&color_white_left>;
+			};
+		};
+
+		power-state-near-full-right {
+			charge-state = "LED_PWRS_CHARGE_NEAR_FULL";
+			charge-port = <1>; /* Right port */
+
+			/* Turn off the left LED */
+			color-0 {
+				led-color = <&color_off_left>;
+			};
+			/* Right LED to White */
+			color-1 {
+				led-color = <&color_white_right>;
+			};
+		};
+
+		power-state-high-left {
+			charge-state = "LED_PWRS_CHARGE";
+			/* Battery percent range 99..100 */
+			batt-lvl = <99 100>;
+
+			charge-port = <0>; /* Left port */
+
+			/* Turn off the right LED */
+			color-0 {
+				led-color = <&color_off_right>;
+			};
+			/* Left LED to White */
+			color-1 {
+				led-color = <&color_white_left>;
+			};
+		};
+
+		power-state-high-right {
+			charge-state = "LED_PWRS_CHARGE";
+			/* Battery percent range 99..100 */
+			batt-lvl = <99 100>;
+			charge-port = <1>; /* Right port */
+
+			/* Turn off the left LED */
+			color-0 {
+				led-color = <&color_off_left>;
+			};
+			/* Right LED to White */
+			color-1 {
+				led-color = <&color_white_right>;
+			};
+		};
+
+		power-state-charge-left {
+			charge-state = "LED_PWRS_CHARGE";
+			/* Battery percent range 0..98 */
+			batt-lvl = <0 98>;
+			charge-port = <0>; /* Left port */
+
+			/* Left LED to Amber */
+			color-0 {
+				led-color = <&color_amber_left>;
+			};
+			/* Turn off the right LED */
+			color-1 {
+				led-color = <&color_off_right>;
+			};
+		};
+
+		power-state-charge-right {
+			charge-state = "LED_PWRS_CHARGE";
+			charge-port = <1>; /* Right port */
+			/* Battery percent range 0..98 */
+			batt-lvl = <0 98>;
+
+			/* Turn off the left LED */
+			color-0 {
+				led-color = <&color_off_left>;
+			};
+			/* Right LED to Amber */
+			color-1 {
+				led-color = <&color_amber_right>;
+			};
+		};
+
+		power-state-discharge {
+			charge-state = "LED_PWRS_DISCHARGE";
+			/* Battery percent range (> Low, <= Full) */
+			batt-lvl = <(BATTERY_LEVEL_LOW + 1) BATTERY_LEVEL_FULL>;
+
+			/* Turn off both LEDs LED */
+			color-0 {
+				led-color = <&color_off_left>;
+			};
+			color-1 {
+				led-color = <&color_off_right>;
+			};
+		};
+
+		power-state-discharge-low {
+			charge-state = "LED_PWRS_DISCHARGE";
+			/* Battery percent range (>= Empty, <= Low) */
+			batt-lvl = <BATTERY_LEVEL_EMPTY BATTERY_LEVEL_LOW>;
+
+			/* Blink both LEDs amber at 0.5 Hz */
+			color-0 {
+				led-color = <&color_amber_left>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_amber_right>;
+				period-ms = <1000>;
+			};
+			color-2 {
+				led-color = <&color_off_left>;
+				period-ms = <1000>;
+			};
+			color-3 {
+				led-color = <&color_off_right>;
+				period-ms = <1000>;
+			};
+		};
+
+		power-state-idle {
+			charge-state = "LED_PWRS_IDLE";
+
+			/* Blink both LEDs amber at 0.5 Hz */
+			color-0 {
+				led-color = <&color_amber_left>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_amber_right>;
+				period-ms = <1000>;
+			};
+			color-2 {
+				led-color = <&color_white_left>;
+				period-ms = <1000>;
+			};
+			color-3 {
+				led-color = <&color_white_right>;
+				period-ms = <1000>;
+			};
+		};
+
+		power-state-forced-idle {
+			charge-state = "LED_PWRS_FORCED_IDLE";
+
+			/* Blink both LEDs amber at 2 Hz */
+			color-0 {
+				led-color = <&color_amber_left>;
+				period-ms = <250>;
+			};
+			color-1 {
+				led-color = <&color_amber_right>;
+				period-ms = <250>;
+			};
+			color-2 {
+				led-color = <&color_white_left>;
+				period-ms = <250>;
+			};
+			color-3 {
+				led-color = <&color_white_right>;
+				period-ms = <250>;
+			};
+		};
+
+		power-state-error {
+			charge-state = "LED_PWRS_ERROR";
+
+			/* Blink both LEDs amber at 2 Hz */
+			color-0 {
+				led-color = <&color_amber_left>;
+				period-ms = <250>;
+			};
+			color-1 {
+				led-color = <&color_amber_right>;
+				period-ms = <250>;
+			};
+			color-2 {
+				led-color = <&color_off_left>;
+				period-ms = <250>;
+			};
+			color-3 {
+				led-color = <&color_off_right>;
+				period-ms = <250>;
+			};
+		};
+
+	};
+};
diff --git a/zephyr/program/rex/karis/project.conf b/zephyr/program/rex/karis/project.conf
new file mode 100644
index 0000000000..ab8ece74d8
--- /dev/null
+++ b/zephyr/program/rex/karis/project.conf
@@ -0,0 +1,13 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Rex-NPCX9 reference-board-specific Kconfig settings.
+CONFIG_BOARD_REX=y
+
+# Ensure recovery key combination (esc+refresh+power) is reliable: b/260555509
+CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI2=y
+
+# Some boards detect a false VBUS reverse current event
+# First investigated on taniks (b/237468526)
+CONFIG_PLATFORM_EC_USBC_NX20P348X_RCP_5VSRC_MASK_ENABLE=y
diff --git a/zephyr/program/rex/karis/project.overlay b/zephyr/program/rex/karis/project.overlay
new file mode 100644
index 0000000000..aaa8c2c3a9
--- /dev/null
+++ b/zephyr/program/rex/karis/project.overlay
@@ -0,0 +1,22 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Rex program common DTSI includes */
+#include "../battery.dtsi"
+#include "../fan.dtsi"
+#include "../generated.dtsi"
+#include "../interrupts.dtsi"
+#include "../keyboard.dtsi"
+#include "../motionsense.dtsi"
+#include "../power_signals.dtsi"
+#include "../rex.dtsi"
+#include "../temp_sensors.dtsi"
+#include "../usbc.dtsi"
+
+/* Rex project DTS includes */
+#include "cbi.dtsi"
+#include "i2c.dtsi"
+#include "led_pins.dtsi"
+#include "led_policy.dtsi"
diff --git a/zephyr/program/rex/karis/src/usb_mux_config.c b/zephyr/program/rex/karis/src/usb_mux_config.c
new file mode 100644
index 0000000000..2c643ea68e
--- /dev/null
+++ b/zephyr/program/rex/karis/src/usb_mux_config.c
@@ -0,0 +1,149 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Rex board-specific USB-C mux configuration */
+
+#include "console.h"
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+#include "hooks.h"
+#include "usb_mux.h"
+#include "usb_mux_config.h"
+#include "usb_pd.h"
+#include "usbc/ppc.h"
+#include "usbc/tcpci.h"
+#include "usbc/usb_muxes.h"
+#include "usbc_config.h"
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/logging/log.h>
+
+#include <dt-bindings/gpio_defines.h>
+
+#ifdef CONFIG_ZTEST
+
+#undef USB_MUX_ENABLE_ALTERNATIVE
+#define USB_MUX_ENABLE_ALTERNATIVE(x)
+
+#undef TCPC_ENABLE_ALTERNATE_BY_NODELABEL
+#define TCPC_ENABLE_ALTERNATE_BY_NODELABEL(x, y)
+
+#undef PPC_ENABLE_ALTERNATE_BY_NODELABEL
+#define PPC_ENABLE_ALTERNATE_BY_NODELABEL(x, y)
+
+#endif /* CONFIG_ZTEST */
+
+LOG_MODULE_DECLARE(rex, CONFIG_REX_LOG_LEVEL);
+
+uint32_t usb_db_type;
+
+static int gpio_unused(const struct gpio_dt_spec *spec)
+{
+	return gpio_pin_configure(spec->port, spec->pin, GPIO_INPUT_PULL_UP);
+}
+
+static void setup_runtime_gpios(void)
+{
+	int ret;
+
+	ret = cros_cbi_get_fw_config(FW_USB_DB, &usb_db_type);
+	if (ret != EC_SUCCESS) {
+		LOG_INF("Failed to get FW_USB_DB from CBI");
+		usb_db_type = FW_USB_DB_NOT_CONNECTED;
+	}
+
+	switch (usb_db_type) {
+	case FW_USB_DB_USB3:
+		gpio_unused(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_rst_odl));
+		gpio_unused(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_rt_int_odl));
+		gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(ps_usb_c1_rt_rst_odl),
+				      GPIO_ODR_HIGH | GPIO_ACTIVE_LOW);
+		gpio_unused(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_frs_en));
+		break;
+
+	case FW_USB_DB_USB4_KB8010:
+		gpio_unused(GPIO_DT_FROM_ALIAS(kb_usb_c1_rst_odl));
+		gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(kb_usb_c1_dp_mode),
+				      GPIO_ODR_HIGH);
+		gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(kb_usb_c1_rt_rst_odl),
+				      GPIO_ODR_HIGH);
+		gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(kb_usb_c1_frs_alert),
+				      GPIO_INPUT);
+		break;
+
+	case FW_USB_DB_USB4_ANX7452:
+	case FW_USB_DB_USB4_ANX7452_V2:
+		gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(anx_usb_c1_rt_hpd_in),
+				      GPIO_OUTPUT_LOW);
+		gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(anx_usb_c1_rt_dp_en),
+				      GPIO_OUTPUT_LOW);
+		gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(anx_usb_c1_rt_usb_en),
+				      GPIO_OUTPUT_LOW);
+		gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(anx_usb_c1_frs_en),
+				      GPIO_OUTPUT_LOW);
+		break;
+
+	default:
+		/* GPIO37 */
+		gpio_unused(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_rst_odl));
+		/* GPIO72 */
+		gpio_unused(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_rt_int_odl));
+		/* GPIO74 */
+		gpio_unused(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_rt_rst_r_odl));
+		/* GPIO83 */
+		gpio_unused(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_frs_en));
+		break;
+	}
+}
+DECLARE_HOOK(HOOK_INIT, setup_runtime_gpios, HOOK_PRIO_FIRST);
+
+static void setup_usb_db(void)
+{
+	switch (usb_db_type) {
+	case FW_USB_DB_NOT_CONNECTED:
+		LOG_INF("USB DB: not connected");
+		break;
+	case FW_USB_DB_USB3:
+		LOG_INF("USB DB: Setting USB3 mux");
+		USB_MUX_ENABLE_ALTERNATIVE(usb_mux_chain_ps8815_port1);
+		TCPC_ENABLE_ALTERNATE_BY_NODELABEL(USBC_PORT_C1,
+						   tcpc_ps8815_port1);
+		PPC_ENABLE_ALTERNATE_BY_NODELABEL(USBC_PORT_C1,
+						  ppc_nx20p_port1);
+		break;
+	case FW_USB_DB_USB4_ANX7452:
+	case FW_USB_DB_USB4_ANX7452_V2:
+		LOG_INF("USB DB: Setting ANX7452 mux");
+		USB_MUX_ENABLE_ALTERNATIVE(usb_mux_chain_anx7452_port1);
+		TCPC_ENABLE_ALTERNATE_BY_NODELABEL(USBC_PORT_C1,
+						   tcpc_rt1716_port1);
+		PPC_ENABLE_ALTERNATE_BY_NODELABEL(USBC_PORT_C1, ppc_syv_port1);
+		break;
+	case FW_USB_DB_USB4_KB8010:
+		LOG_INF("USB DB: Setting KB8010 mux");
+		USB_MUX_ENABLE_ALTERNATIVE(usb_mux_chain_kb8010_port1);
+		TCPC_ENABLE_ALTERNATE_BY_NODELABEL(USBC_PORT_C1,
+						   tcpc_rt1716_port1);
+		PPC_ENABLE_ALTERNATE_BY_NODELABEL(USBC_PORT_C1,
+						  ppc_ktu1125_port1);
+		break;
+	default:
+		LOG_INF("USB DB: No known USB DB found");
+	}
+}
+DECLARE_HOOK(HOOK_INIT, setup_usb_db, HOOK_PRIO_POST_I2C);
+
+__override uint8_t board_get_usb_pd_port_count(void)
+{
+	switch (usb_db_type) {
+	case FW_USB_DB_USB3:
+	case FW_USB_DB_USB4_ANX7452:
+	case FW_USB_DB_USB4_ANX7452_V2:
+	case FW_USB_DB_USB4_KB8010:
+		return 2;
+	default:
+		return 1;
+	}
+}
diff --git a/zephyr/program/rex/karis/src/usbc_config.c b/zephyr/program/rex/karis/src/usbc_config.c
new file mode 100644
index 0000000000..711258a5c9
--- /dev/null
+++ b/zephyr/program/rex/karis/src/usbc_config.c
@@ -0,0 +1,64 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cros_cbi.h"
+#include "driver/ppc/ktu1125_public.h"
+#include "driver/ppc/nx20p348x.h"
+#include "driver/tcpm/ps8xxx_public.h"
+#include "ppc/syv682x_public.h"
+#include "system.h"
+#include "usb_mux_config.h"
+#include "usbc_config.h"
+
+void board_reset_pd_mcu(void)
+{
+	/* Reset TCPC0 */
+	reset_nct38xx_port(USBC_PORT_C0);
+
+	/* Reset TCPC1 */
+	if (usb_db_type == FW_USB_DB_USB3 && tcpc_config[1].rst_gpio.port) {
+		gpio_pin_set_dt(&tcpc_config[1].rst_gpio, 1);
+		msleep(PS8XXX_RESET_DELAY_MS);
+		gpio_pin_set_dt(&tcpc_config[1].rst_gpio, 0);
+		msleep(PS8815_FW_INIT_DELAY_MS);
+	}
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_PPC_INT_ODL:
+		switch (usb_db_type) {
+		case FW_USB_DB_USB3:
+			nx20p348x_interrupt(USBC_PORT_C1);
+			break;
+		case FW_USB_DB_USB4_ANX7452:
+		case FW_USB_DB_USB4_ANX7452_V2:
+			syv682x_interrupt(USBC_PORT_C1);
+			break;
+		case FW_USB_DB_USB4_KB8010:
+			ktu1125_interrupt(USBC_PORT_C1);
+			break;
+		default:
+			break;
+		}
+		break;
+	default:
+		break;
+	}
+}
+
+__override bool board_is_tbt_usb4_port(int port)
+{
+	if (port == USBC_PORT_C0)
+		return true;
+	if (port == USBC_PORT_C1 && usb_db_type != FW_USB_DB_USB3)
+		return true;
+
+	return false;
+}
diff --git a/zephyr/program/rex/keyboard.dtsi b/zephyr/program/rex/keyboard.dtsi
new file mode 100644
index 0000000000..91fad2db92
--- /dev/null
+++ b/zephyr/program/rex/keyboard.dtsi
@@ -0,0 +1,47 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	kblight {
+		compatible = "cros-ec,kblight-pwm";
+		pwms = <&pwm3 0 PWM_HZ(2400) PWM_POLARITY_NORMAL>;
+	};
+};
+
+&pwm3 {
+	status = "okay";
+	pinctrl-0 = <&pwm3_gp80>;
+	pinctrl-names = "default";
+};
+
+&cros_kb_raw {
+	status = "okay";
+	/* No KSO2 (it's inverted and implemented by GPIO) */
+	pinctrl-0 = <
+		&ksi0_gp31
+		&ksi1_gp30
+		&ksi2_gp27
+		&ksi3_gp26
+		&ksi4_gp25
+		&ksi5_gp24
+		&ksi6_gp23
+		&ksi7_gp22
+		&kso00_gp21
+		&kso01_gp20
+		&kso03_gp16
+		&kso04_gp15
+		&kso05_gp14
+		&kso06_gp13
+		&kso07_gp12
+		&kso08_gp11
+		&kso09_gp10
+		&kso10_gp07
+		&kso11_gp06
+		&kso12_gp05
+		&kso13_gp04
+		&kso14_gp82
+	>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/rex/motionsense.dtsi b/zephyr/program/rex/motionsense.dtsi
new file mode 100644
index 0000000000..6d30209a12
--- /dev/null
+++ b/zephyr/program/rex/motionsense.dtsi
@@ -0,0 +1,257 @@
+/*
+ * Copyright 2022 The ChromiumOS Authors
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <dt-bindings/motionsense/utils.h>
+
+
+/ {
+	aliases {
+		/*
+		 * motion sense's <>_INT_EVENT is handled
+		 * by alias. Using the alias, each driver creates
+		 * its own <>_INT_EVENT.
+		 */
+		lsm6dso-int = &base_accel;
+		lis2dw12-int = &lid_accel;
+		tcs3400-int = &als_clear;
+	};
+
+	/*
+	 * Declare mutexes used by sensor drivers.
+	 * A mutex node is used to create an instance of mutex_t.
+	 * A mutex node is referenced by a sensor node if the
+	 * corresponding sensor driver needs to use the
+	 * instance of the mutex.
+	 */
+	motionsense-mutex {
+		compatible = "cros-ec,motionsense-mutex";
+		mutex_lis2dw12: lis2dw12-mutex {
+		};
+
+		mutex_lsm6dso: lsm6dso-mutex {
+		};
+	};
+
+	/* Rotation matrix used by drivers. */
+	motionsense-rotation-ref {
+		compatible = "cros-ec,motionsense-rotation-ref";
+		lid_rot_ref: lid-rotation-ref {
+			mat33 = <0 1 0
+				 1 0 0
+				 0 0 (-1)>;
+		};
+		base_rot_ref: base-rotation-ref {
+			mat33 = <1 0 0
+				 0 (-1) 0
+				 0 0 (-1)>;
+		};
+	};
+
+	/*
+	 * Driver specific data. A driver-specific data can be shared with
+	 * different motion sensors while they are using the same driver.
+	 *
+	 * If a node's compatible starts with "cros-ec,accelgyro-", it is for
+	 * a common structure defined in accelgyro.h.
+	 * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for
+	 * "struct als_drv_data_t" in accelgyro.h
+	 */
+	motionsense-sensor-data {
+		lis2dw12_data: lis2dw12-drv-data {
+			compatible = "cros-ec,drvdata-lis2dw12";
+			status = "okay";
+		};
+
+		lsm6dso_accel_data: lsm6dso-accel-drv-data {
+			compatible = "cros-ec,drvdata-lsm6dso";
+			status = "okay";
+		};
+
+		lsm6dso_gyro_data: lsm6dso-gyro-drv-data {
+			compatible = "cros-ec,drvdata-lsm6dso";
+			status = "okay";
+		};
+
+		tcs_clear_data: tcs3400-clear-drv-data {
+			compatible = "cros-ec,drvdata-tcs3400-clear";
+			status = "okay";
+
+			als-drv-data {
+				compatible = "cros-ec,accelgyro-als-drv-data";
+				als-cal {
+					scale = <1>;
+					uscale = <0>;
+					offset = <0>;
+					als-channel-scale {
+					compatible =
+					"cros-ec,accelgyro-als-channel-scale";
+						k-channel-scale = <1>;
+						cover-scale = <1>;
+					};
+				};
+			};
+		};
+
+		tcs_rgb_data: tcs3400-rgb-drv-data {
+			compatible = "cros-ec,drvdata-tcs3400-rgb";
+			status = "okay";
+
+			/* node for rgb_calibration_t defined in accelgyro.h */
+			rgb_calibration {
+				compatible =
+					"cros-ec,accelgyro-rgb-calibration";
+
+				irt = <1>;
+
+				rgb-cal-x {
+					offset = <0>;
+					coeff = <0 0 0 1>;
+					als-channel-scale {
+					compatible =
+					"cros-ec,accelgyro-als-channel-scale";
+						k-channel-scale = <1>;
+						cover-scale = <1>;
+					};
+				};
+				rgb-cal-y {
+					offset = <0>;
+					coeff = <0 0 0 1>;
+					als-channel-scale {
+					compatible =
+					"cros-ec,accelgyro-als-channel-scale";
+						k-channel-scale = <1>;
+						cover-scale = <1>;
+					};
+				};
+				rgb-cal-z {
+					offset = <0>;
+					coeff = <0 0 0 1>;
+					als-channel-scale {
+					compatible =
+					"cros-ec,accelgyro-als-channel-scale";
+						k-channel-scale = <1>;
+						cover-scale = <1>;
+					};
+				};
+			};
+		};
+	};
+
+	/*
+	 * List of motion sensors that creates motion_sensors array.
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
+	 * motion sensor IDs for lid angle calculation.
+	 */
+	motionsense-sensor {
+		lid_accel: lid-accel {
+			compatible = "cros-ec,lis2dw12";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&mutex_lis2dw12>;
+			port = <&i2c_ec_i2c_sensor_scl_r>;
+			rot-standard-ref = <&lid_rot_ref>;
+			default-range = <2>;
+			drv-data = <&lis2dw12_data>;
+			i2c-spi-addr-flags = "LIS2DWL_ADDR0_FLAGS";
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_accel: base-accel {
+			compatible = "cros-ec,lsm6dso-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&mutex_lsm6dso>;
+			port = <&i2c_ec_i2c_sensor_scl_r>;
+			rot-standard-ref = <&base_rot_ref>;
+			default-range = <4>;
+			drv-data = <&lsm6dso_accel_data>;
+			i2c-spi-addr-flags = "LSM6DSO_ADDR0_FLAGS";
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+					ec-rate = <(100 * USEC_PER_MSEC)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+					ec-rate = <(100 * USEC_PER_MSEC)>;
+				};
+			};
+		};
+
+		base-gyro {
+			compatible = "cros-ec,lsm6dso-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&mutex_lsm6dso>;
+			port = <&i2c_ec_i2c_sensor_scl_r>;
+			rot-standard-ref = <&base_rot_ref>;
+			default-range = <(1000 | ROUND_UP_FLAG)>; /* dps */
+			drv-data = <&lsm6dso_gyro_data>;
+			i2c-spi-addr-flags = "LSM6DSO_ADDR0_FLAGS";
+		};
+
+		als_clear: base-als-clear {
+			compatible = "cros-ec,tcs3400-clear";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_CAMERA";
+			port = <&i2c_ec_i2c_sensor_scl_r>;
+			default-range = <0x10000>;
+			drv-data = <&tcs_clear_data>;
+			i2c-spi-addr-flags = "TCS3400_I2C_ADDR_FLAGS";
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					/* Run ALS sensor in S0 */
+					odr = <1000>;
+				};
+			};
+		};
+
+		base-als-rgb {
+			compatible = "cros-ec,tcs3400-rgb";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_CAMERA";
+			default-range = <0x10000>; /* scale = 1x, uscale = 0 */
+			drv-data = <&tcs_rgb_data>;
+		};
+	};
+
+	motionsense-sensor-info {
+		compatible = "cros-ec,motionsense-sensor-info";
+
+		/* list of entries for motion_als_sensors */
+		als-sensors = <&als_clear>;
+		/*
+		 * list of GPIO interrupts that have to
+		 * be enabled at initial stage
+		 */
+		sensor-irqs = <&int_imu &int_als_rgb &int_accel>;
+		/* list of sensors in force mode */
+		accel-force-mode-sensors = <&lid_accel &als_clear>;
+	};
+};
diff --git a/zephyr/program/rex/power_signals.dtsi b/zephyr/program/rex/power_signals.dtsi
new file mode 100644
index 0000000000..a6a8674760
--- /dev/null
+++ b/zephyr/program/rex/power_signals.dtsi
@@ -0,0 +1,152 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	chosen {
+		intel-ap-pwrseq,espi = &espi0;
+	};
+
+	common-pwrseq {
+		compatible = "intel,ap-pwrseq";
+
+		sys-pwrok-delay = <3>;
+		all-sys-pwrgd-timeout = <20>;
+	};
+
+	pwr-en-pp3300-s5 {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PP1800_S5/PP3300_S5 enable output to LS";
+		enum-name = "PWR_EN_PP3300_A";
+		gpios = <&gpiob 6 GPIO_ACTIVE_HIGH>;
+		output;
+	};
+	pwr-pg-ec-rsmrst-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST power good from regulator";
+		enum-name = "PWR_RSMRST";
+		gpios = <&gpioe 2 GPIO_ACTIVE_HIGH>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-ec-pch-rsmrst-odl {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST output to PCH";
+		enum-name = "PWR_EC_PCH_RSMRST";
+		gpios = <&gpioa 6 GPIO_ACTIVE_HIGH>;
+		output;
+	};
+	pwr-pch-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PCH_PWROK output to PCH";
+		enum-name = "PWR_PCH_PWROK";
+		gpios = <&gpioa 5 GPIO_ACTIVE_HIGH>;
+		output;
+	};
+	pwr-ec-pch-sys-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_PWROK output to PCH";
+		enum-name = "PWR_EC_PCH_SYS_PWROK";
+		gpios = <&gpiob 0 GPIO_ACTIVE_HIGH>;
+		output;
+	};
+	pwr-sys-rst-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_RESET# output to PCH";
+		enum-name = "PWR_SYS_RST";
+		gpios = <&gpioc 5 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+		output;
+	};
+	pwr-slp-s0-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_S0_L input from PCH";
+		enum-name = "PWR_SLP_S0";
+		gpios = <&gpiod 5 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-slp-s3-l {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S3_L input from PCH";
+		enum-name = "PWR_SLP_S3";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S3";
+		vw-invert;
+/*
+ * TODO: Initially, use virtual wire for sleep S3 signal instead of
+ * of the GPIO signal which also exists.
+ *		compatible = "intel,ap-pwrseq-gpio";
+ *		gpios = <&gpio4 1 GPIO_ACTIVE_LOW>;
+ *		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+ */
+	};
+	pwr-slp-s4 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S4 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S4";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4";
+		vw-invert;
+	};
+	pwr-slp-s5 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S5 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S5";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5";
+		vw-invert;
+	};
+	pwr-all-sys-pwrgd {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "all power good";
+		enum-name = "PWR_ALL_SYS_PWRGD";
+		gpios = <&gpiof 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+};
+
+/*
+ * Because the power signals directly reference the GPIOs,
+ * the corresponding named-gpios need to have no-auto-init set.
+ */
+ /* pwr-en-pp3300-s5 */
+&gpio_en_s5_rails {
+	no-auto-init;
+};
+
+/* pwr-pg-ec-rsmrst-od */
+&gpio_seq_ec_rsmrst_odl {
+	no-auto-init;
+};
+
+/* pwr-ec-pch-rsmrst-odl */
+&gpio_ec_soc_rsmrst_l {
+	no-auto-init;
+};
+
+/* pwr-pch-pwrok */
+&gpio_soc_pwrok {
+	no-auto-init;
+};
+
+/* pwr-ec-pch-sys-pwrok */
+&gpio_sys_pwrok {
+	no-auto-init;
+};
+
+/* pwr-sys-rst-l */
+&gpio_sys_rst_odl {
+	no-auto-init;
+};
+
+/* pwr-slp-s0-l */
+&gpio_sys_slp_s0ix_3v3_l {
+	no-auto-init;
+};
+
+/* pwr-slp-s3-l */
+&gpio_slp_s3_ls_l {
+	no-auto-init;
+};
+
+/* pwr-all-sys-pwrgd */
+&gpio_seq_ec_all_sys_pg_od {
+	no-auto-init;
+};
+
diff --git a/zephyr/program/rex/program.conf b/zephyr/program/rex/program.conf
new file mode 100644
index 0000000000..a86646d55f
--- /dev/null
+++ b/zephyr/program/rex/program.conf
@@ -0,0 +1,140 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_PLATFORM_EC=y
+CONFIG_CROS_EC=y
+CONFIG_SYSCON=y
+
+# Shell Commands
+CONFIG_SHELL_HELP=n
+CONFIG_SHELL_HISTORY=y
+CONFIG_SHELL_TAB=y
+CONFIG_SHELL_TAB_AUTOCOMPLETION=y
+CONFIG_KERNEL_SHELL=y
+
+# Disable default features we don't want in a minimal example.
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=y
+CONFIG_PLATFORM_EC_SWITCH=y
+CONFIG_PLATFORM_EC_VBOOT_EFS2=y
+
+# Application processor; communicates with EC via eSPI
+CONFIG_AP=y
+CONFIG_ESPI=y
+CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S3=y
+CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S4=y
+CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S5=y
+CONFIG_PLATFORM_EC_HOSTCMD=y
+CONFIG_HCDEBUG_OFF=y
+# Disabling this until temp sensor support is in
+CONFIG_PLATFORM_EC_THROTTLE_AP=n
+CONFIG_PLATFORM_EC_PORT80=y
+
+# Power Sequecing
+CONFIG_AP_X86_INTEL_MTL=y
+CONFIG_X86_NON_DSX_PWRSEQ_MTL=y
+CONFIG_X86_NON_DSX_PWRSEQ_HOST_CMD=y
+# TODO (b/240434243): This may be needed, but using eSPI VW for now
+CONFIG_PLATFORM_EC_POWERSEQ_SLP_S3_L_OVERRIDE=n
+CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n
+
+# Zephyr Inbuilt AP Power Sequencing Config
+CONFIG_X86_NON_DSX_PWRSEQ_CONSOLE=y
+CONFIG_AP_PWRSEQ_S0IX=y
+CONFIG_AP_PWRSEQ_S0IX_ERROR_RECOVERY=y
+
+# I2C
+CONFIG_PLATFORM_EC_HOSTCMD_I2C_CONTROL=y
+
+# Temperature sensors
+CONFIG_PLATFORM_EC_TEMP_SENSOR_POWER=y
+
+# CBI EEPROM support
+CONFIG_EEPROM=y
+CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=y
+CONFIG_PLATFORM_EC_EEPROM_CBI_WP=y
+
+# Battery
+CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y
+CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y
+CONFIG_PLATFORM_EC_BATTERY_REVIVE_DISCONNECT=y
+
+# Charger
+CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y
+CONFIG_PLATFORM_EC_CHARGER_DEFAULT_CURRENT_LIMIT=512
+CONFIG_PLATFORM_EC_CHARGER_ISL9241=y
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=5
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=10
+CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON=30000
+CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT=15000
+CONFIG_PLATFORM_EC_CHARGER_MIN_INPUT_CURRENT_LIMIT=512
+
+# USBC
+CONFIG_PLATFORM_EC_USBC_PPC=y
+CONFIG_PLATFORM_EC_USBC_PPC_SYV682C=y
+# TODO(b/241340453): after FRS fixed, enable this config
+CONFIG_PLATFORM_EC_USBC_PPC_SYV682X_SMART_DISCHARGE=n
+CONFIG_PLATFORM_EC_USBC_VCONN=y
+
+CONFIG_PLATFORM_EC_USB_DRP_ACC_TRYSRC=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y
+CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y
+CONFIG_PLATFORM_EC_USB_PD_FRS=y
+CONFIG_PLATFORM_EC_USB_PD_FRS_PPC=y
+CONFIG_PLATFORM_EC_USB_PD_LOGGING=y
+CONFIG_PLATFORM_EC_USB_PD_REV30=y
+CONFIG_PLATFORM_EC_USB_PD_TCPC_LOW_POWER=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8815=y
+CONFIG_PLATFORM_EC_USB_PD_TRY_SRC=y
+CONFIG_PLATFORM_EC_USB_PD_DUAL_ROLE_AUTO_TOGGLE=y
+CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=y
+CONFIG_PLATFORM_EC_USB_PD_USB32_DRD=y
+CONFIG_PLATFORM_EC_USB_PD_USB4=y
+CONFIG_PLATFORM_EC_USB_PD_REQUIRE_AP_MODE_ENTRY=y
+CONFIG_PLATFORM_EC_USB_PD_DATA_RESET_MSG=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_CHARGER=y
+CONFIG_PLATFORM_EC_USB_PID=0x504D
+
+# USB Mux
+CONFIG_PLATFORM_EC_USB_MUX_TASK=y
+
+# External power
+CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y
+
+# Standard shimmed features
+CONFIG_PLATFORM_EC_POWER_BUTTON=y
+CONFIG_PLATFORM_EC_LID_SWITCH=y
+
+# Keyboard support
+CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_8042=y
+# Column 2 is driven through the GSC, which inverts the signal going through it
+CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED=y
+CONFIG_PLATFORM_EC_VOLUME_BUTTONS=y
+
+# MKBP event
+CONFIG_PLATFORM_EC_MKBP_EVENT=y
+CONFIG_PLATFORM_EC_MKBP_INPUT_DEVICES=y
+CONFIG_PLATFORM_EC_MKBP_USE_GPIO_AND_HOST_EVENT=y
+
+# Sensors console command
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_I2C_SPEED=y
+
+# Sensors
+CONFIG_PLATFORM_EC_ACCEL_FIFO=y
+CONFIG_PLATFORM_EC_DYNAMIC_MOTION_SENSOR_COUNT=y
+CONFIG_PLATFORM_EC_GMR_TABLET_MODE=y
+CONFIG_PLATFORM_EC_LID_ANGLE=y
+CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y
+CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=y
+CONFIG_PLATFORM_EC_TABLET_MODE=y
+CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=y
+
+# Sensor Drivers
+CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSO=y
+CONFIG_PLATFORM_EC_ACCEL_LIS2DW12=y
+CONFIG_PLATFORM_EC_ALS_TCS3400=y
+
+# System Boot Time
+CONFIG_SYSTEM_BOOT_TIME_LOGGING=y
diff --git a/zephyr/program/rex/rex-ish-ec/project.conf b/zephyr/program/rex/rex-ish-ec/project.conf
new file mode 100644
index 0000000000..d9c0de150c
--- /dev/null
+++ b/zephyr/program/rex/rex-ish-ec/project.conf
@@ -0,0 +1,26 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Disable motionsense
+CONFIG_PLATFORM_EC_MOTIONSENSE=n
+
+# Disable sensors console command
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=n
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=n
+CONFIG_PLATFORM_EC_CONSOLE_CMD_I2C_SPEED=n
+
+# Disable sensors
+CONFIG_PLATFORM_EC_ACCEL_FIFO=n
+CONFIG_PLATFORM_EC_DYNAMIC_MOTION_SENSOR_COUNT=n
+CONFIG_PLATFORM_EC_GMR_TABLET_MODE=n
+CONFIG_PLATFORM_EC_LID_ANGLE=n
+CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=n
+CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=n
+CONFIG_PLATFORM_EC_TABLET_MODE=n
+CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=n
+
+# Disable sensor Drivers
+CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSO=n
+CONFIG_PLATFORM_EC_ACCEL_LIS2DW12=n
+CONFIG_PLATFORM_EC_ALS_TCS3400=n
diff --git a/zephyr/program/rex/rex-ish-ec/project.overlay b/zephyr/program/rex/rex-ish-ec/project.overlay
new file mode 100644
index 0000000000..d292714a25
--- /dev/null
+++ b/zephyr/program/rex/rex-ish-ec/project.overlay
@@ -0,0 +1,23 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Include base Rex */
+#include "../rex/project.overlay"
+
+&i2c0_0 {
+	status = "disabled";
+};
+&i2c_ec_i2c_sensor_scl_r {
+	status = "disabled";
+};
+&int_imu {
+	status = "disabled";
+};
+&int_als_rgb {
+	status = "disabled";
+};
+&int_accel {
+	status = "disabled";
+};
diff --git a/zephyr/program/rex/rex.dtsi b/zephyr/program/rex/rex.dtsi
new file mode 100644
index 0000000000..e6f46ed746
--- /dev/null
+++ b/zephyr/program/rex/rex.dtsi
@@ -0,0 +1,371 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/usb_pd_tcpm.h>
+
+/ {
+	aliases {
+		gpio-wp = &gpio_ec_wp_l;
+		gpio-cbi-wp = &gpio_ec_cbi_wp;
+		gpio-kbd-kso2 = &gpio_ec_kso_02_inv;
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		gpio_ec_entering_rw: ec_entering_rw {
+			enum-name = "GPIO_ENTERING_RW";
+		};
+
+		ioex_usb_c0_sbu_fault_odl: usb_c0_sbu_fault_odl {
+			gpios = <&ioex_c0_port1 2 GPIO_INPUT>;
+		};
+		ioex_usb_c0_rt_rst_ls_l: usb_c0_rt_rst_ls_l {
+			gpios = <&ioex_c0_port0 7 GPIO_OUTPUT>;
+		};
+
+		ioex_usb_c0_frs_en: usb_c0_frs_en {
+			gpios = <&ioex_c0_port0 6 GPIO_OUTPUT_LOW>;
+		};
+
+		/* Need to designate 1.8V for I2C buses on the 1800mV rail */
+		ec-i2c-sensor-scl {
+			gpios = <&gpiob 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		ec-i2c-sensor-sda {
+			gpios = <&gpiob 4 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		ec-i2c-c0-rt-scl {
+			gpios = <&gpiod 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		ec-i2c-c0-rt-sda {
+			gpios = <&gpiod 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+
+		/* Overrides for generated.dtsi */
+		ec_edp_bl_en {
+			gpios = <&gpiod 3 GPIO_OUTPUT_LOW>;
+		};
+		en_pp5000_fan {
+			gpios = <&gpio6 1 GPIO_OUTPUT_LOW>;
+		};
+		usb_c0_tcpc_rst_odl {
+			gpios = <&gpio6 7 (GPIO_ODR_HIGH | GPIO_ACTIVE_LOW)>;
+		};
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		/*
+		 * Override auto-generated GPIO definitions for pins
+		 * that are reconfigured at runtime for specific
+		 * daughterboards.
+		 *
+		 * The flags parameter needs to be 0 here because
+		 * gpio_pin_configure_dt() can only add flags.
+		 */
+
+		usb_c1_rst_odl {
+			gpios = <&gpio3 7 0>;
+			no-auto-init;
+		};
+		usb_c1_rt_int_odl {
+			gpios = <&gpio7 2 0>;
+			no-auto-init;
+		};
+		usb_c1_rt_rst_r_odl {
+			gpios = <&gpio7 4 0>;
+			no-auto-init;
+		};
+		usb_c1_frs_en {
+			gpios = <&gpio8 3 0>;
+			no-auto-init;
+		};
+	};
+
+	aliases {
+		/* GPIO37 */
+		kb-usb-c1-rst-odl = &gpio_usb_c1_rst_odl;
+		anx-usb-c1-rt-hpd-in = &gpio_usb_c1_rst_odl;
+
+		/* GPIO72 */
+		kb-usb-c1-dp-mode = &gpio_usb_c1_rt_int_odl;
+		anx-usb-c1-rt-dp-en = &gpio_usb_c1_rt_int_odl;
+
+		/* GPIO74 */
+		ps-usb-c1-rt-rst-odl = &gpio_usb_c1_rt_rst_r_odl;
+		kb-usb-c1-rt-rst-odl = &gpio_usb_c1_rt_rst_r_odl;
+		anx-usb-c1-rt-usb-en = &gpio_usb_c1_rt_rst_r_odl;
+
+		/* GPIO83 */
+		kb-usb-c1-frs-alert = &gpio_usb_c1_frs_en;
+		anx-usb-c1-frs-en = &gpio_usb_c1_frs_en;
+	};
+
+	/* Special I2C port attribute */
+	named-i2c-ports {
+		ec_i2c_usb_c1_tcp {
+			dynamic-speed;
+		};
+	};
+
+	usba-port-enable-list {
+		compatible = "cros-ec,usba-port-enable-pins";
+		enable-pins = <&gpio_en_pp5000_usba_r>;
+	};
+};
+
+/* host interface */
+&espi0 {
+	status = "okay";
+	pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>;
+	pinctrl-names = "default";
+};
+
+/* Power switch logic input pads */
+&psl_in1_gpd2 {
+	/* LID_OPEN */
+	psl-in-mode = "edge";
+	psl-in-pol = "high-rising";
+};
+
+&psl_in2_gp00 {
+	/* ACOK_OD */
+	psl-in-mode = "edge";
+	psl-in-pol = "high-rising";
+};
+
+&psl_in4_gp02 {
+	/* MECH_PWR_BTN_ODL */
+	psl-in-mode = "edge";
+	psl-in-pol = "low-falling";
+};
+
+/* Power domain device controlled by PSL (Power Switch Logic) IO pads */
+&power_ctrl_psl {
+	status = "okay";
+	pinctrl-names = "sleep";
+	pinctrl-0 = <&psl_in1_gpd2 &psl_in2_gp00 &psl_in4_gp02>;
+};
+
+/* ADC and GPIO alt-function specifications */
+&adc0 {
+	pinctrl-0 = <&adc0_chan0_gp45
+		     &adc0_chan1_gp44
+		     &adc0_chan8_gpf1
+		     &adc0_chan7_gpe1>;
+	pinctrl-names = "default";
+};
+
+&i2c0_0 {
+	label = "I2C_SENSOR";
+	clock-frequency = <I2C_BITRATE_FAST>;
+
+	pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>;
+	pinctrl-names = "default";
+};
+
+&i2c1_0 {
+	label = "I2C_USB_C0_TCPC";
+	clock-frequency = <I2C_BITRATE_FAST>;
+
+	pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>;
+	pinctrl-names = "default";
+
+	tcpc_port0: nct38xx@70 {
+		compatible = "nuvoton,nct38xx";
+		gpio-dev = <&nct3807_C0>;
+		reg = <0x70>;
+		tcpc-flags = <(
+			TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V)>;
+		/* a duplicate of the <&gpio_usb_c0_tcpc_int_odl> node in
+		 * "named-gpios". This is the Zephyr preferred style,
+		 * the "named-gpios" node will be dealt with at a later date.
+		 */
+		irq-gpios = <&gpioe 0 GPIO_ACTIVE_LOW>;
+		/* a duplicate of the <&gpio_usb_c0_tcpc_rst_odl> node in
+		 * "named-gpios". This is the Zephyr preferred style,
+		 * the "named-gpios" node will be dealt with at a later date.
+		 */
+		rst-gpios = <&gpio6 7 (GPIO_OPEN_DRAIN | GPIO_ACTIVE_LOW)>;
+	};
+
+	nct3807_C0: nct3807_C0@70 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nuvoton,nct38xx-gpio";
+		reg = <0x70>;
+		label = "NCT3807_C0";
+
+		ioex_c0_port0: gpio@0 {
+			compatible = "nuvoton,nct38xx-gpio-port";
+			reg = <0x0>;
+			label = "NCT3807_C0_GPIO0";
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <8>;
+			pin_mask = <0xff>;
+			pinmux_mask = <0xf7>;
+		};
+		ioex_c0_port1: gpio@1 {
+			compatible = "nuvoton,nct38xx-gpio-port";
+			reg = <0x1>;
+			label = "NCT3807_C0_GPIO1";
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <8>;
+			pin_mask = <0xff>;
+		};
+	};
+
+	nct3808_alert_0 {
+		compatible = "nuvoton,nct38xx-gpio-alert";
+		irq-gpios = <&gpioe 0 GPIO_ACTIVE_LOW>;
+		nct38xx-dev = <&nct3807_C0>;
+		label = "NCT3807_ALERT_0";
+	};
+};
+
+&i2c2_0 {
+	label = "I2C_PPC0";
+	clock-frequency = <I2C_BITRATE_FAST>;
+
+	pinctrl-0 = <&i2c2_0_sda_scl_gp91_92>;
+	pinctrl-names = "default";
+
+	bc12_port0: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+		irq = <&int_usb_c0_bc12>;
+	};
+
+	ppc_port0_syv: ppc_syv@40 {
+		compatible = "silergy,syv682x";
+		status = "okay";
+		reg = <0x40>;
+		frs_en_gpio = <&ioex_usb_c0_frs_en>;
+	};
+};
+
+&i2c3_0 {
+	label = "I2C_USB_C0_RT";
+	clock-frequency = <I2C_BITRATE_FAST>;
+
+	pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>;
+	pinctrl-names = "default";
+
+	usb_c0_hb_retimer: jhl9040r-c0@56 {
+		compatible = "intel,jhl9040r";
+		reg = <0x56>;
+		ls-en-pin = <&gpio_usb_c0_rt_3p3_sx_en>;
+		int-pin = <&gpio_usb_c0_rt_int_odl>;
+		reset-pin = <&ioex_usb_c0_rt_rst_ls_l>;
+	};
+};
+
+&i2c4_1 {
+	label = "I2C_USB_C1_TCPC";
+	clock-frequency = <I2C_BITRATE_FAST>;
+
+	pinctrl-0 = <&i2c4_1_sda_scl_gpf2_f3>;
+	pinctrl-names = "default";
+
+	tcpc_rt1716_port1: rt1716@4e {
+		compatible = "richtek,rt1715-tcpc";
+		reg = <0x4e>;
+		tcpc-flags = <(TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V)>;
+		/* a duplicate of the <&gpio_usb_c1_tcpc_int_odl> node in
+		 * "named-gpios". This is the Zephyr preferred style,
+		 * the "named-gpios" node will be dealt with at a later date.
+		 */
+		irq-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
+		is-alt;
+	};
+};
+
+&i2c5_0 {
+	label = "I2C_BATTERY";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+
+	pinctrl-0 = <&i2c5_0_sda_scl_gp33_36>;
+	pinctrl-names = "default";
+};
+
+&i2c6_1 {
+	label = "I2C_USB_1_MIX";
+	clock-frequency = <I2C_BITRATE_FAST>;
+
+	pinctrl-0 = <&i2c6_1_sda_scl_gpe3_e4>;
+	pinctrl-names = "default";
+
+	bc12_port1: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+		irq = <&int_usb_c1_bc12>;
+	};
+
+	ppc_ktu1125_port1: ktu1125@38 {
+		compatible = "kinetic,ktu1125";
+		status = "okay";
+		reg = <0x38>;
+		is-alt;
+	};
+
+	ppc_nx20p_port1: nx20p348x@72 {
+		compatible = "nxp,nx20p348x";
+		status = "okay";
+		reg = <0x72>;
+		is-alt;
+	};
+
+	ppc_syv_port1: ppc_syv@40 {
+		compatible = "silergy,syv682x";
+		status = "okay";
+		reg = <0x40>;
+		frs_en_gpio = <&gpio_usb_c1_frs_en>;
+		is-alt;
+	};
+
+	usb_c1_anx7452_retimer: usb-c1-anx7452-retimer@10 {
+		compatible = "analogix,anx7452";
+		reg = <0x10>;
+		usb-en-pin = <&gpio_usb_c1_rt_rst_r_odl>;
+		dp-en-pin = <&gpio_usb_c1_rt_int_odl>;
+	};
+
+	usb_c1_kb8010_retimer: usb-c1-kb8010-retimer@8 {
+		compatible = "kandou,kb8010";
+		reg = <0x08>;
+		reset-pin = <&gpio_usb_c1_rt_rst_r_odl>;
+	};
+};
+
+&i2c7_0 {
+	label = "I2C_CHARGER";
+	clock-frequency = <I2C_BITRATE_FAST>;
+
+	pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>;
+	pinctrl-names = "default";
+
+	cbi_eeprom: eeprom@50 {
+		compatible = "atmel,at24";
+		reg = <0x50>;
+		size = <2048>;
+		pagesize = <16>;
+		address-width = <8>;
+		timeout = <5>;
+	};
+
+	charger: isl9241@9 {
+		compatible = "intersil,isl9241";
+		status = "okay";
+		reg = <0x09>;
+	};
+};
diff --git a/zephyr/program/rex/rex/CMakeLists.txt b/zephyr/program/rex/rex/CMakeLists.txt
new file mode 100644
index 0000000000..4822b7c74c
--- /dev/null
+++ b/zephyr/program/rex/rex/CMakeLists.txt
@@ -0,0 +1,8 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cros_ec_library_include_directories_ifdef(CONFIG_BOARD_REX include)
+zephyr_include_directories("include")
+zephyr_library_sources("src/usb_mux_config.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/usbc_config.c")
diff --git a/zephyr/program/rex/rex/cbi.dtsi b/zephyr/program/rex/rex/cbi.dtsi
new file mode 100644
index 0000000000..6e9e35cf48
--- /dev/null
+++ b/zephyr/program/rex/rex/cbi.dtsi
@@ -0,0 +1,51 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	rex-fw-config {
+		compatible = "cros-ec,cbi-fw-config";
+
+		/*
+		 * FW_CONFIG field to enable USB DB.
+		 */
+		usb-db {
+			enum-name = "FW_USB_DB";
+			start = <12>;
+			size = <3>;
+
+			io-db-unknown {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_USB_DB_NOT_CONNECTED";
+				value = <0>;
+			};
+			io-db-usb3 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_USB_DB_USB3";
+				value = <1>;
+				default;
+			};
+			io-db-usb4-kb8010 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_USB_DB_USB4_KB8010";
+				value = <2>;
+			};
+			io-db-usb4-anx7452 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_USB_DB_USB4_ANX7452";
+				value = <3>;
+			};
+			io-db-usb4-hayden {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_USB_DB_USB4_HB";
+				value = <4>;
+			};
+			io-db-usb4-anx7452v2 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_USB_DB_USB4_ANX7452_V2";
+				value = <5>;
+			};
+		};
+	};
+};
diff --git a/zephyr/program/rex/rex/i2c.dtsi b/zephyr/program/rex/rex/i2c.dtsi
new file mode 100644
index 0000000000..c6b9db71ea
--- /dev/null
+++ b/zephyr/program/rex/rex/i2c.dtsi
@@ -0,0 +1,22 @@
+&i2c4_1 {
+	tcpc_ps8815_port1: ps8xxx@b {
+		compatible = "parade,ps8xxx";
+		reg = <0xb>;
+		tcpc-flags = <(
+			TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V |
+			TCPC_FLAGS_CONTROL_VCONN |
+			TCPC_FLAGS_CONTROL_FRS)>;
+		/* a duplicate of the <&gpio_usb_c1_tcpc_int_odl> node in
+		 * "named-gpios". This is the Zephyr preferred style,
+		 * the "named-gpios" node will be dealt with at a later date.
+		 */
+		irq-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
+		/* a duplicate of the <&gpio_usb_c1_rt_rst_r_odl> node in
+		 * "named-gpios". This is the Zephyr preferred style,
+		 * the "named-gpios" node will be dealt with at a later date.
+		 */
+		rst-gpios = <&gpio7 4 0>;
+		is-alt;
+	};
+};
diff --git a/zephyr/program/rex/rex/include/usb_mux_config.h b/zephyr/program/rex/rex/include/usb_mux_config.h
new file mode 100644
index 0000000000..b43d96f209
--- /dev/null
+++ b/zephyr/program/rex/rex/include/usb_mux_config.h
@@ -0,0 +1,11 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __ZEPHYR_USB_MUX_CONFIG_H
+#define __ZEPHYR_USB_MUX_CONFIG_H
+
+extern uint32_t usb_db_type;
+
+#endif /* __ZEPHYR_USB_MUX_CONFIG_H */
diff --git a/zephyr/program/rex/rex/led_pins.dtsi b/zephyr/program/rex/rex/led_pins.dtsi
new file mode 100644
index 0000000000..7a4ff16273
--- /dev/null
+++ b/zephyr/program/rex/rex/led_pins.dtsi
@@ -0,0 +1,55 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	gpio-led-pins {
+		compatible = "cros-ec,gpio-led-pins";
+
+		left_led: left-led {
+			led-id = "EC_LED_ID_LEFT_LED";
+			led-pins = <&gpio_led_1_l &gpio_led_2_l>;
+			color_off_left: color-off-left {
+				led-color = "LED_OFF";
+				led-values = <1 1>;
+			};
+
+			color_amber_left: color-amber-left {
+				led-color = "LED_AMBER";
+				br-color = "EC_LED_COLOR_AMBER";
+				led-values = <0 1>;
+			};
+
+			color_white_left: color-white-left {
+				led-color = "LED_WHITE";
+				br-color = "EC_LED_COLOR_WHITE";
+				led-values = <1 0>;
+			};
+		};
+
+		right_led: right-led {
+			led-id = "EC_LED_ID_RIGHT_LED";
+			led-pins = <&gpio_led_3_l &gpio_led_4_l>;
+
+			color_off_right: color-off-right {
+				led-color = "LED_OFF";
+				led-values = <1 1>;
+			};
+
+
+			color_amber_right: color-amber-right {
+				led-color = "LED_AMBER";
+				br-color = "EC_LED_COLOR_AMBER";
+				led-values = <0 1>;
+			};
+
+
+			color_white_right: color-white-right {
+				led-color = "LED_WHITE";
+				br-color = "EC_LED_COLOR_WHITE";
+				led-values = <1 0>;
+			};
+		};
+	};
+};
diff --git a/zephyr/program/rex/rex/led_policy.dtsi b/zephyr/program/rex/rex/led_policy.dtsi
new file mode 100644
index 0000000000..ef34d23e3c
--- /dev/null
+++ b/zephyr/program/rex/rex/led_policy.dtsi
@@ -0,0 +1,205 @@
+#include <dt-bindings/battery.h>
+
+/ {
+	led-colors {
+		compatible = "cros-ec,led-policy";
+
+		power-state-near-full-left {
+			charge-state = "LED_PWRS_CHARGE_NEAR_FULL";
+			charge-port = <0>; /* Left port */
+
+			/* Turn off the right LED */
+			color-0 {
+				led-color = <&color_off_right>;
+			};
+			/* Left LED to White */
+			color-1 {
+				led-color = <&color_white_left>;
+			};
+		};
+
+		power-state-near-full-right {
+			charge-state = "LED_PWRS_CHARGE_NEAR_FULL";
+			charge-port = <1>; /* Right port */
+
+			/* Turn off the left LED */
+			color-0 {
+				led-color = <&color_off_left>;
+			};
+			/* Right LED to White */
+			color-1 {
+				led-color = <&color_white_right>;
+			};
+		};
+
+		power-state-high-left {
+			charge-state = "LED_PWRS_CHARGE";
+			/* Battery percent range 99..100 */
+			batt-lvl = <99 100>;
+
+			charge-port = <0>; /* Left port */
+
+			/* Turn off the right LED */
+			color-0 {
+				led-color = <&color_off_right>;
+			};
+			/* Left LED to White */
+			color-1 {
+				led-color = <&color_white_left>;
+			};
+		};
+
+		power-state-high-right {
+			charge-state = "LED_PWRS_CHARGE";
+			/* Battery percent range 99..100 */
+			batt-lvl = <99 100>;
+			charge-port = <1>; /* Right port */
+
+			/* Turn off the left LED */
+			color-0 {
+				led-color = <&color_off_left>;
+			};
+			/* Right LED to White */
+			color-1 {
+				led-color = <&color_white_right>;
+			};
+		};
+
+		power-state-charge-left {
+			charge-state = "LED_PWRS_CHARGE";
+			/* Battery percent range 0..98 */
+			batt-lvl = <0 98>;
+			charge-port = <0>; /* Left port */
+
+			/* Left LED to Amber */
+			color-0 {
+				led-color = <&color_amber_left>;
+			};
+			/* Turn off the right LED */
+			color-1 {
+				led-color = <&color_off_right>;
+			};
+		};
+
+		power-state-charge-right {
+			charge-state = "LED_PWRS_CHARGE";
+			charge-port = <1>; /* Right port */
+			/* Battery percent range 0..98 */
+			batt-lvl = <0 98>;
+
+			/* Turn off the left LED */
+			color-0 {
+				led-color = <&color_off_left>;
+			};
+			/* Right LED to Amber */
+			color-1 {
+				led-color = <&color_amber_right>;
+			};
+		};
+
+		power-state-discharge {
+			charge-state = "LED_PWRS_DISCHARGE";
+			/* Battery percent range (> Low, <= Full) */
+			batt-lvl = <(BATTERY_LEVEL_LOW + 1) BATTERY_LEVEL_FULL>;
+
+			/* Turn off both LEDs LED */
+			color-0 {
+				led-color = <&color_off_left>;
+			};
+			color-1 {
+				led-color = <&color_off_right>;
+			};
+		};
+
+		power-state-discharge-low {
+			charge-state = "LED_PWRS_DISCHARGE";
+			/* Battery percent range (>= Empty, <= Low) */
+			batt-lvl = <BATTERY_LEVEL_EMPTY BATTERY_LEVEL_LOW>;
+
+			/* Blink both LEDs amber at 0.5 Hz */
+			color-0 {
+				led-color = <&color_amber_left>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_amber_right>;
+				period-ms = <1000>;
+			};
+			color-2 {
+				led-color = <&color_off_left>;
+				period-ms = <1000>;
+			};
+			color-3 {
+				led-color = <&color_off_right>;
+				period-ms = <1000>;
+			};
+		};
+
+		power-state-idle {
+			charge-state = "LED_PWRS_IDLE";
+
+			/* Blink both LEDs amber at 0.5 Hz */
+			color-0 {
+				led-color = <&color_amber_left>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_amber_right>;
+				period-ms = <1000>;
+			};
+			color-2 {
+				led-color = <&color_white_left>;
+				period-ms = <1000>;
+			};
+			color-3 {
+				led-color = <&color_white_right>;
+				period-ms = <1000>;
+			};
+		};
+
+		power-state-forced-idle {
+			charge-state = "LED_PWRS_FORCED_IDLE";
+
+			/* Blink both LEDs amber at 2 Hz */
+			color-0 {
+				led-color = <&color_amber_left>;
+				period-ms = <250>;
+			};
+			color-1 {
+				led-color = <&color_amber_right>;
+				period-ms = <250>;
+			};
+			color-2 {
+				led-color = <&color_white_left>;
+				period-ms = <250>;
+			};
+			color-3 {
+				led-color = <&color_white_right>;
+				period-ms = <250>;
+			};
+		};
+
+		power-state-error {
+			charge-state = "LED_PWRS_ERROR";
+
+			/* Blink both LEDs amber at 2 Hz */
+			color-0 {
+				led-color = <&color_amber_left>;
+				period-ms = <250>;
+			};
+			color-1 {
+				led-color = <&color_amber_right>;
+				period-ms = <250>;
+			};
+			color-2 {
+				led-color = <&color_off_left>;
+				period-ms = <250>;
+			};
+			color-3 {
+				led-color = <&color_off_right>;
+				period-ms = <250>;
+			};
+		};
+
+	};
+};
diff --git a/zephyr/program/rex/rex/project.conf b/zephyr/program/rex/rex/project.conf
new file mode 100644
index 0000000000..a22555ad4f
--- /dev/null
+++ b/zephyr/program/rex/rex/project.conf
@@ -0,0 +1,13 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Rex-NPCX9 reference-board-specific Kconfig settings.
+CONFIG_BOARD_REX=y
+
+# Ensure recovery key combination (esc+refresh+power) is reliable: b/260555509
+CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI2=y
+
+# Some boards detect a false VBUS reverse current event
+# First investigated on taniks (b/237468526)
+CONFIG_PLATFORM_EC_USBC_NX20P348X_RCP_5VSRC_MASK_ENABLE=y
diff --git a/zephyr/program/rex/rex/project.overlay b/zephyr/program/rex/rex/project.overlay
new file mode 100644
index 0000000000..aaa8c2c3a9
--- /dev/null
+++ b/zephyr/program/rex/rex/project.overlay
@@ -0,0 +1,22 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Rex program common DTSI includes */
+#include "../battery.dtsi"
+#include "../fan.dtsi"
+#include "../generated.dtsi"
+#include "../interrupts.dtsi"
+#include "../keyboard.dtsi"
+#include "../motionsense.dtsi"
+#include "../power_signals.dtsi"
+#include "../rex.dtsi"
+#include "../temp_sensors.dtsi"
+#include "../usbc.dtsi"
+
+/* Rex project DTS includes */
+#include "cbi.dtsi"
+#include "i2c.dtsi"
+#include "led_pins.dtsi"
+#include "led_policy.dtsi"
diff --git a/zephyr/program/rex/rex/src/usb_mux_config.c b/zephyr/program/rex/rex/src/usb_mux_config.c
new file mode 100644
index 0000000000..2c643ea68e
--- /dev/null
+++ b/zephyr/program/rex/rex/src/usb_mux_config.c
@@ -0,0 +1,149 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Rex board-specific USB-C mux configuration */
+
+#include "console.h"
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+#include "hooks.h"
+#include "usb_mux.h"
+#include "usb_mux_config.h"
+#include "usb_pd.h"
+#include "usbc/ppc.h"
+#include "usbc/tcpci.h"
+#include "usbc/usb_muxes.h"
+#include "usbc_config.h"
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/logging/log.h>
+
+#include <dt-bindings/gpio_defines.h>
+
+#ifdef CONFIG_ZTEST
+
+#undef USB_MUX_ENABLE_ALTERNATIVE
+#define USB_MUX_ENABLE_ALTERNATIVE(x)
+
+#undef TCPC_ENABLE_ALTERNATE_BY_NODELABEL
+#define TCPC_ENABLE_ALTERNATE_BY_NODELABEL(x, y)
+
+#undef PPC_ENABLE_ALTERNATE_BY_NODELABEL
+#define PPC_ENABLE_ALTERNATE_BY_NODELABEL(x, y)
+
+#endif /* CONFIG_ZTEST */
+
+LOG_MODULE_DECLARE(rex, CONFIG_REX_LOG_LEVEL);
+
+uint32_t usb_db_type;
+
+static int gpio_unused(const struct gpio_dt_spec *spec)
+{
+	return gpio_pin_configure(spec->port, spec->pin, GPIO_INPUT_PULL_UP);
+}
+
+static void setup_runtime_gpios(void)
+{
+	int ret;
+
+	ret = cros_cbi_get_fw_config(FW_USB_DB, &usb_db_type);
+	if (ret != EC_SUCCESS) {
+		LOG_INF("Failed to get FW_USB_DB from CBI");
+		usb_db_type = FW_USB_DB_NOT_CONNECTED;
+	}
+
+	switch (usb_db_type) {
+	case FW_USB_DB_USB3:
+		gpio_unused(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_rst_odl));
+		gpio_unused(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_rt_int_odl));
+		gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(ps_usb_c1_rt_rst_odl),
+				      GPIO_ODR_HIGH | GPIO_ACTIVE_LOW);
+		gpio_unused(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_frs_en));
+		break;
+
+	case FW_USB_DB_USB4_KB8010:
+		gpio_unused(GPIO_DT_FROM_ALIAS(kb_usb_c1_rst_odl));
+		gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(kb_usb_c1_dp_mode),
+				      GPIO_ODR_HIGH);
+		gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(kb_usb_c1_rt_rst_odl),
+				      GPIO_ODR_HIGH);
+		gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(kb_usb_c1_frs_alert),
+				      GPIO_INPUT);
+		break;
+
+	case FW_USB_DB_USB4_ANX7452:
+	case FW_USB_DB_USB4_ANX7452_V2:
+		gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(anx_usb_c1_rt_hpd_in),
+				      GPIO_OUTPUT_LOW);
+		gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(anx_usb_c1_rt_dp_en),
+				      GPIO_OUTPUT_LOW);
+		gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(anx_usb_c1_rt_usb_en),
+				      GPIO_OUTPUT_LOW);
+		gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(anx_usb_c1_frs_en),
+				      GPIO_OUTPUT_LOW);
+		break;
+
+	default:
+		/* GPIO37 */
+		gpio_unused(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_rst_odl));
+		/* GPIO72 */
+		gpio_unused(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_rt_int_odl));
+		/* GPIO74 */
+		gpio_unused(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_rt_rst_r_odl));
+		/* GPIO83 */
+		gpio_unused(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_frs_en));
+		break;
+	}
+}
+DECLARE_HOOK(HOOK_INIT, setup_runtime_gpios, HOOK_PRIO_FIRST);
+
+static void setup_usb_db(void)
+{
+	switch (usb_db_type) {
+	case FW_USB_DB_NOT_CONNECTED:
+		LOG_INF("USB DB: not connected");
+		break;
+	case FW_USB_DB_USB3:
+		LOG_INF("USB DB: Setting USB3 mux");
+		USB_MUX_ENABLE_ALTERNATIVE(usb_mux_chain_ps8815_port1);
+		TCPC_ENABLE_ALTERNATE_BY_NODELABEL(USBC_PORT_C1,
+						   tcpc_ps8815_port1);
+		PPC_ENABLE_ALTERNATE_BY_NODELABEL(USBC_PORT_C1,
+						  ppc_nx20p_port1);
+		break;
+	case FW_USB_DB_USB4_ANX7452:
+	case FW_USB_DB_USB4_ANX7452_V2:
+		LOG_INF("USB DB: Setting ANX7452 mux");
+		USB_MUX_ENABLE_ALTERNATIVE(usb_mux_chain_anx7452_port1);
+		TCPC_ENABLE_ALTERNATE_BY_NODELABEL(USBC_PORT_C1,
+						   tcpc_rt1716_port1);
+		PPC_ENABLE_ALTERNATE_BY_NODELABEL(USBC_PORT_C1, ppc_syv_port1);
+		break;
+	case FW_USB_DB_USB4_KB8010:
+		LOG_INF("USB DB: Setting KB8010 mux");
+		USB_MUX_ENABLE_ALTERNATIVE(usb_mux_chain_kb8010_port1);
+		TCPC_ENABLE_ALTERNATE_BY_NODELABEL(USBC_PORT_C1,
+						   tcpc_rt1716_port1);
+		PPC_ENABLE_ALTERNATE_BY_NODELABEL(USBC_PORT_C1,
+						  ppc_ktu1125_port1);
+		break;
+	default:
+		LOG_INF("USB DB: No known USB DB found");
+	}
+}
+DECLARE_HOOK(HOOK_INIT, setup_usb_db, HOOK_PRIO_POST_I2C);
+
+__override uint8_t board_get_usb_pd_port_count(void)
+{
+	switch (usb_db_type) {
+	case FW_USB_DB_USB3:
+	case FW_USB_DB_USB4_ANX7452:
+	case FW_USB_DB_USB4_ANX7452_V2:
+	case FW_USB_DB_USB4_KB8010:
+		return 2;
+	default:
+		return 1;
+	}
+}
diff --git a/zephyr/program/rex/rex/src/usbc_config.c b/zephyr/program/rex/rex/src/usbc_config.c
new file mode 100644
index 0000000000..711258a5c9
--- /dev/null
+++ b/zephyr/program/rex/rex/src/usbc_config.c
@@ -0,0 +1,64 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cros_cbi.h"
+#include "driver/ppc/ktu1125_public.h"
+#include "driver/ppc/nx20p348x.h"
+#include "driver/tcpm/ps8xxx_public.h"
+#include "ppc/syv682x_public.h"
+#include "system.h"
+#include "usb_mux_config.h"
+#include "usbc_config.h"
+
+void board_reset_pd_mcu(void)
+{
+	/* Reset TCPC0 */
+	reset_nct38xx_port(USBC_PORT_C0);
+
+	/* Reset TCPC1 */
+	if (usb_db_type == FW_USB_DB_USB3 && tcpc_config[1].rst_gpio.port) {
+		gpio_pin_set_dt(&tcpc_config[1].rst_gpio, 1);
+		msleep(PS8XXX_RESET_DELAY_MS);
+		gpio_pin_set_dt(&tcpc_config[1].rst_gpio, 0);
+		msleep(PS8815_FW_INIT_DELAY_MS);
+	}
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_PPC_INT_ODL:
+		switch (usb_db_type) {
+		case FW_USB_DB_USB3:
+			nx20p348x_interrupt(USBC_PORT_C1);
+			break;
+		case FW_USB_DB_USB4_ANX7452:
+		case FW_USB_DB_USB4_ANX7452_V2:
+			syv682x_interrupt(USBC_PORT_C1);
+			break;
+		case FW_USB_DB_USB4_KB8010:
+			ktu1125_interrupt(USBC_PORT_C1);
+			break;
+		default:
+			break;
+		}
+		break;
+	default:
+		break;
+	}
+}
+
+__override bool board_is_tbt_usb4_port(int port)
+{
+	if (port == USBC_PORT_C0)
+		return true;
+	if (port == USBC_PORT_C1 && usb_db_type != FW_USB_DB_USB3)
+		return true;
+
+	return false;
+}
diff --git a/zephyr/program/rex/screebo/CMakeLists.txt b/zephyr/program/rex/screebo/CMakeLists.txt
new file mode 100644
index 0000000000..c0b55eb5b4
--- /dev/null
+++ b/zephyr/program/rex/screebo/CMakeLists.txt
@@ -0,0 +1,7 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cros_ec_library_include_directories_ifdef(CONFIG_BOARD_SCREEBO include)
+zephyr_include_directories("include")
+zephyr_library_sources("src/keyboard.c" "src/usb_config.c")
diff --git a/zephyr/program/rex/screebo/cbi.dtsi b/zephyr/program/rex/screebo/cbi.dtsi
new file mode 100644
index 0000000000..2294c8843b
--- /dev/null
+++ b/zephyr/program/rex/screebo/cbi.dtsi
@@ -0,0 +1,58 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	screebo-fw-config {
+		compatible = "cros-ec,cbi-fw-config";
+
+		/*
+		 * FW_CONFIG field to enable USB DB.
+		 */
+		usb-db {
+			enum-name = "FW_USB_DB";
+			start = <2>;
+			size = <3>;
+
+			io-db-unknown {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_USB_DB_NOT_CONNECTED";
+				value = <0>;
+			};
+			io-db-usb3 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_USB_DB_USB3";
+				value = <1>;
+			};
+			io-db-usb4-hayden {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_USB_DB_USB4_HB";
+				value = <2>;
+				default;
+			};
+		};
+		usb-mb {
+			enum-name = "FW_USB_MB";
+			start = <5>;
+			size = <3>;
+
+			io-mb-unknown {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_USB_MB_UNKNOWN";
+				value = <0>;
+			};
+			io-mb-usb3 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_USB_MB_USB3";
+				value = <1>;
+			};
+			io-mb-usb4-hayden {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_USB_MB_USB4_HB";
+				value = <2>;
+				default;
+			};
+		};
+	};
+};
diff --git a/zephyr/program/rex/screebo/gpio.dtsi b/zephyr/program/rex/screebo/gpio.dtsi
new file mode 100644
index 0000000000..2654450c0b
--- /dev/null
+++ b/zephyr/program/rex/screebo/gpio.dtsi
@@ -0,0 +1,307 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ */
+
+/ {
+	named-gpios {
+		compatible = "named-gpios";
+
+		gpio_acok_od: acok_od {
+			gpios = <&gpio0 0 GPIO_INPUT>;
+			enum-name = "GPIO_AC_PRESENT";
+		};
+		gpio_ccd_mode_odl: ccd_mode_odl {
+			gpios = <&gpioe 5 GPIO_INPUT>;
+			enum-name = "GPIO_CCD_MODE_ODL";
+		};
+		gpio_cpu_c10_gate_l: cpu_c10_gate_l {
+			gpios = <&gpioa 7 GPIO_INPUT>;
+		};
+		gpio_ec_batt_pres_odl: ec_batt_pres_odl {
+			gpios = <&gpioa 3 GPIO_INPUT>;
+			enum-name = "GPIO_BATT_PRES_ODL";
+		};
+		gpio_ec_cbi_wp: ec_cbi_wp {
+			gpios = <&gpio7 3 GPIO_OUTPUT>;
+		};
+		gpio_ec_edp_bl_en: ec_edp_bl_en {
+			gpios = <&gpiod 3 GPIO_OUTPUT>;
+			enum-name = "GPIO_ENABLE_BACKLIGHT";
+		};
+		gpio_ec_gsc_packet_mode: ec_gsc_packet_mode {
+			gpios = <&gpio7 5 GPIO_OUTPUT>;
+			enum-name = "GPIO_PACKET_MODE_EN";
+		};
+		gpio_ec_kb_bl_en_l: ec_kb_bl_en_l {
+			gpios = <&gpio8 6 GPIO_OUTPUT>;
+		};
+		gpio_ec_kso_02_inv: ec_kso_02_inv {
+			gpios = <&gpio1 7 (GPIO_OUTPUT | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_ec_mech_pwr_btn_l: ec_mech_pwr_btn_l {
+			gpios = <&gpio0 2 GPIO_INPUT>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		gpio_ec_prochot_in_l: ec_prochot_in_l {
+			gpios = <&gpiof 0 GPIO_INPUT>;
+		};
+		gpio_ec_prochot_odl: ec_prochot_odl {
+			gpios = <&gpio6 3 GPIO_ODR_HIGH>;
+		};
+		gpio_ec_rst_r_odl: ec_rst_r_odl {
+			gpios = <&gpio7 7 GPIO_INPUT>;
+		};
+		gpio_ec_soc_int_odl: ec_soc_int_odl {
+			gpios = <&gpio7 0 GPIO_ODR_LOW>;
+			enum-name = "GPIO_EC_INT_L";
+		};
+		gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl {
+			gpios = <&gpioc 1 GPIO_ODR_LOW>;
+			enum-name = "GPIO_PCH_PWRBTN_L";
+		};
+		gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l {
+			gpios = <&gpioa 6 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_rtcrst: ec_soc_rtcrst {
+			gpios = <&gpio7 6 GPIO_ODR_HIGH>;
+		};
+		gpio_ec_soc_wake_r_odl: ec_soc_wake_r_odl {
+			gpios = <&gpioc 0 GPIO_ODR_LOW>;
+		};
+		gpio_ec_spare_gpio01: ec_spare_gpio01 {
+			gpios = <&gpio0 1 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_ec_spare_gpio42: ec_spare_gpio42 {
+			gpios = <&gpio4 2 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpio66: ec_spare_gpio66 {
+			gpios = <&gpio6 6 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpio94: ec_spare_gpio94 {
+			gpios = <&gpio9 4 GPIO_OUTPUT>;
+		};
+		gpio_usb_a_low_pwr_od: usb_a_low_pwr_od {
+			gpios = <&gpioa 2 GPIO_OUTPUT_LOW>;
+		};
+		gpio_ec_spare_gpioa4: ec_spare_gpioa4 {
+			gpios = <&gpioa 4 GPIO_OUTPUT>;
+		};
+		gpio_usb_c1_rt_3p3_sx_en: usb_c1_rt_3p3_sx_en {
+			gpios = <&gpiob 1 0>;
+			no-auto-init;
+		};
+		gpio_ec_spare_gpioc7: ec_spare_gpioc7 {
+			gpios = <&gpioc 7 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpo32: ec_spare_gpo32 {
+			gpios = <&gpio3 2 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpo35: ec_spare_gpo35 {
+			gpios = <&gpio3 5 GPIO_OUTPUT>;
+		};
+		gpio_ec_wp_l: ec_wp_l {
+			gpios = <&gpioa 1 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_en_pp5000_fan: en_pp5000_fan {
+			gpios = <&gpio6 1 GPIO_OUTPUT>;
+		};
+		gpio_en_pp5000_usba_r: en_pp5000_usba_r {
+			gpios = <&gpiod 7 GPIO_OUTPUT>;
+		};
+		gpio_en_s5_rails: en_s5_rails {
+			gpios = <&gpiob 6 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_TEMP_SENSOR_POWER";
+		};
+		gpio_en_z1_rails: en_z1_rails {
+			gpios = <&gpio8 5 GPIO_OUTPUT>;
+		};
+		gpio_imvp92_vrrdy_od: imvp92_vrrdy_od {
+			gpios = <&gpio4 3 GPIO_INPUT>;
+		};
+		gpio_led_1_l: led_1_l {
+			gpios = <&gpioc 4 GPIO_OUTPUT_HIGH>;
+		};
+		gpio_led_2_l: led_2_l {
+			gpios = <&gpioc 3 GPIO_OUTPUT_HIGH>;
+		};
+		gpio_usb_a1_oc_pu_en: usb_a1_oc_pu_en {
+			gpios = <&gpioc 2 GPIO_OUTPUT_LOW>;
+		};
+		gpio_lid_open: lid_open {
+			gpios = <&gpiod 2 GPIO_INPUT>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+		gpio_seq_ec_all_sys_pg_od: seq_ec_all_sys_pg_od {
+			gpios = <&gpiof 4 GPIO_INPUT>;
+		};
+		gpio_seq_ec_rsmrst_odl: seq_ec_rsmrst_odl {
+			gpios = <&gpioe 2 GPIO_INPUT>;
+		};
+		gpio_slp_s3_ls_l: slp_s3_ls_l {
+			gpios = <&gpio4 1 GPIO_INPUT>;
+		};
+		gpio_sochot_odl: sochot_odl {
+			gpios = <&gpio9 6 GPIO_INPUT>;
+		};
+		gpio_soc_pwrok: soc_pwrok {
+			gpios = <&gpioa 5 GPIO_OUTPUT>;
+		};
+		gpio_sys_pwrok: sys_pwrok {
+			gpios = <&gpiob 0 GPIO_OUTPUT>;
+		};
+		gpio_sys_rst_odl: sys_rst_odl {
+			gpios = <&gpioc 5 GPIO_INPUT>;
+		};
+		gpio_sys_slp_s0ix_3v3_l: sys_slp_s0ix_3v3_l {
+			gpios = <&gpiod 5 GPIO_INPUT>;
+		};
+		gpio_usb_c0_bc12_int_odl: usb_c0_bc12_int_odl {
+			gpios = <&gpioc 6 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C0_BC12_INT_ODL";
+		};
+		gpio_usb_c0_ppc_int_odl: usb_c0_ppc_int_odl {
+			gpios = <&gpio6 2 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C0_PPC_INT_ODL";
+		};
+		gpio_usb_c0_rt_3p3_sx_en: usb_c0_rt_3p3_sx_en {
+			gpios = <&gpio0 3 GPIO_ODR_LOW>;
+		};
+		gpio_usb_c0_rt_int_odl: usb_c0_rt_int_odl {
+			gpios = <&gpioa 0 GPIO_INPUT>;
+		};
+		gpio_usb_c0_tcpc_int_odl: usb_c0_tcpc_int_odl {
+			gpios = <&gpioe 0 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_USB_C0_TCPC_INT_ODL";
+		};
+		gpio_usb_c0_tcpc_rst_odl: usb_c0_tcpc_rst_odl {
+			gpios = <&gpio6 7 GPIO_ODR_HIGH>;
+		};
+		gpio_usb_c1_bc12_int_odl: usb_c1_bc12_int_odl {
+			gpios = <&gpio5 0 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C1_BC12_INT_ODL";
+		};
+		gpio_usb_c1_frs_en: usb_c1_frs_en {
+			gpios = <&gpio8 3 GPIO_ODR_HIGH>;
+		};
+		gpio_usb_c1_ppc_int_odl: usb_c1_ppc_int_odl {
+			gpios = <&gpiof 5 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C1_PPC_INT_ODL";
+		};
+		gpio_usb_c1_rst_odl: usb_c1_rst_odl {
+			gpios = <&gpio3 7 GPIO_ODR_LOW>;
+		};
+		gpio_usb_c1_rt_int_odl: usb_c1_rt_int_odl {
+			gpios = <&gpio7 2 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_usb_c1_rt_rst_r_odl: usb_c1_rt_rst_r_odl {
+			gpios = <&gpio7 4 GPIO_ODR_HIGH>;
+		};
+		gpio_usb_c1_tcpc_int_odl: usb_c1_tcpc_int_odl {
+			gpios = <&gpio3 4 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_USB_C1_TCPC_INT_ODL";
+		};
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		i2c_ec_i2c_usb_c0_tcp: ec_i2c_usb_c0_tcp {
+			i2c-port = <&i2c1_0>;
+			enum-names = "I2C_PORT_USB_C0_TCPC";
+		};
+		i2c_ec_i2c_usb_c0_ppc_b: ec_i2c_usb_c0_ppc_b {
+			i2c-port = <&i2c2_0>;
+			enum-names = "I2C_PORT_PPC0";
+		};
+		i2c_ec_i2c_usb_c0_rt: ec_i2c_usb_c0_rt {
+			i2c-port = <&i2c3_0>;
+			enum-names = "I2C_PORT_USB_C0_RT";
+		};
+		i2c_ec_i2c_usb_c1_tcp: ec_i2c_usb_c1_tcp {
+			i2c-port = <&i2c4_1>;
+			enum-names = "I2C_PORT_USB_C1_TCPC";
+		};
+		i2c_ec_i2c_bat: ec_i2c_bat {
+			i2c-port = <&i2c5_0>;
+			enum-names = "I2C_PORT_BATTERY";
+		};
+		i2c_ec_i2c_usb_c1_mix: ec_i2c_usb_c1_mix {
+			i2c-port = <&i2c6_1>;
+			enum-names = "I2C_PORT_USB_1_MIX";
+		};
+		i2c_ec_i2c_mi: ec_i2c_mi {
+			i2c-port = <&i2c7_0>;
+			enum-names = "I2C_PORT_EEPROM";
+		};
+	};
+};
+
+&adc0 {
+	status = "okay";
+};
+
+&i2c0_0 {
+	status = "disabled";
+};
+
+&i2c1_0 {
+	status = "okay";
+};
+
+&i2c2_0 {
+	status = "okay";
+};
+
+&i2c3_0 {
+	status = "okay";
+};
+
+&i2c4_1 {
+	status = "okay";
+};
+
+&i2c5_0 {
+	status = "okay";
+};
+
+&i2c6_1 {
+	status = "okay";
+};
+
+&i2c7_0 {
+	status = "okay";
+};
+
+&i2c_ctrl0 {
+	status = "disabled";
+};
+
+&i2c_ctrl1 {
+	status = "okay";
+};
+
+&i2c_ctrl2 {
+	status = "okay";
+};
+
+&i2c_ctrl3 {
+	status = "okay";
+};
+
+&i2c_ctrl4 {
+	status = "okay";
+};
+
+&i2c_ctrl5 {
+	status = "okay";
+};
+
+&i2c_ctrl6 {
+	status = "okay";
+};
+
+&i2c_ctrl7 {
+	status = "okay";
+};
diff --git a/zephyr/program/rex/screebo/include/usb_config.h b/zephyr/program/rex/screebo/include/usb_config.h
new file mode 100644
index 0000000000..489beadc3b
--- /dev/null
+++ b/zephyr/program/rex/screebo/include/usb_config.h
@@ -0,0 +1,12 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __ZEPHYR_USB_CONFIG_H
+#define __ZEPHYR_USB_CONFIG_H
+
+extern uint32_t usb_db_type;
+extern uint32_t usb_mb_type;
+
+#endif /* __ZEPHYR_USB_CONFIG_H */
diff --git a/zephyr/program/rex/screebo/led_pins.dtsi b/zephyr/program/rex/screebo/led_pins.dtsi
new file mode 100644
index 0000000000..a71f0562d0
--- /dev/null
+++ b/zephyr/program/rex/screebo/led_pins.dtsi
@@ -0,0 +1,31 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	gpio-led-pins {
+		compatible = "cros-ec,gpio-led-pins";
+
+		combo_led: combo-led {
+			led-id = "EC_LED_ID_BATTERY_LED";
+			led-pins = <&gpio_led_1_l &gpio_led_2_l>;
+			color_off: color-off {
+				led-color = "LED_OFF";
+				led-values = <1 1>;
+			};
+
+			color_amber: color-amber {
+				led-color = "LED_AMBER";
+				br-color = "EC_LED_COLOR_AMBER";
+				led-values = <1 0>;
+			};
+
+			color_white: color-white {
+				led-color = "LED_WHITE";
+				br-color = "EC_LED_COLOR_WHITE";
+				led-values = <0 1>;
+			};
+		};
+	};
+};
diff --git a/zephyr/program/rex/screebo/led_policy.dtsi b/zephyr/program/rex/screebo/led_policy.dtsi
new file mode 100644
index 0000000000..f0665e1137
--- /dev/null
+++ b/zephyr/program/rex/screebo/led_policy.dtsi
@@ -0,0 +1,150 @@
+#include <dt-bindings/battery.h>
+
+/ {
+	led-colors {
+		compatible = "cros-ec,led-policy";
+
+		power-state-charge-lvl-1 {
+			charge-state = "LED_PWRS_CHARGE";
+
+			/* Battery display percent range (>= Empty, <= 94%) */
+			batt-lvl = <BATTERY_LEVEL_EMPTY 94>;
+
+			color-0 {
+				led-color = <&color_amber>;
+			};
+		};
+
+		power-state-charge-lvl-2 {
+			charge-state = "LED_PWRS_CHARGE";
+
+			/* Battery display percent range (>= 95) */
+			batt-lvl = <95 100>;
+
+			color-0 {
+				led-color = <&color_white>;
+			};
+		};
+
+		power-state-near-full {
+			charge-state = "LED_PWRS_CHARGE_NEAR_FULL";
+
+			color-0 {
+				led-color = <&color_white>;
+			};
+		};
+
+		power-state-discharge-s0 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S0";
+			/* Battery display percent range (>= 11%, <= 100%) */
+			batt-lvl = <(BATTERY_LEVEL_LOW + 1) BATTERY_LEVEL_FULL>;
+
+			color-0 {
+				led-color = <&color_white>;
+			};
+		};
+
+		power-state-discharge-s0-batt-low {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S0";
+			/* Battery display percent range (>= 0, <= 10%) */
+			batt-lvl = <BATTERY_LEVEL_EMPTY BATTERY_LEVEL_LOW>;
+
+			/* Amber 1 sec on, 3 sec off */
+			color-0 {
+				led-color = <&color_amber>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <3000>;
+			};
+		};
+
+		power-state-discharge-s3 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S3";
+
+			/* White 1 sec on, 3 sec off */
+			color-0 {
+				led-color = <&color_white>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <3000>;
+			};
+		};
+
+		power-state-discharge-s5 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S5";
+
+			color-0 {
+				led-color = <&color_off>;
+			};
+		};
+
+		power-state-error-s0 {
+			charge-state = "LED_PWRS_ERROR";
+			chipset-state = "POWER_S0";
+			/* Amber 1 sec on, 1 sec off */
+			color-0 {
+				led-color = <&color_amber>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <1000>;
+			};
+		};
+
+		power-state-error-s3 {
+			charge-state = "LED_PWRS_ERROR";
+			chipset-state = "POWER_S3";
+			/* White 1 sec on, 3 sec off */
+			color-0 {
+				led-color = <&color_white>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <3000>;
+			};
+		};
+
+		power-state-error-s5 {
+			charge-state = "LED_PWRS_ERROR";
+			chipset-state = "POWER_S5";
+
+			color-0 {
+				led-color = <&color_off>;
+			};
+		};
+
+		power-state-forced-idle {
+			charge-state = "LED_PWRS_FORCED_IDLE";
+
+			/* White 2 sec on, Amber 2 sec on */
+			color-0 {
+				led-color = <&color_white>;
+				period-ms = <2000>;
+			};
+			color-1 {
+				led-color = <&color_amber>;
+				period-ms = <2000>;
+			};
+		};
+
+		power-state-idle {
+			charge-state = "LED_PWRS_IDLE";
+			chipset-state = "POWER_S5";
+
+			/* LED off when S5, others do not change */
+			color-0 {
+				led-color = <&color_off>;
+			};
+		};
+	};
+};
diff --git a/zephyr/program/rex/screebo/project.conf b/zephyr/program/rex/screebo/project.conf
new file mode 100644
index 0000000000..7d2fbcffd0
--- /dev/null
+++ b/zephyr/program/rex/screebo/project.conf
@@ -0,0 +1,38 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Screebo-NPCX9 variant-board-specific Kconfig settings.
+CONFIG_BOARD_SCREEBO=y
+
+# Battery Configuration
+CONFIG_PLATFORM_EC_BATT_HOST_FULL_FACTOR=99
+CONFIG_PLATFORM_EC_I2C_NACK_RETRY_COUNT=10
+CONFIG_PLATFORM_EC_SMBUS_PEC=y
+
+# Buttons
+CONFIG_PLATFORM_EC_VOLUME_BUTTONS=n
+
+# Keyboard
+CONFIG_PLATFORM_EC_KEYBOARD_REFRESH_ROW3=y
+CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI3=y
+
+# No sensors
+CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSO=n
+CONFIG_PLATFORM_EC_ACCEL_LIS2DW12=n
+CONFIG_PLATFORM_EC_ACCEL_FIFO=n
+CONFIG_PLATFORM_EC_ALS_TCS3400=n
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=n
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=n
+CONFIG_PLATFORM_EC_CONSOLE_CMD_I2C_SPEED=n
+CONFIG_PLATFORM_EC_DYNAMIC_MOTION_SENSOR_COUNT=n
+CONFIG_PLATFORM_EC_GMR_TABLET_MODE=n
+CONFIG_PLATFORM_EC_LID_ANGLE=n
+CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=n
+CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=n
+CONFIG_PLATFORM_EC_TABLET_MODE=n
+CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=n
+
+# USBC
+CONFIG_PLATFORM_EC_PD_MAX_CURRENT_MA=3250
+CONFIG_PLATFORM_EC_PD_MAX_POWER_MW=65000
diff --git a/zephyr/program/rex/screebo/project.overlay b/zephyr/program/rex/screebo/project.overlay
new file mode 100644
index 0000000000..6dba5cea26
--- /dev/null
+++ b/zephyr/program/rex/screebo/project.overlay
@@ -0,0 +1,221 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Rex program common DTSI includes */
+#include "../fan.dtsi"
+#include "gpio.dtsi"
+#include "../interrupts.dtsi"
+#include "../keyboard.dtsi"
+#include "../power_signals.dtsi"
+#include "../rex.dtsi"
+#include "../usbc.dtsi"
+
+/* Screebo project DTS includes */
+#include "cbi.dtsi"
+#include "led_pins.dtsi"
+#include "led_policy.dtsi"
+#include "temp_sensors.dtsi"
+
+/ {
+	named-gpios {
+		/delete-node/ ec-i2c-sensor-scl;
+		/delete-node/ ec-i2c-sensor-sda;
+
+		ioex_usb_c1_rt_rst_ls_l: usb_c1_rt_rst_ls_l {
+			gpios = <&ioex_c1_port0 7 0>;
+			no-auto-init;
+		};
+		ioex_usb_c1_frs_en: usb_c1_frs_en {
+			gpios = <&ioex_c1_port0 6 0>;
+			no-auto-init;
+		};
+
+	};
+
+	unused-pins {
+		compatible = "unused-gpios";
+
+		unused-gpios =
+			<&gpiob 4 0>, /* ec-i2c-sensor-sda */
+			<&gpiob 5 0>, /* ec-i2c-sensor-scl */
+			<&gpio5 6 0>, /* ec_imu_int_r_l */
+			<&gpiod 4 0>, /* ec_als_rgb_int_r_l */
+			<&gpio8 1 0>, /* ec_accel_int_r_l */
+			<&gpio9 7 0>, /* ec_volup_btn_odl */
+			<&gpio9 3 0>, /* ec_voldn_btn_odl */
+			<&gpio9 5 0>, /* tablet_mode_l */
+			<&gpio6 0 0>; /* led_4_l */
+	};
+
+	gpio-interrupts {
+		/delete-node/ ec_imu;
+		/delete-node/ ec_als_rgb;
+		/delete-node/ ec_accel;
+		/delete-node/ volume_up;
+		/delete-node/ volume_down;
+		usb_c0_ppc {
+			handler = "screebo_ppc_interrupt";
+		};
+		usb_c1_ppc {
+			handler = "screebo_ppc_interrupt";
+		};
+	};
+
+	batteries {
+		default_battery: celxpert_c340152 {
+			compatible = "celxpert,c340152", "battery-smart";
+		};
+	};
+
+	aliases {
+		/* GPIO37 */
+		nct-usb-c1-rst-odl = &gpio_usb_c1_rst_odl;
+
+		/* GPIO72 */
+		hbr-usb-c1-rt-int-odl = &gpio_usb_c1_rt_int_odl;
+
+		/* GPIOB1 */
+		hbr-usb-c1-rt-pwr-en = &gpio_usb_c1_rt_3p3_sx_en;
+
+		/* NCT38xx_C1 GPIO07 */
+		hbr-usb-c1-rt-rst = &ioex_usb_c1_rt_rst_ls_l;
+
+		/* NCT38xx_C1 GPIO06 */
+		syv-usb-c1-frs-en = &ioex_usb_c1_frs_en;
+	};
+};
+
+/* ADC and GPIO alt-function specifications */
+&adc0 {
+	pinctrl-0 = <&adc0_chan0_gp45
+		     &adc0_chan1_gp44
+		     &adc0_chan3_gp42
+		     &adc0_chan7_gpe1
+		     &adc0_chan8_gpf1
+		     &adc0_chan11_gpc7>;
+	pinctrl-names = "default";
+};
+
+&i2c3_0 {
+	usb_c1_hb_retimer: jhl9040r-c1@54 {
+		compatible = "intel,jhl9040r";
+		reg = <0x54>;
+		ls-en-pin = <&gpio_usb_c1_rt_3p3_sx_en>;
+		int-pin = <&gpio_usb_c1_rt_int_odl>;
+		reset-pin = <&ioex_usb_c1_rt_rst_ls_l>;
+	};
+};
+
+&i2c4_1 {
+	/delete-node/ rt1716@4e;
+
+	tcpc_nct38xx_port1: nct38xx@73 {
+		compatible = "nuvoton,nct38xx";
+		gpio-dev = <&nct3807_C1>;
+		reg = <0x73>;
+		tcpc-flags = <(
+			TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V)>;
+		/* a duplicate of the <&gpio_usb_c1_tcpc_int_odl> node in
+		 * "named-gpios". This is the Zephyr preferred style,
+		 * the "named-gpios" node will be dealt with at a later date.
+		 */
+		irq-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
+		/* a duplicate of the <&gpio_usb_c1_rst_odl> node in
+		 * "named-gpios". This is the Zephyr preferred style,
+		 * the "named-gpios" node will be dealt with at a later date.
+		 */
+		rst-gpios = <&gpio3 7 0>;
+	};
+
+	nct3807_C1: nct3807_C1@73 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nuvoton,nct38xx-gpio";
+		reg = <0x73>;
+		label = "NCT3807_C1";
+
+		ioex_c1_port0: gpio@0 {
+			compatible = "nuvoton,nct38xx-gpio-port";
+			reg = <0x0>;
+			label = "NCT3807_C1_GPIO0";
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <8>;
+			pin_mask = <0xff>;
+			pinmux_mask = <0xf7>;
+		};
+		ioex_c1_port1: gpio@1 {
+			compatible = "nuvoton,nct38xx-gpio-port";
+			reg = <0x1>;
+			label = "NCT3807_C1_GPIO1";
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <8>;
+			pin_mask = <0xff>;
+		};
+	};
+
+	nct3808_alert_1 {
+		compatible = "nuvoton,nct38xx-gpio-alert";
+		irq-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
+		nct38xx-dev = <&nct3807_C1>;
+		label = "NCT3807_ALERT_0";
+	};
+
+	tcpc_ps8815_port1: ps8xxx@b {
+		compatible = "parade,ps8xxx";
+		reg = <0xb>;
+		tcpc-flags = <(
+			TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V |
+			TCPC_FLAGS_CONTROL_VCONN |
+			TCPC_FLAGS_CONTROL_FRS)>;
+		/* a duplicate of the <&gpio_usb_c1_tcpc_int_odl> node in
+		 * "named-gpios". This is the Zephyr preferred style,
+		 * the "named-gpios" node will be dealt with at a later date.
+		 */
+		irq-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
+		/* a duplicate of the <&gpio_usb_c1_rt_rst_r_odl> node in
+		 * "named-gpios". This is the Zephyr preferred style,
+		 * the "named-gpios" node will be dealt with at a later date.
+		 */
+		rst-gpios = <&gpio7 4 0>;
+		is-alt;
+	};
+};
+
+&i2c6_1 {
+	/delete-node/ usb-c1-kb8010-retimer@8;
+	/delete-node/ ktu1125@38;
+	/delete-node/ ppc_syv@40;
+	/delete-node/ usb-c1-anx7452-retimer@10;
+
+	ppc_syv_port1: ppc_syv@40 {
+		compatible = "silergy,syv682x";
+		status = "okay";
+		reg = <0x40>;
+		frs_en_gpio = <&ioex_usb_c1_frs_en>;
+	};
+};
+
+&usbc_port0 {
+	usb_mux_chain_usb3_port0: usb-mux-chain-0-usb3 {
+		compatible = "cros-ec,usb-mux-chain";
+		usb-muxes = <&virtual_mux_c0>;
+		alternative-chain;
+	};
+};
+
+&usbc_port1 {
+	/delete-node/ usb-mux-chain-1-anx7452;
+	/delete-node/ usb-mux-chain-1-kb8010;
+
+	ppc = <&ppc_syv_port1>;
+	tcpc = <&tcpc_nct38xx_port1>;
+	usb-mux-chain-1 {
+		usb-muxes = <&usb_c1_hb_retimer &virtual_mux_c1>;
+	};
+};
diff --git a/zephyr/program/rex/screebo/src/keyboard.c b/zephyr/program/rex/screebo/src/keyboard.c
new file mode 100644
index 0000000000..5a9818ba7a
--- /dev/null
+++ b/zephyr/program/rex/screebo/src/keyboard.c
@@ -0,0 +1,28 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+
+static const struct ec_response_keybd_config screebo_kb = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &screebo_kb;
+}
diff --git a/zephyr/program/rex/screebo/src/usb_config.c b/zephyr/program/rex/screebo/src/usb_config.c
new file mode 100644
index 0000000000..cb879b79a8
--- /dev/null
+++ b/zephyr/program/rex/screebo/src/usb_config.c
@@ -0,0 +1,179 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Screebo board-specific USB-C configuration */
+
+#include "console.h"
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+#include "driver/ppc/nx20p348x.h"
+#include "driver/tcpm/ps8xxx_public.h"
+#include "hooks.h"
+#include "ppc/syv682x_public.h"
+#include "system.h"
+#include "usb_config.h"
+#include "usb_pd.h"
+#include "usbc/ppc.h"
+#include "usbc/tcpci.h"
+#include "usbc/usb_muxes.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/logging/log.h>
+
+#include <dt-bindings/gpio_defines.h>
+
+LOG_MODULE_REGISTER(screebo, LOG_LEVEL_INF);
+
+uint32_t usb_db_type;
+uint32_t usb_mb_type;
+
+void screebo_ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_PPC_INT_ODL:
+		if (usb_db_type == FW_USB_DB_USB3) {
+			nx20p348x_interrupt(USBC_PORT_C1);
+		} else {
+			syv682x_interrupt(USBC_PORT_C1);
+		}
+		break;
+	default:
+		break;
+	}
+}
+
+void board_reset_pd_mcu(void)
+{
+	/* Reset TCPC0 */
+	reset_nct38xx_port(USBC_PORT_C0);
+
+	/* Reset TCPC1 */
+	if (usb_db_type == FW_USB_DB_USB3) {
+		if (tcpc_config[1].rst_gpio.port) {
+			gpio_pin_set_dt(&tcpc_config[1].rst_gpio, 1);
+			msleep(PS8XXX_RESET_DELAY_MS);
+			gpio_pin_set_dt(&tcpc_config[1].rst_gpio, 0);
+			msleep(PS8815_FW_INIT_DELAY_MS);
+		}
+	} else {
+		reset_nct38xx_port(USBC_PORT_C1);
+	}
+}
+
+static int gpio_unused(const struct gpio_dt_spec *spec)
+{
+	return gpio_pin_configure(spec->port, spec->pin, GPIO_INPUT_PULL_UP);
+}
+
+static void setup_runtime_gpios(void)
+{
+	int ret;
+
+	ret = cros_cbi_get_fw_config(FW_USB_DB, &usb_db_type);
+	if (ret != EC_SUCCESS) {
+		LOG_INF("Failed to get FW_USB_DB from CBI");
+		usb_db_type = FW_USB_DB_NOT_CONNECTED;
+	}
+
+	ret = cros_cbi_get_fw_config(FW_USB_MB, &usb_mb_type);
+	if (ret != 0) {
+		LOG_ERR("Failed to get FW_USB_MB from CBI");
+		usb_mb_type = FW_USB_MB_UNKNOWN;
+	}
+
+	switch (usb_db_type) {
+	case FW_USB_DB_USB3:
+		gpio_unused(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_rst_odl));
+		gpio_unused(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_rt_int_odl));
+		gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(ps_usb_c1_rt_rst_odl),
+				      (GPIO_ODR_HIGH | GPIO_ACTIVE_LOW));
+		gpio_unused(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_frs_en));
+		gpio_unused(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_rt_3p3_sx_en));
+		break;
+
+	case FW_USB_DB_USB4_HB:
+		gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(nct_usb_c1_rst_odl),
+				      (GPIO_ODR_HIGH | GPIO_ACTIVE_LOW));
+		gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(hbr_usb_c1_rt_int_odl),
+				      GPIO_INPUT);
+		gpio_unused(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_rt_rst_r_odl));
+		gpio_unused(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_frs_en));
+		gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(hbr_usb_c1_rt_pwr_en),
+				      GPIO_OUTPUT_LOW);
+		gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(hbr_usb_c1_rt_rst),
+				      GPIO_OUTPUT);
+		gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(syv_usb_c1_frs_en),
+				      GPIO_OUTPUT_LOW);
+		break;
+
+	default:
+		/* GPIO37 */
+		gpio_unused(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_rst_odl));
+		/* GPIO72 */
+		gpio_unused(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_rt_int_odl));
+		/* GPIO74 */
+		gpio_unused(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_rt_rst_r_odl));
+		/* GPIO83 */
+		gpio_unused(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_frs_en));
+		/* GPIOB1 */
+		gpio_unused(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_rt_3p3_sx_en));
+		break;
+	}
+
+	if (usb_mb_type != FW_USB_MB_USB4_HB) {
+		/* Just HBR will use these gpios */
+		gpio_unused(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_rt_3p3_sx_en));
+		gpio_unused(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_rt_int_odl));
+		gpio_unused(GPIO_DT_FROM_NODELABEL(ioex_usb_c0_rt_rst_ls_l));
+	}
+}
+DECLARE_HOOK(HOOK_INIT, setup_runtime_gpios, HOOK_PRIO_FIRST);
+
+static void setup_alt_db(void)
+{
+	if (usb_db_type == FW_USB_DB_USB3) {
+		LOG_INF("USB DB: USB3 DB connected");
+		USB_MUX_ENABLE_ALTERNATIVE(usb_mux_chain_ps8815_port1);
+		TCPC_ENABLE_ALTERNATE_BY_NODELABEL(USBC_PORT_C1,
+						   tcpc_ps8815_port1);
+		PPC_ENABLE_ALTERNATE_BY_NODELABEL(USBC_PORT_C1,
+						  ppc_nx20p_port1);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, setup_alt_db, HOOK_PRIO_POST_I2C);
+
+static void setup_mb_usb(void)
+{
+	if (usb_mb_type == FW_USB_MB_USB3) {
+		LOG_INF("USB MB: C0 port is USB3");
+		USB_MUX_ENABLE_ALTERNATIVE(usb_mux_chain_usb3_port0);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, setup_mb_usb, HOOK_PRIO_POST_I2C);
+
+__override bool board_is_tbt_usb4_port(int port)
+{
+	/* Both C0 and C1 are USB4 port */
+	if (usb_mb_type == FW_USB_MB_USB4_HB)
+		return true;
+
+	return false;
+}
+
+__override uint8_t board_get_usb_pd_port_count(void)
+{
+	switch (usb_db_type) {
+	case FW_USB_DB_USB3:
+	case FW_USB_DB_USB4_HB:
+		return 2;
+	default:
+		return 1;
+	}
+}
diff --git a/zephyr/program/rex/screebo/temp_sensors.dtsi b/zephyr/program/rex/screebo/temp_sensors.dtsi
new file mode 100644
index 0000000000..f254d16ff9
--- /dev/null
+++ b/zephyr/program/rex/screebo/temp_sensors.dtsi
@@ -0,0 +1,100 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <cros/thermistor/thermistor.dtsi>
+
+/ {
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		adc_ddr_soc: ddr_soc {
+			enum-name = "ADC_TEMP_SENSOR_1";
+			io-channels = <&adc0 0>;
+		};
+		adc_vcc: vcc {
+			enum-name = "ADC_TEMP_SENSOR_2";
+			io-channels = <&adc0 1>;
+		};
+		adc_ambient: ambient {
+			enum-name = "ADC_TEMP_SENSOR_3";
+			io-channels = <&adc0 8>;
+		};
+		adc_charger: charger {
+			enum-name = "ADC_TEMP_SENSOR_4";
+			io-channels = <&adc0 7>;
+		};
+		adc_hw_shutdown: hw_shutdown {
+			enum-name = "ADC_TEMP_SENSOR_5";
+			io-channels = <&adc0 3>;
+		};
+		adc_typec: typec {
+			enum-name = "ADC_TEMP_SENSOR_6";
+			io-channels = <&adc0 11>;
+		};
+	};
+
+	temp_ddr_soc: ddr_soc {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_30K9_47K_4050B>;
+		adc = <&adc_ddr_soc>;
+	};
+	temp_ambient: ambient {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_30K9_47K_4050B>;
+		adc = <&adc_ambient>;
+	};
+	temp_charger: charger {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_30K9_47K_4050B>;
+		adc = <&adc_charger>;
+	};
+	temp_vcc: vcc {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_30K9_47K_4050B>;
+		adc = <&adc_vcc>;
+	};
+	temp_hw_shutdown: hw_shutdown {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_30K9_47K_4050B>;
+		adc = <&adc_hw_shutdown>;
+	};
+	temp_typec: typec {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_30K9_47K_4050B>;
+		adc = <&adc_typec>;
+	};
+
+	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
+		ddr_soc {
+			temp_fan_off = <35>;
+			temp_fan_max = <60>;
+			temp_host_high = <90>;
+			temp_host_halt = <95>;
+			temp_host_release_high = <85>;
+			sensor = <&temp_ddr_soc>;
+		};
+		ambient {
+			temp_fan_off = <30>;
+			temp_fan_max = <50>;
+			temp_host_high = <65>;
+			temp_host_halt = <75>;
+			temp_host_release_high = <60>;
+			sensor = <&temp_ambient>;
+		};
+		charger {
+			temp_fan_off = <35>;
+			temp_fan_max = <85>;
+			temp_host_high = <100>;
+			temp_host_halt = <110>;
+			temp_host_release_high = <95>;
+			sensor = <&temp_charger>;
+		};
+	};
+};
+
+&thermistor_3V3_30K9_47K_4050B {
+	status = "okay";
+};
diff --git a/zephyr/program/rex/src/board_power.c b/zephyr/program/rex/src/board_power.c
new file mode 100644
index 0000000000..55561dec43
--- /dev/null
+++ b/zephyr/program/rex/src/board_power.c
@@ -0,0 +1,65 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "gpio/gpio.h"
+#include "gpio_signal.h"
+#include "system_boot_time.h"
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/logging/log.h>
+
+#include <ap_power/ap_power.h>
+#include <ap_power/ap_power_events.h>
+#include <ap_power/ap_power_interface.h>
+#include <ap_power_override_functions.h>
+#include <power_signals.h>
+#include <x86_power_signals.h>
+
+LOG_MODULE_DECLARE(ap_pwrseq, LOG_LEVEL_INF);
+
+#if defined(CONFIG_X86_NON_DSX_PWRSEQ_MTL) || \
+	defined(CONFIG_TEST_X86_NON_DSX_PWRSEQ_MTL)
+#define X86_NON_DSX_MTL_FORCE_SHUTDOWN_TO_MS 50
+
+void board_ap_power_force_shutdown(void)
+{
+	int timeout_ms = X86_NON_DSX_MTL_FORCE_SHUTDOWN_TO_MS;
+
+	/* Turn off PCH_RMSRST to meet tPCH12 */
+	power_signal_set(PWR_EC_PCH_RSMRST, 0);
+
+	/* Turn off PRIM load switch. */
+	power_signal_set(PWR_EN_PP3300_A, 0);
+
+	/* Wait RSMRST to be off. */
+	while (power_signal_get(PWR_RSMRST) && (timeout_ms > 0)) {
+		k_msleep(1);
+		timeout_ms--;
+	};
+
+	if (power_signal_get(PWR_RSMRST)) {
+		LOG_WRN("RSMRST_ODL didn't go low!  Assuming G3.");
+	}
+}
+
+void board_ap_power_action_g3_s5(void)
+{
+	/* Turn on the PP3300_PRIM rail. */
+	power_signal_set(PWR_EN_PP3300_A, 1);
+
+	update_ap_boot_time(ARAIL);
+
+	if (!power_wait_signals_timeout(
+		    IN_PGOOD_ALL_CORE,
+		    AP_PWRSEQ_DT_VALUE(wait_signal_timeout))) {
+		ap_power_ev_send_callbacks(AP_POWER_PRE_INIT);
+	}
+}
+
+bool board_ap_power_check_power_rails_enabled(void)
+{
+	return power_signal_get(PWR_EN_PP3300_A);
+}
+#endif /* CONFIG_X86_NON_DSX_PWRSEQ_MTL */
diff --git a/zephyr/program/rex/src/usb_pd_policy.c b/zephyr/program/rex/src/usb_pd_policy.c
new file mode 100644
index 0000000000..a7ac5aab4f
--- /dev/null
+++ b/zephyr/program/rex/src/usb_pd_policy.c
@@ -0,0 +1,81 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Shared USB-C policy for Rex boards */
+
+#include "charge_manager.h"
+#include "chipset.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "ioexpander.h"
+#include "power_signals.h"
+#include "system.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#include <zephyr/drivers/gpio.h>
+
+int pd_check_vconn_swap(int port)
+{
+	/* Allow VCONN swaps when gpio_en_z1_rails is enabled. */
+	const struct gpio_dt_spec *const en_z1_rails_gpio =
+		GPIO_DT_FROM_NODELABEL(gpio_en_z1_rails);
+
+	return gpio_pin_get_dt(en_z1_rails_gpio);
+}
+
+void pd_power_supply_reset(int port)
+{
+	/* Disable VBUS. */
+	ppc_vbus_source_enable(port, 0);
+
+	/* Enable discharge if we were previously sourcing 5V */
+	if (IS_ENABLED(CONFIG_USB_PD_DISCHARGE))
+		pd_set_vbus_discharge(port, 1);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	/* Disable charging. */
+	rv = ppc_vbus_sink_enable(port, 0);
+	if (rv)
+		return rv;
+
+	if (IS_ENABLED(CONFIG_USB_PD_DISCHARGE)) {
+		pd_set_vbus_discharge(port, 0);
+	}
+
+	/* Provide Vbus. */
+	rv = ppc_vbus_source_enable(port, 1);
+	if (rv) {
+		return rv;
+	}
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+/* Used by Vbus discharge common code with CONFIG_USB_PD_DISCHARGE */
+int board_vbus_source_enabled(int port)
+{
+	return ppc_is_sourcing_vbus(port);
+}
+
+/* Used by USB charger task with CONFIG_USB_PD_5V_EN_CUSTOM */
+int board_is_sourcing_vbus(int port)
+{
+	return board_vbus_source_enabled(port);
+}
diff --git a/zephyr/program/rex/src/usbc_config.c b/zephyr/program/rex/src/usbc_config.c
new file mode 100644
index 0000000000..509ccd8ec7
--- /dev/null
+++ b/zephyr/program/rex/src/usbc_config.c
@@ -0,0 +1,218 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery_fuel_gauge.h"
+#include "charge_manager.h"
+#include "charge_ramp.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "driver/charger/isl9241.h"
+#include "driver/ppc/nx20p348x.h"
+#include "driver/retimer/bb_retimer_public.h"
+#include "driver/tcpm/nct38xx.h"
+#include "driver/tcpm/tcpci.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "ioexpander.h"
+#include "ppc/syv682x_public.h"
+#include "system.h"
+#include "task.h"
+#include "usb_mux.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+
+#include <stdbool.h>
+
+#include <zephyr/drivers/espi.h>
+#include <zephyr/drivers/gpio.h>
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/* eSPI device */
+#define espi_dev DEVICE_DT_GET(DT_CHOSEN(cros_ec_espi))
+
+/*******************************************************************/
+/* USB-C Configuration Start */
+
+static void usbc_interrupt_init(void)
+{
+	/* Only reset TCPC if not sysjump */
+	if (!system_jumped_late()) {
+		board_reset_pd_mcu();
+	}
+
+	/* Enable PPC interrupts. */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_ppc));
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_ppc));
+
+	/* Enable BC 1.2 interrupts */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_bc12));
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_bc12));
+
+	/* Enable SBU fault interrupts */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_sbu_fault));
+}
+DECLARE_HOOK(HOOK_INIT, usbc_interrupt_init, HOOK_PRIO_POST_I2C);
+
+__override void board_overcurrent_event(int port, int is_overcurrented)
+{
+	/*
+	 * Meteorlake PCH uses Virtual Wire for over current error,
+	 * hence Send 'Over Current Virtual Wire' eSPI signal.
+	 */
+	espi_send_vwire(espi_dev, port + ESPI_VWIRE_SIGNAL_SLV_GPIO_0,
+			!is_overcurrented);
+}
+
+void sbu_fault_interrupt(enum gpio_signal signal)
+{
+	int port = USBC_PORT_C0;
+
+	CPRINTSUSB("C%d: SBU fault", port);
+	pd_handle_overcurrent(port);
+}
+
+void reset_nct38xx_port(int port)
+{
+	const struct gpio_dt_spec *reset_gpio_l;
+	const struct device *ioex_port0, *ioex_port1;
+
+	/* TODO(b/225189538): Save and restore ioex signals */
+	if (port == USBC_PORT_C0) {
+		reset_gpio_l = &tcpc_config[0].rst_gpio;
+		ioex_port0 = DEVICE_DT_GET(DT_NODELABEL(ioex_c0_port0));
+		ioex_port1 = DEVICE_DT_GET(DT_NODELABEL(ioex_c0_port1));
+#if DT_NODE_EXISTS(DT_NODELABEL(nct3807_C1))
+	} else if (port == USBC_PORT_C1) {
+		reset_gpio_l = &tcpc_config[1].rst_gpio;
+		ioex_port0 = DEVICE_DT_GET(DT_NODELABEL(ioex_c1_port0));
+		ioex_port1 = DEVICE_DT_GET(DT_NODELABEL(ioex_c1_port1));
+#endif
+	} else {
+		/* Invalid port: do nothing */
+		return;
+	}
+
+	gpio_pin_set_dt(reset_gpio_l, 1);
+	msleep(NCT38XX_RESET_HOLD_DELAY_MS);
+	gpio_pin_set_dt(reset_gpio_l, 0);
+	nct38xx_reset_notify(port);
+	if (NCT3807_RESET_POST_DELAY_MS != 0) {
+		msleep(NCT3807_RESET_POST_DELAY_MS);
+	}
+
+	/* Re-enable the IO expander pins */
+	gpio_reset_port(ioex_port0);
+	gpio_reset_port(ioex_port1);
+}
+
+void bc12_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_BC12_INT_ODL:
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+		break;
+	case GPIO_USB_C1_BC12_INT_ODL:
+		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+		break;
+	default:
+		break;
+	}
+}
+
+static void board_disable_charger_ports(void)
+{
+	int i;
+
+	CPRINTSUSB("Disabling all charger ports");
+
+	/* Disable all ports. */
+	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+		/*
+		 * If this port had booted in dead battery mode, go
+		 * ahead and reset it so EN_SNK responds properly.
+		 */
+		if (nct38xx_get_boot_type(i) == NCT38XX_BOOT_DEAD_BATTERY) {
+			reset_nct38xx_port(i);
+			pd_set_error_recovery(i);
+		}
+
+		/*
+		 * Do not return early if one fails otherwise we can
+		 * get into a boot loop assertion failure.
+		 */
+		if (ppc_vbus_sink_enable(i, 0)) {
+			CPRINTSUSB("Disabling C%d as sink failed.", i);
+		}
+	}
+}
+
+int board_set_active_charge_port(int port)
+{
+	bool is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int i;
+
+	if (port == CHARGE_PORT_NONE) {
+		board_disable_charger_ports();
+		return EC_SUCCESS;
+	} else if (!is_valid_port) {
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * Check if we can reset any ports in dead battery mode
+	 *
+	 * The NCT3807 may continue to keep EN_SNK low on the dead battery port
+	 * and allow a dangerous level of voltage to pass through to the initial
+	 * charge port (see b/183660105).  We must reset the ports if we have
+	 * sufficient battery to do so, which will bring EN_SNK back under
+	 * normal control.
+	 */
+	if (port == USBC_PORT_C0 &&
+	    nct38xx_get_boot_type(port) == NCT38XX_BOOT_DEAD_BATTERY) {
+		/* Handle dead battery boot case */
+		CPRINTSUSB("Found dead battery on C0");
+		/*
+		 * If we have battery, get this port reset ASAP.
+		 * This means temporarily rejecting charge manager
+		 * sets to it.
+		 */
+		if (pd_is_battery_capable()) {
+			reset_nct38xx_port(port);
+			pd_set_error_recovery(port);
+		}
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (ppc_is_sourcing_vbus(port)) {
+		CPRINTSUSB("Skip enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTSUSB("New charge port: C%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+		if (i == port) {
+			continue;
+		}
+		if (ppc_vbus_sink_enable(i, 0)) {
+			CPRINTSUSB("C%d: sink path disable failed.", i);
+		}
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTSUSB("C%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/zephyr/program/rex/temp_sensors.dtsi b/zephyr/program/rex/temp_sensors.dtsi
new file mode 100644
index 0000000000..3c90dc9d8d
--- /dev/null
+++ b/zephyr/program/rex/temp_sensors.dtsi
@@ -0,0 +1,69 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <cros/thermistor/thermistor.dtsi>
+
+/ {
+	temp_ddr_soc: ddr_soc {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_30K9_47K_4050B>;
+		adc = <&adc_temp_sensor_1>;
+	};
+	temp_ambient: ambient {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_30K9_47K_4050B>;
+		adc = <&adc_temp_sensor_2>;
+	};
+	temp_charger: charger {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_30K9_47K_4050B>;
+		adc = <&adc_temp_sensor_3>;
+	};
+	temp_wwan: wwan {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_30K9_47K_4050B>;
+		adc = <&adc_temp_sensor_4>;
+	};
+
+	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
+		ddr_soc {
+			temp_fan_off = <35>;
+			temp_fan_max = <60>;
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			sensor = <&temp_ddr_soc>;
+		};
+		ambient {
+			temp_fan_off = <35>;
+			temp_fan_max = <60>;
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			sensor = <&temp_ambient>;
+		};
+		charger {
+			temp_fan_off = <35>;
+			temp_fan_max = <65>;
+			temp_host_high = <105>;
+			temp_host_halt = <120>;
+			temp_host_release_high = <90>;
+			sensor = <&temp_charger>;
+		};
+		wwan {
+			temp_fan_off = <35>;
+			temp_fan_max = <60>;
+			temp_host_high = <130>;
+			temp_host_halt = <130>;
+			temp_host_release_high = <100>;
+			sensor = <&temp_wwan>;
+		};
+	};
+};
+
+&thermistor_3V3_30K9_47K_4050B {
+	status = "okay";
+};
diff --git a/zephyr/program/rex/usbc.dtsi b/zephyr/program/rex/usbc.dtsi
new file mode 100644
index 0000000000..ada1700ed2
--- /dev/null
+++ b/zephyr/program/rex/usbc.dtsi
@@ -0,0 +1,66 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		usbc_port0: port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+			bc12 = <&bc12_port0>;
+			ppc = <&ppc_port0_syv>;
+			tcpc = <&tcpc_port0>;
+			chg = <&charger>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_c0_hb_retimer
+					     &virtual_mux_c0>;
+			};
+		};
+		port0-muxes {
+			virtual_mux_c0: virtual-mux-c0 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+
+		usbc_port1: port1@1 {
+			compatible = "named-usbc-port";
+			reg = <1>;
+			bc12 = <&bc12_port1>;
+			usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_c1>;
+			};
+			usb_mux_chain_ps8815_port1: usb-mux-chain-ps8815-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_c1 &tcpci_mux_c1>;
+				alternative-chain;
+			};
+			usb_mux_chain_anx7452_port1: usb-mux-chain-1-anx7452 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_c1_anx7452_retimer
+					     &virtual_mux_c1>;
+				alternative-chain;
+			};
+			usb_mux_chain_kb8010_port1: usb-mux-chain-1-kb8010 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_c1_kb8010_retimer
+					     &virtual_mux_c1>;
+				alternative-chain;
+			};
+		};
+		port1-muxes {
+			tcpci_mux_c1: tcpci-mux-c1 {
+				compatible = "cros-ec,usbc-mux-tcpci";
+				hpd-update = "ps8xxx_tcpc_update_hpd_status";
+			};
+			virtual_mux_c1: virtual-mux-c1 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+	};
+};
diff --git a/zephyr/program/roach/BUILD.py b/zephyr/program/roach/BUILD.py
new file mode 100644
index 0000000000..1f9c3dfbbf
--- /dev/null
+++ b/zephyr/program/roach/BUILD.py
@@ -0,0 +1,21 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Define zmake projects for roach."""
+
+
+def register_variant(project_name):
+    """Register a variant of Roach."""
+    register_binman_project(
+        project_name=project_name,
+        zephyr_board="it82202ax-512",
+        dts_overlays=[here / project_name / "project.overlay"],
+        kconfig_files=[
+            here / "program.conf",
+            here / project_name / "project.conf",
+        ],
+    )
+
+
+register_variant("roach")
diff --git a/zephyr/program/roach/CMakeLists.txt b/zephyr/program/roach/CMakeLists.txt
new file mode 100644
index 0000000000..3ff6832de3
--- /dev/null
+++ b/zephyr/program/roach/CMakeLists.txt
@@ -0,0 +1,15 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+
+zephyr_library_sources(
+		"src/fakes.c"
+)
+
+if(DEFINED CONFIG_BOARD_ROACH)
+	project(roach)
+endif()
diff --git a/zephyr/program/roach/Kconfig b/zephyr/program/roach/Kconfig
new file mode 100644
index 0000000000..6d0ef53415
--- /dev/null
+++ b/zephyr/program/roach/Kconfig
@@ -0,0 +1,11 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config BOARD_ROACH
+	bool "Google Roach Board"
+	help
+	  Build Google Roach reference board. Roach is a keyboard EC
+	  using ITE it82202-ax.
+
+source "Kconfig.zephyr"
diff --git a/zephyr/program/roach/adc.dtsi b/zephyr/program/roach/adc.dtsi
new file mode 100644
index 0000000000..759817f50b
--- /dev/null
+++ b/zephyr/program/roach/adc.dtsi
@@ -0,0 +1,22 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		adc_ec_id: ec_id {
+			enum-name = "ADC_ID_1";
+			io-channels = <&adc0 1>;
+		};
+
+	};
+};
+
+&adc0 {
+	status = "okay";
+	pinctrl-0 = <&adc0_ch1_gpi1_default>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/roach/dev_key.pem b/zephyr/program/roach/dev_key.pem
new file mode 100644
index 0000000000..81a04439f8
--- /dev/null
+++ b/zephyr/program/roach/dev_key.pem
@@ -0,0 +1,40 @@
+-----BEGIN PRIVATE KEY-----
+MIIG/QIBADANBgkqhkiG9w0BAQEFAASCBucwggbjAgEAAoIBgQDXuX1KoABlUeHu
+abYwzT3Xp9KJwi3DSWAUhkIb/4KjeVA0a1WmJKlY7lqW9qjzCRTj4kdSMK5DW0jj
+6eq9rwUc17cYH7Si2fFtC4priOX5HHOcErc1n6ezJMJ8qcZzlXrIX/wxLBy9gsb7
+wJEo7vUmN4F95blEDYpMSQ4Z8uAaQVAHNfwpStc29meVDzoD6shDH4uritvEQIbe
+uFhMozAZrExTgloba2ZIX42Ul354bb1sNFU5mQg8EA698V6eDfBQd2wGdOT+0qka
+KtlbkL8u7FlwlxXhwzSOO6xORjjmiHShDGxfjR8yPaWFj7rbY1MZD0Hb+Cf82ziP
+lODHmQOPqH76SHkndKDTfJxv9f46Fm1oRPLkS5wYY/8acN+WlVc3Xq7/JwPrwkTg
+CvB5uwFwF0Ql2fJn+H/jafawQowgyi3zRNsjEpbVgdFwO9eDOdSXbIV56O2GS1o9
+rlhhlgneJH4E59qz3s5SjnOKlFzzkF31TEGJEkmEfWIXnSW5+gsCAQMCggGBAI/Q
+/jHAAEOL6/RGeXXeKTpv4bEsHoIw6rhZgWf/rGz7is2c48QYcOX0PGSkcKIGDe1B
+hOF1yYI820Kb8dPKA2iPz2VqeGyRS54HsZ0F7qYS971hz3kVGndt1v3GhE0OUdrq
+qCDIEykB2f0rC3CfThl6VlPue4KzsYgwtBFMlWbWNVoj/XDcj3n5mmNffAKchYIV
+B8ex59grBJR65YhsyrvIMuJW5rzyRDA/s7hk/vrz0514ONEQsCgKtH6g6b6z9FE1
+VMAT7FsOc4O/W+TyokcKL+FxB2i0AEeF3M2G+2/gRmm0KAGD3OvdIDyFFNfUawaU
+OCSHyaso5mZFk0ZNdDFOc6VzY5Msfn1Nt+uEdkp9S0cNbEAc8uPdH+fww2Vk4q/8
+jQhX5/6KpKZgJOKnNTh6VT7zBc1X+Oh230hRSzvyFQA0DHjTq+OO2d3RJ6gLFB7u
+6Q5LFfr0m7u8pdBWXeOaV/sJTmqpsWQ3gSO/kMuYBRl2ebhSe+sfnfvhttANqwKB
+wQD3tXObHAlSOveSTdjFklZ9Y8aZ+AjiD7dgO4UQM8Hm+2ihKyQspM3i6QFQ64a0
+hphFP07dS54bLR0NQWXO2VrlujZnUmAnobEfJK0iMPnKUqgkauDSv9MObyrWXRuP
+ZGpb/3Qt+q+gL+h6jrkF6+9m5ErlwxHfOOWERoq5iUBx+jZRh6NpX1RWtzJOOled
+MvjUkpdgdgDxX++hVTeucm1egtftcnuwEE0/dDaMc5KCn16H6hTzgrWLSXz1tv7R
+OEsCgcEA3vH5Szr5JAIEQj32vpJ1RvlLBHWB4qV8wrdcCcf917yiYVMMMKKF7Yjz
+2dyU4x4aSfGex+DbYPDB6OseD0t6X/ibGskDoxAx+GNbbH5TAAfUWUXvsWBctCkk
+aCqe7xmY02RnRKh4TcJla+wAH9RCNHt5YapX1LulAnEdCj9a1OTYIW8lBHXAqXRY
+VUfEafY9lHOQhAJLnHyBAr4n+qIPqjoiHudpY8/2/Mb7SIFxP4z3xzB2ARPaGIR4
+KBOUsK1BAoHBAKUjomdoBjbR+mGJOy5hjv5ChGalW0Ffz5V9A2AigUSnmxYcwsht
+3pdGAOCdBHhZutjU3z4yaWdzaLOA7onmPJkmzu+MQBpry2oYc2wgpobhxW2cleHV
+N170xzmTZ7TtnD1U+B6nH8Af8FG0e1lH9O9C3JkstpTQmQLZsdEGKvamzuEFF5uU
+4uR6IYl8OmjMpeMMZOr5VfY/9RY4z8mhnj8B5Uj2/SAK3ipNebL3twG/lFqcDfes
+eQeGU055/zYlhwKBwQCUoVDc0fttVq2BfqR/DE4vUNyto6vsblMsej1b2qk6fcGW
+N111wa6eW0076GNCFBGGoRSFQJJAoIFF8hQKMlGVUGdnMK0XYCFQQjzy/uIABTg7
+g/Ug6uh4G22axxSfZmXiQu+DGvregZjynVVqjYF4UlDrxuU4fRisS2ixf5HjQzrA
+9MNYToBw+DrjhS2b+X5i97WtVt0S/atXKW/8bApxfBa/RPDtNU9TL1IwVkt/s0/a
+IE6rYpFlraVwDQ3LHisCgcAL1TtQxfnpr2m9o+hrhxsghGsyfguc2HVj6VTXmgq9
+zyVGbKlXZqHCzaLFCRxUDuEAvwSbr3ecCuoejhn2g+j/RW48wQsEVkkUGdP56C9T
+I9A1/RTlIgUd4ENc1G7a7bYIfk53oeiA2Cv6rAo0VQUVnu53d2inoARXveV2nz4H
+YCnthGbUS2Jb4/1rwPUBkd/QbBPkPswusY3oIItbR7weJcs9fqFJ87pVPHzN1o9S
+6i4kvMJeLQ85qIdb2oLzexc=
+-----END PRIVATE KEY-----
diff --git a/zephyr/program/roach/gpio.dtsi b/zephyr/program/roach/gpio.dtsi
new file mode 100644
index 0000000000..2620a53207
--- /dev/null
+++ b/zephyr/program/roach/gpio.dtsi
@@ -0,0 +1,203 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/gpio_defines.h>
+
+/ {
+	aliases {
+		gpio-wp = &ec_flash_wp_odl;
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		en_kb_bl: en_kb_bl {
+			gpios = <&gpioa 1 GPIO_OUTPUT>;
+			enum-name = "GPIO_EN_KEYBOARD_BACKLIGHT";
+		};
+
+		ec_flash_wp_odl: ec_flash_wp_odl {
+			gpios = <&gpioi 4 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+
+		base_accel_int_l: base_accel_int_l {
+			gpios = <&gpioh 1 GPIO_INPUT>;
+		};
+
+		en_ec_id_odl: en_ec_id_odl {
+			gpios = <&gpioh 4 GPIO_ODR_HIGH>;
+		};
+
+		tchpad_int_odl: tchpad_int_odl {
+			gpios = <&gpiob 2 GPIO_OPEN_DRAIN>;
+		};
+
+		en_pp3300_tchpad_odl: en_pp3300_tchpad_odl {
+			gpios = <&gpiob 5 GPIO_OUTPUT>;
+		};
+
+		/* TODO: unimplemented GPIOs */
+		/* system.c related */
+		entering_rw: entering_rw {
+			enum-name = "GPIO_ENTERING_RW";
+		};
+	};
+
+	unused-pins {
+		compatible = "unused-gpios";
+
+		unused-gpios =
+			/* gpioa2 */
+			<&gpioa 2 GPIO_INPUT_PULL_DOWN>,
+			/* gpioa3 */
+			<&gpioa 3 GPIO_INPUT_PULL_DOWN>,
+			/* gpioa6 */
+			<&gpioa 6 GPIO_INPUT_PULL_DOWN>,
+			/* gpioa7 */
+			<&gpioa 7 GPIO_INPUT_PULL_DOWN>,
+
+			/* gpiob6 */
+			<&gpiob 6 GPIO_INPUT_PULL_DOWN>,
+			/* gpiob7 */
+			<&gpiob 7 GPIO_INPUT_PULL_DOWN>,
+
+			/* gpioc0 */
+			<&gpioc 0 GPIO_INPUT_PULL_DOWN>,
+			/* gpioc1 */
+			<&gpioc 1 GPIO_INPUT_PULL_DOWN>,
+			/* gpioc2 */
+			<&gpioc 2 GPIO_INPUT_PULL_DOWN>,
+			/* gpioc3 */
+			<&gpioc 3 GPIO_INPUT_PULL_DOWN>,
+			/* gpioc4 */
+			<&gpioc 4 GPIO_INPUT_PULL_DOWN>,
+			/* gpioc5 */
+			<&gpioc 5 GPIO_INPUT_PULL_DOWN>,
+			/* gpioc6 */
+			<&gpioc 6 GPIO_INPUT_PULL_DOWN>,
+			/* gpioc7 */
+			<&gpioc 7 GPIO_INPUT_PULL_DOWN>,
+
+			/* gpiod0 */
+			<&gpiod 0 GPIO_INPUT_PULL_DOWN>,
+			/* gpiod1 */
+			<&gpiod 1 GPIO_INPUT_PULL_DOWN>,
+			/* gpiod2 */
+			<&gpiod 2 GPIO_INPUT_PULL_DOWN>,
+			/* gpiod3 */
+			<&gpiod 3 GPIO_INPUT_PULL_DOWN>,
+			/* gpiod4 */
+			<&gpiod 4 GPIO_INPUT_PULL_DOWN>,
+			/* gpiod5 */
+			<&gpiod 5 GPIO_INPUT_PULL_DOWN>,
+			/* gpiod6 */
+			<&gpiod 6 GPIO_INPUT_PULL_DOWN>,
+			/* gpiod7 */
+			<&gpiod 7 GPIO_INPUT_PULL_DOWN>,
+
+			/* gpioe0 */
+			<&gpioe 0 GPIO_INPUT_PULL_DOWN>,
+			/* gpioe1 */
+			<&gpioe 1 GPIO_INPUT_PULL_DOWN>,
+			/* gpioe2 */
+			<&gpioe 2 GPIO_INPUT_PULL_DOWN>,
+			/* gpioe3 */
+			<&gpioe 3 GPIO_INPUT_PULL_DOWN>,
+			/* gpioe4 */
+			<&gpioe 4 GPIO_INPUT_PULL_DOWN>,
+			/* gpioe5 */
+			<&gpioe 5 GPIO_INPUT_PULL_DOWN>,
+			/* gpioe6 */
+			<&gpioe 6 GPIO_INPUT_PULL_DOWN>,
+			/* gpioe7 */
+			<&gpioe 7 GPIO_INPUT_PULL_DOWN>,
+
+			/* gpiof2 */
+			<&gpiof 2 GPIO_INPUT_PULL_DOWN>,
+			/* gpiof3 */
+			<&gpiof 3 GPIO_INPUT_PULL_DOWN>,
+			/* gpiof4 */
+			<&gpiof 4 GPIO_INPUT_PULL_DOWN>,
+			/* gpiof5 */
+			<&gpiof 5 GPIO_INPUT_PULL_DOWN>,
+
+			/* gpiog0 */
+			<&gpiog 0 GPIO_INPUT_PULL_DOWN>,
+			/* gpiog1 */
+			<&gpiog 1 GPIO_INPUT_PULL_DOWN>,
+			/* gpiog2 */
+			<&gpiog 2 GPIO_INPUT>,
+			/* gpiog3 */
+			<&gpiog 3 GPIO_INPUT>,
+
+			/* gpioh0 */
+			<&gpioh 0 GPIO_INPUT_PULL_DOWN>,
+			/* gpioh3 */
+			<&gpioh 3 GPIO_INPUT_PULL_DOWN>,
+			/* TODO: gpioh5: EC_USB2_N */
+			<&gpioh 5 GPIO_INPUT_PULL_DOWN>,
+			/* TODO: gpioh6: EC_USB2_P */
+			<&gpioh 6 GPIO_INPUT_PULL_DOWN>,
+
+			/* gpioi0 */
+			<&gpioi 0 GPIO_INPUT_PULL_DOWN>,
+			/* gpioi2 */
+			<&gpioi 2 GPIO_INPUT_PULL_DOWN>,
+			/* gpioi3 */
+			<&gpioi 3 GPIO_INPUT_PULL_DOWN>,
+			/* gpioi5 */
+			<&gpioi 5 GPIO_INPUT_PULL_DOWN>,
+			/* gpioi6 */
+			<&gpioi 6 GPIO_INPUT_PULL_DOWN>,
+			/* gpioi7 */
+			<&gpioi 7 GPIO_INPUT_PULL_DOWN>,
+
+			/* gpioj0 */
+			<&gpioj 0 GPIO_INPUT_PULL_DOWN>,
+			/* gpioj1 */
+			<&gpioj 1 GPIO_INPUT_PULL_DOWN>,
+			/* gpioj2 */
+			<&gpioj 2 GPIO_INPUT_PULL_DOWN>,
+			/* gpioj3 */
+			<&gpioj 3 GPIO_INPUT_PULL_DOWN>,
+			/* gpioj4 */
+			<&gpioj 4 GPIO_INPUT_PULL_DOWN>,
+			/* gpioj5 */
+			<&gpioj 5 GPIO_INPUT_PULL_DOWN>,
+			/* gpioj6 */
+			<&gpioj 6 GPIO_OUTPUT_LOW>,
+			/* gpioj7 */
+			<&gpioj 7 GPIO_OUTPUT_LOW>,
+
+			/* gpiom0 */
+			<&gpiom 0 GPIO_INPUT_PULL_DOWN>,
+			/* gpiom1 */
+			<&gpiom 1 GPIO_INPUT_PULL_DOWN>,
+			/* gpiom2 */
+			<&gpiom 2 GPIO_INPUT_PULL_DOWN>,
+			/* gpiom3 */
+			<&gpiom 3 GPIO_INPUT_PULL_DOWN>,
+			/* gpiom4 */
+			<&gpiom 4 GPIO_INPUT_PULL_DOWN>,
+			/* gpiom5 */
+			<&gpiom 5 GPIO_INPUT_PULL_DOWN>,
+			/* gpiom6 */
+			<&gpiom 6 GPIO_INPUT_PULL_DOWN>;
+	};
+};
+
+&uart2 {
+	status = "okay";
+	current-speed = <460800>;
+	clock-frequency = <1804800>;
+};
+
+&ite_uart2_wrapper {
+	status = "okay";
+	pinctrl-0 = <&uart2_rx_gpf0_default
+		     &uart2_tx_gpf1_default>;
+	pinctrl-names = "default";
+};
+
diff --git a/zephyr/program/roach/i2c.dtsi b/zephyr/program/roach/i2c.dtsi
new file mode 100644
index 0000000000..879dbf2a3f
--- /dev/null
+++ b/zephyr/program/roach/i2c.dtsi
@@ -0,0 +1,44 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		i2c_tchpad: tchpad {
+			i2c-port = <&i2c0>;
+			enum-names = "I2C_PORT_TCHPAD";
+		};
+		i2c_sensor: sensor {
+			i2c-port = <&i2c2>;
+			enum-names = "I2C_PORT_SENSOR";
+		};
+	};
+};
+
+&i2c0 {
+	status = "okay";
+	label = "I2C_TCHPAD";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c0_clk_gpb3_default
+		     &i2c0_data_gpb4_default>;
+	pinctrl-names = "default";
+
+	touchpad@15 {
+		compatible = "elan,ekth3000";
+		status = "okay";
+		reg = <0x15>;
+		irq = <&int_tchpad>;
+	};
+};
+
+&i2c2 {
+	status = "okay";
+	label = "I2C_SENSOR";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c2_clk_gpf6_default
+		     &i2c2_data_gpf7_default>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/roach/interrupts.dtsi b/zephyr/program/roach/interrupts.dtsi
new file mode 100644
index 0000000000..36b3f130c4
--- /dev/null
+++ b/zephyr/program/roach/interrupts.dtsi
@@ -0,0 +1,16 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_tchpad: tchpad {
+			irq-pin = <&tchpad_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "touchpad_interrupt";
+		};
+	};
+};
diff --git a/zephyr/program/roach/keyboard.dtsi b/zephyr/program/roach/keyboard.dtsi
new file mode 100644
index 0000000000..4dcf4009c5
--- /dev/null
+++ b/zephyr/program/roach/keyboard.dtsi
@@ -0,0 +1,123 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	cros-keyscan {
+		compatible = "cros-ec,keyscan";
+
+		scan-period = <10000>;
+		output-settle = <80>; /* us */
+
+		actual-key-mask = <
+			0x1c	/* C0 */
+			0xff	/* C1 */
+			0xff	/* C2 */
+			0xff	/* C3 */
+			0xff	/* C4 */
+			0xf5	/* C5 */
+			0xff	/* C6 */
+			0xa4	/* C7 */
+			0xff	/* C8 */
+			0xfe	/* C9 */
+			0x55	/* C10 */
+			0xfa	/* C11 */
+			0xca	/* C12 */
+			>;
+	};
+};
+
+&cros_kb_raw {
+	status = "okay";
+	pinctrl-0 = <&ksi0_default
+		     &ksi1_default
+		     &ksi2_default
+		     &ksi3_default
+		     &ksi4_default
+		     &ksi5_default
+		     &ksi6_default
+		     &ksi7_default
+		     &kso0_default
+		     &kso1_default
+		     &kso2_default
+		     &kso3_default
+		     &kso4_default
+		     &kso5_default
+		     &kso6_default
+		     &kso7_default
+		     &kso8_default
+		     &kso9_default
+		     &kso10_default
+		     &kso11_default
+		     &kso12_default>;
+	pinctrl-names = "default";
+};
+
+&kso0_default {
+	/delete-property/ bias-pull-up;
+};
+
+&kso1_default {
+	/delete-property/ bias-pull-up;
+};
+
+&kso2_default {
+	/delete-property/ bias-pull-up;
+};
+
+&kso3_default {
+	/delete-property/ bias-pull-up;
+};
+
+&kso4_default {
+	/delete-property/ bias-pull-up;
+};
+
+&kso5_default {
+	/delete-property/ bias-pull-up;
+};
+
+&kso6_default {
+	/delete-property/ bias-pull-up;
+};
+
+&kso7_default {
+	/delete-property/ bias-pull-up;
+};
+
+&kso8_default {
+	/delete-property/ bias-pull-up;
+};
+
+&kso9_default {
+	/delete-property/ bias-pull-up;
+};
+
+&kso10_default {
+	/delete-property/ bias-pull-up;
+};
+
+&kso11_default {
+	/delete-property/ bias-pull-up;
+};
+
+&kso12_default {
+	/delete-property/ bias-pull-up;
+};
+
+&kso13_default {
+	/delete-property/ bias-pull-up;
+};
+
+&kso14_default {
+	/delete-property/ bias-pull-up;
+};
+
+&kso16_gpc3_default {
+	/delete-property/ bias-pull-up;
+};
+
+&kso17_gpc5_default {
+	/delete-property/ bias-pull-up;
+};
diff --git a/zephyr/program/roach/program.conf b/zephyr/program/roach/program.conf
new file mode 100644
index 0000000000..97c73ef5b4
--- /dev/null
+++ b/zephyr/program/roach/program.conf
@@ -0,0 +1,40 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_CROS_EC=y
+CONFIG_PLATFORM_EC=y
+CONFIG_SHIMMED_TASKS=y
+
+# SoC configuration
+CONFIG_AP=n
+
+# Optional features
+CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGEN=n
+CONFIG_PLATFORM_EC_CONSOLE_CMD_I2C_PORTMAP=n
+CONFIG_PLATFORM_EC_LID_SWITCH=n
+
+# Signing
+# TODO: this adds ~4.7kB unused code to the RW image.
+# Find a way to enable this for RO only.
+CONFIG_PLATFORM_EC_RWSIG=y
+CONFIG_PLATFORM_EC_RSA_KEY_SIZE=3072
+CONFIG_PLATFORM_EC_RSA_EXPONENT_3=y
+CONFIG_PLATFORM_EC_RWSIG_KEY_PATH="zephyr/program/roach/dev_key.pem"
+
+# UART
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Touchpad
+CONFIG_PLATFORM_EC_TOUCHPAD_ELAN=y
+
+# MKBP
+CONFIG_PLATFORM_EC_CBI=n
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
+CONFIG_PLATFORM_EC_SWITCH=n
+CONFIG_PLATFORM_EC_VBOOT_EFS2=n
+CONFIG_PLATFORM_EC_VBOOT_HASH=n
+
+# USB-C
+CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=n
+CONFIG_PLATFORM_EC_USB_PD_USB4=n
diff --git a/zephyr/program/roach/pwm.dtsi b/zephyr/program/roach/pwm.dtsi
new file mode 100644
index 0000000000..813ef4a8d4
--- /dev/null
+++ b/zephyr/program/roach/pwm.dtsi
@@ -0,0 +1,24 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	kb_bl_pwm {
+		compatible = "cros-ec,kblight-pwm";
+		/*
+		 * Use 324 Hz so that 32Khz clock source is used,
+		 * which is not gated in power saving mode.
+		 */
+		pwms = <&pwm0 0 PWM_HZ(324) PWM_POLARITY_NORMAL>;
+		status = "disabled";
+	};
+};
+
+/* pwm for test */
+&pwm0 {
+	status = "okay";
+	prescaler-cx = <PWM_PRESCALER_C4>;
+	pinctrl-0 = <&pwm0_gpa0_default>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/roach/roach/project.conf b/zephyr/program/roach/roach/project.conf
new file mode 100644
index 0000000000..a8bba34c3e
--- /dev/null
+++ b/zephyr/program/roach/roach/project.conf
@@ -0,0 +1,6 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Variant config
+CONFIG_BOARD_ROACH=y
diff --git a/zephyr/program/roach/roach/project.overlay b/zephyr/program/roach/roach/project.overlay
new file mode 100644
index 0000000000..320c0bec99
--- /dev/null
+++ b/zephyr/program/roach/roach/project.overlay
@@ -0,0 +1,14 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Roach program common DTS includes */
+
+#include "../adc.dtsi"
+#include "../gpio.dtsi"
+#include "../i2c.dtsi"
+#include "../interrupts.dtsi"
+#include "../keyboard.dtsi"
+#include "../pwm.dtsi"
+#include "../rwsig.dtsi"
diff --git a/zephyr/program/roach/rwsig.dtsi b/zephyr/program/roach/rwsig.dtsi
new file mode 100644
index 0000000000..595df69b66
--- /dev/null
+++ b/zephyr/program/roach/rwsig.dtsi
@@ -0,0 +1,39 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+&binman {
+	wp-ro {
+		ec-ro {
+			key-ro {
+				type = "blob";
+				offset = <(0x40000 - 4096 - 1024)>;
+				size = <1024>;
+				filename = "../build-rw/key.vbpubk2";
+			};
+		};
+	};
+
+	ec-rw {
+		rw-fw {
+			/* rwsig module doesn't allow extra contents after
+			 * zephyr-rw.
+			 * Remove rw-fwid since it's only used in FAFT.
+			 */
+			/delete-node/ rw-fwid;
+
+			sig-rw {
+				type = "blob";
+				offset = <(0x40000 - 1024)>;
+				size = <1024>;
+				filename = "../build-rw/ec.sig";
+			};
+
+			/* rwsig assumes the padding bytes between zephyr-rw and
+			 * sig-rw are filled with 0xff.
+			 */
+			pad-byte = <0xff>;
+		};
+	};
+};
diff --git a/zephyr/program/roach/src/fakes.c b/zephyr/program/roach/src/fakes.c
new file mode 100644
index 0000000000..20b1cc9309
--- /dev/null
+++ b/zephyr/program/roach/src/fakes.c
@@ -0,0 +1,26 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "usb_hid_touchpad.h"
+
+void keyboard_clear_buffer(void)
+{
+}
+
+void clear_typematic_key(void)
+{
+}
+
+void keyboard_state_changed(int row, int col, int is_pressed)
+{
+}
+
+void board_touchpad_reset(void)
+{
+}
+
+void set_touchpad_report(struct usb_hid_touchpad_report *report)
+{
+}
diff --git a/zephyr/program/skyrim/BUILD.py b/zephyr/program/skyrim/BUILD.py
new file mode 100644
index 0000000000..2719375808
--- /dev/null
+++ b/zephyr/program/skyrim/BUILD.py
@@ -0,0 +1,48 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Define zmake projects for skyrim."""
+
+
+def register_skyrim_project(
+    project_name,
+):
+    """Register a variant of skyrim."""
+    register_npcx_project(
+        project_name=project_name,
+        zephyr_board="npcx9m3f",
+        dts_overlays=[
+            here / project_name / "project.overlay",
+        ],
+        kconfig_files=[
+            # Common to all projects.
+            here / "program.conf",
+            # Project-specific KConfig customization.
+            here / project_name / "project.conf",
+        ],
+        inherited_from=["skyrim"],
+    )
+
+
+register_skyrim_project(
+    project_name="skyrim",
+)
+
+
+register_skyrim_project(
+    project_name="winterhold",
+)
+
+
+register_skyrim_project(
+    project_name="frostflow",
+)
+
+register_skyrim_project(
+    project_name="crystaldrift",
+)
+
+register_skyrim_project(
+    project_name="markarth",
+)
diff --git a/zephyr/program/skyrim/CMakeLists.txt b/zephyr/program/skyrim/CMakeLists.txt
new file mode 100644
index 0000000000..672a22a5bf
--- /dev/null
+++ b/zephyr/program/skyrim/CMakeLists.txt
@@ -0,0 +1,45 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+
+zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}/include")
+
+zephyr_library_sources("src/common.c")
+zephyr_library_sources("src/power_signals.c")
+
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC
+	"src/usb_pd_policy.c"
+	"src/usbc_config.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LED_COMMON
+	"src/led.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_AMD_STT
+	"src/stt.c")
+
+if(DEFINED CONFIG_BOARD_SKYRIM)
+	project(skyrim)
+	add_subdirectory(skyrim)
+endif()
+
+if(DEFINED CONFIG_BOARD_WINTERHOLD)
+	project(winterhold)
+	add_subdirectory(winterhold)
+endif()
+
+if(DEFINED CONFIG_BOARD_FROSTFLOW)
+	project(frostflow)
+	add_subdirectory(frostflow)
+endif()
+
+if(DEFINED CONFIG_BOARD_CRYSTALDRIFT)
+	project(crystaldrift)
+	add_subdirectory(crystaldrift)
+endif()
+
+if(DEFINED CONFIG_BOARD_MARKARTH)
+	project(markarth)
+	add_subdirectory(markarth)
+endif()
diff --git a/zephyr/program/skyrim/Kconfig b/zephyr/program/skyrim/Kconfig
new file mode 100644
index 0000000000..86fac1ae55
--- /dev/null
+++ b/zephyr/program/skyrim/Kconfig
@@ -0,0 +1,46 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config BOARD_SKYRIM
+	bool "Google Skyrim Board"
+	help
+	  Build Google Skyrim reference board.  This board uses an AMD SoC
+	  and NPCX9 EC
+
+config BOARD_WINTERHOLD
+	bool "Google Winterhold Board"
+	help
+	  Build Google Winterhold reference board.  This board uses an AMD SoC
+	  and NPCX9 EC
+
+config BOARD_FROSTFLOW
+	bool "Google Frostflow Board"
+	help
+	  Build Google Frostflow reference board.  This board uses an AMD SoC
+	  and NPCX9 EC
+
+config BOARD_CRYSTALDRIFT
+	bool "Google Crystaldrift Board"
+	help
+	  Build Google Crystaldrift reference board.  This board uses an AMD SoC
+	  and NPCX9 EC
+
+config BOARD_MARKARTH
+	bool "Google Markarth Board"
+	help
+	  Build Google Markarth reference board.  This board uses an AMD SoC
+	  and NPCX9 EC
+
+config BOARD_USB_HUB_RESET
+	bool "Support USB hub reset or not"
+	default y
+	help
+	  Enable this if your board has a USB hub reset GPIO connect to EC to
+	  reset the USB hub.
+
+module = SKYRIM
+module-str = Skyrim board-specific code
+source "subsys/logging/Kconfig.template.log_config"
+
+source "Kconfig.zephyr"
diff --git a/zephyr/program/skyrim/adc.dtsi b/zephyr/program/skyrim/adc.dtsi
new file mode 100644
index 0000000000..952e5db1d0
--- /dev/null
+++ b/zephyr/program/skyrim/adc.dtsi
@@ -0,0 +1,82 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <cros/thermistor/thermistor.dtsi>
+
+/ {
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		adc_temp_charger: temp-charger {
+			enum-name = "ADC_TEMP_SENSOR_CHARGER";
+			io-channels = <&adc0 1>;
+		};
+		adc_temp_memory: temp-memory {
+			enum-name = "ADC_TEMP_SENSOR_MEMORY";
+			io-channels = <&adc0 2>;
+		};
+		adc_core_imon1: core-imon1 {
+			enum-name = "ADC_CORE_IMON1";
+			io-channels = <&adc0 3>;
+		};
+		adc_core_imon2: core-imon2 {
+			enum-name = "ADC_SOC_IMON2";
+			io-channels = <&adc0 4>;
+		};
+	};
+
+	temp_charger_thermistor: charger-thermistor {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_30K9_47K_4050B>;
+		adc = <&adc_temp_charger>;
+	};
+
+	temp_memory_thermistor: memory-thermistor {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_30K9_47K_4050B>;
+		adc = <&adc_temp_memory>;
+	};
+
+	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
+		temp_sensor_charger: charger-thermistor {
+			temp_host_high = <100>;
+			temp_host_halt = <105>;
+			temp_host_release_high = <80>;
+			sensor = <&temp_charger_thermistor>;
+		};
+
+		temp_sensor_memory: memory-thermistor {
+			temp_host_high = <100>;
+			temp_host_halt = <105>;
+			temp_host_release_high = <80>;
+			power-good-pin = <&gpio_pg_pwr_s5>;
+			sensor = <&temp_memory_thermistor>;
+		};
+
+		temp_sensor_cpu: cpu {
+			temp_host_high = <100>;
+			temp_host_halt = <105>;
+			temp_host_release_high = <80>;
+			temp_fan_off = <60>;
+			temp_fan_max = <90>;
+			power-good-pin = <&gpio_s0_pgood>;
+			sensor = <&temp_cpu>;
+		};
+	};
+};
+
+&adc0 {
+	status = "okay";
+	pinctrl-0 = <&adc0_chan1_gp44
+		     &adc0_chan2_gp43
+		     &adc0_chan3_gp42
+		     &adc0_chan4_gp41>;
+	pinctrl-names = "default";
+};
+
+&thermistor_3V3_30K9_47K_4050B {
+	status = "okay";
+};
diff --git a/zephyr/program/skyrim/crystaldrift/CMakeLists.txt b/zephyr/program/skyrim/crystaldrift/CMakeLists.txt
new file mode 100644
index 0000000000..9867197ba0
--- /dev/null
+++ b/zephyr/program/skyrim/crystaldrift/CMakeLists.txt
@@ -0,0 +1,14 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cros_ec_library_include_directories_ifdef(CONFIG_BOARD_CRYSTALDRIFT include)
+zephyr_library_sources(
+		"src/usb_mux_config.c"
+		"src/ppc_config.c"
+		"src/form_factor.c"
+		"src/keyboard.c"
+		"src/board.c"
+	        "src/thermal.c"
+)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FAN "src/fan.c")
diff --git a/zephyr/program/skyrim/crystaldrift/led_pins.dtsi b/zephyr/program/skyrim/crystaldrift/led_pins.dtsi
new file mode 100644
index 0000000000..ec0d93de8d
--- /dev/null
+++ b/zephyr/program/skyrim/crystaldrift/led_pins.dtsi
@@ -0,0 +1,35 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+
+
+
+gpio-led-pins {
+		compatible = "cros-ec,gpio-led-pins";
+
+		battery_led: battery-led {
+			led-id = "EC_LED_ID_BATTERY_LED";
+			led-pins = <&gpio_ec_chg_led_r &gpio_ec_chg_led_b>;
+
+			color_off: color-off {
+				led-color = "LED_OFF";
+				led-values = <0 0>;
+			};
+
+			color_red: color-red {
+				led-color = "LED_RED";
+				br-color = "EC_LED_COLOR_RED";
+				led-values = <1 0>;
+			};
+
+			color_blue: color-blue {
+				led-color = "LED_BLUE";
+				br-color = "EC_LED_COLOR_BLUE";
+				led-values = <0 1>;
+			};
+		};
+	};
+};
diff --git a/zephyr/program/skyrim/crystaldrift/led_policy.dtsi b/zephyr/program/skyrim/crystaldrift/led_policy.dtsi
new file mode 100644
index 0000000000..24df611f5a
--- /dev/null
+++ b/zephyr/program/skyrim/crystaldrift/led_policy.dtsi
@@ -0,0 +1,103 @@
+#include <dt-bindings/battery.h>
+
+/ {
+	led-colors {
+		compatible = "cros-ec,led-policy";
+
+		power-state-charge {
+			charge-state = "LED_PWRS_CHARGE";
+
+			color-0 {
+				led-color = <&color_red>;
+			};
+		};
+
+		power-state-discharge-s0 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S0";
+			/* Battery percent range (> Low, <= Full) */
+			batt-lvl = <(BATTERY_LEVEL_LOW + 1) BATTERY_LEVEL_FULL>;
+
+			color-0 {
+				led-color = <&color_blue>;
+			};
+		};
+
+		power-state-discharge-s0-batt-low {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S0";
+			/* Battery percent range (>= Empty, <= Low) */
+			batt-lvl = <BATTERY_LEVEL_EMPTY BATTERY_LEVEL_LOW>;
+
+			/* Blue 2 sec, off 1 sec */
+			color-0 {
+				led-color = <&color_blue>;
+				period-ms = <2000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <1000>;
+			};
+		};
+
+		power-state-discharge-s3 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S3";
+
+			/* Red 1 sec, off 3 sec */
+			color-0 {
+				led-color = <&color_red>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <3000>;
+			};
+		};
+
+		power-state-discharge-s5 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S5";
+
+			color-0 {
+				led-color = <&color_off>;
+			};
+		};
+
+		power-state-error {
+			charge-state = "LED_PWRS_ERROR";
+
+			/* Red 1 sec, off 1 sec */
+			color-0 {
+				led-color = <&color_red>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <1000>;
+			};
+		};
+
+		power-state-near-full {
+			charge-state = "LED_PWRS_CHARGE_NEAR_FULL";
+
+			color-0 {
+				led-color = <&color_blue>;
+			};
+		};
+
+		power-state-forced-idle {
+			charge-state = "LED_PWRS_FORCED_IDLE";
+
+			/* Red 2 sec, Blue 2 sec */
+			color-0 {
+				led-color = <&color_red>;
+				period-ms = <2000>;
+			};
+			color-1 {
+				led-color = <&color_blue>;
+				period-ms = <2000>;
+			};
+		};
+	};
+};
diff --git a/zephyr/program/skyrim/crystaldrift/motionsense.dtsi b/zephyr/program/skyrim/crystaldrift/motionsense.dtsi
new file mode 100644
index 0000000000..119c4aaf8e
--- /dev/null
+++ b/zephyr/program/skyrim/crystaldrift/motionsense.dtsi
@@ -0,0 +1,133 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/motionsense/utils.h>
+
+
+/ {
+	aliases {
+		/*
+		 * motion sense's <>_INT_EVENT is handled
+		 * by alias. Using the alias, each driver creates
+		 * its own <>_INT_EVENT.
+		 */
+		bmi3xx-int = &base_accel;
+		bma4xx-int = &lid_accel;
+	};
+
+	/*
+	 * Declare mutexes used by sensor drivers.
+	 * A mutex node is used to create an instance of mutex_t.
+	 * A mutex node is referenced by a sensor node if the
+	 * corresponding sensor driver needs to use the
+	 * instance of the mutex.
+	 */
+	motionsense-mutex {
+		compatible = "cros-ec,motionsense-mutex";
+		lid_mutex: lid-mutex {
+		};
+
+		mutex_bmi3xx: bmi3xx-mutex {
+		};
+	};
+
+	/*
+	 * Driver specific data. A driver-specific data can be shared with
+	 * different motion sensors while they are using the same driver.
+	 *
+	 * If a node's compatible starts with "cros-ec,accelgyro-", it is for
+	 * a common structure defined in accelgyro.h.
+	 * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for
+	 * "struct als_drv_data_t" in accelgyro.h
+	 */
+	motionsense-sensor-data {
+		bma4xx_data: bma4xx-drv-data {
+			compatible = "cros-ec,drvdata-bma4xx";
+			status = "okay";
+		};
+
+		bmi3xx_data: bmi3xx-drv-data {
+			compatible = "cros-ec,drvdata-bmi3xx";
+			status = "okay";
+		};
+	};
+
+	/*
+	 * List of motion sensors that creates motion_sensors array.
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
+	 * motion sensor IDs for lid angle calculation.
+	 */
+	motionsense-sensor {
+		lid_accel: lid-accel {
+			compatible = "cros-ec,bma4xx";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&lid_mutex>;
+			port = <&i2c_sensor>;
+			drv-data = <&bma4xx_data>;
+			rot-standard-ref = <&lid_rot_ref>;
+			default-range = <2>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(12500 | ROUND_UP_FLAG)>;
+					ec-rate = <100>;
+				};
+				ec-s3 {
+					odr = <(12500 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_accel: base-accel {
+			compatible = "cros-ec,bmi3xx-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&mutex_bmi3xx>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&bmi3xx_data>;
+
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(12500 | ROUND_UP_FLAG)>;
+					ec-rate = <100>;
+				};
+				ec-s3 {
+					odr = <(12500 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base-gyro {
+			compatible = "cros-ec,bmi3xx-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&mutex_bmi3xx>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&bmi3xx_data>;
+		};
+	};
+
+	motionsense-sensor-info {
+		compatible = "cros-ec,motionsense-sensor-info";
+
+		/*
+		 * list of GPIO interrupts that have to
+		 * be enabled at initial stage
+		 */
+		sensor-irqs = <&int_lid_accel &int_accel_gyro>;
+	};
+};
diff --git a/zephyr/program/skyrim/crystaldrift/project.conf b/zephyr/program/skyrim/crystaldrift/project.conf
new file mode 100644
index 0000000000..382d193018
--- /dev/null
+++ b/zephyr/program/skyrim/crystaldrift/project.conf
@@ -0,0 +1,32 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Crystaldrift reference-board-specific Kconfig settings.
+CONFIG_BOARD_CRYSTALDRIFT=y
+
+# CBI WP pin present
+CONFIG_PLATFORM_EC_EEPROM_CBI_WP=y
+
+# Crystaldrfit is capable of sinking 100W
+CONFIG_PLATFORM_EC_PD_MAX_POWER_MW=100000
+CONFIG_PLATFORM_EC_PD_MAX_CURRENT_MA=5000
+CONFIG_PLATFORM_EC_PD_MAX_VOLTAGE_MV=20000
+
+# Charger chip
+CONFIG_PLATFORM_EC_CHARGER_ISL9238=y
+
+# Enable alternative charger chip
+CONFIG_PLATFORM_EC_CHARGER_RUNTIME_CONFIG=y
+CONFIG_PLATFORM_EC_CHARGER_ISL9238C=y
+
+# Battery
+CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO=y
+# Get the vbus voltage from TCPC
+CONFIG_PLATFORM_EC_CHARGER_ISL9241=n
+CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_CHARGER=n
+CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_TCPC=y
+
+# Fan
+CONFIG_PLATFORM_EC_THROTTLE_AP_SINGLE_PIN=n
+CONFIG_PLATFORM_EC_CUSTOM_FAN_CONTROL=y
diff --git a/zephyr/program/skyrim/crystaldrift/project.overlay b/zephyr/program/skyrim/crystaldrift/project.overlay
new file mode 100644
index 0000000000..8c92e1965e
--- /dev/null
+++ b/zephyr/program/skyrim/crystaldrift/project.overlay
@@ -0,0 +1,240 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Skyrim program common DTS includes */
+#include "../adc.dtsi"
+#include "../fan.dtsi"
+#include "../gpio.dtsi"
+#include "../i2c.dtsi"
+#include "../interrupts.dtsi"
+#include "../keyboard.dtsi"
+#include "../usbc.dtsi"
+
+/* Crystaldrift project DTS includes*/
+#include "led_pins.dtsi"
+#include "led_policy.dtsi"
+#include "motionsense.dtsi"
+
+/* Crystaldrift overrides follow... */
+/ {
+	/* battery overrides */
+	batteries {
+		default_battery: bms-gf_cr50 {
+			compatible = "bms-gf,cr50", "battery-smart";
+		};
+		gfl_mfp-549358 {
+			compatible = "gfl,mfp-549358", "battery-smart";
+		};
+	};
+
+	named-gpios {
+		/* Crystaldrift-specific GPIO customizations */
+		gpio_ec_chg_led_r: ec_chg_led_r {
+			gpios = <&gpioc 4 GPIO_OUTPUT_LOW>;
+		};
+		gpio_ec_chg_led_b: ec_chg_led_b {
+			gpios = <&gpio8 0 GPIO_OUTPUT_LOW>;
+		};
+		gpio_ec_usbhub_en: ec_usbhub_en {
+			gpios = <&gpio4 5 GPIO_OUTPUT_HIGH>;
+		};
+	};
+
+	gpio-interrupts {
+		int_lid_accel: lid_accel {
+			irq-pin = <&gpio_lid_accel_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "bma4xx_interrupt";
+		};
+	};
+
+	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
+		soc-pct2075 {
+			temp_host_high = <100>;
+			temp_host_halt = <105>;
+			temp_host_release_high = <80>;
+			temp_host_release_halt = <80>;
+			temp_fan_off = <35>;
+			temp_fan_max = <70>;
+			power-good-pin = <&gpio_pg_pwr_s5>;
+			sensor = <&soc_pct2075>;
+		};
+		amb-pct2075 {
+			power-good-pin = <&gpio_pg_pwr_s5>;
+			sensor = <&amb_pct2075>;
+		};
+	};
+	fan_steps: fan-step {
+		compatible = "cros-ec,fan-steps";
+		level_0 {
+			temp_on = <(-1) (-1) 38 (-1) (-1)>;
+			temp_off = <(-1) (-1) 39 (-1) (-1)>;
+			rpm_target = <0>;
+		};
+		level_1 {
+			temp_on = <(-1) (-1) 45 (-1) (-1)>;
+			temp_off = <(-1) (-1) 47 (-1) (-1)>;
+			rpm_target = <3400>;
+		};
+		level_2 {
+			temp_on = <(-1) (-1) 52 (-1) (-1)>;
+			temp_off = <(-1) (-1) 56 (-1) (-1)>;
+			rpm_target = <3800>;
+		};
+		level_3 {
+			temp_on = <(-1) (-1) 61 (-1) (-1)>;
+			temp_off = <(-1) (-1) 68 (-1) (-1)>;
+			rpm_target = <4200>;
+		};
+		level_4 {
+			temp_on = <(-1) (-1) 70 (-1) (-1)>;
+			temp_off = <(-1) (-1) 73 (-1) (-1)>;
+			rpm_target = <4500>;
+		};
+		level_5 {
+			temp_on = <(-1) (-1) 76 (-1) (-1)>;
+			temp_off = <(-1) (-1) 74 (-1) (-1)>;
+			rpm_target = <4800>;
+		};
+	};
+
+	/*
+	 * Note this is expected to vary per-board, so we keep it in the overlay
+	 * file.
+	 */
+	crystaldrift-fw-config {
+		compatible = "cros-ec,cbi-fw-config";
+
+		form-factor {
+			enum-name = "FW_FORM_FACTOR";
+			start = <0>;
+			size = <1>;
+
+			ff-clamshell {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FF_CLAMSHELL";
+				value = <0>;
+			};
+			ff-convertible {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FF_CONVERTIBLE";
+				value = <1>;
+				default;
+			};
+		};
+		io-db {
+			enum-name = "FW_IO_DB";
+			start = <6>;
+			size = <2>;
+
+			io-db-ps8811-ps8818 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_IO_DB_PS8811_PS8818";
+				value = <0>;
+			};
+			io-db-none-anx7483 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_IO_DB_NONE_ANX7483";
+				value = <1>;
+				default;
+			};
+		};
+
+		/*
+		 * FW_CONFIG field to enable fan or not.
+		 */
+		fan {
+			enum-name = "FW_FAN";
+			start = <10>;
+			size = <1>;
+
+			no-fan {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FAN_NOT_PRESENT";
+				value = <0>;
+			};
+			fan-present {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FAN_PRESENT";
+				value = <1>;
+				/*
+				 * Set as default so that unprovisioned
+				 * configs will run the fan regardless.
+				 */
+				default;
+			};
+		};
+
+	};
+
+	/* Rotation matrices for motion sensors. */
+	motionsense-rotation-ref {
+		compatible = "cros-ec,motionsense-rotation-ref";
+		lid_rot_ref: lid-rotation-ref {
+			mat33 = <0 (-1) 0
+				 1 0 0
+				 0 0 1>;
+		};
+
+		lid_rot_ref1: lid-rotation-ref1 {
+			mat33 = <0 1 0
+				 (-1) 0 0
+				 0 0 1>;
+		};
+
+		base_rot_ref: base-rotation-ref {
+			mat33 = <0 1 0
+				 (-1) 0 0
+				 0 0 1>;
+		};
+	};
+};
+
+/* i2c overrides */
+&i2c0_0 {
+	/delete-node/ anx7483@3e;
+};
+&i2c4_1 {
+	/delete-node/ isl9241@9;
+	/delete-node/ isl9538@9;
+	charger: isl9238@9 {
+		compatible = "intersil,isl923x";
+		status = "okay";
+		reg = <0x9>;
+	};
+};
+
+/* usbc overrides */
+&usbc_port0 {
+	/delete-property/ chg_alt;
+};
+&amd_fp6_port0 {
+	board-set = "board_c0_amd_fp6_mux_set";
+};
+/* usbc overrides */
+&usbc_port0 {
+	usb-mux-chain-0 {
+		usb-muxes = <&amd_fp6_port0>;
+	};
+};
+/* fan overrides */
+&fan0 {
+	pwms = <&pwm0 0 PWM_KHZ(25) PWM_POLARITY_NORMAL>;
+	rpm_min = <2500>;
+	rpm_start = <2500>;
+	rpm_max = <4800>;
+};
+
+&temp_sensor_cpu {
+	temp_host_warn = <90>;
+	temp_host_high = <102>;
+	temp_host_halt = <104>;
+	temp_host_release_warn = <87>;
+	temp_host_release_high = <92>;
+	temp_host_release_halt = <94>;
+	temp_fan_off = <38>;
+	temp_fan_max = <76>;
+};
diff --git a/zephyr/program/skyrim/crystaldrift/src/board.c b/zephyr/program/skyrim/crystaldrift/src/board.c
new file mode 100644
index 0000000000..4d64696df1
--- /dev/null
+++ b/zephyr/program/skyrim/crystaldrift/src/board.c
@@ -0,0 +1,23 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "chipset.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "hooks.h"
+
+#include <zephyr/drivers/gpio.h>
+
+static void usb_porta_startup(void)
+{
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_usbhub_en), 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, usb_porta_startup, HOOK_PRIO_DEFAULT);
+
+static void usb_porta_shutdown(void)
+{
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_usbhub_en), 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, usb_porta_shutdown, HOOK_PRIO_DEFAULT);
diff --git a/zephyr/program/skyrim/crystaldrift/src/fan.c b/zephyr/program/skyrim/crystaldrift/src/fan.c
new file mode 100644
index 0000000000..21f9d66daa
--- /dev/null
+++ b/zephyr/program/skyrim/crystaldrift/src/fan.c
@@ -0,0 +1,62 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+#include "fan.h"
+#include "gpio/gpio.h"
+#include "hooks.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(crystaldrift, CONFIG_SKYRIM_LOG_LEVEL);
+
+/*
+ * Skyrim fan support
+ */
+test_export_static void fan_init(void)
+{
+	int ret;
+	uint32_t val;
+	uint32_t board_version;
+	/*
+	 * Retrieve the fan config.
+	 */
+	ret = cros_cbi_get_fw_config(FW_FAN, &val);
+	if (ret != 0) {
+		LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_FAN);
+		return;
+	}
+
+	ret = cbi_get_board_version(&board_version);
+	if (ret != EC_SUCCESS) {
+		LOG_ERR("Error retrieving CBI board version");
+		return;
+	}
+
+	if ((board_version >= 3) && (val != FW_FAN_PRESENT)) {
+		/* Disable the fan */
+		fan_set_count(0);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, fan_init, HOOK_PRIO_POST_FIRST);
+
+/*
+ * Pcore OCP support
+ * Note: early boards should note enable this interrupt as they are not
+ * correctly configured for it.
+ */
+__override bool board_supports_pcore_ocp(void)
+{
+	uint32_t board_version;
+
+	if (cbi_get_board_version(&board_version) == EC_SUCCESS &&
+	    board_version > 3)
+		return true;
+
+	return false;
+}
diff --git a/zephyr/program/skyrim/crystaldrift/src/form_factor.c b/zephyr/program/skyrim/crystaldrift/src/form_factor.c
new file mode 100644
index 0000000000..688765617b
--- /dev/null
+++ b/zephyr/program/skyrim/crystaldrift/src/form_factor.c
@@ -0,0 +1,38 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "accelgyro.h"
+#include "common.h"
+#include "cros_board_info.h"
+#include "hooks.h"
+#include "motionsense_sensors.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(crystaldrift, CONFIG_SKYRIM_LOG_LEVEL);
+
+/*
+ * Mainboard orientation support.
+ */
+
+#define ALT_MAT SENSOR_ROT_STD_REF_NAME(DT_NODELABEL(lid_rot_ref1))
+#define LID_ACCEL SENSOR_ID(DT_NODELABEL(lid_accel))
+
+static void form_factor_init(void)
+{
+	int ret;
+	uint32_t val;
+	/*
+	 * If the board version >=4
+	 * use ver1 rotation matrix.
+	 */
+	ret = cbi_get_board_version(&val);
+	if (ret == EC_SUCCESS && val >= 4) {
+		LOG_INF("Switching to ver1 lid");
+		motion_sensors[LID_ACCEL].rot_standard_ref = &ALT_MAT;
+	}
+}
+DECLARE_HOOK(HOOK_INIT, form_factor_init, HOOK_PRIO_POST_I2C);
diff --git a/zephyr/program/skyrim/crystaldrift/src/keyboard.c b/zephyr/program/skyrim/crystaldrift/src/keyboard.c
new file mode 100644
index 0000000000..fafdd40c0a
--- /dev/null
+++ b/zephyr/program/skyrim/crystaldrift/src/keyboard.c
@@ -0,0 +1,29 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+
+static const struct ec_response_keybd_config skyrim_kb = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &skyrim_kb;
+}
diff --git a/zephyr/program/skyrim/crystaldrift/src/ppc_config.c b/zephyr/program/skyrim/crystaldrift/src/ppc_config.c
new file mode 100644
index 0000000000..4a4bb07a3f
--- /dev/null
+++ b/zephyr/program/skyrim/crystaldrift/src/ppc_config.c
@@ -0,0 +1,31 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Crystaldrift board-specific PPC code */
+
+#include "driver/ppc/aoz1380_public.h"
+#include "driver/ppc/nx20p348x.h"
+#include "usbc_ppc.h"
+
+#include <zephyr/drivers/gpio.h>
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		nx20p348x_interrupt(0);
+		break;
+
+	case GPIO_USB_C1_PPC_INT_ODL:
+		nx20p348x_interrupt(1);
+		break;
+
+	default:
+		break;
+	}
+}
diff --git a/zephyr/program/skyrim/crystaldrift/src/thermal.c b/zephyr/program/skyrim/crystaldrift/src/thermal.c
new file mode 100644
index 0000000000..053fb48027
--- /dev/null
+++ b/zephyr/program/skyrim/crystaldrift/src/thermal.c
@@ -0,0 +1,109 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "fan.h"
+#include "hooks.h"
+#include "tablet_mode.h"
+#include "temp_sensor/temp_sensor.h"
+#include "thermal.h"
+#include "util.h"
+
+#define TEMP_CPU TEMP_SENSOR_ID(DT_NODELABEL(temp_sensor_cpu))
+
+struct fan_step {
+	/*
+	 * Sensor 0~4 trigger point, set -1 if we're not using this
+	 * sensor to determine fan speed.
+	 */
+	int on[TEMP_SENSOR_COUNT];
+	/*
+	 * Sensor 0~4 release point, set -1 if we're not using this
+	 * sensor to determine fan speed.
+	 */
+	int off[TEMP_SENSOR_COUNT];
+	/* Fan rpm */
+	uint16_t rpm[FAN_CH_COUNT];
+};
+
+#define FAN_TABLE_ENTRY(nd)                     \
+	{                                       \
+		.on = DT_PROP(nd, temp_on),     \
+		.off = DT_PROP(nd, temp_off),   \
+		.rpm = DT_PROP(nd, rpm_target), \
+	},
+static const struct fan_step fan_table[] = { DT_FOREACH_CHILD(
+	DT_NODELABEL(fan_steps), FAN_TABLE_ENTRY) };
+
+static const struct fan_step *fan_step_table = fan_table;
+#define NUM_FAN_LEVELS ARRAY_SIZE(fan_table)
+
+int fan_table_to_rpm(int fan, int *temp)
+{
+	/* current fan level */
+	static int current_level;
+	/* previous sensor temperature */
+	static int prev_tmp[TEMP_SENSOR_COUNT];
+	int i;
+
+	/*
+	 * Compare the current and previous temperature, we have
+	 * the three paths :
+	 *  1. decreasing path. (check the release point)
+	 *  2. increasing path. (check the trigger point)
+	 *  3. invariant path. (return the current RPM)
+	 */
+
+	if (temp[TEMP_CPU] < prev_tmp[TEMP_CPU]) {
+		for (i = current_level; i > 0; i--) {
+			if (temp[TEMP_CPU] <= fan_step_table[i].off[TEMP_CPU])
+				current_level = i - 1;
+			else
+				break;
+		}
+	} else if (temp[TEMP_CPU] > prev_tmp[TEMP_CPU]) {
+		for (i = current_level; i < NUM_FAN_LEVELS; i++) {
+			if (temp[TEMP_CPU] >= fan_step_table[i].on[TEMP_CPU])
+				current_level = i;
+			else
+				break;
+		}
+	}
+
+	if (current_level < 0)
+		current_level = 0;
+
+	if (current_level >= NUM_FAN_LEVELS)
+		current_level = NUM_FAN_LEVELS - 1;
+
+	for (i = 0; i < TEMP_SENSOR_COUNT; ++i)
+		prev_tmp[i] = temp[i];
+
+	return fan_step_table[current_level].rpm[fan];
+}
+
+void board_override_fan_control(int fan, int *temp)
+{
+	static int prev_rpm;
+	int current_rpm = 0;
+
+	/*
+	 * In common/fan.c pwm_fan_stop() will turn off fan
+	 * when chipset suspend or shutdown.
+	 */
+	if (chipset_in_state(CHIPSET_STATE_ON)) {
+		fan_set_rpm_mode(fan, 1);
+		current_rpm = fan_table_to_rpm(fan, temp);
+
+		if (current_rpm == prev_rpm) {
+			return;
+		}
+
+		fan_set_rpm_target(fan, current_rpm);
+		prev_rpm = current_rpm;
+	}
+}
diff --git a/zephyr/program/skyrim/crystaldrift/src/usb_mux_config.c b/zephyr/program/skyrim/crystaldrift/src/usb_mux_config.c
new file mode 100644
index 0000000000..bc5b61279e
--- /dev/null
+++ b/zephyr/program/skyrim/crystaldrift/src/usb_mux_config.c
@@ -0,0 +1,178 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Crystaldrift board-specific USB-C mux configuration */
+
+#include "console.h"
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+#include "driver/retimer/anx7483_public.h"
+#include "hooks.h"
+#include "ioexpander.h"
+#include "usb_mux.h"
+#include "usbc/usb_muxes.h"
+#include "ztest/usb_mux_config.h"
+
+#include <zephyr/drivers/gpio.h>
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/*
+ * USB C0 (general) and C1 (just ANX DB) use IOEX pins to
+ * indicate flipped polarity to a protection switch.
+ */
+test_export_static int ioex_set_flip(int port, mux_state_t mux_state)
+{
+	if (port == 0) {
+		if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
+			gpio_pin_set_dt(
+				GPIO_DT_FROM_NODELABEL(ioex_usb_c0_sbu_flip),
+				1);
+		else
+			gpio_pin_set_dt(
+				GPIO_DT_FROM_NODELABEL(ioex_usb_c0_sbu_flip),
+				0);
+	} else {
+		if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
+			gpio_pin_set_dt(
+				GPIO_DT_FROM_NODELABEL(ioex_usb_c1_sbu_flip),
+				1);
+		else
+			gpio_pin_set_dt(
+				GPIO_DT_FROM_NODELABEL(ioex_usb_c1_sbu_flip),
+				0);
+	}
+
+	return EC_SUCCESS;
+}
+
+int board_c0_amd_fp6_mux_set(const struct usb_mux *me, mux_state_t mux_state)
+{
+	/* Set the SBU polarity mux */
+	RETURN_ERROR(ioex_set_flip(me->usb_port, mux_state));
+
+	return EC_SUCCESS;
+}
+
+int board_anx7483_c1_fg_defalut_tuning(const struct usb_mux *me)
+{
+	RETURN_ERROR(
+		anx7483_set_fg(me, ANX7483_PIN_URX1, ANX7483_FG_SETTING_1_2DB));
+	RETURN_ERROR(
+		anx7483_set_fg(me, ANX7483_PIN_URX2, ANX7483_FG_SETTING_1_2DB));
+	RETURN_ERROR(
+		anx7483_set_fg(me, ANX7483_PIN_UTX1, ANX7483_FG_SETTING_1_2DB));
+	RETURN_ERROR(
+		anx7483_set_fg(me, ANX7483_PIN_UTX2, ANX7483_FG_SETTING_1_2DB));
+
+	return EC_SUCCESS;
+}
+int board_anx7483_c1_mux_set(const struct usb_mux *me, mux_state_t mux_state)
+{
+	bool flipped = mux_state & USB_PD_MUX_POLARITY_INVERTED;
+
+	/* Set the SBU polarity mux */
+	RETURN_ERROR(ioex_set_flip(me->usb_port, mux_state));
+
+	/* Remove flipped from the state for easier compraisons */
+	mux_state = mux_state & ~USB_PD_MUX_POLARITY_INVERTED;
+
+	RETURN_ERROR(anx7483_set_default_tuning(me, mux_state));
+
+	/*
+	 * Set the Flat Gain to default every time, to prevent DP only mode's
+	 * Flat Gain change in the last plug.
+	 */
+	RETURN_ERROR(board_anx7483_c1_fg_defalut_tuning(me));
+
+	if (mux_state == USB_PD_MUX_USB_ENABLED) {
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX1,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX2,
+					    ANX7483_EQ_SETTING_12_5DB));
+	} else if (mux_state == USB_PD_MUX_DP_ENABLED) {
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1,
+					    ANX7483_EQ_SETTING_8_4DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2,
+					    ANX7483_EQ_SETTING_8_4DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX1,
+					    ANX7483_EQ_SETTING_8_4DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX2,
+					    ANX7483_EQ_SETTING_8_4DB));
+		RETURN_ERROR(anx7483_set_fg(me, ANX7483_PIN_URX1,
+					    ANX7483_FG_SETTING_0_5DB));
+		RETURN_ERROR(anx7483_set_fg(me, ANX7483_PIN_URX2,
+					    ANX7483_FG_SETTING_0_5DB));
+		RETURN_ERROR(anx7483_set_fg(me, ANX7483_PIN_UTX1,
+					    ANX7483_FG_SETTING_0_5DB));
+		RETURN_ERROR(anx7483_set_fg(me, ANX7483_PIN_UTX2,
+					    ANX7483_FG_SETTING_0_5DB));
+	} else if (mux_state == USB_PD_MUX_DOCK && !flipped) {
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2,
+					    ANX7483_EQ_SETTING_8_4DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX1,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX2,
+					    ANX7483_EQ_SETTING_8_4DB));
+		RETURN_ERROR(anx7483_set_fg(me, ANX7483_PIN_URX2,
+					    ANX7483_FG_SETTING_0_5DB));
+		RETURN_ERROR(anx7483_set_fg(me, ANX7483_PIN_UTX2,
+					    ANX7483_FG_SETTING_0_5DB));
+	} else if (mux_state == USB_PD_MUX_DOCK && flipped) {
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1,
+					    ANX7483_EQ_SETTING_8_4DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX1,
+					    ANX7483_EQ_SETTING_8_4DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX2,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_fg(me, ANX7483_PIN_URX1,
+					    ANX7483_FG_SETTING_0_5DB));
+		RETURN_ERROR(anx7483_set_fg(me, ANX7483_PIN_UTX1,
+					    ANX7483_FG_SETTING_0_5DB));
+	}
+
+	return EC_SUCCESS;
+}
+
+int board_c1_ps8818_mux_set(const struct usb_mux *me, mux_state_t mux_state)
+{
+	CPRINTSUSB("C1: PS8818 mux using default tuning");
+
+	/* Once a DP connection is established, we need to set IN_HPD */
+	if (mux_state & USB_PD_MUX_DP_ENABLED)
+		ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 1);
+	else
+		ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 0);
+
+	return 0;
+}
+
+static void setup_mux(void)
+{
+	uint32_t val;
+
+	if (cros_cbi_get_fw_config(FW_IO_DB, &val) != 0)
+		CPRINTSUSB("Error finding FW_DB_IO in CBI FW_CONFIG");
+	/* Val will have our dts default on error, so continue setup */
+
+	if (val == FW_IO_DB_PS8811_PS8818) {
+		CPRINTSUSB("C1: Setting PS8818 mux");
+		USB_MUX_ENABLE_ALTERNATIVE(usb_mux_chain_ps8818_port1);
+	} else if (val == FW_IO_DB_NONE_ANX7483) {
+		CPRINTSUSB("C1: Setting ANX7483 mux");
+	} else {
+		CPRINTSUSB("Unexpected DB_IO board: %d", val);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, setup_mux, HOOK_PRIO_INIT_I2C);
diff --git a/zephyr/program/skyrim/fan.dtsi b/zephyr/program/skyrim/fan.dtsi
new file mode 100644
index 0000000000..dff26bcb29
--- /dev/null
+++ b/zephyr/program/skyrim/fan.dtsi
@@ -0,0 +1,39 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	fans {
+		compatible = "cros-ec,fans";
+
+		fan0: fan_0 {
+			pwms = <&pwm0 0 PWM_KHZ(25) PWM_POLARITY_NORMAL>;
+			rpm_min = <3100>;
+			rpm_start = <3100>;
+			rpm_max = <8000>;
+			tach = <&tach1>;
+			pgood_gpio = <&gpio_s0_pgood>;
+		};
+	};
+};
+
+/* Tachemeter for fan speed measurement */
+&tach1 {
+	status = "okay";
+	pinctrl-0 = <&ta1_1_in_gp40>;
+	pinctrl-names = "default";
+	port = <NPCX_TACH_PORT_A>; /* port-A is selected */
+	sample-clk = <NPCX_TACH_FREQ_LFCLK>; /* Use LFCLK as sampling clock */
+	pulses-per-round = <2>; /* number of pulses per round of encoder */
+};
+
+&pwm0_gpc3 {
+	drive-open-drain;
+};
+
+&pwm0 {
+	status = "okay";
+	pinctrl-0 = <&pwm0_gpc3>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/skyrim/frostflow/CMakeLists.txt b/zephyr/program/skyrim/frostflow/CMakeLists.txt
new file mode 100644
index 0000000000..dc5d3b0467
--- /dev/null
+++ b/zephyr/program/skyrim/frostflow/CMakeLists.txt
@@ -0,0 +1,16 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cros_ec_library_include_directories_ifdef(CONFIG_BOARD_FROSTFLOW include)
+zephyr_include_directories("include")
+zephyr_library_sources(
+		"src/usb_mux_config.c"
+		"src/ppc_config.c"
+		"src/thermal.c"
+		"src/charger.c"
+)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_KEYBOARD_CUSTOMIZATION
+	"src/keyboard.c"
+	"src/keyboard_customization.c"
+)
diff --git a/zephyr/program/skyrim/frostflow/include/keyboard_customization.h b/zephyr/program/skyrim/frostflow/include/keyboard_customization.h
new file mode 100644
index 0000000000..2f8e9b71a1
--- /dev/null
+++ b/zephyr/program/skyrim/frostflow/include/keyboard_customization.h
@@ -0,0 +1,80 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Keyboard configuration */
+
+#ifndef __KEYBOARD_CUSTOMIZATION_H
+#define __KEYBOARD_CUSTOMIZATION_H
+
+#define KEYBOARD_MASK_PWRBTN KEYBOARD_ROW_TO_MASK(3)
+
+/*
+ * KEYBOARD_COLS_MAX has the build time column size. It's used to allocate
+ * exact spaces for arrays. Actual keyboard scanning is done using
+ * keyboard_cols, which holds a runtime column size.
+ */
+#ifdef CONFIG_KEYBOARD_CUSTOMIZATION
+#undef KEYBOARD_COLS_MAX
+#undef KEYBOARD_ROWS
+
+#define KEYBOARD_COLS_MAX 15
+#define KEYBOARD_ROWS 8
+#endif
+
+/*
+ * WARNING: Do not directly modify it. You should call keyboard_raw_set_cols,
+ * instead. It checks whether you're eligible or not.
+ */
+extern uint8_t keyboard_cols;
+
+#define KEYBOARD_ROW_TO_MASK(r) (1 << (r))
+
+/* Columns and masks for keys we particularly care about */
+#define KEYBOARD_COL_DOWN 11
+#define KEYBOARD_ROW_DOWN 5
+#define KEYBOARD_MASK_DOWN KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_DOWN)
+#define KEYBOARD_COL_ESC 1
+#define KEYBOARD_ROW_ESC 1
+#define KEYBOARD_MASK_ESC KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_ESC)
+#define KEYBOARD_COL_KEY_H 6
+#define KEYBOARD_ROW_KEY_H 1
+#define KEYBOARD_MASK_KEY_H KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_H)
+#define KEYBOARD_COL_KEY_R 3
+#define KEYBOARD_ROW_KEY_R 7
+#define KEYBOARD_MASK_KEY_R KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_R)
+#define KEYBOARD_COL_LEFT_ALT 10
+#define KEYBOARD_ROW_LEFT_ALT 6
+#define KEYBOARD_MASK_LEFT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_ALT)
+#define KEYBOARD_COL_REFRESH 2
+#define KEYBOARD_ROW_REFRESH 3
+#define KEYBOARD_MASK_REFRESH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_REFRESH)
+#define KEYBOARD_COL_RIGHT_ALT 10
+#define KEYBOARD_ROW_RIGHT_ALT 0
+#define KEYBOARD_MASK_RIGHT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_ALT)
+#define KEYBOARD_DEFAULT_COL_VOL_UP 4
+#define KEYBOARD_DEFAULT_ROW_VOL_UP 1
+#define KEYBOARD_COL_LEFT_CTRL 0
+#define KEYBOARD_ROW_LEFT_CTRL 2
+#define KEYBOARD_MASK_LEFT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_CTRL)
+#define KEYBOARD_COL_RIGHT_CTRL 0
+#define KEYBOARD_ROW_RIGHT_CTRL 4
+#define KEYBOARD_MASK_RIGHT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_CTRL)
+#define KEYBOARD_COL_SEARCH 0
+#define KEYBOARD_ROW_SEARCH 3
+#define KEYBOARD_MASK_SEARCH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_SEARCH)
+#define KEYBOARD_COL_KEY_0 9
+#define KEYBOARD_ROW_KEY_0 0
+#define KEYBOARD_MASK_KEY_0 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_0)
+#define KEYBOARD_COL_KEY_1 1
+#define KEYBOARD_ROW_KEY_1 7
+#define KEYBOARD_MASK_KEY_1 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_1)
+#define KEYBOARD_COL_KEY_2 4
+#define KEYBOARD_ROW_KEY_2 6
+#define KEYBOARD_MASK_KEY_2 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_2)
+#define KEYBOARD_COL_LEFT_SHIFT 7
+#define KEYBOARD_ROW_LEFT_SHIFT 1
+#define KEYBOARD_MASK_LEFT_SHIFT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_SHIFT)
+
+#endif /* __KEYBOARD_CUSTOMIZATION_H */
diff --git a/zephyr/program/skyrim/frostflow/led_pins.dtsi b/zephyr/program/skyrim/frostflow/led_pins.dtsi
new file mode 100644
index 0000000000..28766c5271
--- /dev/null
+++ b/zephyr/program/skyrim/frostflow/led_pins.dtsi
@@ -0,0 +1,58 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	pwmleds {
+		compatible = "pwm-leds";
+		pwm_y: pwm_y {
+			pwms = <&pwm2 0 PWM_HZ(100) PWM_POLARITY_INVERTED>;
+		};
+		pwm_w: pwm_w {
+			pwms = <&pwm3 0 PWM_HZ(100) PWM_POLARITY_INVERTED>;
+		};
+	};
+
+	pwm-led-pins {
+		compatible = "cros-ec,pwm-led-pins";
+
+		battery_led: battery-led {
+			led-id = "EC_LED_ID_BATTERY_LED";
+			led-pwms = <&pwm_y &pwm_w>;
+
+			color_off: color-off {
+				led-color = "LED_OFF";
+				led-values = <0 0>;
+			};
+
+			color_amber: color-amber {
+				led-color = "LED_AMBER";
+				br-color = "EC_LED_COLOR_AMBER";
+				led-values = <100 0>;
+			};
+
+			color_white: color-white {
+				led-color = "LED_WHITE";
+				br-color = "EC_LED_COLOR_WHITE";
+				led-values = <0 100>;
+			};
+		};
+	};
+};
+
+/* Amber "battery charging" LED */
+&pwm2 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm2_gpc4>;
+	pinctrl-names = "default";
+};
+
+/* White "battery full" LED */
+&pwm3 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm3_gp80>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/skyrim/frostflow/led_policy.dtsi b/zephyr/program/skyrim/frostflow/led_policy.dtsi
new file mode 100644
index 0000000000..66d61e454e
--- /dev/null
+++ b/zephyr/program/skyrim/frostflow/led_policy.dtsi
@@ -0,0 +1,136 @@
+/ {
+	led-colors {
+		compatible = "cros-ec,led-policy";
+
+		power-state-charge {
+			charge-state = "LED_PWRS_CHARGE";
+			/* Battery percent range (>= Empty, <= 94%) */
+			batt-lvl = <0 94>;
+
+			color-0 {
+				led-color = <&color_amber>;
+			};
+		};
+
+		power-state-charge-lvl-2 {
+			charge-state = "LED_PWRS_CHARGE";
+			/* Battery percent range (>= 95%, <= 100%) */
+			batt-lvl = <95 100>;
+
+			color-0 {
+				led-color = <&color_white>;
+			};
+		};
+
+		power-state-near-full {
+			charge-state = "LED_PWRS_CHARGE_NEAR_FULL";
+
+			color-0 {
+				led-color = <&color_white>;
+			};
+		};
+
+		power-state-discharge-s0 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S0";
+			/* Battery percent range (>= 11%, <= Full) */
+			batt-lvl = <11 100>;
+
+			color-0 {
+				led-color = <&color_white>;
+			};
+		};
+
+		power-state-discharge-s0-batt-low {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S0";
+			/* Battery percent range (>= Empty, <= 10%) */
+			batt-lvl = <0 10>;
+
+			/* Amber 1 sec, off 3 sec */
+			color-0 {
+				led-color = <&color_amber>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <3000>;
+			};
+		};
+
+		power-state-discharge-s3 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S3";
+
+			/* White 1 sec, off 3 sec */
+			color-0 {
+				led-color = <&color_white>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <3000>;
+			};
+		};
+
+		power-state-discharge-s5 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S5";
+
+			color-0 {
+				led-color = <&color_off>;
+			};
+		};
+
+		power-state-error-s0 {
+			charge-state = "LED_PWRS_ERROR";
+			chipset-state = "POWER_S0";
+			/* Amber 1 sec, off 1 sec */
+			color-0 {
+				led-color = <&color_amber>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <1000>;
+			};
+		};
+
+		power-state-error-s3 {
+			charge-state = "LED_PWRS_ERROR";
+			chipset-state = "POWER_S3";
+			/* White 1 sec, off 3 sec */
+			color-0 {
+				led-color = <&color_white>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <3000>;
+			};
+		};
+
+		power-state-error-s5 {
+			charge-state = "LED_PWRS_ERROR";
+			chipset-state = "POWER_S5";
+
+			color-0 {
+				led-color = <&color_off>;
+			};
+		};
+
+		power-state-forced-idle {
+			charge-state = "LED_PWRS_FORCED_IDLE";
+
+			/* Amber 2 sec, White 2 sec */
+			color-0 {
+				led-color = <&color_amber>;
+				period-ms = <2000>;
+			};
+			color-1 {
+				led-color = <&color_white>;
+				period-ms = <2000>;
+			};
+		};
+	};
+};
diff --git a/zephyr/program/skyrim/frostflow/motionsense.dtsi b/zephyr/program/skyrim/frostflow/motionsense.dtsi
new file mode 100644
index 0000000000..119c4aaf8e
--- /dev/null
+++ b/zephyr/program/skyrim/frostflow/motionsense.dtsi
@@ -0,0 +1,133 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/motionsense/utils.h>
+
+
+/ {
+	aliases {
+		/*
+		 * motion sense's <>_INT_EVENT is handled
+		 * by alias. Using the alias, each driver creates
+		 * its own <>_INT_EVENT.
+		 */
+		bmi3xx-int = &base_accel;
+		bma4xx-int = &lid_accel;
+	};
+
+	/*
+	 * Declare mutexes used by sensor drivers.
+	 * A mutex node is used to create an instance of mutex_t.
+	 * A mutex node is referenced by a sensor node if the
+	 * corresponding sensor driver needs to use the
+	 * instance of the mutex.
+	 */
+	motionsense-mutex {
+		compatible = "cros-ec,motionsense-mutex";
+		lid_mutex: lid-mutex {
+		};
+
+		mutex_bmi3xx: bmi3xx-mutex {
+		};
+	};
+
+	/*
+	 * Driver specific data. A driver-specific data can be shared with
+	 * different motion sensors while they are using the same driver.
+	 *
+	 * If a node's compatible starts with "cros-ec,accelgyro-", it is for
+	 * a common structure defined in accelgyro.h.
+	 * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for
+	 * "struct als_drv_data_t" in accelgyro.h
+	 */
+	motionsense-sensor-data {
+		bma4xx_data: bma4xx-drv-data {
+			compatible = "cros-ec,drvdata-bma4xx";
+			status = "okay";
+		};
+
+		bmi3xx_data: bmi3xx-drv-data {
+			compatible = "cros-ec,drvdata-bmi3xx";
+			status = "okay";
+		};
+	};
+
+	/*
+	 * List of motion sensors that creates motion_sensors array.
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
+	 * motion sensor IDs for lid angle calculation.
+	 */
+	motionsense-sensor {
+		lid_accel: lid-accel {
+			compatible = "cros-ec,bma4xx";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&lid_mutex>;
+			port = <&i2c_sensor>;
+			drv-data = <&bma4xx_data>;
+			rot-standard-ref = <&lid_rot_ref>;
+			default-range = <2>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(12500 | ROUND_UP_FLAG)>;
+					ec-rate = <100>;
+				};
+				ec-s3 {
+					odr = <(12500 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_accel: base-accel {
+			compatible = "cros-ec,bmi3xx-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&mutex_bmi3xx>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&bmi3xx_data>;
+
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(12500 | ROUND_UP_FLAG)>;
+					ec-rate = <100>;
+				};
+				ec-s3 {
+					odr = <(12500 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base-gyro {
+			compatible = "cros-ec,bmi3xx-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&mutex_bmi3xx>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&bmi3xx_data>;
+		};
+	};
+
+	motionsense-sensor-info {
+		compatible = "cros-ec,motionsense-sensor-info";
+
+		/*
+		 * list of GPIO interrupts that have to
+		 * be enabled at initial stage
+		 */
+		sensor-irqs = <&int_lid_accel &int_accel_gyro>;
+	};
+};
diff --git a/zephyr/program/skyrim/frostflow/project.conf b/zephyr/program/skyrim/frostflow/project.conf
new file mode 100644
index 0000000000..24503514c4
--- /dev/null
+++ b/zephyr/program/skyrim/frostflow/project.conf
@@ -0,0 +1,29 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Frostflow reference-board-specific Kconfig settings.
+CONFIG_BOARD_FROSTFLOW=y
+CONFIG_PLATFORM_EC_CHARGER_INPUT_CURRENT_DERATE_PCT=10
+
+CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=n
+
+# Frostflow is capable of sinking 45W
+CONFIG_PLATFORM_EC_PD_MAX_POWER_MW=45000
+CONFIG_PLATFORM_EC_PD_MAX_CURRENT_MA=3000
+CONFIG_PLATFORM_EC_PD_MAX_VOLTAGE_MV=20000
+CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON=45000
+
+# Keyboard
+CONFIG_PLATFORM_EC_KEYBOARD_CUSTOMIZATION=y
+
+# Frostflow not have the USB HUB
+CONFIG_BOARD_USB_HUB_RESET=n
+
+# Battery
+CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO=y
+
+# Fan
+CONFIG_PLATFORM_EC_CUSTOM_FAN_CONTROL=y
+
+CONFIG_PLATFORM_EC_USB_PD_STARTUP_DELAY_MS=250
diff --git a/zephyr/program/skyrim/frostflow/project.overlay b/zephyr/program/skyrim/frostflow/project.overlay
new file mode 100644
index 0000000000..82b0beb683
--- /dev/null
+++ b/zephyr/program/skyrim/frostflow/project.overlay
@@ -0,0 +1,312 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Skyrim program common DTS includes */
+#include "../adc.dtsi"
+#include "../fan.dtsi"
+#include "../gpio.dtsi"
+#include "../i2c.dtsi"
+#include "../interrupts.dtsi"
+#include "../keyboard.dtsi"
+#include "../usbc.dtsi"
+
+/* Frostflow project DTS includes*/
+#include "led_pins.dtsi"
+#include "led_policy.dtsi"
+#include "motionsense.dtsi"
+
+/* Frostflow overrides follow... */
+/ {
+	/* battery overrides */
+	batteries {
+		default_battery: cdt_c340152 {
+			compatible = "cdt,c340152", "battery-smart";
+		};
+	};
+
+	named-gpios {
+		/* Frostflow-specific GPIO customizations */
+	};
+
+	gpio-interrupts {
+		int_lid_accel: lid_accel {
+			irq-pin = <&gpio_lid_accel_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "bma4xx_interrupt";
+		};
+	};
+
+	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
+		temp_soc: soc-pct2075 {
+			temp_host_high = <75>;
+			temp_host_halt = <80>;
+			temp_host_release_high = <65>;
+			temp_host_release_halt = <70>;
+			power-good-pin = <&gpio_pg_pwr_s5>;
+			sensor = <&soc_pct2075>;
+		};
+		temp_amb: amb-pct2075 {
+			temp_host_high = <65>;
+			temp_host_halt = <70>;
+			temp_host_release_high = <55>;
+			temp_host_release_halt = <60>;
+			temp_fan_off = <32>;
+			temp_fan_max = <45>;
+			power-good-pin = <&gpio_pg_pwr_s5>;
+			sensor = <&amb_pct2075>;
+		};
+	};
+
+	/* Rotation matrices for motion sensors. */
+	motionsense-rotation-ref {
+		compatible = "cros-ec,motionsense-rotation-ref";
+		lid_rot_ref: lid-rotation-ref {
+			mat33 = <1 0 0
+				 0 1 0
+				 0 0 1>;
+		};
+
+		base_rot_ref: base-rotation-ref {
+			mat33 = <0 1 0
+				 1 0 0
+				 0 0 (-1)>;
+		};
+	};
+
+	ppc_port0: aoz1380 {
+		compatible = "aoz,aoz1380";
+		status = "okay";
+	};
+
+	fan_steps_clamshell: fan-steps-clamshell {
+		compatible = "cros-ec,fan-steps";
+		level_0 {
+			temp_on = <(-1) 37 (-1) (-1) (-1)>;
+			temp_off = <(-1) 99 (-1) (-1) (-1)>;
+			rpm_target = <0>;
+		};
+		level_1 {
+			temp_on = <(-1) 38 (-1) (-1) (-1)>;
+			temp_off = <(-1) 33 (-1) (-1) (-1)>;
+			rpm_target = <2600>;
+		};
+		level_2 {
+			temp_on = <(-1) 42 (-1) (-1) (-1)>;
+			temp_off = <(-1) 37 (-1) (-1) (-1)>;
+			rpm_target = <2900>;
+		};
+		level_3 {
+			temp_on = <(-1) 48 (-1) (-1) (-1)>;
+			temp_off = <(-1) 41 (-1) (-1) (-1)>;
+			rpm_target = <3200>;
+		};
+		level_4 {
+			temp_on = <(-1) 49 (-1) (-1) (-1)>;
+			temp_off = <(-1) 45 (-1) (-1) (-1)>;
+			rpm_target = <3500>;
+		};
+		level_5 {
+			temp_on = <(-1) 50 (-1) (-1) (-1)>;
+			temp_off = <(-1) 46 (-1) (-1) (-1)>;
+			rpm_target = <3700>;
+		};
+		level_6 {
+			temp_on = <(-1) 51 (-1) (-1) (-1)>;
+			temp_off = <(-1) 47 (-1) (-1) (-1)>;
+			rpm_target = <4200>;
+		};
+		level_7 {
+			temp_on = <(-1) 62 (-1) (-1) (-1)>;
+			temp_off = <(-1) 55 (-1) (-1) (-1)>;
+			rpm_target = <4600>;
+		};
+	};
+
+	fan_steps_tablet: fan-steps-tablet {
+		compatible = "cros-ec,fan-steps";
+		level_0 {
+			temp_on = <(-1) 38 (-1) (-1) (-1)>;
+			temp_off = <(-1) 99 (-1) (-1) (-1)>;
+			rpm_target = <0>;
+		};
+		level_1 {
+			temp_on = <(-1) 39 (-1) (-1) (-1)>;
+			temp_off = <(-1) 37 (-1) (-1) (-1)>;
+			rpm_target = <2600>;
+		};
+		level_2 {
+			temp_on = <(-1) 45 (-1) (-1) (-1)>;
+			temp_off = <(-1) 38 (-1) (-1) (-1)>;
+			rpm_target = <2900>;
+		};
+		level_3 {
+			temp_on = <(-1) 54 (-1) (-1) (-1)>;
+			temp_off = <(-1) 44 (-1) (-1) (-1)>;
+			rpm_target = <3200>;
+		};
+		level_4 {
+			temp_on = <(-1) 55 (-1) (-1) (-1)>;
+			temp_off = <(-1) 51 (-1) (-1) (-1)>;
+			rpm_target = <3500>;
+		};
+		level_5 {
+			temp_on = <(-1) 56 (-1) (-1) (-1)>;
+			temp_off = <(-1) 52 (-1) (-1) (-1)>;
+			rpm_target = <3700>;
+		};
+		level_6 {
+			temp_on = <(-1) 57 (-1) (-1) (-1)>;
+			temp_off = <(-1) 53 (-1) (-1) (-1)>;
+			rpm_target = <4200>;
+		};
+		level_7 {
+			temp_on = <(-1) 61 (-1) (-1) (-1)>;
+			temp_off = <(-1) 56 (-1) (-1) (-1)>;
+			rpm_target = <4600>;
+		};
+	};
+
+	/*
+	 * Note this is expected to vary per-board, so we keep it in the board
+	 * dts files.
+	 */
+	Frostflow-fw-config {
+		compatible = "cros-ec,cbi-fw-config";
+
+		/*
+		* FW_CONFIG field to enable fingerprint or not.
+		*/
+		fingerprint {
+			enum-name = "FW_FINGERPRINT";
+			start = <0>;
+			size = <1>;
+
+			fingerprint-absent{
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FINGERPRINT_ABSENT";
+				value = <0>;
+			};
+			fingerprint-present {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FINGERPRINT_PRESENT";
+				value = <1>;
+			};
+		};
+		/*
+		* FW_CONFIG field to enable stylus or not.
+		*/
+		stylus {
+			enum-name = "FW_STYLUS";
+			start = <1>;
+			size = <1>;
+
+			stylus-absent {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_STYLUS_ABSENT";
+				value = <0>;
+			};
+			stylus-present {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_STYLUS_PRESENT";
+				value = <1>;
+			};
+		};
+	};
+};
+
+/* i2c overrides */
+&i2c0_0 {
+	/delete-node/ nx20p348x@71;
+	/delete-node/ anx7483@3e;
+};
+
+&i2c1_0 {
+	/delete-node/ anx7483@3e;
+};
+
+&i2c4_1 {
+	/delete-node/ isl9538@9;
+};
+
+&amd_fp6_port0 {
+	board-set = "board_c0_amd_fp6_mux_set";
+};
+
+/* usbc overrides */
+&usbc_port0 {
+	/delete-property/ chg_alt;
+	usb-mux-chain-0 {
+		usb-muxes = <&amd_fp6_port0>;
+	};
+};
+
+&usbc_port1 {
+	/delete-node/ usb-mux-chain-1-anx;
+	/delete-node/ usb-mux-chain-1-ps;
+	usb-mux-chain-1-ps8818 {
+		compatible = "cros-ec,usb-mux-chain";
+		usb-muxes = <&amd_fp6_port1 &ps8818_port1>;
+	};
+};
+
+&cros_kb_raw {
+	pinctrl-0 = <
+		&ksi0_gp31
+		&ksi1_gp30
+		&ksi2_gp27
+		&ksi3_gp26
+		&ksi4_gp25
+		&ksi5_gp24
+		&ksi6_gp23
+		&ksi7_gp22
+		&kso00_gp21
+		&kso01_gp20
+		&kso03_gp16
+		&kso04_gp15
+		&kso05_gp14
+		&kso06_gp13
+		&kso07_gp12
+		&kso08_gp11
+		&kso09_gp10
+		&kso10_gp07
+		&kso11_gp06
+		&kso12_gp05
+		&kso13_gp04
+		&kso14_gp82
+	>;
+};
+
+/* temperature sensor overrides */
+&temp_sensor_charger {
+	temp_host_high = <75>;
+	temp_host_halt = <80>;
+	temp_host_release_high = <65>;
+	temp_host_release_halt = <70>;
+};
+
+&temp_sensor_memory {
+	temp_host_high = <75>;
+	temp_host_halt = <80>;
+	temp_host_release_high = <65>;
+	temp_host_release_halt = <70>;
+};
+
+&temp_sensor_cpu {
+	/delete-property/ temp_host_high;
+	/delete-property/ temp_host_halt;
+	/delete-property/ temp_host_release_high;
+	/delete-property/ temp_fan_off;
+	/delete-property/ temp_fan_max;
+};
+
+/* fan overrides */
+&fan0 {
+	pwms = <&pwm0 0 PWM_KHZ(25) PWM_POLARITY_NORMAL>;
+	rpm_min = <2400>;
+	rpm_start = <2600>;
+	rpm_max = <4600>;
+	rpm_deviation = <2>;
+};
diff --git a/zephyr/program/skyrim/frostflow/src/charger.c b/zephyr/program/skyrim/frostflow/src/charger.c
new file mode 100644
index 0000000000..18e78bedb3
--- /dev/null
+++ b/zephyr/program/skyrim/frostflow/src/charger.c
@@ -0,0 +1,27 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "charger.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "driver/charger/isl9241.h"
+#include "hooks.h"
+#include "util.h"
+
+static void charger_set_frequence_to_600KHZ(void)
+{
+	charger_set_frequency(600);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, charger_set_frequence_to_600KHZ,
+	     HOOK_PRIO_DEFAULT);
+
+static void charger_set_frequence_to_1020KHZ(void)
+{
+	charger_set_frequency(1020);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, charger_set_frequence_to_1020KHZ,
+	     HOOK_PRIO_DEFAULT);
diff --git a/zephyr/program/skyrim/frostflow/src/keyboard.c b/zephyr/program/skyrim/frostflow/src/keyboard.c
new file mode 100644
index 0000000000..2905f17941
--- /dev/null
+++ b/zephyr/program/skyrim/frostflow/src/keyboard.c
@@ -0,0 +1,74 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+#include "keyboard_scan.h"
+#include "timer.h"
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/* Increase from 50 us, because KSO_02 passes through the H1. */
+	.output_settle_us = 80,
+	/* Other values should be the same as the default configuration. */
+	.debounce_down_us = 9 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x1c, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0x86, 0xff, 0xff, 0x55, 0xff, 0xff, 0xff, 0xff,  /* full set */
+	},
+};
+
+static const struct ec_response_keybd_config frostflow_kb = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &frostflow_kb;
+}
+
+/*
+ * Row Column info for Top row keys T1 - T15.
+ * on frostflow_kb keyboard Row Column is customization
+ * need define row col to mapping matrix layout.
+ */
+__override const struct key {
+	uint8_t row;
+	uint8_t col;
+} vivaldi_keys[] = {
+	{ .row = 4, .col = 2 }, /* T1 */
+	{ .row = 3, .col = 2 }, /* T2 */
+	{ .row = 2, .col = 2 }, /* T3 */
+	{ .row = 1, .col = 2 }, /* T4 */
+	{ .row = 4, .col = 4 }, /* T5 */
+	{ .row = 3, .col = 4 }, /* T6 */
+	{ .row = 2, .col = 4 }, /* T7 */
+	{ .row = 2, .col = 9 }, /* T8 */
+	{ .row = 1, .col = 9 }, /* T9 */
+	{ .row = 1, .col = 4 }, /* T10 */
+	{ .row = 0, .col = 4 }, /* T11 */
+	{ .row = 1, .col = 5 }, /* T12 */
+	{ .row = 3, .col = 5 }, /* T13 */
+	{ .row = 2, .col = 1 }, /* T14 */
+	{ .row = 0, .col = 1 }, /* T15 */
+};
+BUILD_ASSERT(ARRAY_SIZE(vivaldi_keys) == MAX_TOP_ROW_KEYS);
diff --git a/zephyr/program/skyrim/frostflow/src/keyboard_customization.c b/zephyr/program/skyrim/frostflow/src/keyboard_customization.c
new file mode 100644
index 0000000000..b702fca258
--- /dev/null
+++ b/zephyr/program/skyrim/frostflow/src/keyboard_customization.c
@@ -0,0 +1,85 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "gpio.h"
+#include "keyboard_customization.h"
+#include "keyboard_protocol.h"
+#include "keyboard_raw.h"
+
+#include <zephyr/drivers/gpio.h>
+
+static uint16_t scancode_set2[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = {
+	{ 0x0000, 0x0000, 0x0014, 0xe01f, 0xe014, 0x0000, 0x0000, 0x0000 },
+	{ 0x001f, 0x0076, 0x0017, 0x000e, 0x001c, 0x003a, 0x000d, 0x0016 },
+	{ 0x006c, 0xe024, 0xe01d, 0xe020, 0xe038, 0xe071, 0x0026, 0x002a },
+	{ 0x0032, 0x0034, 0x002c, 0x002e, 0x002b, 0x0029, 0x0025, 0x002d },
+	{ 0x0078, 0xe032, 0xe035, 0xe02c, 0xe02d, 0x0041, 0x001e, 0x001d },
+	{ 0x0051, 0x0007, 0x005b, 0x000f, 0x0042, 0x0022, 0x003e, 0x0043 },
+	{ 0x0031, 0x0033, 0x0035, 0x0036, 0x003b, 0x001b, 0x003d, 0x003c },
+	{ 0x0000, 0x0012, 0x0061, 0x0000, 0x0000, 0x0000, 0x0000, 0x0059 },
+	{ 0x0055, 0x0052, 0x0054, 0x004e, 0x004c, 0x0024, 0x0044, 0x004d },
+	{ 0x0045, 0xe021, 0xe023, 0x002f, 0x004b, 0x0049, 0x0046, 0x001a },
+	{ 0xe011, 0x0000, 0x006a, 0x0000, 0x005d, 0x0000, 0x0011, 0x0000 },
+	{ 0xe07a, 0x005d, 0xe075, 0x006b, 0x005a, 0xe072, 0x004a, 0x0066 },
+	{ 0xe06b, 0xe074, 0xe069, 0x0067, 0xe06c, 0x0064, 0x0015, 0xe07d },
+	{ 0x0073, 0x007c, 0x007b, 0x0074, 0x0071, 0xe04a, 0x0070, 0x0021 },
+	{ 0x0023, 0xe05a, 0x0075, 0x0079, 0x007a, 0x0072, 0x007d, 0x0069 },
+};
+
+uint16_t get_scancode_set2(uint8_t row, uint8_t col)
+{
+	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS)
+		return scancode_set2[col][row];
+	return 0;
+}
+
+void set_scancode_set2(uint8_t row, uint8_t col, uint16_t val)
+{
+	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS)
+		scancode_set2[col][row] = val;
+}
+
+#ifdef CONFIG_KEYBOARD_DEBUG
+static uint8_t keycap_label[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = {
+	{ 'c', KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO },
+	{ KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO },
+	{ 'q', KLLI_UNKNO, KLLI_UNKNO, KLLI_TAB, '`', '1', KLLI_UNKNO, 'a' },
+	{ KLLI_R_ALT, KLLI_L_ALT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO },
+	{ KLLI_UNKNO, KLLI_SPACE, 'e', KLLI_F4, KLLI_SEARC, '3', KLLI_F3,
+	  KLLI_UNKNO },
+	{ 'x', 'z', KLLI_F2, KLLI_F1, 's', '2', 'w', KLLI_ESC },
+	{ 'v', 'b', 'g', 't', '5', '4', 'r', 'f' },
+	{ 'm', 'n', 'h', 'y', '6', '7', 'u', 'j' },
+	{ '.', KLLI_DOWN, '\\', 'o', KLLI_F10, '9', KLLI_UNKNO, 'l' },
+	{ KLLI_R_SHT, KLLI_L_SHT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO },
+	{ ',', KLLI_UNKNO, KLLI_F7, KLLI_F6, KLLI_F5, '8', 'i', 'k' },
+	{ KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_F9, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_LEFT, KLLI_UNKNO },
+	{ KLLI_R_CTR, KLLI_L_CTR, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO },
+	{ '/', KLLI_UP, '-', KLLI_UNKNO, '0', 'p', '[', ';' },
+	{ '\'', KLLI_ENTER, KLLI_UNKNO, KLLI_UNKNO, '=', KLLI_B_SPC, ']', 'd' },
+	{ KLLI_UNKNO, KLLI_F8, KLLI_RIGHT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO },
+};
+
+uint8_t get_keycap_label(uint8_t row, uint8_t col)
+{
+	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS)
+		return keycap_label[col][row];
+	return KLLI_UNKNO;
+}
+
+void set_keycap_label(uint8_t row, uint8_t col, uint8_t val)
+{
+	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS)
+		keycap_label[col][row] = val;
+}
+#endif
diff --git a/zephyr/program/skyrim/frostflow/src/ppc_config.c b/zephyr/program/skyrim/frostflow/src/ppc_config.c
new file mode 100644
index 0000000000..3f5658f3a2
--- /dev/null
+++ b/zephyr/program/skyrim/frostflow/src/ppc_config.c
@@ -0,0 +1,49 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Frostflow board-specific PPC code */
+
+#include "driver/ppc/aoz1380_public.h"
+#include "driver/ppc/nx20p348x.h"
+#include "usbc_ppc.h"
+
+#include <zephyr/drivers/gpio.h>
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/*
+ * In the AOZ1380 PPC, there are no programmable features.  We use
+ * the attached NCT3807 to control a GPIO to indicate 1A5 or 3A0
+ * current limits.
+ */
+int board_aoz1380_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	int rv = EC_SUCCESS;
+
+	if (port != 0)
+		return EC_ERROR_INVAL;
+
+	rv = gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(ioex_usb_c0_ilim_3a_en),
+			     (rp == TYPEC_RP_3A0) ? 1 : 0);
+
+	return rv;
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		aoz1380_interrupt(0);
+		break;
+
+	case GPIO_USB_C1_PPC_INT_ODL:
+		nx20p348x_interrupt(1);
+		break;
+
+	default:
+		break;
+	}
+}
diff --git a/zephyr/program/skyrim/frostflow/src/thermal.c b/zephyr/program/skyrim/frostflow/src/thermal.c
new file mode 100644
index 0000000000..101823cc26
--- /dev/null
+++ b/zephyr/program/skyrim/frostflow/src/thermal.c
@@ -0,0 +1,109 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "fan.h"
+#include "tablet_mode.h"
+#include "temp_sensor/temp_sensor.h"
+#include "thermal.h"
+#include "util.h"
+
+#define TEMP_MEM TEMP_SENSOR_ID(DT_NODELABEL(temp_sensor_memory))
+
+struct fan_step {
+	/*
+	 * Sensor 0~4 trigger point, set -1 if we're not using this
+	 * sensor to determine fan speed.
+	 */
+	int on[TEMP_SENSOR_COUNT];
+	/*
+	 * Sensor 0~4 release point, set -1 if we're not using this
+	 * sensor to determine fan speed.
+	 */
+	int off[TEMP_SENSOR_COUNT];
+	/* Fan rpm */
+	uint16_t rpm[FAN_CH_COUNT];
+};
+
+#define FAN_TABLE_ENTRY(nd)                     \
+	{                                       \
+		.on = DT_PROP(nd, temp_on),     \
+		.off = DT_PROP(nd, temp_off),   \
+		.rpm = DT_PROP(nd, rpm_target), \
+	},
+
+static const struct fan_step fan_table_clamshell[] = { DT_FOREACH_CHILD(
+	DT_NODELABEL(fan_steps_clamshell), FAN_TABLE_ENTRY) };
+
+static const struct fan_step fan_table_tablet[] = { DT_FOREACH_CHILD(
+	DT_NODELABEL(fan_steps_tablet), FAN_TABLE_ENTRY) };
+
+static const struct fan_step *fan_step_table;
+#define NUM_FAN_LEVELS ARRAY_SIZE(fan_table_clamshell)
+
+BUILD_ASSERT(ARRAY_SIZE(fan_table_clamshell) == ARRAY_SIZE(fan_table_tablet));
+
+int fan_table_to_rpm(int fan, int *temp)
+{
+	/* current fan level */
+	static int current_level;
+	/* previous sensor temperature */
+	static int prev_tmp[TEMP_SENSOR_COUNT];
+	int i;
+
+	if (tablet_get_mode())
+		fan_step_table = fan_table_tablet;
+	else
+		fan_step_table = fan_table_clamshell;
+
+	/*
+	 * Compare the current and previous temperature, we have
+	 * the three paths :
+	 *  1. decreasing path. (check the release point)
+	 *  2. increasing path. (check the trigger point)
+	 *  3. invariant path. (return the current RPM)
+	 */
+
+	if (temp[TEMP_MEM] < prev_tmp[TEMP_MEM]) {
+		for (i = current_level; i > 0; i--) {
+			if (temp[TEMP_MEM] <= fan_step_table[i].off[TEMP_MEM])
+				current_level = i - 1;
+			else
+				break;
+		}
+	} else if (temp[TEMP_MEM] > prev_tmp[TEMP_MEM]) {
+		for (i = current_level; i < NUM_FAN_LEVELS; i++) {
+			if (temp[TEMP_MEM] >= fan_step_table[i].on[TEMP_MEM])
+				current_level = i;
+			else
+				break;
+		}
+	}
+
+	if (current_level < 0)
+		current_level = 0;
+
+	if (current_level >= NUM_FAN_LEVELS)
+		current_level = NUM_FAN_LEVELS - 1;
+
+	for (i = 0; i < TEMP_SENSOR_COUNT; ++i)
+		prev_tmp[i] = temp[i];
+
+	return fan_step_table[current_level].rpm[fan];
+}
+
+void board_override_fan_control(int fan, int *temp)
+{
+	/*
+	 * In common/fan.c pwm_fan_stop() will turn off fan
+	 * when chipset suspend or shutdown.
+	 */
+	if (chipset_in_state(CHIPSET_STATE_ON)) {
+		fan_set_rpm_mode(fan, 1);
+		fan_set_rpm_target(fan, fan_table_to_rpm(fan, temp));
+	}
+}
diff --git a/zephyr/program/skyrim/frostflow/src/usb_mux_config.c b/zephyr/program/skyrim/frostflow/src/usb_mux_config.c
new file mode 100644
index 0000000000..c7c03bc8cb
--- /dev/null
+++ b/zephyr/program/skyrim/frostflow/src/usb_mux_config.c
@@ -0,0 +1,201 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Frostflow board-specific USB-C mux configuration */
+
+#include "ap_power/ap_power.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "driver/retimer/ps8811.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "i2c/i2c.h"
+#include "ioexpander.h"
+#include "timer.h"
+#include "usb_mux.h"
+#include "usbc/usb_muxes.h"
+#include "util.h"
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+struct ps8811_reg_val {
+	uint8_t reg;
+	uint16_t val;
+};
+
+/*
+ * USB C0 (general) and C1 (just ps8815 DB) use IOEX pins to
+ * indicate flipped polarity to a protection switch.
+ */
+test_export_static int ioex_set_flip(int port, mux_state_t mux_state)
+{
+	if (port == 0) {
+		if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
+			gpio_pin_set_dt(
+				GPIO_DT_FROM_NODELABEL(ioex_usb_c0_sbu_flip),
+				1);
+		else
+			gpio_pin_set_dt(
+				GPIO_DT_FROM_NODELABEL(ioex_usb_c0_sbu_flip),
+				0);
+	} else {
+		if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
+			gpio_pin_set_dt(
+				GPIO_DT_FROM_NODELABEL(ioex_usb_c1_sbu_flip),
+				1);
+		else
+			gpio_pin_set_dt(
+				GPIO_DT_FROM_NODELABEL(ioex_usb_c1_sbu_flip),
+				0);
+	}
+
+	return EC_SUCCESS;
+}
+
+int board_c0_amd_fp6_mux_set(const struct usb_mux *me, mux_state_t mux_state)
+{
+	/* Set the SBU polarity mux */
+	RETURN_ERROR(ioex_set_flip(me->usb_port, mux_state));
+
+	return EC_SUCCESS;
+}
+
+int board_c1_ps8818_mux_set(const struct usb_mux *me, mux_state_t mux_state)
+{
+	CPRINTSUSB("C1: PS8818 mux using default tuning");
+
+	/* Once a DP connection is established, we need to set IN_HPD */
+	if (mux_state & USB_PD_MUX_DP_ENABLED)
+		ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 1);
+	else
+		ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 0);
+
+	return 0;
+}
+
+const static struct ps8811_reg_val equalizer_wwan_table[] = {
+	{
+		/* Set channel A EQ setting */
+		.reg = PS8811_REG1_USB_AEQ_LEVEL,
+		.val = (PS8811_AEQ_I2C_LEVEL_UP_13DB
+			<< PS8811_AEQ_I2C_LEVEL_UP_SHIFT) |
+		       (PS8811_AEQ_PIN_LEVEL_UP_18DB
+			<< PS8811_AEQ_PIN_LEVEL_UP_SHIFT),
+	},
+	{
+		/* Set ADE pin setting */
+		.reg = PS8811_REG1_USB_ADE_CONFIG,
+		.val = (PS8811_ADE_PIN_MID_LEVEL_3DB
+			<< PS8811_ADE_PIN_MID_LEVEL_SHIFT) |
+		       PS8811_AEQ_CONFIG_REG_ENABLE,
+	},
+	{
+		/* Set channel B EQ setting */
+		.reg = PS8811_REG1_USB_BEQ_LEVEL,
+		.val = (PS8811_BEQ_I2C_LEVEL_UP_10P5DB
+			<< PS8811_BEQ_I2C_LEVEL_UP_SHIFT) |
+		       (PS8811_BEQ_PIN_LEVEL_UP_18DB
+			<< PS8811_BEQ_PIN_LEVEL_UP_SHIFT),
+	},
+	{
+		/* Set BDE pin setting */
+		.reg = PS8811_REG1_USB_BDE_CONFIG,
+		.val = (PS8811_BDE_PIN_MID_LEVEL_3DB
+			<< PS8811_BDE_PIN_MID_LEVEL_SHIFT) |
+		       PS8811_BEQ_CONFIG_REG_ENABLE,
+	},
+};
+
+#define NUM_EQ_WWAN_ARRAY ARRAY_SIZE(equalizer_wwan_table)
+
+const static struct ps8811_reg_val equalizer_wlan_table[] = {
+	{
+		/* Set 50ohm adjust for B channel */
+		.reg = PS8811_REG1_50OHM_ADJUST_CHAN_B,
+		.val = (PS8811_50OHM_ADJUST_CHAN_B_MINUS_14PCT
+			<< PS8811_50OHM_ADJUST_CHAN_B_SHIFT),
+	},
+};
+
+#define NUM_EQ_WLAN_ARRAY ARRAY_SIZE(equalizer_wlan_table)
+/* USB-A ports */
+enum usba_port { USBA_PORT_A1, USBA_PORT_COUNT };
+const struct usb_mux usba_ps8811[] = {
+	[USBA_PORT_A1] = {
+		.usb_port = USBA_PORT_A1,
+		.i2c_port = I2C_PORT_NODELABEL(i2c1_0),
+		.i2c_addr_flags = PS8811_I2C_ADDR_FLAGS3,
+	},
+};
+
+static int usba_retimer_init(int port)
+{
+	int rv;
+	int val;
+	int i;
+	const struct usb_mux *me = &usba_ps8811[port];
+
+	rv = ps8811_i2c_read(me, PS8811_REG_PAGE1, PS8811_REG1_USB_BEQ_LEVEL,
+			     &val);
+
+	if (rv) {
+		CPRINTSUSB("A1: PS8811 retimer response fail!");
+		return rv;
+	}
+	CPRINTSUSB("A1: PS8811 retimer detected");
+
+	if (chipset_in_state(CHIPSET_STATE_ON)) {
+		/* Set channel A output swing */
+		rv = ps8811_i2c_field_update(me, PS8811_REG_PAGE1,
+					     PS8811_REG1_USB_CHAN_A_SWING,
+					     PS8811_CHAN_A_SWING_MASK,
+					     0x3 << PS8811_CHAN_A_SWING_SHIFT);
+
+		for (i = 0; i < NUM_EQ_WWAN_ARRAY; i++)
+			rv |= ps8811_i2c_write(me, PS8811_REG_PAGE1,
+					       equalizer_wwan_table[i].reg,
+					       equalizer_wwan_table[i].val);
+		for (i = 0; i < NUM_EQ_WLAN_ARRAY; i++)
+			rv |= ps8811_i2c_write(me, PS8811_REG_PAGE1,
+					       equalizer_wlan_table[i].reg,
+					       equalizer_wlan_table[i].val);
+	}
+	return rv;
+}
+
+void baseboard_a1_retimer_setup(void)
+{
+	int i;
+
+	for (i = 0; i < USBA_PORT_COUNT; ++i)
+		usba_retimer_init(i);
+}
+DECLARE_DEFERRED(baseboard_a1_retimer_setup);
+
+test_export_static void board_resume_change(struct ap_power_ev_callback *cb,
+					    struct ap_power_ev_data data)
+{
+	switch (data.event) {
+	default:
+		return;
+
+	case AP_POWER_STARTUP:
+		/* Any retimer tuning can be done after the retimer turns on */
+		hook_call_deferred(&baseboard_a1_retimer_setup_data, 20 * MSEC);
+		break;
+	}
+}
+
+void board_callback_init(void)
+{
+	static struct ap_power_ev_callback cb;
+
+	/* Setup a resume callback */
+	ap_power_ev_init_callback(&cb, board_resume_change, AP_POWER_STARTUP);
+	ap_power_ev_add_callback(&cb);
+}
+DECLARE_HOOK(HOOK_INIT, board_callback_init, HOOK_PRIO_DEFAULT);
diff --git a/zephyr/program/skyrim/gpio.dtsi b/zephyr/program/skyrim/gpio.dtsi
new file mode 100644
index 0000000000..ef78e9034a
--- /dev/null
+++ b/zephyr/program/skyrim/gpio.dtsi
@@ -0,0 +1,375 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	aliases {
+		gpio-wp = &gpio_wp;
+		gpio-cbi-wp = &gpio_cbi_wp;
+		gpio-kbd-kso2 = &gpio_ec_kso_02_inv;
+	};
+
+	/* GPIOs shared by all boards */
+	named-gpios {
+		compatible = "named-gpios";
+
+		ccd_mode_odl {
+			gpios = <&gpioc 6 GPIO_ODR_HIGH>;
+		};
+		ec_gsc_packet_mode {
+			gpios = <&gpiob 1 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_PACKET_MODE_EN";
+		};
+		gpio_mech_pwr_btn_odl: mech_pwr_btn_odl {
+			gpios = <&gpiod 2 GPIO_INPUT>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		gpio_slp_s3_l: slp_s3_l {
+			gpios = <&gpio6 1 GPIO_INPUT>;
+			enum-name = "GPIO_PCH_SLP_S3_L";
+			alias = "GPIO_PCH_SLP_S0_L";
+		};
+		gpio_slp_s5_l: slp_s5_l {
+			gpios = <&gpio7 2 GPIO_INPUT>;
+			enum-name = "GPIO_PCH_SLP_S5_L";
+		};
+		gpio_pg_pwr_s5: pg_pwr_s5 {
+			gpios = <&gpioc 0 GPIO_INPUT>;
+			enum-name = "GPIO_S5_PGOOD";
+		};
+		gpio_s0_pgood: pg_pcore_s0_r_od {
+			gpios = <&gpiob 6 GPIO_INPUT>;
+			enum-name = "GPIO_S0_PGOOD";
+		};
+		gpio_acok_od: acok_od {
+			gpios = <&gpio0 0 GPIO_INPUT>;
+			enum-name = "GPIO_AC_PRESENT";
+		};
+		gpio_en_pwr_s5: en_pwr_s5 {
+			gpios = <&gpiob 7 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_EN_PWR_A";
+		};
+		gpio_en_pwr_s0_r: en_pwr_s0_r {
+			gpios = <&gpiof 1 GPIO_OUTPUT_LOW>;
+		};
+		gpio_en_pwr_pcore_s0_r: en_pwr_pcore_s0_r {
+			gpios = <&gpioe 1 GPIO_OUTPUT_LOW>;
+		};
+		ec_sys_rst_l {
+			gpios = <&gpio7 6 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_SYS_RESET_L";
+		};
+		gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l {
+			gpios = <&gpioc 5 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_PCH_RSMRST_L";
+		};
+		gpio_ec_pch_wake_odl: ec_soc_wake_l {
+			gpios = <&gpio0 3 GPIO_OUTPUT_HIGH>;
+		};
+		gpio_prochot_odl: prochot_odl {
+			gpios = <&gpiod 5 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_CPU_PROCHOT";
+		};
+		soc_alert_ec_l {
+			gpios = <&gpioe 2 GPIO_INPUT>;
+		};
+		gpio_usb_c0_tcpc_int_odl: usb_c0_tcpc_int_odl {
+			gpios = <&gpioe 0 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_USB_C0_TCPC_INT_ODL";
+		};
+		gpio_usb_c1_tcpc_int_odl: usb_c1_tcpc_int_odl {
+			gpios = <&gpioc 7 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_USB_C1_TCPC_INT_ODL";
+		};
+		gpio_usb_c0_ppc_int_odl: usb_c0_ppc_int_odl {
+			gpios = <&gpio7 5 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C0_PPC_INT_ODL";
+		};
+		gpio_usb_c1_ppc_int_odl: usb_c1_ppc_int_odl {
+			gpios = <&gpiod 4 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C1_PPC_INT_ODL";
+		};
+		gpio_usb_c0_bc12_int_odl: usb_c0_bc12_int_odl {
+			gpios = <&gpioa 4 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_USB_C0_BC12_INT_ODL";
+		};
+		gpio_usb_c1_bc12_int_odl: usb_c1_bc12_int_odl {
+			gpios = <&gpio9 6 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_USB_C1_BC12_INT_ODL";
+		};
+		gpio_usb_c0_tcpc_rst_l: usb_c0_tcpc_rst_l {
+			gpios = <&gpio3 4 (GPIO_OUTPUT_HIGH | GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_USB_C0_TCPC_RST_L";
+		};
+		gpio_usb_c1_tcpc_rst_l: usb_c1_tcpc_rst_l {
+			gpios = <&gpio3 7 (GPIO_OUTPUT_HIGH | GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_USB_C1_TCPC_RST_L";
+		};
+		usb_c0_hpd {
+			gpios = <&gpiof 5 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_USB_C0_DP_HPD";
+		};
+		usb_c1_hpd {
+			gpios = <&gpiof 4 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_USB_C1_DP_HPD";
+		};
+		gpio_lid_open: lid_open {
+			gpios = <&gpio0 2 GPIO_INPUT>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+		gpio_ec_batt_pres_odl: ec_batt_pres_odl {
+			gpios = <&gpio9 4 GPIO_INPUT>;
+			enum-name = "GPIO_BATT_PRES_ODL";
+		};
+		gpio_ec_disable_disp_bl: ec_disable_disp_bl {
+			gpios = <&gpioa 6 GPIO_OUTPUT_HIGH>;
+			enum-name = "GPIO_ENABLE_BACKLIGHT_L";
+		};
+		gpio_usb_fault_odl: usb_fault_odl {
+			gpios = <&gpio5 0 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>;
+		};
+		gpio_en_pwr_s3: en_pwr_s3 {
+			gpios = <&gpio7 4 GPIO_OUTPUT_LOW>;
+		};
+		gpio_pg_groupc_s0_od: pg_groupc_s0_od {
+			gpios = <&gpiof 0 GPIO_INPUT>;
+		};
+		gpio_ec_i2c_usbc_pd_int: ec_i2c_usbc_pd_int {
+			gpios = <&gpioa 3 GPIO_INPUT>;
+		};
+		gpio_soc_thermtrip_odl: soc_thermtrip_odl {
+			gpios = <&gpio9 5 GPIO_INPUT>;
+		};
+		gpio_hub_rst: hub_rst {
+			gpios = <&gpio6 6 GPIO_OUTPUT_HIGH>;
+		};
+		ec_soc_int_l {
+			gpios = <&gpioa 1 GPIO_OUTPUT_HIGH>;
+			enum-name = "GPIO_EC_INT_L";
+		};
+		gpio_ec_soc_pwr_good: ec_soc_pwr_good {
+			gpios = <&gpiod 3 GPIO_OUTPUT_LOW>;
+		};
+		gpio_pcore_ocp_r_l: pcore_ocp_r_l {
+			gpios = <&gpioa 5 GPIO_INPUT>;
+		};
+		gpio_usb_hub_fault_q_odl: usb_hub_fault_q_odl {
+			gpios = <&gpioe 5 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_pg_lpddr5_s3_od: pg_lpddr5_s3_od {
+			gpios = <&gpio7 3 GPIO_INPUT>;
+		};
+		gpio_lid_accel_int_l: 3axis_int_l {
+			gpios = <&gpioa 2 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_ec_soc_pwr_btn_l: ec_soc_pwr_btn_l {
+			gpios = <&gpioa 7 GPIO_OUTPUT_HIGH>;
+			enum-name = "GPIO_PCH_PWRBTN_L";
+		};
+		gpio_volup_btn_odl: volup_btn_odl {
+			gpios = <&gpio6 7 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_UP_L";
+		};
+		gpio_voldn_btn_odl: voldn_btn_odl {
+			gpios = <&gpio7 0 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_DOWN_L";
+		};
+		ec_sc_rst {
+			gpios = <&gpiob 0 GPIO_OUTPUT_LOW>;
+		};
+		gpio_cbi_wp: ec_cbi_wp {
+			gpios = <&gpio8 1 GPIO_OUTPUT_LOW>;
+		};
+		gpio_wp: ec_wp_l {
+			gpios = <&gpiod 7 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_pg_lpddr5_s0_od: pg_lpddr5_s0_od {
+			gpios = <&gpio6 0 GPIO_INPUT>;
+		};
+		ec_espi_rst_l {
+			gpios = <&gpio5 4 GPIO_PULL_DOWN>;
+		};
+		gpio_accel_gyro_int_l: accel_gyro_int_l {
+			gpios = <&gpioa 0 GPIO_INPUT>;
+		};
+		/* unimplemented GPIOs */
+		entering-rw {
+			enum-name = "GPIO_ENTERING_RW";
+		};
+		pch-sys-prwok {
+			enum-name = "GPIO_PCH_SYS_PWROK";
+		};
+		ec_i2c_usb_a0_c0_scl {
+			gpios = <&gpiob 5 GPIO_INPUT>;
+		};
+		ec_i2c_usb_a0_c0_sda {
+			gpios = <&gpiob 4 GPIO_INPUT>;
+		};
+		ec_i2c_usb_a1_c1_scl {
+			gpios = <&gpio9 0 GPIO_INPUT>;
+		};
+		ec_i2c_usb_a1_c1_sda {
+			gpios = <&gpio8 7 GPIO_INPUT>;
+		};
+		ec_i2c_batt_scl {
+			gpios = <&gpio9 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		ec_i2c_batt_sda {
+			gpios = <&gpio9 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		ec_i2c_usbc_mux_scl {
+			gpios = <&gpiod 1 GPIO_INPUT>;
+		};
+		ec_i2c_usbc_mux_sda {
+			gpios = <&gpiod 0 GPIO_INPUT>;
+		};
+		ec_i2c_power_scl {
+			gpios = <&gpiof 3 GPIO_INPUT>;
+		};
+		ec_i2c_power_sda {
+			gpios = <&gpiof 2 GPIO_INPUT>;
+		};
+		ec_i2c_cbi_scl {
+			gpios = <&gpio3 3 GPIO_INPUT>;
+		};
+		ec_i2c_cbi_sda {
+			gpios = <&gpio3 6 GPIO_INPUT>;
+		};
+		ec_i2c_sensor_scl {
+			gpios = <&gpioe 4 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		ec_i2c_sensor_sda {
+			gpios = <&gpioe 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		ec_i2c_soc_sic {
+			gpios = <&gpiob 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		ec_i2c_soc_sid {
+			gpios = <&gpiob 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		en_kb_bl {
+			gpios = <&gpio9 7 GPIO_OUTPUT_HIGH>;
+			enum-name = "GPIO_EN_KEYBOARD_BACKLIGHT";
+		};
+		gpio_ec_kso_02_inv: ec_kso_02_inv {
+			gpios = <&gpio1 7 (GPIO_OUTPUT_LOW | GPIO_ACTIVE_LOW)>;
+		};
+		tablet_mode_l {
+			gpios = <&gpioc 1 GPIO_INPUT>;
+			enum-name = "GPIO_TABLET_MODE_L";
+		};
+		ec_flprg2 {
+			gpios = <&gpio8 6 GPIO_INPUT_PULL_UP>;
+		};
+
+		usb_c0_tcpc_fastsw_ctl_en {
+			gpios = <&ioex_c0_port0 4 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C0_TCPC_FASTSW_CTL_EN";
+		};
+		usb_c0_ppc_en_l {
+			gpios = <&ioex_c0_port1 0 GPIO_OUTPUT_LOW>;
+		};
+		ioex_usb_c0_ilim_3a_en: usb_c0_ppc_ilim_3a_en {
+			gpios = <&ioex_c0_port1 1 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C0_PPC_ILIM_3A_EN";
+		};
+		ioex_usb_c0_sbu_fault_odl: usb_c0_sbu_fault_odl {
+			gpios = <&ioex_c0_port1 2 GPIO_INPUT>;
+		};
+		ioex_en_pp5000_usb_a0_vbus: en_pp5000_usb_a0_vbus {
+			gpios = <&ioex_c0_port1 5 GPIO_OUTPUT_LOW>;
+		};
+		ioex_usb_a0_fault_odl: usb_a0_fault_odl {
+			gpios = <&ioex_c0_port1 6 GPIO_INPUT>;
+		};
+		ioex_usb_c0_sbu_flip: usb_c0_sbu_flip {
+			gpios = <&ioex_c0_port1 7 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C0_SBU_FLIP";
+		};
+
+		usb_a1_retimer_en {
+			gpios = <&ioex_c1_port0 0 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_A1_RETIMER_EN";
+		};
+		usb_a1_retimer_rst {
+			gpios = <&ioex_c1_port0 1 GPIO_OUTPUT_LOW>;
+		};
+		usb_c1_in_hpd {
+			gpios = <&ioex_c1_port0 3 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C1_HPD_IN_DB";
+		};
+		usb_c1_tcpc_fastsw_ctl_en {
+			gpios = <&ioex_c1_port0 4 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C1_TCPC_FASTSW_CTL_EN";
+		};
+		usb_c1_ppc_en_l {
+			gpios = <&ioex_c1_port1 0 GPIO_OUTPUT_LOW>;
+		};
+		usb_c1_ppc_ilim_3a_en {
+			gpios = <&ioex_c1_port1 1 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C1_PPC_ILIM_3A_EN";
+		};
+		ioex_usb_c1_sbu_fault_odl: usb_c1_sbu_fault_odl {
+			gpios = <&ioex_c1_port1 2 GPIO_INPUT>;
+			enum-name = "IOEX_USB_C1_FAULT_ODL";
+		};
+		ioex_en_pp5000_usb_a1_vbus: en_pp5000_usb_a1_vbus {
+			gpios = <&ioex_c1_port1 5 GPIO_OUTPUT_LOW>;
+		};
+		ioex_usb_a1_fault_db_odl: usb_a1_fault_db_odl {
+			gpios = <&ioex_c1_port1 6 GPIO_INPUT>;
+		};
+		ioex_usb_c1_sbu_flip: usb_c1_sbu_flip {
+			gpios = <&ioex_c1_port1 7 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C1_SBU_FLIP";
+		};
+
+		/* STB dumping GPIOs */
+		gpio_ec_sfh_int_h: ec_sfh_int_h {
+			gpios = <&gpio9 3 GPIO_OUTPUT_LOW>;
+		};
+		gpio_sfh_ec_int_h: sfh_ec_int_h {
+			gpios = <&gpio5 6 GPIO_INPUT>;
+		};
+	};
+
+	usba-port-enable-list {
+		compatible = "cros-ec,usba-port-enable-pins";
+		enable-pins = <&ioex_en_pp5000_usb_a0_vbus
+			       &ioex_en_pp5000_usb_a1_vbus>;
+	};
+};
+
+/* PSL input pads*/
+&psl_in1_gpd2 {
+	/* MECH_PWR_BTN_ODL */
+	psl-in-mode = "edge";
+	psl-in-pol = "low-falling";
+};
+
+&psl_in2_gp00 {
+	/* ACOK_OD */
+	psl-in-mode = "edge";
+	psl-in-pol = "high-rising";
+};
+
+&psl_in4_gp02 {
+	/* LID_OPEN */
+	psl-in-mode = "edge";
+	psl-in-pol = "high-rising";
+};
+
+/* Power domain device controlled by PSL (Power Switch Logic) IO pads */
+&power_ctrl_psl {
+	status = "okay";
+	pinctrl-names = "sleep";
+	pinctrl-0 = <&psl_in1_gpd2 &psl_in2_gp00 &psl_in4_gp02>;
+};
+
+/* host interface */
+&espi0 {
+	status = "okay";
+	pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/skyrim/i2c.dtsi b/zephyr/program/skyrim/i2c.dtsi
new file mode 100644
index 0000000000..6bffc60e65
--- /dev/null
+++ b/zephyr/program/skyrim/i2c.dtsi
@@ -0,0 +1,360 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+ #include <dt-bindings/usb_pd_tcpm.h>
+ #include <dt-bindings/usbc_mux.h>
+
+/ {
+	aliases {
+		i2c-0 = &i2c0_0;
+		i2c-1 = &i2c1_0;
+		i2c-2 = &i2c2_0;
+		i2c-3 = &i2c3_0;
+		i2c-4 = &i2c4_1;
+		i2c-5 = &i2c5_0;
+		i2c-7 = &i2c7_0;
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		i2c_tcpc0: tcpc0 {
+			i2c-port = <&i2c0_0>;
+			enum-names = "I2C_PORT_TCPC0";
+		};
+
+		i2c_tcpc1: tcpc1 {
+			i2c-port = <&i2c1_0>;
+			enum-names = "I2C_PORT_TCPC1";
+		};
+
+		battery {
+			i2c-port = <&i2c2_0>;
+			remote-port = <0>;
+			enum-names = "I2C_PORT_BATTERY";
+		};
+
+		usb-mux {
+			i2c-port = <&i2c3_0>;
+			enum-names = "I2C_PORT_USB_MUX";
+		};
+
+		i2c_charger: charger {
+			i2c-port = <&i2c4_1>;
+			enum-names = "I2C_PORT_CHARGER";
+		};
+
+		eeprom {
+			i2c-port = <&i2c5_0>;
+			enum-names = "I2C_PORT_EEPROM";
+		};
+
+		i2c_sensor: sensor {
+			i2c-port = <&i2c6_1>;
+			enum-names = "I2C_PORT_SENSOR";
+		};
+
+		i2c_soc_thermal: soc-thermal {
+			i2c-port = <&i2c7_0>;
+			enum-names = "I2C_PORT_THERMAL_AP";
+		};
+	};
+
+
+};
+
+&i2c0_0 {
+	status = "okay";
+	label = "I2C_TCPC0";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>;
+	pinctrl-names = "default";
+
+	bc12_port0: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+		irq = <&int_usb_c0_bc12>;
+	};
+
+	tcpc_port0: nct38xx@70 {
+		compatible = "nuvoton,nct38xx";
+		reg = <0x70>;
+		gpio-dev = <&nct3807_C0>;
+		tcpc-flags = <(TCPC_FLAGS_TCPCI_REV2_0)>;
+		/* a duplicate of the <&gpio_usb_c0_tcpc_int_odl> node in
+		 * "named-gpios". This is the Zephyr preferred style,
+		 * the "named-gpios" node will be dealt with at a later date.
+		 */
+		irq-gpios = <&gpioe 0 GPIO_ACTIVE_LOW>;
+		/* a duplicate of the <&gpio_usb_c0_tcpc_rst_l> node in
+		 * "named-gpios". This is the Zephyr preferred style,
+		 * the "named-gpios" node will be dealt with at a later date.
+		 */
+		rst-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
+	};
+
+	nct3807_C0: nct3807_C0@70 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nuvoton,nct38xx-gpio";
+		reg = <0x70>;
+		label = "NCT3807_C0";
+
+		ioex_c0_port0: gpio@0 {
+			compatible = "nuvoton,nct38xx-gpio-port";
+			reg = <0x0>;
+			label = "NCT3807_C0_GPIO0";
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <8>;
+			pin_mask = <0xff>;
+			pinmux_mask = <0xf7>;
+		};
+		ioex_c0_port1: gpio@1 {
+			compatible = "nuvoton,nct38xx-gpio-port";
+			reg = <0x1>;
+			label = "NCT3807_C0_GPIO1";
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <8>;
+			pin_mask = <0xff>;
+		};
+	};
+
+	nct3808_alert_0 {
+		compatible = "nuvoton,nct38xx-gpio-alert";
+		irq-gpios = <&gpioe 0 GPIO_ACTIVE_LOW>;
+		nct38xx-dev = <&nct3807_C0>;
+		label = "NCT3807_ALERT_0";
+	};
+
+	anx7483_port0: anx7483@3e {
+		compatible = "analogix,anx7483";
+		reg = <0x3e>;
+		board-set = "board_anx7483_c0_mux_set";
+		flags = <USB_MUX_FLAG_RESETS_IN_G3>;
+	};
+
+	ppc_port0: nx20p348x@71 {
+		compatible = "nxp,nx20p348x";
+		status = "okay";
+		reg = <0x71>;
+	};
+};
+
+&i2c_ctrl0 {
+	status = "okay";
+};
+
+&i2c1_0 {
+	status = "okay";
+	label = "I2C_TCPC1";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>;
+	pinctrl-names = "default";
+
+	bc12_port1: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+		irq = <&int_usb_c1_bc12>;
+	};
+
+	tcpc_port1: nct38xx@70 {
+		compatible = "nuvoton,nct38xx";
+		reg = <0x70>;
+		gpio-dev = <&nct3807_C1>;
+		tcpc-flags = <(TCPC_FLAGS_TCPCI_REV2_0)>;
+		/* a duplicate of the <&gpio_usb_c1_tcpc_int_odl> node in
+		 * "named-gpios". This is the Zephyr preferred style,
+		 * the "named-gpios" node will be dealt with at a later date.
+		 */
+		irq-gpios = <&gpioc 7 GPIO_ACTIVE_LOW>;
+		/* a duplicate of the <&gpio_usb_c1_tcpc_rst_l> node in
+		 * "named-gpios". This is the Zephyr preferred style,
+		 * the "named-gpios" node will be dealt with at a later date.
+		 */
+		rst-gpios = <&gpio3 7 GPIO_ACTIVE_LOW>;
+	};
+
+	nct3807_C1: nct3807_C1@70 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nuvoton,nct38xx-gpio";
+		reg = <0x70>;
+		label = "NCT3807_C1";
+
+		ioex_c1_port0: gpio@0 {
+			compatible = "nuvoton,nct38xx-gpio-port";
+			reg = <0x0>;
+			label = "NCT3807_C1_GPIO0";
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <8>;
+			pin_mask = <0xff>;
+			pinmux_mask = <0xf7>;
+		};
+		ioex_c1_port1: gpio@1 {
+			compatible = "nuvoton,nct38xx-gpio-port";
+			reg = <0x1>;
+			label = "NCT3807_C1_GPIO1";
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <8>;
+			pin_mask = <0xff>;
+		};
+	};
+
+	nct3808_alert_1 {
+		compatible = "nuvoton,nct38xx-gpio-alert";
+		irq-gpios = <&gpioc 7 GPIO_ACTIVE_LOW>;
+		nct38xx-dev = <&nct3807_C1>;
+		label = "NCT3807_ALERT_1";
+	};
+
+	anx7483_port1: anx7483@3e {
+		compatible = "analogix,anx7483";
+		reg = <0x3e>;
+		board-set = "board_anx7483_c1_mux_set";
+		flags = <USB_MUX_FLAG_RESETS_IN_G3>;
+	};
+
+	ppc_port1: nx20p348x@71 {
+		compatible = "nxp,nx20p348x";
+		status = "okay";
+		reg = <0x71>;
+	};
+
+	ps8818_port1: ps8818@28 {
+		compatible = "parade,ps8818";
+		reg = <0x28>;
+		flags = <(USB_MUX_FLAG_RESETS_IN_G3)>;
+		board-set = "board_c1_ps8818_mux_set";
+	};
+};
+
+&i2c_ctrl1 {
+	status = "okay";
+};
+
+&i2c2_0 {
+	status = "okay";
+	label = "I2C_BATTERY";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	pinctrl-0 = <&i2c2_0_sda_scl_gp91_92>;
+	pinctrl-names = "default";
+};
+
+&i2c_ctrl2 {
+	status = "okay";
+};
+
+&i2c3_0 {
+	status = "okay";
+	label = "I2C_USB_MUX";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>;
+	pinctrl-names = "default";
+
+	amd_fp6_port0: amd_fp6@5c {
+		compatible = "amd,usbc-mux-amd-fp6";
+		status = "okay";
+		reg = <0x5c>;
+	};
+	amd_fp6_port1: amd_fp6@52 {
+		compatible = "amd,usbc-mux-amd-fp6";
+		status = "okay";
+		reg = <0x52>;
+	};
+};
+
+&i2c_ctrl3 {
+	status = "okay";
+};
+
+&i2c4_1 {
+	status = "okay";
+	label = "I2C_CHARGER";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c4_1_sda_scl_gpf2_f3>;
+	pinctrl-names = "default";
+
+	charger: isl9241@9 {
+		compatible = "intersil,isl9241";
+		status = "okay";
+		reg = <0x9>;
+	};
+
+	alt_charger: isl9538@9 {
+		compatible = "intersil,isl923x";
+		status = "okay";
+		reg = <0x9>;
+	};
+};
+
+&i2c_ctrl4 {
+	status = "okay";
+};
+
+&i2c5_0 {
+	status = "okay";
+	label = "I2C_EEPROM";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c5_0_sda_scl_gp33_36>;
+	pinctrl-names = "default";
+
+	cbi_eeprom: eeprom@50 {
+		compatible = "atmel,at24";
+		reg = <0x50>;
+		size = <2048>;
+		pagesize = <16>;
+		address-width = <8>;
+		timeout = <5>;
+	};
+};
+
+&i2c_ctrl5 {
+	status = "okay";
+};
+
+&i2c6_1 {
+	status = "okay";
+	label = "I2C_SENSOR";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c6_1_sda_scl_gpe3_e4>;
+	pinctrl-names = "default";
+
+	soc_pct2075: soc-pct2075@48 {
+		compatible = "nxp,pct2075";
+		reg = <0x48>;
+	};
+
+	amb_pct2075: amb-pct2075@4f {
+		compatible = "nxp,pct2075";
+		reg = <0x4f>;
+	};
+};
+
+&i2c_ctrl6 {
+	status = "okay";
+};
+
+&i2c7_0 {
+	status = "okay";
+	label = "I2C_THERMAL_AP";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>;
+	pinctrl-names = "default";
+
+	temp_cpu: cpu@4c {
+		compatible = "amd,sb-tsi";
+		reg = <0x4c>;
+	};
+};
+
+&i2c_ctrl7 {
+	status = "okay";
+};
diff --git a/zephyr/program/skyrim/include/keyboard_customization.h b/zephyr/program/skyrim/include/keyboard_customization.h
new file mode 100644
index 0000000000..2d2a997f91
--- /dev/null
+++ b/zephyr/program/skyrim/include/keyboard_customization.h
@@ -0,0 +1,78 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Keyboard configuration */
+
+#ifndef __KEYBOARD_CUSTOMIZATION_H
+#define __KEYBOARD_CUSTOMIZATION_H
+
+/*
+ * KEYBOARD_COLS_MAX has the build time column size. It's used to allocate
+ * exact spaces for arrays. Actual keyboard scanning is done using
+ * keyboard_cols, which holds a runtime column size.
+ */
+#ifdef CONFIG_KEYBOARD_CUSTOMIZATION
+#undef KEYBOARD_COLS_MAX
+#undef KEYBOARD_ROWS
+
+#define KEYBOARD_COLS_MAX 15
+#define KEYBOARD_ROWS 8
+#endif
+
+/*
+ * WARNING: Do not directly modify it. You should call keyboard_raw_set_cols,
+ * instead. It checks whether you're eligible or not.
+ */
+extern uint8_t keyboard_cols;
+
+#define KEYBOARD_ROW_TO_MASK(r) (1 << (r))
+
+/* Columns and masks for keys we particularly care about */
+#define KEYBOARD_COL_DOWN 11
+#define KEYBOARD_ROW_DOWN 5
+#define KEYBOARD_MASK_DOWN KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_DOWN)
+#define KEYBOARD_COL_ESC 1
+#define KEYBOARD_ROW_ESC 1
+#define KEYBOARD_MASK_ESC KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_ESC)
+#define KEYBOARD_COL_KEY_H 6
+#define KEYBOARD_ROW_KEY_H 1
+#define KEYBOARD_MASK_KEY_H KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_H)
+#define KEYBOARD_COL_KEY_R 3
+#define KEYBOARD_ROW_KEY_R 7
+#define KEYBOARD_MASK_KEY_R KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_R)
+#define KEYBOARD_COL_LEFT_ALT 10
+#define KEYBOARD_ROW_LEFT_ALT 6
+#define KEYBOARD_MASK_LEFT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_ALT)
+#define KEYBOARD_COL_REFRESH 2
+#define KEYBOARD_ROW_REFRESH 3
+#define KEYBOARD_MASK_REFRESH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_REFRESH)
+#define KEYBOARD_COL_RIGHT_ALT 10
+#define KEYBOARD_ROW_RIGHT_ALT 0
+#define KEYBOARD_MASK_RIGHT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_ALT)
+#define KEYBOARD_DEFAULT_COL_VOL_UP 4
+#define KEYBOARD_DEFAULT_ROW_VOL_UP 1
+#define KEYBOARD_COL_LEFT_CTRL 0
+#define KEYBOARD_ROW_LEFT_CTRL 2
+#define KEYBOARD_MASK_LEFT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_CTRL)
+#define KEYBOARD_COL_RIGHT_CTRL 0
+#define KEYBOARD_ROW_RIGHT_CTRL 4
+#define KEYBOARD_MASK_RIGHT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_CTRL)
+#define KEYBOARD_COL_SEARCH 0
+#define KEYBOARD_ROW_SEARCH 3
+#define KEYBOARD_MASK_SEARCH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_SEARCH)
+#define KEYBOARD_COL_KEY_0 9
+#define KEYBOARD_ROW_KEY_0 0
+#define KEYBOARD_MASK_KEY_0 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_0)
+#define KEYBOARD_COL_KEY_1 1
+#define KEYBOARD_ROW_KEY_1 7
+#define KEYBOARD_MASK_KEY_1 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_1)
+#define KEYBOARD_COL_KEY_2 4
+#define KEYBOARD_ROW_KEY_2 6
+#define KEYBOARD_MASK_KEY_2 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_2)
+#define KEYBOARD_COL_LEFT_SHIFT 7
+#define KEYBOARD_ROW_LEFT_SHIFT 1
+#define KEYBOARD_MASK_LEFT_SHIFT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_SHIFT)
+
+#endif /* __KEYBOARD_CUSTOMIZATION_H */
diff --git a/zephyr/program/skyrim/include/ztest/usb_mux_config.h b/zephyr/program/skyrim/include/ztest/usb_mux_config.h
new file mode 100644
index 0000000000..727cdf0654
--- /dev/null
+++ b/zephyr/program/skyrim/include/ztest/usb_mux_config.h
@@ -0,0 +1,19 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#ifndef __SKYRIM_TEST_USB_MUX_CONFIG
+#define __SKYRIM_TEST_USB_MUX_CONFIG
+
+#ifdef CONFIG_ZTEST
+
+#include <zephyr/fff.h>
+
+DECLARE_FAKE_VOID_FUNC(usb_mux_enable_alternative);
+
+#undef USB_MUX_ENABLE_ALTERNATIVE
+#define USB_MUX_ENABLE_ALTERNATIVE(x) usb_mux_enable_alternative()
+
+#endif /* CONFIG_ZTEST */
+
+#endif /* __SKYRIM_TEST_USB_MUX_CONFIG */
diff --git a/zephyr/program/skyrim/interrupts.dtsi b/zephyr/program/skyrim/interrupts.dtsi
new file mode 100644
index 0000000000..b329ad7124
--- /dev/null
+++ b/zephyr/program/skyrim/interrupts.dtsi
@@ -0,0 +1,146 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_lid_open: lid_open {
+			irq-pin = <&gpio_lid_open>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "lid_interrupt";
+		};
+		int_ac_present: ac_present {
+			irq-pin = <&gpio_acok_od>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "extpower_interrupt";
+		};
+		int_power_button: power_button {
+			irq-pin = <&gpio_mech_pwr_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_button_interrupt";
+		};
+		int_slp_s3: slp_s3 {
+			irq-pin = <&gpio_slp_s3_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "baseboard_en_pwr_s0";
+		};
+		int_slp_s5: slp_s5 {
+			irq-pin = <&gpio_slp_s5_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "baseboard_set_en_pwr_s3";
+		};
+		int_s5_pgood: s5_pgood {
+			irq-pin = <&gpio_pg_pwr_s5>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "baseboard_s5_pgood";
+		};
+		int_pg_groupc_s0: pg_groupc_s0 {
+			irq-pin = <&gpio_pg_groupc_s0_od>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "baseboard_set_en_pwr_pcore";
+		};
+		int_pg_lpddr_s3: pg_lpddr_s3 {
+			irq-pin = <&gpio_pg_lpddr5_s3_od>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "baseboard_set_en_pwr_pcore";
+		};
+		int_pg_lpddr_s0: pg_lpddr_s0 {
+			irq-pin = <&gpio_pg_lpddr5_s0_od>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "baseboard_set_soc_pwr_pgood";
+		};
+		int_s0_pgood: s0_pgood {
+			irq-pin = <&gpio_s0_pgood>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "baseboard_s0_pgood";
+		};
+		int_soc_thermtrip: soc_thermtrip {
+			irq-pin = <&gpio_soc_thermtrip_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "baseboard_soc_thermtrip";
+		};
+		int_soc_pcore_ocp: soc_pcore_ocp {
+			irq-pin = <&gpio_pcore_ocp_r_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "baseboard_soc_pcore_ocp";
+		};
+		int_volume_up: volume_up {
+			irq-pin = <&gpio_volup_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+		int_volume_down: volume_down {
+			irq-pin = <&gpio_voldn_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+		int_usb_a0_fault: a0_fault {
+			irq-pin = <&ioex_usb_a0_fault_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "usb_fault_interrupt";
+		};
+		int_usb_a1_fault: a1_fault {
+			irq-pin = <&ioex_usb_a1_fault_db_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "usb_fault_interrupt";
+		};
+		int_usb_c0_sbu_fault: c0_sbu_fault {
+			irq-pin = <&ioex_usb_c0_sbu_fault_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "sbu_fault_interrupt";
+		};
+		int_usb_c1_sbu_fault: c1_sbu_fault {
+			irq-pin = <&ioex_usb_c1_sbu_fault_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "sbu_fault_interrupt";
+		};
+		int_usb_c0_ppc: usb_c0_ppc {
+			irq-pin = <&gpio_usb_c0_ppc_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "ppc_interrupt";
+		};
+		int_usb_c1_ppc: usb_c1_ppc {
+			irq-pin = <&gpio_usb_c1_ppc_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "ppc_interrupt";
+		};
+		int_usb_c0_bc12: usb_c0_bc12 {
+			irq-pin = <&gpio_usb_c0_bc12_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "bc12_interrupt";
+		};
+		int_usb_c1_bc12: usb_c1_bc12 {
+			irq-pin = <&gpio_usb_c1_bc12_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "bc12_interrupt";
+		};
+		int_usb_hub_fault: hub_fault {
+			irq-pin = <&gpio_usb_hub_fault_q_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "usb_fault_interrupt";
+		};
+		int_usb_pd_soc: usb_pd_soc {
+			irq-pin = <&gpio_ec_i2c_usbc_pd_int>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "usb_pd_soc_interrupt";
+		};
+		int_accel_gyro: accel_gyro {
+			irq-pin = <&gpio_accel_gyro_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "bmi3xx_interrupt";
+		};
+		int_prochot: prochot {
+			irq-pin = <&gpio_prochot_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "throttle_ap_prochot_input_interrupt";
+		};
+		int_stb_dump: stb_dump {
+			irq-pin = <&gpio_sfh_ec_int_h>;
+			flags = <GPIO_INT_EDGE_RISING>;
+			handler = "amd_stb_dump_interrupt";
+		};
+	};
+};
diff --git a/zephyr/program/skyrim/keyboard.dtsi b/zephyr/program/skyrim/keyboard.dtsi
new file mode 100644
index 0000000000..aaf305c725
--- /dev/null
+++ b/zephyr/program/skyrim/keyboard.dtsi
@@ -0,0 +1,48 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	kblight {
+		compatible = "cros-ec,kblight-pwm";
+		pwms = <&pwm1 0 PWM_HZ(100) PWM_POLARITY_NORMAL>;
+	};
+};
+
+&pwm1 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm1_gpc2>;
+	pinctrl-names = "default";
+};
+
+&cros_kb_raw {
+	status = "okay";
+	/* No KSO2 (it's inverted and implemented by GPIO) */
+	pinctrl-0 = <
+		&ksi0_gp31
+		&ksi1_gp30
+		&ksi2_gp27
+		&ksi3_gp26
+		&ksi4_gp25
+		&ksi5_gp24
+		&ksi6_gp23
+		&ksi7_gp22
+		&kso00_gp21
+		&kso01_gp20
+		&kso03_gp16
+		&kso04_gp15
+		&kso05_gp14
+		&kso06_gp13
+		&kso07_gp12
+		&kso08_gp11
+		&kso09_gp10
+		&kso10_gp07
+		&kso11_gp06
+		&kso12_gp05
+		&kso13_gp04
+		&kso14_gp82
+	>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/skyrim/markarth/CMakeLists.txt b/zephyr/program/skyrim/markarth/CMakeLists.txt
new file mode 100644
index 0000000000..65740f572a
--- /dev/null
+++ b/zephyr/program/skyrim/markarth/CMakeLists.txt
@@ -0,0 +1,17 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cros_ec_library_include_directories_ifdef(CONFIG_BOARD_MARKARTH include)
+zephyr_library_sources(
+		"src/usb_mux_config.c"
+		"src/ppc_config.c"
+		"src/form_factor.c"
+		"src/keyboard.c"
+		"src/kb_backlight.c"
+		"src/thermal.c"
+)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_KEYBOARD_CUSTOMIZATION
+	"src/keyboard.c"
+	"src/keyboard_customization.c"
+)
diff --git a/zephyr/program/skyrim/markarth/include/keyboard_customization.h b/zephyr/program/skyrim/markarth/include/keyboard_customization.h
new file mode 100644
index 0000000000..8e7e3ee2c1
--- /dev/null
+++ b/zephyr/program/skyrim/markarth/include/keyboard_customization.h
@@ -0,0 +1,80 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Keyboard configuration */
+
+#ifndef __KEYBOARD_CUSTOMIZATION_H
+#define __KEYBOARD_CUSTOMIZATION_H
+
+#define KEYBOARD_MASK_PWRBTN KEYBOARD_ROW_TO_MASK(3)
+
+/*
+ * KEYBOARD_COLS_MAX has the build time column size. It's used to allocate
+ * exact spaces for arrays. Actual keyboard scanning is done using
+ * keyboard_cols, which holds a runtime column size.
+ */
+#ifdef CONFIG_KEYBOARD_CUSTOMIZATION
+#undef KEYBOARD_COLS_MAX
+#undef KEYBOARD_ROWS
+
+#define KEYBOARD_COLS_MAX 13
+#define KEYBOARD_ROWS 8
+#endif
+
+/*
+ * WARNING: Do not directly modify it. You should call keyboard_raw_set_cols,
+ * instead. It checks whether you're eligible or not.
+ */
+extern uint8_t keyboard_cols;
+
+#define KEYBOARD_ROW_TO_MASK(r) (1 << (r))
+
+/* Columns and masks for keys we particularly care about */
+#define KEYBOARD_COL_DOWN 11
+#define KEYBOARD_ROW_DOWN 6
+#define KEYBOARD_MASK_DOWN KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_DOWN)
+#define KEYBOARD_COL_ESC 1
+#define KEYBOARD_ROW_ESC 1
+#define KEYBOARD_MASK_ESC KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_ESC)
+#define KEYBOARD_COL_KEY_H 6
+#define KEYBOARD_ROW_KEY_H 1
+#define KEYBOARD_MASK_KEY_H KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_H)
+#define KEYBOARD_COL_KEY_R 3
+#define KEYBOARD_ROW_KEY_R 7
+#define KEYBOARD_MASK_KEY_R KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_R)
+#define KEYBOARD_COL_LEFT_ALT 10
+#define KEYBOARD_ROW_LEFT_ALT 6
+#define KEYBOARD_MASK_LEFT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_ALT)
+#define KEYBOARD_COL_REFRESH 2
+#define KEYBOARD_ROW_REFRESH 3
+#define KEYBOARD_MASK_REFRESH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_REFRESH)
+#define KEYBOARD_COL_RIGHT_ALT 10
+#define KEYBOARD_ROW_RIGHT_ALT 0
+#define KEYBOARD_MASK_RIGHT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_ALT)
+#define KEYBOARD_DEFAULT_COL_VOL_UP 4
+#define KEYBOARD_DEFAULT_ROW_VOL_UP 0
+#define KEYBOARD_COL_LEFT_CTRL 0
+#define KEYBOARD_ROW_LEFT_CTRL 2
+#define KEYBOARD_MASK_LEFT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_CTRL)
+#define KEYBOARD_COL_RIGHT_CTRL 0
+#define KEYBOARD_ROW_RIGHT_CTRL 4
+#define KEYBOARD_MASK_RIGHT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_CTRL)
+#define KEYBOARD_COL_SEARCH 1
+#define KEYBOARD_ROW_SEARCH 0
+#define KEYBOARD_MASK_SEARCH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_SEARCH)
+#define KEYBOARD_COL_KEY_0 8
+#define KEYBOARD_ROW_KEY_0 6
+#define KEYBOARD_MASK_KEY_0 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_0)
+#define KEYBOARD_COL_KEY_1 1
+#define KEYBOARD_ROW_KEY_1 6
+#define KEYBOARD_MASK_KEY_1 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_1)
+#define KEYBOARD_COL_KEY_2 4
+#define KEYBOARD_ROW_KEY_2 6
+#define KEYBOARD_MASK_KEY_2 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_2)
+#define KEYBOARD_COL_LEFT_SHIFT 7
+#define KEYBOARD_ROW_LEFT_SHIFT 5
+#define KEYBOARD_MASK_LEFT_SHIFT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_SHIFT)
+
+#endif /* __KEYBOARD_CUSTOMIZATION_H */
diff --git a/zephyr/program/skyrim/markarth/led_pins.dtsi b/zephyr/program/skyrim/markarth/led_pins.dtsi
new file mode 100644
index 0000000000..73a8b8c8fa
--- /dev/null
+++ b/zephyr/program/skyrim/markarth/led_pins.dtsi
@@ -0,0 +1,58 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	pwmleds {
+		compatible = "pwm-leds";
+		pwm_y: pwm_y {
+			pwms = <&pwm2 0 PWM_HZ(100) PWM_POLARITY_INVERTED>;
+		};
+		pwm_w: pwm_w {
+			pwms = <&pwm3 0 PWM_HZ(100) PWM_POLARITY_INVERTED>;
+		};
+	};
+
+	pwm-led-pins {
+		compatible = "cros-ec,pwm-led-pins";
+
+		battery_led: battery-led {
+			led-id = "EC_LED_ID_BATTERY_LED";
+			led-pwms = <&pwm_y &pwm_w>;
+
+			color_off: color-off {
+				led-color = "LED_OFF";
+				led-values = <0 0>;
+			};
+
+			color_amber: color-amber {
+				led-color = "LED_AMBER";
+				br-color = "EC_LED_COLOR_AMBER";
+				led-values = <100 0>;
+			};
+
+			color_blue: color-blue {
+				led-color = "LED_BLUE";
+				br-color = "EC_LED_COLOR_BLUE";
+				led-values = <0 100>;
+			};
+		};
+	};
+};
+
+/* Amber "battery charging" LED */
+&pwm2 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm2_gpc4>;
+	pinctrl-names = "default";
+};
+
+/* Blue "battery full" LED */
+&pwm3 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm3_gp80>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/skyrim/markarth/led_policy.dtsi b/zephyr/program/skyrim/markarth/led_policy.dtsi
new file mode 100644
index 0000000000..25217aeecc
--- /dev/null
+++ b/zephyr/program/skyrim/markarth/led_policy.dtsi
@@ -0,0 +1,103 @@
+#include <dt-bindings/battery.h>
+
+/ {
+	led-colors {
+		compatible = "cros-ec,led-policy";
+
+		power-state-charge {
+			charge-state = "LED_PWRS_CHARGE";
+
+			color-0 {
+				led-color = <&color_amber>;
+			};
+		};
+
+		power-state-discharge-s0 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S0";
+			/* Battery percent range (> Low, <= Full) */
+			batt-lvl = <(BATTERY_LEVEL_LOW + 1) BATTERY_LEVEL_FULL>;
+
+			color-0 {
+				led-color = <&color_blue>;
+			};
+		};
+
+		power-state-discharge-s0-batt-low {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S0";
+			/* Battery percent range (>= Empty, <= Low) */
+			batt-lvl = <BATTERY_LEVEL_EMPTY BATTERY_LEVEL_LOW>;
+
+			/* Blue 2 sec, off 1 sec */
+			color-0 {
+				led-color = <&color_blue>;
+				period-ms = <2000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <1000>;
+			};
+		};
+
+		power-state-discharge-s3 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S3";
+
+			/* Amber 1 sec, off 3 sec */
+			color-0 {
+				led-color = <&color_amber>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <3000>;
+			};
+		};
+
+		power-state-discharge-s5 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S5";
+
+			color-0 {
+				led-color = <&color_off>;
+			};
+		};
+
+		power-state-error {
+			charge-state = "LED_PWRS_ERROR";
+
+			/* Amber 1 sec, off 1 sec */
+			color-0 {
+				led-color = <&color_amber>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <1000>;
+			};
+		};
+
+		power-state-near-full {
+			charge-state = "LED_PWRS_CHARGE_NEAR_FULL";
+
+			color-0 {
+				led-color = <&color_blue>;
+			};
+		};
+
+		power-state-forced-idle {
+			charge-state = "LED_PWRS_FORCED_IDLE";
+
+			/* Amber 2 sec, Blue 2 sec */
+			color-0 {
+				led-color = <&color_amber>;
+				period-ms = <2000>;
+			};
+			color-1 {
+				led-color = <&color_blue>;
+				period-ms = <2000>;
+			};
+		};
+	};
+};
diff --git a/zephyr/program/skyrim/markarth/motionsense.dtsi b/zephyr/program/skyrim/markarth/motionsense.dtsi
new file mode 100644
index 0000000000..119c4aaf8e
--- /dev/null
+++ b/zephyr/program/skyrim/markarth/motionsense.dtsi
@@ -0,0 +1,133 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/motionsense/utils.h>
+
+
+/ {
+	aliases {
+		/*
+		 * motion sense's <>_INT_EVENT is handled
+		 * by alias. Using the alias, each driver creates
+		 * its own <>_INT_EVENT.
+		 */
+		bmi3xx-int = &base_accel;
+		bma4xx-int = &lid_accel;
+	};
+
+	/*
+	 * Declare mutexes used by sensor drivers.
+	 * A mutex node is used to create an instance of mutex_t.
+	 * A mutex node is referenced by a sensor node if the
+	 * corresponding sensor driver needs to use the
+	 * instance of the mutex.
+	 */
+	motionsense-mutex {
+		compatible = "cros-ec,motionsense-mutex";
+		lid_mutex: lid-mutex {
+		};
+
+		mutex_bmi3xx: bmi3xx-mutex {
+		};
+	};
+
+	/*
+	 * Driver specific data. A driver-specific data can be shared with
+	 * different motion sensors while they are using the same driver.
+	 *
+	 * If a node's compatible starts with "cros-ec,accelgyro-", it is for
+	 * a common structure defined in accelgyro.h.
+	 * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for
+	 * "struct als_drv_data_t" in accelgyro.h
+	 */
+	motionsense-sensor-data {
+		bma4xx_data: bma4xx-drv-data {
+			compatible = "cros-ec,drvdata-bma4xx";
+			status = "okay";
+		};
+
+		bmi3xx_data: bmi3xx-drv-data {
+			compatible = "cros-ec,drvdata-bmi3xx";
+			status = "okay";
+		};
+	};
+
+	/*
+	 * List of motion sensors that creates motion_sensors array.
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
+	 * motion sensor IDs for lid angle calculation.
+	 */
+	motionsense-sensor {
+		lid_accel: lid-accel {
+			compatible = "cros-ec,bma4xx";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&lid_mutex>;
+			port = <&i2c_sensor>;
+			drv-data = <&bma4xx_data>;
+			rot-standard-ref = <&lid_rot_ref>;
+			default-range = <2>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(12500 | ROUND_UP_FLAG)>;
+					ec-rate = <100>;
+				};
+				ec-s3 {
+					odr = <(12500 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_accel: base-accel {
+			compatible = "cros-ec,bmi3xx-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&mutex_bmi3xx>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&bmi3xx_data>;
+
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(12500 | ROUND_UP_FLAG)>;
+					ec-rate = <100>;
+				};
+				ec-s3 {
+					odr = <(12500 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base-gyro {
+			compatible = "cros-ec,bmi3xx-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&mutex_bmi3xx>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&bmi3xx_data>;
+		};
+	};
+
+	motionsense-sensor-info {
+		compatible = "cros-ec,motionsense-sensor-info";
+
+		/*
+		 * list of GPIO interrupts that have to
+		 * be enabled at initial stage
+		 */
+		sensor-irqs = <&int_lid_accel &int_accel_gyro>;
+	};
+};
diff --git a/zephyr/program/skyrim/markarth/project.conf b/zephyr/program/skyrim/markarth/project.conf
new file mode 100644
index 0000000000..b0d650272c
--- /dev/null
+++ b/zephyr/program/skyrim/markarth/project.conf
@@ -0,0 +1,40 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Markarth reference-board-specific Kconfig settings.
+CONFIG_BOARD_MARKARTH=y
+
+# CBI WP pin present
+CONFIG_PLATFORM_EC_EEPROM_CBI_WP=y
+
+# Markarth is capable of sinking 65W
+CONFIG_PLATFORM_EC_PD_MAX_POWER_MW=65000
+CONFIG_PLATFORM_EC_PD_MAX_CURRENT_MA=3250
+CONFIG_PLATFORM_EC_PD_MAX_VOLTAGE_MV=20000
+
+# Battery
+CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO=y
+
+#Disable BC12
+CONFIG_PLATFORM_EC_USB_CHARGER=n
+
+# Keyboard
+CONFIG_PLATFORM_EC_KEYBOARD_CUSTOMIZATION=y
+
+# Sensors
+CONFIG_PLATFORM_EC_DYNAMIC_MOTION_SENSOR_COUNT=y
+
+# Fan
+CONFIG_PLATFORM_EC_CUSTOM_FAN_CONTROL=y
+
+# Markarth modify monitor VBUS from TCPC
+CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_CHARGER=n
+CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_TCPC=y
+
+# Some boards detect a false VBUS reverse current event
+# First investigated on taniks (b/237468526)
+CONFIG_PLATFORM_EC_USBC_NX20P348X_RCP_5VSRC_MASK_ENABLE=y
+
+# Disable powerindebug
+CONFIG_PLATFORM_EC_CMD_POWERINDEBUG=n
diff --git a/zephyr/program/skyrim/markarth/project.overlay b/zephyr/program/skyrim/markarth/project.overlay
new file mode 100644
index 0000000000..e7a1193145
--- /dev/null
+++ b/zephyr/program/skyrim/markarth/project.overlay
@@ -0,0 +1,296 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Skyrim program common DTS includes */
+#include "../adc.dtsi"
+#include "../fan.dtsi"
+#include "../gpio.dtsi"
+#include "../i2c.dtsi"
+#include "../interrupts.dtsi"
+#include "../keyboard.dtsi"
+#include "../usbc.dtsi"
+
+/* Markarth project DTS includes*/
+#include "led_pins.dtsi"
+#include "led_policy.dtsi"
+#include "motionsense.dtsi"
+
+/* Markarth overrides follow... */
+/ {
+	/* battery overrides */
+	batteries {
+		default_battery: lgc_ap19b8m-2 {
+			compatible = "lgc,ap19b8m", "battery-smart";
+		};
+		cosmx_ap20cbl-3 {
+			compatible = "cosmx,ap20cbl-3", "battery-smart";
+		};
+	};
+
+	named-gpios {
+		/* Markarth-specific GPIO customizations */
+		gpio_usb_c0_bc12_int_odl: usb_c0_bc12_int_odl {
+			gpios = <&gpioa 4 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C0_BC12_INT_ODL";
+		};
+		gpio_usb_c1_bc12_int_odl: usb_c1_bc12_int_odl {
+			gpios = <&gpio9 6 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C1_BC12_INT_ODL";
+		};
+	};
+
+	gpio-interrupts {
+		int_lid_accel: lid_accel {
+			irq-pin = <&gpio_lid_accel_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "bma4xx_interrupt";
+		};
+	};
+
+	/* gpio-interrupts overrides */
+	gpio-interrupts {
+		/delete-node/ usb_c0_bc12;
+		/delete-node/ usb_c1_bc12;
+	};
+
+	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
+		temp_f75303_local: f75303-local {
+			power-good-pin = <&gpio_pg_pwr_s5>;
+			sensor = <&f75303_local>;
+		};
+		temp_f75303_remote_1: f75303-remote-1 {
+			power-good-pin = <&gpio_pg_pwr_s5>;
+			sensor = <&f75303_remote_1>;
+		};
+		temp_f75303_remote_2: f75303-remote-2 {
+			power-good-pin = <&gpio_pg_pwr_s5>;
+			sensor = <&f75303_remote_2>;
+		};
+	};
+
+	fan_steps: fan-step {
+		compatible = "cros-ec,fan-steps";
+		level_0 {
+			temp_on = <(-1) (-1) 75 (-1) 30 (-1)>;
+			temp_off = <(-1) (-1) 99 (-1) 99 (-1)>;
+			rpm_target = <0>;
+		};
+		level_1 {
+			temp_on = <(-1) (-1) 75 (-1) 35 (-1)>;
+			temp_off = <(-1) (-1) 99 (-1) 32 (-1)>;
+			rpm_target = <2200>;
+		};
+		level_2 {
+			temp_on = <(-1) (-1) 75 (-1) 40 (-1)>;
+			temp_off = <(-1) (-1) 99 (-1) 37 (-1)>;
+			rpm_target = <2400>;
+		};
+		level_3 {
+			temp_on = <(-1) (-1) 75 (-1) 43 (-1)>;
+			temp_off = <(-1) (-1) 99 (-1) 41 (-1)>;
+			rpm_target = <2700>;
+		};
+		level_4 {
+			temp_on = <(-1) (-1) 75 (-1) 46 (-1)>;
+			temp_off = <(-1) (-1) 99 (-1) 44 (-1)>;
+			rpm_target = <3000>;
+		};
+		level_5 {
+			temp_on = <(-1) (-1) 95 (-1) 50 (-1)>;
+			temp_off = <(-1) (-1) 90 (-1) 48 (-1)>;
+			rpm_target = <3300>;
+		};
+	};
+
+	/*
+	 * Note this is expected to vary per-board, so we keep it in the overlay
+	 * files.
+	 */
+	markarth-fw-config {
+		compatible = "cros-ec,cbi-fw-config";
+
+		form-factor {
+			enum-name = "FW_FORM_FACTOR";
+			start = <0>;
+			size = <1>;
+
+			ff-clamshell {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FF_CLAMSHELL";
+				value = <0>;
+			};
+			ff-convertible {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FF_CONVERTIBLE";
+				value = <1>;
+				default;
+			};
+		};
+
+		/*
+		 * FW_CONFIG field to enable KB back light or not.
+		 */
+		kb-bl {
+			enum-name = "FW_KB_BL";
+			start = <1>;
+			size = <1>;
+
+			no-kb-bl {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_KB_BL_NOT_PRESENT";
+				value = <0>;
+			};
+			kb-bl-present {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_KB_BL_PRESENT";
+				value = <1>;
+			};
+		};
+	};
+
+	/* Rotation matrices for motion sensors. */
+	motionsense-rotation-ref {
+		compatible = "cros-ec,motionsense-rotation-ref";
+		lid_rot_ref: lid-rotation-ref {
+			mat33 = <0 (-1) 0
+				 1 0 0
+				 0 0 1>;
+		};
+
+		base_rot_ref: base-rotation-ref {
+			mat33 = <0 1 0
+				 (-1) 0 0
+				 0 0 1>;
+		};
+	};
+
+	ppc_port0: aoz1380 {
+		compatible = "aoz,aoz1380";
+		status = "okay";
+	};
+};
+
+/* i2c overrides */
+&i2c0_0 {
+	/delete-node/ nx20p348x@71;
+	/delete-node/ pi3usb9201@5f;
+	/delete-node/ anx7483@3e;
+};
+
+&amd_fp6_port0 {
+	board-set = "board_c0_amd_fp6_mux_set";
+};
+
+&i2c1_0 {
+	/delete-node/ pi3usb9201@5f;
+	/delete-node/ anx7483@3e;
+};
+
+&i2c4_1 {
+	/delete-node/ isl9538@9;
+};
+
+/* usbc overrides */
+&usbc_port0 {
+	/delete-property/ bc12;
+	/delete-property/ chg_alt;
+	usb-mux-chain-0 {
+		usb-muxes = <&amd_fp6_port0>;
+	};
+};
+
+&usbc_port1 {
+	/delete-property/ bc12;
+	/delete-node/ usb-mux-chain-1-anx;
+	/delete-node/ usb-mux-chain-1-ps;
+	usb-mux-chain-1-ps8818 {
+		compatible = "cros-ec,usb-mux-chain";
+		usb-muxes = <&amd_fp6_port1 &ps8818_port1>;
+	};
+};
+
+&i2c6_1 {
+	/delete-node/ soc-pct2075@48;
+	/delete-node/ amb-pct2075@4f;
+	f75303_local: f75303-local@4d {
+		compatible = "cros-ec,temp-sensor-f75303";
+		reg = <0x4d>;
+		temperature-type = "F75303_IDX_LOCAL";
+	};
+	f75303_remote_1: f75303-remote-1@4d {
+		compatible = "cros-ec,temp-sensor-f75303";
+		reg = <0x4d>;
+		temperature-type = "F75303_IDX_REMOTE1";
+	};
+	f75303_remote_2: f75303-remote-2@4d {
+		compatible = "cros-ec,temp-sensor-f75303";
+		reg = <0x4d>;
+		temperature-type = "F75303_IDX_REMOTE2";
+	};
+};
+
+&i2c_sensor {
+	/delete-node/ enum-names;
+	enum-names = "I2C_PORT_THERMAL";
+};
+
+&cros_kb_raw {
+	status = "okay";
+	pinctrl-0 = <
+		&ksi0_gp31
+		&ksi1_gp30
+		&ksi2_gp27
+		&ksi3_gp26
+		&ksi4_gp25
+		&ksi5_gp24
+		&ksi6_gp23
+		&ksi7_gp22
+		&kso00_gp21
+		&kso01_gp20
+		&kso03_gp16
+		&kso04_gp15
+		&kso05_gp14
+		&kso06_gp13
+		&kso07_gp12
+		&kso08_gp11
+		&kso09_gp10
+		&kso10_gp07
+		&kso11_gp06
+		&kso12_gp05
+	>;
+};
+
+&temp_sensor_cpu {
+	temp_host_warn = <92>;
+	temp_host_high = <95>;
+	temp_host_halt = <100>;
+	temp_host_release_warn = <91>;
+	temp_host_release_high = <80>;
+	temp_host_release_halt = <90>;
+};
+
+&temp_sensor_charger {
+	/delete-property/ temp_host_high;
+	/delete-property/ temp_host_halt;
+	/delete-property/ temp_host_release_high;
+	/delete-property/ temp_host_release_halt;
+};
+
+&temp_sensor_memory {
+	/delete-property/ temp_host_high;
+	/delete-property/ temp_host_halt;
+	/delete-property/ temp_host_release_high;
+	/delete-property/ temp_host_release_halt;
+};
+
+/* fan overrides */
+&fan0 {
+	pwms = <&pwm0 0 PWM_KHZ(25) PWM_POLARITY_NORMAL>;
+	rpm_min = <2100>;
+	rpm_start = <2400>;
+	rpm_max = <4464>;
+	rpm_deviation = <2>;
+};
diff --git a/zephyr/program/skyrim/markarth/src/form_factor.c b/zephyr/program/skyrim/markarth/src/form_factor.c
new file mode 100644
index 0000000000..5b8b27663d
--- /dev/null
+++ b/zephyr/program/skyrim/markarth/src/form_factor.c
@@ -0,0 +1,39 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "accelgyro.h"
+#include "common.h"
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "motionsense_sensors.h"
+#include "tablet_mode.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(markarth, CONFIG_SKYRIM_LOG_LEVEL);
+
+static void clamshell_init(void)
+{
+	int ret;
+	uint32_t val;
+
+	/* Check the form factor from CBI */
+	ret = cros_cbi_get_fw_config(FW_FORM_FACTOR, &val);
+	if (ret != 0) {
+		LOG_ERR("Cannot get FW_FORM_FACTOR");
+		return;
+	}
+
+	if (val == FW_FF_CLAMSHELL) {
+		motion_sensor_count = 0;
+		gpio_disable_dt_interrupt(
+			GPIO_INT_FROM_NODELABEL(int_accel_gyro));
+		gmr_tablet_switch_disable();
+	}
+}
+DECLARE_HOOK(HOOK_INIT, clamshell_init, HOOK_PRIO_POST_DEFAULT);
diff --git a/zephyr/program/skyrim/markarth/src/kb_backlight.c b/zephyr/program/skyrim/markarth/src/kb_backlight.c
new file mode 100644
index 0000000000..4f394bd79a
--- /dev/null
+++ b/zephyr/program/skyrim/markarth/src/kb_backlight.c
@@ -0,0 +1,34 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "board_config.h"
+#include "common.h"
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(markarth, CONFIG_SKYRIM_LOG_LEVEL);
+
+__override uint32_t board_override_feature_flags0(uint32_t flags0)
+{
+	int ret;
+	uint32_t val;
+
+	/*
+	 * Remove keyboard backlight feature for devices that don't support it.
+	 */
+	ret = cros_cbi_get_fw_config(FW_KB_BL, &val);
+	if (ret != 0) {
+		LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_KB_BL);
+		return flags0;
+	}
+
+	if (val == FW_KB_BL_NOT_PRESENT)
+		return (flags0 & ~EC_FEATURE_MASK_0(EC_FEATURE_PWM_KEYB));
+	else
+		return flags0;
+}
diff --git a/zephyr/program/skyrim/markarth/src/keyboard.c b/zephyr/program/skyrim/markarth/src/keyboard.c
new file mode 100644
index 0000000000..9a3baaaebe
--- /dev/null
+++ b/zephyr/program/skyrim/markarth/src/keyboard.c
@@ -0,0 +1,74 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+#include "keyboard_scan.h"
+#include "timer.h"
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/* Increase from 50 us, because KSO_02 passes through the H1. */
+	.output_settle_us = 80,
+	/* Other values should be the same as the default configuration. */
+	.debounce_down_us = 9 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x1c, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xa4, 0xff, 0xf7, 0x55, 0xfb, 0xca,
+	},
+};
+
+static const struct ec_response_keybd_config markarth_kb = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &markarth_kb;
+}
+
+/*
+ * Row Column info for Top row keys T1 - T10.
+ * on markarth_kb keyboard Row Column is customization
+ * need define row col to mapping matrix layout.
+ */
+__override const struct key {
+	uint8_t row;
+	uint8_t col;
+} vivaldi_keys[] = {
+	{ .row = 0, .col = 2 }, /* T1 */
+	{ .row = 3, .col = 2 }, /* T2 */
+	{ .row = 2, .col = 2 }, /* T3 */
+	{ .row = 1, .col = 2 }, /* T4 */
+	{ .row = 3, .col = 4 }, /* T5 */
+	{ .row = 2, .col = 4 }, /* T6 */
+	{ .row = 1, .col = 4 }, /* T7 */
+	{ .row = 2, .col = 9 }, /* T8 */
+	{ .row = 1, .col = 9 }, /* T9 */
+	{ .row = 0, .col = 4 }, /* T10 */
+	{ .row = 3, .col = 0 }, /* T11 */
+	{ .row = 1, .col = 5 }, /* T12 */
+	{ .row = 3, .col = 5 }, /* T13 */
+	{ .row = 0, .col = 9 }, /* T14 */
+	{ .row = 0, .col = 11 }, /* T15 */
+};
+BUILD_ASSERT(ARRAY_SIZE(vivaldi_keys) == MAX_TOP_ROW_KEYS);
diff --git a/zephyr/program/skyrim/markarth/src/keyboard_customization.c b/zephyr/program/skyrim/markarth/src/keyboard_customization.c
new file mode 100644
index 0000000000..26d584ffbe
--- /dev/null
+++ b/zephyr/program/skyrim/markarth/src/keyboard_customization.c
@@ -0,0 +1,83 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "gpio.h"
+#include "keyboard_customization.h"
+#include "keyboard_protocol.h"
+#include "keyboard_raw.h"
+
+#include <zephyr/drivers/gpio.h>
+
+static uint16_t scancode_set2[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = {
+	{ 0x0000, 0x0000, 0x0014, 0x0000, 0xe014, 0x0000, 0x0000, 0x0000 },
+	{ 0xe01f, 0x0076, 0x000d, 0x000e, 0x001c, 0x001a, 0x0016, 0x0015 },
+	{ 0x0005, 0x000c, 0x0004, 0x0006, 0x0023, 0x0021, 0x0026, 0x0024 },
+	{ 0x0032, 0x0034, 0x002c, 0x002e, 0x002b, 0x002a, 0x0025, 0x002d },
+	{ 0x000a, 0x0083, 0x000b, 0x0003, 0x001b, 0x0022, 0x001e, 0x001d },
+	{ 0x0051, 0x0000, 0x005b, 0x0000, 0x0042, 0x0041, 0x003e, 0x0043 },
+	{ 0x0031, 0x0033, 0x0035, 0x0036, 0x003b, 0x003a, 0x003d, 0x003c },
+	{ 0x0000, 0x0000, 0x0061, 0x0000, 0x0000, 0x0012, 0x0000, 0x0059 },
+	{ 0x0055, 0x0052, 0x0054, 0x004e, 0x004c, 0x004a, 0x0045, 0x004d },
+	{ 0x0000, 0x0078, 0x0009, 0x0000, 0x004b, 0x0049, 0x0046, 0x0044 },
+	{ 0xe011, 0x0000, 0x006a, 0x0000, 0x005d, 0x0000, 0x0011, 0x0000 },
+	{ 0x0000, 0x0066, 0x0000, 0x005d, 0x005a, 0x0029, 0xe072, 0xe075 },
+	{ 0x0000, 0xe064, 0x0000, 0x0067, 0x0000, 0x0000, 0xe074, 0xe06b },
+};
+
+uint16_t get_scancode_set2(uint8_t row, uint8_t col)
+{
+	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS)
+		return scancode_set2[col][row];
+	return 0;
+}
+
+void set_scancode_set2(uint8_t row, uint8_t col, uint16_t val)
+{
+	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS)
+		scancode_set2[col][row] = val;
+}
+
+#ifdef CONFIG_KEYBOARD_DEBUG
+static uint8_t keycap_label[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = {
+	{ 'c', KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO },
+	{ KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO },
+	{ 'q', KLLI_UNKNO, KLLI_UNKNO, KLLI_TAB, '`', '1', KLLI_UNKNO, 'a' },
+	{ KLLI_R_ALT, KLLI_L_ALT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO },
+	{ KLLI_UNKNO, KLLI_SPACE, 'e', KLLI_F4, KLLI_SEARC, '3', KLLI_F3,
+	  KLLI_UNKNO },
+	{ 'x', 'z', KLLI_F2, KLLI_F1, 's', '2', 'w', KLLI_ESC },
+	{ 'v', 'b', 'g', 't', '5', '4', 'r', 'f' },
+	{ 'm', 'n', 'h', 'y', '6', '7', 'u', 'j' },
+	{ '.', KLLI_DOWN, '\\', 'o', KLLI_F10, '9', KLLI_UNKNO, 'l' },
+	{ KLLI_R_SHT, KLLI_L_SHT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO },
+	{ ',', KLLI_UNKNO, KLLI_F7, KLLI_F6, KLLI_F5, '8', 'i', 'k' },
+	{ KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_F9, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_LEFT, KLLI_UNKNO },
+	{ KLLI_R_CTR, KLLI_L_CTR, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO },
+	{ '/', KLLI_UP, '-', KLLI_UNKNO, '0', 'p', '[', ';' },
+	{ '\'', KLLI_ENTER, KLLI_UNKNO, KLLI_UNKNO, '=', KLLI_B_SPC, ']', 'd' },
+	{ KLLI_UNKNO, KLLI_F8, KLLI_RIGHT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO },
+};
+
+uint8_t get_keycap_label(uint8_t row, uint8_t col)
+{
+	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS)
+		return keycap_label[col][row];
+	return KLLI_UNKNO;
+}
+
+void set_keycap_label(uint8_t row, uint8_t col, uint8_t val)
+{
+	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS)
+		keycap_label[col][row] = val;
+}
+#endif
diff --git a/zephyr/program/skyrim/markarth/src/ppc_config.c b/zephyr/program/skyrim/markarth/src/ppc_config.c
new file mode 100644
index 0000000000..25c36b0c48
--- /dev/null
+++ b/zephyr/program/skyrim/markarth/src/ppc_config.c
@@ -0,0 +1,49 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Markarth board-specific PPC code */
+
+#include "driver/ppc/aoz1380_public.h"
+#include "driver/ppc/nx20p348x.h"
+#include "usbc_ppc.h"
+
+#include <zephyr/drivers/gpio.h>
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/*
+ * In the AOZ1380 PPC, there are no programmable features.  We use
+ * the attached NCT3807 to control a GPIO to indicate 1A5 or 3A0
+ * current limits.
+ */
+int board_aoz1380_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	int rv = EC_SUCCESS;
+
+	if (port != 0)
+		return EC_ERROR_INVAL;
+
+	rv = gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(ioex_usb_c0_ilim_3a_en),
+			     (rp == TYPEC_RP_3A0) ? 1 : 0);
+
+	return rv;
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		aoz1380_interrupt(0);
+		break;
+
+	case GPIO_USB_C1_PPC_INT_ODL:
+		nx20p348x_interrupt(1);
+		break;
+
+	default:
+		break;
+	}
+}
diff --git a/zephyr/program/skyrim/markarth/src/thermal.c b/zephyr/program/skyrim/markarth/src/thermal.c
new file mode 100644
index 0000000000..d92951420c
--- /dev/null
+++ b/zephyr/program/skyrim/markarth/src/thermal.c
@@ -0,0 +1,108 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "fan.h"
+#include "tablet_mode.h"
+#include "temp_sensor/temp_sensor.h"
+#include "thermal.h"
+#include "util.h"
+
+#define TEMP_CPU TEMP_SENSOR_ID(DT_NODELABEL(temp_sensor_cpu))
+#define TEMP_REMOTE_1 TEMP_SENSOR_ID(DT_NODELABEL(temp_f75303_remote_1))
+
+struct fan_step {
+	/*
+	 * Sensor 0~4 trigger point, set -1 if we're not using this
+	 * sensor to determine fan speed.
+	 */
+	int on[TEMP_SENSOR_COUNT];
+	/*
+	 * Sensor 0~4 release point, set -1 if we're not using this
+	 * sensor to determine fan speed.
+	 */
+	int off[TEMP_SENSOR_COUNT];
+	/* Fan rpm */
+	uint16_t rpm[FAN_CH_COUNT];
+};
+
+#define FAN_TABLE_ENTRY(nd)                     \
+	{                                       \
+		.on = DT_PROP(nd, temp_on),     \
+		.off = DT_PROP(nd, temp_off),   \
+		.rpm = DT_PROP(nd, rpm_target), \
+	},
+
+static const struct fan_step fan_table[] = { DT_FOREACH_CHILD(
+	DT_NODELABEL(fan_steps), FAN_TABLE_ENTRY) };
+
+static const struct fan_step *fan_step_table = fan_table;
+#define NUM_FAN_LEVELS ARRAY_SIZE(fan_table)
+
+int fan_table_to_rpm(int fan, int *temp)
+{
+	/* current fan level */
+	static int current_level;
+	/* previous sensor temperature */
+	static int prev_tmp[TEMP_SENSOR_COUNT];
+	int i;
+
+	/*
+	 * Compare the current and previous temperature, we have
+	 * the three paths :
+	 *  1. decreasing path. (check the release point)
+	 *  2. increasing path. (check the trigger point)
+	 *  3. invariant path. (return the current RPM)
+	 */
+
+	if ((temp[TEMP_CPU] < prev_tmp[TEMP_CPU]) ||
+	    (temp[TEMP_REMOTE_1] < prev_tmp[TEMP_REMOTE_1])) {
+		for (i = current_level; i > 0; i--) {
+			if ((temp[TEMP_CPU] <=
+			     fan_step_table[i].off[TEMP_CPU]) &&
+			    (temp[TEMP_REMOTE_1] <=
+			     fan_step_table[i].off[TEMP_REMOTE_1]))
+				current_level = i - 1;
+			else
+				break;
+		}
+	} else if ((temp[TEMP_CPU] > prev_tmp[TEMP_CPU]) ||
+		   (temp[TEMP_REMOTE_1] > prev_tmp[TEMP_REMOTE_1])) {
+		for (i = current_level; i < NUM_FAN_LEVELS; i++) {
+			if ((temp[TEMP_CPU] >=
+			     fan_step_table[i].on[TEMP_CPU]) ||
+			    (temp[TEMP_REMOTE_1] >=
+			     fan_step_table[i].on[TEMP_REMOTE_1]))
+				current_level = i;
+			else
+				break;
+		}
+	}
+
+	if (current_level < 0)
+		current_level = 0;
+
+	if (current_level >= NUM_FAN_LEVELS)
+		current_level = NUM_FAN_LEVELS - 1;
+
+	for (i = 0; i < TEMP_SENSOR_COUNT; ++i)
+		prev_tmp[i] = temp[i];
+
+	return fan_step_table[current_level].rpm[fan];
+}
+
+void board_override_fan_control(int fan, int *temp)
+{
+	/*
+	 * In common/fan.c pwm_fan_stop() will turn off fan
+	 * when chipset suspend or shutdown.
+	 */
+	if (chipset_in_state(CHIPSET_STATE_ON)) {
+		fan_set_rpm_mode(fan, 1);
+		fan_set_rpm_target(fan, fan_table_to_rpm(fan, temp));
+	}
+}
diff --git a/zephyr/program/skyrim/markarth/src/usb_mux_config.c b/zephyr/program/skyrim/markarth/src/usb_mux_config.c
new file mode 100644
index 0000000000..41015df680
--- /dev/null
+++ b/zephyr/program/skyrim/markarth/src/usb_mux_config.c
@@ -0,0 +1,71 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Markarth board-specific USB-C mux configuration */
+
+#include "console.h"
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+#include "driver/retimer/anx7483_public.h"
+#include "hooks.h"
+#include "ioexpander.h"
+#include "usb_mux.h"
+#include "usbc/usb_muxes.h"
+#include "ztest/usb_mux_config.h"
+
+#include <zephyr/drivers/gpio.h>
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/*
+ * USB C0 (general) and C1 (just ANX DB) use IOEX pins to
+ * indicate flipped polarity to a protection switch.
+ */
+test_export_static int ioex_set_flip(int port, mux_state_t mux_state)
+{
+	if (port == 0) {
+		if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
+			gpio_pin_set_dt(
+				GPIO_DT_FROM_NODELABEL(ioex_usb_c0_sbu_flip),
+				1);
+		else
+			gpio_pin_set_dt(
+				GPIO_DT_FROM_NODELABEL(ioex_usb_c0_sbu_flip),
+				0);
+	} else {
+		if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
+			gpio_pin_set_dt(
+				GPIO_DT_FROM_NODELABEL(ioex_usb_c1_sbu_flip),
+				1);
+		else
+			gpio_pin_set_dt(
+				GPIO_DT_FROM_NODELABEL(ioex_usb_c1_sbu_flip),
+				0);
+	}
+
+	return EC_SUCCESS;
+}
+
+int board_c0_amd_fp6_mux_set(const struct usb_mux *me, mux_state_t mux_state)
+{
+	/* Set the SBU polarity mux */
+	RETURN_ERROR(ioex_set_flip(me->usb_port, mux_state));
+
+	return EC_SUCCESS;
+}
+
+int board_c1_ps8818_mux_set(const struct usb_mux *me, mux_state_t mux_state)
+{
+	CPRINTSUSB("C1: PS8818 mux using default tuning");
+
+	/* Once a DP connection is established, we need to set IN_HPD */
+	if (mux_state & USB_PD_MUX_DP_ENABLED)
+		ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 1);
+	else
+		ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 0);
+
+	return 0;
+}
diff --git a/zephyr/program/skyrim/motionsense.dtsi b/zephyr/program/skyrim/motionsense.dtsi
new file mode 100644
index 0000000000..119c4aaf8e
--- /dev/null
+++ b/zephyr/program/skyrim/motionsense.dtsi
@@ -0,0 +1,133 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/motionsense/utils.h>
+
+
+/ {
+	aliases {
+		/*
+		 * motion sense's <>_INT_EVENT is handled
+		 * by alias. Using the alias, each driver creates
+		 * its own <>_INT_EVENT.
+		 */
+		bmi3xx-int = &base_accel;
+		bma4xx-int = &lid_accel;
+	};
+
+	/*
+	 * Declare mutexes used by sensor drivers.
+	 * A mutex node is used to create an instance of mutex_t.
+	 * A mutex node is referenced by a sensor node if the
+	 * corresponding sensor driver needs to use the
+	 * instance of the mutex.
+	 */
+	motionsense-mutex {
+		compatible = "cros-ec,motionsense-mutex";
+		lid_mutex: lid-mutex {
+		};
+
+		mutex_bmi3xx: bmi3xx-mutex {
+		};
+	};
+
+	/*
+	 * Driver specific data. A driver-specific data can be shared with
+	 * different motion sensors while they are using the same driver.
+	 *
+	 * If a node's compatible starts with "cros-ec,accelgyro-", it is for
+	 * a common structure defined in accelgyro.h.
+	 * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for
+	 * "struct als_drv_data_t" in accelgyro.h
+	 */
+	motionsense-sensor-data {
+		bma4xx_data: bma4xx-drv-data {
+			compatible = "cros-ec,drvdata-bma4xx";
+			status = "okay";
+		};
+
+		bmi3xx_data: bmi3xx-drv-data {
+			compatible = "cros-ec,drvdata-bmi3xx";
+			status = "okay";
+		};
+	};
+
+	/*
+	 * List of motion sensors that creates motion_sensors array.
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
+	 * motion sensor IDs for lid angle calculation.
+	 */
+	motionsense-sensor {
+		lid_accel: lid-accel {
+			compatible = "cros-ec,bma4xx";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&lid_mutex>;
+			port = <&i2c_sensor>;
+			drv-data = <&bma4xx_data>;
+			rot-standard-ref = <&lid_rot_ref>;
+			default-range = <2>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(12500 | ROUND_UP_FLAG)>;
+					ec-rate = <100>;
+				};
+				ec-s3 {
+					odr = <(12500 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_accel: base-accel {
+			compatible = "cros-ec,bmi3xx-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&mutex_bmi3xx>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&bmi3xx_data>;
+
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(12500 | ROUND_UP_FLAG)>;
+					ec-rate = <100>;
+				};
+				ec-s3 {
+					odr = <(12500 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base-gyro {
+			compatible = "cros-ec,bmi3xx-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&mutex_bmi3xx>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&bmi3xx_data>;
+		};
+	};
+
+	motionsense-sensor-info {
+		compatible = "cros-ec,motionsense-sensor-info";
+
+		/*
+		 * list of GPIO interrupts that have to
+		 * be enabled at initial stage
+		 */
+		sensor-irqs = <&int_lid_accel &int_accel_gyro>;
+	};
+};
diff --git a/zephyr/program/skyrim/program.conf b/zephyr/program/skyrim/program.conf
new file mode 100644
index 0000000000..d2f5ccdd1d
--- /dev/null
+++ b/zephyr/program/skyrim/program.conf
@@ -0,0 +1,141 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_CROS_EC=y
+CONFIG_PLATFORM_EC=y
+CONFIG_ESPI=y
+
+# Shell features
+CONFIG_SHELL_HISTORY=y
+CONFIG_SHELL_TAB=y
+CONFIG_SHELL_TAB_AUTOCOMPLETION=y
+CONFIG_KERNEL_SHELL=y
+
+# Power sequencing
+CONFIG_AP=y
+CONFIG_AP_X86_AMD=y
+CONFIG_PLATFORM_EC_POWERSEQ=y
+CONFIG_PLATFORM_EC_POWER_BUTTON_TO_PCH_CUSTOM=y
+CONFIG_PLATFORM_EC_POWER_SLEEP_FAILURE_DETECTION=y
+CONFIG_PLATFORM_EC_POWERSEQ_RSMRST_DELAY=y
+CONFIG_PLATFORM_EC_POWERSEQ_S0IX=y
+CONFIG_PLATFORM_EC_POWERSEQ_CPU_PROCHOT_ACTIVE_LOW=y
+CONFIG_PLATFORM_EC_PORT80=y
+
+# Power button
+CONFIG_PLATFORM_EC_POWER_BUTTON=y
+
+# CBI
+CONFIG_EEPROM=y
+CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=y
+CONFIG_PLATFORM_EC_EEPROM_CBI_WP=y
+
+# Temperature Sensors
+CONFIG_PLATFORM_EC_AMD_SB_RMI=y
+CONFIG_PLATFORM_EC_AMD_STT=y
+CONFIG_PLATFORM_EC_THROTTLE_AP=y
+# An external prochot can only be triggered by the charger
+# and during on the fan would increase current draw and make it worse.
+CONFIG_PLATFORM_EC_THROTTLE_AP_NO_FAN=y
+CONFIG_PLATFORM_EC_THROTTLE_AP_SINGLE_PIN=y
+
+# External power
+CONFIG_PLATFORM_EC_HOSTCMD=y
+CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=y
+CONFIG_PLATFORM_EC_BACKLIGHT_LID_ACTIVE_LOW=y
+
+# Lid switch
+CONFIG_PLATFORM_EC_LID_ANGLE=y
+CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y
+CONFIG_PLATFORM_EC_LID_SWITCH=y
+
+# Keyboard
+CONFIG_PLATFORM_EC_KBLIGHT_ENABLE_PIN=y
+CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED=y
+CONFIG_PLATFORM_EC_VOLUME_BUTTONS=y
+CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI3=y
+CONFIG_PLATFORM_EC_KEYBOARD_REFRESH_ROW3=y
+
+# Syscon
+CONFIG_SYSCON=y
+
+# Battery
+CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y
+CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y
+CONFIG_PLATFORM_EC_BATTERY_REVIVE_DISCONNECT=y
+CONFIG_PLATFORM_EC_SMBUS_PEC=y
+
+# Charger
+CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y
+CONFIG_PLATFORM_EC_CHARGER_DEFAULT_CURRENT_LIMIT=512
+CONFIG_PLATFORM_EC_CHARGER_MIN_INPUT_CURRENT_LIMIT=512
+CONFIG_PLATFORM_EC_CHARGER_ISL9241=y
+CONFIG_PLATFORM_EC_CHARGER_DUMP_PROCHOT=y
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=20
+CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON=50000
+
+# USB-C
+CONFIG_PLATFORM_EC_USBC_RETIMER_ANX7451=y
+CONFIG_PLATFORM_EC_USBC_RETIMER_PS8811=y
+CONFIG_PLATFORM_EC_USBC_SS_MUX_DFP_ONLY=y
+CONFIG_PLATFORM_EC_USB_MUX_RUNTIME_CONFIG=y
+CONFIG_PLATFORM_EC_USB_DRP_ACC_TRYSRC=y
+CONFIG_PLATFORM_EC_USB_PID=0x505F
+CONFIG_PLATFORM_EC_USB_PD_5V_EN_CUSTOM=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y
+CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_TCPC=y
+CONFIG_PLATFORM_EC_USB_PD_DP_HPD_GPIO=y
+CONFIG_PLATFORM_EC_USB_PD_FRS=y
+CONFIG_PLATFORM_EC_USB_PD_FRS_TCPC=y
+CONFIG_PLATFORM_EC_USB_PD_LOGGING=y
+CONFIG_PLATFORM_EC_USB_PD_REV30=y
+CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=n
+CONFIG_PLATFORM_EC_USB_PD_TCPC_LOW_POWER=y
+CONFIG_PLATFORM_EC_USB_PD_TCPC_RUNTIME_CONFIG=n
+CONFIG_PLATFORM_EC_USB_PD_USB4=n
+CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_CHARGER=y
+# Give ourselves enough task space to use i2ctrace
+CONFIG_TASK_PD_STACK_SIZE=1280
+
+# Motion sense
+CONFIG_PLATFORM_EC_ACCEL_FIFO=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=y
+CONFIG_PLATFORM_EC_LID_ANGLE=y
+CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y
+CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=y
+
+CONFIG_PLATFORM_EC_MKBP_EVENT=y
+CONFIG_PLATFORM_EC_MKBP_INPUT_DEVICES=y
+CONFIG_PLATFORM_EC_MKBP_USE_GPIO=y
+
+CONFIG_PLATFORM_EC_TABLET_MODE=y
+CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=y
+CONFIG_PLATFORM_EC_GMR_TABLET_MODE=y
+
+CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y
+
+# Misc.
+CONFIG_PLATFORM_EC_AMD_STB_DUMP=y
+CONFIG_PLATFORM_EC_EMULATED_SYSRQ=y
+CONFIG_PLATFORM_EC_PORT80_4_BYTE=y
+
+# System safe mode for improved panic debugging
+CONFIG_PLATFORM_EC_SYSTEM_SAFE_MODE=y # 576 bytes + 56 bytes RAM
+
+# These are debug options that happen to be expensive in terms of flash space.
+# Turn on as needed based on demand.
+CONFIG_FLASH_PAGE_LAYOUT=n # 1876 bytes
+CONFIG_FLASH_SHELL=n # 1852 bytes
+CONFIG_PLATFORM_EC_ACCEL_SPOOF_MODE=y # 548 bytes
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=n # 656 bytes
+CONFIG_PLATFORM_EC_CONSOLE_CMD_MEM=n # 896 bytes
+CONFIG_PLATFORM_EC_CONSOLE_CMD_TCPC_DUMP=n # 1180 bytes
+CONFIG_PLATFORM_EC_CONSOLE_CMD_USB_PD_CABLE=n # 1104 bytes
+CONFIG_SHELL_HELP=n # 3432 bytes
+CONFIG_THREAD_MONITOR=n # 1548 bytes
diff --git a/zephyr/program/skyrim/skyrim/CMakeLists.txt b/zephyr/program/skyrim/skyrim/CMakeLists.txt
new file mode 100644
index 0000000000..fef1c72a31
--- /dev/null
+++ b/zephyr/program/skyrim/skyrim/CMakeLists.txt
@@ -0,0 +1,13 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cros_ec_library_include_directories_ifdef(CONFIG_BOARD_SKYRIM include)
+zephyr_library_sources(
+		"src/usb_mux_config.c"
+		"src/ppc_config.c"
+		"src/form_factor.c"
+		"src/alt_charger.c"
+		"src/keyboard.c"
+)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FAN "src/fan.c")
diff --git a/zephyr/program/skyrim/skyrim/led_pins.dtsi b/zephyr/program/skyrim/skyrim/led_pins.dtsi
new file mode 100644
index 0000000000..28766c5271
--- /dev/null
+++ b/zephyr/program/skyrim/skyrim/led_pins.dtsi
@@ -0,0 +1,58 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	pwmleds {
+		compatible = "pwm-leds";
+		pwm_y: pwm_y {
+			pwms = <&pwm2 0 PWM_HZ(100) PWM_POLARITY_INVERTED>;
+		};
+		pwm_w: pwm_w {
+			pwms = <&pwm3 0 PWM_HZ(100) PWM_POLARITY_INVERTED>;
+		};
+	};
+
+	pwm-led-pins {
+		compatible = "cros-ec,pwm-led-pins";
+
+		battery_led: battery-led {
+			led-id = "EC_LED_ID_BATTERY_LED";
+			led-pwms = <&pwm_y &pwm_w>;
+
+			color_off: color-off {
+				led-color = "LED_OFF";
+				led-values = <0 0>;
+			};
+
+			color_amber: color-amber {
+				led-color = "LED_AMBER";
+				br-color = "EC_LED_COLOR_AMBER";
+				led-values = <100 0>;
+			};
+
+			color_white: color-white {
+				led-color = "LED_WHITE";
+				br-color = "EC_LED_COLOR_WHITE";
+				led-values = <0 100>;
+			};
+		};
+	};
+};
+
+/* Amber "battery charging" LED */
+&pwm2 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm2_gpc4>;
+	pinctrl-names = "default";
+};
+
+/* White "battery full" LED */
+&pwm3 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm3_gp80>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/skyrim/skyrim/led_policy.dtsi b/zephyr/program/skyrim/skyrim/led_policy.dtsi
new file mode 100644
index 0000000000..fce5ad0251
--- /dev/null
+++ b/zephyr/program/skyrim/skyrim/led_policy.dtsi
@@ -0,0 +1,103 @@
+#include <dt-bindings/battery.h>
+
+/ {
+	led-colors {
+		compatible = "cros-ec,led-policy";
+
+		power-state-charge {
+			charge-state = "LED_PWRS_CHARGE";
+
+			color-0 {
+				led-color = <&color_amber>;
+			};
+		};
+
+		power-state-discharge-s0 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S0";
+			/* Battery percent range (> Low, <= Full) */
+			batt-lvl = <(BATTERY_LEVEL_LOW + 1) BATTERY_LEVEL_FULL>;
+
+			color-0 {
+				led-color = <&color_white>;
+			};
+		};
+
+		power-state-discharge-s0-batt-low {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S0";
+			/* Battery percent range (>= Empty, <= Low) */
+			batt-lvl = <BATTERY_LEVEL_EMPTY BATTERY_LEVEL_LOW>;
+
+			/* White 2 sec, off 1 sec */
+			color-0 {
+				led-color = <&color_white>;
+				period-ms = <2000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <1000>;
+			};
+		};
+
+		power-state-discharge-s3 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S3";
+
+			/* White 1 sec, off 1 sec */
+			color-0 {
+				led-color = <&color_white>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <1000>;
+			};
+		};
+
+		power-state-discharge-s5 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S5";
+
+			color-0 {
+				led-color = <&color_off>;
+			};
+		};
+
+		power-state-error {
+			charge-state = "LED_PWRS_ERROR";
+
+			/* Amber 1 sec, off 1 sec */
+			color-0 {
+				led-color = <&color_amber>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <1000>;
+			};
+		};
+
+		power-state-near-full {
+			charge-state = "LED_PWRS_CHARGE_NEAR_FULL";
+
+			color-0 {
+				led-color = <&color_white>;
+			};
+		};
+
+		power-state-forced-idle {
+			charge-state = "LED_PWRS_FORCED_IDLE";
+
+			/* Amber 2 sec, White 2 sec */
+			color-0 {
+				led-color = <&color_amber>;
+				period-ms = <2000>;
+			};
+			color-1 {
+				led-color = <&color_white>;
+				period-ms = <2000>;
+			};
+		};
+	};
+};
diff --git a/zephyr/program/skyrim/skyrim/motionsense.dtsi b/zephyr/program/skyrim/skyrim/motionsense.dtsi
new file mode 100644
index 0000000000..119c4aaf8e
--- /dev/null
+++ b/zephyr/program/skyrim/skyrim/motionsense.dtsi
@@ -0,0 +1,133 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/motionsense/utils.h>
+
+
+/ {
+	aliases {
+		/*
+		 * motion sense's <>_INT_EVENT is handled
+		 * by alias. Using the alias, each driver creates
+		 * its own <>_INT_EVENT.
+		 */
+		bmi3xx-int = &base_accel;
+		bma4xx-int = &lid_accel;
+	};
+
+	/*
+	 * Declare mutexes used by sensor drivers.
+	 * A mutex node is used to create an instance of mutex_t.
+	 * A mutex node is referenced by a sensor node if the
+	 * corresponding sensor driver needs to use the
+	 * instance of the mutex.
+	 */
+	motionsense-mutex {
+		compatible = "cros-ec,motionsense-mutex";
+		lid_mutex: lid-mutex {
+		};
+
+		mutex_bmi3xx: bmi3xx-mutex {
+		};
+	};
+
+	/*
+	 * Driver specific data. A driver-specific data can be shared with
+	 * different motion sensors while they are using the same driver.
+	 *
+	 * If a node's compatible starts with "cros-ec,accelgyro-", it is for
+	 * a common structure defined in accelgyro.h.
+	 * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for
+	 * "struct als_drv_data_t" in accelgyro.h
+	 */
+	motionsense-sensor-data {
+		bma4xx_data: bma4xx-drv-data {
+			compatible = "cros-ec,drvdata-bma4xx";
+			status = "okay";
+		};
+
+		bmi3xx_data: bmi3xx-drv-data {
+			compatible = "cros-ec,drvdata-bmi3xx";
+			status = "okay";
+		};
+	};
+
+	/*
+	 * List of motion sensors that creates motion_sensors array.
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
+	 * motion sensor IDs for lid angle calculation.
+	 */
+	motionsense-sensor {
+		lid_accel: lid-accel {
+			compatible = "cros-ec,bma4xx";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&lid_mutex>;
+			port = <&i2c_sensor>;
+			drv-data = <&bma4xx_data>;
+			rot-standard-ref = <&lid_rot_ref>;
+			default-range = <2>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(12500 | ROUND_UP_FLAG)>;
+					ec-rate = <100>;
+				};
+				ec-s3 {
+					odr = <(12500 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_accel: base-accel {
+			compatible = "cros-ec,bmi3xx-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&mutex_bmi3xx>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&bmi3xx_data>;
+
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(12500 | ROUND_UP_FLAG)>;
+					ec-rate = <100>;
+				};
+				ec-s3 {
+					odr = <(12500 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base-gyro {
+			compatible = "cros-ec,bmi3xx-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&mutex_bmi3xx>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&bmi3xx_data>;
+		};
+	};
+
+	motionsense-sensor-info {
+		compatible = "cros-ec,motionsense-sensor-info";
+
+		/*
+		 * list of GPIO interrupts that have to
+		 * be enabled at initial stage
+		 */
+		sensor-irqs = <&int_lid_accel &int_accel_gyro>;
+	};
+};
diff --git a/zephyr/program/skyrim/skyrim/project.conf b/zephyr/program/skyrim/skyrim/project.conf
new file mode 100644
index 0000000000..231e83f919
--- /dev/null
+++ b/zephyr/program/skyrim/skyrim/project.conf
@@ -0,0 +1,27 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Skyrim reference-board-specific Kconfig settings.
+CONFIG_BOARD_SKYRIM=y
+
+# CBI WP pin present
+CONFIG_PLATFORM_EC_EEPROM_CBI_WP=y
+
+# Skyrim is capable of sinking 100W
+CONFIG_PLATFORM_EC_PD_MAX_POWER_MW=100000
+CONFIG_PLATFORM_EC_PD_MAX_CURRENT_MA=5000
+CONFIG_PLATFORM_EC_PD_MAX_VOLTAGE_MV=20000
+
+# Enable alternative charger chip
+CONFIG_PLATFORM_EC_CHARGER_RUNTIME_CONFIG=y
+CONFIG_PLATFORM_EC_CHARGER_ISL9238C=y
+
+# Battery
+CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO=y
+
+# EC Host Commands
+CONFIG_PLATFORM_EC_HOSTCMD_AP_RESET=y
+
+# Sensors
+CONFIG_PLATFORM_EC_DYNAMIC_MOTION_SENSOR_COUNT=y
diff --git a/zephyr/program/skyrim/skyrim/project.overlay b/zephyr/program/skyrim/skyrim/project.overlay
new file mode 100644
index 0000000000..9aea108821
--- /dev/null
+++ b/zephyr/program/skyrim/skyrim/project.overlay
@@ -0,0 +1,179 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Skyrim program common DTS includes */
+#include "../adc.dtsi"
+#include "../fan.dtsi"
+#include "../gpio.dtsi"
+#include "../i2c.dtsi"
+#include "../interrupts.dtsi"
+#include "../keyboard.dtsi"
+#include "../usbc.dtsi"
+
+/* Skyrim project DTS includes*/
+#include "led_pins.dtsi"
+#include "led_policy.dtsi"
+#include "motionsense.dtsi"
+
+/* Skyrim overrides follow... */
+/ {
+	/* battery overrides */
+	batteries {
+		default_battery: aec_5477109 {
+			compatible = "aec,5477109", "battery-smart";
+		};
+		smp_l20m3pg1 {
+			compatible = "smp,l20m3pg1", "battery-smart";
+		};
+	};
+
+	named-gpios {
+		/* Skyrim-specific GPIO customizations */
+	};
+
+	gpio-interrupts {
+		int_lid_accel: lid_accel {
+			irq-pin = <&gpio_lid_accel_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "bma4xx_interrupt";
+		};
+	};
+
+	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
+		soc-pct2075 {
+			temp_host_high = <100>;
+			temp_host_halt = <105>;
+			temp_host_release_high = <80>;
+			temp_host_release_halt = <80>;
+			temp_fan_off = <35>;
+			temp_fan_max = <70>;
+			power-good-pin = <&gpio_pg_pwr_s5>;
+			sensor = <&soc_pct2075>;
+		};
+		amb-pct2075 {
+			power-good-pin = <&gpio_pg_pwr_s5>;
+			sensor = <&amb_pct2075>;
+		};
+	};
+
+	/*
+	 * Note this is expected to vary per-board, so we keep it in the overlay
+	 * files.
+	 */
+	skyrim-fw-config {
+		compatible = "cros-ec,cbi-fw-config";
+
+		form-factor {
+			enum-name = "FW_FORM_FACTOR";
+			start = <0>;
+			size = <1>;
+
+			ff-clamshell {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FF_CLAMSHELL";
+				value = <0>;
+			};
+			ff-convertible {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FF_CONVERTIBLE";
+				value = <1>;
+				default;
+			};
+		};
+		io-db {
+			enum-name = "FW_IO_DB";
+			start = <6>;
+			size = <2>;
+
+			io-db-ps8811-ps8818 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_IO_DB_PS8811_PS8818";
+				value = <0>;
+			};
+			io-db-none-anx7483 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_IO_DB_NONE_ANX7483";
+				value = <1>;
+				default;
+			};
+		};
+
+		/*
+		 * FW_CONFIG field to enable fan or not.
+		 */
+		fan {
+			enum-name = "FW_FAN";
+			start = <10>;
+			size = <1>;
+
+			no-fan {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FAN_NOT_PRESENT";
+				value = <0>;
+			};
+			fan-present {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FAN_PRESENT";
+				value = <1>;
+				/*
+				 * Set as default so that unprovisioned
+				 * configs will run the fan regardless.
+				 */
+				default;
+			};
+		};
+
+		charger-option {
+			enum-name = "FW_CHARGER";
+			start = <11>;
+			size = <2>;
+
+			charger-option-isl9241 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_CHARGER_ISL9241";
+				value = <0>;
+				default;
+			};
+			charger-option-isl9538 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_CHARGER_ISL9538";
+				value = <1>;
+			};
+		};
+	};
+
+	/* Rotation matrices for motion sensors. */
+	motionsense-rotation-ref {
+		compatible = "cros-ec,motionsense-rotation-ref";
+		lid_rot_ref: lid-rotation-ref {
+			mat33 = <0 (-1) 0
+				 1 0 0
+				 0 0 1>;
+		};
+
+		lid_rot_ref1: lid-rotation-ref1 {
+			mat33 = <0 1 0
+				 (-1) 0 0
+				 0 0 1>;
+		};
+
+		base_rot_ref: base-rotation-ref {
+			mat33 = <0 1 0
+				 (-1) 0 0
+				 0 0 1>;
+		};
+	};
+
+	ppc_port0: aoz1380 {
+		compatible = "aoz,aoz1380";
+		status = "okay";
+	};
+};
+
+/* i2c overrides */
+&i2c0_0 {
+	/delete-node/ nx20p348x@71;
+};
diff --git a/zephyr/program/skyrim/skyrim/skyrim_vif.xml b/zephyr/program/skyrim/skyrim/skyrim_vif.xml
new file mode 100644
index 0000000000..28d6f19049
--- /dev/null
+++ b/zephyr/program/skyrim/skyrim/skyrim_vif.xml
@@ -0,0 +1,346 @@
+<?xml version="1.0" encoding="utf-8"?>
+<vif:VIF xmlns:opt="http://usb.org/VendorInfoFileOptionalContent.xsd" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:vif="http://usb.org/VendorInfoFile.xsd">
+  <vif:VIF_Specification>3.22</vif:VIF_Specification>
+  <vif:VIF_App>
+    <vif:Vendor>USB-IF</vif:Vendor>
+    <vif:Name>VIF Editor</vif:Name>
+    <vif:Version>3.4.2.0</vif:Version>
+  </vif:VIF_App>
+  <vif:Vendor_Name>Google</vif:Vendor_Name>
+  <vif:Model_Part_Number>skyrim</vif:Model_Part_Number>
+  <vif:Product_Revision>FIX-ME</vif:Product_Revision>
+  <vif:TID>65535</vif:TID>
+  <vif:VIF_Product_Type value="0">Port Product</vif:VIF_Product_Type>
+  <vif:Certification_Type value="0">End Product</vif:Certification_Type>
+  <vif:Product>
+    <!--Product Level Content:-->
+  </vif:Product>
+  <vif:Component>
+    <!--Component 0: Port 0-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Component-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Port_Label>0</vif:Port_Label>
+    <vif:Connector_Type value="2">Type-C®</vif:Connector_Type>
+    <vif:USB4_Supported value="false" />
+    <vif:USB_PD_Support value="true" />
+    <vif:PD_Port_Type value="4">DRP</vif:PD_Port_Type>
+    <vif:Type_C_State_Machine value="2">DRP</vif:Type_C_State_Machine>
+    <vif:Port_Battery_Powered value="true" />
+    <vif:BC_1_2_Support value="3">Both</vif:BC_1_2_Support>
+    <vif:Captive_Cable value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;General PD-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Spec_Revision_Major value="3" />
+    <vif:PD_Spec_Revision_Minor value="0" />
+    <vif:PD_Spec_Version_Major value="2" />
+    <vif:PD_Spec_Version_Minor value="0" />
+    <vif:PD_Specification_Revision value="2">Revision 3</vif:PD_Specification_Revision>
+    <vif:SOP_Capable value="true" />
+    <vif:SOP_P_Capable value="true" />
+    <vif:SOP_PP_Capable value="true" />
+    <vif:SOP_P_Debug_Capable value="false" />
+    <vif:SOP_PP_Debug_Capable value="false" />
+    <vif:Manufacturer_Info_Supported_Port value="false" />
+    <vif:Chunking_Implemented_SOP value="true" />
+    <vif:Unchunked_Extended_Messages_Supported value="false" />
+    <vif:Security_Msgs_Supported_SOP value="false" />
+    <vif:Unconstrained_Power value="false" />
+    <vif:Num_Fixed_Batteries value="1" />
+    <vif:Num_Swappable_Battery_Slots value="0" />
+    <vif:ID_Header_Connector_Type_SOP value="2">USB Type-C® Receptacle</vif:ID_Header_Connector_Type_SOP>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Capabilities-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:USB_Comms_Capable value="true" />
+    <vif:DR_Swap_To_DFP_Supported value="true" />
+    <vif:DR_Swap_To_UFP_Supported value="false" />
+    <vif:VCONN_Swap_To_On_Supported value="true" />
+    <vif:VCONN_Swap_To_Off_Supported value="true" />
+    <vif:Responds_To_Discov_SOP_UFP value="true" />
+    <vif:Responds_To_Discov_SOP_DFP value="true" />
+    <vif:Attempts_Discov_SOP value="true" />
+    <vif:Power_Interruption_Available value="0">No Interruption Possible</vif:Power_Interruption_Available>
+    <vif:Data_Reset_Supported value="false" />
+    <vif:Enter_USB_Supported value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;USB Type-C®-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Type_C_Can_Act_As_Host value="true" />
+    <vif:Type_C_Can_Act_As_Device value="false" />
+    <vif:Type_C_Implements_Try_SRC value="true" />
+    <vif:Type_C_Implements_Try_SNK value="false" />
+    <vif:Type_C_Supports_Audio_Accessory value="false" />
+    <vif:Type_C_Is_VCONN_Powered_Accessory value="false" />
+    <vif:Type_C_Is_Debug_Target_SRC value="true" />
+    <vif:Type_C_Is_Debug_Target_SNK value="true" />
+    <vif:RP_Value value="1">1.5A</vif:RP_Value>
+    <vif:Type_C_Port_On_Hub value="false" />
+    <vif:Type_C_Power_Source value="2">Both</vif:Type_C_Power_Source>
+    <vif:Type_C_Sources_VCONN value="true" />
+    <vif:Type_C_Is_Alt_Mode_Controller value="true" />
+    <vif:Type_C_Is_Alt_Mode_Adapter value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Product Power-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Product_Total_Source_Power_mW value="22500">22500 mW</vif:Product_Total_Source_Power_mW>
+    <vif:Port_Source_Power_Type value="1">Shared</vif:Port_Source_Power_Type>
+    <vif:Port_Source_Power_Gang>CPower</vif:Port_Source_Power_Gang>
+    <vif:Port_Source_Power_Gang_Max_Power value="22500">22500 mW</vif:Port_Source_Power_Gang_Max_Power>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;USB Host-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Host_Supports_USB_Data value="true" />
+    <vif:Host_Speed value="1">USB 3.2 Gen 1x1</vif:Host_Speed>
+    <vif:Host_Contains_Captive_Retimer value="true" />
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:Host_Is_Embedded value="false" />
+    <vif:Host_Suspend_Supported value="true" />
+    <vif:Is_DFP_On_Hub value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Battery Charging 1.2-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:BC_1_2_Charging_Port_Type value="1">CDP</vif:BC_1_2_Charging_Port_Type>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Source-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Power_As_Source value="1500">1500 mW</vif:PD_Power_As_Source>
+    <vif:EPR_Supported_As_Src value="false" />
+    <vif:USB_Suspend_May_Be_Cleared value="true" />
+    <vif:Sends_Pings value="false" />
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="3">3A @ 5V</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <vif:Master_Port value="true" />
+    <vif:Has_Invariant_PDOs value="false" />
+    <vif:Num_Src_PDOs value="1" />
+    <vif:PD_OC_Protection value="false" />
+    <!--Bundle: SrcPdoList-->
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!--Source PDO 1-->
+        <vif:Src_PDO_Supply_Type value="0">Fixed</vif:Src_PDO_Supply_Type>
+        <vif:Src_PDO_Peak_Current value="0">100% IOC</vif:Src_PDO_Peak_Current>
+        <vif:Src_PDO_Voltage value="100">5000 mV</vif:Src_PDO_Voltage>
+        <vif:Src_PDO_Max_Current value="300">3000 mA</vif:Src_PDO_Max_Current>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Sink-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Power_As_Sink value="100000">100000 mW</vif:PD_Power_As_Sink>
+    <vif:EPR_Supported_As_Snk value="false" />
+    <vif:No_USB_Suspend_May_Be_Set value="true" />
+    <vif:GiveBack_May_Be_Set value="false" />
+    <vif:Higher_Capability_Set value="false" />
+    <vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source value="0">FR_Swap not supported</vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source>
+    <vif:Num_Snk_PDOs value="3" />
+    <!--Bundle: SnkPdoList-->
+    <vif:SnkPdoList>
+      <vif:SnkPDO>
+        <!--Sink PDO 1-->
+        <vif:Snk_PDO_Supply_Type value="0">Fixed</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Voltage value="100">5000 mV</vif:Snk_PDO_Voltage>
+        <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>
+      </vif:SnkPDO>
+      <vif:SnkPDO>
+        <!--Sink PDO 2-->
+        <vif:Snk_PDO_Supply_Type value="1">Battery</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Op_Power value="60">15000 mW</vif:Snk_PDO_Op_Power>
+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>
+        <vif:Snk_PDO_Max_Voltage value="400">20000 mV</vif:Snk_PDO_Max_Voltage>
+      </vif:SnkPDO>
+      <vif:SnkPDO>
+        <!--Sink PDO 3-->
+        <vif:Snk_PDO_Supply_Type value="2">Variable</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>
+        <vif:Snk_PDO_Max_Voltage value="400">20000 mV</vif:Snk_PDO_Max_Voltage>
+        <vif:Snk_PDO_Op_Current value="500">5000 mA</vif:Snk_PDO_Op_Current>
+      </vif:SnkPDO>
+    </vif:SnkPdoList>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Dual Role-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Accepts_PR_Swap_As_Src value="true" />
+    <vif:Accepts_PR_Swap_As_Snk value="true" />
+    <vif:Requests_PR_Swap_As_Src value="true" />
+    <vif:Requests_PR_Swap_As_Snk value="true" />
+    <vif:FR_Swap_Supported_As_Initial_Sink value="true" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;SOP Discover ID-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:XID_SOP value="0" />
+    <vif:Data_Capable_As_USB_Host_SOP value="true" />
+    <vif:Data_Capable_As_USB_Device_SOP value="false" />
+    <vif:Product_Type_UFP_SOP value="0">Undefined</vif:Product_Type_UFP_SOP>
+    <vif:Product_Type_DFP_SOP value="2">PDUSB Host</vif:Product_Type_DFP_SOP>
+    <vif:DFP_VDO_Port_Number value="0" />
+    <vif:Modal_Operation_Supported_SOP value="false" />
+    <vif:USB_VID_SOP value="6353">18D1</vif:USB_VID_SOP>
+    <vif:PID_SOP value="20575">505F</vif:PID_SOP>
+    <vif:bcdDevice_SOP value="0">0000</vif:bcdDevice_SOP>
+  </vif:Component>
+  <vif:Component>
+    <!--Component 1: Port 1-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Component-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Port_Label>1</vif:Port_Label>
+    <vif:Connector_Type value="2">Type-C®</vif:Connector_Type>
+    <vif:USB4_Supported value="false" />
+    <vif:USB_PD_Support value="true" />
+    <vif:PD_Port_Type value="4">DRP</vif:PD_Port_Type>
+    <vif:Type_C_State_Machine value="2">DRP</vif:Type_C_State_Machine>
+    <vif:Port_Battery_Powered value="true" />
+    <vif:BC_1_2_Support value="3">Both</vif:BC_1_2_Support>
+    <vif:Captive_Cable value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;General PD-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Spec_Revision_Major value="3" />
+    <vif:PD_Spec_Revision_Minor value="0" />
+    <vif:PD_Spec_Version_Major value="2" />
+    <vif:PD_Spec_Version_Minor value="0" />
+    <vif:PD_Specification_Revision value="2">Revision 3</vif:PD_Specification_Revision>
+    <vif:SOP_Capable value="true" />
+    <vif:SOP_P_Capable value="true" />
+    <vif:SOP_PP_Capable value="true" />
+    <vif:SOP_P_Debug_Capable value="false" />
+    <vif:SOP_PP_Debug_Capable value="false" />
+    <vif:Manufacturer_Info_Supported_Port value="false" />
+    <vif:Chunking_Implemented_SOP value="true" />
+    <vif:Unchunked_Extended_Messages_Supported value="false" />
+    <vif:Security_Msgs_Supported_SOP value="false" />
+    <vif:Unconstrained_Power value="false" />
+    <vif:Num_Fixed_Batteries value="1" />
+    <vif:Num_Swappable_Battery_Slots value="0" />
+    <vif:ID_Header_Connector_Type_SOP value="2">USB Type-C® Receptacle</vif:ID_Header_Connector_Type_SOP>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Capabilities-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:USB_Comms_Capable value="true" />
+    <vif:DR_Swap_To_DFP_Supported value="true" />
+    <vif:DR_Swap_To_UFP_Supported value="false" />
+    <vif:VCONN_Swap_To_On_Supported value="true" />
+    <vif:VCONN_Swap_To_Off_Supported value="true" />
+    <vif:Responds_To_Discov_SOP_UFP value="true" />
+    <vif:Responds_To_Discov_SOP_DFP value="true" />
+    <vif:Attempts_Discov_SOP value="true" />
+    <vif:Power_Interruption_Available value="0">No Interruption Possible</vif:Power_Interruption_Available>
+    <vif:Data_Reset_Supported value="false" />
+    <vif:Enter_USB_Supported value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;USB Type-C®-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Type_C_Can_Act_As_Host value="true" />
+    <vif:Type_C_Can_Act_As_Device value="false" />
+    <vif:Type_C_Implements_Try_SRC value="true" />
+    <vif:Type_C_Implements_Try_SNK value="false" />
+    <vif:Type_C_Supports_Audio_Accessory value="false" />
+    <vif:Type_C_Is_VCONN_Powered_Accessory value="false" />
+    <vif:Type_C_Is_Debug_Target_SRC value="true" />
+    <vif:Type_C_Is_Debug_Target_SNK value="true" />
+    <vif:RP_Value value="1">1.5A</vif:RP_Value>
+    <vif:Type_C_Port_On_Hub value="false" />
+    <vif:Type_C_Power_Source value="2">Both</vif:Type_C_Power_Source>
+    <vif:Type_C_Sources_VCONN value="true" />
+    <vif:Type_C_Is_Alt_Mode_Controller value="true" />
+    <vif:Type_C_Is_Alt_Mode_Adapter value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Product Power-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Product_Total_Source_Power_mW value="22500">22500 mW</vif:Product_Total_Source_Power_mW>
+    <vif:Port_Source_Power_Type value="1">Shared</vif:Port_Source_Power_Type>
+    <vif:Port_Source_Power_Gang>CPower</vif:Port_Source_Power_Gang>
+    <vif:Port_Source_Power_Gang_Max_Power value="22500">22500 mW</vif:Port_Source_Power_Gang_Max_Power>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;USB Host-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Host_Supports_USB_Data value="true" />
+    <vif:Host_Speed value="1">USB 3.2 Gen 1x1</vif:Host_Speed>
+    <vif:Host_Contains_Captive_Retimer value="true" />
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:Host_Is_Embedded value="false" />
+    <vif:Host_Suspend_Supported value="true" />
+    <vif:Is_DFP_On_Hub value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Battery Charging 1.2-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:BC_1_2_Charging_Port_Type value="1">CDP</vif:BC_1_2_Charging_Port_Type>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Source-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Power_As_Source value="15000">15000 mW</vif:PD_Power_As_Source>
+    <vif:EPR_Supported_As_Src value="false" />
+    <vif:USB_Suspend_May_Be_Cleared value="true" />
+    <vif:Sends_Pings value="false" />
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="3">3A @ 5V</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <vif:Master_Port value="true" />
+    <vif:Has_Invariant_PDOs value="false" />
+    <vif:Num_Src_PDOs value="1" />
+    <vif:PD_OC_Protection value="false" />
+    <!--Bundle: SrcPdoList-->
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!--Source PDO 1-->
+        <vif:Src_PDO_Supply_Type value="0">Fixed</vif:Src_PDO_Supply_Type>
+        <vif:Src_PDO_Peak_Current value="0">100% IOC</vif:Src_PDO_Peak_Current>
+        <vif:Src_PDO_Voltage value="100">5000 mV</vif:Src_PDO_Voltage>
+        <vif:Src_PDO_Max_Current value="300">3000 mA</vif:Src_PDO_Max_Current>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Sink-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Power_As_Sink value="100000">100000 mW</vif:PD_Power_As_Sink>
+    <vif:EPR_Supported_As_Snk value="false" />
+    <vif:No_USB_Suspend_May_Be_Set value="true" />
+    <vif:GiveBack_May_Be_Set value="false" />
+    <vif:Higher_Capability_Set value="false" />
+    <vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source value="0">FR_Swap not supported</vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source>
+    <vif:Num_Snk_PDOs value="3" />
+    <!--Bundle: SnkPdoList-->
+    <vif:SnkPdoList>
+      <vif:SnkPDO>
+        <!--Sink PDO 1-->
+        <vif:Snk_PDO_Supply_Type value="0">Fixed</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Voltage value="100">5000 mV</vif:Snk_PDO_Voltage>
+        <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>
+      </vif:SnkPDO>
+      <vif:SnkPDO>
+        <!--Sink PDO 2-->
+        <vif:Snk_PDO_Supply_Type value="1">Battery</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Op_Power value="60">15000 mW</vif:Snk_PDO_Op_Power>
+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>
+        <vif:Snk_PDO_Max_Voltage value="400">20000 mV</vif:Snk_PDO_Max_Voltage>
+      </vif:SnkPDO>
+      <vif:SnkPDO>
+        <!--Sink PDO 3-->
+        <vif:Snk_PDO_Supply_Type value="2">Variable</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>
+        <vif:Snk_PDO_Max_Voltage value="400">20000 mV</vif:Snk_PDO_Max_Voltage>
+        <vif:Snk_PDO_Op_Current value="500">5000 mA</vif:Snk_PDO_Op_Current>
+      </vif:SnkPDO>
+    </vif:SnkPdoList>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Dual Role-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Accepts_PR_Swap_As_Src value="true" />
+    <vif:Accepts_PR_Swap_As_Snk value="true" />
+    <vif:Requests_PR_Swap_As_Src value="true" />
+    <vif:Requests_PR_Swap_As_Snk value="true" />
+    <vif:FR_Swap_Supported_As_Initial_Sink value="true" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;SOP Discover ID-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:XID_SOP value="0" />
+    <vif:Data_Capable_As_USB_Host_SOP value="true" />
+    <vif:Data_Capable_As_USB_Device_SOP value="false" />
+    <vif:Product_Type_UFP_SOP value="0">Undefined</vif:Product_Type_UFP_SOP>
+    <vif:Product_Type_DFP_SOP value="2">PDUSB Host</vif:Product_Type_DFP_SOP>
+    <vif:DFP_VDO_Port_Number value="1" />
+    <vif:Modal_Operation_Supported_SOP value="false" />
+    <vif:USB_VID_SOP value="6353">18D1</vif:USB_VID_SOP>
+    <vif:PID_SOP value="20575">505F</vif:PID_SOP>
+    <vif:bcdDevice_SOP value="0">0000</vif:bcdDevice_SOP>
+  </vif:Component>
+</vif:VIF>
diff --git a/zephyr/program/skyrim/skyrim/src/alt_charger.c b/zephyr/program/skyrim/skyrim/src/alt_charger.c
new file mode 100644
index 0000000000..e6e5076c09
--- /dev/null
+++ b/zephyr/program/skyrim/skyrim/src/alt_charger.c
@@ -0,0 +1,37 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charger_chips.h"
+#include "common.h"
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+#include "hooks.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/logging/log.h>
+
+#ifdef CONFIG_ZTEST
+#undef CHG_ENABLE_ALTERNATE
+void chg_enable_alternate_test(int port);
+#define CHG_ENABLE_ALTERNATE(x) chg_enable_alternate_test(x)
+#endif /* CONFIG_ZTEST */
+
+LOG_MODULE_DECLARE(skyrim, CONFIG_SKYRIM_LOG_LEVEL);
+
+test_export_static void alt_charger_init(void)
+{
+	int ret;
+	uint32_t val;
+
+	ret = cros_cbi_get_fw_config(FW_CHARGER, &val);
+	if (ret != 0) {
+		LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_CHARGER);
+		return;
+	}
+
+	if (val == FW_CHARGER_ISL9538)
+		CHG_ENABLE_ALTERNATE(0);
+}
+DECLARE_HOOK(HOOK_INIT, alt_charger_init, HOOK_PRIO_POST_FIRST);
diff --git a/zephyr/program/skyrim/skyrim/src/fan.c b/zephyr/program/skyrim/skyrim/src/fan.c
new file mode 100644
index 0000000000..a33a2dc151
--- /dev/null
+++ b/zephyr/program/skyrim/skyrim/src/fan.c
@@ -0,0 +1,62 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+#include "fan.h"
+#include "gpio/gpio.h"
+#include "hooks.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(skyrim, CONFIG_SKYRIM_LOG_LEVEL);
+
+/*
+ * Skyrim fan support
+ */
+test_export_static void fan_init(void)
+{
+	int ret;
+	uint32_t val;
+	uint32_t board_version;
+	/*
+	 * Retrieve the fan config.
+	 */
+	ret = cros_cbi_get_fw_config(FW_FAN, &val);
+	if (ret != 0) {
+		LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_FAN);
+		return;
+	}
+
+	ret = cbi_get_board_version(&board_version);
+	if (ret != EC_SUCCESS) {
+		LOG_ERR("Error retrieving CBI board version");
+		return;
+	}
+
+	if ((board_version >= 3) && (val != FW_FAN_PRESENT)) {
+		/* Disable the fan */
+		fan_set_count(0);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, fan_init, HOOK_PRIO_POST_FIRST);
+
+/*
+ * Pcore OCP support
+ * Note: early boards should note enable this interrupt as they are not
+ * correctly configured for it.
+ */
+__override bool board_supports_pcore_ocp(void)
+{
+	uint32_t board_version;
+
+	if (cbi_get_board_version(&board_version) == EC_SUCCESS &&
+	    board_version > 3)
+		return true;
+
+	return false;
+}
diff --git a/zephyr/program/skyrim/skyrim/src/form_factor.c b/zephyr/program/skyrim/skyrim/src/form_factor.c
new file mode 100644
index 0000000000..7a240a3447
--- /dev/null
+++ b/zephyr/program/skyrim/skyrim/src/form_factor.c
@@ -0,0 +1,62 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "accelgyro.h"
+#include "common.h"
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "motionsense_sensors.h"
+#include "tablet_mode.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(skyrim, CONFIG_SKYRIM_LOG_LEVEL);
+
+/*
+ * Mainboard orientation support.
+ */
+
+#define ALT_MAT SENSOR_ROT_STD_REF_NAME(DT_NODELABEL(lid_rot_ref1))
+#define LID_ACCEL SENSOR_ID(DT_NODELABEL(lid_accel))
+
+static void form_factor_init(void)
+{
+	int ret;
+	uint32_t val;
+	/*
+	 * If the board version >=4
+	 * use ver1 rotation matrix.
+	 */
+	ret = cbi_get_board_version(&val);
+	if (ret == EC_SUCCESS && val >= 4) {
+		LOG_INF("Switching to ver1 lid");
+		motion_sensors[LID_ACCEL].rot_standard_ref = &ALT_MAT;
+	}
+}
+DECLARE_HOOK(HOOK_INIT, form_factor_init, HOOK_PRIO_POST_I2C);
+
+test_export_static void clamshell_init(void)
+{
+	int ret;
+	uint32_t val;
+
+	/* Check the form factor from CBI */
+	ret = cros_cbi_get_fw_config(FW_FORM_FACTOR, &val);
+	if (ret != 0) {
+		LOG_ERR("Cannot get FW_FORM_FACTOR");
+		return;
+	}
+
+	if (val == FW_FF_CLAMSHELL) {
+		motion_sensor_count = 0;
+		gpio_disable_dt_interrupt(
+			GPIO_INT_FROM_NODELABEL(int_accel_gyro));
+		gmr_tablet_switch_disable();
+	}
+}
+DECLARE_HOOK(HOOK_INIT, clamshell_init, HOOK_PRIO_POST_DEFAULT);
diff --git a/zephyr/program/skyrim/skyrim/src/keyboard.c b/zephyr/program/skyrim/skyrim/src/keyboard.c
new file mode 100644
index 0000000000..e261321e86
--- /dev/null
+++ b/zephyr/program/skyrim/skyrim/src/keyboard.c
@@ -0,0 +1,29 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+
+static const struct ec_response_keybd_config skyrim_kb = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &skyrim_kb;
+}
diff --git a/zephyr/program/skyrim/skyrim/src/ppc_config.c b/zephyr/program/skyrim/skyrim/src/ppc_config.c
new file mode 100644
index 0000000000..5ce6403062
--- /dev/null
+++ b/zephyr/program/skyrim/skyrim/src/ppc_config.c
@@ -0,0 +1,49 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Skyrim board-specific PPC code */
+
+#include "driver/ppc/aoz1380_public.h"
+#include "driver/ppc/nx20p348x.h"
+#include "usbc_ppc.h"
+
+#include <zephyr/drivers/gpio.h>
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/*
+ * In the AOZ1380 PPC, there are no programmable features.  We use
+ * the attached NCT3807 to control a GPIO to indicate 1A5 or 3A0
+ * current limits.
+ */
+int board_aoz1380_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	int rv = EC_SUCCESS;
+
+	if (port != 0)
+		return EC_ERROR_INVAL;
+
+	rv = gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(ioex_usb_c0_ilim_3a_en),
+			     (rp == TYPEC_RP_3A0) ? 1 : 0);
+
+	return rv;
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		aoz1380_interrupt(0);
+		break;
+
+	case GPIO_USB_C1_PPC_INT_ODL:
+		nx20p348x_interrupt(1);
+		break;
+
+	default:
+		break;
+	}
+}
diff --git a/zephyr/program/skyrim/skyrim/src/usb_mux_config.c b/zephyr/program/skyrim/skyrim/src/usb_mux_config.c
new file mode 100644
index 0000000000..2351144849
--- /dev/null
+++ b/zephyr/program/skyrim/skyrim/src/usb_mux_config.c
@@ -0,0 +1,143 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Skyrim board-specific USB-C mux configuration */
+
+#include "console.h"
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+#include "driver/retimer/anx7483_public.h"
+#include "hooks.h"
+#include "ioexpander.h"
+#include "usb_mux.h"
+#include "usbc/usb_muxes.h"
+#include "ztest/usb_mux_config.h"
+
+#include <zephyr/drivers/gpio.h>
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/*
+ * USB C0 (general) and C1 (just ANX DB) use IOEX pins to
+ * indicate flipped polarity to a protection switch.
+ */
+test_export_static int ioex_set_flip(int port, mux_state_t mux_state)
+{
+	if (port == 0) {
+		if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
+			gpio_pin_set_dt(
+				GPIO_DT_FROM_NODELABEL(ioex_usb_c0_sbu_flip),
+				1);
+		else
+			gpio_pin_set_dt(
+				GPIO_DT_FROM_NODELABEL(ioex_usb_c0_sbu_flip),
+				0);
+	} else {
+		if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
+			gpio_pin_set_dt(
+				GPIO_DT_FROM_NODELABEL(ioex_usb_c1_sbu_flip),
+				1);
+		else
+			gpio_pin_set_dt(
+				GPIO_DT_FROM_NODELABEL(ioex_usb_c1_sbu_flip),
+				0);
+	}
+
+	return EC_SUCCESS;
+}
+
+int board_anx7483_c0_mux_set(const struct usb_mux *me, mux_state_t mux_state)
+{
+	/* Set the SBU polarity mux */
+	RETURN_ERROR(ioex_set_flip(me->usb_port, mux_state));
+
+	return anx7483_set_default_tuning(me, mux_state);
+}
+
+int board_anx7483_c1_mux_set(const struct usb_mux *me, mux_state_t mux_state)
+{
+	bool flipped = mux_state & USB_PD_MUX_POLARITY_INVERTED;
+
+	/* Set the SBU polarity mux */
+	RETURN_ERROR(ioex_set_flip(me->usb_port, mux_state));
+
+	/* Remove flipped from the state for easier compraisons */
+	mux_state = mux_state & ~USB_PD_MUX_POLARITY_INVERTED;
+
+	RETURN_ERROR(anx7483_set_default_tuning(me, mux_state));
+
+	if (mux_state == USB_PD_MUX_USB_ENABLED) {
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX1,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX2,
+					    ANX7483_EQ_SETTING_12_5DB));
+	} else if (mux_state == USB_PD_MUX_DP_ENABLED) {
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX1,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX2,
+					    ANX7483_EQ_SETTING_12_5DB));
+	} else if (mux_state == USB_PD_MUX_DOCK && !flipped) {
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX1,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX2,
+					    ANX7483_EQ_SETTING_12_5DB));
+	} else if (mux_state == USB_PD_MUX_DOCK && flipped) {
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX1,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX2,
+					    ANX7483_EQ_SETTING_12_5DB));
+	}
+
+	return EC_SUCCESS;
+}
+
+int board_c1_ps8818_mux_set(const struct usb_mux *me, mux_state_t mux_state)
+{
+	CPRINTSUSB("C1: PS8818 mux using default tuning");
+
+	/* Once a DP connection is established, we need to set IN_HPD */
+	if (mux_state & USB_PD_MUX_DP_ENABLED)
+		ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 1);
+	else
+		ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 0);
+
+	return 0;
+}
+
+test_export_static void setup_mux(void)
+{
+	uint32_t val;
+
+	if (cros_cbi_get_fw_config(FW_IO_DB, &val) != 0)
+		CPRINTSUSB("Error finding FW_DB_IO in CBI FW_CONFIG");
+	/* Val will have our dts default on error, so continue setup */
+
+	if (val == FW_IO_DB_PS8811_PS8818) {
+		CPRINTSUSB("C1: Setting PS8818 mux");
+		USB_MUX_ENABLE_ALTERNATIVE(usb_mux_chain_ps8818_port1);
+	} else if (val == FW_IO_DB_NONE_ANX7483) {
+		CPRINTSUSB("C1: Setting ANX7483 mux");
+	} else {
+		CPRINTSUSB("Unexpected DB_IO board: %d", val);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, setup_mux, HOOK_PRIO_INIT_I2C);
diff --git a/zephyr/program/skyrim/src/common.c b/zephyr/program/skyrim/src/common.c
new file mode 100644
index 0000000000..af82139c1b
--- /dev/null
+++ b/zephyr/program/skyrim/src/common.c
@@ -0,0 +1,8 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(skyrim, CONFIG_SKYRIM_LOG_LEVEL);
diff --git a/zephyr/program/skyrim/src/power_signals.c b/zephyr/program/skyrim/src/power_signals.c
new file mode 100644
index 0000000000..ede5d1ec75
--- /dev/null
+++ b/zephyr/program/skyrim/src/power_signals.c
@@ -0,0 +1,294 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifdef CONFIG_ZTEST
+#define CHARGER_SOLO 0
+#endif
+
+#include "ap_power/ap_power.h"
+#include "charger.h"
+#include "chipset.h"
+#include "config.h"
+#include "driver/amd_stb.h"
+#include "gpio/gpio_int.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "ioexpander.h"
+#include "power.h"
+#include "power/amd_x86.h"
+#include "throttle_ap.h"
+#include "timer.h"
+
+/* Power Signal Input List */
+/* TODO: b/218904113: Convert to using Zephyr GPIOs */
+const struct power_signal_info power_signal_list[] = {
+	[X86_SLP_S3_N] = {
+		.gpio = GPIO_PCH_SLP_S3_L,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "SLP_S3_DEASSERTED",
+	},
+	[X86_SLP_S5_N] = {
+		.gpio = GPIO_PCH_SLP_S5_L,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "SLP_S5_DEASSERTED",
+	},
+	[X86_S0_PGOOD] = {
+		.gpio = GPIO_S0_PGOOD,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "S0_PGOOD",
+	},
+	[X86_S5_PGOOD] = {
+		.gpio = GPIO_S5_PGOOD,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "S5_PGOOD",
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
+
+static void handle_prochot(bool asserted, void *data);
+
+const struct prochot_cfg prochot_cfg = {
+	.gpio_prochot_in = GPIO_CPU_PROCHOT,
+	.callback = handle_prochot,
+};
+
+/* Chipset hooks */
+test_export_static void
+baseboard_suspend_change(struct ap_power_ev_callback *cb,
+			 struct ap_power_ev_data data)
+{
+	switch (data.event) {
+	default:
+		return;
+
+	case AP_POWER_SUSPEND:
+		/* Disable display backlight */
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_disable_disp_bl),
+				1);
+		break;
+
+	case AP_POWER_SHUTDOWN:
+		/* Retimer disable */
+		ioex_set_level(IOEX_USB_A1_RETIMER_EN, 0);
+		break;
+
+	case AP_POWER_RESUME:
+		/* Enable retimer and display backlight */
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_disable_disp_bl),
+				0);
+		break;
+
+	case AP_POWER_STARTUP:
+		ioex_set_level(IOEX_USB_A1_RETIMER_EN, 1);
+		/* Any retimer tuning can be done after the retimer turns on */
+		break;
+	}
+}
+
+static void check_charger_prochot(void)
+{
+	print_charger_prochot(CHARGER_SOLO);
+}
+DECLARE_DEFERRED(check_charger_prochot);
+
+static void handle_prochot(bool asserted, void *data)
+{
+	if (asserted) {
+		ccprints("Charger prochot asserted externally");
+		hook_call_deferred(&check_charger_prochot_data, 0);
+	} else
+		ccprints("Charger prochot deasserted externally");
+}
+
+test_export_static void baseboard_init(void)
+{
+	static struct ap_power_ev_callback cb;
+	const struct gpio_dt_spec *gpio_ec_sfh_int_h =
+		GPIO_DT_FROM_NODELABEL(gpio_ec_sfh_int_h);
+	const struct gpio_dt_spec *gpio_sfh_ec_int_h =
+		GPIO_DT_FROM_NODELABEL(gpio_sfh_ec_int_h);
+
+	/* Setup a suspend/resume callback */
+	ap_power_ev_init_callback(&cb, baseboard_suspend_change,
+				  AP_POWER_STARTUP | AP_POWER_SHUTDOWN |
+					  AP_POWER_RESUME | AP_POWER_SUSPEND);
+	ap_power_ev_add_callback(&cb);
+	/* Enable Power Group interrupts. */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pg_groupc_s0));
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pg_lpddr_s0));
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pg_lpddr_s3));
+
+	/* Enable thermtrip interrupt */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_soc_thermtrip));
+
+	/* Enable prochot interrupt */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_prochot));
+	throttle_ap_config_prochot(&prochot_cfg);
+
+	/* Enable STB dumping interrupt */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_stb_dump));
+	amd_stb_dump_init(gpio_ec_sfh_int_h, gpio_sfh_ec_int_h);
+}
+DECLARE_HOOK(HOOK_INIT, baseboard_init, HOOK_PRIO_POST_I2C);
+
+/**
+ * b/227296844: On G3->S5, wait for RSMRST_L to be deasserted before asserting
+ * PCH_PWRBTN_L.  This can be as long as ~65ms after cold boot.  Then wait an
+ * additional delay of T1a defined in the EDS before changing the power button.
+ */
+#define RSMRST_WAIT_DELAY 70
+#define EDS_PWR_BTN_RSMRST_T1A_DELAY 16
+void board_pwrbtn_to_pch(int level)
+{
+	timestamp_t start;
+
+	/* Add delay for G3 exit if asserting PWRBTN_L and RSMRST_L is low. */
+	if (!level &&
+	    !gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_soc_rsmrst_l))) {
+		start = get_time();
+		do {
+			usleep(500);
+			if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(
+				    gpio_ec_soc_rsmrst_l)))
+				break;
+		} while (time_since32(start) < (RSMRST_WAIT_DELAY * MSEC));
+
+		if (!gpio_pin_get_dt(
+			    GPIO_DT_FROM_NODELABEL(gpio_ec_soc_rsmrst_l)))
+			ccprints("Error pwrbtn: RSMRST_L still low");
+
+		msleep(EDS_PWR_BTN_RSMRST_T1A_DELAY);
+	}
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_soc_pwr_btn_l), level);
+}
+
+/* Note: signal parameter unused */
+void baseboard_set_soc_pwr_pgood(enum gpio_signal unused)
+{
+	gpio_pin_set_dt(
+		GPIO_DT_FROM_NODELABEL(gpio_ec_soc_pwr_good),
+		gpio_pin_get_dt(
+			GPIO_DT_FROM_NODELABEL(gpio_en_pwr_pcore_s0_r)) &&
+			gpio_pin_get_dt(
+				GPIO_DT_FROM_NODELABEL(gpio_pg_lpddr5_s0_od)) &&
+			gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_s0_pgood)));
+}
+
+/* TODO(b/248284045): Remove when boards switch to new chip */
+#define MP2845A_I2C_ADDR_FLAGS 0x20
+#define MP2854A_MFR_VOUT_CMPS_MAX_REG 0x69
+#define MP2854A_MFR_LOW_PWR_SEL BIT(12)
+
+__overridable bool board_supports_pcore_ocp(void)
+{
+	return true;
+}
+
+static void setup_mp2845(void)
+{
+	if (i2c_update16(chg_chips[CHARGER_SOLO].i2c_port,
+			 MP2845A_I2C_ADDR_FLAGS, MP2854A_MFR_VOUT_CMPS_MAX_REG,
+			 MP2854A_MFR_LOW_PWR_SEL, MASK_CLR))
+		ccprints("Failed to send mp2845 workaround");
+
+	if (board_supports_pcore_ocp())
+		gpio_enable_dt_interrupt(
+			GPIO_INT_FROM_NODELABEL(int_soc_pcore_ocp));
+}
+DECLARE_DEFERRED(setup_mp2845);
+
+void baseboard_s0_pgood(enum gpio_signal signal)
+{
+	baseboard_set_soc_pwr_pgood(signal);
+
+	/* Chain off power signal interrupt handler for PG_PCORE_S0_R_OD */
+	power_signal_interrupt(signal);
+
+	/* Set up the MP2845, which is powered in S0 */
+	if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_s0_pgood)))
+		hook_call_deferred(&setup_mp2845_data, 50 * MSEC);
+	else
+		gpio_disable_dt_interrupt(
+			GPIO_INT_FROM_NODELABEL(int_soc_pcore_ocp));
+}
+
+/* Note: signal parameter unused */
+void baseboard_set_en_pwr_pcore(enum gpio_signal unused)
+{
+	/*
+	 * EC must AND signals PG_LPDDR5_S3_OD, PG_GROUPC_S0_OD, and
+	 * EN_PWR_S0_R
+	 */
+	gpio_pin_set_dt(
+		GPIO_DT_FROM_NODELABEL(gpio_en_pwr_pcore_s0_r),
+		gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_pg_lpddr5_s3_od)) &&
+			gpio_pin_get_dt(
+				GPIO_DT_FROM_NODELABEL(gpio_pg_groupc_s0_od)) &&
+			gpio_pin_get_dt(
+				GPIO_DT_FROM_NODELABEL(gpio_en_pwr_s0_r)));
+
+	/* Update EC_SOC_PWR_GOOD based on our results */
+	baseboard_set_soc_pwr_pgood(unused);
+}
+
+void baseboard_en_pwr_s0(enum gpio_signal signal)
+{
+	/* EC must AND signals SLP_S3_L and PG_PWR_S5 */
+	gpio_pin_set_dt(
+		GPIO_DT_FROM_NODELABEL(gpio_en_pwr_s0_r),
+		gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_slp_s3_l)) &&
+			gpio_pin_get_dt(
+				GPIO_DT_FROM_NODELABEL(gpio_pg_pwr_s5)));
+
+	/* Change EN_PWR_PCORE_S0_R if needed*/
+	baseboard_set_en_pwr_pcore(signal);
+
+	/* Now chain off to the normal power signal interrupt handler. */
+	power_signal_interrupt(signal);
+}
+#ifdef CONFIG_BOARD_USB_HUB_RESET
+void baseboard_enable_hub(void)
+{
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_hub_rst), 0);
+}
+DECLARE_DEFERRED(baseboard_enable_hub);
+#endif /* CONFIG_BOARD_USB_HUB_RESET */
+
+void baseboard_s5_pgood(enum gpio_signal signal)
+{
+#ifdef CONFIG_BOARD_USB_HUB_RESET
+	/* We must enable the USB hub at least 30ms after S5 PGOOD */
+	if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_pg_pwr_s5)))
+		hook_call_deferred(&baseboard_enable_hub_data, 30 * MSEC);
+	else
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_hub_rst), 1);
+#endif /* CONFIG_BOARD_USB_HUB_RESET */
+
+	/* Continue to our signal AND-ing and power interrupt */
+	baseboard_en_pwr_s0(signal);
+}
+
+void baseboard_set_en_pwr_s3(enum gpio_signal signal)
+{
+	/* EC must enable PWR_S3 when SLP_S5_L goes high, disable on low */
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pwr_s3),
+			gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_slp_s5_l)));
+
+	/* Chain off the normal power signal interrupt handler */
+	power_signal_interrupt(signal);
+}
+
+void baseboard_soc_thermtrip(enum gpio_signal signal)
+{
+	ccprints("SoC thermtrip reported, shutting down");
+	chipset_force_shutdown(CHIPSET_SHUTDOWN_THERMAL);
+}
+
+void baseboard_soc_pcore_ocp(enum gpio_signal signal)
+{
+	ccprints("SoC Pcore OCP reported, shutting down");
+	chipset_force_shutdown(CHIPSET_SHUTDOWN_BOARD_CUSTOM);
+}
diff --git a/zephyr/program/skyrim/src/stt.c b/zephyr/program/skyrim/src/stt.c
new file mode 100644
index 0000000000..e12f064fa7
--- /dev/null
+++ b/zephyr/program/skyrim/src/stt.c
@@ -0,0 +1,39 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Support code for STT temperature reporting */
+
+#include "chipset.h"
+#include "temp_sensor/f75303.h"
+#include "temp_sensor/pct2075.h"
+#include "temp_sensor/temp_sensor.h"
+
+int board_get_soc_temp_mk(int *temp_mk)
+{
+	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+#ifdef CONFIG_TEMP_SENSOR_PCT2075
+	return pct2075_get_val_mk(PCT2075_SENSOR_ID(DT_NODELABEL(soc_pct2075)),
+				  temp_mk);
+#else
+	return f75303_get_val_mk(F75303_SENSOR_ID(DT_NODELABEL(f75303_local)),
+				 temp_mk);
+#endif
+}
+
+int board_get_ambient_temp_mk(int *temp_mk)
+{
+	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+#ifdef CONFIG_TEMP_SENSOR_PCT2075
+	return pct2075_get_val_mk(PCT2075_SENSOR_ID(DT_NODELABEL(amb_pct2075)),
+				  temp_mk);
+#else
+	return f75303_get_val_mk(
+		F75303_SENSOR_ID(DT_NODELABEL(f75303_remote_1)), temp_mk);
+#endif
+}
diff --git a/zephyr/program/skyrim/src/usb_pd_policy.c b/zephyr/program/skyrim/src/usb_pd_policy.c
new file mode 100644
index 0000000000..745d95bc00
--- /dev/null
+++ b/zephyr/program/skyrim/src/usb_pd_policy.c
@@ -0,0 +1,93 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Shared USB-C policy for Zork boards */
+
+#include "charge_manager.h"
+#include "chipset.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "ioexpander.h"
+#include "system.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#include <zephyr/drivers/gpio.h>
+
+int pd_check_vconn_swap(int port)
+{
+	/*
+	 * Do not allow vconn swap 5V rail is off
+	 * S5_PGOOD depends on PG_PP5000_S5 being asserted,
+	 * so GPIO_S5_PGOOD is a reasonable proxy for PP5000_S5
+	 */
+	return gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_pg_pwr_s5));
+}
+
+void pd_power_supply_reset(int port)
+{
+	/* Disable VBUS. */
+	ppc_vbus_source_enable(port, 0);
+
+	/* Enable discharge if we were previously sourcing 5V */
+	if (IS_ENABLED(CONFIG_USB_PD_DISCHARGE))
+		pd_set_vbus_discharge(port, 1);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	/* Disable charging. */
+	rv = ppc_vbus_sink_enable(port, 0);
+	if (rv)
+		return rv;
+
+	if (IS_ENABLED(CONFIG_USB_PD_DISCHARGE))
+		pd_set_vbus_discharge(port, 0);
+
+	/* Provide Vbus. */
+	rv = ppc_vbus_source_enable(port, 1);
+	if (rv)
+		return rv;
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+__override int board_pd_set_frs_enable(int port, int enable)
+{
+	/*
+	 * Both PPCs require the FRS GPIO to be set as soon as FRS capability
+	 * is established.
+	 */
+	if (port == 0)
+		ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN, enable);
+	else
+		ioex_set_level(IOEX_USB_C1_TCPC_FASTSW_CTL_EN, enable);
+
+	return EC_SUCCESS;
+}
+
+/* Used by Vbus discharge common code with CONFIG_USB_PD_DISCHARGE */
+int board_vbus_source_enabled(int port)
+{
+	return tcpm_get_src_ctrl(port);
+}
+
+/* Used by USB charger task with CONFIG_USB_PD_5V_EN_CUSTOM */
+int board_is_sourcing_vbus(int port)
+{
+	return board_vbus_source_enabled(port);
+}
diff --git a/zephyr/program/skyrim/src/usbc_config.c b/zephyr/program/skyrim/src/usbc_config.c
new file mode 100644
index 0000000000..922e863027
--- /dev/null
+++ b/zephyr/program/skyrim/src/usbc_config.c
@@ -0,0 +1,389 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Skyrim family-specific USB-C configuration */
+
+#include "battery_fuel_gauge.h"
+#include "charge_manager.h"
+#include "charge_ramp.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+#include "driver/bc12/pi3usb9201.h"
+#include "driver/charger/isl923x_public.h"
+#include "driver/charger/isl9241.h"
+#include "driver/ppc/nx20p348x.h"
+#include "driver/retimer/anx7483_public.h"
+#include "driver/retimer/ps8811.h"
+#include "driver/retimer/ps8818_public.h"
+#include "driver/tcpm/nct38xx.h"
+#include "driver/usb_mux/amd_fp6.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "ioexpander.h"
+#include "power.h"
+#include "usb_mux.h"
+#include "usb_pd_tcpm.h"
+#include "usbc/usb_muxes.h"
+#include "usbc_ppc.h"
+
+#include <zephyr/drivers/gpio.h>
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/* USB-A ports */
+enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT };
+
+/* USB-C ports */
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
+BUILD_ASSERT(USBC_PORT_COUNT == CONFIG_USB_PD_PORT_MAX_COUNT);
+
+static void reset_nct38xx_port(int port);
+
+static void usbc_interrupt_init(void)
+{
+	/* Enable PPC interrupts. */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_ppc));
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_ppc));
+
+#ifdef CONFIG_PLATFORM_EC_USB_CHARGER
+	/* Enable BC 1.2 interrupts */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_bc12));
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_bc12));
+#endif
+
+	/* Enable SBU fault interrupts */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_sbu_fault));
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_sbu_fault));
+}
+DECLARE_HOOK(HOOK_INIT, usbc_interrupt_init, HOOK_PRIO_POST_I2C);
+
+static void usb_fault_interrupt_init(void)
+{
+	/* Enable USB fault interrupts when we hit S5 */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_hub_fault));
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_a0_fault));
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_a1_fault));
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, usb_fault_interrupt_init, HOOK_PRIO_DEFAULT);
+
+static void usb_fault_interrupt_disable(void)
+{
+	/* Disable USB fault interrupts leaving S5 */
+	gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_hub_fault));
+	gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_a0_fault));
+	gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_a1_fault));
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, usb_fault_interrupt_disable,
+	     HOOK_PRIO_DEFAULT);
+
+int board_set_active_charge_port(int port)
+{
+	int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int i;
+	int rv;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTSUSB("Disabling all charger ports");
+
+		/* Disable all ports. */
+		for (i = 0; i < ppc_cnt; i++) {
+			/*
+			 * If this port had booted in dead battery mode, go
+			 * ahead and reset it so EN_SNK responds properly.
+			 */
+			if (nct38xx_get_boot_type(i) ==
+			    NCT38XX_BOOT_DEAD_BATTERY) {
+				reset_nct38xx_port(i);
+				pd_set_error_recovery(i);
+			}
+
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (ppc_vbus_sink_enable(i, 0))
+				CPRINTSUSB("Disabling C%d as sink failed.", i);
+		}
+
+		return EC_SUCCESS;
+	} else if (!is_valid_port) {
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * Check if we can reset any ports in dead battery mode
+	 *
+	 * The NCT3807 may continue to keep EN_SNK low on the dead battery port
+	 * and allow a dangerous level of voltage to pass through to the initial
+	 * charge port (see b/183660105).  We must reset the ports if we have
+	 * sufficient battery to do so, which will bring EN_SNK back under
+	 * normal control.
+	 */
+	rv = EC_SUCCESS;
+	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+		if (nct38xx_get_boot_type(i) == NCT38XX_BOOT_DEAD_BATTERY) {
+			CPRINTSUSB("Found dead battery on %d", i);
+			/*
+			 * If we have battery, get this port reset ASAP.
+			 * This means temporarily rejecting charge manager
+			 * sets to it.
+			 */
+			if (pd_is_battery_capable()) {
+				reset_nct38xx_port(i);
+				pd_set_error_recovery(i);
+
+				if (port == i)
+					rv = EC_ERROR_INVAL;
+			} else if (port != i) {
+				/*
+				 * If other port is selected and in dead battery
+				 * mode, reset this port.  Otherwise, reject
+				 * change because we'll brown out.
+				 */
+				if (nct38xx_get_boot_type(port) ==
+				    NCT38XX_BOOT_DEAD_BATTERY) {
+					reset_nct38xx_port(i);
+					pd_set_error_recovery(i);
+				} else {
+					rv = EC_ERROR_INVAL;
+				}
+			}
+		}
+	}
+
+	if (rv != EC_SUCCESS)
+		return rv;
+
+	/* Check if the port is sourcing VBUS. */
+	if (tcpm_get_src_ctrl(port)) {
+		CPRINTSUSB("Skip enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTSUSB("New charge port: C%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < ppc_cnt; i++) {
+		if (i == port)
+			continue;
+
+		if (ppc_vbus_sink_enable(i, 0))
+			CPRINTSUSB("C%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTSUSB("C%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+void sbu_fault_interrupt(enum gpio_signal signal)
+{
+	int port = signal == IOEX_USB_C1_FAULT_ODL ? 1 : 0;
+
+	CPRINTSUSB("C%d: SBU fault", port);
+	pd_handle_overcurrent(port);
+}
+
+static void usb_fault_alert(void)
+{
+	int out;
+
+	out = gpio_pin_get_dt(
+		      GPIO_DT_FROM_NODELABEL(gpio_usb_hub_fault_q_odl)) &&
+	      gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(ioex_usb_a0_fault_odl)) &&
+	      gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(ioex_usb_a1_fault_db_odl));
+
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_fault_odl), out);
+
+	if (out == 0)
+		CPRINTSUSB("USB fault, alerting the SoC");
+}
+DECLARE_DEFERRED(usb_fault_alert);
+
+void usb_fault_interrupt(enum gpio_signal signal)
+{
+	hook_call_deferred(&usb_fault_alert_data, 0);
+}
+
+void usb_pd_soc_interrupt(enum gpio_signal signal)
+{
+	/*
+	 * This interrupt is unexpected with our use of the SoC mux, so just log
+	 * it as a point of interest.
+	 */
+	CPRINTSUSB("SOC PD Interrupt");
+}
+
+#ifdef CONFIG_CHARGER_ISL9241
+/* Round up 3250 max current to multiple of 128mA for ISL9241 AC prochot. */
+static void charger_prochot_init_isl9241(void)
+{
+	isl9241_set_ac_prochot(CHARGER_SOLO, CONFIG_AC_PROCHOT_CURRENT_MA);
+}
+DECLARE_HOOK(HOOK_INIT, charger_prochot_init_isl9241, HOOK_PRIO_DEFAULT);
+#endif /* CONFIG_CHARGER_ISL9241 */
+
+#ifdef CONFIG_CHARGER_ISL9238
+static void charger_prochot_init_isl9238(void)
+{
+	isl923x_set_ac_prochot(CHARGER_SOLO, CONFIG_AC_PROCHOT_CURRENT_MA);
+	isl923x_set_dc_prochot(CHARGER_SOLO, CONFIG_DC_PROCHOT_CURRENT_MA);
+}
+DECLARE_HOOK(HOOK_INIT, charger_prochot_init_isl9238, HOOK_PRIO_DEFAULT);
+#endif /* CONFIG_CHARGER_ISL9238 */
+
+static void reset_nct38xx_port(int port)
+{
+	const struct gpio_dt_spec *reset_gpio_l;
+	const struct device *ioex_port0, *ioex_port1;
+	int rv;
+
+	/* The maximum pin numbers of the NCT38xx IO expander port is 8 */
+	gpio_flags_t saved_port0_flags[8] = { 0 };
+	gpio_flags_t saved_port1_flags[8] = { 0 };
+
+	if (port == USBC_PORT_C0) {
+		reset_gpio_l = &tcpc_config[0].rst_gpio;
+		ioex_port0 = DEVICE_DT_GET(DT_NODELABEL(ioex_c0_port0));
+		ioex_port1 = DEVICE_DT_GET(DT_NODELABEL(ioex_c0_port1));
+	} else if (port == USBC_PORT_C1) {
+		reset_gpio_l = &tcpc_config[1].rst_gpio;
+		ioex_port0 = DEVICE_DT_GET(DT_NODELABEL(ioex_c1_port0));
+		ioex_port1 = DEVICE_DT_GET(DT_NODELABEL(ioex_c1_port1));
+	} else {
+		/* Invalid port: do nothing */
+		return;
+	}
+	gpio_save_port_config(ioex_port0, saved_port0_flags,
+			      ARRAY_SIZE(saved_port0_flags));
+	gpio_save_port_config(ioex_port1, saved_port1_flags,
+			      ARRAY_SIZE(saved_port1_flags));
+
+	gpio_pin_set_dt(reset_gpio_l, 1);
+	msleep(NCT38XX_RESET_HOLD_DELAY_MS);
+	gpio_pin_set_dt(reset_gpio_l, 0);
+	nct38xx_reset_notify(port);
+	if (NCT3807_RESET_POST_DELAY_MS != 0)
+		msleep(NCT3807_RESET_POST_DELAY_MS);
+
+	/* Re-enable the IO expander pins */
+	gpio_restore_port_config(ioex_port0, saved_port0_flags,
+				 ARRAY_SIZE(saved_port0_flags));
+	gpio_restore_port_config(ioex_port1, saved_port1_flags,
+				 ARRAY_SIZE(saved_port1_flags));
+
+	if (power_get_state() == POWER_S0) {
+		/* If we transitioned to S0 during the reset then the restore
+		 * may set the vbus enable pin low. Ensure the A port is
+		 * always powered in S0.
+		 */
+		rv = usb_charge_set_mode(port, USB_CHARGE_MODE_ENABLED,
+					 USB_ALLOW_SUSPEND_CHARGE);
+		if (rv)
+			CPRINTSUSB("S0 TCPC enable failure on port %d(%d)",
+				   port, rv);
+	}
+}
+
+void board_reset_pd_mcu(void)
+{
+	/* Reset TCPC0 */
+	reset_nct38xx_port(USBC_PORT_C0);
+
+	/* Reset TCPC1 */
+	reset_nct38xx_port(USBC_PORT_C1);
+}
+
+#ifdef CONFIG_PLATFORM_EC_USB_CHARGER
+void bc12_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_BC12_INT_ODL:
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+		break;
+
+	case GPIO_USB_C1_BC12_INT_ODL:
+		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+		break;
+
+	default:
+		break;
+	}
+}
+
+/**
+ * Return if VBUS is sagging too low
+ *
+ * For legacy BC1.2 charging with CONFIG_CHARGE_RAMP_SW, ramp up input current
+ * until voltage drops to 4.5V. Don't go lower than this to be kind to the
+ * charger (see b/67964166).
+ */
+#define BC12_MIN_VOLTAGE 4500
+int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
+{
+	int voltage = 0;
+	int rv;
+
+	rv = charger_get_vbus_voltage(port, &voltage);
+
+	if (rv) {
+		CPRINTSUSB("%s rv=%d", __func__, rv);
+		return 0;
+	}
+
+	/*
+	 * b/168569046: The ISL9241 sometimes incorrectly reports 0 for unknown
+	 * reason, causing ramp to stop at 0.5A. Workaround this by ignoring 0.
+	 * This partly defeats the point of ramping, but will still catch
+	 * VBUS below 4.5V and above 0V.
+	 */
+	if (voltage == 0) {
+		CPRINTSUSB("%s vbus=0", __func__);
+		return 0;
+	}
+
+	if (voltage < BC12_MIN_VOLTAGE)
+		CPRINTSUSB("%s vbus=%d", __func__, voltage);
+
+	return voltage < BC12_MIN_VOLTAGE;
+}
+#endif
+
+#define SAFE_RESET_VBUS_DELAY_MS 900
+#define SAFE_RESET_VBUS_MV 5000
+void board_hibernate(void)
+{
+	int port;
+	enum ec_error_list ret;
+
+	/*
+	 * If we are charging, then drop the Vbus level down to 5V to ensure
+	 * that we don't get locked out of the 6.8V OVLO for our PPCs in
+	 * dead-battery mode. This is needed when the TCPC/PPC rails go away.
+	 * (b/79218851, b/143778351, b/147007265)
+	 */
+	port = charge_manager_get_active_charge_port();
+	if (port != CHARGE_PORT_NONE) {
+		pd_request_source_voltage(port, SAFE_RESET_VBUS_MV);
+
+		/* Give PD task and PPC chip time to get to 5V */
+		msleep(SAFE_RESET_VBUS_DELAY_MS);
+	}
+
+	/* Try to put our battery fuel gauge into sleep mode */
+	ret = battery_sleep_fuel_gauge();
+	if ((ret != EC_SUCCESS) && (ret != EC_ERROR_UNIMPLEMENTED))
+		cprints(CC_SYSTEM, "Failed to send battery sleep command");
+}
diff --git a/zephyr/program/skyrim/usbc.dtsi b/zephyr/program/skyrim/usbc.dtsi
new file mode 100644
index 0000000000..a5fb5a88af
--- /dev/null
+++ b/zephyr/program/skyrim/usbc.dtsi
@@ -0,0 +1,42 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		usbc_port0: port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+			bc12 = <&bc12_port0>;
+			tcpc = <&tcpc_port0>;
+			chg = <&charger>;
+			chg_alt = <&alt_charger>;
+			ppc = <&ppc_port0>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&amd_fp6_port0 &anx7483_port0>;
+			};
+		};
+
+		usbc_port1: port1@1 {
+			compatible = "named-usbc-port";
+			reg = <1>;
+			bc12 = <&bc12_port1>;
+			tcpc = <&tcpc_port1>;
+			ppc = <&ppc_port1>;
+			usb-mux-chain-1-anx {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&amd_fp6_port1 &anx7483_port1>;
+			};
+			usb_mux_chain_ps8818_port1: usb-mux-chain-1-ps {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&amd_fp6_port1 &ps8818_port1>;
+				alternative-chain;
+			};
+		};
+	};
+};
diff --git a/zephyr/program/skyrim/winterhold/CMakeLists.txt b/zephyr/program/skyrim/winterhold/CMakeLists.txt
new file mode 100644
index 0000000000..632f11d8f1
--- /dev/null
+++ b/zephyr/program/skyrim/winterhold/CMakeLists.txt
@@ -0,0 +1,17 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+zephyr_library_sources(
+	"src/usb_mux_config.c"
+	"src/ppc_config.c"
+	"src/kb_backlight.c"
+	"src/keyboard.c"
+	"src/sensor.c"
+	"src/battery_present.c"
+	"src/alt_charger.c"
+	"src/thermal.c"
+)
+
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CUSTOM_FAN_DUTY_CONTROL
+  "src/fan.c")
diff --git a/zephyr/program/skyrim/winterhold/led_pins.dtsi b/zephyr/program/skyrim/winterhold/led_pins.dtsi
new file mode 100644
index 0000000000..28766c5271
--- /dev/null
+++ b/zephyr/program/skyrim/winterhold/led_pins.dtsi
@@ -0,0 +1,58 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	pwmleds {
+		compatible = "pwm-leds";
+		pwm_y: pwm_y {
+			pwms = <&pwm2 0 PWM_HZ(100) PWM_POLARITY_INVERTED>;
+		};
+		pwm_w: pwm_w {
+			pwms = <&pwm3 0 PWM_HZ(100) PWM_POLARITY_INVERTED>;
+		};
+	};
+
+	pwm-led-pins {
+		compatible = "cros-ec,pwm-led-pins";
+
+		battery_led: battery-led {
+			led-id = "EC_LED_ID_BATTERY_LED";
+			led-pwms = <&pwm_y &pwm_w>;
+
+			color_off: color-off {
+				led-color = "LED_OFF";
+				led-values = <0 0>;
+			};
+
+			color_amber: color-amber {
+				led-color = "LED_AMBER";
+				br-color = "EC_LED_COLOR_AMBER";
+				led-values = <100 0>;
+			};
+
+			color_white: color-white {
+				led-color = "LED_WHITE";
+				br-color = "EC_LED_COLOR_WHITE";
+				led-values = <0 100>;
+			};
+		};
+	};
+};
+
+/* Amber "battery charging" LED */
+&pwm2 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm2_gpc4>;
+	pinctrl-names = "default";
+};
+
+/* White "battery full" LED */
+&pwm3 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm3_gp80>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/skyrim/winterhold/led_policy.dtsi b/zephyr/program/skyrim/winterhold/led_policy.dtsi
new file mode 100644
index 0000000000..7a8d4c5b81
--- /dev/null
+++ b/zephyr/program/skyrim/winterhold/led_policy.dtsi
@@ -0,0 +1,103 @@
+#include <dt-bindings/battery.h>
+
+/ {
+	led-colors {
+		compatible = "cros-ec,led-policy";
+
+		power-state-charge {
+			charge-state = "LED_PWRS_CHARGE";
+			color-0 {
+				led-color = <&color_white>;
+			};
+		};
+
+		power-state-discharge-s0 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S0";
+			/* Battery percent range (> Low, <= Full) */
+			batt-lvl = <(BATTERY_LEVEL_LOW + 1) BATTERY_LEVEL_FULL>;
+
+			color-0 {
+				led-color = <&color_off>;
+			};
+		};
+
+		power-state-discharge-s0-batt-low {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S0";
+			/* Battery percent range (>= Empty, <= Low) */
+			batt-lvl = <BATTERY_LEVEL_EMPTY BATTERY_LEVEL_LOW>;
+
+			color-0 {
+				led-color = <&color_amber>;
+			};
+		};
+
+		power-state-discharge-s3 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S3";
+			/* Battery percent range (> Low, <= Full) */
+			batt-lvl = <(BATTERY_LEVEL_LOW + 1) BATTERY_LEVEL_FULL>;
+
+			color-0 {
+				led-color = <&color_off>;
+			};
+		};
+
+		power-state-discharge-s3-batt-low {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S3";
+			/* Battery percent range (>= Empty, <= Low) */
+			batt-lvl = <BATTERY_LEVEL_EMPTY BATTERY_LEVEL_LOW>;
+
+			color-0 {
+				led-color = <&color_amber>;
+			};
+		};
+
+		power-state-discharge-s5 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S5";
+
+			color-0 {
+				led-color = <&color_off>;
+			};
+		};
+
+		power-state-error {
+			charge-state = "LED_PWRS_ERROR";
+
+			/* Amber 1 sec, off 1 sec */
+			color-0 {
+				led-color = <&color_amber>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <1000>;
+			};
+		};
+
+		power-state-near-full {
+			charge-state = "LED_PWRS_CHARGE_NEAR_FULL";
+
+			color-0 {
+				led-color = <&color_off>;
+			};
+		};
+
+		power-state-forced-idle {
+			charge-state = "LED_PWRS_FORCED_IDLE";
+
+			/* Amber 2 sec, White 2 sec */
+			color-0 {
+				led-color = <&color_amber>;
+				period-ms = <2000>;
+			};
+			color-1 {
+				led-color = <&color_white>;
+				period-ms = <2000>;
+			};
+		};
+	};
+};
diff --git a/zephyr/program/skyrim/winterhold/motionsense.dtsi b/zephyr/program/skyrim/winterhold/motionsense.dtsi
new file mode 100644
index 0000000000..b019a43f10
--- /dev/null
+++ b/zephyr/program/skyrim/winterhold/motionsense.dtsi
@@ -0,0 +1,138 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/motionsense/utils.h>
+
+
+/ {
+	aliases {
+		/*
+		 * motion sense's <>_INT_EVENT is handled
+		 * by alias. Using the alias, each driver creates
+		 * its own <>_INT_EVENT.
+		 */
+		bmi3xx-int = &base_accel;
+		lis2dw12-int = &base_accel;
+
+		/* Use base accelerometer for on-body sensor */
+		on-body-sensor = &base_accel;
+	};
+
+	/*
+	 * Declare mutexes used by sensor drivers.
+	 * A mutex node is used to create an instance of mutex_t.
+	 * A mutex node is referenced by a sensor node if the
+	 * corresponding sensor driver needs to use the
+	 * instance of the mutex.
+	 */
+	motionsense-mutex {
+		mutex_bmi3xx: bmi3xx-mutex {
+		};
+		mutex_lis2dw12: lis2dw12-mutex {
+		};
+	};
+
+	/*
+	 * Driver specific data. A driver-specific data can be shared with
+	 * different motion sensors while they are using the same driver.
+	 *
+	 * If a node's compatible starts with "cros-ec,accelgyro-", it is for
+	 * a common structure defined in accelgyro.h.
+	 * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for
+	 * "struct als_drv_data_t" in accelgyro.h
+	 */
+	motionsense-sensor-data {
+		bmi3xx_data: bmi3xx-drv-data {
+			compatible = "cros-ec,drvdata-bmi3xx";
+			status = "okay";
+		};
+		lis2dw12_data: lis2dw12-drv-data {
+			compatible = "cros-ec,drvdata-lis2dw12";
+			status = "okay";
+		};
+	};
+
+	/*
+	 * List of motion sensors that creates motion_sensors array.
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
+	 * motion sensor IDs for lid angle calculation.
+	 */
+	motionsense-sensor {
+		base_accel: base-accel {
+			compatible = "cros-ec,lis2dw12";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&mutex_lis2dw12>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			default-range = <2>;
+			drv-data = <&lis2dw12_data>;
+			i2c-spi-addr-flags = "LIS2DWL_ADDR1_FLAGS";
+			bodydetect {
+				compatible = "cros-ec,motionsense-bodydetect";
+				status = "okay";
+				var_noise_factor = <150>;
+				var_threshold = <3000>;
+				confidence_delta = <2900>;
+			};
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				/* 50 Hz to support body detection. */
+				ec-s0 {
+					odr = <(50000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(50000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+	};
+
+	motionsense-sensor-alt {
+		alt_base_accel: alt-base-accel {
+			compatible = "cros-ec,bmi3xx-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&mutex_bmi3xx>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref_bmi>;
+			drv-data = <&bmi3xx_data>;
+			alternate-for = <&base_accel>;
+			bodydetect {
+				compatible = "cros-ec,motionsense-bodydetect";
+				status = "okay";
+				var_noise_factor = <120>;
+				var_threshold = <550>;
+				confidence_delta = <525>;
+			};
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(12500 | ROUND_UP_FLAG)>;
+					ec-rate = <100>;
+				};
+				ec-s3 {
+					odr = <(12500 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+	};
+
+	motionsense-sensor-info {
+		compatible = "cros-ec,motionsense-sensor-info";
+
+		/*
+		 * list of GPIO interrupts that have to
+		 * be enabled at initial stage
+		 */
+		sensor-irqs = <&int_accel_gyro>;
+	};
+};
diff --git a/zephyr/program/skyrim/winterhold/project.conf b/zephyr/program/skyrim/winterhold/project.conf
new file mode 100644
index 0000000000..ef336a4667
--- /dev/null
+++ b/zephyr/program/skyrim/winterhold/project.conf
@@ -0,0 +1,57 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Winterhold reference-board-specific Kconfig settings.
+CONFIG_BOARD_WINTERHOLD=y
+
+# Enable charger chip
+CONFIG_PLATFORM_EC_CHARGER_ISL9238=y
+CONFIG_PLATFORM_EC_CHARGER_ISL9241=n
+CONFIG_PLATFORM_EC_AC_PROCHOT_CURRENT_MA=5000
+CONFIG_PLATFORM_EC_DC_PROCHOT_CURRENT_MA=6570
+
+# Enable alternative charger chip
+CONFIG_PLATFORM_EC_CHARGER_RUNTIME_CONFIG=y
+CONFIG_PLATFORM_EC_CHARGER_ISL9238C=y
+CONFIG_PLATFORM_EC_ISL9238C_ENABLE_BUCK_MODE=y
+CONFIG_PLATFORM_EC_CHARGER_PROFILE_OVERRIDE=y
+CONFIG_PLATFORM_EC_CHARGER_MAINTAIN_VBAT=y
+
+# Forward Buck Phase Comparator bit<15:13> to 100=-2mV
+CONFIG_PLATFORM_EC_ISL9238C_BUCK_PHASE_VOLTAGE=6
+
+# Get the vbus voltage from TCPC
+CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_CHARGER=n
+CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_TCPC=y
+
+# Remove unused sensor
+CONFIG_PLATFORM_EC_ACCEL_BMA4XX=n
+
+# Support LIS2DW12 sensor
+CONFIG_PLATFORM_EC_ACCEL_LIS2DW12=y
+
+# Disable lid configuration
+CONFIG_PLATFORM_EC_LID_ANGLE=n
+CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=n
+
+# Disable tablet mode configuration
+CONFIG_PLATFORM_EC_TABLET_MODE=n
+CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=n
+CONFIG_PLATFORM_EC_GMR_TABLET_MODE=n
+
+# Battery
+CONFIG_PLATFORM_EC_BATTERY_PRESENT_CUSTOM=y
+CONFIG_PLATFORM_EC_BATTERY_HW_PRESENT_CUSTOM=y
+
+# Body detection configuration
+CONFIG_PLATFORM_EC_BODY_DETECTION=y
+CONFIG_PLATFORM_EC_BODY_DETECTION_ALWAYS_ENABLE_IN_S0=y
+CONFIG_PLATFORM_EC_BODY_DETECTION_NOTIFY_MODE_CHANGE=y
+CONFIG_PLATFORM_EC_GESTURE_HOST_DETECTION=y
+
+# GPIO configuration
+CONFIG_GPIO_GET_CONFIG=y
+
+# FAN
+CONFIG_PLATFORM_EC_CUSTOM_FAN_DUTY_CONTROL=y
diff --git a/zephyr/program/skyrim/winterhold/project.overlay b/zephyr/program/skyrim/winterhold/project.overlay
new file mode 100644
index 0000000000..818c625fe9
--- /dev/null
+++ b/zephyr/program/skyrim/winterhold/project.overlay
@@ -0,0 +1,230 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Skyrim program common DTS includes */
+#include "../adc.dtsi"
+#include "../fan.dtsi"
+#include "../gpio.dtsi"
+#include "../i2c.dtsi"
+#include "../interrupts.dtsi"
+#include "../keyboard.dtsi"
+#include "../usbc.dtsi"
+
+/* winterhold project DTS includes*/
+#include "led_pins.dtsi"
+#include "led_policy.dtsi"
+#include "motionsense.dtsi"
+
+/* Winterhold overrides follow... */
+/ {
+	/* battery overrides */
+	batteries {
+		default_battery: lgc_xphx8 {
+			compatible = "lgc,xphx8", "battery-smart";
+		};
+		smp_atlxdy9k {
+			compatible = "smp,atlxdy9k", "battery-smart";
+		};
+		smp_cosxdy9k {
+			compatible = "smp,cosxdy9k", "battery-smart";
+		};
+		byd_wv3k8 {
+			compatible = "byd,wv3k8", "battery-smart";
+		};
+		cosmx_mvk11 {
+			compatible = "cosmx,mvk11", "battery-smart";
+		};
+		sunwoda_atlvkyjx {
+			compatible = "sunwoda,atlvkyjx", "battery-smart";
+		};
+		sunwoda_cosvkyjx {
+			compatible = "sunwoda,cosvkyjx", "battery-smart";
+		};
+		atl_cfd72 {
+			compatible = "atl,cfd72", "battery-smart";
+		};
+	};
+
+	named-gpios {
+		/* Winterhold-specific GPIO customizations */
+	};
+
+	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
+		temp_sensor_soc: soc-pct2075 {
+			temp_host_high = <97>;
+			temp_host_halt = <98>;
+			temp_host_release_high = <87>;
+			temp_host_release_halt = <88>;
+			temp_fan_off = <55>;
+			temp_fan_max = <72>;
+			power-good-pin = <&gpio_pg_pwr_s5>;
+			sensor = <&soc_pct2075>;
+		};
+		temp_sensor_amb: amb-pct2075 {
+			temp_host_warn = <43>;
+			temp_host_high = <97>;
+			temp_host_halt = <98>;
+			temp_host_release_warn = <39>;
+			temp_host_release_high = <87>;
+			temp_host_release_halt = <88>;
+			power-good-pin = <&gpio_pg_pwr_s5>;
+			sensor = <&amb_pct2075>;
+		};
+	};
+
+	/*
+	 * Note this is expected to vary per-board, so we keep it in the overlay
+	 * files.
+	 */
+	Winterhold-fw-config {
+		compatible = "cros-ec,cbi-fw-config";
+
+		/*
+		 * FW_CONFIG field to enable KB back light or not.
+		 */
+		kb-bl {
+			enum-name = "FW_KB_BL";
+			start = <1>;
+			size = <1>;
+
+			no-kb-bl {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_KB_BL_NOT_PRESENT";
+				value = <0>;
+			};
+			kb-bl-present {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_KB_BL_PRESENT";
+				value = <1>;
+			};
+		};
+
+		charger-option {
+			enum-name = "FW_CHARGER";
+			start = <2>;
+			size = <1>;
+
+			charger-option-isl9238 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_CHARGER_ISL9238";
+				value = <0>;
+				default;
+			};
+			charger-option-isl9538 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_CHARGER_ISL9538";
+				value = <1>;
+			};
+		};
+
+		base-sensor {
+			enum-name = "FW_BASE_SENSOR";
+			start = <3>;
+			size = <1>;
+
+			bmi323 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_BASE_BMI323";
+				value = <0>;
+				default;
+			};
+			lis2dw12 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_BASE_LIS2DW12";
+				value = <1>;
+			};
+		};
+	};
+
+	/* Rotation matrices for motion sensors. */
+	motionsense-rotation-ref {
+		compatible = "cros-ec,motionsense-rotation-ref";
+		lid_rot_ref: lid-rotation-ref {
+			mat33 = <0 (-1) 0
+				 1 0 0
+				 0 0 1>;
+		};
+
+		base_rot_ref: base-rotation-ref {
+			mat33 = <0 1 0
+				 (-1) 0 0
+				 0 0 1>;
+		};
+		base_rot_ref_bmi: base-rotation-ref-bmi {
+			mat33 = <0 (-1) 0
+				 1 0 0
+				 0 0 1>;
+		};
+	};
+};
+
+/*i2c overrides */
+&i2c1_0 {
+	/delete-node/ ps8818@28;
+};
+
+&i2c4_1 {
+	/delete-node/ isl9241@9;
+	/delete-node/ isl9538@9;
+	charger: isl9238@9 {
+		compatible = "intersil,isl923x";
+		status = "okay";
+		reg = <0x9>;
+	};
+	alt_charger: isl9538@9 {
+		compatible = "intersil,isl923x";
+		status = "okay";
+		reg = <0x9>;
+	};
+};
+
+/* usbc overrides */
+&usbc_port0 {
+	/delete-property/ chg_alt;
+	chg_alt = <&alt_charger>;
+};
+
+&usbc_port1 {
+	/delete-node/ usb-mux-chain-1-ps;
+};
+
+/* fan overrides */
+&fan0 {
+	pwms = <&pwm0 0 PWM_KHZ(2) PWM_POLARITY_NORMAL>;
+	rpm_min = <2100>;
+	rpm_start = <2800>;
+	rpm_max = <4800>;
+	rpm_deviation = <3>;
+};
+
+/* temperature sensor overrides */
+&temp_sensor_charger {
+	temp_host_high = <97>;
+	temp_host_halt = <98>;
+	temp_host_release_high = <87>;
+	temp_host_release_halt = <88>;
+};
+
+&temp_sensor_memory {
+	temp_host_high = <91>;
+	temp_host_halt = <96>;
+	temp_host_release_high = <81>;
+	temp_host_release_halt = <86>;
+};
+
+&temp_sensor_cpu {
+	temp_host_high = <110>;
+	temp_host_halt = <112>;
+	temp_host_release_high = <96>;
+	temp_host_release_halt = <96>;
+	temp_fan_off = <76>;
+	temp_fan_max = <82>;
+};
+
+/* handler overrides */
+&int_accel_gyro {
+	handler = "base_accel_interrupt";
+};
diff --git a/zephyr/program/skyrim/winterhold/src/alt_charger.c b/zephyr/program/skyrim/winterhold/src/alt_charger.c
new file mode 100644
index 0000000000..19c74afa39
--- /dev/null
+++ b/zephyr/program/skyrim/winterhold/src/alt_charger.c
@@ -0,0 +1,31 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charger_chips.h"
+#include "common.h"
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+#include "hooks.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(winterhold, CONFIG_SKYRIM_LOG_LEVEL);
+
+static void alt_charger_init(void)
+{
+	int ret;
+	uint32_t val;
+
+	ret = cros_cbi_get_fw_config(FW_CHARGER, &val);
+	if (ret != 0) {
+		LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_CHARGER);
+		return;
+	}
+
+	if (val == FW_CHARGER_ISL9538)
+		CHG_ENABLE_ALTERNATE(0);
+}
+DECLARE_HOOK(HOOK_INIT, alt_charger_init, HOOK_PRIO_POST_FIRST);
diff --git a/zephyr/program/skyrim/winterhold/src/battery_present.c b/zephyr/program/skyrim/winterhold/src/battery_present.c
new file mode 100644
index 0000000000..290955a242
--- /dev/null
+++ b/zephyr/program/skyrim/winterhold/src/battery_present.c
@@ -0,0 +1,81 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "battery.h"
+#include "battery_smart.h"
+#include "common.h"
+
+#include <zephyr/drivers/gpio.h>
+
+static enum battery_present batt_pres_prev = BP_NOT_SURE;
+
+__overridable bool board_battery_is_initialized(void)
+{
+	int batt_status;
+
+	return battery_status(&batt_status) != EC_SUCCESS ?
+		       false :
+		       !!(batt_status & STATUS_INITIALIZED);
+}
+
+/*
+ * Physical detection of battery.
+ */
+static enum battery_present battery_check_present_status(void)
+{
+	enum battery_present batt_pres;
+
+	if (battery_is_cut_off())
+		return BP_NO;
+
+	/* Get the physical hardware status */
+	batt_pres = battery_hw_present();
+
+	/*
+	 * If the battery is not physically connected, then no need to perform
+	 * any more checks.
+	 */
+	if (batt_pres == BP_NO)
+		return BP_NO;
+
+	/*
+	 * If the battery is present now and was present last time we checked,
+	 * return early.
+	 */
+	if ((batt_pres == BP_YES) && (batt_pres == batt_pres_prev))
+		return BP_YES;
+
+	/*
+	 * Check battery initialization. If the battery is not initialized,
+	 * then return BP_NOT_SURE. Battery could be in ship
+	 * mode and might require pre-charge current to wake it up. BP_NO is not
+	 * returned here because charger state machine will not provide
+	 * pre-charge current assuming that battery is not present.
+	 */
+	if (!board_battery_is_initialized())
+		return BP_NOT_SURE;
+
+	return BP_YES;
+}
+
+enum battery_present battery_is_present(void)
+{
+	batt_pres_prev = battery_check_present_status();
+	return batt_pres_prev;
+}
+
+enum battery_present battery_hw_present(void)
+{
+	const struct gpio_dt_spec *batt_pres;
+
+	batt_pres = GPIO_DT_FROM_NODELABEL(gpio_ec_batt_pres_odl);
+
+	/*
+	 * The GPIO is low when the battery is physically present.
+	 * But if battery cell voltage < 2.5V, it will not able to
+	 * pull down EC_BATT_PRES_ODL. So we need to set pre-charge
+	 * current even EC_BATT_PRES_ODL is high.
+	 */
+	return gpio_pin_get_dt(batt_pres) ? BP_NOT_SURE : BP_YES;
+}
diff --git a/zephyr/program/skyrim/winterhold/src/fan.c b/zephyr/program/skyrim/winterhold/src/fan.c
new file mode 100644
index 0000000000..a5061a660f
--- /dev/null
+++ b/zephyr/program/skyrim/winterhold/src/fan.c
@@ -0,0 +1,90 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "fan.h"
+#include "math_util.h"
+#include "thermal.h"
+
+#include <zephyr/kernel.h>
+
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_THERMAL, format, ##args)
+
+K_TIMER_DEFINE(grace_period_timer, NULL, NULL);
+
+enum fan_status board_override_fan_control_duty(int ch)
+{
+	int duty, rpm_diff, deviation, duty_step;
+	struct fan_data *data = &fan_data[ch];
+	int rpm_actual = data->rpm_actual;
+	int rpm_target = data->rpm_target;
+
+	/* This works with one fan only. */
+	if (ch != 0) {
+		CPRINTS("Only FAN0 is supported!");
+		return FAN_STATUS_FRUSTRATED;
+	}
+
+	/* Wait for fan RPM to catch up after its duty has been changed. */
+	if (k_timer_remaining_ticks(&grace_period_timer) != 0)
+		return FAN_STATUS_LOCKED;
+
+	duty = fan_get_duty(ch);
+	if (duty == 0 && rpm_target == 0)
+		return FAN_STATUS_STOPPED;
+
+	/*
+	 * If the current RPM is close enough to the target just leave it.
+	 * It's always going to fluctuate a bit anyway.
+	 */
+	deviation = fans[ch].rpm->rpm_deviation * rpm_target / 100;
+	rpm_diff = rpm_target - rpm_actual;
+	if (rpm_diff > deviation) {
+		/* Can't set duty higher than 100%... */
+		if (duty == 100)
+			return FAN_STATUS_FRUSTRATED;
+	} else if (rpm_diff < -deviation) {
+		/* Can't set duty lower than 1%... */
+		if (duty == 1 && rpm_target != 0)
+			return FAN_STATUS_FRUSTRATED;
+	} else {
+		return FAN_STATUS_LOCKED;
+	}
+
+	/*
+	 * The rpm_diff -> duty_step conversion is specific to a specific
+	 * whiterun fan.
+	 * It has been determined empirically.
+	 */
+	if (ABS(rpm_diff) >= 2500) {
+		duty_step = 35;
+		k_timer_start(&grace_period_timer, K_MSEC(800), K_NO_WAIT);
+	} else if (ABS(rpm_diff) >= 2000) {
+		duty_step = 28;
+		k_timer_start(&grace_period_timer, K_MSEC(800), K_NO_WAIT);
+	} else if (ABS(rpm_diff) >= 1000) {
+		duty_step = 14;
+		k_timer_start(&grace_period_timer, K_MSEC(800), K_NO_WAIT);
+	} else if (ABS(rpm_diff) >= 500) {
+		duty_step = 6;
+		k_timer_start(&grace_period_timer, K_MSEC(800), K_NO_WAIT);
+	} else if (ABS(rpm_diff) >= 250) {
+		duty_step = 3;
+		k_timer_start(&grace_period_timer, K_MSEC(600), K_NO_WAIT);
+	} else {
+		duty_step = 1;
+		k_timer_start(&grace_period_timer, K_MSEC(600), K_NO_WAIT);
+	}
+
+	if (rpm_diff > 0)
+		duty = MIN(duty + duty_step, 100);
+	else
+		duty = MAX(duty - duty_step, 1);
+
+	fan_set_duty(ch, duty);
+
+	return FAN_STATUS_CHANGING;
+}
diff --git a/zephyr/program/skyrim/winterhold/src/kb_backlight.c b/zephyr/program/skyrim/winterhold/src/kb_backlight.c
new file mode 100644
index 0000000000..cbbfc0a4e9
--- /dev/null
+++ b/zephyr/program/skyrim/winterhold/src/kb_backlight.c
@@ -0,0 +1,34 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "board_config.h"
+#include "common.h"
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(skyrim, CONFIG_SKYRIM_LOG_LEVEL);
+
+__override uint32_t board_override_feature_flags0(uint32_t flags0)
+{
+	int ret;
+	uint32_t val;
+
+	/*
+	 * Remove keyboard backlight feature for devices that don't support it.
+	 */
+	ret = cros_cbi_get_fw_config(FW_KB_BL, &val);
+	if (ret != 0) {
+		LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_KB_BL);
+		return flags0;
+	}
+
+	if (val == FW_KB_BL_NOT_PRESENT)
+		return (flags0 & ~EC_FEATURE_MASK_0(EC_FEATURE_PWM_KEYB));
+	else
+		return flags0;
+}
diff --git a/zephyr/program/skyrim/winterhold/src/keyboard.c b/zephyr/program/skyrim/winterhold/src/keyboard.c
new file mode 100644
index 0000000000..d3aebe0f2e
--- /dev/null
+++ b/zephyr/program/skyrim/winterhold/src/keyboard.c
@@ -0,0 +1,29 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+
+static const struct ec_response_keybd_config winterhold_kb = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &winterhold_kb;
+}
diff --git a/zephyr/program/skyrim/winterhold/src/ppc_config.c b/zephyr/program/skyrim/winterhold/src/ppc_config.c
new file mode 100644
index 0000000000..d6adb145ff
--- /dev/null
+++ b/zephyr/program/skyrim/winterhold/src/ppc_config.c
@@ -0,0 +1,27 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Winterhold board-specific PPC code */
+
+#include "driver/ppc/nx20p348x.h"
+#include "usbc_ppc.h"
+
+#include <zephyr/drivers/gpio.h>
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		nx20p348x_interrupt(0);
+		break;
+
+	case GPIO_USB_C1_PPC_INT_ODL:
+		nx20p348x_interrupt(1);
+		break;
+
+	default:
+		break;
+	}
+}
diff --git a/zephyr/program/skyrim/winterhold/src/sensor.c b/zephyr/program/skyrim/winterhold/src/sensor.c
new file mode 100644
index 0000000000..2cd9294a10
--- /dev/null
+++ b/zephyr/program/skyrim/winterhold/src/sensor.c
@@ -0,0 +1,50 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+#include "driver/accel_lis2dw12.h"
+#include "driver/accelgyro_bmi3xx.h"
+#include "hooks.h"
+#include "motionsense_sensors.h"
+
+static int cbi_boardversion = -1;
+static int cbi_fwconfig;
+
+void base_accel_interrupt(enum gpio_signal signal)
+{
+	if (cbi_boardversion == 0)
+		bmi3xx_interrupt(signal);
+	else if (cbi_boardversion == 1)
+		lis2dw12_interrupt(signal);
+	else if (cbi_boardversion >= 2) {
+		if (cbi_fwconfig == FW_BASE_BMI323)
+			bmi3xx_interrupt(signal);
+		else if (cbi_fwconfig == FW_BASE_LIS2DW12)
+			lis2dw12_interrupt(signal);
+	} else
+		lis2dw12_interrupt(signal);
+}
+
+static void motionsense_init(void)
+{
+	int ret;
+
+	ret = cbi_get_board_version(&cbi_boardversion);
+	cros_cbi_get_fw_config(FW_BASE_SENSOR, &cbi_fwconfig);
+
+	if (ret == EC_SUCCESS && cbi_boardversion < 1) {
+		MOTIONSENSE_ENABLE_ALTERNATE(alt_base_accel);
+	} else if (cbi_boardversion >= 2) {
+		if (cbi_fwconfig == FW_BASE_BMI323) {
+			MOTIONSENSE_ENABLE_ALTERNATE(alt_base_accel);
+			ccprints("BASE ACCEL is BMI323");
+		} else if (cbi_fwconfig == FW_BASE_LIS2DW12) {
+			ccprints("BASE ACCEL IS LIS2DW12");
+		}
+	}
+}
+DECLARE_HOOK(HOOK_INIT, motionsense_init, HOOK_PRIO_DEFAULT);
diff --git a/zephyr/program/skyrim/winterhold/src/thermal.c b/zephyr/program/skyrim/winterhold/src/thermal.c
new file mode 100644
index 0000000000..0ccd9dd9e2
--- /dev/null
+++ b/zephyr/program/skyrim/winterhold/src/thermal.c
@@ -0,0 +1,211 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "body_detection.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "lid_switch.h"
+#include "temp_sensor/temp_sensor.h"
+#include "thermal.h"
+
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_THERMAL, format, ##args)
+
+/*AMB sensor for thermal tabel control*/
+#define TEMP_AMB TEMP_SENSOR_ID(DT_NODELABEL(temp_sensor_amb))
+/*SOC and CPU sensor for fan tabel control*/
+#define TEMP_SOC TEMP_SENSOR_ID(DT_NODELABEL(temp_sensor_soc))
+#define TEMP_CPU TEMP_SENSOR_ID(DT_NODELABEL(temp_sensor_cpu))
+
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_DESKTOP_LID_OPEN \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = C_TO_K(43), \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(97), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(98), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = C_TO_K(39), \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(87), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(88), \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_desktop_lid_open =
+	THERMAL_DESKTOP_LID_OPEN;
+
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_DESKTOP_LID_CLOSE \
+	{                         \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = C_TO_K(43), \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(97), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(98), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = C_TO_K(39), \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(87), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(88), \
+		},  \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_desktop_lid_close =
+	THERMAL_DESKTOP_LID_CLOSE;
+
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_LAPTOP           \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_WARN] = C_TO_K(42), \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(97), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(98), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_WARN] = C_TO_K(38), \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(87), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(88), \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_laptop =
+	THERMAL_LAPTOP;
+
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define FAN_SOC_DESKTOP_LID_OPEN \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(97), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(98), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(87), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(88), \
+		}, \
+		.temp_fan_off = C_TO_K(55), \
+		.temp_fan_max = C_TO_K(72), \
+	}
+__maybe_unused static const struct ec_thermal_config fan_soc_desktop_lid_open =
+	FAN_SOC_DESKTOP_LID_OPEN;
+
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define FAN_SOC_DESKTOP_LID_CLOSE \
+	{                         \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(97), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(98), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(87), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(88), \
+		}, \
+		.temp_fan_off = C_TO_K(55), \
+		.temp_fan_max = C_TO_K(72),  \
+	}
+__maybe_unused static const struct ec_thermal_config fan_soc_desktop_lid_close =
+	FAN_SOC_DESKTOP_LID_CLOSE;
+
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define FAN_SOC_LAPTOP           \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(97), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(98), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(87), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(88), \
+		}, \
+		.temp_fan_off = C_TO_K(51), \
+		.temp_fan_max = C_TO_K(68), \
+	}
+__maybe_unused static const struct ec_thermal_config fan_soc_laptop =
+	FAN_SOC_LAPTOP;
+
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define FAN_CPU_DESKTOP_LID_OPEN                                        \
+	{                                                               \
+		.temp_fan_off = C_TO_K(72), .temp_fan_max = C_TO_K(82), \
+	}
+__maybe_unused static const struct ec_thermal_config fan_cpu_desktop_lid_open =
+	FAN_CPU_DESKTOP_LID_OPEN;
+
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define FAN_CPU_DESKTOP_LID_CLOSE                                       \
+	{                                                               \
+		.temp_fan_off = C_TO_K(72), .temp_fan_max = C_TO_K(82), \
+	}
+__maybe_unused static const struct ec_thermal_config fan_cpu_desktop_lid_close =
+	FAN_CPU_DESKTOP_LID_CLOSE;
+
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define FAN_CPU_LAPTOP                                                  \
+	{                                                               \
+		.temp_fan_off = C_TO_K(68), .temp_fan_max = C_TO_K(78), \
+	}
+__maybe_unused static const struct ec_thermal_config fan_cpu_laptop =
+	FAN_CPU_LAPTOP;
+
+static int last_amb_temp = -1;
+
+/* Switch thermal table when mode change */
+static void thermal_table_switch(void)
+{
+	enum body_detect_states body_state = body_detect_get_state();
+
+	if (body_state == BODY_DETECTION_OFF_BODY) {
+		if (lid_is_open()) {
+			thermal_params[TEMP_AMB] = thermal_desktop_lid_open;
+			thermal_params[TEMP_SOC] = fan_soc_desktop_lid_open;
+			thermal_params[TEMP_CPU] = fan_cpu_desktop_lid_open;
+			CPRINTS("Thermal: Desktop lid open mode");
+		} else {
+			thermal_params[TEMP_AMB] = thermal_desktop_lid_close;
+			thermal_params[TEMP_SOC] = fan_soc_desktop_lid_close;
+			thermal_params[TEMP_CPU] = fan_cpu_desktop_lid_close;
+			CPRINTS("Thermal: Desktop lid close mode");
+		}
+	} else {
+		thermal_params[TEMP_AMB] = thermal_laptop;
+		thermal_params[TEMP_SOC] = fan_soc_laptop;
+		thermal_params[TEMP_CPU] = fan_cpu_laptop;
+		CPRINTS("Thermal: Laptop mode");
+	}
+}
+DECLARE_HOOK(HOOK_INIT, thermal_table_switch, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_LID_CHANGE, thermal_table_switch, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_BODY_DETECT_CHANGE, thermal_table_switch, HOOK_PRIO_DEFAULT);
+
+/* Set SCI event to host for temperature change */
+static void detect_temp_change(void)
+{
+	int t, rv;
+
+	rv = temp_sensor_read(TEMP_AMB, &t);
+	if (rv == EC_SUCCESS) {
+		if (last_amb_temp != t) {
+			last_amb_temp = t;
+			host_set_single_event(EC_HOST_EVENT_THERMAL_THRESHOLD);
+		}
+	} else if (rv == EC_ERROR_INVAL) {
+		CPRINTS("Temp sensor: Invalid id");
+	}
+}
+DECLARE_HOOK(HOOK_SECOND, detect_temp_change, HOOK_PRIO_TEMP_SENSOR_DONE);
diff --git a/zephyr/program/skyrim/winterhold/src/usb_mux_config.c b/zephyr/program/skyrim/winterhold/src/usb_mux_config.c
new file mode 100644
index 0000000000..b4a8bc2662
--- /dev/null
+++ b/zephyr/program/skyrim/winterhold/src/usb_mux_config.c
@@ -0,0 +1,168 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Winterhold board-specific USB-C mux configuration */
+
+#include "charge_state.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+#include "driver/retimer/anx7483_public.h"
+#include "hooks.h"
+#include "ioexpander.h"
+#include "usb_mux.h"
+#include "usbc/usb_muxes.h"
+
+#include <zephyr/drivers/gpio.h>
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/*
+ * USB C0 (general) and C1 (just ANX DB) use IOEX pins to
+ * indicate flipped polarity to a protection switch.
+ */
+test_export_static int ioex_set_flip(int port, mux_state_t mux_state)
+{
+	if (port == 0) {
+		if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
+			gpio_pin_set_dt(
+				GPIO_DT_FROM_NODELABEL(ioex_usb_c0_sbu_flip),
+				1);
+		else
+			gpio_pin_set_dt(
+				GPIO_DT_FROM_NODELABEL(ioex_usb_c0_sbu_flip),
+				0);
+	} else {
+		if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
+			gpio_pin_set_dt(
+				GPIO_DT_FROM_NODELABEL(ioex_usb_c1_sbu_flip),
+				1);
+		else
+			gpio_pin_set_dt(
+				GPIO_DT_FROM_NODELABEL(ioex_usb_c1_sbu_flip),
+				0);
+	}
+
+	return EC_SUCCESS;
+}
+
+int board_anx7483_c0_mux_set(const struct usb_mux *me, mux_state_t mux_state)
+{
+	/* Set the SBU polarity mux */
+	RETURN_ERROR(ioex_set_flip(me->usb_port, mux_state));
+
+	return anx7483_set_default_tuning(me, mux_state);
+}
+
+int board_anx7483_c1_fg_defalut_tuning(const struct usb_mux *me)
+{
+	RETURN_ERROR(
+		anx7483_set_fg(me, ANX7483_PIN_URX1, ANX7483_FG_SETTING_1_2DB));
+	RETURN_ERROR(
+		anx7483_set_fg(me, ANX7483_PIN_URX2, ANX7483_FG_SETTING_1_2DB));
+	RETURN_ERROR(
+		anx7483_set_fg(me, ANX7483_PIN_UTX1, ANX7483_FG_SETTING_1_2DB));
+	RETURN_ERROR(
+		anx7483_set_fg(me, ANX7483_PIN_UTX2, ANX7483_FG_SETTING_1_2DB));
+
+	return EC_SUCCESS;
+}
+
+int board_anx7483_c1_mux_set(const struct usb_mux *me, mux_state_t mux_state)
+{
+	bool flipped = mux_state & USB_PD_MUX_POLARITY_INVERTED;
+
+	/* Set the SBU polarity mux */
+	RETURN_ERROR(ioex_set_flip(me->usb_port, mux_state));
+
+	/* Remove flipped from the state for easier compraisons */
+	mux_state = mux_state & ~USB_PD_MUX_POLARITY_INVERTED;
+
+	RETURN_ERROR(anx7483_set_default_tuning(me, mux_state));
+
+	/*
+	 * Set the Flat Gain to default every time, to prevent DP only mode's
+	 * Flat Gain change in the last plug.
+	 */
+	RETURN_ERROR(board_anx7483_c1_fg_defalut_tuning(me));
+
+	if (mux_state == USB_PD_MUX_USB_ENABLED) {
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX1,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX2,
+					    ANX7483_EQ_SETTING_12_5DB));
+	} else if (mux_state == USB_PD_MUX_DP_ENABLED) {
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1,
+					    ANX7483_EQ_SETTING_8_4DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2,
+					    ANX7483_EQ_SETTING_8_4DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX1,
+					    ANX7483_EQ_SETTING_8_4DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX2,
+					    ANX7483_EQ_SETTING_8_4DB));
+		RETURN_ERROR(anx7483_set_fg(me, ANX7483_PIN_URX1,
+					    ANX7483_FG_SETTING_0_5DB));
+		RETURN_ERROR(anx7483_set_fg(me, ANX7483_PIN_URX2,
+					    ANX7483_FG_SETTING_0_5DB));
+		RETURN_ERROR(anx7483_set_fg(me, ANX7483_PIN_UTX1,
+					    ANX7483_FG_SETTING_0_5DB));
+		RETURN_ERROR(anx7483_set_fg(me, ANX7483_PIN_UTX2,
+					    ANX7483_FG_SETTING_0_5DB));
+	} else if (mux_state == USB_PD_MUX_DOCK && !flipped) {
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2,
+					    ANX7483_EQ_SETTING_8_4DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX1,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX2,
+					    ANX7483_EQ_SETTING_8_4DB));
+		RETURN_ERROR(anx7483_set_fg(me, ANX7483_PIN_URX2,
+					    ANX7483_FG_SETTING_0_5DB));
+		RETURN_ERROR(anx7483_set_fg(me, ANX7483_PIN_UTX2,
+					    ANX7483_FG_SETTING_0_5DB));
+	} else if (mux_state == USB_PD_MUX_DOCK && flipped) {
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1,
+					    ANX7483_EQ_SETTING_8_4DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX1,
+					    ANX7483_EQ_SETTING_8_4DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX2,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_fg(me, ANX7483_PIN_URX1,
+					    ANX7483_FG_SETTING_0_5DB));
+		RETURN_ERROR(anx7483_set_fg(me, ANX7483_PIN_UTX1,
+					    ANX7483_FG_SETTING_0_5DB));
+	}
+
+	return EC_SUCCESS;
+}
+
+int charger_profile_override(struct charge_state_data *curr)
+{
+	if (chipset_in_state(CHIPSET_STATE_ON)) {
+		curr->requested_current = MIN(curr->requested_current, 1152);
+	}
+
+	return 0;
+}
+
+enum ec_status charger_profile_override_get_param(uint32_t param,
+						  uint32_t *value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+enum ec_status charger_profile_override_set_param(uint32_t param,
+						  uint32_t value)
+{
+	return EC_RES_INVALID_PARAM;
+}
diff --git a/zephyr/program/trogdor/lazor/BUILD.py b/zephyr/program/trogdor/lazor/BUILD.py
new file mode 100644
index 0000000000..ca1a26bdcf
--- /dev/null
+++ b/zephyr/program/trogdor/lazor/BUILD.py
@@ -0,0 +1,25 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Define zmake projects for lazor."""
+
+register_npcx_project(
+    project_name="lazor",
+    zephyr_board="npcx7",
+    dts_overlays=[
+        "adc.dts",
+        "battery.dts",
+        "display.dts",
+        "gpio.dts",
+        "i2c.dts",
+        "host_interface_npcx.dts",
+        "interrupts.dts",
+        "keyboard.dts",
+        "led.dts",
+        "motionsense.dts",
+        "pwm_led.dts",
+        "usbc.dts",
+        "default_gpio_pinctrl.dts",
+    ],
+)
diff --git a/zephyr/program/trogdor/lazor/CMakeLists.txt b/zephyr/program/trogdor/lazor/CMakeLists.txt
new file mode 100644
index 0000000000..b6d5024707
--- /dev/null
+++ b/zephyr/program/trogdor/lazor/CMakeLists.txt
@@ -0,0 +1,23 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(lazor)
+
+cros_ec_library_include_directories(include)
+
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC
+  "src/power.c"
+  "src/usb_pd_policy.c"
+  "src/usbc_config.c")
+
+zephyr_library_sources(
+  "src/sku.c"
+  "src/switchcap.c")
+
+# Board specific implementation
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_I2C
+  "src/i2c.c")
diff --git a/zephyr/program/trogdor/lazor/adc.dts b/zephyr/program/trogdor/lazor/adc.dts
new file mode 100644
index 0000000000..b834001587
--- /dev/null
+++ b/zephyr/program/trogdor/lazor/adc.dts
@@ -0,0 +1,48 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/dt-bindings/adc/adc.h>
+
+/ {
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		vbus {
+			enum-name = "ADC_VBUS";
+			io-channels = <&adc0 1>;
+			/* Measure VBUS through a 1/10 voltage divider */
+			mul = <10>;
+		};
+		amon_bmon {
+			enum-name = "ADC_AMON_BMON";
+			io-channels = <&adc0 2>;
+			/*
+			 * Adapter current output or battery charging/
+			 * discharging current (uV) 18x amplification on
+			 * charger side.
+			 */
+			mul = <1000>;
+			div = <18>;
+		};
+		psys {
+			enum-name = "ADC_PSYS";
+			io-channels = <&adc0 3>;
+			/*
+			 * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor,
+			 * to read 0.8V @ 99 W, i.e. 124000 uW/mV.
+			 */
+			mul = <124000>;
+		};
+	};
+
+};
+
+&adc0 {
+	status = "okay";
+	pinctrl-0 = <&adc0_chan1_gp44
+		     &adc0_chan2_gp43
+		     &adc0_chan3_gp42>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/trogdor/lazor/battery.dts b/zephyr/program/trogdor/lazor/battery.dts
new file mode 100644
index 0000000000..2b17dd4761
--- /dev/null
+++ b/zephyr/program/trogdor/lazor/battery.dts
@@ -0,0 +1,24 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	batteries {
+		default_battery: ap16l5j {
+			compatible = "panasonic,ap16l5j", "battery-smart";
+		};
+		ap16l5j_009 {
+			compatible = "panasonic,ap16l5j-009", "battery-smart";
+		};
+		ap16l8j {
+			compatible = "lgc,ap16l8j", "battery-smart";
+		};
+		lgc_ap18c8k {
+			compatible = "lgc,ap18c8k", "battery-smart";
+		};
+		murata_ap18c4k {
+			compatible = "murata,ap18c4k", "battery-smart";
+		};
+	};
+};
diff --git a/zephyr/program/trogdor/lazor/default_gpio_pinctrl.dts b/zephyr/program/trogdor/lazor/default_gpio_pinctrl.dts
new file mode 100644
index 0000000000..1819bdbc3e
--- /dev/null
+++ b/zephyr/program/trogdor/lazor/default_gpio_pinctrl.dts
@@ -0,0 +1,43 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Adds the &alt1_no_lpc_espi setting over the NPCX7 default setting. */
+&{/def-io-conf-list} {
+	pinmux = <&alt0_gpio_no_spip
+		  &alt0_gpio_no_fpip
+		  &alt1_no_pwrgd
+		  &alt1_no_lpc_espi
+		  &alta_no_peci_en
+		  &altd_npsl_in1_sl
+		  &altd_npsl_in2_sl
+		  &altd_psl_in3_sl
+		  &altd_psl_in4_sl
+		  &alt7_no_ksi0_sl
+		  &alt7_no_ksi1_sl
+		  &alt7_no_ksi2_sl
+		  &alt7_no_ksi3_sl
+		  &alt7_no_ksi4_sl
+		  &alt7_no_ksi5_sl
+		  &alt7_no_ksi6_sl
+		  &alt7_no_ksi7_sl
+		  &alt8_no_kso00_sl
+		  &alt8_no_kso01_sl
+		  &alt8_no_kso02_sl
+		  &alt8_no_kso03_sl
+		  &alt8_no_kso04_sl
+		  &alt8_no_kso05_sl
+		  &alt8_no_kso06_sl
+		  &alt8_no_kso07_sl
+		  &alt9_no_kso08_sl
+		  &alt9_no_kso09_sl
+		  &alt9_no_kso10_sl
+		  &alt9_no_kso11_sl
+		  &alt9_no_kso12_sl
+		  &alt9_no_kso13_sl
+		  &alt9_no_kso14_sl
+		  &alt9_no_kso15_sl
+		  &alta_no_kso16_sl
+		  &alta_no_kso17_sl >;
+};
diff --git a/zephyr/program/trogdor/lazor/display.dts b/zephyr/program/trogdor/lazor/display.dts
new file mode 100644
index 0000000000..65d3a2d91b
--- /dev/null
+++ b/zephyr/program/trogdor/lazor/display.dts
@@ -0,0 +1,18 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	displight {
+		compatible = "cros-ec,displight";
+		pwms = <&pwm5 0 PWM_HZ(4800) PWM_POLARITY_NORMAL>;
+		generic-pwm-channel = <1>;
+	};
+};
+
+&pwm5 {
+	status = "okay";
+	pinctrl-0 = <&pwm5_gpb7>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/trogdor/lazor/gpio.dts b/zephyr/program/trogdor/lazor/gpio.dts
new file mode 100644
index 0000000000..6cde7e644d
--- /dev/null
+++ b/zephyr/program/trogdor/lazor/gpio.dts
@@ -0,0 +1,314 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/wake_mask_event_defines.h>
+
+/ {
+	aliases {
+		gpio-wp = &gpio_ec_wp_odl;
+		gpio-kbd-kso2 = &gpio_ec_kso_02_inv;
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		gpio_usb_c0_pd_int_odl: usb_c0_pd_int_odl {
+			gpios = <&gpioe 0 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_USB_C0_PD_INT_ODL";
+		};
+		gpio_usb_c1_pd_int_odl: usb_c1_pd_int_odl {
+			gpios = <&gpiof 5 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_USB_C1_PD_INT_ODL";
+		};
+		gpio_usb_c0_swctl_int_odl: usb_c0_swctl_int_odl {
+			gpios = <&gpio0 3 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C0_SWCTL_INT_ODL";
+		};
+		gpio_usb_c1_swctl_int_odl: usb_c1_swctl_int_odl {
+			gpios = <&gpio4 0 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C1_SWCTL_INT_ODL";
+		};
+		gpio_usb_c0_bc12_int_l: usb_c0_bc12_int_l {
+			gpios = <&gpio6 1 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_usb_c1_bc12_int_l: usb_c1_bc12_int_l {
+			gpios = <&gpio8 2 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_usb_a0_oc_odl: usb_a0_oc_odl {
+			gpios = <&gpiod 1 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_acok_od: acok_od {
+			gpios = <&gpio0 0 GPIO_INPUT>;
+			enum-name = "GPIO_AC_PRESENT";
+		};
+		gpio_ccd_mode_odl: ccd_mode_odl {
+			gpios = <&gpioe 3 GPIO_INPUT>;
+			enum-name = "GPIO_CCD_MODE_ODL";
+		};
+		gpio_ec_pwr_btn_odl: ec_pwr_btn_odl {
+			gpios = <&gpio0 1 GPIO_INPUT>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		gpio_ec_voldn_btn_odl: ec_voldn_btn_odl {
+			gpios = <&gpio7 0 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_DOWN_L";
+		};
+		gpio_ec_volup_btn_odl: ec_volup_btn_odl {
+			gpios = <&gpiof 2 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_UP_L";
+		};
+		gpio_ec_wp_odl: ec_wp_odl {
+			gpios = <&gpioa 1 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_lid_open_ec: lid_open_ec {
+			gpios = <&gpiod 2 GPIO_INPUT>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+		gpio_ap_rst_l: ap_rst_l {
+			gpios = <&gpioc 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+			enum-name = "GPIO_AP_RST_L";
+		};
+		gpio_ps_hold: ps_hold {
+			gpios = <&gpioa 4 GPIO_INPUT_PULL_DOWN>;
+			enum-name = "GPIO_PS_HOLD";
+		};
+		gpio_ap_suspend: ap_suspend {
+			gpios = <&gpio5 7 GPIO_INPUT>;
+			enum-name = "GPIO_AP_SUSPEND";
+		};
+		gpio_deprecated_ap_rst_req: deprecated_ap_rst_req {
+			gpios = <&gpioc 2 (GPIO_INPUT_PULL_DOWN | GPIO_VOLTAGE_1P8)>;
+			enum-name = "GPIO_DEPRECATED_AP_RST_REQ";
+		};
+		gpio_power_good: power_good {
+			gpios = <&gpio5 4 GPIO_INPUT_PULL_DOWN>;
+			enum-name = "GPIO_POWER_GOOD";
+		};
+		gpio_warm_reset_l: warm_reset_l {
+			gpios = <&gpiof 4 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+			enum-name = "GPIO_WARM_RESET_L";
+		};
+		ap_ec_spi_cs_l {
+			gpios = <&gpio5 3 GPIO_INPUT_PULL_DOWN>;
+		};
+		gpio_tablet_mode_l: tablet_mode_l {
+			gpios = <&gpioc 6 GPIO_INPUT>;
+			enum-name = "GPIO_TABLET_MODE_L";
+		};
+		gpio_accel_gyro_int_l: accel_gyro_int_l {
+			gpios = <&gpioa 0 GPIO_INPUT>;
+		};
+		/*
+		 * Note, this signal is active low when used as the ln9310
+		 * interrupt input, and active high when used as the da9313
+		 * power good input.  The board code clears the active low
+		 * flag when da9313 is detected.
+		 */
+		gpio_switchcap_pg_int_l: gpio_da9313_gpio0: da9313_gpio0 {
+			gpios = <&gpioe 2 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_DA9313_GPIO0";
+		};
+		gpio_ec_rst_odl: ec_rst_odl {
+			gpios = <&gpio0 2 GPIO_INPUT>;
+		};
+		ec_entering_rw {
+			gpios = <&gpioe 1 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_ENTERING_RW";
+		};
+		ec_batt_pres_odl {
+			gpios = <&gpioe 5 GPIO_INPUT>;
+			enum-name = "GPIO_BATT_PRES_ODL";
+		};
+		pm845_resin_l {
+			gpios = <&gpio3 2 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_PMIC_RESIN_L";
+		};
+		pmic_kpd_pwr_odl {
+			gpios = <&gpiod 6 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_PMIC_KPD_PWR_ODL";
+		};
+		ec_int_l {
+			gpios = <&gpioa 2 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_EC_INT_L";
+		};
+		qsip_on {
+			gpios = <&gpio5 0 GPIO_OUTPUT_LOW>;
+		};
+		gpio_hibernate_l: hibernate_l {
+			gpios = <&gpio5 2 GPIO_OUTPUT_HIGH>;
+		};
+		gpio_switchcap_on: switchcap_on {
+			gpios = <&gpiod 5 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_SWITCHCAP_ON";
+		};
+		gpio_vbob_en: vbob_en {
+			gpios = <&gpiod 3 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_VBOB_EN";
+		};
+		gpio_en_pp3300_a: en_pp3300_a {
+			gpios = <&gpioa 6 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_EN_PP3300_A";
+		};
+		gpio_en_pp5000_a: en_pp5000_a {
+			gpios = <&gpio6 7 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_EN_PP5000";
+		};
+		ec_bl_disable_l {
+			gpios = <&gpiob 6 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_ENABLE_BACKLIGHT";
+		};
+		gpio_lid_accel_int_l: lid_accel_int_l {
+			gpios = <&gpio5 6 GPIO_INPUT>;
+		};
+		trackpad_int_gate {
+			gpios = <&gpio7 4 GPIO_OUTPUT_LOW>;
+		};
+		gpio_usb_c0_pd_rst_l: usb_c0_pd_rst_l {
+			gpios = <&gpiof 1 (GPIO_ODR_HIGH | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_usb_c1_pd_rst_l: usb_c1_pd_rst_l {
+			gpios = <&gpioe 4 (GPIO_ODR_HIGH | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_dp_mux_oe_l: dp_mux_oe_l {
+			gpios = <&gpio9 6 GPIO_ODR_HIGH>;
+		};
+		gpio_dp_mux_sel: dp_mux_sel {
+			gpios = <&gpio4 5 GPIO_OUTPUT_LOW>;
+		};
+		gpio_dp_hot_plug_det: dp_hot_plug_det {
+			gpios = <&gpio9 5 GPIO_OUTPUT_LOW>;
+		};
+		gpio_en_usb_a_5v: en_usb_a_5v {
+			gpios = <&gpio8 6 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_EN_USB_A_5V";
+		};
+		usb_a_cdp_ilim_en {
+			gpios = <&gpio7 5 GPIO_OUTPUT_HIGH>;
+		};
+		gpio_ec_chg_led_y_c1: ec_chg_led_y_c1 {
+			gpios = <&gpioc 3 GPIO_OUTPUT_LOW>;
+		};
+		gpio_ec_chg_led_b_c1: ec_chg_led_b_c1 {
+			gpios = <&gpioc 4 GPIO_OUTPUT_LOW>;
+		};
+		gpio_brd_id0: brd_id0 {
+			gpios = <&gpioc 7 GPIO_INPUT>;
+			enum-name = "GPIO_BOARD_VERSION1";
+		};
+		gpio_brd_id1: brd_id1 {
+			gpios = <&gpio9 3 GPIO_INPUT>;
+			enum-name = "GPIO_BOARD_VERSION2";
+		};
+		gpio_brd_id2: brd_id2 {
+			gpios = <&gpio6 3 GPIO_INPUT>;
+			enum-name = "GPIO_BOARD_VERSION3";
+		};
+		gpio_sku_id0: sku_id0 {
+			gpios = <&gpiof 0 GPIO_INPUT>;
+		};
+		gpio_sku_id1: sku_id1 {
+			gpios = <&gpio4 1 GPIO_INPUT>;
+		};
+		gpio_sku_id2: sku_id2 {
+			gpios = <&gpiod 4 GPIO_INPUT>;
+		};
+		arm_x86 {
+			gpios = <&gpio6 6 GPIO_OUTPUT_LOW>;
+		};
+		ec-i2c-sensor-scl {
+			gpios = <&gpiob 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		ec-i2c-sensor-sda {
+			gpios = <&gpiob 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		gpio_ec_kso_02_inv: ec_kso_02_inv {
+			gpios = <&gpio1 7 (GPIO_OUTPUT_LOW | GPIO_ACTIVE_LOW)>;
+		};
+	};
+
+	usba-port-enable-list {
+		compatible = "cros-ec,usba-port-enable-pins";
+		enable-pins = <&gpio_en_usb_a_5v>;
+	};
+
+	hibernate-wake-pins {
+		compatible = "cros-ec,hibernate-wake-pins";
+		wakeup-irqs = <
+			&int_ac_present
+			&int_power_button
+			&int_lid_open
+			&int_ec_rst
+		>;
+	};
+
+	ec-mkbp-host-event-wakeup-mask {
+		compatible = "cros-ec,mkbp-host-event-wakeup-mask";
+		wakeup-mask = <(
+			HOST_EVENT_LID_OPEN |
+			HOST_EVENT_POWER_BUTTON |
+			HOST_EVENT_AC_CONNECTED |
+			HOST_EVENT_AC_DISCONNECTED |
+			HOST_EVENT_HANG_DETECT |
+			HOST_EVENT_RTC |
+			HOST_EVENT_MODE_CHANGE |
+			HOST_EVENT_DEVICE)>;
+	};
+
+	ec-mkbp-event-wakeup-mask {
+		compatible = "cros-ec,mkbp-event-wakeup-mask";
+		wakeup-mask = <(MKBP_EVENT_KEY_MATRIX |
+				MKBP_EVENT_HOST_EVENT |
+				MKBP_EVENT_SENSOR_FIFO)>;
+	};
+
+	gpio_id_sku: sku {
+		compatible = "cros-ec,gpio-id";
+		bits  = <
+			&gpio_sku_id0
+			&gpio_sku_id1
+			&gpio_sku_id2
+		>;
+		system = "binary";
+	};
+
+	gpio_id_board: board {
+		compatible = "cros-ec,gpio-id";
+		bits  = <
+			&gpio_brd_id0
+			&gpio_brd_id1
+			&gpio_brd_id2
+		>;
+		system = "binary_first_base3";
+	};
+
+	unused-pins {
+		compatible = "unused-gpios";
+		unused-gpios =
+			<&gpio5 1 0>,
+			<&gpiod 0 0>,
+			<&gpiof 3 0>,
+			<&gpio0 4 0>,
+			<&gpioc 0 0>,
+			<&gpioa 7 0>,
+			<&gpio8 3 0>,
+			<&gpio8 1 0>,
+			<&gpio3 7 0>,
+			<&gpio7 6 0>,
+			<&gpio3 4 0>,
+			<&gpioc 5 0>,
+			<&gpioa 3 0>,
+			<&gpio7 3 0>,
+			<&gpiod 7 0>,
+			<&gpioa 5 0>,
+			<&gpiob 0 0>,
+			<&gpio9 4 0>,
+			<&gpiob 1 0>,
+			<&gpio6 2 0>,
+			<&gpio3 5 0>,
+			<&gpio9 7 0>,
+			<&gpio6 0 0>,
+			<&gpio7 2 0>;
+	};
+};
diff --git a/zephyr/program/trogdor/lazor/host_interface_npcx.dts b/zephyr/program/trogdor/lazor/host_interface_npcx.dts
new file mode 100644
index 0000000000..b691893854
--- /dev/null
+++ b/zephyr/program/trogdor/lazor/host_interface_npcx.dts
@@ -0,0 +1,12 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* host interface */
+&shi0 {
+	status = "okay";
+	pinctrl-0 = <&shi_gp46_47_53_55>;
+	pinctrl-1 = <&shi_gpio_gp46_47_53_55>;
+	pinctrl-names = "default", "sleep";
+};
diff --git a/zephyr/program/trogdor/lazor/i2c.dts b/zephyr/program/trogdor/lazor/i2c.dts
new file mode 100644
index 0000000000..e10ed04a0e
--- /dev/null
+++ b/zephyr/program/trogdor/lazor/i2c.dts
@@ -0,0 +1,165 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		i2c_power: power {
+			i2c-port = <&i2c0_0>;
+			remote-port = <0>;
+			enum-names = "I2C_PORT_POWER",
+				"I2C_PORT_BATTERY",
+				"I2C_PORT_VIRTUAL_BATTERY",
+				"I2C_PORT_CHARGER";
+		};
+		i2c_tcpc0: tcpc0 {
+			i2c-port = <&i2c1_0>;
+			enum-names = "I2C_PORT_TCPC0";
+		};
+		i2c_tcpc1: tcpc1 {
+			i2c-port = <&i2c2_0>;
+			enum-names = "I2C_PORT_TCPC1";
+		};
+		i2c_eeprom: eeprom {
+			i2c-port = <&i2c5_0>;
+			enum-names = "I2C_PORT_EEPROM";
+		};
+		i2c_sensor: sensor {
+			i2c-port = <&i2c7_0>;
+			enum-names = "I2C_PORT_SENSOR",
+				"I2C_PORT_ACCEL";
+		};
+	};
+
+};
+
+&i2c0_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>;
+	pinctrl-names = "default";
+
+	bc12_port0: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+		irq = <&int_usb_c0_bc12>;
+	};
+
+	charger: isl923x@9 {
+		compatible = "intersil,isl923x";
+		status = "okay";
+		reg = <0x9>;
+	};
+};
+
+&i2c_ctrl0 {
+	status = "okay";
+};
+
+&i2c1_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+	pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>;
+	pinctrl-names = "default";
+
+	ppc_port0: sn5s330@40 {
+		compatible = "ti,sn5s330";
+		status = "okay";
+		reg = <0x40>;
+	};
+
+	tcpc_port0: ps8xxx@b {
+		compatible = "parade,ps8xxx";
+		status = "okay";
+		reg = <0xb>;
+		/* a duplicate of the <&gpio_usb_c0_pd_int_odl> node in
+		 * "named-gpios". This is the Zephyr preferred style,
+		 * the "named-gpios" node will be dealt with at a later date.
+		 */
+		irq-gpios = <&gpioe 0 GPIO_ACTIVE_LOW>;
+		/* a duplicate of the <&gpio_usb_c0_pd_rst_l> node in
+		 * "named-gpios". This is the Zephyr preferred style,
+		 * the "named-gpios" node will be dealt with at a later date.
+		 */
+		rst-gpios = <&gpiof 1 (GPIO_OPEN_DRAIN | GPIO_ACTIVE_LOW)>;
+	};
+};
+
+&i2c_ctrl1 {
+	status = "okay";
+};
+
+&i2c2_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+	pinctrl-0 = <&i2c2_0_sda_scl_gp91_92>;
+	pinctrl-names = "default";
+
+	ppc_port1: sn5s330@40{
+		compatible = "ti,sn5s330";
+		status = "okay";
+		reg = <0x40>;
+	};
+
+	tcpc_port1: ps8xxx@b {
+		compatible = "parade,ps8xxx";
+		status = "okay";
+		reg = <0xb>;
+		/* a duplicate of the <&gpio_usb_c1_pd_int_odl> node in
+		 * "named-gpios". This is the Zephyr preferred style,
+		 * the "named-gpios" node will be dealt with at a later date.
+		 */
+		irq-gpios = <&gpiof 5 GPIO_ACTIVE_LOW>;
+		/* a duplicate of the <&gpio_usb_c1_pd_rst_l> node in
+		 * "named-gpios". This is the Zephyr preferred style,
+		 * the "named-gpios" node will be dealt with at a later date.
+		 */
+		rst-gpios = <&gpioe 4 (GPIO_OPEN_DRAIN | GPIO_ACTIVE_LOW)>;
+	};
+};
+
+&i2c_ctrl2 {
+	status = "okay";
+};
+
+&i2c3_0 {
+	/* Not used as no WLC connected */
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&i2c_ctrl3 {
+	status = "okay";
+};
+
+&i2c5_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c5_0_sda_scl_gp33_36>;
+	pinctrl-names = "default";
+
+	bc12_port1: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+		irq = <&int_usb_c1_bc12>;
+	};
+};
+
+&i2c_ctrl5 {
+	status = "okay";
+};
+
+&i2c7_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>;
+	pinctrl-names = "default";
+};
+
+&i2c_ctrl7 {
+	status = "okay";
+};
diff --git a/zephyr/program/trogdor/lazor/include/sku.h b/zephyr/program/trogdor/lazor/include/sku.h
new file mode 100644
index 0000000000..76825bbba1
--- /dev/null
+++ b/zephyr/program/trogdor/lazor/include/sku.h
@@ -0,0 +1,17 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Lazor board-specific SKU configuration */
+
+#ifndef __ZEPHYR_LAZOR_SKU_H
+#define __ZEPHYR_LAZOR_SKU_H
+
+int board_get_version(void);
+int board_is_clamshell(void);
+int board_has_da9313(void);
+int board_has_ln9310(void);
+int board_has_buck_ic(void);
+
+#endif /* __ZEPHYR_LAZOR_SKU_H */
diff --git a/zephyr/program/trogdor/lazor/interrupts.dts b/zephyr/program/trogdor/lazor/interrupts.dts
new file mode 100644
index 0000000000..90e20b8e48
--- /dev/null
+++ b/zephyr/program/trogdor/lazor/interrupts.dts
@@ -0,0 +1,130 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	aliases {
+		int-wp = &int_wp;
+	};
+
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_ac_present: ac_present {
+			irq-pin = <&gpio_acok_od>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "extpower_interrupt";
+		};
+		int_lid_open: lid_open {
+			irq-pin = <&gpio_lid_open_ec>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "lid_interrupt";
+		};
+		int_wp: wp {
+			irq-pin = <&gpio_ec_wp_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "switch_interrupt";
+		};
+		int_power_button: power_button {
+			irq-pin = <&gpio_ec_pwr_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_button_interrupt";
+		};
+		int_volume_up: volume_up {
+			irq-pin = <&gpio_ec_volup_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+		int_volume_down: volume_down {
+			irq-pin = <&gpio_ec_voldn_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+		/*
+		 * Note this is an active low input, so
+		 * the direction is from logical low to
+		 * logical high.
+		 */
+		int_switchcap_pg: switchcap_pg {
+			irq-pin = <&gpio_switchcap_pg_int_l>;
+			flags = <GPIO_INT_EDGE_RISING>;
+			handler = "ln9310_interrupt";
+		};
+		int_ap_rst: ap_rst {
+			irq-pin = <&gpio_ap_rst_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "chipset_ap_rst_interrupt";
+		};
+		int_ap_suspend: ap_suspend {
+			irq-pin = <&gpio_ap_suspend>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_deprecated_ap_rst_req: deprecated_ap_rst_req {
+			irq-pin = <&gpio_deprecated_ap_rst_req>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_power_good: power_good {
+			irq-pin = <&gpio_power_good>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "chipset_power_good_interrupt";
+		};
+		int_ps_hold: ps_hold {
+			irq-pin = <&gpio_ps_hold>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_warm_reset: warm_reset {
+			irq-pin = <&gpio_warm_reset_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "chipset_warm_reset_interrupt";
+		};
+		int_usb_c0_swctl: usb_c0_swctl {
+			irq-pin = <&gpio_usb_c0_swctl_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "ppc_interrupt";
+		};
+		int_usb_c1_swctl: usb_c1_swctl {
+			irq-pin = <&gpio_usb_c1_swctl_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "ppc_interrupt";
+		};
+		int_usb_c0_bc12: usb_c0_bc12 {
+			irq-pin = <&gpio_usb_c0_bc12_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "usb0_evt";
+		};
+		int_usb_c1_bc12: usb_c1_bc12 {
+			irq-pin = <&gpio_usb_c1_bc12_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "usb1_evt";
+		};
+		int_usb_a0_oc: usb_a0_oc {
+			irq-pin = <&gpio_usb_a0_oc_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "usba_oc_interrupt";
+		};
+		int_ccd_mode: ccd_mode {
+			irq-pin = <&gpio_ccd_mode_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "board_connect_c0_sbu";
+		};
+		int_accel: accel {
+			irq-pin = <&gpio_accel_gyro_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "bmi160_interrupt";
+		};
+		int_tablet_mode: tablet_mode {
+			irq-pin = <&gpio_tablet_mode_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "gmr_tablet_switch_isr";
+		};
+		int_ec_rst: ec_rst {
+			irq-pin = <&gpio_ec_rst_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "wake_isr";
+		};
+	};
+};
diff --git a/zephyr/program/trogdor/lazor/keyboard.dts b/zephyr/program/trogdor/lazor/keyboard.dts
new file mode 100644
index 0000000000..1c463d1d7e
--- /dev/null
+++ b/zephyr/program/trogdor/lazor/keyboard.dts
@@ -0,0 +1,65 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	cros-keyscan {
+		compatible = "cros-ec,keyscan";
+
+		actual-key-mask = <
+			0x14	/* C0 */
+			0xff	/* C1 */
+			0xff	/* C2 */
+			0xff	/* C3 */
+			0xff	/* C4 */
+			0xf5	/* C5 */
+			0xff	/* C6 */
+			0xa4	/* C7 */
+			0xff	/* C8 */
+			0xfe	/* C9 */
+			0x55	/* C10 */
+			0xfa	/* C11 */
+			0xca	/* C12 */
+			>;
+	};
+
+	kblight {
+		compatible = "cros-ec,kblight-pwm";
+		pwms = <&pwm3 0 PWM_KHZ(10) PWM_POLARITY_NORMAL>;
+		generic-pwm-channel = <0>;
+	};
+};
+
+&pwm3 {
+	status = "okay";
+	pinctrl-0 = <&pwm3_gp80>;
+	pinctrl-names = "default";
+};
+
+&cros_kb_raw {
+	status = "okay";
+	/* No KSO2 (it's inverted and implemented by GPIO) */
+	pinctrl-0 = <&ksi0_gp31
+		     &ksi1_gp30
+		     &ksi2_gp27
+		     &ksi3_gp26
+		     &ksi4_gp25
+		     &ksi5_gp24
+		     &ksi6_gp23
+		     &ksi7_gp22
+		     &kso00_gp21
+		     &kso01_gp20
+		     &kso03_gp16
+		     &kso04_gp15
+		     &kso05_gp14
+		     &kso06_gp13
+		     &kso07_gp12
+		     &kso08_gp11
+		     &kso09_gp10
+		     &kso10_gp07
+		     &kso11_gp06
+		     &kso12_gp05
+		     >;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/trogdor/lazor/led.dts b/zephyr/program/trogdor/lazor/led.dts
new file mode 100644
index 0000000000..7694de89ff
--- /dev/null
+++ b/zephyr/program/trogdor/lazor/led.dts
@@ -0,0 +1,90 @@
+/ {
+	led-colors {
+		compatible = "cros-ec,led-policy";
+
+		power-state-charge {
+			charge-state = "LED_PWRS_CHARGE";
+
+			color-0 {
+				led-color = <&color_amber>;
+			};
+		};
+
+		power-state-discharge-s0 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S0";
+
+			color-0 {
+				led-color = <&color_blue>;
+			};
+		};
+
+		power-state-discharge-s3 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S3";
+
+			/* Amber 1 sec, off 3 sec */
+			color-0 {
+				led-color = <&color_amber>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <3000>;
+			};
+		};
+
+		power-state-discharge-s5 {
+			charge-state = "LED_PWRS_DISCHARGE";
+			chipset-state = "POWER_S5";
+
+			color-0 {
+				led-color = <&color_off>;
+			};
+		};
+
+		power-state-error {
+			charge-state = "LED_PWRS_ERROR";
+
+			/* Amber 1 sec, off 1 sec */
+			color-0 {
+				led-color = <&color_amber>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <1000>;
+			};
+		};
+
+		power-state-near-full {
+			charge-state = "LED_PWRS_CHARGE_NEAR_FULL";
+
+			color-0 {
+				led-color = <&color_blue>;
+			};
+		};
+
+		power-state-forced-idle {
+			charge-state = "LED_PWRS_FORCED_IDLE";
+
+			/* Blue 2 sec, Amber 2 sec */
+			color-0 {
+				led-color = <&color_blue>;
+				period-ms = <2000>;
+			};
+			color-1 {
+				led-color = <&color_amber>;
+				period-ms = <2000>;
+			};
+		};
+
+		power-state-idle {
+			charge-state = "LED_PWRS_IDLE";
+
+			color-0 {
+				led-color = <&color_blue>;
+			};
+		};
+	};
+};
diff --git a/zephyr/program/trogdor/lazor/motionsense.dts b/zephyr/program/trogdor/lazor/motionsense.dts
new file mode 100644
index 0000000000..75fe31b997
--- /dev/null
+++ b/zephyr/program/trogdor/lazor/motionsense.dts
@@ -0,0 +1,181 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/motionsense/utils.h>
+
+
+/ {
+	aliases {
+		/*
+		 * motion sense's <>_INT_EVENT is handled
+		 * by alias. Using the alias, each driver creates
+		 * its own <>_INT_EVENT.
+		 */
+		bmi160-int = &base_accel;
+	};
+
+	/*
+	 * Declare mutexes used by sensor drivers.
+	 * A mutex node is used to create an instance of mutex_t.
+	 * A mutex node is referenced by a sensor node if the
+	 * corresponding sensor driver needs to use the
+	 * instance of the mutex.
+	 */
+	motionsense-mutex {
+		compatible = "cros-ec,motionsense-mutex";
+		lid_mutex: lid-mutex {
+		};
+
+		mutex_bmi160: bmi160-mutex {
+		};
+	};
+
+	/* Rotation matrix used by drivers. */
+	motionsense-rotation-ref {
+		compatible = "cros-ec,motionsense-rotation-ref";
+		lid_rot_ref: lid-rotation-ref {
+			mat33 = <(-1) 0 0
+				 0 (-1) 0
+				 0 0 1>;
+		};
+
+		base_rot_ref: base-rotation-ref {
+			mat33 = <1 0 0
+				 0 (-1) 0
+				 0 0 (-1)>;
+		};
+	};
+
+	/*
+	 * Driver specific data. A driver-specific data can be shared with
+	 * different motion sensors while they are using the same driver.
+	 *
+	 * If a node's compatible starts with "cros-ec,accelgyro-", it is for
+	 * a common structure defined in accelgyro.h.
+	 * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for
+	 * "struct als_drv_data_t" in accelgyro.h
+	 */
+	motionsense-sensor-data {
+		bma255_data: bma255-drv-data {
+			compatible = "cros-ec,drvdata-bma255";
+			status = "okay";
+		};
+
+		bmi160_data: bmi160-drv-data {
+			compatible = "cros-ec,drvdata-bmi160";
+			status = "okay";
+		};
+
+		kx022_data: kx022-drv-data {
+			compatible = "cros-ec,drvdata-kionix";
+			status = "okay";
+		};
+	};
+
+	/*
+	 * List of motion sensors that creates motion_sensors array.
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
+	 * motion sensor IDs for lid angle calculation.
+	 */
+	motionsense-sensor {
+		lid_accel: lid-accel {
+			compatible = "cros-ec,bma255";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3_S5";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&lid_mutex>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&lid_rot_ref>;
+			default-range = <2>;
+			drv-data = <&bma255_data>;
+			i2c-spi-addr-flags = "BMA2x2_I2C_ADDR1_FLAGS";
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_accel: base-accel {
+			compatible = "cros-ec,bmi160-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3_S5";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&mutex_bmi160>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&bmi160_data>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base-gyro {
+			compatible = "cros-ec,bmi160-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3_S5";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&mutex_bmi160>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&bmi160_data>;
+		};
+	};
+
+	/*
+	 * List of alternative motion sensors that creates
+	 * motion_sensors_alt array.
+	 */
+	motionsense-sensor-alt {
+		alt_lid_accel {
+			compatible = "cros-ec,kx022";
+			status = "okay";
+			active-mask = "SENSOR_ACTIVE_S0_S3_S5";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&lid_mutex>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&lid_rot_ref>;
+			drv-data = <&kx022_data>;
+			alternate-for = <&lid_accel>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+	};
+
+	motionsense-sensor-info {
+		compatible = "cros-ec,motionsense-sensor-info";
+
+		/*
+		 * list of GPIO interrupts that have to
+		 * be enabled at initial stage
+		 */
+		sensor-irqs = <&int_accel>;
+		/* list of sensors in force mode */
+		accel-force-mode-sensors = <&lid_accel>;
+	};
+};
diff --git a/zephyr/program/trogdor/lazor/prj.conf b/zephyr/program/trogdor/lazor/prj.conf
new file mode 100644
index 0000000000..b94b4c110e
--- /dev/null
+++ b/zephyr/program/trogdor/lazor/prj.conf
@@ -0,0 +1,140 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_CROS_EC=y
+#
+# Lazor actually has a NPCX7M6FC, but
+# the NPCX7M7FC is actually the same die, without the
+# extra RAM being tested. The code size really could
+# do with the extra space, so we pretend the EC is the
+# part with the larger RAM. YMMV.
+#
+CONFIG_SOC_NPCX7M7FC=y
+CONFIG_SOC_SERIES_NPCX7=y
+CONFIG_PLATFORM_EC=y
+CONFIG_PLATFORM_EC_BRINGUP=y
+CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y
+CONFIG_PLATFORM_EC_SWITCH=y
+CONFIG_PLATFORM_EC_LID_SWITCH=y
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=y
+CONFIG_PLATFORM_EC_POWER_BUTTON=y
+
+# PWM
+CONFIG_PWM=y
+
+# Application Processor is Qualcomm SC7180
+CONFIG_AP_ARM_QUALCOMM_SC7180=y
+
+# Board version is selected over GPIO board ID pins.
+CONFIG_PLATFORM_EC_BOARD_VERSION_GPIO=y
+
+# LN9310 Switchcap
+CONFIG_PLATFORM_EC_SWITCHCAP_LN9310=y
+
+# Power Sequencing
+CONFIG_PLATFORM_EC_POWERSEQ=y
+CONFIG_PLATFORM_EC_POWERSEQ_HOST_SLEEP=y
+CONFIG_PLATFORM_EC_POWER_SLEEP_FAILURE_DETECTION=y
+CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK=y
+CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK=y
+
+# Trogdor family does not use EFS2
+CONFIG_PLATFORM_EC_VBOOT_EFS2=n
+
+# MKBP event
+CONFIG_PLATFORM_EC_MKBP_EVENT=y
+CONFIG_PLATFORM_EC_MKBP_USE_GPIO=y
+
+# Keyboard
+CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_MKBP=y
+CONFIG_PLATFORM_EC_MKBP_INPUT_DEVICES=y
+CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED=y
+CONFIG_PLATFORM_EC_VOLUME_BUTTONS=y
+CONFIG_PLATFORM_EC_CMD_BUTTON=y
+
+# Battery
+CONFIG_PLATFORM_EC_I2C_VIRTUAL_BATTERY=y
+CONFIG_PLATFORM_EC_I2C_PASSTHRU_RESTRICTED=y
+CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y
+CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y
+CONFIG_PLATFORM_EC_CHARGER_ISL9238=y
+CONFIG_PLATFORM_EC_CHARGE_RAMP_HW=y
+CONFIG_PLATFORM_EC_USE_BATTERY_DEVICE_CHEMISTRY=y
+CONFIG_PLATFORM_EC_BATTERY_DEVICE_CHEMISTRY="LION"
+CONFIG_PLATFORM_EC_BATTERY_REVIVE_DISCONNECT=y
+CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y
+CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC_CHARGER=y
+CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON=2
+CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON=10000
+CONFIG_PLATFORM_EC_CHARGER_MIN_INPUT_CURRENT_LIMIT=512
+CONFIG_PLATFORM_EC_CHARGER_PROFILE_OVERRIDE=y
+CONFIG_PLATFORM_EC_CHARGER_PSYS=y
+CONFIG_PLATFORM_EC_CHARGER_PSYS_READ=y
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=20
+CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_ADC_AMON_BMON=y
+
+# USB-C
+CONFIG_PLATFORM_EC_USB_PD_USB32_DRD=n
+CONFIG_PLATFORM_EC_USBC_SS_MUX_DFP_ONLY=y
+CONFIG_PLATFORM_EC_USB_DRP_ACC_TRYSRC=y
+CONFIG_PLATFORM_EC_USB_PD_5V_EN_CUSTOM=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y
+CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y
+CONFIG_PLATFORM_EC_USB_PD_REV30=n
+CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=n
+CONFIG_PLATFORM_EC_USB_PD_USB4=n
+CONFIG_PLATFORM_EC_USB_PD_TCPC_LOW_POWER=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_MULTI_PS8XXX=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8751=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8805=y
+CONFIG_PLATFORM_EC_USB_PD_TCPC_RUNTIME_CONFIG=n
+CONFIG_PLATFORM_EC_USB_MUX_RUNTIME_CONFIG=n
+CONFIG_PLATFORM_EC_USB_PD_LOGGING=y
+
+# USB ID
+# This is allocated specifically for Trogdor
+# http://google3/hardware/standards/usb/
+# TODO(b/183608112): Move to device tree
+CONFIG_PLATFORM_EC_USB_PID=0x5043
+
+# RTC
+CONFIG_PLATFORM_EC_RTC=y
+CONFIG_PLATFORM_EC_HOSTCMD_RTC=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_RTC=y
+
+# EC software sync
+CONFIG_PLATFORM_EC_VBOOT_HASH=y
+
+# Sensors
+CONFIG_PLATFORM_EC_ACCEL_FIFO=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=y
+CONFIG_PLATFORM_EC_GMR_TABLET_MODE=y
+CONFIG_PLATFORM_EC_LID_ANGLE=y
+CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y
+CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=y
+CONFIG_PLATFORM_EC_TABLET_MODE=y
+CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=y
+
+# Sensor Drivers
+CONFIG_PLATFORM_EC_ACCEL_BMA255=y
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI160=y
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y
+
+# Console history
+CONFIG_SHELL_HISTORY=y
+CONFIG_SHELL_CMDS=y
+CONFIG_SHELL_HELP=n
+CONFIG_SHELL_MINIMAL=y
+
+# Taskinfo
+CONFIG_THREAD_MONITOR=y
+CONFIG_KERNEL_SHELL=y
+
+CONFIG_SYSCON=y
+
+# Features should be enabled. But the code RAM is not enough, disable them.
+#CONFIG_PLATFORM_EC_ACCEL_SPOOF_MODE=y
+#CONFIG_PLATFORM_EC_EMULATED_SYSRQ=y
diff --git a/zephyr/program/trogdor/lazor/pwm_led.dts b/zephyr/program/trogdor/lazor/pwm_led.dts
new file mode 100644
index 0000000000..507019f4ef
--- /dev/null
+++ b/zephyr/program/trogdor/lazor/pwm_led.dts
@@ -0,0 +1,54 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	pwmleds {
+		compatible = "pwm-leds";
+		pwm_y: pwm_y {
+			pwms = <&pwm0 0 PWM_HZ(324) PWM_POLARITY_NORMAL>;
+		};
+		pwm_b: pwm_b {
+			pwms = <&pwm2 0 PWM_HZ(324) PWM_POLARITY_NORMAL>;
+		};
+	};
+
+	pwm-led-pins {
+		compatible = "cros-ec,pwm-led-pins";
+
+		battery_led: battery-led {
+			led-id = "EC_LED_ID_BATTERY_LED";
+			led-pwms = <&pwm_y &pwm_b>;
+
+			color_off: color-off {
+				led-color = "LED_OFF";
+				led-values = <0 0>;
+			};
+
+			color_amber: color-amber {
+				led-color = "LED_AMBER";
+				br-color = "EC_LED_COLOR_AMBER";
+				led-values = <100 0>;
+			};
+
+			color_blue: color-blue {
+				led-color = "LED_BLUE";
+				br-color = "EC_LED_COLOR_BLUE";
+				led-values = <0 100>;
+			};
+		};
+	};
+};
+
+&pwm0 {
+	status = "okay";
+	pinctrl-0 = <&pwm0_gpc3>;
+	pinctrl-names = "default";
+};
+
+&pwm2 {
+	status = "okay";
+	pinctrl-0 = <&pwm2_gpc4>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/program/trogdor/lazor/src/hibernate.c b/zephyr/program/trogdor/lazor/src/hibernate.c
new file mode 100644
index 0000000000..388ff1b087
--- /dev/null
+++ b/zephyr/program/trogdor/lazor/src/hibernate.c
@@ -0,0 +1,48 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "sku.h"
+#include "system.h"
+#include "usbc_ppc.h"
+
+void board_hibernate(void)
+{
+	int i;
+
+	if (!board_is_clamshell()) {
+		/*
+		 * Sensors are unpowered in hibernate. Apply PD to the
+		 * interrupt lines such that they don't float.
+		 */
+		gpio_pin_configure_dt(
+			GPIO_DT_FROM_NODELABEL(gpio_accel_gyro_int_l),
+			GPIO_DISCONNECTED);
+		gpio_pin_configure_dt(
+			GPIO_DT_FROM_NODELABEL(gpio_lid_accel_int_l),
+			GPIO_DISCONNECTED);
+	}
+
+	/*
+	 * Board rev 5+ has the hardware fix. Don't need the following
+	 * workaround.
+	 */
+	if (system_get_board_version() >= 5)
+		return;
+
+	/*
+	 * Enable the PPC power sink path before EC enters hibernate;
+	 * otherwise, ACOK won't go High and can't wake EC up. Check the
+	 * bug b/170324206 for details.
+	 */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
+		ppc_vbus_sink_enable(i, 1);
+}
+
+void board_hibernate_late(void)
+{
+	/* Set the hibernate GPIO to turn off the rails */
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_hibernate_l), 0);
+}
diff --git a/zephyr/program/trogdor/lazor/src/i2c.c b/zephyr/program/trogdor/lazor/src/i2c.c
new file mode 100644
index 0000000000..e572bbdf37
--- /dev/null
+++ b/zephyr/program/trogdor/lazor/src/i2c.c
@@ -0,0 +1,17 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "i2c.h"
+#include "i2c/i2c.h"
+
+/* Lazor board specific i2c implementation */
+
+#ifdef CONFIG_PLATFORM_EC_I2C_PASSTHRU_RESTRICTED
+int board_allow_i2c_passthru(const struct i2c_cmd_desc_t *cmd_desc)
+{
+	return (i2c_get_device_for_port(cmd_desc->port) ==
+		i2c_get_device_for_port(I2C_PORT_VIRTUAL_BATTERY));
+}
+#endif
diff --git a/zephyr/program/trogdor/lazor/src/power.c b/zephyr/program/trogdor/lazor/src/power.c
new file mode 100644
index 0000000000..5661fa8049
--- /dev/null
+++ b/zephyr/program/trogdor/lazor/src/power.c
@@ -0,0 +1,59 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "gpio.h"
+#include "power.h"
+#include "task.h"
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/init.h>
+
+#include <ap_power/ap_power.h>
+
+static void board_power_change(struct ap_power_ev_callback *cb,
+			       struct ap_power_ev_data data)
+{
+	switch (data.event) {
+	default:
+		return;
+
+	case AP_POWER_PRE_INIT:
+		/* Turn on the 3.3V rail */
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pp3300_a), 1);
+
+		/* Turn on the 5V rail. */
+#ifdef CONFIG_POWER_PP5000_CONTROL
+		power_5v_enable(task_get_current(), 1);
+#else /* !defined(CONFIG_POWER_PP5000_CONTROL) */
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pp5000_a), 1);
+#endif /* defined(CONFIG_POWER_PP5000_CONTROL) */
+		break;
+
+	case AP_POWER_SHUTDOWN_COMPLETE:
+		/* Turn off the 5V rail. */
+#ifdef CONFIG_POWER_PP5000_CONTROL
+		power_5v_enable(task_get_current(), 0);
+#else /* !defined(CONFIG_POWER_PP5000_CONTROL) */
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pp5000_a), 0);
+#endif /* defined(CONFIG_POWER_PP5000_CONTROL) */
+
+		/* Turn off the 3.3V and 5V rails. */
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pp3300_a), 0);
+		break;
+	}
+}
+
+static int board_power_handler_init(void)
+{
+	static struct ap_power_ev_callback cb;
+
+	/* Setup a suspend/resume callback */
+	ap_power_ev_init_callback(&cb, board_power_change,
+				  AP_POWER_PRE_INIT |
+					  AP_POWER_SHUTDOWN_COMPLETE);
+	ap_power_ev_add_callback(&cb);
+	return 0;
+}
+SYS_INIT(board_power_handler_init, APPLICATION, 1);
diff --git a/zephyr/program/trogdor/lazor/src/sku.c b/zephyr/program/trogdor/lazor/src/sku.c
new file mode 100644
index 0000000000..a6187d422f
--- /dev/null
+++ b/zephyr/program/trogdor/lazor/src/sku.c
@@ -0,0 +1,92 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "config.h"
+#include "console.h"
+#include "driver/ln9310.h"
+#include "hooks.h"
+#include "sku.h"
+#include "system.h"
+#include "tcpm/ps8xxx_public.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+static uint8_t sku_id;
+
+enum board_model {
+	LAZOR,
+	LIMOZEEN,
+	UNKNOWN,
+};
+
+static const char *const model_name[] = {
+	"LAZOR",
+	"LIMOZEEN",
+	"UNKNOWN",
+};
+
+static enum board_model get_model(void)
+{
+	if (sku_id == 0 || sku_id == 1 || sku_id == 2 || sku_id == 3)
+		return LAZOR;
+	if (sku_id == 4 || sku_id == 5 || sku_id == 6)
+		return LIMOZEEN;
+	return UNKNOWN;
+}
+
+/* Read SKU ID from GPIO and initialize variables for board variants */
+static void sku_init(void)
+{
+	sku_id = system_get_sku_id();
+	CPRINTS("SKU: %u (%s)", sku_id, model_name[get_model()]);
+}
+DECLARE_HOOK(HOOK_INIT, sku_init, HOOK_PRIO_POST_I2C);
+
+enum battery_cell_type board_get_battery_cell_type(void)
+{
+	switch (get_model()) {
+	case LIMOZEEN:
+		return BATTERY_CELL_TYPE_3S;
+	default:
+		return BATTERY_CELL_TYPE_UNKNOWN;
+	}
+}
+
+int board_is_clamshell(void)
+{
+	return get_model() == LIMOZEEN;
+}
+
+__override uint16_t board_get_ps8xxx_product_id(int port)
+{
+	/*
+	 * Lazor (SKU_ID: 0, 1, 2, 3) rev 3+ changes TCPC from PS8751 to
+	 * PS8805.
+	 *
+	 * Limozeen (SKU_ID: 4, 5, 6) all-rev uses PS8805.
+	 */
+	if (get_model() == LAZOR && system_get_board_version() < 3)
+		return PS8751_PRODUCT_ID;
+
+	return PS8805_PRODUCT_ID;
+}
+
+int board_has_da9313(void)
+{
+	return get_model() == LAZOR;
+}
+
+int board_has_buck_ic(void)
+{
+	return get_model() == LIMOZEEN && system_get_board_version() >= 8;
+}
+
+int board_has_ln9310(void)
+{
+	return get_model() == LIMOZEEN && system_get_board_version() < 8;
+}
diff --git a/zephyr/program/trogdor/lazor/src/switchcap.c b/zephyr/program/trogdor/lazor/src/switchcap.c
new file mode 100644
index 0000000000..45cce0f498
--- /dev/null
+++ b/zephyr/program/trogdor/lazor/src/switchcap.c
@@ -0,0 +1,136 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "config.h"
+#include "console.h"
+#include "driver/ln9310.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "power/qcom.h"
+#include "sku.h"
+#include "system.h"
+
+#include <zephyr/drivers/gpio.h>
+
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args)
+
+/* LN9310 switchcap */
+const struct ln9310_config_t ln9310_config = {
+	.i2c_port = I2C_PORT_POWER,
+	.i2c_addr_flags = LN9310_I2C_ADDR_0_FLAGS,
+};
+
+static void switchcap_init(void)
+{
+	if (board_has_da9313()) {
+		const struct gpio_dt_spec *da9313_gpio =
+			GPIO_DT_FROM_NODELABEL(gpio_da9313_gpio0);
+		gpio_flags_t flags = da9313_gpio->dt_flags;
+
+		CPRINTS("Use switchcap: DA9313");
+
+		/*
+		 * When the chip in power down mode, it outputs high-Z.
+		 * Set pull-down to avoid floating.  Also use the
+		 * gpio_pin_configure() routine here so we can clear
+		 * the active low flag. gpio_pin_configure_dt() only allows
+		 * setting additional flags.
+		 */
+		flags &= ~GPIO_ACTIVE_LOW;
+		flags |= GPIO_INPUT | GPIO_PULL_DOWN;
+		gpio_pin_configure(da9313_gpio->port, da9313_gpio->pin, flags);
+
+		/*
+		 * Configure DA9313 enable, push-pull output. Don't set the
+		 * level here; otherwise, it will override its value and
+		 * shutdown the switchcap when sysjump to RW.
+		 */
+		gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_switchcap_on),
+				      GPIO_OUTPUT);
+	} else if (board_has_ln9310()) {
+		CPRINTS("Use switchcap: LN9310");
+
+		/* Enable interrupt for LN9310 */
+		gpio_enable_dt_interrupt(
+			GPIO_INT_FROM_NODELABEL(int_switchcap_pg));
+
+		/*
+		 * Configure LN9310 enable, open-drain output. Don't set the
+		 * level here; otherwise, it will override its value and
+		 * shutdown the switchcap when sysjump to RW.
+		 *
+		 * Note that the gpio.inc configures it GPIO_OUT_LOW. When
+		 * sysjump to RW, will output push-pull a short period of
+		 * time. As it outputs LOW, should be fine.
+		 *
+		 * This GPIO changes like:
+		 * (1) EC boots from RO -> high-Z
+		 * (2) GPIO init according to gpio.inc -> push-pull LOW
+		 * (3) This function configures it -> open-drain HIGH
+		 * (4) Power sequence turns on the switchcap -> open-drain LOW
+		 * (5) EC sysjumps to RW
+		 * (6) GPIO init according to gpio.inc -> push-pull LOW
+		 * (7) This function configures it -> open-drain LOW
+		 */
+		gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_switchcap_on),
+				      GPIO_OUTPUT | GPIO_OPEN_DRAIN);
+
+		/* Only configure the switchcap if not sysjump */
+		if (!system_jumped_late()) {
+			/*
+			 * Deassert the enable pin, so the
+			 * switchcap won't be enabled after the switchcap is
+			 * configured from standby mode to switching mode.
+			 */
+			gpio_pin_set_dt(
+				GPIO_DT_FROM_NODELABEL(gpio_switchcap_on), 0);
+			ln9310_init();
+		}
+	} else if (board_has_buck_ic()) {
+		CPRINTS("Use Buck IC");
+	} else {
+		CPRINTS("ERROR: No switchcap solution");
+	}
+}
+DECLARE_HOOK(HOOK_INIT, switchcap_init, HOOK_PRIO_DEFAULT);
+
+void board_set_switchcap_power(int enable)
+{
+	if (board_has_da9313()) {
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_switchcap_on),
+				enable);
+	} else if (board_has_ln9310()) {
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_switchcap_on),
+				enable);
+		ln9310_software_enable(enable);
+	} else if (board_has_buck_ic()) {
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_vbob_en), enable);
+	}
+}
+
+int board_is_switchcap_enabled(void)
+{
+	if (board_has_da9313() || board_has_ln9310())
+		return gpio_pin_get_dt(
+			GPIO_DT_FROM_NODELABEL(gpio_switchcap_on));
+
+	/* Board has buck ic*/
+	return gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_vbob_en));
+}
+
+int board_is_switchcap_power_good(void)
+{
+	if (board_has_da9313())
+		return gpio_pin_get_dt(
+			GPIO_DT_FROM_NODELABEL(gpio_da9313_gpio0));
+	else if (board_has_ln9310())
+		return ln9310_power_good();
+
+	/* Board has buck ic no way to check POWER GOOD */
+	return 1;
+}
diff --git a/zephyr/program/trogdor/lazor/src/usb_pd_policy.c b/zephyr/program/trogdor/lazor/src/usb_pd_policy.c
new file mode 100644
index 0000000000..32e3376ca0
--- /dev/null
+++ b/zephyr/program/trogdor/lazor/src/usb_pd_policy.c
@@ -0,0 +1,261 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "chipset.h"
+#include "console.h"
+#include "system.h"
+#include "usb_mux.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#include <zephyr/drivers/gpio.h>
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+int pd_check_vconn_swap(int port)
+{
+	/* In G3, do not allow vconn swap since PP5000 rail is off */
+	return gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pp5000_a));
+}
+
+static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT];
+#if CONFIG_USB_PD_PORT_MAX_COUNT == 1
+static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5 };
+#else
+static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5,
+							 TYPEC_RP_1A5 };
+#endif
+
+static void board_vbus_update_source_current(int port)
+{
+	/* Both port are controlled by PPC SN5S330. */
+	ppc_set_vbus_source_current_limit(port, vbus_rp[port]);
+	ppc_vbus_source_enable(port, vbus_en[port]);
+}
+
+void pd_power_supply_reset(int port)
+{
+	int prev_en;
+
+	prev_en = vbus_en[port];
+
+	/* Disable VBUS */
+	vbus_en[port] = 0;
+	board_vbus_update_source_current(port);
+
+	/* Enable discharge if we were previously sourcing 5V */
+	if (prev_en)
+		pd_set_vbus_discharge(port, 1);
+
+	/* notify host of power info change */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	/* Disable charging */
+	board_vbus_sink_enable(port, 0);
+
+	pd_set_vbus_discharge(port, 0);
+
+	/* Provide VBUS */
+	vbus_en[port] = 1;
+	board_vbus_update_source_current(port);
+
+	/* notify host of power info change */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS; /* we are ready */
+}
+
+int board_vbus_source_enabled(int port)
+{
+	return vbus_en[port];
+}
+
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	vbus_rp[port] = rp;
+	board_vbus_update_source_current(port);
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	return tcpm_check_vbus_level(port, VBUS_PRESENT);
+}
+
+/* ----------------- Vendor Defined Messages ------------------ */
+#ifdef CONFIG_USB_PD_ALT_MODE_DFP
+__override int svdm_dp_config(int port, uint32_t *payload)
+{
+	int opos = pd_alt_mode(port, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT);
+	uint8_t pin_mode = get_dp_pin_mode(port);
+
+	if (!pin_mode)
+		return 0;
+
+	/*
+	 * Defer setting the usb_mux until HPD goes high, svdm_dp_attention().
+	 * The AP only supports one DP phy. An external DP mux switches between
+	 * the two ports. Should switch those muxes when it is really used,
+	 * i.e. HPD high; otherwise, the real use case is preempted, like:
+	 *  (1) plug a dongle without monitor connected to port-0,
+	 *  (2) plug a dongle without monitor connected to port-1,
+	 *  (3) plug a monitor to the port-1 dongle.
+	 */
+
+	payload[0] =
+		VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_CONFIG | VDO_OPOS(opos));
+	payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */
+				1, /* DPv1.3 signaling */
+				2); /* UFP connected */
+	return 2;
+};
+
+__override void svdm_dp_post_config(int port)
+{
+	dp_flags[port] |= DP_FLAGS_DP_ON;
+}
+
+/**
+ * Is the port fine to be muxed its DisplayPort lines?
+ *
+ * Only one port can be muxed to DisplayPort at a time.
+ *
+ * @param port	Port number of TCPC.
+ * @return	1 is fine; 0 is bad as other port is already muxed;
+ */
+static int is_dp_muxable(int port)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
+		if (i != port) {
+			if (usb_mux_get(i) & USB_PD_MUX_DP_ENABLED)
+				return 0;
+		}
+
+	return 1;
+}
+
+__override int svdm_dp_attention(int port, uint32_t *payload)
+{
+	const struct gpio_dt_spec *hpd =
+		GPIO_DT_FROM_NODELABEL(gpio_dp_hot_plug_det);
+	int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]);
+	int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]);
+	int cur_lvl = gpio_pin_get_dt(hpd);
+	mux_state_t mux_state;
+
+	dp_status[port] = payload[1];
+
+	if (!is_dp_muxable(port)) {
+		/* TODO(waihong): Info user? */
+		CPRINTS("p%d: The other port is already muxed.", port);
+		return 0;
+	}
+
+	/*
+	 * Initial implementation to handle HPD. Only the first-plugged port
+	 * works, i.e. sending HPD signal to AP. The second-plugged port
+	 * will be ignored.
+	 *
+	 * TODO(waihong): Continue the above case, if the first-plugged port
+	 * is then unplugged, switch to the second-plugged port and signal AP?
+	 */
+	if (lvl) {
+		/*
+		 * Enable and switch the DP port selection mux to the
+		 * correct port.
+		 *
+		 * TODO(waihong): Better to move switching DP mux to
+		 * the usb_mux abstraction.
+		 */
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_dp_mux_sel),
+				port == 1);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_dp_mux_oe_l), 0);
+
+		/* Connect the SBU lines in PPC chip. */
+		if (IS_ENABLED(CONFIG_USBC_PPC_SBU))
+			ppc_set_sbu(port, 1);
+
+		/*
+		 * Connect the USB SS/DP lines in TCPC chip.
+		 *
+		 * When mf_pref not true, still use the dock muxing
+		 * because of the board USB-C topology (limited to 2
+		 * lanes DP).
+		 */
+		usb_mux_set(port, USB_PD_MUX_DOCK, USB_SWITCH_CONNECT,
+			    polarity_rm_dts(pd_get_polarity(port)));
+	} else {
+		/* Disconnect the DP port selection mux. */
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_dp_mux_oe_l), 1);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_dp_mux_sel), 0);
+
+		/* Disconnect the SBU lines in PPC chip. */
+		if (IS_ENABLED(CONFIG_USBC_PPC_SBU))
+			ppc_set_sbu(port, 0);
+
+		/* Disconnect the DP but keep the USB SS lines in TCPC chip. */
+		usb_mux_set(port, USB_PD_MUX_USB_ENABLED, USB_SWITCH_CONNECT,
+			    polarity_rm_dts(pd_get_polarity(port)));
+	}
+
+	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && (irq || lvl))
+		/*
+		 * Wake up the AP.  IRQ or level high indicates a DP sink is now
+		 * present.
+		 */
+		pd_notify_dp_alt_mode_entry(port);
+
+	/* Configure TCPC for the HPD event, for proper muxing */
+	mux_state = (lvl ? USB_PD_MUX_HPD_LVL : USB_PD_MUX_HPD_LVL_DEASSERTED) |
+		    (irq ? USB_PD_MUX_HPD_IRQ : USB_PD_MUX_HPD_IRQ_DEASSERTED);
+	usb_mux_hpd_update(port, mux_state);
+
+	/* Signal AP for the HPD event, through GPIO to AP */
+	if (irq & cur_lvl) {
+		uint64_t now = get_time().val;
+		/* Wait for the minimum spacing between IRQ_HPD if needed */
+		if (now < svdm_hpd_deadline[port])
+			usleep(svdm_hpd_deadline[port] - now);
+
+		/* Generate IRQ_HPD pulse */
+		gpio_pin_set_dt(hpd, 0);
+		usleep(HPD_DSTREAM_DEBOUNCE_IRQ);
+		gpio_pin_set_dt(hpd, 1);
+
+		/* Set the minimum time delay (2ms) for the next HPD IRQ */
+		svdm_hpd_deadline[port] =
+			get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
+	} else if (irq & !lvl) {
+		CPRINTF("ERR:HPD:IRQ&LOW\n");
+		return 0;
+	}
+	gpio_pin_set_dt(hpd, lvl);
+	/* Set the minimum time delay (2ms) for the next HPD IRQ */
+	svdm_hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
+
+	return 1;
+}
+
+__override void svdm_exit_dp_mode(int port)
+{
+	if (is_dp_muxable(port)) {
+		/* Disconnect the DP port selection mux. */
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_dp_mux_oe_l), 1);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_dp_mux_sel), 0);
+
+		/* Signal AP for the HPD low event */
+		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_dp_hot_plug_det),
+				0);
+	}
+}
+#endif /* CONFIG_USB_PD_ALT_MODE_DFP */
diff --git a/zephyr/program/trogdor/lazor/src/usbc_config.c b/zephyr/program/trogdor/lazor/src/usbc_config.c
new file mode 100644
index 0000000000..80d2cebdf0
--- /dev/null
+++ b/zephyr/program/trogdor/lazor/src/usbc_config.c
@@ -0,0 +1,295 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Lazor board-specific USB-C configuration */
+
+#include "battery_fuel_gauge.h"
+#include "bc12/pi3usb9201_public.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "charger/isl923x_public.h"
+#include "common.h"
+#include "config.h"
+#include "driver/ln9310.h"
+#include "gpio/gpio_int.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "ppc/sn5s330_public.h"
+#include "system.h"
+#include "tcpm/ps8xxx_public.h"
+#include "tcpm/tcpci.h"
+#include "timer.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usbc_ocp.h"
+#include "usbc_ppc.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+int charger_profile_override(struct charge_state_data *curr)
+{
+	int usb_mv;
+	int port;
+
+	if (curr->state != ST_CHARGE)
+		return 0;
+
+	/* Lower the max requested voltage to 5V when battery is full. */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
+	    !(curr->batt.flags & BATT_FLAG_BAD_STATUS) &&
+	    !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
+	    (curr->batt.status & STATUS_FULLY_CHARGED))
+		usb_mv = 5000;
+	else
+		usb_mv = PD_MAX_VOLTAGE_MV;
+
+	if (pd_get_max_voltage() != usb_mv) {
+		CPRINTS("VBUS limited to %dmV", usb_mv);
+		for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++)
+			pd_set_external_voltage_limit(port, usb_mv);
+	}
+
+	return 0;
+}
+
+enum ec_status charger_profile_override_get_param(uint32_t param,
+						  uint32_t *value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+enum ec_status charger_profile_override_set_param(uint32_t param,
+						  uint32_t value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+static void usba_oc_deferred(void)
+{
+	/* Use next number after all USB-C ports to indicate the USB-A port */
+	board_overcurrent_event(
+		CONFIG_USB_PD_PORT_MAX_COUNT,
+		!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_a0_oc_odl)));
+}
+DECLARE_DEFERRED(usba_oc_deferred);
+
+void usba_oc_interrupt(enum gpio_signal signal)
+{
+	hook_call_deferred(&usba_oc_deferred_data, 0);
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_SIGNAL(DT_NODELABEL(gpio_usb_c0_swctl_int_odl)):
+		sn5s330_interrupt(0);
+		break;
+	case GPIO_SIGNAL(DT_NODELABEL(gpio_usb_c1_swctl_int_odl)):
+		sn5s330_interrupt(1);
+		break;
+	default:
+		break;
+	}
+}
+
+static void board_connect_c0_sbu_deferred(void)
+{
+	/*
+	 * If CCD_MODE_ODL asserts, it means there's a debug accessory connected
+	 * and we should enable the SBU FETs.
+	 */
+	ppc_set_sbu(0, 1);
+}
+DECLARE_DEFERRED(board_connect_c0_sbu_deferred);
+
+void board_connect_c0_sbu(enum gpio_signal s)
+{
+	hook_call_deferred(&board_connect_c0_sbu_deferred_data, 0);
+}
+
+/*
+ * Port-0/1 USB mux driver.
+ *
+ * The USB mux is handled by TCPC chip and the HPD update is through a GPIO
+ * to AP. But the TCPC chip is also needed to know the HPD status; otherwise,
+ * the mux misbehaves.
+ */
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
+	},
+	{
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
+	}
+};
+
+__override int board_get_default_battery_type(void)
+{
+	/*
+	 * A 2S battery is set as default. If the board is configured to use
+	 * a 3S battery, according to its SKU_ID, return a 3S battery as
+	 * default. It helps to configure the charger to output a correct
+	 * voltage in case the battery is not attached.
+	 */
+	if (board_get_battery_cell_type() == BATTERY_CELL_TYPE_3S)
+		return BATTERY_LGC_AP18C8K;
+
+	return DEFAULT_BATTERY_TYPE;
+}
+
+/* Initialize board USC-C things */
+static void board_init_usbc(void)
+{
+	/* Enable USB-A overcurrent interrupt */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_a0_oc));
+	/*
+	 * The H1 SBU line for CCD are behind PPC chip. The PPC internal FETs
+	 * for SBU may be disconnected after DP alt mode is off. Should enable
+	 * the CCD_MODE_ODL interrupt to make sure the SBU FETs are connected.
+	 */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_ccd_mode));
+}
+DECLARE_HOOK(HOOK_INIT, board_init_usbc, HOOK_PRIO_DEFAULT);
+
+void board_tcpc_init(void)
+{
+	/* Only reset TCPC if not sysjump */
+	if (!system_jumped_late()) {
+		/* TODO(crosbug.com/p/61098): How long do we need to wait? */
+		board_reset_pd_mcu();
+	}
+
+	/* Enable PPC interrupts */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_swctl));
+
+	/*
+	 * Initialize HPD to low; after sysjump SOC needs to see
+	 * HPD pulse to enable video path
+	 */
+	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
+		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_POST_I2C);
+
+void board_reset_pd_mcu(void)
+{
+	cprints(CC_USB, "Resetting TCPCs...");
+	cflush();
+
+	gpio_pin_set_dt(&tcpc_config[0].rst_gpio, 1);
+	gpio_pin_set_dt(&tcpc_config[1].rst_gpio, 1);
+	msleep(PS8XXX_RESET_DELAY_MS);
+	gpio_pin_set_dt(&tcpc_config[0].rst_gpio, 0);
+	gpio_pin_set_dt(&tcpc_config[1].rst_gpio, 0);
+}
+
+void board_set_tcpc_power_mode(int port, int mode)
+{
+	/* Ignore the "mode" to turn the chip on.  We can only do a reset. */
+	if (mode)
+		return;
+
+	board_reset_pd_mcu();
+}
+
+int board_vbus_sink_enable(int port, int enable)
+{
+	/* Both ports are controlled by PPC SN5S330 */
+	return ppc_vbus_sink_enable(port, enable);
+}
+
+int board_is_sourcing_vbus(int port)
+{
+	/* Both ports are controlled by PPC SN5S330 */
+	return ppc_is_sourcing_vbus(port);
+}
+
+void board_overcurrent_event(int port, int is_overcurrented)
+{
+	/* TODO(b/120231371): Notify AP */
+	CPRINTS("p%d: overcurrent!", port);
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int i;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTS("Disabling all charging port");
+
+		/* Disable all ports. */
+		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (board_vbus_sink_enable(i, 0))
+				CPRINTS("Disabling p%d sink path failed.", i);
+		}
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (board_is_sourcing_vbus(port)) {
+		CPRINTS("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTS("New charge port: p%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		if (i == port)
+			continue;
+
+		if (board_vbus_sink_enable(i, 0))
+			CPRINTS("p%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (board_vbus_sink_enable(port, 1)) {
+		CPRINTS("p%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
+{
+	/*
+	 * Ignore lower charge ceiling on PD transition if our battery is
+	 * critical, as we may brownout.
+	 */
+	if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 &&
+	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
+		CPRINTS("Using max ilim %d", max_ma);
+		charge_ma = max_ma;
+	}
+
+	charge_set_input_current_limit(charge_ma, charge_mv);
+}
diff --git a/zephyr/program/trogdor/lazor/usbc.dts b/zephyr/program/trogdor/lazor/usbc.dts
new file mode 100644
index 0000000000..7864c2716b
--- /dev/null
+++ b/zephyr/program/trogdor/lazor/usbc.dts
@@ -0,0 +1,36 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		/* TODO(b/227359762): lazor: move UBC-C configuration into the
+		 * devicetree
+		 */
+		port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+
+			bc12 = <&bc12_port0>;
+			tcpc = <&tcpc_port0>;
+
+			ppc = <&ppc_port0>;
+
+			chg = <&charger>;
+		};
+
+		port1@1 {
+			compatible = "named-usbc-port";
+			reg = <1>;
+
+			bc12 = <&bc12_port1>;
+			tcpc = <&tcpc_port1>;
+
+			ppc = <&ppc_port1>;
+		};
+	};
+};
diff --git a/zephyr/scripts/named_gpios.py b/zephyr/scripts/named_gpios.py
new file mode 100644
index 0000000000..2eaf344e7f
--- /dev/null
+++ b/zephyr/scripts/named_gpios.py
@@ -0,0 +1,337 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Configure-time checks for the named-gpios node."""
+
+import argparse
+import inspect
+import logging
+from pathlib import Path
+import pickle
+import re
+import site
+import sys
+from typing import List, Optional
+
+
+def _load_edt(zephyr_base, edt_pickle):
+    """Load an EDT object from a pickle file source.
+
+    Args:
+        zephyr_base: pathlib.Path pointing to the Zephyr OS repository.
+        edt_pickle: pathlib.Path pointing to the EDT object, stored as a pickle
+            file.
+
+    Returns:
+        A 3-field tuple: (edtlib, edt, project_name)
+            edtlib: module object for the edtlib
+            edt: EDT object of the devicetree
+            project_name: string containing the name of the project or test.
+
+        Returns None if the edtlib pickle file doesn't exist.
+    """
+    zephyr_devicetree_path = (
+        zephyr_base / "scripts" / "dts" / "python-devicetree" / "src"
+    )
+
+    # Add Zephyr's python-devicetree into the source path.
+    site.addsitedir(zephyr_devicetree_path)
+
+    try:
+        with open(edt_pickle, "rb") as edt_file:
+            edt = pickle.load(edt_file)
+    except FileNotFoundError:
+        # Skip the all EC specific checks if the edt_pickle file doesn't exist.
+        # UnpicklingErrors will raise an exception and fail the build.
+        return None, None, None
+
+    is_test = re.compile(r"twister-out")
+
+    if is_test.search(edt_pickle.as_posix()):
+        # For tests built with twister, the edt.pickle file is located in a
+        # path ending <test_name>/zephyr/.
+        project_name = edt_pickle.parents[1].name
+    else:
+        # For Zephyr EC project, the edt.pickle file is located in a path
+        # ending <project>/build-[ro|rw|single-image]/zephyr/.
+        project_name = edt_pickle.parents[2].name
+
+    edtlib = inspect.getmodule(edt)
+
+    return edtlib, edt, project_name
+
+
+def _detect_gpios_mismatches(node_name, prop_name, prop_gpios, board_gpios):
+    """Verify that all GPIO entries in a -gpios style property match the flags
+    specified in the named-gpios node.
+
+    Args:
+        node_name   - The name of the node containing the -gpios style property.
+        prop_name   - The name of the -gpios style property.
+        prop_gpios  - An edtlib.ControllerAndData class object containing
+                      the GPIO tuples found in the property.
+        board_gpios - A dictionary that maps gpio port/pin tuples to the GPIO
+                      flags. This dictionary is initialized from the children
+                      found in the named-gpios devicetree node.
+
+    Returns:
+        A tuple indicating how many GPIOs were checked, and how many GPIOs
+        had a mismatch.
+    """
+    errors = 0
+    count = 0
+
+    # The -gpios property may be an array of GPIO tuples
+    for gpio in prop_gpios:
+        count += 1
+        gpio_pin = gpio.data["pin"]
+
+        # The "flags" cell should be only 16-bits
+        dt_flags = gpio.data["flags"] & 0xFFFF
+
+        if gpio.controller.labels[0] is not None:
+            nodelabel = gpio.controller.labels[0]
+        else:
+            nodelabel = gpio.controller.name
+
+        if (nodelabel, gpio_pin) not in board_gpios.keys():
+            # GPIO not specified in named-gpios
+            logging.debug(
+                "Warning: property %s/%s = <%s %s 0x%x> not found in named-gpios",
+                node_name,
+                prop_name,
+                nodelabel,
+                gpio_pin,
+                dt_flags,
+            )
+            continue
+
+        if dt_flags != board_gpios[(nodelabel, gpio_pin)]:
+            errors += 1
+            logging.error(
+                "ERROR: property %s/%s = <%s %s 0x%x>. Flags don't match named-gpios 0x%x",
+                node_name,
+                prop_name,
+                nodelabel,
+                gpio_pin,
+                dt_flags,
+                board_gpios[(nodelabel, gpio_pin)],
+            )
+
+    return count, errors
+
+
+def verify_gpios_flags_match(edtlib, edt, project_name):
+    """Check that GPIO flags used across devices matches.
+
+    Until all drivers are upstream, the Zephyr EC devicetrees specify GPIOs
+    in multiple locations: the "named-gpios" node performs the configuration
+    of all GPIOs on the board, and individual drivers may also configure GPIOs.
+
+    This routine finds all "*-gpios" style properties in the devicetree and
+    cross-checks the flags set by "named-gpios" and ensures they match.
+
+    Args:
+        edtlib: Module object for the edtlib library.
+        edt: EDT object representation of a devicetree
+        project_name: A string containing the project/test name
+
+    Returns:
+        True if no GPIO flag mismatches found.  Returns False otherwise.
+    """
+    try:
+        named_gpios = edt.get_node("/named-gpios")
+    except edtlib.EDTError:
+        # If the named-gpios node doesn't exist, return success.
+        return True
+
+    # Dictionary using the gpio,pin tuple as the key. Value set to the flags
+    board_gpios = dict()
+    for node in named_gpios.children.values():
+        if "gpios" not in node.props:
+            continue
+
+        gpios = node.props["gpios"].val
+
+        # edtlib converts a "-gpios" style property to a list of of
+        # ControllerAndData objects.  However, the named-gpios node only
+        # supports a single GPIO per child, so no need to iterate over
+        # the list.
+        gpio = gpios[0]
+        gpio_pin = gpio.data["pin"]
+
+        if gpio.controller.labels[0] is not None:
+            nodelabel = gpio.controller.labels[0]
+        else:
+            nodelabel = gpio.controller.name
+
+        # The named-gpios stores a 32-bit flags, but Zephyr GPIO flags
+        # are limited to the lower 16-bits
+        board_gpios[(nodelabel, gpio_pin)] = gpio.data["flags"] & 0xFFFF
+
+    errors = 0
+    count = 0
+    for node in edt.nodes:
+        for prop_name in node.props.keys():
+            if prop_name.endswith("-gpios"):
+                gpios = node.props[prop_name].val
+
+                prop_gpio_count, prop_gpio_errors = _detect_gpios_mismatches(
+                    node.name, prop_name, gpios, board_gpios
+                )
+                count += prop_gpio_count
+                errors += prop_gpio_errors
+
+    if errors:
+        logging.error("%d GPIO mismatches found in %s.", errors, project_name)
+        return False
+
+    logging.info("Verified %d '*-gpios' properties, all flags match", count)
+    return True
+
+
+def verify_no_duplicates(edtlib, edt, project_name):
+    """Verify there are no duplicate GPIOs in the named-gpios node.
+
+    Args:
+        edtlib: Module object for the edtlib library.
+        edt: EDT object representation of a devicetree
+        project_name: A string containing the project/test name
+
+    Returns:
+        True if no duplicates found.  Returns False otherwise.
+    """
+    # Dictionary of GPIO controllers, indexed by the GPIO controller nodelabel
+    gpio_ctrls = dict()
+    duplicates = 0
+    count = 0
+
+    try:
+        named_gpios = edt.get_node("/named-gpios")
+    except edtlib.EDTError:
+        # If the named-gpios node doesn't exist, return success.
+        return True
+
+    for node in named_gpios.children.values():
+        if "gpios" not in node.props:
+            continue
+
+        gpios = node.props["gpios"].val
+        count += 1
+
+        # edtlib converts a "-gpios" style property to a list of of
+        # ControllerAndData objects.  However, the named-gpios node only
+        # supports a single GPIO per child, so no need to iterate over
+        # the list.
+        gpio = gpios[0]
+        gpio_pin = gpio.data["pin"]
+
+        # Note that EDT stores the node name (not a nodelabel) in the
+        # Node.name property.  Use the nodelabel, if available as the
+        # key for gpio_ctrls.
+        if gpio.controller.labels[0] is not None:
+            nodelabel = gpio.controller.labels[0]
+        else:
+            nodelabel = gpio.controller.name
+
+        if not nodelabel in gpio_ctrls:
+            # Create a dictionary at each GPIO controller
+            gpio_ctrls[nodelabel] = dict()
+
+        if gpio_pin in gpio_ctrls[nodelabel]:
+            logging.error(
+                "Duplicate GPIOs found at nodes: %s and %s",
+                gpio_ctrls[nodelabel][gpio_pin],
+                node.name,
+            )
+            duplicates += 1
+        else:
+            # Store the node name for the new pin
+            gpio_ctrls[nodelabel][gpio_pin] = node.name
+
+    if duplicates:
+        logging.error(
+            "%d duplicate GPIOs found in %s", duplicates, project_name
+        )
+        return False
+
+    logging.info("Verified %d GPIOs, no duplicates found", count)
+    return True
+
+
+# Dictionary used to map log level strings to their corresponding int values.
+log_level_map = {
+    "DEBUG": logging.DEBUG,
+    "INFO": logging.INFO,
+    "WARNING": logging.WARNING,
+    "ERROR": logging.ERROR,
+    "CRITICAL": logging.CRITICAL,
+}
+
+
+def parse_args(argv: Optional[List[str]] = None):
+    """Returns parsed command-line arguments"""
+    parser = argparse.ArgumentParser(
+        prog="named_gpios",
+        description="Zephyr EC specific devicetree checks",
+    )
+
+    parser.add_argument(
+        "--zephyr-base",
+        type=Path,
+        help="Path to Zephyr OS repository",
+        required=True,
+    )
+
+    parser.add_argument(
+        "--edt-pickle",
+        type=Path,
+        help="EDT object file, in pickle format",
+        required=True,
+    )
+
+    parser.add_argument(
+        "-l",
+        "--log-level",
+        choices=log_level_map.values(),
+        metavar=f"{{{','.join(log_level_map)}}}",
+        type=lambda x: log_level_map[x],
+        default=logging.INFO,
+        help="Set the logging level (default=INFO)",
+    )
+
+    return parser.parse_args(argv)
+
+
+def main(argv: Optional[List[str]] = None) -> Optional[int]:
+    """The main function.
+
+    Args:
+        argv: Optionally, the command-line to parse, not including argv[0].
+
+    Returns:
+        Zero upon success, or non-zero upon failure.
+    """
+    args = parse_args(argv)
+
+    log_format = "%(levelname)s: %(message)s"
+
+    logging.basicConfig(format=log_format, level=args.log_level)
+
+    edtlib, edt, project_name = _load_edt(args.zephyr_base, args.edt_pickle)
+
+    if edtlib is None:
+        return 0
+
+    if not verify_no_duplicates(edtlib, edt, project_name):
+        return 1
+
+    if not verify_gpios_flags_match(edtlib, edt, project_name):
+        return 1
+
+    return 0
+
+
+if __name__ == "__main__":
+    sys.exit(main(sys.argv[1:]))
diff --git a/zephyr/shim/CMakeLists.txt b/zephyr/shim/CMakeLists.txt
new file mode 100644
index 0000000000..5b8c815ae1
--- /dev/null
+++ b/zephyr/shim/CMakeLists.txt
@@ -0,0 +1,7 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+add_subdirectory("chip")
+add_subdirectory("core")
+add_subdirectory("src")
diff --git a/zephyr/shim/chip/CMakeLists.txt b/zephyr/shim/chip/CMakeLists.txt
new file mode 100644
index 0000000000..a899a96070
--- /dev/null
+++ b/zephyr/shim/chip/CMakeLists.txt
@@ -0,0 +1,16 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if (DEFINED CONFIG_SOC_FAMILY_NPCX)
+	add_subdirectory(npcx)
+elseif (DEFINED CONFIG_SOC_FAMILY_RISCV_ITE)
+	add_subdirectory(it8xxx2)
+elseif (DEFINED CONFIG_SOC_FAMILY_MEC)
+	add_subdirectory(mchp)
+elseif (DEFINED CONFIG_SOC_FAMILY_STM32)
+	add_subdirectory(stm32)
+else ()
+	add_subdirectory(stub)
+endif()
+
diff --git a/zephyr/shim/chip/it8xxx2/CMakeLists.txt b/zephyr/shim/chip/it8xxx2/CMakeLists.txt
new file mode 100644
index 0000000000..2a1c9d5909
--- /dev/null
+++ b/zephyr/shim/chip/it8xxx2/CMakeLists.txt
@@ -0,0 +1,11 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cros_ec_library_include_directories(include)
+
+zephyr_library_sources(clock.c)
+zephyr_library_sources(gpio.c)
+zephyr_library_sources_ifdef(CONFIG_CROS_EC           system.c)
+zephyr_library_sources_ifdef(CONFIG_CROS_KB_RAW_ITE   keyboard_raw.c)
+zephyr_library_sources_ifdef(CONFIG_PM_POLICY_CUSTOM  power_policy.c)
diff --git a/zephyr/shim/chip/it8xxx2/clock.c b/zephyr/shim/chip/it8xxx2/clock.c
new file mode 100644
index 0000000000..f76e67b223
--- /dev/null
+++ b/zephyr/shim/chip/it8xxx2/clock.c
@@ -0,0 +1,38 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "module_id.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/util.h>
+
+#include <soc.h>
+#include <soc/ite_it8xxx2/reg_def_cros.h>
+
+LOG_MODULE_REGISTER(shim_clock, LOG_LEVEL_ERR);
+
+#define ECPM_NODE DT_INST(0, ite_it8xxx2_ecpm)
+#define HAL_ECPM_REG_BASE_ADDR \
+	((struct ecpm_reg *)DT_REG_ADDR_BY_IDX(ECPM_NODE, 0))
+#define PLLFREQ_MASK 0xf
+
+static const int pll_reg_to_freq[8] = { MHZ(8),	 MHZ(16), MHZ(24), MHZ(32),
+					MHZ(48), MHZ(64), MHZ(72), MHZ(96) };
+
+int clock_get_freq(void)
+{
+	struct ecpm_reg *const ecpm_base = HAL_ECPM_REG_BASE_ADDR;
+	int reg_val = ecpm_base->ECPM_PLLFREQ & PLLFREQ_MASK;
+
+	return pll_reg_to_freq[reg_val];
+}
+
+test_mockable void clock_enable_module(enum module_id module, int enable)
+{
+}
diff --git a/zephyr/shim/chip/it8xxx2/gpio.c b/zephyr/shim/chip/it8xxx2/gpio.c
new file mode 100644
index 0000000000..78aa504140
--- /dev/null
+++ b/zephyr/shim/chip/it8xxx2/gpio.c
@@ -0,0 +1,126 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "gpio/gpio.h"
+#include "gpio_it8xxx2.h"
+
+#include <errno.h>
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(shim_cros_gpio, LOG_LEVEL_ERR);
+
+static const struct unused_pin_config unused_pin_configs[] = {
+	UNUSED_GPIO_CONFIG_LIST
+};
+
+int gpio_config_unused_pins(void)
+{
+	for (size_t i = 0; i < ARRAY_SIZE(unused_pin_configs); ++i) {
+		int rv;
+		int flags;
+		const struct device *dev =
+			device_get_binding(unused_pin_configs[i].dev_name);
+
+		if (dev == NULL) {
+			LOG_ERR("Not found (%s)",
+				unused_pin_configs[i].dev_name);
+			return -ENOTSUP;
+		}
+
+		/*
+		 * Set the default setting for the floating IOs. The floating
+		 * IOs cause the leakage current. Set unused pins as input with
+		 * internal PU to prevent extra power consumption.
+		 */
+		if (unused_pin_configs[i].flags == 0)
+			flags = GPIO_INPUT | GPIO_PULL_UP;
+		else
+			flags = unused_pin_configs[i].flags;
+
+		rv = gpio_pin_configure(dev, unused_pin_configs[i].pin, flags);
+
+		if (rv < 0) {
+			LOG_ERR("Config failed %s-%d (%d)",
+				unused_pin_configs[i].dev_name,
+				unused_pin_configs[i].pin, rv);
+			return rv;
+		}
+	}
+
+	return 0;
+}
+
+int gpio_configure_port_pin(int port, int id, int flags)
+{
+	const struct device *dev;
+
+	/*
+	 * Port number mapping to node
+	 * 0                      gpioa
+	 * ...                    ...
+	 * 50                     gpioksi
+	 * 51                     gpioksoh
+	 * 52                     gpioksol
+	 */
+	switch ((enum gpio_port_to_node)port) {
+	case GPIO_A:
+		dev = DEVICE_DT_GET(DT_NODELABEL(gpioa));
+		break;
+	case GPIO_B:
+		dev = DEVICE_DT_GET(DT_NODELABEL(gpiob));
+		break;
+	case GPIO_C:
+		dev = DEVICE_DT_GET(DT_NODELABEL(gpioc));
+		break;
+	case GPIO_D:
+		dev = DEVICE_DT_GET(DT_NODELABEL(gpiod));
+		break;
+	case GPIO_E:
+		dev = DEVICE_DT_GET(DT_NODELABEL(gpioe));
+		break;
+	case GPIO_F:
+		dev = DEVICE_DT_GET(DT_NODELABEL(gpiof));
+		break;
+	case GPIO_G:
+		dev = DEVICE_DT_GET(DT_NODELABEL(gpiog));
+		break;
+	case GPIO_H:
+		dev = DEVICE_DT_GET(DT_NODELABEL(gpioh));
+		break;
+	case GPIO_I:
+		dev = DEVICE_DT_GET(DT_NODELABEL(gpioi));
+		break;
+	case GPIO_J:
+		dev = DEVICE_DT_GET(DT_NODELABEL(gpioj));
+		break;
+	case GPIO_K:
+		dev = DEVICE_DT_GET(DT_NODELABEL(gpiok));
+		break;
+	case GPIO_L:
+		dev = DEVICE_DT_GET(DT_NODELABEL(gpiol));
+		break;
+	case GPIO_M:
+		dev = DEVICE_DT_GET(DT_NODELABEL(gpiom));
+		break;
+	case GPIO_KSI:
+		dev = DEVICE_DT_GET(DT_NODELABEL(gpioksi));
+		break;
+	case GPIO_KSOH:
+		dev = DEVICE_DT_GET(DT_NODELABEL(gpioksoh));
+		break;
+	case GPIO_KSOL:
+		dev = DEVICE_DT_GET(DT_NODELABEL(gpioksol));
+		break;
+	default:
+		printk("Error port number %d\n", port);
+		return -EINVAL;
+	}
+
+	return gpio_pin_configure(dev, id, flags);
+}
diff --git a/zephyr/shim/chip/it8xxx2/include/flash_chip.h b/zephyr/shim/chip/it8xxx2/include/flash_chip.h
new file mode 100644
index 0000000000..b3f51ba378
--- /dev/null
+++ b/zephyr/shim/chip/it8xxx2/include/flash_chip.h
@@ -0,0 +1,32 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_FLASH_CHIP_H
+#define __CROS_EC_FLASH_CHIP_H
+/*
+ * One page program instruction allows maximum 256 bytes (a page) of data
+ * to be programmed.
+ */
+#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256
+/* Minimum write size */
+#define CONFIG_FLASH_WRITE_SIZE \
+	DT_PROP(DT_INST(0, soc_nv_flash), write_block_size)
+/* Erase bank size */
+#define CONFIG_FLASH_ERASE_SIZE \
+	DT_PROP(DT_INST(0, soc_nv_flash), erase_block_size)
+/* Protect bank size */
+#define CONFIG_FLASH_BANK_SIZE CONFIG_FLASH_ERASE_SIZE
+
+#define CONFIG_RO_STORAGE_OFF 0x0
+#define CONFIG_RW_STORAGE_OFF 0x0
+
+/*
+ * The EC uses the one bank of flash to emulate a SPI-like write protect
+ * register with persistent state.
+ */
+#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE
+#define CONFIG_FW_PSTATE_OFF (CONFIG_RO_STORAGE_OFF + CONFIG_RO_SIZE)
+
+#endif /* __CROS_EC_FLASH_CHIP_H */
diff --git a/zephyr/shim/chip/it8xxx2/include/gpio_it8xxx2.h b/zephyr/shim/chip/it8xxx2/include/gpio_it8xxx2.h
new file mode 100644
index 0000000000..7abf9f560a
--- /dev/null
+++ b/zephyr/shim/chip/it8xxx2/include/gpio_it8xxx2.h
@@ -0,0 +1,28 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_GPIO_IT8XXX2_H
+#define __CROS_EC_GPIO_IT8XXX2_H
+
+enum gpio_port_to_node {
+	GPIO_A,
+	GPIO_B,
+	GPIO_C,
+	GPIO_D,
+	GPIO_E,
+	GPIO_F,
+	GPIO_G,
+	GPIO_H,
+	GPIO_I,
+	GPIO_J,
+	GPIO_K,
+	GPIO_L,
+	GPIO_M,
+	GPIO_KSI = 50,
+	GPIO_KSOH = 51,
+	GPIO_KSOL = 52
+};
+
+#endif /* __CROS_EC_GPIO_IT8XXX2_H */
diff --git a/zephyr/shim/chip/it8xxx2/include/sha256_chip.h b/zephyr/shim/chip/it8xxx2/include/sha256_chip.h
new file mode 100644
index 0000000000..41a6cae589
--- /dev/null
+++ b/zephyr/shim/chip/it8xxx2/include/sha256_chip.h
@@ -0,0 +1,33 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_IT8XXX2_SHA256_H
+#define __CROS_EC_IT8XXX2_SHA256_H
+
+#include "common.h"
+
+struct sha256_ctx {
+	/* W[0] ~ W[15] */
+	uint32_t w[16];
+	/* reserved */
+	uint32_t reserved1[8];
+	/* H[0] ~ H[7] */
+	uint32_t h[8];
+	/* reserved */
+	uint32_t reserved2[30];
+	uint32_t w_index;
+	uint32_t total_len;
+	/* K[0] ~ K[63] */
+	uint32_t k[64];
+} __aligned(256);
+
+void SHA256_abort(struct sha256_ctx *ctx);
+
+#ifdef CONFIG_ZTEST
+extern uint8_t it8xxx2_sha256_get_sha1hbaddr(void);
+extern uint8_t it8xxx2_sha256_get_sha2hbaddr(void);
+#endif
+
+#endif /* __CROS_EC_IT8XXX2_SHA256_H */
diff --git a/zephyr/shim/chip/it8xxx2/keyboard_raw.c b/zephyr/shim/chip/it8xxx2/keyboard_raw.c
new file mode 100644
index 0000000000..442b51a59a
--- /dev/null
+++ b/zephyr/shim/chip/it8xxx2/keyboard_raw.c
@@ -0,0 +1,42 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Functions needed by keyboard scanner module for Chrome EC */
+
+#include "drivers/cros_kb_raw.h"
+#include "gpio_it8xxx2.h"
+#include "keyboard_raw.h"
+
+#include <zephyr/device.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+
+#include <soc.h>
+
+/**
+ * Return true if the current value of the given gpioksi/gpioksoh/gpioksol
+ * port is zero
+ */
+int keyboard_raw_is_input_low(int port, int id)
+{
+	const struct device *dev;
+
+	switch ((enum gpio_port_to_node)port) {
+	case GPIO_KSI:
+		dev = DEVICE_DT_GET(DT_NODELABEL(gpioksi));
+		break;
+	case GPIO_KSOH:
+		dev = DEVICE_DT_GET(DT_NODELABEL(gpioksoh));
+		break;
+	case GPIO_KSOL:
+		dev = DEVICE_DT_GET(DT_NODELABEL(gpioksol));
+		break;
+	default:
+		printk("Error port number %d, return 0\n", port);
+		return 0;
+	}
+
+	return (gpio_pin_get_raw(dev, id) == 0);
+}
diff --git a/zephyr/shim/chip/it8xxx2/power_policy.c b/zephyr/shim/chip/it8xxx2/power_policy.c
new file mode 100644
index 0000000000..c6e73d53a4
--- /dev/null
+++ b/zephyr/shim/chip/it8xxx2/power_policy.c
@@ -0,0 +1,43 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "system.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/pm/pm.h>
+#include <zephyr/pm/policy.h>
+
+#include <soc.h>
+
+static const struct pm_state_info pm_states[] =
+	PM_STATE_INFO_LIST_FROM_DT_CPU(DT_NODELABEL(cpu0));
+
+/* CROS PM policy handler */
+const struct pm_state_info *pm_policy_next_state(uint8_t cpu, int32_t ticks)
+{
+	ARG_UNUSED(cpu);
+
+	/* Deep sleep is allowed */
+	if (DEEP_SLEEP_ALLOWED) {
+		/*
+		 * If there are multiple power states, iterating backward
+		 * is needed to take priority into account.
+		 */
+		for (int i = 0; i < ARRAY_SIZE(pm_states); i++) {
+			/*
+			 * To check if given power state is enabled and
+			 * could be used.
+			 */
+			if (pm_policy_state_lock_is_active(pm_states[i].state,
+							   PM_ALL_SUBSTATES)) {
+				continue;
+			}
+
+			return &pm_states[i];
+		}
+	}
+
+	return NULL;
+}
diff --git a/zephyr/shim/chip/it8xxx2/system.c b/zephyr/shim/chip/it8xxx2/system.c
new file mode 100644
index 0000000000..e5f9cc5cf0
--- /dev/null
+++ b/zephyr/shim/chip/it8xxx2/system.c
@@ -0,0 +1,16 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "system.h"
+
+uintptr_t system_get_fw_reset_vector(uintptr_t base)
+{
+	/*
+	 * Because our reset vector is at the beginning of image copy
+	 * (see init.S). So I just need to return 'base' here and EC will jump
+	 * to the reset vector.
+	 */
+	return base;
+}
diff --git a/zephyr/shim/chip/mchp/CMakeLists.txt b/zephyr/shim/chip/mchp/CMakeLists.txt
new file mode 100644
index 0000000000..f59a1be2b1
--- /dev/null
+++ b/zephyr/shim/chip/mchp/CMakeLists.txt
@@ -0,0 +1,14 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cros_ec_library_include_directories(include)
+
+zephyr_library_sources(clock.c)
+zephyr_library_sources(gpio.c)
+zephyr_library_sources_ifdef(CONFIG_CROS_KB_RAW_MCHP  keyboard_raw.c)
+zephyr_library_sources_ifdef(CONFIG_CROS_EC           system.c)
+
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_EXTERNAL_STORAGE
+        system_external_storage.c
+        system_download_from_flash.c)
diff --git a/zephyr/shim/chip/mchp/Kconfig.xec b/zephyr/shim/chip/mchp/Kconfig.xec
new file mode 100644
index 0000000000..28a6b3ea3c
--- /dev/null
+++ b/zephyr/shim/chip/mchp/Kconfig.xec
@@ -0,0 +1,18 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if PLATFORM_EC
+
+config CROS_SYSTEM_XEC_PRE_INIT_PRIORITY
+	int "System pre-initialization priority"
+	default 15
+	range 10 19
+	depends on SOC_FAMILY_MEC
+	help
+	  This sets the priority of the MCHP XEC chip system initialization.
+	  The chip system initialization verifies the integrity of the BBRAM
+	  must be a lower priority than CONFIG_BBRAM_INIT_PRIORITY and
+	  must be a higher priority than PLATFORM_EC_SYSTEM_PRE_INIT.
+
+endif # PLATFORM_EC
diff --git a/zephyr/shim/chip/mchp/clock.c b/zephyr/shim/chip/mchp/clock.c
new file mode 100644
index 0000000000..2dff137c33
--- /dev/null
+++ b/zephyr/shim/chip/mchp/clock.c
@@ -0,0 +1,78 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "clock_chip.h"
+#include "common.h"
+#include "module_id.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+
+#include <soc.h>
+
+LOG_MODULE_REGISTER(shim_clock, LOG_LEVEL_ERR);
+
+#define PCR_NODE DT_INST(0, microchip_xec_pcr)
+#define HAL_PCR_REG_BASE_ADDR \
+	((struct pcr_regs *)DT_REG_ADDR_BY_IDX(PCR_NODE, 0))
+
+int clock_get_freq(void)
+{
+	const struct device *clk_dev = DEVICE_DT_GET(PCR_NODE);
+	uint32_t bus = MCHP_XEC_PCR_CLK_CPU;
+	uint32_t rate;
+
+	if (clock_control_get_rate(clk_dev, (clock_control_subsys_t)bus,
+				   &rate) != 0) {
+		LOG_ERR("Get %s clock rate error", clk_dev->name);
+		return -EIO;
+	}
+
+	return rate;
+}
+
+void clock_turbo(void)
+{
+	struct pcr_regs *const pcr = HAL_PCR_REG_BASE_ADDR;
+
+	pcr->PROC_CLK_CTRL = 1;
+	__DSB();
+	__ISB();
+	__NOP();
+	__NOP();
+	__NOP();
+	__NOP();
+	__NOP();
+	__NOP();
+}
+
+void clock_normal(void)
+{
+	struct pcr_regs *const pcr = HAL_PCR_REG_BASE_ADDR;
+
+	pcr->PROC_CLK_CTRL = 4;
+	__DSB();
+	__ISB();
+	__NOP();
+	__NOP();
+	__NOP();
+	__NOP();
+	__NOP();
+	__NOP();
+}
+
+test_mockable void clock_enable_module(enum module_id module, int enable)
+{
+	/* Assume we have a single task using MODULE_FAST_CPU */
+	if (module == MODULE_FAST_CPU) {
+		if (enable)
+			clock_turbo();
+		else
+			clock_normal();
+	}
+}
diff --git a/zephyr/shim/chip/mchp/gpio.c b/zephyr/shim/chip/mchp/gpio.c
new file mode 100644
index 0000000000..d772a566d8
--- /dev/null
+++ b/zephyr/shim/chip/mchp/gpio.c
@@ -0,0 +1,54 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "gpio/gpio.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(shim_cros_gpio, LOG_LEVEL_ERR);
+
+static const struct unused_pin_config unused_pin_configs[] = {
+	UNUSED_GPIO_CONFIG_LIST
+};
+
+int gpio_config_unused_pins(void)
+{
+	for (size_t i = 0; i < ARRAY_SIZE(unused_pin_configs); ++i) {
+		int rv;
+		int flags;
+		const struct device *dev =
+			device_get_binding(unused_pin_configs[i].dev_name);
+
+		if (dev == NULL) {
+			LOG_ERR("Not found (%s)",
+				unused_pin_configs[i].dev_name);
+			return -ENOTSUP;
+		}
+
+		/*
+		 * Set the default setting for the floating IOs. The floating
+		 * IOs cause the leakage current. Set unused pins as input with
+		 * internal PU to prevent extra power consumption.
+		 */
+		if (unused_pin_configs[i].flags == 0)
+			flags = GPIO_INPUT | GPIO_PULL_UP;
+		else
+			flags = unused_pin_configs[i].flags;
+
+		rv = gpio_pin_configure(dev, unused_pin_configs[i].pin, flags);
+
+		if (rv < 0) {
+			LOG_ERR("Config failed %s-%d (%d)",
+				unused_pin_configs[i].dev_name,
+				unused_pin_configs[i].pin, rv);
+			return rv;
+		}
+	}
+
+	return 0;
+}
diff --git a/zephyr/shim/chip/mchp/include/clock_chip.h b/zephyr/shim/chip/mchp/include/clock_chip.h
new file mode 100644
index 0000000000..4c14d60ff9
--- /dev/null
+++ b/zephyr/shim/chip/mchp/include/clock_chip.h
@@ -0,0 +1,11 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_CLOCK_CHIP_H
+#define __CROS_EC_CLOCK_CHIP_H
+
+void clock_turbo(void);
+
+#endif /* __CROS_EC_CLOCK_CHIP_H */
diff --git a/zephyr/shim/chip/mchp/include/flash_chip.h b/zephyr/shim/chip/mchp/include/flash_chip.h
new file mode 100644
index 0000000000..de8138614c
--- /dev/null
+++ b/zephyr/shim/chip/mchp/include/flash_chip.h
@@ -0,0 +1,29 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_FLASH_CHIP_H
+#define __CROS_EC_FLASH_CHIP_H
+
+/* TODO(b/226599277): need to check if SST25PF040 is compatible W25X40
+ * MEC1727 uses SST25PF040.
+ * Similar to W25X40, both only have one status reg
+ */
+#define CONFIG_SPI_FLASH_W25X40 /* Internal SPI flash type. */
+#define CONFIG_FLASH_WRITE_SIZE 0x1 /* minimum write size */
+#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* one page size for write */
+#define CONFIG_FLASH_ERASE_SIZE 0x1000
+#define CONFIG_FLASH_BANK_SIZE CONFIG_FLASH_ERASE_SIZE
+
+/* RO image resides at 4KB offset in protected region
+ * The first 4KB in the protected region starting at offset 0 contains
+ * the Boot-ROM TAGs and Boot-ROM Header for EC_RO. These objects are
+ * not loaded into RAM.
+ * RW image is never loaded by the Boot-ROM therefore no TAG or Header
+ * is needed. RW starts at offset 0 in RW storage region.
+ */
+#define CONFIG_RO_STORAGE_OFF 0x1000
+#define CONFIG_RW_STORAGE_OFF 0
+
+#endif /* __CROS_EC_FLASH_CHIP_H */
diff --git a/zephyr/shim/chip/mchp/include/system_chip.h b/zephyr/shim/chip/mchp/include/system_chip.h
new file mode 100644
index 0000000000..01cd1e7391
--- /dev/null
+++ b/zephyr/shim/chip/mchp/include/system_chip.h
@@ -0,0 +1,29 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_SYSTEM_CHIP_H_
+#define __CROS_EC_SYSTEM_CHIP_H_
+
+#define SET_BIT(reg, bit) ((reg) |= (0x1 << (bit)))
+#define CLEAR_BIT(reg, bit) ((reg) &= (~(0x1 << (bit))))
+
+#undef IS_BIT_SET
+#define IS_BIT_SET(reg, bit) (((reg) >> (bit)) & (0x1))
+
+/******************************************************************************/
+/* Optional M4 Registers */
+#define CPU_MPU_CTRL REG32(0xE000ED94)
+#define CPU_MPU_RNR REG32(0xE000ED98)
+#define CPU_MPU_RBAR REG32(0xE000ED9C)
+#define CPU_MPU_RASR REG32(0xE000EDA0)
+
+void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr,
+				uint32_t size, uint32_t exeAddr);
+
+/* Begin and end address for little FW; defined in linker script */
+extern unsigned int __flash_lplfw_start;
+extern unsigned int __flash_lplfw_end;
+
+#endif /* __CROS_EC_SYSTEM_CHIP_H_ */
diff --git a/zephyr/shim/chip/mchp/keyboard_raw.c b/zephyr/shim/chip/mchp/keyboard_raw.c
new file mode 100644
index 0000000000..9183e4d7dd
--- /dev/null
+++ b/zephyr/shim/chip/mchp/keyboard_raw.c
@@ -0,0 +1,25 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Functions needed by keyboard scanner module for Chrome EC */
+
+#include "drivers/cros_kb_raw.h"
+#include "keyboard_raw.h"
+
+#include <zephyr/device.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+
+#include <soc.h>
+
+/**
+ * Return true if the current value of the given input GPIO port is zero
+ */
+int keyboard_raw_is_input_low(int port, int id)
+{
+	const struct device *io_dev = mchp_xec_get_gpio_dev(port);
+
+	return gpio_pin_get_raw(io_dev, id) == 0;
+}
diff --git a/zephyr/shim/chip/mchp/system.c b/zephyr/shim/chip/mchp/system.c
new file mode 100644
index 0000000000..def53cdef9
--- /dev/null
+++ b/zephyr/shim/chip/mchp/system.c
@@ -0,0 +1,74 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "bbram.h"
+#include "system.h"
+#include "system_chip.h"
+
+#include <zephyr/drivers/bbram.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(shim_xec_system, LOG_LEVEL_ERR);
+
+/*
+ * Reset image type back to RO in BBRAM as watchdog resets.
+ * Watchdog reset will reset EC chip, ROM loader loads RO
+ * image stored in SPI flash chip in default.
+ */
+void cros_chip_wdt_handler(const struct device *wdt_dev, int channel_id)
+{
+	const struct device *bbram_dev = DEVICE_DT_GET(DT_NODELABEL(bbram));
+	uint32_t value = EC_IMAGE_RO;
+
+	if (!device_is_ready(bbram_dev)) {
+		LOG_ERR("WDT ISR: device %s is not ready", bbram_dev->name);
+		return;
+	}
+
+	bbram_write(bbram_dev, BBRAM_REGION_OFFSET(ec_img_load),
+		    BBRAM_REGION_SIZE(ec_img_load), (uint8_t *)&value);
+}
+
+static void chip_bbram_status_check(void)
+{
+	const struct device *bbram_dev;
+	int res;
+
+	bbram_dev = DEVICE_DT_GET(DT_NODELABEL(bbram));
+	if (!device_is_ready(bbram_dev)) {
+		LOG_ERR("Error: device %s is not ready", bbram_dev->name);
+		return;
+	}
+
+	res = bbram_check_invalid(bbram_dev);
+	if (res != 0 && res != -ENOTSUP)
+		LOG_INF("VBAT power drop!");
+}
+
+void system_mpu_config(void)
+{
+	/* Reseve for future use */
+}
+
+static int chip_system_init(void)
+{
+	/*
+	 * Check BBRAM power status.
+	 */
+	chip_bbram_status_check();
+
+	system_mpu_config();
+
+	return 0;
+}
+/*
+ * The priority should be lower than CROS_BBRAM_MCHP_INIT_PRIORITY.
+ */
+#if (CONFIG_CROS_SYSTEM_XEC_PRE_INIT_PRIORITY <= CONFIG_BBRAM_INIT_PRIORITY)
+#error CONFIG_CROS_SYSTEM_XEC_PRE_INIT_PRIORITY must greater than \
+	CONFIG_BBRAM_INIT_PRIORITY
+#endif
+SYS_INIT(chip_system_init, PRE_KERNEL_1,
+	 CONFIG_CROS_SYSTEM_XEC_PRE_INIT_PRIORITY);
diff --git a/zephyr/shim/chip/mchp/system_download_from_flash.c b/zephyr/shim/chip/mchp/system_download_from_flash.c
new file mode 100644
index 0000000000..ae3d96fa4a
--- /dev/null
+++ b/zephyr/shim/chip/mchp/system_download_from_flash.c
@@ -0,0 +1,154 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "common.h"
+#include "soc.h"
+#include "system_chip.h"
+
+#include <zephyr/dt-bindings/clock/npcx_clock.h>
+
+#include <stdnoreturn.h>
+
+/* Modules Map */
+#define WDT_NODE DT_INST(0, microchip_xec_watchdog)
+#define STRUCT_WDT_REG_BASE_ADDR ((struct wdt_regs *)(DT_REG_ADDR(WDT_NODE)))
+
+#define PCR_NODE DT_INST(0, microchip_xec_pcr)
+#define STRUCT_PCR_REG_BASE_ADDR \
+	((struct pcr_regs *)DT_REG_ADDR_BY_IDX(PCR_NODE, 0))
+
+#define QSPI_NODE DT_INST(0, microchip_xec_qmspi_ldma)
+#define STRUCT_QSPI_REG_BASE_ADDR \
+	((struct qmspi_regs *)(DT_REG_ADDR(QSPI_NODE)))
+
+#define SPI_READ_111 0x03
+#define SPI_READ_111_FAST 0x0b
+#define SPI_READ_112_FAST 0x3b
+
+#define QSPI_STATUS_DONE (MCHP_QMSPI_STS_DONE | MCHP_QMSPI_STS_DMA_DONE)
+
+#define QSPI_STATUS_ERR                                    \
+	(MCHP_QMSPI_STS_TXB_ERR | MCHP_QMSPI_STS_RXB_ERR | \
+	 MCHP_QMSPI_STS_PROG_ERR | MCHP_QMSPI_STS_LDMA_RX_ERR)
+
+noreturn void __keep __attribute__((section(".code_in_sram2")))
+__start_qspi(uint32_t resetVectAddr)
+{
+	struct pcr_regs *pcr = STRUCT_PCR_REG_BASE_ADDR;
+	struct qmspi_regs *qspi = STRUCT_QSPI_REG_BASE_ADDR;
+	struct wdt_regs *wdt = STRUCT_WDT_REG_BASE_ADDR;
+	uint32_t qsts = 0;
+	uint32_t exeAddr = 0;
+
+	qspi->EXE = MCHP_QMSPI_EXE_START;
+
+	qsts = qspi->STS;
+	while (!(qsts & QSPI_STATUS_DONE)) {
+		qsts = qspi->STS;
+		if (qsts & QSPI_STATUS_ERR)
+			break;
+	}
+
+	/* Stop the watchdog */
+	wdt->CTRL &= ~MCHP_WDT_CTRL_EN;
+
+	qspi->MODE &= ~(MCHP_QMSPI_M_ACTIVATE);
+	if (qsts & QSPI_STATUS_ERR) {
+		pcr->SYS_RST |= MCHP_PCR_SYS_RESET_NOW;
+		while (1)
+			;
+	}
+
+	/*
+	 * Jump to the exeAddr address if needed. Setting bit 0 of address to
+	 * indicate it's a thumb branch for cortex-m series CPU.
+	 */
+	exeAddr = *(uint32_t *)(resetVectAddr & ~0x03u);
+
+	((void (*)(void))(exeAddr | 0x01))();
+
+	/* Should never get here */
+	while (1)
+		;
+}
+
+uintptr_t __lfw_sram_start = CONFIG_CROS_EC_RAM_BASE + CONFIG_CROS_EC_RAM_SIZE;
+
+typedef void (*START_QSPI_IN_SRAM_FP)(uint32_t);
+
+void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr,
+				uint32_t size, uint32_t resetVectAddr)
+{
+	struct pcr_regs *pcr = STRUCT_PCR_REG_BASE_ADDR;
+	struct qmspi_regs *qspi = STRUCT_QSPI_REG_BASE_ADDR;
+	uint32_t fdiv;
+	uint32_t cmdaddr;
+	int i;
+	START_QSPI_IN_SRAM_FP __start_qspi_in_data_sram =
+		(START_QSPI_IN_SRAM_FP)(__lfw_sram_start | 0x01);
+
+	/* Check valid address for jumpiing */
+	__ASSERT_NO_MSG(exeAddr != 0x0);
+	/* Configure QMSPI controller */
+	qspi->MODE = MCHP_QMSPI_M_SRST;
+	fdiv = 2;
+	if (pcr->TURBO_CLK & MCHP_PCR_TURBO_CLK_96M)
+		fdiv *= 2;
+
+	qspi->MODE = (fdiv << MCHP_QMSPI_M_FDIV_POS) & MCHP_QMSPI_M_FDIV_MASK;
+	qspi->MODE |= (MCHP_QMSPI_M_ACTIVATE | MCHP_QMSPI_M_LDMA_RX_EN);
+	qspi->CTRL = BIT(MCHP_QMSPI_C_DESCR_EN_POS);
+
+	/* Transmit 4 bytes(opcode + 24-bit address) on IO0 */
+	qspi->DESCR[0] =
+		(MCHP_QMSPI_C_IFM_1X | MCHP_QMSPI_C_TX_DATA |
+		 MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(4) |
+		 MCHP_QMSPI_C_NEXT_DESCR(1));
+
+	/* Transmit 8 clocks with IO0 and IO1 tri-stated */
+	qspi->DESCR[1] =
+		(MCHP_QMSPI_C_IFM_2X | MCHP_QMSPI_C_TX_DIS |
+		 MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(2) |
+		 MCHP_QMSPI_C_NEXT_DESCR(2));
+
+	/* Read using LDMA RX Chan 0, IFM=2x, Last Descriptor, close */
+	qspi->DESCR[2] = (MCHP_QMSPI_C_IFM_2X | MCHP_QMSPI_C_TX_DIS |
+			  MCHP_QMSPI_C_RX_EN | MCHP_QMSPI_C_RX_DMA_1B |
+			  MCHP_QMSPI_C_CLOSE | MCHP_QMSPI_C_DESCR_LAST |
+			  MCHP_QMSPI_C_NEXT_DESCR(0));
+
+	/* QSPI Local DMA RX channel 0 */
+	qspi->LDMA_RX_DESCR_BM = BIT(2); /* descriptor 2 uses RX LDMA */
+	qspi->LDRX[0].CTRL = MCHP_QMSPI_LDC_EN | MCHP_QMSPI_LDC_UCHL_EN |
+			     MCHP_QMSPI_LDC_INCR_EN;
+	qspi->LDRX[0].MSTART = dstAddr;
+	qspi->LDRX[0].LEN = size;
+
+	switch ((dstAddr | size) & 0x03u) {
+	case 0:
+		qspi->LDRX[0].CTRL |= MCHP_QMSPI_LDC_ASZ_4;
+		break;
+	case 2:
+		qspi->LDRX[0].CTRL |= MCHP_QMSPI_LDC_ASZ_2;
+		break;
+	default:
+		qspi->LDRX[0].CTRL |= MCHP_QMSPI_LDC_ASZ_1;
+		break;
+	}
+
+	cmdaddr = __builtin_bswap32(srcAddr & 0x00ffffff);
+	cmdaddr |= SPI_READ_112_FAST;
+
+	qspi->TX_FIFO = cmdaddr;
+
+	/* MCHP destination location */
+	/* Copy the __start_gdma_in_lpram instructions to LPRAM */
+	for (i = 0; i < &__flash_lplfw_end - &__flash_lplfw_start; i++) {
+		*((uint32_t *)__lfw_sram_start + i) =
+			*(&__flash_lplfw_start + i);
+	}
+
+	/* Call into SRAM routine to start QSPI */
+	__start_qspi_in_data_sram(resetVectAddr);
+}
diff --git a/zephyr/shim/chip/mchp/system_external_storage.c b/zephyr/shim/chip/mchp/system_external_storage.c
new file mode 100644
index 0000000000..b21a9aeb5d
--- /dev/null
+++ b/zephyr/shim/chip/mchp/system_external_storage.c
@@ -0,0 +1,132 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "bbram.h"
+#include "clock_chip.h"
+#include "common.h"
+#include "config_chip.h"
+#include "system.h"
+#include "system_chip.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/bbram.h>
+
+#include <soc.h>
+
+#define MCHP_ECRO_WORD 0x4F524345u /* ASCII ECRO */
+#define MCHP_ECRW_WORD 0x57524345u /* ASCII ECRW */
+#define MCHP_PCR_NODE DT_INST(0, microchip_xec_pcr)
+
+static const struct device *const bbram_dev =
+	COND_CODE_1(DT_HAS_CHOSEN(cros_ec_bbram),
+		    DEVICE_DT_GET(DT_CHOSEN(cros_ec_bbram)), NULL);
+
+/* Build image type string in RO/RW image */
+#ifdef CONFIG_CROS_EC_RO
+const uint32_t mchp_image_type = MCHP_ECRO_WORD;
+#elif CONFIG_CROS_EC_RW
+const uint32_t mchp_image_type = MCHP_ECRW_WORD;
+#else
+#error "Unsupported image type!"
+#endif
+
+/*
+ * Make sure CONFIG_XXX flash offsets are correct for MEC172x 512KB SPI flash.
+ */
+void system_jump_to_booter(void)
+{
+	static uint32_t flash_offset;
+	static uint32_t flash_used;
+
+	__disable_irq();
+
+	/*
+	 * Get memory offset and size for RO/RW regions.
+	 */
+	switch (system_get_shrspi_image_copy()) {
+	case EC_IMAGE_RW:
+		flash_offset =
+			CONFIG_EC_WRITABLE_STORAGE_OFF + CONFIG_RW_STORAGE_OFF;
+		flash_used = CONFIG_CROS_EC_RW_SIZE;
+		break;
+	case EC_IMAGE_RO:
+	default: /* Jump to RO by default */
+		flash_offset = CONFIG_PLATFORM_EC_RO_HEADER_OFFSET;
+		flash_used = CONFIG_CROS_EC_RO_SIZE;
+		break;
+	}
+
+	/*
+	 * Speed up FW download time by increasing clock freq of EC. It will
+	 * restore to default in clock_init() later.
+	 */
+	clock_turbo();
+
+	/* MCHP Read selected image from SPI flash into SRAM
+	 * Need a jump to little-fw (LFW).
+	 */
+	system_download_from_flash(flash_offset,
+				   CONFIG_CROS_EC_PROGRAM_MEMORY_BASE,
+				   flash_used,
+				   (CONFIG_CROS_EC_PROGRAM_MEMORY_BASE + 4u));
+}
+
+uint32_t system_get_lfw_address(void)
+{
+	uint32_t jump_addr = (uint32_t)system_jump_to_booter;
+	return jump_addr;
+}
+
+enum ec_image system_get_shrspi_image_copy(void)
+{
+	enum ec_image img = EC_IMAGE_UNKNOWN;
+	uint32_t value = 0u;
+
+	if (bbram_dev) {
+		if (!bbram_read(bbram_dev, BBRAM_REGION_OFFSET(ec_img_load),
+				BBRAM_REGION_SIZE(ec_img_load),
+				(uint8_t *)&value)) {
+			img = (enum ec_image)(value & 0x7fu);
+		}
+	}
+
+	if (img == EC_IMAGE_UNKNOWN) {
+		img = EC_IMAGE_RO;
+		if (mchp_image_type == MCHP_ECRW_WORD) {
+			img = EC_IMAGE_RW;
+		}
+		system_set_image_copy(img);
+	}
+
+	return img;
+}
+
+/* Flash is not memory mapped. Store a flag indicating the image.
+ * ECS WDT_CNT is register available to applications. It implements bits[3:0]
+ * which are not reset by a watch dog event only by VTR/chip reset.
+ * VBAT memory is safer only if the board has a stable VBAT power rail.
+ */
+void system_set_image_copy(enum ec_image copy)
+{
+	uint32_t value = (uint32_t)copy;
+
+	if (!bbram_dev) {
+		return;
+	}
+
+	switch (copy) {
+	case EC_IMAGE_RW:
+	case EC_IMAGE_RW_B:
+		value = EC_IMAGE_RW;
+		break;
+	case EC_IMAGE_RO:
+	default:
+		value = EC_IMAGE_RO;
+		break;
+	}
+
+	bbram_write(bbram_dev, BBRAM_REGION_OFFSET(ec_img_load),
+		    BBRAM_REGION_SIZE(ec_img_load), (uint8_t *)&value);
+}
diff --git a/zephyr/shim/chip/npcx/CMakeLists.txt b/zephyr/shim/chip/npcx/CMakeLists.txt
new file mode 100644
index 0000000000..79b8cf2a62
--- /dev/null
+++ b/zephyr/shim/chip/npcx/CMakeLists.txt
@@ -0,0 +1,24 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# When building code coverage, the final Zephyr image isn't actually linked
+# and there's no valid image to program. Skip compiling and linking the NPCX
+# monitor when coverage is enabled.
+if (NOT DEFINED CONFIG_COVERAGE)
+  add_subdirectory(npcx_monitor)
+endif()
+
+cros_ec_library_include_directories(include)
+
+zephyr_library_sources(clock.c)
+zephyr_library_sources(gpio.c)
+zephyr_library_sources_ifdef(CONFIG_CROS_KB_RAW_NPCX  keyboard_raw.c)
+zephyr_library_sources_ifdef(CONFIG_CROS_SHI_NPCX     shi.c)
+zephyr_library_sources_ifdef(CONFIG_CROS_EC           system.c)
+
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_EXTERNAL_STORAGE
+        system_external_storage.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API
+        system_download_from_flash.c)
+zephyr_library_sources_ifdef(CONFIG_PM_POLICY_CUSTOM  power_policy.c)
diff --git a/zephyr/shim/chip/npcx/Kconfig.npcx b/zephyr/shim/chip/npcx/Kconfig.npcx
new file mode 100644
index 0000000000..5202d14448
--- /dev/null
+++ b/zephyr/shim/chip/npcx/Kconfig.npcx
@@ -0,0 +1,66 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if PLATFORM_EC
+
+config CROS_SYSTEM_NPCX_PRE_INIT_PRIORITY
+	int "System pre-initialization priority"
+	default 15
+	range 10 19
+	depends on SOC_FAMILY_NPCX
+	help
+	  This sets the priority of the NPCX chip system initialization. The
+	  chip system initialization verifies the integrity of the BBRAM and
+	  must be a lower priority than CONFIG_BBRAM_INIT_PRIORITY and
+	  must be a higher priority than PLATFORM_EC_SYSTEM_PRE_INIT.
+
+config PLATFORM_EC_CONSOLE_CMD_GPIODBG
+	bool "Console command: gpiodbg"
+	depends on SOC_FAMILY_NPCX
+	help
+	  Enable the "gpiodbg" command. This lists all IO pads used on platform
+	  and turns on/off specific pad's input buffer to observe leakage
+	  current through it.
+
+	  Example:
+	     gpiodbg list
+
+	     IDX|ON| GPIO | Name
+	     ---+--+------+----------
+	     00 |* | io03 | recovery_l
+	     01 |* | io93 | wp_l
+	     02 |* | iod2 | ac_present
+	     03 |* | io00 | power_button_l
+	     04 |* | io01 | lid_open
+	     05 |* | io36 | entering_rw
+	     06 |* | io50 | pch_wake_l
+	     07 |* | ioc7 | pgood_fan
+	     08 |* | ioa5 | spi_cs_l
+	     09 |* | io64 | board_version1
+	     10 |* | io65 | board_version2
+	     11 |* | io66 | board_version3
+	     12 |* | io52 | unused pin
+	     13 |* | io54 | unused pin
+
+	     gpiodbg off 11
+	     gpiodbg list
+
+	     IDX|ON| GPIO | Name
+	     ---+--+------+----------
+	     00 |* | io03 | recovery_l
+	     01 |* | io93 | wp_l
+	     02 |* | iod2 | ac_present
+	     03 |* | io00 | power_button_l
+	     04 |* | io01 | lid_open
+	     05 |* | io36 | entering_rw
+	     06 |* | io50 | pch_wake_l
+	     07 |* | ioc7 | pgood_fan
+	     08 |* | ioa5 | spi_cs_l
+	     09 |* | io64 | board_version1
+	     10 |* | io65 | board_version2
+	     11 |  | io66 | board_version3
+	     12 |* | io52 | unused pin
+	     13 |* | io54 | unused pin
+
+endif # PLATFORM_EC
diff --git a/zephyr/shim/chip/npcx/clock.c b/zephyr/shim/chip/npcx/clock.c
new file mode 100644
index 0000000000..f6d1a5db98
--- /dev/null
+++ b/zephyr/shim/chip/npcx/clock.c
@@ -0,0 +1,79 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "clock_chip.h"
+#include "common.h"
+#include "module_id.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/dt-bindings/clock/npcx_clock.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+
+#include <soc.h>
+
+LOG_MODULE_REGISTER(shim_clock, LOG_LEVEL_ERR);
+
+#define CDCG_NODE DT_INST(0, nuvoton_npcx_pcc)
+#define HAL_CDCG_REG_BASE_ADDR \
+	((struct cdcg_reg *)DT_REG_ADDR_BY_IDX(CDCG_NODE, 1))
+
+int clock_get_freq(void)
+{
+	const struct device *clk_dev = DEVICE_DT_GET(NPCX_CLK_CTRL_NODE);
+	const struct npcx_clk_cfg clk_cfg = {
+		.bus = NPCX_CLOCK_BUS_CORE,
+	};
+	uint32_t rate;
+
+	if (clock_control_get_rate(clk_dev, (clock_control_subsys_t *)&clk_cfg,
+				   &rate) != 0) {
+		LOG_ERR("Get %s clock rate error", clk_dev->name);
+		return -EIO;
+	}
+
+	return rate;
+}
+
+void clock_turbo(void)
+{
+	struct cdcg_reg *const cdcg_base = HAL_CDCG_REG_BASE_ADDR;
+
+#if defined(CONFIG_SOC_SERIES_NPCX9)
+	/* For NPCX9:
+	 * Increase CORE_CLK (CPU) as the same as OSC_CLK. Since
+	 * CORE_CLK > 66MHz, we also need to set FIUDIV as 1 but
+	 * can keep AHB6DIV to 0.
+	 */
+	cdcg_base->HFCGP = 0x00;
+#else
+	/* For NPCX7:
+	 * Increase CORE_CLK (CPU) as the same as OSC_CLK. Since
+	 * CORE_CLK > 66MHz, we also need to set AHB6DIV and FIUDIV as 1.
+	 */
+	cdcg_base->HFCGP = 0x01;
+#endif
+	cdcg_base->HFCBCD = BIT(4);
+}
+
+void clock_normal(void)
+{
+	struct cdcg_reg *const cdcg_base = HAL_CDCG_REG_BASE_ADDR;
+
+	cdcg_base->HFCGP = ((FPRED_VAL << 4) | AHB6DIV_VAL);
+	cdcg_base->HFCBCD = (FIUDIV_VAL << 4);
+}
+
+test_mockable void clock_enable_module(enum module_id module, int enable)
+{
+	/* Assume we have a single task using MODULE_FAST_CPU */
+	if (module == MODULE_FAST_CPU) {
+		if (enable)
+			clock_turbo();
+		else
+			clock_normal();
+	}
+}
diff --git a/zephyr/shim/chip/npcx/gpio.c b/zephyr/shim/chip/npcx/gpio.c
new file mode 100644
index 0000000000..ed702bb8bb
--- /dev/null
+++ b/zephyr/shim/chip/npcx/gpio.c
@@ -0,0 +1,204 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "gpio/gpio.h"
+#include "soc_gpio.h"
+#include "util.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/shell/shell.h>
+
+LOG_MODULE_REGISTER(shim_cros_gpio, LOG_LEVEL_ERR);
+
+static const struct unused_pin_config unused_pin_configs[] = {
+	UNUSED_GPIO_CONFIG_LIST
+};
+
+int gpio_config_unused_pins(void)
+{
+	for (size_t i = 0; i < ARRAY_SIZE(unused_pin_configs); ++i) {
+		int rv;
+		int flags;
+		const struct device *dev =
+			device_get_binding(unused_pin_configs[i].dev_name);
+
+		if (dev == NULL) {
+			LOG_ERR("Not found (%s)",
+				unused_pin_configs[i].dev_name);
+			return -ENOTSUP;
+		}
+
+		/*
+		 * Set the default setting for the floating IOs. The floating
+		 * IOs cause the leakage current. Set unused pins as input with
+		 * internal PU to prevent extra power consumption.
+		 */
+		if (unused_pin_configs[i].flags == 0)
+			flags = GPIO_INPUT | GPIO_PULL_UP;
+		else
+			flags = unused_pin_configs[i].flags;
+
+		rv = gpio_pin_configure(dev, unused_pin_configs[i].pin, flags);
+
+		if (rv < 0) {
+			LOG_ERR("Config failed %s-%d (%d)",
+				unused_pin_configs[i].dev_name,
+				unused_pin_configs[i].pin, rv);
+			return rv;
+		}
+	}
+
+	return 0;
+}
+
+int gpio_configure_port_pin(int port, int id, int flags)
+{
+	const struct device *dev = npcx_get_gpio_dev(port);
+
+	return gpio_pin_configure(dev, id, flags);
+}
+
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_GPIODBG
+/*
+ * IO information about each GPIO that is configured in the `named_gpios` and
+ *` unused_pins` device tree nodes.
+ */
+struct npcx_io_info {
+	/* A npcx gpio port device */
+	const struct device *dev;
+	/* A npcx gpio port number */
+	int port;
+	/* Bit number of pin within a npcx gpio port */
+	gpio_pin_t pin;
+	/* GPIO net name */
+	const char *name;
+	/* Enable flag of npcx gpio input buffer */
+	bool enable;
+};
+
+#define NAMED_GPIO_INFO(node)                                      \
+	{                                                          \
+		.dev = DEVICE_DT_GET(DT_GPIO_CTLR(node, gpios)),   \
+		.port = DT_PROP(DT_GPIO_CTLR(node, gpios), index), \
+		.pin = DT_GPIO_PIN(node, gpios),                   \
+		.name = DT_NODE_FULL_NAME(node),                   \
+		.enable = true,                                    \
+	},
+
+#define UNUSED_GPIO_INFO(node, prop, idx)                                     \
+	{                                                                     \
+		.dev = DEVICE_DT_GET(DT_GPIO_CTLR_BY_IDX(node, prop, idx)),   \
+		.port = DT_PROP(DT_GPIO_CTLR_BY_IDX(node, prop, idx), index), \
+		.pin = DT_GPIO_PIN_BY_IDX(node, prop, idx),                   \
+		.name = "unused pin",                                         \
+		.enable = true,                                               \
+	},
+
+#define NAMED_GPIO_INIT(node) \
+	COND_CODE_1(DT_NODE_HAS_PROP(node, gpios), (NAMED_GPIO_INFO(node)), ())
+
+static struct npcx_io_info gpio_info[] = {
+#if DT_NODE_EXISTS(NAMED_GPIOS_NODE)
+	DT_FOREACH_CHILD(NAMED_GPIOS_NODE, NAMED_GPIO_INIT)
+#endif
+#if DT_NODE_EXISTS(UNUSED_GPIOS_NODE)
+		DT_FOREACH_PROP_ELEM(UNUSED_GPIOS_NODE, unused_gpios,
+				     UNUSED_GPIO_INFO)
+#endif
+};
+
+static int get_index_from_arg(const struct shell *sh, char **argv, int *index)
+{
+	char *end_ptr;
+	int num = strtol(argv[1], &end_ptr, 0);
+	const int gpio_cnt = ARRAY_SIZE(gpio_info);
+
+	if (*end_ptr != '\0') {
+		shell_error(sh, "Failed to parse %s", argv[1]);
+		return -EINVAL;
+	}
+
+	if (num >= gpio_cnt) {
+		shell_error(sh, "Index shall be less than %u, was %u", gpio_cnt,
+			    num);
+		return -EINVAL;
+	}
+
+	*index = num;
+
+	return 0;
+}
+
+static int cmd_gpio_list_all(const struct shell *sh, size_t argc, char **argv)
+{
+	ARG_UNUSED(argc);
+	ARG_UNUSED(argv);
+
+	/* Print header */
+	shell_print(sh, "IDX|ON| GPIO | Name");
+	shell_print(sh, "---+--+------+----------");
+
+	/* List all GPIOs in 'named-gpios' and 'unused_pins' DT nodes */
+	for (int i = 0; i < ARRAY_SIZE(gpio_info); i++) {
+		shell_print(sh, "%02d |%s | io%x%x | %s", i,
+			    gpio_info[i].enable ? "*" : " ", gpio_info[i].port,
+			    gpio_info[i].pin, gpio_info[i].name);
+	}
+
+	return 0;
+}
+
+static int cmd_gpio_turn_on(const struct shell *sh, size_t argc, char **argv)
+{
+	int index;
+	int res = get_index_from_arg(sh, argv, &index);
+
+	if (res < 0) {
+		return res;
+	}
+
+	/* Turn on GPIO's input buffer by index */
+	gpio_info[index].enable = true;
+	npcx_gpio_enable_io_pads(gpio_info[index].dev, gpio_info[index].pin);
+
+	return 0;
+}
+
+static int cmd_gpio_turn_off(const struct shell *sh, size_t argc, char **argv)
+{
+	int index;
+	int res = get_index_from_arg(sh, argv, &index);
+
+	if (res < 0) {
+		return res;
+	}
+
+	/* Turn off GPIO's input buffer by index */
+	gpio_info[index].enable = false;
+	npcx_gpio_disable_io_pads(gpio_info[index].dev, gpio_info[index].pin);
+
+	return 0;
+}
+
+SHELL_STATIC_SUBCMD_SET_CREATE(
+	sub_gpiodbg,
+	SHELL_CMD_ARG(list, NULL, "List all GPIOs used on platform by index",
+		      cmd_gpio_list_all, 1, 0),
+	SHELL_CMD_ARG(on, NULL, "<index_in_list> Turn on GPIO's input buffer",
+		      cmd_gpio_turn_on, 2, 0),
+	SHELL_CMD_ARG(off, NULL, "<index_in_list> Turn off GPIO's input buffer",
+		      cmd_gpio_turn_off, 2, 0),
+	SHELL_SUBCMD_SET_END /* Array terminated. */
+);
+
+SHELL_CMD_ARG_REGISTER(gpiodbg, &sub_gpiodbg,
+		       "Commands for power consumption "
+		       "investigation",
+		       NULL, 2, 0);
+
+#endif /* CONFIG_PLATFORM_EC_CONSOLE_CMD_GPIODBG */
diff --git a/zephyr/shim/chip/npcx/include/clock_chip.h b/zephyr/shim/chip/npcx/include/clock_chip.h
new file mode 100644
index 0000000000..6ecca330b6
--- /dev/null
+++ b/zephyr/shim/chip/npcx/include/clock_chip.h
@@ -0,0 +1,14 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_CLOCK_CHIP_H
+#define __CROS_EC_CLOCK_CHIP_H
+
+/**
+ * TODO(b:180112248) implement in zephyr's clock_control.h
+ */
+void clock_turbo(void);
+
+#endif /* __CROS_EC_CLOCK_CHIP_H */
diff --git a/zephyr/shim/chip/npcx/include/flash_chip.h b/zephyr/shim/chip/npcx/include/flash_chip.h
new file mode 100644
index 0000000000..d4c800e434
--- /dev/null
+++ b/zephyr/shim/chip/npcx/include/flash_chip.h
@@ -0,0 +1,28 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_FLASH_CHIP_H
+#define __CROS_EC_FLASH_CHIP_H
+
+#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
+
+#define CONFIG_FLASH_WRITE_SIZE 0x1 /* minimum write size */
+#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* one page size for write */
+#define CONFIG_FLASH_ERASE_SIZE CONFIG_PLATFORM_EC_NPCX_FLASH_ERASE_SIZE
+/*
+ * The smallest protection bank size is 1/8 of 512 KB or 1/16 of 1M flash,
+ * i.e. 64KB.
+ */
+#define CONFIG_FLASH_BANK_SIZE 0x10000
+
+/* RO image resides at start of protected region, right after header */
+#define CONFIG_RO_STORAGE_OFF CONFIG_RO_HDR_SIZE
+
+#define CONFIG_RW_STORAGE_OFF 0
+
+/* Use 4k sector erase for NPCX monitor flash erase operations. */
+#define NPCX_MONITOR_FLASH_ERASE_SIZE 0x1000
+
+#endif /* __CROS_EC_FLASH_CHIP_H */
diff --git a/zephyr/shim/chip/npcx/include/rom_chip.h b/zephyr/shim/chip/npcx/include/rom_chip.h
new file mode 100644
index 0000000000..d59a649c7b
--- /dev/null
+++ b/zephyr/shim/chip/npcx/include/rom_chip.h
@@ -0,0 +1,57 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_ROM_CHIP_H
+#define __CROS_EC_ROM_CHIP_H
+
+#include "common.h"
+
+/* Enumerations of ROM api functions */
+enum API_SIGN_OPTIONS_T {
+	SIGN_NO_CHECK = 0,
+	SIGN_CRC_CHECK = 1,
+};
+
+enum API_RETURN_STATUS_T {
+	/* Successful download */
+	API_RET_STATUS_OK = 0,
+	/* Address is outside of flash or not 4 bytes aligned. */
+	API_RET_STATUS_INVALID_SRC_ADDR = 1,
+	/* Address is outside of RAM or not 4 bytes aligned. */
+	API_RET_STATUS_INVALID_DST_ADDR = 2,
+	/* Size is 0 or not 4 bytes aligned. */
+	API_RET_STATUS_INVALID_SIZE = 3,
+	/* Flash Address + Size is out of flash. */
+	API_RET_STATUS_INVALID_SIZE_OUT_OF_FLASH = 4,
+	/* RAM Address + Size is out of RAM. */
+	API_RET_STATUS_INVALID_SIZE_OUT_OF_RAM = 5,
+	/* Wrong sign option. */
+	API_RET_STATUS_INVALID_SIGN = 6,
+	/* Error during Code copy. */
+	API_RET_STATUS_COPY_FAILED = 7,
+	/* Execution Address is outside of RAM */
+	API_RET_STATUS_INVALID_EXE_ADDR = 8,
+	/* Bad CRC value */
+	API_RET_STATUS_INVALID_SIGNATURE = 9,
+};
+
+/* Macro functions of ROM api functions */
+#define ADDR_DOWNLOAD_FROM_FLASH (*(volatile uint32_t *)0x40)
+#define download_from_flash(src_offset, dest_addr, size, sign, exe_addr, \
+			    status)                                      \
+	(((download_from_flash_ptr)ADDR_DOWNLOAD_FROM_FLASH)(            \
+		src_offset, dest_addr, size, sign, exe_addr, status))
+
+/* Declarations of ROM api functions */
+typedef void (*download_from_flash_ptr)(
+	uint32_t src_offset, /* The offset of the data to be downloaded */
+	uint32_t dest_addr, /* The address of the downloaded data in the RAM*/
+	uint32_t size, /* Number of bytes to download */
+	enum API_SIGN_OPTIONS_T sign, /* Need CRC check or not */
+	uint32_t exe_addr, /* jump to this address after download if not zero */
+	enum API_RETURN_STATUS_T *status /* Status fo download */
+);
+
+#endif /* __CROS_EC_ROM_CHIP_H */
diff --git a/zephyr/shim/chip/npcx/include/system_chip.h b/zephyr/shim/chip/npcx/include/system_chip.h
new file mode 100644
index 0000000000..2f59ad4627
--- /dev/null
+++ b/zephyr/shim/chip/npcx/include/system_chip.h
@@ -0,0 +1,80 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_SYSTEM_CHIP_H_
+#define __CROS_EC_SYSTEM_CHIP_H_
+
+#define SET_BIT(reg, bit) ((reg) |= (0x1 << (bit)))
+#define CLEAR_BIT(reg, bit) ((reg) &= (~(0x1 << (bit))))
+
+/* TODO(b:179900857) Clean this up too */
+#undef IS_BIT_SET
+#define IS_BIT_SET(reg, bit) (((reg) >> (bit)) & (0x1))
+
+/*****************************************************************************/
+/* Memory mapping */
+#define CONFIG_LPRAM_BASE 0x40001400 /* memory address of lpwr ram */
+#define CONFIG_LPRAM_SIZE 0x00000620 /* 1568B low power ram */
+
+/******************************************************************************/
+/* Optional M4 Registers */
+#define CPU_MPU_CTRL REG32(0xE000ED94)
+#define CPU_MPU_RNR REG32(0xE000ED98)
+#define CPU_MPU_RBAR REG32(0xE000ED9C)
+#define CPU_MPU_RASR REG32(0xE000EDA0)
+
+/*
+ * Region assignment. 7 as the highest, a higher index has a higher priority.
+ * For example, using 7 for .iram.text allows us to mark entire RAM XN except
+ * .iram.text, which is used for hibernation.
+ * Region assignment is currently wasteful and can be changed if more
+ * regions are needed in the future. For example, a second region may not
+ * be necessary for all types, and REGION_CODE_RAM / REGION_STORAGE can be
+ * made mutually exclusive.
+ */
+enum mpu_region {
+	REGION_DATA_RAM = 0, /* For internal data RAM */
+	REGION_DATA_RAM2 = 1, /* Second region for unaligned size */
+	REGION_CODE_RAM = 2, /* For internal code RAM */
+	REGION_CODE_RAM2 = 3, /* Second region for unaligned size */
+	REGION_STORAGE = 4, /* For mapped internal storage */
+	REGION_STORAGE2 = 5, /* Second region for unaligned size */
+	REGION_DATA_RAM_TEXT = 6, /* Exempt region of data RAM */
+	REGION_CHIP_RESERVED = 7, /* Reserved for use in chip/ */
+	/* only for chips with MPU supporting 16 regions */
+	REGION_UNCACHED_RAM = 8, /* For uncached data RAM */
+	REGION_UNCACHED_RAM2 = 9, /* Second region for unaligned size */
+	REGION_ROLLBACK = 10, /* For rollback */
+};
+
+/*
+ * Configure the specific memory addresses in the the MPU
+ * (Memory Protection Unit) for Nuvoton different chip series.
+ */
+void system_mpu_config(void);
+
+/* The utilities and variables depend on npcx chip family */
+#if defined(CONFIG_SOC_SERIES_NPCX5) || \
+	defined(CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API)
+/* Bypass for GMDA issue of ROM api utilities only on npcx5 series or if
+ * CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API is defined.
+ */
+void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr,
+				uint32_t size, uint32_t exeAddr);
+
+/* Begin address for hibernate utility; defined in linker script */
+extern unsigned int __flash_lpfw_start;
+
+/* End address for hibernate utility; defined in linker script */
+extern unsigned int __flash_lpfw_end;
+
+/* Begin address for little FW; defined in linker script */
+extern unsigned int __flash_lplfw_start;
+
+/* End address for little FW; defined in linker script */
+extern unsigned int __flash_lplfw_end;
+#endif
+
+#endif // __CROS_EC_SYSTEM_CHIP_H_
diff --git a/zephyr/shim/chip/npcx/keyboard_raw.c b/zephyr/shim/chip/npcx/keyboard_raw.c
new file mode 100644
index 0000000000..1f01952ab9
--- /dev/null
+++ b/zephyr/shim/chip/npcx/keyboard_raw.c
@@ -0,0 +1,27 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Functions needed by keyboard scanner module for Chrome EC */
+
+#include "drivers/cros_kb_raw.h"
+#include "keyboard_raw.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+
+#include <soc.h>
+#include <soc_gpio.h>
+
+/**
+ * Return true if the current value of the given input GPIO port is zero
+ */
+int keyboard_raw_is_input_low(int port, int id)
+{
+	const struct device *io_dev = npcx_get_gpio_dev(port);
+
+	return gpio_pin_get_raw(io_dev, id) == 0;
+}
diff --git a/zephyr/shim/chip/npcx/npcx_monitor/CMakeLists.txt b/zephyr/shim/chip/npcx/npcx_monitor/CMakeLists.txt
new file mode 100644
index 0000000000..d74881b2d9
--- /dev/null
+++ b/zephyr/shim/chip/npcx/npcx_monitor/CMakeLists.txt
@@ -0,0 +1,47 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# The NPCX monitor source needs the chip type and flash layout information
+# provided by the board configuration. This is provided by
+# zephyr/shim/include/config_chip.h, so we need all the include directories
+# of the Zephyr application.
+zephyr_get_include_directories_for_lang(C zephyr_includes STRIP_PREFIX)
+
+# Something in the zephyr_get_compile_options_for_lang() output causes the
+# "-imacros" option to get dropped during expansion when passed to
+# target_compile_options().  Fetch the compile options directly from
+# zephyr_interface which works as expected.
+get_property(
+  zephyr_compile_options
+  TARGET zephyr_interface
+  PROPERTY INTERFACE_COMPILE_OPTIONS
+  )
+
+add_executable(npcx_monitor npcx_monitor.c)
+target_include_directories(npcx_monitor PRIVATE
+  "${PLATFORM_EC}/zephyr/shim/include"
+  "${PLATFORM_EC}/zephyr/shim/chip/npcx/include"
+  )
+target_include_directories(npcx_monitor PRIVATE "${zephyr_includes}")
+target_compile_options(npcx_monitor PRIVATE "${zephyr_compile_options}")
+
+target_link_options(npcx_monitor BEFORE PRIVATE
+  -nostdlib
+  -g
+  -mthumb
+  -Wl,-T,${CMAKE_CURRENT_SOURCE_DIR}/npcx_monitor.ld
+  )
+
+# Create the NPCX monitor binary, locate it the root of the build
+# directory as it needs to be found by the flash_util script
+set(npcx_monitor_elf ${CMAKE_CURRENT_BINARY_DIR}/npcx_monitor.elf)
+set(npcx_monitor_bin ${CMAKE_BINARY_DIR}/npcx_monitor.bin)
+
+add_custom_target(generate_npcx_monitor
+  COMMAND ${CMAKE_OBJCOPY} -O binary ${npcx_monitor_elf} ${npcx_monitor_bin}
+  BYPRODUCTS ${npcx_monitor_bin}
+  DEPENDS npcx_monitor
+  )
+
+add_dependencies(zephyr generate_npcx_monitor)
diff --git a/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.c b/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.c
new file mode 100644
index 0000000000..3062ed98a4
--- /dev/null
+++ b/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.c
@@ -0,0 +1,343 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * NPCX SoC spi flash update tool - monitor firmware
+ */
+
+#include "config_chip.h"
+#include "npcx_monitor.h"
+#include "registers.h"
+
+#include <stdint.h>
+
+#include <zephyr/sys/util.h>
+
+/*
+ * TODO(b/197162681): This was copied from chip/npcx/spiflashfw but this
+ * needs to be moved to Zephyr upstream
+ */
+
+/*****************************************************************************/
+/* spi flash internal functions */
+void sspi_flash_pinmux(int enable)
+{
+	if (enable)
+		CLEAR_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_NO_F_SPI);
+	else
+		SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_NO_F_SPI);
+
+	/* CS0/1 pinmux */
+	if (enable) {
+#if (FIU_CHIP_SELECT == 1)
+		SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_F_SPI_CS1_1);
+#elif (FIU_CHIP_SELECT == 2)
+		SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_F_SPI_CS1_2);
+#endif
+	} else {
+		CLEAR_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_F_SPI_CS1_1);
+		CLEAR_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_F_SPI_CS1_2);
+	}
+}
+
+void sspi_flash_tristate(int enable)
+{
+	if (enable) {
+		/* Enable FIU pins to tri-state */
+		SET_BIT(NPCX_DEVCNT, NPCX_DEVCNT_F_SPI_TRIS);
+	} else {
+		/* Disable FIU pins to tri-state */
+		CLEAR_BIT(NPCX_DEVCNT, NPCX_DEVCNT_F_SPI_TRIS);
+	}
+}
+
+void sspi_flash_execute_cmd(uint8_t code, uint8_t cts)
+{
+	/* set UMA_CODE */
+	NPCX_UMA_CODE = code;
+	/* execute UMA flash transaction */
+	NPCX_UMA_CTS = cts;
+	while (IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE))
+		;
+}
+
+void sspi_flash_cs_level(int level)
+{
+	/* level is high */
+	if (level) {
+		/* Set chip select to high */
+		SET_BIT(NPCX_UMA_ECTS, NPCX_UMA_ECTS_SW_CS1);
+	} else { /* level is low */
+		/* Set chip select to low */
+		CLEAR_BIT(NPCX_UMA_ECTS, NPCX_UMA_ECTS_SW_CS1);
+	}
+}
+
+void sspi_flash_wait_ready(void)
+{
+	uint8_t mask = SPI_FLASH_SR1_BUSY;
+
+	/* Chip Select down. */
+	sspi_flash_cs_level(0);
+	/* Command for Read status register */
+	sspi_flash_execute_cmd(CMD_READ_STATUS_REG, MASK_CMD_ONLY);
+	do {
+		/* Read status register */
+		NPCX_UMA_CTS = MASK_RD_1BYTE;
+		while (IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE))
+			;
+	} while (NPCX_UMA_DB0 & mask); /* Wait for Busy clear */
+	/* Chip Select high. */
+	sspi_flash_cs_level(1);
+}
+
+int sspi_flash_write_enable(void)
+{
+	uint8_t mask = SPI_FLASH_SR1_WEL;
+	/* Write enable command */
+	sspi_flash_execute_cmd(CMD_WRITE_EN, MASK_CMD_ONLY);
+	/* Wait for flash is not busy */
+	sspi_flash_wait_ready();
+
+	if (NPCX_UMA_DB0 & mask)
+		return 1;
+	else
+		return 0;
+}
+
+void sspi_flash_set_address(uint32_t dest_addr)
+{
+	uint8_t *addr = (uint8_t *)&dest_addr;
+	/* Write address */
+	NPCX_UMA_AB2 = addr[2];
+	NPCX_UMA_AB1 = addr[1];
+	NPCX_UMA_AB0 = addr[0];
+}
+
+void sspi_flash_burst_write(unsigned int dest_addr, unsigned int bytes,
+			    const char *data)
+{
+	unsigned int i;
+	/* Chip Select down. */
+	sspi_flash_cs_level(0);
+	/* Set erase address */
+	sspi_flash_set_address(dest_addr);
+	/* Start write */
+	sspi_flash_execute_cmd(CMD_FLASH_PROGRAM, MASK_CMD_WR_ADR);
+	for (i = 0; i < bytes; i++) {
+		sspi_flash_execute_cmd(*data, MASK_CMD_WR_ONLY);
+		data++;
+	}
+	/* Chip Select up */
+	sspi_flash_cs_level(1);
+}
+
+int sspi_flash_physical_clear_stsreg(void)
+{
+	/* Disable tri-state */
+	sspi_flash_tristate(0);
+	/* Enable write */
+	sspi_flash_write_enable();
+
+	NPCX_UMA_DB0 = 0x0;
+	NPCX_UMA_DB1 = 0x0;
+
+	/* Write status register 1/2 */
+	sspi_flash_execute_cmd(CMD_WRITE_STATUS_REG, MASK_CMD_WR_2BYTE);
+
+	/* Wait writing completed */
+	sspi_flash_wait_ready();
+
+	/* Read status register 1/2 for checking */
+	sspi_flash_execute_cmd(CMD_READ_STATUS_REG, MASK_CMD_RD_1BYTE);
+	if (NPCX_UMA_DB0 != 0x00)
+		return 0;
+	sspi_flash_execute_cmd(CMD_READ_STATUS_REG2, MASK_CMD_RD_1BYTE);
+	if (NPCX_UMA_DB0 != 0x00)
+		return 0;
+	/* Enable tri-state */
+	sspi_flash_tristate(1);
+
+	return 1;
+}
+
+void sspi_flash_physical_write(int offset, int size, const char *data)
+{
+	int dest_addr = offset;
+	const int sz_page = CONFIG_FLASH_WRITE_IDEAL_SIZE;
+
+	/* Disable tri-state */
+	sspi_flash_tristate(0);
+
+	/* Write the data per CONFIG_FLASH_WRITE_IDEAL_SIZE bytes */
+	for (; size >= sz_page; size -= sz_page) {
+		/* Enable write */
+		sspi_flash_write_enable();
+		/* Burst UMA transaction */
+		sspi_flash_burst_write(dest_addr, sz_page, data);
+		/* Wait write completed */
+		sspi_flash_wait_ready();
+
+		data += sz_page;
+		dest_addr += sz_page;
+	}
+
+	/* Handle final partial page, if any */
+	if (size != 0) {
+		/* Enable write */
+		sspi_flash_write_enable();
+		/* Burst UMA transaction */
+		sspi_flash_burst_write(dest_addr, size, data);
+
+		/* Wait write completed */
+		sspi_flash_wait_ready();
+	}
+
+	/* Enable tri-state */
+	sspi_flash_tristate(1);
+}
+
+void sspi_flash_physical_erase(int offset, int size)
+{
+	/* Disable tri-state */
+	sspi_flash_tristate(0);
+
+	/* Alignment has been checked in upper layer */
+	for (; size > 0; size -= NPCX_MONITOR_FLASH_ERASE_SIZE,
+			 offset += NPCX_MONITOR_FLASH_ERASE_SIZE) {
+		/* Enable write */
+		sspi_flash_write_enable();
+		/* Set erase address */
+		sspi_flash_set_address(offset);
+		/* Start erase */
+		sspi_flash_execute_cmd(CMD_SECTOR_ERASE, MASK_CMD_ADR);
+
+		/* Wait erase completed */
+		sspi_flash_wait_ready();
+	}
+
+	/* Enable tri-state */
+	sspi_flash_tristate(1);
+}
+
+int sspi_flash_verify(int offset, int size, const char *data)
+{
+	int i, result;
+	uint8_t *ptr_flash;
+	uint8_t *ptr_mram;
+	uint8_t cmp_data;
+
+	ptr_flash = (uint8_t *)(CONFIG_MAPPED_STORAGE_BASE + offset);
+	ptr_mram = (uint8_t *)data;
+	result = 1;
+
+	/* Disable tri-state */
+	sspi_flash_tristate(0);
+
+	/* Start to verify */
+	for (i = 0; i < size; i++) {
+		cmp_data = ptr_mram ? ptr_mram[i] : 0xFF;
+		if (ptr_flash[i] != cmp_data) {
+			result = 0;
+			break;
+		}
+	}
+
+	/* Enable tri-state */
+	sspi_flash_tristate(1);
+	return result;
+}
+
+int sspi_flash_get_image_used(const char *fw_base)
+{
+	const uint8_t *image;
+	int size = MAX(CONFIG_RO_SIZE, CONFIG_RW_SIZE); /* max size is 128KB */
+
+	image = (const uint8_t *)fw_base;
+	/*
+	 * Scan backwards looking for 0xea byte, which is by definition the
+	 * last byte of the image.  See ec.lds.S for how this is inserted at
+	 * the end of the image.
+	 */
+	for (size--; size > 0 && image[size] != 0xea; size--)
+		;
+
+	return size ? size + 1 : 0; /* 0xea byte IS part of the image */
+}
+
+/* Entry function of spi upload function */
+uint32_t __attribute__((section(".startup_text")))
+sspi_flash_upload(int spi_offset, int spi_size)
+{
+	/*
+	 * Flash image has been uploaded to Code RAM
+	 */
+	uint32_t sz_image;
+	uint32_t uut_tag;
+	const char *image_base;
+	uint32_t *flag_upload = (uint32_t *)SPI_PROGRAMMING_FLAG;
+	struct monitor_header_tag *monitor_header =
+		(struct monitor_header_tag *)NPCX_MONITOR_HEADER_ADDR;
+
+	*flag_upload = 0;
+
+	uut_tag = monitor_header->tag;
+	/* If it is UUT tag, read required parameters from header */
+	if (uut_tag == NPCX_MONITOR_UUT_TAG) {
+		sz_image = monitor_header->size;
+		spi_offset = monitor_header->dest_addr;
+		image_base = (const char *)(monitor_header->src_addr);
+	} else {
+		sz_image = spi_size;
+		image_base = (const char *)CONFIG_PROGRAM_MEMORY_BASE;
+	}
+
+	/* Unlock & stop watchdog */
+	NPCX_WDSDM = 0x87;
+	NPCX_WDSDM = 0x61;
+	NPCX_WDSDM = 0x63;
+
+	/* UMA Unlock */
+	CLEAR_BIT(NPCX_UMA_ECTS, NPCX_UMA_ECTS_UMA_LOCK);
+
+	/*
+	 * If UUT is used, assuming the target is the internal flash.
+	 * Don't switch the pinmux and make sure bit 7 of DEVALT0 is set.
+	 */
+	if (uut_tag == NPCX_MONITOR_UUT_TAG)
+		SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_NO_F_SPI);
+	else
+		/* Set pinmux first */
+		sspi_flash_pinmux(1);
+
+	/* Get size of image automatically */
+	if (sz_image == 0)
+		sz_image = sspi_flash_get_image_used(image_base);
+
+	/* Clear status reg of spi flash for protection */
+	if (sspi_flash_physical_clear_stsreg()) {
+		/* Start to erase */
+		sspi_flash_physical_erase(spi_offset, sz_image);
+		/* Start to write */
+		if (image_base != NULL)
+			sspi_flash_physical_write(spi_offset, sz_image,
+						  image_base);
+		/* Verify data */
+		if (sspi_flash_verify(spi_offset, sz_image, image_base))
+			*flag_upload |= 0x02;
+	}
+	if (uut_tag != NPCX_MONITOR_UUT_TAG)
+		/* Disable pinmux */
+		sspi_flash_pinmux(0);
+
+	/* Mark we have finished upload work */
+	*flag_upload |= 0x01;
+
+	/* Return the status back to ROM code is required for UUT */
+	if (uut_tag == NPCX_MONITOR_UUT_TAG)
+		return *flag_upload;
+
+	/* Infinite loop */
+	for (;;)
+		;
+}
diff --git a/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.h b/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.h
new file mode 100644
index 0000000000..80e605eea0
--- /dev/null
+++ b/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.h
@@ -0,0 +1,33 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#ifndef __CROS_EC_NPCX_MONITOR_H
+#define __CROS_EC_NPCX_MONITOR_H
+
+#include <stdint.h>
+
+#define NPCX_MONITOR_UUT_TAG 0xA5075001
+#define NPCX_MONITOR_HEADER_ADDR 0x200C3000
+
+/* Flag to record the progress of programming SPI flash */
+#define SPI_PROGRAMMING_FLAG 0x200C4000
+
+struct monitor_header_tag {
+	/* offset 0x00: TAG NPCX_MONITOR_TAG */
+	uint32_t tag;
+	/* offset 0x04: Size of the binary being programmed (in bytes) */
+	uint32_t size;
+	/* offset 0x08: The RAM address of the binary to program into the SPI */
+	uint32_t src_addr;
+	/* offset 0x0C: The Flash address to be programmed (Absolute address) */
+	uint32_t dest_addr;
+	/* offset 0x10: Maximum allowable flash clock frequency */
+	uint8_t max_clock;
+	/* offset 0x11: SPI Flash read mode */
+	uint8_t read_mode;
+	/* offset 0x12: Reserved */
+	uint16_t reserved;
+} __packed;
+
+#endif /* __CROS_EC_NPCX_MONITOR_H */
diff --git a/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.ld b/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.ld
new file mode 100644
index 0000000000..98892babc6
--- /dev/null
+++ b/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.ld
@@ -0,0 +1,52 @@
+/* Copyright 2017 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * NPCX SoC spi flash update tool
+ */
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+    CODERAM (rx) : ORIGIN = 0x200C3020, LENGTH = 0xFE0
+}
+
+/*
+ * The entry point is informative, for debuggers and simulators,
+ * since the Cortex-M vector points to it anyway.
+ */
+ENTRY(sspi_flash_upload)
+
+
+/* Sections Definitions */
+
+SECTIONS
+{
+    .startup_text :
+    {
+        . = ALIGN(4);
+        *(.startup_text )	/* Startup code */
+        . = ALIGN(4);
+    } >CODERAM
+
+    /*
+     * The program code is stored in the .text section,
+     * which goes to CODERAM.
+     */
+    .text :
+    {
+        . = ALIGN(4);
+        *(.text .text.*)			/* all remaining code */
+        *(.rodata .rodata.*)		/* read-only data (constants) */
+    } >CODERAM
+
+    . = ALIGN(4);
+    _etext = .;
+
+    /*
+     * This address is used by the startup code to
+     * initialise the .data section.
+     */
+    _sidata = _etext;
+
+}
diff --git a/zephyr/shim/chip/npcx/npcx_monitor/registers.h b/zephyr/shim/chip/npcx/npcx_monitor/registers.h
new file mode 100644
index 0000000000..85ab3b2389
--- /dev/null
+++ b/zephyr/shim/chip/npcx/npcx_monitor/registers.h
@@ -0,0 +1,360 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Register map for NPCX processor
+ *
+ * This is meant to be temporary until the NPCX monitor support is moved
+ * to Zephyr upstream
+ */
+
+#ifndef __CROS_EC_REGISTERS_H
+#define __CROS_EC_REGISTERS_H
+
+/*
+ * The monitor code doesn't build cleanly under the Zephyr environment if
+ * include/common.h is included. Replicate the register access macros until
+ * this code is moved upstream.
+ */
+
+/* Macros to access registers */
+#define REG64_ADDR(addr) ((volatile uint64_t *)(addr))
+#define REG32_ADDR(addr) ((volatile uint32_t *)(addr))
+#define REG16_ADDR(addr) ((volatile uint16_t *)(addr))
+#define REG8_ADDR(addr) ((volatile uint8_t *)(addr))
+
+#define REG64(addr) (*REG64_ADDR(addr))
+#define REG32(addr) (*REG32_ADDR(addr))
+#define REG16(addr) (*REG16_ADDR(addr))
+#define REG8(addr) (*REG8_ADDR(addr))
+
+/* Standard macros / definitions */
+#define GENERIC_MAX(x, y) ((x) > (y) ? (x) : (y))
+#define GENERIC_MIN(x, y) ((x) < (y) ? (x) : (y))
+#ifndef MAX
+#define MAX(a, b)                            \
+	({                                   \
+		__typeof__(a) temp_a = (a);  \
+		__typeof__(b) temp_b = (b);  \
+                                             \
+		GENERIC_MAX(temp_a, temp_b); \
+	})
+#endif
+#ifndef MIN
+#define MIN(a, b)                            \
+	({                                   \
+		__typeof__(a) temp_a = (a);  \
+		__typeof__(b) temp_b = (b);  \
+                                             \
+		GENERIC_MIN(temp_a, temp_b); \
+	})
+#endif
+#ifndef NULL
+#define NULL ((void *)0)
+#endif
+
+/******************************************************************************/
+/*
+ * Macro Functions
+ */
+/* Bit functions */
+#define SET_BIT(reg, bit) ((reg) |= (0x1 << (bit)))
+#define CLEAR_BIT(reg, bit) ((reg) &= (~(0x1 << (bit))))
+#define IS_BIT_SET(reg, bit) (((reg) >> (bit)) & (0x1))
+#define UPDATE_BIT(reg, bit, cond)           \
+	{                                    \
+		if (cond)                    \
+			SET_BIT(reg, bit);   \
+		else                         \
+			CLEAR_BIT(reg, bit); \
+	}
+/* Field functions */
+#define GET_POS_FIELD(pos, size) pos
+#define GET_SIZE_FIELD(pos, size) size
+#define FIELD_POS(field) GET_POS_##field
+#define FIELD_SIZE(field) GET_SIZE_##field
+/* Read field functions */
+#define GET_FIELD(reg, field) \
+	_GET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field))
+#define _GET_FIELD_(reg, f_pos, f_size) \
+	(((reg) >> (f_pos)) & ((1 << (f_size)) - 1))
+/* Write field functions */
+#define SET_FIELD(reg, field, value) \
+	_SET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field), value)
+#define _SET_FIELD_(reg, f_pos, f_size, value)                     \
+	((reg) = ((reg) & (~(((1 << (f_size)) - 1) << (f_pos)))) | \
+		 ((value) << (f_pos)))
+
+/* NPCX7 & NPCX9 */
+#define NPCX_DEVALT(n) REG8(NPCX_SCFG_BASE_ADDR + 0x010 + (n))
+
+/******************************************************************************/
+/*
+ * NPCX (Nuvoton M4 EC) Register Definitions
+ */
+
+/* Modules Map */
+#define NPCX_ESPI_BASE_ADDR 0x4000A000
+#define NPCX_MDC_BASE_ADDR 0x4000C000
+#define NPCX_PMC_BASE_ADDR 0x4000D000
+#define NPCX_SIB_BASE_ADDR 0x4000E000
+#define NPCX_SHI_BASE_ADDR 0x4000F000
+#define NPCX_SHM_BASE_ADDR 0x40010000
+#define NPCX_GDMA_BASE_ADDR 0x40011000
+#define NPCX_FIU_BASE_ADDR 0x40020000
+#define NPCX_KBSCAN_REGS_BASE 0x400A3000
+#define NPCX_WOV_BASE_ADDR 0x400A4000
+#define NPCX_APM_BASE_ADDR 0x400A4800
+#define NPCX_GLUE_REGS_BASE 0x400A5000
+#define NPCX_BBRAM_BASE_ADDR 0x400AF000
+#define NPCX_PS2_BASE_ADDR 0x400B1000
+#define NPCX_HFCG_BASE_ADDR 0x400B5000
+#define NPCX_LFCG_BASE_ADDR 0x400B5100
+#define NPCX_FMUL2_BASE_ADDR 0x400B5200
+#define NPCX_MTC_BASE_ADDR 0x400B7000
+#define NPCX_MSWC_BASE_ADDR 0x400C1000
+#define NPCX_SCFG_BASE_ADDR 0x400C3000
+#define NPCX_KBC_BASE_ADDR 0x400C7000
+#define NPCX_ADC_BASE_ADDR 0x400D1000
+#define NPCX_SPI_BASE_ADDR 0x400D2000
+#define NPCX_PECI_BASE_ADDR 0x400D4000
+#define NPCX_TWD_BASE_ADDR 0x400D8000
+
+/* Multi-Modules Map */
+#define NPCX_PWM_BASE_ADDR(mdl) (0x40080000 + ((mdl)*0x2000L))
+#define NPCX_GPIO_BASE_ADDR(mdl) (0x40081000 + ((mdl)*0x2000L))
+#define NPCX_ITIM_BASE_ADDR(mdl) (0x400B0000 + ((mdl)*0x2000L))
+#define NPCX_MIWU_BASE_ADDR(mdl) (0x400BB000 + ((mdl)*0x2000L))
+#define NPCX_MFT_BASE_ADDR(mdl) (0x400E1000 + ((mdl)*0x2000L))
+#define NPCX_PM_CH_BASE_ADDR(mdl) (0x400C9000 + ((mdl)*0x2000L))
+
+/******************************************************************************/
+/* System Configuration (SCFG) Registers */
+#define NPCX_DEVCNT REG8(NPCX_SCFG_BASE_ADDR + 0x000)
+#define NPCX_STRPST REG8(NPCX_SCFG_BASE_ADDR + 0x001)
+#define NPCX_RSTCTL REG8(NPCX_SCFG_BASE_ADDR + 0x002)
+#define NPCX_DEV_CTL4 REG8(NPCX_SCFG_BASE_ADDR + 0x006)
+#define NPCX_LFCGCALCNT REG8(NPCX_SCFG_BASE_ADDR + 0x021)
+#define NPCX_PUPD_EN0 REG8(NPCX_SCFG_BASE_ADDR + 0x028)
+#define NPCX_PUPD_EN1 REG8(NPCX_SCFG_BASE_ADDR + 0x029)
+#define NPCX_SCFG_VER REG8(NPCX_SCFG_BASE_ADDR + 0x02F)
+
+#define TEST_BKSL REG8(NPCX_SCFG_BASE_ADDR + 0x037)
+#define TEST0 REG8(NPCX_SCFG_BASE_ADDR + 0x038)
+#define BLKSEL 0
+
+/* SCFG register fields */
+#define NPCX_DEVCNT_F_SPI_TRIS 6
+#define NPCX_DEVCNT_HIF_TYP_SEL_FIELD FIELD(2, 2)
+#define NPCX_DEVCNT_JEN1_HEN 5
+#define NPCX_DEVCNT_JEN0_HEN 4
+#define NPCX_STRPST_TRIST 1
+#define NPCX_STRPST_TEST 2
+#define NPCX_STRPST_JEN1 4
+#define NPCX_STRPST_JEN0 5
+#define NPCX_STRPST_SPI_COMP 7
+#define NPCX_RSTCTL_VCC1_RST_STS 0
+#define NPCX_RSTCTL_DBGRST_STS 1
+#define NPCX_RSTCTL_VCC1_RST_SCRATCH 3
+#define NPCX_RSTCTL_LRESET_PLTRST_MODE 5
+#define NPCX_RSTCTL_HIPRST_MODE 6
+#define NPCX_DEV_CTL4_F_SPI_SLLK 2
+#define NPCX_DEV_CTL4_SPI_SP_SEL 4
+#define NPCX_DEV_CTL4_WP_IF 5
+#define NPCX_DEV_CTL4_VCC1_RST_LK 6
+#define NPCX_DEVPU0_I2C0_0_PUE 0
+#define NPCX_DEVPU0_I2C0_1_PUE 1
+#define NPCX_DEVPU0_I2C1_0_PUE 2
+#define NPCX_DEVPU0_I2C2_0_PUE 4
+#define NPCX_DEVPU0_I2C3_0_PUE 6
+#define NPCX_DEVPU1_F_SPI_PUD_EN 7
+
+/* DEVALT */
+/* pin-mux for SPI/FIU */
+#define NPCX_DEVALT0_SPIP_SL 0
+#define NPCX_DEVALT0_GPIO_NO_SPIP 3
+#define NPCX_DEVALT0_F_SPI_CS1_2 4
+#define NPCX_DEVALT0_F_SPI_CS1_1 5
+#define NPCX_DEVALT0_F_SPI_QUAD 6
+#define NPCX_DEVALT0_NO_F_SPI 7
+
+/******************************************************************************/
+/* Flash Interface Unit (FIU) Registers */
+#define NPCX_FIU_CFG REG8(NPCX_FIU_BASE_ADDR + 0x000)
+#define NPCX_BURST_CFG REG8(NPCX_FIU_BASE_ADDR + 0x001)
+#define NPCX_RESP_CFG REG8(NPCX_FIU_BASE_ADDR + 0x002)
+#define NPCX_SPI_FL_CFG REG8(NPCX_FIU_BASE_ADDR + 0x014)
+#define NPCX_UMA_CODE REG8(NPCX_FIU_BASE_ADDR + 0x016)
+#define NPCX_UMA_AB0 REG8(NPCX_FIU_BASE_ADDR + 0x017)
+#define NPCX_UMA_AB1 REG8(NPCX_FIU_BASE_ADDR + 0x018)
+#define NPCX_UMA_AB2 REG8(NPCX_FIU_BASE_ADDR + 0x019)
+#define NPCX_UMA_DB0 REG8(NPCX_FIU_BASE_ADDR + 0x01A)
+#define NPCX_UMA_DB1 REG8(NPCX_FIU_BASE_ADDR + 0x01B)
+#define NPCX_UMA_DB2 REG8(NPCX_FIU_BASE_ADDR + 0x01C)
+#define NPCX_UMA_DB3 REG8(NPCX_FIU_BASE_ADDR + 0x01D)
+#define NPCX_UMA_CTS REG8(NPCX_FIU_BASE_ADDR + 0x01E)
+#define NPCX_UMA_ECTS REG8(NPCX_FIU_BASE_ADDR + 0x01F)
+#define NPCX_UMA_DB0_3 REG32(NPCX_FIU_BASE_ADDR + 0x020)
+#define NPCX_FIU_RD_CMD REG8(NPCX_FIU_BASE_ADDR + 0x030)
+#define NPCX_FIU_DMM_CYC REG8(NPCX_FIU_BASE_ADDR + 0x032)
+#define NPCX_FIU_EXT_CFG REG8(NPCX_FIU_BASE_ADDR + 0x033)
+#define NPCX_FIU_UMA_AB0_3 REG32(NPCX_FIU_BASE_ADDR + 0x034)
+
+/* FIU register fields */
+#define NPCX_RESP_CFG_IAD_EN 0
+#define NPCX_RESP_CFG_DEV_SIZE_EX 2
+#define NPCX_UMA_CTS_A_SIZE 3
+#define NPCX_UMA_CTS_C_SIZE 4
+#define NPCX_UMA_CTS_RD_WR 5
+#define NPCX_UMA_CTS_DEV_NUM 6
+#define NPCX_UMA_CTS_EXEC_DONE 7
+#define NPCX_UMA_ECTS_SW_CS0 0
+#define NPCX_UMA_ECTS_SW_CS1 1
+#define NPCX_UMA_ECTS_SEC_CS 2
+#define NPCX_UMA_ECTS_UMA_LOCK 3
+
+/******************************************************************************/
+/* KBC Registers */
+#define NPCX_HICTRL REG8(NPCX_KBC_BASE_ADDR + 0x000)
+#define NPCX_HIIRQC REG8(NPCX_KBC_BASE_ADDR + 0x002)
+#define NPCX_HIKMST REG8(NPCX_KBC_BASE_ADDR + 0x004)
+#define NPCX_HIKDO REG8(NPCX_KBC_BASE_ADDR + 0x006)
+#define NPCX_HIMDO REG8(NPCX_KBC_BASE_ADDR + 0x008)
+#define NPCX_KBCVER REG8(NPCX_KBC_BASE_ADDR + 0x009)
+#define NPCX_HIKMDI REG8(NPCX_KBC_BASE_ADDR + 0x00A)
+#define NPCX_SHIKMDI REG8(NPCX_KBC_BASE_ADDR + 0x00B)
+
+/* KBC register field */
+#define NPCX_HICTRL_OBFKIE 0 /* Automatic Serial IRQ1 for KBC */
+#define NPCX_HICTRL_OBFMIE 1 /* Automatic Serial IRQ12 for Mouse*/
+#define NPCX_HICTRL_OBECIE 2 /* KBC OBE interrupt enable */
+#define NPCX_HICTRL_IBFCIE 3 /* KBC IBF interrupt enable */
+#define NPCX_HICTRL_PMIHIE 4 /* Automatic Serial IRQ11 for PMC1 */
+#define NPCX_HICTRL_PMIOCIE 5 /* PMC1 OBE interrupt enable */
+#define NPCX_HICTRL_PMICIE 6 /* PMC1 IBF interrupt enable */
+#define NPCX_HICTRL_FW_OBF 7 /* Firmware control over OBF */
+
+#define NPCX_HIKMST_OBF 0 /* KB output buffer is full */
+
+/******************************************************************************/
+/* Timer Watch Dog (TWD) Registers */
+#define NPCX_TWCFG REG8(NPCX_TWD_BASE_ADDR + 0x000)
+#define NPCX_TWCP REG8(NPCX_TWD_BASE_ADDR + 0x002)
+#define NPCX_TWDT0 REG16(NPCX_TWD_BASE_ADDR + 0x004)
+#define NPCX_T0CSR REG8(NPCX_TWD_BASE_ADDR + 0x006)
+#define NPCX_WDCNT REG8(NPCX_TWD_BASE_ADDR + 0x008)
+#define NPCX_WDSDM REG8(NPCX_TWD_BASE_ADDR + 0x00A)
+#define NPCX_TWMT0 REG16(NPCX_TWD_BASE_ADDR + 0x00C)
+#define NPCX_TWMWD REG8(NPCX_TWD_BASE_ADDR + 0x00E)
+#define NPCX_WDCP REG8(NPCX_TWD_BASE_ADDR + 0x010)
+
+/* TWD register fields */
+#define NPCX_TWCFG_LTWCFG 0
+#define NPCX_TWCFG_LTWCP 1
+#define NPCX_TWCFG_LTWDT0 2
+#define NPCX_TWCFG_LWDCNT 3
+#define NPCX_TWCFG_WDCT0I 4
+#define NPCX_TWCFG_WDSDME 5
+#define NPCX_TWCFG_WDRST_MODE 6
+#define NPCX_TWCFG_WDC2POR 7
+#define NPCX_T0CSR_RST 0
+#define NPCX_T0CSR_TC 1
+#define NPCX_T0CSR_WDLTD 3
+#define NPCX_T0CSR_WDRST_STS 4
+#define NPCX_T0CSR_WD_RUN 5
+#define NPCX_T0CSR_TESDIS 7
+
+/******************************************************************************/
+/* SPI Register */
+#define NPCX_SPI_DATA REG16(NPCX_SPI_BASE_ADDR + 0x00)
+#define NPCX_SPI_CTL1 REG16(NPCX_SPI_BASE_ADDR + 0x02)
+#define NPCX_SPI_STAT REG8(NPCX_SPI_BASE_ADDR + 0x04)
+
+/* SPI register fields */
+#define NPCX_SPI_CTL1_SPIEN 0
+#define NPCX_SPI_CTL1_SNM 1
+#define NPCX_SPI_CTL1_MOD 2
+#define NPCX_SPI_CTL1_EIR 5
+#define NPCX_SPI_CTL1_EIW 6
+#define NPCX_SPI_CTL1_SCM 7
+#define NPCX_SPI_CTL1_SCIDL 8
+#define NPCX_SPI_CTL1_SCDV 9
+#define NPCX_SPI_STAT_BSY 0
+#define NPCX_SPI_STAT_RBF 1
+
+/******************************************************************************/
+/* Flash Utiltiy definition */
+/*
+ *  Flash commands for the W25Q16CV SPI flash
+ */
+#define CMD_READ_ID 0x9F
+#define CMD_READ_MAN_DEV_ID 0x90
+#define CMD_WRITE_EN 0x06
+#define CMD_WRITE_STATUS 0x50
+#define CMD_READ_STATUS_REG 0x05
+#define CMD_READ_STATUS_REG2 0x35
+#define CMD_WRITE_STATUS_REG 0x01
+#define CMD_FLASH_PROGRAM 0x02
+#define CMD_SECTOR_ERASE 0x20
+#define CMD_BLOCK_32K_ERASE 0x52
+#define CMD_BLOCK_64K_ERASE 0xd8
+#define CMD_PROGRAM_UINT_SIZE 0x08
+#define CMD_PAGE_SIZE 0x00
+#define CMD_READ_ID_TYPE 0x47
+#define CMD_FAST_READ 0x0B
+
+/*
+ * Status registers for the W25Q16CV SPI flash
+ */
+#define SPI_FLASH_SR2_SUS BIT(7)
+#define SPI_FLASH_SR2_CMP BIT(6)
+#define SPI_FLASH_SR2_LB3 BIT(5)
+#define SPI_FLASH_SR2_LB2 BIT(4)
+#define SPI_FLASH_SR2_LB1 BIT(3)
+#define SPI_FLASH_SR2_QE BIT(1)
+#define SPI_FLASH_SR2_SRP1 BIT(0)
+#define SPI_FLASH_SR1_SRP0 BIT(7)
+#define SPI_FLASH_SR1_SEC BIT(6)
+#define SPI_FLASH_SR1_TB BIT(5)
+#define SPI_FLASH_SR1_BP2 BIT(4)
+#define SPI_FLASH_SR1_BP1 BIT(3)
+#define SPI_FLASH_SR1_BP0 BIT(2)
+#define SPI_FLASH_SR1_WEL BIT(1)
+#define SPI_FLASH_SR1_BUSY BIT(0)
+
+/* 0: F_CS0 1: F_CS1_1(GPIO86) 2:F_CS1_2(GPIOA6) */
+#define FIU_CHIP_SELECT 0
+/* Create UMA control mask */
+#define MASK(bit) (0x1 << (bit))
+#define A_SIZE 0x03 /* 0: No ADR field 1: 3-bytes ADR field */
+#define C_SIZE 0x04 /* 0: 1-Byte CMD field 1:No CMD field */
+#define RD_WR 0x05 /* 0: Read 1: Write */
+#define DEV_NUM 0x06 /* 0: PVT is used 1: SHD is used */
+#define EXEC_DONE 0x07
+#define D_SIZE_1 0x01
+#define D_SIZE_2 0x02
+#define D_SIZE_3 0x03
+#define D_SIZE_4 0x04
+#define FLASH_SEL MASK(DEV_NUM)
+
+#define MASK_CMD_ONLY (MASK(EXEC_DONE) | FLASH_SEL)
+#define MASK_CMD_ADR (MASK(EXEC_DONE) | FLASH_SEL | MASK(A_SIZE))
+#define MASK_CMD_ADR_WR \
+	(MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) | MASK(A_SIZE) | D_SIZE_1)
+#define MASK_RD_1BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_1)
+#define MASK_RD_2BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_2)
+#define MASK_RD_3BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_3)
+#define MASK_RD_4BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_4)
+#define MASK_CMD_RD_1BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_1)
+#define MASK_CMD_RD_2BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_2)
+#define MASK_CMD_RD_3BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_3)
+#define MASK_CMD_RD_4BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_4)
+#define MASK_CMD_WR_ONLY (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR))
+#define MASK_CMD_WR_1BYTE \
+	(MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) | MASK(C_SIZE) | D_SIZE_1)
+#define MASK_CMD_WR_2BYTE \
+	(MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) | MASK(C_SIZE) | D_SIZE_2)
+#define MASK_CMD_WR_ADR \
+	(MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) | MASK(A_SIZE))
+
+#endif /* __CROS_EC_REGISTERS_H */
diff --git a/zephyr/shim/chip/npcx/power_policy.c b/zephyr/shim/chip/npcx/power_policy.c
new file mode 100644
index 0000000000..29ebcbd542
--- /dev/null
+++ b/zephyr/shim/chip/npcx/power_policy.c
@@ -0,0 +1,43 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "cros_version.h"
+#include "system.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/pm/pm.h>
+#include <zephyr/pm/policy.h>
+
+#include <soc.h>
+
+static const struct pm_state_info residency_info[] =
+	PM_STATE_INFO_LIST_FROM_DT_CPU(DT_NODELABEL(cpu0));
+
+/* CROS PM policy handler */
+const struct pm_state_info *pm_policy_next_state(uint8_t cpu, int32_t ticks)
+{
+	ARG_UNUSED(cpu);
+
+	if (DEEP_SLEEP_ALLOWED) {
+		for (int i = ARRAY_SIZE(residency_info) - 1; i >= 0; i--) {
+			if (pm_policy_state_lock_is_active(
+				    residency_info[i].state,
+				    PM_ALL_SUBSTATES)) {
+				continue;
+			}
+
+			/* Find suitable power state by residency time */
+			if (ticks == K_TICKS_FOREVER ||
+			    ticks >= k_us_to_ticks_ceil32(
+					     residency_info[i]
+						     .min_residency_us)) {
+				return &residency_info[i];
+			}
+		}
+	}
+
+	return NULL;
+}
diff --git a/zephyr/shim/chip/npcx/shi.c b/zephyr/shim/chip/npcx/shi.c
new file mode 100644
index 0000000000..4e0535b91f
--- /dev/null
+++ b/zephyr/shim/chip/npcx/shi.c
@@ -0,0 +1,118 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Functions needed by Serial Host Interface module for Chrome EC */
+
+#include "chipset.h"
+#include "drivers/cros_shi.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "system.h"
+
+#include <zephyr/device.h>
+#include <zephyr/dt-bindings/clock/npcx_clock.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+
+#include <ap_power/ap_power.h>
+#include <soc.h>
+
+LOG_MODULE_REGISTER(shim_cros_shi, LOG_LEVEL_DBG);
+
+#define SHI_NODE DT_NODELABEL(shi0)
+
+static void shi_enable(void)
+{
+	const struct device *cros_shi_dev = DEVICE_DT_GET(SHI_NODE);
+
+	if (!device_is_ready(cros_shi_dev)) {
+		LOG_ERR("Error: device %s is not ready", cros_shi_dev->name);
+		return;
+	}
+
+	LOG_INF("%s", __func__);
+	cros_shi_enable(cros_shi_dev);
+}
+
+static void shi_disable(void)
+{
+	const struct device *cros_shi_dev = DEVICE_DT_GET(SHI_NODE);
+
+	if (!device_is_ready(cros_shi_dev)) {
+		LOG_ERR("Error: device %s is not ready", cros_shi_dev->name);
+		return;
+	}
+
+	LOG_INF("%s", __func__);
+	cros_shi_disable(cros_shi_dev);
+}
+DECLARE_HOOK(HOOK_SYSJUMP, shi_disable, HOOK_PRIO_DEFAULT);
+
+static void shi_power_change(struct ap_power_ev_callback *cb,
+			     struct ap_power_ev_data data)
+{
+	switch (data.event) {
+	default:
+		return;
+
+#if CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK
+	case AP_POWER_RESUME_INIT:
+		shi_enable();
+		break;
+
+	case AP_POWER_SUSPEND_COMPLETE:
+		shi_disable();
+		break;
+#else
+	case AP_POWER_RESUME:
+		shi_enable();
+		break;
+
+	case AP_POWER_SUSPEND:
+		shi_disable();
+		break;
+#endif
+	}
+}
+
+static void shi_init(void)
+{
+	static struct ap_power_ev_callback cb;
+
+	ap_power_ev_init_callback(&cb, shi_power_change,
+#if CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK
+				  AP_POWER_RESUME_INIT |
+					  AP_POWER_SUSPEND_COMPLETE
+#else
+				  AP_POWER_RESUME | AP_POWER_SUSPEND
+#endif
+	);
+	ap_power_ev_add_callback(&cb);
+
+	if (IS_ENABLED(CONFIG_CROS_SHI_NPCX_DEBUG) ||
+	    (system_jumped_late() && chipset_in_state(CHIPSET_STATE_ON))) {
+		shi_enable();
+	}
+}
+/* Call hook after chipset sets initial power state */
+DECLARE_HOOK(HOOK_INIT, shi_init, HOOK_PRIO_POST_CHIPSET);
+
+/* Get protocol information */
+static enum ec_status shi_get_protocol_info(struct host_cmd_handler_args *args)
+{
+	struct ec_response_get_protocol_info *r = args->response;
+
+	memset(r, '\0', sizeof(*r));
+	r->protocol_versions = BIT(3);
+	r->max_request_packet_size = CONFIG_CROS_SHI_MAX_REQUEST;
+	r->max_response_packet_size = CONFIG_CROS_SHI_MAX_RESPONSE;
+	r->flags = EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED;
+
+	args->response_size = sizeof(*r);
+
+	return EC_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, shi_get_protocol_info,
+		     EC_VER_MASK(0));
diff --git a/zephyr/shim/chip/npcx/system.c b/zephyr/shim/chip/npcx/system.c
new file mode 100644
index 0000000000..5c16d3bd40
--- /dev/null
+++ b/zephyr/shim/chip/npcx/system.c
@@ -0,0 +1,95 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "system.h"
+#include "system_chip.h"
+
+#include <zephyr/drivers/bbram.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(shim_npcx_system, LOG_LEVEL_ERR);
+
+static void chip_bbram_status_check(void)
+{
+	const struct device *bbram_dev;
+	int res;
+
+	bbram_dev = DEVICE_DT_GET(DT_NODELABEL(bbram));
+	if (!device_is_ready(bbram_dev)) {
+		LOG_ERR("Error: device %s is not ready", bbram_dev->name);
+		return;
+	}
+
+	res = bbram_check_invalid(bbram_dev);
+	if (res != 0 && res != -ENOTSUP)
+		LOG_INF("VBAT power drop!");
+
+	res = bbram_check_standby_power(bbram_dev);
+	if (res != 0 && res != -ENOTSUP)
+		LOG_INF("VSBY power drop!");
+
+	res = bbram_check_power(bbram_dev);
+	if (res != 0 && res != -ENOTSUP)
+		LOG_INF("VCC1 power drop!");
+}
+
+/*
+ * Configure address 0x40001600 (Low Power RAM) in the the MPU
+ * (Memory Protection Unit) as a "regular" memory
+ */
+void system_mpu_config(void)
+{
+	if (!IS_ENABLED(CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API))
+		return;
+
+	/*
+	 * npcx9 Rev.1 has the problem for download_from_flash API.
+	 * Workaround it by implementing the system_download_from_flash function
+	 * in the suspend RAM. The functions will do the same, but will provide
+	 * a software solution similar to what's done in the npcx5.
+	 */
+	/* Enable MPU */
+	CPU_MPU_CTRL = 0x7;
+
+	/* Create a new MPU Region to allow execution from low-power ram */
+	CPU_MPU_RNR = REGION_CHIP_RESERVED;
+	CPU_MPU_RASR = CPU_MPU_RASR & 0xFFFFFFFE; /* Disable region */
+	CPU_MPU_RBAR = CONFIG_LPRAM_BASE; /* Set region base address */
+	/*
+	 * Set region size & attribute and enable region
+	 * [31:29] - Reserved.
+	 * [28]    - XN (Execute Never) = 0
+	 * [27]    - Reserved.
+	 * [26:24] - AP                 = 011 (Full access)
+	 * [23:22] - Reserved.
+	 * [21:19,18,17,16] - TEX,S,C,B = 001000 (Normal memory)
+	 * [15:8]  - SRD                = 0 (Subregions enabled)
+	 * [7:6]   - Reserved.
+	 * [5:1]   - SIZE               = 01001 (1K)
+	 * [0]     - ENABLE             = 1 (enabled)
+	 */
+	CPU_MPU_RASR = 0x03080013;
+}
+
+static int chip_system_init(void)
+{
+	/*
+	 * Check BBRAM power status.
+	 */
+	chip_bbram_status_check();
+
+	system_mpu_config();
+
+	return 0;
+}
+/*
+ * The priority should be lower than CROS_BBRAM_NPCX_INIT_PRIORITY.
+ */
+#if (CONFIG_CROS_SYSTEM_NPCX_PRE_INIT_PRIORITY <= CONFIG_BBRAM_INIT_PRIORITY)
+#error CONFIG_CROS_SYSTEM_NPCX_PRE_INIT_PRIORITY must greater than \
+	CONFIG_BBRAM_INIT_PRIORITY
+#endif
+SYS_INIT(chip_system_init, PRE_KERNEL_1,
+	 CONFIG_CROS_SYSTEM_NPCX_PRE_INIT_PRIORITY);
diff --git a/zephyr/shim/chip/npcx/system_download_from_flash.c b/zephyr/shim/chip/npcx/system_download_from_flash.c
new file mode 100644
index 0000000000..53e22d4839
--- /dev/null
+++ b/zephyr/shim/chip/npcx/system_download_from_flash.c
@@ -0,0 +1,160 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "common.h"
+#include "soc.h"
+#include "system_chip.h"
+
+#include <zephyr/dt-bindings/clock/npcx_clock.h>
+#include <zephyr/sys/__assert.h>
+
+#include <stdnoreturn.h>
+
+/* Modules Map */
+#define NPCX_PMC_BASE_ADDR 0x4000D000
+#define NPCX_GDMA_BASE_ADDR 0x40011000
+
+/******************************************************************************/
+/* GDMA (General DMA) Registers */
+#define NPCX_GDMA_CTL REG32(NPCX_GDMA_BASE_ADDR + 0x000)
+#define NPCX_GDMA_SRCB REG32(NPCX_GDMA_BASE_ADDR + 0x004)
+#define NPCX_GDMA_DSTB REG32(NPCX_GDMA_BASE_ADDR + 0x008)
+#define NPCX_GDMA_TCNT REG32(NPCX_GDMA_BASE_ADDR + 0x00C)
+
+/******************************************************************************/
+/* GDMA register fields */
+#define NPCX_GDMA_CTL_GDMAEN 0
+#define NPCX_GDMA_CTL_GDMAMS FIELD(2, 2)
+#define NPCX_GDMA_CTL_DADIR 4
+#define NPCX_GDMA_CTL_SADIR 5
+#define NPCX_GDMA_CTL_SAFIX 7
+#define NPCX_GDMA_CTL_SIEN 8
+#define NPCX_GDMA_CTL_BME 9
+#define NPCX_GDMA_CTL_SBMS 11
+#define NPCX_GDMA_CTL_TWS FIELD(12, 2)
+#define NPCX_GDMA_CTL_DM 15
+#define NPCX_GDMA_CTL_SOFTREQ 16
+#define NPCX_GDMA_CTL_TC 18
+#define NPCX_GDMA_CTL_GDMAERR 20
+#define NPCX_GDMA_CTL_BLOCK_BUG_CORRECTION_DISABLE 26
+
+/******************************************************************************/
+/* Low Power RAM definitions */
+#define NPCX_LPRAM_CTRL REG32(0x40001044)
+
+/******************************************************************************/
+/* Sysjump utilities in low power ram for npcx series. */
+noreturn void __keep __attribute__((section(".lowpower_ram2")))
+__start_gdma(uint32_t exeAddr)
+{
+	/* Enable GDMA now */
+	SET_BIT(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAEN);
+
+	/* Start GDMA */
+	SET_BIT(NPCX_GDMA_CTL, NPCX_GDMA_CTL_SOFTREQ);
+
+	/* Wait for transfer to complete/fail */
+	while (!IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_TC) &&
+	       !IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAERR))
+		;
+
+	/* Disable GDMA now */
+	CLEAR_BIT(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAEN);
+
+	/*
+	 * Failure occurs during GMDA transaction. Let watchdog issue and
+	 * boot from RO region again.
+	 */
+	if (IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAERR))
+		while (1)
+			;
+
+	/*
+	 * Jump to the exeAddr address if needed. Setting bit 0 of address to
+	 * indicate it's a thumb branch for cortex-m series CPU.
+	 */
+	((void (*)(void))(exeAddr | 0x01))();
+
+	/* Should never get here */
+	while (1)
+		;
+}
+
+/* Begin address of Suspend RAM for little FW (GDMA utilities). */
+#define LFW_OFFSET 0x160
+uintptr_t __lpram_lfw_start = CONFIG_LPRAM_BASE + LFW_OFFSET;
+
+void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr,
+				uint32_t size, uint32_t exeAddr)
+{
+	int i;
+	uint8_t chunkSize = 16; /* 4 data burst mode. ie.16 bytes */
+	/*
+	 * GDMA utility in Suspend RAM. Setting bit 0 of address to indicate
+	 * it's a thumb branch for cortex-m series CPU.
+	 */
+	void (*__start_gdma_in_lpram)(uint32_t) =
+		(void (*)(uint32_t))(__lpram_lfw_start | 0x01);
+
+	/*
+	 * Before enabling burst mode for better performance of GDMA, it's
+	 * important to make sure srcAddr, dstAddr and size of transactions
+	 * are 16 bytes aligned in case failure occurs.
+	 */
+	__ASSERT_NO_MSG((size % chunkSize) == 0 && (srcAddr % chunkSize) == 0 &&
+			(dstAddr % chunkSize) == 0);
+
+	/* Check valid address for jumpiing */
+	__ASSERT_NO_MSG(exeAddr != 0x0);
+
+	/* Enable power for the Low Power RAM */
+	CLEAR_BIT(NPCX_PWDWN_CTL(NPCX_PMC_BASE_ADDR, NPCX_PWDWN_CTL6), 6);
+
+	/* Enable Low Power RAM */
+	NPCX_LPRAM_CTRL = 1;
+
+	/*
+	 * Initialize GDMA for flash reading.
+	 * [31:21] - Reserved.
+	 * [20]    - GDMAERR   = 0  (Indicate GMDA transfer error)
+	 * [19]    - Reserved.
+	 * [18]    - TC        = 0  (Terminal Count. Indicate operation is end.)
+	 * [17]    - Reserved.
+	 * [16]    - SOFTREQ   = 0  (Don't trigger here)
+	 * [15]    - DM        = 0  (Set normal demand mode)
+	 * [14]    - Reserved.
+	 * [13:12] - TWS.      = 10 (One double-word for every GDMA transaction)
+	 * [11:10] - Reserved.
+	 * [9]     - BME       = 1  (4-data ie.16 bytes - Burst mode enable)
+	 * [8]     - SIEN      = 0  (Stop interrupt disable)
+	 * [7]     - SAFIX     = 0  (Fixed source address)
+	 * [6]     - Reserved.
+	 * [5]     - SADIR     = 0  (Source address incremented)
+	 * [4]     - DADIR     = 0  (Destination address incremented)
+	 * [3:2]   - GDMAMS    = 00 (Software mode)
+	 * [1]     - Reserved.
+	 * [0]     - ENABLE    = 0  (Don't enable yet)
+	 */
+	NPCX_GDMA_CTL = 0x00002200;
+
+	/* Set source base address */
+	NPCX_GDMA_SRCB = CONFIG_MAPPED_STORAGE_BASE + srcAddr;
+
+	/* Set destination base address */
+	NPCX_GDMA_DSTB = dstAddr;
+
+	/* Set number of transfers */
+	NPCX_GDMA_TCNT = (size / chunkSize);
+
+	/* Clear Transfer Complete event */
+	SET_BIT(NPCX_GDMA_CTL, NPCX_GDMA_CTL_TC);
+
+	/* Copy the __start_gdma_in_lpram instructions to LPRAM */
+	for (i = 0; i < &__flash_lplfw_end - &__flash_lplfw_start; i++)
+		*((uint32_t *)__lpram_lfw_start + i) =
+			*(&__flash_lplfw_start + i);
+
+	/* Start GDMA in Suspend RAM */
+	__start_gdma_in_lpram(exeAddr);
+}
diff --git a/zephyr/shim/chip/npcx/system_external_storage.c b/zephyr/shim/chip/npcx/system_external_storage.c
new file mode 100644
index 0000000000..d3b2d26362
--- /dev/null
+++ b/zephyr/shim/chip/npcx/system_external_storage.c
@@ -0,0 +1,189 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "clock_chip.h"
+#include "common.h"
+#include "rom_chip.h"
+#include "system.h"
+#include "system_chip.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/syscon.h>
+
+/* TODO (b:179900857) Make this implementation not npcx specific. */
+
+static const struct device *mdc_dev = DEVICE_DT_GET(DT_NODELABEL(mdc));
+
+/*
+ * b/218820985: The FWCTL register reset to 0xFF on multiple reads.
+ * Read the register once, and then cache all writes to this register
+ *
+ * TODO: if this is a chip bug, this should be managed by the syscon driver
+ * upstream.
+ */
+static uint32_t fwctrl_cached = 0xFFFFFFFF;
+
+#ifdef CONFIG_SOC_SERIES_NPCX7
+#define NPCX_FWCTRL 0x007
+#define NPCX_FWCTRL_RO_REGION 0
+#define NPCX_FWCTRL_FW_SLOT 1
+#elif defined(CONFIG_SOC_SERIES_NPCX9)
+#define NPCX_FWCTRL 0x009
+#define NPCX_FWCTRL_RO_REGION 6
+#define NPCX_FWCTRL_FW_SLOT 7
+#else
+#error "Unsupported NPCX SoC series."
+#endif
+
+static uint32_t read_fwctrl(void)
+{
+	/* On first entry, read the value and cache it. */
+	if (fwctrl_cached == 0xFFFFFFFF) {
+		syscon_read_reg(mdc_dev, NPCX_FWCTRL, &fwctrl_cached);
+	}
+
+	return fwctrl_cached;
+}
+
+static void write_fwctrl(uint32_t fwctrl)
+{
+	syscon_write_reg(mdc_dev, NPCX_FWCTRL, fwctrl);
+	fwctrl_cached = fwctrl;
+}
+
+void system_jump_to_booter(void)
+{
+	enum API_RETURN_STATUS_T status __attribute__((unused));
+	static uint32_t flash_offset;
+	static uint32_t flash_used;
+	static uint32_t addr_entry;
+
+	/*
+	 * Get memory offset and size for RO/RW regions.
+	 * Both of them need 16-bytes alignment since GDMA burst mode.
+	 */
+	switch (system_get_shrspi_image_copy()) {
+	case EC_IMAGE_RW:
+		flash_offset =
+			CONFIG_EC_WRITABLE_STORAGE_OFF + CONFIG_RW_STORAGE_OFF;
+		flash_used = CONFIG_RW_SIZE;
+		break;
+#ifdef CONFIG_RW_B
+	case EC_IMAGE_RW_B:
+		flash_offset = CONFIG_EC_WRITABLE_STORAGE_OFF +
+			       CONFIG_RW_B_STORAGE_OFF;
+		flash_used = CONFIG_RW_SIZE;
+		break;
+#endif
+	case EC_IMAGE_RO:
+	default: /* Jump to RO by default */
+		flash_offset =
+			CONFIG_EC_PROTECTED_STORAGE_OFF + CONFIG_RO_STORAGE_OFF;
+		flash_used = CONFIG_RO_SIZE;
+		break;
+	}
+
+	/* Make sure the reset vector is inside the destination image */
+	addr_entry =
+		*(uintptr_t *)(flash_offset + CONFIG_MAPPED_STORAGE_BASE + 4);
+
+	/*
+	 * Speed up FW download time by increasing clock freq of EC. It will
+	 * restore to default in clock_init() later.
+	 */
+	clock_turbo();
+
+	/*
+	 * npcx9 Rev.1 has the problem for download_from_flash API.
+	 * Workwaroud it by executing the system_download_from_flash function
+	 * in the suspend RAM like npcx5.
+	 * TODO: Removing npcx9 when Rev.2 is available.
+	 */
+	/* Bypass for GMDA issue of ROM api utilities */
+#if defined(CONFIG_SOC_SERIES_NPCX5) || \
+	defined(CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API)
+	system_download_from_flash(flash_offset, /* The offset of the data in
+						    spi flash */
+				   CONFIG_PROGRAM_MEMORY_BASE, /* RAM Addr of
+								  downloaded
+								  data */
+				   flash_used, /* Number of bytes to download */
+				   addr_entry /* jump to this address after
+						 download */
+	);
+#else
+	download_from_flash(flash_offset, /* The offset of the data in spi flash
+					   */
+			    CONFIG_PROGRAM_MEMORY_BASE, /* RAM Addr of
+							   downloaded data */
+			    flash_used, /* Number of bytes to download      */
+			    SIGN_NO_CHECK, /* Need CRC check or not */
+			    addr_entry, /* jump to this address after download
+					 */
+			    &status /* Status fo download */
+	);
+#endif
+}
+
+uint32_t system_get_lfw_address()
+{
+	/*
+	 * In A3 version, we don't use little FW anymore
+	 * We provide the alternative function in ROM
+	 */
+	uint32_t jump_addr = (uint32_t)system_jump_to_booter;
+	return jump_addr;
+}
+
+enum ec_image system_get_shrspi_image_copy(void)
+{
+	uint32_t fwctrl;
+
+	fwctrl = read_fwctrl();
+
+	if (IS_BIT_SET(fwctrl, NPCX_FWCTRL_RO_REGION)) {
+		/* RO image */
+#ifdef CHIP_HAS_RO_B
+		if (!IS_BIT_SET(fwctrl, NPCX_FWCTRL_FW_SLOT))
+			return EC_IMAGE_RO_B;
+#endif
+		return EC_IMAGE_RO;
+	} else {
+#ifdef CONFIG_RW_B
+		/* RW image */
+		if (!IS_BIT_SET(fwctrl, NPCX_FWCTRL_FW_SLOT))
+			/* Slot A */
+			return EC_IMAGE_RW_B;
+#endif
+		return EC_IMAGE_RW;
+	}
+}
+
+void system_set_image_copy(enum ec_image copy)
+{
+	uint32_t fwctrl;
+
+	fwctrl = read_fwctrl();
+	switch (copy) {
+	case EC_IMAGE_RW:
+		CLEAR_BIT(fwctrl, NPCX_FWCTRL_RO_REGION);
+		SET_BIT(fwctrl, NPCX_FWCTRL_FW_SLOT);
+		break;
+#ifdef CONFIG_RW_B
+	case EC_IMAGE_RW_B:
+		CLEAR_BIT(fwctrl, NPCX_FWCTRL_RO_REGION);
+		CLEAR_BIT(fwctrl, NPCX_FWCTRL_FW_SLOT);
+		break;
+#endif
+	default:
+		/* Fall through to EC_IMAGE_RO */
+	case EC_IMAGE_RO:
+		SET_BIT(fwctrl, NPCX_FWCTRL_RO_REGION);
+		SET_BIT(fwctrl, NPCX_FWCTRL_FW_SLOT);
+		break;
+	}
+
+	write_fwctrl(fwctrl);
+}
diff --git a/zephyr/shim/chip/stm32/CMakeLists.txt b/zephyr/shim/chip/stm32/CMakeLists.txt
new file mode 100644
index 0000000000..8dfbcd5834
--- /dev/null
+++ b/zephyr/shim/chip/stm32/CMakeLists.txt
@@ -0,0 +1,7 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cros_ec_library_include_directories(include)
+
+zephyr_library_sources(clock.c)
diff --git a/zephyr/shim/chip/stm32/clock.c b/zephyr/shim/chip/stm32/clock.c
new file mode 100644
index 0000000000..0218d656bb
--- /dev/null
+++ b/zephyr/shim/chip/stm32/clock.c
@@ -0,0 +1,11 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "clock.h"
+#include "common.h"
+
+test_mockable void clock_enable_module(enum module_id module, int enable)
+{
+}
diff --git a/zephyr/shim/chip/stm32/include/flash_chip.h b/zephyr/shim/chip/stm32/include/flash_chip.h
new file mode 100644
index 0000000000..cd896eca9a
--- /dev/null
+++ b/zephyr/shim/chip/stm32/include/flash_chip.h
@@ -0,0 +1,22 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_FLASH_CHIP_H
+#define __CROS_EC_FLASH_CHIP_H
+
+/* Minimum write size */
+#define CONFIG_FLASH_WRITE_SIZE \
+	DT_PROP(DT_INST(0, soc_nv_flash), write_block_size)
+
+/* No page mode, so use minimum write size */
+#define CONFIG_FLASH_WRITE_IDEAL_SIZE CONFIG_FLASH_WRITE_SIZE
+
+/* RO image offset inside protected storage (RO part) */
+#define CONFIG_RO_STORAGE_OFF 0x0
+
+/* RW image offset inside writable storage (RW part) */
+#define CONFIG_RW_STORAGE_OFF 0x0
+
+#endif /* __CROS_EC_FLASH_CHIP_H */
diff --git a/zephyr/shim/chip/stub/CMakeLists.txt b/zephyr/shim/chip/stub/CMakeLists.txt
new file mode 100644
index 0000000000..8dfbcd5834
--- /dev/null
+++ b/zephyr/shim/chip/stub/CMakeLists.txt
@@ -0,0 +1,7 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cros_ec_library_include_directories(include)
+
+zephyr_library_sources(clock.c)
diff --git a/zephyr/shim/chip/stub/clock.c b/zephyr/shim/chip/stub/clock.c
new file mode 100644
index 0000000000..0218d656bb
--- /dev/null
+++ b/zephyr/shim/chip/stub/clock.c
@@ -0,0 +1,11 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "clock.h"
+#include "common.h"
+
+test_mockable void clock_enable_module(enum module_id module, int enable)
+{
+}
diff --git a/zephyr/shim/core/CMakeLists.txt b/zephyr/shim/core/CMakeLists.txt
new file mode 100644
index 0000000000..ef116e376a
--- /dev/null
+++ b/zephyr/shim/core/CMakeLists.txt
@@ -0,0 +1,7 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if (DEFINED CONFIG_CPU_CORTEX_M)
+    add_subdirectory(cortex-m)
+endif()
diff --git a/zephyr/shim/core/cortex-m/CMakeLists.txt b/zephyr/shim/core/cortex-m/CMakeLists.txt
new file mode 100644
index 0000000000..8cc60076eb
--- /dev/null
+++ b/zephyr/shim/core/cortex-m/CMakeLists.txt
@@ -0,0 +1,7 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CONSOLE_CMD_IRQ irq_command.c)
+zephyr_library_sources_ifdef(CONFIG_MPU mpu.c)
+zephyr_library_sources(panic.c)
\ No newline at end of file
diff --git a/zephyr/shim/core/cortex-m/irq_command.c b/zephyr/shim/core/cortex-m/irq_command.c
new file mode 100644
index 0000000000..651f804800
--- /dev/null
+++ b/zephyr/shim/core/cortex-m/irq_command.c
@@ -0,0 +1,37 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+
+#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+
+/* IRQ counters */
+int irq_count[CONFIG_NUM_IRQS];
+
+void sys_trace_isr_enter_user(int nested_interrupts)
+{
+	ARG_UNUSED(nested_interrupts);
+
+	/* read the exception number */
+	uint32_t irq = __get_IPSR() - 16;
+
+	__ASSERT(irq < CONFIG_NUM_IRQS, "Invalid IRQ number");
+
+	irq_count[irq]++;
+}
+
+static int command_irq(int argc, const char **argv)
+{
+	ARG_UNUSED(argc);
+	ARG_UNUSED(argv);
+
+	for (int i = 0; i < CONFIG_NUM_IRQS; i++) {
+		if (irq_count[i])
+			ccprintf("  IRQ %d: %d\n", i, irq_count[i]);
+	}
+
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(irq, command_irq, "", "List irq counters");
diff --git a/zephyr/shim/core/cortex-m/mpu.c b/zephyr/shim/core/cortex-m/mpu.c
new file mode 100644
index 0000000000..4f1e893d48
--- /dev/null
+++ b/zephyr/shim/core/cortex-m/mpu.c
@@ -0,0 +1,38 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "config.h"
+#include "mpu.h"
+
+#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <zephyr/arch/cpu.h>
+#include <zephyr/init.h>
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(shim_mpu, LOG_LEVEL_ERR);
+
+void mpu_enable(void)
+{
+	for (int index = 0; index < mpu_config.num_regions; index++) {
+		MPU->RNR = index;
+		MPU->RASR |= MPU_RASR_ENABLE_Msk;
+		LOG_DBG("[%d] %08x %08x", index, MPU->RBAR, MPU->RASR);
+	}
+}
+
+static int mpu_disable_fixed_regions(void)
+{
+	/* MPU is configured and enabled by the Zephyr init code, disable the
+	 * fixed sections by default.
+	 */
+	for (int index = 0; index < mpu_config.num_regions; index++) {
+		MPU->RNR = index;
+		MPU->RASR &= ~MPU_RASR_ENABLE_Msk;
+		LOG_DBG("[%d] %08x %08x", index, MPU->RBAR, MPU->RASR);
+	}
+
+	return 0;
+}
+
+SYS_INIT(mpu_disable_fixed_regions, PRE_KERNEL_1, 50);
diff --git a/zephyr/shim/core/cortex-m/panic.c b/zephyr/shim/core/cortex-m/panic.c
new file mode 100644
index 0000000000..d42eec5e1f
--- /dev/null
+++ b/zephyr/shim/core/cortex-m/panic.c
@@ -0,0 +1,67 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "panic.h"
+
+#define BASE_EXCEPTION_FRAME_SIZE_BYTES (8 * sizeof(uint32_t))
+#define FPU_EXCEPTION_FRAME_SIZE_BYTES (18 * sizeof(uint32_t))
+
+/*
+ * Returns non-zero if the exception frame was created on the main stack, or
+ * zero if it's on the process stack.
+ *
+ * See B1.5.8 "Exception return behavior" of ARM DDI 0403D for details.
+ */
+static int32_t is_frame_in_handler_stack(const uint32_t exc_return)
+{
+	return (exc_return & 0xf) == 1 || (exc_return & 0xf) == 9;
+}
+
+/*
+ * Returns the size of the exception frame.
+ *
+ * See B1.5.7 "Stack alignment on exception entry" of ARM DDI 0403D for details.
+ * In short, the exception frame size can be either 0x20, 0x24, 0x68, or 0x6c
+ * depending on FPU context and padding for 8-byte alignment.
+ */
+static uint32_t get_exception_frame_size(const struct panic_data *pdata)
+{
+	uint32_t frame_size = 0;
+
+	/* base exception frame */
+	frame_size += BASE_EXCEPTION_FRAME_SIZE_BYTES;
+
+	/* CPU uses xPSR[9] to indicate whether it padded the stack for
+	 * alignment or not.
+	 */
+	if (pdata->cm.frame[CORTEX_PANIC_FRAME_REGISTER_PSR] & BIT(9))
+		frame_size += sizeof(uint32_t);
+
+#ifdef CONFIG_FPU
+	/* CPU uses EXC_RETURN[4] to indicate whether it stored extended
+	 * frame for FPU or not.
+	 */
+	if (!(pdata->cm.regs[CORTEX_PANIC_REGISTER_LR] & BIT(4)))
+		frame_size += FPU_EXCEPTION_FRAME_SIZE_BYTES;
+#endif
+
+	return frame_size;
+}
+
+/*
+ * Returns the position of the process stack before the exception frame.
+ * It computes the size of the exception frame and adds it to psp.
+ * If the exception happened in the exception context, it returns psp as is.
+ */
+uint32_t get_panic_stack_pointer(const struct panic_data *pdata)
+{
+	uint32_t psp = pdata->cm.regs[CORTEX_PANIC_REGISTER_PSP];
+
+	if (!is_frame_in_handler_stack(
+		    pdata->cm.regs[CORTEX_PANIC_REGISTER_LR]))
+		psp += get_exception_frame_size(pdata);
+
+	return psp;
+}
diff --git a/zephyr/shim/include/adc_chip.h b/zephyr/shim/include/adc_chip.h
new file mode 100644
index 0000000000..f5580a52ab
--- /dev/null
+++ b/zephyr/shim/include/adc_chip.h
@@ -0,0 +1,16 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * This file is left intentionally blank. It is required since the
+ * platform/ec/common/adc.c file includes it. Normally, this file
+ * would define chip specific ADC configs and would reside under
+ * platform/ec/chip/...
+ */
+
+#ifndef __CROS_EC_ADC_CHIP_H
+#define __CROS_EC_ADC_CHIP_H
+
+#endif /* __CROS_EC_ADC_CHIP_H */
diff --git a/zephyr/shim/include/atomic.h b/zephyr/shim/include/atomic.h
index 41260c1238..540a43ccbc 100644
--- a/zephyr/shim/include/atomic.h
+++ b/zephyr/shim/include/atomic.h
@@ -1,45 +1,22 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#ifndef __CROS_EC_ATOMIC_H
-#define __CROS_EC_ATOMIC_H
-
-#include <sys/atomic.h>
-
 /*
- * Below EC APIs are being deprecated and replaced with the Zephyr
- * APIs.  We already get the Zephyr APIs from sys/atomic.h.  The
- * definitions here are provided so we can shim-in modules using the
- * deprecated APIs while the transition is under way.
+ * TODO(b/272518464): Work around coreboot GCC preprocessor bug.
+ * #line marks the *next* line, so it is off by one.
  */
-static inline void deprecated_atomic_clear_bits(uint32_t volatile *addr,
-						uint32_t bits)
-{
-	atomic_and((atomic_t *)addr, bits);
-}
+#line 11
 
-static inline void deprecated_atomic_or(uint32_t volatile *addr, uint32_t bits)
-{
-	atomic_or((atomic_t *)addr, bits);
-}
-
-static inline void deprecated_atomic_add(uint32_t volatile *addr,
-					 uint32_t value)
-{
-	atomic_add((atomic_t *)addr, value);
-}
+#ifndef __CROS_EC_ATOMIC_H
+#define __CROS_EC_ATOMIC_H
 
-static inline void deprecated_atomic_sub(uint32_t volatile *addr,
-					 uint32_t value)
-{
-	atomic_sub((atomic_t *)addr, value);
-}
+#include <zephyr/sys/atomic.h>
 
-static inline uint32_t deprecated_atomic_read_clear(uint32_t volatile *addr)
+static inline atomic_val_t atomic_clear_bits(atomic_t *addr, atomic_val_t bits)
 {
-	return atomic_clear((atomic_t *)addr);
+	return atomic_and(addr, ~bits);
 }
 
-#endif  /* __CROS_EC_ATOMIC_H */
+#endif /* __CROS_EC_ATOMIC_H */
diff --git a/zephyr/shim/include/battery_enum.h b/zephyr/shim/include/battery_enum.h
new file mode 100644
index 0000000000..95fbecf8d2
--- /dev/null
+++ b/zephyr/shim/include/battery_enum.h
@@ -0,0 +1,29 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_CONFIG_CHIP_H
+#error "This file must only be included from config_chip.h and it should be" \
+	"included in all zephyr builds automatically"
+#endif
+
+#define BATTERY_ENUM(val) DT_CAT(BATTERY_, val)
+#define BATTERY_TYPE(id) BATTERY_ENUM(DT_STRING_UPPER_TOKEN(id, enum_name))
+#define BATTERY_TYPE_WITH_COMMA(id) BATTERY_TYPE(id),
+
+/* This produces a list of BATTERY_<ENUM_NAME> identifiers */
+/* clang-format off */
+enum battery_type {
+#if DT_HAS_COMPAT_STATUS_OKAY(battery_smart)
+	DT_FOREACH_STATUS_OKAY(battery_smart, BATTERY_TYPE_WITH_COMMA)
+#endif
+	BATTERY_TYPE_COUNT,
+};
+/* clang-format on */
+
+#undef BATTERY_TYPE_WITH_COMMA
+
+#if DT_NODE_EXISTS(DT_NODELABEL(default_battery_3s))
+extern const enum battery_type DEFAULT_BATTERY_TYPE_3S;
+#endif
diff --git a/zephyr/shim/include/bbram.h b/zephyr/shim/include/bbram.h
new file mode 100644
index 0000000000..4b33c5f281
--- /dev/null
+++ b/zephyr/shim/include/bbram.h
@@ -0,0 +1,33 @@
+/* Copyright 2022 Google LLC
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_BBRAM_H
+#define __CROS_EC_BBRAM_H
+
+#include <zephyr/devicetree.h>
+#include <zephyr/toolchain.h>
+
+BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(named_bbram_regions) == 1,
+	     "only one named-bbram-regions compatible node may be present");
+
+#define BBRAM_NODE DT_COMPAT_GET_ANY_STATUS_OKAY(named_bbram_regions)
+
+/*
+ * Check if a specific region has been defined under the named-bbram-region
+ * node.
+ */
+#define BBRAM_HAS_REGION(name) (DT_NODE_EXISTS(DT_CHILD(BBRAM_NODE, name)))
+
+/*
+ * Get the size of a specific region.
+ */
+#define BBRAM_REGION_SIZE(name) (DT_PROP(DT_CHILD(BBRAM_NODE, name), size))
+
+/*
+ * Get the offset of a specific region.
+ */
+#define BBRAM_REGION_OFFSET(name) (DT_PROP(DT_CHILD(BBRAM_NODE, name), offset))
+
+#endif /* __CROS_EC_BBRAM_H */
diff --git a/zephyr/shim/include/board.h b/zephyr/shim/include/board.h
deleted file mode 100644
index 01f9344a8a..0000000000
--- a/zephyr/shim/include/board.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __BOARD_H
-#define __BOARD_H
-
-/* Intentionally empty. */
-
-#endif  /* __BOARD_H */
diff --git a/zephyr/shim/include/board_led.h b/zephyr/shim/include/board_led.h
new file mode 100644
index 0000000000..ae4b23d74e
--- /dev/null
+++ b/zephyr/shim/include/board_led.h
@@ -0,0 +1,28 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __BOARD_LED_H
+#define __BOARD_LED_H
+
+#include <stdint.h>
+
+#include <zephyr/drivers/pwm.h>
+
+struct board_led_pwm_dt_channel {
+	const struct device *dev;
+	uint32_t channel;
+	pwm_flags_t flags;
+};
+
+#define BOARD_LED_PWM_DT_CHANNEL_INITIALIZER(node_id)        \
+	{                                                    \
+		.dev = DEVICE_DT_GET(DT_PWMS_CTLR(node_id)), \
+		.channel = DT_PWMS_CHANNEL(node_id),         \
+		.flags = DT_PWMS_FLAGS(node_id),             \
+	}
+
+#define BOARD_LED_HZ_TO_PERIOD_NS(freq_hz) (NSEC_PER_SEC / freq_hz)
+
+#endif /* __BOARD_LED_H */
diff --git a/zephyr/shim/include/builtin/assert.h b/zephyr/shim/include/builtin/assert.h
index 183e52ae79..e5e4a34b21 100644
--- a/zephyr/shim/include/builtin/assert.h
+++ b/zephyr/shim/include/builtin/assert.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,10 +6,16 @@
 #ifndef __CROS_EC_ASSERT_H
 #define __CROS_EC_ASSERT_H
 
-#include <sys/__assert.h>
+#include <zephyr/sys/__assert.h>
 
 #undef ASSERT
+#undef assert
 #define ASSERT __ASSERT_NO_MSG
 #define assert __ASSERT_NO_MSG
 
+/* TODO(b/269175417): This should be handled in Zephyr __assert.h */
+#ifndef __ASSERT_UNREACHABLE
+#define __ASSERT_UNREACHABLE CODE_UNREACHABLE
+#endif
+
 #endif /* __CROS_EC_ASSERT_H */
diff --git a/zephyr/shim/include/cbi_flash.h b/zephyr/shim/include/cbi_flash.h
new file mode 100644
index 0000000000..9f2fc26cc4
--- /dev/null
+++ b/zephyr/shim/include/cbi_flash.h
@@ -0,0 +1,28 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_CBI_FLASH_H
+#define __CROS_EC_CBI_FLASH_H
+
+#include "cros_board_info.h"
+
+#include <zephyr/devicetree.h>
+
+#define DT_DRV_COMPAT cros_ec_flash_layout
+
+#define CBI_FLASH_NODE DT_NODELABEL(cbi_flash)
+#define CBI_FLASH_OFFSET DT_PROP(CBI_FLASH_NODE, offset)
+#define CBI_FLASH_PRESERVE DT_PROP(CBI_FLASH_NODE, preserve)
+
+#if CONFIG_PLATFORM_EC_CBI_FLASH
+BUILD_ASSERT(DT_NODE_EXISTS(CBI_FLASH_NODE) == 1,
+	     "CBI flash DT node label not found");
+BUILD_ASSERT((CBI_FLASH_OFFSET % CONFIG_FLASH_ERASE_SIZE) == 0,
+	     "CBI flash offset is not erase-size aligned");
+BUILD_ASSERT((CBI_IMAGE_SIZE % CONFIG_FLASH_ERASE_SIZE) == 0,
+	     "CBI flash size is not erase-size aligned");
+BUILD_ASSERT(CBI_IMAGE_SIZE > 0, "CBI flash size must be greater than zero");
+#endif /* CONFIG_PLATFORM_EC_CBI_FLASH */
+#endif /* __CROS_EC_CBI_FLASH_H */
diff --git a/zephyr/shim/include/charger/chg_bq25710.h b/zephyr/shim/include/charger/chg_bq25710.h
new file mode 100644
index 0000000000..91d100a7de
--- /dev/null
+++ b/zephyr/shim/include/charger/chg_bq25710.h
@@ -0,0 +1,19 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/devicetree.h>
+#if defined(CONFIG_PLATFORM_EC_CHARGER_BQ25720) || \
+	defined(CONFIG_PLATFORM_EC_CHARGER_BQ25710)
+#include "driver/charger/bq25710.h"
+
+#define BQ25710_CHG_COMPAT ti_bq25710
+
+#define CHG_CONFIG_BQ25710(id)                     \
+	{                                          \
+		.i2c_port = I2C_PORT_BY_DEV(id),   \
+		.i2c_addr_flags = DT_REG_ADDR(id), \
+		.drv = &bq25710_drv,               \
+	},
+#endif
diff --git a/zephyr/shim/include/charger/chg_isl923x.h b/zephyr/shim/include/charger/chg_isl923x.h
new file mode 100644
index 0000000000..9156e574de
--- /dev/null
+++ b/zephyr/shim/include/charger/chg_isl923x.h
@@ -0,0 +1,18 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/charger/isl923x_public.h"
+
+#include <zephyr/devicetree.h>
+
+#define ISL923X_CHG_COMPAT intersil_isl923x
+#define ISL923X_EMUL_COMPAT cros_isl923x_emul
+
+#define CHG_CONFIG_ISL923X(id)                     \
+	{                                          \
+		.i2c_port = I2C_PORT_BY_DEV(id),   \
+		.i2c_addr_flags = DT_REG_ADDR(id), \
+		.drv = &isl923x_drv,               \
+	},
diff --git a/zephyr/shim/include/charger/chg_isl9241.h b/zephyr/shim/include/charger/chg_isl9241.h
new file mode 100644
index 0000000000..c6d2239038
--- /dev/null
+++ b/zephyr/shim/include/charger/chg_isl9241.h
@@ -0,0 +1,17 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/charger/isl9241_public.h"
+
+#include <zephyr/devicetree.h>
+
+#define ISL9241_CHG_COMPAT intersil_isl9241
+
+#define CHG_CONFIG_ISL9241(id)                     \
+	{                                          \
+		.i2c_port = I2C_PORT_BY_DEV(id),   \
+		.i2c_addr_flags = DT_REG_ADDR(id), \
+		.drv = &isl9241_drv,               \
+	},
diff --git a/zephyr/shim/include/charger/chg_rt9490.h b/zephyr/shim/include/charger/chg_rt9490.h
new file mode 100644
index 0000000000..44d81eac48
--- /dev/null
+++ b/zephyr/shim/include/charger/chg_rt9490.h
@@ -0,0 +1,18 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/charger/rt9490.h"
+
+#include <zephyr/devicetree.h>
+
+#define RT9490_CHG_COMPAT richtek_rt9490
+#define RT9490_EMUL_COMPAT zephyr_rt9490_emul
+
+#define CHG_CONFIG_RT9490(id)                      \
+	{                                          \
+		.i2c_port = I2C_PORT_BY_DEV(id),   \
+		.i2c_addr_flags = DT_REG_ADDR(id), \
+		.drv = &rt9490_drv,                \
+	},
diff --git a/zephyr/shim/include/charger/chg_sm5803.h b/zephyr/shim/include/charger/chg_sm5803.h
new file mode 100644
index 0000000000..853dd06a63
--- /dev/null
+++ b/zephyr/shim/include/charger/chg_sm5803.h
@@ -0,0 +1,17 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/charger/sm5803.h"
+
+#include <zephyr/devicetree.h>
+
+#define SM5803_CHG_COMPAT siliconmitus_sm5803
+
+#define CHG_CONFIG_SM5803(id)                      \
+	{                                          \
+		.i2c_port = I2C_PORT_BY_DEV(id),   \
+		.i2c_addr_flags = DT_REG_ADDR(id), \
+		.drv = &sm5803_drv,                \
+	},
diff --git a/zephyr/shim/include/charger_chips.h b/zephyr/shim/include/charger_chips.h
new file mode 100644
index 0000000000..503a53330d
--- /dev/null
+++ b/zephyr/shim/include/charger_chips.h
@@ -0,0 +1,33 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_CHARGER_CHIPS_H
+#define __CROS_EC_CHARGER_CHIPS_H
+
+#include "charger.h"
+
+#include <zephyr/devicetree.h>
+
+extern const struct charger_config_t chg_chips_alt[];
+
+#define ALT_CHG_CHIP_CHK(usbc_id, usb_port_num)                              \
+	COND_CODE_1(DT_REG_HAS_IDX(usbc_id, usb_port_num),                   \
+		    (COND_CODE_1(DT_NODE_HAS_PROP(usbc_id, chg_alt), (|| 1), \
+				 (|| 0))),                                   \
+		    (|| 0))
+
+#define CHG_ENABLE_ALTERNATE(usb_port_num)                                     \
+	do {                                                                   \
+		BUILD_ASSERT(                                                  \
+			(0 DT_FOREACH_STATUS_OKAY_VARGS(named_usbc_port,       \
+							ALT_CHG_CHIP_CHK,      \
+							usb_port_num)),        \
+			"Selected USB node does not exist or does not specify" \
+			"a charger alternate chip");                           \
+		memcpy(&chg_chips[usb_port_num], &chg_chips_alt[usb_port_num], \
+		       sizeof(struct charger_config_t));                       \
+	} while (0)
+
+#endif /* __CROS_EC_CHARGER_CHIPS_H */
diff --git a/zephyr/shim/include/charger_enum.h b/zephyr/shim/include/charger_enum.h
new file mode 100644
index 0000000000..a10a274e28
--- /dev/null
+++ b/zephyr/shim/include/charger_enum.h
@@ -0,0 +1,22 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef ZEPHYR_SHIM_INCLUDE_CHARGER_ENUM_H_
+#define ZEPHYR_SHIM_INCLUDE_CHARGER_ENUM_H_
+
+/*
+ * Theoretically, this should enumerate all the chargers
+ * by checking and processing each type, but practically
+ * if OCPC is enabled, there are only 2 chargers.
+ */
+enum chg_id {
+	CHARGER_PRIMARY,
+#if (CONFIG_USB_PD_PORT_MAX_COUNT > 1)
+	CHARGER_SECONDARY,
+#endif /* CONFIG_USB_PD_PORT_MAX_COUNT > 1 */
+	CHARGER_NUM,
+};
+
+#endif /* ZEPHYR_SHIM_INCLUDE_CHARGER_ENUM_H_ */
diff --git a/zephyr/shim/include/config_chip.h b/zephyr/shim/include/config_chip.h
index dc5f14865c..7254f7d786 100644
--- a/zephyr/shim/include/config_chip.h
+++ b/zephyr/shim/include/config_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,6 +6,25 @@
 #ifndef __CROS_EC_CONFIG_CHIP_H
 #define __CROS_EC_CONFIG_CHIP_H
 
+#include <zephyr/devicetree.h>
+#include <zephyr/toolchain.h>
+
+#define LID_ACCEL SENSOR_ID(DT_NODELABEL(lid_accel))
+
+#define SENSOR_NODE DT_PATH(motionsense_sensor)
+#define SENSOR_INFO_NODE DT_PATH(motionsense_sensor_info)
+#define SENSOR_ALT_NODE DT_PATH(motionsense_sensor_alt)
+
+/*
+ * The battery enum is used in various drivers and these assume that it is
+ * always available (defined in board.h). With Zephyr we don't include board.h
+ * so we have a battery_enum.h header in the shim which defines
+ * enum battery_type based on settings in the device tree. Include that here.
+ */
+#ifdef CONFIG_PLATFORM_EC_BATTERY
+#include "battery_enum.h"
+#endif
+
 /*
  * This file translates Kconfig options to platform/ec options.
  *
@@ -16,29 +35,3162 @@
  * common/config.h.
  */
 
-#define CONFIG_ZEPHYR
-#define CHROMIUM_EC
+/*
+ * Obsolete configs - these are options that are not needed, either because
+ * Zephyr features directly replace the option, or because the config option
+ * will not be used with Zephyr OS.
+ */
+
+/*
+ * ROM resident support. The ROM resident capabilities in the Chromium OS
+ * code are used with EC chipsets that provide more flash space than
+ * executable RAM. These options allow storing the initialized data into
+ * an unused area of flash where it is copied directly from flash into data
+ * RAM by the early boot code.
+ *
+ * When ROM resident is disabled, the initialized data is stored in the main
+ * image, copied from flash to executable RAM by the chip boot loader, and
+ * then copied from executable RAM to data RAM by the early boot code.
+ *
+ * Supporting this under Zephyr would require linker changes to the common
+ * Zephyr linking.
+ */
+#undef CONFIG_CHIP_DATA_IN_INIT_ROM
+#undef CONFIG_CHIP_INIT_ROM_REGION
+#undef CONFIG_RO_ROM_RESIDENT_MEM_OFF
+#undef CONFIG_RO_ROM_RESIDENT_SIZE
+#undef CONFIG_RW_ROM_RESIDENT_MEM_OFF
+#undef CONFIG_RW_ROM_RESIDENT_SIZE
+
+/*
+ * ECOS specific options, not used in Zephyr.
+ */
+#undef CONFIG_CONSOLE_UART /* Only used by the Chromium EC chip drivers */
+#undef CONFIG_I2C_MULTI_PORT_CONTROLLER /* Not required by I2C shim */
+#undef CONFIG_IRQ_COUNT /* Only used by Chromium EC core drivers */
+#undef CONFIG_KEYBOARD_KSO_HIGH_DRIVE /* Used by the Chromium EC chip drivers \
+				       */
+#undef CONFIG_LTO /* Link time optimization enabled by Zephyr build system */
+#undef CONFIG_STACK_SIZE /* Only used in Chromium EC core init code */
+#ifndef CONFIG_FPU
+#undef CONFIG_FPU /* Used in Zephyr as well, enabled in Kconfig directly */
+#endif
+#ifndef CONFIG_WATCHDOG
+#undef CONFIG_WATCHDOG /* Used in Zephyr as well, enabled in Kconfig directly \
+			*/
+#endif
+
+/*
+ * The Zephyr I2C shell command provides the same functionality as the Chromium
+ * EC i2cscan and i2cxfer commands, so they are always disabled.
+ */
+#undef CONFIG_CMD_I2C_SCAN
+#undef CONFIG_CMD_I2C_XFER
+
+/*
+ * This not used by the Zephyr code since we always make cros_crc8() available.
+ * Define it here to reduce the delta from the ECOS CONFIG.
+ */
+#undef CONFIG_CRC8
+#define CONFIG_CRC8
+
+/*
+ * This is not used by the Zephyr code.
+ * Define it here to reduce the delta from the ECOS CONFIG.
+ */
+#undef CONFIG_CHIP_PRE_INIT
+#define CONFIG_CHIP_PRE_INIT
+
+#undef CONFIG_BC12_SINGLE_DRIVER
+#ifdef CONFIG_PLATFORM_EC_BC12_SINGLE_DRIVER
+#define CONFIG_BC12_SINGLE_DRIVER
+#endif
+
+/* EC chipset configuration */
+#define HOOK_TICK_INTERVAL CONFIG_CROS_EC_HOOK_TICK_INTERVAL
+#define HOOK_TICK_INTERVAL_MS (HOOK_TICK_INTERVAL / 1000)
+
+/* Chipset and power configuration */
+#ifdef CONFIG_AP_ARM_QUALCOMM_SC7180
+#define CONFIG_CHIPSET_SC7180
+#endif
+
+#ifdef CONFIG_AP_ARM_QUALCOMM_SC7280
+#define CONFIG_CHIPSET_SC7280
+#endif
+
+#ifdef CONFIG_AP_X86_INTEL_CML
+#define CONFIG_CHIPSET_COMETLAKE
+#define CONFIG_CHIPSET_HAS_PRE_INIT_CALLBACK
+#endif
+
+#ifdef CONFIG_AP_X86_INTEL_TGL
+#define CONFIG_CHIPSET_TIGERLAKE
+#endif
+
+#ifdef CONFIG_AP_X86_INTEL_MTL
+#define CONFIG_CHIPSET_METEORLAKE
+#endif
+
+#undef CONFIG_FLASH_PROTECT_DEFERRED
+#ifdef CONFIG_PLATFORM_EC_FLASH_PROTECT_DEFERRED
+#define CONFIG_FLASH_PROTECT_DEFERRED
+#endif
+
+#undef CONFIG_THROTTLE_AP
+#ifdef CONFIG_PLATFORM_EC_THROTTLE_AP
+#define CONFIG_THROTTLE_AP
+#endif
+
+#undef CONFIG_THROTTLE_AP_SINGLE_PIN
+#ifdef CONFIG_PLATFORM_EC_THROTTLE_AP_SINGLE_PIN
+#define CONFIG_THROTTLE_AP_SINGLE_PIN
+#endif
+
+#undef CONFIG_THROTTLE_AP_NO_FAN
+#ifdef CONFIG_PLATFORM_EC_THROTTLE_AP_NO_FAN
+#define CONFIG_THROTTLE_AP_NO_FAN
+#endif
+
+#undef CONFIG_CHIPSET_CAN_THROTTLE
+#ifdef CONFIG_PLATFORM_EC_CHIPSET_CAN_THROTTLE
+#define CONFIG_CHIPSET_CAN_THROTTLE
+#endif
+
+#undef CONFIG_CMD_APTHROTTLE
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_APTHROTTLE
+#define CONFIG_CMD_APTHROTTLE
+#endif
+
+#undef CONFIG_THROTTLE_AP_ON_BAT_DISCHG_CURRENT
+#ifdef CONFIG_PLATFORM_EC_THROTTLE_AP_ON_BAT_DISCHG_CURRENT
+#define CONFIG_THROTTLE_AP_ON_BAT_DISCHG_CURRENT
+#endif
+
+#undef CONFIG_THROTTLE_AP_ON_BAT_VOLTAGE
+#ifdef CONFIG_PLATFORM_EC_THROTTLE_AP_ON_BAT_LOW_VOLTAGE
+#define CONFIG_THROTTLE_AP_ON_BAT_VOLTAGE
+#endif
+
+#undef CONFIG_BACKLIGHT_LID
+#ifdef CONFIG_PLATFORM_EC_BACKLIGHT_LID
+#define CONFIG_BACKLIGHT_LID
+#endif
+
+#undef CONFIG_BACKLIGHT_LID_ACTIVE_LOW
+#ifdef CONFIG_PLATFORM_EC_BACKLIGHT_LID_ACTIVE_LOW
+#define CONFIG_BACKLIGHT_LID_ACTIVE_LOW
+#endif
+
+/* Battery configuration */
+#undef CONFIG_BATTERY
+#ifdef CONFIG_PLATFORM_EC_BATTERY
+#define CONFIG_BATTERY
+#endif /* CONFIG_PLATFORM_EC_BATTERY */
+
+#undef CONFIG_BATTERY_FUEL_GAUGE
+#ifdef CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE
+#define CONFIG_BATTERY_FUEL_GAUGE
+#endif /* CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE */
+
+#undef CONFIG_BATTERY_V1
+#ifdef CONFIG_PLATFORM_EC_BATTERY_V1
+#define CONFIG_BATTERY_V1
+#endif
+
+#undef CONFIG_BATTERY_V2
+#ifdef CONFIG_PLATFORM_EC_BATTERY_V2
+#define CONFIG_BATTERY_V2
+#endif
+
+#undef CONFIG_HOSTCMD_BATTERY_V2
+#ifdef CONFIG_PLATFORM_EC_HOSTCMD_BATTERY_V2
+#define CONFIG_HOSTCMD_BATTERY_V2
+#endif
+
+#undef CONFIG_BATTERY_TYPE_NO_AUTO_DETECT
+#ifdef CONFIG_PLATFORM_EC_BATTERY_TYPE_NO_AUTO_DETECT
+#define CONFIG_BATTERY_TYPE_NO_AUTO_DETECT
+#endif
+
+#undef CONFIG_BATTERY_COUNT
+#define CONFIG_BATTERY_COUNT CONFIG_PLATFORM_EC_BATTERY_COUNT
+
+#undef CONFIG_BATTERY_SMART
+#ifdef CONFIG_PLATFORM_EC_BATTERY_SMART
+#define CONFIG_BATTERY_SMART
+#endif
+
+#undef CONFIG_I2C_VIRTUAL_BATTERY
+#undef I2C_PORT_VIRTUAL_BATTERY
+#ifdef CONFIG_PLATFORM_EC_I2C_VIRTUAL_BATTERY
+#define CONFIG_I2C_VIRTUAL_BATTERY
+#define VIRTUAL_BATTERY_ADDR_FLAGS CONFIG_PLATFORM_EC_I2C_VIRTUAL_BATTERY_ADDR
+#endif
+
+#undef CONFIG_SMART_BATTERY_OPTIONAL_MFG_FUNC
+#ifdef CONFIG_PLATFORM_EC_SMART_BATTERY_OPTIONAL_MFG_FUNC
+#define CONFIG_SMART_BATTERY_OPTIONAL_MFG_FUNC
+#endif
+
+#undef CONFIG_I2C_PASSTHRU_RESTRICTED
+#ifdef CONFIG_PLATFORM_EC_I2C_PASSTHRU_RESTRICTED
+#define CONFIG_I2C_PASSTHRU_RESTRICTED
+#endif
+
+#undef CONFIG_CMD_I2C_SPEED
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_I2C_SPEED
+#define CONFIG_CMD_I2C_SPEED
+#endif
+
+#undef CONFIG_HOSTCMD_I2C_CONTROL
+#ifdef CONFIG_PLATFORM_EC_HOSTCMD_I2C_CONTROL
+#define CONFIG_HOSTCMD_I2C_CONTROL
+#endif
+
+#undef CONFIG_BATTERY_PRESENT_CUSTOM
+#ifdef CONFIG_PLATFORM_EC_BATTERY_PRESENT_CUSTOM
+#define CONFIG_BATTERY_PRESENT_CUSTOM
+#endif
+
+#undef CONFIG_BATTERY_PRESENT_GPIO
+#ifdef CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO
+/* This is always GPIO_BATT_PRES_ODL with Zephyr */
+#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BATT_PRES_ODL
+#endif
+
+#undef CONFIG_BATTERY_CRITICAL_SHUTDOWN_CUT_OFF
+#ifdef CONFIG_PLATFORM_EC_BATTERY_CRITICAL_SHUTDOWN_CUT_OFF
+#define CONFIG_BATTERY_CRITICAL_SHUTDOWN_CUT_OFF
+#endif
+
+#undef CONFIG_BATTERY_CHECK_CHARGE_TEMP_LIMITS
+#ifdef CONFIG_PLATFORM_EC_BATTERY_CHECK_CHARGE_TEMP_LIMITS
+#define CONFIG_BATTERY_CHECK_CHARGE_TEMP_LIMITS
+#endif
+
+#undef CONFIG_BATTERY_CUT_OFF
+#ifdef CONFIG_PLATFORM_EC_BATTERY_CUT_OFF
+#define CONFIG_BATTERY_CUT_OFF
+#endif
+
+#undef CONFIG_BATTERY_HW_PRESENT_CUSTOM
+#ifdef CONFIG_PLATFORM_EC_BATTERY_HW_PRESENT_CUSTOM
+#define CONFIG_BATTERY_HW_PRESENT_CUSTOM
+#endif
+
+#undef CONFIG_BATTERY_REVIVE_DISCONNECT
+#ifdef CONFIG_PLATFORM_EC_BATTERY_REVIVE_DISCONNECT
+#define CONFIG_BATTERY_REVIVE_DISCONNECT
+#endif
+
+#undef CONFIG_BATTERY_MEASURE_IMBALANCE
+#ifdef CONFIG_PLATFORM_EC_BATTERY_MEASURE_IMBALANCE
+
+#define CONFIG_BATTERY_MEASURE_IMBALANCE
+#define CONFIG_BATTERY_MAX_IMBALANCE_MV \
+	CONFIG_PLATFORM_EC_BATTERY_MAX_IMBALANCE_MV
+#define CONFIG_CHARGER_MIN_BAT_PCT_IMBALANCED_POWER_ON \
+	CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_IMBALANCED_POWER_ON
+#endif
+
+#undef CONFIG_BATTERY_STBL_STAT
+#ifdef CONFIG_PLATFORM_EC_BATTERY_STBL_STAT
+#define CONFIG_BATTERY_STBL_STAT
+#define CONFIG_BATT_ALARM_MASK1 CONFIG_PLATFORM_EC_BATT_ALARM_MASK1
+#define CONFIG_BATT_ALARM_MASK2 CONFIG_PLATFORM_EC_BATT_ALARM_MASK2
+#endif
+
+#undef CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV
+#if defined(CONFIG_PLATFORM_EC_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV) && \
+	(CONFIG_PLATFORM_EC_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV > 0)
+#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV \
+	CONFIG_PLATFORM_EC_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV
+#endif
+
+#undef CONFIG_BOARD_RESET_AFTER_POWER_ON
+#ifdef CONFIG_PLATFORM_EC_BOARD_RESET_AFTER_POWER_ON
+#define CONFIG_BOARD_RESET_AFTER_POWER_ON
+#endif
+
+#undef CONFIG_CHARGER_ISL9241
+#ifdef CONFIG_PLATFORM_EC_CHARGER_ISL9241
+#define CONFIG_CHARGER_ISL9241
+#endif
+
+#undef CONFIG_CHARGER_RAA489110
+#ifdef CONFIG_PLATFORM_EC_CHARGER_RAA489110
+#define CONFIG_CHARGER_RAA489110
+#endif
+
+#undef CONFIG_OCPC
+#ifdef CONFIG_PLATFORM_EC_OCPC
+#define CONFIG_OCPC
+#define CONFIG_OCPC_DEF_RBATT_MOHMS CONFIG_PLATFORM_EC_OCPC_DEF_RBATT_MOHMS
+#endif
+
+#undef CONFIG_OCPC_DEF_DRIVELIMIT_MILLIVOLTS
+#ifdef CONFIG_PLATFORM_EC_OCPC_DEF_DRIVELIMIT_MILLIVOLTS
+#define CONFIG_OCPC_DEF_DRIVELIMIT_MILLIVOLTS \
+	CONFIG_PLATFORM_EC_OCPC_DEF_DRIVELIMIT_MILLIVOLTS
+#endif
+
+#undef CONFIG_CHARGER_SINGLE_CHIP
+#ifdef CONFIG_PLATFORM_EC_CHARGER_SINGLE_CHIP
+#define CONFIG_CHARGER_SINGLE_CHIP
+#endif
+
+#undef CONFIG_CHARGER_RUNTIME_CONFIG
+#ifdef CONFIG_PLATFORM_EC_CHARGER_RUNTIME_CONFIG
+#define CONFIG_CHARGER_RUNTIME_CONFIG
+#endif
+
+/*
+ * Note - ISL9241 chargers for all channels are configured with the same
+ * switching frequency set with the Kconfig config.
+ */
+#undef CONFIG_ISL9241_SWITCHING_FREQ
+#if CONFIG_PLATFORM_EC_ISL9241_SWITCHING_FREQ != -1
+#define CONFIG_ISL9241_SWITCHING_FREQ CONFIG_PLATFORM_EC_ISL9241_SWITCHING_FREQ
+#endif
+
+#undef CONFIG_CHARGER_INIT_CUSTOM
+#ifdef CONFIG_PLATFORM_EC_CHARGER_INIT_CUSTOM
+#define CONFIG_CHARGER_INIT_CUSTOM
+#endif
+
+#undef CONFIG_CHARGER_BYPASS_REVERSE_TURBO
+#ifdef CONFIG_PLATFORM_EC_CHARGER_BYPASS_REVERSE_TURBO
+#define CONFIG_CHARGER_BYPASS_REVERSE_TURBO
+#endif
+
+#undef CONFIG_CHARGER_ISL9237
+#ifdef CONFIG_PLATFORM_EC_CHARGER_ISL9237
+#define CONFIG_CHARGER_ISL9237
+#endif
+
+#undef CONFIG_CHARGER_ISL9238
+#ifdef CONFIG_PLATFORM_EC_CHARGER_ISL9238
+#define CONFIG_CHARGER_ISL9238
+#endif
+
+#undef CONFIG_CHARGER_ISL9238C
+#ifdef CONFIG_PLATFORM_EC_CHARGER_ISL9238C
+#define CONFIG_CHARGER_ISL9238C
+#endif
+
+#undef CONFIG_ISL9238C_DISABLE_CMOUT_LATCH
+#ifdef CONFIG_PLATFORM_EC_ISL9238C_DISABLE_CMOUT_LATCH
+#define CONFIG_ISL9238C_DISABLE_CMOUT_LATCH
+#endif
+
+#undef CONFIG_ISL9238C_ENABLE_BUCK_MODE
+#ifdef CONFIG_PLATFORM_EC_ISL9238C_ENABLE_BUCK_MODE
+#define CONFIG_ISL9238C_ENABLE_BUCK_MODE
+#endif
+
+#undef CONFIG_ISL9238C_BUCK_PHASE_VOLTAGE
+#ifdef CONFIG_PLATFORM_EC_ISL9238C_BUCK_PHASE_VOLTAGE
+#define CONFIG_ISL9238C_BUCK_PHASE_VOLTAGE \
+	CONFIG_PLATFORM_EC_ISL9238C_BUCK_PHASE_VOLTAGE
+#endif
+
+#undef CONFIG_AC_PROCHOT_CURRENT_MA
+#ifdef CONFIG_PLATFORM_EC_AC_PROCHOT_CURRENT_MA
+#define CONFIG_AC_PROCHOT_CURRENT_MA CONFIG_PLATFORM_EC_AC_PROCHOT_CURRENT_MA
+#endif
+
+#undef CONFIG_DC_PROCHOT_CURRENT_MA
+#ifdef CONFIG_PLATFORM_EC_DC_PROCHOT_CURRENT_MA
+#define CONFIG_DC_PROCHOT_CURRENT_MA CONFIG_PLATFORM_EC_DC_PROCHOT_CURRENT_MA
+#endif
+
+#undef CONFIG_CHARGER_DUMP_PROCHOT
+#ifdef CONFIG_PLATFORM_EC_CHARGER_DUMP_PROCHOT
+#define CONFIG_CHARGER_DUMP_PROCHOT
+#endif
+
+#undef CONFIG_CHARGER_RAA489000
+#ifdef CONFIG_PLATFORM_EC_CHARGER_RAA489000
+#define CONFIG_CHARGER_RAA489000
+#endif
+
+#undef CONFIG_CHARGER_SM5803
+#ifdef CONFIG_PLATFORM_EC_CHARGER_SM5803
+#define CONFIG_CHARGER_SM5803
+#endif
+
+#undef CONFIG_CHARGER_MAINTAIN_VBAT
+#ifdef CONFIG_PLATFORM_EC_CHARGER_MAINTAIN_VBAT
+#define CONFIG_CHARGER_MAINTAIN_VBAT
+#endif
+
+#undef CONFIG_CHARGER_TRICKLE
+#ifdef CONFIG_PLATFORM_EC_CHARGER_TRICKLE
+#define CONFIG_TRICKLE_CHARGING
+#endif
+
+#ifdef CONFIG_PLATFORM_EC_RAA489000_TRICKLE_CHARGE_CURRENT
+#undef CONFIG_RAA489000_TRICKLE_CHARGE_CURRENT
+#define CONFIG_RAA489000_TRICKLE_CHARGE_CURRENT \
+	CONFIG_PLATFORM_EC_RAA489000_TRICKLE_CHARGE_CURRENT
+#endif
+
+#undef CONFIG_CHARGER_BYPASS_MODE
+#ifdef CONFIG_PLATFORM_EC_CHARGER_BYPASS_MODE
+#define CONFIG_CHARGER_BYPASS_MODE
+#endif
+
+#undef CONFIG_CHARGER_NARROW_VDC
+#ifdef CONFIG_PLATFORM_EC_CHARGER_NARROW_VDC
+#define CONFIG_CHARGER_NARROW_VDC
+#endif
+
+#undef CONFIG_CHARGER_OTG
+#ifdef CONFIG_PLATFORM_EC_CHARGER_OTG
+#define CONFIG_CHARGER_OTG
+#endif
+
+#undef CONFIG_CHIPSET_RESET_HOOK
+#ifdef CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK
+#define CONFIG_CHIPSET_RESET_HOOK
+#endif
+
+#undef CONFIG_CHIPSET_RESUME_INIT_HOOK
+#ifdef CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK
+#define CONFIG_CHIPSET_RESUME_INIT_HOOK
+#endif
+
+#undef CONFIG_CHIP_INIT_ROM_REGION
+#ifdef CONFIG_PLATFORM_EC_CHIP_INIT_ROM_REGION
+#define CONFIG_CHIP_INIT_ROM_REGION
+#endif
+
+#undef CONFIG_EXTPOWER
+#ifdef CONFIG_PLATFORM_EC_EXTPOWER
+#define CONFIG_EXTPOWER
+#endif
+
+#undef CONFIG_EXTPOWER_GPIO
+#ifdef CONFIG_PLATFORM_EC_EXTPOWER_GPIO
+#define CONFIG_EXTPOWER_GPIO
+#endif
+
+/* Bringup configuration */
+#undef CONFIG_BRINGUP
+#ifdef CONFIG_PLATFORM_EC_BRINGUP
+#define CONFIG_BRINGUP
+#endif
+
+#undef CONFIG_EMULATED_SYSRQ
+#ifdef CONFIG_PLATFORM_EC_EMULATED_SYSRQ
+#define CONFIG_EMULATED_SYSRQ
+#endif
+
+/* Host interface selection */
+#undef CONFIG_HOST_INTERFACE_ESPI
+#ifdef CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
+#endif
+
+#undef CONFIG_HOST_INTERFACE_HECI
+#ifdef CONFIG_PLATFORM_EC_HOST_INTERFACE_HECI
+#define CONFIG_HOST_INTERFACE_HECI
+#endif
+
+#undef CONFIG_HOST_INTERFACE_LPC
+#ifdef CONFIG_PLATFORM_EC_HOST_INTERFACE_LPC
+#define CONFIG_HOST_INTERFACE_LPC
+#endif
+
+#undef CONFIG_HOST_INTERFACE_SHI
+#ifdef CONFIG_PLATFORM_EC_HOST_INTERFACE_SHI
+#define CONFIG_HOST_INTERFACE_SHI
+#endif
+
+#undef CONFIG_HOST_INTERFACE_USB
+#ifdef CONFIG_PLATFORM_EC_HOST_INTERFACE_USB
+#define CONFIG_HOST_INTERFACE_USB
+#endif
+
+/* eSPI signals */
+#undef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+#ifdef CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S3
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+#endif
+
+#undef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
+#ifdef CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S4
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
+#endif
+
+#undef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S5
+#ifdef CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S5
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S5
+#endif
+
+#undef CONFIG_HOST_INTERFACE_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST
+#ifdef CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST
+#define CONFIG_HOST_INTERFACE_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST
+#endif
+
+#undef CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US
+#ifdef CONFIG_PLATFORM_EC_DEFAULT_SCI_WIDTH_US
+#define CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US \
+	CONFIG_PLATFORM_EC_DEFAULT_SCI_WIDTH_US
+#endif
+
+#if DT_HAS_CHOSEN(zephyr_flash)
+#define CONFIG_PROGRAM_MEMORY_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash))
+#else
+#error "A zephyr,flash device must be chosen in the device tree"
+#endif
+
+#if DT_HAS_CHOSEN(zephyr_sram)
+#define CONFIG_RAM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
+#define CONFIG_DATA_RAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
+#elif defined(CONFIG_ARCH_POSIX)
+/* The jump data goes at the end of data ram, so for posix, the end of ram is
+ * wherever the jump data ended up.
+ */
+extern char mock_jump_data[CONFIG_PLATFORM_EC_PRESERVED_END_OF_RAM_SIZE];
+#define CONFIG_RAM_BASE 0x0
+#define CONFIG_DATA_RAM_SIZE            \
+	(((uintptr_t)&mock_jump_data) + \
+	 CONFIG_PLATFORM_EC_PRESERVED_END_OF_RAM_SIZE)
+#else
+#error "A zephyr,sram device must be chosen in the device tree"
+#endif
+
+#define CONFIG_RAM_SIZE CONFIG_DATA_RAM_SIZE
+
+#undef CONFIG_PRESERVED_END_OF_RAM_SIZE
+#ifdef CONFIG_PLATFORM_EC_PRESERVED_END_OF_RAM_SIZE
+#define CONFIG_PRESERVED_END_OF_RAM_SIZE \
+	CONFIG_PLATFORM_EC_PRESERVED_END_OF_RAM_SIZE
+#endif
+
+#define CONFIG_RO_MEM_OFF CONFIG_CROS_EC_RO_MEM_OFF
+#define CONFIG_RO_MEM_SIZE CONFIG_CROS_EC_RO_MEM_SIZE
+#define CONFIG_RW_MEM_OFF CONFIG_CROS_EC_RW_MEM_OFF
+#define CONFIG_RW_MEM_SIZE CONFIG_CROS_EC_RW_MEM_SIZE
+
+#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
+#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
+#if defined(CONFIG_PLATFORM_EC_FLASH_PSTATE)
+#define CONFIG_RO_SIZE (CONFIG_CROS_EC_RO_SIZE - CONFIG_FW_PSTATE_SIZE)
+#else
+#define CONFIG_RO_SIZE CONFIG_CROS_EC_RO_SIZE
+#endif
+#define CONFIG_RW_SIZE CONFIG_CROS_EC_RW_SIZE
+
+/*
+ * ROM resident area in flash used to store data objects that are not copied
+ * into code RAM. Enable using the CONFIG_CHIP_INIT_ROM_REGION option.
+ */
+#define CONFIG_RO_ROM_RESIDENT_MEM_OFF CONFIG_RO_SIZE
+#define CONFIG_RO_ROM_RESIDENT_SIZE \
+	(CONFIG_EC_PROTECTED_STORAGE_SIZE - CONFIG_RO_SIZE)
+
+/*
+ * RW firmware in program memory - Identical to RO, only one image loaded at
+ * a time.
+ */
+#define CONFIG_RW_ROM_RESIDENT_MEM_OFF CONFIG_RW_SIZE
+#define CONFIG_RW_ROM_RESIDENT_SIZE \
+	(CONFIG_EC_WRITABLE_STORAGE_SIZE - CONFIG_RW_SIZE)
+
+/* Flash settings */
+#undef CONFIG_EXTERNAL_STORAGE
+#undef CONFIG_INTERNAL_STORAGE
+#undef CONFIG_MAPPED_STORAGE
+#undef CONFIG_FLASH_PSTATE
+#undef CONFIG_FLASH_PSTATE_BANK
+#undef CONFIG_FLASH_PSTATE_LOCKED
+#ifdef CONFIG_PLATFORM_EC_FLASH_CROS
+
+#ifdef CONFIG_BOARD_NATIVE_POSIX
+#include "flash_chip_native_posix.h"
+#else
+#include "flash_chip.h"
+#endif
+
+#define CONFIG_FLASH_CROS
+
+/* Internal, don't use outside this header */
+#define _BINMAN_RO_PATH DT_PATH(binman, wp_ro)
+#define _BINMAN_RW_PATH DT_PATH(binman, ec_rw)
+
+#define CONFIG_EC_PROTECTED_STORAGE_OFF DT_PROP(_BINMAN_RO_PATH, offset)
+#define CONFIG_EC_PROTECTED_STORAGE_SIZE DT_PROP(_BINMAN_RO_PATH, size)
+#define CONFIG_EC_WRITABLE_STORAGE_OFF DT_PROP(_BINMAN_RW_PATH, offset)
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE DT_PROP(_BINMAN_RW_PATH, size)
+
+#undef CONFIG_EXTERNAL_STORAGE
+#ifdef CONFIG_PLATFORM_EC_EXTERNAL_STORAGE
+#define CONFIG_EXTERNAL_STORAGE
+#endif
+
+#undef CONFIG_INTERNAL_STORAGE
+#ifdef CONFIG_PLATFORM_EC_INTERNAL_STORAGE
+#define CONFIG_INTERNAL_STORAGE
+#endif
+
+#undef CONFIG_MAPPED_STORAGE
+#ifdef CONFIG_PLATFORM_EC_MAPPED_STORAGE
+#define CONFIG_MAPPED_STORAGE
+#endif
+
+#undef CONFIG_FLASH_PSTATE
+#ifdef CONFIG_PLATFORM_EC_FLASH_PSTATE
+#define CONFIG_FLASH_PSTATE
+#endif
+
+#undef CONFIG_FLASH_PSTATE_BANK
+#ifdef CONFIG_PLATFORM_EC_FLASH_PSTATE_BANK
+#define CONFIG_FLASH_PSTATE_BANK
+#endif
+
+#undef CONFIG_FLASH_PSTATE_LOCKED
+#ifdef CONFIG_PLATFORM_EC_FLASH_PSTATE_LOCKED
+#define CONFIG_FLASH_PSTATE_LOCKED
+#endif
+
+#undef CONFIG_CMD_FLASH
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_FLASH
+#define CONFIG_CMD_FLASH
+#endif
+
+#undef CONFIG_CMD_FLASHINFO
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_FLASHINFO
+#define CONFIG_CMD_FLASHINFO
+#endif
+
+#undef CONFIG_CMD_FLASH_WP
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_FLASH_WP
+#define CONFIG_CMD_FLASH_WP
+#endif
+
+#undef CONFIG_FLASH_MULTIPLE_REGION
+#ifdef CONFIG_PLATFORM_EC_USE_ZEPHYR_FLASH_PAGE_LAYOUT
+#define CONFIG_FLASH_MULTIPLE_REGION
+#endif
+
+#endif /* CONFIG_PLATFORM_EC_FLASH_CROS */
+
+#undef CONFIG_MAPPED_STORAGE_BASE
+#ifdef CONFIG_PLATFORM_EC_MAPPED_STORAGE_BASE
+#define CONFIG_MAPPED_STORAGE_BASE CONFIG_PLATFORM_EC_MAPPED_STORAGE_BASE
+#endif
+
+#undef CONFIG_FLASH_SIZE_BYTES
+#ifdef CONFIG_PLATFORM_EC_FLASH_SIZE_BYTES
+#define CONFIG_FLASH_SIZE_BYTES CONFIG_PLATFORM_EC_FLASH_SIZE_BYTES
+#endif /* CONFIG_PLATFORM_EC_FLASH_SIZE_BYTES */
+
+#undef CONFIG_ADC_CHANNELS_RUNTIME_CONFIG
+#ifdef CONFIG_PLATFORM_EC_ADC_CHANNELS_RUNTIME_CONFIG
+#define CONFIG_ADC_CHANNELS_RUNTIME_CONFIG
+#endif
+
+#undef CONFIG_CMD_ADC
+#ifdef CONFIG_PLATFORM_EC_ADC_CMD
+#define CONFIG_CMD_ADC
+#endif
+
+#undef CONFIG_TEMP_SENSOR
+#ifdef CONFIG_PLATFORM_EC_TEMP_SENSOR
+#define CONFIG_TEMP_SENSOR
+#endif
+
+#undef CONFIG_TEMP_SENSOR_POWER
+#ifdef CONFIG_PLATFORM_EC_TEMP_SENSOR_POWER
+#define CONFIG_TEMP_SENSOR_POWER
+#endif
+
+#undef CONFIG_THERMISTOR
+#ifdef CONFIG_PLATFORM_EC_THERMISTOR
+#define CONFIG_THERMISTOR
+#endif
+
+#undef CONFIG_TEMP_SENSOR_PCT2075
+#ifdef CONFIG_PLATFORM_EC_TEMP_SENSOR_PCT2075
+#define CONFIG_TEMP_SENSOR_PCT2075
+#endif
+
+#undef CONFIG_TEMP_SENSOR_SB_TSI
+#ifdef CONFIG_PLATFORM_EC_TEMP_SENSOR_SB_TSI
+#define CONFIG_TEMP_SENSOR_SB_TSI
+#endif
+
+#undef CONFIG_TEMP_SENSOR_TMP112
+#ifdef CONFIG_PLATFORM_EC_TEMP_SENSOR_TMP112
+#define CONFIG_TEMP_SENSOR_TMP112
+#endif
+
+#undef CONFIG_TEMP_SENSOR_F75303
+#ifdef CONFIG_PLATFORM_EC_TEMP_SENSOR_F75303
+#define CONFIG_TEMP_SENSOR_F75303
+#endif
+
+#undef CONFIG_FANS
+#ifdef CONFIG_PLATFORM_EC_NUM_FANS
+#define CONFIG_FANS CONFIG_PLATFORM_EC_NUM_FANS
+#endif
+
+#undef CONFIG_FAN_BYPASS_SLOW_RESPONSE
+#ifdef PLATFORM_EC_FAN_BYPASS_SLOW_RESPONSE
+#define CONFIG_FAN_BYPASS_SLOW_RESPONSE
+#endif
+
+#undef CONFIG_CUSTOM_FAN_CONTROL
+#ifdef CONFIG_PLATFORM_EC_CUSTOM_FAN_CONTROL
+#define CONFIG_CUSTOM_FAN_CONTROL
+#endif
+
+#undef CONFIG_FAN_RPM_CUSTOM
+#ifdef CONFIG_PLATFORM_EC_FAN_RPM_CUSTOM
+#define CONFIG_FAN_RPM_CUSTOM
+#endif
+
+#undef CONFIG_I2C_CONTROLLER
+#ifdef CONFIG_PLATFORM_EC_I2C
+/* Also see shim/include/i2c/i2c.h which defines the ports enum */
+#define CONFIG_I2C_CONTROLLER
+#endif
+
+#undef CONFIG_I2C_DEBUG
+#ifdef CONFIG_PLATFORM_EC_I2C_DEBUG
+#define CONFIG_I2C_DEBUG
+#endif
+
+#undef CONFIG_I2C_DEBUG_PASSTHRU
+#ifdef CONFIG_PLATFORM_EC_I2C_DEBUG_PASSTHRU
+#define CONFIG_I2C_DEBUG_PASSTHRU
+#endif
+
+#undef CONFIG_SMBUS_PEC
+#ifdef CONFIG_PLATFORM_EC_SMBUS_PEC
+#define CONFIG_SMBUS_PEC
+#endif
+
+#undef CONFIG_I2C_NACK_RETRY_COUNT
+#ifdef CONFIG_PLATFORM_EC_I2C_NACK_RETRY_COUNT
+#define CONFIG_I2C_NACK_RETRY_COUNT CONFIG_PLATFORM_EC_I2C_NACK_RETRY_COUNT
+#endif
+
+#undef CONFIG_KEYBOARD_PROTOCOL_8042
+#ifdef CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_8042
+#define CONFIG_KEYBOARD_PROTOCOL_8042
+#endif /* CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_8042 */
+
+#undef CONFIG_KEYBOARD_PROTOCOL_MKBP
+#ifdef CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_MKBP
+#define CONFIG_KEYBOARD_PROTOCOL_MKBP
+#endif
+
+#undef CONFIG_KEYBOARD_DEBUG
+#ifdef CONFIG_PLATFORM_EC_KEYBOARD_DEBUG
+#define CONFIG_KEYBOARD_DEBUG
+#endif
+
+#undef CONFIG_KEYBOARD_DISCRETE
+#ifdef CONFIG_PLATFORM_EC_KEYBOARD_DISCRETE
+#define CONFIG_KEYBOARD_DISCRETE
+#define KB_DISCRETE_I2C_ADDR_FLAGS DT_REG_ADDR(DT_NODELABEL(kb_discrete))
+#endif
+
+#undef CONFIG_MKBP_INPUT_DEVICES
+#ifdef CONFIG_PLATFORM_EC_MKBP_INPUT_DEVICES
+#define CONFIG_MKBP_INPUT_DEVICES
+#endif
+
+#undef CONFIG_MKBP_EVENT_WAKEUP_MASK
+#if defined(CONFIG_PLATFORM_EC_MKBP_EVENT_WAKEUP_MASK) && \
+	CONFIG_PLATFORM_EC_MKBP_EVENT_WAKEUP_MASK
+#define CONFIG_MKBP_EVENT_WAKEUP_MASK                                          \
+	DT_PROP(DT_COMPAT_GET_ANY_STATUS_OKAY(cros_ec_mkbp_event_wakeup_mask), \
+		wakeup_mask)
+#endif
+
+#undef CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK
+#if defined(CONFIG_PLATFORM_EC_MKBP_HOST_EVENT_WAKEUP_MASK) && \
+	CONFIG_PLATFORM_EC_MKBP_HOST_EVENT_WAKEUP_MASK
+#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK                    \
+	DT_PROP(DT_COMPAT_GET_ANY_STATUS_OKAY(                \
+			cros_ec_mkbp_host_event_wakeup_mask), \
+		wakeup_mask)
+#endif
+
+#undef CONFIG_CMD_KEYBOARD
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_KEYBOARD
+#define CONFIG_CMD_KEYBOARD
+#endif
+
+#undef CONFIG_KEYBOARD_COL2_INVERTED
+#ifdef CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED
+#define CONFIG_KEYBOARD_COL2_INVERTED
+#endif /* CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED */
+
+#undef CONFIG_KEYBOARD_REFRESH_ROW3
+#ifdef CONFIG_PLATFORM_EC_KEYBOARD_REFRESH_ROW3
+#define CONFIG_KEYBOARD_REFRESH_ROW3
+#endif /* CONFIG_PLATFORM_EC_KEYBOARD_REFRESH_ROW3 */
+
+#undef CONFIG_KEYBOARD_FACTORY_TEST
+#ifdef CONFIG_PLATFORM_EC_KEYBOARD_FACTORY_TEST
+#define CONFIG_KEYBOARD_FACTORY_TEST
+#endif
+
+#undef CONFIG_KEYBOARD_KEYPAD
+#ifdef CONFIG_PLATFORM_EC_KEYBOARD_KEYPAD
+#define CONFIG_KEYBOARD_KEYPAD
+#endif
+
+#undef CONFIG_KEYBOARD_VIVALDI
+#ifdef CONFIG_PLATFORM_EC_KEYBOARD_VIVALDI
+#define CONFIG_KEYBOARD_VIVALDI
+#endif
+
+#undef CONFIG_KEYBOARD_CUSTOMIZATION
+#ifdef CONFIG_PLATFORM_EC_KEYBOARD_CUSTOMIZATION
+#define CONFIG_KEYBOARD_CUSTOMIZATION
+#endif
+
+#undef CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2
+#ifdef CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI2
+#define CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2
+#endif
+
+#undef CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI3
+#ifdef CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI3
+#define CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI3
+#endif
+
+#undef CONFIG_VOLUME_BUTTONS
+#ifdef CONFIG_PLATFORM_EC_VOLUME_BUTTONS
+#define CONFIG_VOLUME_BUTTONS
+#endif
+
+#undef CONFIG_BUTTONS_RUNTIME_CONFIG
+#ifdef CONFIG_PLATFORM_EC_BUTTONS_RUNTIME_CONFIG
+#define CONFIG_BUTTONS_RUNTIME_CONFIG
+#endif
+
+#undef CONFIG_CMD_BUTTON
+#ifdef CONFIG_PLATFORM_EC_CMD_BUTTON
+#define CONFIG_CMD_BUTTON
+#endif
+
+#undef CONFIG_BUTTON_TRIGGERED_RECOVERY
+#ifdef CONFIG_PLATFORM_EC_BUTTON_TRIGGERED_RECOVERY
+#define CONFIG_BUTTON_TRIGGERED_RECOVERY
+#endif
+
+#undef CONFIG_PSE_LTC4291
+#ifdef PLATFORM_EC_PSE_LTC4291
+#define CONFIG_PSE_LTC4291
+#endif
+
+#undef CONFIG_KEYBOARD_BACKLIGHT
+#ifdef CONFIG_PLATFORM_KEYBOARD_BACKLIGHT
+#define CONFIG_KEYBOARD_BACKLIGHT
+#endif
+
+#undef CONFIG_PWM_KBLIGHT
+#ifdef CONFIG_PLATFORM_EC_PWM_KBLIGHT
+#define CONFIG_PWM_KBLIGHT
+#endif
+
+#undef CONFIG_KBLIGHT_ENABLE_PIN
+#ifdef CONFIG_PLATFORM_EC_KBLIGHT_ENABLE_PIN
+#define CONFIG_KBLIGHT_ENABLE_PIN
+#endif
+
+#undef CONFIG_KEYBOARD_STRICT_DEBOUNCE
+#ifdef CONFIG_PLATFORM_EC_KEYBOARD_STRICT_DEBOUNCE
+#define CONFIG_KEYBOARD_STRICT_DEBOUNCE
+#endif
+
+#undef CONFIG_KEYBOARD_SCANCODE_CALLBACK
+#ifdef CONFIG_PLATFORM_KEYBOARD_SCANCODE_CALLBACK
+#define CONFIG_KEYBOARD_SCANCODE_CALLBACK
+#endif
+
+#undef CONFIG_LED_COMMON
+#ifdef CONFIG_PLATFORM_EC_LED_COMMON
+#define CONFIG_LED_COMMON
+#endif
+
+#undef CONFIG_LED_PWM
+#ifdef CONFIG_PLATFORM_EC_LED_PWM
+#define CONFIG_LED_PWM
+#endif
+
+#undef CONFIG_LED_PWM_TASK_DISABLED
+#ifdef CONFIG_PLATFORM_EC_LED_PWM_TASK_DISABLED
+#define CONFIG_LED_PWM_TASK_DISABLED
+#endif
+
+#undef CONFIG_LED_PWM_COUNT
+#if DT_HAS_COMPAT_STATUS_OKAY(cros_ec_pwm_leds)
+#define CONFIG_LED_PWM_COUNT DT_PROP_LEN(DT_INST(0, cros_ec_pwm_leds), leds)
+#endif
+
+#ifdef CONFIG_PLATFORM_EC_LED_PWM_CHARGE_COLOR
+#undef CONFIG_LED_PWM_CHARGE_COLOR
+#define CONFIG_LED_PWM_CHARGE_COLOR CONFIG_PLATFORM_EC_LED_PWM_CHARGE_COLOR
+#endif
+
+#ifdef CONFIG_PLATFORM_EC_LED_PWM_NEAR_FULL_COLOR
+#undef CONFIG_LED_PWM_NEAR_FULL_COLOR
+#define CONFIG_LED_PWM_NEAR_FULL_COLOR \
+	CONFIG_PLATFORM_EC_LED_PWM_NEAR_FULL_COLOR
+#endif
+
+#ifdef CONFIG_PLATFORM_EC_LED_PWM_CHARGE_ERROR_COLOR
+#undef CONFIG_LED_PWM_CHARGE_ERROR_COLOR
+#define CONFIG_LED_PWM_CHARGE_ERROR_COLOR \
+	CONFIG_PLATFORM_EC_LED_PWM_CHARGE_ERROR_COLOR
+#endif
+
+#ifdef CONFIG_PLATFORM_EC_LED_PWM_SOC_ON_COLOR
+#undef CONFIG_LED_PWM_SOC_ON_COLOR
+#define CONFIG_LED_PWM_SOC_ON_COLOR CONFIG_PLATFORM_EC_LED_PWM_SOC_ON_COLOR
+#endif
+
+#ifdef CONFIG_PLATFORM_EC_LED_PWM_SOC_SUSPEND_COLOR
+#undef CONFIG_LED_PWM_SOC_SUSPEND_COLOR
+#define CONFIG_LED_PWM_SOC_SUSPEND_COLOR \
+	CONFIG_PLATFORM_EC_LED_PWM_SOC_SUSPEND_COLOR
+#endif
+
+#ifdef CONFIG_PLATFORM_EC_LED_PWM_LOW_BATT_COLOR
+#undef CONFIG_LED_PWM_LOW_BATT_COLOR
+#define CONFIG_LED_PWM_LOW_BATT_COLOR CONFIG_PLATFORM_EC_LED_PWM_LOW_BATT_COLOR
+#endif
+
+#undef CONFIG_CMD_LEDTEST
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_LEDTEST
+#define CONFIG_CMD_LEDTEST
+#endif
+
+#undef CONFIG_LED_ONOFF_STATES
+#ifdef CONFIG_PLATFORM_EC_LED_ONOFF_STATES
+#define CONFIG_LED_ONOFF_STATES
+#endif
+
+#undef CONFIG_LED_ONOFF_STATES_BAT_LOW
+#ifdef CONFIG_PLATFORM_EC_LED_ONOFF_STATES_BAT_LOW
+#define CONFIG_LED_ONOFF_STATES_BAT_LOW \
+	CONFIG_PLATFORM_EC_LED_ONOFF_STATES_BAT_LOW
+#endif
+
+#undef CONFIG_PWM_DISPLIGHT
+#ifdef CONFIG_PLATFORM_EC_PWM_DISPLIGHT
+#define CONFIG_PWM_DISPLIGHT
+#endif
+
+#undef CONFIG_CPU_PROCHOT_ACTIVE_LOW
+#ifdef CONFIG_PLATFORM_EC_POWERSEQ_CPU_PROCHOT_ACTIVE_LOW
+#define CONFIG_CPU_PROCHOT_ACTIVE_LOW
+#endif
+
+#undef CONFIG_CPU_PROCHOT_GATE_ON_C10
+#ifdef CONFIG_PLATFORM_EC_POWERSEQ_CPU_PROCHOT_GATE_ON_C10
+#define CONFIG_CPU_PROCHOT_GATE_ON_C10
+#endif
+
+#undef CONFIG_POWER_TRACK_HOST_SLEEP_STATE
+#if defined(CONFIG_PLATFORM_EC_POWERSEQ_HOST_SLEEP) || \
+	defined(CONFIG_AP_PWRSEQ_HOST_SLEEP)
+#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
+#endif
+
+#undef CONFIG_POWER_SLEEP_FAILURE_DETECTION
+#ifdef CONFIG_PLATFORM_EC_POWER_SLEEP_FAILURE_DETECTION
+#define CONFIG_POWER_SLEEP_FAILURE_DETECTION
+#endif
+
+#undef CONFIG_POWERSEQ_S0IX_COUNTER
+#ifdef CONFIG_PLATFORM_EC_POWERSEQ_S0IX_COUNTER
+#define CONFIG_POWERSEQ_S0IX_COUNTER
+#endif
+
+#undef CONFIG_HOSTCMD_AP_RESET
+#ifdef CONFIG_PLATFORM_EC_HOSTCMD_AP_RESET
+#define CONFIG_HOSTCMD_AP_RESET
+#endif
+
+#undef CONFIG_CHIPSET_X86_RSMRST_DELAY
+#ifdef CONFIG_PLATFORM_EC_POWERSEQ_RSMRST_DELAY
+#define CONFIG_CHIPSET_X86_RSMRST_DELAY
+#endif
+
+#undef CONFIG_CHIPSET_X86_RSMRST_AFTER_S5
+#ifdef CONFIG_PLATFORM_EC_POWERSEQ_RSMRST_AFTER_S5
+#define CONFIG_CHIPSET_X86_RSMRST_AFTER_S5
+#endif
+
+#undef CONFIG_CHIPSET_SLP_S3_L_OVERRIDE
+#ifdef CONFIG_PLATFORM_EC_POWERSEQ_SLP_S3_L_OVERRIDE
+#define CONFIG_CHIPSET_SLP_S3_L_OVERRIDE
+#endif
+
+#undef CONFIG_CHIPSET_PP3300_RAIL_FIRST
+#ifdef CONFIG_PLATFORM_EC_POWERSEQ_PP3300_RAIL_FIRST
+#define CONFIG_CHIPSET_PP3300_RAIL_FIRST
+#endif
+
+#ifdef CONFIG_PLATFORM_EC_POWERSEQ_RTC_RESET
+#define CONFIG_BOARD_HAS_RTC_RESET
+#define CONFIG_S5_EXIT_WAIT CONFIG_PLATFORM_EC_S5_EXIT_WAIT
+#endif
+
+#undef CONFIG_POWER_PP5000_CONTROL
+#ifdef CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL
+#define CONFIG_POWER_PP5000_CONTROL
+#endif
+
+#undef CONFIG_POWER_S0IX
+#if defined(CONFIG_PLATFORM_EC_POWERSEQ_S0IX) || defined(CONFIG_AP_PWRSEQ_S0IX)
+#define CONFIG_POWER_S0IX
+#endif
+
+#undef CONFIG_POWER_S4_RESIDENCY
+#ifdef CONFIG_PLATFORM_EC_POWERSEQ_S4
+#define CONFIG_POWER_S4_RESIDENCY
+#endif
+
+#undef CONFIG_POWER_BUTTON_X86
+#ifdef CONFIG_PLATFORM_EC_POWERSEQ_INTEL
+#define CONFIG_POWER_BUTTON_X86
+#endif
+
+#undef CONFIG_POWER_BUTTON_IGNORE_LID
+#ifdef CONFIG_PLATFORM_EC_POWER_BUTTON_IGNORE_LID
+#define CONFIG_POWER_BUTTON_IGNORE_LID
+#endif
+
+#undef CONFIG_POWER_BUTTON_TO_PCH_CUSTOM
+#ifdef CONFIG_PLATFORM_EC_POWER_BUTTON_TO_PCH_CUSTOM
+#define CONFIG_POWER_BUTTON_TO_PCH_CUSTOM
+#endif
+
+#undef CONFIG_POWER_BUTTON_INIT_TIMEOUT
+#ifdef CONFIG_PLATFORM_EC_POWER_BUTTON_INIT_TIMEOUT
+#define CONFIG_POWER_BUTTON_INIT_TIMEOUT \
+	CONFIG_PLATFORM_EC_POWER_BUTTON_INIT_TIMEOUT
+#endif
+
+#undef CONFIG_BUTTON_DEBOUNCE
+#define CONFIG_BUTTON_DEBOUNCE CONFIG_PLATFORM_EC_BUTTON_DEBOUNCE
+
+#undef CONFIG_POWERSEQ_FAKE_CONTROL
+#ifdef CONFIG_PLATFORM_EC_POWERSEQ_FAKE_CONTROL
+#define CONFIG_POWERSEQ_FAKE_CONTROL
+#endif
+
+#undef CONFIG_FAKE_SHMEM
+#ifdef CONFIG_ARCH_POSIX
+#define CONFIG_FAKE_SHMEM
+#endif
+
+#undef CONFIG_CMD_S5_TIMEOUT
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_S5_TIMEOUT
+#define CONFIG_CMD_S5_TIMEOUT
+#endif
+
+#undef CONFIG_CMD_SHMEM
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_SHMEM
+#define CONFIG_CMD_SHMEM
+#endif
+
+#undef CONFIG_CROS_FWID_VERSION
+#ifdef CONFIG_PLATFORM_EC_CROS_FWID_VERSION
+#define CONFIG_CROS_FWID_VERSION
+#endif
 
 #ifdef CONFIG_PLATFORM_EC_TIMER
 #define CONFIG_HWTIMER_64BIT
 #define CONFIG_HW_SPECIFIC_UDELAY
-#undef CONFIG_WATCHDOG
+#endif /* CONFIG_PLATFORM_EC_TIMER */
 
 #undef CONFIG_CMD_GETTIME
-#ifdef CONFIG_PLATFORM_EC_TIMER_CMD_GETTIME
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_GETTIME
 #define CONFIG_CMD_GETTIME
-#endif  /* CONFIG_PLATFORM_EC_TIMER_CMD_GETTIME */
+#endif /* CONFIG_PLATFORM_EC_CONSOLE_CMD_GETTIME */
 
 #undef CONFIG_CMD_TIMERINFO
-#ifdef CONFIG_PLATFORM_EC_TIMER_CMD_TIMERINFO
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_TIMERINFO
 #define CONFIG_CMD_TIMERINFO
-#endif  /* CONFIG_PLATFORM_EC_TIMER_CMD_TIMERINFO */
+#endif /* CONFIG_PLATFORM_EC_CONSOLE_CMD_TIMERINFO */
 
 #undef CONFIG_CMD_WAITMS
-#ifdef CONFIG_PLATFORM_EC_TIMER_CMD_WAITMS
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_WAITMS
 #define CONFIG_CMD_WAITMS
-#endif  /* CONFIG_PLATFORM_EC_TIMER_CMD_TIMERINFO */
+#endif /* CONFIG_PLATFORM_EC_CONSOLE_CMD_TIMERINFO */
+
+/* USB-C things */
+#ifdef CONFIG_PLATFORM_EC_USBC
+
+/* Zephyr only supports v2 so we always define this */
+#define CONFIG_USB_PD_TCPMV2
+
+/*
+ * Define these here for now. They are not actually CONFIG options in the EC
+ * code base. Ideally they would be defined in the devicetree (perhaps for a
+ * 'board' driver if not in the USB chip driver itself). Use Kconfig to allow
+ * projects to overwrite the power configurations.
+ *
+ * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
+ * cables only support up to 60W.
+ */
+#define PD_OPERATING_POWER_MW CONFIG_PLATFORM_EC_PD_OPERATING_POWER_MW
+#define PD_MAX_POWER_MW CONFIG_PLATFORM_EC_PD_MAX_POWER_MW
+#define PD_MAX_CURRENT_MA CONFIG_PLATFORM_EC_PD_MAX_CURRENT_MA
+#define PD_MAX_VOLTAGE_MV CONFIG_PLATFORM_EC_PD_MAX_VOLTAGE_MV
+
+#define PD_POWER_SUPPLY_TURN_ON_DELAY \
+	CONFIG_PLATFORM_EC_PD_POWER_SUPPLY_TURN_ON_DELAY
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY \
+	CONFIG_PLATFORM_EC_PD_POWER_SUPPLY_TURN_OFF_DELAY
+#endif /* CONFIG_PLATFORM_EC_USBC */
+
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
+#define CONFIG_EXTPOWER_DEBOUNCE_MS CONFIG_PLATFORM_EC_EXTPOWER_DEBOUNCE_MS
+
+#undef CONFIG_CMD_PPC_DUMP
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_PPC_DUMP
+#define CONFIG_CMD_PPC_DUMP
+#endif
+
+#undef CONFIG_USBC_PPC_LOGGING
+#ifdef CONFIG_PLATFORM_EC_USBC_PPC_LOGGING
+#define CONFIG_USBC_PPC_LOGGING
+#endif
+
+#undef CONFIG_CMD_TCPC_DUMP
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_TCPC_DUMP
+#define CONFIG_CMD_TCPC_DUMP
+#endif
+
+#undef CONFIG_USB_POWER_DELIVERY
+#ifdef CONFIG_PLATFORM_EC_USB_POWER_DELIVERY
+#define CONFIG_USB_POWER_DELIVERY
+#endif
+
+#undef CONFIG_CHARGE_MANAGER
+#ifdef CONFIG_PLATFORM_EC_CHARGE_MANAGER
+#define CONFIG_CHARGE_MANAGER
+
+/* TODO: Put these charger defines in the devicetree? */
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+#endif /* CONFIG_PLATFORM_EC_CHARGE_MANAGER */
+
+#undef CONFIG_CHARGER
+#ifdef CONFIG_PLATFORM_EC_CHARGER
+#define CONFIG_CHARGER
+#endif
+
+#undef CONFIG_CHARGE_STATE_DEBUG
+#ifdef CONFIG_PLATFORM_EC_CHARGE_STATE_DEBUG
+#define CONFIG_CHARGE_STATE_DEBUG
+#endif
+
+#undef CONFIG_CHARGE_DEBUG
+#ifdef CONFIG_PLATFORM_EC_CHARGE_DEBUG
+#define CONFIG_CHARGE_DEBUG
+#endif
+
+#undef CONFIG_CMD_PWR_AVG
+#ifdef CONFIG_PLATFORM_EC_CMD_PWR_AVG
+#define CONFIG_CMD_PWR_AVG
+#endif
+
+#undef CONFIG_CHARGESPLASH
+#ifdef CONFIG_PLATFORM_EC_CHARGESPLASH
+#define CONFIG_CHARGESPLASH
+#endif
+
+#undef CONFIG_CHARGESPLASH_PERIOD
+#ifdef CONFIG_PLATFORM_EC_CHARGESPLASH_PERIOD
+#define CONFIG_CHARGESPLASH_PERIOD CONFIG_PLATFORM_EC_CHARGESPLASH_PERIOD
+#endif
+
+#undef CONFIG_CHARGESPLASH_MAX_REQUESTS_PER_PERIOD
+#ifdef CONFIG_PLATFORM_EC_CHARGESPLASH_MAX_REQUESTS_PER_PERIOD
+#define CONFIG_CHARGESPLASH_MAX_REQUESTS_PER_PERIOD \
+	CONFIG_PLATFORM_EC_CHARGESPLASH_MAX_REQUESTS_PER_PERIOD
+#endif
+
+#undef CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT
+#ifdef CONFIG_PLATFORM_EC_CHARGER_DEFAULT_CURRENT_LIMIT
+#define CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT \
+	CONFIG_PLATFORM_EC_CHARGER_DEFAULT_CURRENT_LIMIT
+#endif
+
+#undef CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT
+#ifdef CONFIG_PLATFORM_EC_CHARGER_MIN_INPUT_CURRENT_LIMIT
+#define CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT \
+	CONFIG_PLATFORM_EC_CHARGER_MIN_INPUT_CURRENT_LIMIT
+#endif
+
+#undef CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
+#ifdef CONFIG_PLATFORM_EC_CHARGER_INPUT_CURRENT_DERATE_PCT
+#define CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT \
+	CONFIG_PLATFORM_EC_CHARGER_INPUT_CURRENT_DERATE_PCT
+#endif
+
+#undef CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON
+#ifdef CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON
+#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON \
+	CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON
+#endif
+
+#undef CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC
+#ifdef CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC
+#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC \
+	CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC
+#endif
+
+#undef CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT
+#ifdef CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT
+#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT \
+	CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT
+#endif
+
+#undef CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
+#ifdef CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON
+#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON \
+	CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON
+#endif
+
+#undef CONFIG_CHARGE_RAMP_SW
+#ifdef CONFIG_PLATFORM_EC_CHARGE_RAMP_SW
+#define CONFIG_CHARGE_RAMP_SW
+#endif
+
+#undef CONFIG_CHARGE_RAMP_HW
+#ifdef CONFIG_PLATFORM_EC_CHARGE_RAMP_HW
+#define CONFIG_CHARGE_RAMP_HW
+#endif
+
+#undef CONFIG_CMD_CHGRAMP
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_CHGRAMP
+#define CONFIG_CMD_CHGRAMP
+#endif
+
+#undef CONFIG_CMD_CHARGER_DUMP
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_DUMP
+#define CONFIG_CMD_CHARGER_DUMP
+#endif
+
+#undef CONFIG_USB_PID
+#ifdef CONFIG_PLATFORM_EC_USB_PID
+#define CONFIG_USB_PID CONFIG_PLATFORM_EC_USB_PID
+#endif
+
+#undef CONFIG_USB_BCD_DEV
+#ifdef CONFIG_PLATFORM_EC_USB_BCD_DEV
+#define CONFIG_USB_BCD_DEV CONFIG_PLATFORM_EC_USB_BCD_DEV
+#endif
+
+#undef CONFIG_USB_VID
+#ifdef CONFIG_PLATFORM_EC_USB_VID
+#define CONFIG_USB_VID CONFIG_PLATFORM_EC_USB_VID
+#endif
+
+#undef CONFIG_USB_MS_EXTENDED_COMPAT_ID_DESCRIPTOR
+#ifdef CONFIG_PLATFORM_EC_USB_MS_EXTENDED_COMPAT_ID_DESCRIPTOR
+#define CONFIG_USB_MS_EXTENDED_COMPAT_ID_DESCRIPTOR \
+	CONFIG_PLATFORM_EC_USB_MS_EXTENDED_COMPAT_ID_DESCRIPTOR
+#endif
+
+/* VBUS-voltage measurement */
+#undef CONFIG_USB_PD_VBUS_MEASURE_NOT_PRESENT
+#ifdef CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_NOT_PRESENT
+#define CONFIG_USB_PD_VBUS_MEASURE_NOT_PRESENT
+#endif
+
+#undef CONFIG_USB_PD_VBUS_MEASURE_CHARGER
+#ifdef CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_CHARGER
+#define CONFIG_USB_PD_VBUS_MEASURE_CHARGER
+#endif
+
+#undef CONFIG_USB_PD_VBUS_MEASURE_TCPC
+#ifdef CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_TCPC
+#define CONFIG_USB_PD_VBUS_MEASURE_TCPC
+#endif
+
+#undef CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT
+#ifdef CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_ADC_EACH_PORT
+#define CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT
+#endif
+
+#undef CONFIG_USB_PD_VBUS_MEASURE_BY_BOARD
+#ifdef CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_BY_BOARD
+#define CONFIG_USB_PD_VBUS_MEASURE_BY_BOARD
+#endif
+
+#undef CONFIG_CMD_VBUS
+#ifdef CONFIG_PLATFORM_EC_CMD_VBUS
+#define CONFIG_CMD_VBUS
+#endif
+
+#undef CONFIG_USB_CHARGER
+#ifdef CONFIG_PLATFORM_EC_USB_CHARGER
+#define CONFIG_USB_CHARGER
+#endif
+
+#undef CONFIG_USB_PORT_ENABLE_DYNAMIC
+#ifdef CONFIG_PLATFORM_EC_USB_PORT_ENABLE_DYNAMIC
+#define CONFIG_USB_PORT_ENABLE_DYNAMIC
+#endif
+
+#undef CONFIG_USB_PORT_POWER_DUMB
+#ifdef CONFIG_PLATFORM_EC_USB_PORT_POWER_DUMB
+#define CONFIG_USB_PORT_POWER_DUMB
+/* usb_charge.h sets USB_PORT_ENABLE_COUNT from this for POWER_DUMB */
+#define USB_PORT_COUNT                                                         \
+	COND_CODE_1(DT_NODE_EXISTS(DT_INST(0, cros_ec_usba_port_enable_pins)), \
+		    (DT_PROP_LEN(DT_INST(0, cros_ec_usba_port_enable_pins),    \
+				 enable_pins)),                                \
+		    (0))
+#endif
+
+#undef CONFIG_USB_PORT_POWER_DUMB_CUSTOM_HOOK
+#ifdef CONFIG_PLATFORM_EC_USB_PORT_POWER_DUMB_CUSTOM_HOOK
+#define CONFIG_USB_PORT_POWER_DUMB_CUSTOM_HOOK
+#endif
+
+#undef CONFIG_USB_PORT_POWER_SMART
+#ifdef CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART
+#define CONFIG_USB_PORT_POWER_SMART
+#undef CONFIG_USB_PORT_POWER_SMART_PORT_COUNT /* override config.h default */
+/* usb_charge.h sets USB_PORT_ENABLE_COUNT from this for POWER_SMART */
+#define CONFIG_USB_PORT_POWER_SMART_PORT_COUNT                                 \
+	COND_CODE_1(DT_NODE_EXISTS(DT_INST(0, cros_ec_usba_port_enable_pins)), \
+		    (DT_PROP_LEN(DT_INST(0, cros_ec_usba_port_enable_pins),    \
+				 enable_pins)),                                \
+		    (0))
+#endif
+
+#undef CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY
+#ifdef CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_CDP_SDP_ONLY
+#define CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY
+#endif
+
+#undef CONFIG_USB_PORT_POWER_SMART_SIMPLE
+#ifdef CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_SIMPLE
+#define CONFIG_USB_PORT_POWER_SMART_SIMPLE
+#endif
+
+#undef CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE
+#ifdef CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_DEFAULT_DISABLED
+#define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_DISABLED
+#endif
+
+#ifdef CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_DEFAULT_SDP
+#define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_SDP2
+#endif
+
+#ifdef CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_DEFAULT_CDP
+#define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_CDP
+#endif
+
+#undef CONFIG_USB_PORT_POWER_SMART_INVERTED
+#ifdef CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_INVERTED
+#define CONFIG_USB_PORT_POWER_SMART_INVERTED
+#endif
+
+#undef CONFIG_BC12_DETECT_RT1718S
+#ifdef CONFIG_PLATFORM_EC_BC12_DETECT_RT1718S
+#define CONFIG_BC12_DETECT_RT1718S
+#endif
+
+#undef CONFIG_BC12_CLIENT_MODE_ONLY_PI3USB9201
+#ifdef CONFIG_PLATFORM_EC_BC12_CLIENT_MODE_ONLY_PI3USB9201
+#define CONFIG_BC12_CLIENT_MODE_ONLY_PI3USB9201
+#endif
+
+#undef CONFIG_BC12_DETECT_PI3USB9201
+#ifdef CONFIG_PLATFORM_EC_BC12_DETECT_PI3USB9201
+#define CONFIG_BC12_DETECT_PI3USB9201
+#endif
+
+#undef CONFIG_BC12_DETECT_MT6360
+#ifdef CONFIG_PLATFORM_EC_BC12_DETECT_MT6360
+#define CONFIG_BC12_DETECT_MT6360
+#endif
+
+#undef CONFIG_BC12_DETECT_DATA_ROLE_TRIGGER
+#ifdef CONFIG_PLATFORM_EC_BC12_DETECT_DATA_ROLE_TRIGGER
+#define CONFIG_BC12_DETECT_DATA_ROLE_TRIGGER
+#endif
+
+#undef CONFIG_MT6360_BC12_GPIO
+#ifdef CONFIG_PLATFORM_EC_MT6360_BC12_GPIO
+#define CONFIG_MT6360_BC12_GPIO
+#endif
+
+#undef CONFIG_HOSTCMD_REGULATOR
+#ifdef CONFIG_PLATFORM_EC_HOSTCMD_REGULATOR
+#define CONFIG_HOSTCMD_REGULATOR
+#endif
+
+#undef CONFIG_USB_PD_DUAL_ROLE
+#ifdef CONFIG_PLATFORM_EC_USB_PD_DUAL_ROLE
+#define CONFIG_USB_PD_DUAL_ROLE
+#endif
+
+#undef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+#ifdef CONFIG_PLATFORM_EC_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+#endif
+
+#undef CONFIG_USB_PD_DISCHARGE
+#if defined(CONFIG_PLATFORM_EC_USB_PD_DISCHARGE) || \
+	defined(CONFIG_TEST_ENABLE_USB_PD_DISCHARGE)
+#define CONFIG_USB_PD_DISCHARGE
+#endif
+
+#undef CONFIG_USB_PD_DISCHARGE_GPIO
+#ifdef CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_GPIO
+#define CONFIG_USB_PD_DISCHARGE_GPIO
+#endif
+
+#undef CONFIG_USB_PD_DISCHARGE_TCPC
+#ifdef CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_TCPC
+#define CONFIG_USB_PD_DISCHARGE_TCPC
+#endif
+
+#undef CONFIG_USB_PD_DISCHARGE_PPC
+#ifdef CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC
+#define CONFIG_USB_PD_DISCHARGE_PPC
+#endif
+
+#undef CONFIG_USB_PD_LOGGING
+#ifdef CONFIG_PLATFORM_EC_USB_PD_LOGGING
+#define CONFIG_USB_PD_LOGGING
+#endif
+
+#undef CONFIG_USB_PD_PRL_EVENT_LOG
+#ifdef CONFIG_PLATFORM_EC_USB_PD_PRL_EVENT_LOG
+#define CONFIG_USB_PD_PRL_EVENT_LOG
+#endif
+
+#undef CONFIG_USB_PD_PRL_EVENT_LOG_CAPACITY
+#ifdef CONFIG_PLATFORM_EC_USB_PD_PRL_EVENT_LOG_CAPACITY
+#define CONFIG_USB_PD_PRL_EVENT_LOG_CAPACITY \
+	CONFIG_PLATFORM_EC_USB_PD_PRL_EVENT_LOG_CAPACITY
+#endif
+
+#undef CONFIG_USBC_OCP
+#ifdef CONFIG_PLATFORM_EC_USBC_OCP
+#define CONFIG_USBC_OCP
+#endif
+
+#undef CONFIG_USB_PD_CONSOLE_CMD
+#ifdef CONFIG_PLATFORM_EC_USB_PD_CONSOLE_CMD
+#define CONFIG_USB_PD_CONSOLE_CMD
+#endif
+
+#undef CONFIG_USB_PD_HOST_CMD
+#if defined(CONFIG_PLATFORM_EC_USB_PD_HOST_CMD) || \
+	defined(CONFIG_TEST_ENABLE_USB_PD_HOST_CMD)
+#define CONFIG_USB_PD_HOST_CMD
+#endif
+
+#undef CONFIG_USB_PD_REV30
+#ifdef CONFIG_PLATFORM_EC_USB_PD_REV30
+#define CONFIG_USB_PD_REV30
+#endif
+
+#undef CONFIG_USB_PD_EXTENDED_MESSAGES
+#ifdef CONFIG_PLATFORM_EC_USB_PD_EXTENDED_MESSAGES
+#define CONFIG_USB_PD_EXTENDED_MESSAGES
+#endif
+
+#undef CONFIG_USB_PD_VBUS_DETECT_TCPC
+#undef CONFIG_USB_PD_VBUS_DETECT_GPIO
+#ifdef CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC
+#define CONFIG_USB_PD_VBUS_DETECT_TCPC
+#endif
+
+#undef CONFIG_USB_PD_VBUS_DETECT_CHARGER
+#ifdef CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_CHARGER
+#define CONFIG_USB_PD_VBUS_DETECT_CHARGER
+#endif
+
+#undef CONFIG_USB_PD_VBUS_DETECT_PPC
+#ifdef CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_PPC
+#define CONFIG_USB_PD_VBUS_DETECT_PPC
+#endif
+
+#undef CONFIG_USB_PD_VBUS_DETECT_NONE
+#ifdef CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_NONE
+#define CONFIG_USB_PD_VBUS_DETECT_NONE
+#endif
+
+#undef CONFIG_USB_PD_5V_EN_CUSTOM
+#ifdef CONFIG_PLATFORM_EC_USB_PD_5V_EN_CUSTOM
+#define CONFIG_USB_PD_5V_EN_CUSTOM
+#endif
+
+#undef CONFIG_USB_PD_5V_CHARGER_CTRL
+#ifdef CONFIG_PLATFORM_EC_USB_PD_5V_CHARGER_CTRL
+#define CONFIG_USB_PD_5V_CHARGER_CTRL
+#endif
+
+#undef CONFIG_USB_TYPEC_SM
+#ifdef CONFIG_PLATFORM_EC_USB_TYPEC_SM
+#define CONFIG_USB_TYPEC_SM
+#endif
+
+#undef CONFIG_USB_PRL_SM
+#ifdef CONFIG_PLATFORM_EC_USB_PRL_SM
+#define CONFIG_USB_PRL_SM
+#endif
+
+#undef CONFIG_USB_PE_SM
+#ifdef CONFIG_PLATFORM_EC_USB_PE_SM
+#define CONFIG_USB_PE_SM
+#endif
+
+#undef CONFIG_USB_DPM_SM
+#ifdef CONFIG_PLATFORM_EC_USB_DPM_SM
+#define CONFIG_USB_DPM_SM
+#endif
+
+#undef CONFIG_USB_PD_DECODE_SOP
+#ifdef CONFIG_PLATFORM_EC_USB_PD_DECODE_SOP
+#define CONFIG_USB_PD_DECODE_SOP
+#endif
+
+#undef CONFIG_USB_VPD
+#ifdef CONFIG_PLATFORM_EC_USB_VPD
+#define CONFIG_USB_VPD
+#endif
+
+#undef CONFIG_USB_CTVPD
+#ifdef CONFIG_PLATFORM_EC_USB_CTVPD
+#define CONFIG_USB_CTVPD
+#endif
+
+#undef CONFIG_USB_DRP_ACC_TRYSRC
+#ifdef CONFIG_PLATFORM_EC_USB_DRP_ACC_TRYSRC
+#define CONFIG_USB_DRP_ACC_TRYSRC
+#endif
+
+#undef CONFIG_USB_PD_TCPM_FUSB302
+#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_FUSB302
+#define CONFIG_USB_PD_TCPM_FUSB302
+#endif
+
+#undef CONFIG_USB_PD_TCPM_NCT38XX
+#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_NCT38XX
+#define CONFIG_USB_PD_TCPM_NCT38XX
+#endif
+
+#undef CONFIG_USB_PD_TCPM_PS8745
+#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8745
+#define CONFIG_USB_PD_TCPM_PS8745
+#endif
+
+#undef CONFIG_USB_PD_TCPM_PS8745_FORCE_ID
+#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8745_FORCE_ID
+#define CONFIG_USB_PD_TCPM_PS8745_FORCE_ID
+#endif
+
+#undef CONFIG_USB_PD_TCPM_PS8751
+#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8751
+#define CONFIG_USB_PD_TCPM_PS8751
+#endif
+
+#undef CONFIG_USB_PD_TCPM_PS8805
+#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8805
+#define CONFIG_USB_PD_TCPM_PS8805
+#endif
+
+#undef CONFIG_USB_PD_TCPM_PS8805_FORCE_DID
+#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8805_FORCE_DID
+#define CONFIG_USB_PD_TCPM_PS8805_FORCE_DID
+#endif
+
+#undef CONFIG_USB_PD_TCPM_PS8815
+#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8815
+#define CONFIG_USB_PD_TCPM_PS8815
+#endif
+
+#undef CONFIG_USB_PD_TCPM_PS8815_FORCE_DID
+#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8815_FORCE_DID
+#define CONFIG_USB_PD_TCPM_PS8815_FORCE_DID
+#endif
+
+#undef CONFIG_USB_PD_TCPM_MULTI_PS8XXX
+#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_MULTI_PS8XXX
+#define CONFIG_USB_PD_TCPM_MULTI_PS8XXX
+#endif
+
+#undef CONFIG_USB_PD_TCPM_RT1715
+#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_RT1715
+#define CONFIG_USB_PD_TCPM_RT1715
+#endif
+
+#undef CONFIG_USB_PD_TCPM_RT1718S
+#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_RT1718S
+#define CONFIG_USB_PD_TCPM_RT1718S
+#endif
+
+#undef CONFIG_USB_PD_TCPM_TUSB422
+#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_TUSB422
+#define CONFIG_USB_PD_TCPM_TUSB422
+#endif
+
+#undef CONFIG_USB_PD_TCPM_TCPCI
+#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_TCPCI
+#define CONFIG_USB_PD_TCPM_TCPCI
+#endif
+
+#undef CONFIG_USB_PD_TCPM_ITE_ON_CHIP
+#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_ITE_ON_CHIP
+#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP
+
+#define IT83XX_USBPD_PHY_PORT_COUNT \
+	COND_CODE_1(DT_NODE_EXISTS(DT_INST(1, ite_it8xxx2_usbpd)), (2), (1))
+
+#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT \
+	DT_NUM_INST_STATUS_OKAY(ite_it8xxx2_usbpd)
+#endif
+
+#undef CONFIG_USB_PD_TCPM_DRIVER_IT8XXX2
+#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_DRIVER_IT8XXX2
+#define CONFIG_USB_PD_TCPM_DRIVER_IT8XXX2
+#if defined(CONFIG_SOC_IT81202_CX) || defined(CONFIG_SOC_IT81302_CX)
+/* CCGCR 04h bit[3,2,1] Rp 3A value is changed to 000b. */
+#define IT8XXX2_USBPD_RP_3A0_VALUE_IS_ZERO
+/*
+ * CCGCR 04h bit[7] is reserved, so we control the power of cc analog module
+ * by CCCSR 05h bit[7,3].
+ */
+#define IT8XXX2_USBPD_CCGCR_BIT7_RESERVED
+#else
+/* Individual setting CC1 and CC2 resistance. */
+#define IT83XX_USBPD_CC1_CC2_RESISTANCE_SEPARATE
+#endif
+#endif
+
+#undef CONFIG_USB_PD_TCPM_DRIVER_IT83XX
+#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_DRIVER_IT83XX
+#define CONFIG_USB_PD_TCPM_DRIVER_IT83XX
+#endif
+
+#undef CONFIG_IT83XX_TUNE_CC_PHY
+#ifdef CONFIG_PLATFORM_EC_IT83XX_TUNE_CC_PHY
+#define CONFIG_IT83XX_TUNE_CC_PHY
+#endif
+
+#undef CONFIG_USB_PD_TCPM_RAA489000
+#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_RAA489000
+#define CONFIG_USB_PD_TCPM_RAA489000
+#endif
+
+#undef CONFIG_USB_PD_TCPM_ANX7447
+#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_ANX7447
+#define CONFIG_USB_PD_TCPM_ANX7447
+#endif
+
+#undef CONFIG_USB_PD_TCPM_ANX7447_AUX_PU_PD
+#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_ANX7447_AUX_PU_PD
+#define CONFIG_USB_PD_TCPM_ANX7447_AUX_PU_PD
+#endif
+
+#undef CONFIG_USB_PD_TCPM_ANX7447_OCM_ERASE_COMMAND
+#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_ANX7447_OCM_ERASE_COMMAND
+#define CONFIG_USB_PD_TCPM_ANX7447_OCM_ERASE_COMMAND
+#endif
+
+#undef CONFIG_USB_PD_PORT_MAX_COUNT
+#define CONFIG_USB_PD_PORT_MAX_COUNT DT_NUM_INST_STATUS_OKAY(named_usbc_port)
+
+#ifdef CONFIG_PLATFORM_EC_USB_POWER_DELIVERY
+/* USBC-PD Port 0 */
+#if CONFIG_USB_PD_PORT_MAX_COUNT > 0
+#define HAS_TASK_PD_C0 1
+
+#ifndef CONFIG_PLATFORM_EC_USB_PD_PORT_0_SHARED
+#define HAS_TASK_PD_INT_C0 1
+#endif /* !CONFIG_PLATFORM_EC_USB_PD_PORT_0_SHARED */
+
+#endif /* CONFIG_USB_PD_PORT_MAX_COUNT > 0 */
+
+/* USBC-PD Port 1 */
+#if CONFIG_USB_PD_PORT_MAX_COUNT > 1
+#define HAS_TASK_PD_C1 1
+
+#ifndef CONFIG_PLATFORM_EC_USB_PD_PORT_1_SHARED
+#define HAS_TASK_PD_INT_C1 1
+#endif /* !CONFIG_PLATFORM_EC_USB_PD_PORT_1_SHARED */
+
+#endif /* CONFIG_USB_PD_PORT_MAX_COUNT > 1 */
+
+/* USBC-PD Port 2 */
+#if CONFIG_USB_PD_PORT_MAX_COUNT > 2
+#define HAS_TASK_PD_C2 1
+
+#ifndef CONFIG_PLATFORM_EC_USB_PD_PORT_2_SHARED
+#define HAS_TASK_PD_INT_C2 1
+#endif /* !CONFIG_PLATFORM_EC_USB_PD_PORT_2_SHARED */
+
+#endif /* CONFIG_USB_PD_PORT_MAX_COUNT > 2 */
+
+/* USBC-PD Port 3 */
+#if CONFIG_USB_PD_PORT_MAX_COUNT > 3
+#define HAS_TASK_PD_C3 1
+
+#ifndef CONFIG_PLATFORM_EC_USB_PD_PORT_3_SHARED
+#define HAS_TASK_PD_INT_C3 1
+#endif /* !CONFIG_PLATFORM_EC_USB_PD_PORT_3_SHARED */
+
+#endif /* CONFIG_USB_PD_PORT_MAX_COUNT > 3 */
+
+#endif /* CONFIG_PLATFORM_EC_USB_POWER_DELIVERY */
+
+/* Remove PD_INT_C* task for ports managed by ITE embedded TCPC */
+#ifdef CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT
+#if CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT >= 1
+#undef HAS_TASK_PD_INT_C0
+#endif
+#if CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT >= 2
+#undef HAS_TASK_PD_INT_C1
+#endif
+#if CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT >= 3
+#undef HAS_TASK_PD_INT_C2
+#endif
+#if CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT >= 4
+#undef HAS_TASK_PD_INT_C3
+#endif
+#endif /* CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT */
+
+#undef CONFIG_USB_PD_PPC
+#ifdef CONFIG_PLATFORM_EC_USB_PD_PPC
+#define CONFIG_USB_PD_PPC
+#endif
+
+#undef CONFIG_USBC_PPC
+#ifdef CONFIG_PLATFORM_EC_USBC_PPC
+#define CONFIG_USBC_PPC
+#endif
+
+#undef CONFIG_USBC_PPC_AOZ1380
+#ifdef CONFIG_PLATFORM_EC_USBC_PPC_AOZ1380
+#define CONFIG_USBC_PPC_AOZ1380
+#endif
+
+#undef CONFIG_USBC_PPC_KTU1125
+#ifdef CONFIG_PLATFORM_EC_USBC_PPC_KTU1125
+#define CONFIG_USBC_PPC_KTU1125
+#endif
+
+#undef CONFIG_USBC_PPC_NX20P3481
+#ifdef CONFIG_PLATFORM_EC_USBC_PPC_NX20P3481
+#define CONFIG_USBC_PPC_NX20P3481
+#endif
+
+#undef CONFIG_USBC_PPC_NX20P3483
+#ifdef CONFIG_PLATFORM_EC_USBC_PPC_NX20P3483
+#define CONFIG_USBC_PPC_NX20P3483
+#endif
+
+#undef CONFIG_USBC_NX20P348X_RCP_5VSRC_MASK_ENABLE
+#ifdef CONFIG_PLATFORM_EC_USBC_NX20P348X_RCP_5VSRC_MASK_ENABLE
+#define CONFIG_USBC_NX20P348X_RCP_5VSRC_MASK_ENABLE
+#endif
+
+#undef CONFIG_USBC_PPC_RT1718S
+#ifdef CONFIG_PLATFORM_EC_USBC_PPC_RT1718S
+#define CONFIG_USBC_PPC_RT1718S
+#endif
+
+#undef CONFIG_USBC_PPC_SN5S330
+#ifdef CONFIG_PLATFORM_EC_USBC_PPC_SN5S330
+#define CONFIG_USBC_PPC_SN5S330
+#endif
+
+#undef CONFIG_USBC_PPC_SYV682X
+#ifdef CONFIG_PLATFORM_EC_USBC_PPC_SYV682X
+#define CONFIG_USBC_PPC_SYV682X
+#endif
+
+#undef CONFIG_USBC_PPC_SYV682C
+#ifdef CONFIG_PLATFORM_EC_USBC_PPC_SYV682C
+#define CONFIG_USBC_PPC_SYV682C
+#endif
+
+#undef CONFIG_SYV682X_HV_ILIM
+#define CONFIG_SYV682X_HV_ILIM CONFIG_PLATFORM_EC_USBC_PPC_SYV682X_HV_ILIM
+
+#undef CONFIG_USBC_PPC_SYV682X_NO_CC
+#ifdef CONFIG_PLATFORM_EC_USBC_PPC_SYV682X_NO_CC
+#define CONFIG_USBC_PPC_SYV682X_NO_CC
+#endif
+
+#undef CONFIG_USBC_PPC_SYV682X_SMART_DISCHARGE
+#ifdef CONFIG_PLATFORM_EC_USBC_PPC_SYV682X_SMART_DISCHARGE
+#define CONFIG_USBC_PPC_SYV682X_SMART_DISCHARGE
+#endif
+
+#undef CONFIG_USB_PD_TCPC_RUNTIME_CONFIG
+#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPC_RUNTIME_CONFIG
+#define CONFIG_USB_PD_TCPC_RUNTIME_CONFIG
+#endif
+
+#undef CONFIG_USB_MUX_RUNTIME_CONFIG
+#ifdef CONFIG_PLATFORM_EC_USB_MUX_RUNTIME_CONFIG
+#define CONFIG_USB_MUX_RUNTIME_CONFIG
+#endif
+
+#undef CONFIG_USB_PD_ALT_MODE
+#ifdef CONFIG_PLATFORM_EC_USB_PD_ALT_MODE
+#define CONFIG_USB_PD_ALT_MODE
+#endif
+
+#undef CONFIG_USB_PD_ALT_MODE_DFP
+#ifdef CONFIG_PLATFORM_EC_USB_PD_ALT_MODE_DFP
+#define CONFIG_USB_PD_ALT_MODE_DFP
+#endif
+
+#undef CONFIG_USB_PD_ALT_MODE_UFP
+#ifdef CONFIG_PLATFORM_EC_USB_PD_ALT_MODE_UFP
+#define CONFIG_USB_PD_ALT_MODE_UFP
+#endif
+
+#undef CONFIG_USB_PD_DISCOVERY
+#ifdef CONFIG_PLATFORM_EC_USB_PD_DISCOVERY
+#define CONFIG_USB_PD_DISCOVERY
+#endif
+
+#undef CONFIG_USB_PD_DPS
+#ifdef CONFIG_PLATFORM_EC_USB_PD_DPS
+#define CONFIG_USB_PD_DPS
+#endif
+
+#undef CONFIG_DP_REDRIVER_TDP142
+#ifdef CONFIG_PLATFORM_EC_DP_REDRIVER_TDP142
+#define CONFIG_DP_REDRIVER_TDP142
+#endif
+
+#undef CONFIG_USBC_RETIMER_FW_UPDATE
+#ifdef CONFIG_PLATFORM_EC_USBC_RETIMER_FW_UPDATE
+#define CONFIG_USBC_RETIMER_FW_UPDATE
+#endif
+
+#undef CONFIG_USBC_RETIMER_INTEL_BB
+#ifdef CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_BB
+#define CONFIG_USBC_RETIMER_INTEL_BB
+#endif
+
+#undef CONFIG_USBC_RETIMER_INTEL_HB
+#ifdef CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_HB
+
+#define USBC_PORT_C0_HB_RETIMER_I2C_ADDR \
+	DT_REG_ADDR(DT_NODELABEL(usb_c0_hb_retimer))
+#define USBC_PORT_C1_HB_RETIMER_I2C_ADDR \
+	DT_REG_ADDR(DT_NODELABEL(usb_c1_hb_retimer))
+#define USBC_PORT_C2_HB_RETIMER_I2C_ADDR \
+	DT_REG_ADDR(DT_NODELABEL(usb_c2_hb_retimer))
+#define USBC_PORT_C3_HB_RETIMER_I2C_ADDR \
+	DT_REG_ADDR(DT_NODELABEL(usb_c3_hb_retimer))
+#define CONFIG_USBC_RETIMER_INTEL_HB
+#endif
+
+#undef CONFIG_USBC_RETIMER_INTEL_BB_RUNTIME_CONFIG
+#ifdef CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_BB_RUNTIME_CONFIG
+#define CONFIG_USBC_RETIMER_INTEL_BB_RUNTIME_CONFIG
+#endif
+
+#undef CONFIG_USBC_RETIMER_INTEL_BB_VPRO_CAPABLE
+#ifdef CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_BB_VPRO_CAPABLE
+#define CONFIG_USBC_RETIMER_INTEL_BB_VPRO_CAPABLE
+#endif
+
+#undef CONFIG_USBC_RETIMER_ANX7451
+#ifdef CONFIG_PLATFORM_EC_USBC_RETIMER_ANX7451
+#define CONFIG_USBC_RETIMER_ANX7451
+#endif
+
+#undef CONFIG_USBC_RETIMER_ANX7483
+#ifdef CONFIG_PLATFORM_EC_USBC_RETIMER_ANX7483
+#define CONFIG_USBC_RETIMER_ANX7483
+#endif
+
+#undef CONFIG_USBC_RETIMER_ANX7452
+#ifdef CONFIG_PLATFORM_EC_USBC_RETIMER_ANX7452
+#define CONFIG_USBC_RETIMER_ANX7452
+#endif
+
+#undef CONFIG_USBC_RETIMER_KB8010
+#ifdef CONFIG_PLATFORM_EC_USBC_RETIMER_KB8010
+#define CONFIG_USBC_RETIMER_KB8010
+#endif
+
+#undef CONFIG_USBC_RETIMER_KB800X
+#ifdef CONFIG_PLATFORM_EC_USBC_RETIMER_KB800X
+#define CONFIG_USBC_RETIMER_KB800X
+#endif
+
+#undef CONFIG_USBC_RETIMER_PS8811
+#ifdef CONFIG_PLATFORM_EC_USBC_RETIMER_PS8811
+#define CONFIG_USBC_RETIMER_PS8811
+#endif
+
+#undef CONFIG_USBC_RETIMER_PS8818
+#ifdef CONFIG_PLATFORM_EC_USBC_RETIMER_PS8818
+#define CONFIG_USBC_RETIMER_PS8818
+#endif
+
+#undef CONFIG_CMD_RETIMER
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_RETIMER
+#define CONFIG_CMD_RETIMER
+#endif
+
+#undef CONFIG_USBC_SS_MUX
+#ifdef CONFIG_PLATFORM_EC_USBC_SS_MUX
+#define CONFIG_USBC_SS_MUX
+#endif
+
+#undef CONFIG_USBC_SS_MUX_DFP_ONLY
+#ifdef CONFIG_PLATFORM_EC_USBC_SS_MUX_DFP_ONLY
+#define CONFIG_USBC_SS_MUX_DFP_ONLY
+#endif
+
+#undef CONFIG_USB_MUX_AP_CONTROL
+#ifdef CONFIG_PLATFORM_EC_USB_MUX_AP_CONTROL
+#define CONFIG_USB_MUX_AP_CONTROL
+#endif
+
+#undef CONFIG_USB_MUX_AMD_FP6
+#ifdef CONFIG_PLATFORM_EC_USB_MUX_AMD_FP6
+#define CONFIG_USB_MUX_AMD_FP6
+#endif
+
+#undef CONFIG_USB_MUX_IT5205
+#ifdef CONFIG_PLATFORM_EC_USB_MUX_IT5205
+#define CONFIG_USB_MUX_IT5205
+#endif
+
+#undef CONFIG_USB_MUX_PS8743
+#ifdef CONFIG_PLATFORM_EC_USB_MUX_PS8743
+#define CONFIG_USB_MUX_PS8743
+#endif
+
+#undef CONFIG_USB_MUX_TUSB546
+#ifdef CONFIG_PLATFORM_EC_USB_MUX_TUSB546
+#define CONFIG_USB_MUX_TUSB546
+#endif
+
+#undef CONFIG_USB_MUX_TUSB1044
+#ifdef CONFIG_PLATFORM_EC_USB_MUX_TUSB1044
+#define CONFIG_USB_MUX_TUSB1044
+#endif
+
+#undef CONFIG_USB_MUX_TUSB1064
+#ifdef CONFIG_PLATFORM_EC_USB_MUX_TUSB1064
+#define CONFIG_USB_MUX_TUSB1064
+#endif
+
+#undef CONFIG_USB_MUX_VIRTUAL
+#ifdef CONFIG_PLATFORM_EC_USB_MUX_VIRTUAL
+#define CONFIG_USB_MUX_VIRTUAL
+#endif
+
+#undef CONFIG_USB_PD_TCPM_MUX
+#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_MUX
+#define CONFIG_USB_PD_TCPM_MUX
+#endif
+
+#undef CONFIG_USB_PD_TCPM_SBU
+#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_SBU
+#define CONFIG_USB_PD_TCPM_SBU
+#endif
+
+#undef CONFIG_USBC_PPC_DEDICATED_INT
+#ifdef CONFIG_PLATFORM_EC_USBC_PPC_DEDICATED_INT
+#define CONFIG_USBC_PPC_DEDICATED_INT
+#endif
+
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_PD
+#define CONFIG_CONSOLE_CMD_PD
+#endif
+
+#ifdef CONFIG_HAS_TASK_PD_INT_C0
+/* This must be defined if any task is active */
+#define CONFIG_HAS_TASK_PD_INT
+#endif
+
+#undef CONFIG_MKBP_EVENT
+#ifdef CONFIG_PLATFORM_EC_MKBP_EVENT
+#define CONFIG_MKBP_EVENT
+#endif
+
+#undef CONFIG_MKBP_USE_GPIO
+#ifdef CONFIG_PLATFORM_EC_MKBP_USE_GPIO
+#define CONFIG_MKBP_USE_GPIO
+#endif
+
+#undef CONFIG_MKBP_USE_HOST_EVENT
+#ifdef CONFIG_PLATFORM_EC_MKBP_USE_HOST_EVENT
+#define CONFIG_MKBP_USE_HOST_EVENT
+#endif
+
+#undef CONFIG_MKBP_USE_HECI
+#ifdef CONFIG_PLATFORM_EC_MKBP_USE_HECI
+#define CONFIG_MKBP_USE_HECI
+#endif
+
+#undef CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT
+#ifdef CONFIG_PLATFORM_EC_MKBP_USE_GPIO_AND_HOST_EVENT
+#define CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT
+#endif
+
+#undef CONFIG_MKBP_USE_CUSTOM
+#ifdef CONFIG_PLATFORM_EC_MKBP_USE_CUSTOM
+#define CONFIG_MKBP_USE_CUSTOM
+#endif
+
+#undef CONFIG_MKBP_USE_GPIO_ACTIVE_HIGH
+#ifdef CONFIG_PLATFORM_EC_MKBP_USE_GPIO_ACTIVE_HIGH
+#define CONFIG_MKBP_USE_GPIO_ACTIVE_HIGH
+#endif
+
+#undef CONFIG_USB_PD_TCPC_LOW_POWER
+#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
+#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPC_LOW_POWER
+#define CONFIG_USB_PD_TCPC_LOW_POWER
+#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE \
+	CONFIG_PLATFORM_EC_USB_PD_TCPC_LPM_EXIT_DEBOUNCE_US
+#endif /* CONFIG_PLATFORM_EC_USB_PD_TCPC_LOW_POWER */
+
+#undef CONFIG_USB_PD_DEBUG_LEVEL
+#ifdef CONFIG_PLATFORM_EC_USB_PD_DEBUG_FIXED_LEVEL
+#define CONFIG_USB_PD_DEBUG_LEVEL CONFIG_PLATFORM_EC_USB_PD_DEBUG_LEVEL
+#endif
+
+#undef CONFIG_USB_PD_INITIAL_DEBUG_LEVEL
+#ifdef CONFIG_PLATFORM_EC_USB_PD_INITIAL_DEBUG_LEVEL
+#define CONFIG_USB_PD_INITIAL_DEBUG_LEVEL \
+	CONFIG_PLATFORM_EC_USB_PD_INITIAL_DEBUG_LEVEL
+#endif
+
+#undef CONFIG_USB_PD_FLAGS
+#ifdef CONFIG_PLATFORM_EC_USB_PD_FLAGS
+#define CONFIG_USB_PD_FLAGS
+#endif
+
+#undef CONFIG_USB_PD_RUNTIME_FLAGS
+#ifdef CONFIG_PLATFORM_EC_USB_PD_RUNTIME_FLAGS
+#define CONFIG_USB_PD_RUNTIME_FLAGS
+#endif
+
+#undef CONFIG_USB_PD_STARTUP_DELAY_MS
+#ifdef CONFIG_PLATFORM_EC_USB_PD_STARTUP_DELAY_MS
+#define CONFIG_USB_PD_STARTUP_DELAY_MS \
+	CONFIG_PLATFORM_EC_USB_PD_STARTUP_DELAY_MS
+#endif
+
+#undef CONFIG_USB_PD_3A_PORTS
+#ifdef CONFIG_PLATFORM_EC_CONFIG_USB_PD_3A_PORTS
+#define CONFIG_USB_PD_3A_PORTS CONFIG_PLATFORM_EC_CONFIG_USB_PD_3A_PORTS
+#endif
+
+#undef CONFIG_USB_PD_TEMP_SENSOR
+#ifdef CONFIG_PLATFORM_EC_USB_PD_TEMP_SENSOR
+#define CONFIG_USB_PD_TEMP_SENSOR CONFIG_PLATFORM_EC_USB_PD_TEMP_SENSOR
+#endif
+
+#undef CONFIG_USB_PD_SHORT_PRESS_MAX_MS
+#ifdef CONFIG_PLATFORM_EC_USB_PD_SHORT_PRESS_MAX_MS
+#define CONFIG_USB_PD_SHORT_PRESS_MAX_MS \
+	CONFIG_PLATFORM_EC_USB_PD_SHORT_PRESS_MAX_MS
+#endif
+
+#undef CONFIG_USB_PD_LONG_PRESS_MAX_MS
+#ifdef CONFIG_PLATFORM_EC_USB_PD_LONG_PRESS_MAX_MS
+#define CONFIG_USB_PD_LONG_PRESS_MAX_MS \
+	CONFIG_PLATFORM_EC_USB_PD_LONG_PRESS_MAX_MS
+#endif
+
+#undef CONFIG_USBC_VCONN
+#ifdef CONFIG_PLATFORM_EC_USBC_VCONN
+#define CONFIG_USBC_VCONN
+#endif
+
+#undef CONFIG_USBC_VCONN_SWAP
+#ifdef CONFIG_PLATFORM_EC_USBC_VCONN_SWAP
+#define CONFIG_USBC_VCONN_SWAP
+#endif
+
+#undef CONFIG_USB_PD_TRY_SRC
+#ifdef CONFIG_PLATFORM_EC_USB_PD_TRY_SRC
+#define CONFIG_USB_PD_TRY_SRC
+#endif
+
+#undef CONFIG_USBC_PPC_POLARITY
+#ifdef CONFIG_PLATFORM_EC_USBC_PPC_POLARITY
+#define CONFIG_USBC_PPC_POLARITY
+#endif
+
+#undef CONFIG_USBC_PPC_SBU
+#ifdef CONFIG_PLATFORM_EC_USBC_PPC_SBU
+#define CONFIG_USBC_PPC_SBU
+#endif
+
+#undef CONFIG_USBC_PPC_VCONN
+#ifdef CONFIG_PLATFORM_EC_USBC_PPC_VCONN
+#define CONFIG_USBC_PPC_VCONN
+#endif
+
+#undef CONFIG_USB_PD_USB32_DRD
+#ifdef CONFIG_PLATFORM_EC_USB_PD_USB32_DRD
+#define CONFIG_USB_PD_USB32_DRD
+#endif
+
+#undef CONFIG_HOSTCMD_PD_CONTROL
+#ifdef CONFIG_PLATFORM_EC_HOSTCMD_PD_CONTROL
+#define CONFIG_HOSTCMD_PD_CONTROL
+#endif
+
+#undef CONFIG_CMD_HCDEBUG
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_HCDEBUG
+#define CONFIG_CMD_HCDEBUG
+#endif
+
+#undef CONFIG_CMD_POWERINDEBUG
+#ifdef CONFIG_PLATFORM_EC_CMD_POWERINDEBUG
+#define CONFIG_CMD_POWERINDEBUG
+#endif
+
+#undef CONFIG_CMD_USB_PD_PE
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_USB_PD_PE
+#define CONFIG_CMD_USB_PD_PE
+#endif
+
+#undef CONFIG_CMD_USB_PD_CABLE
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_USB_PD_CABLE
+#define CONFIG_CMD_USB_PD_CABLE
+#endif
+
+#undef CONFIG_USB_PD_DP_MODE
+#ifdef CONFIG_PLATFORM_EC_USB_PD_DP_MODE
+#define CONFIG_USB_PD_DP_MODE
+#endif
+
+#undef CONFIG_USB_PD_TBT_COMPAT_MODE
+#ifdef CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE
+#define CONFIG_USB_PD_TBT_COMPAT_MODE
+#endif
+
+#undef CONFIG_USB_PD_USB4
+#ifdef CONFIG_PLATFORM_EC_USB_PD_USB4
+#define CONFIG_USB_PD_USB4
+#endif
+
+#undef CONFIG_USB_PD_DATA_RESET_MSG
+#ifdef CONFIG_PLATFORM_EC_USB_PD_DATA_RESET_MSG
+#define CONFIG_USB_PD_DATA_RESET_MSG
+#endif
+
+#undef CONFIG_USB_PD_FRS
+#ifdef CONFIG_PLATFORM_EC_USB_PD_FRS
+#define CONFIG_USB_PD_FRS
+#endif
+
+#undef CONFIG_USB_PD_FRS_TCPC
+#ifdef CONFIG_PLATFORM_EC_USB_PD_FRS_TCPC
+#define CONFIG_USB_PD_FRS_TCPC
+#endif
+
+#undef CONFIG_USB_PD_FRS_PPC
+#ifdef CONFIG_PLATFORM_EC_USB_PD_FRS_PPC
+#define CONFIG_USB_PD_FRS_PPC
+#endif
+
+#undef CONFIG_VSTORE
+#undef VSTORE_SLOT_COUNT
+#ifdef CONFIG_PLATFORM_EC_VSTORE
+#define CONFIG_VSTORE
+#define CONFIG_VSTORE_SLOT_COUNT CONFIG_PLATFORM_EC_VSTORE_SLOT_COUNT
+#endif
+
+#undef CONFIG_LID_SWITCH
+#ifdef CONFIG_PLATFORM_EC_LID_SWITCH
+#define CONFIG_LID_SWITCH
+#endif
+
+/* motion sense */
+#undef CONFIG_MOTIONSENSE
+#ifdef CONFIG_PLATFORM_EC_MOTIONSENSE
+#define CONFIG_MOTIONSENSE
+#endif
+
+#undef CONFIG_ACCEL_FIFO
+#undef CONFIG_ACCEL_FIFO_SIZE
+#undef CONFIG_ACCEL_FIFO_THRES
+#ifdef CONFIG_PLATFORM_EC_ACCEL_FIFO
+#define CONFIG_ACCEL_FIFO
+#define CONFIG_ACCEL_FIFO_SIZE CONFIG_PLATFORM_EC_ACCEL_FIFO_SIZE
+#define CONFIG_ACCEL_FIFO_THRES CONFIG_PLATFORM_EC_ACCEL_FIFO_THRES
+#endif /* CONFIG_PLATFORM_EC_ACCEL_FIFO */
+
+#undef CONFIG_BODY_DETECTION
+#undef CONFIG_BODY_DETECTION_SENSOR
+#undef CONFIG_BODY_DETECTION_MAX_WINDOW_SIZE
+#undef CONFIG_BODY_DETECTION_VAR_THRESHOLD
+#undef CONFIG_BODY_DETECTION_CONFIDENCE_DELTA
+#undef CONFIG_BODY_DETECTION_VAR_NOISE_FACTOR
+#undef CONFIG_BODY_DETECTION_ON_BODY_CON
+#undef CONFIG_BODY_DETECTION_OFF_BODY_CON
+#undef CONFIG_BODY_DETECTION_STATIONARY_DURATION
+#undef CONFIG_BODY_DETECTION_NOTIFY_MODE_CHANGE
+#undef CONFIG_BODY_DETECTION_ALWAYS_ENABLE_IN_S0
+#ifdef CONFIG_PLATFORM_EC_BODY_DETECTION
+#define CONFIG_BODY_DETECTION
+#define CONFIG_BODY_DETECTION_SENSOR SENSOR_ID(DT_ALIAS(on_body_sensor))
+#define CONFIG_BODY_DETECTION_MAX_WINDOW_SIZE \
+	CONFIG_PLATFORM_EC_BODY_DETECTION_MAX_WINDOW_SIZE
+#define CONFIG_BODY_DETECTION_VAR_THRESHOLD \
+	CONFIG_PLATFORM_EC_BODY_DETECTION_VAR_THRESHOLD
+#define CONFIG_BODY_DETECTION_CONFIDENCE_DELTA \
+	CONFIG_PLATFORM_EC_BODY_DETECTION_CONFIDENCE_DELTA
+#define CONFIG_BODY_DETECTION_VAR_NOISE_FACTOR \
+	CONFIG_PLATFORM_EC_BODY_DETECTION_VAR_NOISE_FACTOR
+#define CONFIG_BODY_DETECTION_ON_BODY_CON \
+	CONFIG_PLATFORM_EC_BODY_DETECTION_ON_BODY_CON
+#define CONFIG_BODY_DETECTION_OFF_BODY_CON \
+	CONFIG_PLATFORM_EC_BODY_DETECTION_OFF_BODY_CON
+#define CONFIG_BODY_DETECTION_STATIONARY_DURATION \
+	CONFIG_PLATFORM_EC_BODY_DETECTION_STATIONARY_DURATION
+#ifdef CONFIG_PLATFORM_EC_BODY_DETECTION_NOTIFY_MODE_CHANGE
+#define CONFIG_BODY_DETECTION_NOTIFY_MODE_CHANGE
+#endif /* CONFIG_PLATFORM_EC_BODY_DETECTION_NOTIFY_MODE_CHANGE */
+#ifdef CONFIG_PLATFORM_EC_BODY_DETECTION_NOTIFY_MKBP
+#define CONFIG_BODY_DETECTION_NOTIFY_MKBP
+#endif /* CONFIG_PLATFORM_EC_BODY_DETECTION_NOTIFY_MKBP */
+#ifdef CONFIG_PLATFORM_EC_BODY_DETECTION_ALWAYS_ENABLE_IN_S0
+#define CONFIG_BODY_DETECTION_ALWAYS_ENABLE_IN_S0
+#endif
+#endif /* CONFIG_PLATFORM_EC_BODY_DETECTION */
+
+#undef CONFIG_CMD_ACCELS
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS
+#define CONFIG_CMD_ACCELS
+#endif
+
+#undef CONFIG_CMD_ACCEL_INFO
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO
+#define CONFIG_CMD_ACCEL_INFO
+#endif
+
+#undef CONFIG_ACCEL_SPOOF_MODE
+#ifdef CONFIG_PLATFORM_EC_ACCEL_SPOOF_MODE
+#define CONFIG_ACCEL_SPOOF_MODE
+#endif
+
+#undef CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ
+#ifdef CONFIG_PLATFORM_EC_MAX_SENSOR_FREQ_MILLIHZ
+#define CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ \
+	CONFIG_PLATFORM_EC_MAX_SENSOR_FREQ_MILLIHZ
+#endif
+
+#undef CONFIG_CMD_ACCEL_SPOOF
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_SPOOF
+#define CONFIG_CMD_ACCEL_SPOOF
+#endif
+
+#undef CONFIG_GESTURE_DETECTION
+#undef CONFIG_GESTURE_DETECTION_MASK
+#ifdef CONFIG_PLATFORM_EC_GESTURE_DETECTION
+#define CONFIG_GESTURE_DETECTION
+#define CONFIG_GESTURE_DETECTION_MASK BIT(CONFIG_BODY_DETECTION_SENSOR)
+#endif
+
+#undef CONFIG_GESTURE_HOST_DETECTION
+#ifdef CONFIG_PLATFORM_EC_GESTURE_HOST_DETECTION
+#define CONFIG_GESTURE_HOST_DETECTION
+#endif
+
+#undef CONFIG_SENSOR_TIGHT_TIMESTAMPS
+#ifdef CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS
+#define CONFIG_SENSOR_TIGHT_TIMESTAMPS
+#endif
+
+#undef CONFIG_ALS
+#undef CONFIG_ALS_COUNT
+#if DT_NODE_HAS_PROP(SENSOR_INFO_NODE, als_sensors)
+#define CONFIG_ALS
+#define ALS_COUNT DT_PROP_LEN(SENSOR_INFO_NODE, als_sensors)
+#elif CONFIG_PLATFORM_EC_DEDICATED_ALS
+#define CONFIG_ALS
+#else
+#define ALS_COUNT 0
+#endif
+
+#undef CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
+#ifdef CONFIG_PLATFORM_EC_DYNAMIC_MOTION_SENSOR_COUNT
+#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
+#endif
+
+#undef CONFIG_LID_ANGLE
+#ifdef CONFIG_PLATFORM_EC_LID_ANGLE
+#define CONFIG_LID_ANGLE
+#endif
+
+#undef CONFIG_LID_ANGLE_UPDATE
+#ifdef CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE
+#define CONFIG_LID_ANGLE_UPDATE
+#endif
+
+#undef CONFIG_TABLET_MODE
+#ifdef CONFIG_PLATFORM_EC_TABLET_MODE
+#define CONFIG_TABLET_MODE
+#endif
+
+#undef CONFIG_TABLET_MODE_SWITCH
+#ifdef CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH
+#define CONFIG_TABLET_MODE_SWITCH
+#endif
+
+#undef CONFIG_GMR_TABLET_MODE
+#ifdef CONFIG_PLATFORM_EC_GMR_TABLET_MODE
+#define CONFIG_GMR_TABLET_MODE
+#endif
+
+/* sensors */
+#undef CONFIG_ACCELGYRO_BMI160
+#ifdef CONFIG_PLATFORM_EC_ACCELGYRO_BMI160
+#define CONFIG_ACCELGYRO_BMI160
+#endif
+
+#undef CONFIG_ACCELGYRO_BMI260
+#ifdef CONFIG_PLATFORM_EC_ACCELGYRO_BMI260
+#define CONFIG_ACCELGYRO_BMI260
+#endif
+
+#undef CONFIG_ACCELGYRO_BMI3XX
+#ifdef CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX
+#define CONFIG_ACCELGYRO_BMI3XX
+#endif
+
+#undef CONFIG_ACCEL_BMA255
+#ifdef CONFIG_PLATFORM_EC_ACCEL_BMA255
+#define CONFIG_ACCEL_BMA255
+#endif
+
+#undef CONFIG_ACCEL_BMA4XX
+#ifdef CONFIG_PLATFORM_EC_ACCEL_BMA4XX
+#define CONFIG_ACCEL_BMA4XX
+#endif
+
+#undef CONFIG_ACCEL_KX022
+#ifdef CONFIG_PLATFORM_EC_ACCEL_KX022
+#define CONFIG_ACCEL_KX022
+#endif
+
+#undef CONFIG_ALS_TCS3400_EMULATED_IRQ_EVENT
+#ifdef CONFIG_PLATFORM_EC_ALS_TCS3400_EMULATED_IRQ_EVENT
+#define CONFIG_ALS_TCS3400_EMULATED_IRQ_EVENT
+#endif
+
+#undef CONFIG_ALS_TCS3400
+#ifdef CONFIG_PLATFORM_EC_ALS_TCS3400
+#define CONFIG_ALS_TCS3400
+#endif
+
+#undef CONFIG_ALS_CM32183
+#ifdef CONFIG_PLATFORM_EC_ALS_CM32183
+#define CONFIG_ALS_CM32183
+#endif
+
+#undef CONFIG_ACCELGYRO_ICM426XX
+#ifdef CONFIG_PLATFORM_EC_ACCELGYRO_ICM426XX
+#define CONFIG_ACCELGYRO_ICM426XX
+#endif
+
+#undef CONFIG_ACCELGYRO_ICM42607
+#ifdef CONFIG_PLATFORM_EC_ACCELGYRO_ICM42607
+#define CONFIG_ACCELGYRO_ICM42607
+#endif
+
+#undef CONFIG_ACCELGYRO_LSM6DSO
+#ifdef CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSO
+#define CONFIG_ACCELGYRO_LSM6DSO
+#endif
+
+#undef CONFIG_ACCELGYRO_LSM6DSM
+#ifdef CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSM
+#define CONFIG_ACCELGYRO_LSM6DSM
+#endif
+
+#undef CONFIG_MATH_UTIL
+#ifdef CONFIG_PLATFORM_EC_MATH_UTIL
+#define CONFIG_MATH_UTIL
+#endif
+
+#undef CONFIG_MAX695X_SEVEN_SEGMENT_DISPLAY
+#ifdef CONFIG_PLATFORM_EC_MAX695X_SEVEN_SEGMENT_DISPLAY
+#define CONFIG_MAX695X_SEVEN_SEGMENT_DISPLAY
+#define PORT80_I2C_ADDR \
+	DT_REG_ADDR(DT_COMPAT_GET_ANY_STATUS_OKAY(maxim_max695x))
+BUILD_ASSERT((DT_NUM_INST_STATUS_OKAY(maxim_max695x)) == 1,
+	     "Only one instance of maxim,max695x should be defined");
+#endif
+
+#undef CONFIG_CMD_SEVEN_SEG_DISPLAY
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_SEVEN_SEGMENT_DISPLAY
+#define CONFIG_CMD_SEVEN_SEG_DISPLAY
+#endif
+
+#undef CONFIG_HOSTCMD_GET_UPTIME_INFO
+#ifdef CONFIG_PLATFORM_EC_HOSTCMD_GET_UPTIME_INFO
+#define CONFIG_HOSTCMD_GET_UPTIME_INFO
+#endif
+
+#undef CONFIG_CMD_AP_RESET_LOG
+#ifdef CONFIG_PLATFORM_EC_AP_RESET_LOG
+#define CONFIG_CMD_AP_RESET_LOG
+#endif
+
+#undef CONFIG_POWER_BUTTON
+#ifdef CONFIG_PLATFORM_EC_POWER_BUTTON
+#define CONFIG_POWER_BUTTON
+#endif
+
+#undef CONFIG_COMMON_PANIC_OUTPUT
+#ifdef CONFIG_PLATFORM_EC_PANIC
+#define CONFIG_COMMON_PANIC_OUTPUT
+#endif
+
+#undef CONFIG_DEBUG_ASSSERT_BRIEF
+#ifdef CONFIG_PLATFORM_EC_DEBUG_ASSERT_BRIEF
+#define CONFIG_DEBUG_ASSSERT_BRIEF
+#endif
+
+#undef CONFIG_PANIC_CONSOLE_OUTPUT
+#ifdef CONFIG_PLATFORM_EC_PANIC_CONSOLE_OUTPUT
+#define CONFIG_PANIC_CONSOLE_OUTPUT
+#endif
+
+#undef CONFIG_RNG
+#ifdef CONFIG_PLATFORM_EC_RANDOM
+#define CONFIG_RNG
+#endif
+
+#undef CONFIG_CMD_CRASH
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_CRASH
+#define CONFIG_CMD_CRASH
+#endif
+
+#undef CONFIG_CMD_MEM
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_MEM
+#define CONFIG_CMD_MEM
+#endif
+
+#undef CONFIG_CMD_MD
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_MD
+#define CONFIG_CMD_MD
+#endif
+
+#undef CONFIG_CMD_RW
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_RW
+#define CONFIG_CMD_RW
+#endif
+
+#undef CONFIG_RTC
+#ifdef CONFIG_PLATFORM_EC_RTC
+#define CONFIG_RTC
+#endif
+
+#undef CONFIG_CMD_RTC
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_RTC
+#define CONFIG_CMD_RTC
+#endif
+
+#undef CONFIG_CMD_RTC_ALARM
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_RTC_ALARM
+#define CONFIG_CMD_RTC_ALARM
+#endif
+
+#undef CONFIG_HOSTCMD_RTC
+#ifdef CONFIG_PLATFORM_EC_HOSTCMD_RTC
+#define CONFIG_HOSTCMD_RTC
+#endif
+
+#undef CONFIG_HOST_COMMAND_STATUS
+#ifdef CONFIG_PLATFORM_EC_HOST_COMMAND_STATUS
+#define CONFIG_HOST_COMMAND_STATUS
+#endif
+
+#undef CONFIG_SWITCH
+#ifdef CONFIG_PLATFORM_EC_SWITCH
+#define CONFIG_SWITCH
+#endif
+
+#undef CONFIG_LN9310
+#ifdef CONFIG_PLATFORM_EC_SWITCHCAP_LN9310
+#define CONFIG_LN9310
+#endif
+
+#undef CONFIG_BOARD_VERSION_CBI
+#ifdef CONFIG_PLATFORM_EC_BOARD_VERSION_CBI
+#define CONFIG_BOARD_VERSION_CBI
+#endif
+
+#undef CONFIG_BOARD_VERSION_GPIO
+#ifdef CONFIG_PLATFORM_EC_BOARD_VERSION_GPIO
+#define CONFIG_BOARD_VERSION_GPIO
+#endif
+
+#undef CONFIG_CBI_EEPROM
+#ifdef CONFIG_PLATFORM_EC_CBI_EEPROM
+#define CONFIG_CBI_EEPROM
+#define I2C_ADDR_EEPROM_FLAGS DT_REG_ADDR(DT_NODELABEL(cbi_eeprom))
+#endif
+
+#undef CONFIG_EEPROM_CBI_WP
+#ifdef CONFIG_PLATFORM_EC_EEPROM_CBI_WP
+#define CONFIG_EEPROM_CBI_WP
+#endif
+
+#undef CONFIG_CBI_GPIO
+#ifdef CONFIG_PLATFORM_EC_CBI_GPIO
+#define CONFIG_CBI_GPIO
+#endif
+
+#undef CONFIG_CBI_FLASH
+#ifdef CONFIG_PLATFORM_EC_CBI_FLASH
+#define CONFIG_CBI_FLASH
+#endif
+
+#undef CONFIG_VBOOT_HASH
+#ifdef CONFIG_PLATFORM_EC_VBOOT_HASH
+#define CONFIG_VBOOT_HASH
+#endif
+
+#undef CONFIG_SHA256_HW_ACCELERATE
+#ifdef CONFIG_PLATFORM_EC_SHA256_HW_ACCELERATE
+#define CONFIG_SHA256_HW_ACCELERATE
+#endif
+
+#undef CONFIG_SHA256_UNROLLED
+#ifdef CONFIG_PLATFORM_EC_SHA256_UNROLLED
+#define CONFIG_SHA256_UNROLLED
+#endif
+
+#undef CONFIG_RO_HDR_MEM_OFF
+#ifdef CONFIG_PLATFORM_EC_RO_HEADER_OFFSET
+#define CONFIG_RO_HDR_MEM_OFF CONFIG_PLATFORM_EC_RO_HEADER_OFFSET
+#else
+#define CONFIG_RO_HDR_MEM_OFF 0
+#endif
+
+#undef CONFIG_RO_HDR_SIZE
+#ifdef CONFIG_PLATFORM_EC_RO_HEADER_SIZE
+#define CONFIG_RO_HDR_SIZE CONFIG_PLATFORM_EC_RO_HEADER_SIZE
+#else
+#define CONFIG_RO_HDR_SIZE 0
+#endif
+
+#undef CONFIG_SYSTEM_UNLOCKED
+#ifdef CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED
+#define CONFIG_SYSTEM_UNLOCKED
+#endif
+
+#undef CONFIG_CMD_GPIO_EXTENDED
+#ifdef CONFIG_PLATFORM_EC_CMD_GPIO_EXTENDED
+#define CONFIG_CMD_GPIO_EXTENDED
+#endif
+
+#undef CONFIG_BYPASS_CBI_EEPROM_WP_CHECK
+#ifdef CONFIG_PLATFORM_EC_BYPASS_CBI_EEPROM_WP_CHECK
+#define CONFIG_BYPASS_CBI_EEPROM_WP_CHECK
+#endif
+
+#undef CONFIG_SPI_FLASH_REGS
+#ifdef CONFIG_PLATFORM_EC_SPI_FLASH_REGS
+#define CONFIG_SPI_FLASH_REGS
+#endif
+
+#undef CONFIG_CMD_CHARGEN
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGEN
+#define CONFIG_CMD_CHARGEN
+#endif
+
+#undef CONFIG_DEBUG_ASSERT
+#ifdef CONFIG_PLATFORM_EC_DEBUG_ASSERT
+#define CONFIG_DEBUG_ASSERT
+#endif
+
+#undef CONFIG_DEBUG_ASSERT_BRIEF
+#ifdef CONFIG_PLATFORM_EC_DEBUG_ASSERT_BRIEF
+#define CONFIG_DEBUG_ASSERT_BRIEF
+#endif
+
+#undef CONFIG_DEBUG_ASSERT_REBOOTS
+#ifdef CONFIG_PLATFORM_EC_DEBUG_ASSERT_REBOOTS
+#define CONFIG_DEBUG_ASSERT_REBOOTS
+#endif
+
+#undef CONFIG_CMD_SYSINFO
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_SYSINFO
+#define CONFIG_CMD_SYSINFO
+#endif
+
+#undef CONFIG_CMD_SCRATCHPAD
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_SCRATCHPAD
+#define CONFIG_CMD_SCRATCHPAD
+#endif
+
+#undef CONFIG_CMD_SYSJUMP
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_SYSJUMP
+#define CONFIG_CMD_SYSJUMP
+#endif
+
+#undef CONFIG_WATCHDOG_PERIOD_MS
+#ifdef CONFIG_PLATFORM_EC_WATCHDOG_PERIOD_MS
+#define CONFIG_WATCHDOG_PERIOD_MS CONFIG_PLATFORM_EC_WATCHDOG_PERIOD_MS
+#endif
+
+#undef CONFIG_WATCHDOG_WARNING_LEADING_TIME_MS
+#if defined(CONFIG_PLATFORM_EC_WATCHDOG_WARNING_LEADING_TIME_MS) || \
+	defined(CONFIG_WDT_NPCX_DELAY_CYCLES) ||                    \
+	defined(CONFIG_WDT_ITE_WARNING_LEADING_TIME_MS)
+/*
+ * Note:
+ * NPCX wdt driver uses CONFIG_WDT_NPCX_DELAY_CYCLES to set the leading
+ * time of the watchdog warning timer.
+ * IT8XXX2 WDT driver uses CONFIG_WDT_ITE_WARNING_LEADING_TIME_MS period
+ * between watchdog warning and reset.
+ */
+#ifdef CONFIG_WDT_NPCX_DELAY_CYCLES
+#define CONFIG_WATCHDOG_WARNING_LEADING_TIME_MS \
+	(CONFIG_WDT_NPCX_DELAY_CYCLES * 31)
+#elif CONFIG_WDT_ITE_WARNING_LEADING_TIME_MS
+#define CONFIG_WATCHDOG_WARNING_LEADING_TIME_MS \
+	CONFIG_WDT_ITE_WARNING_LEADING_TIME_MS
+#else
+#define CONFIG_WATCHDOG_WARNING_LEADING_TIME_MS \
+	CONFIG_PLATFORM_EC_WATCHDOG_WARNING_LEADING_TIME_MS
+#endif
+#endif
+
+#undef CONFIG_VBOOT_EFS
+#undef CONFIG_VBOOT_EFS2
+#ifdef CONFIG_PLATFORM_EC_VBOOT_EFS2
+#define CONFIG_VBOOT_EFS2
+#endif
+
+#undef CONFIG_USB_PD_TCPC_VCONN
+#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPC_VCONN
+#define CONFIG_USB_PD_TCPC_VCONN
+#endif
+
+#undef CONFIG_DPTF
+#ifdef CONFIG_PLATFORM_EC_DPTF
+#define CONFIG_DPTF
+#endif
+
+#undef CONFIG_CHARGER_BQ25710
+#ifdef CONFIG_PLATFORM_EC_CHARGER_BQ25710
+#define CONFIG_CHARGER_BQ25710
+#endif
+
+#undef CONFIG_CHARGER_BQ25720
+#ifdef CONFIG_PLATFORM_EC_CHARGER_BQ25720
+#define CONFIG_CHARGER_BQ25720
+#endif
+
+#undef CONFIG_CHARGER_BQ257X0_ILIM2_VTH_CUSTOM
+#ifdef CONFIG_PLATFORM_EC_CHARGER_BQ257X0_ILIM2_VTH_CUSTOM
+#define CONFIG_CHARGER_BQ257X0_ILIM2_VTH_CUSTOM
+#endif
+
+#undef CONFIG_CHARGER_BQ257X0_ILIM2_VTH
+#ifdef CONFIG_PLATFORM_EC_CHARGER_BQ257X0_ILIM2_VTH
+#define CONFIG_CHARGER_BQ257X0_ILIM2_VTH \
+	CONFIG_PLATFORM_EC_CHARGER_BQ257X0_ILIM2_VTH
+#endif
+
+#undef CONFIG_CHARGER_BQ25720_VSYS_TH2_CUSTOM
+#ifdef CONFIG_PLATFORM_EC_CHARGER_BQ25720_VSYS_TH2_CUSTOM
+#define CONFIG_CHARGER_BQ25720_VSYS_TH2_CUSTOM
+#endif
+
+#undef CONFIG_CHARGER_BQ25720_VSYS_TH2_DV
+#ifdef CONFIG_PLATFORM_EC_CHARGER_BQ25720_VSYS_TH2_DV
+#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV \
+	CONFIG_PLATFORM_EC_CHARGER_BQ25720_VSYS_TH2_DV
+#endif
+
+#undef CONFIG_CHARGER_BQ25720_VSYS_UVP_CUSTOM
+#ifdef CONFIG_PLATFORM_EC_CHARGER_BQ25720_VSYS_UVP_CUSTOM
+#define CONFIG_CHARGER_BQ25720_VSYS_UVP_CUSTOM
+#endif
+
+#undef CONFIG_CHARGER_BQ25720_VSYS_UVP
+#ifdef CONFIG_PLATFORM_EC_CHARGER_BQ25720_VSYS_UVP
+#define CONFIG_CHARGER_BQ25720_VSYS_UVP \
+	CONFIG_PLATFORM_EC_CHARGER_BQ25720_VSYS_UVP
+#endif
+
+#undef CONFIG_CHARGER_BQ25720_IDCHG_DEG2_CUSTOM
+#ifdef CONFIG_PLATFORM_EC_CHARGER_BQ25720_IDCHG_DEG2_CUSTOM
+#define CONFIG_CHARGER_BQ25720_IDCHG_DEG2_CUSTOM
+#endif
+
+#undef CONFIG_CHARGER_BQ25720_IDCHG_DEG2
+#ifdef CONFIG_PLATFORM_EC_CHARGER_BQ25720_IDCHG_DEG2
+#define CONFIG_CHARGER_BQ25720_IDCHG_DEG2 \
+	CONFIG_PLATFORM_EC_CHARGER_BQ25720_IDCHG_DEG2
+#endif
+
+#undef CONFIG_CHARGER_BQ25720_IDCHG_TH2_CUSTOM
+#ifdef CONFIG_PLATFORM_EC_CHARGER_BQ25720_IDCHG_TH2_CUSTOM
+#define CONFIG_CHARGER_BQ25720_IDCHG_TH2_CUSTOM
+#endif
+
+#undef CONFIG_CHARGER_BQ25720_IDCHG_TH2
+#ifdef CONFIG_PLATFORM_EC_CHARGER_BQ25720_IDCHG_TH2
+#define CONFIG_CHARGER_BQ25720_IDCHG_TH2 \
+	CONFIG_PLATFORM_EC_CHARGER_BQ25720_IDCHG_TH2
+#endif
+
+#undef CONFIG_CHARGER_BQ25710_VSYS_MIN_VOLTAGE_CUSTOM
+#ifdef CONFIG_PLATFORM_EC_CHARGER_BQ25710_VSYS_MIN_VOLTAGE_CUSTOM
+#define CONFIG_CHARGER_BQ25710_VSYS_MIN_VOLTAGE_CUSTOM
+#endif
+
+#undef CONFIG_CHARGER_BQ25710_VSYS_MIN_VOLTAGE_MV
+#ifdef CONFIG_PLATFORM_EC_CHARGER_BQ25710_VSYS_MIN_VOLTAGE_MV
+#define CONFIG_CHARGER_BQ25710_VSYS_MIN_VOLTAGE_MV \
+	CONFIG_PLATFORM_EC_CHARGER_BQ25710_VSYS_MIN_VOLTAGE_MV
+#endif
+
+#undef CONFIG_HIBERNATE_PSL
+#ifdef CONFIG_PLATFORM_EC_HIBERNATE_PSL
+#define CONFIG_HIBERNATE_PSL
+#endif
+
+#ifdef CONFIG_PLATFORM_EC_HIBERNATE_DELAY_SEC
+#undef CONFIG_HIBERNATE_DELAY_SEC
+#define CONFIG_HIBERNATE_DELAY_SEC CONFIG_PLATFORM_EC_HIBERNATE_DELAY_SEC
+#endif
+
+#undef CONFIG_HIBERNATE
+#ifdef CONFIG_PLATFORM_EC_HIBERNATE
+#define CONFIG_HIBERNATE
+#endif
+
+#undef CONFIG_BATTERY_DEVICE_CHEMISTRY
+#ifdef CONFIG_PLATFORM_EC_USE_BATTERY_DEVICE_CHEMISTRY
+#define CONFIG_BATTERY_DEVICE_CHEMISTRY \
+	CONFIG_PLATFORM_EC_BATTERY_DEVICE_CHEMISTRY
+#endif
+
+#undef CONFIG_CHARGER_BQ25710_PSYS_SENSING
+#ifdef CONFIG_PLATFORM_EC_CHARGER_BQ25710_PSYS_SENSING
+#define CONFIG_CHARGER_BQ25710_PSYS_SENSING
+#endif
+
+#undef CONFIG_CHARGER_BQ25710_CMP_REF_1P2
+#ifdef CONFIG_PLATFORM_EC_CHARGER_BQ25710_CMP_REF_1P2
+#define CONFIG_CHARGER_BQ25710_CMP_REF_1P2
+#endif
+
+#undef CONFIG_CHARGER_BQ25710_CMP_POL_EXTERNAL
+#ifdef CONFIG_PLATFORM_EC_CHARGER_BQ25710_CMP_POL_EXTERNAL
+#define CONFIG_CHARGER_BQ25710_CMP_POL_EXTERNAL
+#endif
+
+#undef CONFIG_CHARGER_BQ25710_PKPWR_TOVLD_DEG_CUSTOM
+#ifdef CONFIG_PLATFORM_EC_CHARGER_BQ25710_PKPWR_TOVLD_DEG_CUSTOM
+#define CONFIG_CHARGER_BQ25710_PKPWR_TOVLD_DEG_CUSTOM
+#endif
+
+#undef CONFIG_CHARGER_BQ25710_PKPWR_TOVLD_DEG
+#ifdef CONFIG_PLATFORM_EC_CHARGER_BQ25710_PKPWR_TOVLD_DEG
+#define CONFIG_CHARGER_BQ25710_PKPWR_TOVLD_DEG \
+	CONFIG_PLATFORM_EC_CHARGER_BQ25710_PKPWR_TOVLD_DEG
+#endif
+
+#undef CONFIG_CHARGER_BQ25710_EN_ACOC
+#ifdef CONFIG_PLATFORM_EC_CHARGER_BQ25710_EN_ACOC
+#define CONFIG_CHARGER_BQ25710_EN_ACOC
+#endif
+
+#undef CONFIG_CHARGER_BQ25710_ACOC_VTH_1P33
+#ifdef CONFIG_PLATFORM_EC_CHARGER_BQ25710_ACOC_VTH_1P33
+#define CONFIG_CHARGER_BQ25710_ACOC_VTH_1P33
+#endif
+
+#undef CONFIG_CHARGER_BQ25710_BATOC_VTH_MINIMUM
+#ifdef CONFIG_PLATFORM_EC_CHARGER_BQ25710_BATOC_VTH_MINIMUM
+#define CONFIG_CHARGER_BQ25710_BATOC_VTH_MINIMUM
+#endif
+
+#undef CONFIG_CHARGER_BQ25710_SENSE_RESISTOR
+#ifdef CONFIG_PLATFORM_EC_CHARGER_BQ25710_SENSE_RESISTOR
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR \
+	CONFIG_PLATFORM_EC_CHARGER_BQ25710_SENSE_RESISTOR
+#endif
+
+#undef CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC
+#ifdef CONFIG_PLATFORM_EC_CHARGER_BQ25710_SENSE_RESISTOR_AC
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC \
+	CONFIG_PLATFORM_EC_CHARGER_BQ25710_SENSE_RESISTOR_AC
+#endif
+
+#undef CONFIG_CHARGER_BQ25710_PP_INOM
+#ifdef CONFIG_PLATFORM_EC_CHARGER_BQ25710_PP_INOM
+#define CONFIG_CHARGER_BQ25710_PP_INOM
+#endif
+
+#undef CONFIG_CHARGER_BQ25710_PP_BATPRES
+#ifdef CONFIG_PLATFORM_EC_CHARGER_BQ25710_PP_BATPRES
+#define CONFIG_CHARGER_BQ25710_PP_BATPRES
+#endif
+
+#undef CONFIG_CHARGER_BQ25710_PP_ACOK
+#ifdef CONFIG_PLATFORM_EC_CHARGER_BQ25710_PP_ACOK
+#define CONFIG_CHARGER_BQ25710_PP_ACOK
+#endif
+
+#undef CONFIG_CHARGER_BQ25710_PP_COMP
+#ifdef CONFIG_PLATFORM_EC_CHARGER_BQ25710_PP_COMP
+#define CONFIG_CHARGER_BQ25710_PP_COMP
+#endif
+
+#undef CONFIG_CHARGER_BQ25720_PP_IDCHG2
+#ifdef CONFIG_PLATFORM_EC_CHARGER_BQ25720_PP_IDCHG2
+#define CONFIG_CHARGER_BQ25720_PP_IDCHG2
+#endif
+
+#undef CONFIG_CHARGER_DISCHARGE_ON_AC
+#ifdef CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC
+#define CONFIG_CHARGER_DISCHARGE_ON_AC
+#endif
+
+#undef CONFIG_CHARGER_DISCHARGE_ON_AC_CUSTOM
+#ifdef CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC_CUSTOM
+#define CONFIG_CHARGER_DISCHARGE_ON_AC_CUSTOM
+#endif
+
+#undef CONFIG_CHARGER_SENSE_RESISTOR
+#ifdef CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR
+#define CONFIG_CHARGER_SENSE_RESISTOR CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR
+#endif
+
+#undef CONFIG_CHARGER_SENSE_RESISTOR_AC
+#ifdef CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC \
+	CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC
+#endif
+
+#undef CONFIG_CHARGER_PROFILE_OVERRIDE
+#ifdef CONFIG_PLATFORM_EC_CHARGER_PROFILE_OVERRIDE
+#define CONFIG_CHARGER_PROFILE_OVERRIDE
+#endif
+
+#undef CONFIG_CHARGER_PSYS
+#ifdef CONFIG_PLATFORM_EC_CHARGER_PSYS
+#define CONFIG_CHARGER_PSYS
+#endif
+
+#undef CONFIG_CHARGER_PSYS_READ
+#ifdef CONFIG_PLATFORM_EC_CHARGER_PSYS_READ
+#define CONFIG_CHARGER_PSYS_READ
+#endif
+
+#undef CONFIG_CMD_CHARGER_ADC_AMON_BMON
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_ADC_AMON_BMON
+#define CONFIG_CMD_CHARGER_ADC_AMON_BMON
+#endif
+
+#undef CONFIG_USB_PD_PULLUP
+#define CONFIG_USB_PD_PULLUP CONFIG_PLATFORM_EC_USB_PD_PULLUP
+
+#undef CONFIG_USB_PD_ONLY_FIXED_PDOS
+#ifdef CONFIG_PLATFORM_EC_USB_PD_ONLY_FIXED_PDOS
+#define CONFIG_USB_PD_ONLY_FIXED_PDOS
+#endif
+
+#undef CONFIG_MP2964
+#ifdef CONFIG_PLATFORM_EC_MP2964
+#define CONFIG_MP2964
+#define I2C_ADDR_MP2964_FLAGS \
+	DT_REG_ADDR(DT_COMPAT_GET_ANY_STATUS_OKAY(mps_mp2964))
+BUILD_ASSERT((DT_NUM_INST_STATUS_OKAY(mps_mp2964)) == 1,
+	     "Only one instance of mps,mp2964 should be defined");
+#endif
+
+#undef CONFIG_INA236
+#ifdef CONFIG_PLATFORM_EC_INA236
+#define CONFIG_INA236
+#endif
+
+#undef CONFIG_ACCELGYRO_ICM_COMM_SPI
+#ifdef CONFIG_PLATFORM_EC_ACCELGYRO_ICM_COMM_SPI
+#define CONFIG_ACCELGYRO_ICM_COMM_SPI
+#endif
+
+#undef CONFIG_ACCELGYRO_ICM_COMM_I2C
+#ifdef CONFIG_PLATFORM_EC_ACCELGYRO_ICM_COMM_I2C
+#define CONFIG_ACCELGYRO_ICM_COMM_I2C
+#endif
+
+#undef CONFIG_ACCELGYRO_BMI_COMM_SPI
+#ifdef CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_SPI
+#define CONFIG_ACCELGYRO_BMI_COMM_SPI
+#endif
+
+#undef CONFIG_ACCELGYRO_BMI_COMM_I2C
+#ifdef CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C
+#define CONFIG_ACCELGYRO_BMI_COMM_I2C
+#endif
+
+#undef CONFIG_CMD_SLEEPMASK
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_SLEEPMASK
+#define CONFIG_CMD_SLEEPMASK
+#endif
+
+#undef CONFIG_CMD_SLEEPMASK_SET
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_SLEEPMASK_SET
+#define CONFIG_CMD_SLEEPMASK_SET
+#endif
+
+#undef CONFIG_LOW_POWER_IDLE
+#ifdef CONFIG_PLATFORM_EC_LOW_POWER_IDLE
+#define CONFIG_LOW_POWER_IDLE
+#endif
+
+#undef CONFIG_LOW_POWER_S0
+#ifdef CONFIG_PLATFORM_EC_LOW_POWER_S0
+#define CONFIG_LOW_POWER_S0
+#endif
+
+#undef CONFIG_POWER_COMMON
+#ifdef CONFIG_PLATFORM_EC_POWER_COMMON
+#define CONFIG_POWER_COMMON
+#endif
+
+#undef CONFIG_PORT80_4_BYTE
+#ifdef CONFIG_PLATFORM_EC_PORT80_4_BYTE
+#define CONFIG_PORT80_4_BYTE
+#endif
+
+#undef CONFIG_PORT80_QUIET
+#ifdef CONFIG_PLATFORM_EC_PORT80_QUIET
+#define CONFIG_PORT80_QUIET
+#endif
+
+#undef CONFIG_PORT80_CUSTOM_FORMAT
+#ifdef CONFIG_PLATFORM_EC_PORT80_CUSTOM_FORMAT
+#define CONFIG_PORT80_CUSTOM_FORMAT
+#endif
+
+#undef CONFIG_ASSERT_CCD_MODE_ON_DTS_CONNECT
+#ifdef CONFIG_PLATFORM_EC_ASSERT_CCD_MODE_ON_DTS_CONNECT
+#define CONFIG_ASSERT_CCD_MODE_ON_DTS_CONNECT
+#endif
+
+#undef CONFIG_CCD_USBC_PORT_NUMBER
+#ifdef CONFIG_PLATFORM_EC_CCD_USBC_PORT_NUMBER
+#define CONFIG_CCD_USBC_PORT_NUMBER CONFIG_PLATFORM_EC_CCD_USBC_PORT_NUMBER
+#endif
+
+#undef CONFIG_ACCEL_LIS2DW12
+#ifdef CONFIG_PLATFORM_EC_ACCEL_LIS2DW12
+#define CONFIG_ACCEL_LIS2DW12
+#endif
+
+#undef CONFIG_CONSOLE_CHANNEL
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CHANNEL
+#define CONFIG_CONSOLE_CHANNEL
+#endif
+
+#undef CONFIG_USB_PD_DP_HPD_GPIO
+#ifdef CONFIG_PLATFORM_EC_USB_PD_DP_HPD_GPIO
+#define CONFIG_USB_PD_DP_HPD_GPIO
+#endif
+
+#undef CONFIG_USB_PD_DP_HPD_GPIO_CUSTOM
+#ifdef CONFIG_PLATFORM_EC_USB_PD_DP_HPD_GPIO_CUSTOM
+#define CONFIG_USB_PD_DP_HPD_GPIO_CUSTOM
+#endif
+
+#undef CONSOLE_CMD_MFALLOW
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_MFALLOW
+#define CONSOLE_CMD_MFALLOW
+#endif
+
+#undef CONFIG_TEMP_SENSOR_FIRST_READ_DELAY_MS
+#ifdef CONFIG_PLATFORM_EC_TEMP_SENSOR_FIRST_READ_DELAY
+#define CONFIG_TEMP_SENSOR_FIRST_READ_DELAY_MS \
+	CONFIG_PLATFORM_EC_TEMP_SENSOR_FIRST_READ_DELAY_MS
+#endif
+
+#undef CONFIG_CMD_S5_TIMEOUT
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_S5_TIMEOUT
+#define CONFIG_CMD_S5_TIMEOUT
+#endif
+
+#undef CONFIG_CMD_BATTERY_CONFIG
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_BATTERY_CONFIG
+#define CONFIG_CMD_BATTERY_CONFIG
+#endif
+
+#undef CONFIG_FW_RESET_VECTOR
+#ifdef CONFIG_PLATFORM_EC_FW_RESET_VECTOR
+#define CONFIG_FW_RESET_VECTOR
+#endif
+
+#undef CONFIG_WP_DISABLE
+#ifdef CONFIG_PLATFORM_EC_WP_DISABLE
+#define CONFIG_WP_DISABLE
+#endif
+
+#undef CONFIG_HOSTCMD_DEBUG_MODE
+#ifdef CONFIG_PLATFORM_EC_HOSTCMD_DEBUG_MODE
+#define CONFIG_HOSTCMD_DEBUG_MODE CONFIG_PLATFORM_EC_HOSTCMD_DEBUG_MODE
+#endif
+
+#undef CONFIG_AMD_SB_RMI
+#ifdef CONFIG_PLATFORM_EC_AMD_SB_RMI
+#define CONFIG_AMD_SB_RMI
+#endif
+
+#undef CONFIG_AMD_STT
+#ifdef CONFIG_PLATFORM_EC_AMD_STT
+#define CONFIG_AMD_STT
+#endif
+
+#ifdef CONFIG_PLATFORM_EC_IOEX_CROS_DRV
+#define CONFIG_IO_EXPANDER_SUPPORT_GET_PORT
+#endif
+
+#undef CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
+#ifdef CONFIG_PLATFORM_EC_USB_PD_REQUIRE_AP_MODE_ENTRY
+#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
+#endif
+
+#undef CONFIG_USB_PD_VDM_AP_CONTROL
+#ifdef CONFIG_PLATFORM_EC_USB_PD_VDM_AP_CONTROL
+#define CONFIG_USB_PD_VDM_AP_CONTROL
+#endif
+
+#undef CONFIG_USB_PD_CLEAR_HARD_RESET_STATUS
+#ifdef CONFIG_PLATFORM_EC_USB_PD_CLEAR_HARD_RESET_STATUS
+#define CONFIG_USB_PD_CLEAR_HARD_RESET_STATUS
+#endif
+
+#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT
+#ifdef CONFIG_PLATFORM_EC_DEDICATED_CHARGE_PORT
+#define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1
+#define DEDICATED_CHARGE_PORT CONFIG_USB_PD_PORT_MAX_COUNT
+#else
+#define CONFIG_DEDICATED_CHARGE_PORT_COUNT 0
+#endif
+
+#undef CONFIG_IO_EXPANDER_CCGXXF
+#ifdef CONFIG_PLATFORM_EC_IOEX_CCGXXF
+#define CONFIG_IO_EXPANDER_CCGXXF
+#endif
+
+#undef CONFIG_PERIPHERAL_CHARGER
+#ifdef CONFIG_PLATFORM_EC_PERIPHERAL_CHARGER
+#define CONFIG_PERIPHERAL_CHARGER
+#endif
+
+#undef CONFIG_CPS8100
+#ifdef CONFIG_PLATFORM_EC_CPS8100
+#define CONFIG_CPS8100
+#endif
+
+#undef CONFIG_HOST_EVENT64
+#ifdef CONFIG_PLATFORM_EC_HOST_EVENT64
+#define CONFIG_HOST_EVENT64
+#undef CONFIG_HOST_EVENT_REPORT_MASK
+#define CONFIG_HOST_EVENT_REPORT_MASK 0xffffffffffffffffULL
+#endif
+
+#undef CONFIG_CUSTOMIZED_DESIGN
+#undef CONFIG_FAN_INIT_SPEED
+#ifdef CONFIG_PLATFORM_EC_CUSTOMIZED_DESIGN
+#define CONFIG_CUSTOMIZED_DESIGN
+#define CONFIG_FAN_INIT_SPEED 20
+#endif
+
+#undef CONFIG_GPU
+#ifdef CONFIG_PLATFORM_EC_GPU
+#define CONFIG_GPU
+#endif
+
+#undef CONFIG_SYSTEM_SAFE_MODE
+#ifdef CONFIG_PLATFORM_EC_SYSTEM_SAFE_MODE
+#define CONFIG_SYSTEM_SAFE_MODE
+#endif
+
+#undef CONFIG_SYSTEM_SAFE_MODE_TIMEOUT_MSEC
+#ifdef CONFIG_PLATFORM_EC_SYSTEM_SAFE_MODE_TIMEOUT_MSEC
+#define CONFIG_SYSTEM_SAFE_MODE_TIMEOUT_MSEC \
+	CONFIG_PLATFORM_EC_SYSTEM_SAFE_MODE_TIMEOUT_MSEC
+#endif
+
+#undef CONFIG_SYSTEM_SAFE_MODE_PRINT_STACK
+#ifdef CONFIG_PLATFORM_EC_SYSTEM_SAFE_MODE_PRINT_STACK
+#define CONFIG_SYSTEM_SAFE_MODE_PRINT_STACK
+#endif
+
+#undef CONFIG_BATT_HOST_FULL_FACTOR
+#ifdef CONFIG_PLATFORM_EC_BATT_HOST_FULL_FACTOR
+#define CONFIG_BATT_HOST_FULL_FACTOR CONFIG_PLATFORM_EC_BATT_HOST_FULL_FACTOR
+#endif
+
+#undef CONFIG_TOUCHPAD
+#ifdef CONFIG_PLATFORM_EC_TOUCHPAD
+#define CONFIG_TOUCHPAD
+#endif
+
+#undef CONFIG_DETACHABLE_BASE
+#ifdef CONFIG_PLATFORM_EC_DETACHABLE_BASE
+#define CONFIG_DETACHABLE_BASE
+#define CONFIG_BASE_ATTACHED_SWITCH
+#endif
+
+#undef CONFIG_BASE_ATTACHED_SWITCH
+#ifdef CONFIG_PLATFORM_EC_BASE_ATTACHED_SWITCH
+#define CONFIG_BASE_ATTACHED_SWITCH
+#endif
+
+#undef CONFIG_RWSIG
+#ifdef CONFIG_PLATFORM_EC_RWSIG
+#define CONFIG_RWSIG
+
+#ifdef CONFIG_PLATFORM_EC_RWSIG_TYPE_RWSIG
+#define CONFIG_RWSIG_TYPE_RWSIG
+#endif
+
+#endif /* CONFIG_PLATFORM_EC_RWSIG */
+
+#undef CONFIG_RSA
+#ifdef CONFIG_PLATFORM_EC_RSA
+#define CONFIG_RSA
+#define CONFIG_RSA_KEY_SIZE CONFIG_PLATFORM_EC_RSA_KEY_SIZE
 
-#endif  /* CONFIG_PLATFORM_EC_TIMER */
+#ifdef CONFIG_PLATFORM_EC_RSA_EXPONENT_3
+#define CONFIG_RSA_EXPONENT_3
+#endif
+#endif /* CONFIG_PLATFORM_EC_RSA */
 
-#endif  /* __CROS_EC_CONFIG_CHIP_H */
+#endif /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/zephyr/shim/include/cpu.h b/zephyr/shim/include/cpu.h
new file mode 100644
index 0000000000..3e65aa0061
--- /dev/null
+++ b/zephyr/shim/include/cpu.h
@@ -0,0 +1,14 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_CPU_H
+#define __CROS_EC_CPU_H
+
+/* Do nothing for Zephyr */
+static inline void cpu_init(void)
+{
+}
+
+#endif /* __CROS_EC_CPU_H */
diff --git a/zephyr/shim/include/cros_als.h b/zephyr/shim/include/cros_als.h
new file mode 100644
index 0000000000..de4ff47885
--- /dev/null
+++ b/zephyr/shim/include/cros_als.h
@@ -0,0 +1,19 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __ZEPHYR_CROS_EC_ALS_H
+#define __ZEPHYR_CROS_EC_ALS_H
+
+#define CM32183_COMPAT nxp_cm32183
+
+#define CM32183_SENSOR_ID(node_id) DT_CAT(CM32183_, node_id)
+#define CM32183_SENSOR_ID_WITH_COMMA(node_id) CM32183_SENSOR_ID(node_id),
+
+enum als_id {
+	DT_FOREACH_STATUS_OKAY(CM32183_COMPAT, CM32183_SENSOR_ID_WITH_COMMA)
+	ALS_COUNT,
+};
+
+#endif /* __ZEPHYR_CROS_EC_ALS_H */
diff --git a/zephyr/shim/include/cros_cbi.h b/zephyr/shim/include/cros_cbi.h
new file mode 100644
index 0000000000..49d3608426
--- /dev/null
+++ b/zephyr/shim/include/cros_cbi.h
@@ -0,0 +1,119 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_CROS_CBI_H
+#define __CROS_EC_CROS_CBI_H
+
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/kernel.h>
+
+/*
+ * Macros are _INST_ types, so require DT_DRV_COMPAT to be defined.
+ */
+#define DT_DRV_COMPAT cros_ec_cbi_ssfc_value
+
+#define CBI_SSFC_VALUE_COMPAT DT_DRV_COMPAT
+#define CBI_SSFC_VALUE_ID(id) DT_CAT(CBI_SSFC_VALUE_, id)
+#define CBI_SSFC_VALUE_ID_WITH_COMMA(id) CBI_SSFC_VALUE_ID(id),
+#define CBI_SSFC_VALUE_INST_ENUM(inst, _) \
+	CBI_SSFC_VALUE_ID_WITH_COMMA(DT_INST(inst, CBI_SSFC_VALUE_COMPAT))
+
+enum cbi_ssfc_value_id {
+	LISTIFY(DT_NUM_INST_STATUS_OKAY(CBI_SSFC_VALUE_COMPAT),
+		CBI_SSFC_VALUE_INST_ENUM, ()) CBI_SSFC_VALUE_COUNT
+};
+
+#undef DT_DRV_COMPAT
+
+/*
+ * Macros to help generate the enum list of field and value names
+ * for the FW_CONFIG CBI data.
+ */
+#define CBI_FW_CONFIG_COMPAT cros_ec_cbi_fw_config
+#define CBI_FW_CONFIG_VALUE_COMPAT cros_ec_cbi_fw_config_value
+
+/*
+ * Retrieve the enum-name property for this node.
+ */
+#define CBI_FW_CONFIG_ENUM(node) DT_STRING_TOKEN(node, enum_name)
+
+/*
+ * Create an enum entry without a value (an enum with a following comma).
+ */
+#define CBI_FW_CONFIG_ENUM_WITH_COMMA(node) CBI_FW_CONFIG_ENUM(node),
+
+/*
+ * Create a single enum entry with assignment to the node's value,
+ * along with a following comma.
+ */
+#define CBI_FW_CONFIG_ENUM_WITH_VALUE(node) \
+	CBI_FW_CONFIG_ENUM(node) = DT_PROP(node, value),
+
+/*
+ * Generate a list of enum entries without a value.
+ */
+#define CBI_FW_CONFIG_CHILD_ENUM_LIST(node) \
+	DT_FOREACH_CHILD_STATUS_OKAY(node, CBI_FW_CONFIG_ENUM_WITH_COMMA)
+
+/*
+ * Enum list of all fields.
+ */
+/* clang-format off */
+enum cbi_fw_config_field_id {
+	DT_FOREACH_STATUS_OKAY(CBI_FW_CONFIG_COMPAT,
+			       CBI_FW_CONFIG_CHILD_ENUM_LIST)
+	CBI_FW_CONFIG_FIELDS_COUNT
+};
+/* clang-format on */
+
+/*
+ * enum list of all child values.
+ */
+/* clang-format off */
+enum cbi_fw_config_value_id {
+	DT_FOREACH_STATUS_OKAY(CBI_FW_CONFIG_VALUE_COMPAT,
+			       CBI_FW_CONFIG_ENUM_WITH_VALUE)
+	CBI_FW_CONFIG_VALUES_LAST /* added to ensure at least one entry */
+};
+/* clang-format on */
+
+/**
+ * @brief Initialize CBI SSFC
+ *
+ * The function has to be called before checking SSFC values.
+ */
+void cros_cbi_ssfc_init(void);
+
+/**
+ * @brief Initialize CBI FW
+ *
+ * The function has to be called before getting CBI FW_CONFIG.
+ */
+void cros_cbi_fw_config_init(void);
+
+/**
+ * @brief Check if the CBI SSFC value matches the one in the EEPROM
+ *
+ * @param value_id The SSFC value to check in EEPROM.
+ *
+ * @return true If matches, false if not.
+ */
+bool cros_cbi_ssfc_check_match(enum cbi_ssfc_value_id value_id);
+
+/**
+ * @brief Retrieve the value of the FW_CONFIG field
+ *
+ * @param field_id Enum identifying the field to return.
+ * @param value Pointer to the returned value.
+ *
+ * @return 0 if value found and returned.
+ * @retval -ENOTSUP Not supported api function.
+ * @retval -EINVAL Invalid field_id.
+ */
+int cros_cbi_get_fw_config(enum cbi_fw_config_field_id field_id,
+			   uint32_t *value);
+
+#endif /* __CROS_EC_CROS_CBI_H */
diff --git a/zephyr/shim/include/ec_tasks.h b/zephyr/shim/include/ec_tasks.h
new file mode 100644
index 0000000000..2b65b4f056
--- /dev/null
+++ b/zephyr/shim/include/ec_tasks.h
@@ -0,0 +1,38 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_EC_TASKS_H
+#define __CROS_EC_EC_TASKS_H
+
+#include "task.h"
+
+#include <zephyr/kernel.h>
+
+/** Starts all of the shimmed EC tasks. Requires CONFIG_SHIMMED_TASKS=y. */
+void start_ec_tasks(void);
+
+/**
+ * Maps an EC task id to a Zephyr thread id.
+ *
+ * @returns Thread id OR NULL if mapping fails
+ */
+k_tid_t task_id_to_thread_id(task_id_t task_id);
+
+/**
+ * Maps a Zephyr thread id to an EC task id.
+ *
+ * @returns Task id OR TASK_ID_INVALID if mapping fails
+ */
+task_id_t thread_id_to_task_id(k_tid_t thread_id);
+
+#ifdef TEST_BUILD
+/**
+ * Set TASK_ID_TEST_RUNNER to current thread tid. Some functions that are tested
+ * require to run in any task context.
+ */
+void set_test_runner_tid(void);
+#endif
+
+#endif /* __CROS_EC_EC_TASKS_H */
diff --git a/zephyr/shim/include/fpu.h b/zephyr/shim/include/fpu.h
new file mode 100644
index 0000000000..7e4c9866ab
--- /dev/null
+++ b/zephyr/shim/include/fpu.h
@@ -0,0 +1,66 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_FPU_H
+#define __CROS_EC_FPU_H
+
+/*
+ * These functions are available in newlib but we are are using Zephyr's
+ * minimal library at present.
+ *
+ * This file is not called math.h to avoid a conflict with the toolchain's
+ * built-in version.
+ *
+ * This code is taken from core/cortex-m/include/fpu.h
+ */
+
+#ifdef CONFIG_FPU
+
+/* Implementation for Cortex-M */
+#ifdef CONFIG_CPU_CORTEX_M
+static inline float sqrtf(float v)
+{
+	float root;
+
+	/* Use the CPU instruction */
+	__asm__ volatile("fsqrts %0, %1" : "=w"(root) : "w"(v));
+
+	return root;
+}
+
+static inline float fabsf(float v)
+{
+	float root;
+
+	/* Use the CPU instruction */
+	__asm__ volatile("fabss %0, %1" : "=w"(root) : "w"(v));
+
+	return root;
+}
+#elif CONFIG_RISCV
+static inline float sqrtf(float v)
+{
+	float root;
+
+	__asm__("fsqrt.s %0, %1" : "=f"(root) : "f"(v));
+	return root;
+}
+
+static inline float fabsf(float v)
+{
+	float abs;
+
+	__asm__("fabs.s %0, %1" : "=f"(abs) : "f"(v));
+	return abs;
+}
+#elif defined(CONFIG_BOARD_NATIVE_POSIX) || defined(CONFIG_SOC_FAMILY_INTEL_ISH)
+#include <math.h>
+#else
+#error "Unsupported core: please add an implementation"
+#endif
+
+#endif /* CONFIG_FPU */
+
+#endif /* __CROS_EC_MATH_H */
diff --git a/zephyr/shim/include/gpio/gpio.h b/zephyr/shim/include/gpio/gpio.h
new file mode 100644
index 0000000000..b2cdc954d9
--- /dev/null
+++ b/zephyr/shim/include/gpio/gpio.h
@@ -0,0 +1,126 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef ZEPHYR_SHIM_INCLUDE_GPIO_GPIO_H_
+#define ZEPHYR_SHIM_INCLUDE_GPIO_GPIO_H_
+
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/toolchain.h>
+
+/*
+ * Validate interrupt flags are valid for the Zephyr GPIO driver.
+ */
+#define IS_GPIO_INTERRUPT_FLAG(flag, mask) ((flag & mask) == mask)
+#define VALID_GPIO_INTERRUPT_FLAG(flag)                             \
+	(IS_GPIO_INTERRUPT_FLAG(flag, GPIO_INT_EDGE_RISING) ||      \
+	 IS_GPIO_INTERRUPT_FLAG(flag, GPIO_INT_EDGE_FALLING) ||     \
+	 IS_GPIO_INTERRUPT_FLAG(flag, GPIO_INT_EDGE_BOTH) ||        \
+	 IS_GPIO_INTERRUPT_FLAG(flag, GPIO_INT_LEVEL_LOW) ||        \
+	 IS_GPIO_INTERRUPT_FLAG(flag, GPIO_INT_LEVEL_HIGH) ||       \
+	 IS_GPIO_INTERRUPT_FLAG(flag, GPIO_INT_EDGE_TO_INACTIVE) || \
+	 IS_GPIO_INTERRUPT_FLAG(flag, GPIO_INT_EDGE_TO_ACTIVE) ||   \
+	 IS_GPIO_INTERRUPT_FLAG(flag, GPIO_INT_LEVEL_INACTIVE) ||   \
+	 IS_GPIO_INTERRUPT_FLAG(flag, GPIO_INT_LEVEL_ACTIVE))
+
+/* Information about each unused pin in the 'unused-pins' device tree node. */
+struct unused_pin_config {
+	/* Device name of a unused gpio pin */
+	const char *dev_name;
+	/* Bit number of pin within a unused gpio pin */
+	gpio_pin_t pin;
+	/* Config flags of unused gpio pin */
+	gpio_flags_t flags;
+};
+
+/**
+ * @brief Set proper configuration for all unused pins.
+ *
+ * This function loops through all unused GPIOs in the node of "unused-gpios"
+ * in the device tree file to set proper configuration. If the GPIO flag is 0,
+ * set the GPIOs default setting for floating IOs to improve the power
+ * consumption.
+ *
+ * @return 0 If successful.
+ * @retval -ENOTSUP Not supported gpio device.
+ * @retval -EIO I/O error when accessing an external GPIO chip.
+ */
+int gpio_config_unused_pins(void) __attribute__((weak));
+
+/**
+ * @brief Set configuration by port and pin of gpio
+ *
+ * @param port GPIO device index
+ * @param pin Pin number.
+ * @param flags Flags for pin configuration: 'GPIO input/output configuration
+ *        flags', 'GPIO pin drive flags', 'GPIO pin bias flags'.
+ *
+ * @return 0 If successful.
+ * @retval -ENOTSUP if any of the configuration options is not supported
+ *                  (unless otherwise directed by flag documentation).
+ * @retval -EINVAL Invalid argument.
+ * @retval -EIO I/O error when accessing an external GPIO chip.
+ * @retval -EWOULDBLOCK if operation would block.
+ */
+int gpio_configure_port_pin(int port, int id, int flags) __attribute__((weak));
+
+BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(unused_gpios) <= 1,
+	     "at most one unused-gpios compatible node may be present");
+
+#define UNUSED_GPIOS_NODE DT_COMPAT_GET_ANY_STATUS_OKAY(unused_gpios)
+
+#if DT_NODE_EXISTS(UNUSED_GPIOS_NODE)
+/**
+ * @brief Length of 'unused-gpios' property
+ *
+ * @return length of 'unused-gpios' prop which type is 'phandle-array'
+ */
+#define UNUSED_GPIOS_LIST_LEN DT_PROP_LEN(UNUSED_GPIOS_NODE, unused_gpios)
+
+/**
+ * @brief Construct a unused_pin_config structure from 'unused-gpios' property
+ *        at index 'i'
+ *
+ * @param i index of 'unused-gpios' prop which type is 'phandles-array'
+ * @return unused_pin_config item at index 'i'
+ */
+#define UNUSED_GPIO_CONFIG_BY_IDX(i, _)                                        \
+	{                                                                      \
+		.dev_name = DEVICE_DT_NAME(DT_GPIO_CTLR_BY_IDX(                \
+			UNUSED_GPIOS_NODE, unused_gpios, i)),                  \
+		.pin = DT_GPIO_PIN_BY_IDX(UNUSED_GPIOS_NODE, unused_gpios, i), \
+		.flags = DT_GPIO_FLAGS_BY_IDX(UNUSED_GPIOS_NODE, unused_gpios, \
+					      i),                              \
+	},
+
+/**
+ * @brief Macro function to construct a list of unused_pin_config items by
+ *        LISTIFY func.
+ *
+ * Example devicetree fragment:
+ *    / {
+ *          unused-pins {
+ *		compatible = "unused-gpios";
+ *		unused-gpios = <&gpio5 1 0>,
+ *			       <&gpiod 0 0>,
+ *			       <&gpiof 3 0>;
+ *	};
+ *
+ * Example usage:
+ * static const struct unused_pin_config unused_pin_configs[] = {
+ * 	UNUSED_GPIO_CONFIG_LIST
+ * };
+ *
+ * @return a list of unused_pin_config items
+ */
+#define UNUSED_GPIO_CONFIG_LIST \
+	LISTIFY(UNUSED_GPIOS_LIST_LEN, UNUSED_GPIO_CONFIG_BY_IDX, (), _)
+
+#else
+#define UNUSED_GPIO_CONFIG_LIST /* Nothing if no 'unused-pins' node */
+#endif /* DT_NODE_EXISTS(UNUSED_GPIOS_NODE) */
+
+#endif /* ZEPHYR_SHIM_INCLUDE_GPIO_GPIO_H_ */
diff --git a/zephyr/shim/include/gpio/gpio_int.h b/zephyr/shim/include/gpio/gpio_int.h
new file mode 100644
index 0000000000..835c5503ba
--- /dev/null
+++ b/zephyr/shim/include/gpio/gpio_int.h
@@ -0,0 +1,87 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef ZEPHYR_SHIM_INCLUDE_GPIO_GPIO_INT_H_
+#define ZEPHYR_SHIM_INCLUDE_GPIO_GPIO_INT_H_
+
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/gpio.h>
+
+/*
+ * Zephyr based interrupt handling.
+ * Uses device tree to configure the interrupt handling.
+ */
+
+/*
+ * Creates an internal name for the interrupt config block.
+ */
+#define GPIO_INT_FROM_NODE(id) DT_CAT(gpio_interrupt_, id)
+
+/*
+ * Maps nodelabel of interrupt node to internal configuration block.
+ */
+#define GPIO_INT_FROM_NODELABEL(lbl) (GPIO_INT_FROM_NODE(DT_NODELABEL(lbl)))
+
+/*
+ * Unique enum name for the interrupt.
+ */
+#define GPIO_INT_ENUM(id) DT_CAT(INT_ENUM_, id)
+
+/*
+ * Create an enum list of the interrupts
+ */
+enum gpio_interrupts {
+#if DT_HAS_COMPAT_STATUS_OKAY(cros_ec_gpio_interrupts)
+	DT_FOREACH_CHILD_SEP(
+		DT_COMPAT_GET_ANY_STATUS_OKAY(cros_ec_gpio_interrupts),
+		GPIO_INT_ENUM, (, )),
+#endif
+	GPIO_INT_COUNT
+};
+
+/*
+ * Forward reference to avoiding exposing internal structure
+ * defined in gpio_int.c
+ */
+struct gpio_int_config;
+
+/*
+ * Enable the interrupt.
+ *
+ * Interrupts are not automatically enabled, so
+ * each interrupt will need a call to activate the interrupt e.g
+ *
+ *   ... // set up device
+ *   gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(my_interrupt_node));
+ */
+int gpio_enable_dt_interrupt(const struct gpio_int_config *const ic);
+
+/*
+ * Disable the interrupt.
+ */
+int gpio_disable_dt_interrupt(const struct gpio_int_config *const ic);
+
+/*
+ * Get the interrupt config for this interrupt.
+ */
+const struct gpio_int_config *
+gpio_interrupt_get_config(enum gpio_interrupts intr);
+
+/*
+ * Declare interrupt configuration data structures.
+ */
+#define GPIO_INT_DECLARE(id) \
+	extern const struct gpio_int_config *const GPIO_INT_FROM_NODE(id);
+
+#if DT_HAS_COMPAT_STATUS_OKAY(cros_ec_gpio_interrupts)
+DT_FOREACH_CHILD(DT_COMPAT_GET_ANY_STATUS_OKAY(cros_ec_gpio_interrupts),
+		 GPIO_INT_DECLARE)
+#endif
+
+#undef GPIO_INT_DECLARE
+#undef GPIO_INT_DECLARE_NODE
+
+#endif /* ZEPHYR_SHIM_INCLUDE_GPIO_GPIO_INT_H_ */
diff --git a/zephyr/shim/include/hook_types.h b/zephyr/shim/include/hook_types.h
new file mode 100644
index 0000000000..9b11a6c27a
--- /dev/null
+++ b/zephyr/shim/include/hook_types.h
@@ -0,0 +1,58 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#ifndef __CROS_EC_HOOK_TYPES_H_
+#define __CROS_EC_HOOK_TYPES_H_
+
+#include <zephyr/sys/util_macro.h>
+
+/*
+ * Some config macros are defined but without any value for some boards, so
+ * IF_ENABLED checks cannot be used. In addition, config values may not be set
+ * when generating the linker script: in that case we emit every possible hook
+ * type, since doing so won't bloat the output if no corresponding sections
+ * were generated.
+ */
+#if defined(TEST_BUILD) || defined(_LINKER)
+#define HOOK_TYPES_TEST_BUILD HOOK_TEST_1, HOOK_TEST_2, HOOK_TEST_3,
+#else
+#define HOOK_TYPES_TEST_BUILD
+#endif
+
+#if defined(CONFIG_USB_SUSPEND) || defined(_LINKER)
+#define HOOK_TYPES_USB_SUSPEND HOOK_USB_PM_CHANGE
+#else
+#define HOOK_TYPES_USB_SUSPEND
+#endif
+
+#if defined(CONFIG_BODY_DETECTION) || defined(_LINKER)
+#define HOOK_TYPES_BODY_DETECTION HOOK_BODY_DETECT_CHANGE
+#else
+#define HOOK_TYPES_BODY_DETECTION
+#endif
+
+/*
+ * HOOK_TYPES_LIST is a sequence of tokens that expands to every enabled
+ * `enum hook_type` value.
+ *
+ * If the enum definition is changed, this macro must also be changed.
+ */
+#define HOOK_TYPES_LIST                                                     \
+	LIST_DROP_EMPTY(                                                    \
+		HOOK_INIT, HOOK_PRE_FREQ_CHANGE, HOOK_FREQ_CHANGE,          \
+		HOOK_SYSJUMP, HOOK_CHIPSET_PRE_INIT, HOOK_CHIPSET_STARTUP,  \
+		HOOK_CHIPSET_RESUME, HOOK_CHIPSET_SUSPEND,                  \
+		IF_ENABLED(CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK,     \
+			   (HOOK_CHIPSET_RESUME_INIT,                       \
+			    HOOK_CHIPSET_SUSPEND_COMPLETE, ))               \
+			HOOK_CHIPSET_SHUTDOWN,                              \
+		HOOK_CHIPSET_SHUTDOWN_COMPLETE, HOOK_CHIPSET_HARD_OFF,      \
+		HOOK_CHIPSET_RESET, HOOK_AC_CHANGE, HOOK_LID_CHANGE,        \
+		HOOK_TABLET_MODE_CHANGE, HOOK_TYPES_BODY_DETECTION,         \
+		HOOK_BASE_ATTACHED_CHANGE, HOOK_POWER_BUTTON_CHANGE,        \
+		HOOK_BATTERY_SOC_CHANGE, HOOK_TYPES_USB_SUSPEND, HOOK_TICK, \
+		HOOK_SECOND, HOOK_USB_PD_DISCONNECT, HOOK_USB_PD_CONNECT,   \
+		HOOK_POWER_SUPPLY_CHANGE, HOOK_TYPES_TEST_BUILD)
+
+#endif
diff --git a/zephyr/shim/include/i2c/i2c.h b/zephyr/shim/include/i2c/i2c.h
new file mode 100644
index 0000000000..42202dc2e2
--- /dev/null
+++ b/zephyr/shim/include/i2c/i2c.h
@@ -0,0 +1,210 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef ZEPHYR_CHROME_I2C_I2C_H
+#define ZEPHYR_CHROME_I2C_I2C_H
+
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/toolchain.h>
+
+BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(named_i2c_ports) == 1,
+	     "only one named-i2c-ports compatible node may be present");
+
+#define NAMED_I2C_PORTS_NODE DT_COMPAT_GET_ANY_STATUS_OKAY(named_i2c_ports)
+
+#define NPCX_PORT_COMPAT nuvoton_npcx_i2c_port
+#define ITE_IT8XXX2_PORT_COMPAT ite_it8xxx2_i2c
+#define ITE_ENHANCE_PORT_COMPAT ite_enhance_i2c
+#define MICROCHIP_XEC_COMPAT microchip_xec_i2c_v2
+#define INTEL_SEDI_I2C_COMPAT intel_sedi_i2c
+#define I2C_EMUL_COMPAT zephyr_i2c_emul_controller
+#define I2C_FOREACH_PORT(fn)                                \
+	DT_FOREACH_STATUS_OKAY(NPCX_PORT_COMPAT, fn)        \
+	DT_FOREACH_STATUS_OKAY(ITE_IT8XXX2_PORT_COMPAT, fn) \
+	DT_FOREACH_STATUS_OKAY(ITE_ENHANCE_PORT_COMPAT, fn) \
+	DT_FOREACH_STATUS_OKAY(MICROCHIP_XEC_COMPAT, fn)    \
+	DT_FOREACH_STATUS_OKAY(INTEL_SEDI_I2C_COMPAT, fn)   \
+	DT_FOREACH_STATUS_OKAY(I2C_EMUL_COMPAT, fn)
+
+/*
+ * Get the legacy I2C port enum value from the I2C bus node identifier.
+ * The value returned by this macro is passed as the 'int port' parameter to all
+ * the legacy APIs provided by i2c_controller.h
+ *
+ * Example devicetree fragment:
+ *
+ *     / {
+ *         soc-if {
+ *             i2c2_0: io_i2c_ctrl2_port0 {
+ *                 compatible = "nuvoton,npcx-i2c-port";
+ *                 #address-cells = <1>;
+ *                 #size-cells = <0>;
+ *                 port = <0x20>;
+ *                 controller = <&i2c_ctrl2>;
+ *                 label = "I2C_2_PORT_0";
+ *                 status = "disabled";
+ *             };
+ *         }.
+ *     };
+ *
+ * Example usage to get the I2C port enum value for i2c2_0:
+ *
+ *     I2C_PORT_BUS(DT_NODELABEL(i2c2_0))
+ *     // I2C_BUS_DT_N_S_soc_if_S_io_i2c_ctrl2_port0
+ *
+ * @param i2c_port_id: node id of a I2C port device
+ */
+#define I2C_PORT_BUS(i2c_port_id) DT_CAT(I2C_BUS_, i2c_port_id)
+#define I2C_PORT_BUS_WITH_COMMA(i2c_port_id) I2C_PORT_BUS(i2c_port_id),
+
+/*
+ * Get the legacy I2C port enum value from a named-i2c-ports child node.
+ *
+ * Example devicetree fragment:
+ *
+ *     i2c0_0: io_i2c_ctrl0_port0 {
+ *         compatible = "nuvoton,npcx-i2c-port";
+ *         #address-cells = <1>;
+ *         #size-cells = <0>;
+ *         port = <0x00>;
+ *         controller = <&i2c_ctrl0>;
+ *         label = "I2C_0_PORT_0";
+ *         status = "disabled";
+ *     };
+ *
+ *     named-i2c-ports {
+ *         compatible = "named-i2c-ports";
+ *         i2c_sensor: sensor {
+ *             i2c-port = <&i2c0_0>;
+ *             enum-names = "I2C_PORT_SENSOR";
+ *         };
+ *     };
+ *
+ * Example usage to get the I2C port enum value for i2c_sensor:
+ *
+ *     I2C_PORT(DT_NODELABEL(i2c_sensor))
+ *
+ * which equals:
+ *
+ *     I2C_PORT_BUS(DT_NODELABEL(i2c0_0))
+ *
+ * @param i2c_named_id: node id of a child of the named-i2c-ports node
+ */
+#define I2C_PORT(i2c_named_id) I2C_PORT_BUS(DT_PHANDLE(i2c_named_id, i2c_port))
+
+/*
+ * Get the legacy I2C port enum from the I2C bus nodelabel. This macro should be
+ * used with the I2C port device node, not the named-i2c-port child node.
+ *
+ *     / {
+ *         soc-if {
+ *             i2c2_0: io_i2c_ctrl2_port0 {
+ *                 compatible = "nuvoton,npcx-i2c-port";
+ *                 #address-cells = <1>;
+ *                 #size-cells = <0>;
+ *                 port = <0x20>;
+ *                 controller = <&i2c_ctrl2>;
+ *                 label = "I2C_2_PORT_0";
+ *                 status = "disabled";
+ *             };
+ *         }.
+ *     };
+ *
+ * Example usage to get the I2C port enum value for i2c2_0:
+ *
+ *     I2C_PORT_NODELABEL(i2c2_0)
+ *     // I2C_BUS_DT_N_S_soc_if_S_io_i2c_ctrl2_port0
+ *
+ * @param label: nodelabel of a I2C port device
+ */
+#define I2C_PORT_NODELABEL(label) I2C_PORT_BUS(DT_NODELABEL(label))
+
+/*
+ * Get the legacy I2C port enum for a child device on an I2C bus.
+ *
+ * Example devicetree fragment:
+ *
+ *     i2c2_0: io_i2c_ctrl2_port0 {
+ *         compatible = "nuvoton,npcx-i2c-port";
+ *         #address-cells = <1>;
+ *         #size-cells = <0>;
+ *         port = <0x20>;
+ *         controller = <&i2c_ctrl2>;
+ *         label = "I2C_2_PORT_0";
+ *         status = "disabled";
+ *     };
+ *
+ *     &i2c2_0 {
+ *         bc12_port0: pi3usb9201@5f {
+ *             compatible = "pericom,pi3usb9201";
+ *             status = "okay";
+ *             reg = <0x5f>;
+ *             irq = <&int_usb_c0_bc12>;
+ *         };
+ *     };
+ *
+ * Example usage to get the I2C port enum value for bc12_port0:
+ *
+ *     I2C_PORT_BY_DEV(DT_NODELABEL(bc12_port0))
+ *
+ *  * which equals:
+ *
+ *     I2C_PORT_BUS(DT_NODELABEL(i2c2_0))
+ *
+ * @param dev_id: node id of a device on the I2C bus
+ */
+#define I2C_PORT_BY_DEV(dev_id) I2C_PORT_BUS(DT_BUS(dev_id))
+
+enum i2c_ports_chip {
+	I2C_FOREACH_PORT(I2C_PORT_BUS_WITH_COMMA) I2C_PORT_COUNT
+};
+
+BUILD_ASSERT(I2C_PORT_COUNT != 0, "No I2C devices defined");
+
+#define I2C_PORT_ENUM_IDX_COMMA(i2c_named_id, prop, idx)        \
+	DT_STRING_UPPER_TOKEN_BY_IDX(i2c_named_id, prop, idx) = \
+		I2C_PORT(i2c_named_id),
+#define NAMED_I2C_PORT_COMMA(i2c_named_id) \
+	DT_FOREACH_PROP_ELEM(i2c_named_id, enum_names, I2C_PORT_ENUM_IDX_COMMA)
+
+/*
+ * The enum i2c_ports maps the hard-coded I2C port names (such as
+ * I2C_PORT_BATTERY or I2C_PORT_SENSOR) to the unique port numbers created by
+ * enum i2c_ports_chip above for every I2C port devicetree node.
+ */
+enum i2c_ports {
+	DT_FOREACH_CHILD_STATUS_OKAY(NAMED_I2C_PORTS_NODE, NAMED_I2C_PORT_COMMA)
+};
+
+/**
+ * @brief Adaptation of platform/ec's port IDs which map a port/bus to a device.
+ *
+ * This function should be implemented per chip and should map the enum value
+ * defined for the chip for encoding each valid port/bus combination. For
+ * example, the npcx chip defines the port/bus combinations NPCX_I2C_PORT* under
+ * chip/npcx/registers-npcx7.h.
+ *
+ * Thus, the npcx shim should implement this function to map the enum values
+ * to the correct devicetree device.
+ *
+ * @param port The port to get the device for.
+ * @return Pointer to the device struct or {@code NULL} if none are available.
+ */
+const struct device *i2c_get_device_for_port(const int port);
+
+/**
+ * @brief Get a port number for a received remote port number.
+ *
+ * This function translate a received port number via the I2C_PASSTHRU host
+ * command to a port number used in ZephyrEC based on remote_port property in
+ * dts. The first port which matches the remote port number is returned.
+ *
+ * @param port The received remote port.
+ * @return Port number used in EC. -1 if the remote port is not defined
+ */
+int i2c_get_port_from_remote_port(int remote_port);
+
+#endif /* ZEPHYR_CHROME_I2C_I2C_H */
diff --git a/zephyr/shim/include/linker.h b/zephyr/shim/include/linker.h
new file mode 100644
index 0000000000..92dc8f5981
--- /dev/null
+++ b/zephyr/shim/include/linker.h
@@ -0,0 +1,12 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_LINKER_H
+#define __CROS_EC_LINKER_H
+
+/* Put the start of shared memory after all allocated RAM symbols */
+#define __shared_mem_buf _image_ram_end
+
+#endif
diff --git a/zephyr/shim/include/motionsense_sensors.h b/zephyr/shim/include/motionsense_sensors.h
new file mode 100644
index 0000000000..f83a8c63ad
--- /dev/null
+++ b/zephyr/shim/include/motionsense_sensors.h
@@ -0,0 +1,75 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_MOTIONSENSE_SENSORS_H
+#define __CROS_EC_MOTIONSENSE_SENSORS_H
+
+#include "motion_sense.h"
+
+#include <zephyr/devicetree.h>
+
+extern struct motion_sensor_t motion_sensors_alt[];
+
+/*
+ * Common macros.
+ */
+#define SENSOR_ROT_STD_REF_NAME(id) DT_CAT(ROT_REF_, id)
+#define SENSOR_ROT_REF_NODE DT_PATH(motionsense_rotation_ref)
+
+/*
+ * Declare rotation parameters, since they may be
+ * dynamically selected.
+ */
+#define DECLARE_EXTERN_SENSOR_ROT_REF(id) \
+	extern const mat33_fp_t SENSOR_ROT_STD_REF_NAME(id);
+
+#if DT_NODE_EXISTS(SENSOR_ROT_REF_NODE)
+DT_FOREACH_CHILD(SENSOR_ROT_REF_NODE, DECLARE_EXTERN_SENSOR_ROT_REF)
+#endif
+#undef DECLARE_EXTERN_SENSOR_ROT_REF
+
+/*
+ * Performs probing of an alternate sensor.
+ * @param alt_idx Index in motion_sensors_alt of the sensor to be probed.
+ *		  It should be gained with SENSOR_ID,
+ *		  e.g. with SENSOR_ID(DT_NODELABEL(label)).
+ * @return EC_SUCCESS if the probe was successful, non-zero otherwise.
+ */
+int motion_sense_probe(enum sensor_alt_id alt_idx);
+
+/*
+ * Performs checking CBI SSFC fields defined in DTS to verify if an alternate
+ * motion sensor is present. If there is a match, the function replaces
+ * a default motion sensor in the motion_sensors array.
+ */
+void motion_sensors_check_ssfc(void);
+
+#define ENABLE_ALT_MOTION_SENSOR(alt_id)                               \
+	motion_sensors[SENSOR_ID(DT_PHANDLE(alt_id, alternate_for))] = \
+		motion_sensors_alt[SENSOR_ID(alt_id)];
+
+/*
+ * Replaces a default motion sensor with an alternate one pointed by nodelabel.
+ */
+#define MOTIONSENSE_ENABLE_ALTERNATE(nodelabel)                            \
+	do {                                                               \
+		BUILD_ASSERT(DT_NODE_EXISTS(DT_NODELABEL(nodelabel)),      \
+			     "Motionsense alternate node does not exist"); \
+		ENABLE_ALT_MOTION_SENSOR(DT_NODELABEL(nodelabel));         \
+	} while (0)
+
+/*
+ * Probes and replaces a default motion sensor with an alternate one pointed by
+ * nodelabel, if the probe was successful.
+ */
+#define MOTIONSENSE_PROBE_AND_ENABLE_ALTERNATE(nodelabel)                    \
+	do {                                                                 \
+		BUILD_ASSERT(DT_NODE_EXISTS(DT_NODELABEL(nodelabel)),        \
+			     "Motionsense alternate node does not exist");   \
+		if (!motion_sense_probe(SENSOR_ID(DT_NODELABEL(nodelabel)))) \
+			ENABLE_ALT_MOTION_SENSOR(DT_NODELABEL(nodelabel));   \
+	} while (0)
+
+#endif /* __CROS_EC_MOTIONSENSE_SENSORS_H */
diff --git a/zephyr/shim/include/motionsense_sensors_defs.h b/zephyr/shim/include/motionsense_sensors_defs.h
new file mode 100644
index 0000000000..35e4de56d7
--- /dev/null
+++ b/zephyr/shim/include/motionsense_sensors_defs.h
@@ -0,0 +1,104 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_MOTIONSENSE_SENSORS_DEFS_H
+#define __CROS_EC_MOTIONSENSE_SENSORS_DEFS_H
+
+#include "common.h"
+
+#include <zephyr/devicetree.h>
+
+#define SENSOR_ID(id) DT_CAT(SENSOR_, id)
+
+/* Define the SENSOR_ID if:
+ * DT_NODE_HAS_STATUS(id, okay) && !DT_NODE_HAS_PROP(id, alternate_for)
+ */
+#define SENSOR_ID_WITH_COMMA(id)                                     \
+	IF_ENABLED(DT_NODE_HAS_STATUS(id, okay),                     \
+		   (COND_CODE_0(DT_NODE_HAS_PROP(id, alternate_for), \
+				(SENSOR_ID(id), ), ())))
+
+/* clang-format off */
+enum sensor_id {
+#if DT_NODE_EXISTS(SENSOR_NODE)
+	DT_FOREACH_CHILD(SENSOR_NODE, SENSOR_ID_WITH_COMMA)
+#endif
+	SENSOR_COUNT,
+};
+/* clang-format on */
+
+#undef SENSOR_ID_WITH_COMMA
+/* Define the SENSOR_ID if:
+ * DT_NODE_HAS_STATUS(id, okay) && DT_NODE_HAS_PROP(id, alternate_for)
+ */
+#define SENSOR_ID_WITH_COMMA(id)                                     \
+	IF_ENABLED(DT_NODE_HAS_STATUS(id, okay),                     \
+		   (COND_CODE_1(DT_NODE_HAS_PROP(id, alternate_for), \
+				(SENSOR_ID(id), ), ())))
+/* clang-format off */
+enum sensor_alt_id {
+#if DT_NODE_EXISTS(SENSOR_ALT_NODE)
+	DT_FOREACH_CHILD(SENSOR_ALT_NODE, SENSOR_ID_WITH_COMMA)
+#endif
+	SENSOR_ALT_COUNT,
+};
+/* clang-format on */
+
+/*
+ * Find the accelerometers for lid angle calculation.
+ *
+ * The angle calculation requires two accelerometers. One is on the lid
+ * and the other one is on the base. So we need to specify which sensor is
+ * on the lid and which one is on the base. We use two labels "lid_accel"
+ * and "base_accel".
+ *
+ * base_accel - label for the accelerometer sensor on the base.
+ * lid_accel - label for the accelerometer sensor on the lid.
+ *
+ * e.g) below shows BMA255 is the accelerometer on the lid and bmi260 is
+ *     the accelerometer on the base.
+ *
+ * motionsense-sensor {
+ *         lid_accel: lid-accel {
+ *                 compatible = "cros-ec,bma255";
+ *                 status = "okay";
+ *                         :
+ *                         :
+ *         };
+ *
+ *	   base_accel: base-accel {
+ *                 compatible = "cros-ec,bmi260";
+ *                 status = "okay";
+ *                      :
+ *                      :
+ *         };
+ * };
+ */
+#ifdef CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_SENSOR_LID SENSOR_ID(DT_NODELABEL(lid_accel))
+#define CONFIG_LID_ANGLE_SENSOR_BASE SENSOR_ID(DT_NODELABEL(base_accel))
+#endif
+
+/*
+ * Get the sensors running in force mode from DT and create a bit mask for it.
+ *
+ * e.g) lid accel and als_clear are in accel_force_mode. The macro below finds
+ *      the corresponding bit for each sensor in bit mask and set it.
+ * motionsense-sensor-info {
+ *        compatible = "cros-ec,motionsense-sensor-info";
+ *
+ *        // list of sensors in force mode
+ *        accel-force-mode-sensors = <&lid_accel &als_clear>;
+ * };
+ */
+#if DT_NODE_HAS_PROP(SENSOR_INFO_NODE, accel_force_mode_sensors)
+#define SENSOR_IN_FORCE_MODE(i, id) \
+	| BIT(SENSOR_ID(DT_PHANDLE_BY_IDX(id, accel_force_mode_sensors, i)))
+#define CONFIG_ACCEL_FORCE_MODE_MASK                                        \
+	(0 LISTIFY(DT_PROP_LEN(SENSOR_INFO_NODE, accel_force_mode_sensors), \
+		   SENSOR_IN_FORCE_MODE, (), SENSOR_INFO_NODE))
+#endif
+
+#endif /* __CROS_EC_MOTIONSENSE_SENSORS_DEFS_H */
diff --git a/zephyr/shim/include/mpu.h b/zephyr/shim/include/mpu.h
new file mode 100644
index 0000000000..29771c9fe0
--- /dev/null
+++ b/zephyr/shim/include/mpu.h
@@ -0,0 +1,35 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_MPU_H
+#define __CROS_EC_MPU_H
+
+/* This matches up with core/cortex-m/include/mpu.h */
+
+/* Location of iram.text */
+extern char __iram_text_start;
+extern char __iram_text_end;
+
+/** Enable MPU */
+void mpu_enable(void);
+
+/**
+ * Returns the value of MPU type register
+ *
+ * @returns 0 for now (always)
+ */
+uint32_t mpu_get_type(void);
+
+/** Protect RAM from code execution */
+int mpu_protect_data_ram(void);
+
+/** Protect code RAM from being overwritten */
+int mpu_protect_code_ram(void);
+
+/** Protect internal mapped flash memory from code execution */
+int mpu_lock_ro_flash(void);
+int mpu_lock_rw_flash(void);
+
+#endif /* __CROS_EC_CPU_H */
diff --git a/zephyr/shim/include/power/power.h b/zephyr/shim/include/power/power.h
new file mode 100644
index 0000000000..a764e0c8b5
--- /dev/null
+++ b/zephyr/shim/include/power/power.h
@@ -0,0 +1,26 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef ZEPHYR_CHROME_POWER_POWER_H
+#define ZEPHYR_CHROME_POWER_POWER_H
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/gpio.h>
+
+#if CONFIG_CROS_EC_POWER_SIGNAL_LIST
+
+#define POWER_SIGNAL_LIST_NODE DT_NODELABEL(power_signal_list)
+
+#define GEN_POWER_SIGNAL_ENUM_ENTRY(cid) \
+	DT_STRING_UPPER_TOKEN(cid, power_enum_name)
+
+enum power_signal {
+	DT_FOREACH_CHILD_SEP(POWER_SIGNAL_LIST_NODE,
+			     GEN_POWER_SIGNAL_ENUM_ENTRY, (, )),
+	POWER_SIGNAL_COUNT
+};
+
+#endif /* CONFIG_CROS_EC_POWER_SIGNAL_LIST */
+#endif /* ZEPHYR_CHROME_POWER_POWER_H */
diff --git a/zephyr/shim/include/power_host_sleep.h b/zephyr/shim/include/power_host_sleep.h
new file mode 100644
index 0000000000..8bc23fc785
--- /dev/null
+++ b/zephyr/shim/include/power_host_sleep.h
@@ -0,0 +1,69 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __POWER_HOST_SLEEP_H
+#define __POWER_HOST_SLEEP_H
+
+/*
+ * This file is for Zephyr ap_pwrseq to reuse legacy EC code.
+ * Eventually this file should be removed.
+ *
+ * TODO: Declaration in this file should be removed once it can be replaced
+ * by implementation in Zephyr code.
+ */
+#if CONFIG_AP_PWRSEQ
+
+#include "ec_commands.h"
+#include "host_command.h"
+#include "lpc.h"
+#include "system.h"
+
+/********************************************************************/
+/* power.h */
+enum power_state {
+	/* Steady states */
+	POWER_G3 = 0, /*
+		       * System is off (not technically all the way into G3,
+		       * which means totally unpowered...)
+		       */
+	POWER_S5, /* System is soft-off */
+	POWER_S4, /* System is suspended to disk */
+	POWER_S3, /* Suspend; RAM on, processor is asleep */
+	POWER_S0, /* System is on */
+#if CONFIG_AP_PWRSEQ_S0IX
+	POWER_S0ix,
+#endif
+	/* Transitions */
+	POWER_G3S5, /* G3 -> S5 (at system init time) */
+	POWER_S5S3, /* S5 -> S3 (skips S4 on non-Intel systems) */
+	POWER_S3S0, /* S3 -> S0 */
+	POWER_S0S3, /* S0 -> S3 */
+	POWER_S3S5, /* S3 -> S5 (skips S4 on non-Intel systems) */
+	POWER_S5G3, /* S5 -> G3 */
+	POWER_S3S4, /* S3 -> S4 */
+	POWER_S4S3, /* S4 -> S3 */
+	POWER_S4S5, /* S4 -> S5 */
+	POWER_S5S4, /* S5 -> S4 */
+#if CONFIG_AP_PWRSEQ_S0IX
+	POWER_S0ixS0, /* S0ix -> S0 */
+	POWER_S0S0ix, /* S0 -> S0ix */
+#endif
+};
+
+#if CONFIG_AP_PWRSEQ_HOST_SLEEP
+/* Context to pass to a host sleep command handler. */
+struct host_sleep_event_context {
+	uint32_t sleep_transitions; /* Number of sleep transitions observed */
+	uint16_t sleep_timeout_ms; /* Timeout in milliseconds */
+};
+
+void ap_power_chipset_handle_host_sleep_event(
+	enum host_sleep_event state, struct host_sleep_event_context *ctx);
+void power_set_host_sleep_state(enum host_sleep_event state);
+#endif /* CONFIG_AP_PWRSEQ_HOST_SLEEP */
+
+#endif /* CONFIG_AP_PWRSEQ */
+
+#endif /* __POWER_HOST_SLEEP_H */
diff --git a/zephyr/shim/include/registers.h b/zephyr/shim/include/registers.h
new file mode 100644
index 0000000000..f17b05f5f8
--- /dev/null
+++ b/zephyr/shim/include/registers.h
@@ -0,0 +1,16 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_REGISTERS_H
+#define __CROS_EC_REGISTERS_H
+
+/*
+ * This file is left intentionally blank. It is required since many of the
+ * shimmed files from platform/ec/common include it. Normally, this file
+ * would define chip specific registers and would reside under
+ * platform/ec/chip/...
+ */
+
+#endif /* __CROS_EC_REGISTERS_H */
diff --git a/zephyr/shim/include/sha256_hw.h b/zephyr/shim/include/sha256_hw.h
new file mode 100644
index 0000000000..5891c6a818
--- /dev/null
+++ b/zephyr/shim/include/sha256_hw.h
@@ -0,0 +1,23 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_SHA256_CHIP_H
+#define __CROS_EC_SHA256_CHIP_H
+
+#include <zephyr/crypto/crypto.h>
+
+struct sha256_ctx {
+	/*
+	 * This is used to buffer:
+	 *   1. the result (digest) of the SHA256 computation.
+	 *   2. the 1st block input data (the key padding) for hmac_SHA256_step.
+	 */
+	uint8_t buf[SHA256_BLOCK_SIZE];
+	struct hash_ctx hash_sha256;
+} __aligned(4);
+
+void SHA256_abort(struct sha256_ctx *ctx);
+
+#endif /* __CROS_EC_SHA256_CHIP_H */
diff --git a/zephyr/shim/include/shimmed_task_id.h b/zephyr/shim/include/shimmed_task_id.h
new file mode 100644
index 0000000000..ba6980e9c5
--- /dev/null
+++ b/zephyr/shim/include/shimmed_task_id.h
@@ -0,0 +1,281 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_SHIMMED_TASK_ID_H
+#define __CROS_EC_SHIMMED_TASK_ID_H
+
+#include "common.h"
+
+/* Task identifier (8 bits) */
+typedef uint8_t task_id_t;
+
+/*
+ * Bitmask of port enable bits, expanding to a value like `BIT(0) | BIT(2) | 0`.
+ */
+#define PD_INT_SHARED_PORT_MASK                                           \
+	(FOR_EACH_NONEMPTY_TERM(                                          \
+		BIT, (|),                                                 \
+		IF_ENABLED(CONFIG_PLATFORM_EC_USB_PD_PORT_0_SHARED, (0)), \
+		IF_ENABLED(CONFIG_PLATFORM_EC_USB_PD_PORT_1_SHARED, (1)), \
+		IF_ENABLED(CONFIG_PLATFORM_EC_USB_PD_PORT_2_SHARED, (2)), \
+		IF_ENABLED(CONFIG_PLATFORM_EC_USB_PD_PORT_3_SHARED, (3)), ) 0)
+
+/* Highest priority on bottom -- same as in platform/ec. */
+enum {
+	EC_TASK_PRIO_LOWEST = 0,
+	EC_SYSWORKQ_PRIO = EC_TASK_PRIO_LOWEST,
+	EC_TASK_RWSIG_PRIO,
+	EC_TASK_TOUCHPAD_PRIO,
+	EC_TASK_CHG_RAMP_PRIO,
+	EC_TASK_USB_CHG_PRIO,
+	EC_TASK_DPS_PRIO,
+	EC_TASK_CHARGER_PRIO,
+	EC_TASK_CHIPSET_PRIO,
+	EC_TASK_MOTIONSENSE_PRIO,
+	EC_TASK_USB_MUX_PRIO,
+	EC_TASK_HOSTCMD_PRIO,
+	EC_SHELL_PRIO,
+	EC_TASK_KEYPROTO_PRIO,
+	EC_TASK_POWERBTN_PRIO,
+	EC_TASK_KEYSCAN_PRIO,
+	EC_TASK_PD_C0_PRIO,
+	EC_TASK_PD_C1_PRIO,
+	EC_TASK_PD_C2_PRIO,
+	EC_TASK_PD_C3_PRIO,
+	EC_TASK_PD_INT_SHARED_PRIO,
+	EC_TASK_PD_INT_C0_PRIO,
+	EC_TASK_PD_INT_C1_PRIO,
+	EC_TASK_PD_INT_C2_PRIO,
+	EC_TASK_PD_INT_C3_PRIO,
+	EC_TASK_CYPD_PRIO,
+	EC_TASK_ALS_PRIO,
+	EC_TASK_PRIO_COUNT,
+};
+
+/* Helper macro to set tasks priorities */
+#define EC_TASK_PRIORITY(prio) K_PRIO_PREEMPT(EC_TASK_PRIO_COUNT - prio - 1)
+
+/*
+ * List of CROS_EC_TASK items. See CONFIG_TASK_LIST in platform/ec's config.h
+ * for more information.  For tests that want their own custom tasks, use
+ * CONFIG_HAS_TEST_TASKS and not CONFIG_SHIMMED_TASKS.
+ */
+#ifdef CONFIG_SHIMMED_TASKS
+#define CROS_EC_TASK_LIST                                                  \
+	COND_CODE_1(HAS_TASK_CHG_RAMP,                                     \
+		    (CROS_EC_TASK(CHG_RAMP, chg_ramp_task, 0,              \
+				  CONFIG_TASK_CHG_RAMP_STACK_SIZE,         \
+				  EC_TASK_CHG_RAMP_PRIO)),                 \
+		    ())                                                    \
+	COND_CODE_1(CONFIG_PLATFORM_EC_USB_CHARGER,                        \
+		    (CROS_EC_TASK(USB_CHG, usb_charger_task_shared, 0,     \
+				  CONFIG_TASK_USB_CHG_STACK_SIZE,          \
+				  EC_TASK_USB_CHG_PRIO)),                  \
+		    ())                                                    \
+	COND_CODE_1(HAS_TASK_DPS,                                          \
+		    (CROS_EC_TASK(DPS, dps_task, 0,                        \
+				  CONFIG_TASK_DPS_STACK_SIZE,              \
+				  EC_TASK_DPS_PRIO)),                      \
+		    ())                                                    \
+	COND_CODE_1(HAS_TASK_CHARGER,                                      \
+		    (CROS_EC_TASK(CHARGER, charger_task, 0,                \
+				  CONFIG_TASK_CHARGER_STACK_SIZE,          \
+				  EC_TASK_CHARGER_PRIO)),                  \
+		    ())                                                    \
+	COND_CODE_1(HAS_TASK_CHIPSET,                                      \
+		    (CROS_EC_TASK(CHIPSET, chipset_task, 0,                \
+				  CONFIG_TASK_CHIPSET_STACK_SIZE,          \
+				  EC_TASK_CHIPSET_PRIO)),                  \
+		    ())                                                    \
+	COND_CODE_1(HAS_TASK_MOTIONSENSE,                                  \
+		    (CROS_EC_TASK(MOTIONSENSE, motion_sense_task, 0,       \
+				  CONFIG_TASK_MOTIONSENSE_STACK_SIZE,      \
+				  EC_TASK_MOTIONSENSE_PRIO)),              \
+		    ())                                                    \
+	IF_ENABLED(HAS_TASK_USB_MUX,                                       \
+		   (CROS_EC_TASK(USB_MUX, usb_mux_task, 0,                 \
+				 CONFIG_TASK_USB_MUX_STACK_SIZE,           \
+				 EC_TASK_USB_MUX_PRIO)))                   \
+	COND_CODE_1(CONFIG_TASK_HOSTCMD_THREAD_DEDICATED,                  \
+		    (CROS_EC_TASK(HOSTCMD, host_command_task, 0,           \
+				  CONFIG_TASK_HOSTCMD_STACK_SIZE,          \
+				  EC_TASK_HOSTCMD_PRIO)),                  \
+		    ())                                                    \
+	COND_CODE_1(HAS_TASK_KEYPROTO,                                     \
+		    (CROS_EC_TASK(KEYPROTO, keyboard_protocol_task, 0,     \
+				  CONFIG_TASK_KEYPROTO_STACK_SIZE,         \
+				  EC_TASK_KEYPROTO_PRIO)),                 \
+		    ())                                                    \
+	COND_CODE_1(HAS_TASK_POWERBTN,                                     \
+		    (CROS_EC_TASK(POWERBTN, power_button_task, 0,          \
+				  CONFIG_TASK_POWERBTN_STACK_SIZE,         \
+				  EC_TASK_POWERBTN_PRIO)),                 \
+		    ())                                                    \
+	COND_CODE_1(HAS_TASK_KEYSCAN,                                      \
+		    (CROS_EC_TASK(KEYSCAN, keyboard_scan_task, 0,          \
+				  CONFIG_TASK_KEYSCAN_STACK_SIZE,          \
+				  EC_TASK_KEYSCAN_PRIO)),                  \
+		    ())                                                    \
+	COND_CODE_1(HAS_TASK_PD_C0,                                        \
+		    (CROS_EC_TASK(PD_C0, pd_task, 0,                       \
+				  CONFIG_TASK_PD_STACK_SIZE,               \
+				  EC_TASK_PD_C0_PRIO)),                    \
+		    ())                                                    \
+	COND_CODE_1(HAS_TASK_PD_C1,                                        \
+		    (CROS_EC_TASK(PD_C1, pd_task, 0,                       \
+				  CONFIG_TASK_PD_STACK_SIZE,               \
+				  EC_TASK_PD_C1_PRIO)),                    \
+		    ())                                                    \
+	COND_CODE_1(HAS_TASK_PD_C2,                                        \
+		    (CROS_EC_TASK(PD_C2, pd_task, 0,                       \
+				  CONFIG_TASK_PD_STACK_SIZE,               \
+				  EC_TASK_PD_C2_PRIO)),                    \
+		    ())                                                    \
+	COND_CODE_1(HAS_TASK_PD_C3,                                        \
+		    (CROS_EC_TASK(PD_C3, pd_task, 0,                       \
+				  CONFIG_TASK_PD_STACK_SIZE,               \
+				  EC_TASK_PD_C3_PRIO)),                    \
+		    ())                                                    \
+	IF_ENABLED(CONFIG_HAS_TASK_PD_INT_SHARED,                          \
+		   (CROS_EC_TASK(PD_INT_SHARED, pd_shared_alert_task,      \
+				 PD_INT_SHARED_PORT_MASK,                  \
+				 CONFIG_TASK_PD_INT_STACK_SIZE,            \
+				 EC_TASK_PD_INT_SHARED_PRIO)))             \
+	COND_CODE_1(HAS_TASK_PD_INT_C0,                                    \
+		    (CROS_EC_TASK(PD_INT_C0, pd_interrupt_handler_task, 0, \
+				  CONFIG_TASK_PD_INT_STACK_SIZE,           \
+				  EC_TASK_PD_INT_C0_PRIO)),                \
+		    ())                                                    \
+	COND_CODE_1(HAS_TASK_PD_INT_C1,                                    \
+		    (CROS_EC_TASK(PD_INT_C1, pd_interrupt_handler_task, 1, \
+				  CONFIG_TASK_PD_INT_STACK_SIZE,           \
+				  EC_TASK_PD_INT_C1_PRIO)),                \
+		    ())                                                    \
+	COND_CODE_1(HAS_TASK_PD_INT_C2,                                    \
+		    (CROS_EC_TASK(PD_INT_C2, pd_interrupt_handler_task, 2, \
+				  CONFIG_TASK_PD_INT_STACK_SIZE,           \
+				  EC_TASK_PD_INT_C2_PRIO)),                \
+		    ())                                                    \
+	COND_CODE_1(HAS_TASK_PD_INT_C3,                                    \
+		    (CROS_EC_TASK(PD_INT_C3, pd_interrupt_handler_task, 3, \
+				  CONFIG_TASK_PD_INT_STACK_SIZE,           \
+				  EC_TASK_PD_INT_C3_PRIO)),                \
+		    ())                                                    \
+	COND_CODE_1(HAS_TASK_CYPD,                                         \
+		    (CROS_EC_TASK(CYPD, cypd_interrupt_handler_task, 0,    \
+				  CONFIG_TASK_CYPD_STACK_SIZE,             \
+				  EC_TASK_CYPD_PRIO)),                     \
+		())                                                    \
+	COND_CODE_1(HAS_TASK_ALS,                                         \
+		    (CROS_EC_TASK(ALS, als_task, 0,    \
+				  CONFIG_TASK_ALS_STACK_SIZE,             \
+				  EC_TASK_ALS_PRIO)),                     \
+		())                                                    \
+	COND_CODE_1(HAS_TASK_TOUCHPAD,                                     \
+		    (CROS_EC_TASK(TOUCHPAD, touchpad_task, 0,              \
+				  CONFIG_TASK_TOUCHPAD_STACK_SIZE,         \
+				  EC_TASK_TOUCHPAD_PRIO)),                 \
+		    ())                                                    \
+	COND_CODE_1(HAS_TASK_RWSIG,                                        \
+		    (CROS_EC_TASK(RWSIG, rwsig_task, 0,                    \
+				  CONFIG_TASK_RWSIG_STACK_SIZE,            \
+				  EC_TASK_RWSIG_PRIO)),                    \
+		    ())
+#elif defined(CONFIG_HAS_TEST_TASKS)
+#include "shimmed_test_tasks.h"
+/*
+ * There are two different ways to define a task list (because historical
+ * reasons). Applications use CROS_EC_TASK_LIST to define their tasks, while
+ * unit tests that need additional tasks use CONFIG_TEST_TASK_LIST. For
+ * shimming a unit test, define CROS_EC_TASK_LIST as whatever
+ * CONFIG_TEST_TASK_LIST expands to.
+ */
+#if defined(CONFIG_TEST_TASK_LIST) && !defined(CROS_EC_TASK_LIST)
+#define CROS_EC_TASK_LIST CONFIG_TEST_TASK_LIST
+#endif /* CONFIG_TEST_TASK_LIST && !CROS_EC_TASK_LIST */
+
+/*
+ * Tests often must link in files that reference task IDs, even when the
+ * shimmed tasks are not created.  Define stub tasks to satisfy the final link.
+ */
+#else /* !CONFIG_SHIMMED_TASKS && !CONFIG_HAS_TEST_TASKS */
+#define CROS_EC_TASK_LIST                                                   \
+	CROS_EC_TASK(CHG_RAMP, NULL, 0, 0, EC_TASK_CHG_RAMP_PRIO)           \
+	CROS_EC_TASK(USB_CHG, NULL, 0, 0, EC_TASK_USB_CHG_PRIO)             \
+	CROS_EC_TASK(DPS, NULL, 0, 0, EC_TASK_DPS_PRIO)                     \
+	CROS_EC_TASK(CHARGER, NULL, 0, 0, EC_TASK_CHARGER_PRIO)             \
+	CROS_EC_TASK(CHIPSET, NULL, 0, 0, EC_TASK_CHIPSET_PRIO)             \
+	CROS_EC_TASK(MOTIONSENSE, NULL, 0, 0, EC_TASK_MOTIONSENSE_PRIO)     \
+	CROS_EC_TASK(USB_MUX, NULL, 0, 0, EC_TASK_USB_MUX_PRIO)             \
+	CROS_EC_TASK(HOSTCMD, NULL, 0, 0, EC_TASK_HOSTCMD_PRIO)             \
+	CROS_EC_TASK(KEYPROTO, NULL, 0, 0, EC_TASK_KEYPROTO_PRIO)           \
+	CROS_EC_TASK(POWERBTN, NULL, 0, 0, EC_TASK_POWERBTN_PRIO)           \
+	CROS_EC_TASK(KEYSCAN, NULL, 0, 0, EC_TASK_KEYSCAN_PRIO)             \
+	CROS_EC_TASK(PD_C0, NULL, 0, 0, EC_TASK_PD_C0_PRIO)                 \
+	CROS_EC_TASK(PD_C1, NULL, 0, 0, EC_TASK_PD_C1_PRIO)                 \
+	CROS_EC_TASK(PD_C2, NULL, 0, 0, EC_TASK_PD_C2_PRIO)                 \
+	CROS_EC_TASK(PD_C3, NULL, 0, 0, EC_TASK_PD_C3_PRIO)                 \
+	CROS_EC_TASK(PD_INT_SHARED, NULL, 0, 0, EC_TASK_PD_INT_SHARED_PRIO) \
+	CROS_EC_TASK(PD_INT_C0, NULL, 0, 0, EC_TASK_PD_INT_C0_PRIO)         \
+	CROS_EC_TASK(PD_INT_C1, NULL, 1, 0, EC_TASK_PD_INT_C1_PRIO)         \
+	CROS_EC_TASK(PD_INT_C2, NULL, 2, 0, EC_TASK_PD_INT_C2_PRIO)         \
+	CROS_EC_TASK(PD_INT_C3, NULL, 3, 0, EC_TASK_PD_INT_C3_PRIO)         \
+	CROS_EC_TASK(CYPD, NULL, 0, 0, EC_TASK_CYPD_PRIO)                   \
+	CROS_EC_TASK(ALS, NULL, 0, 0, EC_TASK_ALS_PRIO)                   \
+	CROS_EC_TASK(TOUCHPAD, NULL, 0, 0, EC_TASK_TOUCHPAD_PRIO)           \
+
+
+#endif /* CONFIG_SHIMMED_TASKS */
+
+#ifndef CROS_EC_TASK_LIST
+#define CROS_EC_TASK_LIST
+#endif /* CROS_EC_TASK_LIST */
+
+/*
+ * Define the task_ids globally for all shimmed platform/ec code to use.
+ * Note that unit test task lists use TASK_TEST, which we can just alias
+ * into a regular CROS_EC_TASK.
+ */
+#define CROS_EC_TASK(name, ...) TASK_ID_##name,
+#define TASK_TEST(name, ...) CROS_EC_TASK(name)
+/* clang-format off */
+enum {
+	CROS_EC_TASK_LIST
+#ifdef TEST_BUILD
+	TASK_ID_TEST_RUNNER,
+#endif
+	TASK_ID_COUNT,
+	TASK_ID_INVALID = 0xff, /* Unable to find the task */
+};
+/* clang-format on */
+#undef CROS_EC_TASK
+#undef TASK_TEST
+
+/*
+ * Additional task IDs for features that runs on non shimmed threads,
+ * thread_id_to_task_id() and task_id_to_thread_id() need to be updated
+ * to identify these tasks.
+ */
+/* clang-format off */
+#define CROS_EC_EXTRA_TASKS(fn)                                         \
+	COND_CODE_1(CONFIG_TASK_HOSTCMD_THREAD_MAIN, (fn(HOSTCMD)),     \
+		(fn(MAIN)))                                             \
+	COND_CODE_1(CONFIG_SHELL_BACKEND_SERIAL, (fn(SHELL)),           \
+		(COND_CODE_1(CONFIG_SHELL_BACKEND_DUMMY, (fn(SHELL)),   \
+		())))							\
+	fn(SYSWORKQ)                                                    \
+	fn(IDLE)
+/* clang-format on */
+
+#define EXTRA_TASK_INTERNAL_ID(name) EXTRA_TASK_##name,
+enum {
+	CROS_EC_EXTRA_TASKS(EXTRA_TASK_INTERNAL_ID) EXTRA_TASK_COUNT,
+};
+
+#define EXTRA_TASK_ID(name) \
+	TASK_ID_##name = (TASK_ID_COUNT + EXTRA_TASK_##name),
+enum { CROS_EC_EXTRA_TASKS(EXTRA_TASK_ID) };
+
+#endif /* __CROS_EC_SHIMMED_TASK_ID_H */
diff --git a/zephyr/shim/include/shimmed_tasks.h b/zephyr/shim/include/shimmed_tasks.h
new file mode 100644
index 0000000000..cfe8d85120
--- /dev/null
+++ b/zephyr/shim/include/shimmed_tasks.h
@@ -0,0 +1,83 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_SHIMMED_TASKS_H
+#define __CROS_EC_SHIMMED_TASKS_H
+
+#ifdef CONFIG_HAS_TASK_CHARGER
+#define HAS_TASK_CHARGER 1
+#endif /* CONFIG_HAS_TASK_CHARGER */
+
+#ifdef CONFIG_HAS_TASK_CHG_RAMP
+#define HAS_TASK_CHG_RAMP 1
+#endif /* CONFIG_HAS_TASK_CHG_RAMP */
+
+#ifdef CONFIG_HAS_TASK_CHIPSET
+#define HAS_TASK_CHIPSET 1
+#endif /* CONFIG_HAS_TASK_CHIPSET */
+
+#ifdef CONFIG_HAS_TASK_DPS
+#define HAS_TASK_DPS 1
+#endif /* CONFIG_HAS_TASK_DPS */
+
+#ifdef CONFIG_HAS_TASK_HOSTCMD
+#define HAS_TASK_HOSTCMD 1
+#define CONFIG_HOSTCMD_EVENTS
+#endif /* CONFIG_HAS_TASK_HOSTCMD */
+
+#ifdef CONFIG_HAS_TASK_KEYSCAN
+#define HAS_TASK_KEYSCAN 1
+#endif /* CONFIG_HAS_TASK_KEYSCAN */
+
+#ifdef CONFIG_HAS_TASK_KEYPROTO
+#define HAS_TASK_KEYPROTO 1
+#endif /* CONFIG_HAS_TASK_KEYPROTO */
+
+#ifdef CONFIG_HAS_TASK_MOTIONSENSE
+#define HAS_TASK_MOTIONSENSE 1
+#endif /* CONFIG_HAS_TASK_MOTIONSENSE */
+
+#ifdef CONFIG_HAS_TASK_POWERBTN
+#define HAS_TASK_POWERBTN 1
+#endif /* CONFIG_HAS_TASK_POWERBTN */
+
+#ifdef CONFIG_HAS_TASK_POWERBTN_CUSTOMER
+#define HAS_TASK_POWERBTN 1
+#endif /* CONFIG_HAS_TASK_POWERBTN_CUSTOMER */
+
+#ifdef CONFIG_PLATFORM_EC_USB_MUX_TASK
+#define HAS_TASK_USB_MUX 1
+#endif /* CONFIG_PLATFORM_EC_USB_MUX_TASK */
+
+#ifdef CONFIG_HAS_TASK_CYPD
+#define HAS_TASK_CYPD 1
+#endif /* CONFIG_HAS_TASK_CYPD */
+
+#ifdef CONFIG_HAS_TASK_ALS
+#define HAS_TASK_ALS 1
+#endif /* CONFIG_HAS_TASK_ALS */
+
+#ifndef CONFIG_TASK_HOSTCMD_THREAD_MAIN
+#define HAS_TASK_MAIN 1
+#endif /* CONFIG_TASK_HOSTCMD_THREAD_DEDICATED */
+
+#if (defined(CONFIG_SHELL_BACKEND_SERIAL) || \
+     defined(CONFIG_SHELL_BACKEND_DUMMY))
+#define HAS_TASK_SHELL 1
+#endif
+
+/* These non-shimmed (extra) tasks are always present */
+#define HAS_TASK_IDLE 1
+#define HAS_TASK_SYSWORKQ 1
+
+#ifdef CONFIG_HAS_TASK_TOUCHPAD
+#define HAS_TASK_TOUCHPAD 1
+#endif /* CONFIG_HAS_TASK_TOUCHPAD */
+
+#ifdef CONFIG_HAS_TASK_RWSIG
+#define HAS_TASK_RWSIG 1
+#endif /* CONFIG_HAS_TASK_RWSIG */
+
+#endif /* __CROS_EC_SHIMMED_TASKS_H */
diff --git a/zephyr/shim/include/temp_sensor/temp_sensor.h b/zephyr/shim/include/temp_sensor/temp_sensor.h
new file mode 100644
index 0000000000..55272f65b2
--- /dev/null
+++ b/zephyr/shim/include/temp_sensor/temp_sensor.h
@@ -0,0 +1,193 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef ZEPHYR_SHIM_INCLUDE_TEMP_SENSOR_TEMP_SENSOR_H_
+#define ZEPHYR_SHIM_INCLUDE_TEMP_SENSOR_TEMP_SENSOR_H_
+
+#include "charger/chg_rt9490.h"
+#include "temp_sensor.h"
+
+#include <zephyr/devicetree.h>
+
+#ifdef CONFIG_PLATFORM_EC_TEMP_SENSOR
+
+#define PCT2075_COMPAT nxp_pct2075
+#define TMP112_COMPAT cros_ec_temp_sensor_tmp112
+#define F75303_COMPAT cros_ec_temp_sensor_f75303
+#define SB_TSI_COMPAT amd_sb_tsi
+#define THERMISTOR_COMPAT cros_ec_temp_sensor_thermistor
+#define TEMP_SENSORS_COMPAT cros_ec_temp_sensors
+#define AMDR23M_COMPAT cros_ec_temp_sensor_amdr23m
+
+#define TEMP_SENSORS_NODEID DT_INST(0, TEMP_SENSORS_COMPAT)
+
+#define TEMP_RT9490_FN(node_id, fn) \
+	COND_CODE_1(DT_NODE_HAS_PROP(node_id, thermistor), (fn(node_id)), ())
+
+#define FOREACH_TEMP_SENSOR(fn)                                             \
+	DT_FOREACH_STATUS_OKAY(PCT2075_COMPAT, fn)                          \
+	DT_FOREACH_STATUS_OKAY(TMP112_COMPAT, fn)                           \
+	DT_FOREACH_STATUS_OKAY(F75303_COMPAT, fn)                           \
+	DT_FOREACH_STATUS_OKAY(AMDR23M_COMPAT, fn)                          \
+	DT_FOREACH_STATUS_OKAY_VARGS(RT9490_CHG_COMPAT, TEMP_RT9490_FN, fn) \
+	DT_FOREACH_STATUS_OKAY(SB_TSI_COMPAT, fn)                           \
+	DT_FOREACH_STATUS_OKAY(THERMISTOR_COMPAT, fn)
+
+#define HAS_POWER_GOOD_PIN(node_id) DT_NODE_HAS_PROP(node_id, power_good_pin) ||
+
+#define ANY_INST_HAS_POWER_GOOD_PIN \
+	(DT_FOREACH_CHILD(TEMP_SENSORS_NODEID, HAS_POWER_GOOD_PIN) 0)
+
+/*
+ * Get the enum temp_sensor_id value from a child node under
+ * "cros-ec,temp-sensors".
+ *
+ * Example devicetree fragment:
+ *
+ *     temp_charger_thermistor: charger-thermistor {
+ *         compatible = "cros-ec,temp-sensor-thermistor";
+ *         thermistor = <&thermistor_3V3_30K9_47K_4050B>;
+ *         adc = <&adc_temp_charger>;
+ *     };
+ *
+ *     named-temp-sensors {
+ *         compatible = "cros-ec,temp-sensors";
+ *         temp_charger: charger-thermistor {
+ *             temp_host_high = <100>;
+ *             temp_host_halt = <105>;
+ *             temp_host_release_high = <80>;
+ *             sensor = <&temp_charger_thermistor>;
+ *         };
+ *     };
+ *
+ * Example usage to get the temperature sensor ID:
+ *
+ *     TEMP_SENSOR_ID(DT_NODELABEL(temp_charger))
+ *
+ * @param node_id: node id of a child of "cros-ec,temp-sensors" node
+ */
+#define TEMP_SENSOR_ID(node_id) DT_CAT(TEMP_SENSOR_, node_id)
+
+/*
+ * Get the enum temp_sensor_id value from a hardware device node.
+ *
+ * Example devicetree fragment:
+ *
+ *     temp_charger_thermistor: charger-thermistor {
+ *         compatible = "cros-ec,temp-sensor-thermistor";
+ *         thermistor = <&thermistor_3V3_30K9_47K_4050B>;
+ *         adc = <&adc_temp_charger>;
+ *     };
+ *
+ *     named-temp-sensors {
+ *         compatible = "cros-ec,temp-sensors";
+ *         temp_charger: charger-thermistor {
+ *             temp_host_high = <100>;
+ *             temp_host_halt = <105>;
+ *             temp_host_release_high = <80>;
+ *             sensor = <&temp_charger_thermistor>;
+ *         };
+ *     };
+ *
+ * Example usage to get the temperature sensor ID:
+ *
+ *     TEMP_SENSOR_ID_BY_DEV(DT_NODELABEL(temp_charger_thermistor))
+ *
+ * which equals:
+ *
+ *     TEMP_SENSOR_ID(DT_NODELABEL(temp_charger))
+ *
+ * @param node_id: node id of a hardware device node
+ */
+#define TEMP_SENSOR_ID_BY_DEV(node_id) DT_CAT(TEMP_SENSOR_DEV, node_id)
+
+#define TEMP_SENSOR_ID_DEV(named_id)                          \
+	TEMP_SENSOR_ID_BY_DEV(DT_PHANDLE(named_id, sensor)) = \
+		TEMP_SENSOR_ID(named_id)
+
+enum temp_sensor_id {
+	DT_FOREACH_CHILD_SEP(TEMP_SENSORS_NODEID, TEMP_SENSOR_ID, (, )),
+	DT_FOREACH_CHILD_SEP(TEMP_SENSORS_NODEID, TEMP_SENSOR_ID_DEV, (, )),
+	TEMP_SENSOR_COUNT,
+};
+
+/* PCT2075 access array */
+/*
+ * Get the PCT2075 sensor ID from a hardware device node.
+ *
+ * @param node_id: node id of a hardware PCT2075 sensor node
+ */
+#define PCT2075_SENSOR_ID(node_id) DT_CAT(PCT2075_, node_id)
+#define PCT2075_SENSOR_ID_WITH_COMMA(node_id) PCT2075_SENSOR_ID(node_id),
+
+/* clang-format off */
+enum pct2075_sensor {
+	DT_FOREACH_STATUS_OKAY(PCT2075_COMPAT, PCT2075_SENSOR_ID_WITH_COMMA)
+	PCT2075_COUNT,
+};
+/* clang-format on */
+
+#undef PCT2075_SENSOR_ID_WITH_COMMA
+
+/* TMP112 access array */
+/*
+ * Get the TMP112 sensor ID from a hardware device node.
+ *
+ * @param node_id: node id of a hardware TMP112 sensor node
+ */
+#define TMP112_SENSOR_ID(node_id) DT_CAT(TMP112_, node_id)
+#define TMP112_SENSOR_ID_WITH_COMMA(node_id) TMP112_SENSOR_ID(node_id),
+
+/* clang-format off */
+enum tmp112_sensor {
+	DT_FOREACH_STATUS_OKAY(TMP112_COMPAT, TMP112_SENSOR_ID_WITH_COMMA)
+	TMP112_COUNT,
+};
+/* clang-format on */
+
+#undef TMP112_SENSOR_ID_WITH_COMMA
+
+/* F75303 access array */
+/*
+ * Get the F75303 sensor ID.
+ *
+ * The F75303 driver only supports a single device instance on the board. Each
+ * device supports 3 temperature sensor types: local, remote1, and remote2.
+ * Use the temperature sensor type as the sensor ID.
+ *
+ * @param node_id: node id of a hardware F75303 sensor node
+ */
+#define F75303_SENSOR_ID(node_id) DT_STRING_TOKEN(node_id, temperature_type)
+
+/* AMDR23M access array */
+/*
+ * Get the AMDR23M sensor ID from a hardware device node.
+ *
+ * @param node_id: node id of a hardware AMDR23M sensor node
+ */
+#define AMDR23M_SENSOR_ID(node_id) DT_CAT(AMDR23M_, node_id)
+#define AMDR23M_SENSOR_ID_WITH_COMMA(node_id) AMDR23M_SENSOR_ID(node_id),
+
+enum amdr23m_sensor {
+	DT_FOREACH_STATUS_OKAY(AMDR23M_COMPAT, AMDR23M_SENSOR_ID_WITH_COMMA)
+		AMDR23M_COUNT,
+};
+
+#undef AMDR23M_SENSOR_ID_WITH_COMMA
+
+struct zephyr_temp_sensor {
+	/* Read sensor value in K into temp_ptr; return non-zero if error. */
+	int (*read)(const struct temp_sensor_t *sensor, int *temp_ptr);
+	void (*update_temperature)(int idx);
+	const struct thermistor_info *thermistor;
+#if ANY_INST_HAS_POWER_GOOD_PIN
+	const struct device *power_good_dev;
+	gpio_pin_t power_good_pin;
+#endif /* ANY_INST_HAS_POWER_GOOD_PIN */
+};
+
+#endif /* CONFIG_PLATFORM_EC_TEMP_SENSOR */
+
+#endif /* ZEPHYR_SHIM_INCLUDE_TEMP_SENSOR_TEMP_SENSOR_H_ */
diff --git a/zephyr/shim/include/usbc/amd_fp6_usb_mux.h b/zephyr/shim/include/usbc/amd_fp6_usb_mux.h
new file mode 100644
index 0000000000..a474a4eee4
--- /dev/null
+++ b/zephyr/shim/include/usbc/amd_fp6_usb_mux.h
@@ -0,0 +1,21 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __ZEPHYR_SHIM_AMD_FP6_USB_MUX_H
+#define __ZEPHYR_SHIM_AMD_FP6_USB_MUX_H
+
+#include "usb_mux.h"
+
+#define AMD_FP6_USB_MUX_COMPAT amd_usbc_mux_amd_fp6
+
+#define USB_MUX_CONFIG_AMD_FP6(mux_id)                         \
+	{                                                      \
+		USB_MUX_COMMON_FIELDS(mux_id),                 \
+			.driver = &amd_fp6_usb_mux_driver,     \
+			.i2c_port = I2C_PORT_BY_DEV(mux_id),   \
+			.i2c_addr_flags = DT_REG_ADDR(mux_id), \
+	}
+
+#endif /* __ZEPHYR_SHIM_AMD_FP6_USB_MUX_H */
diff --git a/zephyr/shim/include/usbc/anx7447_usb_mux.h b/zephyr/shim/include/usbc/anx7447_usb_mux.h
new file mode 100644
index 0000000000..7118e222db
--- /dev/null
+++ b/zephyr/shim/include/usbc/anx7447_usb_mux.h
@@ -0,0 +1,23 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __ZEPHYR_SHIM_ANX7447_USB_MUX_H
+#define __ZEPHYR_SHIM_ANX7447_USB_MUX_H
+
+#include "tcpm/anx7447_public.h"
+
+#define ANX7447_USB_MUX_COMPAT analogix_usbc_mux_anx7447
+
+/* clang-format off */
+#define USB_MUX_CONFIG_ANX7447(mux_id)                                         \
+	{                                                                      \
+		USB_MUX_COMMON_FIELDS(mux_id),                                 \
+		.driver = &anx7447_usb_mux_driver,                             \
+		.hpd_update = COND_CODE_1(DT_PROP(mux_id, hpd_update_enable),  \
+			(&anx7447_tcpc_update_hpd_status), (NULL)),            \
+	}
+/* clang-format on */
+
+#endif /* __ZEPHYR_SHIM_ANX7447_USB_MUX_H */
diff --git a/zephyr/shim/include/usbc/anx7452_usb_mux.h b/zephyr/shim/include/usbc/anx7452_usb_mux.h
new file mode 100644
index 0000000000..1b3cdbcc8e
--- /dev/null
+++ b/zephyr/shim/include/usbc/anx7452_usb_mux.h
@@ -0,0 +1,41 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __ZEPHYR_SHIM_ANX7452_USB_MUX_H
+#define __ZEPHYR_SHIM_ANX7452_USB_MUX_H
+
+#include "driver/retimer/anx7452_public.h"
+
+#define ANX7452_USB_MUX_COMPAT analogix_anx7452
+
+#define ANX7452_USB_EN_GPIO(mux_id) GPIO_SIGNAL(DT_PHANDLE(mux_id, usb_en_pin))
+
+#define ANX7452_DP_EN_GPIO(mux_id)                                \
+	COND_CODE_1(DT_NODE_HAS_PROP(mux_id, dp_en_pin),          \
+		    (GPIO_SIGNAL(DT_PHANDLE(mux_id, dp_en_pin))), \
+		    (GPIO_UNIMPLEMENTED))
+
+#define ANX7452_CONTROLS_CONFIG(mux_id)                         \
+	{                                                       \
+		.usb_enable_gpio = ANX7452_USB_EN_GPIO(mux_id), \
+		.dp_enable_gpio = ANX7452_DP_EN_GPIO(mux_id),   \
+	}
+
+#define USB_MUX_ANX7452_CONTROL_ARRAY(mux_id) \
+	[USB_MUX_PORT(mux_id)] = ANX7452_CONTROLS_CONFIG(mux_id),
+
+#define USB_MUX_ANX7452_CONTROLS_ARRAY                 \
+	DT_FOREACH_STATUS_OKAY(ANX7452_USB_MUX_COMPAT, \
+			       USB_MUX_ANX7452_CONTROL_ARRAY)
+
+#define USB_MUX_CONFIG_ANX7452(mux_id)                         \
+	{                                                      \
+		USB_MUX_COMMON_FIELDS(mux_id),                 \
+			.driver = &anx7452_usb_retimer_driver, \
+			.i2c_port = I2C_PORT_BY_DEV(mux_id),   \
+			.i2c_addr_flags = DT_REG_ADDR(mux_id), \
+	}
+
+#endif /* __ZEPHYR_SHIM_ANX7452_USB_MUX_H */
diff --git a/zephyr/shim/include/usbc/anx7483_usb_mux.h b/zephyr/shim/include/usbc/anx7483_usb_mux.h
new file mode 100644
index 0000000000..1a84d94da3
--- /dev/null
+++ b/zephyr/shim/include/usbc/anx7483_usb_mux.h
@@ -0,0 +1,23 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __ZEPHYR_SHIM_ANX7483_USB_MUX_H
+#define __ZEPHYR_SHIM_ANX7483_USB_MUX_H
+
+#include "driver/retimer/anx7483_public.h"
+
+#define ANX7483_USB_MUX_COMPAT analogix_anx7483
+
+/* clang-format off */
+#define USB_MUX_CONFIG_ANX7483(mux_id)                 \
+	{                                              \
+		USB_MUX_COMMON_FIELDS(mux_id),         \
+		.driver = &anx7483_usb_retimer_driver, \
+		.i2c_port = I2C_PORT_BY_DEV(mux_id),   \
+		.i2c_addr_flags = DT_REG_ADDR(mux_id), \
+	}
+/* clang-format on */
+
+#endif /* __ZEPHYR_SHIM_ANX7483_USB_MUX_H */
diff --git a/zephyr/shim/include/usbc/bb_retimer_usb_mux.h b/zephyr/shim/include/usbc/bb_retimer_usb_mux.h
new file mode 100644
index 0000000000..64dd9ba645
--- /dev/null
+++ b/zephyr/shim/include/usbc/bb_retimer_usb_mux.h
@@ -0,0 +1,115 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __ZEPHYR_SHIM_BB_RETIMER_USB_MUX_H
+#define __ZEPHYR_SHIM_BB_RETIMER_USB_MUX_H
+
+#include "driver/retimer/bb_retimer_public.h"
+
+#if CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_BB
+#define BB_RETIMER_USB_MUX_COMPAT intel_jhl8040r
+#elif CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_HB
+#define BB_RETIMER_USB_MUX_COMPAT intel_jhl9040r
+#endif
+
+/* clang-format off */
+#define USB_MUX_CONFIG_BB_RETIMER(mux_id)              \
+	{                                              \
+		USB_MUX_COMMON_FIELDS(mux_id),         \
+		.driver = &bb_usb_retimer,             \
+		.hpd_update = bb_retimer_hpd_update,   \
+		.i2c_port = I2C_PORT_BY_DEV(mux_id),   \
+		.i2c_addr_flags = DT_REG_ADDR(mux_id), \
+	}
+/* clang-format on */
+
+/**
+ * @brief Get reset gpio for @p mux_id retimer
+ *
+ * @param mux_id BB retimer DTS node
+ */
+#define BB_RETIMER_RESET_GPIO(mux_id) GPIO_SIGNAL(DT_PHANDLE(mux_id, reset_pin))
+
+/**
+ * @brief Get LS_EN gpio for @p mux_id retimer
+ *
+ * @param mux_id BB retimer DTS node
+ */
+#define BB_RETIMER_LS_EN_GPIO(mux_id)                             \
+	COND_CODE_1(DT_NODE_HAS_PROP(mux_id, ls_en_pin),          \
+		    (GPIO_SIGNAL(DT_PHANDLE(mux_id, ls_en_pin))), \
+		    (GPIO_UNIMPLEMENTED))
+
+#define BB_RETIMER_CONTROLS_CONFIG(mux_id)                         \
+	{                                                          \
+		.retimer_rst_gpio = BB_RETIMER_RESET_GPIO(mux_id), \
+		.usb_ls_en_gpio = BB_RETIMER_LS_EN_GPIO(mux_id),   \
+	}
+
+/**
+ * @brief Set entry in bb_controls array
+ *
+ * @param mux_id BB retimer node ID
+ */
+#define USB_MUX_BB_RETIMER_CONTROL_ARRAY(mux_id) \
+	[USB_MUX_PORT(mux_id)] = BB_RETIMER_CONTROLS_CONFIG(mux_id),
+
+/**
+ * @brief Call USB_MUX_BB_RETIMER_CONTROL_ARRAY for every BB retimer in DTS
+ */
+#define USB_MUX_BB_RETIMERS_CONTROLS_ARRAY                \
+	DT_FOREACH_STATUS_OKAY(BB_RETIMER_USB_MUX_COMPAT, \
+			       USB_MUX_BB_RETIMER_CONTROL_ARRAY)
+
+/**
+ * @brief Check if BB retimers @p id_1 and @p id_2 has matching configuration
+ *        Configuration match if reset and ls_en pins are the same for muxes
+ *        which are on the same USB-C port.
+ *
+ * @param id_1 First BB retimer DTS node
+ * @param id_2 Second BB retimer DTS node
+ */
+#define BB_RETIMER_CHECK_PAIR(id_1, id_2)                                      \
+	BUILD_ASSERT(USB_MUX_PORT(id_1) != USB_MUX_PORT(id_2) ||               \
+			     (BB_RETIMER_RESET_GPIO(id_1) ==                   \
+				      BB_RETIMER_RESET_GPIO(id_2) &&           \
+			      BB_RETIMER_LS_EN_GPIO(id_1) ==                   \
+				      BB_RETIMER_LS_EN_GPIO(id_2)),            \
+		     "BB retimers " #id_1 " and " #id_2 " have different pin " \
+		     "configuration and same USB-C port")
+
+/**
+ * @brief Check if BB retimers with @p inst instance number has matching
+ *        configuration with muxes of higher instance number on @p bb_list list.
+ *        Configuration match if reset and ls_en pins are the same for muxes
+ *        which are on the same USB-C port.
+ *
+ * @param inst Instance number of BB retimer mux
+ * @param bb_list List of BB retimers in instance number order
+ */
+#define BB_RETIMER_CHECK_INSTANCE_WITH_LIST(inst, bb_list)           \
+	FOR_EACH_FIXED_ARG(BB_RETIMER_CHECK_PAIR, (;),               \
+			   DT_INST(inst, BB_RETIMER_USB_MUX_COMPAT), \
+			   GET_ARGS_LESS_N(inst, __DEBRACKET bb_list))
+
+/**
+ * @brief Check if BB retimers on the @p bb_list list have matching
+ *        configurations (i.e. reset and ls_en pins are the same for muxes
+ *        which are on the same USB-C port). This check is required, because
+ *        USB_MUX_ENABLE_ALTERNATE() doesn't update bb_control[] array, so all
+ *        BB retimers needs to use the same GPIO pins.
+ *
+ * @param bb_list List of BB retimers in instance number order
+ */
+#define BB_RETIMER_CHECK_SAME_CONTROLS(bb_list)                     \
+	LISTIFY(DT_NUM_INST_STATUS_OKAY(BB_RETIMER_USB_MUX_COMPAT), \
+		BB_RETIMER_CHECK_INSTANCE_WITH_LIST, (;), bb_list);
+
+/** List of all BB retimers in DTS in instance number order */
+#define BB_RETIMER_INSTANCES_LIST                                             \
+	(LISTIFY(DT_NUM_INST_STATUS_OKAY(BB_RETIMER_USB_MUX_COMPAT), DT_INST, \
+		 (, ), BB_RETIMER_USB_MUX_COMPAT))
+
+#endif /* __ZEPHYR_SHIM_BB_RETIMER_USB_MUX_H */
diff --git a/zephyr/shim/include/usbc/bc12_pi3usb9201.h b/zephyr/shim/include/usbc/bc12_pi3usb9201.h
new file mode 100644
index 0000000000..701090133f
--- /dev/null
+++ b/zephyr/shim/include/usbc/bc12_pi3usb9201.h
@@ -0,0 +1,13 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/bc12/pi3usb9201_public.h"
+
+#define PI3USB9201_COMPAT pericom_pi3usb9201
+
+#define BC12_CHIP_PI3USB9201(id)        \
+	{                               \
+		.drv = &pi3usb9201_drv, \
+	},
diff --git a/zephyr/shim/include/usbc/bc12_rt1718s.h b/zephyr/shim/include/usbc/bc12_rt1718s.h
new file mode 100644
index 0000000000..e34f21c9e0
--- /dev/null
+++ b/zephyr/shim/include/usbc/bc12_rt1718s.h
@@ -0,0 +1,13 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "tcpm/rt1718s_public.h"
+
+#define RT1718S_BC12_COMPAT richtek_rt1718s_bc12
+
+#define BC12_CHIP_RT1718S(id)             \
+	{                                 \
+		.drv = &rt1718s_bc12_drv, \
+	},
diff --git a/zephyr/shim/include/usbc/bc12_rt1739.h b/zephyr/shim/include/usbc/bc12_rt1739.h
new file mode 100644
index 0000000000..9e5a622154
--- /dev/null
+++ b/zephyr/shim/include/usbc/bc12_rt1739.h
@@ -0,0 +1,13 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/ppc/rt1739.h"
+
+#define RT1739_BC12_COMPAT richtek_rt1739_bc12
+
+#define BC12_CHIP_RT1739(id)             \
+	{                                \
+		.drv = &rt1739_bc12_drv, \
+	},
diff --git a/zephyr/shim/include/usbc/bc12_rt9490.h b/zephyr/shim/include/usbc/bc12_rt9490.h
new file mode 100644
index 0000000000..c4323728f9
--- /dev/null
+++ b/zephyr/shim/include/usbc/bc12_rt9490.h
@@ -0,0 +1,13 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/charger/rt9490.h"
+
+#define RT9490_BC12_COMPAT richtek_rt9490
+
+#define BC12_CHIP_RT9490(id)             \
+	{                                \
+		.drv = &rt9490_bc12_drv, \
+	},
diff --git a/zephyr/shim/include/usbc/it5205_usb_mux.h b/zephyr/shim/include/usbc/it5205_usb_mux.h
new file mode 100644
index 0000000000..e143038f6c
--- /dev/null
+++ b/zephyr/shim/include/usbc/it5205_usb_mux.h
@@ -0,0 +1,23 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __ZEPHYR_SHIM_IT5205_USB_MUX_H
+#define __ZEPHYR_SHIM_IT5205_USB_MUX_H
+
+#include "usb_mux/it5205_public.h"
+
+#define IT5205_USB_MUX_COMPAT ite_it5205
+
+/* clang-format off */
+#define USB_MUX_CONFIG_IT5205(mux_id)                  \
+	{                                              \
+		USB_MUX_COMMON_FIELDS(mux_id),         \
+		.driver = &it5205_usb_mux_driver,      \
+		.i2c_port = I2C_PORT_BY_DEV(mux_id),   \
+		.i2c_addr_flags = DT_REG_ADDR(mux_id), \
+	}
+/* clang-format on */
+
+#endif /* __ZEPHYR_SHIM_IT5205_USB_MUX_H */
diff --git a/zephyr/shim/include/usbc/kb8010_usb_mux.h b/zephyr/shim/include/usbc/kb8010_usb_mux.h
new file mode 100644
index 0000000000..52177e57b1
--- /dev/null
+++ b/zephyr/shim/include/usbc/kb8010_usb_mux.h
@@ -0,0 +1,35 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __ZEPHYR_SHIM_KB8010_USB_MUX_H
+#define __ZEPHYR_SHIM_KB8010_USB_MUX_H
+
+#include "driver/retimer/kb8010_public.h"
+
+#define KB8010_USB_MUX_COMPAT kandou_kb8010
+
+#define KB8010_RST_GPIO(mux_id) GPIO_SIGNAL(DT_PHANDLE(mux_id, reset_pin))
+
+#define KB8010_CONTROLS_CONFIG(mux_id)                       \
+	{                                                    \
+		.retimer_rst_gpio = KB8010_RST_GPIO(mux_id), \
+	}
+
+#define USB_MUX_KB8010_CONTROL_ARRAY(mux_id) \
+	[USB_MUX_PORT(mux_id)] = KB8010_CONTROLS_CONFIG(mux_id),
+
+#define USB_MUX_KB8010_CONTROLS_ARRAY                 \
+	DT_FOREACH_STATUS_OKAY(KB8010_USB_MUX_COMPAT, \
+			       USB_MUX_KB8010_CONTROL_ARRAY)
+
+#define USB_MUX_CONFIG_KB8010(mux_id)                          \
+	{                                                      \
+		USB_MUX_COMMON_FIELDS(mux_id),                 \
+			.driver = &kb8010_usb_retimer_driver,  \
+			.i2c_port = I2C_PORT_BY_DEV(mux_id),   \
+			.i2c_addr_flags = DT_REG_ADDR(mux_id), \
+	}
+
+#endif /* __ZEPHYR_SHIM_KB8010_USB_MUX_H */
diff --git a/zephyr/shim/include/usbc/ppc.h b/zephyr/shim/include/usbc/ppc.h
new file mode 100644
index 0000000000..a8b5875543
--- /dev/null
+++ b/zephyr/shim/include/usbc/ppc.h
@@ -0,0 +1,112 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef ZEPHYR_CHROME_USBC_PPC_H
+#define ZEPHYR_CHROME_USBC_PPC_H
+
+#include "usbc/ppc_aoz1380.h"
+#include "usbc/ppc_ktu1125.h"
+#include "usbc/ppc_nx20p348x.h"
+#include "usbc/ppc_rt1739.h"
+#include "usbc/ppc_sn5s330.h"
+#include "usbc/ppc_syv682x.h"
+#include "usbc/utils.h"
+#include "usbc_ppc.h"
+
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+
+/**
+ * @brief List of all supported PPC drivers and emulators. Format is
+ * (compatible, config).
+ */
+/* clang-format off */
+#define PPC_DRIVERS                              \
+	(AOZ1380_COMPAT, PPC_CHIP_AOZ1380),      \
+	(KTU1125_COMPAT, PPC_CHIP_KTU1125),      \
+	(NX20P348X_COMPAT, PPC_CHIP_NX20P348X),  \
+	(RT1739_PPC_COMPAT, PPC_CHIP_RT1739),    \
+	(SN5S330_COMPAT, PPC_CHIP_SN5S330),      \
+	(SN5S330_EMUL_COMPAT, PPC_CHIP_SN5S330), \
+	(SYV682X_COMPAT, PPC_CHIP_SYV682X),      \
+	(SYV682X_EMUL_COMPAT, PPC_CHIP_SYV682X)
+/* clang-format on */
+
+/**
+ * @brief List of TCPC compatible strings only.
+ */
+#define PPC_DRIVER_COMPATS \
+	FOR_EACH(USBC_DRIVER_GET_COMPAT_COMMA, (), PPC_DRIVERS)
+
+/**
+ * @brief Create a unique name based on a PPC altnernate node.
+ *
+ *	ppc_syv682x_alt: syv682x@43 {
+ *		compatible = "silergy,syv682x";
+ *		status = "okay";
+ *		reg = <0x43>;
+ *		frs_en_gpio = <&ioex_usb_c0_frs_en>;
+ *		is-alt;
+ *	};
+ *
+ * Usage:
+ *	PPC_ALT_NAME_GET(DT_NODELABEL(ppc_syv682x_alt))
+ *
+ * expands to "ppc_alt_DT_N_S_i2c_100_S_syv682x_43"
+ */
+#define PPC_ALT_NAME_GET(node_id) DT_CAT(ppc_alt_, node_id)
+
+/**
+ * @brief Get the PPC alternate entry based on a nodelabel.
+ *
+ * Usage:
+ *	PPC_ALT_FROM_NODELABEL(ppc_syv682x_alt))
+ *
+ * expands to "ppc_alt_DT_N_S_i2c_100_S_syv682x_43"
+ */
+#define PPC_ALT_FROM_NODELABEL(lbl) (PPC_ALT_NAME_GET(DT_NODELABEL(lbl)))
+
+/**
+ * @brief - Forward declare a global struct ppc_config_t entry based on
+ * a single PPC altnerate from the devicetree.
+ */
+#define PPC_ALT_DECLARATION(node_id) \
+	extern const struct ppc_config_t PPC_ALT_NAME_GET(node_id)
+
+#define PPC_ALT_DECLARE(node_id, config_fn)         \
+	COND_CODE_1(DT_PROP_OR(node_id, is_alt, 0), \
+		    (PPC_ALT_DECLARATION(node_id);), ())
+
+/*
+ * Forward declare a struct ppc_config_t for every PPC node in the tree with the
+ * "is-alt" property set.
+ */
+DT_FOREACH_USBC_DRIVER_STATUS_OK_VARGS(PPC_ALT_DECLARE, PPC_DRIVERS)
+
+extern struct ppc_config_t ppc_chips_alt[];
+
+#define ALT_PPC_CHIP_CHK(usbc_id, usb_port_num)                              \
+	COND_CODE_1(DT_REG_HAS_IDX(usbc_id, usb_port_num),                   \
+		    (COND_CODE_1(DT_NODE_HAS_PROP(usbc_id, ppc_alt), (|| 1), \
+				 (|| 0))),                                   \
+		    (|| 0))
+
+#define PPC_ENABLE_ALTERNATE(usb_port_num)                                            \
+	do {                                                                          \
+		BUILD_ASSERT(                                                         \
+			(0 DT_FOREACH_STATUS_OKAY_VARGS(named_usbc_port,              \
+							ALT_PPC_CHIP_CHK,             \
+							usb_port_num)),               \
+			"Selected USB node does not exist or does not specify a PPC " \
+			"alternate chip");                                            \
+		memcpy(&ppc_chips[usb_port_num], &ppc_chips_alt[usb_port_num],        \
+		       sizeof(struct ppc_config_t));                                  \
+	} while (0)
+
+#define PPC_ENABLE_ALTERNATE_BY_NODELABEL(usb_port_num, nodelabel)           \
+	memcpy(&ppc_chips[usb_port_num], &PPC_ALT_FROM_NODELABEL(nodelabel), \
+	       sizeof(struct ppc_config_t))
+
+#endif /* ZEPHYR_CHROME_USBC_PPC_H */
diff --git a/zephyr/shim/include/usbc/ppc_aoz1380.h b/zephyr/shim/include/usbc/ppc_aoz1380.h
new file mode 100644
index 0000000000..d944fc8eac
--- /dev/null
+++ b/zephyr/shim/include/usbc/ppc_aoz1380.h
@@ -0,0 +1,14 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ppc/aoz1380_public.h"
+
+#define AOZ1380_COMPAT aoz_aoz1380
+
+/* Note: This chip has no i2c interface */
+#define PPC_CHIP_AOZ1380(id)        \
+	{                           \
+		.drv = &aoz1380_drv \
+	}
diff --git a/zephyr/shim/include/usbc/ppc_ktu1125.h b/zephyr/shim/include/usbc/ppc_ktu1125.h
new file mode 100644
index 0000000000..4ca7caca83
--- /dev/null
+++ b/zephyr/shim/include/usbc/ppc_ktu1125.h
@@ -0,0 +1,14 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ppc/ktu1125_public.h"
+
+#define KTU1125_COMPAT kinetic_ktu1125
+
+#define PPC_CHIP_KTU1125(id)                                            \
+	{                                                               \
+		.i2c_port = I2C_PORT_BY_DEV(id),                        \
+		.i2c_addr_flags = DT_REG_ADDR(id), .drv = &ktu1125_drv, \
+	}
diff --git a/zephyr/shim/include/usbc/ppc_nx20p348x.h b/zephyr/shim/include/usbc/ppc_nx20p348x.h
new file mode 100644
index 0000000000..14336ff215
--- /dev/null
+++ b/zephyr/shim/include/usbc/ppc_nx20p348x.h
@@ -0,0 +1,14 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ppc/nx20p348x_public.h"
+
+#define NX20P348X_COMPAT nxp_nx20p348x
+
+#define PPC_CHIP_NX20P348X(id)                                           \
+	{                                                                \
+		.i2c_port = I2C_PORT_BY_DEV(id),                         \
+		.i2c_addr_flags = DT_REG_ADDR(id), .drv = &nx20p348x_drv \
+	}
diff --git a/zephyr/shim/include/usbc/ppc_rt1739.h b/zephyr/shim/include/usbc/ppc_rt1739.h
new file mode 100644
index 0000000000..c740c1c43a
--- /dev/null
+++ b/zephyr/shim/include/usbc/ppc_rt1739.h
@@ -0,0 +1,17 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/ppc/rt1739.h"
+
+#define RT1739_PPC_COMPAT richtek_rt1739_ppc
+
+#define PPC_CHIP_RT1739(id)                                                \
+	{                                                                  \
+		.i2c_port = I2C_PORT_BY_DEV(id),                           \
+		.i2c_addr_flags = DT_REG_ADDR(id), .drv = &rt1739_ppc_drv, \
+		.frs_en = COND_CODE_1(                                     \
+			DT_NODE_HAS_PROP(id, frs_en_gpio),                 \
+			(GPIO_SIGNAL(DT_PHANDLE(id, frs_en_gpio))), (0)),  \
+	}
diff --git a/zephyr/shim/include/usbc/ppc_sn5s330.h b/zephyr/shim/include/usbc/ppc_sn5s330.h
new file mode 100644
index 0000000000..eef2fca843
--- /dev/null
+++ b/zephyr/shim/include/usbc/ppc_sn5s330.h
@@ -0,0 +1,15 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ppc/sn5s330_public.h"
+
+#define SN5S330_COMPAT ti_sn5s330
+#define SN5S330_EMUL_COMPAT cros_sn5s330_emul
+
+#define PPC_CHIP_SN5S330(id)                                           \
+	{                                                              \
+		.i2c_port = I2C_PORT_BY_DEV(id),                       \
+		.i2c_addr_flags = DT_REG_ADDR(id), .drv = &sn5s330_drv \
+	}
diff --git a/zephyr/shim/include/usbc/ppc_syv682x.h b/zephyr/shim/include/usbc/ppc_syv682x.h
new file mode 100644
index 0000000000..87432c2b62
--- /dev/null
+++ b/zephyr/shim/include/usbc/ppc_syv682x.h
@@ -0,0 +1,18 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ppc/syv682x_public.h"
+
+#define SYV682X_COMPAT silergy_syv682x
+#define SYV682X_EMUL_COMPAT zephyr_syv682x_emul
+
+#define PPC_CHIP_SYV682X(id)                                              \
+	{                                                                 \
+		.i2c_port = I2C_PORT_BY_DEV(id),                          \
+		.i2c_addr_flags = DT_REG_ADDR(id), .drv = &syv682x_drv,   \
+		.frs_en = COND_CODE_1(                                    \
+			DT_NODE_HAS_PROP(id, frs_en_gpio),                \
+			(GPIO_SIGNAL(DT_PHANDLE(id, frs_en_gpio))), (0)), \
+	}
diff --git a/zephyr/shim/include/usbc/ps8743_usb_mux.h b/zephyr/shim/include/usbc/ps8743_usb_mux.h
new file mode 100644
index 0000000000..7f9c5e2139
--- /dev/null
+++ b/zephyr/shim/include/usbc/ps8743_usb_mux.h
@@ -0,0 +1,24 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __ZEPHYR_SHIM_PS8743_USB_MUX_H
+#define __ZEPHYR_SHIM_PS8743_USB_MUX_H
+
+#include "usb_mux/ps8743_public.h"
+
+#define PS8743_USB_MUX_COMPAT parade_ps8743
+#define PS8743_EMUL_COMPAT zephyr_ps8743_emul
+
+/* clang-format off */
+#define USB_MUX_CONFIG_PS8743(mux_id)                  \
+	{                                              \
+		USB_MUX_COMMON_FIELDS(mux_id),         \
+		.driver = &ps8743_usb_mux_driver,      \
+		.i2c_port = I2C_PORT_BY_DEV(mux_id),   \
+		.i2c_addr_flags = DT_REG_ADDR(mux_id), \
+	}
+/* clang-format on */
+
+#endif /* __ZEPHYR_SHIM_PS8743_USB_MUX_H */
diff --git a/zephyr/shim/include/usbc/ps8818_usb_mux.h b/zephyr/shim/include/usbc/ps8818_usb_mux.h
new file mode 100644
index 0000000000..400f238366
--- /dev/null
+++ b/zephyr/shim/include/usbc/ps8818_usb_mux.h
@@ -0,0 +1,23 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __ZEPHYR_SHIM_PS8818_USB_MUX_H
+#define __ZEPHYR_SHIM_PS8818_USB_MUX_H
+
+#include "driver/retimer/ps8818_public.h"
+
+#define PS8818_USB_MUX_COMPAT parade_ps8818
+
+/* clang-format off */
+#define USB_MUX_CONFIG_PS8818(mux_id)                  \
+	{                                              \
+		USB_MUX_COMMON_FIELDS(mux_id),         \
+		.driver = &ps8818_usb_retimer_driver,  \
+		.i2c_port = I2C_PORT_BY_DEV(mux_id),   \
+		.i2c_addr_flags = DT_REG_ADDR(mux_id), \
+	}
+/* clang-format on */
+
+#endif /* __ZEPHYR_SHIM_PS8818_USB_MUX_H */
diff --git a/zephyr/shim/include/usbc/tcpc_anx7447.h b/zephyr/shim/include/usbc/tcpc_anx7447.h
new file mode 100644
index 0000000000..4da2e223ce
--- /dev/null
+++ b/zephyr/shim/include/usbc/tcpc_anx7447.h
@@ -0,0 +1,25 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "tcpm/anx7447_public.h"
+
+#include <zephyr/devicetree.h>
+
+#define ANX7447_TCPC_COMPAT analogix_anx7447_tcpc
+
+/* clang-format off */
+#define TCPC_CONFIG_ANX7447(id)                                                \
+	{                                                                      \
+		.bus_type = EC_BUS_TYPE_I2C,                                   \
+		.i2c_info = {                                                  \
+			.port = I2C_PORT_BY_DEV(id),                           \
+			.addr_flags = DT_REG_ADDR(id),                         \
+		},                                                             \
+		.drv = &anx7447_tcpm_drv,                                      \
+		.flags = DT_PROP(id, tcpc_flags),                              \
+		.irq_gpio = GPIO_DT_SPEC_GET_OR(id, irq_gpios, {}),            \
+		.rst_gpio = GPIO_DT_SPEC_GET_OR(id, rst_gpios, {}),            \
+	}
+/* clang-format on */
diff --git a/zephyr/shim/include/usbc/tcpc_anx7447_emul.h b/zephyr/shim/include/usbc/tcpc_anx7447_emul.h
new file mode 100644
index 0000000000..0472479b5a
--- /dev/null
+++ b/zephyr/shim/include/usbc/tcpc_anx7447_emul.h
@@ -0,0 +1,24 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/tcpm/anx7447_public.h"
+
+#include <zephyr/devicetree.h>
+
+#define ANX7447_EMUL_COMPAT cros_anx7447_tcpc_emul
+
+/* clang-format off */
+#define TCPC_CONFIG_ANX7447_EMUL(id)                                           \
+	{                                                                      \
+		.bus_type = EC_BUS_TYPE_I2C,                                   \
+		.i2c_info = {                                                  \
+			.port = I2C_PORT_BY_DEV(id),                           \
+			.addr_flags = DT_REG_ADDR(id),                         \
+		},                                                             \
+		.drv = &anx7447_tcpm_drv,                                      \
+		.irq_gpio = GPIO_DT_SPEC_GET_OR(id, irq_gpios, {}),            \
+		.rst_gpio = GPIO_DT_SPEC_GET_OR(id, rst_gpios, {}),            \
+	}
+/* clang-format on */
diff --git a/zephyr/shim/include/usbc/tcpc_ccgxxf.h b/zephyr/shim/include/usbc/tcpc_ccgxxf.h
new file mode 100644
index 0000000000..1f1360b185
--- /dev/null
+++ b/zephyr/shim/include/usbc/tcpc_ccgxxf.h
@@ -0,0 +1,30 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/tcpm/ccgxxf.h"
+
+#include <zephyr/devicetree.h>
+
+#define CCGXXF_TCPC_COMPAT cypress_ccgxxf
+
+/* clang-format off */
+#define TCPC_CONFIG_CCGXXF(id)                                                 \
+	{                                                                      \
+		.bus_type = EC_BUS_TYPE_I2C,                                   \
+		.i2c_info = {                                                  \
+			.port = I2C_PORT_BY_DEV(id),                           \
+			.addr_flags = DT_REG_ADDR(id),                         \
+		},                                                             \
+		.drv = &ccgxxf_tcpm_drv,                                       \
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,                              \
+		COND_CODE_1(CONFIG_PLATFORM_EC_TCPC_INTERRUPT,                 \
+			(.irq_gpio = GPIO_DT_SPEC_GET_OR(id, irq_gpios, {}),   \
+			 .rst_gpio = GPIO_DT_SPEC_GET_OR(id, rst_gpios, {})),  \
+			(.alert_signal = COND_CODE_1(                          \
+				DT_NODE_HAS_PROP(id, int_pin),                 \
+				(GPIO_SIGNAL(DT_PHANDLE(id, int_pin))),        \
+				(GPIO_LIMIT)))),                               \
+	}
+/* clang-format on */
diff --git a/zephyr/shim/include/usbc/tcpc_fusb302.h b/zephyr/shim/include/usbc/tcpc_fusb302.h
new file mode 100644
index 0000000000..9ac651fa10
--- /dev/null
+++ b/zephyr/shim/include/usbc/tcpc_fusb302.h
@@ -0,0 +1,33 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/tcpm/fusb302.h"
+#include "usbc/utils.h"
+
+#include <zephyr/devicetree.h>
+
+#define FUSB302_TCPC_COMPAT fairchild_fusb302
+
+/* clang-format off */
+#define TCPC_CONFIG_FUSB302(id)                                                \
+	{                                                                      \
+		.bus_type = EC_BUS_TYPE_I2C,                                   \
+		.i2c_info = {                                                  \
+			.port = I2C_PORT_BY_DEV(id),                           \
+			.addr_flags = DT_REG_ADDR(id),                         \
+		},                                                             \
+		.drv = &fusb302_tcpm_drv,                                      \
+		COND_CODE_1(CONFIG_PLATFORM_EC_TCPC_INTERRUPT,                 \
+			(.irq_gpio = GPIO_DT_SPEC_GET_OR(id, irq_gpios, {}),   \
+			 .rst_gpio = GPIO_DT_SPEC_GET_OR(id, rst_gpios, {})),  \
+			(.alert_signal = COND_CODE_1(                          \
+				DT_NODE_HAS_PROP(id, int_pin),                 \
+				(GPIO_SIGNAL(DT_PHANDLE(id, int_pin))),        \
+				(GPIO_LIMIT)))),                               \
+	}
+/* clang-format on */
+
+DT_FOREACH_STATUS_OKAY(FUSB302_TCPC_COMPAT,
+		       TCPC_VERIFY_NO_FLAGS_ACTIVE_ALERT_HIGH)
diff --git a/zephyr/shim/include/usbc/tcpc_generic_emul.h b/zephyr/shim/include/usbc/tcpc_generic_emul.h
new file mode 100644
index 0000000000..9fcff480eb
--- /dev/null
+++ b/zephyr/shim/include/usbc/tcpc_generic_emul.h
@@ -0,0 +1,30 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/tcpm/tcpci.h"
+#include "i2c/i2c.h"
+
+#include <zephyr/devicetree.h>
+
+#define TCPCI_EMUL_COMPAT cros_tcpci_generic_emul
+
+/* clang-format off */
+#define TCPC_CONFIG_TCPCI_EMUL(id)                                             \
+	{                                                                      \
+		.bus_type = EC_BUS_TYPE_I2C,                                   \
+		.i2c_info = {                                                  \
+			.port = I2C_PORT_BY_DEV(id),                           \
+			.addr_flags = DT_REG_ADDR(id),                         \
+		},                                                             \
+		.drv = &tcpci_tcpm_drv,                                        \
+		COND_CODE_1(CONFIG_PLATFORM_EC_TCPC_INTERRUPT,                 \
+			(.irq_gpio = GPIO_DT_SPEC_GET_OR(id, irq_gpios, {}),   \
+			 .rst_gpio = GPIO_DT_SPEC_GET_OR(id, rst_gpios, {})),  \
+			(.alert_signal = COND_CODE_1(                          \
+				DT_NODE_HAS_PROP(id, int_pin),                 \
+				(GPIO_SIGNAL(DT_PHANDLE(id, int_pin))),        \
+				(GPIO_LIMIT)))),                               \
+	}
+/* clang-format on */
diff --git a/zephyr/shim/include/usbc/tcpc_it8xxx2.h b/zephyr/shim/include/usbc/tcpc_it8xxx2.h
new file mode 100644
index 0000000000..aa36d0c39e
--- /dev/null
+++ b/zephyr/shim/include/usbc/tcpc_it8xxx2.h
@@ -0,0 +1,16 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/tcpm/it8xxx2_pd_public.h"
+
+#include <zephyr/devicetree.h>
+
+#define IT8XXX2_TCPC_COMPAT ite_it8xxx2_usbpd
+
+#define TCPC_CONFIG_IT8XXX2(id)                                             \
+	{                                                                   \
+		.bus_type = EC_BUS_TYPE_EMBEDDED, .drv = &it8xxx2_tcpm_drv, \
+		.flags = 0,                                                 \
+	}
diff --git a/zephyr/shim/include/usbc/tcpc_nct38xx.h b/zephyr/shim/include/usbc/tcpc_nct38xx.h
new file mode 100644
index 0000000000..2381a4f7db
--- /dev/null
+++ b/zephyr/shim/include/usbc/tcpc_nct38xx.h
@@ -0,0 +1,44 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_TCPC_NCT38XX_H
+#define __CROS_EC_TCPC_NCT38XX_H
+
+#include "driver/tcpm/nct38xx.h"
+
+#include <zephyr/devicetree.h>
+
+#define NCT38XX_TCPC_COMPAT nuvoton_nct38xx
+
+/* clang-format off */
+#define TCPC_CONFIG_NCT38XX(id)                                                \
+	{                                                                      \
+		.bus_type = EC_BUS_TYPE_I2C,                                   \
+		.i2c_info = {                                                  \
+			.port = I2C_PORT_BY_DEV(id),                           \
+			.addr_flags = DT_REG_ADDR(id),                         \
+		},                                                             \
+		.drv = &nct38xx_tcpm_drv,                                      \
+		.flags = DT_PROP(id, tcpc_flags),                              \
+		COND_CODE_1(CONFIG_PLATFORM_EC_TCPC_INTERRUPT,                 \
+			(.irq_gpio = GPIO_DT_SPEC_GET_OR(id, irq_gpios, {}),   \
+			 .rst_gpio = GPIO_DT_SPEC_GET_OR(id, rst_gpios, {})),  \
+			(.alert_signal = COND_CODE_1(                          \
+				DT_NODE_HAS_PROP(id, int_pin),                 \
+				(GPIO_SIGNAL(DT_PHANDLE(id, int_pin))),        \
+				(GPIO_LIMIT)))),                               \
+	}
+/* clang-format on */
+
+/**
+ * @brief Get the NCT38XX GPIO device from the TCPC port enumeration
+ *
+ * @param port The enumeration of TCPC port
+ *
+ * @return NULL if failed, otherwise a pointer to NCT38XX GPIO device
+ */
+const struct device *nct38xx_get_gpio_device_from_port(const int port);
+
+#endif /* __CROS_EC_TCPC_NCT38XX_H */
diff --git a/zephyr/shim/include/usbc/tcpc_ps8xxx.h b/zephyr/shim/include/usbc/tcpc_ps8xxx.h
new file mode 100644
index 0000000000..f68e30a6c1
--- /dev/null
+++ b/zephyr/shim/include/usbc/tcpc_ps8xxx.h
@@ -0,0 +1,39 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_TCPC_PS8XXX_H
+#define __CROS_EC_TCPC_PS8XXX_H
+
+#include "driver/tcpm/ps8xxx_public.h"
+#include "usbc/utils.h"
+
+#include <zephyr/devicetree.h>
+
+#define PS8XXX_COMPAT parade_ps8xxx
+
+/* clang-format off */
+#define TCPC_CONFIG_PS8XXX(id)                                                 \
+	{                                                                      \
+		.bus_type = EC_BUS_TYPE_I2C,                                   \
+		.i2c_info = {                                                  \
+			.port = I2C_PORT_BY_DEV(id),                           \
+			.addr_flags = DT_REG_ADDR(id),                         \
+		},                                                             \
+		.drv = &ps8xxx_tcpm_drv,                                       \
+		.flags = DT_PROP(id, tcpc_flags),                              \
+		COND_CODE_1(CONFIG_PLATFORM_EC_TCPC_INTERRUPT,                 \
+			(.irq_gpio = GPIO_DT_SPEC_GET_OR(id, irq_gpios, {}),   \
+			 .rst_gpio = GPIO_DT_SPEC_GET_OR(id, rst_gpios, {})),  \
+			(.alert_signal = COND_CODE_1(                          \
+				DT_NODE_HAS_PROP(id, int_pin),                 \
+				(GPIO_SIGNAL(DT_PHANDLE(id, int_pin))),        \
+				(GPIO_LIMIT)))                                 \
+		),                                                             \
+	}
+/* clang-format on */
+
+DT_FOREACH_STATUS_OKAY(PS8XXX_COMPAT, TCPC_VERIFY_NO_FLAGS_ACTIVE_ALERT_HIGH)
+
+#endif /* __CROS_EC_TCPC_PS8XXX_H */
diff --git a/zephyr/shim/include/usbc/tcpc_ps8xxx_emul.h b/zephyr/shim/include/usbc/tcpc_ps8xxx_emul.h
new file mode 100644
index 0000000000..493150ebaa
--- /dev/null
+++ b/zephyr/shim/include/usbc/tcpc_ps8xxx_emul.h
@@ -0,0 +1,29 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/tcpm/ps8xxx_public.h"
+
+#include <zephyr/devicetree.h>
+
+#define PS8XXX_EMUL_COMPAT cros_ps8xxx_emul
+
+/* clang-format off */
+#define TCPC_CONFIG_PS8XXX_EMUL(id)                                            \
+	{                                                                      \
+		.bus_type = EC_BUS_TYPE_I2C,                                   \
+		.i2c_info = {                                                  \
+			.port = I2C_PORT_BY_DEV(id),                           \
+			.addr_flags = DT_REG_ADDR(id),                         \
+		},                                                             \
+		.drv = &ps8xxx_tcpm_drv,                                       \
+		COND_CODE_1(CONFIG_PLATFORM_EC_TCPC_INTERRUPT,                 \
+			(.irq_gpio = GPIO_DT_SPEC_GET_OR(id, irq_gpios, {}),   \
+			 .rst_gpio = GPIO_DT_SPEC_GET_OR(id, rst_gpios, {})),  \
+			(.alert_signal = COND_CODE_1(                          \
+				DT_NODE_HAS_PROP(id, int_pin),                 \
+				(GPIO_SIGNAL(DT_PHANDLE(id, int_pin))),        \
+				(GPIO_LIMIT)))),                               \
+	}
+/* clang-format on */
diff --git a/zephyr/shim/include/usbc/tcpc_raa489000.h b/zephyr/shim/include/usbc/tcpc_raa489000.h
new file mode 100644
index 0000000000..c721da5ea4
--- /dev/null
+++ b/zephyr/shim/include/usbc/tcpc_raa489000.h
@@ -0,0 +1,23 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/tcpm/raa489000.h"
+
+#include <zephyr/devicetree.h>
+
+#define RAA489000_TCPC_COMPAT renesas_raa489000
+
+/* clang-format off */
+#define TCPC_CONFIG_RAA489000(id)                      \
+	{                                              \
+		.bus_type = EC_BUS_TYPE_I2C,           \
+		.i2c_info = {                          \
+			.port = I2C_PORT_BY_DEV(id),   \
+			.addr_flags = DT_REG_ADDR(id), \
+		},                                     \
+		.drv = &raa489000_tcpm_drv,            \
+		.flags = DT_PROP(id, tcpc_flags),      \
+	}
+/* clang-format on */
diff --git a/zephyr/shim/include/usbc/tcpc_rt1715.h b/zephyr/shim/include/usbc/tcpc_rt1715.h
new file mode 100644
index 0000000000..225e483932
--- /dev/null
+++ b/zephyr/shim/include/usbc/tcpc_rt1715.h
@@ -0,0 +1,28 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/tcpm/rt1715.h"
+#include "usbc/utils.h"
+
+#include <zephyr/devicetree.h>
+
+#define RT1715_TCPC_COMPAT richtek_rt1715_tcpc
+
+/* clang-format off */
+#define TCPC_CONFIG_RT1715(id)                                                 \
+	{                                                                      \
+		.bus_type = EC_BUS_TYPE_I2C,                                   \
+		.i2c_info = {                                                  \
+			.port = I2C_PORT_BY_DEV(id),                           \
+			.addr_flags = DT_REG_ADDR(id),                         \
+		},                                                             \
+		.drv = &rt1715_tcpm_drv,                                       \
+		.flags = DT_PROP(id, tcpc_flags),                              \
+		.irq_gpio = GPIO_DT_SPEC_GET_OR(id, irq_gpios, {}), \
+	}
+/* clang-format on */
+
+DT_FOREACH_STATUS_OKAY(RT1715_TCPC_COMPAT,
+		       TCPC_VERIFY_NO_FLAGS_ACTIVE_ALERT_HIGH)
diff --git a/zephyr/shim/include/usbc/tcpc_rt1718s.h b/zephyr/shim/include/usbc/tcpc_rt1718s.h
new file mode 100644
index 0000000000..198939175b
--- /dev/null
+++ b/zephyr/shim/include/usbc/tcpc_rt1718s.h
@@ -0,0 +1,28 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "tcpm/rt1718s_public.h"
+#include "usbc/utils.h"
+
+#include <zephyr/devicetree.h>
+
+#define RT1718S_TCPC_COMPAT richtek_rt1718s_tcpc
+
+/* clang-format off */
+#define TCPC_CONFIG_RT1718S(id)                                                \
+	{                                                                      \
+		.bus_type = EC_BUS_TYPE_I2C,                                   \
+		.i2c_info = {                                                  \
+			.port = I2C_PORT_BY_DEV(id),                           \
+			.addr_flags = DT_REG_ADDR(id),                         \
+		},                                                             \
+		.drv = &rt1718s_tcpm_drv,                                      \
+		.flags = DT_PROP(id, tcpc_flags),                              \
+		.irq_gpio = GPIO_DT_SPEC_GET_OR(id, irq_gpios, {}),            \
+	}
+/* clang-format on */
+
+DT_FOREACH_STATUS_OKAY(RT1718S_TCPC_COMPAT,
+		       TCPC_VERIFY_NO_FLAGS_ACTIVE_ALERT_HIGH)
diff --git a/zephyr/shim/include/usbc/tcpc_rt1718s_emul.h b/zephyr/shim/include/usbc/tcpc_rt1718s_emul.h
new file mode 100644
index 0000000000..0d9a95cbea
--- /dev/null
+++ b/zephyr/shim/include/usbc/tcpc_rt1718s_emul.h
@@ -0,0 +1,28 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __ZEPHYR_SHIM_TCPC_RT1718S_EMUL_H
+#define __ZEPHYR_SHIM_TCPC_RT1718S_EMUL_H
+
+#include "driver/tcpm/rt1718s_public.h"
+
+#include <zephyr/devicetree.h>
+
+#define RT1718S_EMUL_COMPAT cros_rt1718s_tcpc_emul
+
+/* clang-format off */
+#define TCPC_CONFIG_RT1718S_EMUL(id)                                           \
+	{                                                                      \
+		.bus_type = EC_BUS_TYPE_I2C,                                   \
+		.i2c_info = {                                                  \
+			.port = I2C_PORT_BY_DEV(id),                           \
+			.addr_flags = DT_REG_ADDR(id),                         \
+		},                                                             \
+		.drv = &rt1718s_tcpm_drv,                                      \
+		.irq_gpio = GPIO_DT_SPEC_GET_OR(id, irq_gpios, {}),            \
+	}
+/* clang-format on */
+
+#endif /* __ZEPHYR_SHIM_TPCP_RT1718S_EMUL_H */
diff --git a/zephyr/shim/include/usbc/tcpci.h b/zephyr/shim/include/usbc/tcpci.h
new file mode 100644
index 0000000000..179a309568
--- /dev/null
+++ b/zephyr/shim/include/usbc/tcpci.h
@@ -0,0 +1,120 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/tcpm/tcpci.h"
+#include "usbc/tcpc_anx7447.h"
+#include "usbc/tcpc_anx7447_emul.h"
+#include "usbc/tcpc_ccgxxf.h"
+#include "usbc/tcpc_fusb302.h"
+#include "usbc/tcpc_generic_emul.h"
+#include "usbc/tcpc_nct38xx.h"
+#include "usbc/tcpc_ps8xxx.h"
+#include "usbc/tcpc_ps8xxx_emul.h"
+#include "usbc/tcpc_raa489000.h"
+#include "usbc/tcpc_rt1715.h"
+#include "usbc/tcpc_rt1718s.h"
+#include "usbc/utils.h"
+
+#include <zephyr/devicetree.h>
+
+#define TCPCI_COMPAT cros_ec_tcpci
+
+/**
+ * @brief List of all supported TCPC drivers and emulators. Format is
+ * (compatible, config).
+ */
+/* clang-format off */
+#define TCPC_DRIVERS                                     \
+	(ANX7447_TCPC_COMPAT, TCPC_CONFIG_ANX7447),      \
+	(CCGXXF_TCPC_COMPAT, TCPC_CONFIG_CCGXXF),        \
+	(FUSB302_TCPC_COMPAT, TCPC_CONFIG_FUSB302),      \
+	(IT8XXX2_TCPC_COMPAT, TCPC_CONFIG_IT8XXX2),      \
+	(PS8XXX_COMPAT, TCPC_CONFIG_PS8XXX),             \
+	(NCT38XX_TCPC_COMPAT, TCPC_CONFIG_NCT38XX),      \
+	(RAA489000_TCPC_COMPAT, TCPC_CONFIG_RAA489000),  \
+	(RT1718S_TCPC_COMPAT, TCPC_CONFIG_RT1718S),      \
+	(RT1715_TCPC_COMPAT, TCPC_CONFIG_RT1715),        \
+	(TCPCI_COMPAT, TCPC_CONFIG_TCPCI),               \
+	(TCPCI_EMUL_COMPAT, TCPC_CONFIG_TCPCI_EMUL),     \
+	(PS8XXX_EMUL_COMPAT, TCPC_CONFIG_PS8XXX_EMUL),   \
+	(ANX7447_EMUL_COMPAT, TCPC_CONFIG_ANX7447_EMUL), \
+	(RT1718S_EMUL_COMPAT, TCPC_CONFIG_RT1718S_EMUL)
+/* clang-format on */
+
+/**
+ * @brief List of TCPC compatible strings only.
+ */
+#define TCPC_DRIVER_COMPATS \
+	FOR_EACH(USBC_DRIVER_GET_COMPAT_COMMA, (), TCPC_DRIVERS)
+
+/* clang-format off */
+#define TCPC_CONFIG_TCPCI(id)                            \
+	{                                                \
+		.bus_type = EC_BUS_TYPE_I2C,           \
+		.i2c_info = {                          \
+			.port = I2C_PORT_BY_DEV(id),   \
+			.addr_flags = DT_REG_ADDR(id), \
+		},                                     \
+		.drv = &tcpci_tcpm_drv, \
+	}
+/* clang-format on */
+
+/**
+ * @brief Create a unique name based on a TCPC alternate node.
+ *
+ *	tcpc_rt1715_alt: rt1715@43 {
+ *		compatible = "richtek,rt1715-tcpc";
+ *		status = "okay";
+ *		reg = <0x43>;
+ *		is-alt;
+ *	};
+ *
+ * Usage:
+ *	TCPC_ALT_NAME_GET(DT_NODELABEL(tcpc_rt1715_alt))
+ *
+ * expands to "tcpc_alt_DT_N_S_i2c_100_S_rt1715_43"
+ */
+#define TCPC_ALT_NAME_GET(node_id) DT_CAT(tcpc_alt_, node_id)
+
+/**
+ * @brief Get the TCPC alternate entry based on a nodelabel.
+ *
+ * Usage:
+ *	TCPC_ALT_FROM_NODELABEL(tcpc_rt1715_alt)
+ *
+ * expands to "tcpc_alt_DT_N_S_i2c_100_S_rt1715_43"
+ */
+#define TCPC_ALT_FROM_NODELABEL(lbl) (TCPC_ALT_NAME_GET(DT_NODELABEL(lbl)))
+
+/**
+ * @brief - Forward declare a global struct tcpc_config_t entry based on
+ * a single TCPC alternate from the devicetree.
+ */
+#define TCPC_ALT_DECLARATION(node_id) \
+	extern const struct tcpc_config_t TCPC_ALT_NAME_GET(node_id)
+
+/**
+ * @brief Forward declare a global "struct tcpc_config_t" entry, only if
+ * the TCPC node contains the "is-alt" property.
+ *
+ * @param node_id Node ID of the TCPC device
+ * @param config_fn Unused by this macro, but required by the
+ *                  DT_FOREACH_USBC_DRIVER_STATUS_OK_VARGS() wrapper.
+ */
+#define TCPC_ALT_DECLARE(node_id, config_fn)        \
+	COND_CODE_1(DT_PROP_OR(node_id, is_alt, 0), \
+		    (TCPC_ALT_DECLARATION(node_id);), ())
+
+/*
+ * For all TCPC drivers/emulators, forward declare a struct
+ * tcpc_config_t for every node in the tree with the "is-alt" property
+ * set.
+ */
+DT_FOREACH_USBC_DRIVER_STATUS_OK_VARGS(TCPC_ALT_DECLARE, TCPC_DRIVERS)
+
+#define TCPC_ENABLE_ALTERNATE_BY_NODELABEL(usb_port_num, nodelabel) \
+	memcpy(&tcpc_config[usb_port_num],                          \
+	       &TCPC_ALT_FROM_NODELABEL(nodelabel),                 \
+	       sizeof(struct tcpc_config_t))
diff --git a/zephyr/shim/include/usbc/tcpci_usb_mux.h b/zephyr/shim/include/usbc/tcpci_usb_mux.h
new file mode 100644
index 0000000000..3c8f062920
--- /dev/null
+++ b/zephyr/shim/include/usbc/tcpci_usb_mux.h
@@ -0,0 +1,47 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __ZEPHYR_SHIM_TCPCI_USB_MUX_H
+#define __ZEPHYR_SHIM_TCPCI_USB_MUX_H
+
+#include "dt-bindings/usbc_mux.h"
+#include "tcpm/ps8xxx_public.h"
+#include "tcpm/tcpci.h"
+
+#define TCPCI_TCPM_USB_MUX_COMPAT cros_ec_usbc_mux_tcpci
+#define PS8XXX_USB_MUX_COMPAT parade_usbc_mux_ps8xxx
+
+/**
+ * Add I2C configuration and USB_MUX_FLAG_NOT_TCPC to enforce it when
+ * mux_read()/mux_write() functions are used.
+ */
+/* clang-format off */
+#define USB_MUX_CONFIG_TCPCI_TCPM_WITH_I2C(mux_id)                             \
+	{                                                                      \
+		USB_MUX_COMMON_FIELDS_WITH_FLAGS(                              \
+			mux_id, USB_MUX_FLAG_NOT_TCPC, USB_MUX_FLAG_NOT_TCPC), \
+		.driver = &tcpci_tcpm_usb_mux_driver,                          \
+		.hpd_update = USB_MUX_CALLBACK_OR_NULL(mux_id, hpd_update),    \
+		.i2c_port = I2C_PORT_BY_DEV(mux_id),                           \
+		.i2c_addr_flags = DT_REG_ADDR(mux_id),                         \
+	}
+/* clang-format on */
+
+/** Use I2C configuration from TCPC */
+/* clang-format off */
+#define USB_MUX_CONFIG_TCPCI_TCPM_WO_I2C(mux_id)                               \
+	{                                                                      \
+		USB_MUX_COMMON_FIELDS(mux_id),                                 \
+		.driver = &tcpci_tcpm_usb_mux_driver,                          \
+		.hpd_update = USB_MUX_CALLBACK_OR_NULL(mux_id, hpd_update),    \
+	}
+/* clang-format on */
+
+#define USB_MUX_CONFIG_TCPCI_TCPM(mux_id)                         \
+	COND_CODE_1(DT_NODE_HAS_PROP(mux_id, reg),                \
+		    (USB_MUX_CONFIG_TCPCI_TCPM_WITH_I2C(mux_id)), \
+		    (USB_MUX_CONFIG_TCPCI_TCPM_WO_I2C(mux_id)))
+
+#endif /* __ZEPHYR_SHIM_TCPCI_USB_MUX_H */
diff --git a/zephyr/shim/include/usbc/tusb1064_usb_mux.h b/zephyr/shim/include/usbc/tusb1064_usb_mux.h
new file mode 100644
index 0000000000..e14b500000
--- /dev/null
+++ b/zephyr/shim/include/usbc/tusb1064_usb_mux.h
@@ -0,0 +1,43 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __ZEPHYR_SHIM_TUSB1064_USB_MUX_H
+#define __ZEPHYR_SHIM_TUSB1064_USB_MUX_H
+
+#include "driver/usb_mux/tusb1064.h"
+
+#define TUSB1064_USB_MUX_COMPAT ti_tusb1064
+#define TUSB1064_EMUL_COMPAT zephyr_tusb1064_emul
+
+#if defined(CONFIG_USB_MUX_TUSB1044)
+/* clang-format off */
+#define USB_MUX_CONFIG_TUSB1064(mux_id)                \
+	{                                              \
+		USB_MUX_COMMON_FIELDS(mux_id),         \
+		.driver = &tusb1064_usb_mux_driver,    \
+		.i2c_port = I2C_PORT_BY_DEV(mux_id),   \
+		.i2c_addr_flags = DT_REG_ADDR(mux_id), \
+		.hpd_update = &tusb1044_hpd_update,    \
+	}
+#elif defined(CONFIG_USB_MUX_TUSB546)
+#define USB_MUX_CONFIG_TUSB1064(mux_id)                \
+	{                                              \
+		USB_MUX_COMMON_FIELDS(mux_id),         \
+		.driver = &tusb1064_usb_mux_driver,    \
+		.i2c_port = I2C_PORT_BY_DEV(mux_id),   \
+		.i2c_addr_flags = DT_REG_ADDR(mux_id), \
+	}
+#else
+#define USB_MUX_CONFIG_TUSB1064(mux_id)                \
+	{                                              \
+		USB_MUX_COMMON_FIELDS(mux_id),         \
+		.driver = &tusb1064_usb_mux_driver,    \
+		.i2c_port = I2C_PORT_BY_DEV(mux_id),   \
+		.i2c_addr_flags = DT_REG_ADDR(mux_id), \
+	}
+/* clang-format on */
+#endif /* defined(CONFIG_USB_MUX_TUSB1044) */
+
+#endif /* __ZEPHYR_SHIM_TUBS1064_USB_MUX_H */
diff --git a/zephyr/shim/include/usbc/usb_muxes.h b/zephyr/shim/include/usbc/usb_muxes.h
new file mode 100644
index 0000000000..7b8ad06088
--- /dev/null
+++ b/zephyr/shim/include/usbc/usb_muxes.h
@@ -0,0 +1,487 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef ZEPHYR_CHROME_USBC_USB_MUXES_H
+#define ZEPHYR_CHROME_USBC_USB_MUXES_H
+
+#include "usb_mux.h"
+#include "usbc/amd_fp6_usb_mux.h"
+#include "usbc/anx7447_usb_mux.h"
+#include "usbc/anx7452_usb_mux.h"
+#include "usbc/anx7483_usb_mux.h"
+#include "usbc/bb_retimer_usb_mux.h"
+#include "usbc/it5205_usb_mux.h"
+#include "usbc/kb8010_usb_mux.h"
+#include "usbc/ps8743_usb_mux.h"
+#include "usbc/ps8818_usb_mux.h"
+#include "usbc/tcpci_usb_mux.h"
+#include "usbc/tusb1064_usb_mux.h"
+#include "usbc/utils.h"
+#include "usbc/virtual_usb_mux.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/sys/util_macro.h>
+
+/**
+ * @brief List of USB mux drivers compatibles and their configurations. Each
+ *        element of list has to have (compatible, config) format.
+ */
+/* clang-format off */
+#define USB_MUX_DRIVERS                                         \
+	(AMD_FP6_USB_MUX_COMPAT, USB_MUX_CONFIG_AMD_FP6),       \
+	(ANX7447_USB_MUX_COMPAT, USB_MUX_CONFIG_ANX7447),       \
+	(ANX7452_USB_MUX_COMPAT, USB_MUX_CONFIG_ANX7452),       \
+	(ANX7483_USB_MUX_COMPAT, USB_MUX_CONFIG_ANX7483),       \
+	(BB_RETIMER_USB_MUX_COMPAT, USB_MUX_CONFIG_BB_RETIMER), \
+	(IT5205_USB_MUX_COMPAT, USB_MUX_CONFIG_IT5205),         \
+	(KB8010_USB_MUX_COMPAT, USB_MUX_CONFIG_KB8010),         \
+	(PS8743_USB_MUX_COMPAT, USB_MUX_CONFIG_PS8743),         \
+	(PS8743_EMUL_COMPAT, USB_MUX_CONFIG_PS8743),         \
+	(PS8818_USB_MUX_COMPAT, USB_MUX_CONFIG_PS8818),         \
+	(PS8XXX_USB_MUX_COMPAT, USB_MUX_CONFIG_TCPCI_TCPM),     \
+	(TCPCI_TCPM_USB_MUX_COMPAT, USB_MUX_CONFIG_TCPCI_TCPM), \
+	(TUSB1064_USB_MUX_COMPAT, USB_MUX_CONFIG_TUSB1064),     \
+	(TUSB1064_EMUL_COMPAT, USB_MUX_CONFIG_TUSB1064),        \
+	(VIRTUAL_USB_MUX_COMPAT, USB_MUX_CONFIG_VIRTUAL)
+/* clang-format on */
+
+/**
+ * @brief Name of USB mux chain structure for given port and place in chain.
+ *        Note, that root of chain is not referred by this name, but
+ *        usb_muxes[@p port_id].
+ *
+ * @param idx Place in chain
+ * @param port_id USBC port id
+ */
+#define USB_MUX_CHAIN_STRUCT_NAME(idx, port_id) \
+	DT_CAT4(USB_MUX_chain_port_, port_id, _mux_, idx)
+
+/**
+ * @brief Declaration of USB mux chain structure for @p idx mux in @p port_id
+ *        USB-C port's chain
+ *
+ * @param port_id USBC port ID (number)
+ * @param idx Place in chain
+ */
+#define USB_MUX_CHAIN_STRUCT_DECLARE(port_id, idx) \
+	MAYBE_CONST struct usb_mux_chain USB_MUX_CHAIN_STRUCT_NAME(idx, port_id)
+
+/**
+ * @brief Name of USB mux structure if node @p mux_id is not EMPTY.
+ *
+ * @param mux_id USB mux node ID
+ */
+#define USB_MUX_STRUCT_NAME(mux_id) \
+	COND_CODE_0(IS_EMPTY(mux_id), (DT_CAT(USB_MUX_NODE_, mux_id)), (EMPTY))
+
+/**
+ * @brief USB muxes in chain should be constant only if configuration
+ *        cannot change in runtime
+ */
+#define MAYBE_CONST \
+	COND_CODE_1(CONFIG_PLATFORM_EC_USB_MUX_RUNTIME_CONFIG, (), (const))
+
+/**
+ * @brief Declaration of USB mux structure
+ *
+ * @param mux_id USB mux node ID
+ */
+#define USB_MUX_STRUCT_DECLARE(mux_id) \
+	MAYBE_CONST struct usb_mux USB_MUX_STRUCT_NAME(mux_id)
+
+/**
+ * @brief Declaration of USB mux board_init function
+ *
+ * @param mux_id USB mux node ID
+ */
+#define USB_MUX_CB_BOARD_INIT_DECLARE(mux_id) \
+	int DT_STRING_TOKEN(mux_id, board_init)(const struct usb_mux *);
+
+/**
+ * @brief Declaration of USB mux board_set function
+ *
+ * @param mux_id USB mux node ID
+ */
+#define USB_MUX_CB_BOARD_SET_DECLARE(mux_id)                           \
+	int DT_STRING_TOKEN(mux_id, board_set)(const struct usb_mux *, \
+					       mux_state_t);
+
+/**
+ * @brief Get pointer by referencing @p name or NULL if @p name is EMPTY
+ *
+ * @param name Identifier to reference
+ */
+#define USB_MUX_POINTER_OR_NULL(name) \
+	COND_CODE_0(IS_EMPTY(name), (&name), (NULL))
+
+/**
+ * @brief Get node id of @p idx USB mux in chain
+ *
+ * @param chain_id USB mux chain node ID
+ * @param idx Position of USB mux in chain
+ */
+#define USB_MUX_GET_CHAIN_N(chain_id, idx) \
+	DT_PHANDLE_BY_IDX(chain_id, usb_muxes, idx)
+
+/**
+ * @brief Get next USB mux chain structure name or EMPTY if it is last mux
+ *
+ * @param chain_id USB mux chain node ID
+ * @param idx Position of USB mux in chain
+ */
+#define USB_MUX_CHAIN_NEXT_NAME(chain_id, idx)                              \
+	GET_ARG_N(2,                                                        \
+		  GET_ARGS_LESS_N(idx,                                      \
+				  LISTIFY(DT_PROP_LEN(chain_id, usb_muxes), \
+					  USB_MUX_CHAIN_STRUCT_NAME, (, ),  \
+					  USBC_PORT(chain_id))),            \
+		  EMPTY)
+
+/**
+ * @brief Get pointer to next USB mux in chain or NULL if it is last mux
+ *
+ * @param chain_id USB mux chain node ID
+ * @param idx Position of USB mux in chain
+ */
+#define USB_MUX_CHAIN_NEXT_POINTER(chain_id, idx) \
+	USB_MUX_POINTER_OR_NULL(USB_MUX_CHAIN_NEXT_NAME(chain_id, idx))
+
+/**
+ * @brief Get pointer to USB mux that is @p idx in chain @p chain_id
+ *
+ * @param chain_id USB mux chain node ID
+ * @param idx Position of USB mux in chain
+ */
+#define USB_MUX_POINTER(chain_id, idx) \
+	&USB_MUX_STRUCT_NAME(USB_MUX_GET_CHAIN_N(chain_id, idx))
+
+/**
+ * @brief Generate pointer to function from @p cb_name property or NULL
+ *        if property doesn't exist
+ *
+ * @param mux_id USB mux node ID
+ * @param cb_name Name of property with callback function
+ */
+#define USB_MUX_CALLBACK_OR_NULL(mux_id, cb_name) \
+	USB_MUX_POINTER_OR_NULL(DT_STRING_TOKEN_OR(mux_id, cb_name, EMPTY))
+
+/**
+ * @brief Set struct usb_mux fields common for all USB muxes and alter flags
+ *
+ * @param mux_id USB mux node ID
+ * @param flags_mask Mask for bits that should be ignored in flags property
+ * @param flags_val Value that should be used instead for masked bits
+ */
+#define USB_MUX_COMMON_FIELDS_WITH_FLAGS(mux_id, flags_mask, flags_val) \
+	.usb_port = USB_MUX_PORT(mux_id),                               \
+	.board_init = USB_MUX_CALLBACK_OR_NULL(mux_id, board_init),     \
+	.board_set = USB_MUX_CALLBACK_OR_NULL(mux_id, board_set),       \
+	.flags = (DT_PROP_OR(mux_id, flags, 0) & ~(flags_mask)) | (flags_val)
+
+/**
+ * @brief Set struct usb_mux fields common for all USB muxes
+ *
+ * @param mux_id USB mux node ID
+ */
+#define USB_MUX_COMMON_FIELDS(mux_id) \
+	USB_MUX_COMMON_FIELDS_WITH_FLAGS(mux_id, 0, 0)
+
+/**
+ * @brief Declare USB mux structure
+ *
+ * @param mux_id USB mux node ID
+ * @param conf Driver configuration function
+ */
+#define USB_MUX_DECLARE(mux_id, conf) extern USB_MUX_STRUCT_DECLARE(mux_id);
+
+/**
+ * @brief Define USB mux structure using driver USB_MUX_CONFIG_* macro
+ *
+ * @param mux_id USB mux node ID
+ * @param conf Driver configuration function
+ */
+#define USB_MUX_DEFINE(mux_id, conf) \
+	USB_MUX_STRUCT_DECLARE(mux_id) = conf(mux_id);
+
+/**
+ * @brief Call @p cb_op if @p mux_id has @p cb_prop property
+ *
+ * @param mux_id USB mux node ID
+ * @param cb_prop The callback property name
+ * @param cb_op Operation to perform on USB muxes
+ */
+#define USB_MUX_CB_DECLARE_IF_EXIST(mux_id, cb_prop, cb_op) \
+	COND_CODE_1(DT_NODE_HAS_PROP(mux_id, cb_prop), (cb_op(mux_id)), ())
+
+/**
+ * @brief Declare USB mux board_set function @p mux_id has board_set property
+ *
+ * @param mux_id USB mux node ID
+ * @param conf Driver configuration function
+ */
+#define USB_MUX_CB_BOARD_SET_DECLARE_IF_EXISTS(mux_id, conf) \
+	USB_MUX_CB_DECLARE_IF_EXIST(mux_id, board_set,       \
+				    USB_MUX_CB_BOARD_SET_DECLARE)
+
+/**
+ * @brief Declare USB mux board_init function @p mux_id has board_init property
+ *
+ * @param mux_id USB mux node ID
+ * @param conf Driver configuration function
+ */
+#define USB_MUX_CB_BOARD_INIT_DECLARE_IF_EXISTS(mux_id, conf) \
+	USB_MUX_CB_DECLARE_IF_EXIST(mux_id, board_init,       \
+				    USB_MUX_CB_BOARD_INIT_DECLARE)
+
+/**
+ * @brief Call @p op operation for each USB mux node that is compatible with
+ *        any driver from the USB_MUX_DRIVERS list.
+ *        DT_FOREACH_STATUS_OKAY_VARGS() macro can not be used in @p op
+ *
+ * @param op Operation to perform on each USB mux. Should accept mux node ID and
+ *           driver config as arguments.
+ */
+#define USB_MUX_FOREACH_MUX_DT_VARGS(op) \
+	DT_FOREACH_USBC_DRIVER_STATUS_OK_VARGS(op, USB_MUX_DRIVERS)
+
+/**
+ * @brief Convert @p mux_id and @p conf pair into USB_MUX_LIST entry
+ *
+ * @param mux_id USB mux node ID
+ * @param conf Driver configuration function
+ */
+#define USB_MUX_TO_LIST(mux_id, conf) , (mux_id, conf)
+
+/**
+ * @brief List of all USB muxes with config matched by compatible. List is in
+ *        format (mux1_id, conf1) , (mux2_id, conf2) ...
+ */
+#define USB_MUX_LIST \
+	LIST_DROP_EMPTY(USB_MUX_FOREACH_MUX_DT_VARGS(USB_MUX_TO_LIST))
+
+/**
+ * @brief Call @p op with @p args arguments
+ *
+ * @param op Operation to perform on USB mux. Should accept mux node ID and
+ *           driver config as arguments.
+ * @param args Arguments for @p op. Should be in format (mux_id, conf).
+ */
+#define USB_MUX_CALL_OP(args, op) op args
+
+/**
+ * @brief Call @p op operation for each USB mux node from USB_MUX_LIST. This is
+ *        like USB_MUX_FOREACH_MUX_DT_VARGS(), except
+ *        DT_FOREACH_STATUS_OKAY_VARGS() macro can be used in @p op
+ *
+ * @param op Operation to perform on each USB mux. Should accept mux node ID and
+ *           driver config as arguments.
+ */
+#define USB_MUX_FOREACH_MUX(op)                                              \
+	COND_CODE_0(                                                         \
+		IS_EMPTY(USB_MUX_LIST),                                      \
+		(FOR_EACH_FIXED_ARG(USB_MUX_CALL_OP, (), op, USB_MUX_LIST)), \
+		(EMPTY))
+
+/**
+ * @brief Initialise chain structure for @p idx mux
+ *
+ * @param chain_id Chain DTS node ID
+ * @param idx USB mux index
+ */
+#define USB_MUX_CHAIN_STRUCT_INIT(chain_id, idx)                   \
+	{                                                          \
+		.mux = USB_MUX_POINTER(chain_id, idx),             \
+		.next = USB_MUX_CHAIN_NEXT_POINTER(chain_id, idx), \
+	}
+
+/**
+ * @brief Helper macro to set chain structure value for @p idx mux
+ *
+ * @param chain_id Chain DTS node ID
+ * @param idx USB mux index
+ */
+#define USB_MUX_CHAIN_STRUCT_SET(chain_id, idx) \
+	(struct usb_mux_chain) USB_MUX_CHAIN_STRUCT_INIT(chain_id, idx)
+
+/**
+ * @brief Declaration of USB mux chain extern structure for @p idx mux in
+ *        @p chain_id chain
+ *
+ * @param chain_id USB mux chain node ID
+ * @param idx Place in chain
+ */
+#define USB_MUX_CHAIN_STRUCT_DECLARE_EXTERN_OP(chain_id, idx) \
+	extern USB_MUX_CHAIN_STRUCT_DECLARE(USBC_PORT(chain_id), idx);
+
+/**
+ * @brief Declaration of USB mux chain structure for @p idx mux in @p chain_id
+ *        chain
+ *
+ * @param chain_id USB mux chain node ID
+ * @param idx Place in chain
+ */
+#define USB_MUX_CHAIN_STRUCT_DECLARE_OP(chain_id, idx) \
+	USB_MUX_CHAIN_STRUCT_DECLARE(USBC_PORT(chain_id), idx);
+
+/**
+ * @brief Definition of USB mux chain structure for @p idx mux in @p chain_id
+ *        chain
+ *
+ * @param chain_id USB mux chain node ID
+ * @param idx Place in chain
+ */
+#define USB_MUX_CHAIN_STRUCT_DEFINE_OP(chain_id, idx)            \
+	USB_MUX_CHAIN_STRUCT_DECLARE(USBC_PORT(chain_id), idx) = \
+		USB_MUX_CHAIN_STRUCT_INIT(chain_id, idx);
+
+/**
+ * @brief Call @p op if @p idx is not 0 (is not the root mux of chain)
+ *
+ * @param chain_id Chain DTS node ID
+ * @param unused2 This argument is expected by DT_FOREACH_PROP_ELEM_VARGS
+ * @param idx Position of USB mux in chain
+ * @param op Operation to perform on USB muxes
+ */
+#define USB_MUX_SKIP_ROOT(chain_id, unused2, idx, op) \
+	COND_CODE_1(UTIL_BOOL(idx), (op(chain_id, idx)), ())
+
+/**
+ * @brief Call @p op for each mux in @p chain_id chain except the root mux
+ *
+ * @param chain_id Chain DTS node ID
+ * @param op Operation to perform on USB muxes
+ */
+#define USB_MUX_FOREACH_NO_ROOT_MUX(chain_id, op) \
+	DT_FOREACH_PROP_ELEM_VARGS(chain_id, usb_muxes, USB_MUX_SKIP_ROOT, op)
+
+/**
+ * @brief Create usb_muxes array entry for @p chain_id chain
+ *
+ * @param chain_id Chain DTS node ID
+ */
+#define USB_MUX_DEFINE_ROOT_MUX(chain_id) \
+	[USBC_PORT(chain_id)] = USB_MUX_CHAIN_STRUCT_INIT(chain_id, 0),
+
+/**
+ * @brief Call @p op only if chain @p chain_id is not alternative
+ *
+ * @param chain_id Chain DTS node ID
+ * @param op Operation to perform on main USB mux chain
+ * @param ... Arguments to pass to the @p op operation
+ */
+#define USB_MUX_FOR_MAIN_CHAIN(chain_id, op, ...)         \
+	COND_CODE_0(DT_PROP(chain_id, alternative_chain), \
+		    (op(chain_id, ##__VA_ARGS__)), ())
+
+/**
+ * @brief Call @p op for each USB mux chain
+ *
+ * @param op Operation to perform on USB mux chain
+ */
+#define USB_MUX_FOREACH_CHAIN(op) \
+	DT_FOREACH_STATUS_OKAY(cros_ec_usb_mux_chain, op)
+
+/**
+ * @brief Call @p op for each USB mux chain with arguments
+ *
+ * @param op Operation to perform on USB mux chain
+ * @param ... Arguments to pass to the @p op operation
+ */
+#define USB_MUX_FOREACH_CHAIN_VARGS(op, ...) \
+	DT_FOREACH_STATUS_OKAY_VARGS(cros_ec_usb_mux_chain, op, __VA_ARGS__)
+
+/**
+ * @brief Construct first half of conditional expression (?:) that evaluates to
+ *        @p chain_id USB port if @p idx mux in @p chain_id is the same as
+ *        @p mux_id
+ *
+ * @param chain_id USB mux chain node ID
+ * @param unused2 This argument is expected by DT_FOREACH_PROP_ELEM_VARGS
+ * @param idx Position of USB mux in chain
+ * @param mux_id USB mux node ID to compare with @p idx mux
+ */
+#define USB_MUX_PORT_IF_SAME_NODES(chain_id, unused2, idx, mux_id) \
+	DT_SAME_NODE(mux_id, USB_MUX_GET_CHAIN_N(chain_id, idx)) ? \
+		USBC_PORT(chain_id):
+
+/**
+ * @brief Compare @p mux_id with all muxes in @p chain_id
+ *
+ * @param chain_id USB mux chain node ID
+ * @param mux_id USB mux node ID
+ */
+#define USB_MUX_FIND_PORT(chain_id, mux_id)             \
+	DT_FOREACH_PROP_ELEM_VARGS(chain_id, usb_muxes, \
+				   USB_MUX_PORT_IF_SAME_NODES, mux_id)
+
+/**
+ * @brief Get port for @p mux_id by looking for an usb mux chain where @p mux_id
+ *        is present. If the mux is not present in any chain, this macro
+ *        evaluate to -1.
+ *
+ * This expands to:
+ *     (DT_DEP_ORD(mux_id) == DT_DEP_ORD(USB_MUX_GET_CHAIN_N(chain1_id, 0))) ?
+ *         USBC_PORT(chain1_id) :
+ *     (DT_DEP_ORD(mux_id) == DT_DEP_ORD(USB_MUX_GET_CHAIN_N(chain1_id, 1))) ?
+ *         USBC_PORT(chain1_id) :
+ *         ...
+ *     (DT_DEP_ORD(mux_id) == DT_DEP_ORD(USB_MUX_GET_CHAIN_N(chain1_id, n))) ?
+ *         USBC_PORT(chain1_id) :
+ *     (DT_DEP_ORD(mux_id) == DT_DEP_ORD(USB_MUX_GET_CHAIN_N(chain2_id, 0))) ?
+ *         USBC_PORT(chain2_id) :
+ *         ...
+ *     (DT_DEP_ORD(mux_id) == DT_DEP_ORD(USB_MUX_GET_CHAIN_N(chainm_id, k))) ?
+ *         USBC_PORT(chainm_id) : (-1)
+ *
+ * @param mux_id USB mux node ID
+ */
+#define USB_MUX_PORT(mux_id) \
+	(USB_MUX_FOREACH_CHAIN_VARGS(USB_MUX_FIND_PORT, mux_id)(-1))
+
+/**
+ * @brief Set usb_mux_chain structure for mux @p idx in chain @p chain_id
+ *
+ * @param chain_id Alternative USB mux chain node ID
+ * @param idx Position of the mux in chain
+ */
+#define USB_MUX_SET_ALTERNATIVE(chain_id, idx)                \
+	USB_MUX_CHAIN_STRUCT_NAME(idx, USBC_PORT(chain_id)) = \
+		USB_MUX_CHAIN_STRUCT_SET(chain_id, idx);
+
+/**
+ * @brief Enable alternative USB mux chain
+ *
+ * @param chain_id Alternative USB mux chain node ID
+ */
+#define USB_MUX_ENABLE_ALTERNATIVE_NODE(chain_id)                              \
+	do {                                                                   \
+		usb_muxes[USBC_PORT(chain_id)] =                               \
+			USB_MUX_CHAIN_STRUCT_SET(chain_id, 0);                 \
+		USB_MUX_FOREACH_NO_ROOT_MUX(chain_id, USB_MUX_SET_ALTERNATIVE) \
+	} while (0)
+
+/**
+ * @brief Enable alternative USB mux chain
+ *
+ * @param nodelabel Label of alternative USB mux chain
+ */
+#define USB_MUX_ENABLE_ALTERNATIVE(nodelabel) \
+	USB_MUX_ENABLE_ALTERNATIVE_NODE(DT_NODELABEL(nodelabel))
+
+/**
+ * Forward declare all usb_mux structures e.g.
+ * MAYBE_CONST struct usb_mux USB_MUX_NODE_<node_id>;
+ */
+USB_MUX_FOREACH_MUX(USB_MUX_DECLARE)
+
+/**
+ * Forward declare all usb_mux_chain structures e.g.
+ * extern MAYBE_CONST struct usb_mux_chain
+ * USB_MUX_chain_port_<node_id>_mux_<position_id>;
+ */
+USB_MUX_FOREACH_CHAIN_VARGS(USB_MUX_FOREACH_NO_ROOT_MUX,
+			    USB_MUX_CHAIN_STRUCT_DECLARE_EXTERN_OP)
+
+#endif /* ZEPHYR_CHROME_USBC_USB_MUXES_H */
diff --git a/zephyr/shim/include/usbc/utils.h b/zephyr/shim/include/usbc/utils.h
new file mode 100644
index 0000000000..40011257e2
--- /dev/null
+++ b/zephyr/shim/include/usbc/utils.h
@@ -0,0 +1,100 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_ZEPHYR_SHIM_USBC_UTIL
+
+/*
+ * Enable interrupt from the `irq` property of an instance's node.
+ *
+ * @param inst: instance number
+ */
+#define BC12_GPIO_ENABLE_INTERRUPT(inst)             \
+	IF_ENABLED(DT_INST_NODE_HAS_PROP(inst, irq), \
+		   (gpio_enable_dt_interrupt(        \
+			    GPIO_INT_FROM_NODE(DT_INST_PHANDLE(inst, irq)));))
+
+/*
+ * Get the port number from a child of `named-usbc-port` node.
+ *
+ * @param id: node id
+ */
+#define USBC_PORT(id) DT_REG_ADDR(DT_PARENT(id))
+
+/*
+ * Get the port number from a `named-usbc-port` node.
+ *
+ * @param id: `named-usbc-port` node id
+ */
+#define USBC_PORT_NEW(id) DT_REG_ADDR(id)
+
+/*
+ * Get the port number from a child of `named-usbc-port` node.
+ *
+ * @param inst: instance number of the node
+ */
+#define USBC_PORT_FROM_INST(inst) USBC_PORT(DT_DRV_INST(inst))
+
+/*
+ * Check that the TCPC interrupt flag defined in the devicetree is the same as
+ * the hardware.
+ *
+ * @param id: node id of the tcpc port
+ */
+#define TCPC_VERIFY_NO_FLAGS_ACTIVE_ALERT_HIGH(id)                             \
+	BUILD_ASSERT(                                                          \
+		(DT_PROP(id, tcpc_flags) & TCPC_FLAGS_ALERT_ACTIVE_HIGH) == 0, \
+		"TCPC interrupt configuration error for " DT_NODE_FULL_NAME(   \
+			id));
+
+/**
+ * @brief Macros used to process USB-C driver organized as a
+ * (compatible, config) tuple.  Where "compatible" is the devictree compatible
+ * string and "config" is the macro used to initialize the USB-C driver
+ * instance.
+ *
+ * The "config" macro has a single parameter, the devicetree node ID of the
+ * USB-C device driver (not the ID of the named-usbc-port node).
+ */
+#define USBC_DRIVER_GET_COMPAT(driver) GET_ARG_N(1, __DEBRACKET driver)
+#define USBC_DRIVER_GET_COMPAT_COMMA(driver) USBC_DRIVER_GET_COMPAT(driver),
+#define USBC_DRIVER_GET_CONFIG(driver) GET_ARG_N(2, __DEBRACKET driver)
+#define USBC_DRIVER_GET_CONFIG(driver) GET_ARG_N(2, __DEBRACKET driver)
+
+/**
+ * @brief Call @p op operation for each node that is compatible with @p driver
+ *
+ * @param driver USB driver description in format (compatible, config)
+ * @param op Operation to perform on each USB device. Should accept mux node ID
+ *           and driver config as arguments.
+ */
+#define USBC_DRIVER_CONFIG(driver, op)                                   \
+	DT_FOREACH_STATUS_OKAY_VARGS(USBC_DRIVER_GET_COMPAT(driver), op, \
+				     USBC_DRIVER_GET_CONFIG(driver))
+
+/**
+ * @brief Call @p op operation for each USB driver node that found in the
+ *        devicetree that matches a compatible from the caller supplied
+ *        driver list.
+ *
+ * @param op Operation to perform on each USB driver. Should accept node ID and
+ *           driver config as arguments.
+ * @param driver_list USB driver list, each driver in format
+ *                    (compatible, config), separated by commas.
+ */
+#define DT_FOREACH_USBC_DRIVER_STATUS_OK_VARGS(op, driver_list) \
+	FOR_EACH_FIXED_ARG(USBC_DRIVER_CONFIG, (), op, driver_list)
+
+/**
+ * @brief When processing the named-usbc-port, the node ID of the USB-C port
+ * and the node ID of a property (ppc, tcpc, etc), are passed as a tuple
+ * as the fixed argument to FOR_EACH_FIXED_ARG.
+ *
+ * The macros below extract the USB-C node ID and the property node ID
+ * from this tuple.
+ */
+#define NODES_GET_USBC_ID(nodes) GET_ARG_N(1, __DEBRACKET nodes)
+#define NODES_GET_PROP_ID(nodes) GET_ARG_N(2, __DEBRACKET nodes)
+
+#endif /* __CROS_EC_ZEPHYR_SHIM_USBC_UTIL */
diff --git a/zephyr/shim/include/usbc/virtual_usb_mux.h b/zephyr/shim/include/usbc/virtual_usb_mux.h
new file mode 100644
index 0000000000..bbb2d8730e
--- /dev/null
+++ b/zephyr/shim/include/usbc/virtual_usb_mux.h
@@ -0,0 +1,20 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __ZEPHYR_SHIM_VIRTUAL_USB_MUX_H
+#define __ZEPHYR_SHIM_VIRTUAL_USB_MUX_H
+
+#include "usb_mux.h"
+
+#define VIRTUAL_USB_MUX_COMPAT cros_ec_usbc_mux_virtual
+
+#define USB_MUX_CONFIG_VIRTUAL(mux_id)                     \
+	{                                                  \
+		USB_MUX_COMMON_FIELDS(mux_id),             \
+			.driver = &virtual_usb_mux_driver, \
+			.hpd_update = &virtual_hpd_update, \
+	}
+
+#endif /* __ZEPHYR_SHIM_VIRTUAL_USB_MUX_H */
diff --git a/zephyr/shim/include/zephyr_adc.h b/zephyr/shim/include/zephyr_adc.h
new file mode 100644
index 0000000000..d4139692f7
--- /dev/null
+++ b/zephyr/shim/include/zephyr_adc.h
@@ -0,0 +1,42 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_ZEPHYR_ADC_H
+#define __CROS_EC_ZEPHYR_ADC_H
+
+#include <zephyr/drivers/adc.h>
+
+#ifdef CONFIG_ADC
+
+#define ZSHIM_ADC_ID(node_id) DT_STRING_UPPER_TOKEN(node_id, enum_name)
+
+enum adc_channel {
+#if DT_NODE_EXISTS(DT_INST(0, named_adc_channels))
+	DT_FOREACH_CHILD_SEP(DT_INST(0, named_adc_channels), ZSHIM_ADC_ID,
+			     (, )),
+#endif /* named_adc_channels */
+	ADC_CH_COUNT
+};
+
+struct adc_t {
+	const char *name;
+	const struct device *dev;
+	uint8_t input_ch;
+	int factor_mul;
+	int factor_div;
+	struct adc_channel_cfg channel_cfg;
+};
+
+#ifndef CONFIG_ADC_CHANNELS_RUNTIME_CONFIG
+extern const struct adc_t adc_channels[];
+#else
+extern struct adc_t adc_channels[];
+#endif /* CONFIG_ADC_CHANNELS_RUNTIME_CONFIG */
+#else
+/* Empty declaration to avoid warnings if adc.h is included */
+enum adc_channel { ADC_CH_COUNT };
+#endif /* CONFIG_ADC */
+
+#endif /* __CROS_EC_ZEPHYR_ADC_H */
diff --git a/zephyr/shim/include/zephyr_console_shim.h b/zephyr/shim/include/zephyr_console_shim.h
index 5f242b6830..6db39db204 100644
--- a/zephyr/shim/include/zephyr_console_shim.h
+++ b/zephyr/shim/include/zephyr_console_shim.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,41 +6,56 @@
 #ifndef __CROS_EC_ZEPHYR_CONSOLE_SHIM_H
 #define __CROS_EC_ZEPHYR_CONSOLE_SHIM_H
 
-#include <shell/shell.h>
+#include <zephyr/shell/shell.h>
+
+struct zephyr_console_command {
+	/* Handler for the command.  argv[0] will be the command name. */
+	int (*handler)(int argc, const char **argv);
+#ifdef CONFIG_SHELL_HELP
+	/* Description of args */
+	const char *argdesc;
+	/* Short help for command */
+	const char *help;
+#endif
+};
+
+#ifdef CONFIG_SHELL_HELP
+#define _HELP_ARGS(A, H) .argdesc = A, .help = H,
+#else
+#define _HELP_ARGS(A, H)
+#endif
 
 /**
  * zshim_run_ec_console_command() - Dispatch a CrOS EC console command
  * using Zephyr's shell
  *
- * @handler:		A CrOS EC shell command handler.
- * @shell:		The Zephyr shell to run on.
+ * @command:		Pointer to a struct zephyr_console_command
  * @argc:		The number of command line arguments.
  * @argv:		The NULL-terminated list of arguments.
- * @help_str:		The help string to display when "-h" is passed.
- * @argdesc:		The string describing the arguments to the command.
  *
  * Return: the return value from the handler.
  */
-int zshim_run_ec_console_command(int (*handler)(int argc, char **argv),
-				 const struct shell *shell, size_t argc,
-				 char **argv, const char *help_str,
-				 const char *argdesc);
+int zshim_run_ec_console_command(const struct zephyr_console_command *command,
+				 size_t argc, const char **argv);
 
 /* Internal wrappers for DECLARE_CONSOLE_COMMAND_* macros. */
-#define _ZEPHYR_SHELL_COMMAND_SHIM_2(NAME, ROUTINE_ID, ARGDESC, HELP,	\
-				     WRAPPER_ID)			\
-	static int WRAPPER_ID(const struct shell *shell, size_t argc,        \
-			      char **argv)                                   \
-	{                                                                    \
-		return zshim_run_ec_console_command(ROUTINE_ID, shell, argc, \
-						    argv, HELP, ARGDESC);    \
-	}                                                                    \
-	SHELL_CMD_ARG_REGISTER(NAME, NULL, HELP, WRAPPER_ID, 0,              \
+#define _ZEPHYR_SHELL_COMMAND_SHIM_2(NAME, ROUTINE_ID, ARGDESC, HELP,       \
+				     WRAPPER_ID, ENTRY_ID)                  \
+	static const struct zephyr_console_command ENTRY_ID = {             \
+		.handler = ROUTINE_ID, _HELP_ARGS(ARGDESC, HELP)            \
+	};                                                                  \
+	static int WRAPPER_ID(const struct shell *shell, size_t argc,       \
+			      const char **argv)                            \
+	{                                                                   \
+		return zshim_run_ec_console_command(&ENTRY_ID, argc, argv); \
+	}                                                                   \
+	SHELL_CMD_ARG_REGISTER(NAME, NULL, HELP, WRAPPER_ID, 0,             \
 			       SHELL_OPT_ARG_MAX)
 
-#define _ZEPHYR_SHELL_COMMAND_SHIM(NAME, ROUTINE_ID, ARGDESC, HELP)   \
-	_ZEPHYR_SHELL_COMMAND_SHIM_2(NAME, ROUTINE_ID, ARGDESC, HELP, \
-				     UTIL_CAT(zshim_wrapper_, ROUTINE_ID))
+#define _ZEPHYR_SHELL_COMMAND_SHIM(NAME, ROUTINE_ID, ARGDESC, HELP)        \
+	_ZEPHYR_SHELL_COMMAND_SHIM_2(NAME, ROUTINE_ID, ARGDESC, HELP,      \
+				     UTIL_CAT(zshim_wrapper_, ROUTINE_ID), \
+				     UTIL_CAT(zshim_entry_, ROUTINE_ID))
 
 /* These macros mirror the macros provided by the CrOS EC. */
 #define DECLARE_CONSOLE_COMMAND(NAME, ROUTINE, ARGDESC, HELP) \
@@ -55,4 +70,22 @@ int zshim_run_ec_console_command(int (*handler)(int argc, char **argv),
 #define DECLARE_SAFE_CONSOLE_COMMAND(NAME, ROUTINE, ARGDESC, HELP) \
 	_ZEPHYR_SHELL_COMMAND_SHIM(NAME, ROUTINE, ARGDESC, HELP)
 
-#endif  /* __CROS_EC_ZEPHYR_CONSOLE_SHIM_H */
+/**
+ * console_buf_notify_chars() - Notify the console host command buffer
+ * of bytes on the console.
+ *
+ * @s:			The pointer to the string.
+ * @len:		The size of the string.
+ *
+ * Return: the number of bytes consumed.
+ */
+size_t console_buf_notify_chars(const char *s, size_t len);
+
+/**
+ * get_shell_thread() - Get the thread id for the shell backend
+ *
+ * @returns Backend shell thread id or NULL if not enabled
+ */
+k_tid_t get_shell_thread(void);
+
+#endif /* __CROS_EC_ZEPHYR_CONSOLE_SHIM_H */
diff --git a/zephyr/shim/include/zephyr_espi_shim.h b/zephyr/shim/include/zephyr_espi_shim.h
new file mode 100644
index 0000000000..ddc4da075c
--- /dev/null
+++ b/zephyr/shim/include/zephyr_espi_shim.h
@@ -0,0 +1,60 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_ZEPHYR_ESPI_SHIM_H
+#define __CROS_EC_ZEPHYR_ESPI_SHIM_H
+
+#include <stdbool.h>
+#include <stdint.h>
+
+/**
+ * Check if the message is an ACPI command.
+ *
+ * @param data The full ACPI event data.
+ * @return True if the message is a command.
+ */
+bool is_acpi_command(uint32_t data);
+
+/**
+ * Get the value component of the ACPI message.
+ *
+ * @param data The full ACPI event data.
+ * @return The value component of the ACPI message.
+ */
+uint32_t get_acpi_value(uint32_t data);
+
+/**
+ * Check if the 8042 event data contains an input-buffer-full (IBF) event.
+ *
+ * @param data The full 8042 event data.
+ * @return True if the data contains an IBF event.
+ */
+bool is_8042_ibf(uint32_t data);
+
+/**
+ * Check if the 8042 event data contains an output-buffer-empty (OBE) event.
+ *
+ * @param data The full 8042 event data.
+ * @return True if the data contains an OBE event.
+ */
+bool is_8042_obe(uint32_t data);
+
+/**
+ * Get the type of 8042 message.
+ *
+ * @param data The full 8042 event data.
+ * @return The type component of the message.
+ */
+uint32_t get_8042_type(uint32_t data);
+
+/**
+ * Get the data from an 8042 message.
+ *
+ * @param data The full 8042 event data.
+ * @return The data component of the message.
+ */
+uint32_t get_8042_data(uint32_t data);
+
+#endif /* __CROS_EC_ZEPHYR_ESPI_SHIM_H */
diff --git a/zephyr/shim/include/zephyr_gpio_signal.h b/zephyr/shim/include/zephyr_gpio_signal.h
new file mode 100644
index 0000000000..bf59c07738
--- /dev/null
+++ b/zephyr/shim/include/zephyr_gpio_signal.h
@@ -0,0 +1,186 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#if !defined(__CROS_EC_GPIO_SIGNAL_H) || defined(__CROS_EC_ZEPHYR_GPIO_SIGNAL_H)
+#error "This file must only be included from gpio_signal.h. Include gpio_signal.h directly."
+#endif
+#define __CROS_EC_ZEPHYR_GPIO_SIGNAL_H
+
+#include <zephyr/devicetree.h>
+#include <zephyr/toolchain.h>
+
+BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(named_gpios) == 1,
+	     "only one named-gpios compatible node may be present");
+
+#define NAMED_GPIOS_NODE DT_COMPAT_GET_ANY_STATUS_OKAY(named_gpios)
+
+/*
+ * Returns the node path for a specific named-gpios gpio
+ */
+#define NAMED_GPIOS_GPIO_NODE(name) DT_CHILD(NAMED_GPIOS_NODE, name)
+
+/** @brief Returns the enum-name property as a token
+ *
+ * Returns the enum-name property for this node as an upper case token
+ * suitable for use as a GPIO signal name.
+ * The enum-name property must exist, so this macro should only
+ * be called conditionally upon checking the property exists.
+ */
+#define GPIO_SIGNAL_NAME_FROM_ENUM(id) DT_STRING_UPPER_TOKEN(id, enum_name)
+
+/** @brief Creates a GPIO signal name using the DTS ordinal number
+ *
+ * Create a GPIO signal name for a GPIO that does not contain
+ * the enum-name property. The DTS ordinal number is used
+ * to generate a unique name for this GPIO.
+ */
+#define GPIO_SIGNAL_NAME_FROM_ORD(ord) DT_CAT(GPIO_ORD_, ord)
+
+/** @brief Generate a GPIO signal name for this id
+ *
+ * Depending on whether the enum-name property exists, create
+ * a GPIO signal name from either the enum-name or a
+ * unique name generated using the DTS ordinal.
+ */
+#define GPIO_SIGNAL_NAME(id)                          \
+	COND_CODE_1(DT_NODE_HAS_PROP(id, enum_name),  \
+		    (GPIO_SIGNAL_NAME_FROM_ENUM(id)), \
+		    (GPIO_SIGNAL_NAME_FROM_ORD(id##_ORD)))
+
+#define GPIO_SIGNAL(id) GPIO_SIGNAL_NAME(id)
+
+#define GPIO_IMPL_SIGNAL(id) \
+	COND_CODE_1(DT_NODE_HAS_PROP(id, gpios), (GPIO_SIGNAL(id), ), ())
+
+#define GPIO_UNIMPL_SIGNAL(id)                       \
+	COND_CODE_1(DT_NODE_HAS_PROP(id, gpios), (), \
+		    (GPIO_SIGNAL_NAME(id) = GPIO_UNIMPLEMENTED, ))
+/*
+ * Create a list of aliases to allow remapping of aliased names.
+ */
+#define GPIO_DT_MK_ALIAS(id) \
+	DT_STRING_UPPER_TOKEN(id, alias) = DT_STRING_UPPER_TOKEN(id, enum_name),
+
+#define GPIO_DT_ALIAS_LIST(id) \
+	COND_CODE_1(DT_NODE_HAS_PROP(id, alias), (GPIO_DT_MK_ALIAS(id)), ())
+
+/* clang-format off */
+enum gpio_signal {
+	GPIO_UNIMPLEMENTED = -1,
+#if DT_NODE_EXISTS(NAMED_GPIOS_NODE)
+	DT_FOREACH_CHILD(NAMED_GPIOS_NODE, GPIO_IMPL_SIGNAL)
+#endif
+	GPIO_COUNT,
+#if DT_NODE_EXISTS(NAMED_GPIOS_NODE)
+	DT_FOREACH_CHILD(NAMED_GPIOS_NODE, GPIO_UNIMPL_SIGNAL)
+	DT_FOREACH_CHILD(NAMED_GPIOS_NODE, GPIO_DT_ALIAS_LIST)
+#endif
+	GPIO_LIMIT = 0x0FFF,
+
+	IOEX_SIGNAL_START = GPIO_LIMIT + 1,
+	IOEX_SIGNAL_END = IOEX_SIGNAL_START,
+	IOEX_LIMIT = 0x1FFF,
+};
+/* clang-format on */
+#undef GPIO_DT_ALIAS_LIST
+#undef GPIO_DT_MK_ALIAS
+#undef GPIO_IMPL_SIGNAL
+#undef GPIO_UNIMPL_SIGNAL
+
+BUILD_ASSERT(GPIO_COUNT < GPIO_LIMIT);
+
+/** @brief Converts a node identifier under named gpios to enum
+ *
+ * Converts the specified node identifier name, which should be nested under
+ * the named_gpios node, into the correct enum gpio_signal that can be used
+ * with platform/ec gpio API
+ */
+#define NAMED_GPIO(name) GPIO_SIGNAL(DT_CHILD(NAMED_GPIOS_NODE, name))
+
+/** @brief Obtain a named gpio enum from a label and property
+ *
+ * Obtains a valid enum gpio_signal that can be used with platform/ec gpio API
+ * from the property of a labeled node. The property has to point to a
+ * named_gpios node.
+ */
+#define NAMED_GPIO_NODELABEL(label, prop) \
+	GPIO_SIGNAL(DT_PHANDLE(DT_NODELABEL(label), prop))
+
+/** @brief Converts a signal to a gpio_dt_spec pointer name.
+ *
+ * Prepend "DT_" to the the gpio_signal name to create a name that
+ * can be used as a pointer to gpio_dt_spec.
+ *
+ * For example, given the DTS node under "named-gpios":
+ *
+ * gpio_ec_wp_l: ec_wp_l {
+ *	gpio = <&gpioe 5 GPIO_INPUT>;
+ *	enum-name = "GPIO_WP_L";
+ * };
+ *
+ * aliases {
+ *	other_name = &gpio_ec_wp_l;
+ * };
+ *
+ * The following methods can all be used to access the GPIO:
+ *
+ * inp = gpio_get_level(GPIO_WP_L); // Legacy access
+ * inp = gpio_pin_get_dt(DT_GPIO_LID_OPEN); // Zephyr API
+ * inp = gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_wp_l)); // Zephyr API
+ * inp = gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(other_name));
+ * enum gpio_signal sig = GPIO_WP_L;
+ * inp = gpio_pin_get_dt(gpio_get_dt_spec(sig)); // Zephyr API
+ *
+ * DT_GPIO_LID_OPEN, GPIO_DT_FROM_NODELABEL and GPIO_DT_FROM_ALIAS will
+ * resolve at build time, whereas gpio_get_dt_spec() will resolve at run-time.
+ */
+#define GPIO_DT_NAME(signal) DT_CAT(DT_, signal)
+
+#define GPIO_DT_FROM_NODE(id) GPIO_DT_NAME(GPIO_SIGNAL(id))
+
+#define GPIO_DT_FROM_ALIAS(id) GPIO_DT_FROM_NODE(DT_ALIAS(id))
+
+#define GPIO_DT_FROM_NODELABEL(label) GPIO_DT_FROM_NODE(DT_NODELABEL(label))
+
+#if DT_NODE_EXISTS(NAMED_GPIOS_NODE)
+/*
+ * Declare the pointers that refer to the gpio_dt_spec entries
+ * for each GPIO.
+ */
+struct gpio_dt_spec;
+
+#define GPIO_DT_PTR_DECL(id)                                               \
+	COND_CODE_1(DT_NODE_HAS_PROP(id, gpios),                           \
+		    (extern const struct gpio_dt_spec *const GPIO_DT_NAME( \
+			     GPIO_SIGNAL(id));),                           \
+		    ())
+
+DT_FOREACH_CHILD(NAMED_GPIOS_NODE, GPIO_DT_PTR_DECL)
+
+#undef GPIO_DT_PTR_DECL
+
+#endif /* DT_NODE_EXISTS(NAMED_GPIOS_NODE) */
+
+#define IOEXPANDER_ID_EXPAND(id) ioex_chip_##id
+#define IOEXPANDER_ID(id) IOEXPANDER_ID_EXPAND(id)
+#define IOEXPANDER_ID_FROM_INST_WITH_COMMA(id) IOEXPANDER_ID(id),
+/* clang-format off */
+enum ioexpander_id {
+	DT_FOREACH_STATUS_OKAY(cros_ioex_chip,
+			       IOEXPANDER_ID_FROM_INST_WITH_COMMA)
+	CONFIG_IO_EXPANDER_PORT_COUNT
+};
+/* clang-format on */
+
+/**
+ * Obtain the gpio_dt_spec structure associated with
+ * this gpio signal.
+ *
+ * @param signal	GPIO signal to get gpio_dt_spec for
+ * @returns		gpio_dt_spec associated with signal, or 0 if invalid
+ */
+const struct gpio_dt_spec *gpio_get_dt_spec(enum gpio_signal signal);
+
+#undef IOEXPANDER_ID_FROM_INST_WITH_COMMA
diff --git a/zephyr/shim/include/zephyr_hooks_shim.h b/zephyr/shim/include/zephyr_hooks_shim.h
new file mode 100644
index 0000000000..3e0c43088f
--- /dev/null
+++ b/zephyr/shim/include/zephyr_hooks_shim.h
@@ -0,0 +1,63 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#if !defined(__CROS_EC_HOOKS_H) || defined(__CROS_EC_ZEPHYR_HOOKS_SHIM_H)
+#error "This file must only be included from hooks.h. Include hooks.h directly."
+#endif
+#define __CROS_EC_ZEPHYR_HOOKS_SHIM_H
+
+#include "common.h"
+#include "cros_version.h"
+
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+
+/**
+ * The internal data structure stored for a deferred function.
+ */
+struct deferred_data {
+	struct k_work_delayable *work;
+};
+
+/**
+ * See include/hooks.h for documentation.
+ */
+int hook_call_deferred(const struct deferred_data *data, int us);
+
+#define DECLARE_DEFERRED(routine)                                    \
+	K_WORK_DELAYABLE_DEFINE(routine##_work_data,                 \
+				(void (*)(struct k_work *))routine); \
+	__maybe_unused const struct deferred_data routine##_data = { \
+		.work = &routine##_work_data,                        \
+	}
+
+/**
+ * Record describing a single hook routine.
+ */
+struct zephyr_shim_hook_info {
+	void (*routine)(void);
+	uint16_t priority; /* HOOK_PRIO_LAST = 9999 */
+};
+
+/*
+ * List of hook routines.
+ *
+ * Values are contiguous, where *start is the first and *(end - 1) is the last.
+ */
+struct zephyr_shim_hook_list {
+	const struct zephyr_shim_hook_info *start;
+	const struct zephyr_shim_hook_info *end;
+};
+
+/**
+ * See include/hooks.h for documentation.
+ */
+#define DECLARE_HOOK(_hooktype, _routine, _priority)                 \
+	static const STRUCT_SECTION_ITERABLE_ALTERNATE(              \
+		zephyr_shim_hook_##_hooktype, zephyr_shim_hook_info, \
+		_cros_hook_##_hooktype##_##_routine) = {             \
+		.routine = _routine,                                 \
+		.priority = _priority,                               \
+	}
diff --git a/zephyr/shim/include/zephyr_host_command.h b/zephyr/shim/include/zephyr_host_command.h
new file mode 100644
index 0000000000..844f9ae395
--- /dev/null
+++ b/zephyr/shim/include/zephyr_host_command.h
@@ -0,0 +1,57 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#if !defined(__CROS_EC_HOST_COMMAND_H) || \
+	defined(__CROS_EC_ZEPHYR_HOST_COMMAND_H)
+#error "This file must only be included from host_command.h. " \
+	"Include host_command.h directly"
+#endif
+#define __CROS_EC_ZEPHYR_HOST_COMMAND_H
+
+#include <stdbool.h>
+
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+
+/* Initializes and runs the host command handler loop.  */
+void host_command_task(void *u);
+
+/* Takes over the main thread and runs the host command loop. */
+void host_command_main(void);
+
+/*
+ * Returns the main thread id. Will be the same as the HOSTCMD thread
+ * when CONFIG_TASK_HOSTCMD_THREAD_MAIN is enabled.
+ */
+k_tid_t get_main_thread(void);
+
+/*
+ * Returns the HOSTCMD thread id. Will be different than the main thread
+ * when CONFIG_TASK_HOSTCMD_THREAD_DEDICATED is enabled.
+ */
+k_tid_t get_hostcmd_thread(void);
+
+#ifdef CONFIG_PLATFORM_EC_HOSTCMD
+
+/**
+ * See include/host_command.h for documentation.
+ */
+#define DECLARE_HOST_COMMAND(_command, _routine, _version_mask)         \
+	static const STRUCT_SECTION_ITERABLE(host_command,              \
+					     _cros_hcmd_##_command) = { \
+		.command = _command,                                    \
+		.handler = _routine,                                    \
+		.version_mask = _version_mask,                          \
+	}
+#else /* !CONFIG_PLATFORM_EC_HOSTCMD */
+
+/*
+ * Create a global var to reference the host command. The linker should remove
+ * it since it is never referenced.
+ */
+#define DECLARE_HOST_COMMAND(command, routine, version_mask) \
+	int __remove_##command = ((int)(routine))
+
+#endif /* CONFIG_PLATFORM_EC_HOSTCMD */
diff --git a/zephyr/shim/include/zephyr_mkbp_event.h b/zephyr/shim/include/zephyr_mkbp_event.h
new file mode 100644
index 0000000000..0221be81d4
--- /dev/null
+++ b/zephyr/shim/include/zephyr_mkbp_event.h
@@ -0,0 +1,23 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#if !defined(__CROS_EC_MKBP_EVENT_H) || defined(__CROS_EC_ZEPHYR_MKBP_EVENT_H)
+#error "This file must only be included from mkbp_event.h. " \
+	"Include mkbp_event.h directly"
+#endif
+#define __CROS_EC_ZEPHYR_MKBP_EVENT_H
+
+const struct mkbp_event_source *
+zephyr_find_mkbp_event_source(uint8_t event_type);
+
+/**
+ * See include/mkbp_event.h for documentation.
+ */
+#define DECLARE_EVENT_SOURCE(_type, _func)                             \
+	static const STRUCT_SECTION_ITERABLE(mkbp_event_source,        \
+					     _cros_evtsrc_##_func) = { \
+		.event_type = _type,                                   \
+		.get_data = _func,                                     \
+	}
diff --git a/zephyr/shim/include/zephyr_shim.h b/zephyr/shim/include/zephyr_shim.h
new file mode 100644
index 0000000000..dce1706c5b
--- /dev/null
+++ b/zephyr/shim/include/zephyr_shim.h
@@ -0,0 +1,36 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __BOARD_H
+#define __BOARD_H
+
+#include "common.h"
+
+#include <zephyr/devicetree.h>
+
+/* Included shimed version of gpio signal. */
+#include "gpio_signal.h"
+
+/* Include shimmed version of power signal */
+#include "power/power.h"
+
+/* Include board specific i2c mapping if I2C is enabled. */
+#if defined(CONFIG_I2C)
+#include "i2c/i2c.h"
+#endif
+
+/* Include board specific sensor configuration if motionsense is enabled */
+#ifdef CONFIG_MOTIONSENSE
+#include "motionsense_sensors_defs.h"
+#endif
+
+/*
+ * Should generate enums for each charger.
+ */
+#ifdef CONFIG_PLATFORM_EC_OCPC
+#include "charger_enum.h"
+#endif
+
+#endif /* __BOARD_H */
diff --git a/zephyr/shim/include/zephyr_write_protect.h b/zephyr/shim/include/zephyr_write_protect.h
new file mode 100644
index 0000000000..f3b267cb51
--- /dev/null
+++ b/zephyr/shim/include/zephyr_write_protect.h
@@ -0,0 +1,46 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_ZEPHYR_WRITE_PROTECT_H
+#define __CROS_EC_ZEPHYR_WRITE_PROTECT_H
+
+#include "gpio/gpio_int.h"
+#include "gpio_signal.h"
+
+#include <zephyr/drivers/gpio.h>
+
+/**
+ * Check the WP state. The function depends on the alias 'gpio_wp'. It is used
+ * to replace the enum-name.
+ *
+ * @return true if the WP is active, false otherwise.
+ */
+static inline int write_protect_is_asserted(void)
+{
+#if defined(CONFIG_WP_ALWAYS)
+	return true;
+#elif defined(CONFIG_WP_DISABLE)
+	return false;
+#else
+	return gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_wp));
+#endif
+}
+
+/**
+ * Enable interrupt for WP pin. The interrupt itself has to be defined in a node
+ * with compatible = "cros-ec,gpio-interrupts" and pointed by the alias int_wp.
+ *
+ * @return 0 if success
+ */
+static inline int write_protect_enable_interrupt(void)
+{
+#if DT_NODE_EXISTS(DT_ALIAS(int_wp))
+	return gpio_enable_dt_interrupt(GPIO_INT_FROM_NODE(DT_ALIAS(int_wp)));
+#else
+	return -1;
+#endif
+}
+
+#endif /* __CROS_EC_ZEPHYR_WRITE_PROTECT_H */
diff --git a/zephyr/shim/src/CMakeLists.txt b/zephyr/shim/src/CMakeLists.txt
index 5f8eaf88ad..ace881454d 100644
--- a/zephyr/shim/src/CMakeLists.txt
+++ b/zephyr/shim/src/CMakeLists.txt
@@ -1,6 +1,97 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
-zephyr_sources(console.c)
-zephyr_sources_ifdef(CONFIG_PLATFORM_EC_TIMER hwtimer.c)
+zephyr_library_sources(console.c)
+zephyr_library_sources(crc.c)
+zephyr_library_sources(gpio.c)
+zephyr_library_sources(gpio_int.c)
+
+add_subdirectory("buttons")
+add_subdirectory("cbi")
+add_subdirectory("led_driver")
+
+if (DEFINED CONFIG_SOC_FAMILY_INTEL_ISH)
+  zephyr_library_sources(ish_system.c)
+elseif (DEFINED CONFIG_ARCH_POSIX)
+  zephyr_library_sources(ztest_system.c)
+else()
+  zephyr_library_sources(system.c)
+endif()
+
+zephyr_library_sources_ifdef(no_libgcc                  libgcc_${ARCH}.S)
+
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC_RETIMER_ANX7452 anx7452_usb_mux.c)
+zephyr_library_sources_ifdef(CONFIG_NAMED_ADC_CHANNELS      adc.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_BATTERY
+                                                            battery.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_BC12_DETECT_RT9490
+                                                            bc12_rt9490.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER_RT9490
+                                                            chg_rt9490.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER     charger.c)
+zephyr_library_sources_ifdef(CONFIG_AP_PWRSEQ               chipset_api.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI
+                                                            espi.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FAN         fan.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FLASH_CROS  flash.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_GPIO_ID
+							    gpio_id.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_HOOKS       hooks.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_HOSTCMD     host_command.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_HOSTCMD_CONSOLE
+                                                            console_buffer.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_IOEX_CROS_DRV
+                                                            ioex.c
+                                                            ioex_drv.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC_RETIMER_KB8010 kb8010_usb_mux.c)
+if (NOT DEFINED CONFIG_PLATFORM_EC_KEYBOARD_DISCRETE)
+  zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_KEYBOARD
+                                                            keyboard_raw.c)
+endif()
+zephyr_library_sources_ifdef(CONFIG_CROS_EC_KEYSCAN         keyscan.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LOG_BACKEND_CONSOLE_BUFFER
+                             log_backend_console_buffer.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_MKBP_EVENT  mkbp_event.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_MOTIONSENSE
+                                                            motionsense_sensors.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_PANIC       panic.c)
+zephyr_library_sources_ifdef(CONFIG_CROS_EC_POWER_SIGNAL_LIST
+							    power.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_PWM_HC      pwm_hc.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LED_PWM     pwm_led.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_RANDOM      random.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_RTC         rtc.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_SWITCHCAP_GPIO
+							    switchcap_gpio.c)
+zephyr_library_sources_ifdef(CONFIG_CROS_EC_SWITCHCAP_LN9310
+							    switchcap_ln9310.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_TEMP_SENSOR temp_sensors.c
+                                                            thermal.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_TIMER       hwtimer.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_I2C         i2c.c)
+zephyr_library_sources_ifdef(CONFIG_SHIMMED_TASKS           tasks.c)
+zephyr_library_sources_ifdef(CONFIG_WATCHDOG                watchdog.c)
+if (DEFINED CONFIG_PLATFORM_EC_USB_CHARGER)
+  zephyr_library_sources_ifndef(CONFIG_PLATFORM_EC_BC12_SINGLE_DRIVER
+                                                            bc12.c)
+endif()
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_BC12_DETECT_PI3USB9201
+	                                                     bc12_pi3usb9201.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC_PPC    ppc.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_TCPM_NCT38XX
+                                                            tcpc_nct38xx.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC        tcpc.c)
+
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBA        usba.c)
+zephyr_library_sources_ifdef(CONFIG_AP_PWRSEQ power_host_sleep_api.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_MUX     usb_muxes.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_BB
+                                                            bb_retimer_usb_mux.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_HB
+                                                            bb_retimer_usb_mux.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_SYSTEM_SAFE_MODE system_safe_mode.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_SHA256_HW_ZEPHYR
+	                                                    sha256_hw.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_HOST_COMMAND_MEMORY_DUMP
+	                                                    register_memory_dump.c)
diff --git a/zephyr/shim/src/adc.c b/zephyr/shim/src/adc.c
new file mode 100644
index 0000000000..661a3c40e1
--- /dev/null
+++ b/zephyr/shim/src/adc.c
@@ -0,0 +1,79 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc.h"
+#include "zephyr_adc.h"
+
+#include <zephyr/devicetree/io-channels.h>
+#include <zephyr/drivers/adc.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(shim_adc, LOG_LEVEL_ERR);
+
+#if defined(CONFIG_PLATFORM_EC_ADC_CMD) && defined(CONFIG_ADC_SHELL)
+#error "Define only one 'adc' console command."
+#endif
+
+#define ADC_CHANNEL_INIT(node_id) \
+	[ZSHIM_ADC_ID(node_id)] = {                                       \
+		.name = DT_NODE_FULL_NAME(node_id),                       \
+		.dev = DEVICE_DT_GET(DT_IO_CHANNELS_CTLR(node_id)),       \
+		.input_ch = DT_IO_CHANNELS_INPUT(node_id),                \
+		.factor_mul = DT_PROP(node_id, mul),                      \
+		.factor_div = DT_PROP(node_id, div),                      \
+		.channel_cfg = {                                          \
+			.channel_id = DT_IO_CHANNELS_INPUT(node_id),      \
+			.gain = DT_STRING_TOKEN(node_id, gain),           \
+			.reference = DT_STRING_TOKEN(node_id, reference), \
+			.acquisition_time =                               \
+				DT_PROP(node_id, acquisition_time),       \
+			.differential = DT_PROP(node_id, differential),   \
+		},                                                        \
+	},
+#ifdef CONFIG_ADC_CHANNELS_RUNTIME_CONFIG
+struct adc_t adc_channels[] = { DT_FOREACH_CHILD(DT_INST(0, named_adc_channels),
+						 ADC_CHANNEL_INIT) };
+#else
+const struct adc_t adc_channels[] = { DT_FOREACH_CHILD(
+	DT_INST(0, named_adc_channels), ADC_CHANNEL_INIT) };
+#endif
+
+static int init_device_bindings(void)
+{
+	for (int i = 0; i < ARRAY_SIZE(adc_channels); i++) {
+		if (!device_is_ready(adc_channels[i].dev))
+			k_oops();
+
+		adc_channel_setup(adc_channels[i].dev,
+				  &adc_channels[i].channel_cfg);
+	}
+
+	return 0;
+}
+SYS_INIT(init_device_bindings, POST_KERNEL, 51);
+
+test_mockable int adc_read_channel(enum adc_channel ch)
+{
+	int ret = 0, rv;
+	struct adc_sequence seq = {
+		.options = NULL,
+		.channels = BIT(adc_channels[ch].input_ch),
+		.buffer = &ret,
+		.buffer_size = sizeof(ret),
+		.resolution = CONFIG_PLATFORM_EC_ADC_RESOLUTION,
+		.oversampling = CONFIG_PLATFORM_EC_ADC_OVERSAMPLING,
+		.calibrate = false,
+	};
+
+	rv = adc_read(adc_channels[ch].dev, &seq);
+	if (rv)
+		return rv;
+
+	adc_raw_to_millivolts(adc_ref_internal(adc_channels[ch].dev),
+			      ADC_GAIN_1, CONFIG_PLATFORM_EC_ADC_RESOLUTION,
+			      &ret);
+	ret = (ret * adc_channels[ch].factor_mul) / adc_channels[ch].factor_div;
+	return ret;
+}
diff --git a/zephyr/shim/src/anx7452_usb_mux.c b/zephyr/shim/src/anx7452_usb_mux.c
new file mode 100644
index 0000000000..a2ceef5a3a
--- /dev/null
+++ b/zephyr/shim/src/anx7452_usb_mux.c
@@ -0,0 +1,14 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "usb_mux.h"
+#include "usbc/usb_muxes.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/sys/util_macro.h>
+
+const struct anx7452_control anx7452_controls[] = {
+	USB_MUX_ANX7452_CONTROLS_ARRAY
+};
diff --git a/zephyr/shim/src/battery.c b/zephyr/shim/src/battery.c
new file mode 100644
index 0000000000..733c1ff82b
--- /dev/null
+++ b/zephyr/shim/src/battery.c
@@ -0,0 +1,73 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery_fuel_gauge.h"
+
+#include <zephyr/devicetree.h>
+
+#define NODE_FUEL_GAUGE(node) \
+	{ \
+	.manuf_name = DT_PROP(node, manuf_name), \
+	.device_name = DT_PROP(node, device_name), \
+	.ship_mode = { \
+		.wb_support = DT_PROP_OR(node, ship_mode_wb_support, 0), \
+		.reg_addr = DT_PROP(node, ship_mode_reg_addr), \
+		.reg_data = DT_PROP(node, ship_mode_reg_data), \
+	}, \
+	.sleep_mode = { \
+		.sleep_supported = DT_PROP_OR(node, sleep_mode_support, 0), \
+		.reg_addr = DT_PROP_OR(node, sleep_mode_reg_addr, 0), \
+		.reg_data = DT_PROP_OR(node, sleep_mode_reg_data, 0), \
+	}, \
+	.fet = { \
+		.mfgacc_support = DT_PROP_OR(node, fet_mfgacc_support, 0), \
+		.mfgacc_smb_block = DT_PROP_OR(node, fet_mfgacc_smb_block, 0), \
+		.reg_addr = DT_PROP_OR(node, fet_reg_addr, 0), \
+		.reg_mask = DT_PROP(node, fet_reg_mask), \
+		.disconnect_val = DT_PROP(node, fet_disconnect_val), \
+		.cfet_mask = DT_PROP_OR(node, fet_cfet_mask, 0), \
+		.cfet_off_val = DT_PROP_OR(node, fet_cfet_off_val, 0), \
+	}, \
+	COND_CODE_1(UTIL_AND(IS_ENABLED(CONFIG_BATTERY_MEASURE_IMBALANCE), \
+			     DT_NODE_HAS_PROP(node, imbalance_mv)), \
+		(.imbalance_mv = DT_STRING_TOKEN(node, imbalance_mv),), ()) \
+},
+
+#define NODE_BATT_INFO(node)                                                 \
+	{                                                                    \
+		.voltage_max = DT_PROP(node, voltage_max),                   \
+		.voltage_normal = DT_PROP(node, voltage_normal),             \
+		.voltage_min = DT_PROP(node, voltage_min),                   \
+		.precharge_voltage = DT_PROP_OR(node, precharge_voltage, 0), \
+		.precharge_current = DT_PROP_OR(node, precharge_current, 0), \
+		.start_charging_min_c = DT_PROP(node, start_charging_min_c), \
+		.start_charging_max_c = DT_PROP(node, start_charging_max_c), \
+		.charging_min_c = DT_PROP(node, charging_min_c),             \
+		.charging_max_c = DT_PROP(node, charging_max_c),             \
+		.discharging_min_c = DT_PROP(node, discharging_min_c),       \
+		.discharging_max_c = DT_PROP(node, discharging_max_c),       \
+	},
+
+#define NODE_BATT_PARAMS(node)                            \
+	{ .fuel_gauge = NODE_FUEL_GAUGE(node).batt_info = \
+		  NODE_BATT_INFO(node) },
+
+#if DT_HAS_COMPAT_STATUS_OKAY(battery_smart)
+
+const struct board_batt_params board_battery_info[] = { DT_FOREACH_STATUS_OKAY(
+	battery_smart, NODE_BATT_PARAMS) };
+
+#if DT_NODE_EXISTS(DT_NODELABEL(default_battery))
+#define BAT_ENUM(node) DT_CAT(BATTERY_, node)
+const enum battery_type DEFAULT_BATTERY_TYPE =
+	BATTERY_TYPE(DT_NODELABEL(default_battery));
+#endif
+
+#if DT_NODE_EXISTS(DT_NODELABEL(default_battery_3s))
+#define BAT_ENUM(node) DT_CAT(BATTERY_, node)
+const enum battery_type DEFAULT_BATTERY_TYPE_3S =
+	BATTERY_TYPE(DT_NODELABEL(default_battery_3s));
+#endif
+#endif /* DT_HAS_COMPAT_STATUS_OKAY(battery_smart) */
diff --git a/zephyr/shim/src/bb_retimer_usb_mux.c b/zephyr/shim/src/bb_retimer_usb_mux.c
new file mode 100644
index 0000000000..b0e3944528
--- /dev/null
+++ b/zephyr/shim/src/bb_retimer_usb_mux.c
@@ -0,0 +1,32 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "usb_mux.h"
+#include "usbc/usb_muxes.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/sys/util_macro.h>
+
+BB_RETIMER_CHECK_SAME_CONTROLS(BB_RETIMER_INSTANCES_LIST)
+
+/**
+ * @brief bb_controls array should be constant only if configuration cannot
+ *        change in runtime
+ */
+#define BB_CONTROLS_CONST                                                    \
+	COND_CODE_1(CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_BB_RUNTIME_CONFIG, \
+		    (), (const))
+
+/**
+ * Define bb_controls for BB retimers in USB muxes chain e.g.
+ * [0] = {
+ *         .retimer_rst_gpio = IOEX_USB_C0_BB_RETIMER_RST,
+ *         .usb_ls_en_gpio = IOEX_USB_C0_BB_RETIMER_LS_EN,
+ * },
+ * [1] = { ... },
+ */
+BB_CONTROLS_CONST struct bb_usb_control bb_controls[] = {
+	USB_MUX_BB_RETIMERS_CONTROLS_ARRAY
+};
diff --git a/zephyr/shim/src/bc12.c b/zephyr/shim/src/bc12.c
new file mode 100644
index 0000000000..ed5fe101b2
--- /dev/null
+++ b/zephyr/shim/src/bc12.c
@@ -0,0 +1,40 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "usb_charge.h"
+#include "usbc/bc12_pi3usb9201.h"
+#include "usbc/bc12_rt1718s.h"
+#include "usbc/bc12_rt1739.h"
+#include "usbc/bc12_rt9490.h"
+#include "usbc/tcpc_rt1718s.h"
+#include "usbc/utils.h"
+
+#include <zephyr/devicetree.h>
+
+/* Check RT1718S dependency. BC12 node must be dependent on TCPC node. */
+#if DT_HAS_COMPAT_STATUS_OKAY(RT1718S_BC12_COMPAT)
+BUILD_ASSERT(DT_HAS_COMPAT_STATUS_OKAY(RT1718S_TCPC_COMPAT));
+#endif
+
+#define BC12_CHIP_ENTRY(usbc_id, bc12_id, chip_fn) \
+	[USBC_PORT_NEW(usbc_id)] = chip_fn(bc12_id)
+
+#define CHECK_COMPAT(compat, usbc_id, bc12_id, config)   \
+	COND_CODE_1(DT_NODE_HAS_COMPAT(bc12_id, compat), \
+		    (BC12_CHIP_ENTRY(usbc_id, bc12_id, config)), ())
+
+#define BC12_CHIP_FIND(usbc_id, bc12_id)                                       \
+	CHECK_COMPAT(RT1718S_BC12_COMPAT, usbc_id, bc12_id, BC12_CHIP_RT1718S) \
+	CHECK_COMPAT(RT1739_BC12_COMPAT, usbc_id, bc12_id, BC12_CHIP_RT1739)   \
+	CHECK_COMPAT(RT9490_BC12_COMPAT, usbc_id, bc12_id, BC12_CHIP_RT9490)   \
+	CHECK_COMPAT(PI3USB9201_COMPAT, usbc_id, bc12_id, BC12_CHIP_PI3USB9201)
+
+#define BC12_CHIP(usbc_id)                           \
+	COND_CODE_1(DT_NODE_HAS_PROP(usbc_id, bc12), \
+		    (BC12_CHIP_FIND(usbc_id, DT_PHANDLE(usbc_id, bc12))), ())
+
+/* BC1.2 controllers */
+struct bc12_config bc12_ports[CHARGE_PORT_COUNT] = { DT_FOREACH_STATUS_OKAY(
+	named_usbc_port, BC12_CHIP) };
diff --git a/zephyr/shim/src/bc12_pi3usb9201.c b/zephyr/shim/src/bc12_pi3usb9201.c
new file mode 100644
index 0000000000..d41fcc3212
--- /dev/null
+++ b/zephyr/shim/src/bc12_pi3usb9201.c
@@ -0,0 +1,54 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define DT_DRV_COMPAT pericom_pi3usb9201
+
+#include "bc12/pi3usb9201_public.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "i2c/i2c.h"
+#include "task.h"
+#include "usb_charge.h"
+#include "usb_pd.h"
+#include "usbc/utils.h"
+
+#include <zephyr/devicetree.h>
+
+#define USBC_PORT_BC12(usbc_id, bc12_id)                \
+	[USBC_PORT_NEW(usbc_id)] = {                    \
+		.i2c_port = I2C_PORT_BY_DEV(bc12_id),   \
+		.i2c_addr_flags = DT_REG_ADDR(bc12_id), \
+	},
+
+#define PI3SUSB9201_CHECK(usbc_id, bc12_id)                          \
+	COND_CODE_1(DT_NODE_HAS_COMPAT(bc12_id, pericom_pi3usb9201), \
+		    (USBC_PORT_BC12(usbc_id, bc12_id)), ())
+
+#define BC12_CHIP(usbc_id)                                                   \
+	COND_CODE_1(DT_NODE_HAS_PROP(usbc_id, bc12),                         \
+		    (PI3SUSB9201_CHECK(usbc_id, DT_PHANDLE(usbc_id, bc12))), \
+		    ())
+
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	DT_FOREACH_STATUS_OKAY(named_usbc_port, BC12_CHIP)
+};
+
+static void bc12_enable_irqs(void){
+	DT_INST_FOREACH_STATUS_OKAY(BC12_GPIO_ENABLE_INTERRUPT)
+} DECLARE_HOOK(HOOK_INIT, bc12_enable_irqs, HOOK_PRIO_DEFAULT);
+
+#if DT_INST_NODE_HAS_PROP(0, irq)
+void usb0_evt(enum gpio_signal signal)
+{
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+#endif
+
+#if DT_INST_NODE_HAS_PROP(1, irq)
+void usb1_evt(enum gpio_signal signal)
+{
+	usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+}
+#endif
diff --git a/zephyr/shim/src/bc12_rt9490.c b/zephyr/shim/src/bc12_rt9490.c
new file mode 100644
index 0000000000..2da28050ec
--- /dev/null
+++ b/zephyr/shim/src/bc12_rt9490.c
@@ -0,0 +1,43 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define DT_DRV_COMPAT richtek_rt9490
+
+#include "driver/charger/rt9490.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "usbc/utils.h"
+
+#include <zephyr/devicetree.h>
+
+static void rt9490_bc12_enable_irqs(void)
+{
+	DT_INST_FOREACH_STATUS_OKAY(BC12_GPIO_ENABLE_INTERRUPT);
+}
+DECLARE_HOOK(HOOK_INIT, rt9490_bc12_enable_irqs, HOOK_PRIO_DEFAULT);
+
+#define RT9490_DISPATCH_INTERRUPT(usbc_id, bc12_id)                        \
+	IF_ENABLED(DT_NODE_HAS_PROP(bc12_id, irq),                         \
+		   (case GPIO_SIGNAL(                                      \
+			    DT_PHANDLE(DT_PHANDLE(bc12_id, irq), irq_pin)) \
+		    : rt9490_interrupt(USBC_PORT_NEW(usbc_id));            \
+		    break;))
+
+#define RT9490_CHECK(usbc_id, bc12_id)                           \
+	COND_CODE_1(DT_NODE_HAS_COMPAT(bc12_id, richtek_rt9490), \
+		    (RT9490_DISPATCH_INTERRUPT(usbc_id, bc12_id)), ())
+
+#define RT9490_INTERRUPT(usbc_id)                    \
+	COND_CODE_1(DT_NODE_HAS_PROP(usbc_id, bc12), \
+		    (RT9490_CHECK(usbc_id, DT_PHANDLE(usbc_id, bc12))), ())
+
+void rt9490_bc12_dt_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+		DT_FOREACH_STATUS_OKAY(named_usbc_port, RT9490_INTERRUPT)
+	default:
+		break;
+	}
+}
diff --git a/zephyr/shim/src/buttons/CMakeLists.txt b/zephyr/shim/src/buttons/CMakeLists.txt
new file mode 100644
index 0000000000..de15c60889
--- /dev/null
+++ b/zephyr/shim/src/buttons/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+zephyr_library_sources_ifdef(CONFIG_INPUT_GPIO_KEYS         buttons.c)
+zephyr_library_sources_ifdef(CONFIG_INPUT_GPIO_KEYS         power_button.c)
diff --git a/zephyr/shim/src/buttons/buttons.c b/zephyr/shim/src/buttons/buttons.c
new file mode 100644
index 0000000000..32f79705c3
--- /dev/null
+++ b/zephyr/shim/src/buttons/buttons.c
@@ -0,0 +1,37 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "power_button.h"
+
+#include <zephyr/device.h>
+#include <zephyr/input/input.h>
+#include <zephyr/logging/log.h>
+
+#include <dt-bindings/buttons.h>
+
+LOG_MODULE_REGISTER(button, CONFIG_GPIO_LOG_LEVEL);
+
+#define DT_DRV_COMPAT zephyr_gpio_keys
+
+static void buttons_cb_handler(struct input_event *evt)
+{
+	if (evt->type != INPUT_EV_KEY) {
+		return;
+	}
+
+	LOG_DBG("Button %s, code=%u, pin_state=%d", evt->dev->name, evt->code,
+		evt->value);
+
+	switch (evt->code) {
+	case BUTTON_POWER:
+		handle_power_button(evt->value);
+		break;
+	default:
+		LOG_ERR("Unknown button code=%u", evt->code);
+		break;
+	}
+}
+INPUT_LISTENER_CB_DEFINE(DEVICE_DT_GET_ONE(zephyr_gpio_keys),
+			 buttons_cb_handler);
diff --git a/zephyr/shim/src/buttons/power_button.c b/zephyr/shim/src/buttons/power_button.c
new file mode 100644
index 0000000000..8a4ebc9ac3
--- /dev/null
+++ b/zephyr/shim/src/buttons/power_button.c
@@ -0,0 +1,121 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "hooks.h"
+#include "host_command.h"
+#include "power_button.h"
+#include "task.h"
+#include "util.h"
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/shell/shell.h>
+
+LOG_MODULE_REGISTER(power_button, CONFIG_GPIO_LOG_LEVEL);
+
+#define POWER_BUTTON_NODE DT_NODELABEL(power_button)
+static const struct gpio_dt_spec power_button =
+	GPIO_DT_SPEC_GET(POWER_BUTTON_NODE, gpios);
+
+static struct power_button_data_s {
+	int8_t state;
+} power_button_data;
+
+int power_button_is_pressed(void)
+{
+	return power_button_data.state;
+}
+
+int power_button_signal_asserted(void)
+{
+	return gpio_pin_get_dt(&power_button);
+}
+
+int power_button_wait_for_release(int timeout_us)
+{
+	int check_interval_us = 30000;
+	bool released;
+
+	released =
+		WAIT_FOR(!(power_button_data.state), timeout_us,
+			 task_wait_event(MIN(timeout_us, check_interval_us)));
+
+	return released ? 0 : -ETIMEDOUT;
+}
+
+void handle_power_button(int8_t new_pin_state)
+{
+	LOG_DBG("Handling power button state=%d", new_pin_state);
+
+	power_button_data.state = new_pin_state;
+
+	hook_notify(HOOK_POWER_BUTTON_CHANGE);
+	host_set_single_event(EC_HOST_EVENT_POWER_BUTTON);
+}
+
+void power_button_simulate_press(unsigned int duration)
+{
+	int8_t temp = power_button_data.state;
+
+	LOG_INF("Simulating %d ms power button press.", duration);
+	handle_power_button(1);
+
+	if (duration > 0)
+		k_sleep(K_MSEC(duration));
+
+	LOG_INF("Simulating power button release.");
+	handle_power_button(0);
+
+	power_button_data.state = temp;
+}
+
+/* LCOV_EXCL_START */
+/* Stubbed to be overridden by specific x86 board */
+__overridable void power_button_pch_press(void)
+{
+}
+
+/* Stubbed to be overridden by specific x86 board */
+__overridable void power_button_pch_release(void)
+{
+}
+
+/* Stubbed to be overridden by specific x86 board */
+__overridable void power_button_pch_pulse(void)
+{
+}
+
+/* Stubbed to be overridden by specific board */
+__overridable int64_t get_time_dsw_pwrok(void)
+{
+	return 0;
+}
+
+/* Stubbed to be overridden by specific board */
+__overridable void board_pwrbtn_to_pch(int level)
+{
+}
+/* LCOV_EXCL_STOP */
+
+/*****************************************************************************/
+/* Console commands */
+static int command_powerbtn(const struct shell *shell, size_t argc, char **argv)
+{
+	int ms = 200; /* Press duration in ms */
+	char *e;
+
+	if (argc > 1) {
+		ms = strtoi(argv[1], &e, 0);
+		if (*e || ms < 0)
+			return EC_ERROR_PARAM1;
+	}
+
+	power_button_simulate_press(ms);
+	return EC_SUCCESS;
+}
+
+SHELL_CMD_ARG_REGISTER(powerbtn, NULL,
+		       "Simulate power button press for \'n\' msec",
+		       command_powerbtn, 1, 1);
diff --git a/zephyr/shim/src/buttons/power_button.h b/zephyr/shim/src/buttons/power_button.h
new file mode 100644
index 0000000000..7c220f99ca
--- /dev/null
+++ b/zephyr/shim/src/buttons/power_button.h
@@ -0,0 +1,13 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef BUTTONS_POWER_BUTTON_H_
+#define BUTTONS_POWER_BUTTON_H_
+
+#include <stdint.h>
+
+void handle_power_button(int8_t new_pin_state);
+
+#endif /* BUTTONS_POWER_BUTTON_H_ */
diff --git a/zephyr/shim/src/cbi/CMakeLists.txt b/zephyr/shim/src/cbi/CMakeLists.txt
new file mode 100644
index 0000000000..42e825a3c0
--- /dev/null
+++ b/zephyr/shim/src/cbi/CMakeLists.txt
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CBI        cros_cbi.c
+                                                           cros_cbi_fw_config.c
+                                                           cros_cbi_ssfc.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CBI_EEPROM cbi_eeprom.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CBI_FLASH cbi_flash.c)
diff --git a/zephyr/shim/src/cbi/cbi_eeprom.c b/zephyr/shim/src/cbi/cbi_eeprom.c
new file mode 100644
index 0000000000..f2343ffac8
--- /dev/null
+++ b/zephyr/shim/src/cbi/cbi_eeprom.c
@@ -0,0 +1,79 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "cros_board_info.h"
+#include "write_protect.h"
+
+#include <zephyr/drivers/eeprom.h>
+#include <zephyr/drivers/gpio.h>
+
+#define CBI_EEPROM_NODE DT_NODELABEL(cbi_eeprom)
+
+BUILD_ASSERT(DT_NODE_EXISTS(CBI_EEPROM_NODE), "cbi_eeprom node not defined");
+
+#ifdef CONFIG_PLATFORM_EC_EEPROM_CBI_WP
+#if !DT_NODE_EXISTS(DT_ALIAS(gpio_cbi_wp))
+#error gpio_cbi_wp alias has to point to the CBI WP output pin.
+#endif
+
+void cbi_latch_eeprom_wp(void)
+{
+	cprints(CC_SYSTEM, "CBI WP latched");
+	gpio_pin_set_dt(GPIO_DT_FROM_ALIAS(gpio_cbi_wp), 1);
+}
+#endif /* CONFIG_PLATFORM_EC_EEPROM_CBI_WP */
+
+test_mockable_static int eeprom_load(uint8_t offset, uint8_t *data, int len)
+{
+	const struct device *dev;
+
+	dev = DEVICE_DT_GET(CBI_EEPROM_NODE);
+
+	if (!device_is_ready(dev)) {
+		return -ENODEV;
+	}
+
+	return eeprom_read(dev, offset, data, len);
+}
+
+static int eeprom_is_write_protected(void)
+{
+	if (IS_ENABLED(CONFIG_PLATFORM_EC_BYPASS_CBI_EEPROM_WP_CHECK)) {
+		return 0;
+	}
+
+#ifdef CONFIG_PLATFORM_EC_EEPROM_CBI_WP
+	return gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_cbi_wp));
+#else
+	/* GSC controlled write protect */
+	return write_protect_is_asserted();
+#endif
+}
+
+static int eeprom_store(uint8_t *cbi)
+{
+	const struct device *dev;
+
+	dev = DEVICE_DT_GET(CBI_EEPROM_NODE);
+
+	if (!device_is_ready(dev)) {
+		return -ENODEV;
+	}
+
+	return eeprom_write(dev, 0, cbi,
+			    ((struct cbi_header *)cbi)->total_size);
+}
+
+static const struct cbi_storage_driver eeprom_drv = {
+	.store = eeprom_store,
+	.load = eeprom_load,
+	.is_protected = eeprom_is_write_protected,
+};
+
+const struct cbi_storage_config_t cbi_config = {
+	.storage_type = CBI_STORAGE_TYPE_EEPROM,
+	.drv = &eeprom_drv,
+};
diff --git a/zephyr/shim/src/cbi/cbi_flash.c b/zephyr/shim/src/cbi/cbi_flash.c
new file mode 100644
index 0000000000..53518a09a7
--- /dev/null
+++ b/zephyr/shim/src/cbi/cbi_flash.c
@@ -0,0 +1,64 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi_flash.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "flash.h"
+#include "system.h"
+#include "write_protect.h"
+
+#include <zephyr/devicetree.h>
+
+LOG_MODULE_REGISTER(cbi_flash, LOG_LEVEL_ERR);
+
+static bool is_cbi_section(uint8_t offset, int len)
+{
+	if (len < 0) {
+		return false;
+	}
+	if (offset + len > CBI_IMAGE_SIZE) {
+		return false;
+	}
+	return true;
+}
+
+static int flash_load(uint8_t offset, uint8_t *data, int len)
+{
+	if (!is_cbi_section(offset, len)) {
+		return EC_ERROR_INVAL;
+	}
+	return crec_flash_unprotected_read(CBI_FLASH_OFFSET + offset, len,
+					   (char *)data);
+}
+
+static int flash_is_write_protected(void)
+{
+	return system_is_locked();
+}
+
+static int flash_store(uint8_t *cbi)
+{
+	int rv;
+
+	rv = crec_flash_physical_erase(CBI_FLASH_OFFSET, CBI_IMAGE_SIZE);
+	if (rv) {
+		LOG_ERR("CBI flash erase before write failed, rv: %d\n", rv);
+		return rv;
+	}
+	return crec_flash_physical_write(CBI_FLASH_OFFSET, CBI_IMAGE_SIZE,
+					 (const char *)cbi);
+}
+
+static const struct cbi_storage_driver flash_drv = {
+	.store = flash_store,
+	.load = flash_load,
+	.is_protected = flash_is_write_protected,
+};
+
+const struct cbi_storage_config_t cbi_config = {
+	.storage_type = CBI_STORAGE_TYPE_FLASH,
+	.drv = &flash_drv,
+};
diff --git a/zephyr/shim/src/cbi/cros_cbi.c b/zephyr/shim/src/cbi/cros_cbi.c
new file mode 100644
index 0000000000..e6fa3e8cd1
--- /dev/null
+++ b/zephyr/shim/src/cbi/cros_cbi.c
@@ -0,0 +1,16 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+#include "hooks.h"
+
+static void cros_cbi_ec_init(void)
+{
+	cros_cbi_ssfc_init();
+	cros_cbi_fw_config_init();
+}
+
+DECLARE_HOOK(HOOK_INIT, cros_cbi_ec_init, HOOK_PRIO_FIRST);
diff --git a/zephyr/shim/src/cbi/cros_cbi_fw_config.c b/zephyr/shim/src/cbi/cros_cbi_fw_config.c
new file mode 100644
index 0000000000..b4ea79d7fb
--- /dev/null
+++ b/zephyr/shim/src/cbi/cros_cbi_fw_config.c
@@ -0,0 +1,201 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(cros_cbi_fw_config, LOG_LEVEL_ERR);
+
+/*
+ * Validation macros.
+ * These are moved out of header files to avoid exposing them outside
+ * this file scope.
+ */
+
+/*
+ * Statically count the number of bits set in a 32 bit constant expression.
+ */
+#define BIT_SET(v, b) ((v >> b) & 1)
+#define BIT_COUNT(v)                                                         \
+	(BIT_SET(v, 31) + BIT_SET(v, 30) + BIT_SET(v, 29) + BIT_SET(v, 28) + \
+	 BIT_SET(v, 27) + BIT_SET(v, 26) + BIT_SET(v, 25) + BIT_SET(v, 24) + \
+	 BIT_SET(v, 23) + BIT_SET(v, 22) + BIT_SET(v, 21) + BIT_SET(v, 20) + \
+	 BIT_SET(v, 19) + BIT_SET(v, 18) + BIT_SET(v, 17) + BIT_SET(v, 16) + \
+	 BIT_SET(v, 15) + BIT_SET(v, 14) + BIT_SET(v, 13) + BIT_SET(v, 12) + \
+	 BIT_SET(v, 11) + BIT_SET(v, 10) + BIT_SET(v, 9) + BIT_SET(v, 8) +   \
+	 BIT_SET(v, 7) + BIT_SET(v, 6) + BIT_SET(v, 5) + BIT_SET(v, 4) +     \
+	 BIT_SET(v, 3) + BIT_SET(v, 2) + BIT_SET(v, 1) + BIT_SET(v, 0))
+
+/*
+ * Shorthand macros to access properties on the field node.
+ */
+#define FW_START(id) DT_PROP(id, start)
+#define FW_SIZE(id) DT_PROP(id, size)
+
+/*
+ * Calculate the mask of the field from the size.
+ */
+#define FW_MASK(id) ((1 << FW_SIZE(id)) - 1)
+
+/*
+ * Calculate the mask and shift it to the correct start bit.
+ */
+#define FW_SHIFT_MASK(id) (FW_MASK(id) << FW_START(id))
+
+/*
+ * For a child "cros-ec,cbi-fw-config-value" node, retrieve the
+ * size of the parent field this value is associated with.
+ */
+#define FW_PARENT_SIZE(id) DT_PROP(DT_PARENT(id), size)
+
+/*
+ * For a child "cros-ec,cbi-fw-config-value" node, retrieve the
+ * start of the parent field this value is associated with.
+ */
+#define FW_PARENT_START(id) DT_PROP(DT_PARENT(id), start)
+
+/*
+ * Validation check to ensure total field sizes do not exceed 32 bits.
+ * The FOREACH loop is nested, one to iterate through all the
+ * fw_config nodes, and another for the child field nodes in each
+ * of the fw_config nodes.
+ */
+#define PLUS_FIELD_SIZE(inst) +DT_PROP(inst, size)
+#define FIELDS_ALL_SIZE(inst) \
+	DT_FOREACH_CHILD_STATUS_OKAY(inst, PLUS_FIELD_SIZE)
+
+/*
+ * Result is the sum of all the field sizes.
+ */
+#define TOTAL_FW_CONFIG_NODES_SIZE \
+	(0 DT_FOREACH_STATUS_OKAY(CBI_FW_CONFIG_COMPAT, FIELDS_ALL_SIZE))
+
+BUILD_ASSERT(TOTAL_FW_CONFIG_NODES_SIZE <= 32,
+	     "CBI FW Config is bigger than 32 bits");
+
+/*
+ * Validation check to ensure there are no overlapping fields.
+ * OR together all the masks, count the bits, and compare against the
+ * total of the sizes. They should match.
+ */
+#define OR_FIELD_SHIFT_MASK(id) | FW_SHIFT_MASK(id)
+#define FIELDS_ALL_BITS_SET(inst) \
+	DT_FOREACH_CHILD_STATUS_OKAY(inst, OR_FIELD_SHIFT_MASK)
+
+#define TOTAL_BITS_SET \
+	(0 DT_FOREACH_STATUS_OKAY(CBI_FW_CONFIG_COMPAT, FIELDS_ALL_BITS_SET))
+
+BUILD_ASSERT(BIT_COUNT(TOTAL_BITS_SET) == TOTAL_FW_CONFIG_NODES_SIZE,
+	     "CBI FW Config has overlapping fields");
+
+/*
+ * Validation for each assigned field values.
+ * The value must fit within the parent's defined size.
+ */
+#define FW_VALUE_BUILD_ASSERT(inst)                                      \
+	BUILD_ASSERT(DT_PROP(inst, value) < (1 << FW_PARENT_SIZE(inst)), \
+		     "CBI FW Config value too big");
+
+DT_FOREACH_STATUS_OKAY(CBI_FW_CONFIG_VALUE_COMPAT, FW_VALUE_BUILD_ASSERT)
+
+/*
+ * Macro to initialise the fields to default value (if specified)
+ */
+#define CBI_FW_CONFIG_INIT_DEFAULT(id, fw_config)            \
+	do {                                                 \
+		if (DT_PROP(id, default)) {                  \
+			fw_config |= DT_PROP(id, value)      \
+				     << FW_PARENT_START(id); \
+		}                                            \
+	} while (0);
+/*
+ * Define bit fields based on the device tree entries. Example:
+ * cbi-fw-config {
+ *	compatible = "cros-ec,cbi-fw-config";
+ *
+ *	fan {
+ *		enum-name = "FW_CONFIG_FAN";
+ *		start = <0>;
+ *		size = <1>;
+ *		fan_present {
+ *			enum-name = "FW_FAN_PRESENT"
+ *			compatible = "cros-ec,cbi-fw-config-value";
+ *			value = <1>;
+ *		};
+ *	};
+ * };
+ *
+ * Creates
+ * switch (field_id) {
+ * case FW_CONFIG_FAN:
+ *	return (value >> 0) & 1;
+ *	...
+ * }
+ *
+ */
+
+/*
+ * The per-field case statement.
+ * Extract the field value using the start and size.
+ */
+#define FW_FIELD_CASE(id, cached, value)                         \
+	case CBI_FW_CONFIG_ENUM(id):                             \
+		*value = (cached >> FW_START(id)) & FW_MASK(id); \
+		break;
+
+/*
+ * Create a case for every child of this "cros-ec,cbi-fw-config" node.
+ */
+#define FW_FIELD_NODES(inst, cached, value) \
+	DT_FOREACH_CHILD_STATUS_OKAY_VARGS(inst, FW_FIELD_CASE, cached, value)
+
+uint32_t cached_fw_config;
+
+void cros_cbi_fw_config_init(void)
+{
+	if (cbi_get_fw_config(&cached_fw_config) != EC_SUCCESS) {
+		/*
+		 * Missing fw config will set the default or 0 for
+		 * every field.
+		 */
+		cached_fw_config = 0;
+		DT_FOREACH_STATUS_OKAY_VARGS(CBI_FW_CONFIG_VALUE_COMPAT,
+					     CBI_FW_CONFIG_INIT_DEFAULT,
+					     cached_fw_config)
+	}
+
+	LOG_INF("Read CBI FW Config : 0x%08X\n", cached_fw_config);
+}
+
+static int cros_cbi_fw_config_get_field(uint32_t cached_fw_config,
+					enum cbi_fw_config_field_id field_id,
+					uint32_t *value)
+{
+	switch (field_id) {
+		/*
+		 * Iterate through all the the "cros-ec,cbi-fw-config" nodes,
+		 * and create cases for all of their child nodes.
+		 */
+		DT_FOREACH_STATUS_OKAY_VARGS(CBI_FW_CONFIG_COMPAT,
+					     FW_FIELD_NODES, cached_fw_config,
+					     value)
+	default:
+		return -EINVAL;
+	}
+	return 0;
+}
+
+test_mockable int cros_cbi_get_fw_config(enum cbi_fw_config_field_id field_id,
+					 uint32_t *value)
+{
+	int rc;
+
+	rc = cros_cbi_fw_config_get_field(cached_fw_config, field_id, value);
+	if (rc)
+		LOG_ERR("CBI FW Config field not found: %d\n", field_id);
+	return rc;
+}
diff --git a/zephyr/shim/src/cbi/cros_cbi_ssfc.c b/zephyr/shim/src/cbi/cros_cbi_ssfc.c
new file mode 100644
index 0000000000..f20ca457f4
--- /dev/null
+++ b/zephyr/shim/src/cbi/cros_cbi_ssfc.c
@@ -0,0 +1,172 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(cros_cbi_ssfc, LOG_LEVEL_ERR);
+
+/* Actually, two "compatible" values are handle here - cros_ec_cbi_ssfc_value
+ * and cros_ec_cbi_ssfc. cros_ec_cbi_ssfc_value nodes are grandchildren of the
+ * cros_ec_cbi_ssfc node. cros_ec_cbi_ssfc_value is introduced to iterate over
+ * grandchildren of the cros_ec_cbi_ssfc (macro DT_FOREACH_CHILD can not be
+ * nested) and it can be pointed by a sensor dts to indicate alternative usage.
+ */
+#define DT_DRV_COMPAT cros_ec_cbi_ssfc_value
+
+BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(cros_ec_cbi_ssfc) < 2,
+	     "More than 1 CBI SSFS node");
+#define CBI_SSFC_NODE DT_INST(0, cros_ec_cbi_ssfc)
+
+#define CBI_SSFC_INIT_DEFAULT_ID(id, ssfc)                              \
+	do {                                                            \
+		if (DT_PROP(id, default)) {                             \
+			ssfc.CBI_SSFC_UNION_ENTRY_NAME(DT_PARENT(id)) = \
+				DT_PROP(id, value);                     \
+		}                                                       \
+	} while (0);
+
+#define CBI_SSFC_INIT_DEFAULT(inst, ssfc) \
+	CBI_SSFC_INIT_DEFAULT_ID(DT_DRV_INST(inst), ssfc)
+
+#define CBI_SSFC_VALUE_ARRAY_ID(id) \
+	[CBI_SSFC_VALUE_ID(id)] = DT_PROP(id, value),
+
+#define CBI_SSFC_VALUE_ARRAY(inst) CBI_SSFC_VALUE_ARRAY_ID(DT_DRV_INST(inst))
+
+#define CBI_SSFC_VALUE_BUILD_ASSERT(inst)                    \
+	BUILD_ASSERT(DT_INST_PROP(inst, value) <= UINT8_MAX, \
+		     "CBI SSFS value too big");
+
+#define CBI_SSFC_PARENT_VALUE_CASE_GENERATE(value_id, value_parent, value) \
+	case value_id:                                                     \
+		*value = value_parent;                                     \
+		break;
+
+#define CBI_SSFC_PARENT_VALUE_CASE_ID(id, cached_ssfc, value) \
+	CBI_SSFC_PARENT_VALUE_CASE_GENERATE(                  \
+		CBI_SSFC_VALUE_ID(id),                        \
+		cached_ssfc.CBI_SSFC_UNION_ENTRY_NAME(DT_PARENT(id)), value)
+
+#define CBI_SSFC_PARENT_VALUE_CASE(inst, cached_ssfc, value) \
+	CBI_SSFC_PARENT_VALUE_CASE_ID(DT_DRV_INST(inst), cached_ssfc, value)
+
+#define CBI_SSFC_UNION_ENTRY_NAME(id) DT_CAT(cbi_ssfc_, id)
+#define CBI_SSFC_UNION_ENTRY(id)               \
+	uint32_t CBI_SSFC_UNION_ENTRY_NAME(id) \
+		: DT_PROP(id, size);
+
+#define CBI_SSFC_PLUS_FIELD_SIZE(id) +DT_PROP(id, size)
+#define CBI_SSFC_FIELDS_SIZE                                                 \
+	(0 COND_CODE_1(                                                      \
+		DT_NODE_EXISTS(CBI_SSFC_NODE),                               \
+		(DT_FOREACH_CHILD(CBI_SSFC_NODE, CBI_SSFC_PLUS_FIELD_SIZE)), \
+		()))
+
+BUILD_ASSERT(CBI_SSFC_FIELDS_SIZE <= 32, "CBI SSFS is bigger than 32 bits");
+
+/*
+ * Define union bit fields based on the device tree entries. Example:
+ * cbi-ssfc {
+ *	compatible = "cros-ec,cbi-ssfc";
+ *
+ *	base_sensor {
+ *		enum-name = "BASE_SENSOR";
+ *		size = <3>;
+ *		bmi160 {
+ *			compatible = "cros-ec,cbi-ssfc-value";
+ *			status = "okay";
+ *			value = <1>;
+ *		};
+ *	};
+ *	lid_sensor {
+ *		enum-name = "LID_SENSOR";
+ *		size = <3>;
+ *		bma255 {
+ *			compatible = "cros-ec,cbi-ssfc-value";
+ *			status = "okay";
+ *			value = <1>;
+ *		};
+ *	};
+ *	lightbar {
+ *		enum-name = "LIGHTBAR";
+ *		size = <2>;
+ *		10_led {
+ *			compatible = "cros-ec,cbi-ssfc-value";
+ *			status = "okay";
+ *			value = <1>;
+ *		};
+ *	};
+ * };
+ * Should be converted into
+ * union cbi_ssfc {
+ *	struct {
+ *		uint32_t cbi_ssfc_DT_N_S_cbi_ssfc_S_base_sensor:3
+ *		uint32_t cbi_ssfc_DT_N_S_cbi_ssfc_S_lid_sensor:3
+ *		uint32_t cbi_ssfc_DT_N_S_cbi_ssfc_S_lightbar:2
+ *		uint32_t reserved : 24;
+ *	};
+ *	uint32_t raw_value;
+ * };
+ */
+union cbi_ssfc {
+	struct {
+#if DT_NODE_EXISTS(CBI_SSFC_NODE)
+		DT_FOREACH_CHILD(CBI_SSFC_NODE, CBI_SSFC_UNION_ENTRY)
+		uint32_t reserved : (32 - CBI_SSFC_FIELDS_SIZE);
+#endif
+	};
+	uint32_t raw_value;
+};
+
+BUILD_ASSERT(sizeof(union cbi_ssfc) == sizeof(uint32_t),
+	     "CBI SSFS structure exceeds 32 bits");
+
+DT_INST_FOREACH_STATUS_OKAY(CBI_SSFC_VALUE_BUILD_ASSERT)
+
+static const uint8_t ssfc_values[] = { DT_INST_FOREACH_STATUS_OKAY(
+	CBI_SSFC_VALUE_ARRAY) };
+
+static union cbi_ssfc cached_ssfc;
+
+void cros_cbi_ssfc_init(void)
+{
+	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS) {
+		DT_INST_FOREACH_STATUS_OKAY_VARGS(CBI_SSFC_INIT_DEFAULT,
+						  cached_ssfc)
+	}
+
+	LOG_INF("Read CBI SSFC : 0x%08X\n", cached_ssfc.raw_value);
+}
+
+static int cros_cbi_ssfc_get_parent_field_value(union cbi_ssfc cached_ssfc,
+						enum cbi_ssfc_value_id value_id,
+						uint32_t *value)
+{
+	switch (value_id) {
+		DT_INST_FOREACH_STATUS_OKAY_VARGS(CBI_SSFC_PARENT_VALUE_CASE,
+						  cached_ssfc, value)
+	default:
+		LOG_ERR("CBI SSFC parent field value not found: %d\n",
+			value_id);
+		return -EINVAL;
+	}
+	return 0;
+}
+
+bool cros_cbi_ssfc_check_match(enum cbi_ssfc_value_id value_id)
+{
+	int rc;
+	uint32_t value;
+
+	rc = cros_cbi_ssfc_get_parent_field_value(cached_ssfc, value_id,
+						  &value);
+	if (rc) {
+		return false;
+	}
+	return value == ssfc_values[value_id];
+}
diff --git a/zephyr/shim/src/charger.c b/zephyr/shim/src/charger.c
new file mode 100644
index 0000000000..9d6021ad7d
--- /dev/null
+++ b/zephyr/shim/src/charger.c
@@ -0,0 +1,61 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charger.h"
+#include "charger/chg_bq25710.h"
+#include "charger/chg_isl923x.h"
+#include "charger/chg_isl9241.h"
+#include "charger/chg_rt9490.h"
+#include "charger/chg_sm5803.h"
+#include "usbc/utils.h"
+
+#include <zephyr/devicetree.h>
+
+#define CHG_CHIP_ENTRY(usbc_id, chg_id, config_fn) \
+	[USBC_PORT_NEW(usbc_id)] = config_fn(chg_id)
+
+#define CHECK_COMPAT(compat, usbc_id, chg_id, config_fn) \
+	COND_CODE_1(DT_NODE_HAS_COMPAT(chg_id, compat),  \
+		    (CHG_CHIP_ENTRY(usbc_id, chg_id, config_fn)), ())
+
+#define CHG_CHIP_FIND(usbc_id, chg_id)                                         \
+	CHECK_COMPAT(BQ25710_CHG_COMPAT, usbc_id, chg_id, CHG_CONFIG_BQ25710)  \
+	CHECK_COMPAT(ISL923X_CHG_COMPAT, usbc_id, chg_id, CHG_CONFIG_ISL923X)  \
+	CHECK_COMPAT(ISL923X_EMUL_COMPAT, usbc_id, chg_id, CHG_CONFIG_ISL923X) \
+	CHECK_COMPAT(ISL9241_CHG_COMPAT, usbc_id, chg_id, CHG_CONFIG_ISL9241)  \
+	CHECK_COMPAT(RT9490_CHG_COMPAT, usbc_id, chg_id, CHG_CONFIG_RT9490)    \
+	CHECK_COMPAT(RT9490_EMUL_COMPAT, usbc_id, chg_id, CHG_CONFIG_RT9490)   \
+	CHECK_COMPAT(SM5803_CHG_COMPAT, usbc_id, chg_id, CHG_CONFIG_SM5803)
+
+#define CHG_CHIP(usbc_id)                           \
+	COND_CODE_1(DT_NODE_HAS_PROP(usbc_id, chg), \
+		    (CHG_CHIP_FIND(usbc_id, DT_PHANDLE(usbc_id, chg))), ())
+
+#define CHG_CHIP_ALT(usbc_id)                                               \
+	COND_CODE_1(DT_NODE_HAS_PROP(usbc_id, chg_alt),                     \
+		    (CHG_CHIP_FIND(usbc_id, DT_PHANDLE(usbc_id, chg_alt))), \
+		    ())
+
+#define MAYBE_CONST \
+	COND_CODE_1(CONFIG_PLATFORM_EC_CHARGER_RUNTIME_CONFIG, (), (const))
+
+/* Charger chips */
+MAYBE_CONST struct charger_config_t chg_chips[] = { DT_FOREACH_STATUS_OKAY(
+	named_usbc_port, CHG_CHIP) };
+
+/* Alternate options */
+const struct charger_config_t chg_chips_alt[] = { DT_FOREACH_STATUS_OKAY(
+	named_usbc_port, CHG_CHIP_ALT) };
+
+#ifdef CONFIG_PLATFORM_EC_CHARGER_SINGLE_CHIP
+BUILD_ASSERT(ARRAY_SIZE(chg_chips) == 1,
+	     "For the CHARGER_SINGLE_CHIP config, the number of defined charger "
+	     "chips must equal 1.");
+#else
+BUILD_ASSERT(
+	ARRAY_SIZE(chg_chips) == CONFIG_USB_PD_PORT_MAX_COUNT,
+	"For the OCPC config, the number of defined charger chips must equal "
+	"the number of USB-C ports.");
+#endif
diff --git a/zephyr/shim/src/chg_rt9490.c b/zephyr/shim/src/chg_rt9490.c
new file mode 100644
index 0000000000..4162e7255b
--- /dev/null
+++ b/zephyr/shim/src/chg_rt9490.c
@@ -0,0 +1,26 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define DT_DRV_COMPAT richtek_rt9490
+
+#include "driver/charger/rt9490.h"
+
+#include <zephyr/devicetree.h>
+
+#if DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT)
+
+BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
+	     "This driver doesn't support multiple rt9490 instance");
+
+#define RT9490_NODE DT_INST(0, DT_DRV_COMPAT)
+
+const struct rt9490_init_setting rt9490_setting = {
+	.eoc_current = DT_PROP(RT9490_NODE, eoc_current),
+	.mivr = DT_PROP(RT9490_NODE, mivr),
+	.boost_voltage = DT_PROP(RT9490_NODE, boost_voltage),
+	.boost_current = DT_PROP(RT9490_NODE, boost_current),
+};
+
+#endif /* DT_HAS_COMPAT_STATUS_OKAY */
diff --git a/zephyr/shim/src/chipset_api.c b/zephyr/shim/src/chipset_api.c
new file mode 100644
index 0000000000..859a6681b9
--- /dev/null
+++ b/zephyr/shim/src/chipset_api.c
@@ -0,0 +1,75 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Chipset interface APIs */
+
+#include "ap_power/ap_power_interface.h"
+#include "charge_state.h"
+#include "chipset_state_check.h"
+#include "common.h"
+#include "system.h"
+
+int chipset_in_state(int state_mask)
+{
+	return ap_power_in_state(state_mask);
+}
+
+int chipset_in_or_transitioning_to_state(int state_mask)
+{
+	return ap_power_in_or_transitioning_to_state(state_mask);
+}
+
+void chipset_exit_hard_off(void)
+{
+	ap_power_exit_hardoff();
+}
+
+void chipset_force_shutdown(enum chipset_shutdown_reason reason)
+{
+	ap_power_force_shutdown((enum ap_power_shutdown_reason)reason);
+}
+
+void chipset_reset(enum chipset_shutdown_reason reason)
+{
+	ap_power_reset((enum ap_power_shutdown_reason)reason);
+}
+
+/* TODO: b/214509787
+ * To be added later when this functionality is implemented in ap_pwrseq.
+ */
+void chipset_throttle_cpu(int throttle)
+{
+}
+
+void init_reset_log(void)
+{
+	ap_power_init_reset_log();
+}
+
+bool board_ap_power_is_startup_ok(void)
+{
+	/*
+	 * Try multiple times with some delay to allow chargers to become ready
+	 * if needed. 40 tries with 100ms delay is arbitrary, but follows all
+	 * existing systems.
+	 */
+	for (int tries = 0; tries < 40; tries++) {
+		/*
+		 * TODO(b/260909787) this logic should be handled by a single
+		 * function that works in all configurations. system_can_boot_ap
+		 * is a subset of charge_prevent_power_on, but works in all
+		 * configurations.
+		 */
+		bool power_ok = IS_ENABLED(CONFIG_CHARGER) &&
+						IS_ENABLED(CONFIG_BATTERY) ?
+					!charge_prevent_power_on(false) :
+					system_can_boot_ap();
+		if (power_ok)
+			return true;
+
+		msleep(100);
+	}
+	return false;
+}
diff --git a/zephyr/shim/src/chipset_state_check.h b/zephyr/shim/src/chipset_state_check.h
new file mode 100644
index 0000000000..c33a3f9553
--- /dev/null
+++ b/zephyr/shim/src/chipset_state_check.h
@@ -0,0 +1,20 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CHIPSET_STATE_CHECK_H__
+#define __CHIPSET_STATE_CHECK_H__
+
+#include "ap_power/ap_power_interface.h"
+#include "chipset.h"
+
+BUILD_ASSERT((int)AP_POWER_STATE_HARD_OFF == (int)CHIPSET_STATE_HARD_OFF);
+BUILD_ASSERT((int)AP_POWER_STATE_SOFT_OFF == (int)CHIPSET_STATE_SOFT_OFF);
+BUILD_ASSERT((int)AP_POWER_STATE_SUSPEND == (int)CHIPSET_STATE_SUSPEND);
+BUILD_ASSERT((int)AP_POWER_STATE_ON == (int)CHIPSET_STATE_ON);
+BUILD_ASSERT((int)AP_POWER_STATE_STANDBY == (int)CHIPSET_STATE_STANDBY);
+BUILD_ASSERT((int)AP_POWER_STATE_ANY_OFF == (int)CHIPSET_STATE_ANY_OFF);
+BUILD_ASSERT((int)AP_POWER_STATE_ANY_SUSPEND == (int)CHIPSET_STATE_ANY_SUSPEND);
+
+#endif /* __CHIPSET_STATE_CHECK_H__ */
diff --git a/zephyr/shim/src/console.c b/zephyr/shim/src/console.c
index 17364c4870..6df3511cd1 100644
--- a/zephyr/shim/src/console.c
+++ b/zephyr/shim/src/console.c
@@ -1,89 +1,497 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <kernel.h>
-#include <shell/shell.h>
+/*
+ * TODO(b/238433667): Include EC printf functions
+ * (crec_vsnprintf/crec_snprintf) until we switch to the standard
+ * vsnprintf/snprintf.
+ */
+#include "builtin/stdio.h"
+#include "console.h"
+#include "printf.h"
+#include "task.h"
+#include "uart.h"
+#include "usb_console.h"
+#include "zephyr_console_shim.h"
+
+#include <stdbool.h>
 #include <string.h>
-#include <sys/printk.h>
-#include <zephyr.h>
 
-#include "console.h"
+#include <zephyr/device.h>
+#include <zephyr/drivers/uart.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/shell/shell.h>
+#ifdef CONFIG_SHELL_BACKEND_DUMMY /* nocheck */
+#include <zephyr/shell/shell_dummy.h> /* nocheck */
+#endif
+#include <zephyr/shell/shell_uart.h>
+#include <zephyr/sys/printk.h>
+#include <zephyr/sys/ring_buffer.h>
+
+#if !defined(CONFIG_SHELL_BACKEND_SERIAL) && \
+	!defined(CONFIG_SHELL_BACKEND_DUMMY) /* nocheck */
+#error Must select either CONFIG_SHELL_BACKEND_SERIAL or \
+	CONFIG_SHELL_BACKEND_DUMMY /* nocheck */
+#endif
+#if defined(CONFIG_SHELL_BACKEND_SERIAL) && \
+	defined(CONFIG_SHELL_BACKEND_DUMMY) /* nocheck */
+#error Must select only one shell backend
+#endif
 
-int cputs(enum console_channel channel, const char *str)
+LOG_MODULE_REGISTER(shim_console, LOG_LEVEL_ERR);
+
+static const struct device *uart_shell_dev =
+	DEVICE_DT_GET(DT_CHOSEN(zephyr_shell_uart));
+static const struct shell *shell_zephyr;
+static struct k_poll_signal shell_uninit_signal;
+static struct k_poll_signal shell_init_signal;
+/*
+ * A flag is kept to indicate if the shell has been (or is about
+ * to be) stopped, so that output won't be sent via zephyr_fprintf()
+ * (which requires locking the shell).
+ */
+static bool shell_stopped;
+static bool rx_bypass_enabled;
+RING_BUF_DECLARE(rx_buffer, CONFIG_UART_RX_BUF_SIZE);
+
+#if defined(CONFIG_UART_INTERRUPT_DRIVEN)
+
+static void uart_rx_handle(const struct device *dev)
 {
-	return cprintf(channel, "%s\n", str);
+	static uint8_t scratch;
+	static uint8_t *data;
+	static uint32_t len, rd_len;
+
+	do {
+		/* Get some bytes on the ring buffer */
+		len = ring_buf_put_claim(&rx_buffer, &data, rx_buffer.size);
+		if (len > 0) {
+			/* Read from the FIFO up to `len` bytes */
+			rd_len = uart_fifo_read(dev, data, len);
+
+			/* Put `rd_len` bytes on the ring buffer */
+			ring_buf_put_finish(&rx_buffer, rd_len);
+		} else {
+			/*
+			 * There's no room on the ring buffer, throw away 1
+			 * byte.
+			 */
+			rd_len = uart_fifo_read(dev, &scratch, 1);
+		}
+	} while (rd_len != 0 && rd_len == len);
 }
 
-static const struct shell *current_shell;
+test_mockable_static void uart_callback(const struct device *dev,
+					void *user_data)
+{
+	uart_irq_update(dev);
+
+	if (uart_irq_rx_ready(dev))
+		uart_rx_handle(dev);
+}
+#endif
+
+static void shell_uninit_callback(const struct shell *shell, int res)
+{
+	if (!res) {
+#if defined(CONFIG_UART_INTERRUPT_DRIVEN)
+		/* Set the new callback */
+		uart_irq_callback_user_data_set(uart_shell_dev, uart_callback,
+						NULL);
+
+		/*
+		 * Disable TX interrupts. We don't actually use TX but for some
+		 * reason none of this works without this line.
+		 */
+		uart_irq_tx_disable(uart_shell_dev);
+
+		/* Enable RX interrupts */
+		uart_irq_rx_enable(uart_shell_dev);
+#endif
+	}
+
+	/* Notify the uninit signal that we finished */
+	k_poll_signal_raise(&shell_uninit_signal, res);
+}
 
-static void console_vprintf(enum console_channel channel, const char *format,
-			    va_list args)
+void bypass_cb(const struct shell *shell, uint8_t *data, size_t len)
 {
-	if (current_shell && channel == CC_COMMAND) {
-		shell_vfprintf(current_shell, SHELL_NORMAL, format, args);
-		return;
+	if (!ring_buf_put(&rx_buffer, data, len)) {
+		printk("Failed to write to uart ring buf\n");
 	}
+}
+
+void uart_shell_rx_bypass(bool enable)
+{
+	shell_set_bypass(shell_zephyr, enable ? bypass_cb : NULL);
+	rx_bypass_enabled = enable;
+}
+
+int uart_shell_stop(void)
+{
+	struct k_poll_event event = K_POLL_EVENT_INITIALIZER(
+		K_POLL_TYPE_SIGNAL, K_POLL_MODE_NOTIFY_ONLY,
+		&shell_uninit_signal);
 
 	/*
-	 * TODO(jrosenth): investigate using the logging subsystem
-	 * and generating modules for the channels instead of printk
+	 * Set the shell_stopped flag so that no output will
+	 * be sent to the uart via zephyr_fprintf after this point.
 	 */
-	vprintk(format, args);
+	shell_stopped = true;
+	/* Clear all pending input */
+	uart_clear_input();
+
+#if defined(CONFIG_UART_INTERRUPT_DRIVEN)
+	/* Disable RX and TX interrupts */
+	uart_irq_rx_disable(uart_shell_dev);
+	uart_irq_tx_disable(uart_shell_dev);
+#endif
+
+	/* Initialize the uninit signal */
+	k_poll_signal_init(&shell_uninit_signal);
+
+	/* Stop the shell */
+	shell_uninit(shell_zephyr, shell_uninit_callback);
+
+	/* Wait for the shell to be turned off, the signal will wake us */
+	k_poll(&event, 1, K_FOREVER);
+
+	/* Event was signaled, return the result */
+	return event.signal->result;
 }
 
-__attribute__((__format__(__printf__, 2, 3))) int
-cprintf(enum console_channel channel, const char *format, ...)
+static const struct shell_backend_config_flags shell_cfg_flags =
+	SHELL_DEFAULT_BACKEND_CONFIG_FLAGS;
+
+static void shell_init_from_work(struct k_work *work)
 {
-	va_list args;
+	bool log_backend = 1;
+	uint32_t level = CONFIG_LOG_MAX_LEVEL;
+	ARG_UNUSED(work);
+
+#ifdef CONFIG_SHELL_BACKEND_SERIAL
+	log_backend = CONFIG_SHELL_BACKEND_SERIAL_LOG_LEVEL > 0;
+	if (CONFIG_SHELL_BACKEND_SERIAL_LOG_LEVEL <= LOG_LEVEL_DBG)
+		level = CONFIG_SHELL_BACKEND_SERIAL_LOG_LEVEL;
+#endif
+
+	/* Initialize the shell and re-enable both RX and TX */
+	shell_init(shell_zephyr, uart_shell_dev, shell_cfg_flags, log_backend,
+		   level);
+
+#if defined(CONFIG_UART_INTERRUPT_DRIVEN)
+	uart_irq_rx_enable(uart_shell_dev);
+	uart_irq_tx_enable(uart_shell_dev);
+#endif
+
+	/* Notify the init signal that initialization is complete */
+	k_poll_signal_raise(&shell_init_signal, 0);
+}
+
+void uart_shell_start(void)
+{
+	static struct k_work shell_init_work;
+	struct k_poll_event event = K_POLL_EVENT_INITIALIZER(
+		K_POLL_TYPE_SIGNAL, K_POLL_MODE_NOTIFY_ONLY,
+		&shell_init_signal);
+
+#if defined(CONFIG_UART_INTERRUPT_DRIVEN)
+	/* Disable RX and TX interrupts */
+	uart_irq_rx_disable(uart_shell_dev);
+	uart_irq_tx_disable(uart_shell_dev);
+#endif
+
+	/* Initialize k_work to call shell init (this makes it thread safe) */
+	k_work_init(&shell_init_work, shell_init_from_work);
+
+	/* Initialize the init signal to make sure we're read to listen */
+	k_poll_signal_init(&shell_init_signal);
+
+	/* Submit the work to be run by the kernel */
+	k_work_submit(&shell_init_work);
+
+	/* Wait for initialization to be run, the signal will wake us */
+	k_poll(&event, 1, K_FOREVER);
+	shell_stopped = false;
+}
+
+#ifdef CONFIG_SHELL_HELP
+static void print_console_help(const char *name,
+			       const struct zephyr_console_command *command)
+{
+	if (command->help)
+		printk("%s\n", command->help);
+	if (command->argdesc)
+		printk("Usage: %s %s\n", name, command->argdesc);
+}
+#endif
+
+int zshim_run_ec_console_command(const struct zephyr_console_command *command,
+				 size_t argc, const char **argv)
+{
+	int ret;
+
+	/*
+	 * The Zephyr shell only displays the help string and not
+	 * the argument descriptor when passing "-h" or "--help".  Mimic the
+	 * cros-ec behavior by displaying both the user types "<command> help",
+	 */
+#ifdef CONFIG_SHELL_HELP
+	for (int i = 1; i < argc; i++) {
+		if (!command->help && !command->argdesc)
+			break;
+		if (!strcmp(argv[i], "help")) {
+			print_console_help(argv[0], command);
+			return 0;
+		}
+	}
+#endif
+
+	ret = command->handler(argc, argv);
+	if (ret == EC_SUCCESS)
+		return ret;
+
+	/* Print common parameter error conditions and help on error */
+	if (ret >= EC_ERROR_PARAM1 && ret < EC_ERROR_PARAM_COUNT)
+		printk("Parameter %d invalid\n", ret - EC_ERROR_PARAM1 + 1);
+	else if (ret == EC_ERROR_PARAM_COUNT)
+		printk("Wrong number of parameters\n");
+	else
+		printk("Command returned error: %d\n", ret);
+
+#ifdef CONFIG_SHELL_HELP
+	print_console_help(argv[0], command);
+#endif
+	return ret;
+}
+
+BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(ec_console) <= 1,
+	     "at most one ec-console compatible node may be present");
+
+#define EC_CONSOLE_NODE DT_COMPAT_GET_ANY_STATUS_OKAY(ec_console)
+#if DT_NODE_EXISTS(EC_CONSOLE_NODE)
+
+static const char *const disabled_channels[] =
+	DT_PROP(EC_CONSOLE_NODE, disabled);
+static const size_t disabled_channel_count =
+	DT_PROP_LEN(EC_CONSOLE_NODE, disabled);
+static int init_ec_console(void)
+{
+	for (size_t i = 0; i < disabled_channel_count; i++)
+		console_channel_disable(disabled_channels[i]);
 
-	va_start(args, format);
-	console_vprintf(channel, format, args);
-	va_end(args);
 	return 0;
 }
+SYS_INIT(init_ec_console, PRE_KERNEL_1, 50);
+#endif /* CONFIG_PLATFORM_EC_CONSOLE_CHANNEL */
 
-__attribute__((__format__(__printf__, 2, 3))) int
-cprints(enum console_channel channel, const char *format, ...)
+static int init_ec_shell(void)
 {
-	va_list args;
+#if defined(CONFIG_SHELL_BACKEND_SERIAL)
+	shell_zephyr = shell_backend_uart_get_ptr();
+#elif defined(CONFIG_SHELL_BACKEND_DUMMY) /* nocheck */
+	shell_zephyr = shell_backend_dummy_get_ptr(); /* nocheck */
+#else
+#error A shell backend must be enabled
+#endif
+	return 0;
+}
+SYS_INIT(init_ec_shell, PRE_KERNEL_1, 50);
 
-	cprintf(channel, "[%lld ", k_uptime_get());
-	va_start(args, format);
-	console_vprintf(channel, format, args);
-	va_end(args);
-	cprintf(channel, "]\n");
+#ifdef TEST_BUILD
+const struct shell *get_ec_shell(void)
+{
+	return shell_zephyr;
+}
+#endif
+
+k_tid_t get_shell_thread(void)
+{
+	if (shell_zephyr == NULL) {
+		return NULL;
+	}
+	return shell_zephyr->thread;
+}
+
+void uart_tx_start(void)
+{
+}
+
+int uart_tx_ready(void)
+{
+	return 1;
+}
+
+int uart_tx_char_raw(void *context, int c)
+{
+	uart_write_char(c);
 	return 0;
 }
 
-void cflush(void)
+void uart_write_char(char c)
+{
+	uart_poll_out(uart_shell_dev, c);
+
+	if (IS_ENABLED(CONFIG_PLATFORM_EC_HOSTCMD_CONSOLE) && !k_is_in_isr())
+		console_buf_notify_chars(&c, 1);
+}
+
+void uart_flush_output(void)
 {
+	uart_tx_flush();
+}
+
+void uart_tx_flush(void)
+{
+#if defined(CONFIG_UART_INTERRUPT_DRIVEN)
+	while (!uart_irq_tx_complete(uart_shell_dev))
+		;
+#endif
+}
+
+int uart_getc(void)
+{
+	uint8_t c;
+	int rv = -1;
+
 	/*
-	 * Do nothing.  Output is sent immediately without buffering
-	 * from a printk() in Zephyr.
+	 * Don't try to read from the uart when the console
+	 * owns it.
 	 */
+	if (!shell_stopped && !rx_bypass_enabled) {
+		LOG_ERR("Shell must be stopped or rx bypass enabled");
+		return -1;
+	}
+
+	if (IS_ENABLED(CONFIG_UART_INTERRUPT_DRIVEN) || rx_bypass_enabled) {
+		if (ring_buf_get(&rx_buffer, &c, 1)) {
+			rv = c;
+		}
+	} else {
+		rv = uart_poll_in(uart_shell_dev, &c);
+		if (!rv) {
+			rv = c;
+		}
+	}
+	return rv;
 }
 
-int zshim_run_ec_console_command(int (*handler)(int argc, char **argv),
-				 const struct shell *shell, size_t argc,
-				 char **argv, const char *help_str,
-				 const char *argdesc)
+void uart_clear_input(void)
 {
-	for (int i = 1; i < argc; i++) {
-		if (!help_str && !argdesc)
-			break;
-		if (!strcmp(argv[i], "-h")) {
-			if (help_str)
-				shell_fprintf(shell, SHELL_NORMAL, "%s\n",
-					      help_str);
-			if (argdesc)
-				shell_fprintf(shell, SHELL_NORMAL,
-					      "Usage: %s\n", argdesc);
-			return 0;
+#if defined(CONFIG_UART_INTERRUPT_DRIVEN)
+	/* Reset the input ring buffer */
+	ring_buf_reset(&rx_buffer);
+#endif
+}
+
+static void handle_sprintf_rv(int rv, size_t *len)
+{
+	if (rv < 0) {
+		LOG_ERR("Print buffer is too small");
+		*len = CONFIG_SHELL_PRINTF_BUFF_SIZE;
+	} else {
+		*len += rv;
+	}
+}
+
+static void zephyr_print(const char *buff, size_t size)
+{
+	/*
+	 * shell_* functions can not be used in ISRs so optionally use
+	 * printk instead.
+	 * If the shell is about to be (or is) stopped, use printk, since the
+	 * output may be stalled and the shell mutex held.
+	 * Also, console_buf_notify_chars uses a mutex, which may not be
+	 * locked in ISRs.
+	 */
+	bool in_isr = k_is_in_isr();
+
+	if (in_isr || shell_stopped ||
+	    shell_zephyr->ctx->state != SHELL_STATE_ACTIVE) {
+		if (IS_ENABLED(CONFIG_PLATFORM_EC_ISR_CONSOLE_OUTPUT) ||
+		    !in_isr) {
+			printk("!%s", buff);
 		}
+	} else {
+		shell_fprintf(shell_zephyr, SHELL_NORMAL, "%s", buff);
+		if (IS_ENABLED(CONFIG_PLATFORM_EC_HOSTCMD_CONSOLE))
+			console_buf_notify_chars(buff, size);
+		if (IS_ENABLED(CONFIG_PLATFORM_EC_CONSOLE_DEBUG))
+			printk("%s", buff);
 	}
+}
+
+#if defined(CONFIG_USB_CONSOLE) || defined(CONFIG_USB_CONSOLE_STREAM)
+BUILD_ASSERT(0, "USB console is not supported with Zephyr");
+#endif /* defined(CONFIG_USB_CONSOLE) || defined(CONFIG_USB_CONSOLE_STREAM) */
+
+int cputs(enum console_channel channel, const char *outstr)
+{
+	/* Filter out inactive channels */
+	if (console_channel_is_disabled(channel))
+		return EC_SUCCESS;
+
+	zephyr_print(outstr, strlen(outstr));
+
+	return 0;
+}
+
+int cprintf(enum console_channel channel, const char *format, ...)
+{
+	int rv;
+	va_list args;
+	size_t len = 0;
+	char buff[CONFIG_SHELL_PRINTF_BUFF_SIZE];
+
+	/* Filter out inactive channels */
+	if (console_channel_is_disabled(channel))
+		return EC_SUCCESS;
+
+	va_start(args, format);
+	rv = crec_vsnprintf(buff, CONFIG_SHELL_PRINTF_BUFF_SIZE, format, args);
+	va_end(args);
+	handle_sprintf_rv(rv, &len);
+
+	zephyr_print(buff, len);
+
+	return rv > 0 ? EC_SUCCESS : rv;
+}
+
+int cprints(enum console_channel channel, const char *format, ...)
+{
+	int rv;
+	va_list args;
+	char buff[CONFIG_SHELL_PRINTF_BUFF_SIZE];
+	size_t len = 0;
+
+	/* Filter out inactive channels */
+	if (console_channel_is_disabled(channel))
+		return EC_SUCCESS;
+
+	buff[0] = '[';
+	len = 1;
+
+	rv = snprintf_timestamp_now(buff + len, sizeof(buff) - len);
+	handle_sprintf_rv(rv, &len);
+
+	rv = crec_snprintf(buff + len, CONFIG_SHELL_PRINTF_BUFF_SIZE - len,
+			   " ");
+	handle_sprintf_rv(rv, &len);
+
+	va_start(args, format);
+	rv = crec_vsnprintf(buff + len, CONFIG_SHELL_PRINTF_BUFF_SIZE - len,
+			    format, args);
+	va_end(args);
+	handle_sprintf_rv(rv, &len);
+
+	rv = crec_snprintf(buff + len, CONFIG_SHELL_PRINTF_BUFF_SIZE - len,
+			   "]\n");
+	handle_sprintf_rv(rv, &len);
+
+	zephyr_print(buff, len);
 
-	current_shell = shell;
-	return handler(argc, argv);
+	return rv > 0 ? EC_SUCCESS : rv;
 }
diff --git a/zephyr/shim/src/console_buffer.c b/zephyr/shim/src/console_buffer.c
new file mode 100644
index 0000000000..f5e80b2d20
--- /dev/null
+++ b/zephyr/shim/src/console_buffer.c
@@ -0,0 +1,148 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "console.h"
+#include "ec_commands.h"
+
+#include <zephyr/kernel.h>
+
+static char console_buf[CONFIG_PLATFORM_EC_HOSTCMD_CONSOLE_BUF_SIZE];
+static uint32_t previous_snapshot_idx;
+static uint32_t current_snapshot_idx;
+static uint32_t read_next_idx;
+static uint32_t head_idx;
+static uint32_t tail_idx;
+
+static inline uint32_t next_idx(uint32_t cur_idx)
+{
+	return (cur_idx + 1) % ARRAY_SIZE(console_buf);
+}
+
+K_MUTEX_DEFINE(console_write_lock);
+
+size_t console_buf_notify_chars(const char *s, size_t len)
+{
+	/*
+	 * This is just notifying of console characters for debugging
+	 * output, so if we are unable to lock the mutex immediately,
+	 * then just drop the string.
+	 */
+	if (k_mutex_lock(&console_write_lock, K_NO_WAIT))
+		return 0;
+	/* We got the mutex. */
+	for (size_t i = 0; i < len; i++) {
+		/* Don't copy null byte into buffer */
+		if (!(*s)) {
+			s++;
+			continue;
+		}
+
+		uint32_t new_tail = next_idx(tail_idx);
+
+		/* Check if we are starting to overwrite our snapshot
+		 * heads
+		 */
+		if (new_tail == head_idx)
+			head_idx = next_idx(head_idx);
+		if (new_tail == previous_snapshot_idx)
+			previous_snapshot_idx = next_idx(previous_snapshot_idx);
+		if (new_tail == current_snapshot_idx)
+			current_snapshot_idx = next_idx(current_snapshot_idx);
+		if (new_tail == read_next_idx)
+			read_next_idx = next_idx(read_next_idx);
+
+		console_buf[tail_idx] = *s++;
+		tail_idx = new_tail;
+	}
+	k_mutex_unlock(&console_write_lock);
+	return len;
+}
+
+enum ec_status uart_console_read_buffer_init(void)
+{
+	if (k_mutex_lock(&console_write_lock, K_MSEC(100)))
+		/* Failed to acquire console buffer mutex */
+		return EC_RES_TIMEOUT;
+
+	/* For read next, start reading at the beginning of the buffer */
+	read_next_idx = head_idx;
+	/*
+	 * For read recent, start reading at the beginning of the previous
+	 * snapshot
+	 */
+	previous_snapshot_idx = current_snapshot_idx;
+	/*
+	 * Limit read command to characters available at the moment of creating
+	 * snapshot
+	 */
+	current_snapshot_idx = tail_idx;
+
+	k_mutex_unlock(&console_write_lock);
+
+	return EC_RES_SUCCESS;
+}
+
+int uart_console_read_buffer(uint8_t type, char *dest, uint16_t dest_size,
+			     uint16_t *write_count_out)
+{
+	uint32_t *head;
+	uint16_t write_count = 0;
+
+	switch (type) {
+	case CONSOLE_READ_NEXT:
+		/*
+		 * Start where we left or from the beginning of the buffer after
+		 * snapshot
+		 */
+		head = &read_next_idx;
+		break;
+	case CONSOLE_READ_RECENT:
+		/* Start from end of previous snapshot */
+		head = &previous_snapshot_idx;
+		break;
+	default:
+		return EC_RES_INVALID_PARAM;
+	}
+
+	/* We need to make sure we have room for at least the null byte */
+	if (dest_size == 0)
+		return EC_RES_INVALID_PARAM;
+
+	if (k_mutex_lock(&console_write_lock, K_MSEC(100)))
+		/* Failed to acquire console buffer mutex */
+		return EC_RES_TIMEOUT;
+
+	if (*head == current_snapshot_idx) {
+		/* No new data, return empty response */
+		k_mutex_unlock(&console_write_lock);
+		*write_count_out = 0;
+		return EC_RES_SUCCESS;
+	}
+
+	do {
+		if (write_count >= dest_size - 1)
+			/* Buffer is full, minus the space for a null byte */
+			break;
+
+		dest[write_count] = console_buf[*head];
+		write_count++;
+		*head = next_idx(*head);
+	} while (*head != current_snapshot_idx);
+
+	dest[write_count] = '\0';
+	write_count++;
+
+	*write_count_out = write_count;
+	k_mutex_unlock(&console_write_lock);
+
+	return EC_RES_SUCCESS;
+}
+
+/* ECOS uart buffer, putc is blocking instead. */
+int uart_buffer_full(void)
+{
+	return false;
+}
diff --git a/zephyr/shim/src/crc.c b/zephyr/shim/src/crc.c
new file mode 100644
index 0000000000..6c9475752b
--- /dev/null
+++ b/zephyr/shim/src/crc.c
@@ -0,0 +1,27 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "crc.h"
+#include "crc8.h"
+
+#include <zephyr/sys/crc.h>
+
+/* Polynomial representation for x^8 + x^2 + x + 1 is 0x07 */
+#define SMBUS_POLYNOMIAL 0x07
+
+inline uint8_t cros_crc8(const uint8_t *data, int len)
+{
+	return crc8(data, len, SMBUS_POLYNOMIAL, 0, false);
+}
+
+uint8_t cros_crc8_arg(const uint8_t *data, int len, uint8_t previous_crc)
+{
+	return crc8(data, len, SMBUS_POLYNOMIAL, previous_crc, false);
+}
+
+uint16_t cros_crc16(const uint8_t *data, int len, uint16_t previous_crc)
+{
+	return crc16_itu_t(previous_crc, data, len);
+}
diff --git a/zephyr/shim/src/espi.c b/zephyr/shim/src/espi.c
new file mode 100644
index 0000000000..90351040b7
--- /dev/null
+++ b/zephyr/shim/src/espi.c
@@ -0,0 +1,929 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "acpi.h"
+#include "chipset.h"
+#include "common.h"
+#include "espi.h"
+#include "hooks.h"
+#include "i8042_protocol.h"
+#include "keyboard_protocol.h"
+#include "keyboard_8042.h"
+#include "lpc.h"
+#include "port80.h"
+#include "power.h"
+#include "system_boot_time.h"
+#include "task.h"
+#include "timer.h"
+#include "zephyr_espi_shim.h"
+
+#include <stdint.h>
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/espi.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+
+#include <ap_power/ap_power.h>
+#include <ap_power/ap_power_espi.h>
+#include <ap_power/ap_power_events.h>
+#include <atomic.h>
+
+#define VWIRE_PULSE_TRIGGER_TIME \
+	CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US
+
+LOG_MODULE_REGISTER(espi_shim, CONFIG_ESPI_LOG_LEVEL);
+
+/*
+ * Some functions are compiled depending on combinations of
+ * CONFIG_PLATFORM_EC_POWERSEQ, CONFIG_AP_PWRSEQ and
+ * CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK.
+ *
+ * Tests are compiled without CONFIG_PLATFORM_EC_POWERSEQ and
+ * CONFIG_AP_PWRSEQ defined, but use the lpc functions.
+ *
+ * Legacy vwire power signal handling is required
+ * by CONFIG_PLATFORM_EC_POWERSEQ.
+ *
+ * CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK is used to handle
+ * the PLTRST# vwire signal separate to the legacy power signal handling.
+ *
+ * Where !defined(CONFIG_AP_PWRSEQ) is used, the code is required either
+ * by the tests, or by the legacy power signal handling.
+ */
+
+/* host command packet handler structure */
+static struct host_packet lpc_packet;
+/*
+ * For the eSPI host command, request & response use the same share memory.
+ * This is for input request temp buffer.
+ */
+static uint8_t params_copy[EC_LPC_HOST_PACKET_SIZE] __aligned(4);
+static bool init_done;
+
+/*
+ * A mapping of platform/ec signals to Zephyr virtual wires.
+ *
+ * This should be a macro which takes a parameter M, and does a
+ * functional application of M to 2-tuples of (platform/ec signal,
+ * zephyr vwire).
+ */
+#define VW_SIGNAL_TRANSLATION_LIST(M)                                      \
+	M(VW_SLP_S3_L, ESPI_VWIRE_SIGNAL_SLP_S3)                           \
+	M(VW_SLP_S4_L, ESPI_VWIRE_SIGNAL_SLP_S4)                           \
+	M(VW_SLP_S5_L, ESPI_VWIRE_SIGNAL_SLP_S5)                           \
+	M(VW_SUS_STAT_L, ESPI_VWIRE_SIGNAL_SUS_STAT)                       \
+	M(VW_PLTRST_L, ESPI_VWIRE_SIGNAL_PLTRST)                           \
+	M(VW_OOB_RST_WARN, ESPI_VWIRE_SIGNAL_OOB_RST_WARN)                 \
+	M(VW_OOB_RST_ACK, ESPI_VWIRE_SIGNAL_OOB_RST_ACK)                   \
+	M(VW_WAKE_L, ESPI_VWIRE_SIGNAL_WAKE)                               \
+	M(VW_PME_L, ESPI_VWIRE_SIGNAL_PME)                                 \
+	M(VW_ERROR_FATAL, ESPI_VWIRE_SIGNAL_ERR_FATAL)                     \
+	M(VW_ERROR_NON_FATAL, ESPI_VWIRE_SIGNAL_ERR_NON_FATAL)             \
+	M(VW_PERIPHERAL_BTLD_STATUS_DONE, ESPI_VWIRE_SIGNAL_SLV_BOOT_DONE) \
+	M(VW_SCI_L, ESPI_VWIRE_SIGNAL_SCI)                                 \
+	M(VW_SMI_L, ESPI_VWIRE_SIGNAL_SMI)                                 \
+	M(VW_HOST_RST_ACK, ESPI_VWIRE_SIGNAL_HOST_RST_ACK)                 \
+	M(VW_HOST_RST_WARN, ESPI_VWIRE_SIGNAL_HOST_RST_WARN)               \
+	M(VW_SUS_ACK, ESPI_VWIRE_SIGNAL_SUS_ACK)                           \
+	M(VW_SUS_WARN_L, ESPI_VWIRE_SIGNAL_SUS_WARN)                       \
+	M(VW_SUS_PWRDN_ACK_L, ESPI_VWIRE_SIGNAL_SUS_PWRDN_ACK)             \
+	M(VW_SLP_A_L, ESPI_VWIRE_SIGNAL_SLP_A)                             \
+	M(VW_SLP_LAN, ESPI_VWIRE_SIGNAL_SLP_LAN)                           \
+	M(VW_SLP_WLAN, ESPI_VWIRE_SIGNAL_SLP_WLAN)
+
+/*
+ * These two macros are intended to be used as as the M parameter to
+ * the list above, generating case statements returning the
+ * translation for the first parameter to the second, and the second
+ * to the first, respectively.
+ */
+#define CASE_CROS_TO_ZEPHYR(A, B) \
+	case A:                   \
+		return B;
+#define CASE_ZEPHYR_TO_CROS(A, B) CASE_CROS_TO_ZEPHYR(B, A)
+
+#if !defined(CONFIG_AP_PWRSEQ)
+/* Translate a platform/ec signal to a Zephyr signal */
+static enum espi_vwire_signal signal_to_zephyr_vwire(enum espi_vw_signal signal)
+{
+	switch (signal) {
+		VW_SIGNAL_TRANSLATION_LIST(CASE_CROS_TO_ZEPHYR);
+	default:
+		LOG_ERR("Invalid virtual wire signal (%d)", signal);
+		return -1;
+	}
+}
+
+#if defined(CONFIG_PLATFORM_EC_POWERSEQ)
+/* Translate a Zephyr vwire to a platform/ec signal */
+static enum espi_vw_signal zephyr_vwire_to_signal(enum espi_vwire_signal vwire)
+{
+	switch (vwire) {
+		VW_SIGNAL_TRANSLATION_LIST(CASE_ZEPHYR_TO_CROS);
+	default:
+		LOG_ERR("Invalid zephyr vwire (%d)", vwire);
+		return -1;
+	}
+}
+#endif /* defined(CONFIG_PLATFORM_EC_POWERSEQ) */
+
+/*
+ * Bit field for each signal which can have an interrupt enabled.
+ * Note the interrupt is always enabled, it just depends whether we
+ * route it to the power_signal_interrupt handler or not.
+ */
+static atomic_t signal_interrupt_enabled;
+
+/* To be used with VW_SIGNAL_TRASLATION_LIST */
+#define CASE_CROS_TO_BIT(A, _) CASE_CROS_TO_ZEPHYR(A, BIT(A - VW_SIGNAL_START))
+
+/* Convert from an EC signal to the corresponding interrupt enabled bit. */
+static uint32_t signal_to_interrupt_bit(enum espi_vw_signal signal)
+{
+	switch (signal) {
+		VW_SIGNAL_TRANSLATION_LIST(CASE_CROS_TO_BIT);
+	default:
+		return 0;
+	}
+}
+
+#endif /* !defined(CONFIG_AP_PWRSEQ) */
+
+#ifdef CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK
+/*
+ * Deferred handler for PLTRST processing.
+ */
+static void espi_chipset_reset(void)
+{
+	if (IS_ENABLED(CONFIG_AP_PWRSEQ)) {
+		ap_power_ev_send_callbacks(AP_POWER_RESET);
+	} else {
+		hook_notify(HOOK_CHIPSET_RESET);
+	}
+
+	update_ap_boot_time(ESPIRST);
+}
+DECLARE_DEFERRED(espi_chipset_reset);
+#endif /* CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK */
+
+/*
+ * Callback for vwire received.
+ * PLTRST (platform reset) is handled specially by
+ * invoking HOOK_CHIPSET_RESET.
+ */
+#if defined(CONFIG_PLATFORM_EC_POWERSEQ) || \
+	defined(CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK)
+static void espi_vwire_handler(const struct device *dev,
+			       struct espi_callback *cb,
+			       struct espi_event event)
+{
+#if defined(CONFIG_PLATFORM_EC_POWERSEQ)
+	int ec_signal = zephyr_vwire_to_signal(event.evt_details);
+
+	if (signal_interrupt_enabled & signal_to_interrupt_bit(ec_signal)) {
+		power_signal_interrupt(ec_signal);
+	}
+#endif
+#if defined(CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK)
+	/* If PLTRST# asserted (low) then send reset hook */
+	if (event.evt_details == ESPI_VWIRE_SIGNAL_PLTRST &&
+	    event.evt_data == 0) {
+		hook_call_deferred(&espi_chipset_reset_data, MSEC);
+		update_ap_boot_time(PLTRST_LOW);
+#ifdef CONFIG_BOARD_AZALEA
+	if (IS_ENABLED(CONFIG_HAS_TASK_KEYPROTO))
+		i8042_pause_to_host_queue(true);
+#endif
+	} else if (event.evt_details == ESPI_VWIRE_SIGNAL_PLTRST &&
+		   event.evt_data == 1) {
+		update_ap_boot_time(PLTRST_HIGH);
+#ifdef CONFIG_BOARD_AZALEA
+	if (IS_ENABLED(CONFIG_HAS_TASK_KEYPROTO))
+		i8042_pause_to_host_queue(false);
+#endif
+	}
+#endif
+}
+#endif
+
+#define espi_dev DEVICE_DT_GET(DT_CHOSEN(cros_ec_espi))
+
+#if !defined(CONFIG_AP_PWRSEQ)
+
+int espi_vw_set_wire(enum espi_vw_signal signal, uint8_t level)
+{
+	int ret = espi_send_vwire(espi_dev, signal_to_zephyr_vwire(signal),
+				  level);
+
+	if (ret != 0)
+		LOG_ERR("Encountered error sending virtual wire signal");
+
+	return ret;
+}
+
+int espi_vw_get_wire(enum espi_vw_signal signal)
+{
+	uint8_t level;
+
+	if (espi_receive_vwire(espi_dev, signal_to_zephyr_vwire(signal),
+			       &level) < 0) {
+		LOG_ERR("Encountered error receiving virtual wire signal");
+		return 0;
+	}
+
+	return level;
+}
+
+int espi_vw_enable_wire_int(enum espi_vw_signal signal)
+{
+	atomic_or(&signal_interrupt_enabled, signal_to_interrupt_bit(signal));
+	return 0;
+}
+
+int espi_vw_disable_wire_int(enum espi_vw_signal signal)
+{
+	atomic_and(&signal_interrupt_enabled, ~signal_to_interrupt_bit(signal));
+	return 0;
+}
+
+#endif /* !defined(CONFIG_AP_PWRSEQ) */
+
+uint8_t *lpc_get_memmap_range(void)
+{
+	uint32_t lpc_memmap = 0;
+	int result = espi_read_lpc_request(espi_dev, EACPI_GET_SHARED_MEMORY,
+					   &lpc_memmap);
+
+	if (result != EC_SUCCESS)
+		LOG_ERR("Get lpc_memmap failed (%d)!\n", result);
+
+	return (uint8_t *)lpc_memmap;
+}
+
+/**
+ * Update the level-sensitive wake signal to the AP.
+ *
+ * @param wake_events	Currently asserted wake events
+ */
+static void lpc_update_wake(host_event_t wake_events)
+{
+
+#ifndef CONFIG_PLATFORM_EC_UNIMPLEMENTED_GPIO
+	/*
+	 * Mask off power button event, since the AP gets that through a
+	 * separate dedicated GPIO.
+	 */
+	wake_events &= ~EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON);
+
+	/* Signal is asserted low when wake events is non-zero */
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_pch_wake_odl),
+			!wake_events);
+#endif
+}
+
+#if !defined(CONFIG_AP_PWRSEQ)
+
+static void lpc_generate_smi(void)
+{
+	/* Enforce signal-high for long enough to debounce high */
+	espi_vw_set_wire(VW_SMI_L, 1);
+	udelay(VWIRE_PULSE_TRIGGER_TIME);
+	espi_vw_set_wire(VW_SMI_L, 0);
+	udelay(VWIRE_PULSE_TRIGGER_TIME);
+	espi_vw_set_wire(VW_SMI_L, 1);
+}
+
+static void lpc_generate_sci(void)
+{
+#ifndef CONFIG_PLATFORM_EC_SCI_GPIO
+	/* Enforce signal-high for long enough to debounce high */
+	espi_vw_set_wire(VW_SCI_L, 1);
+	udelay(VWIRE_PULSE_TRIGGER_TIME);
+	espi_vw_set_wire(VW_SCI_L, 0);
+	udelay(VWIRE_PULSE_TRIGGER_TIME);
+	espi_vw_set_wire(VW_SCI_L, 1);
+#else
+	/* Enforce signal-high for long enough to debounce high */
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_sci_l), 1);
+	udelay(65);
+	/* Generate a falling edge */
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_sci_l), 0);
+	udelay(65);
+	/* Set signal high, now that we've generated the edge */
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_sci_l), 1);
+#endif
+}
+
+#else
+
+/*
+ * Use Zephyr API.
+ */
+static void lpc_generate_signal(enum espi_vwire_signal signal)
+{
+	/* Enforce signal-high for long enough to debounce high */
+	espi_send_vwire(espi_dev, signal, 1);
+	udelay(VWIRE_PULSE_TRIGGER_TIME);
+	espi_send_vwire(espi_dev, signal, 0);
+	udelay(VWIRE_PULSE_TRIGGER_TIME);
+	espi_send_vwire(espi_dev, signal, 1);
+}
+
+static void lpc_generate_sci(void)
+{
+	lpc_generate_signal(ESPI_VWIRE_SIGNAL_SCI);
+}
+
+static void lpc_generate_smi(void)
+{
+	lpc_generate_signal(ESPI_VWIRE_SIGNAL_SMI);
+}
+
+#endif /* !defined(CONFIG_AP_PWRSEQ) */
+
+void lpc_update_host_event_status(void)
+{
+	uint32_t enable;
+	uint32_t status;
+	int need_sci = 0;
+	int need_smi = 0;
+	int rv;
+
+	if (!init_done)
+		return;
+
+	/* Disable PMC1 interrupt while updating status register */
+	enable = 0;
+	rv = espi_write_lpc_request(espi_dev, ECUSTOM_HOST_SUBS_INTERRUPT_EN,
+				    &enable);
+	if (rv) {
+		LOG_ERR("ESPI write failed: "
+			"ECUSTOM_HOST_SUBS_INTERRUPT_EN = %d",
+			rv);
+		return;
+	}
+
+	rv = espi_read_lpc_request(espi_dev, EACPI_READ_STS, &status);
+	if (rv) {
+		LOG_ERR("ESPI read failed: EACPI_READ_STS = %d", rv);
+	} else {
+		if (lpc_get_host_events_by_type(LPC_HOST_EVENT_SMI)) {
+			/* Only generate SMI for first event */
+			if (!(status & EC_LPC_STATUS_SMI_PENDING))
+				need_smi = 1;
+
+			status |= EC_LPC_STATUS_SMI_PENDING;
+			rv = espi_write_lpc_request(espi_dev, EACPI_WRITE_STS,
+						    &status);
+		} else {
+			status &= ~EC_LPC_STATUS_SMI_PENDING;
+			rv = espi_write_lpc_request(espi_dev, EACPI_WRITE_STS,
+						    &status);
+		}
+		if (rv) {
+			LOG_ERR("ESPI write failed: EACPI_WRITE_STS = %d", rv);
+		}
+	}
+
+	rv = espi_read_lpc_request(espi_dev, EACPI_READ_STS, &status);
+	if (rv) {
+		LOG_ERR("ESPI read failed: EACPI_READ_STS = %d", rv);
+	} else {
+		if (lpc_get_host_events_by_type(LPC_HOST_EVENT_SCI)) {
+			/* Generate SCI for every event */
+			need_sci = 1;
+
+			status |= EC_LPC_STATUS_SCI_PENDING;
+			rv = espi_write_lpc_request(espi_dev, EACPI_WRITE_STS,
+						    &status);
+		} else {
+			status &= ~EC_LPC_STATUS_SCI_PENDING;
+			rv = espi_write_lpc_request(espi_dev, EACPI_WRITE_STS,
+						    &status);
+		}
+		if (rv) {
+			LOG_ERR("ESPI write failed: EACPI_WRITE_STS = %d", rv);
+		}
+	}
+
+	*(host_event_t *)host_get_memmap(EC_MEMMAP_HOST_EVENTS) =
+		lpc_get_host_events();
+
+	enable = 1;
+	rv = espi_write_lpc_request(espi_dev, ECUSTOM_HOST_SUBS_INTERRUPT_EN,
+				    &enable);
+	if (rv) {
+		LOG_ERR("ESPI write failed: "
+			"ECUSTOM_HOST_SUBS_INTERRUPT_EN = %d",
+			rv);
+	}
+
+	/* Process the wake events. */
+	lpc_update_wake(lpc_get_host_events_by_type(LPC_HOST_EVENT_WAKE));
+
+	/* Send pulse on SMI signal if needed */
+	if (need_smi)
+		lpc_generate_smi();
+
+	/* ACPI 5.0-12.6.1: Generate SCI for SCI_EVT=1. */
+	if (need_sci)
+		lpc_generate_sci();
+}
+
+static void lpc_host_command_init(void)
+{
+	/* We support LPC args and version 3 protocol */
+	*(lpc_get_memmap_range() + EC_MEMMAP_HOST_CMD_FLAGS) =
+		EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED |
+		EC_HOST_CMD_FLAG_VERSION_3;
+
+	/* Sufficiently initialized */
+	init_done = 1;
+
+	lpc_update_host_event_status();
+}
+
+DECLARE_HOOK(HOOK_INIT, lpc_host_command_init, HOOK_PRIO_INIT_LPC);
+
+static void handle_acpi_write(uint32_t data)
+{
+	uint8_t value, result;
+	uint8_t is_cmd = is_acpi_command(data);
+	uint32_t status;
+	int rv;
+
+	value = get_acpi_value(data);
+
+	/* Handle whatever this was. */
+	if (acpi_ap_to_ec(is_cmd, value, &result)) {
+		data = result;
+		rv = espi_write_lpc_request(espi_dev, EACPI_WRITE_CHAR, &data);
+		if (rv) {
+			LOG_ERR("ESPI write failed: EACPI_WRITE_CHAR = %d", rv);
+		}
+	}
+
+	/* Clear processing flag */
+	rv = espi_read_lpc_request(espi_dev, EACPI_READ_STS, &status);
+	if (rv) {
+		LOG_ERR("ESPI read failed: EACPI_READ_STS = %d", rv);
+	} else {
+		status &= ~EC_LPC_STATUS_PROCESSING;
+		rv = espi_write_lpc_request(espi_dev, EACPI_WRITE_STS, &status);
+		if (rv) {
+			LOG_ERR("ESPI write failed: EACPI_WRITE_STS = %d", rv);
+		}
+	}
+
+	/*
+	 * ACPI 5.0-12.6.1: Generate SCI for Input Buffer Empty / Output Buffer
+	 * Full condition on the kernel channel.
+	 */
+	lpc_generate_sci();
+}
+
+static void lpc_send_response_packet(struct host_packet *pkt)
+{
+	uint32_t data;
+	int rv;
+
+	/* TODO(b/176523211): check whether add EC_RES_IN_PROGRESS handle */
+
+	/* Write result to the data byte.  This sets the TOH status bit. */
+	data = pkt->driver_result;
+	rv = espi_write_lpc_request(espi_dev, ECUSTOM_HOST_CMD_SEND_RESULT,
+				    &data);
+	if (rv) {
+		LOG_ERR("ESPI write failed: ECUSTOM_HOST_CMD_SEND_RESULT = %d",
+			rv);
+	}
+}
+
+static void handle_host_write(uint32_t data)
+{
+	uint32_t shm_mem_host_cmd;
+	int rv;
+
+	if (EC_COMMAND_PROTOCOL_3 != (data & 0xff)) {
+		LOG_ERR("Don't support this version of the host command");
+		/* TODO:(b/175217186): error response for other versions */
+		return;
+	}
+
+	rv = espi_read_lpc_request(espi_dev, ECUSTOM_HOST_CMD_GET_PARAM_MEMORY,
+				   &shm_mem_host_cmd);
+	if (rv) {
+		LOG_ERR("ESPI read failed: EACPI_READ_STS = %d", rv);
+		return;
+	}
+	lpc_packet.send_response = lpc_send_response_packet;
+
+	lpc_packet.request = (const void *)shm_mem_host_cmd;
+	lpc_packet.request_temp = params_copy;
+	lpc_packet.request_max = sizeof(params_copy);
+	/* Don't know the request size so pass in the entire buffer */
+	lpc_packet.request_size = EC_LPC_HOST_PACKET_SIZE;
+
+	lpc_packet.response = (void *)shm_mem_host_cmd;
+	lpc_packet.response_max = EC_LPC_HOST_PACKET_SIZE;
+	lpc_packet.response_size = 0;
+
+	lpc_packet.driver_result = EC_RES_SUCCESS;
+
+	host_packet_receive(&lpc_packet);
+	return;
+}
+
+void lpc_set_acpi_status_mask(uint8_t mask)
+{
+	uint32_t status;
+	int rv;
+
+	rv = espi_read_lpc_request(espi_dev, EACPI_READ_STS, &status);
+	if (rv) {
+		LOG_ERR("ESPI read failed: EACPI_READ_STS = %d", rv);
+		return;
+	}
+	status |= mask;
+	rv = espi_write_lpc_request(espi_dev, EACPI_WRITE_STS, &status);
+	if (rv) {
+		LOG_ERR("ESPI write failed: EACPI_WRITE_STS = %d", rv);
+	}
+}
+
+void lpc_clear_acpi_status_mask(uint8_t mask)
+{
+	uint32_t status;
+	int rv;
+
+	rv = espi_read_lpc_request(espi_dev, EACPI_READ_STS, &status);
+	if (rv) {
+		LOG_ERR("ESPI read failed: EACPI_READ_STS = %d", rv);
+		return;
+	}
+	status &= ~mask;
+	rv = espi_write_lpc_request(espi_dev, EACPI_WRITE_STS, &status);
+	if (rv) {
+		LOG_ERR("ESPI write failed: EACPI_WRITE_STS = %d", rv);
+	}
+}
+
+/* Get protocol information */
+static enum ec_status lpc_get_protocol_info(struct host_cmd_handler_args *args)
+{
+	struct ec_response_get_protocol_info *r = args->response;
+
+	memset(r, 0, sizeof(*r));
+	r->protocol_versions = BIT(3);
+	r->max_request_packet_size = EC_LPC_HOST_PACKET_SIZE;
+	r->max_response_packet_size = EC_LPC_HOST_PACKET_SIZE;
+	r->flags = 0;
+
+	args->response_size = sizeof(*r);
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, lpc_get_protocol_info,
+		     EC_VER_MASK(0));
+
+/*
+ * This function is needed only for the obsolete platform which uses the GPIO
+ * for KBC's IRQ.
+ */
+void lpc_keyboard_resume_irq(void)
+{
+}
+
+void lpc_keyboard_clear_buffer(void)
+{
+	int rv;
+	/* Clear OBF flag in host STATUS and HIKMST regs */
+	rv = espi_write_lpc_request(espi_dev, E8042_CLEAR_OBF, 0);
+	if (rv) {
+		LOG_ERR("ESPI write failed: E8042_CLEAR_OBF = %d", rv);
+	}
+}
+
+int lpc_keyboard_has_char(void)
+{
+	uint32_t status;
+	int rv;
+
+	/* if OBF bit is '1', that mean still have a data in DBBOUT */
+	rv = espi_read_lpc_request(espi_dev, E8042_OBF_HAS_CHAR, &status);
+	if (rv) {
+		LOG_ERR("ESPI read failed: E8042_OBF_HAS_CHAR = %d", rv);
+		return 0;
+	}
+	return status;
+}
+
+test_mockable void lpc_keyboard_put_char(uint8_t chr, int send_irq)
+{
+	uint32_t kb_char = chr;
+	int rv;
+
+	rv = espi_write_lpc_request(espi_dev, E8042_WRITE_KB_CHAR, &kb_char);
+	if (rv) {
+		LOG_ERR("ESPI write failed: E8042_WRITE_KB_CHAR = %d", rv);
+		return;
+	}
+	LOG_INF("KB put %02x", kb_char);
+}
+
+/* Put an aux char to host buffer by HIMDO and assert status bit 5. */
+void lpc_aux_put_char(uint8_t chr, int send_irq)
+{
+	uint32_t kb_char = chr;
+	uint32_t status = I8042_AUX_DATA;
+	int rv;
+
+	rv = espi_write_lpc_request(espi_dev, E8042_SET_FLAG, &status);
+	if (rv) {
+		LOG_ERR("ESPI write failed: E8042_SET_FLAG = %d", rv);
+	}
+	rv = espi_write_lpc_request(espi_dev, E8042_WRITE_KB_CHAR, &kb_char);
+	if (rv) {
+		LOG_ERR("ESPI write failed: E8042_WRITE_KB_CHAR = %d", rv);
+	}
+	LOG_INF("AUX put %02x", kb_char);
+}
+
+#ifdef CONFIG_THIRD_PARTY_CUSTOMIZED_DESIGN
+
+void lpc_kbc_ibf_clear(void)
+{
+	int rv;
+	int data;
+
+	rv = espi_read_lpc_request(espi_dev, E8042_CLEAR_IBF, &data);
+	if (rv) {
+		LOG_ERR("ESPI read failed: E8042_CLEAR_IBF = %d", rv);
+		return;
+	}
+}
+
+/*
+ * this can delay EC release irq and clear IBF
+ * it will let host not send data too fast, make EC
+ * have time to process 8042 data and also not lose data
+ * after delay finish read HIKMDI clear IBF data and release 8042 irq
+ */
+static void lpc_kbc_process(void)
+{
+	int rv;
+
+	rv = espi_write_lpc_request(espi_dev, E8042_RESUME_IRQ, 0);
+	if (rv) {
+		LOG_ERR("ESPI write failed: E8042_RESUME_IRQ = %d", rv);
+	}
+}
+DECLARE_DEFERRED(lpc_kbc_process);
+
+static void kbc_ibf_obe_handler(uint32_t data)
+{
+#ifdef HAS_TASK_KEYPROTO
+	uint8_t is_ibf = is_8042_ibf(data);
+	uint32_t status = I8042_AUX_DATA;
+	int rv;
+
+	if (is_ibf == HOST_KBC_EVT_IBF) {
+		if (keyboard_host_write_avaliable() == 0) {
+			LOG_ERR("kbc buffer full");
+			/* Pause 8042 irq let KB task process data */
+			rv = espi_write_lpc_request(espi_dev, E8042_PAUSE_IRQ, 0);
+			if (rv) {
+				LOG_ERR("ESPI write failed: E8042_PAUSE_IRQ = %d", rv);
+			}
+			hook_call_deferred(&lpc_kbc_process_data, MSEC);
+		} else {
+			/* put data to queue and trigger 8042 task*/
+			keyboard_host_write(get_8042_data(data), get_8042_type(data));
+		}
+	} else if (IS_ENABLED(CONFIG_8042_AUX)) {
+		rv = espi_write_lpc_request(espi_dev, E8042_CLEAR_FLAG,
+					    &status);
+		if (rv) {
+			LOG_ERR("ESPI write failed: E8042_CLEAR_FLAG = %d", rv);
+		}
+	}
+	task_wake(TASK_ID_KEYPROTO);
+#endif
+}
+#else
+static void kbc_ibf_obe_handler(uint32_t data)
+{
+#ifdef HAS_TASK_KEYPROTO
+	uint8_t is_ibf = is_8042_ibf(data);
+	uint32_t status = I8042_AUX_DATA;
+	int rv;
+
+	if (is_ibf) {
+		keyboard_host_write(get_8042_data(data), get_8042_type(data));
+	} else if (IS_ENABLED(CONFIG_8042_AUX)) {
+		rv = espi_write_lpc_request(espi_dev, E8042_CLEAR_FLAG,
+					    &status);
+		if (rv) {
+			LOG_ERR("ESPI write failed: E8042_CLEAR_FLAG = %d", rv);
+		}
+	}
+	task_wake(TASK_ID_KEYPROTO);
+#endif
+}
+#endif
+
+int lpc_keyboard_input_pending(void)
+{
+	uint32_t status;
+	int rv;
+
+	/* if IBF bit is '1', that mean still have a data in DBBIN */
+	rv = espi_read_lpc_request(espi_dev, E8042_IBF_HAS_CHAR, &status);
+	if (rv) {
+		LOG_ERR("ESPI read failed: E8042_IBF_HAS_CHAR = %d", rv);
+		return 0;
+	}
+	return status;
+}
+
+static void espi_peripheral_handler(const struct device *dev,
+				    struct espi_callback *cb,
+				    struct espi_event event)
+{
+	uint16_t event_type = event.evt_details;
+
+	if (IS_ENABLED(CONFIG_PLATFORM_EC_PORT80) &&
+	    event_type == ESPI_PERIPHERAL_DEBUG_PORT80) {
+		port_80_write(event.evt_data);
+	}
+
+	if (IS_ENABLED(CONFIG_PLATFORM_EC_ACPI) &&
+	    event_type == ESPI_PERIPHERAL_HOST_IO) {
+		handle_acpi_write(event.evt_data);
+	}
+
+	if (IS_ENABLED(CONFIG_PLATFORM_EC_HOSTCMD) &&
+	    event_type == ESPI_PERIPHERAL_EC_HOST_CMD) {
+		handle_host_write(event.evt_data);
+	}
+
+	if (IS_ENABLED(CONFIG_ESPI_PERIPHERAL_8042_KBC) &&
+	    IS_ENABLED(HAS_TASK_KEYPROTO) &&
+	    event_type == ESPI_PERIPHERAL_8042_KBC) {
+		kbc_ibf_obe_handler(event.evt_data);
+	}
+}
+
+#if defined(CONFIG_PLATFORM_EC_CUSTOMIZED_DESIGN)
+/* Workaround for ADM fw18 known issue */
+static int espi_channel_vr_ready;
+int get_espi_virtual_wire_channel_status(void)
+{
+	return espi_channel_vr_ready;
+}
+
+void clear_espi_virtual_wire_channel_status(void)
+{
+	espi_channel_vr_ready = 0;
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, clear_espi_virtual_wire_channel_status, HOOK_PRIO_DEFAULT);
+
+static void custom_espi_channel_ready_handler(const struct device *dev,
+				    struct espi_callback *cb,
+				    struct espi_event event)
+{
+	if (event.evt_type == ESPI_BUS_EVENT_CHANNEL_READY) {
+		switch (event.evt_details) {
+		case ESPI_CHANNEL_VWIRE:
+			espi_channel_vr_ready = 1;
+			break;
+		default:
+		}
+	}
+}
+#endif
+
+static int zephyr_shim_setup_espi(void)
+{
+	uint32_t enable = 1;
+	static const struct {
+		espi_callback_handler_t handler;
+		enum espi_bus_event event_type;
+	} callbacks[] = {
+#if defined(CONFIG_PLATFORM_EC_POWERSEQ) || \
+	defined(CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK)
+		{
+			.handler = espi_vwire_handler,
+			.event_type = ESPI_BUS_EVENT_VWIRE_RECEIVED,
+		},
+#endif
+		{
+			.handler = espi_peripheral_handler,
+			.event_type = ESPI_BUS_PERIPHERAL_NOTIFICATION,
+		},
+#if defined(CONFIG_AP_PWRSEQ) && DT_HAS_COMPAT_STATUS_OKAY(intel_ap_pwrseq_vw)
+		{
+			.handler = power_signal_espi_cb,
+			.event_type = POWER_SIGNAL_ESPI_BUS_EVENTS,
+		},
+#endif
+#if defined(CONFIG_PLATFORM_EC_CUSTOMIZED_DESIGN)
+		{
+			.handler = custom_espi_channel_ready_handler,
+			.event_type = ESPI_BUS_EVENT_CHANNEL_READY,
+		},
+#endif
+	};
+	static struct espi_callback cb[ARRAY_SIZE(callbacks)];
+
+	struct espi_cfg cfg = {
+		.io_caps = ESPI_IO_MODE_QUAD_LINES,
+		.channel_caps = ESPI_CHANNEL_VWIRE | ESPI_CHANNEL_PERIPHERAL |
+				ESPI_CHANNEL_OOB,
+		.max_freq = 50,
+	};
+
+	if (!device_is_ready(espi_dev))
+		k_oops();
+
+	/* Setup callbacks */
+	for (size_t i = 0; i < ARRAY_SIZE(callbacks); i++) {
+		espi_init_callback(&cb[i], callbacks[i].handler,
+				   callbacks[i].event_type);
+		espi_add_callback(espi_dev, &cb[i]);
+	}
+
+	/* Configure eSPI after callbacks are registered */
+	if (espi_config(espi_dev, &cfg)) {
+		LOG_ERR("Failed to configure eSPI device");
+		return -1;
+	}
+
+	/* Enable host interface interrupts */
+	espi_write_lpc_request(espi_dev, ECUSTOM_HOST_SUBS_INTERRUPT_EN,
+			       &enable);
+#ifdef CONFIG_BOARD_AZALEA
+	if (IS_ENABLED(CONFIG_HAS_TASK_KEYPROTO))
+		i8042_pause_to_host_queue(true);
+#endif
+	return 0;
+}
+
+/* Must be before zephyr_shim_setup_hooks. */
+SYS_INIT(zephyr_shim_setup_espi, APPLICATION, 0);
+
+bool is_acpi_command(uint32_t data)
+{
+	struct espi_evt_data_acpi *acpi = (struct espi_evt_data_acpi *)&data;
+
+	return acpi->type;
+}
+
+uint32_t get_acpi_value(uint32_t data)
+{
+	struct espi_evt_data_acpi *acpi = (struct espi_evt_data_acpi *)&data;
+
+	return acpi->data;
+}
+
+bool is_8042_ibf(uint32_t data)
+{
+	struct espi_evt_data_kbc *kbc = (struct espi_evt_data_kbc *)&data;
+
+	return kbc->evt & HOST_KBC_EVT_IBF;
+}
+
+bool is_8042_obe(uint32_t data)
+{
+	struct espi_evt_data_kbc *kbc = (struct espi_evt_data_kbc *)&data;
+
+	return kbc->evt & HOST_KBC_EVT_OBE;
+}
+
+uint32_t get_8042_type(uint32_t data)
+{
+	struct espi_evt_data_kbc *kbc = (struct espi_evt_data_kbc *)&data;
+
+	return kbc->type;
+}
+
+uint32_t get_8042_data(uint32_t data)
+{
+	struct espi_evt_data_kbc *kbc = (struct espi_evt_data_kbc *)&data;
+
+	return kbc->data;
+}
+
+static void espi_sysjump(void)
+{
+	uint32_t enable = 0;
+
+	/* Disable host interface interrupts during the sysjump */
+	espi_write_lpc_request(espi_dev, ECUSTOM_HOST_SUBS_INTERRUPT_EN,
+			       &enable);
+}
+DECLARE_HOOK(HOOK_SYSJUMP, espi_sysjump, HOOK_PRIO_DEFAULT);
diff --git a/zephyr/shim/src/fan.c b/zephyr/shim/src/fan.c
new file mode 100644
index 0000000000..464c0e2795
--- /dev/null
+++ b/zephyr/shim/src/fan.c
@@ -0,0 +1,415 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define DT_DRV_COMPAT cros_ec_fans
+
+#include "fan.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "math_util.h"
+#include "system.h"
+#include "util.h"
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/pwm.h>
+#include <zephyr/drivers/sensor.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/util_macro.h>
+
+LOG_MODULE_REGISTER(fan_shim, LOG_LEVEL_ERR);
+
+BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
+	     "Exactly one instance of cros-ec,fans should be defined.");
+
+#define FAN_CONFIGS(node_id)                                                   \
+	const struct fan_conf node_id##_conf = {                               \
+		.flags = (COND_CODE_1(DT_PROP(node_id, not_use_rpm_mode), (0), \
+				      (FAN_USE_RPM_MODE))) |                   \
+			 (COND_CODE_1(DT_PROP(node_id, use_fast_start),        \
+				      (FAN_USE_FAST_START), (0))),             \
+		.ch = node_id,                                                 \
+		.pgood_gpio = COND_CODE_1(                                     \
+			DT_NODE_HAS_PROP(node_id, pgood_gpio),                 \
+			(GPIO_SIGNAL(DT_PHANDLE(node_id, pgood_gpio))),        \
+			(GPIO_UNIMPLEMENTED)),                                 \
+		.enable_gpio = COND_CODE_1(                                    \
+			DT_NODE_HAS_PROP(node_id, enable_gpio),                \
+			(GPIO_SIGNAL(DT_PHANDLE(node_id, enable_gpio))),       \
+			(GPIO_UNIMPLEMENTED)),                                 \
+	};                                                                     \
+	const struct fan_rpm node_id##_rpm = {                                 \
+		.rpm_min = DT_PROP(node_id, rpm_min),                          \
+		.rpm_start = DT_PROP(node_id, rpm_start),                      \
+		.rpm_max = DT_PROP(node_id, rpm_max),                          \
+		.rpm_deviation = DT_PROP(node_id, rpm_deviation),              \
+	};
+
+#define FAN_INST(node_id)                \
+	[node_id] = {                    \
+		.conf = &node_id##_conf, \
+		.rpm = &node_id##_rpm,   \
+	},
+
+#define FAN_CONTROL_INST(node_id)                                 \
+	[node_id] = {                                             \
+		.pwm = PWM_DT_SPEC_GET(node_id),                  \
+		.tach = DEVICE_DT_GET(DT_PHANDLE(node_id, tach)), \
+	},
+
+DT_INST_FOREACH_CHILD(0, FAN_CONFIGS)
+
+const struct fan_t fans[FAN_CH_COUNT] = { DT_INST_FOREACH_CHILD(0, FAN_INST) };
+
+/* Data structure to define PWM and tachometer. */
+struct fan_config {
+	struct pwm_dt_spec pwm;
+
+	const struct device *tach;
+};
+
+struct fan_data fan_data[FAN_CH_COUNT];
+static const struct fan_config fan_config[FAN_CH_COUNT] = {
+	DT_INST_FOREACH_CHILD(0, FAN_CONTROL_INST)
+};
+
+static void fan_pwm_update(int ch)
+{
+	const struct fan_config *cfg = &fan_config[ch];
+	struct fan_data *data = &fan_data[ch];
+	const struct device *pwm_dev = cfg->pwm.dev;
+	uint32_t pulse_ns;
+	int ret;
+
+	if (!device_is_ready(pwm_dev)) {
+		LOG_ERR("PWM device %s not ready", pwm_dev->name);
+		return;
+	}
+
+	if (data->pwm_enabled) {
+		pulse_ns = DIV_ROUND_NEAREST(
+			cfg->pwm.period * data->pwm_percent, 100);
+	} else {
+		pulse_ns = 0;
+	}
+
+	LOG_DBG("FAN PWM %s set percent (%d), pulse %d", pwm_dev->name,
+		data->pwm_percent, pulse_ns);
+
+	ret = pwm_set_pulse_dt(&cfg->pwm, pulse_ns);
+	if (ret) {
+		LOG_ERR("pwm_set_pulse_dt failed %s (%d)", pwm_dev->name, ret);
+	}
+}
+
+/**
+ * Get fan rpm value
+ *
+ * @param   ch      operation channel
+ * @return          Actual rpm
+ */
+static int fan_rpm(int ch)
+{
+	const struct device *dev = fan_config[ch].tach;
+	struct sensor_value val = { 0 };
+
+	if (!device_is_ready(dev)) {
+		LOG_ERR("Tach device %s not ready", dev->name);
+		return 0;
+	}
+
+	sensor_sample_fetch_chan(dev, SENSOR_CHAN_RPM);
+	sensor_channel_get(dev, SENSOR_CHAN_RPM, &val);
+
+	return (int)val.val1;
+}
+
+/**
+ * Check all fans are stopped
+ *
+ * @return   1: all fans are stopped. 0: else.
+ */
+static int fan_all_disabled(void)
+{
+	int ch;
+
+	for (ch = 0; ch < fan_get_count(); ch++) {
+		if (fan_data[ch].auto_status != FAN_STATUS_STOPPED) {
+			return 0;
+		}
+	}
+	return 1;
+}
+
+/**
+ * Adjust fan duty by difference between target and actual rpm
+ *
+ * @param   ch        operation channel
+ * @param   rpm_diff  difference between target and actual rpm
+ * @param   duty      current fan duty
+ */
+static void fan_adjust_duty(int ch, int rpm_diff, int duty)
+{
+	int duty_step = 0;
+
+	/* Find suitable duty step */
+	if (ABS(rpm_diff) >= 2000) {
+		duty_step = 20;
+	} else if (ABS(rpm_diff) >= 1000) {
+		duty_step = 10;
+	} else if (ABS(rpm_diff) >= 500) {
+		duty_step = 5;
+	} else if (ABS(rpm_diff) >= 250) {
+		duty_step = 3;
+	} else {
+		duty_step = 1;
+	}
+
+	/* Adjust fan duty step by step */
+	if (rpm_diff > 0) {
+		duty = MIN(duty + duty_step, 100);
+	} else {
+		duty = MAX(duty - duty_step, 1);
+	}
+
+	fan_set_duty(ch, duty);
+
+	LOG_DBG("fan%d: duty %d, rpm_diff %d", ch, duty, rpm_diff);
+}
+
+/**
+ * Smart fan control function.
+ *
+ * The function sets the pwm duty to reach the target rpm
+ *
+ * @param   ch         operation channel
+ */
+enum fan_status fan_smart_control(int ch)
+{
+	struct fan_data *data = &fan_data[ch];
+	int duty, rpm_diff;
+	int rpm_actual = data->rpm_actual;
+	int rpm_target = data->rpm_target;
+	int deviation = fans[ch].rpm->rpm_deviation;
+
+	/* wait rpm is stable */
+	if (ABS(rpm_actual - data->rpm_pre) > (rpm_target * deviation / 100)) {
+		data->rpm_pre = rpm_actual;
+		return FAN_STATUS_CHANGING;
+	}
+
+	/* Record previous rpm */
+	data->rpm_pre = rpm_actual;
+
+	/* Adjust PWM duty */
+	rpm_diff = rpm_target - rpm_actual;
+
+	duty = fan_get_duty(ch);
+	if (duty == 0 && rpm_target == 0) {
+		return FAN_STATUS_STOPPED;
+	}
+
+	if (rpm_diff > (rpm_target * deviation / 100)) {
+		/* Increase PWM duty */
+		if (duty == 100) {
+			return FAN_STATUS_FRUSTRATED;
+		}
+
+		fan_adjust_duty(ch, rpm_diff, duty);
+		return FAN_STATUS_CHANGING;
+	} else if (rpm_diff < -(rpm_target * deviation / 100)) {
+		/* Decrease PWM duty */
+		if (duty == 1 && rpm_target != 0) {
+			return FAN_STATUS_FRUSTRATED;
+		}
+
+		fan_adjust_duty(ch, rpm_diff, duty);
+		return FAN_STATUS_CHANGING;
+	}
+
+	return FAN_STATUS_LOCKED;
+}
+
+static void fan_tick_func_rpm(int ch)
+{
+	struct fan_data *data = &fan_data[ch];
+
+	if (!fan_get_enabled(ch))
+		return;
+
+	/* Get actual rpm */
+	data->rpm_actual = fan_rpm(ch);
+
+	/* TODO: b/279132492 */
+#ifdef CONFIG_PLATFORM_EC_CUSTOM_FAN_DUTY_CONTROL
+	data->auto_status = board_override_fan_control_duty(ch);
+#else
+	/* Do smart fan stuff */
+	data->auto_status = fan_smart_control(ch);
+#endif
+}
+
+static void fan_tick_func_duty(int ch)
+{
+	struct fan_data *data = &fan_data[ch];
+
+	/* Fan in duty mode still want rpm_actual being updated. */
+	if (data->flags & FAN_USE_RPM_MODE) {
+		data->rpm_actual = fan_rpm(ch);
+		if (data->rpm_actual > 0) {
+			data->auto_status = FAN_STATUS_LOCKED;
+		} else {
+			data->auto_status = FAN_STATUS_STOPPED;
+		}
+	} else {
+		if (fan_get_duty(ch) > 0) {
+			data->auto_status = FAN_STATUS_LOCKED;
+		} else {
+			data->auto_status = FAN_STATUS_STOPPED;
+		}
+	}
+}
+
+void fan_tick_func(void)
+{
+	int ch;
+
+	for (ch = 0; ch < fan_get_count(); ch++) {
+		switch (fan_data[ch].current_fan_mode) {
+		case FAN_RPM:
+			fan_tick_func_rpm(ch);
+			break;
+		case FAN_DUTY:
+			fan_tick_func_duty(ch);
+			break;
+		default:
+			LOG_ERR("Invalid fan %d mode: %d", ch,
+				fan_data[ch].current_fan_mode);
+		}
+	}
+}
+DECLARE_HOOK(HOOK_TICK, fan_tick_func, HOOK_PRIO_DEFAULT);
+
+int fan_get_duty(int ch)
+{
+	return fan_data[ch].pwm_percent;
+}
+
+int fan_get_rpm_mode(int ch)
+{
+	return fan_data[ch].current_fan_mode == FAN_RPM ? 1 : 0;
+}
+
+void fan_set_rpm_mode(int ch, int rpm_mode)
+{
+	struct fan_data *data = &fan_data[ch];
+
+	if (rpm_mode && (data->flags & FAN_USE_RPM_MODE)) {
+		data->current_fan_mode = FAN_RPM;
+	} else {
+		data->current_fan_mode = FAN_DUTY;
+	}
+}
+
+int fan_get_rpm_actual(int ch)
+{
+	/* Check PWM is enabled first */
+	if (fan_get_duty(ch) == 0) {
+		return 0;
+	}
+
+	LOG_DBG("fan %d: get actual rpm = %d", ch, fan_data[ch].rpm_actual);
+	return fan_data[ch].rpm_actual;
+}
+
+int fan_get_enabled(int ch)
+{
+	return fan_data[ch].pwm_enabled;
+}
+
+void fan_set_enabled(int ch, int enabled)
+{
+	if (!enabled) {
+		fan_data[ch].auto_status = FAN_STATUS_STOPPED;
+	}
+
+	fan_data[ch].pwm_enabled = enabled;
+
+	fan_pwm_update(ch);
+}
+
+void fan_channel_setup(int ch, unsigned int flags)
+{
+	struct fan_data *data = &fan_data[ch];
+
+	data->flags = flags;
+	/* Set default fan states */
+	data->current_fan_mode = FAN_DUTY;
+	data->auto_status = FAN_STATUS_STOPPED;
+}
+
+void fan_set_duty(int ch, int percent)
+{
+	/* duty is zero */
+	if (!percent) {
+		fan_data[ch].auto_status = FAN_STATUS_STOPPED;
+		if (fan_all_disabled()) {
+			enable_sleep(SLEEP_MASK_FAN);
+		}
+	} else {
+		disable_sleep(SLEEP_MASK_FAN);
+	}
+
+	fan_data[ch].pwm_percent = percent;
+
+	fan_pwm_update(ch);
+}
+
+int fan_get_rpm_target(int ch)
+{
+	return fan_data[ch].rpm_target;
+}
+
+enum fan_status fan_get_status(int ch)
+{
+	return fan_data[ch].auto_status;
+}
+
+#ifndef CONFIG_PLATFORM_EC_FAN_RPM_CUSTOM
+void fan_set_rpm_target(int ch, int rpm)
+{
+	if (rpm == 0) {
+		/* If rpm = 0, disable PWM immediately. Why?*/
+		fan_set_duty(ch, 0);
+	} else {
+		/* This is the counterpart of disabling PWM above. */
+		if (!fan_get_enabled(ch)) {
+			fan_set_enabled(ch, 1);
+		}
+		if (rpm > fans[ch].rpm->rpm_max) {
+			rpm = fans[ch].rpm->rpm_max;
+		} else if (rpm < fans[ch].rpm->rpm_min) {
+			rpm = fans[ch].rpm->rpm_min;
+		}
+	}
+
+	/* Set target rpm */
+	fan_data[ch].rpm_target = rpm;
+	LOG_DBG("fan %d: set target rpm = %d", ch, fan_data[ch].rpm_target);
+}
+#endif
+
+int fan_is_stalled(int ch)
+{
+	int is_pgood = 1;
+	const struct gpio_dt_spec *gp =
+		gpio_get_dt_spec(fans[ch].conf->enable_gpio);
+
+	if (gp != NULL) {
+		is_pgood = gpio_pin_get_dt(gp);
+	}
+
+	return fan_get_enabled(ch) && fan_get_duty(ch) &&
+	       !fan_get_rpm_actual(ch) && is_pgood;
+}
diff --git a/zephyr/shim/src/flash.c b/zephyr/shim/src/flash.c
new file mode 100644
index 0000000000..df684e3447
--- /dev/null
+++ b/zephyr/shim/src/flash.c
@@ -0,0 +1,406 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "drivers/cros_flash.h"
+#include "registers.h"
+#include "task.h"
+#include "util.h"
+
+#include <zephyr/drivers/flash.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+
+#include <flash.h>
+
+LOG_MODULE_REGISTER(shim_flash, LOG_LEVEL_ERR);
+
+#if !DT_HAS_CHOSEN(cros_ec_flash_controller)
+#error "cros-ec,flash-controller device must be chosen"
+#else
+#define cros_flash_dev DEVICE_DT_GET(DT_CHOSEN(cros_ec_flash_controller))
+#endif
+#if !DT_HAS_CHOSEN(zephyr_flash_controller)
+#error "zephyr,flash-controller device must be chosen"
+#else
+#define flash_ctrl_dev DEVICE_DT_GET(DT_CHOSEN(zephyr_flash_controller))
+#endif
+
+K_MUTEX_DEFINE(flash_lock);
+
+#ifdef CONFIG_EXTERNAL_STORAGE
+void crec_flash_lock_mapped_storage(int lock)
+{
+	if (lock)
+		mutex_lock(&flash_lock);
+	else
+		mutex_unlock(&flash_lock);
+}
+#endif
+
+test_mockable int crec_flash_physical_write(int offset, int size,
+					    const char *data)
+{
+	int rv;
+
+	/* Fail if offset, size, and data aren't at least word-aligned */
+	if ((offset | size | (uint32_t)(uintptr_t)data) &
+	    (CONFIG_FLASH_WRITE_SIZE - 1))
+		return EC_ERROR_INVAL;
+
+	/*
+	 * We need to call cros_flash driver because the procedure
+	 * may differ depending on the chip type e.g. ite chips need to
+	 * call watchdog_reload before calling the Zephyr flash driver.
+	 */
+	rv = cros_flash_physical_write(cros_flash_dev, offset, size, data);
+
+	return rv;
+}
+
+int crec_flash_physical_erase(int offset, int size)
+{
+	int rv;
+
+	/*
+	 * We need to call cros_flash driver because the procedure
+	 * may differ depending on the chip type e.g. ite chips need to
+	 * split a large erase operation and reload watchdog, otherwise
+	 * EC reboot happens
+	 */
+	rv = cros_flash_physical_erase(cros_flash_dev, offset, size);
+
+	return rv;
+}
+
+int crec_flash_physical_get_protect(int bank)
+{
+	/*
+	 * We need to call cros_flash driver because Zephyr flash API
+	 * doesn't support reading protected areas and the procedure is
+	 * different for each flash type.
+	 */
+	return cros_flash_physical_get_protect(cros_flash_dev, bank);
+}
+
+uint32_t crec_flash_physical_get_protect_flags(void)
+{
+	/*
+	 * We need to call cros_flash driver because Zephyr flash API
+	 * doesn't support reading protected areas and the procedure is
+	 * different for each flash type.
+	 */
+	return cros_flash_physical_get_protect_flags(cros_flash_dev);
+}
+
+int crec_flash_physical_protect_at_boot(uint32_t new_flags)
+{
+	/*
+	 * It is EC specific, so it needs to be implemented in cros_flash driver
+	 * per chip.
+	 */
+	return cros_flash_physical_protect_at_boot(cros_flash_dev, new_flags);
+}
+
+int crec_flash_physical_protect_now(int all)
+{
+	/*
+	 * It is EC specific, so it needs to be implemented in cros_flash driver
+	 * per chip.
+	 */
+	return cros_flash_physical_protect_now(cros_flash_dev, all);
+}
+
+test_mockable int crec_flash_physical_read(int offset, int size, char *data)
+{
+	int rv;
+
+	/*
+	 * Lock the physical flash operation here because, we call the Zephyr
+	 * driver directly.
+	 */
+	crec_flash_lock_mapped_storage(1);
+
+	rv = flash_read(flash_ctrl_dev, offset, data, size);
+
+	/* Unlock physical flash operations */
+	crec_flash_lock_mapped_storage(0);
+
+	return rv;
+}
+
+static int flash_dev_init(void)
+{
+	if (!device_is_ready(cros_flash_dev) ||
+	    !device_is_ready(flash_ctrl_dev))
+		k_oops();
+	cros_flash_init(cros_flash_dev);
+
+	return 0;
+}
+
+uint32_t crec_flash_physical_get_valid_flags(void)
+{
+	return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW |
+	       EC_FLASH_PROTECT_ALL_NOW;
+}
+
+uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
+{
+	uint32_t ret = 0;
+
+	/* If RO protection isn't enabled, its at-boot state can be changed. */
+	if (!(cur_flags & EC_FLASH_PROTECT_RO_NOW))
+		ret |= EC_FLASH_PROTECT_RO_AT_BOOT;
+
+	/*
+	 * If entire flash isn't protected at this boot, it can be enabled if
+	 * the WP GPIO is asserted.
+	 */
+	if (!(cur_flags & EC_FLASH_PROTECT_ALL_NOW) &&
+	    (cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED))
+		ret |= EC_FLASH_PROTECT_ALL_NOW;
+
+	return ret;
+}
+
+#if IS_ENABLED(CONFIG_PLATFORM_EC_USE_ZEPHYR_FLASH_PAGE_LAYOUT)
+int crec_flash_bank_size(int bank)
+{
+	int rv;
+	struct flash_pages_info info;
+
+	rv = flash_get_page_info_by_idx(flash_ctrl_dev, bank, &info);
+
+	if (rv)
+		return -1;
+
+	return info.size;
+}
+
+int crec_flash_bank_erase_size(int bank)
+{
+	return crec_flash_bank_size(bank);
+}
+
+int crec_flash_bank_index(int offset)
+{
+	int rv;
+	struct flash_pages_info info;
+
+	rv = flash_get_page_info_by_offs(flash_ctrl_dev, offset, &info);
+
+	if (rv)
+		return -1;
+
+	return info.index;
+}
+
+int crec_flash_bank_count(int offset, int size)
+{
+	int begin, end;
+
+	if (size < 1)
+		return -1;
+
+	begin = crec_flash_bank_index(offset);
+	end = crec_flash_bank_index(offset + size - 1);
+
+	if (begin < 0 || end < 0)
+		return -1;
+
+	return end - begin + 1;
+}
+
+int crec_flash_bank_start_offset(int bank)
+{
+	int rv;
+	struct flash_pages_info info;
+
+	rv = flash_get_page_info_by_idx(flash_ctrl_dev, bank, &info);
+
+	if (rv)
+		return -1;
+
+	return info.start_offset;
+}
+
+/*
+ * Flash_get_region() is used to get information about region which contains
+ * 'start_idx' sector. Information about region is saved in a ec_flash_bank
+ * structure. Function returns EC_RES_IN_PROGRESS if there are more regions.
+ * EC_RES_SUCCESS is returned if the region is the last one. EC_RES_ERROR is
+ * returned if there was an error.
+ *
+ * Please note that 'start_idx' should point to first sector of the region
+ * otherwise number of sectors in region will be wrong.
+ */
+static int flash_get_region(size_t start_idx, struct ec_flash_bank *region)
+{
+	struct flash_pages_info first, next;
+	size_t total_pages;
+	int rv;
+
+	total_pages = flash_get_page_count(flash_ctrl_dev);
+	rv = flash_get_page_info_by_idx(flash_ctrl_dev, start_idx, &first);
+	if (rv)
+		return EC_RES_ERROR;
+
+	/* Region has sectors with the same size, save these information now. */
+	region->count = 1;
+	region->size_exp = __fls(first.size);
+	region->write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE);
+	region->erase_size_exp = __fls(first.size);
+	region->protect_size_exp = __fls(first.size);
+
+	for (size_t i = start_idx + 1; i < total_pages; i++) {
+		rv = flash_get_page_info_by_idx(flash_ctrl_dev, i, &next);
+		if (rv)
+			return EC_RES_ERROR;
+
+		/*
+		 * If size of the next page is different than size of the first
+		 * page of this region then we know how many pages the region
+		 * has and this is not the last region.
+		 */
+		if (next.size != first.size)
+			return EC_RES_IN_PROGRESS;
+
+		region->count++;
+	}
+
+	return EC_RES_SUCCESS;
+}
+
+/*
+ * Both crec_flash_print_region_into() and crec_flash_response_fill_banks()
+ * could be easily implemented if we had an access to flash layout structure
+ * that aggregates pages with the same size in one entry ('compressed' form).
+ *
+ * Zephyr internally keeps flash layout in structure of this type, but using the
+ * flash API it's only possible to get information about single pages. Extending
+ * flash API encounters resistance from developers.
+ */
+void crec_flash_print_region_info(void)
+{
+	const struct flash_parameters *params;
+	struct ec_flash_bank region;
+	size_t sector_idx = 0;
+	int res;
+
+	params = flash_get_parameters(flash_ctrl_dev);
+	if (!params)
+		return;
+
+	cprintf(CC_COMMAND, "Regions:\n");
+	do {
+		res = flash_get_region(sector_idx, &region);
+		if (res != EC_RES_SUCCESS && res != EC_RES_IN_PROGRESS)
+			break;
+
+		cprintf(CC_COMMAND, " %d region%s:\n", region.count,
+			(region.count == 1 ? "" : "s"));
+		cprintf(CC_COMMAND, "  Erase:   %4d B (to %d-bits)\n",
+			1 << region.erase_size_exp,
+			params->erase_value ? 1 : 0);
+		cprintf(CC_COMMAND, "  Size/Protect: %4d B\n",
+			1 << region.size_exp);
+
+		sector_idx += region.count;
+	} while (res == EC_RES_IN_PROGRESS);
+}
+
+int crec_flash_response_fill_banks(struct ec_response_flash_info_2 *r,
+				   int num_banks)
+{
+	struct ec_flash_bank region;
+	size_t sector_idx = 0;
+	int banks_idx = 0;
+	int res;
+
+	do {
+		res = flash_get_region(sector_idx, &region);
+		if (res != EC_RES_SUCCESS && res != EC_RES_IN_PROGRESS)
+			break;
+
+		if (banks_idx < num_banks)
+			memcpy(&r->banks[banks_idx], &region,
+			       sizeof(struct ec_flash_bank));
+
+		sector_idx += region.count;
+		banks_idx++;
+	} while (res == EC_RES_IN_PROGRESS);
+
+	r->num_banks_desc = MIN(banks_idx, num_banks);
+	r->num_banks_total = banks_idx;
+
+	return res;
+}
+
+int crec_flash_total_banks(void)
+{
+	return flash_get_page_count(flash_ctrl_dev);
+}
+#endif /* CONFIG_PLATFORM_EC_USE_ZEPHYR_FLASH_PAGE_LAYOUT */
+
+#if IS_ENABLED(CONFIG_SHELL)
+static int command_flashchip(const struct shell *shell, size_t argc,
+			     char **argv)
+{
+	uint8_t manufacturer;
+	uint16_t device;
+	uint8_t status1;
+	uint8_t status2;
+	int res;
+
+	res = cros_flash_physical_get_status(cros_flash_dev, &status1,
+					     &status2);
+
+	if (!res)
+		shell_fprintf(shell, SHELL_NORMAL,
+			      "Status 1: 0x%02x, Status 2: 0x%02x\n", status1,
+			      status2);
+
+	res = cros_flash_physical_get_jedec_id(cros_flash_dev, &manufacturer,
+					       &device);
+
+	if (!res)
+		shell_fprintf(shell, SHELL_NORMAL,
+			      "Manufacturer: 0x%02x, DID: 0x%04x\n",
+			      manufacturer, device);
+
+	return 0;
+}
+SHELL_CMD_REGISTER(flashchip, NULL, "Information about flash chip",
+		   command_flashchip);
+#endif
+
+/*
+ * The priority flash_dev_init should be lower than GPIO initialization because
+ * it calls gpio_pin_get_dt function.
+ */
+#if CONFIG_PLATFORM_EC_FLASH_INIT_PRIORITY <= \
+	CONFIG_PLATFORM_EC_GPIO_INIT_PRIORITY
+#error "Flash must be initialized after GPIOs"
+#endif
+#if IS_ENABLED(CONFIG_SOC_FAMILY_NPCX)
+#if CONFIG_PLATFORM_EC_FLASH_INIT_PRIORITY <= \
+	CONFIG_CROS_FLASH_NPCX_INIT_PRIORITY
+#error "CONFIG_PLATFORM_EC_FLASH_INIT_PRIORITY must be greater than" \
+	"CONFIG_CROS_FLASH_NPCX_INIT_PRIORITY."
+#endif
+#elif IS_ENABLED(CONFIG_SOC_FAMILY_MEC)
+#if CONFIG_PLATFORM_EC_FLASH_INIT_PRIORITY <= \
+	CONFIG_CROS_FLASH_MCHP_INIT_PRIORITY
+#error "CONFIG_PLATFORM_EC_FLASH_INIT_PRIORITY must be greater than" \
+	"CONFIG_CROS_FLASH_MCHP_INIT_PRIORITY."
+#endif
+#elif IS_ENABLED(CONFIG_CROS_FLASH)
+#if CONFIG_PLATFORM_EC_FLASH_INIT_PRIORITY <= CONFIG_CROS_FLASH_INIT_PRIORITY
+#error "CONFIG_PLATFORM_EC_FLASH_INIT_PRIORITY must be greater than" \
+	"CONFIG_CROS_FLASH_INIT_PRIORITY."
+#endif
+#endif
+SYS_INIT(flash_dev_init, POST_KERNEL, CONFIG_PLATFORM_EC_FLASH_INIT_PRIORITY);
diff --git a/zephyr/shim/src/gpio.c b/zephyr/shim/src/gpio.c
new file mode 100644
index 0000000000..5e2d28d26b
--- /dev/null
+++ b/zephyr/shim/src/gpio.c
@@ -0,0 +1,413 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifdef __REQUIRE_ZEPHYR_GPIOS__
+#undef __REQUIRE_ZEPHYR_GPIOS__
+#endif
+#include "cros_version.h"
+#include "gpio.h"
+#include "gpio/gpio.h"
+#include "ioexpander.h"
+#include "system.h"
+
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(gpio_shim, LOG_LEVEL_ERR);
+
+/*
+ * Static information about each GPIO that is configured in the named_gpios
+ * device tree node.
+ */
+struct gpio_config {
+	/* Access structure for lookup */
+	struct gpio_dt_spec spec;
+	/* GPIO net name */
+	const char *name;
+	/* From DTS, excludes interrupts flags */
+	gpio_flags_t init_flags;
+	/* From DTS, skips initialisation */
+	bool no_auto_init;
+};
+
+/*
+ * Initialise a gpio_dt_spec structure.
+ * Normally the standard macro (GPIO_DT_SPEC_GET) could be used, but
+ * the flags stored in our device tree config are the full 32 bit flags,
+ * whereas the standard macros assume that only 8 bits of initial flags
+ * will be needed.
+ */
+#define OUR_DT_SPEC(id)                                         \
+	{                                                       \
+		.port = DEVICE_DT_GET(DT_GPIO_CTLR(id, gpios)), \
+		.pin = DT_GPIO_PIN(id, gpios),                  \
+		.dt_flags = 0xFF & (DT_GPIO_FLAGS(id, gpios)),  \
+	}
+
+#define GPIO_CONFIG(id)                                    \
+	{                                                  \
+		.spec = OUR_DT_SPEC(id),                   \
+		.name = DT_NODE_FULL_NAME(id),             \
+		.init_flags = DT_GPIO_FLAGS(id, gpios),    \
+		.no_auto_init = DT_PROP(id, no_auto_init), \
+	},
+#define GPIO_IMPL_CONFIG(id) \
+	COND_CODE_1(DT_NODE_HAS_PROP(id, gpios), (GPIO_CONFIG(id)), ())
+
+static const struct gpio_config configs[] = {
+#if DT_NODE_EXISTS(NAMED_GPIOS_NODE)
+	DT_FOREACH_CHILD(NAMED_GPIOS_NODE, GPIO_IMPL_CONFIG)
+#endif
+};
+
+#undef GPIO_IMPL_CONFIG
+#undef GPIO_CONFIG
+#undef OUR_DT_SPEC
+
+/*
+ * Generate a pointer for each GPIO, pointing to the gpio_dt_spec entry
+ * in the table. These are named after the GPIO generated signal name,
+ * so they can be used directly in Zephyr GPIO API calls.
+ *
+ * Potentially, instead of generating a pointer, the macro could
+ * point directly into the table by exposing the gpio_config struct.
+ *
+ * Skip generating a pointer to unimplemented GPIOs. If GPIO is unimplemented,
+ * GPIO_SIGNAL(id) is resolved to an gpio_signal enum entry which has a value
+ * of -1 (GPIO_UNIMPLEMENTED). As a result we could point to address outside
+ * of the configs array. Also some compilers don't like negative index.
+ */
+
+#define GPIO_PTRS(id)                                               \
+	COND_CODE_1(DT_NODE_HAS_PROP(id, gpios),                    \
+		    (const struct gpio_dt_spec *const GPIO_DT_NAME( \
+			     GPIO_SIGNAL(id)) =                     \
+			     &configs[GPIO_SIGNAL(id)].spec;),      \
+		    ())
+
+#if DT_NODE_EXISTS(NAMED_GPIOS_NODE)
+DT_FOREACH_CHILD(NAMED_GPIOS_NODE, GPIO_PTRS)
+#endif
+
+int gpio_is_implemented(enum gpio_signal signal)
+{
+	return signal >= 0 && signal < ARRAY_SIZE(configs);
+}
+
+int gpio_get_level(enum gpio_signal signal)
+{
+	if (!gpio_is_implemented(signal))
+		return 0;
+
+	const int l = gpio_pin_get_raw(configs[signal].spec.port,
+				       configs[signal].spec.pin);
+
+	if (l < 0) {
+		LOG_ERR("Cannot read %s (%d)", configs[signal].name, l);
+		return 0;
+	}
+	return l;
+}
+
+int gpio_get_ternary(enum gpio_signal signal)
+{
+	int pd, pu;
+	int flags = gpio_get_default_flags(signal);
+
+	/* Read GPIO with internal pull-down */
+	gpio_set_flags(signal, GPIO_INPUT | GPIO_PULL_DOWN);
+	pd = gpio_get_level(signal);
+	udelay(100);
+
+	/* Read GPIO with internal pull-up */
+	gpio_set_flags(signal, GPIO_INPUT | GPIO_PULL_UP);
+	pu = gpio_get_level(signal);
+	udelay(100);
+
+	/* Reset GPIO flags */
+	gpio_set_flags(signal, flags);
+
+	/* Check PU and PD readings to determine tristate */
+	return pu && !pd ? 2 : pd;
+}
+
+const char *gpio_get_name(enum gpio_signal signal)
+{
+	if (!gpio_is_implemented(signal))
+		return "UNIMPLEMENTED";
+
+	return configs[signal].name;
+}
+
+void gpio_set_level(enum gpio_signal signal, int value)
+{
+	if (!gpio_is_implemented(signal))
+		return;
+
+	int rv = gpio_pin_set_raw(configs[signal].spec.port,
+				  configs[signal].spec.pin, value);
+
+	if (rv < 0) {
+		LOG_ERR("Cannot write %s (%d)", configs[signal].name, rv);
+	}
+}
+
+void gpio_set_level_verbose(enum console_channel channel,
+			    enum gpio_signal signal, int value)
+{
+	cprints(channel, "Set %s: %d", gpio_get_name(signal), value);
+	gpio_set_level(signal, value);
+}
+
+void gpio_or_ioex_set_level(int signal, int value)
+{
+	gpio_set_level(signal, value);
+}
+
+int gpio_or_ioex_get_level(int signal, int *value)
+{
+	*value = gpio_get_level(signal);
+	return EC_SUCCESS;
+}
+
+/* Don't define any 1.8V bit if not supported. */
+#ifndef GPIO_VOLTAGE_1P8
+#define GPIO_VOLTAGE_1P8 0
+#endif
+
+/* GPIO flags which are the same in Zephyr and this codebase */
+#define GPIO_CONVERSION_SAME_BITS                                             \
+	(GPIO_OPEN_DRAIN | GPIO_PULL_UP | GPIO_PULL_DOWN | GPIO_VOLTAGE_1P8 | \
+	 GPIO_INPUT | GPIO_OUTPUT | GPIO_OUTPUT_INIT_LOW |                    \
+	 GPIO_OUTPUT_INIT_HIGH)
+
+#define FLAGS_HANDLED_FROM_ZEPHYR                                      \
+	(GPIO_CONVERSION_SAME_BITS | GPIO_INT_ENABLE | GPIO_INT_EDGE | \
+	 GPIO_INT_HIGH_1 | GPIO_INT_LOW_0)
+
+#define FLAGS_HANDLED_TO_ZEPHYR                                               \
+	(GPIO_CONVERSION_SAME_BITS | GPIO_INT_F_RISING | GPIO_INT_F_FALLING | \
+	 GPIO_INT_F_LOW | GPIO_INT_F_HIGH)
+
+int convert_from_zephyr_flags(const gpio_flags_t zephyr)
+{
+	/* Start out with the bits that are the same. */
+	int ec_flags = zephyr & GPIO_CONVERSION_SAME_BITS;
+	gpio_flags_t unhandled_flags = zephyr & (~FLAGS_HANDLED_FROM_ZEPHYR);
+
+	/* TODO(b/173789980): handle conversion of more bits? */
+	if (unhandled_flags) {
+		LOG_WRN("Unhandled GPIO bits in zephyr->ec conversion: 0x%08X",
+			unhandled_flags);
+	}
+
+	if (zephyr & GPIO_INT_ENABLE) {
+		if (zephyr & GPIO_INT_EDGE) {
+			if (zephyr & GPIO_INT_HIGH_1)
+				ec_flags |= GPIO_INT_F_RISING;
+			if (zephyr & GPIO_INT_LOW_0)
+				ec_flags |= GPIO_INT_F_FALLING;
+		} else {
+			if (zephyr & GPIO_INT_LOW_0)
+				ec_flags |= GPIO_INT_F_LOW;
+			if (zephyr & GPIO_INT_HIGH_1)
+				ec_flags |= GPIO_INT_F_HIGH;
+		}
+	}
+
+	return ec_flags;
+}
+
+gpio_flags_t convert_to_zephyr_flags(int ec_flags)
+{
+	/* Start out with the bits that are the same. */
+	gpio_flags_t zephyr_flags = ec_flags & GPIO_CONVERSION_SAME_BITS;
+	int unhandled_flags = ec_flags & (~FLAGS_HANDLED_TO_ZEPHYR);
+
+	/* TODO(b/173789980): handle conversion of more bits? */
+	if (unhandled_flags) {
+		LOG_WRN("Unhandled GPIO bits in ec->zephyr conversion: 0x%08X",
+			unhandled_flags);
+	}
+
+	if (ec_flags & GPIO_INT_F_RISING)
+		zephyr_flags |= GPIO_INT_ENABLE | GPIO_INT_EDGE |
+				GPIO_INT_HIGH_1;
+	if (ec_flags & GPIO_INT_F_FALLING)
+		zephyr_flags |= GPIO_INT_ENABLE | GPIO_INT_EDGE |
+				GPIO_INT_LOW_0;
+	if (ec_flags & GPIO_INT_F_LOW)
+		zephyr_flags |= GPIO_INT_ENABLE | GPIO_INT_LOW_0;
+	if (ec_flags & GPIO_INT_F_HIGH)
+		zephyr_flags |= GPIO_INT_ENABLE | GPIO_INT_HIGH_1;
+
+	return zephyr_flags;
+}
+
+int gpio_get_flags(enum gpio_signal signal)
+{
+	return gpio_get_default_flags(signal);
+}
+
+int gpio_get_default_flags(enum gpio_signal signal)
+{
+	if (!gpio_is_implemented(signal))
+		return 0;
+
+	return convert_from_zephyr_flags(configs[signal].init_flags);
+}
+
+const struct gpio_dt_spec *gpio_get_dt_spec(enum gpio_signal signal)
+{
+	if (!gpio_is_implemented(signal))
+		return 0;
+	return &configs[signal].spec;
+}
+
+/* Allow access to this function in tests so we can run it multiple times
+ * without having to create a new binary for each run.
+ */
+test_export_static int init_gpios(void)
+{
+	gpio_flags_t flags;
+	bool is_sys_jumped = system_jumped_to_this_image();
+
+	for (size_t i = 0; i < ARRAY_SIZE(configs); ++i) {
+		int rv;
+
+		/* Skip GPIOs that have set no-auto-init. */
+		if (configs[i].no_auto_init)
+			continue;
+
+		if (!device_is_ready(configs[i].spec.port))
+			LOG_ERR("Not found (%s)", configs[i].name);
+
+		/*
+		 * The configs[i].init_flags variable is read-only, so the
+		 * following assignment is needed because the flags need
+		 * adjusting on a warm reboot.
+		 */
+		flags = configs[i].init_flags;
+
+		/*
+		 * For warm boot, do not set the output state.
+		 */
+		if (is_sys_jumped && (flags & GPIO_OUTPUT)) {
+			flags &=
+				~(GPIO_OUTPUT_INIT_LOW | GPIO_OUTPUT_INIT_HIGH);
+		}
+
+		rv = gpio_pin_configure_dt(&configs[i].spec, flags);
+		if (rv < 0) {
+			LOG_ERR("Config failed %s (%d)", configs[i].name, rv);
+		}
+	}
+
+	/* Configure unused pins in chip driver for better power consumption */
+	if (gpio_config_unused_pins) {
+		int rv;
+
+		rv = gpio_config_unused_pins();
+		if (rv < 0) {
+			return rv;
+		}
+	}
+
+	return 0;
+}
+#if CONFIG_PLATFORM_EC_GPIO_INIT_PRIORITY <= CONFIG_KERNEL_INIT_PRIORITY_DEFAULT
+#error "GPIOs must initialize after the kernel default initialization"
+#endif
+SYS_INIT(init_gpios, POST_KERNEL, CONFIG_PLATFORM_EC_GPIO_INIT_PRIORITY);
+
+void gpio_reset(enum gpio_signal signal)
+{
+	if (!gpio_is_implemented(signal))
+		return;
+
+	gpio_pin_configure_dt(&configs[signal].spec,
+			      configs[signal].init_flags);
+}
+
+int gpio_save_port_config(const struct device *port, gpio_flags_t *flags,
+			  int buff_size)
+{
+	int state_offset = 0;
+
+	for (size_t i = 0; i < ARRAY_SIZE(configs); ++i) {
+		if (state_offset >= buff_size) {
+			LOG_ERR("%s buffer is too small", __func__);
+			return EC_ERROR_UNKNOWN;
+		}
+
+		if (port == configs[i].spec.port) {
+			gpio_pin_get_config_dt(&configs[i].spec,
+					       &flags[state_offset++]);
+		}
+	}
+
+	return EC_SUCCESS;
+}
+
+int gpio_restore_port_config(const struct device *port, gpio_flags_t *flags,
+			     int buff_size)
+{
+	int state_offset = 0;
+
+	for (size_t i = 0; i < ARRAY_SIZE(configs); ++i) {
+		if (state_offset >= buff_size) {
+			LOG_ERR("%s buffer is too small", __func__);
+			return EC_ERROR_UNKNOWN;
+		}
+
+		if (port == configs[i].spec.port) {
+			gpio_pin_configure_dt(&configs[i].spec,
+					      flags[state_offset++]);
+		}
+	}
+
+	return EC_SUCCESS;
+}
+
+void gpio_reset_port(const struct device *port)
+{
+	for (size_t i = 0; i < ARRAY_SIZE(configs); ++i) {
+		if (port == configs[i].spec.port) {
+			gpio_pin_configure_dt(&configs[i].spec,
+					      configs[i].init_flags);
+		}
+	}
+}
+
+void gpio_set_flags(enum gpio_signal signal, int flags)
+{
+	if (!gpio_is_implemented(signal))
+		return;
+
+	gpio_pin_configure_dt(&configs[signal].spec,
+			      convert_to_zephyr_flags(flags));
+}
+
+void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
+{
+	const gpio_flags_t zephyr_flags = convert_to_zephyr_flags(flags);
+
+	/* Using __builtin_ctz here will guarantee that this loop is as
+	 * performant as the underlying architecture allows it to be.
+	 */
+	while (mask != 0) {
+		int pin = __builtin_ctz(mask);
+
+		gpio_configure_port_pin(port, pin, zephyr_flags);
+		mask &= ~BIT(pin);
+	}
+}
+
+int signal_is_gpio(int signal)
+{
+	return true;
+}
diff --git a/zephyr/shim/src/gpio_id.c b/zephyr/shim/src/gpio_id.c
new file mode 100644
index 0000000000..8a3aafd45a
--- /dev/null
+++ b/zephyr/shim/src/gpio_id.c
@@ -0,0 +1,74 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifdef __REQUIRE_ZEPHYR_GPIOS__
+#undef __REQUIRE_ZEPHYR_GPIOS__
+#endif
+
+#include "gpio.h"
+#include "util.h"
+
+#include <zephyr/devicetree.h>
+
+#define CONVERT_NUMERAL_SYSTEM_EVAL(system, bits, nbits) \
+	system##_from_bits(bits, nbits)
+#define CONVERT_NUMERAL_SYSTEM(system, bits, nbits) \
+	CONVERT_NUMERAL_SYSTEM_EVAL(system, bits, nbits)
+
+/* TODO: b/218904113: Convert to using Zephyr GPIOs */
+#define READ_PIN_FROM_PHANDLE(node_id, prop, idx) \
+	gpio_get_ternary(GPIO_SIGNAL(DT_PHANDLE_BY_IDX(node_id, prop, idx))),
+
+#define SKU_GPIO_ID_NODE DT_NODELABEL(gpio_id_sku)
+#if DT_NODE_HAS_STATUS(SKU_GPIO_ID_NODE, okay)
+
+__override uint32_t board_get_sku_id(void)
+{
+	static uint32_t sku_id = (uint32_t)-1;
+
+	if (sku_id == (uint32_t)-1) {
+		int bits[] = { DT_FOREACH_PROP_ELEM(SKU_GPIO_ID_NODE, bits,
+						    READ_PIN_FROM_PHANDLE) };
+
+		if (sizeof(bits) == 0)
+			return (uint32_t)-1;
+
+		sku_id = CONVERT_NUMERAL_SYSTEM(
+			DT_STRING_TOKEN(SKU_GPIO_ID_NODE, system), bits,
+			ARRAY_SIZE(bits));
+	}
+
+	return sku_id;
+}
+
+#endif
+
+#define BOARD_GPIO_ID_NODE DT_NODELABEL(gpio_id_board)
+#if DT_NODE_HAS_STATUS(SKU_GPIO_ID_NODE, okay)
+
+__override int board_get_version(void)
+{
+	static int board_version = -1;
+
+	if (board_version == -1) {
+		int bits[] = { DT_FOREACH_PROP_ELEM(BOARD_GPIO_ID_NODE, bits,
+						    READ_PIN_FROM_PHANDLE) };
+
+		if (sizeof(bits) == 0)
+			return -1;
+
+		board_version = CONVERT_NUMERAL_SYSTEM(
+			DT_STRING_TOKEN(BOARD_GPIO_ID_NODE, system), bits,
+			ARRAY_SIZE(bits));
+	}
+
+	return board_version;
+}
+
+#endif
+
+BUILD_ASSERT(DT_NODE_HAS_STATUS(SKU_GPIO_ID_NODE, okay) ||
+		     DT_NODE_HAS_STATUS(BOARD_GPIO_ID_NODE, okay),
+	     "neither sku or board id nodelabels found");
diff --git a/zephyr/shim/src/gpio_int.c b/zephyr/shim/src/gpio_int.c
new file mode 100644
index 0000000000..58b543912c
--- /dev/null
+++ b/zephyr/shim/src/gpio_int.c
@@ -0,0 +1,214 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifdef __REQUIRE_ZEPHYR_GPIOS__
+#undef __REQUIRE_ZEPHYR_GPIOS__
+#endif
+#include "cros_version.h"
+#include "gpio.h"
+#include "gpio/gpio.h"
+#include "gpio/gpio_int.h"
+
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(gpio_int, LOG_LEVEL_ERR);
+
+/*
+ * Structure containing the read-only configuration data for an
+ * interrupt, such as the initial flags and the handler vector.
+ * The RW callback data is kept in a separate array.
+ */
+struct gpio_int_config {
+	void (*handler)(enum gpio_signal); /* Handler to call */
+	gpio_flags_t flags; /* Flags */
+	const struct device *port; /* GPIO device */
+	gpio_pin_t pin; /* GPIO pin */
+	enum gpio_signal signal; /* Signal associated with interrupt */
+};
+
+/*
+ * Verify there is only a single interrupt node.
+ */
+#if DT_HAS_COMPAT_STATUS_OKAY(cros_ec_gpio_interrupts)
+BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(cros_ec_gpio_interrupts) == 1,
+	     "Only one node for cros_ec_gpio_interrupts is allowed");
+#endif
+
+/*
+ * Shorthand to get the node containing the interrupt DTS.
+ */
+#define DT_IRQ_NODE DT_COMPAT_GET_ANY_STATUS_OKAY(cros_ec_gpio_interrupts)
+
+/*
+ * Declare all the external handlers.
+ */
+
+#define INT_HANDLER_DECLARE(id) \
+	extern void DT_STRING_TOKEN(id, handler)(enum gpio_signal);
+
+#if DT_HAS_COMPAT_STATUS_OKAY(cros_ec_gpio_interrupts)
+DT_FOREACH_CHILD_STATUS_OKAY(DT_IRQ_NODE, INT_HANDLER_DECLARE)
+#endif
+
+#undef INT_HANDLER_DECLARE
+
+/*
+ * Create an array of callbacks. This is separate from the
+ * configuration so that the writable data is in BSS.
+ */
+struct gpio_callback int_cb_data[GPIO_INT_COUNT];
+
+/*
+ * Create an instance of a gpio_int_config structure from a DTS node
+ */
+
+#define INT_CONFIG_ENTRY(id, irq_pin)                                \
+	{                                                            \
+		.handler = DT_STRING_TOKEN(id, handler),             \
+		.flags = DT_PROP(id, flags),                         \
+		.port = DEVICE_DT_GET(DT_GPIO_CTLR(irq_pin, gpios)), \
+		.pin = DT_GPIO_PIN(irq_pin, gpios),                  \
+		.signal = GPIO_SIGNAL(irq_pin),                      \
+	},
+
+#define INT_CONFIG_FROM_NODE(id) INT_CONFIG_ENTRY(id, DT_PROP(id, irq_pin))
+
+#if DT_HAS_COMPAT_STATUS_OKAY(cros_ec_gpio_interrupts)
+/*
+ * Create an array of gpio_int_config containing the read-only configuration
+ * for this interrupt.
+ */
+static const struct gpio_int_config gpio_int_data[] = {
+
+	DT_FOREACH_CHILD_STATUS_OKAY(DT_IRQ_NODE, INT_CONFIG_FROM_NODE)
+};
+#endif
+
+#undef INT_CONFIG_ENTRY
+#undef INT_CONFIG_FROM_NODE
+
+/*
+ * Now initialize a pointer for each interrupt that points to the
+ * configuration array entries. These are used externally
+ * to reference the interrupts (to enable or disable).
+ * These pointers are externally declared in gpio/gpio_int.h
+ * and the names are referenced via a macro using the node label or
+ * node id.
+ */
+
+#define INT_CONFIG_PTR_DECLARE(id)                                   \
+	const struct gpio_int_config *const GPIO_INT_FROM_NODE(id) = \
+		&gpio_int_data[GPIO_INT_ENUM(id)];
+
+#if DT_HAS_COMPAT_STATUS_OKAY(cros_ec_gpio_interrupts)
+
+DT_FOREACH_CHILD_STATUS_OKAY(DT_IRQ_NODE, INT_CONFIG_PTR_DECLARE)
+
+#endif
+
+#undef INT_CONFIG_PTR_DECLARE
+
+/*
+ * Mapping of GPIO signal to interrupt configuration block.
+ */
+static const struct gpio_int_config *
+signal_to_interrupt(enum gpio_signal signal)
+{
+#if DT_HAS_COMPAT_STATUS_OKAY(cros_ec_gpio_interrupts)
+	for (int i = 0; i < ARRAY_SIZE(gpio_int_data); i++) {
+		if (signal == gpio_int_data[i].signal)
+			return &gpio_int_data[i];
+	}
+#endif
+	return NULL;
+}
+
+#if DT_HAS_COMPAT_STATUS_OKAY(cros_ec_gpio_interrupts)
+/*
+ * Callback handler.
+ * Call the stored interrupt handler.
+ */
+static void gpio_cb_handler(const struct device *dev,
+			    struct gpio_callback *cbdata, uint32_t pins)
+{
+	/*
+	 * Retrieve the array index from the callback pointer, and
+	 * use that to get the interrupt config array entry.
+	 */
+	const struct gpio_int_config *conf =
+		&gpio_int_data[cbdata - &int_cb_data[0]];
+	conf->handler(conf->signal);
+}
+
+/*
+ * Enable the interrupt.
+ * Check whether the callback is already installed, and if
+ * not, init and add the callback before enabling the
+ * interrupt.
+ */
+int gpio_enable_dt_interrupt(const struct gpio_int_config *conf)
+{
+	/*
+	 * Get the callback data associated with this interrupt
+	 * by calculating the index in the gpio_int_config array.
+	 */
+	struct gpio_callback *cb = &int_cb_data[conf - &gpio_int_data[0]];
+	gpio_flags_t flags;
+	/*
+	 * Check whether callback has been initialised.
+	 */
+	if (!cb->handler) {
+		/*
+		 * Initialise and add the callback.
+		 */
+		gpio_init_callback(cb, gpio_cb_handler, BIT(conf->pin));
+		gpio_add_callback(conf->port, cb);
+	}
+	flags = (conf->flags | GPIO_INT_ENABLE) & ~GPIO_INT_DISABLE;
+	return gpio_pin_interrupt_configure(conf->port, conf->pin, flags);
+}
+
+const struct gpio_int_config *
+gpio_interrupt_get_config(enum gpio_interrupts intr)
+{
+	return &gpio_int_data[intr];
+}
+
+/*
+ * Legacy API calls to enable/disable interrupts.
+ */
+int gpio_enable_interrupt(enum gpio_signal signal)
+{
+	const struct gpio_int_config *ic = signal_to_interrupt(signal);
+
+	if (ic == NULL)
+		return -1;
+
+	return gpio_enable_dt_interrupt(ic);
+}
+
+#endif
+
+/*
+ * Disable the interrupt by setting the GPIO_INT_DISABLE flag.
+ */
+int gpio_disable_dt_interrupt(const struct gpio_int_config *conf)
+{
+	return gpio_pin_interrupt_configure(conf->port, conf->pin,
+					    GPIO_INT_DISABLE);
+}
+
+int gpio_disable_interrupt(enum gpio_signal signal)
+{
+	const struct gpio_int_config *ic = signal_to_interrupt(signal);
+
+	if (ic == NULL)
+		return -1;
+
+	return gpio_disable_dt_interrupt(ic);
+}
diff --git a/zephyr/shim/src/hooks.c b/zephyr/shim/src/hooks.c
new file mode 100644
index 0000000000..8c49857c3e
--- /dev/null
+++ b/zephyr/shim/src/hooks.c
@@ -0,0 +1,265 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "console.h"
+#include "ec_tasks.h"
+#include "hook_types.h"
+#include "hooks.h"
+#include "task.h"
+#include "timer.h"
+
+#include <zephyr/kernel.h>
+
+#include <ap_power/ap_power.h>
+#include <ap_power/ap_power_events.h>
+
+/*
+ * hook_registry maps each hook_type to the list of handlers for that hook type.
+ *
+ * Because this structure is not supported by the usual STRUCT_SECTION_FOREACH,
+ * this code must manually generate references to the symbols generated by
+ * STRUCT_SECTION_ITERABLE_ALTERNATE in zephyr_hooks_shim.h.
+ */
+#define HOOK_LIST_EXTERNS(type)                          \
+	extern const struct zephyr_shim_hook_info        \
+		_zephyr_shim_hook_##type##_list_start[]; \
+	extern const struct zephyr_shim_hook_info        \
+		_zephyr_shim_hook_##type##_list_end[];
+FOR_EACH(HOOK_LIST_EXTERNS, (), HOOK_TYPES_LIST)
+
+#define HOOK_LIST_ENTRY(type)                                   \
+	[type] = {                                              \
+		.start = _zephyr_shim_hook_##type##_list_start, \
+		.end = _zephyr_shim_hook_##type##_list_end,     \
+	}
+static const struct zephyr_shim_hook_list hook_registry[] = { FOR_EACH(
+	HOOK_LIST_ENTRY, (, ), HOOK_TYPES_LIST) };
+BUILD_ASSERT(ARRAY_SIZE(hook_registry) == HOOK_TYPE_COUNT,
+	     "All defined hook types must be represented in hook_registry");
+BUILD_ASSERT(NUM_VA_ARGS_LESS_1(HOOK_TYPES_LIST) + 1 == HOOK_TYPE_COUNT,
+	     "At least one hook type is missing from HOOK_TYPES_LIST");
+
+static void hook_second_work(struct k_work *work);
+static void hook_tick_work(struct k_work *work);
+
+static K_WORK_DELAYABLE_DEFINE(hook_seconds_work_data, hook_second_work);
+static K_WORK_DELAYABLE_DEFINE(hook_ticks_work_data, hook_tick_work);
+
+static void work_queue_error(const void *data, int rv)
+{
+	cprints(CC_HOOK,
+		"Warning: deferred call not submitted, "
+		"deferred_data=0x%p, err=%d",
+		data, rv);
+}
+
+static void hook_second_work(struct k_work *work)
+{
+	int rv;
+
+	hook_notify(HOOK_SECOND);
+
+	rv = k_work_reschedule(&hook_seconds_work_data, K_SECONDS(1));
+	if (rv < 0)
+		work_queue_error(&hook_seconds_work_data, rv);
+}
+
+static void hook_tick_work(struct k_work *work)
+{
+	int rv;
+
+	hook_notify(HOOK_TICK);
+
+	rv = k_work_reschedule(&hook_ticks_work_data,
+			       K_USEC(HOOK_TICK_INTERVAL));
+	if (rv < 0)
+		work_queue_error(&hook_ticks_work_data, rv);
+}
+
+static void check_hook_task_priority(void)
+{
+	k_tid_t thread = &k_sys_work_q.thread;
+
+	/*
+	 * Numerically lower priorities take precedence, so verify the hook
+	 * related threads cannot preempt any of the shimmed tasks.
+	 */
+	if (k_thread_priority_get(thread) < (TASK_ID_COUNT - 1))
+		cprintf(CC_HOOK,
+			"ERROR: %s has priority %d but must be >= %d\n",
+			k_thread_name_get(thread),
+			k_thread_priority_get(thread), (TASK_ID_COUNT - 1));
+}
+DECLARE_HOOK(HOOK_INIT, check_hook_task_priority, HOOK_PRIO_FIRST);
+
+static int zephyr_shim_setup_hooks(void)
+{
+	int rv;
+
+	/* Startup the HOOK_TICK and HOOK_SECOND recurring work */
+	rv = k_work_reschedule(&hook_seconds_work_data, K_SECONDS(1));
+	if (rv < 0)
+		work_queue_error(&hook_seconds_work_data, rv);
+
+	rv = k_work_reschedule(&hook_ticks_work_data,
+			       K_USEC(HOOK_TICK_INTERVAL));
+	if (rv < 0)
+		work_queue_error(&hook_ticks_work_data, rv);
+
+	return 0;
+}
+
+SYS_INIT(zephyr_shim_setup_hooks, APPLICATION, 1);
+
+void hook_notify(enum hook_type type)
+{
+	const struct zephyr_shim_hook_info *start = hook_registry[type].start;
+	const struct zephyr_shim_hook_info *end = hook_registry[type].end;
+	int last_prio = HOOK_PRIO_FIRST - 1;
+
+	__ASSERT(type >= 0 && type < HOOK_TYPE_COUNT,
+		 "hook type %d is out of range (maximum hook_type value %d)",
+		 type, HOOK_TYPE_COUNT);
+
+	while (1) {
+		/*
+		 * Find the lowest priority that is larger than the last pass'
+		 * priority. That is, the next highest uncalled priority.
+		 */
+		int prio = INT_MAX;
+
+		for (const struct zephyr_shim_hook_info *p = start; p != end;
+		     p++) {
+			__ASSERT(
+				IN_RANGE(p->priority, HOOK_PRIO_FIRST,
+					 HOOK_PRIO_LAST),
+				"Hook priority %d (handler %p) is out of range",
+				p->priority, p->routine);
+			if (p->priority > last_prio)
+				prio = MIN(prio, p->priority);
+		}
+
+		if (prio == INT_MAX) {
+			/* No more handlers of higher priority */
+			break;
+		}
+		last_prio = prio;
+
+		/* Call each handler with the located priority */
+		for (const struct zephyr_shim_hook_info *p = start; p != end;
+		     p++) {
+			if (p->priority == prio)
+				p->routine();
+		}
+	};
+}
+
+int hook_call_deferred(const struct deferred_data *data, int us)
+{
+	struct k_work_delayable *work = data->work;
+	int rv = 0;
+
+	if (us == -1) {
+		k_work_cancel_delayable(work);
+	} else if (us >= 0) {
+		rv = k_work_reschedule(work, K_USEC(us));
+		if (rv < 0) {
+			work_queue_error(data, rv);
+		}
+	} else {
+		return EC_ERROR_PARAM2;
+	}
+
+	return rv >= 0 ? EC_SUCCESS : rv;
+}
+
+/*
+ * Shims for interconnecting AP power sequence events with legacy hooks.
+ * Depending on whether the power sequence code is running in zephyr or
+ * not, a shim is setup to send events either from the legacy hooks to
+ * the AP power event callbacks, or vice versa.
+ */
+#ifdef CONFIG_AP_PWRSEQ
+
+/*
+ * Callback handler, dispatch to hooks
+ */
+static void ev_handler(struct ap_power_ev_callback *cb,
+		       struct ap_power_ev_data data)
+{
+	switch (data.event) {
+	default:
+		break;
+
+#define CASE_HOOK(h)                           \
+	case AP_POWER_##h:                     \
+		hook_notify(HOOK_CHIPSET_##h); \
+		break
+
+		CASE_HOOK(PRE_INIT);
+		CASE_HOOK(STARTUP);
+		CASE_HOOK(RESUME);
+		CASE_HOOK(SUSPEND);
+#if CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK
+		CASE_HOOK(RESUME_INIT);
+		CASE_HOOK(SUSPEND_COMPLETE);
+#endif
+		CASE_HOOK(SHUTDOWN);
+		CASE_HOOK(SHUTDOWN_COMPLETE);
+		CASE_HOOK(HARD_OFF);
+		CASE_HOOK(RESET);
+	}
+}
+
+/*
+ * Events are received from the AP power event system and sent to the hooks.
+ */
+static int zephyr_shim_ap_power_event(void)
+{
+	static struct ap_power_ev_callback cb;
+
+	/*
+	 * Register for all events.
+	 */
+	ap_power_ev_init_callback(
+		&cb, ev_handler,
+		AP_POWER_PRE_INIT | AP_POWER_STARTUP | AP_POWER_RESUME |
+			AP_POWER_SUSPEND |
+#if CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK
+			AP_POWER_RESUME_INIT | AP_POWER_SUSPEND_COMPLETE |
+#endif
+			AP_POWER_SHUTDOWN | AP_POWER_SHUTDOWN_COMPLETE |
+			AP_POWER_HARD_OFF | AP_POWER_RESET);
+	ap_power_ev_add_callback(&cb);
+	return 0;
+}
+
+SYS_INIT(zephyr_shim_ap_power_event, APPLICATION, 1);
+#else /* !CONFIG_AP_PWRSEQ */
+
+/*
+ * Events received from the hooks and sent to the AP power event callbacks.
+ */
+#define EV_HOOK(h)                                        \
+	static void hook_##h(void)                        \
+	{                                                 \
+		ap_power_ev_send_callbacks(AP_POWER_##h); \
+	}                                                 \
+	DECLARE_HOOK(HOOK_CHIPSET_##h, hook_##h, HOOK_PRIO_DEFAULT)
+
+EV_HOOK(PRE_INIT);
+EV_HOOK(STARTUP);
+EV_HOOK(RESUME);
+EV_HOOK(SUSPEND);
+#if CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK
+EV_HOOK(RESUME_INIT);
+EV_HOOK(SUSPEND_COMPLETE);
+#endif
+EV_HOOK(SHUTDOWN);
+EV_HOOK(SHUTDOWN_COMPLETE);
+EV_HOOK(HARD_OFF);
+EV_HOOK(RESET);
+#endif /* !CONFIG_AP_PWRSEQ */
diff --git a/zephyr/shim/src/host_command.c b/zephyr/shim/src/host_command.c
new file mode 100644
index 0000000000..5205a1585f
--- /dev/null
+++ b/zephyr/shim/src/host_command.c
@@ -0,0 +1,29 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "host_command.h"
+#include "task.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/sys/iterable_sections.h>
+
+struct host_command *zephyr_find_host_command(int command)
+{
+	STRUCT_SECTION_FOREACH(host_command, cmd)
+	{
+		if (cmd->command == command)
+			return cmd;
+	}
+
+	return NULL;
+}
+
+void host_command_main(void)
+{
+	k_thread_priority_set(get_main_thread(),
+			      EC_TASK_PRIORITY(EC_TASK_HOSTCMD_PRIO));
+	k_thread_name_set(get_main_thread(), "HOSTCMD");
+	host_command_task(NULL);
+}
diff --git a/zephyr/shim/src/hwtimer.c b/zephyr/shim/src/hwtimer.c
index 85c72c5c59..09082b05f1 100644
--- a/zephyr/shim/src/hwtimer.c
+++ b/zephyr/shim/src/hwtimer.c
@@ -1,13 +1,13 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <kernel.h>
+#include "hwtimer.h"
+
 #include <stdint.h>
-#include <zephyr.h>
 
-#include "hwtimer.h"
+#include <zephyr/kernel.h>
 
 uint64_t __hw_clock_source_read64(void)
 {
@@ -23,7 +23,7 @@ uint32_t __hw_clock_event_get(void)
 	return 0;
 }
 
-void udelay(unsigned us)
+void udelay(unsigned int us)
 {
 	k_busy_wait(us);
 }
diff --git a/zephyr/shim/src/i2c.c b/zephyr/shim/src/i2c.c
new file mode 100644
index 0000000000..4a354b9dc9
--- /dev/null
+++ b/zephyr/shim/src/i2c.c
@@ -0,0 +1,145 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "i2c.h"
+#include "i2c/i2c.h"
+
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/sys/util.h>
+
+/*
+ * Initialize device bindings in i2c_devices.
+ * This macro should be called from within DT_FOREACH_CHILD.
+ */
+#define INIT_DEV_BINDING(i2c_port_id) \
+	[I2C_PORT_BUS(i2c_port_id)] = DEVICE_DT_GET(i2c_port_id),
+
+#define INIT_REMOTE_PORTS(id) [I2C_PORT(id)] = DT_PROP_OR(id, remote_port, -1),
+
+#define I2C_PORT_FLAGS(id)                                                     \
+	COND_CODE_1(DT_PROP(id, dynamic_speed), (I2C_PORT_FLAG_DYNAMIC_SPEED), \
+		    (0))
+
+#define I2C_PORT_INIT(id)                    \
+	{                                    \
+		.port = I2C_PORT(id),        \
+		.flags = I2C_PORT_FLAGS(id), \
+	},
+/*
+ * Long term we will not need these, for now they're needed to get things to
+ * build since these extern symbols are usually defined in
+ * board/${BOARD}/board.c.
+ *
+ * Since all the ports will eventually be handled by device tree. This will
+ * be removed at that point.
+ */
+const struct i2c_port_t i2c_ports[] = { DT_FOREACH_CHILD_STATUS_OKAY(
+	NAMED_I2C_PORTS_NODE, I2C_PORT_INIT) };
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+static const int i2c_remote_ports[I2C_PORT_COUNT] = {
+	DT_FOREACH_CHILD_STATUS_OKAY(NAMED_I2C_PORTS_NODE, INIT_REMOTE_PORTS)
+};
+
+static const struct device *i2c_devices[I2C_PORT_COUNT] = { I2C_FOREACH_PORT(
+	INIT_DEV_BINDING) };
+
+const struct device *i2c_get_device_for_port(const int port)
+{
+	if (port < 0 || port >= I2C_PORT_COUNT)
+		return NULL;
+	return i2c_devices[port];
+}
+
+int i2c_get_port_from_remote_port(int remote_port)
+{
+	for (int port = 0; port < I2C_PORT_COUNT; port++) {
+		if (i2c_remote_ports[port] == remote_port)
+			return port;
+	}
+
+	/*
+	 * Remote port is not defined, return 1:1 mapping to support TCPC
+	 * firmware updates, which always query the EC for the correct I2C
+	 * port number.
+	 */
+	return remote_port;
+}
+
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_I2C_PORTMAP
+static int command_i2c_portmap(int argc, const char **argv)
+{
+	int i;
+
+	if (argc > 1) {
+		return EC_ERROR_PARAM_COUNT;
+	}
+
+	ccprintf("Zephyr remote I2C ports (%d):\n", I2C_PORT_COUNT);
+	for (i = 0; i < I2C_PORT_COUNT; i++) {
+		ccprintf("  %d : %d\n", i, i2c_remote_ports[i]);
+	}
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(i2c_portmap, command_i2c_portmap, NULL,
+			"Show I2C port mapping");
+#endif /* CONFIG_PLATFORM_EC_CONSOLE_CMD_I2C_PORTMAP */
+
+int chip_i2c_set_freq(int port, enum i2c_freq freq)
+{
+	uint32_t dev_config;
+	uint32_t speed;
+	int ret = EC_SUCCESS;
+
+	switch (freq) {
+	case I2C_FREQ_100KHZ:
+		speed = I2C_SPEED_STANDARD;
+		break;
+	case I2C_FREQ_400KHZ:
+		speed = I2C_SPEED_FAST;
+		break;
+	case I2C_FREQ_1000KHZ:
+		speed = I2C_SPEED_FAST_PLUS;
+		break;
+	default:
+		return EC_ERROR_INVAL;
+	}
+
+	ret = i2c_get_config(i2c_get_device_for_port(port), &dev_config);
+	if (!ret) {
+		dev_config &= ~I2C_SPEED_MASK;
+		dev_config |= I2C_SPEED_SET(speed);
+		ret = i2c_configure(i2c_get_device_for_port(port), dev_config);
+	}
+
+	return ret;
+}
+
+enum i2c_freq chip_i2c_get_freq(int port)
+{
+	uint32_t dev_config;
+	int ret = EC_SUCCESS;
+	const struct device *dev = i2c_get_device_for_port(port);
+
+	if (dev == NULL)
+		return I2C_FREQ_COUNT;
+
+	ret = i2c_get_config(dev, &dev_config);
+
+	if (ret)
+		return I2C_FREQ_COUNT;
+
+	switch (I2C_SPEED_GET(dev_config)) {
+	case I2C_SPEED_STANDARD:
+		return I2C_FREQ_100KHZ;
+	case I2C_SPEED_FAST:
+		return I2C_FREQ_400KHZ;
+	case I2C_SPEED_FAST_PLUS:
+		return I2C_FREQ_1000KHZ;
+	default:
+		return I2C_FREQ_COUNT;
+	}
+}
diff --git a/zephyr/shim/src/ioex.c b/zephyr/shim/src/ioex.c
new file mode 100644
index 0000000000..da8a1ea05a
--- /dev/null
+++ b/zephyr/shim/src/ioex.c
@@ -0,0 +1,55 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifdef __REQUIRE_ZEPHYR_GPIOS__
+#undef __REQUIRE_ZEPHYR_GPIOS__
+#endif
+#include "common.h"
+#include "ioexpander.h"
+
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(ioex_shim, LOG_LEVEL_ERR);
+
+int ioex_init(int ioex)
+{
+	const struct ioexpander_drv *drv = ioex_config[ioex].drv;
+	int rv;
+
+	if (ioex_config[ioex].flags & IOEX_FLAGS_INITIALIZED)
+		return EC_SUCCESS;
+
+	if (drv->init != NULL) {
+		rv = drv->init(ioex);
+		if (rv != EC_SUCCESS)
+			return rv;
+	}
+
+	ioex_config[ioex].flags |= IOEX_FLAGS_INITIALIZED;
+
+	return EC_SUCCESS;
+}
+
+static int ioex_init_default(void)
+{
+	int ret;
+	int i;
+
+	for (i = 0; i < CONFIG_IO_EXPANDER_PORT_COUNT; i++) {
+		/* IO Expander has been initialized, skip re-initializing */
+		if (ioex_config[i].flags &
+		    (IOEX_FLAGS_INITIALIZED | IOEX_FLAGS_DEFAULT_INIT_DISABLED))
+			continue;
+
+		ret = ioex_init(i);
+		if (ret)
+			LOG_ERR("Can't initialize ioex %d", i);
+	}
+
+	return 0;
+}
+SYS_INIT(ioex_init_default, POST_KERNEL, CONFIG_PLATFORM_EC_IOEX_INIT_PRIORITY);
diff --git a/zephyr/shim/src/ioex_drv.c b/zephyr/shim/src/ioex_drv.c
new file mode 100644
index 0000000000..98f67a4459
--- /dev/null
+++ b/zephyr/shim/src/ioex_drv.c
@@ -0,0 +1,386 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifdef __REQUIRE_ZEPHYR_GPIOS__
+#undef __REQUIRE_ZEPHYR_GPIOS__
+#endif
+#include "common.h"
+#include "config.h"
+/* Include drivers if enabled */
+#ifdef CONFIG_PLATFORM_EC_IOEX_IT8801
+#include "driver/ioexpander/it8801.h"
+#endif
+#ifdef CONFIG_PLATFORM_EC_IOEX_PCA9675
+#include "driver/ioexpander/pca9675.h"
+#endif
+#ifdef CONFIG_PLATFORM_EC_IOEX_PCAL6408
+#include "driver/ioexpander/pcal6408.h"
+#endif
+#ifdef CONFIG_PLATFORM_EC_IOEX_TCA64XXA
+#include "driver/ioexpander/tca64xxa.h"
+#endif
+#ifdef CONFIG_PLATFORM_EC_IOEX_CCGXXF
+#include "driver/tcpm/ccgxxf.h"
+#endif
+#ifdef CONFIG_PLATFORM_EC_IOEX_NCT38XX
+#include "driver/tcpm/nct38xx.h"
+#endif
+#include "gpio.h"
+#include "i2c.h"
+#include "ioexpander.h"
+
+#include <errno.h>
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/gpio/gpio_utils.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/sys/util.h>
+
+#define DT_DRV_COMPAT cros_ioex_port
+#define DT_DRV_COMPAT_CHIP cros_ioex_chip
+
+LOG_MODULE_REGISTER(cros_ioex_port, CONFIG_GPIO_LOG_LEVEL);
+
+struct ioex_drv_data {
+	const struct device *dev;
+	int ioex;
+	int port;
+
+	sys_slist_t callbacks;
+	struct k_work worker;
+
+	const struct device *int_gpio_dev;
+	gpio_pin_t int_gpio_pin;
+	gpio_flags_t int_gpio_flags;
+	struct gpio_callback int_gpio_callback;
+	gpio_port_value_t cached_values;
+	gpio_port_value_t pin_trig_edge_rising;
+	gpio_port_value_t pin_trig_edge_falling;
+	gpio_port_value_t pin_trig_level_zero;
+	gpio_port_value_t pin_trig_level_one;
+};
+
+static int shim_ioex_pin_configure(const struct device *dev, gpio_pin_t pin,
+				   gpio_flags_t flags)
+{
+	const struct ioexpander_config_t *cfg = dev->config;
+	struct ioex_drv_data *drv_data = dev->data;
+	int res;
+
+	res = cfg->drv->set_flags_by_mask(drv_data->ioex, drv_data->port,
+					  BIT(pin),
+					  convert_from_zephyr_flags(flags));
+	if (res)
+		return -EIO;
+
+	return 0;
+}
+
+static int shim_ioex_port_get_raw(const struct device *dev,
+				  gpio_port_value_t *value)
+{
+	const struct ioexpander_config_t *cfg = dev->config;
+	struct ioex_drv_data *drv_data = dev->data;
+	int res;
+
+	res = cfg->drv->get_port(drv_data->ioex, drv_data->port, value);
+	if (res)
+		return -EIO;
+
+	return 0;
+}
+
+static int shim_ioex_port_set_masked_raw(const struct device *dev,
+					 gpio_port_pins_t mask,
+					 gpio_port_value_t value)
+{
+	const struct ioexpander_config_t *cfg = dev->config;
+	struct ioex_drv_data *drv_data = dev->data;
+	int res;
+
+	res = cfg->drv->set_level(drv_data->ioex, drv_data->port, mask, value);
+	if (res)
+		return -EIO;
+
+	return 0;
+}
+
+static int shim_ioex_port_set_bits_raw(const struct device *dev,
+				       gpio_port_pins_t pins)
+{
+	const struct ioexpander_config_t *cfg = dev->config;
+	struct ioex_drv_data *drv_data = dev->data;
+	int res;
+
+	res = cfg->drv->set_level(drv_data->ioex, drv_data->port, pins, 1);
+	if (res)
+		return -EIO;
+
+	return 0;
+}
+
+static int shim_ioex_port_clear_bits_raw(const struct device *dev,
+					 gpio_port_pins_t pins)
+{
+	const struct ioexpander_config_t *cfg = dev->config;
+	struct ioex_drv_data *drv_data = dev->data;
+	int res;
+
+	res = cfg->drv->set_level(drv_data->ioex, drv_data->port, pins, 0);
+	if (res)
+		return -EIO;
+
+	return 0;
+}
+
+static int shim_ioex_port_toggle_bits(const struct device *dev,
+				      gpio_port_pins_t pins)
+{
+	const struct ioexpander_config_t *cfg = dev->config;
+	struct ioex_drv_data *drv_data = dev->data;
+	int to_set;
+	int to_clr;
+	int res;
+	int val;
+
+	res = cfg->drv->get_port(drv_data->ioex, drv_data->port, &val);
+	if (res)
+		return -EIO;
+
+	to_set = (~val) & pins;
+	to_clr = val & pins;
+
+	res = cfg->drv->set_level(drv_data->ioex, drv_data->port, to_set, 1);
+	if (res)
+		return -EIO;
+
+	res = cfg->drv->set_level(drv_data->ioex, drv_data->port, to_clr, 0);
+	if (res)
+		return -EIO;
+
+	return 0;
+}
+
+static int shim_ioex_pin_interrupt_configure(const struct device *dev,
+					     gpio_pin_t pin,
+					     enum gpio_int_mode mode,
+					     enum gpio_int_trig trig)
+{
+	const struct ioexpander_config_t *cfg = dev->config;
+	struct ioex_drv_data *drv_data = dev->data;
+	int flags;
+	int res;
+
+	if (!drv_data->int_gpio_dev) {
+		LOG_ERR("Trying to enable interrupt on ioex %d without "
+			"defined IO expander interrupt pin",
+			drv_data->ioex);
+		return -EIO;
+	}
+
+	res = cfg->drv->get_flags_by_mask(drv_data->ioex, drv_data->port,
+					  BIT(pin), &flags);
+	if (res)
+		return -EIO;
+
+	flags |= convert_from_zephyr_flags(mode | trig);
+
+	res = cfg->drv->set_flags_by_mask(drv_data->ioex, drv_data->port,
+					  BIT(pin), flags);
+	if (res)
+		return -EIO;
+
+	if (!cfg->drv->enable_interrupt) {
+		LOG_ERR("Trying to enable interrupt on ioex %d which doesn't "
+			"support interrupts",
+			drv_data->ioex);
+		return -EIO;
+	}
+
+	res = cfg->drv->enable_interrupt(drv_data->ioex, drv_data->port,
+					 BIT(pin), (mode & GPIO_INT_ENABLE));
+	if (res)
+		return -EIO;
+
+	if (mode == GPIO_INT_MODE_DISABLED) {
+		drv_data->pin_trig_edge_rising &= ~BIT(pin);
+		drv_data->pin_trig_edge_falling &= ~BIT(pin);
+		drv_data->pin_trig_level_zero &= ~BIT(pin);
+		drv_data->pin_trig_level_one &= ~BIT(pin);
+	} else if (mode == GPIO_INT_MODE_EDGE) {
+		if (trig & GPIO_INT_LOW_0)
+			drv_data->pin_trig_edge_falling |= BIT(pin);
+		if (trig & GPIO_INT_HIGH_1)
+			drv_data->pin_trig_edge_rising |= BIT(pin);
+	} else {
+		if (trig & GPIO_INT_LOW_0)
+			drv_data->pin_trig_level_zero |= BIT(pin);
+		if (trig & GPIO_INT_HIGH_1)
+			drv_data->pin_trig_level_one |= BIT(pin);
+	}
+
+	return 0;
+}
+
+static void shim_ioex_isr(const struct device *dev,
+			  struct gpio_callback *callback, gpio_port_pins_t pins)
+{
+	struct ioex_drv_data *drv_data =
+		CONTAINER_OF(callback, struct ioex_drv_data, int_gpio_callback);
+
+	k_work_submit(&drv_data->worker);
+}
+
+static void shim_ioex_worker(struct k_work *worker)
+{
+	struct ioex_drv_data *drv_data =
+		CONTAINER_OF(worker, struct ioex_drv_data, worker);
+	const struct ioexpander_drv *drv = ioex_config[drv_data->ioex].drv;
+	int interrupted_pins_level = 0;
+	int interrupted_pins_edge = 0;
+	int interrupted_pins = 0;
+	int current_values;
+	int changed_pins;
+
+	if (drv_data->ioex < 0) {
+		LOG_ERR("Invalid int IOEX");
+		return;
+	}
+
+	if (!drv->get_port) {
+		LOG_ERR("IO expander doesn't support get_port function");
+		return;
+	}
+
+	if (drv->get_port(drv_data->ioex, drv_data->port, &current_values)) {
+		LOG_ERR("Couldn't get int ioex values");
+		return;
+	}
+
+	changed_pins = current_values ^ drv_data->cached_values;
+
+	/* Edge rising */
+	interrupted_pins_edge |= (changed_pins & current_values) &
+				 drv_data->pin_trig_edge_rising;
+	/* Edge falling */
+	interrupted_pins_edge |= (changed_pins & (~current_values)) &
+				 drv_data->pin_trig_edge_falling;
+	/* Level 1 */
+	interrupted_pins_level |=
+		(current_values & drv_data->pin_trig_level_one);
+	/* Level 0 */
+	interrupted_pins_level |=
+		((~current_values) & drv_data->pin_trig_level_zero);
+
+	interrupted_pins = (interrupted_pins_edge | interrupted_pins_level);
+	gpio_fire_callbacks(&drv_data->callbacks, drv_data->dev,
+			    interrupted_pins);
+
+	drv_data->cached_values = current_values;
+
+	/* Recalling this function will simulate interrupts triggered by
+	 * logic level instead of level change (edge).
+	 * Function will be called repeatedly until the level change to value
+	 * not triggering the interrupt.
+	 */
+	if (interrupted_pins_level)
+		k_work_submit(worker);
+}
+
+static int shim_ioex_init(const struct device *dev)
+{
+	struct ioex_drv_data *drv_data = dev->data;
+
+	drv_data->dev = dev;
+
+	/* IO expander may have specified GPIO pin that should trigger
+	 * interrupt handling routines for signals on this IO expander.
+	 * If this GPIO is specified, it should be configured as interrupt
+	 * pin and should have callback assigned to it.
+	 */
+	if (drv_data->int_gpio_dev) {
+		int res;
+
+		res = gpio_pin_configure(drv_data->int_gpio_dev,
+					 drv_data->int_gpio_pin,
+					 drv_data->int_gpio_flags | GPIO_INPUT);
+		if (res)
+			return -EIO;
+
+		gpio_init_callback(&drv_data->int_gpio_callback, shim_ioex_isr,
+				   BIT(drv_data->int_gpio_pin));
+
+		res = gpio_add_callback(drv_data->int_gpio_dev,
+					&drv_data->int_gpio_callback);
+		if (res)
+			return -EIO;
+
+		k_work_init(&drv_data->worker, shim_ioex_worker);
+	}
+
+	return 0;
+}
+
+static int shim_ioex_manage_callback(const struct device *dev,
+				     struct gpio_callback *callback,
+				     bool enable)
+{
+	struct ioex_drv_data *drv_data = dev->data;
+
+	return gpio_manage_callback(&drv_data->callbacks, callback, enable);
+}
+
+static const struct gpio_driver_api api_table = {
+	.pin_configure = shim_ioex_pin_configure,
+	.port_get_raw = shim_ioex_port_get_raw,
+	.port_set_masked_raw = shim_ioex_port_set_masked_raw,
+	.port_set_bits_raw = shim_ioex_port_set_bits_raw,
+	.port_clear_bits_raw = shim_ioex_port_clear_bits_raw,
+	.port_toggle_bits = shim_ioex_port_toggle_bits,
+	.pin_interrupt_configure = shim_ioex_pin_interrupt_configure,
+	.manage_callback = shim_ioex_manage_callback,
+};
+
+#define IOEX_INIT_CONFIG_ELEM(id)                                    \
+	{                                                            \
+		.i2c_host_port = I2C_PORT(DT_PHANDLE(id, i2c_port)), \
+		.i2c_addr_flags = DT_PROP(id, i2c_addr),             \
+		.drv = &DT_STRING_TOKEN(id, drv),                    \
+		.flags = DT_PROP(id, flags),                         \
+	},
+
+#define IOEX_INIT_DATA(idx)                                                  \
+	{                                                                    \
+		.ioex = IOEXPANDER_ID(DT_PARENT(DT_DRV_INST(idx))),          \
+		.port = DT_REG_ADDR(DT_DRV_INST(idx)),                       \
+		COND_CODE_1(                                                 \
+			DT_NODE_HAS_PROP(DT_PARENT(DT_DRV_INST(idx)),        \
+					 int_gpios),                         \
+			(.int_gpio_dev = DEVICE_DT_GET(DT_PHANDLE(           \
+				 DT_PARENT(DT_DRV_INST(idx)), int_gpios)),   \
+			 .int_gpio_pin = DT_GPIO_PIN(                        \
+				 DT_PARENT(DT_DRV_INST(idx)), int_gpios),    \
+			 .int_gpio_flags = DT_GPIO_FLAGS(                    \
+				 DT_PARENT(DT_DRV_INST(idx)), int_gpios), ), \
+			())                                                  \
+	}
+
+struct ioexpander_config_t ioex_config[] = { DT_FOREACH_STATUS_OKAY(
+	DT_DRV_COMPAT_CHIP, IOEX_INIT_CONFIG_ELEM) };
+
+#define GPIO_PORT_INIT(idx)                                                  \
+	static struct ioex_drv_data ioex_##idx##_data = IOEX_INIT_DATA(idx); \
+	DEVICE_DT_INST_DEFINE(                                               \
+		idx, shim_ioex_init, NULL, &ioex_##idx##_data,               \
+		&ioex_config[IOEXPANDER_ID(DT_PARENT(DT_DRV_INST(idx)))],    \
+		POST_KERNEL, CONFIG_PLATFORM_EC_IOEX_INIT_PRIORITY,          \
+		&api_table);
+
+DT_INST_FOREACH_STATUS_OKAY(GPIO_PORT_INIT)
diff --git a/zephyr/shim/src/ish_system.c b/zephyr/shim/src/ish_system.c
new file mode 100644
index 0000000000..bb98d5b98e
--- /dev/null
+++ b/zephyr/shim/src/ish_system.c
@@ -0,0 +1,107 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "power.h"
+#include "system.h"
+
+int chipset_in_state(int state_mask)
+{
+	return state_mask & CHIPSET_STATE_ON;
+}
+
+test_mockable const char *system_get_chip_vendor(void)
+{
+	return "Intel";
+}
+
+test_mockable const char *system_get_chip_name(void)
+{
+	return "Intel x86";
+}
+
+test_mockable const char *system_get_chip_revision(void)
+{
+	return "";
+}
+
+test_mockable int system_get_bbram(enum system_bbram_idx idx, uint8_t *value)
+{
+	/* This is not applied to ISH, keep to pass build */
+	return EC_ERROR_UNIMPLEMENTED;
+}
+
+/*
+ * CONFIG_PLATFORM_EC_FLASH_CROS and CONFIG_EC_PROTECTED_STORAGE_OFF
+ * are not applicable to ISH.
+ * Below functions are added to pass build requirement.
+ * However do not include this block if CONFIG_ZTEST is enabled; to
+ * avoid duplicate definitions which are in ztest_system.c too.
+ */
+#if !defined(CONFIG_ZTEST)
+#ifndef CONFIG_PLATFORM_EC_FLASH_CROS
+int crec_flash_read(int offset, int size, char *data)
+{
+	return EC_ERROR_INVAL;
+}
+
+uint32_t crec_flash_get_protect(void)
+{
+	return 0;
+}
+#endif
+
+#ifndef CONFIG_EC_PROTECTED_STORAGE_OFF
+uint32_t flash_get_rw_offset(enum ec_image copy)
+{
+	return 0;
+}
+#endif
+#endif /* CONFIG_ZTEST */
+
+test_mockable int system_set_bbram(enum system_bbram_idx idx, uint8_t value)
+{
+	/* This is not applied to ISH, keep to pass build */
+	return EC_ERROR_UNIMPLEMENTED;
+}
+
+test_mockable void system_reset(int flags)
+{
+	__builtin_unreachable();
+}
+
+test_mockable void system_hibernate(uint32_t seconds, uint32_t microseconds)
+{
+	/* This is not applied to ISH, keep to pass build */
+}
+
+int system_get_scratchpad(uint32_t *value)
+{
+	return EC_ERROR_UNIMPLEMENTED;
+}
+
+int system_set_scratchpad(uint32_t value)
+{
+	return EC_ERROR_UNIMPLEMENTED;
+}
+
+void chip_save_reset_flags(uint32_t flags)
+{
+	/* TODO: will add implementation later */
+}
+
+uint32_t chip_read_reset_flags(void)
+{
+	/* TODO: will add implementation later */
+	return EC_RESET_FLAG_POWER_ON;
+}
+
+test_export_static int system_preinitialize(void)
+{
+	system_set_reset_flags(chip_read_reset_flags());
+	return 0;
+}
+
+SYS_INIT(system_preinitialize, PRE_KERNEL_1,
+	 CONFIG_PLATFORM_EC_SYSTEM_PRE_INIT_PRIORITY);
diff --git a/zephyr/shim/src/kb8010_usb_mux.c b/zephyr/shim/src/kb8010_usb_mux.c
new file mode 100644
index 0000000000..0d5febbe82
--- /dev/null
+++ b/zephyr/shim/src/kb8010_usb_mux.c
@@ -0,0 +1,11 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "retimer/kb8010_public.h"
+#include "usbc/usb_muxes.h"
+
+const struct kb8010_control kb8010_controls[] = {
+	USB_MUX_KB8010_CONTROLS_ARRAY
+};
diff --git a/zephyr/shim/src/keyboard_raw.c b/zephyr/shim/src/keyboard_raw.c
new file mode 100644
index 0000000000..73b3c2acaf
--- /dev/null
+++ b/zephyr/shim/src/keyboard_raw.c
@@ -0,0 +1,74 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Functions needed by keyboard scanner module for Chrome EC */
+
+#include "drivers/cros_kb_raw.h"
+#include "keyboard_raw.h"
+
+#include <zephyr/device.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+
+#include <soc.h>
+
+LOG_MODULE_REGISTER(shim_cros_kb_raw, LOG_LEVEL_ERR);
+
+BUILD_ASSERT(DT_HAS_CHOSEN(cros_ec_raw_kb),
+	     "a cros-ec,raw-kb device must be chosen");
+#define cros_kb_raw_dev DEVICE_DT_GET(DT_CHOSEN(cros_ec_raw_kb))
+
+/**
+ * Initialize the raw keyboard interface.
+ */
+void keyboard_raw_init(void)
+{
+	if (!device_is_ready(cros_kb_raw_dev))
+		k_oops();
+
+	LOG_INF("%s", __func__);
+	cros_kb_raw_init(cros_kb_raw_dev);
+}
+
+/**
+ * Finish initialization after task scheduling has started.
+ */
+void keyboard_raw_task_start(void)
+{
+	keyboard_raw_enable_interrupt(1);
+}
+
+/**
+ * Drive the specified column low.
+ */
+test_mockable void keyboard_raw_drive_column(int col)
+{
+	cros_kb_raw_drive_column(cros_kb_raw_dev, col);
+}
+
+/**
+ * Read raw row state.
+ * Bits are 1 if signal is present, 0 if not present.
+ */
+test_mockable int keyboard_raw_read_rows(void)
+{
+	return cros_kb_raw_read_rows(cros_kb_raw_dev);
+}
+
+/**
+ * Enable or disable keyboard interrupts.
+ */
+void keyboard_raw_enable_interrupt(int enable)
+{
+	cros_kb_raw_enable_interrupt(cros_kb_raw_dev, enable);
+}
+
+/**
+ * Enable or disable keyboard alternative function.
+ */
+void keybaord_raw_config_alt(bool enable)
+{
+	cros_kb_raw_config_alt(cros_kb_raw_dev, enable);
+}
diff --git a/zephyr/shim/src/keyscan.c b/zephyr/shim/src/keyscan.c
new file mode 100644
index 0000000000..46bb5fcc7f
--- /dev/null
+++ b/zephyr/shim/src/keyscan.c
@@ -0,0 +1,36 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define DT_DRV_COMPAT cros_ec_keyscan
+
+#include "keyboard_scan.h"
+
+#include <assert.h>
+
+#include <zephyr/kernel.h>
+
+#include <soc.h>
+
+BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
+	     "Exactly one instance of cros-ec,keyscan should be defined.");
+
+/* The keyboard matrix should have at least enough columns for the
+ * standard keyboard with no keypad.
+ */
+BUILD_ASSERT(DT_INST_PROP_LEN(0, actual_key_mask) >= KEYBOARD_COLS_NO_KEYPAD);
+
+/*
+ * Override the default keyscan_config if the board defines a
+ * cros-kb-raw-keyscan node.
+ */
+__override struct keyboard_scan_config keyscan_config = {
+	.output_settle_us = DT_INST_PROP(0, output_settle),
+	.debounce_down_us = DT_INST_PROP(0, debounce_down),
+	.debounce_up_us = DT_INST_PROP(0, debounce_up),
+	.scan_period_us = DT_INST_PROP(0, scan_period),
+	.min_post_scan_delay_us = DT_INST_PROP(0, min_post_scan_delay),
+	.poll_timeout_us = DT_INST_PROP(0, poll_timeout),
+	.actual_key_mask = DT_INST_PROP(0, actual_key_mask),
+};
diff --git a/zephyr/shim/src/led_driver/CMakeLists.txt b/zephyr/shim/src/led_driver/CMakeLists.txt
new file mode 100644
index 0000000000..7f513ed425
--- /dev/null
+++ b/zephyr/shim/src/led_driver/CMakeLists.txt
@@ -0,0 +1,7 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LED_DT      led.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LED_DT_GPIO led_gpio.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LED_DT_PWM  led_pwm.c)
diff --git a/zephyr/shim/src/led_driver/led.c b/zephyr/shim/src/led_driver/led.c
new file mode 100644
index 0000000000..ba1a4d1155
--- /dev/null
+++ b/zephyr/shim/src/led_driver/led.c
@@ -0,0 +1,304 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power and battery LED control.
+ */
+
+#define DT_DRV_COMPAT cros_ec_led_policy
+
+#include "battery.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "chipset.h"
+#include "ec_commands.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "led.h"
+#include "led_common.h"
+#include "power.h"
+#include "system.h"
+#include "util.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(led, LOG_LEVEL_ERR);
+
+BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
+	     "Exactly one instance of cros-ec,led-policy should be defined.");
+
+struct led_color_node_t {
+	struct led_pins_node_t *pins_node;
+	int acc_period;
+};
+
+#define DECLARE_PINS_NODE(id) extern struct led_pins_node_t PINS_NODE(id);
+
+#if CONFIG_PLATFORM_EC_LED_DT_PWM
+DT_FOREACH_CHILD_STATUS_OKAY_VARGS(
+	DT_COMPAT_GET_ANY_STATUS_OKAY(cros_ec_pwm_led_pins), DT_FOREACH_CHILD,
+	DECLARE_PINS_NODE)
+#elif CONFIG_PLATFORM_EC_LED_DT_GPIO
+DT_FOREACH_CHILD_STATUS_OKAY_VARGS(
+	DT_COMPAT_GET_ANY_STATUS_OKAY(cros_ec_gpio_led_pins), DT_FOREACH_CHILD,
+	DECLARE_PINS_NODE)
+#endif
+
+/*
+ * Currently 4 different colors are supported for blinking LED, each of which
+ * can have different periods. Each period slot is the accumulation of previous
+ * periods as described below. Last slot is the total accumulation which is
+ * used as a dividing factor to calculate ticks to switch color
+ * Eg LED_COLOR_1 1 sec, LED_COLOR_2 2 sec, LED_COLOR_3 3 sec, LED_COLOR_4 3 sec
+ * period_1 = 1, period_2 = 1 + 2, period_3 = 1 + 2 + 3, period_4 =1 + 2 + 3 + 3
+ * ticks -> 0, 1, 2, 3, 4, 5, 6, 7, 8, 0, 1, 2 and so on (ticks % 9)
+ * 0 < period_1 -> LED_COLOR_1 for 1 sec
+ * 1, 2 < period_2 -> LED_COLOR_2 for 2 secs
+ * 3, 4, 5 < period_3 -> LED_COLOR_3 for 3 secs
+ * 6, 7, 8 < period_4 -> LED_COLOR_4 for 3 secs
+ */
+#define MAX_COLOR 4
+
+struct node_prop_t {
+	enum led_pwr_state pwr_state;
+	enum power_state chipset_state;
+	int batt_state_mask;
+	int batt_state;
+	int8_t batt_lvl[2];
+	int8_t charge_port;
+	struct led_color_node_t led_colors[MAX_COLOR];
+};
+
+/*
+ * acc_period is the accumulated period value of all color-x children
+ * led_colors[0].acc_period = period value of color-0 node
+ * led_colors[1].acc_period = period value of color-0 + color-1 nodes
+ * led_colors[2].acc_period = period value of color-0 + color-1 + color-2 nodes
+ * and so on. If period prop or color node doesn't exist, period val is 0
+ * It is stored in terms of number of ticks by dividing it with
+ * HOOT_TICK_INTERVAL_MS
+ */
+
+#define PERIOD_VAL(id)                               \
+	COND_CODE_1(DT_NODE_HAS_PROP(id, period_ms), \
+		    (DT_PROP(id, period_ms) / HOOK_TICK_INTERVAL_MS), (0))
+
+#define LED_PERIOD(color_num, state_id) \
+	PERIOD_VAL(DT_CHILD(state_id, color_##color_num))
+
+#define LED_PLUS_PERIOD(color_num, state_id) +LED_PERIOD(color_num, state_id)
+
+#define ACC_PERIOD(color_num, state_id) \
+	(0 LISTIFY(color_num, LED_PLUS_PERIOD, (), state_id))
+
+#define PINS_NODE_ADDR(id) DT_PHANDLE(id, led_color)
+#define LED_COLOR_INIT(color_num, color_num_plus_one, state_id)                \
+	{                                                                      \
+		.pins_node = COND_CODE_1(                                      \
+			DT_NODE_EXISTS(DT_CHILD(state_id, color_##color_num)), \
+			(&PINS_NODE(PINS_NODE_ADDR(                            \
+				DT_CHILD(state_id, color_##color_num)))),      \
+			(NULL)),                                               \
+		.acc_period = ACC_PERIOD(color_num_plus_one, state_id)         \
+	}
+
+/*
+ * Initialize node_array struct with prop listed in dts
+ */
+#define SET_LED_VALUES(state_id)                                              \
+	{ .pwr_state = GET_PROP(state_id, charge_state),                      \
+	  .chipset_state = GET_PROP(state_id, chipset_state),                 \
+	  .batt_state_mask =                                                  \
+		  COND_CODE_1(DT_NODE_HAS_PROP(state_id, batt_state_mask),    \
+			      (DT_PROP(state_id, batt_state_mask)), (-1)),    \
+	  .batt_state = COND_CODE_1(DT_NODE_HAS_PROP(state_id, batt_state),   \
+				    (DT_PROP(state_id, batt_state)), (-1)),   \
+	  .batt_lvl = COND_CODE_1(DT_NODE_HAS_PROP(state_id, batt_lvl),       \
+				  (DT_PROP(state_id, batt_lvl)),              \
+				  ({ -1, -1 })),                              \
+	  .charge_port = COND_CODE_1(DT_NODE_HAS_PROP(state_id, charge_port), \
+				     (DT_PROP(state_id, charge_port)), (-1)), \
+	  .led_colors = {                                                     \
+		  LED_COLOR_INIT(0, 1, state_id),                             \
+		  LED_COLOR_INIT(1, 2, state_id),                             \
+		  LED_COLOR_INIT(2, 3, state_id),                             \
+		  LED_COLOR_INIT(3, 4, state_id),                             \
+	  } },
+
+static const struct node_prop_t node_array[] = { DT_INST_FOREACH_CHILD(
+	0, SET_LED_VALUES) };
+
+test_export_static enum power_state get_chipset_state(void)
+{
+	enum power_state chipset_state = 0;
+
+	/*
+	 * Only covers subset of power states as other states don't
+	 * alter LED behavior
+	 */
+	if (chipset_in_state(CHIPSET_STATE_ON))
+		/* S0 */
+		chipset_state = POWER_S0;
+	else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
+		/* S3 */
+		chipset_state = POWER_S3;
+	else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		/* S5 */
+		chipset_state = POWER_S5;
+
+	return chipset_state;
+}
+
+#define GET_PERIOD(n_idx, c_idx) node_array[n_idx].led_colors[c_idx].acc_period
+#define GET_PIN_NODE(n_idx, c_idx) node_array[n_idx].led_colors[c_idx].pins_node
+
+static void set_color(int node_idx, uint32_t ticks)
+{
+	int color_idx = 0;
+
+	/* If accumulated period value is not 0, it's a blinking LED */
+	if (GET_PERIOD(node_idx, MAX_COLOR - 1) != 0) {
+		/*  Period is accumulated at the last index */
+		ticks = ticks % GET_PERIOD(node_idx, MAX_COLOR - 1);
+	}
+
+	/*
+	 * Period value of 0 indicates solid LED color (non-blinking)
+	 * In case of dual port battery LEDs, period value of 0 is
+	 * also used to turn-off non-active port LED
+	 * Nodes with period value of 0 strictly need to be listed before
+	 * nodes with non-zero period values as we are accumulating the
+	 * period at each node.
+	 *
+	 * TODO: Remove the strict sequence requirement for listing the
+	 * zero-period value nodes.
+	 */
+	for (color_idx = 0; color_idx < MAX_COLOR; color_idx++) {
+		struct led_pins_node_t *pins_node =
+			GET_PIN_NODE(node_idx, color_idx);
+		int period = GET_PERIOD(node_idx, color_idx);
+
+		if (pins_node == NULL)
+			break; /* No more valid color nodes, break here */
+
+		if (!led_auto_control_is_enabled(pins_node->led_id))
+			break; /* Auto control is disabled */
+
+		/*
+		 * Period value that we use here is in terms of number
+		 * of ticks stored during initialization of the struct
+		 */
+		if (period == 0)
+			led_set_color_with_node(pins_node);
+		else if (ticks < period) {
+			led_set_color_with_node(pins_node);
+			break;
+		}
+	}
+}
+
+static int match_node(int node_idx)
+{
+	/* Check if this node depends on power state */
+	if (node_array[node_idx].pwr_state != LED_PWRS_UNCHANGE) {
+		enum led_pwr_state pwr_state = led_pwr_get_state();
+
+		if (node_array[node_idx].pwr_state != pwr_state)
+			return -1;
+
+		/* Check if this node depends on charge port */
+		if (node_array[node_idx].charge_port != -1) {
+			int port = charge_manager_get_active_charge_port();
+
+			if (node_array[node_idx].charge_port != port)
+				return -1;
+		}
+	}
+
+	/* Check if this node depends on chipset state */
+	if (node_array[node_idx].chipset_state != 0) {
+		enum power_state chipset_state = get_chipset_state();
+
+		if (node_array[node_idx].chipset_state != chipset_state)
+			return -1;
+	}
+
+	/* check if this node depends on battery status */
+	if (node_array[node_idx].batt_state_mask != -1) {
+		int batt_state;
+
+		battery_status(&batt_state);
+		if ((node_array[node_idx].batt_state_mask & batt_state) !=
+		    (node_array[node_idx].batt_state_mask &
+		     node_array[node_idx].batt_state))
+			return -1;
+	}
+
+	/* Check if this node depends on battery level */
+	if (node_array[node_idx].batt_lvl[0] != -1) {
+		int curr_batt_lvl =
+			DIV_ROUND_NEAREST(charge_get_display_charge(), 10);
+
+		if ((curr_batt_lvl < node_array[node_idx].batt_lvl[0]) ||
+		    (curr_batt_lvl > node_array[node_idx].batt_lvl[1]))
+			return -1;
+	}
+
+	/* We found the node that matches the current system state */
+	return node_idx;
+}
+
+static void board_led_set_color(void)
+{
+	static uint32_t ticks;
+	bool found_node = false;
+
+	ticks++;
+
+	/*
+	 * Find all the nodes that match the current state of the system and
+	 * set color for these nodes. Depending on the policy defined in
+	 * led.dts, a node could depend on power-state, chipset-state, extra
+	 * flags like battery percentage etc.
+	 * We must find at least one node that indicates the LED Behavior for
+	 * current system state.
+	 */
+	for (int i = 0; i < ARRAY_SIZE(node_array); i++) {
+		if (match_node(i) != -1) {
+			found_node = true;
+			set_color(i, ticks);
+		}
+	}
+
+	if (!found_node)
+		LOG_ERR("Node with matching prop not found");
+}
+
+/* Called by hook task every HOOK_TICK_INTERVAL_MS */
+static void led_tick(void)
+{
+	board_led_set_color();
+}
+DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
+
+void led_control(enum ec_led_id led_id, enum ec_led_state state)
+{
+	enum led_color color;
+
+	if ((led_id != EC_LED_ID_RECOVERY_HW_REINIT_LED) &&
+	    (led_id != EC_LED_ID_SYSRQ_DEBUG_LED))
+		return;
+
+	if (state == LED_STATE_RESET) {
+		led_auto_control(EC_LED_ID_BATTERY_LED, 1);
+		board_led_set_color();
+		return;
+	}
+
+	color = state ? LED_BLUE : LED_OFF;
+
+	led_auto_control(EC_LED_ID_BATTERY_LED, 0);
+
+	led_set_color(color, led_id);
+}
diff --git a/zephyr/shim/src/led_driver/led.h b/zephyr/shim/src/led_driver/led.h
new file mode 100644
index 0000000000..f1d0110a8d
--- /dev/null
+++ b/zephyr/shim/src/led_driver/led.h
@@ -0,0 +1,120 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_LED_H__
+#define __CROS_EC_LED_H__
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/pwm.h>
+
+#define PINS_NODE(id) DT_CAT(PIN_NODE_, id)
+#define PINS_ARRAY(id) DT_CAT(PINS_ARRAY_, id)
+
+/*
+ * Return string-token if the property exists, otherwise return 0
+ */
+#define GET_PROP(id, prop)                      \
+	COND_CODE_1(DT_NODE_HAS_PROP(id, prop), \
+		    (DT_STRING_UPPER_TOKEN(id, prop)), (0))
+
+/*
+ * Return string-token if the property exists, otherwise return
+ * EC_LED_COLOR_INVALID.
+ */
+#define GET_COLOR_PROP_NVE(id, prop)            \
+	COND_CODE_1(DT_NODE_HAS_PROP(id, prop), \
+		    (DT_STRING_UPPER_TOKEN(id, prop)), (EC_LED_COLOR_INVALID))
+
+#define LED_ENUM(id, enum_name) DT_STRING_TOKEN(id, enum_name)
+#define LED_ENUM_WITH_COMMA(id, enum_name)           \
+	COND_CODE_1(DT_NODE_HAS_PROP(id, enum_name), \
+		    (LED_ENUM(id, enum_name), ), ())
+
+enum led_color {
+	LED_OFF,
+	LED_RED,
+	LED_GREEN,
+	LED_BLUE,
+	LED_YELLOW,
+	LED_WHITE,
+	LED_AMBER,
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
+};
+
+/*
+ * Struct defining LED GPIO pin and value to set.
+ */
+struct gpio_pin_t {
+	enum gpio_signal signal;
+	int val;
+};
+
+/*
+ * Struct defining LED PWM pin and duty cycle to set.
+ */
+struct pwm_pin_t {
+	struct pwm_dt_spec pwm;
+	uint32_t pulse_ns; /* PWM Duty cycle ns */
+};
+
+/*
+ * Pin node contains LED color and array of gpio/pwm pins
+ * to alter in order to enable the given color.
+ */
+struct led_pins_node_t {
+	/*
+	 * Link between color and pins node. Only used to support
+	 * ectool functionality.
+	 */
+	int led_color;
+
+	/*
+	 * Link between color and pins node. Only used to support
+	 * ectool functionality.
+	 */
+	enum ec_led_id led_id;
+
+	/* Brightness Range color, only used to support ectool functionality */
+	enum ec_led_colors br_color;
+
+#if CONFIG_PLATFORM_EC_LED_DT_GPIO
+	/* Array of GPIO pins to set to enable particular color */
+	struct gpio_pin_t *gpio_pins;
+#endif
+
+#if CONFIG_PLATFORM_EC_LED_DT_PWM
+	/* Array of PWM pins to set to enable particular color */
+	struct pwm_pin_t *pwm_pins;
+#endif
+
+	/* Number of pins per color */
+	uint8_t pins_count;
+};
+
+/**
+ * Set LED color using color enum
+ *
+ * @param color		LED Color to enable
+ * @param led_id	LED ID to set the color for
+ */
+void led_set_color(enum led_color color, enum ec_led_id led_id);
+
+/**
+ * Set LED color using pins node
+ *
+ * @param *pins_node	Pins node to enable the color corresponding
+ *			to the node.
+ */
+void led_set_color_with_node(const struct led_pins_node_t *pins_node);
+
+#ifdef TEST_BUILD
+const struct led_pins_node_t *led_get_node(enum led_color color,
+					   enum ec_led_id led_id);
+
+enum power_state get_chipset_state(void);
+#endif /* TEST_BUILD */
+
+#endif /* __CROS_EC_LED_H__ */
diff --git a/zephyr/shim/src/led_driver/led_gpio.c b/zephyr/shim/src/led_driver/led_gpio.c
new file mode 100644
index 0000000000..2419663859
--- /dev/null
+++ b/zephyr/shim/src/led_driver/led_gpio.c
@@ -0,0 +1,147 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * GPIO LED control.
+ */
+
+#define DT_DRV_COMPAT cros_ec_gpio_led_pins
+
+#include "ec_commands.h"
+#include "led.h"
+#include "util.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(gpio_led, LOG_LEVEL_ERR);
+
+BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
+	     "Exactly one instance of cros-ec,gpio-led-pins should be defined.");
+
+#define SET_PIN(node_id, prop, i)                                      \
+	{ .signal = GPIO_SIGNAL(                                       \
+		  DT_PHANDLE_BY_IDX(DT_PARENT(node_id), led_pins, i)), \
+	  .val = DT_PROP_BY_IDX(node_id, prop, i) },
+
+#define SET_GPIO_PIN(node_id) \
+	{ DT_FOREACH_PROP_ELEM(node_id, led_values, SET_PIN) };
+
+#define GEN_PINS_ARRAY(id) struct gpio_pin_t PINS_ARRAY(id)[] = SET_GPIO_PIN(id)
+
+DT_INST_FOREACH_CHILD_STATUS_OKAY_VARGS(0, DT_FOREACH_CHILD, GEN_PINS_ARRAY)
+
+#define SET_PIN_NODE(node_id)                                \
+	{ .led_color = GET_PROP(node_id, led_color),         \
+	  .led_id = GET_PROP(DT_PARENT(node_id), led_id),    \
+	  .br_color = GET_COLOR_PROP_NVE(node_id, br_color), \
+	  .gpio_pins = PINS_ARRAY(node_id),                  \
+	  .pins_count = DT_PROP_LEN(node_id, led_values) };
+
+/*
+ * Initialize led_pins_node_t struct for each pin node defined
+ */
+#define GEN_PINS_NODES(id) \
+	const struct led_pins_node_t PINS_NODE(id) = SET_PIN_NODE(id)
+
+DT_INST_FOREACH_CHILD_STATUS_OKAY_VARGS(0, DT_FOREACH_CHILD, GEN_PINS_NODES)
+
+/*
+ * Array of pointers to each pin node
+ */
+#define PINS_NODE_PTR(id) &PINS_NODE(id),
+const struct led_pins_node_t *pins_node[] = {
+	DT_INST_FOREACH_CHILD_STATUS_OKAY_VARGS(0, DT_FOREACH_CHILD,
+						PINS_NODE_PTR)
+};
+
+/*
+ * Set all the GPIO pins defined in the node to the defined value,
+ * to enable the color.
+ */
+void led_set_color_with_node(const struct led_pins_node_t *pins_node)
+{
+	for (int j = 0; j < pins_node->pins_count; j++) {
+		gpio_pin_set_dt(
+			gpio_get_dt_spec(pins_node->gpio_pins[j].signal),
+			pins_node->gpio_pins[j].val);
+	}
+}
+
+/*
+ * Iterate through LED pins nodes to find the color matching node.
+ */
+void led_set_color(enum led_color color, enum ec_led_id led_id)
+{
+	for (int i = 0; i < ARRAY_SIZE(pins_node); i++) {
+		if ((pins_node[i]->led_color == color) &&
+		    (pins_node[i]->led_id == led_id)) {
+			led_set_color_with_node(pins_node[i]);
+			break;
+		}
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	for (int i = 0; i < ARRAY_SIZE(pins_node); i++) {
+		int br_color = pins_node[i]->br_color;
+
+		if (br_color != EC_LED_COLOR_INVALID)
+			brightness_range[br_color] = 1;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	bool color_set = false;
+
+	for (int i = 0; i < ARRAY_SIZE(pins_node); i++) {
+		int br_color = pins_node[i]->br_color;
+
+		if (br_color != EC_LED_COLOR_INVALID &&
+		    brightness[br_color] != 0) {
+			color_set = true;
+			led_set_color(pins_node[i]->led_color, led_id);
+		}
+	}
+
+	/* If no color was set, turn off the LED */
+	if (!color_set)
+		led_set_color(LED_OFF, led_id);
+
+	return EC_SUCCESS;
+}
+
+__override int led_is_supported(enum ec_led_id led_id)
+{
+	static int supported_leds = -1;
+
+	if (supported_leds == -1) {
+		supported_leds = 0;
+
+		for (int i = 0; i < ARRAY_SIZE(pins_node); i++)
+			supported_leds |= (1 << pins_node[i]->led_id);
+	}
+
+	return ((1 << (int)led_id) & supported_leds);
+}
+
+#ifdef TEST_BUILD
+const struct led_pins_node_t *led_get_node(enum led_color color,
+					   enum ec_led_id led_id)
+{
+	const struct led_pins_node_t *pin_node = NULL;
+
+	for (int i = 0; i < ARRAY_SIZE(pins_node); i++) {
+		if (pins_node[i]->led_id == led_id &&
+		    pins_node[i]->led_color == color) {
+			pin_node = pins_node[i];
+			break;
+		}
+	}
+
+	return pin_node;
+}
+#endif /* TEST_BUILD */
diff --git a/zephyr/shim/src/led_driver/led_pwm.c b/zephyr/shim/src/led_driver/led_pwm.c
new file mode 100644
index 0000000000..a747c3d3b9
--- /dev/null
+++ b/zephyr/shim/src/led_driver/led_pwm.c
@@ -0,0 +1,158 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * PWM LED control.
+ */
+
+#define DT_DRV_COMPAT cros_ec_pwm_led_pins
+
+#include "ec_commands.h"
+#include "led.h"
+#include "util.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/pwm.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(pwm_led, LOG_LEVEL_ERR);
+
+BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
+	     "Exactly one instance of cros-ec,pwm-led-pins should be defined.");
+
+/*
+ * Period in ns from frequency(Hz) defined in pins node
+ * period in sec = 1/freq
+ * period in nsec = (1*nsec_per_sec)/freq
+ * This value is also used calculate duty_cycle in ns (pulse_ns below).
+ * Duty cycle in perct defined in pin node is used to calculate pulse_ns
+ * pulse_ns = (period_ns*duty_cycle_in_perct)/100
+ * e.g. freq = 500 Hz, period_ns = 1000000000/500 = 2000000ns
+ * duty_cycle = 50 %, pulse_ns  = (2000000*50)/100 = 1000000ns
+ */
+
+#define SET_PIN(node_id, prop, i)                                            \
+	{                                                                    \
+		.pwm = PWM_DT_SPEC_GET(                                      \
+			DT_PHANDLE_BY_IDX(DT_PARENT(node_id), led_pwms, i)), \
+		.pulse_ns = DIV_ROUND_NEAREST(                               \
+			DT_PWMS_PERIOD(DT_PHANDLE_BY_IDX(DT_PARENT(node_id), \
+							 led_pwms, i)) *     \
+				DT_PROP_BY_IDX(node_id, prop, i),            \
+			100),                                                \
+	},
+
+#define SET_PWM_PIN(node_id) \
+	{ DT_FOREACH_PROP_ELEM(node_id, led_values, SET_PIN) };
+
+#define GEN_PINS_ARRAY(id) struct pwm_pin_t PINS_ARRAY(id)[] = SET_PWM_PIN(id)
+
+DT_INST_FOREACH_CHILD_STATUS_OKAY_VARGS(0, DT_FOREACH_CHILD, GEN_PINS_ARRAY)
+
+#define SET_PIN_NODE(node_id)                                \
+	{ .led_color = GET_PROP(node_id, led_color),         \
+	  .led_id = GET_PROP(DT_PARENT(node_id), led_id),    \
+	  .br_color = GET_COLOR_PROP_NVE(node_id, br_color), \
+	  .pwm_pins = PINS_ARRAY(node_id),                   \
+	  .pins_count = DT_PROP_LEN(node_id, led_values) };
+
+/*
+ * Initialize led_pins_node_t struct for each pin node defined
+ */
+#define GEN_PINS_NODES(id) \
+	const struct led_pins_node_t PINS_NODE(id) = SET_PIN_NODE(id)
+
+DT_INST_FOREACH_CHILD_STATUS_OKAY_VARGS(0, DT_FOREACH_CHILD, GEN_PINS_NODES)
+
+/*
+ * Array of pointers to each pin node
+ */
+#define PINS_NODE_PTR(id) &PINS_NODE(id),
+
+const struct led_pins_node_t *pins_node[] = {
+	DT_INST_FOREACH_CHILD_STATUS_OKAY_VARGS(0, DT_FOREACH_CHILD,
+						PINS_NODE_PTR)
+};
+
+/*
+ * Set all the PWM channels defined in the node to the defined value,
+ * to enable the color. Defined value is duty cycle in percentage
+ * converted to duty cycle in ns (pulse_ns)
+ */
+void led_set_color_with_node(const struct led_pins_node_t *pins_node)
+{
+	struct pwm_pin_t *pwm_pins = pins_node->pwm_pins;
+	for (int j = 0; j < pins_node->pins_count; j++) {
+		pwm_set_pulse_dt(&pwm_pins[j].pwm, pwm_pins[j].pulse_ns);
+	}
+}
+
+/*
+ * Iterate through LED pins nodes to find the color matching node.
+ */
+void led_set_color(enum led_color color, enum ec_led_id led_id)
+{
+	for (int i = 0; i < ARRAY_SIZE(pins_node); i++) {
+		if ((pins_node[i]->led_color == color) &&
+		    (pins_node[i]->led_id == led_id)) {
+			led_set_color_with_node(pins_node[i]);
+			break;
+		}
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	memset(brightness_range, 0, EC_LED_COLOR_COUNT);
+
+	for (int i = 0; i < ARRAY_SIZE(pins_node); i++) {
+		int br_color = pins_node[i]->br_color;
+
+		if (pins_node[i]->led_id != led_id) {
+			continue;
+		}
+
+		if (br_color != EC_LED_COLOR_INVALID) {
+			brightness_range[br_color] = 100;
+		}
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	bool color_set = false;
+
+	for (int i = 0; i < ARRAY_SIZE(pins_node); i++) {
+		int br_color = pins_node[i]->br_color;
+
+		if (pins_node[i]->led_id != led_id) {
+			continue;
+		}
+
+		if (br_color != EC_LED_COLOR_INVALID &&
+		    brightness[br_color] != 0) {
+			color_set = true;
+			led_set_color(pins_node[i]->led_color, led_id);
+		}
+	}
+
+	/* If no color was set, turn off the LED */
+	if (!color_set)
+		led_set_color(LED_OFF, led_id);
+
+	return EC_SUCCESS;
+}
+
+__override int led_is_supported(enum ec_led_id led_id)
+{
+	static int supported_leds = -1;
+
+	if (supported_leds == -1) {
+		supported_leds = 0;
+
+		for (int i = 0; i < ARRAY_SIZE(pins_node); i++)
+			supported_leds |= (1 << pins_node[i]->led_id);
+	}
+
+	return ((1 << (int)led_id) & supported_leds);
+}
diff --git a/zephyr/shim/src/libgcc_arm.S b/zephyr/shim/src/libgcc_arm.S
new file mode 100644
index 0000000000..9e087ecf5f
--- /dev/null
+++ b/zephyr/shim/src/libgcc_arm.S
@@ -0,0 +1,11 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "../../third_party/libaeabi-cortexm0/core/cortex-m/ldivmod.S"
+#include "../../third_party/libaeabi-cortexm0/core/cortex-m/uldivmod.S"
+
+exception_panic:
+	mov r0, #3 @ K_ERR_KERNEL_OOPS
+	b z_fatal_error
diff --git a/zephyr/shim/src/log_backend_console_buffer.c b/zephyr/shim/src/log_backend_console_buffer.c
new file mode 100644
index 0000000000..3f455469c4
--- /dev/null
+++ b/zephyr/shim/src/log_backend_console_buffer.c
@@ -0,0 +1,56 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+
+#include <zephyr/logging/log_backend.h>
+#include <zephyr/logging/log_backend_std.h>
+#include <zephyr/logging/log_output.h>
+
+static uint8_t
+	char_out_buf[CONFIG_PLATFORM_EC_LOG_BACKEND_CONSOLE_BUFFER_TMP_BUF_SIZE];
+
+static int char_out(uint8_t *data, size_t length, void *ctx)
+{
+	/*
+	 * console_buf_notify_chars uses a mutex, which may not be
+	 * locked in ISRs.
+	 */
+	if (k_is_in_isr())
+		return 0;
+	return console_buf_notify_chars(data, length);
+}
+LOG_OUTPUT_DEFINE(log_output_console_buffer, char_out, char_out_buf,
+		  sizeof(char_out_buf));
+
+static void process(const struct log_backend *const backend,
+		    union log_msg_generic *msg)
+{
+	uint32_t flags = log_backend_std_get_flags();
+	log_format_func_t log_output_func =
+		log_format_func_t_get(LOG_OUTPUT_TEXT);
+	log_output_func(&log_output_console_buffer, &msg->log, flags);
+}
+
+static void panic(struct log_backend const *const backend)
+{
+	log_backend_std_panic(&log_output_console_buffer);
+}
+
+static void dropped(const struct log_backend *const backend, uint32_t cnt)
+{
+	log_backend_std_dropped(&log_output_console_buffer, cnt);
+}
+
+const struct log_backend_api log_backend_console_buffer_api = {
+	.process = process,
+	.panic = panic,
+	.dropped = IS_ENABLED(CONFIG_LOG_MODE_DEFERRED) ? dropped : NULL,
+	/* TODO(b/244170593): Support switching output formats */
+	.format_set = NULL,
+};
+
+LOG_BACKEND_DEFINE(log_backend_console_buffer, log_backend_console_buffer_api,
+		   true);
diff --git a/zephyr/shim/src/mkbp_event.c b/zephyr/shim/src/mkbp_event.c
new file mode 100644
index 0000000000..7fbb0ec00c
--- /dev/null
+++ b/zephyr/shim/src/mkbp_event.c
@@ -0,0 +1,19 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "mkbp_event.h"
+
+#include <zephyr/sys/iterable_sections.h>
+
+const struct mkbp_event_source *zephyr_find_mkbp_event_source(uint8_t type)
+{
+	STRUCT_SECTION_FOREACH(mkbp_event_source, evtsrc)
+	{
+		if (evtsrc->event_type == type)
+			return evtsrc;
+	}
+
+	return NULL;
+}
diff --git a/zephyr/shim/src/motionsense_driver/bma255-drvinfo.inc b/zephyr/shim/src/motionsense_driver/bma255-drvinfo.inc
new file mode 100644
index 0000000000..a16c4f0fbc
--- /dev/null
+++ b/zephyr/shim/src/motionsense_driver/bma255-drvinfo.inc
@@ -0,0 +1,44 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/accel_bma2x2_public.h"
+
+/*
+ * CREATE_SENSOR_DATA which is defined in motionsense_sensors.c is
+ * the helper to create sensor driver specific data.
+ *
+ * CREATE_SENSOR_DATA gets two arguments. One is the compatible
+ * property value specified in device tree and the other one is the macro
+ * that actually creates sensor driver specific data. The macro gets
+ * node id and the name to be used for the sensor driver data.
+ */
+
+/*
+ * Create driver data for each BMI260 drvinfo instance in device tree.
+ * (compatible = "cros-ec,drvdata-bma255")
+ */
+/* Declare BMA255 driver data */
+#define CREATE_SENSOR_DATA_BMA255(id, drvdata_name)	\
+	static struct accelgyro_saved_data_t drvdata_name;
+
+CREATE_SENSOR_DATA(cros_ec_drvdata_bma255, CREATE_SENSOR_DATA_BMA255)
+
+/*
+ * CREATE_MOTION_SENSOR which is defined in motionsense_sensors.c is
+ * the macro to create an entry in motion_sensors array.
+ * The macro gets value of compatible property of
+ * the sensor in device tree and sensor specific values like chip ID,
+ * type of sensor, name of driver, default min/max frequency.
+ * Then using the values, it creates the corresponding motion_sense_t entry
+ * in motion_sensors array.
+ */
+
+/*
+ * Create a motion_sensor_t entry for each BMA255
+ * instance(compatible = "cros-ec,bma255") in device tree.
+ */
+CREATE_MOTION_SENSOR(cros_ec_bma255, MOTIONSENSE_CHIP_BMA255,	\
+	MOTIONSENSE_TYPE_ACCEL, bma2x2_accel_drv,		\
+	BMA255_ACCEL_MIN_FREQ, BMA255_ACCEL_MAX_FREQ)
diff --git a/zephyr/shim/src/motionsense_driver/bma4xx-drvinfo.inc b/zephyr/shim/src/motionsense_driver/bma4xx-drvinfo.inc
new file mode 100644
index 0000000000..3d02e5db70
--- /dev/null
+++ b/zephyr/shim/src/motionsense_driver/bma4xx-drvinfo.inc
@@ -0,0 +1,44 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/accel_bma4xx.h"
+
+/*
+ * CREATE_SENSOR_DATA which is defined in motionsense_sensors.c is
+ * the helper to create sensor driver specific data.
+ *
+ * CREATE_SENSOR_DATA gets two arguments. One is the compatible
+ * property value specified in device tree and the other one is the macro
+ * that actually creates sensor driver specific data. The macro gets
+ * node id and the name to be used for the sensor driver data.
+ */
+
+/*
+ * Create driver data for each BMA4xx drvinfo instance in device tree.
+ * (compatible = "cros-ec,drvdata-bma4xx")
+ */
+/* Declare BMA4xx driver data */
+#define CREATE_SENSOR_DATA_BMA4XX(id, drvdata_name)	\
+	static struct accelgyro_saved_data_t drvdata_name;
+
+CREATE_SENSOR_DATA(cros_ec_drvdata_bma4xx, CREATE_SENSOR_DATA_BMA4XX)
+
+/*
+ * CREATE_MOTION_SENSOR which is defined in motionsense_sensors.c is
+ * the macro to create an entry in motion_sensors array.
+ * The macro gets value of compatible property of
+ * the sensor in device tree and sensor specific values like chip ID,
+ * type of sensor, name of driver, default min/max frequency.
+ * Then using the values, it creates the corresponding motion_sense_t entry
+ * in motion_sensors array.
+ */
+
+/*
+ * Create a motion_sensor_t entry for each BMA4XX
+ * instance(compatible = "cros-ec,bma4xx") in device tree.
+ */
+CREATE_MOTION_SENSOR(cros_ec_bma4xx, MOTIONSENSE_CHIP_BMA422,	\
+	MOTIONSENSE_TYPE_ACCEL, bma4_accel_drv,		\
+	BMA4_ACCEL_MIN_FREQ, BMA4_ACCEL_MAX_FREQ)
diff --git a/zephyr/shim/src/motionsense_driver/bmi160-drvinfo.inc b/zephyr/shim/src/motionsense_driver/bmi160-drvinfo.inc
new file mode 100644
index 0000000000..36d20db7be
--- /dev/null
+++ b/zephyr/shim/src/motionsense_driver/bmi160-drvinfo.inc
@@ -0,0 +1,57 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/accelgyro_bmi_common_public.h"
+#include "driver/accelgyro_bmi160_public.h"
+
+/*
+ * CREATE_SENSOR_DATA which is defined in motionsense_sensros.c is
+ * the helper to create sensor driver specific data.
+ *
+ * CREATE_SENSOR_DATA gets two arguments. One is the compatible
+ * property value specified in device tree and the other one is the macro
+ * that actually creates sensor driver specific data. The macro gets
+ * node id and the name to be used for the sensor driver data.
+ */
+
+/*
+ * Create driver data. It can be shared among the entries in
+ * motion_sensors array which are using the same bmi160 driver.
+ */
+#define CREATE_SENSOR_DATA_BMI160(id, drvdata_name)			\
+	static struct bmi_drv_data_t drvdata_name;
+
+/*
+ * Create driver data for each BMI160 drvinfo instance in device tree.
+ * (compatible = "cros-ec,drvdata-bmi160")
+ */
+CREATE_SENSOR_DATA(cros_ec_drvdata_bmi160, CREATE_SENSOR_DATA_BMI160)
+/*
+ * CREATE_MOTION_SENSOR which is defined in motionsense_sensors.c is
+ * the macro to create an entry in motion_sensors array.
+ * The macro gets value of compatible property of
+ * the sensor in device tree and sensor specific values like chip ID,
+ * type of sensor, name of driver, default min/max frequency.
+ * Then using the values, it creates the corresponding motion_sense_t entry
+ * in motion_sensors array.
+ */
+
+/*
+ * Here, we call CREATE_MOTION_SENSOR to create a motion_sensor_t entry
+ * for each BMI160_accel instance(compatible = "cros-ec,bmi160-accel")
+ * in device tree.
+ */
+CREATE_MOTION_SENSOR(cros_ec_bmi160_accel, MOTIONSENSE_CHIP_BMI160,	\
+		MOTIONSENSE_TYPE_ACCEL,	bmi160_drv,			\
+		BMI_ACCEL_MIN_FREQ, BMI_ACCEL_MAX_FREQ)
+
+/*
+ * Here, we call CREATE_MOTION_SENSOR to create a motion_sensor_t entry
+ * for each BMI260_gyro instance (compatible = "cros-ec,bmi160-gyro")
+ * in device tree.
+ */
+CREATE_MOTION_SENSOR(cros_ec_bmi160_gyro, MOTIONSENSE_CHIP_BMI160,	\
+		MOTIONSENSE_TYPE_GYRO, bmi160_drv,			\
+		BMI_GYRO_MIN_FREQ, BMI_GYRO_MAX_FREQ)
diff --git a/zephyr/shim/src/motionsense_driver/bmi260-drvinfo.inc b/zephyr/shim/src/motionsense_driver/bmi260-drvinfo.inc
new file mode 100644
index 0000000000..72bfc5b4b3
--- /dev/null
+++ b/zephyr/shim/src/motionsense_driver/bmi260-drvinfo.inc
@@ -0,0 +1,57 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/accelgyro_bmi_common_public.h"
+#include "driver/accelgyro_bmi260_public.h"
+
+/*
+ * CREATE_SENSOR_DATA which is defined in motionsense_sensros.c is
+ * the helper to create sensor driver specific data.
+ *
+ * CREATE_SENSOR_DATA gets two arguments. One is the compatible
+ * property value specified in device tree and the other one is the macro
+ * that actually creates sensor driver specific data. The macro gets
+ * node id and the name to be used for the sensor driver data.
+ */
+
+/*
+ * Create driver data. It can be shared among the entries in
+ * motion_sensors array which are using the same bmi260 driver.
+ */
+#define CREATE_SENSOR_DATA_BMI260(id, drvdata_name)			\
+	static struct bmi_drv_data_t drvdata_name;
+
+/*
+ * Create driver data for each BMI260 drvinfo instance in device tree.
+ * (compatible = "cros-ec,drvdata-bmi260")
+ */
+CREATE_SENSOR_DATA(cros_ec_drvdata_bmi260, CREATE_SENSOR_DATA_BMI260)
+/*
+ * CREATE_MOTION_SENSOR which is defined in motionsense_sensros.c is
+ * the macro to create an entry in motion_sensors array.
+ * The macro gets value of compatible property of
+ * the sensor in device tree and sensor specific values like chip ID,
+ * type of sensor, name of driver, default min/max frequency.
+ * Then using the values, it creates the corresponding motion_sense_t entry
+ * in motion_sensors array.
+ */
+
+/*
+ * Here, we call CREATE_MOTION_SENSOR to create a motion_sensor_t entry
+ * for each BMI260_accel instance(compatible = "cros-ec,bmi260-accel")
+ * in device tree.
+ */
+CREATE_MOTION_SENSOR(cros_ec_bmi260_accel, MOTIONSENSE_CHIP_BMI260,	\
+		MOTIONSENSE_TYPE_ACCEL,	bmi260_drv,			\
+		BMI_ACCEL_MIN_FREQ, BMI_ACCEL_MAX_FREQ)
+
+/*
+ * Here, we call CREATE_MOTION_SENSOR to create a motion_sensor_t entry
+ * for each BMI260_gyro instance (compatible = "cros-ec,bmi260-gyro")
+ * in device tree.
+ */
+CREATE_MOTION_SENSOR(cros_ec_bmi260_gyro, MOTIONSENSE_CHIP_BMI260,	\
+		MOTIONSENSE_TYPE_GYRO, bmi260_drv,			\
+		BMI_GYRO_MIN_FREQ, BMI_GYRO_MAX_FREQ)
diff --git a/zephyr/shim/src/motionsense_driver/bmi3xx-drvinfo.inc b/zephyr/shim/src/motionsense_driver/bmi3xx-drvinfo.inc
new file mode 100644
index 0000000000..c28f5c1786
--- /dev/null
+++ b/zephyr/shim/src/motionsense_driver/bmi3xx-drvinfo.inc
@@ -0,0 +1,57 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/accelgyro_bmi_common_public.h"
+#include "driver/accelgyro_bmi3xx.h"
+
+/*
+ * CREATE_SENSOR_DATA which is defined in motionsense_sensros.c is
+ * the helper to create sensor driver specific data.
+ *
+ * CREATE_SENSOR_DATA gets two arguments. One is the compatible
+ * property value specified in device tree and the other one is the macro
+ * that actually creates sensor driver specific data. The macro gets
+ * node id and the name to be used for the sensor driver data.
+ */
+
+/*
+ * Create driver data. It can be shared among the entries in
+ * motion_sensors array which are using the same bmi3xx driver.
+ */
+#define CREATE_SENSOR_DATA_BMI3XX(id, drvdata_name)			\
+	static struct bmi_drv_data_t drvdata_name;
+
+/*
+ * Create driver data for each BMI3XX drvinfo instance in device tree.
+ * (compatible = "cros-ec,drvdata-bmi3xx")
+ */
+CREATE_SENSOR_DATA(cros_ec_drvdata_bmi3xx, CREATE_SENSOR_DATA_BMI3XX)
+/*
+ * CREATE_MOTION_SENSOR which is defined in motionsense_sensros.c is
+ * the macro to create an entry in motion_sensors array.
+ * The macro gets value of compatible property of
+ * the sensor in device tree and sensor specific values like chip ID,
+ * type of sensor, name of driver, default min/max frequency.
+ * Then using the values, it creates the corresponding motion_sense_t entry
+ * in motion_sensors array.
+ */
+
+/*
+ * Here, we call CREATE_MOTION_SENSOR to create a motion_sensor_t entry
+ * for each BMI3XX_accel instance(compatible = "cros-ec,bmi3xx-accel")
+ * in device tree.
+ */
+CREATE_MOTION_SENSOR(cros_ec_bmi3xx_accel, MOTIONSENSE_CHIP_BMI323,	\
+		MOTIONSENSE_TYPE_ACCEL,	bmi3xx_drv,			\
+		BMI_ACCEL_MIN_FREQ, BMI_ACCEL_MAX_FREQ)
+
+/*
+ * Here, we call CREATE_MOTION_SENSOR to create a motion_sensor_t entry
+ * for each BMI3XX_gyro instance (compatible = "cros-ec,bmi3xx-gyro")
+ * in device tree.
+ */
+CREATE_MOTION_SENSOR(cros_ec_bmi3xx_gyro, MOTIONSENSE_CHIP_BMI323,	\
+		MOTIONSENSE_TYPE_GYRO, bmi3xx_drv,			\
+		BMI_GYRO_MIN_FREQ, BMI_GYRO_MAX_FREQ)
diff --git a/zephyr/shim/src/motionsense_driver/drvdata-accelgyro.h b/zephyr/shim/src/motionsense_driver/drvdata-accelgyro.h
new file mode 100644
index 0000000000..ab2f08a496
--- /dev/null
+++ b/zephyr/shim/src/motionsense_driver/drvdata-accelgyro.h
@@ -0,0 +1,125 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Macros are to help creating driver data. A driver data that uses
+ * any data structures defined in accelgyro.h should use the macros here
+ * to utilize the information in device tree.
+ *
+ */
+#ifndef __ZEPHYR_SHIM_SRC_MOTIONSENSE_DRIVER_DRVDATA_ACCELGYRO_H
+#define __ZEPHYR_SHIM_SRC_MOTIONSENSE_DRIVER_DRVDATA_ACCELGYRO_H
+
+/*
+ * compatible = "cros-ec,accelgyro-als-channel-scale"
+ * als_channel_scale_t in accelgyro.h
+ *
+ * e.g) The following is the example in DT for als_channel_scale_t
+ * als-channel-scale {
+ *	compatible = "cros-ec,accelgyro-als-channel-scale";
+ *		k-channel-scale = <1>;
+ *		cover-scale = <1>;
+ *	};
+ */
+#define ACCELGYRO_ALS_CHANNEL_SCALE(id)                                     \
+	{                                                                   \
+		.k_channel_scale =                                          \
+			ALS_CHANNEL_SCALE(DT_PROP(id, k_channel_scale)),    \
+		.cover_scale = ALS_CHANNEL_SCALE(DT_PROP(id, cover_scale)), \
+	}
+
+#define ALS_CALIBRATION_CHANNEL_SCALE(id) \
+	.als_cal.channel_scale = ACCELGYRO_ALS_CHANNEL_SCALE(id),
+
+#define ALS_CALIBRATION_SET(id)                \
+	.als_cal.scale = DT_PROP(id, scale),   \
+	.als_cal.uscale = DT_PROP(id, uscale), \
+	.als_cal.offset = DT_PROP(id, offset), \
+	ALS_CALIBRATION_CHANNEL_SCALE(DT_CHILD(id, als_channel_scale))
+
+/*
+ * compatible = "cros-ec,accelgyro-als-drv-data"
+ * als_drv_data_t in accelgyro.h
+ *
+ * e.g) The following is the example in DT for als_drv_data_t
+ * als-drv-data {
+ *	compatible = "cros-ec,accelgyro-als-drv-data";
+ *	als-cal {
+ *		scale = <1>;
+ *		uscale = <0>;
+ *		offset = <0>;
+ *		als-channel-scale {
+ *		compatible = "cros-ec,accelgyro-als-channel-scale";
+ *			k-channel-scale = <1>;
+ *			cover-scale = <1>;
+ *		};
+ *	};
+ * };
+ */
+#define ACCELGYRO_ALS_DRV_DATA(id)                         \
+	{                                                  \
+		ALS_CALIBRATION_SET(DT_CHILD(id, als_cal)) \
+	}
+
+#define RGB_CAL_RGB_SET_SCALE(id) .scale = ACCELGYRO_ALS_CHANNEL_SCALE(id),
+
+#define RGB_CAL_RGB_SET_ONE(id, suffix)                                \
+	.rgb_cal[suffix] = {                                           \
+		.offset = DT_PROP(id, offset),                         \
+		.coeff[0] = FLOAT_TO_FP(DT_PROP_BY_IDX(id, coeff, 0)), \
+		.coeff[1] = FLOAT_TO_FP(DT_PROP_BY_IDX(id, coeff, 1)), \
+		.coeff[2] = FLOAT_TO_FP(DT_PROP_BY_IDX(id, coeff, 2)), \
+		.coeff[3] = FLOAT_TO_FP(DT_PROP_BY_IDX(id, coeff, 3)), \
+		RGB_CAL_RGB_SET_SCALE(DT_CHILD(id, als_channel_scale)) \
+	},
+
+/*
+ * compatible = "cros-ec,accelgyro-rgb-calibration"
+ * rgb_calibration_t in accelgyro.h
+ *
+ * e.g) The following is the example in DT for rgb_calibration_t
+ * rgb_calibration {
+ * 	compatible = "cros-ec,accelgyro-rgb-calibration";
+ *
+ *	irt = <1>;
+ *
+ *	rgb-cal-x {
+ *		offset = <0>;
+ *		coeff = <0 0 0 0>;
+ *		als-channel-scale {
+ *		compatible = "cros-ec,accelgyro-als-channel-scale";
+ *			k-channel-scale = <1>;
+ *			cover-scale = <1>;
+ *		};
+ *	};
+ *	rgb-cal-y {
+ *		offset = <0>;
+ *		coeff = <0 0 0 0>;
+ *		als-channel-scale {
+ *		compatible = "cros-ec,accelgyro-als-channel-scale";
+ *			k-channel-scale = <1>;
+ *			cover-scale = <1>;
+ *		};
+ *	};
+ *	rgb-cal-z {
+ *		offset = <0>;
+ *		coeff = <0 0 0 0>;
+ *		als-channel-scale {
+ *		compatible = "cros-ec,accelgyro-als-channel-scale";
+ *			k-channel-scale = <1>;
+ *			cover-scale = <1>;
+ *		};
+ *	};
+ * };
+ */
+#define ACCELGYRO_RGB_CALIBRATION(id)                                 \
+	{                                                             \
+		RGB_CAL_RGB_SET_ONE(DT_CHILD(id, rgb_cal_x), X)       \
+		RGB_CAL_RGB_SET_ONE(DT_CHILD(id, rgb_cal_y), Y)       \
+		RGB_CAL_RGB_SET_ONE(DT_CHILD(id, rgb_cal_z), Z).irt = \
+			INT_TO_FP(DT_PROP(id, irt)),                  \
+	}
+
+#endif /* __ZEPHYR_SHIM_SRC_MOTIONSENSE_DRIVER_DRVDATA_ACCELGYRO_H */
diff --git a/zephyr/shim/src/motionsense_driver/icm42607-drvinfo.inc b/zephyr/shim/src/motionsense_driver/icm42607-drvinfo.inc
new file mode 100644
index 0000000000..ede16342ea
--- /dev/null
+++ b/zephyr/shim/src/motionsense_driver/icm42607-drvinfo.inc
@@ -0,0 +1,57 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/accelgyro_icm_common.h"
+#include "driver/accelgyro_icm42607.h"
+
+/*
+ * CREATE_SENSOR_DATA which is defined in motionsense_sensors.c is
+ * the helper to create sensor driver specific data.
+ *
+ * CREATE_SENSOR_DATA gets two arguments. One is the compatible
+ * property value specified in device tree and the other one is the macro
+ * that actually creates sensor driver specific data. The macro gets
+ * node id and the name to be used for the sensor driver data.
+ */
+
+/*
+ * Create driver data. It can be shared among the entries in
+ * motion_sensors array which are using the same icm42607 driver.
+ */
+#define CREATE_SENSOR_DATA_ICM42607(id, drvdata_name) \
+	static struct icm_drv_data_t drvdata_name;
+
+/*
+ * Create driver data for each icm42607 drvinfo instance in device tree.
+ * (compatible = "cros-ec,drvdata-icm42607")
+ */
+CREATE_SENSOR_DATA(cros_ec_drvdata_icm42607, CREATE_SENSOR_DATA_ICM42607)
+/*
+ * CREATE_MOTION_SENSOR which is defined in motionsense_sensors.c is
+ * the macro to create an entry in motion_sensors array.
+ * The macro gets value of compatible property of
+ * the sensor in device tree and sensor specific values like chip ID,
+ * type of sensor, name of driver, default min/max frequency.
+ * Then using the values, it creates the corresponding motion_sense_t entry
+ * in motion_sensors array.
+ */
+
+/*
+ * Here, we call CREATE_MOTION_SENSOR to create a motion_sensor_t entry
+ * for each icm42607 accel instance(compatible = "cros-ec,icm42607-accel")
+ * in device tree.
+ */
+CREATE_MOTION_SENSOR(cros_ec_icm42607_accel, MOTIONSENSE_CHIP_ICM42607, \
+		MOTIONSENSE_TYPE_ACCEL,	icm42607_drv, \
+		ICM42607_ACCEL_MIN_FREQ, ICM42607_ACCEL_MAX_FREQ)
+
+/*
+ * Here, we call CREATE_MOTION_SENSOR to create a motion_sensor_t entry
+ * for each icm42607 gyro instance (compatible = "cros-ec,icm42607-gyro")
+ * in device tree.
+ */
+CREATE_MOTION_SENSOR(cros_ec_icm42607_gyro, MOTIONSENSE_CHIP_ICM42607, \
+		MOTIONSENSE_TYPE_GYRO, icm42607_drv, \
+		ICM42607_GYRO_MIN_FREQ, ICM42607_GYRO_MAX_FREQ)
diff --git a/zephyr/shim/src/motionsense_driver/icm426xx-drvinfo.inc b/zephyr/shim/src/motionsense_driver/icm426xx-drvinfo.inc
new file mode 100644
index 0000000000..d949829750
--- /dev/null
+++ b/zephyr/shim/src/motionsense_driver/icm426xx-drvinfo.inc
@@ -0,0 +1,57 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/accelgyro_icm_common.h"
+#include "driver/accelgyro_icm426xx.h"
+
+/*
+ * CREATE_SENSOR_DATA which is defined in motionsense_sensors.c is
+ * the helper to create sensor driver specific data.
+ *
+ * CREATE_SENSOR_DATA gets two arguments. One is the compatible
+ * property value specified in device tree and the other one is the macro
+ * that actually creates sensor driver specific data. The macro gets
+ * node id and the name to be used for the sensor driver data.
+ */
+
+/*
+ * Create driver data. It can be shared among the entries in
+ * motion_sensors array which are using the same icm426xx driver.
+ */
+#define CREATE_SENSOR_DATA_ICM426XX(id, drvdata_name)			\
+	static struct icm_drv_data_t drvdata_name;
+
+/*
+ * Create driver data for each icm426xx drvinfo instance in device tree.
+ * (compatible = "cros-ec,drvdata-icm426xx")
+ */
+CREATE_SENSOR_DATA(cros_ec_drvdata_icm426xx, CREATE_SENSOR_DATA_ICM426XX)
+/*
+ * CREATE_MOTION_SENSOR which is defined in motionsense_sensors.c is
+ * the macro to create an entry in motion_sensors array.
+ * The macro gets value of compatible property of
+ * the sensor in device tree and sensor specific values like chip ID,
+ * type of sensor, name of driver, default min/max frequency.
+ * Then using the values, it creates the corresponding motion_sense_t entry
+ * in motion_sensors array.
+ */
+
+/*
+ * Here, we call CREATE_MOTION_SENSOR to create a motion_sensor_t entry
+ * for each icm426xx accel instance(compatible = "cros-ec,icm426xx-accel")
+ * in device tree.
+ */
+CREATE_MOTION_SENSOR(cros_ec_icm426xx_accel, MOTIONSENSE_CHIP_ICM426XX,	\
+		MOTIONSENSE_TYPE_ACCEL,	icm426xx_drv,			\
+		ICM426XX_ACCEL_MIN_FREQ, ICM426XX_ACCEL_MAX_FREQ)
+
+/*
+ * Here, we call CREATE_MOTION_SENSOR to create a motion_sensor_t entry
+ * for each icm426xx gyro instance (compatible = "cros-ec,icm426xx-gyro")
+ * in device tree.
+ */
+CREATE_MOTION_SENSOR(cros_ec_icm426xx_gyro, MOTIONSENSE_CHIP_ICM426XX,	\
+		MOTIONSENSE_TYPE_GYRO, icm426xx_drv,			\
+		ICM426XX_GYRO_MIN_FREQ, ICM426XX_GYRO_MAX_FREQ)
diff --git a/zephyr/shim/src/motionsense_driver/kx022-drvinfo.inc b/zephyr/shim/src/motionsense_driver/kx022-drvinfo.inc
new file mode 100644
index 0000000000..26885230e1
--- /dev/null
+++ b/zephyr/shim/src/motionsense_driver/kx022-drvinfo.inc
@@ -0,0 +1,44 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/accel_kionix.h"
+
+/*
+ * CREATE_SENSOR_DATA which is defined in motionsense_sensors.c is
+ * the helper to create sensor driver specific data.
+ *
+ * CREATE_SENSOR_DATA gets two arguments. One is the compatible
+ * property value specified in device tree and the other one is the macro
+ * that actually creates sensor driver specific data. The macro gets
+ * node id and the name to be used for the sensor driver data.
+ */
+
+/*
+ * Create driver data for each Kionix drvinfo instance in device tree.
+ * (compatible = "cros-ec,drvdata-kionix")
+ */
+/* Declare Kionix driver data */
+#define CREATE_SENSOR_DATA_KIONIX(id, drvdata_name)	\
+	static struct kionix_accel_data drvdata_name;
+
+CREATE_SENSOR_DATA(cros_ec_drvdata_kionix, CREATE_SENSOR_DATA_KIONIX)
+
+/*
+ * CREATE_MOTION_SENSOR which is defined in motionsense_sensors.c is
+ * the macro to create an entry in motion_sensors array.
+ * The macro gets value of compatible property of
+ * the sensor in device tree and sensor specific values like chip ID,
+ * type of sensor, name of driver, default min/max frequency.
+ * Then using the values, it creates the corresponding motion_sense_t entry
+ * in motion_sensors array.
+ */
+
+/*
+ * Create a motion_sensor_t entry for each KX022
+ * instance(compatible = "cros-ec,kx022") in device tree.
+ */
+CREATE_MOTION_SENSOR(cros_ec_kx022, MOTIONSENSE_CHIP_KX022,      \
+		     MOTIONSENSE_TYPE_ACCEL, kionix_accel_drv,   \
+		     KX022_ACCEL_MIN_FREQ, KX022_ACCEL_MAX_FREQ)
diff --git a/zephyr/shim/src/motionsense_driver/lis2dw12-drvinfo.inc b/zephyr/shim/src/motionsense_driver/lis2dw12-drvinfo.inc
new file mode 100644
index 0000000000..4605fcd749
--- /dev/null
+++ b/zephyr/shim/src/motionsense_driver/lis2dw12-drvinfo.inc
@@ -0,0 +1,44 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "accel_lis2dw12_public.h"
+
+/*
+ * CREATE_SENSOR_DATA which is defined in motionsense_sensors.c is
+ * the helper to create sensor driver specific data.
+ *
+ * CREATE_SENSOR_DATA gets two arguments. One is the compatible
+ * property value specified in device tree and the other one is the macro
+ * that actually creates sensor driver specific data. The macro gets
+ * node id and the name to be used for the sensor driver data.
+ */
+
+/*
+ * Create driver data for each Kionix drvinfo instance in device tree.
+ * (compatible = "cros-ec,drvdata-lis2dw12")
+ */
+/* Declare LIS2DW12 driver data */
+#define CREATE_SENSOR_DATA_LIS2DW12(id, drvdata_name)	\
+	static struct motion_sensor_t drvdata_name;
+
+CREATE_SENSOR_DATA(cros_ec_drvdata_lis2dw12, CREATE_SENSOR_DATA_LIS2DW12)
+
+/*
+ * CREATE_MOTION_SENSOR which is defined in motionsense_sensors.c is
+ * the macro to create an entry in motion_sensors array.
+ * The macro gets value of compatible property of
+ * the sensor in device tree and sensor specific values like chip ID,
+ * type of sensor, name of driver, default min/max frequency.
+ * Then using the values, it creates the corresponding motion_sense_t entry
+ * in motion_sensors array.
+ */
+
+/*
+ * Create a motion_sensor_t entry for each LIS2DW12
+ * instance(compatible = "cros-ec,lis2dw12") in device tree.
+ */
+CREATE_MOTION_SENSOR(cros_ec_lis2dw12, MOTIONSENSE_CHIP_LIS2DW12,	\
+		     MOTIONSENSE_TYPE_ACCEL, lis2dw12_drv,		\
+		     LIS2DW12_ODR_MIN_VAL, LIS2DW12_ODR_MAX_VAL)
diff --git a/zephyr/shim/src/motionsense_driver/lsm6dsm-drvinfo.inc b/zephyr/shim/src/motionsense_driver/lsm6dsm-drvinfo.inc
new file mode 100644
index 0000000000..32faaa087f
--- /dev/null
+++ b/zephyr/shim/src/motionsense_driver/lsm6dsm-drvinfo.inc
@@ -0,0 +1,57 @@
+/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/accelgyro_lsm6dsm.h"
+#include "driver/stm_mems_common.h"
+
+/*
+ * CREATE_SENSOR_DATA which is defined in motionsense_sensors.c is
+ * the helper to create sensor driver specific data.
+ *
+ * CREATE_SENSOR_DATA gets two arguments. One is the compatible
+ * property value specified in device tree and the other one is the macro
+ * that actually creates sensor driver specific data. The macro gets
+ * node id and the name to be used for the sensor driver data.
+ */
+
+/*
+ * Create driver data. This must be a separate instance for
+ * each entry of the lsm6dsm device in the motion_sensors array.
+ */
+#define CREATE_SENSOR_DATA_LSM6DSM(id, drvdata_name) \
+	static struct lsm6dsm_data drvdata_name = LSM6DSM_DATA;
+
+/*
+ * Create driver data for each lsm6dsm drvinfo instance in device tree.
+ * (compatible = "cros-ec,drvdata-lsm6dsm")
+ */
+CREATE_SENSOR_DATA(cros_ec_drvdata_lsm6dsm, CREATE_SENSOR_DATA_LSM6DSM)
+/*
+ * CREATE_MOTION_SENSOR which is defined in motionsense_sensors.c is
+ * the macro to create an entry in motion_sensors array.
+ * The macro gets value of compatible property of
+ * the sensor in device tree and sensor specific values like chip ID,
+ * type of sensor, name of driver, default min/max frequency.
+ * Then using the values, it creates the corresponding motion_sense_t entry
+ * in motion_sensors array.
+ */
+
+/*
+ * Here, we call CREATE_MOTION_SENSOR to create a motion_sensor_t entry
+ * for each lsm6dsm accel instance(compatible = "cros-ec,lsm6dsm-accel")
+ * in device tree.
+ */
+CREATE_MOTION_SENSOR(cros_ec_lsm6dsm_accel, MOTIONSENSE_CHIP_LSM6DSM, \
+		MOTIONSENSE_TYPE_ACCEL,	lsm6dsm_drv, \
+		LSM6DSM_ODR_MIN_VAL, LSM6DSM_ODR_MAX_VAL)
+
+/*
+ * Here, we call CREATE_MOTION_SENSOR to create a motion_sensor_t entry
+ * for each lsm6dsm gyro instance (compatible = "cros-ec,lsm6dsm-gyro")
+ * in device tree.
+ */
+CREATE_MOTION_SENSOR(cros_ec_lsm6dsm_gyro, MOTIONSENSE_CHIP_LSM6DSM, \
+		MOTIONSENSE_TYPE_GYRO, lsm6dsm_drv, \
+		LSM6DSM_ODR_MIN_VAL, LSM6DSM_ODR_MAX_VAL)
diff --git a/zephyr/shim/src/motionsense_driver/lsm6dso-drvinfo.inc b/zephyr/shim/src/motionsense_driver/lsm6dso-drvinfo.inc
new file mode 100644
index 0000000000..dfffa2fe2a
--- /dev/null
+++ b/zephyr/shim/src/motionsense_driver/lsm6dso-drvinfo.inc
@@ -0,0 +1,57 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/accelgyro_lsm6dso.h"
+#include "driver/stm_mems_common.h"
+
+/*
+ * CREATE_SENSOR_DATA which is defined in motionsense_sensors.c is
+ * the helper to create sensor driver specific data.
+ *
+ * CREATE_SENSOR_DATA gets two arguments. One is the compatible
+ * property value specified in device tree and the other one is the macro
+ * that actually creates sensor driver specific data. The macro gets
+ * node id and the name to be used for the sensor driver data.
+ */
+
+/*
+ * Create driver data. This must be a separate instance for
+ * each entry of the lsm6dso device in the motion_sensors array.
+ */
+#define CREATE_SENSOR_DATA_LSM6DSO(id, drvdata_name) \
+	static struct stprivate_data drvdata_name;
+
+/*
+ * Create driver data for each lsm6dso drvinfo instance in device tree.
+ * (compatible = "cros-ec,drvdata-lsm6dso")
+ */
+CREATE_SENSOR_DATA(cros_ec_drvdata_lsm6dso, CREATE_SENSOR_DATA_LSM6DSO)
+/*
+ * CREATE_MOTION_SENSOR which is defined in motionsense_sensors.c is
+ * the macro to create an entry in motion_sensors array.
+ * The macro gets value of compatible property of
+ * the sensor in device tree and sensor specific values like chip ID,
+ * type of sensor, name of driver, default min/max frequency.
+ * Then using the values, it creates the corresponding motion_sense_t entry
+ * in motion_sensors array.
+ */
+
+/*
+ * Here, we call CREATE_MOTION_SENSOR to create a motion_sensor_t entry
+ * for each lsm6dso accel instance(compatible = "cros-ec,lsm6dso-accel")
+ * in device tree.
+ */
+CREATE_MOTION_SENSOR(cros_ec_lsm6dso_accel, MOTIONSENSE_CHIP_LSM6DSO, \
+		MOTIONSENSE_TYPE_ACCEL,	lsm6dso_drv, \
+		LSM6DSO_ODR_MIN_VAL, LSM6DSO_ODR_MAX_VAL)
+
+/*
+ * Here, we call CREATE_MOTION_SENSOR to create a motion_sensor_t entry
+ * for each lsm6dso gyro instance (compatible = "cros-ec,lsm6dso-gyro")
+ * in device tree.
+ */
+CREATE_MOTION_SENSOR(cros_ec_lsm6dso_gyro, MOTIONSENSE_CHIP_LSM6DSO, \
+		MOTIONSENSE_TYPE_GYRO, lsm6dso_drv, \
+		LSM6DSO_ODR_MIN_VAL, LSM6DSO_ODR_MAX_VAL)
diff --git a/zephyr/shim/src/motionsense_driver/sensor_drv_list.inc b/zephyr/shim/src/motionsense_driver/sensor_drv_list.inc
new file mode 100644
index 0000000000..1ea1ba2a2d
--- /dev/null
+++ b/zephyr/shim/src/motionsense_driver/sensor_drv_list.inc
@@ -0,0 +1,57 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * A driver should create <chip>-drvinfo.inc to create
+ * driver-specific data and an motion sensor entry in
+ * motion_sensors array that are used by motion sense task.
+ *
+ * This file includes the .inc file and is used by motionsense_sensrs.c to
+ * create the sensor driver data and the entries in mostion_sensors array.
+ *
+ * e.g) bma255-drvinfo.inc is provided for BMA255 chip
+ *
+ * #ifdef CONFIG_ACCEL_BMA255
+ * #include "bma255-drvinfo.inc"
+ * #endif
+ */
+
+/* supported sensor driver list */
+#ifdef CONFIG_PLATFORM_EC_ACCEL_BMA255
+#include "bma255-drvinfo.inc"
+#endif
+#ifdef CONFIG_PLATFORM_EC_ACCEL_BMA4XX
+#include "bma4xx-drvinfo.inc"
+#endif
+#ifdef CONFIG_PLATFORM_EC_ACCEL_KX022
+#include "kx022-drvinfo.inc"
+#endif
+#ifdef CONFIG_PLATFORM_EC_ACCEL_LIS2DW12
+#include "lis2dw12-drvinfo.inc"
+#endif
+#ifdef CONFIG_PLATFORM_EC_ACCELGYRO_BMI160
+#include "bmi160-drvinfo.inc"
+#endif
+#ifdef CONFIG_PLATFORM_EC_ACCELGYRO_BMI260
+#include "bmi260-drvinfo.inc"
+#endif
+#ifdef CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX
+#include "bmi3xx-drvinfo.inc"
+#endif
+#ifdef CONFIG_PLATFORM_EC_ALS_TCS3400
+#include "tcs3400-drvinfo.inc"
+#endif
+#ifdef CONFIG_PLATFORM_EC_ACCELGYRO_ICM426XX
+#include "icm426xx-drvinfo.inc"
+#endif
+#ifdef CONFIG_PLATFORM_EC_ACCELGYRO_ICM42607
+#include "icm42607-drvinfo.inc"
+#endif
+#ifdef CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSO
+#include "lsm6dso-drvinfo.inc"
+#endif
+#ifdef CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSM
+#include "lsm6dsm-drvinfo.inc"
+#endif
diff --git a/zephyr/shim/src/motionsense_driver/tcs3400-drvinfo.inc b/zephyr/shim/src/motionsense_driver/tcs3400-drvinfo.inc
new file mode 100644
index 0000000000..9d42860ac7
--- /dev/null
+++ b/zephyr/shim/src/motionsense_driver/tcs3400-drvinfo.inc
@@ -0,0 +1,79 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/als_tcs3400_public.h"
+
+/*
+ * CREATE_SENSOR_DATA which is defined in motionsense_sensros.c is
+ * the helper to create sensor driver specific data.
+ *
+ * CREATE_SENSOR_DATA gets two arguments. One is the compatible
+ * property value specified in device tree and the other one is the macro
+ * that actually creates sensor driver specific data. The macro gets
+ * node id and the name to be used for the sensor driver data.
+ */
+
+/* include macros for common data strutures from accelgyro.h */
+#include "drvdata-accelgyro.h"
+
+/* Create driver data for tcs3400 driver. */
+#define CREATE_SENSOR_DATA_TCS3400_CLEAR(id, drvdata_name)		\
+	static struct als_drv_data_t drvdata_name =			\
+	    ACCELGYRO_ALS_DRV_DATA(DT_CHILD(id, als_drv_data));
+
+/*
+ * Create driver data for each TCS3400-clear drvdata instance in device tree.
+ * (compatible = "cros-ec,drvdata-tcs3400-clear")
+ */
+CREATE_SENSOR_DATA(cros_ec_drvdata_tcs3400_clear,	\
+	CREATE_SENSOR_DATA_TCS3400_CLEAR)
+
+/* driver data for tcs3400 rgb */
+#define TCS3400_RGB_SATRURATION(id)					\
+		COND_CODE_1(DT_NODE_HAS_PROP(id, again),		\
+			(.saturation.again = DT_PROP(id, again),),	\
+			(.saturation.again = TCS_DEFAULT_AGAIN,))	\
+		COND_CODE_1(DT_NODE_HAS_PROP(id, atime),		\
+			(.saturation.again = DT_PROP(id, atime),),	\
+			(.saturation.again = TCS_DEFAULT_ATIME,))
+
+#define CREATE_SENSOR_DATA_TCS3400_RGB(id, drvdata_name)		\
+	static struct tcs3400_rgb_drv_data_t drvdata_name = {		\
+		.calibration = ACCELGYRO_RGB_CALIBRATION(		\
+			DT_CHILD(id, rgb_calibration)),			\
+		TCS3400_RGB_SATRURATION(DT_CHILD(id, saturation))	\
+	};
+
+/*
+ * Create driver data for each TCS3400-rgb drvdata instance in device tree.
+ * (compatible = "cros-ec,drvdata-tcs3400-rgb")
+ */
+CREATE_SENSOR_DATA(cros_ec_drvdata_tcs3400_rgb, CREATE_SENSOR_DATA_TCS3400_RGB)
+/*
+ * CREATE_MOTION_SENSOR which is defined in motionsense_sensros.c is
+ * the macro to create an entry in motion_sensors array.
+ * The macro gets value of compatible property of
+ * the sensor in device tree and sensor specific values like chip ID,
+ * type of sensor, name of driver, default min/max frequency.
+ * Then using the values, it creates the corresponding motion_sense_t entry
+ * in motion_sensors array.
+ */
+
+/*
+ * Here, we call CREATE_MOTION_SENSOR to create a motion_sensor_t entry
+ * for each TCS3400 clear instance (compatible = "cros-ec,tcs3400-clear")
+ * in device tree.
+ */
+CREATE_MOTION_SENSOR(cros_ec_tcs3400_clear, MOTIONSENSE_CHIP_TCS3400,	\
+		MOTIONSENSE_TYPE_LIGHT, tcs3400_drv,			\
+		TCS3400_LIGHT_MIN_FREQ, TCS3400_LIGHT_MAX_FREQ)
+
+/*
+ * Here, we call CREATE_MOTION_SENSOR to create a motion_sensor_t entry
+ * for each TCS3400 RGB instance (compatible = "cros-ec,tcs3400-rgb")
+ * in device tree.
+ */
+CREATE_MOTION_SENSOR(cros_ec_tcs3400_rgb, MOTIONSENSE_CHIP_TCS3400,	\
+		MOTIONSENSE_TYPE_LIGHT_RGB, tcs3400_rgb_drv, 0, 0)
diff --git a/zephyr/shim/src/motionsense_sensors.c b/zephyr/shim/src/motionsense_sensors.c
new file mode 100644
index 0000000000..b4f64d97ce
--- /dev/null
+++ b/zephyr/shim/src/motionsense_sensors.c
@@ -0,0 +1,472 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "accelgyro.h"
+#include "common.h"
+#include "cros_cbi.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "motionsense_sensors.h"
+
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(shim_cros_motionsense_sensors);
+
+#define SENSOR_MUTEX_NODE DT_PATH(motionsense_mutex)
+#define SENSOR_MUTEX_NAME(id) DT_CAT(MUTEX_, id)
+
+#if DT_NODE_EXISTS(SENSOR_MUTEX_NODE)
+#define DECLARE_SENSOR_MUTEX(id) K_MUTEX_DEFINE(SENSOR_MUTEX_NAME(id));
+
+/*
+ * Declare mutex for
+ * each child node of "/motionsense-mutex" node in DT.
+ *
+ * A mutex can be shared among the motion sensors.
+ */
+DT_FOREACH_CHILD(SENSOR_MUTEX_NODE, DECLARE_SENSOR_MUTEX)
+#endif /* DT_NODE_EXISTS(SENSOR_MUTEX_NODE) */
+
+#define MAT_ITEM(i, id) FLOAT_TO_FP((int32_t)(DT_PROP_BY_IDX(id, mat33, i)))
+#define DECLARE_SENSOR_ROT_REF(id)                                   \
+	const mat33_fp_t SENSOR_ROT_STD_REF_NAME(id) = {             \
+		{ FOR_EACH_FIXED_ARG(MAT_ITEM, (, ), id, 0, 1, 2) }, \
+		{ FOR_EACH_FIXED_ARG(MAT_ITEM, (, ), id, 3, 4, 5) }, \
+		{ FOR_EACH_FIXED_ARG(MAT_ITEM, (, ), id, 6, 7, 8) }, \
+	};
+
+/*
+ * Declare 3x3 rotation matrix for
+ * each child node of "/motionsense-rotation-ref" node in DT.
+ *
+ * A rotation matrix can be shared among the motion sensors.
+ */
+#if DT_NODE_EXISTS(SENSOR_ROT_REF_NODE)
+DT_FOREACH_CHILD(SENSOR_ROT_REF_NODE, DECLARE_SENSOR_ROT_REF)
+#endif
+
+#define SENSOR_BODYDETECT_NODE DT_PATH(motionsense_bodydetect)
+#define SENSOR_BODYDETECT_NAME(id) DT_CAT(BODYDETECT_, id)
+
+#define DECLARE_BODYDETECT_CONFIG(id)                                    \
+	const struct body_detect_params SENSOR_BODYDETECT_NAME(          \
+		DT_PARENT(id)) = {                                       \
+		.var_noise_factor = DT_PROP_OR(id, var_noise_factor, 0), \
+		.var_threshold = DT_PROP_OR(id, var_threshold, 0),       \
+		.confidence_delta = DT_PROP_OR(id, confidence_delta, 0), \
+	};
+
+/*
+ * Declare body detection parameters structure for each node with
+ * status = "okay" and compatible = "cros-ec,motionsense-bodydetect".
+ */
+DT_FOREACH_STATUS_OKAY(cros_ec_motionsense_bodydetect,
+		       DECLARE_BODYDETECT_CONFIG)
+
+/*
+ * Declare sensor driver data for
+ * each child node with status = "okay" of
+ * "/motionsense-sensor-data" node in DT.
+ *
+ * A driver data can be shared among the motion sensors.
+ */
+#define SENSOR_DATA_NAME(id) DT_CAT(SENSOR_DAT_, id)
+#define SENSOR_DATA_NODE DT_PATH(motionsense_sensor_data)
+
+#define SENSOR_DATA(inst, compat, create_data_macro) \
+	create_data_macro(DT_INST(inst, compat),     \
+			  SENSOR_DATA_NAME(DT_INST(inst, compat)))
+
+/*
+ * CREATE_SENSOR_DATA is a helper macro that gets
+ * compat and create_data_macro as parameters.
+ *
+ * For each node with compatible = "compat",
+ * CREATE_SENSOR_DATA expands "create_data_macro" macro with the node id and
+ * the designated name for the sensor driver data to be created. The
+ * "create_datda_macro" macro is responsible for creating the sensor driver
+ * data with the name.
+ *
+ * Sensor drivers should provide <chip>-drvinfo.inc file and, in the file,
+ * it should have the macro that creates its sensor driver data using device
+ * tree and pass the macro via CREATE_SENSOR_DATA.
+ *
+ * e.g) The below is contents of tcs3400-drvinfo.inc file. The file has
+ * CREATE_SENSOR_DATA_TCS3400_CLEAR that creates the static instance of
+ * "struct als_drv_data_t" with the given name and initializes it
+ * with device tree. Then use CREATE_SENSOR_DATA.
+ *
+ * ----------- bma255-drvinfo.inc -----------
+ * #define CREATE_SENSOR_DATA_TCS3400_CLEAR(id, drvdata_name)      \
+ *       static struct als_drv_data_t drvdata_name =               \
+ *           ACCELGYRO_ALS_DRV_DATA(DT_CHILD(id, als_drv_data));
+ *
+ * CREATE_SENSOR_DATA(cros_ec_drvdata_tcs3400_clear,   \
+ *                    CREATE_SENSOR_DATA_TCS3400_CLEAR)
+ */
+#define CREATE_SENSOR_DATA(compat, create_data_macro)                     \
+	LISTIFY(DT_NUM_INST_STATUS_OKAY(compat), SENSOR_DATA, (), compat, \
+		create_data_macro)
+
+/*
+ * sensor_drv_list.inc is included three times in this file. This is the first
+ * time and it is for creating sensor driver-specific data. So we ignore
+ * CREATE_MOTION_SENSOR() that creates motion sensor at this time.
+ */
+#define CREATE_MOTION_SENSOR(s_compat, s_chip, s_type, s_drv, s_min_freq, \
+			     s_max_freq)
+
+/*
+ * Here, we declare all sensor driver data. How to create the data is
+ * defined in <chip>-drvinfo.inc file and ,in turn, the file is included
+ * in sensor_drv_list.inc.
+ */
+#if DT_NODE_EXISTS(SENSOR_DATA_NODE)
+#include "motionsense_driver/sensor_drv_list.inc"
+#endif
+
+/*
+ * Get the address of the mutex which is referred by phandle.
+ * See motionsense-sensor-base.yaml and cros-ec,motionsense-mutex.yaml
+ * for DT example and details.
+ */
+#define SENSOR_MUTEX(id)                        \
+	IF_ENABLED(DT_NODE_HAS_PROP(id, mutex), \
+		   (.mutex = &SENSOR_MUTEX_NAME(DT_PHANDLE(id, mutex)), ))
+
+/*
+ * Set the interrupt pin which is referred by the phandle.
+ */
+#define SENSOR_INT_SIGNAL(id)                        \
+	IF_ENABLED(DT_NODE_HAS_PROP(id, int_signal), \
+		   (.int_signal = GPIO_SIGNAL(DT_PHANDLE(id, int_signal)), ))
+
+/*
+ * Set flags based on values defined in the node.
+ */
+#define SENSOR_FLAGS(id)                                        \
+	.flags = 0 IF_ENABLED(DT_NODE_HAS_PROP(id, int_signal), \
+			      (| MOTIONSENSE_FLAG_INT_SIGNAL)),
+
+/*
+ * Get I2C port number which is referred by phandle.
+ * See motionsense-sensor-base.yaml for DT example and details.
+ */
+#define SENSOR_I2C_PORT(id)                    \
+	IF_ENABLED(DT_NODE_HAS_PROP(id, port), \
+		   (.port = I2C_PORT(DT_PHANDLE(id, port)), ))
+
+/*
+ * Get I2C or SPI address.
+ * See motionsense-sensor-base.yaml for DT example and details.
+ */
+#define SENSOR_I2C_SPI_ADDR_FLAGS(id)                        \
+	IF_ENABLED(DT_NODE_HAS_PROP(id, i2c_spi_addr_flags), \
+		   (.i2c_spi_addr_flags =                    \
+			    DT_STRING_TOKEN(id, i2c_spi_addr_flags), ))
+
+/*
+ * Get the address of rotation matrix which is referred by phandle.
+ * See motionsense-sensor-base.yaml and cros-ec,motionsense-rotation-ref.yaml
+ * for DT example and details.
+ */
+#define SENSOR_ROT_STD_REF(id)                                    \
+	IF_ENABLED(DT_NODE_HAS_PROP(id, rot_standard_ref),        \
+		   (.rot_standard_ref = &SENSOR_ROT_STD_REF_NAME( \
+			    DT_PHANDLE(id, rot_standard_ref)), ))
+
+/*
+ * Get the address of driver-specific data which is referred by phandle.
+ * See motionsense-sensor-base.yaml for DT example and details.
+ */
+#define SENSOR_DRV_DATA(id)                        \
+	IF_ENABLED(DT_NODE_HAS_PROP(id, drv_data), \
+		   (.drv_data =                    \
+			    &SENSOR_DATA_NAME(DT_PHANDLE(id, drv_data)), ))
+
+/*
+ * Get the address of body detect specific data.
+ * See motionsense-sensor-base.yaml for DT example and details.
+ */
+#define SENSOR_BODYDETECT(id)                                \
+	IF_ENABLED(DT_NODE_EXISTS(DT_CHILD(id, bodydetect)), \
+		   (.bd_params = &SENSOR_BODYDETECT_NAME(id), ))
+
+/*
+ * Get odr and ec_rate for the motion sensor.
+ * See motionsense-sensor-base.yaml and cros-ec,motionsense-sensor-config.yaml
+ * for DT example and details.
+ */
+#define SET_CONFIG_EC(cfg_id, cfg_suffix)                                   \
+	[SENSOR_CONFIG_##cfg_suffix] = {                                    \
+		IF_ENABLED(DT_NODE_HAS_PROP(cfg_id, odr),                   \
+			   (.odr = DT_PROP(cfg_id, odr), ))                 \
+			IF_ENABLED(DT_NODE_HAS_PROP(cfg_id, ec_rate),       \
+				   (.ec_rate = DT_PROP(cfg_id, ec_rate), )) \
+	}
+
+/* Get configs */
+#define CREATE_SENSOR_CONFIG(cfgs_id)                                         \
+	.config = {                                                           \
+		IF_ENABLED(DT_NODE_EXISTS(DT_CHILD(cfgs_id, ap)),             \
+			   (SET_CONFIG_EC(DT_CHILD(cfgs_id, ap), AP), ))      \
+			IF_ENABLED(DT_NODE_EXISTS(DT_CHILD(cfgs_id, ec_s0)),  \
+				   (SET_CONFIG_EC(DT_CHILD(cfgs_id, ec_s0),   \
+						  EC_S0), ))                  \
+				IF_ENABLED(DT_NODE_EXISTS(                    \
+						   DT_CHILD(cfgs_id, ec_s3)), \
+					   (SET_CONFIG_EC(DT_CHILD(cfgs_id,   \
+								   ec_s3),    \
+							  EC_S3), ))          \
+					IF_ENABLED(DT_NODE_EXISTS(DT_CHILD(   \
+							   cfgs_id, ec_s5)),  \
+						   (SET_CONFIG_EC(            \
+							    DT_CHILD(cfgs_id, \
+								     ec_s5),  \
+							    EC_S5), ))        \
+	}
+
+#define SENSOR_CONFIG(id)                                 \
+	IF_ENABLED(DT_NODE_EXISTS(DT_CHILD(id, configs)), \
+		   (CREATE_SENSOR_CONFIG(DT_CHILD(id, configs)), ))
+
+/* Get and assign the basic information for a motion sensor */
+#define SENSOR_BASIC_INFO(id)                                                \
+	.name = DT_NODE_FULL_NAME(id),                                       \
+	.active_mask = DT_STRING_TOKEN(id, active_mask),                     \
+	.location = DT_STRING_TOKEN(id, location),                           \
+	.default_range = (int)(DT_PROP(id, default_range)),                  \
+	SENSOR_I2C_SPI_ADDR_FLAGS(id) SENSOR_MUTEX(id) SENSOR_I2C_PORT(id)   \
+		SENSOR_ROT_STD_REF(id) SENSOR_DRV_DATA(id) SENSOR_CONFIG(id) \
+			SENSOR_INT_SIGNAL(id) SENSOR_FLAGS(id)               \
+				SENSOR_BODYDETECT(id)
+
+/* Create motion sensor node with node ID */
+#define DO_MK_SENSOR_ENTRY(id, s_chip, s_type, s_drv, s_min_freq, s_max_freq) \
+	[SENSOR_ID(id)] = { SENSOR_BASIC_INFO(id).chip = s_chip,              \
+			    .type = s_type, .drv = &s_drv,                    \
+			    .min_frequency = s_min_freq,                      \
+			    .max_frequency = s_max_freq },
+
+/* Construct an entry iff the alternate_for property is missing. */
+#define MK_SENSOR_ENTRY(inst, s_compat, s_chip, s_type, s_drv, s_min_freq,    \
+			s_max_freq)                                           \
+	COND_CODE_0(DT_NODE_HAS_PROP(DT_INST(inst, s_compat), alternate_for), \
+		    (DO_MK_SENSOR_ENTRY(DT_INST(inst, s_compat), s_chip,      \
+					s_type, s_drv, s_min_freq,            \
+					s_max_freq)),                         \
+		    ())
+
+/* Construct an entry iff the alternate_for property exists. */
+#define MK_SENSOR_ALT_ENTRY(inst, s_compat, s_chip, s_type, s_drv, s_min_freq, \
+			    s_max_freq)                                        \
+	COND_CODE_1(DT_NODE_HAS_PROP(DT_INST(inst, s_compat), alternate_for),  \
+		    (DO_MK_SENSOR_ENTRY(DT_INST(inst, s_compat), s_chip,       \
+					s_type, s_drv, s_min_freq,             \
+					s_max_freq)),                          \
+		    ())
+
+#undef CREATE_SENSOR_DATA
+/*
+ * Sensor driver-specific data creation stage is already done. So this
+ * time we ignore CREATE_SENSOR_DATA().
+ */
+#define CREATE_SENSOR_DATA(compat, create_data_macro)
+#undef CREATE_MOTION_SENSOR
+
+/*
+ * CREATE_MOTION_SENSOR is a help macro that read the sensor information from
+ * device tree and creates an entry in motion_sensors array which is used
+ * by motion sense task. The help macro gets compatible value of the
+ * sensor node and several driver specific information like CHIP_ID,
+ * SENSOR_TYPE, driver instance name, and min/max frequency.
+ *
+ * <chip>-drvinfo.inc file which is provided by sensor driver should use
+ * CREATE_MOTION_SENSOR to provide driver specific information.
+ *
+ * e.g) The below is contents of tcs3400-drvinfo.inc file. The file has
+ * CREATE_MOTION_SENSOR like below to create the sensor entry. The file uses
+ * the help macro two times since the chip supports two functions
+ * ALS clear and ALS RGB.
+
+ * ------------- tcs3400-drvinfo.inc -------------
+ * // Here, we call CREATE_MOTION_SENSOR to create a motion_sensor_t entry
+ * // for each TCS3400 clear instance (compatible = "cros-ec,tcs3400-clear")
+ * // in device tree.
+ * CREATE_MOTION_SENSOR(cros_ec_tcs3400_clear, MOTIONSENSE_CHIP_TCS3400,   \
+ *       MOTIONSENSE_TYPE_LIGHT, tcs3400_drv,            \
+ *       TCS3400_LIGHT_MIN_FREQ, TCS3400_LIGHT_MAX_FREQ)
+
+ *
+ * // Here, we call CREATE_MOTION_SENSOR to create a motion_sensor_t entry
+ * // for each TCS3400 RGB instance (compatible = "cros-ec,tcs3400-rgb")
+ * // in device tree.
+ *
+ * CREATE_MOTION_SENSOR(cros_ec_tcs3400_rgb, MOTIONSENSE_CHIP_TCS3400, \
+ *       MOTIONSENSE_TYPE_LIGHT_RGB, tcs3400_rgb_drv, 0, 0)
+ * -----------------------------------------------
+ */
+#define CREATE_MOTION_SENSOR(s_compat, s_chip, s_type, s_drv, s_min_freq, \
+			     s_max_freq)                                  \
+	LISTIFY(DT_NUM_INST_STATUS_OKAY(s_compat), MK_SENSOR_ENTRY, (),   \
+		s_compat, s_chip, s_type, s_drv, s_min_freq, s_max_freq)
+
+/*
+ * Here, we include sensor_drv_list.inc AGAIN but this time it only
+ * uses CREATE_MOTION_SENSOR to create the motion sensor entries.
+ */
+struct motion_sensor_t motion_sensors[] = {
+#if DT_NODE_EXISTS(SENSOR_NODE)
+#include "motionsense_driver/sensor_drv_list.inc"
+#endif
+};
+
+/*
+ * Remap the CREATE_MOTION_SENSOR to call MK_SENSOR_ALT_ENTRY to create a list
+ * of alternate sensors that will be used at runtime.
+ */
+#undef CREATE_MOTION_SENSOR
+#define CREATE_MOTION_SENSOR(s_compat, s_chip, s_type, s_drv, s_min_freq,   \
+			     s_max_freq)                                    \
+	LISTIFY(DT_NUM_INST_STATUS_OKAY(s_compat), MK_SENSOR_ALT_ENTRY, (), \
+		s_compat, s_chip, s_type, s_drv, s_min_freq, s_max_freq)
+
+/*
+ * The list of alternate motion sensors that may be used at runtime to replace
+ * an entry in the motion_sensors array.
+ */
+__maybe_unused struct motion_sensor_t motion_sensors_alt[] = {
+#if DT_NODE_EXISTS(SENSOR_ALT_NODE)
+#include "motionsense_driver/sensor_drv_list.inc"
+#endif
+};
+
+#ifdef CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
+unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+#else
+const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+#endif
+
+/*
+ * Create a list of ALS sensors needed by motion sense
+ *
+ * The following example adds tcs3400 als sensor to motion_als_sensors array
+ *
+ * motionsense-sensors {
+ *         lid_accel: bma255 {
+ *             :
+ *         };
+ *             :
+ *             :
+ *         als_clear: tcs3400 {
+ *             :
+ *         };
+ * };
+ *
+ * motionsense-sensor-info {
+ *       compatible = "cros-ec,motionsense-sensor-info";
+ *
+ *       // list of entries for motion_als_sensors
+ *       als-sensors = <&als_clear>;
+ *                  :
+ *                  :
+ * };
+ */
+#if DT_NODE_HAS_PROP(SENSOR_INFO_NODE, als_sensors)
+#define ALS_SENSOR_ENTRY_WITH_COMMA(i, id) \
+	&motion_sensors[SENSOR_ID(DT_PHANDLE_BY_IDX(id, als_sensors, i))],
+const struct motion_sensor_t *motion_als_sensors[] = { LISTIFY(
+	DT_PROP_LEN(SENSOR_INFO_NODE, als_sensors), ALS_SENSOR_ENTRY_WITH_COMMA,
+	(), SENSOR_INFO_NODE) };
+BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
+#endif
+
+/*
+ * Enable interrupts for motion sensors
+ *
+ * e.g) list of named-gpio nodes
+ * motionsense-sensor-info {
+ *        compatible = "cros-ec,motionsense-sensor-info";
+ *
+ *         // list of GPIO interrupts that have to
+ *         // be enabled at initial stage
+ *        sensor-irqs = <&int_imu &int_als_rgb>;
+ * };
+ */
+#if DT_NODE_HAS_PROP(SENSOR_INFO_NODE, sensor_irqs)
+#define SENSOR_GPIO_ENABLE_INTERRUPT(i, id) \
+	gpio_enable_dt_interrupt(           \
+		GPIO_INT_FROM_NODE(DT_PHANDLE_BY_IDX(id, sensor_irqs, i)));
+static void sensor_enable_irqs(void){
+	LISTIFY(DT_PROP_LEN(SENSOR_INFO_NODE, sensor_irqs),
+		SENSOR_GPIO_ENABLE_INTERRUPT, (), SENSOR_INFO_NODE)
+} DECLARE_HOOK(HOOK_INIT, sensor_enable_irqs, HOOK_PRIO_DEFAULT);
+#endif
+
+/* Handle the alternative motion sensors */
+#define CHECK_SSFC_AND_ENABLE_ALT_SENSOR(id)                                 \
+	do {                                                                 \
+		if (cros_cbi_ssfc_check_match(CBI_SSFC_VALUE_ID(             \
+			    DT_PHANDLE(id, alternate_ssfc_indicator)))) {    \
+			LOG_INF("Replacing \"%s\" for \"%s\" based on SSFC", \
+				motion_sensors[SENSOR_ID(DT_PHANDLE(         \
+						       id, alternate_for))]  \
+					.name,                               \
+				motion_sensors_alt[SENSOR_ID(id)].name);     \
+			ENABLE_ALT_MOTION_SENSOR(id);                        \
+		}                                                            \
+	} while (0)
+
+#define ALT_SENSOR_CHECK_SSFC_ID(id)                                          \
+	COND_CODE_1(UTIL_AND(DT_NODE_HAS_PROP(id, alternate_for),             \
+			     DT_NODE_HAS_PROP(id, alternate_ssfc_indicator)), \
+		    (CHECK_SSFC_AND_ENABLE_ALT_SENSOR(id);), ())
+
+#if DT_NODE_EXISTS(SENSOR_ALT_NODE)
+
+int motion_sense_probe(enum sensor_alt_id alt_idx)
+{
+	int res;
+
+	LOG_INF("Probing \"%s\" chip %d type %d loc %d",
+		motion_sensors_alt[alt_idx].name,
+		motion_sensors_alt[alt_idx].chip,
+		motion_sensors_alt[alt_idx].type,
+		motion_sensors_alt[alt_idx].location);
+
+	__ASSERT(motion_sensors_alt[alt_idx].drv->probe != NULL,
+		 "No probing function for alt sensor: %d", alt_idx);
+	res = motion_sensors_alt[alt_idx].drv->probe(
+		&motion_sensors_alt[alt_idx]);
+	LOG_INF("%sfound\n", (res != EC_SUCCESS ? "not " : ""));
+
+	return res;
+}
+
+void motion_sensors_check_ssfc(void){
+	DT_FOREACH_CHILD(SENSOR_ALT_NODE, ALT_SENSOR_CHECK_SSFC_ID)
+}
+#endif /* DT_NODE_EXISTS(SENSOR_ALT_NODE) */
+
+#define DEF_MOTION_ISR_NAME_ENUM(id) \
+	DT_STRING_UPPER_TOKEN(DT_PHANDLE(id, int_signal), enum_name)
+#define DEF_MOTION_ISR_NAME_ENUM_WITH_SUFFIX(name) DT_CAT(name, _ISR)
+#define DEF_MOTION_ISR_NAME(id) \
+	DEF_MOTION_ISR_NAME_ENUM_WITH_SUFFIX(DEF_MOTION_ISR_NAME_ENUM(id))
+
+#define DEF_MOTION_ISR(id)                                               \
+	void DEF_MOTION_ISR_NAME(id)(enum gpio_signal signal)            \
+	{                                                                \
+		__ASSERT(motion_sensors[SENSOR_ID(id)].drv->interrupt,   \
+			 "No interrupt handler for signal: %x", signal); \
+		motion_sensors[SENSOR_ID(id)].drv->interrupt(signal);    \
+	}
+
+#define DEF_MOTION_CHECK_ISR(id) \
+	COND_CODE_1(DT_NODE_HAS_PROP(id, int_signal), (DEF_MOTION_ISR(id)), ())
+
+#if DT_NODE_EXISTS(SENSOR_NODE)
+DT_FOREACH_CHILD(SENSOR_NODE, DEF_MOTION_CHECK_ISR)
+#endif
diff --git a/zephyr/shim/src/panic.c b/zephyr/shim/src/panic.c
new file mode 100644
index 0000000000..28bb045fde
--- /dev/null
+++ b/zephyr/shim/src/panic.c
@@ -0,0 +1,213 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "builtin/assert.h"
+#include "common.h"
+#include "panic.h"
+#include "system_safe_mode.h"
+
+#include <zephyr/arch/cpu.h>
+#include <zephyr/fatal.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/logging/log_ctrl.h>
+
+/*
+ * Arch-specific configuration
+ *
+ * For each architecture, define:
+ * - PANIC_ARCH, which should be the corresponding arch field of the
+ *   panic_data struct.
+ * - PANIC_REG_LIST, which is a macro that takes a parameter M, and
+ *   applies M to 3-tuples of:
+ *   - zephyr esf field name
+ *   - panic_data struct field name
+ *   - human readable name
+ */
+
+#if defined(CONFIG_ARM)
+#define PANIC_ARCH PANIC_ARCH_CORTEX_M
+#if defined(CONFIG_EXTRA_EXCEPTION_INFO)
+#define EXTRA_PANIC_REG_LIST(M)                                              \
+	M(extra_info.callee->v1, cm.regs[CORTEX_PANIC_REGISTER_R4], v1)      \
+	M(extra_info.callee->v2, cm.regs[CORTEX_PANIC_REGISTER_R5], v2)      \
+	M(extra_info.callee->v3, cm.regs[CORTEX_PANIC_REGISTER_R6], v3)      \
+	M(extra_info.callee->v4, cm.regs[CORTEX_PANIC_REGISTER_R7], v4)      \
+	M(extra_info.callee->v5, cm.regs[CORTEX_PANIC_REGISTER_R8], v5)      \
+	M(extra_info.callee->v6, cm.regs[CORTEX_PANIC_REGISTER_R9], v6)      \
+	M(extra_info.callee->v7, cm.regs[CORTEX_PANIC_REGISTER_R10], v7)     \
+	M(extra_info.callee->v8, cm.regs[CORTEX_PANIC_REGISTER_R11], v8)     \
+	M(extra_info.callee->psp, cm.regs[CORTEX_PANIC_REGISTER_PSP], psp)   \
+	M(extra_info.exc_return, cm.regs[CORTEX_PANIC_REGISTER_LR], exc_rtn) \
+	M(extra_info.msp, cm.regs[CORTEX_PANIC_REGISTER_MSP], msp)
+/*
+ * IPSR is not copied. IPSR is a subset of xPSR, which is already
+ * captured in PANIC_REG_LIST.
+ */
+#else
+#define EXTRA_PANIC_REG_LIST(M)
+#endif
+/* TODO(b/245423691): Copy other status registers (e.g. CFSR) when available. */
+#define PANIC_REG_LIST(M)                \
+	M(basic.r0, cm.frame[0], a1)     \
+	M(basic.r1, cm.frame[1], a2)     \
+	M(basic.r2, cm.frame[2], a3)     \
+	M(basic.r3, cm.frame[3], a4)     \
+	M(basic.r12, cm.frame[4], ip)    \
+	M(basic.lr, cm.frame[5], lr)     \
+	M(basic.pc, cm.frame[6], pc)     \
+	M(basic.xpsr, cm.frame[7], xpsr) \
+	EXTRA_PANIC_REG_LIST(M)
+#define PANIC_REG_EXCEPTION(pdata) pdata->cm.regs[1]
+#define PANIC_REG_REASON(pdata) pdata->cm.regs[3]
+#define PANIC_REG_INFO(pdata) pdata->cm.regs[4]
+#elif defined(CONFIG_RISCV) && !defined(CONFIG_64BIT)
+/*
+ * Not all registers are passed in the context from Zephyr
+ * (see include/zephyr/arch/riscv/exp.h), in particular
+ * the mcause register is not saved (mstatus is saved instead).
+ * The assignments must match include/panic_defs.h
+ */
+#define PANIC_ARCH PANIC_ARCH_RISCV_RV32I
+#define PANIC_REG_LIST(M)         \
+	M(ra, riscv.regs[29], ra) \
+	M(a0, riscv.regs[26], a0) \
+	M(a1, riscv.regs[25], a1) \
+	M(a2, riscv.regs[24], a2) \
+	M(a3, riscv.regs[23], a3) \
+	M(a4, riscv.regs[22], a4) \
+	M(a5, riscv.regs[21], a5) \
+	M(a6, riscv.regs[20], a6) \
+	M(a7, riscv.regs[19], a7) \
+	M(t0, riscv.regs[18], t0) \
+	M(t1, riscv.regs[17], t1) \
+	M(t2, riscv.regs[16], t2) \
+	M(t3, riscv.regs[15], t3) \
+	M(t4, riscv.regs[14], t4) \
+	M(t5, riscv.regs[13], t5) \
+	M(t6, riscv.regs[12], t6) \
+	M(mepc, riscv.mepc, mepc) \
+	M(mstatus, riscv.mcause, mstatus)
+#define PANIC_REG_EXCEPTION(pdata) (pdata->riscv.mcause)
+#define PANIC_REG_REASON(pdata) (pdata->riscv.regs[11])
+#define PANIC_REG_INFO(pdata) (pdata->riscv.regs[10])
+#else
+/* Not implemented for this arch */
+#define PANIC_ARCH 0
+#define PANIC_REG_LIST(M)
+static uint8_t placeholder_exception_reg;
+static uint32_t placeholder_reason_reg;
+static uint32_t placeholder_info_reg;
+#define PANIC_REG_EXCEPTION(unused) placeholder_exception_reg
+#define PANIC_REG_REASON(unused) placeholder_reason_reg
+#define PANIC_REG_INFO(unused) placeholder_info_reg
+#endif
+
+/* Macros to be applied to PANIC_REG_LIST as M */
+#define PANIC_COPY_REGS(esf_field, pdata_field, human_name) \
+	pdata->pdata_field = esf->esf_field;
+#define PANIC_PRINT_REGS(esf_field, pdata_field, human_name) \
+	panic_printf("  %-8s = 0x%08X\n", #human_name, pdata->pdata_field);
+
+void panic_data_print(const struct panic_data *pdata)
+{
+	PANIC_REG_LIST(PANIC_PRINT_REGS);
+}
+
+static void copy_esf_to_panic_data(const z_arch_esf_t *esf,
+				   struct panic_data *pdata)
+{
+	pdata->arch = PANIC_ARCH;
+	pdata->struct_version = 2;
+	pdata->flags = (PANIC_ARCH == PANIC_ARCH_CORTEX_M) ?
+			       PANIC_DATA_FLAG_FRAME_VALID :
+			       0;
+	pdata->reserved = 0;
+	pdata->struct_size = sizeof(*pdata);
+	pdata->magic = PANIC_DATA_MAGIC;
+
+	PANIC_REG_LIST(PANIC_COPY_REGS);
+}
+
+void k_sys_fatal_error_handler(unsigned int reason, const z_arch_esf_t *esf)
+{
+	struct panic_data *pdata = get_panic_data_write();
+	/*
+	 * If CONFIG_LOG is on, the exception details
+	 * have already been logged to the console.
+	 */
+	if (!IS_ENABLED(CONFIG_LOG)) {
+		panic_printf("Fatal error: %u\n", reason);
+	}
+
+	if (PANIC_ARCH && esf) {
+		copy_esf_to_panic_data(esf, pdata);
+		if (!IS_ENABLED(CONFIG_LOG)) {
+			panic_data_print(panic_get_data());
+		}
+	}
+
+	LOG_PANIC();
+
+	/* Start system safe mode if possible */
+	if (IS_ENABLED(CONFIG_PLATFORM_EC_SYSTEM_SAFE_MODE)) {
+		if (reason != K_ERR_KERNEL_PANIC &&
+		    start_system_safe_mode() == EC_SUCCESS) {
+			/* Returning from k_sys_fatal_error_handler will cause
+			 * the faulting thread to be aborted and resume the
+			 * kernel
+			 */
+			pdata->flags |= PANIC_DATA_FLAG_SAFE_MODE_STARTED;
+			return;
+		}
+		pdata->flags |= PANIC_DATA_FLAG_SAFE_MODE_FAIL_PRECONDITIONS;
+	}
+
+	/*
+	 * Reboot immediately, don't wait for watchdog, otherwise
+	 * the watchdog will overwrite this panic.
+	 */
+	panic_reboot();
+	__ASSERT_UNREACHABLE;
+}
+
+void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
+{
+	struct panic_data *const pdata = get_panic_data_write();
+
+	/* Setup panic data structure */
+	memset(pdata, 0, CONFIG_PANIC_DATA_SIZE);
+	pdata->magic = PANIC_DATA_MAGIC;
+	pdata->struct_size = CONFIG_PANIC_DATA_SIZE;
+	pdata->struct_version = 2;
+	pdata->arch = PANIC_ARCH;
+
+	/* Log panic cause */
+	PANIC_REG_EXCEPTION(pdata) = exception;
+	PANIC_REG_REASON(pdata) = reason;
+	PANIC_REG_INFO(pdata) = info;
+
+	/* Allow architecture specific logic */
+	arch_panic_set_reason(reason, info, exception);
+}
+
+void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception)
+{
+	struct panic_data *const pdata = panic_get_data();
+
+	if (pdata && pdata->struct_version == 2) {
+		*exception = PANIC_REG_EXCEPTION(pdata);
+		*reason = PANIC_REG_REASON(pdata);
+		*info = PANIC_REG_INFO(pdata);
+	} else {
+		*exception = *reason = *info = 0;
+	}
+}
+
+__overridable void arch_panic_set_reason(uint32_t reason, uint32_t info,
+					 uint8_t exception)
+{
+	/* Default implementation, do nothing. */
+}
diff --git a/zephyr/shim/src/power.c b/zephyr/shim/src/power.c
new file mode 100644
index 0000000000..ab58cf391d
--- /dev/null
+++ b/zephyr/shim/src/power.c
@@ -0,0 +1,40 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "power.h"
+#include "power/power.h"
+
+#include <zephyr/sys/util.h>
+
+#define GEN_POWER_SIGNAL_STRUCT_ENTRY_GPIO(cid) \
+	DT_STRING_UPPER_TOKEN(DT_PROP(cid, power_gpio_pin), enum_name)
+#define GEN_POWER_SIGNAL_STRUCT_ENTRY_FLAGS(cid)              \
+	(DT_GPIO_FLAGS(DT_PROP(cid, power_gpio_pin), gpios) & \
+			 GPIO_ACTIVE_LOW ?                    \
+		 POWER_SIGNAL_ACTIVE_LOW :                    \
+		 POWER_SIGNAL_ACTIVE_HIGH)
+#define GEN_POWER_SIGNAL_STRUCT_ENTRY_NAME(cid) DT_PROP(cid, power_enum_name)
+
+#define GEN_POWER_SIGNAL_STRUCT_ENTRY(cid)                         \
+	{                                                          \
+		.gpio = GEN_POWER_SIGNAL_STRUCT_ENTRY_GPIO(cid),   \
+		.flags = GEN_POWER_SIGNAL_STRUCT_ENTRY_FLAGS(cid), \
+		.name = GEN_POWER_SIGNAL_STRUCT_ENTRY_NAME(cid)    \
+	}
+#define GEN_POWER_SIGNAL_STRUCT(cid) \
+	[GEN_POWER_SIGNAL_ENUM_ENTRY(cid)] = GEN_POWER_SIGNAL_STRUCT_ENTRY(cid),
+
+const struct power_signal_info power_signal_list[] = { DT_FOREACH_CHILD(
+	POWER_SIGNAL_LIST_NODE, GEN_POWER_SIGNAL_STRUCT) };
+BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
+
+/*
+ * Verify the number of required power-signals are specified in
+ * the DeviceTree
+ */
+#define POWER_SIGNALS_REQUIRED \
+	DT_PROP(POWER_SIGNAL_LIST_NODE, power_signals_required)
+BUILD_ASSERT(POWER_SIGNALS_REQUIRED == POWER_SIGNAL_COUNT);
diff --git a/zephyr/shim/src/power_host_sleep_api.c b/zephyr/shim/src/power_host_sleep_api.c
new file mode 100644
index 0000000000..95d9496782
--- /dev/null
+++ b/zephyr/shim/src/power_host_sleep_api.c
@@ -0,0 +1,75 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include <zephyr/kernel.h>
+
+#include <ap_power/ap_power_interface.h>
+#include <power_host_sleep.h>
+
+#ifndef CONFIG_AP_PWRSEQ_DRIVER
+static enum power_state
+translate_ap_power_state(enum power_states_ndsx ap_power_state)
+{
+	switch (ap_power_state) {
+	case SYS_POWER_STATE_S5:
+		return POWER_S5;
+	case SYS_POWER_STATE_S3:
+		return POWER_S3;
+#if CONFIG_AP_PWRSEQ_S0IX
+	case SYS_POWER_STATE_S0ix:
+		return POWER_S0ix;
+#endif
+	default:
+		return 0;
+	}
+}
+
+int ap_power_get_lazy_wake_mask(enum power_states_ndsx state,
+				host_event_t *mask)
+{
+	enum power_state st;
+
+	st = translate_ap_power_state(state);
+	if (!st)
+		return -EINVAL;
+	return get_lazy_wake_mask(st, mask);
+}
+#else
+#include "ap_power/ap_pwrseq.h"
+
+static enum power_state
+translate_ap_power_state(enum ap_pwrseq_state ap_power_state)
+{
+	switch (ap_power_state) {
+	case AP_POWER_STATE_S5:
+		return POWER_S5;
+	case AP_POWER_STATE_S3:
+		return POWER_S3;
+#if CONFIG_AP_PWRSEQ_S0IX
+	case AP_POWER_STATE_S0IX:
+		return POWER_S0ix;
+#endif
+	default:
+		return 0;
+	}
+}
+
+int ap_power_get_lazy_wake_mask(enum ap_pwrseq_state state, host_event_t *mask)
+{
+	enum power_state st;
+
+	st = translate_ap_power_state(state);
+	if (!st)
+		return -EINVAL;
+	return get_lazy_wake_mask(st, mask);
+}
+#endif /* CONFIG_AP_PWRSEQ_DRIVER */
+
+#if CONFIG_AP_PWRSEQ_HOST_SLEEP
+void power_chipset_handle_host_sleep_event(enum host_sleep_event state,
+					   struct host_sleep_event_context *ctx)
+{
+	ap_power_chipset_handle_host_sleep_event(state, ctx);
+}
+#endif
diff --git a/zephyr/shim/src/ppc.c b/zephyr/shim/src/ppc.c
new file mode 100644
index 0000000000..f4049b26cb
--- /dev/null
+++ b/zephyr/shim/src/ppc.c
@@ -0,0 +1,103 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "usbc/ppc.h"
+#include "usbc/ppc_aoz1380.h"
+#include "usbc/ppc_ktu1125.h"
+#include "usbc/ppc_nx20p348x.h"
+#include "usbc/ppc_rt1739.h"
+#include "usbc/ppc_sn5s330.h"
+#include "usbc/ppc_syv682x.h"
+#include "usbc_ppc.h"
+
+#include <zephyr/devicetree.h>
+
+#define PPC_CHIP_ENTRY(usbc_id, ppc_id, config_fn) \
+	[USBC_PORT_NEW(usbc_id)] = config_fn(ppc_id),
+
+#define CHECK_COMPAT(compat, usbc_id, ppc_id, config_fn) \
+	COND_CODE_1(DT_NODE_HAS_COMPAT(ppc_id, compat),  \
+		    (PPC_CHIP_ENTRY(usbc_id, ppc_id, config_fn)), ())
+
+/**
+ * @param driver Tuple containing the PPC (compatible, config) pair.
+ * @param nodes Tuple containing the (usbc_node_id, ppc_node_id) pair
+ */
+#define CHECK_COMPAT_HELPER(driver, nodes)                                     \
+	CHECK_COMPAT(USBC_DRIVER_GET_COMPAT(driver), NODES_GET_USBC_ID(nodes), \
+		     NODES_GET_PROP_ID(nodes), USBC_DRIVER_GET_CONFIG(driver))
+
+#define PPC_CHIP_FIND(usbc_id, ppc_id)                                 \
+	FOR_EACH_FIXED_ARG(CHECK_COMPAT_HELPER, (), (usbc_id, ppc_id), \
+			   PPC_DRIVERS)
+
+/*
+ * This macro gets invoked for every driver in the PPC_DRIVERS list.
+ * If the passed in ppc node contains the specified compat string, then
+ * this macro returns 1.  Otherwise the macro returns nothing (EMPTY).
+ */
+#define PPC_HAS_COMPAT(compat, ppc) \
+	IF_ENABLED(DT_NODE_HAS_COMPAT(ppc, compat), 1)
+
+/*
+ * Verify the compatible property of a PPC node is valid.
+ *
+ * Call PPC_HAS_COMPAT() for all PPC compatible strings listed in the
+ * PPC_DRIVERS list.  If the resulting list is empty, then there was no
+ * matching PPC driver found and this macro generates a build error.
+ */
+#define PPC_PROP_COMPATIBLE_VERIFY(ppc)                                        \
+	IF_ENABLED(                                                            \
+		IS_EMPTY(FOR_EACH_FIXED_ARG(PPC_HAS_COMPAT, (), ppc,           \
+					    PPC_DRIVER_COMPATS)),              \
+		(BUILD_ASSERT(0, "Invalid PPC compatible on node: " STRINGIFY( \
+					 ppc));))
+
+/* clang-format off */
+#define PPC_CHIP_STUB(usbc_id) \
+	[USBC_PORT_NEW(usbc_id)] = {},
+/* clang-format on */
+
+#define PPC_CHIP(usbc_id)                                               \
+	COND_CODE_1(DT_NODE_HAS_PROP(usbc_id, ppc),                     \
+		    (PPC_CHIP_FIND(usbc_id, DT_PHANDLE(usbc_id, ppc))), \
+		    (PPC_CHIP_STUB(usbc_id)))
+
+#define PPC_CHIP_VERIFY(usbc_id)                   \
+	IF_ENABLED(DT_NODE_HAS_PROP(usbc_id, ppc), \
+		   (PPC_PROP_COMPATIBLE_VERIFY(DT_PHANDLE(usbc_id, ppc))))
+
+#define PPC_CHIP_ALT(usbc_id)                                               \
+	COND_CODE_1(DT_NODE_HAS_PROP(usbc_id, ppc_alt),                     \
+		    (PPC_CHIP_FIND(usbc_id, DT_PHANDLE(usbc_id, ppc_alt))), \
+		    ())
+
+/*
+ * The PPC_CHIP_VERIFY macro expands to nothing when the PPC driver
+ * compatible string is found in the PPC_DRIVER_COMPATS list.  Otherwise the
+ * macro expands to a BUILD_ASSERT error.
+ */
+DT_FOREACH_STATUS_OKAY(named_usbc_port, PPC_CHIP_VERIFY)
+
+struct ppc_config_t ppc_chips[] = { DT_FOREACH_STATUS_OKAY(named_usbc_port,
+							   PPC_CHIP) };
+
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+struct ppc_config_t ppc_chips_alt[] = { DT_FOREACH_STATUS_OKAY(named_usbc_port,
+							       PPC_CHIP_ALT) };
+
+#define PPC_ALT_DEFINITION(node_id, config_fn) \
+	const struct ppc_config_t PPC_ALT_NAME_GET(node_id) = config_fn(node_id)
+
+#define PPC_ALT_DEFINE(node_id, config_fn)          \
+	COND_CODE_1(DT_PROP_OR(node_id, is_alt, 0), \
+		    (PPC_ALT_DEFINITION(node_id, config_fn);), ())
+
+/*
+ * Define a global struct ppc_config_t for every PPC node in the tree with the
+ * "is-alt" property set.
+ */
+DT_FOREACH_USBC_DRIVER_STATUS_OK_VARGS(PPC_ALT_DEFINE, PPC_DRIVERS)
diff --git a/zephyr/shim/src/pwm_hc.c b/zephyr/shim/src/pwm_hc.c
new file mode 100644
index 0000000000..3c7b2f1737
--- /dev/null
+++ b/zephyr/shim/src/pwm_hc.c
@@ -0,0 +1,109 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "console.h"
+#include "drivers/cros_displight.h"
+#include "ec_commands.h"
+#include "host_command.h"
+#include "keyboard_backlight.h"
+#include "pwm.h"
+#include "util.h"
+
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/pwm.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(pwm_shim, LOG_LEVEL_ERR);
+
+#define HAS_PWM_GENERIC_CHANNEL(compat)                         \
+	DT_NODE_HAS_PROP(DT_COMPAT_GET_ANY_STATUS_OKAY(compat), \
+			 generic_pwm_channel)
+
+#define PWM_GENERIC_CHANNEL_ID(compat) \
+	DT_PROP(DT_COMPAT_GET_ANY_STATUS_OKAY(compat), generic_pwm_channel)
+
+#ifdef CONFIG_PWM_KBLIGHT
+static bool pwm_is_kblight(int type, int index)
+{
+	if (type == EC_PWM_TYPE_KB_LIGHT)
+		return true;
+
+#if HAS_PWM_GENERIC_CHANNEL(cros_ec_kblight_pwm)
+	if (type == EC_PWM_TYPE_GENERIC &&
+	    index == PWM_GENERIC_CHANNEL_ID(cros_ec_kblight_pwm))
+		return true;
+#endif /* HAS_PWM_GENERIC_CHANNEL(cros_ec_kblight_pwm) */
+
+	return false;
+}
+#endif /* CONFIG_PWM_KBLIGHT */
+
+#ifdef CONFIG_PLATFORM_EC_PWM_DISPLIGHT
+static bool pwm_is_displight(int type, int index)
+{
+	if (type == EC_PWM_TYPE_DISPLAY_LIGHT)
+		return true;
+
+#if HAS_PWM_GENERIC_CHANNEL(cros_ec_displight)
+	if (type == EC_PWM_TYPE_GENERIC &&
+	    index == PWM_GENERIC_CHANNEL_ID(cros_ec_displight))
+		return true;
+#endif /* HAS_PWM_GENERIC_CHANNEL(cros_ec_displight) */
+
+	return false;
+}
+#endif /* CONFIG_PLATFORM_EC_PWM_DISPLIGHT */
+
+static enum ec_status
+host_command_pwm_set_duty(struct host_cmd_handler_args *args)
+{
+	__maybe_unused const struct ec_params_pwm_set_duty *p = args->params;
+
+#ifdef CONFIG_PLATFORM_EC_PWM_KBLIGHT
+	if (pwm_is_kblight(p->pwm_type, p->index)) {
+		kblight_set(PWM_RAW_TO_PERCENT(p->duty));
+		kblight_enable(p->duty > 0);
+		return EC_RES_SUCCESS;
+	}
+#endif
+#ifdef CONFIG_PLATFORM_EC_PWM_DISPLIGHT
+	if (pwm_is_displight(p->pwm_type, p->index)) {
+		displight_set(PWM_RAW_TO_PERCENT(p->duty));
+		return EC_RES_SUCCESS;
+	}
+#endif
+
+	return EC_RES_INVALID_PARAM;
+}
+DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_DUTY, host_command_pwm_set_duty,
+		     EC_VER_MASK(0));
+
+static enum ec_status
+host_command_pwm_get_duty(struct host_cmd_handler_args *args)
+{
+	__maybe_unused const struct ec_params_pwm_get_duty *p = args->params;
+	__maybe_unused struct ec_response_pwm_get_duty *r = args->response;
+
+#ifdef CONFIG_PLATFORM_EC_PWM_KBLIGHT
+	if (pwm_is_kblight(p->pwm_type, p->index)) {
+		r->duty = PWM_PERCENT_TO_RAW(kblight_get());
+		args->response_size = sizeof(*r);
+		return EC_RES_SUCCESS;
+	}
+#endif
+#ifdef CONFIG_PLATFORM_EC_PWM_DISPLIGHT
+	if (pwm_is_displight(p->pwm_type, p->index)) {
+		r->duty = PWM_PERCENT_TO_RAW(displight_get());
+		args->response_size = sizeof(*r);
+		return EC_RES_SUCCESS;
+	}
+#endif
+
+	return EC_RES_INVALID_PARAM;
+}
+DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_DUTY, host_command_pwm_get_duty,
+		     EC_VER_MASK(0));
diff --git a/zephyr/shim/src/pwm_led.c b/zephyr/shim/src/pwm_led.c
new file mode 100644
index 0000000000..81cc3a9c28
--- /dev/null
+++ b/zephyr/shim/src/pwm_led.c
@@ -0,0 +1,224 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define DT_DRV_COMPAT cros_ec_pwm_leds
+
+#include <string.h>
+
+#include <zephyr/devicetree.h>
+
+#if DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT)
+
+#include "charge_manager.h"
+#include "common.h"
+#include "ec_commands.h"
+#include "hooks.h"
+#include "led_common.h"
+#include "led_pwm.h"
+#include "util.h"
+
+LOG_MODULE_REGISTER(pwm_led, LOG_LEVEL_ERR);
+
+BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) <= 1,
+	     "Multiple CrOS EC PWM LED instances defined");
+
+#define PWM_LEDS_LEN DT_INST_PROP_LEN(0, leds)
+BUILD_ASSERT((PWM_LEDS_LEN > 0) && (PWM_LEDS_LEN <= 2),
+	     "Unsupported number of LEDs defined");
+
+#define PWM_LED_0_0_PERIOD \
+	DT_PWMS_PERIOD_BY_IDX(DT_INST_PHANDLE_BY_IDX(0, leds, 0), 0)
+#define PWM_LED_PERIOD_BUILD_ASSERT(node_id, prop, idx, ...)      \
+	BUILD_ASSERT(PWM_LED_0_0_PERIOD ==                        \
+			     DT_PWMS_PERIOD_BY_IDX(node_id, idx), \
+		     "PWM LED period mismatch");
+#define PWM_LEDS_BUILD_ASSERT(node_id, prop, idx)                         \
+	DT_FOREACH_PROP_ELEM_VARGS(DT_PHANDLE_BY_IDX(node_id, prop, idx), \
+				   pwms, PWM_LED_PERIOD_BUILD_ASSERT)
+
+DT_INST_FOREACH_PROP_ELEM(0, leds, PWM_LEDS_BUILD_ASSERT)
+
+#define PWM_LED_NAME(node_id) DT_STRING_UPPER_TOKEN(node_id, ec_led_name)
+
+const enum ec_led_id supported_led_ids[] = { DT_INST_FOREACH_CHILD_SEP(
+	0, PWM_LED_NAME, (, )) };
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+BUILD_ASSERT(ARRAY_SIZE(supported_led_ids) == DT_INST_PROP_LEN(0, leds),
+	     "Mismatch count of LED device phandles and LED name map entries.");
+
+static void pwm_led_set_duty(const struct pwm_dt_spec *pwm, int percent)
+{
+	uint32_t pulse_ns;
+	int rv;
+
+	if (!device_is_ready(pwm->dev)) {
+		LOG_ERR("PWM device %s not ready", pwm->dev->name);
+		return;
+	}
+
+	pulse_ns = DIV_ROUND_NEAREST(pwm->period * percent, 100);
+
+	LOG_DBG("LED PWM %s set percent (%d), pulse %d", pwm->dev->name,
+		percent, pulse_ns);
+
+	rv = pwm_set_pulse_dt(pwm, pulse_ns);
+	if (rv) {
+		LOG_ERR("pwm_set_pulse_dt() failed %s (%d)", pwm->dev->name,
+			rv);
+	}
+}
+
+#define PWM_CHANNEL_DT_BY_IDX(node_id, prop, idx, led_ch)                     \
+	static const struct pwm_dt_spec _pwm_dt_spec_##idx##_ch_##led_ch =    \
+		PWM_DT_SPEC_GET_BY_IDX(DT_PHANDLE_BY_IDX(node_id, prop, idx), \
+				       led_ch);
+
+#define PWM_CHANNEL_DT_BY_IDX_COND(node_id, prop, idx, led_ch)            \
+	IF_ENABLED(DT_PROP_HAS_IDX(DT_PHANDLE_BY_IDX(node_id, prop, idx), \
+				   pwms, led_ch),                         \
+		   (PWM_CHANNEL_DT_BY_IDX(node_id, prop, idx, led_ch)))
+
+#define PWM_LED_DT_INIT(node_id, prop, idx)               \
+	PWM_CHANNEL_DT_BY_IDX_COND(node_id, prop, idx, 0) \
+	PWM_CHANNEL_DT_BY_IDX_COND(node_id, prop, idx, 1) \
+	PWM_CHANNEL_DT_BY_IDX_COND(node_id, prop, idx, 2)
+
+DT_INST_FOREACH_PROP_ELEM(0, leds, PWM_LED_DT_INIT)
+
+#define PWM_CHANNEL_BY_IDX_COND(node_id, prop, idx, led_ch)                \
+	COND_CODE_1(DT_PROP_HAS_IDX(DT_PHANDLE_BY_IDX(node_id, prop, idx), \
+				    pwms, led_ch),                         \
+		    (&_pwm_dt_spec_##idx##_ch_##led_ch), (PWM_LED_NO_CHANNEL))
+
+#define PWM_LED_INIT(node_id, prop, idx)                               \
+	[PWM_LED##idx] = {                                             \
+		.ch0 = PWM_CHANNEL_BY_IDX_COND(node_id, prop, idx, 0), \
+		.ch1 = PWM_CHANNEL_BY_IDX_COND(node_id, prop, idx, 1), \
+		.ch2 = PWM_CHANNEL_BY_IDX_COND(node_id, prop, idx, 2), \
+		.set_duty = &pwm_led_set_duty,                         \
+	},
+
+struct pwm_led pwm_leds[] = { DT_INST_FOREACH_PROP_ELEM(0, leds,
+							PWM_LED_INIT) };
+
+#define EC_LED_COLOR_BLANK \
+	{                  \
+		0          \
+	}
+
+struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = {
+	[EC_LED_COLOR_RED] =
+		DT_INST_PROP_OR(0, color_map_red, EC_LED_COLOR_BLANK),
+	[EC_LED_COLOR_GREEN] =
+		DT_INST_PROP_OR(0, color_map_green, EC_LED_COLOR_BLANK),
+	[EC_LED_COLOR_BLUE] =
+		DT_INST_PROP_OR(0, color_map_blue, EC_LED_COLOR_BLANK),
+	[EC_LED_COLOR_YELLOW] =
+		DT_INST_PROP_OR(0, color_map_yellow, EC_LED_COLOR_BLANK),
+	[EC_LED_COLOR_WHITE] =
+		DT_INST_PROP_OR(0, color_map_white, EC_LED_COLOR_BLANK),
+	[EC_LED_COLOR_AMBER] =
+		DT_INST_PROP_OR(0, color_map_amber, EC_LED_COLOR_BLANK),
+};
+
+BUILD_ASSERT(DT_INST_PROP_LEN(0, brightness_range) == EC_LED_COLOR_COUNT,
+	     "brightness_range must have exactly EC_LED_COLOR_COUNT values");
+
+static const uint8_t dt_brigthness_range[EC_LED_COLOR_COUNT] =
+	DT_INST_PROP(0, brightness_range);
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	/* led_id is ignored, same ranges for all LEDs */
+	memcpy(brightness_range, dt_brigthness_range,
+	       sizeof(dt_brigthness_range));
+}
+
+#define PWM_NAME_TO_ID(node_id)                \
+	case PWM_LED_NAME(node_id):            \
+		pwm_id = DT_REG_ADDR(node_id); \
+		break;
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	enum pwm_led_id pwm_id;
+
+	switch (led_id) {
+		DT_INST_FOREACH_CHILD(0, PWM_NAME_TO_ID)
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+
+	if (DT_INST_NODE_HAS_PROP(0, color_map_red) &&
+	    brightness[EC_LED_COLOR_RED]) {
+		set_pwm_led_color(pwm_id, EC_LED_COLOR_RED);
+	} else if (DT_INST_NODE_HAS_PROP(0, color_map_green) &&
+		   brightness[EC_LED_COLOR_GREEN]) {
+		set_pwm_led_color(pwm_id, EC_LED_COLOR_GREEN);
+	} else if (DT_INST_NODE_HAS_PROP(0, color_map_blue) &&
+		   brightness[EC_LED_COLOR_BLUE]) {
+		set_pwm_led_color(pwm_id, EC_LED_COLOR_BLUE);
+	} else if (DT_INST_NODE_HAS_PROP(0, color_map_yellow) &&
+		   brightness[EC_LED_COLOR_YELLOW]) {
+		set_pwm_led_color(pwm_id, EC_LED_COLOR_YELLOW);
+	} else if (DT_INST_NODE_HAS_PROP(0, color_map_white) &&
+		   brightness[EC_LED_COLOR_WHITE]) {
+		set_pwm_led_color(pwm_id, EC_LED_COLOR_WHITE);
+	} else if (DT_INST_NODE_HAS_PROP(0, color_map_amber) &&
+		   brightness[EC_LED_COLOR_AMBER]) {
+		set_pwm_led_color(pwm_id, EC_LED_COLOR_AMBER);
+	} else {
+		/* Otherwise, the "color" is "off". */
+		set_pwm_led_color(pwm_id, -1);
+	}
+
+	return EC_SUCCESS;
+}
+
+#if DT_INST_NODE_HAS_PROP(0, sidesel)
+
+BUILD_ASSERT((PWM_LED_0_0_PERIOD * 2) ==
+		     DT_PWMS_PERIOD(DT_INST_PROP(0, sidesel)),
+	     "Sidesel PWM period not properly set");
+
+static const struct pwm_dt_spec _pwm_dt_spec_sidesel =
+	PWM_DT_SPEC_GET_BY_IDX(DT_INST_PROP(0, sidesel), 0);
+
+/* Illuminates the LED on the side of the active charging port. If not charging,
+ * illuminates both LEDs.
+ */
+static void led_set_charge_port_tick(void)
+{
+	int port;
+	int side_select_duty;
+
+	port = charge_manager_get_active_charge_port();
+	switch (port) {
+	case 0:
+		side_select_duty = 100;
+		break;
+	case 1:
+		side_select_duty = 0;
+		break;
+	default:
+		side_select_duty = 50;
+	}
+
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		pwm_led_set_duty(&_pwm_dt_spec_sidesel, side_select_duty);
+}
+DECLARE_HOOK(HOOK_TICK, led_set_charge_port_tick, HOOK_PRIO_DEFAULT);
+
+static void board_led_init(void)
+{
+	/* Illuminate motherboard and daughter board LEDs equally to start. */
+	pwm_led_set_duty(&_pwm_dt_spec_sidesel, 50);
+}
+DECLARE_HOOK(HOOK_INIT, board_led_init, HOOK_PRIO_DEFAULT);
+
+#endif /* DT_INST_NODE_HAS_PROP(0, sidesel) */
+
+#endif /* DT_HAS_COMPAT_STATUS_OKAY */
diff --git a/zephyr/shim/src/random.c b/zephyr/shim/src/random.c
new file mode 100644
index 0000000000..a18d83066e
--- /dev/null
+++ b/zephyr/shim/src/random.c
@@ -0,0 +1,69 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "host_command.h"
+#include "printf.h"
+#include "system.h"
+
+#include <zephyr/drivers/entropy.h>
+#include <zephyr/kernel.h>
+
+#define rng DEVICE_DT_GET(DT_CHOSEN(zephyr_entropy))
+
+void trng_rand_bytes(void *buffer, size_t len)
+{
+	/*
+	 * In EC, we use size_t to represent buffer size, but Zephyr uses
+	 * uint16_t. Crash the system if user requested more than UINT16_MAX
+	 * bytes.
+	 */
+	if (!device_is_ready(rng) || len > UINT16_MAX)
+		k_oops();
+
+	if (entropy_get_entropy(rng, (uint8_t *)buffer, (uint16_t)len))
+		k_oops();
+}
+
+#if defined(CONFIG_PLATFORM_EC_CONSOLE_CMD_RAND)
+static int command_rand(const struct shell *shell, int argc, const char **argv)
+{
+	uint8_t data[32];
+	char str_buf[hex_str_buf_size(sizeof(data))];
+
+	trng_rand_bytes(data, sizeof(data));
+
+	snprintf_hex_buffer(str_buf, sizeof(str_buf),
+			    HEX_BUF(data, sizeof(data)));
+	shell_fprintf(shell, SHELL_NORMAL, "rand %s\n", str_buf);
+
+	return EC_SUCCESS;
+}
+SHELL_CMD_REGISTER(rand, NULL, "Output random bytes to console.", command_rand);
+#endif
+
+#if defined(CONFIG_PLATFORM_EC_HOSTCMD_RAND)
+static enum ec_status host_command_rand(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_rand_num *p = args->params;
+	struct ec_response_rand_num *r = args->response;
+	uint16_t num_rand_bytes = p->num_rand_bytes;
+
+	if (system_is_locked())
+		return EC_RES_ACCESS_DENIED;
+
+	if (num_rand_bytes > args->response_max)
+		return EC_RES_OVERFLOW;
+
+	trng_rand_bytes(r->rand, num_rand_bytes);
+
+	args->response_size = num_rand_bytes;
+
+	return EC_RES_SUCCESS;
+}
+
+DECLARE_HOST_COMMAND(EC_CMD_RAND_NUM, host_command_rand,
+		     EC_VER_MASK(EC_VER_RAND_NUM));
+#endif
diff --git a/zephyr/shim/src/register_memory_dump.c b/zephyr/shim/src/register_memory_dump.c
new file mode 100644
index 0000000000..9e150f07a4
--- /dev/null
+++ b/zephyr/shim/src/register_memory_dump.c
@@ -0,0 +1,55 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "ec_tasks.h"
+#include "hooks.h"
+#include "host_command_memory_dump.h"
+#include "string.h"
+
+#include <zephyr/arch/cpu.h>
+#include <zephyr/kernel.h>
+#include <zephyr/kernel/thread.h>
+
+static bool task_is_excluded_from_memory_dump(task_id_t task_id)
+{
+	/* List of sensitive threads that must be excluded from memory dump */
+	static const task_id_t memory_dump_exclude_tasks[] = {
+		COND_CODE_1(CONFIG_HAS_TASK_KEYSCAN, (TASK_ID_KEYSCAN), ()),
+		COND_CODE_1(CONFIG_HAS_TASK_KEYPROTO, (TASK_ID_KEYPROTO), ()),
+		COND_CODE_1(CONFIG_HAS_TASK_WOV, (TASK_ID_WOV), ())
+	};
+	for (int i = 0; i < ARRAY_SIZE(memory_dump_exclude_tasks); i++) {
+		if (task_id == memory_dump_exclude_tasks[i]) {
+			return true;
+		}
+	}
+	return false;
+}
+
+test_export_static void register_thread_memory_dump(k_tid_t thread)
+{
+	register_memory_dump(thread->stack_info.start,
+			     thread->stack_info.size -
+				     thread->stack_info.delta);
+}
+
+test_export_static void register_known_threads_memory_dump(void)
+{
+	k_tid_t thread;
+
+	for (task_id_t task_id = 0; task_id < TASK_ID_COUNT + EXTRA_TASK_COUNT;
+	     task_id++) {
+		if (task_is_excluded_from_memory_dump(task_id)) {
+			continue;
+		}
+		thread = task_id_to_thread_id(task_id);
+		if (thread == NULL) {
+			continue;
+		}
+		register_thread_memory_dump(thread);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, register_known_threads_memory_dump, HOOK_PRIO_FIRST);
diff --git a/zephyr/shim/src/rtc.c b/zephyr/shim/src/rtc.c
new file mode 100644
index 0000000000..b3d2be1086
--- /dev/null
+++ b/zephyr/shim/src/rtc.c
@@ -0,0 +1,239 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "drivers/cros_rtc.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "system.h"
+#include "util.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(shim_cros_rtc, LOG_LEVEL_ERR);
+
+#define CROS_RTC_NODE DT_CHOSEN(cros_rtc)
+static const struct device *cros_rtc_dev;
+
+#ifdef CONFIG_HOSTCMD_EVENTS
+static void set_rtc_host_event(void)
+{
+	host_set_single_event(EC_HOST_EVENT_RTC);
+}
+DECLARE_DEFERRED(set_rtc_host_event);
+#endif
+
+void rtc_callback(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	if (IS_ENABLED(CONFIG_HOSTCMD_EVENTS)) {
+		hook_call_deferred(&set_rtc_host_event_data, 0);
+	}
+}
+
+/** Initialize the rtc. */
+static int system_init_rtc(void)
+{
+	cros_rtc_dev = DEVICE_DT_GET(CROS_RTC_NODE);
+	if (!cros_rtc_dev) {
+		LOG_ERR("Error: device %s is not ready", cros_rtc_dev->name);
+		return -ENODEV;
+	}
+
+	/* set the RTC callback */
+	cros_rtc_configure(cros_rtc_dev, rtc_callback);
+
+	return 0;
+}
+SYS_INIT(system_init_rtc, APPLICATION, 1);
+
+uint32_t system_get_rtc_sec(void)
+{
+	uint32_t seconds;
+
+	cros_rtc_get_value(cros_rtc_dev, &seconds);
+
+	return seconds;
+}
+
+void system_set_rtc(uint32_t seconds)
+{
+	cros_rtc_set_value(cros_rtc_dev, seconds);
+}
+
+void system_reset_rtc_alarm(void)
+{
+	if (!cros_rtc_dev) {
+		/* TODO(b/183115086): check the error handler for NULL device */
+		LOG_ERR("rtc_dev hasn't initialized.");
+		return;
+	}
+
+	cros_rtc_reset_alarm(cros_rtc_dev);
+}
+
+/*
+ * For NPCX series, The alarm counter only stores wakeup time in seconds.
+ * Microseconds will be ignored.
+ */
+void system_set_rtc_alarm(uint32_t seconds, uint32_t microseconds)
+{
+	if (!cros_rtc_dev) {
+		LOG_ERR("rtc_dev hasn't initialized.");
+		return;
+	}
+
+	/* If time = 0, clear the current alarm */
+	if (seconds == EC_RTC_ALARM_CLEAR && microseconds == 0) {
+		system_reset_rtc_alarm();
+		return;
+	}
+
+	/*
+	 * Adding 1 additional second because system_get_rtc_sec
+	 * returns the number of seconds truncated to the nearest
+	 * integer. This results in missed alarms if the actual
+	 * value is 7.99 seconds and 7 seconds is returned.
+	 */
+	seconds += system_get_rtc_sec() + 1;
+
+	cros_rtc_set_alarm(cros_rtc_dev, seconds, microseconds);
+}
+
+/*
+ * Return the seconds remaining before the RTC alarm goes off.
+ * Returns 0 if alarm is not set.
+ */
+uint32_t system_get_rtc_alarm(void)
+{
+	uint32_t seconds, microseconds;
+
+	cros_rtc_get_alarm(cros_rtc_dev, &seconds, &microseconds);
+
+	/*
+	 * Return 0:
+	 * 1. If alarm is not set to go off, OR
+	 * 2. If alarm is set and has already gone off
+	 */
+	if (seconds == 0) {
+		return 0;
+	}
+
+	return seconds - system_get_rtc_sec();
+}
+
+/* Console commands */
+void print_system_rtc(enum console_channel ch)
+{
+	uint32_t sec = system_get_rtc_sec();
+
+	cprintf(ch, "RTC: 0x%08x (%d.00 s)\n", sec, sec);
+}
+
+/*
+ * TODO(b/179055201): This is similar to the same function in some of the
+ * chip-specific code. We should factor out the common parts.
+ */
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_RTC
+static int command_system_rtc(int argc, const char **argv)
+{
+	if (argc == 3 && !strcasecmp(argv[1], "set")) {
+		char *e;
+		unsigned int t = strtoi(argv[2], &e, 0);
+
+		if (*e)
+			return EC_ERROR_PARAM2;
+
+		system_set_rtc(t);
+	} else if (argc > 1) {
+		return EC_ERROR_INVAL;
+	}
+
+	print_system_rtc(CC_COMMAND);
+
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(rtc, command_system_rtc, "[set <seconds>]",
+			"Get/set real-time clock");
+
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_RTC_ALARM
+/**
+ * Test the RTC alarm by setting an interrupt on RTC match.
+ */
+static int command_rtc_alarm_test(int argc, const char **argv)
+{
+	int s = 1, us = 0;
+	char *e;
+
+	if (argc > 1) {
+		s = strtoi(argv[1], &e, 10);
+		if (*e)
+			return EC_ERROR_PARAM1;
+	}
+	if (argc > 2) {
+		us = strtoi(argv[2], &e, 10);
+		if (*e)
+			return EC_ERROR_PARAM2;
+	}
+
+	ccprintf("Setting RTC alarm\n");
+
+	system_set_rtc_alarm(s, us);
+
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(rtc_alarm, command_rtc_alarm_test,
+			"[seconds [microseconds]]", "Test alarm");
+#endif /* CONFIG_PLATFORM_EC_CONSOLE_CMD_RTC_ALARM */
+#endif /* CONFIG_PLATFORM_EC_CONSOLE_CMD_RTC */
+
+#ifdef CONFIG_PLATFORM_EC_HOSTCMD_RTC
+static enum ec_status system_rtc_get_value(struct host_cmd_handler_args *args)
+{
+	struct ec_response_rtc *r = args->response;
+
+	r->time = system_get_rtc_sec();
+	args->response_size = sizeof(*r);
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_VALUE, system_rtc_get_value,
+		     EC_VER_MASK(0));
+
+static enum ec_status system_rtc_set_value(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_rtc *p = args->params;
+
+	system_set_rtc(p->time);
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_VALUE, system_rtc_set_value,
+		     EC_VER_MASK(0));
+
+static enum ec_status system_rtc_set_alarm(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_rtc *p = args->params;
+
+	system_set_rtc_alarm(p->time, 0);
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_ALARM, system_rtc_set_alarm,
+		     EC_VER_MASK(0));
+
+static enum ec_status system_rtc_get_alarm(struct host_cmd_handler_args *args)
+{
+	struct ec_response_rtc *r = args->response;
+
+	r->time = system_get_rtc_alarm();
+	args->response_size = sizeof(*r);
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_ALARM, system_rtc_get_alarm,
+		     EC_VER_MASK(0));
+
+#endif /* CONFIG_PLATFORM_EC_HOSTCMD_RTC */
diff --git a/zephyr/shim/src/sha256_hw.c b/zephyr/shim/src/sha256_hw.c
new file mode 100644
index 0000000000..dd6b236c3c
--- /dev/null
+++ b/zephyr/shim/src/sha256_hw.c
@@ -0,0 +1,136 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* SHA256 module for Chrome EC */
+
+#include "sha256.h"
+
+#include <zephyr/crypto/crypto.h>
+#include <zephyr/device.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(sha256_hw_shim, CONFIG_CRYPTO_LOG_LEVEL);
+
+static const struct device *sha256_hw_dev =
+	DEVICE_DT_GET(DT_CHOSEN(cros_ec_sha));
+
+void SHA256_init(struct sha256_ctx *ctx)
+{
+	int ret;
+	struct hash_ctx *hash_ctx = &ctx->hash_sha256;
+
+	hash_ctx->flags = CAP_SYNC_OPS | CAP_SEPARATE_IO_BUFS;
+	ret = hash_begin_session(sha256_hw_dev, hash_ctx,
+				 CRYPTO_HASH_ALGO_SHA256);
+	if (ret != 0) {
+		LOG_ERR("SHA256 Init Fail");
+	}
+}
+
+void SHA256_update(struct sha256_ctx *ctx, const uint8_t *data, uint32_t len)
+{
+	int ret;
+	struct hash_pkt pkt = {
+		.in_buf = (uint8_t *)data,
+		.in_len = len,
+		.out_buf = ctx->buf,
+	};
+	struct hash_ctx *hash_ctx = &ctx->hash_sha256;
+
+	ret = hash_update(hash_ctx, &pkt);
+
+	if (ret != 0) {
+		LOG_ERR("SHA256 Update Fail");
+	}
+}
+
+void SHA256_abort(struct sha256_ctx *ctx)
+{
+	struct hash_ctx *hash_ctx = &ctx->hash_sha256;
+
+	hash_free_session(sha256_hw_dev, hash_ctx);
+}
+
+uint8_t *SHA256_final(struct sha256_ctx *ctx)
+{
+	int ret;
+	struct hash_pkt pkt = {
+		.in_buf = NULL,
+		.in_len = 0,
+		.out_buf = ctx->buf,
+	};
+	struct hash_ctx *hash_ctx = &ctx->hash_sha256;
+
+	/*
+	 * Call hash_compute function with zero input data to finish SHA256
+	 * computation and get the digest.
+	 */
+	ret = hash_compute(hash_ctx, &pkt);
+
+	if (ret != 0) {
+		LOG_ERR("SHA256 Final Fail");
+	}
+
+	hash_free_session(sha256_hw_dev, hash_ctx);
+	return ctx->buf;
+}
+
+static void hmac_SHA256_step(uint8_t *output, uint8_t mask, const uint8_t *key,
+			     const int key_len, const uint8_t *data,
+			     const int data_len)
+{
+	struct sha256_ctx hmac_ctx;
+	uint8_t *key_pad = hmac_ctx.buf;
+	int i;
+
+	memset(hmac_ctx.buf, mask, sizeof(hmac_ctx.buf));
+	for (i = 0; i < key_len; i++)
+		key_pad[i] ^= key[i];
+
+	SHA256_init(&hmac_ctx);
+	SHA256_update(&hmac_ctx, key_pad, SHA256_BLOCK_SIZE);
+	SHA256_update(&hmac_ctx, data, data_len);
+	SHA256_final(&hmac_ctx);
+	__ASSERT(sizeof(hmac_ctx.buf) <= SHA256_BLOCK_SIZE,
+		 "hmac buf size > SHA256 block size");
+	memcpy(output, hmac_ctx.buf, SHA256_DIGEST_SIZE);
+}
+
+/*
+ * Note: When the API is called, it will consume sizeof(struct sha256_ctx) of
+ * TASK_STACK_SIZE because a variable of structure sha256_ctx is declared
+ * in the function hmac_SHA256_step.
+ */
+void hmac_SHA256(uint8_t *output, const uint8_t *key, const int key_len,
+		 const uint8_t *message, const int message_len)
+{
+	/* This code does not support key_len > block_size. */
+	__ASSERT(key_len <= SHA256_BLOCK_SIZE,
+		 "Key length > SHA256 block size");
+
+	/*
+	 * i_key_pad = key (zero-padded) ^ 0x36
+	 * output = hash(i_key_pad || message)
+	 * (Use output as temporary buffer)
+	 */
+	hmac_SHA256_step(output, 0x36, key, key_len, message, message_len);
+
+	/*
+	 * o_key_pad = key (zero-padded) ^ 0x5c
+	 * output = hash(o_key_pad || output)
+	 */
+	hmac_SHA256_step(output, 0x5c, key, key_len, output,
+			 SHA256_DIGEST_SIZE);
+}
+
+static int zephyr_shim_init_sha256(void)
+{
+	if (!device_is_ready(sha256_hw_dev)) {
+		k_oops();
+	}
+
+	return 0;
+}
+SYS_INIT(zephyr_shim_init_sha256, APPLICATION, 0);
diff --git a/zephyr/shim/src/switchcap_gpio.c b/zephyr/shim/src/switchcap_gpio.c
new file mode 100644
index 0000000000..982e5ff98c
--- /dev/null
+++ b/zephyr/shim/src/switchcap_gpio.c
@@ -0,0 +1,44 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define DT_DRV_COMPAT cros_ec_switchcap_gpio
+
+#include "common.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/kernel.h>
+
+/* TODO(b/218600962): Consolidate switchcap code. */
+
+#define SC_PIN_ENABLE_GPIO DT_INST_PROP(0, enable_pin)
+#define SC_PIN_ENABLE GPIO_DT_FROM_NODE(SC_PIN_ENABLE_GPIO)
+
+#define SC_PIN_POWER_GOOD_GPIO DT_INST_PROP(0, power_good_pin)
+#define SC_PIN_POWER_GOOD_EXISTS DT_NODE_EXISTS(SC_PIN_POWER_GOOD_GPIO)
+#define SC_PIN_POWER_GOOD GPIO_DT_FROM_NODE(SC_PIN_POWER_GOOD_GPIO)
+
+static const int32_t poff_delay_ms = DT_INST_PROP_OR(0, poff_delay_ms, 0);
+
+void board_set_switchcap_power(int enable)
+{
+	gpio_pin_set_dt(SC_PIN_ENABLE, enable);
+	if (!enable && poff_delay_ms > 0)
+		k_msleep(poff_delay_ms);
+}
+
+int board_is_switchcap_enabled(void)
+{
+	return gpio_pin_get_dt(SC_PIN_ENABLE);
+}
+
+int board_is_switchcap_power_good(void)
+{
+#if SC_PIN_POWER_GOOD_EXISTS
+	return gpio_pin_get_dt(SC_PIN_POWER_GOOD);
+#else
+	return 1;
+#endif
+}
diff --git a/zephyr/shim/src/switchcap_ln9310.c b/zephyr/shim/src/switchcap_ln9310.c
new file mode 100644
index 0000000000..54087ef6f2
--- /dev/null
+++ b/zephyr/shim/src/switchcap_ln9310.c
@@ -0,0 +1,43 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define DT_DRV_COMPAT lion_ln9310
+
+#include "common.h"
+#include "ln9310.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/gpio.h>
+
+/* TODO(b/218600962): Consolidate switchcap code. */
+
+#define SC_PIN_ENABLE_GPIO DT_INST_PROP(0, enable_pin)
+#define SC_PIN_ENABLE GPIO_DT_FROM_NODE(SC_PIN_ENABLE_GPIO)
+
+#define SC_PORT_NODE DT_INST_PHANDLE(0, port)
+#define SC_PORT DT_STRING_UPPER_TOKEN_BY_IDX(SC_PORT_NODE, enum_names, 0)
+
+#define SC_ADDR_FLAGS DT_INST_STRING_UPPER_TOKEN(0, addr_flags)
+
+void board_set_switchcap_power(int enable)
+{
+	gpio_pin_set_dt(SC_PIN_ENABLE, enable);
+	ln9310_software_enable(enable);
+}
+
+int board_is_switchcap_enabled(void)
+{
+	return gpio_pin_get_dt(SC_PIN_ENABLE);
+}
+
+int board_is_switchcap_power_good(void)
+{
+	return ln9310_power_good();
+}
+
+const struct ln9310_config_t ln9310_config = {
+	.i2c_port = SC_PORT,
+	.i2c_addr_flags = SC_ADDR_FLAGS,
+};
diff --git a/zephyr/shim/src/system.c b/zephyr/shim/src/system.c
new file mode 100644
index 0000000000..5150956ba6
--- /dev/null
+++ b/zephyr/shim/src/system.c
@@ -0,0 +1,459 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "bbram.h"
+#include "common.h"
+#include "console.h"
+#include "cros_version.h"
+#include "system.h"
+#include "watchdog.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/bbram.h>
+#include <zephyr/logging/log.h>
+#include <drivers/cros_system.h>
+
+/* 2 second delay for waiting the H1 reset */
+#define WAIT_RESET_TIME                                     \
+	(CONFIG_PLATFORM_EC_PREINIT_HW_CYCLES_PER_SEC * 2 / \
+	 CONFIG_PLATFORM_EC_WAIT_RESET_CYCLES_PER_ITERATION)
+
+LOG_MODULE_REGISTER(shim_system, LOG_LEVEL_ERR);
+
+static const struct device *const bbram_dev =
+	COND_CODE_1(DT_HAS_CHOSEN(cros_ec_bbram),
+		    DEVICE_DT_GET(DT_CHOSEN(cros_ec_bbram)), NULL);
+static const struct device *sys_dev;
+
+/* Map idx to a bbram offset/size, or return -1 on invalid idx */
+static int bbram_lookup(enum system_bbram_idx idx, int *offset_out,
+			int *size_out)
+{
+	switch (idx) {
+#if BBRAM_HAS_REGION(pd0)
+	case SYSTEM_BBRAM_IDX_PD0:
+		*offset_out = BBRAM_REGION_OFFSET(pd0);
+		*size_out = BBRAM_REGION_SIZE(pd0);
+		break;
+#endif
+#if BBRAM_HAS_REGION(pd1)
+	case SYSTEM_BBRAM_IDX_PD1:
+		*offset_out = BBRAM_REGION_OFFSET(pd1);
+		*size_out = BBRAM_REGION_SIZE(pd1);
+		break;
+#endif
+#if BBRAM_HAS_REGION(pd2)
+	case SYSTEM_BBRAM_IDX_PD2:
+		*offset_out = BBRAM_REGION_OFFSET(pd2);
+		*size_out = BBRAM_REGION_SIZE(pd2);
+		break;
+#endif
+#if BBRAM_HAS_REGION(try_slot)
+	case SYSTEM_BBRAM_IDX_TRY_SLOT:
+		*offset_out = BBRAM_REGION_OFFSET(try_slot);
+		*size_out = BBRAM_REGION_SIZE(try_slot);
+		break;
+#endif
+#ifdef CONFIG_PLATFORM_EC_CUSTOMIZED_DESIGN
+#if BBRAM_HAS_REGION(charge_limit_max)
+	case SYSTEM_BBRAM_IDX_CHARGE_LIMIT_MAX:
+		*offset_out = BBRAM_REGION_OFFSET(charge_limit_max);
+		*size_out = BBRAM_REGION_SIZE(charge_limit_max);
+		break;
+#endif
+#if BBRAM_HAS_REGION(fp_led_level)
+	case SYSTEM_BBRAM_IDX_FP_LED_LEVEL:
+		*offset_out = BBRAM_REGION_OFFSET(fp_led_level);
+		*size_out = BBRAM_REGION_SIZE(fp_led_level);
+		break;
+
+#endif
+#if BBRAM_HAS_REGION(kb_status)
+	case SYSTEM_BBRAM_IDX_KBSTATE:
+		*offset_out = BBRAM_REGION_OFFSET(kb_status);
+		*size_out = BBRAM_REGION_SIZE(kb_status);
+		break;
+
+#endif
+#if BBRAM_HAS_REGION(bios_function)
+	case SYSTEM_BBRAM_IDX_BIOS_FUNCTION:
+		*offset_out = BBRAM_REGION_OFFSET(bios_function);
+		*size_out = BBRAM_REGION_SIZE(bios_function);
+		break;
+
+#endif
+#if BBRAM_HAS_REGION(chassis_was_open)
+	case SYSTEM_BBRAM_IDX_CHASSIS_WAS_OPEN:
+		*offset_out = BBRAM_REGION_OFFSET(chassis_was_open);
+		*size_out = BBRAM_REGION_SIZE(chassis_was_open);
+		break;
+
+#endif
+#if BBRAM_HAS_REGION(chassis_magic)
+	case SYSTEM_BBRAM_IDX_CHASSIS_MAGIC:
+		*offset_out = BBRAM_REGION_OFFSET(chassis_magic);
+		*size_out = BBRAM_REGION_SIZE(chassis_magic);
+		break;
+
+#endif
+#if BBRAM_HAS_REGION(chassis_total)
+	case SYSTEM_BBRAM_IDX_CHASSIS_TOTAL:
+		*offset_out = BBRAM_REGION_OFFSET(chassis_total);
+		*size_out = BBRAM_REGION_SIZE(chassis_total);
+		break;
+
+#endif
+#if BBRAM_HAS_REGION(chassis_vtr_open)
+	case SYSTEM_BBRAM_IDX_CHASSIS_VTR_OPEN:
+		*offset_out = BBRAM_REGION_OFFSET(chassis_vtr_open);
+		*size_out = BBRAM_REGION_SIZE(chassis_vtr_open);
+		break;
+
+#endif
+#endif
+	default:
+		return EC_ERROR_INVAL;
+	}
+	return EC_SUCCESS;
+}
+
+int system_get_bbram(enum system_bbram_idx idx, uint8_t *value)
+{
+	int offset, size, rc;
+
+	if (bbram_dev == NULL)
+		return EC_ERROR_INVAL;
+
+	rc = bbram_lookup(idx, &offset, &size);
+	if (rc)
+		return rc;
+
+	rc = bbram_read(bbram_dev, offset, size, value);
+
+	return rc ? EC_ERROR_INVAL : EC_SUCCESS;
+}
+
+int system_set_bbram(enum system_bbram_idx idx, uint8_t value)
+{
+	int offset, size, rc;
+
+	if (bbram_dev == NULL)
+		return EC_ERROR_INVAL;
+
+	rc = bbram_lookup(idx, &offset, &size);
+	if (rc)
+		return rc;
+
+	rc = bbram_write(bbram_dev, offset, size, &value);
+
+	return rc ? EC_ERROR_INVAL : EC_SUCCESS;
+}
+
+void chip_save_reset_flags(uint32_t flags)
+{
+	if (bbram_dev == NULL) {
+		LOG_ERR("bbram_dev doesn't binding");
+		return;
+	}
+
+	bbram_write(bbram_dev, BBRAM_REGION_OFFSET(saved_reset_flags),
+		    BBRAM_REGION_SIZE(saved_reset_flags), (uint8_t *)&flags);
+}
+
+uint32_t chip_read_reset_flags(void)
+{
+	uint32_t flags;
+
+	if (bbram_dev == NULL) {
+		LOG_ERR("bbram_dev doesn't binding");
+		return 0;
+	}
+
+	bbram_read(bbram_dev, BBRAM_REGION_OFFSET(saved_reset_flags),
+		   BBRAM_REGION_SIZE(saved_reset_flags), (uint8_t *)&flags);
+
+	return flags;
+}
+
+int system_set_scratchpad(uint32_t value)
+{
+	if (bbram_dev == NULL) {
+		LOG_ERR("bbram_dev doesn't binding");
+		return -EC_ERROR_INVAL;
+	}
+
+	return bbram_write(bbram_dev, BBRAM_REGION_OFFSET(scratchpad),
+			   BBRAM_REGION_SIZE(scratchpad), (uint8_t *)&value);
+}
+
+int system_get_scratchpad(uint32_t *value)
+{
+	if (bbram_dev == NULL) {
+		LOG_ERR("bbram_dev doesn't binding");
+		return -EC_ERROR_INVAL;
+	}
+
+	if (bbram_read(bbram_dev, BBRAM_REGION_OFFSET(scratchpad),
+		       BBRAM_REGION_SIZE(scratchpad), (uint8_t *)value)) {
+		return -EC_ERROR_INVAL;
+	}
+
+	return 0;
+}
+
+test_mockable void system_hibernate(uint32_t seconds, uint32_t microseconds)
+{
+	const struct device *sys_dev = device_get_binding("CROS_SYSTEM");
+	int err;
+
+	/* Flush console before hibernating */
+	cflush();
+
+	if (board_hibernate)
+		board_hibernate();
+
+	/* Save 'wake-up from hibernate' reset flag */
+	chip_save_reset_flags(chip_read_reset_flags() |
+			      EC_RESET_FLAG_HIBERNATE);
+
+	err = cros_system_hibernate(sys_dev, seconds, microseconds);
+	if (err < 0) {
+		LOG_ERR("hibernate failed %d", err);
+		return;
+	}
+
+	/*
+	 * Ignore infinite loop for coverage as the test would fail via timeout
+	 * and not report regardless of executing code.
+	 */
+	/* LCOV_EXCL_START */
+	/* should never reach this point */
+	while (1)
+		continue;
+	/* LCOV_EXCL_STOP */
+}
+
+#ifdef CONFIG_PM
+/**
+ * Print low power idle statistics
+ */
+static int command_idle_stats(int argc, const char **argv)
+{
+	const struct device *sys_dev = device_get_binding("CROS_SYSTEM");
+
+	timestamp_t ts = get_time();
+	uint64_t deep_sleep_ticks = cros_system_deep_sleep_ticks(sys_dev);
+
+	ccprintf("Time spent in deep-sleep:            %.6llds\n",
+		 k_ticks_to_us_near64(deep_sleep_ticks));
+	ccprintf("Total time on:                       %.6llds\n", ts.val);
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, "",
+			"Print last idle stats");
+#endif
+
+const char *system_get_chip_vendor(void)
+{
+	const struct device *sys_dev = device_get_binding("CROS_SYSTEM");
+
+	return cros_system_chip_vendor(sys_dev);
+}
+
+const char *system_get_chip_name(void)
+{
+	const struct device *sys_dev = device_get_binding("CROS_SYSTEM");
+
+	return cros_system_chip_name(sys_dev);
+}
+
+const char *system_get_chip_revision(void)
+{
+	const struct device *sys_dev = device_get_binding("CROS_SYSTEM");
+
+	return cros_system_chip_revision(sys_dev);
+}
+
+test_mockable void system_reset(int flags)
+{
+	int err;
+	uint32_t save_flags;
+
+	if (!sys_dev)
+		LOG_ERR("sys_dev get binding failed");
+
+	/* Disable interrupts to avoid task swaps during reboot */
+	interrupt_disable_all();
+
+	/*  Get flags to be saved in BBRAM */
+	system_encode_save_flags(flags, &save_flags);
+
+	/* Store flags to battery backed RAM. */
+	chip_save_reset_flags(save_flags);
+
+	/* If WAIT_EXT is set, then allow 10 seconds for external reset */
+	if (flags & SYSTEM_RESET_WAIT_EXT) {
+		int i;
+
+		/* Wait 10 seconds for external reset */
+		for (i = 0; i < 1000; i++) {
+			watchdog_reload();
+			udelay(10000);
+		}
+	}
+
+	err = cros_system_soc_reset(sys_dev);
+
+	if (err < 0)
+		LOG_ERR("soc reset failed");
+
+	/*
+	 * Ignore infinite loop for coverage as the test would fail via timeout
+	 * and not report regardless of executing code.
+	 */
+	/* LCOV_EXCL_START */
+	/* should never return */
+	while (1)
+		continue;
+	/* LCOV_EXCL_STOP */
+}
+
+static int check_reset_cause(void)
+{
+	uint32_t chip_flags = 0; /* used to write back to the BBRAM */
+	uint32_t system_flags = chip_read_reset_flags(); /* system reset flag */
+	int chip_reset_cause = 0; /* chip-level reset cause */
+
+	chip_reset_cause = cros_system_get_reset_cause(sys_dev);
+	if (chip_reset_cause < 0)
+		return -1;
+
+	/*
+	 * TODO(b/182876692): Implement CONFIG_POWER_BUTTON_INIT_IDLE &
+	 * CONFIG_BOARD_FORCE_RESET_PIN.
+	 */
+
+	switch (chip_reset_cause) {
+	case POWERUP:
+		system_flags |= EC_RESET_FLAG_POWER_ON;
+		/*
+		 * Power-on restart, so set a flag and save it for the next
+		 * imminent reset. Later code will check for this flag and wait
+		 * for the second reset. Waking from PSL hibernate is power-on
+		 * for EC but not for H1, so do not wait for the second reset.
+		 */
+		if (IS_ENABLED(CONFIG_BOARD_RESET_AFTER_POWER_ON) &&
+		    ((system_flags & EC_RESET_FLAG_HIBERNATE) == 0)) {
+			system_flags |= EC_RESET_FLAG_INITIAL_PWR;
+			chip_flags |= EC_RESET_FLAG_INITIAL_PWR;
+		}
+		break;
+
+	case VCC1_RST_PIN:
+		/*
+		 * If configured, check the saved flags to see whether the
+		 * previous restart was a power-on, in which case treat this
+		 * restart as a power-on as well. This is to workaround the fact
+		 * that the H1 will reset the EC at power up.
+		 */
+		if (IS_ENABLED(CONFIG_BOARD_RESET_AFTER_POWER_ON)) {
+			if (system_flags & EC_RESET_FLAG_INITIAL_PWR) {
+				/*
+				 * The previous restart was a power-on so treat
+				 * this restart as that, and clear the flag so
+				 * later code will not wait for the second
+				 * reset.
+				 */
+				system_flags = (system_flags &
+						~EC_RESET_FLAG_INITIAL_PWR) |
+					       EC_RESET_FLAG_POWER_ON;
+			} else {
+				/*
+				 * No previous reset flag, so this is a
+				 * subsequent restart i.e any restarts after the
+				 * second restart caused by the H1.
+				 */
+				system_flags |= EC_RESET_FLAG_RESET_PIN;
+			}
+		} else {
+			system_flags |= EC_RESET_FLAG_RESET_PIN;
+		}
+		break;
+
+	case DEBUG_RST:
+		system_flags |= EC_RESET_FLAG_SOFT;
+		break;
+
+	case WATCHDOG_RST:
+		/*
+		 * Don't set EC_RESET_FLAG_WATCHDOG flag if watchdog is issued
+		 * by system_reset or hibernate in order to distinguish reset
+		 * cause is panic reason or not.
+		 */
+		if (!(system_flags & (EC_RESET_FLAG_SOFT | EC_RESET_FLAG_HARD |
+				      EC_RESET_FLAG_HIBERNATE)))
+			system_flags |= EC_RESET_FLAG_WATCHDOG;
+		break;
+	}
+
+	/* Clear & set the reset flags for the following reset. */
+	chip_save_reset_flags(chip_flags);
+
+	/* Set the system reset flags. */
+	system_set_reset_flags(system_flags);
+
+	return 0;
+}
+
+test_export_static int system_preinitialize(void)
+{
+	if (bbram_dev && !device_is_ready(bbram_dev)) {
+		LOG_ERR("Error: device %s is not ready", bbram_dev->name);
+		return -1;
+	}
+
+	sys_dev = device_get_binding("CROS_SYSTEM");
+	if (!sys_dev) {
+		/*
+		 * TODO(b/183022804): This should not happen in normal
+		 * operation. Check whether the error check can be change to
+		 * build-time error, or at least a fatal run-time error.
+		 */
+		LOG_ERR("sys_dev gets binding failed");
+		return -1;
+	}
+
+	/* check the reset cause */
+	if (check_reset_cause() != 0) {
+		LOG_ERR("check the reset cause failed");
+		return -1;
+	}
+
+	/*
+	 * For some boards on power-on, the EC is reset by the H1 after
+	 * power-on, so the EC sees 2 resets. This config enables the EC to save
+	 * a flag on the first power-up restart, and then wait for the second
+	 * reset before any other setup is done (such as GPIOs, timers, UART
+	 * etc.) On the second reset, the saved flag is used to detect the
+	 * previous power-on, and treat the second reset as a power-on instead
+	 * of a reset.
+	 */
+#ifdef CONFIG_BOARD_RESET_AFTER_POWER_ON
+	if (system_get_reset_flags() & EC_RESET_FLAG_INITIAL_PWR) {
+		/*
+		 * The current initial stage couldn't use the kernel delay
+		 * function. Use CPU nop instruction to wait for the external
+		 * reset from H1.
+		 */
+		for (uint32_t i = WAIT_RESET_TIME; i; i--)
+			arch_nop();
+	}
+#endif
+	system_common_pre_init();
+	return 0;
+}
+
+SYS_INIT(system_preinitialize, PRE_KERNEL_1,
+	 CONFIG_PLATFORM_EC_SYSTEM_PRE_INIT_PRIORITY);
diff --git a/zephyr/shim/src/system_safe_mode.c b/zephyr/shim/src/system_safe_mode.c
new file mode 100644
index 0000000000..98ccc83c53
--- /dev/null
+++ b/zephyr/shim/src/system_safe_mode.c
@@ -0,0 +1,41 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_tasks.h"
+#include "panic.h"
+#include "string.h"
+#include "system.h"
+#include "system_safe_mode.h"
+
+#include <zephyr/arch/cpu.h>
+#include <zephyr/kernel.h>
+#include <zephyr/kernel/thread.h>
+
+__override int disable_non_safe_mode_critical_tasks(void)
+{
+	for (task_id_t task_id = 0; task_id < TASK_ID_COUNT + EXTRA_TASK_COUNT;
+	     task_id++) {
+		k_tid_t thread_id = task_id_to_thread_id(task_id);
+
+		/* Don't abort the thread when:
+		 * 1) The task to thread lookup failed
+		 * 2) It's the current thread since it will be aborted
+		 *    automatically by the Zephyr kernel.
+		 * 3) The thread is safe mode critical
+		 */
+		if (thread_id == NULL || thread_id == k_current_get() ||
+		    is_task_safe_mode_critical(task_id)) {
+			continue;
+		}
+		k_thread_abort(thread_id);
+	}
+	return EC_SUCCESS;
+}
+
+static void safe_mode_timeout_cb(struct k_timer *unused)
+{
+	handle_system_safe_mode_timeout();
+}
+K_TIMER_DEFINE(safe_mode_timeout, safe_mode_timeout_cb, NULL);
diff --git a/zephyr/shim/src/tasks.c b/zephyr/shim/src/tasks.c
new file mode 100644
index 0000000000..aa89c9ee5c
--- /dev/null
+++ b/zephyr/shim/src/tasks.c
@@ -0,0 +1,449 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "ec_tasks.h"
+#include "host_command.h"
+#include "task.h"
+#include "timer.h"
+#include "zephyr_console_shim.h"
+
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/shell/shell.h>
+#include <zephyr/sys/atomic.h>
+
+/* Ensure that the idle task is at lower priority than lowest priority task. */
+BUILD_ASSERT(EC_TASK_PRIORITY(EC_TASK_PRIO_LOWEST) < K_IDLE_PRIO,
+	     "CONFIG_NUM_PREEMPT_PRIORITIES too small, some tasks would run at "
+	     "idle priority");
+
+/* Forward declare all task entry point functions */
+#define CROS_EC_TASK(name, entry, ...) void entry(void *p);
+#define TASK_TEST(name, entry, ...) CROS_EC_TASK(name, entry)
+CROS_EC_TASK_LIST
+#undef CROS_EC_TASK
+#undef TASK_TEST
+
+/* Statically declare all threads here */
+#define CROS_EC_TASK(name, entry, parameter, stack_size, priority)      \
+	K_THREAD_DEFINE(name, stack_size, entry, parameter, NULL, NULL, \
+			EC_TASK_PRIORITY(priority), 0, -1);
+#define TASK_TEST(name, e, p, size) CROS_EC_TASK(name, e, p, size)
+CROS_EC_TASK_LIST
+#undef CROS_EC_TASK
+#undef TASK_TEST
+
+struct task_ctx_base_data {
+	/** A wait-able event that is raised when a new task event is posted */
+	struct k_poll_signal new_event;
+	/** The current platform/ec events set for this task/thread */
+	atomic_t event_mask;
+};
+
+/*
+ * Create a mapping from the cros-ec task ID to the Zephyr thread.
+ */
+#undef CROS_EC_TASK
+#define CROS_EC_TASK(_name, _entry, _parameter, _size, _prio) _name,
+#ifdef TEST_BUILD
+static k_tid_t task_to_k_tid[TASK_ID_COUNT] = {
+#else
+const static k_tid_t task_to_k_tid[TASK_ID_COUNT] = {
+#endif
+	CROS_EC_TASK_LIST
+};
+
+static struct task_ctx_base_data shimmed_tasks_data[TASK_ID_COUNT];
+static struct task_ctx_base_data extra_tasks_data[EXTRA_TASK_COUNT];
+/* Task timer structures. Keep separate from the context ones to avoid memory
+ * holes due to int64_t fields in struct _timeout.
+ */
+static struct k_timer shimmed_tasks_timers[TASK_ID_COUNT + EXTRA_TASK_COUNT];
+
+static int tasks_started;
+#undef CROS_EC_TASK
+#undef TASK_TEST
+
+static struct task_ctx_base_data *task_get_base_data(task_id_t cros_task_id)
+{
+	if (cros_task_id >= TASK_ID_COUNT + EXTRA_TASK_COUNT) {
+		return NULL;
+	}
+
+	if (cros_task_id >= TASK_ID_COUNT) {
+		return &extra_tasks_data[cros_task_id - TASK_ID_COUNT];
+	}
+
+	return &shimmed_tasks_data[cros_task_id];
+}
+
+test_export_static k_tid_t get_idle_thread(void)
+{
+	extern struct k_thread z_idle_threads[];
+
+	if (!IS_ENABLED(CONFIG_SMP)) {
+		return &z_idle_threads[0];
+	}
+	__ASSERT(false, "%s does not support SMP", __func__);
+	return NULL;
+}
+
+test_export_static k_tid_t get_sysworkq_thread(void)
+{
+	return &k_sys_work_q.thread;
+}
+
+k_tid_t get_main_thread(void)
+{
+	/* Pointer to the main thread, defined in kernel/init.c */
+	extern struct k_thread z_main_thread;
+
+	return &z_main_thread;
+}
+
+test_mockable k_tid_t get_hostcmd_thread(void)
+{
+#ifdef HAS_TASK_HOSTCMD
+	if (IS_ENABLED(CONFIG_TASK_HOSTCMD_THREAD_MAIN)) {
+		return get_main_thread();
+	}
+	return task_to_k_tid[TASK_ID_HOSTCMD];
+#endif /* HAS_TASK_HOSTCMD */
+	__ASSERT(false, "HOSTCMD task is not enabled");
+	return NULL;
+}
+
+k_tid_t task_id_to_thread_id(task_id_t task_id)
+{
+	if (task_id < 0) {
+		__ASSERT(false, "Invalid task id %d", task_id);
+		return NULL;
+	}
+	if (task_id < TASK_ID_COUNT) {
+		return task_to_k_tid[task_id];
+	}
+	if (task_id < TASK_ID_COUNT + EXTRA_TASK_COUNT) {
+		switch (task_id) {
+		case TASK_ID_SYSWORKQ:
+			return get_sysworkq_thread();
+
+#ifdef HAS_TASK_HOSTCMD
+		case TASK_ID_HOSTCMD:
+			return get_hostcmd_thread();
+#endif /* HAS_TASK_HOSTCMD */
+
+#ifdef HAS_TASK_MAIN
+		case TASK_ID_MAIN:
+			return get_main_thread();
+#endif /* HAS_TASK_MAIN */
+
+		case TASK_ID_IDLE:
+			return get_idle_thread();
+
+		case TASK_ID_SHELL:
+			return get_shell_thread();
+		}
+	}
+	__ASSERT(false, "Failed to map task %d to thread", task_id);
+	return NULL;
+}
+
+task_id_t thread_id_to_task_id(k_tid_t thread_id)
+{
+	if (thread_id == NULL) {
+		__ASSERT(false, "Invalid thread_id");
+		return TASK_ID_INVALID;
+	}
+
+	if (get_sysworkq_thread() == thread_id) {
+		return TASK_ID_SYSWORKQ;
+	}
+
+#ifdef HAS_TASK_HOSTCMD
+	if (get_hostcmd_thread() == thread_id) {
+		return TASK_ID_HOSTCMD;
+	}
+#endif /* HAS_TASK_HOSTCMD */
+
+#ifdef HAS_TASK_MAIN
+	if (get_main_thread() == thread_id) {
+		return TASK_ID_MAIN;
+	}
+#endif /* HAS_TASK_MAIN */
+
+	if (get_idle_thread() == thread_id) {
+		return TASK_ID_IDLE;
+	}
+
+	if (get_shell_thread() == thread_id) {
+		return TASK_ID_SHELL;
+	}
+
+	for (size_t i = 0; i < TASK_ID_COUNT; ++i) {
+		if (task_to_k_tid[i] == thread_id) {
+			return i;
+		}
+	}
+
+	__ASSERT(false, "Failed to map thread to task");
+	return TASK_ID_INVALID;
+}
+
+task_id_t task_get_current(void)
+{
+	return thread_id_to_task_id(k_current_get());
+}
+
+atomic_t *task_get_event_bitmap(task_id_t cros_task_id)
+{
+	struct task_ctx_base_data *data;
+
+	data = task_get_base_data(cros_task_id);
+
+	return data == NULL ? NULL : &data->event_mask;
+}
+
+void task_set_event(task_id_t cros_task_id, uint32_t event)
+{
+	struct task_ctx_base_data *data;
+
+	data = task_get_base_data(cros_task_id);
+
+	if (data != NULL) {
+		atomic_or(&data->event_mask, event);
+		k_poll_signal_raise(&data->new_event, 0);
+	}
+}
+
+uint32_t task_wait_event(int timeout_us)
+{
+	struct task_ctx_base_data *data;
+
+	data = task_get_base_data(task_get_current());
+
+	__ASSERT_NO_MSG(data != NULL);
+
+	const k_timeout_t timeout = (timeout_us == -1) ? K_FOREVER :
+							 K_USEC(timeout_us);
+	const int64_t tick_deadline =
+		k_uptime_ticks() + k_us_to_ticks_near64(timeout_us);
+
+	struct k_poll_event poll_events[1] = {
+		K_POLL_EVENT_INITIALIZER(K_POLL_TYPE_SIGNAL,
+					 K_POLL_MODE_NOTIFY_ONLY,
+					 &data->new_event),
+	};
+
+	/* Wait for signal, then clear it before reading events */
+	const int rv = k_poll(poll_events, ARRAY_SIZE(poll_events), timeout);
+
+	k_poll_signal_reset(&data->new_event);
+	uint32_t events = atomic_set(&data->event_mask, 0);
+
+	if (rv == -EAGAIN) {
+		events |= TASK_EVENT_TIMER;
+	}
+
+	/* If we didn't get an event, we need to wait again. There is a very
+	 * small chance of us reading the event_mask one signaled event too
+	 * early. In that case, just wait again for the remaining timeout
+	 */
+	if (events == 0) {
+		const int64_t ticks_left = tick_deadline - k_uptime_ticks();
+
+		events |= TASK_EVENT_TIMER;
+
+		if (ticks_left > 0) {
+			return task_wait_event(
+				k_ticks_to_us_near64(ticks_left));
+		}
+	}
+
+	return events;
+}
+
+uint32_t task_wait_event_mask(uint32_t event_mask, int timeout_us)
+{
+	struct task_ctx_base_data *data;
+
+	data = task_get_base_data(task_get_current());
+
+	uint32_t events = 0;
+	const int64_t tick_deadline =
+		k_uptime_ticks() + k_us_to_ticks_near64(timeout_us);
+
+	/*  Need to return timeout flags if it occurs as well */
+	event_mask |= TASK_EVENT_TIMER;
+
+	while (!(event_mask & events)) {
+		const int64_t ticks_left = tick_deadline - k_uptime_ticks();
+
+		if (timeout_us != -1 && ticks_left <= 0) {
+			events |= TASK_EVENT_TIMER;
+			break;
+		}
+
+		struct k_poll_event poll_events[1] = {
+			K_POLL_EVENT_INITIALIZER(K_POLL_TYPE_SIGNAL,
+						 K_POLL_MODE_NOTIFY_ONLY,
+						 &data->new_event),
+		};
+
+		/* Ensure to honor the -1 timeout as FOREVER */
+		k_poll(poll_events, ARRAY_SIZE(poll_events),
+		       timeout_us == -1 ? K_FOREVER : K_TICKS(ticks_left));
+		k_poll_signal_reset(&data->new_event);
+		events |= atomic_set(&data->event_mask, 0);
+	}
+
+	/* Replace any events that weren't in the mask */
+	if (events & ~event_mask) {
+		atomic_or(&data->event_mask, events & ~event_mask);
+		k_poll_signal_raise(&data->new_event, 0);
+	}
+
+	return events & event_mask;
+}
+
+/*
+ * Callback function to use with k_timer_start to set the
+ * TASK_EVENT_TIMER event on a task.
+ */
+static void timer_expire(struct k_timer *timer_id)
+{
+	task_id_t cros_ec_task_id = timer_id - shimmed_tasks_timers;
+
+	task_set_event(cros_ec_task_id, TASK_EVENT_TIMER);
+}
+
+int timer_arm(timestamp_t event, task_id_t cros_ec_task_id)
+{
+	struct k_timer *timer;
+	timestamp_t now = get_time();
+
+	timer = &shimmed_tasks_timers[cros_ec_task_id];
+
+	if (event.val <= now.val) {
+		/* Timer requested for now or in the past, fire right away */
+		task_set_event(cros_ec_task_id, TASK_EVENT_TIMER);
+		return EC_SUCCESS;
+	}
+
+	/* Check for a running timer */
+	if (k_timer_remaining_get(timer))
+		return EC_ERROR_BUSY;
+
+	k_timer_start(timer, K_USEC(event.val - now.val), K_NO_WAIT);
+	return EC_SUCCESS;
+}
+
+void timer_cancel(task_id_t cros_ec_task_id)
+{
+	struct k_timer *timer;
+
+	timer = &shimmed_tasks_timers[cros_ec_task_id];
+
+	k_timer_stop(timer);
+}
+
+#ifdef TEST_BUILD
+void set_test_runner_tid(void)
+{
+	task_to_k_tid[TASK_ID_TEST_RUNNER] = k_current_get();
+}
+
+#ifdef CONFIG_TASKS_SET_TEST_RUNNER_TID_RULE
+#include <zephyr/ztest.h>
+static void set_test_runner_tid_rule_before(const struct ztest_unit_test *test,
+					    void *data)
+{
+	ARG_UNUSED(test);
+	ARG_UNUSED(data);
+	set_test_runner_tid();
+}
+
+ZTEST_RULE(set_test_runner_tid, set_test_runner_tid_rule_before, NULL);
+#endif /* CONFIG_TASKS_SET_TEST_RUNNER_TID_RULE */
+#endif /* TEST_BUILD */
+
+void start_ec_tasks(void)
+{
+	for (size_t i = 0; i < TASK_ID_COUNT + EXTRA_TASK_COUNT; ++i) {
+		k_timer_init(&shimmed_tasks_timers[i], timer_expire, NULL);
+	}
+
+	for (size_t i = 0; i < TASK_ID_COUNT; ++i) {
+#ifdef TEST_BUILD
+		/* The test runner thread is automatically started. */
+		if (i == TASK_ID_TEST_RUNNER) {
+			continue;
+		}
+#endif
+		k_thread_start(task_to_k_tid[i]);
+	}
+
+	tasks_started = 1;
+}
+
+/*
+ * Initialize all of the kernel objects before application code starts.
+ * This allows us to set events on tasks before they even start, e.g. in
+ * INIT_HOOKS.
+ */
+int init_signals(void)
+{
+	for (size_t i = 0; i < TASK_ID_COUNT + EXTRA_TASK_COUNT; ++i) {
+		struct task_ctx_base_data *const data = task_get_base_data(i);
+
+		k_poll_signal_init(&data->new_event);
+	}
+
+	return 0;
+}
+SYS_INIT(init_signals, POST_KERNEL, 50);
+
+int task_start_called(void)
+{
+	return tasks_started;
+}
+/*
+ * TODO(b/190203712): Implement this
+ * LCOV_EXCL_START
+ */
+void task_disable_task(task_id_t tskid)
+{
+}
+/* LCOV_EXCL_STOP */
+
+/*
+ * This function cannot be tested since it is architecture specific.
+ * LCOV_EXCL_START
+ */
+void task_clear_pending_irq(int irq)
+{
+#if CONFIG_ITE_IT8XXX2_INTC
+	ite_intc_isr_clear(irq);
+#endif
+}
+/* LCOV_EXCL_STOP */
+
+void task_enable_irq(int irq)
+{
+	arch_irq_enable(irq);
+}
+
+inline bool in_interrupt_context(void)
+{
+	return k_is_in_isr();
+}
+
+inline bool in_deferred_context(void)
+{
+	/*
+	 * Deferred calls run in the sysworkq.
+	 */
+	return (k_current_get() == get_sysworkq_thread());
+}
diff --git a/zephyr/shim/src/tcpc.c b/zephyr/shim/src/tcpc.c
new file mode 100644
index 0000000000..2f9de20cee
--- /dev/null
+++ b/zephyr/shim/src/tcpc.c
@@ -0,0 +1,237 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "hooks.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usbc/tcpc_anx7447.h"
+#include "usbc/tcpc_anx7447_emul.h"
+#include "usbc/tcpc_ccgxxf.h"
+#include "usbc/tcpc_fusb302.h"
+#include "usbc/tcpc_generic_emul.h"
+#include "usbc/tcpc_it8xxx2.h"
+#include "usbc/tcpc_nct38xx.h"
+#include "usbc/tcpc_ps8xxx.h"
+#include "usbc/tcpc_ps8xxx_emul.h"
+#include "usbc/tcpc_raa489000.h"
+#include "usbc/tcpc_rt1715.h"
+#include "usbc/tcpc_rt1718s.h"
+#include "usbc/tcpc_rt1718s_emul.h"
+#include "usbc/tcpci.h"
+#include "usbc/utils.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/util.h>
+
+LOG_MODULE_REGISTER(tcpc, CONFIG_GPIO_LOG_LEVEL);
+
+#define HAS_TCPC_PROP(usbc_id) \
+	COND_CODE_1(DT_NODE_HAS_PROP(usbc_id, tcpc), (|| 1), ())
+
+#define DT_HAS_TCPC (0 DT_FOREACH_STATUS_OKAY(named_usbc_port, HAS_TCPC_PROP))
+
+#if DT_HAS_TCPC
+
+#define TCPC_CHIP_ENTRY(usbc_id, tcpc_id, config_fn) \
+	[USBC_PORT_NEW(usbc_id)] = config_fn(tcpc_id),
+
+#define CHECK_COMPAT(compat, usbc_id, tcpc_id, config_fn) \
+	COND_CODE_1(DT_NODE_HAS_COMPAT(tcpc_id, compat),  \
+		    (TCPC_CHIP_ENTRY(usbc_id, tcpc_id, config_fn)), ())
+
+/**
+ * @param driver Tuple containing the TCPC (compatible, config) pair.
+ * @param nodes Tuple containing the (usbc_node_id, tcpc_node_id) pair
+ */
+#define CHECK_COMPAT_HELPER(driver, nodes)                                     \
+	CHECK_COMPAT(USBC_DRIVER_GET_COMPAT(driver), NODES_GET_USBC_ID(nodes), \
+		     NODES_GET_PROP_ID(nodes), USBC_DRIVER_GET_CONFIG(driver))
+
+#define TCPC_CHIP_FIND(usbc_id, tcpc_id)                                \
+	FOR_EACH_FIXED_ARG(CHECK_COMPAT_HELPER, (), (usbc_id, tcpc_id), \
+			   TCPC_DRIVERS)
+
+/*
+ * This macro gets invoked for every driver in the TCPC_DRIVERS list.
+ * If the passed in tcpc node contains the specified compat string, then
+ * this macro returns 1.  Otherwise the macro returns nothing (EMPTY).
+ */
+#define TCPC_HAS_COMPAT(compat, tcpc) \
+	IF_ENABLED(DT_NODE_HAS_COMPAT(tcpc, compat), 1)
+
+/*
+ * Verify the compatible property of a TCPC node is valid.
+ *
+ * Call TCPC_HAS_COMPAT() for all TCPC compatible strings listed in the
+ * TCPC_DRIVERS list.  If the resulting list is empty, then there was no
+ * matching TCPC driver found and this macro generates a build error.
+ */
+#define TCPC_PROP_COMPATIBLE_VERIFY(tcpc)                                     \
+	IF_ENABLED(IS_EMPTY(FOR_EACH_FIXED_ARG(TCPC_HAS_COMPAT, (), tcpc,     \
+					       TCPC_DRIVER_COMPATS)),         \
+		   (BUILD_ASSERT(                                             \
+			    0, "Invalid TCPC compatible on node: " STRINGIFY( \
+				       tcpc));))
+
+/* clang-format off */
+#define TCPC_CHIP_STUB(usbc_id) \
+	[USBC_PORT_NEW(usbc_id)] = {},
+/* clang-format on */
+
+#define TCPC_CHIP(usbc_id)                                                \
+	COND_CODE_1(DT_NODE_HAS_PROP(usbc_id, tcpc),                      \
+		    (TCPC_CHIP_FIND(usbc_id, DT_PHANDLE(usbc_id, tcpc))), \
+		    (TCPC_CHIP_STUB(usbc_id)))
+
+#define TCPC_CHIP_VERIFY(usbc_id)                   \
+	IF_ENABLED(DT_NODE_HAS_PROP(usbc_id, tcpc), \
+		   (TCPC_PROP_COMPATIBLE_VERIFY(DT_PHANDLE(usbc_id, tcpc))))
+
+#define MAYBE_CONST \
+	COND_CODE_1(CONFIG_PLATFORM_EC_USB_PD_TCPC_RUNTIME_CONFIG, (), (const))
+
+/*
+ * The TCPC_CHIP_VERIFY macro expands to nothing when the TCPC driver
+ * compatible string is found in the TCPC_DRIVER_COMPATS list. Otherwise
+ * the macro expands to a BUILD_ASSERT error.
+ */
+DT_FOREACH_STATUS_OKAY(named_usbc_port, TCPC_CHIP_VERIFY)
+
+/* Type C Port Controllers */
+MAYBE_CONST struct tcpc_config_t tcpc_config[] = { DT_FOREACH_STATUS_OKAY(
+	named_usbc_port, TCPC_CHIP) };
+
+#define TCPC_ALT_DEFINITION(node_id, config_fn)                 \
+	const struct tcpc_config_t TCPC_ALT_NAME_GET(node_id) = \
+		config_fn(node_id)
+
+#define TCPC_ALT_DEFINE(node_id, config_fn)         \
+	COND_CODE_1(DT_PROP_OR(node_id, is_alt, 0), \
+		    (TCPC_ALT_DEFINITION(node_id, config_fn);), ())
+
+/*
+ * Define a struct tcpc_config_t for every TCPC node in the tree with the
+ * "is-alt" property set.
+ */
+DT_FOREACH_USBC_DRIVER_STATUS_OK_VARGS(TCPC_ALT_DEFINE, TCPC_DRIVERS)
+
+#ifdef CONFIG_PLATFORM_EC_TCPC_INTERRUPT
+
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == CONFIG_USB_PD_PORT_MAX_COUNT);
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+	uint16_t alert_mask[] = { PD_STATUS_TCPC_ALERT_0,
+				  PD_STATUS_TCPC_ALERT_1,
+				  PD_STATUS_TCPC_ALERT_2,
+				  PD_STATUS_TCPC_ALERT_3 };
+
+	/*
+	 * Check which port has the ALERT line set and ignore if that TCPC has
+	 * its reset line active.
+	 */
+	for (int i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		/*
+		 * if the interrupt port exists and the interrupt is active
+		 */
+		if (tcpc_config[i].irq_gpio.port &&
+		    gpio_pin_get_dt(&tcpc_config[i].irq_gpio))
+			/*
+			 * if the reset line does not exist or exists but is
+			 * not active.
+			 */
+			if (!tcpc_config[i].rst_gpio.port ||
+			    !gpio_pin_get_dt(&tcpc_config[i].rst_gpio))
+				status |= alert_mask[i];
+	}
+
+	return status;
+}
+
+struct gpio_callback int_gpio_cb[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+static void tcpc_int_gpio_callback(const struct device *dev,
+				   struct gpio_callback *cb, uint32_t pins)
+{
+	/*
+	 * Retrieve the array index from the callback pointer, and
+	 * use that to get the port number.
+	 */
+	int port = cb - &int_gpio_cb[0];
+
+	schedule_deferred_pd_interrupt(port);
+}
+
+/*
+ * Enable all tcpc interrupts from devicetree bindings.
+ * Check whether the callback is already installed, and if
+ * not, init and add the callback before enabling the
+ * interrupt.
+ */
+void tcpc_enable_interrupt(void)
+{
+	for (int i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		/*
+		 * Check whether the interrupt pin has been configured
+		 * by the devicetree.
+		 */
+		if (!tcpc_config[i].irq_gpio.port)
+			continue;
+		/*
+		 * Check whether the gpio pin is ready
+		 */
+		if (!gpio_is_ready_dt(&tcpc_config[i].irq_gpio)) {
+			LOG_ERR("tcpc port #%i interrupt not ready.", i);
+			return;
+		}
+		/*
+		 * TODO(b/267537103): Once named-gpios support is dropped,
+		 * evaluate if this code should call gpio_pin_configure_dt()
+		 *
+		 * Check whether callback has been initialised
+		 */
+		if (!int_gpio_cb[i].handler) {
+			/*
+			 * Initialise and add the callback.
+			 */
+			gpio_init_callback(&int_gpio_cb[i],
+					   tcpc_int_gpio_callback,
+					   BIT(tcpc_config[i].irq_gpio.pin));
+			gpio_add_callback(tcpc_config[i].irq_gpio.port,
+					  &int_gpio_cb[i]);
+		}
+
+		gpio_pin_interrupt_configure_dt(&tcpc_config[i].irq_gpio,
+						GPIO_INT_EDGE_TO_ACTIVE);
+	}
+}
+/*
+ * priority set to POST_I2C + 1 so projects can make local edits to
+ * tcpc_config as needed at POST_I2C before the interrupts are enabled.
+ */
+DECLARE_HOOK(HOOK_INIT, tcpc_enable_interrupt, HOOK_PRIO_POST_I2C + 1);
+
+#else /* CONFIG_PLATFORM_EC_TCPC_INTERRUPT */
+
+/* TCPC GPIO Interrupt Handlers */
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	for (int i = 0; i < ARRAY_SIZE(tcpc_config); i++) {
+		/* No alerts if the alert pin is not set in the devicetree */
+		if (tcpc_config[i].alert_signal == GPIO_LIMIT) {
+			continue;
+		}
+
+		if (signal == tcpc_config[i].alert_signal) {
+			schedule_deferred_pd_interrupt(i);
+			break;
+		}
+	}
+}
+
+#endif /* CONFIG_PLATFORM_EC_TCPC_INTERRUPT */
+#endif /* DT_HAS_COMPAT_STATUS_OKAY */
diff --git a/zephyr/shim/src/tcpc_nct38xx.c b/zephyr/shim/src/tcpc_nct38xx.c
new file mode 100644
index 0000000000..5d3f5ac25c
--- /dev/null
+++ b/zephyr/shim/src/tcpc_nct38xx.c
@@ -0,0 +1,38 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "config.h"
+#include "usbc/tcpc_nct38xx.h"
+#include "usbc/utils.h"
+
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+
+#define GPIO_DEV_WITH_COMMA(id) DEVICE_DT_GET(DT_PHANDLE(id, gpio_dev)),
+
+#define GPIO_DEV_BINDING(usbc_id, tcpc_id)                                     \
+	COND_CODE_1(DT_NODE_HAS_PROP(tcpc_id, gpio_dev),                       \
+		    ([USBC_PORT_NEW(usbc_id)] = GPIO_DEV_WITH_COMMA(tcpc_id)), \
+		    ())
+
+#define NCT38XX_CHECK(usbc_id, tcpc_id)                           \
+	COND_CODE_1(DT_NODE_HAS_COMPAT(tcpc_id, nuvoton_nct38xx), \
+		    (GPIO_DEV_BINDING(usbc_id, tcpc_id)), ())
+
+#define NCT38XX_GPIO(usbc_id)                        \
+	COND_CODE_1(DT_NODE_HAS_PROP(usbc_id, tcpc), \
+		    (NCT38XX_CHECK(usbc_id, DT_PHANDLE(usbc_id, tcpc))), ())
+
+/* NCT38XX GPIO device pool for binding the TCPC port and NCT38XX GPIO device */
+static const struct device *nct38xx_gpio_devices[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	DT_FOREACH_STATUS_OKAY(named_usbc_port, NCT38XX_GPIO)
+};
+
+const struct device *nct38xx_get_gpio_device_from_port(const int port)
+{
+	if (port < 0 || port >= CONFIG_USB_PD_PORT_MAX_COUNT)
+		return NULL;
+	return nct38xx_gpio_devices[port];
+}
diff --git a/zephyr/shim/src/temp_sensors.c b/zephyr/shim/src/temp_sensors.c
new file mode 100644
index 0000000000..ae5c40b6aa
--- /dev/null
+++ b/zephyr/shim/src/temp_sensors.c
@@ -0,0 +1,378 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc.h"
+#include "charger/chg_rt9490.h"
+#include "driver/charger/rt9490.h"
+#include "hooks.h"
+#include "temp_sensor.h"
+#include "temp_sensor/f75303.h"
+#include "temp_sensor/pct2075.h"
+#include "temp_sensor/sb_tsi.h"
+#include "temp_sensor/temp_sensor.h"
+#include "temp_sensor/thermistor.h"
+#include "temp_sensor/tmp112.h"
+
+#ifdef CONFIG_PLATFORM_EC_CUSTOMIZED_DESIGN
+#include "lotus/amd_r23m.h"
+#endif /* CONFIG_PLATFORM_EC_CUSTOMIZED_DESIGN */
+
+#if DT_HAS_COMPAT_STATUS_OKAY(TEMP_SENSORS_COMPAT)
+
+BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(TEMP_SENSORS_COMPAT) == 1,
+	     "Only one temperature sensors node is allowed");
+
+#define GET_POWER_GOOD_PROP(node_id) DT_PROP(node_id, power_good_pin)
+
+#define GET_POWER_GOOD_DEV(node_id) \
+	DEVICE_DT_GET(DT_GPIO_CTLR(GET_POWER_GOOD_PROP(node_id), gpios))
+
+#define GET_POWER_GOOD_PIN(node_id) \
+	DT_GPIO_PIN(GET_POWER_GOOD_PROP(node_id), gpios)
+
+#define POWER_GOOD_ENTRY(node_id)                      \
+	.power_good_dev = GET_POWER_GOOD_DEV(node_id), \
+	.power_good_pin = GET_POWER_GOOD_PIN(node_id),
+
+#define POWER_GOOD_ENTRY_NULL(node_id) \
+	.power_good_dev = NULL, .power_good_pin = 0,
+
+#define POWER_GOOD(node_id)                                \
+	[TEMP_SENSOR_ID(node_id)] = { COND_CODE_1(         \
+		DT_NODE_HAS_PROP(node_id, power_good_pin), \
+		(POWER_GOOD_ENTRY(node_id)),               \
+		(POWER_GOOD_ENTRY_NULL(node_id))) }
+
+#if ANY_INST_HAS_POWER_GOOD_PIN
+#define FILL_POWER_GOOD(node_id)                                       \
+	COND_CODE_1(DT_NODE_HAS_PROP(node_id, power_good_pin),         \
+		    (.power_good_dev = GET_POWER_GOOD_DEV(node_id),    \
+		     .power_good_pin = GET_POWER_GOOD_PIN(node_id), ), \
+		    (.power_good_dev = NULL, .power_good_pin = 0, ))
+#else
+#define FILL_POWER_GOOD(node_id)
+#endif /* ANY_INST_HAS_POWER_GOOD_PIN */
+
+#ifndef CONFIG_PLATFORM_EC_CUSTOMIZED_DESIGN
+
+static int thermistor_get_temp(const struct temp_sensor_t *sensor,
+			       int *temp_ptr)
+{
+	return thermistor_get_temperature(sensor->idx, temp_ptr,
+					  sensor->zephyr_info->thermistor);
+}
+
+#define GET_THERMISTOR_DATUM(node_sample_id)                                 \
+	[DT_PROP(node_sample_id,                                             \
+		 sample_index)] = { .mv = DT_PROP(node_sample_id, milivolt), \
+				    .temp = DT_PROP(node_sample_id, temp) }
+
+#define DEFINE_THERMISTOR_DATA(node_id)                                   \
+	static const struct thermistor_data_pair DT_CAT(                  \
+		node_id, _thermistor_data)[] = {                          \
+		DT_FOREACH_CHILD_SEP(node_id, GET_THERMISTOR_DATUM, (, )) \
+	};
+
+#define GET_THERMISTOR_INFO(node_id)                                \
+	(&(const struct thermistor_info){                           \
+		.scaling_factor = DT_PROP(node_id, scaling_factor), \
+		.num_pairs = DT_PROP(node_id, num_pairs),           \
+		.data = DT_CAT(node_id, _thermistor_data),          \
+	})
+
+#define GET_ZEPHYR_TEMP_SENSOR_THERMISTOR(named_id, sensor_id) \
+	(&(const struct zephyr_temp_sensor){                   \
+		.read = &thermistor_get_temp,                  \
+		.thermistor = GET_THERMISTOR_INFO(             \
+			DT_PHANDLE(sensor_id, thermistor)),    \
+		.update_temperature = NULL,                    \
+		FILL_POWER_GOOD(named_id) })
+
+#define TEMP_THERMISTOR(named_id, sensor_id)                                 \
+	[TEMP_SENSOR_ID(named_id)] = {                                       \
+		.name = DT_NODE_FULL_NAME(sensor_id),                        \
+		.idx = ZSHIM_ADC_ID(DT_PHANDLE(sensor_id, adc)),             \
+		.type = TEMP_SENSOR_TYPE_BOARD,                              \
+		.zephyr_info = GET_ZEPHYR_TEMP_SENSOR_THERMISTOR(named_id,   \
+								 sensor_id), \
+	}
+
+DT_FOREACH_STATUS_OKAY(cros_ec_thermistor, DEFINE_THERMISTOR_DATA)
+
+#endif /* CONFIG_PLATFORM_EC_CUSTOMIZED_DESIGN */
+
+#if DT_HAS_COMPAT_STATUS_OKAY(PCT2075_COMPAT)
+/* The function maybe unused because a temperature sensor can be added to dts
+ * without a reference in the cros_ec_temp_sensors node.
+ */
+__maybe_unused static int pct2075_get_temp(const struct temp_sensor_t *sensor,
+					   int *temp_ptr)
+{
+	return pct2075_get_val_k(sensor->idx, temp_ptr);
+}
+#endif /* PCT2075_COMPAT */
+
+#define DEFINE_PCT2075_DATA(node_id)                                  \
+	[PCT2075_SENSOR_ID(node_id)] = {                              \
+		.i2c_port = I2C_PORT_BY_DEV(node_id),                 \
+		.i2c_addr_flags =                                     \
+			(DT_REG_ADDR(node_id) | I2C_FLAG_BIG_ENDIAN), \
+	},
+
+#define GET_ZEPHYR_TEMP_SENSOR_PCT2075(named_id)                  \
+	(&(const struct zephyr_temp_sensor){                      \
+		.read = &pct2075_get_temp,                        \
+		.thermistor = NULL,                               \
+		.update_temperature = pct2075_update_temperature, \
+		FILL_POWER_GOOD(named_id) })
+
+#define TEMP_PCT2075(named_id, sensor_id)                                \
+	[TEMP_SENSOR_ID(named_id)] = {                                   \
+		.name = DT_NODE_FULL_NAME(sensor_id),                    \
+		.idx = PCT2075_SENSOR_ID(sensor_id),                     \
+		.type = TEMP_SENSOR_TYPE_BOARD,                          \
+		.zephyr_info = GET_ZEPHYR_TEMP_SENSOR_PCT2075(named_id), \
+	}
+
+const struct pct2075_sensor_t pct2075_sensors[PCT2075_COUNT] = {
+	DT_FOREACH_STATUS_OKAY(PCT2075_COMPAT, DEFINE_PCT2075_DATA)
+};
+
+#if DT_HAS_COMPAT_STATUS_OKAY(SB_TSI_COMPAT)
+/* The function maybe unused because a temperature sensor can be added to dts
+ * without a reference in the cros_ec_temp_sensors node.
+ */
+__maybe_unused static int sb_tsi_get_temp(const struct temp_sensor_t *sensor,
+					  int *temp_ptr)
+{
+	return sb_tsi_get_val(sensor->idx, temp_ptr);
+}
+
+/* There can be only one SB TSI sensor with current driver */
+#if DT_NUM_INST_STATUS_OKAY(SB_TSI_COMPAT) > 1
+#error "Unsupported number of SB TSI sensors"
+#endif
+
+#endif /* SB_TSI_COMPAT */
+
+#define GET_ZEPHYR_TEMP_SENSOR_SB_TSI(named_id)                          \
+	(&(const struct zephyr_temp_sensor){ .read = &sb_tsi_get_temp,   \
+					     .thermistor = NULL,         \
+					     .update_temperature = NULL, \
+					     FILL_POWER_GOOD(named_id) })
+
+#define TEMP_SB_TSI(named_id, sensor_id)                                \
+	[TEMP_SENSOR_ID(named_id)] = {                                  \
+		.name = DT_NODE_FULL_NAME(sensor_id),                   \
+		.idx = 0,                                               \
+		.type = TEMP_SENSOR_TYPE_CPU,                           \
+		.zephyr_info = GET_ZEPHYR_TEMP_SENSOR_SB_TSI(named_id), \
+	}
+
+#if DT_HAS_COMPAT_STATUS_OKAY(TMP112_COMPAT)
+/* The function maybe unused because a temperature sensor can be added to dts
+ * without a reference in the cros_ec_temp_sensors node.
+ */
+__maybe_unused static int tmp112_get_temp(const struct temp_sensor_t *sensor,
+					  int *temp_ptr)
+{
+	return tmp112_get_val_k(sensor->idx, temp_ptr);
+}
+#endif /* TMP112_COMPAT */
+
+#define DEFINE_TMP112_DATA(node_id)                     \
+	[TMP112_SENSOR_ID(node_id)] = {                 \
+		.i2c_port = I2C_PORT_BY_DEV(node_id),   \
+		.i2c_addr_flags = DT_REG_ADDR(node_id), \
+	},
+
+#define GET_ZEPHYR_TEMP_SENSOR_TMP112(named_id)                  \
+	(&(const struct zephyr_temp_sensor){                     \
+		.read = &tmp112_get_temp,                        \
+		.thermistor = NULL,                              \
+		.update_temperature = tmp112_update_temperature, \
+		FILL_POWER_GOOD(named_id) })
+
+#define TEMP_TMP112(named_id, sensor_id)                                \
+	[TEMP_SENSOR_ID(named_id)] = {                                  \
+		.name = DT_NODE_FULL_NAME(sensor_id),                   \
+		.idx = TMP112_SENSOR_ID(sensor_id),                     \
+		.type = TEMP_SENSOR_TYPE_BOARD,                         \
+		.zephyr_info = GET_ZEPHYR_TEMP_SENSOR_TMP112(named_id), \
+	}
+
+const struct tmp112_sensor_t tmp112_sensors[TMP112_COUNT] = {
+	DT_FOREACH_STATUS_OKAY(TMP112_COMPAT, DEFINE_TMP112_DATA)
+};
+
+#if DT_HAS_COMPAT_STATUS_OKAY(F75303_COMPAT)
+/* The function maybe unused because a temperature sensor can be added to dts
+ * without a reference in the cros_ec_temp_sensors node.
+ */
+__maybe_unused static int f75303_get_temp(const struct temp_sensor_t *sensor,
+					  int *temp_ptr)
+{
+	return f75303_get_val_k(sensor->idx, temp_ptr);
+}
+#endif /* f75303_COMPAT */
+
+#define DEFINE_F75303_DATA(sensor_id)                     \
+	[F75303_SENSOR_ID(sensor_id)] = {                 \
+		.i2c_port = I2C_PORT_BY_DEV(sensor_id),   \
+		.i2c_addr_flags = DT_REG_ADDR(sensor_id), \
+	},
+
+#define GET_ZEPHYR_TEMP_SENSOR_F75303(named_id, sensor_id)       \
+	(&(const struct zephyr_temp_sensor){                     \
+		.read = &f75303_get_temp,                        \
+		.thermistor = NULL,                              \
+		.update_temperature = f75303_update_temperature, \
+		FILL_POWER_GOOD(named_id) })
+
+#define TEMP_F75303(named_id, sensor_id)                                    \
+	[TEMP_SENSOR_ID(named_id)] = {                                      \
+		.name = DT_NODE_FULL_NAME(sensor_id),                       \
+		.idx = F75303_SENSOR_ID(sensor_id),                         \
+		.type = TEMP_SENSOR_TYPE_BOARD,                             \
+		.zephyr_info =                                              \
+			GET_ZEPHYR_TEMP_SENSOR_F75303(named_id, sensor_id), \
+	}
+
+const struct f75303_sensor_t f75303_sensors[F75303_IDX_COUNT] = {
+	DT_FOREACH_STATUS_OKAY(F75303_COMPAT, DEFINE_F75303_DATA)
+};
+
+
+#ifdef CONFIG_PLATFORM_EC_CUSTOMIZED_DESIGN
+#if DT_HAS_COMPAT_STATUS_OKAY(AMDR23M_COMPAT)
+/* The function maybe unused because a temperature sensor can be added to dts
+ * without a reference in the cros_ec_temp_sensors node.
+ */
+__maybe_unused static int amdr23m_get_temp(const struct temp_sensor_t *sensor,
+					  int *temp_ptr)
+{
+	return amdr23m_get_val_k(sensor->idx, temp_ptr);
+}
+#endif /* AMDR23M_COMPAT_COMPAT */
+
+#define DEFINE_AMDR23M_DATA(node_id)                     \
+	[AMDR23M_SENSOR_ID(node_id)] = {                 \
+		.i2c_port = I2C_PORT_BY_DEV(node_id),   \
+		.i2c_addr_flags = DT_REG_ADDR(node_id), \
+	},
+
+#define GET_ZEPHYR_TEMP_SENSOR_AMDR23M(named_id, sensor_id)        \
+	(&(const struct zephyr_temp_sensor){                     \
+		.read = &amdr23m_get_temp,                        \
+		.thermistor = NULL,                              \
+		.update_temperature = amdr23m_update_temperature, \
+		FILL_POWER_GOOD(named_id) })
+
+#define TEMP_AMDR23M(named_id, sensor_id)                                \
+	[TEMP_SENSOR_ID(named_id)] = {                                  \
+		.name = DT_NODE_FULL_NAME(sensor_id),                   \
+		.idx = AMDR23M_SENSOR_ID(sensor_id),                     \
+		.type = TEMP_SENSOR_TYPE_BOARD,                         \
+		.zephyr_info = GET_ZEPHYR_TEMP_SENSOR_AMDR23M(named_id, sensor_id), \
+	}
+
+const struct amdr23m_sensor_t amdr23m_sensors[AMDR23M_COUNT] = {
+	DT_FOREACH_STATUS_OKAY(AMDR23M_COMPAT, DEFINE_AMDR23M_DATA)
+};
+#endif /* CONFIG_PLATFORM_EC_CUSTOMIZED_DESIGN */
+
+/* There can be only one thermistor on RT9490 with current driver */
+#define ADD_ONE(node_id) 1 +
+#if DT_FOREACH_STATUS_OKAY_VARGS(RT9490_CHG_COMPAT, TEMP_RT9490_FN, \
+				 ADD_ONE) 0 > 1
+#error "Unsupported number of thermistor on RT9490"
+#endif
+#undef ADD_ONE
+
+#define GET_ZEPHYR_TEMP_SENSOR_RT9490(named_id, sensor_id)  \
+	(&(const struct zephyr_temp_sensor){                \
+		.read = &rt9490_get_thermistor_val,         \
+		.thermistor = GET_THERMISTOR_INFO(          \
+			DT_PHANDLE(sensor_id, thermistor)), \
+		.update_temperature = NULL,                 \
+		FILL_POWER_GOOD(named_id) })
+
+#define TEMP_RT9490(named_id, sensor_id) \
+	COND_CODE_1(DT_NODE_HAS_PROP(sensor_id, thermistor), (                 \
+		[TEMP_SENSOR_ID(named_id)] = {                                 \
+			.name = DT_NODE_FULL_NAME(sensor_id),                  \
+			.idx = 0,                                              \
+			.type = TEMP_SENSOR_TYPE_BOARD,                        \
+			.zephyr_info = GET_ZEPHYR_TEMP_SENSOR_RT9490(named_id, \
+				       sensor_id),                             \
+		} ), ())
+
+#define DT_DRV_COMPAT TEMP_SENSORS_COMPAT
+
+#define CHECK_COMPAT(compat, named_id, sensor_id, config_fn) \
+	COND_CODE_1(DT_NODE_HAS_COMPAT(sensor_id, compat),   \
+		    (config_fn(named_id, sensor_id)), ())
+
+#define TEMP_SENSOR_FIND(named_id, sensor_id)                                 \
+	CHECK_COMPAT(THERMISTOR_COMPAT, named_id, sensor_id, TEMP_THERMISTOR) \
+	CHECK_COMPAT(PCT2075_COMPAT, named_id, sensor_id, TEMP_PCT2075)       \
+	CHECK_COMPAT(SB_TSI_COMPAT, named_id, sensor_id, TEMP_SB_TSI)         \
+	CHECK_COMPAT(TMP112_COMPAT, named_id, sensor_id, TEMP_TMP112)         \
+	CHECK_COMPAT(RT9490_CHG_COMPAT, named_id, sensor_id, TEMP_RT9490)     \
+	CHECK_COMPAT(F75303_COMPAT, named_id, sensor_id, TEMP_F75303)         \
+	CHECK_COMPAT(AMDR23M_COMPAT, named_id, sensor_id, TEMP_AMDR23M)
+
+
+#define TEMP_SENSOR_ENTRY(named_id) \
+	TEMP_SENSOR_FIND(named_id, DT_PHANDLE(named_id, sensor))
+
+const struct temp_sensor_t temp_sensors[] = { DT_FOREACH_CHILD_SEP(
+	TEMP_SENSORS_NODEID, TEMP_SENSOR_ENTRY, (, )) };
+
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+static bool temp_sensor_check_power(const struct temp_sensor_t *sensor)
+{
+#if ANY_INST_HAS_POWER_GOOD_PIN
+	if (sensor->zephyr_info->power_good_dev) {
+		if (!gpio_pin_get(sensor->zephyr_info->power_good_dev,
+				  sensor->zephyr_info->power_good_pin))
+			return false;
+	}
+#endif
+	return true;
+}
+
+int temp_sensor_read(enum temp_sensor_id id, int *temp_ptr)
+{
+	const struct temp_sensor_t *sensor;
+
+	if (id < 0 || id >= TEMP_SENSOR_COUNT)
+		return EC_ERROR_INVAL;
+	sensor = temp_sensors + id;
+
+	if (!temp_sensor_check_power(sensor))
+		return EC_ERROR_NOT_POWERED;
+
+	return sensor->zephyr_info->read(sensor, temp_ptr);
+}
+
+void temp_sensors_update(void)
+{
+	for (int i = 0; i < TEMP_SENSOR_COUNT; i++) {
+		const struct temp_sensor_t *sensor = temp_sensors + i;
+
+		if (!sensor->zephyr_info->update_temperature)
+			continue;
+
+		if (!temp_sensor_check_power(sensor))
+			continue;
+
+		sensor->zephyr_info->update_temperature(sensor->idx);
+	}
+}
+DECLARE_HOOK(HOOK_SECOND, temp_sensors_update, HOOK_PRIO_TEMP_SENSOR);
+
+#endif /* DT_HAS_COMPAT_STATUS_OKAY(TEMP_SENSORS_COMPAT) */
diff --git a/zephyr/shim/src/test_util.c b/zephyr/shim/src/test_util.c
new file mode 100644
index 0000000000..e999772fc6
--- /dev/null
+++ b/zephyr/shim/src/test_util.c
@@ -0,0 +1,20 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Test utilities.
+ */
+
+#include "test_util.h"
+
+/* Linear congruential pseudo random number generator */
+uint32_t prng(uint32_t seed)
+{
+	return 22695477 * seed + 1;
+}
+
+uint32_t prng_no_seed(void)
+{
+	static uint32_t seed = 0x1234abcd;
+	return seed = prng(seed);
+}
diff --git a/zephyr/shim/src/thermal.c b/zephyr/shim/src/thermal.c
new file mode 100644
index 0000000000..fd1b0bfb52
--- /dev/null
+++ b/zephyr/shim/src/thermal.c
@@ -0,0 +1,52 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+#include "temp_sensor.h"
+#include "temp_sensor/temp_sensor.h"
+
+#define THERMAL_CONFIG(node_id) \
+	[TEMP_SENSOR_ID(node_id)] = {				\
+		.temp_host = {						\
+			[EC_TEMP_THRESH_WARN] =			\
+			C_TO_K(DT_PROP_OR(node_id,			\
+					  temp_host_warn,		\
+					  -273)),			\
+			[EC_TEMP_THRESH_HIGH] =			\
+			C_TO_K(DT_PROP_OR(node_id,			\
+					  temp_host_high,		\
+					  -273)),			\
+			[EC_TEMP_THRESH_HALT] =			\
+			C_TO_K(DT_PROP_OR(node_id,			\
+					  temp_host_halt,		\
+					  -273)),			\
+		},							\
+		.temp_host_release = {					\
+			[EC_TEMP_THRESH_WARN] = C_TO_K(		\
+				DT_PROP_OR(node_id,			\
+					   temp_host_release_warn,	\
+					   -273)),			\
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(		\
+				DT_PROP_OR(node_id,			\
+					   temp_host_release_high,	\
+					   -273)),			\
+			[EC_TEMP_THRESH_HALT] = C_TO_K(		\
+				DT_PROP_OR(node_id,			\
+					   temp_host_release_halt,	\
+					   -273)),			\
+		},							\
+		.temp_fan_off = C_TO_K(DT_PROP_OR(node_id,		\
+						  temp_fan_off,	\
+						  -273)),		\
+		.temp_fan_max = C_TO_K(DT_PROP_OR(node_id,		\
+						  temp_fan_max,	\
+						  -273)),		\
+	}
+
+struct ec_thermal_config thermal_params[] = {
+#if DT_HAS_COMPAT_STATUS_OKAY(TEMP_SENSORS_COMPAT)
+	DT_FOREACH_CHILD_SEP(TEMP_SENSORS_NODEID, THERMAL_CONFIG, (, ))
+#endif /* DT_HAS_COMPAT_STATUS_OKAY(TEMP_SENSORS_COMPAT) */
+};
diff --git a/zephyr/shim/src/usb_muxes.c b/zephyr/shim/src/usb_muxes.c
new file mode 100644
index 0000000000..b3854e2ca8
--- /dev/null
+++ b/zephyr/shim/src/usb_muxes.c
@@ -0,0 +1,92 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "usb_mux.h"
+#include "usbc/usb_muxes.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/sys/util_macro.h>
+
+/**
+ * @brief Check if @p mux_id is not part of @p chain_id or if @p chain_id USBC
+ *        port is the same as @p mux_port. Result ends with && to construct
+ *        logical expression using FOREACH macro.
+ *
+ * @param chain_id Chain DTS node ID
+ * @param mux_id USB mux node ID
+ * @param mux_port Port which should be associated with @p mux_id
+ */
+#define USB_MUX_NOT_IN_CHAIN_OR_PORT_EQ(chain_id, mux_id, mux_port) \
+	((USB_MUX_FIND_PORT(chain_id, mux_id)(-1)) == -1 ||         \
+	 USBC_PORT(chain_id) == mux_port) &&
+
+/**
+ * @brief Check if all chains that contains @p mux_id have the same USB-C port
+ *
+ * @param mux_id USB mux node ID
+ * @param unused_conf Unused argument required by USB_MUX_FOREACH_MUX()
+ */
+#define USB_MUX_CHECK_ALL_PORTS_ARE_SAME(mux_id, unused_conf)                \
+	BUILD_ASSERT(                                                        \
+		USB_MUX_FOREACH_CHAIN_VARGS(USB_MUX_NOT_IN_CHAIN_OR_PORT_EQ, \
+					    mux_id, USB_MUX_PORT(mux_id)) 1, \
+		"USB mux  " #mux_id " is in chains for different ports");
+
+/** Check if for every mux, chains where mux is present have the same port */
+USB_MUX_FOREACH_MUX(USB_MUX_CHECK_ALL_PORTS_ARE_SAME)
+
+/**
+ * Declare all usb_mux_chain structures e.g.
+ * MAYBE_CONST struct usb_mux_chain
+ * USB_MUX_chain_port_<port_id>_mux_<position_id>;
+ */
+USB_MUX_FOREACH_CHAIN_VARGS(USB_MUX_FOREACH_NO_ROOT_MUX,
+			    USB_MUX_CHAIN_STRUCT_DECLARE_OP)
+
+/**
+ * Define usb_mux_chain structures for main chain e.g.
+ *
+ * MAYBE_CONST struct usb_mux_chain
+ * USB_MUX_chain_port_<port_id>_mux_<position_id> = {
+ *         .mux = &USB_MUX_NODE_DT_N_S_usbc_S_port0_0_S_virtual_mux_0,
+ *         .next = &USB_MUX_chain_port_0_mux_1,
+ * }
+ */
+USB_MUX_FOREACH_CHAIN_VARGS(USB_MUX_FOR_MAIN_CHAIN, USB_MUX_FOREACH_NO_ROOT_MUX,
+			    USB_MUX_CHAIN_STRUCT_DEFINE_OP)
+
+/**
+ * Forward declarations for board_init and board_set callbacks. e.g.
+ * int c0_mux0_board_init(const struct usb_mux *);
+ * int c1_mux0_board_set(const struct usb_mux *, mux_state_t);
+ */
+USB_MUX_FOREACH_MUX(USB_MUX_CB_BOARD_INIT_DECLARE_IF_EXISTS)
+USB_MUX_FOREACH_MUX(USB_MUX_CB_BOARD_SET_DECLARE_IF_EXISTS)
+
+/**
+ * Define root of each USB muxes chain e.g.
+ * [0] = {
+ *         .mux = &USB_MUX_NODE_DT_N_S_usbc_S_port0_0_S_virtual_mux_0,
+ *         .next = &USB_MUX_chain_port_0_mux_1,
+ * },
+ * [1] = { ... },
+ */
+MAYBE_CONST struct usb_mux_chain usb_muxes[] = { USB_MUX_FOREACH_CHAIN_VARGS(
+	USB_MUX_FOR_MAIN_CHAIN, USB_MUX_DEFINE_ROOT_MUX) };
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == CONFIG_USB_PD_PORT_MAX_COUNT);
+
+/**
+ * Define all USB muxes e.g.
+ * MAYBE_CONST struct usb_mux USB_MUX_NODE_DT_N_S_usbc_S_port0_0_S_mux_0 = {
+ *         .usb_port = 0,
+ *         .board_init = NULL,
+ *         .board_set = NULL,
+ *         .flags = 0,
+ *         .driver = &virtual_usb_mux_driver,
+ *         .hpd_update = &virtual_hpd_update,
+ * };
+ * MAYBE_CONST struct usb_mux USB_MUX_NODE_<node_id> = { ... };
+ */
+USB_MUX_FOREACH_MUX(USB_MUX_DEFINE)
diff --git a/zephyr/shim/src/usba.c b/zephyr/shim/src/usba.c
new file mode 100644
index 0000000000..91d906ac31
--- /dev/null
+++ b/zephyr/shim/src/usba.c
@@ -0,0 +1,26 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define DT_DRV_COMPAT cros_ec_usba_port_enable_pins
+
+#include "hooks.h"
+#include "usb_charge.h"
+
+#include <zephyr/devicetree.h>
+
+#define PIN(node_id, prop, idx) \
+	GPIO_SIGNAL(DT_PHANDLE_BY_IDX(node_id, prop, idx)),
+
+BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 0,
+	     "No compatible USBA Port Enable instance found");
+
+#define USBA_ENABLE_PINS(inst) DT_INST_FOREACH_PROP_ELEM(inst, enable_pins, PIN)
+
+#if !IS_ENABLED(CONFIG_PLATFORM_EC_USB_PORT_ENABLE_DYNAMIC)
+const
+#endif
+	int usb_port_enable[USB_PORT_ENABLE_COUNT] = {
+		DT_INST_FOREACH_STATUS_OKAY(USBA_ENABLE_PINS)
+	};
diff --git a/zephyr/shim/src/watchdog.c b/zephyr/shim/src/watchdog.c
new file mode 100644
index 0000000000..0b96cbaa0e
--- /dev/null
+++ b/zephyr/shim/src/watchdog.c
@@ -0,0 +1,172 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "config.h"
+#include "hooks.h"
+#include "watchdog.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/watchdog.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(watchdog_shim, LOG_LEVEL_ERR);
+
+struct watchdog_info {
+	const struct device *wdt_dev;
+	struct wdt_timeout_cfg config;
+};
+
+__maybe_unused static void wdt_warning_handler(const struct device *wdt_dev,
+					       int channel_id);
+
+const struct watchdog_info wdt_info[] = {
+	{
+		.wdt_dev = DEVICE_DT_GET(DT_CHOSEN(cros_ec_watchdog)),
+		.config = {
+#if DT_NODE_HAS_COMPAT(DT_CHOSEN(cros_ec_watchdog), st_stm32_watchdog)
+			.flags = WDT_FLAG_RESET_SOC,
+			.window.min = 0U,
+			.window.max = CONFIG_WATCHDOG_PERIOD_MS,
+			.callback = NULL,
+#else
+			.flags = WDT_FLAG_RESET_SOC,
+			.window.min = 0U,
+			.window.max = CONFIG_AUX_TIMER_PERIOD_MS,
+			.callback = wdt_warning_handler,
+#endif
+		},
+	},
+#ifdef CONFIG_PLATFORM_EC_WATCHDOG_HELPER
+	{
+		.wdt_dev = DEVICE_DT_GET(DT_CHOSEN(cros_ec_watchdog_helper)),
+		.config = {
+			.flags = 0U,
+			.window.min = 0U,
+			.window.max = CONFIG_AUX_TIMER_PERIOD_MS,
+			.callback = wdt_warning_handler,
+		},
+	},
+#endif
+};
+
+/* Array to keep channel used to implement watchdog */
+int wdt_chan[ARRAY_SIZE(wdt_info)];
+bool watchdog_initialized;
+
+#ifdef TEST_BUILD
+bool wdt_warning_triggered;
+#endif /* TEST_BUILD */
+
+static int watchdog_config(const struct watchdog_info *info)
+{
+	const struct device *wdt_dev = info->wdt_dev;
+	const struct wdt_timeout_cfg *config = &info->config;
+	int chan;
+
+	chan = wdt_install_timeout(wdt_dev, config);
+
+	/* If watchdog is running, reinstall it. */
+	if (chan == -EBUSY) {
+		wdt_disable(wdt_dev);
+		chan = wdt_install_timeout(wdt_dev, config);
+	}
+
+	if (chan < 0) {
+		LOG_ERR("Watchdog install error: %d", chan);
+	}
+
+	return chan;
+}
+
+static int watchdog_enable(const struct device *wdt_dev)
+{
+	int err;
+
+	err = wdt_setup(wdt_dev, 0);
+	if (err < 0)
+		LOG_ERR("Watchdog %s setup error: %d", wdt_dev->name, err);
+
+	return err;
+}
+
+static int watchdog_init_device(const struct watchdog_info *info)
+{
+	const struct device *wdt_dev = info->wdt_dev;
+	int chan, err;
+
+	if (!device_is_ready(wdt_dev)) {
+		LOG_ERR("Error: device %s is not ready", wdt_dev->name);
+		return -ENODEV;
+	}
+
+	chan = watchdog_config(info);
+	if (chan < 0)
+		return chan;
+
+	err = watchdog_enable(wdt_dev);
+	if (err < 0)
+		return err;
+
+	return chan;
+}
+
+int watchdog_init(void)
+{
+	int err = EC_SUCCESS;
+
+	if (watchdog_initialized)
+		return -EBUSY;
+
+	for (int i = 0; i < ARRAY_SIZE(wdt_info); i++) {
+		wdt_chan[i] = watchdog_init_device(&wdt_info[i]);
+		if (wdt_chan[i] < 0 && err == EC_SUCCESS)
+			err = wdt_chan[i];
+	}
+
+	watchdog_initialized = true;
+	watchdog_reload();
+
+	return err;
+}
+
+void watchdog_reload(void)
+{
+	if (!watchdog_initialized)
+		return;
+
+	for (int i = 0; i < ARRAY_SIZE(wdt_info); i++) {
+		if (wdt_chan[i] < 0)
+			continue;
+
+		wdt_feed(wdt_info[i].wdt_dev, wdt_chan[i]);
+	}
+}
+DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT);
+
+__maybe_unused static void wdt_warning_handler(const struct device *wdt_dev,
+					       int channel_id)
+{
+	const char *thread_name = k_thread_name_get(k_current_get());
+
+#ifdef CONFIG_RISCV
+	printk("WDT pre-warning MEPC:%p THREAD_NAME:%s\n",
+	       (void *)csr_read(mepc), thread_name);
+#else
+	/* TODO(b/176523207): watchdog warning message */
+	printk("Watchdog deadline is close! THREAD_NAME:%s\n", thread_name);
+#endif
+#ifdef TEST_BUILD
+	wdt_warning_triggered = true;
+#endif
+#ifdef CONFIG_SOC_SERIES_MEC172X
+	extern void cros_chip_wdt_handler(const struct device *wdt_dev,
+					  int channel_id);
+	cros_chip_wdt_handler(wdt_dev, channel_id);
+#endif
+
+	/* Watchdog is disabled after calling handler. Re-enable it now. */
+	watchdog_enable(wdt_dev);
+}
diff --git a/zephyr/shim/src/ztest_system.c b/zephyr/shim/src/ztest_system.c
new file mode 100644
index 0000000000..13614ec8f0
--- /dev/null
+++ b/zephyr/shim/src/ztest_system.c
@@ -0,0 +1,101 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "charge_manager.h"
+#include "common.h"
+#include "cros_version.h"
+#include "sysjump.h"
+#include "system.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+char mock_jump_data[CONFIG_PLATFORM_EC_PRESERVED_END_OF_RAM_SIZE];
+
+/* When CONFIG_RAM_SIZE is defined, this is provided by common/system.c */
+#ifndef CONFIG_RAM_SIZE
+struct jump_data *get_jump_data(void)
+{
+	return (struct jump_data *)&mock_jump_data;
+}
+#endif
+
+__attribute__((weak)) void system_reset(int flags)
+{
+	__builtin_unreachable();
+}
+
+__attribute__((weak)) void software_panic(uint32_t reason, uint32_t info)
+{
+	__builtin_unreachable();
+}
+
+static uint8_t bbram[SYSTEM_BBRAM_IDX_TRY_SLOT + 1];
+
+test_mockable int system_get_bbram(enum system_bbram_idx idx, uint8_t *value)
+{
+	if (idx <= SYSTEM_BBRAM_IDX_TRY_SLOT) {
+		*value = bbram[idx];
+		return EC_SUCCESS;
+	}
+	return EC_ERROR_INVAL;
+}
+
+test_mockable int system_set_bbram(enum system_bbram_idx idx, uint8_t value)
+{
+	if (idx <= SYSTEM_BBRAM_IDX_TRY_SLOT) {
+		bbram[idx] = value;
+		return EC_SUCCESS;
+	}
+	return EC_ERROR_INVAL;
+}
+
+/* When CONFIG_EC_PROTECTED_STORAGE_OFF is defined, this is provided by
+ * common/system.c
+ */
+#ifndef CONFIG_EC_PROTECTED_STORAGE_OFF
+uint32_t flash_get_rw_offset(enum ec_image copy)
+{
+	return 0;
+}
+#endif
+
+/* When CONFIG_PLATFORM_EC_FLASH_CROS is defined, this is provided by
+ * common/flash.c
+ */
+#ifndef CONFIG_PLATFORM_EC_FLASH_CROS
+int crec_flash_read(int offset, int size, char *data)
+{
+	return EC_ERROR_INVAL;
+}
+
+uint32_t crec_flash_get_protect(void)
+{
+	return 0;
+}
+#endif
+
+test_mockable const char *system_get_chip_vendor(void)
+{
+	return "Testing";
+}
+
+test_mockable const char *system_get_chip_name(void)
+{
+	return "emu";
+}
+
+test_mockable const char *system_get_chip_revision(void)
+{
+	return "";
+}
+
+test_mockable void board_reset_pd_mcu(void)
+{
+}
+
+test_mockable void system_hibernate(uint32_t seconds, uint32_t microseconds)
+{
+}
diff --git a/zephyr/subsys/CMakeLists.txt b/zephyr/subsys/CMakeLists.txt
new file mode 100644
index 0000000000..dfd1a35871
--- /dev/null
+++ b/zephyr/subsys/CMakeLists.txt
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(ap_pwrseq)
+add_subdirectory(emul)
diff --git a/zephyr/subsys/Kconfig b/zephyr/subsys/Kconfig
new file mode 100644
index 0000000000..48011312d5
--- /dev/null
+++ b/zephyr/subsys/Kconfig
@@ -0,0 +1,5 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+rsource "ap_pwrseq/Kconfig"
diff --git a/zephyr/subsys/ap_pwrseq/CMakeLists.txt b/zephyr/subsys/ap_pwrseq/CMakeLists.txt
new file mode 100644
index 0000000000..1e5ce44e2f
--- /dev/null
+++ b/zephyr/subsys/ap_pwrseq/CMakeLists.txt
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library_include_directories(include)
+
+zephyr_library_sources_ifdef(CONFIG_AP_EVENTS ap_events.c)
+
+zephyr_library_sources_ifdef(CONFIG_AP_PWRSEQ
+	ap_power_interface.c
+	power_host_sleep.c
+	power_signals.c
+	)
+
+zephyr_library_sources_ifdef(CONFIG_AP_PWRSEQ_SIGNAL_GPIO signal_gpio.c)
+zephyr_library_sources_ifdef(CONFIG_AP_PWRSEQ_SIGNAL_VW signal_vw.c)
+zephyr_library_sources_ifdef(CONFIG_AP_PWRSEQ_SIGNAL_ADC signal_adc.c)
+
+zephyr_library_sources_ifdef(CONFIG_AP_PWRSEQ_DRIVER ap_pwrseq.c)
+zephyr_library_sources_ifdef(CONFIG_AP_PWRSEQ_DRIVER ap_pwrseq_sm.c)
+
+zephyr_library_sources_ifdef(CONFIG_X86_NON_DSX_PWRSEQ
+	x86_non_dsx_common_pwrseq_sm_handler.c
+	x86_non_dsx_chipset_power_state.c)
+zephyr_library_sources_ifdef(CONFIG_AP_PWRSEQ_S0IX_ERROR_RECOVERY
+	x86_non_dsx_common_pwrseq_host_sleep.c)
+zephyr_library_sources_ifdef(CONFIG_X86_NON_DSX_PWRSEQ_CONSOLE
+	x86_non_dsx_common_pwrseq_console.c)
+zephyr_library_sources_ifdef(CONFIG_X86_NON_DSX_PWRSEQ_HOST_CMD
+	x86_non_dsx_common_pwrseq_host_command.c)
+zephyr_library_sources_ifdef(CONFIG_X86_NON_DSX_PWRSEQ_ADL
+	x86_non_dsx_adlp_pwrseq_sm.c)
+zephyr_library_sources_ifdef(CONFIG_X86_NON_DSX_PWRSEQ_MTL
+	x86_non_dsx_mtl_pwrseq_sm.c)
diff --git a/zephyr/subsys/ap_pwrseq/Kconfig b/zephyr/subsys/ap_pwrseq/Kconfig
new file mode 100644
index 0000000000..8bb064aac9
--- /dev/null
+++ b/zephyr/subsys/ap_pwrseq/Kconfig
@@ -0,0 +1,196 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+menuconfig AP_PWRSEQ
+	bool "AP Power sequencing support"
+	default y
+	depends on DT_HAS_INTEL_AP_PWRSEQ_ENABLED && !TEST_DISABLE_AP_PWRSEQ
+	select HAS_TASK_POWERBTN
+	select GPIO_GET_CONFIG
+	help
+	  Enables AP power sequencing support with
+	  embedded controller. This includes normal shutdown, critical
+	  shutdown and reset handling.
+	  Enabling this automatically enables HAS_TASK_POWERBTN since this task
+	  is required to handle power button pressed/released by user.
+	  Enabling this also enables retrieving the GPIO config feature
+	  so that the value of output GPIOs can be determined.
+
+if AP_PWRSEQ
+
+module = AP_PWRSEQ
+module-str = AP power sequencing
+source "subsys/logging/Kconfig.template.log_config"
+
+config AP_PWRSEQ_DRIVER
+	bool "AP Power sequencing driver support"
+	select SMF
+	select SMF_ANCESTOR_SUPPORT
+	select EVENTS
+	help
+	  AP power sequence driver establishes an underlaying framework to
+	  easily add or extend AP Power Sequence action handler routines, it is
+	  designed to follow the zephyr's State Machine Framework (SMF).
+
+config AP_PWRSEQ_SIGNAL_ADC
+	bool
+	default y
+	depends on DT_HAS_INTEL_AP_PWRSEQ_ADC_ENABLED
+	select SENSOR
+	help
+	  Helper symbol to enable ADC based power sequencing.
+
+config AP_PWRSEQ_SIGNAL_EXTERNAL
+	bool
+	default y
+	depends on DT_HAS_INTEL_AP_PWRSEQ_EXTERNAL_ENABLED
+	help
+	  Helper symbol to enable external signal based power sequencing.
+
+config AP_PWRSEQ_SIGNAL_GPIO
+	bool
+	default y
+	depends on DT_HAS_INTEL_AP_PWRSEQ_GPIO_ENABLED
+	help
+	  Helper symbol to enable GPIO based power sequencing.
+
+config AP_PWRSEQ_SIGNAL_VW
+	bool
+	default y
+	depends on DT_HAS_INTEL_AP_PWRSEQ_VW_ENABLED
+	help
+	  Helper symbol to enable virtual wire (VW) based power sequencing.
+
+config AP_PWRSEQ_SIGNAL_DEBUG_NAMES
+	bool
+	default y if PLATFORM_EC_BRINGUP
+	help
+	  Enable this option to allow display of the more descriptive
+	  dbg-name based signal names.
+	  Disable this option to just show the enum-name of the signals.
+	  Enabled by default during bringup.
+
+	  Disabling the option will save around 520 bytes of flash space.
+
+config AP_PWRSEQ_AUTOSTART
+	bool "Start the power sequence thread automatically"
+	default n
+	help
+	  This option starts the AP power sequence task
+	  at initialisation. If not set, ap_pwrseq_thread_start()
+	  needs to be called to start the task.
+
+	  Disable this option if there is other board or module
+	  initialization that must occur before the AP power sequence
+	  thread is started.
+
+config AP_PWRSEQ_STACK_SIZE
+	int "AP pwrseq stack size (in bytes)"
+	help
+	  This option specifies the size of the stack used by the
+	  AP power sequencing state machine thread handler.
+	  This must be set in a board configuration. If a default
+	  is set here, it cannot be overridden (if necessary), since
+	  this Kconfig appears before the EC chip specific stack
+	  sizes.
+
+config AP_PWRSEQ_THREAD_PRIORITY
+	int "AP pwrseq thread priority"
+	default 12
+	help
+	  This option determines AP power sequence thread priority, this number
+	  must be selected in such way thread priority is in the middle of all
+	  the enabled threads.
+
+config X86_NON_DSX_PWRSEQ
+	bool
+	default n
+	help
+	  This option enables Non Deep Sleep Well power sequencing for
+	  Intel x86 chips.
+
+config X86_NON_DSX_PWRSEQ_ADL
+	bool "x86 Non Deep Sx power sequencing on ADL"
+	depends on AP_X86_INTEL_ADL
+	select X86_NON_DSX_PWRSEQ
+	default n
+	help
+	  This enables AP power sequencing support for Intel Alderlake
+	  family of chipset.
+
+config X86_NON_DSX_PWRSEQ_MTL
+	bool "x86 Non Deep Sx power sequencing on MTL"
+	depends on AP_X86_INTEL_MTL
+	select X86_NON_DSX_PWRSEQ
+	default n
+	help
+	  This enables AP power sequencing support for Intel Meteorlake
+	  family of chipset.
+
+config X86_NON_DSX_PWRSEQ_CONSOLE
+	bool "Console commands for x86 Non Deep Sx power sequencing"
+	depends on X86_NON_DSX_PWRSEQ
+	default n
+	help
+	  This option enables Non Deep Sleep Well power sequencing shell
+	  console commands to debug.
+
+config X86_NON_DSX_PWRSEQ_HOST_CMD
+	bool "Host commands for x86 Non Deep Sx power sequencing"
+	depends on X86_NON_DSX_PWRSEQ
+	default y
+	help
+	  This option enables Non Deep Sleep Well power sequencing host
+	  commands to debug.
+
+config AP_PWRSEQ_HOST_SLEEP
+	bool "Handle host sleep state changes"
+	help
+	  Enable AP power sequencing to receive and process host command
+	  host sleep state changes.
+
+config AP_PWRSEQ_S0IX
+	bool "Enable power state S0ix for Intel x86 chipset"
+	select AP_PWRSEQ_HOST_SLEEP
+	default n
+	help
+	  This option enables power state S0ix for Intel x86 chipset. As
+	  required, AP_PWRSEQ_HOST_SLEEP for host sleep event handling is
+	  enabled.
+
+config AP_PWRSEQ_S0IX_ERROR_RECOVERY
+	bool "Detect failure to enter or exit Sleep state"
+	depends on AP_PWRSEQ_HOST_SLEEP
+	help
+	  Enables detection of the AP failing to go to sleep, perhaps due to a
+	  bug in the internal SoC periodic housekeeping code.
+
+	  Failure information is reported via the EC_CMD_HOST_SLEEP_EVENT host
+	  command.
+
+config AP_PWRSEQ_S0IX_COUNTER
+	bool "Enable S0ix counter"
+	depends on AP_PWRSEQ_S0IX
+	depends on AP_PWRSEQ_HOST_SLEEP
+	default y
+	help
+	  Enables counter which increases at every transitions to S0ix state.
+	  Counter can be read via host command.
+
+config AP_PWRSEQ_DEBUG_MODE_COMMAND
+	bool "Console commands to enable/disable AP debug mode"
+	depends on X86_NON_DSX_PWRSEQ
+	default y
+	help
+	  Intel debugger puts SOC in boot halt mode for step debugging,
+	  during this time EC may lose Sx lines, This option enables console
+	  command to enable debug mode and prevent force shutdown.
+
+endif
+
+config AP_EVENTS
+	bool "Enable AP events"
+	default y
+	help
+	  Helper symbol to enable Application Processor(AP) events.
diff --git a/zephyr/subsys/ap_pwrseq/ap_events.c b/zephyr/subsys/ap_pwrseq/ap_events.c
new file mode 100644
index 0000000000..0d99c0fe36
--- /dev/null
+++ b/zephyr/subsys/ap_pwrseq/ap_events.c
@@ -0,0 +1,80 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/kernel.h>
+
+#include <ap_power/ap_power.h>
+#include <ap_power/ap_power_events.h>
+
+static sys_slist_t callbacks;
+/*
+ * Contains the accumulated set of events that any
+ * callback has registered. This is a hint to detect events that
+ * have never had any callbacks registered, in which case the
+ * callback list does not have to be run.
+ */
+static uint32_t cb_set;
+
+static int ap_power_ev_manage_callback(struct ap_power_ev_callback *cb,
+				       bool set)
+{
+	__ASSERT(cb, "No callback!");
+	__ASSERT(cb->handler, "No callback handler!");
+
+	if (!sys_slist_is_empty(&callbacks)) {
+		if (!sys_slist_find_and_remove(&callbacks, &cb->node)) {
+			if (!set) {
+				return -EINVAL;
+			}
+		}
+	}
+	if (set) {
+		sys_slist_prepend(&callbacks, &cb->node);
+		cb_set |= cb->events;
+	}
+	return 0;
+}
+
+int ap_power_ev_add_callback(struct ap_power_ev_callback *cb)
+{
+	return ap_power_ev_manage_callback(cb, true);
+}
+
+int ap_power_ev_remove_callback(struct ap_power_ev_callback *cb)
+{
+	return ap_power_ev_manage_callback(cb, false);
+}
+
+void ap_power_ev_add_events(struct ap_power_ev_callback *cb,
+			    enum ap_power_events events)
+{
+	__ASSERT(cb, "Callback pointer should not be NULL");
+
+	cb->events |= events;
+	cb_set |= events;
+}
+
+/*
+ * Run the callback list
+ */
+void ap_power_ev_send_callbacks(enum ap_power_events event)
+{
+	struct ap_power_ev_data data;
+	struct ap_power_ev_callback *cb, *tmp;
+
+	/*
+	 * If no callbacks for this event, don't run the queue.
+	 */
+	if ((cb_set & event) == 0) {
+		return;
+	}
+	data.event = event;
+	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&callbacks, cb, tmp, node)
+	{
+		if (cb->events & event) {
+			cb->handler(cb, data);
+		}
+	}
+}
diff --git a/zephyr/subsys/ap_pwrseq/ap_power_interface.c b/zephyr/subsys/ap_pwrseq/ap_power_interface.c
new file mode 100644
index 0000000000..684bcbb5e0
--- /dev/null
+++ b/zephyr/subsys/ap_pwrseq/ap_power_interface.c
@@ -0,0 +1,184 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <ap_power/ap_power_interface.h>
+#include <x86_non_dsx_common_pwrseq_sm_handler.h>
+
+LOG_MODULE_DECLARE(ap_pwrseq, CONFIG_AP_PWRSEQ_LOG_LEVEL);
+
+#ifndef CONFIG_AP_PWRSEQ_DRIVER
+bool ap_power_in_state(enum ap_power_state_mask state_mask)
+{
+	int need_mask = 0;
+
+	switch (pwr_sm_get_state()) {
+	case SYS_POWER_STATE_UNINIT:
+		LOG_WRN("%s: init not yet complete; AP state is unknown",
+			__func__);
+		return false;
+	case SYS_POWER_STATE_G3:
+		need_mask = AP_POWER_STATE_HARD_OFF;
+		break;
+	case SYS_POWER_STATE_G3S5:
+	case SYS_POWER_STATE_S5G3:
+		/*
+		 * In between hard and soft off states.  Match only if caller
+		 * will accept both.
+		 */
+		need_mask = AP_POWER_STATE_HARD_OFF | AP_POWER_STATE_SOFT_OFF;
+		break;
+	case SYS_POWER_STATE_S5:
+		need_mask = AP_POWER_STATE_SOFT_OFF;
+		break;
+	case SYS_POWER_STATE_S5S4:
+	case SYS_POWER_STATE_S4S5:
+		need_mask = AP_POWER_STATE_SOFT_OFF | AP_POWER_STATE_SUSPEND;
+		break;
+	case SYS_POWER_STATE_S4:
+	case SYS_POWER_STATE_S4S3:
+	case SYS_POWER_STATE_S3S4:
+	case SYS_POWER_STATE_S3:
+		need_mask = AP_POWER_STATE_SUSPEND;
+		break;
+	case SYS_POWER_STATE_S3S0:
+	case SYS_POWER_STATE_S0S3:
+		need_mask = AP_POWER_STATE_SUSPEND | AP_POWER_STATE_ON;
+		break;
+	case SYS_POWER_STATE_S0:
+		need_mask = AP_POWER_STATE_ON;
+		break;
+#if CONFIG_AP_PWRSEQ_S0IX
+	case SYS_POWER_STATE_S0ixS0:
+	case SYS_POWER_STATE_S0S0ix:
+		need_mask = AP_POWER_STATE_ON | AP_POWER_STATE_STANDBY;
+		break;
+	case SYS_POWER_STATE_S0ix:
+		need_mask = AP_POWER_STATE_STANDBY;
+		break;
+#endif
+	}
+	/* Return non-zero if all needed bits are present */
+	return (state_mask & need_mask) == need_mask;
+}
+
+bool ap_power_in_or_transitioning_to_state(enum ap_power_state_mask state_mask)
+{
+	switch (pwr_sm_get_state()) {
+	case SYS_POWER_STATE_UNINIT:
+		LOG_WRN("%s: init not yet complete; AP state is unknown",
+			__func__);
+		return 0;
+	case SYS_POWER_STATE_G3:
+	case SYS_POWER_STATE_S5G3:
+		return state_mask & AP_POWER_STATE_HARD_OFF;
+	case SYS_POWER_STATE_S5:
+	case SYS_POWER_STATE_G3S5:
+	case SYS_POWER_STATE_S4S5:
+		return state_mask & AP_POWER_STATE_SOFT_OFF;
+	case SYS_POWER_STATE_S3:
+	case SYS_POWER_STATE_S4:
+	case SYS_POWER_STATE_S3S4:
+	case SYS_POWER_STATE_S5S4:
+	case SYS_POWER_STATE_S4S3:
+	case SYS_POWER_STATE_S0S3:
+		return state_mask & AP_POWER_STATE_SUSPEND;
+#if CONFIG_AP_PWRSEQ_S0IX
+	case SYS_POWER_STATE_S0ix:
+	case SYS_POWER_STATE_S0S0ix:
+		return state_mask & AP_POWER_STATE_STANDBY;
+#endif
+	case SYS_POWER_STATE_S0:
+	case SYS_POWER_STATE_S3S0:
+#if CONFIG_AP_PWRSEQ_S0IX
+	case SYS_POWER_STATE_S0ixS0:
+#endif
+		return state_mask & AP_POWER_STATE_ON;
+	}
+	/* Unknown power state; return false. */
+	return 0;
+}
+
+void ap_power_exit_hardoff(void)
+{
+	enum power_states_ndsx power_state;
+
+	/*
+	 * If not in the soft-off state, hard-off state, or headed there,
+	 * nothing to do.
+	 */
+	power_state = pwr_sm_get_state();
+	if (power_state != SYS_POWER_STATE_G3 &&
+	    power_state != SYS_POWER_STATE_S5G3 &&
+	    power_state != SYS_POWER_STATE_S5)
+		return;
+	request_start_from_g3();
+}
+#else
+bool ap_power_in_state(enum ap_power_state_mask state_mask)
+{
+	/*
+	 * PWRSEQ_DRIVER will only expose stable power states (transitions
+	 * occur automatically and are not visible to API consumers), so
+	 * return ap_power_in_or_transitioning_to_state since it is
+	 * equivalent to this function.
+	 */
+	return ap_power_in_or_transitioning_to_state(state_mask);
+}
+
+bool ap_power_in_or_transitioning_to_state(enum ap_power_state_mask state_mask)
+{
+	const struct device *dev = ap_pwrseq_get_instance();
+
+	switch (ap_pwrseq_get_current_state(dev)) {
+	case AP_POWER_STATE_G3:
+		return state_mask & AP_POWER_STATE_HARD_OFF;
+	case AP_POWER_STATE_S5:
+		return state_mask & AP_POWER_STATE_SOFT_OFF;
+	case AP_POWER_STATE_S3:
+	case AP_POWER_STATE_S4:
+		return state_mask & AP_POWER_STATE_SUSPEND;
+#if CONFIG_AP_PWRSEQ_S0IX
+	case AP_POWER_STATE_S0IX:
+		return state_mask & AP_POWER_STATE_STANDBY;
+#endif
+	case AP_POWER_STATE_S0:
+		return state_mask & AP_POWER_STATE_ON;
+	default:
+		break;
+	}
+	/* Unknown power state; return false. */
+	return 0;
+}
+
+void ap_power_exit_hardoff(void)
+{
+	const struct device *dev = ap_pwrseq_get_instance();
+	enum ap_pwrseq_state power_state;
+
+	ap_pwrseq_state_lock(dev);
+	/*
+	 * If not in the soft-off state, hard-off state, or headed there,
+	 * nothing to do.
+	 */
+	power_state = ap_pwrseq_get_current_state(dev);
+	if (power_state == AP_POWER_STATE_G3 ||
+	    power_state == AP_POWER_STATE_S5) {
+		request_start_from_g3();
+	}
+
+	ap_pwrseq_state_unlock(dev);
+}
+
+void ap_pwrseq_task_start(void)
+{
+	const struct device *dev = ap_pwrseq_get_instance();
+
+	ap_pwrseq_start(dev, chipset_pwr_seq_get_state());
+}
+#endif /* CONFIG_AP_PWRSEQ_DRIVER */
+
+void ap_power_init_reset_log(void)
+{
+}
diff --git a/zephyr/subsys/ap_pwrseq/ap_pwrseq.c b/zephyr/subsys/ap_pwrseq/ap_pwrseq.c
new file mode 100644
index 0000000000..6960938205
--- /dev/null
+++ b/zephyr/subsys/ap_pwrseq/ap_pwrseq.c
@@ -0,0 +1,314 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ap_pwrseq_drv_sm.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/atomic.h>
+
+LOG_MODULE_REGISTER(ap_pwrseq, CONFIG_AP_PWRSEQ_LOG_LEVEL);
+
+#define AP_PWRSEQ_EVENT_MASK GENMASK(AP_PWRSEQ_EVENT_COUNT - 1, 0)
+#define AP_PWRSEQ_STATES_MASK GENMASK(AP_POWER_STATE_COUNT - 1, 0)
+
+struct ap_pwrseq_cb_list {
+	uint32_t states;
+	sys_slist_t list;
+	struct k_spinlock lock;
+};
+
+struct ap_pwrseq_data {
+	/* State machine data reference. */
+	void *sm_data;
+	/* Driver event object to receive events posted. */
+	struct k_event evt;
+	/*
+	 * This mutex object blocks state machine transitions to prevent race
+	 * condition when doing power state related tasks. Must be held when
+	 * accessing `sm_data`.
+	 */
+	struct k_mutex mux;
+	/* State entry notification list. */
+	struct ap_pwrseq_cb_list entry_list;
+	/* State exit notification list. */
+	struct ap_pwrseq_cb_list exit_list;
+};
+
+/* Resolve into substate name string */
+#define AP_PWRSEQ_SUB_STATE_STR_DEFINE_WITH_COMA(state) state,
+
+#define AP_PWRSEQ_EACH_SUB_STATE_STR_DEFINE(node_id, prop, idx) \
+	AP_PWRSEQ_SUB_STATE_STR_DEFINE_WITH_COMA(               \
+		DT_CAT5(node_id, _P_, prop, _IDX_, idx))
+
+#define AP_PWRSEQ_EACH_SUB_STATE_STR_DEF_NODE_CHILD_DEFINE(node_id)          \
+	COND_CODE_1(                                                         \
+		DT_NODE_HAS_PROP(node_id, application),                      \
+		(DT_FOREACH_PROP_ELEM(node_id, application,                  \
+				      AP_PWRSEQ_EACH_SUB_STATE_STR_DEFINE)), \
+		(COND_CODE_1(DT_NODE_HAS_PROP(node_id, chipset),             \
+			     (DT_FOREACH_PROP_ELEM(                          \
+				     node_id, chipset,                       \
+				     AP_PWRSEQ_EACH_SUB_STATE_STR_DEFINE)),  \
+			     ())))
+
+static const char *const ap_pwrseq_state_str[AP_POWER_STATE_COUNT] = {
+	"AP_POWER_STATE_UNINIT",
+	"AP_POWER_STATE_G3",
+	"AP_POWER_STATE_S5",
+	"AP_POWER_STATE_S4",
+	"AP_POWER_STATE_S3",
+	"AP_POWER_STATE_S2",
+	"AP_POWER_STATE_S1",
+	"AP_POWER_STATE_S0",
+	DT_FOREACH_STATUS_OKAY(
+		ap_pwrseq_sub_states,
+		AP_PWRSEQ_EACH_SUB_STATE_STR_DEF_NODE_CHILD_DEFINE)
+};
+BUILD_ASSERT(ARRAY_SIZE(ap_pwrseq_state_str) == AP_POWER_STATE_COUNT);
+
+static struct ap_pwrseq_data ap_pwrseq_task_data;
+
+static void ap_pwrseq_add_state_callback(struct ap_pwrseq_cb_list *cb_list,
+					 sys_snode_t *node)
+{
+	if (!sys_slist_is_empty(&cb_list->list)) {
+		sys_slist_find_and_remove(&cb_list->list, node);
+	}
+
+	sys_slist_prepend(&cb_list->list, node);
+}
+
+static int
+ap_pwrseq_register_state_callback(struct ap_pwrseq_state_callback *state_cb,
+				  struct ap_pwrseq_cb_list *cb_list)
+{
+	if (!(state_cb->states_bit_mask & AP_PWRSEQ_STATES_MASK)) {
+		return -EINVAL;
+	}
+
+	__ASSERT(state_cb->cb, "Callback pointer should not be NULL");
+
+	k_spinlock_key_t key = k_spin_lock(&cb_list->lock);
+
+	ap_pwrseq_add_state_callback(cb_list, &state_cb->node);
+
+	cb_list->states |= AP_PWRSEQ_STATES_MASK & state_cb->states_bit_mask;
+	k_spin_unlock(&cb_list->lock, key);
+
+	return 0;
+}
+
+static void ap_pwrseq_send_callback(const struct device *dev,
+				    const enum ap_pwrseq_state entry,
+				    const enum ap_pwrseq_state exit,
+				    bool is_entry)
+{
+	struct ap_pwrseq_data *const data = dev->data;
+	struct ap_pwrseq_cb_list *cb_list = is_entry ? &data->entry_list :
+						       &data->exit_list;
+	const enum ap_pwrseq_state *state = is_entry ? &entry : &exit;
+	struct ap_pwrseq_state_callback *state_cb, *tmp;
+
+	if (!(cb_list->states & BIT(*state))) {
+		return;
+	}
+	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&cb_list->list, state_cb, tmp, node)
+	{
+		if (state_cb->states_bit_mask & BIT(*state)) {
+			state_cb->cb(dev, entry, exit);
+		}
+	}
+}
+
+static void ap_pwrseq_send_entry_callback(const struct device *dev,
+					  const enum ap_pwrseq_state entry,
+					  const enum ap_pwrseq_state exit)
+{
+	ap_pwrseq_send_callback(dev, entry, exit, true);
+}
+
+static void ap_pwrseq_send_exit_callback(const struct device *dev,
+					 const enum ap_pwrseq_state entry,
+					 const enum ap_pwrseq_state exit)
+{
+	ap_pwrseq_send_callback(dev, entry, exit, false);
+}
+
+static uint32_t ap_pwrseq_wait_event(const struct device *dev)
+{
+	struct ap_pwrseq_data *const data = dev->data;
+	uint32_t events;
+
+	events = k_event_wait(&data->evt, AP_PWRSEQ_EVENT_MASK, false,
+			      Z_FOREVER);
+	/* Clear all events posted */
+	k_event_clear(&data->evt, events);
+
+	return events & AP_PWRSEQ_EVENT_MASK;
+}
+
+static void ap_pwrseq_thread(void *arg, void *unused1, void *unused2)
+{
+	struct device *const dev = (struct device *)arg;
+	struct ap_pwrseq_data *const data = dev->data;
+	enum ap_pwrseq_state cur_state, new_state;
+	int run_status;
+	uint32_t events;
+
+	LOG_INF("Power Sequence thread start");
+	while (true) {
+		events = ap_pwrseq_wait_event(dev);
+		if (!events) {
+			continue;
+		}
+		LOG_DBG("Events posted: %0#x", events);
+
+		/**
+		 * Process generated events and keep looping while state
+		 * transitions are occurring.
+		 **/
+		while (true) {
+			ap_pwrseq_state_lock(dev);
+
+			cur_state = ap_pwrseq_sm_get_cur_state(data->sm_data);
+			run_status =
+				ap_pwrseq_sm_run_state(data->sm_data, events);
+			new_state = ap_pwrseq_sm_get_cur_state(data->sm_data);
+
+			ap_pwrseq_state_unlock(dev);
+			if (run_status) {
+				/* Was this terminated? */
+				return;
+			}
+
+			/* Check if state transition took place */
+			if (cur_state == new_state) {
+				break;
+			}
+			LOG_INF("%s -> %s", ap_pwrseq_get_state_str(cur_state),
+				ap_pwrseq_get_state_str(new_state));
+
+			ap_pwrseq_send_exit_callback(dev, new_state, cur_state);
+
+			ap_pwrseq_send_entry_callback(dev, new_state,
+						      cur_state);
+		}
+	}
+}
+
+static int ap_pwrseq_driver_init(const struct device *dev);
+
+DEVICE_DEFINE(ap_pwrseq_dev, "ap_pwrseq_drv", ap_pwrseq_driver_init, NULL,
+	      &ap_pwrseq_task_data, NULL, APPLICATION,
+	      CONFIG_APPLICATION_INIT_PRIORITY, NULL);
+
+K_THREAD_DEFINE(ap_pwrseq_tid, CONFIG_AP_PWRSEQ_STACK_SIZE, ap_pwrseq_thread,
+		DEVICE_GET(ap_pwrseq_dev), NULL, NULL,
+		CONFIG_AP_PWRSEQ_THREAD_PRIORITY, 0, K_TICKS_FOREVER);
+
+static int ap_pwrseq_driver_init(const struct device *dev)
+{
+	struct ap_pwrseq_data *const data = dev->data;
+
+	data->sm_data = ap_pwrseq_sm_get_instance();
+
+	k_mutex_init(&data->mux);
+	k_event_init(&data->evt);
+
+	return 0;
+}
+
+/**
+ *  Global functions definition.
+ **/
+const struct device *ap_pwrseq_get_instance(void)
+{
+	return DEVICE_GET(ap_pwrseq_dev);
+}
+
+int ap_pwrseq_start(const struct device *dev, enum ap_pwrseq_state init_state)
+{
+	struct ap_pwrseq_data *const data = dev->data;
+	int ret;
+
+	ap_pwrseq_state_lock(dev);
+	ret = ap_pwrseq_sm_init(data->sm_data, ap_pwrseq_tid, init_state);
+	ap_pwrseq_state_unlock(dev);
+	if (ret) {
+		return ret;
+	}
+
+	k_thread_start(ap_pwrseq_tid);
+
+	return 0;
+}
+
+void ap_pwrseq_post_event(const struct device *dev, enum ap_pwrseq_event event)
+{
+	struct ap_pwrseq_data *const data = dev->data;
+
+	if (event >= AP_PWRSEQ_EVENT_COUNT) {
+		return;
+	}
+
+	LOG_DBG("Posting Event: %0#lx", BIT(event));
+	k_event_post(&data->evt, BIT(event));
+}
+
+enum ap_pwrseq_state ap_pwrseq_get_current_state(const struct device *dev)
+{
+	struct ap_pwrseq_data *const data = dev->data;
+	enum ap_pwrseq_state ret_state;
+
+	ap_pwrseq_state_lock(dev);
+
+	ret_state = ap_pwrseq_sm_get_cur_state(data->sm_data);
+
+	ap_pwrseq_state_unlock(dev);
+
+	return ret_state;
+}
+
+const char *const ap_pwrseq_get_state_str(enum ap_pwrseq_state state)
+{
+	if (state >= AP_POWER_STATE_COUNT) {
+		return NULL;
+	}
+
+	return ap_pwrseq_state_str[state];
+}
+
+int ap_pwrseq_state_lock(const struct device *dev)
+{
+	struct ap_pwrseq_data *const data = dev->data;
+
+	/* Acquire lock to ensure no `run` operation is in progress. */
+	return k_mutex_lock(&data->mux, K_FOREVER);
+}
+
+int ap_pwrseq_state_unlock(const struct device *dev)
+{
+	struct ap_pwrseq_data *const data = dev->data;
+
+	return k_mutex_unlock(&data->mux);
+}
+
+int ap_pwrseq_register_state_entry_callback(
+	const struct device *dev, struct ap_pwrseq_state_callback *state_cb)
+{
+	struct ap_pwrseq_data *data = dev->data;
+
+	return ap_pwrseq_register_state_callback(state_cb, &data->entry_list);
+}
+
+int ap_pwrseq_register_state_exit_callback(
+	const struct device *dev, struct ap_pwrseq_state_callback *state_cb)
+{
+	struct ap_pwrseq_data *data = dev->data;
+
+	return ap_pwrseq_register_state_callback(state_cb, &data->exit_list);
+}
diff --git a/zephyr/subsys/ap_pwrseq/ap_pwrseq_drv_sm.h b/zephyr/subsys/ap_pwrseq/ap_pwrseq_drv_sm.h
new file mode 100644
index 0000000000..b2c71bf20d
--- /dev/null
+++ b/zephyr/subsys/ap_pwrseq/ap_pwrseq_drv_sm.h
@@ -0,0 +1,71 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _AP_PWRSEQ_INT_SM_H_
+#define _AP_PWRSEQ_INT_SM_H_
+#include "ap_power/ap_pwrseq.h"
+
+#include <zephyr/kernel/thread.h>
+
+/**
+ * This following AP Power Sequence state machine functions are only available
+ * for subsystem driver.
+ **/
+
+/**
+ * @brief Obtain AP power sequence state machine instance.
+ *
+ * @param None.
+ *
+ * @retval Return instance data of the state machine, only one instance is
+ * allowed per application.
+ **/
+void *ap_pwrseq_sm_get_instance(void);
+
+/**
+ * @brief Sets AP power sequence state machine initial state.
+ *
+ * @param data Pointer to AP power sequence state machine instance data.
+ *
+ * @param tid AP power sequence instance thread associated to this state
+ * machine. Functions `ap_pwrseq_sm_set_state` and `ap_pwrseq_sm_run_state` are
+ * meant to be executed only within this thread context.
+ *
+ * @param init_state State machine initial state.
+ *
+ * @retval SUCCESS Upon success, init_state ‘entry’ action handlers on all
+ * implemented levels will be invoked.
+ * @retval -EINVAL State provided is invalid.
+ * @retval -EPERM  State machine is already initialized.
+ **/
+int ap_pwrseq_sm_init(void *const data, k_tid_t tid,
+		      enum ap_pwrseq_state init_state);
+
+/**
+ * @brief Execute current state `run` action handlers.
+ *
+ * This function is meant to be executed only within AP power sequence driver
+ * thread context. `tid` was given in `ap_pwrseq_sm_init`.
+ *
+ * @param data Pointer to AP power sequence state machine instance data.
+ *
+ * @param events Events to be processed in current `run` iteration.
+ *
+ * @retval SUCCESS Upon success, provided `run` action handlers will be executed
+ * for all levels in current state.
+ * @retval -EINVAL State machine has not been initialized.
+ **/
+int ap_pwrseq_sm_run_state(void *const data, uint32_t events);
+
+/**
+ * @brief Get current state enumeration value.
+ *
+ * @param data Pointer to AP power sequence state machine instance data.
+ *
+ * @retval Enum value Upon success.
+ * @retval AP_POWER_STATE_UNDEF If state machine has not been initialized.
+ **/
+enum ap_pwrseq_state ap_pwrseq_sm_get_cur_state(void *const data);
+#endif /* _AP_PWRSEQ_INT_SM_H_ */
diff --git a/zephyr/subsys/ap_pwrseq/ap_pwrseq_sm.c b/zephyr/subsys/ap_pwrseq/ap_pwrseq_sm.c
new file mode 100644
index 0000000000..538aae8bc7
--- /dev/null
+++ b/zephyr/subsys/ap_pwrseq/ap_pwrseq_sm.c
@@ -0,0 +1,262 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ap_power/ap_pwrseq_sm.h"
+
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(ap_pwrseq, CONFIG_AP_PWRSEQ_LOG_LEVEL);
+
+struct ap_pwrseq_sm_data {
+	/* Zephyr SMF context */
+	struct smf_ctx smf;
+	/* Pointer to array of states structures */
+	const struct ap_pwrseq_smf **states;
+	/* Bitfiled of events */
+	uint32_t events;
+	/* Id of current thread executing state machine */
+	k_tid_t tid;
+	/* State entering during state transition */
+	enum ap_pwrseq_state entry;
+	/* State exiting during state transition */
+	enum ap_pwrseq_state exit;
+	/* Flag to inform if current `run` action has been handled */
+	bool run_handled;
+	/* Flag to inform if current `entry` action has been handled */
+	bool entry_handled;
+	/* Flag to inform if current `exit` action has been handled */
+	bool exit_handled;
+	/* Flag to inform that state transition is in progress */
+	bool in_transition;
+};
+
+/**
+ * Declare weak `struct smf_state` definitions of all ACPI states for
+ * architecture and chipset level. These are used as placeholder to keep AP
+ * power sequence state machine hierarchy in case corresponding state action
+ * handlers are not provided by implementation.
+ **/
+#define AP_POWER_ARCH_STATE_WEAK_DEFINE(name)                 \
+	const struct smf_state __weak arch_##name##_actions = \
+		SMF_CREATE_STATE(NULL, NULL, NULL, NULL);
+
+#define AP_POWER_CHIPSET_STATE_WEAK_DEFINE(name)                 \
+	const struct smf_state __weak chipset_##name##_actions = \
+		SMF_CREATE_STATE(NULL, NULL, NULL, &arch_##name##_actions);
+
+/**
+ * Declare weak `struct ap_pwrseq_smf` definitions of all ACPI states for
+ * application level. These are used as placeholder to keep AP
+ * power sequence state machine hierarchy in case corresponding state action
+ * handlers are not provided by implementation.
+ **/
+#define AP_POWER_APP_STATE_WEAK_DEFINE(name)                            \
+	const struct ap_pwrseq_smf __weak app_state_##name = {          \
+		.actions = SMF_CREATE_STATE(NULL, NULL, NULL,           \
+					    &chipset_##name##_actions), \
+		.state = name                                           \
+	};
+
+#define AP_POWER_STATE_WEAK_DEFINE(name)         \
+	AP_POWER_ARCH_STATE_WEAK_DEFINE(name)    \
+	AP_POWER_CHIPSET_STATE_WEAK_DEFINE(name) \
+	AP_POWER_APP_STATE_WEAK_DEFINE(name)
+
+AP_POWER_STATE_WEAK_DEFINE(AP_POWER_STATE_G3)
+AP_POWER_STATE_WEAK_DEFINE(AP_POWER_STATE_S5)
+AP_POWER_STATE_WEAK_DEFINE(AP_POWER_STATE_S4)
+AP_POWER_STATE_WEAK_DEFINE(AP_POWER_STATE_S3)
+AP_POWER_STATE_WEAK_DEFINE(AP_POWER_STATE_S2)
+AP_POWER_STATE_WEAK_DEFINE(AP_POWER_STATE_S1)
+AP_POWER_STATE_WEAK_DEFINE(AP_POWER_STATE_S0)
+
+#define AP_PWRSEQ_STATE_DEFINE(name) [name] = &app_state_##name
+
+/* Sub States defines */
+#define AP_PWRSEQ_APP_SUB_STATE_DEFINE(state) [state] = &app_state_##state,
+
+#define AP_PWRSEQ_APP_SUB_STATE_DEFINE_(state) \
+	AP_PWRSEQ_APP_SUB_STATE_DEFINE(state)
+
+#define AP_PWRSEQ_EACH_APP_SUB_STATE_NODE_DEFINE__(node_id, prop, idx) \
+	AP_PWRSEQ_APP_SUB_STATE_DEFINE_(                               \
+		DT_CAT6(node_id, _P_, prop, _IDX_, idx, _STRING_UPPER_TOKEN))
+
+#define AP_PWRSEQ_EACH_CHIPSET_SUB_STATE_NODE_DEFINE(state) \
+	[state] = &chipset_##state##_actions,
+
+#define AP_PWRSEQ_EACH_CHIPSET_SUB_STATE_NODE_DEFINE_(state) \
+	AP_PWRSEQ_EACH_CHIPSET_SUB_STATE_NODE_DEFINE(state)
+
+#define AP_PWRSEQ_EACH_CHIPSET_SUB_STATE_NODE_DEFINE__(node_id, prop, idx) \
+	AP_PWRSEQ_EACH_CHIPSET_SUB_STATE_NODE_DEFINE_(                     \
+		DT_CAT6(node_id, _P_, prop, _IDX_, idx, _STRING_UPPER_TOKEN))
+
+#define AP_PWRSEQ_EACH_SUB_STATE_NODE_CHILD_DEFINE(node_id)                   \
+	COND_CODE_1(                                                          \
+		DT_NODE_HAS_PROP(node_id, chipset),                           \
+		(DT_FOREACH_PROP_ELEM(                                        \
+			node_id, chipset,                                     \
+			AP_PWRSEQ_EACH_CHIPSET_SUB_STATE_NODE_DEFINE__)),     \
+		(COND_CODE_1(                                                 \
+			DT_NODE_HAS_PROP(node_id, application),               \
+			(DT_FOREACH_PROP_ELEM(                                \
+				node_id, application,                         \
+				AP_PWRSEQ_EACH_APP_SUB_STATE_NODE_DEFINE__)), \
+			())))
+
+/**
+ * @brief Array containing power state action handlers for all state and
+ * and substates available for AP power sequence state machine, these items
+ * correspond to `enum ap_pwrseq_state`.
+ **/
+static const struct ap_pwrseq_smf *ap_pwrseq_states[AP_POWER_STATE_COUNT] = {
+	AP_PWRSEQ_STATE_DEFINE(AP_POWER_STATE_G3),
+	AP_PWRSEQ_STATE_DEFINE(AP_POWER_STATE_S5),
+	AP_PWRSEQ_STATE_DEFINE(AP_POWER_STATE_S4),
+	AP_PWRSEQ_STATE_DEFINE(AP_POWER_STATE_S3),
+	AP_PWRSEQ_STATE_DEFINE(AP_POWER_STATE_S2),
+	AP_PWRSEQ_STATE_DEFINE(AP_POWER_STATE_S1),
+	AP_PWRSEQ_STATE_DEFINE(AP_POWER_STATE_S0),
+	DT_FOREACH_STATUS_OKAY(ap_pwrseq_sub_states,
+			       AP_PWRSEQ_EACH_SUB_STATE_NODE_CHILD_DEFINE)
+};
+
+static struct ap_pwrseq_sm_data sm_data_0 = {
+	.states = ap_pwrseq_states,
+};
+
+/* Private functions available only for AP Power Sequence subsystem driver. */
+void *ap_pwrseq_sm_get_instance(void)
+{
+	return &sm_data_0;
+}
+
+int ap_pwrseq_sm_init(void *const data, k_tid_t tid,
+		      enum ap_pwrseq_state init_state)
+{
+	struct ap_pwrseq_sm_data *sm_data = data;
+
+	if (sm_data->smf.current || sm_data->tid) {
+		return -EPERM;
+	}
+
+	if (init_state >= AP_POWER_STATE_COUNT) {
+		return -EINVAL;
+	}
+
+	sm_data->entry = sm_data->exit = AP_POWER_STATE_UNDEF;
+	smf_set_initial(&sm_data->smf,
+			(const struct smf_state *)sm_data->states[init_state]);
+	sm_data->tid = tid;
+
+	return 0;
+}
+
+int ap_pwrseq_sm_run_state(void *const data, uint32_t events)
+{
+	struct ap_pwrseq_sm_data *sm_data = data;
+	int ret;
+
+	if (sm_data->tid != k_current_get()) {
+		/* Called by wrong thread */
+		return -EPERM;
+	}
+
+	if (sm_data->smf.current == NULL) {
+		return -EINVAL;
+	}
+
+	sm_data->in_transition = false;
+	sm_data->entry = sm_data->exit = AP_POWER_STATE_UNDEF;
+	sm_data->run_handled = false;
+	sm_data->events = events;
+
+	ret = smf_run_state((struct smf_ctx *const)sm_data);
+
+	return ret;
+}
+
+enum ap_pwrseq_state ap_pwrseq_sm_get_cur_state(void *const data)
+{
+	struct ap_pwrseq_sm_data *sm_data = data;
+
+	if (!sm_data->smf.current) {
+		return AP_POWER_STATE_UNDEF;
+	}
+
+	return ((struct ap_pwrseq_smf *)sm_data->smf.current)->state;
+}
+
+/* Public functions for action handlers implementation. */
+int ap_pwrseq_sm_set_state(void *const data, enum ap_pwrseq_state state)
+{
+	struct ap_pwrseq_sm_data *sm_data = data;
+
+	if (sm_data->tid != k_current_get()) {
+		/* Called by wrong thread */
+		return -EPERM;
+	}
+
+	if (state >= AP_POWER_STATE_COUNT ||
+	    /* Only one state transition is permited within `run` iterations */
+	    sm_data->in_transition) {
+		return -EINVAL;
+	}
+
+	/* Transition has started, update corresponding flags */
+	sm_data->in_transition = true;
+	sm_data->entry_handled = sm_data->exit_handled = false;
+	sm_data->entry = state;
+	sm_data->exit = ((struct ap_pwrseq_smf *)sm_data->smf.current)->state;
+	smf_set_state((struct smf_ctx *const)&sm_data->smf,
+		      (const struct smf_state *)sm_data->states[state]);
+
+	return 0;
+}
+
+bool ap_pwrseq_sm_is_event_set(void *const data, enum ap_pwrseq_event event)
+{
+	struct ap_pwrseq_sm_data *sm_data = data;
+
+	return ((sm_data->events & BIT(event)) == BIT(event));
+}
+
+enum ap_pwrseq_state ap_pwrseq_sm_get_entry_state(void *const data)
+{
+	struct ap_pwrseq_sm_data *sm_data = data;
+
+	if (sm_data->tid != k_current_get()) {
+		/* Called by wrong thread */
+		return -EPERM;
+	}
+
+	return sm_data->entry;
+}
+
+enum ap_pwrseq_state ap_pwrseq_sm_get_exit_state(void *const data)
+{
+	struct ap_pwrseq_sm_data *sm_data = data;
+
+	if (sm_data->tid != k_current_get()) {
+		/* Called by wrong thread */
+		return -EPERM;
+	}
+
+	return sm_data->exit;
+}
+
+#define AP_POWER_SM_HANDLER_DEF(action)                                \
+	void ap_pwrseq_sm_exec_##action##_handler(                     \
+		void *const data, ap_pwr_state_action_handler handler) \
+	{                                                              \
+		struct ap_pwrseq_sm_data *sm_data = data;              \
+		if (handler && !sm_data->action##_handled)             \
+			sm_data->action##_handled = !!handler(data);   \
+	}
+
+AP_POWER_SM_HANDLER_DEF(entry)
+AP_POWER_SM_HANDLER_DEF(run)
+AP_POWER_SM_HANDLER_DEF(exit)
diff --git a/zephyr/subsys/ap_pwrseq/include/ap_power_host_sleep.h b/zephyr/subsys/ap_pwrseq/include/ap_power_host_sleep.h
new file mode 100644
index 0000000000..e615f634b8
--- /dev/null
+++ b/zephyr/subsys/ap_pwrseq/include/ap_power_host_sleep.h
@@ -0,0 +1,80 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __AP_POWER_HOST_SLEEP_H
+#define __AP_POWER_HOST_SLEEP_H
+
+#include <ap_power/ap_power_interface.h>
+#include <power_host_sleep.h>
+
+#ifdef CONFIG_AP_PWRSEQ_DRIVER
+#include "ap_power/ap_pwrseq.h"
+#endif
+
+/*
+ * Deferred call to set active mask according to current power state
+ */
+void ap_power_set_active_wake_mask(void);
+
+/*
+ * Get lazy wake masks for the sleep state provided
+ *
+ * @param state Power state
+ * @param mask  Lazy wake mask.
+ *
+ * @return 0 for success; -EINVAL if power state is not S3/S5/S0ix
+ */
+#ifndef CONFIG_AP_PWRSEQ_DRIVER
+int ap_power_get_lazy_wake_mask(enum power_states_ndsx state,
+				host_event_t *mask);
+#else
+int ap_power_get_lazy_wake_mask(enum ap_pwrseq_state state, host_event_t *mask);
+#endif
+
+#if CONFIG_AP_PWRSEQ_S0IX
+/* For S0ix path, flag to notify sleep change */
+enum ap_power_sleep_type {
+	AP_POWER_SLEEP_NONE,
+	AP_POWER_SLEEP_SUSPEND,
+	AP_POWER_SLEEP_RESUME,
+};
+
+/*
+ * Reset host sleep state and clean up
+ */
+void ap_power_reset_host_sleep_state(void);
+
+/*
+ * Get current sleep type notified.
+ *
+ * @return enum ap_power_sleep_type
+ */
+enum ap_power_sleep_type ap_power_sleep_get_notify(void);
+
+/*
+ * Check if the sleep type current power transition indicates is the same
+ * as what is notified. If same, means host sleep event notified by AP
+ * through Host Command and SLP_S0 are consistent. Process
+ * the transition. Otherwise, no action.
+ *
+ * @param check_state Sleep type which is going to transit to.
+ */
+void ap_power_sleep_notify_transition(enum ap_power_sleep_type check_state);
+#endif /* CONFIG_AP_PWRSEQ_S0IX */
+
+/*
+ * Get sleep timeout from host command context
+ */
+uint16_t host_get_sleep_timeout(void);
+
+/*
+ * Set sleep transitions for host command response
+ *
+ * @param val sleep transitions
+ *
+ */
+void host_set_sleep_transitions(uint32_t val);
+
+#endif /* __AP_PWRSEQ_HOST_SLEEP_H */
diff --git a/zephyr/subsys/ap_pwrseq/include/ap_power_override_functions.h b/zephyr/subsys/ap_pwrseq/include/ap_power_override_functions.h
new file mode 100644
index 0000000000..bfaeb49477
--- /dev/null
+++ b/zephyr/subsys/ap_pwrseq/include/ap_power_override_functions.h
@@ -0,0 +1,94 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ * @brief Declare functions that are supplied externally.
+ * The functions are all prepended with board_ap_power_ to indicate
+ * they have external implementations.
+ *
+ * TODO(b/223923728): Longer term, a framework should be put in place to
+ * allow extensibility for selected functions.
+ *
+ * The external functions may need to access
+ * devicetree properties for values such
+ * as timeouts etc.
+ */
+
+#ifndef __AP_PWRSEQ_AP_POWER_BOARD_FUNCTIONS_H__
+#define __AP_PWRSEQ_AP_POWER_BOARD_FUNCTIONS_H__
+
+#include <zephyr/devicetree.h>
+
+/**
+ * @brief Evaluate whether system state is OK to start the AP.
+ *
+ * This is most often used to block startup when there is insufficient power
+ * available to reliably run the AP, such as if an attached battery's state of
+ * charge is very low.
+ *
+ * @return true if the system may proceed out of hard-off.
+ */
+bool board_ap_power_is_startup_ok(void);
+
+/**
+ * @brief Force AP shutdown
+ *
+ * Immediately shut down the AP.
+ */
+void board_ap_power_force_shutdown(void);
+
+#ifndef CONFIG_AP_PWRSEQ_DRIVER
+/**
+ * @brief Called to transition from G3 to S5
+ *
+ * Action to start transition from G3 to S5.
+ * Usually involves enabling the main power rails.
+ */
+void board_ap_power_action_g3_s5(void);
+
+/**
+ * @brief Called to transition from S3 to S0
+ *
+ * Action to start transition from S3 to S0.
+ */
+void board_ap_power_action_s3_s0(void);
+
+/* @brief Called to transition from S0 to S3
+ *
+ * Action to start transition from S0 to S3.
+ */
+void board_ap_power_action_s0_s3(void);
+
+/* @brief Called on S0 state
+ *
+ * Action to handle S0 state.
+ */
+void board_ap_power_action_s0(void);
+
+/**
+ * @brief Assert PCH power OK signal to AP
+ *
+ * @return 0 Success
+ * @return -1 Timeout or error
+ */
+int board_ap_power_assert_pch_power_ok(void);
+
+/**
+ * @brief Check board power rails enabled or not
+ *
+ * @return true Enabled
+ * @return false Not enabled
+ */
+bool board_ap_power_check_power_rails_enabled(void);
+#endif /* CONFIG_AP_PWRSEQ_DRIVER */
+
+/**
+ * @brief macro to access configuration properties from DTS
+ */
+#define AP_PWRSEQ_DT_VALUE(p) \
+	DT_PROP(DT_COMPAT_GET_ANY_STATUS_OKAY(intel_ap_pwrseq), p)
+
+#endif /* __AP_PWRSEQ_AP_POWER_BOARD_FUNCTIONS_H__ */
diff --git a/zephyr/subsys/ap_pwrseq/include/power_signals.h b/zephyr/subsys/ap_pwrseq/include/power_signals.h
new file mode 100644
index 0000000000..130285a8ee
--- /dev/null
+++ b/zephyr/subsys/ap_pwrseq/include/power_signals.h
@@ -0,0 +1,319 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ * @brief Definition of the power signals API.
+ *
+ * Defines the API for accessing the power signals.
+ *
+ * The AP power sequence code uses power signals to monitor and control
+ * the startup and shutdown of the AP. These power signals may be
+ * accessed from a variety of sources, such as GPIOs, eSPI virtual
+ * wires, and board specific sources. Regardless of the source
+ * of the signal or control, a single API is used to access these signals.
+ * The configuration of the source of the signals is done via
+ * devicetree, using a number of different compatibles each
+ * representing a different source of the signals.
+ *
+ * The power sequence code identifies the signals via a common enum,
+ * which is generated from a common set of enum names in devicetree.
+ *
+ * The API defined here also functions to deal with the signals
+ * as a set i.e being able to watch for a certain set of signals
+ * to become asserted.
+ *
+ * Intermediate layers provide a way of mapping these signals
+ * to the underlying source; the intent is that these signals
+ * provide a logical state for the signal, regardless of whatever
+ * polarity the physical pin is defined as i.e an input signal may be
+ * considered asserted if the voltage is low, but this is a platform
+ * specific attribute, and should be configured at the h/w layer e.g
+ * a GPIO that is asserted when low should be configured using the
+ * GPIO_ACTIVE_LOW flag, so that the logical asserted signal is
+ * read as '1', not '0'.
+ */
+
+#ifndef __AP_PWRSEQ_POWER_SIGNALS_H__
+#define __AP_PWRSEQ_POWER_SIGNALS_H__
+
+#include <zephyr/devicetree.h>
+
+/**
+ * @brief Definitions for AP power sequence signals.
+ *
+ * Defines the enums for the AP power sequence signals.
+ */
+
+/**
+ * @brief Generate the enum for this power signal.
+ */
+#define PWR_SIGNAL_ENUM(id) DT_STRING_UPPER_TOKEN(id, enum_name)
+
+#define PWR_DT_INST_SIGNAL_ENUM(inst) \
+	DT_INST_STRING_UPPER_TOKEN(inst, enum_name)
+
+#define PWR_SIGNAL_ENUM_COMMA(id) PWR_SIGNAL_ENUM(id),
+
+/**
+ * @brief Enum of all power signals.
+ *
+ * Defines the enums of all the power signals configured
+ * in the system. Uses the 'enum-name' property to name
+ * the signal.
+ *
+ * The order that these compatibles are processed in
+ * must be the same as in power_signals.c
+ */
+/* clang-format off */
+enum power_signal {
+	DT_FOREACH_STATUS_OKAY(intel_ap_pwrseq_gpio, PWR_SIGNAL_ENUM_COMMA)
+	DT_FOREACH_STATUS_OKAY(intel_ap_pwrseq_vw, PWR_SIGNAL_ENUM_COMMA)
+	DT_FOREACH_STATUS_OKAY(intel_ap_pwrseq_external, PWR_SIGNAL_ENUM_COMMA)
+	DT_FOREACH_STATUS_OKAY(intel_ap_pwrseq_adc, PWR_SIGNAL_ENUM_COMMA)
+	POWER_SIGNAL_COUNT,
+};
+/* clang-format on */
+
+#undef PWR_SIGNAL_ENUM_COMMA
+
+#if CONFIG_AP_PWRSEQ_SIGNAL_EXTERNAL
+/**
+ * Definitions required for external (board-specific)
+ * power signals.
+ *
+ * int board_power_signal_get(enum power_signal signal)
+ * {
+ *     int value;
+ *
+ *     switch(signal) {
+ *     default:
+ *         LOG(LOG_ERR, "Unknown power signal!");
+ *         return -1;
+ *
+ *     case PWR_VCCST_PWRGD:
+ *         value = ...
+ *         return value;
+ *     }
+ * }
+ *
+ */
+
+/**
+ * @brief Board specific function to get power signal.
+ *
+ * Function to get power signals that are board specific
+ * values. Only required when 'intel_ap_pwrseq_external'
+ * compatible nodes are defined in devicetree, indicating that
+ * the particular signal is to be sourced via this board
+ * level function.
+ *
+ * @param signal Power signal value to return
+ * @return 0 or 1 Power signal value
+ * @return negative Error
+ */
+int board_power_signal_get(enum power_signal signal);
+
+/**
+ * @brief Board specific function to set power signal.
+ *
+ * @param signal Power signal value to set
+ * @param value Value to set signal to.
+ * @return 0 Success
+ * @return negative Error
+ */
+int board_power_signal_set(enum power_signal signal, int value);
+
+#endif /* CONFIG_AP_PWRSEQ_SIGNAL_EXTERNAL */
+
+/**
+ * @brief Get the value of this power signal.
+ *
+ * Retrieve the value of this power signal.
+ *
+ * @param signal The power_signal to get.
+ * @return 0 or 1 Value of signal
+ * @return negative If error occurred
+ */
+int power_signal_get(enum power_signal signal);
+
+/**
+ * @brief Set the output of this power signal.
+ *
+ * Only some signals allow the output to be set.
+ *
+ * @param signal The power_signal to set.
+ * @param value The output value to set it to.
+ * @return 0 is successful
+ * @return negative If output cannot be set.
+ */
+int power_signal_set(enum power_signal signal, int value);
+
+/**
+ * @brief Enable this power signal
+ *
+ * Enable this signal to be used as a power_signal.
+ * Typically this means the interrupt associated with this
+ * signal is enabled.
+ *
+ * Power signals are enabled by default at startup, and if
+ * a power signal is disabled via power_signal_disable(), it will
+ * need to be re-enabled before the signal is included in the
+ * input handling again.
+ *
+ * @param signal The power_signal to enable.
+ * @return 0 is successful
+ * @return negative If unsuccessful
+ */
+int power_signal_enable(enum power_signal signal);
+
+/**
+ * @brief Disable this power signal
+ *
+ * Disable the signal so that it does not update the
+ * input handling (i.e does not call power_signal_interrupt() etc.)
+ * Once disabled, a signal must be re-enabled using
+ * power_signal_enable() to allow the signal to be used again.
+ *
+ * @param signal The power_signal to disable.
+ * @return 0 is successful
+ * @return negative If unsuccessful
+ */
+int power_signal_disable(enum power_signal signal);
+
+/**
+ * @brief Get the debug name associated with this signal.
+ *
+ * @param signal The power_signal value to get.
+ * @return string The name of the signal.
+ */
+const char *power_signal_name(enum power_signal signal);
+
+/**
+ * @brief Initialize the power signal interface.
+ *
+ * Called when the power sequence code is ready to start
+ * processing inputs and outputs.
+ */
+void power_signal_init(void);
+
+/**
+ * @brief Power signal interrupt handler
+ *
+ * Called when an input signal has changed.
+ * May be called from interrupt context.
+ *
+ * @param signal The power_signal that has changed.
+ * @param value The new value of the signal
+ */
+void power_signal_interrupt(enum power_signal signal, int value);
+
+/**
+ * Interrupt based signals update a bitfield mask, which can be
+ * used to wait for signal changes.
+ */
+typedef uint32_t power_signal_mask_t;
+
+/**
+ * @brief Get the current interrupt bitfield
+ *
+ * @return Interrupt power signals as a mask.
+ */
+power_signal_mask_t power_get_signals(void);
+
+/**
+ * @brief Set the signal debug mask
+ *
+ * Sets a debug mask of signals.
+ * A log is generated whenever any of these signals change.
+ *
+ * @param debug Mask of signals to be flagged for logging
+ */
+void power_set_debug(power_signal_mask_t debug);
+
+/**
+ * @brief Get the signal debug mask
+ *
+ * Gets the current debug mask of signals.
+ *
+ * @return Current mask of signals to be flagged for logging
+ */
+power_signal_mask_t power_get_debug(void);
+
+/**
+ * @brief Check if the desired signals match.
+ *
+ * Masks off the signals using the mask and
+ * compare against the wanted signals.
+ *
+ * @param mask Mask of signals to be checked
+ * @param wait Matching value.
+ * @return True if all the masked signals match the wanted signals
+ */
+static inline bool power_signals_match(power_signal_mask_t mask,
+				       power_signal_mask_t want)
+{
+	return (power_get_signals() & mask) == (want & mask);
+}
+
+/**
+ * @brief Check if all the desired signals are asserted.
+ *
+ * @param want Mask of signals to be checked
+ * @return True if all the wanted signals are asserted.
+ */
+static inline bool power_signals_on(power_signal_mask_t want)
+{
+	return power_signals_match(want, want);
+}
+
+/**
+ * @brief Check if the desired signals are deasserted.
+ *
+ * @param want Mask of signals to be checked
+ * @return True if all the wanted signals are deasserted.
+ */
+static inline bool power_signals_off(power_signal_mask_t want)
+{
+	return power_signals_match(want, 0);
+}
+
+/**
+ * @brief Wait until the selected power signals match
+ *
+ * Given a signal mask and wanted value, wait until the
+ * selected power signals match the wanted value.
+ *
+ * @param want The value of the signals to wait for.
+ * @param mask The mask of the selected signals
+ * @param timeout The amount of time to wait in ms.
+ * @return 0 if the signals matched.
+ * @return negative If the signals did not match before the timeout.
+ */
+int power_wait_mask_signals_timeout(power_signal_mask_t want,
+				    power_signal_mask_t mask, int timeout);
+
+/**
+ * @brief Wait until the selected power signals match, with timeout
+ *
+ * Given a set of signals, wait until all of
+ * the signals are asserted.
+ *
+ * @param want The value of the signals to wait for.
+ * @param timeout The amount of time to wait in ms.
+ * @return 0 if the signals matched.
+ */
+static inline int power_wait_signals_timeout(power_signal_mask_t want,
+					     int timeout)
+{
+	return power_wait_mask_signals_timeout(want, want, timeout);
+}
+
+/**
+ * @brief Create a mask from a power signal.
+ */
+#define POWER_SIGNAL_MASK(signal) (1 << (signal))
+
+#endif /* __AP_PWRSEQ_POWER_SIGNALS_H__ */
diff --git a/zephyr/subsys/ap_pwrseq/include/signal_adc.h b/zephyr/subsys/ap_pwrseq/include/signal_adc.h
new file mode 100644
index 0000000000..9e9a30ac69
--- /dev/null
+++ b/zephyr/subsys/ap_pwrseq/include/signal_adc.h
@@ -0,0 +1,74 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __AP_PWRSEQ_SIGNAL_ADC_H__
+#define __AP_PWRSEQ_SIGNAL_ADC_H__
+
+#include <zephyr/devicetree.h>
+
+#include <power_signals.h>
+
+#define PWR_SIG_TAG_ADC PWR_ADC_
+
+/*
+ * Generate enums for the analogue converters.
+ * These enums are only used internally
+ * to assign an index to each signal that is specific
+ * to the source.
+ */
+
+#define TAG_ADC(tag, name) DT_CAT(tag, name)
+
+#define PWR_ADC_ENUM(id) TAG_ADC(PWR_SIG_TAG_ADC, PWR_SIGNAL_ENUM(id)),
+
+enum pwr_sig_adc {
+	DT_FOREACH_STATUS_OKAY(intel_ap_pwrseq_adc, PWR_ADC_ENUM)
+		PWR_SIG_ADC_COUNT
+};
+
+#undef PWR_ADC_ENUM
+#undef TAG_ADC
+
+/**
+ * @brief Get the value of the ADC power signal.
+ *
+ * The analogue-to-digital converter is used to read an analogue
+ * value and to convert that via a threshold to a 0/1 signal.
+ *
+ * @param adc The enum of the value to get.
+ * @return the current value of the power signal.
+ */
+int power_signal_adc_get(enum pwr_sig_adc adc);
+
+/**
+ * @brief Enable the ADC signal.
+ *
+ * This will not only enable the interrupt driven update
+ * of this signal, but will also enable the ADC itself.
+ *
+ * @param signal The pwr_sig_adc to enable.
+ * @return 0 if successful
+ * @return -error if failed
+ */
+int power_signal_adc_enable(enum pwr_sig_adc adc);
+
+/**
+ * @brief Disable the ADC signal.
+ *
+ * This will disable the interrupt updating of this signal, and will
+ * also disable the ADC from running.
+ *
+ * @param signal The pwr_sig_adc to disable.
+ * @return 0 if successful
+ * @return -error if failed
+ */
+int power_signal_adc_disable(enum pwr_sig_adc adc);
+
+/**
+ * @brief Initialize the ADCs for the power signals.
+ */
+void power_signal_adc_init(void);
+
+#endif /* __AP_PWRSEQ_SIGNAL_ADC_H__ */
diff --git a/zephyr/subsys/ap_pwrseq/include/signal_gpio.h b/zephyr/subsys/ap_pwrseq/include/signal_gpio.h
new file mode 100644
index 0000000000..9a201fc742
--- /dev/null
+++ b/zephyr/subsys/ap_pwrseq/include/signal_gpio.h
@@ -0,0 +1,77 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __AP_PWRSEQ_SIGNAL_GPIO_H__
+#define __AP_PWRSEQ_SIGNAL_GPIO_H__
+
+#include <zephyr/devicetree.h>
+
+#include <power_signals.h>
+
+#define PWR_SIG_TAG_GPIO PWR_GPIO_
+
+/*
+ * Generate enums for the GPIOs.
+ * These enums are only used internally
+ * to assign an index to each signal that is specific
+ * to the source.
+ */
+
+#define TAG_GPIO(tag, name) DT_CAT(tag, name)
+
+#define PWR_GPIO_ENUM(id) TAG_GPIO(PWR_SIG_TAG_GPIO, PWR_SIGNAL_ENUM(id)),
+
+/* clang-format off */
+enum pwr_sig_gpio {
+	DT_FOREACH_STATUS_OKAY(intel_ap_pwrseq_gpio, PWR_GPIO_ENUM)
+	PWR_SIG_GPIO_COUNT
+};
+/* clang-format on */
+
+#undef PWR_GPIO_ENUM
+#undef TAG_GPIO
+
+/**
+ * @brief Get the value of the GPIO power signal.
+ *
+ * @param signal The power_signal_gpios value to get.
+ * @return the current value of the power signal.
+ */
+int power_signal_gpio_get(enum pwr_sig_gpio gpio);
+
+/**
+ * @brief Set the output of this GPIO power signal.
+ *
+ * @param signal The GPIO to set.
+ * @param value The output value to set it to.
+ * @return 0 is successful
+ * @return negative If output cannot be set.
+ */
+int power_signal_gpio_set(enum pwr_sig_gpio gpio, int value);
+
+/**
+ * @brief Enable the GPIO interrupt
+ *
+ * @param signal The power_signal_gpios to enable.
+ * @return 0 if successful
+ * @return -error if failed
+ */
+int power_signal_gpio_enable(enum pwr_sig_gpio gpio);
+
+/**
+ * @brief Disable the GPIO interrupt
+ *
+ * @param signal The power_signal_gpios to disable.
+ * @return 0 if successful
+ * @return -error if failed
+ */
+int power_signal_gpio_disable(enum pwr_sig_gpio gpio);
+
+/**
+ * @brief Initialize the GPIOs for the power signals.
+ */
+void power_signal_gpio_init(void);
+
+#endif /* __AP_PWRSEQ_SIGNAL_GPIO_H__ */
diff --git a/zephyr/subsys/ap_pwrseq/include/signal_vw.h b/zephyr/subsys/ap_pwrseq/include/signal_vw.h
new file mode 100644
index 0000000000..e4c29521d3
--- /dev/null
+++ b/zephyr/subsys/ap_pwrseq/include/signal_vw.h
@@ -0,0 +1,49 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __AP_PWRSEQ_SIGNAL_VW_H__
+#define __AP_PWRSEQ_SIGNAL_VW_H__
+
+#include <zephyr/devicetree.h>
+
+#include <power_signals.h>
+
+#define PWR_SIG_TAG_VW PWR_VW_
+
+/*
+ * Generate enums for the virtual wire signals.
+ * These enums are only used internally
+ * to assign an index to each signal that is specific
+ * to the source.
+ */
+
+#define TAG_VW(tag, name) DT_CAT(tag, name)
+
+#define PWR_VW_ENUM(id) TAG_VW(PWR_SIG_TAG_VW, PWR_SIGNAL_ENUM(id)),
+
+enum pwr_sig_vw {
+	DT_FOREACH_STATUS_OKAY(intel_ap_pwrseq_vw, PWR_VW_ENUM) PWR_SIG_VW_COUNT
+};
+
+#undef PWR_VW_ENUM
+#undef TAG_VW
+
+/**
+ * @brief Get the value of the virtual wire signal.
+ *
+ * @param index The VW signal index to get.
+ * @return the current value of the virtual wire.
+ */
+int power_signal_vw_get(enum pwr_sig_vw vw);
+
+/**
+ * @brief Initialize the power signal interface.
+ *
+ * Called when the power sequence code is ready to start
+ * processing inputs and outputs.
+ */
+void power_signal_vw_init(void);
+
+#endif /* __AP_PWRSEQ_SIGNAL_VW_H__ */
diff --git a/zephyr/subsys/ap_pwrseq/include/x86_common_pwrseq.h b/zephyr/subsys/ap_pwrseq/include/x86_common_pwrseq.h
new file mode 100644
index 0000000000..b36b7f7714
--- /dev/null
+++ b/zephyr/subsys/ap_pwrseq/include/x86_common_pwrseq.h
@@ -0,0 +1,24 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __X86_COMMON_PWRSEQ_H__
+#define __X86_COMMON_PWRSEQ_H__
+
+#include <zephyr/logging/log.h>
+
+#include <ap_power/ap_power_interface.h>
+#include <ap_power_override_functions.h>
+#include <power_signals.h>
+#include <x86_power_signals.h>
+
+#ifndef CONFIG_AP_PWRSEQ_DRIVER
+/* This encapsulates the attributes of the state machine */
+struct pwrseq_context {
+	/* On power-on start boot up sequence */
+	enum power_states_ndsx power_state;
+};
+#endif
+
+#endif /* __X86_COMMON_PWRSEQ_H__ */
diff --git a/zephyr/subsys/ap_pwrseq/include/x86_non_dsx_common_pwrseq_sm_handler.h b/zephyr/subsys/ap_pwrseq/include/x86_non_dsx_common_pwrseq_sm_handler.h
new file mode 100644
index 0000000000..2f9b01fbee
--- /dev/null
+++ b/zephyr/subsys/ap_pwrseq/include/x86_non_dsx_common_pwrseq_sm_handler.h
@@ -0,0 +1,39 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __X86_NON_DSX_COMMON_PWRSEQ_SM_HANDLER_H__
+#define __X86_NON_DSX_COMMON_PWRSEQ_SM_HANDLER_H__
+
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/types.h>
+
+#ifdef CONFIG_AP_PWRSEQ_DRIVE
+#include <ap_power/ap_pwrseq.h>
+#else
+#include <ap_power/ap_power.h>
+#include <ap_power/ap_power_events.h>
+#endif
+#include <ap_power_host_sleep.h>
+#include <x86_common_pwrseq.h>
+
+#ifndef CONFIG_AP_PWRSEQ_DRIVER
+/* The wait time is ~150 msec, allow for safety margin. */
+#define IN_PCH_SLP_SUS_WAIT_TIME_MS 250
+
+enum power_states_ndsx chipset_pwr_sm_run(enum power_states_ndsx curr_state);
+enum power_states_ndsx chipset_pwr_seq_get_state(void);
+enum power_states_ndsx pwr_sm_get_state(void);
+const char *const pwr_sm_get_state_name(enum power_states_ndsx state);
+#else
+enum ap_pwrseq_state chipset_pwr_seq_get_state(void);
+const char *const pwr_sm_get_state_name(enum ap_pwrseq_state state);
+#endif
+void request_start_from_g3(void);
+void apshutdown(void);
+void ap_pwrseq_handle_chipset_reset(void);
+void set_start_from_g3_delay_seconds(uint32_t d_time);
+
+#endif /* __X86_NON_DSX_COMMON_PWRSEQ_SM_HANDLER_H__ */
diff --git a/zephyr/subsys/ap_pwrseq/include/x86_power_signals.h b/zephyr/subsys/ap_pwrseq/include/x86_power_signals.h
new file mode 100644
index 0000000000..7c7e25d951
--- /dev/null
+++ b/zephyr/subsys/ap_pwrseq/include/x86_power_signals.h
@@ -0,0 +1,84 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Define power signals from device tree */
+
+#ifndef __X86_POWER_SIGNALS_H__
+#define __X86_POWER_SIGNALS_H__
+
+#define IN_PCH_SLP_S0 POWER_SIGNAL_MASK(PWR_SLP_S0)
+#define IN_PCH_SLP_S3 POWER_SIGNAL_MASK(PWR_SLP_S3)
+#define IN_PCH_SLP_S4 POWER_SIGNAL_MASK(PWR_SLP_S4)
+#define IN_PCH_SLP_S5 POWER_SIGNAL_MASK(PWR_SLP_S5)
+
+/*
+ * Define the chipset specific power signal masks and values
+ * matching the AP state.
+ */
+#if defined(CONFIG_AP_X86_INTEL_ADL)
+
+/* Input state flags */
+#define IN_PCH_SLP_SUS POWER_SIGNAL_MASK(PWR_SLP_SUS)
+#define IN_PGOOD_ALL_CORE POWER_SIGNAL_MASK(PWR_DSW_PWROK)
+#define PWRSEQ_G3S5_UP_SIGNAL IN_PCH_SLP_SUS
+#define PWRSEQ_G3S5_UP_VALUE 0
+
+#define MASK_ALL_POWER_GOOD                     \
+	(POWER_SIGNAL_MASK(PWR_RSMRST) |        \
+	 POWER_SIGNAL_MASK(PWR_ALL_SYS_PWRGD) | \
+	 POWER_SIGNAL_MASK(PWR_DSW_PWROK) | POWER_SIGNAL_MASK(PWR_PG_PP1P05))
+
+#define MASK_VW_POWER                                                       \
+	(POWER_SIGNAL_MASK(PWR_RSMRST) | POWER_SIGNAL_MASK(PWR_DSW_PWROK) | \
+	 POWER_SIGNAL_MASK(PWR_SLP_SUS))
+#define VALUE_VW_POWER \
+	(POWER_SIGNAL_MASK(PWR_RSMRST) | POWER_SIGNAL_MASK(PWR_DSW_PWROK))
+
+#define MASK_S0                                                           \
+	(MASK_ALL_POWER_GOOD | POWER_SIGNAL_MASK(PWR_SLP_S0) |            \
+	 POWER_SIGNAL_MASK(PWR_SLP_S3) | POWER_SIGNAL_MASK(PWR_SLP_SUS) | \
+	 POWER_SIGNAL_MASK(PWR_SLP_S4) | POWER_SIGNAL_MASK(PWR_SLP_S5))
+#define VALUE_S0 MASK_ALL_POWER_GOOD
+
+#define MASK_S3 MASK_S0
+#define VALUE_S3 (MASK_ALL_POWER_GOOD | POWER_SIGNAL_MASK(PWR_SLP_S3))
+
+#define MASK_S5                                                             \
+	(POWER_SIGNAL_MASK(PWR_RSMRST) | POWER_SIGNAL_MASK(PWR_DSW_PWROK) | \
+	 POWER_SIGNAL_MASK(PWR_SLP_S3) | POWER_SIGNAL_MASK(PWR_SLP_S4) |    \
+	 POWER_SIGNAL_MASK(PWR_SLP_S5))
+#define VALUE_S5 MASK_S5
+
+#elif defined(CONFIG_AP_X86_INTEL_MTL)
+
+#define IN_PGOOD_ALL_CORE POWER_SIGNAL_MASK(PWR_RSMRST)
+#define PWRSEQ_G3S5_UP_SIGNAL IN_PGOOD_ALL_CORE
+#define PWRSEQ_G3S5_UP_VALUE IN_PGOOD_ALL_CORE
+
+#define MASK_ALL_POWER_GOOD \
+	(POWER_SIGNAL_MASK(PWR_RSMRST) | POWER_SIGNAL_MASK(PWR_ALL_SYS_PWRGD))
+
+#define MASK_VW_POWER POWER_SIGNAL_MASK(PWR_RSMRST)
+#define VALUE_VW_POWER POWER_SIGNAL_MASK(PWR_RSMRST)
+
+#define MASK_S0                                                          \
+	(MASK_ALL_POWER_GOOD | POWER_SIGNAL_MASK(PWR_SLP_S0) |           \
+	 POWER_SIGNAL_MASK(PWR_SLP_S3) | POWER_SIGNAL_MASK(PWR_SLP_S4) | \
+	 POWER_SIGNAL_MASK(PWR_SLP_S5))
+#define VALUE_S0 MASK_ALL_POWER_GOOD
+
+#define MASK_S3 MASK_S0
+#define VALUE_S3 (MASK_ALL_POWER_GOOD | POWER_SIGNAL_MASK(PWR_SLP_S3))
+
+#define MASK_S5                                                          \
+	(POWER_SIGNAL_MASK(PWR_RSMRST) | POWER_SIGNAL_MASK(PWR_SLP_S3) | \
+	 POWER_SIGNAL_MASK(PWR_SLP_S4) | POWER_SIGNAL_MASK(PWR_SLP_S5))
+#define VALUE_S5 MASK_S5
+
+#else
+#warning("Input power signals state flags not defined");
+#endif
+
+#endif /* __X86_POWER_SIGNALS_H__ */
diff --git a/zephyr/subsys/ap_pwrseq/power_host_sleep.c b/zephyr/subsys/ap_pwrseq/power_host_sleep.c
new file mode 100644
index 0000000000..82e84a02fd
--- /dev/null
+++ b/zephyr/subsys/ap_pwrseq/power_host_sleep.c
@@ -0,0 +1,301 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <ap_power/ap_power_interface.h>
+#include <ap_power/ap_pwrseq.h>
+#include <x86_non_dsx_common_pwrseq_sm_handler.h>
+
+LOG_MODULE_DECLARE(ap_pwrseq, CONFIG_AP_PWRSEQ_LOG_LEVEL);
+
+#if CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI
+
+/* If host doesn't program S0ix lazy wake mask, use default S0ix mask */
+#define DEFAULT_WAKE_MASK_S0IX                        \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
+
+/*
+ * Set the wake mask according to the current power state:
+ * 1. On transition to S0, wake mask is reset.
+ * 2. In non-S0 states, active mask set by host gets a higher preference.
+ * 3. If host has not set any active mask, then check if a lazy mask exists
+ *    for the current power state.
+ * 4. If state is S0ix and no lazy or active wake mask is set, then use default
+ *    S0ix mask to be compatible with older BIOS versions.
+ */
+#ifndef CONFIG_AP_PWRSEQ_DRIVER
+void power_update_wake_mask(void)
+{
+	host_event_t wake_mask;
+	enum power_states_ndsx state;
+
+	state = pwr_sm_get_state();
+
+	if (state == SYS_POWER_STATE_S0)
+		wake_mask = 0;
+	else if (lpc_is_active_wm_set_by_host() ||
+		 ap_power_get_lazy_wake_mask(state, &wake_mask))
+		return;
+#if CONFIG_AP_PWRSEQ_S0IX
+	if ((state == SYS_POWER_STATE_S0ix) && (wake_mask == 0))
+		wake_mask = DEFAULT_WAKE_MASK_S0IX;
+#endif
+
+	lpc_set_host_event_mask(LPC_HOST_EVENT_WAKE, wake_mask);
+}
+#else
+void power_update_wake_mask(void)
+{
+	const struct device *dev = ap_pwrseq_get_instance();
+	host_event_t wake_mask;
+	enum ap_pwrseq_state state;
+
+	state = ap_pwrseq_get_current_state(dev);
+
+	if (state == AP_POWER_STATE_S0)
+		wake_mask = 0;
+	else if (lpc_is_active_wm_set_by_host() ||
+		 ap_power_get_lazy_wake_mask(state, &wake_mask))
+		return;
+#if CONFIG_AP_PWRSEQ_S0IX
+	if ((state == AP_POWER_STATE_S0IX) && (wake_mask == 0))
+		wake_mask = DEFAULT_WAKE_MASK_S0IX;
+#endif
+
+	lpc_set_host_event_mask(LPC_HOST_EVENT_WAKE, wake_mask);
+}
+#endif /* CONFIG_AP_PWRSEQ_DRIVER */
+
+static void power_update_wake_mask_deferred(struct k_work *work)
+{
+	power_update_wake_mask();
+}
+
+static K_WORK_DELAYABLE_DEFINE(power_update_wake_mask_deferred_data,
+			       power_update_wake_mask_deferred);
+
+void ap_power_set_active_wake_mask(void)
+{
+	int rv;
+
+	/*
+	 * Allow state machine to stabilize and update wake mask after 5msec. It
+	 * was observed that on platforms where host wakes up periodically from
+	 * S0ix for hardware book-keeping activities, there is a small window
+	 * where host is not really up and running software, but still SLP_S0#
+	 * is de-asserted and hence setting wake mask right away can cause user
+	 * wake events to be missed.
+	 *
+	 * Time for deferred callback was chosen to be 5msec based on the fact
+	 * that it takes ~2msec for the periodic wake cycle to complete on the
+	 * host for KBL.
+	 */
+	rv = k_work_schedule(&power_update_wake_mask_deferred_data, K_MSEC(5));
+	if (rv == 0) {
+		/*
+		 * A work is already scheduled or submitted, since power state
+		 * has changed again and the work is not processed, we should
+		 * reschedule it.
+		 */
+		rv = k_work_reschedule(&power_update_wake_mask_deferred_data,
+				       K_MSEC(5));
+	}
+	__ASSERT(rv >= 0, "Set wake mask work queue error");
+}
+
+#else /* CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI */
+static void ap_power_set_active_wake_mask(void)
+{
+}
+#endif /* CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI */
+
+#if CONFIG_AP_PWRSEQ_S0IX
+/*
+ * Backup copies of SCI and SMI mask to preserve across S0ix suspend/resume
+ * cycle. If the host uses S0ix, BIOS is not involved during suspend and resume
+ * operations and hence SCI/SMI masks are programmed only once during boot-up.
+ *
+ * These backup variables are set whenever host expresses its interest to
+ * enter S0ix and then lpc_host_event_mask for SCI and SMI are cleared. When
+ * host resumes from S0ix, masks from backup variables are copied over to
+ * lpc_host_event_mask for SCI and SMI.
+ */
+static host_event_t backup_sci_mask;
+static host_event_t backup_smi_mask;
+
+/* Flag to notify listeners about suspend/resume events. */
+enum ap_power_sleep_type sleep_state = AP_POWER_SLEEP_NONE;
+
+/*
+ * Clear host event masks for SMI and SCI when host is entering S0ix. This is
+ * done to prevent any SCI/SMI interrupts when the host is in suspend. Since
+ * BIOS is not involved in the suspend path, EC needs to take care of clearing
+ * these masks.
+ */
+static void power_s0ix_suspend_clear_masks(void)
+{
+	host_event_t sci_mask, smi_mask;
+
+	sci_mask = lpc_get_host_event_mask(LPC_HOST_EVENT_SCI);
+	smi_mask = lpc_get_host_event_mask(LPC_HOST_EVENT_SMI);
+
+	/* Do not backup already-cleared SCI/SMI masks. */
+	if (!sci_mask && !smi_mask)
+		return;
+
+	backup_sci_mask = sci_mask;
+	backup_smi_mask = smi_mask;
+	lpc_set_host_event_mask(LPC_HOST_EVENT_SCI, 0);
+	lpc_set_host_event_mask(LPC_HOST_EVENT_SMI, 0);
+}
+
+/*
+ * Restore host event masks for SMI and SCI when host exits S0ix. This is done
+ * because BIOS is not involved in the resume path and so EC needs to restore
+ * the masks from backup variables.
+ */
+static void power_s0ix_resume_restore_masks(void)
+{
+	/*
+	 * No need to restore SCI/SMI masks if both backup_sci_mask and
+	 * backup_smi_mask are zero. This indicates that there was a failure to
+	 * enter S0ix(SLP_S0# assertion) and hence SCI/SMI masks were never
+	 * backed up.
+	 */
+	if (!backup_sci_mask && !backup_smi_mask)
+		return;
+	lpc_set_host_event_mask(LPC_HOST_EVENT_SCI, backup_sci_mask);
+	lpc_set_host_event_mask(LPC_HOST_EVENT_SMI, backup_smi_mask);
+	backup_sci_mask = backup_smi_mask = 0;
+}
+
+/*
+ * Following functions are called in the S0ix path, not S3 path.
+ */
+
+/*
+ * Notify the sleep type that is going to transit to; this is a token to
+ * ensure both host sleep event passed by Host Command and SLP_S0 satisfy
+ * the conditions to suspend or resume.
+ *
+ * @param new_state Notified sleep type
+ */
+static void ap_power_sleep_set_notify(enum ap_power_sleep_type new_state)
+{
+	sleep_state = new_state;
+}
+
+enum ap_power_sleep_type ap_power_sleep_get_notify(void)
+{
+	return sleep_state;
+}
+
+#ifdef CONFIG_AP_PWRSEQ_S0IX_COUNTER
+atomic_t s0ix_counter;
+#endif
+
+void ap_power_sleep_notify_transition(enum ap_power_sleep_type check_state)
+{
+	if (sleep_state != check_state)
+		return;
+
+	if (check_state == AP_POWER_SLEEP_SUSPEND) {
+		/*
+		 * Transition to S0ix;
+		 * clear mask before others running suspend.
+		 */
+		power_s0ix_suspend_clear_masks();
+		ap_power_ev_send_callbacks(AP_POWER_SUSPEND);
+#ifdef CONFIG_AP_PWRSEQ_S0IX_COUNTER
+		atomic_inc(&s0ix_counter);
+#endif
+	} else if (check_state == AP_POWER_SLEEP_RESUME) {
+		ap_power_ev_send_callbacks(AP_POWER_RESUME);
+		/*
+		 * Transition is done; reset sleep state after resume.
+		 */
+		ap_power_sleep_set_notify(AP_POWER_SLEEP_NONE);
+	}
+}
+#endif /* CONFIG_AP_PWRSEQ_S0IX */
+
+#if CONFIG_AP_PWRSEQ_HOST_SLEEP
+#define HOST_SLEEP_EVENT_DEFAULT_RESET 0
+
+static struct host_sleep_event_context *g_ctx;
+
+void ap_power_reset_host_sleep_state(void)
+{
+	power_set_host_sleep_state(HOST_SLEEP_EVENT_DEFAULT_RESET);
+	ap_power_ev_send_callbacks(AP_POWER_S0IX_RESET_TRACKING);
+	ap_power_chipset_handle_host_sleep_event(HOST_SLEEP_EVENT_DEFAULT_RESET,
+						 NULL);
+}
+
+/* TODO: hook to reset event */
+void ap_power_handle_chipset_reset(void)
+{
+	if (ap_power_in_state(AP_POWER_STATE_STANDBY))
+		ap_power_reset_host_sleep_state();
+}
+
+void ap_power_chipset_handle_host_sleep_event(
+	enum host_sleep_event state, struct host_sleep_event_context *ctx)
+{
+	LOG_DBG("host sleep event = %d!", state);
+
+	g_ctx = ctx;
+
+#if CONFIG_AP_PWRSEQ_S0IX
+	if (state == HOST_SLEEP_EVENT_S0IX_SUSPEND) {
+		/*
+		 * Indicate to power state machine that a new host event for
+		 * s0ix/s3 suspend has been received and so chipset suspend
+		 * notification needs to be sent to listeners.
+		 */
+		ap_power_sleep_set_notify(AP_POWER_SLEEP_SUSPEND);
+		ap_power_ev_send_callbacks(AP_POWER_S0IX_SUSPEND_START);
+		power_signal_enable(PWR_SLP_S0);
+	} else if (state == HOST_SLEEP_EVENT_S0IX_RESUME) {
+		/*
+		 * Set sleep state to resume; restore SCI/SMI masks;
+		 * SLP_S0 should be de-asserted already, disable interrupt.
+		 */
+		ap_power_sleep_set_notify(AP_POWER_SLEEP_RESUME);
+		power_s0ix_resume_restore_masks();
+		power_signal_disable(PWR_SLP_S0);
+		ap_power_ev_send_callbacks(AP_POWER_S0IX_RESUME_COMPLETE);
+
+		/*
+		 * If the sleep signal timed out and never transitioned, then
+		 * the wake mask was modified to its suspend state (S0ix), so
+		 * that the event wakes the system. Explicitly restore the wake
+		 * mask to its S0 state now.
+		 */
+		power_update_wake_mask();
+
+	} else if (state == HOST_SLEEP_EVENT_DEFAULT_RESET) {
+		power_signal_disable(PWR_SLP_S0);
+	}
+#endif /* CONFIG_AP_PWRSEQ_S0IX */
+
+#ifndef CONFIG_AP_PWRSEQ_DRIVER
+	ap_pwrseq_wake();
+#else
+	ap_pwrseq_post_event(ap_pwrseq_get_instance(), AP_PWRSEQ_EVENT_HOST);
+#endif /* CONFIG_AP_PWRSEQ_DRIVER */
+}
+
+uint16_t host_get_sleep_timeout(void)
+{
+	return g_ctx->sleep_timeout_ms;
+}
+
+void host_set_sleep_transitions(uint32_t val)
+{
+	g_ctx->sleep_transitions = val;
+}
+
+#endif /* CONFIG_AP_PWRSEQ_HOST_SLEEP */
diff --git a/zephyr/subsys/ap_pwrseq/power_signals.c b/zephyr/subsys/ap_pwrseq/power_signals.c
new file mode 100644
index 0000000000..84a8b8ad53
--- /dev/null
+++ b/zephyr/subsys/ap_pwrseq/power_signals.c
@@ -0,0 +1,333 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "signal_adc.h"
+#include "signal_gpio.h"
+#include "signal_vw.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/atomic.h>
+#include <zephyr/toolchain.h>
+#ifdef CONFIG_AP_PWRSEQ_DRIVER
+#include <ap_power/ap_pwrseq.h>
+#endif
+
+#include <ap_power/ap_pwrseq.h>
+#include <power_signals.h>
+
+LOG_MODULE_DECLARE(ap_pwrseq, CONFIG_AP_PWRSEQ_LOG_LEVEL);
+
+BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(intel_ap_pwrseq) == 1,
+	     "Only one node for intel_ap_pwrseq is allowed");
+
+BUILD_ASSERT(POWER_SIGNAL_COUNT <= 32, "Too many power signals");
+
+/*
+ * Enum indicating type of signal.
+ */
+enum signal_source {
+	PWR_SIG_SRC_GPIO,
+	PWR_SIG_SRC_VW,
+	PWR_SIG_SRC_EXT,
+	PWR_SIG_SRC_ADC,
+};
+
+struct ps_config {
+	const char *debug_name;
+	uint8_t source;
+	uint8_t src_enum;
+};
+
+#define TAG_PWR_ENUM(tag, name) DT_CAT(tag, name)
+
+#define PWR_ENUM(id, tag) TAG_PWR_ENUM(tag, PWR_SIGNAL_ENUM(id))
+
+#ifdef CONFIG_AP_PWRSEQ_SIGNAL_DEBUG_NAMES
+#define DBGNAME(id) "(" DT_PROP(id, enum_name) ") " DT_PROP(id, dbg_label)
+#else
+#define DBGNAME(id) DT_PROP(id, enum_name)
+#endif
+
+#define GEN_PS_ENTRY(id, src, tag)             \
+	{                                      \
+		.debug_name = DBGNAME(id),     \
+		.source = src,                 \
+		.src_enum = PWR_ENUM(id, tag), \
+	},
+
+#define GEN_PS_ENTRY_NO_ENUM(id, src)      \
+	{                                  \
+		.debug_name = DBGNAME(id), \
+		.source = src,             \
+	},
+
+/*
+ * Generate the power signal configuration array.
+ */
+/* clang-format off */
+static const struct ps_config sig_config[] = {
+	DT_FOREACH_STATUS_OKAY_VARGS(intel_ap_pwrseq_gpio, GEN_PS_ENTRY,
+				     PWR_SIG_SRC_GPIO, PWR_SIG_TAG_GPIO)
+	DT_FOREACH_STATUS_OKAY_VARGS(intel_ap_pwrseq_vw, GEN_PS_ENTRY,
+				     PWR_SIG_SRC_VW, PWR_SIG_TAG_VW)
+	DT_FOREACH_STATUS_OKAY_VARGS(intel_ap_pwrseq_external,
+				     GEN_PS_ENTRY_NO_ENUM, PWR_SIG_SRC_EXT)
+	DT_FOREACH_STATUS_OKAY_VARGS(intel_ap_pwrseq_adc, GEN_PS_ENTRY,
+				     PWR_SIG_SRC_ADC, PWR_SIG_TAG_ADC)
+};
+/* clang-format on */
+
+#define PWR_SIGNAL_POLLED(id) PWR_SIGNAL_ENUM(id),
+
+/*
+ * List of power signals that need to be polled.
+ */
+static const uint8_t polled_signals[] = { DT_FOREACH_STATUS_OKAY(
+	intel_ap_pwrseq_external, PWR_SIGNAL_POLLED) };
+
+/*
+ * Bitmasks of power signals. A previous copy is held so that
+ * logging of changes can occur if the signal is in the debug mask.
+ */
+static atomic_t power_signals, prev_power_signals;
+
+static power_signal_mask_t debug_signals;
+
+void power_set_debug(power_signal_mask_t debug)
+{
+	debug_signals = debug;
+	/* Copy the current values */
+	atomic_set(&prev_power_signals, atomic_get(&power_signals));
+}
+
+power_signal_mask_t power_get_debug(void)
+{
+	return debug_signals;
+}
+
+static inline void check_debug(enum power_signal signal)
+{
+	/*
+	 * Only check for debug display if the logging level requires it.
+	 */
+	if ((CONFIG_AP_PWRSEQ_LOG_LEVEL >= LOG_LEVEL_INF) &&
+	    (debug_signals & POWER_SIGNAL_MASK(signal))) {
+		bool value = atomic_test_bit(&power_signals, signal);
+
+		if (value != atomic_test_bit(&prev_power_signals, signal)) {
+			LOG_INF("%s -> %d", power_signal_name(signal), value);
+			atomic_set_bit_to(&prev_power_signals, signal, value);
+		}
+	}
+}
+
+power_signal_mask_t power_get_signals(void)
+{
+	power_signal_mask_t mask = 0;
+
+	for (int i = 0; i < ARRAY_SIZE(polled_signals); i++) {
+		if (power_signal_get(polled_signals[i])) {
+			mask |= POWER_SIGNAL_MASK(polled_signals[i]);
+		}
+	}
+	return mask | atomic_get(&power_signals);
+}
+
+#ifndef CONFIG_AP_PWRSEQ_DRIVER
+void power_signal_interrupt(enum power_signal signal, int value)
+{
+	atomic_set_bit_to(&power_signals, signal, value);
+	check_debug(signal);
+	ap_pwrseq_wake();
+}
+#else
+void power_signal_interrupt(enum power_signal signal, int value)
+{
+	const struct device *ap_pwrseq_dev = ap_pwrseq_get_instance();
+
+	atomic_set_bit_to(&power_signals, signal, value);
+	check_debug(signal);
+	ap_pwrseq_post_event(ap_pwrseq_dev, AP_PWRSEQ_EVENT_POWER_SIGNAL);
+}
+#endif
+int power_wait_mask_signals_timeout(power_signal_mask_t mask,
+				    power_signal_mask_t want, int timeout)
+{
+	if (mask == 0) {
+		return 0;
+	}
+	want &= mask;
+	while (timeout-- > 0) {
+		if ((power_get_signals() & mask) == want) {
+			return 0;
+		}
+		k_msleep(1);
+	}
+	return -ETIMEDOUT;
+}
+
+int power_signal_get(enum power_signal signal)
+{
+	const struct ps_config *cp;
+
+	if (signal < 0 || signal >= POWER_SIGNAL_COUNT) {
+		return -EINVAL;
+	}
+	cp = &sig_config[signal];
+	switch (cp->source) {
+	default:
+		return -EINVAL; /* should never happen */
+
+#if CONFIG_AP_PWRSEQ_SIGNAL_GPIO
+	case PWR_SIG_SRC_GPIO:
+		return power_signal_gpio_get(cp->src_enum);
+#endif
+
+#if CONFIG_AP_PWRSEQ_SIGNAL_VW
+	case PWR_SIG_SRC_VW:
+		return power_signal_vw_get(cp->src_enum);
+#endif
+
+#if CONFIG_AP_PWRSEQ_SIGNAL_EXTERNAL
+	case PWR_SIG_SRC_EXT:
+		return board_power_signal_get(signal);
+#endif
+
+#if CONFIG_AP_PWRSEQ_SIGNAL_ADC
+	case PWR_SIG_SRC_ADC:
+		return power_signal_adc_get(cp->src_enum);
+#endif
+	}
+}
+
+int power_signal_set(enum power_signal signal, int value)
+{
+	const struct ps_config *cp;
+	int ret;
+
+	if (signal < 0 || signal >= POWER_SIGNAL_COUNT) {
+		return -EINVAL;
+	}
+	cp = &sig_config[signal];
+	LOG_DBG("Set %s to %d", power_signal_name(signal), value);
+	switch (cp->source) {
+	default:
+		return -EINVAL;
+
+#if CONFIG_AP_PWRSEQ_SIGNAL_GPIO
+	case PWR_SIG_SRC_GPIO:
+		ret = power_signal_gpio_set(cp->src_enum, value);
+		break;
+#endif
+
+#if CONFIG_AP_PWRSEQ_SIGNAL_EXTERNAL
+	case PWR_SIG_SRC_EXT:
+		ret = board_power_signal_set(signal, value);
+		break;
+#endif
+	}
+	/*
+	 * Output succeeded, update mask.
+	 */
+	if (ret == 0) {
+		atomic_set_bit_to(&power_signals, signal, value);
+		check_debug(signal);
+	}
+	return ret;
+}
+
+int power_signal_enable(enum power_signal signal)
+{
+	const struct ps_config *cp;
+
+	if (signal < 0 || signal >= POWER_SIGNAL_COUNT) {
+		return -EINVAL;
+	}
+	cp = &sig_config[signal];
+	switch (cp->source) {
+	default:
+		/*
+		 * Not sure if board (external) signals will
+		 * need interrupt enable/disable.
+		 */
+		return -EINVAL;
+
+#if CONFIG_AP_PWRSEQ_SIGNAL_GPIO
+	case PWR_SIG_SRC_GPIO:
+		return power_signal_gpio_enable(cp->src_enum);
+#endif
+#if CONFIG_AP_PWRSEQ_SIGNAL_ADC
+	case PWR_SIG_SRC_ADC:
+		return power_signal_adc_enable(cp->src_enum);
+#endif
+	}
+}
+
+int power_signal_disable(enum power_signal signal)
+{
+	const struct ps_config *cp;
+
+	if (signal < 0 || signal >= POWER_SIGNAL_COUNT) {
+		return -EINVAL;
+	}
+	cp = &sig_config[signal];
+	switch (cp->source) {
+	default:
+		return -EINVAL;
+
+#if CONFIG_AP_PWRSEQ_SIGNAL_GPIO
+	case PWR_SIG_SRC_GPIO:
+		return power_signal_gpio_disable(cp->src_enum);
+#endif
+#if CONFIG_AP_PWRSEQ_SIGNAL_ADC
+	case PWR_SIG_SRC_ADC:
+		return power_signal_adc_disable(cp->src_enum);
+#endif
+	}
+}
+
+const char *power_signal_name(enum power_signal signal)
+{
+	if (signal < 0 || signal >= POWER_SIGNAL_COUNT) {
+		return NULL;
+	}
+	return sig_config[signal].debug_name;
+}
+
+void power_signal_init(void)
+{
+	if (IS_ENABLED(CONFIG_AP_PWRSEQ_SIGNAL_GPIO)) {
+		power_signal_gpio_init();
+	}
+	if (IS_ENABLED(CONFIG_AP_PWRSEQ_SIGNAL_VW)) {
+		power_signal_vw_init();
+	}
+	if (IS_ENABLED(CONFIG_AP_PWRSEQ_SIGNAL_ADC)) {
+		power_signal_adc_init();
+	}
+	/*
+	 * Initialise the mask with the current values.
+	 * This includes the outputs as well.
+	 */
+	for (int i = 0; i < POWER_SIGNAL_COUNT; i++) {
+		if (power_signal_get(i) == 1) {
+			atomic_set_bit(&power_signals, i);
+		}
+	}
+	/*
+	 * Some signals are polled (such as the board external signals),
+	 * so clear these values from the initial state so they
+	 * don't get OR'ed in later on.
+	 */
+	for (int i = 0; i < ARRAY_SIZE(polled_signals); i++) {
+		atomic_clear_bit(&power_signals, polled_signals[i]);
+	}
+	/*
+	 * Save the current state so that new changes can be
+	 * checked against the debug mask.
+	 */
+	atomic_set(&prev_power_signals, atomic_get(&power_signals));
+}
diff --git a/zephyr/subsys/ap_pwrseq/signal_adc.c b/zephyr/subsys/ap_pwrseq/signal_adc.c
new file mode 100644
index 0000000000..693ac91dba
--- /dev/null
+++ b/zephyr/subsys/ap_pwrseq/signal_adc.c
@@ -0,0 +1,204 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "signal_adc.h"
+
+#include <zephyr/drivers/adc.h>
+#include <zephyr/drivers/sensor.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/atomic.h>
+
+#include <power_signals.h>
+
+#define DT_DRV_COMPAT intel_ap_pwrseq_adc
+
+LOG_MODULE_DECLARE(ap_pwrseq, CONFIG_AP_PWRSEQ_LOG_LEVEL);
+
+struct adc_config {
+	const struct device *dev_trig_high;
+	const struct device *dev_trig_low;
+	const struct device *adc_dev;
+	uint8_t adc_ch;
+	uint16_t threshold;
+	enum power_signal signal;
+};
+
+#define ADC_HIGH_DEV(node_id) DEVICE_DT_GET(DT_IO_CHANNELS_CTLR(node_id))
+
+#define ADC_HIGH_CHAN(node_id) DT_IO_CHANNELS_INPUT(node_id)
+
+#define ADC_THRESH(node_id) DT_PROP(node_id, threshold_mv)
+
+#define INIT_ADC_CONFIG(inst)                                                 \
+	{                                                                     \
+		.dev_trig_high =                                              \
+			DEVICE_DT_GET(DT_INST_PHANDLE(inst, trigger_high)),   \
+		.dev_trig_low =                                               \
+			DEVICE_DT_GET(DT_INST_PHANDLE(inst, trigger_low)),    \
+		.adc_dev = ADC_HIGH_DEV(DT_INST_PHANDLE(inst, trigger_high)), \
+		.adc_ch = ADC_HIGH_CHAN(DT_INST_PHANDLE(inst, trigger_high)), \
+		.threshold = ADC_THRESH(DT_INST_PHANDLE(inst, trigger_high)), \
+		.signal = PWR_DT_INST_SIGNAL_ENUM(inst),                      \
+	},
+
+static const struct adc_config config[] = { DT_INST_FOREACH_STATUS_OKAY(
+	INIT_ADC_CONFIG) };
+
+/*
+ * Bit allocations for atomic state
+ */
+enum { ADC_BIT_VALUE = 0, ADC_BIT_LOW_ENABLED = 1, ADC_BIT_HIGH_ENABLED = 2 };
+
+atomic_t adc_state[ARRAY_SIZE(config)];
+
+static void set_trigger(const struct device *dev, atomic_t *state, int bit,
+			bool enable)
+{
+	/*
+	 * Only enable or disable if the trigger is not
+	 * already enabled or disabled.
+	 */
+	if (enable ? !atomic_test_and_set_bit(state, bit) :
+		     atomic_test_and_clear_bit(state, bit)) {
+		struct sensor_value val;
+
+		val.val1 = enable;
+		sensor_attr_set(dev, SENSOR_CHAN_VOLTAGE, SENSOR_ATTR_ALERT,
+				&val);
+	}
+}
+
+static void set_low_trigger(enum pwr_sig_adc adc, bool enable)
+{
+	set_trigger(config[adc].dev_trig_low, &adc_state[adc],
+		    ADC_BIT_LOW_ENABLED, enable);
+}
+
+static void set_high_trigger(enum pwr_sig_adc adc, bool enable)
+{
+	set_trigger(config[adc].dev_trig_high, &adc_state[adc],
+		    ADC_BIT_HIGH_ENABLED, enable);
+}
+
+static void trigger_high(enum pwr_sig_adc adc)
+{
+	set_high_trigger(adc, false);
+	atomic_set_bit(&adc_state[adc], ADC_BIT_VALUE);
+	set_low_trigger(adc, true);
+	LOG_DBG("power signal adc%d is HIGH", adc);
+	power_signal_interrupt(config[adc].signal, 1);
+}
+
+static void trigger_low(enum pwr_sig_adc adc)
+{
+	set_low_trigger(adc, false);
+	atomic_clear_bit(&adc_state[adc], ADC_BIT_VALUE);
+	set_high_trigger(adc, true);
+	LOG_DBG("power signal adc%d is LOW", adc);
+	power_signal_interrupt(config[adc].signal, 0);
+}
+
+int power_signal_adc_get(enum pwr_sig_adc adc)
+{
+	if (adc < 0 || adc >= ARRAY_SIZE(config)) {
+		return -EINVAL;
+	}
+	return atomic_test_bit(&adc_state[adc], ADC_BIT_VALUE);
+}
+
+int power_signal_adc_enable(enum pwr_sig_adc adc)
+{
+	if (adc < 0 || adc >= ARRAY_SIZE(config)) {
+		return -EINVAL;
+	}
+
+	/* Only need to enable relevant trigger depending on current state */
+	if (atomic_test_bit(&adc_state[adc], ADC_BIT_VALUE)) {
+		set_low_trigger(adc, true);
+	} else {
+		set_high_trigger(adc, true);
+	}
+	return 0;
+}
+
+int power_signal_adc_disable(enum pwr_sig_adc adc)
+{
+	if (adc < 0 || adc >= ARRAY_SIZE(config)) {
+		return -EINVAL;
+	}
+	set_low_trigger(adc, false);
+	set_high_trigger(adc, false);
+	return 0;
+}
+
+/*
+ * Macros to create individual callbacks for
+ * high and low triggers for each ADC.
+ */
+
+#define TAG_ADC(tag, name) DT_CAT(tag, name)
+
+#define PWR_ADC_ENUM(inst) \
+	TAG_ADC(PWR_SIG_TAG_ADC, PWR_DT_INST_SIGNAL_ENUM(inst))
+
+#define ADC_CB(inst, lev) cb_##lev##_##inst
+
+#define ADC_CB_DEFINE(inst, lev)                                            \
+	static void ADC_CB(inst, lev)(const struct device *dev,             \
+				      const struct sensor_trigger *trigger) \
+	{                                                                   \
+		trigger_##lev(PWR_ADC_ENUM(inst));                          \
+	}
+
+DT_INST_FOREACH_STATUS_OKAY_VARGS(ADC_CB_DEFINE, high)
+DT_INST_FOREACH_STATUS_OKAY_VARGS(ADC_CB_DEFINE, low)
+
+#define ADC_CB_COMMA(inst, lev) ADC_CB(inst, lev),
+
+void power_signal_adc_init(void)
+{
+	struct sensor_trigger trig = { .type = SENSOR_TRIG_THRESHOLD,
+				       .chan = SENSOR_CHAN_VOLTAGE };
+	sensor_trigger_handler_t low_cb[] = { DT_INST_FOREACH_STATUS_OKAY_VARGS(
+		ADC_CB_COMMA, low) };
+	sensor_trigger_handler_t high_cb[] = {
+		DT_INST_FOREACH_STATUS_OKAY_VARGS(ADC_CB_COMMA, high)
+	};
+	int i, rv;
+	int32_t val = 0;
+
+	for (i = 0; i < ARRAY_SIZE(low_cb); i++) {
+		/*
+		 * Read initial value.
+		 */
+		const struct device *dev = config[i].adc_dev;
+		struct adc_sequence seq = {
+			.options = NULL,
+			.channels = BIT(config[i].adc_ch),
+			.buffer = &val,
+			.buffer_size = sizeof(val),
+			.resolution = CONFIG_PLATFORM_EC_ADC_RESOLUTION,
+			.oversampling = CONFIG_PLATFORM_EC_ADC_OVERSAMPLING,
+			.calibrate = false,
+		};
+
+		rv = adc_read(dev, &seq);
+		if (rv) {
+			LOG_ERR("ADC %s:%d initial read failed", dev->name,
+				config[i].adc_ch);
+		} else {
+			adc_raw_to_millivolts(adc_ref_internal(dev), ADC_GAIN_1,
+					      CONFIG_PLATFORM_EC_ADC_RESOLUTION,
+					      &val);
+			if (val >= config[i].threshold) {
+				atomic_set_bit(&adc_state[i], ADC_BIT_VALUE);
+			}
+		}
+		/* Set high and low trigger callbacks */
+		sensor_trigger_set(config[i].dev_trig_high, &trig, high_cb[i]);
+		sensor_trigger_set(config[i].dev_trig_low, &trig, low_cb[i]);
+		power_signal_adc_enable(i);
+	}
+}
diff --git a/zephyr/subsys/ap_pwrseq/signal_gpio.c b/zephyr/subsys/ap_pwrseq/signal_gpio.c
new file mode 100644
index 0000000000..b47f1afd3d
--- /dev/null
+++ b/zephyr/subsys/ap_pwrseq/signal_gpio.c
@@ -0,0 +1,175 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "signal_gpio.h"
+#include "system.h"
+
+#include <zephyr/drivers/gpio.h>
+
+#include <power_signals.h>
+
+#define DT_DRV_COMPAT intel_ap_pwrseq_gpio
+
+#define INIT_GPIO_SPEC(inst) GPIO_DT_SPEC_INST_GET(inst, gpios),
+
+const static struct gpio_dt_spec spec[] = { DT_INST_FOREACH_STATUS_OKAY(
+	INIT_GPIO_SPEC) };
+
+/*
+ * Configuration for GPIO inputs.
+ */
+struct ps_gpio_int {
+	gpio_flags_t flags;
+	uint8_t signal;
+	unsigned int output : 1;
+	unsigned int no_enable : 1;
+};
+
+#define INIT_GPIO_CONFIG(inst)                                      \
+	{                                                           \
+		.flags = DT_INST_PROP_OR(inst, interrupt_flags, 0), \
+		.signal = PWR_DT_INST_SIGNAL_ENUM(inst),            \
+		.no_enable = DT_INST_PROP(inst, no_enable),         \
+		.output = DT_INST_PROP(inst, output),               \
+	},
+
+const static struct ps_gpio_int gpio_config[] = { DT_INST_FOREACH_STATUS_OKAY(
+	INIT_GPIO_CONFIG) };
+
+static struct gpio_callback int_cb[ARRAY_SIZE(gpio_config)];
+
+int power_signal_gpio_enable(enum pwr_sig_gpio index)
+{
+	gpio_flags_t flags;
+
+	if (index < 0 || index >= ARRAY_SIZE(gpio_config)) {
+		return -EINVAL;
+	}
+	/*
+	 * Do not allow interrupts on an output GPIO.
+	 */
+	if (gpio_config[index].output) {
+		return -EINVAL;
+	}
+	flags = gpio_config[index].flags;
+
+	/* Only enable if flags are present. */
+	if (flags) {
+		return gpio_pin_interrupt_configure_dt(&spec[index], flags);
+	}
+	return -EINVAL;
+}
+
+int power_signal_gpio_disable(enum pwr_sig_gpio index)
+{
+	gpio_flags_t flags;
+
+	if (index < 0 || index >= ARRAY_SIZE(gpio_config)) {
+		return -EINVAL;
+	}
+	/*
+	 * Do not allow interrupts on an output GPIO.
+	 */
+	if (gpio_config[index].output) {
+		return -EINVAL;
+	}
+	flags = gpio_config[index].flags;
+
+	/* Disable if flags are present. */
+	if (flags) {
+		return gpio_pin_interrupt_configure_dt(&spec[index],
+						       GPIO_INT_DISABLE);
+	}
+	return -EINVAL;
+}
+
+void power_signal_gpio_interrupt(const struct device *port,
+				 struct gpio_callback *cb,
+				 gpio_port_pins_t pins)
+{
+	int index = cb - int_cb;
+
+	power_signal_interrupt(gpio_config[index].signal,
+			       gpio_pin_get_dt(&spec[index]));
+}
+
+int power_signal_gpio_get(enum pwr_sig_gpio index)
+{
+	if (index < 0 || index >= ARRAY_SIZE(gpio_config)) {
+		return -EINVAL;
+	}
+	/*
+	 * Getting the current value of an output is
+	 * done by retrieving the config and checking what the
+	 * output state has been set to, not by reading the
+	 * physical level of the pin (open drain outputs
+	 * may have a low voltage).
+	 */
+	if (IS_ENABLED(CONFIG_GPIO_GET_CONFIG) && gpio_config[index].output) {
+		int rv;
+		gpio_flags_t flags;
+
+		rv = gpio_pin_get_config_dt(&spec[index], &flags);
+		if (rv == 0) {
+			int pin = (flags & GPIO_OUTPUT_INIT_HIGH) ? 1 : 0;
+			/* If active low signal, invert it */
+			if (spec[index].dt_flags & GPIO_ACTIVE_LOW) {
+				pin = !pin;
+			}
+			return pin;
+		}
+		/*
+		 * -ENOSYS is returned when this API call is not supported,
+		 *  so drop into the default method of returning the pin value.
+		 */
+		if (rv != -ENOSYS) {
+			return rv;
+		}
+	}
+	return gpio_pin_get_dt(&spec[index]);
+}
+
+int power_signal_gpio_set(enum pwr_sig_gpio index, int value)
+{
+	if (index < 0 || index >= ARRAY_SIZE(gpio_config)) {
+		return -EINVAL;
+	}
+	if (!gpio_config[index].output) {
+		return -EINVAL;
+	}
+	return gpio_pin_set_dt(&spec[index], value);
+}
+void power_signal_gpio_init(void)
+{
+	/*
+	 * If there has been a sysjump, do not set the output
+	 * to the deasserted state.
+	 */
+	gpio_flags_t out_flags = system_jumped_to_this_image() ?
+					 GPIO_OUTPUT :
+					 GPIO_OUTPUT_INACTIVE;
+
+	for (int i = 0; i < ARRAY_SIZE(gpio_config); i++) {
+		if (gpio_config[i].output) {
+			gpio_pin_configure_dt(&spec[i], out_flags);
+		} else {
+			gpio_pin_configure_dt(&spec[i], GPIO_INPUT);
+			/* If interrupt, initialise it */
+			if (gpio_config[i].flags) {
+				gpio_init_callback(&int_cb[i],
+						   power_signal_gpio_interrupt,
+						   BIT(spec[i].pin));
+				gpio_add_callback(spec[i].port, &int_cb[i]);
+				/*
+				 * If the interrupt is to be enabled at
+				 * startup, enable the interrupt.
+				 */
+				if (!gpio_config[i].no_enable) {
+					power_signal_gpio_enable(i);
+				}
+			}
+		}
+	}
+}
diff --git a/zephyr/subsys/ap_pwrseq/signal_vw.c b/zephyr/subsys/ap_pwrseq/signal_vw.c
new file mode 100644
index 0000000000..200e17af24
--- /dev/null
+++ b/zephyr/subsys/ap_pwrseq/signal_vw.c
@@ -0,0 +1,140 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "signal_vw.h"
+
+#include <zephyr/drivers/espi.h>
+
+#include <atomic.h>
+#include <x86_non_dsx_common_pwrseq_sm_handler.h>
+
+#define DT_DRV_COMPAT intel_ap_pwrseq_vw
+
+/*
+ * A callback must be registered on the ESPI device (for the
+ * bus events that are required to be handled) that calls
+ * power_signal_espi_cb().
+ *
+ * This registration is done in a common ESPI initialisation module so
+ * that there is no possibility of missing events.
+ */
+
+LOG_MODULE_DECLARE(ap_pwrseq, CONFIG_AP_PWRSEQ_LOG_LEVEL);
+
+#define INIT_ESPI_SIGNAL(inst)                                                 \
+	{                                                                      \
+		.espi_signal = DT_INST_STRING_UPPER_TOKEN(inst, virtual_wire), \
+		.signal = PWR_DT_INST_SIGNAL_ENUM(inst),                       \
+		.invert = DT_INST_PROP(inst, vw_invert),                       \
+	},
+
+/*
+ * Struct containing the eSPI virtual wire config.
+ */
+struct vw_config {
+	uint8_t espi_signal; /* associated VW signal */
+	uint8_t signal; /* power signal */
+	bool invert; /* Invert the signal value */
+};
+
+const static struct vw_config vw_config[] = { DT_INST_FOREACH_STATUS_OKAY(
+	INIT_ESPI_SIGNAL) };
+
+/*
+ * Current signal value.
+ */
+static atomic_t signal_data;
+/*
+ * Mask of valid signals. A signal is considered valid once an
+ * initial value has been received for it.
+ */
+static atomic_t signal_valid;
+
+#define espi_dev DEVICE_DT_GET(DT_CHOSEN(intel_ap_pwrseq_espi))
+
+BUILD_ASSERT(ARRAY_SIZE(vw_config) <= (sizeof(atomic_t) * 8));
+
+/*
+ * Set the value of the VW signal, and optionally
+ * call the power signal interrupt handling.
+ */
+static void vw_set(int index, int data, bool notify)
+{
+	bool value = vw_config[index].invert ? !data : !!data;
+
+	atomic_set_bit_to(&signal_data, index, value);
+	atomic_set_bit(&signal_valid, index);
+	if (notify) {
+		power_signal_interrupt(vw_config[index].signal, value);
+	}
+}
+
+/*
+ * Update all the VW signals.
+ */
+static void vw_update_all(bool notify)
+{
+	for (int i = 0; i < ARRAY_SIZE(vw_config); i++) {
+		uint8_t vw_value;
+
+		if (espi_receive_vwire(espi_dev, vw_config[i].espi_signal,
+				       &vw_value) == 0) {
+			vw_set(i, vw_value, notify);
+		}
+	}
+}
+
+void power_signal_espi_cb(const struct device *dev, struct espi_callback *cb,
+			  struct espi_event event)
+{
+	LOG_DBG("ESPI event type 0x%x %d:%d", event.evt_type, event.evt_details,
+		event.evt_data);
+	switch (event.evt_type) {
+	default:
+		__ASSERT(0, "ESPI unknown event type: %d", event.evt_type);
+		break;
+
+	case ESPI_BUS_EVENT_CHANNEL_READY:
+		/* Virtual wire channel status change */
+		if (event.evt_details == ESPI_CHANNEL_VWIRE) {
+			if (event.evt_data) {
+				/* If now ready, update all the signals */
+				vw_update_all(true);
+			} else {
+				/* If not ready, invalidate the signals */
+				atomic_clear(&signal_valid);
+			}
+		}
+		break;
+
+	case ESPI_BUS_EVENT_VWIRE_RECEIVED:
+		for (int i = 0; i < ARRAY_SIZE(vw_config); i++) {
+			if (event.evt_details == vw_config[i].espi_signal) {
+				vw_set(i, event.evt_data, true);
+			}
+		}
+		break;
+	}
+}
+
+int power_signal_vw_get(enum pwr_sig_vw vw)
+{
+	if (vw < 0 || vw >= ARRAY_SIZE(vw_config) ||
+	    !atomic_test_bit(&signal_valid, vw)) {
+		return -EINVAL;
+	}
+	return atomic_test_bit(&signal_data, vw);
+}
+
+void power_signal_vw_init(void)
+{
+	/*
+	 * Check whether the bus is ready, and if so,
+	 * initialise the current values of the signals.
+	 */
+	if (espi_get_channel_status(espi_dev, ESPI_CHANNEL_VWIRE)) {
+		vw_update_all(false);
+	}
+}
diff --git a/zephyr/subsys/ap_pwrseq/x86_non_dsx_adlp_pwrseq_sm.c b/zephyr/subsys/ap_pwrseq/x86_non_dsx_adlp_pwrseq_sm.c
new file mode 100644
index 0000000000..9ef482b712
--- /dev/null
+++ b/zephyr/subsys/ap_pwrseq/x86_non_dsx_adlp_pwrseq_sm.c
@@ -0,0 +1,176 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <x86_non_dsx_common_pwrseq_sm_handler.h>
+
+LOG_MODULE_DECLARE(ap_pwrseq, CONFIG_AP_PWRSEQ_LOG_LEVEL);
+
+static void ap_off(void)
+{
+	power_signal_set(PWR_VCCST_PWRGD, 0);
+	power_signal_set(PWR_PCH_PWROK, 0);
+	power_signal_set(PWR_EC_PCH_SYS_PWROK, 0);
+}
+
+static int check_pch_out_of_suspend(void)
+{
+	int ret;
+	/*
+	 * Wait for SLP_SUS deasserted.
+	 */
+	ret = power_wait_mask_signals_timeout(IN_PCH_SLP_SUS, 0,
+					      IN_PCH_SLP_SUS_WAIT_TIME_MS);
+	if (ret == 0) {
+		LOG_DBG("SLP_SUS now %d", power_signal_get(PWR_SLP_SUS));
+		return 1;
+	}
+	LOG_ERR("wait SLP_SUS deassertion timeout");
+	return 0; /* timeout */
+}
+
+/* Handle ALL_SYS_PWRGD signal
+ * This will be overridden if the custom signal handler is needed
+ */
+int all_sys_pwrgd_handler(void)
+{
+	int retry = 0;
+
+	/* SLP_S3 is off */
+	if (power_signal_get(PWR_SLP_S3) == 1) {
+		ap_off();
+		return 1;
+	}
+
+	/* TODO: Add condition for no power sequencer */
+	power_wait_signals_timeout(POWER_SIGNAL_MASK(PWR_ALL_SYS_PWRGD),
+				   AP_PWRSEQ_DT_VALUE(all_sys_pwrgd_timeout));
+
+	if (power_signal_get(PWR_DSW_PWROK) == 0) {
+		/* Todo: Remove workaround for the retry
+		 * without this change the system hits G3 as it detects
+		 * ALL_SYS_PWRGD as 0 and then 1 as a glitch
+		 */
+		while (power_signal_get(PWR_ALL_SYS_PWRGD) == 0) {
+			if (++retry > 2) {
+				LOG_ERR("PG_EC_ALL_SYS_PWRGD not ok");
+				ap_off();
+				return -1;
+			}
+			k_msleep(10);
+		}
+	}
+
+	/* PG_EC_ALL_SYS_PWRGD is asserted, enable VCCST_PWRGD_OD. */
+
+	if (!power_signals_on(POWER_SIGNAL_MASK(PWR_VCCST_PWRGD))) {
+		k_msleep(AP_PWRSEQ_DT_VALUE(vccst_pwrgd_delay));
+		power_signal_set(PWR_VCCST_PWRGD, 1);
+	}
+	return 0;
+}
+
+/* Generate SYS_PWROK->SOC if needed by system */
+void generate_sys_pwrok_handler(void)
+{
+	/* Enable PCH_SYS_PWROK. */
+	if (power_signal_get(PWR_EC_PCH_SYS_PWROK) == 0) {
+		k_msleep(AP_PWRSEQ_DT_VALUE(sys_pwrok_delay));
+		/* Check if we lost power while waiting. */
+		if (power_signal_get(PWR_ALL_SYS_PWRGD) == 0) {
+			LOG_DBG("PG_EC_ALL_SYS_PWRGD deasserted, "
+				"shutting AP off!");
+			ap_off();
+			return;
+		}
+		LOG_INF("Turning on PWR_EC_PCH_SYS_PWROK");
+		power_signal_set(PWR_EC_PCH_SYS_PWROK, 1);
+		/* PCH will now release PLT_RST */
+	}
+}
+
+/* Chipset specific power state machine handler */
+
+/* TODO: Separate with and without power sequencer logic here */
+
+void s0_action_handler(void)
+{
+	int ret;
+
+	/* Handle DSW_PWROK passthrough */
+	/* This is not needed for alderlake silego, guarded by CONFIG? */
+
+	/* Check ALL_SYS_PWRGD and take action */
+	ret = all_sys_pwrgd_handler();
+	if (ret) {
+		LOG_DBG("ALL_SYS_PWRGD handling failed err= %d", ret);
+		return;
+	}
+
+	/* Send PCH_PWROK->SoC if conditions met */
+	/* TODO: There is possibility of EC not needing to generate
+	 * this as power sequencer may do it
+	 */
+	ret = board_ap_power_assert_pch_power_ok();
+	if (ret) {
+		LOG_DBG("PCH_PWROK handling failed err=%d", ret);
+		return;
+	}
+
+	/* SYS_PWROK may be optional and the delay must be
+	 * configurable as it is variable with platform
+	 */
+	/* Send SYS_PWROK->SoC if conditions met */
+	generate_sys_pwrok_handler();
+}
+
+void s3s0_action_handler(void)
+{
+}
+
+void s0s3_action_handler(void)
+{
+	ap_off();
+}
+
+enum power_states_ndsx g3s5_action_handler(void)
+{
+	/*
+	 * Now wait for SLP_SUS_L to go high based on tPCH32. If this
+	 * signal doesn't go high within 250 msec then go back to G3.
+	 */
+	if (check_pch_out_of_suspend()) {
+		ap_power_ev_send_callbacks(AP_POWER_PRE_INIT);
+		return SYS_POWER_STATE_G3S5;
+	}
+	return SYS_POWER_STATE_S5G3;
+}
+
+enum power_states_ndsx chipset_pwr_sm_run(enum power_states_ndsx curr_state)
+{
+	/* Add chipset specific state handling if any */
+	switch (curr_state) {
+	case SYS_POWER_STATE_G3S5:
+		board_ap_power_action_g3_s5();
+		curr_state = g3s5_action_handler();
+		break;
+	case SYS_POWER_STATE_S5:
+		break;
+	case SYS_POWER_STATE_S3S0:
+		board_ap_power_action_s3_s0();
+		s3s0_action_handler();
+		break;
+	case SYS_POWER_STATE_S0S3:
+		board_ap_power_action_s0_s3();
+		s0s3_action_handler();
+		break;
+	case SYS_POWER_STATE_S0:
+		board_ap_power_action_s0();
+		s0_action_handler();
+		break;
+	default:
+		break;
+	}
+	return curr_state;
+}
diff --git a/zephyr/subsys/ap_pwrseq/x86_non_dsx_chipset_power_state.c b/zephyr/subsys/ap_pwrseq/x86_non_dsx_chipset_power_state.c
new file mode 100644
index 0000000000..58629cab82
--- /dev/null
+++ b/zephyr/subsys/ap_pwrseq/x86_non_dsx_chipset_power_state.c
@@ -0,0 +1,293 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifdef CONFIG_AP_PWRSEQ_DRIVER
+#include <ap_power/ap_power_events.h>
+#include <ap_power/ap_pwrseq_sm.h>
+#endif
+#include <x86_common_pwrseq.h>
+#include <x86_non_dsx_common_pwrseq_sm_handler.h>
+
+LOG_MODULE_DECLARE(ap_pwrseq, CONFIG_AP_PWRSEQ_LOG_LEVEL);
+
+/**
+ * Determine the current state of the CPU from the
+ * power signals.
+ */
+#ifndef CONFIG_AP_PWRSEQ_DRIVER
+enum power_states_ndsx chipset_pwr_seq_get_state(void)
+{
+	power_signal_mask_t sig = power_get_signals();
+
+	/*
+	 * Chip is shut down, G3 state.
+	 */
+	if ((sig & MASK_ALL_POWER_GOOD) == 0) {
+		LOG_DBG("All power rails off, G3 state");
+		return SYS_POWER_STATE_G3;
+	}
+	/*
+	 * Not enough power rails up to read VW signals.
+	 * Force a shutdown.
+	 */
+	if ((sig & MASK_VW_POWER) != VALUE_VW_POWER) {
+		LOG_ERR("Not enough power signals on (%#x), forcing shutdown",
+			sig);
+		ap_power_force_shutdown(AP_POWER_SHUTDOWN_G3);
+		return SYS_POWER_STATE_G3;
+	}
+
+	/*
+	 * Enough power signals are up, so
+	 * wait for virtual wire signals to become available.
+	 * Not sure how long to wait? 5 seconds total.
+	 */
+	for (int delay = 0; delay < 500; k_msleep(10), delay++) {
+#if defined(CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S3)
+		if (power_signal_get(PWR_SLP_S3) < 0)
+			continue;
+#endif
+#if defined(CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S4)
+		if (power_signal_get(PWR_SLP_S4) < 0)
+			continue;
+#endif
+#if defined(CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S5)
+		if (power_signal_get(PWR_SLP_S5) < 0)
+			continue;
+#endif
+		/*
+		 * All signals valid.
+		 */
+		LOG_DBG("All VW signals valid after %d ms", delay * 10);
+		break;
+	}
+	/* Re-read the power signals */
+	sig = power_get_signals();
+
+	/*
+	 * S0, all power OK, no suspend or sleep on.
+	 */
+	if ((sig & MASK_S0) == VALUE_S0) {
+		LOG_DBG("CPU in S0 state");
+		return SYS_POWER_STATE_S0;
+	}
+	/*
+	 * S3, all power OK, PWR_SLP_S3 on.
+	 */
+	if ((sig & MASK_S3) == VALUE_S3) {
+		LOG_DBG("CPU in S3 state");
+		return SYS_POWER_STATE_S3;
+	}
+	/*
+	 * S5, some power signals on, PWR_SLP_S5 on.
+	 */
+	if ((sig & MASK_S5) == VALUE_S5) {
+		LOG_DBG("CPU in S5 state");
+		return SYS_POWER_STATE_S5;
+	}
+	/*
+	 * Unable to determine state, force to G3.
+	 */
+	LOG_INF("Unable to determine CPU state (%#x), forcing shutdown", sig);
+	ap_power_force_shutdown(AP_POWER_SHUTDOWN_G3);
+	return SYS_POWER_STATE_G3;
+}
+#else
+static void x86_non_dsx_chipset_state_entry_cb(const struct device *dev,
+					       const enum ap_pwrseq_state entry,
+					       const enum ap_pwrseq_state exit)
+{
+	switch (entry) {
+	case AP_POWER_STATE_G3:
+		if (exit >= AP_POWER_STATE_S5) {
+			ap_power_ev_send_callbacks(AP_POWER_HARD_OFF);
+		}
+		ap_power_ev_send_callbacks(AP_POWER_SHUTDOWN);
+		ap_power_ev_send_callbacks(AP_POWER_SHUTDOWN_COMPLETE);
+		break;
+
+	case AP_POWER_STATE_S3:
+		ap_power_ev_send_callbacks(AP_POWER_STARTUP);
+		break;
+
+	case AP_POWER_STATE_S0:
+		/* Notify power event rails are up */
+		ap_power_ev_send_callbacks(AP_POWER_RESUME);
+		break;
+
+#if CONFIG_AP_PWRSEQ_S0IX
+	case AP_POWER_STATE_S0IX:
+		ap_power_ev_send_callbacks(AP_POWER_S0IX_SUSPEND);
+#if CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK
+		ap_power_ev_send_callbacks(AP_POWER_SUSPEND_COMPLETE);
+#endif
+		break;
+#endif
+
+	default:
+		break;
+	}
+}
+
+static void x86_non_dsx_chipset_state_exit_cb(const struct device *dev,
+					      const enum ap_pwrseq_state entry,
+					      const enum ap_pwrseq_state exit)
+{
+	switch (exit) {
+	case AP_POWER_STATE_G3:
+		ap_power_ev_send_callbacks(AP_POWER_PRE_INIT);
+		break;
+
+	case AP_POWER_STATE_S3:
+#if CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK
+		if (entry == AP_POWER_STATE_S0) {
+			/* Notify power event before resume */
+			ap_power_ev_send_callbacks(AP_POWER_RESUME_INIT);
+		}
+#endif
+		break;
+
+	case AP_POWER_STATE_S0:
+		ap_power_ev_send_callbacks(AP_POWER_SUSPEND);
+#if CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK
+		if (entry == AP_POWER_STATE_S3) {
+			/* Notify power event after suspend */
+			ap_power_ev_send_callbacks(AP_POWER_SUSPEND_COMPLETE);
+		}
+#endif
+		break;
+
+#if CONFIG_AP_PWRSEQ_S0IX
+	case AP_POWER_STATE_S0IX:
+#if CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK
+		ap_power_ev_send_callbacks(AP_POWER_RESUME_INIT);
+#endif
+		ap_power_ev_send_callbacks(AP_POWER_S0IX_RESUME);
+		break;
+#endif
+
+	default:
+		break;
+	}
+}
+
+static int x86_non_dsx_chipset_init_events(void)
+{
+	static struct ap_pwrseq_state_callback ap_pwrseq_entry_cb;
+	static struct ap_pwrseq_state_callback ap_pwrseq_exit_cb;
+	const struct device *ap_pwrseq_dev = ap_pwrseq_get_instance();
+
+	power_signal_init();
+
+	ap_pwrseq_entry_cb.cb = x86_non_dsx_chipset_state_entry_cb;
+	ap_pwrseq_entry_cb.states_bit_mask =
+		(BIT(AP_POWER_STATE_G3) | BIT(AP_POWER_STATE_S3) |
+		 BIT(AP_POWER_STATE_S0)
+#if CONFIG_AP_PWRSEQ_S0IX
+		 | BIT(AP_POWER_STATE_S0IX)
+#endif
+		);
+
+	ap_pwrseq_register_state_entry_callback(ap_pwrseq_dev,
+						&ap_pwrseq_entry_cb);
+
+	ap_pwrseq_exit_cb.cb = x86_non_dsx_chipset_state_exit_cb;
+	ap_pwrseq_exit_cb.states_bit_mask =
+		(BIT(AP_POWER_STATE_G3) | BIT(AP_POWER_STATE_S3) |
+		 BIT(AP_POWER_STATE_S0)
+#if CONFIG_AP_PWRSEQ_S0IX
+		 | BIT(AP_POWER_STATE_S0IX)
+#endif
+		);
+
+	ap_pwrseq_register_state_exit_callback(ap_pwrseq_dev,
+					       &ap_pwrseq_exit_cb);
+
+	ap_power_ev_send_callbacks(AP_POWER_INITIALIZED);
+
+	return 0;
+}
+SYS_INIT(x86_non_dsx_chipset_init_events, APPLICATION,
+	 CONFIG_APPLICATION_INIT_PRIORITY);
+
+enum ap_pwrseq_state chipset_pwr_seq_get_state(void)
+{
+	power_signal_mask_t sig;
+
+	sig = power_get_signals();
+	/*
+	 * Chip is shut down, G3 state.
+	 */
+	if ((sig & MASK_ALL_POWER_GOOD) == 0) {
+		LOG_DBG("All power rails off, G3 state");
+		return AP_POWER_STATE_G3;
+	}
+	/*
+	 * Not enough power rails up to read VW signals.
+	 * Force a shutdown.
+	 */
+	if ((sig & MASK_VW_POWER) != VALUE_VW_POWER) {
+		LOG_ERR("Not enough power signals on (%#x), forcing shutdown",
+			sig);
+		ap_power_force_shutdown(AP_POWER_SHUTDOWN_G3);
+		return AP_POWER_STATE_G3;
+	}
+
+	/*
+	 * Enough power signals are up, so
+	 * wait for virtual wire signals to become available.
+	 * Not sure how long to wait? 5 seconds total.
+	 */
+	for (int delay = 0; delay < 500; k_msleep(10), delay++) {
+#if defined(CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S3)
+		if (power_signal_get(PWR_SLP_S3) < 0)
+			continue;
+#endif
+#if defined(CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S4)
+		if (power_signal_get(PWR_SLP_S4) < 0)
+			continue;
+#endif
+#if defined(CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S5)
+		if (power_signal_get(PWR_SLP_S5) < 0)
+			continue;
+#endif
+		/*
+		 * All signals valid.
+		 */
+		LOG_DBG("All VW signals valid after %d ms", delay * 10);
+		break;
+	}
+	/* Re-read the power signals */
+	sig = power_get_signals();
+
+	/*
+	 * S0, all power OK, no suspend or sleep on.
+	 */
+	if ((sig & MASK_S0) == VALUE_S0) {
+		LOG_DBG("CPU in S0 state");
+		return AP_POWER_STATE_S0;
+	}
+	/*
+	 * S3, all power OK, PWR_SLP_S3 on.
+	 */
+	if ((sig & MASK_S3) == VALUE_S3) {
+		LOG_DBG("CPU in S3 state");
+		return AP_POWER_STATE_S3;
+	}
+	/*
+	 * S5, some power signals on, PWR_SLP_S5 on.
+	 */
+	if ((sig & MASK_S5) == VALUE_S5) {
+		LOG_DBG("CPU in S5 state");
+		return AP_POWER_STATE_S5;
+	}
+	/*
+	 * Unable to determine state, force to G3.
+	 */
+	LOG_INF("Unable to determine CPU state (%#x), forcing shutdown", sig);
+	ap_power_force_shutdown(AP_POWER_SHUTDOWN_G3);
+	return AP_POWER_STATE_G3;
+}
+#endif /* CONFIG_AP_PWRSEQ_DRIVER */
diff --git a/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_console.c b/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_console.c
new file mode 100644
index 0000000000..a31d9e3f3a
--- /dev/null
+++ b/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_console.c
@@ -0,0 +1,89 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <stdlib.h>
+
+#include <zephyr/shell/shell.h>
+
+#include <x86_non_dsx_common_pwrseq_sm_handler.h>
+
+LOG_MODULE_DECLARE(ap_pwrseq, CONFIG_AP_PWRSEQ_LOG_LEVEL);
+
+/* Console commands */
+static int powerinfo_handler(const struct shell *shell, size_t argc,
+			     char **argv)
+{
+#ifndef CONFIG_AP_PWRSEQ_DRIVER
+	enum power_states_ndsx state = pwr_sm_get_state();
+#else
+	const struct device *dev = ap_pwrseq_get_instance();
+	enum ap_pwrseq_state state = ap_pwrseq_get_current_state(dev);
+#endif
+
+	shell_fprintf(shell, SHELL_INFO, "power state %d = %s, in 0x%04x\n",
+		      state, pwr_sm_get_state_name(state), power_get_signals());
+	return 0;
+}
+
+SHELL_CMD_REGISTER(powerinfo, NULL, NULL, powerinfo_handler);
+
+static int powerindebug_handler(const struct shell *shell, size_t argc,
+				char **argv)
+{
+	int i;
+	char *e;
+	power_signal_mask_t current;
+
+	/* If one arg, set the mask */
+	if (argc == 2) {
+		int m = strtol(argv[1], &e, 0);
+
+		if (*e)
+			return -EINVAL;
+
+		power_set_debug(m);
+	}
+
+	/* Print the mask */
+	current = power_get_signals();
+	shell_fprintf(shell, SHELL_INFO, "power in:   0x%05x\n", current);
+	shell_fprintf(shell, SHELL_INFO, "debug mask: 0x%05x\n",
+		      power_get_debug());
+
+	/* Print the decode */
+	shell_fprintf(shell, SHELL_INFO, "bit meanings:\n");
+	for (i = 0; i < POWER_SIGNAL_COUNT; i++) {
+		power_signal_mask_t mask = POWER_SIGNAL_MASK(i);
+		bool valid = (power_signal_get(i) >= 0);
+
+		shell_fprintf(shell, SHELL_INFO, "  0x%05x %d%s %s\n", mask,
+			      (current & mask) ? 1 : 0, valid ? " " : "!",
+			      power_signal_name(i));
+	}
+
+	return 0;
+};
+
+SHELL_CMD_REGISTER(powerindebug, NULL, "[mask] Get/set power input debug mask",
+		   powerindebug_handler);
+
+static int apshutdown_handler(const struct shell *shell, size_t argc,
+			      char **argv)
+{
+	ap_power_force_shutdown(AP_POWER_SHUTDOWN_CONSOLE_CMD);
+	return 0;
+}
+
+SHELL_CMD_REGISTER(apshutdown, NULL, NULL, apshutdown_handler);
+
+static int apreset_handler(const struct shell *shell, size_t argc, char **argv)
+{
+	ap_power_reset(AP_POWER_SHUTDOWN_CONSOLE_CMD);
+	return 0;
+}
+
+SHELL_CMD_REGISTER(apreset, NULL, NULL, apreset_handler);
+
+/* End of console commands */
diff --git a/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_host_command.c b/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_host_command.c
new file mode 100644
index 0000000000..ee6e2cf41e
--- /dev/null
+++ b/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_host_command.c
@@ -0,0 +1,92 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <x86_non_dsx_common_pwrseq_sm_handler.h>
+
+/* Host commands */
+static enum ec_status
+host_command_reboot_ap_on_g3(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_reboot_ap_on_g3_v1 *cmd = args->params;
+
+	/* Store request for processing at g3 */
+	request_start_from_g3();
+
+	switch (args->version) {
+	case 0:
+		break;
+	case 1:
+		/* Store user specified delay to wait in G3 state */
+		set_start_from_g3_delay_seconds(cmd->reboot_ap_at_g3_delay);
+		break;
+	default:
+		return EC_RES_INVALID_PARAM;
+	}
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_REBOOT_AP_ON_G3, host_command_reboot_ap_on_g3,
+		     EC_VER_MASK(0) | EC_VER_MASK(1));
+
+#if CONFIG_AP_PWRSEQ_HOST_SLEEP
+/* Track last reported sleep event */
+static enum host_sleep_event host_sleep_state;
+
+static enum ec_status
+host_command_host_sleep_event(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_host_sleep_event_v1 *p = args->params;
+	struct ec_response_host_sleep_event_v1 *r = args->response;
+	struct host_sleep_event_context ctx;
+	enum host_sleep_event state = p->sleep_event;
+
+	host_sleep_state = state;
+	ctx.sleep_transitions = 0;
+	switch (state) {
+	case HOST_SLEEP_EVENT_S0IX_SUSPEND:
+	case HOST_SLEEP_EVENT_S3_SUSPEND:
+	case HOST_SLEEP_EVENT_S3_WAKEABLE_SUSPEND:
+		ctx.sleep_timeout_ms = EC_HOST_SLEEP_TIMEOUT_DEFAULT;
+
+		/* The original version contained only state. */
+		if (args->version >= 1)
+			ctx.sleep_timeout_ms =
+				p->suspend_params.sleep_timeout_ms;
+
+		break;
+
+	default:
+		break;
+	}
+
+	ap_power_chipset_handle_host_sleep_event(host_sleep_state, &ctx);
+	switch (state) {
+	case HOST_SLEEP_EVENT_S0IX_RESUME:
+	case HOST_SLEEP_EVENT_S3_RESUME:
+		if (args->version >= 1) {
+			r->resume_response.sleep_transitions =
+				ctx.sleep_transitions;
+
+			args->response_size = sizeof(*r);
+		}
+
+		break;
+
+	default:
+		break;
+	}
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_HOST_SLEEP_EVENT, host_command_host_sleep_event,
+		     EC_VER_MASK(0) | EC_VER_MASK(1));
+
+void power_set_host_sleep_state(enum host_sleep_event state)
+{
+	host_sleep_state = state;
+}
+#endif /* CONFIG_AP_PWRSEQ_HOST_SLEEP */
+
+/* End of host commands */
diff --git a/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_host_sleep.c b/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_host_sleep.c
new file mode 100644
index 0000000000..550e414ed0
--- /dev/null
+++ b/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_host_sleep.c
@@ -0,0 +1,191 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <ap_power_host_sleep.h>
+#include <x86_non_dsx_common_pwrseq_sm_handler.h>
+
+static uint16_t sleep_signal_timeout;
+static uint16_t host_sleep_timeout_default = CONFIG_SLEEP_TIMEOUT_MS;
+static uint32_t sleep_signal_transitions;
+static enum sleep_hang_type timeout_hang_type;
+
+static void sleep_transition_timeout(struct k_work *work);
+
+static K_WORK_DELAYABLE_DEFINE(sleep_transition_timeout_data,
+			       sleep_transition_timeout);
+
+/**
+ * Type of sleep hang detected
+ */
+enum sleep_hang_type {
+	SLEEP_HANG_NONE,
+	SLEEP_HANG_S0IX_SUSPEND,
+	SLEEP_HANG_S0IX_RESUME
+};
+
+void power_chipset_handle_sleep_hang(enum sleep_hang_type hang_type)
+{
+	/*
+	 * Wake up the AP so they don't just chill in a non-suspended state and
+	 * burn power. Overload a vaguely related event bit since event bits are
+	 * at a premium. If the system never entered S0ix, then manually set the
+	 * wake mask to pretend it did, so that the hang detect event wakes the
+	 * system.
+	 */
+#ifndef CONFIG_AP_PWRSEQ_DRIVER
+	if (pwr_sm_get_state() == SYS_POWER_STATE_S0) {
+		host_event_t sleep_wake_mask;
+
+		ap_power_get_lazy_wake_mask(SYS_POWER_STATE_S0ix,
+					    &sleep_wake_mask);
+		lpc_set_host_event_mask(LPC_HOST_EVENT_WAKE, sleep_wake_mask);
+	}
+#else
+	const struct device *dev = ap_pwrseq_get_instance();
+
+	if (ap_pwrseq_get_current_state(dev) == AP_POWER_STATE_S0) {
+		host_event_t sleep_wake_mask;
+
+		ap_power_get_lazy_wake_mask(AP_POWER_STATE_S0IX,
+					    &sleep_wake_mask);
+		lpc_set_host_event_mask(LPC_HOST_EVENT_WAKE, sleep_wake_mask);
+	}
+#endif
+
+	ccprintf("Warning: Detected sleep hang! Waking host up!");
+	host_set_single_event(EC_HOST_EVENT_HANG_DETECT);
+}
+
+static void sleep_transition_timeout(struct k_work *work)
+{
+	/* Mark the timeout. */
+	sleep_signal_transitions |= EC_HOST_RESUME_SLEEP_TIMEOUT;
+	k_work_cancel_delayable(&sleep_transition_timeout_data);
+
+	if (timeout_hang_type != SLEEP_HANG_NONE) {
+		power_chipset_handle_sleep_hang(timeout_hang_type);
+	}
+}
+
+static void sleep_increment_transition(void)
+{
+	if ((sleep_signal_transitions & EC_HOST_RESUME_SLEEP_TRANSITIONS_MASK) <
+	    EC_HOST_RESUME_SLEEP_TRANSITIONS_MASK)
+		sleep_signal_transitions += 1;
+}
+
+void sleep_suspend_transition(void)
+{
+	sleep_increment_transition();
+	k_work_cancel_delayable(&sleep_transition_timeout_data);
+}
+
+void sleep_resume_transition(void)
+{
+	sleep_increment_transition();
+
+	/*
+	 * Start the timer again to ensure the AP doesn't get itself stuck in
+	 * a state where it's no longer in a sleep state (S0ix/S3), but from
+	 * the Linux perspective is still suspended. Perhaps a bug in the SoC-
+	 * internal periodic housekeeping code might result in a situation
+	 * like this.
+	 */
+	if (sleep_signal_timeout) {
+		timeout_hang_type = SLEEP_HANG_S0IX_RESUME;
+		k_work_schedule(&sleep_transition_timeout_data,
+				K_MSEC(sleep_signal_timeout));
+	}
+}
+
+void sleep_start_suspend(void)
+{
+	uint16_t timeout = host_get_sleep_timeout();
+
+	sleep_signal_transitions = 0;
+
+	/* Use 0xFFFF to disable the timeout */
+	if (timeout == EC_HOST_SLEEP_TIMEOUT_INFINITE) {
+		sleep_signal_timeout = 0;
+		return;
+	}
+
+	/* Use zero internally to indicate host doesn't set timeout value;
+	 * we will use default timeout.
+	 */
+	if (timeout == EC_HOST_SLEEP_TIMEOUT_DEFAULT) {
+		timeout = host_sleep_timeout_default;
+	}
+
+	sleep_signal_timeout = timeout;
+	timeout_hang_type = SLEEP_HANG_S0IX_SUSPEND;
+	k_work_schedule(&sleep_transition_timeout_data, K_MSEC(timeout));
+}
+
+void sleep_complete_resume(void)
+{
+	/*
+	 * Ensure we don't schedule another sleep_transition_timeout
+	 * if the the HOST_SLEEP_EVENT_S0IX_RESUME message arrives before
+	 * the CHIPSET task transitions to the POWER_S0ixS0 state.
+	 */
+	sleep_signal_timeout = 0;
+	k_work_cancel_delayable(&sleep_transition_timeout_data);
+	host_set_sleep_transitions(sleep_signal_transitions);
+}
+
+void sleep_reset_tracking(void)
+{
+	sleep_signal_transitions = 0;
+	sleep_signal_timeout = 0;
+	timeout_hang_type = SLEEP_HANG_NONE;
+}
+
+/*
+ * s0ix event handler.
+ */
+static void ap_power_sleep_event_handler(struct ap_power_ev_callback *cb,
+					 struct ap_power_ev_data data)
+{
+	switch (data.event) {
+	case AP_POWER_S0IX_SUSPEND_START:
+		sleep_start_suspend();
+		break;
+	case AP_POWER_S0IX_SUSPEND:
+		sleep_suspend_transition();
+		break;
+	case AP_POWER_S0IX_RESUME:
+		sleep_resume_transition();
+		break;
+	case AP_POWER_S0IX_RESUME_COMPLETE:
+		sleep_complete_resume();
+		break;
+	case AP_POWER_S0IX_RESET_TRACKING:
+		sleep_reset_tracking();
+		break;
+	default:
+		break;
+	}
+}
+
+/*
+ * Registers callback for s0ix events.
+ */
+static int ap_power_sleep_s0ix_event(void)
+{
+	static struct ap_power_ev_callback cb;
+
+	/*
+	 * Register for all events.
+	 */
+	ap_power_ev_init_callback(
+		&cb, ap_power_sleep_event_handler,
+		AP_POWER_S0IX_SUSPEND_START | AP_POWER_S0IX_SUSPEND |
+			AP_POWER_S0IX_RESUME | AP_POWER_S0IX_RESUME_COMPLETE |
+			AP_POWER_S0IX_RESET_TRACKING);
+	ap_power_ev_add_callback(&cb);
+	return 0;
+}
+SYS_INIT(ap_power_sleep_s0ix_event, APPLICATION, 1);
diff --git a/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c b/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c
new file mode 100644
index 0000000000..b66b43347b
--- /dev/null
+++ b/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c
@@ -0,0 +1,784 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "system_boot_time.h"
+#include "zephyr_console_shim.h"
+
+#include <zephyr/init.h>
+
+#include <atomic.h>
+#ifndef CONFIG_AP_PWRSEQ_DRIVER
+#include <x86_non_dsx_common_pwrseq_sm_handler.h>
+#else
+#include "ap_power/ap_pwrseq.h"
+#include "ap_power/ap_pwrseq_sm.h"
+#include "x86_non_dsx_common_pwrseq_sm_handler.h"
+#include "zephyr_console_shim.h"
+#endif
+
+/* Delay in ms when starting from G3 */
+static uint32_t start_from_g3_delay_ms;
+
+#ifdef CONFIG_AP_PWRSEQ_DEBUG_MODE_COMMAND
+static bool in_debug_mode;
+#endif
+
+/*
+ * Flags, may be set/cleared from other threads.
+ */
+enum {
+	S5_INACTIVE_TIMER_RUNNING,
+	START_FROM_G3,
+	FLAGS_MAX,
+};
+static ATOMIC_DEFINE(flags, FLAGS_MAX);
+
+#ifndef CONFIG_AP_PWRSEQ_DRIVER
+static K_KERNEL_STACK_DEFINE(pwrseq_thread_stack, CONFIG_AP_PWRSEQ_STACK_SIZE);
+static struct k_thread pwrseq_thread_data;
+static struct pwrseq_context pwrseq_ctx = {
+	.power_state = SYS_POWER_STATE_UNINIT,
+};
+static struct k_sem pwrseq_sem;
+
+static void s5_inactive_timer_handler(struct k_timer *timer);
+/* S5 inactive timer*/
+K_TIMER_DEFINE(s5_inactive_timer, s5_inactive_timer_handler, NULL);
+
+LOG_MODULE_REGISTER(ap_pwrseq, CONFIG_AP_PWRSEQ_LOG_LEVEL);
+
+/**
+ * @brief power_state names for debug
+ */
+static const char *const pwrsm_dbg[] = {
+	[SYS_POWER_STATE_UNINIT] = "Unknown",
+	[SYS_POWER_STATE_G3] = "G3",
+	[SYS_POWER_STATE_S5] = "S5",
+	[SYS_POWER_STATE_S4] = "S4",
+	[SYS_POWER_STATE_S3] = "S3",
+#if CONFIG_AP_PWRSEQ_S0IX
+	[SYS_POWER_STATE_S0ix] = "S0ix",
+#endif
+	[SYS_POWER_STATE_S0] = "S0",
+	[SYS_POWER_STATE_G3S5] = "G3S5",
+	[SYS_POWER_STATE_S5S4] = "S5S4",
+	[SYS_POWER_STATE_S4S3] = "S4S3",
+	[SYS_POWER_STATE_S3S0] = "S3S0",
+	[SYS_POWER_STATE_S5G3] = "S5G3",
+	[SYS_POWER_STATE_S4S5] = "S4S5",
+	[SYS_POWER_STATE_S3S4] = "S3S4",
+	[SYS_POWER_STATE_S0S3] = "S0S3",
+#if CONFIG_AP_PWRSEQ_S0IX
+	[SYS_POWER_STATE_S0ixS0] = "S0ixS0",
+	[SYS_POWER_STATE_S0S0ix] = "S0S0ix",
+#endif
+};
+#else
+static void x86_non_dsx_timer_handler(struct k_timer *timer);
+
+K_TIMER_DEFINE(x86_non_dsx_timer, x86_non_dsx_timer_handler, NULL);
+
+LOG_MODULE_DECLARE(ap_pwrseq, CONFIG_AP_PWRSEQ_LOG_LEVEL);
+#endif /* CONFIG_AP_PWRSEQ_DRIVER */
+
+/*
+ * Returns true if all signals in mask are valid.
+ * This is only done for virtual wire signals.
+ */
+static inline bool signals_valid(power_signal_mask_t signals)
+{
+#if defined(CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S3)
+	if ((signals & POWER_SIGNAL_MASK(PWR_SLP_S3)) &&
+	    power_signal_get(PWR_SLP_S3) < 0)
+		return false;
+#endif
+#if defined(CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S4)
+	if ((signals & POWER_SIGNAL_MASK(PWR_SLP_S4)) &&
+	    power_signal_get(PWR_SLP_S4) < 0)
+		return false;
+#endif
+#if defined(CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S5)
+	if ((signals & POWER_SIGNAL_MASK(PWR_SLP_S5)) &&
+	    power_signal_get(PWR_SLP_S5) < 0)
+		return false;
+#endif
+	return true;
+}
+
+static inline bool signals_valid_and_on(power_signal_mask_t signals)
+{
+	return signals_valid(signals) && power_signals_on(signals);
+}
+
+static inline bool signals_valid_and_off(power_signal_mask_t signals)
+{
+	return signals_valid(signals) && power_signals_off(signals);
+}
+
+#ifndef CONFIG_AP_PWRSEQ_DRIVER
+enum power_states_ndsx pwr_sm_get_state(void)
+{
+	return pwrseq_ctx.power_state;
+}
+
+const char *const pwr_sm_get_state_name(enum power_states_ndsx state)
+{
+	return pwrsm_dbg[state];
+}
+
+void pwr_sm_set_state(enum power_states_ndsx new_state)
+{
+	/* Add locking mechanism if multiple thread can update it */
+	LOG_DBG("Power state: %s --> %s",
+		pwr_sm_get_state_name(pwrseq_ctx.power_state),
+		pwr_sm_get_state_name(new_state));
+	pwrseq_ctx.power_state = new_state;
+}
+
+void ap_pwrseq_wake(void)
+{
+	k_sem_give(&pwrseq_sem);
+}
+
+/*
+ * Set a flag to enable starting the AP once it is in G3.
+ * This is called from ap_power_exit_hardoff() which checks
+ * to ensure that the AP is in S5 or G3 state before calling
+ * this function.
+ * It can also be called via a hostcmd, which allows the flag
+ * to be set in any AP state.
+ */
+void request_start_from_g3(void)
+{
+	LOG_INF("Request start from G3");
+	atomic_set_bit(flags, START_FROM_G3);
+	/*
+	 * If in S5, restart the timer to give the CPU more time
+	 * to respond to a power button press (which is presumably
+	 * why we are being called). This avoids having the S5
+	 * inactivity timer expiring before the AP can process
+	 * the power button press and start up.
+	 */
+	if (pwr_sm_get_state() == SYS_POWER_STATE_S5) {
+		atomic_clear_bit(flags, S5_INACTIVE_TIMER_RUNNING);
+	}
+	ap_pwrseq_wake();
+}
+
+static void s5_inactive_timer_handler(struct k_timer *timer)
+{
+	ap_pwrseq_wake();
+}
+
+static void shutdown_and_notify(enum ap_power_shutdown_reason reason)
+{
+	ap_power_force_shutdown(reason);
+	ap_power_ev_send_callbacks(AP_POWER_SHUTDOWN);
+	ap_power_ev_send_callbacks(AP_POWER_SHUTDOWN_COMPLETE);
+}
+
+void apshutdown(void)
+{
+	if (pwr_sm_get_state() != SYS_POWER_STATE_G3) {
+		shutdown_and_notify(AP_POWER_SHUTDOWN_G3);
+		pwr_sm_set_state(SYS_POWER_STATE_G3);
+	}
+}
+#else
+const char *const pwr_sm_get_state_name(enum ap_pwrseq_state state)
+{
+	return ap_pwrseq_get_state_str(state);
+}
+
+static void x86_non_dsx_timer_handler(struct k_timer *timer)
+{
+	if (atomic_test_bit(flags, S5_INACTIVE_TIMER_RUNNING)) {
+		ap_pwrseq_post_event(ap_pwrseq_get_instance(),
+				     AP_PWRSEQ_EVENT_POWER_TIMEOUT);
+	} else if (atomic_test_bit(flags, START_FROM_G3)) {
+		ap_pwrseq_post_event(ap_pwrseq_get_instance(),
+				     AP_PWRSEQ_EVENT_POWER_STARTUP);
+	}
+}
+
+void request_start_from_g3(void)
+{
+	const struct device *dev = ap_pwrseq_get_instance();
+
+	LOG_INF("Request start from G3");
+	/*
+	 * If in S5, restart the timer to give the CPU more time
+	 * to respond to a power button press (which is presumably
+	 * why we are being called). This avoids having the S5
+	 * inactivity timer expiring before the AP can process
+	 * the power button press and start up.
+	 */
+	if (ap_pwrseq_get_current_state(dev) == AP_POWER_STATE_S5 &&
+	    AP_PWRSEQ_DT_VALUE(s5_inactivity_timeout)) {
+		k_timer_start(
+			&x86_non_dsx_timer,
+			K_SECONDS(AP_PWRSEQ_DT_VALUE(s5_inactivity_timeout)),
+			K_NO_WAIT);
+		return;
+	}
+
+	atomic_set_bit(flags, START_FROM_G3);
+	if (ap_pwrseq_get_current_state(dev) == AP_POWER_STATE_G3) {
+		if (start_from_g3_delay_ms) {
+			k_timer_start(&x86_non_dsx_timer,
+				      K_MSEC(start_from_g3_delay_ms),
+				      K_NO_WAIT);
+			start_from_g3_delay_ms = 0;
+		} else {
+			ap_pwrseq_post_event(dev,
+					     AP_PWRSEQ_EVENT_POWER_STARTUP);
+		}
+	}
+}
+
+void apshutdown(void)
+{
+	const struct device *dev = ap_pwrseq_get_instance();
+
+	ap_pwrseq_state_lock(dev);
+
+	if (ap_pwrseq_get_current_state(dev) != AP_POWER_STATE_G3) {
+		ap_power_force_shutdown(AP_POWER_SHUTDOWN_G3);
+	}
+
+	ap_pwrseq_state_unlock(dev);
+}
+#endif /* CONFIG_AP_PWRSEQ_DRIVER */
+
+void ap_power_force_shutdown(enum ap_power_shutdown_reason reason)
+{
+#ifdef CONFIG_AP_PWRSEQ_DEBUG_MODE_COMMAND
+	/* This prevents force shutdown if debug mode is enabled */
+	if (in_debug_mode) {
+		LOG_WRN("debug_mode is enabled, preventing force shutdown");
+		return;
+	}
+#endif /* CONFIG_AP_PWRSEQ_DEBUG_MODE_COMMAND */
+	board_ap_power_force_shutdown();
+}
+
+void set_start_from_g3_delay_seconds(uint32_t d_time)
+{
+	start_from_g3_delay_ms = d_time * MSEC;
+}
+
+void ap_power_reset(enum ap_power_shutdown_reason reason)
+{
+	/*
+	 * Irrespective of cold_reset value, always toggle SYS_RESET_L to
+	 * perform an AP reset. RCIN# which was used earlier to trigger
+	 * a warm reset is known to not work in certain cases where the CPU
+	 * is in a bad state (crbug.com/721853).
+	 *
+	 * The EC cannot control warm vs cold reset of the AP using
+	 * SYS_RESET_L; it's more of a request.
+	 */
+	LOG_DBG("%s: %d", __func__, reason);
+
+	/*
+	 * Toggling SYS_RESET_L will not have any impact when it's already
+	 * low (i,e. AP is in reset state).
+	 */
+	if (power_signal_get(PWR_SYS_RST)) {
+		LOG_DBG("Chipset is in reset state");
+		return;
+	}
+
+	power_signal_set(PWR_SYS_RST, 1);
+	/*
+	 * Debounce time for SYS_RESET_L is 16 ms. Wait twice that period
+	 * to be safe.
+	 */
+	k_msleep(AP_PWRSEQ_DT_VALUE(sys_reset_delay));
+	power_signal_set(PWR_SYS_RST, 0);
+	ap_power_ev_send_callbacks(AP_POWER_RESET);
+}
+
+/* Check RSMRST is fine to move from S5 to higher state */
+int rsmrst_power_is_good(void)
+{
+	/* TODO: Check if this is still intact */
+	return power_signal_get(PWR_RSMRST);
+}
+
+/* Handling RSMRST signal is mostly common across x86 chipsets */
+void rsmrst_pass_thru_handler(void)
+{
+	/* Handle RSMRST passthrough */
+	/* TODO: Add additional conditions for RSMRST handling */
+	int in_sig_val = power_signal_get(PWR_RSMRST);
+	int out_sig_val = power_signal_get(PWR_EC_PCH_RSMRST);
+
+	if (in_sig_val != out_sig_val) {
+		if (in_sig_val)
+			k_msleep(AP_PWRSEQ_DT_VALUE(rsmrst_delay));
+		LOG_DBG("Setting PWR_EC_PCH_RSMRST to %d", in_sig_val);
+		power_signal_set(PWR_EC_PCH_RSMRST, in_sig_val);
+		update_ap_boot_time(RSMRST);
+	}
+}
+
+#ifndef CONFIG_AP_PWRSEQ_DRIVER
+/* Common power sequencing */
+static int common_pwr_sm_run(int state)
+{
+	switch (state) {
+	case SYS_POWER_STATE_G3:
+		/*
+		 * If the START_FROM_G3 flag is set, begin starting
+		 * the AP. There may be a delay set, so only start
+		 * after that delay.
+		 */
+		if (atomic_test_and_clear_bit(flags, START_FROM_G3)) {
+			LOG_INF("Starting from G3, delay %d ms",
+				start_from_g3_delay_ms);
+			k_msleep(start_from_g3_delay_ms);
+			start_from_g3_delay_ms = 0;
+
+			if (!board_ap_power_is_startup_ok()) {
+				LOG_INF("Start from G3 inhibited"
+					" by !is_startup_ok");
+				break;
+			}
+			return SYS_POWER_STATE_G3S5;
+		}
+
+		break;
+
+	case SYS_POWER_STATE_G3S5:
+		if ((power_get_signals() & PWRSEQ_G3S5_UP_SIGNAL) ==
+		    PWRSEQ_G3S5_UP_VALUE)
+			return SYS_POWER_STATE_S5;
+		else
+			return SYS_POWER_STATE_S5G3;
+
+	case SYS_POWER_STATE_S5:
+		/* In S5 make sure no more signal lost */
+		/* If A-rails are stable then move to higher state */
+		if (board_ap_power_check_power_rails_enabled() &&
+		    rsmrst_power_is_good()) {
+			/* rsmrst is intact */
+			rsmrst_pass_thru_handler();
+			if (signals_valid_and_off(IN_PCH_SLP_S5)) {
+				k_timer_stop(&s5_inactive_timer);
+				/* Clear the timer running flag */
+				atomic_clear_bit(flags,
+						 S5_INACTIVE_TIMER_RUNNING);
+				/* Clear any request to exit hard-off */
+				atomic_clear_bit(flags, START_FROM_G3);
+				LOG_INF("Clearing request to exit G3");
+				return SYS_POWER_STATE_S5S4;
+			}
+		}
+		/*
+		 * S5 state has an inactivity timer, so moving
+		 * to S5G3 (where the power rails are turned off) is
+		 * delayed for some time, usually ~10 seconds or so.
+		 * The purpose of this delay is:
+		 *  - to handle AP initiated cold boot, where the AP
+		 *    will go to S5 for a short time and then restart.
+		 *  - give time for the power button to be pressed,
+		 *    which may set the START_FROM_G3 flag.
+		 */
+		if (AP_PWRSEQ_DT_VALUE(s5_inactivity_timeout) == 0)
+			return SYS_POWER_STATE_S5G3;
+		else if (AP_PWRSEQ_DT_VALUE(s5_inactivity_timeout) > 0) {
+			/*
+			 * Test and set timer running flag.
+			 * If it was 0, then the timer wasn't running
+			 * and it is started (and the flag is set),
+			 * otherwise it is already set, so no change.
+			 */
+			if (!atomic_test_and_set_bit(
+				    flags, S5_INACTIVE_TIMER_RUNNING)) {
+				/*
+				 * Timer is not started, or needs
+				 * restarting.
+				 */
+				k_timer_start(&s5_inactive_timer,
+					      K_SECONDS(AP_PWRSEQ_DT_VALUE(
+						      s5_inactivity_timeout)),
+					      K_NO_WAIT);
+			} else if (k_timer_status_get(&s5_inactive_timer) > 0) {
+				/* Timer is expired */
+				atomic_clear_bit(flags,
+						 S5_INACTIVE_TIMER_RUNNING);
+				return SYS_POWER_STATE_S5G3;
+			}
+		}
+		break;
+
+	case SYS_POWER_STATE_S5G3:
+		shutdown_and_notify(AP_POWER_SHUTDOWN_G3);
+		/* Notify power event before we enter G3 */
+		ap_power_ev_send_callbacks(AP_POWER_HARD_OFF);
+		return SYS_POWER_STATE_G3;
+
+	case SYS_POWER_STATE_S5S4:
+		/* Check if the PCH has come out of suspend state */
+		if (rsmrst_power_is_good()) {
+			LOG_DBG("RSMRST is ok");
+			return SYS_POWER_STATE_S4;
+		}
+		LOG_DBG("RSMRST is not ok");
+		return SYS_POWER_STATE_S5;
+
+	case SYS_POWER_STATE_S4:
+		if (signals_valid_and_on(IN_PCH_SLP_S5) ||
+		    !rsmrst_power_is_good())
+			return SYS_POWER_STATE_S4S5;
+		else if (signals_valid_and_off(IN_PCH_SLP_S4))
+			return SYS_POWER_STATE_S4S3;
+
+		break;
+
+	case SYS_POWER_STATE_S4S3:
+		if (!power_signals_on(IN_PGOOD_ALL_CORE)) {
+			/* Required rail went away */
+			shutdown_and_notify(AP_POWER_SHUTDOWN_POWERFAIL);
+			return SYS_POWER_STATE_G3;
+		}
+
+		/* Notify power event that rails are up */
+		ap_power_ev_send_callbacks(AP_POWER_STARTUP);
+
+#if CONFIG_AP_PWRSEQ_S0IX
+		/*
+		 * Clearing the S0ix flag on the path to S0
+		 * to handle any reset conditions.
+		 */
+		ap_power_reset_host_sleep_state();
+#endif
+		return SYS_POWER_STATE_S3;
+
+	case SYS_POWER_STATE_S3:
+		/* AP is out of suspend to RAM */
+		if (!rsmrst_power_is_good()) {
+			LOG_WRN("RSMRST De-asserted");
+			return SYS_POWER_STATE_S3S4;
+		}
+		if (!power_signals_on(IN_PGOOD_ALL_CORE)) {
+			/* Required rail went away, go straight to S5 */
+			shutdown_and_notify(AP_POWER_SHUTDOWN_POWERFAIL);
+			return SYS_POWER_STATE_G3;
+		} else if (signals_valid_and_off(IN_PCH_SLP_S3))
+			return SYS_POWER_STATE_S3S0;
+		else if (signals_valid_and_on(IN_PCH_SLP_S4))
+			return SYS_POWER_STATE_S3S4;
+
+		break;
+
+	case SYS_POWER_STATE_S3S0:
+		if (!power_signals_on(IN_PGOOD_ALL_CORE)) {
+			shutdown_and_notify(AP_POWER_SHUTDOWN_POWERFAIL);
+			return SYS_POWER_STATE_G3;
+		}
+
+		/* All the power rails must be stable */
+		if (power_signal_get(PWR_ALL_SYS_PWRGD)) {
+			/*
+			 * Disable idle task deep sleep when in S0.
+			 */
+			disable_sleep(SLEEP_MASK_AP_RUN);
+#if CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK
+			/* Notify power event before resume */
+			ap_power_ev_send_callbacks(AP_POWER_RESUME_INIT);
+#endif
+			/* Notify power event rails are up */
+			ap_power_ev_send_callbacks(AP_POWER_RESUME);
+			return SYS_POWER_STATE_S0;
+		}
+		break;
+
+#if CONFIG_AP_PWRSEQ_S0IX
+	case SYS_POWER_STATE_S0ix:
+		/* System in S0 only if SLP_S0 and SLP_S3 are de-asserted */
+		if (power_signals_off(IN_PCH_SLP_S0) &&
+		    signals_valid_and_off(IN_PCH_SLP_S3)) {
+			/* TODO: Make sure ap reset handling is done
+			 * before leaving S0ix.
+			 */
+			return SYS_POWER_STATE_S0ixS0;
+		} else if (!power_signals_on(IN_PGOOD_ALL_CORE))
+			return SYS_POWER_STATE_S0;
+
+		break;
+
+	case SYS_POWER_STATE_S0S0ix:
+		/*
+		 * Check sleep state and notify listeners of S0ix suspend if
+		 * HC already set sleep suspend state.
+		 */
+		ap_power_sleep_notify_transition(AP_POWER_SLEEP_SUSPEND);
+		ap_power_ev_send_callbacks(AP_POWER_S0IX_SUSPEND);
+
+		/*
+		 * Enable idle task deep sleep. Allow the low power idle task
+		 * to go into deep sleep in S0ix.
+		 */
+		enable_sleep(SLEEP_MASK_AP_RUN);
+
+#if CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK
+		ap_power_ev_send_callbacks(AP_POWER_SUSPEND_COMPLETE);
+#endif
+
+		return SYS_POWER_STATE_S0ix;
+
+	case SYS_POWER_STATE_S0ixS0:
+		/*
+		 * Disable idle task deep sleep. This means that the low
+		 * power idle task will not go into deep sleep while in S0.
+		 */
+		disable_sleep(SLEEP_MASK_AP_RUN);
+
+		ap_power_ev_send_callbacks(AP_POWER_S0IX_RESUME
+#if CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK
+					   | AP_POWER_RESUME_INIT
+#endif
+		);
+
+		return SYS_POWER_STATE_S0;
+
+#endif /* CONFIG_AP_PWRSEQ_S0IX */
+
+	case SYS_POWER_STATE_S0:
+		if (!power_signals_on(IN_PGOOD_ALL_CORE)) {
+			shutdown_and_notify(AP_POWER_SHUTDOWN_POWERFAIL);
+			return SYS_POWER_STATE_G3;
+		} else if (signals_valid_and_on(IN_PCH_SLP_S3)) {
+			return SYS_POWER_STATE_S0S3;
+
+#if CONFIG_AP_PWRSEQ_S0IX
+			/*
+			 * SLP_S0 may assert in system idle scenario without a
+			 * kernel freeze call. This may cause interrupt storm
+			 * since there is no freeze/unfreeze of threads/process
+			 * in the idle scenario. Ignore the SLP_S0 assertions in
+			 * idle scenario by checking the host sleep state.
+			 */
+		} else if (ap_power_sleep_get_notify() ==
+				   AP_POWER_SLEEP_SUSPEND &&
+			   power_signals_on(IN_PCH_SLP_S0)) {
+			return SYS_POWER_STATE_S0S0ix;
+		} else if (ap_power_sleep_get_notify() ==
+			   AP_POWER_SLEEP_RESUME) {
+			ap_power_sleep_notify_transition(AP_POWER_SLEEP_RESUME);
+#endif /* CONFIG_AP_PWRSEQ_S0IX */
+		}
+
+		break;
+
+	case SYS_POWER_STATE_S4S5:
+		/* Notify power event before we remove power rails */
+		ap_power_ev_send_callbacks(AP_POWER_SHUTDOWN);
+
+		/*
+		 * If support controlling power of wifi/WWAN/BT devices
+		 * add handling here.
+		 */
+
+		/* Nofity power event after we remove power rails */
+		ap_power_ev_send_callbacks(AP_POWER_SHUTDOWN_COMPLETE);
+
+		/* Always enter into S5 state. The S5 state is required to
+		 * correctly handle global resets which have a bit of delay
+		 * while the SLP_Sx_L signals are asserted then deasserted.
+		 */
+		/* TODO */
+		/* power_s5_up = 0; */
+
+		return SYS_POWER_STATE_S5;
+
+	case SYS_POWER_STATE_S3S4:
+		return SYS_POWER_STATE_S4;
+
+	case SYS_POWER_STATE_S0S3:
+		/* Notify power event before we remove power rails */
+		ap_power_ev_send_callbacks(AP_POWER_SUSPEND);
+#if CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK
+		/* Notify power event after suspend */
+		ap_power_ev_send_callbacks(AP_POWER_SUSPEND_COMPLETE);
+#endif
+
+		/*
+		 * Enable idle task deep sleep. Allow the low power idle task
+		 * to go into deep sleep in S3 or lower.
+		 */
+		enable_sleep(SLEEP_MASK_AP_RUN);
+
+#if CONFIG_AP_PWRSEQ_S0IX
+		/* Re-initialize S0ix flag */
+		ap_power_reset_host_sleep_state();
+#endif
+
+		return SYS_POWER_STATE_S3;
+
+	default:
+		break;
+	}
+
+	return state;
+}
+
+/*
+ * Determine the current CPU state and ensure it
+ * is matching what is required.
+ */
+static void pwr_seq_set_initial_state(void)
+{
+	uint32_t reset_flags = system_get_reset_flags();
+	/* Determine current state using chipset specific handler */
+	enum power_states_ndsx state = chipset_pwr_seq_get_state();
+
+	/*
+	 * Not in warm boot, but CPU is not shutdown.
+	 */
+	if (((reset_flags & EC_RESET_FLAG_SYSJUMP) == 0) &&
+	    (state != SYS_POWER_STATE_G3)) {
+		ap_power_force_shutdown(AP_POWER_SHUTDOWN_G3);
+		state = SYS_POWER_STATE_G3;
+	}
+	pwr_sm_set_state(state);
+}
+
+static void pwrseq_loop_thread(void *p1, void *p2, void *p3)
+{
+	enum power_states_ndsx curr_state, new_state;
+	power_signal_mask_t this_in_signals;
+	power_signal_mask_t last_in_signals = 0;
+	enum power_states_ndsx last_state = -1;
+
+	/*
+	 * Let clients know that the AP power state is now
+	 * initialized and ready.
+	 */
+	ap_power_ev_send_callbacks(AP_POWER_INITIALIZED);
+	while (1) {
+		curr_state = pwr_sm_get_state();
+
+		/*
+		 * In order to prevent repeated console spam, only print the
+		 * current power state if something has actually changed.  It's
+		 * possible that one of the power signals goes away briefly and
+		 * comes back by the time we update our signals.
+		 */
+		this_in_signals = power_get_signals();
+
+		if (this_in_signals != last_in_signals ||
+		    curr_state != last_state) {
+			LOG_INF("power state %d = %s, in 0x%04x", curr_state,
+				pwr_sm_get_state_name(curr_state),
+				this_in_signals);
+			last_in_signals = this_in_signals;
+			last_state = curr_state;
+		}
+
+		/* Run chipset specific state machine */
+		new_state = chipset_pwr_sm_run(curr_state);
+
+		/*
+		 * Run common power state machine
+		 * if the state has changed in chipset state
+		 * machine then skip running common state
+		 * machine
+		 */
+		if (curr_state == new_state)
+			new_state = common_pwr_sm_run(curr_state);
+
+		if (curr_state != new_state) {
+			pwr_sm_set_state(new_state);
+			ap_power_set_active_wake_mask();
+		} else {
+			/*
+			 * No state transition, we can go to sleep and wait
+			 * for any event to wake us up.
+			 */
+			k_sem_take(&pwrseq_sem, K_FOREVER);
+		}
+	}
+}
+
+static inline void create_pwrseq_thread(void)
+{
+	k_thread_create(&pwrseq_thread_data, pwrseq_thread_stack,
+			K_KERNEL_STACK_SIZEOF(pwrseq_thread_stack),
+			(k_thread_entry_t)pwrseq_loop_thread, NULL, NULL, NULL,
+			CONFIG_AP_PWRSEQ_THREAD_PRIORITY, 0,
+			IS_ENABLED(CONFIG_AP_PWRSEQ_AUTOSTART) ? K_NO_WAIT :
+								 K_FOREVER);
+
+	k_thread_name_set(&pwrseq_thread_data, "pwrseq_task");
+}
+
+void ap_pwrseq_task_start(void)
+{
+	if (!IS_ENABLED(CONFIG_AP_PWRSEQ_AUTOSTART)) {
+		k_thread_start(&pwrseq_thread_data);
+	}
+}
+
+static void init_pwr_seq_state(void)
+{
+	atomic_clear_bit(flags, START_FROM_G3);
+	/*
+	 * The state of the CPU needs to be determined now
+	 * so that init routines can check the state of
+	 * the CPU.
+	 */
+	pwr_seq_set_initial_state();
+}
+
+/* Initialize power sequence system state */
+static int pwrseq_init(void)
+{
+	LOG_INF("Pwrseq Init");
+
+	k_sem_init(&pwrseq_sem, 0, 1);
+	/* Initialize signal handlers */
+	power_signal_init();
+	LOG_DBG("Init pwr seq state");
+	init_pwr_seq_state();
+	/* Create power sequence state handler core function thread */
+	create_pwrseq_thread();
+	return 0;
+}
+
+/*
+ * The initialization must occur after system I/O initialization that
+ * the signals depend upon, such as GPIO, ADC etc.
+ */
+SYS_INIT(pwrseq_init, APPLICATION, CONFIG_APPLICATION_INIT_PRIORITY);
+#endif /* CONFIG_AP_PWRSEQ_DRIVER */
+
+#ifdef CONFIG_AP_PWRSEQ_DEBUG_MODE_COMMAND
+/*
+ * Intel debugger puts SOC in boot halt mode for step debugging,
+ * during this time EC may lose Sx lines, Adding this console
+ * command to avoid force shutdown.
+ */
+static int disable_force_shutdown(int argc, const char **argv)
+{
+	if (argc > 1) {
+		if (!strcmp(argv[1], "enable")) {
+			in_debug_mode = true;
+		} else if (!strcmp(argv[1], "disable")) {
+			in_debug_mode = false;
+		} else {
+			return EC_ERROR_PARAM1;
+		}
+	}
+	LOG_INF("debug_mode = %s", (in_debug_mode ? "enabled" : "disabled"));
+
+	return EC_SUCCESS;
+}
+
+DECLARE_CONSOLE_COMMAND(debug_mode, disable_force_shutdown, "[enable|disable]",
+			"Prevents force shutdown if enabled");
+#endif /* CONFIG_AP_PWRSEQ_DEBUG_MODE_COMMAND */
diff --git a/zephyr/subsys/ap_pwrseq/x86_non_dsx_mtl_pwrseq_sm.c b/zephyr/subsys/ap_pwrseq/x86_non_dsx_mtl_pwrseq_sm.c
new file mode 100644
index 0000000000..80fa06e454
--- /dev/null
+++ b/zephyr/subsys/ap_pwrseq/x86_non_dsx_mtl_pwrseq_sm.c
@@ -0,0 +1,59 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <x86_non_dsx_common_pwrseq_sm_handler.h>
+
+LOG_MODULE_DECLARE(ap_pwrseq, CONFIG_AP_PWRSEQ_LOG_LEVEL);
+
+static void ap_off(void)
+{
+	power_signal_set(PWR_PCH_PWROK, 0);
+	power_signal_set(PWR_EC_PCH_SYS_PWROK, 0);
+}
+
+/* Generate SYS_PWROK->SOC if needed by system */
+static void generate_pwrok_handler(void)
+{
+	int all_sys_pwrgd_in;
+
+	if (power_signal_get(PWR_EC_PCH_SYS_PWROK) == 0) {
+		k_msleep(AP_PWRSEQ_DT_VALUE(sys_pwrok_delay));
+	}
+
+	all_sys_pwrgd_in = power_signal_get(PWR_ALL_SYS_PWRGD);
+	/* Loop through all PWROK signals defined by the board */
+	if (all_sys_pwrgd_in == 0) {
+		LOG_DBG("PG_EC_ALL_SYS_PWRGD deasserted, "
+			"shutting AP off!");
+		ap_off();
+		return;
+	}
+
+	power_signal_set(PWR_EC_PCH_SYS_PWROK, all_sys_pwrgd_in);
+	/* PCH_PWROK is set to combined result of ALL_SYS_PWRGD and SLP_S3 */
+	power_signal_set(PWR_PCH_PWROK,
+			 all_sys_pwrgd_in && !power_signal_get(PWR_SLP_S3));
+}
+
+/* Chipset specific power state machine handler */
+enum power_states_ndsx chipset_pwr_sm_run(enum power_states_ndsx curr_state)
+{
+	/* Add chipset specific state handling if any */
+	switch (curr_state) {
+	case SYS_POWER_STATE_G3S5:
+		board_ap_power_action_g3_s5();
+		break;
+	case SYS_POWER_STATE_S0S3:
+		ap_off();
+		break;
+	case SYS_POWER_STATE_S0:
+		/* Send SYS_PWROK->SoC if conditions met */
+		generate_pwrok_handler();
+		break;
+	default:
+		break;
+	}
+	return curr_state;
+}
diff --git a/zephyr/subsys/emul/CMakeLists.txt b/zephyr/subsys/emul/CMakeLists.txt
new file mode 100644
index 0000000000..3394afcc94
--- /dev/null
+++ b/zephyr/subsys/emul/CMakeLists.txt
@@ -0,0 +1,2 @@
+
+add_subdirectory("ap_pwrseq")
diff --git a/zephyr/subsys/emul/Kconfig b/zephyr/subsys/emul/Kconfig
new file mode 100644
index 0000000000..48011312d5
--- /dev/null
+++ b/zephyr/subsys/emul/Kconfig
@@ -0,0 +1,5 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+rsource "ap_pwrseq/Kconfig"
diff --git a/zephyr/subsys/emul/ap_pwrseq/CMakeLists.txt b/zephyr/subsys/emul/ap_pwrseq/CMakeLists.txt
new file mode 100644
index 0000000000..476232d13b
--- /dev/null
+++ b/zephyr/subsys/emul/ap_pwrseq/CMakeLists.txt
@@ -0,0 +1 @@
+zephyr_library_sources_ifdef(CONFIG_EMUL_POWER_SIGNALS  emul_power_signals.c)
diff --git a/zephyr/subsys/emul/ap_pwrseq/Kconfig b/zephyr/subsys/emul/ap_pwrseq/Kconfig
new file mode 100644
index 0000000000..309ee08eae
--- /dev/null
+++ b/zephyr/subsys/emul/ap_pwrseq/Kconfig
@@ -0,0 +1,34 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if ZTEST
+
+config EMUL_POWER_SIGNALS
+	bool "Enable Power Signals Emulator"
+	help
+	  Power signals emulator imitates the behavior of power signals
+	  that interact with the EC within a given platform. It enables testing
+	  AP Power Sequence execution in a virtual environment.
+
+if EMUL_POWER_SIGNALS
+
+module = EMUL_POWER_SIGNALS
+module-str = Power Signals Emulator
+source "subsys/logging/Kconfig.template.log_config"
+
+config EMUL_POWER_SIGNALS_WORK_QUEUE_STACK_SIZE
+	int "Power Signals Emulator internal work queue stack size"
+	default 1024
+	help
+	  Power Signal Emulator has its own dedicated work queue, this defines
+	  work queue thread stack size.
+
+config EMUL_POWER_SIGNALS_WORK_QUEUE_PRIO
+	int "Power Signals Emulator internal work queue thread priority"
+	default 0
+	help
+	  Defines work queue thread thread priority.
+
+endif # EMUL_POWER_SIGNALS
+endif # ZTEST
diff --git a/zephyr/subsys/emul/ap_pwrseq/emul_power_signals.c b/zephyr/subsys/emul/ap_pwrseq/emul_power_signals.c
new file mode 100644
index 0000000000..50a2becf21
--- /dev/null
+++ b/zephyr/subsys/emul/ap_pwrseq/emul_power_signals.c
@@ -0,0 +1,593 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ap_power/ap_power.h"
+#include "ap_power/ap_power_events.h"
+#include "chipset.h"
+#include "emul/emul_power_signals.h"
+#include "power_signals.h"
+#include "test_state.h"
+
+#include <zephyr/drivers/adc.h>
+#include <zephyr/drivers/espi.h>
+#include <zephyr/drivers/espi_emul.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/ztest.h>
+
+LOG_MODULE_REGISTER(emul_power_signal, CONFIG_EMUL_POWER_SIGNALS_LOG_LEVEL);
+
+/**
+ * @brief Power signal source type.
+ */
+enum power_signal_emul_source {
+	PWR_SIG_EMUL_SRC_GPIO,
+	PWR_SIG_EMUL_SRC_VW,
+	PWR_SIG_EMUL_SRC_EXT,
+	PWR_SIG_EMUL_SRC_ADC,
+};
+
+struct wv_dt_spec {
+	enum espi_vwire_signal espi_signal;
+	bool invert;
+};
+
+/**
+ * @brief Power signal containers definition.
+ */
+union power_signal_emul_signal_spec {
+	struct gpio_dt_spec gpio;
+	struct adc_dt_spec adc;
+	struct wv_dt_spec vw;
+};
+
+/**
+ * @brief Power signal descriptor.
+ */
+struct power_signal_emul_signal_desc {
+	const enum power_signal enum_id;
+	const char *name;
+	const enum power_signal_emul_source source;
+	const union power_signal_emul_signal_spec spec;
+};
+
+/**
+ * @brief Power signal output definition.
+ */
+struct power_signal_emul_output {
+	struct power_signal_emul_signal_desc desc;
+	const int assert_value;
+	const int assert_delay_ms;
+	const int deassert_value;
+	const int deassert_delay_ms;
+	const int init_value;
+	const bool initialized;
+	const bool invert;
+	struct k_work_delayable d_work;
+	int value;
+};
+
+enum power_signal_edge {
+	EDGE_ACTIVE_ON_ASSERT,
+	EDGE_ACTIVE_ON_DEASSERT,
+	EDGE_ACTIVE_ON_BOTH,
+};
+
+/**
+ * @brief Power signal input definition.
+ */
+struct power_signal_emul_input {
+	struct power_signal_emul_signal_desc desc;
+	const int assert_value;
+	const int init_value;
+	const bool initialized;
+	const enum power_signal_edge edge;
+	struct gpio_callback cb;
+	int value;
+};
+
+/**
+ * @brief Power signal node definition,
+ *        One node contains at least one input signal and one or more output
+ *        signals.
+ */
+struct power_signal_emul_node {
+	const char *name;
+	struct power_signal_emul_input input;
+	const int outputs_count;
+	struct power_signal_emul_output *const outputs;
+};
+
+#define VW_DT_SPEC_GET(id)                                              \
+	{                                                               \
+		.espi_signal = DT_STRING_UPPER_TOKEN(id, virtual_wire), \
+		.invert = DT_PROP(id, vw_invert),                       \
+	}
+
+#define EMUL_POWER_SIGNAL_GET_SOURCE(inst)                                    \
+	COND_CODE_1(                                                          \
+		DT_NODE_HAS_COMPAT(inst, intel_ap_pwrseq_gpio),               \
+		(PWR_SIG_EMUL_SRC_GPIO),                                      \
+		(COND_CODE_1(                                                 \
+			DT_NODE_HAS_COMPAT(inst, intel_ap_pwrseq_vw),         \
+			(PWR_SIG_EMUL_SRC_VW),                                \
+			(COND_CODE_1(DT_NODE_HAS_COMPAT(                      \
+					     inst, intel_ap_pwrseq_external), \
+				     (PWR_SIG_EMUL_SRC_EXT),                  \
+				     (PWR_SIG_EMUL_SRC_ADC))))))
+
+#define EMUL_POWER_SIGNAL_GET_SIGNAL_SPEC(inst, dir_signal)                    \
+	{                                                                      \
+		COND_CODE_1(DT_NODE_HAS_COMPAT(DT_PROP(inst, dir_signal),      \
+					       intel_ap_pwrseq_gpio),          \
+			    (.gpio = GPIO_DT_SPEC_GET(                         \
+				     DT_PROP(inst, dir_signal), gpios)),       \
+			    (COND_CODE_1(DT_NODE_HAS_COMPAT(                   \
+						 DT_PROP(inst, dir_signal),    \
+						 intel_ap_pwrseq_vw),          \
+					 (.vw = VW_DT_SPEC_GET(                \
+						  DT_PROP(inst, dir_signal))), \
+					 ())))                                 \
+	}
+
+#define EMUL_POWER_SIGNAL_GET_SIGNAL(inst, dir)                             \
+	{                                                                   \
+		.enum_id = PWR_SIGNAL_ENUM(DT_PROP(inst, dir)),             \
+		.name = DT_PROP(DT_PROP(inst, dir), enum_name),             \
+		.source = EMUL_POWER_SIGNAL_GET_SOURCE(DT_PROP(inst, dir)), \
+		.spec = EMUL_POWER_SIGNAL_GET_SIGNAL_SPEC(inst, dir),       \
+	}
+
+#define EMUL_POWER_SIGNAL_IN_DEF(inst)                                    \
+	{                                                                 \
+		.desc = EMUL_POWER_SIGNAL_GET_SIGNAL(inst, input_signal), \
+		.assert_value = DT_PROP(inst, assert_value),              \
+		.init_value = DT_PROP_OR(inst, init_value, 0),            \
+		.edge = DT_STRING_TOKEN(inst, edge),                      \
+		.initialized = DT_NODE_HAS_PROP(inst, init_value),        \
+	}
+
+#define EMUL_POWER_SIGNAL_OUT_DEF(inst)                                    \
+	{                                                                  \
+		.desc = EMUL_POWER_SIGNAL_GET_SIGNAL(inst, output_signal), \
+		.assert_value = DT_PROP(inst, assert_value),               \
+		.assert_delay_ms = DT_PROP(inst, assert_delay_ms),         \
+		.deassert_value = DT_PROP(inst, deassert_value),           \
+		.deassert_delay_ms = DT_PROP(inst, deassert_delay_ms),     \
+		.init_value = DT_PROP_OR(inst, init_value, 0),             \
+		.initialized = DT_NODE_HAS_PROP(inst, init_value),         \
+		.invert = DT_PROP(inst, invert_value),                     \
+	},
+
+#define EMUL_POWER_SIGNAL_OUT_ARRAY_DEF(inst)                                 \
+	static struct power_signal_emul_output DT_CAT(inst, _output)[] = {    \
+		DT_FOREACH_CHILD_STATUS_OKAY(inst, EMUL_POWER_SIGNAL_OUT_DEF) \
+	};
+
+#define EMUL_POWER_SIGNAL_GET_INPUT_ENUM(inst) ENUM_##inst##_OUTPUT,
+
+#define EMUL_POWER_SIGNAL_NODES_DEF(inst)                                      \
+	enum {                                                                 \
+		DT_FOREACH_CHILD_STATUS_OKAY(inst,                             \
+					     EMUL_POWER_SIGNAL_GET_INPUT_ENUM) \
+			DT_CAT(inst, _OUTPUT_COUNT),                           \
+	};                                                                     \
+	__COND_CODE(IS_EQ(DT_CAT(inst, _OUTPUT_COUNT), 0), (),                 \
+		    (EMUL_POWER_SIGNAL_OUT_ARRAY_DEF(inst)))                   \
+	static struct power_signal_emul_node DT_CAT(inst, _node) = {           \
+		.name = DT_NODE_FULL_NAME(inst),                               \
+		.input = EMUL_POWER_SIGNAL_IN_DEF(inst),                       \
+		.outputs_count = inst##_OUTPUT_COUNT,                          \
+		.outputs = __COND_CODE(IS_EQ(DT_CAT(inst, _OUTPUT_COUNT), 0),  \
+				       (NULL), (DT_CAT(inst, _output))),       \
+	};
+
+DT_FOREACH_STATUS_OKAY(intel_ap_pwr_signal_emul, EMUL_POWER_SIGNAL_NODES_DEF)
+
+#define EMUL_POWER_SIGNAL_NODES_ARRAY_GET_NODES_REFS_WITH_COMMA(inst) \
+	(&DT_CAT(inst, _node)),
+
+#define EMUL_POWER_SIGNAL_NODES_ARRAY_GET_NODES_REFS(inst) \
+	EMUL_POWER_SIGNAL_NODES_ARRAY_GET_NODES_REFS_WITH_COMMA(inst)
+
+#define EMUL_POWER_SIGNAL_NODES_ARRAY_GET_IO_SIGNALS(inst, prop, idx) \
+	EMUL_POWER_SIGNAL_NODES_ARRAY_GET_NODES_REFS(                 \
+		DT_PHANDLE_BY_IDX(inst, prop, idx))
+
+#define EMUL_POWER_SIGNAL_NODES_ARRAY_DEF(inst)                          \
+	static struct power_signal_emul_node *DT_CAT(inst, _nodes)[] = { \
+		DT_FOREACH_PROP_ELEM(                                    \
+			inst, nodes,                                     \
+			EMUL_POWER_SIGNAL_NODES_ARRAY_GET_IO_SIGNALS)    \
+	};
+
+DT_FOREACH_STATUS_OKAY(intel_ap_pwr_test_platform,
+		       EMUL_POWER_SIGNAL_NODES_ARRAY_DEF)
+
+#define EMUL_POWER_SIGNAL_TEST_PLATFORM_GET_NODES_REFS_ITEM(inst) \
+	DT_CAT(inst, _nodes),
+
+#define EMUL_POWER_SIGNAL_TEST_PLATFORM_GET_NODES_REFS(inst) \
+	EMUL_POWER_SIGNAL_TEST_PLATFORM_GET_NODES_REFS_ITEM(inst)
+
+#define EMUL_POWER_SIGNAL_TEST_PLATFORM_GET_IO_SIGNALS(inst, prop, idx) \
+	EMUL_POWER_SIGNAL_TEST_PLATFORM_GET_NODES_REFS(                 \
+		DT_PHANDLE_BY_IDX(inst, prop, idx))
+
+#define EMUL_POWER_SIGNAL_TEST_PLATFORM_GET_NODES(inst)                 \
+	{                                                               \
+		DT_FOREACH_PROP_ELEM(                                   \
+			inst, nodes,                                    \
+			EMUL_POWER_SIGNAL_TEST_PLATFORM_GET_IO_SIGNALS) \
+	}
+
+#define EMUL_POWER_SIGNAL_TEST_PLATFORM_DEF(inst)             \
+	const struct power_signal_emul_test_platform inst = { \
+		.name_id = DT_NODE_FULL_NAME(inst),           \
+		.nodes_count = DT_PROP_LEN(inst, nodes),      \
+		.nodes = DT_CAT(inst, _nodes),                \
+	};
+
+DT_FOREACH_STATUS_OKAY(intel_ap_pwr_test_platform,
+		       EMUL_POWER_SIGNAL_TEST_PLATFORM_DEF)
+
+static K_KERNEL_STACK_DEFINE(work_q_stack,
+			     CONFIG_EMUL_POWER_SIGNALS_WORK_QUEUE_STACK_SIZE);
+
+struct k_work_q work_q;
+
+static const struct power_signal_emul_test_platform *cur_test_platform;
+
+static bool emul_ready;
+
+/**
+ * @brief Set GPIO type power signal to specified value.
+ *
+ * @param spec Pointer to container for GPIO pin information specified in
+ *             devicetree.
+ * @param value Value to be set on GPIO.
+ */
+static void power_signal_emul_set_gpio_value(const struct gpio_dt_spec *spec,
+					     int value)
+{
+	gpio_flags_t gpio_flags;
+	int ret;
+
+	ret = gpio_emul_flags_get(spec->port, spec->pin, &gpio_flags);
+	zassert_ok(ret, "Getting GPIO flags!!");
+
+	if (gpio_flags & GPIO_INPUT) {
+		ret = gpio_emul_input_set(
+			spec->port, spec->pin,
+			gpio_flags & GPIO_ACTIVE_LOW ? !value : !!value);
+	} else if (gpio_flags & GPIO_OUTPUT) {
+		ret = gpio_pin_set(spec->port, spec->pin, value);
+	}
+	zassert_ok(ret, "Setting GPIO value!!");
+}
+
+/**
+ * @brief Set virtual wire type power signal to value.
+ *
+ * @param spec Pointer to container for virtual wire information specified in
+ *             devicetree.
+ * @param value Value to be set on virtual wire.
+ */
+static void power_signal_emul_set_vw_value(const struct wv_dt_spec *vw,
+					   int value)
+{
+	const struct device *espi =
+		DEVICE_DT_GET_ANY(zephyr_espi_emul_controller);
+
+	emul_espi_host_send_vw(espi, vw->espi_signal,
+			       vw->invert ? !value : !!value);
+}
+
+/**
+ * @brief Set power signal to specified value.
+ *
+ * @param desc Pointer to power signal descriptor.
+ * @param value Value to be set on power signal.
+ */
+static void
+power_signal_emul_set_value(struct power_signal_emul_signal_desc *desc,
+			    int value)
+{
+	LOG_DBG("Set Signal %s -> %d", desc->name, value);
+
+	switch (desc->source) {
+	case PWR_SIG_EMUL_SRC_GPIO:
+		power_signal_emul_set_gpio_value(&desc->spec.gpio, !!value);
+		break;
+
+	case PWR_SIG_EMUL_SRC_EXT:
+		zassert_ok(power_signal_set(desc->enum_id, value),
+			   "Setting %s Signal value!!", desc->name);
+		break;
+
+	case PWR_SIG_EMUL_SRC_VW:
+		power_signal_emul_set_vw_value(&desc->spec.vw, value);
+		break;
+
+	default:
+		zassert_unreachable("Undefined Signal %s!!", desc->name);
+	}
+	power_signal_interrupt(desc->enum_id, value);
+}
+
+/**
+ * @brief Get GPIO type power signal value.
+ *
+ * @param spec Pointer to container for GPIO pin information specified in
+ *             devicetree.
+ *
+ * @return GPIO type power signal value.
+ */
+static int power_signal_emul_get_gpio_value(const struct gpio_dt_spec *spec)
+{
+	gpio_flags_t gpio_flags;
+	int ret;
+
+	ret = gpio_emul_flags_get(spec->port, spec->pin, &gpio_flags);
+	zassert_ok(ret, "Getting GPIO flags!!");
+
+	if (gpio_flags & GPIO_INPUT) {
+		ret = gpio_pin_get(spec->port, spec->pin);
+	} else if (gpio_flags & GPIO_OUTPUT) {
+		ret = gpio_emul_output_get(spec->port, spec->pin);
+		ret = gpio_flags & GPIO_ACTIVE_LOW ? !ret : !!ret;
+	}
+
+	return ret;
+}
+
+/**
+ * @brief Get power signal value.
+ *
+ * @param desc Pointer to power signal descriptor.
+ *
+ * @return Power signal value.
+ */
+static int
+power_signal_emul_get_value(struct power_signal_emul_signal_desc *desc)
+{
+	int ret;
+
+	switch (desc->source) {
+	case PWR_SIG_EMUL_SRC_GPIO:
+		ret = power_signal_emul_get_gpio_value(&desc->spec.gpio);
+		break;
+
+	case PWR_SIG_EMUL_SRC_VW:
+		ret = power_signal_get(desc->enum_id);
+		break;
+
+	default:
+		ret = power_signal_get(desc->enum_id);
+		break;
+	}
+
+	return ret;
+}
+
+/**
+ * @brief Handle GPIO type power signal interrupt.
+ *
+ * @param port Pointer to GPIO device.
+ * @param cb Original struct gpio_callback owning this handler.
+ * @param pins Mask of pins that triggers the callback handler.
+ */
+static void emul_power_signal_gpio_interrupt(const struct device *port,
+					     struct gpio_callback *cb,
+					     gpio_port_pins_t pins)
+{
+	struct power_signal_emul_input *in_signal =
+		CONTAINER_OF(cb, struct power_signal_emul_input, cb);
+	struct power_signal_emul_node *node =
+		CONTAINER_OF(in_signal, struct power_signal_emul_node, input);
+	int value;
+	int delay;
+
+	value = power_signal_emul_get_value(&in_signal->desc);
+	if (value == in_signal->value) {
+		return;
+	}
+
+	in_signal->value = value;
+
+	if (!emul_ready) {
+		return;
+	}
+
+	if (in_signal->edge == EDGE_ACTIVE_ON_DEASSERT &&
+	    value == in_signal->assert_value) {
+		return;
+	} else if (in_signal->edge == EDGE_ACTIVE_ON_ASSERT &&
+		   value != in_signal->assert_value) {
+		return;
+	}
+
+	LOG_DBG("INT: Set Signal %s -> %d", in_signal->desc.name, value);
+	for (int i = 0; i < node->outputs_count; i++) {
+		struct power_signal_emul_output *out_signal = &node->outputs[i];
+
+		out_signal->value = (value == in_signal->assert_value) ^
+						    out_signal->invert ?
+					    out_signal->assert_value :
+					    out_signal->deassert_value;
+
+		delay = (value == in_signal->assert_value) ?
+				out_signal->assert_delay_ms :
+				out_signal->deassert_delay_ms;
+
+		LOG_DBG("INT: Delay Signal %s", out_signal->desc.name);
+		k_work_schedule_for_queue(&work_q, &out_signal->d_work,
+					  K_MSEC(delay));
+	}
+}
+
+/**
+ * @brief Handle power signal delayed work.
+ *
+ * This will set power signal value accordingly.
+ *
+ * @param work Pointer to work structure.
+ */
+static void emul_signal_work_hanlder(struct k_work *work)
+{
+	struct k_work_delayable *d_work = k_work_delayable_from_work(work);
+	struct power_signal_emul_output *out_signal =
+		CONTAINER_OF(d_work, struct power_signal_emul_output, d_work);
+
+	power_signal_emul_set_value(&out_signal->desc, out_signal->value);
+}
+
+/**
+ * @brief Initialize power signal emulator node.
+ *
+ * This will enable corresponding initiator power signal interruption and
+ * its handler's power signals work structures.
+ *
+ * @param node Pointer to node containing power signals.
+ */
+static int power_signal_init_node(struct power_signal_emul_node *node)
+{
+	struct power_signal_emul_input *in_signal = &node->input;
+	struct power_signal_emul_output *out_signal;
+
+	if (!node->outputs_count) {
+		LOG_ERR("Node does not have output signal!!");
+		return -EINVAL;
+	}
+
+	LOG_DBG("Initializing node: %s", node->name);
+	for (int i = 0; i < node->outputs_count; i++) {
+		out_signal = &node->outputs[i];
+
+		if (out_signal->initialized) {
+			power_signal_emul_set_value(&out_signal->desc,
+						    out_signal->init_value);
+			out_signal->value = out_signal->init_value;
+		} else {
+			out_signal->value =
+				power_signal_emul_get_value(&out_signal->desc);
+		}
+		k_work_init_delayable(&out_signal->d_work,
+				      emul_signal_work_hanlder);
+	}
+
+	if (in_signal->initialized) {
+		power_signal_emul_set_value(&in_signal->desc,
+					    in_signal->init_value);
+		in_signal->value = in_signal->init_value;
+	} else {
+		in_signal->value =
+			power_signal_emul_get_value(&in_signal->desc);
+	}
+	if (in_signal->desc.source == PWR_SIG_EMUL_SRC_GPIO) {
+		gpio_init_callback(&in_signal->cb,
+				   emul_power_signal_gpio_interrupt,
+				   BIT(in_signal->desc.spec.gpio.pin));
+
+		gpio_add_callback(in_signal->desc.spec.gpio.port,
+				  &in_signal->cb);
+
+		gpio_pin_interrupt_configure_dt(&in_signal->desc.spec.gpio,
+						GPIO_INT_EDGE_BOTH);
+	}
+	return 0;
+}
+
+/** See description in emul_power_signals.h */
+int power_signal_emul_load(
+	const struct power_signal_emul_test_platform *test_platform)
+{
+	int ret;
+
+	if (cur_test_platform) {
+		LOG_ERR("Power Signal Emulator Busy!!");
+		return -EBUSY;
+	}
+
+	cur_test_platform = test_platform;
+
+	LOG_DBG("Loading Emulator test: %s", cur_test_platform->name_id);
+
+	for (int i = 0; i < cur_test_platform->nodes_count; i++) {
+		ret = power_signal_init_node(cur_test_platform->nodes[i]);
+		if (ret) {
+			power_signal_emul_unload();
+			return ret;
+		}
+	}
+
+	emul_ready = true;
+	LOG_DBG("Loading Emulator test Done");
+	return 0;
+}
+
+/** See description in emul_power_signals.h */
+int power_signal_emul_unload(void)
+{
+	struct power_signal_emul_node *node;
+	struct power_signal_emul_output *out_signal;
+	struct power_signal_emul_input *in_signal;
+
+	if (!cur_test_platform) {
+		LOG_ERR("No Test Platform Loaded!!");
+		return -EINVAL;
+	}
+
+	emul_ready = false;
+	for (int i = 0; i < cur_test_platform->nodes_count; i++) {
+		node = cur_test_platform->nodes[i];
+		in_signal = &node->input;
+
+		if (in_signal->desc.source != PWR_SIG_EMUL_SRC_GPIO) {
+			/* Currently, Only output GPIO signals are supported */
+			continue;
+		}
+
+		for (int j = 0; j < node->outputs_count; j++) {
+			static struct k_work_sync work_sync;
+
+			out_signal = &node->outputs[j];
+			k_work_cancel_delayable_sync(&out_signal->d_work,
+						     &work_sync);
+		}
+		gpio_pin_interrupt_configure_dt(&in_signal->desc.spec.gpio,
+						GPIO_INT_DISABLE);
+		if (in_signal->cb.handler) {
+			gpio_remove_callback(in_signal->desc.spec.gpio.port,
+					     &in_signal->cb);
+		}
+	}
+	cur_test_platform = NULL;
+	return 0;
+}
+
+/**
+ * @brief Initialize power signal emulator internal work queue.
+ *
+ * @param dev Unused parameter.
+ *
+ * @return 0 Return success only.
+ */
+static int power_signal_emul_work_q_init(void)
+{
+	struct k_work_queue_config cfg = {
+		.name = "psignal_emul",
+		.no_yield = true,
+	};
+
+	k_work_queue_start(&work_q, work_q_stack,
+			   K_KERNEL_STACK_SIZEOF(work_q_stack),
+			   CONFIG_EMUL_POWER_SIGNALS_WORK_QUEUE_PRIO, &cfg);
+	return 0;
+}
+
+SYS_INIT(power_signal_emul_work_q_init, POST_KERNEL,
+	 CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
diff --git a/zephyr/test/.pylintrc b/zephyr/test/.pylintrc
new file mode 100644
index 0000000000..f4609e3781
--- /dev/null
+++ b/zephyr/test/.pylintrc
@@ -0,0 +1,27 @@
+[BASIC]
+additional-builtins=
+    here,
+    register_binman_project,
+    register_host_project,
+    register_host_test,
+    register_npcx_project,
+    register_raw_project,
+good-names=BUILD
+
+# cros lint doesn't inherit the pylintrc from the parent dir.
+# These settings are copied from platform/ec/pylintrc
+[MESSAGES CONTROL]
+
+disable=
+    bad-continuation,
+    bad-whitespace,
+    # These have nothing to do with black, they are just annoying
+    fixme,
+    too-many-arguments,
+    too-many-statements,
+    too-many-branches,
+    too-many-locals
+
+[format]
+
+string-quote=double
diff --git a/zephyr/test/accel_cal/CMakeLists.txt b/zephyr/test/accel_cal/CMakeLists.txt
new file mode 100644
index 0000000000..07c9ed8599
--- /dev/null
+++ b/zephyr/test/accel_cal/CMakeLists.txt
@@ -0,0 +1,24 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(accel_cal)
+
+# Ensure that we get the definitions from test_config.h
+zephyr_compile_definitions("TEST_ACCEL_CAL")
+
+# Include the local test directory for shimmed_test_tasks.h
+zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}")
+
+# Include test file and unit under test
+target_sources(app PRIVATE
+	"${PLATFORM_EC}/test/accel_cal.c"
+	"${PLATFORM_EC}/common/accel_cal.c"
+	"${PLATFORM_EC}/common/kasa.c"
+	"${PLATFORM_EC}/common/mat44.c"
+	"${PLATFORM_EC}/common/math_util.c"
+	"${PLATFORM_EC}/common/newton_fit.c"
+	"${PLATFORM_EC}/common/stillness_detector.c"
+	"${PLATFORM_EC}/common/vec3.c")
diff --git a/zephyr/test/accel_cal/boards/native_posix.overlay b/zephyr/test/accel_cal/boards/native_posix.overlay
new file mode 100644
index 0000000000..c4d4413ad7
--- /dev/null
+++ b/zephyr/test/accel_cal/boards/native_posix.overlay
@@ -0,0 +1,6 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <board-overlays/native_posix.dts>
diff --git a/zephyr/test/accel_cal/prj.conf b/zephyr/test/accel_cal/prj.conf
new file mode 100644
index 0000000000..20e6ee59bf
--- /dev/null
+++ b/zephyr/test/accel_cal/prj.conf
@@ -0,0 +1,8 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_ZTEST=y
+CONFIG_HAS_TEST_TASKS=y
+CONFIG_PLATFORM_EC=y
+CONFIG_CROS_EC=y
diff --git a/zephyr/test/accel_cal/shimmed_test_tasks.h b/zephyr/test/accel_cal/shimmed_test_tasks.h
new file mode 100644
index 0000000000..12f4c8dc22
--- /dev/null
+++ b/zephyr/test/accel_cal/shimmed_test_tasks.h
@@ -0,0 +1,6 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "accel_cal.tasklist"
diff --git a/zephyr/test/accel_cal/testcase.yaml b/zephyr/test/accel_cal/testcase.yaml
new file mode 100644
index 0000000000..73e5376374
--- /dev/null
+++ b/zephyr/test/accel_cal/testcase.yaml
@@ -0,0 +1,4 @@
+common:
+  platform_allow: native_posix
+tests:
+  accel_cal.default: {}
diff --git a/zephyr/test/amd/CMakeLists.txt b/zephyr/test/amd/CMakeLists.txt
new file mode 100644
index 0000000000..a46cb31520
--- /dev/null
+++ b/zephyr/test/amd/CMakeLists.txt
@@ -0,0 +1,11 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(amd)
+
+add_subdirectory(${PLATFORM_EC}/zephyr/test/test_utils test_utils)
+
+target_sources_ifdef(CONFIG_TEST_AMD_STB_DUMP app PRIVATE src/stb_dump.c)
\ No newline at end of file
diff --git a/zephyr/test/amd/Kconfig b/zephyr/test/amd/Kconfig
new file mode 100644
index 0000000000..e5fe04dee8
--- /dev/null
+++ b/zephyr/test/amd/Kconfig
@@ -0,0 +1,9 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config TEST_AMD_STB_DUMP
+	bool "Enable STB dump test"
+	select PLATFORM_EC_AMD_STB_DUMP
+
+source "Kconfig.zephyr"
diff --git a/zephyr/test/amd/boards/native_posix.overlay b/zephyr/test/amd/boards/native_posix.overlay
new file mode 100644
index 0000000000..477a989e1a
--- /dev/null
+++ b/zephyr/test/amd/boards/native_posix.overlay
@@ -0,0 +1,35 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <board-overlays/native_posix.dts>
+#include <dt-bindings/gpio_defines.h>
+
+/ {
+	named-gpios {
+		compatible = "named-gpios";
+
+		/* STB dumping GPIOs */
+		gpio_ec_sfh_int_h: ec_sfh_int_h {
+			gpios = <&gpio0 0 GPIO_OUTPUT_LOW>;
+		};
+		gpio_sfh_ec_int_h: sfh_ec_int_h {
+			gpios = <&gpio0 1 GPIO_INPUT>;
+		};
+	};
+
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_stb_dump: stb_dump {
+			irq-pin = <&gpio_sfh_ec_int_h>;
+			flags = <GPIO_INT_EDGE_RISING>;
+			handler = "amd_stb_dump_interrupt";
+		};
+	};
+};
+
+&gpio0 {
+	ngpios = <2>;
+};
\ No newline at end of file
diff --git a/zephyr/test/amd/prj.conf b/zephyr/test/amd/prj.conf
new file mode 100644
index 0000000000..36d99e8716
--- /dev/null
+++ b/zephyr/test/amd/prj.conf
@@ -0,0 +1,15 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_ZTEST=y
+CONFIG_ZTEST_ASSERT_VERBOSE=1
+CONFIG_ZTEST_NEW_API=y
+CONFIG_ASSERT=y
+
+CONFIG_CROS_EC=y
+CONFIG_PLATFORM_EC=y
+CONFIG_EMUL=y
+CONFIG_GPIO=y
+
+CONFIG_AP_X86_AMD=y
\ No newline at end of file
diff --git a/zephyr/test/amd/src/stb_dump.c b/zephyr/test/amd/src/stb_dump.c
new file mode 100644
index 0000000000..d05041c7dc
--- /dev/null
+++ b/zephyr/test/amd/src/stb_dump.c
@@ -0,0 +1,40 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/fff.h>
+#include <zephyr/ztest.h>
+
+#include <driver/amd_stb.h>
+#include <gpio.h>
+#include <gpio/gpio_int.h>
+
+ZTEST_SUITE(stb_dump, NULL, NULL, NULL, NULL, NULL);
+
+ZTEST(stb_dump, test_stb_dump)
+{
+	const struct gpio_dt_spec *ec_sfh_int =
+		GPIO_DT_FROM_NODELABEL(gpio_ec_sfh_int_h);
+	const struct gpio_dt_spec *sfh_ec_int =
+		GPIO_DT_FROM_NODELABEL(gpio_sfh_ec_int_h);
+	int rv;
+
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_stb_dump));
+	amd_stb_dump_init(ec_sfh_int, sfh_ec_int);
+
+	amd_stb_dump_trigger();
+	rv = gpio_emul_output_get(ec_sfh_int->port, ec_sfh_int->pin);
+	zassert_equal(rv, 1);
+	zassert_true(amd_stb_dump_in_progress());
+
+	rv = gpio_emul_input_set(sfh_ec_int->port, sfh_ec_int->pin, true);
+	zassert_ok(rv);
+	/* Give the interrupt handler plenty of time to run. */
+	k_msleep(10);
+	zassert_false(amd_stb_dump_in_progress());
+	rv = gpio_emul_output_get(ec_sfh_int->port, ec_sfh_int->pin);
+	zassert_equal(rv, 0);
+}
diff --git a/zephyr/test/amd/testcase.yaml b/zephyr/test/amd/testcase.yaml
new file mode 100644
index 0000000000..f124f8d9e2
--- /dev/null
+++ b/zephyr/test/amd/testcase.yaml
@@ -0,0 +1,10 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+common:
+  platform_allow: native_posix
+tests:
+  amd.stb_dump:
+    extra_configs:
+      - CONFIG_TEST_AMD_STB_DUMP=y
diff --git a/zephyr/test/amd_power/CMakeLists.txt b/zephyr/test/amd_power/CMakeLists.txt
new file mode 100644
index 0000000000..0bbe26971d
--- /dev/null
+++ b/zephyr/test/amd_power/CMakeLists.txt
@@ -0,0 +1,16 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(amd_power)
+
+add_subdirectory(${PLATFORM_EC}/zephyr/test/test_utils test_utils)
+
+# Include the local test directory for shimmed_test_tasks.h
+zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}")
+zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}/include")
+
+FILE(GLOB_RECURSE test_sources src/*.c)
+target_sources(app PRIVATE ${test_sources})
diff --git a/zephyr/test/amd_power/Kconfig b/zephyr/test/amd_power/Kconfig
new file mode 100644
index 0000000000..581f3fc5d2
--- /dev/null
+++ b/zephyr/test/amd_power/Kconfig
@@ -0,0 +1,5 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+source "Kconfig.zephyr"
diff --git a/zephyr/test/amd_power/boards/native_posix.overlay b/zephyr/test/amd_power/boards/native_posix.overlay
new file mode 100644
index 0000000000..b29221aae6
--- /dev/null
+++ b/zephyr/test/amd_power/boards/native_posix.overlay
@@ -0,0 +1,158 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <board-overlays/native_posix.dts>
+#include <dt-bindings/gpio_defines.h>
+#include <cros/binman.dtsi>
+
+/ {
+	chosen {
+		cros-ec,espi = &espi0;
+		cros-ec,flash-controller = &cros_flash;
+	};
+	aliases {
+		gpio-wp = &gpio_wp_l;
+	};
+	cros_flash: cros-flash {
+		compatible = "cros-ec,flash-emul";
+	};
+
+	/*
+	 * Keep these GPIOs in pin order.
+	 * If you need to add one, make sure you increase
+	 * ngpios in the gpio0 node further down.
+	 *
+	 * Note that all outputs need to also be set as input pins to
+	 * read them from a test.
+	 */
+	named-gpios {
+		compatible = "named-gpios";
+
+		gpio_acok_od: acok_od {
+			gpios = <&gpio0 0 GPIO_INPUT>;
+			enum-name = "GPIO_AC_PRESENT";
+		};
+		ec_bl_disable_l {
+			gpios = <&gpio0 1 GPIO_INPUT>;
+			enum-name = "GPIO_ENABLE_BACKLIGHT";
+		};
+		gpio_slp_s3_l: slp_s3_l {
+			gpios = <&gpio0 2 GPIO_INPUT>;
+			enum-name = "GPIO_PCH_SLP_S3_L";
+			alias = "GPIO_PCH_SLP_S0_L";
+		};
+		gpio_slp_s5_l: slp_s5_l {
+			gpios = <&gpio0 3 GPIO_INPUT>;
+			enum-name = "GPIO_PCH_SLP_S5_L";
+		};
+		gpio_pg_pwr_s5: pg_pwr_s5 {
+			gpios = <&gpio0 4 GPIO_INPUT>;
+			enum-name = "GPIO_S5_PGOOD";
+		};
+		gpio_s0_pgood: s0_pgood {
+			gpios = <&gpio0 5 GPIO_INPUT>;
+			enum-name = "GPIO_S0_PGOOD";
+		};
+		gpio_en_pwr_s5: en_pwr_s5 {
+			gpios = <&gpio0 6 (GPIO_OUTPUT_LOW | GPIO_INPUT)>;
+			enum-name = "GPIO_EN_PWR_A";
+		};
+		gpio_wp_l: wp_l {
+			gpios = <&gpio0 7 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l {
+			gpios = <&gpio0 8 (GPIO_OUTPUT_LOW | GPIO_INPUT)>;
+			enum-name = "GPIO_PCH_RSMRST_L";
+		};
+		gpio_lid_open_ec: lid_open_ec {
+			/* GPIO_PULL_UP will cause this start asserted. */
+			gpios = <&gpio0 9 (GPIO_INPUT | GPIO_PULL_UP)>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+		gpio_mech_pwr_btn_odl: mech_pwr_btn_odl {
+			/* PULL_UP to start as not pressed */
+			gpios = <&gpio0 10 (GPIO_INPUT | GPIO_PULL_UP)>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		gpio_ec_soc_pwr_btn_l: ec_soc_pwr_btn_l {
+			gpios = <&gpio0 11 GPIO_OUTPUT_HIGH>;
+			enum-name = "GPIO_PCH_PWRBTN_L";
+		};
+		gpio_sys_rst_l: ec_sys_rst_l {
+			gpios = <&gpio0 12 GPIO_OUTPUT_HIGH>;
+			enum-name = "GPIO_SYS_RESET_L";
+		};
+		gpio_prochot_odl: prochot_odl {
+			gpios = <&gpio0 13 (GPIO_ODR_HIGH | GPIO_INPUT)>;
+			enum-name = "GPIO_CPU_PROCHOT";
+		};
+		pch-sys-prwok {
+			gpios = <&gpio0 14 (GPIO_OUTPUT_LOW | GPIO_INPUT)>;
+			enum-name = "GPIO_PCH_SYS_PWROK";
+		};
+		gpio_ec_pch_wake_odl: ec_soc_wake_l {
+			gpios = <&gpio0 15 GPIO_OUTPUT_HIGH>;
+		};
+		/* STB dumping GPIOs */
+		gpio_ec_sfh_int_h: ec_sfh_int_h {
+			gpios = <&gpio0 16 (GPIO_OUTPUT_LOW | GPIO_INPUT)>;
+		};
+		gpio_sfh_ec_int_h: sfh_ec_int_h {
+			gpios = <&gpio0 17 GPIO_INPUT>;
+		};
+	};
+
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_lid_open_ec: lid_open_ec {
+			irq-pin = <&gpio_lid_open_ec>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "lid_interrupt";
+		};
+		int_power_button: power_button {
+			irq-pin = <&gpio_mech_pwr_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_button_interrupt";
+		};
+		int_slp_s3: slp_s3 {
+			irq-pin = <&gpio_slp_s3_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_slp_s5: slp_s5 {
+			irq-pin = <&gpio_slp_s5_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_s5_pgood: s5_pgood {
+			irq-pin = <&gpio_pg_pwr_s5>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_s0_pgood: s0_pgood {
+			irq-pin = <&gpio_s0_pgood>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_stb_dump: stb_dump {
+			irq-pin = <&gpio_sfh_ec_int_h>;
+			flags = <GPIO_INT_EDGE_RISING>;
+			handler = "amd_stb_dump_interrupt";
+		};
+	};
+};
+
+&gpio0 {
+	ngpios = <18>;
+};
+
+&espi0 {
+	espi-host@0 {
+		status = "okay";
+		compatible = "zephyr,espi-emul-espi-host";
+		reg = <0x0>;
+	};
+};
diff --git a/zephyr/test/amd_power/prj.conf b/zephyr/test/amd_power/prj.conf
new file mode 100644
index 0000000000..05ca479f23
--- /dev/null
+++ b/zephyr/test/amd_power/prj.conf
@@ -0,0 +1,58 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_ASSERT=y
+CONFIG_TEST=y
+CONFIG_ZTEST=y
+CONFIG_ZTEST_ASSERT_VERBOSE=1
+CONFIG_ZTEST_MOCKING=y
+CONFIG_ZTEST_NEW_API=y
+
+CONFIG_INPUT=y
+
+# Print logs from Zephyr LOG_MODULE to stdout
+CONFIG_NATIVE_UART_0_ON_STDINOUT=y
+
+# Enable debugging features
+CONFIG_DEBUG=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_OPTIMIZATIONS=y
+CONFIG_PLATFORM_EC_CONSOLE_DEBUG=y
+CONFIG_SHELL_BACKEND_DUMMY=y
+
+CONFIG_CROS_EC=y
+CONFIG_EMUL=y
+CONFIG_FLASH=y
+CONFIG_GPIO=y
+CONFIG_GPIO_GET_CONFIG=y
+CONFIG_PLATFORM_EC=y
+CONFIG_RING_BUFFER=y
+CONFIG_SERIAL=y
+CONFIG_SHELL_BACKEND_DUMMY=y
+CONFIG_SHELL_BACKEND_DUMMY_BUF_SIZE=2000
+CONFIG_SHELL_BACKEND_SERIAL=n
+CONFIG_SHIMMED_TASKS=y
+
+CONFIG_ESPI=y
+CONFIG_EMUL_ESPI_HOST=y
+CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION=y
+CONFIG_ESPI_PERIPHERAL_CUSTOM_OPCODE=y
+CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD=y
+CONFIG_PLATFORM_EC_HOSTCMD=y
+CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK=y
+
+# AMD power sequencing
+CONFIG_AP_X86_AMD=y
+CONFIG_PLATFORM_EC_AMD_STB_DUMP=y
+CONFIG_PLATFORM_EC_EXTPOWER=y
+CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y
+CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI=y
+CONFIG_PLATFORM_EC_LID_SWITCH=y
+CONFIG_PLATFORM_EC_POWERSEQ=y
+CONFIG_PLATFORM_EC_POWERSEQ_S0IX=y
+CONFIG_PLATFORM_EC_POWERSEQ_HOST_SLEEP=y
+CONFIG_PLATFORM_EC_POWERSEQ_S0IX_COUNTER=y
+CONFIG_PLATFORM_EC_POWERSEQ_RSMRST_DELAY=y
+CONFIG_PLATFORM_EC_POWER_BUTTON=y
+CONFIG_PLATFORM_EC_POWER_SLEEP_FAILURE_DETECTION=y
diff --git a/zephyr/test/amd_power/src/amd_power.c b/zephyr/test/amd_power/src/amd_power.c
new file mode 100644
index 0000000000..8796a53921
--- /dev/null
+++ b/zephyr/test/amd_power/src/amd_power.c
@@ -0,0 +1,901 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "driver/amd_stb.h"
+#include "ec_app_main.h"
+#include "emul/emul_stub_device.h"
+#include "gpio.h"
+#include "gpio/gpio_int.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "include/power_button.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power/amd_x86.h"
+#include "task.h"
+
+#include <setjmp.h>
+
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/fff.h>
+#include <zephyr/input/input.h>
+#include <zephyr/kernel.h>
+#include <zephyr/shell/shell_dummy.h>
+#include <zephyr/ztest.h>
+
+#include <dt-bindings/buttons.h>
+
+void set_initial_pwrbtn_state(void);
+
+/* All emulated GPIOS are on one device */
+#define GPIO_DEVICE \
+	DEVICE_DT_GET(DT_GPIO_CTLR(NAMED_GPIOS_GPIO_NODE(s0_pgood), gpios))
+#define SLP_S3_PIN DT_GPIO_PIN(NAMED_GPIOS_GPIO_NODE(slp_s3_l), gpios)
+#define SLP_S5_PIN DT_GPIO_PIN(NAMED_GPIOS_GPIO_NODE(slp_s5_l), gpios)
+#define PGOOD_S0_PIN DT_GPIO_PIN(NAMED_GPIOS_GPIO_NODE(s0_pgood), gpios)
+#define PGOOD_S5_PIN DT_GPIO_PIN(NAMED_GPIOS_GPIO_NODE(pg_pwr_s5), gpios)
+#define PWRBTN_IN_PIN \
+	DT_GPIO_PIN(NAMED_GPIOS_GPIO_NODE(mech_pwr_btn_odl), gpios)
+#define PWRBTN_OUT_PIN \
+	DT_GPIO_PIN(NAMED_GPIOS_GPIO_NODE(ec_soc_pwr_btn_l), gpios)
+#define PROCHOT_PIN DT_GPIO_PIN(NAMED_GPIOS_GPIO_NODE(prochot_odl), gpios)
+#define LID_PIN DT_GPIO_PIN(NAMED_GPIOS_GPIO_NODE(lid_open_ec), gpios)
+#define STB_OUT_PIN DT_GPIO_PIN(NAMED_GPIOS_GPIO_NODE(ec_sfh_int_h), gpios)
+
+/*
+ * Provide standard array of power signals for the module based on our DTS enum
+ * names we filled in
+ */
+const struct power_signal_info power_signal_list[] = {
+	[X86_SLP_S3_N] = {
+		.gpio = GPIO_PCH_SLP_S3_L,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "SLP_S3_DEASSERTED",
+	},
+	[X86_SLP_S5_N] = {
+		.gpio = GPIO_PCH_SLP_S5_L,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "SLP_S5_DEASSERTED",
+	},
+	[X86_S0_PGOOD] = {
+		.gpio = GPIO_S0_PGOOD,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "S0_PGOOD",
+	},
+	[X86_S5_PGOOD] = {
+		.gpio = GPIO_S5_PGOOD,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "S5_PGOOD",
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
+
+struct hook_tracker {
+	int startup_count;
+	int resume_count;
+	int reset_count;
+	int suspend_count;
+	int shutdown_count;
+};
+
+static struct hook_tracker hook_counts;
+
+static void do_chipset_startup(void)
+{
+	hook_counts.startup_count++;
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, do_chipset_startup, HOOK_PRIO_DEFAULT);
+
+static void do_chipset_resume(void)
+{
+	hook_counts.resume_count++;
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, do_chipset_resume, HOOK_PRIO_DEFAULT);
+
+static void do_chipset_reset(void)
+{
+	hook_counts.reset_count++;
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESET, do_chipset_reset, HOOK_PRIO_DEFAULT);
+
+static void do_chipset_suspend(void)
+{
+	hook_counts.suspend_count++;
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, do_chipset_suspend, HOOK_PRIO_DEFAULT);
+
+static void do_chipset_shutdown(void)
+{
+	hook_counts.shutdown_count++;
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, do_chipset_shutdown, HOOK_PRIO_DEFAULT);
+
+FAKE_VALUE_FUNC(int, system_can_boot_ap);
+FAKE_VALUE_FUNC(int, system_jumped_to_this_image);
+FAKE_VALUE_FUNC(int, battery_wait_for_stable);
+int battery_is_present(void)
+{
+	return 1;
+}
+
+/**
+ * @brief FFF fakes that will be registered as a callback to monitor SYS reset
+ * and watch the power button output
+ * Implements `gpio_callback_handler_t`.
+ */
+FAKE_VOID_FUNC(interrupt_sys_reset_monitor, const struct device *,
+	       struct gpio_callback *, gpio_port_pins_t);
+FAKE_VOID_FUNC(interrupt_pwr_btn_monitor, const struct device *,
+	       struct gpio_callback *, gpio_port_pins_t);
+
+/**
+ * @brief Fixture to hold state while the suite is running.
+ */
+struct amd_power_fixture {
+	/** Configuration for the interrupt pin change callback */
+	struct gpio_callback callback_sys_reset;
+	struct gpio_callback callback_pwr_btn;
+
+	const struct gpio_dt_spec *sys_reset_pin;
+	const struct gpio_dt_spec *pwr_btn_pin;
+};
+
+static struct amd_power_fixture fixture;
+
+static void *amd_power_setup(void)
+{
+	/* STB dump GPIOs */
+	const struct gpio_dt_spec *gpio_ec_sfh_int_h =
+		GPIO_DT_FROM_NODELABEL(gpio_ec_sfh_int_h);
+	const struct gpio_dt_spec *gpio_sfh_ec_int_h =
+		GPIO_DT_FROM_NODELABEL(gpio_sfh_ec_int_h);
+
+	/* Add a callback for SYS reset so we can log edges */
+	fixture.sys_reset_pin = GPIO_DT_FROM_NODELABEL(gpio_sys_rst_l);
+	fixture.callback_sys_reset = (struct gpio_callback){
+		.pin_mask = BIT(fixture.sys_reset_pin->pin),
+		.handler = interrupt_sys_reset_monitor,
+	};
+
+	zassert_ok(gpio_add_callback(fixture.sys_reset_pin->port,
+				     &fixture.callback_sys_reset),
+		   "Could not configure GPIO callback.");
+
+	/* Add a power button edge callback */
+	fixture.pwr_btn_pin = GPIO_DT_FROM_NODELABEL(gpio_ec_soc_pwr_btn_l);
+	fixture.callback_pwr_btn = (struct gpio_callback){
+		.pin_mask = BIT(fixture.pwr_btn_pin->pin),
+		.handler = interrupt_pwr_btn_monitor,
+	};
+
+	zassert_ok(gpio_add_callback(fixture.pwr_btn_pin->port,
+				     &fixture.callback_pwr_btn),
+		   "Could not configure GPIO callback.");
+
+	/* Configure and enable STB dump */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_stb_dump));
+	amd_stb_dump_init(gpio_ec_sfh_int_h, gpio_sfh_ec_int_h);
+
+	return &fixture;
+}
+
+static void amd_power_teardown(void *data)
+{
+	/* Cleanup the GPIO callback on the interrupt pin */
+	struct amd_power_fixture *f = (struct amd_power_fixture *)data;
+
+	gpio_remove_callback(f->sys_reset_pin->port, &f->callback_sys_reset);
+	gpio_remove_callback(f->pwr_btn_pin->port, &f->callback_pwr_btn);
+}
+
+void amd_power_before(void *fixture)
+{
+	static const struct device *gpio_dev = GPIO_DEVICE;
+
+	RESET_FAKE(system_can_boot_ap);
+	system_can_boot_ap_fake.return_val = 1;
+	RESET_FAKE(system_jumped_to_this_image);
+	system_jumped_to_this_image_fake.return_val = 0;
+	RESET_FAKE(interrupt_sys_reset_monitor);
+	RESET_FAKE(interrupt_pwr_btn_monitor);
+
+	memset(&hook_counts, 0, sizeof(hook_counts));
+
+	/* Start GPIOs out in G3, lid open */
+	zassert_ok(gpio_emul_input_set(gpio_dev, SLP_S5_PIN, 0));
+	zassert_ok(gpio_emul_input_set(gpio_dev, SLP_S3_PIN, 0));
+	zassert_ok(gpio_emul_input_set(gpio_dev, PGOOD_S0_PIN, 0));
+	zassert_ok(gpio_emul_input_set(gpio_dev, PGOOD_S5_PIN, 0));
+	zassert_ok(gpio_emul_input_set(gpio_dev, LID_PIN, 1));
+	power_set_state(POWER_G3);
+	task_wake(TASK_ID_CHIPSET);
+	k_sleep(K_MSEC(500));
+	zassert_equal(power_get_state(), POWER_G3, "power_state=%d",
+		      power_get_state());
+	zassert_equal(power_has_signals(POWER_SIGNAL_MASK(0)), 0);
+}
+
+void amd_power_after(void *fixture)
+{
+	static const struct device *gpio_dev = GPIO_DEVICE;
+
+	host_clear_events(EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT));
+	init_reset_log();
+	system_clear_reset_flags(EC_RESET_FLAG_AP_OFF | EC_RESET_FLAG_AP_IDLE);
+	chipset_throttle_cpu(0);
+
+	/* Ensure we let go of the power button */
+	zassert_ok(gpio_emul_input_set(gpio_dev, PWRBTN_IN_PIN, 1));
+	k_sleep(K_MSEC(500));
+}
+
+ZTEST_SUITE(amd_power, NULL, amd_power_setup, amd_power_before, amd_power_after,
+	    amd_power_teardown);
+
+ZTEST(amd_power, test_power_chipset_init_ap_off)
+{
+	system_set_reset_flags(EC_RESET_FLAG_AP_OFF);
+	zassert_equal(power_chipset_init(), POWER_G3);
+	power_set_state(POWER_G3);
+
+	task_wake(TASK_ID_CHIPSET);
+	k_sleep(K_MSEC(500));
+	zassert_equal(power_get_state(), POWER_G3, "power_state=%d",
+		      power_get_state());
+}
+
+/* General helper to get us up to S0 */
+static void amd_power_s0_on(void)
+{
+	static const struct device *gpio_dev = GPIO_DEVICE;
+
+	/* "press" the power button */
+	zassert_ok(gpio_emul_input_set(gpio_dev, PWRBTN_IN_PIN, 0));
+	k_sleep(K_MSEC(500));
+	zassert_equal(gpio_emul_output_get(gpio_dev, PWRBTN_OUT_PIN), 0);
+
+	/* and "release" */
+	zassert_ok(gpio_emul_input_set(gpio_dev, PWRBTN_IN_PIN, 1));
+	k_sleep(K_MSEC(500));
+	zassert_equal(gpio_emul_output_get(gpio_dev, PWRBTN_OUT_PIN), 1);
+
+	/* Observe we're heading up and toggle appropriate "soc" outputs */
+	zassert_equal(power_get_state(), POWER_G3S5, "power_state=%d",
+		      power_get_state());
+	zassert_ok(gpio_emul_input_set(gpio_dev, PGOOD_S5_PIN, 1));
+	k_sleep(K_MSEC(500));
+
+	zassert_equal(power_get_state(), POWER_S5, "power_state=%d",
+		      power_get_state());
+	zassert_ok(gpio_emul_input_set(gpio_dev, SLP_S5_PIN, 1));
+	k_sleep(K_MSEC(500));
+
+	/* Verify hook_notify calls that come from the AMD power file */
+	zassert_equal(hook_counts.startup_count, 1);
+	zassert_equal(power_get_state(), POWER_S3, "power_state=%d",
+		      power_get_state());
+	zassert_ok(gpio_emul_input_set(gpio_dev, SLP_S3_PIN, 1));
+	k_sleep(K_MSEC(500));
+
+	zassert_equal(hook_counts.resume_count, 1);
+	zassert_equal(power_get_state(), POWER_S0, "power_state=%d",
+		      power_get_state());
+	zassert_ok(gpio_emul_input_set(gpio_dev, PGOOD_S0_PIN, 1));
+}
+
+ZTEST(amd_power, test_power_happy_s0_path)
+{
+	amd_power_s0_on();
+}
+
+ZTEST(amd_power, test_power_s5_power_loss_in_s5)
+{
+	static const struct device *gpio_dev = GPIO_DEVICE;
+
+	/* "press" the power button */
+	zassert_ok(gpio_emul_input_set(gpio_dev, PWRBTN_IN_PIN, 0));
+	k_sleep(K_MSEC(500));
+	zassert_equal(gpio_emul_output_get(gpio_dev, PWRBTN_OUT_PIN), 0);
+
+	/* and "release" */
+	zassert_ok(gpio_emul_input_set(gpio_dev, PWRBTN_IN_PIN, 1));
+	k_sleep(K_MSEC(500));
+	zassert_equal(gpio_emul_output_get(gpio_dev, PWRBTN_OUT_PIN), 1);
+
+	/* Observe we're heading up and toggle appropriate "soc" outputs */
+	zassert_equal(power_get_state(), POWER_G3S5, "power_state=%d",
+		      power_get_state());
+	zassert_ok(gpio_emul_input_set(gpio_dev, PGOOD_S5_PIN, 1));
+	k_sleep(K_MSEC(500));
+
+	zassert_equal(power_get_state(), POWER_S5, "power_state=%d",
+		      power_get_state());
+
+	/* But now we've lost S5 power good, so go to G3 */
+	zassert_ok(gpio_emul_input_set(gpio_dev, PGOOD_S5_PIN, 0));
+	k_sleep(K_MSEC(500));
+	zassert_equal(power_get_state(), POWER_G3, "power_state=%d",
+		      power_get_state());
+}
+
+ZTEST(amd_power, test_power_s5_power_loss_in_s3)
+{
+	static const struct device *gpio_dev = GPIO_DEVICE;
+
+	/* "press" the power button */
+	zassert_ok(gpio_emul_input_set(gpio_dev, PWRBTN_IN_PIN, 0));
+	k_sleep(K_MSEC(500));
+	zassert_equal(gpio_emul_output_get(gpio_dev, PWRBTN_OUT_PIN), 0);
+
+	/* and "release" */
+	zassert_ok(gpio_emul_input_set(gpio_dev, PWRBTN_IN_PIN, 1));
+	k_sleep(K_MSEC(500));
+	zassert_equal(gpio_emul_output_get(gpio_dev, PWRBTN_OUT_PIN), 1);
+
+	/* Observe we're heading up and toggle appropriate "soc" outputs */
+	zassert_equal(power_get_state(), POWER_G3S5, "power_state=%d",
+		      power_get_state());
+	zassert_ok(gpio_emul_input_set(gpio_dev, PGOOD_S5_PIN, 1));
+	k_sleep(K_MSEC(500));
+
+	zassert_equal(power_get_state(), POWER_S5, "power_state=%d",
+		      power_get_state());
+	zassert_ok(gpio_emul_input_set(gpio_dev, SLP_S5_PIN, 1));
+	k_sleep(K_MSEC(500));
+
+	/* Verify hook_notify calls that come from the AMD power file */
+	zassert_equal(hook_counts.startup_count, 1);
+	zassert_equal(power_get_state(), POWER_S3, "power_state=%d",
+		      power_get_state());
+
+	/* But now we've lost S5 power good, so go to G3 */
+	zassert_ok(gpio_emul_input_set(gpio_dev, PGOOD_S5_PIN, 0));
+	k_sleep(K_MSEC(500));
+	zassert_equal(power_get_state(), POWER_G3, "power_state=%d",
+		      power_get_state());
+}
+
+ZTEST(amd_power, test_power_s5_loss_in_s0)
+{
+	static const struct device *gpio_dev = GPIO_DEVICE;
+
+	amd_power_s0_on();
+
+	/* But now we've lost S5 power good, so go to G3 */
+	zassert_ok(gpio_emul_input_set(gpio_dev, PGOOD_S5_PIN, 0));
+	k_sleep(K_MSEC(500));
+	zassert_equal(power_get_state(), POWER_G3, "power_state=%d",
+		      power_get_state());
+}
+
+ZTEST(amd_power, test_power_happy_shutdown)
+{
+	static const struct device *gpio_dev = GPIO_DEVICE;
+
+	amd_power_s0_on();
+
+	/* Start de-sequencing with S0 PGOOD and SLP_S3 */
+	zassert_ok(gpio_emul_input_set(gpio_dev, PGOOD_S0_PIN, 0));
+	zassert_ok(gpio_emul_input_set(gpio_dev, SLP_S3_PIN, 0));
+	k_sleep(K_MSEC(500));
+
+	/* Verify hook_notify calls that come from the AMD power file */
+	zassert_equal(hook_counts.suspend_count, 1);
+	zassert_equal(power_get_state(), POWER_S3, "power_state=%d",
+		      power_get_state());
+
+	zassert_ok(gpio_emul_input_set(gpio_dev, SLP_S5_PIN, 0));
+	k_sleep(K_MSEC(500));
+
+	zassert_equal(hook_counts.shutdown_count, 1);
+	zassert_equal(power_get_state(), POWER_S5, "power_state=%d",
+		      power_get_state());
+
+	zassert_ok(gpio_emul_input_set(gpio_dev, PGOOD_S5_PIN, 0));
+	k_sleep(K_MSEC(500));
+	zassert_equal(power_get_state(), POWER_G3, "power_state=%d",
+		      power_get_state());
+}
+
+ZTEST(amd_power, test_power_happy_suspend_resume)
+{
+	struct ec_params_host_sleep_event_v1 host_sleep_ev_p = {
+		.sleep_event = HOST_SLEEP_EVENT_S0IX_SUSPEND,
+		.suspend_params = { EC_HOST_SLEEP_TIMEOUT_DEFAULT },
+	};
+	struct ec_response_host_sleep_event_v1 host_sleep_ev_r;
+	struct host_cmd_handler_args host_sleep_ev_args = BUILD_HOST_COMMAND(
+		EC_CMD_HOST_SLEEP_EVENT, 1, host_sleep_ev_r, host_sleep_ev_p);
+	static const struct device *gpio_dev = GPIO_DEVICE;
+
+	amd_power_s0_on();
+
+	/* Sleepy time */
+	zassert_ok(host_command_process(&host_sleep_ev_args));
+	zassert_ok(gpio_emul_input_set(gpio_dev, SLP_S3_PIN, 0));
+	k_sleep(K_MSEC(500));
+
+	zassert_equal(hook_counts.suspend_count, 1);
+	zassert_equal(power_get_state(), POWER_S0ix, "power_state=%d",
+		      power_get_state());
+
+	/* And time to wake */
+	hook_counts.resume_count = 0;
+	zassert_ok(gpio_emul_input_set(gpio_dev, SLP_S3_PIN, 1));
+	k_sleep(K_MSEC(500));
+	host_sleep_ev_p.sleep_event = HOST_SLEEP_EVENT_S0IX_RESUME;
+	zassert_ok(host_command_process(&host_sleep_ev_args));
+	k_sleep(K_MSEC(500));
+
+	zassert_equal(hook_counts.resume_count, 1);
+	zassert_equal(power_get_state(), POWER_S0, "power_state=%d",
+		      power_get_state());
+}
+
+ZTEST(amd_power, test_power_suspend_power_loss)
+{
+	struct ec_params_host_sleep_event_v1 host_sleep_ev_p = {
+		.sleep_event = HOST_SLEEP_EVENT_S0IX_SUSPEND,
+		.suspend_params = { EC_HOST_SLEEP_TIMEOUT_DEFAULT },
+	};
+	struct ec_response_host_sleep_event_v1 host_sleep_ev_r;
+	struct host_cmd_handler_args host_sleep_ev_args = BUILD_HOST_COMMAND(
+		EC_CMD_HOST_SLEEP_EVENT, 1, host_sleep_ev_r, host_sleep_ev_p);
+	static const struct device *gpio_dev = GPIO_DEVICE;
+
+	amd_power_s0_on();
+
+	/* Sleepy time */
+	zassert_ok(host_command_process(&host_sleep_ev_args));
+	zassert_ok(gpio_emul_input_set(gpio_dev, SLP_S3_PIN, 0));
+	k_sleep(K_MSEC(500));
+
+	zassert_equal(hook_counts.suspend_count, 1);
+	zassert_equal(power_get_state(), POWER_S0ix, "power_state=%d",
+		      power_get_state());
+
+	/* Oh no!  S5 power has been lost cap'n */
+	zassert_ok(gpio_emul_input_set(gpio_dev, PGOOD_S5_PIN, 0));
+	k_sleep(K_MSEC(500));
+	zassert_equal(power_get_state(), POWER_G3, "power_state=%d",
+		      power_get_state());
+}
+
+ZTEST(amd_power, test_power_suspend_shut_down)
+{
+	struct ec_params_host_sleep_event_v1 host_sleep_ev_p = {
+		.sleep_event = HOST_SLEEP_EVENT_S0IX_SUSPEND,
+		.suspend_params = { EC_HOST_SLEEP_TIMEOUT_DEFAULT },
+	};
+	struct ec_response_host_sleep_event_v1 host_sleep_ev_r;
+	struct host_cmd_handler_args host_sleep_ev_args = BUILD_HOST_COMMAND(
+		EC_CMD_HOST_SLEEP_EVENT, 1, host_sleep_ev_r, host_sleep_ev_p);
+	static const struct device *gpio_dev = GPIO_DEVICE;
+
+	amd_power_s0_on();
+
+	/* Sleepy time */
+	zassert_ok(host_command_process(&host_sleep_ev_args));
+	zassert_ok(gpio_emul_input_set(gpio_dev, SLP_S3_PIN, 0));
+	k_sleep(K_MSEC(500));
+
+	zassert_equal(hook_counts.suspend_count, 1);
+	zassert_equal(power_get_state(), POWER_S0ix, "power_state=%d",
+		      power_get_state());
+
+	/* Something caused AP shutdown while we slept */
+	zassert_ok(gpio_emul_input_set(gpio_dev, SLP_S5_PIN, 0));
+	k_sleep(K_MSEC(500));
+	zassert_equal(power_get_state(), POWER_S5, "power_state=%d",
+		      power_get_state());
+}
+
+ZTEST(amd_power, test_power_suspend_hang)
+{
+	struct ec_params_host_sleep_event_v1 host_sleep_ev_p = {
+		.sleep_event = HOST_SLEEP_EVENT_S0IX_SUSPEND,
+		.suspend_params = { EC_HOST_SLEEP_TIMEOUT_DEFAULT },
+	};
+	struct ec_response_host_sleep_event_v1 host_sleep_ev_r;
+	struct host_cmd_handler_args host_sleep_ev_args = BUILD_HOST_COMMAND(
+		EC_CMD_HOST_SLEEP_EVENT, 1, host_sleep_ev_r, host_sleep_ev_p);
+	const char *buffer;
+	size_t buffer_size;
+
+	amd_power_s0_on();
+
+	/* Send sleep event, but fail to actually transition the signal */
+	shell_backend_dummy_clear_output(get_ec_shell());
+	zassert_ok(host_command_process(&host_sleep_ev_args));
+	k_sleep(K_MSEC(CONFIG_SLEEP_TIMEOUT_MS * 2));
+
+	zassert_equal(power_get_state(), POWER_S0);
+	buffer = shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+	zassert_true(strstr(buffer, "Detected sleep hang!") != NULL);
+}
+
+ZTEST(amd_power, test_power_stb_dump_interrupt)
+{
+	struct ec_params_host_sleep_event_v1 host_sleep_ev_p = {
+		.sleep_event = HOST_SLEEP_EVENT_S0IX_SUSPEND,
+		.suspend_params = { EC_HOST_SLEEP_TIMEOUT_DEFAULT },
+	};
+	struct ec_response_host_sleep_event_v1 host_sleep_ev_r;
+	struct host_cmd_handler_args host_sleep_ev_args = BUILD_HOST_COMMAND(
+		EC_CMD_HOST_SLEEP_EVENT, 1, host_sleep_ev_r, host_sleep_ev_p);
+	static const struct device *gpio_dev = GPIO_DEVICE;
+
+	amd_power_s0_on();
+
+	/* Send sleep event, but fail to actually transition the signal */
+	zassert_ok(host_command_process(&host_sleep_ev_args));
+	k_sleep(K_MSEC(CONFIG_SLEEP_TIMEOUT_MS * 2));
+
+	zassert_equal(power_get_state(), POWER_S0);
+	/* Watch for our STB dump to trigger */
+	zassert_equal(gpio_emul_output_get(gpio_dev, STB_OUT_PIN), 1);
+
+	/* But a reset came in before we finished the STB dump */
+	chipset_reset(CHIPSET_RESET_HANG_REBOOT);
+
+	/* Observe we're not longer asserting the OUT pin */
+	zassert_equal(gpio_emul_output_get(gpio_dev, STB_OUT_PIN), 0);
+}
+
+ZTEST(amd_power, test_power_forced_shutdown)
+{
+	static const struct device *gpio_dev = GPIO_DEVICE;
+
+	amd_power_s0_on();
+
+	/* Report a critical thermal event */
+	chipset_force_shutdown(CHIPSET_SHUTDOWN_THERMAL);
+	k_sleep(K_MSEC(500));
+
+	/* Chipset task sends the power button to the processor */
+	zassert_equal(gpio_emul_output_get(gpio_dev, PWRBTN_OUT_PIN), 0);
+	zassert_equal(chipset_get_shutdown_reason(), CHIPSET_SHUTDOWN_THERMAL);
+
+	/* Allow our rails to turn off for shutdown */
+	zassert_ok(gpio_emul_input_set(gpio_dev, PGOOD_S0_PIN, 0));
+	zassert_ok(gpio_emul_input_set(gpio_dev, SLP_S3_PIN, 0));
+	k_sleep(K_MSEC(500));
+
+	zassert_ok(gpio_emul_input_set(gpio_dev, SLP_S5_PIN, 0));
+	k_sleep(K_MSEC(500));
+
+	/* Power button should be released now that we shut down */
+	zassert_equal(gpio_emul_output_get(gpio_dev, PWRBTN_OUT_PIN), 1);
+}
+
+ZTEST(amd_power, test_power_forced_shutdown_espi_reset)
+{
+	static const struct device *gpio_dev = GPIO_DEVICE;
+
+	amd_power_s0_on();
+
+	/* Report a critical thermal event */
+	chipset_force_shutdown(CHIPSET_SHUTDOWN_THERMAL);
+	k_sleep(K_MSEC(500));
+
+	/* Chipset task sends the power button to the processor */
+	zassert_equal(gpio_emul_output_get(gpio_dev, PWRBTN_OUT_PIN), 0);
+	zassert_equal(chipset_get_shutdown_reason(), CHIPSET_SHUTDOWN_THERMAL);
+
+	/*
+	 * Before our rails went down, we got an eSPI reset assert which removes
+	 * the power button assert since the processor is shutting down
+	 */
+	chipset_handle_espi_reset_assert();
+	zassert_equal(gpio_emul_output_get(gpio_dev, PWRBTN_OUT_PIN), 1);
+}
+
+ZTEST(amd_power, test_power_chipset_reset_s0)
+{
+	amd_power_s0_on();
+
+	/* Report a special keyboard reset */
+	chipset_reset(CHIPSET_RESET_KB_SYSRESET);
+	k_sleep(K_MSEC(500));
+
+	/* Verify our reporting and SYS_RESET toggles */
+	zassert_equal(chipset_get_shutdown_reason(), CHIPSET_RESET_KB_SYSRESET);
+	zassert_equal(2, interrupt_sys_reset_monitor_fake.call_count,
+		      "Interrupt pin asserted only %d times.",
+		      interrupt_sys_reset_monitor_fake.call_count);
+}
+
+ZTEST(amd_power, test_power_chipset_reset_g3)
+{
+	/* Report a special keyboard reset */
+	chipset_reset(CHIPSET_RESET_KB_SYSRESET);
+	k_sleep(K_MSEC(500));
+
+	/* Verify we didn't report the reset attempt */
+	zassert_equal(chipset_get_shutdown_reason(), CHIPSET_RESET_UNKNOWN);
+	zassert_equal(0, interrupt_sys_reset_monitor_fake.call_count);
+}
+
+ZTEST(amd_power, test_power_chipset_throttle_s0)
+{
+	static const struct device *gpio_dev = GPIO_DEVICE;
+
+	amd_power_s0_on();
+
+	/* Report we need to throttle */
+	chipset_throttle_cpu(1);
+
+	/* Verify we see PROCHOT asserted */
+	zassert_ok(gpio_emul_input_set(gpio_dev, PGOOD_S0_PIN, 0));
+}
+
+ZTEST(amd_power, test_power_chipset_throttle_g3)
+{
+	static const struct device *gpio_dev = GPIO_DEVICE;
+
+	/* Report we need to throttle */
+	chipset_throttle_cpu(1);
+
+	/* Verify we ignored it since we're off */
+	zassert_ok(gpio_emul_input_set(gpio_dev, PGOOD_S0_PIN, 1));
+}
+
+ZTEST(amd_power, test_sysjump_s0)
+{
+	/* Simulate a "sysjump" in S0 */
+	amd_power_s0_on();
+
+	RESET_FAKE(system_jumped_to_this_image);
+	system_jumped_to_this_image_fake.return_val = 1;
+	zassert_equal(power_chipset_init(), POWER_S0);
+}
+
+ZTEST(amd_power, test_sysjump_s5)
+{
+	static const struct device *gpio_dev = GPIO_DEVICE;
+
+	/* Only set S5 PGOOD this time */
+	zassert_ok(gpio_emul_input_set(gpio_dev, PGOOD_S5_PIN, 1));
+
+	RESET_FAKE(system_jumped_to_this_image);
+	system_jumped_to_this_image_fake.return_val = 1;
+	zassert_equal(power_chipset_init(), POWER_S5);
+}
+
+ZTEST(amd_power, test_sysjump_g3)
+{
+	/* "Sysjump" with no power rails on */
+	RESET_FAKE(system_jumped_to_this_image);
+	system_jumped_to_this_image_fake.return_val = 1;
+	zassert_equal(power_chipset_init(), POWER_G3);
+}
+
+/* power_button_x86 tests */
+ZTEST(amd_power, test_lid_open_power_on)
+{
+	static const struct device *gpio_dev = GPIO_DEVICE;
+
+	/* "close" our lid and observe we're still in G3 */
+	zassert_ok(gpio_emul_input_set(gpio_dev, LID_PIN, 0));
+	k_sleep(K_MSEC(500));
+	zassert_equal(power_get_state(), POWER_G3, "power_state=%d",
+		      power_get_state());
+
+	/* "open" and observe we try to power on */
+	zassert_ok(gpio_emul_input_set(gpio_dev, LID_PIN, 1));
+	k_sleep(K_MSEC(500));
+	zassert_equal(power_get_state(), POWER_G3S5, "power_state=%d",
+		      power_get_state());
+}
+
+ZTEST(amd_power, test_power_long_button_press)
+{
+	struct ec_params_config_power_button pwr_btn_p = {
+		.flags = EC_POWER_BUTTON_ENABLE_PULSE,
+	};
+	struct host_cmd_handler_args pwr_btn_hc_args =
+		BUILD_HOST_COMMAND_PARAMS(EC_CMD_CONFIG_POWER_BUTTON, 0,
+					  pwr_btn_p);
+	static const struct device *gpio_dev = GPIO_DEVICE;
+
+	amd_power_s0_on();
+
+	/* Clear our counts */
+	RESET_FAKE(interrupt_pwr_btn_monitor);
+
+	/* Tell the EC we do want toggles */
+	zassert_ok(host_command_process(&pwr_btn_hc_args));
+
+	/* "press" the power button */
+	zassert_ok(gpio_emul_input_set(gpio_dev, PWRBTN_IN_PIN, 0));
+
+	/* Hold it long enough to trigger our toggle */
+	k_sleep(K_SECONDS(10));
+
+	/* Now release */
+	zassert_ok(gpio_emul_input_set(gpio_dev, PWRBTN_IN_PIN, 1));
+	k_sleep(K_MSEC(500));
+	zassert_equal(gpio_emul_output_get(gpio_dev, PWRBTN_OUT_PIN), 1);
+
+	/* Look for our edges */
+	zassert_equal(4, interrupt_pwr_btn_monitor_fake.call_count,
+		      "Interrupt pin asserted only %d times.",
+		      interrupt_pwr_btn_monitor_fake.call_count);
+}
+
+ZTEST(amd_power, test_power_long_button_press_toggle_disabled)
+{
+	struct ec_params_config_power_button pwr_btn_p = {
+		.flags = 0,
+	};
+	struct host_cmd_handler_args pwr_btn_hc_args =
+		BUILD_HOST_COMMAND_PARAMS(EC_CMD_CONFIG_POWER_BUTTON, 0,
+					  pwr_btn_p);
+	static const struct device *gpio_dev = GPIO_DEVICE;
+
+	amd_power_s0_on();
+
+	/* Clear our counts */
+	RESET_FAKE(interrupt_pwr_btn_monitor);
+
+	/* Tell the EC we no longer want toggles */
+	zassert_ok(host_command_process(&pwr_btn_hc_args));
+
+	/* "press" the power button */
+	zassert_ok(gpio_emul_input_set(gpio_dev, PWRBTN_IN_PIN, 0));
+
+	/* Hold it long enough to trigger our toggle */
+	k_sleep(K_SECONDS(10));
+
+	/* Now release */
+	zassert_ok(gpio_emul_input_set(gpio_dev, PWRBTN_IN_PIN, 1));
+	k_sleep(K_MSEC(500));
+	zassert_equal(gpio_emul_output_get(gpio_dev, PWRBTN_OUT_PIN), 1);
+
+	/* Look for our edges */
+	zassert_equal(2, interrupt_pwr_btn_monitor_fake.call_count,
+		      "Interrupt pin asserted only %d times.",
+		      interrupt_pwr_btn_monitor_fake.call_count);
+}
+
+ZTEST(amd_power, test_power_button_eat_release)
+{
+	static const struct device *gpio_dev = GPIO_DEVICE;
+
+	/* "press" the power button */
+	zassert_ok(gpio_emul_input_set(gpio_dev, PWRBTN_IN_PIN, 0));
+	k_sleep(K_MSEC(500));
+	zassert_equal(gpio_emul_output_get(gpio_dev, PWRBTN_OUT_PIN), 0);
+
+	/* Trigger some internal condition that causes us to force release */
+	power_button_pch_release();
+	k_sleep(K_MSEC(500));
+	zassert_equal(gpio_emul_output_get(gpio_dev, PWRBTN_OUT_PIN), 1);
+
+	/* AP should see assert and release */
+	zassert_equal(2, interrupt_pwr_btn_monitor_fake.call_count,
+		      "Interrupt pin asserted only %d times.",
+		      interrupt_pwr_btn_monitor_fake.call_count);
+
+	/* Now really release */
+	zassert_ok(gpio_emul_input_set(gpio_dev, PWRBTN_IN_PIN, 1));
+	k_sleep(K_MSEC(500));
+
+	/* Output should have remained the same */
+	zassert_equal(2, interrupt_pwr_btn_monitor_fake.call_count,
+		      "Interrupt pin asserted only %d times.",
+		      interrupt_pwr_btn_monitor_fake.call_count);
+}
+
+ZTEST(amd_power, test_power_button_init_ap_off)
+{
+	static const struct device *gpio_dev = GPIO_DEVICE;
+
+	/* Clear our counts */
+	RESET_FAKE(interrupt_pwr_btn_monitor);
+
+	system_set_reset_flags(EC_RESET_FLAG_AP_OFF);
+
+	set_initial_pwrbtn_state();
+	k_sleep(K_MSEC(500));
+
+	/* Power button is forced high (off) */
+	zassert_equal(gpio_emul_output_get(gpio_dev, PWRBTN_OUT_PIN), 1);
+	zassert_equal(1, interrupt_pwr_btn_monitor_fake.call_count,
+		      "Interrupt pin asserted only %d times.",
+		      interrupt_pwr_btn_monitor_fake.call_count);
+}
+
+ZTEST(amd_power, test_power_button_init_ap_idle)
+{
+	/* Clear our counts */
+	RESET_FAKE(interrupt_pwr_btn_monitor);
+
+	system_set_reset_flags(EC_RESET_FLAG_AP_IDLE);
+
+	set_initial_pwrbtn_state();
+	k_sleep(K_MSEC(500));
+
+	/* Power button should do nothing */
+	zassert_equal(0, interrupt_pwr_btn_monitor_fake.call_count,
+		      "Interrupt pin asserted only %d times.",
+		      interrupt_pwr_btn_monitor_fake.call_count);
+}
+
+ZTEST(amd_power, test_power_button_sysjump_init_pressed)
+{
+	struct ec_params_config_power_button pwr_btn_p = {
+		.flags = EC_POWER_BUTTON_ENABLE_PULSE,
+	};
+	struct host_cmd_handler_args pwr_btn_hc_args =
+		BUILD_HOST_COMMAND_PARAMS(EC_CMD_CONFIG_POWER_BUTTON, 0,
+					  pwr_btn_p);
+	static const struct device *gpio_dev = GPIO_DEVICE;
+
+	/* Simulate a "sysjump" in S0 */
+	amd_power_s0_on();
+
+	/* Tell the EC we do want toggles */
+	zassert_ok(host_command_process(&pwr_btn_hc_args));
+
+	RESET_FAKE(system_jumped_to_this_image);
+	system_jumped_to_this_image_fake.return_val = 1;
+	RESET_FAKE(interrupt_pwr_btn_monitor);
+
+	/* Power button pressed as we jump */
+	zassert_ok(gpio_emul_input_set(gpio_dev, PWRBTN_IN_PIN, 0));
+	k_sleep(K_MSEC(500));
+
+	set_initial_pwrbtn_state();
+
+	/* Power button is forced asserted with a toggle in there */
+	zassert_equal(gpio_emul_output_get(gpio_dev, PWRBTN_OUT_PIN), 0);
+	zassert_equal(3, interrupt_pwr_btn_monitor_fake.call_count,
+		      "Interrupt pin asserted only %d times.",
+		      interrupt_pwr_btn_monitor_fake.call_count);
+}
+
+ZTEST(amd_power, test_power_button_sysjump_init_no_press)
+{
+	static const struct device *gpio_dev = GPIO_DEVICE;
+
+	/* Simulate a "sysjump" in S0 */
+	amd_power_s0_on();
+
+	RESET_FAKE(system_jumped_to_this_image);
+	system_jumped_to_this_image_fake.return_val = 1;
+	RESET_FAKE(interrupt_pwr_btn_monitor);
+
+	set_initial_pwrbtn_state();
+
+	/* Power button did nothing */
+	zassert_equal(gpio_emul_output_get(gpio_dev, PWRBTN_OUT_PIN), 1);
+	zassert_equal(0, interrupt_pwr_btn_monitor_fake.call_count,
+		      "Interrupt pin asserted only %d times.",
+		      interrupt_pwr_btn_monitor_fake.call_count);
+}
+
+void test_main(void)
+{
+	ec_app_main();
+	/*
+	 * Fake sleep long enough to ensure all automatic power sequencing is
+	 * done
+	 */
+	k_sleep(K_SECONDS(11));
+
+	ztest_run_test_suites(NULL);
+
+	ztest_verify_all_test_suites_ran();
+}
+
+/* These 2 lines are needed because we don't define an espi host driver */
+#define DT_DRV_COMPAT zephyr_espi_emul_espi_host
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
diff --git a/zephyr/test/amd_power/testcase.yaml b/zephyr/test/amd_power/testcase.yaml
new file mode 100644
index 0000000000..9b34158b0b
--- /dev/null
+++ b/zephyr/test/amd_power/testcase.yaml
@@ -0,0 +1,6 @@
+common:
+  platform_allow: native_posix
+tests:
+  amd_power.default:
+    extra_dtc_overlay_files:
+    - boards/native_posix.overlay
diff --git a/zephyr/test/ap_power/CMakeLists.txt b/zephyr/test/ap_power/CMakeLists.txt
new file mode 100644
index 0000000000..4669dac07e
--- /dev/null
+++ b/zephyr/test/ap_power/CMakeLists.txt
@@ -0,0 +1,16 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(ap_power)
+
+add_subdirectory(${PLATFORM_EC}/zephyr/test/test_utils test_utils)
+
+# Include the local test directory for shimmed_test_tasks.h
+zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}")
+zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}/include")
+
+FILE(GLOB_RECURSE test_sources src/*.c)
+target_sources(app PRIVATE ${test_sources})
diff --git a/zephyr/test/ap_power/Kconfig b/zephyr/test/ap_power/Kconfig
new file mode 100644
index 0000000000..ac7b264855
--- /dev/null
+++ b/zephyr/test/ap_power/Kconfig
@@ -0,0 +1,5 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+source "Kconfig.zephyr"
diff --git a/zephyr/test/ap_power/boards/alderlake.dts b/zephyr/test/ap_power/boards/alderlake.dts
new file mode 100644
index 0000000000..58c68529c3
--- /dev/null
+++ b/zephyr/test/ap_power/boards/alderlake.dts
@@ -0,0 +1,396 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/gpio_defines.h>
+
+/ {
+	common-pwrseq {
+		compatible = "intel,ap-pwrseq";
+		s5-inactivity-timeout = <1>;
+		all-sys-pwrgd-timeout = <50>;
+	};
+
+	en_pp5000: pwr-en-pp5000-s5 {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PP5000_S5 enable output to regulator";
+		enum-name = "PWR_EN_PP5000_A";
+		gpios = <&gpio0 10 0>;
+		output;
+	};
+	en_pp3300: pwr-en-pp3300-s5 {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PP3300_S5 enable output to LS";
+		enum-name = "PWR_EN_PP3300_A";
+		gpios = <&gpio0 11 0>;
+		output;
+	};
+	rsmrst: pwr-pg-ec-rsmrst-odl {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST power good from regulator";
+		enum-name = "PWR_RSMRST";
+		gpios = <&gpio0 12 0>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	ec_pch_rsmrst: pwr-ec-pch-rsmrst-odl {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST output to PCH";
+		enum-name = "PWR_EC_PCH_RSMRST";
+		gpios = <&gpio0 13 0>;
+		output;
+	};
+	slp_s0: pwr-slp-s0-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_S0_L input from PCH";
+		enum-name = "PWR_SLP_S0";
+		gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+		no-enable;
+	};
+	slp_s3: pwr-slp-s3-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_S3_L input from PCH";
+		enum-name = "PWR_SLP_S3";
+		gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	slp_sus: pwr-slp-sus-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_SUS_L input from PCH";
+		enum-name = "PWR_SLP_SUS";
+		gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	ec_soc_dsw_pwrok: pwr-ec-soc-dsw-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "DSW_PWROK output to PCH";
+		enum-name = "PWR_EC_SOC_DSW_PWROK";
+		gpios = <&gpio0 17 0>;
+		output;
+	};
+	pwr-vccst-pwrgd-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "VCCST_PWRGD output to PCH";
+		enum-name = "PWR_VCCST_PWRGD";
+		gpios = <&gpio0 18 0>;
+		output;
+	};
+	pwr-imvp9-vrrdy-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "VRRDY input from IMVP9";
+		enum-name = "PWR_IMVP9_VRRDY";
+		gpios = <&gpio0 19 0>;
+	};
+	pch_pwrok: pwr-pch-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PCH_PWROK output to PCH";
+		enum-name = "PWR_PCH_PWROK";
+		gpios = <&gpio0 20 0>;
+		output;
+	};
+	pwr-ec-pch-sys-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_PWROK output to PCH";
+		enum-name = "PWR_EC_PCH_SYS_PWROK";
+		gpios = <&gpio0 21 0>;
+		output;
+	};
+	pwr-sys-rst-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_RESET# output to PCH";
+		enum-name = "PWR_SYS_RST";
+		gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
+		output;
+	};
+	slp_s4: pwr-slp-s4 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S4 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S4";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4";
+		vw-invert;
+	};
+	slp_s5: pwr-slp-s5 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S5 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S5";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5";
+		vw-invert;
+	};
+	all_sys_pwrgd: pwr-all-sys-pwrgd {
+		compatible = "intel,ap-pwrseq-external";
+		dbg-label = "Combined all power good";
+		enum-name = "PWR_ALL_SYS_PWRGD";
+	};
+	dsw_pwrok: pwr-pp3300-pwrok {
+		compatible = "intel,ap-pwrseq-external";
+		dbg-label = "PP3300 PWROK";
+		enum-name = "PWR_DSW_PWROK";
+	};
+
+	adc0: adc {
+		compatible = "zephyr,adc-emul";
+		nchannels = <6>;
+		ref-internal-mv = <3300>;
+		#io-channel-cells = <1>;
+		status = "okay";
+	};
+	mock_cmp_high: mock-cmp-high {
+		compatible = "cros,vcmp-mock";
+		threshold-mv = <50>;
+		io-channels = <&adc0 0>;
+	};
+	mock_cmp_low: mock-cmp-low {
+		compatible = "cros,vcmp-mock";
+		threshold-mv = <100>;
+		io-channels = <&adc0 1>;
+	};
+	pwr-pp1p05-pwrok {
+		compatible = "intel,ap-pwrseq-adc";
+		dbg-label = "PP1P05 PWROK (from ADC)";
+		enum-name = "PWR_PG_PP1P05";
+		trigger-high = <&mock_cmp_high>;
+		trigger-low = <&mock_cmp_low>;
+	};
+
+	en_pp3300_emul: en-pp3300-emul {
+		compatible = "intel,ap-pwr-signal-emul";
+		input-signal = <&en_pp3300>;
+		init-value = <0>;
+		pp3300-dsw-pwrok-emul {
+			output-signal = <&dsw_pwrok>;
+			assert-delay-ms = <10>;
+			init-value= <0>;
+		};
+	};
+
+	en_pp5000_emul: en-pp5000-emul {
+		compatible = "intel,ap-pwr-signal-emul";
+		input-signal = <&en_pp5000>;
+		init-value = <0>;
+		pp5000-rsmrst-emul {
+			output-signal = <&rsmrst>;
+			assert-delay-ms = <40>;
+			init-value= <0>;
+		};
+	};
+
+	ec_soc_dsw_pwrok_emul: ec-soc-dsw-pwrok-emul {
+		compatible = "intel,ap-pwr-signal-emul";
+		input-signal = <&ec_soc_dsw_pwrok>;
+		init-value = <0>;
+		ec-dsw-pwrok-slp-sus-emul {
+			output-signal = <&slp_sus>;
+			assert-delay-ms = <20>;
+			init-value= <1>;
+			invert-value;
+		};
+	};
+
+	ec_pch_rsmrst_emul: ec-pch-rsmrst-emul {
+		compatible = "intel,ap-pwr-signal-emul";
+		input-signal = <&ec_pch_rsmrst>;
+		init-value = <0>;
+		ec-pch-rsmrst-slp-s5-emul {
+			output-signal = <&slp_s5>;
+			assert-delay-ms = <20>;
+			invert-value;
+			init-value= <1>;
+		};
+		ec-pch-rsmrst-slp-s4-emul {
+			output-signal = <&slp_s4>;
+			assert-delay-ms = <30>;
+			invert-value;
+			init-value= <1>;
+		};
+		ec-pch-rsmrst-slp-s3-emul {
+			output-signal = <&slp_s3>;
+			assert-delay-ms = <40>;
+			init-value= <1>;
+			invert-value;
+		};
+		ec-pch-rsmrst-slp-s0-emul {
+			output-signal = <&slp_s0>;
+			assert-delay-ms = <45>;
+			init-value= <1>;
+			invert-value;
+		};
+		ec-pch-rsmrst-all-sys-pwrgd {
+			output-signal = <&all_sys_pwrgd>;
+			assert-delay-ms = <50>;
+			init-value= <0>;
+		};
+	};
+
+	tp-sys-g3-to-s0 {
+		compatible = "intel,ap-pwr-test-platform";
+		nodes = <&en_pp3300_emul &en_pp5000_emul
+			      &ec_soc_dsw_pwrok_emul &ec_pch_rsmrst_emul>;
+	};
+
+	pch_pwrok_power_fail_emul: pch-pwrok-power-fail-emul {
+		compatible = "intel,ap-pwr-signal-emul";
+		input-signal = <&pch_pwrok>;
+		init-value = <0>;
+		pch-pwrok-dsw-pwrok-emul {
+			output-signal = <&dsw_pwrok>;
+			assert-delay-ms = <50>;
+			invert-value;
+		};
+		pch-pwrok-slp-sus-emul {
+			output-signal = <&slp_sus>;
+			assert-delay-ms = <60>;
+		};
+	};
+
+	tp-sys-s0-power-fail {
+		compatible = "intel,ap-pwr-test-platform";
+		nodes = <&pch_pwrok_power_fail_emul>;
+	};
+
+	pch_pwrok_power_down_emul: pch-pwrok-power-down-emul {
+		compatible = "intel,ap-pwr-signal-emul";
+		input-signal = <&pch_pwrok>;
+		init-value = <0>;
+		edge = "EDGE_ACTIVE_ON_ASSERT";
+		pch-pwrok-slp-sus-emul {
+			output-signal = <&slp_sus>;
+			assert-delay-ms = <70>;
+		};
+
+		pch_pwrok-rsmrst-emul {
+			output-signal = <&rsmrst>;
+			assert-delay-ms = <60>;
+			invert-value;
+		};
+
+		pch-pwrok-slp-s5-emul {
+			output-signal = <&slp_s5>;
+			assert-delay-ms = <50>;
+		};
+
+		pch-pwrok-slp-s4-emul {
+			output-signal = <&slp_s4>;
+			assert-delay-ms = <30>;
+		};
+
+		pch-pwrok-slp-s3-emul {
+			output-signal = <&slp_s3>;
+			assert-delay-ms = <20>;
+		};
+
+		pch-pwrok-slp-s0-emul {
+			output-signal = <&slp_s0>;
+			assert-delay-ms = <15>;
+		};
+	};
+
+	tp-sys-g3-to-s0-power-down {
+		compatible = "intel,ap-pwr-test-platform";
+		nodes = <&en_pp3300_emul &en_pp5000_emul
+			      &ec_soc_dsw_pwrok_emul &ec_pch_rsmrst_emul
+			      &pch_pwrok_power_down_emul>;
+	};
+
+	tp-sys-s5-slp-sus-fail {
+		compatible = "intel,ap-pwr-test-platform";
+		nodes = <&en_pp3300_emul>;
+	};
+
+	ec_pch_rsmrst_s4_dsw_pwrok_fail_emul:
+			ec-pch-rsmrst-s4-dsw-pwrok-fail-emul {
+		compatible = "intel,ap-pwr-signal-emul";
+		input-signal = <&ec_pch_rsmrst>;
+		init-value = <0>;
+		ec-pch-rsmrst-slp-s5-emul {
+			output-signal = <&slp_s5>;
+			assert-delay-ms = <20>;
+			invert-value;
+			init-value= <1>;
+		};
+		ec-pch-rsmrst-slp-s4-emul {
+			output-signal = <&slp_s4>;
+			assert-delay-ms = <30>;
+			invert-value;
+			init-value= <1>;
+		};
+		pch-pwrok-dsw-pwrok-emul {
+			output-signal = <&dsw_pwrok>;
+			assert-delay-ms = <50>;
+			invert-value;
+		};
+	};
+
+	tp-sys-s4-dsw-pwrok-fail {
+		compatible = "intel,ap-pwr-test-platform";
+		nodes = <&en_pp3300_emul &en_pp5000_emul &ec_soc_dsw_pwrok_emul
+			     &ec_pch_rsmrst_s4_dsw_pwrok_fail_emul>;
+	};
+
+	ec_pch_rsmrst_s3_dsw_pwrok_fail_emul:
+			ec-pch-rsmrst-s3-dsw-pwrok-fail-emul {
+		compatible = "intel,ap-pwr-signal-emul";
+		input-signal = <&ec_pch_rsmrst>;
+		init-value = <0>;
+		ec-pch-rsmrst-slp-s5-emul {
+			output-signal = <&slp_s5>;
+			assert-delay-ms = <20>;
+			invert-value;
+			init-value= <1>;
+		};
+		ec-pch-rsmrst-slp-s4-emul {
+			output-signal = <&slp_s4>;
+			assert-delay-ms = <30>;
+			invert-value;
+			init-value= <1>;
+		};
+		ec-pch-rsmrst-slp-s3-emul {
+			output-signal = <&slp_s3>;
+			assert-delay-ms = <30>;
+			invert-value;
+			init-value= <1>;
+		};
+		pch-pwrok-dsw-pwrok-emul {
+			output-signal = <&dsw_pwrok>;
+			assert-delay-ms = <50>;
+			invert-value;
+		};
+	};
+
+	tp-sys-s3-dsw-pwrok-fail {
+		compatible = "intel,ap-pwr-test-platform";
+		nodes = <&en_pp3300_emul &en_pp5000_emul &ec_soc_dsw_pwrok_emul
+			     &ec_pch_rsmrst_s3_dsw_pwrok_fail_emul>;
+	};
+
+	pch_sleep: pch-sleep {
+		compatible = "intel,ap-pwr-signal-emul";
+		input-signal = <&pch_pwrok>;
+
+		slp-s0-suspend-emul {
+			output-signal = <&slp_s0>;
+			init-value=<1>;
+		};
+	};
+
+	tp-sys-sleep {
+		compatible = "intel,ap-pwr-test-platform";
+		nodes = <&pch_sleep>;
+	};
+
+	pch_wake: pch-wake {
+		compatible = "intel,ap-pwr-signal-emul";
+		input-signal = <&pch_pwrok>;
+
+		slp-s0-resume-emul {
+			output-signal = <&slp_s0>;
+			init-value=<0>;
+		};
+	};
+
+	tp-sys-wake {
+		compatible = "intel,ap-pwr-test-platform";
+		nodes = <&pch_wake>;
+	};
+
+};
diff --git a/zephyr/test/ap_power/boards/native_posix.overlay b/zephyr/test/ap_power/boards/native_posix.overlay
new file mode 100644
index 0000000000..b30240a094
--- /dev/null
+++ b/zephyr/test/ap_power/boards/native_posix.overlay
@@ -0,0 +1,71 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <board-overlays/native_posix.dts>
+#include <cros/binman.dtsi>
+#include <dt-bindings/gpio_defines.h>
+#include <freq.h>
+
+/ {
+	chosen {
+		cros-ec,espi = &espi0;
+		intel-ap-pwrseq,espi = &espi0;
+	};
+
+	/*
+	 * Keep these GPIOs in pin order.
+	 * If you need to add one, make sure you increase
+	 * ngpios in the gpio0 node further down.
+	 */
+	named-gpios {
+		compatible = "named-gpios";
+
+		gpio_ec_pwr_btn_odl: ec_pwr_btn_odl {
+			/* GPIO_PULL_UP will cause this start asserted,
+			 * i.e. not pressed.
+			 */
+			gpios = <&gpio0 1 (GPIO_INPUT | GPIO_PULL_UP)>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		gpio_pch_pwrbtn_l: pch_pwrbtn_l {
+			gpios = <&gpio0 2 GPIO_OUTPUT>;
+			enum-name = "GPIO_PCH_PWRBTN_L";
+		};
+		gpio_ec_pch_wake_odl: ec_pch_wake_odl {
+			gpios = <&gpio0 3 GPIO_OUTPUT_HIGH>;
+		};
+		gpio_lid_open_ec: lid_open_ec {
+			/* GPIO_PULL_UP will cause this start asserted. */
+			gpios = <&gpio0 4 (GPIO_INPUT | GPIO_PULL_UP)>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+	};
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_lid_open_ec: lid_open_ec {
+			irq-pin = <&gpio_lid_open_ec>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "lid_interrupt";
+		};
+	};
+
+	clock: clock {
+		compatible = "cros,clock-control-emul";
+		clock-frequency = <DT_FREQ_M(100)>; /* 100 MHz */
+	};
+};
+
+&espi0 {
+	espi-host@0 {
+		status = "okay";
+		compatible = "zephyr,espi-emul-espi-host";
+		reg = <0x0>;
+	};
+};
+
+&gpio0 {
+	ngpios = <23>;
+};
diff --git a/zephyr/test/ap_power/include/test_mocks.h b/zephyr/test/ap_power/include/test_mocks.h
new file mode 100644
index 0000000000..5efa0c7570
--- /dev/null
+++ b/zephyr/test/ap_power/include/test_mocks.h
@@ -0,0 +1,24 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __TEST_AP_POWER_TEST_MOCKS_H
+#define __TEST_AP_POWER_TEST_MOCKS_H
+
+#include <stdint.h>
+
+#include <zephyr/fff.h>
+
+/*
+ * Mock declarations
+ */
+
+/* Mocks for common/extpower_gpio.c */
+DECLARE_FAKE_VALUE_FUNC(int, extpower_is_present);
+
+/* Mocks for common/system.c */
+DECLARE_FAKE_VOID_FUNC(system_hibernate, uint32_t, uint32_t);
+DECLARE_FAKE_VALUE_FUNC(int, system_can_boot_ap);
+
+#endif /* __TEST_AP_POWER_TEST_MOCKS_H */
diff --git a/zephyr/test/ap_power/include/test_state.h b/zephyr/test/ap_power/include/test_state.h
new file mode 100644
index 0000000000..2a7fbe822d
--- /dev/null
+++ b/zephyr/test/ap_power/include/test_state.h
@@ -0,0 +1,19 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef ZEPHYR_TEST_AP_POWER_INCLUDE_TEST_STATE_H_
+#define ZEPHYR_TEST_AP_POWER_INCLUDE_TEST_STATE_H_
+
+#include <stdbool.h>
+
+struct test_state {
+	bool ec_app_main_run;
+};
+
+bool ap_power_predicate_pre_main(const void *state);
+
+bool ap_power_predicate_post_main(const void *state);
+
+#endif /* ZEPHYR_TEST_AP_POWER_INCLUDE_TEST_STATE_H_ */
diff --git a/zephyr/test/ap_power/prj.conf b/zephyr/test/ap_power/prj.conf
new file mode 100644
index 0000000000..49e722a299
--- /dev/null
+++ b/zephyr/test/ap_power/prj.conf
@@ -0,0 +1,61 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_ZTEST=y
+CONFIG_ZTEST_ASSERT_VERBOSE=1
+CONFIG_ZTEST_MOCKING=y
+CONFIG_ZTEST_NEW_API=y
+CONFIG_ZTEST_PARAMETER_COUNT=24
+CONFIG_TEST=y
+CONFIG_ASSERT=y
+
+# Print logs from Zephyr LOG_MODULE to stdout
+CONFIG_NATIVE_UART_0_ON_STDINOUT=y
+
+# Simulate 10 ticks per ms
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=10000
+CONFIG_TASKS_SET_TEST_RUNNER_TID_RULE=y
+
+# Enable exception stack traces for better errors
+CONFIG_EXCEPTION_STACK_TRACE=y
+
+# Enable debugging features
+CONFIG_DEBUG=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_OPTIMIZATIONS=y
+CONFIG_PLATFORM_EC_CONSOLE_DEBUG=y
+CONFIG_SHELL_BACKEND_DUMMY=y
+CONFIG_SHELL_BACKEND_SERIAL=n
+# We aren't using the serial console, but there is still a lot of code that
+# assumes that a serial port exists.
+CONFIG_SERIAL=y
+
+CONFIG_PLATFORM_EC=y
+CONFIG_CROS_EC=y
+CONFIG_SHIMMED_TASKS=y
+CONFIG_EMUL=y
+CONFIG_GPIO=y
+CONFIG_HEAP_MEM_POOL_SIZE=1024
+
+CONFIG_AP_PWRSEQ_STACK_SIZE=1024
+
+CONFIG_ESPI=y
+CONFIG_EMUL_ESPI_HOST=y
+CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION=y
+CONFIG_ESPI_PERIPHERAL_CUSTOM_OPCODE=y
+CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD=y
+CONFIG_PLATFORM_EC_HOSTCMD=y
+CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK=y
+
+# Short delay for hibernate
+CONFIG_PLATFORM_EC_HIBERNATE_DELAY_SEC=20
+
+# These items are not required.
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
+CONFIG_PLATFORM_EC_SWITCH=n
+CONFIG_PLATFORM_EC_VBOOT_HASH=n
+
+CONFIG_PLATFORM_EC_LID_SWITCH=y
+CONFIG_PLATFORM_EC_POWER_BUTTON=y
+CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI=y
diff --git a/zephyr/test/ap_power/src/ap_pwrseq.c b/zephyr/test/ap_power/src/ap_pwrseq.c
new file mode 100644
index 0000000000..a968b0c38d
--- /dev/null
+++ b/zephyr/test/ap_power/src/ap_pwrseq.c
@@ -0,0 +1,307 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ap_power/ap_power.h"
+#include "ap_power/ap_power_interface.h"
+#include "chipset.h"
+#include "ec_commands.h"
+#include "emul/emul_power_signals.h"
+#include "host_command.h"
+#include "test_mocks.h"
+#include "test_state.h"
+
+#include <zephyr/drivers/espi.h>
+#include <zephyr/drivers/espi_emul.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/ztest.h>
+
+#include <ap_power/ap_pwrseq.h>
+
+static struct ap_power_ev_callback test_cb;
+static int power_resume_count;
+static int power_start_up_count;
+static int power_hard_off_count;
+static int power_shutdown_count;
+static int power_shutdown_complete_count;
+static int power_suspend_count;
+
+static void emul_ev_handler(struct ap_power_ev_callback *callback,
+			    struct ap_power_ev_data data)
+{
+	switch (data.event) {
+	case AP_POWER_RESUME:
+		power_resume_count++;
+		break;
+
+	case AP_POWER_STARTUP:
+		power_start_up_count++;
+		break;
+
+	case AP_POWER_HARD_OFF:
+		power_hard_off_count++;
+		break;
+
+	case AP_POWER_SHUTDOWN:
+		power_shutdown_count++;
+		break;
+
+	case AP_POWER_SHUTDOWN_COMPLETE:
+		power_shutdown_complete_count++;
+		break;
+
+	case AP_POWER_SUSPEND:
+		power_suspend_count++;
+		break;
+	default:
+		break;
+	};
+}
+
+static void ap_pwrseq_reset_ev_counters(void)
+{
+	power_resume_count = 0;
+	power_start_up_count = 0;
+	power_hard_off_count = 0;
+	power_shutdown_count = 0;
+	power_shutdown_complete_count = 0;
+	power_suspend_count = 0;
+}
+
+ZTEST(ap_pwrseq, test_ap_pwrseq_0)
+{
+	zassert_equal(0,
+		      power_signal_emul_load(
+			      EMUL_POWER_SIGNAL_TEST_PLATFORM(tp_sys_g3_to_s0)),
+		      "Unable to load test platform `tp_sys_g3_to_s0`");
+
+	k_msleep(500);
+
+	zassert_equal(1, power_start_up_count,
+		      "AP_POWER_STARTUP event not generated");
+	zassert_equal(1, power_resume_count,
+		      "AP_POWER_RESUME event not generated");
+}
+
+ZTEST(ap_pwrseq, test_ap_pwrseq_0_sleep)
+{
+	struct ec_params_host_sleep_event_v1 host_sleep_ev_p = {
+		.sleep_event = HOST_SLEEP_EVENT_S0IX_SUSPEND,
+		.suspend_params = { EC_HOST_SLEEP_TIMEOUT_DEFAULT },
+	};
+	struct ec_response_host_sleep_event_v1 host_sleep_ev_r;
+	struct host_cmd_handler_args host_sleep_ev_args = BUILD_HOST_COMMAND(
+		EC_CMD_HOST_SLEEP_EVENT, 1, host_sleep_ev_r, host_sleep_ev_p);
+
+	struct ec_params_s0ix_cnt s0ix_cnt_ev_p = {
+		.flags = EC_S0IX_COUNTER_RESET
+	};
+	struct ec_response_s0ix_cnt s0ix_cnt_ev_r;
+	struct host_cmd_handler_args s0ix_cnt_ev_args = BUILD_HOST_COMMAND(
+		EC_CMD_GET_S0IX_COUNTER, 0, s0ix_cnt_ev_r, s0ix_cnt_ev_p);
+
+	/* Verify that counter is set to 0 */
+	zassert_ok(host_command_process(&s0ix_cnt_ev_args),
+		   "Failed to get s0ix counter");
+	zassert_equal(s0ix_cnt_ev_r.s0ix_counter, 0);
+
+	/* Send host sleep event */
+	zassert_ok(host_command_process(&host_sleep_ev_args));
+
+	/* Assert SLP_S0# */
+	zassert_equal(0,
+		      power_signal_emul_load(
+			      EMUL_POWER_SIGNAL_TEST_PLATFORM(tp_sys_sleep)),
+		      "Unable to load test platform `tp_sys_g3_to_s0`");
+
+	k_msleep(500);
+
+	/*
+	 * Verify that counter has been increased,
+	 * clear the flag for get command
+	 */
+	s0ix_cnt_ev_p.flags = 0;
+	zassert_ok(host_command_process(&s0ix_cnt_ev_args),
+		   "Failed to get s0ix counter");
+	zassert_equal(s0ix_cnt_ev_r.s0ix_counter, 1);
+}
+
+ZTEST(ap_pwrseq, test_ap_pwrseq_0_wake)
+{
+	struct ec_params_host_sleep_event_v1 p = {
+		.sleep_event = HOST_SLEEP_EVENT_S0IX_RESUME,
+		.suspend_params = { EC_HOST_SLEEP_TIMEOUT_DEFAULT },
+	};
+	struct ec_response_host_sleep_event_v1 r;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_HOST_SLEEP_EVENT, 1, r, p);
+	struct ec_params_s0ix_cnt s0ix_cnt_ev_p = { .flags = 0 };
+	struct ec_response_s0ix_cnt s0ix_cnt_ev_r;
+	struct host_cmd_handler_args s0ix_cnt_ev_args = BUILD_HOST_COMMAND(
+		EC_CMD_GET_S0IX_COUNTER, 0, s0ix_cnt_ev_r, s0ix_cnt_ev_p);
+
+	/* Confirm that counters keeps the same value through wakeup */
+	zassert_ok(host_command_process(&s0ix_cnt_ev_args),
+		   "Failed to get s0ix counter");
+	zassert_equal(s0ix_cnt_ev_r.s0ix_counter, 1);
+
+	zassert_equal(0,
+		      power_signal_emul_load(
+			      EMUL_POWER_SIGNAL_TEST_PLATFORM(tp_sys_wake)),
+		      "Unable to load test platform `tp_sys_g3_to_s0`");
+
+	k_msleep(500);
+	zassert_ok(host_command_process(&args));
+	zassert_ok(host_command_process(&s0ix_cnt_ev_args),
+		   "Failed to get sleep counter");
+	zassert_equal(s0ix_cnt_ev_r.s0ix_counter, 1);
+
+	/* Verify the reset command sets the counter to zero */
+	s0ix_cnt_ev_p.flags = EC_S0IX_COUNTER_RESET;
+	zassert_ok(host_command_process(&s0ix_cnt_ev_args),
+		   "Failed to get s0ix counter");
+
+	s0ix_cnt_ev_p.flags = 0;
+	zassert_ok(host_command_process(&s0ix_cnt_ev_args),
+		   "Failed to get s0ix counter");
+	zassert_equal(s0ix_cnt_ev_r.s0ix_counter, 0);
+}
+
+ZTEST(ap_pwrseq, test_ap_pwrseq_1)
+{
+	zassert_equal(0,
+		      power_signal_emul_load(EMUL_POWER_SIGNAL_TEST_PLATFORM(
+			      tp_sys_s0_power_fail)),
+		      "Unable to load test platform `tp_sys_s0_power_fail`");
+
+	/*
+	 * Once emulated power signals are loaded, we need to wake AP power
+	 * Sequence thread up to start executing new set of power signals
+	 */
+	ap_pwrseq_wake();
+	k_msleep(500);
+	zassert_equal(1, power_shutdown_count,
+		      "AP_POWER_SHUTDOWN event not generated");
+	zassert_equal(1, power_shutdown_complete_count,
+		      "AP_POWER_SHUTDOWN_COMPLETE event not generated");
+	zassert_equal(0, power_suspend_count,
+		      "AP_POWER_SUSPEND event generated");
+}
+
+ZTEST(ap_pwrseq, test_ap_pwrseq_2)
+{
+	zassert_equal(
+		0,
+		power_signal_emul_load(EMUL_POWER_SIGNAL_TEST_PLATFORM(
+			tp_sys_g3_to_s0_power_down)),
+		"Unable to load test platform `tp_sys_g3_to_s0_power_down`");
+
+	ap_power_exit_hardoff();
+	k_msleep(2000);
+	zassert_equal(2, power_shutdown_count,
+		      "AP_POWER_SHUTDOWN event not generated");
+	zassert_equal(2, power_shutdown_complete_count,
+		      "AP_POWER_SHUTDOWN_COMPLETE event not generated");
+	zassert_equal(1, power_suspend_count,
+		      "AP_POWER_SUSPEND event not generated");
+	zassert_equal(1, power_hard_off_count,
+		      "AP_POWER_HARD_OFF event not generated");
+}
+
+ZTEST(ap_pwrseq, test_ap_pwrseq_3)
+{
+	zassert_equal(0,
+		      power_signal_emul_load(EMUL_POWER_SIGNAL_TEST_PLATFORM(
+			      tp_sys_s5_slp_sus_fail)),
+		      "Unable to load test platform `tp_sys_s5_slp_sus_fail`");
+
+	ap_power_exit_hardoff();
+	k_msleep(500);
+
+	zassert_equal(1, power_hard_off_count,
+		      "AP_POWER_HARD_OFF event not generated");
+}
+
+ZTEST(ap_pwrseq, test_ap_pwrseq_4)
+{
+	zassert_equal(
+		0,
+		power_signal_emul_load(EMUL_POWER_SIGNAL_TEST_PLATFORM(
+			tp_sys_s4_dsw_pwrok_fail)),
+		"Unable to load test platform `tp_sys_s4_dsw_pwrok_fail`");
+
+	ap_power_exit_hardoff();
+	k_msleep(500);
+
+	zassert_equal(0, power_hard_off_count,
+		      "AP_POWER_HARD_OFF event generated");
+	zassert_equal(1, power_shutdown_count,
+		      "AP_POWER_SHUTDOWN event not generated");
+	zassert_equal(1, power_shutdown_complete_count,
+		      "AP_POWER_SHUTDOWN_COMPLETE event not generated");
+}
+
+ZTEST(ap_pwrseq, test_ap_pwrseq_5)
+{
+	zassert_equal(
+		0,
+		power_signal_emul_load(EMUL_POWER_SIGNAL_TEST_PLATFORM(
+			tp_sys_s3_dsw_pwrok_fail)),
+		"Unable to load test platform `tp_sys_s3_dsw_pwrok_fail`");
+
+	ap_power_exit_hardoff();
+	k_msleep(500);
+
+	zassert_equal(0, power_hard_off_count,
+		      "AP_POWER_HARD_OFF event generated");
+	zassert_equal(1, power_shutdown_count,
+		      "AP_POWER_SHUTDOWN event not generated");
+	zassert_equal(1, power_shutdown_complete_count,
+		      "AP_POWER_SHUTDOWN_COMPLETE event not generated");
+}
+
+ZTEST(ap_pwrseq, test_insufficient_power_blocks_s5)
+{
+	zassert_equal(0,
+		      power_signal_emul_load(
+			      EMUL_POWER_SIGNAL_TEST_PLATFORM(tp_sys_g3_to_s0)),
+		      "Unable to load test platform `tp_sys_g3_to_s0`");
+	system_can_boot_ap_fake.return_val = 0;
+
+	ap_power_exit_hardoff();
+	k_msleep(5000);
+
+	zassert_equal(40, system_can_boot_ap_fake.call_count);
+	zassert_true(
+		chipset_in_or_transitioning_to_state(CHIPSET_STATE_HARD_OFF));
+}
+
+void ap_pwrseq_after_test(void *data)
+{
+	power_signal_emul_unload();
+	ap_pwrseq_reset_ev_counters();
+}
+
+void *ap_pwrseq_setup_suite(void)
+{
+	ap_power_ev_init_callback(&test_cb, emul_ev_handler,
+				  AP_POWER_RESUME | AP_POWER_STARTUP |
+					  AP_POWER_HARD_OFF | AP_POWER_SUSPEND |
+					  AP_POWER_SHUTDOWN |
+					  AP_POWER_SHUTDOWN_COMPLETE);
+
+	ap_power_ev_add_callback(&test_cb);
+
+	return NULL;
+}
+
+void ap_pwrseq_teardown_suite(void *data)
+{
+	ap_power_ev_remove_callback(&test_cb);
+}
+
+ZTEST_SUITE(ap_pwrseq, ap_power_predicate_post_main, ap_pwrseq_setup_suite,
+	    NULL, ap_pwrseq_after_test, NULL);
diff --git a/zephyr/test/ap_power/src/board.c b/zephyr/test/ap_power/src/board.c
new file mode 100644
index 0000000000..f08ccf9ef7
--- /dev/null
+++ b/zephyr/test/ap_power/src/board.c
@@ -0,0 +1,104 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+#include <ap_power/ap_power_interface.h>
+#include <ap_power_override_functions.h>
+#include <power_signals.h>
+#include <timer.h>
+#include <x86_power_signals.h>
+
+static bool signal_PWR_ALL_SYS_PWRGD;
+static bool signal_PWR_DSW_PWROK;
+static bool signal_PWR_PG_PP1P05;
+
+int board_power_signal_set(enum power_signal signal, int value)
+{
+	switch (signal) {
+	default:
+		zassert_unreachable("Unknown signal");
+		return -1;
+
+	case PWR_ALL_SYS_PWRGD:
+		signal_PWR_ALL_SYS_PWRGD = value;
+		return 0;
+
+	case PWR_DSW_PWROK:
+		signal_PWR_DSW_PWROK = value;
+		return 0;
+
+	case PWR_PG_PP1P05:
+		signal_PWR_PG_PP1P05 = value;
+		return 0;
+	}
+}
+
+int board_power_signal_get(enum power_signal signal)
+{
+	switch (signal) {
+	default:
+		zassert_unreachable("Unknown signal");
+		return -1;
+
+	case PWR_ALL_SYS_PWRGD:
+		return signal_PWR_ALL_SYS_PWRGD;
+
+	case PWR_DSW_PWROK:
+		return signal_PWR_DSW_PWROK;
+
+	case PWR_PG_PP1P05:
+		return signal_PWR_PG_PP1P05;
+	}
+}
+
+void board_ap_power_force_shutdown(void)
+{
+}
+
+int board_ap_power_assert_pch_power_ok(void)
+{
+	power_signal_set(PWR_PCH_PWROK, 1);
+	return 0;
+}
+
+static void generate_ec_soc_dsw_pwrok_handler(void)
+{
+	int in_sig_val = power_signal_get(PWR_DSW_PWROK);
+
+	if (in_sig_val != power_signal_get(PWR_EC_SOC_DSW_PWROK)) {
+		power_signal_set(PWR_EC_SOC_DSW_PWROK, 1);
+	}
+}
+
+void board_ap_power_action_g3_s5(void)
+{
+	power_signal_enable(PWR_DSW_PWROK);
+
+	power_signal_set(PWR_EN_PP3300_A, 1);
+	power_signal_set(PWR_EN_PP5000_A, 1);
+
+	power_wait_signals_timeout(IN_PGOOD_ALL_CORE, 100 * MSEC);
+
+	generate_ec_soc_dsw_pwrok_handler();
+}
+
+void board_ap_power_action_s3_s0(void)
+{
+}
+
+void board_ap_power_action_s0_s3(void)
+{
+}
+
+void board_ap_power_action_s0(void)
+{
+}
+
+bool board_ap_power_check_power_rails_enabled(void)
+{
+	return true;
+}
diff --git a/zephyr/test/ap_power/src/console_command.c b/zephyr/test/ap_power/src/console_command.c
new file mode 100644
index 0000000000..7789a13919
--- /dev/null
+++ b/zephyr/test/ap_power/src/console_command.c
@@ -0,0 +1,32 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "ec_commands.h"
+#include "test_state.h"
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+ZTEST_USER(console_cmd_debug_mode, test_debug_mode_default)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "debug_mode"),
+		   "failed to get debug_mode");
+}
+
+ZTEST_USER(console_cmd_debug_mode, test_debug_mode_disabled)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "debug_mode disable"),
+		   "failed to disable debug_mode");
+}
+
+ZTEST_USER(console_cmd_debug_mode, test_debug_mode_enabled)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "debug_mode enable"),
+		   "failed to enable debug_mode");
+}
+
+ZTEST_SUITE(console_cmd_debug_mode, ap_power_predicate_post_main, NULL, NULL,
+	    NULL, NULL);
diff --git a/zephyr/test/ap_power/src/events.c b/zephyr/test/ap_power/src/events.c
new file mode 100644
index 0000000000..2528d356f6
--- /dev/null
+++ b/zephyr/test/ap_power/src/events.c
@@ -0,0 +1,190 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ * @brief Unit Tests for AP power events
+ */
+
+#include "ap_power/ap_power.h"
+#include "ap_power/ap_power_events.h"
+#include "hooks.h"
+#include "test_state.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/espi.h>
+#include <zephyr/drivers/espi_emul.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/ztest.h>
+
+/*
+ * Structure passed to event listeners.
+ */
+struct events {
+	struct ap_power_ev_callback cb;
+	enum ap_power_events event;
+	int count;
+};
+
+/*
+ * Common handler.
+ * Increment count, and store event received.
+ */
+static void ev_handler(struct ap_power_ev_callback *callback,
+		       struct ap_power_ev_data data)
+{
+	struct events *ev = CONTAINER_OF(callback, struct events, cb);
+
+	ev->count++;
+	ev->event = data.event;
+}
+
+/**
+ * @brief TestPurpose: Check registration
+ *
+ * @details
+ * Validate that listeners can be registered, even multiple times
+ *
+ * Expected Results
+ *  - Multiple registrations do not result in multiple calls.
+ */
+ZTEST(events, test_registration)
+{
+	static struct events cb;
+
+	ap_power_ev_init_callback(&cb.cb, ev_handler, AP_POWER_RESET);
+	ap_power_ev_add_callback(&cb.cb);
+	ap_power_ev_send_callbacks(AP_POWER_RESET);
+	zassert_equal(1, cb.count, "Callback not called");
+	zassert_equal(AP_POWER_RESET, cb.event, "Wrong event");
+	ap_power_ev_send_callbacks(AP_POWER_SUSPEND);
+	zassert_equal(1, cb.count, "Callback called");
+
+	ap_power_ev_remove_callback(&cb.cb);
+	ap_power_ev_send_callbacks(AP_POWER_RESET);
+	zassert_equal(1, cb.count, "Callback called");
+	cb.count = 0; /* Reset to make it clear */
+	cb.event = 0;
+	/* Add it twice */
+	ap_power_ev_add_callback(&cb.cb);
+	ap_power_ev_add_callback(&cb.cb);
+	ap_power_ev_send_callbacks(AP_POWER_RESET);
+	zassert_equal(1, cb.count, "Callback not called");
+	zassert_equal(AP_POWER_RESET, cb.event, "Wrong event");
+	ap_power_ev_remove_callback(&cb.cb);
+	/* Second remove should be no-op */
+	ap_power_ev_remove_callback(&cb.cb);
+}
+
+/**
+ * @brief TestPurpose: Verify reset callback from ESPI
+ *
+ * @details
+ * Validate that the reset callback is sent with ESPI PLTRST#
+ *
+ * Expected Results
+ *  - The AP_POWER_RESET event is sent
+ */
+ZTEST(events, test_pltrst)
+{
+	static struct events cb;
+	const struct device *espi =
+		DEVICE_DT_GET_ANY(zephyr_espi_emul_controller);
+
+	zassert_not_null(espi, "Cannot get ESPI device");
+
+	ap_power_ev_init_callback(&cb.cb, ev_handler, AP_POWER_RESET);
+	ap_power_ev_add_callback(&cb.cb);
+
+	emul_espi_host_send_vw(espi, ESPI_VWIRE_SIGNAL_PLTRST, 0);
+	/*
+	 * Since the event is being sent via a deferred function,
+	 * wait for the deferral time.
+	 */
+	k_usleep(2 * 1000);
+	zassert_equal(1, cb.count, "Callback not called");
+	zassert_equal(AP_POWER_RESET, cb.event, "Wrong event");
+}
+
+/**
+ * @brief TestPurpose: Check event mask changes
+ *
+ * @details
+ * Validate that listeners adjust the event mask.
+ *
+ * Expected Results
+ *  - Event mask changes are honoured
+ */
+ZTEST(events, test_event_mask)
+{
+	static struct events cb;
+
+	ap_power_ev_init_callback(&cb.cb, ev_handler, 0);
+	ap_power_ev_add_callback(&cb.cb);
+	ap_power_ev_send_callbacks(AP_POWER_RESET);
+	zassert_equal(0, cb.count, "Callback called");
+	ap_power_ev_init_callback(&cb.cb, ev_handler, AP_POWER_RESET);
+
+	ap_power_ev_send_callbacks(AP_POWER_RESET);
+	zassert_equal(1, cb.count, "Callback not called");
+	ap_power_ev_send_callbacks(AP_POWER_SUSPEND);
+	zassert_equal(1, cb.count, "Callback called");
+
+	/* Add interest in event */
+	cb.count = 0;
+	ap_power_ev_add_events(&cb.cb, AP_POWER_SUSPEND);
+	ap_power_ev_send_callbacks(AP_POWER_RESET);
+	zassert_equal(1, cb.count, "Callback not called");
+	zassert_equal(AP_POWER_RESET, cb.event, "Wrong event");
+	ap_power_ev_send_callbacks(AP_POWER_SUSPEND);
+	zassert_equal(2, cb.count, "Callback not called");
+	zassert_equal(AP_POWER_SUSPEND, cb.event, "Wrong event");
+
+	ap_power_ev_remove_callback(&cb.cb);
+}
+
+static int count_hook_shutdown, count_hook_startup;
+
+static void hook_shutdown(void)
+{
+	count_hook_shutdown++;
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, hook_shutdown, HOOK_PRIO_DEFAULT);
+
+static void hook_startup(void)
+{
+	count_hook_startup++;
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, hook_startup, HOOK_PRIO_DEFAULT);
+
+/**
+ * @brief TestPurpose: Verify correct interconnection with hook framework.
+ *
+ * @details
+ * Validate that events get passed back to the hook subsystem.
+ *
+ * Expected Results
+ *  - Events originating from the AP power event API get delivered via hooks.
+ */
+ZTEST(events, test_hooks)
+{
+	count_hook_startup = count_hook_shutdown = 0;
+	ap_power_ev_send_callbacks(AP_POWER_STARTUP);
+	zassert_equal(0, count_hook_shutdown, "shutdown hook called");
+	zassert_equal(1, count_hook_startup, "startup hook not called");
+	zassert_equal(0, count_hook_shutdown,
+		      "reset event, shutdown hook called");
+	zassert_equal(1, count_hook_startup,
+		      "reset event, startup hook called");
+	ap_power_ev_send_callbacks(AP_POWER_SHUTDOWN);
+	zassert_equal(1, count_hook_shutdown, "shutdown hook not called");
+	zassert_equal(1, count_hook_startup, "startup hook called");
+}
+
+/**
+ * @brief Test Suite: Verifies AP power notification functionality.
+ */
+ZTEST_SUITE(events, ap_power_predicate_post_main, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/ap_power/src/hibdelay.c b/zephyr/test/ap_power/src/hibdelay.c
new file mode 100644
index 0000000000..11fac953ea
--- /dev/null
+++ b/zephyr/test/ap_power/src/hibdelay.c
@@ -0,0 +1,37 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "ec_commands.h"
+#include "test_state.h"
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+ZTEST_SUITE(console_cmd_hibdelay, ap_power_predicate_post_main, NULL, NULL,
+	    NULL, NULL);
+
+ZTEST_USER(console_cmd_hibdelay, test_too_many_args)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "hibdelay 1 2"), NULL);
+}
+
+ZTEST_USER(console_cmd_hibdelay, test_no_args)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "hibdelay"), NULL);
+}
+
+ZTEST_USER(console_cmd_hibdelay, test_invalid_arg)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "hibdelay 3.4");
+
+	zassert_equal(rv, EC_ERROR_PARAM1, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+}
+
+ZTEST_USER(console_cmd_hibdelay, test_valid_args)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "hibdelay 5"), NULL);
+}
diff --git a/zephyr/test/ap_power/src/hibernate.c b/zephyr/test/ap_power/src/hibernate.c
new file mode 100644
index 0000000000..23030bdcb3
--- /dev/null
+++ b/zephyr/test/ap_power/src/hibernate.c
@@ -0,0 +1,39 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "hooks.h"
+#include "test_mocks.h"
+#include "test_state.h"
+
+#include <zephyr/device.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/ztest.h>
+
+#include <ap_power/ap_power.h>
+#include <ap_power/ap_power_events.h>
+#include <ap_power/ap_power_interface.h>
+
+ZTEST(hibernate, test_g3_hibernate)
+{
+	extpower_is_present_fake.return_val = 0;
+	ap_power_ev_send_callbacks(AP_POWER_HARD_OFF);
+	k_sleep(K_SECONDS(30));
+	zassert_equal(1, system_hibernate_fake.call_count);
+}
+
+ZTEST(hibernate, test_ac_changed)
+{
+	extpower_is_present_fake.return_val = 1;
+	hook_notify(HOOK_AC_CHANGE);
+	k_sleep(K_SECONDS(30));
+	zassert_equal(0, system_hibernate_fake.call_count);
+	extpower_is_present_fake.return_val = 0;
+	hook_notify(HOOK_AC_CHANGE);
+	k_sleep(K_SECONDS(30));
+	zassert_equal(1, system_hibernate_fake.call_count);
+}
+
+ZTEST_SUITE(hibernate, ap_power_predicate_post_main, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/ap_power/src/host_command.c b/zephyr/test/ap_power/src/host_command.c
new file mode 100644
index 0000000000..1898bb86b5
--- /dev/null
+++ b/zephyr/test/ap_power/src/host_command.c
@@ -0,0 +1,25 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+#include "host_command.h"
+#include "test_state.h"
+
+#include <zephyr/ztest.h>
+
+ZTEST(host_cmd, test_hibernate_get)
+{
+	struct ec_response_hibernation_delay response;
+	struct ec_params_hibernation_delay params = {
+		.seconds = 0,
+	};
+
+	zassert_ok(ec_cmd_hibernation_delay(NULL, &params, &response));
+	params.seconds = 123;
+	zassert_ok(ec_cmd_hibernation_delay(NULL, &params, &response));
+	zassert_equal(123, response.hibernate_delay, NULL);
+}
+
+ZTEST_SUITE(host_cmd, ap_power_predicate_post_main, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/ap_power/src/main.c b/zephyr/test/ap_power/src/main.c
new file mode 100644
index 0000000000..9ed34eee4a
--- /dev/null
+++ b/zephyr/test/ap_power/src/main.c
@@ -0,0 +1,39 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_app_main.h"
+#include "test_state.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+bool ap_power_predicate_pre_main(const void *state)
+{
+	return ((struct test_state *)state)->ec_app_main_run == false;
+}
+
+bool ap_power_predicate_post_main(const void *state)
+{
+	return !ap_power_predicate_pre_main(state);
+}
+
+void test_main(void)
+{
+	struct test_state state = {
+		.ec_app_main_run = false,
+	};
+
+	/* Run all the suites that depend on main not being called yet */
+	ztest_run_test_suites(&state);
+
+	ec_app_main();
+	state.ec_app_main_run = true;
+
+	/* Run all the suites that depend on main being called */
+	ztest_run_test_suites(&state);
+
+	/* Check that every suite ran */
+	ztest_verify_all_test_suites_ran();
+}
diff --git a/zephyr/test/ap_power/src/signals.c b/zephyr/test/ap_power/src/signals.c
new file mode 100644
index 0000000000..3547243f8c
--- /dev/null
+++ b/zephyr/test/ap_power/src/signals.c
@@ -0,0 +1,523 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ * @brief Unit Tests for power signals API
+ */
+
+#include "ec_tasks.h"
+#include "emul/emul_stub_device.h"
+#include "gpio.h"
+#include "gpio/gpio.h"
+#include "gpio/gpio_int.h"
+#include "power_signals.h"
+#include "test_state.h"
+#include "vcmp_mock.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/espi.h>
+#include <zephyr/drivers/espi_emul.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/drivers/sensor.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/ztest.h>
+
+extern bool gpio_test_interrupt_triggered;
+
+static const struct device *emul_port;
+
+/*
+ * Map of signal to GPIO pin.
+ * This must match overlay.dts
+ */
+static struct {
+	enum power_signal signal;
+	int pin;
+} signal_to_pin_table[] = {
+	{ PWR_EN_PP5000_A, 10 }, { PWR_EN_PP3300_A, 11 },
+	{ PWR_RSMRST, 12 },	 { PWR_EC_PCH_RSMRST, 13 },
+	{ PWR_SLP_S0, 14 },	 { PWR_SLP_S3, 15 },
+	{ PWR_SLP_SUS, 16 },	 { PWR_EC_SOC_DSW_PWROK, 17 },
+	{ PWR_VCCST_PWRGD, 18 }, { PWR_IMVP9_VRRDY, 19 },
+	{ PWR_PCH_PWROK, 20 },	 { PWR_EC_PCH_SYS_PWROK, 21 },
+	{ PWR_SYS_RST, 22 },
+};
+
+/*
+ * Retrieve the GPIO pin number corresponding to this signal.
+ */
+static int signal_to_pin(enum power_signal signal)
+{
+	for (int i = 0; i < ARRAY_SIZE(signal_to_pin_table); i++) {
+		if (signal_to_pin_table[i].signal == signal) {
+			return signal_to_pin_table[i].pin;
+		}
+	}
+	zassert_unreachable("Unknown signal");
+	return -1;
+}
+
+/*
+ * Set the raw input of the corresponding GPIO
+ */
+static void emul_set(enum power_signal signal, int value)
+{
+	gpio_emul_input_set(emul_port, signal_to_pin(signal), value);
+}
+
+/*
+ * Get the raw output of the corresponding GPIO
+ */
+static int emul_get(enum power_signal signal)
+{
+	return gpio_emul_output_get(emul_port, signal_to_pin(signal));
+}
+
+/**
+ * @brief TestPurpose: Check input/output validation
+ *
+ * @details
+ * Validate that input/output GPIOs do not accept invalidate requests.
+ *
+ * Expected Results
+ *  - Error when invalid requests are made.
+ */
+ZTEST(signals, test_validate_request)
+{
+	/* Can't set output on input */
+	zassert_equal(-EINVAL, power_signal_set(PWR_SLP_S0, 1),
+		      "power_signal_set on input pin should not succeed");
+	/* Can't enable interrupt on output */
+	zassert_equal(-EINVAL, power_signal_enable(PWR_VCCST_PWRGD),
+		      "enable interrupt on output pin should not succeed");
+	/* Can't disable interrupt on output */
+	zassert_equal(-EINVAL, power_signal_disable(PWR_VCCST_PWRGD),
+		      "disable interrupt on output pin should not succeed");
+	/* Can't enable interrupt on input with no interrupt flags */
+	zassert_equal(-EINVAL, power_signal_enable(PWR_IMVP9_VRRDY),
+		      "enable interrupt on input pin without interrupt config");
+	/* Can't disable interrupt on input with no interrupt flags */
+	zassert_equal(
+		-EINVAL, power_signal_disable(PWR_IMVP9_VRRDY),
+		"disable interrupt on input pin without interrupt config");
+	/* Invalid signal - should be rejectde */
+	zassert_equal(-EINVAL, power_signal_get(-1),
+		      "power_signal_get with -1 signal should fail");
+	zassert_equal(-EINVAL, power_signal_set(-1, 1),
+		      "power_signal_set with -1 signal should fail");
+	zassert_equal(-EINVAL, power_signal_enable(-1),
+		      "enable interrupt with -1 signal should fail");
+	zassert_equal(-EINVAL, power_signal_disable(-1),
+		      "disable interrupt with -1 signal should fail");
+}
+
+/**
+ * @brief TestPurpose: Verify board specific signals
+ *
+ * @details
+ * Validate access to board specific signals
+ *
+ * Expected Results
+ *  - Can set and get board specific signals.
+ */
+ZTEST(signals, test_board_signals)
+{
+	/*
+	 * Check that the board level signals get correctly invoked.
+	 */
+	zassert_ok(power_signal_set(PWR_ALL_SYS_PWRGD, 1),
+		   "power_signal_set on board signal failed");
+	zassert_equal(1, power_signal_get(PWR_ALL_SYS_PWRGD),
+		      "power_signal_get on board signal should return 1");
+}
+
+/**
+ * @brief TestPurpose: Check name retrieval
+ *
+ * @details
+ * Validate out of bounds request
+ *
+ * Expected Results
+ *  - Retrieve name or null for request.
+ */
+ZTEST(signals, test_signal_name)
+{
+	for (int signal = 0; signal < POWER_SIGNAL_COUNT; signal++) {
+		zassert_not_null(power_signal_name(signal),
+				 "Signal name for %d should be not null",
+				 signal);
+	}
+	zassert_is_null(power_signal_name(-1),
+			"Out of bounds signal name should be null");
+	zassert_is_null(power_signal_name(POWER_SIGNAL_COUNT),
+			"Out of bounds signal name should be null");
+}
+
+/**
+ * @brief TestPurpose: Verify output signals are de-asserted at startup.
+ *
+ * @details
+ * Confirm that output signals are initialised correctly.
+ * Output pins are by default set to a de-asserted state at start-up, so
+ * signals that are active-low should be set to physical high, signals
+ * that are active-high should be set to physical low.
+ * In overlay.dts, the only output power signal that is active-low is
+ * PWR_SYS_RST
+ *
+ * Expected Results
+ *  - Output signals are initialised as de-asserted.
+ */
+ZTEST(signals, test_init_outputs)
+{
+	static const enum power_signal active_high[] = {
+		PWR_EN_PP5000_A, PWR_EN_PP3300_A, PWR_EC_PCH_RSMRST,
+		PWR_EC_SOC_DSW_PWROK, PWR_PCH_PWROK
+	};
+	static const enum power_signal active_low[] = { PWR_SYS_RST };
+
+	for (int i = 0; i < ARRAY_SIZE(active_high); i++) {
+		zassert_equal(0, emul_get(active_high[i]),
+			      "Signal %d (%s) init to de-asserted state failed",
+			      active_high[i],
+			      power_signal_name(active_high[i]));
+	}
+	for (int i = 0; i < ARRAY_SIZE(active_low); i++) {
+		zassert_equal(1, emul_get(active_low[i]),
+			      "Signal %d (%s) init to de-asserted state failed",
+			      active_low[i], power_signal_name(active_low[i]));
+	}
+}
+
+/**
+ * @brief TestPurpose: Verify input signals are read correctly
+ *
+ * @details
+ * Confirm that input signals are read correctly. Signal values
+ * are set via the GPIO emul driver.
+ *
+ * Expected Results
+ *  - Input signals are read correctly.
+ */
+ZTEST(signals, test_gpio_input)
+{
+	emul_set(PWR_RSMRST, 1);
+	zassert_equal(1, power_signal_get(PWR_RSMRST),
+		      "power_signal_get of PWR_RSMRST should be 1");
+	emul_set(PWR_RSMRST, 0);
+	zassert_equal(0, power_signal_get(PWR_RSMRST),
+		      "power_signal_get of PWR_RSMRST should be 0");
+	/* ACTIVE_LOW input */
+	emul_set(PWR_SLP_S0, 0);
+	zassert_equal(
+		1, power_signal_get(PWR_SLP_S0),
+		"power_signal_get of active-low signal PWR_SLP_S0 should be 1");
+	emul_set(PWR_SLP_S0, 1);
+	zassert_equal(0, power_signal_get(PWR_SLP_S0),
+		      "power_signal_get of active-low PWR_SLP_S0 should be 0");
+}
+
+/**
+ * @brief TestPurpose: Verify output signals are written correctly
+ *
+ * @details
+ * Confirm that output signals are written correctly.
+ *
+ * Expected Results
+ *  - Set signals are written correctly
+ */
+ZTEST(signals, test_gpio_output)
+{
+	power_signal_set(PWR_PCH_PWROK, 1);
+	zassert_equal(1, emul_get(PWR_PCH_PWROK),
+		      "power_signal_set of PWR_PCH_PWROK should be 1");
+	power_signal_set(PWR_PCH_PWROK, 0);
+	zassert_equal(0, emul_get(PWR_PCH_PWROK),
+		      "power_signal_set of PWR_PCH_PWROK should be 0");
+	/* ACTIVE_LOW output */
+	power_signal_set(PWR_SYS_RST, 0);
+	zassert_equal(1, emul_get(PWR_SYS_RST),
+		      "power_signal_set of PWR_SYS_RST should be 1");
+	power_signal_set(PWR_SYS_RST, 1);
+	zassert_equal(0, emul_get(PWR_SYS_RST),
+		      "power_signal_set of PWR_SYS_RST should be 0");
+}
+
+/**
+ * @brief TestPurpose: Verify signal mask handling
+ *
+ * @details
+ * Confirm that signal mask processing works as expected,
+ * such as checking that pin changes send interrupts that
+ * modifies the power signal mask.
+ *
+ * Expected Results
+ *  - Multiple signal mask processing works
+ */
+ZTEST(signals, test_signal_mask)
+{
+	power_signal_mask_t vm = POWER_SIGNAL_MASK(PWR_IMVP9_VRRDY);
+	power_signal_mask_t bm = POWER_SIGNAL_MASK(PWR_ALL_SYS_PWRGD);
+	power_signal_mask_t m;
+
+	/*
+	 * Set board level (polled) signal.
+	 */
+	power_signal_set(PWR_ALL_SYS_PWRGD, 1);
+	zassert_equal(
+		bm, (power_get_signals() & bm),
+		"Expected PWR_ALL_SYS_PWRGD signal to be present in mask");
+	/*
+	 * Use GPIO that does not interrupt to confirm that a pin change
+	 * will not update the power signal mask.
+	 */
+	emul_set(PWR_IMVP9_VRRDY, 0);
+	m = power_get_signals() & vm;
+	zassert_equal(0, (power_get_signals() & vm), "Expected mask to be 0");
+	emul_set(PWR_IMVP9_VRRDY, 1);
+	zassert_equal(0, (power_get_signals() & vm), "Expected mask to be 0");
+	zassert_equal(true, power_signals_match(bm, bm),
+		      "Expected match of mask to signal match");
+	zassert_equal(-ETIMEDOUT, power_wait_mask_signals_timeout(bm, 0, 5),
+		      "Expected timeout waiting for mask to be 0");
+	zassert_ok(power_wait_mask_signals_timeout(0, vm, 5),
+		   "expected match with a 0 mask (always true)");
+}
+
+/**
+ * @brief TestPurpose: Verify set/get of debug mask
+ *
+ * @details
+ * Confirm that debug mask setting works
+ *
+ * Expected Results
+ *  - Can set/get debug mask
+ */
+ZTEST(signals, test_debug_mask)
+{
+	power_signal_mask_t old;
+	power_signal_mask_t dm = 0xDEADBEEF;
+
+	old = power_get_debug();
+	power_set_debug(dm);
+	zassert_equal(dm, power_get_debug(),
+		      "Debug mask does not match set value");
+	/*
+	 * Reset back to default.
+	 */
+	power_set_debug(old);
+}
+
+/**
+ * @brief TestPurpose: Verify interrupts work as expected
+ *
+ * @details
+ * For no-enable interrupts, ensure that they are not enabled at the start.
+ * For default, ensure that the interrupts are enabled.
+ * Check that enable/disable interrupt works.
+ *
+ * Expected Results
+ *  - interrupt enabling/disabling works
+ */
+ZTEST(signals, test_gpio_interrupts)
+{
+	power_signal_mask_t rsm = POWER_SIGNAL_MASK(PWR_RSMRST);
+	power_signal_mask_t s3 = POWER_SIGNAL_MASK(PWR_SLP_S3);
+	power_signal_mask_t s0 = POWER_SIGNAL_MASK(PWR_SLP_S0);
+
+	/* Check that GPIO pin changes update the signal mask. */
+	emul_set(PWR_RSMRST, 1);
+	zassert_equal(true, power_signals_on(rsm),
+		      "PWR_RSMRST not updated in mask");
+	emul_set(PWR_RSMRST, 0);
+	zassert_equal(true, power_signals_off(rsm),
+		      "PWR_RSMRST not updated in mask");
+
+	/*
+	 * Check that an ACTIVE_LOW signal gets asserted in
+	 * the mask (physical value of GPIO pin 0 is set as 1 in mask)
+	 */
+	emul_set(PWR_SLP_S3, 0);
+	zassert_equal(true, power_signals_on(s3),
+		      "SLP_S3 signal should be on in mask");
+	emul_set(PWR_SLP_S3, 1);
+	zassert_equal(true, power_signals_off(s3),
+		      "SLP_S3 should be off in mask");
+
+	/*
+	 * Check that disabled interrupt on the GPIO does not trigger
+	 * and update the mask.
+	 */
+	emul_set(PWR_SLP_S0, 0);
+	zassert_equal(false, power_signals_on(s0),
+		      "SLP_S0 should not have updated");
+	emul_set(PWR_SLP_S0, 1);
+	zassert_equal(false, power_signals_on(s0),
+		      "SLP_S0 should not have updated");
+
+	power_signal_enable(PWR_SLP_S0);
+	emul_set(PWR_SLP_S0, 0);
+	zassert_equal(true, power_signals_on(s0),
+		      "SLP_S0 should have updated the mask");
+	emul_set(PWR_SLP_S0, 1);
+	zassert_equal(true, power_signals_off(s0),
+		      "SLP_S0 should have updated the mask");
+
+	/*
+	 * Disable the GPIO interrupt again.
+	 */
+	power_signal_disable(PWR_SLP_S0);
+	emul_set(PWR_SLP_S0, 0);
+	zassert_equal(false, power_signals_on(s0),
+		      "SLP_S0 should not have updated the mask");
+	emul_set(PWR_SLP_S0, 1);
+	zassert_equal(true, power_signals_off(s0),
+		      "SLP_S0 should not have updated the mask");
+}
+
+/**
+ * @brief TestPurpose: Verify reception of VW signals
+ *
+ * @details
+ * Confirm that ESPI virtual wire signals can be received.
+ *
+ * Expected Results
+ *  - Virtual wire signals are received.
+ */
+ZTEST(signals, test_espi_vw)
+{
+	const struct device *espi =
+		DEVICE_DT_GET_ANY(zephyr_espi_emul_controller);
+
+	zassert_not_null(espi, "Cannot get ESPI device");
+	/*
+	 * Send a VW signal, and check that it is received.
+	 * The signal is configured as an inverted signal,
+	 * so sending a 0 value should be received as a signal.
+	 */
+	emul_espi_host_send_vw(espi, ESPI_VWIRE_SIGNAL_SLP_S5, 0);
+	zassert_equal(1, power_signal_get(PWR_SLP_S5), "VW SLP_S5 should be 1");
+	emul_espi_host_send_vw(espi, ESPI_VWIRE_SIGNAL_SLP_S5, 1);
+	zassert_equal(0, power_signal_get(PWR_SLP_S5), "VW SLP_S5 should be 0");
+}
+
+enum trigger_expect {
+	ADC_TRIG_NONE,
+	ADC_TRIG_HIGH,
+	ADC_TRIG_LOW,
+};
+
+static void check_adc_triggers(enum trigger_expect expect)
+{
+	const struct device *trigger_high =
+		DEVICE_DT_GET(DT_NODELABEL(mock_cmp_high));
+	const struct device *trigger_low =
+		DEVICE_DT_GET(DT_NODELABEL(mock_cmp_low));
+	struct sensor_value val_high;
+	struct sensor_value val_low;
+
+	sensor_attr_get(trigger_high, SENSOR_CHAN_VOLTAGE, SENSOR_ATTR_ALERT,
+			&val_high);
+	sensor_attr_get(trigger_low, SENSOR_CHAN_VOLTAGE, SENSOR_ATTR_ALERT,
+			&val_low);
+	switch (expect) {
+	case ADC_TRIG_NONE:
+		zassert_equal(0, val_high.val1,
+			      "high trigger should be disabled");
+		zassert_equal(0, val_low.val1,
+			      "low trigger should be disabled");
+		break;
+	case ADC_TRIG_HIGH:
+		zassert_equal(1, val_high.val1,
+			      "high trigger should be enabled");
+		zassert_equal(0, val_low.val1,
+			      "low trigger should be disabled");
+		break;
+	case ADC_TRIG_LOW:
+		zassert_equal(0, val_high.val1,
+			      "high trigger should be disabled");
+		zassert_equal(1, val_low.val1, "low trigger should be enabled");
+		break;
+	}
+}
+
+ZTEST(signals, test_adc_get)
+{
+	const struct device *trigger_high =
+		DEVICE_DT_GET(DT_NODELABEL(mock_cmp_high));
+	const struct device *trigger_low =
+		DEVICE_DT_GET(DT_NODELABEL(mock_cmp_low));
+
+	/* Always start low */
+	vcmp_mock_trigger(trigger_low);
+
+	zassert_equal(0, power_signal_get(PWR_PG_PP1P05),
+		      "power_signal_get of PWR_PG_PP1P05 should be 0");
+	check_adc_triggers(ADC_TRIG_HIGH);
+
+	/* Signal goes up... */
+	vcmp_mock_trigger(trigger_high);
+
+	zassert_equal(1, power_signal_get(PWR_PG_PP1P05),
+		      "power_signal_get of PWR_PG_PP1P05 should be 1");
+	check_adc_triggers(ADC_TRIG_LOW);
+
+	/* ...signal goes down. */
+	vcmp_mock_trigger(trigger_low);
+
+	zassert_equal(0, power_signal_get(PWR_PG_PP1P05),
+		      "power_signal_get of PWR_PG_PP1P05 should be 0");
+	check_adc_triggers(ADC_TRIG_HIGH);
+}
+
+ZTEST(signals, test_adc_enable_disable)
+{
+	const struct device *trigger_high =
+		DEVICE_DT_GET(DT_NODELABEL(mock_cmp_high));
+	const struct device *trigger_low =
+		DEVICE_DT_GET(DT_NODELABEL(mock_cmp_low));
+
+	/* Always start from low */
+	vcmp_mock_trigger(trigger_low);
+	check_adc_triggers(ADC_TRIG_HIGH);
+
+	power_signal_disable(PWR_PG_PP1P05);
+	check_adc_triggers(ADC_TRIG_NONE);
+
+	power_signal_enable(PWR_PG_PP1P05);
+	check_adc_triggers(ADC_TRIG_HIGH);
+
+	vcmp_mock_trigger(trigger_high);
+	check_adc_triggers(ADC_TRIG_LOW);
+
+	power_signal_disable(PWR_PG_PP1P05);
+	check_adc_triggers(ADC_TRIG_NONE);
+
+	power_signal_enable(PWR_PG_PP1P05);
+	check_adc_triggers(ADC_TRIG_LOW);
+}
+
+static void *init_dev(void)
+{
+	emul_port = DEVICE_DT_GET(DT_NODELABEL(gpio0));
+
+	return NULL;
+}
+
+static void init_signals(void *data)
+{
+	power_signal_init();
+}
+
+/**
+ * @brief Test Suite: Verifies power signal functionality.
+ */
+ZTEST_SUITE(signals, ap_power_predicate_post_main, init_dev, init_signals, NULL,
+	    NULL);
+
+/* These 2 lines are needed because we don't define an espi host driver */
+#define DT_DRV_COMPAT zephyr_espi_emul_espi_host
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
diff --git a/zephyr/test/ap_power/src/test_mocks.c b/zephyr/test/ap_power/src/test_mocks.c
new file mode 100644
index 0000000000..b22b9ddd0b
--- /dev/null
+++ b/zephyr/test/ap_power/src/test_mocks.c
@@ -0,0 +1,33 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "test_mocks.h"
+
+#include <zephyr/fff.h>
+#include <zephyr/ztest.h>
+
+/* Mocks for common/extpower_gpio.c */
+DEFINE_FAKE_VALUE_FUNC(int, extpower_is_present);
+
+/* Mocks for common/system.c */
+DEFINE_FAKE_VOID_FUNC(system_hibernate, uint32_t, uint32_t);
+DEFINE_FAKE_VALUE_FUNC(int, system_can_boot_ap);
+
+/**
+ * @brief Reset all the fakes before each test.
+ */
+static void fff_reset_rule_before(const struct ztest_unit_test *test,
+				  void *data)
+{
+	ARG_UNUSED(test);
+	ARG_UNUSED(data);
+
+	RESET_FAKE(extpower_is_present);
+	RESET_FAKE(system_hibernate);
+	RESET_FAKE(system_can_boot_ap);
+	system_can_boot_ap_fake.return_val = 1;
+}
+
+ZTEST_RULE(fff_reset_rule, fff_reset_rule_before, NULL);
diff --git a/zephyr/test/ap_power/testcase.yaml b/zephyr/test/ap_power/testcase.yaml
new file mode 100644
index 0000000000..cba1157944
--- /dev/null
+++ b/zephyr/test/ap_power/testcase.yaml
@@ -0,0 +1,14 @@
+common:
+  platform_allow: native_posix
+tests:
+  ap_power.alderlake:
+    extra_dtc_overlay_files:
+    - boards/native_posix.overlay
+    - boards/alderlake.dts
+    extra_configs:
+    - CONFIG_EMUL_POWER_SIGNALS=y
+    - CONFIG_X86_NON_DSX_PWRSEQ_ADL=y
+    - CONFIG_AP_PWRSEQ_S0IX=y
+    - CONFIG_AP_X86_INTEL_ADL=y
+    - CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S4=y
+    - CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S5=y
diff --git a/zephyr/test/base32/CMakeLists.txt b/zephyr/test/base32/CMakeLists.txt
new file mode 100644
index 0000000000..97e01b0ab7
--- /dev/null
+++ b/zephyr/test/base32/CMakeLists.txt
@@ -0,0 +1,9 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(base32)
+
+target_sources(app PRIVATE "${PLATFORM_EC}/test/base32.c")
diff --git a/zephyr/test/base32/boards/native_posix.overlay b/zephyr/test/base32/boards/native_posix.overlay
new file mode 100644
index 0000000000..c4d4413ad7
--- /dev/null
+++ b/zephyr/test/base32/boards/native_posix.overlay
@@ -0,0 +1,6 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <board-overlays/native_posix.dts>
diff --git a/zephyr/test/base32/prj.conf b/zephyr/test/base32/prj.conf
new file mode 100644
index 0000000000..2962b8f42f
--- /dev/null
+++ b/zephyr/test/base32/prj.conf
@@ -0,0 +1,7 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_ZTEST=y
+CONFIG_PLATFORM_EC=y
+CONFIG_CROS_EC=y
diff --git a/zephyr/test/base32/testcase.yaml b/zephyr/test/base32/testcase.yaml
new file mode 100644
index 0000000000..8db1025c2a
--- /dev/null
+++ b/zephyr/test/base32/testcase.yaml
@@ -0,0 +1,4 @@
+common:
+  platform_allow: native_posix
+tests:
+  base32.default: {}
diff --git a/zephyr/test/crc/CMakeLists.txt b/zephyr/test/crc/CMakeLists.txt
new file mode 100644
index 0000000000..b0b0996312
--- /dev/null
+++ b/zephyr/test/crc/CMakeLists.txt
@@ -0,0 +1,10 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(crc)
+
+# Include the test source and the file under test
+target_sources(app PRIVATE main.c)
diff --git a/zephyr/test/crc/boards/native_posix.overlay b/zephyr/test/crc/boards/native_posix.overlay
new file mode 100644
index 0000000000..90c864d2fd
--- /dev/null
+++ b/zephyr/test/crc/boards/native_posix.overlay
@@ -0,0 +1,6 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <board-overlays/native_posix.dts>
diff --git a/zephyr/test/crc/main.c b/zephyr/test/crc/main.c
new file mode 100644
index 0000000000..ab87c58705
--- /dev/null
+++ b/zephyr/test/crc/main.c
@@ -0,0 +1,34 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "crc.h"
+#include "crc8.h"
+
+#include <zephyr/ztest_assert.h>
+#include <zephyr/ztest_test_new.h>
+
+ZTEST_SUITE(crc_driver, NULL, NULL, NULL, NULL, NULL);
+
+ZTEST(crc_driver, test_crc8_known_data)
+{
+	uint8_t buffer[10] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 8 };
+
+	int crc = cros_crc8(buffer, 10);
+
+	/* Verifies polynomial values of 0x07 representing x^8 + x^2 + x + 1 */
+	zassert_equal(crc, 170, "CRC8 hash did not match");
+}
+
+ZTEST(crc_driver, test_crc16_known_data)
+{
+	uint8_t buffer[10] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 8 };
+
+	int crc = cros_crc16(buffer, 10, 0);
+
+	/*
+	 * Verifies polynomial values of 0x1021 representing X^16 + X^15 + X^2 +
+	 * 1
+	 */
+	zassert_equal(crc, 60681, "CRC16 hash did not match");
+}
diff --git a/zephyr/test/crc/prj.conf b/zephyr/test/crc/prj.conf
new file mode 100644
index 0000000000..89fdcc1efe
--- /dev/null
+++ b/zephyr/test/crc/prj.conf
@@ -0,0 +1,8 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_ZTEST=y
+CONFIG_ZTEST_NEW_API=y
+CONFIG_PLATFORM_EC=y
+CONFIG_CROS_EC=y
diff --git a/zephyr/test/crc/testcase.yaml b/zephyr/test/crc/testcase.yaml
new file mode 100644
index 0000000000..2a7787979d
--- /dev/null
+++ b/zephyr/test/crc/testcase.yaml
@@ -0,0 +1,4 @@
+common:
+  platform_allow: native_posix
+tests:
+  crc.default: {}
diff --git a/zephyr/test/drivers/CMakeLists.txt b/zephyr/test/drivers/CMakeLists.txt
new file mode 100644
index 0000000000..75b6f1891b
--- /dev/null
+++ b/zephyr/test/drivers/CMakeLists.txt
@@ -0,0 +1,93 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(drivers)
+
+add_subdirectory(common)
+add_subdirectory(${PLATFORM_EC}/zephyr/test/test_utils test_utils)
+
+get_target_property(TEST_SOURCES app SOURCES)
+
+# Add linked suites here
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_DEFAULT default)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_DEFAULT_CONSOLE_CMDS default/src/console_cmd)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_AMD_FP6_USB_MUX amd_fp6_usb_mux)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_ANX7447 anx7447)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_AP_MUX_CONTROL ap_mux_control)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_AP_VDM_CONTROL ap_vdm_control)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_CBI_FLASH cbi_flash)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_CONSOLE_CMD_CRASH console_cmd_crash)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_CONSOLE_CMD_MFALLOW console_cmd_mfallow)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_COMMON_CBI common_cbi)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_COMMON_CBI_GPIO common_cbi_gpio)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_COMMON_CHARGER common_charger)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_CHARGESPLASH chargesplash)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_CROS_FLASH cros_flash)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_FLASH flash)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_ICM42607 icm42607)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_ISL923X isl923x)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_ISL9241 isl9241)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_I2C_CONTROLLER i2c_controller)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_IT8XXX2_HW_SHA256 it8xxx2_hw_sha256)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_KEYBOARD_8042 keyboard_8042)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_KEYBOARD_SCAN keyboard_scan)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_LED_DRIVER led_driver)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_MKBP mkbp)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_NCT38XX nct38xx)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_NX20P348X nx20p348x)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_PANIC_OUTPUT panic_output)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_POWER_HOST_SLEEP power_host_sleep)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_RT1718S rt1718s)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_RT9490 rt9490)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_RANDOM random)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_SHIM_GPIO_ID shim_gpio_id)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_SHIM_PWM_HC shim_pwm_hc)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_SHIM_RTC shim_rtc)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_TIMER timer)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_USB_COMMON usb_common)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_USB_MALFUNCTION_SINK usb_malfunction_sink)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_USB_PD_DISCOVERY usb_pd_discovery)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_USB_PD_DPS dps)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_USB_PORT_POWER_DUMB usb_port_power_dumb)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_USB_RETIMER_FW_UPDATE usb_retimer_fw_update)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_USBC_ALT_MODE usbc_alt_mode)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_USBC_CONSOLE_PD usbc_console_pd)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_USBC_CTVPD usbc_ctvpd)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_USBC_FRS usbc_frs)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_USBC_SVDM_DFP_ONLY usbc_svdm_dfp_only)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_USBC_TBT_MODE usbc_tbt_mode)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_USBC_RETIMER usbc_retimer)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_USBC_USB4_MODE usbc_usb4_mode)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_USBC_VCONN_SWAP usbc_vconn_swap)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_USBC_OCP usbc_ocp)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_USBC_PPC usbc_ppc)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_USBC_TCPC usbc_tcpc)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_HOST_COMMANDS host_cmd)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_HOST_COMMAND_READ_MEMMAP host_cmd_read_memmap)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_SYSTEM system)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_LOCATE_CHIP_ALTS locate_chip)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_BUTTON button)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_CONSOLE console)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_HOST_CMD_THREAD host_command_thread)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_PI3USB9201 bc12_pi3usb9201)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_MEMMAP memmap)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_LED_COMMON led_common)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_PS8XXX ps8xxx)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_GPIO_UNHOOK gpio_unhook)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_HOST_COMMAND_MEMORY_DUMP host_command_memory_dump)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_ANX7452 anx7452)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_SM5803 sm5803)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_BODY_DETECTION body_detection)
+
+get_target_property(TEST_SOURCES_NEW app SOURCES)
+
+# Check to make sure at least one suite was added
+list(REMOVE_ITEM TEST_SOURCES_NEW ${TEST_SOURCES})
+if(NOT TEST_SOURCES_NEW)
+  message(FATAL_ERROR "Invalid configuration, must add test sources")
+endif()
+
+set_compiler_property(APPEND PROPERTY coverage -O0)
diff --git a/zephyr/test/drivers/Kconfig b/zephyr/test/drivers/Kconfig
new file mode 100644
index 0000000000..5d14fb0c3b
--- /dev/null
+++ b/zephyr/test/drivers/Kconfig
@@ -0,0 +1,272 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config BUG_249829957
+	bool "Tracking b/249829957"
+
+config LINK_TEST_SUITE_DEFAULT
+	bool "Link and test the default test suite"
+
+config LINK_TEST_SUITE_DEFAULT_CONSOLE_CMDS
+	bool "Link and test the default console commands test suite"
+
+config LINK_TEST_SUITE_CONSOLE_CMD_CRASH
+	bool "Link and test the console command crash test suite"
+
+config LINK_TEST_SUITE_CONSOLE_CMD_MFALLOW
+	bool "Link and test the console command mfallow test suite"
+
+config LINK_TEST_SUITE_AMD_FP6_USB_MUX
+	bool "Link and test the AMD FP6 USB mux tests"
+
+config LINK_TEST_SUITE_ANX7447
+	bool "Link and test the anx7447 tests"
+
+config LINK_TEST_SUITE_AP_MUX_CONTROL
+	bool "Link and test the ap_mux_control tests"
+
+config LINK_TEST_SUITE_AP_VDM_CONTROL
+	bool "Link and test the ap_vdm_control tests"
+
+config LINK_TEST_SUITE_BUTTON
+	bool "Link tests for common/button.c"
+
+config LINK_TEST_SUITE_CBI_FLASH
+	bool "Link and execute the zephyr/shim/src/cbi/cbi_flash.c tests"
+	help
+	  Include the CBI Flash storage driver test suite
+	  in the binary.
+
+config LINK_TEST_SUITE_CHARGESPLASH
+	bool "Link and test the chargesplash tests"
+
+config LINK_TEST_SUITE_COMMON_CBI
+	bool "Link and execute the common/cbi.c tests"
+
+config LINK_TEST_SUITE_COMMON_CBI_GPIO
+	bool "Link and execute the common/cbi_gpio.c tests"
+
+config LINK_TEST_SUITE_COMMON_CHARGER
+	bool "Link and execute the common/charger.c tests"
+
+config LINK_TEST_SUITE_CROS_FLASH
+	bool "Link and execute the cros-flash driver tests"
+	help
+	  Include the test suite exercising cros-flash driver in the binary.
+
+config LINK_TEST_SUITE_FLASH
+	bool "Link and execute the common/flash.c tests"
+	help
+	  Include the test suite exercising flash-related code in the binary.
+
+config LINK_TEST_SUITE_GPIO_UNHOOK
+  	bool "Link and execute the unhooked gpio tests"
+
+config LINK_TEST_SUITE_HOST_COMMANDS
+	select PLATFORM_EC_CHARGE_STATE_DEBUG
+	bool "Link and test the host command tests"
+
+config LINK_TEST_SUITE_HOST_COMMAND_READ_MEMMAP
+	bool "Link and test the host command read memmap tests"
+
+config LINK_TEST_SUITE_ICM42607
+	bool "Link and test the icm42607 tests"
+
+config LINK_TEST_SUITE_ISL923X
+	bool "Link and test the isl923x tests"
+
+config LINK_TEST_SUITE_ISL9241
+	bool "Link and test the isl9241 tests"
+
+config LINK_TEST_SUITE_I2C_CONTROLLER
+	bool "Link and test the i2c_controller tests"
+
+config LINK_TEST_SUITE_IT8XXX2_HW_SHA256
+	bool "Link and test the it8xxx2_hw_sha256 tests"
+	help
+	  Include the it8xxx2_hw_sha256 test suite
+	  in the binary.
+
+config LINK_TEST_SUITE_KEYBOARD_8042
+	bool "Link and test the keyboard_8042 tests"
+
+config LINK_TEST_SUITE_KEYBOARD_SCAN
+	bool "Link and test the keyboard_scan tests"
+	select PLATFORM_EC_MKBP_EVENT_WAKEUP_MASK
+	select PLATFORM_EC_MKBP_HOST_EVENT_WAKEUP_MASK
+
+config LINK_TEST_SUITE_LED_DRIVER
+	bool "Link and test the led_driver tests"
+
+config LINK_TEST_SUITE_LOCATE_CHIP_ALTS
+	bool "Link tests for alternate operations of the locate chip host cmd"
+	help
+	  Compile a binary that allows the non herobrine paths of the locate
+	  chip command to execute
+
+config LINK_TEST_SUITE_MKBP
+	bool "Link and test the mkbp tests"
+
+config LINK_TEST_SUITE_NCT38XX
+	bool "Link and test the nct38xx tests"
+
+config LINK_TEST_SUITE_NX20P348X
+	bool "Link and test the nx20p348x tests"
+	select PLATFORM_EC_CONSOLE_CMD_PPC_DUMP
+	select PLATFORM_EC_USB_PD_LOGGING
+
+config LINK_TEST_SUITE_PANIC_OUTPUT
+	bool "Link and test the panic_output tests"
+
+config LINK_TEST_SUITE_POWER_HOST_SLEEP
+	bool "Link and run the power/host_sleep.c specific tests"
+
+config LINK_TEST_SUITE_PS8XXX
+	bool "Link and test the ps8xxx tests"
+
+config LINK_TEST_SUITE_RT1718S
+	bool "Link and test the rt1718s tests"
+	help
+	  Link tests rt1718s test suite for the TCPM driver related function
+	  tests.
+
+config LINK_TEST_SUITE_RT9490
+	bool "Link and test the rt9490 tests"
+
+config LINK_TEST_SUITE_RANDOM
+	bool "Link and run random (trng) tests"
+	help
+	  Include the test suite exercising RNG code in the binary.
+
+config LINK_TEST_SUITE_SHIM_GPIO_ID
+	bool "Link and run the gpio tests"
+
+config LINK_TEST_SUITE_SHIM_PWM_HC
+	bool "Link and run the shim pwm_hc tests"
+
+config LINK_TEST_SUITE_SHIM_RTC
+	bool "Link and run the shim rtc tests"
+
+config LINK_TEST_SUITE_SYSTEM
+	bool "Link tests for common system code"
+
+config LINK_TEST_SUITE_TIMER
+	bool "Link and test the timer tests"
+
+config LINK_TEST_SUITE_USB_COMMON
+	bool "Link and test USB common code tests"
+
+config LINK_TEST_SUITE_USB_PD_DISCOVERY
+	bool "Link and test USB PD discovery tests"
+
+config LINK_TEST_SUITE_USB_MALFUNCTION_SINK
+	bool "Link and test the usb_malfunction_sink tests"
+
+config LINK_TEST_SUITE_USB_PD_DPS
+	bool "Link and test the dps tests"
+
+config LINK_TEST_SUITE_USB_PORT_POWER_DUMB
+	bool "Link and test the usb_port_power_dumb tests"
+
+config LINK_TEST_SUITE_USB_RETIMER_FW_UPDATE
+	bool "Link and test the usb_retimer_fw_update tests"
+
+config LINK_TEST_SUITE_USBC_ALT_MODE
+	bool "Link and test the usbc_alt_mode tests"
+
+config LINK_TEST_SUITE_USBC_CONSOLE_PD
+	bool"Link and test the usbc_console_pd tests"
+
+config LINK_TEST_SUITE_USBC_CTVPD
+	bool "Link tests for charge-through VCONN-powered device support"
+	select EMUL_TCPCI_PARTNER_VPD
+	select LOG
+
+config LINK_TEST_SUITE_USBC_FRS
+	bool "Link tests for fast role swap support"
+	select LOG
+	select PLATFORM_EC_USB_PD_FRS
+
+config LINK_TEST_SUITE_USBC_OCP
+	bool "Link tests for common USBC OCP code"
+
+config LINK_TEST_SUITE_USBC_PPC
+	bool "Link tests for common USBC PPC code"
+
+config LINK_TEST_SUITE_USBC_TCPC
+	bool "Link tests for common USBC TCPC code"
+	help
+	  Include the USBC TCPC test suite in the
+	  binary.
+
+config LINK_TEST_SUITE_USBC_SVDM_DFP_ONLY
+	bool "Link and test the usbc_svdm_dfp_only tests"
+
+config LINK_TEST_SUITE_USBC_RETIMER
+	bool "Link the USBC retimer tests"
+
+config LINK_TEST_SUITE_USBC_RETIMER_ANX7483
+	bool "Link and test the ANX7484 tests"
+	select LINK_TEST_SUITE_USBC_RETIMER
+	select PLATFORM_EC_USBC_RETIMER_ANX7483
+	help
+	  Include the ANX7483 test suite in the binary.
+
+config LINK_TEST_SUITE_USBC_RETIMER_PS8811
+	bool "Link and test the PS8811 tests"
+	select LINK_TEST_SUITE_USBC_RETIMER
+	select PLATFORM_EC_USBC_RETIMER_PS8811
+	help
+	  Include the PS8811 test suite in the binary.
+
+config LINK_TEST_SUITE_USBC_TBT_MODE
+	bool "Link and test the usbc_tbt_mode tests"
+
+config LINK_TEST_SUITE_USBC_USB4_MODE
+	bool "Link and test the usbc_usb4_mode tests"
+	help
+	  Include the usbc_usb4 test suite in the binary.
+
+config LINK_TEST_SUITE_USBC_VCONN_SWAP
+	bool "Link and test the usbc_vconn_swap tests"
+	help
+	  Include the test suite exercising VCONN Swap behaviors in the binary.
+
+config LINK_TEST_SUITE_CONSOLE
+	bool "Link and test the console tests"
+	select UART_INTERRUPT_DRIVEN
+
+config LINK_TEST_SUITE_HOST_CMD_THREAD
+	bool "Link and test the host command thread override tests"
+
+config LINK_TEST_SUITE_PI3USB9201
+	bool "Link and test the pi3usb9201 tests"
+
+config LINK_TEST_SUITE_MEMMAP
+	bool "Link and test memory mapped tests for common/flash.c"
+	select PLATFORM_EC_MAPPED_STORAGE
+
+config LINK_TEST_SUITE_LED_COMMON
+	bool "Link and test the led_common.c file"
+	depends on !PLATFORM_EC_LED_DT
+	select PLATFORM_EC_LED_COMMON
+
+config LINK_TEST_SUITE_HOST_COMMAND_MEMORY_DUMP
+	bool "Link and test memory dump host commands tests"
+
+config LINK_TEST_SUITE_ANX7452
+	bool "Link and test the anx7452 tests"
+	help
+	  Include the test suite of ANX7452 retimer in the binary. The tests
+	  use I2C emulation.
+
+config LINK_TEST_SUITE_SM5803
+	bool "Link and test the SM5803 charger tests"
+
+config LINK_TEST_SUITE_BODY_DETECTION
+	bool "Link and test the body detection tests"
+	help
+	  Include the test suite exercising body detection behaviors in the binary.
+
+source "Kconfig.zephyr"
diff --git a/zephyr/test/drivers/README.md b/zephyr/test/drivers/README.md
new file mode 100644
index 0000000000..7dfc5c51e5
--- /dev/null
+++ b/zephyr/test/drivers/README.md
@@ -0,0 +1,49 @@
+This is the drivers test directory. The goal is to have many driver test suites
+in few binaries, so that compile time will be faster than many small tests, and
+so we can test interactions between different subsystems easily.
+
+## Run all the test suites
+
+```bash
+(chroot) ec $ ./twister -T zephyr/test/drivers
+```
+
+To see all the output of twister in stdout (for example if the build fails)
+
+```bash
+(chroot) ec $ ./twister -v -i -T zephyr/test/drivers
+```
+
+## Code coverage
+
+See the [EC code coverage] doc.
+
+## Debugging
+
+You need the host version of gdb:
+
+```bash
+(chroot) sudo emerge -j sys-devel/gdb
+```
+
+Build all the drivers tests
+```bash
+(chroot) ec $ ./twister -b -T zephyr/test/drivers
+```
+
+Then run gdb
+
+Example of running gdb on the `drivers.default` test binary:
+
+```
+(chroot) ec $ gdb twister-out/native_posix/drivers.default/zephyr/zephyr.exe
+# Set breakpoints, run, etc.
+```
+
+Another of running gdb now on the `drivers.chargesplash` test binary:
+
+```
+(chroot) ec $ gdb twister-out/native_posix/drivers.chargesplash/zephyr/zephyr.exe
+```
+
+[EC code coverage]: ../../../docs/code_coverage.md#zephyr-ztest-code-coverage
diff --git a/zephyr/test/drivers/amd_fp6_usb_mux/CMakeLists.txt b/zephyr/test/drivers/amd_fp6_usb_mux/CMakeLists.txt
new file mode 100644
index 0000000000..76b6294a55
--- /dev/null
+++ b/zephyr/test/drivers/amd_fp6_usb_mux/CMakeLists.txt
@@ -0,0 +1,5 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_sources(app PRIVATE src/amd_fp6_usb_mux_test.c)
diff --git a/zephyr/test/drivers/amd_fp6_usb_mux/src/amd_fp6_usb_mux_test.c b/zephyr/test/drivers/amd_fp6_usb_mux/src/amd_fp6_usb_mux_test.c
new file mode 100644
index 0000000000..8d8a6982cf
--- /dev/null
+++ b/zephyr/test/drivers/amd_fp6_usb_mux/src/amd_fp6_usb_mux_test.c
@@ -0,0 +1,151 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "emul/emul_amd_fp6.h"
+#include "hooks.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "usb_mux.h"
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+#define TEST_PORT 0
+#define AMD_FP6_NODE DT_NODELABEL(amd_fp6_emul0)
+
+struct amd_fp6_usb_mux_fixture {
+	const struct emul *amd_fp6_emul;
+};
+
+static void *amd_fp6_usb_mux_setup(void)
+{
+	static struct amd_fp6_usb_mux_fixture fix;
+
+	fix.amd_fp6_emul = EMUL_DT_GET(AMD_FP6_NODE);
+
+	return &fix;
+}
+
+static void amd_fp6_usb_mux_before(void *fixture)
+{
+	ARG_UNUSED(fixture);
+
+	/* Default to S0 for most cases */
+	test_set_chipset_to_s0();
+}
+
+ZTEST_SUITE(amd_fp6_usb_mux, drivers_predicate_post_main, amd_fp6_usb_mux_setup,
+	    amd_fp6_usb_mux_before, NULL, NULL);
+
+ZTEST(amd_fp6_usb_mux, test_usb_mode_set)
+{
+	/* Test a basic set to USB mode */
+	usb_mux_set(TEST_PORT, USB_PD_MUX_USB_ENABLED, USB_SWITCH_CONNECT, 0);
+
+	zassert_equal(usb_mux_get(TEST_PORT), USB_PD_MUX_USB_ENABLED);
+}
+
+ZTEST(amd_fp6_usb_mux, test_dp_mode_set)
+{
+	/* Test a basic set to DP mode */
+	usb_mux_set(TEST_PORT, USB_PD_MUX_DP_ENABLED, USB_SWITCH_CONNECT, 0);
+
+	zassert_equal(usb_mux_get(TEST_PORT), USB_PD_MUX_DP_ENABLED);
+}
+
+ZTEST(amd_fp6_usb_mux, test_dock_mode_set)
+{
+	/* Test a basic set to docked mode */
+	usb_mux_set(TEST_PORT, USB_PD_MUX_DOCK, USB_SWITCH_CONNECT, 0);
+
+	zassert_equal(usb_mux_get(TEST_PORT), USB_PD_MUX_DOCK);
+}
+
+ZTEST(amd_fp6_usb_mux, test_safe_mode_set)
+{
+	/* Test a basic set to safe mode */
+	usb_mux_set(TEST_PORT, USB_PD_MUX_SAFE_MODE, USB_SWITCH_CONNECT, 0);
+
+	/* Note: this driver uses "none" and "safe" interchangeably */
+	zassert_equal(usb_mux_get(TEST_PORT), USB_PD_MUX_NONE);
+}
+
+ZTEST(amd_fp6_usb_mux, test_none_set)
+{
+	/* Test a basic set to none */
+	usb_mux_set(TEST_PORT, USB_PD_MUX_NONE, USB_SWITCH_CONNECT, 0);
+
+	zassert_equal(usb_mux_get(TEST_PORT), USB_PD_MUX_NONE);
+}
+
+ZTEST(amd_fp6_usb_mux, test_dp_flipped_set)
+{
+	/* Test a basic set to DP mode but flipped */
+	usb_mux_set(TEST_PORT, USB_PD_MUX_DP_ENABLED, USB_SWITCH_CONNECT, 1);
+
+	zassert_equal(usb_mux_get(TEST_PORT),
+		      USB_PD_MUX_DP_ENABLED | USB_PD_MUX_POLARITY_INVERTED);
+}
+
+ZTEST(amd_fp6_usb_mux, test_hpd_unsupported)
+{
+	/* Try to set HPD on the mux */
+	usb_mux_set(TEST_PORT, USB_PD_MUX_HPD_LVL, USB_SWITCH_CONNECT, 0);
+
+	/* And observe it didn't work */
+	zassert_equal(usb_mux_get(TEST_PORT), USB_PD_MUX_NONE);
+}
+
+ZTEST_F(amd_fp6_usb_mux, test_mux_not_ready)
+{
+	/* Set the crossbar to not ready yet */
+	amd_fp6_emul_set_xbar(fixture->amd_fp6_emul, false);
+
+	/* Send a basic set to USB mode */
+	usb_mux_set(TEST_PORT, USB_PD_MUX_USB_ENABLED, USB_SWITCH_CONNECT, 0);
+
+	k_sleep(K_MSEC(100));
+	zassert_not_equal(usb_mux_get(TEST_PORT), USB_PD_MUX_USB_ENABLED);
+
+	/* Allow the crossbar to be ready now */
+	amd_fp6_emul_set_xbar(fixture->amd_fp6_emul, true);
+	/* Driver retry is 1 second, so sleep for twice that */
+	k_sleep(K_SECONDS(2));
+
+	zassert_equal(usb_mux_get(TEST_PORT), USB_PD_MUX_USB_ENABLED);
+}
+
+ZTEST_F(amd_fp6_usb_mux, test_chipset_reset)
+{
+	/* Start with a set to dock mode but flipped */
+	usb_mux_set(TEST_PORT, USB_PD_MUX_DOCK, USB_SWITCH_CONNECT, 1);
+
+	zassert_equal(usb_mux_get(TEST_PORT),
+		      USB_PD_MUX_DOCK | USB_PD_MUX_POLARITY_INVERTED);
+
+	/* Now "reset the SoC" with a register clear and hook notify */
+	amd_fp6_emul_reset_regs(fixture->amd_fp6_emul);
+	zassert_equal(usb_mux_get(TEST_PORT), USB_PD_MUX_NONE);
+	hook_notify(HOOK_CHIPSET_RESET);
+	/* Driver retry is 1 second, so sleep for twice that */
+	k_sleep(K_SECONDS(2));
+
+	zassert_equal(usb_mux_get(TEST_PORT),
+		      USB_PD_MUX_DOCK | USB_PD_MUX_POLARITY_INVERTED);
+}
+
+ZTEST_F(amd_fp6_usb_mux, test_long_command)
+{
+	/* Allow the mux to take a while, like on real systems */
+	amd_fp6_emul_set_delay(fixture->amd_fp6_emul, 6);
+
+	/* Send a basic set to USB mode */
+	usb_mux_set(TEST_PORT, USB_PD_MUX_USB_ENABLED, USB_SWITCH_CONNECT, 1);
+
+	k_sleep(K_MSEC(200));
+	zassert_equal(usb_mux_get(TEST_PORT),
+		      USB_PD_MUX_USB_ENABLED | USB_PD_MUX_POLARITY_INVERTED);
+}
diff --git a/zephyr/test/drivers/amd_fp6_usb_mux/usbc.dts b/zephyr/test/drivers/amd_fp6_usb_mux/usbc.dts
new file mode 100644
index 0000000000..b57d5c8023
--- /dev/null
+++ b/zephyr/test/drivers/amd_fp6_usb_mux/usbc.dts
@@ -0,0 +1,28 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/usb_pd_tcpm.h>
+
+/ {
+	usbc {
+		port0@0 {
+			compatible = "named-usbc-port";
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&amd_fp6_emul0>;
+			};
+		};
+	};
+};
+
+&i2c2 {
+	status="okay";
+
+	amd_fp6_emul0: amd_fp6_emul@5c {
+		compatible = "amd,usbc-mux-amd-fp6";
+		status = "okay";
+		reg = <0x5c>;
+	};
+};
diff --git a/zephyr/test/drivers/anx7447/CMakeLists.txt b/zephyr/test/drivers/anx7447/CMakeLists.txt
new file mode 100644
index 0000000000..b699fae981
--- /dev/null
+++ b/zephyr/test/drivers/anx7447/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Add source files
+target_sources(app PRIVATE src/low_power_mode.c)
diff --git a/zephyr/test/drivers/anx7447/prj.conf b/zephyr/test/drivers/anx7447/prj.conf
new file mode 100644
index 0000000000..e22306aea6
--- /dev/null
+++ b/zephyr/test/drivers/anx7447/prj.conf
@@ -0,0 +1,5 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_PLATFORM_EC_USB_PD_TCPC_LOW_POWER=y
diff --git a/zephyr/test/drivers/anx7447/src/low_power_mode.c b/zephyr/test/drivers/anx7447/src/low_power_mode.c
new file mode 100644
index 0000000000..91f132ef6d
--- /dev/null
+++ b/zephyr/test/drivers/anx7447/src/low_power_mode.c
@@ -0,0 +1,57 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "emul/tcpc/emul_tcpci.h"
+#include "tcpm/anx7447_public.h"
+#include "tcpm/tcpci.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "usb_pd.h"
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/ztest.h>
+
+#define ANX7447_NODE DT_NODELABEL(anx7447_emul)
+
+static const int tcpm_anx7447_port = USBC_PORT_C0;
+
+ZTEST_SUITE(low_power_mode, drivers_predicate_post_main, NULL, NULL, NULL,
+	    NULL);
+
+ZTEST(low_power_mode, test_enter_low_power_in_source_mode)
+{
+	uint16_t reg_val = 0;
+	const struct emul *anx7447_emul = EMUL_DT_GET(ANX7447_NODE);
+
+	pd_set_dual_role(tcpm_anx7447_port, PD_DRP_FORCE_SOURCE);
+	tcpci_emul_set_reg(anx7447_emul, TCPC_REG_ROLE_CTRL, 0);
+
+	zassert_ok(anx7447_tcpm_drv.enter_low_power_mode(tcpm_anx7447_port),
+		   "Cannot enter low power mode");
+	zassert_ok(tcpci_emul_get_reg(anx7447_emul, TCPC_REG_ROLE_CTRL,
+				      &reg_val),
+		   "Cannot get TCPC Role Register value");
+	zassert_equal(
+		reg_val,
+		TCPC_REG_ROLE_CTRL_SET(TYPEC_NO_DRP, TYPEC_RP_USB, TYPEC_CC_RP,
+				       TYPEC_CC_RP),
+		"Role register value is not as expected while entering low power mode");
+}
+
+ZTEST(low_power_mode, test_enter_low_power_not_in_source_mode)
+{
+	uint16_t reg_val = 0;
+	const struct emul *anx7447_emul = EMUL_DT_GET(ANX7447_NODE);
+
+	pd_set_dual_role(tcpm_anx7447_port, PD_DRP_FORCE_SINK);
+	tcpci_emul_set_reg(anx7447_emul, TCPC_REG_ROLE_CTRL, 0);
+
+	zassert_ok(anx7447_tcpm_drv.enter_low_power_mode(tcpm_anx7447_port),
+		   "Cannot enter low power mode");
+	zassert_ok(tcpci_emul_get_reg(anx7447_emul, TCPC_REG_ROLE_CTRL,
+				      &reg_val),
+		   "Cannot get TCPC Role Register value");
+	zassert_equal(reg_val, 0, "Role register value is changed");
+}
diff --git a/zephyr/test/drivers/anx7447/tcpc_policy.dts b/zephyr/test/drivers/anx7447/tcpc_policy.dts
new file mode 100644
index 0000000000..6bdae81e73
--- /dev/null
+++ b/zephyr/test/drivers/anx7447/tcpc_policy.dts
@@ -0,0 +1,30 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/usb_pd_tcpm.h>
+
+/ {
+	usbc {
+		port0@0 {
+			compatible = "named-usbc-port";
+			tcpc = <&anx7447_emul>;
+		};
+	};
+};
+
+&i2c0 {
+	status="okay";
+
+	anx7447_emul: anx7447_emul@2c {
+		compatible = "cros,anx7447-tcpc-emul";
+		reg = <0x2c>;
+		tcpc-flags = <(
+			TCPC_FLAGS_VBUS_MONITOR |
+			TCPC_FLAGS_ALERT_OD |
+			TCPC_FLAGS_CONTROL_VCONN |
+			TCPC_FLAGS_CONTROL_FRS)>;
+	};
+};
+
diff --git a/zephyr/test/drivers/anx7452/CMakeLists.txt b/zephyr/test/drivers/anx7452/CMakeLists.txt
new file mode 100644
index 0000000000..a61fa0a1c6
--- /dev/null
+++ b/zephyr/test/drivers/anx7452/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Add source files
+target_sources(app PRIVATE src/anx7452.c)
diff --git a/zephyr/test/drivers/anx7452/prj.conf b/zephyr/test/drivers/anx7452/prj.conf
new file mode 100644
index 0000000000..96bb372274
--- /dev/null
+++ b/zephyr/test/drivers/anx7452/prj.conf
@@ -0,0 +1,3 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
diff --git a/zephyr/test/drivers/anx7452/src/anx7452.c b/zephyr/test/drivers/anx7452/src/anx7452.c
new file mode 100644
index 0000000000..c68c2e3853
--- /dev/null
+++ b/zephyr/test/drivers/anx7452/src/anx7452.c
@@ -0,0 +1,336 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "driver/retimer/anx7452.h"
+#include "driver/retimer/anx7452_public.h"
+#include "emul/emul_anx7452.h"
+#include "emul/emul_common_i2c.h"
+#include "i2c.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_mocks.h"
+#include "test/drivers/test_state.h"
+#include "timer.h"
+#include "usb_mux.h"
+
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/fff.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+#define GPIO_USB_C1_USB_EN_PATH NAMED_GPIOS_GPIO_NODE(usb_c1_usb_en)
+#define GPIO_USB_C1_USB_EN_PORT DT_GPIO_PIN(GPIO_USB_C1_USB_EN_PATH, gpios)
+#define GPIO_USB_C1_USB_EN_SIGNAL GPIO_SIGNAL(GPIO_USB_C1_USB_EN_PATH)
+#define GPIO_USB_C1_DP_EN_PATH NAMED_GPIOS_GPIO_NODE(usb_c1_dp_en)
+#define GPIO_USB_C1_DP_EN_PORT DT_GPIO_PIN(GPIO_USB_C1_DP_EN_PATH, gpios)
+
+#define ANX7452_NODE DT_NODELABEL(usb_c1_anx7452_emul)
+#define EMUL EMUL_DT_GET(ANX7452_NODE)
+#define COMMON_DATA(port) emul_anx7452_get_i2c_common_data(EMUL, port)
+
+static inline void reset_anx7452_state(void)
+{
+	test_set_chipset_to_s0();
+	i2c_common_emul_set_write_func(COMMON_DATA(TOP_EMUL_PORT), NULL, NULL);
+	i2c_common_emul_set_read_func(COMMON_DATA(TOP_EMUL_PORT), NULL, NULL);
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA(TOP_EMUL_PORT),
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA(TOP_EMUL_PORT),
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	i2c_common_emul_set_write_func(COMMON_DATA(CTLTOP_EMUL_PORT), NULL,
+				       NULL);
+	i2c_common_emul_set_read_func(COMMON_DATA(CTLTOP_EMUL_PORT), NULL,
+				      NULL);
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA(CTLTOP_EMUL_PORT),
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA(CTLTOP_EMUL_PORT),
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	gpio_set_level(GPIO_USB_C1_USB_EN_SIGNAL, 0);
+
+	anx7452_emul_reset(EMUL);
+}
+
+ZTEST(anx7452, test_anx7452_init)
+{
+	const struct device *usb_en_gpio_dev =
+		DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_USB_C1_USB_EN_PATH, gpios));
+	const struct device *dp_en_gpio_dev =
+		DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_USB_C1_DP_EN_PATH, gpios));
+	const uint8_t top_reg_val = ANX7452_TOP_REG_EN |
+				    ANX7452_TOP_RESERVED_BIT |
+				    ANX7452_TOP_USB3_INFO;
+	uint32_t start_ms;
+	uint32_t end_ms;
+
+	zassert_not_null(usb_en_gpio_dev, "Cannot get USB EN GPIO device");
+	zassert_not_null(dp_en_gpio_dev, "Cannot get DP EN GPIO device");
+
+	/* Test successful init */
+	zassert_equal(
+		EC_SUCCESS,
+		anx7452_usb_retimer_driver.init(usb_muxes[USBC_PORT_C1].mux),
+		NULL);
+	zassert_equal(anx7452_emul_get_reg(EMUL, ANX7452_TOP_STATUS_REG),
+		      top_reg_val, NULL);
+	zassert_equal(1,
+		      gpio_emul_output_get(usb_en_gpio_dev,
+					   GPIO_USB_C1_USB_EN_PORT),
+		      NULL);
+	zassert_equal(
+		0, gpio_emul_output_get(dp_en_gpio_dev, GPIO_USB_C1_DP_EN_PORT),
+		NULL);
+
+	reset_anx7452_state();
+	/* Setup emulator fail on write */
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA(TOP_EMUL_PORT),
+					   ANX7452_TOP_STATUS_REG);
+	/* With reg write fail, init should fail */
+	zassert_equal(
+		EC_ERROR_TIMEOUT,
+		anx7452_usb_retimer_driver.init(usb_muxes[USBC_PORT_C1].mux),
+		NULL);
+	zassert_not_equal(anx7452_emul_get_reg(EMUL, ANX7452_TOP_STATUS_REG),
+			  top_reg_val, NULL);
+	zassert_equal(1,
+		      gpio_emul_output_get(usb_en_gpio_dev,
+					   GPIO_USB_C1_USB_EN_PORT),
+		      NULL);
+	zassert_equal(
+		0, gpio_emul_output_get(dp_en_gpio_dev, GPIO_USB_C1_DP_EN_PORT),
+		NULL);
+
+	reset_anx7452_state();
+	/* Setup emulator fail on read */
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA(TOP_EMUL_PORT),
+					  ANX7452_TOP_STATUS_REG);
+	start_ms = k_uptime_get();
+	/* With reg read fail, init should fail */
+	zassert_equal(
+		EC_ERROR_TIMEOUT,
+		anx7452_usb_retimer_driver.init(usb_muxes[USBC_PORT_C1].mux),
+		NULL);
+	end_ms = k_uptime_get();
+	/* With timeout caused by read fail, the time took should be greater
+	 * than or equal to configured timeout value
+	 */
+	zassert_true((end_ms - start_ms) > ANX7452_I2C_WAKE_TIMEOUT_MS, NULL);
+	zassert_not_equal(anx7452_emul_get_reg(EMUL, ANX7452_TOP_STATUS_REG),
+			  top_reg_val, NULL);
+	zassert_equal(1,
+		      gpio_emul_output_get(usb_en_gpio_dev,
+					   GPIO_USB_C1_USB_EN_PORT),
+		      NULL);
+	zassert_equal(
+		0, gpio_emul_output_get(dp_en_gpio_dev, GPIO_USB_C1_DP_EN_PORT),
+		NULL);
+
+	reset_anx7452_state();
+	/* Set AP to off state and wait for chipset task */
+	test_set_chipset_to_g3();
+	start_ms = k_uptime_get();
+	/* With AP off, init should fail and pins should be unset */
+	zassert_equal(
+		EC_ERROR_NOT_POWERED,
+		anx7452_usb_retimer_driver.init(usb_muxes[USBC_PORT_C1].mux),
+		NULL);
+	end_ms = k_uptime_get();
+	zassert_true((end_ms - start_ms) < 30, NULL);
+	zassert_not_equal(anx7452_emul_get_reg(EMUL, ANX7452_TOP_STATUS_REG),
+			  top_reg_val, NULL);
+	zassert_equal(0,
+		      gpio_emul_output_get(usb_en_gpio_dev,
+					   GPIO_USB_C1_USB_EN_PORT),
+		      NULL);
+	zassert_equal(
+		0, gpio_emul_output_get(dp_en_gpio_dev, GPIO_USB_C1_DP_EN_PORT),
+		NULL);
+}
+
+ZTEST(anx7452, test_anx7452_get)
+{
+	mux_state_t mux_state = 0;
+
+	zassert_equal(EC_SUCCESS,
+		      anx7452_usb_retimer_driver.get(
+			      usb_muxes[USBC_PORT_C1].mux, &mux_state));
+
+	anx7452_emul_set_reg(EMUL, ANX7452_TOP_STATUS_REG,
+			     ANX7452_TOP_REG_EN | ANX7452_TOP_FLIP_INFO);
+	zassert_equal(EC_SUCCESS,
+		      anx7452_usb_retimer_driver.get(
+			      usb_muxes[USBC_PORT_C1].mux, &mux_state));
+	zassert_equal(mux_state, USB_PD_MUX_POLARITY_INVERTED);
+
+	anx7452_emul_set_reg(EMUL, ANX7452_TOP_STATUS_REG,
+			     ANX7452_TOP_REG_EN | ANX7452_TOP_DP_INFO);
+	zassert_equal(EC_SUCCESS,
+		      anx7452_usb_retimer_driver.get(
+			      usb_muxes[USBC_PORT_C1].mux, &mux_state));
+	zassert_equal(mux_state, USB_PD_MUX_DP_ENABLED);
+
+	anx7452_emul_set_reg(EMUL, ANX7452_TOP_STATUS_REG,
+			     ANX7452_TOP_REG_EN | ANX7452_TOP_TBT_INFO);
+	zassert_equal(EC_SUCCESS,
+		      anx7452_usb_retimer_driver.get(
+			      usb_muxes[USBC_PORT_C1].mux, &mux_state));
+	zassert_equal(mux_state, USB_PD_MUX_TBT_COMPAT_ENABLED);
+
+	anx7452_emul_set_reg(EMUL, ANX7452_TOP_STATUS_REG,
+			     ANX7452_TOP_REG_EN | ANX7452_TOP_USB3_INFO);
+	zassert_equal(EC_SUCCESS,
+		      anx7452_usb_retimer_driver.get(
+			      usb_muxes[USBC_PORT_C1].mux, &mux_state));
+	zassert_equal(mux_state, USB_PD_MUX_USB_ENABLED);
+
+	anx7452_emul_set_reg(EMUL, ANX7452_TOP_STATUS_REG,
+			     ANX7452_TOP_REG_EN | ANX7452_TOP_USB4_INFO);
+	zassert_equal(EC_SUCCESS,
+		      anx7452_usb_retimer_driver.get(
+			      usb_muxes[USBC_PORT_C1].mux, &mux_state));
+	zassert_equal(mux_state, USB_PD_MUX_USB4_ENABLED);
+
+	reset_anx7452_state();
+	test_set_chipset_to_g3();
+	zassert_equal(EC_ERROR_NOT_POWERED,
+		      anx7452_usb_retimer_driver.get(
+			      usb_muxes[USBC_PORT_C1].mux, &mux_state));
+	zassert_equal(mux_state, USB_PD_MUX_NONE);
+
+	reset_anx7452_state();
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA(TOP_EMUL_PORT),
+					  ANX7452_TOP_STATUS_REG);
+	zassert_equal(EC_ERROR_INVAL,
+		      anx7452_usb_retimer_driver.get(
+			      usb_muxes[USBC_PORT_C1].mux, &mux_state));
+}
+
+ZTEST(anx7452, test_anx7452_set)
+{
+	mux_state_t mux_state = 0;
+	bool ack_required;
+
+	zassert_equal(EC_SUCCESS, anx7452_usb_retimer_driver.set(
+					  usb_muxes[USBC_PORT_C1].mux,
+					  mux_state, &ack_required));
+	zassert_equal(ack_required, false);
+
+	zassert_equal(anx7452_emul_get_reg(EMUL, ANX7452_CTLTOP_CFG0_REG), 0);
+	zassert_equal(EC_SUCCESS,
+		      anx7452_usb_retimer_driver.set(
+			      usb_muxes[USBC_PORT_C1].mux,
+			      USB_PD_MUX_POLARITY_INVERTED, &ack_required));
+	zassert_equal(anx7452_emul_get_reg(EMUL, ANX7452_CTLTOP_CFG0_REG),
+		      ANX7452_CTLTOP_CFG0_FLIP_EN);
+
+	zassert_equal(EC_SUCCESS,
+		      anx7452_usb_retimer_driver.set(
+			      usb_muxes[USBC_PORT_C1].mux,
+			      USB_PD_MUX_USB_ENABLED, &ack_required));
+	zassert_equal(anx7452_emul_get_reg(EMUL, ANX7452_CTLTOP_CFG0_REG),
+		      ANX7452_CTLTOP_CFG0_USB3_EN);
+
+	zassert_equal(anx7452_emul_get_reg(EMUL, ANX7452_CTLTOP_CFG1_REG), 0);
+	zassert_equal(EC_SUCCESS,
+		      anx7452_usb_retimer_driver.set(
+			      usb_muxes[USBC_PORT_C1].mux,
+			      USB_PD_MUX_DP_ENABLED, &ack_required));
+	zassert_equal(anx7452_emul_get_reg(EMUL, ANX7452_CTLTOP_CFG1_REG),
+		      ANX7452_CTLTOP_CFG1_DP_EN);
+
+	zassert_equal(anx7452_emul_get_reg(EMUL, ANX7452_CTLTOP_CFG2_REG), 0);
+	zassert_equal(EC_SUCCESS,
+		      anx7452_usb_retimer_driver.set(
+			      usb_muxes[USBC_PORT_C1].mux,
+			      USB_PD_MUX_USB4_ENABLED, &ack_required));
+	zassert_equal(anx7452_emul_get_reg(EMUL, ANX7452_CTLTOP_CFG2_REG),
+		      ANX7452_CTLTOP_CFG2_USB4_EN);
+
+	zassert_equal(EC_SUCCESS,
+		      anx7452_usb_retimer_driver.set(
+			      usb_muxes[USBC_PORT_C1].mux,
+			      USB_PD_MUX_TBT_COMPAT_ENABLED, &ack_required));
+	zassert_equal(anx7452_emul_get_reg(EMUL, ANX7452_CTLTOP_CFG2_REG),
+		      ANX7452_CTLTOP_CFG2_TBT_EN);
+
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA(CTLTOP_EMUL_PORT),
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA(CTLTOP_EMUL_PORT),
+					  ANX7452_CTLTOP_CFG0_REG);
+	zassert_equal(EC_ERROR_INVAL, anx7452_usb_retimer_driver.set(
+					      usb_muxes[USBC_PORT_C1].mux,
+					      mux_state, &ack_required));
+
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA(CTLTOP_EMUL_PORT),
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA(CTLTOP_EMUL_PORT),
+					  ANX7452_CTLTOP_CFG1_REG);
+	zassert_equal(EC_ERROR_INVAL, anx7452_usb_retimer_driver.set(
+					      usb_muxes[USBC_PORT_C1].mux,
+					      mux_state, &ack_required));
+
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA(CTLTOP_EMUL_PORT),
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA(CTLTOP_EMUL_PORT),
+					  ANX7452_CTLTOP_CFG2_REG);
+	zassert_equal(EC_ERROR_INVAL, anx7452_usb_retimer_driver.set(
+					      usb_muxes[USBC_PORT_C1].mux,
+					      mux_state, &ack_required));
+
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA(CTLTOP_EMUL_PORT),
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA(CTLTOP_EMUL_PORT),
+					   ANX7452_CTLTOP_CFG0_REG);
+	zassert_equal(EC_ERROR_INVAL,
+		      anx7452_usb_retimer_driver.set(
+			      usb_muxes[USBC_PORT_C1].mux,
+			      USB_PD_MUX_POLARITY_INVERTED, &ack_required));
+
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA(CTLTOP_EMUL_PORT),
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA(CTLTOP_EMUL_PORT),
+					   ANX7452_CTLTOP_CFG1_REG);
+	zassert_equal(EC_ERROR_INVAL,
+		      anx7452_usb_retimer_driver.set(
+			      usb_muxes[USBC_PORT_C1].mux,
+			      USB_PD_MUX_DP_ENABLED, &ack_required));
+
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA(CTLTOP_EMUL_PORT),
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA(CTLTOP_EMUL_PORT),
+					   ANX7452_CTLTOP_CFG2_REG);
+	zassert_equal(EC_ERROR_INVAL,
+		      anx7452_usb_retimer_driver.set(
+			      usb_muxes[USBC_PORT_C1].mux,
+			      USB_PD_MUX_USB4_ENABLED, &ack_required));
+
+	reset_anx7452_state();
+	test_set_chipset_to_g3();
+	zassert_equal(EC_ERROR_NOT_POWERED, anx7452_usb_retimer_driver.set(
+						    usb_muxes[USBC_PORT_C1].mux,
+						    mux_state, &ack_required));
+}
+
+static void anx7452_before(void *state)
+{
+	ARG_UNUSED(state);
+	reset_anx7452_state();
+}
+
+static void anx7452_after(void *state)
+{
+	ARG_UNUSED(state);
+	reset_anx7452_state();
+}
+
+ZTEST_SUITE(anx7452, drivers_predicate_post_main, NULL, anx7452_before,
+	    anx7452_after, NULL);
diff --git a/zephyr/test/drivers/anx7452/usbc.dts b/zephyr/test/drivers/anx7452/usbc.dts
new file mode 100644
index 0000000000..ca70142cdf
--- /dev/null
+++ b/zephyr/test/drivers/anx7452/usbc.dts
@@ -0,0 +1,32 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/usb_pd_tcpm.h>
+
+/ {
+	usbc {
+		port1@1 {
+			compatible = "named-usbc-port";
+			reg = <1>;
+			usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_c1_anx7452_emul>;
+			};
+		};
+	};
+
+};
+&i2c3 {
+	status = "okay";
+
+	/delete-node/ bbretimer@42;
+
+	usb_c1_anx7452_emul: anx7452@10 {
+		compatible = "analogix,anx7452";
+		reg = <0x10>;
+		usb-en-pin = <&usb_c1_usb_en>;
+		dp-en-pin = <&usb_c1_dp_en>;
+	};
+};
diff --git a/zephyr/test/drivers/ap_mux_control/CMakeLists.txt b/zephyr/test/drivers/ap_mux_control/CMakeLists.txt
new file mode 100644
index 0000000000..005e72e714
--- /dev/null
+++ b/zephyr/test/drivers/ap_mux_control/CMakeLists.txt
@@ -0,0 +1,19 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Create library name based on current directory
+zephyr_library_get_current_dir_lib_name(${ZEPHYR_BASE} lib_name)
+
+# Create interface library
+zephyr_interface_library_named(${lib_name})
+
+# Add include paths
+zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}")
+zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}/include")
+
+# Add source files
+zephyr_library_sources("${CMAKE_CURRENT_SOURCE_DIR}/src/ap_mux_control.c")
+
+# Link in the library
+zephyr_library_link_libraries(${lib_name})
diff --git a/zephyr/test/drivers/ap_mux_control/prj.conf b/zephyr/test/drivers/ap_mux_control/prj.conf
new file mode 100644
index 0000000000..75b05bce0b
--- /dev/null
+++ b/zephyr/test/drivers/ap_mux_control/prj.conf
@@ -0,0 +1,6 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_PLATFORM_EC_USB_MUX_AP_CONTROL=y
+CONFIG_PLATFORM_EC_USB_MUX_TASK=y
diff --git a/zephyr/test/drivers/ap_mux_control/src/ap_mux_control.c b/zephyr/test/drivers/ap_mux_control/src/ap_mux_control.c
new file mode 100644
index 0000000000..993c6e680c
--- /dev/null
+++ b/zephyr/test/drivers/ap_mux_control/src/ap_mux_control.c
@@ -0,0 +1,96 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "usb_mux.h"
+
+#include <zephyr/ztest.h>
+
+static void ap_mux_control_before(void *data)
+{
+	/* Set chipset on to ensure muxes are "powered" */
+	test_set_chipset_to_s0();
+
+	/*
+	 * Set all muxes to NONE to begin with and give time for the USB_MUX
+	 * task to process them.
+	 */
+	usb_mux_set(USBC_PORT_C0, USB_PD_MUX_NONE, USB_SWITCH_CONNECT, 0);
+	k_sleep(K_SECONDS(1));
+
+	/* And test the assumption that setting NONE worked */
+	zassert_equal(usb_mux_get(USBC_PORT_C0), USB_PD_MUX_NONE,
+		      "Failed to set mux to initial state");
+}
+
+static void ap_mux_control_after(void *data)
+{
+	/*
+	 * Set all muxes to NONE now that we're done and give time for the
+	 * USB_MUX task to process them.
+	 */
+	usb_mux_set(USBC_PORT_C0, USB_PD_MUX_NONE, USB_SWITCH_CONNECT, 0);
+	k_sleep(K_SECONDS(1));
+}
+
+ZTEST_SUITE(ap_mux_control, drivers_predicate_post_main, NULL,
+	    ap_mux_control_before, ap_mux_control_after, NULL);
+
+ZTEST(ap_mux_control, test_feature_present)
+{
+	struct ec_response_get_features feat = host_cmd_get_features();
+
+	zassert_true(feat.flags[1] &
+			     EC_FEATURE_MASK_1(EC_FEATURE_TYPEC_AP_MUX_SET),
+		     "Failed to see feature present");
+}
+
+ZTEST(ap_mux_control, test_set_muxes)
+{
+	struct ec_response_typec_status status;
+	struct typec_usb_mux_set mux_set;
+	uint32_t port_events;
+	int index;
+	uint8_t set_mode = USB_PD_MUX_DOCK;
+
+	/* Test setting both mux indexes and receiving their events */
+	/* TODO(b/239457738): Loop counter should come from device tree */
+	for (index = 0; index < 2; index++) {
+		mux_set.mux_index = index;
+		mux_set.mux_flags = set_mode;
+
+		host_cmd_typec_control_usb_mux_set(USBC_PORT_C0, mux_set);
+
+		/* Give the task processing time */
+		k_sleep(K_SECONDS(1));
+
+		/*
+		 * TODO(b/239460181): The "AP" should receive
+		 * EC_HOST_EVENT_PD_MCU
+		 */
+
+		/* We should see the right index's event set on the port */
+		status = host_cmd_typec_status(USBC_PORT_C0);
+		port_events = index ? PD_STATUS_EVENT_MUX_1_SET_DONE :
+				      PD_STATUS_EVENT_MUX_0_SET_DONE;
+		zassert_true(status.events & port_events, "Port event missing");
+
+		/* Clear this mux's event */
+		host_cmd_typec_control_clear_events(USBC_PORT_C0, port_events);
+	}
+
+	/*
+	 * Verify our mux mode is reported as set, and that our mux events are
+	 * cleared out
+	 */
+	status = host_cmd_typec_status(USBC_PORT_C0);
+	port_events = PD_STATUS_EVENT_MUX_0_SET_DONE |
+		      PD_STATUS_EVENT_MUX_1_SET_DONE;
+	zassert_false(status.events & port_events, "Port events still set");
+	zassert_equal(status.mux_state, set_mode,
+		      "Mux set to unexpected state");
+}
diff --git a/zephyr/test/drivers/ap_vdm_control/CMakeLists.txt b/zephyr/test/drivers/ap_vdm_control/CMakeLists.txt
new file mode 100644
index 0000000000..6b1756bac4
--- /dev/null
+++ b/zephyr/test/drivers/ap_vdm_control/CMakeLists.txt
@@ -0,0 +1,16 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Create library name based on current directory
+zephyr_library_get_current_dir_lib_name(${ZEPHYR_BASE} lib_name)
+
+# Create interface library
+zephyr_interface_library_named(${lib_name})
+
+# Add source files
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_VDM_AP_CONTROL "${CMAKE_CURRENT_SOURCE_DIR}/src/ap_vdm_control.c")
+zephyr_library_sources_ifndef(CONFIG_PLATFORM_EC_USB_PD_VDM_AP_CONTROL "${CMAKE_CURRENT_SOURCE_DIR}/src/ap_vdm_control_disabled.c")
+
+# Link in the library
+zephyr_library_link_libraries(${lib_name})
diff --git a/zephyr/test/drivers/ap_vdm_control/prj.conf b/zephyr/test/drivers/ap_vdm_control/prj.conf
new file mode 100644
index 0000000000..fb5596ffdc
--- /dev/null
+++ b/zephyr/test/drivers/ap_vdm_control/prj.conf
@@ -0,0 +1,12 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_PLATFORM_EC_USB_PD_DP_HPD_GPIO=y
+CONFIG_PLATFORM_EC_USB_MUX_AP_CONTROL=y
+CONFIG_PLATFORM_EC_USB_MUX_TASK=y
+CONFIG_SHIMMED_TASKS=y
+CONFIG_PLATFORM_EC_USB_PD_VDM_AP_CONTROL=y
+
+CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=n
+CONFIG_PLATFORM_EC_USB_PD_USB4=n
diff --git a/zephyr/test/drivers/ap_vdm_control/src/ap_vdm_control.c b/zephyr/test/drivers/ap_vdm_control/src/ap_vdm_control.c
new file mode 100644
index 0000000000..a5f5fbd7ef
--- /dev/null
+++ b/zephyr/test/drivers/ap_vdm_control/src/ap_vdm_control.c
@@ -0,0 +1,1115 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "usb_dp_alt_mode.h"
+#include "usb_mux.h"
+#include "usb_pd_vdo.h"
+
+#include <stdint.h>
+
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/kernel.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/ztest.h>
+
+#include <gpio.h>
+
+#define TEST_PORT USBC_PORT_C0
+
+struct ap_vdm_control_fixture {
+	const struct emul *tcpci_emul;
+	const struct emul *charger_emul;
+	struct tcpci_partner_data partner;
+	struct tcpci_src_emul_data src_ext;
+};
+
+struct tcpci_cable_data passive_usb3 = {
+	.identity_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_PD, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_IDENT) |
+		VDO_SVDM_VERS(VDM_VER20),
+	.identity_vdm[VDO_INDEX_IDH] = VDO_IDH(
+		/* USB host */ false, /* USB device */ false, IDH_PTYPE_PCABLE,
+		/* modal operation */ false, USB_VID_GOOGLE),
+	.identity_vdm[VDO_INDEX_CSTAT] = 0,
+	.identity_vdm[VDO_INDEX_PRODUCT] = VDO_PRODUCT(0x1234, 0xABCD),
+	.identity_vdm[VDO_INDEX_PTYPE_CABLE1] =
+		VDO_REV30_PASSIVE(USB_R30_SS_U32_U40_GEN2, USB_VBUS_CUR_3A,
+				  USB_REV30_LATENCY_1m, USB_REV30_TYPE_C),
+	.identity_vdos = VDO_INDEX_PTYPE_CABLE1 + 1,
+
+};
+
+static void add_dp_discovery(struct tcpci_partner_data *partner)
+{
+	/* Add Discover Identity response */
+	partner->identity_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_PD, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_IDENT) |
+		VDO_SVDM_VERS(VDM_VER20);
+	partner->identity_vdm[VDO_INDEX_IDH] = VDO_IDH(
+		/* USB host */ false, /* USB device */ true, IDH_PTYPE_HUB,
+		/* modal operation */ true, USB_VID_GOOGLE);
+	partner->identity_vdm[VDO_INDEX_CSTAT] = 0;
+	partner->identity_vdm[VDO_INDEX_PRODUCT] = VDO_PRODUCT(0x1234, 0x5678);
+	/* Hardware version 1, firmware version 2 */
+	partner->identity_vdm[VDO_INDEX_PTYPE_UFP1_VDO] = VDO_UFP1(
+		(VDO_UFP1_CAPABILITY_USB20 | VDO_UFP1_CAPABILITY_USB32),
+		USB_TYPEC_RECEPTACLE, VDO_UFP1_ALT_MODE_RECONFIGURE,
+		USB_R30_SS_U32_U40_GEN2);
+	partner->identity_vdos = VDO_INDEX_PTYPE_UFP1_VDO + 1;
+
+	/* Add Discover Modes response */
+	/* Support one mode for DisplayPort VID.*/
+	partner->modes_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_DISPLAYPORT, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_MODES) |
+		VDO_SVDM_VERS(VDM_VER20);
+	partner->modes_vdm[VDO_INDEX_HDR + 1] =
+		VDO_MODE_DP(MODE_DP_PIN_C | MODE_DP_PIN_D, 0, 1,
+			    CABLE_RECEPTACLE, MODE_DP_V13, MODE_DP_SNK);
+	partner->modes_vdos = VDO_INDEX_HDR + 2;
+
+	/* Add Discover SVIDs response */
+	/* Support DisplayPort VID. */
+	partner->svids_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_PD, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_SVID) |
+		VDO_SVDM_VERS(VDM_VER20);
+	partner->svids_vdm[VDO_INDEX_HDR + 1] =
+		VDO_SVID(USB_SID_DISPLAYPORT, 0);
+	partner->svids_vdos = VDO_INDEX_HDR + 2;
+}
+
+static void add_displayport_mode_responses(struct tcpci_partner_data *partner)
+{
+	/* Add DisplayPort EnterMode response */
+	partner->enter_mode_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_DISPLAYPORT, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_ENTER_MODE) |
+		VDO_SVDM_VERS(VDM_VER20);
+	partner->enter_mode_vdos = VDO_INDEX_HDR + 1;
+
+	/* Add DisplayPort StatusUpdate response */
+	partner->dp_status_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_DISPLAYPORT, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DP_STATUS) |
+		VDO_SVDM_VERS(VDM_VER20);
+	partner->dp_status_vdm[VDO_INDEX_HDR + 1] =
+		VDO_DP_STATUS(0, /* IRQ_HPD */
+			      false, /* HPD_HI|LOW - Changed*/
+			      0, /* request exit DP */
+			      0, /* request exit USB */
+			      1, /* MF pref */
+			      true, /* DP Enabled */
+			      0, /* power low e.g. normal */
+			      0x2 /* Connected as Sink */);
+	partner->dp_status_vdos = VDO_INDEX_HDR + 2;
+
+	/* Add DisplayPort Configure Response */
+	partner->dp_config_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_DISPLAYPORT, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DP_CONFIG) |
+		VDO_SVDM_VERS(VDM_VER20);
+	partner->dp_config_vdos = VDO_INDEX_HDR + 1;
+}
+
+static void verify_vdm_req(struct ap_vdm_control_fixture *fixture,
+			   struct typec_vdm_req *req)
+{
+	struct tcpci_partner_log_msg *msg;
+	bool message_seen = 0;
+
+	SYS_SLIST_FOR_EACH_CONTAINER(&fixture->partner.msg_log, msg, node)
+	{
+		uint16_t header = sys_get_le16(msg->buf);
+
+		/* Ignore messages from ourselves */
+		if (msg->sender == TCPCI_PARTNER_SENDER_PARTNER)
+			continue;
+
+		/*
+		 * Control messages, non-VDMs, and extended messages are not of
+		 * interest
+		 */
+		if ((PD_HEADER_CNT(header) == 0) ||
+		    (PD_HEADER_TYPE(header) != PD_DATA_VENDOR_DEF) ||
+		    (PD_HEADER_EXT(header) != 0)) {
+			continue;
+		}
+
+		if (req->partner_type != msg->sop)
+			continue;
+
+		/* We have a VDM, check entry we're interested in */
+		if (memcmp(msg->buf + 2, req->vdm_data,
+			   req->vdm_data_objects * sizeof(uint32_t)) == 0) {
+			message_seen = true;
+			break;
+		}
+	}
+
+	zassert_true(message_seen, "Expected message not found");
+}
+
+static void verify_no_vdms(struct ap_vdm_control_fixture *fixture)
+{
+	struct tcpci_partner_log_msg *msg;
+
+	/* LCOV_EXCL_START */
+	/*
+	 * Code is not expected to be reached, but this check is
+	 * written to be tolerant of unrelated messages coming through
+	 * during the test run to avoid needlessly brittle test code.
+	 */
+	SYS_SLIST_FOR_EACH_CONTAINER(&fixture->partner.msg_log, msg, node)
+	{
+		uint16_t header = sys_get_le16(msg->buf);
+
+		/* Ignore messages from ourselves */
+		if (msg->sender == TCPCI_PARTNER_SENDER_PARTNER)
+			continue;
+
+		/*
+		 * Control messages, non-VDMs, and extended messages are not of
+		 * interest
+		 */
+		if ((PD_HEADER_CNT(header) == 0) ||
+		    (PD_HEADER_TYPE(header) != PD_DATA_VENDOR_DEF) ||
+		    (PD_HEADER_EXT(header) != 0)) {
+			continue;
+		}
+
+		zassert_unreachable();
+	}
+	/* LCOV_EXCL_STOP */
+}
+
+static void *ap_vdm_control_setup(void)
+{
+	static struct ap_vdm_control_fixture fixture;
+	struct tcpci_partner_data *partner = &fixture.partner;
+	struct tcpci_src_emul_data *src_ext = &fixture.src_ext;
+
+	tcpci_partner_init(partner, PD_REV30);
+	partner->extensions = tcpci_src_emul_init(src_ext, partner, NULL);
+
+	/* Get references for the emulators */
+	fixture.tcpci_emul = EMUL_DT_GET(DT_NODELABEL(tcpci_emul));
+	fixture.charger_emul = EMUL_DT_GET(DT_NODELABEL(isl923x_emul));
+
+	return &fixture;
+}
+
+static void ap_vdm_control_before(void *data)
+{
+	struct ap_vdm_control_fixture *fix = data;
+	struct tcpci_partner_data *partner = &fix->partner;
+
+	/* Set chipset on so the "AP" is on to give us commands */
+	test_set_chipset_to_s0();
+
+	/* Set up the partner as DP-capable with a passive cable */
+	add_dp_discovery(partner);
+	partner->cable = &passive_usb3;
+	add_displayport_mode_responses(partner);
+
+	/* Connect our port partner */
+	connect_source_to_port(&fix->partner, &fix->src_ext, 0, fix->tcpci_emul,
+			       fix->charger_emul);
+}
+
+static void ap_vdm_control_after(void *data)
+{
+	struct ap_vdm_control_fixture *fix = data;
+
+	disconnect_source_from_port(fix->tcpci_emul, fix->charger_emul);
+	tcpci_partner_common_clear_logged_msgs(&fix->partner);
+}
+
+ZTEST_SUITE(ap_vdm_control, drivers_predicate_post_main, ap_vdm_control_setup,
+	    ap_vdm_control_before, ap_vdm_control_after, NULL);
+
+ZTEST_F(ap_vdm_control, test_feature_present)
+{
+	struct ec_response_get_features feat = host_cmd_get_features();
+
+	zassert_true(feat.flags[1] &
+			     EC_FEATURE_MASK_1(EC_FEATURE_TYPEC_AP_VDM_SEND),
+		     "Failed to see feature present");
+}
+
+/* TYPEC_CONTROL_COMMAND_SEND_VDM_REQ tests */
+ZTEST_F(ap_vdm_control, test_send_vdm_req_bad_port)
+{
+	struct ec_params_typec_control params = {
+		.port = 85,
+		.command = TYPEC_CONTROL_COMMAND_SEND_VDM_REQ,
+		.vdm_req_params = {
+			.vdm_data = { 0 },
+			.vdm_data_objects = 1,
+			.partner_type = TYPEC_PARTNER_SOP,
+		},
+	};
+
+	zassert_equal(ec_cmd_typec_control(NULL, &params), EC_RES_INVALID_PARAM,
+		      "Failed to see port error");
+}
+
+ZTEST_F(ap_vdm_control, test_send_vdm_req_bad_type)
+{
+	struct ec_params_typec_control params = {
+		.port = TEST_PORT,
+		.command = TYPEC_CONTROL_COMMAND_SEND_VDM_REQ,
+		.vdm_req_params = {
+			.vdm_data = { 0 },
+			.vdm_data_objects = 1,
+			.partner_type = TYPEC_PARTNER_SOP_PRIME_PRIME + 1,
+		},
+	};
+
+	zassert_equal(ec_cmd_typec_control(NULL, &params), EC_RES_INVALID_PARAM,
+		      "Failed to see port error");
+}
+
+ZTEST_F(ap_vdm_control, test_send_vdm_req_bad_count)
+{
+	struct ec_params_typec_control params = {
+		.port = TEST_PORT,
+		.command = TYPEC_CONTROL_COMMAND_SEND_VDM_REQ,
+		.vdm_req_params = {
+			.vdm_data = { 0 },
+			.vdm_data_objects = 0,
+			.partner_type = TYPEC_PARTNER_SOP,
+		},
+	};
+
+	zassert_equal(ec_cmd_typec_control(NULL, &params), EC_RES_INVALID_PARAM,
+		      "Failed to see port error");
+}
+
+ZTEST_F(ap_vdm_control, test_send_vdm_sop_req_valid)
+{
+	uint32_t vdm_req_header = VDO(USB_SID_PD, 1, CMD_DISCOVER_IDENT) |
+				  VDO_SVDM_VERS(VDM_VER20);
+	struct typec_vdm_req req = {
+		.vdm_data = { vdm_req_header },
+		.vdm_data_objects = 1,
+		.partner_type = TYPEC_PARTNER_SOP,
+	};
+
+	tcpci_partner_common_enable_pd_logging(&fixture->partner, true);
+	host_cmd_typec_control_vdm_req(TEST_PORT, req);
+	k_sleep(K_SECONDS(1));
+
+	tcpci_partner_common_enable_pd_logging(&fixture->partner, false);
+
+	/* Look for our REQ */
+	verify_vdm_req(fixture, &req);
+}
+
+ZTEST_F(ap_vdm_control, test_send_vdm_sop_prime_req_valid)
+{
+	uint32_t vdm_req_header = VDO(USB_SID_PD, 1, CMD_DISCOVER_IDENT) |
+				  VDO_SVDM_VERS(VDM_VER20);
+	struct typec_vdm_req req = {
+		.vdm_data = { vdm_req_header },
+		.vdm_data_objects = 1,
+		.partner_type = TYPEC_PARTNER_SOP_PRIME,
+	};
+
+	tcpci_partner_common_enable_pd_logging(&fixture->partner, true);
+	host_cmd_typec_control_vdm_req(TEST_PORT, req);
+	k_sleep(K_SECONDS(1));
+
+	tcpci_partner_common_enable_pd_logging(&fixture->partner, false);
+
+	/* Look for our REQ */
+	verify_vdm_req(fixture, &req);
+}
+
+ZTEST_F(ap_vdm_control, test_send_vdm_sop_attention_bad)
+{
+	uint32_t vdm_req_header = VDO(USB_SID_DISPLAYPORT, 1, CMD_ATTENTION) |
+				  VDO_SVDM_VERS(VDM_VER20);
+	struct ec_params_typec_control params = {
+		.port = TEST_PORT,
+		.command = TYPEC_CONTROL_COMMAND_SEND_VDM_REQ,
+		.vdm_req_params = {
+			.vdm_data = { vdm_req_header },
+			.vdm_data_objects = 5,
+			.partner_type = TYPEC_PARTNER_SOP,
+		},
+	};
+
+	zassert_equal(ec_cmd_typec_control(NULL, &params), EC_RES_INVALID_PARAM,
+		      "Failed to see port error");
+}
+
+ZTEST_F(ap_vdm_control, test_send_vdm_req_in_progress)
+{
+	uint32_t vdm_req_header = VDO(USB_SID_PD, 1, CMD_DISCOVER_IDENT) |
+				  VDO_SVDM_VERS(VDM_VER20);
+	struct ec_params_typec_control params = {
+		.port = TEST_PORT,
+		.command = TYPEC_CONTROL_COMMAND_SEND_VDM_REQ,
+		.vdm_req_params = {
+			.vdm_data = { vdm_req_header },
+			.vdm_data_objects = 1,
+			.partner_type = TYPEC_PARTNER_SOP,
+		},
+	};
+
+	/*
+	 * First command should succeed, but given no time to process the second
+	 * should return busy
+	 */
+	zassert_equal(ec_cmd_typec_control(NULL, &params), EC_RES_SUCCESS,
+		      "Failed to send successful request");
+	zassert_equal(ec_cmd_typec_control(NULL, &params), EC_RES_BUSY,
+		      "Failed to see busy");
+}
+
+/* EC_CMD_TYPEC_VDM_RESPONSE tests */
+ZTEST_F(ap_vdm_control, test_vdm_response_ack)
+{
+	struct ec_response_typec_status status;
+	struct ec_response_typec_vdm_response vdm_resp;
+	uint32_t vdm_req_header = VDO(USB_SID_PD, 1, CMD_DISCOVER_IDENT) |
+				  VDO_SVDM_VERS(VDM_VER20);
+	struct typec_vdm_req req = {
+		.vdm_data = { vdm_req_header },
+		.vdm_data_objects = 1,
+		.partner_type = TYPEC_PARTNER_SOP,
+	};
+
+	host_cmd_typec_control_vdm_req(TEST_PORT, req);
+	k_sleep(K_SECONDS(1));
+
+	/* Look for our notification and reply */
+	status = host_cmd_typec_status(TEST_PORT);
+	zassert_true(status.events & PD_STATUS_EVENT_VDM_REQ_REPLY,
+		     "Failed to see VDM ACK event");
+
+	vdm_resp = host_cmd_typec_vdm_response(TEST_PORT);
+	zassert_equal(vdm_resp.vdm_response_err, EC_RES_SUCCESS);
+	zassert_equal(vdm_resp.partner_type, req.partner_type,
+		      "Failed to see correct partner");
+	zassert_equal(vdm_resp.vdm_data_objects, fixture->partner.identity_vdos,
+		      "Failed to see correct VDO num");
+	zassert_equal(memcmp(vdm_resp.vdm_response,
+			     fixture->partner.identity_vdm,
+			     vdm_resp.vdm_data_objects * sizeof(uint32_t)),
+		      0, "Failed to see correct VDM contents");
+}
+
+ZTEST_F(ap_vdm_control, test_vdm_request_nak)
+{
+	struct ec_response_typec_status status;
+	struct ec_response_typec_vdm_response vdm_resp;
+	uint32_t vdm_req_header = VDO(USB_SID_DISPLAYPORT, 1, CMD_ENTER_MODE) |
+				  VDO_SVDM_VERS(VDM_VER20);
+	struct typec_vdm_req req = {
+		.vdm_data = { vdm_req_header },
+		.vdm_data_objects = 1,
+		.partner_type = TYPEC_PARTNER_SOP,
+	};
+
+	/* Add DisplayPort EnterMode NAK */
+	fixture->partner.enter_mode_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_DISPLAYPORT, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_NAK) | CMD_ENTER_MODE) |
+		VDO_SVDM_VERS(VDM_VER20);
+	fixture->partner.enter_mode_vdos = VDO_INDEX_HDR + 1;
+
+	host_cmd_typec_control_vdm_req(TEST_PORT, req);
+	k_sleep(K_SECONDS(1));
+
+	/* Look for our notification and reply */
+	status = host_cmd_typec_status(TEST_PORT);
+	zassert_true(status.events & PD_STATUS_EVENT_VDM_REQ_REPLY,
+		     "Failed to see VDM NAK event");
+
+	vdm_resp = host_cmd_typec_vdm_response(TEST_PORT);
+	zassert_equal(vdm_resp.vdm_response_err, EC_RES_SUCCESS);
+	zassert_equal(vdm_resp.partner_type, req.partner_type,
+		      "Failed to see correct partner");
+	zassert_equal(vdm_resp.vdm_data_objects,
+		      fixture->partner.enter_mode_vdos,
+		      "Failed to see correct VDO num");
+	zassert_equal(memcmp(vdm_resp.vdm_response,
+			     fixture->partner.enter_mode_vdm,
+			     vdm_resp.vdm_data_objects * sizeof(uint32_t)),
+		      0, "Failed to see correct VDM contents");
+}
+
+ZTEST_F(ap_vdm_control, test_vdm_request_failed)
+{
+	struct ec_response_typec_status status;
+	struct ec_response_typec_vdm_response vdm_resp;
+
+	uint32_t vdm_req_header = VDO(USB_SID_DISPLAYPORT, 1, CMD_ENTER_MODE) |
+				  VDO_SVDM_VERS(VDM_VER20);
+	struct typec_vdm_req req = {
+		.vdm_data = { vdm_req_header },
+		.vdm_data_objects = 1,
+		.partner_type = TYPEC_PARTNER_SOP,
+	};
+
+	/* Do not advertise an EnterMode response */
+	fixture->partner.enter_mode_vdos = 0;
+
+	host_cmd_typec_control_vdm_req(TEST_PORT, req);
+	k_sleep(K_SECONDS(1));
+
+	/* Look for our notification and lack of reply */
+	status = host_cmd_typec_status(TEST_PORT);
+	zassert_true(status.events & PD_STATUS_EVENT_VDM_REQ_FAILED,
+		     "Failed to see notice of no reply");
+
+	vdm_resp = host_cmd_typec_vdm_response(TEST_PORT);
+	zassert_equal(vdm_resp.vdm_response_err, EC_RES_UNAVAILABLE,
+		      "Failed to get unavailable");
+}
+
+ZTEST_F(ap_vdm_control, test_vdm_request_bad_port)
+{
+	struct ec_response_typec_vdm_response vdm_resp;
+	struct ec_params_typec_vdm_response params = { .port = 88 };
+
+	zassert_equal(ec_cmd_typec_vdm_response(NULL, &params, &vdm_resp),
+		      EC_RES_INVALID_PARAM, "Failed to see bad port");
+}
+
+ZTEST_F(ap_vdm_control, test_vdm_request_in_progress)
+{
+	struct ec_response_typec_vdm_response vdm_resp;
+
+	uint32_t vdm_req_header = VDO(USB_SID_PD, 1, CMD_DISCOVER_IDENT) |
+				  VDO_SVDM_VERS(VDM_VER20);
+	struct typec_vdm_req req = {
+		.vdm_data = { vdm_req_header },
+		.vdm_data_objects = 1,
+		.partner_type = TYPEC_PARTNER_SOP,
+	};
+
+	host_cmd_typec_control_vdm_req(TEST_PORT, req);
+
+	/* Give no processing time and immediately ask for our result */
+	vdm_resp = host_cmd_typec_vdm_response(TEST_PORT);
+	zassert_equal(vdm_resp.vdm_response_err, EC_RES_BUSY,
+		      "Failed to get busy");
+}
+
+ZTEST_F(ap_vdm_control, test_vdm_request_no_send)
+{
+	struct ec_response_typec_vdm_response vdm_resp;
+
+	/* Check for an error on a fresh connection with no VDM REQ sent */
+	vdm_resp = host_cmd_typec_vdm_response(TEST_PORT);
+	zassert_equal(vdm_resp.vdm_response_err, EC_RES_UNAVAILABLE,
+		      "Failed to see no message ready");
+}
+
+ZTEST_F(ap_vdm_control, test_vdm_response_disconnect_clear)
+{
+	struct ec_response_typec_vdm_response vdm_resp;
+	uint32_t vdm_req_header = VDO(USB_SID_PD, 1, CMD_DISCOVER_IDENT) |
+				  VDO_SVDM_VERS(VDM_VER20);
+	struct typec_vdm_req req = {
+		.vdm_data = { vdm_req_header },
+		.vdm_data_objects = 1,
+		.partner_type = TYPEC_PARTNER_SOP,
+	};
+
+	host_cmd_typec_control_vdm_req(TEST_PORT, req);
+	k_sleep(K_SECONDS(1));
+
+	/* Now disconnect and verify there's nothing to see here */
+	disconnect_source_from_port(fixture->tcpci_emul, fixture->charger_emul);
+
+	vdm_resp = host_cmd_typec_vdm_response(TEST_PORT);
+	zassert_equal(vdm_resp.vdm_response_err, EC_RES_UNAVAILABLE,
+		      "Failed to see reply cleared");
+	zassert_equal(vdm_resp.vdm_data_objects, 0,
+		      "Failed to see no VDOs available");
+}
+
+/* Tests for the DP entry flow and related requirements */
+static void verify_expected_reply(enum typec_partner_type type,
+				  int expected_num_objects, uint32_t *contents)
+{
+	struct ec_response_typec_status status;
+	struct ec_response_typec_vdm_response vdm_resp;
+
+	status = host_cmd_typec_status(TEST_PORT);
+	zassert_true(status.events & PD_STATUS_EVENT_VDM_REQ_REPLY,
+		     "Failed to see VDM ACK event");
+
+	vdm_resp = host_cmd_typec_vdm_response(TEST_PORT);
+	zassert_equal(vdm_resp.partner_type, type,
+		      "Failed to see correct partner");
+	zassert_equal(vdm_resp.vdm_data_objects, expected_num_objects,
+		      "Failed to see correct number of objects");
+	zassert_equal(memcmp(vdm_resp.vdm_response, contents,
+			     expected_num_objects * sizeof(uint32_t)),
+		      0, "Failed to see correct VDM contents");
+}
+
+static void run_verify_dp_entry(struct ap_vdm_control_fixture *fixture,
+				int opos)
+{
+	/*
+	 * Test the full flow of DP entry and configure, to set up for
+	 * further test cases.
+	 */
+	struct typec_vdm_req req = {
+		.vdm_data = { VDO(USB_SID_DISPLAYPORT, 1,
+				  CMD_ENTER_MODE | VDO_OPOS(opos)) |
+			      VDO_SVDM_VERS(VDM_VER20) },
+		.vdm_data_objects = 1,
+		.partner_type = TYPEC_PARTNER_SOP,
+	};
+
+	/* Step 1: EnterMode */
+	host_cmd_typec_control_vdm_req(TEST_PORT, req);
+	k_sleep(K_MSEC(100));
+
+	verify_expected_reply(req.partner_type,
+			      fixture->partner.enter_mode_vdos,
+			      fixture->partner.enter_mode_vdm);
+
+	/* Step 2: DP Status */
+	req.vdm_data[0] =
+		VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_STATUS | VDO_OPOS(opos)) |
+		VDO_SVDM_VERS(VDM_VER20);
+	req.vdm_data[1] = VDO_DP_STATUS(0, /* HPD IRQ  ... not applicable */
+					0, /* HPD level ... not applicable */
+					0, /* exit DP? ... no */
+					0, /* usb mode? ... no */
+					0, /* multi-function ... no */
+					0, /* currently enabled ... no */
+					0, /* power low? ... no */
+					1 /* DP source connected */);
+	req.vdm_data_objects = 2;
+	req.partner_type = TYPEC_PARTNER_SOP;
+
+	host_cmd_typec_control_vdm_req(TEST_PORT, req);
+	k_sleep(K_MSEC(100));
+
+	verify_expected_reply(req.partner_type, fixture->partner.dp_status_vdos,
+			      fixture->partner.dp_status_vdm);
+
+	/* Step 3: DP Configure */
+	req.vdm_data[0] =
+		VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_CONFIG | VDO_OPOS(opos)) |
+		VDO_SVDM_VERS(VDM_VER20);
+	req.vdm_data[1] = VDO_DP_CFG(MODE_DP_PIN_D, /* pin mode */
+				     1, /* DPv1.3 signaling */
+				     2); /* Set that partner should be DP sink
+					  */
+	req.vdm_data_objects = 2;
+	req.partner_type = TYPEC_PARTNER_SOP;
+
+	host_cmd_typec_control_vdm_req(TEST_PORT, req);
+	k_sleep(K_MSEC(100));
+
+	verify_expected_reply(req.partner_type, fixture->partner.dp_config_vdos,
+			      fixture->partner.dp_config_vdm);
+}
+
+ZTEST_F(ap_vdm_control, test_vdm_attention_none)
+{
+	struct ec_response_typec_vdm_response vdm_resp;
+	int opos = 1;
+
+	run_verify_dp_entry(fixture, opos);
+
+	/* Check that we have no Attention messages and none in the queue */
+	vdm_resp = host_cmd_typec_vdm_response(TEST_PORT);
+	zassert_equal(vdm_resp.vdm_attention_objects, 0,
+		      "Failed to see empty message");
+	zassert_equal(vdm_resp.vdm_attention_left, 0,
+		      "Failed to see no more messages");
+}
+
+ZTEST_F(ap_vdm_control, test_vdm_attention_one)
+{
+	uint32_t vdm_attention_data[2];
+	int opos = 1;
+	struct ec_response_typec_status status;
+	struct ec_response_typec_vdm_response vdm_resp;
+
+	run_verify_dp_entry(fixture, opos);
+
+	/* Test that we see our Attention message */
+	vdm_attention_data[0] =
+		VDO(USB_SID_DISPLAYPORT, 1,
+		    VDO_OPOS(opos) | VDO_CMDT(CMDT_INIT) | CMD_ATTENTION) |
+		VDO_SVDM_VERS(VDM_VER20);
+	vdm_attention_data[1] = VDO_DP_STATUS(1, /* IRQ_HPD */
+					      true, /* HPD_HI|LOW - Changed*/
+					      0, /* request exit DP */
+					      0, /* request exit USB */
+					      0, /* MF pref */
+					      true, /* DP Enabled */
+					      0, /* power low e.g. normal */
+					      0x2 /* Connected as Sink */);
+	tcpci_partner_send_data_msg(&fixture->partner, PD_DATA_VENDOR_DEF,
+				    vdm_attention_data, 2, 0);
+
+	k_sleep(K_MSEC(100));
+	/*
+	 * Verify the event and the contents of our Attention
+	 */
+	status = host_cmd_typec_status(TEST_PORT);
+	zassert_true(status.events & PD_STATUS_EVENT_VDM_ATTENTION,
+		     "Failed to see VDM Attention event");
+
+	vdm_resp = host_cmd_typec_vdm_response(TEST_PORT);
+	zassert_equal(vdm_resp.vdm_attention_objects, 2,
+		      "Failed to see correct number of objects");
+	zassert_equal(vdm_resp.vdm_attention_left, 0,
+		      "Failed to see 0 more in queue");
+	zassert_equal(memcmp(vdm_resp.vdm_attention, vdm_attention_data,
+			     vdm_resp.vdm_attention_objects * sizeof(uint32_t)),
+		      0, "Failed to see correct Attention VDM contents");
+}
+
+ZTEST_F(ap_vdm_control, test_vdm_attention_two)
+{
+	uint32_t vdm_attention_first[2];
+	uint32_t vdm_attention_second[2];
+	int opos = 1;
+	struct ec_response_typec_status status;
+	struct ec_response_typec_vdm_response vdm_resp;
+
+	run_verify_dp_entry(fixture, opos);
+
+	/* Test that we see our first Attention message followed by second */
+	vdm_attention_first[0] =
+		VDO(USB_SID_DISPLAYPORT, 1,
+		    VDO_OPOS(opos) | VDO_CMDT(CMDT_INIT) | CMD_ATTENTION) |
+		VDO_SVDM_VERS(VDM_VER20);
+	vdm_attention_first[1] = VDO_DP_STATUS(0, /* IRQ_HPD */
+					       false, /* HPD_HI|LOW - Changed*/
+					       0, /* request exit DP */
+					       0, /* request exit USB */
+					       0, /* MF pref */
+					       true, /* DP Enabled */
+					       0, /* power low e.g. normal */
+					       0x2 /* Connected as Sink */);
+	tcpci_partner_send_data_msg(&fixture->partner, PD_DATA_VENDOR_DEF,
+				    vdm_attention_first, 2, 0);
+
+	k_sleep(K_MSEC(100));
+
+	/* Number two time */
+	vdm_attention_second[0] =
+		VDO(USB_SID_DISPLAYPORT, 1,
+		    VDO_OPOS(opos) | VDO_CMDT(CMDT_INIT) | CMD_ATTENTION) |
+		VDO_SVDM_VERS(VDM_VER20);
+	vdm_attention_second[1] = VDO_DP_STATUS(1, /* IRQ_HPD */
+						true, /* HPD_HI|LOW - Changed*/
+						0, /* request exit DP */
+						0, /* request exit USB */
+						0, /* MF pref */
+						true, /* DP Enabled */
+						0, /* power low e.g. normal */
+						0x2 /* Connected as Sink */);
+	tcpci_partner_send_data_msg(&fixture->partner, PD_DATA_VENDOR_DEF,
+				    vdm_attention_second, 2, 0);
+
+	k_sleep(K_MSEC(100));
+	/*
+	 * Verify the event and the contents of our Attention from each in
+	 * the proper order
+	 */
+	status = host_cmd_typec_status(TEST_PORT);
+	zassert_true(status.events & PD_STATUS_EVENT_VDM_ATTENTION,
+		     "Failed to see VDM Attention event");
+
+	vdm_resp = host_cmd_typec_vdm_response(TEST_PORT);
+	zassert_equal(vdm_resp.vdm_attention_objects, 2,
+		      "Failed to see correct number of objects");
+	zassert_equal(vdm_resp.vdm_attention_left, 1,
+		      "Failed to see 1 more in queue");
+	zassert_equal(memcmp(vdm_resp.vdm_attention, vdm_attention_first,
+			     vdm_resp.vdm_attention_objects * sizeof(uint32_t)),
+		      0, "Failed to see correct first Attention VDM contents");
+
+	vdm_resp = host_cmd_typec_vdm_response(TEST_PORT);
+	zassert_equal(vdm_resp.vdm_attention_objects, 2,
+		      "Failed to see correct number of objects");
+	zassert_equal(vdm_resp.vdm_attention_left, 0,
+		      "Failed to see 0 more in queue");
+	zassert_equal(memcmp(vdm_resp.vdm_attention, vdm_attention_second,
+			     vdm_resp.vdm_attention_objects * sizeof(uint32_t)),
+		      0, "Failed to see correct second Attention VDM contents");
+}
+
+ZTEST_F(ap_vdm_control, test_vdm_attention_disconnect_clear)
+{
+	uint32_t vdm_attention_data[2];
+	int opos = 1;
+	struct ec_response_typec_vdm_response vdm_resp;
+
+	run_verify_dp_entry(fixture, opos);
+
+	/* Send an Attention message */
+	vdm_attention_data[0] =
+		VDO(USB_SID_DISPLAYPORT, 1,
+		    VDO_OPOS(opos) | VDO_CMDT(CMDT_INIT) | CMD_ATTENTION);
+	vdm_attention_data[0] |= VDO_SVDM_VERS(VDM_VER20);
+	vdm_attention_data[1] = VDO_DP_STATUS(1, /* IRQ_HPD */
+					      true, /* HPD_HI|LOW - Changed*/
+					      0, /* request exit DP */
+					      0, /* request exit USB */
+					      0, /* MF pref */
+					      true, /* DP Enabled */
+					      0, /* power low e.g. normal */
+					      0x2 /* Connected as Sink */);
+	tcpci_partner_send_data_msg(&fixture->partner, PD_DATA_VENDOR_DEF,
+				    vdm_attention_data, 2, 0);
+
+	k_sleep(K_SECONDS(1));
+	/*
+	 * Disconnect and verify no messages are reported
+	 */
+	disconnect_source_from_port(fixture->tcpci_emul, fixture->charger_emul);
+
+	vdm_resp = host_cmd_typec_vdm_response(TEST_PORT);
+	zassert_equal(vdm_resp.vdm_attention_objects, 0,
+		      "Failed to see empty message");
+	zassert_equal(vdm_resp.vdm_attention_left, 0,
+		      "Failed to see no more messages");
+}
+
+ZTEST_F(ap_vdm_control, test_no_ec_dp_enter)
+{
+	struct ec_params_typec_control params = {
+		.port = TEST_PORT,
+		.command = TYPEC_CONTROL_COMMAND_ENTER_MODE,
+		.mode_to_enter = TYPEC_MODE_DP,
+	};
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_PARAMS(EC_CMD_TYPEC_CONTROL, 0, params);
+
+	/*
+	 * Confirm that the EC doesn't try to send EnterMode messages for DP on
+	 * its own through the EC DPM logic
+	 */
+	tcpci_partner_common_enable_pd_logging(&fixture->partner, true);
+	zassert_equal(host_command_process(&args), EC_RES_INVALID_PARAM);
+	k_sleep(K_SECONDS(1));
+
+	tcpci_partner_common_enable_pd_logging(&fixture->partner, false);
+
+	verify_no_vdms(fixture);
+}
+
+ZTEST_F(ap_vdm_control, test_no_ec_dp_exit)
+{
+	/*
+	 * Confirm that the EC won't try to exit DP mode on its own through the
+	 * EC's DPM logic
+	 */
+	run_verify_dp_entry(fixture, 1);
+
+	tcpci_partner_common_enable_pd_logging(&fixture->partner, true);
+	host_cmd_typec_control_exit_modes(TEST_PORT);
+	k_sleep(K_SECONDS(1));
+
+	tcpci_partner_common_enable_pd_logging(&fixture->partner, false);
+
+	verify_no_vdms(fixture);
+}
+
+ZTEST_F(ap_vdm_control, test_dp_stub_returns)
+{
+	int temp;
+	uint32_t data[2];
+
+	/*
+	 * Confirm that the DP stubs return what we expect them to without
+	 * the EC running its DP module
+	 */
+	run_verify_dp_entry(fixture, 1);
+
+	zassert_false(dp_is_active(TEST_PORT));
+	zassert_true(dp_is_idle(TEST_PORT));
+	zassert_false(dp_entry_is_done(TEST_PORT));
+	zassert_equal(dp_setup_next_vdm(TEST_PORT, &temp, data),
+		      MSG_SETUP_ERROR);
+}
+
+ZTEST_F(ap_vdm_control, test_no_ec_dp_mode)
+{
+	struct ec_response_typec_status status;
+	struct ec_response_usb_pd_control_v2 legacy_status;
+	struct ec_params_usb_pd_control params = {
+		.port = TEST_PORT,
+		.role = USB_PD_CTRL_ROLE_NO_CHANGE,
+		.mux = USB_PD_CTRL_MUX_NO_CHANGE,
+		.swap = USB_PD_CTRL_SWAP_NONE
+	};
+	struct host_cmd_handler_args args = BUILD_HOST_COMMAND(
+		EC_CMD_USB_PD_CONTROL, 2, legacy_status, params);
+
+	/*
+	 * Confirm that neither old nor new APIs see the EC selecting a DP pin
+	 * mode
+	 */
+	run_verify_dp_entry(fixture, 1);
+
+	zassert_ok(host_command_process(&args));
+	zassert_equal(legacy_status.dp_mode, 0);
+
+	status = host_cmd_typec_status(TEST_PORT);
+	zassert_equal(status.dp_pin, 0);
+}
+
+ZTEST_F(ap_vdm_control, test_vdm_hpd_level)
+{
+	uint32_t vdm_attention_data[2];
+	int opos = 1;
+	const struct gpio_dt_spec *gpio =
+		GPIO_DT_FROM_NODELABEL(gpio_usb_c0_hpd);
+
+	/* HPD GPIO should be low before the test */
+	zassert_equal(gpio_emul_output_get(gpio->port, gpio->pin), 0);
+
+	run_verify_dp_entry(fixture, opos);
+
+	/* Now send Attention to change HPD */
+	vdm_attention_data[0] =
+		VDO(USB_SID_DISPLAYPORT, 1,
+		    VDO_OPOS(opos) | VDO_CMDT(CMDT_INIT) | CMD_ATTENTION) |
+		VDO_SVDM_VERS(VDM_VER20);
+	vdm_attention_data[1] = VDO_DP_STATUS(1, /* IRQ_HPD */
+					      true, /* HPD_HI|LOW - Changed*/
+					      0, /* request exit DP */
+					      0, /* request exit USB */
+					      0, /* MF pref */
+					      true, /* DP Enabled */
+					      0, /* power low e.g. normal */
+					      0x2 /* Connected as Sink */);
+	tcpci_partner_send_data_msg(&fixture->partner, PD_DATA_VENDOR_DEF,
+				    vdm_attention_data, 2, 0);
+
+	k_sleep(K_MSEC(100));
+	/*
+	 * Verify the HPD GPIO is set now
+	 */
+	zassert_equal(gpio_emul_output_get(gpio->port, gpio->pin), 1);
+}
+
+ZTEST_F(ap_vdm_control, test_vdm_hpd_irq_ignored)
+{
+	uint32_t vdm_attention_data[2];
+	int opos = 1;
+	const struct gpio_dt_spec *gpio =
+		GPIO_DT_FROM_NODELABEL(gpio_usb_c0_hpd);
+
+	/* HPD GPIO should be low before the test */
+	zassert_equal(gpio_emul_output_get(gpio->port, gpio->pin), 0);
+
+	run_verify_dp_entry(fixture, opos);
+
+	/* Send our bad Attention message */
+	vdm_attention_data[0] =
+		VDO(USB_SID_DISPLAYPORT, 1,
+		    VDO_OPOS(opos) | VDO_CMDT(CMDT_INIT) | CMD_ATTENTION) |
+		VDO_SVDM_VERS(VDM_VER20);
+	vdm_attention_data[1] = VDO_DP_STATUS(1, /* IRQ_HPD */
+					      false, /* HPD_HI|LOW - Changed*/
+					      0, /* request exit DP */
+					      0, /* request exit USB */
+					      0, /* MF pref */
+					      true, /* DP Enabled */
+					      0, /* power low e.g. normal */
+					      0x2 /* Connected as Sink */);
+	tcpci_partner_send_data_msg(&fixture->partner, PD_DATA_VENDOR_DEF,
+				    vdm_attention_data, 2, 0);
+
+	k_sleep(K_MSEC(100));
+	/*
+	 * Verify the HPD IRQ was rejected since HPD is low
+	 */
+	zassert_equal(gpio_emul_output_get(gpio->port, gpio->pin), 0);
+}
+
+ZTEST_F(ap_vdm_control, test_vdm_status_hpd)
+{
+	int opos = 1;
+	const struct gpio_dt_spec *gpio =
+		GPIO_DT_FROM_NODELABEL(gpio_usb_c0_hpd);
+
+	/* HPD GPIO should be low before the test */
+	zassert_equal(gpio_emul_output_get(gpio->port, gpio->pin), 0);
+
+	/* Set up our slightly different DP Status */
+	fixture->partner.dp_status_vdm[VDO_INDEX_HDR + 1] =
+		VDO_DP_STATUS(0, /* IRQ_HPD */
+			      true, /* HPD_HI|LOW - Changed*/
+			      0, /* request exit DP */
+			      0, /* request exit USB */
+			      1, /* MF pref */
+			      true, /* DP Enabled */
+			      0, /* power low e.g. normal */
+			      0x2 /* Connected as Sink */);
+
+	/* Run Entry step by step to check HPD at each point */
+	struct typec_vdm_req req = {
+		.vdm_data = { VDO(USB_SID_DISPLAYPORT, 1,
+				  CMD_ENTER_MODE | VDO_OPOS(opos)) |
+			      VDO_SVDM_VERS(VDM_VER20) },
+		.vdm_data_objects = 1,
+		.partner_type = TYPEC_PARTNER_SOP,
+	};
+
+	/* Step 1: EnterMode */
+	host_cmd_typec_control_vdm_req(TEST_PORT, req);
+	k_sleep(K_MSEC(100));
+
+	verify_expected_reply(req.partner_type,
+			      fixture->partner.enter_mode_vdos,
+			      fixture->partner.enter_mode_vdm);
+
+	/* Step 2: DP Status */
+	req.vdm_data[0] =
+		VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_STATUS | VDO_OPOS(opos)) |
+		VDO_SVDM_VERS(VDM_VER20);
+	req.vdm_data[1] = VDO_DP_STATUS(0, /* HPD IRQ  ... not applicable */
+					0, /* HPD level ... not applicable */
+					0, /* exit DP? ... no */
+					0, /* usb mode? ... no */
+					0, /* multi-function ... no */
+					0, /* currently enabled ... no */
+					0, /* power low? ... no */
+					1 /* DP source connected */);
+	req.vdm_data_objects = 2;
+	req.partner_type = TYPEC_PARTNER_SOP;
+
+	host_cmd_typec_control_vdm_req(TEST_PORT, req);
+	k_sleep(K_MSEC(100));
+
+	verify_expected_reply(req.partner_type, fixture->partner.dp_status_vdos,
+			      fixture->partner.dp_status_vdm);
+	/* Wait for it... */
+	zassert_equal(gpio_emul_output_get(gpio->port, gpio->pin), 0);
+
+	/* Step 3: DP Configure */
+	req.vdm_data[0] =
+		VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_CONFIG | VDO_OPOS(opos)) |
+		VDO_SVDM_VERS(VDM_VER20);
+	req.vdm_data[1] = VDO_DP_CFG(MODE_DP_PIN_D, /* pin mode */
+				     1, /* DPv1.3 signaling */
+				     2); /* Set that partner should be DP sink
+					  */
+	req.vdm_data_objects = 2;
+	req.partner_type = TYPEC_PARTNER_SOP;
+
+	host_cmd_typec_control_vdm_req(TEST_PORT, req);
+	k_sleep(K_MSEC(100));
+
+	verify_expected_reply(req.partner_type, fixture->partner.dp_config_vdos,
+			      fixture->partner.dp_config_vdm);
+	/* Now! */
+	zassert_equal(gpio_emul_output_get(gpio->port, gpio->pin), 1);
+}
+
+ZTEST_F(ap_vdm_control, test_vdm_hpd_disconnect_clear)
+{
+	uint32_t vdm_attention_data[2];
+	int opos = 1;
+	const struct gpio_dt_spec *gpio =
+		GPIO_DT_FROM_NODELABEL(gpio_usb_c0_hpd);
+
+	run_verify_dp_entry(fixture, opos);
+
+	/* Test that we see our Attention message */
+	vdm_attention_data[0] =
+		VDO(USB_SID_DISPLAYPORT, 1,
+		    VDO_OPOS(opos) | VDO_CMDT(CMDT_INIT) | CMD_ATTENTION) |
+		VDO_SVDM_VERS(VDM_VER20);
+	vdm_attention_data[1] = VDO_DP_STATUS(1, /* IRQ_HPD */
+					      true, /* HPD_HI|LOW - Changed*/
+					      0, /* request exit DP */
+					      0, /* request exit USB */
+					      0, /* MF pref */
+					      true, /* DP Enabled */
+					      0, /* power low e.g. normal */
+					      0x2 /* Connected as Sink */);
+	tcpci_partner_send_data_msg(&fixture->partner, PD_DATA_VENDOR_DEF,
+				    vdm_attention_data, 2, 0);
+
+	k_sleep(K_MSEC(100));
+	/*
+	 * Verify the HPD GPIO is set now
+	 */
+	zassert_equal(gpio_emul_output_get(gpio->port, gpio->pin), 1);
+
+	/* And disconnect */
+	disconnect_source_from_port(fixture->tcpci_emul, fixture->charger_emul);
+	zassert_equal(gpio_emul_output_get(gpio->port, gpio->pin), 0);
+}
+
+ZTEST_F(ap_vdm_control, test_vdm_wake_on_dock)
+{
+	uint32_t vdm_attention_data[2];
+	int opos = 1;
+	const struct gpio_dt_spec *gpio =
+		GPIO_DT_FROM_NODELABEL(gpio_usb_c0_hpd);
+
+	/* HPD GPIO should be low before the test */
+	zassert_equal(gpio_emul_output_get(gpio->port, gpio->pin), 0);
+
+	run_verify_dp_entry(fixture, opos);
+
+	/* Now put the AP to "sleep" */
+	test_set_chipset_to_power_level(POWER_S3);
+
+	/* Drain the MKBP event queue first */
+	struct host_cmd_handler_args args;
+	struct ec_response_get_next_event event;
+
+	args.version = 0;
+	args.command = EC_CMD_GET_NEXT_EVENT;
+	args.params = NULL;
+	args.params_size = 0;
+	args.response = &event;
+	args.response_max = sizeof(event);
+	args.response_size = 0;
+
+	while (host_command_process(&args) == EC_RES_SUCCESS) {
+	}
+
+	/* Test that we see our Attention message cause an event */
+	vdm_attention_data[0] =
+		VDO(USB_SID_DISPLAYPORT, 1,
+		    VDO_OPOS(opos) | VDO_CMDT(CMDT_INIT) | CMD_ATTENTION) |
+		VDO_SVDM_VERS(VDM_VER20);
+	vdm_attention_data[1] = VDO_DP_STATUS(1, /* IRQ_HPD */
+					      true, /* HPD_HI|LOW - Changed*/
+					      0, /* request exit DP */
+					      0, /* request exit USB */
+					      0, /* MF pref */
+					      true, /* DP Enabled */
+					      0, /* power low e.g. normal */
+					      0x2 /* Connected as Sink */);
+	tcpci_partner_send_data_msg(&fixture->partner, PD_DATA_VENDOR_DEF,
+				    vdm_attention_data, 2, 0);
+
+	k_sleep(K_MSEC(100));
+
+	/* Look for our MKBP event */
+	zassert_equal(host_command_process(&args), EC_RES_SUCCESS);
+	zassert_equal(event.event_type, EC_MKBP_EVENT_DP_ALT_MODE_ENTERED);
+}
diff --git a/zephyr/test/drivers/ap_vdm_control/src/ap_vdm_control_disabled.c b/zephyr/test/drivers/ap_vdm_control/src/ap_vdm_control_disabled.c
new file mode 100644
index 0000000000..a101373046
--- /dev/null
+++ b/zephyr/test/drivers/ap_vdm_control/src/ap_vdm_control_disabled.c
@@ -0,0 +1,53 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "usb_pd_ap_vdm_control.h"
+
+#include <stdint.h>
+
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+#define TEST_PORT USBC_PORT_C0
+
+ZTEST_SUITE(ap_vdm_control_disabled, drivers_predicate_post_main, NULL, NULL,
+	    NULL, NULL);
+
+ZTEST(ap_vdm_control_disabled, test_feature_absent)
+{
+	struct ec_response_get_features feat = host_cmd_get_features();
+
+	zassert_false(feat.flags[1] &
+		      EC_FEATURE_MASK_1(EC_FEATURE_TYPEC_AP_VDM_SEND));
+}
+
+ZTEST(ap_vdm_control_disabled, test_send_vdm_req_fails)
+{
+	struct ec_params_typec_control params = {
+		.port = TEST_PORT,
+		.command = TYPEC_CONTROL_COMMAND_SEND_VDM_REQ,
+		.vdm_req_params = {
+			.vdm_data = { 0 },
+			.vdm_data_objects = 1,
+			.partner_type = TYPEC_PARTNER_SOP,
+		},
+	};
+
+	zassert_equal(ec_cmd_typec_control(NULL, &params),
+		      EC_RES_INVALID_PARAM);
+}
+
+ZTEST(ap_vdm_control_disabled, test_vdm_response_fails)
+{
+	struct ec_response_typec_vdm_response vdm_resp;
+	struct ec_params_typec_vdm_response params = { .port = TEST_PORT };
+
+	zassert_equal(ec_cmd_typec_vdm_response(NULL, &params, &vdm_resp),
+		      EC_RES_INVALID_COMMAND);
+}
diff --git a/zephyr/test/drivers/bc12_pi3usb9201/CMakeLists.txt b/zephyr/test/drivers/bc12_pi3usb9201/CMakeLists.txt
new file mode 100644
index 0000000000..2f1925b635
--- /dev/null
+++ b/zephyr/test/drivers/bc12_pi3usb9201/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright 2022 The ChromiumOS Authors
+#Use of this source code is governed by a BSD-style license that can be
+#found in the LICENSE file.
+
+target_sources(app PRIVATE src/pi3usb9201.c)
+target_sources(app PRIVATE src/pi3usb9201_interrupt.c)
diff --git a/zephyr/test/drivers/bc12_pi3usb9201/src/pi3usb9201.c b/zephyr/test/drivers/bc12_pi3usb9201/src/pi3usb9201.c
new file mode 100644
index 0000000000..a4ca811ce2
--- /dev/null
+++ b/zephyr/test/drivers/bc12_pi3usb9201/src/pi3usb9201.c
@@ -0,0 +1,279 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "emul/emul_pi3usb9201.h"
+#include "extpower.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "timer.h"
+#include "usb_charge.h"
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/ztest.h>
+LOG_MODULE_REGISTER(test_drivers_bc12, LOG_LEVEL_DBG);
+
+#define EMUL_NODE DT_NODELABEL(pi3usb9201_emul0)
+
+/* Control_1 register bit definitions */
+#define PI3USB9201_REG_CTRL_1_INT_MASK BIT(0)
+#define PI3USB9201_REG_CTRL_1_MODE_SHIFT 1
+#define PI3USB9201_REG_CTRL_1_MODE_MASK \
+	(0x7 << PI3USB9201_REG_CTRL_1_MODE_SHIFT)
+
+/* Control_2 register bit definitions */
+#define PI3USB9201_REG_CTRL_2_AUTO_SW BIT(1)
+#define PI3USB9201_REG_CTRL_2_START_DET BIT(3)
+
+/* Host status register bit definitions */
+#define PI3USB9201_REG_HOST_STS_BC12_DET BIT(0)
+#define PI3USB9201_REG_HOST_STS_DEV_PLUG BIT(1)
+#define PI3USB9201_REG_HOST_STS_DEV_UNPLUG BIT(2)
+
+enum pi3usb9201_mode {
+	PI3USB9201_POWER_DOWN,
+	PI3USB9201_SDP_HOST_MODE,
+	PI3USB9201_DCP_HOST_MODE,
+	PI3USB9201_CDP_HOST_MODE,
+	PI3USB9201_CLIENT_MODE,
+	PI3USB9201_RESERVED_1,
+	PI3USB9201_RESERVED_2,
+	PI3USB9201_USB_PATH_ON,
+};
+
+enum pi3usb9201_client_sts {
+	CHG_OTHER = 0,
+	CHG_2_4A,
+	CHG_2_0A,
+	CHG_1_0A,
+	CHG_RESERVED,
+	CHG_CDP,
+	CHG_SDP,
+	CHG_DCP,
+};
+
+struct bc12_status {
+	enum charge_supplier supplier;
+	int current_limit;
+};
+
+static const struct bc12_status bc12_chg_limits[] = {
+	[CHG_OTHER] = { .supplier = CHARGE_SUPPLIER_OTHER,
+			.current_limit = 500 },
+	[CHG_2_4A] = { .supplier = CHARGE_SUPPLIER_PROPRIETARY,
+		       .current_limit = USB_CHARGER_MAX_CURR_MA },
+	[CHG_2_0A] = { .supplier = CHARGE_SUPPLIER_PROPRIETARY,
+		       .current_limit = USB_CHARGER_MAX_CURR_MA },
+	[CHG_1_0A] = { .supplier = CHARGE_SUPPLIER_PROPRIETARY,
+		       .current_limit = 1000 },
+	[CHG_RESERVED] = { .supplier = CHARGE_SUPPLIER_NONE,
+			   /* Not charging, limit is set to default */
+			   .current_limit =
+				   CONFIG_PLATFORM_EC_CHARGER_DEFAULT_CURRENT_LIMIT },
+	[CHG_CDP] = { .supplier = CHARGE_SUPPLIER_BC12_CDP,
+		      .current_limit = USB_CHARGER_MAX_CURR_MA },
+	[CHG_SDP] = { .supplier = CHARGE_SUPPLIER_BC12_SDP,
+		      .current_limit = 500 },
+#if defined(CONFIG_CHARGE_RAMP_SW) || defined(CONFIG_CHARGE_RAMP_HW)
+	[CHG_DCP] = { .supplier = CHARGE_SUPPLIER_BC12_DCP,
+		      .current_limit = USB_CHARGER_MAX_CURR_MA },
+#else
+	[CHG_DCP] = { .supplier = CHARGE_SUPPLIER_BC12_DCP,
+		      .current_limit = 500 },
+#endif
+};
+
+#define GPIO_BATT_PRES_ODL_PATH NAMED_GPIOS_GPIO_NODE(ec_batt_pres_odl)
+#define GPIO_BATT_PRES_ODL_PORT DT_GPIO_PIN(GPIO_BATT_PRES_ODL_PATH, gpios)
+
+static void test_bc12_pi3usb9201_host_mode(void)
+{
+	const struct emul *emul = EMUL_DT_GET(EMUL_NODE);
+	uint8_t a, b;
+
+	/*
+	 * Pretend that the USB-C Port Manager (TCPMv2) has set the port data
+	 * role to DFP.
+	 */
+	usb_charger_task_set_event(0, USB_CHG_EVENT_DR_DFP);
+	msleep(1);
+	/*
+	 * Expect the pi3usb9201 driver to configure CDP host mode and unmask
+	 * interrupts.
+	 */
+	pi3usb9201_emul_get_reg(emul, PI3USB9201_REG_CTRL_1, &a);
+	b = PI3USB9201_CDP_HOST_MODE << PI3USB9201_REG_CTRL_1_MODE_SHIFT;
+	zassert_equal(a, b);
+
+	/* Pretend that a device has been plugged in. */
+	msleep(500);
+	pi3usb9201_emul_set_reg(emul, PI3USB9201_REG_HOST_STS,
+				PI3USB9201_REG_HOST_STS_DEV_PLUG);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+	msleep(1);
+	/* Expect the pi3usb9201 driver to configure SDP host mode. */
+	pi3usb9201_emul_get_reg(emul, PI3USB9201_REG_CTRL_1, &a);
+	b = PI3USB9201_SDP_HOST_MODE << PI3USB9201_REG_CTRL_1_MODE_SHIFT;
+	zassert_equal(a, b);
+	pi3usb9201_emul_set_reg(emul, PI3USB9201_REG_HOST_STS, 0);
+
+	/* Pretend that a device has been unplugged. */
+	msleep(500);
+	pi3usb9201_emul_set_reg(emul, PI3USB9201_REG_HOST_STS,
+				PI3USB9201_REG_HOST_STS_DEV_UNPLUG);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+	msleep(1);
+	/* Expect the pi3usb9201 driver to configure CDP host mode. */
+	pi3usb9201_emul_get_reg(emul, PI3USB9201_REG_CTRL_1, &a);
+	b = PI3USB9201_CDP_HOST_MODE << PI3USB9201_REG_CTRL_1_MODE_SHIFT;
+	zassert_equal(a, b);
+	pi3usb9201_emul_set_reg(emul, PI3USB9201_REG_HOST_STS, 0);
+}
+
+static void
+test_bc12_pi3usb9201_client_mode(enum pi3usb9201_client_sts detect_result,
+				 enum charge_supplier supplier,
+				 int current_limit)
+{
+	const struct emul *emul = EMUL_DT_GET(EMUL_NODE);
+	uint8_t a, b;
+	int port, voltage;
+
+	/*
+	 * Pretend that the USB-C Port Manager (TCPMv2) has set the port data
+	 * role to UFP and decided charging from the port is allowed.
+	 */
+	msleep(500);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_DR_UFP);
+	charge_manager_update_dualrole(USBC_PORT_C0, CAP_DEDICATED);
+	msleep(1);
+	/*
+	 * Expect the pi3usb9201 driver to configure client mode and start
+	 * detection.
+	 */
+	pi3usb9201_emul_get_reg(emul, PI3USB9201_REG_CTRL_1, &a);
+	b = PI3USB9201_CLIENT_MODE << PI3USB9201_REG_CTRL_1_MODE_SHIFT;
+	zassert_equal(a, b);
+	pi3usb9201_emul_get_reg(emul, PI3USB9201_REG_CTRL_2, &a);
+	b = PI3USB9201_REG_CTRL_2_START_DET;
+	zassert_equal(a, b);
+
+	/* Pretend that detection completed. */
+	msleep(500);
+	pi3usb9201_emul_set_reg(emul, PI3USB9201_REG_CLIENT_STS,
+				1 << detect_result);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+	msleep(1);
+	/* Expect the pi3usb9201 driver to clear the start bit. */
+	pi3usb9201_emul_get_reg(emul, PI3USB9201_REG_CTRL_2, &a);
+	zassert_equal(a, 0);
+	pi3usb9201_emul_set_reg(emul, PI3USB9201_REG_CLIENT_STS, 0);
+	/*
+	 * Expect the charge manager to select the detected BC1.2 supplier.
+	 */
+	port = CHARGE_PORT_NONE;
+	voltage = 0;
+	if (supplier != CHARGE_SUPPLIER_NONE) {
+		port = USBC_PORT_C0;
+		voltage = USB_CHARGER_VOLTAGE_MV;
+	}
+	/* Wait for the charge port to update. */
+	msleep(500);
+	zassert_equal(charge_manager_get_active_charge_port(), port);
+	zassert_equal(charge_manager_get_supplier(), supplier);
+	zassert_equal(charge_manager_get_charger_current(), current_limit,
+		      NULL);
+	zassert_equal(charge_manager_get_charger_voltage(), voltage);
+
+	/*
+	 * Pretend that the USB-C Port Manager (TCPMv2) has set the port data
+	 * role to disconnected.
+	 */
+	msleep(500);
+	usb_charger_task_set_event(0, USB_CHG_EVENT_CC_OPEN);
+	msleep(1);
+	/*
+	 * Expect the pi3usb9201 driver to configure power down mode and mask
+	 * interrupts.
+	 */
+	pi3usb9201_emul_get_reg(emul, PI3USB9201_REG_CTRL_1, &a);
+	b = PI3USB9201_POWER_DOWN << PI3USB9201_REG_CTRL_1_MODE_SHIFT;
+	b |= PI3USB9201_REG_CTRL_1_INT_MASK;
+	zassert_equal(a, b);
+	/* Expect the charge manager to have no active supplier. */
+	zassert_equal(charge_manager_get_active_charge_port(), CHARGE_PORT_NONE,
+		      NULL);
+	zassert_equal(charge_manager_get_supplier(), CHARGE_SUPPLIER_NONE,
+		      NULL);
+	zassert_equal(charge_manager_get_charger_current(),
+		      CONFIG_PLATFORM_EC_CHARGER_DEFAULT_CURRENT_LIMIT);
+	zassert_equal(charge_manager_get_charger_voltage(), 0);
+}
+
+/*
+ * PI3USB9201 is a dual-role BC1.2 charger detector/advertiser used on USB
+ * ports. It can be programmed to operate in host mode or client mode through
+ * I2C. When operating as a host, PI3USB9201 enables BC1.2 SDP/CDP/DCP
+ * advertisement to the attached USB devices via the D+/- connection. When
+ * operating as a client, PI3USB9201 starts BC1.2 detection to detect the
+ * attached host type. In both host mode and client mode, the detection results
+ * are reported through I2C to the controller.
+ */
+ZTEST_USER(bc12, test_bc12_pi3usb9201)
+{
+	const struct device *batt_pres_dev =
+		DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_BATT_PRES_ODL_PATH, gpios));
+	const struct emul *emul = EMUL_DT_GET(EMUL_NODE);
+	uint8_t a, b;
+
+	/* Pretend we have battery and AC so charging works normally. */
+	zassert_ok(gpio_emul_input_set(batt_pres_dev, GPIO_BATT_PRES_ODL_PORT,
+				       0),
+		   NULL);
+	zassert_equal(BP_YES, battery_is_present());
+	set_ac_enabled(true);
+
+	/* Wait long enough for TCPMv2 to be idle. */
+	msleep(2000);
+
+	/*
+	 * Pretend that the USB-C Port Manager (TCPMv2) has set the port data
+	 * role to disconnected.
+	 */
+	usb_charger_task_set_event(0, USB_CHG_EVENT_CC_OPEN);
+	usb_charger_task_set_event(1, USB_CHG_EVENT_CC_OPEN);
+	msleep(1);
+	/*
+	 * Expect the pi3usb9201 driver to configure power down mode and mask
+	 * interrupts.
+	 */
+	pi3usb9201_emul_get_reg(emul, PI3USB9201_REG_CTRL_1, &a);
+	b = PI3USB9201_POWER_DOWN << PI3USB9201_REG_CTRL_1_MODE_SHIFT;
+	b |= PI3USB9201_REG_CTRL_1_INT_MASK;
+	zassert_equal(a, b);
+
+	test_bc12_pi3usb9201_host_mode();
+
+	for (int c = CHG_OTHER; c <= CHG_DCP; c++) {
+		LOG_INF("Test client mode supplier %d", c);
+		test_bc12_pi3usb9201_client_mode(
+			c, bc12_chg_limits[c].supplier,
+			bc12_chg_limits[c].current_limit);
+	}
+}
+
+/*
+ * TODO(b/216660795): Cleanup state using a teardown_fn
+ */
+static void bc12_after(void *unused)
+{
+	set_ac_enabled(false);
+}
+
+ZTEST_SUITE(bc12, drivers_predicate_post_main, NULL, NULL, bc12_after, NULL);
diff --git a/zephyr/test/drivers/bc12_pi3usb9201/src/pi3usb9201_interrupt.c b/zephyr/test/drivers/bc12_pi3usb9201/src/pi3usb9201_interrupt.c
new file mode 100644
index 0000000000..4df0112d21
--- /dev/null
+++ b/zephyr/test/drivers/bc12_pi3usb9201/src/pi3usb9201_interrupt.c
@@ -0,0 +1,119 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "gpio_signal.h"
+#include "task.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "usb_charge.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/fff.h>
+#include <zephyr/ztest.h>
+
+/* Get reference to externally linked handlers (defined in DTS) */
+#define USBC0_GPIO_PATH NAMED_GPIOS_GPIO_NODE(usb_c0_bc12_int_l)
+#define USBC0_GPIO_DEV DEVICE_DT_GET(DT_GPIO_CTLR(USBC0_GPIO_PATH, gpios))
+#define USBC0_GPIO_PORT DT_GPIO_PIN(USBC0_GPIO_PATH, gpios)
+
+#define USBC1_GPIO_PATH NAMED_GPIOS_GPIO_NODE(usb_c1_bc12_int_l)
+#define USBC1_GPIO_DEV DEVICE_DT_GET(DT_GPIO_CTLR(USBC1_GPIO_PATH, gpios))
+#define USBC1_GPIO_PORT DT_GPIO_PIN(USBC1_GPIO_PATH, gpios)
+
+static void toggle_gpio(const struct device *dev, gpio_pin_t pin)
+{
+	static const int values[] = { 1, 0, 1 };
+
+	for (int i = 0; i < ARRAY_SIZE(values); ++i) {
+		gpio_emul_input_set(dev, pin, values[i]);
+	}
+}
+
+FAKE_VOID_FUNC(usb_charger_task_event, int, uint32_t);
+
+struct pi3usb9201_fixture {
+	const struct bc12_drv *drv[2];
+	struct bc12_drv mock_drv;
+};
+
+static void *setup(void)
+{
+	static struct pi3usb9201_fixture fixture;
+
+	fixture.mock_drv.usb_charger_task_event = usb_charger_task_event;
+
+	return &fixture;
+}
+
+static void before(void *f)
+{
+	struct pi3usb9201_fixture *fixture = f;
+
+	fixture->drv[0] = bc12_ports[0].drv;
+	fixture->drv[1] = bc12_ports[1].drv;
+
+	RESET_FAKE(usb_charger_task_event);
+	test_set_chipset_to_s0();
+}
+
+static void after(void *f)
+{
+	struct pi3usb9201_fixture *fixture = f;
+
+	bc12_ports[0].drv = fixture->drv[0];
+	bc12_ports[1].drv = fixture->drv[1];
+}
+
+ZTEST_SUITE(pi3usb9201, drivers_predicate_post_main, setup, before, after,
+	    NULL);
+
+ZTEST_F(pi3usb9201, test_usb0_evt)
+{
+	/* Set up the driver to use the mock */
+	bc12_ports[0].drv = &fixture->mock_drv;
+
+	/* Trigger the event and verify that port0 was added to the task event
+	 * bitmap
+	 */
+	toggle_gpio(USBC0_GPIO_DEV, USBC0_GPIO_PORT);
+	zassert_true(*task_get_event_bitmap(TASK_ID_USB_CHG) & BIT(0));
+
+	/* Give the task a bit of time to process the events */
+	task_wake(TASK_ID_USB_CHG);
+	k_msleep(500);
+
+	/* Ensure that the callback was made (it should be the first, but others
+	 * may exist).
+	 */
+	zassert_true(usb_charger_task_event_fake.call_count > 0);
+	zassert_equal(0, usb_charger_task_event_fake.arg0_history[0]);
+	zassert_equal(USB_CHG_EVENT_BC12,
+		      usb_charger_task_event_fake.arg1_history[0]);
+}
+
+ZTEST_F(pi3usb9201, test_usb1_evt)
+{
+	/* Set up the driver to use the mock */
+	bc12_ports[1].drv = &fixture->mock_drv;
+
+	/* Trigger the event and verify that port1 was added to the task event
+	 * bitmap
+	 */
+	toggle_gpio(USBC1_GPIO_DEV, USBC1_GPIO_PORT);
+	zassert_true(*task_get_event_bitmap(TASK_ID_USB_CHG) & BIT(1));
+
+	/* Give the task a bit of time to process the events */
+	task_wake(TASK_ID_USB_CHG);
+	k_msleep(500);
+
+	/* Ensure that the callback was made (it should be the first, but others
+	 * may exist).
+	 */
+	zassert_true(usb_charger_task_event_fake.call_count > 0);
+	zassert_equal(1, usb_charger_task_event_fake.arg0_history[0]);
+	zassert_equal(USB_CHG_EVENT_BC12,
+		      usb_charger_task_event_fake.arg1_history[0]);
+}
diff --git a/zephyr/test/drivers/boards/native_posix.overlay b/zephyr/test/drivers/boards/native_posix.overlay
new file mode 100644
index 0000000000..40b78725ba
--- /dev/null
+++ b/zephyr/test/drivers/boards/native_posix.overlay
@@ -0,0 +1,1229 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <board-overlays/native_posix.dts>
+#include <cros/binman.dtsi>
+#include <cros/thermistor/thermistor.dtsi>
+#include <dt-bindings/gpio_defines.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/wake_mask_event_defines.h>
+#include <freq.h>
+
+/ {
+	chosen {
+		cros-ec,espi = &espi0;
+		cros-ec,watchdog = &wdt_counter;
+		cros-ec,raw-kb = &cros_kb_raw;
+		cros-ec,flash = &flash0;
+		cros-ec,flash-controller = &cros_flash;
+		cros,rtc = &cros_rtc;
+		zephyr,shell-uart = &test_uart;
+	};
+
+	aliases {
+		bma4xx-int = &ms_bma4xx;
+		bmi260-int = &ms_bmi260_accel;
+		bmi160-int = &ms_bmi160_accel;
+		tcs3400-int = &tcs3400_clear;
+		gpio-wp = &gpio_wp_l;
+		gpio-cbi-wp = &gpio_ec_cbi_wp;
+		gpio-kbd-kso2 = &gpio_ec_kso_02_inv;
+		int-wp = &int_wp_l;
+		/*
+		 * Use LIS2DW12 accelerometer for on-body sensor.
+		 * The base_accel is currently using bma255. However, that
+		 * sensor driver (accel_bma2x2.c) does not support body
+		 * detection, since it's missing get_rms_noise().
+		 */
+		on-body-sensor = &ms_lis2dw12_accel;
+	};
+
+	ec-console {
+		compatible = "ec-console";
+		disabled = "events", "lpc", "hostcmd";
+	};
+
+	ec-mkbp-host-event-wakeup-mask {
+		compatible = "cros-ec,mkbp-host-event-wakeup-mask";
+		wakeup-mask = <(
+			HOST_EVENT_LID_OPEN |
+			HOST_EVENT_POWER_BUTTON |
+			HOST_EVENT_AC_CONNECTED |
+			HOST_EVENT_AC_DISCONNECTED |
+			HOST_EVENT_HANG_DETECT |
+			HOST_EVENT_RTC |
+			HOST_EVENT_MODE_CHANGE |
+			HOST_EVENT_DEVICE |
+			HOST_EVENT_KEYBOARD_RECOVERY)>;
+	};
+
+	ec-mkbp-event-wakeup-mask {
+		compatible = "cros-ec,mkbp-event-wakeup-mask";
+		wakeup-mask = <(MKBP_EVENT_KEY_MATRIX | \
+				MKBP_EVENT_HOST_EVENT | \
+				MKBP_EVENT_SENSOR_FIFO)>;
+	};
+
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+			bc12 = <&pi3usb9201_emul0>;
+			chg = <&isl923x_emul>;
+			tcpc = <&tcpci_emul>;
+			ppc = <&sn5s330_emul>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&tcpci_mux_c0
+					     &virtual_mux_c0>;
+			};
+		};
+		port0-muxes {
+			tcpci_mux_c0: tcpci-mux-c0 {
+				compatible = "cros-ec,usbc-mux-tcpci";
+			};
+			virtual_mux_c0: virtual-mux-c0 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+
+		port1@1 {
+			compatible = "named-usbc-port";
+			reg = <1>;
+			bc12 = <&pi3usb9201_emul1>;
+			tcpc = <&ps8xxx_emul>;
+			ppc = <&syv682x_emul>;
+			usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_c1_bb_retimer_emul
+					     &virtual_mux_c1>;
+			};
+		};
+		port1-muxes {
+			virtual_mux_c1: virtual-mux-c1 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+	};
+
+	/*
+	 * Keep these GPIOs in pin order.
+	 * If you need to add one, make sure you increase
+	 * ngpios in the gpio0 node further down.
+	 */
+	named-gpios {
+		compatible = "named-gpios";
+
+		gpio_acok_od: acok_od {
+			gpios = <&gpio0 0 GPIO_INPUT>;
+			enum-name = "GPIO_AC_PRESENT";
+		};
+
+		/*
+		 * TODO(b/270601972):
+		 * Important note on testing emulated output GPIOs: Using
+		 * gpio_set_level() won't be observable from a gpio_get_level()
+		 * unless the output gpio is also configured as an input gpio.
+		 *
+		 * One may also configure the gpio as an input in the test
+		 * itself instead of device tree.
+		 */
+
+		/* In test WP is output because CBI use it, but it is also
+		 * input, because test_all_tags set it to enable write
+		 * protection.
+		 */
+		gpio_wp_l: wp_l {
+			gpios = <&gpio0 2 (GPIO_INPUT | GPIO_OUTPUT |
+					   GPIO_ACTIVE_LOW)>;
+		};
+		gpio_ec_kso_02_inv: ec_kso_02_inv {
+			gpios = <&gpio0 3 (GPIO_INPUT | GPIO_OUTPUT_LOW)>;
+		};
+		pg_ec_dsw_pwrok {
+			gpios = <&gpio0 4 GPIO_INPUT>;
+			enum-name = "GPIO_TEMP_SENSOR_POWER";
+		};
+		gpio_ec_pch_wake_odl: ec_pch_wake_odl {
+			gpios = <&gpio0 5 GPIO_OUTPUT_HIGH>;
+		};
+		/* Setup USB C1 pin as output to check their state in test */
+		usb_c1_ls_en: usb_c1_ls_en {
+			gpios = <&gpio0 6 (GPIO_INPUT_PULL_UP |
+					   GPIO_OUTPUT)>;
+		};
+		usb_c1_rt_rst_odl: usb_c1_rt_rst_odl {
+			gpios = <&gpio0 7 (GPIO_OUTPUT | GPIO_INPUT)>;
+		};
+		gpio_usb_c1_frs_en: usb_c1_frs_en {
+			gpios = <&gpio0 8 (GPIO_OUTPUT_LOW)>;
+		};
+		usb_c0_tcpc_int_odl: usb_c0_tcpc_int_odl {
+			gpios = <&gpio0 9 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		usb_c1_tcpc_int_odl: usb_c1_tcpc_int_odl {
+			gpios = <&gpio0 10 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		usb_c0_tcpc_rst_l: usb_c0_tcpc_rst_l {
+			gpios = <&gpio0 11 (GPIO_OUTPUT_HIGH | GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		usb_c1_tcpc_rst_l: usb_c1_tcpc_rst_l {
+			gpios = <&gpio0 12 (GPIO_OUTPUT_HIGH | GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_usb_c1_ppc_int: usb_c1_ppc_int {
+			gpios = <&gpio0 13 GPIO_INPUT>;
+		};
+		gpio_usb_c0_ppc_int: usb_c0_ppc_int {
+			gpios = <&gpio0 14 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_switchcap_pg_int_l: switchcap_pg_int_l {
+			gpios = <&gpio0 15 (GPIO_OUTPUT | GPIO_INPUT)>;
+		};
+		gpio_ap_rst_l: ap_rst_l {
+			gpios = <&gpio0 16 GPIO_INPUT>;
+			enum-name = "GPIO_AP_RST_L";
+		};
+		gpio_ps_hold: ps_hold {
+			gpios = <&gpio0 17 (GPIO_INPUT | GPIO_PULL_DOWN)>;
+			enum-name = "GPIO_PS_HOLD";
+		};
+		gpio_mb_power_good: mb_power_good {
+			gpios = <&gpio0 18 (GPIO_OUTPUT | GPIO_INPUT |
+				GPIO_PULL_DOWN)>;
+			enum-name = "GPIO_POWER_GOOD";
+		};
+		gpio_ap_suspend: ap_suspend {
+			gpios = <&gpio0 19 GPIO_INPUT>;
+			enum-name = "GPIO_AP_SUSPEND";
+		};
+		gpio_pmic_kpd_pwr_odl: pmic_kpd_pwr_odl {
+			gpios = <&gpio0 20 GPIO_OUTPUT_HIGH>;
+			enum-name = "GPIO_PMIC_KPD_PWR_ODL";
+		};
+		gpio_pmic_resin_l: pmic_resin_l {
+			gpios = <&gpio0 21 GPIO_OUTPUT_HIGH>;
+			enum-name = "GPIO_PMIC_RESIN_L";
+		};
+		gpio_warm_reset_l: warm_reset_l {
+			gpios = <&gpio0 22 GPIO_INPUT>;
+			enum-name = "GPIO_WARM_RESET_L";
+		};
+		gpio_lid_open_ec: lid_open_ec {
+			/* GPIO_PULL_UP will cause this start asserted. */
+			gpios = <&gpio0 23 (GPIO_INPUT | GPIO_PULL_UP)>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+		gpio_switchcap_on: switchcap_on {
+			gpios = <&gpio0 24 (GPIO_INPUT | GPIO_OUTPUT_LOW)>;
+		};
+		gpio_ec_pwr_btn_odl: ec_pwr_btn_odl {
+			/* GPIO_PULL_UP will cause this start asserted,
+			 * i.e. not pressed.
+			 */
+			gpios = <&gpio0 25 (GPIO_ACTIVE_LOW | GPIO_INPUT | GPIO_PULL_UP)>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		gpio_src_vph_pwr_pg: src_vph_pwr_pg {
+			gpios = <&gpio0 26 (GPIO_INPUT | GPIO_OUTPUT |
+				GPIO_PULL_DOWN)>;
+		};
+		gpio_test: test {
+			gpios = <&gpio0 27 (GPIO_INPUT | GPIO_OUTPUT)>;
+			enum-name = "GPIO_TEST";
+		};
+		ec_batt_pres_odl {
+			gpios = <&gpio0 28 GPIO_INPUT>;
+			enum-name = "GPIO_BATT_PRES_ODL";
+		};
+		gpio_no_init: no_init {
+			gpios = <&gpio0 29 (GPIO_ACTIVE_LOW | GPIO_INPUT)>;
+			no-auto-init;
+		};
+		gpio_ec_chg_led_y_c0: ec_chg_led_y_c0 {
+			gpios = <&gpio0 30 (GPIO_INPUT | GPIO_OUTPUT_LOW)>;
+		};
+		gpio_ec_chg_led_w_c0: ec_chg_led_w_c0 {
+			gpios = <&gpio0 31 (GPIO_INPUT | GPIO_OUTPUT_LOW)>;
+		};
+		/* gpio1 */
+		gpio_ec_chg_led_y_c1: ec_chg_led_y_c1 {
+			gpios = <&gpio1 0 (GPIO_INPUT | GPIO_OUTPUT_LOW)>;
+		};
+		gpio_ec_chg_led_w_c1: ec_chg_led_w_c1 {
+			gpios = <&gpio1 1 (GPIO_INPUT | GPIO_OUTPUT_LOW)>;
+		};
+		gpio_ap_ec_int_l: ap_ec_int_l {
+			gpios = <&gpio1 2 GPIO_OUTPUT_HIGH>;
+			enum-name = "GPIO_EC_INT_L";
+		};
+		gpio_ec_voldn_btn_odl: ec_voldn_btn_odl {
+			gpios = <&gpio1 3 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_DOWN_L";
+		};
+		gpio_ec_volup_btn_odl: ec_volup_btn_odl {
+			gpios = <&gpio1 4 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_UP_L";
+		};
+		gpio_en_pp5000_usba_r: en_pp5000_usba_r {
+			gpios = <&gpio1 5 (GPIO_INPUT | GPIO_OUTPUT_LOW)>;
+			enum-name = "GPIO_EN_PP5000_USBA_R";
+		};
+		gpio_ec_pg_pin_temp: ec_pg_pin_temp {
+			gpios = <&gpio1 6 GPIO_INPUT>;
+		};
+		gpio_sku_id0: sku_id0 {
+			gpios = <&gpio1 7 GPIO_INPUT>;
+		};
+		gpio_brd_id0: brd_id0 {
+			gpios = <&gpio1 8 GPIO_INPUT>;
+		};
+		gpio_ec_cbi_wp: ec_cbi_wp {
+			gpios = <&gpio1 9 GPIO_OUTPUT>;
+		};
+		gpio_usb_c0_bc12_int_l: usb_c0_bc12_int_l {
+			gpios = <&gpio1 10 GPIO_INPUT>;
+		};
+		gpio_usb_c1_bc12_int_l: usb_c1_bc12_int_l {
+			gpios = <&gpio1 11 GPIO_INPUT>;
+		};
+                gpio_usb_c0_hpd: usb_c0_hpd {
+                        gpios = <&gpio1 12 (GPIO_OUTPUT_LOW | GPIO_INPUT)>;
+                        enum-name = "GPIO_USB_C0_DP_HPD";
+                };
+                gpio_usb_c1_hpd: usb_c1_hpd {
+                        gpios = <&gpio1 13 (GPIO_OUTPUT_LOW | GPIO_INPUT)>;
+                        enum-name = "GPIO_USB_C1_DP_HPD";
+                };
+		usb_c1_usb_en: usb_c1_usb_en {
+			gpios = <&gpio1 14 GPIO_OUTPUT_LOW>;
+		};
+		usb_c1_dp_en: usb_c1_dp_en {
+			gpios = <&gpio1 15 GPIO_OUTPUT_LOW>;
+		};
+	};
+
+	gpio1: gpio@101 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0x101 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <16>;
+	};
+
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_ac_present: ac_present {
+			irq-pin = <&gpio_acok_od>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "extpower_interrupt";
+		};
+		int_usb_c0_ppc: usb_c0_ppc {
+			irq-pin = <&gpio_usb_c0_ppc_int>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "ppc_alert";
+		};
+		int_usb_c1_ppc: usb_c1_ppc {
+			irq-pin = <&gpio_usb_c1_ppc_int>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "ppc_alert";
+		};
+		int_switchcap_pg: switchcap_pg {
+			irq-pin = <&gpio_switchcap_pg_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "ln9310_interrupt";
+		};
+		int_gpio_test: test {
+			irq-pin = <&gpio_test>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "gpio_test_interrupt";
+		};
+		int_lid_open_ec: lid_open_ec {
+			irq-pin = <&gpio_lid_open_ec>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "lid_interrupt";
+		};
+		int_mb_power_good: mb_power_good {
+			irq-pin = <&gpio_mb_power_good>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_wp_l: wp_l {
+			irq-pin = <&gpio_wp_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "switch_interrupt";
+		};
+		int_usb_c0_bc12: usb_c0_bc12 {
+			irq-pin = <&gpio_usb_c0_bc12_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "usb0_evt";
+		};
+		int_usb_c1_bc12: usb_c1_bc12 {
+			irq-pin = <&gpio_usb_c1_bc12_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "usb1_evt";
+		};
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		named_i2c0: i2c0 {
+			i2c-port = <&i2c0>;
+			enum-names = "I2C_PORT_BATTERY",
+				"I2C_PORT_POWER",
+				"I2C_PORT_CHARGER",
+				"I2C_PORT_EEPROM",
+				"I2C_PORT_ACCEL",
+				"I2C_PORT_VIRTUAL_BATTERY";
+		};
+		named_i2c1: i2c1 {
+			i2c-port = <&i2c1>;
+			enum-names = "I2C_PORT_SENSOR";
+		};
+		named_i2c2: i2c2 {
+			i2c-port = <&i2c2>;
+			dynamic-speed;
+			enum-names = "I2C_PORT_USB_C0";
+		};
+		named_i2c3: i2c3 {
+			i2c-port = <&i2c3>;
+			dynamic-speed;
+			enum-names = "I2C_PORT_USB_C1";
+		};
+	};
+
+	batteries {
+		default_battery: lgc_ac17a8m {
+			compatible = "lgc,ac17a8m", "battery-smart";
+		};
+		ap16l5j {
+			compatible = "panasonic,ap16l5j", "battery-smart";
+			ship_mode_wb_support = <1>;
+			sleep_mode_support = <1>;
+			fet_mfgacc_support = <1>;
+		};
+		ap16l8j {
+			compatible = "lgc,ap16l8j", "battery-smart";
+			ship_mode_wb_support = <1>;
+			sleep_mode_support = <1>;
+			fet_cfet_mask = <0>;
+			fet_mfgacc_support = <1>;
+		};
+	};
+
+	cbi-ssfc {
+		compatible = "cros-ec,cbi-ssfc";
+		cbi_ssfc_base_sensor: base_sensor {
+			enum-name = "BASE_SENSOR";
+			size = <2>;
+			base_sensor_0: base0 {
+				compatible = "cros-ec,cbi-ssfc-value";
+				status = "okay";
+				value = <1>;
+				default;
+			};
+			base_sensor_1: base1 {
+				compatible = "cros-ec,cbi-ssfc-value";
+				status = "okay";
+				value = <2>;
+			};
+		};
+	};
+
+	cbi-fw-config {
+		compatible = "cros-ec,cbi-fw-config";
+		field-1 {
+			enum-name = "FW_CONFIG_FIELD_1";
+			start = <0>;
+			size = <2>;
+			val-0 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FIELD_1_A";
+				value = <0>;
+			};
+			val-1 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FIELD_1_B";
+				value = <1>;
+				default;
+			};
+		};
+		field-2 {
+			enum-name = "FW_CONFIG_FIELD_2";
+			start = <5>;
+			size = <1>;
+			val-1 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FIELD_2_X";
+				value = <1>;
+			};
+		};
+	};
+
+	adc0: adc {
+		compatible = "zephyr,adc-emul";
+		nchannels = <6>;
+		ref-internal-mv = <3300>;
+		#io-channel-cells = <1>;
+		status = "okay";
+	};
+
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		adc_charger: charger {
+			enum-name = "ADC_TEMP_SENSOR_CHARGER";
+			io-channels = <&adc0 0>;
+		};
+		adc_pp3300_regulator: pp3300-regulator {
+			enum-name = "ADC_TEMP_SENSOR_PP3300_REGULATOR";
+			io-channels = <&adc0 1>;
+		};
+		adc_ddr_soc: ddr-soc {
+			enum-name = "ADC_TEMP_SENSOR_DDR_SOC";
+			io-channels = <&adc0 2>;
+		};
+		adc_fan: fan {
+			enum-name = "ADC_TEMP_SENSOR_FAN";
+			io-channels = <&adc0 3>;
+		};
+		amon_bmon {
+			enum-name = "ADC_AMON_BMON";
+			io-channels = <&adc0 4>;
+			mul = <1000>;
+			div = <20>;
+		};
+		psys {
+			enum-name = "ADC_PSYS";
+			io-channels = <&adc0 5>;
+			mul = <124000>;
+		};
+	};
+
+	temp_charger: charger {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_13K7_47K_4050B>;
+		adc = <&adc_charger>;
+	};
+	temp_pp3300_regulator: pp3300-regulator {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_30K9_47K_4050B>;
+		adc = <&adc_pp3300_regulator>;
+	};
+	temp_ddr_soc: ddr-soc {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_ddr_soc>;
+	};
+	temp_fan: fan {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V0_22K6_47K_4050B>;
+		adc = <&adc_fan>;
+	};
+
+	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
+		named_temp_charger: charger {
+			status = "okay";
+			temp_fan_off = <40>;
+			temp_fan_max = <55>;
+			temp_host_high = <75>;
+			temp_host_halt = <80>;
+			temp_host_release_high = <65>;
+			power-good-pin = <&gpio_ec_pg_pin_temp>;
+			sensor = <&temp_charger>;
+		};
+		named_temp_pp3300_regulator: pp3300-regulator {
+			status = "okay";
+			temp_fan_off = <40>;
+			temp_fan_max = <55>;
+			temp_host_high = <75>;
+			temp_host_halt = <80>;
+			temp_host_release_high = <65>;
+			power-good-pin = <&gpio_ec_pg_pin_temp>;
+			sensor = <&temp_pp3300_regulator>;
+		};
+		named_temp_ddr_soc: ddr-soc {
+			status = "okay";
+			temp_fan_off = <35>;
+			temp_fan_max = <50>;
+			temp_host_high = <70>;
+			temp_host_halt = <80>;
+			temp_host_release_high = <65>;
+			power-good-pin = <&gpio_ec_pg_pin_temp>;
+			sensor = <&temp_ddr_soc>;
+		};
+		named_temp_fan: fan {
+			status = "okay";
+			temp_fan_off = <35>;
+			temp_fan_max = <50>;
+			temp_host_high = <70>;
+			temp_host_halt = <80>;
+			temp_host_release_high = <65>;
+			power-good-pin = <&gpio_ec_pg_pin_temp>;
+			sensor = <&temp_fan>;
+		};
+		named_pct2075: soc {
+			status = "okay";
+			power-good-pin = <&gpio_ec_pg_pin_temp>;
+			sensor = <&pct2075_emul>;
+		};
+	};
+
+	/*
+	 * Declare mutexes used by sensor drivers.
+	 * A mutex node is used to create an instance of mutex_t.
+	 * A mutex node is referenced by a sensor node if the
+	 * corresponding sensor driver needs to use the
+	 * instance of the mutex.
+	 */
+	motionsense-mutex {
+		compatible = "cros-ec,motionsense-mutex";
+		mutex_bma255: bma255-mutex {
+		};
+
+		mutex_bma4xx: bma4xx-mutex {
+		};
+
+		mutex_bmi260: bmi260-mutex {
+		};
+
+		mutex_bmi160: bmi160-mutex {
+		};
+
+		mutex_lis2dw12: lis2dw12-mutex {
+		};
+	};
+
+	/*
+	 * Driver specific data. A driver-specific data can be shared with
+	 * different motion sensors while they are using the same driver.
+	 */
+	motionsense-sensor-data {
+		bma255_data: bma255-drv-data {
+			compatible = "cros-ec,drvdata-bma255";
+			status = "okay";
+		};
+
+		bma4xx_data: bma4xx-drv-data {
+			compatible = "cros-ec,drvdata-bma4xx";
+			status = "okay";
+		};
+
+		bmi260_data: bmi260-drv-data {
+			compatible = "cros-ec,drvdata-bmi260";
+			status = "okay";
+		};
+
+		bmi160_data: bmi160-drv-data {
+			compatible = "cros-ec,drvdata-bmi160";
+			status = "okay";
+		};
+
+		lis2dw12_data: lis2dw12-drv-data {
+			compatible = "cros-ec,drvdata-lis2dw12";
+			status = "okay";
+		};
+
+		tcs_clear_data: tcs3400-clear-drv-data {
+			compatible = "cros-ec,drvdata-tcs3400-clear";
+			status = "okay";
+
+			als-drv-data {
+				compatible = "cros-ec,accelgyro-als-drv-data";
+				als-cal {
+					scale = <1>;
+					uscale = <0>;
+					offset = <0>;
+					als-channel-scale {
+					compatible =
+					"cros-ec,accelgyro-als-channel-scale";
+						k-channel-scale = <1>;
+						cover-scale = <1>;
+					};
+				};
+			};
+		};
+
+		tcs_rgb_data: tcs3400-rgb-drv-data {
+			compatible = "cros-ec,drvdata-tcs3400-rgb";
+			status = "okay";
+
+			/* node for rgb_calibration_t defined in accelgyro.h */
+			rgb_calibration {
+				compatible =
+					"cros-ec,accelgyro-rgb-calibration";
+
+				irt = <1>;
+
+				rgb-cal-x {
+					offset = <0>;
+					coeff = <0 1 0 0>;
+					als-channel-scale {
+					compatible =
+					"cros-ec,accelgyro-als-channel-scale";
+						k-channel-scale = <1>;
+						cover-scale = <1>;
+					};
+				};
+				rgb-cal-y {
+					offset = <0>;
+					coeff = <0 0 1 0>;
+					als-channel-scale {
+					compatible =
+					"cros-ec,accelgyro-als-channel-scale";
+						k-channel-scale = <1>;
+						cover-scale = <1>;
+					};
+				};
+				rgb-cal-z {
+					offset = <0>;
+					coeff = <0 0 0 1>;
+					als-channel-scale {
+					compatible =
+					"cros-ec,accelgyro-als-channel-scale";
+						k-channel-scale = <1>;
+						cover-scale = <1>;
+					};
+				};
+			};
+		};
+	};
+
+	/*
+	 * List of motion sensors that creates motion_sensors array.
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
+	 * motion sensor IDs for lid angle calculation.
+	 */
+	motionsense-sensor {
+		base_accel: ms_bma255: ms-bma255 {
+			compatible = "cros-ec,bma255";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3_S5";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&mutex_bma255>;
+			port = <&named_i2c0>;
+			default-range = <2>;
+			drv-data = <&bma255_data>;
+			i2c-spi-addr-flags = "BMA2x2_I2C_ADDR1_FLAGS";
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					/* Run ALS sensor in S0 */
+					odr = <1000>;
+				};
+				ec-s3 {
+					odr = <10000>;
+				};
+				ec-s5 {
+					odr = <10000>;
+				};
+			};
+		};
+		lid_accel: ms_bmi260_accel: ms-bmi260-accel {
+			compatible = "cros-ec,bmi260-accel";
+			status = "okay";
+
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&mutex_bmi260>;
+			port = <&named_i2c0>;
+			drv-data = <&bmi260_data>;
+			default-range = <4>;
+			i2c-spi-addr-flags = "BMI260_ADDR0_FLAGS";
+		};
+
+		ms_bmi260_gyro: ms-bmi260-gyro {
+			compatible = "cros-ec,bmi260-gyro";
+			status = "okay";
+
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&mutex_bmi260>;
+			port = <&named_i2c0>;
+			drv-data = <&bmi260_data>;
+			default-range = <1000>; /* dps */
+			i2c-spi-addr-flags = "BMI260_ADDR0_FLAGS";
+		};
+
+		ms_bmi160_accel: ms-bmi160-accel {
+			compatible = "cros-ec,bmi160-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3_S5";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&mutex_bmi160>;
+			port = <&named_i2c1>;
+			drv-data = <&bmi160_data>;
+			default-range = <4>;
+			i2c-spi-addr-flags = "BMI160_ADDR0_FLAGS";
+		};
+
+		ms_bmi160_gyro: ms-bmi160-gyro {
+			compatible = "cros-ec,bmi160-gyro";
+			status = "okay";
+
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&mutex_bmi160>;
+			port = <&named_i2c1>;
+			drv-data = <&bmi160_data>;
+			default-range = <1000>; /* dps */
+			i2c-spi-addr-flags = "BMI160_ADDR0_FLAGS";
+		};
+
+		ms_bma4xx: ms-bma4xx {
+			compatible = "cros-ec,bma4xx";
+			status = "okay";
+
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&mutex_bma4xx>;
+			port = <&named_i2c1>;
+			drv-data = <&bma4xx_data>;
+			default-range = <4>;
+			i2c-spi-addr-flags = "BMA4_I2C_ADDR_SECONDARY";
+		};
+
+		ms_lis2dw12_accel: ms-lis2dw12-accel {
+			compatible = "cros-ec,lis2dw12";
+			status = "okay";
+
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&mutex_lis2dw12>;
+			port = <&named_i2c0>;
+			drv-data = <&lis2dw12_data>;
+			default-range = <2>;
+			i2c-spi-addr-flags = "LIS2DWL_ADDR1_FLAGS";
+		};
+
+		tcs3400_clear: tcs3400-clear {
+			compatible = "cros-ec,tcs3400-clear";
+			status = "okay";
+
+			location = "MOTIONSENSE_LOC_BASE";
+			port = <&named_i2c1>;
+			default-range = <0x10000>;
+			drv-data = <&tcs_clear_data>;
+			i2c-spi-addr-flags = "TCS3400_I2C_ADDR_FLAGS";
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					/* Run ALS sensor in S0 */
+					odr = <1000>;
+				};
+			};
+		};
+
+		tcs3400_rgb: tcs3400-rgb {
+			compatible = "cros-ec,tcs3400-rgb";
+			status = "okay";
+
+			location = "MOTIONSENSE_LOC_BASE";
+			default-range = <0x10000>; /* scale = 1x, uscale = 0 */
+			drv-data = <&tcs_rgb_data>;
+		};
+	};
+
+	motionsense-sensor-info {
+		compatible = "cros-ec,motionsense-sensor-info";
+		accel-force-mode-sensors = <&ms_bma255 &ms_lis2dw12_accel>;
+	};
+
+	/*
+	 * Add extra i2c buses to test the I2C passthrough: 1 for sensor and
+	 * 2 dedicated for TCPC.
+	 */
+	i2c1: i2c@400 {
+		status = "okay";
+		compatible = "zephyr,i2c-emul-controller";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x400 4>;
+
+		tcs_emul: tcs@39 {
+			compatible = "zephyr,tcs3400-emul";
+			reg = <0x39>;
+			error-on-ro-write;
+			error-on-reserved-bit-write;
+			error-on-msb-first-access;
+		};
+
+		accel_bmi160: bmi160@68 {
+			compatible = "zephyr,bmi-emul";
+			reg = <0x68>;
+			device-model = "BMI_EMUL_160";
+			error-on-ro-write;
+			error-on-wo-read;
+			error-on-reserved-bit-write;
+			simulate-command-exec-time;
+		};
+
+		bma422_emul: bma4xx@19 {
+			compatible = "cros,bma4xx-emul";
+			status = "okay";
+			reg = <0x19>;
+			motionsense-sensor = <&ms_bma4xx>;
+		};
+	};
+
+	i2c2: i2c@500 {
+		status = "okay";
+		compatible = "zephyr,i2c-emul-controller";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x500 4>;
+
+		pi3usb9201_emul0: pi3usb9201@5f {
+			compatible = "pericom,pi3usb9201";
+			reg = <0x5f>;
+			irq = <&int_usb_c0_bc12>;
+		};
+
+		sn5s330_emul: sn5s330@40 {
+			compatible = "cros,sn5s330-emul";
+			reg = <0x40>;
+			int-pin = <&gpio_usb_c0_ppc_int>;
+		};
+
+		tcpci_emul: tcpci_emul@82 {
+			compatible = "cros,tcpci-generic-emul";
+			status = "okay";
+			reg = <0x82>;
+			irq-gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
+			rst-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	i2c3: i2c@600 {
+		status = "okay";
+		compatible = "zephyr,i2c-emul-controller";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x600 4>;
+
+		pi3usb9201_emul1: pi3usb9201@5d {
+			compatible = "pericom,pi3usb9201";
+			reg = <0x5d>;
+			irq = <&int_usb_c1_bc12>;
+		};
+
+		syv682x_emul: syv682x@41 {
+			compatible = "zephyr,syv682x-emul";
+			reg = <0x41>;
+			frs_en_gpio = <&gpio_usb_c1_frs_en>;
+			alert_gpio = <&gpio_usb_c1_ppc_int>;
+		};
+
+		usb_c1_bb_retimer_emul: bbretimer@42 {
+			compatible = "intel,jhl8040r";
+			reg = <0x42>;
+			reset-pin = <&usb_c1_rt_rst_odl>;
+			ls-en-pin = <&usb_c1_ls_en>;
+		};
+
+		anx7483_emul: anx7483_emul@3e {
+			compatible = "cros,anx7483-emul", "analogix,anx7483";
+			reg = <0x3e>;
+		};
+
+		ps8811_emul: ps8811_emul@72 {
+			compatible = "cros,ps8811-emul";
+			reg = <0x72>;
+		};
+
+		ps8xxx_emul: ps8xxx_emul@b {
+			compatible = "cros,ps8xxx-emul";
+			reg = <0xb>;
+			irq-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
+			rst-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
+			p0-i2c-addr = <0x8>;
+			p1-i2c-addr = <0x9>;
+			gpio-i2c-addr = <0x1a>;
+		};
+
+		pct2075_emul: pct2075@48 {
+			compatible = "nxp,pct2075";
+			reg = <0x48>;
+		};
+	};
+
+	clock: clock {
+		compatible = "cros,clock-control-emul";
+		clock-frequency = <DT_FREQ_M(100)>; /* 100 MHz */
+	};
+
+	wdt_counter: wdt-counter {
+		compatible = "zephyr,counter-watchdog";
+		status = "okay";
+		counter = <&counter0>;
+	};
+
+	cros_kb_raw: kb-raw-emul {
+		compatible = "cros-ec,kb-raw-emul";
+	};
+
+	cros_flash: cros-flash {
+		compatible = "cros-ec,flash-emul";
+	};
+
+	cros_rtc: cros-rtc {
+		compatible = "cros-ec,rtc-emul";
+	};
+
+	pwms {
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		pwm_blue_left: pwm@0 {
+			compatible = "cros,pwm-mock";
+			reg = <0 1>;
+			#pwm-cells = <3>;
+			status = "okay";
+		};
+		pwm_white_left: pwm@1 {
+			compatible = "cros,pwm-mock";
+			reg = <1 1>;
+			#pwm-cells = <3>;
+			status = "okay";
+		};
+		pwm_amber_right: pwm@2 {
+			compatible = "cros,pwm-mock";
+			reg = <2 1>;
+			#pwm-cells = <3>;
+			status = "okay";
+		};
+		pwm_white_right: pwm@3 {
+			compatible = "cros,pwm-mock";
+			reg = <3 1>;
+			#pwm-cells = <3>;
+			status = "okay";
+		};
+		pwm_kblight: pwm@4 {
+			compatible = "cros,pwm-mock";
+			reg = <4 1>;
+			#pwm-cells = <3>;
+			status = "okay";
+		};
+		pwm_displight: pwm@5 {
+			compatible = "cros,pwm-mock";
+			reg = <5 1>;
+			#pwm-cells = <3>;
+			status = "okay";
+		};
+	};
+
+	pwmleds {
+		compatible = "pwm-leds";
+
+		pwmled_blue_left: pwmled_b_left {
+			pwms = <&pwm_blue_left 0 1000000 PWM_POLARITY_NORMAL>;
+		};
+		pwmled_white_left: pwmled_w_left {
+			pwms = <&pwm_white_left 0 1000000 PWM_POLARITY_NORMAL>;
+		};
+		pwmled_amber_right: pwmled_y_right {
+			pwms = <&pwm_amber_right 0 1000000 PWM_POLARITY_NORMAL>;
+		};
+		pwmled_white_right: pwmled_w_right {
+			pwms = <&pwm_white_right 0 1000000 PWM_POLARITY_NORMAL>;
+		};
+	};
+
+	pwm-led-pins {
+		compatible = "cros-ec,pwm-led-pins";
+
+		left-led {
+			led-id = "EC_LED_ID_LEFT_LED";
+			led-pwms = <&pwmled_blue_left &pwmled_white_left>;
+
+			color-off {
+				led-color = "LED_OFF";
+				led-values = <0 0>;
+			};
+			color-blue {
+				led-color = "LED_BLUE";
+				br-color = "EC_LED_COLOR_BLUE";
+				led-values = <100 0>;
+			};
+			color-white {
+				led-color = "LED_WHITE";
+				br-color = "EC_LED_COLOR_WHITE";
+				led-values = <0 100>;
+			};
+		};
+
+		right-led {
+			led-id = "EC_LED_ID_RIGHT_LED";
+			led-pwms = <&pwmled_amber_right &pwmled_white_right>;
+
+			color-off {
+				led-color = "LED_OFF";
+				led-values = <0 0>;
+			};
+			color-amber {
+				led-color = "LED_AMBER";
+				br-color = "EC_LED_COLOR_AMBER";
+				led-values = <100 0>;
+			};
+			color-white {
+				led-color = "LED_WHITE";
+				br-color = "EC_LED_COLOR_WHITE";
+				led-values = <0 100>;
+			};
+		};
+	};
+
+	led-colors {
+		compatible = "cros-ec,led-policy";
+	};
+
+	kblight {
+		compatible = "cros-ec,kblight-pwm";
+		pwms = <&pwm_kblight 0 PWM_KHZ(10) PWM_POLARITY_NORMAL>;
+		generic-pwm-channel = <0>;
+	};
+
+	displight {
+		compatible = "cros-ec,displight";
+		pwms = <&pwm_kblight 0 PWM_KHZ(10) PWM_POLARITY_NORMAL>;
+		generic-pwm-channel = <1>;
+	};
+	test_uart: uart@55556666 {
+	   compatible = "vnd,serial";
+	   reg = <0x55556666 0x1000>;
+	   status = "okay";
+	   buffer-size = <200>;
+	};
+
+};
+
+&espi0 {
+	espi-host@0 {
+		status = "okay";
+		compatible = "zephyr,espi-emul-espi-host";
+		reg = <0x0>;
+	};
+};
+
+&gpio0 {
+	ngpios = <32>;
+};
+
+&i2c0 {
+	cbi_eeprom: eeprom@56 {
+		compatible = "atmel,at24";
+		reg = <0x56>;
+		size = <512>;
+		pagesize = <8>;
+		address-width = <8>;
+		timeout = <5>;
+	};
+
+	battery: sb@b {
+		compatible = "zephyr,smart-battery-emul";
+		reg = <0xb>;
+		cycle-count = <99>;
+		version = "BATTERY_SPEC_VER_1_1_WITH_PEC";
+		/* Real battery voltages are multiples of 4.4V. */
+		desired-charg-volt = <5000>;
+		desired-charg-cur = <1000>;
+		mf-name = "LGC";
+		dev-name = "AC17A8M";
+	};
+
+	battery2: sb@3a {
+		compatible = "zephyr,smart-battery-emul";
+		reg = <0x3a>;
+		cycle-count = <99>;
+		version = "BATTERY_SPEC_VER_1_1_WITH_PEC";
+		/* Real battery voltages are multiples of 4.4V. */
+		desired-charg-volt = <5000>;
+		desired-charg-cur = <1000>;
+		mf-name = "PANASONIC";
+		dev-name = "AP16L5J";
+	};
+
+	bma_emul: bma@18 {
+		compatible = "zephyr,bma255-emul";
+		reg = <0x18>;
+		error-on-compensation-not-ready;
+		error-on-ro-write;
+		error-on-reserved-bit-write;
+		error-on-msb-first-access;
+	};
+
+	accel_bmi260: bmi260@68 {
+		compatible = "zephyr,bmi-emul";
+		reg = <0x68>;
+		device-model = "BMI_EMUL_260";
+		error-on-ro-write;
+		error-on-wo-read;
+		error-on-reserved-bit-write;
+		simulate-command-exec-time;
+	};
+
+	ln9310: ln9310@72 {
+		compatible = "cros,ln9310-emul";
+		status = "okay";
+		reg = <0x72>;
+		pg-int-pin = <&gpio_switchcap_pg_int_l>;
+	};
+
+	lis2dw12_emul: lis2dw12@19 {
+		compatible = "cros,lis2dw12-emul";
+		status = "okay";
+		reg = <0x19>;
+	};
+
+	i2c_mock: i2c_mock@84 {
+		compatible = "cros,i2c-mock";
+		status = "okay";
+		reg = <0x84>;
+	};
+
+	isl923x_emul: isl923x@9 {
+		compatible = "cros,isl923x-emul";
+		status = "okay";
+		reg = <0x9>;
+		battery = <&battery>;
+	};
+
+
+};
+
+/* Enable all thermistors for testing */
+&thermistor_3V3_30K9_47K_4050B  {
+	status = "okay";
+};
+
+&thermistor_3V0_22K6_47K_4050B  {
+	status = "okay";
+};
+
+&thermistor_3V3_13K7_47K_4050B  {
+	status = "okay";
+};
+
+&thermistor_3V3_51K1_47K_4050B  {
+	status = "okay";
+};
+
+&flash0 {
+        erase-block-size = <0x1000>;
+        write-block-size = <1>;
+        reg = <0x00000000 DT_SIZE_K(512)>;
+};
diff --git a/zephyr/test/drivers/body_detection/CMakeLists.txt b/zephyr/test/drivers/body_detection/CMakeLists.txt
new file mode 100644
index 0000000000..7a2e343d37
--- /dev/null
+++ b/zephyr/test/drivers/body_detection/CMakeLists.txt
@@ -0,0 +1,5 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_sources(app PRIVATE src/body_detection.c)
diff --git a/zephyr/test/drivers/body_detection/src/body_detection.c b/zephyr/test/drivers/body_detection/src/body_detection.c
new file mode 100644
index 0000000000..f7e49251c9
--- /dev/null
+++ b/zephyr/test/drivers/body_detection/src/body_detection.c
@@ -0,0 +1,225 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "accelgyro.h"
+#include "body_detection.h"
+#include "console.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/fff.h>
+#include <zephyr/kernel.h>
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+FAKE_VALUE_FUNC(int, get_data_rate, struct motion_sensor_t *);
+FAKE_VALUE_FUNC(int, get_rms_noise, struct motion_sensor_t *);
+
+extern struct motion_sensor_t *body_sensor;
+extern uint64_t var_threshold_scaled, confidence_delta_scaled;
+
+/*
+ * In order to be independent from a motion sensor driver changes mock
+ * two functions that are used during body detection parameters initialization.
+ */
+const static struct accelgyro_drv mock_drv = {
+	.get_data_rate = get_data_rate,
+	.get_rms_noise = get_rms_noise,
+};
+const static struct accelgyro_drv *old_drv;
+
+static void body_detect_mode_before(void *state)
+{
+	ARG_UNUSED(state);
+	body_detect_reset();
+}
+
+static void body_detect_mode_after(void *state)
+{
+	ARG_UNUSED(state);
+	body_detect_reset();
+}
+
+/**
+ * @brief TestPurpose: various body_detect_change_state operations.
+ */
+ZTEST_USER(bodydetectmode, test_body_detect_set_state)
+{
+	enum body_detect_states body_detect_state;
+
+	body_detect_state = body_detect_get_state();
+	zassert_equal(body_detect_state, BODY_DETECTION_ON_BODY,
+		      "unexpected body detect initial mode: %d",
+		      body_detect_state);
+
+	body_detect_change_state(BODY_DETECTION_OFF_BODY, false);
+	body_detect_state = body_detect_get_state();
+	zassert_equal(body_detect_state, BODY_DETECTION_OFF_BODY,
+		      "unexpected body detect mode: %d", body_detect_state);
+
+	body_detect_change_state(BODY_DETECTION_ON_BODY, false);
+	body_detect_state = body_detect_get_state();
+	zassert_equal(body_detect_state, BODY_DETECTION_ON_BODY,
+		      "unexpected body detect mode: %d", body_detect_state);
+}
+
+/**
+ * @brief TestPurpose: ensure that console bodydetectmode forces the status,
+ * inhibiting body_detect_change_state, and then unforce it with reset.
+ */
+ZTEST_USER(bodydetectmode, test_setbodydetectionmode_forced)
+{
+	int ret;
+	enum body_detect_states body_detect_state;
+
+	body_detect_state = body_detect_get_state();
+	zassert_equal(body_detect_state, BODY_DETECTION_ON_BODY,
+		      "unexpected body detect initial mode: %d",
+		      body_detect_state);
+
+	/**
+	 * Set body detect mode to "off", since it defaults "on".
+	 */
+	ret = shell_execute_cmd(get_ec_shell(), "bodydetectmode off");
+	zassert_equal(ret, EC_SUCCESS, "unexpected command return status: %d",
+		      ret);
+	body_detect_state = body_detect_get_state();
+	zassert_equal(body_detect_state, BODY_DETECTION_OFF_BODY,
+		      "unexpected body detect mode: %d", body_detect_state);
+
+	/**
+	 * Set body detect mode to "on", to validate it can be enabled also.
+	 */
+	ret = shell_execute_cmd(get_ec_shell(), "bodydetectmode on");
+	zassert_equal(ret, EC_SUCCESS, "unexpected command return status: %d",
+		      ret);
+	body_detect_state = body_detect_get_state();
+	zassert_equal(body_detect_state, BODY_DETECTION_ON_BODY,
+		      "unexpected body detect mode: %d", body_detect_state);
+
+	/**
+	 * Reset body detect mode. This returns body detect to "on".
+	 */
+	ret = shell_execute_cmd(get_ec_shell(), "bodydetectmode reset");
+	zassert_equal(ret, EC_SUCCESS, "unexpected command return status: %d",
+		      ret);
+	body_detect_state = body_detect_get_state();
+	zassert_equal(body_detect_state, BODY_DETECTION_ON_BODY,
+		      "unexpected body detect mode: %d", body_detect_state);
+}
+
+/**
+ * @brief TestPurpose: check the "too many arguments" case.
+ */
+ZTEST_USER(bodydetectmode, test_setbodydetectionmode_too_many_args)
+{
+	int ret;
+
+	ret = shell_execute_cmd(get_ec_shell(),
+				"bodydetectmode too many arguments");
+	zassert_equal(ret, EC_ERROR_PARAM_COUNT,
+		      "unexpected command return status: %d", ret);
+}
+
+/**
+ * @brief TestPurpose: check the "unknown argument" case.
+ */
+ZTEST_USER(bodydetectmode, test_setbodydetectionmode_unknown_arg)
+{
+	int ret;
+
+	ret = shell_execute_cmd(get_ec_shell(), "bodydetectmode X");
+	zassert_equal(ret, EC_ERROR_PARAM1,
+		      "unexpected command return status: %d", ret);
+}
+
+ZTEST_SUITE(bodydetectmode, drivers_predicate_post_main, NULL,
+	    body_detect_mode_before, body_detect_mode_after, NULL);
+
+static void body_detect_init_before(void *state)
+{
+	ARG_UNUSED(state);
+
+	RESET_FAKE(get_data_rate);
+	RESET_FAKE(get_rms_noise);
+
+	/* ODR = 50 Hz */
+	get_data_rate_fake.return_val = 50 * 1000;
+	/* RMS noise of LIS2DW12 with ODR set to 50Hz */
+	get_rms_noise_fake.return_val = 636;
+
+	old_drv = body_sensor->drv;
+	body_sensor->drv = &mock_drv;
+	body_detect_reset();
+}
+
+static void body_detect_init_after(void *state)
+{
+	ARG_UNUSED(state);
+
+	body_sensor->drv = old_drv;
+	body_sensor->bd_params = NULL;
+	body_detect_reset();
+}
+
+#define DEFAULT_CONFIDENCE_DELTA 1467
+#define DEFAULT_VAR_THRESHOLD 1665
+
+/**
+ * @brief TestPurpose: check variance properties with default input parameters
+ */
+ZTEST_USER(bodydetectinit, test_defaultparams)
+{
+	/*
+	 * body_detect_reset was already called in body_detect_init_before.
+	 * No need to invoke it here.
+	 */
+	zassert_equal(confidence_delta_scaled, DEFAULT_CONFIDENCE_DELTA);
+	zassert_equal(var_threshold_scaled, DEFAULT_VAR_THRESHOLD);
+	zassert_equal(1, get_rms_noise_fake.call_count);
+	zassert_equal(1, get_data_rate_fake.call_count);
+}
+
+/**
+ * @brief TestPurpose: check variance properties with custom parameters
+ * If any parameter is set to zero it should be replaced with default
+ * value read from Kconfig.
+ */
+ZTEST_USER(bodydetectinit, test_customparams)
+{
+	struct body_detect_params params;
+
+	body_sensor->bd_params = &params;
+
+	memset(&params, 0, sizeof(params));
+
+	body_detect_reset();
+	zassert_equal(confidence_delta_scaled, DEFAULT_CONFIDENCE_DELTA);
+	zassert_equal(var_threshold_scaled, DEFAULT_VAR_THRESHOLD);
+	zassert_equal(2, get_rms_noise_fake.call_count);
+	zassert_equal(2, get_data_rate_fake.call_count);
+
+	params.confidence_delta = 2900;
+	params.var_threshold = 3000;
+
+	body_detect_reset();
+	zassert_equal(confidence_delta_scaled, 8105);
+	zassert_equal(var_threshold_scaled, 8513);
+	zassert_equal(3, get_rms_noise_fake.call_count);
+	zassert_equal(3, get_data_rate_fake.call_count);
+
+	params.confidence_delta = 2900;
+	params.var_threshold = 3000;
+	params.var_noise_factor = 150;
+
+	body_detect_reset();
+	zassert_equal(confidence_delta_scaled, 8105);
+	zassert_equal(var_threshold_scaled, 8547);
+	zassert_equal(4, get_rms_noise_fake.call_count);
+	zassert_equal(4, get_data_rate_fake.call_count);
+}
+
+ZTEST_SUITE(bodydetectinit, drivers_predicate_post_main, NULL,
+	    body_detect_init_before, body_detect_init_after, NULL);
diff --git a/zephyr/test/drivers/button/CMakeLists.txt b/zephyr/test/drivers/button/CMakeLists.txt
new file mode 100644
index 0000000000..0070d595b1
--- /dev/null
+++ b/zephyr/test/drivers/button/CMakeLists.txt
@@ -0,0 +1,5 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+zephyr_library_sources(src/main.c)
diff --git a/zephyr/test/drivers/button/src/main.c b/zephyr/test/drivers/button/src/main.c
new file mode 100644
index 0000000000..08874d8032
--- /dev/null
+++ b/zephyr/test/drivers/button/src/main.c
@@ -0,0 +1,349 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "button.h"
+#include "console.h"
+#include "hooks.h"
+#include "mkbp_fifo.h"
+#include "power.h"
+#include "test/drivers/test_state.h"
+#include "timer.h"
+
+#include <zephyr/fff.h>
+#include <zephyr/kernel.h>
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+/*
+ * TODO (b/b/253284635) Timeouts here don't quite align with the button press
+ *   duration. This is caused by an issue with the Zephyr scheduling for delayed
+ *   work that's causing us to need to sleep longer than "reasonable".
+ */
+
+FAKE_VOID_FUNC(chipset_reset, enum chipset_shutdown_reason);
+
+static char *button_debug_state_strings[] = {
+	"STATE_DEBUG_NONE", "STATE_DEBUG_CHECK",
+	"STATE_STAGING",    "STATE_DEBUG_MODE_ACTIVE",
+	"STATE_SYSRQ_PATH", "STATE_WARM_RESET_PATH",
+	"STATE_SYSRQ_EXEC", "STATE_WARM_RESET_EXEC",
+};
+
+#define ASSERT_DEBUG_STATE(expected)                                          \
+	do {                                                                  \
+		enum debug_state state = get_button_debug_state();            \
+		zassert_equal(expected, state,                                \
+			      "Button debug state expected to be %d(%s),"     \
+			      " but was %d(%s)",                              \
+			      expected, button_debug_state_strings[expected], \
+			      state, button_debug_state_strings[state]);      \
+	} while (false)
+
+struct button_fixture {
+	timestamp_t fake_time;
+};
+
+static void *button_setup(void)
+{
+	static struct button_fixture fixture;
+
+	/* Set the mock clock */
+	get_time_mock = &fixture.fake_time;
+	return &fixture;
+}
+
+static void button_before(void *f)
+{
+	((struct button_fixture *)f)->fake_time.val = 0;
+	reset_button_debug_state();
+	button_init();
+	/* Sleep for 30s to flush any pending tasks */
+	k_sleep(K_SECONDS(30));
+	mkbp_clear_fifo();
+
+	RESET_FAKE(chipset_reset);
+}
+
+ZTEST_SUITE(button, drivers_predicate_post_main, button_setup, button_before,
+	    NULL, NULL);
+
+static inline void pass_time(uint64_t duration_ms)
+{
+	get_time_mock->val += duration_ms * 1000;
+	k_msleep(duration_ms);
+}
+
+ZTEST(button, test_press_one_button_no_change)
+{
+	/* Press the volume-up button for 1/2 a second */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "button vup 500"));
+
+	/* Wait for the timeout */
+	pass_time(11000);
+	ASSERT_DEBUG_STATE(STATE_DEBUG_NONE);
+}
+
+ZTEST(button, test_press_vup_vdown_too_short)
+{
+	/* Press both volume-up and volume-down for 1/2 second */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "button vup 500"));
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "button vdown 500"));
+
+	/* Let the deferred calls get run (800ms) */
+	pass_time(800);
+	ASSERT_DEBUG_STATE(STATE_DEBUG_CHECK);
+
+	/* Wait for the timeout */
+	pass_time(11000);
+	ASSERT_DEBUG_STATE(STATE_DEBUG_NONE);
+}
+
+ZTEST(button, test_fail_check_button_released_too_soon)
+{
+	/* Press both volume-up and volume-down for 0.9 seconds */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "button vup 9000"));
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "button vdown 9000"));
+
+	/* Let the deferred calls get run (800ms) */
+	pass_time(800);
+	ASSERT_DEBUG_STATE(STATE_DEBUG_CHECK);
+
+	/* Wait for the timeout, should put us in staging */
+	pass_time(11000);
+	ASSERT_DEBUG_STATE(STATE_STAGING);
+
+	/* Wait for the handler to be called and set us to ACTIVE mode */
+	pass_time(7000);
+	ASSERT_DEBUG_STATE(STATE_DEBUG_MODE_ACTIVE);
+
+	/* Wait for the deadline to pass, putting us back in NONE */
+	pass_time(11000);
+	ASSERT_DEBUG_STATE(STATE_DEBUG_NONE);
+}
+
+ZTEST(button, test_fail_check_button_stuck)
+{
+	/* Press both volume-up and volume-down for 0.9 seconds */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "button vup 30000"));
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "button vdown 30000"));
+
+	/* Let the deferred calls get run (800ms) */
+	pass_time(800);
+	ASSERT_DEBUG_STATE(STATE_DEBUG_CHECK);
+
+	/* Wait for the timeout, should put us in staging */
+	pass_time(11000);
+	ASSERT_DEBUG_STATE(STATE_STAGING);
+
+	/* Do a plain sleep to force the error condition of waking up the
+	 * handler too early (since the time isn't moving forward).
+	 */
+	k_msleep(11000);
+
+	/* Now sleep and move the clock forward to timeout the debug process */
+	pass_time(11000);
+	ASSERT_DEBUG_STATE(STATE_DEBUG_NONE);
+}
+
+ZTEST(button, test_activate_sysrq_path_then_timeout)
+{
+	/* Press both volume-up and volume-down for 1/2 second */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "button vup 10500"));
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "button vdown 10500"));
+
+	/* Let the deferred calls get run (800ms) */
+	pass_time(800);
+	ASSERT_DEBUG_STATE(STATE_DEBUG_CHECK);
+
+	/* Wait for the buttons to be released */
+	pass_time(11000);
+	ASSERT_DEBUG_STATE(STATE_STAGING);
+
+	/* Wait a bit and check that we activated debug mode */
+	pass_time(11000);
+	ASSERT_DEBUG_STATE(STATE_DEBUG_MODE_ACTIVE);
+
+	/* Press volume up button to put in sysrq_path */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "button vup 500"));
+	pass_time(800);
+	ASSERT_DEBUG_STATE(STATE_STAGING);
+
+	/* Wait for timeout and go into sysrq_path */
+	pass_time(500);
+	ASSERT_DEBUG_STATE(STATE_SYSRQ_PATH);
+
+	/* Now sleep and move the clock forward to timeout the debug process */
+	pass_time(11000);
+	ASSERT_DEBUG_STATE(STATE_DEBUG_NONE);
+}
+
+ZTEST(button, test_activate_sysrq_path_4_times)
+{
+	/* Press both volume-up and volume-down for 1/2 second */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "button vup 10500"));
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "button vdown 10500"));
+
+	/* Let the deferred calls get run (800ms) */
+	pass_time(800);
+	ASSERT_DEBUG_STATE(STATE_DEBUG_CHECK);
+
+	/* Wait for the buttons to be released */
+	pass_time(11000);
+	ASSERT_DEBUG_STATE(STATE_STAGING);
+
+	/* Wait a bit and check that we activated debug mode */
+	pass_time(11000);
+	ASSERT_DEBUG_STATE(STATE_DEBUG_MODE_ACTIVE);
+
+	/* Press volume up button to put in sysrq_path */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "button vup 500"));
+	pass_time(800);
+	ASSERT_DEBUG_STATE(STATE_STAGING);
+
+	/* Wait for timeout and go into sysrq_path */
+	pass_time(500);
+	ASSERT_DEBUG_STATE(STATE_SYSRQ_PATH);
+
+	/* Press vup again (#2) */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "button vup 500"));
+	pass_time(800);
+	pass_time(500);
+
+	/* Press vup again (#3) */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "button vup 500"));
+	pass_time(800);
+	pass_time(500);
+
+	/* Press vup again (#4) */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "button vup 500"));
+	pass_time(800);
+	pass_time(500);
+	ASSERT_DEBUG_STATE(STATE_DEBUG_NONE);
+}
+
+ZTEST(button, test_activate_sysrq_exec)
+{
+	uint32_t event_data = 0;
+
+	/* Press both volume-up and volume-down for 1/2 second */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "button vup 10500"));
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "button vdown 10500"));
+
+	/* Let the deferred calls get run (800ms) */
+	pass_time(800);
+	ASSERT_DEBUG_STATE(STATE_DEBUG_CHECK);
+
+	/* Wait for the buttons to be released */
+	pass_time(11000);
+	ASSERT_DEBUG_STATE(STATE_STAGING);
+
+	/* Wait a bit and check that we activated debug mode */
+	pass_time(11000);
+	ASSERT_DEBUG_STATE(STATE_DEBUG_MODE_ACTIVE);
+
+	/* Press volume up button to put in sysrq_path */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "button vup 500"));
+	pass_time(800);
+	ASSERT_DEBUG_STATE(STATE_STAGING);
+
+	/* Wait for timeout and go into sysrq_path */
+	pass_time(500);
+	ASSERT_DEBUG_STATE(STATE_SYSRQ_PATH);
+
+	/* Now sleep and move the clock forward to timeout the debug process */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "button vdown 500"));
+	pass_time(800);
+	pass_time(500);
+	ASSERT_DEBUG_STATE(STATE_DEBUG_NONE);
+
+	/* Flush all the button events */
+	while (mkbp_fifo_get_next_event((uint8_t *)&event_data,
+					EC_MKBP_EVENT_BUTTON) > 0)
+		;
+
+	/* Check for sysrq event */
+	zassert_equal(4, mkbp_fifo_get_next_event((uint8_t *)&event_data,
+						  EC_MKBP_EVENT_SYSRQ));
+	zassert_equal((uint32_t)'x', event_data);
+}
+
+ZTEST(button, test_activate_warm_reset_then_timeout)
+{
+	/* Press both volume-up and volume-down for 1/2 second */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "button vup 10500"));
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "button vdown 10500"));
+
+	/* Let the deferred calls get run (800ms) */
+	pass_time(800);
+	ASSERT_DEBUG_STATE(STATE_DEBUG_CHECK);
+
+	/* Wait for the buttons to be released */
+	pass_time(11000);
+	ASSERT_DEBUG_STATE(STATE_STAGING);
+
+	/* Wait a bit and check that we activated debug mode */
+	pass_time(11000);
+	ASSERT_DEBUG_STATE(STATE_DEBUG_MODE_ACTIVE);
+
+	/* Press volume down button to put in warm_reset_path */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "button vdown 500"));
+	pass_time(800);
+	ASSERT_DEBUG_STATE(STATE_STAGING);
+
+	/* Wait for timeout and go into warm_reset_path */
+	pass_time(500);
+	ASSERT_DEBUG_STATE(STATE_WARM_RESET_PATH);
+
+	/* Now sleep and move the clock forward to timeout the debug process */
+	pass_time(11000);
+	ASSERT_DEBUG_STATE(STATE_DEBUG_NONE);
+}
+
+ZTEST(button, test_activate_warm_reset_exec)
+{
+	/* Press both volume-up and volume-down for 1/2 second */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "button vup 10500"));
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "button vdown 10500"));
+
+	/* Let the deferred calls get run (800ms) */
+	pass_time(800);
+	ASSERT_DEBUG_STATE(STATE_DEBUG_CHECK);
+
+	/* Wait for the buttons to be released */
+	pass_time(11000);
+	ASSERT_DEBUG_STATE(STATE_STAGING);
+
+	/* Wait a bit and check that we activated debug mode */
+	pass_time(11000);
+	ASSERT_DEBUG_STATE(STATE_DEBUG_MODE_ACTIVE);
+
+	/* Press volume down button to put in warm_reset_path */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "button vdown 500"));
+	pass_time(800);
+	ASSERT_DEBUG_STATE(STATE_STAGING);
+
+	/* Wait for timeout and go into warm_reset_path */
+	pass_time(500);
+	ASSERT_DEBUG_STATE(STATE_WARM_RESET_PATH);
+
+	/* Now sleep and move the clock forward to timeout the debug process.
+	 * Doing this in two steps verifies that even after the handler executes
+	 * "too early" we can still recover via the vup button that's coming
+	 * next. This is caused by effectively, sleeping so the scheduler runs,
+	 * but not ticking the clock forward yet until the next sleep.
+	 */
+	k_msleep(11000);
+	pass_time(11000);
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "button vup 500"));
+	pass_time(800);
+	ASSERT_DEBUG_STATE(STATE_STAGING);
+
+	pass_time(11000);
+	ASSERT_DEBUG_STATE(STATE_DEBUG_NONE);
+	zassert_equal(1, chipset_reset_fake.call_count);
+	zassert_equal(CHIPSET_RESET_DBG_WARM_REBOOT,
+		      chipset_reset_fake.arg0_val);
+}
diff --git a/zephyr/test/drivers/cbi_flash/CMakeLists.txt b/zephyr/test/drivers/cbi_flash/CMakeLists.txt
new file mode 100644
index 0000000000..8617e1d491
--- /dev/null
+++ b/zephyr/test/drivers/cbi_flash/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Add source files
+target_sources(app PRIVATE src/cbi_flash.c)
diff --git a/zephyr/test/drivers/cbi_flash/binman.dts b/zephyr/test/drivers/cbi_flash/binman.dts
new file mode 100644
index 0000000000..93a72a515f
--- /dev/null
+++ b/zephyr/test/drivers/cbi_flash/binman.dts
@@ -0,0 +1,67 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	binman {
+		filename = "ec.bin";
+		pad-byte = <0x1d>;
+		wp-ro {
+			compatible = "cros-ec,flash-layout";
+			type = "section";
+			offset = <0x0>;
+			size = <0x40000>;
+			read-only;
+			ec-ro {
+				type = "section";
+				ro-fw {
+					type = "blob";
+					filename = "zephyr_ro.bin";
+				};
+				fmap {
+				};
+				ro-frid {
+					type = "text";
+					size = <32>;
+					text-label = "version";
+				};
+			};
+			cbi_flash: cbi {
+				compatible = "cros-ec,flash-layout";
+				type = "fill";
+				offset = <(0x40000 - 0x1000)>;
+				size = <0x1000>;
+				fill-byte = [ff];
+				preserve;
+			};
+		};
+		ec-rw {
+			compatible = "cros-ec,flash-layout";
+			type = "section";
+			offset = <0x40000>;
+			size = <0x40000>;
+			rw-fw {
+				type = "section";
+				zephyr-rw {
+					type = "blob";
+					filename = "zephyr_rw.bin";
+				};
+				rw-fwid {
+					/* Fix the lcoation of the FWID to the
+					 * last 32 bytes of the flash. This
+					 * ensures the RW entries in the FMAP
+					 * stored in the RO section of flash
+					 * are always correct.
+					 */
+					offset = <(0x40000 - 32)>;
+					type = "text";
+					size = <32>;
+					text-label = "version";
+				};
+			};
+		};
+	};
+};
diff --git a/zephyr/test/drivers/cbi_flash/src/cbi_flash.c b/zephyr/test/drivers/cbi_flash/src/cbi_flash.c
new file mode 100644
index 0000000000..021287fbb4
--- /dev/null
+++ b/zephyr/test/drivers/cbi_flash/src/cbi_flash.c
@@ -0,0 +1,106 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cros_board_info.h"
+#include "emul/emul_flash.h"
+#include "flash.h"
+#include "test/drivers/test_mocks.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/fff.h>
+#include <zephyr/ztest.h>
+
+#define CBI_FLASH_NODE DT_NODELABEL(cbi_flash)
+#define CBI_FLASH_OFFSET DT_PROP(CBI_FLASH_NODE, offset)
+
+FAKE_VALUE_FUNC(int, crec_flash_unprotected_read, int, int, char *);
+
+ZTEST(cbi_flash, test_cbi_flash_is_write_protected)
+{
+	system_is_locked_fake.return_val = 1;
+	zassert_equal(cbi_config.drv->is_protected(), 1);
+	zassert_equal(system_is_locked_fake.call_count, 1);
+}
+
+ZTEST(cbi_flash, test_cbi_flash_is_write_protected_false)
+{
+	system_is_locked_fake.return_val = 0;
+	zassert_equal(cbi_config.drv->is_protected(), 0);
+	zassert_equal(system_is_locked_fake.call_count, 1);
+}
+
+ZTEST(cbi_flash, test_cbi_flash_load)
+{
+	int index;
+	uint8_t input_data[CBI_IMAGE_SIZE];
+	uint8_t data[CBI_IMAGE_SIZE];
+
+	for (index = 0; index < CBI_IMAGE_SIZE; index++) {
+		input_data[index] = index % 255;
+	}
+	cbi_config.drv->store(input_data);
+	crec_flash_unprotected_read_fake.custom_fake = crec_flash_physical_read;
+
+	zassert_ok(cbi_config.drv->load(0, data, CBI_IMAGE_SIZE));
+	for (index = 0; index < CBI_IMAGE_SIZE; index++) {
+		zassert_equal(data[index], index % 255);
+	}
+
+	zassert_ok(cbi_config.drv->load(211, data, CBI_IMAGE_SIZE - 400));
+	for (index = 0; index < CBI_IMAGE_SIZE - 400; index++) {
+		zassert_equal(data[index], (index + 211) % 255);
+	}
+
+	zassert_ok(cbi_config.drv->load(211, data, 0));
+	for (index = 0; index < 0; index++) {
+		zassert_equal(data[index], (index + 211) % 255);
+	}
+
+	zassert_equal(cbi_config.drv->load(0, data, -1), EC_ERROR_INVAL);
+
+	zassert_equal(cbi_config.drv->load(-1, data, CBI_IMAGE_SIZE),
+		      EC_ERROR_INVAL);
+
+	zassert_equal(cbi_config.drv->load(0, data, CBI_IMAGE_SIZE + 1),
+		      EC_ERROR_INVAL);
+
+	zassert_equal(cbi_config.drv->load(1, data, CBI_IMAGE_SIZE),
+		      EC_ERROR_INVAL);
+}
+
+ZTEST(cbi_flash, test_cbi_flash_load_error)
+{
+	uint8_t data[CBI_IMAGE_SIZE];
+
+	crec_flash_unprotected_read_fake.return_val = EC_ERROR_INVAL;
+	zassert_equal(cbi_config.drv->load(0, data, CBI_IMAGE_SIZE),
+		      EC_ERROR_INVAL);
+}
+
+ZTEST(cbi_flash, test_cbi_flash_store)
+{
+	uint8_t data[CBI_IMAGE_SIZE];
+
+	zassert_ok(cbi_config.drv->store(data));
+}
+
+ZTEST(cbi_flash, test_cbi_flash_store_fail)
+{
+	uint8_t data[CBI_IMAGE_SIZE];
+
+	cros_flash_emul_enable_protect();
+	zassert_equal(cbi_config.drv->store(data), EC_ERROR_ACCESS_DENIED);
+	cros_flash_emul_protect_reset();
+}
+
+static void cbi_flash_before(void *fixture)
+{
+	ARG_UNUSED(fixture);
+	RESET_FAKE(crec_flash_unprotected_read);
+}
+
+ZTEST_SUITE(cbi_flash, drivers_predicate_post_main, NULL, cbi_flash_before,
+	    NULL, NULL);
diff --git a/zephyr/test/drivers/chargesplash/CMakeLists.txt b/zephyr/test/drivers/chargesplash/CMakeLists.txt
new file mode 100644
index 0000000000..f0746a4cdd
--- /dev/null
+++ b/zephyr/test/drivers/chargesplash/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Add source files
+target_sources(app PRIVATE src/chargesplash.c)
diff --git a/zephyr/test/drivers/chargesplash/src/chargesplash.c b/zephyr/test/drivers/chargesplash/src/chargesplash.c
new file mode 100644
index 0000000000..8ca872155b
--- /dev/null
+++ b/zephyr/test/drivers/chargesplash/src/chargesplash.c
@@ -0,0 +1,302 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "chipset.h"
+#include "config.h"
+#include "ec_commands.h"
+#include "extpower.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "lid_switch.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "timer.h"
+
+#include <stdbool.h>
+
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/kernel.h>
+#include <zephyr/shell/shell.h>
+#include <zephyr/shell/shell_uart.h>
+#include <zephyr/sys/__assert.h>
+#include <zephyr/ztest.h>
+
+/* Do a chargesplash host cmd */
+static enum ec_status
+chargesplash_hostcmd(enum ec_chargesplash_cmd cmd,
+		     struct ec_response_chargesplash *response)
+{
+	struct ec_params_chargesplash params = { .cmd = cmd };
+
+	return ec_cmd_chargesplash(NULL, &params, response);
+}
+
+static bool is_chargesplash_requested(void)
+{
+	struct ec_response_chargesplash response;
+
+	zassert_ok(chargesplash_hostcmd(EC_CHARGESPLASH_GET_STATE, &response),
+		   NULL);
+
+	return response.requested;
+}
+
+static struct k_poll_signal s0_signal = K_POLL_SIGNAL_INITIALIZER(s0_signal);
+static struct k_poll_event s0_event = K_POLL_EVENT_INITIALIZER(
+	K_POLL_TYPE_SIGNAL, K_POLL_MODE_NOTIFY_ONLY, &s0_signal);
+
+static void handle_chipset_s0_event(void)
+{
+	k_poll_signal_raise(&s0_signal, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, handle_chipset_s0_event, HOOK_PRIO_LAST);
+
+static void wait_for_chipset_startup(void)
+{
+	if (!chipset_in_state(CHIPSET_STATE_ON)) {
+		k_poll_signal_reset(&s0_signal);
+		k_poll(&s0_event, 1, K_FOREVER);
+	}
+
+	/*
+	 * TODO(b/230362548): We need to give the EC a bit to "calm down"
+	 * after reaching S0.
+	 */
+	msleep(2000);
+}
+
+#define GPIO_LID_OPEN_EC_NODE DT_NODELABEL(gpio_lid_open_ec)
+#define GPIO_LID_OPEN_EC_CTLR DT_GPIO_CTLR(GPIO_LID_OPEN_EC_NODE, gpios)
+#define GPIO_LID_OPEN_EC_PORT DT_GPIO_PIN(GPIO_LID_OPEN_EC_NODE, gpios)
+
+static void set_lid(bool open, bool inhibit_boot)
+{
+	const struct device *lid_switch_dev =
+		DEVICE_DT_GET(GPIO_LID_OPEN_EC_CTLR);
+
+	__ASSERT(lid_is_open() != open,
+		 "Lid change was requested, but it's already in that state");
+
+	if (!open) {
+		__ASSERT(!inhibit_boot,
+			 "inhibit_boot should not be used with a lid close");
+	}
+
+	zassert_ok(gpio_emul_input_set(lid_switch_dev, GPIO_LID_OPEN_EC_PORT,
+				       open),
+		   "Failed to set lid switch GPIO");
+
+	while (lid_is_open() != open) {
+		usleep(LID_DEBOUNCE_US + 1);
+	}
+
+	if (inhibit_boot) {
+		wait_for_chipset_startup();
+		test_set_chipset_to_g3();
+	}
+}
+
+/* Simulate a regular power button press */
+static void pulse_power_button(void)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "powerbtn"));
+}
+
+static void reset_state(void *unused)
+{
+	test_set_chipset_to_g3();
+
+	/*
+	 * Prevent critical low battery from moving us back to G3 when
+	 * lid is opened.
+	 */
+	test_set_battery_level(75);
+
+	if (lid_is_open()) {
+		set_lid(false, false);
+	}
+
+	if (extpower_is_present()) {
+		set_ac_enabled(false);
+	}
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "chargesplash reset"),
+		   "'chargesplash reset' shell command failed");
+}
+
+ZTEST_SUITE(chargesplash, drivers_predicate_post_main, NULL, reset_state, NULL,
+	    reset_state);
+
+/*
+ * When the lid is open and AC is connected, the chargesplash should
+ * be requested.
+ */
+ZTEST_USER(chargesplash, test_connect_ac)
+{
+	set_lid(true, true);
+
+	set_ac_enabled(true);
+	zassert_true(is_chargesplash_requested(),
+		     "chargesplash should be requested");
+	wait_for_chipset_startup();
+}
+
+/*
+ * When AC is not connected and we open the lid, the chargesplash
+ * should not be requested.
+ */
+ZTEST_USER(chargesplash, test_no_connect_ac)
+{
+	set_lid(true, false);
+	zassert_false(is_chargesplash_requested(),
+		      "chargesplash should not be requested");
+	wait_for_chipset_startup();
+}
+
+/*
+ * When we connect AC with the lid closed, the chargesplash should not
+ * be requested.
+ */
+ZTEST_USER(chargesplash, test_ac_connect_when_lid_closed)
+{
+	set_ac_enabled(true);
+	zassert_false(is_chargesplash_requested(),
+		      "chargesplash should not be requested");
+}
+
+/*
+ * Test that, after many repeated requests, the chargesplash
+ * feature becomes locked and non-functional.  This condition
+ * replicates a damaged charger or port which cannot maintain a
+ * reliable connection.
+ *
+ * Then, ensure the lockout clears after the chargesplash period
+ * passes.
+ */
+ZTEST_USER(chargesplash, test_lockout)
+{
+	int i;
+
+	set_lid(true, true);
+
+	for (i = 0; i < CONFIG_CHARGESPLASH_MAX_REQUESTS_PER_PERIOD; i++) {
+		set_ac_enabled(true);
+
+		zassert_true(is_chargesplash_requested(),
+			     "chargesplash should be requested");
+		wait_for_chipset_startup();
+
+		set_ac_enabled(false);
+		test_set_chipset_to_g3();
+	}
+
+	set_ac_enabled(true);
+	zassert_false(is_chargesplash_requested(),
+		      "chargesplash should be locked out");
+	set_ac_enabled(false);
+
+	sleep(CONFIG_CHARGESPLASH_PERIOD);
+
+	set_ac_enabled(true);
+	zassert_true(is_chargesplash_requested(),
+		     "lockout should have cleared");
+	wait_for_chipset_startup();
+}
+
+/* Test cancel chargesplash request by power button push */
+ZTEST_USER(chargesplash, test_power_button)
+{
+	set_lid(true, true);
+
+	set_ac_enabled(true);
+	zassert_true(is_chargesplash_requested(),
+		     "chargesplash should be requested");
+	wait_for_chipset_startup();
+	zassert_true(is_chargesplash_requested(),
+		     "chargesplash should still be requested");
+
+	pulse_power_button();
+	zassert_false(is_chargesplash_requested(),
+		      "chargesplash should be canceled by power button push");
+	zassert_true(chipset_in_state(CHIPSET_STATE_ON),
+		     "chipset should be on");
+}
+
+/* Manually lockout the feature via the shell */
+ZTEST_USER(chargesplash, test_manual_lockout_via_console)
+{
+	/*
+	 * Put an entry in the request log so the lockout has
+	 * something to wait on to clear.
+	 */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "chargesplash request"),
+		   NULL);
+	zassert_true(is_chargesplash_requested(),
+		     "chargesplash should be requested");
+	wait_for_chipset_startup();
+	test_set_chipset_to_g3();
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "chargesplash lockout"),
+		   NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "chargesplash request"),
+		   NULL);
+	zassert_false(is_chargesplash_requested(),
+		      "chargesplash should be not requested due to lockout");
+
+	sleep(CONFIG_CHARGESPLASH_PERIOD);
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "chargesplash request"),
+		   NULL);
+	zassert_true(is_chargesplash_requested(),
+		     "lockout should have cleared");
+	wait_for_chipset_startup();
+}
+
+/* Manually lockout the feature via host command */
+ZTEST_USER(chargesplash, test_manual_lockout_via_hostcmd)
+{
+	struct ec_response_chargesplash response;
+
+	zassert_ok(chargesplash_hostcmd(EC_CHARGESPLASH_REQUEST, &response),
+		   NULL);
+	zassert_true(is_chargesplash_requested(),
+		     "chargesplash should be requested");
+	wait_for_chipset_startup();
+	test_set_chipset_to_g3();
+
+	zassert_ok(chargesplash_hostcmd(EC_CHARGESPLASH_LOCKOUT, &response),
+		   NULL);
+	zassert_ok(chargesplash_hostcmd(EC_CHARGESPLASH_REQUEST, &response),
+		   NULL);
+	zassert_false(is_chargesplash_requested(),
+		      "chargesplash should be not requested due to lockout");
+
+	sleep(CONFIG_CHARGESPLASH_PERIOD);
+
+	zassert_ok(chargesplash_hostcmd(EC_CHARGESPLASH_REQUEST, &response),
+		   NULL);
+	zassert_true(is_chargesplash_requested(),
+		     "lockout should have cleared");
+	wait_for_chipset_startup();
+}
+
+/* Simulate an actual run of the display loop */
+ZTEST_USER(chargesplash, test_display_loop)
+{
+	struct ec_response_chargesplash response;
+
+	set_lid(true, true);
+	set_ac_enabled(true);
+	zassert_true(is_chargesplash_requested());
+	wait_for_chipset_startup();
+
+	zassert_ok(chargesplash_hostcmd(EC_CHARGESPLASH_DISPLAY_READY,
+					&response),
+		   NULL);
+
+	zassert_true(is_chargesplash_requested());
+	pulse_power_button();
+	zassert_false(is_chargesplash_requested());
+}
diff --git a/zephyr/test/drivers/common/CMakeLists.txt b/zephyr/test/drivers/common/CMakeLists.txt
new file mode 100644
index 0000000000..854294ab11
--- /dev/null
+++ b/zephyr/test/drivers/common/CMakeLists.txt
@@ -0,0 +1,13 @@
+# Common sources
+target_sources(app PRIVATE
+  src/main.c
+  src/test_mocks.c
+  src/test_rules.c
+  src/utils.c
+  src/stubs.c
+)
+target_include_directories(app PRIVATE
+    ${CMAKE_CURRENT_SOURCE_DIR}/include
+    ${PLATFORM_EC}/driver/ppc/
+    ${PLATFORM_EC}/zephyr/shim/src/led_driver
+)
diff --git a/zephyr/test/drivers/common/include/test/drivers/charger_utils.h b/zephyr/test/drivers/common/include/test/drivers/charger_utils.h
new file mode 100644
index 0000000000..22331c8575
--- /dev/null
+++ b/zephyr/test/drivers/common/include/test/drivers/charger_utils.h
@@ -0,0 +1,30 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef ZEPHYR_TEST_DRIVERS_INCLUDE_CHARGER_UTILS_H_
+#define ZEPHYR_TEST_DRIVERS_INCLUDE_CHARGER_UTILS_H_
+
+#include "charger.h"
+
+/**
+ * @brief Get the index of the charger in chg_chips
+ *
+ * @param charger Pointer to the charger driver.
+ * @return The index of the charger if found
+ * @return board_get_charger_chip_count() if not found
+ */
+static inline uint8_t get_charger_num(const struct charger_drv *charger)
+{
+	const uint8_t chip_count = board_get_charger_chip_count();
+	uint8_t chip;
+
+	for (chip = 0; chip < chip_count; ++chip) {
+		if (chg_chips[chip].drv == charger)
+			return chip;
+	}
+	return chip;
+}
+
+#endif /* ZEPHYR_TEST_DRIVERS_INCLUDE_CHARGER_UTILS_H_ */
diff --git a/zephyr/test/drivers/common/include/test/drivers/stubs.h b/zephyr/test/drivers/common/include/test/drivers/stubs.h
new file mode 100644
index 0000000000..63718649f8
--- /dev/null
+++ b/zephyr/test/drivers/common/include/test/drivers/stubs.h
@@ -0,0 +1,31 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __TEST_DRIVERS_STUBS_H
+#define __TEST_DRIVERS_STUBS_H
+
+#include "power.h"
+
+#include <zephyr/fff.h>
+
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
+
+/**
+ * @brief Set product ID that should be returned by board_get_ps8xxx_product_id
+ *
+ * @param product_id ID of PS8xxx product which is emulated
+ */
+void board_set_ps8xxx_product_id(uint16_t product_id);
+
+/* Declare fake function to allow tests to examine calls to this function */
+DECLARE_FAKE_VOID_FUNC(system_hibernate, uint32_t, uint32_t);
+
+DECLARE_FAKE_VOID_FUNC(board_reset_pd_mcu);
+
+void sys_arch_reboot(int type);
+
+/* Declare GPIO_TEST interrupt handler */
+void gpio_test_interrupt(enum gpio_signal signal);
+#endif /* __TEST_DRIVERS_STUBS_H */
diff --git a/zephyr/test/drivers/common/include/test/drivers/tcpci_test_common.h b/zephyr/test/drivers/common/include/test/drivers/tcpci_test_common.h
new file mode 100644
index 0000000000..9abaa1be53
--- /dev/null
+++ b/zephyr/test/drivers/common/include/test/drivers/tcpci_test_common.h
@@ -0,0 +1,264 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __TCPCI_TEST_COMMON_H
+#define __TCPCI_TEST_COMMON_H
+
+#include "stubs.h"
+
+/**
+ * @brief Check TCPC register value using zassert API
+ *
+ * @param emul Pointer to TCPCI emulator
+ * @param reg TCPC register address to check
+ * @param exp_val Expected value of register
+ * @param line Line number to print in case of failure
+ */
+void check_tcpci_reg_f(const struct emul *emul, int reg, uint16_t exp_val,
+		       int line);
+#define check_tcpci_reg(emul, reg, exp_val) \
+	check_tcpci_reg_f((emul), (reg), (exp_val), __LINE__)
+
+/**
+ * @brief Check TCPC register value with mask using zassert API
+ *
+ * @param emul Pointer to TCPCI emulator
+ * @param reg TCPC register address to check
+ * @param exp_val Expected value of register
+ * @param mask Bits that are checked
+ * @param line Line number to print in case of failure
+ */
+void check_tcpci_reg_with_mask_f(const struct emul *emul, int reg,
+				 uint16_t exp_val, uint16_t mask, int line);
+#define check_tcpci_reg_with_mask(emul, reg, exp_val, mask) \
+	check_tcpci_reg_with_mask_f((emul), (reg), (exp_val), (mask), __LINE__)
+
+/**
+ * @brief Test TCPCI init and vbus level callback
+ *
+ * @param emul Pointer to TCPCI emulator
+ * @param common_data Pointer to argument emul's i2c_common_emul_data
+ * @param port Select USBC port that will be used to obtain tcpm_drv from
+ *             tcpc_config
+ */
+void test_tcpci_init(const struct emul *emul,
+		     struct i2c_common_emul_data *common_data,
+		     enum usbc_port port);
+
+/**
+ * @brief Test TCPCI release callback
+ *
+ * @param emul Pointer to TCPCI emulator
+ * @param common_data Pointer to argument emul's i2c_common_emul_data
+ * @param port Select USBC port that will be used to obtain tcpm_drv from
+ *             tcpc_config
+ */
+void test_tcpci_release(const struct emul *emul,
+			struct i2c_common_emul_data *common_data,
+			enum usbc_port port);
+
+/**
+ * @brief Test TCPCI get cc callback
+ *
+ * @param emul Pointer to TCPCI emulator
+ * @param common_data Pointer to argument emul's i2c_common_emul_data
+ * @param port Select USBC port that will be used to obtain tcpm_drv from
+ *             tcpc_config
+ */
+void test_tcpci_get_cc(const struct emul *emul,
+		       struct i2c_common_emul_data *common_data,
+		       enum usbc_port port);
+
+/**
+ * @brief Test TCPCI set cc callback
+ *
+ * @param emul Pointer to TCPCI emulator
+ * @param common_data Pointer to argument emul's i2c_common_emul_data
+ * @param port Select USBC port that will be used to obtain tcpm_drv from
+ *             tcpc_config
+ */
+void test_tcpci_set_cc(const struct emul *emul,
+		       struct i2c_common_emul_data *common_data,
+		       enum usbc_port port);
+
+/**
+ * @brief Test TCPCI set polarity callback
+ *
+ * @param emul Pointer to TCPCI emulator
+ * @param common_data Pointer to argument emul's i2c_common_emul_data
+ * @param port Select USBC port that will be used to obtain tcpm_drv from
+ *             tcpc_config
+ */
+void test_tcpci_set_polarity(const struct emul *emul,
+			     struct i2c_common_emul_data *common_data,
+			     enum usbc_port port);
+
+/**
+ * @brief Test TCPCI set vconn callback
+ *
+ * @param emul Pointer to TCPCI emulator
+ * @param common_data Pointer to argument emul's i2c_common_emul_data
+ * @param port Select USBC port that will be used to obtain tcpm_drv from
+ *             tcpc_config
+ */
+void test_tcpci_set_vconn(const struct emul *emul,
+			  struct i2c_common_emul_data *common_data,
+			  enum usbc_port port);
+
+/**
+ * @brief Test TCPCI set msg header callback
+ *
+ * @param emul Pointer to TCPCI emulator
+ * @param common_data Pointer to argument emul's i2c_common_emul_data
+ * @param port Select USBC port that will be used to obtain tcpm_drv from
+ *             tcpc_config
+ */
+void test_tcpci_set_msg_header(const struct emul *emul,
+			       struct i2c_common_emul_data *common_data,
+			       enum usbc_port port);
+
+/**
+ * @brief Test TCPCI rx and sop prime enable callback
+ *
+ * @param emul Pointer to TCPCI emulator
+ * @param common_data Pointer to argument emul's i2c_common_emul_data
+ * @param port Select USBC port that will be used to obtain tcpm_drv from
+ *             tcpc_config
+ */
+void test_tcpci_set_rx_detect(const struct emul *emul,
+			      struct i2c_common_emul_data *common_data,
+			      enum usbc_port port);
+
+/**
+ * @brief Test TCPCI get raw message from TCPC callback
+ *
+ * @param emul Pointer to TCPCI emulator
+ * @param port Select USBC port that will be used to obtain tcpm_drv from
+ *             tcpc_config
+ */
+void test_tcpci_get_rx_message_raw(const struct emul *emul,
+				   struct i2c_common_emul_data *common_data,
+				   enum usbc_port port);
+
+/**
+ * @brief Test TCPCI transmitting message from TCPC callback
+ *
+ * @param emul Pointer to TCPCI emulator
+ * @param common_data Pointer to argument emul's i2c_common_emul_data
+ * @param port Select USBC port that will be used to obtain tcpm_drv from
+ *             tcpc_config
+ */
+void test_tcpci_transmit(const struct emul *emul,
+			 struct i2c_common_emul_data *common_data,
+			 enum usbc_port port);
+
+/**
+ * @brief Test TCPCI alert callback
+ *
+ * @param emul Pointer to TCPCI emulator
+ * @param common_data Pointer to argument emul's i2c_common_emul_data
+ * @param port Select USBC port that will be used to obtain tcpm_drv from
+ *             tcpc_config
+ */
+void test_tcpci_alert(const struct emul *emul,
+		      struct i2c_common_emul_data *common_data,
+		      enum usbc_port port);
+
+/**
+ * @brief Test TCPCI alert RX message callback
+ *
+ * @param emul Pointer to TCPCI emulator
+ * @param common_data Pointer to argument emul's i2c_common_emul_data
+ * @param port Select USBC port that will be used to obtain tcpm_drv from
+ *             tcpc_config
+ */
+void test_tcpci_alert_rx_message(const struct emul *emul,
+				 struct i2c_common_emul_data *common_data,
+				 enum usbc_port port);
+
+/**
+ * @brief Test TCPCI auto discharge on disconnect callback
+ *
+ * @param emul Pointer to TCPCI emulator
+ * @param common_data Pointer to argument emul's i2c_common_emul_data
+ * @param port Select USBC port that will be used to obtain tcpm_drv from
+ *             tcpc_config
+ */
+void test_tcpci_auto_discharge(const struct emul *emul,
+			       struct i2c_common_emul_data *common_data,
+			       enum usbc_port port);
+
+/**
+ * @brief Test TCPCI drp toggle callback
+ *
+ * @param emul Pointer to TCPCI emulator
+ * @param common_data Pointer to argument emul's i2c_common_emul_data
+ * @param port Select USBC port that will be used to obtain tcpm_drv from
+ *             tcpc_config
+ */
+void test_tcpci_drp_toggle(const struct emul *emul,
+			   struct i2c_common_emul_data *common_data,
+			   enum usbc_port port);
+
+/**
+ * @brief Test TCPCI get chip info callback
+ *
+ * @param emul Pointer to TCPCI emulator
+ * @param common_data Pointer to argument emul's i2c_common_emul_data
+ * @param port Select USBC port that will be used to obtain tcpm_drv from
+ *             tcpc_config
+ */
+void test_tcpci_get_chip_info(const struct emul *emul,
+			      struct i2c_common_emul_data *common_data,
+			      enum usbc_port port);
+
+/**
+ * @brief Test TCPCI enter low power mode callback
+ *
+ * @param emul Pointer to TCPCI emulator
+ * @param common_data Pointer to argument emul's i2c_common_emul_data
+ * @param port Select USBC port that will be used to obtain tcpm_drv from
+ *             tcpc_config
+ */
+void test_tcpci_low_power_mode(const struct emul *emul,
+			       struct i2c_common_emul_data *common_data,
+			       enum usbc_port port);
+
+/**
+ * @brief Test TCPCI set bist test mode callback
+ *
+ * @param emul Pointer to TCPCI emulator
+ * @param common_data Pointer to argument emul's i2c_common_emul_data
+ * @param port Select USBC port that will be used to obtain tcpm_drv from
+ *             tcpc_config
+ */
+void test_tcpci_set_bist_mode(const struct emul *emul,
+			      struct i2c_common_emul_data *common_data,
+			      enum usbc_port port);
+
+/**
+ * @brief Test TCPCI hard reset re-init callback
+ *
+ * @param emul Pointer to TCPCI emulator
+ * @param common_data Pointer to emulated I2C bus
+ * @param port Select USBC port that will be used to obtain tcpm_drv from
+ *             tcpc_config
+ */
+void test_tcpci_hard_reset_reinit(const struct emul *emul,
+				  struct i2c_common_emul_data *common_data,
+				  enum usbc_port port);
+
+/**
+ * @brief Test TCPCI get vbus voltage callback
+ *
+ * @param emul Pointer to TCPCI emulator
+ * @param common_data Pointer to emulated I2C bus
+ * @param port Select USBC port that will be used to obtain tcpm_drv from
+ *             tcpc_config
+ */
+void test_tcpci_get_vbus_voltage(const struct emul *emul,
+				 struct i2c_common_emul_data *common_data,
+				 enum usbc_port port);
+#endif /* __TCPCI_TEST_COMMON_H */
diff --git a/zephyr/test/drivers/common/include/test/drivers/test_mocks.h b/zephyr/test/drivers/common/include/test/drivers/test_mocks.h
new file mode 100644
index 0000000000..6644de8d88
--- /dev/null
+++ b/zephyr/test/drivers/common/include/test/drivers/test_mocks.h
@@ -0,0 +1,125 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __TEST_DRIVERS_TEST_MOCKS_H
+#define __TEST_DRIVERS_TEST_MOCKS_H
+
+#include <stdint.h>
+
+#include <zephyr/fff.h>
+
+/*
+ * Convenience macros
+ */
+
+/**
+ * @brief  Helper macro for inspecting the argument history of a given
+ *         fake. Counts number of times the fake was called with a given
+ *         argument.
+ * @param  FAKE - FFF-provided fake structure (no pointers).
+ * @param  ARG_NUM - Zero-based index of the argument to compare.
+ * @param  VAL - Expression the argument must equal.
+ * @return Returns the number of times a call was made to the fake
+ *         where the argument `ARG_NUM` equals `VAL`.
+ */
+#define MOCK_COUNT_CALLS_WITH_ARG_VALUE(FAKE, ARG_NUM, VAL)              \
+	({                                                               \
+		int count = 0;                                           \
+		for (int i = 0; i < (FAKE).call_count; i++) {            \
+			if ((FAKE).arg##ARG_NUM##_history[i] == (VAL)) { \
+				count++;                                 \
+			}                                                \
+		}                                                        \
+		count;                                                   \
+	})
+
+/**
+ * @brief  Helper macro for asserting that a certain register write occurred.
+ *         Used when wrapping an I2C emulator mock write function in FFF. Prints
+ *         useful error messages when the assertion fails.
+ * @param  FAKE - name of the fake whose arg history to insepct. Do not include
+ *          '_fake' at the end.
+ * @param  CALL_NUM - Index in to the call history that this write should have
+ *          occurred at. Zero based.
+ * @param  EXPECTED_REG - The register address that was supposed to be written.
+ * @param  EXPECTED_VAL - The 8-bit value that was supposed to be written, or
+ *          `MOCK_IGNORE_VALUE` to suppress this check.
+ */
+#define MOCK_ASSERT_I2C_WRITE(FAKE, CALL_NUM, EXPECTED_REG, EXPECTED_VAL)                   \
+	do {                                                                                \
+		zassert_true((CALL_NUM) < FAKE##_fake.call_count,                           \
+			     "Call #%d did not occur (%d I2C writes total)",                \
+			     (CALL_NUM), FAKE##_fake.call_count);                           \
+		zassert_equal(                                                              \
+			FAKE##_fake.arg1_history[(CALL_NUM)], (EXPECTED_REG),               \
+			"Expected I2C write #%d to register 0x%02x (" #EXPECTED_REG         \
+			") but wrote to reg 0x%02x",                                        \
+			(CALL_NUM), (EXPECTED_REG),                                         \
+			FAKE##_fake.arg1_history[(CALL_NUM)]);                              \
+		if ((EXPECTED_VAL) != MOCK_IGNORE_VALUE) {                                  \
+			zassert_equal(                                                      \
+				FAKE##_fake.arg2_history[(CALL_NUM)],                       \
+				(EXPECTED_VAL),                                             \
+				"Expected I2C write #%d to register 0x%02x (" #EXPECTED_REG \
+				") to write 0x%02x (" #EXPECTED_VAL                         \
+				") but wrote 0x%02x",                                       \
+				(CALL_NUM), (EXPECTED_REG), (EXPECTED_VAL),                 \
+				FAKE##_fake.arg2_history[(CALL_NUM)]);                      \
+		}                                                                           \
+	} while (0)
+
+/** @brief Value to pass to MOCK_ASSERT_I2C_WRITE to ignore the actual value
+ *         written.
+ */
+#define MOCK_IGNORE_VALUE (-1)
+
+/**
+ * @brief  Helper macro for asserting that a certain register read occurred.
+ *         Used when wrapping an I2C emulator mock read function in FFF. Prints
+ *         useful error messages when the assertion fails.
+ * @param  FAKE - name of the fake whose arg history to insepct. Do not include
+ *          '_fake' at the end.
+ * @param  CALL_NUM - Index in to the call history that this write should have
+ *          occurred at. Zero based.
+ * @param  EXPECTED_REG - The register address that was supposed to be read
+ *          from.
+ */
+#define MOCK_ASSERT_I2C_READ(FAKE, CALL_NUM, EXPECTED_REG)                           \
+	do {                                                                         \
+		zassert_true((CALL_NUM) < FAKE##_fake.call_count,                    \
+			     "Call #%d did not occur (%d I2C reads total)",          \
+			     (CALL_NUM), FAKE##_fake.call_count);                    \
+		zassert_equal(                                                       \
+			FAKE##_fake.arg1_history[(CALL_NUM)], (EXPECTED_REG),        \
+			"Expected I2C read #%d from register 0x%02x (" #EXPECTED_REG \
+			") but read from reg 0x%02x",                                \
+			(CALL_NUM), (EXPECTED_REG),                                  \
+			FAKE##_fake.arg1_history[(CALL_NUM)]);                       \
+	} while (0)
+
+/*
+ * Mock declarations
+ */
+
+/* Mocks for common/init_rom.c */
+DECLARE_FAKE_VALUE_FUNC(const void *, init_rom_map, const void *, int);
+DECLARE_FAKE_VOID_FUNC(init_rom_unmap, const void *, int);
+DECLARE_FAKE_VALUE_FUNC(int, init_rom_copy, int, int, int);
+
+/* Mocks for common/system.c */
+DECLARE_FAKE_VALUE_FUNC(int, system_jumped_late);
+DECLARE_FAKE_VALUE_FUNC(int, system_is_locked);
+DECLARE_FAKE_VOID_FUNC(system_reset, int);
+DECLARE_FAKE_VOID_FUNC(software_panic, uint32_t, uint32_t);
+DECLARE_FAKE_VOID_FUNC(assert_post_action, const char *, unsigned int);
+
+/* Mocks for common/lid_angle.c */
+DECLARE_FAKE_VOID_FUNC(lid_angle_peripheral_enable, int);
+
+/* Mocks for gpio.h */
+DECLARE_FAKE_VALUE_FUNC(int, gpio_config_unused_pins);
+DECLARE_FAKE_VALUE_FUNC(int, gpio_configure_port_pin, int, int, int);
+
+#endif /* __TEST_DRIVERS_TEST_MOCKS_H */
diff --git a/zephyr/test/drivers/common/include/test/drivers/test_state.h b/zephyr/test/drivers/common/include/test/drivers/test_state.h
new file mode 100644
index 0000000000..b4496c6af9
--- /dev/null
+++ b/zephyr/test/drivers/common/include/test/drivers/test_state.h
@@ -0,0 +1,27 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef ZEPHYR_TEST_DRIVERS_INCLUDE_TEST_STATE_H_
+#define ZEPHYR_TEST_DRIVERS_INCLUDE_TEST_STATE_H_
+
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct test_state {
+	bool ec_app_main_run;
+};
+
+bool drivers_predicate_pre_main(const void *state);
+
+bool drivers_predicate_post_main(const void *state);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZEPHYR_TEST_DRIVERS_INCLUDE_TEST_STATE_H_ */
diff --git a/zephyr/test/drivers/common/include/test/drivers/utils.h b/zephyr/test/drivers/common/include/test/drivers/utils.h
new file mode 100644
index 0000000000..a123fd640c
--- /dev/null
+++ b/zephyr/test/drivers/common/include/test/drivers/utils.h
@@ -0,0 +1,677 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef ZEPHYR_TEST_DRIVERS_INCLUDE_UTILS_H_
+#define ZEPHYR_TEST_DRIVERS_INCLUDE_UTILS_H_
+
+#include "charger.h"
+#include "emul/tcpc/emul_tcpci_partner_src.h"
+#include "extpower.h"
+#include "host_command.h"
+#include "lpc.h"
+#include "power.h"
+#include "usbc/utils.h"
+
+#include <stddef.h>
+#include <string.h>
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/ztest.h>
+
+/**
+ * @brief Helper macro for EMUL_GET_USBC_BINDING. If @p usbc_id has the same
+ *        port number as @p port, then struct emul* for @p chip phandle is
+ *        returned.
+ *
+ * @param usbc_id Named usbc port ID
+ * @param port Port number to match with named usbc port
+ * @param chip Name of chip phandle property
+ */
+#define EMUL_GET_USBC_BINDING_IF_PORT_MATCH(usbc_id, port, chip) \
+	COND_CODE_1(IS_EQ(USBC_PORT_NEW(usbc_id), port),         \
+		    (EMUL_DT_GET(DT_PHANDLE(usbc_id, chip))), ())
+
+/**
+ * @brief Get struct emul from phandle @p chip property of USBC @p port
+ *
+ * @param port Named usbc port number. The value has to be integer literal.
+ * @param chip Name of chip property that is phandle to required emulator.
+ */
+#define EMUL_GET_USBC_BINDING(port, chip)                                 \
+	DT_FOREACH_STATUS_OKAY_VARGS(named_usbc_port,                     \
+				     EMUL_GET_USBC_BINDING_IF_PORT_MATCH, \
+				     port, chip)
+
+/** @brief Set emulated battery level. Call all necessary hooks. */
+void test_set_battery_level(int percentage);
+
+/** @brief Set chipset to S0 state. Call all necessary hooks. */
+void test_set_chipset_to_s0(void);
+
+/**
+ * @brief Set the chipset to any stable state. Call all necessary hooks.
+ *
+ * Supported states are:
+ * <ul>
+ *   <li>POWER_G3 (same as calling test_set_chipset_to_g3())</li>
+ *   <li>POWER_S5</li>
+ *   <li>POWER_S4</li>
+ *   <li>POWER_S3</li>
+ *   <li>POWER_S0 (same as calling test_set_chipset_to_s0()</li>
+ *   <li>POWER_S0ix (if either CONFIG_PLATFORM_EC_POWERSEQ_S0IX or
+ *       CONFIG_AP_PWRSEQ_S0IX are enabled)</li>
+ * </ul>
+ *
+ * @param new_state The new state. Must be a steady state (see above).
+ */
+void test_set_chipset_to_power_level(enum power_state new_state);
+
+/** @brief Set chipset to G3 state. Call all necessary hooks. */
+void test_set_chipset_to_g3(void);
+
+/**
+ * Run an ACPI read to the specified address.
+ *
+ * This function assumes a successful ACPI read process and will make a
+ * call to the zassert_* API. A failure here will fail the calling test.
+ *
+ * @param acpi_addr Address to query
+ * @return Byte read
+ */
+uint8_t acpi_read(uint8_t acpi_addr);
+
+/**
+ * Run an ACPI write to the specified address.
+ *
+ * This function assumes a successful ACPI write process and will make a
+ * call to the zassert_* API. A failure here will fail the calling test.
+ *
+ * @param acpi_addr Address to write
+ * @param write_byte Byte to write to address
+ */
+void acpi_write(uint8_t acpi_addr, uint8_t write_byte);
+
+/**
+ * Run the host command to gather our EC feature flags.
+ *
+ * This function assumes a successful host command processing and will make a
+ * call to the zassert_* API.  A failure here will fail the calling test.
+ *
+ * @return The result of the host command
+ */
+static inline struct ec_response_get_features host_cmd_get_features(void)
+{
+	struct ec_response_get_features response;
+
+	zassert_ok(ec_cmd_get_features(NULL, &response),
+		   "Failed to get features");
+	return response;
+}
+
+/**
+ * Run the host command to get the charge state for a given charger number.
+ *
+ * This function assumes a successful host command processing and will make a
+ * call to the zassert_* API. A failure here will fail the calling test.
+ *
+ * @param chgnum The charger number to query.
+ * @return The result of the query.
+ */
+static inline struct ec_response_charge_state host_cmd_charge_state(int chgnum)
+{
+	struct ec_params_charge_state params = {
+		.chgnum = chgnum,
+		.cmd = CHARGE_STATE_CMD_GET_STATE,
+	};
+	struct ec_response_charge_state response;
+
+	zassert_ok(ec_cmd_charge_state(NULL, &params, &response),
+		   "Failed to get charge state for chgnum %d", chgnum);
+	return response;
+}
+
+/**
+ * Run the host command to get the USB PD power info for a given port.
+ *
+ * This function assumes a successful host command processing and will make a
+ * call to the zassert_* API. A failure here will fail the calling test.
+ *
+ * @param port The USB port to get info from.
+ * @return The result of the query.
+ */
+static inline struct ec_response_usb_pd_power_info host_cmd_power_info(int port)
+{
+	struct ec_params_usb_pd_power_info params = { .port = port };
+	struct ec_response_usb_pd_power_info response;
+
+	zassert_ok(ec_cmd_usb_pd_power_info(NULL, &params, &response),
+		   "Failed to get power info for port %d", port);
+	return response;
+}
+
+/**
+ * Run the host command to get the Type-C status information for a given port.
+ *
+ * This function assumes a successful host command processing and will make a
+ * call to the zassert_* API. A failure here will fail the calling test.
+ *
+ * @param port The USB port to get info from.
+ * @return The result of the query.
+ */
+static inline struct ec_response_typec_status host_cmd_typec_status(int port)
+{
+	struct ec_params_typec_status params = { .port = port };
+	struct ec_response_typec_status response;
+
+	zassert_ok(ec_cmd_typec_status(NULL, &params, &response),
+		   "Failed to get Type-C state for port %d", port);
+	return response;
+}
+
+/**
+ * Run the host command to get the most recent VDM response for the AP
+ *
+ * This function asserts a successful host command processing and will make a
+ * call to the zassert_* API. A failure here will fail the calling test.
+ *
+ * @param port The USB port to get info from.
+ * @return The result of the query.
+ */
+struct ec_response_typec_vdm_response host_cmd_typec_vdm_response(int port);
+
+static inline struct ec_response_usb_pd_control
+host_cmd_usb_pd_control(int port, enum usb_pd_control_swap swap)
+{
+	struct ec_params_usb_pd_control params = { .port = port, .swap = swap };
+	struct ec_response_usb_pd_control response;
+
+	zassert_ok(ec_cmd_usb_pd_control(NULL, &params, &response),
+		   "Failed to process usb_pd_control_swap for port %d, swap %d",
+		   port, swap);
+	return response;
+}
+
+/**
+ * Run the host command to suspend/resume PD ports
+ *
+ * This function assumes a successful host command processing and will make a
+ * call to the zassert_* API. A failure here will fail the calling test.
+ *
+ * @param port The USB port to operate on
+ * @param cmd The sub-command to run
+ */
+static inline void host_cmd_pd_control(int port, enum ec_pd_control_cmd cmd)
+{
+	struct ec_params_pd_control params = { .chip = port, .subcmd = cmd };
+
+	zassert_ok(ec_cmd_pd_control(NULL, &params),
+		   "Failed to process pd_control for port %d, cmd %d", port,
+		   cmd);
+}
+
+/**
+ * Run the host command to control or query the charge state
+ *
+ * @return The result of the query.
+ */
+static inline struct ec_response_charge_control
+host_cmd_charge_control(enum ec_charge_control_mode mode,
+			enum ec_charge_control_cmd cmd)
+{
+	struct ec_params_charge_control params = { .cmd = cmd,
+						   .mode = mode,
+						   .sustain_soc = {
+							   .lower = -1,
+							   .upper = -1,
+						   } };
+	struct ec_response_charge_control response;
+
+	zassert_ok(ec_cmd_charge_control_v2(NULL, &params, &response),
+		   "Failed to get charge control values");
+
+	return response;
+}
+
+/**
+ * @brief Call the host command HOST_EVENT with the user supplied action.
+ *
+ * @param action    - HOST_EVENT action parameter.
+ * @param mask_type - Event mask type to apply to the HOST_EVENT action.
+ * @param r         - Pointer to the response object to fill.
+ */
+enum ec_status host_cmd_host_event(enum ec_host_event_action action,
+				   enum ec_host_event_mask_type mask_type,
+				   struct ec_response_host_event *r);
+
+/**
+ * @brief Call the host command MOTION_SENSE with the dump sub-command
+ *
+ * Note: this function uses the zassert_ API. It will fail the test if the host
+ * command fails.
+ *
+ * @param max_sensor_count The maximum number of sensor data objects to populate
+ *        in the response object.
+ * @param response Pointer to the response object to fill.
+ * @param response_size Size of the response buffer.
+ */
+void host_cmd_motion_sense_dump(int max_sensor_count,
+				struct ec_response_motion_sense *response,
+				size_t response_size);
+
+/**
+ * @brief Call the host command MOTION_SENSE with the data sub-command
+ *
+ * @param sensor_num The sensor index in the motion_sensors array to query
+ * @param response Pointer to the response data structure to fill on success
+ * @return The result code from the host command
+ */
+int host_cmd_motion_sense_data(uint8_t sensor_num,
+			       struct ec_response_motion_sense *response);
+
+/**
+ * @brief Call the host command MOTION_SENSE with the info sub-command
+ *
+ * @param cmd_version The command version
+ * @param sensor_num The sensor index in the motion_sensors array to query
+ * @param response Pointer to the response data structure to fill on success
+ * @return The result code from the host command
+ */
+int host_cmd_motion_sense_info(uint8_t cmd_version, uint8_t sensor_num,
+			       struct ec_response_motion_sense *response);
+
+/**
+ * @brief Call the host command MOTION_SENSE with the ec_rate sub-command
+ *
+ * This function performs a read of the current rate by passing
+ * EC_MOTION_SENSE_NO_VALUE as the data rate. Otherwise, the data rate should be
+ * updated.
+ *
+ * @param sensor_num The sensor index in the motion_sensors array to query
+ * @param data_rate_ms The new data rate or EC_MOTION_SENSE_NO_VALUE to read
+ * @param response Pointer to the response data structure to fill on success
+ * @return The result code from the host command
+ */
+int host_cmd_motion_sense_ec_rate(uint8_t sensor_num, int data_rate_ms,
+				  struct ec_response_motion_sense *response);
+
+/**
+ * @brief Call the host command MOTION_SENSE with the odr sub-command
+ *
+ * This function performs a read of the current odr by passing
+ * EC_MOTION_SENSE_NO_VALUE as the data rate. Otherwise, the data rate should be
+ * updated.
+ *
+ * @param sensor_num The sensor index in the motion_sensors array to query
+ * @param odr The new ODR to set
+ * @param round_up Whether or not to round up the ODR
+ * @param response Pointer to the response data structure to fill on success
+ * @return The result code form the host command
+ */
+int host_cmd_motion_sense_odr(uint8_t sensor_num, int32_t odr, bool round_up,
+			      struct ec_response_motion_sense *response);
+
+/**
+ * @brief Call the host command MOTION_SENSE with the sensor range sub-command
+ *
+ * This function attempts to set the sensor range and returns the range value.
+ * If the range value is EC_MOTION_SENSE_NO_VALUE, then the host command will
+ * not attempt to update the range.
+ *
+ * @param sensor_num The sensor index in the motion_sensors array to query
+ * @param range The new range to set
+ * @param round_up Whether or not to round up the range.
+ * @param response Pointer to the response data structure to fill on success
+ * @return The result code from the host command
+ */
+int host_cmd_motion_sense_range(uint8_t sensor_num, int32_t range,
+				bool round_up,
+				struct ec_response_motion_sense *response);
+
+/**
+ * @brief Call the host command MOTION_SENSE with the sensor offset sub-command
+ *
+ * This function attempts to set the offset if the flags field includes
+ * MOTION_SENSE_SET_OFFSET. Otherwise, the temperature and offsets are ignored.
+ * The response field will include the current (after modification) offsets and
+ * temperature.
+ *
+ * @param sensor_num The sensor index in the motion_sensors array to query
+ * @param flags The flags to pass to the host command
+ * @param temperature The temperature at which the offsets were attained (set)
+ * @param offset_x The X offset to set
+ * @param offset_y The Y offset to set
+ * @param offset_z The Z offset to set
+ * @param response Pointer to the response data structure to fill on success
+ * @return The result code from the host command
+ */
+int host_cmd_motion_sense_offset(uint8_t sensor_num, uint16_t flags,
+				 int16_t temperature, int16_t offset_x,
+				 int16_t offset_y, int16_t offset_z,
+				 struct ec_response_motion_sense *response);
+
+/**
+ * @brief Call the host command MOTION_SENSE with the sensor scale sub-command
+ *
+ * This function attempts to set the scale if the flags field includes
+ * MOTION_SENSE_SET_OFFSET. Otherwise, the temperature and scales are ignored.
+ * The response field will include the current (after modification) scales and
+ * temperature.
+ *
+ * @param sensor_num The sensor index in the motion_sensors array to query
+ * @param flags The flags to pass to the host command
+ * @param temperature The temperature at which the scales were attained (set)
+ * @param scale_x The X scale to set
+ * @param scale_y The Y scale to set
+ * @param scale_z The Z scale to set
+ * @param response Pointer to the response data structure to fill on success
+ * @return The result code from the host command
+ */
+int host_cmd_motion_sense_scale(uint8_t sensor_num, uint16_t flags,
+				int16_t temperature, int16_t scale_x,
+				int16_t scale_y, int16_t scale_z,
+				struct ec_response_motion_sense *response);
+
+/**
+ * @brief Enable/disable sensor calibration via host command
+ *
+ * @param sensor_num The sensor index in the motion_sensors array to query
+ * @param enable Whether to enable or disable the calibration
+ * @param response Pointer to the response data structure to fill on success
+ * @return The result code from the host command
+ */
+int host_cmd_motion_sense_calib(uint8_t sensor_num, bool enable,
+				struct ec_response_motion_sense *response);
+
+/**
+ * @brief Set the sensor's fifo flush bit
+ *
+ * @param sensor_num The sensor index in the motion_sensors array to query
+ * @param response Pointer to the response data structure to fill on success
+ * @param response_size Size of the response buffer.
+ * @return The result code from the host command
+ */
+int host_cmd_motion_sense_fifo_flush(uint8_t sensor_num,
+				     struct ec_response_motion_sense *response,
+				     size_t response_size);
+
+/**
+ * @brief Get the current fifo info
+ *
+ * @param response Pointer to the response data structure to fill on success
+ * @param response_size Size of the response buffer.
+ * @return The result code from the host command
+ */
+int host_cmd_motion_sense_fifo_info(struct ec_response_motion_sense *response,
+				    size_t response_size);
+
+/**
+ * @brief Get the current fifo data
+ *
+ * @param buffer_length The number of entries available on the response pointer
+ * @param response Pointer to the response data structure to fill on success
+ * @return The result code from the host command
+ */
+int host_cmd_motion_sense_fifo_read(uint8_t buffer_length,
+				    struct ec_response_motion_sense *response);
+
+/**
+ * @brief Call the int_enable motionsense host command
+ *
+ * @param enable 0 for disable, 1 for enable. All others are invalid
+ * @param response Pointer to the response data structure to fill on success
+ * @return The result code from the host command
+ */
+int host_cmd_motion_sense_int_enable(int8_t enable,
+				     struct ec_response_motion_sense *response);
+
+/**
+ * @brief Call the spoof motion_sense subcommand
+ *
+ * @param sensor_num The sensor index in motion_sensors
+ * @param enable The enable field, for normal operations this will be one of
+ * enum motionsense_spoof_mode
+ * @param values0 The X value to set if using custom mode
+ * @param values1 The Y value to set if using custom mode
+ * @param values2 The Z value to set if using custom mode
+ * @param response Pointer to the response data structure to fill on success
+ * @return The result code from the host command
+ */
+int host_cmd_motion_sense_spoof(uint8_t sensor_num, uint8_t enable,
+				int16_t values0, int16_t values1,
+				int16_t values2,
+				struct ec_response_motion_sense *response);
+
+/**
+ * @brief Call the keyboard wake angle motion_sense subcommand
+ *
+ * @param data Angle to set
+ * @param response Pointer to the response data structure to fill on success
+ * @return The result code from the host command
+ */
+int host_cmd_motion_sense_kb_wake_angle(
+	int16_t data, struct ec_response_motion_sense *response);
+
+/**
+ * @brief Call the lid angle motion_sense subcommand
+ *
+ * @param response Pointer to the response data structure to fill on success
+ * @return The result code from the host command
+ */
+int host_cmd_motion_sense_lid_angle(struct ec_response_motion_sense *response);
+
+/**
+ * @brief Call the tablet mode lid angle threshold motion_sense subcommand
+ *
+ * @param lid_angle Lid angle for transitioning to tablet mode
+ * @param hys_degree Hysteresis or above transition
+ * @param response Pointer to the response data structure to fill on success
+ * @return The result code from the host command
+ */
+int host_cmd_motion_sense_tablet_mode_lid_angle(
+	int16_t lid_angle, int16_t hys_degree,
+	struct ec_response_motion_sense *response);
+
+/**
+ * Run the host command to get the PD discovery responses.
+ *
+ * @param port          The USB-C port number
+ * @param partner_type  SOP, SOP', or SOP''
+ * @param response      Destination buffer for command response;
+ *                      should hold struct ec_response_typec_discovery and
+ *                      enough struct svid_mode_info for expected response.
+ * @param response_size Number of bytes in response
+ */
+void host_cmd_typec_discovery(int port, enum typec_partner_type partner_type,
+			      void *response, size_t response_size);
+
+/**
+ * Run the host command to control PD port behavior, with the sub-command of
+ * TYPEC_CONTROL_COMMAND_ENTER_MODE
+ *
+ * @param port	The USB-C port number
+ * @param mode	Mode to enter
+ */
+void host_cmd_typec_control_enter_mode(int port, enum typec_mode mode);
+
+/**
+ * Run the host command to control PD port behavior, with the sub-command of
+ * TYPEC_CONTROL_COMMAND_EXIT_MODES
+ *
+ * @param port      The USB-C port number
+ */
+void host_cmd_typec_control_exit_modes(int port);
+
+/**
+ * Run the host command to control PD port behavior, with the sub-command of
+ * TYPEC_CONTROL_COMMAND_USB_MUX_SET
+ *
+ * @param port		The USB-C port number
+ * @param mux_set	Mode and mux index to set
+ */
+void host_cmd_typec_control_usb_mux_set(int port,
+					struct typec_usb_mux_set mux_set);
+
+/**
+ * Run the host command to control PD port behavior, with the sub-command of
+ * TYPEC_CONTROL_COMMAND_CLEAR_EVENTS
+ *
+ * @param port		The USB-C port number
+ * @param events	Events to clear for the port (see PD_STATUS_EVENT_*
+ *			definitions for options)
+ */
+void host_cmd_typec_control_clear_events(int port, uint32_t events);
+
+/**
+ * Run the host command to control PD port behavior, with the sub-command of
+ * TYPEC_CONTROL_COMMAND_BIST_SHARE_MODE
+ *
+ * @param port		The USB-C port number
+ * @param enable	enable bist share mode or not
+ */
+void host_cmd_typec_control_bist_share_mode(int port, int enable);
+
+/**
+ * Run the host command to control PD port behavior, with the sub-command of
+ * TYPEC_CONTROL_COMMAND_SEND_VDM_REQ
+ *
+ * @param port		The USB-C port number
+ * @param vdm_req	VDM request data
+ */
+void host_cmd_typec_control_vdm_req(int port, struct typec_vdm_req vdm_req);
+
+struct host_events_ctx {
+	host_event_t lpc_host_events;
+	host_event_t lpc_host_event_mask[LPC_HOST_EVENT_COUNT];
+};
+
+/**
+ * Save all host events. This should be run as part of the "before" action for
+ * any test suite that manipulates the host events.
+ *
+ * @param host_events_ctx	Caller allocated storage to save the host
+ *				events.
+ */
+void host_events_save(struct host_events_ctx *host_events_ctx);
+
+/**
+ * Restore all host events. This should be run as part of the "after" action for
+ * any test suite that manipulates the host events.
+ *
+ * @param host_events_ctx	Saved host events context information.
+ */
+void host_events_restore(struct host_events_ctx *host_events_ctx);
+
+#define GPIO_ACOK_OD_NODE DT_NODELABEL(gpio_acok_od)
+#define GPIO_ACOK_OD_PIN DT_GPIO_PIN(GPIO_ACOK_OD_NODE, gpios)
+
+/**
+ * Set whether or not AC is enabled.
+ *
+ * If enabled, the device _should_ begin charging.
+ *
+ * This function assumes a successful gpio emulator call and will make a call
+ * to the zassert_* API. A failure here will fail the calling test.
+ *
+ * This function sleeps to wait for the GPIO interrupt to take place.
+ *
+ * @param enabled Whether or not to enable AC.
+ */
+static inline void set_ac_enabled(bool enabled)
+{
+	const struct device *acok_dev =
+		DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_ACOK_OD_NODE, gpios));
+
+	zassert_ok(gpio_emul_input_set(acok_dev, GPIO_ACOK_OD_PIN, enabled),
+		   NULL);
+	/*
+	 * b/253284635 - Sleep for a full second past the debounce time
+	 * to ensure the power button debounce logic runs.
+	 */
+	k_sleep(K_MSEC(CONFIG_EXTPOWER_DEBOUNCE_MS + 1000));
+	zassert_equal(enabled, extpower_is_present(), NULL);
+}
+
+/**
+ * @brief Connect a power source to a given port.
+ *
+ * Note: this is function currently only supports an ISL923X charger chip.
+ *
+ * @param partner Pointer to the emulated TCPCI partner device
+ * @param src Pointer to the emulated source extension
+ * @param pdo_index The index of the PDO object within the src to use
+ * @param tcpci_emul The TCPCI emulator that the source will connect to
+ * @param charger_emul The charger chip emulator
+ */
+void connect_source_to_port(struct tcpci_partner_data *partner,
+			    struct tcpci_src_emul_data *src, int pdo_index,
+			    const struct emul *tcpci_emul,
+			    const struct emul *charger_emul);
+
+/**
+ * @brief Disconnect a power source from a given port.
+ *
+ * Note: this is function currently only supports an ISL923X charger chip.
+ *
+ * @param tcpci_emul The TCPCI emulator that will be disconnected
+ * @param charger_emul The charger chip emulator
+ */
+void disconnect_source_from_port(const struct emul *tcpci_emul,
+				 const struct emul *charger_emul);
+
+/**
+ * @brief Connect a power sink to a given port.
+ *
+ * Note: this is function currently only supports an ISL923X charger chip.
+ *
+ * @param partner Pointer to the emulated TCPCI partner device
+ * @param tcpci_emul The TCPCI emulator that the source will connect to
+ * @param charger_emul The charger chip emulator
+ */
+void connect_sink_to_port(struct tcpci_partner_data *partner,
+			  const struct emul *tcpci_emul,
+			  const struct emul *charger_emul);
+
+/**
+ * @brief Disconnect a power sink from a given port.
+ *
+ * @param tcpci_emul The TCPCI emulator that will be disconnected
+ */
+void disconnect_sink_from_port(const struct emul *tcpci_emul);
+
+/**
+ * @brief Allocate memory for a test pourpose
+ *
+ * @param bytes Number of bytes to allocate
+ *
+ * @return Pointer to valid memory or NULL
+ */
+void *test_malloc(size_t bytes);
+
+/**
+ * @brief Free memory allocated by @ref test_malloc
+ *
+ * @param mem Pointer to the memory
+ */
+void test_free(void *mem);
+
+/**
+ * @brief Force the chipset to state G3 and then transition to S3 and finally
+ * S5.
+ *
+ */
+void test_set_chipset_to_g3_then_transition_to_s5(void);
+
+/**
+ * @brief Checks console command with expected console output and expected
+ * return value
+ *
+ */
+#define CHECK_CONSOLE_CMD(cmd, expected_output, expected_rv)                 \
+	check_console_cmd((cmd), (expected_output), (expected_rv), __FILE__, \
+			  __LINE__)
+void check_console_cmd(const char *cmd, const char *expected_output,
+		       const int expected_rv, const char *file, const int line);
+#endif /* ZEPHYR_TEST_DRIVERS_INCLUDE_UTILS_H_ */
diff --git a/zephyr/test/drivers/common/src/main.c b/zephyr/test/drivers/common/src/main.c
new file mode 100644
index 0000000000..dab681b936
--- /dev/null
+++ b/zephyr/test/drivers/common/src/main.c
@@ -0,0 +1,64 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_app_main.h"
+#include "hooks.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+/**
+ * @brief Semaphore that signals when hooks have completed
+ */
+static struct k_sem init_hooks_completed;
+
+/**
+ * @brief Hook callback function. Gets registered with the lowest priority so
+ *        that we know all actual hooks have finished. Increments the semaphore.
+ */
+static void hook_completed_callback(void)
+{
+	/* Signal that hooks are completed */
+	k_sem_give(&init_hooks_completed);
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, hook_completed_callback, HOOK_PRIO_LAST);
+
+bool drivers_predicate_pre_main(const void *state)
+{
+	return ((struct test_state *)state)->ec_app_main_run == false;
+}
+
+bool drivers_predicate_post_main(const void *state)
+{
+	return !drivers_predicate_pre_main(state);
+}
+
+void test_main(void)
+{
+	k_sem_init(&init_hooks_completed, 0, 1);
+
+	struct test_state state = {
+		.ec_app_main_run = false,
+	};
+
+	/* Run all the suites that depend on main not being called yet */
+	ztest_run_all(&state);
+
+	ec_app_main();
+	state.ec_app_main_run = true;
+
+/* Delay the post-main tests until hooks finish. Allow a generous
+ * timeout before failing. Tests with mocked power states interfere
+ * with this mechanism, so proceed normally in this case.
+ */
+#if !IS_ENABLED(CONFIG_POWER_SEQUENCE_MOCK)
+	zassert_ok(k_sem_take(&init_hooks_completed, K_SECONDS(10)),
+		   "Timed out waiting for hooks to finish");
+#endif /* !IS_ENABLED(CONFIG_POWER_SEQUENCE_MOCK) */
+
+	/* Run all the suites that depend on main being called */
+	ztest_run_all(&state);
+}
diff --git a/zephyr/test/drivers/common/src/stubs.c b/zephyr/test/drivers/common/src/stubs.c
new file mode 100644
index 0000000000..c623b95a82
--- /dev/null
+++ b/zephyr/test/drivers/common/src/stubs.c
@@ -0,0 +1,258 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "battery_fuel_gauge.h"
+#include "bc12/pi3usb9201_public.h"
+#include "charge_ramp.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "charger/isl923x_public.h"
+#include "charger/isl9241_public.h"
+#include "config.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "i2c/i2c.h"
+#include "power.h"
+#include "ppc/sn5s330_public.h"
+#include "ppc/syv682x_public.h"
+#include "retimer/bb_retimer_public.h"
+#include "tcpm/ps8xxx_public.h"
+#include "tcpm/tcpci.h"
+#include "test/drivers/stubs.h"
+#include "usb_mux.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_ppc.h"
+
+#include <zephyr/fff.h>
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(stubs);
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/* All of these definitions are just to get the test to link. None of these
+ * functions are useful or behave as they should. Please remove them once the
+ * real code is able to be added.  Most of the things here should either be
+ * in emulators or in the native_posix board-specific code or part of the
+ * device tree.
+ */
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int i;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTS("Disabling all charging port");
+
+		/* Disable all ports. */
+		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (board_vbus_sink_enable(i, 0))
+				CPRINTS("Disabling p%d sink path failed.", i);
+		}
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (board_is_sourcing_vbus(port)) {
+		CPRINTS("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTS("New charge port: p%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		if (i == port)
+			continue;
+
+		if (board_vbus_sink_enable(i, 0))
+			CPRINTS("p%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (board_vbus_sink_enable(port, 1)) {
+		CPRINTS("p%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
+{
+	return 0;
+}
+
+BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
+
+static uint16_t ps8xxx_product_id = PS8805_PRODUCT_ID;
+
+uint16_t board_get_ps8xxx_product_id(int port)
+{
+	if (tcpc_config[port].drv == &ps8xxx_tcpm_drv) {
+		return ps8xxx_product_id;
+	}
+
+	return 0;
+}
+
+void board_set_ps8xxx_product_id(uint16_t product_id)
+{
+	ps8xxx_product_id = product_id;
+}
+
+int board_vbus_sink_enable(int port, int enable)
+{
+	/* Both ports are controlled by PPC SN5S330 */
+	return ppc_vbus_sink_enable(port, enable);
+}
+
+int board_is_sourcing_vbus(int port)
+{
+	/* Both ports are controlled by PPC SN5S330 */
+	return ppc_is_sourcing_vbus(port);
+}
+
+void pd_power_supply_reset(int port)
+{
+}
+
+int pd_check_vconn_swap(int port)
+{
+	return !chipset_in_state(CHIPSET_STATE_HARD_OFF);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	return EC_SUCCESS;
+}
+
+DEFINE_FAKE_VOID_FUNC(system_hibernate, uint32_t, uint32_t);
+
+DEFINE_FAKE_VOID_FUNC(board_reset_pd_mcu);
+
+#ifndef CONFIG_PLATFORM_EC_TCPC_INTERRUPT
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	/*
+	 * Check which port has the ALERT line set and ignore if that TCPC has
+	 * its reset line active.
+	 */
+	if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(usb_c0_tcpc_int_odl))) {
+		if (gpio_pin_get_dt(
+			    GPIO_DT_FROM_NODELABEL(usb_c0_tcpc_rst_l)) == 0)
+			status |= PD_STATUS_TCPC_ALERT_0;
+	}
+
+	if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(usb_c1_tcpc_int_odl))) {
+		if (gpio_pin_get_dt(
+			    GPIO_DT_FROM_NODELABEL(usb_c1_tcpc_rst_l)) == 0)
+			status |= PD_STATUS_TCPC_ALERT_1;
+	}
+
+	return status;
+}
+#endif
+
+void ppc_alert(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_SIGNAL(DT_NODELABEL(gpio_usb_c0_ppc_int)):
+		ppc_chips[USBC_PORT_C0].drv->interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_SIGNAL(DT_NODELABEL(gpio_usb_c1_ppc_int)):
+		ppc_chips[USBC_PORT_C1].drv->interrupt(USBC_PORT_C1);
+		break;
+	default:
+		return;
+	}
+}
+
+/* TODO: This code should really be generic, and run based on something in
+ * the dts.
+ */
+static void stubs_interrupt_init(void)
+{
+	cprints(CC_USB, "Resetting TCPCs...");
+	cflush();
+
+#if !(CONFIG_PLATFORM_EC_TCPC_INTERRUPT)
+	/* Enable TCPC interrupts. */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0));
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1));
+#endif
+
+	/* Reset generic TCPCI on port 0. */
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(usb_c0_tcpc_rst_l), 1);
+	msleep(1);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(usb_c0_tcpc_rst_l), 0);
+
+	/* Reset PS8XXX on port 1. */
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(usb_c1_tcpc_rst_l), 1);
+	msleep(PS8XXX_RESET_DELAY_MS);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(usb_c1_tcpc_rst_l), 0);
+
+	/* Enable PPC interrupts. */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_ppc));
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_ppc));
+
+	/* Enable SwitchCap interrupt */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_switchcap_pg));
+}
+DECLARE_HOOK(HOOK_INIT, stubs_interrupt_init, HOOK_PRIO_POST_I2C);
+
+void board_set_switchcap_power(int enable)
+{
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_switchcap_on), enable);
+	/* TODO(b/217554681): So, the ln9310 emul should probably be setting
+	 * this instead of setting it here.
+	 */
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_src_vph_pwr_pg), enable);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_mb_power_good), enable);
+}
+
+int board_is_switchcap_enabled(void)
+{
+	return gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_switchcap_on));
+}
+
+int board_is_switchcap_power_good(void)
+{
+	return gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_src_vph_pwr_pg));
+}
+
+void sys_arch_reboot(int type)
+{
+	ARG_UNUSED(type);
+}
+
+/* GPIO TEST interrupt handler */
+bool gpio_test_interrupt_triggered;
+void gpio_test_interrupt(enum gpio_signal signal)
+{
+	ARG_UNUSED(signal);
+	printk("%s called\n", __func__);
+	gpio_test_interrupt_triggered = true;
+}
+
+int clock_get_freq(void)
+{
+	return 16000000;
+}
diff --git a/zephyr/test/drivers/common/src/test_mocks.c b/zephyr/test/drivers/common/src/test_mocks.c
new file mode 100644
index 0000000000..21cd4c0c1b
--- /dev/null
+++ b/zephyr/test/drivers/common/src/test_mocks.c
@@ -0,0 +1,51 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "test/drivers/test_mocks.h"
+
+#include <zephyr/ztest.h>
+
+/* Mocks for common/init_rom.c */
+DEFINE_FAKE_VALUE_FUNC(const void *, init_rom_map, const void *, int);
+DEFINE_FAKE_VOID_FUNC(init_rom_unmap, const void *, int);
+DEFINE_FAKE_VALUE_FUNC(int, init_rom_copy, int, int, int);
+
+/* Mocks for common/system.c */
+DEFINE_FAKE_VALUE_FUNC(int, system_jumped_late);
+DEFINE_FAKE_VALUE_FUNC(int, system_is_locked);
+DEFINE_FAKE_VOID_FUNC(system_reset, int);
+DEFINE_FAKE_VOID_FUNC(software_panic, uint32_t, uint32_t);
+DEFINE_FAKE_VOID_FUNC(assert_post_action, const char *, unsigned int);
+
+/* Mocks for common/lid_angle.c */
+DEFINE_FAKE_VOID_FUNC(lid_angle_peripheral_enable, int);
+
+/* Mocks for gpio.h */
+DEFINE_FAKE_VALUE_FUNC(int, gpio_config_unused_pins);
+DEFINE_FAKE_VALUE_FUNC(int, gpio_configure_port_pin, int, int, int);
+
+/**
+ * @brief Reset all the fakes before each test.
+ */
+static void fff_reset_rule_before(const struct ztest_unit_test *test,
+				  void *data)
+{
+	ARG_UNUSED(test);
+	ARG_UNUSED(data);
+
+	RESET_FAKE(init_rom_map);
+	RESET_FAKE(init_rom_unmap);
+	RESET_FAKE(init_rom_copy);
+	RESET_FAKE(system_jumped_late);
+	RESET_FAKE(system_is_locked);
+	RESET_FAKE(system_reset);
+	RESET_FAKE(software_panic);
+	RESET_FAKE(assert_post_action);
+	RESET_FAKE(lid_angle_peripheral_enable);
+	RESET_FAKE(gpio_config_unused_pins);
+	RESET_FAKE(gpio_configure_port_pin);
+}
+
+ZTEST_RULE(fff_reset_rule, fff_reset_rule_before, NULL);
diff --git a/zephyr/test/drivers/common/src/test_rules.c b/zephyr/test/drivers/common/src/test_rules.c
new file mode 100644
index 0000000000..42195b25d7
--- /dev/null
+++ b/zephyr/test/drivers/common/src/test_rules.c
@@ -0,0 +1,38 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "emul/tcpc/emul_tcpci.h"
+#include "motion_sense_fifo.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/utils.h"
+#include "usb_pd_tcpm.h"
+
+#include <zephyr/ztest.h>
+
+static void motion_sense_fifo_reset_before(const struct ztest_unit_test *test,
+					   void *data)
+{
+	ARG_UNUSED(test);
+	ARG_UNUSED(data);
+	motion_sense_fifo_reset();
+}
+ZTEST_RULE(motion_sense_fifo_reset, motion_sense_fifo_reset_before, NULL);
+
+static void tcpci_revision_reset_before(const struct ztest_unit_test *test,
+					void *data)
+{
+	ARG_UNUSED(test);
+	ARG_UNUSED(data);
+	const struct emul *tcpc_c0_emul = EMUL_GET_USBC_BINDING(0, tcpc);
+	const struct emul *tcpc_c1_emul = EMUL_GET_USBC_BINDING(1, tcpc);
+
+	/* Set TCPCI to revision 2 for both emulators */
+	tcpc_config[USBC_PORT_C0].flags |= TCPC_FLAGS_TCPCI_REV2_0;
+	tcpci_emul_set_rev(tcpc_c0_emul, TCPCI_EMUL_REV2_0_VER1_1);
+
+	tcpc_config[USBC_PORT_C1].flags |= TCPC_FLAGS_TCPCI_REV2_0;
+	tcpci_emul_set_rev(tcpc_c1_emul, TCPCI_EMUL_REV2_0_VER1_1);
+}
+ZTEST_RULE(tcpci_revision_reset, tcpci_revision_reset_before, NULL);
diff --git a/zephyr/test/drivers/common/src/utils.c b/zephyr/test/drivers/common/src/utils.c
new file mode 100644
index 0000000000..f8a75fca97
--- /dev/null
+++ b/zephyr/test/drivers/common/src/utils.c
@@ -0,0 +1,678 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "acpi.h"
+#include "battery.h"
+#include "battery_smart.h"
+#include "charge_state.h"
+#include "chipset.h"
+#include "emul/emul_isl923x.h"
+#include "emul/emul_smart_battery.h"
+#include "emul/emul_stub_device.h"
+#include "emul/tcpc/emul_tcpci_partner_src.h"
+#include "hooks.h"
+#include "lpc.h"
+#include "power.h"
+#include "task.h"
+#include "tcpm/tcpci.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/kernel.h>
+#include <zephyr/shell/shell.h>
+#include <zephyr/shell/shell_dummy.h>
+#include <zephyr/shell/shell_uart.h>
+#include <zephyr/ztest.h>
+
+#define BATTERY_NODE DT_NODELABEL(battery)
+#define GPIO_BATT_PRES_ODL_PATH NAMED_GPIOS_GPIO_NODE(ec_batt_pres_odl)
+#define GPIO_BATT_PRES_ODL_PORT DT_GPIO_PIN(GPIO_BATT_PRES_ODL_PATH, gpios)
+
+void test_set_battery_level(int percentage)
+{
+	struct sbat_emul_bat_data *bat;
+	const struct emul *emul = EMUL_DT_GET(BATTERY_NODE);
+	const struct device *battery_gpio_dev =
+		DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_BATT_PRES_ODL_PATH, gpios));
+	bat = sbat_emul_get_bat_data(emul);
+
+	bat->cap = bat->full_cap * percentage / 100;
+	bat->volt = battery_get_info()->voltage_normal;
+	bat->design_mv = bat->volt;
+
+	/* Set battery present gpio. */
+	zassert_ok(gpio_emul_input_set(battery_gpio_dev,
+				       GPIO_BATT_PRES_ODL_PORT, 0),
+		   NULL);
+
+	/* We need to wait for the charge task to re-read battery parameters */
+	WAIT_FOR(!charge_want_shutdown(), CHARGE_MAX_SLEEP_USEC + 1,
+		 k_sleep(K_SECONDS(1)));
+}
+
+void test_set_chipset_to_s0(void)
+{
+	printk("%s: Forcing power on\n", __func__);
+
+	task_wake(TASK_ID_CHIPSET);
+	k_sleep(K_SECONDS(1));
+
+	/*
+	 * Make sure that battery is in good condition to
+	 * not trigger hibernate in charge_state.c
+	 * Set battery voltage to expected value and capacity to 50%. Battery
+	 * will not be full and accepts charging, but will not trigger
+	 * hibernate. Charge level is set to the default value of an emulator
+	 * (emul/emul_smart_battery.c). b/244366201.
+	 */
+	test_set_battery_level(50);
+
+	/* The easiest way to power on seems to be the shell command. */
+	zassert_equal(EC_SUCCESS, shell_execute_cmd(get_ec_shell(), "power on"),
+		      NULL);
+
+	k_sleep(K_SECONDS(1));
+
+	/* Check if chipset is in correct state */
+	zassert_equal(POWER_S0, power_get_state(), "Expected S0, got %d",
+		      power_get_state());
+}
+
+void test_set_chipset_to_power_level(enum power_state new_state)
+{
+	zassert_true(new_state == POWER_G3 || new_state == POWER_S5 ||
+			     new_state == POWER_S4 || new_state == POWER_S3 ||
+			     new_state == POWER_S0
+#ifdef CONFIG_POWER_S0IX
+			     || new_state == POWER_S0ix
+#endif
+		     ,
+		     "Power state must be one of the steady states");
+	task_wake(TASK_ID_CHIPSET);
+	k_sleep(K_SECONDS(1));
+
+	if (new_state == POWER_G3) {
+		test_set_chipset_to_g3();
+		return;
+	}
+
+	test_set_chipset_to_s0();
+
+	power_set_state(new_state);
+
+	k_sleep(K_SECONDS(1));
+
+	/* Check if chipset is in correct state */
+	zassert_equal(new_state, power_get_state(), "Expected %d, got %d",
+		      new_state, power_get_state());
+}
+
+void test_set_chipset_to_g3(void)
+{
+	/* Let power code to settle on a particular state first. */
+	task_wake(TASK_ID_CHIPSET);
+	k_sleep(K_SECONDS(1));
+
+	printk("%s: Forcing shutdown\n", __func__);
+	chipset_force_shutdown(CHIPSET_RESET_KB_SYSRESET);
+	k_sleep(K_SECONDS(20));
+	/* Check if chipset is in correct state */
+	zassert_equal(POWER_G3, power_get_state(), "Expected G3, got %d",
+		      power_get_state());
+}
+
+#if DT_HAS_COMPAT_STATUS_OKAY(cros_isl923x_emul)
+void connect_source_to_port(struct tcpci_partner_data *partner,
+			    struct tcpci_src_emul_data *src, int pdo_index,
+			    const struct emul *tcpci_emul,
+			    const struct emul *charger_emul)
+{
+	set_ac_enabled(true);
+	zassert_ok(tcpci_partner_connect_to_tcpci(partner, tcpci_emul));
+
+	isl923x_emul_set_adc_vbus(charger_emul,
+				  PDO_FIXED_GET_VOLT(src->pdo[pdo_index]));
+
+	k_sleep(K_SECONDS(10));
+}
+
+void disconnect_source_from_port(const struct emul *tcpci_emul,
+				 const struct emul *charger_emul)
+{
+	set_ac_enabled(false);
+	zassert_ok(tcpci_emul_disconnect_partner(tcpci_emul));
+	isl923x_emul_set_adc_vbus(charger_emul, 0);
+	k_sleep(K_SECONDS(1));
+}
+
+void connect_sink_to_port(struct tcpci_partner_data *partner,
+			  const struct emul *tcpci_emul,
+			  const struct emul *charger_emul)
+{
+	/*
+	 * TODO(b/221439302) Updating the TCPCI emulator registers, updating the
+	 *   vbus, as well as alerting should all be a part of the connect
+	 *   function.
+	 */
+	/* Enforce that we only support the isl923x emulator for now */
+	__ASSERT_NO_MSG(EMUL_DT_GET(DT_NODELABEL(isl923x_emul)) ==
+			charger_emul);
+	isl923x_emul_set_adc_vbus(charger_emul, 0);
+	zassert_ok(tcpci_emul_set_vbus_level(tcpci_emul, VBUS_SAFE0V));
+	tcpci_tcpc_alert(0);
+	k_sleep(K_SECONDS(1));
+
+	zassert_ok(tcpci_partner_connect_to_tcpci(partner, tcpci_emul));
+
+	/* Wait for PD negotiation and current ramp.
+	 * TODO(b/213906889): Check message timing and contents.
+	 */
+	k_sleep(K_SECONDS(10));
+}
+
+void disconnect_sink_from_port(const struct emul *tcpci_emul)
+{
+	zassert_ok(tcpci_emul_disconnect_partner(tcpci_emul));
+	k_sleep(K_SECONDS(1));
+}
+#endif /* DT_HAS_COMPAT_STATUS_OKAY(cros_isl923x_emul) */
+
+uint8_t acpi_read(uint8_t acpi_addr)
+{
+	uint8_t readval;
+	/*
+	 * See ec_commands.h for details on the required process
+	 * First, send the read command, which should populate no data
+	 */
+	zassert_ok(acpi_ap_to_ec(true, EC_CMD_ACPI_READ, &readval),
+		   "Failed to send read command");
+
+	/* Next, time for the address which should populate our result */
+	zassert_equal(acpi_ap_to_ec(false, acpi_addr, &readval), 1,
+		      "Failed to read value");
+	return readval;
+}
+
+void acpi_write(uint8_t acpi_addr, uint8_t write_byte)
+{
+	uint8_t readval;
+	/*
+	 * See ec_commands.h for details on the required process
+	 * First, send the read command, which should populate no data
+	 */
+	zassert_ok(acpi_ap_to_ec(true, EC_CMD_ACPI_WRITE, &readval),
+		   "Failed to send read command");
+
+	/* Next, time for the address we want to write */
+	zassert_ok(acpi_ap_to_ec(false, acpi_addr, &readval),
+		   "Failed to write address");
+
+	/* Finally, time to write the data */
+	zassert_ok(acpi_ap_to_ec(false, write_byte, &readval),
+		   "Failed to write value");
+}
+
+enum ec_status host_cmd_host_event(enum ec_host_event_action action,
+				   enum ec_host_event_mask_type mask_type,
+				   struct ec_response_host_event *r)
+{
+	enum ec_status ret_val;
+
+	struct ec_params_host_event params = {
+		.action = action,
+		.mask_type = mask_type,
+	};
+
+	ret_val = ec_cmd_host_event(NULL, &params, r);
+
+	return ret_val;
+}
+
+void host_cmd_motion_sense_dump(int max_sensor_count,
+				struct ec_response_motion_sense *response,
+				size_t response_size)
+{
+	struct ec_params_motion_sense params = {
+		.cmd = MOTIONSENSE_CMD_DUMP,
+		.dump = {
+			.max_sensor_count = max_sensor_count,
+		},
+	};
+
+	struct host_cmd_handler_args args = {
+		.send_response = stub_send_response_callback,
+		.command = EC_CMD_MOTION_SENSE_CMD,
+		.version = 4,
+		.params = &params,
+		.params_size = sizeof(params),
+		.response = response,
+		.response_max = response_size,
+		.response_size = 0,
+	};
+
+	zassert_ok(host_command_process(&args),
+		   "Failed to get motion_sense dump");
+}
+
+int host_cmd_motion_sense_data(uint8_t sensor_num,
+			       struct ec_response_motion_sense *response)
+{
+	struct ec_params_motion_sense params = {
+		.cmd = MOTIONSENSE_CMD_DATA,
+		.sensor_odr = {
+			.sensor_num = sensor_num,
+		},
+	};
+
+	return ec_cmd_motion_sense_cmd_v4(NULL, &params, response);
+}
+
+int host_cmd_motion_sense_info(uint8_t cmd_version, uint8_t sensor_num,
+			       struct ec_response_motion_sense *response)
+{
+	struct ec_params_motion_sense params = {
+		.cmd = MOTIONSENSE_CMD_INFO,
+		.sensor_odr = {
+			.sensor_num = sensor_num,
+		},
+	};
+	struct host_cmd_handler_args args = BUILD_HOST_COMMAND(
+		EC_CMD_MOTION_SENSE_CMD, cmd_version, *response, params);
+
+	return host_command_process(&args);
+}
+
+int host_cmd_motion_sense_ec_rate(uint8_t sensor_num, int data_rate_ms,
+				  struct ec_response_motion_sense *response)
+{
+	struct ec_params_motion_sense params = {
+		.cmd = MOTIONSENSE_CMD_EC_RATE,
+		.ec_rate = {
+			.sensor_num = sensor_num,
+			.data = data_rate_ms,
+		},
+	};
+
+	return ec_cmd_motion_sense_cmd_v1(NULL, &params, response);
+}
+
+int host_cmd_motion_sense_odr(uint8_t sensor_num, int32_t odr, bool round_up,
+			      struct ec_response_motion_sense *response)
+{
+	struct ec_params_motion_sense params = {
+		.cmd = MOTIONSENSE_CMD_SENSOR_ODR,
+		.sensor_odr = {
+			.sensor_num = sensor_num,
+			.data = odr,
+			.roundup = round_up,
+		},
+	};
+
+	return ec_cmd_motion_sense_cmd_v1(NULL, &params, response);
+}
+
+int host_cmd_motion_sense_range(uint8_t sensor_num, int32_t range,
+				bool round_up,
+				struct ec_response_motion_sense *response)
+{
+	struct ec_params_motion_sense params = {
+		.cmd = MOTIONSENSE_CMD_SENSOR_RANGE,
+		.sensor_range = {
+			.sensor_num = sensor_num,
+			.data = range,
+			.roundup = round_up,
+		},
+	};
+
+	return ec_cmd_motion_sense_cmd_v1(NULL, &params, response);
+}
+
+int host_cmd_motion_sense_offset(uint8_t sensor_num, uint16_t flags,
+				 int16_t temperature, int16_t offset_x,
+				 int16_t offset_y, int16_t offset_z,
+				 struct ec_response_motion_sense *response)
+{
+	struct ec_params_motion_sense params = {
+		.cmd = MOTIONSENSE_CMD_SENSOR_OFFSET,
+		.sensor_offset = {
+			.sensor_num = sensor_num,
+			.flags = flags,
+			.temp = temperature,
+			.offset = { offset_x, offset_y, offset_z },
+		},
+	};
+
+	return ec_cmd_motion_sense_cmd_v1(NULL, &params, response);
+}
+
+int host_cmd_motion_sense_scale(uint8_t sensor_num, uint16_t flags,
+				int16_t temperature, int16_t scale_x,
+				int16_t scale_y, int16_t scale_z,
+				struct ec_response_motion_sense *response)
+{
+	struct ec_params_motion_sense params = {
+		.cmd = MOTIONSENSE_CMD_SENSOR_SCALE,
+		.sensor_scale = {
+			.sensor_num = sensor_num,
+			.flags = flags,
+			.temp = temperature,
+			.scale = { scale_x, scale_y, scale_z },
+		},
+	};
+
+	return ec_cmd_motion_sense_cmd_v1(NULL, &params, response);
+}
+
+int host_cmd_motion_sense_calib(uint8_t sensor_num, bool enable,
+				struct ec_response_motion_sense *response)
+{
+	struct ec_params_motion_sense params = {
+		.cmd = MOTIONSENSE_CMD_PERFORM_CALIB,
+		.perform_calib = {
+			.sensor_num = sensor_num,
+			.enable = enable,
+		},
+	};
+
+	return ec_cmd_motion_sense_cmd_v1(NULL, &params, response);
+}
+
+int host_cmd_motion_sense_fifo_flush(uint8_t sensor_num,
+				     struct ec_response_motion_sense *response,
+				     size_t response_size)
+{
+	struct ec_params_motion_sense params = {
+		.cmd = MOTIONSENSE_CMD_FIFO_FLUSH,
+		.sensor_odr = {
+			.sensor_num = sensor_num,
+		},
+	};
+
+	struct host_cmd_handler_args args = {
+		.send_response = stub_send_response_callback,
+		.command = EC_CMD_MOTION_SENSE_CMD,
+		.version = 1,
+		.params = &params,
+		.params_size = sizeof(params),
+		.response = response,
+		.response_max = response_size,
+		.response_size = 0,
+	};
+
+	return host_command_process(&args);
+}
+
+int host_cmd_motion_sense_fifo_info(struct ec_response_motion_sense *response,
+				    size_t response_size)
+{
+	struct ec_params_motion_sense params = {
+		.cmd = MOTIONSENSE_CMD_FIFO_INFO,
+	};
+
+	struct host_cmd_handler_args args = {
+		.send_response = stub_send_response_callback,
+		.command = EC_CMD_MOTION_SENSE_CMD,
+		.version = 1,
+		.params = &params,
+		.params_size = sizeof(params),
+		.response = response,
+		.response_max = response_size,
+		.response_size = 0,
+	};
+
+	return host_command_process(&args);
+}
+
+int host_cmd_motion_sense_fifo_read(uint8_t buffer_length,
+				    struct ec_response_motion_sense *response)
+{
+	struct ec_params_motion_sense params = {
+		.cmd = MOTIONSENSE_CMD_FIFO_READ,
+		.fifo_read = {
+			.max_data_vector = buffer_length,
+		},
+	};
+
+	return ec_cmd_motion_sense_cmd_v1(NULL, &params, response);
+}
+
+int host_cmd_motion_sense_int_enable(int8_t enable,
+				     struct ec_response_motion_sense *response)
+{
+	struct ec_params_motion_sense params = {
+		.cmd = MOTIONSENSE_CMD_FIFO_INT_ENABLE,
+		.fifo_int_enable = {
+			.enable = enable,
+		},
+	};
+
+	return ec_cmd_motion_sense_cmd_v1(NULL, &params, response);
+}
+
+int host_cmd_motion_sense_spoof(uint8_t sensor_num, uint8_t enable,
+				int16_t values0, int16_t values1,
+				int16_t values2,
+				struct ec_response_motion_sense *response)
+{
+	struct ec_params_motion_sense params = {
+		.cmd = MOTIONSENSE_CMD_SPOOF,
+		.spoof = {
+			.sensor_id = sensor_num,
+			.spoof_enable = enable,
+			.components = { values0, values1, values2 },
+		},
+	};
+
+	return ec_cmd_motion_sense_cmd_v1(NULL, &params, response);
+}
+
+int host_cmd_motion_sense_kb_wake_angle(
+	int16_t data, struct ec_response_motion_sense *response)
+{
+	struct ec_params_motion_sense params = {
+		.cmd = MOTIONSENSE_CMD_KB_WAKE_ANGLE,
+		.kb_wake_angle = {
+			.data = data,
+		},
+	};
+
+	return ec_cmd_motion_sense_cmd_v1(NULL, &params, response);
+}
+
+int host_cmd_motion_sense_lid_angle(struct ec_response_motion_sense *response)
+{
+	struct ec_params_motion_sense params = {
+		.cmd = MOTIONSENSE_CMD_LID_ANGLE,
+	};
+
+	return ec_cmd_motion_sense_cmd_v1(NULL, &params, response);
+}
+
+int host_cmd_motion_sense_tablet_mode_lid_angle(
+	int16_t lid_angle, int16_t hys_degree,
+	struct ec_response_motion_sense *response)
+{
+	struct ec_params_motion_sense
+		params = { .cmd = MOTIONSENSE_CMD_TABLET_MODE_LID_ANGLE,
+			   .tablet_mode_threshold = {
+				   .lid_angle = lid_angle,
+				   .hys_degree = hys_degree,
+			   } };
+
+	return ec_cmd_motion_sense_cmd_v1(NULL, &params, response);
+}
+
+void host_cmd_typec_discovery(int port, enum typec_partner_type partner_type,
+			      void *response, size_t response_size)
+{
+	struct ec_params_typec_discovery params = {
+		.port = port, .partner_type = partner_type
+	};
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_PARAMS(EC_CMD_TYPEC_DISCOVERY, 0, params);
+	/* The expected response to EC_CMD_TYPEC_DISCOVERY extends beyond the
+	 * bounds of struct ec_response_typec_discovery.
+	 */
+	args.response = response;
+	args.response_max = response_size;
+
+	zassert_ok(host_command_process(&args),
+		   "Failed to get Type-C state for port %d", port);
+}
+
+void host_cmd_typec_control_enter_mode(int port, enum typec_mode mode)
+{
+	struct ec_params_typec_control params = {
+		.port = port,
+		.command = TYPEC_CONTROL_COMMAND_ENTER_MODE,
+		.mode_to_enter = mode
+	};
+
+	zassert_ok(ec_cmd_typec_control(NULL, &params),
+		   "Failed to send Type-C control for port %d", port);
+}
+
+void host_cmd_typec_control_exit_modes(int port)
+{
+	struct ec_params_typec_control params = {
+		.port = port, .command = TYPEC_CONTROL_COMMAND_EXIT_MODES
+	};
+
+	zassert_ok(ec_cmd_typec_control(NULL, &params),
+		   "Failed to send Type-C control for port %d", port);
+}
+
+void host_cmd_typec_control_usb_mux_set(int port,
+					struct typec_usb_mux_set mux_set)
+{
+	struct ec_params_typec_control params = {
+		.port = port,
+		.command = TYPEC_CONTROL_COMMAND_USB_MUX_SET,
+		.mux_params = mux_set,
+	};
+
+	zassert_ok(ec_cmd_typec_control(NULL, &params),
+		   "Failed to send Type-C control for port %d", port);
+}
+
+void host_cmd_typec_control_clear_events(int port, uint32_t events)
+{
+	struct ec_params_typec_control params = {
+		.port = port,
+		.command = TYPEC_CONTROL_COMMAND_CLEAR_EVENTS,
+		.clear_events_mask = events,
+	};
+
+	zassert_ok(ec_cmd_typec_control(NULL, &params),
+		   "Failed to send Type-C control for port %d", port);
+}
+
+void host_cmd_typec_control_bist_share_mode(int port, int enable)
+{
+	struct ec_params_typec_control params = {
+		.port = port,
+		.command = TYPEC_CONTROL_COMMAND_BIST_SHARE_MODE,
+		.bist_share_mode = enable
+	};
+
+	zassert_ok(ec_cmd_typec_control(NULL, &params),
+		   "Failed to send Type-C control for port %d", port);
+}
+
+void host_cmd_typec_control_vdm_req(int port, struct typec_vdm_req vdm_req)
+{
+	struct ec_params_typec_control params = {
+		.port = port,
+		.command = TYPEC_CONTROL_COMMAND_SEND_VDM_REQ,
+		.vdm_req_params = vdm_req,
+	};
+
+	zassert_ok(ec_cmd_typec_control(NULL, &params),
+		   "Failed to send Type-C control for port %d", port);
+}
+
+struct ec_response_typec_vdm_response host_cmd_typec_vdm_response(int port)
+{
+	struct ec_params_typec_vdm_response params = { .port = port };
+	struct ec_response_typec_vdm_response response;
+
+	zassert_ok(ec_cmd_typec_vdm_response(NULL, &params, &response),
+		   "Failed to get Type-C state for port %d", port);
+	return response;
+}
+
+void host_events_save(struct host_events_ctx *host_events_ctx)
+{
+	host_events_ctx->lpc_host_events = lpc_get_host_events();
+
+	for (int i = 0; i < LPC_HOST_EVENT_COUNT; i++) {
+		host_events_ctx->lpc_host_event_mask[i] =
+			lpc_get_host_events_by_type(i);
+	}
+}
+
+void host_events_restore(struct host_events_ctx *host_events_ctx)
+{
+	lpc_set_host_event_state(host_events_ctx->lpc_host_events);
+
+	for (int i = 0; i < LPC_HOST_EVENT_COUNT; i++) {
+		lpc_set_host_event_mask(
+			i, host_events_ctx->lpc_host_event_mask[i]);
+	}
+}
+
+K_HEAP_DEFINE(test_heap, 2048);
+
+void *test_malloc(size_t bytes)
+{
+	void *mem;
+
+	mem = k_heap_alloc(&test_heap, bytes, K_NO_WAIT);
+
+	if (mem == NULL) {
+		printk("Failed to alloc %d bytes\n", bytes);
+	}
+
+	return mem;
+}
+
+void test_free(void *mem)
+{
+	k_heap_free(&test_heap, mem);
+}
+
+int emul_init_stub(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	return 0;
+}
+
+/* These 2 lines are needed because we don't define an espi host driver */
+#define DT_DRV_COMPAT zephyr_espi_emul_espi_host
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
+
+void check_console_cmd(const char *cmd, const char *expected_output,
+		       const int expected_rv, const char *file, const int line)
+{
+	const char *buffer;
+	size_t buffer_size;
+	int rv;
+
+	shell_backend_dummy_clear_output(get_ec_shell());
+	rv = shell_execute_cmd(get_ec_shell(), cmd);
+
+	zassert_equal(expected_rv, rv,
+		      "%s:%u \'%s\' - Expected %d, returned %d", file, line,
+		      cmd, expected_rv, rv);
+
+	if (expected_output) {
+		buffer = shell_backend_dummy_get_output(get_ec_shell(),
+							&buffer_size);
+		zassert_true(strstr(buffer, expected_output),
+			     "Invalid console output %s", buffer);
+	}
+}
diff --git a/zephyr/test/drivers/common_cbi/CMakeLists.txt b/zephyr/test/drivers/common_cbi/CMakeLists.txt
new file mode 100644
index 0000000000..45df234fbc
--- /dev/null
+++ b/zephyr/test/drivers/common_cbi/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Add source files
+target_sources(app PRIVATE src/test_common_cbi.c)
diff --git a/zephyr/test/drivers/common_cbi/src/test_common_cbi.c b/zephyr/test/drivers/common_cbi/src/test_common_cbi.c
new file mode 100644
index 0000000000..c038f9c31e
--- /dev/null
+++ b/zephyr/test/drivers/common_cbi/src/test_common_cbi.c
@@ -0,0 +1,239 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cros_board_info.h"
+#include "host_command.h"
+#include "test/drivers/test_mocks.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/drivers/eeprom.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/ztest.h>
+
+#define WP_L_GPIO_PATH NAMED_GPIOS_GPIO_NODE(wp_l)
+#define CBI_EEPROM_DEV DEVICE_DT_GET(DT_NODELABEL(cbi_eeprom))
+
+FAKE_VALUE_FUNC(int, eeprom_load, uint8_t, uint8_t *, int);
+
+static int gpio_wp_l_set(int value)
+{
+	const struct device *wp_l_gpio_dev =
+		DEVICE_DT_GET(DT_GPIO_CTLR(WP_L_GPIO_PATH, gpios));
+
+	return gpio_emul_input_set(wp_l_gpio_dev,
+				   DT_GPIO_PIN(WP_L_GPIO_PATH, gpios), value);
+}
+
+static int __test_eeprom_load_default_impl(uint8_t offset, uint8_t *data,
+					   int len)
+{
+	int ret = eeprom_read(CBI_EEPROM_DEV, offset, data, len);
+
+	return ret;
+}
+
+ZTEST(common_cbi, test_cbi_latch_eeprom_wp)
+{
+	const struct gpio_dt_spec *wp = GPIO_DT_FROM_ALIAS(gpio_cbi_wp);
+
+	zassert_equal(gpio_emul_output_get(wp->port, wp->pin), 0);
+
+	cbi_latch_eeprom_wp();
+
+	zassert_equal(gpio_emul_output_get(wp->port, wp->pin), 1);
+}
+
+ZTEST(common_cbi, test_do_cbi_read__cant_load_head)
+{
+	enum cbi_data_tag arbitrary_unused_tag = CBI_TAG_SKU_ID;
+	uint8_t arbitrary_unused_byte_buffer[100];
+	uint8_t unused_data_size;
+
+	/* Force a do_cbi_read() to eeprom */
+	cbi_invalidate_cache();
+
+	/* Return arbitrary nonzero value */
+	eeprom_load_fake.return_val = 1;
+	eeprom_load_fake.custom_fake = NULL;
+
+	zassert_equal(cbi_get_board_info(arbitrary_unused_tag,
+					 arbitrary_unused_byte_buffer,
+					 &unused_data_size),
+		      EC_ERROR_UNKNOWN);
+}
+
+ZTEST(common_cbi, test_cbi_set_string__null_str)
+{
+	struct cbi_data data = { 0 };
+	struct cbi_data unused_data = { 0 };
+	enum cbi_data_tag arbitrary_valid_tag = CBI_TAG_BOARD_VERSION;
+
+	zassert_equal(cbi_set_string((uint8_t *)&data, arbitrary_valid_tag,
+				     NULL),
+		      (uint8_t *)&data);
+
+	/* Validate no writes happened */
+	zassert_mem_equal(&data, &unused_data, sizeof(data));
+}
+
+ZTEST(common_cbi, test_cbi_set_string)
+{
+	const char arbitrary_str[] = "hello cbi";
+	enum cbi_data_tag arbitrary_valid_tag = CBI_TAG_SKU_ID;
+
+	struct cbi_data_wrapper {
+		struct cbi_data data;
+		uint8_t value_arr[ARRAY_SIZE(arbitrary_str)];
+	};
+	struct cbi_data_wrapper cbi_data = { 0 };
+
+	/* Set some provided memory then check values */
+	uint8_t *addr_byte_after_store = cbi_set_string(
+		(uint8_t *)&cbi_data, arbitrary_valid_tag, arbitrary_str);
+
+	zassert_equal(cbi_data.data.tag, arbitrary_valid_tag);
+	zassert_equal(cbi_data.data.size, ARRAY_SIZE(arbitrary_str));
+	zassert_mem_equal(cbi_data.data.value, arbitrary_str,
+			  cbi_data.data.size);
+
+	uint32_t expected_added_memory =
+		(ARRAY_SIZE(arbitrary_str) + sizeof(cbi_data.data));
+
+	/* Validate that next address for write was set appropriately */
+	zassert_equal_ptr(addr_byte_after_store - expected_added_memory,
+			  &cbi_data.data);
+}
+
+ZTEST_USER(common_cbi, test_hc_cbi_set_then_get)
+{
+	const uint8_t data[] = "I love test coverage! <3";
+
+	struct actual_set_params {
+		struct ec_params_set_cbi params;
+		uint8_t actual_data[ARRAY_SIZE(data)];
+	};
+
+	struct actual_set_params hc_set_params = {
+		.params = {
+		.tag = CBI_TAG_SKU_ID,
+		/* Force a reload */
+		.flag = CBI_SET_INIT,
+		.size = ARRAY_SIZE(data),
+		},
+	};
+	struct host_cmd_handler_args set_args = BUILD_HOST_COMMAND_PARAMS(
+		EC_CMD_SET_CROS_BOARD_INFO, 0, hc_set_params);
+
+	memcpy(hc_set_params.params.data, data, ARRAY_SIZE(data));
+
+	/* Turn off write-protect so we can actually write */
+	gpio_wp_l_set(1);
+
+	zassert_ok(host_command_process(&set_args));
+
+	/* Now verify our write by invoking a get host command */
+
+	struct ec_params_get_cbi hc_get_params = {
+		.flag = CBI_GET_RELOAD,
+		.tag = hc_set_params.params.tag,
+	};
+
+	struct test_ec_params_get_cbi_response {
+		uint8_t data[ARRAY_SIZE(data)];
+	};
+	struct test_ec_params_get_cbi_response hc_get_response;
+	struct host_cmd_handler_args get_args = BUILD_HOST_COMMAND(
+		EC_CMD_GET_CROS_BOARD_INFO, 0, hc_get_response, hc_get_params);
+
+	zassert_ok(host_command_process(&get_args));
+	zassert_mem_equal(hc_get_response.data, hc_set_params.actual_data,
+			  hc_set_params.params.size);
+}
+
+ZTEST_USER(common_cbi, test_hc_cbi_set__bad_size)
+{
+	const char data[] = "hello";
+
+	struct actual_set_params {
+		struct ec_params_set_cbi params;
+		/* We want less data than we need for our size */
+		uint8_t actual_data[0];
+	};
+	struct actual_set_params hc_set_params = {
+		.params = {
+		.tag = CBI_TAG_SKU_ID,
+		/* Force a reload */
+		.flag = CBI_SET_INIT,
+		.size = ARRAY_SIZE(data),
+		},
+	};
+	struct host_cmd_handler_args args = BUILD_HOST_COMMAND_PARAMS(
+		EC_CMD_SET_CROS_BOARD_INFO, 0, hc_set_params);
+
+	zassert_equal(host_command_process(&args), EC_RES_INVALID_PARAM);
+}
+
+ZTEST_USER(common_cbi, test_hc_cbi_set_then_get__with_too_small_response)
+{
+	const uint8_t data[] = "I'm way too big of a payload for you!";
+
+	struct actual_set_params {
+		struct ec_params_set_cbi params;
+		uint8_t actual_data[ARRAY_SIZE(data)];
+	};
+
+	struct actual_set_params hc_set_params = {
+		.params = {
+		.tag = CBI_TAG_SKU_ID,
+		/* Force a reload */
+		.flag = CBI_SET_INIT,
+		.size = ARRAY_SIZE(data),
+		},
+	};
+	struct host_cmd_handler_args set_args = BUILD_HOST_COMMAND_PARAMS(
+		EC_CMD_SET_CROS_BOARD_INFO, 0, hc_set_params);
+
+	memcpy(hc_set_params.params.data, data, ARRAY_SIZE(data));
+
+	/* Turn off write-protect so we can actually write */
+	gpio_wp_l_set(1);
+
+	zassert_ok(host_command_process(&set_args));
+
+	/* Now verify our write by invoking a get host command */
+
+	struct ec_params_get_cbi hc_get_params = {
+		.flag = CBI_GET_RELOAD,
+		.tag = hc_set_params.params.tag,
+	};
+
+	struct test_ec_params_get_cbi_response {
+		/*
+		 * Want want less space than we need to retrieve cbi data, by
+		 * allocating an array of size zero, we're implicitly setting
+		 * the response_max value of the host command to be zero. So the
+		 * host command will fail because it the EC knows it doesn't
+		 * have enough response space to actually fetch the data for the
+		 * host.
+		 */
+		uint8_t data[0];
+	};
+	struct test_ec_params_get_cbi_response hc_get_response;
+	struct host_cmd_handler_args get_args = BUILD_HOST_COMMAND(
+		EC_CMD_GET_CROS_BOARD_INFO, 0, hc_get_response, hc_get_params);
+
+	zassert_equal(host_command_process(&get_args), EC_RES_INVALID_PARAM);
+}
+
+static void test_common_cbi_before_after(void *test_data)
+{
+	RESET_FAKE(eeprom_load);
+	eeprom_load_fake.custom_fake = __test_eeprom_load_default_impl;
+
+	cbi_create();
+}
+
+ZTEST_SUITE(common_cbi, drivers_predicate_post_main, NULL,
+	    test_common_cbi_before_after, test_common_cbi_before_after, NULL);
diff --git a/zephyr/test/drivers/common_cbi_gpio/CMakeLists.txt b/zephyr/test/drivers/common_cbi_gpio/CMakeLists.txt
new file mode 100644
index 0000000000..2459cb1dec
--- /dev/null
+++ b/zephyr/test/drivers/common_cbi_gpio/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Add source files
+target_sources(app PRIVATE src/test_common_cbi_gpio.c)
diff --git a/zephyr/test/drivers/common_cbi_gpio/src/test_common_cbi_gpio.c b/zephyr/test/drivers/common_cbi_gpio/src/test_common_cbi_gpio.c
new file mode 100644
index 0000000000..8e8e4f6a8b
--- /dev/null
+++ b/zephyr/test/drivers/common_cbi_gpio/src/test_common_cbi_gpio.c
@@ -0,0 +1,73 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cros_board_info.h"
+#include "test/drivers/test_mocks.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/ztest.h>
+
+FAKE_VALUE_FUNC(int, system_get_board_version);
+FAKE_VALUE_FUNC(int, cbi_set_board_info, enum cbi_data_tag, const uint8_t *,
+		uint8_t);
+
+ZTEST(cbi_gpio, test_cbio_is_write_protected)
+{
+	zassert_true(cbi_config.drv->is_protected());
+}
+
+ZTEST(cbi_gpio, test_cbi_gpio_read__negative_board_id)
+{
+	uint8_t unused_offset = 0;
+	uint8_t unused_data = 0;
+	uint8_t unused_len = 0;
+
+	system_get_board_version_fake.return_val = -1;
+	zassert_equal(cbi_config.drv->load(unused_offset, &unused_data,
+					   unused_len),
+		      EC_ERROR_UNKNOWN);
+}
+
+ZTEST(cbi_gpio, test_cbi_gpio_read__bad_board_info_set)
+{
+	uint8_t unused_offset = 0;
+	uint8_t unused_data = 0;
+	uint8_t unused_len = 0;
+
+	/* Arbitrary nonzero to indicate failure */
+	cbi_set_board_info_fake.return_val = 1;
+	zassert_equal(cbi_config.drv->load(unused_offset, &unused_data,
+					   unused_len),
+		      EC_ERROR_UNKNOWN);
+}
+
+ZTEST(cbi_gpio, test_cbi_gpio_read__negative_board_id_then_bad_board_info_set)
+{
+	/* Tests the path of two separate errors occurring */
+
+	uint8_t unused_offset = 0;
+	uint8_t unused_data = 0;
+	uint8_t unused_len = 0;
+
+	system_get_board_version_fake.return_val = -1;
+
+	/* Arbitrary nonzero to indicate failure */
+	cbi_set_board_info_fake.return_val = 1;
+	zassert_equal(cbi_config.drv->load(unused_offset, &unused_data,
+					   unused_len),
+		      EC_ERROR_UNKNOWN);
+}
+
+static void test_cbi_gpio_before_after(void *test_data)
+{
+	ARG_UNUSED(test_data);
+
+	RESET_FAKE(system_get_board_version);
+	/* Make each cbi fetch fresh */
+	cbi_invalidate_cache();
+}
+
+ZTEST_SUITE(cbi_gpio, drivers_predicate_post_main, NULL,
+	    test_cbi_gpio_before_after, test_cbi_gpio_before_after, NULL);
diff --git a/zephyr/test/drivers/common_charger/CMakeLists.txt b/zephyr/test/drivers/common_charger/CMakeLists.txt
new file mode 100644
index 0000000000..3d39309233
--- /dev/null
+++ b/zephyr/test/drivers/common_charger/CMakeLists.txt
@@ -0,0 +1,11 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Add source files
+target_sources(app
+  PRIVATE
+    src/test_charge_state.c
+    src/test_common_charger.c
+    src/test_common_charger_mocked.c
+)
diff --git a/zephyr/test/drivers/common_charger/src/test_charge_state.c b/zephyr/test/drivers/common_charger/src/test_charge_state.c
new file mode 100644
index 0000000000..b900e97661
--- /dev/null
+++ b/zephyr/test/drivers/common_charger/src/test_charge_state.c
@@ -0,0 +1,129 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "charge_state.h"
+#include "math_util.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/ztest.h>
+
+int battery_outside_charging_temperature(void);
+
+struct charge_state_fixture {
+	struct charge_state_data charge_state_data;
+};
+
+static void *setup(void)
+{
+	static struct charge_state_fixture fixture;
+
+	return &fixture;
+}
+
+static void before(void *f)
+{
+	struct charge_state_fixture *fixture = f;
+
+	fixture->charge_state_data = *charge_get_status();
+}
+
+static void after(void *f)
+{
+	struct charge_state_fixture *fixture = f;
+
+	*charge_get_status() = fixture->charge_state_data;
+}
+
+ZTEST_SUITE(charge_state, drivers_predicate_post_main, setup, before, after,
+	    NULL);
+
+ZTEST(charge_state, test_battery_flag_bad_temperature)
+{
+	struct charge_state_data *curr = charge_get_status();
+
+	curr->batt.flags |= BATT_FLAG_BAD_TEMPERATURE;
+	zassert_ok(battery_outside_charging_temperature());
+}
+
+ZTEST(charge_state, test_battery_temperature_range)
+{
+	struct charge_state_data *curr = charge_get_status();
+	const struct battery_info *batt_info = battery_get_info();
+
+	curr->batt.flags &= ~BATT_FLAG_BAD_TEMPERATURE;
+
+	/* Start off without a desired voltage/current */
+	curr->batt.desired_voltage = 0;
+	curr->batt.desired_current = 0;
+
+	/* Temperature is too high */
+	curr->batt.temperature =
+		CELSIUS_TO_DECI_KELVIN(batt_info->start_charging_max_c + 1);
+	zassert_equal(1, battery_outside_charging_temperature());
+
+	/* Temperature is too low */
+	curr->batt.temperature =
+		CELSIUS_TO_DECI_KELVIN(batt_info->start_charging_min_c - 1);
+	zassert_equal(1, battery_outside_charging_temperature());
+
+	/* Temperature is just right */
+	curr->batt.temperature =
+		CELSIUS_TO_DECI_KELVIN((batt_info->start_charging_max_c +
+					batt_info->start_charging_min_c) /
+				       2);
+	zassert_ok(battery_outside_charging_temperature());
+
+	/* Set an arbitrary desired current */
+	curr->batt.desired_current = 3;
+
+	/* Temperature is too high */
+	curr->batt.temperature =
+		CELSIUS_TO_DECI_KELVIN(batt_info->charging_max_c + 1);
+	zassert_equal(1, battery_outside_charging_temperature());
+
+	/* Set an arbitrary desired voltage */
+	curr->batt.desired_voltage = 5;
+
+	/* Temperature is too low */
+	curr->batt.temperature =
+		CELSIUS_TO_DECI_KELVIN(batt_info->charging_min_c - 1);
+	zassert_equal(1, battery_outside_charging_temperature());
+
+	/* Temperature is just right */
+	curr->batt.temperature = CELSIUS_TO_DECI_KELVIN(
+		(batt_info->charging_max_c + batt_info->charging_min_c) / 2);
+	zassert_ok(battery_outside_charging_temperature());
+}
+
+ZTEST(charge_state, test_current_limit_derating)
+{
+	int charger_current_limit;
+
+	charge_set_input_current_limit(1000, 5000);
+	zassert_ok(charger_get_input_current_limit(0, &charger_current_limit));
+	/*
+	 * ISL923x sets ICL in multiples of 20 mA, so 950 mA gets rounded down
+	 * to the nearest multiple of 20.
+	 */
+	zassert_equal(
+		charger_current_limit, 944,
+		"%d%% derating of 1A should be 944 mA, but charger is set for %d mA",
+		CONFIG_PLATFORM_EC_CHARGER_INPUT_CURRENT_DERATE_PCT,
+		charger_current_limit);
+}
+
+ZTEST(charge_state, test_minimum_current_limit)
+{
+	int charger_current_limit;
+
+	charge_set_input_current_limit(50, 5000);
+	zassert_ok(charger_get_input_current_limit(0, &charger_current_limit));
+	zassert_equal(charger_current_limit, 96,
+		      "Minimum input current limit should be %d mA,"
+		      " but current limit is %d (capped to %d)",
+		      96, charger_current_limit,
+		      CONFIG_PLATFORM_EC_CHARGER_MIN_INPUT_CURRENT_LIMIT);
+}
diff --git a/zephyr/test/drivers/common_charger/src/test_common_charger.c b/zephyr/test/drivers/common_charger/src/test_common_charger.c
new file mode 100644
index 0000000000..46403636d6
--- /dev/null
+++ b/zephyr/test/drivers/common_charger/src/test_common_charger.c
@@ -0,0 +1,146 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_ramp.h"
+#include "driver/charger/isl923x_public.h"
+#include "ec_commands.h"
+#include "host_command.h"
+#include "test/drivers/charger_utils.h"
+#include "test/drivers/test_mocks.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+#include <zephyr/ztest_assert.h>
+
+/* Tested wrt isl923x without RAA489000 */
+
+/* Only single charger-chip configured for the drivers overlay */
+#define CHG_NUM get_charger_num(&isl923x_drv)
+
+/*
+ * Only faking functions that return an essentially constant value no chip
+ * register reading and thus no emulator reading.
+ */
+FAKE_VALUE_FUNC(int, isl923x_ramp_is_stable, int);
+FAKE_VALUE_FUNC(int, isl923x_ramp_is_detected, int);
+
+ZTEST(common_charger, test_chg_ramp_is_stable)
+{
+	isl923x_ramp_is_stable_fake.return_val = 1;
+
+	zassert_equal(chg_ramp_is_stable(),
+		      isl923x_ramp_is_stable_fake.return_val);
+	zassert_equal(isl923x_ramp_is_stable_fake.call_count, 1);
+	zassert_equal(isl923x_ramp_is_stable_fake.arg0_val, CHG_NUM);
+}
+
+ZTEST(common_charger, test_chg_ramp_is_detected)
+{
+	isl923x_ramp_is_stable_fake.return_val = 0;
+
+	zassert_equal(chg_ramp_is_detected(),
+		      isl923x_ramp_is_detected_fake.return_val);
+	zassert_equal(isl923x_ramp_is_detected_fake.call_count, 1);
+	zassert_equal(isl923x_ramp_is_detected_fake.arg0_val, CHG_NUM);
+}
+
+ZTEST(common_charger, test_chg_ramp_get_current_limit)
+{
+	zassert_equal(chg_ramp_get_current_limit(),
+		      CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT);
+}
+
+ZTEST(common_charger, test_charger_get_min_bat_pct_for_power_on)
+{
+	zassert_equal(charger_get_min_bat_pct_for_power_on(),
+		      CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON);
+}
+
+ZTEST(common_charger, test_charger_set_vsys_compensation__bad_arg)
+{
+	/* Not supported without RAA489000 */
+	struct ocpc_data unused = { 0 };
+	/* All arguments but 0th are unused. */
+	zassert_equal(charger_set_vsys_compensation(INT_MAX, &unused, 0, 0),
+		      EC_ERROR_INVAL);
+}
+
+ZTEST(common_charger, test_charger_set_vsys_compensation__unsupported)
+{
+	/* Not supported without RAA489000 */
+	struct ocpc_data unused = { 0 };
+	/* All arguments but 0th are unused. */
+	zassert_equal(charger_set_vsys_compensation(CHG_NUM, &unused, 0, 0),
+		      EC_ERROR_UNIMPLEMENTED);
+}
+
+ZTEST(common_charger, test_charger_is_icl_reached__bad_arg)
+{
+	bool unused = false;
+
+	zassert_equal(charger_is_icl_reached(INT_MAX, &unused), EC_ERROR_INVAL);
+	zassert_equal(charger_is_icl_reached(INT_MIN, &unused), EC_ERROR_INVAL);
+}
+
+ZTEST(common_charger, test_charger_is_icl_reached__unsupported)
+{
+	/* Not supported by isl923x */
+	bool unused;
+
+	zassert_equal(charger_is_icl_reached(CHG_NUM, &unused),
+		      EC_ERROR_UNIMPLEMENTED);
+}
+
+ZTEST(common_charger, test_charger_enable_linear_charge__bad_arg)
+{
+	/* Not supported without RAA489000 */
+	/* All arguments but 0th are unused. */
+	zassert_equal(charger_enable_linear_charge(INT_MAX, false),
+		      EC_ERROR_INVAL);
+}
+
+ZTEST(common_charger, test_charger_enable_linear_charge__unsupported)
+{
+	/* Not supported without RAA489000 */
+	/* All arguments but 0th are unused. */
+	zassert_equal(charger_enable_linear_charge(CHG_NUM, false),
+		      EC_ERROR_UNIMPLEMENTED);
+}
+
+ZTEST(common_charger, test_charger_get_battery_cells__bad_arg)
+{
+	/* Not supported by isl923x */
+	/* All arguments but 0th are unused. */
+	int unused;
+
+	zassert_equal(charger_get_battery_cells(INT_MAX, &unused),
+		      EC_ERROR_INVAL);
+}
+
+ZTEST(common_charger, test_charger_get_battery_cells__unsupported)
+{
+	/* Not supported by isl923x */
+	/* All arguments but 0th are unused. */
+	int unused;
+
+	zassert_equal(charger_get_battery_cells(CHG_NUM, &unused),
+		      EC_ERROR_UNIMPLEMENTED);
+}
+
+static void suite_common_charger_before_after(void *test_data)
+{
+	ARG_UNUSED(test_data);
+
+	RESET_FAKE(isl923x_ramp_is_stable);
+	RESET_FAKE(isl923x_ramp_is_detected);
+	/* Driver's default hard-coded value */
+	isl923x_ramp_is_detected_fake.return_val = 1;
+
+	isl923x_drv.init(CHG_NUM);
+}
+
+ZTEST_SUITE(common_charger, drivers_predicate_post_main, NULL,
+	    suite_common_charger_before_after, NULL, NULL);
diff --git a/zephyr/test/drivers/common_charger/src/test_common_charger_mocked.c b/zephyr/test/drivers/common_charger/src/test_common_charger_mocked.c
new file mode 100644
index 0000000000..c353b7b6c5
--- /dev/null
+++ b/zephyr/test/drivers/common_charger/src/test_common_charger_mocked.c
@@ -0,0 +1,598 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_ramp.h"
+#include "charger.h"
+#include "test/drivers/charger_utils.h"
+#include "test/drivers/test_state.h"
+
+#include <string.h>
+
+#include <zephyr/fff.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+#include <zephyr/ztest_assert.h>
+
+/* This test suite only works if the chg_chips array is not const. */
+BUILD_ASSERT(IS_ENABLED(CONFIG_PLATFORM_EC_CHARGER_RUNTIME_CONFIG),
+	     "chg_chips array cannot be const.");
+
+/** Index of the charger chip we are overriding / working with. */
+#define CHG_NUM (0)
+
+/* FFF fakes for driver functions. These get assigned to members of the
+ * charger_drv struct
+ */
+FAKE_VALUE_FUNC(enum ec_error_list, enable_otg_power, int, int);
+FAKE_VALUE_FUNC(enum ec_error_list, set_otg_current_voltage, int, int, int);
+FAKE_VALUE_FUNC(int, is_sourcing_otg_power, int, int);
+FAKE_VALUE_FUNC(enum ec_error_list, get_actual_current, int, int *);
+FAKE_VALUE_FUNC(enum ec_error_list, get_actual_voltage, int, int *);
+FAKE_VALUE_FUNC(enum ec_error_list, set_voltage, int, int);
+FAKE_VALUE_FUNC(enum ec_error_list, get_vsys_voltage, int, int, int *);
+FAKE_VALUE_FUNC(enum ec_error_list, enable_bypass_mode, int, bool);
+FAKE_VALUE_FUNC(enum ec_error_list, set_vsys_compensation, int,
+		struct ocpc_data *, int, int);
+FAKE_VALUE_FUNC(enum ec_error_list, is_icl_reached, int, bool *);
+FAKE_VALUE_FUNC(enum ec_error_list, enable_linear_charge, int, bool);
+FAKE_VALUE_FUNC(enum ec_error_list, get_battery_cells, int, int *);
+
+/**
+ * @brief If non-NULL, board_get_charger_chip_count returns the value this
+ * pointer points to.
+ */
+static uint8_t *fake_charger_count;
+
+/**
+ * @brief Override of definition from common/charger.c. Allows adjusting the
+ * number of chargers. This is not an FFF mock because FFF mock return values
+ * default to 0 until the test code gets a change to update it, which can cause
+ * a race condition as the EC initializes. This function has the correct
+ * count as soon as the program starts, which is CHARGER_NUM chargers.
+ *
+ * @return uint8_t Number of charger chips
+ */
+uint8_t board_get_charger_chip_count(void)
+{
+	if (fake_charger_count) {
+		return *fake_charger_count;
+	}
+
+	/* Default value */
+	return CHARGER_NUM;
+}
+
+struct common_charger_mocked_driver_fixture {
+	/* The original driver pointer that gets restored after the tests */
+	const struct charger_drv *saved_driver_ptr;
+	/* Mock driver that gets substituted */
+	struct charger_drv mock_driver;
+};
+
+ZTEST(common_charger_mocked_driver, test_charger_enable_otg_power__invalid)
+{
+	/* charger number out of bounds */
+	zassert_equal(EC_ERROR_INVAL, charger_enable_otg_power(-1, 0));
+	zassert_equal(EC_ERROR_INVAL, charger_enable_otg_power(INT_MAX, 0));
+}
+
+ZTEST(common_charger_mocked_driver, test_charger_enable_otg_power__unimpl)
+{
+	/* enable_otg_power is NULL */
+	zassert_equal(EC_ERROR_UNIMPLEMENTED,
+		      charger_enable_otg_power(CHG_NUM, 1));
+}
+
+ZTEST_F(common_charger_mocked_driver, test_charger_enable_otg_power)
+{
+	fixture->mock_driver.enable_otg_power = enable_otg_power;
+	enable_otg_power_fake.return_val = 123;
+
+	zassert_equal(enable_otg_power_fake.return_val,
+		      charger_enable_otg_power(CHG_NUM, 1));
+
+	zassert_equal(1, enable_otg_power_fake.call_count);
+	zassert_equal(CHG_NUM, enable_otg_power_fake.arg0_history[0]);
+	zassert_equal(1, enable_otg_power_fake.arg1_history[0]);
+}
+
+ZTEST(common_charger_mocked_driver,
+      test_charger_set_otg_current_voltage__invalid)
+{
+	/* charger number out of bounds */
+	zassert_equal(EC_ERROR_INVAL,
+		      charger_set_otg_current_voltage(-1, 0, 0));
+	zassert_equal(EC_ERROR_INVAL,
+		      charger_set_otg_current_voltage(INT_MAX, 0, 0));
+}
+
+ZTEST(common_charger_mocked_driver,
+      test_charger_set_otg_current_voltage__unimpl)
+{
+	/* set_otg_current_voltage is NULL */
+	zassert_equal(EC_ERROR_UNIMPLEMENTED,
+		      charger_set_otg_current_voltage(CHG_NUM, 0, 0));
+}
+
+ZTEST_F(common_charger_mocked_driver, test_charger_set_otg_current_voltage)
+{
+	fixture->mock_driver.set_otg_current_voltage = set_otg_current_voltage;
+	set_otg_current_voltage_fake.return_val = 123;
+
+	zassert_equal(set_otg_current_voltage_fake.return_val,
+		      charger_set_otg_current_voltage(CHG_NUM, 10, 20));
+
+	zassert_equal(1, set_otg_current_voltage_fake.call_count);
+	zassert_equal(CHG_NUM, set_otg_current_voltage_fake.arg0_history[0]);
+	zassert_equal(10, set_otg_current_voltage_fake.arg1_history[0]);
+	zassert_equal(20, set_otg_current_voltage_fake.arg2_history[0]);
+}
+
+ZTEST(common_charger_mocked_driver, test_charger_is_sourcing_otg_power__invalid)
+{
+	/* is_sourcing_otg_power is NULL */
+	zassert_equal(0, charger_is_sourcing_otg_power(0));
+}
+
+ZTEST_F(common_charger_mocked_driver, test_charger_is_sourcing_otg_power)
+{
+	fixture->mock_driver.is_sourcing_otg_power = is_sourcing_otg_power;
+	is_sourcing_otg_power_fake.return_val = 123;
+
+	zassert_equal(is_sourcing_otg_power_fake.return_val,
+		      charger_is_sourcing_otg_power(0));
+
+	zassert_equal(1, is_sourcing_otg_power_fake.call_count);
+}
+
+ZTEST(common_charger_mocked_driver, test_charger_get_actual_current__invalid)
+{
+	/* charger number out of bounds */
+	zassert_equal(EC_ERROR_INVAL, charger_get_actual_current(-1, NULL));
+	zassert_equal(EC_ERROR_INVAL,
+		      charger_get_actual_current(INT_MAX, NULL));
+}
+
+ZTEST(common_charger_mocked_driver, test_charger_get_actual_current__unimpl)
+{
+	/* get_actual_current is NULL */
+	zassert_equal(EC_ERROR_UNIMPLEMENTED,
+		      charger_get_actual_current(CHG_NUM, NULL));
+}
+
+/**
+ * @brief Custom fake for get_actual_current that can write to the output param
+ */
+static enum ec_error_list get_actual_current_custom_fake(int chgnum,
+							 int *current)
+{
+	ARG_UNUSED(chgnum);
+
+	*current = 1000;
+
+	return EC_SUCCESS;
+}
+
+ZTEST_F(common_charger_mocked_driver, test_charger_get_actual_current)
+{
+	int current;
+
+	fixture->mock_driver.get_actual_current = get_actual_current;
+	get_actual_current_fake.custom_fake = get_actual_current_custom_fake;
+
+	zassert_equal(EC_SUCCESS,
+		      charger_get_actual_current(CHG_NUM, &current));
+
+	zassert_equal(1, get_actual_current_fake.call_count);
+	zassert_equal(CHG_NUM, get_actual_current_fake.arg0_history[0]);
+	zassert_equal(1000, current);
+}
+
+ZTEST(common_charger_mocked_driver, test_charger_get_actual_voltage__invalid)
+{
+	/* charger number out of bounds */
+	zassert_equal(EC_ERROR_INVAL, charger_get_actual_voltage(-1, NULL));
+	zassert_equal(EC_ERROR_INVAL,
+		      charger_get_actual_voltage(INT_MAX, NULL));
+}
+
+ZTEST(common_charger_mocked_driver, test_charger_get_actual_voltage__unimpl)
+{
+	/* get_actual_voltage is NULL */
+	zassert_equal(EC_ERROR_UNIMPLEMENTED,
+		      charger_get_actual_voltage(CHG_NUM, NULL));
+}
+
+/**
+ * @brief Custom fake for get_actual_voltage that can write to the output param
+ */
+static enum ec_error_list get_actual_voltage_custom_fake(int chgnum,
+							 int *voltage)
+{
+	ARG_UNUSED(chgnum);
+
+	*voltage = 2000;
+
+	return EC_SUCCESS;
+}
+
+ZTEST_F(common_charger_mocked_driver, test_charger_get_actual_voltage)
+{
+	int voltage;
+
+	fixture->mock_driver.get_actual_voltage = get_actual_voltage;
+	get_actual_voltage_fake.custom_fake = get_actual_voltage_custom_fake;
+
+	zassert_equal(EC_SUCCESS,
+		      charger_get_actual_voltage(CHG_NUM, &voltage));
+
+	zassert_equal(1, get_actual_voltage_fake.call_count);
+	zassert_equal(CHG_NUM, get_actual_voltage_fake.arg0_history[0]);
+	zassert_equal(2000, voltage);
+}
+
+ZTEST(common_charger_mocked_driver, test_charger_set_voltage__invalid)
+{
+	/* charger number out of bounds */
+	zassert_equal(EC_ERROR_INVAL, charger_set_voltage(-1, 0));
+	zassert_equal(EC_ERROR_INVAL, charger_set_voltage(INT_MAX, 0));
+}
+
+ZTEST(common_charger_mocked_driver, test_charger_set_voltage__unimpl)
+{
+	/* set_voltage is NULL */
+	zassert_equal(EC_ERROR_UNIMPLEMENTED, charger_set_voltage(CHG_NUM, 0));
+}
+
+ZTEST_F(common_charger_mocked_driver, test_charger_set_voltage)
+{
+	fixture->mock_driver.set_voltage = set_voltage;
+	set_voltage_fake.return_val = 123;
+
+	zassert_equal(set_voltage_fake.return_val,
+		      charger_set_voltage(CHG_NUM, 2000));
+
+	zassert_equal(1, set_voltage_fake.call_count);
+	zassert_equal(CHG_NUM, set_voltage_fake.arg0_history[0]);
+	zassert_equal(2000, set_voltage_fake.arg1_history[0]);
+}
+
+ZTEST(common_charger_mocked_driver, test_charger_get_vsys_voltage__invalid)
+{
+	/* Cannot do chgnum bounds checking because
+	 * charger_get_valid_chgnum() will convert chgnum to 0 unless
+	 * CONFIG_CHARGER_SINGLE_CHIP is turned off.
+	 */
+
+	/* get_vsys_voltage is NULL */
+	zassert_equal(EC_ERROR_UNIMPLEMENTED,
+		      charger_get_vsys_voltage(CHG_NUM, NULL));
+}
+
+/**
+ * @brief Custom fake for get_vsys_voltage that can write to the output param
+ */
+static enum ec_error_list get_vsys_voltage_custom_fake(int chgnum, int port,
+						       int *voltage)
+{
+	ARG_UNUSED(chgnum);
+	ARG_UNUSED(port);
+
+	*voltage = 2000;
+
+	return EC_SUCCESS;
+}
+
+ZTEST_F(common_charger_mocked_driver, test_charger_get_vsys_voltage)
+{
+	int vsys_voltage;
+
+	fixture->mock_driver.get_vsys_voltage = get_vsys_voltage;
+	get_vsys_voltage_fake.custom_fake = get_vsys_voltage_custom_fake;
+
+	zassert_equal(EC_SUCCESS,
+		      charger_get_vsys_voltage(CHG_NUM, &vsys_voltage));
+
+	zassert_equal(1, get_vsys_voltage_fake.call_count);
+	zassert_equal(CHG_NUM, get_vsys_voltage_fake.arg0_history[0]);
+	zassert_equal(CHG_NUM, get_vsys_voltage_fake.arg1_history[0]);
+	zassert_equal(2000, vsys_voltage);
+}
+
+ZTEST(common_charger_mocked_driver, test_charger_enable_bypass_mode__invalid)
+{
+	/* enable_bypass_mode is NULL */
+	zassert_equal(EC_ERROR_UNIMPLEMENTED,
+		      charger_enable_bypass_mode(CHG_NUM, false));
+}
+
+ZTEST_F(common_charger_mocked_driver, test_charger_enable_bypass_mode)
+{
+	fixture->mock_driver.enable_bypass_mode = enable_bypass_mode;
+	enable_bypass_mode_fake.return_val = 123;
+
+	zassert_equal(123, charger_enable_bypass_mode(CHG_NUM, true));
+
+	zassert_equal(1, enable_bypass_mode_fake.call_count);
+	zassert_true(enable_bypass_mode_fake.arg1_history[0]);
+}
+
+ZTEST(common_charger_mocked_driver, test_charger_get_params__error_flags)
+{
+	/* When one of the parameters cannot be retrieved, a corresponding flag
+	 * is set. Since all of the driver functions are unimplemented by
+	 * default, this should cause all error flags to be set.
+	 */
+
+	struct charger_params params;
+
+	charger_get_params(&params);
+
+	zassert_true(params.flags & CHG_FLAG_BAD_CURRENT);
+	zassert_true(params.flags & CHG_FLAG_BAD_VOLTAGE);
+	zassert_true(params.flags & CHG_FLAG_BAD_INPUT_CURRENT);
+	zassert_true(params.flags & CHG_FLAG_BAD_STATUS);
+	zassert_true(params.flags & CHG_FLAG_BAD_OPTION);
+}
+
+ZTEST(common_charger_mocked_driver,
+      test_charger_get_input_current_limit__invalid)
+{
+	zassert_equal(EC_ERROR_INVAL,
+		      charger_get_input_current_limit(-1, false));
+	zassert_equal(EC_ERROR_INVAL,
+		      charger_get_input_current_limit(INT_MAX, false));
+}
+
+ZTEST(common_charger_mocked_driver,
+      test_charger_get_input_current_limit__unimpl)
+{
+	zassert_equal(EC_ERROR_UNIMPLEMENTED,
+		      charger_get_input_current_limit(CHG_NUM, false));
+}
+
+ZTEST(common_charger_mocked_driver, test_charger_get_input_current__invalid)
+{
+	zassert_equal(EC_ERROR_INVAL, charger_get_input_current(-1, NULL));
+	zassert_equal(EC_ERROR_INVAL, charger_get_input_current(INT_MAX, NULL));
+}
+
+ZTEST(common_charger_mocked_driver, test_charger_get_input_current__unimpl)
+{
+	zassert_equal(EC_ERROR_UNIMPLEMENTED,
+		      charger_get_input_current(CHG_NUM, NULL));
+}
+
+ZTEST(common_charger_mocked_driver, test_charger_manufacturer_id__invalid)
+{
+	uint8_t zero = 0;
+
+	fake_charger_count = &zero;
+	zassert_equal(EC_ERROR_INVAL, charger_manufacturer_id(NULL));
+}
+
+ZTEST(common_charger_mocked_driver, test_charger_manufacturer_id__unimpl)
+{
+	zassert_equal(EC_ERROR_UNIMPLEMENTED, charger_manufacturer_id(NULL));
+}
+
+ZTEST(common_charger_mocked_driver, test_charger_device_id__invalid)
+{
+	uint8_t zero = 0;
+
+	fake_charger_count = &zero;
+	zassert_equal(EC_ERROR_INVAL, charger_device_id(NULL));
+}
+
+ZTEST(common_charger_mocked_driver, test_charger_device_id__unimpl)
+{
+	zassert_equal(EC_ERROR_UNIMPLEMENTED, charger_device_id(NULL));
+}
+
+ZTEST(common_charger_mocked_driver, test_charger_get_option__invalid)
+{
+	uint8_t zero = 0;
+
+	fake_charger_count = &zero;
+	zassert_equal(EC_ERROR_INVAL, charger_get_option(NULL));
+}
+
+ZTEST(common_charger_mocked_driver, test_charger_get_option__unimpl)
+{
+	zassert_equal(EC_ERROR_UNIMPLEMENTED, charger_get_option(NULL));
+}
+
+ZTEST(common_charger_mocked_driver, test_charger_set_option__invalid)
+{
+	uint8_t zero = 0;
+
+	fake_charger_count = &zero;
+	zassert_equal(EC_ERROR_INVAL, charger_set_option(0));
+}
+
+ZTEST(common_charger_mocked_driver, test_charger_set_option__unimpl)
+{
+	zassert_equal(EC_ERROR_UNIMPLEMENTED, charger_set_option(0));
+}
+
+ZTEST(common_charger_mocked_driver, test_chg_ramp_is_stable__invalid)
+{
+	uint8_t zero = 0;
+
+	fake_charger_count = &zero;
+	zassert_false(chg_ramp_is_stable());
+}
+
+ZTEST(common_charger_mocked_driver, test_chg_ramp_is_stable__unimpl)
+{
+	/* Returns 0 if ramp_is_stable not implemented */
+	zassert_false(chg_ramp_is_stable());
+}
+
+ZTEST(common_charger_mocked_driver, test_chg_ramp_is_detected__invalid)
+{
+	uint8_t zero = 0;
+
+	fake_charger_count = &zero;
+	zassert_false(chg_ramp_is_detected());
+}
+
+ZTEST(common_charger_mocked_driver, test_chg_ramp_is_detected__unimpl)
+{
+	/* Returns 0 if ramp_is_detected not implemented */
+	zassert_false(chg_ramp_is_detected());
+}
+
+ZTEST(common_charger_mocked_driver, test_chg_ramp_get_current_limit__invalid)
+{
+	uint8_t zero = 0;
+
+	fake_charger_count = &zero;
+	zassert_false(chg_ramp_get_current_limit());
+}
+
+ZTEST(common_charger_mocked_driver, test_chg_ramp_get_current_limit__unimpl)
+{
+	/* Returns 0 if ramp_get_current_limit not implemented */
+	zassert_false(chg_ramp_get_current_limit());
+}
+
+ZTEST(common_charger_mocked_driver, test_charger_post_init__invalid)
+{
+	uint8_t zero = 0;
+
+	fake_charger_count = &zero;
+	zassert_equal(EC_ERROR_INVAL, charger_post_init());
+}
+
+ZTEST(common_charger_mocked_driver, test_charger_post_init__unimpl)
+{
+	zassert_equal(EC_ERROR_UNIMPLEMENTED, charger_post_init());
+}
+
+ZTEST(common_charger_mocked_driver, test_charger_get_info__invalid)
+{
+	uint8_t zero = 0;
+
+	fake_charger_count = &zero;
+	zassert_is_null(charger_get_info());
+}
+
+ZTEST(common_charger_mocked_driver, test_charger_get_info__unimpl)
+{
+	zassert_is_null(charger_get_info());
+}
+
+ZTEST(common_charger_mocked_driver, test_charger_get_status__invalid)
+{
+	uint8_t zero = 0;
+
+	fake_charger_count = &zero;
+	zassert_equal(EC_ERROR_INVAL, charger_get_status(NULL));
+}
+
+ZTEST(common_charger_mocked_driver, test_charger_set_mode__invalid)
+{
+	uint8_t zero = 0;
+
+	fake_charger_count = &zero;
+	zassert_equal(EC_ERROR_INVAL, charger_set_mode(0));
+}
+
+ZTEST(common_charger_mocked_driver, test_charger_set_mode__unimpl)
+{
+	zassert_equal(EC_ERROR_UNIMPLEMENTED, charger_set_mode(0));
+}
+
+ZTEST_F(common_charger_mocked_driver, test_charger_set_vsys_compensation)
+{
+	fixture->mock_driver.set_vsys_compensation = set_vsys_compensation;
+	set_vsys_compensation_fake.return_val = 123;
+
+	zassert_equal(123, charger_set_vsys_compensation(CHG_NUM, NULL, 0, 0));
+
+	zassert_equal(1, set_vsys_compensation_fake.call_count);
+}
+
+ZTEST_F(common_charger_mocked_driver, test_charger_is_icl_reached)
+{
+	fixture->mock_driver.is_icl_reached = is_icl_reached;
+	is_icl_reached_fake.return_val = 123;
+
+	zassert_equal(123, charger_is_icl_reached(CHG_NUM, NULL));
+
+	zassert_equal(1, is_icl_reached_fake.call_count);
+}
+
+ZTEST_F(common_charger_mocked_driver, test_charger_enable_linear_charge)
+{
+	fixture->mock_driver.enable_linear_charge = enable_linear_charge;
+	enable_linear_charge_fake.return_val = 123;
+
+	zassert_equal(123, charger_enable_linear_charge(CHG_NUM, 0));
+
+	zassert_equal(1, enable_linear_charge_fake.call_count);
+}
+
+ZTEST_F(common_charger_mocked_driver, test_charger_get_battery_cells)
+{
+	fixture->mock_driver.get_battery_cells = get_battery_cells;
+	get_battery_cells_fake.return_val = 123;
+
+	zassert_equal(123, charger_get_battery_cells(CHG_NUM, NULL));
+
+	zassert_equal(1, get_battery_cells_fake.call_count);
+}
+
+static void *setup(void)
+{
+	static struct common_charger_mocked_driver_fixture f;
+
+	zassert_true(board_get_charger_chip_count() > 0,
+		     "Need at least one charger chip present.");
+
+	/* Back up the current charger driver and substitute our own */
+	f.saved_driver_ptr = chg_chips[CHG_NUM].drv;
+	chg_chips[CHG_NUM].drv = &f.mock_driver;
+
+	return &f;
+}
+
+static void reset(void *data)
+{
+	struct common_charger_mocked_driver_fixture *f = data;
+
+	/* Reset the mock driver's function pointer table. Each tests adds these
+	 * as-needed
+	 */
+	f->mock_driver = (struct charger_drv){ 0 };
+
+	/* Reset fakes */
+	RESET_FAKE(enable_otg_power);
+	RESET_FAKE(set_otg_current_voltage);
+	RESET_FAKE(is_sourcing_otg_power);
+	RESET_FAKE(get_actual_current);
+	RESET_FAKE(get_actual_voltage);
+	RESET_FAKE(set_voltage);
+	RESET_FAKE(get_vsys_voltage);
+	RESET_FAKE(enable_bypass_mode);
+	RESET_FAKE(set_vsys_compensation);
+	RESET_FAKE(is_icl_reached);
+	RESET_FAKE(enable_linear_charge);
+	RESET_FAKE(get_battery_cells);
+
+	fake_charger_count = NULL;
+}
+
+static void teardown(void *data)
+{
+	struct common_charger_mocked_driver_fixture *f = data;
+
+	/* Restore the original driver */
+	chg_chips[CHG_NUM].drv = f->saved_driver_ptr;
+}
+
+ZTEST_SUITE(common_charger_mocked_driver, drivers_predicate_post_main, setup,
+	    reset, reset, teardown);
diff --git a/zephyr/test/drivers/console/CMakeLists.txt b/zephyr/test/drivers/console/CMakeLists.txt
new file mode 100644
index 0000000000..ec12af6393
--- /dev/null
+++ b/zephyr/test/drivers/console/CMakeLists.txt
@@ -0,0 +1,8 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_sources(app
+  PRIVATE
+    src/shell.c
+)
\ No newline at end of file
diff --git a/zephyr/test/drivers/console/src/shell.c b/zephyr/test/drivers/console/src/shell.c
new file mode 100644
index 0000000000..c7a85b8f32
--- /dev/null
+++ b/zephyr/test/drivers/console/src/shell.c
@@ -0,0 +1,88 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "test/drivers/test_state.h"
+#include "uart.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/uart.h>
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+void uart_callback(const struct device *dev, void *user_data);
+void bypass_cb(const struct shell *shell, uint8_t *data, size_t len);
+
+static const struct device *uart_shell_dev =
+	DEVICE_DT_GET(DT_CHOSEN(zephyr_shell_uart));
+
+static void shell_before(void *f)
+{
+	ARG_UNUSED(f);
+	uart_shell_start();
+	k_msleep(500);
+	uart_clear_input();
+}
+
+ZTEST_SUITE(shell, drivers_predicate_post_main, NULL, shell_before, NULL, NULL);
+
+ZTEST(shell, test_shell_stop_read_raw_data)
+{
+	const char uart_data[] = "ABCDEFGHIJKLMNOPQRSTUVWXYZ";
+
+	uart_shell_stop();
+	k_msleep(500);
+	zassert_true(uart_irq_tx_ready(uart_shell_dev) != 0);
+
+	uart_clear_input();
+
+	/* Run the callback once, should be empty */
+	uart_callback(uart_shell_dev, NULL);
+
+	zassert_equal(-1, uart_getc());
+
+	uart_clear_input();
+
+	/* Manually fill the buffer */
+	for (size_t i = 0; i < CONFIG_UART_RX_BUF_SIZE; ++i) {
+		bypass_cb(get_ec_shell(),
+			  (uint8_t *)&uart_data[i % ARRAY_SIZE(uart_data)], 1);
+	}
+
+	/* Push 1 extra character that should be dropped */
+	bypass_cb(get_ec_shell(), (uint8_t *)uart_data, 1);
+
+	/* Run the callback again to make sure we didn't lose any data */
+	uart_callback(uart_shell_dev, NULL);
+
+	for (size_t i = 0; i < CONFIG_UART_RX_BUF_SIZE; ++i) {
+		int c = uart_getc();
+
+		zassert_equal(
+			(int)uart_data[i % ARRAY_SIZE(uart_data)], c,
+			"Expected %uth character to be %c, but uart_getc() returned %c",
+			i, uart_data[i % ARRAY_SIZE(uart_data)], (char)c);
+	}
+
+	zassert_equal(-1, uart_getc());
+}
+
+ZTEST(shell, test_help_command)
+{
+	/* Verify that the `help` subcommand works for a random command */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "accelinfo help"));
+}
+
+ZTEST(shell, test_rx_bypass)
+{
+	const char uart_data = 'T';
+
+	bypass_cb(get_ec_shell(), (uint8_t *)&uart_data, 1);
+
+	/* Check that with the shell running and rx bypass disabled (default),
+	 * we cannot pull values from the uart buffer directly.
+	 */
+	zassert_equal(-1, uart_getc());
+}
diff --git a/zephyr/test/drivers/console_cmd_crash/CMakeLists.txt b/zephyr/test/drivers/console_cmd_crash/CMakeLists.txt
new file mode 100644
index 0000000000..dc9eea08d0
--- /dev/null
+++ b/zephyr/test/drivers/console_cmd_crash/CMakeLists.txt
@@ -0,0 +1,8 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_sources(app
+  PRIVATE
+    src/crash.c
+)
\ No newline at end of file
diff --git a/zephyr/test/drivers/console_cmd_crash/src/crash.c b/zephyr/test/drivers/console_cmd_crash/src/crash.c
new file mode 100644
index 0000000000..4218aa74d6
--- /dev/null
+++ b/zephyr/test/drivers/console_cmd_crash/src/crash.c
@@ -0,0 +1,34 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "builtin/assert.h"
+#include "console.h"
+#include "test/drivers/test_mocks.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+ZTEST_SUITE(console_cmd_crash, drivers_predicate_post_main, NULL, NULL, NULL,
+	    NULL);
+
+ZTEST_USER(console_cmd_crash, test_wrong_num_args)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "crash");
+
+	zassert_equal(EC_ERROR_PARAM1, rv, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+}
+
+ZTEST_USER(console_cmd_crash, test_assert)
+{
+	int rv;
+
+	RESET_FAKE(assert_post_action);
+	rv = shell_execute_cmd(get_ec_shell(), "crash assert");
+
+	zassert_equal(EC_ERROR_UNKNOWN, rv, NULL);
+	zassert_equal(1, assert_post_action_fake.call_count, NULL);
+}
diff --git a/zephyr/test/drivers/console_cmd_mfallow/CMakeLists.txt b/zephyr/test/drivers/console_cmd_mfallow/CMakeLists.txt
new file mode 100644
index 0000000000..abaf5246ba
--- /dev/null
+++ b/zephyr/test/drivers/console_cmd_mfallow/CMakeLists.txt
@@ -0,0 +1,15 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Create library name based on current directory
+zephyr_library_get_current_dir_lib_name(${ZEPHYR_BASE} lib_name)
+
+# Create interface library
+zephyr_interface_library_named(${lib_name})
+
+# Add source files
+zephyr_library_sources("${CMAKE_CURRENT_SOURCE_DIR}/src/console_cmd_mfallow.c")
+
+# Link in the library
+zephyr_library_link_libraries(${lib_name})
diff --git a/zephyr/test/drivers/console_cmd_mfallow/prj.conf b/zephyr/test/drivers/console_cmd_mfallow/prj.conf
new file mode 100644
index 0000000000..4caf617623
--- /dev/null
+++ b/zephyr/test/drivers/console_cmd_mfallow/prj.conf
@@ -0,0 +1,6 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_PLATFORM_EC_CONSOLE_CMD_MFALLOW=y
+CONFIG_PLATFORM_EC_USB_PD_REQUIRE_AP_MODE_ENTRY=y
diff --git a/zephyr/test/drivers/console_cmd_mfallow/src/console_cmd_mfallow.c b/zephyr/test/drivers/console_cmd_mfallow/src/console_cmd_mfallow.c
new file mode 100644
index 0000000000..97b3150017
--- /dev/null
+++ b/zephyr/test/drivers/console_cmd_mfallow/src/console_cmd_mfallow.c
@@ -0,0 +1,235 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "ec_commands.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "usb_dp_alt_mode.h"
+#include "usb_mux.h"
+#include "usb_pd_vdo.h"
+
+#include <stdint.h>
+
+#include <zephyr/kernel.h>
+#include <zephyr/shell/shell.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/ztest.h>
+
+#define TEST_PORT USBC_PORT_C0
+
+struct console_cmd_mfallow_fixture {
+	const struct emul *tcpci_emul;
+	const struct emul *charger_emul;
+	struct tcpci_partner_data partner;
+	struct tcpci_src_emul_data src_ext;
+};
+
+static void add_dp_discovery(struct tcpci_partner_data *partner)
+{
+	/* Add Discover Identity response */
+	partner->identity_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_PD, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_IDENT) |
+		VDO_SVDM_VERS(VDM_VER20);
+	partner->identity_vdm[VDO_INDEX_IDH] = VDO_IDH(
+		/* USB host */ false, /* USB device */ true, IDH_PTYPE_HUB,
+		/* modal operation */ true, USB_VID_GOOGLE);
+	partner->identity_vdm[VDO_INDEX_CSTAT] = 0;
+	partner->identity_vdm[VDO_INDEX_PRODUCT] = VDO_PRODUCT(0x1234, 0x5678);
+	/* Hardware version 1, firmware version 2 */
+	partner->identity_vdm[VDO_INDEX_PTYPE_UFP1_VDO] = VDO_UFP1(
+		(VDO_UFP1_CAPABILITY_USB20 | VDO_UFP1_CAPABILITY_USB32),
+		USB_TYPEC_RECEPTACLE, VDO_UFP1_ALT_MODE_RECONFIGURE,
+		USB_R30_SS_U32_U40_GEN2);
+	partner->identity_vdos = VDO_INDEX_PTYPE_UFP1_VDO + 1;
+
+	/* Add Discover Modes response */
+	/* Support one mode for DisplayPort VID.*/
+	partner->modes_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_DISPLAYPORT, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_MODES) |
+		VDO_SVDM_VERS(VDM_VER20);
+	partner->modes_vdm[VDO_INDEX_HDR + 1] =
+		VDO_MODE_DP(MODE_DP_PIN_C | MODE_DP_PIN_D, 0, 1,
+			    CABLE_RECEPTACLE, MODE_DP_V13, MODE_DP_SNK);
+	partner->modes_vdos = VDO_INDEX_HDR + 2;
+
+	/* Add Discover SVIDs response */
+	/* Support DisplayPort VID. */
+	partner->svids_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_PD, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_SVID) |
+		VDO_SVDM_VERS(VDM_VER20);
+	partner->svids_vdm[VDO_INDEX_HDR + 1] =
+		VDO_SVID(USB_SID_DISPLAYPORT, 0);
+	partner->svids_vdos = VDO_INDEX_HDR + 2;
+}
+
+static void add_displayport_mode_responses(struct tcpci_partner_data *partner)
+{
+	/* Add DisplayPort EnterMode response */
+	partner->enter_mode_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_DISPLAYPORT, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_ENTER_MODE) |
+		VDO_SVDM_VERS(VDM_VER20);
+	partner->enter_mode_vdos = VDO_INDEX_HDR + 1;
+
+	/* Add DisplayPort StatusUpdate response */
+	partner->dp_status_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_DISPLAYPORT, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DP_STATUS) |
+		VDO_SVDM_VERS(VDM_VER20);
+	partner->dp_status_vdm[VDO_INDEX_HDR + 1] =
+		VDO_DP_STATUS(0, /* IRQ_HPD */
+			      false, /* HPD_HI|LOW - Changed*/
+			      0, /* request exit DP */
+			      0, /* request exit USB */
+			      1, /* MF pref - must be 1 for this test */
+			      true, /* DP Enabled */
+			      0, /* power low e.g. normal */
+			      0x2 /* Connected as Sink */);
+	partner->dp_status_vdos = VDO_INDEX_HDR + 2;
+
+	/* Add DisplayPort Configure Response */
+	partner->dp_config_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_DISPLAYPORT, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DP_CONFIG) |
+		VDO_SVDM_VERS(VDM_VER20);
+	partner->dp_config_vdos = VDO_INDEX_HDR + 1;
+}
+
+static uint32_t dp_config_extract(struct console_cmd_mfallow_fixture *fixture)
+{
+	struct tcpci_partner_log_msg *msg;
+
+	SYS_SLIST_FOR_EACH_CONTAINER(&fixture->partner.msg_log, msg, node)
+	{
+		uint16_t header = sys_get_le16(msg->buf);
+
+		/* Ignore messages from ourselves */
+		if (msg->sender == TCPCI_PARTNER_SENDER_PARTNER)
+			continue;
+
+		/*
+		 * Control messages, non-VDMs, and extended messages are not of
+		 * interest
+		 */
+		if ((PD_HEADER_CNT(header) == 0) ||
+		    (PD_HEADER_TYPE(header) != PD_DATA_VENDOR_DEF) ||
+		    (PD_HEADER_EXT(header) != 0)) {
+			continue;
+		}
+
+		uint32_t vdm_header = sys_get_le32(msg->buf + 2);
+
+		/* We have a VDM, return if it's DP:Configure */
+		if (PD_VDO_SVDM(vdm_header) &&
+		    (PD_VDO_CMD(vdm_header) == CMD_DP_CONFIG))
+			return sys_get_le32(msg->buf + 6);
+	}
+
+	zassert_unreachable();
+	return 0;
+}
+
+static void *console_cmd_mfallow_setup(void)
+{
+	static struct console_cmd_mfallow_fixture fixture;
+	struct tcpci_partner_data *partner = &fixture.partner;
+	struct tcpci_src_emul_data *src_ext = &fixture.src_ext;
+
+	tcpci_partner_init(partner, PD_REV30);
+	partner->extensions = tcpci_src_emul_init(src_ext, partner, NULL);
+
+	/* Get references for the emulators */
+	fixture.tcpci_emul = EMUL_DT_GET(DT_NODELABEL(tcpci_emul));
+	fixture.charger_emul = EMUL_DT_GET(DT_NODELABEL(isl923x_emul));
+
+	return &fixture;
+}
+
+static void console_cmd_mfallow_before(void *data)
+{
+	struct console_cmd_mfallow_fixture *fix = data;
+	struct tcpci_partner_data *partner = &fix->partner;
+
+	/* Set chipset on so the "AP" is on to give us commands */
+	test_set_chipset_to_s0();
+
+	/* Set up the partner as DP-capable with pin modes C and D */
+	add_dp_discovery(partner);
+	add_displayport_mode_responses(partner);
+
+	/* Connect our port partner */
+	connect_source_to_port(&fix->partner, &fix->src_ext, 0, fix->tcpci_emul,
+			       fix->charger_emul);
+}
+
+static void console_cmd_mfallow_after(void *data)
+{
+	struct console_cmd_mfallow_fixture *fix = data;
+
+	disconnect_source_from_port(fix->tcpci_emul, fix->charger_emul);
+	tcpci_partner_common_clear_logged_msgs(&fix->partner);
+}
+
+ZTEST_SUITE(console_cmd_mfallow, drivers_predicate_post_main,
+	    console_cmd_mfallow_setup, console_cmd_mfallow_before,
+	    console_cmd_mfallow_after, NULL);
+
+ZTEST_F(console_cmd_mfallow, test_mfallow_bad_arg_num)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "mfallow");
+
+	zassert_equal(EC_ERROR_PARAM_COUNT, rv);
+}
+
+ZTEST_F(console_cmd_mfallow, test_mfallow_bad_port)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "mfallow fish true");
+
+	zassert_equal(EC_ERROR_PARAM1, rv);
+}
+
+ZTEST_F(console_cmd_mfallow, test_mfallow_bad_boolean)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "mfallow 0 sardine");
+
+	zassert_equal(EC_ERROR_PARAM2, rv);
+}
+
+ZTEST_F(console_cmd_mfallow, test_mfallow_true)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "mfallow 0 true");
+
+	zassert_equal(EC_SUCCESS, rv);
+
+	tcpci_partner_common_enable_pd_logging(&fixture->partner, true);
+	host_cmd_typec_control_enter_mode(TEST_PORT, TYPEC_MODE_DP);
+	k_sleep(K_MSEC(500));
+	tcpci_partner_common_enable_pd_logging(&fixture->partner, false);
+
+	uint32_t config_vdo = dp_config_extract(fixture);
+
+	zassert_equal(PD_DP_CFG_PIN(config_vdo), MODE_DP_PIN_D);
+}
+
+ZTEST_F(console_cmd_mfallow, test_mfallow_false)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "mfallow 0 false");
+
+	zassert_equal(EC_SUCCESS, rv);
+
+	tcpci_partner_common_enable_pd_logging(&fixture->partner, true);
+	host_cmd_typec_control_enter_mode(TEST_PORT, TYPEC_MODE_DP);
+	k_sleep(K_MSEC(500));
+	tcpci_partner_common_enable_pd_logging(&fixture->partner, false);
+
+	uint32_t config_vdo = dp_config_extract(fixture);
+
+	zassert_equal(PD_DP_CFG_PIN(config_vdo), MODE_DP_PIN_C);
+}
diff --git a/zephyr/test/drivers/cros_flash/CMakeLists.txt b/zephyr/test/drivers/cros_flash/CMakeLists.txt
new file mode 100644
index 0000000000..e4ba721303
--- /dev/null
+++ b/zephyr/test/drivers/cros_flash/CMakeLists.txt
@@ -0,0 +1,5 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_sources(app PRIVATE src/main.c)
diff --git a/zephyr/test/drivers/cros_flash/boards/native_posix.overlay b/zephyr/test/drivers/cros_flash/boards/native_posix.overlay
new file mode 100644
index 0000000000..e6be5ad416
--- /dev/null
+++ b/zephyr/test/drivers/cros_flash/boards/native_posix.overlay
@@ -0,0 +1,26 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "../../boards/native_posix.overlay"
+
+/delete-node/ &cros_flash;
+
+/ {
+	chosen {
+		cros-ec,flash-controller = &cros_flash;
+	};
+
+	soc {
+		cros_flash: cros-flash {
+			compatible = "cros-ec,cros-flash";
+		};
+	};
+};
+
+&flash0 {
+        erase-block-size = <0x4000>;
+        write-block-size = <1>;
+        reg = <0x00000000 DT_SIZE_K(512)>;
+};
diff --git a/zephyr/test/drivers/cros_flash/src/main.c b/zephyr/test/drivers/cros_flash/src/main.c
new file mode 100644
index 0000000000..48a6437f1f
--- /dev/null
+++ b/zephyr/test/drivers/cros_flash/src/main.c
@@ -0,0 +1,706 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "../../../../drivers/cros_flash/cros_flash.h"
+#include "drivers/cros_flash.h"
+#include "ec_commands.h"
+#include "flash.h"
+#include "gpio_signal.h"
+#include "system.h"
+#include "test/drivers/test_mocks.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/fff.h>
+#include <zephyr/ztest.h>
+
+#define WP_L_GPIO_PATH NAMED_GPIOS_GPIO_NODE(wp_l)
+
+static int gpio_wp_l_set(int value)
+{
+	const struct device *wp_l_gpio_dev =
+		DEVICE_DT_GET(DT_GPIO_CTLR(WP_L_GPIO_PATH, gpios));
+
+	return gpio_emul_input_set(wp_l_gpio_dev,
+				   DT_GPIO_PIN(WP_L_GPIO_PATH, gpios), value);
+}
+
+#define cros_flash_dev DEVICE_DT_GET(DT_CHOSEN(cros_ec_flash_controller))
+
+FAKE_VALUE_FUNC(int, flash_change_wp, const struct device *, uint32_t,
+		uint32_t);
+FAKE_VALUE_FUNC(int, flash_get_wp, const struct device *, uint32_t *);
+FAKE_VALUE_FUNC(int, flash_change_rdp, const struct device *, bool, bool);
+FAKE_VALUE_FUNC(int, flash_get_rdp, const struct device *, bool *, bool *);
+FAKE_VALUE_FUNC(int, flash_block_protection_changes, const struct device *);
+FAKE_VALUE_FUNC(int, flash_block_control_access, const struct device *);
+FAKE_VALUE_FUNC(const uint8_t *, system_get_jump_tag, uint16_t, int *, int *);
+
+static uint32_t protected_mask;
+static bool protection_changes_blocked;
+static bool control_access_blocked;
+static bool rdp_enabled;
+
+static struct cros_flash_protection current_protection;
+static int protection_struct_version;
+
+static const uint8_t *system_get_jump_tag_custom_fake(uint16_t tag,
+						      int *version, int *size)
+{
+	if (tag != FLASH_SYSJUMP_TAG)
+		return NULL;
+	if (version)
+		*version = protection_struct_version;
+	if (size)
+		*size = sizeof(current_protection);
+	return (uint8_t *)&current_protection;
+}
+
+static int flash_block_protection_changes_custom_fake(const struct device *dev)
+{
+	protection_changes_blocked = true;
+
+	return 0;
+}
+
+static int flash_block_control_access_custom_fake(const struct device *dev)
+{
+	control_access_blocked = true;
+
+	return 0;
+}
+
+static int flash_get_wp_custom_fake(const struct device *dev, uint32_t *wp_mask)
+{
+	*wp_mask = protected_mask;
+
+	return 0;
+}
+
+static int flash_change_wp_custom_fake(const struct device *dev,
+				       uint32_t disable_mask,
+				       uint32_t enable_mask)
+{
+	if (protection_changes_blocked)
+		ztest_test_fail();
+
+	protected_mask &= ~disable_mask;
+	protected_mask |= enable_mask;
+
+	return 0;
+}
+
+static int flash_get_rdp_custom_fake(const struct device *dev, bool *enabled,
+				     bool *permanent)
+{
+	if (enabled)
+		*enabled = rdp_enabled;
+
+	if (permanent)
+		*permanent = false;
+
+	return 0;
+}
+
+static int flash_change_rdp_custom_fake(const struct device *dev, bool enable,
+					bool permanent)
+{
+	/*
+	 * We don't support disabling RDP, enabling RDP permanently or
+	 * protection changes are blocked.
+	 */
+	if ((!enable && rdp_enabled) || permanent || protection_changes_blocked)
+		ztest_test_fail();
+
+	rdp_enabled = enable;
+
+	return 0;
+}
+
+ZTEST_USER(cros_flash, test_init_no_hwwp_no_protection)
+{
+	cros_flash_init(cros_flash_dev);
+
+	/* Check that there are no protection changes. */
+	zassert_equal(flash_change_wp_fake.call_count, 0);
+	zassert_equal(flash_change_rdp_fake.call_count, 0);
+	zassert_equal(flash_block_control_access_fake.call_count, 0);
+	zassert_equal(flash_block_protection_changes_fake.call_count, 0);
+
+	/* Check that no reset was requested. */
+	zassert_equal(system_reset_fake.call_count, 0);
+}
+
+ZTEST_USER(cros_flash, test_init_no_hwwp_protected_wp_region_success)
+{
+	/* First sector that belongs to WP region is protected. */
+	protected_mask = 0x1;
+
+	cros_flash_init(cros_flash_dev);
+
+	/* Expect that write protection was disabled. */
+	zassert_equal(flash_change_wp_fake.call_count, 1, "flash_change_wp %d",
+		      flash_change_wp_fake.call_count);
+	zassert_equal(protected_mask, 0);
+
+	/* Check if no other protection changes. */
+	zassert_equal(flash_change_rdp_fake.call_count, 0);
+
+	/* Check that reset was requested. */
+	zassert_equal(system_reset_fake.call_count, 1);
+}
+
+ZTEST_USER(cros_flash, test_init_no_hwwp_disabling_wp_failure_no_reboot)
+{
+	flash_change_wp_fake.return_val = -EINVAL;
+	flash_change_wp_fake.custom_fake = NULL;
+
+	cros_flash_init(cros_flash_dev);
+
+	/* Check that reset was NOT requested. It would lead to reboot loop */
+	zassert_equal(system_reset_fake.call_count, 0);
+}
+
+ZTEST_USER(cros_flash, test_init_no_hwwp_enabled_rdp_is_not_disabled)
+{
+	rdp_enabled = true;
+
+	cros_flash_init(cros_flash_dev);
+
+	/* Check that there was no attempt to change RDP */
+	zassert_equal(flash_change_rdp_fake.call_count, 0);
+}
+
+ZTEST_USER(cros_flash, test_init_no_hwwp_rdp_enabled_no_reboot)
+{
+	rdp_enabled = true;
+
+	cros_flash_init(cros_flash_dev);
+
+	/* Check that reset was NOT requested. It would lead to reboot loop */
+	zassert_equal(system_reset_fake.call_count, 0);
+}
+
+ZTEST_USER(cros_flash, test_init_hwwp_no_ro_at_boot_no_protection)
+{
+	/* Enable HW WP. */
+	gpio_wp_l_set(0);
+
+	cros_flash_init(cros_flash_dev);
+
+	/*
+	 * Expect that WP region is not protected, because RO_AT_BOOT is not
+	 * enabled.
+	 */
+	zassert_equal(flash_change_wp_fake.call_count, 0);
+	zassert_equal(protected_mask, 0);
+
+	/* Check that there was no attempt to change RDP. */
+	zassert_equal(flash_change_rdp_fake.call_count, 0);
+}
+
+ZTEST_USER(cros_flash, test_init_hwwp_no_ro_at_boot_no_reboot)
+{
+	/* Enable HW WP. */
+	gpio_wp_l_set(0);
+
+	cros_flash_init(cros_flash_dev);
+
+	/* Check that reset was not requested. */
+	zassert_equal(system_reset_fake.call_count, 0);
+}
+
+ZTEST_USER(cros_flash, test_init_hwwp_no_ro_at_boot_option_bytes_enabled)
+{
+	/* Enable HW WP. */
+	gpio_wp_l_set(0);
+
+	cros_flash_init(cros_flash_dev);
+
+	/*
+	 * Check that option register was not disabled. If RO_AT_BOOT is not
+	 * enabled we allow to boot without disabling option register, so we
+	 * can enable protection later.
+	 */
+	zassert_equal(flash_block_protection_changes_fake.call_count, 0);
+}
+
+ZTEST_USER(cros_flash, test_init_hwwp_no_ro_at_boot_disables_protection)
+{
+	/* Enable HW WP. */
+	gpio_wp_l_set(0);
+
+	/* Protect WP region. */
+	protected_mask = 0xffff;
+
+	cros_flash_init(cros_flash_dev);
+
+	/* Expect that WP region protection is disabled. */
+	zassert_equal(flash_change_wp_fake.call_count, 1);
+	zassert_equal(protected_mask, 0);
+
+	/* Check that reset was requested. */
+	zassert_equal(system_reset_fake.call_count, 1);
+}
+
+ZTEST_USER(cros_flash, test_init_hwwp_rdp_and_wp_enabled_no_reboot)
+{
+	/* Enable HW WP. */
+	gpio_wp_l_set(0);
+
+	/* Enable RDP. It's used as a PSTATE (source of RO_AT_BOOT flag) */
+	rdp_enabled = true;
+
+	/* Protect WP region */
+	protected_mask = 0xffff;
+
+	cros_flash_init(cros_flash_dev);
+
+	/* Expect that WP region is still protected. */
+	zassert_equal(flash_change_wp_fake.call_count, 0);
+	zassert_equal(protected_mask, 0xffff);
+
+	/* Check that reset was not requested. */
+	zassert_equal(system_reset_fake.call_count, 0);
+}
+
+ZTEST_USER(cros_flash, test_init_hwwp_rdp_and_wp_enabled_disables_option)
+{
+	/* Enable HW WP. */
+	gpio_wp_l_set(0);
+
+	/* Enable RDP. It's used as a PSTATE (source of RO_AT_BOOT flag) */
+	rdp_enabled = true;
+
+	/* Protect WP region */
+	protected_mask = 0xffff;
+
+	cros_flash_init(cros_flash_dev);
+
+	/*
+	 * Check that option register was disabled. It means that we can't
+	 * change protection later.
+	 */
+	zassert_equal(flash_block_protection_changes_fake.call_count, 1);
+}
+
+ZTEST_USER(cros_flash, test_init_hwwp_rdp_enabled_wp_disabled)
+{
+	/* Enable HW WP. */
+	gpio_wp_l_set(0);
+
+	/* Enable RDP. It's used as a PSTATE (source of RO_AT_BOOT flag). */
+	rdp_enabled = true;
+
+	cros_flash_init(cros_flash_dev);
+
+	/* Expect that WP region is protected. */
+	zassert_equal(flash_change_wp_fake.call_count, 1);
+	zassert_equal(protected_mask, 0xffff);
+
+	/* Check that reset was requested. */
+	zassert_equal(system_reset_fake.call_count, 1);
+}
+
+ZTEST_USER(cros_flash, test_init_hwwp_rdp_enabled_wp_get_failure)
+{
+	/* Enable HW WP. */
+	gpio_wp_l_set(0);
+
+	/* Enable RDP. It's used as a PSTATE (source of RO_AT_BOOT flag). */
+	rdp_enabled = true;
+
+	/* Simulate failure to get write protection status */
+	flash_get_wp_fake.return_val = -EINVAL;
+	flash_get_wp_fake.custom_fake = NULL;
+
+	cros_flash_init(cros_flash_dev);
+
+	/* Expect that WP region is protected. */
+	zassert_equal(flash_change_wp_fake.call_count, 1);
+	zassert_equal(protected_mask, 0xffff);
+
+	/* Check that reset was requested. */
+	zassert_equal(system_reset_fake.call_count, 1);
+}
+
+ZTEST_USER(cros_flash, test_init_decode_jump_data_no_data)
+{
+	/* Tell cros_flash_init() that it should restore data */
+	system_set_reset_flags(EC_RESET_FLAG_SYSJUMP);
+
+	system_get_jump_tag_fake.return_val = NULL;
+	system_get_jump_tag_fake.custom_fake = NULL;
+
+	zassert_equal(cros_flash_init(cros_flash_dev), -ENODATA);
+}
+
+ZTEST_USER(cros_flash, test_init_decode_jump_data_wrong_version)
+{
+	/* Tell cros_flash_init() that it should restore data */
+	system_set_reset_flags(EC_RESET_FLAG_SYSJUMP);
+	protection_struct_version = 2;
+
+	zassert_equal(cros_flash_init(cros_flash_dev), -ENOENT);
+}
+
+ZTEST_USER(cros_flash, test_init_decode_jump_data_success)
+{
+	/* Tell cros_flash_init() that it should restore data */
+	system_set_reset_flags(EC_RESET_FLAG_SYSJUMP);
+
+	current_protection.control_access_blocked = true;
+	current_protection.protection_changes_blocked = true;
+
+	zassert_equal(cros_flash_init(cros_flash_dev), 0);
+
+	/* Check that ALL_NOW is reported. */
+	zassert_equal(cros_flash_physical_get_protect_flags(cros_flash_dev),
+		      EC_FLASH_PROTECT_ALL_NOW);
+}
+
+ZTEST_USER(cros_flash, test_protect_now)
+{
+	cros_flash_init(cros_flash_dev);
+
+	/* Protect RO now. */
+	cros_flash_physical_protect_now(cros_flash_dev, 0);
+
+	/* Check that only option bytes are disabled. */
+	zassert_equal(flash_block_protection_changes_fake.call_count, 1);
+	zassert_equal(flash_block_control_access_fake.call_count, 0);
+}
+
+ZTEST_USER(cros_flash, test_protect_now_all)
+{
+	cros_flash_init(cros_flash_dev);
+
+	/* Protect ALL now. */
+	cros_flash_physical_protect_now(cros_flash_dev, 1);
+
+	/* Check that only option bytes are disabled. */
+	zassert_equal(flash_block_protection_changes_fake.call_count, 1);
+	zassert_equal(flash_block_control_access_fake.call_count, 1);
+}
+
+ZTEST_USER(cros_flash, test_protect_at_boot_protection_changes_blocked)
+{
+	cros_flash_init(cros_flash_dev);
+
+	/* Protect RO now. */
+	cros_flash_physical_protect_now(cros_flash_dev, 0);
+
+	/* Check that protect at boot fails */
+	zassert_equal(cros_flash_physical_protect_at_boot(
+			      cros_flash_dev, EC_FLASH_PROTECT_RO_AT_BOOT),
+		      -EACCES);
+}
+
+ZTEST_USER(cros_flash, test_protect_at_boot_hwwp_disabled_ro_at_boot)
+{
+	cros_flash_init(cros_flash_dev);
+
+	cros_flash_physical_protect_at_boot(cros_flash_dev,
+					    EC_FLASH_PROTECT_RO_AT_BOOT);
+
+	/* When HW WP is disabled we expect only RDP to be enabled. */
+	zassert_equal(flash_change_wp_fake.call_count, 0);
+	zassert_equal(flash_change_rdp_fake.call_count, 1);
+	zassert_true(rdp_enabled);
+}
+
+ZTEST_USER(cros_flash, test_protect_at_boot_hwwp_enabled_ro_at_boot)
+{
+	cros_flash_init(cros_flash_dev);
+
+	/* Enable HW WP. */
+	gpio_wp_l_set(0);
+
+	cros_flash_physical_protect_at_boot(cros_flash_dev,
+					    EC_FLASH_PROTECT_RO_AT_BOOT);
+
+	/* WP and RDP should be enabled. */
+	zassert_equal(flash_change_wp_fake.call_count, 1);
+	zassert_equal(protected_mask, 0xffff);
+	zassert_equal(flash_change_rdp_fake.call_count, 1);
+	zassert_true(rdp_enabled);
+}
+
+ZTEST_USER(cros_flash, test_protect_at_boot_hwwp_enabled_ro_at_boot_rdp_failed)
+{
+	cros_flash_init(cros_flash_dev);
+
+	/* Enable HW WP. */
+	gpio_wp_l_set(0);
+
+	flash_change_rdp_fake.custom_fake = NULL;
+	flash_change_rdp_fake.return_val = -EINVAL;
+
+	zassert_equal(cros_flash_physical_protect_at_boot(
+			      cros_flash_dev, EC_FLASH_PROTECT_RO_AT_BOOT),
+		      -EINVAL);
+
+	/* WP should be enabled. */
+	zassert_equal(flash_change_wp_fake.call_count, 1);
+	zassert_equal(protected_mask, 0xffff);
+	zassert_equal(flash_change_rdp_fake.call_count, 1);
+}
+
+ZTEST_USER(cros_flash, test_protect_at_boot_hwwp_enabled_ro_at_boot_wp_failed)
+{
+	cros_flash_init(cros_flash_dev);
+
+	/* Enable HW WP. */
+	gpio_wp_l_set(0);
+
+	flash_change_wp_fake.custom_fake = NULL;
+	flash_change_wp_fake.return_val = -EINVAL;
+
+	zassert_equal(cros_flash_physical_protect_at_boot(
+			      cros_flash_dev, EC_FLASH_PROTECT_RO_AT_BOOT),
+		      -EINVAL);
+
+	/* RDP should be enabled. */
+	zassert_equal(flash_change_wp_fake.call_count, 1);
+	zassert_equal(flash_change_rdp_fake.call_count, 1);
+	zassert_true(rdp_enabled);
+}
+
+ZTEST_USER(cros_flash, test_protect_at_boot_hwwp_enabled_all_at_boot)
+{
+	cros_flash_init(cros_flash_dev);
+
+	/* Enable HW WP. */
+	gpio_wp_l_set(0);
+
+	cros_flash_physical_protect_at_boot(cros_flash_dev,
+					    EC_FLASH_PROTECT_ALL_AT_BOOT);
+
+	/* Whole flash should be protected, but RDP disabled. */
+	zassert_equal(flash_change_wp_fake.call_count, 1);
+	zassert_equal(protected_mask, 0xffffffff);
+	zassert_equal(flash_change_rdp_fake.call_count, 0);
+}
+
+ZTEST_USER(cros_flash, test_protect_at_boot_hwwp_enabled_ro_all_at_boot)
+{
+	cros_flash_init(cros_flash_dev);
+
+	/* Enable HW WP. */
+	gpio_wp_l_set(0);
+
+	cros_flash_physical_protect_at_boot(
+		cros_flash_dev,
+		EC_FLASH_PROTECT_ALL_AT_BOOT | EC_FLASH_PROTECT_RO_AT_BOOT);
+
+	/* Whole flash should be protected, but RDP disabled. */
+	zassert_equal(flash_change_wp_fake.call_count, 1);
+	zassert_equal(protected_mask, 0xffffffff);
+	zassert_equal(flash_change_rdp_fake.call_count, 1);
+	zassert_true(rdp_enabled);
+}
+
+ZTEST_USER(cros_flash, test_get_protect_flags)
+{
+	cros_flash_init(cros_flash_dev);
+
+	/* Check that nothing is reported. */
+	zassert_equal(cros_flash_physical_get_protect_flags(cros_flash_dev), 0);
+}
+
+ZTEST_USER(cros_flash, test_get_protect_flags_control_disabled)
+{
+	cros_flash_init(cros_flash_dev);
+
+	/* Protect ALL now. */
+	cros_flash_physical_protect_now(cros_flash_dev, 1);
+
+	/* Check that ALL_NOW is reported. */
+	zassert_equal(cros_flash_physical_get_protect_flags(cros_flash_dev),
+		      EC_FLASH_PROTECT_ALL_NOW);
+}
+
+ZTEST_USER(cros_flash, test_get_protect_flags_rdp_enabled)
+{
+	cros_flash_init(cros_flash_dev);
+
+	/* Enable RDP. */
+	rdp_enabled = true;
+
+	/* Check that RO_AT_BOOT is reported. */
+	zassert_equal(cros_flash_physical_get_protect_flags(cros_flash_dev),
+		      EC_FLASH_PROTECT_RO_AT_BOOT);
+}
+
+ZTEST_USER(cros_flash, test_get_protect_flags_rdp_enabled_control_disabled)
+{
+	cros_flash_init(cros_flash_dev);
+
+	/* Protect ALL now. */
+	cros_flash_physical_protect_now(cros_flash_dev, 1);
+
+	/* Enable RDP. */
+	rdp_enabled = true;
+
+	/* Check that RO_AT_BOOT is reported. */
+	zassert_equal(cros_flash_physical_get_protect_flags(cros_flash_dev),
+		      EC_FLASH_PROTECT_ALL_NOW | EC_FLASH_PROTECT_RO_AT_BOOT);
+}
+
+ZTEST_USER(cros_flash, test_get_protect_flags_failed_to_get_rdp)
+{
+	cros_flash_init(cros_flash_dev);
+
+	flash_get_rdp_fake.return_val = -ENOTSUP;
+	flash_get_rdp_fake.custom_fake = NULL;
+
+	/* Check that error is reported. */
+	zassert_equal(cros_flash_physical_get_protect_flags(cros_flash_dev),
+		      EC_FLASH_PROTECT_ERROR_UNKNOWN);
+}
+
+ZTEST_USER(cros_flash, test_get_protect)
+{
+	cros_flash_init(cros_flash_dev);
+
+	protected_mask = 0x10001;
+
+	zassert_true(cros_flash_physical_get_protect(cros_flash_dev, 0));
+	zassert_true(cros_flash_physical_get_protect(cros_flash_dev, 16));
+	zassert_false(cros_flash_physical_get_protect(cros_flash_dev, 15));
+}
+
+ZTEST_USER(cros_flash, test_get_protect_control_disabled)
+{
+	cros_flash_init(cros_flash_dev);
+
+	/* Protect ALL now. */
+	cros_flash_physical_protect_now(cros_flash_dev, 1);
+
+	/* Check that protection is enabled inside and outside WP region. */
+	zassert_true(cros_flash_physical_get_protect(cros_flash_dev, 0));
+	zassert_true(cros_flash_physical_get_protect(cros_flash_dev, 31));
+}
+
+ZTEST_USER(cros_flash, test_get_protect_failure)
+{
+	cros_flash_init(cros_flash_dev);
+
+	flash_get_wp_fake.return_val = -EINVAL;
+	flash_get_wp_fake.custom_fake = NULL;
+
+	/* Check that protection is disabled on sectors. */
+	zassert_false(cros_flash_physical_get_protect(cros_flash_dev, 0));
+	zassert_false(cros_flash_physical_get_protect(cros_flash_dev, 31));
+}
+
+ZTEST_USER(cros_flash, test_write)
+{
+	cros_flash_init(cros_flash_dev);
+
+	uint32_t some_value = 42;
+
+	cros_flash_physical_write(cros_flash_dev, 0x4000, sizeof(some_value),
+				  (const char *)&some_value);
+
+	uint32_t read_value = 0;
+
+	crec_flash_physical_read(0x4000, sizeof(read_value),
+				 (char *)&read_value);
+
+	zassert_equal(some_value, read_value);
+}
+
+ZTEST_USER(cros_flash, test_erase)
+{
+	cros_flash_init(cros_flash_dev);
+
+	uint32_t some_value = 42;
+
+	cros_flash_physical_write(cros_flash_dev, 0x4000, sizeof(some_value),
+				  (const char *)&some_value);
+
+	cros_flash_physical_erase(cros_flash_dev, 0x4000,
+				  DT_PROP(DT_CHOSEN(cros_ec_flash),
+					  erase_block_size));
+
+	uint32_t read_value = 0;
+
+	crec_flash_physical_read(0x4000, sizeof(read_value),
+				 (char *)&read_value);
+
+	zassert_not_equal(some_value, read_value);
+}
+
+ZTEST_USER(cros_flash, test_write_control_disabled)
+{
+	cros_flash_init(cros_flash_dev);
+
+	/* Protect ALL now. */
+	cros_flash_physical_protect_now(cros_flash_dev, 1);
+
+	uint32_t some_value = 42;
+
+	zassert_equal(cros_flash_physical_write(cros_flash_dev, 0x4000,
+						sizeof(some_value),
+						(const char *)&some_value),
+		      -EACCES);
+}
+
+ZTEST_USER(cros_flash, test_erase_control_disabled)
+{
+	cros_flash_init(cros_flash_dev);
+
+	/* Protect ALL now. */
+	cros_flash_physical_protect_now(cros_flash_dev, 1);
+
+	zassert_equal(
+		cros_flash_physical_erase(cros_flash_dev, 0x4000,
+					  DT_PROP(DT_CHOSEN(cros_ec_flash),
+						  erase_block_size)),
+		-EACCES);
+}
+
+void cros_flash_before(void *fixture)
+{
+	/* Disable HW WP. */
+	gpio_wp_l_set(1);
+
+	protected_mask = 0x0;
+	RESET_FAKE(flash_change_wp);
+	RESET_FAKE(flash_get_wp);
+
+	rdp_enabled = false;
+	RESET_FAKE(flash_change_rdp);
+	RESET_FAKE(flash_get_rdp);
+
+	protection_changes_blocked = false;
+	control_access_blocked = false;
+	RESET_FAKE(flash_block_protection_changes);
+	RESET_FAKE(flash_block_control_access);
+
+	RESET_FAKE(system_reset);
+
+	current_protection.control_access_blocked = false;
+	current_protection.protection_changes_blocked = false;
+	protection_struct_version = 1;
+	RESET_FAKE(system_get_jump_tag)
+
+	system_clear_reset_flags(0xffffffff);
+
+	flash_get_wp_fake.custom_fake = flash_get_wp_custom_fake;
+	flash_change_wp_fake.custom_fake = flash_change_wp_custom_fake;
+	flash_get_rdp_fake.custom_fake = flash_get_rdp_custom_fake;
+	flash_change_rdp_fake.custom_fake = flash_change_rdp_custom_fake;
+	flash_block_protection_changes_fake.custom_fake =
+		flash_block_protection_changes_custom_fake;
+	flash_block_control_access_fake.custom_fake =
+		flash_block_control_access_custom_fake;
+	system_get_jump_tag_fake.custom_fake = system_get_jump_tag_custom_fake;
+}
+
+ZTEST_SUITE(cros_flash, drivers_predicate_post_main, NULL, cros_flash_before,
+	    NULL, NULL);
diff --git a/zephyr/test/drivers/default/CMakeLists.txt b/zephyr/test/drivers/default/CMakeLists.txt
new file mode 100644
index 0000000000..757239590b
--- /dev/null
+++ b/zephyr/test/drivers/default/CMakeLists.txt
@@ -0,0 +1,68 @@
+target_sources(app PRIVATE
+    src/battery.c
+    src/bb_retimer.c
+    src/bma2x2.c
+    src/bma4xx.c
+    src/bmi_common.c
+    src/bmi160.c
+    src/bmi260.c
+    src/charge_manager.c
+    src/charge_ramp.c
+    src/charge_state_prevent_power_on.c
+    src/console.c
+    src/cros_cbi.c
+    src/espi.c
+    src/gpio.c
+    src/integration/usbc/usb.c
+    src/integration/usbc/usb_20v_3a_pd_charger.c
+    src/integration/usbc/usb_5v_3a_pd_sink.c
+    src/integration/usbc/usb_5v_3a_pd_source.c
+    src/integration/usbc/usb_attach_src_snk.c
+    src/integration/usbc/usb_hard_reset.c
+    src/integration/usbc/usb_pd_bist_shared.c
+    src/integration/usbc/usb_pd_ctrl_msg.c
+    src/integration/usbc/usb_pd_rev3.c
+    src/i2c.c
+    src/i2c_passthru.c
+    src/isl923x.c
+    src/led.c
+    src/lid_angle.c
+    src/lid_switch.c
+    src/lis2dw12.c
+    src/ln9310.c
+    src/locate_chip.c
+    src/motion_sense/motion_sense.c
+    src/panic.c
+    src/panic_output.c
+    src/port80.c
+    src/power_common.c
+    src/ppc_sn5s330.c
+    src/ppc_syv682x.c
+    src/ps8xxx.c
+    src/smart.c
+    src/stm_mems_common.c
+    src/tablet_mode.c
+    src/task.c
+    src/tcpci.c
+    src/tcpci_test_common.c
+    src/tcpm_header.c
+    src/tcs3400.c
+    src/temp_sensor.c
+    src/thermistor.c
+    src/uart_hostcmd.c
+    src/usb_mux.c
+    src/util.c
+    src/vboot_hash.c
+    src/virtual_battery.c
+    src/vstore.c
+    src/watchdog.c
+)
+
+add_subdirectory(
+    ${PLATFORM_EC}/zephyr/test/drivers/mock_panic_output
+    mock_panic_output
+)
+
+# This test does not work when power functions are mocked, so only run it for
+# the plain `drivers.default` test case.
+zephyr_library_sources_ifndef(CONFIG_POWER_SEQUENCE_MOCK src/chipset.c)
diff --git a/zephyr/test/drivers/default/boards/native_posix.overlay b/zephyr/test/drivers/default/boards/native_posix.overlay
new file mode 100644
index 0000000000..a5e73e5653
--- /dev/null
+++ b/zephyr/test/drivers/default/boards/native_posix.overlay
@@ -0,0 +1,34 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "../../boards/native_posix.overlay"
+
+/*
+ * The TCPCI test verfies the mux behavior in two configurations:
+ *   flags = USB_MUX_FLAG_NOT_TCPC;
+ *   flags = 0;
+ *
+ * When USB_MUX_FLAG_NOT_TCPC is set, the TCPCI mux driver must initialize
+ * the I2C bus and address from the devicetree.
+ *
+ * The TCPCI mux doesn't have it's owm emulator and sends it's I2C transactions
+ * through the normal TCPCI driver, which then connects to the TCPCI emulator.
+ *
+ * Use 2 compaible strings here so that the same I2C device node gets setup for
+ * both the emulator and the TPCI mux.
+ */
+&tcpci_emul {
+	compatible = "cros,tcpci-generic-emul", "cros-ec,usbc-mux-tcpci";
+};
+
+/ {
+	usbc {
+		port0@0 {
+			usb-mux-chain-0 {
+				usb-muxes = <&tcpci_emul &virtual_mux_c0>;
+			};
+		};
+	};
+};
diff --git a/zephyr/test/drivers/default/boards/power_button.dtsi b/zephyr/test/drivers/default/boards/power_button.dtsi
new file mode 100644
index 0000000000..f16a81bcbb
--- /dev/null
+++ b/zephyr/test/drivers/default/boards/power_button.dtsi
@@ -0,0 +1,19 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include <dt-bindings/buttons.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	gpio-keys {
+		compatible = "zephyr,gpio-keys";
+		debounce-interval-ms = <30>;
+		power_button: power_button {
+			gpios = <&gpio0 25 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			/* TODO: use an INPUT_KEY code here. */
+			zephyr,code = <BUTTON_POWER>;
+		};
+	};
+
+};
diff --git a/zephyr/test/drivers/default/prj.conf b/zephyr/test/drivers/default/prj.conf
new file mode 100644
index 0000000000..d125545fdb
--- /dev/null
+++ b/zephyr/test/drivers/default/prj.conf
@@ -0,0 +1,15 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_PLATFORM_EC_CMD_BUTTON=y
+CONFIG_PLATFORM_EC_CMD_POWERINDEBUG=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_RTC=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_RTC_ALARM=y
+CONFIG_PLATFORM_EC_RTC=y
+CONFIG_PLATFORM_EC_VOLUME_BUTTONS=y
+CONFIG_TASK_HOSTCMD_THREAD_MAIN=y
+
+CONFIG_SYSTEM_FAKE=y
+CONFIG_GPIO_GET_CONFIG=y
+CONFIG_PLATFORM_EC_CHARGER_INPUT_CURRENT_DERATE_PCT=0
diff --git a/zephyr/test/drivers/default/src/battery.c b/zephyr/test/drivers/default/src/battery.c
new file mode 100644
index 0000000000..a5d1dcad0c
--- /dev/null
+++ b/zephyr/test/drivers/default/src/battery.c
@@ -0,0 +1,242 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "battery_fuel_gauge.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_smart_battery.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/fff.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+#define GPIO_BATT_PRES_ODL_PATH NAMED_GPIOS_GPIO_NODE(ec_batt_pres_odl)
+#define GPIO_BATT_PRES_ODL_PORT DT_GPIO_PIN(GPIO_BATT_PRES_ODL_PATH, gpios)
+
+FAKE_VALUE_FUNC(int, battery2_write_func, const struct emul *, int, uint8_t,
+		int, void *);
+FAKE_VALUE_FUNC(int, battery2_read_func, const struct emul *, int, uint8_t *,
+		int, void *);
+
+bool authenticate_battery_type(int index, const char *manuf_name);
+
+extern int battery_fuel_gauge_type_override;
+
+struct battery_fixture {
+	struct i2c_common_emul_data *battery_i2c_common;
+	i2c_common_emul_finish_write_func finish_write_func;
+	i2c_common_emul_start_read_func start_read_func;
+};
+
+static void *battery_setup(void)
+{
+	static struct battery_fixture fixture;
+	static const struct emul *emul = EMUL_DT_GET(DT_NODELABEL(battery));
+
+	fixture.battery_i2c_common =
+		emul_smart_battery_get_i2c_common_data(emul);
+
+	return &fixture;
+}
+
+static void battery_before(void *data)
+{
+	struct battery_fixture *fixture = data;
+
+	RESET_FAKE(battery2_write_func);
+	RESET_FAKE(battery2_read_func);
+	fixture->finish_write_func = fixture->battery_i2c_common->finish_write;
+	fixture->start_read_func = fixture->battery_i2c_common->start_read;
+}
+
+static void battery_after(void *data)
+{
+	struct battery_fixture *fixture = data;
+	const struct device *dev =
+		DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_BATT_PRES_ODL_PATH, gpios));
+
+	/* Set default state (battery is present) */
+	gpio_emul_input_set(dev, GPIO_BATT_PRES_ODL_PORT, 0);
+	battery_fuel_gauge_type_override = -1;
+
+	i2c_common_emul_set_write_func(fixture->battery_i2c_common, NULL, NULL);
+	i2c_common_emul_set_read_func(fixture->battery_i2c_common, NULL, NULL);
+	fixture->battery_i2c_common->finish_write = fixture->finish_write_func;
+	fixture->battery_i2c_common->start_read = fixture->start_read_func;
+}
+
+ZTEST_SUITE(battery, drivers_predicate_post_main, battery_setup, battery_before,
+	    battery_after, NULL);
+
+ZTEST_USER(battery, test_battery_is_present_gpio)
+{
+	const struct device *dev =
+		DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_BATT_PRES_ODL_PATH, gpios));
+
+	zassert_not_null(dev, NULL);
+	/* ec_batt_pres_odl = 0 means battery present. */
+	zassert_ok(gpio_emul_input_set(dev, GPIO_BATT_PRES_ODL_PORT, 0));
+	zassert_equal(BP_YES, battery_is_present());
+	/* ec_batt_pres_odl = 1 means battery missing. */
+	zassert_ok(gpio_emul_input_set(dev, GPIO_BATT_PRES_ODL_PORT, 1));
+	zassert_equal(BP_NO, battery_is_present());
+}
+
+ZTEST(battery, test_authenticate_battery_type)
+{
+	/* Invalid index */
+	zassert_false(authenticate_battery_type(BATTERY_TYPE_COUNT, NULL));
+	/* Use fuel-gauge 1's manufacturer name for index 0 */
+	zassert_false(authenticate_battery_type(
+		0, board_battery_info[1].fuel_gauge.manuf_name));
+	/* Use the correct manufacturer name, but wrong device name (because the
+	 * index is 1 and not 0)
+	 */
+	zassert_false(authenticate_battery_type(
+		1, board_battery_info[1].fuel_gauge.manuf_name));
+}
+
+ZTEST(battery, test_board_get_default_battery_type)
+{
+	zassert_equal(DEFAULT_BATTERY_TYPE, board_get_default_battery_type());
+}
+
+ZTEST_F(battery, test_board_cutoff_actuates_driver)
+{
+	/* We check the return type because board_is_cut_off() is set outside of
+	 * board_cut_off_battery() and may be changed by other factors.
+	 */
+
+	/* Setup error conditions for battery 1*/
+	battery_fuel_gauge_type_override = 1;
+	fixture->battery_i2c_common->finish_write = NULL;
+	i2c_common_emul_set_write_func(fixture->battery_i2c_common,
+				       battery2_write_func, NULL);
+
+	/* Check that i2c error returns EC_RES_ERROR */
+	battery2_write_func_fake.return_val = -1;
+	zassert_equal(EC_RES_ERROR, board_cut_off_battery());
+
+	/* Check for OK when i2c succeeds */
+	battery2_write_func_fake.return_val = 0;
+	zassert_ok(board_cut_off_battery());
+}
+
+ZTEST_F(battery, test_sleep)
+{
+	/* Check 1st battery (lgc,ac17a8m) */
+	battery_fuel_gauge_type_override = 0;
+	zassert_equal(EC_ERROR_UNIMPLEMENTED, battery_sleep_fuel_gauge());
+
+	/* Check 2nd battery (panasonic,ap15l5j) */
+	battery_fuel_gauge_type_override = 1;
+	fixture->battery_i2c_common->finish_write = NULL;
+	i2c_common_emul_set_write_func(fixture->battery_i2c_common,
+				       battery2_write_func, NULL);
+	zassert_ok(battery_sleep_fuel_gauge());
+}
+
+struct battery2_read_data {
+	size_t count;
+	const uint8_t *values;
+};
+
+static int battery2_read(const struct emul *target, int reg, uint8_t *val,
+			 int bytes, void *d)
+{
+	struct battery2_read_data *data = d;
+
+	if (bytes < data->count) {
+		*val = data->values[bytes];
+	}
+
+	return 0;
+}
+
+ZTEST(battery, test_is_charge_fet_disabled__cfet_mask_is_0)
+{
+	battery_fuel_gauge_type_override = 2;
+	zassert_equal(0, battery_is_charge_fet_disabled());
+}
+
+ZTEST_F(battery, test_is_charge_fet_disabled__i2c_error)
+{
+	/* Set the battery to battery 1 */
+	battery_fuel_gauge_type_override = 1;
+
+	/* Override the finish_write common callback since we don't actually
+	 * want to be messing with the emulator.
+	 */
+	fixture->battery_i2c_common->finish_write = NULL;
+
+	/* Set up an error condition for battery 1 to fail writing to i2c */
+	battery2_write_func_fake.return_val = -1;
+	i2c_common_emul_set_write_func(fixture->battery_i2c_common,
+				       battery2_write_func, NULL);
+
+	/* Verify the error */
+	zassert_equal(-1, battery_is_charge_fet_disabled());
+}
+
+ZTEST_F(battery, test_is_charge_fet_disabled)
+{
+	static uint8_t values[] = { 0x20, 0x54 };
+
+	static struct battery2_read_data data = {
+		.count = ARRAY_SIZE(values),
+		.values = values,
+	};
+
+	/* Set up the fake read function */
+	battery2_read_func_fake.custom_fake = battery2_read;
+	i2c_common_emul_set_read_func(fixture->battery_i2c_common,
+				      battery2_read_func, &data);
+
+	/* Override the finish_write and start_read common callback since we
+	 * don't actually want to be messing with the emulator.
+	 */
+	fixture->battery_i2c_common->finish_write = NULL;
+	fixture->battery_i2c_common->start_read = NULL;
+
+	zassert_equal(1, battery_is_charge_fet_disabled());
+}
+
+ZTEST_F(battery, test_get_disconnect_state__fail_i2c_read)
+{
+	/* Use battery 0 */
+	battery_fuel_gauge_type_override = 0;
+
+	/* Configure i2c to fail on read */
+	battery2_read_func_fake.return_val = -1;
+	i2c_common_emul_set_read_func(fixture->battery_i2c_common,
+				      battery2_read_func, NULL);
+
+	/* Check for disconnect error */
+	zassert_equal(BATTERY_DISCONNECT_ERROR, battery_get_disconnect_state());
+}
+
+ZTEST_F(battery, test_get_disconnect_state)
+{
+	static const uint8_t values[] = { 0x00, 0x20 };
+	static struct battery2_read_data data = {
+		.count = ARRAY_SIZE(values),
+		.values = values,
+	};
+
+	/* Use battery 0 */
+	battery_fuel_gauge_type_override = 0;
+
+	/* Enable i2c reads and set them to always return 0x2000 */
+	battery2_read_func_fake.custom_fake = battery2_read;
+	i2c_common_emul_set_read_func(fixture->battery_i2c_common,
+				      battery2_read_func, &data);
+
+	zassert_equal(BATTERY_DISCONNECTED, battery_get_disconnect_state());
+}
diff --git a/zephyr/test/drivers/default/src/bb_retimer.c b/zephyr/test/drivers/default/src/bb_retimer.c
new file mode 100644
index 0000000000..ea335c2965
--- /dev/null
+++ b/zephyr/test/drivers/default/src/bb_retimer.c
@@ -0,0 +1,654 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "chipset.h"
+#include "common.h"
+#include "driver/retimer/bb_retimer.h"
+#include "ec_tasks.h"
+#include "emul/emul_bb_retimer.h"
+#include "emul/emul_common_i2c.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "usb_prl_sm.h"
+#include "usb_tc_sm.h"
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+#define GPIO_USB_C1_LS_EN_PATH NAMED_GPIOS_GPIO_NODE(usb_c1_ls_en)
+#define GPIO_USB_C1_LS_EN_PORT DT_GPIO_PIN(GPIO_USB_C1_LS_EN_PATH, gpios)
+#define GPIO_USB_C1_RT_RST_ODL_PATH NAMED_GPIOS_GPIO_NODE(usb_c1_rt_rst_odl)
+#define GPIO_USB_C1_RT_RST_ODL_PORT \
+	DT_GPIO_PIN(GPIO_USB_C1_RT_RST_ODL_PATH, gpios)
+#define BB_RETIMER_NODE DT_NODELABEL(usb_c1_bb_retimer_emul)
+
+/** Test is retimer fw update capable function. */
+ZTEST_USER(bb_retimer, test_bb_is_fw_update_capable)
+{
+	/* BB retimer is fw update capable */
+	zassert_true(bb_usb_retimer.is_retimer_fw_update_capable());
+}
+
+/** Test is retimer fw update capable function. */
+ZTEST_USER(bb_retimer_no_tasks, test_bb_set_state)
+{
+	struct pd_discovery *disc;
+	uint32_t conn, exp_conn;
+	const struct emul *emul = EMUL_DT_GET(BB_RETIMER_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bb_retimer_get_i2c_common_data(emul);
+	bool ack_required;
+
+	set_test_runner_tid();
+
+	/* Setup emulator fail on write */
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   BB_RETIMER_REG_CONNECTION_STATE);
+
+	/* Test fail on reset register write */
+	zassert_equal(EC_ERROR_INVAL,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_NONE, &ack_required),
+		      NULL);
+	zassert_false(ack_required, "ACK is never required for BB retimer");
+
+	/* Do not fail on write */
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Set UFP role for whole test */
+	tc_set_data_role(USBC_PORT_C1, PD_ROLE_UFP);
+	zassert_equal(PD_ROLE_UFP, pd_get_data_role(USBC_PORT_C1));
+
+	/* Test none mode */
+	bb_emul_set_reg(emul, BB_RETIMER_REG_CONNECTION_STATE, 0x12144678);
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_NONE, &ack_required),
+		      NULL);
+	zassert_false(ack_required, "ACK is never required for BB retimer");
+	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
+	/* Only UFP mode is set */
+	exp_conn = BB_RETIMER_USB_DATA_ROLE;
+	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
+		      exp_conn, conn);
+
+	/* Test USB3 gen1 mode */
+	prl_set_rev(USBC_PORT_C1, TCPCI_MSG_SOP_PRIME, PD_REV10);
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_USB_ENABLED, &ack_required),
+		      NULL);
+	zassert_false(ack_required, "ACK is never required for BB retimer");
+	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
+	exp_conn = BB_RETIMER_USB_DATA_ROLE |
+		   BB_RETIMER_DATA_CONNECTION_PRESENT |
+		   BB_RETIMER_USB_3_CONNECTION;
+	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
+		      exp_conn, conn);
+
+	/* Test USB3 gen2 mode */
+	disc = pd_get_am_discovery_and_notify_access(USBC_PORT_C1,
+						     TCPCI_MSG_SOP_PRIME);
+	disc->identity.product_t1.p_rev30.ss = USB_R30_SS_U32_U40_GEN2;
+	prl_set_rev(USBC_PORT_C1, TCPCI_MSG_SOP_PRIME, PD_REV30);
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_USB_ENABLED, &ack_required),
+		      NULL);
+	zassert_false(ack_required, "ACK is never required for BB retimer");
+	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
+	exp_conn = BB_RETIMER_USB_DATA_ROLE |
+		   BB_RETIMER_DATA_CONNECTION_PRESENT |
+		   BB_RETIMER_USB_3_CONNECTION | BB_RETIMER_USB_3_SPEED;
+	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
+		      exp_conn, conn);
+
+	/* Test TBT mode */
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_TBT_COMPAT_ENABLED,
+					 &ack_required),
+		      NULL);
+	zassert_false(ack_required, "ACK is never required for BB retimer");
+	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
+	exp_conn = BB_RETIMER_USB_DATA_ROLE |
+		   BB_RETIMER_DATA_CONNECTION_PRESENT |
+		   BB_RETIMER_TBT_CONNECTION;
+	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
+		      exp_conn, conn);
+
+	/* Test USB4 mode */
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_USB4_ENABLED,
+					 &ack_required),
+		      NULL);
+	zassert_false(ack_required, "ACK is never required for BB retimer");
+	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
+	exp_conn = BB_RETIMER_USB_DATA_ROLE |
+		   BB_RETIMER_DATA_CONNECTION_PRESENT | BB_RETIMER_USB4_ENABLED;
+	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
+		      exp_conn, conn);
+
+	/* Test USB4 mode with polarity inverted */
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_USB4_ENABLED |
+						 USB_PD_MUX_POLARITY_INVERTED,
+					 &ack_required),
+		      NULL);
+	zassert_false(ack_required, "ACK is never required for BB retimer");
+	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
+	exp_conn = BB_RETIMER_USB_DATA_ROLE |
+		   BB_RETIMER_DATA_CONNECTION_PRESENT |
+		   BB_RETIMER_CONNECTION_ORIENTATION | BB_RETIMER_USB4_ENABLED;
+	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
+		      exp_conn, conn);
+
+	/* Test DP mode */
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_DP_ENABLED, &ack_required),
+		      NULL);
+	zassert_false(ack_required, "ACK is never required for BB retimer");
+	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
+	exp_conn = BB_RETIMER_USB_DATA_ROLE |
+		   BB_RETIMER_DATA_CONNECTION_PRESENT |
+		   BB_RETIMER_DP_CONNECTION;
+	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
+		      exp_conn, conn);
+
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_DP_ENABLED |
+						 USB_PD_MUX_HPD_IRQ,
+					 &ack_required),
+		      NULL);
+	zassert_false(ack_required, "ACK is never required for BB retimer");
+	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
+	exp_conn = BB_RETIMER_USB_DATA_ROLE |
+		   BB_RETIMER_DATA_CONNECTION_PRESENT |
+		   BB_RETIMER_DP_CONNECTION | BB_RETIMER_IRQ_HPD;
+	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
+		      exp_conn, conn);
+
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_DP_ENABLED |
+						 USB_PD_MUX_HPD_LVL,
+					 &ack_required),
+		      NULL);
+	zassert_false(ack_required, "ACK is never required for BB retimer");
+	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
+	exp_conn = BB_RETIMER_USB_DATA_ROLE |
+		   BB_RETIMER_DATA_CONNECTION_PRESENT |
+		   BB_RETIMER_DP_CONNECTION | BB_RETIMER_HPD_LVL;
+	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
+		      exp_conn, conn);
+}
+
+/** Test retimer idle mode setting. */
+ZTEST_USER(bb_retimer_no_tasks, test_bb_set_idle_mode)
+{
+	const uint32_t usb3_conn =
+		BB_RETIMER_ACTIVE_PASSIVE | BB_RETIMER_USB_3_SPEED |
+		BB_RETIMER_USB_3_CONNECTION | BB_RETIMER_RE_TIMER_DRIVER |
+		BB_RETIMER_DATA_CONNECTION_PRESENT;
+	const uint32_t idle_conn =
+		BB_RETIMER_ACTIVE_PASSIVE | BB_RETIMER_USB_3_SPEED |
+		BB_RETIMER_RE_TIMER_DRIVER | BB_RETIMER_DATA_CONNECTION_PRESENT;
+	const struct emul *emul = EMUL_DT_GET(BB_RETIMER_NODE);
+	struct usb_mux usb_mux_c1;
+	uint32_t conn;
+	bool ack_required;
+
+	set_test_runner_tid();
+
+	/* Enable IDLE mode port C1 mux */
+	usb_mux_c1 = *usb_muxes[USBC_PORT_C1].mux;
+	usb_mux_c1.flags |= USB_MUX_FLAG_CAN_IDLE;
+
+	/* Check if USB3 is enabled before idle entry */
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(&usb_mux_c1, USB_PD_MUX_USB_ENABLED,
+					 &ack_required),
+		      NULL);
+	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
+	zassert_equal(conn, usb3_conn, "Expected state 0x%02x, got 0x%02x",
+		      usb3_conn, conn);
+
+	/* Check if USB3 is disabled on idle entry */
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set_idle_mode(&usb_mux_c1, true), NULL);
+	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
+	zassert_equal(conn, idle_conn, "Expected state 0x%02x, got 0x%02x",
+		      idle_conn, conn);
+
+	/* Check if USB3 is re-enabled on idle exit */
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set_idle_mode(&usb_mux_c1, false), NULL);
+	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
+	zassert_equal(conn, usb3_conn, "Expected state 0x%02x, got 0x%02x",
+		      usb3_conn, conn);
+}
+
+/** Test retimer dp connection setting. */
+ZTEST_USER(bb_retimer_no_tasks, test_bb_retimer_set_dp_connection)
+{
+	const uint32_t enable_dp_conn = BB_RETIMER_DP_CONNECTION;
+	const uint32_t disable_dp_conn = 0;
+	const struct emul *emul = EMUL_DT_GET(BB_RETIMER_NODE);
+	struct usb_mux usb_mux_c1;
+	uint32_t conn;
+
+	set_test_runner_tid();
+
+	usb_mux_c1 = *usb_muxes[USBC_PORT_C1].mux;
+
+	/* Check if DP is enabled */
+	zassert_equal(EC_SUCCESS,
+		      bb_retimer_set_dp_connection(&usb_mux_c1, true), NULL);
+	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
+	zassert_equal(conn, enable_dp_conn, "Expected state 0x%02x, got 0x%02x",
+		      enable_dp_conn, conn);
+
+	/* Check if DP is disabled */
+	zassert_equal(EC_SUCCESS,
+		      bb_retimer_set_dp_connection(&usb_mux_c1, false), NULL);
+	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
+	zassert_equal(conn, disable_dp_conn,
+		      "Expected state 0x%02x, got 0x%02x", disable_dp_conn,
+		      conn);
+}
+
+/** Test setting different options for DFP role */
+ZTEST_USER(bb_retimer_no_tasks, test_bb_set_dfp_state)
+{
+	union tbt_mode_resp_device device_resp;
+	union tbt_mode_resp_cable cable_resp;
+	struct pd_discovery *disc, *dev_disc;
+	uint32_t conn, exp_conn;
+	const struct emul *emul = EMUL_DT_GET(BB_RETIMER_NODE);
+	bool ack_required;
+
+	set_test_runner_tid();
+
+	tc_set_data_role(USBC_PORT_C1, PD_ROLE_DFP);
+	zassert_equal(PD_ROLE_DFP, pd_get_data_role(USBC_PORT_C1));
+
+	/* Test PD mux none mode with DFP should clear all bits in state */
+	bb_emul_set_reg(emul, BB_RETIMER_REG_CONNECTION_STATE, 0x12144678);
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_NONE, &ack_required),
+		      NULL);
+	zassert_false(ack_required, "ACK is never required for BB retimer");
+	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
+	exp_conn = 0;
+	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
+		      exp_conn, conn);
+
+	/* Set active cable type */
+	disc = pd_get_am_discovery_and_notify_access(USBC_PORT_C1,
+						     TCPCI_MSG_SOP_PRIME);
+	disc->identity.idh.product_type = IDH_PTYPE_ACABLE;
+	disc->identity.product_t2.a2_rev30.active_elem = ACTIVE_RETIMER;
+	disc->identity.product_t1.p_rev30.ss = USB_R30_SS_U32_U40_GEN2;
+	prl_set_rev(USBC_PORT_C1, TCPCI_MSG_SOP_PRIME, PD_REV30);
+
+	/* Set cable VDO */
+	disc->svid_cnt = 1;
+	disc->svids[0].svid = USB_VID_INTEL;
+	disc->svids[0].discovery = PD_DISC_COMPLETE;
+	disc->svids[0].mode_cnt = 1;
+	cable_resp.tbt_alt_mode = TBT_ALTERNATE_MODE;
+	cable_resp.tbt_cable_speed = TBT_SS_RES_0;
+	cable_resp.tbt_rounded = TBT_GEN3_NON_ROUNDED;
+	cable_resp.tbt_cable = TBT_CABLE_NON_OPTICAL;
+	cable_resp.retimer_type = USB_NOT_RETIMER;
+	cable_resp.lsrx_comm = BIDIR_LSRX_COMM;
+	cable_resp.tbt_active_passive = TBT_CABLE_PASSIVE;
+	disc->svids[0].mode_vdo[0] = cable_resp.raw_value;
+
+	/* Set device VDO */
+	dev_disc = pd_get_am_discovery_and_notify_access(USBC_PORT_C1,
+							 TCPCI_MSG_SOP);
+	dev_disc->svid_cnt = 1;
+	dev_disc->svids[0].svid = USB_VID_INTEL;
+	dev_disc->svids[0].discovery = PD_DISC_COMPLETE;
+	dev_disc->svids[0].mode_cnt = 1;
+	device_resp.tbt_alt_mode = TBT_ALTERNATE_MODE;
+	device_resp.tbt_adapter = TBT_ADAPTER_TBT3;
+	device_resp.intel_spec_b0 = VENDOR_SPECIFIC_NOT_SUPPORTED;
+	device_resp.vendor_spec_b0 = VENDOR_SPECIFIC_NOT_SUPPORTED;
+	device_resp.vendor_spec_b1 = VENDOR_SPECIFIC_NOT_SUPPORTED;
+	dev_disc->svids[0].mode_vdo[0] = device_resp.raw_value;
+
+	/* Test USB mode with active cable */
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_USB_ENABLED, &ack_required),
+		      NULL);
+	zassert_false(ack_required, "ACK is never required for BB retimer");
+	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
+	exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT |
+		   BB_RETIMER_USB_3_CONNECTION | BB_RETIMER_USB_3_SPEED |
+		   BB_RETIMER_RE_TIMER_DRIVER | BB_RETIMER_ACTIVE_PASSIVE;
+	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
+		      exp_conn, conn);
+
+	/* Test TBT mode with active cable */
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_TBT_COMPAT_ENABLED,
+					 &ack_required),
+		      NULL);
+	zassert_false(ack_required, "ACK is never required for BB retimer");
+	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
+	exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT |
+		   BB_RETIMER_TBT_CONNECTION | BB_RETIMER_ACTIVE_PASSIVE;
+	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
+		      exp_conn, conn);
+
+	/* Test TBT mode with retimer */
+	cable_resp.retimer_type = USB_RETIMER;
+	disc->svids[0].mode_vdo[0] = cable_resp.raw_value;
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_TBT_COMPAT_ENABLED,
+					 &ack_required),
+		      NULL);
+	zassert_false(ack_required, "ACK is never required for BB retimer");
+	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
+	exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT |
+		   BB_RETIMER_TBT_CONNECTION | BB_RETIMER_RE_TIMER_DRIVER |
+		   BB_RETIMER_ACTIVE_PASSIVE;
+	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
+		      exp_conn, conn);
+
+	/* Test TBT mode with optical cable */
+	cable_resp.retimer_type = USB_NOT_RETIMER;
+	cable_resp.tbt_cable = TBT_CABLE_OPTICAL;
+	disc->svids[0].mode_vdo[0] = cable_resp.raw_value;
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_TBT_COMPAT_ENABLED,
+					 &ack_required),
+		      NULL);
+	zassert_false(ack_required, "ACK is never required for BB retimer");
+	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
+	exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT |
+		   BB_RETIMER_TBT_CONNECTION | BB_RETIMER_TBT_CABLE_TYPE |
+		   BB_RETIMER_ACTIVE_PASSIVE;
+	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
+		      exp_conn, conn);
+
+	/* Test TBT mode with active link training */
+	cable_resp.tbt_cable = TBT_CABLE_NON_OPTICAL;
+	cable_resp.lsrx_comm = UNIDIR_LSRX_COMM;
+	disc->svids[0].mode_vdo[0] = cable_resp.raw_value;
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_TBT_COMPAT_ENABLED,
+					 &ack_required),
+		      NULL);
+	zassert_false(ack_required, "ACK is never required for BB retimer");
+	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
+	exp_conn =
+		BB_RETIMER_DATA_CONNECTION_PRESENT | BB_RETIMER_TBT_CONNECTION |
+		BB_RETIMER_TBT_ACTIVE_LINK_TRAINING | BB_RETIMER_ACTIVE_PASSIVE;
+	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
+		      exp_conn, conn);
+
+	/* Test TBT mode with different cable speeds */
+	cable_resp.lsrx_comm = BIDIR_LSRX_COMM;
+	cable_resp.tbt_cable_speed = TBT_SS_U31_GEN1;
+	disc->svids[0].mode_vdo[0] = cable_resp.raw_value;
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_TBT_COMPAT_ENABLED,
+					 &ack_required),
+		      NULL);
+	zassert_false(ack_required, "ACK is never required for BB retimer");
+	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
+	exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT |
+		   BB_RETIMER_TBT_CONNECTION |
+		   BB_RETIMER_USB4_TBT_CABLE_SPEED_SUPPORT(1) |
+		   BB_RETIMER_ACTIVE_PASSIVE;
+	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
+		      exp_conn, conn);
+
+	cable_resp.tbt_cable_speed = TBT_SS_U32_GEN1_GEN2;
+	disc->svids[0].mode_vdo[0] = cable_resp.raw_value;
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_TBT_COMPAT_ENABLED,
+					 &ack_required),
+		      NULL);
+	zassert_false(ack_required, "ACK is never required for BB retimer");
+	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
+	exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT |
+		   BB_RETIMER_TBT_CONNECTION |
+		   BB_RETIMER_USB4_TBT_CABLE_SPEED_SUPPORT(2) |
+		   BB_RETIMER_ACTIVE_PASSIVE;
+	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
+		      exp_conn, conn);
+
+	cable_resp.tbt_cable_speed = TBT_SS_TBT_GEN3;
+	disc->svids[0].mode_vdo[0] = cable_resp.raw_value;
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_TBT_COMPAT_ENABLED,
+					 &ack_required),
+		      NULL);
+	zassert_false(ack_required, "ACK is never required for BB retimer");
+	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
+	exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT |
+		   BB_RETIMER_TBT_CONNECTION |
+		   BB_RETIMER_USB4_TBT_CABLE_SPEED_SUPPORT(3) |
+		   BB_RETIMER_ACTIVE_PASSIVE;
+	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
+		      exp_conn, conn);
+
+	/* Test TBT mode with TBT gen4 cable */
+	cable_resp.tbt_cable_speed = TBT_SS_RES_0;
+	cable_resp.tbt_rounded = TBT_GEN3_GEN4_ROUNDED_NON_ROUNDED;
+	disc->svids[0].mode_vdo[0] = cable_resp.raw_value;
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_TBT_COMPAT_ENABLED,
+					 &ack_required),
+		      NULL);
+	zassert_false(ack_required, "ACK is never required for BB retimer");
+	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
+	exp_conn =
+		BB_RETIMER_DATA_CONNECTION_PRESENT | BB_RETIMER_TBT_CONNECTION |
+		BB_RETIMER_TBT_CABLE_GENERATION(1) | BB_RETIMER_ACTIVE_PASSIVE;
+	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
+		      exp_conn, conn);
+
+	/* Test TBT mode with legacy TBT adapter */
+	cable_resp.tbt_rounded = TBT_GEN3_NON_ROUNDED;
+	disc->svids[0].mode_vdo[0] = cable_resp.raw_value;
+	device_resp.tbt_adapter = TBT_ADAPTER_TBT2_LEGACY;
+	dev_disc->svids[0].mode_vdo[0] = device_resp.raw_value;
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_TBT_COMPAT_ENABLED,
+					 &ack_required),
+		      NULL);
+	zassert_false(ack_required, "ACK is never required for BB retimer");
+	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
+	exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT |
+		   BB_RETIMER_TBT_CONNECTION | BB_RETIMER_TBT_TYPE |
+		   BB_RETIMER_ACTIVE_PASSIVE;
+	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
+		      exp_conn, conn);
+
+	/* Test TBT mode with Intel specific b0 */
+	device_resp.tbt_adapter = TBT_ADAPTER_TBT3;
+	device_resp.intel_spec_b0 = VENDOR_SPECIFIC_SUPPORTED;
+	dev_disc->svids[0].mode_vdo[0] = device_resp.raw_value;
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_TBT_COMPAT_ENABLED,
+					 &ack_required),
+		      NULL);
+	zassert_false(ack_required, "ACK is never required for BB retimer");
+	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
+	exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT |
+		   BB_RETIMER_TBT_CONNECTION | BB_RETIMER_ACTIVE_PASSIVE;
+
+	if (IS_ENABLED(CONFIG_USBC_RETIMER_INTEL_BB_VPRO_CAPABLE))
+		exp_conn |= BB_RETIMER_VPRO_DOCK_DP_OVERDRIVE;
+
+	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
+		      exp_conn, conn);
+
+	/* Test TBT mode with vendor specific b1 */
+	device_resp.intel_spec_b0 = VENDOR_SPECIFIC_NOT_SUPPORTED;
+	device_resp.vendor_spec_b1 = VENDOR_SPECIFIC_SUPPORTED;
+	dev_disc->svids[0].mode_vdo[0] = device_resp.raw_value;
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_TBT_COMPAT_ENABLED,
+					 &ack_required),
+		      NULL);
+	zassert_false(ack_required, "ACK is never required for BB retimer");
+	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
+	exp_conn =
+		BB_RETIMER_DATA_CONNECTION_PRESENT | BB_RETIMER_TBT_CONNECTION |
+		BB_RETIMER_VPRO_DOCK_DP_OVERDRIVE | BB_RETIMER_ACTIVE_PASSIVE;
+	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
+		      exp_conn, conn);
+}
+
+/** Test BB retimer init */
+ZTEST_USER(bb_retimer, test_bb_init)
+{
+	const struct device *gpio_dev =
+		DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_USB_C1_LS_EN_PATH, gpios));
+	const struct emul *emul = EMUL_DT_GET(BB_RETIMER_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bb_retimer_get_i2c_common_data(emul);
+
+	zassert_not_null(gpio_dev, "Cannot get GPIO device");
+
+	/* Set AP to normal state and wait for chipset task */
+	test_set_chipset_to_s0();
+
+	/* Setup emulator fail on read */
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  BB_RETIMER_REG_VENDOR_ID);
+	/* Test fail on vendor ID read */
+	zassert_equal(EC_ERROR_INVAL,
+		      bb_usb_retimer.init(usb_muxes[USBC_PORT_C1].mux), NULL);
+	/* Enable pins should be set always after init, when AP is on */
+	zassert_equal(1, gpio_emul_output_get(gpio_dev, GPIO_USB_C1_LS_EN_PORT),
+		      NULL);
+	zassert_equal(
+		1, gpio_emul_output_get(gpio_dev, GPIO_USB_C1_RT_RST_ODL_PORT),
+		NULL);
+
+	/* Setup wrong vendor ID */
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	bb_emul_set_reg(emul, BB_RETIMER_REG_VENDOR_ID, 0x12144678);
+	/* Test fail on wrong vendor ID */
+	zassert_equal(EC_ERROR_INVAL,
+		      bb_usb_retimer.init(usb_muxes[USBC_PORT_C1].mux), NULL);
+	zassert_equal(1, gpio_emul_output_get(gpio_dev, GPIO_USB_C1_LS_EN_PORT),
+		      NULL);
+	zassert_equal(
+		1, gpio_emul_output_get(gpio_dev, GPIO_USB_C1_RT_RST_ODL_PORT),
+		NULL);
+
+	/* Setup emulator fail on device ID read */
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  BB_RETIMER_REG_DEVICE_ID);
+	bb_emul_set_reg(emul, BB_RETIMER_REG_VENDOR_ID, BB_RETIMER_VENDOR_ID_1);
+	/* Test fail on device ID read */
+	zassert_equal(EC_ERROR_INVAL,
+		      bb_usb_retimer.init(usb_muxes[USBC_PORT_C1].mux), NULL);
+	zassert_equal(1, gpio_emul_output_get(gpio_dev, GPIO_USB_C1_LS_EN_PORT),
+		      NULL);
+	zassert_equal(
+		1, gpio_emul_output_get(gpio_dev, GPIO_USB_C1_RT_RST_ODL_PORT),
+		NULL);
+
+	/* Setup wrong device ID */
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	bb_emul_set_reg(emul, BB_RETIMER_REG_DEVICE_ID, 0x12144678);
+	/* Test fail on wrong device ID */
+	zassert_equal(EC_ERROR_INVAL,
+		      bb_usb_retimer.init(usb_muxes[USBC_PORT_C1].mux), NULL);
+	zassert_equal(1, gpio_emul_output_get(gpio_dev, GPIO_USB_C1_LS_EN_PORT),
+		      NULL);
+	zassert_equal(
+		1, gpio_emul_output_get(gpio_dev, GPIO_USB_C1_RT_RST_ODL_PORT),
+		NULL);
+
+	/* Test successful init */
+	bb_emul_set_reg(emul, BB_RETIMER_REG_DEVICE_ID, BB_RETIMER_DEVICE_ID);
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.init(usb_muxes[USBC_PORT_C1].mux), NULL);
+	zassert_equal(1, gpio_emul_output_get(gpio_dev, GPIO_USB_C1_LS_EN_PORT),
+		      NULL);
+	zassert_equal(
+		1, gpio_emul_output_get(gpio_dev, GPIO_USB_C1_RT_RST_ODL_PORT),
+		NULL);
+
+	/* Set AP to off state and wait for chipset task */
+	test_set_chipset_to_g3();
+
+	/* With AP off, init should fail and pins should be unset */
+	zassert_equal(EC_ERROR_NOT_POWERED,
+		      bb_usb_retimer.init(usb_muxes[USBC_PORT_C1].mux), NULL);
+	zassert_equal(0, gpio_emul_output_get(gpio_dev, GPIO_USB_C1_LS_EN_PORT),
+		      NULL);
+
+	msleep(1);
+	zassert_equal(
+		0, gpio_emul_output_get(gpio_dev, GPIO_USB_C1_RT_RST_ODL_PORT),
+		NULL);
+}
+
+/** Test BB retimer console command */
+ZTEST_USER(bb_retimer, test_bb_console_cmd)
+{
+	int rv;
+
+	/* Validate well formed shell commands */
+	rv = shell_execute_cmd(get_ec_shell(), "retimer 1 r 2");
+	zassert_ok(rv, "rv=%d", rv);
+	rv = shell_execute_cmd(get_ec_shell(), "retimer 1 w 2 0");
+	zassert_ok(rv, "rv=%d", rv);
+
+	/* Validate errors for malformed shell commands */
+	rv = shell_execute_cmd(get_ec_shell(), "retimer x");
+	zassert_equal(EC_ERROR_PARAM_COUNT, rv, "rv=%d", rv);
+	rv = shell_execute_cmd(get_ec_shell(), "retimer x r 2");
+	zassert_equal(EC_ERROR_PARAM1, rv, "rv=%d", rv);
+	rv = shell_execute_cmd(get_ec_shell(), "retimer 0 r 2");
+	zassert_equal(EC_ERROR_UNIMPLEMENTED, rv, "rv=%d", rv);
+	rv = shell_execute_cmd(get_ec_shell(), "retimer 1 x 2");
+	zassert_equal(EC_ERROR_PARAM2, rv, "rv=%d", rv);
+	rv = shell_execute_cmd(get_ec_shell(), "retimer 1 r x");
+	zassert_equal(EC_ERROR_PARAM3, rv, "rv=%d", rv);
+	rv = shell_execute_cmd(get_ec_shell(), "retimer 1 w 2 x");
+	zassert_equal(EC_ERROR_PARAM4, rv, "rv=%d", rv);
+}
+
+ZTEST_SUITE(bb_retimer_no_tasks, drivers_predicate_pre_main, NULL, NULL, NULL,
+	    NULL);
+
+ZTEST_SUITE(bb_retimer, drivers_predicate_post_main, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/drivers/default/src/bma2x2.c b/zephyr/test/drivers/default/src/bma2x2.c
new file mode 100644
index 0000000000..b66fc9d056
--- /dev/null
+++ b/zephyr/test/drivers/default/src/bma2x2.c
@@ -0,0 +1,941 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "accelgyro.h"
+#include "common.h"
+#include "driver/accel_bma2x2.h"
+#include "emul/emul_bma255.h"
+#include "emul/emul_common_i2c.h"
+#include "i2c.h"
+#include "motion_sense.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+/** How accurate comparision of vectors should be. */
+#define V_EPS 8
+
+#define BMA_NODE DT_NODELABEL(bma_emul)
+
+/** Mutex for test motion sensor  */
+static mutex_t sensor_mutex;
+
+/** Rotation used in some tests */
+static const mat33_fp_t test_rotation = { { 0, FLOAT_TO_FP(1), 0 },
+					  { FLOAT_TO_FP(-1), 0, 0 },
+					  { 0, 0, FLOAT_TO_FP(-1) } };
+
+/** Rotate given vector by test rotation */
+void rotate_int3v_by_test_rotation(int16_t *v)
+{
+	int16_t t;
+
+	t = v[0];
+	v[0] = -v[1];
+	v[1] = t;
+	v[2] = -v[2];
+}
+
+static struct accelgyro_saved_data_t acc_data;
+
+/** Mock minimal motion sensor setup required for bma2x2 driver test */
+static struct motion_sensor_t ms = {
+	.name = "bma_emul",
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.drv = &bma2x2_accel_drv,
+	.mutex = &sensor_mutex,
+	.drv_data = &acc_data,
+	.port = I2C_PORT_NODELABEL(i2c0),
+	.i2c_spi_addr_flags = DT_REG_ADDR(BMA_NODE),
+	.rot_standard_ref = NULL,
+	.current_range = 0,
+};
+
+/** Set emulator offset values to vector of three int16_t */
+static void set_emul_offset(const struct emul *emul, int16_t *offset)
+{
+	bma_emul_set_off(emul, BMA_EMUL_AXIS_X, offset[0]);
+	bma_emul_set_off(emul, BMA_EMUL_AXIS_Y, offset[1]);
+	bma_emul_set_off(emul, BMA_EMUL_AXIS_Z, offset[2]);
+}
+
+/** Save emulator offset values to vector of three int16_t */
+static void get_emul_offset(const struct emul *emul, int16_t *offset)
+{
+	offset[0] = bma_emul_get_off(emul, BMA_EMUL_AXIS_X);
+	offset[1] = bma_emul_get_off(emul, BMA_EMUL_AXIS_Y);
+	offset[2] = bma_emul_get_off(emul, BMA_EMUL_AXIS_Z);
+}
+
+/** Set emulator accelerometer values to vector of three int16_t */
+static void set_emul_acc(const struct emul *emul, int16_t *acc)
+{
+	bma_emul_set_acc(emul, BMA_EMUL_AXIS_X, acc[0]);
+	bma_emul_set_acc(emul, BMA_EMUL_AXIS_Y, acc[1]);
+	bma_emul_set_acc(emul, BMA_EMUL_AXIS_Z, acc[2]);
+}
+
+/** Convert accelerometer read to units used by emulator */
+static void drv_acc_to_emul(intv3_t drv, int range, int16_t *out)
+{
+	const int scale = MOTION_SCALING_FACTOR / BMA_EMUL_1G;
+
+	out[0] = drv[0] * range / scale;
+	out[1] = drv[1] * range / scale;
+	out[2] = drv[2] * range / scale;
+}
+
+/** Compare two vectors of three int16_t */
+static void compare_int3v_f(int16_t *exp_v, int16_t *v, int line)
+{
+	int i;
+
+	for (i = 0; i < 3; i++) {
+		zassert_within(
+			exp_v[i], v[i], V_EPS,
+			"Expected [%d; %d; %d], got [%d; %d; %d]; line: %d",
+			exp_v[0], exp_v[1], exp_v[2], v[0], v[1], v[2], line);
+	}
+}
+#define compare_int3v(exp_v, v) compare_int3v_f(exp_v, v, __LINE__)
+
+/** Data for reset fail function */
+struct reset_func_data {
+	/** Fail for given attempts */
+	int fail_attempts;
+	/** Do not fail for given attempts */
+	int ok_before_fail;
+	/** Reset register value after given attempts */
+	int reset_value;
+};
+
+/**
+ * Custom emulator function used in init test. It returns cmd soft when reset
+ * register is accessed data.reset_value times. Error is returned after
+ * accessing register data.ok_before_fail times. Error is returned during next
+ * data.fail_attempts times.
+ */
+static int emul_read_reset(const struct emul *emul, int reg, uint8_t *buf,
+			   int bytes, void *data)
+{
+	struct reset_func_data *d = data;
+
+	reg = bma_emul_access_reg(emul, reg, bytes, true /* = read */);
+	if (reg != BMA2x2_RST_ADDR) {
+		return 1;
+	}
+
+	if (d->reset_value > 0) {
+		d->reset_value--;
+		bma_emul_set_reg(emul, BMA2x2_RST_ADDR, BMA2x2_CMD_SOFT_RESET);
+	} else {
+		bma_emul_set_reg(emul, BMA2x2_RST_ADDR, 0);
+	}
+
+	if (d->ok_before_fail > 0) {
+		d->ok_before_fail--;
+		return 1;
+	}
+
+	if (d->fail_attempts > 0) {
+		d->fail_attempts--;
+		return -EIO;
+	}
+
+	return 1;
+}
+
+/**
+ * Test get offset with and without rotation. Also test behaviour on I2C error.
+ */
+ZTEST_USER(bma2x2, test_bma_get_offset)
+{
+	const struct emul *emul = EMUL_DT_GET(BMA_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bma_get_i2c_common_data(emul);
+	int16_t ret_offset[3];
+	int16_t exp_offset[3];
+	int16_t temp;
+
+	/* Test fail on each axis */
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  BMA2x2_OFFSET_X_AXIS_ADDR);
+	zassert_equal(EC_ERROR_INVAL,
+		      ms.drv->get_offset(&ms, ret_offset, &temp), NULL);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  BMA2x2_OFFSET_Y_AXIS_ADDR);
+	zassert_equal(EC_ERROR_INVAL,
+		      ms.drv->get_offset(&ms, ret_offset, &temp), NULL);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  BMA2x2_OFFSET_Z_AXIS_ADDR);
+	zassert_equal(EC_ERROR_INVAL,
+		      ms.drv->get_offset(&ms, ret_offset, &temp), NULL);
+
+	/* Do not fail on read */
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Set emulator offset */
+	exp_offset[0] = BMA_EMUL_1G / 10;
+	exp_offset[1] = BMA_EMUL_1G / 20;
+	exp_offset[2] = -(int)BMA_EMUL_1G / 30;
+	set_emul_offset(emul, exp_offset);
+	/* Disable rotation */
+	ms.rot_standard_ref = NULL;
+
+	/* Test get offset without rotation */
+	zassert_equal(EC_SUCCESS, ms.drv->get_offset(&ms, ret_offset, &temp),
+		      NULL);
+	zassert_equal(temp, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP);
+	compare_int3v(exp_offset, ret_offset);
+
+	/* Setup rotation and rotate expected offset */
+	ms.rot_standard_ref = &test_rotation;
+	rotate_int3v_by_test_rotation(exp_offset);
+
+	/* Test get offset with rotation */
+	zassert_equal(EC_SUCCESS, ms.drv->get_offset(&ms, ret_offset, &temp),
+		      NULL);
+	zassert_equal(temp, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP);
+	compare_int3v(exp_offset, ret_offset);
+}
+
+/**
+ * Test set offset with and without rotation. Also test behaviour on I2C error.
+ */
+ZTEST_USER(bma2x2, test_bma_set_offset)
+{
+	const struct emul *emul = EMUL_DT_GET(BMA_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bma_get_i2c_common_data(emul);
+	int16_t ret_offset[3];
+	int16_t exp_offset[3] = { 0, 0, 0 };
+	int16_t temp = 0;
+
+	/* Test fail on each axis */
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   BMA2x2_OFFSET_X_AXIS_ADDR);
+	zassert_equal(EC_ERROR_INVAL, ms.drv->set_offset(&ms, exp_offset, temp),
+		      NULL);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   BMA2x2_OFFSET_Y_AXIS_ADDR);
+	zassert_equal(EC_ERROR_INVAL, ms.drv->set_offset(&ms, exp_offset, temp),
+		      NULL);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   BMA2x2_OFFSET_Z_AXIS_ADDR);
+	zassert_equal(EC_ERROR_INVAL, ms.drv->set_offset(&ms, exp_offset, temp),
+		      NULL);
+
+	/* Do not fail on write */
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Set input offset */
+	exp_offset[0] = BMA_EMUL_1G / 10;
+	exp_offset[1] = BMA_EMUL_1G / 20;
+	exp_offset[2] = -(int)BMA_EMUL_1G / 30;
+	/* Disable rotation */
+	ms.rot_standard_ref = NULL;
+
+	/* Test set offset without rotation */
+	zassert_equal(EC_SUCCESS, ms.drv->set_offset(&ms, exp_offset, temp),
+		      NULL);
+	get_emul_offset(emul, ret_offset);
+	compare_int3v(exp_offset, ret_offset);
+
+	/* Setup rotation and rotate input for set_offset function */
+	ms.rot_standard_ref = &test_rotation;
+	ret_offset[0] = exp_offset[0];
+	ret_offset[1] = exp_offset[1];
+	ret_offset[2] = exp_offset[2];
+	rotate_int3v_by_test_rotation(ret_offset);
+
+	/* Test set offset with rotation */
+	zassert_equal(EC_SUCCESS, ms.drv->set_offset(&ms, ret_offset, temp),
+		      NULL);
+	get_emul_offset(emul, ret_offset);
+	compare_int3v(exp_offset, ret_offset);
+}
+
+/*
+ * Try to set range and check if expected range was set in driver and in
+ * emulator.
+ */
+static void check_set_range_f(const struct emul *emul, int range, int rnd,
+			      int exp_range, int line)
+{
+	uint8_t exp_range_reg;
+	uint8_t range_reg;
+
+	zassert_equal(EC_SUCCESS, ms.drv->set_range(&ms, range, rnd),
+		      "set_range failed; line: %d", line);
+	zassert_equal(exp_range, ms.current_range,
+		      "Expected range %d, got %d; line %d", exp_range,
+		      ms.current_range, line);
+	range_reg = bma_emul_get_reg(emul, BMA2x2_RANGE_SELECT_ADDR);
+	range_reg &= BMA2x2_RANGE_SELECT_MSK;
+
+	switch (exp_range) {
+	case 2:
+		exp_range_reg = BMA2x2_RANGE_2G;
+		break;
+	case 4:
+		exp_range_reg = BMA2x2_RANGE_4G;
+		break;
+	case 8:
+		exp_range_reg = BMA2x2_RANGE_8G;
+		break;
+	case 16:
+		exp_range_reg = BMA2x2_RANGE_16G;
+		break;
+	default:
+		/* Unknown expected range */
+		zassert_unreachable(
+			"Expected range %d not supported by device; line %d",
+			exp_range, line);
+		return;
+	}
+
+	zassert_equal(exp_range_reg, range_reg,
+		      "Expected range reg 0x%x, got 0x%x; line %d",
+		      exp_range_reg, range_reg, line);
+}
+#define check_set_range(emul, range, rnd, exp_range) \
+	check_set_range_f(emul, range, rnd, exp_range, __LINE__)
+
+/** Test set range with and without I2C errors. */
+ZTEST_USER(bma2x2, test_bma_set_range)
+{
+	const struct emul *emul = EMUL_DT_GET(BMA_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bma_get_i2c_common_data(emul);
+	int start_range;
+
+	/* Setup starting range, shouldn't be changed on error */
+	start_range = 2;
+	ms.current_range = start_range;
+	bma_emul_set_reg(emul, BMA2x2_RANGE_SELECT_ADDR, BMA2x2_RANGE_2G);
+	/* Setup emulator fail on read */
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  BMA2x2_RANGE_SELECT_ADDR);
+
+	/* Test fail on read */
+	zassert_equal(EC_ERROR_INVAL, ms.drv->set_range(&ms, 12, 0));
+	zassert_equal(start_range, ms.current_range);
+	zassert_equal(BMA2x2_RANGE_2G,
+		      bma_emul_get_reg(emul, BMA2x2_RANGE_SELECT_ADDR), NULL);
+	zassert_equal(EC_ERROR_INVAL, ms.drv->set_range(&ms, 12, 1));
+	zassert_equal(start_range, ms.current_range);
+	zassert_equal(BMA2x2_RANGE_2G,
+		      bma_emul_get_reg(emul, BMA2x2_RANGE_SELECT_ADDR), NULL);
+
+	/* Do not fail on read */
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Setup emulator fail on write */
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   BMA2x2_RANGE_SELECT_ADDR);
+
+	/* Test fail on write */
+	zassert_equal(EC_ERROR_INVAL, ms.drv->set_range(&ms, 12, 0));
+	zassert_equal(start_range, ms.current_range);
+	zassert_equal(BMA2x2_RANGE_2G,
+		      bma_emul_get_reg(emul, BMA2x2_RANGE_SELECT_ADDR), NULL);
+	zassert_equal(EC_ERROR_INVAL, ms.drv->set_range(&ms, 12, 1));
+	zassert_equal(start_range, ms.current_range);
+	zassert_equal(BMA2x2_RANGE_2G,
+		      bma_emul_get_reg(emul, BMA2x2_RANGE_SELECT_ADDR), NULL);
+
+	/* Do not fail on write */
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test setting range with rounding down */
+	check_set_range(emul, 1, 0, 2);
+	check_set_range(emul, 2, 0, 2);
+	check_set_range(emul, 3, 0, 2);
+	check_set_range(emul, 4, 0, 4);
+	check_set_range(emul, 5, 0, 4);
+	check_set_range(emul, 6, 0, 4);
+	check_set_range(emul, 7, 0, 4);
+	check_set_range(emul, 8, 0, 8);
+	check_set_range(emul, 9, 0, 8);
+	check_set_range(emul, 15, 0, 8);
+	check_set_range(emul, 16, 0, 16);
+	check_set_range(emul, 17, 0, 16);
+
+	/* Test setting range with rounding up */
+	check_set_range(emul, 1, 1, 2);
+	check_set_range(emul, 2, 1, 2);
+	check_set_range(emul, 3, 1, 4);
+	check_set_range(emul, 4, 1, 4);
+	check_set_range(emul, 5, 1, 8);
+	check_set_range(emul, 6, 1, 8);
+	check_set_range(emul, 7, 1, 8);
+	check_set_range(emul, 8, 1, 8);
+	check_set_range(emul, 9, 1, 16);
+	check_set_range(emul, 15, 1, 16);
+	check_set_range(emul, 16, 1, 16);
+	check_set_range(emul, 17, 1, 16);
+}
+
+/** Test init with and without I2C errors. */
+ZTEST_USER(bma2x2, test_bma_init)
+{
+	struct reset_func_data reset_func_data;
+	const struct emul *emul = EMUL_DT_GET(BMA_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bma_get_i2c_common_data(emul);
+
+	/* Setup emulator fail read function */
+	i2c_common_emul_set_read_fail_reg(common_data, BMA2x2_CHIP_ID_ADDR);
+
+	/* Test fail on chip id read */
+	zassert_equal(EC_ERROR_UNKNOWN, ms.drv->init(&ms));
+
+	/* Disable failing on chip id read, but set wrong value */
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	bma_emul_set_reg(emul, BMA2x2_CHIP_ID_ADDR, 23);
+
+	/* Test wrong chip id */
+	zassert_equal(EC_ERROR_ACCESS_DENIED, ms.drv->init(&ms));
+
+	/* Set correct chip id, but fail on reset reg read */
+	i2c_common_emul_set_read_fail_reg(common_data, BMA2x2_RST_ADDR);
+	bma_emul_set_reg(emul, BMA2x2_CHIP_ID_ADDR, BMA255_CHIP_ID_MAJOR);
+
+	/* Test fail on reset register read */
+	zassert_equal(EC_ERROR_INVAL, ms.drv->init(&ms));
+
+	/* Do not fail on read */
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Setup emulator fail on write */
+	i2c_common_emul_set_write_fail_reg(common_data, BMA2x2_RST_ADDR);
+
+	/* Test fail on reset register write */
+	zassert_equal(EC_ERROR_INVAL, ms.drv->init(&ms));
+
+	/* Do not fail on write */
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Setup emulator fail reset read function */
+	reset_func_data.ok_before_fail = 1;
+	reset_func_data.fail_attempts = 100;
+	reset_func_data.reset_value = 0;
+	i2c_common_emul_set_read_func(common_data, emul_read_reset,
+				      &reset_func_data);
+
+	/* Test fail on too many reset read errors */
+	zassert_equal(EC_ERROR_TIMEOUT, ms.drv->init(&ms));
+
+	/* Test success after reset read errors */
+	reset_func_data.ok_before_fail = 1;
+	reset_func_data.fail_attempts = 3;
+	zassert_equal(EC_RES_SUCCESS, ms.drv->init(&ms));
+
+	/* Test success without read errors */
+	reset_func_data.fail_attempts = 0;
+	zassert_equal(EC_RES_SUCCESS, ms.drv->init(&ms));
+
+	/* Test fail on too many reset read wrong value */
+	reset_func_data.fail_attempts = 0;
+	reset_func_data.reset_value = 100;
+	zassert_equal(EC_ERROR_TIMEOUT, ms.drv->init(&ms));
+
+	/* Test success on few reset read wrong value */
+	reset_func_data.fail_attempts = 0;
+	reset_func_data.reset_value = 4;
+	zassert_equal(EC_RES_SUCCESS, ms.drv->init(&ms));
+
+	/* Remove custom emulator read function */
+	i2c_common_emul_set_read_func(common_data, NULL, NULL);
+}
+
+/*
+ * Try to set data rate and check if expected rate was set in driver and in
+ * emulator.
+ */
+static void check_set_rate_f(const struct emul *emul, int rate, int rnd,
+			     int exp_rate, int line)
+{
+	uint8_t exp_rate_reg;
+	uint8_t rate_reg;
+	int drv_rate;
+
+	zassert_equal(EC_SUCCESS, ms.drv->set_data_rate(&ms, rate, rnd),
+		      "set_data_rate failed; line: %d", line);
+	drv_rate = ms.drv->get_data_rate(&ms);
+	zassert_equal(exp_rate, drv_rate, "Expected rate %d, got %d; line %d",
+		      exp_rate, drv_rate, line);
+	rate_reg = bma_emul_get_reg(emul, BMA2x2_BW_SELECT_ADDR);
+	rate_reg &= BMA2x2_BW_MSK;
+
+	switch (exp_rate) {
+	case 7812:
+		exp_rate_reg = BMA2x2_BW_7_81HZ;
+		break;
+	case 15625:
+		exp_rate_reg = BMA2x2_BW_15_63HZ;
+		break;
+	case 31250:
+		exp_rate_reg = BMA2x2_BW_31_25HZ;
+		break;
+	case 62500:
+		exp_rate_reg = BMA2x2_BW_62_50HZ;
+		break;
+	case 125000:
+		exp_rate_reg = BMA2x2_BW_125HZ;
+		break;
+	case 250000:
+		exp_rate_reg = BMA2x2_BW_250HZ;
+		break;
+	case 500000:
+		exp_rate_reg = BMA2x2_BW_500HZ;
+		break;
+	case 1000000:
+		exp_rate_reg = BMA2x2_BW_1000HZ;
+		break;
+	default:
+		/* Unknown expected rate */
+		zassert_unreachable(
+			"Expected rate %d not supported by device; line %d",
+			exp_rate, line);
+		return;
+	}
+
+	zassert_equal(exp_rate_reg, rate_reg,
+		      "Expected rate reg 0x%x, got 0x%x; line %d", exp_rate_reg,
+		      rate_reg, line);
+}
+#define check_set_rate(emul, rate, rnd, exp_rate) \
+	check_set_rate_f(emul, rate, rnd, exp_rate, __LINE__)
+
+/** Test set and get rate with and without I2C errors. */
+ZTEST_USER(bma2x2, test_bma_rate)
+{
+	const struct emul *emul = EMUL_DT_GET(BMA_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bma_get_i2c_common_data(emul);
+	uint8_t reg_rate;
+	int drv_rate;
+
+	/* Test setting rate with rounding down */
+	check_set_rate(emul, 1, 0, 7812);
+	check_set_rate(emul, 1, 0, 7812);
+	check_set_rate(emul, 7811, 0, 7812);
+	check_set_rate(emul, 7812, 0, 7812);
+	check_set_rate(emul, 7813, 0, 7812);
+	check_set_rate(emul, 15624, 0, 7812);
+	check_set_rate(emul, 15625, 0, 15625);
+	check_set_rate(emul, 15626, 0, 15625);
+	check_set_rate(emul, 31249, 0, 15625);
+	check_set_rate(emul, 31250, 0, 31250);
+	check_set_rate(emul, 31251, 0, 31250);
+	check_set_rate(emul, 62499, 0, 31250);
+	check_set_rate(emul, 62500, 0, 62500);
+	check_set_rate(emul, 62501, 0, 62500);
+	check_set_rate(emul, 124999, 0, 62500);
+	check_set_rate(emul, 125000, 0, 125000);
+	check_set_rate(emul, 125001, 0, 125000);
+	check_set_rate(emul, 249999, 0, 125000);
+	check_set_rate(emul, 250000, 0, 250000);
+	check_set_rate(emul, 250001, 0, 250000);
+	check_set_rate(emul, 499999, 0, 250000);
+	check_set_rate(emul, 500000, 0, 500000);
+	check_set_rate(emul, 500001, 0, 500000);
+	check_set_rate(emul, 999999, 0, 500000);
+	check_set_rate(emul, 1000000, 0, 1000000);
+	check_set_rate(emul, 1000001, 0, 1000000);
+	check_set_rate(emul, 2000000, 0, 1000000);
+
+	/* Test setting rate with rounding up */
+	check_set_rate(emul, 1, 1, 7812);
+	check_set_rate(emul, 1, 1, 7812);
+	check_set_rate(emul, 7811, 1, 7812);
+	check_set_rate(emul, 7812, 1, 7812);
+	check_set_rate(emul, 7813, 1, 15625);
+	check_set_rate(emul, 15624, 1, 15625);
+	check_set_rate(emul, 15625, 1, 15625);
+	check_set_rate(emul, 15626, 1, 31250);
+	check_set_rate(emul, 31249, 1, 31250);
+	check_set_rate(emul, 31250, 1, 31250);
+	check_set_rate(emul, 31251, 1, 62500);
+	check_set_rate(emul, 62499, 1, 62500);
+	check_set_rate(emul, 62500, 1, 62500);
+	check_set_rate(emul, 62501, 1, 125000);
+	check_set_rate(emul, 124999, 1, 125000);
+	check_set_rate(emul, 125000, 1, 125000);
+	check_set_rate(emul, 125001, 1, 250000);
+	check_set_rate(emul, 249999, 1, 250000);
+	check_set_rate(emul, 250000, 1, 250000);
+	check_set_rate(emul, 250001, 1, 500000);
+	check_set_rate(emul, 499999, 1, 500000);
+	check_set_rate(emul, 500000, 1, 500000);
+	check_set_rate(emul, 500001, 1, 1000000);
+	check_set_rate(emul, 999999, 1, 1000000);
+	check_set_rate(emul, 1000000, 1, 1000000);
+	check_set_rate(emul, 1000001, 1, 1000000);
+	check_set_rate(emul, 2000000, 1, 1000000);
+
+	/* Current rate shouldn't be changed on error */
+	drv_rate = ms.drv->get_data_rate(&ms);
+	reg_rate = bma_emul_get_reg(emul, BMA2x2_BW_SELECT_ADDR);
+
+	/* Setup emulator fail on read */
+	i2c_common_emul_set_read_fail_reg(common_data, BMA2x2_BW_SELECT_ADDR);
+
+	/* Test fail on read */
+	zassert_equal(EC_ERROR_INVAL, ms.drv->set_data_rate(&ms, 15625, 0),
+		      NULL);
+	zassert_equal(drv_rate, ms.drv->get_data_rate(&ms));
+	zassert_equal(reg_rate, bma_emul_get_reg(emul, BMA2x2_BW_SELECT_ADDR),
+		      NULL);
+	zassert_equal(EC_ERROR_INVAL, ms.drv->set_data_rate(&ms, 15625, 1),
+		      NULL);
+	zassert_equal(drv_rate, ms.drv->get_data_rate(&ms));
+	zassert_equal(reg_rate, bma_emul_get_reg(emul, BMA2x2_BW_SELECT_ADDR),
+		      NULL);
+
+	/* Do not fail on read */
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Setup emulator fail on write */
+	i2c_common_emul_set_write_fail_reg(common_data, BMA2x2_BW_SELECT_ADDR);
+
+	/* Test fail on write */
+	zassert_equal(EC_ERROR_INVAL, ms.drv->set_data_rate(&ms, 15625, 0),
+		      NULL);
+	zassert_equal(drv_rate, ms.drv->get_data_rate(&ms));
+	zassert_equal(reg_rate, bma_emul_get_reg(emul, BMA2x2_BW_SELECT_ADDR),
+		      NULL);
+	zassert_equal(EC_ERROR_INVAL, ms.drv->set_data_rate(&ms, 15625, 1),
+		      NULL);
+	zassert_equal(drv_rate, ms.drv->get_data_rate(&ms));
+	zassert_equal(reg_rate, bma_emul_get_reg(emul, BMA2x2_BW_SELECT_ADDR),
+		      NULL);
+
+	/* Do not fail on write */
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+}
+
+/** Test read with and without I2C errors. */
+ZTEST_USER(bma2x2, test_bma_read)
+{
+	const struct emul *emul = EMUL_DT_GET(BMA_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bma_get_i2c_common_data(emul);
+	int16_t ret_acc[3];
+	int16_t exp_acc[3];
+	intv3_t ret_acc_v;
+
+	/* Set offset 0 to simplify test */
+	bma_emul_set_off(emul, BMA_EMUL_AXIS_X, 0);
+	bma_emul_set_off(emul, BMA_EMUL_AXIS_Y, 0);
+	bma_emul_set_off(emul, BMA_EMUL_AXIS_Z, 0);
+
+	/* Test fail on each axis */
+	i2c_common_emul_set_read_fail_reg(common_data, BMA2x2_X_AXIS_LSB_ADDR);
+	zassert_equal(EC_ERROR_INVAL, ms.drv->read(&ms, ret_acc_v));
+	i2c_common_emul_set_read_fail_reg(common_data, BMA2x2_X_AXIS_MSB_ADDR);
+	zassert_equal(EC_ERROR_INVAL, ms.drv->read(&ms, ret_acc_v));
+	i2c_common_emul_set_read_fail_reg(common_data, BMA2x2_Y_AXIS_LSB_ADDR);
+	zassert_equal(EC_ERROR_INVAL, ms.drv->read(&ms, ret_acc_v));
+	i2c_common_emul_set_read_fail_reg(common_data, BMA2x2_Y_AXIS_MSB_ADDR);
+	zassert_equal(EC_ERROR_INVAL, ms.drv->read(&ms, ret_acc_v));
+	i2c_common_emul_set_read_fail_reg(common_data, BMA2x2_Z_AXIS_LSB_ADDR);
+	zassert_equal(EC_ERROR_INVAL, ms.drv->read(&ms, ret_acc_v));
+	i2c_common_emul_set_read_fail_reg(common_data, BMA2x2_Z_AXIS_MSB_ADDR);
+	zassert_equal(EC_ERROR_INVAL, ms.drv->read(&ms, ret_acc_v));
+
+	/* Do not fail on read */
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Set input accelerometer values */
+	exp_acc[0] = BMA_EMUL_1G / 10;
+	exp_acc[1] = BMA_EMUL_1G / 20;
+	exp_acc[2] = -(int)BMA_EMUL_1G / 30;
+	set_emul_acc(emul, exp_acc);
+	/* Disable rotation */
+	ms.rot_standard_ref = NULL;
+	/* Set range to 2G */
+	zassert_equal(EC_SUCCESS, ms.drv->set_range(&ms, 2, 0));
+
+	/* Test read without rotation */
+	zassert_equal(EC_SUCCESS, ms.drv->read(&ms, ret_acc_v));
+	drv_acc_to_emul(ret_acc_v, 2, ret_acc);
+	compare_int3v(exp_acc, ret_acc);
+
+	/* Set range to 4G */
+	zassert_equal(EC_SUCCESS, ms.drv->set_range(&ms, 4, 0));
+
+	/* Test read without rotation */
+	zassert_equal(EC_SUCCESS, ms.drv->read(&ms, ret_acc_v));
+	drv_acc_to_emul(ret_acc_v, 4, ret_acc);
+	compare_int3v(exp_acc, ret_acc);
+
+	/* Setup rotation and rotate expected vector */
+	ms.rot_standard_ref = &test_rotation;
+	rotate_int3v_by_test_rotation(exp_acc);
+	/* Set range to 2G */
+	zassert_equal(EC_SUCCESS, ms.drv->set_range(&ms, 2, 0));
+
+	/* Test read with rotation */
+	zassert_equal(EC_SUCCESS, ms.drv->read(&ms, ret_acc_v));
+	drv_acc_to_emul(ret_acc_v, 2, ret_acc);
+	compare_int3v(exp_acc, ret_acc);
+
+	/* Set range to 4G */
+	zassert_equal(EC_SUCCESS, ms.drv->set_range(&ms, 4, 0));
+
+	/* Test read with rotation */
+	zassert_equal(EC_SUCCESS, ms.drv->read(&ms, ret_acc_v));
+	drv_acc_to_emul(ret_acc_v, 4, ret_acc);
+	compare_int3v(exp_acc, ret_acc);
+}
+
+/** Data for functions used in perform_calib test */
+struct calib_func_data {
+	/** Time when offset compensation where triggered */
+	int calib_start;
+	/** Time how long offset cal ready should be unset */
+	int time;
+	/** Flag indicate if read should fail after compensation is triggered */
+	int read_fail;
+};
+
+/**
+ * Custom emulator read function used in perform_calib test. It controls if
+ * cal ready bit in offset control register should be set. It is set after
+ * data.time miliseconds passed from data.calib_start time. Function returns
+ * error when offset control register is accessed when cal ready bit is not set
+ * and data.read_fail is not zero.
+ */
+static int emul_read_calib_func(const struct emul *emul, int reg, uint8_t *val,
+				int bytes, void *data)
+{
+	struct calib_func_data *d = data;
+	uint8_t reg_val;
+	int cur_time;
+
+	reg = bma_emul_access_reg(emul, reg, bytes, true /* = read */);
+	if (reg != BMA2x2_OFFSET_CTRL_ADDR) {
+		return 1;
+	}
+
+	reg_val = bma_emul_get_reg(emul, BMA2x2_OFFSET_CTRL_ADDR);
+	cur_time = k_uptime_get_32();
+	if (cur_time - d->calib_start < d->time) {
+		if (d->read_fail) {
+			return -EIO;
+		}
+		reg_val &= ~BMA2x2_OFFSET_CAL_READY;
+	} else {
+		reg_val |= BMA2x2_OFFSET_CAL_READY;
+	}
+	bma_emul_set_reg(emul, BMA2x2_OFFSET_CTRL_ADDR, reg_val);
+
+	return 1;
+}
+
+/**
+ * Custom emulator write function used in perform_calib test. It sets
+ * calib_start field in data with time when offset compensation process was
+ * triggerd.
+ */
+static int emul_write_calib_func(const struct emul *emul, int reg, uint8_t val,
+				 int bytes, void *data)
+{
+	struct calib_func_data *d = data;
+
+	reg = bma_emul_access_reg(emul, reg, bytes, false /* = read */);
+	if (reg != BMA2x2_OFFSET_CTRL_ADDR) {
+		return 1;
+	}
+
+	if (val & BMA2x2_OFFSET_TRIGGER_MASK) {
+		d->calib_start = k_uptime_get_32();
+	}
+
+	return 1;
+}
+
+/** Test offset compensation with and without I2C errors. */
+ZTEST_USER(bma2x2, test_bma_perform_calib)
+{
+	struct calib_func_data func_data;
+	const struct emul *emul = EMUL_DT_GET(BMA_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bma_get_i2c_common_data(emul);
+	int16_t start_off[3];
+	int16_t exp_off[3];
+	int16_t ret_off[3];
+	int range;
+	int rate;
+	mat33_fp_t rot = { { FLOAT_TO_FP(1), 0, 0 },
+			   { 0, FLOAT_TO_FP(1), 0 },
+			   { 0, 0, FLOAT_TO_FP(-1) } };
+
+	/* Range and rate cannot change after calibration */
+	range = 4;
+	rate = 125000;
+	zassert_equal(EC_SUCCESS, ms.drv->set_range(&ms, range, 0));
+	zassert_equal(EC_SUCCESS, ms.drv->set_data_rate(&ms, rate, 0));
+
+	/* Set offset 0 */
+	start_off[0] = 0;
+	start_off[1] = 0;
+	start_off[2] = 0;
+	set_emul_offset(emul, start_off);
+
+	/* Set input accelerometer values */
+	exp_off[0] = BMA_EMUL_1G / 10;
+	exp_off[1] = BMA_EMUL_1G / 20;
+	exp_off[2] = -(int)BMA_EMUL_1G / 30;
+	set_emul_acc(emul, exp_off);
+
+	/*
+	 * Expected offset is [-X, -Y, 1G - Z] for no rotation or positive
+	 * rotation on Z axis
+	 */
+	exp_off[0] = -exp_off[0];
+	exp_off[1] = -exp_off[1];
+	exp_off[2] = BMA_EMUL_1G - exp_off[2];
+
+	/* Setup emulator calibration functions */
+	i2c_common_emul_set_read_func(common_data, emul_read_calib_func,
+				      &func_data);
+	i2c_common_emul_set_write_func(common_data, emul_write_calib_func,
+				       &func_data);
+
+	/* Setup emulator to fail on first access to offset control register */
+	func_data.calib_start = k_uptime_get_32();
+	func_data.read_fail = 1;
+	func_data.time = 1000000;
+
+	/* Test success on disabling calibration */
+	zassert_equal(EC_SUCCESS, ms.drv->perform_calib(&ms, 0));
+	zassert_equal(range, ms.current_range);
+	zassert_equal(rate, ms.drv->get_data_rate(&ms));
+
+	/* Test fail on first access to offset control register */
+	zassert_equal(EC_ERROR_INVAL, ms.drv->perform_calib(&ms, 1));
+	zassert_equal(range, ms.current_range);
+	zassert_equal(rate, ms.drv->get_data_rate(&ms));
+
+	/* Setup emulator to return cal not ready */
+	func_data.calib_start = k_uptime_get_32();
+	func_data.read_fail = 0;
+	func_data.time = 1000000;
+
+	/* Test fail on cal not ready */
+	zassert_equal(EC_ERROR_ACCESS_DENIED, ms.drv->perform_calib(&ms, 1),
+		      NULL);
+	zassert_equal(range, ms.current_range);
+	zassert_equal(rate, ms.drv->get_data_rate(&ms));
+
+	/*
+	 * Setup emulator to fail on access to offset control register after
+	 * triggering offset compensation
+	 */
+	func_data.calib_start = 0;
+	func_data.read_fail = 1;
+	func_data.time = 160;
+
+	/* Test fail on read during offset compensation */
+	zassert_equal(EC_ERROR_INVAL, ms.drv->perform_calib(&ms, 1));
+	zassert_equal(range, ms.current_range);
+	zassert_equal(rate, ms.drv->get_data_rate(&ms));
+
+	/*
+	 * Setup emulator to return cal not ready for 1s after triggering
+	 * offset compensation
+	 */
+	func_data.calib_start = 0;
+	func_data.read_fail = 0;
+	func_data.time = 1000;
+
+	zassert_equal(EC_RES_TIMEOUT, ms.drv->perform_calib(&ms, 1));
+	zassert_equal(range, ms.current_range);
+	zassert_equal(rate, ms.drv->get_data_rate(&ms));
+
+	/*
+	 * Setup emulator to return cal not ready for 160ms after triggering
+	 * offset compensation
+	 */
+	func_data.calib_start = 0;
+	func_data.read_fail = 0;
+	func_data.time = 160;
+	/* Disable rotation */
+	ms.rot_standard_ref = NULL;
+
+	/* Test successful offset compenastion without rotation */
+	zassert_equal(EC_SUCCESS, ms.drv->perform_calib(&ms, 1));
+	zassert_equal(range, ms.current_range);
+	zassert_equal(rate, ms.drv->get_data_rate(&ms));
+	get_emul_offset(emul, ret_off);
+	compare_int3v(exp_off, ret_off);
+
+	func_data.calib_start = 0;
+	/* Enable rotation with negative value on Z axis */
+	ms.rot_standard_ref = &rot;
+	/* Expected offset -1G - accelerometer[Z] */
+	exp_off[2] =
+		-((int)BMA_EMUL_1G) - bma_emul_get_acc(emul, BMA_EMUL_AXIS_Z);
+
+	/* Test successful offset compenastion with negative Z rotation */
+	zassert_equal(EC_SUCCESS, ms.drv->perform_calib(&ms, 1));
+	zassert_equal(range, ms.current_range);
+	zassert_equal(rate, ms.drv->get_data_rate(&ms));
+	get_emul_offset(emul, ret_off);
+	compare_int3v(exp_off, ret_off);
+
+	func_data.calib_start = 0;
+	/* Set positive rotation on Z axis */
+	rot[2][2] = FLOAT_TO_FP(1);
+	/* Expected offset 1G - accelerometer[Z] */
+	exp_off[2] = BMA_EMUL_1G - bma_emul_get_acc(emul, BMA_EMUL_AXIS_Z);
+
+	/* Test successful offset compenastion with positive Z rotation */
+	zassert_equal(EC_SUCCESS, ms.drv->perform_calib(&ms, 1));
+	zassert_equal(range, ms.current_range);
+	zassert_equal(rate, ms.drv->get_data_rate(&ms));
+	get_emul_offset(emul, ret_off);
+	compare_int3v(exp_off, ret_off);
+
+	/* Remove custom emulator functions */
+	i2c_common_emul_set_read_func(common_data, NULL, NULL);
+	i2c_common_emul_set_write_func(common_data, NULL, NULL);
+}
+
+/** Test get resolution. */
+ZTEST_USER(bma2x2, test_bma_get_resolution)
+{
+	/* Resolution should be always 12 bits */
+	zassert_equal(12, ms.drv->get_resolution(&ms));
+}
+
+static void *bma2x2_setup(void)
+{
+	k_mutex_init(&sensor_mutex);
+
+	return NULL;
+}
+
+static void bma2x2_after(void *data)
+{
+	ms.rot_standard_ref = NULL;
+}
+
+ZTEST_SUITE(bma2x2, drivers_predicate_post_main, bma2x2_setup, NULL,
+	    bma2x2_after, NULL);
diff --git a/zephyr/test/drivers/default/src/bma4xx.c b/zephyr/test/drivers/default/src/bma4xx.c
new file mode 100644
index 0000000000..86ed8edcfe
--- /dev/null
+++ b/zephyr/test/drivers/default/src/bma4xx.c
@@ -0,0 +1,460 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "accelgyro.h"
+#include "common.h"
+#include "driver/accel_bma4xx.h"
+#include "emul/emul_bma4xx.h"
+#include "emul/emul_common_i2c.h"
+#include "i2c.h"
+#include "motion_sense.h"
+#include "motion_sense_fifo.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/fff.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/ztest.h>
+
+#define EMUL EMUL_DT_GET(DT_NODELABEL(bma422_emul))
+#define SENSOR bma4xx_emul_get_sensor_data(EMUL)
+
+LOG_MODULE_REGISTER(test_bma4xx, LOG_LEVEL_INF);
+
+ZTEST_SUITE(bma4xx, drivers_predicate_post_main, NULL, NULL, NULL, NULL);
+
+static int read_wrong_chip_id(const struct emul *target, int reg, uint8_t *val,
+			      int bytes, void *data)
+{
+	if (reg == BMA4_CHIP_ID_ADDR) {
+		*val = 0x13;
+		return 0;
+	}
+	return 1;
+}
+
+ZTEST_USER(bma4xx, test_init)
+{
+	/* Basic initialization works. */
+	zassert_ok(bma4_accel_drv.init(SENSOR));
+
+	/* Sensor gets turned off if it was already on. */
+	bma4xx_emul_set_accel_enabled(EMUL, true);
+	zassert_ok(bma4_accel_drv.init(SENSOR));
+	zassert_false(bma4xx_emul_is_accel_enabled(EMUL));
+
+	/* Unexpected chip ID is an error. */
+	i2c_common_emul_set_read_func(bma4xx_emul_get_i2c(EMUL),
+				      read_wrong_chip_id, NULL);
+	zassert_equal(EC_ERROR_HW_INTERNAL, bma4_accel_drv.init(SENSOR));
+}
+
+ZTEST_USER(bma4xx, test_set_range)
+{
+	/* Sets to ±16g successfully. */
+	zassert_ok(bma4_accel_drv.set_range(SENSOR, 16, 0));
+	zassert_equal(16, bma4xx_emul_get_accel_range(EMUL));
+
+	/* ±3g with roundup flag is ±4. */
+	zassert_ok(bma4_accel_drv.set_range(SENSOR, 3, 1));
+	zassert_equal(4, bma4xx_emul_get_accel_range(EMUL));
+
+	/* .. ±2g without roundup flag. */
+	zassert_ok(bma4_accel_drv.set_range(SENSOR, 3, 0));
+	zassert_equal(2, bma4xx_emul_get_accel_range(EMUL));
+
+	/* Communication errors bubble up and don't change the range. */
+	i2c_common_emul_set_write_fail_reg(bma4xx_emul_get_i2c(EMUL),
+					   BMA4_ACCEL_RANGE_ADDR);
+	zassert_not_equal(0, bma4_accel_drv.set_range(SENSOR, 8, 0));
+	zassert_equal(2, bma4xx_emul_get_accel_range(EMUL));
+}
+
+ZTEST_USER(bma4xx, test_data_rate)
+{
+	int odr;
+
+	/* Requesting zero ODR disables the sensor. */
+	bma4xx_emul_set_accel_enabled(EMUL, true);
+	zassert_ok(bma4_accel_drv.set_data_rate(SENSOR, 0, 0));
+	zassert_false(bma4xx_emul_is_accel_enabled(EMUL));
+
+	/*
+	 * Minimum supported ODR is 0.78125 Hz; smaller requested values should
+	 * still yield a nonzero ODR and enable a previously-disabled sensor.
+	 */
+	zassert_ok(bma4_accel_drv.set_data_rate(SENSOR, 200, 0));
+	zassert_true(bma4xx_emul_is_accel_enabled(EMUL));
+	odr = bma4_accel_drv.get_data_rate(SENSOR);
+	zassert_equal(781, odr, "actual reported data rate was %d mHz", odr);
+	zassert_equal(781, bma4xx_emul_get_odr(EMUL),
+		      "emulator ODR did not match driver ODR");
+
+	/*
+	 * Faster than can be supported goes to the maximum possible ODR. 4 kHz
+	 * rounds down to 3.2 kHz which is still too high, so we actually get
+	 * 1.6 kHz.
+	 */
+	zassert_ok(bma4_accel_drv.set_data_rate(SENSOR, 4000 * 1000, 0));
+	odr = bma4_accel_drv.get_data_rate(SENSOR);
+	zassert_equal(1600 * 1000, odr, "actual reported data rate was %d mHz",
+		      odr);
+	zassert_equal(1600 * 1000, bma4xx_emul_get_odr(EMUL),
+		      "emulator ODR did not match driver ODR");
+
+	/* Rounds up only if requested, otherwise down. */
+	zassert_ok(bma4_accel_drv.set_data_rate(SENSOR, 160 * 1000, 0));
+	odr = bma4xx_emul_get_odr(EMUL);
+	zassert_equal(100 * 1000, odr, "actual ODR was %d", odr);
+	zassert_ok(bma4_accel_drv.set_data_rate(SENSOR, 160 * 1000, 1));
+	odr = bma4xx_emul_get_odr(EMUL);
+	zassert_equal(200 * 1000, odr, "actual ODR was %d", odr);
+
+	/* Communication errors bubble up and reported ODR is unchanged. */
+	i2c_common_emul_set_write_fail_reg(bma4xx_emul_get_i2c(EMUL),
+					   BMA4_ACCEL_CONFIG_ADDR);
+	zassert_not_equal(0,
+			  bma4_accel_drv.set_data_rate(SENSOR, 100 * 1000, 0));
+	zassert_equal(200 * 1000, bma4_accel_drv.get_data_rate(SENSOR));
+}
+
+ZTEST_USER(bma4xx, test_read_data)
+{
+	intv3_t acceleration;
+
+	bma4xx_emul_set_accel_data(EMUL, 627, 1, -809);
+	zassert_ok(bma4_accel_drv.read(SENSOR, acceleration));
+	/*
+	 * read() returns raw sensor data, which is shifted. The consumer of the
+	 * data is expected to know this and possibly also compensate for
+	 * scaling when the sensitivity changes.
+	 */
+	zassert_equal(acceleration[0], 627 << 4, "actual value was %d",
+		      acceleration[0]);
+	zassert_equal(acceleration[1], 1 << 4, "actual value was %d",
+		      acceleration[1]);
+	zassert_equal(acceleration[2], -(809 << 4), "actual value was %d",
+		      acceleration[2]);
+
+	/* Communication errors bubble up. */
+	i2c_common_emul_set_read_fail_reg(bma4xx_emul_get_i2c(EMUL),
+					  BMA4_DATA_8_ADDR);
+	zassert_not_equal(bma4_accel_drv.read(SENSOR, acceleration), 0);
+}
+
+ZTEST_USER(bma4xx, test_offset)
+{
+	int16_t offsets[] = { 4, -40, 400 };
+	int8_t offset_regs[3];
+	uint16_t temperature;
+
+	/* set_offset writes offsets successfully. */
+	zassert_ok(bma4_accel_drv.set_offset(SENSOR, offsets, 0));
+	bma4xx_emul_get_offset(EMUL, &offset_regs);
+	/*
+	 * Parameter to set_offset is in milli-g, but register values are 3.9mg
+	 * per LSb; driver scales the inputs as needed, rounding to nearest
+	 * integer.
+	 */
+	zassert_equal(offset_regs[0], 1, "actual value is %d", offset_regs[0]);
+	zassert_equal(offset_regs[1], -10, "actual value is %d",
+		      offset_regs[1]);
+	zassert_equal(offset_regs[2], 103, "actual value is %d",
+		      offset_regs[2]);
+
+	/* get_offset agrees with the programmed offsets, scaled back to mg. */
+	memset(offsets, 0, sizeof(offsets));
+	zassert_ok(bma4_accel_drv.get_offset(SENSOR, offsets, &temperature));
+	zassert_equal(offsets[0], 4, "actual value is %d", offsets[0]);
+	zassert_equal(offsets[1], -39, "actual value is %d", offsets[1]);
+	zassert_equal(offsets[2], 402, "actual value is %d", offsets[2]);
+
+	/* Out of range offsets are clamped to the accepted range. */
+	offsets[0] = 684;
+	offsets[1] = -800;
+	offsets[2] = 0;
+	zassert_ok(bma4_accel_drv.set_offset(SENSOR, offsets, 0));
+	bma4xx_emul_get_offset(EMUL, &offset_regs);
+	zassert_equal(offset_regs[0], 127);
+	zassert_equal(offset_regs[1], -128);
+	zassert_equal(offset_regs[2], 0);
+
+	/* Communication errors bubble up. */
+	i2c_common_emul_set_write_fail_reg(bma4xx_emul_get_i2c(EMUL),
+					   BMA4_OFFSET_1_ADDR);
+	zassert_not_equal(bma4_accel_drv.set_offset(SENSOR, offsets, 0), 0);
+	i2c_common_emul_set_read_fail_reg(bma4xx_emul_get_i2c(EMUL),
+					  BMA4_OFFSET_0_ADDR);
+	zassert_not_equal(
+		bma4_accel_drv.get_offset(SENSOR, offsets, &temperature), 0);
+}
+
+ZTEST_USER(bma4xx, test_resolution)
+{
+	/* Resolution is always 12 bits. */
+	zassert_equal(bma4_accel_drv.get_resolution(SENSOR), 12);
+}
+
+ZTEST_USER(bma4xx, test_interrupt)
+{
+	uint8_t int_map_data, int1_io_ctrl;
+	bool int_latched_mode;
+	const uint8_t two_frames_data[] = {
+		4 << 4,
+		0,
+		(42 & 0xF) << 4,
+		42 >> 4,
+		(421 & 0xF) << 4,
+		421 >> 4,
+		0,
+		0,
+		0,
+		0,
+		1 << 4,
+		0,
+	};
+	uint32_t evt = CONFIG_ACCEL_BMA4XX_INT_EVENT;
+	struct ec_response_motion_sensor_data host_data[8];
+	int host_frames_read;
+	uint16_t host_data_sz;
+
+	/* Run init to get interrupts configured. */
+	zassert_ok(bma4_accel_drv.init(SENSOR));
+	/* Verify interrupt configuration is as expected. */
+	zassert_true(bma4xx_emul_is_fifo_enabled(EMUL));
+	int_map_data = bma4xx_emul_get_interrupt_config(EMUL, &int1_io_ctrl,
+							&int_latched_mode);
+	zassert_equal(int_map_data, 0x07); /* all interrupts on INT1 */
+	/* INT1 output enabled, active-low push-pull. */
+	zassert_equal(int1_io_ctrl, 0x08);
+	zassert_true(int_latched_mode);
+
+	/* Ensure every sample gets queued to the AP. */
+	SENSOR->oversampling_ratio = 1;
+
+	/* Queue two samples of data and run the interrupt handler. */
+	bma4xx_emul_set_fifo_data(EMUL, two_frames_data,
+				  sizeof(two_frames_data));
+	zassert_ok(bma4_accel_drv.irq_handler(SENSOR, &evt));
+
+	/*
+	 * Retrieve the data that should have been queued for the host by the
+	 * interrupt handler.
+	 */
+	host_frames_read = motion_sense_fifo_read(sizeof(host_data),
+						  ARRAY_SIZE(host_data),
+						  &host_data, &host_data_sz);
+	BUILD_ASSERT(ARRAY_SIZE(host_data) > 4,
+		     "must be possible to retrieve "
+		     "more than the expected number of frames");
+	zassert_equal(host_frames_read, 4,
+		      "actually put %d frames into the FIFO", host_frames_read);
+
+	/* First frame is a timestamp which we don't care about. */
+	zassert_equal(host_data[0].flags, MOTIONSENSE_SENSOR_FLAG_TIMESTAMP);
+	/* Next is the first sample from the sensor. */
+	zassert_equal(host_data[1].flags, 0);
+	zassert_equal(host_data[1].sensor_num, bma4xx_emul_get_sensor_num(EMUL),
+		      "data was generated by an unexpected sensor");
+	zassert_equal(host_data[1].data[0], 0x40, "X accel was %d",
+		      host_data[1].data[0]);
+	zassert_equal(host_data[1].data[1], 42 << 4, "Y accel was %d",
+		      host_data[1].data[1]);
+	zassert_equal(host_data[1].data[2], 421 << 4, "Z accel was %d",
+		      host_data[1].data[2]);
+	/* Another uninteresting timestamp frame. */
+	zassert_equal(host_data[2].flags, MOTIONSENSE_SENSOR_FLAG_TIMESTAMP);
+	/* And the second sample from the sensor. */
+	zassert_equal(host_data[3].flags, 0);
+	zassert_equal(host_data[3].sensor_num, bma4xx_emul_get_sensor_num(EMUL),
+		      "data was generated by an unexpected sensor");
+	zassert_equal(host_data[3].data[0], 0, "X accel was %d",
+		      host_data[3].data[0]);
+	zassert_equal(host_data[3].data[1], 0, "Y accel was %d",
+		      host_data[3].data[1]);
+	zassert_equal(host_data[3].data[2], 1 << 4, "Z accel was %d",
+		      host_data[3].data[2]);
+}
+
+/**
+ * This struct captures I2C transactions during the calibration test.
+ *
+ * Using a bespoke log like this rather than <zephyr/fff.h> fakes is simpler
+ * to understand because it records only the relevant information. The
+ * calibration_read_byte and calibration_write_byte functions are responsible
+ * for logging each read or write transaction into a log, for inspection later.
+ */
+struct calibration_log {
+	struct {
+		uint8_t addr;
+		bool write;
+		uint8_t write_val;
+	} activity[256];
+	size_t count;
+};
+
+static int calibration_read_byte(const struct emul *emul, int reg, uint8_t *val,
+				 int bytes, void *ctx)
+{
+	struct calibration_log *log = ctx;
+	/* Sensor is reading 0, 0, +0.992g at 4g sensitivity. */
+	const uint8_t acc_data[6] = { 0, 0, 0, 0, (508 & 0xF) << 4, 508 >> 4 };
+
+	zassert_true(log->count <= ARRAY_SIZE(log->activity),
+		     "i2c log overflowed");
+
+	reg += bytes; /* burst reads */
+	log->activity[log->count].write = false;
+	log->activity[log->count].addr = reg;
+	log->count++;
+
+	switch (reg) {
+	case BMA4_STATUS_ADDR:
+		*val = 0x90; /* drdy_acc + cmd_rdy */
+		break;
+	case BMA4_DATA_8_ADDR:
+	case BMA4_DATA_8_ADDR + 1:
+	case BMA4_DATA_8_ADDR + 2:
+	case BMA4_DATA_8_ADDR + 3:
+	case BMA4_DATA_8_ADDR + 4:
+	case BMA4_DATA_8_ADDR + 5:
+		*val = acc_data[reg - BMA4_DATA_8_ADDR];
+		break;
+	default:
+		*val = 0;
+	}
+	return 0;
+}
+
+static int calibration_write_byte(const struct emul *emul, int reg, uint8_t val,
+				  int bytes, void *ctx)
+{
+	struct calibration_log *log = ctx;
+
+	__ASSERT_NO_MSG(bytes >= 1);
+	reg += bytes - 1; /* burst writes */
+
+	log->activity[log->count].write = true;
+	log->activity[log->count].addr = reg;
+	log->activity[log->count].write_val = val;
+	log->count++;
+
+	return 0;
+}
+
+ZTEST_USER(bma4xx, test_calibration)
+{
+	struct calibration_log log = {
+		.count = 0,
+	};
+	size_t log_asserted = 0;
+
+/**
+ * Macro that walks through the calibration log, asserting on each operation.
+ *
+ * Each use of ASSERT_NEXT consumes the oldest entry (increments log_asserted)
+ * and checks that entry for being the correct kind of transaction against the
+ * expected register, and that the expected value was written if it was a write.
+ */
+#define ASSERT_NEXT(want_write, want_addr, want_write_val)                     \
+	do {                                                                   \
+		zassert_true(log_asserted < log.count,                         \
+			     "no more logs to check (have %d entries)",        \
+			     log.count);                                       \
+                                                                               \
+		bool was_write = log.activity[log_asserted].write;             \
+		zassert_equal(was_write, want_write,                           \
+			      "transaction at index %d was a %s",              \
+			      log_asserted, was_write ? "write" : "read");     \
+                                                                               \
+		uint8_t addr = log.activity[log_asserted].addr;                \
+		zassert_equal(addr, want_addr,                                 \
+			      "transaction at index %d was with register %#x", \
+			      log_asserted, addr);                             \
+                                                                               \
+		if (want_write) {                                              \
+			uint8_t write_val =                                    \
+				log.activity[log_asserted].write_val;          \
+			zassert_equal(write_val, want_write_val,               \
+				      "write at index %d wrote value %#x",     \
+				      log_asserted, write_val);                \
+		}                                                              \
+		log_asserted++;                                                \
+	} while (0)
+
+#define ASSERT_R(addr) ASSERT_NEXT(false, addr, 0)
+#define ASSERT_W(addr, val) ASSERT_NEXT(true, addr, val)
+#define ASSERT_RW(addr, val)         \
+	do {                         \
+		ASSERT_R(addr);      \
+		ASSERT_W(addr, val); \
+	} while (0)
+
+	/* Range must be set before calibration. */
+	zassert_ok(bma4_accel_drv.set_range(SENSOR, 4, 0));
+
+	/* Record transactions in the log. */
+	i2c_common_emul_set_read_func(bma4xx_emul_get_i2c(EMUL),
+				      calibration_read_byte, &log);
+	i2c_common_emul_set_write_func(bma4xx_emul_get_i2c(EMUL),
+				       calibration_write_byte, &log);
+
+	zassert_ok(bma4_accel_drv.perform_calib(SENSOR, 1));
+
+	/* Log messages help determine where failures occur when they happen. */
+	LOG_INF("Verify configuration readout");
+	/* Read current configuration to store back on completion. */
+	ASSERT_R(BMA4_ACCEL_CONFIG_ADDR);
+	ASSERT_R(BMA4_ACCEL_RANGE_ADDR);
+	ASSERT_R(BMA4_FIFO_CONFIG_1_ADDR);
+	ASSERT_R(BMA4_POWER_CTRL_ADDR);
+	ASSERT_R(BMA4_POWER_CONF_ADDR);
+	LOG_INF("Verify configuration setting for calibration");
+	/* Disabled offset. */
+	ASSERT_RW(BMA4_NV_CONFIG_ADDR, 0);
+	/* Disabled FIFO. */
+	ASSERT_W(BMA4_FIFO_CONFIG_1_ADDR, 0);
+	/* Configured to 50 Hz continuous mode. */
+	ASSERT_W(BMA4_ACCEL_CONFIG_ADDR, 0xb7);
+	/* Enabled sensor. */
+	ASSERT_RW(BMA4_POWER_CTRL_ADDR, 0x04);
+	/* Power save mode disabled. */
+	ASSERT_RW(BMA4_POWER_CONF_ADDR, 0);
+
+	/* Reads 32 samples, polling for data ready before each read. */
+	LOG_INF("Verify calibration data capture");
+	for (int i = 0; i < 32; i++) {
+		ASSERT_R(BMA4_STATUS_ADDR);
+		ASSERT_R(BMA4_DATA_8_ADDR);
+		ASSERT_R(BMA4_DATA_8_ADDR + 1);
+		ASSERT_R(BMA4_DATA_8_ADDR + 2);
+		ASSERT_R(BMA4_DATA_8_ADDR + 3);
+		ASSERT_R(BMA4_DATA_8_ADDR + 4);
+		ASSERT_R(BMA4_DATA_8_ADDR + 5);
+	}
+
+	/*
+	 * Wrote new offset. It's a small positive Z axis offset since we're
+	 * reading not quite 1g on Z.
+	 */
+	LOG_INF("Verify expected offset applied");
+	ASSERT_W(BMA4_OFFSET_0_ADDR, 0);
+	ASSERT_W(BMA4_OFFSET_1_ADDR, 0);
+	ASSERT_W(BMA4_OFFSET_2_ADDR, 0x1);
+
+	LOG_INF("Verify applied final configuration");
+	/* Re-enabled offset. */
+	ASSERT_RW(BMA4_NV_CONFIG_ADDR, BMA4_NV_ACCEL_OFFSET_MSK);
+	/* Restored the original configuration. */
+	ASSERT_W(BMA4_ACCEL_CONFIG_ADDR, 0);
+	ASSERT_W(BMA4_ACCEL_RANGE_ADDR, 0);
+	ASSERT_W(BMA4_FIFO_CONFIG_1_ADDR, 0);
+	ASSERT_W(BMA4_POWER_CTRL_ADDR, 0);
+	ASSERT_W(BMA4_POWER_CONF_ADDR, 0);
+
+	zassert_equal(log_asserted, log.count,
+		      "logged %d transactions, but only %d were checked",
+		      log.count, log_asserted);
+}
diff --git a/zephyr/test/drivers/default/src/bmi160.c b/zephyr/test/drivers/default/src/bmi160.c
new file mode 100644
index 0000000000..e11febbd96
--- /dev/null
+++ b/zephyr/test/drivers/default/src/bmi160.c
@@ -0,0 +1,2239 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "driver/accelgyro_bmi160.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "emul/emul_bmi.h"
+#include "emul/emul_common_i2c.h"
+#include "i2c.h"
+#include "motion_sense_fifo.h"
+#include "test/drivers/test_mocks.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+#define BMI_NODE DT_NODELABEL(accel_bmi160)
+#define BMI_ACC_SENSOR_ID SENSOR_ID(DT_NODELABEL(ms_bmi160_accel))
+#define BMI_GYR_SENSOR_ID SENSOR_ID(DT_NODELABEL(ms_bmi160_gyro))
+#define BMI_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(SENSOR_ID(DT_ALIAS(bmi160_int)))
+
+/** How accurate comparision of vectors should be */
+#define V_EPS 8
+
+/** Convert from one type of vector to another */
+#define convert_int3v_int16(v, r) \
+	do {                      \
+		r[0] = v[0];      \
+		r[1] = v[1];      \
+		r[2] = v[2];      \
+	} while (0)
+
+/** Rotation used in some tests */
+static const mat33_fp_t test_rotation = { { 0, FLOAT_TO_FP(1), 0 },
+					  { FLOAT_TO_FP(-1), 0, 0 },
+					  { 0, 0, FLOAT_TO_FP(-1) } };
+/** Rotate given vector by test rotation */
+static void rotate_int3v_by_test_rotation(intv3_t v)
+{
+	int16_t t;
+
+	t = v[0];
+	v[0] = -v[1];
+	v[1] = t;
+	v[2] = -v[2];
+}
+
+/** Set emulator accelerometer offset values to intv3_t vector */
+static void set_emul_acc_offset(const struct emul *emul, intv3_t offset)
+{
+	bmi_emul_set_off(emul, BMI_EMUL_ACC_X, offset[0]);
+	bmi_emul_set_off(emul, BMI_EMUL_ACC_Y, offset[1]);
+	bmi_emul_set_off(emul, BMI_EMUL_ACC_Z, offset[2]);
+}
+
+/** Save emulator accelerometer offset values to intv3_t vector */
+static void get_emul_acc_offset(const struct emul *emul, intv3_t offset)
+{
+	offset[0] = bmi_emul_get_off(emul, BMI_EMUL_ACC_X);
+	offset[1] = bmi_emul_get_off(emul, BMI_EMUL_ACC_Y);
+	offset[2] = bmi_emul_get_off(emul, BMI_EMUL_ACC_Z);
+}
+
+/** Set emulator accelerometer values to intv3_t vector */
+static void set_emul_acc(const struct emul *emul, intv3_t acc)
+{
+	bmi_emul_set_value(emul, BMI_EMUL_ACC_X, acc[0]);
+	bmi_emul_set_value(emul, BMI_EMUL_ACC_Y, acc[1]);
+	bmi_emul_set_value(emul, BMI_EMUL_ACC_Z, acc[2]);
+}
+
+/** Set emulator gyroscope offset values to intv3_t vector */
+static void set_emul_gyr_offset(const struct emul *emul, intv3_t offset)
+{
+	bmi_emul_set_off(emul, BMI_EMUL_GYR_X, offset[0]);
+	bmi_emul_set_off(emul, BMI_EMUL_GYR_Y, offset[1]);
+	bmi_emul_set_off(emul, BMI_EMUL_GYR_Z, offset[2]);
+}
+
+/** Save emulator gyroscope offset values to intv3_t vector */
+static void get_emul_gyr_offset(const struct emul *emul, intv3_t offset)
+{
+	offset[0] = bmi_emul_get_off(emul, BMI_EMUL_GYR_X);
+	offset[1] = bmi_emul_get_off(emul, BMI_EMUL_GYR_Y);
+	offset[2] = bmi_emul_get_off(emul, BMI_EMUL_GYR_Z);
+}
+
+/** Set emulator gyroscope values to vector of three int16_t */
+static void set_emul_gyr(const struct emul *emul, intv3_t gyr)
+{
+	bmi_emul_set_value(emul, BMI_EMUL_GYR_X, gyr[0]);
+	bmi_emul_set_value(emul, BMI_EMUL_GYR_Y, gyr[1]);
+	bmi_emul_set_value(emul, BMI_EMUL_GYR_Z, gyr[2]);
+}
+
+/** Convert accelerometer read to units used by emulator */
+static void drv_acc_to_emul(intv3_t drv, int range, intv3_t out)
+{
+	const int scale = MOTION_SCALING_FACTOR / BMI_EMUL_1G;
+
+	out[0] = drv[0] * range / scale;
+	out[1] = drv[1] * range / scale;
+	out[2] = drv[2] * range / scale;
+}
+
+/** Convert gyroscope read to units used by emulator */
+static void drv_gyr_to_emul(intv3_t drv, int range, intv3_t out)
+{
+	const int scale = MOTION_SCALING_FACTOR / BMI_EMUL_125_DEG_S;
+
+	range /= 125;
+	out[0] = drv[0] * range / scale;
+	out[1] = drv[1] * range / scale;
+	out[2] = drv[2] * range / scale;
+}
+
+/** Compare two vectors of intv3_t type */
+static void compare_int3v_f(intv3_t exp_v, intv3_t v, int eps, int line)
+{
+	int i;
+
+	for (i = 0; i < 3; i++) {
+		zassert_within(
+			exp_v[i], v[i], eps,
+			"Expected [%d; %d; %d], got [%d; %d; %d]; line: %d",
+			exp_v[0], exp_v[1], exp_v[2], v[0], v[1], v[2], line);
+	}
+}
+#define compare_int3v_eps(exp_v, v, e) compare_int3v_f(exp_v, v, e, __LINE__)
+#define compare_int3v(exp_v, v) compare_int3v_eps(exp_v, v, V_EPS)
+
+/** Test get accelerometer offset with and without rotation */
+ZTEST_USER(bmi160, test_bmi_acc_get_offset)
+{
+	struct motion_sensor_t *ms;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bmi_get_i2c_common_data(emul);
+	int16_t ret[3];
+	intv3_t ret_v;
+	intv3_t exp_v;
+	int16_t temp;
+
+	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
+
+	/* Set emulator offset */
+	exp_v[0] = BMI_EMUL_1G / 10;
+	exp_v[1] = BMI_EMUL_1G / 20;
+	exp_v[2] = -(int)BMI_EMUL_1G / 30;
+	set_emul_acc_offset(emul, exp_v);
+	/* BMI driver returns value in mg units */
+	exp_v[0] = 1000 / 10;
+	exp_v[1] = 1000 / 20;
+	exp_v[2] = -1000 / 30;
+
+	/* Test fail on offset read */
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_OFFSET_ACC70);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->get_offset(ms, ret, &temp),
+		      NULL);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_OFFSET_ACC70 + 1);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->get_offset(ms, ret, &temp),
+		      NULL);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_OFFSET_ACC70 + 2);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->get_offset(ms, ret, &temp),
+		      NULL);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Disable rotation */
+	ms->rot_standard_ref = NULL;
+
+	/* Test get offset without rotation */
+	zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp));
+	zassert_equal(temp, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP);
+	convert_int3v_int16(ret, ret_v);
+	compare_int3v(exp_v, ret_v);
+
+	/* Setup rotation and rotate expected offset */
+	ms->rot_standard_ref = &test_rotation;
+	rotate_int3v_by_test_rotation(exp_v);
+
+	/* Test get offset with rotation */
+	zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp));
+	zassert_equal(temp, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP);
+	convert_int3v_int16(ret, ret_v);
+	compare_int3v(exp_v, ret_v);
+}
+
+/** Test get gyroscope offset with and without rotation */
+ZTEST_USER(bmi160, test_bmi_gyr_get_offset)
+{
+	struct motion_sensor_t *ms;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bmi_get_i2c_common_data(emul);
+	int16_t ret[3];
+	intv3_t ret_v;
+	intv3_t exp_v;
+	int16_t temp;
+
+	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
+
+	/* Do not fail on read */
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Set emulator offset */
+	exp_v[0] = BMI_EMUL_125_DEG_S / 100;
+	exp_v[1] = BMI_EMUL_125_DEG_S / 200;
+	exp_v[2] = -(int)BMI_EMUL_125_DEG_S / 300;
+	set_emul_gyr_offset(emul, exp_v);
+	/* BMI driver returns value in mdeg/s units */
+	exp_v[0] = 125000 / 100;
+	exp_v[1] = 125000 / 200;
+	exp_v[2] = -125000 / 300;
+
+	/* Test fail on offset read */
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_OFFSET_GYR70);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->get_offset(ms, ret, &temp),
+		      NULL);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_OFFSET_GYR70 + 1);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->get_offset(ms, ret, &temp),
+		      NULL);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_OFFSET_GYR70 + 2);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->get_offset(ms, ret, &temp),
+		      NULL);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_OFFSET_EN_GYR98);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->get_offset(ms, ret, &temp),
+		      NULL);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Disable rotation */
+	ms->rot_standard_ref = NULL;
+
+	/* Test get offset without rotation */
+	zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp));
+	zassert_equal(temp, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP);
+	convert_int3v_int16(ret, ret_v);
+	compare_int3v_eps(exp_v, ret_v, 64);
+
+	/* Setup rotation and rotate expected offset */
+	ms->rot_standard_ref = &test_rotation;
+	rotate_int3v_by_test_rotation(exp_v);
+
+	/* Test get offset with rotation */
+	zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp));
+	zassert_equal(temp, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP);
+	convert_int3v_int16(ret, ret_v);
+	compare_int3v_eps(exp_v, ret_v, 64);
+}
+
+/**
+ * Test set accelerometer offset with and without rotation. Also test behaviour
+ * on I2C error.
+ */
+ZTEST_USER(bmi160, test_bmi_acc_set_offset)
+{
+	struct motion_sensor_t *ms;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bmi_get_i2c_common_data(emul);
+	int16_t input_v[3];
+	int16_t temp = 0;
+	intv3_t ret_v;
+	intv3_t exp_v;
+
+	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
+
+	/* Test fail on OFFSET EN GYR98 register read and write */
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_OFFSET_EN_GYR98);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
+		      NULL);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(common_data, BMI160_OFFSET_EN_GYR98);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
+		      NULL);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test fail on offset write */
+	i2c_common_emul_set_write_fail_reg(common_data, BMI160_OFFSET_ACC70);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
+		      NULL);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   BMI160_OFFSET_ACC70 + 1);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
+		      NULL);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   BMI160_OFFSET_ACC70 + 2);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
+		      NULL);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Set input offset */
+	exp_v[0] = BMI_EMUL_1G / 10;
+	exp_v[1] = BMI_EMUL_1G / 20;
+	exp_v[2] = -(int)BMI_EMUL_1G / 30;
+	/* BMI driver accept value in mg units */
+	input_v[0] = 1000 / 10;
+	input_v[1] = 1000 / 20;
+	input_v[2] = -1000 / 30;
+	/* Disable rotation */
+	ms->rot_standard_ref = NULL;
+
+	/* Test set offset without rotation */
+	zassert_equal(EC_SUCCESS, ms->drv->set_offset(ms, input_v, temp));
+	get_emul_acc_offset(emul, ret_v);
+	/*
+	 * Depending on used range, accelerometer values may be up to 6 bits
+	 * more accurate then offset value resolution.
+	 */
+	compare_int3v_eps(exp_v, ret_v, 64);
+	/* Accelerometer offset should be enabled */
+	zassert_true(bmi_emul_get_reg(emul, BMI160_OFFSET_EN_GYR98) &
+			     BMI160_OFFSET_ACC_EN,
+		     NULL);
+
+	/* Setup rotation and rotate input for set_offset function */
+	ms->rot_standard_ref = &test_rotation;
+	convert_int3v_int16(input_v, ret_v);
+	rotate_int3v_by_test_rotation(ret_v);
+	convert_int3v_int16(ret_v, input_v);
+
+	/* Test set offset with rotation */
+	zassert_equal(EC_SUCCESS, ms->drv->set_offset(ms, input_v, temp));
+	get_emul_acc_offset(emul, ret_v);
+	compare_int3v_eps(exp_v, ret_v, 64);
+	/* Accelerometer offset should be enabled */
+	zassert_true(bmi_emul_get_reg(emul, BMI160_OFFSET_EN_GYR98) &
+			     BMI160_OFFSET_ACC_EN,
+		     NULL);
+}
+
+/**
+ * Test set gyroscope offset with and without rotation. Also test behaviour
+ * on I2C error.
+ */
+ZTEST_USER(bmi160, test_bmi_gyr_set_offset)
+{
+	struct motion_sensor_t *ms;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bmi_get_i2c_common_data(emul);
+	int16_t input_v[3] = { 0, 0, 0 };
+	int16_t temp = 0;
+	intv3_t ret_v;
+	intv3_t exp_v;
+
+	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
+
+	/* Test fail on OFFSET EN GYR98 register read and write */
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_OFFSET_EN_GYR98);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
+		      NULL);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(common_data, BMI160_OFFSET_EN_GYR98);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
+		      NULL);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test fail on offset write */
+	i2c_common_emul_set_write_fail_reg(common_data, BMI160_OFFSET_GYR70);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
+		      NULL);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   BMI160_OFFSET_GYR70 + 1);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
+		      NULL);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   BMI160_OFFSET_GYR70 + 2);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
+		      NULL);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Set input offset */
+	exp_v[0] = BMI_EMUL_125_DEG_S / 100;
+	exp_v[1] = BMI_EMUL_125_DEG_S / 200;
+	exp_v[2] = -(int)BMI_EMUL_125_DEG_S / 300;
+	/* BMI driver accept value in mdeg/s units */
+	input_v[0] = 125000 / 100;
+	input_v[1] = 125000 / 200;
+	input_v[2] = -125000 / 300;
+	/* Disable rotation */
+	ms->rot_standard_ref = NULL;
+
+	/* Test set offset without rotation */
+	zassert_equal(EC_SUCCESS, ms->drv->set_offset(ms, input_v, temp));
+	get_emul_gyr_offset(emul, ret_v);
+	compare_int3v(exp_v, ret_v);
+	/* Gyroscope offset should be enabled */
+	zassert_true(bmi_emul_get_reg(emul, BMI160_OFFSET_EN_GYR98) &
+			     BMI160_OFFSET_GYRO_EN,
+		     NULL);
+
+	/* Setup rotation and rotate input for set_offset function */
+	ms->rot_standard_ref = &test_rotation;
+	convert_int3v_int16(input_v, ret_v);
+	rotate_int3v_by_test_rotation(ret_v);
+	convert_int3v_int16(ret_v, input_v);
+
+	/* Test set offset with rotation */
+	zassert_equal(EC_SUCCESS, ms->drv->set_offset(ms, input_v, temp));
+	get_emul_gyr_offset(emul, ret_v);
+	compare_int3v(exp_v, ret_v);
+	zassert_true(bmi_emul_get_reg(emul, BMI160_OFFSET_EN_GYR98) &
+			     BMI160_OFFSET_GYRO_EN,
+		     NULL);
+}
+
+/**
+ * Test set gyroscope offset with extreme values.
+ */
+ZTEST_USER(bmi160, test_bmi_gyr_set_offset_min_max)
+{
+	struct motion_sensor_t *ms;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	int16_t input_v[3];
+	int16_t temp = 0;
+	intv3_t ret_v;
+	intv3_t exp_v;
+
+	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
+
+	/* Set expected offsets */
+	exp_v[0] = 8176;
+	exp_v[1] = -8192;
+	exp_v[2] = 0;
+	/* Set some extreme values. */
+	input_v[0] = INT16_MAX;
+	input_v[1] = INT16_MIN;
+	input_v[2] = 0;
+	/* Disable rotation */
+	ms->rot_standard_ref = NULL;
+
+	/* Test set offset without rotation */
+	zassert_equal(EC_SUCCESS, ms->drv->set_offset(ms, input_v, temp));
+	get_emul_gyr_offset(emul, ret_v);
+	compare_int3v(exp_v, ret_v);
+	/* Gyroscope offset should be enabled */
+	zassert_true(bmi_emul_get_reg(emul, BMI160_OFFSET_EN_GYR98) &
+			     BMI160_OFFSET_GYRO_EN,
+		     NULL);
+
+	/* Setup rotation and rotate input for set_offset function */
+	ms->rot_standard_ref = &test_rotation;
+	convert_int3v_int16(input_v, ret_v);
+	rotate_int3v_by_test_rotation(ret_v);
+	convert_int3v_int16(ret_v, input_v);
+
+	/* Test set offset with rotation */
+	zassert_equal(EC_SUCCESS, ms->drv->set_offset(ms, input_v, temp));
+	get_emul_gyr_offset(emul, ret_v);
+	compare_int3v(exp_v, ret_v);
+	zassert_true(bmi_emul_get_reg(emul, BMI160_OFFSET_EN_GYR98) &
+			     BMI160_OFFSET_GYRO_EN,
+		     NULL);
+}
+
+/**
+ * Try to set accelerometer range and check if expected range was set
+ * in driver and in emulator.
+ */
+static void check_set_acc_range_f(const struct emul *emul,
+				  struct motion_sensor_t *ms, int range,
+				  int rnd, int exp_range, int line)
+{
+	uint8_t exp_range_reg;
+	uint8_t range_reg;
+
+	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, range, rnd),
+		      "set_range failed; line: %d", line);
+	zassert_equal(exp_range, ms->current_range,
+		      "Expected range %d, got %d; line %d", exp_range,
+		      ms->current_range, line);
+	range_reg = bmi_emul_get_reg(emul, BMI160_ACC_RANGE);
+
+	switch (exp_range) {
+	case 2:
+		exp_range_reg = BMI160_GSEL_2G;
+		break;
+	case 4:
+		exp_range_reg = BMI160_GSEL_4G;
+		break;
+	case 8:
+		exp_range_reg = BMI160_GSEL_8G;
+		break;
+	case 16:
+		exp_range_reg = BMI160_GSEL_16G;
+		break;
+	default:
+		/* Unknown expected range */
+		zassert_unreachable(
+			"Expected range %d not supported by device; line %d",
+			exp_range, line);
+		return;
+	}
+
+	zassert_equal(exp_range_reg, range_reg,
+		      "Expected range reg 0x%x, got 0x%x; line %d",
+		      exp_range_reg, range_reg, line);
+}
+#define check_set_acc_range(emul, ms, range, rnd, exp_range) \
+	check_set_acc_range_f(emul, ms, range, rnd, exp_range, __LINE__)
+
+/** Test set accelerometer range with and without I2C errors */
+ZTEST_USER(bmi160, test_bmi_acc_set_range)
+{
+	struct motion_sensor_t *ms;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bmi_get_i2c_common_data(emul);
+	int start_range;
+
+	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
+
+	/* Setup starting range, shouldn't be changed on error */
+	start_range = 2;
+	ms->current_range = start_range;
+	bmi_emul_set_reg(emul, BMI160_ACC_RANGE, BMI160_GSEL_2G);
+	/* Setup emulator fail on write */
+	i2c_common_emul_set_write_fail_reg(common_data, BMI160_ACC_RANGE);
+
+	/* Test fail on write */
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_range(ms, 12, 0));
+	zassert_equal(start_range, ms->current_range);
+	zassert_equal(BMI160_GSEL_2G, bmi_emul_get_reg(emul, BMI160_ACC_RANGE),
+		      NULL);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_range(ms, 12, 1));
+	zassert_equal(start_range, ms->current_range);
+	zassert_equal(BMI160_GSEL_2G, bmi_emul_get_reg(emul, BMI160_ACC_RANGE),
+		      NULL);
+
+	/* Do not fail on write */
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test setting range with rounding down */
+	check_set_acc_range(emul, ms, 1, 0, 2);
+	check_set_acc_range(emul, ms, 2, 0, 2);
+	check_set_acc_range(emul, ms, 3, 0, 2);
+	check_set_acc_range(emul, ms, 4, 0, 4);
+	check_set_acc_range(emul, ms, 5, 0, 4);
+	check_set_acc_range(emul, ms, 6, 0, 4);
+	check_set_acc_range(emul, ms, 7, 0, 4);
+	check_set_acc_range(emul, ms, 8, 0, 8);
+	check_set_acc_range(emul, ms, 9, 0, 8);
+	check_set_acc_range(emul, ms, 15, 0, 8);
+	check_set_acc_range(emul, ms, 16, 0, 16);
+	check_set_acc_range(emul, ms, 17, 0, 16);
+
+	/* Test setting range with rounding up */
+	check_set_acc_range(emul, ms, 1, 1, 2);
+	check_set_acc_range(emul, ms, 2, 1, 2);
+	check_set_acc_range(emul, ms, 3, 1, 4);
+	check_set_acc_range(emul, ms, 4, 1, 4);
+	check_set_acc_range(emul, ms, 5, 1, 8);
+	check_set_acc_range(emul, ms, 6, 1, 8);
+	check_set_acc_range(emul, ms, 7, 1, 8);
+	check_set_acc_range(emul, ms, 8, 1, 8);
+	check_set_acc_range(emul, ms, 9, 1, 16);
+	check_set_acc_range(emul, ms, 15, 1, 16);
+	check_set_acc_range(emul, ms, 16, 1, 16);
+	check_set_acc_range(emul, ms, 17, 1, 16);
+}
+
+/**
+ * Try to set gyroscope range and check if expected range was set in driver and
+ * in emulator.
+ */
+static void check_set_gyr_range_f(const struct emul *emul,
+				  struct motion_sensor_t *ms, int range,
+				  int rnd, int exp_range, int line)
+{
+	uint8_t exp_range_reg;
+	uint8_t range_reg;
+
+	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, range, rnd),
+		      "set_range failed; line: %d", line);
+	zassert_equal(exp_range, ms->current_range,
+		      "Expected range %d, got %d; line %d", exp_range,
+		      ms->current_range, line);
+	range_reg = bmi_emul_get_reg(emul, BMI160_GYR_RANGE);
+
+	switch (exp_range) {
+	case 125:
+		exp_range_reg = BMI160_DPS_SEL_125;
+		break;
+	case 250:
+		exp_range_reg = BMI160_DPS_SEL_250;
+		break;
+	case 500:
+		exp_range_reg = BMI160_DPS_SEL_500;
+		break;
+	case 1000:
+		exp_range_reg = BMI160_DPS_SEL_1000;
+		break;
+	case 2000:
+		exp_range_reg = BMI160_DPS_SEL_2000;
+		break;
+	default:
+		/* Unknown expected range */
+		zassert_unreachable(
+			"Expected range %d not supported by device; line %d",
+			exp_range, line);
+		return;
+	}
+
+	zassert_equal(exp_range_reg, range_reg,
+		      "Expected range reg 0x%x, got 0x%x; line %d",
+		      exp_range_reg, range_reg, line);
+}
+#define check_set_gyr_range(emul, ms, range, rnd, exp_range) \
+	check_set_gyr_range_f(emul, ms, range, rnd, exp_range, __LINE__)
+
+/** Test set gyroscope range with and without I2C errors */
+ZTEST_USER(bmi160, test_bmi_gyr_set_range)
+{
+	struct motion_sensor_t *ms;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bmi_get_i2c_common_data(emul);
+	int start_range;
+
+	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
+
+	/* Setup starting range, shouldn't be changed on error */
+	start_range = 250;
+	ms->current_range = start_range;
+	bmi_emul_set_reg(emul, BMI160_GYR_RANGE, BMI160_DPS_SEL_250);
+	/* Setup emulator fail on write */
+	i2c_common_emul_set_write_fail_reg(common_data, BMI160_GYR_RANGE);
+
+	/* Test fail on write */
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_range(ms, 125, 0));
+	zassert_equal(start_range, ms->current_range);
+	zassert_equal(BMI160_DPS_SEL_250,
+		      bmi_emul_get_reg(emul, BMI160_GYR_RANGE), NULL);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_range(ms, 125, 1));
+	zassert_equal(start_range, ms->current_range);
+	zassert_equal(BMI160_DPS_SEL_250,
+		      bmi_emul_get_reg(emul, BMI160_GYR_RANGE), NULL);
+
+	/* Do not fail on write */
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test setting range with rounding down */
+	check_set_gyr_range(emul, ms, 1, 0, 125);
+	check_set_gyr_range(emul, ms, 124, 0, 125);
+	check_set_gyr_range(emul, ms, 125, 0, 125);
+	check_set_gyr_range(emul, ms, 126, 0, 125);
+	check_set_gyr_range(emul, ms, 249, 0, 125);
+	check_set_gyr_range(emul, ms, 250, 0, 250);
+	check_set_gyr_range(emul, ms, 251, 0, 250);
+	check_set_gyr_range(emul, ms, 499, 0, 250);
+	check_set_gyr_range(emul, ms, 500, 0, 500);
+	check_set_gyr_range(emul, ms, 501, 0, 500);
+	check_set_gyr_range(emul, ms, 999, 0, 500);
+	check_set_gyr_range(emul, ms, 1000, 0, 1000);
+	check_set_gyr_range(emul, ms, 1001, 0, 1000);
+	check_set_gyr_range(emul, ms, 1999, 0, 1000);
+	check_set_gyr_range(emul, ms, 2000, 0, 2000);
+	check_set_gyr_range(emul, ms, 2001, 0, 2000);
+
+	/* Test setting range with rounding up */
+	check_set_gyr_range(emul, ms, 1, 1, 125);
+	check_set_gyr_range(emul, ms, 124, 1, 125);
+	check_set_gyr_range(emul, ms, 125, 1, 125);
+	check_set_gyr_range(emul, ms, 126, 1, 250);
+	check_set_gyr_range(emul, ms, 249, 1, 250);
+	check_set_gyr_range(emul, ms, 250, 1, 250);
+	check_set_gyr_range(emul, ms, 251, 1, 500);
+	check_set_gyr_range(emul, ms, 499, 1, 500);
+	check_set_gyr_range(emul, ms, 500, 1, 500);
+	check_set_gyr_range(emul, ms, 501, 1, 1000);
+	check_set_gyr_range(emul, ms, 999, 1, 1000);
+	check_set_gyr_range(emul, ms, 1000, 1, 1000);
+	check_set_gyr_range(emul, ms, 1001, 1, 2000);
+	check_set_gyr_range(emul, ms, 1999, 1, 2000);
+	check_set_gyr_range(emul, ms, 2000, 1, 2000);
+	check_set_gyr_range(emul, ms, 2001, 1, 2000);
+}
+
+/** Test get resolution of acclerometer and gyroscope sensor */
+ZTEST_USER(bmi160, test_bmi_get_resolution)
+{
+	struct motion_sensor_t *ms;
+
+	/* Test accelerometer */
+	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
+
+	/* Resolution should be always 16 bits */
+	zassert_equal(16, ms->drv->get_resolution(ms));
+
+	/* Test gyroscope */
+	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
+
+	/* Resolution should be always 16 bits */
+	zassert_equal(16, ms->drv->get_resolution(ms));
+}
+
+/**
+ * Try to set accelerometer data rate and check if expected rate was set
+ * in driver and in emulator.
+ */
+static void check_set_acc_rate_f(const struct emul *emul,
+				 struct motion_sensor_t *ms, int rate, int rnd,
+				 int exp_rate, int line)
+{
+	uint8_t exp_rate_reg;
+	uint8_t rate_reg;
+	int drv_rate;
+
+	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, rate, rnd),
+		      "set_data_rate failed; line: %d", line);
+	drv_rate = ms->drv->get_data_rate(ms);
+	zassert_equal(exp_rate, drv_rate, "Expected rate %d, got %d; line %d",
+		      exp_rate, drv_rate, line);
+	rate_reg = bmi_emul_get_reg(emul, BMI160_ACC_CONF);
+	rate_reg &= BMI_ODR_MASK;
+
+	switch (exp_rate) {
+	case 12500:
+		exp_rate_reg = 0x5;
+		break;
+	case 25000:
+		exp_rate_reg = 0x6;
+		break;
+	case 50000:
+		exp_rate_reg = 0x7;
+		break;
+	case 100000:
+		exp_rate_reg = 0x8;
+		break;
+	case 200000:
+		exp_rate_reg = 0x9;
+		break;
+	case 400000:
+		exp_rate_reg = 0xa;
+		break;
+	case 800000:
+		exp_rate_reg = 0xb;
+		break;
+	case 1600000:
+		exp_rate_reg = 0xc;
+		break;
+	default:
+		/* Unknown expected rate */
+		zassert_unreachable(
+			"Expected rate %d not supported by device; line %d",
+			exp_rate, line);
+		return;
+	}
+
+	zassert_equal(exp_rate_reg, rate_reg,
+		      "Expected rate reg 0x%x, got 0x%x; line %d", exp_rate_reg,
+		      rate_reg, line);
+}
+#define check_set_acc_rate(emul, ms, rate, rnd, exp_rate) \
+	check_set_acc_rate_f(emul, ms, rate, rnd, exp_rate, __LINE__)
+
+/** Test set and get accelerometer rate with and without I2C errors */
+ZTEST_USER(bmi160, test_bmi_acc_rate)
+{
+	struct motion_sensor_t *ms;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bmi_get_i2c_common_data(emul);
+	uint8_t reg_rate;
+	int pmu_status;
+	int drv_rate;
+
+	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
+
+	/* Test setting rate with rounding down */
+	check_set_acc_rate(emul, ms, 12500, 0, 12500);
+	check_set_acc_rate(emul, ms, 12501, 0, 12500);
+	check_set_acc_rate(emul, ms, 24999, 0, 12500);
+	check_set_acc_rate(emul, ms, 25000, 0, 25000);
+	check_set_acc_rate(emul, ms, 25001, 0, 25000);
+	check_set_acc_rate(emul, ms, 49999, 0, 25000);
+	check_set_acc_rate(emul, ms, 50000, 0, 50000);
+	check_set_acc_rate(emul, ms, 50001, 0, 50000);
+	check_set_acc_rate(emul, ms, 99999, 0, 50000);
+	check_set_acc_rate(emul, ms, 100000, 0, 100000);
+	check_set_acc_rate(emul, ms, 100001, 0, 100000);
+	check_set_acc_rate(emul, ms, 199999, 0, 100000);
+	check_set_acc_rate(emul, ms, 200000, 0, 200000);
+	check_set_acc_rate(emul, ms, 200001, 0, 200000);
+	check_set_acc_rate(emul, ms, 399999, 0, 200000);
+	/*
+	 * We cannot test frequencies from 400000 to 1600000 because
+	 * CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ is set to 250000
+	 */
+
+	/* Test setting rate with rounding up */
+	check_set_acc_rate(emul, ms, 6251, 1, 12500);
+	check_set_acc_rate(emul, ms, 12499, 1, 12500);
+	check_set_acc_rate(emul, ms, 12500, 1, 12500);
+	check_set_acc_rate(emul, ms, 12501, 1, 25000);
+	check_set_acc_rate(emul, ms, 24999, 1, 25000);
+	check_set_acc_rate(emul, ms, 25000, 1, 25000);
+	check_set_acc_rate(emul, ms, 25001, 1, 50000);
+	check_set_acc_rate(emul, ms, 49999, 1, 50000);
+	check_set_acc_rate(emul, ms, 50000, 1, 50000);
+	check_set_acc_rate(emul, ms, 50001, 1, 100000);
+	check_set_acc_rate(emul, ms, 99999, 1, 100000);
+	check_set_acc_rate(emul, ms, 100000, 1, 100000);
+	check_set_acc_rate(emul, ms, 100001, 1, 200000);
+	check_set_acc_rate(emul, ms, 199999, 1, 200000);
+	check_set_acc_rate(emul, ms, 200000, 1, 200000);
+
+	/* Test out of range rate with rounding down */
+	zassert_equal(EC_RES_INVALID_PARAM, ms->drv->set_data_rate(ms, 1, 0),
+		      NULL);
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      ms->drv->set_data_rate(ms, 12499, 0), NULL);
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      ms->drv->set_data_rate(ms, 400000, 0), NULL);
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      ms->drv->set_data_rate(ms, 2000000, 0), NULL);
+
+	/* Test out of range rate with rounding up */
+	zassert_equal(EC_RES_INVALID_PARAM, ms->drv->set_data_rate(ms, 1, 1),
+		      NULL);
+	zassert_equal(EC_RES_INVALID_PARAM, ms->drv->set_data_rate(ms, 6250, 1),
+		      NULL);
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      ms->drv->set_data_rate(ms, 200001, 1), NULL);
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      ms->drv->set_data_rate(ms, 400000, 1), NULL);
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      ms->drv->set_data_rate(ms, 2000000, 1), NULL);
+
+	/* Current rate shouldn't be changed on error */
+	drv_rate = ms->drv->get_data_rate(ms);
+	reg_rate = bmi_emul_get_reg(emul, BMI160_ACC_CONF);
+
+	/* Setup emulator fail on read */
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_ACC_CONF);
+
+	/* Test fail on read */
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 50000, 0),
+		      NULL);
+	zassert_equal(drv_rate, ms->drv->get_data_rate(ms));
+	zassert_equal(reg_rate, bmi_emul_get_reg(emul, BMI160_ACC_CONF));
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 50000, 1),
+		      NULL);
+	zassert_equal(drv_rate, ms->drv->get_data_rate(ms));
+	zassert_equal(reg_rate, bmi_emul_get_reg(emul, BMI160_ACC_CONF));
+
+	/* Do not fail on read */
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Setup emulator fail on write */
+	i2c_common_emul_set_write_fail_reg(common_data, BMI160_ACC_CONF);
+
+	/* Test fail on write */
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 50000, 0),
+		      NULL);
+	zassert_equal(drv_rate, ms->drv->get_data_rate(ms));
+	zassert_equal(reg_rate, bmi_emul_get_reg(emul, BMI160_ACC_CONF));
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 50000, 1),
+		      NULL);
+	zassert_equal(drv_rate, ms->drv->get_data_rate(ms));
+	zassert_equal(reg_rate, bmi_emul_get_reg(emul, BMI160_ACC_CONF));
+
+	/* Do not fail on write */
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test disabling sensor */
+	pmu_status = BMI160_PMU_NORMAL << BMI160_PMU_ACC_OFFSET;
+	pmu_status |= BMI160_PMU_NORMAL << BMI160_PMU_GYR_OFFSET;
+	bmi_emul_set_reg(emul, BMI160_PMU_STATUS, pmu_status);
+	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, 0, 0));
+
+	bmi_read8(ms->port, ms->i2c_spi_addr_flags, BMI160_PMU_STATUS,
+		  &pmu_status);
+	zassert_equal(BMI160_PMU_NORMAL << BMI160_PMU_GYR_OFFSET, pmu_status,
+		      "Gyroscope should be still enabled");
+
+	/* Test enabling sensor */
+	bmi_emul_set_reg(emul, BMI160_PMU_STATUS, 0);
+	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, 50000, 0));
+
+	bmi_read8(ms->port, ms->i2c_spi_addr_flags, BMI160_PMU_STATUS,
+		  &pmu_status);
+	zassert_equal(BMI160_PMU_NORMAL << BMI160_PMU_ACC_OFFSET, pmu_status,
+		      "Accelerometer should be enabled");
+}
+
+/**
+ * Try to set gyroscope data rate and check if expected rate was set
+ * in driver and in emulator.
+ */
+static void check_set_gyr_rate_f(const struct emul *emul,
+				 struct motion_sensor_t *ms, int rate, int rnd,
+				 int exp_rate, int line)
+{
+	uint8_t exp_rate_reg;
+	uint8_t rate_reg;
+	int drv_rate;
+
+	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, rate, rnd),
+		      "set_data_rate failed; line: %d", line);
+	drv_rate = ms->drv->get_data_rate(ms);
+	zassert_equal(exp_rate, drv_rate, "Expected rate %d, got %d; line %d",
+		      exp_rate, drv_rate, line);
+	rate_reg = bmi_emul_get_reg(emul, BMI160_GYR_CONF);
+	rate_reg &= BMI_ODR_MASK;
+
+	switch (exp_rate) {
+	case 25000:
+		exp_rate_reg = 0x6;
+		break;
+	case 50000:
+		exp_rate_reg = 0x7;
+		break;
+	case 100000:
+		exp_rate_reg = 0x8;
+		break;
+	case 200000:
+		exp_rate_reg = 0x9;
+		break;
+	case 400000:
+		exp_rate_reg = 0xa;
+		break;
+	case 800000:
+		exp_rate_reg = 0xb;
+		break;
+	case 1600000:
+		exp_rate_reg = 0xc;
+		break;
+	case 3200000:
+		exp_rate_reg = 0xc;
+		break;
+	default:
+		/* Unknown expected rate */
+		zassert_unreachable(
+			"Expected rate %d not supported by device; line %d",
+			exp_rate, line);
+		return;
+	}
+
+	zassert_equal(exp_rate_reg, rate_reg,
+		      "Expected rate reg 0x%x, got 0x%x; line %d", exp_rate_reg,
+		      rate_reg, line);
+}
+#define check_set_gyr_rate(emul, ms, rate, rnd, exp_rate) \
+	check_set_gyr_rate_f(emul, ms, rate, rnd, exp_rate, __LINE__)
+
+/** Test set and get gyroscope rate with and without I2C errors */
+ZTEST_USER(bmi160, test_bmi_gyr_rate)
+{
+	struct motion_sensor_t *ms;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bmi_get_i2c_common_data(emul);
+	uint8_t reg_rate;
+	int pmu_status;
+	int drv_rate;
+
+	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
+
+	/* Test setting rate with rounding down */
+	check_set_gyr_rate(emul, ms, 25000, 0, 25000);
+	check_set_gyr_rate(emul, ms, 25001, 0, 25000);
+	check_set_gyr_rate(emul, ms, 49999, 0, 25000);
+	check_set_gyr_rate(emul, ms, 50000, 0, 50000);
+	check_set_gyr_rate(emul, ms, 50001, 0, 50000);
+	check_set_gyr_rate(emul, ms, 99999, 0, 50000);
+	check_set_gyr_rate(emul, ms, 100000, 0, 100000);
+	check_set_gyr_rate(emul, ms, 100001, 0, 100000);
+	check_set_gyr_rate(emul, ms, 199999, 0, 100000);
+	check_set_gyr_rate(emul, ms, 200000, 0, 200000);
+	check_set_gyr_rate(emul, ms, 200001, 0, 200000);
+	check_set_gyr_rate(emul, ms, 399999, 0, 200000);
+	/*
+	 * We cannot test frequencies from 400000 to 3200000 because
+	 * CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ is set to 250000
+	 */
+
+	/* Test setting rate with rounding up */
+	check_set_gyr_rate(emul, ms, 12501, 1, 25000);
+	check_set_gyr_rate(emul, ms, 24999, 1, 25000);
+	check_set_gyr_rate(emul, ms, 25000, 1, 25000);
+	check_set_gyr_rate(emul, ms, 25001, 1, 50000);
+	check_set_gyr_rate(emul, ms, 49999, 1, 50000);
+	check_set_gyr_rate(emul, ms, 50000, 1, 50000);
+	check_set_gyr_rate(emul, ms, 50001, 1, 100000);
+	check_set_gyr_rate(emul, ms, 99999, 1, 100000);
+	check_set_gyr_rate(emul, ms, 100000, 1, 100000);
+	check_set_gyr_rate(emul, ms, 100001, 1, 200000);
+	check_set_gyr_rate(emul, ms, 199999, 1, 200000);
+	check_set_gyr_rate(emul, ms, 200000, 1, 200000);
+
+	/* Test out of range rate with rounding down */
+	zassert_equal(EC_RES_INVALID_PARAM, ms->drv->set_data_rate(ms, 1, 0),
+		      NULL);
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      ms->drv->set_data_rate(ms, 24999, 0), NULL);
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      ms->drv->set_data_rate(ms, 400000, 0), NULL);
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      ms->drv->set_data_rate(ms, 4000000, 0), NULL);
+
+	/* Test out of range rate with rounding up */
+	zassert_equal(EC_RES_INVALID_PARAM, ms->drv->set_data_rate(ms, 1, 1),
+		      NULL);
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      ms->drv->set_data_rate(ms, 12499, 1), NULL);
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      ms->drv->set_data_rate(ms, 200001, 1), NULL);
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      ms->drv->set_data_rate(ms, 400000, 1), NULL);
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      ms->drv->set_data_rate(ms, 4000000, 1), NULL);
+
+	/* Current rate shouldn't be changed on error */
+	drv_rate = ms->drv->get_data_rate(ms);
+	reg_rate = bmi_emul_get_reg(emul, BMI160_GYR_CONF);
+
+	/* Setup emulator fail on read */
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_GYR_CONF);
+
+	/* Test fail on read */
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 50000, 0),
+		      NULL);
+	zassert_equal(drv_rate, ms->drv->get_data_rate(ms));
+	zassert_equal(reg_rate, bmi_emul_get_reg(emul, BMI160_GYR_CONF));
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 50000, 1),
+		      NULL);
+	zassert_equal(drv_rate, ms->drv->get_data_rate(ms));
+	zassert_equal(reg_rate, bmi_emul_get_reg(emul, BMI160_GYR_CONF));
+
+	/* Do not fail on read */
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Setup emulator fail on write */
+	i2c_common_emul_set_write_fail_reg(common_data, BMI160_GYR_CONF);
+
+	/* Test fail on write */
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 50000, 0),
+		      NULL);
+	zassert_equal(drv_rate, ms->drv->get_data_rate(ms));
+	zassert_equal(reg_rate, bmi_emul_get_reg(emul, BMI160_GYR_CONF));
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 50000, 1),
+		      NULL);
+	zassert_equal(drv_rate, ms->drv->get_data_rate(ms));
+	zassert_equal(reg_rate, bmi_emul_get_reg(emul, BMI160_GYR_CONF));
+
+	/* Do not fail on write */
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test disabling sensor */
+	pmu_status = BMI160_PMU_NORMAL << BMI160_PMU_ACC_OFFSET;
+	pmu_status |= BMI160_PMU_NORMAL << BMI160_PMU_GYR_OFFSET;
+	bmi_emul_set_reg(emul, BMI160_PMU_STATUS, pmu_status);
+	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, 0, 0));
+
+	bmi_read8(ms->port, ms->i2c_spi_addr_flags, BMI160_PMU_STATUS,
+		  &pmu_status);
+	zassert_equal(BMI160_PMU_NORMAL << BMI160_PMU_ACC_OFFSET, pmu_status,
+		      "Accelerometer should be still enabled");
+
+	/* Test enabling sensor */
+	bmi_emul_set_reg(emul, BMI160_PMU_STATUS, 0);
+	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, 50000, 0));
+
+	bmi_read8(ms->port, ms->i2c_spi_addr_flags, BMI160_PMU_STATUS,
+		  &pmu_status);
+	zassert_equal(BMI160_PMU_NORMAL << BMI160_PMU_GYR_OFFSET, pmu_status,
+		      "Gyroscope should be enabled");
+}
+
+/**
+ * Test setting and getting scale in accelerometer and gyroscope sensors.
+ * Correct appling scale to results is checked in "read" test.
+ */
+ZTEST_USER(bmi160, test_bmi_scale)
+{
+	struct motion_sensor_t *ms;
+	int16_t ret_scale[3];
+	int16_t exp_scale[3] = { 100, 231, 421 };
+	int16_t t;
+
+	/* Test accelerometer */
+	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
+
+	zassert_equal(EC_SUCCESS, ms->drv->set_scale(ms, exp_scale, 0));
+	zassert_equal(EC_SUCCESS, ms->drv->get_scale(ms, ret_scale, &t));
+
+	zassert_equal(t, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP);
+	zassert_equal(exp_scale[0], ret_scale[0]);
+	zassert_equal(exp_scale[1], ret_scale[1]);
+	zassert_equal(exp_scale[2], ret_scale[2]);
+
+	/* Test gyroscope */
+	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
+
+	zassert_equal(EC_SUCCESS, ms->drv->set_scale(ms, exp_scale, 0));
+	zassert_equal(EC_SUCCESS, ms->drv->get_scale(ms, ret_scale, &t));
+
+	zassert_equal(t, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP);
+	zassert_equal(exp_scale[0], ret_scale[0]);
+	zassert_equal(exp_scale[1], ret_scale[1]);
+	zassert_equal(exp_scale[2], ret_scale[2]);
+}
+
+/** Test reading temperature using accelerometer and gyroscope sensors */
+ZTEST_USER(bmi160, test_bmi_read_temp)
+{
+	struct motion_sensor_t *ms_acc, *ms_gyr;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bmi_get_i2c_common_data(emul);
+	int ret_temp;
+	int exp_temp;
+
+	ms_acc = &motion_sensors[BMI_ACC_SENSOR_ID];
+	ms_gyr = &motion_sensors[BMI_GYR_SENSOR_ID];
+
+	/* Setup emulator fail on read */
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_TEMPERATURE_0);
+	zassert_equal(EC_ERROR_NOT_POWERED,
+		      ms_acc->drv->read_temp(ms_acc, &ret_temp), NULL);
+	zassert_equal(EC_ERROR_NOT_POWERED,
+		      ms_gyr->drv->read_temp(ms_gyr, &ret_temp), NULL);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_TEMPERATURE_1);
+	zassert_equal(EC_ERROR_NOT_POWERED,
+		      ms_acc->drv->read_temp(ms_acc, &ret_temp), NULL);
+	zassert_equal(EC_ERROR_NOT_POWERED,
+		      ms_gyr->drv->read_temp(ms_gyr, &ret_temp), NULL);
+	/* Do not fail on read */
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Fail on invalid temperature */
+	bmi_emul_set_reg(emul, BMI160_TEMPERATURE_0, 0x00);
+	bmi_emul_set_reg(emul, BMI160_TEMPERATURE_1, 0x80);
+	zassert_equal(EC_ERROR_NOT_POWERED,
+		      ms_acc->drv->read_temp(ms_acc, &ret_temp), NULL);
+	zassert_equal(EC_ERROR_NOT_POWERED,
+		      ms_gyr->drv->read_temp(ms_gyr, &ret_temp), NULL);
+
+	/*
+	 * Test correct values. Both motion sensors should return the same
+	 * temperature.
+	 */
+	exp_temp = C_TO_K(23);
+	bmi_emul_set_reg(emul, BMI160_TEMPERATURE_0, 0x00);
+	bmi_emul_set_reg(emul, BMI160_TEMPERATURE_1, 0x00);
+	zassert_equal(EC_SUCCESS, ms_acc->drv->read_temp(ms_acc, &ret_temp),
+		      NULL);
+	zassert_equal(exp_temp, ret_temp);
+	zassert_equal(EC_SUCCESS, ms_gyr->drv->read_temp(ms_gyr, &ret_temp),
+		      NULL);
+	zassert_equal(exp_temp, ret_temp);
+
+	exp_temp = C_TO_K(87);
+	bmi_emul_set_reg(emul, BMI160_TEMPERATURE_0, 0xff);
+	bmi_emul_set_reg(emul, BMI160_TEMPERATURE_1, 0x7f);
+	zassert_equal(EC_SUCCESS, ms_acc->drv->read_temp(ms_acc, &ret_temp),
+		      NULL);
+	zassert_equal(exp_temp, ret_temp);
+	zassert_equal(EC_SUCCESS, ms_gyr->drv->read_temp(ms_gyr, &ret_temp),
+		      NULL);
+	zassert_equal(exp_temp, ret_temp);
+
+	exp_temp = C_TO_K(-41);
+	bmi_emul_set_reg(emul, BMI160_TEMPERATURE_0, 0x01);
+	bmi_emul_set_reg(emul, BMI160_TEMPERATURE_1, 0x80);
+	zassert_equal(EC_SUCCESS, ms_acc->drv->read_temp(ms_acc, &ret_temp),
+		      NULL);
+	zassert_equal(exp_temp, ret_temp);
+	zassert_equal(EC_SUCCESS, ms_gyr->drv->read_temp(ms_gyr, &ret_temp),
+		      NULL);
+	zassert_equal(exp_temp, ret_temp);
+
+	exp_temp = C_TO_K(47);
+	bmi_emul_set_reg(emul, BMI160_TEMPERATURE_0, 0x00);
+	bmi_emul_set_reg(emul, BMI160_TEMPERATURE_1, 0x30);
+	zassert_equal(EC_SUCCESS, ms_acc->drv->read_temp(ms_acc, &ret_temp),
+		      NULL);
+	zassert_equal(exp_temp, ret_temp);
+	zassert_equal(EC_SUCCESS, ms_gyr->drv->read_temp(ms_gyr, &ret_temp),
+		      NULL);
+	zassert_equal(exp_temp, ret_temp);
+}
+
+/** Test reading accelerometer sensor data */
+ZTEST_USER(bmi160, test_bmi_acc_read)
+{
+	struct motion_sensor_t *ms;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bmi_get_i2c_common_data(emul);
+	intv3_t ret_v;
+	intv3_t exp_v;
+	int16_t scale[3] = { MOTION_SENSE_DEFAULT_SCALE,
+			     MOTION_SENSE_DEFAULT_SCALE,
+			     MOTION_SENSE_DEFAULT_SCALE };
+
+	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
+
+	/* Set offset 0 to simplify test */
+	bmi_emul_set_off(emul, BMI_EMUL_ACC_X, 0);
+	bmi_emul_set_off(emul, BMI_EMUL_ACC_Y, 0);
+	bmi_emul_set_off(emul, BMI_EMUL_ACC_Z, 0);
+
+	/* Fail on read status */
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_STATUS);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v));
+
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* When not ready, driver should return saved raw value */
+	exp_v[0] = 100;
+	exp_v[1] = 200;
+	exp_v[2] = 300;
+	ms->raw_xyz[0] = exp_v[0];
+	ms->raw_xyz[1] = exp_v[1];
+	ms->raw_xyz[2] = exp_v[2];
+
+	/* Status not ready */
+	bmi_emul_set_reg(emul, BMI160_STATUS, 0);
+	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v));
+	compare_int3v(exp_v, ret_v);
+
+	/* Status only GYR ready */
+	bmi_emul_set_reg(emul, BMI160_STATUS, BMI160_DRDY_GYR);
+	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v));
+	compare_int3v(exp_v, ret_v);
+
+	/* Status ACC ready */
+	bmi_emul_set_reg(emul, BMI160_STATUS, BMI160_DRDY_ACC);
+
+	/* Set input accelerometer values */
+	exp_v[0] = BMI_EMUL_1G / 10;
+	exp_v[1] = BMI_EMUL_1G / 20;
+	exp_v[2] = -(int)BMI_EMUL_1G / 30;
+	set_emul_acc(emul, exp_v);
+	/* Disable rotation */
+	ms->rot_standard_ref = NULL;
+	/* Set scale */
+	zassert_equal(EC_SUCCESS, ms->drv->set_scale(ms, scale, 0));
+	/* Set range to 2G */
+	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, 2, 0));
+
+	/* Test read without rotation */
+	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v));
+	drv_acc_to_emul(ret_v, 2, ret_v);
+	compare_int3v(exp_v, ret_v);
+
+	/* Set range to 4G */
+	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, 4, 0));
+
+	/* Test read without rotation */
+	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v));
+	drv_acc_to_emul(ret_v, 4, ret_v);
+	compare_int3v(exp_v, ret_v);
+
+	/* Setup rotation and rotate expected vector */
+	ms->rot_standard_ref = &test_rotation;
+	rotate_int3v_by_test_rotation(exp_v);
+	/* Set range to 2G */
+	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, 2, 0));
+
+	/* Test read with rotation */
+	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v));
+	drv_acc_to_emul(ret_v, 2, ret_v);
+	compare_int3v(exp_v, ret_v);
+
+	/* Set range to 4G */
+	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, 4, 0));
+
+	/* Test read with rotation */
+	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v));
+	drv_acc_to_emul(ret_v, 4, ret_v);
+	compare_int3v(exp_v, ret_v);
+
+	/* Fail on read of data registers */
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_ACC_X_L_G);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v));
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_ACC_X_H_G);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v));
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_ACC_Y_L_G);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v));
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_ACC_Y_H_G);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v));
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_ACC_Z_L_G);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v));
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_ACC_Z_H_G);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v));
+
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	ms->rot_standard_ref = NULL;
+}
+
+/** Test reading gyroscope sensor data */
+ZTEST_USER(bmi160, test_bmi_gyr_read)
+{
+	struct motion_sensor_t *ms;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bmi_get_i2c_common_data(emul);
+	intv3_t ret_v;
+	intv3_t exp_v;
+	int16_t scale[3] = { MOTION_SENSE_DEFAULT_SCALE,
+			     MOTION_SENSE_DEFAULT_SCALE,
+			     MOTION_SENSE_DEFAULT_SCALE };
+
+	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
+
+	/* Set offset 0 to simplify test */
+	bmi_emul_set_off(emul, BMI_EMUL_GYR_X, 0);
+	bmi_emul_set_off(emul, BMI_EMUL_GYR_Y, 0);
+	bmi_emul_set_off(emul, BMI_EMUL_GYR_Z, 0);
+
+	/* Fail on read status */
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_STATUS);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v));
+
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* When not ready, driver should return saved raw value */
+	exp_v[0] = 100;
+	exp_v[1] = 200;
+	exp_v[2] = 300;
+	ms->raw_xyz[0] = exp_v[0];
+	ms->raw_xyz[1] = exp_v[1];
+	ms->raw_xyz[2] = exp_v[2];
+
+	/* Status not ready */
+	bmi_emul_set_reg(emul, BMI160_STATUS, 0);
+	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v));
+	compare_int3v(exp_v, ret_v);
+
+	/* Status only ACC ready */
+	bmi_emul_set_reg(emul, BMI160_STATUS, BMI160_DRDY_ACC);
+	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v));
+	compare_int3v(exp_v, ret_v);
+
+	/* Status GYR ready */
+	bmi_emul_set_reg(emul, BMI160_STATUS, BMI160_DRDY_GYR);
+
+	/* Set input accelerometer values */
+	exp_v[0] = BMI_EMUL_125_DEG_S / 10;
+	exp_v[1] = BMI_EMUL_125_DEG_S / 20;
+	exp_v[2] = -(int)BMI_EMUL_125_DEG_S / 30;
+	set_emul_gyr(emul, exp_v);
+	/* Disable rotation */
+	ms->rot_standard_ref = NULL;
+	/* Set scale */
+	zassert_equal(EC_SUCCESS, ms->drv->set_scale(ms, scale, 0));
+	/* Set range to 125°/s */
+	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, 125, 0));
+
+	/* Test read without rotation */
+	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v));
+	drv_gyr_to_emul(ret_v, 125, ret_v);
+	compare_int3v(exp_v, ret_v);
+
+	/* Set range to 1000°/s */
+	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, 1000, 0));
+
+	/* Test read without rotation */
+	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v));
+	drv_gyr_to_emul(ret_v, 1000, ret_v);
+	compare_int3v(exp_v, ret_v);
+
+	/* Setup rotation and rotate expected vector */
+	ms->rot_standard_ref = &test_rotation;
+	rotate_int3v_by_test_rotation(exp_v);
+	/* Set range to 125°/s */
+	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, 125, 0));
+
+	/* Test read with rotation */
+	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v));
+	drv_gyr_to_emul(ret_v, 125, ret_v);
+	compare_int3v(exp_v, ret_v);
+
+	/* Set range to 1000°/s */
+	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, 1000, 0));
+
+	/* Test read with rotation */
+	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v));
+	drv_gyr_to_emul(ret_v, 1000, ret_v);
+	compare_int3v(exp_v, ret_v);
+
+	/* Fail on read of data registers */
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_GYR_X_L_G);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v));
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_GYR_X_H_G);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v));
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_GYR_Y_L_G);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v));
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_GYR_Y_H_G);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v));
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_GYR_Z_L_G);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v));
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_GYR_Z_H_G);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v));
+
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	ms->rot_standard_ref = NULL;
+}
+
+/**
+ * Custom emulatro read function which always return not ready STATUS register.
+ * Used in calibration test.
+ */
+static int emul_nrdy(const struct emul *emul, int reg, uint8_t *val, int byte,
+		     void *data)
+{
+	if (reg == BMI160_STATUS) {
+		bmi_emul_set_reg(emul, BMI160_STATUS, 0);
+		*val = 0;
+
+		return 0;
+	}
+
+	return 1;
+}
+
+/** Test acceleromtere calibration */
+ZTEST_USER(bmi160, test_bmi_acc_perform_calib)
+{
+	struct motion_sensor_t *ms;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bmi_get_i2c_common_data(emul);
+	uint8_t pmu_status;
+	intv3_t start_off;
+	intv3_t exp_off;
+	intv3_t ret_off;
+	int range;
+	int rate;
+	mat33_fp_t rot = { { FLOAT_TO_FP(1), 0, 0 },
+			   { 0, FLOAT_TO_FP(1), 0 },
+			   { 0, 0, FLOAT_TO_FP(-1) } };
+
+	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
+
+	/* Enable sensors */
+	pmu_status = BMI160_PMU_NORMAL << BMI160_PMU_ACC_OFFSET;
+	pmu_status |= BMI160_PMU_NORMAL << BMI160_PMU_GYR_OFFSET;
+	bmi_emul_set_reg(emul, BMI160_PMU_STATUS, pmu_status);
+
+	/* Range and rate cannot change after calibration */
+	range = 4;
+	rate = 50000;
+	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, range, 0));
+	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, rate, 0));
+
+	/* Set offset 0 */
+	start_off[0] = 0;
+	start_off[1] = 0;
+	start_off[2] = 0;
+	set_emul_acc_offset(emul, start_off);
+
+	/* Set input accelerometer values */
+	exp_off[0] = BMI_EMUL_1G / 10;
+	exp_off[1] = BMI_EMUL_1G / 20;
+	exp_off[2] = BMI_EMUL_1G - (int)BMI_EMUL_1G / 30;
+	set_emul_acc(emul, exp_off);
+
+	/*
+	 * Expected offset is [-X, -Y, 1G - Z] for no rotation or positive
+	 * rotation on Z axis
+	 */
+	exp_off[0] = -exp_off[0];
+	exp_off[1] = -exp_off[1];
+	exp_off[2] = BMI_EMUL_1G - exp_off[2];
+
+	/* Test fail on rate set */
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_ACC_CONF);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->perform_calib(ms, 1));
+	zassert_equal(range, ms->current_range);
+	zassert_equal(rate, ms->drv->get_data_rate(ms));
+
+	/* Test fail on status read */
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_STATUS);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->perform_calib(ms, 1));
+	zassert_equal(range, ms->current_range);
+	zassert_equal(rate, ms->drv->get_data_rate(ms));
+	/* Stop fast offset compensation before next test */
+	bmi_emul_set_reg(emul, BMI160_CMD_REG, BMI160_CMD_NOOP);
+
+	/* Test fail on data not ready */
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_func(common_data, emul_nrdy, NULL);
+	zassert_equal(EC_RES_TIMEOUT, ms->drv->perform_calib(ms, 1));
+	zassert_equal(range, ms->current_range);
+	zassert_equal(rate, ms->drv->get_data_rate(ms));
+	/* Remove custom emulator read function */
+	i2c_common_emul_set_read_func(common_data, NULL, NULL);
+	/* Stop fast offset compensation before next test */
+	bmi_emul_set_reg(emul, BMI160_CMD_REG, BMI160_CMD_NOOP);
+
+	/* Disable rotation */
+	ms->rot_standard_ref = NULL;
+	/* Test successful offset compenastion without rotation */
+	zassert_equal(EC_SUCCESS, ms->drv->perform_calib(ms, 1));
+	zassert_equal(range, ms->current_range);
+	zassert_equal(rate, ms->drv->get_data_rate(ms));
+	get_emul_acc_offset(emul, ret_off);
+	/*
+	 * Depending on used range, accelerometer values may be up to 6 bits
+	 * more accurate then offset value resolution.
+	 */
+	compare_int3v_eps(exp_off, ret_off, 64);
+	/* Acelerometer offset should be enabled */
+	zassert_true(bmi_emul_get_reg(emul, BMI160_OFFSET_EN_GYR98) &
+			     BMI160_OFFSET_ACC_EN,
+		     NULL);
+
+	/* Enable rotation with negative value on Z axis */
+	ms->rot_standard_ref = &rot;
+	/* Expected offset -1G - accelerometer[Z] */
+	bmi_emul_set_value(emul, BMI_EMUL_ACC_Z, -(int)BMI_EMUL_1G - 1234);
+	exp_off[2] = 1234;
+
+	/* Test successful offset compenastion with negative Z rotation */
+	zassert_equal(EC_SUCCESS, ms->drv->perform_calib(ms, 1));
+	zassert_equal(range, ms->current_range);
+	zassert_equal(rate, ms->drv->get_data_rate(ms));
+	get_emul_acc_offset(emul, ret_off);
+	compare_int3v_eps(exp_off, ret_off, 64);
+	/* Acelerometer offset should be enabled */
+	zassert_true(bmi_emul_get_reg(emul, BMI160_OFFSET_EN_GYR98) &
+			     BMI160_OFFSET_ACC_EN,
+		     NULL);
+
+	/* Set positive rotation on Z axis */
+	rot[2][2] = FLOAT_TO_FP(1);
+	/* Expected offset 1G - accelerometer[Z] */
+	bmi_emul_set_value(emul, BMI_EMUL_ACC_Z, BMI_EMUL_1G - 1234);
+	exp_off[2] = 1234;
+
+	/* Test successful offset compenastion with positive Z rotation */
+	zassert_equal(EC_SUCCESS, ms->drv->perform_calib(ms, 1));
+	zassert_equal(range, ms->current_range);
+	zassert_equal(rate, ms->drv->get_data_rate(ms));
+	get_emul_acc_offset(emul, ret_off);
+	compare_int3v_eps(exp_off, ret_off, 64);
+	/* Acelerometer offset should be enabled */
+	zassert_true(bmi_emul_get_reg(emul, BMI160_OFFSET_EN_GYR98) &
+			     BMI160_OFFSET_ACC_EN,
+		     NULL);
+	/* Disable rotation */
+	ms->rot_standard_ref = NULL;
+}
+
+/** Test gyroscope calibration */
+ZTEST_USER(bmi160, test_bmi_gyr_perform_calib)
+{
+	struct motion_sensor_t *ms;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bmi_get_i2c_common_data(emul);
+	uint8_t pmu_status;
+	intv3_t start_off;
+	intv3_t exp_off;
+	intv3_t ret_off;
+	int range;
+	int rate;
+
+	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
+
+	/* Enable sensors */
+	pmu_status = BMI160_PMU_NORMAL << BMI160_PMU_ACC_OFFSET;
+	pmu_status |= BMI160_PMU_NORMAL << BMI160_PMU_GYR_OFFSET;
+	bmi_emul_set_reg(emul, BMI160_PMU_STATUS, pmu_status);
+
+	/* Range and rate cannot change after calibration */
+	range = 250;
+	rate = 50000;
+	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, range, 0));
+	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, rate, 0));
+
+	/* Set offset 0 */
+	start_off[0] = 0;
+	start_off[1] = 0;
+	start_off[2] = 0;
+	set_emul_gyr_offset(emul, start_off);
+
+	/* Set input accelerometer values */
+	exp_off[0] = BMI_EMUL_125_DEG_S / 100;
+	exp_off[1] = BMI_EMUL_125_DEG_S / 200;
+	exp_off[2] = -(int)BMI_EMUL_125_DEG_S / 300;
+	set_emul_gyr(emul, exp_off);
+
+	/* Expected offset is [-X, -Y, -Z] */
+	exp_off[0] = -exp_off[0];
+	exp_off[1] = -exp_off[1];
+	exp_off[2] = -exp_off[2];
+
+	/* Test success on disabling calibration */
+	zassert_equal(EC_SUCCESS, ms->drv->perform_calib(ms, 0));
+	zassert_equal(range, ms->current_range);
+	zassert_equal(rate, ms->drv->get_data_rate(ms));
+
+	/* Test fail on rate set */
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_GYR_CONF);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->perform_calib(ms, 1));
+	zassert_equal(range, ms->current_range);
+	zassert_equal(rate, ms->drv->get_data_rate(ms));
+
+	/* Test fail on status read */
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_STATUS);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->perform_calib(ms, 1));
+	zassert_equal(range, ms->current_range);
+	zassert_equal(rate, ms->drv->get_data_rate(ms));
+	/* Stop fast offset compensation before next test */
+	bmi_emul_set_reg(emul, BMI160_CMD_REG, BMI160_CMD_NOOP);
+
+	/* Test fail on data not ready */
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_func(common_data, emul_nrdy, NULL);
+	zassert_equal(EC_RES_TIMEOUT, ms->drv->perform_calib(ms, 1));
+	zassert_equal(range, ms->current_range);
+	zassert_equal(rate, ms->drv->get_data_rate(ms));
+	/* Remove custom emulator read function */
+	i2c_common_emul_set_read_func(common_data, NULL, NULL);
+	/* Stop fast offset compensation before next test */
+	bmi_emul_set_reg(emul, BMI160_CMD_REG, BMI160_CMD_NOOP);
+
+	/* Test successful offset compenastion */
+	zassert_equal(EC_SUCCESS, ms->drv->perform_calib(ms, 1));
+	zassert_equal(range, ms->current_range);
+	zassert_equal(rate, ms->drv->get_data_rate(ms));
+	get_emul_gyr_offset(emul, ret_off);
+	/*
+	 * Depending on used range, gyroscope values may be up to 4 bits
+	 * more accurate then offset value resolution.
+	 */
+	compare_int3v_eps(exp_off, ret_off, 32);
+	/* Gyroscope offset should be enabled */
+	zassert_true(bmi_emul_get_reg(emul, BMI160_OFFSET_EN_GYR98) &
+			     BMI160_OFFSET_GYRO_EN,
+		     NULL);
+}
+
+/** Test init function of BMI160 accelerometer and gyroscope sensors */
+ZTEST_USER(bmi160, test_bmi_init)
+{
+	struct motion_sensor_t *ms_acc, *ms_gyr;
+
+	ms_acc = &motion_sensors[BMI_ACC_SENSOR_ID];
+	ms_gyr = &motion_sensors[BMI_GYR_SENSOR_ID];
+
+	/* Test successful init */
+	zassert_equal(EC_RES_SUCCESS, ms_acc->drv->init(ms_acc));
+
+	zassert_equal(EC_RES_SUCCESS, ms_gyr->drv->init(ms_gyr));
+}
+
+/** Data for custom emulator read function used in FIFO test */
+struct fifo_func_data {
+	uint16_t interrupts;
+};
+
+/**
+ * Custom emulator read function used in FIFO test. It sets interrupt registers
+ * to value passed as additional data. It sets interrupt registers to 0 after
+ * access.
+ */
+static int emul_fifo_func(const struct emul *emul, int reg, uint8_t *val,
+			  int byte, void *data)
+{
+	struct fifo_func_data *d = data;
+
+	if (reg + byte == BMI160_INT_STATUS_0) {
+		bmi_emul_set_reg(emul, BMI160_INT_STATUS_0,
+				 d->interrupts & 0xff);
+		d->interrupts &= 0xff00;
+	} else if (reg + byte == BMI160_INT_STATUS_1) {
+		bmi_emul_set_reg(emul, BMI160_INT_STATUS_1,
+				 (d->interrupts >> 8) & 0xff);
+		d->interrupts &= 0xff;
+	}
+
+	return 1;
+}
+
+/**
+ * Run irq handler on accelerometer sensor and check if committed data in FIFO
+ * match what was set in FIFO frames in emulator.
+ */
+static void check_fifo_f(struct motion_sensor_t *ms_acc,
+			 struct motion_sensor_t *ms_gyr,
+			 struct bmi_emul_frame *frame, int acc_range,
+			 int gyr_range, int line)
+{
+	struct ec_response_motion_sensor_data vector;
+	struct bmi_emul_frame *f_acc, *f_gyr;
+	uint32_t event = BMI_INT_EVENT;
+	uint16_t size;
+	intv3_t exp_v;
+	intv3_t ret_v;
+
+	/* Find first frame of acc and gyr type */
+	f_acc = frame;
+	while (f_acc != NULL && !(f_acc->type & BMI_EMUL_FRAME_ACC)) {
+		f_acc = f_acc->next;
+	}
+
+	f_gyr = frame;
+	while (f_gyr != NULL && !(f_gyr->type & BMI_EMUL_FRAME_GYR)) {
+		f_gyr = f_gyr->next;
+	}
+
+	/* Read FIFO in driver */
+	zassert_equal(EC_SUCCESS, ms_acc->drv->irq_handler(ms_acc, &event),
+		      "Failed to read FIFO in irq handler, line %d", line);
+
+	/* Read all data committed to FIFO */
+	while (motion_sense_fifo_read(sizeof(vector), 1, &vector, &size)) {
+		/* Ignore timestamp frames */
+		if (vector.flags == MOTIONSENSE_SENSOR_FLAG_TIMESTAMP) {
+			continue;
+		}
+
+		/* Check acclerometer frames */
+		if (ms_acc - motion_sensors == vector.sensor_num) {
+			if (f_acc == NULL) {
+				zassert_unreachable(
+					"Not expected acclerometer data in FIFO, line %d",
+					line);
+			}
+
+			convert_int3v_int16(vector.data, ret_v);
+			drv_acc_to_emul(ret_v, acc_range, ret_v);
+			exp_v[0] = f_acc->acc_x;
+			exp_v[1] = f_acc->acc_y;
+			exp_v[2] = f_acc->acc_z;
+			compare_int3v_f(exp_v, ret_v, V_EPS, line);
+			f_acc = f_acc->next;
+		}
+
+		/* Check gyroscope frames */
+		if (ms_gyr - motion_sensors == vector.sensor_num) {
+			if (f_gyr == NULL) {
+				zassert_unreachable(
+					"Not expected gyroscope data in FIFO, line %d",
+					line);
+			}
+
+			convert_int3v_int16(vector.data, ret_v);
+			drv_gyr_to_emul(ret_v, gyr_range, ret_v);
+			exp_v[0] = f_gyr->gyr_x;
+			exp_v[1] = f_gyr->gyr_y;
+			exp_v[2] = f_gyr->gyr_z;
+			compare_int3v_f(exp_v, ret_v, V_EPS, line);
+			f_gyr = f_gyr->next;
+		}
+	}
+
+	/* Skip frames of different type at the end */
+	while (f_acc != NULL && !(f_acc->type & BMI_EMUL_FRAME_ACC)) {
+		f_acc = f_acc->next;
+	}
+
+	while (f_gyr != NULL && !(f_gyr->type & BMI_EMUL_FRAME_GYR)) {
+		f_gyr = f_gyr->next;
+	}
+
+	/* All frames are readed */
+	zassert_is_null(f_acc, "Not all accelerometer frames are read, line %d",
+			line);
+	zassert_is_null(f_gyr, "Not all gyroscope frames are read, line %d",
+			line);
+}
+#define check_fifo(ms_acc, ms_gyr, frame, acc_range, gyr_range) \
+	check_fifo_f(ms_acc, ms_gyr, frame, acc_range, gyr_range, __LINE__)
+
+/** Test irq handler of accelerometer sensor */
+ZTEST_USER(bmi160, test_bmi_acc_fifo)
+{
+	struct motion_sensor_t *ms, *ms_gyr;
+	struct fifo_func_data func_data;
+	struct bmi_emul_frame f[3];
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bmi_get_i2c_common_data(emul);
+	int gyr_range = 125;
+	int acc_range = 2;
+	int event;
+
+	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
+	ms_gyr = &motion_sensors[BMI_GYR_SENSOR_ID];
+
+	/* init bmi before test */
+	zassert_equal(EC_RES_SUCCESS, ms->drv->init(ms));
+	zassert_equal(EC_RES_SUCCESS, ms_gyr->drv->init(ms_gyr));
+
+	/* Need to be set to collect all data in FIFO */
+	ms->oversampling_ratio = 1;
+	ms_gyr->oversampling_ratio = 1;
+	/* Only BMI event should be handled */
+	event = 0x1234 & ~BMI_INT_EVENT;
+	zassert_equal(EC_ERROR_NOT_HANDLED, ms->drv->irq_handler(ms, &event),
+		      NULL);
+
+	event = BMI_INT_EVENT;
+
+	/* Test fail to read interrupt status registers */
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_INT_STATUS_0);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->irq_handler(ms, &event));
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_INT_STATUS_1);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->irq_handler(ms, &event));
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test no interrupt */
+	bmi_emul_set_reg(emul, BMI160_INT_STATUS_0, 0);
+	bmi_emul_set_reg(emul, BMI160_INT_STATUS_1, 0);
+
+	/* Enable sensor FIFO */
+	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, 50000, 0));
+
+	/* Trigger irq handler and check results */
+	check_fifo(ms, ms_gyr, NULL, acc_range, gyr_range);
+
+	/* Set custom function for FIFO test */
+	i2c_common_emul_set_read_func(common_data, emul_fifo_func, &func_data);
+	/* Set range */
+	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, acc_range, 0));
+	zassert_equal(EC_SUCCESS, ms_gyr->drv->set_range(ms_gyr, gyr_range, 0),
+		      NULL);
+	/* Setup single accelerometer frame */
+	f[0].type = BMI_EMUL_FRAME_ACC;
+	f[0].acc_x = BMI_EMUL_1G / 10;
+	f[0].acc_y = BMI_EMUL_1G / 20;
+	f[0].acc_z = -(int)BMI_EMUL_1G / 30;
+	f[0].next = NULL;
+	bmi_emul_append_frame(emul, f);
+	/* Setup interrupts register */
+	func_data.interrupts = BMI160_FWM_INT;
+
+	/* Trigger irq handler and check results */
+	check_fifo(ms, ms_gyr, f, acc_range, gyr_range);
+
+	/* Setup second accelerometer frame */
+	f[1].type = BMI_EMUL_FRAME_ACC;
+	f[1].acc_x = -(int)BMI_EMUL_1G / 40;
+	f[1].acc_y = BMI_EMUL_1G / 50;
+	f[1].acc_z = BMI_EMUL_1G / 60;
+	f[0].next = &(f[1]);
+	f[1].next = NULL;
+	bmi_emul_append_frame(emul, f);
+	/* Setup interrupts register */
+	func_data.interrupts = BMI160_FWM_INT;
+
+	/* Trigger irq handler and check results */
+	check_fifo(ms, ms_gyr, f, acc_range, gyr_range);
+
+	/* Enable sensor FIFO */
+	zassert_equal(EC_SUCCESS, ms_gyr->drv->set_data_rate(ms_gyr, 50000, 0),
+		      NULL);
+
+	/* Setup first gyroscope frame (after two accelerometer frames) */
+	f[2].type = BMI_EMUL_FRAME_GYR;
+	f[2].gyr_x = -(int)BMI_EMUL_125_DEG_S / 100;
+	f[2].gyr_y = BMI_EMUL_125_DEG_S / 200;
+	f[2].gyr_z = BMI_EMUL_125_DEG_S / 300;
+	f[1].next = &(f[2]);
+	f[2].next = NULL;
+	bmi_emul_append_frame(emul, f);
+	/* Setup interrupts register */
+	func_data.interrupts = BMI160_FWM_INT;
+
+	/* Trigger irq handler and check results */
+	check_fifo(ms, ms_gyr, f, acc_range, gyr_range);
+
+	/* Setup second accelerometer frame to by gyroscope frame too */
+	f[1].type |= BMI_EMUL_FRAME_GYR;
+	f[1].gyr_x = -(int)BMI_EMUL_125_DEG_S / 300;
+	f[1].gyr_y = BMI_EMUL_125_DEG_S / 400;
+	f[1].gyr_z = BMI_EMUL_125_DEG_S / 500;
+	bmi_emul_append_frame(emul, f);
+	/* Setup interrupts register */
+	func_data.interrupts = BMI160_FWM_INT;
+
+	/* Trigger irq handler and check results */
+	check_fifo(ms, ms_gyr, f, acc_range, gyr_range);
+
+	/* Skip frame should be ignored by driver */
+	bmi_emul_set_skipped_frames(emul, 8);
+	bmi_emul_append_frame(emul, f);
+	/* Setup interrupts register */
+	func_data.interrupts = BMI160_FWM_INT;
+
+	/* Trigger irq handler and check results */
+	check_fifo(ms, ms_gyr, f, acc_range, gyr_range);
+
+	/* Setup second frame as an config frame */
+	f[1].type = BMI_EMUL_FRAME_CONFIG;
+	/* Indicate that accelerometer range changed */
+	f[1].config = 0x1;
+	bmi_emul_append_frame(emul, f);
+	/* Setup interrupts register */
+	func_data.interrupts = BMI160_FWM_INT;
+
+	/* Trigger irq handler and check results */
+	check_fifo(ms, ms_gyr, f, acc_range, gyr_range);
+
+	/* Remove custom emulator read function */
+	i2c_common_emul_set_read_func(common_data, NULL, NULL);
+}
+
+/** Test irq handler of gyroscope sensor */
+ZTEST_USER(bmi160, test_bmi_gyr_fifo)
+{
+	struct motion_sensor_t *ms;
+	uint32_t event;
+
+	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
+
+	/* Interrupt shuldn't be triggered for gyroscope motion sense */
+	event = BMI_INT_EVENT;
+	zassert_equal(EC_ERROR_NOT_HANDLED, ms->drv->irq_handler(ms, &event),
+		      NULL);
+}
+
+/** Test reading from compass via `bmi160_sec_raw_read8()` */
+ZTEST_USER(bmi160, test_bmi_sec_raw_read8)
+{
+	struct motion_sensor_t *ms = &motion_sensors[BMI_ACC_SENSOR_ID];
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	uint8_t expected_read_value = 0xAA;
+	uint8_t requested_reg_addr = 0x55;
+	uint8_t actual_reg_addr;
+	int actual_read_value;
+	int ret;
+
+	bmi_emul_set_reg(emul, BMI160_MAG_I2C_READ_DATA, expected_read_value);
+
+	ret = bmi160_sec_raw_read8(ms->port, ms->i2c_spi_addr_flags,
+				   requested_reg_addr, &actual_read_value);
+
+	/* Verify return value */
+	zassert_equal(ret, EC_RES_SUCCESS, "Expected return code %d but got %d",
+		      EC_RES_SUCCESS, ret);
+
+	/* Verify the correct value was read */
+	zassert_equal(expected_read_value, actual_read_value,
+		      "Read value $%02x but expected to read $%02x",
+		      actual_read_value, expected_read_value);
+
+	/* Verify the intended register address was read */
+	actual_reg_addr = bmi_emul_get_reg(emul, BMI160_MAG_I2C_READ_ADDR);
+	zassert_equal(requested_reg_addr, actual_reg_addr,
+		      "Read reg $%02x but expected to read $%02x",
+		      actual_reg_addr, requested_reg_addr);
+}
+
+/** Test writing to compass via `bmi160_sec_raw_write8()` */
+ZTEST_USER(bmi160, test_bmi_sec_raw_write8)
+{
+	struct motion_sensor_t *ms = &motion_sensors[BMI_ACC_SENSOR_ID];
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	uint8_t expected_write_value = 0xAB;
+	uint8_t requested_reg_addr = 0x56;
+	uint8_t actual_reg_addr;
+	int actual_written_value;
+	int ret;
+
+	ret = bmi160_sec_raw_write8(ms->port, ms->i2c_spi_addr_flags,
+				    requested_reg_addr, expected_write_value);
+
+	/* Verify return value */
+	zassert_equal(ret, EC_RES_SUCCESS, "Expected return code %d but got %d",
+		      EC_RES_SUCCESS, ret);
+
+	/* Verify the correct value was written */
+	actual_written_value =
+		bmi_emul_get_reg(emul, BMI160_MAG_I2C_WRITE_DATA);
+	zassert_equal(expected_write_value, actual_written_value,
+		      "Wrote value $%02x but expected to write $%02x",
+		      actual_written_value, expected_write_value);
+
+	/* Verify the intended register address was used */
+	actual_reg_addr = bmi_emul_get_reg(emul, BMI160_MAG_I2C_WRITE_ADDR);
+	zassert_equal(requested_reg_addr, actual_reg_addr,
+		      "Wrote reg $%02x but expected to write $%02x",
+		      actual_reg_addr, requested_reg_addr);
+}
+
+/** Test setting an offset on an invalid sensor type */
+ZTEST_USER(bmi160, test_bmi_set_offset_invalid_type)
+{
+	struct motion_sensor_t ms_fake;
+	int ret;
+	int16_t unused_offset = 0;
+	int16_t temp = 0;
+
+	/* make a copy of the accel motion sensor so we modify its type */
+	memcpy(&ms_fake, &motion_sensors[BMI_ACC_SENSOR_ID], sizeof(ms_fake));
+	ms_fake.type = MOTIONSENSE_TYPE_MAX;
+
+	ret = ms_fake.drv->set_offset(&ms_fake, &unused_offset, temp);
+
+	zassert_equal(ret, EC_RES_INVALID_PARAM,
+		      "Expected return code of %d but got %d",
+		      EC_RES_INVALID_PARAM, ret);
+}
+
+/** Test performing a calibration on a magnetometer, which is not supported */
+ZTEST_USER(bmi160, test_bmi_perform_calib_invalid_type)
+{
+	struct motion_sensor_t ms_fake;
+	int ret;
+
+	/* make a copy of the accel motion sensor so we modify its type */
+	memcpy(&ms_fake, &motion_sensors[BMI_ACC_SENSOR_ID], sizeof(ms_fake));
+	ms_fake.type = MOTIONSENSE_TYPE_MAG;
+
+	ret = ms_fake.drv->perform_calib(&ms_fake, 1);
+
+	zassert_equal(ret, EC_RES_INVALID_PARAM,
+		      "Expected return code of %d but got %d",
+		      EC_RES_INVALID_PARAM, ret);
+}
+
+/** Test reading the onboard temperature sensor */
+ZTEST_USER(bmi160, test_bmi_temp_sensor)
+{
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	int ret;
+
+	/* Part 1:
+	 * Set up the register so we read 300 Kelvin. 0x0000 is 23 deg C, and
+	 * each LSB is 0.5^9 deg C. See BMI160 datasheet for more details.
+	 */
+	int actual_read_temp_k, expected_temp_k = 300;
+	uint16_t temp_reg_value = (K_TO_C(expected_temp_k) - 23) << 9;
+
+	bmi_emul_set_reg(emul, BMI160_TEMPERATURE_0, temp_reg_value & 0xFF);
+	bmi_emul_set_reg(emul, BMI160_TEMPERATURE_1, temp_reg_value >> 8);
+
+	/* The output will be in Kelvin */
+	ret = bmi160_get_sensor_temp(BMI_ACC_SENSOR_ID, &actual_read_temp_k);
+
+	zassert_equal(ret, EC_RES_SUCCESS, "Expected %d but got %d",
+		      EC_RES_SUCCESS, ret);
+	zassert_equal(expected_temp_k, actual_read_temp_k,
+		      "Expected %dK but got %dK", expected_temp_k,
+		      actual_read_temp_k);
+
+	/* Part 2:
+	 * Have the chip return an invalid reading.
+	 */
+	temp_reg_value = BMI_INVALID_TEMP;
+	bmi_emul_set_reg(emul, BMI160_TEMPERATURE_0, temp_reg_value & 0xFF);
+	bmi_emul_set_reg(emul, BMI160_TEMPERATURE_1, temp_reg_value >> 8);
+
+	ret = bmi160_get_sensor_temp(BMI_ACC_SENSOR_ID, &actual_read_temp_k);
+
+	zassert_equal(ret, EC_ERROR_NOT_POWERED, "Expected %d but got %d",
+		      EC_ERROR_NOT_POWERED, ret);
+}
+
+ZTEST_USER(bmi160, test_bmi_interrupt_handler)
+{
+	/* The accelerometer interrupt handler simply sets an event flag for the
+	 * motion sensing task. Make sure that flag starts cleared, fire the
+	 * interrupt, and ensure the flag is set.
+	 */
+
+	atomic_t *mask;
+
+	mask = task_get_event_bitmap(TASK_ID_MOTIONSENSE);
+	zassert_true(mask != NULL,
+		     "Got a null pointer when getting event bitmap.");
+	zassert_true((*mask & CONFIG_ACCELGYRO_BMI160_INT_EVENT) == 0,
+		     "Event flag is set before firing interrupt");
+
+	bmi160_interrupt(0);
+
+	mask = task_get_event_bitmap(TASK_ID_MOTIONSENSE);
+	zassert_true(mask != NULL,
+		     "Got a null pointer when getting event bitmap.");
+	zassert_true(*mask & CONFIG_ACCELGYRO_BMI160_INT_EVENT,
+		     "Event flag is not set after firing interrupt");
+}
+
+/* Make an I2C emulator mock wrapped in FFF for use with test_bmi_init_chip_id()
+ */
+FAKE_VALUE_FUNC(int, bmi_init_chip_id_mock_write_fn, const struct emul *, int,
+		uint8_t, int, void *);
+
+/** Test handling of invalid or unreadable chip IDs in init() */
+ZTEST_USER(bmi160, test_bmi_init_chip_id)
+{
+	struct motion_sensor_t *ms = &motion_sensors[BMI_ACC_SENSOR_ID];
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bmi_get_i2c_common_data(emul);
+	int ret;
+
+	/* Part 1: Cannot read the Chip ID register */
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_CHIP_ID);
+	ret = ms->drv->init(ms);
+
+	zassert_equal(ret, EC_ERROR_UNKNOWN, "Expected %d but got %d",
+		      EC_ERROR_UNKNOWN, ret);
+
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Part 2: Incorrect chip ID - this triggers a series of writes in an
+	 * attempt to 'unlock' the chip.
+	 */
+
+	/* Have the mocked write function return 1 so everything is passed
+	 * through. We only care about using FFF to capture the argument
+	 * history.
+	 */
+
+	RESET_FAKE(bmi_init_chip_id_mock_write_fn);
+	bmi_init_chip_id_mock_write_fn_fake.return_val = 1;
+	i2c_common_emul_set_write_func(common_data,
+				       bmi_init_chip_id_mock_write_fn, NULL);
+
+	/* Return a phony chip ID */
+	bmi_emul_set_reg(emul, BMI160_CHIP_ID, 0xFF);
+
+	ret = ms->drv->init(ms);
+
+	/* Verify return value */
+	zassert_equal(ret, EC_ERROR_ACCESS_DENIED, "Expected %d but got %d",
+		      EC_ERROR_ACCESS_DENIED, ret);
+
+	/* Verify that all expected I2C writes were completed, in order */
+	MOCK_ASSERT_I2C_WRITE(bmi_init_chip_id_mock_write_fn, 0, BMI160_CMD_REG,
+			      BMI160_CMD_EXT_MODE_EN_B0);
+	MOCK_ASSERT_I2C_WRITE(bmi_init_chip_id_mock_write_fn, 1, BMI160_CMD_REG,
+			      BMI160_CMD_EXT_MODE_EN_B1);
+	MOCK_ASSERT_I2C_WRITE(bmi_init_chip_id_mock_write_fn, 2, BMI160_CMD_REG,
+			      BMI160_CMD_EXT_MODE_EN_B2);
+	MOCK_ASSERT_I2C_WRITE(bmi_init_chip_id_mock_write_fn, 3,
+			      BMI160_CMD_EXT_MODE_ADDR, BMI160_CMD_PAGING_EN);
+	MOCK_ASSERT_I2C_WRITE(bmi_init_chip_id_mock_write_fn, 4,
+			      BMI160_CMD_EXT_MODE_ADDR, 0);
+
+	i2c_common_emul_set_write_func(common_data, NULL, NULL);
+}
+
+static void bmi160_before(void *fixture)
+{
+	ARG_UNUSED(fixture);
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bmi_get_i2c_common_data(emul);
+	struct motion_sensor_t *acc_ms;
+	struct motion_sensor_t *gyr_ms;
+
+	acc_ms = &motion_sensors[BMI_ACC_SENSOR_ID];
+	gyr_ms = &motion_sensors[BMI_GYR_SENSOR_ID];
+
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	bmi_emul_set_reg(emul, BMI160_CHIP_ID, 0xd1);
+
+	/* Disable rotation */
+	gyr_ms->rot_standard_ref = NULL;
+	acc_ms->rot_standard_ref = NULL;
+
+	zassert_equal(EC_SUCCESS, acc_ms->drv->set_data_rate(acc_ms, 50000, 0),
+		      NULL);
+	zassert_equal(EC_SUCCESS, gyr_ms->drv->set_data_rate(gyr_ms, 50000, 0),
+		      NULL);
+}
+
+static void bmi160_after(void *state)
+{
+	ARG_UNUSED(state);
+	struct motion_sensor_t *acc_ms, *gyr_ms;
+
+	acc_ms = &motion_sensors[BMI_ACC_SENSOR_ID];
+	gyr_ms = &motion_sensors[BMI_GYR_SENSOR_ID];
+
+	acc_ms->drv->set_data_rate(acc_ms, 0, 0);
+	gyr_ms->drv->set_data_rate(gyr_ms, 0, 0);
+
+	gyr_ms->rot_standard_ref = NULL;
+	acc_ms->rot_standard_ref = NULL;
+}
+
+ZTEST_SUITE(bmi160, drivers_predicate_pre_main, NULL, bmi160_before,
+	    bmi160_after, NULL);
+
+/** Cause an interrupt and verify the motion_sense task handled it. */
+ZTEST_USER(bmi160_tasks, test_irq_handling)
+{
+	struct bmi_emul_frame f[3];
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+
+	f[0].type = BMI_EMUL_FRAME_ACC;
+	f[0].acc_x = BMI_EMUL_1G / 10;
+	f[0].acc_y = BMI_EMUL_1G / 20;
+	f[0].acc_z = -(int)BMI_EMUL_1G / 30;
+	f[0].next = NULL;
+	bmi_emul_append_frame(emul, f);
+	bmi_emul_set_reg(emul, BMI160_INT_STATUS_0, BMI160_FWM_INT & 0xff);
+	bmi_emul_set_reg(emul, BMI160_INT_STATUS_1,
+			 (BMI160_FWM_INT >> 8) & 0xff);
+
+	bmi160_interrupt(0);
+	k_sleep(K_SECONDS(10));
+
+	/* Verify that the motion_sense_task read it. */
+	zassert_equal(bmi_emul_get_reg(emul, BMI160_INT_STATUS_0), 0, NULL);
+	zassert_equal(bmi_emul_get_reg(emul, BMI160_INT_STATUS_1), 0, NULL);
+}
+
+ZTEST_SUITE(bmi160_tasks, drivers_predicate_post_main, NULL, bmi160_before,
+	    bmi160_after, NULL);
diff --git a/zephyr/test/drivers/default/src/bmi260.c b/zephyr/test/drivers/default/src/bmi260.c
new file mode 100644
index 0000000000..1bc45b3883
--- /dev/null
+++ b/zephyr/test/drivers/default/src/bmi260.c
@@ -0,0 +1,2304 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "driver/accelgyro_bmi260.h"
+#include "driver/accelgyro_bmi_common.h"
+#include "emul/emul_bmi.h"
+#include "emul/emul_common_i2c.h"
+#include "i2c.h"
+#include "motion_sense_fifo.h"
+#include "test/drivers/test_mocks.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/fff.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+#define BMI_NODE DT_NODELABEL(accel_bmi260)
+#define BMI_ACC_SENSOR_ID SENSOR_ID(DT_NODELABEL(ms_bmi260_accel))
+#define BMI_GYR_SENSOR_ID SENSOR_ID(DT_NODELABEL(ms_bmi260_gyro))
+#define BMI_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(SENSOR_ID(DT_ALIAS(bmi260_int)))
+
+/** How accurate comparision of vectors should be */
+#define V_EPS 8
+
+/** Convert from one type of vector to another */
+#define convert_int3v_int16(v, r) \
+	do {                      \
+		r[0] = v[0];      \
+		r[1] = v[1];      \
+		r[2] = v[2];      \
+	} while (0)
+
+/** Rotation used in some tests */
+static const mat33_fp_t test_rotation = { { 0, FLOAT_TO_FP(1), 0 },
+					  { FLOAT_TO_FP(-1), 0, 0 },
+					  { 0, 0, FLOAT_TO_FP(-1) } };
+/** Rotate given vector by test rotation */
+static void rotate_int3v_by_test_rotation(intv3_t v)
+{
+	int16_t t;
+
+	t = v[0];
+	v[0] = -v[1];
+	v[1] = t;
+	v[2] = -v[2];
+}
+
+/** Set emulator accelerometer offset values to intv3_t vector */
+static void set_emul_acc_offset(const struct emul *emul, intv3_t offset)
+{
+	bmi_emul_set_off(emul, BMI_EMUL_ACC_X, offset[0]);
+	bmi_emul_set_off(emul, BMI_EMUL_ACC_Y, offset[1]);
+	bmi_emul_set_off(emul, BMI_EMUL_ACC_Z, offset[2]);
+}
+
+/** Save emulator accelerometer offset values to intv3_t vector */
+static void get_emul_acc_offset(const struct emul *emul, intv3_t offset)
+{
+	offset[0] = bmi_emul_get_off(emul, BMI_EMUL_ACC_X);
+	offset[1] = bmi_emul_get_off(emul, BMI_EMUL_ACC_Y);
+	offset[2] = bmi_emul_get_off(emul, BMI_EMUL_ACC_Z);
+}
+
+/** Set emulator accelerometer values to intv3_t vector */
+static void set_emul_acc(const struct emul *emul, intv3_t acc)
+{
+	bmi_emul_set_value(emul, BMI_EMUL_ACC_X, acc[0]);
+	bmi_emul_set_value(emul, BMI_EMUL_ACC_Y, acc[1]);
+	bmi_emul_set_value(emul, BMI_EMUL_ACC_Z, acc[2]);
+}
+
+/** Set emulator gyroscope offset values to intv3_t vector */
+static void set_emul_gyr_offset(const struct emul *emul, intv3_t offset)
+{
+	bmi_emul_set_off(emul, BMI_EMUL_GYR_X, offset[0]);
+	bmi_emul_set_off(emul, BMI_EMUL_GYR_Y, offset[1]);
+	bmi_emul_set_off(emul, BMI_EMUL_GYR_Z, offset[2]);
+}
+
+/** Save emulator gyroscope offset values to intv3_t vector */
+static void get_emul_gyr_offset(const struct emul *emul, intv3_t offset)
+{
+	offset[0] = bmi_emul_get_off(emul, BMI_EMUL_GYR_X);
+	offset[1] = bmi_emul_get_off(emul, BMI_EMUL_GYR_Y);
+	offset[2] = bmi_emul_get_off(emul, BMI_EMUL_GYR_Z);
+}
+
+/** Set emulator gyroscope values to vector of three int16_t */
+static void set_emul_gyr(const struct emul *emul, intv3_t gyr)
+{
+	bmi_emul_set_value(emul, BMI_EMUL_GYR_X, gyr[0]);
+	bmi_emul_set_value(emul, BMI_EMUL_GYR_Y, gyr[1]);
+	bmi_emul_set_value(emul, BMI_EMUL_GYR_Z, gyr[2]);
+}
+
+/** Convert accelerometer read to units used by emulator */
+static void drv_acc_to_emul(intv3_t drv, int range, intv3_t out)
+{
+	const int scale = MOTION_SCALING_FACTOR / BMI_EMUL_1G;
+
+	out[0] = drv[0] * range / scale;
+	out[1] = drv[1] * range / scale;
+	out[2] = drv[2] * range / scale;
+}
+
+/** Convert gyroscope read to units used by emulator */
+static void drv_gyr_to_emul(intv3_t drv, int range, intv3_t out)
+{
+	const int scale = MOTION_SCALING_FACTOR / BMI_EMUL_125_DEG_S;
+
+	range /= 125;
+	out[0] = drv[0] * range / scale;
+	out[1] = drv[1] * range / scale;
+	out[2] = drv[2] * range / scale;
+}
+
+/** Compare two vectors of intv3_t type */
+static void compare_int3v_f(intv3_t exp_v, intv3_t v, int eps, int line)
+{
+	int i;
+
+	for (i = 0; i < 3; i++) {
+		zassert_within(
+			exp_v[i], v[i], eps,
+			"Expected [%d; %d; %d], got [%d; %d; %d]; line: %d",
+			exp_v[0], exp_v[1], exp_v[2], v[0], v[1], v[2], line);
+	}
+}
+#define compare_int3v_eps(exp_v, v, e) compare_int3v_f(exp_v, v, e, __LINE__)
+#define compare_int3v(exp_v, v) compare_int3v_eps(exp_v, v, V_EPS)
+
+/**
+ * Custom emulator read function which always return INIT OK status in
+ * INTERNAL STATUS register. Used in init test.
+ */
+static int emul_init_ok(const struct emul *emul, int reg, uint8_t *val,
+			int byte, void *data)
+{
+	bmi_emul_set_reg(emul, BMI260_INTERNAL_STATUS, BMI260_INIT_OK);
+
+	return 1;
+}
+
+/** Init BMI260 before test */
+static void bmi_init_emul(void)
+{
+	struct motion_sensor_t *ms_acc;
+	struct motion_sensor_t *ms_gyr;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data;
+	int ret;
+
+	common_data = emul_bmi_get_i2c_common_data(emul);
+	ms_acc = &motion_sensors[BMI_ACC_SENSOR_ID];
+	ms_gyr = &motion_sensors[BMI_GYR_SENSOR_ID];
+
+	/*
+	 * Init BMI before test. It is needed custom function to set value of
+	 * BMI260_INTERNAL_STATUS register, because init function triggers reset
+	 * which clears value set in this register before test.
+	 */
+	i2c_common_emul_set_read_func(common_data, emul_init_ok, NULL);
+
+	ret = ms_acc->drv->init(ms_acc);
+	zassert_equal(EC_RES_SUCCESS, ret, "Got accel init error %d", ret);
+
+	ret = ms_gyr->drv->init(ms_gyr);
+	zassert_equal(EC_RES_SUCCESS, ret, "Got gyro init error %d", ret);
+
+	/* Remove custom emulator read function */
+	i2c_common_emul_set_read_func(common_data, NULL, NULL);
+}
+
+/** Test get accelerometer offset with and without rotation */
+ZTEST_USER(bmi260, test_bmi_acc_get_offset)
+{
+	struct motion_sensor_t *ms;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data;
+	int16_t ret[3];
+	intv3_t ret_v;
+	intv3_t exp_v;
+	int16_t temp;
+
+	common_data = emul_bmi_get_i2c_common_data(emul);
+	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
+
+	/* Set emulator offset */
+	exp_v[0] = BMI_EMUL_1G / 10;
+	exp_v[1] = BMI_EMUL_1G / 20;
+	exp_v[2] = -(int)BMI_EMUL_1G / 30;
+	set_emul_acc_offset(emul, exp_v);
+	/* BMI driver returns value in mg units */
+	exp_v[0] = 1000 / 10;
+	exp_v[1] = 1000 / 20;
+	exp_v[2] = -1000 / 30;
+
+	/* Test fail on offset read */
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_OFFSET_ACC70);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->get_offset(ms, ret, &temp),
+		      NULL);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_OFFSET_ACC70 + 1);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->get_offset(ms, ret, &temp),
+		      NULL);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_OFFSET_ACC70 + 2);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->get_offset(ms, ret, &temp),
+		      NULL);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Disable rotation */
+	ms->rot_standard_ref = NULL;
+
+	/* Test get offset without rotation */
+	zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp));
+	zassert_equal(temp, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP);
+	convert_int3v_int16(ret, ret_v);
+	compare_int3v(exp_v, ret_v);
+
+	/* Setup rotation and rotate expected offset */
+	ms->rot_standard_ref = &test_rotation;
+	rotate_int3v_by_test_rotation(exp_v);
+
+	/* Test get offset with rotation */
+	zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp));
+	zassert_equal(temp, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP);
+	convert_int3v_int16(ret, ret_v);
+	compare_int3v(exp_v, ret_v);
+}
+
+/** Test get gyroscope offset with and without rotation */
+ZTEST_USER(bmi260, test_bmi_gyr_get_offset)
+{
+	struct motion_sensor_t *ms;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data;
+	int16_t ret[3];
+	intv3_t ret_v;
+	intv3_t exp_v;
+	int16_t temp;
+
+	common_data = emul_bmi_get_i2c_common_data(emul);
+	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
+
+	/* Do not fail on read */
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Set emulator offset */
+	exp_v[0] = BMI_EMUL_125_DEG_S / 100;
+	exp_v[1] = BMI_EMUL_125_DEG_S / 200;
+	exp_v[2] = -(int)BMI_EMUL_125_DEG_S / 300;
+	set_emul_gyr_offset(emul, exp_v);
+	/* BMI driver returns value in mdeg/s units */
+	exp_v[0] = 125000 / 100;
+	exp_v[1] = 125000 / 200;
+	exp_v[2] = -125000 / 300;
+
+	/* Test fail on offset read */
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_OFFSET_GYR70);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->get_offset(ms, ret, &temp),
+		      NULL);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_OFFSET_GYR70 + 1);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->get_offset(ms, ret, &temp),
+		      NULL);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_OFFSET_GYR70 + 2);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->get_offset(ms, ret, &temp),
+		      NULL);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_OFFSET_EN_GYR98);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->get_offset(ms, ret, &temp),
+		      NULL);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Disable rotation */
+	ms->rot_standard_ref = NULL;
+
+	/* Test get offset without rotation */
+	zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp));
+	zassert_equal(temp, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP);
+	convert_int3v_int16(ret, ret_v);
+	compare_int3v_eps(exp_v, ret_v, 64);
+
+	/* Setup rotation and rotate expected offset */
+	ms->rot_standard_ref = &test_rotation;
+	rotate_int3v_by_test_rotation(exp_v);
+
+	/* Test get offset with rotation */
+	zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp));
+	zassert_equal(temp, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP);
+	convert_int3v_int16(ret, ret_v);
+	compare_int3v_eps(exp_v, ret_v, 64);
+}
+
+/**
+ * Test set accelerometer offset with and without rotation. Also test behaviour
+ * on I2C error.
+ */
+ZTEST_USER(bmi260, test_bmi_acc_set_offset)
+{
+	struct motion_sensor_t *ms;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data;
+	int16_t input_v[3] = { 0, 0, 0 };
+	int16_t temp = 0;
+	intv3_t ret_v;
+	intv3_t exp_v;
+	uint8_t nv_c;
+
+	common_data = emul_bmi_get_i2c_common_data(emul);
+	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
+
+	/* Test fail on NV CONF register read and write */
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_NV_CONF);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
+		      NULL);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(common_data, BMI260_NV_CONF);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
+		      NULL);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test fail on offset write */
+	i2c_common_emul_set_write_fail_reg(common_data, BMI160_OFFSET_ACC70);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
+		      NULL);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   BMI160_OFFSET_ACC70 + 1);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
+		      NULL);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   BMI160_OFFSET_ACC70 + 2);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
+		      NULL);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Setup NV_CONF register value */
+	bmi_emul_set_reg(emul, BMI260_NV_CONF, 0x7);
+	/* Set input offset */
+	exp_v[0] = BMI_EMUL_1G / 10;
+	exp_v[1] = BMI_EMUL_1G / 20;
+	exp_v[2] = -(int)BMI_EMUL_1G / 30;
+	/* BMI driver accept value in mg units */
+	input_v[0] = 1000 / 10;
+	input_v[1] = 1000 / 20;
+	input_v[2] = -1000 / 30;
+	/* Disable rotation */
+	ms->rot_standard_ref = NULL;
+
+	/* Test set offset without rotation */
+	zassert_equal(EC_SUCCESS, ms->drv->set_offset(ms, input_v, temp));
+	get_emul_acc_offset(emul, ret_v);
+	/*
+	 * Depending on used range, accelerometer values may be up to 6 bits
+	 * more accurate then offset value resolution.
+	 */
+	compare_int3v_eps(exp_v, ret_v, 64);
+	nv_c = bmi_emul_get_reg(emul, BMI260_NV_CONF);
+	/* Only ACC_OFFSET_EN bit should be changed */
+	zassert_equal(0x7 | BMI260_ACC_OFFSET_EN, nv_c,
+		      "Expected 0x%x, got 0x%x", 0x7 | BMI260_ACC_OFFSET_EN,
+		      nv_c);
+
+	/* Setup NV_CONF register value */
+	bmi_emul_set_reg(emul, BMI260_NV_CONF, 0);
+	/* Setup rotation and rotate input for set_offset function */
+	ms->rot_standard_ref = &test_rotation;
+	convert_int3v_int16(input_v, ret_v);
+	rotate_int3v_by_test_rotation(ret_v);
+	convert_int3v_int16(ret_v, input_v);
+
+	/* Test set offset with rotation */
+	zassert_equal(EC_SUCCESS, ms->drv->set_offset(ms, input_v, temp));
+	get_emul_acc_offset(emul, ret_v);
+	compare_int3v_eps(exp_v, ret_v, 64);
+	nv_c = bmi_emul_get_reg(emul, BMI260_NV_CONF);
+	/* Only ACC_OFFSET_EN bit should be changed */
+	zassert_equal(BMI260_ACC_OFFSET_EN, nv_c, "Expected 0x%x, got 0x%x",
+		      BMI260_ACC_OFFSET_EN, nv_c);
+}
+
+/**
+ * Test set gyroscope offset with and without rotation. Also test behaviour
+ * on I2C error.
+ */
+ZTEST_USER(bmi260, test_bmi_gyr_set_offset)
+{
+	struct motion_sensor_t *ms;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data;
+	int16_t input_v[3];
+	int16_t temp = 0;
+	intv3_t ret_v;
+	intv3_t exp_v;
+
+	common_data = emul_bmi_get_i2c_common_data(emul);
+	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
+
+	/* Test fail on OFFSET EN GYR98 register read and write */
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_OFFSET_EN_GYR98);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
+		      NULL);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(common_data, BMI260_OFFSET_EN_GYR98);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
+		      NULL);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test fail on offset write */
+	i2c_common_emul_set_write_fail_reg(common_data, BMI260_OFFSET_GYR70);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
+		      NULL);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   BMI260_OFFSET_GYR70 + 1);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
+		      NULL);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   BMI260_OFFSET_GYR70 + 2);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
+		      NULL);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Set input offset */
+	exp_v[0] = BMI_EMUL_125_DEG_S / 100;
+	exp_v[1] = BMI_EMUL_125_DEG_S / 200;
+	exp_v[2] = -(int)BMI_EMUL_125_DEG_S / 300;
+	/* BMI driver accept value in mdeg/s units */
+	input_v[0] = 125000 / 100;
+	input_v[1] = 125000 / 200;
+	input_v[2] = -125000 / 300;
+	/* Disable rotation */
+	ms->rot_standard_ref = NULL;
+
+	/* Test set offset without rotation */
+	zassert_equal(EC_SUCCESS, ms->drv->set_offset(ms, input_v, temp));
+	get_emul_gyr_offset(emul, ret_v);
+	/*
+	 * Depending on used range, gyroscope values may be up to 4 bits
+	 * more accurate then offset value resolution.
+	 */
+	compare_int3v_eps(exp_v, ret_v, 32);
+	/* Gyroscope offset should be enabled */
+	zassert_true(bmi_emul_get_reg(emul, BMI260_OFFSET_EN_GYR98) &
+			     BMI260_OFFSET_GYRO_EN,
+		     NULL);
+
+	/* Setup rotation and rotate input for set_offset function */
+	ms->rot_standard_ref = &test_rotation;
+	convert_int3v_int16(input_v, ret_v);
+	rotate_int3v_by_test_rotation(ret_v);
+	convert_int3v_int16(ret_v, input_v);
+
+	/* Test set offset with rotation */
+	zassert_equal(EC_SUCCESS, ms->drv->set_offset(ms, input_v, temp));
+	get_emul_gyr_offset(emul, ret_v);
+	compare_int3v_eps(exp_v, ret_v, 32);
+	zassert_true(bmi_emul_get_reg(emul, BMI260_OFFSET_EN_GYR98) &
+			     BMI260_OFFSET_GYRO_EN,
+		     NULL);
+}
+
+/**
+ * Try to set accelerometer range and check if expected range was set
+ * in driver and in emulator.
+ */
+static void check_set_acc_range_f(const struct emul *emul,
+				  struct motion_sensor_t *ms, int range,
+				  int rnd, int exp_range, int line)
+{
+	uint8_t exp_range_reg;
+	uint8_t range_reg;
+
+	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, range, rnd),
+		      "set_range failed; line: %d", line);
+	zassert_equal(exp_range, ms->current_range,
+		      "Expected range %d, got %d; line %d", exp_range,
+		      ms->current_range, line);
+	range_reg = bmi_emul_get_reg(emul, BMI260_ACC_RANGE);
+
+	switch (exp_range) {
+	case 2:
+		exp_range_reg = BMI260_GSEL_2G;
+		break;
+	case 4:
+		exp_range_reg = BMI260_GSEL_4G;
+		break;
+	case 8:
+		exp_range_reg = BMI260_GSEL_8G;
+		break;
+	case 16:
+		exp_range_reg = BMI260_GSEL_16G;
+		break;
+	default:
+		/* Unknown expected range */
+		zassert_unreachable(
+			"Expected range %d not supported by device; line %d",
+			exp_range, line);
+		return;
+	}
+
+	zassert_equal(exp_range_reg, range_reg,
+		      "Expected range reg 0x%x, got 0x%x; line %d",
+		      exp_range_reg, range_reg, line);
+}
+#define check_set_acc_range(emul, ms, range, rnd, exp_range) \
+	check_set_acc_range_f(emul, ms, range, rnd, exp_range, __LINE__)
+
+/** Test set accelerometer range with and without I2C errors */
+ZTEST_USER(bmi260, test_bmi_acc_set_range)
+{
+	struct motion_sensor_t *ms;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data;
+	int start_range;
+
+	common_data = emul_bmi_get_i2c_common_data(emul);
+	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
+
+	/* Setup starting range, shouldn't be changed on error */
+	start_range = 2;
+	ms->current_range = start_range;
+	bmi_emul_set_reg(emul, BMI260_ACC_RANGE, BMI260_GSEL_2G);
+	/* Setup emulator fail on write */
+	i2c_common_emul_set_write_fail_reg(common_data, BMI260_ACC_RANGE);
+
+	/* Test fail on write */
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_range(ms, 12, 0));
+	zassert_equal(start_range, ms->current_range);
+	zassert_equal(BMI260_GSEL_2G, bmi_emul_get_reg(emul, BMI260_ACC_RANGE),
+		      NULL);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_range(ms, 12, 1));
+	zassert_equal(start_range, ms->current_range);
+	zassert_equal(BMI260_GSEL_2G, bmi_emul_get_reg(emul, BMI260_ACC_RANGE),
+		      NULL);
+
+	/* Do not fail on write */
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test setting range with rounding down */
+	check_set_acc_range(emul, ms, 1, 0, 2);
+	check_set_acc_range(emul, ms, 2, 0, 2);
+	check_set_acc_range(emul, ms, 3, 0, 2);
+	check_set_acc_range(emul, ms, 4, 0, 4);
+	check_set_acc_range(emul, ms, 5, 0, 4);
+	check_set_acc_range(emul, ms, 6, 0, 4);
+	check_set_acc_range(emul, ms, 7, 0, 4);
+	check_set_acc_range(emul, ms, 8, 0, 8);
+	check_set_acc_range(emul, ms, 9, 0, 8);
+	check_set_acc_range(emul, ms, 15, 0, 8);
+	check_set_acc_range(emul, ms, 16, 0, 16);
+	check_set_acc_range(emul, ms, 17, 0, 16);
+
+	/* Test setting range with rounding up */
+	check_set_acc_range(emul, ms, 1, 1, 2);
+	check_set_acc_range(emul, ms, 2, 1, 2);
+	check_set_acc_range(emul, ms, 3, 1, 4);
+	check_set_acc_range(emul, ms, 4, 1, 4);
+	check_set_acc_range(emul, ms, 5, 1, 8);
+	check_set_acc_range(emul, ms, 6, 1, 8);
+	check_set_acc_range(emul, ms, 7, 1, 8);
+	check_set_acc_range(emul, ms, 8, 1, 8);
+	check_set_acc_range(emul, ms, 9, 1, 16);
+	check_set_acc_range(emul, ms, 15, 1, 16);
+	check_set_acc_range(emul, ms, 16, 1, 16);
+	check_set_acc_range(emul, ms, 17, 1, 16);
+}
+
+/**
+ * Try to set gyroscope range and check if expected range was set in driver and
+ * in emulator.
+ */
+static void check_set_gyr_range_f(const struct emul *emul,
+				  struct motion_sensor_t *ms, int range,
+				  int rnd, int exp_range, int line)
+{
+	uint8_t exp_range_reg;
+	uint8_t range_reg;
+
+	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, range, rnd),
+		      "set_range failed; line: %d", line);
+	zassert_equal(exp_range, ms->current_range,
+		      "Expected range %d, got %d; line %d", exp_range,
+		      ms->current_range, line);
+	range_reg = bmi_emul_get_reg(emul, BMI260_GYR_RANGE);
+
+	switch (exp_range) {
+	case 125:
+		exp_range_reg = BMI260_DPS_SEL_125;
+		break;
+	case 250:
+		exp_range_reg = BMI260_DPS_SEL_250;
+		break;
+	case 500:
+		exp_range_reg = BMI260_DPS_SEL_500;
+		break;
+	case 1000:
+		exp_range_reg = BMI260_DPS_SEL_1000;
+		break;
+	case 2000:
+		exp_range_reg = BMI260_DPS_SEL_2000;
+		break;
+	default:
+		/* Unknown expected range */
+		zassert_unreachable(
+			"Expected range %d not supported by device; line %d",
+			exp_range, line);
+		return;
+	}
+
+	zassert_equal(exp_range_reg, range_reg,
+		      "Expected range reg 0x%x, got 0x%x; line %d",
+		      exp_range_reg, range_reg, line);
+}
+#define check_set_gyr_range(emul, ms, range, rnd, exp_range) \
+	check_set_gyr_range_f(emul, ms, range, rnd, exp_range, __LINE__)
+
+/** Test set gyroscope range with and without I2C errors */
+ZTEST_USER(bmi260, test_bmi_gyr_set_range)
+{
+	struct motion_sensor_t *ms;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data;
+	int start_range;
+
+	common_data = emul_bmi_get_i2c_common_data(emul);
+	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
+
+	/* Setup starting range, shouldn't be changed on error */
+	start_range = 250;
+	ms->current_range = start_range;
+	bmi_emul_set_reg(emul, BMI260_GYR_RANGE, BMI260_DPS_SEL_250);
+	/* Setup emulator fail on write */
+	i2c_common_emul_set_write_fail_reg(common_data, BMI260_GYR_RANGE);
+
+	/* Test fail on write */
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_range(ms, 125, 0));
+	zassert_equal(start_range, ms->current_range);
+	zassert_equal(BMI260_DPS_SEL_250,
+		      bmi_emul_get_reg(emul, BMI260_GYR_RANGE), NULL);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_range(ms, 125, 1));
+	zassert_equal(start_range, ms->current_range);
+	zassert_equal(BMI260_DPS_SEL_250,
+		      bmi_emul_get_reg(emul, BMI260_GYR_RANGE), NULL);
+
+	/* Do not fail on write */
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test setting range with rounding down */
+	check_set_gyr_range(emul, ms, 1, 0, 125);
+	check_set_gyr_range(emul, ms, 124, 0, 125);
+	check_set_gyr_range(emul, ms, 125, 0, 125);
+	check_set_gyr_range(emul, ms, 126, 0, 125);
+	check_set_gyr_range(emul, ms, 249, 0, 125);
+	check_set_gyr_range(emul, ms, 250, 0, 250);
+	check_set_gyr_range(emul, ms, 251, 0, 250);
+	check_set_gyr_range(emul, ms, 499, 0, 250);
+	check_set_gyr_range(emul, ms, 500, 0, 500);
+	check_set_gyr_range(emul, ms, 501, 0, 500);
+	check_set_gyr_range(emul, ms, 999, 0, 500);
+	check_set_gyr_range(emul, ms, 1000, 0, 1000);
+	check_set_gyr_range(emul, ms, 1001, 0, 1000);
+	check_set_gyr_range(emul, ms, 1999, 0, 1000);
+	check_set_gyr_range(emul, ms, 2000, 0, 2000);
+	check_set_gyr_range(emul, ms, 2001, 0, 2000);
+
+	/* Test setting range with rounding up */
+	check_set_gyr_range(emul, ms, 1, 1, 125);
+	check_set_gyr_range(emul, ms, 124, 1, 125);
+	check_set_gyr_range(emul, ms, 125, 1, 125);
+	check_set_gyr_range(emul, ms, 126, 1, 250);
+	check_set_gyr_range(emul, ms, 249, 1, 250);
+	check_set_gyr_range(emul, ms, 250, 1, 250);
+	check_set_gyr_range(emul, ms, 251, 1, 500);
+	check_set_gyr_range(emul, ms, 499, 1, 500);
+	check_set_gyr_range(emul, ms, 500, 1, 500);
+	check_set_gyr_range(emul, ms, 501, 1, 1000);
+	check_set_gyr_range(emul, ms, 999, 1, 1000);
+	check_set_gyr_range(emul, ms, 1000, 1, 1000);
+	check_set_gyr_range(emul, ms, 1001, 1, 2000);
+	check_set_gyr_range(emul, ms, 1999, 1, 2000);
+	check_set_gyr_range(emul, ms, 2000, 1, 2000);
+	check_set_gyr_range(emul, ms, 2001, 1, 2000);
+}
+
+/** Test get resolution of acclerometer and gyroscope sensor */
+ZTEST_USER(bmi260, test_bmi_get_resolution)
+{
+	struct motion_sensor_t *ms;
+
+	/* Test accelerometer */
+	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
+
+	/* Resolution should be always 16 bits */
+	zassert_equal(16, ms->drv->get_resolution(ms));
+
+	/* Test gyroscope */
+	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
+
+	/* Resolution should be always 16 bits */
+	zassert_equal(16, ms->drv->get_resolution(ms));
+}
+
+/**
+ * Try to set accelerometer data rate and check if expected rate was set
+ * in driver and in emulator.
+ */
+static void check_set_acc_rate_f(const struct emul *emul,
+				 struct motion_sensor_t *ms, int rate, int rnd,
+				 int exp_rate, int line)
+{
+	uint8_t exp_rate_reg;
+	uint8_t rate_reg;
+	int drv_rate;
+
+	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, rate, rnd),
+		      "set_data_rate failed; line: %d", line);
+	drv_rate = ms->drv->get_data_rate(ms);
+	zassert_equal(exp_rate, drv_rate, "Expected rate %d, got %d; line %d",
+		      exp_rate, drv_rate, line);
+	rate_reg = bmi_emul_get_reg(emul, BMI260_ACC_CONF);
+	rate_reg &= BMI_ODR_MASK;
+
+	switch (exp_rate) {
+	case 12500:
+		exp_rate_reg = 0x5;
+		break;
+	case 25000:
+		exp_rate_reg = 0x6;
+		break;
+	case 50000:
+		exp_rate_reg = 0x7;
+		break;
+	case 100000:
+		exp_rate_reg = 0x8;
+		break;
+	case 200000:
+		exp_rate_reg = 0x9;
+		break;
+	case 400000:
+		exp_rate_reg = 0xa;
+		break;
+	case 800000:
+		exp_rate_reg = 0xb;
+		break;
+	case 1600000:
+		exp_rate_reg = 0xc;
+		break;
+	default:
+		/* Unknown expected rate */
+		zassert_unreachable(
+			"Expected rate %d not supported by device; line %d",
+			exp_rate, line);
+		return;
+	}
+
+	zassert_equal(exp_rate_reg, rate_reg,
+		      "Expected rate reg 0x%x, got 0x%x; line %d", exp_rate_reg,
+		      rate_reg, line);
+}
+#define check_set_acc_rate(emul, ms, rate, rnd, exp_rate) \
+	check_set_acc_rate_f(emul, ms, rate, rnd, exp_rate, __LINE__)
+
+/** Test set and get accelerometer rate with and without I2C errors */
+ZTEST_USER(bmi260, test_bmi_acc_rate)
+{
+	struct motion_sensor_t *ms;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data;
+	uint8_t reg_rate;
+	uint8_t pwr_ctrl;
+	int drv_rate;
+
+	common_data = emul_bmi_get_i2c_common_data(emul);
+	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
+
+	/* Test setting rate with rounding down */
+	check_set_acc_rate(emul, ms, 12500, 0, 12500);
+	check_set_acc_rate(emul, ms, 12501, 0, 12500);
+	check_set_acc_rate(emul, ms, 24999, 0, 12500);
+	check_set_acc_rate(emul, ms, 25000, 0, 25000);
+	check_set_acc_rate(emul, ms, 25001, 0, 25000);
+	check_set_acc_rate(emul, ms, 49999, 0, 25000);
+	check_set_acc_rate(emul, ms, 50000, 0, 50000);
+	check_set_acc_rate(emul, ms, 50001, 0, 50000);
+	check_set_acc_rate(emul, ms, 99999, 0, 50000);
+	check_set_acc_rate(emul, ms, 100000, 0, 100000);
+	check_set_acc_rate(emul, ms, 100001, 0, 100000);
+	check_set_acc_rate(emul, ms, 199999, 0, 100000);
+	check_set_acc_rate(emul, ms, 200000, 0, 200000);
+	check_set_acc_rate(emul, ms, 200001, 0, 200000);
+	check_set_acc_rate(emul, ms, 399999, 0, 200000);
+	/*
+	 * We cannot test frequencies from 400000 to 1600000 because
+	 * CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ is set to 250000
+	 */
+
+	/* Test setting rate with rounding up */
+	check_set_acc_rate(emul, ms, 6251, 1, 12500);
+	check_set_acc_rate(emul, ms, 12499, 1, 12500);
+	check_set_acc_rate(emul, ms, 12500, 1, 12500);
+	check_set_acc_rate(emul, ms, 12501, 1, 25000);
+	check_set_acc_rate(emul, ms, 24999, 1, 25000);
+	check_set_acc_rate(emul, ms, 25000, 1, 25000);
+	check_set_acc_rate(emul, ms, 25001, 1, 50000);
+	check_set_acc_rate(emul, ms, 49999, 1, 50000);
+	check_set_acc_rate(emul, ms, 50000, 1, 50000);
+	check_set_acc_rate(emul, ms, 50001, 1, 100000);
+	check_set_acc_rate(emul, ms, 99999, 1, 100000);
+	check_set_acc_rate(emul, ms, 100000, 1, 100000);
+	check_set_acc_rate(emul, ms, 100001, 1, 200000);
+	check_set_acc_rate(emul, ms, 199999, 1, 200000);
+	check_set_acc_rate(emul, ms, 200000, 1, 200000);
+
+	/* Test out of range rate with rounding down */
+	zassert_equal(EC_RES_INVALID_PARAM, ms->drv->set_data_rate(ms, 1, 0),
+		      NULL);
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      ms->drv->set_data_rate(ms, 12499, 0), NULL);
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      ms->drv->set_data_rate(ms, 400000, 0), NULL);
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      ms->drv->set_data_rate(ms, 2000000, 0), NULL);
+
+	/* Test out of range rate with rounding up */
+	zassert_equal(EC_RES_INVALID_PARAM, ms->drv->set_data_rate(ms, 1, 1),
+		      NULL);
+	zassert_equal(EC_RES_INVALID_PARAM, ms->drv->set_data_rate(ms, 6250, 1),
+		      NULL);
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      ms->drv->set_data_rate(ms, 200001, 1), NULL);
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      ms->drv->set_data_rate(ms, 400000, 1), NULL);
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      ms->drv->set_data_rate(ms, 2000000, 1), NULL);
+
+	/* Current rate shouldn't be changed on error */
+	drv_rate = ms->drv->get_data_rate(ms);
+	reg_rate = bmi_emul_get_reg(emul, BMI260_ACC_CONF);
+
+	/* Setup emulator fail on read */
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_ACC_CONF);
+
+	/* Test fail on read */
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 50000, 0),
+		      NULL);
+	zassert_equal(drv_rate, ms->drv->get_data_rate(ms));
+	zassert_equal(reg_rate, bmi_emul_get_reg(emul, BMI260_ACC_CONF));
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 50000, 1),
+		      NULL);
+	zassert_equal(drv_rate, ms->drv->get_data_rate(ms));
+	zassert_equal(reg_rate, bmi_emul_get_reg(emul, BMI260_ACC_CONF));
+
+	/* Do not fail on read */
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Setup emulator fail on write */
+	i2c_common_emul_set_write_fail_reg(common_data, BMI260_ACC_CONF);
+
+	/* Test fail on write */
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 50000, 0),
+		      NULL);
+	zassert_equal(drv_rate, ms->drv->get_data_rate(ms));
+	zassert_equal(reg_rate, bmi_emul_get_reg(emul, BMI260_ACC_CONF));
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 50000, 1),
+		      NULL);
+	zassert_equal(drv_rate, ms->drv->get_data_rate(ms));
+	zassert_equal(reg_rate, bmi_emul_get_reg(emul, BMI260_ACC_CONF));
+
+	/* Do not fail on write */
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test disabling sensor */
+	bmi_emul_set_reg(emul, BMI260_PWR_CTRL,
+			 BMI260_AUX_EN | BMI260_GYR_EN | BMI260_ACC_EN);
+	bmi_emul_set_reg(emul, BMI260_ACC_CONF, BMI260_FILTER_PERF);
+	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, 0, 0));
+
+	pwr_ctrl = bmi_emul_get_reg(emul, BMI260_PWR_CTRL);
+	reg_rate = bmi_emul_get_reg(emul, BMI260_ACC_CONF);
+	zassert_equal(BMI260_AUX_EN | BMI260_GYR_EN, pwr_ctrl);
+	zassert_true(!(reg_rate & BMI260_FILTER_PERF));
+
+	/* Test enabling sensor */
+	bmi_emul_set_reg(emul, BMI260_PWR_CTRL, 0);
+	bmi_emul_set_reg(emul, BMI260_ACC_CONF, 0);
+	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, 50000, 0));
+
+	pwr_ctrl = bmi_emul_get_reg(emul, BMI260_PWR_CTRL);
+	reg_rate = bmi_emul_get_reg(emul, BMI260_ACC_CONF);
+	zassert_equal(BMI260_ACC_EN, pwr_ctrl);
+	zassert_true(reg_rate & BMI260_FILTER_PERF);
+
+	/* Test disabling sensor (by setting rate to 0) but failing. */
+	i2c_common_emul_set_write_fail_reg(common_data, BMI260_PWR_CTRL);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 0, 0),
+		      "Did not properly handle failed power down.");
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test enabling sensor but failing. (after first disabling it) */
+	ms->drv->set_data_rate(ms, 0, 0);
+
+	i2c_common_emul_set_write_fail_reg(common_data, BMI260_PWR_CTRL);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 50000, 0),
+		      "Did not properly handle failed power up.");
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+}
+
+/**
+ * Try to set gyroscope data rate and check if expected rate was set
+ * in driver and in emulator.
+ */
+static void check_set_gyr_rate_f(const struct emul *emul,
+				 struct motion_sensor_t *ms, int rate, int rnd,
+				 int exp_rate, int line)
+{
+	uint8_t exp_rate_reg;
+	uint8_t rate_reg;
+	int drv_rate;
+
+	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, rate, rnd),
+		      "set_data_rate failed; line: %d", line);
+	drv_rate = ms->drv->get_data_rate(ms);
+	zassert_equal(exp_rate, drv_rate, "Expected rate %d, got %d; line %d",
+		      exp_rate, drv_rate, line);
+	rate_reg = bmi_emul_get_reg(emul, BMI260_GYR_CONF);
+	rate_reg &= BMI_ODR_MASK;
+
+	switch (exp_rate) {
+	case 25000:
+		exp_rate_reg = 0x6;
+		break;
+	case 50000:
+		exp_rate_reg = 0x7;
+		break;
+	case 100000:
+		exp_rate_reg = 0x8;
+		break;
+	case 200000:
+		exp_rate_reg = 0x9;
+		break;
+	case 400000:
+		exp_rate_reg = 0xa;
+		break;
+	case 800000:
+		exp_rate_reg = 0xb;
+		break;
+	case 1600000:
+		exp_rate_reg = 0xc;
+		break;
+	case 3200000:
+		exp_rate_reg = 0xc;
+		break;
+	default:
+		/* Unknown expected rate */
+		zassert_unreachable(
+			"Expected rate %d not supported by device; line %d",
+			exp_rate, line);
+		return;
+	}
+
+	zassert_equal(exp_rate_reg, rate_reg,
+		      "Expected rate reg 0x%x, got 0x%x; line %d", exp_rate_reg,
+		      rate_reg, line);
+}
+#define check_set_gyr_rate(emul, ms, rate, rnd, exp_rate) \
+	check_set_gyr_rate_f(emul, ms, rate, rnd, exp_rate, __LINE__)
+
+/** Test set and get gyroscope rate with and without I2C errors */
+ZTEST_USER(bmi260, test_bmi_gyr_rate)
+{
+	struct motion_sensor_t *ms;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data;
+	uint8_t reg_rate;
+	uint8_t pwr_ctrl;
+	int drv_rate;
+
+	common_data = emul_bmi_get_i2c_common_data(emul);
+	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
+
+	/* Test setting rate with rounding down */
+	check_set_gyr_rate(emul, ms, 25000, 0, 25000);
+	check_set_gyr_rate(emul, ms, 25001, 0, 25000);
+	check_set_gyr_rate(emul, ms, 49999, 0, 25000);
+	check_set_gyr_rate(emul, ms, 50000, 0, 50000);
+	check_set_gyr_rate(emul, ms, 50001, 0, 50000);
+	check_set_gyr_rate(emul, ms, 99999, 0, 50000);
+	check_set_gyr_rate(emul, ms, 100000, 0, 100000);
+	check_set_gyr_rate(emul, ms, 100001, 0, 100000);
+	check_set_gyr_rate(emul, ms, 199999, 0, 100000);
+	check_set_gyr_rate(emul, ms, 200000, 0, 200000);
+	check_set_gyr_rate(emul, ms, 200001, 0, 200000);
+	check_set_gyr_rate(emul, ms, 399999, 0, 200000);
+	/*
+	 * We cannot test frequencies from 400000 to 3200000 because
+	 * CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ is set to 250000
+	 */
+
+	/* Test setting rate with rounding up */
+	check_set_gyr_rate(emul, ms, 12501, 1, 25000);
+	check_set_gyr_rate(emul, ms, 24999, 1, 25000);
+	check_set_gyr_rate(emul, ms, 25000, 1, 25000);
+	check_set_gyr_rate(emul, ms, 25001, 1, 50000);
+	check_set_gyr_rate(emul, ms, 49999, 1, 50000);
+	check_set_gyr_rate(emul, ms, 50000, 1, 50000);
+	check_set_gyr_rate(emul, ms, 50001, 1, 100000);
+	check_set_gyr_rate(emul, ms, 99999, 1, 100000);
+	check_set_gyr_rate(emul, ms, 100000, 1, 100000);
+	check_set_gyr_rate(emul, ms, 100001, 1, 200000);
+	check_set_gyr_rate(emul, ms, 199999, 1, 200000);
+	check_set_gyr_rate(emul, ms, 200000, 1, 200000);
+
+	/* Test out of range rate with rounding down */
+	zassert_equal(EC_RES_INVALID_PARAM, ms->drv->set_data_rate(ms, 1, 0),
+		      NULL);
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      ms->drv->set_data_rate(ms, 24999, 0), NULL);
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      ms->drv->set_data_rate(ms, 400000, 0), NULL);
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      ms->drv->set_data_rate(ms, 4000000, 0), NULL);
+
+	/* Test out of range rate with rounding up */
+	zassert_equal(EC_RES_INVALID_PARAM, ms->drv->set_data_rate(ms, 1, 1),
+		      NULL);
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      ms->drv->set_data_rate(ms, 12499, 1), NULL);
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      ms->drv->set_data_rate(ms, 200001, 1), NULL);
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      ms->drv->set_data_rate(ms, 400000, 1), NULL);
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      ms->drv->set_data_rate(ms, 4000000, 1), NULL);
+
+	/* Current rate shouldn't be changed on error */
+	drv_rate = ms->drv->get_data_rate(ms);
+	reg_rate = bmi_emul_get_reg(emul, BMI260_GYR_CONF);
+
+	/* Setup emulator fail on read */
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_GYR_CONF);
+
+	/* Test fail on read */
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 50000, 0),
+		      NULL);
+	zassert_equal(drv_rate, ms->drv->get_data_rate(ms));
+	zassert_equal(reg_rate, bmi_emul_get_reg(emul, BMI260_GYR_CONF));
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 50000, 1),
+		      NULL);
+	zassert_equal(drv_rate, ms->drv->get_data_rate(ms));
+	zassert_equal(reg_rate, bmi_emul_get_reg(emul, BMI260_GYR_CONF));
+
+	/* Do not fail on read */
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Setup emulator fail on write */
+	i2c_common_emul_set_write_fail_reg(common_data, BMI260_GYR_CONF);
+
+	/* Test fail on write */
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 50000, 0),
+		      NULL);
+	zassert_equal(drv_rate, ms->drv->get_data_rate(ms));
+	zassert_equal(reg_rate, bmi_emul_get_reg(emul, BMI260_GYR_CONF));
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 50000, 1),
+		      NULL);
+	zassert_equal(drv_rate, ms->drv->get_data_rate(ms));
+	zassert_equal(reg_rate, bmi_emul_get_reg(emul, BMI260_GYR_CONF));
+
+	/* Do not fail on write */
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test disabling sensor */
+	bmi_emul_set_reg(emul, BMI260_PWR_CTRL,
+			 BMI260_AUX_EN | BMI260_GYR_EN | BMI260_ACC_EN);
+	bmi_emul_set_reg(emul, BMI260_GYR_CONF,
+			 BMI260_FILTER_PERF | BMI260_GYR_NOISE_PERF);
+	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, 0, 0));
+
+	pwr_ctrl = bmi_emul_get_reg(emul, BMI260_PWR_CTRL);
+	reg_rate = bmi_emul_get_reg(emul, BMI260_GYR_CONF);
+	zassert_equal(BMI260_AUX_EN | BMI260_ACC_EN, pwr_ctrl);
+	zassert_true(!(reg_rate & (BMI260_FILTER_PERF | BMI260_GYR_NOISE_PERF)),
+		     NULL);
+
+	/* Test enabling sensor */
+	bmi_emul_set_reg(emul, BMI260_PWR_CTRL, 0);
+	bmi_emul_set_reg(emul, BMI260_GYR_CONF, 0);
+	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, 50000, 0));
+
+	pwr_ctrl = bmi_emul_get_reg(emul, BMI260_PWR_CTRL);
+	reg_rate = bmi_emul_get_reg(emul, BMI260_GYR_CONF);
+	zassert_equal(BMI260_GYR_EN, pwr_ctrl);
+	zassert_true(reg_rate & (BMI260_FILTER_PERF | BMI260_GYR_NOISE_PERF),
+		     NULL);
+}
+
+/**
+ * Test setting and getting scale in accelerometer and gyroscope sensors.
+ * Correct appling scale to results is checked in "read" test.
+ */
+ZTEST_USER(bmi260, test_bmi_scale)
+{
+	struct motion_sensor_t *ms;
+	int16_t ret_scale[3];
+	int16_t exp_scale[3] = { 100, 231, 421 };
+	int16_t t;
+
+	/* Test accelerometer */
+	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
+
+	zassert_equal(EC_SUCCESS, ms->drv->set_scale(ms, exp_scale, 0));
+	zassert_equal(EC_SUCCESS, ms->drv->get_scale(ms, ret_scale, &t));
+
+	zassert_equal(t, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP);
+	zassert_equal(exp_scale[0], ret_scale[0]);
+	zassert_equal(exp_scale[1], ret_scale[1]);
+	zassert_equal(exp_scale[2], ret_scale[2]);
+
+	/* Test gyroscope */
+	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
+
+	zassert_equal(EC_SUCCESS, ms->drv->set_scale(ms, exp_scale, 0));
+	zassert_equal(EC_SUCCESS, ms->drv->get_scale(ms, ret_scale, &t));
+
+	zassert_equal(t, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP);
+	zassert_equal(exp_scale[0], ret_scale[0]);
+	zassert_equal(exp_scale[1], ret_scale[1]);
+	zassert_equal(exp_scale[2], ret_scale[2]);
+}
+
+/** Test reading temperature using accelerometer and gyroscope sensors */
+ZTEST_USER(bmi260, test_bmi_read_temp)
+{
+	struct motion_sensor_t *ms_acc, *ms_gyr;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data;
+	int ret_temp;
+	int exp_temp;
+
+	common_data = emul_bmi_get_i2c_common_data(emul);
+	ms_acc = &motion_sensors[BMI_ACC_SENSOR_ID];
+	ms_gyr = &motion_sensors[BMI_GYR_SENSOR_ID];
+
+	/* Setup emulator fail on read */
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_TEMPERATURE_0);
+	zassert_equal(EC_ERROR_NOT_POWERED,
+		      ms_acc->drv->read_temp(ms_acc, &ret_temp), NULL);
+	zassert_equal(EC_ERROR_NOT_POWERED,
+		      ms_gyr->drv->read_temp(ms_gyr, &ret_temp), NULL);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_TEMPERATURE_1);
+	zassert_equal(EC_ERROR_NOT_POWERED,
+		      ms_acc->drv->read_temp(ms_acc, &ret_temp), NULL);
+	zassert_equal(EC_ERROR_NOT_POWERED,
+		      ms_gyr->drv->read_temp(ms_gyr, &ret_temp), NULL);
+	/* Do not fail on read */
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Fail on invalid temperature */
+	bmi_emul_set_reg(emul, BMI260_TEMPERATURE_0, 0x00);
+	bmi_emul_set_reg(emul, BMI260_TEMPERATURE_1, 0x80);
+	zassert_equal(EC_ERROR_NOT_POWERED,
+		      ms_acc->drv->read_temp(ms_acc, &ret_temp), NULL);
+	zassert_equal(EC_ERROR_NOT_POWERED,
+		      ms_gyr->drv->read_temp(ms_gyr, &ret_temp), NULL);
+
+	/*
+	 * Test correct values. Both motion sensors should return the same
+	 * temperature.
+	 */
+	exp_temp = C_TO_K(23);
+	bmi_emul_set_reg(emul, BMI260_TEMPERATURE_0, 0x00);
+	bmi_emul_set_reg(emul, BMI260_TEMPERATURE_1, 0x00);
+	zassert_equal(EC_SUCCESS, ms_acc->drv->read_temp(ms_acc, &ret_temp),
+		      NULL);
+	zassert_equal(exp_temp, ret_temp);
+	zassert_equal(EC_SUCCESS, ms_gyr->drv->read_temp(ms_gyr, &ret_temp),
+		      NULL);
+	zassert_equal(exp_temp, ret_temp);
+
+	exp_temp = C_TO_K(87);
+	bmi_emul_set_reg(emul, BMI260_TEMPERATURE_0, 0xff);
+	bmi_emul_set_reg(emul, BMI260_TEMPERATURE_1, 0x7f);
+	zassert_equal(EC_SUCCESS, ms_acc->drv->read_temp(ms_acc, &ret_temp),
+		      NULL);
+	zassert_equal(exp_temp, ret_temp);
+	zassert_equal(EC_SUCCESS, ms_gyr->drv->read_temp(ms_gyr, &ret_temp),
+		      NULL);
+	zassert_equal(exp_temp, ret_temp);
+
+	exp_temp = C_TO_K(-41);
+	bmi_emul_set_reg(emul, BMI260_TEMPERATURE_0, 0x01);
+	bmi_emul_set_reg(emul, BMI260_TEMPERATURE_1, 0x80);
+	zassert_equal(EC_SUCCESS, ms_acc->drv->read_temp(ms_acc, &ret_temp),
+		      NULL);
+	zassert_equal(exp_temp, ret_temp);
+	zassert_equal(EC_SUCCESS, ms_gyr->drv->read_temp(ms_gyr, &ret_temp),
+		      NULL);
+	zassert_equal(exp_temp, ret_temp);
+
+	exp_temp = C_TO_K(47);
+	bmi_emul_set_reg(emul, BMI260_TEMPERATURE_0, 0x00);
+	bmi_emul_set_reg(emul, BMI260_TEMPERATURE_1, 0x30);
+	zassert_equal(EC_SUCCESS, ms_acc->drv->read_temp(ms_acc, &ret_temp),
+		      NULL);
+	zassert_equal(exp_temp, ret_temp);
+	zassert_equal(EC_SUCCESS, ms_gyr->drv->read_temp(ms_gyr, &ret_temp),
+		      NULL);
+	zassert_equal(exp_temp, ret_temp);
+}
+
+/** Test reading accelerometer sensor data */
+ZTEST_USER(bmi260, test_bmi_acc_read)
+{
+	struct motion_sensor_t *ms;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data;
+	intv3_t ret_v;
+	intv3_t exp_v;
+	int16_t scale[3] = { MOTION_SENSE_DEFAULT_SCALE,
+			     MOTION_SENSE_DEFAULT_SCALE,
+			     MOTION_SENSE_DEFAULT_SCALE };
+
+	common_data = emul_bmi_get_i2c_common_data(emul);
+	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
+
+	/* Set offset 0 to simplify test */
+	bmi_emul_set_off(emul, BMI_EMUL_ACC_X, 0);
+	bmi_emul_set_off(emul, BMI_EMUL_ACC_Y, 0);
+	bmi_emul_set_off(emul, BMI_EMUL_ACC_Z, 0);
+
+	/* Fail on read status */
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_STATUS);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v));
+
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* When not ready, driver should return saved raw value */
+	exp_v[0] = 100;
+	exp_v[1] = 200;
+	exp_v[2] = 300;
+	ms->raw_xyz[0] = exp_v[0];
+	ms->raw_xyz[1] = exp_v[1];
+	ms->raw_xyz[2] = exp_v[2];
+
+	/* Status not ready */
+	bmi_emul_set_reg(emul, BMI260_STATUS, 0);
+	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v));
+	compare_int3v(exp_v, ret_v);
+
+	/* Status only GYR ready */
+	bmi_emul_set_reg(emul, BMI260_STATUS, BMI260_DRDY_GYR);
+	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v));
+	compare_int3v(exp_v, ret_v);
+
+	/* Status ACC ready */
+	bmi_emul_set_reg(emul, BMI260_STATUS, BMI260_DRDY_ACC);
+
+	/* Set input accelerometer values */
+	exp_v[0] = BMI_EMUL_1G / 10;
+	exp_v[1] = BMI_EMUL_1G / 20;
+	exp_v[2] = -(int)BMI_EMUL_1G / 30;
+	set_emul_acc(emul, exp_v);
+	/* Disable rotation */
+	ms->rot_standard_ref = NULL;
+	/* Set scale */
+	zassert_equal(EC_SUCCESS, ms->drv->set_scale(ms, scale, 0));
+	/* Set range to 2G */
+	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, 2, 0));
+
+	/* Test read without rotation */
+	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v));
+	drv_acc_to_emul(ret_v, 2, ret_v);
+	compare_int3v(exp_v, ret_v);
+
+	/* Set range to 4G */
+	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, 4, 0));
+
+	/* Test read without rotation */
+	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v));
+	drv_acc_to_emul(ret_v, 4, ret_v);
+	compare_int3v(exp_v, ret_v);
+
+	/* Setup rotation and rotate expected vector */
+	ms->rot_standard_ref = &test_rotation;
+	rotate_int3v_by_test_rotation(exp_v);
+	/* Set range to 2G */
+	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, 2, 0));
+
+	/* Test read with rotation */
+	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v));
+	drv_acc_to_emul(ret_v, 2, ret_v);
+	compare_int3v(exp_v, ret_v);
+
+	/* Set range to 4G */
+	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, 4, 0));
+
+	/* Test read with rotation */
+	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v));
+	drv_acc_to_emul(ret_v, 4, ret_v);
+	compare_int3v(exp_v, ret_v);
+
+	/* Fail on read of data registers */
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_ACC_X_L_G);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v));
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_ACC_X_H_G);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v));
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_ACC_Y_L_G);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v));
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_ACC_Y_H_G);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v));
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_ACC_Z_L_G);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v));
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_ACC_Z_H_G);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v));
+
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	ms->rot_standard_ref = NULL;
+}
+
+/** Test reading gyroscope sensor data */
+ZTEST_USER(bmi260, test_bmi_gyr_read)
+{
+	struct motion_sensor_t *ms;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data;
+	intv3_t ret_v;
+	intv3_t exp_v;
+	int16_t scale[3] = { MOTION_SENSE_DEFAULT_SCALE,
+			     MOTION_SENSE_DEFAULT_SCALE,
+			     MOTION_SENSE_DEFAULT_SCALE };
+
+	common_data = emul_bmi_get_i2c_common_data(emul);
+	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
+
+	/* Set offset 0 to simplify test */
+	bmi_emul_set_off(emul, BMI_EMUL_GYR_X, 0);
+	bmi_emul_set_off(emul, BMI_EMUL_GYR_Y, 0);
+	bmi_emul_set_off(emul, BMI_EMUL_GYR_Z, 0);
+
+	/* Fail on read status */
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_STATUS);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v));
+
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* When not ready, driver should return saved raw value */
+	exp_v[0] = 100;
+	exp_v[1] = 200;
+	exp_v[2] = 300;
+	ms->raw_xyz[0] = exp_v[0];
+	ms->raw_xyz[1] = exp_v[1];
+	ms->raw_xyz[2] = exp_v[2];
+
+	/* Status not ready */
+	bmi_emul_set_reg(emul, BMI260_STATUS, 0);
+	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v));
+	compare_int3v(exp_v, ret_v);
+
+	/* Status only ACC ready */
+	bmi_emul_set_reg(emul, BMI260_STATUS, BMI260_DRDY_ACC);
+	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v));
+	compare_int3v(exp_v, ret_v);
+
+	/* Status GYR ready */
+	bmi_emul_set_reg(emul, BMI260_STATUS, BMI260_DRDY_GYR);
+
+	/* Set input accelerometer values */
+	exp_v[0] = BMI_EMUL_125_DEG_S / 10;
+	exp_v[1] = BMI_EMUL_125_DEG_S / 20;
+	exp_v[2] = -(int)BMI_EMUL_125_DEG_S / 30;
+	set_emul_gyr(emul, exp_v);
+	/* Disable rotation */
+	ms->rot_standard_ref = NULL;
+	/* Set scale */
+	zassert_equal(EC_SUCCESS, ms->drv->set_scale(ms, scale, 0));
+	/* Set range to 125°/s */
+	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, 125, 0));
+
+	/* Test read without rotation */
+	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v));
+	drv_gyr_to_emul(ret_v, 125, ret_v);
+	compare_int3v(exp_v, ret_v);
+
+	/* Set range to 1000°/s */
+	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, 1000, 0));
+
+	/* Test read without rotation */
+	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v));
+	drv_gyr_to_emul(ret_v, 1000, ret_v);
+	compare_int3v(exp_v, ret_v);
+
+	/* Setup rotation and rotate expected vector */
+	ms->rot_standard_ref = &test_rotation;
+	rotate_int3v_by_test_rotation(exp_v);
+	/* Set range to 125°/s */
+	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, 125, 0));
+
+	/* Test read with rotation */
+	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v));
+	drv_gyr_to_emul(ret_v, 125, ret_v);
+	compare_int3v(exp_v, ret_v);
+
+	/* Set range to 1000°/s */
+	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, 1000, 0));
+
+	/* Test read with rotation */
+	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v));
+	drv_gyr_to_emul(ret_v, 1000, ret_v);
+	compare_int3v(exp_v, ret_v);
+
+	/* Fail on read of data registers */
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_GYR_X_L_G);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v));
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_GYR_X_H_G);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v));
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_GYR_Y_L_G);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v));
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_GYR_Y_H_G);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v));
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_GYR_Z_L_G);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v));
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_GYR_Z_H_G);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v));
+
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	ms->rot_standard_ref = NULL;
+}
+
+/** Test accelerometer calibration */
+ZTEST_USER(bmi260, test_bmi_acc_perform_calib)
+{
+	struct motion_sensor_t *ms;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data;
+	intv3_t start_off;
+	intv3_t exp_off;
+	intv3_t ret_off;
+	int range;
+	int rate;
+
+	common_data = emul_bmi_get_i2c_common_data(emul);
+	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
+
+	bmi_init_emul();
+
+	/* Disable rotation */
+	ms->rot_standard_ref = NULL;
+
+	/* Range and rate cannot change after calibration */
+	range = 4;
+	rate = 50000;
+	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, range, 0));
+	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, rate, 0));
+
+	/* Set offset 0 */
+	start_off[0] = 0;
+	start_off[1] = 0;
+	start_off[2] = 0;
+	set_emul_acc_offset(emul, start_off);
+
+	/* Set input accelerometer values */
+	exp_off[0] = BMI_EMUL_1G / 10;
+	exp_off[1] = BMI_EMUL_1G / 20;
+	exp_off[2] = BMI_EMUL_1G - (int)BMI_EMUL_1G / 30;
+	set_emul_acc(emul, exp_off);
+
+	/* Expected offset is [-X, -Y, 1G - Z] */
+	exp_off[0] = -exp_off[0];
+	exp_off[1] = -exp_off[1];
+	exp_off[2] = BMI_EMUL_1G - exp_off[2];
+
+	/* Test success on disabling calibration */
+	zassert_equal(EC_SUCCESS, ms->drv->perform_calib(ms, 0));
+	zassert_equal(range, ms->current_range);
+	zassert_equal(rate, ms->drv->get_data_rate(ms));
+
+	/* Test fail on rate read */
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_ACC_CONF);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->perform_calib(ms, 1));
+	zassert_equal(range, ms->current_range);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	zassert_equal(rate, ms->drv->get_data_rate(ms));
+
+	/* Test fail on status read */
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_STATUS);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->perform_calib(ms, 1));
+	zassert_equal(range, ms->current_range);
+	zassert_equal(rate, ms->drv->get_data_rate(ms));
+
+	/* Test fail on data not ready */
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	bmi_emul_set_reg(emul, BMI260_STATUS, 0);
+	zassert_equal(EC_ERROR_TIMEOUT, ms->drv->perform_calib(ms, 1));
+	zassert_equal(range, ms->current_range);
+	zassert_equal(rate, ms->drv->get_data_rate(ms));
+
+	/* Setup data status ready for rest of the test */
+	bmi_emul_set_reg(emul, BMI260_STATUS, BMI260_DRDY_ACC);
+
+	/* Test fail on data read */
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_ACC_X_L_G);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->perform_calib(ms, 1));
+	zassert_equal(range, ms->current_range);
+	zassert_equal(rate, ms->drv->get_data_rate(ms));
+
+	/* Test fail on setting offset */
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_NV_CONF);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->perform_calib(ms, 1));
+	zassert_equal(range, ms->current_range);
+	zassert_equal(rate, ms->drv->get_data_rate(ms));
+
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test successful offset compenastion */
+	zassert_equal(EC_SUCCESS, ms->drv->perform_calib(ms, 1));
+	zassert_equal(range, ms->current_range);
+	zassert_equal(rate, ms->drv->get_data_rate(ms));
+	get_emul_acc_offset(emul, ret_off);
+	/*
+	 * Depending on used range, accelerometer values may be up to 6 bits
+	 * more accurate then offset value resolution.
+	 */
+	compare_int3v_eps(exp_off, ret_off, 64);
+}
+
+/** Test gyroscope calibration */
+ZTEST_USER(bmi260, test_bmi_gyr_perform_calib)
+{
+	struct motion_sensor_t *ms;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data;
+	intv3_t start_off;
+	intv3_t exp_off;
+	intv3_t ret_off;
+	int range;
+	int rate;
+
+	common_data = emul_bmi_get_i2c_common_data(emul);
+	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
+
+	bmi_init_emul();
+
+	/* Range and rate cannot change after calibration */
+	range = 125;
+	rate = 50000;
+	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, range, 0));
+	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, rate, 0));
+
+	/* Set offset 0 */
+	start_off[0] = 0;
+	start_off[1] = 0;
+	start_off[2] = 0;
+	set_emul_gyr_offset(emul, start_off);
+
+	/* Set input accelerometer values */
+	exp_off[0] = BMI_EMUL_125_DEG_S / 100;
+	exp_off[1] = BMI_EMUL_125_DEG_S / 200;
+	exp_off[2] = -(int)BMI_EMUL_125_DEG_S / 300;
+	set_emul_gyr(emul, exp_off);
+
+	/* Expected offset is [-X, -Y, -Z] */
+	exp_off[0] = -exp_off[0];
+	exp_off[1] = -exp_off[1];
+	exp_off[2] = -exp_off[2];
+
+	/* Test success on disabling calibration */
+	zassert_equal(EC_SUCCESS, ms->drv->perform_calib(ms, 0));
+	zassert_equal(range, ms->current_range);
+	zassert_equal(rate, ms->drv->get_data_rate(ms));
+
+	/* Test fail on rate read */
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_GYR_CONF);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->perform_calib(ms, 1));
+	zassert_equal(range, ms->current_range);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	zassert_equal(rate, ms->drv->get_data_rate(ms));
+
+	/* Test fail on status read */
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_STATUS);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->perform_calib(ms, 1));
+	zassert_equal(range, ms->current_range);
+	zassert_equal(rate, ms->drv->get_data_rate(ms));
+
+	/* Test fail on data not ready */
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	bmi_emul_set_reg(emul, BMI260_STATUS, 0);
+	zassert_equal(EC_ERROR_TIMEOUT, ms->drv->perform_calib(ms, 1));
+	zassert_equal(range, ms->current_range);
+	zassert_equal(rate, ms->drv->get_data_rate(ms));
+
+	/*
+	 * Setup data status ready for rest of the test. Gyroscope calibration
+	 * should check DRDY_GYR bit, but current driver check only for ACC.
+	 */
+	bmi_emul_set_reg(emul, BMI260_STATUS,
+			 BMI260_DRDY_ACC | BMI260_DRDY_GYR);
+
+	/* Test fail on data read */
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_GYR_X_L_G);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->perform_calib(ms, 1));
+	zassert_equal(range, ms->current_range);
+	zassert_equal(rate, ms->drv->get_data_rate(ms));
+
+	/* Test fail on setting offset */
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_OFFSET_EN_GYR98);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->perform_calib(ms, 1));
+	zassert_equal(range, ms->current_range);
+	zassert_equal(rate, ms->drv->get_data_rate(ms));
+
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test successful offset compenastion */
+	zassert_equal(EC_SUCCESS, ms->drv->perform_calib(ms, 1));
+	zassert_equal(range, ms->current_range);
+	zassert_equal(rate, ms->drv->get_data_rate(ms));
+	get_emul_gyr_offset(emul, ret_off);
+	/*
+	 * Depending on used range, gyroscope values may be up to 4 bits
+	 * more accurate then offset value resolution.
+	 */
+	compare_int3v_eps(exp_off, ret_off, 32);
+}
+
+/**
+ * A custom fake to use with the `init_rom_map` mock that returns the
+ * value of `addr`
+ */
+static const void *init_rom_map_addr_passthru(const void *addr, int size)
+{
+	return addr;
+}
+
+/** Test init function of BMI260 accelerometer and gyroscope sensors */
+ZTEST_USER(bmi260, test_bmi_init)
+{
+	struct motion_sensor_t *ms_acc, *ms_gyr;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data;
+
+	common_data = emul_bmi_get_i2c_common_data(emul);
+	ms_acc = &motion_sensors[BMI_ACC_SENSOR_ID];
+	ms_gyr = &motion_sensors[BMI_GYR_SENSOR_ID];
+
+	/* The mock should return whatever is passed in to its addr param */
+	RESET_FAKE(init_rom_map);
+	init_rom_map_fake.custom_fake = init_rom_map_addr_passthru;
+
+	bmi_init_emul();
+}
+
+/** Data for custom emulator read function used in FIFO test */
+struct fifo_func_data {
+	uint16_t interrupts;
+};
+
+/**
+ * Custom emulator read function used in FIFO test. It sets interrupt registers
+ * to value passed as additional data. It sets interrupt registers to 0 after
+ * access.
+ */
+static int emul_fifo_func(const struct emul *emul, int reg, uint8_t *val,
+			  int byte, void *data)
+{
+	struct fifo_func_data *d = data;
+
+	if (reg + byte == BMI260_INT_STATUS_0) {
+		bmi_emul_set_reg(emul, BMI260_INT_STATUS_0,
+				 d->interrupts & 0xff);
+		d->interrupts &= 0xff00;
+	} else if (reg + byte == BMI260_INT_STATUS_1) {
+		bmi_emul_set_reg(emul, BMI260_INT_STATUS_1,
+				 (d->interrupts >> 8) & 0xff);
+		d->interrupts &= 0xff;
+	}
+
+	return 1;
+}
+
+/**
+ * Run irq handler on accelerometer sensor and check if committed data in FIFO
+ * match what was set in FIFO frames in emulator.
+ */
+static void check_fifo_f(struct motion_sensor_t *ms_acc,
+			 struct motion_sensor_t *ms_gyr,
+			 struct bmi_emul_frame *frame, int acc_range,
+			 int gyr_range, int line)
+{
+	struct ec_response_motion_sensor_data vector;
+	struct bmi_emul_frame *f_acc, *f_gyr;
+	uint32_t event = BMI_INT_EVENT;
+	uint16_t size;
+	intv3_t exp_v;
+	intv3_t ret_v;
+
+	/* Find first frame of acc and gyr type */
+	f_acc = frame;
+	while (f_acc != NULL && !(f_acc->type & BMI_EMUL_FRAME_ACC)) {
+		f_acc = f_acc->next;
+	}
+
+	f_gyr = frame;
+	while (f_gyr != NULL && !(f_gyr->type & BMI_EMUL_FRAME_GYR)) {
+		f_gyr = f_gyr->next;
+	}
+
+	/* Read FIFO in driver */
+	zassert_equal(EC_SUCCESS, ms_acc->drv->irq_handler(ms_acc, &event),
+		      "Failed to read FIFO in irq handler, line %d", line);
+
+	/* Read all data committed to FIFO */
+	while (motion_sense_fifo_read(sizeof(vector), 1, &vector, &size)) {
+		/* Ignore timestamp frames */
+		if (vector.flags == MOTIONSENSE_SENSOR_FLAG_TIMESTAMP) {
+			continue;
+		}
+
+		/* Check acclerometer frames */
+		if (ms_acc - motion_sensors == vector.sensor_num) {
+			if (f_acc == NULL) {
+				zassert_unreachable(
+					"Not expected acclerometer data in FIFO, line %d",
+					line);
+			}
+
+			convert_int3v_int16(vector.data, ret_v);
+			drv_acc_to_emul(ret_v, acc_range, ret_v);
+			exp_v[0] = f_acc->acc_x;
+			exp_v[1] = f_acc->acc_y;
+			exp_v[2] = f_acc->acc_z;
+			compare_int3v_f(exp_v, ret_v, V_EPS, line);
+			f_acc = f_acc->next;
+		}
+
+		/* Check gyroscope frames */
+		if (ms_gyr - motion_sensors == vector.sensor_num) {
+			if (f_gyr == NULL) {
+				zassert_unreachable(
+					"Not expected gyroscope data in FIFO, line %d",
+					line);
+			}
+
+			convert_int3v_int16(vector.data, ret_v);
+			drv_gyr_to_emul(ret_v, gyr_range, ret_v);
+			exp_v[0] = f_gyr->gyr_x;
+			exp_v[1] = f_gyr->gyr_y;
+			exp_v[2] = f_gyr->gyr_z;
+			compare_int3v_f(exp_v, ret_v, V_EPS, line);
+			f_gyr = f_gyr->next;
+		}
+	}
+
+	/* Skip frames of different type at the end */
+	while (f_acc != NULL && !(f_acc->type & BMI_EMUL_FRAME_ACC)) {
+		f_acc = f_acc->next;
+	}
+
+	while (f_gyr != NULL && !(f_gyr->type & BMI_EMUL_FRAME_GYR)) {
+		f_gyr = f_gyr->next;
+	}
+
+	/* All frames are readed */
+	zassert_is_null(f_acc, "Not all accelerometer frames are read, line %d",
+			line);
+	zassert_is_null(f_gyr, "Not all gyroscope frames are read, line %d",
+			line);
+}
+#define check_fifo(ms_acc, ms_gyr, frame, acc_range, gyr_range) \
+	check_fifo_f(ms_acc, ms_gyr, frame, acc_range, gyr_range, __LINE__)
+
+/** Test irq handler of accelerometer sensor */
+ZTEST_USER(bmi260, test_bmi_acc_fifo)
+{
+	struct motion_sensor_t *ms, *ms_gyr;
+	struct fifo_func_data func_data;
+	struct bmi_emul_frame f[3];
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data;
+	int gyr_range = 125;
+	int acc_range = 2;
+	int event;
+
+	common_data = emul_bmi_get_i2c_common_data(emul);
+	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
+	ms_gyr = &motion_sensors[BMI_GYR_SENSOR_ID];
+
+	bmi_init_emul();
+
+	/* Need to be set to collect all data in FIFO */
+	ms->oversampling_ratio = 1;
+	ms_gyr->oversampling_ratio = 1;
+	/* Only BMI event should be handled */
+	event = 0x1234 & ~BMI_INT_EVENT;
+	zassert_equal(EC_ERROR_NOT_HANDLED, ms->drv->irq_handler(ms, &event),
+		      NULL);
+
+	event = BMI_INT_EVENT;
+
+	/* Test fail to read interrupt status registers */
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_INT_STATUS_0);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->irq_handler(ms, &event));
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_INT_STATUS_1);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->irq_handler(ms, &event));
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test no interrupt */
+	bmi_emul_set_reg(emul, BMI260_INT_STATUS_0, 0);
+	bmi_emul_set_reg(emul, BMI260_INT_STATUS_1, 0);
+
+	/* Enable sensor FIFO */
+	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, 50000, 0));
+
+	/* Trigger irq handler and check results */
+	check_fifo(ms, ms_gyr, NULL, acc_range, gyr_range);
+
+	/* Set custom function for FIFO test */
+	i2c_common_emul_set_read_func(common_data, emul_fifo_func, &func_data);
+	/* Set range */
+	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, acc_range, 0));
+	zassert_equal(EC_SUCCESS, ms_gyr->drv->set_range(ms_gyr, gyr_range, 0),
+		      NULL);
+	/* Setup single accelerometer frame */
+	f[0].type = BMI_EMUL_FRAME_ACC;
+	f[0].acc_x = BMI_EMUL_1G / 10;
+	f[0].acc_y = BMI_EMUL_1G / 20;
+	f[0].acc_z = -(int)BMI_EMUL_1G / 30;
+	f[0].next = NULL;
+	bmi_emul_append_frame(emul, f);
+	/* Setup interrupts register */
+	func_data.interrupts = BMI260_FWM_INT;
+
+	/* Trigger irq handler and check results */
+	check_fifo(ms, ms_gyr, f, acc_range, gyr_range);
+
+	/* Setup second accelerometer frame */
+	f[1].type = BMI_EMUL_FRAME_ACC;
+	f[1].acc_x = -(int)BMI_EMUL_1G / 40;
+	f[1].acc_y = BMI_EMUL_1G / 50;
+	f[1].acc_z = BMI_EMUL_1G / 60;
+	f[0].next = &(f[1]);
+	f[1].next = NULL;
+	bmi_emul_append_frame(emul, f);
+	/* Setup interrupts register */
+	func_data.interrupts = BMI260_FWM_INT;
+
+	/* Trigger irq handler and check results */
+	check_fifo(ms, ms_gyr, f, acc_range, gyr_range);
+
+	/* Enable sensor FIFO */
+	zassert_equal(EC_SUCCESS, ms_gyr->drv->set_data_rate(ms_gyr, 50000, 0),
+		      NULL);
+
+	/* Setup first gyroscope frame (after two accelerometer frames) */
+	f[2].type = BMI_EMUL_FRAME_GYR;
+	f[2].gyr_x = -(int)BMI_EMUL_125_DEG_S / 100;
+	f[2].gyr_y = BMI_EMUL_125_DEG_S / 200;
+	f[2].gyr_z = BMI_EMUL_125_DEG_S / 300;
+	f[1].next = &(f[2]);
+	f[2].next = NULL;
+	bmi_emul_append_frame(emul, f);
+	/* Setup interrupts register */
+	func_data.interrupts = BMI260_FWM_INT;
+
+	/* Trigger irq handler and check results */
+	check_fifo(ms, ms_gyr, f, acc_range, gyr_range);
+
+	/* Setup second accelerometer frame to by gyroscope frame too */
+	f[1].type |= BMI_EMUL_FRAME_GYR;
+	f[1].gyr_x = -(int)BMI_EMUL_125_DEG_S / 300;
+	f[1].gyr_y = BMI_EMUL_125_DEG_S / 400;
+	f[1].gyr_z = BMI_EMUL_125_DEG_S / 500;
+	bmi_emul_append_frame(emul, f);
+	/* Setup interrupts register */
+	func_data.interrupts = BMI260_FWM_INT;
+
+	/* Trigger irq handler and check results */
+	check_fifo(ms, ms_gyr, f, acc_range, gyr_range);
+
+	/* Skip frame should be ignored by driver */
+	bmi_emul_set_skipped_frames(emul, 8);
+	bmi_emul_append_frame(emul, f);
+	/* Setup interrupts register */
+	func_data.interrupts = BMI260_FWM_INT;
+
+	/* Trigger irq handler and check results */
+	check_fifo(ms, ms_gyr, f, acc_range, gyr_range);
+
+	/* Setup second frame as an config frame */
+	f[1].type = BMI_EMUL_FRAME_CONFIG;
+	/* Indicate that accelerometer range changed */
+	f[1].config = 0x1;
+	bmi_emul_append_frame(emul, f);
+	/* Setup interrupts register */
+	func_data.interrupts = BMI260_FWM_INT;
+
+	/* Trigger irq handler and check results */
+	check_fifo(ms, ms_gyr, f, acc_range, gyr_range);
+
+	/* Remove custom emulator read function */
+	i2c_common_emul_set_read_func(common_data, NULL, NULL);
+}
+
+/** Test irq handler of gyroscope sensor */
+ZTEST_USER(bmi260, test_bmi_gyr_fifo)
+{
+	struct motion_sensor_t *ms;
+	uint32_t event;
+
+	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
+
+	/* Interrupt shuldn't be triggered for gyroscope motion sense */
+	event = BMI_INT_EVENT;
+	zassert_equal(EC_ERROR_NOT_HANDLED, ms->drv->irq_handler(ms, &event),
+		      NULL);
+}
+
+ZTEST_USER(bmi260, test_unsupported_configs)
+{
+	/*
+	 * This test checks that we properly handle passing in invalid sensor
+	 * types or attempting unsupported operations on certain sensor types.
+	 */
+
+	struct motion_sensor_t ms_fake;
+
+	/* Part 1:
+	 * Setting offset on anything that is not an accel or gyro is an error.
+	 * Make a copy of the accelerometer motion sensor struct and modify its
+	 * type to magnetometer for this test.
+	 */
+	memcpy(&ms_fake, &motion_sensors[BMI_ACC_SENSOR_ID], sizeof(ms_fake));
+	ms_fake.type = MOTIONSENSE_TYPE_MAG;
+
+	int16_t offset[3] = { 0 };
+	int ret =
+		ms_fake.drv->set_offset(&ms_fake, (const int16_t *)&offset, 0);
+	zassert_equal(
+		ret, EC_RES_INVALID_PARAM,
+		"Expected a return code of %d (EC_RES_INVALID_PARAM) but got %d",
+		EC_RES_INVALID_PARAM, ret);
+
+	/* Part 2:
+	 * Running a calibration on a magnetometer is also not supported.
+	 */
+	memcpy(&ms_fake, &motion_sensors[BMI_ACC_SENSOR_ID], sizeof(ms_fake));
+	ms_fake.type = MOTIONSENSE_TYPE_MAG;
+
+	ret = ms_fake.drv->perform_calib(&ms_fake, 1);
+	zassert_equal(
+		ret, EC_RES_INVALID_PARAM,
+		"Expected a return code of %d (EC_RES_INVALID_PARAM) but got %d",
+		EC_RES_INVALID_PARAM, ret);
+}
+
+ZTEST_USER(bmi260, test_interrupt_handler)
+{
+	/* The accelerometer interrupt handler simply sets an event flag for the
+	 * motion sensing task. Make sure that flag starts cleared, fire the
+	 * interrupt, and ensure the flag is set.
+	 */
+
+	atomic_t *mask;
+
+	mask = task_get_event_bitmap(TASK_ID_MOTIONSENSE);
+	zassert_true(mask != NULL,
+		     "Got a null pointer when getting event bitmap.");
+	zassert_true((*mask & CONFIG_ACCELGYRO_BMI260_INT_EVENT) == 0,
+		     "Event flag is set before firing interrupt");
+
+	bmi260_interrupt(0);
+
+	mask = task_get_event_bitmap(TASK_ID_MOTIONSENSE);
+	zassert_true(mask != NULL,
+		     "Got a null pointer when getting event bitmap.");
+	zassert_true(*mask & CONFIG_ACCELGYRO_BMI260_INT_EVENT,
+		     "Event flag is not set after firing interrupt");
+}
+
+ZTEST_USER(bmi260, test_bmi_init_chip_id)
+{
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bmi_get_i2c_common_data(emul);
+	struct motion_sensor_t *ms_acc = &motion_sensors[BMI_ACC_SENSOR_ID];
+
+	/* Part 1:
+	 * Error occurs while reading the chip ID
+	 */
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_CHIP_ID);
+	int ret = ms_acc->drv->init(ms_acc);
+
+	zassert_equal(ret, EC_ERROR_UNKNOWN,
+		      "Expected %d (EC_ERROR_UNKNOWN) but got %d",
+		      EC_ERROR_UNKNOWN, ret);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Part 2:
+	 * Test cases where the returned chip ID does not match what is
+	 * expected. This involves overriding values in the motion_sensor
+	 * struct, so make a copy first.
+	 */
+	struct motion_sensor_t ms_fake;
+
+	memcpy(&ms_fake, ms_acc, sizeof(ms_fake));
+
+	/* Part 2a: expecting MOTIONSENSE_CHIP_BMI220 but get BMI260's chip ID!
+	 */
+	bmi_emul_set_reg(emul, BMI260_CHIP_ID, BMI260_CHIP_ID_MAJOR);
+	ms_fake.chip = MOTIONSENSE_CHIP_BMI220;
+
+	ret = ms_fake.drv->init(&ms_fake);
+	zassert_equal(ret, EC_ERROR_ACCESS_DENIED,
+		      "Expected %d (EC_ERROR_ACCESS_DENIED) but got %d",
+		      EC_ERROR_ACCESS_DENIED, ret);
+
+	/* Part 2b: expecting MOTIONSENSE_CHIP_BMI260 but get BMI220's chip ID!
+	 */
+	bmi_emul_set_reg(emul, BMI260_CHIP_ID, BMI220_CHIP_ID_MAJOR);
+	ms_fake.chip = MOTIONSENSE_CHIP_BMI260;
+
+	ret = ms_fake.drv->init(&ms_fake);
+	zassert_equal(ret, EC_ERROR_ACCESS_DENIED,
+		      "Expected %d (EC_ERROR_ACCESS_DENIED) but got %d",
+		      EC_ERROR_ACCESS_DENIED, ret);
+
+	/* Part 2c: use an invalid expected chip */
+	ms_fake.chip = MOTIONSENSE_CHIP_MAX;
+
+	ret = ms_fake.drv->init(&ms_fake);
+	zassert_equal(ret, EC_ERROR_ACCESS_DENIED,
+		      "Expected %d (EC_ERROR_ACCESS_DENIED) but got %d",
+		      EC_ERROR_ACCESS_DENIED, ret);
+}
+
+/* Make an I2C emulator mock wrapped in FFF */
+FAKE_VALUE_FUNC(int, bmi_config_load_no_mapped_flash_mock_read_fn,
+		const struct emul *, int, uint8_t *, int, void *);
+struct i2c_common_emul_data *common_data;
+static int bmi_config_load_no_mapped_flash_mock_read_fn_helper(
+	const struct emul *emul, int reg, uint8_t *val, int bytes, void *data)
+{
+	if (reg == BMI260_INTERNAL_STATUS && val) {
+		/* We want to force-return a status of 'initialized' when this
+		 * is read.
+		 */
+		*val = BMI260_INIT_OK;
+		return 0;
+	}
+	/* For other registers, go through the normal emulator route */
+	return 1;
+}
+
+ZTEST_USER(bmi260, test_bmi_config_load_no_mapped_flash)
+{
+	/* Tests the situation where we load BMI config data when flash memory
+	 * is not mapped (basically what occurs when `init_rom_map()` in
+	 * `bmi_config_load()` returns NULL)
+	 */
+
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data;
+	struct motion_sensor_t *ms_acc = &motion_sensors[BMI_ACC_SENSOR_ID];
+	int ret, num_status_reg_reads;
+
+	common_data = emul_bmi_get_i2c_common_data(emul);
+
+	/* Force bmi_config_load() to have to manually copy from memory */
+	RESET_FAKE(init_rom_map);
+	init_rom_map_fake.return_val = NULL;
+
+	/* Force init_rom_copy() to succeed */
+	RESET_FAKE(init_rom_copy);
+	init_rom_copy_fake.return_val = 0;
+
+	/* Set proper chip ID and raise the INIT_OK flag to signal that config
+	 * succeeded.
+	 */
+	bmi_emul_set_reg(emul, BMI260_CHIP_ID, BMI260_CHIP_ID_MAJOR);
+	i2c_common_emul_set_read_func(
+		common_data, bmi_config_load_no_mapped_flash_mock_read_fn,
+		NULL);
+	RESET_FAKE(bmi_config_load_no_mapped_flash_mock_read_fn);
+	bmi_config_load_no_mapped_flash_mock_read_fn_fake.custom_fake =
+		bmi_config_load_no_mapped_flash_mock_read_fn_helper;
+
+	/* Part 1: successful path */
+	ret = ms_acc->drv->init(ms_acc);
+
+	zassert_equal(ret, EC_RES_SUCCESS, "Got %d but expected %d", ret,
+		      EC_RES_SUCCESS);
+
+	/* Check the number of times we accessed BMI260_INTERNAL_STATUS */
+	num_status_reg_reads = MOCK_COUNT_CALLS_WITH_ARG_VALUE(
+		bmi_config_load_no_mapped_flash_mock_read_fn_fake, 1,
+		BMI260_INTERNAL_STATUS);
+	zassert_equal(1, num_status_reg_reads,
+		      "Accessed status reg %d times but expected %d.",
+		      num_status_reg_reads, 1);
+
+	/* Part 2: write to `BMI260_INIT_ADDR_0` fails */
+	i2c_common_emul_set_write_fail_reg(common_data, BMI260_INIT_ADDR_0);
+
+	ret = ms_acc->drv->init(ms_acc);
+	zassert_equal(ret, EC_ERROR_INVALID_CONFIG, "Got %d but expected %d",
+		      ret, EC_ERROR_INVALID_CONFIG);
+
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Part 3: init_rom_copy() fails w/ a non-zero return code of 255. */
+	init_rom_copy_fake.return_val = 255;
+
+	ret = ms_acc->drv->init(ms_acc);
+	zassert_equal(ret, EC_ERROR_INVALID_CONFIG, "Got %d but expected %d",
+		      ret, EC_ERROR_INVALID_CONFIG);
+
+	init_rom_copy_fake.return_val = 0;
+
+	/* Part 4: write to `BMI260_INIT_DATA` fails */
+	i2c_common_emul_set_write_fail_reg(common_data, BMI260_INIT_DATA);
+
+	ret = ms_acc->drv->init(ms_acc);
+	zassert_equal(ret, EC_ERROR_INVALID_CONFIG, "Got %d but expected %d",
+		      ret, EC_ERROR_INVALID_CONFIG);
+
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Cleanup */
+	i2c_common_emul_set_read_func(common_data, NULL, NULL);
+}
+
+ZTEST_USER(bmi260, test_bmi_config_unsupported_chip)
+{
+	/* Test what occurs when we try to configure a chip that is
+	 * turned off in Kconfig (BMI220). This test assumes that
+	 * CONFIG_ACCELGYRO_BMI220 is NOT defined.
+	 */
+
+#if defined(CONFIG_ACCELGYRO_BMI220)
+#error "Test test_bmi_config_unsupported_chip will not work properly with " \
+	"CONFIG_ACCELGYRO_BMI220 defined."
+#endif
+
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data;
+	struct motion_sensor_t ms_fake;
+
+	common_data = emul_bmi_get_i2c_common_data(emul);
+
+	/* Set up struct and emaulator to be a BMI220 chip, which
+	 * `bmi_config_load()` does not support in the current configuration
+	 */
+
+	memcpy(&ms_fake, &motion_sensors[BMI_ACC_SENSOR_ID], sizeof(ms_fake));
+	ms_fake.chip = MOTIONSENSE_CHIP_BMI220;
+	bmi_emul_set_reg(emul, BMI260_CHIP_ID, BMI220_CHIP_ID_MAJOR);
+
+	int ret = ms_fake.drv->init(&ms_fake);
+
+	zassert_equal(ret, EC_ERROR_INVALID_CONFIG, "Expected %d but got %d",
+		      EC_ERROR_INVALID_CONFIG, ret);
+}
+
+ZTEST_USER(bmi260, test_init_config_read_failure)
+{
+	/* Test proper response to a failed read from the register
+	 * BMI260_INTERNAL_STATUS.
+	 */
+
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data;
+	struct motion_sensor_t *ms_acc = &motion_sensors[BMI_ACC_SENSOR_ID];
+	int ret;
+
+	common_data = emul_bmi_get_i2c_common_data(emul);
+
+	/* Set up i2c emulator and mocks */
+	bmi_emul_set_reg(emul, BMI260_CHIP_ID, BMI260_CHIP_ID_MAJOR);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_INTERNAL_STATUS);
+	RESET_FAKE(init_rom_map);
+	init_rom_map_fake.custom_fake = init_rom_map_addr_passthru;
+
+	ret = ms_acc->drv->init(ms_acc);
+
+	zassert_equal(ret, EC_ERROR_INVALID_CONFIG, "Expected %d but got %d",
+		      EC_ERROR_INVALID_CONFIG, ret);
+}
+
+/* Mock read function and counter used to test the timeout when
+ * waiting for the chip to initialize
+ */
+static int timeout_test_status_reg_access_count;
+static int status_timeout_mock_read_fn(const struct emul *emul, int reg,
+				       uint8_t *val, int bytes, void *data)
+{
+	if (reg == BMI260_INTERNAL_STATUS && val) {
+		/* We want to force-return a non-OK status each time */
+		timeout_test_status_reg_access_count++;
+		*val = BMI260_INIT_ERR;
+		return 0;
+	} else {
+		return 1;
+	}
+}
+
+ZTEST_USER(bmi260, test_init_config_status_timeout)
+{
+	/* We allow up to 15 tries to get a successful BMI260_INIT_OK
+	 * value from the BMI260_INTERNAL_STATUS register. Make sure
+	 * we properly handle the case where the chip is not initialized
+	 * before the timeout.
+	 */
+
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data;
+	struct motion_sensor_t *ms_acc = &motion_sensors[BMI_ACC_SENSOR_ID];
+	int ret;
+
+	common_data = emul_bmi_get_i2c_common_data(emul);
+
+	/* Set up i2c emulator and mocks */
+	bmi_emul_set_reg(emul, BMI260_CHIP_ID, BMI260_CHIP_ID_MAJOR);
+	timeout_test_status_reg_access_count = 0;
+	i2c_common_emul_set_read_func(common_data, status_timeout_mock_read_fn,
+				      NULL);
+	RESET_FAKE(init_rom_map);
+	init_rom_map_fake.custom_fake = init_rom_map_addr_passthru;
+
+	ret = ms_acc->drv->init(ms_acc);
+
+	zassert_equal(timeout_test_status_reg_access_count, 15,
+		      "Expected %d attempts but counted %d", 15,
+		      timeout_test_status_reg_access_count);
+	zassert_equal(ret, EC_ERROR_INVALID_CONFIG, "Expected %d but got %d",
+		      EC_ERROR_INVALID_CONFIG, ret);
+}
+
+/**
+ * @brief Put the driver and emulator in to a consistent state before each test.
+ *
+ * @param arg Test fixture (unused)
+ */
+static void bmi260_test_before(void *arg)
+{
+	ARG_UNUSED(arg);
+
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data;
+	struct motion_sensor_t *ms_acc = &motion_sensors[BMI_ACC_SENSOR_ID];
+	struct motion_sensor_t *ms_gyr = &motion_sensors[BMI_GYR_SENSOR_ID];
+
+	common_data = emul_bmi_get_i2c_common_data(emul);
+
+	/* Reset I2C */
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_func(common_data, NULL, NULL);
+	i2c_common_emul_set_write_func(common_data, NULL, NULL);
+
+	/* Reset local fakes(s) */
+	RESET_FAKE(bmi_config_load_no_mapped_flash_mock_read_fn);
+
+	/* Clear rotation matrices */
+	ms_acc->rot_standard_ref = NULL;
+	ms_gyr->rot_standard_ref = NULL;
+
+	/* Set Chip ID register to BMI260 (required for init() to succeed) */
+	bmi_emul_set_reg(emul, BMI260_CHIP_ID, BMI260_CHIP_ID_MAJOR);
+}
+
+ZTEST_SUITE(bmi260, drivers_predicate_pre_main, NULL, bmi260_test_before, NULL,
+	    NULL);
diff --git a/zephyr/test/drivers/default/src/bmi_common.c b/zephyr/test/drivers/default/src/bmi_common.c
new file mode 100644
index 0000000000..bdd3999d65
--- /dev/null
+++ b/zephyr/test/drivers/default/src/bmi_common.c
@@ -0,0 +1,129 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "accelgyro_bmi_common.h"
+#include "emul/emul_bmi.h"
+#include "emul/emul_common_i2c.h"
+#include "i2c.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/fff.h>
+#include <zephyr/ztest.h>
+
+#define BMI_NODE DT_NODELABEL(accel_bmi160)
+#define BMI_ACC_SENSOR_ID SENSOR_ID(DT_NODELABEL(ms_bmi160_accel))
+
+FAKE_VALUE_FUNC(int, i2c_write_handler, const struct emul *, int, uint8_t, int,
+		void *);
+FAKE_VALUE_FUNC(int, i2c_read_handler, const struct emul *, int, uint8_t *, int,
+		void *);
+
+void bmi_common_before(void *f)
+{
+	ARG_UNUSED(f);
+
+	RESET_FAKE(i2c_write_handler);
+	RESET_FAKE(i2c_read_handler);
+}
+
+void bmi_common_after(void *f)
+{
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bmi_get_i2c_common_data(emul);
+	ARG_UNUSED(f);
+
+	motion_sensors[BMI_ACC_SENSOR_ID].type = MOTIONSENSE_TYPE_ACCEL;
+	i2c_common_emul_set_write_func(common_data, NULL, NULL);
+	i2c_common_emul_set_read_func(common_data, NULL, NULL);
+}
+
+ZTEST_SUITE(bmi_common, drivers_predicate_post_main, NULL, bmi_common_before,
+	    bmi_common_after, NULL);
+
+ZTEST(bmi_common, test_get_xyz_reg_mag)
+{
+	int reg;
+
+	motion_sensors[BMI_ACC_SENSOR_ID].type = MOTIONSENSE_TYPE_MAG;
+	reg = bmi_get_xyz_reg(&motion_sensors[BMI_ACC_SENSOR_ID]);
+
+	zassert_equal(BMI160_MAG_X_L_G, reg, "Expected %d, but got %d",
+		      BMI160_MAG_X_L_G, reg);
+
+	motion_sensors[BMI_ACC_SENSOR_ID].type = MOTIONSENSE_TYPE_PROX;
+	reg = bmi_get_xyz_reg(&motion_sensors[BMI_ACC_SENSOR_ID]);
+
+	zassert_equal(-1, reg, "Expected 0, but got %d", reg);
+}
+
+ZTEST(bmi_common, test_write16)
+{
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bmi_get_i2c_common_data(emul);
+
+	i2c_write_handler_fake.return_val = 0;
+	i2c_common_emul_set_write_func(common_data, i2c_write_handler, NULL);
+	zassert_ok(bmi_write16(
+		motion_sensors[BMI_ACC_SENSOR_ID].port,
+		motion_sensors[BMI_ACC_SENSOR_ID].i2c_spi_addr_flags, 0,
+		0x1234));
+	zassert_equal(2, i2c_write_handler_fake.call_count);
+	zassert_equal(0, i2c_write_handler_fake.arg1_history[0]);
+	zassert_equal(0, i2c_write_handler_fake.arg1_history[1]);
+	zassert_equal(0x34, i2c_write_handler_fake.arg2_history[0],
+		      "got 0x%02x", i2c_write_handler_fake.arg2_history[0]);
+	zassert_equal(0x12, i2c_write_handler_fake.arg2_history[1],
+		      "got 0x%02x", i2c_write_handler_fake.arg2_history[1]);
+	zassert_equal(1, i2c_write_handler_fake.arg3_history[0], "got %d",
+		      i2c_write_handler_fake.arg3_history[0]);
+	zassert_equal(2, i2c_write_handler_fake.arg3_history[1], "got %d",
+		      i2c_write_handler_fake.arg3_history[1]);
+}
+
+ZTEST(bmi_common, test_read32)
+{
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bmi_get_i2c_common_data(emul);
+	int data = 0;
+
+	i2c_read_handler_fake.return_val = 0;
+	i2c_common_emul_set_read_func(common_data, i2c_read_handler, NULL);
+	zassert_ok(
+		bmi_read32(motion_sensors[BMI_ACC_SENSOR_ID].port,
+			   motion_sensors[BMI_ACC_SENSOR_ID].i2c_spi_addr_flags,
+			   0, &data));
+	zassert_equal(4, i2c_read_handler_fake.call_count);
+	zassert_equal(0, i2c_read_handler_fake.arg1_history[0]);
+	zassert_equal(0, i2c_read_handler_fake.arg1_history[1]);
+	zassert_equal(0, i2c_read_handler_fake.arg1_history[2]);
+	zassert_equal(0, i2c_read_handler_fake.arg1_history[3]);
+	zassert_equal(0, i2c_read_handler_fake.arg3_history[0], "got %d",
+		      i2c_read_handler_fake.arg3_history[0]);
+	zassert_equal(1, i2c_read_handler_fake.arg3_history[1], "got %d",
+		      i2c_read_handler_fake.arg3_history[1]);
+	zassert_equal(2, i2c_read_handler_fake.arg3_history[2], "got %d",
+		      i2c_read_handler_fake.arg3_history[2]);
+	zassert_equal(3, i2c_read_handler_fake.arg3_history[3], "got %d",
+		      i2c_read_handler_fake.arg3_history[3]);
+}
+
+ZTEST(bmi_common, test_list_activities)
+{
+	struct bmi_drv_data_t *data =
+		BMI_GET_DATA(&motion_sensors[BMI_ACC_SENSOR_ID]);
+	uint32_t enabled = 0;
+	uint32_t disabled = 0;
+
+	data->enabled_activities = 0x12;
+	data->disabled_activities = 0x34;
+
+	zassert_ok(bmi_list_activities(&motion_sensors[BMI_ACC_SENSOR_ID],
+				       &enabled, &disabled));
+	zassert_equal(0x12, enabled);
+	zassert_equal(0x34, disabled);
+}
diff --git a/zephyr/test/drivers/default/src/charge_manager.c b/zephyr/test/drivers/default/src/charge_manager.c
new file mode 100644
index 0000000000..d5affff95e
--- /dev/null
+++ b/zephyr/test/drivers/default/src/charge_manager.c
@@ -0,0 +1,58 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "ec_commands.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/ztest.h>
+
+ZTEST_SUITE(charge_manager, drivers_predicate_post_main, NULL, NULL, NULL,
+	    NULL);
+
+/**
+ * Test the default implementation of board_fill_source_power_info(). The fill
+ * function should reset all the power info values. If the test binary overrides
+ * board_fill_source_power_info(), then this test can be removed.
+ */
+ZTEST_USER(charge_manager, test_default_fill_power_info)
+{
+	struct ec_response_usb_pd_power_info info = {
+		.meas = {
+			.voltage_now = 10,
+			.voltage_max = 10,
+			.current_max = 10,
+			.current_lim = 10,
+		},
+		.max_power = 10,
+	};
+
+	board_fill_source_power_info(0, &info);
+	zassert_equal(info.meas.voltage_now, 0);
+	zassert_equal(info.meas.voltage_max, 0);
+	zassert_equal(info.meas.current_max, 0);
+	zassert_equal(info.meas.current_lim, 0);
+	zassert_equal(info.max_power, 0);
+}
+
+/**
+ * Test the default implementation of board_charge_port_is_connected(). This
+ * function should always return 1 regardless of input.
+ */
+ZTEST_USER(charge_manager, test_default_charge_port_is_connected)
+{
+	zassert_true(board_charge_port_is_connected(-1));
+	zassert_true(board_charge_port_is_connected(0));
+	zassert_true(board_charge_port_is_connected(1));
+	zassert_true(board_charge_port_is_connected(500));
+}
+
+ZTEST_USER(charge_manager, test_default_charge_port_is_sink)
+{
+	zassert_true(board_charge_port_is_sink(-1));
+	zassert_true(board_charge_port_is_sink(0));
+	zassert_true(board_charge_port_is_sink(1));
+	zassert_true(board_charge_port_is_sink(500));
+}
diff --git a/zephyr/test/drivers/default/src/charge_ramp.c b/zephyr/test/drivers/default/src/charge_ramp.c
new file mode 100644
index 0000000000..3511b56001
--- /dev/null
+++ b/zephyr/test/drivers/default/src/charge_ramp.c
@@ -0,0 +1,59 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "charge_ramp.h"
+#include "system.h"
+#include "system_fake.h"
+#include "test/drivers/test_mocks.h"
+
+#include <zephyr/fff.h>
+#include <zephyr/ztest.h>
+
+static void charge_ramp_before(void *state)
+{
+	ARG_UNUSED(state);
+	RESET_FAKE(system_is_locked);
+}
+
+static void charge_ramp_after(void *state)
+{
+	ARG_UNUSED(state);
+	RESET_FAKE(system_is_locked);
+}
+
+/* Test ramping logic.
+ *
+ * Not testing BC1.2 chargers because driver tests should cover them.
+ */
+ZTEST_USER(charge_ramp, test_ramp)
+{
+	zassert_equal(chg_ramp_allowed(0, CHARGE_SUPPLIER_PD), 0);
+	zassert_equal(chg_ramp_max(0, CHARGE_SUPPLIER_PD, 1234), 0);
+
+	zassert_equal(chg_ramp_allowed(0, CHARGE_SUPPLIER_TYPEC), 0);
+	zassert_equal(chg_ramp_max(0, CHARGE_SUPPLIER_TYPEC, 1234), 0);
+
+	zassert_equal(chg_ramp_allowed(0, CHARGE_SUPPLIER_TYPEC_DTS), 1);
+	zassert_equal(chg_ramp_max(0, CHARGE_SUPPLIER_TYPEC_DTS, 1234), 1234);
+}
+
+/* Disable ramping in locked RO */
+ZTEST_USER(charge_ramp, test_ramp_locked)
+{
+	enum ec_image old_image = system_get_shrspi_image_copy();
+
+	system_set_shrspi_image_copy(EC_IMAGE_RO);
+	zassert_false(system_is_in_rw());
+
+	system_is_locked_fake.return_val = 1;
+
+	zassert_equal(chg_ramp_allowed(0, CHARGE_SUPPLIER_TYPEC_DTS), 0);
+
+	system_set_shrspi_image_copy(old_image);
+}
+
+ZTEST_SUITE(charge_ramp, NULL, NULL, charge_ramp_before, charge_ramp_after,
+	    NULL);
diff --git a/zephyr/test/drivers/default/src/charge_state_prevent_power_on.c b/zephyr/test/drivers/default/src/charge_state_prevent_power_on.c
new file mode 100644
index 0000000000..07e15ea1f6
--- /dev/null
+++ b/zephyr/test/drivers/default/src/charge_state_prevent_power_on.c
@@ -0,0 +1,90 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_state.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/ztest.h>
+
+/* Test external variable defined in charge_state_v2 */
+extern int charge_prevent_power_on_automatic_power_on;
+
+struct charge_state_prevent_power_on_fixture {
+	struct charge_state_data charge_state_backup;
+	int automatic_power_on;
+};
+
+static void *setup(void)
+{
+	static struct charge_state_prevent_power_on_fixture fixture;
+
+	return &fixture;
+}
+
+static void before(void *f)
+{
+	struct charge_state_prevent_power_on_fixture *fixture = f;
+
+	/* Backup the current state */
+	fixture->charge_state_backup = *charge_get_status();
+	fixture->automatic_power_on =
+		charge_prevent_power_on_automatic_power_on;
+
+	/* Reset the automatic_power_on global */
+	charge_prevent_power_on_automatic_power_on = 1;
+}
+
+static void after(void *f)
+{
+	struct charge_state_prevent_power_on_fixture *fixture = f;
+
+	/* Restore the state from 'before' */
+	*charge_get_status() = fixture->charge_state_backup;
+	charge_prevent_power_on_automatic_power_on =
+		fixture->automatic_power_on;
+}
+
+ZTEST_SUITE(charge_state_prevent_power_on, drivers_predicate_post_main, setup,
+	    before, after, NULL);
+
+ZTEST(charge_state_prevent_power_on, test_allow_power_on)
+{
+	struct batt_params *params = &charge_get_status()->batt;
+
+	/* Force a call to refresh the battery parameters */
+	params->is_present = BP_NOT_SURE;
+	/* Set the charge state to be high enough */
+	params->state_of_charge =
+		CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON;
+
+	/* Verify that we can power on when the power button was pressed */
+	zassert_false(charge_prevent_power_on(true));
+}
+
+ZTEST(charge_state_prevent_power_on, test_low_charge)
+{
+	struct batt_params *params = &charge_get_status()->batt;
+
+	/* Force a low charge state */
+	params->state_of_charge =
+		CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON - 1;
+
+	/* Verify that we cannot power on during an automatic power-on */
+	zassert_true(charge_prevent_power_on(false));
+}
+
+ZTEST(charge_state_prevent_power_on, test_consuming_full_input_current)
+{
+	struct batt_params *params = &charge_get_status()->batt;
+
+	params->state_of_charge = 50;
+	zassert_true(charge_is_consuming_full_input_current());
+
+	params->state_of_charge = 0;
+	zassert_false(charge_is_consuming_full_input_current());
+
+	params->state_of_charge = 100;
+	zassert_false(charge_is_consuming_full_input_current());
+}
diff --git a/zephyr/test/drivers/default/src/chipset.c b/zephyr/test/drivers/default/src/chipset.c
new file mode 100644
index 0000000000..89ba761c23
--- /dev/null
+++ b/zephyr/test/drivers/default/src/chipset.c
@@ -0,0 +1,101 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "chipset.h"
+#include "console.h"
+#include "test/drivers/test_state.h"
+
+#include <stdint.h>
+
+#include <zephyr/fff.h>
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+#include <ap_power/ap_power.h>
+#include <ap_power/ap_power_events.h>
+
+ZTEST(chipset, test_get_ap_reset_stats__bad_pointers)
+{
+	zassert_equal(EC_ERROR_INVAL, get_ap_reset_stats(NULL, 0, NULL));
+}
+
+ZTEST(chipset, test_get_ap_reset_stats__happy_path)
+{
+	struct ap_reset_log_entry reset_log_entries[4];
+	uint32_t actual_reset_count, reset_count;
+
+	memset(reset_log_entries, 0, sizeof(reset_log_entries));
+
+	/* Report two AP resets */
+	report_ap_reset(CHIPSET_RESET_AP_WATCHDOG);
+	report_ap_reset(CHIPSET_RESET_HANG_REBOOT);
+
+	zassert_equal(EC_SUCCESS,
+		      get_ap_reset_stats(reset_log_entries,
+					 ARRAY_SIZE(reset_log_entries),
+					 &reset_count));
+
+	/* Check the reset causes. The reset entry log is not a FIFO, so we get
+	 * the last two empty slots followed by the two we triggered above.
+	 */
+	zassert_equal(0, reset_log_entries[0].reset_cause);
+	zassert_equal(0, reset_log_entries[1].reset_cause);
+	zassert_equal(CHIPSET_RESET_AP_WATCHDOG,
+		      reset_log_entries[2].reset_cause);
+	zassert_equal(CHIPSET_RESET_HANG_REBOOT,
+		      reset_log_entries[3].reset_cause);
+
+	/* Check reset count */
+	actual_reset_count = test_chipset_get_ap_resets_since_ec_boot();
+	zassert_equal(actual_reset_count, reset_count,
+		      "Found %d resets, expected %d", reset_count,
+		      actual_reset_count);
+}
+
+ZTEST(chipset, test_console_cmd_apreset)
+{
+	struct ap_reset_log_entry reset_log_entries[4];
+	uint32_t reset_count;
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "apreset"));
+
+	/* Make sure an AP reset happened. The expected reset log entry is at
+	 * index 3 because we read out 3 empty slots first.
+	 */
+	zassert_ok(get_ap_reset_stats(reset_log_entries,
+				      ARRAY_SIZE(reset_log_entries),
+				      &reset_count));
+
+	zassert_equal(CHIPSET_RESET_CONSOLE_CMD,
+		      reset_log_entries[3].reset_cause);
+}
+
+ZTEST(chipset, test_console_cmd_apshutdown)
+{
+	struct ap_reset_log_entry reset_log_entries[4];
+	uint32_t reset_count;
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "apshutdown"));
+
+	/* Make sure an AP reset happened. The expected reset log entry is at
+	 * index 3 because we read out 3 empty slots first.
+	 */
+	zassert_ok(get_ap_reset_stats(reset_log_entries,
+				      ARRAY_SIZE(reset_log_entries),
+				      &reset_count));
+
+	zassert_equal(CHIPSET_SHUTDOWN_CONSOLE_CMD,
+		      reset_log_entries[3].reset_cause);
+}
+
+static void reset(void *arg)
+{
+	ARG_UNUSED(arg);
+
+	test_chipset_corrupt_reset_log_checksum();
+	init_reset_log();
+}
+
+ZTEST_SUITE(chipset, drivers_predicate_post_main, NULL, reset, reset, NULL);
diff --git a/zephyr/test/drivers/default/src/console.c b/zephyr/test/drivers/default/src/console.c
new file mode 100644
index 0000000000..c5148baf76
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console.c
@@ -0,0 +1,240 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "builtin/stdio.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "test/drivers/test_state.h"
+#include "uart.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/shell/shell_dummy.h>
+#include <zephyr/ztest.h>
+
+ZTEST_USER(console, test_printf_overflow)
+{
+	char buffer[10];
+
+	zassert_equal(-EC_ERROR_OVERFLOW,
+		      crec_snprintf(buffer, 4, "1234567890"), NULL);
+	zassert_equal(0, strcmp(buffer, "123"), "got '%s'", buffer);
+	zassert_equal(-EC_ERROR_OVERFLOW,
+		      crec_snprintf(buffer, 4, "%%%%%%%%%%"), NULL);
+	zassert_equal(0, strcmp(buffer, "%%%"), "got '%s'", buffer);
+}
+
+/* This test is identical to test_buf_notify_null in
+ * test/console_edit.c. Please keep them in sync to verify that
+ * uart_console_read_buffer works identically in legacy EC and zephyr.
+ */
+ZTEST_USER(console, test_buf_notify_null)
+{
+	char buffer[100];
+	uint16_t write_count;
+	size_t consumed_count;
+
+	/* Flush the console buffer before we start. */
+	zassert_ok(uart_console_read_buffer_init(), NULL);
+
+	/* Write a nul char to the buffer. */
+	consumed_count = console_buf_notify_chars("ab\0c", 4);
+
+	/* Check if all bytes were consumed by console buffer */
+	zassert_equal(consumed_count, 4, "got %d", consumed_count);
+
+	/* Check if the nul is present in the buffer. */
+	zassert_ok(uart_console_read_buffer_init(), NULL);
+	zassert_ok(uart_console_read_buffer(CONSOLE_READ_RECENT, buffer,
+					    sizeof(buffer), &write_count),
+		   NULL);
+	zassert_equal(0, strncmp(buffer, "abc", 4), "got '%s'", buffer);
+	zassert_equal(write_count, 4, "got %d", write_count);
+}
+
+ZTEST_USER(console, test_console_read_buffer_invalid_type)
+{
+	char buffer[100];
+	uint16_t write_count;
+	uint8_t invalid_type = CONSOLE_READ_RECENT + 1;
+
+	/* Flush the console buffer before we start. */
+	zassert_ok(uart_console_read_buffer_init(), NULL);
+
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      uart_console_read_buffer(invalid_type, buffer,
+					       sizeof(buffer), &write_count),
+		      NULL);
+}
+
+ZTEST_USER(console, test_console_read_buffer_size_zero)
+{
+	char buffer[100];
+	uint16_t write_count;
+
+	/* Flush the console buffer before we start. */
+	zassert_ok(uart_console_read_buffer_init(), NULL);
+
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      uart_console_read_buffer(CONSOLE_READ_RECENT, buffer, 0,
+					       &write_count),
+		      NULL);
+}
+
+ZTEST_USER(console, test_uart_buffer_full)
+{
+	zassert_false(uart_buffer_full(), NULL);
+}
+
+static const char *large_string =
+	"This is a very long string, it will cause a buffer flush at "
+	"some point while printing to the shell. Long long text. Blah "
+	"blah. Long long text. Blah blah. Long long text. Blah blah.";
+ZTEST_USER(console, test_shell_fprintf_full)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+	const char *outbuffer;
+	size_t buffer_size;
+
+	zassert_true(strlen(large_string) >=
+			     shell_zephyr->fprintf_ctx->buffer_size,
+		     "large_string is too short, fix test.");
+
+	shell_backend_dummy_clear_output(shell_zephyr);
+	shell_fprintf(shell_zephyr, SHELL_NORMAL, "%s", large_string);
+
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+	zassert_true(strncmp(outbuffer, large_string, strlen(large_string)) ==
+			     0,
+		     "Invalid console output %s", outbuffer);
+}
+
+ZTEST_USER(console, test_cprint_too_big)
+{
+	zassert_true(strlen(large_string) >= CONFIG_SHELL_PRINTF_BUFF_SIZE,
+		     "buffer is too short, fix test.");
+
+	zassert_equal(cprintf(CC_COMMAND, "%s", large_string),
+		      -EC_ERROR_OVERFLOW, NULL);
+}
+
+ZTEST_USER(console, test_cmd_chan_invalid_mask)
+{
+	zassert_equal(EC_ERROR_PARAM1,
+		      shell_execute_cmd(get_ec_shell(), "chan foobar"));
+}
+
+ZTEST_USER(console, test_cmd_chan_set)
+{
+	char cmd[100];
+
+	zassert_true(crec_snprintf(cmd, sizeof(cmd), "chan %d",
+				   CC_MASK(CC_ACCEL)) > 0);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), cmd));
+
+	zassert_false(console_channel_is_disabled(CC_COMMAND));
+	zassert_false(console_channel_is_disabled(CC_ACCEL));
+	zassert_true(console_channel_is_disabled(CC_CHARGER));
+}
+
+ZTEST_USER(console, test_cmd_chan_by_name)
+{
+	const char name[] = "charger";
+	char cmd[100];
+
+	console_channel_enable(name);
+
+	/* Toggle 'charger' off */
+	zassert_true(crec_snprintf(cmd, sizeof(cmd), "chan %s", name) > 0,
+		     "Failed to compose chan %s command.", name);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), cmd),
+		   "Failed to execute chan %s command.", name);
+	zassert_true(console_channel_is_disabled(CC_CHARGER),
+		     "Failed to enable %s channel.", name);
+
+	/* Toggle 'charger' on */
+	zassert_true(crec_snprintf(cmd, sizeof(cmd), "chan %s", name) > 0,
+		     "Failed to compose chan %s command.", name);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), cmd),
+		   "Failed to execute chan %s command.", name);
+	zassert_false(console_channel_is_disabled(CC_CHARGER),
+		      "Failed to disable %s channel.", name);
+}
+
+ZTEST_USER(console, test_cmd_chan_show)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+	const char *outbuffer;
+	size_t buffer_size;
+	char cmd[100];
+
+	zassert_true(crec_snprintf(cmd, sizeof(cmd), "chan %d",
+				   CC_MASK(CC_ACCEL)) > 0);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), cmd));
+	shell_backend_dummy_clear_output(shell_zephyr);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "chan"));
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+
+	zassert_true(
+		strstr(outbuffer,
+		       "\r\n # Mask     E Channel\r\n 0 00000001 * command\r\n"
+		       " 1 00000002 * accel\r\n 2 00000004   charger\r\n") !=
+			NULL,
+		"Invalid console output %s", outbuffer);
+}
+
+ZTEST_USER(console, test_cmd_chan_save_restore)
+{
+	char cmd[100];
+
+	zassert_true(crec_snprintf(cmd, sizeof(cmd), "chan %d",
+				   CC_MASK(CC_ACCEL)) > 0);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), cmd));
+
+	zassert_false(console_channel_is_disabled(CC_COMMAND));
+	zassert_false(console_channel_is_disabled(CC_ACCEL));
+	zassert_true(console_channel_is_disabled(CC_CHARGER));
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "chan save"));
+	zassert_true(crec_snprintf(cmd, sizeof(cmd), "chan %d",
+				   CC_MASK(CC_ACCEL) | CC_MASK(CC_CHARGER)) >
+		     0);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), cmd));
+
+	zassert_false(console_channel_is_disabled(CC_COMMAND));
+	zassert_false(console_channel_is_disabled(CC_ACCEL));
+	zassert_false(console_channel_is_disabled(CC_CHARGER));
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "chan restore"));
+
+	zassert_false(console_channel_is_disabled(CC_COMMAND));
+	zassert_false(console_channel_is_disabled(CC_ACCEL));
+	zassert_true(console_channel_is_disabled(CC_CHARGER));
+}
+
+ZTEST_SUITE(console, drivers_predicate_post_main, NULL, NULL, NULL, NULL);
+
+ZTEST_USER(console_pre, test_cmd_chan_save_restore)
+{
+	/* These are not mentioned in ec-console in native_posix.overlay. */
+	zassert_false(console_channel_is_disabled(CC_COMMAND));
+	zassert_false(console_channel_is_disabled(CC_ACCEL));
+	zassert_false(console_channel_is_disabled(CC_CHARGER));
+	/* These are disabled in ec-console in native_posix.overlay. */
+	zassert_true(console_channel_is_disabled(CC_EVENTS));
+	zassert_true(console_channel_is_disabled(CC_LPC));
+	zassert_true(console_channel_is_disabled(CC_HOSTCMD));
+
+	/* Disable an invalid channel, and verify nothing changed. */
+	console_channel_disable("not_a_valid_channel");
+
+	zassert_false(console_channel_is_disabled(CC_COMMAND));
+	zassert_false(console_channel_is_disabled(CC_ACCEL));
+	zassert_false(console_channel_is_disabled(CC_CHARGER));
+	zassert_true(console_channel_is_disabled(CC_EVENTS));
+	zassert_true(console_channel_is_disabled(CC_LPC));
+	zassert_true(console_channel_is_disabled(CC_HOSTCMD));
+}
+
+ZTEST_SUITE(console_pre, drivers_predicate_pre_main, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/drivers/default/src/console_cmd/CMakeLists.txt b/zephyr/test/drivers/default/src/console_cmd/CMakeLists.txt
new file mode 100644
index 0000000000..b4ed741430
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/CMakeLists.txt
@@ -0,0 +1,46 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_sources(app PRIVATE
+	adc.c
+	battery.c
+	cbi.c
+	charge_manager.c
+	charge_state.c
+	charger.c
+	chargen.c
+	accelinit.c
+	accelinfo.c
+	accelspoof.c
+	accelrate.c
+	accelrange.c
+	accelread.c
+	accelres.c
+	button.c
+	cutoff.c
+	ec_features.c
+	gpio.c
+	i2c_portmap.c
+	md.c
+	hcdebug.c
+	hibdelay.c
+	hostevent.c
+	panic_output.c
+	port80.c
+	powerindebug.c
+	power_button.c
+	pwr_avg.c
+	rtc.c
+	rw.c
+	shared_mem.c
+	sleepmask.c
+	sleeptimeout.c
+	switch.c
+	sysinfo.c
+	tcpci_dump.c
+	usb_pd_console.c
+	vboot_hash.c
+	version.c
+	waitms.c
+)
\ No newline at end of file
diff --git a/zephyr/test/drivers/default/src/console_cmd/accelinfo.c b/zephyr/test/drivers/default/src/console_cmd/accelinfo.c
new file mode 100644
index 0000000000..aac63c01b7
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/accelinfo.c
@@ -0,0 +1,55 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "config.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "test/drivers/test_state.h"
+#include "timer.h"
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+static void console_cmd_accelinfo_after(void *fixture)
+{
+	ARG_UNUSED(fixture);
+	shell_execute_cmd(get_ec_shell(), "accelinfo off");
+}
+
+ZTEST_SUITE(console_cmd_accelinfo, drivers_predicate_post_main, NULL, NULL,
+	    console_cmd_accelinfo_after, NULL);
+
+ZTEST_USER(console_cmd_accelinfo, test_too_many_args)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "accelinfo arg1 arg2");
+
+	zassert_equal(rv, EC_ERROR_PARAM_COUNT, "Expected %d, but got %d",
+		      EC_ERROR_PARAM_COUNT, rv);
+}
+
+ZTEST_USER(console_cmd_accelinfo, test_print_once)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "accelinfo"));
+}
+
+ZTEST_USER(console_cmd_accelinfo, test_invalid_arg)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "accelinfo bar");
+
+	zassert_equal(rv, EC_ERROR_PARAM1, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+}
+
+ZTEST_USER(console_cmd_accelinfo, test_enable_disable)
+{
+	/*
+	 * There's no way to verify what is being printed to the console yet, so
+	 * just assert that the command executed and returned 0.
+	 */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "accelinfo on"));
+	k_msleep(CONFIG_MOTION_MIN_SENSE_WAIT_TIME * MSEC * 2);
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "accelinfo off"));
+}
diff --git a/zephyr/test/drivers/default/src/console_cmd/accelinit.c b/zephyr/test/drivers/default/src/console_cmd/accelinit.c
new file mode 100644
index 0000000000..2633c05f58
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/accelinit.c
@@ -0,0 +1,93 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "accelgyro.h"
+#include "console.h"
+#include "motion_sense.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/fff.h>
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+FAKE_VALUE_FUNC(int, mock_init, struct motion_sensor_t *);
+
+struct console_cmd_accelinit_fixture {
+	const struct accelgyro_drv *sensor_0_drv;
+	struct accelgyro_drv mock_drv;
+};
+
+static void *console_cmd_accelinit_setup(void)
+{
+	static struct console_cmd_accelinit_fixture fixture = {
+		.mock_drv = {
+			.init = mock_init,
+		},
+	};
+	fixture.sensor_0_drv = motion_sensors[0].drv;
+
+	return &fixture;
+}
+
+static void console_cmd_accelinit_before(void *fixture)
+{
+	ARG_UNUSED(fixture);
+	RESET_FAKE(mock_init);
+	FFF_RESET_HISTORY();
+}
+static void console_cmd_accelinit_after(void *fixture)
+{
+	struct console_cmd_accelinit_fixture *this = fixture;
+
+	motion_sensors[0].drv = this->sensor_0_drv;
+	motion_sensors[0].drv->init(&motion_sensors[0]);
+}
+
+ZTEST_SUITE(console_cmd_accelinit, drivers_predicate_post_main,
+	    console_cmd_accelinit_setup, console_cmd_accelinit_before,
+	    console_cmd_accelinit_after, NULL);
+
+ZTEST_USER(console_cmd_accelinit, test_invalid_sensor_num)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "accelinit f");
+	zassert_equal(EC_ERROR_PARAM1, rv, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "accelinit -1");
+	zassert_equal(EC_ERROR_PARAM1, rv, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "accelinit 100");
+	zassert_equal(EC_ERROR_PARAM1, rv, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+}
+
+ZTEST_USER(console_cmd_accelinit, test_state_was_set)
+{
+	motion_sensors[0].state = SENSOR_INIT_ERROR;
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "accelinit 0"));
+	zassert_equal(SENSOR_INITIALIZED, motion_sensors[0].state,
+		      "Expected %d, but got %d", SENSOR_INITIALIZED,
+		      motion_sensors[0].state);
+}
+
+ZTEST_USER_F(console_cmd_accelinit, test_fail_3_times)
+{
+	mock_init_fake.return_val = 1;
+	motion_sensors[0].drv = &fixture->mock_drv;
+	motion_sensors[0].state = SENSOR_INITIALIZED;
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "accelinit 0"));
+	zassert_equal(3, mock_init_fake.call_count,
+		      "Expected 3 calls, but got %d",
+		      mock_init_fake.call_count);
+	zassert_equal(SENSOR_INIT_ERROR, motion_sensors[0].state,
+		      "Expected %d, but got %d", SENSOR_INIT_ERROR,
+		      motion_sensors[0].state);
+}
diff --git a/zephyr/test/drivers/default/src/console_cmd/accelrange.c b/zephyr/test/drivers/default/src/console_cmd/accelrange.c
new file mode 100644
index 0000000000..04ec7e6004
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/accelrange.c
@@ -0,0 +1,118 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "driver/accel_bma2x2.h"
+#include "ec_commands.h"
+#include "emul/emul_bma255.h"
+#include "emul/emul_common_i2c.h"
+#include "i2c.h"
+#include "motion_sense.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+#define EMUL_NODE DT_NODELABEL(bma_emul)
+
+#define BMA_ORD DT_DEP_ORD(EMUL_LABEL)
+
+static void console_cmd_accelrange_after(void *fixture)
+{
+	const struct emul *emul = EMUL_DT_GET(EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bma_get_i2c_common_data(emul);
+
+	ARG_UNUSED(fixture);
+	shell_execute_cmd(get_ec_shell(), "accelrange 0 2");
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+}
+
+ZTEST_SUITE(console_cmd_accelrange, drivers_predicate_post_main, NULL, NULL,
+	    console_cmd_accelrange_after, NULL);
+
+ZTEST_USER(console_cmd_accelrange, test_num_args)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "accelrange");
+	zassert_equal(rv, EC_ERROR_PARAM_COUNT, "Expected %d, but got %d",
+		      EC_ERROR_PARAM_COUNT, rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "accelrange 0 1 2 3");
+	zassert_equal(rv, EC_ERROR_PARAM_COUNT, "Expected %d, but got %d",
+		      EC_ERROR_PARAM_COUNT, rv);
+}
+
+ZTEST_USER(console_cmd_accelrange, test_bad_sensor_num)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "accelrange t");
+	zassert_equal(rv, EC_ERROR_PARAM1, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "accelrange -1");
+	zassert_equal(rv, EC_ERROR_PARAM1, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "accelrange 100");
+	zassert_equal(rv, EC_ERROR_PARAM1, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+}
+
+ZTEST_USER(console_cmd_accelrange, test_print_range)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "accelrange 0"));
+}
+
+ZTEST_USER(console_cmd_accelrange, test_set_invalid_range)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "accelrange 0 t");
+
+	zassert_equal(rv, EC_ERROR_PARAM2, "Expected %d, but got %d",
+		      EC_ERROR_PARAM2, rv);
+}
+
+ZTEST_USER(console_cmd_accelrange, test_set_range_round_up_implicit)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "accelrange 0 3"));
+	zassert_equal(motion_sensors[0].current_range, 4,
+		      "Expected 4, but got %d",
+		      motion_sensors[0].current_range);
+}
+
+ZTEST_USER(console_cmd_accelrange, test_set_range_round_up_explicit)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "accelrange 0 3 1"));
+	zassert_equal(motion_sensors[0].current_range, 4,
+		      "Expected 4, but got %d",
+		      motion_sensors[0].current_range);
+}
+
+ZTEST_USER(console_cmd_accelrange, test_set_range_round_down)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "accelrange 0 5 0"));
+	zassert_equal(motion_sensors[0].current_range, 4,
+		      "Expected 4, but got %d",
+		      motion_sensors[0].current_range);
+}
+
+ZTEST_USER(console_cmd_accelrange, test_i2c_error)
+{
+	const struct emul *emul = EMUL_DT_GET(EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bma_get_i2c_common_data(emul);
+	int rv;
+
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  BMA2x2_RANGE_SELECT_ADDR);
+
+	rv = shell_execute_cmd(get_ec_shell(), "accelrange 0 3");
+	zassert_equal(rv, EC_ERROR_PARAM2, "Expected %d, but got %d",
+		      EC_ERROR_PARAM2, rv);
+}
diff --git a/zephyr/test/drivers/default/src/console_cmd/accelrate.c b/zephyr/test/drivers/default/src/console_cmd/accelrate.c
new file mode 100644
index 0000000000..3a5b2cd9bf
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/accelrate.c
@@ -0,0 +1,104 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "ec_commands.h"
+#include "motion_sense.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+static int original_sensor_0_s0_config_odr;
+
+static void *console_cmd_accelrate_setup(void)
+{
+	original_sensor_0_s0_config_odr =
+		motion_sensors[0].config[SENSOR_CONFIG_EC_S0].odr;
+	return NULL;
+}
+
+static void console_cmd_accelrate_after(void *state)
+{
+	ARG_UNUSED(state);
+	motion_sensors[0].config[SENSOR_CONFIG_EC_S0].odr =
+		original_sensor_0_s0_config_odr;
+}
+
+ZTEST_SUITE(console_cmd_accelrate, drivers_predicate_post_main,
+	    console_cmd_accelrate_setup, NULL, console_cmd_accelrate_after,
+	    NULL);
+
+ZTEST_USER(console_cmd_accelrate, test_bad_arg_count)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "accelrate");
+	zassert_equal(EC_ERROR_PARAM_COUNT, rv, "Expected %d, but got %d",
+		      EC_ERROR_PARAM_COUNT, rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "accelrate 1 2 3 4");
+	zassert_equal(EC_ERROR_PARAM_COUNT, rv, "Expected %d, but got %d",
+		      EC_ERROR_PARAM_COUNT, rv);
+}
+
+ZTEST_USER(console_cmd_accelrate, test_invalid_sensor_num)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "accelrate f");
+	zassert_equal(EC_ERROR_PARAM1, rv, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "accelrate -1");
+	zassert_equal(EC_ERROR_PARAM1, rv, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "accelrate 100");
+	zassert_equal(EC_ERROR_PARAM1, rv, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+}
+
+ZTEST_USER(console_cmd_accelrate, test_print_rate)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "accelrate 0"));
+}
+
+ZTEST_USER(console_cmd_accelrate, test_bad_rate_value)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "accelrate 0 f");
+
+	zassert_equal(EC_ERROR_PARAM2, rv, "Expected %d, but got %d",
+		      EC_ERROR_PARAM2, rv);
+}
+
+ZTEST_USER(console_cmd_accelrate, test_set_ap_rate)
+{
+	test_set_chipset_to_s0();
+
+	motion_sensors[0].config[SENSOR_CONFIG_EC_S0].odr = 0;
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "accelrate 0 100"));
+	zassert_equal(100 | ROUND_UP_FLAG,
+		      motion_sensors[0].config[SENSOR_CONFIG_EC_S0].odr,
+		      "Expected %d, but got %d", 100 | ROUND_UP_FLAG,
+		      motion_sensors[0].config[SENSOR_CONFIG_EC_S0].odr);
+
+	/* Try explicit round up value: 1 */
+	motion_sensors[0].config[SENSOR_CONFIG_EC_S0].odr = 0;
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "accelrate 0 100 1"),
+		   NULL);
+	zassert_equal(100 | ROUND_UP_FLAG,
+		      motion_sensors[0].config[SENSOR_CONFIG_EC_S0].odr,
+		      "Expected %d, but got %d", 100 | ROUND_UP_FLAG,
+		      motion_sensors[0].config[SENSOR_CONFIG_EC_S0].odr);
+
+	motion_sensors[0].config[SENSOR_CONFIG_EC_S0].odr = 0;
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "accelrate 0 100 0"),
+		   NULL);
+	zassert_equal(100, motion_sensors[0].config[SENSOR_CONFIG_EC_S0].odr,
+		      "Expected %d, but got %d", 100 | ROUND_UP_FLAG,
+		      motion_sensors[0].config[SENSOR_CONFIG_EC_S0].odr);
+}
diff --git a/zephyr/test/drivers/default/src/console_cmd/accelread.c b/zephyr/test/drivers/default/src/console_cmd/accelread.c
new file mode 100644
index 0000000000..e622faf58f
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/accelread.c
@@ -0,0 +1,124 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "accelgyro.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "motion_sense.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/fff.h>
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+FAKE_VALUE_FUNC(int, mock_read, const struct motion_sensor_t *, int *);
+FAKE_VALUE_FUNC(int, mock_set_data_rate, const struct motion_sensor_t *, int,
+		int);
+FAKE_VALUE_FUNC(int, mock_get_data_rate, const struct motion_sensor_t *);
+
+struct console_cmd_accelread_fixture {
+	const struct accelgyro_drv *sensor_0_drv;
+	struct accelgyro_drv mock_drv;
+};
+
+static void *console_cmd_accelread_setup(void)
+{
+	static struct console_cmd_accelread_fixture fixture = {
+		.mock_drv = {
+			.read = mock_read,
+			/*
+			 * Data rate functions are required so that motion_sense
+			 * task doesn't segfault.
+			 */
+			.set_data_rate = mock_set_data_rate,
+			.get_data_rate = mock_get_data_rate,
+		},
+	};
+	fixture.sensor_0_drv = motion_sensors[0].drv;
+
+	return &fixture;
+}
+
+static void console_cmd_accelread_before(void *fixture)
+{
+	ARG_UNUSED(fixture);
+	RESET_FAKE(mock_read);
+	RESET_FAKE(mock_set_data_rate);
+	RESET_FAKE(mock_get_data_rate);
+	FFF_RESET_HISTORY();
+}
+
+static void console_cmd_accelread_after(void *fixture)
+{
+	struct console_cmd_accelread_fixture *this = fixture;
+
+	motion_sensors[0].drv = this->sensor_0_drv;
+}
+
+ZTEST_SUITE(console_cmd_accelread, drivers_predicate_pre_main,
+	    console_cmd_accelread_setup, console_cmd_accelread_before,
+	    console_cmd_accelread_after, NULL);
+
+ZTEST_USER(console_cmd_accelread, test_too_few_arguments)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "accelread");
+
+	zassert_equal(EC_ERROR_PARAM_COUNT, rv, "Expected %d, but got %d",
+		      EC_ERROR_PARAM_COUNT, rv);
+}
+
+ZTEST_USER(console_cmd_accelread, test_invalid_sensor_num)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "accelread f");
+	zassert_equal(EC_ERROR_PARAM1, rv, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "accelread -1");
+	zassert_equal(EC_ERROR_PARAM1, rv, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "accelread 100");
+	zassert_equal(EC_ERROR_PARAM1, rv, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+}
+
+static struct console_cmd_accelread_fixture *current_fixture;
+
+int mock_read_call_super(const struct motion_sensor_t *s, int *v)
+{
+	return current_fixture->sensor_0_drv->read(s, v);
+}
+
+ZTEST_USER_F(console_cmd_accelread, test_read)
+{
+	current_fixture = fixture;
+	mock_read_fake.custom_fake = mock_read_call_super;
+	mock_get_data_rate_fake.return_val = 100;
+	motion_sensors[0].drv = &fixture->mock_drv;
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "accelread 0"));
+	zassert_equal(1, mock_read_fake.call_count,
+		      "Expected only 1 call to read, but got %d",
+		      mock_read_fake.call_count);
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "accelread 0 2"));
+	zassert_equal(3, mock_read_fake.call_count,
+		      "Expected only 3 call to read, but got %d",
+		      mock_read_fake.call_count);
+}
+
+ZTEST_USER_F(console_cmd_accelread, test_read_fail)
+{
+	mock_read_fake.return_val = 1;
+	motion_sensors[0].drv = &fixture->mock_drv;
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "accelread 0"));
+	zassert_equal(1, mock_read_fake.call_count,
+		      "Expected only 1 call to read, but got %d",
+		      mock_read_fake.call_count);
+}
diff --git a/zephyr/test/drivers/default/src/console_cmd/accelres.c b/zephyr/test/drivers/default/src/console_cmd/accelres.c
new file mode 100644
index 0000000000..21c0075b0f
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/accelres.c
@@ -0,0 +1,127 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "accelgyro.h"
+#include "console.h"
+#include "driver/accel_bma2x2.h"
+#include "ec_commands.h"
+#include "motion_sense.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/fff.h>
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+FAKE_VALUE_FUNC(int, set_resolution, const struct motion_sensor_t *, int, int);
+
+struct console_cmd_accelres_fixture {
+	const struct accelgyro_drv *sensor_0_drv;
+	struct accelgyro_drv mock_drv;
+};
+
+void *console_cmd_accelres_setup(void)
+{
+	static struct console_cmd_accelres_fixture fixture = {
+		.mock_drv = {
+			.set_resolution = set_resolution,
+		},
+	};
+
+	fixture.sensor_0_drv = motion_sensors[0].drv;
+
+	return &fixture;
+}
+
+void console_cmd_accelres_before(void *fixture)
+{
+	ARG_UNUSED(fixture);
+	RESET_FAKE(set_resolution);
+	FFF_RESET_HISTORY();
+}
+
+void console_cmd_accelres_after(void *fixture)
+{
+	struct console_cmd_accelres_fixture *this = fixture;
+
+	motion_sensors[0].drv = this->sensor_0_drv;
+}
+
+ZTEST_SUITE(console_cmd_accelres, drivers_predicate_post_main,
+	    console_cmd_accelres_setup, NULL, console_cmd_accelres_after, NULL);
+
+ZTEST_USER(console_cmd_accelres, test_too_few_args)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "accelres");
+
+	zassert_equal(EC_ERROR_PARAM_COUNT, rv, "Expected %d, but got %d",
+		      EC_ERROR_PARAM_COUNT, rv);
+}
+
+ZTEST_USER(console_cmd_accelres, test_too_many_args)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "accelres 1 2 3 4");
+
+	zassert_equal(EC_ERROR_PARAM_COUNT, rv, "Expected %d, but got %d",
+		      EC_ERROR_PARAM_COUNT, rv);
+}
+
+ZTEST_USER(console_cmd_accelres, test_invalid_sensor_num)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "accelres f");
+	zassert_equal(EC_ERROR_PARAM1, rv, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "accelres -1");
+	zassert_equal(EC_ERROR_PARAM1, rv, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "accelres 100");
+	zassert_equal(EC_ERROR_PARAM1, rv, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+}
+
+ZTEST_USER(console_cmd_accelres, test_print_res)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "accelres 0"));
+}
+
+ZTEST_USER(console_cmd_accelres, test_set_res__invalid_data)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "accelres 0 f");
+
+	zassert_equal(EC_ERROR_PARAM2, rv, "Expected %d, but got %d",
+		      EC_ERROR_PARAM2, rv);
+}
+
+ZTEST_USER(console_cmd_accelres, test_set_res__no_setter)
+{
+	int resolution;
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "accelres 0 4"));
+	resolution = motion_sensors[0].drv->get_resolution(&motion_sensors[0]);
+	zassert_equal(BMA2x2_RESOLUTION, resolution, "Expected %d, but got %d",
+		      BMA2x2_RESOLUTION, resolution);
+}
+
+ZTEST_USER_F(console_cmd_accelres, test_set_res__bad_res_value)
+{
+	int rv;
+
+	set_resolution_fake.return_val = EC_ERROR_INVAL;
+	motion_sensors[0].drv = &fixture->mock_drv;
+	rv = shell_execute_cmd(get_ec_shell(), "accelres 0 0");
+	zassert_equal(EC_ERROR_PARAM2, rv, "Expected %d, but got %d",
+		      EC_ERROR_PARAM2, rv);
+}
+
+ZTEST_USER(console_cmd_accelres, test_invalid_rounding_arg)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "accelres 0 12 f");
+
+	zassert_equal(EC_ERROR_PARAM3, rv, "Expected %d, but got %d",
+		      EC_ERROR_PARAM3, rv);
+}
diff --git a/zephyr/test/drivers/default/src/console_cmd/accelspoof.c b/zephyr/test/drivers/default/src/console_cmd/accelspoof.c
new file mode 100644
index 0000000000..fe11525531
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/accelspoof.c
@@ -0,0 +1,97 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "ec_commands.h"
+#include "motion_sense.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+static void console_cmd_accelspoof_after(void *fixture)
+{
+	ARG_UNUSED(fixture);
+	shell_execute_cmd(get_ec_shell(), "accelspoof 0 off");
+	motion_sensors[0].spoof_xyz[0] = 0;
+	motion_sensors[0].spoof_xyz[1] = 0;
+	motion_sensors[0].spoof_xyz[2] = 0;
+}
+
+ZTEST_SUITE(console_cmd_accelspoof, drivers_predicate_post_main, NULL, NULL,
+	    console_cmd_accelspoof_after, NULL);
+
+ZTEST_USER(console_cmd_accelspoof, test_too_few_args)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "accelspoof");
+
+	zassert_equal(rv, EC_ERROR_PARAM_COUNT, "Expected %d, but got %d",
+		      EC_ERROR_PARAM_COUNT, rv);
+}
+
+ZTEST_USER(console_cmd_accelspoof, test_invalid_sensor_id)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "accelspoof -1");
+	zassert_equal(rv, EC_ERROR_PARAM1, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "accelspoof 100");
+	zassert_equal(rv, EC_ERROR_PARAM1, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+}
+
+ZTEST_USER(console_cmd_accelspoof, test_print_mode)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "accelspoof 0"));
+}
+
+ZTEST_USER(console_cmd_accelspoof, test_invalid_boolean)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "accelspoof 0 bar");
+
+	zassert_equal(rv, EC_ERROR_PARAM2, "Expected %d, but got %d",
+		      EC_ERROR_PARAM2, rv);
+}
+
+ZTEST_USER(console_cmd_accelspoof, test_enable_disable)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "accelspoof 0 on"));
+	zassert_true(motion_sensors[0].flags & MOTIONSENSE_FLAG_IN_SPOOF_MODE,
+		     NULL);
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "accelspoof 0 off"));
+	zassert_false(motion_sensors[0].flags & MOTIONSENSE_FLAG_IN_SPOOF_MODE,
+		      NULL);
+}
+
+ZTEST_USER(console_cmd_accelspoof, test_wrong_num_axis_args)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "accelspoof 0 on 1");
+
+	zassert_equal(rv, EC_ERROR_PARAM_COUNT, "Expected %d, but got %d",
+		      EC_ERROR_PARAM_COUNT, rv);
+}
+
+ZTEST_USER(console_cmd_accelspoof, test_enable_explicit_values)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "accelspoof 0 on 1 2 3"),
+		   NULL);
+	zassert_equal(1, motion_sensors[0].spoof_xyz[0]);
+	zassert_equal(2, motion_sensors[0].spoof_xyz[1]);
+	zassert_equal(3, motion_sensors[0].spoof_xyz[2]);
+}
+
+ZTEST_USER(console_cmd_accelspoof, test_enable_implicit_values)
+{
+	motion_sensors[0].raw_xyz[0] = 4;
+	motion_sensors[0].raw_xyz[1] = 5;
+	motion_sensors[0].raw_xyz[2] = 6;
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "accelspoof 0 on"));
+	zassert_equal(4, motion_sensors[0].spoof_xyz[0]);
+	zassert_equal(5, motion_sensors[0].spoof_xyz[1]);
+	zassert_equal(6, motion_sensors[0].spoof_xyz[2]);
+}
diff --git a/zephyr/test/drivers/default/src/console_cmd/adc.c b/zephyr/test/drivers/default/src/console_cmd/adc.c
new file mode 100644
index 0000000000..754932a9e8
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/adc.c
@@ -0,0 +1,43 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "ec_commands.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+/* Default adc command, lists out channels */
+ZTEST_USER(console_cmd_adc, test_adc_noname)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "adc"),
+		   "Failed default print");
+}
+
+/* adc with named channels */
+ZTEST_USER(console_cmd_adc, test_adc_named_channels)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "adc 0"),
+		   "Failed to get charger adc channel.");
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "adc 2"),
+		   "Failed to get ddr-soc adc channel.");
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "adc 3"),
+		   "Failed to get fan adc channel.");
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "adc 5"),
+		   "Failed to get psys adc channel.");
+}
+
+/* adc with unknown channel */
+ZTEST_USER(console_cmd_adc, test_adc_wrong_name)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "adc 9");
+
+	zassert_equal(rv, EC_ERROR_PARAM1, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+}
+
+ZTEST_SUITE(console_cmd_adc, NULL, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/drivers/default/src/console_cmd/battery.c b/zephyr/test/drivers/default/src/console_cmd/battery.c
new file mode 100644
index 0000000000..f5fa78d684
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/battery.c
@@ -0,0 +1,90 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery_smart.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_smart_battery.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+struct console_cmd_battery_fixture {
+	const struct emul *emul;
+	struct i2c_common_emul_data *i2c_emul;
+};
+
+static void *console_cmd_battery_setup(void)
+{
+	static struct console_cmd_battery_fixture fixture = {
+		.emul = EMUL_DT_GET(DT_NODELABEL(battery)),
+	};
+
+	fixture.i2c_emul = emul_smart_battery_get_i2c_common_data(fixture.emul);
+
+	return &fixture;
+}
+
+static void console_cmd_battery_after(void *f)
+{
+	struct console_cmd_battery_fixture *fixture = f;
+
+	i2c_common_emul_set_read_fail_reg(fixture->i2c_emul,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+}
+
+/* Default battery command */
+ZTEST_USER(console_cmd_battery, test_battery_default)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "battery"),
+		   "Failed default print");
+}
+
+ZTEST_USER_F(console_cmd_battery, test_battery_status_i2c_error)
+{
+	/* Force a failure on the battery i2c write to SB_BATTERY_STATUS */
+	i2c_common_emul_set_read_fail_reg(fixture->i2c_emul, SB_BATTERY_STATUS);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "battery"),
+		   "Failed default print");
+}
+
+/* Battery command with repeat */
+ZTEST_USER(console_cmd_battery, test_battery_repeat)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "battery 2"),
+		   "Failed default print");
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "battery 8"),
+		   "Failed default print");
+}
+
+/* Battery command with repeat and sleep */
+ZTEST_USER(console_cmd_battery, test_battery_repeat_sleep)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "battery 2 400"),
+		   "Failed default print");
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "battery 8 200"),
+		   "Failed default print");
+}
+
+/* Battery command with invalid repeat and sleep */
+ZTEST_USER(console_cmd_battery, test_battery_bad_repeat_sleep)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "battery fish 400");
+
+	zassert_equal(rv, EC_ERROR_INVAL, "Expected %d, but got %d",
+		      EC_ERROR_INVAL, rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "battery 2 fish");
+
+	zassert_equal(rv, EC_ERROR_INVAL, "Expected %d, but got %d",
+		      EC_ERROR_INVAL, rv);
+}
+
+ZTEST_SUITE(console_cmd_battery, drivers_predicate_post_main,
+	    console_cmd_battery_setup, NULL, console_cmd_battery_after, NULL);
diff --git a/zephyr/test/drivers/default/src/console_cmd/button.c b/zephyr/test/drivers/default/src/console_cmd/button.c
new file mode 100644
index 0000000000..0df137e90b
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/button.c
@@ -0,0 +1,67 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "ec_commands.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+ZTEST_USER(console_cmd_button, test_button_no_arg)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "button");
+
+	zassert_equal(EC_ERROR_PARAM_COUNT, rv, "Expected %d, returned %d",
+		      EC_ERROR_PARAM_COUNT, rv);
+}
+
+ZTEST_USER(console_cmd_button, test_button_vup)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "button vup a");
+
+	zassert_equal(EC_ERROR_PARAM2, rv, "Expected %d, returned %d",
+		      EC_ERROR_PARAM2, rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "button vup 50");
+
+	zassert_ok(rv, "Expected %d, returned %d", EC_SUCCESS, rv);
+}
+
+ZTEST_USER(console_cmd_button, test_button_vdown)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "button vdown a");
+
+	zassert_equal(EC_ERROR_PARAM2, rv, "Expected %d, returned %d",
+		      EC_ERROR_PARAM2, rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "button vdown 50");
+
+	zassert_ok(rv, "Expected %d, returned %d", EC_SUCCESS, rv);
+}
+
+ZTEST_USER(console_cmd_button, test_button_rec)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "button rec 50");
+
+	if (IS_ENABLED(CONFIG_DEDICATED_RECOVERY_BUTTON)) {
+		zassert_ok(rv, "Expected %d, returned %d", EC_SUCCESS, rv);
+	} else {
+		/* Recovery button does not exist */
+		zassert_equal(EC_ERROR_PARAM1, rv, "Expected %d, returned %d",
+			      EC_ERROR_PARAM1, rv);
+	}
+}
+
+ZTEST_SUITE(console_cmd_button, NULL, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/drivers/default/src/console_cmd/cbi.c b/zephyr/test/drivers/default/src/console_cmd/cbi.c
new file mode 100644
index 0000000000..297431657e
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/cbi.c
@@ -0,0 +1,81 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+static void set_wp(bool value)
+{
+	const struct gpio_dt_spec *wp = GPIO_DT_FROM_NODELABEL(gpio_wp_l);
+
+	gpio_pin_set_dt(wp, value);
+}
+
+static void before(void *unused)
+{
+	/* Ensure eeprom is ready */
+	set_wp(false);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "cbi remove 42 init"),
+		   NULL);
+}
+
+static void after(void *unused)
+{
+	/* re-enable WP */
+	set_wp(true);
+}
+
+ZTEST_SUITE(console_cmd_cbi, drivers_predicate_post_main, NULL, before, after,
+	    NULL);
+
+ZTEST_USER(console_cmd_cbi, test_base)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "cbi"), NULL);
+}
+
+ZTEST_USER(console_cmd_cbi, test_wp)
+{
+	set_wp(true);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "cbi remove 42"), NULL);
+}
+
+ZTEST_USER(console_cmd_cbi, test_remove)
+{
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "cbi remove"), NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "cbi remove 42"), NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "cbi remove abc"), NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "cbi remove 42 1"), NULL);
+}
+
+ZTEST_USER(console_cmd_cbi, test_set)
+{
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "cbi set"), NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "cbi set 10"), NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "cbi set 11 1"), NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "cbi set 12 1 4"), NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "cbi set 13 1 4 4"),
+		   NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "cbi set 14 1 10"), NULL);
+}
+
+ZTEST_USER(console_cmd_cbi, test_extra)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(),
+				     "cbi remove 42 skip_write"),
+		   NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "cbi remove 42 init"),
+		   NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(),
+				     "cbi remove 42 init skip_write"),
+		   NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(),
+				     "cbi remove 42 skip_write init"),
+		   NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "cbi remove 42 extra"),
+		   NULL);
+}
diff --git a/zephyr/test/drivers/default/src/console_cmd/charge_manager.c b/zephyr/test/drivers/default/src/console_cmd/charge_manager.c
new file mode 100644
index 0000000000..698db8b316
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/charge_manager.c
@@ -0,0 +1,118 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "console.h"
+#include "emul/emul_isl923x.h"
+#include "emul/tcpc/emul_tcpci.h"
+#include "emul/tcpc/emul_tcpci_partner_snk.h"
+#include "tcpm/tcpci.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+struct console_cmd_charge_manager_fixture {
+	struct tcpci_partner_data sink_5v_3a;
+	struct tcpci_snk_emul_data sink_ext;
+	const struct emul *tcpci_emul;
+	const struct emul *charger_emul;
+};
+
+static void *console_cmd_charge_manager_setup(void)
+{
+	static struct console_cmd_charge_manager_fixture test_fixture;
+
+	/* Get references for the emulators */
+	test_fixture.tcpci_emul = EMUL_GET_USBC_BINDING(0, tcpc);
+	test_fixture.charger_emul = EMUL_GET_USBC_BINDING(0, chg);
+
+	/* Initialized the sink to request 5V and 3A */
+	tcpci_partner_init(&test_fixture.sink_5v_3a, PD_REV20);
+	test_fixture.sink_5v_3a.extensions = tcpci_snk_emul_init(
+		&test_fixture.sink_ext, &test_fixture.sink_5v_3a, NULL);
+	test_fixture.sink_ext.pdo[1] =
+		PDO_FIXED(5000, 3000, PDO_FIXED_UNCONSTRAINED);
+
+	return &test_fixture;
+}
+
+static void console_cmd_charge_manager_after(void *state)
+{
+	struct console_cmd_charge_manager_fixture *fixture = state;
+
+	shell_execute_cmd(get_ec_shell(), "chgoverride -1");
+	disconnect_sink_from_port(fixture->tcpci_emul);
+}
+
+ZTEST_SUITE(console_cmd_charge_manager, drivers_predicate_post_main,
+	    console_cmd_charge_manager_setup, NULL,
+	    console_cmd_charge_manager_after, NULL);
+
+/**
+ * Test the chgsup (charge supplier info) command. This command only prints to
+ * console some information which is not yet possible to verify. So just check
+ * that the console command ran successfully.
+ */
+ZTEST_USER(console_cmd_charge_manager, test_chgsup)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "chgsup"));
+}
+
+/**
+ * Test chgoverride command with no arguments. This should just print the
+ * current override port.
+ */
+ZTEST_USER(console_cmd_charge_manager, test_chgoverride_missing_port)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "chgoverride"));
+}
+
+ZTEST_USER(console_cmd_charge_manager, test_chgoverride_off_from_off)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "chgoverride -1"));
+	zassert_equal(charge_manager_get_override(), OVERRIDE_OFF);
+}
+
+ZTEST_USER(console_cmd_charge_manager, test_chgoverride_disable_from_off)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "chgoverride -2"));
+	zassert_equal(charge_manager_get_override(), OVERRIDE_DONT_CHARGE,
+		      NULL);
+}
+
+ZTEST_USER(console_cmd_charge_manager, test_chgoverride_0_from_off)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "chgoverride 0"));
+	zassert_equal(charge_manager_get_override(), 0);
+}
+
+ZTEST_USER_F(console_cmd_charge_manager, test_chgoverride_0_from_sink)
+{
+	test_set_chipset_to_g3();
+	k_sleep(K_SECONDS(1));
+
+	/* Set chipset to ON, this will set TCPM to DRP */
+	test_set_chipset_to_s0();
+
+	/* TODO(b/214401892): Check why need to give time TCPM to spin */
+	k_sleep(K_SECONDS(1));
+
+	connect_sink_to_port(&fixture->sink_5v_3a, fixture->tcpci_emul,
+			     fixture->charger_emul);
+	zassert_equal(shell_execute_cmd(get_ec_shell(), "chgoverride 0"),
+		      EC_ERROR_INVAL, NULL);
+}
+
+ZTEST_USER(console_cmd_charge_manager, test_chgoverride_invalid_port)
+{
+	char cmd[256];
+
+	zassert_true(sprintf(cmd, "chgoverride %d", CHARGE_PORT_COUNT) > 0,
+		     NULL);
+	zassert_equal(shell_execute_cmd(get_ec_shell(), cmd), EC_ERROR_PARAM1,
+		      NULL);
+}
diff --git a/zephyr/test/drivers/default/src/console_cmd/charge_state.c b/zephyr/test/drivers/default/src/console_cmd/charge_state.c
new file mode 100644
index 0000000000..851725af36
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/charge_state.c
@@ -0,0 +1,291 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_state.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+ZTEST_USER(console_cmd_charge_state, test_idle_too_few_args)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "chgstate idle");
+	zassert_equal(rv, EC_ERROR_PARAM_COUNT, "Expected %d, but got %d",
+		      EC_ERROR_PARAM_COUNT, rv);
+}
+
+ZTEST_USER(console_cmd_charge_state, test_idle_arg_not_a_bool)
+{
+	int rv;
+
+	/*
+	 * There are many strings that will fail parse_bool(), just test one to
+	 * test the code path in the command, other tests for parse_bool are
+	 * done in the respective unit test.
+	 */
+	rv = shell_execute_cmd(get_ec_shell(), "chgstate idle g");
+	zassert_equal(rv, EC_ERROR_PARAM2, "Expected %d, but got %d",
+		      EC_ERROR_PARAM2, rv);
+}
+
+ZTEST_USER(console_cmd_charge_state, test_idle_on__no_ac)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "chgstate idle on");
+	zassert_equal(rv, EC_ERROR_NOT_POWERED, "Expected %d, but got %d",
+		      EC_ERROR_NOT_POWERED, rv);
+}
+
+ZTEST_USER(console_cmd_charge_state, test_discharge_on__no_ac)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "chgstate discharge on");
+	zassert_equal(rv, EC_ERROR_NOT_POWERED, "Expected %d, but got %d",
+		      EC_ERROR_NOT_POWERED, rv);
+}
+
+ZTEST_USER(console_cmd_charge_state, test_discharge_too_few_args)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "chgstate discharge");
+	zassert_equal(rv, EC_ERROR_PARAM_COUNT, "Expected %d, but got %d",
+		      EC_ERROR_PARAM_COUNT, rv);
+}
+
+ZTEST_USER(console_cmd_charge_state, test_discharge_arg_not_a_bool)
+{
+	int rv;
+
+	/*
+	 * There are many strings that will fail parse_bool(), just test one to
+	 * test the code path in the command, other tests for parse_bool are
+	 * done in the respective unit test.
+	 */
+	rv = shell_execute_cmd(get_ec_shell(), "chgstate discharge g");
+	zassert_equal(rv, EC_ERROR_PARAM2, "Expected %d, but got %d",
+		      EC_ERROR_PARAM2, rv);
+}
+
+ZTEST_USER(console_cmd_charge_state, test_debug_too_few_args)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "chgstate debug");
+	zassert_equal(rv, EC_ERROR_PARAM_COUNT, "Expected %d, but got %d",
+		      EC_ERROR_PARAM_COUNT, rv);
+}
+
+ZTEST_USER(console_cmd_charge_state, test_debug_arg_not_bool)
+{
+	int rv;
+
+	/*
+	 * There are many strings that will fail parse_bool(), just test one to
+	 * test the code path in the command, other tests for parse_bool are
+	 * done in the respective unit test.
+	 */
+	rv = shell_execute_cmd(get_ec_shell(), "chgstate debug g");
+	zassert_equal(rv, EC_ERROR_PARAM2, "Expected %d, but got %d",
+		      EC_ERROR_PARAM2, rv);
+}
+
+ZTEST_USER(console_cmd_charge_state, test_debug_on)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "chgstate debug on"),
+		   NULL);
+}
+
+ZTEST_USER(console_cmd_charge_state, test_debug_on_show_charging_progress)
+{
+	/*
+	 * Force reset the previous display charge so the charge state task
+	 * prints on the next iteration.
+	 */
+	reset_prev_disp_charge();
+	charging_progress_displayed();
+
+	/* Enable debug printing */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "chgstate debug on"),
+		   NULL);
+
+	/* Sleep at least 1 full iteration of the charge state loop */
+	k_sleep(K_USEC(CHARGE_MAX_SLEEP_USEC + 1));
+
+	zassert_true(charging_progress_displayed());
+}
+
+ZTEST_USER(console_cmd_charge_state, test_sustain_too_few_args__2_args)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "chgstate sustain");
+	zassert_equal(rv, EC_ERROR_PARAM_COUNT, "Expected %d, but got %d",
+		      EC_ERROR_PARAM_COUNT, rv);
+}
+
+ZTEST_USER(console_cmd_charge_state, test_sustain_too_few_args__3_args)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "chgstate sustain 5");
+	zassert_equal(rv, EC_ERROR_PARAM_COUNT, "Expected %d, but got %d",
+		      EC_ERROR_PARAM_COUNT, rv);
+}
+
+ZTEST_USER(console_cmd_charge_state, test_sustain_invalid_params)
+{
+	/* Verify that lower bound is less than upper bound */
+	zassert_equal(shell_execute_cmd(get_ec_shell(),
+					"chgstate sustain 50 30"),
+		      EC_ERROR_INVAL, NULL);
+
+	/* Verify that lower bound is at least 0 (when upper bound is given) */
+	zassert_equal(shell_execute_cmd(get_ec_shell(),
+					"chgstate sustain -5 30"),
+		      EC_ERROR_INVAL, NULL);
+
+	/* Verify that upper bound is at most 100 */
+	zassert_equal(shell_execute_cmd(get_ec_shell(),
+					"chgstate sustain 50 101"),
+		      EC_ERROR_INVAL, NULL);
+
+	/* Verify invalid lower bound (not a number) */
+	zassert_equal(shell_execute_cmd(get_ec_shell(),
+					"chgstate sustain a 50"),
+		      EC_ERROR_PARAM2);
+
+	/* Verify invalid uppoer bound (not a number) */
+	zassert_equal(shell_execute_cmd(get_ec_shell(),
+					"chgstate sustain 30 a"),
+		      EC_ERROR_PARAM3);
+}
+
+struct console_cmd_charge_state_fixture {
+	struct tcpci_partner_data source_5v_3a;
+	struct tcpci_src_emul_data source_ext;
+	const struct emul *tcpci_emul;
+	const struct emul *charger_emul;
+};
+
+static void *console_cmd_charge_state_setup(void)
+{
+	static struct console_cmd_charge_state_fixture fixture;
+
+	/* Get references for the emulators */
+	fixture.tcpci_emul = EMUL_GET_USBC_BINDING(0, tcpc);
+	fixture.charger_emul = EMUL_GET_USBC_BINDING(0, chg);
+
+	/* Initialized the source to supply 5V and 3A */
+	tcpci_partner_init(&fixture.source_5v_3a, PD_REV20);
+	fixture.source_5v_3a.extensions = tcpci_src_emul_init(
+		&fixture.source_ext, &fixture.source_5v_3a, NULL);
+	fixture.source_ext.pdo[1] =
+		PDO_FIXED(5000, 3000, PDO_FIXED_UNCONSTRAINED);
+
+	return &fixture;
+}
+
+static void console_cmd_charge_state_after(void *data)
+{
+	struct console_cmd_charge_state_fixture *fixture = data;
+
+	disconnect_source_from_port(fixture->tcpci_emul, fixture->charger_emul);
+	shell_execute_cmd(get_ec_shell(), "chgstate debug off");
+	shell_execute_cmd(get_ec_shell(), "chgstate sustain -1 -1");
+}
+
+ZTEST_SUITE(console_cmd_charge_state, drivers_predicate_post_main,
+	    console_cmd_charge_state_setup, NULL,
+	    console_cmd_charge_state_after, NULL);
+
+ZTEST_USER_F(console_cmd_charge_state, test_idle_on_from_normal)
+{
+	/* Connect a source so we start charging */
+	connect_source_to_port(&fixture->source_5v_3a, &fixture->source_ext, 1,
+			       fixture->tcpci_emul, fixture->charger_emul);
+
+	/* Verify that we're in "normal" mode */
+	zassert_equal(get_chg_ctrl_mode(), CHARGE_CONTROL_NORMAL);
+
+	/* Move to idle */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "chgstate idle on"));
+	zassert_equal(get_chg_ctrl_mode(), CHARGE_CONTROL_IDLE);
+}
+
+ZTEST_USER_F(console_cmd_charge_state, test_normal_from_idle)
+{
+	/* Connect a source so we start charging */
+	connect_source_to_port(&fixture->source_5v_3a, &fixture->source_ext, 1,
+			       fixture->tcpci_emul, fixture->charger_emul);
+
+	/* Verify that we're in "normal" mode */
+	zassert_equal(get_chg_ctrl_mode(), CHARGE_CONTROL_NORMAL);
+
+	/* Move to idle */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "chgstate idle on"));
+	zassert_equal(get_chg_ctrl_mode(), CHARGE_CONTROL_IDLE);
+
+	/* Move back to normal */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "chgstate idle off"),
+		   NULL);
+	zassert_equal(get_chg_ctrl_mode(), CHARGE_CONTROL_NORMAL);
+}
+
+ZTEST_USER_F(console_cmd_charge_state, test_discharge_on)
+{
+	/* Connect a source so we start charging */
+	connect_source_to_port(&fixture->source_5v_3a, &fixture->source_ext, 1,
+			       fixture->tcpci_emul, fixture->charger_emul);
+
+	/* Verify that we're in "normal" mode */
+	zassert_equal(get_chg_ctrl_mode(), CHARGE_CONTROL_NORMAL);
+
+	/* Enable discharge */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "chgstate discharge on"),
+		   NULL);
+	zassert_equal(get_chg_ctrl_mode(), CHARGE_CONTROL_DISCHARGE);
+}
+
+ZTEST_USER_F(console_cmd_charge_state, test_discharge_off)
+{
+	/* Connect a source so we start charging */
+	connect_source_to_port(&fixture->source_5v_3a, &fixture->source_ext, 1,
+			       fixture->tcpci_emul, fixture->charger_emul);
+
+	/* Verify that we're in "normal" mode */
+	zassert_equal(get_chg_ctrl_mode(), CHARGE_CONTROL_NORMAL);
+
+	/* Enable discharge */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "chgstate discharge on"),
+		   NULL);
+	zassert_equal(get_chg_ctrl_mode(), CHARGE_CONTROL_DISCHARGE);
+
+	/* Disable discharge */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "chgstate discharge off"),
+		   NULL);
+	zassert_equal(get_chg_ctrl_mode(), CHARGE_CONTROL_NORMAL);
+}
+
+ZTEST_USER(console_cmd_charge_state, test_sustain)
+{
+	struct ec_response_charge_control charge_control_values;
+
+	/* Verify that lower bound is less than upper bound */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "chgstate sustain 30 50"),
+		   NULL);
+
+	charge_control_values = host_cmd_charge_control(
+		CHARGE_CONTROL_NORMAL, EC_CHARGE_CONTROL_CMD_GET);
+	zassert_equal(charge_control_values.sustain_soc.lower, 30);
+	zassert_equal(charge_control_values.sustain_soc.upper, 50);
+}
diff --git a/zephyr/test/drivers/default/src/console_cmd/chargen.c b/zephyr/test/drivers/default/src/console_cmd/chargen.c
new file mode 100644
index 0000000000..473ad78abb
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/chargen.c
@@ -0,0 +1,44 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "system.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "uart.h"
+
+#include <stdio.h>
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/uart/serial_test.h>
+#include <zephyr/shell/shell_dummy.h>
+#include <zephyr/ztest.h>
+
+const char expected_output[] =
+	"0123456789abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ"
+	"0123456789abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ\r\n";
+
+ZTEST_USER(console_cmd_chargen, test_no_args)
+{
+	const struct device *uart_shell_dev =
+		DEVICE_DT_GET(DT_CHOSEN(zephyr_shell_uart));
+	const struct shell *shell_zephyr = get_ec_shell();
+	uint32_t nread;
+	char read_buf[126] = { 0 };
+
+	shell_backend_dummy_clear_output(shell_zephyr);
+
+	uart_clear_input();
+	zassert_ok(shell_execute_cmd(shell_zephyr, "chargen 62 124"), NULL);
+	k_sleep(K_MSEC(500));
+
+	nread = serial_vnd_read_out_data(uart_shell_dev, read_buf,
+					 sizeof(read_buf));
+	zassert_true(nread == sizeof(read_buf));
+	zassert_true(memcmp(read_buf, expected_output, nread));
+}
+
+ZTEST_SUITE(console_cmd_chargen, drivers_predicate_post_main, NULL, NULL, NULL,
+	    NULL);
diff --git a/zephyr/test/drivers/default/src/console_cmd/charger.c b/zephyr/test/drivers/default/src/console_cmd/charger.c
new file mode 100644
index 0000000000..420ef67fe4
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/charger.c
@@ -0,0 +1,184 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "dptf.h"
+#include "ec_commands.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+/* Tests which need no fixture */
+ZTEST_USER(console_cmd_charger, test_default_dump)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "charger"),
+		   "Failed default print");
+}
+
+ZTEST_USER(console_cmd_charger, test_good_index)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "charger 0"),
+		   "Failed index 0 print");
+}
+
+/* Bad parameter tests */
+ZTEST_USER(console_cmd_charger, test_bad_index)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "charger 55");
+
+	zassert_equal(rv, EC_ERROR_PARAM1, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+}
+
+ZTEST_USER(console_cmd_charger, test_bad_command)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "charger fish");
+
+	zassert_equal(rv, EC_ERROR_PARAM1, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+}
+
+ZTEST_USER(console_cmd_charger, test_bad_input_current)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "charger input fish");
+
+	zassert_equal(rv, EC_ERROR_PARAM2, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+}
+
+ZTEST_USER(console_cmd_charger, test_bad_current)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "charger current fish");
+
+	zassert_equal(rv, EC_ERROR_PARAM2, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+}
+
+ZTEST_USER(console_cmd_charger, test_bad_voltage)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "charger voltage fish");
+
+	zassert_equal(rv, EC_ERROR_PARAM2, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+}
+
+ZTEST_USER(console_cmd_charger, test_bad_dptf_current)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "charger dptf fish");
+
+	zassert_equal(rv, EC_ERROR_PARAM2, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+}
+
+/* Good parameter sub-command tests */
+ZTEST_USER(console_cmd_charger, test_good_input_current)
+{
+	int input_current;
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "charger input 1000"),
+		   "Failed to set input current");
+	zassert_ok(charger_get_input_current_limit(0, &input_current),
+		   "Failed to get input current");
+	zassert_equal(input_current, 1000,
+		      "Input current not set in charger: %d", input_current);
+}
+
+ZTEST_USER(console_cmd_charger, test_good_dptf)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "charger dptf 1000"),
+		   "Failed to set dptf current");
+	zassert_equal(dptf_get_charging_current_limit(), 1000,
+		      "Unexpected dptf current");
+}
+
+ZTEST_USER(console_cmd_charger, test_unsupported_dump)
+{
+	/* Must define CONFIG_CMD_CHARGER_DUMP for this sub-command */
+	int rv = shell_execute_cmd(get_ec_shell(), "charger dump");
+
+	zassert_equal(rv, EC_ERROR_PARAM1, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+}
+
+/* Fixture needed to supply AC for manual current/voltage set */
+struct console_cmd_charger_fixture {
+	struct tcpci_partner_data source_5v_3a;
+	struct tcpci_src_emul_data source_ext;
+	const struct emul *tcpci_emul;
+	const struct emul *charger_emul;
+};
+
+static void *console_cmd_charger_setup(void)
+{
+	static struct console_cmd_charger_fixture fixture;
+
+	/* Assume we have one charger at index 0 */
+	zassert_true(board_get_charger_chip_count() > 0,
+		     "Insufficient chargers found");
+
+	/* Get references for the emulators */
+	fixture.tcpci_emul = EMUL_DT_GET(DT_NODELABEL(tcpci_emul));
+	fixture.charger_emul = EMUL_DT_GET(DT_NODELABEL(isl923x_emul));
+
+	/* Initialized the source to supply 5V and 3A */
+	tcpci_partner_init(&fixture.source_5v_3a, PD_REV20);
+	fixture.source_5v_3a.extensions = tcpci_src_emul_init(
+		&fixture.source_ext, &fixture.source_5v_3a, NULL);
+	fixture.source_ext.pdo[1] =
+		PDO_FIXED(5000, 3000, PDO_FIXED_UNCONSTRAINED);
+
+	return &fixture;
+}
+
+static void console_cmd_charger_after(void *data)
+{
+	struct console_cmd_charger_fixture *fixture = data;
+
+	/* Disconnect the source, and ensure we reset charge params */
+	disconnect_source_from_port(fixture->tcpci_emul, fixture->charger_emul);
+	host_cmd_charge_control(CHARGE_CONTROL_NORMAL,
+				EC_CHARGE_CONTROL_CMD_SET);
+}
+
+/* Tests that need the fixture */
+ZTEST_USER_F(console_cmd_charger, test_good_current)
+{
+	int current;
+
+	/* Connect a source so we start charging */
+	connect_source_to_port(&fixture->source_5v_3a, &fixture->source_ext, 1,
+			       fixture->tcpci_emul, fixture->charger_emul);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "charger current 1000"),
+		   "Failed to set current");
+
+	/* Give the charger task time to pick up the manual current */
+	k_sleep(K_SECONDS(1));
+
+	zassert_ok(charger_get_current(0, &current), "Failed to get current");
+	zassert_equal(current, 1000, "Current not set in charger: %d", current);
+}
+
+ZTEST_USER_F(console_cmd_charger, test_good_voltage)
+{
+	int voltage;
+
+	/* Connect a source so we start charging */
+	connect_source_to_port(&fixture->source_5v_3a, &fixture->source_ext, 1,
+			       fixture->tcpci_emul, fixture->charger_emul);
+	/* Note: select a fake voltage larger than the charger's minimum */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "charger voltage 3000"),
+		   "Failed to set voltage");
+
+	/* Give the charger task time to pick up the manual voltage */
+	k_sleep(K_SECONDS(1));
+
+	zassert_ok(charger_get_voltage(0, &voltage), "Failed to get voltage");
+	zassert_equal(voltage, 3000, "Voltage not set in charger: %d", voltage);
+}
+
+ZTEST_SUITE(console_cmd_charger, drivers_predicate_post_main,
+	    console_cmd_charger_setup, NULL, console_cmd_charger_after, NULL);
diff --git a/zephyr/test/drivers/default/src/console_cmd/cutoff.c b/zephyr/test/drivers/default/src/console_cmd/cutoff.c
new file mode 100644
index 0000000000..2b5a9c67d2
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/cutoff.c
@@ -0,0 +1,86 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "hooks.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+static void console_cmd_cutoff_after(void *unused)
+{
+	ARG_UNUSED(unused);
+	set_ac_enabled(true);
+	hook_notify(HOOK_AC_CHANGE);
+	k_msleep(500);
+}
+
+ZTEST_SUITE(console_cmd_cutoff, drivers_predicate_post_main, NULL, NULL,
+	    console_cmd_cutoff_after, NULL);
+
+ZTEST_USER(console_cmd_cutoff, test_sb_cutoff)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "cutoff");
+
+	zassert_equal(EC_RES_SUCCESS, rv, "Expected %d, but got %d",
+		      EC_RES_SUCCESS, rv);
+	zassert_true(battery_is_cut_off(), NULL);
+}
+
+ZTEST_USER(console_cmd_cutoff, test_invalid_arg1)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "cutoff bad_arg");
+
+	zassert_equal(EC_ERROR_INVAL, rv, "Expected %d, but got %d",
+		      EC_ERROR_INVAL, rv);
+	zassert_false(battery_is_cut_off(), NULL);
+}
+
+ZTEST_USER(console_cmd_cutoff, test_at_shutdown)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "cutoff at-shutdown");
+
+	zassert_equal(EC_RES_SUCCESS, rv, "Expected %d, but got %d",
+		      EC_RES_SUCCESS, rv);
+	zassert_false(battery_is_cut_off(), NULL);
+	hook_notify(HOOK_CHIPSET_SHUTDOWN);
+	zassert_true(WAIT_FOR(battery_is_cut_off(), 1500000, k_msleep(250)),
+		     NULL);
+}
+
+ZTEST_USER(console_cmd_cutoff, test_clear_pending_shutdown)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "cutoff at-shutdown");
+
+	zassert_true(extpower_is_present(), NULL);
+	zassert_equal(EC_RES_SUCCESS, rv, "Expected %d, but got %d",
+		      EC_RES_SUCCESS, rv);
+
+	/* Triggering the AC_CHANGE hook will cancel the pending cutoff */
+	hook_notify(HOOK_AC_CHANGE);
+
+	/* The shutdown will no longer cutoff the battery */
+	hook_notify(HOOK_CHIPSET_SHUTDOWN);
+	zassert_false(WAIT_FOR(battery_is_cut_off(), 1500000, k_msleep(250)),
+		      NULL);
+}
+
+ZTEST_USER(console_cmd_cutoff, test_ac_change_exits_cutoff)
+{
+	int rv;
+
+	set_ac_enabled(false);
+
+	rv = shell_execute_cmd(get_ec_shell(), "cutoff");
+	zassert_equal(EC_RES_SUCCESS, rv, "Expected %d, but got %d",
+		      EC_RES_SUCCESS, rv);
+
+	set_ac_enabled(true);
+	zassert_false(battery_is_cut_off(), NULL);
+}
diff --git a/zephyr/test/drivers/default/src/console_cmd/ec_features.c b/zephyr/test/drivers/default/src/console_cmd/ec_features.c
new file mode 100644
index 0000000000..48e6eec819
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/ec_features.c
@@ -0,0 +1,29 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "builtin/stdio.h"
+#include "console.h"
+#include "host_command.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+ZTEST_SUITE(console_cmd_ec_features, drivers_predicate_post_main, NULL, NULL,
+	    NULL, NULL);
+
+ZTEST_USER(console_cmd_ec_features, test_feat)
+{
+	char expected[50];
+	int ret;
+
+	ret = snprintf(expected, sizeof(expected),
+		       " 0-31: 0x%08x\r\n32-63: 0x%08x", get_feature_flags0(),
+		       get_feature_flags1());
+	zassert_true(ret >= 0 && ret < sizeof(expected));
+
+	CHECK_CONSOLE_CMD("feat", expected, EC_SUCCESS);
+}
diff --git a/zephyr/test/drivers/default/src/console_cmd/gpio.c b/zephyr/test/drivers/default/src/console_cmd/gpio.c
new file mode 100644
index 0000000000..c4b83b8ab4
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/gpio.c
@@ -0,0 +1,37 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "ec_commands.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+ZTEST_USER(console_cmd_gpio, test_read_invoke_success)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "gpioget test"), NULL);
+}
+
+ZTEST_USER(console_cmd_gpio, test_read_invoke_fail)
+{
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "gpioget DOES_NOT_EXIST"),
+		   NULL);
+}
+
+ZTEST_USER(console_cmd_gpio, test_set_gpio)
+{
+	const struct gpio_dt_spec *gp = GPIO_DT_FROM_NODELABEL(gpio_test);
+
+	zassert_ok(gpio_pin_set_dt(gp, 0), NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "gpioset test 1"), NULL);
+	zassert_equal(gpio_pin_get_dt(gp), 1, NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "gpioset test 0"), NULL);
+	zassert_equal(gpio_pin_get_dt(gp), 0, NULL);
+}
+
+ZTEST_SUITE(console_cmd_gpio, drivers_predicate_post_main, NULL, NULL, NULL,
+	    NULL);
diff --git a/zephyr/test/drivers/default/src/console_cmd/hcdebug.c b/zephyr/test/drivers/default/src/console_cmd/hcdebug.c
new file mode 100644
index 0000000000..68dc6c72be
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/hcdebug.c
@@ -0,0 +1,49 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "ec_commands.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+static void console_cmd_hcdebug_after(void *fixture)
+{
+	ARG_UNUSED(fixture);
+	shell_execute_cmd(get_ec_shell(), "hcdebug off");
+}
+
+ZTEST_SUITE(console_cmd_hcdebug, drivers_predicate_post_main, NULL, NULL,
+	    console_cmd_hcdebug_after, NULL);
+
+ZTEST_USER(console_cmd_hcdebug, test_too_many_args)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "hcdebug arg1 arg2");
+
+	zassert_not_equal(rv, EC_SUCCESS, "Expected %d, but got %d",
+			  EC_ERROR_PARAM_COUNT, rv);
+}
+
+ZTEST_USER(console_cmd_hcdebug, test_no_args)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "hcdebug"), NULL);
+}
+
+ZTEST_USER(console_cmd_hcdebug, test_invalid_arg)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "hcdebug bar");
+
+	zassert_equal(rv, EC_ERROR_PARAM1, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+}
+
+ZTEST_USER(console_cmd_hcdebug, test_valid_args)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "hcdebug off"), NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "hcdebug normal"), NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "hcdebug every"), NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "hcdebug params"), NULL);
+}
diff --git a/zephyr/test/drivers/default/src/console_cmd/hibdelay.c b/zephyr/test/drivers/default/src/console_cmd/hibdelay.c
new file mode 100644
index 0000000000..8275ece94d
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/hibdelay.c
@@ -0,0 +1,37 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "ec_commands.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+ZTEST_SUITE(console_cmd_hibdelay, drivers_predicate_post_main, NULL, NULL, NULL,
+	    NULL);
+
+ZTEST_USER(console_cmd_hibdelay, test_too_many_args)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "hibdelay 1 2"), NULL);
+}
+
+ZTEST_USER(console_cmd_hibdelay, test_no_args)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "hibdelay"), NULL);
+}
+
+ZTEST_USER(console_cmd_hibdelay, test_invalid_arg)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "hibdelay 3.4");
+
+	zassert_equal(rv, EC_ERROR_PARAM1, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+}
+
+ZTEST_USER(console_cmd_hibdelay, test_valid_args)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "hibdelay 5"), NULL);
+}
diff --git a/zephyr/test/drivers/default/src/console_cmd/hostevent.c b/zephyr/test/drivers/default/src/console_cmd/hostevent.c
new file mode 100644
index 0000000000..1db57f5836
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/hostevent.c
@@ -0,0 +1,189 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "ec_commands.h"
+#include "include/lpc.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+#define HOSTEVENT_PRINT_FORMAT "016" PRIx64
+
+struct console_cmd_hostevent_fixture {
+	struct host_events_ctx ctx;
+};
+
+static void *console_cmd_hostevent_setup(void)
+{
+	static struct console_cmd_hostevent_fixture fixture = { 0 };
+
+	return &fixture;
+}
+
+static void console_cmd_hostevent_before(void *fixture)
+{
+	struct console_cmd_hostevent_fixture *f = fixture;
+
+	host_events_save(&f->ctx);
+}
+
+static void console_cmd_hostevent_after(void *fixture)
+{
+	struct console_cmd_hostevent_fixture *f = fixture;
+
+	host_events_restore(&f->ctx);
+}
+
+static int console_cmd_hostevent(const char *subcommand, host_event_t mask)
+{
+	int rv;
+	char cmd_buf[CONFIG_SHELL_CMD_BUFF_SIZE];
+
+	rv = snprintf(cmd_buf, CONFIG_SHELL_CMD_BUFF_SIZE,
+		      "hostevent %s 0x%" HOSTEVENT_PRINT_FORMAT, subcommand,
+		      mask);
+
+	zassert_between_inclusive(rv, 0, CONFIG_SHELL_CMD_BUFF_SIZE,
+				  "hostevent console command too long");
+
+	return shell_execute_cmd(get_ec_shell(), cmd_buf);
+}
+
+/* hostevent with no arguments */
+ZTEST_USER(console_cmd_hostevent, test_hostevent)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "hostevent"),
+		   "Failed default print");
+}
+
+/* hostevent with invalid arguments */
+ZTEST_USER(console_cmd_hostevent, test_hostevent_invalid)
+{
+	int rv;
+	host_event_t mask = 0;
+
+	/* Test invalid sub-command */
+	rv = console_cmd_hostevent("invalid", mask);
+	zassert_equal(rv, EC_ERROR_PARAM1, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+
+	/* Test invalid mask */
+	rv = shell_execute_cmd(get_ec_shell(), "hostevent set invalid-mask");
+	zassert_equal(rv, EC_ERROR_PARAM2, "Expected %d, but got %d",
+		      EC_ERROR_PARAM2, rv);
+}
+
+/* hostevent with sub-commands and verification */
+ZTEST_USER(console_cmd_hostevent, test_hostevent_sub_commands)
+{
+	int rv;
+	enum ec_status ret_val;
+	host_event_t event_mask;
+	host_event_t all_events = 0;
+	host_event_t set_events;
+	struct ec_response_host_event result = { 0 };
+	struct {
+		enum lpc_host_event_type type;
+		const char *name;
+		host_event_t mask;
+	} subcommand[] = {
+		{
+			.type = LPC_HOST_EVENT_SMI,
+			.name = "SMI",
+			.mask = EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED),
+		},
+		{
+			.type = LPC_HOST_EVENT_SCI,
+			.name = "SCI",
+			.mask = EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN),
+		},
+		{
+			.type = LPC_HOST_EVENT_WAKE,
+			.name = "WAKE",
+			.mask = EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON),
+		},
+		{
+			.type = LPC_HOST_EVENT_ALWAYS_REPORT,
+			.name = "ALWAYS_REPORT",
+			.mask = EC_HOST_EVENT_MASK(
+				EC_HOST_EVENT_AC_DISCONNECTED),
+		},
+	};
+
+	for (int i = 0; i < ARRAY_SIZE(subcommand); i++) {
+		event_mask = lpc_get_host_event_mask(subcommand[i].type);
+		zassert_false(event_mask & subcommand[i].mask,
+			      "%s mask is set before test started",
+			      subcommand[i].name);
+		/*
+		 * Setting mask value overwrites existing setting, so OR in
+		 * the test bit.
+		 */
+		event_mask |= subcommand[i].mask;
+		rv = console_cmd_hostevent(subcommand[i].name, event_mask);
+		zassert_ok(rv, "Subcommand %s failed", subcommand[i].name);
+		zassert_true(lpc_get_host_event_mask(subcommand[i].type) &
+				     subcommand[i].mask,
+			     "Failed to set %s event mask", subcommand[i].name);
+
+		/*
+		 * It is only valid to set host events, once at least one mask
+		 * value includes the event.  Setting host events preserves
+		 * existing events.
+		 */
+		zassert_false(host_get_events() & subcommand[i].mask,
+			      "Host event is set before test started");
+		rv = console_cmd_hostevent("set", subcommand[i].mask);
+		zassert_ok(rv, "Subcommand SET failed");
+
+		all_events |= subcommand[i].mask;
+	}
+
+	/* Verify all host events were set, and none were lost */
+	zassert_true((host_get_events() & all_events) == all_events,
+		     "Failed to set host events");
+
+	/* Test clearing of host events */
+	set_events = all_events;
+	for (int i = 0; i < ARRAY_SIZE(subcommand); i++) {
+		set_events &= ~subcommand[i].mask;
+		rv = console_cmd_hostevent("clear", subcommand[i].mask);
+		zassert_ok(rv, "Subcommand CLEAR failed");
+
+		zassert_true((host_get_events() & set_events) == set_events,
+			     "Failed to clear host event");
+	}
+
+	/* Verify the backup host events were set, and none were cleared */
+	ret_val = host_cmd_host_event(EC_HOST_EVENT_GET, EC_HOST_EVENT_B,
+				      &result);
+	zassert_equal(ret_val, EC_RES_SUCCESS, "Expected=%d, returned=%d",
+		      EC_RES_SUCCESS, ret_val);
+	zassert_true((result.value & all_events) == all_events,
+		     "Failed to set host events backup");
+
+	/* Test clearing of backup host events */
+	set_events = all_events;
+	for (int i = 0; i < ARRAY_SIZE(subcommand); i++) {
+		set_events &= ~subcommand[i].mask;
+		rv = console_cmd_hostevent("clearb", subcommand[i].mask);
+		zassert_ok(rv, "Subcommand CLEAR failed");
+
+		ret_val = host_cmd_host_event(EC_HOST_EVENT_GET,
+					      EC_HOST_EVENT_B, &result);
+		zassert_equal(ret_val, EC_RES_SUCCESS,
+			      "Expected=%d, returned=%d", EC_RES_SUCCESS,
+			      ret_val);
+		zassert_true((result.value & set_events) == set_events,
+			     "Failed to clear host events backup");
+	}
+}
+
+ZTEST_SUITE(console_cmd_hostevent, drivers_predicate_post_main,
+	    console_cmd_hostevent_setup, console_cmd_hostevent_before,
+	    console_cmd_hostevent_after, NULL);
diff --git a/zephyr/test/drivers/default/src/console_cmd/i2c_portmap.c b/zephyr/test/drivers/default/src/console_cmd/i2c_portmap.c
new file mode 100644
index 0000000000..7651127218
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/i2c_portmap.c
@@ -0,0 +1,27 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "ec_commands.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+ZTEST_SUITE(console_cmd_i2c_portmap, drivers_predicate_post_main, NULL, NULL,
+	    NULL, NULL);
+
+ZTEST_USER(console_cmd_i2c_portmap, test_too_many_args)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "i2c_portmap arg1");
+
+	zassert_equal(rv, EC_ERROR_PARAM_COUNT, "Expected %d, but got %d",
+		      EC_ERROR_PARAM_COUNT, rv);
+}
+
+ZTEST_USER(console_cmd_i2c_portmap, test_get_i2c_portmap)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "i2c_portmap"), NULL);
+}
diff --git a/zephyr/test/drivers/default/src/console_cmd/md.c b/zephyr/test/drivers/default/src/console_cmd/md.c
new file mode 100644
index 0000000000..0db049a635
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/md.c
@@ -0,0 +1,83 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+ZTEST_SUITE(console_cmd_md, drivers_predicate_post_main, NULL, NULL, NULL,
+	    NULL);
+
+ZTEST_USER(console_cmd_md, test_too_few_args)
+{
+	zassert_equal(EC_ERROR_PARAM_COUNT,
+		      shell_execute_cmd(get_ec_shell(), "md"), NULL);
+}
+
+ZTEST_USER(console_cmd_md, test_error_param1)
+{
+	zassert_equal(EC_ERROR_PARAM1,
+		      shell_execute_cmd(get_ec_shell(), "md .j"), NULL);
+}
+
+ZTEST_USER(console_cmd_md, test_error_bad_address)
+{
+	zassert_equal(EC_ERROR_PARAM1,
+		      shell_execute_cmd(get_ec_shell(), "md not_an_address"),
+		      NULL);
+}
+
+ZTEST_USER(console_cmd_md, test_default_count)
+{
+	uint8_t memory[] = { 0x01, 0x02, 0x03, 0x04 };
+	char cmd[128] = { 0 };
+
+	zassert_true(sprintf(cmd, "md %" PRIuPTR, (uintptr_t)memory) != 0,
+		     NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), cmd), NULL);
+}
+
+ZTEST_USER(console_cmd_md, test_count_arg)
+{
+	uint8_t memory[] = { 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08 };
+	char cmd[128] = { 0 };
+
+	zassert_true(sprintf(cmd, "md %" PRIuPTR " 2", (uintptr_t)memory) != 0,
+		     NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), cmd), NULL);
+}
+
+ZTEST_USER(console_cmd_md, test_byte_format)
+{
+	uint8_t memory[] = { 0x01, 0x02, 0x03, 0x04 };
+	char cmd[128] = { 0 };
+
+	zassert_true(sprintf(cmd, "md .b %" PRIuPTR, (uintptr_t)memory) != 0,
+		     NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), cmd), NULL);
+}
+
+ZTEST_USER(console_cmd_md, test_half_format)
+{
+	uint8_t memory[] = { 0x01, 0x02, 0x03, 0x04 };
+	char cmd[128] = { 0 };
+
+	zassert_true(sprintf(cmd, "md .h %" PRIuPTR, (uintptr_t)memory) != 0,
+		     NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), cmd), NULL);
+}
+
+ZTEST_USER(console_cmd_md, test_string_format)
+{
+	char memory[] = "hello world";
+	char cmd[128] = { 0 };
+
+	zassert_true(sprintf(cmd, "md .s %" PRIuPTR " 12", (uintptr_t)memory) !=
+			     0,
+		     NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), cmd), NULL);
+}
diff --git a/zephyr/test/drivers/default/src/console_cmd/panic_output.c b/zephyr/test/drivers/default/src/console_cmd/panic_output.c
new file mode 100644
index 0000000000..d9365c3618
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/panic_output.c
@@ -0,0 +1,95 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "ec_commands.h"
+#include "panic.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+/* Test panicinfo when a panic hasn't occurred */
+ZTEST_USER(console_cmd_panic_output, test_panicinfo)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "panicinfo"),
+		   "Failed default print");
+}
+
+/* Test panicinfo with one invalid argument */
+ZTEST_USER(console_cmd_panic_output, test_panicinfo_bad_arg)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "panicinfo fish");
+
+	zassert_equal(rv, EC_ERROR_PARAM1, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+}
+
+/* Test panicinfo with two arguments */
+ZTEST_USER(console_cmd_panic_output, test_panicinfo_two_args)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "panicinfo go fish");
+
+	zassert_equal(rv, EC_ERROR_PARAM_COUNT, "Expected %d, but got %d",
+		      EC_ERROR_PARAM_COUNT, rv);
+}
+
+/* Fixture needed to save panic data state */
+struct console_cmd_panic_output_fixture {
+	struct panic_data *p_data;
+	struct panic_data cpy_data;
+};
+
+static void *console_cmd_panic_setup(void)
+{
+	static struct console_cmd_panic_output_fixture fixture;
+
+	return &fixture;
+}
+
+static void console_cmd_panic_before(void *data)
+{
+	struct console_cmd_panic_output_fixture *fixture = data;
+
+	fixture->p_data = get_panic_data_write();
+	fixture->cpy_data = *fixture->p_data;
+}
+
+static void console_cmd_panic_after(void *data)
+{
+	struct console_cmd_panic_output_fixture *fixture = data;
+
+	struct panic_data *p_data = fixture->p_data;
+
+	*p_data = fixture->cpy_data;
+}
+
+/* Tests that need the fixture */
+ZTEST_USER_F(console_cmd_panic_output, test_panicinfo_with_panic)
+{
+	fixture->p_data->flags = 0x1;
+	fixture->p_data->struct_size = CONFIG_PANIC_DATA_SIZE;
+	fixture->p_data->magic = PANIC_DATA_MAGIC;
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "panicinfo"),
+		   "Failed to print details about panic.");
+}
+
+/* Test clear argument. Should always succeed. */
+ZTEST_USER_F(console_cmd_panic_output, test_panicinfo_clear)
+{
+	fixture->p_data->flags = 0x1;
+	fixture->p_data->struct_size = CONFIG_PANIC_DATA_SIZE;
+	fixture->p_data->magic = PANIC_DATA_MAGIC;
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "panicinfo clear"),
+		   "Clear command failed");
+	zassert_equal(fixture->p_data->flags, 0, "Panic flags not cleared");
+	zassert_equal(fixture->p_data->struct_size, 0,
+		      "Panic struct size not cleared");
+	zassert_equal(fixture->p_data->magic, 0, "Panic magic not cleared");
+}
+
+ZTEST_SUITE(console_cmd_panic_output, NULL, console_cmd_panic_setup,
+	    console_cmd_panic_before, console_cmd_panic_after, NULL);
diff --git a/zephyr/test/drivers/default/src/console_cmd/port80.c b/zephyr/test/drivers/default/src/console_cmd/port80.c
new file mode 100644
index 0000000000..1f2d91f6c1
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/port80.c
@@ -0,0 +1,45 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ * @brief Unit Tests for ESPI port 80 console command
+ */
+
+#include "console.h"
+#include "ec_commands.h"
+#include "port80.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+/**
+ * @brief TestPurpose: Verify port 80 console commands
+ *
+ * @details
+ * Validate that the port 80 console commands work.
+ *
+ * Expected Results
+ *  - The port 80 console commands return the appropriate result
+ */
+ZTEST(console_cmd_port80, test_port80_console)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "port80"), NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "port80 flush"), NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "port80 scroll"), NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "port80 intprint"), NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "port80 unknown_param"),
+		   NULL);
+}
+
+/**
+ * @brief Test Suite: Verifies port 80 console commands.
+ */
+ZTEST_SUITE(console_cmd_port80, drivers_predicate_post_main, NULL, NULL, NULL,
+	    NULL);
diff --git a/zephyr/test/drivers/default/src/console_cmd/power_button.c b/zephyr/test/drivers/default/src/console_cmd/power_button.c
new file mode 100644
index 0000000000..d9900e8667
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/power_button.c
@@ -0,0 +1,35 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/ztest.h>
+
+#include <console.h>
+
+ZTEST_SUITE(console_cmd_power_button, NULL, NULL, NULL, NULL, NULL);
+
+ZTEST_USER(console_cmd_power_button, test_return_ok)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "powerbtn"), NULL);
+}
+
+ZTEST_USER(console_cmd_power_button, test_negative_delay)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "powerbtn -1");
+
+	zassert_not_equal(rv, EC_SUCCESS,
+			  "Command should error on negative delay");
+}
+
+ZTEST_USER(console_cmd_power_button, test_invalid_arg)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "powerbtn foo");
+
+	zassert_equal(rv, EC_ERROR_PARAM1, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+}
diff --git a/zephyr/test/drivers/default/src/console_cmd/powerindebug.c b/zephyr/test/drivers/default/src/console_cmd/powerindebug.c
new file mode 100644
index 0000000000..946960ea86
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/powerindebug.c
@@ -0,0 +1,36 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "ec_commands.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+ZTEST_USER(console_cmd_powerindebug, test_no_params)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "powerindebug"),
+		   "Failed to get debug mask");
+}
+
+ZTEST_USER(console_cmd_powerindebug, test_good_params)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "powerindebug 0x10"),
+		   "Failed to set debug mask");
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "powerindebug 0"),
+		   "Failed to set debug mask");
+}
+
+ZTEST_USER(console_cmd_powerindebug, test_bad_params)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "powerindebug fish");
+
+	zassert_equal(rv, EC_ERROR_PARAM1, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+}
+
+ZTEST_SUITE(console_cmd_powerindebug, NULL, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/drivers/default/src/console_cmd/pwr_avg.c b/zephyr/test/drivers/default/src/console_cmd/pwr_avg.c
new file mode 100644
index 0000000000..b21755a465
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/pwr_avg.c
@@ -0,0 +1,47 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "console.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <stdio.h>
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/shell/shell_dummy.h>
+#include <zephyr/ztest.h>
+
+ZTEST_SUITE(console_cmd_pwr_avg, drivers_predicate_post_main, NULL, NULL, NULL,
+	    NULL);
+
+ZTEST_USER(console_cmd_pwr_avg, test_too_many_args)
+{
+	zassert_equal(EC_ERROR_PARAM_COUNT,
+		      shell_execute_cmd(get_ec_shell(), "pwr_avg 5"));
+}
+
+ZTEST_USER(console_cmd_pwr_avg, test_printout)
+{
+	int mv = battery_get_avg_voltage();
+	int ma = battery_get_avg_current();
+	char expected_output[1024];
+	const char *buffer;
+	size_t buffer_size;
+
+	shell_backend_dummy_clear_output(get_ec_shell());
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "pwr_avg"));
+
+	buffer = shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+
+	sprintf(expected_output, "mv = %d", mv);
+	zassert_true(strstr(buffer, expected_output));
+
+	sprintf(expected_output, "ma = %d", ma);
+	zassert_true(strstr(buffer, expected_output));
+
+	sprintf(expected_output, "mw = %d", mv * ma / 1000);
+	zassert_true(strstr(buffer, expected_output));
+}
diff --git a/zephyr/test/drivers/default/src/console_cmd/rtc.c b/zephyr/test/drivers/default/src/console_cmd/rtc.c
new file mode 100644
index 0000000000..974d3709b7
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/rtc.c
@@ -0,0 +1,73 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "ec_commands.h"
+#include "system.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/ztest.h>
+
+ZTEST_USER(console_cmd_rtc, test_rtc_no_arg)
+{
+	char expected_buffer[32];
+	uint32_t sec = 7;
+
+	snprintf(expected_buffer, sizeof(expected_buffer),
+		 "RTC: 0x%08x (%d.00 s)", sec, sec);
+
+	system_set_rtc(sec);
+
+	CHECK_CONSOLE_CMD("rtc", expected_buffer, EC_SUCCESS);
+}
+
+ZTEST_USER(console_cmd_rtc, test_rtc_invalid)
+{
+	CHECK_CONSOLE_CMD("rtc set", NULL, EC_ERROR_INVAL);
+}
+
+ZTEST_USER(console_cmd_rtc, test_rtc_set)
+{
+	char command[32];
+	char expected_buffer[32];
+	uint32_t sec = 48879;
+
+	snprintf(expected_buffer, sizeof(expected_buffer),
+		 "RTC: 0x%08x (%d.00 s)", sec, sec);
+	snprintf(command, sizeof(command), "rtc set %d", sec);
+
+	CHECK_CONSOLE_CMD(command, expected_buffer, EC_SUCCESS);
+}
+
+ZTEST_USER(console_cmd_rtc, test_rtc_set_bad)
+{
+	CHECK_CONSOLE_CMD("rtc set t", NULL, EC_ERROR_PARAM2);
+}
+
+ZTEST_USER(console_cmd_rtc, test_rtc_alarm_no_args)
+{
+	CHECK_CONSOLE_CMD("rtc_alarm", "Setting RTC alarm", EC_SUCCESS);
+}
+
+ZTEST_USER(console_cmd_rtc, test_rtc_alarm_good_args)
+{
+	CHECK_CONSOLE_CMD("rtc_alarm 1", "Setting RTC alarm", EC_SUCCESS);
+	CHECK_CONSOLE_CMD("rtc_alarm 1 5", "Setting RTC alarm", EC_SUCCESS);
+}
+
+ZTEST_USER(console_cmd_rtc, test_rtc_alarm_bad_args)
+{
+	CHECK_CONSOLE_CMD("rtc_alarm t", NULL, EC_ERROR_PARAM1);
+	CHECK_CONSOLE_CMD("rtc_alarm 1 t", NULL, EC_ERROR_PARAM2);
+}
+
+ZTEST_USER(console_cmd_rtc, test_rtc_alarm_reset)
+{
+	CHECK_CONSOLE_CMD("rtc_alarm 0", "Setting RTC alarm", EC_SUCCESS);
+	CHECK_CONSOLE_CMD("rtc_alarm 0 0", "Setting RTC alarm", EC_SUCCESS);
+}
+
+ZTEST_SUITE(console_cmd_rtc, NULL, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/drivers/default/src/console_cmd/rw.c b/zephyr/test/drivers/default/src/console_cmd/rw.c
new file mode 100644
index 0000000000..1560254f92
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/rw.c
@@ -0,0 +1,102 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+ZTEST_SUITE(console_cmd_rw, drivers_predicate_post_main, NULL, NULL, NULL,
+	    NULL);
+
+ZTEST_USER(console_cmd_rw, test_too_few_args)
+{
+	zassert_equal(EC_ERROR_PARAM_COUNT,
+		      shell_execute_cmd(get_ec_shell(), "rw"), NULL);
+}
+
+ZTEST_USER(console_cmd_rw, test_error_param1)
+{
+	zassert_equal(EC_ERROR_PARAM1,
+		      shell_execute_cmd(get_ec_shell(), "rw .j"), NULL);
+
+	zassert_equal(EC_ERROR_PARAM1,
+		      shell_execute_cmd(get_ec_shell(), "rw .j not_an_address"),
+		      NULL);
+}
+
+ZTEST_USER(console_cmd_rw, test_error_bad_address)
+{
+	zassert_equal(EC_ERROR_PARAM1,
+		      shell_execute_cmd(get_ec_shell(), "rw not_an_address"),
+		      NULL);
+	zassert_equal(EC_ERROR_PARAM2,
+		      shell_execute_cmd(get_ec_shell(), "rw .b not_an_address"),
+		      NULL);
+}
+
+ZTEST_USER(console_cmd_rw, test_read)
+{
+	uint8_t memory[] = { 0x01, 0x02, 0x03, 0x04 };
+	char cmd[128] = { 0 };
+
+	zassert_true(sprintf(cmd, "rw .b %" PRIuPTR, (uintptr_t)memory) != 0,
+		     NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), cmd), NULL);
+
+	zassert_true(sprintf(cmd, "rw .h %" PRIuPTR, (uintptr_t)memory) != 0,
+		     NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), cmd), NULL);
+
+	zassert_true(sprintf(cmd, "rw %" PRIuPTR, (uintptr_t)memory) != 0,
+		     NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), cmd), NULL);
+}
+
+ZTEST_USER(console_cmd_rw, test_write_invalid_value)
+{
+	zassert_equal(EC_ERROR_PARAM2,
+		      shell_execute_cmd(get_ec_shell(), "rw 0 not-a-value"),
+		      NULL);
+	zassert_equal(EC_ERROR_PARAM3,
+		      shell_execute_cmd(get_ec_shell(), "rw .b 0 not-a-value"),
+		      NULL);
+}
+
+ZTEST_USER(console_cmd_rw, test_write)
+{
+	uint8_t memory[4] = { 0 };
+	char cmd[128] = { 0 };
+
+	zassert_true(sprintf(cmd, "rw .b %" PRIuPTR " 1", (uintptr_t)memory) !=
+			     0,
+		     NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), cmd), NULL);
+	zassert_equal(1, memory[0], "memory[0] was %u", memory[0]);
+	zassert_equal(0, memory[1], "memory[1] was %u", memory[1]);
+	zassert_equal(0, memory[2], "memory[2] was %u", memory[2]);
+	zassert_equal(0, memory[3], "memory[3] was %u", memory[3]);
+
+	memset(memory, 0, 4);
+	zassert_true(sprintf(cmd, "rw .h %" PRIuPTR " 258",
+			     (uintptr_t)memory) != 0,
+		     NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), cmd), NULL);
+	zassert_equal(2, memory[0], "memory[0] was %u", memory[0]);
+	zassert_equal(1, memory[1], "memory[1] was %u", memory[1]);
+	zassert_equal(0, memory[2], "memory[2] was %u", memory[2]);
+	zassert_equal(0, memory[3], "memory[3] was %u", memory[3]);
+
+	memset(memory, 0, 4);
+	zassert_true(sprintf(cmd, "rw %" PRIuPTR " 16909060",
+			     (uintptr_t)memory) != 0,
+		     NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), cmd), NULL);
+	zassert_equal(4, memory[0], "memory[0] was %u", memory[0]);
+	zassert_equal(3, memory[1], "memory[1] was %u", memory[1]);
+	zassert_equal(2, memory[2], "memory[2] was %u", memory[2]);
+	zassert_equal(1, memory[3], "memory[3] was %u", memory[3]);
+}
diff --git a/zephyr/test/drivers/default/src/console_cmd/shared_mem.c b/zephyr/test/drivers/default/src/console_cmd/shared_mem.c
new file mode 100644
index 0000000000..ed796124e4
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/shared_mem.c
@@ -0,0 +1,24 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "shared_mem.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+ZTEST_SUITE(console_cmd_shared_mem, drivers_predicate_post_main, NULL, NULL,
+	    NULL, NULL);
+
+ZTEST_USER(console_cmd_shared_mem, test_shmem)
+{
+	char expected[32];
+
+	snprintf(expected, sizeof(expected), "Size:%6d", shared_mem_size());
+
+	CHECK_CONSOLE_CMD("shmem", expected, EC_SUCCESS);
+}
diff --git a/zephyr/test/drivers/default/src/console_cmd/sleepmask.c b/zephyr/test/drivers/default/src/console_cmd/sleepmask.c
new file mode 100644
index 0000000000..40d174e6af
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/sleepmask.c
@@ -0,0 +1,100 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "system.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/shell/shell_dummy.h>
+#include <zephyr/ztest.h>
+
+ZTEST_USER(console_cmd_sleepmask, test_no_args)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+	const char *outbuffer;
+	size_t buffer_size;
+
+	shell_backend_dummy_clear_output(shell_zephyr);
+
+	zassert_ok(shell_execute_cmd(shell_zephyr, "sleepmask"), NULL);
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+
+	zassert_true(buffer_size > 0, NULL);
+	zassert_not_null(strstr(outbuffer, "sleep mask"), NULL);
+}
+
+ZTEST_USER(console_cmd_sleepmask, test_bad_args)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+
+	zassert_equal(EC_ERROR_PARAM1,
+		      shell_execute_cmd(shell_zephyr, "sleepmask whoopsie"),
+		      NULL);
+}
+
+ZTEST_USER(console_cmd_sleepmask, test_set_sleep_mask_directly)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+	const char *outbuffer;
+	size_t buffer_size;
+
+	shell_backend_dummy_clear_output(shell_zephyr);
+
+	/* Set mask as 0 */
+	zassert_ok(shell_execute_cmd(shell_zephyr, "sleepmask 0"), NULL);
+	shell_backend_dummy_clear_output(shell_zephyr);
+
+	/* Get mask and weakly verify mask is 0 */
+	zassert_ok(shell_execute_cmd(shell_zephyr, "sleepmask"), NULL);
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+
+	zassert_not_null(strstr(outbuffer, "0"), NULL);
+	zassert_is_null(strstr(outbuffer, "1"), NULL);
+
+	/* Set mask as 1 */
+	zassert_ok(shell_execute_cmd(shell_zephyr, "sleepmask 1"), NULL);
+	shell_backend_dummy_clear_output(shell_zephyr);
+
+	/* Get mask and weakly verify mask is 1 */
+	zassert_ok(shell_execute_cmd(shell_zephyr, "sleepmask"), NULL);
+	zassert_not_null(strstr(outbuffer, "1"), NULL);
+}
+
+ZTEST_USER(console_cmd_sleepmask, test_enable_disable_force_sleepmask)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+
+	/* Verifying enabled to disabled */
+
+	zassert_ok(shell_execute_cmd(shell_zephyr, "sleepmask on"), NULL);
+
+	int enabled_bits = sleep_mask & SLEEP_MASK_FORCE_NO_DSLEEP;
+
+	zassert_ok(shell_execute_cmd(shell_zephyr, "sleepmask off"), NULL);
+
+	int disabled_bits = sleep_mask & SLEEP_MASK_FORCE_NO_DSLEEP;
+
+	zassert_false(enabled_bits & disabled_bits, NULL);
+
+	/* Verifying disabled to enabled */
+
+	zassert_ok(shell_execute_cmd(shell_zephyr, "sleepmask on"), NULL);
+
+	enabled_bits = sleep_mask & SLEEP_MASK_FORCE_NO_DSLEEP;
+	zassert_false(enabled_bits & disabled_bits, NULL);
+}
+
+static void console_cmd_sleepmask_before_after(void *test_data)
+{
+	ARG_UNUSED(test_data);
+
+	enable_sleep(-1);
+}
+
+ZTEST_SUITE(console_cmd_sleepmask, drivers_predicate_post_main, NULL,
+	    console_cmd_sleepmask_before_after,
+	    console_cmd_sleepmask_before_after, NULL);
diff --git a/zephyr/test/drivers/default/src/console_cmd/sleeptimeout.c b/zephyr/test/drivers/default/src/console_cmd/sleeptimeout.c
new file mode 100644
index 0000000000..3bd8a39f3f
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/sleeptimeout.c
@@ -0,0 +1,44 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "ec_commands.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+ZTEST_USER(console_cmd_sleeptimeout, test_no_params)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "sleeptimeout"),
+		   "Failed default print");
+}
+
+ZTEST_USER(console_cmd_sleeptimeout, test_good_params)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "sleeptimeout default"),
+		   "Failed to set default sleep timeout");
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "sleeptimeout infinite"),
+		   "Failed to disable sleep timeout");
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "sleeptimeout 1500"),
+		   "Failed to set sleep timeout to a custom value");
+}
+
+ZTEST_USER(console_cmd_sleeptimeout, test_bad_params)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "sleeptimeout 0");
+
+	zassert_equal(rv, EC_ERROR_PARAM1, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+
+	rv = shell_execute_cmd(get_ec_shell(),
+			       "sleeptimeout EC_HOST_SLEEP_TIMEOUT_INFINITE");
+
+	zassert_equal(rv, EC_ERROR_PARAM1, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+}
+
+ZTEST_SUITE(console_cmd_sleeptimeout, NULL, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/drivers/default/src/console_cmd/switch.c b/zephyr/test/drivers/default/src/console_cmd/switch.c
new file mode 100644
index 0000000000..f533ebe7b9
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/switch.c
@@ -0,0 +1,31 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+ZTEST_SUITE(console_cmd_switch, drivers_predicate_post_main, NULL, NULL, NULL,
+	    NULL);
+
+ZTEST_USER(console_cmd_switch, test_mmapinfo)
+{
+	uint8_t *memmap_switches = host_get_memmap(EC_MEMMAP_SWITCHES);
+	uint8_t before = *memmap_switches;
+	char expected[32];
+
+	*memmap_switches = 0x3;
+	snprintf(expected, sizeof(expected), "memmap switches = 0x%x",
+		 *memmap_switches);
+
+	CHECK_CONSOLE_CMD("mmapinfo", expected, EC_SUCCESS);
+	CHECK_CONSOLE_CMD("mmapinfo", "lid_open", EC_SUCCESS);
+	CHECK_CONSOLE_CMD("mmapinfo", "powerbtn", EC_SUCCESS);
+
+	*memmap_switches = before;
+}
diff --git a/zephyr/test/drivers/default/src/console_cmd/sysinfo.c b/zephyr/test/drivers/default/src/console_cmd/sysinfo.c
new file mode 100644
index 0000000000..ba14e9158f
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/sysinfo.c
@@ -0,0 +1,84 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "system.h"
+#include "test/drivers/test_mocks.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/fff.h>
+#include <zephyr/shell/shell_dummy.h>
+#include <zephyr/ztest.h>
+
+ZTEST_USER(console_cmd_sysinfo, test_no_args)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+	const char *outbuffer;
+	size_t buffer_size;
+
+	shell_backend_dummy_clear_output(shell_zephyr);
+
+	zassert_ok(shell_execute_cmd(shell_zephyr, "sysinfo"), NULL);
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+
+	zassert_true(buffer_size > 0, NULL);
+
+	/* Weakly verify some contents */
+	zassert_not_null(strstr(outbuffer, "Reset flags:"), NULL);
+	zassert_not_null(strstr(outbuffer, "Copy:"), NULL);
+	zassert_not_null(strstr(outbuffer, "Jumped:"), NULL);
+	zassert_not_null(strstr(outbuffer, "Recovery:"), NULL);
+	zassert_not_null(strstr(outbuffer, "Flags:"), NULL);
+}
+
+ZTEST_USER(console_cmd_sysinfo, test_no_args__sys_locked)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+	const char *outbuffer;
+	size_t buffer_size;
+
+	/* System unlocked */
+	shell_backend_dummy_clear_output(shell_zephyr);
+	system_is_locked_fake.return_val = false;
+
+	zassert_ok(shell_execute_cmd(shell_zephyr, "sysinfo"), NULL);
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+
+	zassert_true(buffer_size > 0, NULL);
+	zassert_not_null(strstr(outbuffer, "unlocked"), NULL);
+
+	/* System locked */
+	shell_backend_dummy_clear_output(shell_zephyr);
+	system_is_locked_fake.return_val = true;
+
+	zassert_true(buffer_size > 0, NULL);
+	zassert_ok(shell_execute_cmd(shell_zephyr, "sysinfo"), NULL);
+
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+	zassert_not_null(strstr(outbuffer, "locked"), NULL);
+
+	/* Verify system_is_locked in sysinfo cmd response remains */
+	shell_backend_dummy_clear_output(shell_zephyr);
+	system_is_locked_fake.return_val = false;
+
+	zassert_ok(shell_execute_cmd(shell_zephyr, "sysinfo"), NULL);
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+
+	zassert_true(buffer_size > 0, NULL);
+	zassert_not_null(strstr(outbuffer, "locked"), NULL);
+}
+
+static void console_cmd_sysinfo_before_after(void *test_data)
+{
+	ARG_UNUSED(test_data);
+
+	system_common_reset_state();
+}
+
+ZTEST_SUITE(console_cmd_sysinfo, drivers_predicate_post_main, NULL,
+	    console_cmd_sysinfo_before_after, console_cmd_sysinfo_before_after,
+	    NULL);
diff --git a/zephyr/test/drivers/default/src/console_cmd/tcpci_dump.c b/zephyr/test/drivers/default/src/console_cmd/tcpci_dump.c
new file mode 100644
index 0000000000..fc8533280b
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/tcpci_dump.c
@@ -0,0 +1,46 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "ec_commands.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+ZTEST_USER(console_cmd_tcpci_dump, test_no_params)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "tcpci_dump");
+
+	zassert_equal(rv, EC_ERROR_PARAM_COUNT, "Expected %d, but got %d",
+		      EC_ERROR_PARAM_COUNT, rv);
+}
+
+ZTEST_USER(console_cmd_tcpci_dump, test_good_index)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "tcpci_dump 0"),
+		   "Failed index 0 print");
+}
+
+ZTEST_USER(console_cmd_tcpci_dump, test_bad_index)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "tcpci_dump 84");
+
+	zassert_equal(rv, EC_ERROR_INVAL, "Expected %d, but got %d",
+		      EC_ERROR_INVAL, rv);
+}
+
+static void console_cmd_tcpci_dump_begin(void *data)
+{
+	ARG_UNUSED(data);
+
+	/* Assume we have at least one TCPC */
+	zassert_true(board_get_charger_chip_count() > 0,
+		     "Insufficient TCPCs found");
+}
+
+ZTEST_SUITE(console_cmd_tcpci_dump, drivers_predicate_post_main, NULL,
+	    console_cmd_tcpci_dump_begin, NULL, NULL);
diff --git a/zephyr/test/drivers/default/src/console_cmd/usb_pd_console.c b/zephyr/test/drivers/default/src/console_cmd/usb_pd_console.c
new file mode 100644
index 0000000000..859205f403
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/usb_pd_console.c
@@ -0,0 +1,403 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "ec_commands.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "usb_pd.h"
+#include "usb_pd_dpm_sm.h"
+#include "usb_prl_sm.h"
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+static void console_cmd_usb_pd_after(void *fixture)
+{
+	ARG_UNUSED(fixture);
+
+	/* TODO (b/230059737) */
+	test_set_chipset_to_g3();
+	k_sleep(K_SECONDS(1));
+	test_set_chipset_to_s0();
+	k_sleep(K_SECONDS(10));
+
+	/* Keep port used by testsuite enabled (default state) */
+	pd_comm_enable(0, 1);
+	pd_set_suspend(0, 0);
+	pd_set_bist_share_mode(0);
+}
+
+ZTEST_SUITE(console_cmd_usb_pd, drivers_predicate_post_main, NULL, NULL,
+	    console_cmd_usb_pd_after, NULL);
+
+ZTEST_USER(console_cmd_usb_pd, test_too_few_args)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "pd");
+	zassert_equal(rv, EC_ERROR_PARAM_COUNT, "Expected %d, but got %d",
+		      EC_ERROR_PARAM_COUNT, rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "pd 0");
+	zassert_equal(rv, EC_ERROR_PARAM_COUNT, "Expected %d, but got %d",
+		      EC_ERROR_PARAM_COUNT, rv);
+}
+
+ZTEST_USER(console_cmd_usb_pd, test_dump)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "pd dump 0");
+	zassert_equal(rv, EC_SUCCESS, "Expected %d, but got %d", EC_SUCCESS,
+		      rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "pd dump 4");
+	zassert_equal(rv, EC_SUCCESS, "Expected %d, but got %d", EC_SUCCESS,
+		      rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "pd dump -4");
+	zassert_equal(rv, EC_SUCCESS, "Expected %d, but got %d", EC_SUCCESS,
+		      rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "pd dump x");
+	zassert_equal(rv, EC_ERROR_PARAM2, "Expected %d, but got %d",
+		      EC_ERROR_PARAM2, rv);
+}
+
+ZTEST_USER(console_cmd_usb_pd, test_trysrc)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "pd trysrc 0");
+	zassert_equal(rv, EC_SUCCESS, "Expected %d, but got %d", EC_SUCCESS,
+		      rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "pd trysrc 2");
+	zassert_equal(rv, EC_SUCCESS, "Expected %d, but got %d", EC_SUCCESS,
+		      rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "pd trysrc 5");
+	zassert_equal(rv, EC_ERROR_PARAM3, "Expected %d, but got %d",
+		      EC_ERROR_PARAM3, rv);
+}
+
+ZTEST_USER(console_cmd_usb_pd, test_version)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "pd version");
+	zassert_equal(rv, EC_SUCCESS, "Expected %d, but got %d", EC_SUCCESS,
+		      rv);
+}
+
+ZTEST_USER(console_cmd_usb_pd, test_bad_port)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "pd 5");
+	zassert_equal(rv, EC_ERROR_PARAM_COUNT, "Expected %d, but got %d",
+		      EC_ERROR_PARAM_COUNT, rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "pd 5 tx");
+	zassert_equal(rv, EC_ERROR_PARAM2, "Expected %d, but got %d",
+		      EC_ERROR_PARAM2, rv);
+}
+
+ZTEST_USER(console_cmd_usb_pd, test_tx)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "pd 0 tx");
+	zassert_equal(rv, EC_SUCCESS, "Expected %d, but got %d", EC_SUCCESS,
+		      rv);
+}
+
+ZTEST_USER(console_cmd_usb_pd, test_charger)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "pd 0 charger");
+	zassert_equal(rv, EC_SUCCESS, "Expected %d, but got %d", EC_SUCCESS,
+		      rv);
+}
+
+ZTEST_USER(console_cmd_usb_pd, test_dev)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "pd 0 dev");
+	zassert_equal(rv, EC_SUCCESS, "Expected %d, but got %d", EC_SUCCESS,
+		      rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "pd 0 dev 20");
+	zassert_equal(rv, EC_SUCCESS, "Expected %d, but got %d", EC_SUCCESS,
+		      rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "pd 0 dev x");
+	zassert_equal(rv, EC_ERROR_PARAM3, "Expected %d, but got %d",
+		      EC_ERROR_PARAM3, rv);
+}
+
+ZTEST_USER(console_cmd_usb_pd, test_disable)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "pd 0 disable");
+	zassert_equal(rv, EC_SUCCESS, "Expected %d, but got %d", EC_SUCCESS,
+		      rv);
+}
+
+ZTEST_USER(console_cmd_usb_pd, test_enable)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "pd 0 enable");
+	zassert_equal(rv, EC_SUCCESS, "Expected %d, but got %d", EC_SUCCESS,
+		      rv);
+}
+
+ZTEST_USER(console_cmd_usb_pd, test_suspend)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "pd 0 suspend");
+	zassert_equal(rv, EC_SUCCESS, "Expected %d, but got %d", EC_SUCCESS,
+		      rv);
+}
+
+ZTEST_USER(console_cmd_usb_pd, test_resume)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "pd 0 resume");
+	zassert_equal(rv, EC_SUCCESS, "Expected %d, but got %d", EC_SUCCESS,
+		      rv);
+}
+
+ZTEST_USER(console_cmd_usb_pd, test_bistsharemode)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "pd bistsharemode enable");
+	zassert_equal(rv, EC_SUCCESS, "Expected %d, but got %d", EC_SUCCESS,
+		      rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "pd bistsharemode disable");
+	zassert_equal(rv, EC_SUCCESS, "Expected %d, but got %d", EC_SUCCESS,
+		      rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "pd bistsharemode foo");
+	zassert_equal(rv, EC_ERROR_PARAM2, "Expected %d, but got %d",
+		      EC_ERROR_PARAM2, rv);
+}
+
+ZTEST_USER(console_cmd_usb_pd, test_hard)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "pd 0 hard");
+	zassert_equal(rv, EC_SUCCESS, "Expected %d, but got %d", EC_SUCCESS,
+		      rv);
+}
+
+ZTEST_USER(console_cmd_usb_pd, test_soft)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "pd 0 soft");
+	zassert_equal(rv, EC_SUCCESS, "Expected %d, but got %d", EC_SUCCESS,
+		      rv);
+}
+
+ZTEST_USER(console_cmd_usb_pd, test_swap)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "pd 0 swap");
+	zassert_equal(rv, EC_ERROR_PARAM_COUNT, "Expected %d, but got %d",
+		      EC_ERROR_PARAM_COUNT, rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "pd 0 swap power");
+	zassert_equal(rv, EC_SUCCESS, "Expected %d, but got %d", EC_SUCCESS,
+		      rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "pd 0 swap data");
+	zassert_equal(rv, EC_SUCCESS, "Expected %d, but got %d", EC_SUCCESS,
+		      rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "pd 0 swap vconn");
+	zassert_equal(rv, EC_SUCCESS, "Expected %d, but got %d", EC_SUCCESS,
+		      rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "pd 0 swap x");
+	zassert_equal(rv, EC_ERROR_PARAM3, "Expected %d, but got %d",
+		      EC_ERROR_PARAM3, rv);
+}
+
+ZTEST_USER(console_cmd_usb_pd, test_dualrole)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "pd 0 dualrole");
+	zassert_equal(rv, EC_SUCCESS, "Expected %d, but got %d", EC_SUCCESS,
+		      rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "pd 0 dualrole on");
+	zassert_equal(rv, EC_SUCCESS, "Expected %d, but got %d", EC_SUCCESS,
+		      rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "pd 0 dualrole off");
+	zassert_equal(rv, EC_SUCCESS, "Expected %d, but got %d", EC_SUCCESS,
+		      rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "pd 0 dualrole freeze");
+	zassert_equal(rv, EC_SUCCESS, "Expected %d, but got %d", EC_SUCCESS,
+		      rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "pd 0 dualrole sink");
+	zassert_equal(rv, EC_SUCCESS, "Expected %d, but got %d", EC_SUCCESS,
+		      rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "pd 0 dualrole source");
+	zassert_equal(rv, EC_SUCCESS, "Expected %d, but got %d", EC_SUCCESS,
+		      rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "pd 0 dualrole x");
+	zassert_equal(rv, EC_ERROR_PARAM4, "Expected %d, but got %d",
+		      EC_ERROR_PARAM4, rv);
+
+	pd_set_dual_role(0, PD_DRP_TOGGLE_OFF);
+	CHECK_CONSOLE_CMD("pd 0 dualrole", "dual-role toggling: off",
+			  EC_SUCCESS);
+
+	pd_set_dual_role(0, PD_DRP_FREEZE);
+	CHECK_CONSOLE_CMD("pd 0 dualrole", "dual-role toggling: freeze",
+			  EC_SUCCESS);
+
+	pd_set_dual_role(0, PD_DRP_FORCE_SINK);
+	CHECK_CONSOLE_CMD("pd 0 dualrole", "dual-role toggling: force sink",
+			  EC_SUCCESS);
+
+	pd_set_dual_role(0, PD_DRP_FORCE_SOURCE);
+	CHECK_CONSOLE_CMD("pd 0 dualrole", "dual-role toggling: force source",
+			  EC_SUCCESS);
+}
+
+ZTEST_USER(console_cmd_usb_pd, test_state)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "pd 0 state");
+	zassert_equal(rv, EC_SUCCESS, "Expected %d, but got %d", EC_SUCCESS,
+		      rv);
+}
+
+ZTEST_USER(console_cmd_usb_pd, test_srccaps)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "pd 0 srccaps");
+	zassert_equal(rv, EC_SUCCESS, "Expected %d, but got %d", EC_SUCCESS,
+		      rv);
+}
+
+ZTEST_USER(console_cmd_usb_pd, test_timer)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "pd 0 timer");
+	zassert_equal(rv, EC_SUCCESS, "Expected %d, but got %d", EC_SUCCESS,
+		      rv);
+}
+
+ZTEST_USER(console_cmd_usb_pd, test_cc)
+{
+	char expected_output[10];
+
+	snprintf(expected_output, sizeof(expected_output), "C0 CC%d",
+		 pd_get_task_cc_state(0));
+	CHECK_CONSOLE_CMD("pd 0 cc", expected_output, EC_SUCCESS);
+}
+
+static void set_device_vdo(int port, enum tcpci_msg_type type)
+{
+	union tbt_mode_resp_device device_resp;
+	struct pd_discovery *dev_disc;
+
+	dev_disc = pd_get_am_discovery_and_notify_access(port, type);
+	dev_disc->svid_cnt = 1;
+	dev_disc->svids[0].svid = USB_VID_INTEL;
+	dev_disc->svids[0].discovery = PD_DISC_COMPLETE;
+	dev_disc->svids[0].mode_cnt = 1;
+	device_resp.tbt_alt_mode = TBT_ALTERNATE_MODE;
+	device_resp.tbt_adapter = TBT_ADAPTER_TBT3;
+	device_resp.intel_spec_b0 = VENDOR_SPECIFIC_NOT_SUPPORTED;
+	device_resp.vendor_spec_b0 = VENDOR_SPECIFIC_NOT_SUPPORTED;
+	device_resp.vendor_spec_b1 = VENDOR_SPECIFIC_NOT_SUPPORTED;
+	dev_disc->svids[0].mode_vdo[0] = device_resp.raw_value;
+}
+
+static void set_active_cable_type(int port, enum tcpci_msg_type type,
+				  enum idh_ptype ptype)
+{
+	struct pd_discovery *dev_disc;
+
+	dev_disc = pd_get_am_discovery_and_notify_access(port, type);
+	dev_disc->identity.idh.product_type = ptype;
+	prl_set_rev(port, type, PD_REV30);
+}
+
+ZTEST_USER(console_cmd_usb_pd, test_pe)
+{
+	int rv;
+
+	pd_set_identity_discovery(0, TCPCI_MSG_SOP, PD_DISC_COMPLETE);
+
+	rv = shell_execute_cmd(get_ec_shell(), "pe 0 dump");
+	zassert_ok(rv, "Expected %d, but got %d", EC_SUCCESS, rv);
+
+	set_device_vdo(0, TCPCI_MSG_SOP);
+	rv = shell_execute_cmd(get_ec_shell(), "pe 0 dump");
+	zassert_ok(rv, "Expected %d, but got %d", EC_SUCCESS, rv);
+
+	/* Handle error scenarios */
+	rv = shell_execute_cmd(get_ec_shell(), "pe 0");
+	zassert_equal(rv, EC_ERROR_PARAM_COUNT, "Expected %d, but got %d",
+		      EC_ERROR_PARAM_COUNT, rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "pe x dump");
+	zassert_equal(rv, EC_ERROR_PARAM2, "Expected %d, but got %d",
+		      EC_ERROR_PARAM2, rv);
+}
+
+ZTEST_USER(console_cmd_usb_pd, test_pdcable)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "pdcable 0");
+	zassert_ok(rv, "Expected %d, but got %d", EC_SUCCESS, rv);
+
+	set_device_vdo(0, TCPCI_MSG_SOP_PRIME);
+
+	/* Set active cable type IDH_PTYPE_ACABLE */
+	set_active_cable_type(0, TCPCI_MSG_SOP_PRIME, IDH_PTYPE_ACABLE);
+	rv = shell_execute_cmd(get_ec_shell(), "pdcable 0");
+	zassert_ok(rv, "Expected %d, but got %d", EC_SUCCESS, rv);
+
+	/* Set active cable type IDH_PTYPE_PCABLE */
+	set_active_cable_type(0, TCPCI_MSG_SOP_PRIME, IDH_PTYPE_PCABLE);
+	rv = shell_execute_cmd(get_ec_shell(), "pdcable 0");
+	zassert_ok(rv, "Expected %d, but got %d", EC_SUCCESS, rv);
+
+	/* Handle error scenarios */
+	rv = shell_execute_cmd(get_ec_shell(), "pdcable");
+	zassert_equal(rv, EC_ERROR_PARAM_COUNT, "Expected %d, but got %d",
+		      EC_ERROR_PARAM_COUNT, rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "pdcable t");
+	zassert_equal(rv, EC_ERROR_PARAM2, "Expected %d, but got %d",
+		      EC_ERROR_PARAM2, rv);
+}
diff --git a/zephyr/test/drivers/default/src/console_cmd/vboot_hash.c b/zephyr/test/drivers/default/src/console_cmd/vboot_hash.c
new file mode 100644
index 0000000000..83a14ff46f
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/vboot_hash.c
@@ -0,0 +1,237 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "console.h"
+#include "flash.h"
+#include "printf.h"
+#include "sha256.h"
+#include "system.h"
+#include "test/drivers/test_state.h"
+#include "vboot_hash.h"
+
+#include <string.h>
+
+#include <zephyr/fff.h>
+#include <zephyr/shell/shell_dummy.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/ztest.h>
+
+#define CUSTOM_HASH_LENGTH (32)
+
+struct console_cmd_hash_fixture {
+	uint8_t rw_hash[SHA256_DIGEST_SIZE];
+	uint8_t ro_hash[SHA256_DIGEST_SIZE];
+};
+
+ZTEST_F(console_cmd_hash, test_get_rw)
+{
+	const char *outbuffer;
+	size_t buffer_size;
+
+	/* Start calculating the RW image hash */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "hash rw"), NULL);
+
+	/* Wait for completion */
+	WAIT_FOR(!vboot_hash_in_progress(), 1000000, k_sleep(K_MSEC(10)));
+
+	/* Call again with no args to see the resulting hash */
+	shell_backend_dummy_clear_output(get_ec_shell());
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "hash"), NULL);
+	outbuffer =
+		shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+
+	/* The RW hash should be reported. */
+	char hash_buf[hex_str_buf_size(SHA256_DIGEST_SIZE)];
+
+	snprintf_hex_buffer(hash_buf, sizeof(hash_buf),
+			    HEX_BUF(fixture->rw_hash, SHA256_DIGEST_SIZE));
+
+	zassert_ok(!strstr(outbuffer, hash_buf), "Output was: `%s`", outbuffer);
+}
+
+ZTEST_F(console_cmd_hash, test_get_ro)
+{
+	const char *outbuffer;
+	size_t buffer_size;
+
+	/* Start calculating the RW image hash */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "hash ro"), NULL);
+
+	/* Wait for completion */
+	WAIT_FOR(!vboot_hash_in_progress(), 1000000, k_sleep(K_MSEC(10)));
+
+	/* Call again with no args to see the resulting hash */
+	shell_backend_dummy_clear_output(get_ec_shell());
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "hash"), NULL);
+	outbuffer =
+		shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+
+	/* The RO hash should be reported. */
+	char hash_buf[hex_str_buf_size(SHA256_DIGEST_SIZE)];
+
+	snprintf_hex_buffer(hash_buf, sizeof(hash_buf),
+			    HEX_BUF(fixture->ro_hash, SHA256_DIGEST_SIZE));
+
+	zassert_ok(!strstr(outbuffer, hash_buf), "Output was: `%s`", outbuffer);
+}
+
+ZTEST_F(console_cmd_hash, test_abort)
+{
+	const char *outbuffer;
+	size_t buffer_size;
+
+	/* Start calculating the RO image hash */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "hash ro"), NULL);
+
+	/* Immediately cancel */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "hash abort"), NULL);
+
+	/* Call again with no args to check status */
+	shell_backend_dummy_clear_output(get_ec_shell());
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "hash"), NULL);
+	outbuffer =
+		shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+
+	/* Depending on timing, we should see one of these statuses */
+	zassert_true(strstr(outbuffer, "(invalid)") ||
+			     strstr(outbuffer, "(aborting)"),
+		     "Output was: `%s`", outbuffer);
+}
+
+ZTEST_F(console_cmd_hash, test_custom_range)
+{
+	char command[256];
+	uint32_t offset = flash_get_rw_offset(system_get_active_copy());
+
+	/* Hash an arbitrary portion of the flash */
+	snprintf(command, sizeof(command), "hash 0x%x %u", offset,
+		 CUSTOM_HASH_LENGTH);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), command));
+
+	WAIT_FOR(!vboot_hash_in_progress(), 1000000, k_sleep(K_MSEC(10)));
+
+	/* Calculate the expected hash */
+	struct sha256_ctx hash_ctx;
+	uint8_t *hash;
+	uint8_t buf[CUSTOM_HASH_LENGTH];
+
+	zassert_ok(crec_flash_read(offset, sizeof(buf), buf));
+	SHA256_init(&hash_ctx);
+	SHA256_update(&hash_ctx, buf, sizeof(buf));
+	hash = SHA256_final(&hash_ctx);
+
+	/* Call again with no args to check status */
+	const char *outbuffer;
+	size_t buffer_size;
+
+	shell_backend_dummy_clear_output(get_ec_shell());
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "hash"));
+	outbuffer =
+		shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+
+	/* Compare hashes */
+	char hash_buf[hex_str_buf_size(SHA256_DIGEST_SIZE)];
+
+	snprintf_hex_buffer(hash_buf, sizeof(hash_buf),
+			    HEX_BUF(hash, SHA256_DIGEST_SIZE));
+
+	zassert_ok(!strstr(outbuffer, hash_buf), "Output was: `%s`. Actual: %s",
+		   outbuffer, hash_buf);
+}
+
+ZTEST_F(console_cmd_hash, test_custom_range_with_nonce)
+{
+	char command[256];
+	uint32_t offset = flash_get_rw_offset(system_get_active_copy());
+	int nonce = 1234;
+
+	/* Hash an arbitrary portion of the flash w/ nonce */
+	snprintf(command, sizeof(command), "hash 0x%x %u %d", offset,
+		 CUSTOM_HASH_LENGTH, nonce);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), command));
+
+	WAIT_FOR(!vboot_hash_in_progress(), 1000000, k_sleep(K_MSEC(10)));
+
+	/* Calculate the expected hash */
+	struct sha256_ctx hash_ctx;
+	uint8_t *hash;
+	uint8_t buf[CUSTOM_HASH_LENGTH];
+
+	zassert_ok(crec_flash_read(offset, sizeof(buf), buf));
+	SHA256_init(&hash_ctx);
+	SHA256_update(&hash_ctx, (const uint8_t *)&nonce, sizeof(nonce));
+	SHA256_update(&hash_ctx, buf, sizeof(buf));
+	hash = SHA256_final(&hash_ctx);
+
+	/* Call again with no args to check status */
+	const char *outbuffer;
+	size_t buffer_size;
+
+	shell_backend_dummy_clear_output(get_ec_shell());
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "hash"));
+	outbuffer =
+		shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+
+	/* Compare hashes */
+	char hash_buf[hex_str_buf_size(SHA256_DIGEST_SIZE)];
+
+	snprintf_hex_buffer(hash_buf, sizeof(hash_buf),
+			    HEX_BUF(hash, SHA256_DIGEST_SIZE));
+
+	zassert_ok(!strstr(outbuffer, hash_buf), "Output was: `%s`. Actual: %s",
+		   outbuffer, hash_buf);
+}
+
+ZTEST(console_cmd_hash, test_invalid)
+{
+	/* Invalid subcommand */
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "hash foo"));
+
+	/* For custom ranges, non-numbers are invalid */
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "hash a b"));
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "hash 1 b"));
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "hash 1 2 c"));
+}
+
+static void *setup(void)
+{
+	static struct console_cmd_hash_fixture f;
+
+	return &f;
+}
+
+static void before(void *data)
+{
+	struct console_cmd_hash_fixture *f =
+		(struct console_cmd_hash_fixture *)data;
+	const uint8_t *hash_ptr;
+	int rv;
+
+	/* Stop and clear current hash */
+	vboot_hash_abort();
+
+	/* Get the RW hash and save it to our fixture */
+	rv = vboot_get_rw_hash(&hash_ptr);
+	zassert_ok(rv, "Got %d", rv);
+	memcpy(f->rw_hash, hash_ptr, sizeof(f->rw_hash));
+
+	/* Compute the RO hash, too */
+	rv = vboot_get_ro_hash(&hash_ptr);
+	zassert_ok(rv, "Got %d", rv);
+	memcpy(f->ro_hash, hash_ptr, sizeof(f->ro_hash));
+}
+
+static void after(void *data)
+{
+	ARG_UNUSED(data);
+
+	/* Stop and clear current hash */
+	vboot_hash_abort();
+
+	/* Wait a moment to allow the hashing to stop */
+	k_sleep(K_MSEC(100));
+}
+
+ZTEST_SUITE(console_cmd_hash, drivers_predicate_post_main, setup, before, after,
+	    NULL);
diff --git a/zephyr/test/drivers/default/src/console_cmd/version.c b/zephyr/test/drivers/default/src/console_cmd/version.c
new file mode 100644
index 0000000000..e3606b5d0e
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/version.c
@@ -0,0 +1,37 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "system.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/shell/shell_dummy.h>
+#include <zephyr/ztest.h>
+
+ZTEST_USER(console_cmd_version, test_no_args)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+	const char *outbuffer;
+	size_t buffer_size;
+
+	shell_backend_dummy_clear_output(shell_zephyr);
+
+	zassert_ok(shell_execute_cmd(shell_zephyr, "version"), NULL);
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+
+	zassert_true(buffer_size > 0, NULL);
+
+	/* Weakly verify some contents */
+	zassert_not_null(strstr(outbuffer, "Chip:"), NULL);
+	zassert_not_null(strstr(outbuffer, "Board:"), NULL);
+	zassert_not_null(strstr(outbuffer, "RO:"), NULL);
+	zassert_not_null(strstr(outbuffer, "RW:"), NULL);
+	zassert_not_null(strstr(outbuffer, "Build:"), NULL);
+}
+
+ZTEST_SUITE(console_cmd_version, drivers_predicate_post_main, NULL, NULL, NULL,
+	    NULL);
diff --git a/zephyr/test/drivers/default/src/console_cmd/waitms.c b/zephyr/test/drivers/default/src/console_cmd/waitms.c
new file mode 100644
index 0000000000..703e233568
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/waitms.c
@@ -0,0 +1,52 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "timer.h"
+
+#include <stdio.h>
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+static void test_int(int ms)
+{
+	char cmd[32];
+	unsigned long measured;
+	timestamp_t start;
+	timestamp_t end;
+
+	sprintf(cmd, "waitms %d", ms);
+	start = get_time();
+	zassert_ok(shell_execute_cmd(get_ec_shell(), cmd),
+		   "Failed to execute 'waitms' command");
+	end = get_time();
+	measured = (end.val - start.val) / 1000;
+	zassert_equal(measured, ms, "'waitms %d' failed, took %ld ms", ms,
+		      measured);
+}
+
+ZTEST_SUITE(console_cmd_waitms, NULL, NULL, NULL, NULL, NULL);
+
+ZTEST_USER(console_cmd_waitms, test_waitms)
+{
+	/*
+	 * Test across three orders of magnitude. Beyond ~3s the watchdog will
+	 * trigger so don't need to bother testing 10s of seconds or greater.
+	 */
+	test_int(0);
+	test_int(5);
+	test_int(75);
+	test_int(250);
+	test_int(1000);
+
+	/* A plain string should fail. */
+	zassert_true(shell_execute_cmd(get_ec_shell(), "waitms string"), NULL);
+
+	/* Floats and negative ints should fail. */
+	zassert_true(shell_execute_cmd(get_ec_shell(), "waitms 123.456"), NULL);
+	zassert_true(shell_execute_cmd(get_ec_shell(), "waitms -67.3"), NULL);
+	zassert_true(shell_execute_cmd(get_ec_shell(), "waitms -7"), NULL);
+}
diff --git a/zephyr/test/drivers/default/src/cros_cbi.c b/zephyr/test/drivers/default/src/cros_cbi.c
new file mode 100644
index 0000000000..2669abe21e
--- /dev/null
+++ b/zephyr/test/drivers/default/src/cros_cbi.c
@@ -0,0 +1,55 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cros_cbi.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/device.h>
+#include <zephyr/ztest.h>
+
+ZTEST(cros_cbi, test_check_match)
+{
+	int value;
+
+	value = cros_cbi_ssfc_check_match(
+		CBI_SSFC_VALUE_ID(DT_NODELABEL(base_sensor_0)));
+	zassert_true(value, "Expected cbi ssfc to match base_sensor_0");
+
+	value = cros_cbi_ssfc_check_match(
+		CBI_SSFC_VALUE_ID(DT_NODELABEL(base_sensor_1)));
+	zassert_false(value, "Expected cbi ssfc not to match base_sensor_1");
+
+	value = cros_cbi_ssfc_check_match(CBI_SSFC_VALUE_COUNT);
+	zassert_false(value, "Expected cbi ssfc to fail on invalid enum");
+}
+
+ZTEST(cros_cbi, test_fail_check_match)
+{
+	int value;
+
+	value = cros_cbi_ssfc_check_match(CBI_SSFC_VALUE_COUNT);
+	zassert_false(value,
+		      "Expected cbi ssfc to never match CBI_SSFC_VALUE_COUNT");
+}
+
+ZTEST(cros_cbi, test_fw_config)
+{
+	uint32_t value;
+	int ret;
+
+	ret = cros_cbi_get_fw_config(FW_CONFIG_FIELD_1, &value);
+	zassert_true(ret == 0,
+		     "Expected no error return from cros_cbi_get_fw_config");
+	zassert_true(value == FW_FIELD_1_B,
+		     "Expected field value to match FW_FIELD_1_B as default");
+
+	ret = cros_cbi_get_fw_config(FW_CONFIG_FIELD_2, &value);
+	zassert_true(ret == 0,
+		     "Expected no error return from cros_cbi_get_fw_config");
+	zassert_false(value == FW_FIELD_2_X,
+		      "Expected field value to not match FW_FIELD_2_X");
+}
+
+ZTEST_SUITE(cros_cbi, drivers_predicate_post_main, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/drivers/default/src/espi.c b/zephyr/test/drivers/default/src/espi.c
new file mode 100644
index 0000000000..86428d4ba6
--- /dev/null
+++ b/zephyr/test/drivers/default/src/espi.c
@@ -0,0 +1,278 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+#include "gpio.h"
+#include "host_command.h"
+#include "system.h"
+#include "test/drivers/test_mocks.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <string.h>
+
+#include <zephyr/fff.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+#define PORT 0
+
+#define AC_OK_OD_GPIO_NAME "acok_od"
+
+static void espi_before(void *state)
+{
+	ARG_UNUSED(state);
+	RESET_FAKE(system_is_locked);
+}
+
+static void espi_after(void *state)
+{
+	ARG_UNUSED(state);
+	RESET_FAKE(system_is_locked);
+}
+
+ZTEST_USER(espi, test_host_command_get_protocol_info)
+{
+	struct ec_response_get_protocol_info response;
+	struct host_cmd_handler_args args;
+
+	zassert_ok(ec_cmd_get_protocol_info(&args, &response));
+	zassert_equal(args.response_size, sizeof(response));
+	zassert_equal(response.protocol_versions, BIT(3));
+	zassert_equal(response.max_request_packet_size, EC_LPC_HOST_PACKET_SIZE,
+		      NULL);
+	zassert_equal(response.max_response_packet_size,
+		      EC_LPC_HOST_PACKET_SIZE, NULL);
+	zassert_equal(response.flags, 0);
+}
+
+ZTEST_USER(espi, test_host_command_usb_pd_power_info)
+{
+	/* Only test we've enabled the command */
+	struct ec_response_usb_pd_power_info response;
+	struct ec_params_usb_pd_power_info params = { .port = PORT };
+	struct host_cmd_handler_args args;
+
+	zassert_ok(ec_cmd_usb_pd_power_info(&args, &params, &response));
+	zassert_equal(args.response_size, sizeof(response));
+}
+
+ZTEST_USER(espi, test_host_command_typec_status)
+{
+	/* Only test we've enabled the command */
+	struct ec_params_typec_status params = { .port = PORT };
+	struct ec_response_typec_status response;
+	struct host_cmd_handler_args args;
+
+	zassert_ok(ec_cmd_typec_status(&args, &params, &response));
+	zassert_equal(args.response_size, sizeof(response));
+}
+
+ZTEST_USER(espi, test_host_command_gpio_get_v0)
+{
+	struct ec_params_gpio_get p = {
+		/* Checking for AC enabled */
+		.name = AC_OK_OD_GPIO_NAME,
+	};
+	struct ec_response_gpio_get response;
+
+	struct host_cmd_handler_args args;
+
+	set_ac_enabled(true);
+
+	zassert_ok(ec_cmd_gpio_get(&args, &p, &response));
+	zassert_equal(args.response_size, sizeof(response));
+	zassert_true(response.val);
+
+	set_ac_enabled(false);
+
+	zassert_ok(ec_cmd_gpio_get(&args, &p, &response));
+	zassert_equal(args.response_size, sizeof(response));
+	zassert_false(response.val);
+}
+
+ZTEST_USER(espi, test_host_command_gpio_get_v1_get_by_name)
+{
+	struct ec_params_gpio_get_v1 p = {
+		.subcmd = EC_GPIO_GET_BY_NAME,
+		/* Checking for AC enabled */
+		.get_value_by_name = {
+			   AC_OK_OD_GPIO_NAME,
+		},
+	};
+	struct ec_response_gpio_get_v1 response;
+
+	struct host_cmd_handler_args args;
+
+	set_ac_enabled(true);
+
+	zassert_ok(ec_cmd_gpio_get_v1(&args, &p, &response));
+	zassert_equal(args.response_size, sizeof(response.get_value_by_name),
+		      NULL);
+	zassert_true(response.get_info.val);
+
+	set_ac_enabled(false);
+
+	zassert_ok(ec_cmd_gpio_get_v1(&args, &p, &response));
+	zassert_equal(args.response_size, sizeof(response.get_value_by_name),
+		      NULL);
+	zassert_false(response.get_info.val);
+}
+
+ZTEST_USER(espi, test_host_command_gpio_get_v1_get_count)
+{
+	struct ec_params_gpio_get_v1 p = {
+		.subcmd = EC_GPIO_GET_COUNT,
+	};
+	struct ec_response_gpio_get_v1 response;
+
+	struct host_cmd_handler_args args;
+
+	zassert_ok(ec_cmd_gpio_get_v1(&args, &p, &response), NULL);
+	zassert_equal(args.response_size, sizeof(response.get_count), NULL);
+	zassert_equal(response.get_count.val, GPIO_COUNT, NULL);
+}
+
+ZTEST_USER(espi, test_host_command_gpio_get_v1_get_info)
+{
+	const enum gpio_signal signal = GPIO_SIGNAL(DT_NODELABEL(gpio_acok_od));
+	struct ec_params_gpio_get_v1 p = {
+		.subcmd = EC_GPIO_GET_INFO,
+		.get_info = {
+			.index = signal,
+		},
+	};
+	struct ec_response_gpio_get_v1 response;
+
+	struct host_cmd_handler_args args;
+
+	set_ac_enabled(true);
+
+	zassert_ok(ec_cmd_gpio_get_v1(&args, &p, &response), NULL);
+	zassert_equal(args.response_size, sizeof(response), NULL);
+	zassert_ok(strcmp(response.get_info.name, AC_OK_OD_GPIO_NAME), NULL);
+	zassert_true(response.get_info.val, NULL);
+
+	set_ac_enabled(false);
+
+	zassert_ok(ec_cmd_gpio_get_v1(&args, &p, &response), NULL);
+	zassert_equal(args.response_size, sizeof(response), NULL);
+	zassert_ok(strcmp(response.get_info.name, AC_OK_OD_GPIO_NAME), NULL);
+	zassert_false(response.get_info.val, NULL);
+}
+
+ZTEST_USER(espi, test_host_command_gpio_set)
+{
+	struct nothing {
+		int place_holder;
+	};
+	const struct gpio_dt_spec *gp = GPIO_DT_FROM_NODELABEL(gpio_test);
+	struct ec_params_gpio_set p = {
+		.name = "test",
+		.val = 0,
+	};
+
+	/* Force value to 1 to see change */
+	zassert_ok(gpio_pin_set_dt(gp, 1), NULL);
+
+	zassert_ok(ec_cmd_gpio_set(NULL, &p), NULL);
+	zassert_equal(gpio_pin_get_dt(gp), p.val, NULL);
+
+	p.val = 1;
+
+	zassert_ok(ec_cmd_gpio_set(NULL, &p), NULL);
+	zassert_equal(gpio_pin_get_dt(gp), p.val, NULL);
+}
+
+ZTEST(espi, test_hc_gpio_get_v0_invalid_name)
+{
+	struct ec_response_gpio_get response;
+	struct ec_params_gpio_get params = { .name = "INVALID_GPIO_NAME" };
+
+	zassert_equal(EC_RES_ERROR, ec_cmd_gpio_get(NULL, &params, &response),
+		      NULL);
+}
+
+ZTEST(espi, test_hc_gpio_get_v1_get_by_name_invalid_name)
+{
+	struct ec_response_gpio_get_v1 response;
+	struct ec_params_gpio_get_v1 params = {
+		.subcmd = EC_GPIO_GET_BY_NAME,
+		.get_value_by_name.name = "INVALID_GPIO_NAME",
+	};
+
+	zassert_equal(EC_RES_ERROR,
+		      ec_cmd_gpio_get_v1(NULL, &params, &response), NULL);
+}
+
+ZTEST(espi, test_hc_gpio_get_v1_get_info_invalid_index)
+{
+	struct ec_response_gpio_get_v1 response;
+	struct ec_params_gpio_get_v1 params = {
+		.subcmd = EC_GPIO_GET_INFO,
+		.get_info.index = GPIO_COUNT,
+	};
+
+	zassert_equal(EC_RES_ERROR,
+		      ec_cmd_gpio_get_v1(NULL, &params, &response), NULL);
+}
+
+ZTEST(espi, test_hc_gpio_get_v1_invalid_subcmd)
+{
+	struct ec_response_gpio_get_v1 response;
+	struct ec_params_gpio_get_v1 params = {
+		.subcmd = EC_CMD_GPIO_GET,
+	};
+
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      ec_cmd_gpio_get_v1(NULL, &params, &response), NULL);
+}
+
+/* EC_CMD_GET_FEATURES */
+ZTEST_USER(espi, test_host_command_ec_cmd_get_features)
+{
+	struct ec_response_get_features response;
+
+	int rv = ec_cmd_get_features(NULL, &response);
+
+	zassert_equal(rv, EC_RES_SUCCESS, "Expected %d, but got %d",
+		      EC_RES_SUCCESS, rv);
+
+	/* Check features returned */
+	uint32_t feature_mask;
+
+	feature_mask = EC_FEATURE_MASK_0(EC_FEATURE_FLASH);
+	feature_mask |= EC_FEATURE_MASK_0(EC_FEATURE_MOTION_SENSE);
+	feature_mask |= EC_FEATURE_MASK_0(EC_FEATURE_KEYB);
+	zassert_true((response.flags[0] & feature_mask),
+		     "Known features were not returned.");
+	feature_mask = EC_FEATURE_MASK_1(EC_FEATURE_UNIFIED_WAKE_MASKS);
+	feature_mask |= EC_FEATURE_MASK_1(EC_FEATURE_HOST_EVENT64);
+	feature_mask |= EC_FEATURE_MASK_1(EC_FEATURE_EXEC_IN_RAM);
+	zassert_true((response.flags[1] & feature_mask),
+		     "Known features were not returned.");
+}
+
+ZTEST(espi, test_hc_gpio_set_system_is_locked)
+{
+	struct ec_params_gpio_set params;
+
+	system_is_locked_fake.return_val = 1;
+	zassert_equal(EC_RES_ACCESS_DENIED, ec_cmd_gpio_set(NULL, &params),
+		      NULL);
+}
+
+ZTEST(espi, test_hc_gpio_set_invalid_gpio_name)
+{
+	struct ec_params_gpio_set params = {
+		.name = "",
+		.val = 0,
+	};
+
+	zassert_equal(EC_RES_ERROR, ec_cmd_gpio_set(NULL, &params), NULL);
+}
+
+ZTEST_SUITE(espi, drivers_predicate_post_main, NULL, espi_before, espi_after,
+	    NULL);
diff --git a/zephyr/test/drivers/default/src/gpio.c b/zephyr/test/drivers/default/src/gpio.c
new file mode 100644
index 0000000000..e9a89d9b68
--- /dev/null
+++ b/zephyr/test/drivers/default/src/gpio.c
@@ -0,0 +1,563 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ * @brief Unit Tests for GPIO.
+ */
+
+#include "common.h"
+#include "ec_tasks.h"
+#include "gpio.h"
+#include "gpio/gpio.h"
+#include "gpio/gpio_int.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_mocks.h"
+#include "test/drivers/test_state.h"
+#include "util.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/ztest.h>
+
+extern bool gpio_test_interrupt_triggered;
+
+/* Function signature for shim/src/gpio.c test_export_static */
+int init_gpios(const struct device *unused);
+
+/**
+ * @brief TestPurpose: Verify Zephyr to EC GPIO bitmask conversion.
+ *
+ * @details
+ * Validate Zephyr to EC GPIO bitmask conversion.
+ *
+ * Expected Results
+ *  - GPIO bitmask conversions are successful
+ */
+ZTEST(gpio, test_convert_from_zephyr_flags)
+{
+	int retval;
+	struct {
+		int zephyr_bmask;
+		gpio_flags_t expected_ec_bmask;
+	} validate[] = {
+		{ GPIO_DISCONNECTED, GPIO_FLAG_NONE },
+		{ GPIO_OUTPUT_INIT_LOW, GPIO_LOW },
+		{ GPIO_OUTPUT_INIT_HIGH, GPIO_HIGH },
+		{ GPIO_VOLTAGE_1P8, GPIO_SEL_1P8V },
+		{ GPIO_INT_ENABLE, GPIO_FLAG_NONE },
+		{ GPIO_INT_ENABLE | GPIO_INT_EDGE, GPIO_FLAG_NONE },
+		{ GPIO_INT_ENABLE | GPIO_INT_EDGE | GPIO_INT_HIGH_1,
+		  GPIO_INT_F_RISING },
+		{ GPIO_INT_ENABLE | GPIO_INT_EDGE | GPIO_INT_LOW_0,
+		  GPIO_INT_F_FALLING },
+		{ GPIO_INT_ENABLE | GPIO_INT_HIGH_1, GPIO_INT_F_HIGH },
+		{ GPIO_INT_ENABLE | GPIO_INT_LOW_0, GPIO_INT_F_LOW },
+		{ GPIO_OUTPUT_INIT_LOGICAL, 0 },
+		{ GPIO_OPEN_DRAIN | GPIO_PULL_UP,
+		  GPIO_OPEN_DRAIN | GPIO_PULL_UP },
+	};
+	int num_tests = ARRAY_SIZE(validate);
+
+	for (int i = 0; i < num_tests; i++) {
+		retval = convert_from_zephyr_flags(validate[i].zephyr_bmask);
+		zassert_equal(validate[i].expected_ec_bmask, retval,
+			      "[%d] Expected 0x%08X, returned 0x%08X.", i,
+			      validate[i].expected_ec_bmask, retval);
+	}
+}
+
+/**
+ * @brief TestPurpose: Verify EC to Zephyr GPIO bitmask conversion.
+ *
+ * @details
+ * Validate EC to Zephyr GPIO bitmask conversion.
+ *
+ * Expected Results
+ *  - GPIO bitmask conversions are successful
+ */
+ZTEST(gpio, test_convert_to_zephyr_flags)
+{
+	gpio_flags_t retval;
+
+	struct {
+		gpio_flags_t ec_bmask;
+		int expected_zephyr_bmask;
+	} validate[] = {
+		{ GPIO_FLAG_NONE, GPIO_DISCONNECTED },
+		{ GPIO_LOW, GPIO_OUTPUT_INIT_LOW },
+		{ GPIO_HIGH, GPIO_OUTPUT_INIT_HIGH },
+		{ GPIO_INT_F_RISING,
+		  GPIO_INT_ENABLE | GPIO_INT_EDGE | GPIO_INT_HIGH_1 },
+		{ GPIO_INT_F_FALLING,
+		  GPIO_INT_ENABLE | GPIO_INT_EDGE | GPIO_INT_LOW_0 },
+		{ GPIO_INT_F_LOW, GPIO_INT_ENABLE | GPIO_INT_LOW_0 },
+		{ GPIO_INT_F_HIGH, GPIO_INT_ENABLE | GPIO_INT_HIGH_1 },
+		{ GPIO_SEL_1P8V, GPIO_VOLTAGE_1P8 },
+	};
+	int num_tests = ARRAY_SIZE(validate);
+
+	for (int i = 0; i < num_tests; i++) {
+		retval = convert_to_zephyr_flags(validate[i].ec_bmask);
+		zassert_equal(validate[i].expected_zephyr_bmask, retval,
+			      "[%d] Expected 0x%08X, returned 0x%08X.", i,
+			      validate[i].expected_zephyr_bmask, retval);
+	}
+}
+
+/**
+ * @brief TestPurpose: Verify GPIO signal_is_gpio.
+ *
+ * @details
+ * Validate signal_is_gpio
+ *
+ * Expected Results
+ *  - Success
+ */
+ZTEST(gpio, test_signal_is_gpio)
+{
+	zassert_true(signal_is_gpio(GPIO_SIGNAL(DT_NODELABEL(gpio_test))),
+		     "Expected true");
+}
+
+/**
+ * @brief TestPurpose: Verify legacy API GPIO set/get level.
+ *
+ * @details
+ * Validate set/get level for legacy API
+ * This tests the legacy API, though no Zepyhr
+ * based code should use it.
+ *
+ * Expected Results
+ *  - Success
+ */
+ZTEST(gpio, test_legacy_gpio_get_set_level)
+{
+	enum gpio_signal signal = GPIO_SIGNAL(DT_NODELABEL(gpio_test));
+	int level;
+
+	/* Test invalid signal */
+	gpio_set_level(GPIO_COUNT, 0);
+	zassert_equal(0, gpio_get_level(GPIO_COUNT), "Expected level==0");
+
+	/* Test valid signal */
+	gpio_set_level(signal, 0);
+	zassert_ok(gpio_or_ioex_get_level(signal, &level));
+	zassert_equal(0, gpio_get_level(signal), "Expected level==0");
+	zassert_equal(0, level);
+
+	gpio_set_level(signal, 1);
+	zassert_ok(gpio_or_ioex_get_level(signal, &level));
+	zassert_equal(1, gpio_get_level(signal), "Expected level==1");
+	zassert_equal(1, level);
+
+	level = gpio_get_ternary(signal);
+	gpio_set_level_verbose(CC_CHIPSET, signal, 0);
+	zassert_equal(0, gpio_get_level(signal), "Expected level==0");
+}
+
+/**
+ * @brief TestPurpose: Verify legacy GPIO enable/disable interrupt.
+ *
+ * @details
+ * Validate gpio_enable_interrupt/gpio_disable_interrupt
+ * Uses the legacy API. No Zephyr code should use this API.
+ *
+ * Expected Results
+ *  - Success
+ */
+
+ZTEST(gpio, test_legacy_gpio_enable_interrupt)
+{
+	enum gpio_signal signal = GPIO_SIGNAL(DT_NODELABEL(gpio_test));
+
+	gpio_test_interrupt_triggered = false;
+
+	/* Test invalid signal */
+	zassert_not_equal(EC_SUCCESS, gpio_disable_interrupt(GPIO_COUNT), NULL);
+	zassert_not_equal(EC_SUCCESS, gpio_enable_interrupt(GPIO_COUNT), NULL);
+	zassert_false(gpio_test_interrupt_triggered);
+
+	/* Test valid signal */
+	zassert_ok(gpio_disable_interrupt(signal));
+	gpio_set_level(signal, 0);
+	zassert_false(gpio_test_interrupt_triggered);
+	gpio_set_level(signal, 1);
+	zassert_false(gpio_test_interrupt_triggered);
+
+	zassert_ok(gpio_enable_interrupt(signal));
+	gpio_set_level(signal, 0);
+	zassert_true(gpio_test_interrupt_triggered);
+	gpio_test_interrupt_triggered = false;
+	gpio_set_level(signal, 1);
+	zassert_true(gpio_test_interrupt_triggered);
+}
+
+/**
+ * @brief TestPurpose: Verify GPIO set/get level.
+ *
+ * @details
+ * Validate set/get level
+ *
+ * Expected Results
+ *  - Success
+ */
+ZTEST(gpio, test_gpio_pin_get_set_level)
+{
+	const struct gpio_dt_spec *gp = GPIO_DT_FROM_NODELABEL(gpio_test);
+
+	/* Test invalid signal */
+	zassert_equal(NULL, gpio_get_dt_spec(-1), "Expected NULL ptr");
+
+	zassert_false(gp == NULL, "Unexpected NULL ptr");
+	/* Test valid signal */
+	gpio_pin_set_dt(gp, 0);
+	zassert_equal(0, gpio_pin_get_dt(gp), "Expected level==0");
+
+	gpio_pin_set_dt(gp, 1);
+	zassert_equal(1, gpio_pin_get_dt(gp), "Expected level==1");
+}
+
+/**
+ * @brief TestPurpose: Verify GPIO get name.
+ *
+ * @details
+ * Validate gpio_get_name
+ *
+ * Expected Results
+ *  - Success
+ */
+ZTEST(gpio, test_gpio_get_name)
+{
+	enum gpio_signal signal = GPIO_SIGNAL(DT_NODELABEL(gpio_test));
+	const char *signal_name;
+
+	/* Test invalid signal */
+	signal_name = gpio_get_name(GPIO_COUNT);
+	zassert_mem_equal("UNIMPLEMENTED", signal_name, strlen(signal_name),
+			  "gpio_get_name returned a valid signal \'%s\'",
+			  signal_name);
+
+	/* Test valid signal */
+	signal_name = gpio_get_name(signal);
+	zassert_mem_equal("test", signal_name, strlen(signal_name),
+			  "gpio_get_name returned signal \'%s\'", signal_name);
+}
+
+/**
+ * @brief Helper function to get GPIO flags
+ *
+ * @param signal
+ * @return gpio_flags_t
+ */
+gpio_flags_t gpio_helper_get_flags(enum gpio_signal signal)
+{
+	const struct gpio_dt_spec *spec;
+	gpio_flags_t flags;
+
+	spec = gpio_get_dt_spec(signal);
+	gpio_emul_flags_get(spec->port, spec->pin, &flags);
+
+	return flags;
+}
+
+/**
+ * @brief TestPurpose: Verify GPIO get default flags.
+ *
+ * @details
+ * Validate gpio_get_default_flags
+ *
+ * Expected Results
+ *  - Success
+ */
+ZTEST(gpio, test_gpio_get_default_flags)
+{
+	enum gpio_signal signal = GPIO_SIGNAL(DT_NODELABEL(gpio_test));
+	gpio_flags_t flags;
+	gpio_flags_t flags_at_start[GPIO_COUNT];
+	int def_flags;
+
+	/* Snapshot of GPIO flags before testing */
+	for (int i = 0; i < GPIO_COUNT; i++)
+		flags_at_start[i] = gpio_helper_get_flags(i);
+
+	/* Test invalid signal */
+	def_flags = gpio_get_default_flags(GPIO_COUNT);
+	zassert_equal(0, def_flags, "Expected 0x0, returned 0x%08X", def_flags);
+	gpio_set_flags(GPIO_COUNT, GPIO_INPUT);
+
+	/* Verify flags didn't change */
+	for (int i = 0; i < GPIO_COUNT; i++) {
+		flags = gpio_helper_get_flags(i);
+		zassert_equal(flags_at_start[i], flags,
+			      "%s[%d] flags_at_start=0x%x, flags=0x%x",
+			      gpio_get_name(i), i, flags_at_start[i], flags);
+	}
+
+	/* Test valid signal */
+	def_flags = gpio_get_default_flags(signal);
+	zassert_equal(GPIO_INPUT | GPIO_OUTPUT, def_flags,
+		      "Expected 0x%08x, returned 0x%08X",
+		      GPIO_INPUT | GPIO_OUTPUT, def_flags);
+
+	gpio_set_flags(signal, GPIO_INPUT);
+	flags = gpio_helper_get_flags(signal);
+	zassert_equal(flags, GPIO_INPUT, "Flags set 0x%x", flags);
+
+	gpio_set_flags(signal, GPIO_OUTPUT);
+	flags = gpio_helper_get_flags(signal);
+	zassert_equal(flags, GPIO_OUTPUT, "Flags set 0x%x", flags);
+}
+
+/**
+ * @brief TestPurpose: Verify GPIO no-auto-init.
+ *
+ * @details
+ * Validate no-auto-init device tree property,
+ * which will not initialise the GPIO at startup.
+ *
+ * Expected Results
+ *  - Success
+ */
+ZTEST(gpio, test_gpio_no_auto_init)
+{
+	const struct gpio_dt_spec *gp = GPIO_DT_FROM_NODELABEL(gpio_no_init);
+	enum gpio_signal signal = GPIO_SIGNAL(DT_NODELABEL(gpio_no_init));
+	gpio_flags_t flags;
+
+	flags = gpio_helper_get_flags(signal);
+	zassert_equal(0, flags, "Expected 0x%08x, returned 0x%08X", 0, flags);
+
+	/* Configure pin. */
+	gpio_pin_configure_dt(gp, GPIO_INPUT | GPIO_OUTPUT);
+	flags = gpio_helper_get_flags(signal);
+	zassert_equal(flags, (GPIO_ACTIVE_LOW | GPIO_OUTPUT | GPIO_INPUT),
+		      "Flags set 0x%x", flags);
+}
+
+/**
+ * @brief TestPurpose: Verify GPIO reset.
+ *
+ * @details
+ * Validate gpio_reset
+ *
+ * Expected Results
+ *  - Success
+ */
+ZTEST(gpio, test_gpio_reset)
+{
+	enum gpio_signal signal = GPIO_SIGNAL(DT_NODELABEL(gpio_test));
+	gpio_flags_t flags;
+	gpio_flags_t flags_at_start[GPIO_COUNT];
+
+	/* Snapshot of GPIO flags before testing */
+	for (int i = 0; i < GPIO_COUNT; i++)
+		flags_at_start[i] = gpio_helper_get_flags(i);
+
+	/* Test reset on invalid signal */
+	gpio_reset(GPIO_COUNT);
+
+	/* Verify flags didn't change */
+	for (int i = 0; i < GPIO_COUNT; i++) {
+		flags = gpio_helper_get_flags(i);
+		zassert_equal(flags_at_start[i], flags,
+			      "%s[%d] flags_at_start=0x%x, flags=0x%x",
+			      gpio_get_name(i), i, flags_at_start[i], flags);
+	}
+
+	/* Test reset on valid signal */
+	gpio_set_flags(signal, GPIO_OUTPUT);
+	flags = gpio_helper_get_flags(signal);
+	zassert_equal(flags, GPIO_OUTPUT, "Flags set 0x%x", flags);
+
+	gpio_reset(signal);
+
+	flags = gpio_helper_get_flags(signal);
+	zassert_equal(flags, gpio_get_default_flags(signal), "Flags set 0x%x",
+		      flags);
+}
+
+ZTEST(gpio, test_gpio_save_port_config)
+{
+	const struct device *port =
+		DEVICE_DT_GET(DT_GPIO_CTLR(DT_NODELABEL(gpio_test), gpios));
+	const struct gpio_dt_spec *spec;
+	gpio_flags_t flags[32] = { 0 };
+	gpio_flags_t zephyr_flags;
+	gpio_flags_t flags_at_start[GPIO_COUNT];
+	int index = 0;
+
+	/* Snapshot of GPIO flags before testing */
+	for (int i = 0; i < GPIO_COUNT; i++) {
+		flags_at_start[i] = gpio_helper_get_flags(i);
+		gpio_set_flags(i, GPIO_OUTPUT);
+	}
+
+	/* save the current state of the port */
+	gpio_save_port_config(port, flags, sizeof(flags));
+
+	for (int i = 0; i < GPIO_COUNT; i++) {
+		spec = gpio_get_dt_spec(i);
+		if (spec->port == port) {
+			gpio_pin_get_config_dt(spec, &zephyr_flags);
+			zassert_equal(flags[index], zephyr_flags,
+				      "Flags get 0x%x", flags[index]);
+			index++;
+		}
+	}
+
+	for (int i = 0; i < GPIO_COUNT; ++i) {
+		gpio_set_flags(i, flags_at_start[i]);
+	}
+}
+
+ZTEST(gpio, test_gpio_restore_port_config)
+{
+	const struct device *port =
+		DEVICE_DT_GET(DT_GPIO_CTLR(DT_NODELABEL(gpio_test), gpios));
+	const struct gpio_dt_spec *spec;
+	gpio_flags_t flags[32] = { 0 };
+	gpio_flags_t zephyr_flags;
+	gpio_flags_t flags_at_start[GPIO_COUNT];
+	int index = 0;
+
+	/* Snapshot of GPIO flags before testing */
+	for (int i = 0; i < GPIO_COUNT; i++) {
+		flags_at_start[i] = gpio_helper_get_flags(i);
+		gpio_set_flags(i, GPIO_OUTPUT);
+	}
+
+	/* save the current state of the port */
+	gpio_save_port_config(port, flags, sizeof(flags));
+
+	/* reset the port */
+	gpio_reset_port(port);
+
+	/* restore the port config and check */
+	gpio_restore_port_config(port, flags, sizeof(flags));
+
+	for (int i = 0; i < GPIO_COUNT; i++) {
+		spec = gpio_get_dt_spec(i);
+		if (spec->port == port) {
+			gpio_pin_get_config_dt(spec, &zephyr_flags);
+			zassert_equal(flags[index], zephyr_flags,
+				      "Flags get 0x%x", flags[index]);
+			index++;
+		}
+	}
+
+	for (int i = 0; i < GPIO_COUNT; ++i) {
+		gpio_set_flags(i, flags_at_start[i]);
+	}
+}
+
+ZTEST(gpio, test_gpio_reset_port)
+{
+	const struct device *port =
+		DEVICE_DT_GET(DT_GPIO_CTLR(DT_NODELABEL(gpio_test), gpios));
+	enum gpio_signal signal = GPIO_SIGNAL(DT_NODELABEL(gpio_test));
+	gpio_flags_t flags;
+	gpio_flags_t flags_at_start[GPIO_COUNT];
+
+	/* Snapshot of GPIO flags before testing */
+	for (int i = 0; i < GPIO_COUNT; i++)
+		flags_at_start[i] = gpio_helper_get_flags(i);
+
+	/* Test reset on invalid signal */
+	gpio_reset_port(NULL);
+
+	/* Verify flags didn't change */
+	for (int i = 0; i < GPIO_COUNT; i++) {
+		flags = gpio_helper_get_flags(i);
+		zassert_equal(flags_at_start[i], flags,
+			      "%s[%d] flags_at_start=0x%x, flags=0x%x",
+			      gpio_get_name(i), i, flags_at_start[i], flags);
+	}
+
+	/* Test reset on valid signal */
+	gpio_set_flags(signal, GPIO_OUTPUT);
+	flags = gpio_helper_get_flags(signal);
+	zassert_equal(flags, GPIO_OUTPUT, "Flags set 0x%x", flags);
+
+	gpio_reset_port(port);
+
+	flags = gpio_helper_get_flags(signal);
+	zassert_equal(flags, gpio_get_default_flags(signal), "Flags set 0x%x",
+		      flags);
+
+	for (int i = 0; i < GPIO_COUNT; ++i) {
+		gpio_set_flags(i, flags_at_start[i]);
+	}
+}
+
+ZTEST(gpio, test_gpio_set_flags_by_mask)
+{
+	gpio_set_flags_by_mask(0, BIT(27), GPIO_OUTPUT);
+	zassert_equal(gpio_configure_port_pin_fake.call_count, 1);
+	zassert_equal(gpio_configure_port_pin_fake.arg0_val, 0);
+	zassert_equal(gpio_configure_port_pin_fake.arg1_val, 27);
+	zassert_equal(gpio_configure_port_pin_fake.arg2_val,
+		      convert_to_zephyr_flags(GPIO_OUTPUT));
+}
+
+ZTEST(gpio, test_init_gpios_fail_on_unused_pins_custom_func)
+{
+	gpio_config_unused_pins_fake.return_val = -1;
+
+	zassert_equal(-1, init_gpios(NULL));
+}
+
+/**
+ * @brief TestPurpose: Verify GPIO enable/disable interrupt.
+ *
+ * @details
+ * Validate gpio_enable_dt_interrupt
+ *
+ * Expected Results
+ *  - Success
+ */
+ZTEST(gpio, test_gpio_enable_dt_interrupt)
+{
+	const struct gpio_dt_spec *gp = GPIO_DT_FROM_NODELABEL(gpio_test);
+	const struct gpio_int_config *intr =
+		GPIO_INT_FROM_NODELABEL(int_gpio_test);
+
+	gpio_test_interrupt_triggered = false;
+
+	/* Test valid signal */
+	zassert_ok(gpio_disable_dt_interrupt(intr));
+	gpio_pin_set_dt(gp, 0);
+	zassert_false(gpio_test_interrupt_triggered);
+	gpio_pin_set_dt(gp, 1);
+	zassert_false(gpio_test_interrupt_triggered);
+
+	zassert_ok(gpio_enable_dt_interrupt(intr));
+	gpio_pin_set_dt(gp, 0);
+	zassert_true(gpio_test_interrupt_triggered);
+	gpio_test_interrupt_triggered = false;
+	gpio_pin_set_dt(gp, 1);
+	zassert_true(gpio_test_interrupt_triggered);
+}
+
+/**
+ * @brief GPIO test setup handler.
+ */
+static void gpio_before(void *state)
+{
+	ARG_UNUSED(state);
+	/** TODO: Reset all signals here. Currently other tests fail when reset
+	 * for(int i = 0; i < GPIO_COUNT; i++)	{
+	 *	gpio_reset(i);
+	 * }
+	 */
+	gpio_reset(GPIO_SIGNAL(DT_NODELABEL(gpio_test)));
+}
+
+/**
+ * @brief Test Suite: Verifies GPIO functionality.
+ */
+ZTEST_SUITE(gpio, drivers_predicate_pre_main, NULL, gpio_before, NULL, NULL);
diff --git a/zephyr/test/drivers/default/src/i2c.c b/zephyr/test/drivers/default/src/i2c.c
new file mode 100644
index 0000000000..b171f7dab9
--- /dev/null
+++ b/zephyr/test/drivers/default/src/i2c.c
@@ -0,0 +1,147 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+#include "host_command.h"
+#include "i2c.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+ZTEST_USER(i2c, test_i2c_set_speed_success)
+{
+	struct ec_response_i2c_control response;
+	struct ec_params_i2c_control get_params = {
+		.port = I2C_PORT_USB_C0,
+		.cmd = EC_I2C_CONTROL_GET_SPEED,
+	};
+	struct host_cmd_handler_args get_args;
+	struct ec_params_i2c_control set_params = {
+		.port = I2C_PORT_USB_C0,
+		.cmd = EC_I2C_CONTROL_SET_SPEED,
+	};
+	struct host_cmd_handler_args set_args;
+
+	/* Get the speed: 100. */
+	zassert_ok(ec_cmd_i2c_control(&get_args, &get_params, &response), NULL);
+	zassert_equal(get_args.response_size, sizeof(response), NULL);
+	zassert_equal(response.cmd_response.speed_khz, 100,
+		      "response.cmd_response.speed_khz = %d",
+		      response.cmd_response.speed_khz);
+
+	/* Set the speed to 400. */
+	set_params.cmd_params.speed_khz = 400;
+	zassert_ok(ec_cmd_i2c_control(&set_args, &set_params, &response), NULL);
+	zassert_equal(set_args.response_size, sizeof(response), NULL);
+	zassert_equal(response.cmd_response.speed_khz, 100,
+		      "response.cmd_response.speed_khz = %d",
+		      response.cmd_response.speed_khz);
+
+	/* Get the speed to verify. */
+	zassert_ok(ec_cmd_i2c_control(&get_args, &get_params, &response), NULL);
+	zassert_equal(get_args.response_size, sizeof(response), NULL);
+	zassert_equal(response.cmd_response.speed_khz, 400,
+		      "response.cmd_response.speed_khz = %d",
+		      response.cmd_response.speed_khz);
+
+	/* Set the speed to 1000. */
+	set_params.cmd_params.speed_khz = 1000;
+	zassert_ok(ec_cmd_i2c_control(&set_args, &set_params, &response), NULL);
+	zassert_equal(set_args.response_size, sizeof(response), NULL);
+	zassert_equal(response.cmd_response.speed_khz, 400,
+		      "response.cmd_response.speed_khz = %d",
+		      response.cmd_response.speed_khz);
+
+	/* Get the speed to verify. */
+	zassert_ok(ec_cmd_i2c_control(&get_args, &get_params, &response), NULL);
+	zassert_equal(get_args.response_size, sizeof(response), NULL);
+	zassert_equal(response.cmd_response.speed_khz, 1000,
+		      "response.cmd_response.speed_khz = %d",
+		      response.cmd_response.speed_khz);
+
+	/* Set the speed back to 100. */
+	set_params.cmd_params.speed_khz = 100;
+	zassert_ok(ec_cmd_i2c_control(&set_args, &set_params, &response), NULL);
+	zassert_equal(set_args.response_size, sizeof(response), NULL);
+	zassert_equal(response.cmd_response.speed_khz, 1000,
+		      "response.cmd_response.speed_khz = %d",
+		      response.cmd_response.speed_khz);
+}
+
+ZTEST_USER(i2c, test_i2c_set_speed_not_dynamic)
+{
+	struct ec_response_i2c_control response;
+	struct ec_params_i2c_control set_params = {
+		.port = I2C_PORT_POWER,
+		.cmd = EC_I2C_CONTROL_SET_SPEED,
+		.cmd_params.speed_khz = 400,
+	};
+
+	/* Set the speed to 400 on a bus which doesn't support dynamic-speed. */
+	zassert_equal(EC_RES_ERROR,
+		      ec_cmd_i2c_control(NULL, &set_params, &response), NULL);
+}
+
+ZTEST_USER(i2c, test_i2c_control_wrong_port)
+{
+	struct ec_response_i2c_control response;
+	struct ec_params_i2c_control get_params = {
+		.port = 10,
+		.cmd = EC_I2C_CONTROL_GET_SPEED,
+	};
+
+	/* Set the .port=10, which is not defined. */
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      ec_cmd_i2c_control(NULL, &get_params, &response), NULL);
+}
+
+ZTEST_USER(i2c, test_i2c_control_wrong_cmd)
+{
+	struct ec_response_i2c_control response;
+	struct ec_params_i2c_control params = {
+		.port = I2C_PORT_USB_C0,
+		.cmd = 10,
+	};
+
+	/* Call the .cmd=10, which is not defined. */
+	zassert_equal(EC_RES_INVALID_COMMAND,
+		      ec_cmd_i2c_control(NULL, &params, &response), NULL);
+}
+
+ZTEST_USER(i2c, test_i2c_set_speed_wrong_freq)
+{
+	struct ec_response_i2c_control response;
+	struct ec_params_i2c_control set_params = {
+		.port = I2C_PORT_USB_C0,
+		.cmd = EC_I2C_CONTROL_SET_SPEED,
+		.cmd_params.speed_khz = 123,
+	};
+
+	/* Set the speed to 123 KHz (an invalid speed). */
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      ec_cmd_i2c_control(NULL, &set_params, &response), NULL);
+}
+
+static void i2c_freq_reset(void)
+{
+	/* The test modifies this port. Reset it to the DTS defined. */
+	zassert_ok(i2c_set_freq(I2C_PORT_USB_C0, I2C_FREQ_100KHZ), NULL);
+}
+
+static void *i2c_setup(void)
+{
+	i2c_freq_reset();
+	return NULL;
+}
+
+static void i2c_teardown(void *state)
+{
+	ARG_UNUSED(state);
+	i2c_freq_reset();
+}
+
+ZTEST_SUITE(i2c, drivers_predicate_post_main, i2c_setup, NULL, NULL,
+	    i2c_teardown);
diff --git a/zephyr/test/drivers/default/src/i2c_passthru.c b/zephyr/test/drivers/default/src/i2c_passthru.c
new file mode 100644
index 0000000000..21726ea8f6
--- /dev/null
+++ b/zephyr/test/drivers/default/src/i2c_passthru.c
@@ -0,0 +1,341 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/ln9310.h"
+#include "ec_commands.h"
+#include "host_command.h"
+#include "i2c.h"
+#include "test/drivers/test_mocks.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+FAKE_VALUE_FUNC(int, board_allow_i2c_passthru, const struct i2c_cmd_desc_t *);
+
+int board_allow_i2c_passthru_custom_fake(const struct i2c_cmd_desc_t *cmd_desc)
+{
+	/* Only allow passthru on I2C_PORT_USB_C0 */
+	return i2c_get_device_for_port(cmd_desc->port) ==
+	       i2c_get_device_for_port(I2C_PORT_USB_C0);
+}
+
+ZTEST_USER(i2c_passthru, test_read_without_write)
+{
+	uint8_t param_buf[sizeof(struct ec_params_i2c_passthru) +
+			  sizeof(struct ec_params_i2c_passthru_msg)];
+	uint8_t response_buf[sizeof(struct ec_response_i2c_passthru) + 2];
+	struct ec_params_i2c_passthru *params =
+		(struct ec_params_i2c_passthru *)&param_buf;
+	struct ec_response_i2c_passthru *response =
+		(struct ec_response_i2c_passthru *)&response_buf;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_SIMPLE(EC_CMD_I2C_PASSTHRU, 0);
+
+	params->port = I2C_PORT_POWER;
+	params->num_msgs = 1;
+	params->msg[0].addr_flags = LN9310_I2C_ADDR_0_FLAGS | EC_I2C_FLAG_READ;
+	params->msg[0].len = 1;
+	args.params = &param_buf;
+	args.params_size = sizeof(param_buf);
+	args.response = &response_buf;
+	args.response_max = sizeof(response_buf);
+
+	zassert_ok(host_command_process(&args));
+	zassert_ok(args.result);
+	zassert_equal(response->i2c_status, EC_I2C_STATUS_NAK);
+	zassert_equal(args.response_size,
+		      sizeof(struct ec_response_i2c_passthru), NULL);
+}
+
+ZTEST_USER(i2c_passthru, test_passthru_invalid_params)
+{
+	uint16_t tcpc_addr = DT_REG_ADDR(DT_NODELABEL(tcpci_emul));
+	uint8_t *out_data;
+	uint8_t param_buf[sizeof(struct ec_params_i2c_passthru) +
+			  2 * sizeof(struct ec_params_i2c_passthru_msg) + 1];
+	uint8_t response_buf[sizeof(struct ec_response_i2c_passthru) + 2];
+	struct ec_params_i2c_passthru *passthru_params =
+		(struct ec_params_i2c_passthru *)&param_buf;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_SIMPLE(EC_CMD_I2C_PASSTHRU, 0);
+
+	passthru_params->port = I2C_PORT_USB_C0;
+	passthru_params->num_msgs = 2;
+	passthru_params->msg[0].addr_flags = tcpc_addr;
+	passthru_params->msg[0].len = 1;
+	passthru_params->msg[1].addr_flags = tcpc_addr | EC_I2C_FLAG_READ;
+	passthru_params->msg[1].len = 2; /* 2 byte vendor ID */
+
+	/* Write data follows the passthru messages */
+	out_data = (uint8_t *)&passthru_params->msg[2];
+	out_data[0] = 0; /* TCPC_REG_VENDOR_ID 0x0 */
+
+	args.params = &param_buf;
+	args.params_size = sizeof(param_buf);
+	args.response = &response_buf;
+	args.response_max = sizeof(response_buf);
+
+	/* Set the params_size to smaller than struct ec_params_i2c_passthru */
+	args.params_size = 1;
+	zassert_equal(host_command_process(&args), EC_RES_INVALID_PARAM);
+
+	/* Set the params_size so it truncates the 2nd I2C message */
+	args.params_size = sizeof(struct ec_params_i2c_passthru) +
+			   sizeof(struct ec_params_i2c_passthru_msg);
+	zassert_equal(host_command_process(&args), EC_RES_INVALID_PARAM);
+
+	/* Don't provide enough room for the response */
+	args.params_size = sizeof(param_buf);
+	args.response_max = sizeof(struct ec_response_i2c_passthru) + 1;
+	zassert_equal(host_command_process(&args), EC_RES_INVALID_PARAM);
+
+	/* Don't provide the write data */
+	args.response_max = sizeof(response_buf);
+	args.params_size = sizeof(struct ec_params_i2c_passthru) +
+			   2 * sizeof(struct ec_params_i2c_passthru_msg);
+	zassert_equal(host_command_process(&args), EC_RES_INVALID_PARAM);
+}
+
+ZTEST_USER(i2c_passthru, test_passthru_protect)
+{
+	struct ec_response_i2c_passthru_protect response;
+	struct ec_params_i2c_passthru_protect status_params = {
+		.port = I2C_PORT_SENSOR,
+		.subcmd = EC_CMD_I2C_PASSTHRU_PROTECT_STATUS,
+	};
+	struct host_cmd_handler_args status_args = BUILD_HOST_COMMAND(
+		EC_CMD_I2C_PASSTHRU_PROTECT, 0, response, status_params);
+	struct ec_params_i2c_passthru_protect enable_params = {
+		.port = I2C_PORT_SENSOR,
+		.subcmd = EC_CMD_I2C_PASSTHRU_PROTECT_ENABLE,
+	};
+
+	/* Check the protect status: 0 (unprotected) */
+	zassert_ok(ec_cmd_i2c_passthru_protect(&status_args, &status_params,
+					       &response),
+		   NULL);
+	zassert_equal(status_args.response_size, sizeof(response), NULL);
+	zassert_equal(response.status, 0, "response.status = %d",
+		      response.status);
+
+	/* Protect the bus */
+	zassert_ok(ec_cmd_i2c_passthru_protect(NULL, &enable_params, &response),
+		   NULL);
+
+	/* Check the protect status: 1 (protected) */
+	zassert_ok(ec_cmd_i2c_passthru_protect(&status_args, &status_params,
+					       &response),
+		   NULL);
+	zassert_equal(status_args.response_size, sizeof(response), NULL);
+	zassert_equal(response.status, 1, "response.status = %d",
+		      response.status);
+
+	/* Error case: wrong subcmd */
+	status_params.subcmd = 10;
+	zassert_equal(ec_cmd_i2c_passthru_protect(NULL, &status_params,
+						  &response),
+		      EC_RES_INVALID_COMMAND, NULL);
+	status_params.subcmd = EC_CMD_I2C_PASSTHRU_PROTECT_STATUS;
+
+	/* Error case: wrong port */
+	status_params.port = 10;
+	zassert_equal(ec_cmd_i2c_passthru_protect(NULL, &status_params,
+						  &response),
+		      EC_RES_INVALID_PARAM, NULL);
+	status_params.port = I2C_PORT_SENSOR;
+
+	/* Error case: response size not enough */
+	status_args.response_max = 0;
+	zassert_equal(host_command_process(&status_args), EC_RES_INVALID_PARAM,
+		      NULL);
+	status_args.response_max = sizeof(response);
+
+	/* Error case: params size not enough */
+	status_args.params_size = 0;
+	zassert_equal(host_command_process(&status_args), EC_RES_INVALID_PARAM,
+		      NULL);
+	status_args.params_size = sizeof(status_params);
+}
+
+ZTEST_USER(i2c_passthru, test_passthru_protect_tcpcs)
+{
+	struct ec_params_i2c_passthru_protect enable_params = {
+		.port = I2C_PORT_SENSOR,
+		.subcmd = EC_CMD_I2C_PASSTHRU_PROTECT_ENABLE_TCPCS,
+	};
+	struct ec_response_i2c_passthru_protect enable_response;
+	uint16_t tcpc_addr = DT_REG_ADDR(DT_NODELABEL(tcpci_emul));
+	uint8_t *out_data;
+	uint8_t param_buf[sizeof(struct ec_params_i2c_passthru) +
+			  2 * sizeof(struct ec_params_i2c_passthru_msg) + 1];
+	uint8_t response_buf[sizeof(struct ec_response_i2c_passthru) + 2];
+	struct ec_params_i2c_passthru *passthru_params =
+		(struct ec_params_i2c_passthru *)&param_buf;
+	struct ec_response_i2c_passthru *passthru_response =
+		(struct ec_response_i2c_passthru *)&response_buf;
+	struct host_cmd_handler_args passthru_args =
+		BUILD_HOST_COMMAND_SIMPLE(EC_CMD_I2C_PASSTHRU, 0);
+
+	/* If the system is unlocked, TCPC protection is disabled */
+	system_is_locked_fake.return_val = false;
+
+	/* Protect the all TCPC buses */
+	zassert_ok(ec_cmd_i2c_passthru_protect(NULL, &enable_params,
+					       &enable_response),
+		   NULL);
+
+	passthru_params->port = I2C_PORT_USB_C0;
+	passthru_params->num_msgs = 2;
+	passthru_params->msg[0].addr_flags = tcpc_addr;
+	passthru_params->msg[0].len = 1;
+	passthru_params->msg[1].addr_flags = tcpc_addr | EC_I2C_FLAG_READ;
+	passthru_params->msg[1].len = 2; /* 2 byte vendor ID */
+
+	/* Write data follows the passthru messages */
+	out_data = (uint8_t *)&passthru_params->msg[2];
+	out_data[0] = 0; /* TCPC_REG_VENDOR_ID 0x0 */
+
+	passthru_args.params = &param_buf;
+	passthru_args.params_size = sizeof(param_buf);
+	passthru_args.response = &response_buf;
+	passthru_args.response_max = sizeof(response_buf);
+
+	zassert_ok(host_command_process(&passthru_args));
+	zassert_ok(passthru_args.result);
+	zassert_ok(passthru_response->i2c_status);
+	zassert_equal(passthru_args.response_size,
+		      sizeof(struct ec_response_i2c_passthru) + 2, NULL);
+
+	/* Now attempt TCPC protection while the system is locked */
+	system_is_locked_fake.return_val = true;
+
+	/* Protect the all TCPC buses */
+	zassert_ok(ec_cmd_i2c_passthru_protect(NULL, &enable_params,
+					       &enable_response),
+		   NULL);
+
+	zassert_equal(host_command_process(&passthru_args),
+		      EC_RES_ACCESS_DENIED);
+}
+
+ZTEST_USER(i2c_passthru, test_passthru_restricted)
+{
+	uint16_t tcpc_addr = DT_REG_ADDR(DT_NODELABEL(tcpci_emul));
+	uint16_t ps8xxx_addr = DT_REG_ADDR(DT_NODELABEL(ps8xxx_emul));
+	uint8_t *out_data;
+	uint8_t tcpc_param_buf[sizeof(struct ec_params_i2c_passthru) +
+			       2 * sizeof(struct ec_params_i2c_passthru_msg) +
+			       1];
+	uint8_t tcpc_rsp_buf[sizeof(struct ec_response_i2c_passthru) + 2];
+	struct ec_params_i2c_passthru *tcpc_params =
+		(struct ec_params_i2c_passthru *)&tcpc_param_buf;
+	struct ec_response_i2c_passthru *tcpc_response =
+		(struct ec_response_i2c_passthru *)&tcpc_rsp_buf;
+	struct host_cmd_handler_args tcpc_args =
+		BUILD_HOST_COMMAND_SIMPLE(EC_CMD_I2C_PASSTHRU, 0);
+
+	uint8_t ps8xxx_param_buf[sizeof(struct ec_params_i2c_passthru) +
+				 2 * sizeof(struct ec_params_i2c_passthru_msg) +
+				 1];
+	uint8_t ps8xxx_rsp_buf[sizeof(struct ec_response_i2c_passthru) + 2];
+	struct ec_params_i2c_passthru *ps8xxx_params =
+		(struct ec_params_i2c_passthru *)&ps8xxx_param_buf;
+	struct ec_response_i2c_passthru *ps8xxx_response =
+		(struct ec_response_i2c_passthru *)&ps8xxx_rsp_buf;
+	struct host_cmd_handler_args ps8xxx_args =
+		BUILD_HOST_COMMAND_SIMPLE(EC_CMD_I2C_PASSTHRU, 0);
+
+	if (!IS_ENABLED(CONFIG_PLATFORM_EC_I2C_PASSTHRU_RESTRICTED)) {
+		ztest_test_skip();
+		return;
+	}
+
+	/*
+	 * Setup passthru command to the TCPCI emulator - which is always
+	 * permitted by our board_allow_i2c_passthru() fake.
+	 */
+	tcpc_params->port = I2C_PORT_USB_C0;
+	tcpc_params->num_msgs = 2;
+	tcpc_params->msg[0].addr_flags = tcpc_addr;
+	tcpc_params->msg[0].len = 1;
+	tcpc_params->msg[1].addr_flags = tcpc_addr | EC_I2C_FLAG_READ;
+	tcpc_params->msg[1].len = 2; /* 2 byte vendor ID */
+
+	/* Write data follows the passthru messages */
+	out_data = (uint8_t *)&tcpc_params->msg[2];
+	out_data[0] = 0; /* TCPC_REG_VENDOR_ID 0x0 */
+
+	tcpc_args.params = &tcpc_param_buf;
+	tcpc_args.params_size = sizeof(tcpc_param_buf);
+	tcpc_args.response = &tcpc_rsp_buf;
+	tcpc_args.response_max = sizeof(tcpc_rsp_buf);
+
+	/*
+	 * Setup passthru command to the PS8xxx emulator, which should be
+	 * rejected when the system is locked.
+	 */
+	ps8xxx_params->port = I2C_PORT_USB_C1;
+	ps8xxx_params->num_msgs = 2;
+	ps8xxx_params->msg[0].addr_flags = ps8xxx_addr;
+	ps8xxx_params->msg[0].len = 1;
+	ps8xxx_params->msg[1].addr_flags = ps8xxx_addr | EC_I2C_FLAG_READ;
+	ps8xxx_params->msg[1].len = 2; /* 2-byte vendor ID */
+
+	/* Write data follows the passthru messages */
+	out_data = (uint8_t *)&ps8xxx_params->msg[2];
+	out_data[0] = 0; /* TCPC_REG_VENDOR_ID 0x0 */
+
+	ps8xxx_args.params = &ps8xxx_param_buf;
+	ps8xxx_args.params_size = sizeof(ps8xxx_param_buf);
+	ps8xxx_args.response = &ps8xxx_rsp_buf;
+	ps8xxx_args.response_max = sizeof(ps8xxx_rsp_buf);
+
+	/* Install our board_allow_i2c_passthru() handler */
+	board_allow_i2c_passthru_fake.custom_fake =
+		board_allow_i2c_passthru_custom_fake;
+
+	/* When the system is unlocked, no restrictions apply */
+	system_is_locked_fake.return_val = false;
+
+	zassert_ok(host_command_process(&tcpc_args));
+	zassert_ok(tcpc_args.result);
+	zassert_ok(tcpc_response->i2c_status);
+	zassert_equal(tcpc_args.response_size,
+		      sizeof(struct ec_response_i2c_passthru) + 2, NULL);
+
+	zassert_ok(host_command_process(&ps8xxx_args));
+	zassert_ok(ps8xxx_args.result);
+	zassert_ok(ps8xxx_response->i2c_status);
+	zassert_equal(ps8xxx_args.response_size,
+		      sizeof(struct ec_response_i2c_passthru) + 2, NULL);
+
+	/* Lock the system which enables board_allow_i2c_passthru() */
+	system_is_locked_fake.return_val = true;
+
+	zassert_ok(host_command_process(&tcpc_args));
+	zassert_ok(tcpc_args.result);
+	zassert_ok(tcpc_response->i2c_status);
+	zassert_equal(tcpc_args.response_size,
+		      sizeof(struct ec_response_i2c_passthru) + 2, NULL);
+
+	zassert_equal(host_command_process(&ps8xxx_args), EC_RES_ACCESS_DENIED);
+}
+
+static void i2c_passthru_before(void *state)
+{
+	ARG_UNUSED(state);
+	RESET_FAKE(board_allow_i2c_passthru);
+	board_allow_i2c_passthru_fake.return_val = 1;
+}
+
+static void i2c_passthru_after(void *state)
+{
+	ARG_UNUSED(state);
+	i2c_passthru_protect_reset();
+}
+
+ZTEST_SUITE(i2c_passthru, drivers_predicate_post_main, NULL,
+	    i2c_passthru_before, i2c_passthru_after, NULL);
diff --git a/zephyr/test/drivers/default/src/integration/usbc/usb.c b/zephyr/test/drivers/default/src/integration/usbc/usb.c
new file mode 100644
index 0000000000..9028cda246
--- /dev/null
+++ b/zephyr/test/drivers/default/src/integration/usbc/usb.c
@@ -0,0 +1,158 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery_smart.h"
+#include "driver/tcpm/ps8xxx_public.h"
+#include "ec_commands.h"
+#include "ec_tasks.h"
+#include "emul/emul_isl923x.h"
+#include "emul/emul_smart_battery.h"
+#include "emul/tcpc/emul_ps8xxx.h"
+#include "emul/tcpc/emul_tcpci.h"
+#include "emul/tcpc/emul_tcpci_partner_drp.h"
+#include "emul/tcpc/emul_tcpci_partner_snk.h"
+#include "emul/tcpc/emul_tcpci_partner_src.h"
+#include "host_command.h"
+#include "task.h"
+#include "tcpm/tcpci.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "test/usb_pe.h"
+#include "usb_tc_sm.h"
+
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+#define BATTERY_NODE DT_NODELABEL(battery)
+
+#define GPIO_AC_OK_PATH NAMED_GPIOS_GPIO_NODE(acok_od)
+#define GPIO_AC_OK_PIN DT_GPIO_PIN(GPIO_AC_OK_PATH, gpios)
+
+#define GPIO_BATT_PRES_ODL_PATH NAMED_GPIOS_GPIO_NODE(ec_batt_pres_odl)
+#define GPIO_BATT_PRES_ODL_PORT DT_GPIO_PIN(GPIO_BATT_PRES_ODL_PATH, gpios)
+
+static void integration_usb_before(void *state)
+{
+	const struct emul *tcpci_emul = EMUL_GET_USBC_BINDING(0, tcpc);
+	const struct emul *tcpci_emul2 = EMUL_GET_USBC_BINDING(1, tcpc);
+	const struct emul *charger_emul = EMUL_GET_USBC_BINDING(0, chg);
+
+	/* Restart the PD task and let it settle */
+	task_set_event(TASK_ID_PD_C0, TASK_EVENT_RESET_DONE);
+	k_sleep(K_SECONDS(1));
+
+	/* Reset vbus to 0mV */
+	/* TODO(b/217610871): Remove redundant test state cleanup */
+	isl923x_emul_set_adc_vbus(charger_emul, 0);
+	const struct emul *battery_emul = EMUL_DT_GET(BATTERY_NODE);
+	struct sbat_emul_bat_data *bat;
+	const struct device *gpio_dev =
+		DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_AC_OK_PATH, gpios));
+
+	ARG_UNUSED(state);
+	/*
+	 * TODO(b/217755888): Refactor to using assume API
+	 */
+	zassert_ok(tcpc_config[0].drv->init(0));
+	zassert_ok(tcpc_config[1].drv->init(1));
+	tcpc_config[USBC_PORT_C0].flags &= ~TCPC_FLAGS_TCPCI_REV2_0;
+	tcpci_emul_set_rev(tcpci_emul, TCPCI_EMUL_REV1_0_VER1_0);
+	pd_set_suspend(0, 0);
+	pd_set_suspend(1, 0);
+	/* Reset to disconnected state. */
+	/*
+	 * TODO(b/217755888): Refactor to using assume API
+	 */
+	zassert_ok(tcpci_emul_disconnect_partner(tcpci_emul));
+	zassert_ok(tcpci_emul_disconnect_partner(tcpci_emul2));
+
+	/* Battery defaults to charging, so reset to not charging. */
+	bat = sbat_emul_get_bat_data(battery_emul);
+	bat->cur = -5;
+
+	/*
+	 * TODO(b/217755888): Refactor to using assume API
+	 */
+	zassert_ok(gpio_emul_input_set(gpio_dev, GPIO_AC_OK_PIN, 0));
+}
+
+static void integration_usb_after(void *state)
+{
+	const struct emul *tcpci_emul = EMUL_GET_USBC_BINDING(0, tcpc);
+	const struct emul *tcpci_emul2 = EMUL_GET_USBC_BINDING(1, tcpc);
+	const struct emul *charger_emul = EMUL_GET_USBC_BINDING(0, chg);
+	ARG_UNUSED(state);
+
+	/* TODO: This function should trigger gpios to signal there is nothing
+	 * attached to the port.
+	 */
+	/*
+	 * TODO(b/217755888): Refactor to using assume API
+	 */
+	zassert_ok(tcpci_emul_disconnect_partner(tcpci_emul));
+	zassert_ok(tcpci_emul_disconnect_partner(tcpci_emul2));
+	/* Give time to actually disconnect */
+	k_sleep(K_SECONDS(1));
+
+	/* Reset vbus to 0mV */
+	isl923x_emul_set_adc_vbus(charger_emul, 0);
+}
+
+ZTEST(integration_usb, test_attach_drp)
+{
+	const struct emul *tcpci_emul = EMUL_GET_USBC_BINDING(0, tcpc);
+	struct tcpci_partner_data my_drp;
+	struct tcpci_drp_emul_data drp_ext;
+	struct tcpci_src_emul_data src_ext;
+	struct tcpci_snk_emul_data snk_ext;
+
+	/* Set chipset to ON, this will set TCPM to DRP */
+	test_set_chipset_to_s0();
+
+	/* TODO(b/214401892): Check why need to give time TCPM to spin */
+	k_sleep(K_SECONDS(1));
+
+	/* Attach emulated sink */
+	tcpci_partner_init(&my_drp, PD_REV20);
+	my_drp.extensions = tcpci_drp_emul_init(
+		&drp_ext, &my_drp, PD_ROLE_SINK,
+		tcpci_src_emul_init(&src_ext, &my_drp, NULL),
+		tcpci_snk_emul_init(&snk_ext, &my_drp, NULL));
+
+	zassert_ok(tcpci_partner_connect_to_tcpci(&my_drp, tcpci_emul));
+
+	/* Wait for PD negotiation */
+	k_sleep(K_SECONDS(10));
+
+	/*
+	 * Test that SRC ready is achieved
+	 * TODO: Change it to examining EC_CMD_TYPEC_STATUS
+	 */
+	zassert_equal(PE_SNK_READY, get_state_pe(USBC_PORT_C0));
+	zassert_ok(tcpci_emul_disconnect_partner(tcpci_emul));
+}
+
+ZTEST(integration_usb, test_event_loop)
+{
+	int paused = tc_event_loop_is_paused(USBC_PORT_C0);
+
+	tc_pause_event_loop(USBC_PORT_C0);
+	zassert_equal(1, tc_event_loop_is_paused(USBC_PORT_C0));
+
+	tc_start_event_loop(USBC_PORT_C0);
+	zassert_equal(0, tc_event_loop_is_paused(USBC_PORT_C0));
+
+	/* Restore pause state from beginning */
+	if (paused) {
+		tc_pause_event_loop(USBC_PORT_C0);
+	} else {
+		tc_start_event_loop(USBC_PORT_C0);
+	}
+}
+
+ZTEST_SUITE(integration_usb, drivers_predicate_post_main, NULL,
+	    integration_usb_before, integration_usb_after, NULL);
diff --git a/zephyr/test/drivers/default/src/integration/usbc/usb_20v_3a_pd_charger.c b/zephyr/test/drivers/default/src/integration/usbc/usb_20v_3a_pd_charger.c
new file mode 100644
index 0000000000..8b1bd1a6f1
--- /dev/null
+++ b/zephyr/test/drivers/default/src/integration/usbc/usb_20v_3a_pd_charger.c
@@ -0,0 +1,231 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery_smart.h"
+#include "emul/emul_isl923x.h"
+#include "emul/emul_smart_battery.h"
+#include "emul/tcpc/emul_tcpci_partner_src.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "usb_pd.h"
+
+#include <zephyr/ztest.h>
+
+#define BATTERY_NODE DT_NODELABEL(battery)
+
+struct usb_attach_20v_3a_pd_charger_fixture {
+	struct tcpci_partner_data charger_20v;
+	struct tcpci_src_emul_data src_ext;
+	const struct emul *tcpci_emul;
+	const struct emul *charger_emul;
+};
+
+static inline void
+connect_charger_to_port(struct usb_attach_20v_3a_pd_charger_fixture *fixture)
+{
+	set_ac_enabled(true);
+	zassert_ok(tcpci_partner_connect_to_tcpci(&fixture->charger_20v,
+						  fixture->tcpci_emul),
+		   NULL);
+
+	isl923x_emul_set_adc_vbus(fixture->charger_emul,
+				  PDO_FIXED_GET_VOLT(fixture->src_ext.pdo[1]));
+
+	/* Wait for PD negotiation and current ramp.
+	 * TODO(b/213906889): Check message timing and contents.
+	 */
+	k_sleep(K_SECONDS(10));
+}
+
+static inline void disconnect_charger_from_port(
+	struct usb_attach_20v_3a_pd_charger_fixture *fixture)
+{
+	set_ac_enabled(false);
+	zassert_ok(tcpci_emul_disconnect_partner(fixture->tcpci_emul));
+	isl923x_emul_set_adc_vbus(fixture->charger_emul, 0);
+	k_sleep(K_SECONDS(1));
+}
+
+static void *usb_attach_20v_3a_pd_charger_setup(void)
+{
+	static struct usb_attach_20v_3a_pd_charger_fixture test_fixture;
+
+	/* Get references for the emulators */
+	test_fixture.tcpci_emul = EMUL_GET_USBC_BINDING(0, tcpc);
+	test_fixture.charger_emul = EMUL_GET_USBC_BINDING(0, chg);
+
+	/* Initialized the charger to supply 20V and 3A */
+	tcpci_partner_init(&test_fixture.charger_20v, PD_REV20);
+	test_fixture.charger_20v.extensions = tcpci_src_emul_init(
+		&test_fixture.src_ext, &test_fixture.charger_20v, NULL);
+	test_fixture.src_ext.pdo[1] =
+		PDO_FIXED(20000, 3000, PDO_FIXED_UNCONSTRAINED);
+
+	return &test_fixture;
+}
+
+static void usb_attach_20v_3a_pd_charger_before(void *data)
+{
+	connect_charger_to_port(
+		(struct usb_attach_20v_3a_pd_charger_fixture *)data);
+}
+
+static void usb_attach_20v_3a_pd_charger_after(void *data)
+{
+	disconnect_charger_from_port(
+		(struct usb_attach_20v_3a_pd_charger_fixture *)data);
+}
+
+ZTEST_SUITE(usb_attach_20v_3a_pd_charger, drivers_predicate_post_main,
+	    usb_attach_20v_3a_pd_charger_setup,
+	    usb_attach_20v_3a_pd_charger_before,
+	    usb_attach_20v_3a_pd_charger_after, NULL);
+
+ZTEST(usb_attach_20v_3a_pd_charger, test_battery_is_charging)
+{
+	const struct emul *emul = EMUL_DT_GET(BATTERY_NODE);
+	uint16_t battery_status;
+
+	zassert_ok(sbat_emul_get_word_val(emul, SB_BATTERY_STATUS,
+					  &battery_status),
+		   NULL);
+	zassert_equal(battery_status & STATUS_DISCHARGING, 0,
+		      "Battery is discharging: %d", battery_status);
+}
+
+ZTEST(usb_attach_20v_3a_pd_charger, test_charge_state)
+{
+	struct ec_response_charge_state state = host_cmd_charge_state(0);
+
+	zassert_true(state.get_state.ac, "AC_OK not triggered");
+	zassert_true(state.get_state.chg_voltage > 0,
+		     "Expected a charge voltage, but got %dmV",
+		     state.get_state.chg_voltage);
+	zassert_true(state.get_state.chg_current > 0,
+		     "Expected a charge current, but got %dmA",
+		     state.get_state.chg_current);
+}
+
+ZTEST(usb_attach_20v_3a_pd_charger, test_typec_status)
+{
+	struct ec_response_typec_status status = host_cmd_typec_status(0);
+
+	zassert_true(status.pd_enabled, "PD is disabled");
+	zassert_true(status.dev_connected, "Device disconnected");
+	zassert_true(status.sop_connected, "Charger is not SOP capable");
+	zassert_equal(status.source_cap_count, 2,
+		      "Expected 2 source PDOs, but got %d",
+		      status.source_cap_count);
+	zassert_equal(status.power_role, PD_ROLE_SINK,
+		      "Expected power role to be %d, but got %d", PD_ROLE_SINK,
+		      status.power_role);
+}
+
+ZTEST(usb_attach_20v_3a_pd_charger, test_power_info)
+{
+	struct ec_response_usb_pd_power_info info = host_cmd_power_info(0);
+
+	zassert_equal(info.role, USB_PD_PORT_POWER_SINK,
+		      "Expected role to be %d, but got %d",
+		      USB_PD_PORT_POWER_SINK, info.role);
+	zassert_equal(info.type, USB_CHG_TYPE_PD,
+		      "Expected type to be %d, but got %d", USB_CHG_TYPE_PD,
+		      info.type);
+	zassert_equal(info.meas.voltage_max, 20000,
+		      "Expected charge voltage max of 20000mV, but got %dmV",
+		      info.meas.voltage_max);
+	zassert_within(
+		info.meas.voltage_now, 20000, 2000,
+		"Charging voltage expected to be near 20000mV, but was %dmV",
+		info.meas.voltage_now);
+	zassert_equal(info.meas.current_max, 3000,
+		      "Current max expected to be 3000mV, but was %dmV",
+		      info.meas.current_max);
+	zassert_true(info.meas.current_lim >= 3000,
+		     "VBUS max is set to 3000mA, but PD is reporting %dmA",
+		     info.meas.current_lim);
+	zassert_equal(info.max_power, 20000 * 3000,
+		      "Charging expected to be at %duW, but PD max is %duW",
+		      20000 * 3000, info.max_power);
+}
+
+ZTEST_F(usb_attach_20v_3a_pd_charger, test_disconnect_battery_not_charging)
+{
+	const struct emul *emul = EMUL_DT_GET(BATTERY_NODE);
+	uint16_t battery_status;
+
+	disconnect_charger_from_port(fixture);
+	zassert_ok(sbat_emul_get_word_val(emul, SB_BATTERY_STATUS,
+					  &battery_status),
+		   NULL);
+	zassert_equal(battery_status & STATUS_DISCHARGING, STATUS_DISCHARGING,
+		      "Battery is not discharging: %d", battery_status);
+}
+
+ZTEST_F(usb_attach_20v_3a_pd_charger, test_disconnect_charge_state)
+{
+	struct ec_response_charge_state state;
+
+	disconnect_charger_from_port(fixture);
+	state = host_cmd_charge_state(0);
+
+	zassert_false(state.get_state.ac, "AC_OK not triggered");
+	zassert_equal(state.get_state.chg_current, 0,
+		      "Max charge current expected 0mA, but was %dmA",
+		      state.get_state.chg_current);
+	zassert_equal(state.get_state.chg_input_current,
+		      CONFIG_PLATFORM_EC_CHARGER_DEFAULT_CURRENT_LIMIT,
+		      "Charge input current limit expected %dmA, but was %dmA",
+		      CONFIG_PLATFORM_EC_CHARGER_DEFAULT_CURRENT_LIMIT,
+		      state.get_state.chg_input_current);
+}
+
+ZTEST_F(usb_attach_20v_3a_pd_charger, test_disconnect_typec_status)
+{
+	struct ec_response_typec_status typec_status;
+
+	disconnect_charger_from_port(fixture);
+	typec_status = host_cmd_typec_status(0);
+
+	zassert_false(typec_status.pd_enabled);
+	zassert_false(typec_status.dev_connected);
+	zassert_false(typec_status.sop_connected);
+	zassert_equal(typec_status.source_cap_count, 0,
+		      "Expected 0 source caps, but got %d",
+		      typec_status.source_cap_count);
+	zassert_equal(typec_status.power_role, USB_CHG_TYPE_NONE,
+		      "Expected power role to be %d, but got %d",
+		      USB_CHG_TYPE_NONE, typec_status.power_role);
+}
+
+ZTEST_F(usb_attach_20v_3a_pd_charger, test_disconnect_power_info)
+{
+	struct ec_response_usb_pd_power_info power_info;
+
+	disconnect_charger_from_port(fixture);
+	power_info = host_cmd_power_info(0);
+
+	zassert_equal(power_info.role, USB_PD_PORT_POWER_DISCONNECTED,
+		      "Expected power role to be %d, but got %d",
+		      USB_PD_PORT_POWER_DISCONNECTED, power_info.role);
+	zassert_equal(power_info.type, USB_CHG_TYPE_NONE,
+		      "Expected charger type to be %d, but got %s",
+		      USB_CHG_TYPE_NONE, power_info.type);
+	zassert_equal(power_info.max_power, 0,
+		      "Expected the maximum power to be 0uW, but got %duW",
+		      power_info.max_power);
+	zassert_equal(power_info.meas.voltage_max, 0,
+		      "Expected maximum voltage of 0mV, but got %dmV",
+		      power_info.meas.voltage_max);
+	zassert_within(power_info.meas.voltage_now, 5, 5,
+		       "Expected present voltage near 0mV, but got %dmV",
+		       power_info.meas.voltage_now);
+	zassert_equal(power_info.meas.current_max, 0,
+		      "Expected maximum current of 0mA, but got %dmA",
+		      power_info.meas.current_max);
+	zassert_true(power_info.meas.current_lim >= 0,
+		     "Expected the PD current limit to be >= 0, but got %dmA",
+		     power_info.meas.current_lim);
+}
diff --git a/zephyr/test/drivers/default/src/integration/usbc/usb_5v_3a_pd_sink.c b/zephyr/test/drivers/default/src/integration/usbc/usb_5v_3a_pd_sink.c
new file mode 100644
index 0000000000..bff3d9661e
--- /dev/null
+++ b/zephyr/test/drivers/default/src/integration/usbc/usb_5v_3a_pd_sink.c
@@ -0,0 +1,254 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery_smart.h"
+#include "emul/emul_isl923x.h"
+#include "emul/emul_smart_battery.h"
+#include "emul/tcpc/emul_tcpci_partner_snk.h"
+#include "tcpm/tcpci.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "timer.h"
+#include "usb_pd.h"
+
+#include <stdint.h>
+
+#include <zephyr/ztest.h>
+
+struct usb_attach_5v_3a_pd_sink_fixture {
+	struct tcpci_partner_data sink_5v_3a;
+	struct tcpci_snk_emul_data snk_ext;
+	const struct emul *tcpci_emul;
+	const struct emul *charger_emul;
+};
+
+/* Chromebooks only charge PD partners at 5v */
+#define TEST_SRC_PORT_VBUS_MV 5000
+#define TEST_SRC_PORT_TARGET_MA 3000
+
+#define TEST_INITIAL_SINK_CAP \
+	PDO_FIXED(TEST_SRC_PORT_VBUS_MV, TEST_SRC_PORT_TARGET_MA, 0)
+/* Only used to verify sink capabilities being received by SRC port */
+#define TEST_ADDITIONAL_SINK_CAP PDO_FIXED(TEST_SRC_PORT_VBUS_MV, 5000, 0)
+
+static void *usb_attach_5v_3a_pd_sink_setup(void)
+{
+	static struct usb_attach_5v_3a_pd_sink_fixture test_fixture;
+
+	/* Get references for the emulators */
+	test_fixture.tcpci_emul = EMUL_GET_USBC_BINDING(0, tcpc);
+	test_fixture.charger_emul = EMUL_GET_USBC_BINDING(0, chg);
+
+	return &test_fixture;
+}
+
+static void usb_attach_5v_3a_pd_sink_before(void *data)
+{
+	struct usb_attach_5v_3a_pd_sink_fixture *test_fixture = data;
+
+	/* Set chipset to ON, this will set TCPM to DRP */
+	test_set_chipset_to_s0();
+
+	/* TODO(b/214401892): Check why need to give time TCPM to spin */
+	k_sleep(K_SECONDS(1));
+
+	/* Initialized the sink to request 5V and 3A */
+	tcpci_partner_init(&test_fixture->sink_5v_3a, PD_REV20);
+	test_fixture->sink_5v_3a.extensions = tcpci_snk_emul_init(
+		&test_fixture->snk_ext, &test_fixture->sink_5v_3a, NULL);
+	test_fixture->snk_ext.pdo[0] = TEST_INITIAL_SINK_CAP;
+	test_fixture->snk_ext.pdo[1] = TEST_ADDITIONAL_SINK_CAP;
+	connect_sink_to_port(&test_fixture->sink_5v_3a,
+			     test_fixture->tcpci_emul,
+			     test_fixture->charger_emul);
+}
+
+static void usb_attach_5v_3a_pd_sink_after(void *data)
+{
+	struct usb_attach_5v_3a_pd_sink_fixture *test_fixture = data;
+
+	disconnect_sink_from_port(test_fixture->tcpci_emul);
+}
+
+ZTEST_SUITE(usb_attach_5v_3a_pd_sink, drivers_predicate_post_main,
+	    usb_attach_5v_3a_pd_sink_setup, usb_attach_5v_3a_pd_sink_before,
+	    usb_attach_5v_3a_pd_sink_after, NULL);
+
+ZTEST_F(usb_attach_5v_3a_pd_sink, test_partner_pd_completed)
+{
+	zassert_true(fixture->snk_ext.pd_completed);
+}
+
+ZTEST(usb_attach_5v_3a_pd_sink, test_battery_is_discharging)
+{
+	const struct emul *emul = EMUL_DT_GET(DT_NODELABEL(battery));
+	uint16_t battery_status;
+
+	zassert_ok(sbat_emul_get_word_val(emul, SB_BATTERY_STATUS,
+					  &battery_status));
+	zassert_equal(battery_status & STATUS_DISCHARGING, STATUS_DISCHARGING,
+		      "Battery is not discharging: %d", battery_status);
+}
+
+ZTEST(usb_attach_5v_3a_pd_sink, test_typec_status)
+{
+	struct ec_response_typec_status status = host_cmd_typec_status(0);
+
+	zassert_true(status.pd_enabled, "PD is disabled");
+	zassert_true(status.dev_connected, "Device disconnected");
+	zassert_true(status.sop_connected, "Charger is not SOP capable");
+	zassert_equal(status.sink_cap_count, 2,
+		      "Expected 2 sink PDOs, but got %d",
+		      status.sink_cap_count);
+	zassert_equal(status.power_role, PD_ROLE_SOURCE,
+		      "Expected power role to be %d, but got %d",
+		      PD_ROLE_SOURCE, status.power_role);
+}
+
+ZTEST(usb_attach_5v_3a_pd_sink, test_power_info)
+{
+	struct ec_response_usb_pd_power_info info = host_cmd_power_info(0);
+
+	zassert_equal(info.role, USB_PD_PORT_POWER_SOURCE,
+		      "Expected role to be %d, but got %d",
+		      USB_PD_PORT_POWER_SOURCE, info.role);
+	zassert_equal(info.type, USB_CHG_TYPE_NONE,
+		      "Expected type to be %d, but got %d", USB_CHG_TYPE_NONE,
+		      info.type);
+	zassert_equal(info.meas.voltage_max, 0,
+		      "Expected charge voltage max of 0mV, but got %dmV",
+		      info.meas.voltage_max);
+	zassert_within(
+		info.meas.voltage_now, TEST_SRC_PORT_VBUS_MV, 500,
+		"Charging voltage expected to be near 5000mV, but was %dmV",
+		info.meas.voltage_now);
+	zassert_equal(info.meas.current_max, TEST_SRC_PORT_TARGET_MA,
+		      "Current max expected to be 1500mV, but was %dmV",
+		      info.meas.current_max);
+	zassert_equal(info.meas.current_lim, 0,
+		      "VBUS max is set to 0mA, but PD is reporting %dmA",
+		      info.meas.current_lim);
+	zassert_equal(info.max_power, 0,
+		      "Charging expected to be at %duW, but PD max is %duW", 0,
+		      info.max_power);
+}
+
+ZTEST_F(usb_attach_5v_3a_pd_sink, test_disconnect_battery_discharging)
+{
+	const struct emul *emul = EMUL_DT_GET(DT_NODELABEL(battery));
+	uint16_t battery_status;
+
+	disconnect_sink_from_port(fixture->tcpci_emul);
+	zassert_ok(sbat_emul_get_word_val(emul, SB_BATTERY_STATUS,
+					  &battery_status));
+	zassert_equal(battery_status & STATUS_DISCHARGING, STATUS_DISCHARGING,
+		      "Battery is not discharging: %d", battery_status);
+}
+
+ZTEST_F(usb_attach_5v_3a_pd_sink, test_disconnect_charge_state)
+{
+	struct ec_response_charge_state state;
+
+	disconnect_sink_from_port(fixture->tcpci_emul);
+	state = host_cmd_charge_state(0);
+
+	zassert_false(state.get_state.ac, "AC_OK not triggered");
+	zassert_equal(state.get_state.chg_current, 0,
+		      "Max charge current expected 0mA, but was %dmA",
+		      state.get_state.chg_current);
+	zassert_equal(state.get_state.chg_input_current,
+		      CONFIG_PLATFORM_EC_CHARGER_DEFAULT_CURRENT_LIMIT,
+		      "Charge input current limit expected %dmA, but was %dmA",
+		      CONFIG_PLATFORM_EC_CHARGER_DEFAULT_CURRENT_LIMIT,
+		      state.get_state.chg_input_current);
+}
+
+ZTEST_F(usb_attach_5v_3a_pd_sink, test_disconnect_typec_status)
+{
+	struct ec_response_typec_status typec_status;
+
+	disconnect_sink_from_port(fixture->tcpci_emul);
+	typec_status = host_cmd_typec_status(0);
+
+	zassert_false(typec_status.pd_enabled);
+	zassert_false(typec_status.dev_connected);
+	zassert_false(typec_status.sop_connected);
+	zassert_equal(typec_status.source_cap_count, 0,
+		      "Expected 0 source caps, but got %d",
+		      typec_status.source_cap_count);
+	zassert_equal(typec_status.power_role, USB_CHG_TYPE_NONE,
+		      "Expected power role to be %d, but got %d",
+		      USB_CHG_TYPE_NONE, typec_status.power_role);
+}
+
+ZTEST_F(usb_attach_5v_3a_pd_sink, test_disconnect_power_info)
+{
+	struct ec_response_usb_pd_power_info power_info;
+
+	disconnect_sink_from_port(fixture->tcpci_emul);
+	power_info = host_cmd_power_info(0);
+
+	zassert_equal(power_info.role, USB_PD_PORT_POWER_DISCONNECTED,
+		      "Expected power role to be %d, but got %d",
+		      USB_PD_PORT_POWER_DISCONNECTED, power_info.role);
+	zassert_equal(power_info.type, USB_CHG_TYPE_NONE,
+		      "Expected charger type to be %d, but got %s",
+		      USB_CHG_TYPE_NONE, power_info.type);
+	zassert_equal(power_info.max_power, 0,
+		      "Expected the maximum power to be 0uW, but got %duW",
+		      power_info.max_power);
+	zassert_equal(power_info.meas.voltage_max, 0,
+		      "Expected maximum voltage of 0mV, but got %dmV",
+		      power_info.meas.voltage_max);
+	zassert_within(power_info.meas.voltage_now, 5, 5,
+		       "Expected present voltage near 0mV, but got %dmV",
+		       power_info.meas.voltage_now);
+	zassert_equal(power_info.meas.current_max, 0,
+		      "Expected maximum current of 0mA, but got %dmA",
+		      power_info.meas.current_max);
+	zassert_true(power_info.meas.current_lim >= 0,
+		     "Expected the PD current limit to be >= 0, but got %dmA",
+		     power_info.meas.current_lim);
+}
+
+/**
+ * @brief TestPurpose: Verify GotoMin message.
+ *
+ * @details
+ *  - TCPM is configured initially as Source
+ *  - Initiate Goto_Min request
+ *  - Verify emulated sink PD negotiation is completed
+ *
+ * Expected Results
+ *  - Sink completes Goto Min PD negotiation
+ */
+ZTEST_F(usb_attach_5v_3a_pd_sink, test_verify_goto_min)
+{
+	pd_dpm_request(0, DPM_REQUEST_GOTO_MIN);
+	k_sleep(K_SECONDS(1));
+
+	zassert_true(fixture->snk_ext.pd_completed);
+}
+
+/**
+ * @brief TestPurpose: Verify Ping message.
+ *
+ * @details
+ *  - TCPM is configured initially as Source
+ *  - Initiate Ping request
+ *  - Verify emulated sink received ping message
+ *
+ * Expected Results
+ *  - Sink received ping message
+ */
+ZTEST_F(usb_attach_5v_3a_pd_sink, test_verify_ping_msg)
+{
+	tcpci_snk_emul_clear_ping_received(&fixture->snk_ext);
+
+	pd_dpm_request(0, DPM_REQUEST_SEND_PING);
+	k_sleep(K_USEC(PD_T_SOURCE_ACTIVITY));
+
+	zassert_true(fixture->snk_ext.ping_received);
+}
diff --git a/zephyr/test/drivers/default/src/integration/usbc/usb_5v_3a_pd_source.c b/zephyr/test/drivers/default/src/integration/usbc/usb_5v_3a_pd_source.c
new file mode 100644
index 0000000000..252509f9ba
--- /dev/null
+++ b/zephyr/test/drivers/default/src/integration/usbc/usb_5v_3a_pd_source.c
@@ -0,0 +1,363 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "battery_smart.h"
+#include "dps.h"
+#include "emul/emul_isl923x.h"
+#include "emul/emul_smart_battery.h"
+#include "emul/tcpc/emul_tcpci_partner_src.h"
+#include "system.h"
+#include "task.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "usb_pd.h"
+
+#include <zephyr/shell/shell_dummy.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/sys/slist.h>
+#include <zephyr/ztest.h>
+
+#define BATTERY_NODE DT_NODELABEL(battery)
+
+#define GPIO_BATT_PRES_ODL_PATH NAMED_GPIOS_GPIO_NODE(ec_batt_pres_odl)
+#define GPIO_BATT_PRES_ODL_PORT DT_GPIO_PIN(GPIO_BATT_PRES_ODL_PATH, gpios)
+
+#define TEST_PORT 0
+
+struct usb_attach_5v_3a_pd_source_fixture {
+	struct tcpci_partner_data source_5v_3a;
+	struct tcpci_src_emul_data src_ext;
+	const struct emul *tcpci_emul;
+	const struct emul *charger_emul;
+};
+
+static void *usb_attach_5v_3a_pd_source_setup(void)
+{
+	static struct usb_attach_5v_3a_pd_source_fixture test_fixture;
+
+	/* Get references for the emulators */
+	test_fixture.tcpci_emul = EMUL_GET_USBC_BINDING(TEST_PORT, tcpc);
+	test_fixture.charger_emul = EMUL_GET_USBC_BINDING(TEST_PORT, chg);
+
+	/* Initialized the charger to supply 5V and 3A */
+	tcpci_partner_init(&test_fixture.source_5v_3a, PD_REV20);
+	test_fixture.source_5v_3a.extensions = tcpci_src_emul_init(
+		&test_fixture.src_ext, &test_fixture.source_5v_3a, NULL);
+	test_fixture.src_ext.pdo[1] =
+		PDO_FIXED(5000, 3000, PDO_FIXED_UNCONSTRAINED);
+
+	return &test_fixture;
+}
+
+static void usb_attach_5v_3a_pd_source_before(void *data)
+{
+	struct usb_attach_5v_3a_pd_source_fixture *fixture = data;
+
+	connect_source_to_port(&fixture->source_5v_3a, &fixture->src_ext, 1,
+			       fixture->tcpci_emul, fixture->charger_emul);
+}
+
+static void usb_attach_5v_3a_pd_source_after(void *data)
+{
+	struct usb_attach_5v_3a_pd_source_fixture *fixture = data;
+
+	disconnect_source_from_port(fixture->tcpci_emul, fixture->charger_emul);
+}
+
+static void control_battery_present(bool present)
+{
+	const struct device *dev =
+		DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_BATT_PRES_ODL_PATH, gpios));
+
+	/* 0 means battery present */
+	zassert_ok(gpio_emul_input_set(dev, GPIO_BATT_PRES_ODL_PORT, !present));
+}
+
+ZTEST_SUITE(usb_attach_5v_3a_pd_source, drivers_predicate_post_main,
+	    usb_attach_5v_3a_pd_source_setup, usb_attach_5v_3a_pd_source_before,
+	    usb_attach_5v_3a_pd_source_after, NULL);
+
+ZTEST(usb_attach_5v_3a_pd_source, test_battery_is_charging)
+{
+	const struct emul *emul = EMUL_DT_GET(BATTERY_NODE);
+	uint16_t battery_status;
+
+	zassert_ok(sbat_emul_get_word_val(emul, SB_BATTERY_STATUS,
+					  &battery_status));
+	zassert_equal(battery_status & STATUS_DISCHARGING, 0,
+		      "Battery is discharging: %d", battery_status);
+}
+
+ZTEST(usb_attach_5v_3a_pd_source, test_charge_state)
+{
+	struct ec_response_charge_state state =
+		host_cmd_charge_state(TEST_PORT);
+
+	zassert_true(state.get_state.ac, "AC_OK not triggered");
+	zassert_true(state.get_state.chg_voltage > 0,
+		     "Expected a charge voltage, but got %dmV",
+		     state.get_state.chg_voltage);
+	zassert_true(state.get_state.chg_current > 0,
+		     "Expected a charge current, but got %dmA",
+		     state.get_state.chg_current);
+}
+
+ZTEST(usb_attach_5v_3a_pd_source, test_typec_status)
+{
+	struct ec_response_typec_status status = host_cmd_typec_status(0);
+
+	zassert_true(status.pd_enabled, "PD is disabled");
+	zassert_true(status.dev_connected, "Device disconnected");
+	zassert_true(status.sop_connected, "Charger is not SOP capable");
+	zassert_equal(status.source_cap_count, 2,
+		      "Expected 2 source PDOs, but got %d",
+		      status.source_cap_count);
+	zassert_equal(status.power_role, PD_ROLE_SINK,
+		      "Expected power role to be %d, but got %d", PD_ROLE_SINK,
+		      status.power_role);
+}
+
+ZTEST(usb_attach_5v_3a_pd_source, test_power_info)
+{
+	struct ec_response_usb_pd_power_info info = host_cmd_power_info(0);
+
+	zassert_equal(info.role, USB_PD_PORT_POWER_SINK,
+		      "Expected role to be %d, but got %d",
+		      USB_PD_PORT_POWER_SINK, info.role);
+	zassert_equal(info.type, USB_CHG_TYPE_PD,
+		      "Expected type to be %d, but got %d", USB_CHG_TYPE_PD,
+		      info.type);
+	zassert_equal(info.meas.voltage_max, 5000,
+		      "Expected charge voltage max of 5000mV, but got %dmV",
+		      info.meas.voltage_max);
+	zassert_within(
+		info.meas.voltage_now, 5000, 500,
+		"Charging voltage expected to be near 5000mV, but was %dmV",
+		info.meas.voltage_now);
+	zassert_equal(info.meas.current_max, 3000,
+		      "Current max expected to be 3000mV, but was %dmV",
+		      info.meas.current_max);
+	zassert_true(info.meas.current_lim >= 3000,
+		     "VBUS max is set to 3000mA, but PD is reporting %dmA",
+		     info.meas.current_lim);
+	zassert_equal(info.max_power, 5000 * 3000,
+		      "Charging expected to be at %duW, but PD max is %duW",
+		      5000 * 3000, info.max_power);
+}
+
+ZTEST_F(usb_attach_5v_3a_pd_source, test_disconnect_battery_not_charging)
+{
+	const struct emul *emul = EMUL_DT_GET(BATTERY_NODE);
+	uint16_t battery_status;
+
+	disconnect_source_from_port(fixture->tcpci_emul, fixture->charger_emul);
+	zassert_ok(sbat_emul_get_word_val(emul, SB_BATTERY_STATUS,
+					  &battery_status));
+	zassert_equal(battery_status & STATUS_DISCHARGING, STATUS_DISCHARGING,
+		      "Battery is not discharging: %d", battery_status);
+}
+
+ZTEST_F(usb_attach_5v_3a_pd_source, test_disconnect_charge_state)
+{
+	struct ec_response_charge_state state;
+
+	disconnect_source_from_port(fixture->tcpci_emul, fixture->charger_emul);
+	state = host_cmd_charge_state(TEST_PORT);
+
+	zassert_false(state.get_state.ac, "AC_OK not triggered");
+	zassert_equal(state.get_state.chg_current, 0,
+		      "Max charge current expected 0mA, but was %dmA",
+		      state.get_state.chg_current);
+	zassert_equal(state.get_state.chg_input_current,
+		      CONFIG_PLATFORM_EC_CHARGER_DEFAULT_CURRENT_LIMIT,
+		      "Charge input current limit expected %dmA, but was %dmA",
+		      CONFIG_PLATFORM_EC_CHARGER_DEFAULT_CURRENT_LIMIT,
+		      state.get_state.chg_input_current);
+}
+
+ZTEST_F(usb_attach_5v_3a_pd_source, test_disconnect_typec_status)
+{
+	struct ec_response_typec_status typec_status;
+
+	disconnect_source_from_port(fixture->tcpci_emul, fixture->charger_emul);
+	typec_status = host_cmd_typec_status(0);
+
+	zassert_false(typec_status.pd_enabled);
+	zassert_false(typec_status.dev_connected);
+	zassert_false(typec_status.sop_connected);
+	zassert_equal(typec_status.source_cap_count, 0,
+		      "Expected 0 source caps, but got %d",
+		      typec_status.source_cap_count);
+	zassert_equal(typec_status.power_role, USB_CHG_TYPE_NONE,
+		      "Expected power role to be %d, but got %d",
+		      USB_CHG_TYPE_NONE, typec_status.power_role);
+}
+
+ZTEST_F(usb_attach_5v_3a_pd_source, test_disconnect_power_info)
+{
+	struct ec_response_usb_pd_power_info power_info;
+
+	disconnect_source_from_port(fixture->tcpci_emul, fixture->charger_emul);
+	power_info = host_cmd_power_info(0);
+
+	zassert_equal(power_info.role, USB_PD_PORT_POWER_DISCONNECTED,
+		      "Expected power role to be %d, but got %d",
+		      USB_PD_PORT_POWER_DISCONNECTED, power_info.role);
+	zassert_equal(power_info.type, USB_CHG_TYPE_NONE,
+		      "Expected charger type to be %d, but got %s",
+		      USB_CHG_TYPE_NONE, power_info.type);
+	zassert_equal(power_info.max_power, 0,
+		      "Expected the maximum power to be 0uW, but got %duW",
+		      power_info.max_power);
+	zassert_equal(power_info.meas.voltage_max, 0,
+		      "Expected maximum voltage of 0mV, but got %dmV",
+		      power_info.meas.voltage_max);
+	zassert_within(power_info.meas.voltage_now, 5, 5,
+		       "Expected present voltage near 0mV, but got %dmV",
+		       power_info.meas.voltage_now);
+	zassert_equal(power_info.meas.current_max, 0,
+		      "Expected maximum current of 0mA, but got %dmA",
+		      power_info.meas.current_max);
+	zassert_true(power_info.meas.current_lim >= 0,
+		     "Expected the PD current limit to be >= 0, but got %dmA",
+		     power_info.meas.current_lim);
+}
+
+ZTEST(usb_attach_5v_3a_pd_source,
+      test_ap_can_boot_on_low_battery_while_charging)
+{
+	const struct emul *smart_batt_emul = EMUL_DT_GET(DT_NODELABEL(battery));
+	struct sbat_emul_bat_data *batt_data =
+		sbat_emul_get_bat_data(smart_batt_emul);
+
+	/* Set capacity to what gives a charge percentage less than required
+	 * for booting the AP
+	 *
+	 * Capacaity is reset by emulator's ZTEST_RULE
+	 */
+	batt_data->cap = (CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON *
+			  batt_data->design_cap / 100) -
+			 1;
+
+	zassert_true(system_can_boot_ap());
+}
+
+ZTEST_F(usb_attach_5v_3a_pd_source,
+	test_ap_fails_to_boot_on_low_battery_while_not_charging)
+{
+	const struct emul *smart_batt_emul = EMUL_DT_GET(DT_NODELABEL(battery));
+	struct sbat_emul_bat_data *batt_data =
+		sbat_emul_get_bat_data(smart_batt_emul);
+
+	/* Set capacity to what gives a charge percentage less than required
+	 * for booting the AP
+	 *
+	 * Capacaity is reset by emulator's ZTEST_RULE
+	 */
+	batt_data->cap = (CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON *
+			  batt_data->design_cap / 100) -
+			 1;
+
+	disconnect_source_from_port(fixture->tcpci_emul, fixture->charger_emul);
+
+	zassert_false(system_can_boot_ap());
+}
+
+ZTEST_F(usb_attach_5v_3a_pd_source, test_uvdm_ignored)
+{
+	uint32_t vdm_header = VDO(USB_VID_GOOGLE, 0 /* unstructured */, 0);
+
+	tcpci_partner_common_enable_pd_logging(&fixture->source_5v_3a, true);
+	tcpci_partner_send_data_msg(&fixture->source_5v_3a, PD_DATA_VENDOR_DEF,
+				    &vdm_header, 1, 0);
+	k_sleep(K_SECONDS(1));
+	tcpci_partner_common_enable_pd_logging(&fixture->source_5v_3a, false);
+
+	bool tcpm_response = false;
+	struct tcpci_partner_log_msg *msg;
+
+	/* The TCPM does not support any unstructured VDMs. In PD 2.0, it should
+	 * ignore them.
+	 */
+
+	SYS_SLIST_FOR_EACH_CONTAINER(&fixture->source_5v_3a.msg_log, msg, node)
+	{
+		/* Ignore messages from the port partner */
+		if (msg->sender == TCPCI_PARTNER_SENDER_PARTNER) {
+			continue;
+		}
+
+		if (msg->sender == TCPCI_PARTNER_SENDER_TCPM) {
+			tcpm_response = true;
+			break;
+		}
+	}
+
+	zassert_false(tcpm_response,
+		      "Sent unstructured VDM to TCPM; TCPM did not ignore");
+}
+
+ZTEST_F(usb_attach_5v_3a_pd_source, test_dps_battery_absent)
+{
+	control_battery_present(false);
+	zassert_false(battery_is_present(), "dps battery is present");
+	task_wake(TASK_ID_DPS);
+	/* wait dps_config.t_check*/
+	k_sleep(K_MSEC(5000));
+	zassert_true(dps_get_flag() & DPS_FLAG_NO_BATTERY,
+		     "DPS_FLAG_NO_BATTERY is set");
+	control_battery_present(true);
+	zassert_true(battery_is_present(), "dps battery is not present");
+}
+
+ZTEST_F(usb_attach_5v_3a_pd_source, test_dps_enable)
+{
+	dps_enable(false);
+	zassert_false(dps_is_enabled());
+	task_wake(TASK_ID_DPS);
+	/* wait dps_config.t_check*/
+	k_sleep(K_MSEC(5000));
+	zassert_true(dps_get_flag() & DPS_FLAG_DISABLED,
+		     "DPS_FLAG_DISABLED is set");
+	dps_enable(true);
+	zassert_true(dps_is_enabled());
+}
+
+ZTEST_F(usb_attach_5v_3a_pd_source, test_dps_info)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+
+	const char *outbuffer;
+	uint32_t buffer_size;
+	/* Arbitrary array size for sprintf should not need this amount */
+	char format_buffer[100];
+
+	shell_backend_dummy_clear_output(shell_zephyr);
+
+	/* Print current status to console */
+	zassert_ok(shell_execute_cmd(shell_zephyr, "dps"), NULL);
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+
+	/* Should include extra information about the charging port */
+	/* Charging Port */
+	sprintf(format_buffer, "C%d", TEST_PORT);
+	zassert_not_null(strstr(outbuffer, format_buffer));
+	/* We are a sink to a 5v3a source, so check requested mv/ma */
+	sprintf(format_buffer, "Requested: %dmV/%dmA", 5000, 3000);
+	zassert_not_null(strstr(outbuffer, format_buffer));
+	/*
+	 * Measured input power is shown (values vary so not asserting on
+	 * numbers)
+	 */
+	zassert_not_null(strstr(outbuffer, "Measured:"));
+	/* Efficient Voltage - Value varies based on battery*/
+	zassert_not_null(strstr(outbuffer, "Efficient:"));
+	/* Battery Design Voltage (varies based on battery) */
+	zassert_not_null(strstr(outbuffer, "Batt:"));
+	/* PDMaxMV */
+	sprintf(format_buffer, "PDMaxMV:   %dmV", pd_get_max_voltage());
+	zassert_not_null(strstr(outbuffer, format_buffer));
+}
diff --git a/zephyr/test/drivers/default/src/integration/usbc/usb_attach_src_snk.c b/zephyr/test/drivers/default/src/integration/usbc/usb_attach_src_snk.c
new file mode 100644
index 0000000000..c53a416f77
--- /dev/null
+++ b/zephyr/test/drivers/default/src/integration/usbc/usb_attach_src_snk.c
@@ -0,0 +1,792 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/tcpm/ps8xxx_public.h"
+#include "ec_commands.h"
+#include "ec_tasks.h"
+#include "emul/emul_isl923x.h"
+#include "emul/tcpc/emul_ps8xxx.h"
+#include "emul/tcpc/emul_tcpci.h"
+#include "emul/tcpc/emul_tcpci_partner_snk.h"
+#include "emul/tcpc/emul_tcpci_partner_src.h"
+#include "host_command.h"
+#include "tcpm/tcpci.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "test/usb_pe.h"
+
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+#define SNK_PORT USBC_PORT_C0
+#define SRC_PORT USBC_PORT_C1
+
+#define DEFAULT_VBUS_MV 5000
+
+/* Determined by CONFIG_PLATFORM_EC_USB_PD_PULLUP */
+#define DEFAULT_VBUS_SRC_PORT_MA 1500
+
+/* SRC TCPCI Emulator attaches as TYPEC_CC_VOLT_RP_3_0 */
+#define DEFAULT_VBUS_SNK_PORT_MA 3000
+
+#define DEFAULT_SINK_SENT_TO_SOURCE_CAP_COUNT 1
+#define DEFAULT_SOURCE_SENT_TO_SINK_CAP_COUNT 1
+
+struct emul_state {
+	/* TODO(b/217737667): Remove driver specific code. */
+	const struct emul *tcpci_generic_emul;
+	const struct emul *tcpci_ps8xxx_emul;
+	const struct emul *charger_isl923x_emul;
+	struct tcpci_partner_data my_src;
+	struct tcpci_src_emul_data src_ext;
+	struct tcpci_partner_data my_snk;
+	struct tcpci_snk_emul_data snk_ext;
+};
+
+struct integration_usb_attach_src_then_snk_fixture {
+	struct emul_state my_emulator_state;
+};
+
+struct integration_usb_attach_snk_then_src_fixture {
+	struct emul_state my_emulator_state;
+};
+
+static void integration_usb_setup(struct emul_state *fixture)
+{
+	const struct emul *tcpci_emul = EMUL_GET_USBC_BINDING(0, tcpc);
+	const struct emul *tcpci_emul2 = EMUL_GET_USBC_BINDING(1, tcpc);
+	const struct emul *charger_emul = EMUL_GET_USBC_BINDING(0, chg);
+
+	/* Setting these are required because compiler believes these values are
+	 * not compile time constants.
+	 */
+	/*
+	 * TODO(b/217758708): emuls should be identified at compile-time.
+	 */
+	fixture->tcpci_generic_emul = tcpci_emul;
+	fixture->tcpci_ps8xxx_emul = tcpci_emul2;
+	fixture->charger_isl923x_emul = charger_emul;
+
+	tcpci_partner_init(&fixture->my_snk, PD_REV20);
+	fixture->my_snk.extensions =
+		tcpci_snk_emul_init(&fixture->snk_ext, &fixture->my_snk, NULL);
+
+	tcpci_partner_init(&fixture->my_src, PD_REV20);
+	fixture->my_src.extensions =
+		tcpci_src_emul_init(&fixture->src_ext, &fixture->my_src, NULL);
+
+	/*
+	 * TODO(b/221288815): TCPCI config flags should be compile-time
+	 * constants
+	 * TODO(b/209907615): Verify TCPCI rev1 on non-port partner.
+	 */
+	/* Turn TCPCI rev 2 ON */
+	tcpc_config[SNK_PORT].flags |= TCPC_FLAGS_TCPCI_REV2_0;
+	tcpc_config[SRC_PORT].flags |= TCPC_FLAGS_TCPCI_REV2_0;
+}
+
+static void *integration_usb_src_snk_setup(void)
+{
+	static struct integration_usb_attach_src_then_snk_fixture fixture_state;
+
+	integration_usb_setup(&fixture_state.my_emulator_state);
+
+	return &fixture_state;
+}
+
+static void *integration_usb_snk_src_setup(void)
+{
+	static struct integration_usb_attach_snk_then_src_fixture fixture_state;
+
+	integration_usb_setup(&fixture_state.my_emulator_state);
+
+	return &fixture_state;
+}
+
+static void attach_src_snk_common_before(struct emul_state *my_emul_state)
+{
+	const struct emul *tcpci_emul_src = my_emul_state->tcpci_generic_emul;
+	const struct emul *tcpci_emul_snk = my_emul_state->tcpci_ps8xxx_emul;
+	const struct emul *charger_emul = my_emul_state->charger_isl923x_emul;
+
+	/* Reset vbus to 0mV */
+	/* TODO(b/217737667): Remove driver specific code. */
+	isl923x_emul_set_adc_vbus(charger_emul, 0);
+
+	zassert_ok(tcpc_config[SNK_PORT].drv->init(SNK_PORT));
+	/*
+	 * Arbitrary FW ver. The emulator should really be setting this
+	 * during its init.
+	 */
+	tcpci_emul_set_reg(tcpci_emul_snk, PS8XXX_REG_FW_REV, 0x31);
+
+	zassert_ok(tcpc_config[SRC_PORT].drv->init(SRC_PORT));
+
+	pd_set_suspend(SNK_PORT, false);
+	pd_set_suspend(SRC_PORT, false);
+
+	/* Reset to disconnected state. */
+	zassert_ok(tcpci_emul_disconnect_partner(tcpci_emul_src));
+	zassert_ok(tcpci_emul_disconnect_partner(tcpci_emul_snk));
+
+	/* Set chipset to ON, this will set TCPM to DRP */
+	test_set_chipset_to_s0();
+}
+
+static void attach_src_snk_common_after(struct emul_state *my_emul_state)
+{
+	const struct emul *tcpci_generic_emul =
+		my_emul_state->tcpci_generic_emul;
+	const struct emul *tcpci_ps8xxx_emul = my_emul_state->tcpci_ps8xxx_emul;
+	const struct emul *charger_emul = my_emul_state->charger_isl923x_emul;
+
+	tcpci_emul_disconnect_partner(tcpci_generic_emul);
+	tcpci_emul_disconnect_partner(tcpci_ps8xxx_emul);
+
+	/* Give time to actually disconnect */
+	k_sleep(K_SECONDS(1));
+
+	/* Reset vbus to 0mV */
+	/* TODO(b/217737667): Remove driver specific code. */
+	isl923x_emul_set_adc_vbus(charger_emul, 0);
+}
+
+static void attach_emulated_snk(struct emul_state *my_emul_state)
+{
+	const struct emul *tcpci_emul_snk = my_emul_state->tcpci_ps8xxx_emul;
+	struct tcpci_partner_data *my_snk = &my_emul_state->my_snk;
+	uint16_t power_reg_val;
+
+	/* Turn on VBUS detection */
+	/*
+	 * TODO(b/223901282): integration tests should not be setting vbus
+	 * detection via registers, also this should be turned on by default.
+	 */
+	tcpci_emul_get_reg(tcpci_emul_snk, TCPC_REG_POWER_STATUS,
+			   &power_reg_val);
+	tcpci_emul_set_reg(tcpci_emul_snk, TCPC_REG_POWER_STATUS,
+			   power_reg_val | TCPC_REG_POWER_STATUS_VBUS_DET);
+
+	/* Necessary for TCPCIv2 vSave0V detection on VBUS to reach attached
+	 * state
+	 */
+	tcpci_emul_set_reg(tcpci_emul_snk, TCPC_REG_EXT_STATUS,
+			   TCPC_REG_EXT_STATUS_SAFE0V);
+
+	zassert_ok(tcpci_partner_connect_to_tcpci(my_snk, tcpci_emul_snk),
+		   NULL);
+
+	/* TODO(b/214401892): Check why need to give time TCPM to spin */
+	k_sleep(K_SECONDS(1));
+}
+
+static void attach_emulated_src(struct emul_state *my_emul_state)
+{
+	const struct emul *tcpci_emul_src = my_emul_state->tcpci_generic_emul;
+	const struct emul *charger_emul = my_emul_state->charger_isl923x_emul;
+	struct tcpci_partner_data *my_src = &my_emul_state->my_src;
+	uint16_t power_reg_val;
+
+	/* Turn on VBUS detection */
+	/*
+	 * TODO(b/223901282): integration tests should not be setting vbus
+	 * detection via registers, also this should be turned on by default.
+	 */
+	tcpci_emul_get_reg(tcpci_emul_src, TCPC_REG_POWER_STATUS,
+			   &power_reg_val);
+	tcpci_emul_set_reg(tcpci_emul_src, TCPC_REG_POWER_STATUS,
+			   power_reg_val | TCPC_REG_POWER_STATUS_VBUS_DET);
+
+	/* Necessary for TCPCIv2 vSave0V detection on VBUS to reach attached
+	 * state
+	 */
+	tcpci_emul_set_reg(tcpci_emul_src, TCPC_REG_EXT_STATUS,
+			   TCPC_REG_EXT_STATUS_SAFE0V);
+
+	zassert_ok(tcpci_partner_connect_to_tcpci(my_src, tcpci_emul_src),
+		   NULL);
+	isl923x_emul_set_adc_vbus(charger_emul, DEFAULT_VBUS_MV);
+}
+
+static void integration_usb_attach_snk_then_src_before(void *state)
+{
+	struct integration_usb_attach_src_then_snk_fixture *fixture = state;
+	struct emul_state *my_state = &fixture->my_emulator_state;
+
+	attach_src_snk_common_before(my_state);
+
+	/* 1) Attach SINK */
+	attach_emulated_snk(my_state);
+
+	/* Wait for PD negotiation */
+	k_sleep(K_SECONDS(10));
+
+	/* 2) Attach SOURCE */
+	attach_emulated_src(my_state);
+
+	/* Wait for PD negotiation */
+	k_sleep(K_SECONDS(10));
+}
+
+static void integration_usb_attach_src_then_snk_before(void *state)
+{
+	struct integration_usb_attach_src_then_snk_fixture *fixture = state;
+	struct emul_state *my_state = &fixture->my_emulator_state;
+
+	attach_src_snk_common_before(my_state);
+
+	/* 1) Attach SOURCE */
+	attach_emulated_src(my_state);
+
+	/* Wait for PD negotiation */
+	k_sleep(K_SECONDS(10));
+
+	/* 2) Attach SINK */
+	attach_emulated_snk(my_state);
+
+	/* Wait for PD negotiation */
+	k_sleep(K_SECONDS(10));
+}
+
+static void integration_usb_attach_src_then_snk_after(void *state)
+{
+	struct integration_usb_attach_src_then_snk_fixture *fixture = state;
+
+	attach_src_snk_common_after(&fixture->my_emulator_state);
+}
+
+static void integration_usb_attach_snk_then_src_after(void *state)
+{
+	struct integration_usb_attach_snk_then_src_fixture *fixture = state;
+
+	attach_src_snk_common_after(&fixture->my_emulator_state);
+}
+
+ZTEST_F(integration_usb_attach_src_then_snk, test_verify_snk_port_pd_info)
+{
+	struct ec_response_usb_pd_power_info response;
+
+	response = host_cmd_power_info(SNK_PORT);
+
+	/* Assert */
+	zassert_equal(response.role, USB_PD_PORT_POWER_SINK,
+		      "Power role %d, but PD reports role %d",
+		      USB_PD_PORT_POWER_SINK, response.role);
+	zassert_equal(response.type, USB_CHG_TYPE_PD,
+		      "Charger type %d, but PD reports type %d",
+		      USB_CHG_TYPE_PD, response.type);
+
+	zassert_equal(response.meas.voltage_max, DEFAULT_VBUS_MV,
+		      "Charging at VBUS %dmV, but PD reports %dmV",
+		      DEFAULT_VBUS_MV, response.meas.voltage_max);
+
+	zassert_within(response.meas.voltage_now, DEFAULT_VBUS_MV,
+		       DEFAULT_VBUS_MV / 10,
+		       "Actually charging at VBUS %dmV, but PD reports %dmV",
+		       DEFAULT_VBUS_MV, response.meas.voltage_now);
+
+	zassert_equal(response.meas.current_max, DEFAULT_VBUS_SNK_PORT_MA,
+		      "Charging at VBUS max %dmA, but PD reports %dmA",
+		      DEFAULT_VBUS_SNK_PORT_MA, response.meas.current_max);
+
+	zassert_true(response.meas.current_lim >= DEFAULT_VBUS_SNK_PORT_MA,
+		     "Charging at VBUS max %dmA, but PD current limit %dmA",
+		     DEFAULT_VBUS_SNK_PORT_MA, response.meas.current_lim);
+
+	zassert_equal(response.max_power,
+		      DEFAULT_VBUS_MV * DEFAULT_VBUS_SNK_PORT_MA,
+		      "Charging up to %duW, PD max power %duW",
+		      DEFAULT_VBUS_MV * DEFAULT_VBUS_SNK_PORT_MA,
+		      response.max_power);
+}
+
+ZTEST_F(integration_usb_attach_src_then_snk, test_verify_src_port_pd_info)
+{
+	struct ec_response_usb_pd_power_info response;
+
+	response = host_cmd_power_info(SRC_PORT);
+
+	/* Assert */
+	zassert_equal(response.role, USB_PD_PORT_POWER_SOURCE,
+		      "Power role %d, but PD reports role %d", PD_ROLE_SOURCE,
+		      response.role);
+
+	zassert_equal(response.type, USB_CHG_TYPE_NONE,
+		      "Charger type %d, but PD reports type %d",
+		      USB_CHG_TYPE_NONE, response.type);
+
+	/* TODO(b/209907615): Confirm measure value requirements */
+	zassert_within(response.meas.voltage_now, DEFAULT_VBUS_MV,
+		       DEFAULT_VBUS_MV / 10,
+		       "Expected Charging at VBUS %dmV, but PD reports %dmV",
+		       DEFAULT_VBUS_MV, response.meas.voltage_now);
+
+	zassert_equal(response.meas.current_max, DEFAULT_VBUS_SRC_PORT_MA,
+		      "Charging at VBUS max %dmA, but PD reports %dmA",
+		      DEFAULT_VBUS_SRC_PORT_MA, response.meas.current_max);
+
+	/* Note: We are the source so we skip checking: */
+	/* meas.voltage_max */
+	/* max_power */
+	/* current limit */
+}
+
+ZTEST_F(integration_usb_attach_snk_then_src, test_verify_snk_port_pd_info)
+{
+	struct ec_response_usb_pd_power_info response;
+
+	response = host_cmd_power_info(SNK_PORT);
+
+	/* Assert */
+	zassert_equal(response.role, USB_PD_PORT_POWER_SINK,
+		      "Power role %d, but PD reports role %d",
+		      USB_PD_PORT_POWER_SINK, response.role);
+	zassert_equal(response.type, USB_CHG_TYPE_PD,
+		      "Charger type %d, but PD reports type %d",
+		      USB_CHG_TYPE_PD, response.type);
+
+	/* Verify Default 5V and 3A */
+	zassert_equal(response.meas.voltage_max, DEFAULT_VBUS_MV,
+		      "Charging at VBUS %dmV, but PD reports %dmV",
+		      DEFAULT_VBUS_MV, response.meas.voltage_max);
+
+	zassert_within(response.meas.voltage_now, DEFAULT_VBUS_MV,
+		       DEFAULT_VBUS_MV / 10,
+		       "Actually charging at VBUS %dmV, but PD reports %dmV",
+		       DEFAULT_VBUS_MV, response.meas.voltage_now);
+
+	zassert_equal(response.meas.current_max, DEFAULT_VBUS_SNK_PORT_MA,
+		      "Charging at VBUS max %dmA, but PD reports %dmA",
+		      DEFAULT_VBUS_SNK_PORT_MA, response.meas.current_max);
+
+	zassert_true(response.meas.current_lim >= DEFAULT_VBUS_SNK_PORT_MA,
+		     "Charging at VBUS max %dmA, but PD current limit %dmA",
+		     DEFAULT_VBUS_SNK_PORT_MA, response.meas.current_lim);
+
+	zassert_equal(response.max_power,
+		      DEFAULT_VBUS_MV * DEFAULT_VBUS_SNK_PORT_MA,
+		      "Charging up to %duW, PD max power %duW",
+		      DEFAULT_VBUS_MV * DEFAULT_VBUS_SNK_PORT_MA,
+		      response.max_power);
+}
+
+ZTEST_F(integration_usb_attach_snk_then_src, test_verify_src_port_pd_info)
+{
+	struct ec_response_usb_pd_power_info response;
+
+	response = host_cmd_power_info(SRC_PORT);
+
+	/* Assert */
+	zassert_equal(response.role, USB_PD_PORT_POWER_SOURCE,
+		      "Power role %d, but PD reports role %d", PD_ROLE_SOURCE,
+		      response.role);
+
+	zassert_equal(response.type, USB_CHG_TYPE_NONE,
+		      "Charger type %d, but PD reports type %d",
+		      USB_CHG_TYPE_NONE, response.type);
+
+	/* Verify Default 5V and 3A */
+	/* TODO(b/209907615): Confirm measure value requirements */
+	zassert_within(response.meas.voltage_now, DEFAULT_VBUS_MV,
+		       DEFAULT_VBUS_MV / 10,
+		       "Expected Charging at VBUS %dmV, but PD reports %dmV",
+		       DEFAULT_VBUS_MV, response.meas.voltage_now);
+
+	zassert_equal(response.meas.current_max, DEFAULT_VBUS_SRC_PORT_MA,
+		      "Charging at VBUS max %dmA, but PD reports %dmA",
+		      DEFAULT_VBUS_SRC_PORT_MA, response.meas.current_max);
+
+	/* Note: We are the source so we skip checking: */
+	/* meas.voltage_max */
+	/* max_power */
+	/* current limit */
+}
+
+ZTEST_F(integration_usb_attach_src_then_snk, test_verify_snk_port_typec_status)
+{
+	struct ec_response_typec_status response =
+		host_cmd_typec_status(SNK_PORT);
+
+	zassert_true(response.pd_enabled, "Source attached but PD disabled");
+
+	zassert_true(response.dev_connected,
+		     "Source attached but device disconnected");
+
+	zassert_true(response.sop_connected,
+		     "Source attached but not SOP capable");
+
+	zassert_equal(response.source_cap_count,
+		      DEFAULT_SOURCE_SENT_TO_SINK_CAP_COUNT,
+		      "Source received %d source PDOs",
+		      response.source_cap_count);
+
+	/* The source emulator is being attached to a sink port (our policy
+	 * engine) so it does not send any sink caps, so sink port received no
+	 * sink caps.
+	 */
+	zassert_equal(response.sink_cap_count, 0, "Port received %d sink PDOs",
+		      response.sink_cap_count);
+
+	zassert_equal(response.power_role, PD_ROLE_SINK,
+		      "Source attached, but TCPM power role is %d",
+		      response.power_role);
+}
+
+ZTEST_F(integration_usb_attach_src_then_snk, test_verify_src_port_typec_status)
+{
+	struct ec_response_typec_status response =
+		host_cmd_typec_status(SRC_PORT);
+
+	zassert_true(response.pd_enabled, "Sink attached but PD disabled");
+
+	zassert_true(response.dev_connected,
+		     "Sink attached but device disconnected");
+
+	zassert_true(response.sop_connected,
+		     "Sink attached but not SOP capable");
+
+	/* The sink emulator is being attached to a source port (our policy
+	 * engine) so it does not send any sink caps, so source port received no
+	 * sink caps.
+	 */
+	zassert_equal(response.source_cap_count, 0,
+		      "Port received %d source PDOs",
+		      response.source_cap_count);
+
+	zassert_equal(response.sink_cap_count,
+		      DEFAULT_SINK_SENT_TO_SOURCE_CAP_COUNT,
+		      "Port received %d sink PDOs", response.sink_cap_count);
+
+	zassert_equal(response.power_role, PD_ROLE_SOURCE,
+		      "Sink attached, but TCPM power role is %d",
+		      response.power_role);
+}
+
+ZTEST_F(integration_usb_attach_snk_then_src, test_verify_snk_port_typec_status)
+{
+	struct ec_response_typec_status response =
+		host_cmd_typec_status(SNK_PORT);
+
+	zassert_true(response.pd_enabled, "Source attached but PD disabled");
+
+	zassert_true(response.dev_connected,
+		     "Source attached but device disconnected");
+
+	zassert_true(response.sop_connected,
+		     "Source attached but not SOP capable");
+
+	zassert_equal(response.source_cap_count,
+		      DEFAULT_SOURCE_SENT_TO_SINK_CAP_COUNT,
+		      "Source received %d source PDOs",
+		      response.source_cap_count);
+
+	/* The source emulator is being attached to a sink port (our policy
+	 * engine) so it does not send any sink caps, so sink port received no
+	 * sink caps.
+	 */
+	zassert_equal(response.sink_cap_count, 0, "Port received %d sink PDOs",
+		      response.sink_cap_count);
+
+	zassert_equal(response.power_role, PD_ROLE_SINK,
+		      "Source attached, but TCPM power role is %d",
+		      response.power_role);
+}
+
+ZTEST_F(integration_usb_attach_snk_then_src, test_verify_src_port_typec_status)
+{
+	struct ec_response_typec_status response =
+		host_cmd_typec_status(SRC_PORT);
+
+	zassert_true(response.pd_enabled, "Sink attached but PD disabled");
+
+	zassert_true(response.dev_connected,
+		     "Sink attached but device disconnected");
+
+	zassert_true(response.sop_connected,
+		     "Sink attached but not SOP capable");
+
+	/* The sink emulator is being attached to a source port (our policy
+	 * engine) so it does not send any sink caps, so source port received no
+	 * sink caps.
+	 */
+	zassert_equal(response.source_cap_count, 0,
+		      "Port received %d source PDOs",
+		      response.source_cap_count);
+
+	zassert_equal(response.sink_cap_count,
+		      DEFAULT_SINK_SENT_TO_SOURCE_CAP_COUNT,
+		      "Port received %d sink PDOs", response.sink_cap_count);
+
+	zassert_equal(response.power_role, PD_ROLE_SOURCE,
+		      "Sink attached, but TCPM power role is %d",
+		      response.power_role);
+}
+
+ZTEST_SUITE(integration_usb_attach_src_then_snk, drivers_predicate_post_main,
+	    integration_usb_src_snk_setup,
+	    integration_usb_attach_src_then_snk_before,
+	    integration_usb_attach_src_then_snk_after, NULL);
+
+ZTEST_SUITE(integration_usb_attach_snk_then_src, drivers_predicate_post_main,
+	    integration_usb_snk_src_setup,
+	    integration_usb_attach_snk_then_src_before,
+	    integration_usb_attach_snk_then_src_after, NULL);
+
+struct usb_detach_test_fixture {
+	struct emul_state fixture;
+};
+
+static void integration_usb_test_detach(const struct emul *e)
+{
+	zassert_ok(tcpci_emul_disconnect_partner(e));
+}
+
+static void integration_usb_test_sink_detach(struct emul_state *fixture)
+{
+	integration_usb_test_detach(fixture->tcpci_ps8xxx_emul);
+}
+
+static void integration_usb_test_source_detach(struct emul_state *fixture)
+{
+	integration_usb_test_detach(fixture->tcpci_generic_emul);
+}
+
+void *usb_detach_test_setup(void)
+{
+	static struct usb_detach_test_fixture usb_detach_fixture = { 0 };
+
+	integration_usb_setup(&usb_detach_fixture.fixture);
+
+	return &usb_detach_fixture;
+}
+
+static void usb_detach_test_before(void *state)
+{
+	struct usb_detach_test_fixture *fixture = state;
+	struct emul_state *my_state = &fixture->fixture;
+
+	attach_src_snk_common_before(my_state);
+
+	/* 1) Attach SINK */
+	attach_emulated_snk(my_state);
+
+	/* Wait for PD negotiation */
+	k_sleep(K_SECONDS(10));
+
+	/* 2) Attach SOURCE */
+	attach_emulated_src(my_state);
+
+	/* Wait for PD negotiation */
+	k_sleep(K_SECONDS(10));
+}
+
+static void usb_detach_test_after(void *state)
+{
+	struct usb_detach_test_fixture *fixture = state;
+
+	attach_src_snk_common_after(&fixture->fixture);
+}
+
+ZTEST_F(usb_detach_test, test_verify_detach_src_snk)
+{
+	struct emul_state *emul_state = &fixture->fixture;
+	struct ec_response_usb_pd_power_info src_power_info = { 0 };
+	struct ec_response_usb_pd_power_info snk_power_info = { 0 };
+
+	integration_usb_test_source_detach(emul_state);
+	integration_usb_test_sink_detach(emul_state);
+
+	k_sleep(K_SECONDS(10));
+	isl923x_emul_set_adc_vbus(emul_state->charger_isl923x_emul, 0);
+
+	snk_power_info = host_cmd_power_info(SNK_PORT);
+	src_power_info = host_cmd_power_info(SRC_PORT);
+
+	/* Validate Sink power info */
+	zassert_equal(snk_power_info.role, USB_PD_PORT_POWER_DISCONNECTED,
+		      "Power role %d, but PD reports role %d",
+		      USB_PD_PORT_POWER_DISCONNECTED, snk_power_info.role);
+	zassert_equal(snk_power_info.type, USB_CHG_TYPE_NONE,
+		      "Charger type %d, but PD reports type %d",
+		      USB_CHG_TYPE_NONE, snk_power_info.type);
+
+	zassert_equal(snk_power_info.meas.voltage_max, 0,
+		      "Charging at VBUS %dmV, but PD reports %dmV", 0,
+		      snk_power_info.meas.voltage_max);
+
+	zassert_within(snk_power_info.meas.voltage_now, 0, 10,
+		       "Actually charging at VBUS %dmV, but PD reports %dmV", 0,
+		       snk_power_info.meas.voltage_now);
+
+	zassert_equal(snk_power_info.meas.current_max, 0,
+		      "Charging at VBUS max %dmA, but PD reports %dmA", 0,
+		      snk_power_info.meas.current_max);
+
+	zassert_true(snk_power_info.meas.current_lim >= 0,
+		     "Charging at VBUS max %dmA, but PD current limit %dmA", 0,
+		     snk_power_info.meas.current_lim);
+
+	zassert_equal(snk_power_info.max_power, 0,
+		      "Charging up to %duW, PD max power %duW", 0,
+		      snk_power_info.max_power);
+
+	/* Validate Source power info */
+	zassert_equal(src_power_info.role, USB_PD_PORT_POWER_DISCONNECTED,
+		      "Power role %d, but PD reports role %d",
+		      USB_PD_PORT_POWER_DISCONNECTED, src_power_info.role);
+
+	zassert_equal(src_power_info.type, USB_CHG_TYPE_NONE,
+		      "Charger type %d, but PD reports type %d",
+		      USB_CHG_TYPE_NONE, src_power_info.type);
+
+	/* TODO(b/209907615): Confirm measure value requirements */
+	zassert_within(src_power_info.meas.voltage_now, 0, 10,
+		       "Expected Charging at VBUS %dmV, but PD reports %dmV",
+		       DEFAULT_VBUS_MV, src_power_info.meas.voltage_now);
+
+	zassert_equal(src_power_info.meas.current_max, 0,
+		      "Charging at VBUS max %dmA, but PD reports %dmA", 0,
+		      src_power_info.meas.current_max);
+}
+
+ZTEST_F(usb_detach_test, test_verify_detach_snk_src)
+{
+	struct emul_state *emul_state = &fixture->fixture;
+	struct ec_response_usb_pd_power_info src_power_info = { 0 };
+	struct ec_response_usb_pd_power_info snk_power_info = { 0 };
+
+	integration_usb_test_sink_detach(emul_state);
+	integration_usb_test_source_detach(emul_state);
+
+	k_sleep(K_SECONDS(10));
+	isl923x_emul_set_adc_vbus(emul_state->charger_isl923x_emul, 0);
+
+	snk_power_info = host_cmd_power_info(SNK_PORT);
+	src_power_info = host_cmd_power_info(SRC_PORT);
+
+	/* Validate Sink power info */
+	zassert_equal(snk_power_info.role, USB_PD_PORT_POWER_DISCONNECTED,
+		      "Power role %d, but PD reports role %d",
+		      USB_PD_PORT_POWER_DISCONNECTED, snk_power_info.role);
+	zassert_equal(snk_power_info.type, USB_CHG_TYPE_NONE,
+		      "Charger type %d, but PD reports type %d",
+		      USB_CHG_TYPE_NONE, snk_power_info.type);
+
+	zassert_equal(snk_power_info.meas.voltage_max, 0,
+		      "Charging at VBUS %dmV, but PD reports %dmV", 0,
+		      snk_power_info.meas.voltage_max);
+
+	zassert_within(snk_power_info.meas.voltage_now, 0, 10,
+		       "Actually charging at VBUS %dmV, but PD reports %dmV", 0,
+		       snk_power_info.meas.voltage_now);
+
+	zassert_equal(snk_power_info.meas.current_max, 0,
+		      "Charging at VBUS max %dmA, but PD reports %dmA", 0,
+		      snk_power_info.meas.current_max);
+
+	zassert_true(snk_power_info.meas.current_lim >= 0,
+		     "Charging at VBUS max %dmA, but PD current limit %dmA", 0,
+		     snk_power_info.meas.current_lim);
+
+	zassert_equal(snk_power_info.max_power, 0,
+		      "Charging up to %duW, PD max power %duW", 0,
+		      snk_power_info.max_power);
+
+	/* Validate Source power info */
+	zassert_equal(src_power_info.role, USB_PD_PORT_POWER_DISCONNECTED,
+		      "Power role %d, but PD reports role %d",
+		      USB_PD_PORT_POWER_DISCONNECTED, src_power_info.role);
+
+	zassert_equal(src_power_info.type, USB_CHG_TYPE_NONE,
+		      "Charger type %d, but PD reports type %d",
+		      USB_CHG_TYPE_NONE, src_power_info.type);
+
+	/* TODO(b/209907615): Confirm measure value requirements */
+	zassert_within(src_power_info.meas.voltage_now, 0, 10,
+		       "Expected Charging at VBUS %dmV, but PD reports %dmV",
+		       DEFAULT_VBUS_MV, src_power_info.meas.voltage_now);
+
+	zassert_equal(src_power_info.meas.current_max, 0,
+		      "Charging at VBUS max %dmA, but PD reports %dmA", 0,
+		      src_power_info.meas.current_max);
+}
+
+ZTEST_F(usb_detach_test, test_verify_detach_sink)
+{
+	struct emul_state *emul_state = &fixture->fixture;
+	struct ec_response_usb_pd_power_info pd_power_info = { 0 };
+
+	integration_usb_test_sink_detach(emul_state);
+	k_sleep(K_SECONDS(10));
+	isl923x_emul_set_adc_vbus(emul_state->charger_isl923x_emul, 0);
+
+	pd_power_info = host_cmd_power_info(SNK_PORT);
+
+	/* Assert */
+	zassert_equal(pd_power_info.role, USB_PD_PORT_POWER_SINK,
+		      "Power role %d, but PD reports role %d",
+		      USB_PD_PORT_POWER_SINK, pd_power_info.role);
+	zassert_equal(pd_power_info.type, USB_CHG_TYPE_PD,
+		      "Charger type %d, but PD reports type %d",
+		      USB_CHG_TYPE_PD, pd_power_info.type);
+
+	zassert_equal(pd_power_info.meas.voltage_max, DEFAULT_VBUS_MV,
+		      "Charging at VBUS %dmV, but PD reports %dmV",
+		      DEFAULT_VBUS_MV, pd_power_info.meas.voltage_max);
+
+	zassert_within(pd_power_info.meas.voltage_now, 0, 10,
+		       "Actually charging at VBUS %dmV, but PD reports %dmV", 0,
+		       pd_power_info.meas.voltage_now);
+
+	zassert_equal(pd_power_info.meas.current_max, DEFAULT_VBUS_SNK_PORT_MA,
+		      "Charging at VBUS max %dmA, but PD reports %dmA",
+		      DEFAULT_VBUS_SNK_PORT_MA, pd_power_info.meas.current_max);
+
+	zassert_true(pd_power_info.meas.current_lim >= 500,
+		     "Charging at VBUS max %dmA, but PD current limit %dmA",
+		     500, pd_power_info.meas.current_lim);
+
+	zassert_equal(pd_power_info.max_power,
+		      DEFAULT_VBUS_MV * DEFAULT_VBUS_SNK_PORT_MA,
+		      "Charging up to %duW, PD max power %duW",
+		      DEFAULT_VBUS_MV * DEFAULT_VBUS_SNK_PORT_MA,
+		      pd_power_info.max_power);
+}
+
+ZTEST_F(usb_detach_test, test_verify_detach_source)
+{
+	struct emul_state *emul_state = &fixture->fixture;
+	struct ec_response_usb_pd_power_info pd_power_info = { SNK_PORT };
+
+	integration_usb_test_source_detach(emul_state);
+	k_sleep(K_SECONDS(10));
+	isl923x_emul_set_adc_vbus(emul_state->charger_isl923x_emul, 0);
+
+	pd_power_info = host_cmd_power_info(SNK_PORT);
+
+	/* Assert */
+	zassert_equal(pd_power_info.role, USB_PD_PORT_POWER_DISCONNECTED,
+		      "Power role %d, but PD reports role %d",
+		      USB_PD_PORT_POWER_DISCONNECTED, pd_power_info.role);
+
+	zassert_equal(pd_power_info.type, USB_CHG_TYPE_NONE,
+		      "Charger type %d, but PD reports type %d",
+		      USB_CHG_TYPE_NONE, pd_power_info.type);
+
+	/* TODO(b/209907615): Confirm measure value requirements */
+	zassert_within(pd_power_info.meas.voltage_now, 0, 10,
+		       "Expected Charging at VBUS %dmV, but PD reports %dmV",
+		       DEFAULT_VBUS_MV, pd_power_info.meas.voltage_now);
+
+	zassert_equal(pd_power_info.meas.current_max, 0,
+		      "Charging at VBUS max %dmA, but PD reports %dmA", 0,
+		      pd_power_info.meas.current_max);
+}
+
+ZTEST_SUITE(usb_detach_test, drivers_predicate_post_main,
+	    integration_usb_src_snk_setup, usb_detach_test_before,
+	    usb_detach_test_after, NULL);
diff --git a/zephyr/test/drivers/default/src/integration/usbc/usb_hard_reset.c b/zephyr/test/drivers/default/src/integration/usbc/usb_hard_reset.c
new file mode 100644
index 0000000000..1c2d9704cd
--- /dev/null
+++ b/zephyr/test/drivers/default/src/integration/usbc/usb_hard_reset.c
@@ -0,0 +1,213 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "ec_tasks.h"
+#include "emul/emul_isl923x.h"
+#include "emul/tcpc/emul_tcpci_partner_drp.h"
+#include "tcpm/tcpci.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/tcpci_test_common.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "test/usb_pe.h"
+#include "usb_pd.h"
+
+#include <stdint.h>
+
+#include <zephyr/ztest.h>
+
+#define TEST_USB_PORT 0
+
+#define TEST_ADDED_PDO PDO_FIXED(10000, 3000, PDO_FIXED_UNCONSTRAINED)
+
+struct usb_hard_reset_source_fixture {
+	struct tcpci_partner_data partner_emul;
+	struct tcpci_snk_emul_data snk_ext;
+	struct tcpci_src_emul_data src_ext;
+	struct tcpci_drp_emul_data drp_ext;
+	const struct emul *tcpci_emul;
+	const struct emul *charger_emul;
+	enum pd_power_role drp_partner_pd_role;
+};
+
+static void *usb_hard_reset_source_setup(void)
+{
+	static struct usb_hard_reset_source_fixture fixture;
+
+	/* Get references for the emulators */
+	fixture.tcpci_emul = EMUL_GET_USBC_BINDING(TEST_USB_PORT, tcpc);
+	fixture.charger_emul = EMUL_GET_USBC_BINDING(TEST_USB_PORT, chg);
+	fixture.drp_partner_pd_role = PD_ROLE_SOURCE;
+
+	return &fixture;
+}
+
+static void
+tcpci_drp_emul_connect_partner(struct tcpci_partner_data *partner_emul,
+			       const struct emul *tcpci_emul,
+			       const struct emul *charger_emul)
+{
+	isl923x_emul_set_adc_vbus(charger_emul, 0);
+	zassert_ok(tcpci_emul_set_vbus_level(tcpci_emul, VBUS_SAFE0V));
+
+	zassert_ok(tcpci_partner_connect_to_tcpci(partner_emul, tcpci_emul),
+		   NULL);
+	isl923x_emul_set_adc_vbus(charger_emul, 5000);
+}
+
+static void usb_hard_reset_before(void *data)
+{
+	struct usb_hard_reset_source_fixture *fixture = data;
+
+	set_test_runner_tid();
+
+	test_set_chipset_to_g3();
+	k_sleep(K_SECONDS(1));
+
+	/* Set chipset to ON, this will set TCPM to DRP */
+	test_set_chipset_to_s0();
+
+	/* TODO(b/214401892): Check why need to give time TCPM to spin */
+	k_sleep(K_SECONDS(1));
+
+	/* Initialized DRP */
+	tcpci_partner_init(&fixture->partner_emul, PD_REV20);
+	fixture->partner_emul.extensions = tcpci_drp_emul_init(
+		&fixture->drp_ext, &fixture->partner_emul,
+		fixture->drp_partner_pd_role,
+		tcpci_src_emul_init(&fixture->src_ext, &fixture->partner_emul,
+				    NULL),
+		tcpci_snk_emul_init(&fixture->snk_ext, &fixture->partner_emul,
+				    NULL));
+	/* Add additional Sink PDO to partner to verify
+	 * PE_DR_SNK_Get_Sink_Cap/PE_SRC_Get_Sink_Cap (these are shared PE
+	 * states) state was reached
+	 */
+	fixture->snk_ext.pdo[1] = TEST_ADDED_PDO;
+
+	/* Turn TCPCI rev 2 ON */
+	tcpc_config[TEST_USB_PORT].flags |= TCPC_FLAGS_TCPCI_REV2_0;
+
+	tcpci_drp_emul_connect_partner(&fixture->partner_emul,
+				       fixture->tcpci_emul,
+				       fixture->charger_emul);
+
+	k_sleep(K_SECONDS(10));
+}
+
+static void usb_hard_reset_after(void *data)
+{
+	struct usb_hard_reset_source_fixture *fixture = data;
+
+	isl923x_emul_set_adc_vbus(fixture->charger_emul, 0);
+	zassert_ok(tcpci_emul_disconnect_partner(fixture->tcpci_emul));
+	k_sleep(K_SECONDS(1));
+}
+
+/** ZTEST_SUITE to setup DRP partner_emul as SOURCE  */
+ZTEST_SUITE(usb_hard_reset_source, drivers_predicate_post_main,
+	    usb_hard_reset_source_setup, usb_hard_reset_before,
+	    usb_hard_reset_after, NULL);
+
+/**
+ * @brief TestPurpose: Perform a normal hard reset.
+ */
+ZTEST_F(usb_hard_reset_source, test_normal)
+{
+	int state;
+
+	/* Partner sends the Hard Reset. */
+	tcpci_partner_common_send_hard_reset(&fixture->partner_emul);
+	/* Partner waits ~30 ms - 650 ms (PD_T_SAFE_0V) */
+	k_sleep(K_MSEC(30));
+	/* Partner drops to vSafe0V */
+	isl923x_emul_set_adc_vbus(fixture->charger_emul, 0);
+	zassert_ok(tcpci_emul_set_vbus_level(fixture->tcpci_emul, VBUS_SAFE0V));
+
+	/* Partner waits ~660 ms - 1000 ms (PD_T_SRC_RECOVER_MAX)
+	 * + 0 ms - 275 ms (PD_T_SRC_TURN_ON)
+	 */
+	k_sleep(K_MSEC(660));
+
+	/* Partner sets VBUS present */
+	isl923x_emul_set_adc_vbus(fixture->charger_emul, 5000);
+	zassert_ok(
+		tcpci_emul_set_vbus_level(fixture->tcpci_emul, VBUS_PRESENT));
+
+	/* Wait for everything to settle, and check state. */
+	k_sleep(K_SECONDS(2));
+	state = get_state_tc(TEST_USB_PORT);
+	zassert_equal(state, /* TC_ATTACHED_SNK */ 7, "Got %d", state);
+	state = get_state_pe(TEST_USB_PORT);
+	zassert_equal(state, PE_SNK_READY, "Got %d", state);
+}
+
+/**
+ * @brief TestPurpose: Perform a hard reset where the VBUS doesn't reach
+ *        vSave0V on time.
+ */
+ZTEST_F(usb_hard_reset_source, test_vsafe0v_late)
+{
+	int state;
+
+	/* Partner sends the Hard Reset. */
+	tcpci_partner_common_send_hard_reset(&fixture->partner_emul);
+	/* Partner more than ~30 ms - 650 ms (PD_T_SAFE_0V) */
+	k_sleep(K_MSEC(660));
+	/* Partner drops to vSafe0V */
+	isl923x_emul_set_adc_vbus(fixture->charger_emul, 0);
+	zassert_ok(tcpci_emul_set_vbus_level(fixture->tcpci_emul, VBUS_SAFE0V));
+
+	/* Partner waits ~660 ms - 1000 ms (PD_T_SRC_RECOVER_MAX)
+	 * + 0 ms - 275 ms (PD_T_SRC_TURN_ON)
+	 */
+	k_sleep(K_MSEC(660));
+
+	/* Partner sets VBUS present */
+	isl923x_emul_set_adc_vbus(fixture->charger_emul, 5000);
+	zassert_ok(
+		tcpci_emul_set_vbus_level(fixture->tcpci_emul, VBUS_PRESENT));
+
+	/* Wait for everything to settle, and check state. */
+	k_sleep(K_SECONDS(2));
+	state = get_state_tc(TEST_USB_PORT);
+	zassert_equal(state, /* TC_ATTACHED_SNK */ 7, "Got %d", state);
+	state = get_state_pe(TEST_USB_PORT);
+	zassert_equal(state, PE_SNK_READY, "Got %d", state);
+}
+
+/**
+ * @brief TestPurpose: Perform a hard reset where the VBUS present is late.
+ */
+ZTEST_F(usb_hard_reset_source, test_vbus_present_late)
+{
+	int state;
+
+	/* Partner sends the Hard Reset. */
+	tcpci_partner_common_send_hard_reset(&fixture->partner_emul);
+	/* Partner waits ~30 ms - 650 ms (PD_T_SAFE_0V) */
+	k_sleep(K_MSEC(30));
+	/* Partner drops to vSafe0V */
+	isl923x_emul_set_adc_vbus(fixture->charger_emul, 0);
+	zassert_ok(tcpci_emul_set_vbus_level(fixture->tcpci_emul, VBUS_SAFE0V));
+
+	/* Partner waits more than ~660 ms - 1000 ms (PD_T_SRC_RECOVER_MAX)
+	 * + 0 ms - 275 ms (PD_T_SRC_TURN_ON)
+	 */
+	k_sleep(K_MSEC(1300));
+
+	/* Partner sets VBUS present */
+	isl923x_emul_set_adc_vbus(fixture->charger_emul, 5000);
+	zassert_ok(
+		tcpci_emul_set_vbus_level(fixture->tcpci_emul, VBUS_PRESENT));
+
+	/* Wait for everything to settle, and check state. */
+	k_sleep(K_SECONDS(2));
+	state = get_state_tc(TEST_USB_PORT);
+	zassert_equal(state, /* TC_ATTACHED_SNK */ 7, "Got %d", state);
+	state = get_state_pe(TEST_USB_PORT);
+	zassert_equal(state, PE_SNK_READY, "Got %d", state);
+}
diff --git a/zephyr/test/drivers/default/src/integration/usbc/usb_pd_bist_shared.c b/zephyr/test/drivers/default/src/integration/usbc/usb_pd_bist_shared.c
new file mode 100644
index 0000000000..6284881690
--- /dev/null
+++ b/zephyr/test/drivers/default/src/integration/usbc/usb_pd_bist_shared.c
@@ -0,0 +1,221 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "emul/emul_isl923x.h"
+#include "emul/emul_smart_battery.h"
+#include "emul/tcpc/emul_tcpci_partner_snk.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "usb_common.h"
+#include "usb_pd.h"
+#include "util.h"
+
+#include <zephyr/ztest.h>
+
+struct usb_pd_bist_shared_fixture {
+	struct tcpci_partner_data sink_5v_500ma;
+	struct tcpci_snk_emul_data snk_ext_500ma;
+	struct tcpci_partner_data src;
+	struct tcpci_src_emul_data src_ext;
+	const struct emul *tcpci_emul; /* USBC_PORT_C0 in dts */
+	const struct emul *tcpci_ps8xxx_emul; /* USBC_PORT_C1 in dts */
+	const struct emul *charger_emul;
+};
+
+static void *usb_pd_bist_shared_setup(void)
+{
+	static struct usb_pd_bist_shared_fixture test_fixture;
+
+	/* Get references for the emulators */
+	test_fixture.tcpci_emul = EMUL_GET_USBC_BINDING(0, tcpc);
+	test_fixture.charger_emul = EMUL_GET_USBC_BINDING(0, chg);
+	test_fixture.tcpci_ps8xxx_emul = EMUL_GET_USBC_BINDING(1, tcpc);
+
+	return &test_fixture;
+}
+
+static void usb_pd_bist_shared_before(void *data)
+{
+	struct usb_pd_bist_shared_fixture *test_fixture = data;
+
+	/* Set chipset to ON, this will set TCPM to DRP */
+	test_set_chipset_to_s0();
+
+	/* TODO(b/214401892): Check why need to give time TCPM to spin */
+	k_sleep(K_SECONDS(1));
+
+	/* Initialized the sink to request 5V and 500mA */
+	tcpci_partner_init(&test_fixture->sink_5v_500ma, PD_REV30);
+	test_fixture->sink_5v_500ma.extensions =
+		tcpci_snk_emul_init(&test_fixture->snk_ext_500ma,
+				    &test_fixture->sink_5v_500ma, NULL);
+	test_fixture->snk_ext_500ma.pdo[0] = PDO_FIXED(5000, 500, 0);
+
+	/* Initialized the source */
+	tcpci_partner_init(&test_fixture->src, PD_REV30);
+	test_fixture->src.extensions = tcpci_src_emul_init(
+		&test_fixture->src_ext, &test_fixture->src, NULL);
+
+	/* Initially connect the 5V 500mA partner to C0 */
+	connect_sink_to_port(&test_fixture->sink_5v_500ma,
+			     test_fixture->tcpci_emul,
+			     test_fixture->charger_emul);
+}
+
+static void usb_pd_bist_shared_after(void *data)
+{
+	struct usb_pd_bist_shared_fixture *test_fixture = data;
+
+	/* Disocnnect C0 as sink, C1 as source */
+	disconnect_sink_from_port(test_fixture->tcpci_emul);
+	disconnect_source_from_port(test_fixture->tcpci_ps8xxx_emul,
+				    test_fixture->charger_emul);
+	host_cmd_typec_control_bist_share_mode(USBC_PORT_C0, 0);
+}
+
+ZTEST_SUITE(usb_pd_bist_shared, drivers_predicate_post_main,
+	    usb_pd_bist_shared_setup, usb_pd_bist_shared_before,
+	    usb_pd_bist_shared_after, NULL);
+
+ZTEST_F(usb_pd_bist_shared, test_verify_bist_shared_mode)
+{
+	uint32_t bist_data;
+	uint32_t f5v_cap;
+
+	/*
+	 * Verify we were offered the 1.5A source cap because of our low current
+	 * needs initially
+	 */
+	f5v_cap = fixture->snk_ext_500ma.last_5v_source_cap;
+	/* Capability should be 5V fixed, 1.5 A */
+	zassert_equal((f5v_cap & PDO_TYPE_MASK), PDO_TYPE_FIXED,
+		      "PDO type wrong");
+	zassert_equal(PDO_FIXED_VOLTAGE(f5v_cap), 5000, "PDO voltage wrong");
+	zassert_equal(PDO_FIXED_CURRENT(f5v_cap), 1500,
+		      "PDO initial current wrong");
+
+	/* Start up BIST shared test mode */
+	bist_data = BDO(BDO_MODE_SHARED_ENTER, 0);
+	zassert_ok(tcpci_partner_send_data_msg(&fixture->sink_5v_500ma,
+					       PD_DATA_BIST, &bist_data, 1, 0),
+		   "Failed to send BIST enter message");
+
+	/* The DUT has tBISTSharedTestMode (1 second) to offer us 3A now */
+	k_sleep(K_SECONDS(1));
+
+	f5v_cap = fixture->snk_ext_500ma.last_5v_source_cap;
+	/* Capability should be 5V fixed, 3.0 A */
+	zassert_equal((f5v_cap & PDO_TYPE_MASK), PDO_TYPE_FIXED,
+		      "PDO type wrong");
+	zassert_equal(PDO_FIXED_VOLTAGE(f5v_cap), 5000, "PDO voltage wrong");
+	zassert_equal(PDO_FIXED_CURRENT(f5v_cap), 3000,
+		      "PDO current didn't increase in BIST mode");
+
+	/* Leave BIST shared test mode */
+	bist_data = BDO(BDO_MODE_SHARED_EXIT, 0);
+	zassert_ok(tcpci_partner_send_data_msg(&fixture->sink_5v_500ma,
+					       PD_DATA_BIST, &bist_data, 1, 0),
+		   "Failed to send BIST exit message");
+
+	/*
+	 * The DUT may now execute ErrorRecovery or simply send a new
+	 * Source_Cap.  Either way, we should go back to 1.5 A
+	 */
+	k_sleep(K_SECONDS(5));
+
+	f5v_cap = fixture->snk_ext_500ma.last_5v_source_cap;
+	/* Capability should be 5V fixed, 1.5 A */
+	zassert_equal((f5v_cap & PDO_TYPE_MASK), PDO_TYPE_FIXED,
+		      "PDO type wrong");
+	zassert_equal(PDO_FIXED_VOLTAGE(f5v_cap), 5000, "PDO voltage wrong");
+	zassert_equal(PDO_FIXED_CURRENT(f5v_cap), 1500,
+		      "PDO current didn't decrease after BIST exit");
+}
+
+ZTEST_F(usb_pd_bist_shared, test_verify_bist_shared_no_snk_entry)
+{
+	uint32_t bist_data;
+	uint32_t f5v_cap;
+
+	/*
+	 * Ensure we only enter BIST shared mode when acting as a source.  We
+	 * must not enter shared mode from PE_SNK_Ready.
+	 */
+
+	/* Attach a new source */
+	connect_source_to_port(&fixture->src, &fixture->src_ext, 1,
+			       fixture->tcpci_ps8xxx_emul,
+			       fixture->charger_emul);
+
+	/* Have the source send the BIST Enter Mode */
+	bist_data = BDO(BDO_MODE_SHARED_ENTER, 0);
+	zassert_ok(tcpci_partner_send_data_msg(&fixture->src, PD_DATA_BIST,
+					       &bist_data, 1, 0),
+		   "Failed to send BIST enter message");
+
+	/* Wait tBISTSharedTestMode (1 second) */
+	k_sleep(K_SECONDS(1));
+
+	/* Verify our low power sink on C0 still only has 1.5 A */
+	f5v_cap = fixture->snk_ext_500ma.last_5v_source_cap;
+	/* Capability should be 5V fixed, 1.5 A */
+	zassert_equal((f5v_cap & PDO_TYPE_MASK), PDO_TYPE_FIXED,
+		      "PDO type wrong");
+	zassert_equal(PDO_FIXED_VOLTAGE(f5v_cap), 5000, "PDO voltage wrong");
+	zassert_equal(PDO_FIXED_CURRENT(f5v_cap), 1500,
+		      "PDO current incorrect after bad BIST entry");
+}
+
+ZTEST_F(usb_pd_bist_shared, test_verify_bist_shared_exit_no_action)
+{
+	uint32_t bist_data;
+	uint32_t f5v_cap;
+
+	/*
+	 * Verify that if we receive a BIST shared mode exit with no entry, we
+	 * take no action on the port.
+	 */
+	tcpci_snk_emul_clear_last_5v_cap(&fixture->snk_ext_500ma);
+
+	bist_data = BDO(BDO_MODE_SHARED_EXIT, 0);
+	zassert_ok(tcpci_partner_send_data_msg(&fixture->sink_5v_500ma,
+					       PD_DATA_BIST, &bist_data, 1, 0),
+		   "Failed to send BIST exit message");
+
+	/* Wait for the time it would take to settle out exit */
+	k_sleep(K_SECONDS(5));
+
+	/* Verify we didn't receive any new source caps due to the mode exit */
+	f5v_cap = fixture->snk_ext_500ma.last_5v_source_cap;
+	zassert_equal(f5v_cap, 0, "Received unexpected source cap");
+}
+
+ZTEST_F(usb_pd_bist_shared, test_verify_control_bist_shared_mode)
+{
+	uint32_t f5v_cap;
+
+	host_cmd_typec_control_bist_share_mode(USBC_PORT_C0, 1);
+	zassert_ok(tcpci_partner_send_control_msg(&fixture->sink_5v_500ma,
+						  PD_CTRL_GET_SOURCE_CAP, 0),
+		   "Failed to send get src cap");
+	/* wait tSenderResponse (26 ms) */
+	k_sleep(K_MSEC(26));
+	/*
+	 * Verify we were offered the 3A source cap because of
+	 * bist share mode be enabled.
+	 */
+	f5v_cap = fixture->snk_ext_500ma.last_5v_source_cap;
+	/* Capability should be 5V fixed, 3 A */
+	zassert_equal((f5v_cap & PDO_TYPE_MASK), PDO_TYPE_FIXED,
+		      "PDO type wrong");
+	zassert_equal(PDO_FIXED_VOLTAGE(f5v_cap), 5000, "PDO voltage wrong");
+	zassert_equal(PDO_FIXED_CURRENT(f5v_cap), 3000,
+		      "PDO initial current wrong");
+	zassert_equal(typec_get_default_current_limit_rp(USBC_PORT_C0),
+		      TYPEC_RP_3A0, "Default rp not 3A");
+
+	host_cmd_typec_control_bist_share_mode(USBC_PORT_C0, 0);
+}
diff --git a/zephyr/test/drivers/default/src/integration/usbc/usb_pd_ctrl_msg.c b/zephyr/test/drivers/default/src/integration/usbc/usb_pd_ctrl_msg.c
new file mode 100644
index 0000000000..36b539aeb6
--- /dev/null
+++ b/zephyr/test/drivers/default/src/integration/usbc/usb_pd_ctrl_msg.c
@@ -0,0 +1,387 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "ec_tasks.h"
+#include "emul/emul_isl923x.h"
+#include "emul/tcpc/emul_tcpci_partner_drp.h"
+#include "tcpm/tcpci.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "test/usb_pe.h"
+#include "usb_pd.h"
+
+#include <stdint.h>
+
+#include <zephyr/ztest.h>
+
+#define TEST_USB_PORT 0
+BUILD_ASSERT(TEST_USB_PORT == USBC_PORT_C0);
+
+#define TEST_ADDED_PDO PDO_FIXED(10000, 3000, PDO_FIXED_UNCONSTRAINED)
+
+struct usb_pd_ctrl_msg_test_fixture {
+	struct tcpci_partner_data partner_emul;
+	struct tcpci_snk_emul_data snk_ext;
+	struct tcpci_src_emul_data src_ext;
+	struct tcpci_drp_emul_data drp_ext;
+	const struct emul *tcpci_emul;
+	const struct emul *charger_emul;
+	enum pd_power_role drp_partner_pd_role;
+};
+
+struct usb_pd_ctrl_msg_test_sink_fixture {
+	struct usb_pd_ctrl_msg_test_fixture fixture;
+};
+
+struct usb_pd_ctrl_msg_test_source_fixture {
+	struct usb_pd_ctrl_msg_test_fixture fixture;
+};
+
+static void
+tcpci_drp_emul_connect_partner(struct tcpci_partner_data *partner_emul,
+			       const struct emul *tcpci_emul,
+			       const struct emul *charger_emul)
+{
+	isl923x_emul_set_adc_vbus(charger_emul, 0);
+	zassert_ok(tcpci_emul_set_vbus_level(tcpci_emul, VBUS_SAFE0V));
+	zassert_ok(tcpci_partner_connect_to_tcpci(partner_emul, tcpci_emul),
+		   NULL);
+}
+
+static void disconnect_partner(struct usb_pd_ctrl_msg_test_fixture *fixture)
+{
+	zassert_ok(tcpci_emul_disconnect_partner(fixture->tcpci_emul));
+	k_sleep(K_SECONDS(1));
+}
+
+static void *usb_pd_ctrl_msg_setup_emul(void)
+{
+	static struct usb_pd_ctrl_msg_test_fixture fixture;
+
+	/* Get references for the emulators */
+	fixture.tcpci_emul = EMUL_GET_USBC_BINDING(TEST_USB_PORT, tcpc);
+	fixture.charger_emul = EMUL_GET_USBC_BINDING(TEST_USB_PORT, chg);
+
+	return &fixture;
+}
+
+static void *usb_pd_ctrl_msg_sink_setup(void)
+{
+	struct usb_pd_ctrl_msg_test_fixture *fixture =
+		usb_pd_ctrl_msg_setup_emul();
+
+	fixture->drp_partner_pd_role = PD_ROLE_SINK;
+
+	return fixture;
+}
+
+static void *usb_pd_ctrl_msg_source_setup(void)
+{
+	struct usb_pd_ctrl_msg_test_fixture *fixture =
+		usb_pd_ctrl_msg_setup_emul();
+
+	fixture->drp_partner_pd_role = PD_ROLE_SOURCE;
+
+	return fixture;
+}
+
+static void usb_pd_ctrl_msg_before(void *data)
+{
+	struct usb_pd_ctrl_msg_test_fixture *fixture = data;
+
+	set_test_runner_tid();
+
+	test_set_chipset_to_g3();
+	k_sleep(K_SECONDS(1));
+
+	/* Set chipset to ON, this will set TCPM to DRP */
+	test_set_chipset_to_s0();
+
+	/* TODO(b/214401892): Check why need to give time TCPM to spin */
+	k_sleep(K_SECONDS(1));
+
+	/* Initialized DRP */
+	tcpci_partner_init(&fixture->partner_emul, PD_REV20);
+	fixture->partner_emul.extensions = tcpci_drp_emul_init(
+		&fixture->drp_ext, &fixture->partner_emul,
+		fixture->drp_partner_pd_role,
+		tcpci_src_emul_init(&fixture->src_ext, &fixture->partner_emul,
+				    NULL),
+		tcpci_snk_emul_init(&fixture->snk_ext, &fixture->partner_emul,
+				    NULL));
+	/* Add additional Sink PDO to partner to verify
+	 * PE_DR_SNK_Get_Sink_Cap/PE_SRC_Get_Sink_Cap (these are shared PE
+	 * states) state was reached
+	 */
+	fixture->snk_ext.pdo[1] = TEST_ADDED_PDO;
+
+	/* Turn TCPCI rev 2 ON */
+	tcpc_config[TEST_USB_PORT].flags |= TCPC_FLAGS_TCPCI_REV2_0;
+
+	tcpci_drp_emul_connect_partner(&fixture->partner_emul,
+				       fixture->tcpci_emul,
+				       fixture->charger_emul);
+
+	k_sleep(K_SECONDS(10));
+}
+
+static void usb_pd_ctrl_msg_after(void *data)
+{
+	struct usb_pd_ctrl_msg_test_fixture *fixture = data;
+
+	disconnect_partner(fixture);
+}
+
+/** ZTEST_SUITE to setup DRP partner_emul as SINK */
+ZTEST_SUITE(usb_pd_ctrl_msg_test_sink, drivers_predicate_post_main,
+	    usb_pd_ctrl_msg_sink_setup, usb_pd_ctrl_msg_before,
+	    usb_pd_ctrl_msg_after, NULL);
+
+/** ZTEST_SUITE to setup DRP partner_emul as SOURCE  */
+ZTEST_SUITE(usb_pd_ctrl_msg_test_source, drivers_predicate_post_main,
+	    usb_pd_ctrl_msg_source_setup, usb_pd_ctrl_msg_before,
+	    usb_pd_ctrl_msg_after, NULL);
+
+ZTEST_F(usb_pd_ctrl_msg_test_sink, test_verify_vconn_swap)
+{
+	struct usb_pd_ctrl_msg_test_fixture *super_fixture = &fixture->fixture;
+	struct ec_response_typec_status snk_resp = { 0 };
+	int rv = 0;
+
+	snk_resp = host_cmd_typec_status(TEST_USB_PORT);
+
+	zassert_equal(PD_ROLE_VCONN_SRC, snk_resp.vconn_role,
+		      "SNK Returned vconn_role=%u", snk_resp.vconn_role);
+
+	/* Send VCONN_SWAP request */
+	rv = tcpci_partner_send_control_msg(&super_fixture->partner_emul,
+					    PD_CTRL_VCONN_SWAP, 0);
+	zassert_ok(rv, "Failed to send VCONN_SWAP request, rv=%d", rv);
+
+	k_sleep(K_SECONDS(1));
+
+	snk_resp = host_cmd_typec_status(TEST_USB_PORT);
+	zassert_equal(PD_ROLE_VCONN_OFF, snk_resp.vconn_role,
+		      "SNK Returned vconn_role=%u", snk_resp.vconn_role);
+}
+
+ZTEST_F(usb_pd_ctrl_msg_test_sink, test_verify_pr_swap)
+{
+	struct usb_pd_ctrl_msg_test_fixture *super_fixture = &fixture->fixture;
+	struct ec_response_typec_status snk_resp = { 0 };
+	int rv = 0;
+
+	snk_resp = host_cmd_typec_status(TEST_USB_PORT);
+
+	zassert_equal(PD_ROLE_SINK, snk_resp.power_role,
+		      "SNK Returned power_role=%u", snk_resp.power_role);
+
+	/* Ignore ACCEPT in common handler for PR Swap request,
+	 * causes soft reset
+	 */
+	tcpci_partner_common_handler_mask_msg(&super_fixture->partner_emul,
+					      PD_CTRL_ACCEPT, true);
+
+	/* Send PR_SWAP request */
+	rv = tcpci_partner_send_control_msg(&super_fixture->partner_emul,
+					    PD_CTRL_PR_SWAP, 0);
+	zassert_ok(rv, "Failed to send PR_SWAP request, rv=%d", rv);
+
+	/* Send PS_RDY request */
+	rv = tcpci_partner_send_control_msg(&super_fixture->partner_emul,
+					    PD_CTRL_PS_RDY, 15);
+	zassert_ok(rv, "Failed to send PS_RDY request, rv=%d", rv);
+
+	k_sleep(K_MSEC(20));
+
+	snk_resp = host_cmd_typec_status(TEST_USB_PORT);
+	zassert_equal(PD_ROLE_SOURCE, snk_resp.power_role,
+		      "SNK Returned power_role=%u", snk_resp.power_role);
+
+	tcpci_partner_common_handler_mask_msg(&super_fixture->partner_emul,
+					      PD_CTRL_ACCEPT, false);
+}
+
+/**
+ * @brief TestPurpose: Verify DR Swap when DRP partner is configured as sink.
+ *
+ * @details
+ *  - TCPM is brought up as Sink/UFP
+ *  - TCPM over time will evaluate and trigger DR Swap to Sink/DFP
+ *
+ * Expected Results
+ *  - TypeC status query returns PD_ROLE_DFP
+ */
+ZTEST_F(usb_pd_ctrl_msg_test_sink, test_verify_dr_swap)
+{
+	struct ec_response_typec_status typec_status =
+		host_cmd_typec_status(TEST_USB_PORT);
+
+	zassert_equal(PD_ROLE_DFP, typec_status.data_role,
+		      "Returned data_role=%u", typec_status.data_role);
+}
+
+/**
+ * @brief TestPurpose: Verify DR Swap is rejected when DRP partner is
+ * configured as source.
+ *
+ * @details
+ *  - TCPM is configured initially as Sink/UFP.
+ *  - TCPM initiates DR swap according to policy (Sink/DFP)
+ *  - Partner requests DR Swap.
+ *  - Verify Request is rejected due the TCPM not being UFP.
+ *
+ * Expected Results
+ *  - Data role does not change on TEST_USB_PORT after DR Swap request.
+ */
+ZTEST_F(usb_pd_ctrl_msg_test_source, test_verify_dr_swap_rejected)
+{
+	struct usb_pd_ctrl_msg_test_fixture *super_fixture = &fixture->fixture;
+	struct ec_response_typec_status typec_status = { 0 };
+	int rv = 0;
+
+	typec_status = host_cmd_typec_status(TEST_USB_PORT);
+	zassert_equal(PD_ROLE_DFP, typec_status.data_role,
+		      "Returned data_role=%u", typec_status.data_role);
+
+	/* Send DR_SWAP request */
+	rv = tcpci_partner_send_control_msg(&super_fixture->partner_emul,
+					    PD_CTRL_DR_SWAP, 0);
+	zassert_ok(rv, "Failed to send DR_SWAP request, rv=%d", rv);
+
+	k_sleep(K_MSEC(20));
+
+	/* Verify DR_Swap request is REJECTED */
+	typec_status = host_cmd_typec_status(TEST_USB_PORT);
+	zassert_equal(PD_ROLE_DFP, typec_status.data_role,
+		      "Returned data_role=%u", typec_status.data_role);
+}
+
+/**
+ * @brief TestPurpose: Verify DR Swap via DPM request when DRP is configured
+ * as source
+ *
+ * @details
+ *  - TCPM is configured initially as Sink/UFP.
+ *  - TCPM initiates DR swap according to policy (Sink/DFP)
+ *  - Test case initiates DPM DR Swap.
+ *  - Verify DR Swap Request is processed.
+ *
+ * Expected Results
+ *  - Data role changes after DPM DR Swap request
+ */
+ZTEST_F(usb_pd_ctrl_msg_test_source, test_verify_dpm_dr_swap)
+{
+	struct ec_response_typec_status typec_status = { 0 };
+
+	typec_status = host_cmd_typec_status(TEST_USB_PORT);
+	zassert_equal(PD_ROLE_DFP, typec_status.data_role,
+		      "Returned data_role=%u", typec_status.data_role);
+
+	pd_dpm_request(TEST_USB_PORT, DPM_REQUEST_DR_SWAP);
+	k_sleep(K_SECONDS(1));
+
+	typec_status = host_cmd_typec_status(TEST_USB_PORT);
+	zassert_equal(PD_ROLE_UFP, typec_status.data_role,
+		      "Returned data_role=%u", typec_status.data_role);
+}
+
+/**
+ * @brief TestPurpose: Verify TCPM initiates Get_Sink_Cap message during a typec
+ * status host command and receives sink_capabilities message.
+ *
+ * @details
+ *  - TCPM is configured initially as Sink
+ *  - TypeC Status Host Command is Invoked
+ *
+ * Expected Results
+ *  - TypeC Status Host Command reveals sink capabilility PDOs.
+ */
+ZTEST(usb_pd_ctrl_msg_test_source, test_verify_dpm_get_sink_cap)
+{
+	struct ec_response_typec_status typec_status = { 0 };
+
+	typec_status = host_cmd_typec_status(TEST_USB_PORT);
+
+	zassert_true(typec_status.sink_cap_count > 1);
+	zassert_equal(typec_status.sink_cap_pdos[1], TEST_ADDED_PDO);
+}
+
+/**
+ * @brief TestPurpose: Verify TCPM initiates Get_Sink_Cap message during a typec
+ * status host command and receives sink_capabilities message.
+ *
+ * @details
+ *  - TCPM is configured initially as Source
+ *  - TypeC Status Host Command is Invoked
+ *
+ * Expected Results
+ *  - TypeC Status Host Command reveals sink capabilility PDOs.
+ */
+ZTEST(usb_pd_ctrl_msg_test_sink, test_verify_get_sink_cap)
+{
+	struct ec_response_typec_status typec_status = { 0 };
+
+	typec_status = host_cmd_typec_status(TEST_USB_PORT);
+
+	zassert_true(typec_status.sink_cap_count > 1);
+	zassert_equal(typec_status.sink_cap_pdos[1], TEST_ADDED_PDO);
+}
+
+/**
+ * @brief TestPurpose: Verify BIST TX MODE 2.
+ *
+ * @details
+ *  - TCPM is configured initially as Sink
+ *  - Initiate BIST TX
+ *
+ * Expected Results
+ *  - BIST occurs and we transition back to READY state
+ */
+ZTEST_F(usb_pd_ctrl_msg_test_source, test_verify_bist_tx_mode2)
+{
+	struct usb_pd_ctrl_msg_test_fixture *super_fixture = &fixture->fixture;
+	uint32_t bdo = BDO(BDO_MODE_CARRIER2, 0);
+
+	tcpci_partner_send_data_msg(&super_fixture->partner_emul, PD_DATA_BIST,
+				    &bdo, 1, 0);
+
+	pd_dpm_request(TEST_USB_PORT, DPM_REQUEST_BIST_TX);
+	k_sleep(K_MSEC(10));
+	zassert_equal(get_state_pe(TEST_USB_PORT), PE_BIST_TX);
+
+	k_sleep(K_SECONDS(5));
+	zassert_equal(get_state_pe(TEST_USB_PORT), PE_SNK_READY);
+}
+
+/**
+ * @brief TestPurpose: Verify BIST TX TEST DATA.
+ *
+ * @details
+ *  - TCPM is configured initially as Sink
+ *  - Initiate BIST TX
+ *  - End testing via signaling a Hard Reset
+ *
+ * Expected Results
+ *  - Partner remains in BIST_TX state until hard reset is received.
+ */
+ZTEST_F(usb_pd_ctrl_msg_test_source, test_verify_bist_tx_test_data)
+{
+	struct usb_pd_ctrl_msg_test_fixture *super_fixture = &fixture->fixture;
+	uint32_t bdo = BDO(BDO_MODE_TEST_DATA, 0);
+
+	tcpci_partner_send_data_msg(&super_fixture->partner_emul, PD_DATA_BIST,
+				    &bdo, 1, 0);
+
+	pd_dpm_request(TEST_USB_PORT, DPM_REQUEST_BIST_TX);
+	k_sleep(K_SECONDS(5));
+	zassert_equal(get_state_pe(TEST_USB_PORT), PE_BIST_TX);
+
+	tcpci_partner_common_send_hard_reset(&super_fixture->partner_emul);
+	k_sleep(K_SECONDS(1));
+	zassert_equal(get_state_pe(TEST_USB_PORT), PE_SNK_READY);
+}
diff --git a/zephyr/test/drivers/default/src/integration/usbc/usb_pd_rev3.c b/zephyr/test/drivers/default/src/integration/usbc/usb_pd_rev3.c
new file mode 100644
index 0000000000..0ae92b88b4
--- /dev/null
+++ b/zephyr/test/drivers/default/src/integration/usbc/usb_pd_rev3.c
@@ -0,0 +1,486 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "battery_smart.h"
+#include "chipset.h"
+#include "ec_commands.h"
+#include "emul/emul_isl923x.h"
+#include "emul/emul_smart_battery.h"
+#include "emul/tcpc/emul_tcpci_partner_src.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "usb_common.h"
+#include "usb_pd.h"
+#include "util.h"
+
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/sys/slist.h>
+#include <zephyr/ztest.h>
+
+#define TEST_PORT 0
+
+struct usb_attach_5v_3a_pd_source_rev3_fixture {
+	struct tcpci_partner_data source_5v_3a;
+	struct tcpci_src_emul_data src_ext;
+	const struct emul *tcpci_emul;
+	const struct emul *charger_emul;
+};
+
+static void *usb_attach_5v_3a_pd_source_setup(void)
+{
+	static struct usb_attach_5v_3a_pd_source_rev3_fixture test_fixture;
+
+	/* Get references for the emulators */
+	test_fixture.tcpci_emul = EMUL_GET_USBC_BINDING(0, tcpc);
+	test_fixture.charger_emul = EMUL_GET_USBC_BINDING(0, chg);
+
+	/* Initialized the charger to supply 5V and 3A */
+	tcpci_partner_init(&test_fixture.source_5v_3a, PD_REV30);
+	test_fixture.source_5v_3a.extensions = tcpci_src_emul_init(
+		&test_fixture.src_ext, &test_fixture.source_5v_3a, NULL);
+	test_fixture.src_ext.pdo[1] =
+		PDO_FIXED(5000, 3000, PDO_FIXED_UNCONSTRAINED);
+
+	/* Set the partner's USB PD Revision to 3.1 */
+	test_fixture.source_5v_3a.rmdo = 0x31000000;
+
+	return &test_fixture;
+}
+
+static void usb_attach_5v_3a_pd_source_before(void *data)
+{
+	struct usb_attach_5v_3a_pd_source_rev3_fixture *fixture = data;
+
+	/* Set chipset to ON, this will set TCPM to DRP */
+	test_set_chipset_to_s0();
+
+	/* TODO(b/214401892): Check why need to give time TCPM to spin */
+	k_sleep(K_SECONDS(1));
+
+	connect_source_to_port(&fixture->source_5v_3a, &fixture->src_ext, 1,
+			       fixture->tcpci_emul, fixture->charger_emul);
+
+	/* Clear Alert and Status receive checks */
+	tcpci_src_emul_clear_alert_received(&fixture->src_ext);
+	tcpci_src_emul_clear_status_received(&fixture->src_ext);
+	zassert_false(fixture->src_ext.alert_received);
+	zassert_false(fixture->src_ext.status_received);
+
+	/* Initial check on power state */
+	zassert_true(chipset_in_state(CHIPSET_STATE_ON));
+}
+
+static void usb_attach_5v_3a_pd_source_after(void *data)
+{
+	struct usb_attach_5v_3a_pd_source_rev3_fixture *fixture = data;
+
+	disconnect_source_from_port(fixture->tcpci_emul, fixture->charger_emul);
+}
+
+ZTEST_SUITE(usb_attach_5v_3a_pd_source_rev3, drivers_predicate_post_main,
+	    usb_attach_5v_3a_pd_source_setup, usb_attach_5v_3a_pd_source_before,
+	    usb_attach_5v_3a_pd_source_after, NULL);
+
+ZTEST_F(usb_attach_5v_3a_pd_source_rev3, test_batt_cap)
+{
+	int battery_index = 0;
+
+	tcpci_partner_common_send_get_battery_capabilities(
+		&fixture->source_5v_3a, battery_index);
+
+	/* Allow some time for TCPC to process and respond */
+	k_sleep(K_SECONDS(1));
+
+	zassert_true(fixture->source_5v_3a.battery_capabilities
+			     .have_response[battery_index],
+		     "No battery capabilities response stored.");
+
+	/* The response */
+	struct pd_bcdb *bcdb =
+		&fixture->source_5v_3a.battery_capabilities.bcdb[battery_index];
+
+	zassert_equal(USB_VID_GOOGLE, bcdb->vid, "Incorrect battery VID");
+	zassert_equal(CONFIG_USB_PID, bcdb->pid, "Incorrect battery PID");
+	zassert_false((bcdb->battery_type) & BIT(0),
+		      "Invalid battery ref bit should not be set");
+
+	/* Verify the battery capacity and last full charge capacity. These
+	 * fields require that the battery is present and that we can
+	 * access information about the nominal voltage and capacity.
+	 *
+	 * TODO(b/237427945): Add test for case when battery is not present
+	 */
+
+	/* See pe_give_battery_cap_entry() in common/usbc/usb_pe_drp_sm.c */
+
+	zassert_true(battery_is_present(), "Battery must be present");
+	zassert_true(IS_ENABLED(HAS_TASK_HOSTCMD) &&
+			     *host_get_memmap(EC_MEMMAP_BATTERY_VERSION) != 0,
+		     "Cannot access battery data");
+
+	/* Millivolts */
+	int design_volt = *(int *)host_get_memmap(EC_MEMMAP_BATT_DVLT);
+
+	/* Milliamphours */
+	int design_cap = *(int *)host_get_memmap(EC_MEMMAP_BATT_DCAP);
+	int full_cap = *(int *)host_get_memmap(EC_MEMMAP_BATT_LFCC);
+
+	/* Multiply millivolts by milliamphours and scale to deciwatthours
+	 * (0.1 Wh), the unit of energy used in the PD messages.
+	 */
+
+	int expected_design_cap =
+		DIV_ROUND_NEAREST((design_cap * design_volt), 1000 * 1000 / 10);
+
+	int expected_last_charge_cap =
+		DIV_ROUND_NEAREST((design_cap * full_cap), 1000 * 1000 / 10);
+
+	zassert_equal(expected_design_cap, bcdb->design_cap,
+		      "Design capacity not correct. Expected %d but got %d",
+		      expected_design_cap, bcdb->design_cap);
+	zassert_equal(
+		expected_last_charge_cap, bcdb->last_full_charge_cap,
+		"Last full charge capacity not correct. Expected %d but got %d",
+		expected_last_charge_cap, bcdb->last_full_charge_cap);
+}
+
+ZTEST_F(usb_attach_5v_3a_pd_source_rev3, test_batt_cap_invalid)
+{
+	/* Request data on a battery that does not exist. The PD stack only
+	 * supports battery 0.
+	 */
+
+	int battery_index = 5;
+
+	tcpci_partner_common_send_get_battery_capabilities(
+		&fixture->source_5v_3a, battery_index);
+
+	/* Allow some time for TCPC to process and respond */
+	k_sleep(K_SECONDS(1));
+
+	/* Ensure we get a response that says our battery index was invalid */
+
+	zassert_true(fixture->source_5v_3a.battery_capabilities
+			     .have_response[battery_index],
+		     "No battery capabilities response stored.");
+	zassert_true(
+		(fixture->source_5v_3a.battery_capabilities.bcdb[battery_index]
+			 .battery_type) &
+			BIT(0),
+		"Invalid battery ref bit should be set");
+}
+
+ZTEST_F(usb_attach_5v_3a_pd_source_rev3, test_verify_typec_status_using_rmdo)
+{
+	struct ec_params_typec_status params = { .port = TEST_PORT };
+	struct ec_response_typec_status response;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_TYPEC_STATUS, 0, response, params);
+
+	/* Check that the revision response in EC_CMD_TYPEC_STATUS matches
+	 * bits 16-31 of the partner's RMDO
+	 */
+	zassert_ok(host_command_process(&args));
+	zassert_equal(response.sop_revision, fixture->source_5v_3a.rmdo >> 16);
+}
+
+ZTEST_F(usb_attach_5v_3a_pd_source_rev3, test_verify_alert_msg)
+{
+	zassert_equal(pd_broadcast_alert_msg(ADO_OTP_EVENT), EC_SUCCESS);
+
+	k_sleep(K_SECONDS(2));
+	zassert_true(fixture->src_ext.alert_received);
+}
+
+ZTEST_F(usb_attach_5v_3a_pd_source_rev3,
+	test_verify_alert_on_power_state_change)
+{
+	/* Suspend and check partner received Alert and Status messages */
+	hook_notify(HOOK_CHIPSET_SUSPEND);
+	k_sleep(K_SECONDS(2));
+	zassert_true(fixture->src_ext.alert_received);
+	zassert_true(fixture->src_ext.status_received);
+	tcpci_src_emul_clear_alert_received(&fixture->src_ext);
+	tcpci_src_emul_clear_status_received(&fixture->src_ext);
+	zassert_false(fixture->src_ext.alert_received);
+	zassert_false(fixture->src_ext.status_received);
+
+	/* Shutdown and check partner received Alert and Status messages */
+	hook_notify(HOOK_CHIPSET_SHUTDOWN);
+	k_sleep(K_SECONDS(2));
+	zassert_true(fixture->src_ext.alert_received);
+	zassert_true(fixture->src_ext.status_received);
+	tcpci_src_emul_clear_alert_received(&fixture->src_ext);
+	tcpci_src_emul_clear_status_received(&fixture->src_ext);
+	zassert_false(fixture->src_ext.alert_received);
+	zassert_false(fixture->src_ext.status_received);
+
+	/* Startup and check partner received Alert and Status messages */
+	hook_notify(HOOK_CHIPSET_STARTUP);
+	k_sleep(K_SECONDS(2));
+	zassert_true(fixture->src_ext.alert_received);
+	zassert_true(fixture->src_ext.status_received);
+	tcpci_src_emul_clear_alert_received(&fixture->src_ext);
+	tcpci_src_emul_clear_status_received(&fixture->src_ext);
+	zassert_false(fixture->src_ext.alert_received);
+	zassert_false(fixture->src_ext.status_received);
+
+	/* Resume and check partner received Alert and Status messages */
+	hook_notify(HOOK_CHIPSET_RESUME);
+	k_sleep(K_SECONDS(2));
+	zassert_true(fixture->src_ext.alert_received);
+	zassert_true(fixture->src_ext.status_received);
+}
+
+ZTEST_F(usb_attach_5v_3a_pd_source_rev3,
+	test_verify_simultaneous_alert_status_resolution)
+{
+	zassert_false(fixture->src_ext.alert_received);
+	zassert_false(fixture->src_ext.status_received);
+
+	tcpci_partner_common_enable_pd_logging(&fixture->source_5v_3a, true);
+	zassert_equal(pd_broadcast_alert_msg(ADO_OTP_EVENT), EC_SUCCESS);
+	tcpci_partner_send_control_msg(&fixture->source_5v_3a,
+				       PD_CTRL_GET_STATUS, 0);
+	k_sleep(K_SECONDS(2));
+	tcpci_partner_common_enable_pd_logging(&fixture->source_5v_3a, false);
+
+	/*
+	 * The initial Alert message will be discarded, so the expected message
+	 * order is Get_Status->Status->Alert. This will be followed by another
+	 * Get_Status->Status transaction, but that is covered in other tests.
+	 * This test only checks the first 3 messages.
+	 */
+	int i = 0;
+	bool header_mismatch = false;
+	enum tcpci_partner_msg_sender expected_senders[3] = {
+		TCPCI_PARTNER_SENDER_PARTNER, TCPCI_PARTNER_SENDER_TCPM,
+		TCPCI_PARTNER_SENDER_TCPM
+	};
+	uint16_t expected_headers[3] = { 0x0012, 0xb002, 0x1006 };
+	struct tcpci_partner_log_msg *msg;
+
+	SYS_SLIST_FOR_EACH_CONTAINER(&fixture->source_5v_3a.msg_log, msg, node)
+	{
+		uint16_t header = sys_get_le16(msg->buf);
+
+		if (i >= 3)
+			break;
+
+		if (msg->sender != expected_senders[i] ||
+		    PD_HEADER_EXT(header) !=
+			    PD_HEADER_EXT(expected_headers[i]) ||
+		    PD_HEADER_CNT(header) !=
+			    PD_HEADER_CNT(expected_headers[i]) ||
+		    PD_HEADER_TYPE(header) !=
+			    PD_HEADER_TYPE(expected_headers[i])) {
+			header_mismatch = true;
+			break;
+		}
+
+		i++;
+	}
+
+	zassert_false(header_mismatch);
+	zassert_true(fixture->src_ext.alert_received);
+	zassert_true(fixture->src_ext.status_received);
+}
+
+ZTEST_F(usb_attach_5v_3a_pd_source_rev3,
+	test_verify_inaction_on_pd_button_press_while_awake)
+{
+	uint32_t ado;
+
+	/* While awake expect nothing on valid press */
+	ado = ADO_EXTENDED_ALERT_EVENT | ADO_POWER_BUTTON_PRESS;
+	tcpci_partner_send_data_msg(&fixture->source_5v_3a, PD_DATA_ALERT, &ado,
+				    1, 0);
+	k_sleep(K_SECONDS(2));
+	ado = ADO_EXTENDED_ALERT_EVENT | ADO_POWER_BUTTON_RELEASE;
+	tcpci_partner_send_data_msg(&fixture->source_5v_3a, PD_DATA_ALERT, &ado,
+				    1, 0);
+	k_sleep(K_SECONDS(2));
+	zassert_false(fixture->src_ext.alert_received);
+	zassert_false(fixture->src_ext.status_received);
+	zassert_true(chipset_in_state(CHIPSET_STATE_ON));
+}
+
+ZTEST_F(usb_attach_5v_3a_pd_source_rev3,
+	test_verify_inaction_on_invalid_pd_button_press)
+{
+	uint32_t ado;
+
+	/* Shutdown device to test wake from USB PD power button */
+	chipset_force_shutdown(CHIPSET_SHUTDOWN_BUTTON);
+	k_sleep(K_SECONDS(10));
+
+	/* Clear alert and status flags set during shutdown */
+	tcpci_src_emul_clear_alert_received(&fixture->src_ext);
+	tcpci_src_emul_clear_status_received(&fixture->src_ext);
+	zassert_false(fixture->src_ext.alert_received);
+	zassert_false(fixture->src_ext.status_received);
+	zassert_true(chipset_in_state(CHIPSET_STATE_ANY_OFF));
+
+	/* While in S5/G3 expect nothing on invalid (too long) press */
+	ado = ADO_EXTENDED_ALERT_EVENT | ADO_POWER_BUTTON_PRESS;
+	tcpci_partner_send_data_msg(&fixture->source_5v_3a, PD_DATA_ALERT, &ado,
+				    1, 0);
+	k_sleep(K_SECONDS(10));
+	ado = ADO_EXTENDED_ALERT_EVENT | ADO_POWER_BUTTON_RELEASE;
+	tcpci_partner_send_data_msg(&fixture->source_5v_3a, PD_DATA_ALERT, &ado,
+				    1, 0);
+	k_sleep(K_SECONDS(2));
+	zassert_false(fixture->src_ext.alert_received);
+	zassert_false(fixture->src_ext.status_received);
+	zassert_true(chipset_in_state(CHIPSET_STATE_ANY_OFF));
+
+	/* Wake device to setup for subsequent tests */
+	chipset_power_on();
+	k_sleep(K_SECONDS(10));
+}
+
+ZTEST_F(usb_attach_5v_3a_pd_source_rev3, test_verify_startup_on_pd_button_press)
+{
+	uint32_t ado;
+
+	/* Shutdown device to test wake from USB PD power button. Shutting down
+	 * the device may involve a Hard Reset upon entry to G3 (10 seconds
+	 * after S5). Wait long enough for that process to complete.
+	 */
+	chipset_force_shutdown(CHIPSET_SHUTDOWN_BUTTON);
+	k_sleep(K_SECONDS(15));
+
+	/* Clear alert and status flags set during shutdown */
+	tcpci_src_emul_clear_alert_received(&fixture->src_ext);
+	tcpci_src_emul_clear_status_received(&fixture->src_ext);
+	zassert_false(fixture->src_ext.alert_received);
+	zassert_false(fixture->src_ext.status_received);
+	zassert_true(chipset_in_state(CHIPSET_STATE_ANY_OFF));
+
+	/* While in S5/G3 expect Alert->Get_Status->Status on valid press */
+	ado = ADO_EXTENDED_ALERT_EVENT | ADO_POWER_BUTTON_PRESS;
+	tcpci_partner_send_data_msg(&fixture->source_5v_3a, PD_DATA_ALERT, &ado,
+				    1, 0);
+	k_sleep(K_SECONDS(2));
+	ado = ADO_EXTENDED_ALERT_EVENT | ADO_POWER_BUTTON_RELEASE;
+	tcpci_partner_send_data_msg(&fixture->source_5v_3a, PD_DATA_ALERT, &ado,
+				    1, 0);
+	k_sleep(K_SECONDS(2));
+	zassert_true(fixture->src_ext.alert_received);
+	zassert_true(fixture->src_ext.status_received);
+	zassert_true(chipset_in_state(CHIPSET_STATE_ON));
+}
+
+ZTEST_F(usb_attach_5v_3a_pd_source_rev3,
+	test_verify_chipset_on_pd_button_behavior)
+{
+	uint32_t ado;
+
+	/* Expect no power state change on short press */
+	ado = ADO_EXTENDED_ALERT_EVENT | ADO_POWER_BUTTON_PRESS;
+	tcpci_partner_send_data_msg(&fixture->source_5v_3a, PD_DATA_ALERT, &ado,
+				    1, 0);
+	k_sleep(K_SECONDS(2));
+	ado = ADO_EXTENDED_ALERT_EVENT | ADO_POWER_BUTTON_RELEASE;
+	tcpci_partner_send_data_msg(&fixture->source_5v_3a, PD_DATA_ALERT, &ado,
+				    1, 0);
+	k_sleep(K_SECONDS(2));
+	zassert_false(fixture->src_ext.alert_received);
+	zassert_false(fixture->src_ext.status_received);
+	zassert_true(chipset_in_state(CHIPSET_STATE_ON));
+
+	/* Expect no change on invalid button press while chipset is on */
+	ado = ADO_EXTENDED_ALERT_EVENT | ADO_POWER_BUTTON_PRESS;
+	tcpci_partner_send_data_msg(&fixture->source_5v_3a, PD_DATA_ALERT, &ado,
+				    1, 0);
+	k_sleep(K_SECONDS(10));
+	ado = ADO_EXTENDED_ALERT_EVENT | ADO_POWER_BUTTON_RELEASE;
+	tcpci_partner_send_data_msg(&fixture->source_5v_3a, PD_DATA_ALERT, &ado,
+				    1, 0);
+	k_sleep(K_SECONDS(2));
+	zassert_false(fixture->src_ext.alert_received);
+	zassert_false(fixture->src_ext.status_received);
+	zassert_true(chipset_in_state(CHIPSET_STATE_ON));
+
+	/*
+	 * Expect no power state change on 6 second press->press->release due
+	 * to the timers resetting on the second press.
+	 */
+	ado = ADO_EXTENDED_ALERT_EVENT | ADO_POWER_BUTTON_PRESS;
+	tcpci_partner_send_data_msg(&fixture->source_5v_3a, PD_DATA_ALERT, &ado,
+				    1, 0);
+	k_sleep(K_SECONDS(3));
+	tcpci_partner_send_data_msg(&fixture->source_5v_3a, PD_DATA_ALERT, &ado,
+				    1, 0);
+	k_sleep(K_SECONDS(3));
+	ado = ADO_EXTENDED_ALERT_EVENT | ADO_POWER_BUTTON_RELEASE;
+	tcpci_partner_send_data_msg(&fixture->source_5v_3a, PD_DATA_ALERT, &ado,
+				    1, 0);
+	k_sleep(K_SECONDS(2));
+	zassert_false(fixture->src_ext.alert_received);
+	zassert_false(fixture->src_ext.status_received);
+	zassert_true(chipset_in_state(CHIPSET_STATE_ON));
+
+	/* Expect power state change on long press */
+	ado = ADO_EXTENDED_ALERT_EVENT | ADO_POWER_BUTTON_PRESS;
+	tcpci_partner_send_data_msg(&fixture->source_5v_3a, PD_DATA_ALERT, &ado,
+				    1, 0);
+	k_sleep(K_SECONDS(6));
+	ado = ADO_EXTENDED_ALERT_EVENT | ADO_POWER_BUTTON_RELEASE;
+	tcpci_partner_send_data_msg(&fixture->source_5v_3a, PD_DATA_ALERT, &ado,
+				    1, 0);
+	k_sleep(K_SECONDS(2));
+	zassert_true(fixture->src_ext.alert_received);
+	zassert_true(fixture->src_ext.status_received);
+	zassert_true(chipset_in_state(CHIPSET_STATE_ANY_OFF));
+
+	/* Wake device to setup for subsequent tests */
+	chipset_power_on();
+	k_sleep(K_SECONDS(10));
+}
+
+ZTEST_F(usb_attach_5v_3a_pd_source_rev3, test_verify_uvdm_not_supported)
+{
+	uint32_t vdm_header = VDO(USB_VID_GOOGLE, 0 /* unstructured */, 0);
+
+	tcpci_partner_common_enable_pd_logging(&fixture->source_5v_3a, true);
+	tcpci_partner_send_data_msg(&fixture->source_5v_3a, PD_DATA_VENDOR_DEF,
+				    &vdm_header, 1, 0);
+	k_sleep(K_SECONDS(1));
+	tcpci_partner_common_enable_pd_logging(&fixture->source_5v_3a, false);
+
+	bool not_supported_seen = false;
+	struct tcpci_partner_log_msg *msg;
+
+	/* The TCPM does not support any unstructured VDMs. In PD 3.0, it should
+	 * respond with Not_Supported.
+	 */
+
+	SYS_SLIST_FOR_EACH_CONTAINER(&fixture->source_5v_3a.msg_log, msg, node)
+	{
+		uint16_t header = sys_get_le16(msg->buf);
+
+		/* Ignore messages from the port partner. */
+		if (msg->sender == TCPCI_PARTNER_SENDER_PARTNER) {
+			continue;
+		}
+
+		if (msg->sender == TCPCI_PARTNER_SENDER_TCPM &&
+		    PD_HEADER_GET_SOP(header) == TCPCI_MSG_SOP &&
+		    PD_HEADER_CNT(header) == 0 && PD_HEADER_EXT(header) == 0 &&
+		    PD_HEADER_TYPE(header) == PD_CTRL_NOT_SUPPORTED) {
+			not_supported_seen = true;
+			break;
+		}
+	}
+
+	zassert_true(
+		not_supported_seen,
+		"Sent unstructured VDM to TCPM; did not receive Not_Supported");
+}
diff --git a/zephyr/test/drivers/default/src/isl923x.c b/zephyr/test/drivers/default/src/isl923x.c
new file mode 100644
index 0000000000..8dbfdf530b
--- /dev/null
+++ b/zephyr/test/drivers/default/src/isl923x.c
@@ -0,0 +1,1088 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "battery_smart.h"
+#include "driver/charger/isl923x.h"
+#include "driver/charger/isl923x_public.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_isl923x.h"
+#include "system.h"
+#include "test/drivers/charger_utils.h"
+#include "test/drivers/test_mocks.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/fff.h>
+#include <zephyr/ztest.h>
+
+BUILD_ASSERT(CONFIG_CHARGER_SENSE_RESISTOR == 10 ||
+	     CONFIG_CHARGER_SENSE_RESISTOR == 5);
+
+BUILD_ASSERT(CONFIG_CHARGER_SENSE_RESISTOR_AC == 20 ||
+	     CONFIG_CHARGER_SENSE_RESISTOR_AC == 10);
+
+BUILD_ASSERT(IS_ENABLED(CONFIG_CHARGER_ISL9238),
+	     "Must test on ISL9238; ISL9237, ISL9238c, and RAA489000 are not"
+	     " yet supported");
+
+#if CONFIG_CHARGER_SENSE_RESISTOR == 10
+#define EXPECTED_CURRENT_MA(n) (n)
+#define EXPECTED_CURRENT_REG(n) (n)
+#else
+#define EXPECTED_CURRENT_MA(n) (n * 2)
+#define EXPECTED_CURRENT_REG(n) (n / 2)
+#endif
+
+#if CONFIG_CHARGER_SENSE_RESISTOR_AC == 20
+#define EXPECTED_INPUT_CURRENT_MA(n) (n)
+#define EXPECTED_INPUT_CURRENT_REG(n) (n)
+#else
+#define EXPECTED_INPUT_CURRENT_MA(n) (n * 2)
+#define EXPECTED_INPUT_CURRENT_REG(n) (n / 2)
+#endif
+
+#define CHARGER_NUM get_charger_num(&isl923x_drv)
+#define ISL923X_EMUL EMUL_DT_GET(DT_NODELABEL(isl923x_emul))
+#define COMMON_DATA emul_isl923x_get_i2c_common_data(ISL923X_EMUL)
+
+static int mock_write_fn_always_fail(const struct emul *emul, int reg,
+				     uint8_t val, int bytes, void *data)
+{
+	ztest_test_fail();
+	return 0;
+}
+
+ZTEST(isl923x, test_isl923x_set_current)
+{
+	int expected_current_milli_amps[] = {
+		EXPECTED_CURRENT_MA(0),	   EXPECTED_CURRENT_MA(4),
+		EXPECTED_CURRENT_MA(8),	   EXPECTED_CURRENT_MA(16),
+		EXPECTED_CURRENT_MA(32),   EXPECTED_CURRENT_MA(64),
+		EXPECTED_CURRENT_MA(128),  EXPECTED_CURRENT_MA(256),
+		EXPECTED_CURRENT_MA(512),  EXPECTED_CURRENT_MA(1024),
+		EXPECTED_CURRENT_MA(2048), EXPECTED_CURRENT_MA(4096)
+	};
+	int current_milli_amps;
+
+	/* Test I2C failure when reading charge current */
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, ISL923X_REG_CHG_CURRENT);
+	zassert_equal(EC_ERROR_INVAL,
+		      isl923x_drv.get_current(CHARGER_NUM, &current_milli_amps),
+		      NULL);
+
+	/* Reset fail register */
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	for (int i = 0; i < ARRAY_SIZE(expected_current_milli_amps); ++i) {
+		zassert_ok(isl923x_drv.set_current(
+				   CHARGER_NUM, expected_current_milli_amps[i]),
+			   "Failed to set the current to %dmA",
+			   expected_current_milli_amps[i]);
+		zassert_ok(isl923x_drv.get_current(CHARGER_NUM,
+						   &current_milli_amps),
+			   "Failed to get current");
+		zassert_equal(expected_current_milli_amps[i],
+			      current_milli_amps,
+			      "Expected current %dmA but got %dmA",
+			      expected_current_milli_amps[i],
+			      current_milli_amps);
+	}
+}
+
+ZTEST(isl923x, test_isl923x_set_voltage)
+{
+	int expected_voltage_milli_volts[] = { 8,    16,   32,	 64,
+					       128,  256,  512,	 1024,
+					       2048, 4096, 8192, 16384 };
+	int voltage_milli_volts;
+
+	/* Test 0mV first, it's a special case because of voltage_min */
+	zassert_ok(isl923x_drv.set_voltage(CHARGER_NUM, 0),
+		   "Failed to set the voltage to 0mV");
+	zassert_ok(isl923x_drv.get_voltage(CHARGER_NUM, &voltage_milli_volts),
+		   "Failed to get voltage");
+	zassert_equal(battery_get_info()->voltage_min, voltage_milli_volts,
+		      "Expected voltage %dmV but got %dmV",
+		      battery_get_info()->voltage_min, voltage_milli_volts);
+
+	for (int i = 0; i < ARRAY_SIZE(expected_voltage_milli_volts); ++i) {
+		zassert_ok(isl923x_drv.set_voltage(
+				   CHARGER_NUM,
+				   expected_voltage_milli_volts[i]),
+			   "Failed to set the voltage to %dmV",
+			   expected_voltage_milli_volts[i]);
+		zassert_ok(isl923x_drv.get_voltage(CHARGER_NUM,
+						   &voltage_milli_volts),
+			   "Failed to get voltage");
+		zassert_equal(expected_voltage_milli_volts[i],
+			      voltage_milli_volts,
+			      "Expected voltage %dmV but got %dmV",
+			      expected_voltage_milli_volts[i],
+			      voltage_milli_volts);
+	}
+}
+
+ZTEST(isl923x, test_isl923x_set_input_current_limit)
+{
+	int expected_current_milli_amps[] = { EXPECTED_INPUT_CURRENT_MA(0),
+					      EXPECTED_INPUT_CURRENT_MA(4),
+					      EXPECTED_INPUT_CURRENT_MA(8),
+					      EXPECTED_INPUT_CURRENT_MA(16),
+					      EXPECTED_INPUT_CURRENT_MA(32),
+					      EXPECTED_INPUT_CURRENT_MA(64),
+					      EXPECTED_INPUT_CURRENT_MA(128),
+					      EXPECTED_INPUT_CURRENT_MA(256),
+					      EXPECTED_INPUT_CURRENT_MA(512),
+					      EXPECTED_INPUT_CURRENT_MA(1024),
+					      EXPECTED_INPUT_CURRENT_MA(2048),
+					      EXPECTED_INPUT_CURRENT_MA(4096) };
+	int current_milli_amps;
+
+	/* Test failing to write to current limit 1 reg */
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA,
+					   ISL923X_REG_ADAPTER_CURRENT_LIMIT1);
+	zassert_equal(EC_ERROR_INVAL,
+		      isl923x_drv.set_input_current_limit(CHARGER_NUM, 0),
+		      NULL);
+
+	/* Test failing to write to current limit 2 reg */
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA,
+					   ISL923X_REG_ADAPTER_CURRENT_LIMIT2);
+	zassert_equal(EC_ERROR_INVAL,
+		      isl923x_drv.set_input_current_limit(CHARGER_NUM, 0),
+		      NULL);
+
+	/* Reset fail register */
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test failing to read current limit 1 reg */
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA,
+					  ISL923X_REG_ADAPTER_CURRENT_LIMIT1);
+	zassert_equal(EC_ERROR_INVAL,
+		      isl923x_drv.get_input_current_limit(CHARGER_NUM,
+							  &current_milli_amps),
+		      NULL);
+
+	/* Reset fail register */
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test normal code path */
+	for (int i = 0; i < ARRAY_SIZE(expected_current_milli_amps); ++i) {
+		zassert_ok(isl923x_drv.set_input_current_limit(
+				   CHARGER_NUM, expected_current_milli_amps[i]),
+			   "Failed to set input current limit to %dmV",
+			   expected_current_milli_amps[i]);
+		zassert_ok(isl923x_drv.get_input_current_limit(
+				   CHARGER_NUM, &current_milli_amps),
+			   "Failed to get input current limit");
+		zassert_equal(expected_current_milli_amps[i],
+			      current_milli_amps,
+			      "Expected input current %dmA but got %dmA",
+			      expected_current_milli_amps[i],
+			      current_milli_amps);
+	}
+}
+
+ZTEST(isl923x, test_isl923x_psys)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "psys"));
+}
+
+ZTEST(isl923x, test_manufacturer_id)
+{
+	const struct emul *isl923x_emul = ISL923X_EMUL;
+	int id;
+
+	isl923x_emul_set_manufacturer_id(isl923x_emul, 0x1234);
+	zassert_ok(isl923x_drv.manufacturer_id(CHARGER_NUM, &id));
+	zassert_equal(0x1234, id);
+
+	/* Test read error */
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA,
+					  ISL923X_REG_MANUFACTURER_ID);
+	zassert_equal(EC_ERROR_INVAL,
+		      isl923x_drv.manufacturer_id(CHARGER_NUM, &id), NULL);
+
+	/* Reset fail register */
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+}
+
+ZTEST(isl923x, test_device_id)
+{
+	const struct emul *isl923x_emul = ISL923X_EMUL;
+	int id;
+
+	isl923x_emul_set_device_id(isl923x_emul, 0x5678);
+	zassert_ok(isl923x_drv.device_id(CHARGER_NUM, &id));
+	zassert_equal(0x5678, id);
+
+	/* Test read error */
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, ISL923X_REG_DEVICE_ID);
+	zassert_equal(EC_ERROR_INVAL, isl923x_drv.device_id(CHARGER_NUM, &id),
+		      NULL);
+
+	/* Reset fail register */
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+}
+
+ZTEST(isl923x, test_options)
+{
+	uint32_t option;
+
+	/* Test failed control 0 read */
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, ISL923X_REG_CONTROL0);
+	zassert_equal(EC_ERROR_INVAL,
+		      isl923x_drv.get_option(CHARGER_NUM, &option), NULL);
+
+	/* Test failed control 1 read */
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, ISL923X_REG_CONTROL1);
+	zassert_equal(EC_ERROR_INVAL,
+		      isl923x_drv.get_option(CHARGER_NUM, &option), NULL);
+
+	/* Reset failed read */
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test failed control 0 write */
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA, ISL923X_REG_CONTROL0);
+	zassert_equal(EC_ERROR_INVAL,
+		      isl923x_drv.set_option(CHARGER_NUM, option), NULL);
+
+	/* Test failed control 1 write */
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA, ISL923X_REG_CONTROL1);
+	zassert_equal(EC_ERROR_INVAL,
+		      isl923x_drv.set_option(CHARGER_NUM, option), NULL);
+
+	/* Reset failed write */
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test normal write/read, note that bits 23 and 0 are always 0 */
+	zassert_ok(isl923x_drv.set_option(CHARGER_NUM, 0xffffffff));
+	zassert_ok(isl923x_drv.get_option(CHARGER_NUM, &option));
+	zassert_equal(0xff7ffffe, option,
+		      "Expected options 0xff7ffffe but got 0x%x", option);
+}
+
+ZTEST(isl923x, test_get_info)
+{
+	const struct charger_info *info = isl923x_drv.get_info(CHARGER_NUM);
+
+	zassert_ok(strcmp("isl9238", info->name));
+	zassert_equal(ISL9238_SYS_VOLTAGE_REG_MAX, info->voltage_max);
+	zassert_equal(ISL923X_SYS_VOLTAGE_REG_MIN, info->voltage_min);
+	zassert_equal(8, info->voltage_step);
+	zassert_equal(EXPECTED_CURRENT_MA(6080), info->current_max);
+	zassert_equal(EXPECTED_CURRENT_MA(4), info->current_min);
+	zassert_equal(EXPECTED_CURRENT_MA(4), info->current_step);
+	zassert_equal(EXPECTED_INPUT_CURRENT_MA(6080), info->input_current_max,
+		      NULL);
+	zassert_equal(EXPECTED_INPUT_CURRENT_MA(4), info->input_current_min,
+		      NULL);
+	zassert_equal(EXPECTED_INPUT_CURRENT_MA(4), info->input_current_step,
+		      NULL);
+}
+
+ZTEST(isl923x, test_status)
+{
+	int status;
+
+	zassert_ok(isl923x_drv.get_status(CHARGER_NUM, &status));
+	zassert_equal(CHARGER_LEVEL_2, status);
+}
+
+ZTEST(isl923x, test_set_mode)
+{
+	const struct emul *isl923x_emul = ISL923X_EMUL;
+
+	/* Enable learn mode and set mode (actual value doesn't matter) */
+	zassert_ok(isl923x_drv.discharge_on_ac(CHARGER_NUM, true));
+	zassert_ok(isl923x_drv.set_mode(CHARGER_NUM, 0));
+	/* Learn mode should still be set */
+	zassert_true(isl923x_emul_is_learn_mode_enabled(isl923x_emul));
+
+	/* Disable learn mode, but keep the bits */
+	zassert_ok(isl923x_drv.discharge_on_ac(CHARGER_NUM, false));
+	isl923x_emul_set_learn_mode_enabled(isl923x_emul, true);
+	zassert_ok(isl923x_drv.set_mode(CHARGER_NUM, 0));
+	/* Learn mode should still be off */
+	zassert_true(!isl923x_emul_is_learn_mode_enabled(isl923x_emul));
+}
+
+ZTEST(isl923x, test_post_init)
+{
+	zassert_ok(isl923x_drv.post_init(CHARGER_NUM));
+}
+
+ZTEST(isl923x, test_set_ac_prochot)
+{
+	const struct emul *isl923x_emul = ISL923X_EMUL;
+	const struct device *i2c_dev = isl923x_emul_get_parent(isl923x_emul);
+	uint16_t expected_current_milli_amps[] = {
+		EXPECTED_INPUT_CURRENT_MA(0),
+		EXPECTED_INPUT_CURRENT_MA(128),
+		EXPECTED_INPUT_CURRENT_MA(256),
+		EXPECTED_INPUT_CURRENT_MA(512),
+		EXPECTED_INPUT_CURRENT_MA(1024),
+		EXPECTED_INPUT_CURRENT_MA(2048),
+		EXPECTED_INPUT_CURRENT_MA(4096)
+	};
+	uint16_t current_milli_amps;
+
+	/* Test can't set current above max */
+	zassert_equal(EC_ERROR_INVAL,
+		      isl923x_set_ac_prochot(
+			      CHARGER_NUM, ISL923X_AC_PROCHOT_CURRENT_MAX + 1),
+		      NULL);
+
+	/* Test failed I2C write to prochot register */
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA, ISL923X_REG_PROCHOT_AC);
+	zassert_equal(EC_ERROR_INVAL, isl923x_set_ac_prochot(CHARGER_NUM, 0),
+		      NULL);
+
+	/* Clear write fail reg */
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	for (int i = 0; i < ARRAY_SIZE(expected_current_milli_amps); ++i) {
+		uint8_t reg_addr = ISL923X_REG_PROCHOT_AC;
+
+		/*
+		 * Due to resistor multiplying the current, the upper end of the
+		 * test data might be out of bounds (which is already tested
+		 * above). Skip the test.
+		 */
+		if (expected_current_milli_amps[i] >
+		    ISL923X_AC_PROCHOT_CURRENT_MAX) {
+			continue;
+		}
+
+		zassert_ok(isl923x_set_ac_prochot(
+				   CHARGER_NUM, expected_current_milli_amps[i]),
+			   "Failed to set AC prochot to %dmA",
+			   expected_current_milli_amps[i]);
+		zassert_ok(i2c_write_read(i2c_dev, isl923x_emul->bus.i2c->addr,
+					  &reg_addr, sizeof(reg_addr),
+					  &current_milli_amps,
+					  sizeof(current_milli_amps)),
+			   "Failed to read AC prochot register");
+		zassert_equal(EXPECTED_INPUT_CURRENT_REG(
+				      expected_current_milli_amps[i]),
+			      current_milli_amps,
+			      "AC prochot expected %dmA but got %dmA",
+			      EXPECTED_INPUT_CURRENT_REG(
+				      expected_current_milli_amps[i]),
+			      current_milli_amps);
+	}
+}
+ZTEST(isl923x, test_set_dc_prochot)
+{
+	const struct emul *isl923x_emul = ISL923X_EMUL;
+	const struct device *i2c_dev = isl923x_emul_get_parent(isl923x_emul);
+	uint16_t expected_current_milli_amps[] = {
+		EXPECTED_CURRENT_MA(256),  EXPECTED_CURRENT_MA(512),
+		EXPECTED_CURRENT_MA(1024), EXPECTED_CURRENT_MA(2048),
+		EXPECTED_CURRENT_MA(4096), EXPECTED_CURRENT_MA(8192)
+	};
+	uint16_t current_milli_amps;
+
+	/* Test can't set current above max */
+	zassert_equal(EC_ERROR_INVAL,
+		      isl923x_set_dc_prochot(
+			      CHARGER_NUM, ISL923X_DC_PROCHOT_CURRENT_MAX + 1),
+		      NULL);
+
+	/* Test failed I2C write to prochot register */
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA, ISL923X_REG_PROCHOT_DC);
+	zassert_equal(EC_ERROR_INVAL, isl923x_set_dc_prochot(CHARGER_NUM, 0),
+		      NULL);
+
+	/* Clear write fail reg */
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	for (int i = 0; i < ARRAY_SIZE(expected_current_milli_amps); ++i) {
+		uint8_t reg_addr = ISL923X_REG_PROCHOT_DC;
+
+		/*
+		 * Due to resistor multiplying the current, the upper end of the
+		 * test data might be out of bounds (which is already tested
+		 * above). Skip the test.
+		 */
+		if (expected_current_milli_amps[i] >
+		    ISL923X_DC_PROCHOT_CURRENT_MAX) {
+			continue;
+		}
+		zassert_ok(isl923x_set_dc_prochot(
+				   CHARGER_NUM, expected_current_milli_amps[i]),
+			   "Failed to set DC prochot to %dmA",
+			   expected_current_milli_amps[i]);
+		zassert_ok(i2c_write_read(i2c_dev, isl923x_emul->bus.i2c->addr,
+					  &reg_addr, sizeof(reg_addr),
+					  &current_milli_amps,
+					  sizeof(current_milli_amps)),
+			   "Failed to read DC prochot register");
+		zassert_equal(
+			EXPECTED_CURRENT_REG(expected_current_milli_amps[i]),
+			current_milli_amps,
+			"AC prochot expected %dmA but got %dmA",
+			EXPECTED_CURRENT_REG(expected_current_milli_amps[i]),
+			current_milli_amps);
+	}
+}
+
+ZTEST(isl923x, test_comparator_inversion)
+{
+	const struct emul *isl923x_emul = ISL923X_EMUL;
+	const struct device *i2c_dev = isl923x_emul_get_parent(isl923x_emul);
+	uint8_t reg_addr = ISL923X_REG_CONTROL2;
+	uint16_t reg_value;
+	uint8_t tx_buf[] = { reg_addr, 0, 0 };
+
+	/* Test failed read, should not write */
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, ISL923X_REG_CONTROL2);
+	i2c_common_emul_set_write_func(COMMON_DATA, mock_write_fn_always_fail,
+				       NULL);
+	zassert_equal(EC_ERROR_INVAL,
+		      isl923x_set_comparator_inversion(CHARGER_NUM, false),
+		      NULL);
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_func(COMMON_DATA, NULL, NULL);
+
+	/* Test failed write */
+	zassert_ok(i2c_write(i2c_dev, tx_buf, sizeof(tx_buf),
+			     isl923x_emul->bus.i2c->addr),
+		   "Failed to clear CTRL2 register");
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA, ISL923X_REG_CONTROL2);
+	zassert_equal(EC_ERROR_INVAL,
+		      isl923x_set_comparator_inversion(CHARGER_NUM, true),
+		      NULL);
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test enable comparator inversion */
+	zassert_ok(isl923x_set_comparator_inversion(CHARGER_NUM, true));
+	zassert_ok(i2c_write_read(i2c_dev, isl923x_emul->bus.i2c->addr,
+				  &reg_addr, sizeof(reg_addr), &reg_value,
+				  sizeof(reg_value)),
+		   "Failed to read CTRL 2 register");
+	zassert_true((reg_value & ISL923X_C2_INVERT_CMOUT) != 0);
+
+	/* Test disable comparator inversion */
+	zassert_ok(isl923x_set_comparator_inversion(CHARGER_NUM, false));
+	zassert_ok(i2c_write_read(i2c_dev, isl923x_emul->bus.i2c->addr,
+				  &reg_addr, sizeof(reg_addr), &reg_value,
+				  sizeof(reg_value)),
+		   "Failed to read CTRL 2 register");
+	zassert_true((reg_value & ISL923X_C2_INVERT_CMOUT) == 0);
+}
+
+ZTEST(isl923x, test_discharge_on_ac)
+{
+	const struct emul *isl923x_emul = ISL923X_EMUL;
+	const struct device *i2c_dev = isl923x_emul_get_parent(isl923x_emul);
+	const struct i2c_common_emul_cfg *cfg =
+		isl923x_emul_get_cfg(isl923x_emul);
+	uint8_t reg_addr = ISL923X_REG_CONTROL1;
+	uint8_t tx_buf[] = { reg_addr, 0, 0 };
+	uint16_t reg_value;
+
+	/* Test failure to read CTRL1 register */
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, ISL923X_REG_CONTROL1);
+	zassert_equal(EC_ERROR_INVAL,
+		      isl923x_drv.discharge_on_ac(CHARGER_NUM, true), NULL);
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Set CTRL1 register to 0 */
+	zassert_ok(i2c_write(i2c_dev, tx_buf, sizeof(tx_buf), cfg->addr));
+
+	/* Test failure to write CTRL1 register */
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA, ISL923X_REG_CONTROL1);
+	zassert_equal(EC_ERROR_INVAL,
+		      isl923x_drv.discharge_on_ac(CHARGER_NUM, true), NULL);
+	zassert_ok(i2c_write_read(i2c_dev, isl923x_emul->bus.i2c->addr,
+				  &reg_addr, sizeof(reg_addr), &reg_value,
+				  sizeof(reg_value)),
+		   NULL);
+	zassert_equal(0, reg_value);
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test enabling discharge on AC */
+	zassert_ok(isl923x_drv.discharge_on_ac(CHARGER_NUM, true));
+
+	zassert_ok(i2c_write_read(i2c_dev, isl923x_emul->bus.i2c->addr,
+				  &reg_addr, sizeof(reg_addr), &reg_value,
+				  sizeof(reg_value)),
+		   NULL);
+	zassert_true((reg_value & ISL923X_C1_LEARN_MODE_ENABLE) != 0);
+
+	/* Test disabling discharge on AC */
+	zassert_ok(isl923x_drv.discharge_on_ac(CHARGER_NUM, false));
+
+	zassert_ok(i2c_write_read(i2c_dev, isl923x_emul->bus.i2c->addr,
+				  &reg_addr, sizeof(reg_addr), &reg_value,
+				  sizeof(reg_value)),
+		   NULL);
+	zassert_true((reg_value & ISL923X_C1_LEARN_MODE_ENABLE) == 0);
+}
+
+ZTEST(isl923x, test_get_vbus_voltage)
+{
+	const struct emul *isl923x_emul = ISL923X_EMUL;
+	/* Standard fixed-power PD source voltages. */
+	int test_voltage_mv[] = { 5000, 9000, 15000, 20000 };
+	int voltage;
+
+	/* Test fail to read the ADC vbus register */
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, RAA489000_REG_ADC_VBUS);
+	zassert_equal(EC_ERROR_INVAL,
+		      isl923x_drv.get_vbus_voltage(CHARGER_NUM, 0, &voltage),
+		      NULL);
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	for (int i = 0; i < ARRAY_SIZE(test_voltage_mv); ++i) {
+		int expected_voltage_mv = test_voltage_mv[i];
+
+		isl923x_emul_set_adc_vbus(isl923x_emul, expected_voltage_mv);
+		zassert_ok(isl923x_drv.get_vbus_voltage(CHARGER_NUM, 0,
+							&voltage),
+			   NULL);
+		/* isl923x_get_vbus_voltage treats the measured voltage as
+		 * having an effective step size of 96 mV. This is slightly
+		 * different than the scheme described in the ISL9238 datasheet.
+		 * Reported VBUS should therefore be within 100 mV of nominal
+		 * VBUS.
+		 */
+		zassert_within(expected_voltage_mv, voltage, 100,
+			       "Expected %dmV but got %dmV",
+			       expected_voltage_mv, voltage);
+	}
+}
+
+ZTEST(isl923x, test_init)
+{
+	const struct emul *isl923x_emul = ISL923X_EMUL;
+	int input_current;
+
+	/* Test failed CTRL2 register read (prochot debounce) */
+	isl923x_emul_reset_registers(isl923x_emul);
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, ISL923X_REG_CONTROL2);
+	isl923x_drv.init(CHARGER_NUM);
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	zassert_ok(isl923x_drv.get_input_current_limit(CHARGER_NUM,
+						       &input_current),
+		   NULL);
+	zassert_equal(0, input_current,
+		      "Expected input current 0mA but got %dmA", input_current);
+
+	/* Test failed CTRL2 register write */
+	isl923x_emul_reset_registers(isl923x_emul);
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA, ISL923X_REG_CONTROL2);
+	isl923x_drv.init(CHARGER_NUM);
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+	zassert_ok(isl923x_drv.get_input_current_limit(CHARGER_NUM,
+						       &input_current),
+		   NULL);
+	zassert_equal(0, input_current,
+		      "Expected input current 0mA but got %dmA", input_current);
+
+	/* Test failed CTRL 0 read */
+	isl923x_emul_reset_registers(isl923x_emul);
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, ISL923X_REG_CONTROL0);
+	isl923x_drv.init(CHARGER_NUM);
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	zassert_ok(isl923x_drv.get_input_current_limit(CHARGER_NUM,
+						       &input_current),
+		   NULL);
+
+	zassert_equal(0, input_current,
+		      "Expected input current 0mA but got %dmA", input_current);
+
+	/* Test failed CTRL 0 write */
+	isl923x_emul_reset_registers(isl923x_emul);
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA, ISL923X_REG_CONTROL0);
+	isl923x_drv.init(CHARGER_NUM);
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+	zassert_ok(isl923x_drv.get_input_current_limit(CHARGER_NUM,
+						       &input_current),
+		   NULL);
+
+	zassert_equal(0, input_current,
+		      "Expected input current 0mA but got %dmA", input_current);
+
+	/* Test failed CTRL 3 read */
+	isl923x_emul_reset_registers(isl923x_emul);
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, ISL9238_REG_CONTROL3);
+	isl923x_drv.init(CHARGER_NUM);
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	zassert_ok(isl923x_drv.get_input_current_limit(CHARGER_NUM,
+						       &input_current),
+		   NULL);
+	zassert_equal(0, input_current,
+		      "Expected input current 0mA but got %dmA", input_current);
+
+	/* Test failed CTRL 3 write */
+	isl923x_emul_reset_registers(isl923x_emul);
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA, ISL9238_REG_CONTROL3);
+	isl923x_drv.init(CHARGER_NUM);
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+	zassert_ok(isl923x_drv.get_input_current_limit(CHARGER_NUM,
+						       &input_current),
+		   NULL);
+	zassert_equal(0, input_current,
+		      "Expected input current 0mA but got %dmA", input_current);
+
+	/* Test failed write adapter current limit */
+	isl923x_emul_reset_registers(isl923x_emul);
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA,
+					   ISL923X_REG_ADAPTER_CURRENT_LIMIT1);
+	isl923x_drv.init(CHARGER_NUM);
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+	zassert_ok(isl923x_drv.get_input_current_limit(CHARGER_NUM,
+						       &input_current),
+		   NULL);
+	zassert_equal(0, input_current,
+		      "Expected input current 0mA but got %dmA", input_current);
+}
+
+ZTEST(isl923x, test_init_late_jump)
+{
+	int input_current;
+
+	isl923x_drv.init(CHARGER_NUM);
+
+	/* Init again with system_jumped_late() returning true and make sure
+	 * the input current limit is still correct.
+	 */
+
+	system_jumped_late_fake.return_val = 1;
+	isl923x_drv.init(CHARGER_NUM);
+
+	zassert_equal(EC_SUCCESS,
+		      isl923x_drv.get_input_current_limit(CHARGER_NUM,
+							  &input_current),
+		      "Could not read input current limit.");
+	zassert_equal(CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT, input_current,
+		      "Input current (%d) not at (%d)", input_current,
+		      CONFIG_CHARGER_DEFAULT_CURRENT_LIMIT);
+}
+
+ZTEST(isl923x, test_isl923x_is_acok)
+{
+	const struct emul *isl923x_emul = ISL923X_EMUL;
+	enum ec_error_list rv;
+	bool acok;
+
+	/* Part 1: invalid charger number */
+	rv = raa489000_is_acok(board_get_charger_chip_count() + 1, &acok);
+	zassert_equal(EC_ERROR_INVAL, rv,
+		      "Invalid charger num, but AC OK check succeeded");
+
+	/* Part 2: error accessing register */
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, ISL9238_REG_INFO2);
+
+	rv = raa489000_is_acok(CHARGER_NUM, &acok);
+	zassert_equal(EC_ERROR_INVAL, rv,
+		      "Register read failure, but AC OK check succeeded");
+
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Part 3: successful path - ACOK is true */
+	raa489000_emul_set_acok_pin(isl923x_emul, 1);
+
+	rv = raa489000_is_acok(CHARGER_NUM, &acok);
+	zassert_equal(EC_SUCCESS, rv, "AC OK check did not return success");
+	zassert_true(acok, "AC OK is false");
+
+	/* Part 3: successful path - ACOK is false */
+	raa489000_emul_set_acok_pin(isl923x_emul, 0);
+
+	rv = raa489000_is_acok(CHARGER_NUM, &acok);
+	zassert_equal(EC_SUCCESS, rv, "AC OK check did not return success");
+	zassert_false(acok, "AC OK is true");
+
+	/*
+	 * Charger is sourcing - ACOK is always false,
+	 * even if the pin is asserted.
+	 */
+	raa489000_emul_set_acok_pin(isl923x_emul, 1);
+	raa489000_emul_set_state_machine_state(isl923x_emul,
+					       RAA489000_INFO2_STATE_OTG);
+
+	rv = raa489000_is_acok(CHARGER_NUM, &acok);
+	zassert_equal(EC_SUCCESS, rv, "AC OK check did not return success");
+	zassert_false(acok, "ACOK is true when sourcing, expected false");
+}
+
+ZTEST(isl923x, test_isl923x_enable_asgate)
+{
+	const struct emul *isl923x_emul = ISL923X_EMUL;
+	int rv;
+
+	/* Part 1: Try enabling the ASGATE */
+	rv = raa489000_enable_asgate(CHARGER_NUM, true);
+
+	zassert_equal(EC_SUCCESS, rv, "Expected return code of %d but got %d",
+		      EC_SUCCESS, rv);
+	zassert_true(
+		isl923x_emul_peek_reg(isl923x_emul, RAA489000_REG_CONTROL8) &
+			RAA489000_C8_ASGATE_ON_READY,
+		"RAA489000_C8_ASGATE_ON_READY bit not set in Control Reg 8");
+
+	/* Part 2: Turn it back off */
+	rv = raa489000_enable_asgate(CHARGER_NUM, false);
+
+	zassert_equal(EC_SUCCESS, rv, "Expected return code of %d but got %d",
+		      EC_SUCCESS, rv);
+	zassert_false(isl923x_emul_peek_reg(isl923x_emul,
+					    RAA489000_REG_CONTROL8) &
+			      RAA489000_C8_ASGATE_ON_READY,
+		      "RAA489000_C8_ASGATE_ON_READY bit set in Control Reg 8");
+}
+
+/* Mock read and write functions to use in the hibernation test */
+FAKE_VALUE_FUNC(int, hibernate_mock_read_fn, const struct emul *, int,
+		uint8_t *, int, void *);
+FAKE_VALUE_FUNC(int, hibernate_mock_write_fn, const struct emul *, int, uint8_t,
+		int, void *);
+
+/**
+ * @brief Setup function for the hibernate tests.
+ */
+static void isl923x_hibernate_before(void *state)
+{
+	ARG_UNUSED(state);
+
+	/* Reset mocks and make the read/write mocks pass all data through */
+	RESET_FAKE(hibernate_mock_read_fn);
+	RESET_FAKE(hibernate_mock_write_fn);
+	hibernate_mock_read_fn_fake.return_val = 1;
+	hibernate_mock_write_fn_fake.return_val = 1;
+
+	i2c_common_emul_set_read_func(COMMON_DATA, hibernate_mock_read_fn,
+				      NULL);
+	i2c_common_emul_set_write_func(COMMON_DATA, hibernate_mock_write_fn,
+				       NULL);
+
+	/* Don't fail on any register access */
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+}
+
+/**
+ * @brief Teardown function for the hibernate tests.
+ */
+static void isl923x_hibernate_after(void *state)
+{
+	ARG_UNUSED(state);
+
+	/* Clear the mock read/write functions */
+	i2c_common_emul_set_read_func(COMMON_DATA, NULL, NULL);
+	i2c_common_emul_set_write_func(COMMON_DATA, NULL, NULL);
+
+	/* Don't fail on any register access */
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+}
+
+ZTEST(isl923x_hibernate, test_isl923x_hibernate__happy_path)
+{
+	const struct emul *isl923x_emul = ISL923X_EMUL;
+	uint16_t actual;
+
+	raa489000_hibernate(CHARGER_NUM, false);
+
+	/* Check ISL923X_REG_CONTROL0 */
+	actual = isl923x_emul_peek_reg(isl923x_emul, ISL923X_REG_CONTROL0);
+
+	zassert_false(actual & RAA489000_C0_EN_CHG_PUMPS_TO_100PCT,
+		      "RAA489000_C0_EN_CHG_PUMPS_TO_100PCT should not be set");
+	zassert_false(actual & RAA489000_C0_BGATE_FORCE_ON,
+		      "RAA489000_C0_BGATE_FORCE_ON should not be set");
+
+	/* Check ISL923X_REG_CONTROL1 */
+	actual = isl923x_emul_peek_reg(isl923x_emul, ISL923X_REG_CONTROL1);
+
+	zassert_false(
+		actual & RAA489000_C1_ENABLE_SUPP_SUPPORT_MODE,
+		"RAA489000_C1_ENABLE_SUPP_SUPPORT_MODE should not be set");
+	zassert_false(actual & ISL923X_C1_ENABLE_PSYS,
+		      "ISL923X_C1_ENABLE_PSYS should not be set");
+	zassert_true(actual & RAA489000_C1_BGATE_FORCE_OFF,
+		     "RAA489000_C1_BGATE_FORCE_OFF should be set");
+	zassert_true(actual & ISL923X_C1_DISABLE_MON,
+		     "ISL923X_C1_DISABLE_MON should be set");
+
+	/* Check ISL9238_REG_CONTROL3 (disable_adc = false) */
+	actual = isl923x_emul_peek_reg(isl923x_emul, ISL9238_REG_CONTROL3);
+
+	zassert_true(actual & RAA489000_ENABLE_ADC,
+		     "RAA489000_ENABLE_ADC should be set");
+
+	/* Check ISL9238_REG_CONTROL4 */
+	actual = isl923x_emul_peek_reg(isl923x_emul, ISL9238_REG_CONTROL4);
+
+	zassert_true(actual & RAA489000_C4_DISABLE_GP_CMP,
+		     "RAA489000_C4_DISABLE_GP_CMP should be set");
+
+	/* Ensure all expected register reads and writes happened */
+	int registers[] = { ISL923X_REG_CONTROL0, ISL923X_REG_CONTROL1,
+			    ISL9238_REG_CONTROL3, ISL9238_REG_CONTROL4 };
+
+	for (int i = 0; i < ARRAY_SIZE(registers); i++) {
+		/* Each reg has 2 reads and 2 writes because they are 16-bit */
+		MOCK_ASSERT_I2C_READ(hibernate_mock_read_fn, i * 2,
+				     registers[i]);
+		MOCK_ASSERT_I2C_READ(hibernate_mock_read_fn, (i * 2) + 1,
+				     registers[i]);
+		MOCK_ASSERT_I2C_WRITE(hibernate_mock_write_fn, i * 2,
+				      registers[i], MOCK_IGNORE_VALUE);
+		MOCK_ASSERT_I2C_WRITE(hibernate_mock_write_fn, (i * 2) + 1,
+				      registers[i], MOCK_IGNORE_VALUE);
+	}
+}
+
+ZTEST(isl923x_hibernate, test_isl923x_hibernate__invalid_charger_number)
+{
+	/* Mocks should just be pass-through */
+	RESET_FAKE(hibernate_mock_read_fn);
+	RESET_FAKE(hibernate_mock_write_fn);
+	hibernate_mock_read_fn_fake.return_val = 1;
+	hibernate_mock_write_fn_fake.return_val = 1;
+
+	raa489000_hibernate(board_get_charger_chip_count() + 1, false);
+
+	/* Make sure no I2C activity happened */
+	zassert_equal(hibernate_mock_read_fn_fake.call_count, 0,
+		      "No I2C reads should have happened");
+	zassert_equal(hibernate_mock_write_fn_fake.call_count, 0,
+		      "No I2C writes should have happened");
+}
+
+ZTEST(isl923x_hibernate, test_isl923x_hibernate__fail_at_ISL923X_REG_CONTROL0)
+{
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, ISL923X_REG_CONTROL0);
+
+	raa489000_hibernate(CHARGER_NUM, false);
+
+	/*
+	 * We have no return codes to check, so instead verify that the first
+	 * successful I2C write is to CONTROL1 and not CONTROL0.
+	 */
+
+	MOCK_ASSERT_I2C_WRITE(hibernate_mock_write_fn, 0, ISL923X_REG_CONTROL1,
+			      MOCK_IGNORE_VALUE);
+}
+
+ZTEST(isl923x_hibernate, test_isl923x_hibernate__fail_at_ISL923X_REG_CONTROL1)
+{
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, ISL923X_REG_CONTROL1);
+
+	raa489000_hibernate(CHARGER_NUM, false);
+
+	/*
+	 * Ensure we skipped CONTROL1. (NB: due to 16-bit regs, each write takes
+	 * two calls to the mock_write_fn)
+	 */
+
+	MOCK_ASSERT_I2C_WRITE(hibernate_mock_write_fn, 0, ISL923X_REG_CONTROL0,
+			      MOCK_IGNORE_VALUE);
+	MOCK_ASSERT_I2C_WRITE(hibernate_mock_write_fn, 1, ISL923X_REG_CONTROL0,
+			      MOCK_IGNORE_VALUE);
+	MOCK_ASSERT_I2C_WRITE(hibernate_mock_write_fn, 2, ISL9238_REG_CONTROL3,
+			      MOCK_IGNORE_VALUE);
+	MOCK_ASSERT_I2C_WRITE(hibernate_mock_write_fn, 3, ISL9238_REG_CONTROL3,
+			      MOCK_IGNORE_VALUE);
+}
+
+ZTEST(isl923x_hibernate, test_isl923x_hibernate__fail_at_ISL9238_REG_CONTROL3)
+{
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, ISL9238_REG_CONTROL3);
+
+	raa489000_hibernate(CHARGER_NUM, false);
+
+	/*
+	 * Ensure we skipped CONTROL3. (NB: due to 16-bit regs, each write takes
+	 * two calls to the mock_write_fn)
+	 */
+
+	MOCK_ASSERT_I2C_WRITE(hibernate_mock_write_fn, 2, ISL923X_REG_CONTROL1,
+			      MOCK_IGNORE_VALUE);
+	MOCK_ASSERT_I2C_WRITE(hibernate_mock_write_fn, 3, ISL923X_REG_CONTROL1,
+			      MOCK_IGNORE_VALUE);
+	MOCK_ASSERT_I2C_WRITE(hibernate_mock_write_fn, 4, ISL9238_REG_CONTROL4,
+			      MOCK_IGNORE_VALUE);
+	MOCK_ASSERT_I2C_WRITE(hibernate_mock_write_fn, 5, ISL9238_REG_CONTROL4,
+			      MOCK_IGNORE_VALUE);
+}
+
+ZTEST(isl923x_hibernate, test_isl923x_hibernate__fail_at_ISL9238_REG_CONTROL4)
+{
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, ISL9238_REG_CONTROL4);
+
+	raa489000_hibernate(CHARGER_NUM, false);
+
+	/*
+	 * Ensure we skipped CONTROL4. (i.e. the last calls should be to write
+	 * to CONTROL3)
+	 */
+	MOCK_ASSERT_I2C_WRITE(hibernate_mock_write_fn,
+			      hibernate_mock_write_fn_fake.call_count - 2,
+			      ISL9238_REG_CONTROL3, MOCK_IGNORE_VALUE);
+	MOCK_ASSERT_I2C_WRITE(hibernate_mock_write_fn,
+			      hibernate_mock_write_fn_fake.call_count - 1,
+			      ISL9238_REG_CONTROL3, MOCK_IGNORE_VALUE);
+}
+
+ZTEST(isl923x_hibernate, test_isl923x_hibernate__adc_disable)
+{
+	const struct emul *isl923x_emul = ISL923X_EMUL;
+	uint16_t expected;
+
+	raa489000_hibernate(CHARGER_NUM, true);
+
+	/* Check ISL9238_REG_CONTROL3 (disable_adc = true) */
+	expected = isl923x_emul_peek_reg(isl923x_emul, ISL9238_REG_CONTROL3);
+	expected &= ~RAA489000_ENABLE_ADC;
+
+	MOCK_ASSERT_I2C_READ(hibernate_mock_read_fn, 4, ISL9238_REG_CONTROL3);
+	MOCK_ASSERT_I2C_READ(hibernate_mock_read_fn, 5, ISL9238_REG_CONTROL3);
+	MOCK_ASSERT_I2C_WRITE(hibernate_mock_write_fn, 4, ISL9238_REG_CONTROL3,
+			      expected & 0xff);
+	MOCK_ASSERT_I2C_WRITE(hibernate_mock_write_fn, 5, ISL9238_REG_CONTROL3,
+			      expected >> 8);
+}
+
+ZTEST(isl923x_hibernate, test_isl9238c_hibernate)
+{
+	const struct emul *isl923x_emul = ISL923X_EMUL;
+	uint16_t control1_expected, control2_expected, control3_expected;
+	int rv;
+
+	/* Part 1: Happy path */
+	control1_expected =
+		(isl923x_emul_peek_reg(isl923x_emul, ISL923X_REG_CONTROL1) &
+		 ~ISL923X_C1_ENABLE_PSYS) |
+		ISL923X_C1_DISABLE_MON;
+	control2_expected =
+		isl923x_emul_peek_reg(isl923x_emul, ISL923X_REG_CONTROL2) |
+		ISL923X_C2_COMPARATOR;
+	control3_expected =
+		isl923x_emul_peek_reg(isl923x_emul, ISL9238_REG_CONTROL3) |
+		ISL9238_C3_BGATE_OFF;
+
+	rv = isl9238c_hibernate(CHARGER_NUM);
+
+	zassert_equal(EC_SUCCESS, rv, "Expected return code %d but got %d",
+		      EC_SUCCESS, rv);
+	zassert_equal(isl923x_emul_peek_reg(isl923x_emul, ISL923X_REG_CONTROL1),
+		      control1_expected,
+		      "Unexpected register value 0x%02x. Should be 0x%02x",
+		      isl923x_emul_peek_reg(isl923x_emul, ISL923X_REG_CONTROL1),
+		      control1_expected);
+	zassert_equal(isl923x_emul_peek_reg(isl923x_emul, ISL923X_REG_CONTROL2),
+		      control2_expected,
+		      "Unexpected register value 0x%02x. Should be 0x%02x",
+		      isl923x_emul_peek_reg(isl923x_emul, ISL923X_REG_CONTROL2),
+		      control2_expected);
+	zassert_equal(isl923x_emul_peek_reg(isl923x_emul, ISL9238_REG_CONTROL3),
+		      control3_expected,
+		      "Unexpected register value 0x%02x. Should be 0x%02x",
+		      isl923x_emul_peek_reg(isl923x_emul, ISL9238_REG_CONTROL3),
+		      control3_expected);
+
+	/* Part 2: Fail reading each register and check for error code */
+	int registers[] = { ISL923X_REG_CONTROL1, ISL923X_REG_CONTROL2,
+			    ISL9238_REG_CONTROL3 };
+
+	for (int i = 0; i < ARRAY_SIZE(registers); i++) {
+		i2c_common_emul_set_read_fail_reg(COMMON_DATA, registers[i]);
+
+		rv = isl9238c_hibernate(CHARGER_NUM);
+
+		zassert_equal(EC_ERROR_INVAL, rv,
+			      "Wrong return code. Expected %d but got %d",
+			      EC_ERROR_INVAL, rv);
+	}
+}
+
+ZTEST(isl923x_hibernate, test_isl9238c_resume)
+{
+	const struct emul *isl923x_emul = ISL923X_EMUL;
+	uint16_t control1_expected, control2_expected, control3_expected;
+	int rv;
+
+	/* Part 1: Happy path */
+	control1_expected =
+		isl923x_emul_peek_reg(isl923x_emul, ISL923X_REG_CONTROL1) |
+		ISL923X_C1_ENABLE_PSYS;
+	control2_expected =
+		isl923x_emul_peek_reg(isl923x_emul, ISL923X_REG_CONTROL2) &
+		~ISL923X_C2_COMPARATOR;
+	control3_expected =
+		isl923x_emul_peek_reg(isl923x_emul, ISL9238_REG_CONTROL3) &
+		~ISL9238_C3_BGATE_OFF;
+
+	rv = isl9238c_resume(CHARGER_NUM);
+
+	zassert_equal(EC_SUCCESS, rv, "Expected return code %d but got %d",
+		      EC_SUCCESS, rv);
+	zassert_equal(isl923x_emul_peek_reg(isl923x_emul, ISL923X_REG_CONTROL1),
+		      control1_expected,
+		      "Unexpected register value 0x%02x. Should be 0x%02x",
+		      isl923x_emul_peek_reg(isl923x_emul, ISL923X_REG_CONTROL1),
+		      control1_expected);
+	zassert_equal(isl923x_emul_peek_reg(isl923x_emul, ISL923X_REG_CONTROL2),
+		      control2_expected,
+		      "Unexpected register value 0x%02x. Should be 0x%02x",
+		      isl923x_emul_peek_reg(isl923x_emul, ISL923X_REG_CONTROL2),
+		      control2_expected);
+	zassert_equal(isl923x_emul_peek_reg(isl923x_emul, ISL9238_REG_CONTROL3),
+		      control3_expected,
+		      "Unexpected register value 0x%02x. Should be 0x%02x",
+		      isl923x_emul_peek_reg(isl923x_emul, ISL9238_REG_CONTROL3),
+		      control3_expected);
+
+	/* Part 2: Fail reading each register and check for error code */
+	int registers[] = { ISL923X_REG_CONTROL1, ISL923X_REG_CONTROL2,
+			    ISL9238_REG_CONTROL3 };
+
+	for (int i = 0; i < ARRAY_SIZE(registers); i++) {
+		i2c_common_emul_set_read_fail_reg(COMMON_DATA, registers[i]);
+
+		rv = isl9238c_resume(CHARGER_NUM);
+
+		zassert_equal(EC_ERROR_INVAL, rv,
+			      "Wrong return code. Expected %d but got %d",
+			      EC_ERROR_INVAL, rv);
+	}
+}
+
+ZTEST_SUITE(isl923x, drivers_predicate_pre_main, NULL, NULL, NULL, NULL);
+
+ZTEST_SUITE(isl923x_hibernate, drivers_predicate_post_main, NULL,
+	    isl923x_hibernate_before, isl923x_hibernate_after, NULL);
diff --git a/zephyr/test/drivers/default/src/led.c b/zephyr/test/drivers/default/src/led.c
new file mode 100644
index 0000000000..3f727599b4
--- /dev/null
+++ b/zephyr/test/drivers/default/src/led.c
@@ -0,0 +1,91 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+#include "led.h"
+#include "led_common.h"
+#include "pwm_mock.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/pwm.h>
+#include <zephyr/ztest.h>
+#include <zephyr/ztest_assert.h>
+
+ZTEST_SUITE(pwm_led_driver, drivers_predicate_post_main, NULL, NULL, NULL,
+	    NULL);
+
+ZTEST(pwm_led_driver, test_led_set_brightness)
+{
+	const uint8_t brightness_off[EC_LED_COLOR_COUNT] = {};
+	const uint8_t brightness_white[EC_LED_COLOR_COUNT] = {
+		[EC_LED_COLOR_WHITE] = 1
+	};
+	const uint8_t brightness_amber[EC_LED_COLOR_COUNT] = {
+		[EC_LED_COLOR_AMBER] = 1
+	};
+	const struct device *pwm_blue_left =
+		DEVICE_DT_GET(DT_NODELABEL(pwm_blue_left));
+	const struct device *pwm_white_left =
+		DEVICE_DT_GET(DT_NODELABEL(pwm_white_left));
+	const struct device *pwm_amber_right =
+		DEVICE_DT_GET(DT_NODELABEL(pwm_amber_right));
+	const struct device *pwm_white_right =
+		DEVICE_DT_GET(DT_NODELABEL(pwm_white_right));
+
+	/* Turn off all LEDs */
+	led_set_brightness(EC_LED_ID_LEFT_LED, brightness_off);
+	led_set_brightness(EC_LED_ID_RIGHT_LED, brightness_off);
+	zassert_equal(pwm_mock_get_duty(pwm_blue_left, 0), 0, NULL);
+	zassert_equal(pwm_mock_get_duty(pwm_white_left, 0), 0, NULL);
+	zassert_equal(pwm_mock_get_duty(pwm_amber_right, 0), 0, NULL);
+	zassert_equal(pwm_mock_get_duty(pwm_white_right, 0), 0, NULL);
+
+	/* Call led_set_color(LED_WHITE, LEFT_LED) */
+	led_set_brightness(EC_LED_ID_LEFT_LED, brightness_white);
+	zassert_equal(pwm_mock_get_duty(pwm_blue_left, 0), 0, NULL);
+	zassert_equal(pwm_mock_get_duty(pwm_white_left, 0), 100, NULL);
+	zassert_equal(pwm_mock_get_duty(pwm_amber_right, 0), 0, NULL);
+	zassert_equal(pwm_mock_get_duty(pwm_white_right, 0), 0, NULL);
+
+	/* Unsupporte, call led_set_color(LED_OFF, LEFT_LED) */
+	led_set_brightness(EC_LED_ID_LEFT_LED, brightness_amber);
+	zassert_equal(pwm_mock_get_duty(pwm_blue_left, 0), 0, NULL);
+	zassert_equal(pwm_mock_get_duty(pwm_white_left, 0), 0, NULL);
+	zassert_equal(pwm_mock_get_duty(pwm_amber_right, 0), 0, NULL);
+	zassert_equal(pwm_mock_get_duty(pwm_white_right, 0), 0, NULL);
+
+	/* Call led_set_color(AMBER, RIGHT_LED) */
+	led_set_brightness(EC_LED_ID_RIGHT_LED, brightness_amber);
+	zassert_equal(pwm_mock_get_duty(pwm_blue_left, 0), 0, NULL);
+	zassert_equal(pwm_mock_get_duty(pwm_white_left, 0), 0, NULL);
+	zassert_equal(pwm_mock_get_duty(pwm_amber_right, 0), 100, NULL);
+	zassert_equal(pwm_mock_get_duty(pwm_white_right, 0), 0, NULL);
+}
+
+ZTEST(pwm_led_driver, test_led_get_brightness)
+{
+	uint8_t brightness[EC_LED_COLOR_COUNT];
+	const uint8_t expected_left[EC_LED_COLOR_COUNT] = {
+		[EC_LED_COLOR_BLUE] = 100,
+		[EC_LED_COLOR_WHITE] = 100,
+	};
+	const uint8_t expected_right[EC_LED_COLOR_COUNT] = {
+		[EC_LED_COLOR_WHITE] = 100,
+		[EC_LED_COLOR_AMBER] = 100,
+	};
+
+	/* Verify LED colors defined in device tree are reflected in the
+	 * brightness array.
+	 */
+	memset(brightness, 255, sizeof(brightness));
+	led_get_brightness_range(EC_LED_ID_LEFT_LED, brightness);
+	zassert_mem_equal(brightness, expected_left, sizeof(brightness), NULL);
+
+	memset(brightness, 255, sizeof(brightness));
+	led_get_brightness_range(EC_LED_ID_RIGHT_LED, brightness);
+	zassert_mem_equal(brightness, expected_right, sizeof(brightness), NULL);
+}
diff --git a/zephyr/test/drivers/default/src/lid_angle.c b/zephyr/test/drivers/default/src/lid_angle.c
new file mode 100644
index 0000000000..3611e176d4
--- /dev/null
+++ b/zephyr/test/drivers/default/src/lid_angle.c
@@ -0,0 +1,70 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+#include "lid_angle.h"
+#include "test/drivers/test_mocks.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/ztest.h>
+
+#define LID_ANGLE_MIN_LARGE_ANGLE 0
+#define LID_ANGLE_MAX_LARGE_ANGLE 360
+
+static void lid_angle_after(void *f)
+{
+	ARG_UNUSED(f);
+	/* Reset the wake angle */
+	lid_angle_set_wake_angle(180);
+	/* Flush the buffer */
+	lid_angle_update(LID_ANGLE_UNRELIABLE);
+	lid_angle_update(LID_ANGLE_UNRELIABLE);
+	lid_angle_update(LID_ANGLE_UNRELIABLE);
+	lid_angle_update(LID_ANGLE_UNRELIABLE);
+}
+
+ZTEST_SUITE(lid_angle, drivers_predicate_post_main, NULL, NULL, lid_angle_after,
+	    NULL);
+
+ZTEST(lid_angle, test_get_set_wake_angle)
+{
+	lid_angle_set_wake_angle(LID_ANGLE_MIN_LARGE_ANGLE - 1);
+	zassert_equal(LID_ANGLE_MIN_LARGE_ANGLE, lid_angle_get_wake_angle(),
+		      NULL);
+
+	lid_angle_set_wake_angle(LID_ANGLE_MAX_LARGE_ANGLE + 1);
+	zassert_equal(LID_ANGLE_MAX_LARGE_ANGLE, lid_angle_get_wake_angle(),
+		      NULL);
+
+	lid_angle_set_wake_angle(
+		(LID_ANGLE_MIN_LARGE_ANGLE + LID_ANGLE_MAX_LARGE_ANGLE) / 2);
+	zassert_equal((LID_ANGLE_MIN_LARGE_ANGLE + LID_ANGLE_MAX_LARGE_ANGLE) /
+			      2,
+		      lid_angle_get_wake_angle(), NULL);
+}
+
+ZTEST(lid_angle, test_no_wake_min_large_angle)
+{
+	lid_angle_set_wake_angle(LID_ANGLE_MIN_LARGE_ANGLE);
+	lid_angle_update(45);
+	lid_angle_update(45);
+	lid_angle_update(45);
+	lid_angle_update(45);
+
+	zassert_equal(1, lid_angle_peripheral_enable_fake.call_count, NULL);
+	zassert_equal(0, lid_angle_peripheral_enable_fake.arg0_val, NULL);
+}
+
+ZTEST(lid_angle, test_wake_max_large_angle)
+{
+	lid_angle_set_wake_angle(LID_ANGLE_MAX_LARGE_ANGLE);
+	lid_angle_update(45);
+	lid_angle_update(45);
+	lid_angle_update(45);
+	lid_angle_update(45);
+
+	zassert_equal(1, lid_angle_peripheral_enable_fake.call_count, NULL);
+	zassert_equal(1, lid_angle_peripheral_enable_fake.arg0_val, NULL);
+}
diff --git a/zephyr/test/drivers/default/src/lid_switch.c b/zephyr/test/drivers/default/src/lid_switch.c
new file mode 100644
index 0000000000..f71e590d62
--- /dev/null
+++ b/zephyr/test/drivers/default/src/lid_switch.c
@@ -0,0 +1,297 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+#include "host_command.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/shell/shell_dummy.h>
+#include <zephyr/ztest.h>
+
+#include <console.h>
+#include <lid_switch.h>
+
+#define LID_GPIO_PATH NAMED_GPIOS_GPIO_NODE(lid_open_ec)
+#define LID_GPIO_PIN DT_GPIO_PIN(LID_GPIO_PATH, gpios)
+
+int emul_lid_open(void)
+{
+	const struct device *lid_gpio_dev =
+		DEVICE_DT_GET(DT_GPIO_CTLR(LID_GPIO_PATH, gpios));
+
+	return gpio_emul_input_set(lid_gpio_dev, LID_GPIO_PIN, 1);
+}
+
+int emul_lid_close(void)
+{
+	const struct device *lid_gpio_dev =
+		DEVICE_DT_GET(DT_GPIO_CTLR(LID_GPIO_PATH, gpios));
+
+	return gpio_emul_input_set(lid_gpio_dev, LID_GPIO_PIN, 0);
+}
+
+static void *lid_switch_setup(void)
+{
+	/**
+	 * Set chipset to S0 as chipset power on after opening lid may disturb
+	 * test
+	 */
+	test_set_chipset_to_s0();
+
+	return NULL;
+}
+
+static void lid_switch_before(void *unused)
+{
+	/* Make sure that interrupt fire at the next lid open/close */
+	zassert_ok(emul_lid_close());
+	zassert_ok(emul_lid_open());
+	k_sleep(K_MSEC(100));
+}
+
+static void lid_switch_after(void *unused)
+{
+	struct ec_params_force_lid_open params = {
+		.enabled = 0,
+	};
+	int res;
+
+	res = ec_cmd_force_lid_open(NULL, &params);
+	if (res)
+		TC_ERROR("host_command_process() failed (%d)\n", res);
+
+	res = emul_lid_open();
+	if (res)
+		TC_ERROR("emul_lid_open() failed (%d)\n", res);
+	k_sleep(K_MSEC(100));
+}
+
+ZTEST(lid_switch, test_lid_open)
+{
+	/* Start closed. */
+	zassert_ok(emul_lid_close());
+	k_sleep(K_MSEC(100));
+	zassert_equal(lid_is_open(), 0);
+
+	zassert_ok(emul_lid_open());
+	k_sleep(K_MSEC(100));
+	zassert_equal(lid_is_open(), 1);
+}
+
+ZTEST(lid_switch, test_lid_debounce)
+{
+	/* Start closed. */
+	zassert_ok(emul_lid_close());
+	k_sleep(K_MSEC(100));
+	zassert_equal(lid_is_open(), 0);
+
+	/* Create interrupts quickly before they can be handled. */
+	zassert_ok(emul_lid_open());
+	zassert_ok(emul_lid_close());
+	zassert_ok(emul_lid_open());
+	k_sleep(K_MSEC(100));
+	zassert_equal(lid_is_open(), 1);
+}
+
+ZTEST(lid_switch, test_lid_close)
+{
+	/* Start open. */
+	zassert_ok(emul_lid_open());
+	k_sleep(K_MSEC(100));
+
+	zassert_ok(emul_lid_close());
+	k_sleep(K_MSEC(200));
+	zassert_equal(lid_is_open(), 0);
+}
+
+ZTEST(lid_switch, test_enable_lid_detect)
+{
+	/* Start open. */
+	zassert_ok(emul_lid_open(), NULL);
+	k_sleep(K_MSEC(500));
+	zassert_equal(lid_is_open(), 1, NULL);
+
+	/* Disable lid detect interrupts */
+	enable_lid_detect(false);
+	k_sleep(K_MSEC(100));
+
+	/* Close lid but check if still indicates open as interrupt is
+	 * disabled
+	 */
+	zassert_ok(emul_lid_close(), NULL);
+	k_sleep(K_MSEC(100));
+	zassert_equal(lid_is_open(), 1, NULL);
+	zassert_ok(emul_lid_open(), NULL);
+	k_sleep(K_MSEC(100));
+
+	/* Restore lid detect interrupts, confirm interrupt is firing again */
+	enable_lid_detect(true);
+	zassert_ok(emul_lid_close(), NULL);
+	k_sleep(K_MSEC(100));
+	zassert_equal(lid_is_open(), 0, NULL);
+}
+
+ZTEST(lid_switch, test_cmd_lidopen)
+{
+	/* Start closed. */
+	zassert_ok(emul_lid_close());
+	k_sleep(K_MSEC(100));
+	zassert_equal(lid_is_open(), 0);
+
+	/* Forced override lid open. */
+	zassert_equal(EC_SUCCESS, shell_execute_cmd(get_ec_shell(), "lidopen"),
+		      NULL);
+	zassert_equal(lid_is_open(), 1);
+	k_sleep(K_MSEC(100));
+
+	printk("GPIO lid open/close\n");
+	/* Open & close with gpio. */
+	zassert_ok(emul_lid_open());
+	zassert_ok(emul_lid_close());
+	k_sleep(K_MSEC(500));
+	zassert_equal(lid_is_open(), 0);
+}
+
+ZTEST(lid_switch, test_cmd_lidopen_bounce)
+{
+	/* Start closed. */
+	zassert_ok(emul_lid_close());
+	k_sleep(K_MSEC(100));
+	zassert_equal(lid_is_open(), 0);
+
+	printk("Console lid open\n");
+	/* Forced override lid open. */
+	zassert_equal(EC_SUCCESS, shell_execute_cmd(get_ec_shell(), "lidopen"),
+		      NULL);
+	zassert_equal(lid_is_open(), 1);
+	k_sleep(K_MSEC(100));
+
+	printk("Console lid open\n");
+	/* Forced override lid open. */
+	zassert_equal(EC_SUCCESS, shell_execute_cmd(get_ec_shell(), "lidopen"),
+		      NULL);
+	zassert_equal(lid_is_open(), 1);
+	k_sleep(K_MSEC(100));
+
+	printk("GPIO lid open/close\n");
+	/* Open & close with gpio. */
+	zassert_ok(emul_lid_open());
+	zassert_ok(emul_lid_close());
+	k_sleep(K_MSEC(500));
+	zassert_equal(lid_is_open(), 0);
+}
+
+ZTEST(lid_switch, test_cmd_lidclose)
+{
+	/* Start open. */
+	zassert_ok(emul_lid_open());
+	k_sleep(K_MSEC(100));
+	zassert_equal(lid_is_open(), 1);
+
+	/* Forced override lid close. */
+	zassert_equal(EC_SUCCESS, shell_execute_cmd(get_ec_shell(), "lidclose"),
+		      NULL);
+	zassert_equal(lid_is_open(), 0);
+	k_sleep(K_MSEC(100));
+
+	printk("GPIO lid close/open\n");
+	/* Close & open with gpio. */
+	zassert_ok(emul_lid_close());
+	zassert_ok(emul_lid_open());
+	k_sleep(K_MSEC(500));
+	zassert_equal(lid_is_open(), 1);
+}
+
+ZTEST(lid_switch, test_cmd_lidclose_bounce)
+{
+	/* Start open. */
+	zassert_ok(emul_lid_open());
+	k_sleep(K_MSEC(100));
+	zassert_equal(lid_is_open(), 1);
+
+	/* Forced override lid close. */
+	zassert_equal(EC_SUCCESS, shell_execute_cmd(get_ec_shell(), "lidclose"),
+		      NULL);
+	zassert_equal(lid_is_open(), 0);
+	k_sleep(K_MSEC(100));
+
+	/* Forced override lid close. */
+	zassert_equal(EC_SUCCESS, shell_execute_cmd(get_ec_shell(), "lidclose"),
+		      NULL);
+	zassert_equal(lid_is_open(), 0);
+	k_sleep(K_MSEC(100));
+
+	printk("GPIO lid close/open\n");
+	/* Close & open with gpio. */
+	zassert_ok(emul_lid_close());
+	zassert_ok(emul_lid_open());
+	k_sleep(K_MSEC(500));
+	zassert_equal(lid_is_open(), 1);
+}
+
+#if defined(CONFIG_SHELL_BACKEND_DUMMY)
+ZTEST(lid_switch, test_cmd_lidstate_open)
+{
+	const char *buffer;
+	size_t buffer_size;
+
+	/* Start open. */
+	zassert_ok(emul_lid_open());
+	k_sleep(K_MSEC(100));
+	zassert_equal(lid_is_open(), 1);
+
+	/* Read the state with console. */
+	shell_backend_dummy_clear_output(get_ec_shell());
+	zassert_equal(EC_SUCCESS, shell_execute_cmd(get_ec_shell(), "lidstate"),
+		      NULL);
+	buffer = shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+	zassert_true(strcmp(buffer, "\r\nlid state: open\r\n") == 0,
+		     "Invalid console output %s", buffer);
+}
+
+ZTEST(lid_switch, test_cmd_lidstate_close)
+{
+	const char *buffer;
+	size_t buffer_size;
+
+	/* Start closed. */
+	zassert_ok(emul_lid_close());
+	k_sleep(K_MSEC(100));
+	zassert_equal(lid_is_open(), 0);
+
+	/* Read the state with console. */
+	shell_backend_dummy_clear_output(get_ec_shell());
+	zassert_equal(EC_SUCCESS, shell_execute_cmd(get_ec_shell(), "lidstate"),
+		      NULL);
+	buffer = shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+	zassert_true(strcmp(buffer, "\r\nlid state: closed\r\n") == 0,
+		     "Invalid console output %s", buffer);
+}
+#else
+#error This test requires CONFIG_SHELL_BACKEND_DUMMY
+#endif
+
+ZTEST(lid_switch, test_hc_force_lid_open)
+{
+	struct ec_params_force_lid_open params = {
+		.enabled = 1,
+	};
+
+	/* Start closed. */
+	zassert_ok(emul_lid_close());
+	k_sleep(K_MSEC(100));
+	zassert_equal(lid_is_open(), 0);
+
+	zassert_ok(ec_cmd_force_lid_open(NULL, &params));
+	k_sleep(K_MSEC(100));
+	zassert_equal(lid_is_open(), 1);
+}
+
+ZTEST_SUITE(lid_switch, drivers_predicate_post_main, lid_switch_setup,
+	    lid_switch_before, lid_switch_after, NULL);
diff --git a/zephyr/test/drivers/default/src/lis2dw12.c b/zephyr/test/drivers/default/src/lis2dw12.c
new file mode 100644
index 0000000000..e7609300a0
--- /dev/null
+++ b/zephyr/test/drivers/default/src/lis2dw12.c
@@ -0,0 +1,456 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/accel_lis2dw12.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_lis2dw12.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/ztest.h>
+
+#define LIS2DW12_NODELABEL DT_NODELABEL(ms_lis2dw12_accel)
+#define LIS2DW12_SENSOR_ID SENSOR_ID(LIS2DW12_NODELABEL)
+#define LIS2DW12_EMUL_NODE DT_NODELABEL(lis2dw12_emul)
+
+#include <stdio.h>
+
+#define CHECK_XYZ_EQUALS(VEC1, VEC2)                                  \
+	do {                                                          \
+		zassert_equal((VEC1)[X], (VEC2)[X],                   \
+			      "Got %d for X, expected %d", (VEC1)[X], \
+			      (VEC2)[X]);                             \
+		zassert_equal((VEC1)[Y], (VEC2)[Y],                   \
+			      "Got %d for Y, expected %d", (VEC1)[Y], \
+			      (VEC2)[Y]);                             \
+		zassert_equal((VEC1)[Z], (VEC2)[Z],                   \
+			      "Got %d for Z, expected %d", (VEC1)[Z], \
+			      (VEC2)[Z]);                             \
+	} while (0)
+
+/** Used with the LIS2DW12 set rate function to control rounding behavior */
+enum lis2dw12_round_mode {
+	ROUND_DOWN,
+	ROUND_UP,
+};
+
+static inline void lis2dw12_setup(void)
+{
+	lis2dw12_emul_reset(EMUL_DT_GET(LIS2DW12_EMUL_NODE));
+
+	/* Reset certain sensor struct values */
+	struct motion_sensor_t *ms = &motion_sensors[LIS2DW12_SENSOR_ID];
+
+	ms->current_range = 0;
+}
+
+static void lis2dw12_before(void *state)
+{
+	ARG_UNUSED(state);
+	lis2dw12_setup();
+}
+
+static void lis2dw12_after(void *state)
+{
+	ARG_UNUSED(state);
+	lis2dw12_setup();
+}
+
+ZTEST(lis2dw12, test_lis2dw12_init__fail_read_who_am_i)
+{
+	const struct emul *emul = EMUL_DT_GET(LIS2DW12_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_lis2dw12_get_i2c_common_data(emul);
+	struct motion_sensor_t *ms = &motion_sensors[LIS2DW12_SENSOR_ID];
+	int rv;
+
+	i2c_common_emul_set_read_fail_reg(common_data, LIS2DW12_WHO_AM_I_REG);
+	rv = ms->drv->init(ms);
+	zassert_equal(EC_ERROR_INVAL, rv);
+}
+
+ZTEST(lis2dw12, test_lis2dw12_init__fail_who_am_i)
+{
+	const struct emul *emul = EMUL_DT_GET(LIS2DW12_EMUL_NODE);
+	struct motion_sensor_t *ms = &motion_sensors[LIS2DW12_SENSOR_ID];
+	int rv;
+
+	lis2dw12_emul_set_who_am_i(emul, ~LIS2DW12_WHO_AM_I);
+
+	rv = ms->drv->init(ms);
+	zassert_equal(EC_ERROR_ACCESS_DENIED, rv,
+		      "init returned %d but was expecting %d", rv,
+		      EC_ERROR_ACCESS_DENIED);
+}
+
+ZTEST(lis2dw12, test_lis2dw12_init__fail_write_soft_reset)
+{
+	const struct emul *emul = EMUL_DT_GET(LIS2DW12_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_lis2dw12_get_i2c_common_data(emul);
+	struct motion_sensor_t *ms = &motion_sensors[LIS2DW12_SENSOR_ID];
+	int rv;
+
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   LIS2DW12_SOFT_RESET_ADDR);
+	rv = ms->drv->init(ms);
+	zassert_equal(EC_ERROR_INVAL, rv);
+}
+
+ZTEST(lis2dw12, test_lis2dw12_init__timeout_read_soft_reset)
+{
+	const struct emul *emul = EMUL_DT_GET(LIS2DW12_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_lis2dw12_get_i2c_common_data(emul);
+	struct motion_sensor_t *ms = &motion_sensors[LIS2DW12_SENSOR_ID];
+	int rv;
+
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  LIS2DW12_SOFT_RESET_ADDR);
+	rv = ms->drv->init(ms);
+	zassert_equal(EC_ERROR_TIMEOUT, rv, "init returned %d but expected %d",
+		      rv, EC_ERROR_TIMEOUT);
+}
+
+static int lis2dw12_test_mock_write_fail_set_bdu(const struct emul *emul,
+						 int reg, uint8_t val,
+						 int bytes, void *data)
+{
+	if (reg == LIS2DW12_BDU_ADDR && bytes == 1 &&
+	    (val & LIS2DW12_BDU_MASK) != 0) {
+		return -EIO;
+	}
+	return 1;
+}
+
+ZTEST(lis2dw12, test_lis2dw12_init__fail_set_bdu)
+{
+	const struct emul *emul = EMUL_DT_GET(LIS2DW12_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_lis2dw12_get_i2c_common_data(emul);
+	struct motion_sensor_t *ms = &motion_sensors[LIS2DW12_SENSOR_ID];
+	int rv;
+
+	i2c_common_emul_set_write_func(
+		common_data, lis2dw12_test_mock_write_fail_set_bdu, NULL);
+	rv = ms->drv->init(ms);
+	zassert_equal(EC_ERROR_INVAL, rv, "init returned %d but expected %d",
+		      rv, EC_ERROR_INVAL);
+	zassert_true(lis2dw12_emul_get_soft_reset_count(emul) > 0,
+		     "expected at least one soft reset");
+}
+
+ZTEST(lis2dw12, test_lis2dw12_init__fail_set_lir)
+{
+	const struct emul *emul = EMUL_DT_GET(LIS2DW12_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_lis2dw12_get_i2c_common_data(emul);
+	struct motion_sensor_t *ms = &motion_sensors[LIS2DW12_SENSOR_ID];
+	int rv;
+
+	i2c_common_emul_set_read_fail_reg(common_data, LIS2DW12_LIR_ADDR);
+
+	rv = ms->drv->init(ms);
+	zassert_equal(EC_ERROR_INVAL, rv, "init returned %d but expected %d",
+		      rv, EC_ERROR_INVAL);
+	zassert_true(lis2dw12_emul_get_soft_reset_count(emul) > 0,
+		     "expected at least one soft reset");
+}
+
+static int lis2dw12_test_mock_write_fail_set_power_mode(const struct emul *emul,
+							int reg, uint8_t val,
+							int bytes, void *data)
+{
+	if (reg == LIS2DW12_ACC_LPMODE_ADDR && bytes == 1 &&
+	    (val & LIS2DW12_ACC_LPMODE_MASK) != 0) {
+		/* Cause an error when trying to set the LPMODE */
+		return -EIO;
+	}
+	return 1;
+}
+
+ZTEST(lis2dw12, test_lis2dw12_init__fail_set_power_mode)
+{
+	const struct emul *emul = EMUL_DT_GET(LIS2DW12_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_lis2dw12_get_i2c_common_data(emul);
+	struct motion_sensor_t *ms = &motion_sensors[LIS2DW12_SENSOR_ID];
+	int rv;
+
+	i2c_common_emul_set_write_func(
+		common_data, lis2dw12_test_mock_write_fail_set_power_mode,
+		NULL);
+
+	rv = ms->drv->init(ms);
+	zassert_equal(EC_ERROR_INVAL, rv, "init returned %d but expected %d",
+		      rv, EC_ERROR_INVAL);
+	zassert_true(lis2dw12_emul_get_soft_reset_count(emul) > 0,
+		     "expected at least one soft reset");
+}
+
+ZTEST(lis2dw12, test_lis2dw12_init__success)
+{
+	const struct emul *emul = EMUL_DT_GET(LIS2DW12_EMUL_NODE);
+	struct motion_sensor_t *ms = &motion_sensors[LIS2DW12_SENSOR_ID];
+	struct stprivate_data *drvdata = ms->drv_data;
+
+	int rv;
+
+	rv = ms->drv->init(ms);
+	zassert_equal(EC_SUCCESS, rv, "init returned %d but expected %d", rv,
+		      EC_SUCCESS);
+	zassert_true(lis2dw12_emul_get_soft_reset_count(emul) > 0,
+		     "expected at least one soft reset");
+	zassert_equal(LIS2DW12_RESOLUTION, drvdata->resol,
+		      "Expected resolution of %d but got %d",
+		      LIS2DW12_RESOLUTION, drvdata->resol);
+}
+
+ZTEST(lis2dw12, test_lis2dw12_set_power_mode)
+{
+	const struct emul *emul = EMUL_DT_GET(LIS2DW12_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_lis2dw12_get_i2c_common_data(emul);
+	struct motion_sensor_t *ms = &motion_sensors[LIS2DW12_SENSOR_ID];
+	int rv;
+
+	/* Part 1: happy path */
+	rv = lis2dw12_set_power_mode(ms, LIS2DW12_LOW_POWER,
+				     LIS2DW12_LOW_POWER_MODE_2);
+	zassert_equal(rv, EC_SUCCESS, "Expected %d but got %d", EC_SUCCESS, rv);
+
+	/* Part 2: unimplemented modes */
+	rv = lis2dw12_set_power_mode(ms, LIS2DW12_LOW_POWER,
+				     LIS2DW12_LOW_POWER_MODE_1);
+	zassert_equal(rv, EC_ERROR_UNIMPLEMENTED, "Expected %d but got %d",
+		      EC_ERROR_UNIMPLEMENTED, rv);
+
+	/* Part 3: attempt to set mode but cannot modify reg. */
+	i2c_common_emul_set_read_fail_reg(common_data, LIS2DW12_ACC_MODE_ADDR);
+	rv = lis2dw12_set_power_mode(ms, LIS2DW12_LOW_POWER,
+				     LIS2DW12_LOW_POWER_MODE_2);
+	zassert_equal(rv, EC_ERROR_INVAL, "Expected %d but got %d",
+		      EC_ERROR_INVAL, rv);
+}
+
+ZTEST(lis2dw12, test_lis2dw12_set_range)
+{
+	const struct emul *emul = EMUL_DT_GET(LIS2DW12_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_lis2dw12_get_i2c_common_data(emul);
+	struct motion_sensor_t *ms = &motion_sensors[LIS2DW12_SENSOR_ID];
+	int rv;
+
+	/* Part 1: Happy path. Go above the max range; it will be automatically
+	 * clamped.
+	 */
+
+	rv = ms->drv->set_range(ms, LIS2DW12_ACCEL_FS_MAX_VAL + 1, 0);
+	zassert_equal(rv, EC_SUCCESS, "Expected %d but got %d", EC_SUCCESS, rv);
+	zassert_equal(ms->current_range, LIS2DW12_ACCEL_FS_MAX_VAL,
+		      "Expected %d but got %d", LIS2DW12_ACCEL_FS_MAX_VAL,
+		      ms->current_range);
+
+	/* Part 2: Error accessing register */
+	i2c_common_emul_set_read_fail_reg(common_data, LIS2DW12_FS_ADDR);
+	rv = ms->drv->set_range(ms, LIS2DW12_ACCEL_FS_MAX_VAL, 0);
+	zassert_equal(rv, EC_ERROR_INVAL, "Expected %d but got %d",
+		      EC_ERROR_INVAL, rv);
+}
+
+ZTEST(lis2dw12, test_lis2dw12_set_rate)
+{
+	const struct emul *emul = EMUL_DT_GET(LIS2DW12_EMUL_NODE);
+	struct motion_sensor_t *ms = &motion_sensors[LIS2DW12_SENSOR_ID];
+	struct stprivate_data *drv_data = ms->drv_data;
+	int rv;
+
+	/* Part 1: Turn off sensor with rate=0 */
+	rv = ms->drv->set_data_rate(ms, 0, 0);
+
+	zassert_equal(lis2dw12_emul_peek_odr(emul), LIS2DW12_ODR_POWER_OFF_VAL,
+		      "Output data rate should be %d but got %d",
+		      LIS2DW12_ODR_POWER_OFF_VAL, lis2dw12_emul_peek_odr(emul));
+	zassert_equal(drv_data->base.odr, LIS2DW12_ODR_POWER_OFF_VAL,
+		      "Output data rate should be %d but got %d",
+		      LIS2DW12_ODR_POWER_OFF_VAL, drv_data->base.odr);
+	zassert_equal(rv, EC_SUCCESS, "Returned %d but expected %d", rv,
+		      EC_SUCCESS);
+
+	/* Part 2: Set some output data rates. We will request a certain rate
+	 * and make sure the closest supported rate is used.
+	 */
+
+	static const struct {
+		int requested_rate; /* millihertz */
+		enum lis2dw12_round_mode round;
+		int expected_norm_rate; /* millihertz */
+		uint8_t expected_reg_val;
+	} test_params[] = {
+		{ 1000, ROUND_DOWN, LIS2DW12_ODR_MIN_VAL,
+		  LIS2DW12_ODR_12HZ_VAL },
+		{ 12501, ROUND_DOWN, 12500, LIS2DW12_ODR_12HZ_VAL },
+		{ 25001, ROUND_DOWN, 25000, LIS2DW12_ODR_25HZ_VAL },
+		{ 50001, ROUND_DOWN, 50000, LIS2DW12_ODR_50HZ_VAL },
+		{ 100001, ROUND_DOWN, 100000, LIS2DW12_ODR_100HZ_VAL },
+		{ 200001, ROUND_DOWN, 200000, LIS2DW12_ODR_200HZ_VAL },
+		{ 400001, ROUND_DOWN, 400000, LIS2DW12_ODR_400HZ_VAL },
+		{ 800001, ROUND_DOWN, 800000, LIS2DW12_ODR_800HZ_VAL },
+		{ 1600001, ROUND_DOWN, 1600000, LIS2DW12_ODR_1_6kHZ_VAL },
+		{ 3200001, ROUND_DOWN, LIS2DW12_ODR_MAX_VAL,
+		  LIS2DW12_ODR_1_6kHZ_VAL },
+
+		{ 1000, ROUND_UP, LIS2DW12_ODR_MIN_VAL, LIS2DW12_ODR_12HZ_VAL },
+		{ 12501, ROUND_UP, 25000, LIS2DW12_ODR_25HZ_VAL },
+		{ 25001, ROUND_UP, 50000, LIS2DW12_ODR_50HZ_VAL },
+		{ 50001, ROUND_UP, 100000, LIS2DW12_ODR_100HZ_VAL },
+		{ 100001, ROUND_UP, 200000, LIS2DW12_ODR_200HZ_VAL },
+		{ 200001, ROUND_UP, 400000, LIS2DW12_ODR_400HZ_VAL },
+		{ 400001, ROUND_UP, 800000, LIS2DW12_ODR_800HZ_VAL },
+		{ 800001, ROUND_UP, 1600000, LIS2DW12_ODR_1_6kHZ_VAL },
+		{ 1600001, ROUND_UP, LIS2DW12_ODR_MAX_VAL,
+		  LIS2DW12_ODR_1_6kHZ_VAL },
+	};
+
+	for (size_t i = 0; i < ARRAY_SIZE(test_params); i++) {
+		/* For each test vector in the above array */
+		drv_data->base.odr = -1;
+		rv = ms->drv->set_data_rate(ms, test_params[i].requested_rate,
+					    test_params[i].round);
+
+		/* Check the normalized rate the driver chose */
+		zassert_equal(
+			drv_data->base.odr, test_params[i].expected_norm_rate,
+			"For requested rate %d, output data rate should be %d but got %d",
+			test_params[i].requested_rate,
+			test_params[i].expected_norm_rate, drv_data->base.odr);
+
+		/* Read ODR and mode bits back from CTRL1 register */
+		uint8_t odr_bits = lis2dw12_emul_peek_odr(emul);
+
+		zassert_equal(
+			odr_bits, test_params[i].expected_reg_val,
+			"For requested rate %d, ODR bits should be 0x%x but got 0x%x - %d",
+			test_params[i].requested_rate,
+			test_params[i].expected_reg_val, odr_bits,
+			LIS2DW12_ODR_MAX_VAL);
+
+		/* Check if high performance mode was enabled if rate >=
+		 * 50,000mHz
+		 */
+
+		uint8_t mode_bits = lis2dw12_emul_peek_mode(emul);
+		uint8_t lpmode_bits = lis2dw12_emul_peek_lpmode(emul);
+
+		if (odr_bits >= LIS2DW12_ODR_50HZ_VAL) {
+			/* High performance mode, LP mode immaterial */
+			zassert_equal(mode_bits, LIS2DW12_HIGH_PERF,
+				      "MODE[1:0] should be 0x%x, but got 0x%x",
+				      LIS2DW12_HIGH_PERF, mode_bits);
+
+		} else {
+			/* Low power mode, LP mode 2 */
+			zassert_equal(mode_bits, LIS2DW12_LOW_POWER,
+				      "MODE[1:0] should be 0x%x, but got 0x%x",
+				      LIS2DW12_LOW_POWER, mode_bits);
+
+			zassert_equal(
+				lpmode_bits, LIS2DW12_LOW_POWER_MODE_2,
+				"LPMODE[1:0] should be 0x%x, but got 0x%x",
+				LIS2DW12_LOW_POWER_MODE_2, lpmode_bits);
+		}
+	}
+}
+
+ZTEST(lis2dw12, test_lis2dw12_read)
+{
+	const struct emul *emul = EMUL_DT_GET(LIS2DW12_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_lis2dw12_get_i2c_common_data(emul);
+
+	struct motion_sensor_t *ms = &motion_sensors[LIS2DW12_SENSOR_ID];
+	struct stprivate_data *drvdata = ms->drv_data;
+	intv3_t sample = { 0, 0, 0 };
+	int rv;
+
+	/* Reading requires a range to be set. Use 1 so it has no effect
+	 * when scaling samples. Also need to set the sensor resolution
+	 * manually.
+	 */
+
+	ms->drv->set_range(ms, 1, 0);
+	drvdata->resol = LIS2DW12_RESOLUTION;
+
+	/* Part 1: Try to read from sensor, but cannot check status register for
+	 * ready bit
+	 */
+
+	i2c_common_emul_set_read_fail_reg(common_data, LIS2DW12_STATUS_REG);
+
+	rv = ms->drv->read(ms, sample);
+
+	zassert_equal(rv, EC_ERROR_INVAL,
+		      "Expected return val of %d but got %d", EC_ERROR_INVAL,
+		      rv);
+
+	/* Part 2: Try to read sensor, but no new data is available. In this
+	 * case, the driver should return the reading in from `ms->raw_xyz`
+	 */
+
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	lis2dw12_emul_clear_accel_reading(emul);
+	ms->raw_xyz[X] = 123;
+	ms->raw_xyz[Y] = 456;
+	ms->raw_xyz[Z] = 789;
+
+	rv = ms->drv->read(ms, sample);
+
+	zassert_equal(rv, EC_SUCCESS, "Expected return val of %d but got %d",
+		      EC_SUCCESS, rv);
+	CHECK_XYZ_EQUALS(sample, ms->raw_xyz);
+
+	/* Part 3: Read from sensor w/ data ready, but an error occurs during
+	 * read.
+	 */
+	intv3_t fake_sample = { 100, 200, 300 };
+
+	i2c_common_emul_set_read_fail_reg(common_data, LIS2DW12_OUT_X_L_ADDR);
+	lis2dw12_emul_set_accel_reading(emul, fake_sample);
+
+	rv = ms->drv->read(ms, sample);
+
+	zassert_equal(rv, EC_ERROR_INVAL,
+		      "Expected return val of %d but got %d", EC_ERROR_INVAL,
+		      rv);
+
+	/* Part 4: Success */
+
+	intv3_t expected_sample;
+
+	for (int i = 0; i < ARRAY_SIZE(expected_sample); i++) {
+		/* The read routine will normalize `fake_sample` to use the full
+		 * range of INT16, so we need to compensate in our expected
+		 * output
+		 */
+
+		expected_sample[i] =
+			fake_sample[i] * (1 << (16 - LIS2DW12_RESOLUTION));
+	}
+
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	lis2dw12_emul_set_accel_reading(emul, fake_sample);
+
+	rv = ms->drv->read(ms, sample);
+
+	zassert_equal(rv, EC_SUCCESS, "Expected return val of %d but got %d",
+		      EC_SUCCESS, rv);
+	CHECK_XYZ_EQUALS(sample, expected_sample);
+}
+
+ZTEST_SUITE(lis2dw12, drivers_predicate_post_main, NULL, lis2dw12_before,
+	    lis2dw12_after, NULL);
diff --git a/zephyr/test/drivers/default/src/ln9310.c b/zephyr/test/drivers/default/src/ln9310.c
new file mode 100644
index 0000000000..509d6831ec
--- /dev/null
+++ b/zephyr/test/drivers/default/src/ln9310.c
@@ -0,0 +1,685 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/ln9310.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_ln9310.h"
+#include "test/drivers/test_state.h"
+#include "timer.h"
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/i2c_emul.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+#include <zephyr/ztest_assert.h>
+
+/*
+ * TODO(b/201420132): Implement approach for tests to immediately schedule work
+ * to avoid any sleeping
+ */
+#define TEST_DELAY_MS 50
+
+#define EMUL_LN9310_NODE DT_NODELABEL(ln9310)
+
+/*
+ * Chip revisions below LN9310_BC_STS_C_CHIP_REV_FIXED require an alternative
+ * software startup to properly initialize and power up.
+ */
+#define REQUIRES_CFLY_PRECHARGE_STARTUP_CHIP_REV \
+	(LN9310_BC_STS_C_CHIP_REV_FIXED - 1)
+
+ZTEST(ln9310, test_ln9310_read_chip_fails)
+{
+	const struct emul *emulator = EMUL_DT_GET(EMUL_LN9310_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_ln9310_get_i2c_common_data(emulator);
+
+	zassert_not_null(emulator, NULL);
+
+	ln9310_emul_set_context(emulator);
+	ln9310_emul_reset(emulator);
+	/* Battery and chip rev won't matter here so only testing one pair */
+	ln9310_emul_set_battery_cell_type(emulator, BATTERY_CELL_TYPE_2S);
+	ln9310_emul_set_version(emulator, LN9310_BC_STS_C_CHIP_REV_FIXED);
+
+	i2c_common_emul_set_read_fail_reg(common_data, LN9310_REG_BC_STS_C);
+
+	zassert_true(ln9310_init() != 0);
+	zassert_false(ln9310_emul_is_init(emulator));
+
+	/* TODO(b/201420132) */
+	k_msleep(TEST_DELAY_MS);
+	zassert_false(ln9310_power_good());
+
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+}
+
+ZTEST(ln9310, test_ln9310_2s_powers_up)
+{
+	const struct emul *emulator = EMUL_DT_GET(EMUL_LN9310_NODE);
+
+	zassert_not_null(emulator, NULL);
+
+	ln9310_emul_set_context(emulator);
+	ln9310_emul_reset(emulator);
+	ln9310_emul_set_battery_cell_type(emulator, BATTERY_CELL_TYPE_2S);
+	ln9310_emul_set_version(emulator, LN9310_BC_STS_C_CHIP_REV_FIXED);
+
+	zassert_ok(ln9310_init());
+	zassert_true(ln9310_emul_is_init(emulator));
+
+	/* TODO(b/201420132) */
+	k_msleep(TEST_DELAY_MS);
+	zassert_false(ln9310_power_good());
+
+	ln9310_software_enable(true);
+
+	k_msleep(TEST_DELAY_MS);
+	zassert_true(ln9310_power_good());
+}
+
+ZTEST(ln9310, test_ln9310_3s_powers_up)
+{
+	const struct emul *emulator = EMUL_DT_GET(EMUL_LN9310_NODE);
+
+	zassert_not_null(emulator, NULL);
+
+	ln9310_emul_set_context(emulator);
+	ln9310_emul_reset(emulator);
+	ln9310_emul_set_battery_cell_type(emulator, BATTERY_CELL_TYPE_3S);
+	ln9310_emul_set_version(emulator, LN9310_BC_STS_C_CHIP_REV_FIXED);
+
+	zassert_ok(ln9310_init());
+	zassert_true(ln9310_emul_is_init(emulator));
+
+	/* TODO(b/201420132) */
+	k_msleep(TEST_DELAY_MS);
+	zassert_false(ln9310_power_good());
+
+	ln9310_software_enable(true);
+
+	k_msleep(TEST_DELAY_MS);
+	zassert_true(ln9310_power_good());
+}
+
+struct startup_workaround_data {
+	bool startup_workaround_attempted;
+	bool startup_workaround_should_fail;
+};
+
+static int mock_write_fn_intercept_startup_workaround(const struct emul *emul,
+						      int reg, uint8_t val,
+						      int bytes, void *data)
+{
+	struct startup_workaround_data *test_data = data;
+
+	uint8_t startup_workaround_val =
+		(LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_ON |
+		 LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_ON);
+
+	test_data->startup_workaround_attempted =
+		test_data->startup_workaround_attempted ||
+		((reg == LN9310_REG_TEST_MODE_CTRL) &&
+		 (val == startup_workaround_val));
+
+	if (test_data->startup_workaround_should_fail)
+		return -1;
+
+	return 1;
+}
+
+ZTEST(ln9310, test_ln9310_2s_cfly_precharge_startup)
+{
+	const struct emul *emulator = EMUL_DT_GET(EMUL_LN9310_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_ln9310_get_i2c_common_data(emulator);
+
+	struct startup_workaround_data test_data = {
+		.startup_workaround_attempted = false,
+		.startup_workaround_should_fail = false,
+	};
+
+	zassert_not_null(emulator, NULL);
+
+	ln9310_emul_set_context(emulator);
+	ln9310_emul_reset(emulator);
+	ln9310_emul_set_battery_cell_type(emulator, BATTERY_CELL_TYPE_2S);
+	ln9310_emul_set_version(emulator,
+				REQUIRES_CFLY_PRECHARGE_STARTUP_CHIP_REV);
+
+	zassert_ok(ln9310_init());
+	zassert_true(ln9310_emul_is_init(emulator));
+
+	/* TODO(b/201420132) */
+	k_msleep(TEST_DELAY_MS);
+	zassert_false(ln9310_power_good());
+
+	i2c_common_emul_set_write_func(
+		common_data, mock_write_fn_intercept_startup_workaround,
+		&test_data);
+
+	ln9310_software_enable(true);
+	zassert_true(test_data.startup_workaround_attempted);
+
+	/* TODO(b/201420132) */
+	k_msleep(TEST_DELAY_MS);
+	zassert_true(ln9310_power_good());
+
+	ln9310_software_enable(false);
+
+	/* TODO(b/201420132) */
+	k_msleep(TEST_DELAY_MS);
+	zassert_false(ln9310_power_good());
+
+	i2c_common_emul_set_write_func(common_data, NULL, NULL);
+}
+
+ZTEST(ln9310, test_ln9310_3s_cfly_precharge_startup)
+{
+	const struct emul *emulator = EMUL_DT_GET(EMUL_LN9310_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_ln9310_get_i2c_common_data(emulator);
+
+	struct startup_workaround_data test_data = {
+		.startup_workaround_attempted = false,
+		.startup_workaround_should_fail = false,
+	};
+
+	zassert_not_null(emulator, NULL);
+
+	ln9310_emul_set_context(emulator);
+	ln9310_emul_reset(emulator);
+	ln9310_emul_set_battery_cell_type(emulator, BATTERY_CELL_TYPE_3S);
+	ln9310_emul_set_version(emulator,
+				REQUIRES_CFLY_PRECHARGE_STARTUP_CHIP_REV);
+
+	zassert_ok(ln9310_init());
+	zassert_true(ln9310_emul_is_init(emulator));
+
+	/* TODO(b/201420132) */
+	k_msleep(TEST_DELAY_MS);
+	zassert_false(ln9310_power_good());
+
+	i2c_common_emul_set_write_func(
+		common_data, mock_write_fn_intercept_startup_workaround,
+		&test_data);
+
+	ln9310_software_enable(true);
+	zassert_true(test_data.startup_workaround_attempted);
+
+	/* TODO(b/201420132) */
+	k_msleep(TEST_DELAY_MS);
+	zassert_true(ln9310_power_good());
+
+	ln9310_software_enable(false);
+
+	/* TODO(b/201420132) */
+	k_msleep(TEST_DELAY_MS);
+	zassert_false(ln9310_power_good());
+
+	i2c_common_emul_set_write_func(common_data, NULL, NULL);
+}
+
+ZTEST(ln9310, test_ln9310_cfly_precharge_exceeds_retries)
+{
+	const struct emul *emulator = EMUL_DT_GET(EMUL_LN9310_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_ln9310_get_i2c_common_data(emulator);
+
+	struct startup_workaround_data test_data = {
+		.startup_workaround_attempted = false,
+		.startup_workaround_should_fail = true,
+	};
+
+	zassert_not_null(emulator, NULL);
+
+	ln9310_emul_set_context(emulator);
+	ln9310_emul_reset(emulator);
+	/*
+	 * Battery and chip rev won't matter for statement
+	 * coverage here so only testing one pair.
+	 */
+	ln9310_emul_set_battery_cell_type(emulator, BATTERY_CELL_TYPE_2S);
+	ln9310_emul_set_version(emulator,
+				REQUIRES_CFLY_PRECHARGE_STARTUP_CHIP_REV);
+
+	zassert_ok(ln9310_init());
+	zassert_true(ln9310_emul_is_init(emulator));
+
+	/* TODO(b/201420132) */
+	k_msleep(TEST_DELAY_MS);
+	zassert_false(ln9310_power_good());
+
+	i2c_common_emul_set_write_func(
+		common_data, mock_write_fn_intercept_startup_workaround,
+		&test_data);
+
+	ln9310_software_enable(true);
+	zassert_true(test_data.startup_workaround_attempted);
+
+	/* TODO(b/201420132) */
+	k_msleep(TEST_DELAY_MS);
+	zassert_false(ln9310_power_good());
+
+	i2c_common_emul_set_write_func(common_data, NULL, NULL);
+}
+
+ZTEST(ln9310, test_ln9310_battery_unknown)
+{
+	const struct emul *emulator = EMUL_DT_GET(EMUL_LN9310_NODE);
+
+	zassert_not_null(emulator, NULL);
+
+	ln9310_emul_set_context(emulator);
+	ln9310_emul_reset(emulator);
+	/*
+	 * Chip rev won't matter for statement
+	 * cov so only testing one version.
+	 */
+	ln9310_emul_set_battery_cell_type(emulator, BATTERY_CELL_TYPE_UNKNOWN);
+	ln9310_emul_set_version(emulator, LN9310_BC_STS_C_CHIP_REV_FIXED);
+
+	zassert_true(ln9310_init() != 0);
+	zassert_false(ln9310_emul_is_init(emulator));
+
+	/* TODO(b/201420132) */
+	k_msleep(TEST_DELAY_MS);
+	zassert_false(ln9310_power_good());
+
+	ln9310_software_enable(true);
+
+	/* TODO(b/201420132) */
+	k_msleep(TEST_DELAY_MS);
+	zassert_false(ln9310_power_good());
+}
+
+ZTEST(ln9310, test_ln9310_2s_battery_read_fails)
+{
+	const struct emul *emulator = EMUL_DT_GET(EMUL_LN9310_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_ln9310_get_i2c_common_data(emulator);
+
+	zassert_not_null(emulator, NULL);
+
+	ln9310_emul_set_context(emulator);
+	ln9310_emul_reset(emulator);
+
+	ln9310_emul_set_battery_cell_type(emulator, BATTERY_CELL_TYPE_2S);
+	ln9310_emul_set_version(emulator, LN9310_BC_STS_C_CHIP_REV_FIXED);
+
+	i2c_common_emul_set_read_fail_reg(common_data, LN9310_REG_BC_STS_B);
+
+	zassert_true(ln9310_init() != 0);
+	zassert_false(ln9310_emul_is_init(emulator));
+
+	/* TODO(b/201420132) */
+	k_msleep(TEST_DELAY_MS);
+	zassert_false(ln9310_power_good());
+
+	/* For Battery 2S Versions: Test Read Battery Voltage Failure Too */
+	ln9310_emul_reset(emulator);
+	ln9310_emul_set_battery_cell_type(emulator, BATTERY_CELL_TYPE_2S);
+	ln9310_emul_set_version(emulator, LN9310_BC_STS_C_CHIP_REV_FIXED);
+
+	i2c_common_emul_set_read_fail_reg(common_data, LN9310_REG_TRACK_CTRL);
+
+	zassert_false(ln9310_init() == 0);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+}
+
+ZTEST(ln9310, test_ln9310_lion_ctrl_reg_fails)
+{
+	const struct emul *emulator = EMUL_DT_GET(EMUL_LN9310_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_ln9310_get_i2c_common_data(emulator);
+
+	zassert_not_null(emulator, NULL);
+
+	ln9310_emul_set_context(emulator);
+	ln9310_emul_reset(emulator);
+	/* Battery won't matter here so only testing one version */
+	ln9310_emul_set_battery_cell_type(emulator, BATTERY_CELL_TYPE_2S);
+	ln9310_emul_set_version(emulator, LN9310_BC_STS_C_CHIP_REV_FIXED);
+
+	i2c_common_emul_set_read_fail_reg(common_data, LN9310_REG_LION_CTRL);
+
+	zassert_true(ln9310_init() != 0);
+	zassert_false(ln9310_emul_is_init(emulator));
+
+	/* TODO(b/201420132) */
+	k_msleep(TEST_DELAY_MS);
+	zassert_false(ln9310_power_good());
+
+	/* TODO(b/201420132) */
+	k_msleep(TEST_DELAY_MS);
+	ln9310_software_enable(true);
+	zassert_false(ln9310_power_good());
+
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+}
+
+struct precharge_timeout_data {
+	timestamp_t time_to_mock;
+	bool handled_clearing_standby_en_bit_timeout;
+};
+
+static int mock_intercept_startup_ctrl_reg(const struct emul *emulator, int reg,
+					   uint8_t val, int bytes, void *data)
+{
+	struct precharge_timeout_data *test_data = data;
+
+	if (reg == LN9310_REG_STARTUP_CTRL &&
+	    test_data->handled_clearing_standby_en_bit_timeout == false) {
+		if (val == 0) {
+			timestamp_t time = get_time();
+
+			time.val += 1 + LN9310_CFLY_PRECHARGE_TIMEOUT;
+			test_data->time_to_mock = time;
+			get_time_mock = &test_data->time_to_mock;
+		} else {
+			/* ln9310 aborts a startup attempt */
+			test_data->handled_clearing_standby_en_bit_timeout =
+				true;
+			get_time_mock = NULL;
+		}
+	}
+	return 1;
+}
+
+ZTEST(ln9310, test_ln9310_cfly_precharge_timesout)
+{
+	const struct emul *emulator = EMUL_DT_GET(EMUL_LN9310_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_ln9310_get_i2c_common_data(emulator);
+	struct precharge_timeout_data test_data = {
+		.time_to_mock = {
+			.val = -1,
+			.le = {
+				.lo = -1,
+				.hi = -1,
+			},
+		},
+		.handled_clearing_standby_en_bit_timeout = false,
+	};
+
+	zassert_not_null(emulator, NULL);
+
+	ln9310_emul_set_context(emulator);
+	ln9310_emul_reset(emulator);
+	/* Battery and chip rev won't matter here so only testing one pair */
+	ln9310_emul_set_battery_cell_type(emulator, BATTERY_CELL_TYPE_2S);
+	ln9310_emul_set_version(emulator,
+				REQUIRES_CFLY_PRECHARGE_STARTUP_CHIP_REV);
+
+	zassert_ok(ln9310_init());
+	zassert_true(ln9310_emul_is_init(emulator));
+
+	/* TODO(b/201420132) */
+	k_msleep(TEST_DELAY_MS);
+	zassert_false(ln9310_power_good());
+
+	i2c_common_emul_set_write_func(
+		common_data, mock_intercept_startup_ctrl_reg, &test_data);
+
+	ln9310_software_enable(true);
+	/* TODO(b/201420132) */
+	k_msleep(TEST_DELAY_MS);
+	zassert_true(test_data.handled_clearing_standby_en_bit_timeout);
+	/* It only times out on one attempt, it should subsequently startup */
+	zassert_true(ln9310_power_good());
+
+	i2c_common_emul_set_write_func(common_data, NULL, NULL);
+}
+
+struct reg_to_fail_data {
+	int reg_access_to_fail;
+	int reg_access_fail_countdown;
+};
+
+static int mock_read_intercept_reg_to_fail(const struct emul *emul, int reg,
+					   uint8_t *val, int bytes, void *data)
+{
+	struct reg_to_fail_data *test_data = data;
+
+	if (reg == test_data->reg_access_to_fail) {
+		test_data->reg_access_fail_countdown--;
+		if (test_data->reg_access_fail_countdown <= 0)
+			return -1;
+	}
+	return 1;
+}
+
+ZTEST(ln9310, test_ln9310_interrupt_reg_fail)
+{
+	const struct emul *emulator = EMUL_DT_GET(EMUL_LN9310_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_ln9310_get_i2c_common_data(emulator);
+	struct reg_to_fail_data test_data = {
+		.reg_access_to_fail = 0,
+		.reg_access_fail_countdown = 0,
+	};
+
+	zassert_not_null(emulator, NULL);
+
+	ln9310_emul_set_context(emulator);
+	ln9310_emul_reset(emulator);
+	/* Battery and chip rev won't matter here so only testing one pair */
+	ln9310_emul_set_battery_cell_type(emulator, BATTERY_CELL_TYPE_2S);
+	ln9310_emul_set_version(emulator, LN9310_BC_STS_C_CHIP_REV_FIXED);
+
+	zassert_ok(ln9310_init());
+	zassert_true(ln9310_emul_is_init(emulator));
+
+	i2c_common_emul_set_read_func(
+		common_data, mock_read_intercept_reg_to_fail, &test_data);
+
+	/* Fail in beginning of software enable */
+	test_data.reg_access_to_fail = LN9310_REG_INT1;
+	test_data.reg_access_fail_countdown = 1;
+
+	ln9310_software_enable(true);
+
+	/* TODO(b/201420132) */
+	k_msleep(TEST_DELAY_MS);
+	zassert_false(ln9310_power_good());
+	zassert_true(test_data.reg_access_fail_countdown <= 0);
+
+	/* Fail in irq interrupt handler */
+	test_data.reg_access_fail_countdown = 2;
+
+	ln9310_software_enable(true);
+	/* TODO(b/201420132) */
+	k_msleep(TEST_DELAY_MS);
+	zassert_false(ln9310_power_good());
+	zassert_true(test_data.reg_access_fail_countdown <= 0);
+
+	i2c_common_emul_set_read_func(common_data, NULL, NULL);
+}
+
+ZTEST(ln9310, test_ln9310_sys_sts_reg_fail)
+{
+	const struct emul *emulator = EMUL_DT_GET(EMUL_LN9310_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_ln9310_get_i2c_common_data(emulator);
+	struct reg_to_fail_data test_data = {
+		.reg_access_to_fail = 0,
+		.reg_access_fail_countdown = 0,
+	};
+
+	zassert_not_null(emulator, NULL);
+
+	ln9310_emul_set_context(emulator);
+	ln9310_emul_reset(emulator);
+	/* Battery and chip rev won't matter here so only testing one pair */
+	ln9310_emul_set_battery_cell_type(emulator, BATTERY_CELL_TYPE_2S);
+	ln9310_emul_set_version(emulator, LN9310_BC_STS_C_CHIP_REV_FIXED);
+
+	zassert_ok(ln9310_init());
+	zassert_true(ln9310_emul_is_init(emulator));
+
+	i2c_common_emul_set_read_func(
+		common_data, &mock_read_intercept_reg_to_fail, &test_data);
+
+	/* Register only read once and in the interrupt handler */
+	test_data.reg_access_to_fail = LN9310_REG_SYS_STS;
+	test_data.reg_access_fail_countdown = 1;
+
+	ln9310_software_enable(1);
+
+	/* TODO(b/201420132) */
+	k_msleep(TEST_DELAY_MS);
+
+	zassert_false(ln9310_power_good());
+	zassert_true(test_data.reg_access_fail_countdown <= 0);
+
+	i2c_common_emul_set_read_func(common_data, NULL, NULL);
+}
+
+struct reg_to_intercept {
+	int reg;
+	uint8_t replace_val;
+};
+
+static int mock_read_interceptor(const struct emul *emul, int reg, uint8_t *val,
+				 int bytes, void *data)
+{
+	struct reg_to_intercept *test_data = data;
+
+	if (test_data->reg == reg) {
+		*val = test_data->replace_val;
+		return 0;
+	}
+
+	return 1;
+}
+
+ZTEST(ln9310, test_ln9310_reset_explicit_detected_startup)
+{
+	const struct emul *emulator = EMUL_DT_GET(EMUL_LN9310_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_ln9310_get_i2c_common_data(emulator);
+	struct reg_to_intercept test_data = {
+		.reg = LN9310_REG_LION_CTRL,
+		.replace_val = 0,
+	};
+
+	zassert_not_null(emulator, NULL);
+
+	ln9310_emul_set_context(emulator);
+	ln9310_emul_reset(emulator);
+	/* Battery and chip rev won't matter here so only testing one pair */
+	ln9310_emul_set_battery_cell_type(emulator, BATTERY_CELL_TYPE_2S);
+	ln9310_emul_set_version(emulator, LN9310_BC_STS_C_CHIP_REV_FIXED);
+
+	zassert_ok(ln9310_init());
+	zassert_true(ln9310_emul_is_init(emulator));
+
+	i2c_common_emul_set_read_func(common_data, &mock_read_interceptor,
+				      &test_data);
+
+	ln9310_software_enable(true);
+
+	/* TODO(b/201420132) */
+	k_msleep(TEST_DELAY_MS);
+
+	zassert_true(ln9310_power_good());
+
+	i2c_common_emul_set_read_func(common_data, NULL, NULL);
+}
+
+ZTEST(ln9310, test_ln9310_update_startup_seq_fails)
+{
+	const struct emul *emulator = EMUL_DT_GET(EMUL_LN9310_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_ln9310_get_i2c_common_data(emulator);
+	struct reg_to_fail_data test_data = {
+		.reg_access_to_fail = LN9310_REG_CFG_4,
+		.reg_access_fail_countdown = 1,
+	};
+
+	zassert_not_null(emulator, NULL);
+
+	ln9310_emul_set_context(emulator);
+	ln9310_emul_reset(emulator);
+	/* Battery won't matter here so only testing one pair */
+	ln9310_emul_set_battery_cell_type(emulator, BATTERY_CELL_TYPE_2S);
+	/* Requires older version of chip */
+	ln9310_emul_set_version(emulator,
+				REQUIRES_CFLY_PRECHARGE_STARTUP_CHIP_REV);
+
+	i2c_common_emul_set_read_func(
+		common_data, &mock_read_intercept_reg_to_fail, &test_data);
+
+	zassert_false(ln9310_init() == 0);
+	zassert_false(ln9310_emul_is_init(emulator));
+
+	ln9310_software_enable(true);
+
+	/* TODO(b/201420132) */
+	k_msleep(TEST_DELAY_MS);
+
+	zassert_false(ln9310_power_good());
+	zassert_true(test_data.reg_access_fail_countdown <= 0);
+
+	i2c_common_emul_set_read_func(common_data, NULL, NULL);
+}
+
+ZTEST(ln9310, test_ln9310_state_change_only_on_mode_change_interrupt)
+{
+	const struct emul *emulator = EMUL_DT_GET(EMUL_LN9310_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_ln9310_get_i2c_common_data(emulator);
+	struct reg_to_intercept test_data = {
+		.reg = LN9310_REG_INT1,
+		.replace_val = 0,
+	};
+
+	zassert_not_null(emulator, NULL);
+
+	ln9310_emul_set_context(emulator);
+	ln9310_emul_reset(emulator);
+	/* Battery and chip rev won't matter here so only testing one pair */
+	ln9310_emul_set_battery_cell_type(emulator, BATTERY_CELL_TYPE_2S);
+	ln9310_emul_set_version(emulator, LN9310_BC_STS_C_CHIP_REV_FIXED);
+
+	zassert_ok(ln9310_init());
+	zassert_true(ln9310_emul_is_init(emulator));
+
+	i2c_common_emul_set_read_func(common_data, &mock_read_interceptor,
+				      &test_data);
+
+	ln9310_software_enable(true);
+
+	/* TODO(b/201420132) */
+	k_msleep(TEST_DELAY_MS);
+
+	zassert_false(ln9310_power_good());
+
+	i2c_common_emul_set_read_func(common_data, NULL, NULL);
+}
+
+static inline void reset_ln9310_state(void)
+{
+	ln9310_reset_to_initial_state();
+	get_time_mock = NULL;
+}
+
+static void ln9310_before(void *state)
+{
+	ARG_UNUSED(state);
+	reset_ln9310_state();
+}
+
+static void ln9310_after(void *state)
+{
+	ARG_UNUSED(state);
+	reset_ln9310_state();
+}
+
+ZTEST_SUITE(ln9310, drivers_predicate_post_main, NULL, ln9310_before,
+	    ln9310_after, NULL);
diff --git a/zephyr/test/drivers/default/src/locate_chip.c b/zephyr/test/drivers/default/src/locate_chip.c
new file mode 100644
index 0000000000..5efaa439f3
--- /dev/null
+++ b/zephyr/test/drivers/default/src/locate_chip.c
@@ -0,0 +1,124 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "host_command.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/fff.h>
+#include <zephyr/kernel.h>
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+/**
+ * @brief TestPurpose: test the TCPC locate valid case.
+ */
+ZTEST_USER(locate_chip, test_hc_locate_chip_tcpc)
+{
+	int ret;
+	struct ec_params_locate_chip p;
+	struct ec_response_locate_chip r;
+
+	p.type = EC_CHIP_TYPE_TCPC;
+	p.index = 0;
+
+	ret = ec_cmd_locate_chip(NULL, &p, &r);
+
+	zassert_equal(ret, EC_RES_SUCCESS, "Unexpected return value: %d", ret);
+	zassert_equal(r.bus_type, EC_BUS_TYPE_I2C, "Unexpected bus_type: %d",
+		      r.bus_type);
+	zassert_equal(r.i2c_info.port, 2, "Unexpected port: %d",
+		      r.i2c_info.port);
+	zassert_equal(r.i2c_info.addr_flags, 0x82, "Unexpected addr_flags: %d",
+		      r.i2c_info.addr_flags);
+
+	p.type = EC_CHIP_TYPE_TCPC;
+	p.index = 1;
+
+	ret = ec_cmd_locate_chip(NULL, &p, &r);
+
+	zassert_equal(ret, EC_RES_SUCCESS, "Unexpected return value: %d", ret);
+	zassert_equal(r.bus_type, EC_BUS_TYPE_I2C, "Unexpected bus_type: %d",
+		      r.bus_type);
+	zassert_equal(r.i2c_info.port, 3, "Unexpected port: %d",
+		      r.i2c_info.port);
+	zassert_equal(r.i2c_info.addr_flags, 0x0b, "Unexpected addr_flags: %d",
+		      r.i2c_info.addr_flags);
+}
+
+/**
+ * @brief TestPurpose: test the TCPC index overflow case.
+ */
+ZTEST_USER(locate_chip, test_hc_locate_chip_tcpc_overflow)
+{
+	int ret;
+	struct ec_params_locate_chip p;
+	struct ec_response_locate_chip r;
+
+	p.type = EC_CHIP_TYPE_TCPC;
+	p.index = 10;
+
+	ret = ec_cmd_locate_chip(NULL, &p, &r);
+
+	zassert_equal(ret, EC_RES_OVERFLOW, "Unexpected return value: %d", ret);
+}
+
+/**
+ * @brief TestPurpose: test the EEPROM locate valid case.
+ */
+ZTEST_USER(locate_chip, test_hc_locate_chip_eeprom)
+{
+	int ret;
+	struct ec_params_locate_chip p;
+	struct ec_response_locate_chip r;
+
+	p.type = EC_CHIP_TYPE_CBI_EEPROM;
+	p.index = 0;
+
+	ret = ec_cmd_locate_chip(NULL, &p, &r);
+
+	zassert_equal(ret, EC_RES_SUCCESS, "Unexpected return value: %d", ret);
+	zassert_equal(r.bus_type, EC_BUS_TYPE_I2C, "Unexpected bus_type: %d",
+		      r.bus_type);
+	zassert_equal(r.i2c_info.port, I2C_PORT_EEPROM, "Unexpected port: %d",
+		      r.i2c_info.port);
+	zassert_equal(r.i2c_info.addr_flags, I2C_ADDR_EEPROM_FLAGS,
+		      "Unexpected addr_flags: %d", r.i2c_info.addr_flags);
+}
+
+/**
+ * @brief TestPurpose: test the EEPROM index overflow case.
+ */
+ZTEST_USER(locate_chip, test_hc_locate_chip_eeprom_overflow)
+{
+	int ret;
+	struct ec_params_locate_chip p;
+	struct ec_response_locate_chip r;
+
+	p.type = EC_CHIP_TYPE_CBI_EEPROM;
+	p.index = 1;
+
+	ret = ec_cmd_locate_chip(NULL, &p, &r);
+
+	zassert_equal(ret, EC_RES_OVERFLOW, "Unexpected return value: %d", ret);
+}
+
+/**
+ * @brief TestPurpose: test the invalid parameter case.
+ */
+ZTEST_USER(locate_chip, test_hc_locate_chip_invalid)
+{
+	int ret;
+	struct ec_params_locate_chip p;
+	struct ec_response_locate_chip r;
+
+	p.type = EC_CHIP_TYPE_COUNT;
+	ret = ec_cmd_locate_chip(NULL, &p, &r);
+
+	zassert_equal(ret, EC_RES_INVALID_PARAM, "Unexpected return value: %d",
+		      ret);
+}
+
+ZTEST_SUITE(locate_chip, drivers_predicate_post_main, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/drivers/default/src/motion_sense/motion_sense.c b/zephyr/test/drivers/default/src/motion_sense/motion_sense.c
new file mode 100644
index 0000000000..9ea6509fe3
--- /dev/null
+++ b/zephyr/test/drivers/default/src/motion_sense/motion_sense.c
@@ -0,0 +1,51 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "motion_sense.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/ztest.h>
+
+extern enum chipset_state_mask sensor_active;
+
+ZTEST_SUITE(motion_sense, drivers_predicate_post_main, NULL, NULL, NULL, NULL);
+
+ZTEST_USER(motion_sense, test_ec_motion_sensor_fill_values)
+{
+	struct ec_response_motion_sensor_data dst = {
+		.data = { 1, 2, 3 },
+	};
+	const int32_t v[] = { 4, 5, 6 };
+
+	ec_motion_sensor_fill_values(&dst, v);
+	zassert_equal(dst.data[0], v[0]);
+	zassert_equal(dst.data[1], v[1]);
+	zassert_equal(dst.data[2], v[2]);
+}
+
+ZTEST_USER(motion_sense, test_ec_motion_sensor_clamp_i16)
+{
+	zassert_equal(ec_motion_sensor_clamp_i16(0), 0);
+	zassert_equal(ec_motion_sensor_clamp_i16(200), 200);
+	zassert_equal(ec_motion_sensor_clamp_i16(-512), -512);
+	zassert_equal(ec_motion_sensor_clamp_i16(INT16_MAX + 1), INT16_MAX,
+		      NULL);
+	zassert_equal(ec_motion_sensor_clamp_i16(INT16_MIN - 1), INT16_MIN,
+		      NULL);
+}
+
+ZTEST_USER(motion_sense, test_ec_motion_sense_get_ec_config)
+{
+	/* illegal state, should be translated to S5 */
+	sensor_active = 42;
+	zassert_equal(motion_sense_get_ec_config(), SENSOR_CONFIG_EC_S5);
+	/* all valid states */
+	sensor_active = SENSOR_ACTIVE_S0;
+	zassert_equal(motion_sense_get_ec_config(), SENSOR_CONFIG_EC_S0);
+	sensor_active = SENSOR_ACTIVE_S3;
+	zassert_equal(motion_sense_get_ec_config(), SENSOR_CONFIG_EC_S3);
+	sensor_active = SENSOR_ACTIVE_S5;
+	zassert_equal(motion_sense_get_ec_config(), SENSOR_CONFIG_EC_S5);
+}
diff --git a/zephyr/test/drivers/default/src/panic.c b/zephyr/test/drivers/default/src/panic.c
new file mode 100644
index 0000000000..a2addc786d
--- /dev/null
+++ b/zephyr/test/drivers/default/src/panic.c
@@ -0,0 +1,107 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ * @brief Unit Tests for panic.
+ */
+
+#include "common.h"
+#include "ec_tasks.h"
+#include "panic.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/device.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/ztest.h>
+
+struct panic_test_fixture {
+	struct panic_data saved_pdata;
+};
+
+static void *panic_test_setup(void)
+{
+	static struct panic_test_fixture panic_fixture = { 0 };
+
+	return &panic_fixture;
+}
+
+static void panic_before(void *state)
+{
+	struct panic_test_fixture *fixture = state;
+	struct panic_data *pdata = get_panic_data_write();
+
+	ARG_UNUSED(state);
+
+	fixture->saved_pdata = *pdata;
+}
+
+static void panic_after(void *state)
+{
+	struct panic_test_fixture *fixture = state;
+	struct panic_data *pdata = get_panic_data_write();
+
+	ARG_UNUSED(state);
+
+	*pdata = fixture->saved_pdata;
+}
+
+/**
+ * @brief Test Suite: Verifies panic functionality.
+ */
+ZTEST_SUITE(panic, drivers_predicate_post_main, panic_test_setup, panic_before,
+	    panic_after, NULL);
+
+/**
+ * @brief TestPurpose: Verify panic set/get reason.
+ *
+ * @details
+ * Validate panic set/get reason.
+ *
+ * Expected Results
+ *  - Success
+ */
+ZTEST(panic, test_panic_reason)
+{
+	uint32_t reason;
+	uint32_t info;
+	uint8_t exception;
+	struct panic_data *pdata = panic_get_data();
+
+	zassert_is_null(pdata, NULL);
+	panic_set_reason(PANIC_SW_WATCHDOG, 0, 0);
+
+	panic_get_reason(&reason, &info, &exception);
+
+	zassert_equal(PANIC_SW_WATCHDOG, reason);
+	zassert_equal(0, info);
+	zassert_equal(0, exception);
+
+	pdata = panic_get_data();
+	zassert_not_null(pdata, NULL);
+	zassert_equal(pdata->struct_version, 2);
+	zassert_equal(pdata->magic, PANIC_DATA_MAGIC);
+	zassert_equal(pdata->struct_size, CONFIG_PANIC_DATA_SIZE);
+
+	panic_data_print(pdata);
+}
+
+ZTEST(panic, test_panic_data_start_bad_magic)
+{
+	struct panic_data *pdata = get_panic_data_write();
+
+	pdata->magic = PANIC_DATA_MAGIC + 1;
+	zassert_equal(0, get_panic_data_start(), NULL);
+}
+
+ZTEST(panic, test_get_panic_data_start)
+{
+	struct panic_data *pdata = get_panic_data_write();
+
+	pdata->magic = PANIC_DATA_MAGIC;
+	zassert_equal((uintptr_t)pdata, get_panic_data_start(), NULL);
+}
diff --git a/zephyr/test/drivers/default/src/panic_output.c b/zephyr/test/drivers/default/src/panic_output.c
new file mode 100644
index 0000000000..f815744d8c
--- /dev/null
+++ b/zephyr/test/drivers/default/src/panic_output.c
@@ -0,0 +1,74 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "panic.h"
+#include "test/drivers/test_mocks.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/ztest.h>
+
+ZTEST_SUITE(panic_output, drivers_predicate_post_main, NULL, NULL, NULL, NULL);
+
+ZTEST(panic_output, test_panic_printf)
+{
+	panic_printf("test output string from %s\n", __func__);
+}
+
+ZTEST(panic_output, test_panic_puts)
+{
+	panic_puts("test output string\n");
+}
+
+ZTEST(panic_output, test_panic_sw_reason_is_valid)
+{
+	zassert_false(panic_sw_reason_is_valid(PANIC_SW_BASE - 1), NULL);
+	/* PANIC_SW_DIV_ZERO */
+	zassert_true(panic_sw_reason_is_valid(PANIC_SW_BASE), NULL);
+	/* PANIC_SW_STACK_OVERFLOW */
+	zassert_true(panic_sw_reason_is_valid(PANIC_SW_BASE + 1), NULL);
+	/* PANIC_SW_PD_CRASH */
+	zassert_true(panic_sw_reason_is_valid(PANIC_SW_BASE + 2), NULL);
+	/* PANIC_SW_ASSERT */
+	zassert_true(panic_sw_reason_is_valid(PANIC_SW_BASE + 3), NULL);
+	/* PANIC_SW_WATCHDOG */
+	zassert_true(panic_sw_reason_is_valid(PANIC_SW_BASE + 4), NULL);
+	/* PANIC_SW_RNG */
+	zassert_true(panic_sw_reason_is_valid(PANIC_SW_BASE + 5), NULL);
+	/* PANIC_SW_PMIC_FAULT */
+	zassert_true(panic_sw_reason_is_valid(PANIC_SW_BASE + 6), NULL);
+	zassert_false(panic_sw_reason_is_valid(PANIC_SW_BASE + 7), NULL);
+}
+
+ZTEST(panic_output, test_panic)
+{
+	panic(__func__);
+	zassert_equal(1, system_reset_fake.call_count,
+		      "Expected system_reset() to be called once, but was "
+		      "called %d times",
+		      system_reset_fake.call_count);
+	zassert_equal(0, system_reset_fake.arg0_val,
+		      "Expected system_reset() to be called with flags=0, but "
+		      "got flags=%d",
+		      system_reset_fake.arg0_val);
+}
+
+ZTEST(panic_output, test_panic_assert_fail)
+{
+	int line_num = __LINE__;
+
+	panic_assert_fail("Test panic message", __func__, __FILE__, line_num);
+	zassert_equal(1, software_panic_fake.call_count,
+		      "Expected sofware_panic() to be called once, but was "
+		      "called %d times",
+		      software_panic_fake.call_count);
+	zassert_equal(PANIC_SW_ASSERT, software_panic_fake.arg0_val,
+		      "Expected software_panic() to be called with "
+		      "reason=%d (PANIC_SW_ASSERT) but got %d",
+		      PANIC_SW_ASSERT, software_panic_fake.arg0_val);
+	zassert_equal(line_num, software_panic_fake.arg1_val,
+		      "Expected software_panic() to be called with "
+		      "line=%d but got %d",
+		      line_num, software_panic_fake.arg1_val);
+}
diff --git a/zephyr/test/drivers/default/src/port80.c b/zephyr/test/drivers/default/src/port80.c
new file mode 100644
index 0000000000..6bde1392c7
--- /dev/null
+++ b/zephyr/test/drivers/default/src/port80.c
@@ -0,0 +1,190 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ * @brief Unit Tests for ESPI port 80 writes
+ */
+
+#include "console.h"
+#include "ec_commands.h"
+#include "host_command.h"
+#include "port80.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+/*
+ * Flush any existing writes.
+ */
+static void port80_flush(void)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "port80 flush"), NULL);
+}
+
+/**
+ * @brief TestPurpose: Verify port 80 writes
+ *
+ * @details
+ * Validate that the port 80 writes are processed correctly.
+ *
+ * Expected Results
+ *  - The port 80 writes are received
+ */
+ZTEST(port80, test_port80_write)
+{
+	struct ec_response_port80_read response;
+	struct ec_params_port80_read params;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_PORT80_READ, 1, response, params);
+
+	port80_flush();
+	port_80_write(0x12);
+	port_80_write(0x34);
+	/* Check the buffer using the host cmd */
+
+	/* Get the buffer info */
+	params.subcmd = EC_PORT80_GET_INFO;
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_ok(args.result, NULL);
+	zassert_equal(args.response_size, sizeof(response.get_info), NULL);
+	zassert_equal(response.get_info.writes, 2, NULL);
+	/* Read the buffer */
+	params.subcmd = EC_PORT80_READ_BUFFER;
+	params.read_buffer.offset = 0;
+	params.read_buffer.num_entries = 2;
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_ok(args.result, NULL);
+	zassert_equal(args.response_size, sizeof(uint16_t) * 2, NULL);
+	zassert_equal(response.data.codes[0], 0x12, NULL);
+	zassert_equal(response.data.codes[1], 0x34, NULL);
+}
+
+/**
+ * @brief TestPurpose: Verify port 80 read parameters
+ *
+ * @details
+ * Validate that the port 80 read parameters are checked
+ *
+ * Expected Results
+ *  - The port 80 parameters are verified
+ */
+ZTEST(port80, test_port80_offset)
+{
+	struct ec_response_port80_read response;
+	struct ec_params_port80_read params;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_PORT80_READ, 1, response, params);
+
+	port80_flush();
+
+	params.subcmd = EC_PORT80_READ_BUFFER;
+	params.read_buffer.offset = 0;
+	params.read_buffer.num_entries = 0;
+	zassert_equal(host_command_process(&args), EC_RES_INVALID_PARAM, NULL);
+	params.read_buffer.offset = 0xFFFF;
+	params.read_buffer.num_entries = 2;
+	zassert_equal(host_command_process(&args), EC_RES_INVALID_PARAM, NULL);
+	params.read_buffer.offset = 0;
+	params.read_buffer.num_entries = 0xFFFF;
+	zassert_equal(host_command_process(&args), EC_RES_INVALID_PARAM, NULL);
+}
+
+/**
+ * @brief TestPurpose: Verify port 80 reset event
+ *
+ * @details
+ * Validate that the port 80 handling works for the reset event
+ *
+ * Expected Results
+ *  - The port 80 handling detects the reset event.
+ */
+ZTEST(port80, test_port80_special)
+{
+	struct ec_params_port80_read params;
+	struct ec_response_port80_last_boot response;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_PORT80_READ, 0, response, params);
+
+	port80_flush();
+	port_80_write(0xDEAD);
+	port_80_write(0xAA); /* must be < 0x100 */
+	port_80_write(PORT_80_EVENT_RESET);
+	/* Check the buffer using the host cmd version 0*/
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_ok(args.result, NULL);
+	zassert_equal(args.response_size, sizeof(response), NULL);
+	zassert_equal(response.code, 0xAA, NULL);
+}
+
+/**
+ * @brief TestPurpose: Verify port 80 subcommand
+ *
+ * @details
+ * Validate that the port 80 host subcommand is checked.
+ *
+ * Expected Results
+ *  - The port 80 handling detects an invalid subcommand.
+ */
+ZTEST(port80, test_port80_subcmd)
+{
+	struct ec_params_port80_read params;
+	struct ec_response_port80_last_boot response;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_PORT80_READ, 1, response, params);
+
+	params.subcmd = 0xFFFF;
+	zassert_ok(!host_command_process(&args), NULL);
+}
+
+/**
+ * @brief TestPurpose: Verify port 80 write wrap
+ *
+ * @details
+ * Validate that the port 80 host writes wrap around.
+ *
+ * Expected Results
+ *  - The port 80 writes overwrites the history array.
+ */
+ZTEST(port80, test_port80_wrap)
+{
+	struct ec_params_port80_read params;
+	struct ec_response_port80_read response;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_PORT80_READ, 1, response, params);
+	uint32_t size, count;
+
+	port80_flush();
+	/* Get the history array size */
+	params.subcmd = EC_PORT80_GET_INFO;
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_ok(args.result, NULL);
+	zassert_equal(args.response_size, sizeof(response.get_info), NULL);
+	size = response.get_info.history_size;
+	count = size + size / 2; /* Ensure write will wrap the history */
+	for (uint32_t i = 0; i < count; i++) {
+		port_80_write(i);
+	}
+	/*
+	 * Retrieve the first entry in the history array.
+	 * It should equal the size of the array.
+	 */
+	params.subcmd = EC_PORT80_READ_BUFFER;
+	params.read_buffer.offset = 0;
+	params.read_buffer.num_entries = 1;
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_ok(args.result, NULL);
+	zassert_equal(args.response_size, sizeof(uint16_t), NULL);
+	zassert_equal(response.data.codes[0], size, NULL);
+}
+
+/**
+ * @brief Test Suite: Verifies port 80 writes.
+ */
+ZTEST_SUITE(port80, drivers_predicate_post_main, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/drivers/default/src/power_common.c b/zephyr/test/drivers/default/src/power_common.c
new file mode 100644
index 0000000000..c5b5363aa1
--- /dev/null
+++ b/zephyr/test/drivers/default/src/power_common.c
@@ -0,0 +1,706 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "battery_smart.h"
+#include "chipset.h"
+#include "common.h"
+#include "ec_tasks.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_smart_battery.h"
+#include "extpower.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "power.h"
+#include "task.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <string.h>
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/shell/shell.h>
+#include <zephyr/shell/shell_dummy.h>
+#include <zephyr/shell/shell_uart.h>
+#include <zephyr/ztest.h>
+
+#define BATTERY_NODE DT_NODELABEL(battery)
+
+/* Description of all power states with chipset state masks */
+static struct {
+	/* Power state */
+	enum power_state p_state;
+	/*
+	 * CHIPSET_STATE_* to which this state transition (the same as
+	 * transition_from for static states)
+	 */
+	int transition_to;
+	/* CHIPSET_STATE_* from which this state transition */
+	int transition_from;
+} test_power_state_desc[] = {
+	{
+		.p_state = POWER_G3,
+		.transition_to = CHIPSET_STATE_HARD_OFF,
+		.transition_from = CHIPSET_STATE_HARD_OFF,
+	},
+	{
+		.p_state = POWER_G3S5,
+		.transition_to = CHIPSET_STATE_SOFT_OFF,
+		.transition_from = CHIPSET_STATE_HARD_OFF,
+	},
+	{
+		.p_state = POWER_S5G3,
+		.transition_to = CHIPSET_STATE_HARD_OFF,
+		.transition_from = CHIPSET_STATE_SOFT_OFF,
+	},
+	{
+		.p_state = POWER_S5,
+		.transition_to = CHIPSET_STATE_SOFT_OFF,
+		.transition_from = CHIPSET_STATE_SOFT_OFF,
+	},
+	{
+		.p_state = POWER_S5S3,
+		.transition_to = CHIPSET_STATE_SUSPEND,
+		.transition_from = CHIPSET_STATE_SOFT_OFF,
+	},
+	{
+		.p_state = POWER_S3S5,
+		.transition_to = CHIPSET_STATE_SOFT_OFF,
+		.transition_from = CHIPSET_STATE_SUSPEND,
+	},
+	{
+		.p_state = POWER_S3,
+		.transition_to = CHIPSET_STATE_SUSPEND,
+		.transition_from = CHIPSET_STATE_SUSPEND,
+	},
+	{
+		.p_state = POWER_S3S0,
+		.transition_to = CHIPSET_STATE_ON,
+		.transition_from = CHIPSET_STATE_SUSPEND,
+	},
+	{
+		.p_state = POWER_S0S3,
+		.transition_to = CHIPSET_STATE_SUSPEND,
+		.transition_from = CHIPSET_STATE_ON,
+	},
+	{
+		.p_state = POWER_S0,
+		.transition_to = CHIPSET_STATE_ON,
+		.transition_from = CHIPSET_STATE_ON,
+	},
+};
+
+/*
+ * Chipset state masks used by chipset_in_state and
+ * chipset_in_or_transitioning_to_state tests
+ */
+static int in_state_test_masks[] = {
+	CHIPSET_STATE_HARD_OFF,
+	CHIPSET_STATE_SOFT_OFF,
+	CHIPSET_STATE_SUSPEND,
+	CHIPSET_STATE_ON,
+	CHIPSET_STATE_STANDBY,
+	CHIPSET_STATE_ANY_OFF,
+	CHIPSET_STATE_ANY_SUSPEND,
+	CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_SOFT_OFF,
+};
+
+/** Test chipset_in_state() for each state */
+ZTEST(power_common_no_tasks, test_power_chipset_in_state)
+{
+	bool expected_in_state;
+	bool transition_from;
+	bool transition_to;
+	bool in_state;
+	int mask;
+
+	for (int i = 0; i < ARRAY_SIZE(test_power_state_desc); i++) {
+		/* Set given power state */
+		power_set_state(test_power_state_desc[i].p_state);
+		/* Test with selected state masks */
+		for (int j = 0; j < ARRAY_SIZE(in_state_test_masks); j++) {
+			mask = in_state_test_masks[j];
+			/*
+			 * Currently tested mask match with state if it match
+			 * with transition_to and from chipset states
+			 */
+			transition_to = mask &
+					test_power_state_desc[i].transition_to;
+			transition_from =
+				mask & test_power_state_desc[i].transition_from;
+			expected_in_state = transition_to && transition_from;
+			in_state = chipset_in_state(mask);
+			zassert_equal(expected_in_state, in_state,
+				      "Wrong chipset_in_state() == %d, "
+				      "should be %d; mask 0x%x; power state %d "
+				      "in test case %d",
+				      in_state, expected_in_state, mask,
+				      test_power_state_desc[i].p_state, i);
+		}
+	}
+}
+
+/** Test chipset_in_or_transitioning_to_state() for each state */
+ZTEST(power_common_no_tasks, test_power_chipset_in_or_transitioning_to_state)
+{
+	bool expected_in_state;
+	bool in_state;
+	int mask;
+
+	for (int i = 0; i < ARRAY_SIZE(test_power_state_desc); i++) {
+		/* Set given power state */
+		power_set_state(test_power_state_desc[i].p_state);
+		/* Test with selected state masks */
+		for (int j = 0; j < ARRAY_SIZE(in_state_test_masks); j++) {
+			mask = in_state_test_masks[j];
+			/*
+			 * Currently tested mask match with state if it match
+			 * with transition_to chipset state
+			 */
+			expected_in_state =
+				mask & test_power_state_desc[i].transition_to;
+			in_state = chipset_in_or_transitioning_to_state(mask);
+			zassert_equal(expected_in_state, in_state,
+				      "Wrong "
+				      "chipset_in_or_transitioning_to_state() "
+				      "== %d, should be %d; mask 0x%x; "
+				      "power state %d in test case %d",
+				      in_state, expected_in_state, mask,
+				      test_power_state_desc[i].p_state, i);
+		}
+	}
+}
+
+/* Test using chipset_exit_hard_off() in different power states. The only
+ * way to test the value of want_g3_exit is to set the power state to G3
+ * and then to see if test_power_common_state() transitions to G3S5 or not.
+ */
+ZTEST(power_common_no_tasks, test_power_exit_hard_off)
+{
+	/*
+	 * Every test runs in a new thread, we need to add this thread to the
+	 * dynamic shimmed tasks or this test will fail.
+	 */
+	set_test_runner_tid();
+
+	/* Force initial state */
+	power_set_state(POWER_G3);
+	test_power_common_state();
+	zassert_equal(POWER_G3, power_get_state());
+
+	/* Test after exit hard off, we reach G3S5 */
+	chipset_exit_hard_off();
+	test_power_common_state();
+	zassert_equal(POWER_G3S5, power_get_state());
+
+	/* Go back to G3 and check we stay there */
+	power_set_state(POWER_G3);
+	test_power_common_state();
+	zassert_equal(POWER_G3, power_get_state());
+
+	/* Exit G3 again */
+	chipset_exit_hard_off();
+	test_power_common_state();
+	zassert_equal(POWER_G3S5, power_get_state());
+
+	/* Go to S5G3 */
+	power_set_state(POWER_S5G3);
+	test_power_common_state();
+	zassert_equal(POWER_S5G3, power_get_state());
+
+	/* Test exit hard off in S5G3 -- should set want_g3_exit */
+	chipset_exit_hard_off();
+	/* Go back to G3 and check we exit it to G3S5 */
+	power_set_state(POWER_G3);
+	test_power_common_state();
+	zassert_equal(POWER_G3S5, power_get_state());
+
+	/* Test exit hard off is cleared on entering S5 */
+	chipset_exit_hard_off();
+	power_set_state(POWER_S5);
+	test_power_common_state();
+	zassert_equal(POWER_S5, power_get_state());
+
+	/* Go back to G3 and check we stay in G3 */
+	power_set_state(POWER_G3);
+	test_power_common_state();
+	zassert_equal(POWER_G3, power_get_state());
+
+	/* Test exit hard off doesn't work on other states */
+	power_set_state(POWER_S5S3);
+	test_power_common_state();
+	zassert_equal(POWER_S5S3, power_get_state());
+	chipset_exit_hard_off();
+	test_power_common_state();
+
+	/* Go back to G3 and check we stay in G3 */
+	power_set_state(POWER_G3);
+	test_power_common_state();
+	zassert_equal(POWER_G3, power_get_state());
+}
+
+/* Test reboot ap on g3 host command is triggering reboot */
+ZTEST(power_common_no_tasks, test_power_reboot_ap_at_g3)
+{
+	struct ec_params_reboot_ap_on_g3_v1 params;
+	int delay_ms;
+	int64_t before_time;
+
+	/*
+	 * Every test runs in a new thread, we need to add this thread to the
+	 * dynamic shimmed tasks or this test will fail.
+	 */
+	set_test_runner_tid();
+
+	/* Force initial state S0 */
+	power_set_state(POWER_S0);
+	test_power_common_state();
+	zassert_equal(POWER_S0, power_get_state());
+
+	/* Test version 0 (no delay argument) */
+	zassert_equal(EC_RES_SUCCESS, ec_cmd_reboot_ap_on_g3(NULL));
+
+	/* Go to G3 and check if reboot is triggered */
+	power_set_state(POWER_G3);
+	test_power_common_state();
+	zassert_equal(POWER_G3S5, power_get_state());
+
+	/* Test version 1 (with delay argument) */
+	delay_ms = 3000;
+	params.reboot_ap_at_g3_delay = delay_ms / 1000; /* in seconds */
+	zassert_equal(EC_RES_SUCCESS, ec_cmd_reboot_ap_on_g3_v1(NULL, &params));
+
+	/* Go to G3 and check if reboot is triggered after delay */
+	power_set_state(POWER_G3);
+	before_time = k_uptime_get();
+	test_power_common_state();
+	zassert_true(k_uptime_delta(&before_time) >= 3000);
+	zassert_equal(POWER_G3S5, power_get_state());
+}
+
+/** Test setting cutoff and stay-up battery levels through host command */
+ZTEST(power_common, test_power_hc_smart_discharge)
+{
+	struct ec_response_smart_discharge response;
+	struct ec_params_smart_discharge params;
+	const struct emul *emul = EMUL_DT_GET(BATTERY_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_smart_battery_get_i2c_common_data(emul);
+	int hours_to_zero;
+	int hibern_drate;
+	int cutoff_drate;
+	int stayup_cap;
+	int cutoff_cap;
+
+	/* Set up host command parameters */
+	params.flags = EC_SMART_DISCHARGE_FLAGS_SET;
+
+	/* Test fail when battery capacity is not available */
+	i2c_common_emul_set_read_fail_reg(common_data, SB_FULL_CHARGE_CAPACITY);
+	zassert_equal(EC_RES_UNAVAILABLE,
+		      ec_cmd_smart_discharge(NULL, &params, &response));
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Setup discharge rates */
+	params.drate.hibern = 10;
+	params.drate.cutoff = 100;
+	/* Test fail on higher discahrge in hibernation than cutoff */
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      ec_cmd_smart_discharge(NULL, &params, &response));
+
+	/* Setup discharge rates */
+	params.drate.hibern = 10;
+	params.drate.cutoff = 0;
+	/* Test fail on only one discharge rate set to 0 */
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      ec_cmd_smart_discharge(NULL, &params, &response));
+
+	/* Setup correct parameters */
+	hours_to_zero = 1000;
+	hibern_drate = 100; /* uA */
+	cutoff_drate = 10; /* uA */
+	/* Need at least 100 mA capacity to stay 1000h using 0.1mAh */
+	stayup_cap = hibern_drate * hours_to_zero / 1000;
+	/* Need at least 10 mA capacity to stay 1000h using 0.01mAh */
+	cutoff_cap = cutoff_drate * hours_to_zero / 1000;
+
+	params.drate.hibern = hibern_drate;
+	params.drate.cutoff = cutoff_drate;
+	params.hours_to_zero = hours_to_zero;
+
+	/* Test if correct values are set */
+	zassert_equal(EC_RES_SUCCESS,
+		      ec_cmd_smart_discharge(NULL, &params, &response));
+	zassert_equal(hibern_drate, response.drate.hibern);
+	zassert_equal(cutoff_drate, response.drate.cutoff);
+	zassert_equal(hours_to_zero, response.hours_to_zero);
+	zassert_equal(stayup_cap, response.dzone.stayup);
+	zassert_equal(cutoff_cap, response.dzone.cutoff);
+
+	/* Setup discharge rate to 0 */
+	params.drate.hibern = 0;
+	params.drate.cutoff = 0;
+	/* Update hours to zero */
+	hours_to_zero = 2000;
+	params.hours_to_zero = hours_to_zero;
+	/* Need at least 200 mA capacity to stay 2000h using 0.1mAh */
+	stayup_cap = hibern_drate * hours_to_zero / 1000;
+	/* Need at least 20 mA capacity to stay 2000h using 0.01mAh */
+	cutoff_cap = cutoff_drate * hours_to_zero / 1000;
+
+	/* Test that command doesn't change drate but apply new hours to zero */
+	zassert_equal(EC_RES_SUCCESS,
+		      ec_cmd_smart_discharge(NULL, &params, &response));
+	zassert_equal(hibern_drate, response.drate.hibern);
+	zassert_equal(cutoff_drate, response.drate.cutoff);
+	zassert_equal(hours_to_zero, response.hours_to_zero);
+	zassert_equal(stayup_cap, response.dzone.stayup);
+	zassert_equal(cutoff_cap, response.dzone.cutoff);
+
+	/* Setup any parameters != 0 */
+	params.drate.hibern = 1000;
+	params.drate.cutoff = 1000;
+	/* Clear set flag */
+	params.flags = 0;
+
+	/* Test that command doesn't change drate and dzone */
+	zassert_equal(EC_RES_SUCCESS,
+		      ec_cmd_smart_discharge(NULL, &params, &response));
+	zassert_equal(hibern_drate, response.drate.hibern);
+	zassert_equal(cutoff_drate, response.drate.cutoff);
+	zassert_equal(hours_to_zero, response.hours_to_zero);
+	zassert_equal(stayup_cap, response.dzone.stayup);
+	zassert_equal(cutoff_cap, response.dzone.cutoff);
+}
+
+/**
+ * Test if default board_system_is_idle() recognize cutoff and stay-up
+ * levels correctly.
+ */
+ZTEST(power_common, test_power_board_system_is_idle)
+{
+	struct ec_response_smart_discharge response;
+	struct ec_params_smart_discharge params;
+	struct sbat_emul_bat_data *bat;
+	const struct emul *emul = EMUL_DT_GET(BATTERY_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_smart_battery_get_i2c_common_data(emul);
+	uint64_t last_shutdown_time = 0;
+	uint64_t target;
+	uint64_t now;
+
+	bat = sbat_emul_get_bat_data(emul);
+
+	/* Set up host command parameters */
+	params.drate.hibern = 100; /* uA */
+	params.drate.cutoff = 10; /* uA */
+	params.hours_to_zero = 1000; /* h */
+	params.flags = EC_SMART_DISCHARGE_FLAGS_SET;
+	/* Set stay-up and cutoff zones */
+	zassert_equal(EC_RES_SUCCESS,
+		      ec_cmd_smart_discharge(NULL, &params, &response));
+
+	/* Test shutdown ignore is send when target time is in future */
+	target = 1125;
+	now = 1000;
+	zassert_equal(CRITICAL_SHUTDOWN_IGNORE,
+		      board_system_is_idle(last_shutdown_time, &target, now),
+		      NULL);
+
+	/* Set "now" time after target time */
+	now = target + 30;
+
+	/*
+	 * Test hibernation is requested when battery remaining capacity
+	 * is not available
+	 */
+	i2c_common_emul_set_read_fail_reg(common_data, SB_REMAINING_CAPACITY);
+	zassert_equal(CRITICAL_SHUTDOWN_HIBERNATE,
+		      board_system_is_idle(last_shutdown_time, &target, now),
+		      NULL);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Setup remaining capacity to trigger cutoff */
+	bat->cap = response.dzone.cutoff - 5;
+	zassert_equal(CRITICAL_SHUTDOWN_CUTOFF,
+		      board_system_is_idle(last_shutdown_time, &target, now),
+		      NULL);
+
+	/* Setup remaining capacity to trigger stay-up and ignore shutdown */
+	bat->cap = response.dzone.stayup - 5;
+	zassert_equal(CRITICAL_SHUTDOWN_IGNORE,
+		      board_system_is_idle(last_shutdown_time, &target, now),
+		      NULL);
+
+	/* Setup remaining capacity to be in safe zone to hibernate */
+	bat->cap = response.dzone.stayup + 5;
+	zassert_equal(CRITICAL_SHUTDOWN_HIBERNATE,
+		      board_system_is_idle(last_shutdown_time, &target, now),
+		      NULL);
+}
+
+/**
+ * Test power console command
+ */
+ZTEST(power_common, test_power_console_cmd)
+{
+	const char *buffer;
+	size_t buffer_size;
+
+	test_set_chipset_to_g3();
+	shell_backend_dummy_clear_output(get_ec_shell());
+	zassert_equal(EC_SUCCESS, shell_execute_cmd(get_ec_shell(), "power"),
+		      NULL);
+	buffer = shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+	zassert_true(strcmp(buffer, "\r\noff\r\n") == 0 ||
+			     strcmp(buffer, "\r\nOFF\r\n") == 0,
+		     "Invalid console output %s", buffer);
+
+	test_set_chipset_to_s0();
+	shell_backend_dummy_clear_output(get_ec_shell());
+	zassert_equal(EC_SUCCESS, shell_execute_cmd(get_ec_shell(), "power"),
+		      NULL);
+	buffer = shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+	zassert_true(strcmp(buffer, "\r\non\r\n") == 0 ||
+			     strcmp(buffer, "\r\nON\r\n") == 0,
+		     "Invalid console output %s", buffer);
+
+	zassert_equal(EC_ERROR_PARAM1,
+		      shell_execute_cmd(get_ec_shell(), "power x"), NULL);
+
+	zassert_equal(EC_SUCCESS, shell_execute_cmd(get_ec_shell(), "power on"),
+		      NULL);
+
+	zassert_equal(EC_SUCCESS,
+		      shell_execute_cmd(get_ec_shell(), "power off"), NULL);
+}
+
+/**
+ * Test powerinfo console command
+ */
+ZTEST_USER(power_common, test_powerinfo_console_cmd)
+{
+	char expected_buffer[32];
+
+	snprintf(expected_buffer, sizeof(expected_buffer), "power state %d",
+		 power_get_state());
+
+	CHECK_CONSOLE_CMD("powerinfo", expected_buffer, EC_SUCCESS);
+}
+
+/**
+ * Common setup for hibernation delay tests. Smart discharge zone is setup,
+ * battery is set in safe zone (which trigger hibernation), power state is
+ * set to G3 and AC is disabled. system_hibernate mock is reset.
+ */
+static void setup_hibernation_delay(void *state)
+{
+	struct ec_response_smart_discharge response;
+	struct ec_params_smart_discharge params;
+	struct sbat_emul_bat_data *bat;
+	const struct emul *emul = EMUL_DT_GET(BATTERY_NODE);
+	ARG_UNUSED(state);
+
+	bat = sbat_emul_get_bat_data(emul);
+
+	/* Setup smart discharge zone and set capacity to safe zone */
+	params.drate.hibern = 100; /* uA */
+	params.drate.cutoff = 10; /* uA */
+	params.hours_to_zero = 10000; /* h */
+	params.flags = EC_SMART_DISCHARGE_FLAGS_SET;
+	zassert_equal(EC_RES_SUCCESS,
+		      ec_cmd_smart_discharge(NULL, &params, &response));
+	/*
+	 * Make sure that battery is in safe zone in good condition to
+	 * not trigger hibernate in charge_state.c
+	 */
+	bat->cap = response.dzone.stayup + 5;
+	bat->volt = battery_get_info()->voltage_normal;
+
+	/* Force initial state */
+	test_set_chipset_to_g3();
+
+	/* Disable AC */
+	set_ac_enabled(false);
+
+	RESET_FAKE(system_hibernate);
+}
+
+/** Test setting hibernation delay through host command */
+ZTEST(power_common_hibernation, test_power_hc_hibernation_delay)
+{
+	struct ec_response_hibernation_delay response;
+	struct ec_params_hibernation_delay params;
+	uint32_t h_delay;
+	int sleep_time;
+
+	/* Ensure the lid is closed so AC connect does not boot system */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "lidclose"));
+
+	zassert_equal(power_get_state(), POWER_G3,
+		      "Power state is %d, expected G3", power_get_state());
+	/* This is a no-op, but it will reset the last_shutdown_time. */
+	power_set_state(POWER_G3);
+
+	/* Set hibernate delay */
+	h_delay = 9;
+	params.seconds = h_delay;
+	zassert_equal(EC_RES_SUCCESS,
+		      ec_cmd_hibernation_delay(NULL, &params, &response));
+
+	zassert_equal(0, response.time_g3, "Time from last G3 enter %d != 0",
+		      response.time_g3);
+	zassert_equal(h_delay, response.time_remaining,
+		      "Time to hibernation %d != %d", response.time_remaining,
+		      h_delay);
+	zassert_equal(h_delay, response.hibernate_delay,
+		      "Hibernation delay %d != %d", h_delay,
+		      response.hibernate_delay);
+
+	/* Kick chipset task to process new hibernation delay */
+	task_wake(TASK_ID_CHIPSET);
+	/* Wait some arbitrary time less than hibernate delay */
+	sleep_time = 6;
+	k_msleep(sleep_time * 1000);
+
+	/* Get hibernate delay */
+	params.seconds = 0;
+	zassert_equal(EC_RES_SUCCESS,
+		      ec_cmd_hibernation_delay(NULL, &params, &response));
+
+	zassert_equal(sleep_time, response.time_g3,
+		      "Time from last G3 enter %d != %d", response.time_g3,
+		      sleep_time);
+	zassert_equal(h_delay - sleep_time, response.time_remaining,
+		      "Time to hibernation %d != %d", response.time_remaining,
+		      h_delay - sleep_time);
+	zassert_equal(h_delay, response.hibernate_delay,
+		      "Hibernation delay %d != %d", h_delay,
+		      response.hibernate_delay);
+	zassert_equal(0, system_hibernate_fake.call_count,
+		      "system_hibernate() shouldn't be called before delay");
+
+	/* Wait to end of the hibenate delay */
+	k_msleep((h_delay - sleep_time) * 1000);
+
+	/* Get hibernate delay */
+	params.seconds = 0;
+	zassert_equal(EC_RES_SUCCESS,
+		      ec_cmd_hibernation_delay(NULL, &params, &response));
+
+	zassert_equal(h_delay, response.time_g3,
+		      "Time from last G3 enter %d != %d", response.time_g3,
+		      h_delay);
+	zassert_equal(0, response.time_remaining, "Time to hibernation %d != 0",
+		      response.time_remaining);
+	zassert_equal(h_delay, response.hibernate_delay,
+		      "Hibernation delay %d != %d", h_delay,
+		      response.hibernate_delay);
+	zassert_equal(1, system_hibernate_fake.call_count,
+		      "system_hibernate() should be called after delay %d",
+		      system_hibernate_fake.call_count);
+
+	/* Wait some more time */
+	k_msleep(2000);
+
+	/* Get hibernate delay */
+	params.seconds = 0;
+	zassert_equal(EC_RES_SUCCESS,
+		      ec_cmd_hibernation_delay(NULL, &params, &response));
+
+	/* After hibernation, remaining time shouldn't be negative */
+	zassert_equal(0, response.time_remaining, "Time to hibernation %d != 0",
+		      response.time_remaining);
+
+	/* Enable AC */
+	set_ac_enabled(true);
+
+	/* Reset system_hibernate fake to check that it is not called on AC */
+	RESET_FAKE(system_hibernate);
+	/* Allow chipset task to spin with enabled AC */
+	task_wake(TASK_ID_CHIPSET);
+	k_msleep(1);
+
+	/* Get hibernate delay */
+	params.seconds = 0;
+	zassert_equal(EC_RES_SUCCESS,
+		      ec_cmd_hibernation_delay(NULL, &params, &response));
+
+	zassert_equal(0, response.time_g3,
+		      "Time from last G3 enter %d should be 0 on AC",
+		      response.time_g3);
+	zassert_equal(0, system_hibernate_fake.call_count,
+		      "system_hibernate() shouldn't be called on AC");
+
+	/* Disable AC */
+	set_ac_enabled(false);
+
+	/* Go to different state */
+	power_set_state(POWER_G3S5);
+	zassert_equal(POWER_G3S5, power_get_state());
+
+	/* Get hibernate delay */
+	params.seconds = 0;
+	zassert_equal(EC_RES_SUCCESS,
+		      ec_cmd_hibernation_delay(NULL, &params, &response));
+
+	zassert_equal(0, response.time_g3,
+		      "Time from last G3 enter %d should be 0 on state != G3",
+		      response.time_g3);
+}
+
+/** Test setting hibernation delay through UART command */
+ZTEST(power_common_hibernation, test_power_cmd_hibernation_delay)
+{
+	uint32_t h_delay;
+	int sleep_time;
+
+	zassert_equal(power_get_state(), POWER_G3,
+		      "Power state is %d, expected G3", power_get_state());
+	/* This is a no-op, but it will reset the last_shutdown_time. */
+	power_set_state(POWER_G3);
+
+	/* Test success on call without argument */
+	zassert_equal(EC_SUCCESS, shell_execute_cmd(get_ec_shell(), "hibdelay"),
+		      NULL);
+
+	/* Test error on hibernation delay argument that is not a number */
+	zassert_equal(EC_ERROR_PARAM1,
+		      shell_execute_cmd(get_ec_shell(), "hibdelay test1"),
+		      NULL);
+
+	/* Set hibernate delay */
+	h_delay = 3;
+	zassert_equal(EC_SUCCESS,
+		      shell_execute_cmd(get_ec_shell(), "hibdelay 3"), NULL);
+
+	/* Kick chipset task to process new hibernation delay */
+	task_wake(TASK_ID_CHIPSET);
+	/* Wait some arbitrary time less than hibernate delay */
+	sleep_time = 2;
+	k_msleep(sleep_time * 1000);
+
+	zassert_equal(0, system_hibernate_fake.call_count,
+		      "system_hibernate() shouldn't be called before delay");
+
+	/* Wait to end of the hibenate delay */
+	k_msleep((h_delay - sleep_time) * 1000);
+
+	zassert_equal(1, system_hibernate_fake.call_count,
+		      "system_hibernate() should be called after delay %d",
+		      system_hibernate_fake.call_count);
+}
+
+ZTEST_SUITE(power_common_no_tasks, drivers_predicate_pre_main, NULL, NULL, NULL,
+	    NULL);
+
+ZTEST_SUITE(power_common, drivers_predicate_post_main, NULL, NULL, NULL, NULL);
+
+ZTEST_SUITE(power_common_hibernation, drivers_predicate_post_main, NULL,
+	    setup_hibernation_delay, NULL, NULL);
diff --git a/zephyr/test/drivers/default/src/ppc_sn5s330.c b/zephyr/test/drivers/default/src/ppc_sn5s330.c
new file mode 100644
index 0000000000..664d9fed36
--- /dev/null
+++ b/zephyr/test/drivers/default/src/ppc_sn5s330.c
@@ -0,0 +1,689 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/ppc/sn5s330.h"
+#include "driver/ppc/sn5s330_public.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_sn5s330.h"
+#include "test/drivers/test_mocks.h"
+#include "test/drivers/test_state.h"
+#include "usbc_ppc.h"
+
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/fff.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+/** This must match the index of the sn5s330 in ppc_chips[] */
+#define SN5S330_PORT 0
+#define EMUL EMUL_DT_GET(DT_NODELABEL(sn5s330_emul))
+#define COMMON_DATA emul_sn5s330_get_i2c_common_data(EMUL)
+#define FUNC_SET1_ILIMPP1_MSK 0x1F
+#define SN5S330_INTERRUPT_DELAYMS 15
+
+FAKE_VOID_FUNC(sn5s330_emul_interrupt_set_stub);
+
+/*
+ * TODO(b/203364783): Exclude other threads from interacting with the emulator
+ * to avoid test flakiness
+ */
+
+struct intercept_write_data {
+	int reg_to_intercept;
+	uint8_t val_intercepted;
+};
+
+struct intercept_read_data {
+	int reg_to_intercept;
+	bool replace_reg_val;
+	uint8_t replacement_val;
+};
+
+static int intercept_read_func(const struct emul *emul, int reg, uint8_t *val,
+			       int bytes, void *data)
+{
+	struct intercept_read_data *test_data = data;
+
+	if (test_data->reg_to_intercept && test_data->replace_reg_val)
+		*val = test_data->replacement_val;
+
+	return EC_SUCCESS;
+}
+
+static int intercept_write_func(const struct emul *emul, int reg, uint8_t val,
+				int bytes, void *data)
+{
+	struct intercept_write_data *test_data = data;
+
+	if (test_data->reg_to_intercept == reg)
+		test_data->val_intercepted = val;
+
+	return 1;
+}
+
+static int fail_until_write_func(const struct emul *emul, int reg, uint8_t val,
+				 int bytes, void *data)
+{
+	uint32_t *count = data;
+
+	if (*count != 0) {
+		*count -= 1;
+		return -EIO;
+	}
+	return 1;
+}
+
+ZTEST(ppc_sn5s330, test_fail_once_func_set1)
+{
+	const struct emul *emul = EMUL;
+	uint32_t count = 1;
+	uint8_t func_set1_value;
+
+	i2c_common_emul_set_write_func(COMMON_DATA, fail_until_write_func,
+				       &count);
+
+	zassert_ok(sn5s330_drv.init(SN5S330_PORT));
+	zassert_equal(count, 0);
+	sn5s330_emul_peek_reg(emul, SN5S330_FUNC_SET1, &func_set1_value);
+	zassert_true((func_set1_value & SN5S330_ILIM_1_62) != 0);
+	i2c_common_emul_set_write_func(COMMON_DATA, NULL, NULL);
+}
+
+ZTEST(ppc_sn5s330, test_dead_battery_boot_force_pp2_fets_set)
+{
+	struct intercept_write_data test_write_data = {
+		.reg_to_intercept = SN5S330_FUNC_SET3,
+		.val_intercepted = 0,
+	};
+	struct intercept_read_data test_read_data = {
+		.reg_to_intercept = SN5S330_INT_STATUS_REG4,
+		.replace_reg_val = true,
+		.replacement_val = SN5S330_DB_BOOT,
+	};
+
+	i2c_common_emul_set_write_func(COMMON_DATA, intercept_write_func,
+				       &test_write_data);
+	i2c_common_emul_set_read_func(COMMON_DATA, intercept_read_func,
+				      &test_read_data);
+
+	zassert_ok(sn5s330_drv.init(SN5S330_PORT));
+
+	/*
+	 * Although the device enables PP2_FET on dead battery boot by setting
+	 * the PP2_EN bit, the driver also force sets this bit during dead
+	 * battery boot by writing that bit to the FUNC_SET3 reg.
+	 *
+	 * TODO(b/207034759): Verify need or remove redundant PP2 set.
+	 */
+	zassert_true(test_write_data.val_intercepted & SN5S330_PP2_EN);
+	zassert_false(sn5s330_drv.is_sourcing_vbus(SN5S330_PORT));
+}
+
+ZTEST(ppc_sn5s330, test_enter_low_power_mode)
+{
+	const struct emul *emul = EMUL;
+
+	uint8_t func_set2_reg;
+	uint8_t func_set3_reg;
+	uint8_t func_set4_reg;
+	uint8_t func_set9_reg;
+
+	/*
+	 * Requirements were extracted from TI's recommended changes for octopus
+	 * to lower power use during hibernate as well as the follow up changes
+	 * we made to allow the device to wake up from hibernate.
+	 *
+	 * For Reference: b/111006203#comment35
+	 */
+
+	zassert_ok(sn5s330_drv.init(SN5S330_PORT));
+	zassert_ok(sn5s330_drv.enter_low_power_mode(SN5S330_PORT));
+
+	/* 1) Verify VBUS power paths are off */
+	sn5s330_emul_peek_reg(emul, SN5S330_FUNC_SET3, &func_set3_reg);
+	zassert_equal(func_set3_reg & SN5S330_PP1_EN, 0);
+	zassert_equal(func_set3_reg & SN5S330_PP2_EN, 0);
+
+	/* 2) Verify VCONN power path is off */
+	sn5s330_emul_peek_reg(emul, SN5S330_FUNC_SET4, &func_set4_reg);
+	zassert_not_equal(func_set4_reg & SN5S330_CC_EN, 0, NULL);
+	zassert_equal(func_set4_reg & SN5S330_VCONN_EN, 0);
+
+	/* 3) Verify SBU FET is off */
+	sn5s330_emul_peek_reg(emul, SN5S330_FUNC_SET2, &func_set2_reg);
+	zassert_equal(func_set2_reg & SN5S330_SBU_EN, 0);
+
+	/* 4) Verify VBUS and SBU OVP comparators are off */
+	sn5s330_emul_peek_reg(emul, SN5S330_FUNC_SET9, &func_set9_reg);
+	zassert_equal(func_set9_reg & SN5S330_FORCE_OVP_EN_SBU, 0);
+	zassert_equal(func_set9_reg & SN5S330_PWR_OVR_VBUS, 0);
+	zassert_not_equal(func_set9_reg & SN5S330_OVP_EN_CC, 0, NULL);
+	zassert_equal(func_set9_reg & SN5S330_FORCE_ON_VBUS_OVP, 0);
+	zassert_equal(func_set9_reg & SN5S330_FORCE_ON_VBUS_UVP, 0);
+}
+
+ZTEST(ppc_sn5s330, test_vbus_source_sink_enable)
+{
+	const struct emul *emul = EMUL;
+	uint8_t func_set3_reg;
+
+	zassert_ok(sn5s330_drv.init(SN5S330_PORT));
+
+	/* Test enable/disable VBUS source FET */
+	zassert_ok(sn5s330_drv.vbus_source_enable(SN5S330_PORT, true));
+	sn5s330_emul_peek_reg(emul, SN5S330_FUNC_SET3, &func_set3_reg);
+	zassert_not_equal(func_set3_reg & SN5S330_PP1_EN, 0, NULL);
+
+	zassert_ok(sn5s330_drv.vbus_source_enable(SN5S330_PORT, false));
+	sn5s330_emul_peek_reg(emul, SN5S330_FUNC_SET3, &func_set3_reg);
+	zassert_equal(func_set3_reg & SN5S330_PP1_EN, 0);
+
+	/* Test enable/disable VBUS sink FET */
+	zassert_ok(sn5s330_drv.vbus_sink_enable(SN5S330_PORT, true));
+	sn5s330_emul_peek_reg(emul, SN5S330_FUNC_SET3, &func_set3_reg);
+	zassert_not_equal(func_set3_reg & SN5S330_PP2_EN, 0, NULL);
+
+	zassert_ok(sn5s330_drv.vbus_sink_enable(SN5S330_PORT, false));
+	sn5s330_emul_peek_reg(emul, SN5S330_FUNC_SET3, &func_set3_reg);
+	zassert_equal(func_set3_reg & SN5S330_PP2_EN, 0);
+}
+
+/* This test depends on EC GIPO initialization happening before I2C */
+BUILD_ASSERT(CONFIG_PLATFORM_EC_GPIO_INIT_PRIORITY < CONFIG_I2C_INIT_PRIORITY,
+	     "GPIO initialization must happen before I2C");
+ZTEST(ppc_sn5s330, test_vbus_discharge)
+{
+	const struct emul *emul = EMUL;
+	uint8_t func_set3_reg;
+
+	zassert_ok(sn5s330_drv.init(SN5S330_PORT));
+
+	/* Test enable/disable VBUS discharging */
+	zassert_ok(sn5s330_drv.discharge_vbus(SN5S330_PORT, true));
+	sn5s330_emul_peek_reg(emul, SN5S330_FUNC_SET3, &func_set3_reg);
+	zassert_not_equal(func_set3_reg & SN5S330_VBUS_DISCH_EN, 0, NULL);
+
+	zassert_ok(sn5s330_drv.discharge_vbus(SN5S330_PORT, false));
+	sn5s330_emul_peek_reg(emul, SN5S330_FUNC_SET3, &func_set3_reg);
+	zassert_equal(func_set3_reg & SN5S330_VBUS_DISCH_EN, 0);
+}
+
+ZTEST(ppc_sn5s330, test_set_vbus_source_current_limit)
+{
+	const struct emul *emul = EMUL;
+	uint8_t func_set1_reg;
+
+	/* Test every TCPC Pull Resistance Value */
+	zassert_ok(sn5s330_drv.init(SN5S330_PORT));
+
+	/* USB */
+	zassert_ok(sn5s330_drv.set_vbus_source_current_limit(SN5S330_PORT,
+							     TYPEC_RP_USB),
+		   NULL);
+	sn5s330_emul_peek_reg(emul, SN5S330_FUNC_SET1, &func_set1_reg);
+	zassert_equal(func_set1_reg & FUNC_SET1_ILIMPP1_MSK, SN5S330_ILIM_0_63,
+		      NULL);
+
+	/* 1.5A */
+	zassert_ok(sn5s330_drv.set_vbus_source_current_limit(SN5S330_PORT,
+							     TYPEC_RP_1A5),
+		   NULL);
+	sn5s330_emul_peek_reg(emul, SN5S330_FUNC_SET1, &func_set1_reg);
+	zassert_equal(func_set1_reg & FUNC_SET1_ILIMPP1_MSK, SN5S330_ILIM_1_62,
+		      NULL);
+
+	/* 3.0A */
+	zassert_ok(sn5s330_drv.set_vbus_source_current_limit(SN5S330_PORT,
+							     TYPEC_RP_3A0),
+		   NULL);
+	sn5s330_emul_peek_reg(emul, SN5S330_FUNC_SET1, &func_set1_reg);
+	zassert_equal(func_set1_reg & FUNC_SET1_ILIMPP1_MSK, SN5S330_ILIM_3_06,
+		      NULL);
+
+	/* Unknown/Reserved - We set result as USB */
+	zassert_ok(sn5s330_drv.set_vbus_source_current_limit(SN5S330_PORT,
+							     TYPEC_RP_RESERVED),
+		   NULL);
+	sn5s330_emul_peek_reg(emul, SN5S330_FUNC_SET1, &func_set1_reg);
+	zassert_equal(func_set1_reg & FUNC_SET1_ILIMPP1_MSK, SN5S330_ILIM_0_63,
+		      NULL);
+}
+
+ZTEST(ppc_sn5s330, test_sn5s330_set_sbu)
+#ifdef CONFIG_USBC_PPC_SBU
+{
+	const struct emul *emul = EMUL;
+	uint8_t func_set2_reg;
+
+	zassert_ok(sn5s330_drv.init(SN5S330_PORT));
+
+	/* Verify driver enables SBU FET */
+	zassert_ok(sn5s330_drv.set_sbu(SN5S330_PORT, true));
+	sn5s330_emul_peek_reg(emul, SN5S330_FUNC_SET2, &func_set2_reg);
+	zassert_not_equal(func_set2_reg & SN5S330_SBU_EN, 0, NULL);
+
+	/* Verify driver disables SBU FET */
+	zassert_ok(sn5s330_drv.set_sbu(SN5S330_PORT, false));
+	sn5s330_emul_peek_reg(emul, SN5S330_FUNC_SET2, &func_set2_reg);
+	zassert_equal(func_set2_reg & SN5S330_SBU_EN, 0);
+}
+#else
+{
+	ztest_test_skip();
+}
+#endif /* CONFIG_USBC_PPC_SBU */
+
+ZTEST(ppc_sn5s330, test_sn5s330_vbus_overcurrent)
+{
+	const struct emul *emul = EMUL;
+	uint8_t int_trip_rise_reg1;
+
+	zassert_ok(sn5s330_drv.init(SN5S330_PORT));
+
+	sn5s330_emul_make_vbus_overcurrent(emul);
+	/*
+	 * TODO(b/201420132): Replace arbitrary sleeps.
+	 */
+	/* Make sure interrupt happens first. */
+	k_msleep(SN5S330_INTERRUPT_DELAYMS);
+	zassert_true(sn5s330_emul_interrupt_set_stub_fake.call_count > 0);
+
+	/*
+	 * Verify we cleared vbus overcurrent interrupt trip rise bit so the
+	 * driver can detect future overcurrent clamping interrupts.
+	 */
+	sn5s330_emul_peek_reg(emul, SN5S330_INT_TRIP_RISE_REG1,
+			      &int_trip_rise_reg1);
+	zassert_equal(int_trip_rise_reg1 & SN5S330_ILIM_PP1_MASK, 0);
+}
+
+ZTEST(ppc_sn5s330, test_sn5s330_vbus_overcurrent_late_jump)
+{
+	const struct emul *emul = EMUL;
+	uint8_t int_trip_rise_reg1;
+
+	/* Simulate the system jumping late. The second call to init() will
+	 * skip certain interrupt setup work. Make sure the interrupt continues
+	 * to function.
+	 */
+
+	zassert_ok(sn5s330_drv.init(SN5S330_PORT));
+	system_jumped_late_fake.return_val = 1;
+	zassert_ok(sn5s330_drv.init(SN5S330_PORT));
+
+	sn5s330_emul_make_vbus_overcurrent(emul);
+	/*
+	 * TODO(b/201420132): Replace arbitrary sleeps.
+	 */
+	/* Make sure interrupt happens first. */
+	k_msleep(SN5S330_INTERRUPT_DELAYMS);
+	zassert_true(sn5s330_emul_interrupt_set_stub_fake.call_count > 0);
+
+	/*
+	 * Verify we cleared vbus overcurrent interrupt trip rise bit so the
+	 * driver can detect future overcurrent clamping interrupts.
+	 */
+	sn5s330_emul_peek_reg(emul, SN5S330_INT_TRIP_RISE_REG1,
+			      &int_trip_rise_reg1);
+	zassert_equal(int_trip_rise_reg1 & SN5S330_ILIM_PP1_MASK, 0);
+}
+
+ZTEST(ppc_sn5s330, test_sn5s330_disable_vbus_low_interrupt)
+{
+	const struct emul *emul = EMUL;
+
+	/* Interrupt disabled here */
+	zassert_ok(sn5s330_drv.init(SN5S330_PORT));
+	/* Would normally cause a vbus low interrupt */
+	sn5s330_emul_lower_vbus_below_minv(emul);
+	zassert_equal(sn5s330_emul_interrupt_set_stub_fake.call_count, 0);
+}
+
+ZTEST(ppc_sn5s330, test_sn5s330_disable_vbus_low_interrupt_late_jump)
+{
+	const struct emul *emul = EMUL;
+
+	/* Simulate the system jumping late. The second call to init() will
+	 * skip certain interrupt setup work. Make sure the interrupt continues
+	 * to function.
+	 */
+
+	zassert_ok(sn5s330_drv.init(SN5S330_PORT));
+	system_jumped_late_fake.return_val = 1;
+	zassert_ok(sn5s330_drv.init(SN5S330_PORT));
+
+	/* Would normally cause a vbus low interrupt */
+	sn5s330_emul_lower_vbus_below_minv(emul);
+	zassert_equal(sn5s330_emul_interrupt_set_stub_fake.call_count, 0);
+}
+
+ZTEST(ppc_sn5s330, test_sn5s330_set_vconn_fet)
+{
+	if (!IS_ENABLED(CONFIG_USBC_PPC_VCONN)) {
+		ztest_test_skip();
+		return;
+	}
+
+	const struct emul *emul = EMUL;
+	uint8_t func_set4_reg;
+
+	zassert_ok(sn5s330_drv.init(SN5S330_PORT));
+
+	sn5s330_drv.set_vconn(SN5S330_PORT, false);
+	sn5s330_emul_peek_reg(emul, SN5S330_FUNC_SET4, &func_set4_reg);
+	zassert_equal(func_set4_reg & SN5S330_VCONN_EN, 0);
+
+	sn5s330_drv.set_vconn(SN5S330_PORT, true);
+	sn5s330_emul_peek_reg(emul, SN5S330_FUNC_SET4, &func_set4_reg);
+	zassert_not_equal(func_set4_reg & SN5S330_VCONN_EN, 0, NULL);
+}
+
+/* Make an I2C emulator mock read func wrapped in FFF */
+FAKE_VALUE_FUNC(int, dump_read_fn, const struct emul *, int, uint8_t *, int,
+		void *);
+
+ZTEST(ppc_sn5s330, test_dump)
+{
+	int ret;
+
+	/* Set up our fake read function to pass through to the real emul */
+	RESET_FAKE(dump_read_fn);
+	dump_read_fn_fake.return_val = 1;
+	i2c_common_emul_set_read_func(COMMON_DATA, dump_read_fn, NULL);
+
+	ret = sn5s330_drv.reg_dump(SN5S330_PORT);
+
+	zassert_equal(EC_SUCCESS, ret, "Expected EC_SUCCESS, got %d", ret);
+
+	/* Check that all the expected I2C reads were performed. */
+	MOCK_ASSERT_I2C_READ(dump_read_fn, 0, SN5S330_FUNC_SET1);
+	MOCK_ASSERT_I2C_READ(dump_read_fn, 1, SN5S330_FUNC_SET2);
+	MOCK_ASSERT_I2C_READ(dump_read_fn, 2, SN5S330_FUNC_SET3);
+	MOCK_ASSERT_I2C_READ(dump_read_fn, 3, SN5S330_FUNC_SET4);
+	MOCK_ASSERT_I2C_READ(dump_read_fn, 4, SN5S330_FUNC_SET5);
+	MOCK_ASSERT_I2C_READ(dump_read_fn, 5, SN5S330_FUNC_SET6);
+	MOCK_ASSERT_I2C_READ(dump_read_fn, 6, SN5S330_FUNC_SET7);
+	MOCK_ASSERT_I2C_READ(dump_read_fn, 7, SN5S330_FUNC_SET8);
+	MOCK_ASSERT_I2C_READ(dump_read_fn, 8, SN5S330_FUNC_SET9);
+	MOCK_ASSERT_I2C_READ(dump_read_fn, 9, SN5S330_FUNC_SET10);
+	MOCK_ASSERT_I2C_READ(dump_read_fn, 10, SN5S330_FUNC_SET11);
+	MOCK_ASSERT_I2C_READ(dump_read_fn, 11, SN5S330_FUNC_SET12);
+	MOCK_ASSERT_I2C_READ(dump_read_fn, 12, SN5S330_INT_STATUS_REG1);
+	MOCK_ASSERT_I2C_READ(dump_read_fn, 13, SN5S330_INT_STATUS_REG2);
+	MOCK_ASSERT_I2C_READ(dump_read_fn, 14, SN5S330_INT_STATUS_REG3);
+	MOCK_ASSERT_I2C_READ(dump_read_fn, 15, SN5S330_INT_STATUS_REG4);
+	MOCK_ASSERT_I2C_READ(dump_read_fn, 16, SN5S330_INT_TRIP_RISE_REG1);
+	MOCK_ASSERT_I2C_READ(dump_read_fn, 17, SN5S330_INT_TRIP_RISE_REG2);
+	MOCK_ASSERT_I2C_READ(dump_read_fn, 18, SN5S330_INT_TRIP_RISE_REG3);
+	MOCK_ASSERT_I2C_READ(dump_read_fn, 19, SN5S330_INT_TRIP_FALL_REG1);
+	MOCK_ASSERT_I2C_READ(dump_read_fn, 20, SN5S330_INT_TRIP_FALL_REG2);
+	MOCK_ASSERT_I2C_READ(dump_read_fn, 21, SN5S330_INT_TRIP_FALL_REG3);
+	MOCK_ASSERT_I2C_READ(dump_read_fn, 22, SN5S330_INT_MASK_RISE_REG1);
+	MOCK_ASSERT_I2C_READ(dump_read_fn, 23, SN5S330_INT_MASK_RISE_REG2);
+	MOCK_ASSERT_I2C_READ(dump_read_fn, 24, SN5S330_INT_MASK_RISE_REG3);
+	MOCK_ASSERT_I2C_READ(dump_read_fn, 25, SN5S330_INT_MASK_FALL_REG1);
+	MOCK_ASSERT_I2C_READ(dump_read_fn, 26, SN5S330_INT_MASK_FALL_REG2);
+	MOCK_ASSERT_I2C_READ(dump_read_fn, 27, SN5S330_INT_MASK_FALL_REG3);
+}
+
+enum i2c_operation {
+	I2C_WRITE,
+	I2C_READ,
+};
+
+#define INIT_I2C_FAIL_HELPER(COMMON_DATA, RW, REG)                             \
+	do {                                                                   \
+		if ((RW) == I2C_READ) {                                        \
+			i2c_common_emul_set_read_fail_reg((COMMON_DATA),       \
+							  (REG));              \
+			i2c_common_emul_set_write_fail_reg(                    \
+				(COMMON_DATA), I2C_COMMON_EMUL_NO_FAIL_REG);   \
+		} else if ((RW) == I2C_WRITE) {                                \
+			i2c_common_emul_set_read_fail_reg(                     \
+				(COMMON_DATA), I2C_COMMON_EMUL_NO_FAIL_REG);   \
+			i2c_common_emul_set_write_fail_reg((COMMON_DATA),      \
+							   (REG));             \
+		} else {                                                       \
+			zassert_true(false, "Invalid I2C operation");          \
+		}                                                              \
+		zassert_equal(                                                 \
+			EC_ERROR_INVAL, sn5s330_drv.init(SN5S330_PORT),        \
+			"Did not get EC_ERROR_INVAL when reg %s (0x%02x)"      \
+			"could not be %s",                                     \
+			#REG, (REG), ((RW) == I2C_READ) ? "read" : "written"); \
+	} while (0)
+
+ZTEST(ppc_sn5s330, test_init_reg_fails)
+{
+	/* Fail on each of the I2C operations the init function does to ensure
+	 * we get the correct return value. This includes operations made by
+	 * clr_flags() and set_flags().
+	 */
+
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE, SN5S330_FUNC_SET5);
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_READ, SN5S330_FUNC_SET6);
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE, SN5S330_FUNC_SET6);
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE, SN5S330_FUNC_SET2);
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE, SN5S330_FUNC_SET9);
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE, SN5S330_FUNC_SET11);
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_READ, SN5S330_FUNC_SET8);
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE, SN5S330_FUNC_SET8);
+
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_READ, SN5S330_FUNC_SET4);
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE, SN5S330_FUNC_SET4);
+
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_READ, SN5S330_FUNC_SET3);
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE, SN5S330_FUNC_SET3);
+
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_READ, SN5S330_FUNC_SET10);
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE, SN5S330_FUNC_SET10);
+
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE, SN5S330_INT_STATUS_REG4);
+
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE,
+			     SN5S330_INT_MASK_RISE_REG1);
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE,
+			     SN5S330_INT_MASK_FALL_REG1);
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE,
+			     SN5S330_INT_MASK_RISE_REG2);
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE,
+			     SN5S330_INT_MASK_FALL_REG2);
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE,
+			     SN5S330_INT_MASK_RISE_REG3);
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE,
+			     SN5S330_INT_MASK_FALL_REG3);
+
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_READ, SN5S330_INT_STATUS_REG4);
+
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE,
+			     SN5S330_INT_TRIP_RISE_REG1);
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE,
+			     SN5S330_INT_TRIP_RISE_REG2);
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE,
+			     SN5S330_INT_TRIP_RISE_REG3);
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE,
+			     SN5S330_INT_TRIP_FALL_REG1);
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE,
+			     SN5S330_INT_TRIP_FALL_REG2);
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE,
+			     SN5S330_INT_TRIP_FALL_REG3);
+}
+
+static int pp_fet_test_mock_read_fn(const struct emul *emul, int reg,
+				    uint8_t *val, int bytes, void *data)
+{
+	int *counter = data;
+
+	zassert_true(counter, "data cannot be a NULL pointer");
+
+	/* Pretend to be in dead battery mode (needed for part 2 of the test) */
+	if (reg == SN5S330_INT_STATUS_REG4) {
+		*val = SN5S330_DB_BOOT;
+		return 0;
+	}
+
+	/* Fail if we try to read SN5S330_FUNC_SET3 after the counter hits 0 */
+	if (reg == SN5S330_FUNC_SET3 && (*counter)-- <= 0) {
+		printf("Failing\n");
+		return -EIO;
+	}
+
+	return 1;
+}
+
+ZTEST(ppc_sn5s330, test_pp_fet_enable_fail)
+{
+	/* We attempt to enable the PP (power path) FET at two points during
+	 * the init function, constituting the second and third accesses to the
+	 * FUNC_SET3 register. We need to allow the first N reads/writes to
+	 * succeed to test failure handling of each call to
+	 * sn5s330_pp_fet_enable(). The second call requires us to be in dead
+	 * battery mode, which we take care of in the mock read function.
+	 */
+
+	int counter;
+	int ret;
+
+	i2c_common_emul_set_read_func(COMMON_DATA, pp_fet_test_mock_read_fn,
+				      &counter);
+
+	/* Allow only the first access to the reg to succeed. This tests the
+	 * error handling of the first call to sn5s330_pp_fet_enable().
+	 */
+
+	counter = 1;
+	ret = sn5s330_drv.init(SN5S330_PORT);
+
+	zassert_equal(EC_ERROR_INVAL, ret, "Expected EC_ERROR_INVAL but got %d",
+		      ret);
+
+	/* Allow only the first two accesses to succeed. This tests the error
+	 * handling of the second call to sn5s330_pp_fet_enable().
+	 */
+
+	counter = 2;
+	ret = sn5s330_drv.init(SN5S330_PORT);
+
+	zassert_equal(EC_ERROR_INVAL, ret, "Expected EC_ERROR_INVAL but got %d",
+		      ret);
+}
+
+ZTEST(ppc_sn5s330, test_set_polarity)
+{
+	int ret;
+	uint8_t reg_val;
+
+	/* Ensure flags start cleared */
+	sn5s330_emul_peek_reg(EMUL, SN5S330_FUNC_SET4, &reg_val);
+	zassert_false(reg_val & SN5S330_CC_POLARITY,
+		      "Polarity flags should not be set after reset.");
+
+	/* Set polarity flags */
+	ret = sn5s330_drv.set_polarity(SN5S330_PORT, 1);
+	zassert_equal(EC_SUCCESS, ret, "Expected EC_SUCCESS but got %d", ret);
+
+	sn5s330_emul_peek_reg(EMUL, SN5S330_FUNC_SET4, &reg_val);
+	zassert_true(reg_val & SN5S330_CC_POLARITY,
+		     "Polarity flags should be set.");
+
+	/* Clear polarity flags */
+	ret = sn5s330_drv.set_polarity(SN5S330_PORT, 0);
+	zassert_equal(EC_SUCCESS, ret, "Expected EC_SUCCESS but got %d", ret);
+
+	sn5s330_emul_peek_reg(EMUL, SN5S330_FUNC_SET4, &reg_val);
+	zassert_false(reg_val & SN5S330_CC_POLARITY,
+		      "Polarity flags should be cleared.");
+}
+
+ZTEST(ppc_sn5s330, test_set_vbus_source_current_limit_fail)
+{
+	int ret;
+
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, SN5S330_FUNC_SET1);
+
+	ret = sn5s330_drv.set_vbus_source_current_limit(SN5S330_PORT,
+							TYPEC_RP_3A0);
+	zassert_equal(EC_ERROR_INVAL, ret, "Expected EC_ERROR_INVAL but got %d",
+		      ret);
+}
+
+ZTEST(ppc_sn5s330, test_sn5s330_discharge_vbus_fail)
+{
+	int ret;
+
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, SN5S330_FUNC_SET3);
+
+	ret = sn5s330_drv.discharge_vbus(SN5S330_PORT, false);
+	zassert_equal(EC_ERROR_INVAL, ret, "Expected EC_ERROR_INVAL but got %d",
+		      ret);
+}
+
+ZTEST(ppc_sn5s330, test_low_power_mode_fail)
+{
+	/* Test failed I2C operations in the enter low power mode function */
+
+	int ret;
+
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, SN5S330_FUNC_SET3);
+	ret = sn5s330_drv.enter_low_power_mode(SN5S330_PORT);
+	zassert_equal(EC_ERROR_INVAL, ret, "Expected EC_ERROR_INVAL but got %d",
+		      ret);
+
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, SN5S330_FUNC_SET4);
+	ret = sn5s330_drv.enter_low_power_mode(SN5S330_PORT);
+	zassert_equal(EC_ERROR_INVAL, ret, "Expected EC_ERROR_INVAL but got %d",
+		      ret);
+
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, SN5S330_FUNC_SET2);
+	ret = sn5s330_drv.enter_low_power_mode(SN5S330_PORT);
+	zassert_equal(EC_ERROR_INVAL, ret, "Expected EC_ERROR_INVAL but got %d",
+		      ret);
+
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, SN5S330_FUNC_SET9);
+	ret = sn5s330_drv.enter_low_power_mode(SN5S330_PORT);
+	zassert_equal(EC_ERROR_INVAL, ret, "Expected EC_ERROR_INVAL but got %d",
+		      ret);
+}
+
+ZTEST(ppc_sn5s330, test_sn5s330_set_vconn_fail)
+{
+	/* Test failed I2C operations in the set Vconn function */
+
+	int ret;
+
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, SN5S330_FUNC_SET4);
+	ret = sn5s330_drv.set_vconn(SN5S330_PORT, 0);
+	zassert_equal(EC_ERROR_INVAL, ret, "Expected EC_ERROR_INVAL but got %d",
+		      ret);
+}
+
+static inline void reset_sn5s330_state(void)
+{
+	i2c_common_emul_set_write_func(COMMON_DATA, NULL, NULL);
+	i2c_common_emul_set_read_func(COMMON_DATA, NULL, NULL);
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	sn5s330_emul_reset(EMUL);
+	RESET_FAKE(sn5s330_emul_interrupt_set_stub);
+}
+
+static void ppc_sn5s330_before(void *state)
+{
+	ARG_UNUSED(state);
+	reset_sn5s330_state();
+}
+
+static void ppc_sn5s330_after(void *state)
+{
+	ARG_UNUSED(state);
+	reset_sn5s330_state();
+}
+
+ZTEST_SUITE(ppc_sn5s330, drivers_predicate_post_main, NULL, ppc_sn5s330_before,
+	    ppc_sn5s330_after, NULL);
diff --git a/zephyr/test/drivers/default/src/ppc_syv682x.c b/zephyr/test/drivers/default/src/ppc_syv682x.c
new file mode 100644
index 0000000000..6755fa6f56
--- /dev/null
+++ b/zephyr/test/drivers/default/src/ppc_syv682x.c
@@ -0,0 +1,823 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_syv682x.h"
+#include "syv682x.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "timer.h"
+#include "usbc_ppc.h"
+
+#include <zephyr/device.h>
+#include <zephyr/devicetree/gpio.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/fff.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+#include <zephyr/ztest_assert.h>
+
+#define SYV682X_NODE DT_NODELABEL(syv682x_emul)
+#define GPIO_USB_C1_FRS_EN_PATH NAMED_GPIOS_GPIO_NODE(usb_c1_frs_en)
+
+struct ppc_syv682x_fixture {
+	const struct emul *ppc_emul;
+	struct i2c_common_emul_data *common_data;
+	const struct device *frs_en_gpio_port;
+	int frs_en_gpio_pin;
+};
+
+/* Configuration for a mock I2C access function that sometimes fails. */
+struct reg_to_fail_data {
+	int reg_access_to_fail;
+	int reg_access_fail_countdown;
+};
+
+static const int syv682x_port = 1;
+
+static void *syv682x_test_setup(void)
+{
+	static struct ppc_syv682x_fixture fixture;
+
+	fixture.ppc_emul = EMUL_DT_GET(SYV682X_NODE);
+	fixture.common_data =
+		emul_syv682x_get_i2c_common_data(fixture.ppc_emul);
+	zassert_not_null(fixture.ppc_emul, NULL);
+	fixture.frs_en_gpio_port =
+		DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_USB_C1_FRS_EN_PATH, gpios));
+	zassert_not_null(fixture.frs_en_gpio_port, NULL);
+	fixture.frs_en_gpio_pin = DT_GPIO_PIN(GPIO_USB_C1_FRS_EN_PATH, gpios);
+
+	return &fixture;
+}
+
+static void syv682x_test_before(void *data)
+{
+	/* Reset ppc_discharge_vbus to disable to clear the cached force
+	 * discharge bit in the CONTROL_2 register
+	 */
+	ppc_discharge_vbus(syv682x_port, false);
+}
+
+static void syv682x_test_after(void *data)
+{
+	struct ppc_syv682x_fixture *fixture = data;
+	const struct emul *emul = fixture->ppc_emul;
+	struct i2c_common_emul_data *common_data = fixture->common_data;
+
+	/* Disable the power path and clear interrupt conditions. */
+	zassert_ok(syv682x_emul_set_reg(emul, SYV682X_CONTROL_1_REG,
+					SYV682X_CONTROL_1_PWR_ENB),
+		   NULL);
+	syv682x_emul_set_condition(emul, SYV682X_STATUS_NONE,
+				   SYV682X_CONTROL_4_NONE);
+
+	/* Clear the mock read/write functions */
+	i2c_common_emul_set_read_func(common_data, NULL, NULL);
+	i2c_common_emul_set_write_func(common_data, NULL, NULL);
+
+	/* Don't fail on any register access */
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+}
+
+ZTEST_SUITE(ppc_syv682x, drivers_predicate_post_main, syv682x_test_setup,
+	    syv682x_test_before, syv682x_test_after, NULL);
+
+ZTEST_F(ppc_syv682x, test_syv682x_board_is_syv682c)
+{
+	/*
+	 * The SYV682x driver should assume a version-C part in the absence of a
+	 * board override.
+	 */
+	zassert_true(syv682x_board_is_syv682c(syv682x_port));
+}
+
+static void check_control_1_default_init(uint8_t control_1)
+{
+	/*
+	 * During init, when not in dead battery mode, the driver should
+	 * configure the high-voltage channel as sink but leave the power path
+	 * disabled. The driver should set the current limits according to
+	 * configuration.
+	 */
+	int ilim;
+
+	zassert_true(control_1 & SYV682X_CONTROL_1_PWR_ENB,
+		     "Default init, but power path enabled");
+	ilim = (control_1 & SYV682X_HV_ILIM_MASK) >> SYV682X_HV_ILIM_BIT_SHIFT;
+	zassert_equal(ilim, CONFIG_PLATFORM_EC_USBC_PPC_SYV682X_HV_ILIM,
+		      "Default init, but HV current limit set to %d", ilim);
+	zassert_false(control_1 & SYV682X_CONTROL_1_HV_DR,
+		      "Default init, but source mode selected");
+	zassert_true(control_1 & SYV682X_CONTROL_1_CH_SEL,
+		     "Default init, but 5V power path selected");
+}
+
+ZTEST_F(ppc_syv682x, test_syv682x_init_dead_battery)
+{
+	uint8_t reg;
+
+	/*
+	 * With a dead battery, the device powers up sinking VBUS, and the
+	 * driver should keep that going.
+	 */
+	zassert_ok(syv682x_emul_set_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_1_REG,
+					SYV682X_CONTROL_1_CH_SEL),
+		   NULL);
+	syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_VSAFE_5V,
+				   SYV682X_CONTROL_4_NONE);
+	zassert_ok(ppc_init(syv682x_port), "PPC init failed");
+	zassert_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_1_REG, &reg),
+		   NULL);
+	zassert_true(reg & SYV682X_CONTROL_1_CH_SEL,
+		     "Dead battery init, but CH_SEL set to 5V power path");
+	zassert_false(reg & (SYV682X_CONTROL_1_PWR_ENB |
+			     SYV682X_CONTROL_1_HV_DR),
+		      "Dead battery init, but CONTROL_1 is 0x%x", reg);
+	zassert_false(ppc_is_sourcing_vbus(syv682x_port),
+		      "Dead battery init, but VBUS source enabled");
+}
+
+ZTEST_F(ppc_syv682x, test_syv682x_init_vsafe0v)
+{
+	uint8_t reg;
+
+	/* With VBUS at vSafe0V, init should set the default configuration. */
+	zassert_ok(syv682x_emul_set_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_1_REG,
+					SYV682X_CONTROL_1_PWR_ENB),
+		   NULL);
+	syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_VSAFE_0V,
+				   SYV682X_CONTROL_4_NONE);
+	zassert_ok(ppc_init(syv682x_port), "PPC init failed");
+	zassert_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_1_REG, &reg),
+		   NULL);
+	check_control_1_default_init(reg);
+}
+
+ZTEST_F(ppc_syv682x, test_syv682x_init_sink_disabled)
+{
+	uint8_t reg;
+
+	/* With sink disabled, init should do the same thing. */
+	zassert_ok(syv682x_emul_set_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_1_REG,
+					SYV682X_CONTROL_1_CH_SEL),
+		   NULL);
+	syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_VSAFE_0V,
+				   SYV682X_CONTROL_4_NONE);
+	zassert_ok(ppc_init(syv682x_port), "PPC init failed");
+	zassert_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_1_REG, &reg),
+		   NULL);
+	check_control_1_default_init(reg);
+}
+
+ZTEST_F(ppc_syv682x, test_syv682x_init_common)
+{
+	uint8_t reg;
+	int ilim;
+
+	zassert_ok(ppc_init(syv682x_port), "PPC init failed");
+	zassert_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_1_REG, &reg),
+		   NULL);
+
+	/*
+	 * Any init sequence should also disable the FRS GPIO, set the 5V
+	 * current limit according to configuration, set over-current, over-
+	 * voltage, and discharge parameters appropriately, and enable CC lines.
+	 */
+	zassert_equal(gpio_emul_output_get(fixture->frs_en_gpio_port,
+					   fixture->frs_en_gpio_pin),
+		      0, "FRS enabled, but FRS GPIO not asserted");
+	ilim = (reg & SYV682X_5V_ILIM_MASK) >> SYV682X_5V_ILIM_BIT_SHIFT;
+	zassert_equal(ilim, CONFIG_PLATFORM_EC_USB_PD_PULLUP,
+		      "Default init, but 5V current limit set to %d", ilim);
+	zassert_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_2_REG, &reg),
+		   NULL);
+	zassert_equal(reg,
+		      (SYV682X_OC_DELAY_10MS << SYV682X_OC_DELAY_SHIFT) |
+			      (SYV682X_DSG_RON_200_OHM
+			       << SYV682X_DSG_RON_SHIFT) |
+			      (SYV682X_DSG_TIME_50MS << SYV682X_DSG_TIME_SHIFT),
+		      "Default init, but CONTROL_2 is 0x%x", reg);
+	zassert_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_3_REG, &reg),
+		   NULL);
+	zassert_equal(reg,
+		      (SYV682X_OVP_23_7 << SYV682X_OVP_BIT_SHIFT) |
+			      SYV682X_RVS_MASK,
+		      "Default init, but CONTROL_3 is 0x%x", reg);
+	zassert_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_4_REG, &reg),
+		   NULL);
+	zassert_equal(reg & ~SYV682X_CONTROL_4_INT_MASK,
+		      SYV682X_CONTROL_4_CC1_BPS | SYV682X_CONTROL_4_CC2_BPS,
+		      "Default init, but CONTROL_4 is 0x%x", reg);
+}
+
+ZTEST_F(ppc_syv682x, test_syv682x_vbus_source_enable)
+{
+	uint8_t reg;
+
+	zassert_ok(ppc_vbus_source_enable(syv682x_port, true),
+		   "VBUS enable failed");
+	zassert_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_1_REG, &reg),
+		   "Reading CONTROL_1 failed");
+	zassert_equal(reg & SYV682X_CONTROL_1_PWR_ENB, 0,
+		      "VBUS sourcing enabled but power path disabled");
+	zassert_true(ppc_is_sourcing_vbus(syv682x_port),
+		     "PPC is not sourcing VBUS after VBUS enabled");
+}
+
+ZTEST_F(ppc_syv682x, test_syv682x_vbus_source_disable)
+{
+	zassert_ok(ppc_vbus_source_enable(syv682x_port, false),
+		   "VBUS disable failed");
+	zassert_false(ppc_is_sourcing_vbus(syv682x_port),
+		      "PPC sourcing VBUS after disable");
+}
+
+ZTEST_F(ppc_syv682x, test_syv682x_interrupt_source_oc)
+{
+	zassert_ok(ppc_vbus_source_enable(syv682x_port, true),
+		   "VBUS enable failed");
+	/* An OC event less than 100 ms should not cause VBUS to turn off. */
+	syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_OC_5V,
+				   SYV682X_CONTROL_4_NONE);
+	msleep(50);
+	zassert_true(ppc_is_sourcing_vbus(syv682x_port),
+		     "PPC is not sourcing VBUS after 50 ms OC");
+	/* But one greater than 100 ms should. */
+	msleep(60);
+	zassert_false(ppc_is_sourcing_vbus(syv682x_port),
+		      "PPC is sourcing VBUS after 100 ms OC");
+}
+
+ZTEST_F(ppc_syv682x, test_syv682x_interrupt_tsd)
+{
+	/*
+	 * A TSD event should cause the driver to disable source and sink paths.
+	 * (The device will have already physically disabled them.) The state of
+	 * the sink path is not part of the driver's API.
+	 */
+	zassert_ok(ppc_vbus_source_enable(syv682x_port, true),
+		   "Source enable failed");
+	syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_TSD,
+				   SYV682X_CONTROL_4_NONE);
+	msleep(1);
+	zassert_false(ppc_is_sourcing_vbus(syv682x_port),
+		      "PPC is sourcing power after TSD");
+}
+
+ZTEST_F(ppc_syv682x, test_syv682x_interrupt_vbus_ovp)
+{
+	/* An OVP event should cause the driver to disable the source path. */
+	zassert_ok(ppc_vbus_source_enable(syv682x_port, true),
+		   "Source enable failed");
+	syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_OVP,
+				   SYV682X_CONTROL_4_NONE);
+	msleep(1);
+	zassert_false(ppc_is_sourcing_vbus(syv682x_port),
+		      "PPC is sourcing power after OVP");
+}
+
+ZTEST_F(ppc_syv682x, test_syv682x_interrupt_vbus_hv_oc)
+{
+	uint8_t reg;
+
+	/*
+	 * A high-voltage OC while sinking should cause the driver to try to
+	 * re-enable the sink path until the OC count limit is reached, at which
+	 * point the driver should leave it disabled.
+	 */
+	zassert_ok(ppc_vbus_sink_enable(syv682x_port, true),
+		   "Sink enable failed");
+	syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_OC_HV,
+				   SYV682X_CONTROL_4_NONE);
+	msleep(1);
+	zassert_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_1_REG, &reg),
+		   "Reading CONTROL_1 failed");
+	zassert_equal(reg & SYV682X_CONTROL_1_PWR_ENB, 0,
+		      "Power path disabled after HV_OC handled");
+	syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_OC_HV,
+				   SYV682X_CONTROL_4_NONE);
+	/* Alert GPIO doesn't change so wait for delayed syv682x interrupt */
+	msleep(15);
+	zassert_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_1_REG, &reg),
+		   "Reading CONTROL_1 failed");
+	zassert_equal(reg & SYV682X_CONTROL_1_PWR_ENB, 0,
+		      "Power path disabled after HV_OC handled");
+	syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_OC_HV,
+				   SYV682X_CONTROL_4_NONE);
+	/* Alert GPIO doesn't change so wait for delayed syv682x interrupt */
+	msleep(15);
+	zassert_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_1_REG, &reg),
+		   "Reading CONTROL_1 failed");
+	zassert_equal(reg & SYV682X_CONTROL_1_PWR_ENB,
+		      SYV682X_CONTROL_1_PWR_ENB,
+		      "Power path enabled after HV_OC handled 3 times");
+}
+
+ZTEST_F(ppc_syv682x, test_syv682x_interrupt_vconn_oc)
+{
+	uint8_t reg;
+
+	/*
+	 * A VCONN OC event less than 100 ms should not cause the driver to turn
+	 * VCONN off.
+	 */
+	ppc_set_vconn(syv682x_port, true);
+	syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_NONE,
+				   SYV682X_CONTROL_4_VCONN_OCP);
+	msleep(1);
+	zassert_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_4_REG, &reg),
+		   "Reading CONTROL_4 failed");
+	zassert_true(reg & (SYV682X_CONTROL_4_VCONN1 |
+			    SYV682X_CONTROL_4_VCONN2),
+		     "VCONN disabled after initial VCONN OC");
+	msleep(50);
+	zassert_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_4_REG, &reg),
+		   "Reading CONTROL_4 failed");
+	zassert_true(reg & (SYV682X_CONTROL_4_VCONN1 |
+			    SYV682X_CONTROL_4_VCONN2),
+		     "VCONN disabled after short VCONN OC");
+	/*
+	 * But if the event keeps going for over 100 ms continuously, the driver
+	 * should turn VCONN off.
+	 */
+	msleep(60);
+	zassert_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_4_REG, &reg),
+		   "Reading CONTROL_4 failed");
+	zassert_false(reg & (SYV682X_CONTROL_4_VCONN1 |
+			     SYV682X_CONTROL_4_VCONN2),
+		      "VCONN enabled after long VCONN OC");
+}
+
+ZTEST_F(ppc_syv682x, test_syv682x_interrupt_vconn_ov)
+{
+	uint8_t reg;
+
+	/*
+	 * A VCONN over-voltage (VBAT_OVP) event will cause the device to
+	 * disconnect CC and VCONN. The driver should then reinitialize the
+	 * device, which will enable both CC lines but leave VCONN disabled. The
+	 * driver should then run generic CC over-voltage handling.
+	 */
+	ppc_set_vconn(syv682x_port, true);
+	syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_NONE,
+				   SYV682X_CONTROL_4_VBAT_OVP);
+	msleep(1);
+	zassert_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_4_REG, &reg),
+		   "Reading CONTROL_4 failed");
+	zassert_true(reg & SYV682X_CONTROL_4_CC1_BPS,
+		     "CC1 disabled after handling VBAT_OVP");
+	zassert_true(reg & SYV682X_CONTROL_4_CC2_BPS,
+		     "CC2 disabled after handling VBAT_OVP");
+	zassert_false(reg & (SYV682X_CONTROL_4_VCONN1 |
+			     SYV682X_CONTROL_4_VCONN2),
+		      "VCONN enabled after handling VBAT_OVP");
+}
+
+ZTEST_F(ppc_syv682x, test_syv682x_frs_enable)
+{
+	const struct device *gpio_dev =
+		DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_USB_C1_FRS_EN_PATH, gpios));
+	uint8_t reg;
+
+	/*
+	 * Enabling FRS should enable only the appropriate CC line based on
+	 * polarity. Disabling FRS should enable both CC lines.
+	 */
+	ppc_vbus_sink_enable(syv682x_port, true);
+	zassert_false(ppc_is_sourcing_vbus(syv682x_port),
+		      "PPC is sourcing VBUS after sink enabled");
+	ppc_set_polarity(syv682x_port, 0 /* CC1 */);
+	ppc_set_frs_enable(syv682x_port, true);
+	zassert_equal(gpio_emul_output_get(gpio_dev, fixture->frs_en_gpio_pin),
+		      1, "FRS enabled, but FRS GPIO not asserted");
+	zassert_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_4_REG, &reg),
+		   "Reading CONTROL_4 failed");
+	zassert_equal(
+		reg & (SYV682X_CONTROL_4_CC1_BPS | SYV682X_CONTROL_4_CC2_BPS),
+		SYV682X_CONTROL_4_CC1_BPS,
+		"FRS enabled with CC1 polarity, but CONTROL_4 is 0x%x", reg);
+}
+
+ZTEST_F(ppc_syv682x, test_syv682x_frs_disable)
+{
+	const struct device *gpio_dev =
+		DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_USB_C1_FRS_EN_PATH, gpios));
+	uint8_t reg;
+
+	ppc_vbus_sink_enable(syv682x_port, true);
+	zassert_false(ppc_is_sourcing_vbus(syv682x_port),
+		      "PPC is sourcing VBUS after sink enabled");
+	ppc_set_polarity(syv682x_port, 0 /* CC1 */);
+
+	ppc_set_frs_enable(syv682x_port, false);
+	zassert_equal(gpio_emul_output_get(gpio_dev, fixture->frs_en_gpio_pin),
+		      0, "FRS disabled, but FRS GPIO not deasserted");
+	zassert_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_4_REG, &reg),
+		   "Reading CONTROL_4 failed");
+	zassert_equal(
+		reg & (SYV682X_CONTROL_4_CC1_BPS | SYV682X_CONTROL_4_CC2_BPS),
+		SYV682X_CONTROL_4_CC1_BPS | SYV682X_CONTROL_4_CC2_BPS,
+		"FRS disabled with CC1 polarity, but CONTROL_4 is 0x%x", reg);
+}
+
+ZTEST_F(ppc_syv682x, test_syv682x_frs_trigger)
+{
+	/*
+	 * An FRS event when the PPC is Sink should cause the PPC to switch from
+	 * Sink to Source.
+	 */
+	syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_FRS,
+				   SYV682X_CONTROL_4_NONE);
+	msleep(1);
+	zassert_true(ppc_is_sourcing_vbus(syv682x_port),
+		     "PPC is not sourcing VBUS after FRS signal handled");
+	syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_NONE,
+				   SYV682X_CONTROL_4_NONE);
+}
+
+ZTEST_F(ppc_syv682x, test_syv682x_source_current_limit_usb_default)
+{
+	uint8_t reg;
+	int ilim_val;
+
+	zassert_ok(ppc_set_vbus_source_current_limit(syv682x_port,
+						     TYPEC_RP_USB),
+		   "Could not set source current limit");
+	zassert_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_1_REG, &reg),
+		   "Reading CONTROL_1 failed");
+	ilim_val = (reg & SYV682X_5V_ILIM_MASK) >> SYV682X_5V_ILIM_BIT_SHIFT;
+	zassert_equal(reg & SYV682X_5V_ILIM_MASK, SYV682X_5V_ILIM_1_25,
+		      "Set USB Rp value, but 5V_ILIM is %d", ilim_val);
+}
+
+ZTEST_F(ppc_syv682x, test_syv682x_source_current_limit_1500ma)
+{
+	uint8_t reg;
+	int ilim_val;
+
+	zassert_ok(ppc_set_vbus_source_current_limit(syv682x_port,
+						     TYPEC_RP_1A5),
+		   "Could not set source current limit");
+	zassert_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_1_REG, &reg),
+		   "Reading CONTROL_1 failed");
+	ilim_val = (reg & SYV682X_5V_ILIM_MASK) >> SYV682X_5V_ILIM_BIT_SHIFT;
+	zassert_equal(ilim_val, SYV682X_5V_ILIM_1_75,
+		      "Set 1.5A Rp value, but 5V_ILIM is %d", ilim_val);
+}
+
+ZTEST_F(ppc_syv682x, test_syv682x_source_current_limit_3000ma)
+{
+	uint8_t reg;
+	int ilim_val;
+
+	zassert_ok(ppc_set_vbus_source_current_limit(syv682x_port,
+						     TYPEC_RP_3A0),
+		   "Could not set source current limit");
+	zassert_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_1_REG, &reg),
+		   "Reading CONTROL_1 failed");
+	ilim_val = (reg & SYV682X_5V_ILIM_MASK) >> SYV682X_5V_ILIM_BIT_SHIFT;
+	zassert_equal(ilim_val, SYV682X_5V_ILIM_3_30,
+		      "Set 3.0A Rp value, but 5V_ILIM is %d", ilim_val);
+}
+
+ZTEST_F(ppc_syv682x, test_syv682x_write_busy)
+{
+	/*
+	 * Writes should fail while the BUSY bit is set, except that writes to
+	 * CONTROL_4 should succeed on the SYV682C. 1000 reads is intentionally
+	 * many more than the driver is expected to make before reaching its
+	 * timeout. It is not a goal of this test to verify the frequency of
+	 * polling or the exact value of the timeout.
+	 */
+	syv682x_emul_set_busy_reads(fixture->ppc_emul, 1000);
+	zassert_equal(ppc_set_vbus_source_current_limit(syv682x_port,
+							TYPEC_RP_USB),
+		      EC_ERROR_TIMEOUT, "SYV682 busy, but write completed");
+	zassert_ok(ppc_set_frs_enable(syv682x_port, false),
+		   "Could not set CONTROL_4 while busy on SYV682C");
+
+	/*
+	 * If the busy bit clears before the driver reaches its timeout, the
+	 * write should succeed.
+	 */
+	syv682x_emul_set_busy_reads(fixture->ppc_emul, 1);
+	zassert_equal(ppc_set_vbus_source_current_limit(syv682x_port,
+							TYPEC_RP_USB),
+		      0, "SYV682 not busy, but write failed");
+
+	syv682x_emul_set_busy_reads(fixture->ppc_emul, 0);
+}
+
+ZTEST_F(ppc_syv682x, test_syv682x_dev_is_connected)
+{
+	uint8_t reg;
+
+	zassert_ok(ppc_dev_is_connected(syv682x_port, PPC_DEV_SRC),
+		   "Could not connect device as source");
+	zassert_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_2_REG, &reg),
+		   "Reading CONTROL_2 failed");
+	zassert_false(reg & SYV682X_CONTROL_2_FDSG,
+		      "Connected as source, but force discharge enabled");
+
+	zassert_ok(ppc_dev_is_connected(syv682x_port, PPC_DEV_DISCONNECTED),
+		   "Could not disconnect device");
+	zassert_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_2_REG, &reg),
+		   "Reading CONTROL_2 failed");
+	zassert_true(reg & SYV682X_CONTROL_2_FDSG,
+		     "Disconnected, but force discharge disabled");
+
+	zassert_ok(ppc_dev_is_connected(syv682x_port, PPC_DEV_SNK),
+		   "Could not connect device as source");
+}
+
+ZTEST_F(ppc_syv682x, test_syv682x_vbus_sink_enable_trivial)
+{
+	/*
+	 * If VBUS source is already enabled, disabling VBUS sink should
+	 * trivially succeed.
+	 */
+	zassert_ok(ppc_vbus_source_enable(syv682x_port, true),
+		   "VBUS enable failed");
+	zassert_ok(ppc_vbus_sink_enable(syv682x_port, false),
+		   "Sink disable failed");
+}
+
+ZTEST_F(ppc_syv682x, test_syv682x_vbus_sink_enable_power_path)
+{
+	uint8_t reg;
+	int ilim;
+
+	/*
+	 * After enabling VBUS sink, the HV power path should be enabled in sink
+	 * mode with the configured current limit.
+	 */
+	zassert_ok(ppc_vbus_source_enable(syv682x_port, false),
+		   "VBUS enable failed");
+	zassert_ok(ppc_vbus_sink_enable(syv682x_port, true),
+		   "Sink disable failed");
+	zassert_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_1_REG, &reg),
+		   NULL);
+	zassert_true(reg & SYV682X_CONTROL_1_CH_SEL,
+		     "Sink enabled, but CH_SEL set to 5V power path");
+	zassert_false(reg & SYV682X_CONTROL_1_PWR_ENB,
+		      "Sink enabled, but power path disabled");
+	zassert_false(reg & SYV682X_CONTROL_1_HV_DR,
+		      "Sink enabled, but high-voltage path in source mode");
+	ilim = (reg & SYV682X_HV_ILIM_MASK) >> SYV682X_HV_ILIM_BIT_SHIFT;
+	zassert_equal(ilim, CONFIG_PLATFORM_EC_USBC_PPC_SYV682X_HV_ILIM,
+		      "Sink enabled, but HV current limit set to %d", ilim);
+}
+
+ZTEST_F(ppc_syv682x, test_syv682x_vbus_sink_disable)
+{
+	uint8_t reg;
+
+	zassert_ok(ppc_vbus_source_enable(syv682x_port, false),
+		   "VBUS enable failed");
+	zassert_ok(ppc_vbus_sink_enable(syv682x_port, true),
+		   "Sink disable failed");
+
+	zassert_ok(ppc_vbus_sink_enable(syv682x_port, false),
+		   "Sink disable failed");
+	zassert_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_1_REG, &reg),
+		   NULL);
+	zassert_true(reg & SYV682X_CONTROL_1_PWR_ENB,
+		     "Sink disabled, but power path enabled");
+}
+
+ZTEST_F(ppc_syv682x, test_syv682x_vbus_sink_oc_limit)
+{
+	zassert_ok(ppc_vbus_sink_enable(syv682x_port, true),
+		   "Sink enable failed");
+
+	/* Generate 4 consecutive sink over-current interrupts. After reaching
+	 * this count, the driver should prevent sink enable until the count is
+	 * cleared by sink disable.
+	 */
+	for (int i = 0; i < 4; ++i) {
+		syv682x_emul_set_condition(fixture->ppc_emul,
+					   SYV682X_STATUS_OC_HV,
+					   SYV682X_CONTROL_4_NONE);
+		msleep(15);
+	}
+	syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_NONE,
+				   SYV682X_CONTROL_4_NONE);
+
+	zassert_not_equal(ppc_vbus_sink_enable(syv682x_port, true), EC_SUCCESS,
+			  "VBUS sink enable succeeded after 4 OC events");
+
+	zassert_ok(ppc_vbus_sink_enable(syv682x_port, false),
+		   "Sink disable failed");
+	zassert_ok(ppc_vbus_sink_enable(syv682x_port, true),
+		   "Sink enable failed");
+	zassert_ok(ppc_vbus_sink_enable(syv682x_port, false),
+		   "Sink disable failed");
+}
+
+ZTEST_F(ppc_syv682x, test_syv682x_set_vconn)
+{
+	syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_NONE,
+				   SYV682X_CONTROL_4_VBAT_OVP);
+	zassert_not_equal(ppc_set_vconn(syv682x_port, true), EC_SUCCESS,
+			  "VBAT OVP, but ppc_set_vconn succeeded");
+}
+
+ZTEST(ppc_syv682x, test_syv682x_ppc_dump)
+{
+	/*
+	 * The ppc_dump command should succeed for this port. Don't check the
+	 * output, since there are no standard requirements for that.
+	 */
+	const struct ppc_drv *drv = ppc_chips[syv682x_port].drv;
+
+	zassert_ok(drv->reg_dump(syv682x_port), "ppc_dump command failed");
+}
+
+/* Intercepts I2C reads as a mock. Fails to read for the register at offset
+ * reg_access_to_fail on read number N, where N is the initial value of
+ * reg_access_fail_countdown.
+ */
+static int mock_read_intercept_reg_fail(const struct emul *emul, int reg,
+					uint8_t *val, int bytes, void *data)
+{
+	struct reg_to_fail_data *test_data = data;
+
+	if (reg == test_data->reg_access_to_fail) {
+		test_data->reg_access_fail_countdown--;
+		if (test_data->reg_access_fail_countdown <= 0)
+			return -1;
+	}
+	return 1;
+}
+
+ZTEST_F(ppc_syv682x, test_syv682x_i2c_error_status)
+{
+	/* Failed STATUS read should cause init to fail. */
+	i2c_common_emul_set_read_fail_reg(fixture->common_data,
+					  SYV682X_STATUS_REG);
+	zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS,
+			  "STATUS read error, but init succeeded");
+	i2c_common_emul_set_read_fail_reg(fixture->common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+}
+
+ZTEST_F(ppc_syv682x, test_syv682x_i2c_error_control_1)
+{
+	const struct ppc_drv *drv = ppc_chips[syv682x_port].drv;
+	struct reg_to_fail_data reg_fail = {
+		.reg_access_to_fail = 0,
+		.reg_access_fail_countdown = 0,
+	};
+
+	/* Failed CONTROL_1 read */
+	i2c_common_emul_set_read_fail_reg(fixture->common_data,
+					  SYV682X_CONTROL_1_REG);
+	zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS,
+			  "CONTROL_1 read error, but init succeeded");
+	zassert_not_equal(ppc_vbus_source_enable(syv682x_port, true),
+			  EC_SUCCESS,
+			  "CONTROL_1 read error, but VBUS source enable "
+			  "succeeded");
+	zassert_not_equal(ppc_vbus_sink_enable(syv682x_port, true), EC_SUCCESS,
+			  "CONTROL_1 read error, but VBUS sink enable "
+			  "succeeded");
+	zassert_not_equal(ppc_set_vbus_source_current_limit(syv682x_port,
+							    TYPEC_RP_USB),
+			  EC_SUCCESS,
+			  "CONTROL_1 read error, but set current limit "
+			  "succeeded");
+	zassert_ok(drv->reg_dump(syv682x_port),
+		   "CONTROL_1 read error, and ppc_dump failed");
+	i2c_common_emul_set_read_fail_reg(fixture->common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Init reads CONTROL_1 several times. The 3rd read happens while
+	 * setting the source current limit. Check that init fails when that
+	 * read fails.
+	 */
+	i2c_common_emul_set_read_func(fixture->common_data,
+				      &mock_read_intercept_reg_fail, &reg_fail);
+	reg_fail.reg_access_to_fail = SYV682X_CONTROL_1_REG;
+	reg_fail.reg_access_fail_countdown = 3;
+	zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS,
+			  "CONTROL_1 read error, but init succeeded");
+	i2c_common_emul_set_read_func(fixture->common_data, NULL, NULL);
+
+	/* Failed CONTROL_1 write */
+	i2c_common_emul_set_write_fail_reg(fixture->common_data,
+					   SYV682X_CONTROL_1_REG);
+
+	/* During init, the driver will write CONTROL_1 either to disable all
+	 * power paths (normal case) or to enable the sink path (dead battery
+	 * case). vSafe0V in STATUS is one indication of the normal case.
+	 */
+	syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_VSAFE_0V,
+				   SYV682X_CONTROL_4_NONE);
+	zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS,
+			  "CONTROL_1 write error, but init succeeded");
+	syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_NONE,
+				   SYV682X_CONTROL_4_NONE);
+	zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS,
+			  "CONTROL_1 write error, but init succeeded");
+
+	zassert_not_equal(ppc_vbus_source_enable(syv682x_port, true),
+			  EC_SUCCESS,
+			  "CONTROL_1 write error, but VBUS source "
+			  "enable succeeded");
+	i2c_common_emul_set_write_fail_reg(fixture->common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+}
+
+ZTEST_F(ppc_syv682x, test_syv682x_i2c_error_control_2)
+{
+	/* Failed CONTROL_2 read */
+	i2c_common_emul_set_read_fail_reg(fixture->common_data,
+					  SYV682X_CONTROL_2_REG);
+	zassert_not_equal(ppc_discharge_vbus(syv682x_port, true), EC_SUCCESS,
+			  "CONTROL_2 read error, but VBUS discharge succeeded");
+	i2c_common_emul_set_read_fail_reg(fixture->common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Failed CONTROL_2 write */
+	i2c_common_emul_set_write_fail_reg(fixture->common_data,
+					   SYV682X_CONTROL_2_REG);
+	zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS,
+			  "CONTROL_2 write error, but init succeeded");
+	i2c_common_emul_set_write_fail_reg(fixture->common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+}
+
+ZTEST_F(ppc_syv682x, test_syv682x_i2c_error_control_3)
+{
+	/* Failed CONTROL_3 read */
+	i2c_common_emul_set_read_fail_reg(fixture->common_data,
+					  SYV682X_CONTROL_3_REG);
+	zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS,
+			  "CONTROL_3 read error, but VBUS discharge succeeded");
+	i2c_common_emul_set_read_fail_reg(fixture->common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Failed CONTROL_3 write */
+	i2c_common_emul_set_write_fail_reg(fixture->common_data,
+					   SYV682X_CONTROL_3_REG);
+	zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS,
+			  "CONTROL_3 write error, but init succeeded");
+	i2c_common_emul_set_write_fail_reg(fixture->common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+}
+
+ZTEST_F(ppc_syv682x, test_syv682x_i2c_error_control_4)
+{
+	/* Failed CONTROL_4 read */
+	i2c_common_emul_set_read_fail_reg(fixture->common_data,
+					  SYV682X_CONTROL_4_REG);
+	zassert_not_equal(ppc_set_vconn(syv682x_port, true), EC_SUCCESS,
+			  "CONTROL_2 read error, but VCONN set succeeded");
+	i2c_common_emul_set_read_fail_reg(fixture->common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Failed CONTROL_4 write */
+	i2c_common_emul_set_write_fail_reg(fixture->common_data,
+					   SYV682X_CONTROL_4_REG);
+	zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS,
+			  "CONTROL_4 write error, but init succeeded");
+	zassert_not_equal(ppc_set_vconn(syv682x_port, true), EC_SUCCESS,
+			  "CONTROL_4 write error, but VCONN set succeeded");
+	i2c_common_emul_set_write_fail_reg(fixture->common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+}
diff --git a/zephyr/test/drivers/default/src/ps8xxx.c b/zephyr/test/drivers/default/src/ps8xxx.c
new file mode 100644
index 0000000000..cb0ac7d2d5
--- /dev/null
+++ b/zephyr/test/drivers/default/src/ps8xxx.c
@@ -0,0 +1,1482 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "driver/tcpm/ps8xxx.h"
+#include "driver/tcpm/ps8xxx_public.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/tcpc/emul_ps8xxx.h"
+#include "emul/tcpc/emul_tcpci.h"
+#include "i2c.h"
+#include "tcpm/tcpci.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/tcpci_test_common.h"
+#include "test/drivers/test_state.h"
+#include "timer.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+#define PS8XXX_EMUL_NODE DT_NODELABEL(ps8xxx_emul)
+
+/** Test PS8xxx init fail conditions common for all PS8xxx devices */
+static void test_ps8xxx_init_fail(void)
+{
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(ps8xxx_emul);
+
+	/* Test fail on FW reg read */
+	i2c_common_emul_set_read_fail_reg(common_data, PS8XXX_REG_FW_REV);
+	zassert_equal(EC_ERROR_TIMEOUT, ps8xxx_tcpm_drv.init(USBC_PORT_C1),
+		      NULL);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test fail on FW reg set to 0 */
+	tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, 0x0);
+	zassert_equal(EC_ERROR_TIMEOUT, ps8xxx_tcpm_drv.init(USBC_PORT_C1),
+		      NULL);
+
+	/* Set arbitrary FW reg value != 0 for rest of the test */
+	tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, 0x31);
+
+	/* Test fail on TCPCI init */
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_POWER_STATUS,
+			   TCPC_REG_POWER_STATUS_UNINIT);
+	zassert_equal(EC_ERROR_TIMEOUT, ps8xxx_tcpm_drv.init(USBC_PORT_C1),
+		      NULL);
+}
+
+ZTEST(ps8805, test_init_fail)
+{
+	test_ps8xxx_init_fail();
+}
+
+ZTEST(ps8815, test_init_fail)
+{
+	test_ps8xxx_init_fail();
+}
+
+ZTEST(ps8745, test_init_fail)
+{
+	test_ps8xxx_init_fail();
+}
+
+/**
+ * Test PS8805 init and indirectly ps8705_dci_disable which is
+ * used by PS8805
+ */
+ZTEST(ps8805, test_ps8805_init)
+{
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(ps8xxx_emul);
+	struct i2c_common_emul_data *p1_i2c_common_data =
+		ps8xxx_emul_get_i2c_common_data(ps8xxx_emul,
+						PS8XXX_EMUL_PORT_1);
+
+	/* Set arbitrary FW reg value != 0 for this test */
+	tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, 0x31);
+	/* Set correct power status for this test */
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_POWER_STATUS, 0x0);
+
+	/* Test fail on read I2C debug reg */
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  PS8XXX_REG_I2C_DEBUGGING_ENABLE);
+	zassert_equal(EC_ERROR_INVAL, ps8xxx_tcpm_drv.init(USBC_PORT_C1));
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test fail on read DCI reg */
+	i2c_common_emul_set_read_fail_reg(p1_i2c_common_data,
+					  PS8XXX_P1_REG_MUX_USB_DCI_CFG);
+	zassert_equal(EC_ERROR_INVAL, ps8xxx_tcpm_drv.init(USBC_PORT_C1));
+	i2c_common_emul_set_read_fail_reg(p1_i2c_common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test successful init */
+	zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.init(USBC_PORT_C1));
+	check_tcpci_reg(ps8xxx_emul, PS8XXX_REG_I2C_DEBUGGING_ENABLE,
+			PS8XXX_REG_I2C_DEBUGGING_ENABLE_ON);
+	zassert_equal(PS8XXX_REG_MUX_USB_DCI_CFG_MODE_OFF,
+		      ps8xxx_emul_get_dci_cfg(ps8xxx_emul) &
+			      PS8XXX_REG_MUX_USB_DCI_CFG_MODE_MASK,
+		      NULL);
+}
+
+/** Test PS8815 init */
+ZTEST(ps8815, test_ps8815_init)
+{
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *p1_i2c_common_data =
+		ps8xxx_emul_get_i2c_common_data(ps8xxx_emul,
+						PS8XXX_EMUL_PORT_1);
+
+	/* Set arbitrary FW reg value != 0 for this test */
+	tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, 0x31);
+	/* Set correct power status for rest of the test */
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_POWER_STATUS, 0x0);
+
+	/* Test fail on reading HW revision register */
+	i2c_common_emul_set_read_fail_reg(p1_i2c_common_data,
+					  PS8815_P1_REG_HW_REVISION);
+	zassert_equal(EC_ERROR_INVAL, ps8xxx_tcpm_drv.init(USBC_PORT_C1));
+	i2c_common_emul_set_read_fail_reg(p1_i2c_common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test successful init */
+	zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.init(USBC_PORT_C1));
+}
+
+/** Test PS8745 init */
+ZTEST(ps8745, test_ps8745_init)
+{
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *p1_i2c_common_data =
+		ps8xxx_emul_get_i2c_common_data(ps8xxx_emul,
+						PS8XXX_EMUL_PORT_1);
+
+	/* Set arbitrary FW reg value != 0 for this test */
+	tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, 0x31);
+	/* Set correct power status for rest of the test */
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_POWER_STATUS, 0x0);
+
+	/* Test fail on reading HW revision register */
+	i2c_common_emul_set_read_fail_reg(p1_i2c_common_data,
+					  PS8815_P1_REG_HW_REVISION);
+	zassert_equal(EC_ERROR_INVAL, ps8xxx_tcpm_drv.init(USBC_PORT_C1), NULL);
+	i2c_common_emul_set_read_fail_reg(p1_i2c_common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test successful init */
+	zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.init(USBC_PORT_C1), NULL);
+}
+
+/** Test PS8xxx release */
+static void test_ps8xxx_release(void)
+{
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(ps8xxx_emul);
+
+	uint64_t start_ms;
+
+	/* Test successful release with correct FW reg read */
+	start_ms = k_uptime_get();
+	zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.release(USBC_PORT_C1));
+	zassert_true(k_uptime_get() - start_ms < 10,
+		     "release on correct FW reg read shouldn't wait for chip");
+
+	/* Test delay on FW reg read fail */
+	i2c_common_emul_set_read_fail_reg(common_data, PS8XXX_REG_FW_REV);
+	start_ms = k_uptime_get();
+	zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.release(USBC_PORT_C1));
+	zassert_true(k_uptime_get() - start_ms >= 10,
+		     "release on FW reg read fail should wait for chip");
+}
+
+ZTEST(ps8805, test_release)
+{
+	test_ps8xxx_release();
+}
+
+ZTEST(ps8815, test_release)
+{
+	test_ps8xxx_release();
+}
+
+/**
+ * Check if PS8815 set_cc write correct value to ROLE_CTRL register and if
+ * PS8815 specific workaround is applied to RP_DETECT_CONTROL.
+ */
+static void check_ps8815_set_cc(enum tcpc_rp_value rp, enum tcpc_cc_pull cc,
+				uint16_t rp_detect_ctrl, const char *test_case)
+{
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	uint16_t reg_val, exp_role_ctrl;
+
+	/* Clear RP detect register to see if it is set after test */
+	tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_RP_DETECT_CONTROL, 0);
+
+	exp_role_ctrl = TCPC_REG_ROLE_CTRL_SET(TYPEC_NO_DRP, rp, cc, cc);
+
+	zassert_equal(EC_SUCCESS,
+		      ps8xxx_tcpm_drv.select_rp_value(USBC_PORT_C1, rp),
+		      "Failed to set RP for case: %s", test_case);
+	zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.set_cc(USBC_PORT_C1, cc),
+		      "Failed to set CC for case: %s", test_case);
+
+	zassert_ok(tcpci_emul_get_reg(ps8xxx_emul, TCPC_REG_ROLE_CTRL,
+				      &reg_val),
+		   "Failed tcpci_emul_get_reg() for case: %s", test_case);
+	zassert_equal(exp_role_ctrl, reg_val,
+		      "0x%x != (role_ctrl = 0x%x) for case: %s", exp_role_ctrl,
+		      reg_val, test_case);
+	zassert_ok(tcpci_emul_get_reg(ps8xxx_emul, PS8XXX_REG_RP_DETECT_CONTROL,
+				      &reg_val),
+		   "Failed tcpci_emul_get_reg() for case: %s", test_case);
+	zassert_equal(rp_detect_ctrl, reg_val,
+		      "0x%x != (rp detect = 0x%x) for case: %s", rp_detect_ctrl,
+		      reg_val, test_case);
+}
+
+/** Test PS8815 set cc and device specific workarounds */
+ZTEST(ps8815, test_ps8815_set_cc)
+{
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	int64_t start_time;
+	int64_t delay;
+
+	/*
+	 * Set other hw revision to disable workaround for b/171430855 (delay
+	 * 1 ms on role control reg update). Delay could introduce thread switch
+	 * which may disturb this test.
+	 */
+	ps8xxx_emul_set_hw_rev(ps8xxx_emul, 0x0a02);
+
+	/* Set firmware version <= 0x10 to set "disable rp detect" workaround */
+	tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, 0x8);
+	zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.init(USBC_PORT_C1));
+
+	check_ps8815_set_cc(TYPEC_RP_1A5, TYPEC_CC_RP, RP_DETECT_DISABLE,
+			    "fw rev 0x8 \"disable rp detect\" workaround");
+
+	/* First call to set_cc should disarm workaround */
+	check_ps8815_set_cc(TYPEC_RP_1A5, TYPEC_CC_RP, 0,
+			    "second call without workaround");
+
+	/* drp_toggle should rearm "disable rp detect" workaround */
+	zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.drp_toggle(USBC_PORT_C1),
+		      NULL);
+	check_ps8815_set_cc(TYPEC_RP_1A5, TYPEC_CC_RP, RP_DETECT_DISABLE,
+			    "drp_toggle rearm workaround");
+
+	/*
+	 * Set firmware version <= 0x10 to set "disable rp detect" workaround
+	 * again
+	 */
+	tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, 0xa);
+	zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.init(USBC_PORT_C1));
+
+	/* CC RD shouldn't trigger "disable rp detect" workaround */
+	check_ps8815_set_cc(TYPEC_RP_1A5, TYPEC_CC_RD, 0,
+			    "CC RD not trigger workaround");
+
+	/*
+	 * Set firmware version > 0x10 to unset "disable rp detect"
+	 * workaround
+	 */
+	tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, 0x12);
+	zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.init(USBC_PORT_C1));
+
+	/* Firmware > 0x10 shouldn't trigger "disable rp detect" workaround */
+	check_ps8815_set_cc(TYPEC_RP_1A5, TYPEC_CC_RP, 0,
+			    "fw rev > 0x10 not trigger workaround");
+
+	/*
+	 * Set hw revision 0x0a00 to enable workaround for b/171430855 (delay
+	 * 1 ms on role control reg update)
+	 */
+	ps8xxx_emul_set_hw_rev(ps8xxx_emul, 0x0a00);
+	zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.init(USBC_PORT_C1));
+
+	start_time = k_uptime_get();
+	check_ps8815_set_cc(TYPEC_RP_1A5, TYPEC_CC_RP, 0,
+			    "delay on HW rev 0x0a00");
+	delay = k_uptime_delta(&start_time);
+	zassert_true(delay >= 1, "expected delay on HW rev 0x0a00 (delay %lld)",
+		     delay);
+
+	/*
+	 * Set hw revision 0x0a01 to enable workaround for b/171430855 (delay
+	 * 1 ms on role control reg update)
+	 */
+	ps8xxx_emul_set_hw_rev(ps8xxx_emul, 0x0a01);
+	zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.init(USBC_PORT_C1));
+	start_time = k_uptime_get();
+	check_ps8815_set_cc(TYPEC_RP_1A5, TYPEC_CC_RP, 0,
+			    "delay on HW rev 0x0a01");
+	delay = k_uptime_delta(&start_time);
+	zassert_true(delay >= 1, "expected delay on HW rev 0x0a01 (delay %lld)",
+		     delay);
+
+	/*
+	 * Set other hw revision to disable workaround for b/171430855 (delay
+	 * 1 ms on role control reg update)
+	 */
+	ps8xxx_emul_set_hw_rev(ps8xxx_emul, 0x0a02);
+	zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.init(USBC_PORT_C1));
+	start_time = k_uptime_get();
+	check_ps8815_set_cc(TYPEC_RP_1A5, TYPEC_CC_RP, 0,
+			    "no delay on other HW rev");
+	delay = k_uptime_delta(&start_time);
+	zassert_true(delay == 0,
+		     "unexpected delay on HW rev 0x0a02 (delay %lld)", delay);
+}
+
+/** Test PS8xxx set vconn */
+static void test_ps8xxx_set_vconn(void)
+{
+	uint64_t start_ms;
+
+	/* Test vconn enable */
+	start_ms = k_uptime_get();
+	zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.set_vconn(USBC_PORT_C1, 1),
+		      NULL);
+	zassert_true(k_uptime_get() - start_ms < 10,
+		     "VCONN enable should be without delay");
+
+	/* Test vconn disable */
+	start_ms = k_uptime_get();
+	zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.set_vconn(USBC_PORT_C1, 0),
+		      NULL);
+	/* Delay for VCONN disable is required because of issue b/185202064 */
+	zassert_true(k_uptime_get() - start_ms >= 10,
+		     "VCONN disable require minimum 10ms delay");
+}
+
+ZTEST(ps8805, test_set_vconn)
+{
+	test_ps8xxx_set_vconn();
+}
+
+ZTEST(ps8815, test_set_vconn)
+{
+	test_ps8xxx_set_vconn();
+}
+
+/** Test PS8xxx transmitting message from TCPC */
+static void test_ps8xxx_transmit(void)
+{
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(ps8xxx_emul);
+
+	struct tcpci_emul_msg *msg;
+	uint64_t exp_cnt, cnt;
+	uint16_t reg_val;
+
+	msg = tcpci_emul_get_tx_msg(ps8xxx_emul);
+
+	/* Test fail on transmitting BIST MODE 2 message */
+	i2c_common_emul_set_write_fail_reg(common_data, TCPC_REG_TRANSMIT);
+	zassert_equal(EC_ERROR_INVAL,
+		      ps8xxx_tcpm_drv.transmit(
+			      USBC_PORT_C1, TCPCI_MSG_TX_BIST_MODE_2, 0, NULL),
+		      NULL);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test sending BIST MODE 2 message */
+	exp_cnt = PS8751_BIST_COUNTER;
+	zassert_equal(EC_SUCCESS,
+		      ps8xxx_tcpm_drv.transmit(
+			      USBC_PORT_C1, TCPCI_MSG_TX_BIST_MODE_2, 0, NULL),
+		      NULL);
+	check_tcpci_reg(ps8xxx_emul, PS8XXX_REG_BIST_CONT_MODE_CTR, 0);
+	zassert_equal(TCPCI_MSG_TX_BIST_MODE_2, msg->sop_type);
+
+	/* Check BIST counter value */
+	zassert_ok(tcpci_emul_get_reg(ps8xxx_emul,
+				      PS8XXX_REG_BIST_CONT_MODE_BYTE2,
+				      &reg_val),
+		   NULL);
+	cnt = reg_val;
+	cnt <<= 8;
+	zassert_ok(tcpci_emul_get_reg(ps8xxx_emul,
+				      PS8XXX_REG_BIST_CONT_MODE_BYTE1,
+				      &reg_val),
+		   NULL);
+	cnt |= reg_val;
+	cnt <<= 8;
+	zassert_ok(tcpci_emul_get_reg(ps8xxx_emul,
+				      PS8XXX_REG_BIST_CONT_MODE_BYTE0,
+				      &reg_val),
+		   NULL);
+	cnt |= reg_val;
+	zassert_equal(exp_cnt, cnt, "0x%llx != 0x%llx", exp_cnt, cnt);
+}
+
+ZTEST(ps8805, test_transmit)
+{
+	test_ps8xxx_transmit();
+}
+
+ZTEST(ps8815, test_transmit)
+{
+	test_ps8xxx_transmit();
+}
+
+/** Test PS8805 and PS8815 drp toggle */
+static void test_ps88x5_drp_toggle(bool delay_expected)
+{
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(ps8xxx_emul);
+
+	uint16_t exp_role_ctrl;
+	int64_t start_time;
+	int64_t delay;
+
+	/* Test fail on command write */
+	i2c_common_emul_set_write_fail_reg(common_data, TCPC_REG_COMMAND);
+	zassert_equal(EC_ERROR_INVAL, ps8xxx_tcpm_drv.drp_toggle(USBC_PORT_C1),
+		      NULL);
+
+	/* Test fail on role control write */
+	i2c_common_emul_set_write_fail_reg(common_data, TCPC_REG_ROLE_CTRL);
+	zassert_equal(EC_ERROR_INVAL, ps8xxx_tcpm_drv.drp_toggle(USBC_PORT_C1),
+		      NULL);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test fail on CC status read */
+	i2c_common_emul_set_read_fail_reg(common_data, TCPC_REG_CC_STATUS);
+	zassert_equal(EC_ERROR_INVAL, ps8xxx_tcpm_drv.drp_toggle(USBC_PORT_C1),
+		      NULL);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Set CC status as snk, CC lines set arbitrary */
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_CC_STATUS,
+			   TCPC_REG_CC_STATUS_SET(1, TYPEC_CC_VOLT_OPEN,
+						  TYPEC_CC_VOLT_RA));
+
+	/*
+	 * TODO(b/203858808): PS8815 sleep here if specific FW rev.
+	 *                    Find way to test 1 ms delay
+	 */
+	/* Test drp toggle when CC is snk. Role control CC lines should be RP */
+	exp_role_ctrl = TCPC_REG_ROLE_CTRL_SET(TYPEC_DRP, TYPEC_RP_USB,
+					       TYPEC_CC_RP, TYPEC_CC_RP);
+	start_time = k_uptime_get();
+	zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.drp_toggle(USBC_PORT_C1),
+		      NULL);
+	delay = k_uptime_delta(&start_time);
+	if (delay_expected) {
+		zassert_true(delay >= 1, "expected delay (%lld ms)", delay);
+	} else {
+		zassert_true(delay == 0, "unexpected delay (%lld ms)", delay);
+	}
+	check_tcpci_reg(ps8xxx_emul, TCPC_REG_ROLE_CTRL, exp_role_ctrl);
+	check_tcpci_reg(ps8xxx_emul, TCPC_REG_COMMAND,
+			TCPC_REG_COMMAND_LOOK4CONNECTION);
+
+	/* Set CC status as src, CC lines set arbitrary */
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_CC_STATUS,
+			   TCPC_REG_CC_STATUS_SET(0, TYPEC_CC_VOLT_OPEN,
+						  TYPEC_CC_VOLT_RA));
+
+	/* Test drp toggle when CC is src. Role control CC lines should be RD */
+	exp_role_ctrl = TCPC_REG_ROLE_CTRL_SET(TYPEC_DRP, TYPEC_RP_USB,
+					       TYPEC_CC_RD, TYPEC_CC_RD);
+	start_time = k_uptime_get();
+	zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.drp_toggle(USBC_PORT_C1),
+		      NULL);
+	delay = k_uptime_delta(&start_time);
+	if (delay_expected) {
+		zassert_true(delay >= 1, "expected delay (%lld ms)", delay);
+	} else {
+		zassert_true(delay == 0, "unexpected delay (%lld ms)", delay);
+	}
+	check_tcpci_reg(ps8xxx_emul, TCPC_REG_ROLE_CTRL, exp_role_ctrl);
+	check_tcpci_reg(ps8xxx_emul, TCPC_REG_COMMAND,
+			TCPC_REG_COMMAND_LOOK4CONNECTION);
+}
+
+/** Test PS8815 drp toggle */
+ZTEST(ps8815, test_ps8815_drp_toggle)
+{
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+
+	/*
+	 * Set hw revision 0x0a00 to enable workaround for b/171430855 (delay
+	 * 1 ms on role control reg update)
+	 */
+	ps8xxx_emul_set_hw_rev(ps8xxx_emul, 0x0a00);
+	zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.init(USBC_PORT_C1));
+	test_ps88x5_drp_toggle(true);
+
+	/*
+	 * Set other hw revision to disable workaround for b/171430855 (delay
+	 * 1 ms on role control reg update)
+	 */
+	ps8xxx_emul_set_hw_rev(ps8xxx_emul, 0x0a02);
+	zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.init(USBC_PORT_C1));
+	test_ps88x5_drp_toggle(false);
+}
+
+/** Test PS8805 drp toggle */
+ZTEST(ps8805, test_drp_toggle)
+{
+	test_ps88x5_drp_toggle(false);
+}
+
+/** Test PS8xxx get chip info code used by all PS8xxx devices */
+static void test_ps8xxx_get_chip_info(uint16_t current_product_id)
+{
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(ps8xxx_emul);
+
+	struct ec_response_pd_chip_info_v1 info;
+	uint16_t vendor, product, device_id, fw_rev;
+
+	/* Setup chip info */
+	vendor = PS8XXX_VENDOR_ID;
+	/* Get currently used product ID */
+	product = current_product_id;
+	/* Arbitrary choose device ID that doesn't require fixing */
+	device_id = 0x2;
+	/* Arbitrary revision */
+	fw_rev = 0x32;
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_VENDOR_ID, vendor);
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_PRODUCT_ID, product);
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_BCD_DEV, device_id);
+	tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, fw_rev);
+
+	/* Test fail on reading FW revision */
+	i2c_common_emul_set_read_fail_reg(common_data, PS8XXX_REG_FW_REV);
+	zassert_equal(EC_ERROR_INVAL,
+		      ps8xxx_tcpm_drv.get_chip_info(USBC_PORT_C1, 1, &info),
+		      NULL);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test reading chip info */
+	zassert_equal(EC_SUCCESS,
+		      ps8xxx_tcpm_drv.get_chip_info(USBC_PORT_C1, 1, &info),
+		      NULL);
+	zassert_equal(vendor, info.vendor_id);
+	zassert_equal(product, info.product_id);
+	zassert_equal(device_id, info.device_id);
+	zassert_equal(fw_rev, info.fw_version_number);
+
+	/* Test fail on wrong vendor id */
+	vendor = 0x0;
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_VENDOR_ID, vendor);
+	zassert_equal(EC_ERROR_UNKNOWN,
+		      ps8xxx_tcpm_drv.get_chip_info(USBC_PORT_C1, 1, &info),
+		      NULL);
+
+	/* Set correct vendor id */
+	vendor = PS8XXX_VENDOR_ID;
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_VENDOR_ID, vendor);
+
+	/* Set firmware revision to 0 */
+	fw_rev = 0x0;
+	tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, fw_rev);
+
+	/*
+	 * Test fail on firmware revision equals to 0 when getting chip info
+	 * from live device
+	 */
+	zassert_equal(EC_ERROR_UNKNOWN,
+		      ps8xxx_tcpm_drv.get_chip_info(USBC_PORT_C1, 1, &info),
+		      NULL);
+
+	/*
+	 * Test if firmware revision 0 is accepted when getting chip info from
+	 * not live device
+	 */
+	zassert_equal(EC_SUCCESS,
+		      ps8xxx_tcpm_drv.get_chip_info(USBC_PORT_C1, 0, &info),
+		      NULL);
+	zassert_equal(vendor, info.vendor_id);
+	zassert_equal(product, info.product_id);
+	zassert_equal(device_id, info.device_id);
+	zassert_equal(fw_rev, info.fw_version_number);
+
+	/* Set wrong vendor id */
+	vendor = 0;
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_VENDOR_ID, vendor);
+
+	/* Test fail on vendor id mismatch on live device */
+	zassert_equal(EC_ERROR_UNKNOWN,
+		      ps8xxx_tcpm_drv.get_chip_info(USBC_PORT_C1, 1, &info),
+		      NULL);
+
+	/* Test that vendor id is fixed on not live device */
+	zassert_equal(EC_SUCCESS,
+		      ps8xxx_tcpm_drv.get_chip_info(USBC_PORT_C1, 0, &info),
+		      NULL);
+	zassert_equal(PS8XXX_VENDOR_ID, info.vendor_id);
+	zassert_equal(product, info.product_id);
+	zassert_equal(device_id, info.device_id);
+	zassert_equal(fw_rev, info.fw_version_number);
+
+	/* Set correct vendor id */
+	vendor = PS8XXX_VENDOR_ID;
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_VENDOR_ID, vendor);
+
+	/* Set wrong product id */
+	product = 0;
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_PRODUCT_ID, product);
+
+	/* Test fail on product id mismatch on live device */
+	zassert_equal(EC_ERROR_UNKNOWN,
+		      ps8xxx_tcpm_drv.get_chip_info(USBC_PORT_C1, 1, &info),
+		      NULL);
+
+	/* Test that product id is fixed on not live device */
+	zassert_equal(EC_SUCCESS,
+		      ps8xxx_tcpm_drv.get_chip_info(USBC_PORT_C1, 0, &info),
+		      NULL);
+	zassert_equal(vendor, info.vendor_id);
+	zassert_equal(board_get_ps8xxx_product_id(USBC_PORT_C1),
+		      info.product_id, NULL);
+	zassert_equal(device_id, info.device_id);
+	zassert_equal(fw_rev, info.fw_version_number);
+
+	zassert_equal(false, check_ps8755_chip(USBC_PORT_C1));
+}
+
+ZTEST(ps8805, test_ps8805_get_chip_info)
+{
+	test_ps8xxx_get_chip_info(PS8805_PRODUCT_ID);
+}
+
+ZTEST(ps8815, test_ps8815_get_chip_info)
+{
+	test_ps8xxx_get_chip_info(PS8815_PRODUCT_ID);
+}
+
+ZTEST(ps8745, test_ps8745_get_chip_info)
+{
+	test_ps8xxx_get_chip_info(PS8815_PRODUCT_ID);
+}
+
+/** Test PS8805 get chip info and indirectly ps8805_make_device_id */
+ZTEST(ps8805, test_ps8805_get_chip_info_fix_dev_id)
+{
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *p0_i2c_common_data =
+		ps8xxx_emul_get_i2c_common_data(ps8xxx_emul,
+						PS8XXX_EMUL_PORT_0);
+	struct ec_response_pd_chip_info_v1 info;
+	uint16_t vendor, product, device_id, fw_rev;
+	uint16_t chip_rev;
+
+	struct {
+		uint16_t exp_dev_id;
+		uint16_t chip_rev;
+	} test_param[] = {
+		/* Test A3 chip revision */
+		{
+			.exp_dev_id = 0x2,
+			.chip_rev = 0xa0,
+		},
+		/* Test A2 chip revision */
+		{
+			.exp_dev_id = 0x1,
+			.chip_rev = 0x0,
+		},
+	};
+
+	/* Setup chip info */
+	vendor = PS8XXX_VENDOR_ID;
+	product = PS8805_PRODUCT_ID;
+	/* Arbitrary revision */
+	fw_rev = 0x32;
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_VENDOR_ID, vendor);
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_PRODUCT_ID, product);
+	tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, fw_rev);
+
+	/* Set correct power status for this test */
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_POWER_STATUS, 0x0);
+	/* Init to allow access to "hidden" I2C ports */
+	zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.init(USBC_PORT_C1));
+
+	/* Set device id which requires fixing */
+	device_id = 0x1;
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_BCD_DEV, device_id);
+
+	/* Test error on fixing device id because of fail chip revision read */
+	i2c_common_emul_set_read_fail_reg(p0_i2c_common_data,
+					  PS8805_P0_REG_CHIP_REVISION);
+	zassert_equal(EC_ERROR_INVAL,
+		      ps8xxx_tcpm_drv.get_chip_info(USBC_PORT_C1, 1, &info),
+		      NULL);
+	i2c_common_emul_set_read_fail_reg(p0_i2c_common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Set wrong chip revision */
+	chip_rev = 0x32;
+	ps8xxx_emul_set_chip_rev(ps8xxx_emul, chip_rev);
+
+	/* Test error on fixing device id */
+	zassert_equal(EC_ERROR_UNKNOWN,
+		      ps8xxx_tcpm_drv.get_chip_info(USBC_PORT_C1, 1, &info),
+		      NULL);
+
+	/* Test fixing device id for specific chip revisions */
+	for (int i = 0; i < ARRAY_SIZE(test_param); i++) {
+		ps8xxx_emul_set_chip_rev(ps8xxx_emul, test_param[i].chip_rev);
+
+		/* Test correct device id after fixing */
+		zassert_equal(
+			EC_SUCCESS,
+			ps8xxx_tcpm_drv.get_chip_info(USBC_PORT_C1, 1, &info),
+			"Failed to get chip info in test case %d (chip_rev 0x%x)",
+			i, test_param[i].chip_rev);
+		zassert_equal(
+			vendor, info.vendor_id,
+			"0x%x != (vendor = 0x%x) in test case %d (chip_rev 0x%x)",
+			vendor, info.vendor_id, i, test_param[i].chip_rev);
+		zassert_equal(
+			product, info.product_id,
+			"0x%x != (product = 0x%x) in test case %d (chip_rev 0x%x)",
+			product, info.product_id, i, test_param[i].chip_rev);
+		zassert_equal(
+			test_param[i].exp_dev_id, info.device_id,
+			"0x%x != (device = 0x%x) in test case %d (chip_rev 0x%x)",
+			test_param[i].exp_dev_id, info.device_id, i,
+			test_param[i].chip_rev);
+		zassert_equal(
+			fw_rev, info.fw_version_number,
+			"0x%x != (FW rev = 0x%x) in test case %d (chip_rev 0x%x)",
+			fw_rev, info.fw_version_number, i,
+			test_param[i].chip_rev);
+	}
+}
+
+/** Test PS8745 get chip info and indirectly ps8745_make_device_id */
+ZTEST(ps8745, test_ps8745_get_chip_info_fix_dev_id)
+{
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *p1_i2c_common_data =
+		ps8xxx_emul_get_i2c_common_data(ps8xxx_emul,
+						PS8XXX_EMUL_PORT_1);
+	struct ec_response_pd_chip_info_v1 info;
+	uint16_t vendor, product, device_id, fw_rev;
+	uint16_t hw_rev;
+
+	struct {
+		uint16_t exp_dev_id;
+		uint16_t hw_rev;
+	} test_param[] = {
+		/* Test A0 HW revision */
+		{
+			.exp_dev_id = 0x1,
+			.hw_rev = 0x0a00,
+		},
+		/* Test A1 HW revision */
+		{
+			.exp_dev_id = 0x2,
+			.hw_rev = 0x0a01,
+		},
+		/* Test A2 HW revision */
+		{
+			.exp_dev_id = 0x3,
+			.hw_rev = 0x0a02,
+		},
+	};
+
+	/* Setup chip info */
+	vendor = PS8XXX_VENDOR_ID;
+	product = PS8815_PRODUCT_ID;
+	/* Arbitrary revision */
+	fw_rev = 0x32;
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_VENDOR_ID, vendor);
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_PRODUCT_ID, product);
+	tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, fw_rev);
+
+	/* Set device id which requires fixing */
+	device_id = 0x1;
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_BCD_DEV, device_id);
+
+	/* Test error on fixing device id because of fail hw revision read */
+	i2c_common_emul_set_read_fail_reg(p1_i2c_common_data,
+					  PS8815_P1_REG_HW_REVISION);
+	zassert_equal(EC_ERROR_INVAL,
+		      ps8xxx_tcpm_drv.get_chip_info(USBC_PORT_C1, 1, &info),
+		      NULL);
+	i2c_common_emul_set_read_fail_reg(p1_i2c_common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Set wrong hw revision */
+	hw_rev = 0x32;
+	ps8xxx_emul_set_hw_rev(ps8xxx_emul, hw_rev);
+
+	/* Test error on fixing device id */
+	zassert_equal(EC_ERROR_UNKNOWN,
+		      ps8xxx_tcpm_drv.get_chip_info(USBC_PORT_C1, 1, &info),
+		      NULL);
+
+	/* Test fixing device id for specific HW revisions */
+	for (int i = 0; i < ARRAY_SIZE(test_param); i++) {
+		ps8xxx_emul_set_hw_rev(ps8xxx_emul, test_param[i].hw_rev);
+
+		/* Test correct device id after fixing */
+		zassert_equal(
+			EC_SUCCESS,
+			ps8xxx_tcpm_drv.get_chip_info(USBC_PORT_C1, 1, &info),
+			"Failed to get chip info in test case %d (hw_rev 0x%x)",
+			i, test_param[i].hw_rev);
+		zassert_equal(
+			vendor, info.vendor_id,
+			"0x%x != (vendor = 0x%x) in test case %d (hw_rev 0x%x)",
+			vendor, info.vendor_id, i, test_param[i].hw_rev);
+		zassert_equal(
+			product, info.product_id,
+			"0x%x != (product = 0x%x) in test case %d (hw_rev 0x%x)",
+			product, info.product_id, i, test_param[i].hw_rev);
+		zassert_equal(
+			test_param[i].exp_dev_id, info.device_id,
+			"0x%x != (device = 0x%x) in test case %d (hw_rev 0x%x)",
+			test_param[i].exp_dev_id, info.device_id, i,
+			test_param[i].hw_rev);
+		zassert_equal(
+			fw_rev, info.fw_version_number,
+			"0x%x != (FW rev = 0x%x) in test case %d (hw_rev 0x%x)",
+			fw_rev, info.fw_version_number, i,
+			test_param[i].hw_rev);
+	}
+}
+
+/** Test PS8815 get chip info and indirectly ps8815_make_device_id */
+ZTEST(ps8815, test_ps8815_get_chip_info_fix_dev_id)
+{
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *p1_i2c_common_data =
+		ps8xxx_emul_get_i2c_common_data(ps8xxx_emul,
+						PS8XXX_EMUL_PORT_1);
+	struct ec_response_pd_chip_info_v1 info;
+	uint16_t vendor, product, device_id, fw_rev;
+	uint16_t hw_rev;
+
+	struct {
+		uint16_t exp_dev_id;
+		uint16_t hw_rev;
+	} test_param[] = {
+		/* Test A0 HW revision */
+		{
+			.exp_dev_id = 0x1,
+			.hw_rev = 0x0a00,
+		},
+		/* Test A1 HW revision */
+		{
+			.exp_dev_id = 0x2,
+			.hw_rev = 0x0a01,
+		},
+		/* Test A2 HW revision */
+		{
+			.exp_dev_id = 0x3,
+			.hw_rev = 0x0a02,
+		},
+	};
+
+	/* Setup chip info */
+	vendor = PS8XXX_VENDOR_ID;
+	product = PS8815_PRODUCT_ID;
+	/* Arbitrary revision */
+	fw_rev = 0x32;
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_VENDOR_ID, vendor);
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_PRODUCT_ID, product);
+	tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, fw_rev);
+
+	/* Set device id which requires fixing */
+	device_id = 0x1;
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_BCD_DEV, device_id);
+
+	/* Test error on fixing device id because of fail hw revision read */
+	i2c_common_emul_set_read_fail_reg(p1_i2c_common_data,
+					  PS8815_P1_REG_HW_REVISION);
+	zassert_equal(EC_ERROR_INVAL,
+		      ps8xxx_tcpm_drv.get_chip_info(USBC_PORT_C1, 1, &info),
+		      NULL);
+	i2c_common_emul_set_read_fail_reg(p1_i2c_common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Set wrong hw revision */
+	hw_rev = 0x32;
+	ps8xxx_emul_set_hw_rev(ps8xxx_emul, hw_rev);
+
+	/* Test error on fixing device id */
+	zassert_equal(EC_ERROR_UNKNOWN,
+		      ps8xxx_tcpm_drv.get_chip_info(USBC_PORT_C1, 1, &info),
+		      NULL);
+
+	/* Test fixing device id for specific HW revisions */
+	for (int i = 0; i < ARRAY_SIZE(test_param); i++) {
+		ps8xxx_emul_set_hw_rev(ps8xxx_emul, test_param[i].hw_rev);
+
+		/* Test correct device id after fixing */
+		zassert_equal(
+			EC_SUCCESS,
+			ps8xxx_tcpm_drv.get_chip_info(USBC_PORT_C1, 1, &info),
+			"Failed to get chip info in test case %d (hw_rev 0x%x)",
+			i, test_param[i].hw_rev);
+		zassert_equal(
+			vendor, info.vendor_id,
+			"0x%x != (vendor = 0x%x) in test case %d (hw_rev 0x%x)",
+			vendor, info.vendor_id, i, test_param[i].hw_rev);
+		zassert_equal(
+			product, info.product_id,
+			"0x%x != (product = 0x%x) in test case %d (hw_rev 0x%x)",
+			product, info.product_id, i, test_param[i].hw_rev);
+		zassert_equal(
+			test_param[i].exp_dev_id, info.device_id,
+			"0x%x != (device = 0x%x) in test case %d (hw_rev 0x%x)",
+			test_param[i].exp_dev_id, info.device_id, i,
+			test_param[i].hw_rev);
+		zassert_equal(
+			fw_rev, info.fw_version_number,
+			"0x%x != (FW rev = 0x%x) in test case %d (hw_rev 0x%x)",
+			fw_rev, info.fw_version_number, i,
+			test_param[i].hw_rev);
+	}
+}
+
+/** Test PS8805 get/set gpio */
+ZTEST(ps8805, test_ps8805_gpio)
+{
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *gpio_i2c_common_data =
+		ps8xxx_emul_get_i2c_common_data(ps8xxx_emul,
+						PS8XXX_EMUL_PORT_GPIO);
+	uint8_t exp_ctrl, gpio_ctrl;
+	int level;
+
+	struct {
+		enum ps8805_gpio signal;
+		uint16_t gpio_reg;
+		int level;
+	} test_param[] = {
+		/* Chain of set and unset GPIO to test */
+		{
+			.gpio_reg = PS8805_REG_GPIO_0,
+			.signal = PS8805_GPIO_0,
+			.level = 1,
+		},
+		{
+			.gpio_reg = PS8805_REG_GPIO_1,
+			.signal = PS8805_GPIO_1,
+			.level = 1,
+		},
+		{
+			.gpio_reg = PS8805_REG_GPIO_2,
+			.signal = PS8805_GPIO_2,
+			.level = 1,
+		},
+		/* Test setting GPIO 0 which is already set */
+		{
+			.gpio_reg = PS8805_REG_GPIO_0,
+			.signal = PS8805_GPIO_0,
+			.level = 1,
+		},
+		/* Test clearing GPIOs */
+		{
+			.gpio_reg = PS8805_REG_GPIO_0,
+			.signal = PS8805_GPIO_0,
+			.level = 0,
+		},
+		{
+			.gpio_reg = PS8805_REG_GPIO_1,
+			.signal = PS8805_GPIO_1,
+			.level = 0,
+		},
+		{
+			.gpio_reg = PS8805_REG_GPIO_2,
+			.signal = PS8805_GPIO_2,
+			.level = 0,
+		},
+		/* Test clearing GPIO 0 which is already unset */
+		{
+			.gpio_reg = PS8805_REG_GPIO_0,
+			.signal = PS8805_GPIO_0,
+			.level = 1,
+		},
+	};
+
+	/* Set arbitrary FW reg value != 0 for this test */
+	tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, 0x31);
+	/* Set correct power status for this test */
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_POWER_STATUS, 0x0);
+	/* Init to allow access to "hidden" I2C ports */
+	zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.init(USBC_PORT_C1));
+
+	/* Test fail on invalid signal for gpio control reg */
+	zassert_equal(EC_ERROR_INVAL,
+		      ps8805_gpio_set_level(USBC_PORT_C1, PS8805_GPIO_NUM, 1),
+		      NULL);
+	zassert_equal(EC_ERROR_INVAL,
+		      ps8805_gpio_get_level(USBC_PORT_C1, PS8805_GPIO_NUM,
+					    &level),
+		      NULL);
+
+	/* Setup fail on gpio control reg read */
+	i2c_common_emul_set_read_fail_reg(gpio_i2c_common_data,
+					  PS8805_REG_GPIO_CONTROL);
+
+	/* Test fail on reading gpio control reg */
+	zassert_equal(EC_ERROR_INVAL,
+		      ps8805_gpio_set_level(USBC_PORT_C1, PS8805_GPIO_0, 1),
+		      NULL);
+	zassert_equal(EC_ERROR_INVAL,
+		      ps8805_gpio_get_level(USBC_PORT_C1, PS8805_GPIO_0,
+					    &level),
+		      NULL);
+
+	/* Do not fail on gpio control reg read */
+	i2c_common_emul_set_read_fail_reg(gpio_i2c_common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test fail on writing gpio control reg */
+	i2c_common_emul_set_write_fail_reg(gpio_i2c_common_data,
+					   PS8805_REG_GPIO_CONTROL);
+	zassert_equal(EC_ERROR_INVAL,
+		      ps8805_gpio_set_level(USBC_PORT_C1, PS8805_GPIO_0, 1),
+		      NULL);
+	i2c_common_emul_set_write_fail_reg(gpio_i2c_common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Clear gpio control reg */
+	ps8xxx_emul_set_gpio_ctrl(ps8xxx_emul, 0x0);
+	exp_ctrl = 0;
+
+	/* Test set and unset GPIO */
+	for (int i = 0; i < ARRAY_SIZE(test_param); i++) {
+		if (test_param[i].level) {
+			exp_ctrl |= test_param[i].gpio_reg;
+		} else {
+			exp_ctrl &= ~test_param[i].gpio_reg;
+		}
+		zassert_equal(
+			EC_SUCCESS,
+			ps8805_gpio_set_level(USBC_PORT_C1,
+					      test_param[i].signal,
+					      test_param[i].level),
+			"Failed gpio_set in test case %d (gpio %d, level %d)",
+			i, test_param[i].signal, test_param[i].level);
+		zassert_equal(
+			EC_SUCCESS,
+			ps8805_gpio_get_level(USBC_PORT_C1,
+					      test_param[i].signal, &level),
+			"Failed gpio_get in test case %d (gpio %d, level %d)",
+			i, test_param[i].signal, test_param[i].level);
+		zassert_equal(
+			test_param[i].level, level,
+			"%d != (gpio_get_level = %d) in test case %d (gpio %d, level %d)",
+			test_param[i].level, level, i, test_param[i].signal,
+			test_param[i].level);
+		gpio_ctrl = ps8xxx_emul_get_gpio_ctrl(ps8xxx_emul);
+		zassert_equal(
+			exp_ctrl, gpio_ctrl,
+			"0x%x != (gpio_ctrl = 0x%x) in test case %d (gpio %d, level %d)",
+			exp_ctrl, gpio_ctrl, i, test_param[i].signal,
+			test_param[i].level);
+	}
+}
+
+/** Test TCPCI init and vbus level */
+static void test_ps8xxx_tcpci_init(void)
+{
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(ps8xxx_emul);
+
+	test_tcpci_init(ps8xxx_emul, common_data, USBC_PORT_C1);
+}
+
+ZTEST(ps8805, test_tcpci_init)
+{
+	test_ps8xxx_tcpci_init();
+}
+
+ZTEST(ps8815, test_tcpci_init)
+{
+	test_ps8xxx_tcpci_init();
+}
+
+ZTEST(ps8745, test_tcpci_init)
+{
+	test_ps8xxx_tcpci_init();
+}
+
+/** Test TCPCI release */
+static void test_ps8xxx_tcpci_release(void)
+{
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(ps8xxx_emul);
+
+	test_tcpci_release(ps8xxx_emul, common_data, USBC_PORT_C1);
+}
+
+ZTEST(ps8805, test_tcpci_release)
+{
+	test_ps8xxx_tcpci_release();
+}
+
+ZTEST(ps8815, test_tcpci_release)
+{
+	test_ps8xxx_tcpci_release();
+}
+
+/** Test TCPCI get cc */
+static void test_ps8xxx_tcpci_get_cc(void)
+{
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(ps8xxx_emul);
+
+	test_tcpci_get_cc(ps8xxx_emul, common_data, USBC_PORT_C1);
+}
+
+ZTEST(ps8805, test_tcpci_get_cc)
+{
+	test_ps8xxx_tcpci_get_cc();
+}
+
+ZTEST(ps8815, test_tcpci_get_cc)
+{
+	test_ps8xxx_tcpci_get_cc();
+}
+
+/** Test TCPCI set cc */
+static void test_ps8xxx_tcpci_set_cc(void)
+{
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(ps8xxx_emul);
+
+	test_tcpci_set_cc(ps8xxx_emul, common_data, USBC_PORT_C1);
+}
+
+ZTEST(ps8805, test_tcpci_set_cc)
+{
+	test_ps8xxx_tcpci_set_cc();
+}
+
+ZTEST(ps8815, test_tcpci_set_cc)
+{
+	test_ps8xxx_tcpci_set_cc();
+}
+
+ZTEST(ps8745, test_tcpci_set_cc)
+{
+	test_ps8xxx_tcpci_set_cc();
+}
+
+/** Test TCPCI set polarity */
+static void test_ps8xxx_tcpci_set_polarity(void)
+{
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(ps8xxx_emul);
+
+	test_tcpci_set_polarity(ps8xxx_emul, common_data, USBC_PORT_C1);
+}
+
+ZTEST(ps8805, test_tcpci_set_polarity)
+{
+	test_ps8xxx_tcpci_set_polarity();
+}
+
+ZTEST(ps8815, test_tcpci_set_polarity)
+{
+	test_ps8xxx_tcpci_set_polarity();
+}
+
+/** Test TCPCI set vconn */
+static void test_ps8xxx_tcpci_set_vconn(void)
+{
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(ps8xxx_emul);
+
+	test_tcpci_set_vconn(ps8xxx_emul, common_data, USBC_PORT_C1);
+}
+
+ZTEST(ps8805, test_tcpci_set_vconn)
+{
+	test_ps8xxx_tcpci_set_vconn();
+}
+
+ZTEST(ps8815, test_tcpci_set_vconn)
+{
+	test_ps8xxx_tcpci_set_vconn();
+}
+
+/** Test TCPCI set msg header */
+static void test_ps8xxx_tcpci_set_msg_header(void)
+{
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(ps8xxx_emul);
+
+	test_tcpci_set_msg_header(ps8xxx_emul, common_data, USBC_PORT_C1);
+}
+
+ZTEST(ps8805, test_tcpci_set_msg_header)
+{
+	test_ps8xxx_tcpci_set_msg_header();
+}
+
+ZTEST(ps8815, test_tcpci_set_msg_header)
+{
+	test_ps8xxx_tcpci_set_msg_header();
+}
+
+/** Test TCPCI get raw message */
+static void test_ps8xxx_tcpci_get_rx_message_raw(void)
+{
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(ps8xxx_emul);
+
+	test_tcpci_get_rx_message_raw(ps8xxx_emul, common_data, USBC_PORT_C1);
+}
+
+ZTEST(ps8805, test_tcpci_get_rx_message_raw)
+{
+	test_ps8xxx_tcpci_get_rx_message_raw();
+}
+
+ZTEST(ps8815, test_tcpci_get_rx_message_raw)
+{
+	test_ps8xxx_tcpci_get_rx_message_raw();
+}
+
+ZTEST(ps8745, test_tcpci_get_rx_message_raw)
+{
+	test_ps8xxx_tcpci_get_rx_message_raw();
+}
+
+/** Test TCPCI transmitting message */
+static void test_ps8xxx_tcpci_transmit(void)
+{
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(ps8xxx_emul);
+
+	test_tcpci_transmit(ps8xxx_emul, common_data, USBC_PORT_C1);
+}
+
+ZTEST(ps8805, test_tcpci_transmit)
+{
+	test_ps8xxx_tcpci_transmit();
+}
+
+ZTEST(ps8815, test_tcpci_transmit)
+{
+	test_ps8xxx_tcpci_transmit();
+}
+
+/** Test TCPCI alert */
+static void test_ps8xxx_tcpci_alert(void)
+{
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(ps8xxx_emul);
+
+	test_tcpci_alert(ps8xxx_emul, common_data, USBC_PORT_C1);
+}
+
+ZTEST(ps8805, test_tcpci_alert)
+{
+	test_ps8xxx_tcpci_alert();
+}
+
+ZTEST(ps8815, test_tcpci_alert)
+{
+	test_ps8xxx_tcpci_alert();
+}
+
+/** Test TCPCI alert RX message */
+static void test_ps8xxx_tcpci_alert_rx_message(void)
+{
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(ps8xxx_emul);
+
+	test_tcpci_alert_rx_message(ps8xxx_emul, common_data, USBC_PORT_C1);
+}
+
+ZTEST(ps8805, test_tcpci_alert_rx_message)
+{
+	test_ps8xxx_tcpci_alert_rx_message();
+}
+
+ZTEST(ps8815, test_tcpci_alert_rx_message)
+{
+	test_ps8xxx_tcpci_alert_rx_message();
+}
+
+/** Test TCPCI enter low power mode */
+static void test_ps8xxx_tcpci_low_power_mode(void)
+{
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(ps8xxx_emul);
+	/*
+	 * PS8751/PS8815 has the auto sleep function that enters
+	 * low power mode on its own in ~2 seconds. Other chips
+	 * don't have it. Stub it out for PS8751/PS8815.
+	 */
+	if (board_get_ps8xxx_product_id(USBC_PORT_C1) == PS8751_PRODUCT_ID ||
+	    board_get_ps8xxx_product_id(USBC_PORT_C1) == PS8815_PRODUCT_ID)
+		return;
+	test_tcpci_low_power_mode(ps8xxx_emul, common_data, USBC_PORT_C1);
+}
+
+ZTEST(ps8805, test_tcpci_low_power_mode)
+{
+	test_ps8xxx_tcpci_low_power_mode();
+}
+
+ZTEST(ps8815, test_tcpci_low_power_mode)
+{
+	test_ps8xxx_tcpci_low_power_mode();
+}
+
+/** Test TCPCI set bist test mode */
+static void test_ps8xxx_tcpci_set_bist_mode(void)
+{
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(ps8xxx_emul);
+
+	test_tcpci_set_bist_mode(ps8xxx_emul, common_data, USBC_PORT_C1);
+}
+
+ZTEST(ps8805, test_tcpci_set_bist_mode)
+{
+	test_ps8xxx_tcpci_set_bist_mode();
+}
+
+ZTEST(ps8815, test_tcpci_set_bist_mode)
+{
+	test_ps8xxx_tcpci_set_bist_mode();
+}
+
+/* Setup no fail for all I2C devices associated with PS8xxx emulator */
+static void setup_no_fail_all(void)
+{
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(ps8xxx_emul);
+
+	struct i2c_common_emul_data *p0_i2c_common_data =
+		ps8xxx_emul_get_i2c_common_data(ps8xxx_emul,
+						PS8XXX_EMUL_PORT_0);
+	struct i2c_common_emul_data *p1_i2c_common_data =
+		ps8xxx_emul_get_i2c_common_data(ps8xxx_emul,
+						PS8XXX_EMUL_PORT_1);
+	struct i2c_common_emul_data *gpio_i2c_common_data =
+		ps8xxx_emul_get_i2c_common_data(ps8xxx_emul,
+						PS8XXX_EMUL_PORT_GPIO);
+
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	if (p0_i2c_common_data != NULL) {
+		i2c_common_emul_set_read_fail_reg(p0_i2c_common_data,
+						  I2C_COMMON_EMUL_NO_FAIL_REG);
+		i2c_common_emul_set_write_fail_reg(p0_i2c_common_data,
+						   I2C_COMMON_EMUL_NO_FAIL_REG);
+	}
+
+	if (p1_i2c_common_data != NULL) {
+		i2c_common_emul_set_read_fail_reg(p1_i2c_common_data,
+						  I2C_COMMON_EMUL_NO_FAIL_REG);
+		i2c_common_emul_set_write_fail_reg(p1_i2c_common_data,
+						   I2C_COMMON_EMUL_NO_FAIL_REG);
+	}
+
+	if (gpio_i2c_common_data != NULL) {
+		i2c_common_emul_set_read_fail_reg(gpio_i2c_common_data,
+						  I2C_COMMON_EMUL_NO_FAIL_REG);
+		i2c_common_emul_set_write_fail_reg(gpio_i2c_common_data,
+						   I2C_COMMON_EMUL_NO_FAIL_REG);
+	}
+}
+
+/**
+ * Setup PS8xxx emulator to mimic PS8805 and setup no fail for all I2C devices
+ * associated with PS8xxx emulator
+ */
+static void ps8805_before(void *state)
+{
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	ARG_UNUSED(state);
+
+	board_set_ps8xxx_product_id(PS8805_PRODUCT_ID);
+	ps8xxx_emul_set_product_id(ps8xxx_emul, PS8805_PRODUCT_ID);
+	setup_no_fail_all();
+	zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.init(USBC_PORT_C1));
+}
+
+static void ps8805_after(void *state)
+{
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	ARG_UNUSED(state);
+
+	/* Set correct firmware revision */
+	tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, 0x31);
+}
+
+/**
+ * Setup PS8xxx emulator to mimic PS8815 and setup no fail for all I2C devices
+ * associated with PS8xxx emulator
+ */
+static void ps8815_before(void *state)
+{
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	ARG_UNUSED(state);
+
+	board_set_ps8xxx_product_id(PS8815_PRODUCT_ID);
+	ps8xxx_emul_set_reg_id(ps8xxx_emul, PS8815_REG_ID);
+	ps8xxx_emul_set_product_id(ps8xxx_emul, PS8815_PRODUCT_ID);
+	setup_no_fail_all();
+	zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.init(USBC_PORT_C1));
+}
+
+static void ps8815_after(void *state)
+{
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	ARG_UNUSED(state);
+
+	/* Set correct firmware revision */
+	tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, 0x31);
+}
+
+/**
+ * Setup PS8xxx emulator to mimic PS8745 and setup no fail for all I2C devices
+ * associated with PS8xxx emulator
+ */
+static void ps8745_before(void *state)
+{
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	ARG_UNUSED(state);
+
+	board_set_ps8xxx_product_id(PS8815_PRODUCT_ID);
+	ps8xxx_emul_set_product_id(ps8xxx_emul, PS8815_PRODUCT_ID);
+	ps8xxx_emul_set_reg_id(ps8xxx_emul, PS8745_REG_ID);
+	setup_no_fail_all();
+	zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.init(USBC_PORT_C1), NULL);
+}
+
+static void ps8745_after(void *state)
+{
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	ARG_UNUSED(state);
+
+	/* Set correct firmware revision */
+	tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, 0x31);
+}
+
+ZTEST_SUITE(ps8805, drivers_predicate_pre_main, NULL, ps8805_before,
+	    ps8805_after, NULL);
+
+ZTEST_SUITE(ps8815, drivers_predicate_pre_main, NULL, ps8815_before,
+	    ps8815_after, NULL);
+
+ZTEST_SUITE(ps8745, drivers_predicate_pre_main, NULL, ps8745_before,
+	    ps8745_after, NULL);
diff --git a/zephyr/test/drivers/default/src/smart.c b/zephyr/test/drivers/default/src/smart.c
new file mode 100644
index 0000000000..7ee0c2a219
--- /dev/null
+++ b/zephyr/test/drivers/default/src/smart.c
@@ -0,0 +1,590 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "battery_smart.h"
+#include "common.h"
+#include "console.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_smart_battery.h"
+#include "i2c.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/shell/shell.h>
+#include <zephyr/shell/shell_uart.h>
+#include <zephyr/ztest.h>
+
+#define BATTERY_NODE DT_NODELABEL(battery)
+
+/** Test all simple getters */
+ZTEST_USER(smart_battery, test_battery_getters)
+{
+	struct sbat_emul_bat_data *bat;
+	const struct emul *emul = EMUL_DT_GET(BATTERY_NODE);
+	char block[32];
+	int expected;
+	int word;
+
+	bat = sbat_emul_get_bat_data(emul);
+
+	zassert_equal(EC_SUCCESS, battery_get_mode(&word));
+	zassert_equal(bat->mode, word, "%d != %d", bat->mode, word);
+
+	expected = 100 * bat->cap / bat->design_cap;
+	zassert_equal(EC_SUCCESS, battery_state_of_charge_abs(&word));
+	zassert_equal(expected, word, "%d != %d", expected, word);
+
+	zassert_equal(EC_SUCCESS, battery_cycle_count(&word));
+	zassert_equal(bat->cycle_count, word, "%d != %d", bat->cycle_count,
+		      word);
+	zassert_equal(EC_SUCCESS, battery_design_voltage(&word));
+	zassert_equal(bat->design_mv, word, "%d != %d", bat->design_mv, word);
+	zassert_equal(EC_SUCCESS, battery_serial_number(&word));
+	zassert_equal(bat->sn, word, "%d != %d", bat->sn, word);
+	zassert_equal(EC_SUCCESS, get_battery_manufacturer_name(block, 32),
+		      NULL);
+	zassert_mem_equal(block, bat->mf_name, bat->mf_name_len, "%s != %s",
+			  block, bat->mf_name);
+	zassert_equal(EC_SUCCESS, battery_device_name(block, 32));
+	zassert_mem_equal(block, bat->dev_name, bat->dev_name_len, "%s != %s",
+			  block, bat->dev_name);
+	zassert_equal(EC_SUCCESS, battery_device_chemistry(block, 32));
+	zassert_mem_equal(block, bat->dev_chem, bat->dev_chem_len, "%s != %s",
+			  block, bat->dev_chem);
+	word = battery_get_avg_current();
+	zassert_equal(bat->avg_cur, word, "%d != %d", bat->avg_cur, word);
+	word = battery_get_avg_voltage();
+	zassert_equal(bat->volt, word, "%d != %d", bat->volt, word);
+
+	bat->avg_cur = 200;
+	expected = (bat->full_cap - bat->cap) * 60 / bat->avg_cur;
+	zassert_equal(EC_SUCCESS, battery_time_to_full(&word));
+	zassert_equal(expected, word, "%d != %d", expected, word);
+
+	bat->cur = -200;
+	expected = bat->cap * 60 / (-bat->cur);
+	zassert_equal(EC_SUCCESS, battery_run_time_to_empty(&word));
+	zassert_equal(expected, word, "%d != %d", expected, word);
+
+	bat->avg_cur = -200;
+	expected = bat->cap * 60 / (-bat->avg_cur);
+	zassert_equal(EC_SUCCESS, battery_time_to_empty(&word));
+	zassert_equal(expected, word, "%d != %d", expected, word);
+}
+
+/** Test getting capacity. These functions should force mAh mode */
+ZTEST_USER(smart_battery, test_battery_get_capacity)
+{
+	struct sbat_emul_bat_data *bat;
+	const struct emul *emul = EMUL_DT_GET(BATTERY_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_smart_battery_get_i2c_common_data(emul);
+	int word;
+
+	bat = sbat_emul_get_bat_data(emul);
+
+	/* Test fail when checking battery mode */
+	i2c_common_emul_set_read_fail_reg(common_data, SB_BATTERY_MODE);
+	zassert_equal(EC_ERROR_INVAL, battery_remaining_capacity(&word));
+	zassert_equal(EC_ERROR_INVAL, battery_full_charge_capacity(&word),
+		      NULL);
+	zassert_equal(EC_ERROR_INVAL, battery_design_capacity(&word));
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test getting remaining capacity and if mAh mode is forced */
+	bat->mode |= MODE_CAPACITY;
+	zassert_equal(EC_SUCCESS, battery_remaining_capacity(&word));
+	zassert_equal(bat->cap, word, "%d != %d", bat->cap, word);
+	zassert_false(bat->mode & MODE_CAPACITY, "mAh mode not forced");
+
+	/* Test getting full charge capacity and if mAh mode is forced */
+	bat->mode |= MODE_CAPACITY;
+	zassert_equal(EC_SUCCESS, battery_full_charge_capacity(&word));
+	zassert_equal(bat->full_cap, word, "%d != %d", bat->full_cap, word);
+	zassert_false(bat->mode & MODE_CAPACITY, "mAh mode not forced");
+
+	/* Test getting design capacity and if mAh mode is forced */
+	bat->mode |= MODE_CAPACITY;
+	zassert_equal(EC_SUCCESS, battery_design_capacity(&word));
+	zassert_equal(bat->design_cap, word, "%d != %d", bat->design_cap, word);
+	zassert_false(bat->mode & MODE_CAPACITY, "mAh mode not forced");
+}
+
+/** Test battery status */
+ZTEST_USER(smart_battery, test_battery_status)
+{
+	struct sbat_emul_bat_data *bat;
+	const struct emul *emul = EMUL_DT_GET(BATTERY_NODE);
+	int expected;
+	int status;
+
+	bat = sbat_emul_get_bat_data(emul);
+
+	bat->status = 0;
+	bat->cur = -200;
+	bat->cap_alarm = 0;
+	bat->time_alarm = 0;
+	bat->cap = bat->full_cap / 2;
+	bat->error_code = STATUS_CODE_OVERUNDERFLOW;
+
+	expected = 0;
+	expected |= STATUS_DISCHARGING;
+	expected |= STATUS_CODE_OVERUNDERFLOW;
+
+	zassert_equal(EC_SUCCESS, battery_status(&status));
+	zassert_equal(expected, status, "%d != %d", expected, status);
+}
+
+/** Test wait for stable function */
+ZTEST_USER(smart_battery, test_battery_wait_for_stable)
+{
+	const struct emul *emul = EMUL_DT_GET(BATTERY_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_smart_battery_get_i2c_common_data(emul);
+
+	/* Should fail when read function always fail */
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_FAIL_ALL_REG);
+	zassert_equal(EC_ERROR_NOT_POWERED, battery_wait_for_stable());
+
+	/* Should be ok with default handler */
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	zassert_equal(EC_SUCCESS, battery_wait_for_stable());
+}
+
+/** Test manufacture date */
+ZTEST_USER(smart_battery, test_battery_manufacture_date)
+{
+	struct sbat_emul_bat_data *bat;
+	const struct emul *emul = EMUL_DT_GET(BATTERY_NODE);
+	int day, month, year;
+	int exp_month = 5;
+	int exp_year = 2018;
+	int exp_day = 19;
+	uint16_t date;
+
+	bat = sbat_emul_get_bat_data(emul);
+
+	date = sbat_emul_date_to_word(exp_day, exp_month, exp_year);
+	bat->mf_date = date;
+
+	zassert_equal(EC_SUCCESS, battery_manufacture_date(&year, &month, &day),
+		      NULL);
+	zassert_equal(exp_day, day, "%d != %d", exp_day, day);
+	zassert_equal(exp_month, month, "%d != %d", exp_month, month);
+	zassert_equal(exp_year, year, "%d != %d", exp_year, year);
+}
+
+/** Test time at rate */
+ZTEST_USER(smart_battery, test_battery_time_at_rate)
+{
+	struct sbat_emul_bat_data *bat;
+	const struct emul *emul = EMUL_DT_GET(BATTERY_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_smart_battery_get_i2c_common_data(emul);
+	int expect_time;
+	int minutes;
+	int rate;
+
+	bat = sbat_emul_get_bat_data(emul);
+
+	/* Test fail on rate 0 */
+	rate = 0;
+	zassert_equal(EC_ERROR_INVAL, battery_time_at_rate(rate, &minutes),
+		      NULL);
+
+	/* 10mAh at rate 6000mA will be discharged in 6s */
+	bat->cap = 10;
+	rate = -6000;
+
+	/* Test fail on writing at rate register */
+	i2c_common_emul_set_write_fail_reg(common_data, SB_AT_RATE);
+	zassert_equal(EC_ERROR_INVAL, battery_time_at_rate(rate, &minutes),
+		      NULL);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test fail on reading at rate ok register */
+	i2c_common_emul_set_read_fail_reg(common_data, SB_AT_RATE_OK);
+	zassert_equal(EC_ERROR_INVAL, battery_time_at_rate(rate, &minutes),
+		      NULL);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/*
+	 * Expected discharging rate is less then 10s,
+	 * so AtRateOk() register should return 0
+	 */
+	zassert_equal(EC_ERROR_TIMEOUT, battery_time_at_rate(rate, &minutes),
+		      NULL);
+
+	/* 3000mAh at rate 300mA will be discharged in 10h */
+	bat->cap = 3000;
+	rate = -300;
+	expect_time = 600;
+
+	zassert_equal(EC_SUCCESS, battery_time_at_rate(rate, &minutes));
+	zassert_equal(expect_time, minutes, "%d != %d", expect_time, minutes);
+
+	/* 1000mAh at rate 1000mA will be charged in 1h */
+	bat->cap = bat->full_cap - 1000;
+	rate = 1000;
+	/* battery_time_at_rate report time to full as negative number */
+	expect_time = -60;
+
+	zassert_equal(EC_SUCCESS, battery_time_at_rate(rate, &minutes));
+	zassert_equal(expect_time, minutes, "%d != %d", expect_time, minutes);
+}
+
+/** Test battery get params */
+ZTEST_USER(smart_battery, test_battery_get_params)
+{
+	struct sbat_emul_bat_data *bat;
+	struct batt_params batt;
+	const struct emul *emul = EMUL_DT_GET(BATTERY_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_smart_battery_get_i2c_common_data(emul);
+	int flags;
+
+	bat = sbat_emul_get_bat_data(emul);
+
+	/* Fail temperature read */
+	i2c_common_emul_set_read_fail_reg(common_data, SB_TEMPERATURE);
+	flags = BATT_FLAG_WANT_CHARGE | BATT_FLAG_RESPONSIVE |
+		BATT_FLAG_BAD_TEMPERATURE;
+	batt.flags = 0;
+	battery_get_params(&batt);
+	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
+
+	/* Fail state of charge read; want charge cannot be set */
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  SB_RELATIVE_STATE_OF_CHARGE);
+	flags = BATT_FLAG_RESPONSIVE | BATT_FLAG_BAD_STATE_OF_CHARGE;
+	batt.flags = 0;
+	battery_get_params(&batt);
+	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
+
+	/* Fail voltage read */
+	i2c_common_emul_set_read_fail_reg(common_data, SB_VOLTAGE);
+	flags = BATT_FLAG_WANT_CHARGE | BATT_FLAG_RESPONSIVE |
+		BATT_FLAG_BAD_VOLTAGE;
+	batt.flags = 0;
+	battery_get_params(&batt);
+	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
+
+	/* Fail current read */
+	i2c_common_emul_set_read_fail_reg(common_data, SB_CURRENT);
+	flags = BATT_FLAG_WANT_CHARGE | BATT_FLAG_RESPONSIVE |
+		BATT_FLAG_BAD_CURRENT;
+	batt.flags = 0;
+	battery_get_params(&batt);
+	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
+
+	/* Fail average current read */
+	i2c_common_emul_set_read_fail_reg(common_data, SB_AVERAGE_CURRENT);
+	flags = BATT_FLAG_WANT_CHARGE | BATT_FLAG_RESPONSIVE |
+		BATT_FLAG_BAD_AVERAGE_CURRENT;
+	batt.flags = 0;
+	battery_get_params(&batt);
+	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
+
+	/* Fail charging voltage read; want charge cannot be set */
+	i2c_common_emul_set_read_fail_reg(common_data, SB_CHARGING_VOLTAGE);
+	flags = BATT_FLAG_RESPONSIVE | BATT_FLAG_BAD_DESIRED_VOLTAGE;
+	batt.flags = 0;
+	battery_get_params(&batt);
+	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
+
+	/* Fail charging voltage read; want charge cannot be set */
+	i2c_common_emul_set_read_fail_reg(common_data, SB_CHARGING_CURRENT);
+	flags = BATT_FLAG_RESPONSIVE | BATT_FLAG_BAD_DESIRED_CURRENT;
+	batt.flags = 0;
+	battery_get_params(&batt);
+	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
+
+	/* Fail remaining capacity read */
+	i2c_common_emul_set_read_fail_reg(common_data, SB_REMAINING_CAPACITY);
+	flags = BATT_FLAG_WANT_CHARGE | BATT_FLAG_RESPONSIVE |
+		BATT_FLAG_BAD_REMAINING_CAPACITY;
+	batt.flags = 0;
+	battery_get_params(&batt);
+	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
+
+	/* Fail full capacity read */
+	i2c_common_emul_set_read_fail_reg(common_data, SB_FULL_CHARGE_CAPACITY);
+	flags = BATT_FLAG_WANT_CHARGE | BATT_FLAG_RESPONSIVE |
+		BATT_FLAG_BAD_FULL_CAPACITY;
+	batt.flags = 0;
+	battery_get_params(&batt);
+	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
+
+	/* Fail status read */
+	i2c_common_emul_set_read_fail_reg(common_data, SB_BATTERY_STATUS);
+	flags = BATT_FLAG_WANT_CHARGE | BATT_FLAG_RESPONSIVE |
+		BATT_FLAG_BAD_STATUS;
+	batt.flags = 0;
+	battery_get_params(&batt);
+	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
+
+	/* Fail all */
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_FAIL_ALL_REG);
+	flags = BATT_FLAG_BAD_ANY;
+	batt.flags = 0;
+	battery_get_params(&batt);
+	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
+
+	/* Use default handler, everything should be ok */
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	flags = BATT_FLAG_WANT_CHARGE | BATT_FLAG_RESPONSIVE;
+	batt.flags = 0;
+	battery_get_params(&batt);
+	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
+}
+
+struct mfgacc_data {
+	int reg;
+	uint8_t *buf;
+	int len;
+};
+
+static int mfgacc_read_func(const struct emul *emul, int reg, uint8_t *val,
+			    int bytes, void *data)
+{
+	struct mfgacc_data *conf = data;
+
+	if (bytes == 0 && conf->reg == reg) {
+		sbat_emul_set_response(emul, reg, conf->buf, conf->len, false);
+	}
+
+	return 1;
+}
+
+/** Test battery manufacturer access */
+ZTEST_USER(smart_battery, test_battery_mfacc)
+{
+	struct sbat_emul_bat_data *bat;
+	struct mfgacc_data mfacc_conf;
+	const struct emul *emul = EMUL_DT_GET(BATTERY_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_smart_battery_get_i2c_common_data(emul);
+	uint8_t recv_buf[10];
+	uint8_t mf_data[10];
+	uint16_t cmd;
+	int len;
+
+	bat = sbat_emul_get_bat_data(emul);
+
+	/* Select arbitrary command number for the test */
+	cmd = 0x1234;
+
+	/* Test fail on to short receive buffer */
+	len = 2;
+	zassert_equal(EC_ERROR_INVAL,
+		      sb_read_mfgacc(cmd, SB_ALT_MANUFACTURER_ACCESS, recv_buf,
+				     len),
+		      NULL);
+
+	/* Set correct length for rest of the test */
+	len = 10;
+
+	/* Test fail on writing SB_MANUFACTURER_ACCESS register */
+	i2c_common_emul_set_write_fail_reg(common_data, SB_MANUFACTURER_ACCESS);
+	zassert_equal(EC_ERROR_INVAL,
+		      sb_read_mfgacc(cmd, SB_ALT_MANUFACTURER_ACCESS, recv_buf,
+				     len),
+		      NULL);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test fail on reading manufacturer data (custom handler is not set) */
+	zassert_equal(EC_ERROR_INVAL,
+		      sb_read_mfgacc(cmd, SB_ALT_MANUFACTURER_ACCESS, recv_buf,
+				     len),
+		      NULL);
+
+	/* Set arbitrary manufacturer data */
+	for (int i = 1; i < len; i++) {
+		mf_data[i] = i;
+	}
+	/* Set first byte of message as length */
+	mf_data[0] = len;
+
+	/* Setup custom handler */
+	mfacc_conf.reg = SB_ALT_MANUFACTURER_ACCESS;
+	mfacc_conf.len = len;
+	mfacc_conf.buf = mf_data;
+	i2c_common_emul_set_read_func(common_data, mfgacc_read_func,
+				      &mfacc_conf);
+
+	/* Test error when mf_data doesn't start with command */
+	zassert_equal(EC_ERROR_UNKNOWN,
+		      sb_read_mfgacc(cmd, SB_ALT_MANUFACTURER_ACCESS, recv_buf,
+				     len),
+		      NULL);
+
+	/* Set beginning of the manufacturer data */
+	mf_data[1] = cmd & 0xff;
+	mf_data[2] = (cmd >> 8) & 0xff;
+
+	/* Test successful manufacturer data read */
+	zassert_equal(EC_SUCCESS,
+		      sb_read_mfgacc(cmd, SB_ALT_MANUFACTURER_ACCESS, recv_buf,
+				     len),
+		      NULL);
+	/* Compare received data ignoring length byte */
+	zassert_mem_equal(mf_data + 1, recv_buf, len - 1, NULL);
+
+	/* Disable custom read function */
+	i2c_common_emul_set_read_func(common_data, NULL, NULL);
+}
+
+/** Test battery fake charge level set and read */
+ZTEST_USER(smart_battery, test_battery_fake_charge)
+{
+	struct sbat_emul_bat_data *bat;
+	struct batt_params batt;
+	const struct emul *emul = EMUL_DT_GET(BATTERY_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_smart_battery_get_i2c_common_data(emul);
+	int remaining_cap;
+	int fake_charge;
+	int charge;
+	int flags;
+
+	bat = sbat_emul_get_bat_data(emul);
+
+	/* Success on command with no argument */
+	zassert_equal(EC_SUCCESS, shell_execute_cmd(get_ec_shell(), "battfake"),
+		      NULL);
+
+	/* Fail on command with argument which is not a number */
+	zassert_equal(EC_ERROR_PARAM1,
+		      shell_execute_cmd(get_ec_shell(), "battfake test"), NULL);
+
+	/* Fail on command with charge level above 100% */
+	zassert_equal(EC_ERROR_PARAM1,
+		      shell_execute_cmd(get_ec_shell(), "battfake 123"), NULL);
+
+	/* Fail on command with charge level below 0% */
+	zassert_equal(EC_ERROR_PARAM1,
+		      shell_execute_cmd(get_ec_shell(), "battfake -23"), NULL);
+
+	/* Set fake charge level */
+	fake_charge = 65;
+	zassert_equal(EC_SUCCESS,
+		      shell_execute_cmd(get_ec_shell(), "battfake 65"), NULL);
+
+	/* Test that fake charge level is applied */
+	flags = BATT_FLAG_WANT_CHARGE | BATT_FLAG_RESPONSIVE;
+	batt.flags = 0;
+	battery_get_params(&batt);
+	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
+	zassert_equal(fake_charge, batt.state_of_charge, "%d%% != %d%%",
+		      fake_charge, batt.state_of_charge);
+	remaining_cap = bat->full_cap * fake_charge / 100;
+	zassert_equal(remaining_cap, batt.remaining_capacity, "%d != %d",
+		      remaining_cap, batt.remaining_capacity);
+
+	/* Test fake remaining capacity when full capacity is not available */
+	i2c_common_emul_set_read_fail_reg(common_data, SB_FULL_CHARGE_CAPACITY);
+	flags = BATT_FLAG_WANT_CHARGE | BATT_FLAG_RESPONSIVE |
+		BATT_FLAG_BAD_FULL_CAPACITY;
+	batt.flags = 0;
+	battery_get_params(&batt);
+	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
+	zassert_equal(fake_charge, batt.state_of_charge, "%d%% != %d%%",
+		      fake_charge, batt.state_of_charge);
+	remaining_cap = bat->design_cap * fake_charge / 100;
+	zassert_equal(remaining_cap, batt.remaining_capacity, "%d != %d",
+		      remaining_cap, batt.remaining_capacity);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Disable fake charge level */
+	zassert_equal(EC_SUCCESS,
+		      shell_execute_cmd(get_ec_shell(), "battfake -1"), NULL);
+
+	/* Test that fake charge level is not applied */
+	flags = BATT_FLAG_WANT_CHARGE | BATT_FLAG_RESPONSIVE;
+	batt.flags = 0;
+	battery_get_params(&batt);
+	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
+	charge = 100 * bat->cap / bat->full_cap;
+	zassert_equal(charge, batt.state_of_charge, "%d%% != %d%%", charge,
+		      batt.state_of_charge);
+	zassert_equal(bat->cap, batt.remaining_capacity, "%d != %d", bat->cap,
+		      batt.remaining_capacity);
+}
+
+static void reset_battfake(void *data)
+{
+	shell_execute_cmd(get_ec_shell(), "battfake -1");
+}
+
+/** Test battery fake temperature set and read */
+ZTEST_USER(smart_battery, test_battery_fake_temperature)
+{
+	struct sbat_emul_bat_data *bat;
+	struct batt_params batt;
+	const struct emul *emul = EMUL_DT_GET(BATTERY_NODE);
+	int fake_temp;
+	int flags;
+
+	bat = sbat_emul_get_bat_data(emul);
+
+	/* Success on command with no argument */
+	zassert_equal(EC_SUCCESS,
+		      shell_execute_cmd(get_ec_shell(), "batttempfake"), NULL);
+
+	/* Fail on command with argument which is not a number */
+	zassert_equal(EC_ERROR_PARAM1,
+		      shell_execute_cmd(get_ec_shell(), "batttempfake test"),
+		      NULL);
+
+	/* Fail on command with too high temperature (above 500.0 K) */
+	zassert_equal(EC_ERROR_PARAM1,
+		      shell_execute_cmd(get_ec_shell(), "batttempfake 5001"),
+		      NULL);
+
+	/* Fail on command with too low temperature (below 0 K) */
+	zassert_equal(EC_ERROR_PARAM1,
+		      shell_execute_cmd(get_ec_shell(), "batttempfake -23"),
+		      NULL);
+
+	/* Set fake temperature */
+	fake_temp = 2840;
+	zassert_equal(EC_SUCCESS,
+		      shell_execute_cmd(get_ec_shell(), "batttempfake 2840"),
+		      NULL);
+
+	/* Test that fake temperature is applied */
+	flags = BATT_FLAG_WANT_CHARGE | BATT_FLAG_RESPONSIVE;
+	batt.flags = 0;
+	battery_get_params(&batt);
+	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
+	zassert_equal(fake_temp, batt.temperature, "%d != %d", fake_temp,
+		      batt.temperature);
+
+	/* Disable fake temperature */
+	zassert_equal(EC_SUCCESS,
+		      shell_execute_cmd(get_ec_shell(), "batttempfake -1"),
+		      NULL);
+
+	/* Test that fake temperature is not applied */
+	flags = BATT_FLAG_WANT_CHARGE | BATT_FLAG_RESPONSIVE;
+	batt.flags = 0;
+	battery_get_params(&batt);
+	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
+	zassert_equal(bat->temp, batt.temperature, "%d != %d", bat->temp,
+		      batt.temperature);
+}
+
+ZTEST_SUITE(smart_battery, drivers_predicate_post_main, NULL, NULL,
+	    reset_battfake, NULL);
diff --git a/zephyr/test/drivers/default/src/stm_mems_common.c b/zephyr/test/drivers/default/src/stm_mems_common.c
new file mode 100644
index 0000000000..09f1cf8506
--- /dev/null
+++ b/zephyr/test/drivers/default/src/stm_mems_common.c
@@ -0,0 +1,339 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "driver/stm_mems_common.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/i2c_mock.h"
+#include "i2c/i2c.h"
+#include "test/drivers/test_state.h"
+
+#include <errno.h>
+
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/ztest.h>
+
+#define MOCK_EMUL EMUL_DT_GET(DT_NODELABEL(i2c_mock))
+#define COMMON_DATA emul_i2c_mock_get_i2c_common_data(MOCK_EMUL)
+
+struct mock_properties {
+	/* Incremented by the mock function every time it is called */
+	int call_count;
+};
+
+static int mock_read_fn(const struct emul *emul, int reg, uint8_t *val,
+			int bytes, void *data)
+{
+	ztest_check_expected_value(reg);
+	ztest_check_expected_value(bytes);
+	if (val != NULL) {
+		/* Allow passing a mocked read byte through the output param */
+		ztest_copy_return_data(val, sizeof(*val));
+	}
+	return ztest_get_return_value();
+}
+
+static int mock_write_fn(const struct emul *emul, int reg, uint8_t val,
+			 int bytes, void *data)
+{
+	struct mock_properties *props = (struct mock_properties *)data;
+
+	if (props)
+		props->call_count++;
+
+	ztest_check_expected_value(reg);
+	ztest_check_expected_value(val);
+	ztest_check_expected_value(bytes);
+	return ztest_get_return_value();
+}
+
+ZTEST(stm_mems_common, test_st_raw_read_n)
+{
+	const struct emul *emul = MOCK_EMUL;
+
+	int rv;
+
+	i2c_common_emul_set_read_func(COMMON_DATA, mock_read_fn, NULL);
+	/*
+	 * Ensure the MSb (auto-increment bit) in the register address gets
+	 * set, but also return an error condition
+	 */
+	ztest_expect_value(mock_read_fn, reg, 0x80);
+	ztest_expect_value(mock_read_fn, bytes, 0);
+	ztest_returns_value(mock_read_fn, -EIO);
+
+	rv = st_raw_read_n(I2C_PORT_POWER, i2c_mock_get_addr(emul), 0, NULL, 2);
+	/* The shim layer translates -EIO to EC_ERROR_INVAL. */
+	zassert_equal(rv, EC_ERROR_INVAL, "rv was %d but expected %d", rv,
+		      EC_ERROR_INVAL);
+}
+
+ZTEST(stm_mems_common, test_st_raw_read_n_noinc)
+{
+	const struct emul *emul = MOCK_EMUL;
+
+	int rv;
+
+	i2c_common_emul_set_read_func(COMMON_DATA, mock_read_fn, NULL);
+	/*
+	 * Unlike `st_raw_read_n`, the MSb (auto-increment bit) in the register
+	 * address should NOT be automatically set. Also return an error.
+	 */
+	ztest_expect_value(mock_read_fn, reg, 0x00);
+	ztest_expect_value(mock_read_fn, bytes, 0);
+	ztest_returns_value(mock_read_fn, -EIO);
+
+	rv = st_raw_read_n_noinc(I2C_PORT_POWER, i2c_mock_get_addr(emul), 0,
+				 NULL, 2);
+	/* The shim layer translates -EIO to EC_ERROR_INVAL. */
+	zassert_equal(rv, EC_ERROR_INVAL, "rv was %d but expected %d", rv,
+		      EC_ERROR_INVAL);
+}
+
+ZTEST(stm_mems_common, test_st_write_data_with_mask)
+{
+	const struct emul *emul = MOCK_EMUL;
+
+	int rv;
+
+	const struct motion_sensor_t sensor = {
+		.port = I2C_PORT_POWER,
+		.i2c_spi_addr_flags = i2c_mock_get_addr(emul),
+	};
+
+	/* Arbitrary named test parameters */
+	uint8_t test_addr = 0xAA;
+	uint8_t initial_value = 0x55;
+	uint8_t test_mask = 0xF0;
+	uint8_t test_data = 0xFF;
+	uint8_t expected_new_value = (initial_value & ~test_mask) |
+				     (test_data & test_mask);
+
+	/* Part 1: error occurs when reading initial value from sensor */
+	i2c_common_emul_set_read_func(COMMON_DATA, mock_read_fn, NULL);
+	ztest_expect_value(mock_read_fn, reg, test_addr);
+	ztest_expect_value(mock_read_fn, bytes, 0);
+	/* Value is immaterial but ztest has no way to explicitly ignore it */
+	ztest_return_data(mock_read_fn, val, &initial_value);
+	ztest_returns_value(mock_read_fn, -EIO);
+
+	rv = st_write_data_with_mask(&sensor, test_addr, test_mask, test_data);
+	/* The shim layer translates -EIO to EC_ERROR_INVAL. */
+	zassert_equal(rv, EC_ERROR_INVAL, "rv was %d but expected %d", rv,
+		      EC_ERROR_INVAL);
+
+	/*
+	 * Part 2: initial read succeeds, but the initial value already
+	 * matches the new value, so no write happens.
+	 */
+	ztest_expect_value(mock_read_fn, reg, test_addr);
+	ztest_expect_value(mock_read_fn, bytes, 0);
+	ztest_return_data(mock_read_fn, val, &expected_new_value);
+	ztest_returns_value(mock_read_fn, 0);
+
+	struct mock_properties write_fn_props = {
+		.call_count = 0,
+	};
+
+	i2c_common_emul_set_write_func(COMMON_DATA, mock_write_fn,
+				       &write_fn_props);
+
+	rv = st_write_data_with_mask(&sensor, test_addr, test_mask, test_data);
+	zassert_equal(rv, EC_SUCCESS, "rv was %d but expected %d", rv,
+		      EC_SUCCESS);
+	zassert_equal(write_fn_props.call_count, 0,
+		      "mock_write_fn was called.");
+
+	/*
+	 * Part 3: this time a write is required, but it fails. This also
+	 * tests the masking logic.
+	 */
+	ztest_expect_value(mock_read_fn, reg, test_addr);
+	ztest_expect_value(mock_read_fn, bytes, 0);
+	ztest_return_data(mock_read_fn, val, &initial_value);
+	ztest_returns_value(mock_read_fn, 0);
+
+	write_fn_props.call_count = 0; /* Reset call count */
+	ztest_expect_value(mock_write_fn, reg, test_addr);
+	ztest_expect_value(mock_write_fn, bytes, 1);
+	ztest_expect_value(mock_write_fn, val, expected_new_value);
+	ztest_returns_value(mock_write_fn, -EIO);
+
+	rv = st_write_data_with_mask(&sensor, test_addr, test_mask, test_data);
+	/* The shim layer translates -EIO to EC_ERROR_INVAL. */
+	zassert_equal(rv, EC_ERROR_INVAL, "rv was %d but expected %d", rv,
+		      EC_ERROR_INVAL);
+	zassert_equal(write_fn_props.call_count, 1,
+		      "mock_write_fn was not called.");
+}
+
+ZTEST(stm_mems_common, test_st_get_resolution)
+{
+	int expected_resolution = 123;
+	int rv;
+
+	struct stprivate_data driver_data = {
+		.resol = expected_resolution,
+	};
+
+	const struct motion_sensor_t sensor = {
+		.drv_data = &driver_data,
+	};
+
+	rv = st_get_resolution(&sensor);
+	zassert_equal(rv, expected_resolution, "rv is %d but expected %d", rv,
+		      expected_resolution);
+}
+
+ZTEST(stm_mems_common, test_st_set_offset)
+{
+	int16_t expected_offset[3] = { 123, 456, 789 };
+
+	struct stprivate_data driver_data;
+	const struct motion_sensor_t sensor = {
+		.drv_data = &driver_data,
+	};
+
+	int rv = st_set_offset(&sensor, expected_offset, 0);
+
+	zassert_equal(rv, EC_SUCCESS, "rv as %d but expected %d", rv,
+		      EC_SUCCESS);
+	zassert_equal(driver_data.offset[X], expected_offset[X],
+		      "X offset is %d but expected %d", driver_data.offset[X],
+		      expected_offset[X]);
+	zassert_equal(driver_data.offset[Y], expected_offset[Y],
+		      "Y offset is %d but expected %d", driver_data.offset[Y],
+		      expected_offset[Y]);
+	zassert_equal(driver_data.offset[Z], expected_offset[Z],
+		      "Z offset is %d but expected %d", driver_data.offset[Z],
+		      expected_offset[Z]);
+}
+
+ZTEST(stm_mems_common, test_st_get_offset)
+{
+	struct stprivate_data driver_data = {
+		.offset = { [X] = 123, [Y] = 456, [Z] = 789 },
+	};
+	const struct motion_sensor_t sensor = {
+		.drv_data = &driver_data,
+	};
+
+	int16_t temp_out = 0;
+	int16_t actual_offset[3] = { 0, 0, 0 };
+
+	int rv = st_get_offset(&sensor, actual_offset, &temp_out);
+
+	zassert_equal(rv, EC_SUCCESS, "rv as %d but expected %d", rv,
+		      EC_SUCCESS);
+	zassert_equal(
+		temp_out, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP,
+		"temp is %d but should be %d (EC_MOTION_SENSE_INVALID_CALIB_TEMP)",
+		temp_out, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP);
+
+	zassert_equal(actual_offset[X], driver_data.offset[X],
+		      "X offset is %d but expected %d", actual_offset[X],
+		      driver_data.offset[X]);
+	zassert_equal(actual_offset[Y], driver_data.offset[Y],
+		      "Y offset is %d but expected %d", actual_offset[Y],
+		      driver_data.offset[Y]);
+	zassert_equal(actual_offset[Z], driver_data.offset[Z],
+		      "Z offset is %d but expected %d", actual_offset[Z],
+		      driver_data.offset[Z]);
+}
+
+ZTEST(stm_mems_common, test_st_get_data_rate)
+{
+	int expected_data_rate = 456;
+	int rv;
+
+	struct stprivate_data driver_data = {
+		.base = {
+			.odr = expected_data_rate,
+		},
+	};
+
+	const struct motion_sensor_t sensor = {
+		.drv_data = &driver_data,
+	};
+
+	rv = st_get_data_rate(&sensor);
+	zassert_equal(rv, expected_data_rate, "rv is %d but expected %d", rv,
+		      expected_data_rate);
+}
+
+ZTEST(stm_mems_common, test_st_normalize)
+{
+	struct stprivate_data driver_data = {
+		.resol = 12, /* 12 bits of useful data (arbitrary) */
+		.offset = {  /* Arbitrary offsets */
+			[X] = -100,
+			[Y] = 200,
+			[Z] = 100,
+		},
+	};
+	/* Fixed-point identity matrix that performs no rotation. */
+	const mat33_fp_t identity_rot_matrix = {
+		{ INT_TO_FP(1), INT_TO_FP(0), INT_TO_FP(0) },
+		{ INT_TO_FP(0), INT_TO_FP(1), INT_TO_FP(0) },
+		{ INT_TO_FP(0), INT_TO_FP(0), INT_TO_FP(1) },
+	};
+	const struct motion_sensor_t sensor = {
+		.drv_data = &driver_data,
+		.rot_standard_ref = &identity_rot_matrix,
+		.current_range = 32, /* used to scale offsets (arbitrary) */
+	};
+
+	/* Accelerometer data is passed in with the format:
+	 * (lower address)                  (higher address)
+	 *  [X LSB] [X MSB] [Y LSB] [Y MSB] [Z LSB] [Z MSB]
+	 *
+	 * The LSB are left-aligned and contain noise/junk data
+	 * in their least-significant bit positions. When interpreted
+	 * as int16 samples, the `driver_data.resol`-count most
+	 * significant bits are what we actually use. For this test, we
+	 * set `resol` to 12, so there will be 12 useful bits and 4 noise
+	 * bits. This test (and the EC code) assume we are compiling on
+	 * a little-endian machine. The samples themselvesare unsigned and
+	 * biased at 2^12/2 = 2^11.
+	 */
+	uint16_t input_reading[] = {
+		((BIT(11) - 100) << 4) | 0x000a,
+		((BIT(11) + 0) << 4) | 0x000b,
+		((BIT(11) + 100) << 4) | 0x000c,
+	};
+
+	/* Expected outputs w/ noise bits suppressed and offsets applied.
+	 * Note that the data stays left-aligned.
+	 */
+	intv3_t expected_output = {
+		((BIT(11) - 100) << 4) + driver_data.offset[X],
+		((BIT(11) + 0) << 4) + driver_data.offset[Y],
+		((BIT(11) + 100) << 4) + driver_data.offset[Z],
+	};
+
+	intv3_t actual_output = { 0 };
+
+	st_normalize(&sensor, (int *)&actual_output, (uint8_t *)input_reading);
+
+	zassert_within(actual_output[X], expected_output[X], 0.5f,
+		       "X output is %d but expected %d", actual_output[X],
+		       expected_output[X]);
+	zassert_within(actual_output[Y], expected_output[Y], 0.5f,
+		       "Y output is %d but expected %d", actual_output[Y],
+		       expected_output[Y]);
+	zassert_within(actual_output[Z], expected_output[Z], 0.5f,
+		       "Z output is %d but expected %d", actual_output[Z],
+		       expected_output[Z]);
+}
+
+static void stm_mems_common_before(void *state)
+{
+	ARG_UNUSED(state);
+	i2c_mock_reset(MOCK_EMUL);
+}
+
+ZTEST_SUITE(stm_mems_common, drivers_predicate_post_main, NULL,
+	    stm_mems_common_before, NULL, NULL);
diff --git a/zephyr/test/drivers/default/src/tablet_mode.c b/zephyr/test/drivers/default/src/tablet_mode.c
new file mode 100644
index 0000000000..773f2c2bf8
--- /dev/null
+++ b/zephyr/test/drivers/default/src/tablet_mode.c
@@ -0,0 +1,172 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "tablet_mode.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/fff.h>
+#include <zephyr/kernel.h>
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+static void tabletmode_before(void *state)
+{
+	ARG_UNUSED(state);
+	tablet_reset();
+}
+
+static void tabletmode_after(void *state)
+{
+	ARG_UNUSED(state);
+	tablet_reset();
+}
+
+/**
+ * @brief TestPurpose: various tablet_set_mode operations, make sure lid and
+ * base works independently.
+ */
+ZTEST_USER(tabletmode, test_tablet_set_mode)
+{
+	int ret;
+
+	ret = tablet_get_mode();
+	zassert_equal(ret, 0, "unexpected tablet initial mode: %d", ret);
+
+	tablet_set_mode(1, TABLET_TRIGGER_LID);
+	ret = tablet_get_mode();
+	zassert_equal(ret, 1, "unexpected tablet mode: %d", ret);
+
+	tablet_set_mode(1, TABLET_TRIGGER_BASE);
+	ret = tablet_get_mode();
+	zassert_equal(ret, 1, "unexpected tablet mode: %d", ret);
+
+	/**
+	 * Tablet mode should remain enabled, since both _LID and _BASE were set
+	 * previously, and this only clears _LID.
+	 */
+	tablet_set_mode(0, TABLET_TRIGGER_LID);
+	ret = tablet_get_mode();
+	zassert_equal(ret, 1, "unexpected tablet mode: %d", ret);
+
+	/**
+	 * Both _LID and _BASE are now cleared, so DUT is no longer in tablet
+	 * mode.
+	 */
+	tablet_set_mode(0, TABLET_TRIGGER_BASE);
+	ret = tablet_get_mode();
+	zassert_equal(ret, 0, "unexpected tablet mode: %d", ret);
+}
+
+/**
+ * @brief TestPurpose: test the tablet_disable functionality.
+ */
+ZTEST_USER(tabletmode, test_tablet_disable)
+{
+	int ret;
+
+	ret = tablet_get_mode();
+	zassert_equal(ret, 0, "unexpected tablet initial mode: %d", ret);
+
+	tablet_disable();
+	tablet_set_mode(1, TABLET_TRIGGER_LID);
+
+	ret = tablet_get_mode();
+	zassert_equal(ret, 0, "unexpected tablet mode: %d", ret);
+}
+
+/**
+ * @brief TestPurpose: check that tabletmode on and off changes the mode.
+ */
+ZTEST_USER(tabletmode, test_settabletmode_on_off)
+{
+	int ret;
+
+	ret = tablet_get_mode();
+	zassert_equal(ret, 0, "unexpected tablet initial mode: %d", ret);
+
+	ret = shell_execute_cmd(get_ec_shell(), "tabletmode");
+	zassert_equal(ret, EC_SUCCESS, "unexpected command return status: %d",
+		      ret);
+
+	ret = tablet_get_mode();
+	zassert_equal(ret, 0, "unexpected tablet mode: %d", ret);
+
+	ret = shell_execute_cmd(get_ec_shell(), "tabletmode on");
+	zassert_equal(ret, EC_SUCCESS, "unexpected command return status: %d",
+		      ret);
+
+	ret = tablet_get_mode();
+	zassert_equal(ret, 1, "unexpected tablet mode: %d", ret);
+
+	ret = shell_execute_cmd(get_ec_shell(), "tabletmode off");
+	zassert_equal(ret, EC_SUCCESS, "unexpected command return status: %d",
+		      ret);
+
+	ret = tablet_get_mode();
+	zassert_equal(ret, 0, "unexpected tablet mode: %d", ret);
+}
+
+/**
+ * @brief TestPurpose: ensure that console tabletmode forces the status,
+ * inhibiting tablet_set_mode, and then unforce it with reset.
+ */
+ZTEST_USER(tabletmode, test_settabletmode_forced)
+{
+	int ret;
+
+	ret = tablet_get_mode();
+	zassert_equal(ret, 0, "unexpected tablet initial mode: %d", ret);
+
+	ret = shell_execute_cmd(get_ec_shell(), "tabletmode on");
+	zassert_equal(ret, EC_SUCCESS, "unexpected command return status: %d",
+		      ret);
+
+	ret = tablet_get_mode();
+	zassert_equal(ret, 1, "unexpected tablet mode: %d", ret);
+
+	tablet_set_mode(0, TABLET_TRIGGER_LID);
+
+	ret = tablet_get_mode();
+	zassert_equal(ret, 1, "unexpected tablet mode: %d", ret);
+
+	ret = shell_execute_cmd(get_ec_shell(), "tabletmode reset");
+	zassert_equal(ret, EC_SUCCESS, "unexpected command return status: %d",
+		      ret);
+
+	tablet_set_mode(0, TABLET_TRIGGER_LID);
+
+	ret = tablet_get_mode();
+	zassert_equal(ret, 0, "unexpected tablet mode: %d", ret);
+}
+
+/**
+ * @brief TestPurpose: check the "too many arguments" case.
+ */
+ZTEST_USER(tabletmode, test_settabletmode_too_many_args)
+{
+	int ret;
+
+	ret = shell_execute_cmd(get_ec_shell(),
+				"tabletmode too many arguments");
+	zassert_equal(ret, EC_ERROR_PARAM_COUNT,
+		      "unexpected command return status: %d", ret);
+}
+
+/**
+ * @brief TestPurpose: check the "unknown argument" case.
+ */
+ZTEST_USER(tabletmode, test_settabletmode_unknown_arg)
+{
+	int ret;
+
+	ret = shell_execute_cmd(get_ec_shell(), "tabletmode X");
+	zassert_equal(ret, EC_ERROR_PARAM1,
+		      "unexpected command return status: %d", ret);
+}
+
+ZTEST_SUITE(tabletmode, drivers_predicate_post_main, NULL, tabletmode_before,
+	    tabletmode_after, NULL);
diff --git a/zephyr/test/drivers/default/src/task.c b/zephyr/test/drivers/default/src/task.c
new file mode 100644
index 0000000000..4c4087c5a1
--- /dev/null
+++ b/zephyr/test/drivers/default/src/task.c
@@ -0,0 +1,84 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "task.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "timer.h"
+
+#include <zephyr/ztest.h>
+
+struct tasks_fixture {
+	timestamp_t fake_time;
+};
+
+static void *setup(void)
+{
+	static struct tasks_fixture fixture;
+
+	return &fixture;
+}
+
+static void before(void *f)
+{
+	struct tasks_fixture *fixture = f;
+
+	fixture->fake_time.val = 0;
+}
+
+static void after(void *f)
+{
+	ARG_UNUSED(f);
+
+	get_time_mock = NULL;
+}
+
+ZTEST_SUITE(tasks, drivers_predicate_post_main, setup, before, after, NULL);
+
+ZTEST(tasks, test_enable_irq)
+{
+	arch_irq_disable(0);
+	task_enable_irq(0);
+	zassert_true(arch_irq_is_enabled(0));
+}
+
+ZTEST(tasks, test_interrupt_context)
+{
+	zassert_false(in_interrupt_context());
+}
+
+ZTEST_F(tasks, test_timer_arm_before_now)
+{
+	timestamp_t deadline = {
+		.val = 5,
+	};
+
+	fixture->fake_time.val = 15;
+	get_time_mock = &fixture->fake_time;
+
+	zassert_ok(timer_arm(deadline, TASK_ID_MOTIONSENSE));
+	zassert_equal(*task_get_event_bitmap(TASK_ID_MOTIONSENSE) &
+			      TASK_EVENT_TIMER,
+		      TASK_EVENT_TIMER);
+}
+
+ZTEST_F(tasks, test_timer_arm_busy)
+{
+	timestamp_t deadline = {
+		.val = UINT64_C(5000000),
+	};
+
+	fixture->fake_time.val = 0;
+	get_time_mock = &fixture->fake_time;
+
+	zassert_ok(timer_arm(deadline, TASK_ID_MOTIONSENSE));
+	zassert_equal(EC_ERROR_BUSY, timer_arm(deadline, TASK_ID_MOTIONSENSE));
+}
+
+ZTEST(tasks, test_get_event_bitmap_invalid_tid)
+{
+	zassert_is_null(
+		task_get_event_bitmap(TASK_ID_COUNT + EXTRA_TASK_COUNT));
+}
diff --git a/zephyr/test/drivers/default/src/tcpci.c b/zephyr/test/drivers/default/src/tcpci.c
new file mode 100644
index 0000000000..9cc4b6c25f
--- /dev/null
+++ b/zephyr/test/drivers/default/src/tcpci.c
@@ -0,0 +1,582 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "ec_tasks.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/tcpc/emul_tcpci.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "tcpm/tcpci.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/tcpci_test_common.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+#define TCPCI_EMUL_NODE DT_NODELABEL(tcpci_emul)
+
+/* Convenience pointer directly to the TCPCI mux under test */
+static struct usb_mux *tcpci_usb_mux;
+
+/** Test TCPCI init and vbus level */
+ZTEST(tcpci, test_generic_tcpci_init)
+{
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
+
+	test_tcpci_init(emul, common_data, USBC_PORT_C0);
+}
+
+/** Test TCPCI release */
+ZTEST(tcpci, test_generic_tcpci_release)
+{
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
+
+	test_tcpci_release(emul, common_data, USBC_PORT_C0);
+}
+
+/** Test TCPCI get cc */
+ZTEST(tcpci, test_generic_tcpci_get_cc)
+{
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
+
+	test_tcpci_get_cc(emul, common_data, USBC_PORT_C0);
+}
+
+/** Test TCPCI set cc */
+ZTEST(tcpci, test_generic_tcpci_set_cc)
+{
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
+
+	test_tcpci_set_cc(emul, common_data, USBC_PORT_C0);
+}
+
+/** Test TCPCI set polarity */
+ZTEST(tcpci, test_generic_tcpci_set_polarity)
+{
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
+
+	test_tcpci_set_polarity(emul, common_data, USBC_PORT_C0);
+}
+
+/** Test TCPCI set vconn */
+ZTEST(tcpci, test_generic_tcpci_set_vconn)
+{
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
+
+	test_tcpci_set_vconn(emul, common_data, USBC_PORT_C0);
+}
+
+/** Test TCPCI set msg header */
+ZTEST(tcpci, test_generic_tcpci_set_msg_header)
+{
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
+
+	test_tcpci_set_msg_header(emul, common_data, USBC_PORT_C0);
+}
+
+/** Test TCPCI rx and sop prime enable */
+ZTEST(tcpci, test_generic_tcpci_set_rx_detect)
+{
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
+
+	test_tcpci_set_rx_detect(emul, common_data, USBC_PORT_C0);
+}
+
+/** Test TCPCI get vbus voltage */
+ZTEST(tcpci, test_generic_tcpci_get_vbus_voltage)
+{
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
+
+	test_tcpci_get_vbus_voltage(emul, common_data, USBC_PORT_C0);
+}
+
+/** Test TCPCI get raw message from TCPC revision 2.0 */
+ZTEST(tcpci, test_generic_tcpci_get_rx_message_raw_rev2)
+{
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
+
+	/* Revision 2.0 is set by default in test_rules */
+	test_tcpci_get_rx_message_raw(emul, common_data, USBC_PORT_C0);
+}
+
+/** Test TCPCI get raw message from TCPC revision 1.0 */
+ZTEST(tcpci, test_generic_tcpci_get_rx_message_raw_rev1)
+{
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
+
+	tcpc_config[USBC_PORT_C0].flags = 0;
+	tcpci_emul_set_rev(emul, TCPCI_EMUL_REV1_0_VER1_0);
+
+	test_tcpci_get_rx_message_raw(emul, common_data, USBC_PORT_C0);
+}
+
+/** Test TCPCI transmitting message from TCPC revision 2.0 */
+ZTEST(tcpci, test_generic_tcpci_transmit_rev2)
+{
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
+
+	/* Revision 2.0 is set by default in test_rules */
+	test_tcpci_transmit(emul, common_data, USBC_PORT_C0);
+}
+
+/** Test TCPCI transmitting message from TCPC revision 1.0 */
+ZTEST(tcpci, test_generic_tcpci_transmit_rev1)
+{
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
+
+	tcpc_config[USBC_PORT_C0].flags = 0;
+	tcpci_emul_set_rev(emul, TCPCI_EMUL_REV1_0_VER1_0);
+
+	test_tcpci_transmit(emul, common_data, USBC_PORT_C0);
+}
+
+/** Test TCPCI alert */
+ZTEST(tcpci, test_generic_tcpci_alert)
+{
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
+
+	test_tcpci_alert(emul, common_data, USBC_PORT_C0);
+}
+
+/** Test TCPCI alert RX message */
+ZTEST(tcpci, test_generic_tcpci_alert_rx_message)
+{
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
+
+	test_tcpci_alert_rx_message(emul, common_data, USBC_PORT_C0);
+}
+
+/** Test TCPCI auto discharge on disconnect */
+ZTEST(tcpci, test_generic_tcpci_auto_discharge)
+{
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
+
+	test_tcpci_auto_discharge(emul, common_data, USBC_PORT_C0);
+}
+
+/** Test TCPCI drp toggle */
+ZTEST(tcpci, test_generic_tcpci_drp_toggle)
+{
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
+
+	test_tcpci_drp_toggle(emul, common_data, USBC_PORT_C0);
+}
+
+/** Test TCPCI get chip info */
+ZTEST(tcpci, test_generic_tcpci_get_chip_info)
+{
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
+
+	test_tcpci_get_chip_info(emul, common_data, USBC_PORT_C0);
+
+	zassert_equal(EC_ERROR_INVAL,
+		      tcpci_get_chip_info(board_get_usb_pd_port_count(), false,
+					  NULL),
+		      "get_chip_info should return INVAL for an invalid port");
+}
+
+/** Test TCPCI enter low power mode */
+ZTEST(tcpci, test_generic_tcpci_low_power_mode)
+{
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
+
+	test_tcpci_low_power_mode(emul, common_data, USBC_PORT_C0);
+}
+
+/** Test TCPCI set bist test mode */
+ZTEST(tcpci, test_generic_tcpci_set_bist_mode)
+{
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
+
+	test_tcpci_set_bist_mode(emul, common_data, USBC_PORT_C0);
+}
+
+/** Test TCPCI discharge vbus */
+ZTEST(tcpci, test_generic_tcpci_discharge_vbus)
+{
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	uint8_t exp_ctrl, initial_ctrl;
+
+	/* Set initial value for POWER ctrl register. Chosen arbitrary. */
+	initial_ctrl = TCPC_REG_POWER_CTRL_VBUS_VOL_MONITOR_DIS |
+		       TCPC_REG_POWER_CTRL_VOLT_ALARM_DIS;
+	tcpci_emul_set_reg(emul, TCPC_REG_POWER_CTRL, initial_ctrl);
+
+	/* Test discharge enable */
+	exp_ctrl = initial_ctrl | TCPC_REG_POWER_CTRL_FORCE_DISCHARGE;
+	tcpci_tcpc_discharge_vbus(USBC_PORT_C0, 1);
+	check_tcpci_reg(emul, TCPC_REG_POWER_CTRL, exp_ctrl);
+
+	/* Test discharge disable */
+	exp_ctrl = initial_ctrl & ~TCPC_REG_POWER_CTRL_FORCE_DISCHARGE;
+	tcpci_tcpc_discharge_vbus(USBC_PORT_C0, 0);
+	check_tcpci_reg(emul, TCPC_REG_POWER_CTRL, exp_ctrl);
+}
+
+/** Test TCPC xfer */
+ZTEST(tcpci, test_tcpc_xfer)
+{
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	uint16_t val, exp_val;
+	uint8_t reg;
+
+	/* Set value to register (value and register chosen arbitrary) */
+	exp_val = 0x7fff;
+	reg = TCPC_REG_ALERT_MASK;
+	tcpci_emul_set_reg(emul, reg, exp_val);
+
+	/* Test reading value using tcpc_xfer() function */
+	zassert_equal(EC_SUCCESS,
+		      tcpc_xfer(USBC_PORT_C0, &reg, 1, (uint8_t *)&val, 2),
+		      NULL);
+	zassert_equal(exp_val, val, "0x%x != 0x%x", exp_val, val);
+}
+
+/** Test TCPCI debug accessory enable/disable */
+ZTEST(tcpci, test_generic_tcpci_debug_accessory)
+{
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	uint8_t exp_val, initial_val;
+
+	/* Set initial value for STD output register. Chosen arbitrary. */
+	initial_val = TCPC_REG_CONFIG_STD_OUTPUT_AUDIO_CONN_N |
+		      TCPC_REG_CONFIG_STD_OUTPUT_MUX_USB |
+		      TCPC_REG_CONFIG_STD_OUTPUT_CONNECTOR_FLIPPED |
+		      TCPC_REG_CONFIG_STD_OUTPUT_DBG_ACC_CONN_N;
+	tcpci_emul_set_reg(emul, TCPC_REG_CONFIG_STD_OUTPUT, initial_val);
+
+	/* Test debug accessory connect */
+	exp_val = initial_val & ~TCPC_REG_CONFIG_STD_OUTPUT_DBG_ACC_CONN_N;
+	tcpci_tcpc_debug_accessory(USBC_PORT_C0, 1);
+	check_tcpci_reg(emul, TCPC_REG_CONFIG_STD_OUTPUT, exp_val);
+
+	/* Test debug accessory disconnect */
+	exp_val = initial_val | TCPC_REG_CONFIG_STD_OUTPUT_DBG_ACC_CONN_N;
+	tcpci_tcpc_debug_accessory(USBC_PORT_C0, 0);
+	check_tcpci_reg(emul, TCPC_REG_CONFIG_STD_OUTPUT, exp_val);
+}
+
+/* Setup TCPCI usb mux to behave as it is used only for usb mux */
+static void set_usb_mux_not_tcpc(void)
+{
+	tcpci_usb_mux->flags = USB_MUX_FLAG_NOT_TCPC;
+}
+
+/* Setup TCPCI usb mux to behave as it is used for usb mux and TCPC */
+static void set_usb_mux_tcpc(void)
+{
+	tcpci_usb_mux->flags = 0;
+}
+
+/** Test TCPCI mux init */
+ZTEST(tcpci, test_generic_tcpci_mux_init)
+{
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
+	const struct usb_mux *tcpci_usb_mux = usb_muxes[USBC_PORT_C0].mux;
+
+	/* Set as usb mux with TCPC for first init call */
+	set_usb_mux_tcpc();
+
+	/* Make sure that TCPC is not accessed */
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_FAIL_ALL_REG);
+	zassert_equal(EC_SUCCESS, tcpci_tcpm_mux_init(tcpci_usb_mux));
+
+	/* Set as only usb mux without TCPC for rest of the test */
+	set_usb_mux_not_tcpc();
+
+	/* Test fail on power status read */
+	i2c_common_emul_set_read_fail_reg(common_data, TCPC_REG_POWER_STATUS);
+	zassert_equal(EC_ERROR_INVAL, tcpci_tcpm_mux_init(tcpci_usb_mux));
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test fail on uninitialised bit set */
+	tcpci_emul_set_reg(emul, TCPC_REG_POWER_STATUS,
+			   TCPC_REG_POWER_STATUS_UNINIT);
+	zassert_equal(EC_ERROR_TIMEOUT, tcpci_tcpm_mux_init(tcpci_usb_mux),
+		      NULL);
+	tcpci_emul_set_reg(emul, TCPC_REG_POWER_STATUS, 0);
+
+	/* Set default power status for rest of the test */
+	zassert_ok(tcpci_emul_set_vbus_level(emul, VBUS_REMOVED));
+
+	/* Test fail on alert mask write fail */
+	i2c_common_emul_set_write_fail_reg(common_data, TCPC_REG_ALERT_MASK);
+	zassert_equal(EC_ERROR_UNKNOWN, tcpci_tcpm_mux_init(tcpci_usb_mux),
+		      NULL);
+
+	/* Test fail on alert write fail */
+	i2c_common_emul_set_write_fail_reg(common_data, TCPC_REG_ALERT);
+	zassert_equal(EC_ERROR_UNKNOWN, tcpci_tcpm_mux_init(tcpci_usb_mux),
+		      NULL);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Set arbitrary value to alert and alert mask registers */
+	tcpci_emul_set_reg(emul, TCPC_REG_ALERT, 0xffff);
+	tcpci_emul_set_reg(emul, TCPC_REG_ALERT_MASK, 0xffff);
+
+	/* Test success init */
+	zassert_equal(EC_SUCCESS, tcpci_tcpm_mux_init(tcpci_usb_mux));
+	check_tcpci_reg(emul, TCPC_REG_ALERT_MASK, 0);
+	check_tcpci_reg(emul, TCPC_REG_ALERT, 0);
+}
+
+/** Test TCPCI mux enter low power mode */
+ZTEST(tcpci, test_generic_tcpci_mux_enter_low_power)
+{
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
+	const struct usb_mux *tcpci_usb_mux = usb_muxes[USBC_PORT_C0].mux;
+
+	/* Set as usb mux with TCPC for first enter_low_power call */
+	set_usb_mux_tcpc();
+
+	/* Make sure that TCPC is not accessed */
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_FAIL_ALL_REG);
+	zassert_equal(EC_SUCCESS, tcpci_tcpm_mux_enter_low_power(tcpci_usb_mux),
+		      NULL);
+
+	/* Set as only usb mux without TCPC for rest of the test */
+	set_usb_mux_not_tcpc();
+
+	/* Test error on failed command set */
+	i2c_common_emul_set_write_fail_reg(common_data, TCPC_REG_COMMAND);
+	zassert_equal(EC_ERROR_INVAL,
+		      tcpci_tcpm_mux_enter_low_power(tcpci_usb_mux), NULL);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test correct command is issued */
+	zassert_equal(EC_SUCCESS, tcpci_tcpm_mux_enter_low_power(tcpci_usb_mux),
+		      NULL);
+	check_tcpci_reg(emul, TCPC_REG_COMMAND, TCPC_REG_COMMAND_I2CIDLE);
+}
+
+/** Test TCPCI mux set and get */
+static void test_generic_tcpci_mux_set_get(void)
+{
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
+	const struct usb_mux *tcpci_usb_mux = usb_muxes[USBC_PORT_C0].mux;
+	mux_state_t mux_state, mux_state_get;
+	uint16_t exp_val, initial_val;
+	bool ack;
+
+	mux_state = USB_PD_MUX_NONE;
+
+	/* Test fail on standard output config register read */
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  TCPC_REG_CONFIG_STD_OUTPUT);
+	zassert_equal(EC_ERROR_INVAL,
+		      tcpci_tcpm_mux_set(tcpci_usb_mux, mux_state, &ack), NULL);
+	zassert_equal(EC_ERROR_INVAL,
+		      tcpci_tcpm_mux_get(tcpci_usb_mux, &mux_state_get), NULL);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test fail on standard output config register write */
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   TCPC_REG_CONFIG_STD_OUTPUT);
+	zassert_equal(EC_ERROR_INVAL,
+		      tcpci_tcpm_mux_set(tcpci_usb_mux, mux_state, &ack), NULL);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Set initial value for STD output register. Chosen arbitrary. */
+	initial_val = TCPC_REG_CONFIG_STD_OUTPUT_AUDIO_CONN_N |
+		      TCPC_REG_CONFIG_STD_OUTPUT_MUX_USB |
+		      TCPC_REG_CONFIG_STD_OUTPUT_CONNECTOR_FLIPPED |
+		      TCPC_REG_CONFIG_STD_OUTPUT_DBG_ACC_CONN_N;
+	tcpci_emul_set_reg(emul, TCPC_REG_CONFIG_STD_OUTPUT, initial_val);
+
+	/* Test setting/getting no MUX connection without polarity inverted */
+	exp_val = (initial_val & ~TCPC_REG_CONFIG_STD_OUTPUT_MUX_MASK) |
+		  TCPC_REG_CONFIG_STD_OUTPUT_MUX_NONE;
+	exp_val &= ~TCPC_REG_CONFIG_STD_OUTPUT_CONNECTOR_FLIPPED;
+	mux_state = USB_PD_MUX_NONE;
+	zassert_equal(EC_SUCCESS,
+		      tcpci_tcpm_mux_set(tcpci_usb_mux, mux_state, &ack), NULL);
+	check_tcpci_reg(emul, TCPC_REG_CONFIG_STD_OUTPUT, exp_val);
+	zassert_false(ack, "Ack from host shouldn't be required");
+	zassert_equal(EC_SUCCESS,
+		      tcpci_tcpm_mux_get(tcpci_usb_mux, &mux_state_get), NULL);
+	zassert_equal(mux_state, mux_state_get, "Expected state 0x%x, got 0x%x",
+		      mux_state, mux_state_get);
+
+	/* Test setting/getting MUX DP with polarity inverted */
+	exp_val = (initial_val & ~TCPC_REG_CONFIG_STD_OUTPUT_MUX_MASK) |
+		  TCPC_REG_CONFIG_STD_OUTPUT_MUX_DP |
+		  TCPC_REG_CONFIG_STD_OUTPUT_CONNECTOR_FLIPPED;
+	mux_state = USB_PD_MUX_DP_ENABLED | USB_PD_MUX_POLARITY_INVERTED;
+	zassert_equal(EC_SUCCESS,
+		      tcpci_tcpm_mux_set(tcpci_usb_mux, mux_state, &ack), NULL);
+	check_tcpci_reg(emul, TCPC_REG_CONFIG_STD_OUTPUT, exp_val);
+	zassert_false(ack, "Ack from host shouldn't be required");
+	zassert_equal(EC_SUCCESS,
+		      tcpci_tcpm_mux_get(tcpci_usb_mux, &mux_state_get), NULL);
+	zassert_equal(mux_state, mux_state_get, "Expected state 0x%x, got 0x%x",
+		      mux_state, mux_state_get);
+
+	/* Test setting/getting MUX USB without polarity inverted */
+	exp_val = (initial_val & ~TCPC_REG_CONFIG_STD_OUTPUT_MUX_MASK) |
+		  TCPC_REG_CONFIG_STD_OUTPUT_MUX_USB;
+	exp_val &= ~TCPC_REG_CONFIG_STD_OUTPUT_CONNECTOR_FLIPPED;
+	mux_state = USB_PD_MUX_USB_ENABLED;
+	zassert_equal(EC_SUCCESS,
+		      tcpci_tcpm_mux_set(tcpci_usb_mux, mux_state, &ack), NULL);
+	check_tcpci_reg(emul, TCPC_REG_CONFIG_STD_OUTPUT, exp_val);
+	zassert_false(ack, "Ack from host shouldn't be required");
+	zassert_equal(EC_SUCCESS,
+		      tcpci_tcpm_mux_get(tcpci_usb_mux, &mux_state_get), NULL);
+	zassert_equal(mux_state, mux_state_get, "Expected state 0x%x, got 0x%x",
+		      mux_state, mux_state_get);
+
+	/* Test setting/getting MUX USB and DP with polarity inverted */
+	exp_val = (initial_val & ~TCPC_REG_CONFIG_STD_OUTPUT_MUX_MASK) |
+		  TCPC_REG_CONFIG_STD_OUTPUT_MUX_DP |
+		  TCPC_REG_CONFIG_STD_OUTPUT_MUX_USB |
+		  TCPC_REG_CONFIG_STD_OUTPUT_CONNECTOR_FLIPPED;
+	mux_state = USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED |
+		    USB_PD_MUX_POLARITY_INVERTED;
+	zassert_equal(EC_SUCCESS,
+		      tcpci_tcpm_mux_set(tcpci_usb_mux, mux_state, &ack), NULL);
+	check_tcpci_reg(emul, TCPC_REG_CONFIG_STD_OUTPUT, exp_val);
+	zassert_false(ack, "Ack from host shouldn't be required");
+	zassert_equal(EC_SUCCESS,
+		      tcpci_tcpm_mux_get(tcpci_usb_mux, &mux_state_get), NULL);
+	zassert_equal(mux_state, mux_state_get, "Expected state 0x%x, got 0x%x",
+		      mux_state, mux_state_get);
+}
+
+ZTEST(tcpci, test_generic_tcpci_mux_set_get)
+{
+	test_generic_tcpci_mux_set_get();
+}
+
+ZTEST(tcpci, test_generic_tcpci_mux_set_get__not_tcpc)
+{
+	set_usb_mux_not_tcpc();
+	test_generic_tcpci_mux_set_get();
+	set_usb_mux_tcpc();
+}
+
+ZTEST(tcpci, test_generic_tcpci_hard_reset_reinit)
+{
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
+
+	test_tcpci_hard_reset_reinit(emul, common_data, USBC_PORT_C0);
+}
+
+void validate_mux_read_write16(const struct usb_mux *tcpci_usb_mux)
+{
+	const int reg = TCPC_REG_ALERT;
+	const int expected = 65261;
+	int restore = 0;
+	int temp = 0;
+
+	zassert_ok(mux_read16(tcpci_usb_mux, reg, &restore),
+		   "Failed to read mux");
+
+	if (IS_ENABLED(CONFIG_BUG_249829957)) {
+		zassert_ok(mux_write16(tcpci_usb_mux, reg, expected),
+			   "Failed to write mux");
+		zassert_ok(mux_read16(tcpci_usb_mux, reg, &temp),
+			   "Failed to read mux");
+		zassert_equal(expected, temp, "expected=0x%X, read=0x%X",
+			      expected, temp);
+	}
+
+	zassert_ok(mux_write16(tcpci_usb_mux, reg, restore),
+		   "Failed to write mux");
+}
+
+/** Test usb_mux read/write APIs */
+ZTEST(tcpci, test_usb_mux_read_write)
+{
+	const int flags_restore = tcpci_usb_mux->flags;
+
+	/* Configure mux read/writes for TCPC APIs */
+	tcpci_usb_mux->flags &= ~USB_MUX_FLAG_NOT_TCPC;
+	validate_mux_read_write16(tcpci_usb_mux);
+
+	/* Configure mux read/writes for I2C APIs */
+	tcpci_usb_mux->flags |= USB_MUX_FLAG_NOT_TCPC;
+	validate_mux_read_write16(tcpci_usb_mux);
+
+	tcpci_usb_mux->flags = flags_restore;
+}
+
+static void *tcpci_setup(void)
+{
+	/* This test suite assumes that first usb mux for port C0 is TCPCI */
+	__ASSERT(usb_muxes[USBC_PORT_C0].mux->driver ==
+			 &tcpci_tcpm_usb_mux_driver,
+		 "Invalid config of usb_muxes in test/drivers/src/stubs.c");
+
+	tcpci_usb_mux = (struct usb_mux *)usb_muxes[USBC_PORT_C0].mux;
+
+	return NULL;
+}
+
+static void tcpci_after(void *state)
+{
+	set_usb_mux_tcpc();
+}
+
+ZTEST_SUITE(tcpci, drivers_predicate_pre_main, tcpci_setup, NULL, tcpci_after,
+	    NULL);
diff --git a/zephyr/test/drivers/default/src/tcpci_test_common.c b/zephyr/test/drivers/default/src/tcpci_test_common.c
new file mode 100644
index 0000000000..b0255d345e
--- /dev/null
+++ b/zephyr/test/drivers/default/src/tcpci_test_common.c
@@ -0,0 +1,1102 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/tcpc/emul_tcpci.h"
+#include "tcpm/tcpci.h"
+#include "test/drivers/tcpci_test_common.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+/** Check TCPC register value */
+void check_tcpci_reg_f(const struct emul *emul, int reg, uint16_t exp_val,
+		       int line)
+{
+	uint16_t reg_val;
+
+	zassert_ok(tcpci_emul_get_reg(emul, reg, &reg_val),
+		   "Failed tcpci_emul_get_reg(); line: %d", line);
+	zassert_equal(exp_val, reg_val, "Expected 0x%x, got 0x%x; line: %d",
+		      exp_val, reg_val, line);
+}
+
+/** Check TCPC register value with mask */
+void check_tcpci_reg_with_mask_f(const struct emul *emul, int reg,
+				 uint16_t exp_val, uint16_t mask, int line)
+{
+	uint16_t reg_val;
+
+	zassert_ok(tcpci_emul_get_reg(emul, reg, &reg_val),
+		   "Failed tcpci_emul_get_reg(); line: %d", line);
+	zassert_equal(exp_val & mask, reg_val & mask,
+		      "Expected 0x%x, got 0x%x, mask 0x%x; line: %d", exp_val,
+		      reg_val, mask, line);
+}
+
+/** Test TCPCI init and vbus level */
+void test_tcpci_init(const struct emul *emul,
+		     struct i2c_common_emul_data *common_data,
+		     enum usbc_port port)
+{
+	const struct tcpm_drv *drv = tcpc_config[port].drv;
+	uint16_t exp_mask;
+
+	tcpc_config[port].flags |= TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V;
+
+	/* Test fail on power status read */
+	i2c_common_emul_set_read_fail_reg(common_data, TCPC_REG_POWER_STATUS);
+	zassert_equal(EC_ERROR_INVAL, drv->init(port));
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test fail on uninitialised bit set */
+	tcpci_emul_set_reg(emul, TCPC_REG_POWER_STATUS,
+			   TCPC_REG_POWER_STATUS_UNINIT);
+	zassert_equal(EC_ERROR_TIMEOUT, drv->init(port));
+	tcpci_emul_set_reg(emul, TCPC_REG_POWER_STATUS, 0);
+
+	/*
+	 * Set expected alert mask. It is used in test until vSafe0V tcpc
+	 * config flag is revmoved.
+	 */
+	exp_mask = TCPC_REG_ALERT_TX_SUCCESS | TCPC_REG_ALERT_TX_FAILED |
+		   TCPC_REG_ALERT_TX_DISCARDED | TCPC_REG_ALERT_RX_STATUS |
+		   TCPC_REG_ALERT_RX_HARD_RST | TCPC_REG_ALERT_CC_STATUS |
+		   TCPC_REG_ALERT_FAULT | TCPC_REG_ALERT_POWER_STATUS;
+
+	/* Set TCPCI emulator VBUS to safe0v (disconnected) */
+	zassert_ok(tcpci_emul_set_vbus_level(emul, VBUS_SAFE0V));
+
+	/* Test init with VBUS safe0v without vSafe0V tcpc config flag */
+	zassert_equal(EC_SUCCESS, drv->init(port));
+	zassert_true(drv->check_vbus_level(port, VBUS_SAFE0V));
+	zassert_false(drv->check_vbus_level(port, VBUS_PRESENT));
+	check_tcpci_reg(emul, TCPC_REG_POWER_STATUS_MASK,
+			TCPC_REG_POWER_STATUS_VBUS_PRES);
+	check_tcpci_reg(emul, TCPC_REG_ALERT_MASK, exp_mask);
+
+	/* Set TCPCI emulator VBUS to present (connected, above 4V) */
+	zassert_ok(tcpci_emul_set_vbus_level(emul, VBUS_PRESENT));
+
+	/* Test init with VBUS present without vSafe0V tcpc config flag */
+	zassert_equal(EC_SUCCESS, drv->init(port));
+	zassert_false(drv->check_vbus_level(port, VBUS_SAFE0V));
+	zassert_true(drv->check_vbus_level(port, VBUS_PRESENT));
+	check_tcpci_reg(emul, TCPC_REG_POWER_STATUS_MASK,
+			TCPC_REG_POWER_STATUS_VBUS_PRES);
+	check_tcpci_reg(emul, TCPC_REG_ALERT_MASK, exp_mask);
+
+	/* Disable vSafe0V tcpc config flag and update expected alert mask */
+	exp_mask |= TCPC_REG_ALERT_EXT_STATUS;
+	tcpc_config[port].flags = TCPC_FLAGS_TCPCI_REV2_0;
+
+	/* Test init with VBUS present with vSafe0V tcpc config flag */
+	zassert_equal(EC_SUCCESS, drv->init(port));
+	zassert_false(drv->check_vbus_level(port, VBUS_SAFE0V));
+	zassert_true(drv->check_vbus_level(port, VBUS_PRESENT));
+	check_tcpci_reg(emul, TCPC_REG_POWER_STATUS_MASK,
+			TCPC_REG_POWER_STATUS_VBUS_PRES);
+	check_tcpci_reg(emul, TCPC_REG_ALERT_MASK, exp_mask);
+
+	/* Set TCPCI emulator VBUS to safe0v (disconnected) */
+	zassert_ok(tcpci_emul_set_vbus_level(emul, VBUS_SAFE0V));
+
+	/* Test init with VBUS safe0v with vSafe0V tcpc config flag */
+	zassert_equal(EC_SUCCESS, drv->init(port));
+	zassert_true(drv->check_vbus_level(port, VBUS_SAFE0V));
+	zassert_false(drv->check_vbus_level(port, VBUS_PRESENT));
+	check_tcpci_reg(emul, TCPC_REG_POWER_STATUS_MASK,
+			TCPC_REG_POWER_STATUS_VBUS_PRES);
+	check_tcpci_reg(emul, TCPC_REG_ALERT_MASK, exp_mask);
+
+	/*
+	 * Set TCPCI emulator VBUS to disconnected but not at vSafe0V
+	 * (VBUS in 0.8V - 3.5V range)
+	 */
+	zassert_ok(tcpci_emul_set_vbus_level(emul, VBUS_REMOVED));
+
+	/* Test init with VBUS not safe0v with vSafe0V tcpc config flag */
+	zassert_equal(EC_SUCCESS, drv->init(port));
+	zassert_false(drv->check_vbus_level(port, VBUS_SAFE0V));
+	zassert_false(drv->check_vbus_level(port, VBUS_PRESENT));
+	check_tcpci_reg(emul, TCPC_REG_POWER_STATUS_MASK,
+			TCPC_REG_POWER_STATUS_VBUS_PRES);
+	check_tcpci_reg(emul, TCPC_REG_ALERT_MASK, exp_mask);
+}
+
+/** Test TCPCI release */
+void test_tcpci_release(const struct emul *emul,
+			struct i2c_common_emul_data *common_data,
+			enum usbc_port port)
+{
+	const struct tcpm_drv *drv = tcpc_config[port].drv;
+
+	tcpci_emul_set_reg(emul, TCPC_REG_ALERT, 0xffff);
+
+	zassert_equal(EC_SUCCESS, drv->release(port));
+	check_tcpci_reg(emul, TCPC_REG_POWER_STATUS_MASK, 0);
+	check_tcpci_reg(emul, TCPC_REG_ALERT_MASK, 0);
+	check_tcpci_reg(emul, TCPC_REG_ALERT, 0);
+}
+
+/** Test TCPCI get cc */
+void test_tcpci_get_cc(const struct emul *emul,
+		       struct i2c_common_emul_data *common_data,
+		       enum usbc_port port)
+{
+	const struct tcpm_drv *drv = tcpc_config[port].drv;
+	enum tcpc_cc_voltage_status cc1, cc2;
+	uint16_t cc_status, role_ctrl;
+
+	struct {
+		/* TCPCI CC status register */
+		enum tcpc_cc_voltage_status cc[2];
+		bool connect_result;
+		/* TCPCI ROLE ctrl register */
+		enum tcpc_cc_pull role_cc[2];
+		enum tcpc_drp drp;
+	} test_param[] = {
+		/* Test DRP with open state */
+		{
+			.cc = { TYPEC_CC_VOLT_OPEN, TYPEC_CC_VOLT_OPEN },
+			.connect_result = false,
+			.drp = TYPEC_DRP,
+		},
+		/* Test DRP with cc1 open state, cc2 src RA */
+		{
+			.cc = { TYPEC_CC_VOLT_OPEN, TYPEC_CC_VOLT_RA },
+			.connect_result = false,
+			.drp = TYPEC_DRP,
+		},
+		/* Test DRP with cc1 src RA, cc2 src RD */
+		{
+			.cc = { TYPEC_CC_VOLT_RA, TYPEC_CC_VOLT_RD },
+			.connect_result = false,
+			.drp = TYPEC_DRP,
+		},
+		/* Test DRP with cc1 snk open, cc2 snk default */
+		{
+			.cc = { TYPEC_CC_VOLT_OPEN, TYPEC_CC_VOLT_RP_DEF },
+			.connect_result = true,
+			.drp = TYPEC_DRP,
+		},
+		/* Test DRP with cc1 snk 1.5, cc2 snk 3.0 */
+		{
+			.cc = { TYPEC_CC_VOLT_RP_1_5, TYPEC_CC_VOLT_RP_3_0 },
+			.connect_result = true,
+			.drp = TYPEC_DRP,
+		},
+		/* Test no DRP with cc1 src open, cc2 src RA */
+		{
+			.cc = { TYPEC_CC_VOLT_OPEN, TYPEC_CC_VOLT_RA },
+			.connect_result = false,
+			.drp = TYPEC_NO_DRP,
+			.role_cc = { TYPEC_CC_RP, TYPEC_CC_RP },
+		},
+		/* Test no DRP with cc1 src RD, cc2 snk default */
+		{
+			.cc = { TYPEC_CC_VOLT_RD, TYPEC_CC_VOLT_RP_DEF },
+			.connect_result = false,
+			.drp = TYPEC_NO_DRP,
+			.role_cc = { TYPEC_CC_RP, TYPEC_CC_RD },
+		},
+		/* Test no DRP with cc1 snk default, cc2 snk open */
+		{
+			.cc = { TYPEC_CC_VOLT_RP_DEF, TYPEC_CC_VOLT_OPEN },
+			.connect_result = false,
+			.drp = TYPEC_NO_DRP,
+			.role_cc = { TYPEC_CC_RD, TYPEC_CC_RD },
+		},
+		/* Test no DRP with cc1 snk 3.0, cc2 snk 1.5 */
+		{
+			.cc = { TYPEC_CC_VOLT_RP_3_0, TYPEC_CC_VOLT_RP_1_5 },
+			.connect_result = false,
+			.drp = TYPEC_NO_DRP,
+			.role_cc = { TYPEC_CC_RD, TYPEC_CC_RD },
+		},
+	};
+
+	for (int i = 0; i < ARRAY_SIZE(test_param); i++) {
+		role_ctrl = TCPC_REG_ROLE_CTRL_SET(test_param[i].drp, 0,
+						   test_param[i].role_cc[0],
+						   test_param[i].role_cc[1]);
+		/* If CC status is TYPEC_CC_VOLT_RP_*, then BIT(2) is ignored */
+		cc_status = TCPC_REG_CC_STATUS_SET(test_param[i].connect_result,
+						   test_param[i].cc[0],
+						   test_param[i].cc[1]);
+		tcpci_emul_set_reg(emul, TCPC_REG_ROLE_CTRL, role_ctrl);
+		tcpci_emul_set_reg(emul, TCPC_REG_CC_STATUS, cc_status);
+		zassert_equal(
+			EC_SUCCESS, drv->get_cc(port, &cc1, &cc2),
+			"Failed to get CC in test case %d (CC 0x%x, role 0x%x)",
+			i, cc_status, role_ctrl);
+		zassert_equal(
+			test_param[i].cc[0], cc1,
+			"0x%x != (cc1 = 0x%x) in test case %d (CC 0x%x, role 0x%x)",
+			test_param[i].cc[0], cc1, i, cc_status, role_ctrl);
+		zassert_equal(
+			test_param[i].cc[1], cc2,
+			"0x%x != (cc2 = 0x%x) in test case %d (CC 0x%x, role 0x%x)",
+			test_param[i].cc[0], cc1, i, cc_status, role_ctrl);
+	}
+}
+
+/** Test TCPCI set cc */
+void test_tcpci_set_cc(const struct emul *emul,
+		       struct i2c_common_emul_data *common_data,
+		       enum usbc_port port)
+{
+	const struct tcpm_drv *drv = tcpc_config[port].drv;
+	enum tcpc_rp_value rp;
+	enum tcpc_cc_pull cc;
+
+	/* Test setting default RP and cc open */
+	rp = TYPEC_RP_USB;
+	cc = TYPEC_CC_OPEN;
+	zassert_equal(EC_SUCCESS, drv->select_rp_value(port, rp));
+	zassert_equal(EC_SUCCESS, drv->set_cc(port, cc));
+	check_tcpci_reg(emul, TCPC_REG_ROLE_CTRL,
+			TCPC_REG_ROLE_CTRL_SET(TYPEC_NO_DRP, rp, cc, cc));
+
+	/* Test error on failed role ctrl set */
+	i2c_common_emul_set_write_fail_reg(common_data, TCPC_REG_ROLE_CTRL);
+	zassert_equal(EC_ERROR_INVAL, drv->set_cc(port, TYPEC_CC_OPEN));
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test setting 1.5 RP and cc RD */
+	rp = TYPEC_RP_1A5;
+	cc = TYPEC_CC_RD;
+	zassert_equal(EC_SUCCESS, drv->select_rp_value(port, rp));
+	zassert_equal(EC_SUCCESS, drv->set_cc(port, cc));
+	check_tcpci_reg(emul, TCPC_REG_ROLE_CTRL,
+			TCPC_REG_ROLE_CTRL_SET(TYPEC_NO_DRP, rp, cc, cc));
+
+	/* Test setting 3.0 RP and cc RP */
+	rp = TYPEC_RP_3A0;
+	cc = TYPEC_CC_RP;
+	zassert_equal(EC_SUCCESS, drv->select_rp_value(port, rp));
+	zassert_equal(EC_SUCCESS, drv->set_cc(port, cc));
+	check_tcpci_reg(emul, TCPC_REG_ROLE_CTRL,
+			TCPC_REG_ROLE_CTRL_SET(TYPEC_NO_DRP, rp, cc, cc));
+
+	/*
+	 * Test setting 3.0 RP and cc RA. drv->select_rp_value() is
+	 * intentionally not called to check if selected rp is persistent.
+	 */
+	cc = TYPEC_CC_RA;
+	zassert_equal(EC_SUCCESS, drv->set_cc(port, cc));
+	check_tcpci_reg(emul, TCPC_REG_ROLE_CTRL,
+			TCPC_REG_ROLE_CTRL_SET(TYPEC_NO_DRP, rp, cc, cc));
+}
+
+/** Test TCPCI set polarity */
+void test_tcpci_set_polarity(const struct emul *emul,
+			     struct i2c_common_emul_data *common_data,
+			     enum usbc_port port)
+{
+	const struct tcpm_drv *drv = tcpc_config[port].drv;
+	uint8_t initial_ctrl;
+	uint8_t exp_ctrl;
+
+	/* Set initial value for TCPC ctrl register. Chosen arbitrary. */
+	initial_ctrl = TCPC_REG_TCPC_CTRL_DEBUG_ACC_CONTROL |
+		       TCPC_REG_TCPC_CTRL_BIST_TEST_MODE;
+	tcpci_emul_set_reg(emul, TCPC_REG_TCPC_CTRL, initial_ctrl);
+
+	/* Test error on failed polarity set */
+	exp_ctrl = initial_ctrl;
+	i2c_common_emul_set_write_fail_reg(common_data, TCPC_REG_TCPC_CTRL);
+	zassert_equal(EC_ERROR_INVAL, drv->set_polarity(port, POLARITY_CC2),
+		      NULL);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+	check_tcpci_reg(emul, TCPC_REG_TCPC_CTRL, exp_ctrl);
+
+	/* Test setting polarity CC2 */
+	exp_ctrl = initial_ctrl | TCPC_REG_TCPC_CTRL_SET(1);
+	zassert_equal(EC_SUCCESS, drv->set_polarity(port, POLARITY_CC2));
+	check_tcpci_reg(emul, TCPC_REG_TCPC_CTRL, exp_ctrl);
+
+	/* Test setting polarity CC1 */
+	exp_ctrl = initial_ctrl & ~TCPC_REG_TCPC_CTRL_SET(1);
+	zassert_equal(EC_SUCCESS, drv->set_polarity(port, POLARITY_CC1));
+	check_tcpci_reg(emul, TCPC_REG_TCPC_CTRL, exp_ctrl);
+
+	/* Test setting polarity CC2 DTS */
+	exp_ctrl = initial_ctrl | TCPC_REG_TCPC_CTRL_SET(1);
+	zassert_equal(EC_SUCCESS, drv->set_polarity(port, POLARITY_CC2_DTS),
+		      NULL);
+	check_tcpci_reg(emul, TCPC_REG_TCPC_CTRL, exp_ctrl);
+
+	/* Test setting polarity CC1 DTS */
+	exp_ctrl = initial_ctrl & ~TCPC_REG_TCPC_CTRL_SET(1);
+	zassert_equal(EC_SUCCESS, drv->set_polarity(port, POLARITY_CC1_DTS),
+		      NULL);
+	check_tcpci_reg(emul, TCPC_REG_TCPC_CTRL, exp_ctrl);
+}
+
+/** Test TCPCI set vconn */
+void test_tcpci_set_vconn(const struct emul *emul,
+			  struct i2c_common_emul_data *common_data,
+			  enum usbc_port port)
+{
+	const struct tcpm_drv *drv = tcpc_config[port].drv;
+	uint8_t initial_ctrl;
+	uint8_t exp_ctrl;
+
+	/* Set initial value for POWER ctrl register. Chosen arbitrary. */
+	initial_ctrl = TCPC_REG_POWER_CTRL_VBUS_VOL_MONITOR_DIS |
+		       TCPC_REG_POWER_CTRL_FORCE_DISCHARGE;
+	tcpci_emul_set_reg(emul, TCPC_REG_POWER_CTRL, initial_ctrl);
+
+	/* Test error on failed vconn set */
+	exp_ctrl = initial_ctrl;
+	i2c_common_emul_set_write_fail_reg(common_data, TCPC_REG_POWER_CTRL);
+	zassert_equal(EC_ERROR_INVAL, drv->set_vconn(port, 1));
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+	check_tcpci_reg(emul, TCPC_REG_POWER_CTRL, exp_ctrl);
+
+	/* Test vconn enable */
+	exp_ctrl = initial_ctrl | TCPC_REG_POWER_CTRL_SET(1);
+	zassert_equal(EC_SUCCESS, drv->set_vconn(port, 1));
+	check_tcpci_reg(emul, TCPC_REG_POWER_CTRL, exp_ctrl);
+
+	/* Test vconn disable */
+	exp_ctrl = initial_ctrl & ~TCPC_REG_POWER_CTRL_SET(1);
+	zassert_equal(EC_SUCCESS, drv->set_vconn(port, 0));
+	check_tcpci_reg(emul, TCPC_REG_POWER_CTRL, exp_ctrl);
+}
+
+/** Test TCPCI set msg header */
+void test_tcpci_set_msg_header(const struct emul *emul,
+			       struct i2c_common_emul_data *common_data,
+			       enum usbc_port port)
+{
+	const struct tcpm_drv *drv = tcpc_config[port].drv;
+
+	/* Test error on failed header set */
+	i2c_common_emul_set_write_fail_reg(common_data, TCPC_REG_MSG_HDR_INFO);
+	zassert_equal(EC_ERROR_INVAL,
+		      drv->set_msg_header(port, PD_ROLE_SINK, PD_ROLE_UFP),
+		      NULL);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test setting sink UFP */
+	zassert_equal(EC_SUCCESS,
+		      drv->set_msg_header(port, PD_ROLE_SINK, PD_ROLE_UFP),
+		      NULL);
+	check_tcpci_reg(emul, TCPC_REG_MSG_HDR_INFO,
+			TCPC_REG_MSG_HDR_INFO_SET(PD_ROLE_UFP, PD_ROLE_SINK));
+
+	/* Test setting sink DFP */
+	zassert_equal(EC_SUCCESS,
+		      drv->set_msg_header(port, PD_ROLE_SINK, PD_ROLE_DFP),
+		      NULL);
+	check_tcpci_reg(emul, TCPC_REG_MSG_HDR_INFO,
+			TCPC_REG_MSG_HDR_INFO_SET(PD_ROLE_DFP, PD_ROLE_SINK));
+
+	/* Test setting source UFP */
+	zassert_equal(EC_SUCCESS,
+		      drv->set_msg_header(port, PD_ROLE_SOURCE, PD_ROLE_UFP),
+		      NULL);
+	check_tcpci_reg(emul, TCPC_REG_MSG_HDR_INFO,
+			TCPC_REG_MSG_HDR_INFO_SET(PD_ROLE_UFP, PD_ROLE_SOURCE));
+
+	/* Test setting source DFP */
+	zassert_equal(EC_SUCCESS,
+		      drv->set_msg_header(port, PD_ROLE_SOURCE, PD_ROLE_DFP),
+		      NULL);
+	check_tcpci_reg(emul, TCPC_REG_MSG_HDR_INFO,
+			TCPC_REG_MSG_HDR_INFO_SET(PD_ROLE_DFP, PD_ROLE_SOURCE));
+}
+
+/** Test TCPCI rx and sop prime enable */
+void test_tcpci_set_rx_detect(const struct emul *emul,
+			      struct i2c_common_emul_data *common_data,
+			      enum usbc_port port)
+{
+	const struct tcpm_drv *drv = tcpc_config[port].drv;
+
+	/* Test error from rx_enable on rx detect set */
+	i2c_common_emul_set_write_fail_reg(common_data, TCPC_REG_RX_DETECT);
+	zassert_equal(EC_ERROR_INVAL, drv->set_rx_enable(port, 1));
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test rx disable */
+	zassert_equal(EC_SUCCESS, drv->set_rx_enable(port, 0));
+	check_tcpci_reg(emul, TCPC_REG_RX_DETECT, 0x0);
+
+	/* Test setting sop prime with rx disable doesn't change RX_DETECT */
+	zassert_equal(EC_SUCCESS, drv->sop_prime_enable(port, 1));
+	check_tcpci_reg(emul, TCPC_REG_RX_DETECT, 0x0);
+
+	/* Test that enabling rx after sop prime will set RX_DETECT properly */
+	zassert_equal(EC_SUCCESS, drv->set_rx_enable(port, 1));
+	check_tcpci_reg(emul, TCPC_REG_RX_DETECT,
+			TCPC_REG_RX_DETECT_SOP_SOPP_SOPPP_HRST_MASK);
+
+	/* Test error from sop_prime on rx detect set */
+	i2c_common_emul_set_write_fail_reg(common_data, TCPC_REG_RX_DETECT);
+	zassert_equal(EC_ERROR_INVAL, drv->sop_prime_enable(port, 0));
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test disabling sop prime with rx enabled does change RX_DETECT */
+	zassert_equal(EC_SUCCESS, drv->sop_prime_enable(port, 0));
+	check_tcpci_reg(emul, TCPC_REG_RX_DETECT,
+			TCPC_REG_RX_DETECT_SOP_HRST_MASK);
+
+	/* Test that enabling rx after disabling sop prime set RX_DETECT */
+	zassert_equal(EC_SUCCESS, drv->set_rx_enable(port, 0));
+	check_tcpci_reg(emul, TCPC_REG_RX_DETECT, 0x0);
+	zassert_equal(EC_SUCCESS, drv->set_rx_enable(port, 1));
+	check_tcpci_reg(emul, TCPC_REG_RX_DETECT,
+			TCPC_REG_RX_DETECT_SOP_HRST_MASK);
+}
+
+/** Test TCPCI get raw message from TCPC */
+void test_tcpci_get_rx_message_raw(const struct emul *emul,
+				   struct i2c_common_emul_data *common_data,
+				   enum usbc_port port)
+{
+	const struct tcpm_drv *drv = tcpc_config[port].drv;
+	struct tcpci_emul_msg msg;
+	uint32_t payload[7];
+	uint16_t rx_mask;
+	uint8_t buf[32];
+	int exp_head;
+	int i, head;
+	int size;
+
+	tcpci_emul_set_reg(emul, TCPC_REG_ALERT, 0x0);
+	tcpci_emul_set_reg(emul, TCPC_REG_DEV_CAP_2,
+			   TCPC_REG_DEV_CAP_2_LONG_MSG);
+	tcpci_emul_set_reg(emul, TCPC_REG_RX_DETECT,
+			   TCPC_REG_RX_DETECT_SOP | TCPC_REG_RX_DETECT_SOPP);
+
+	for (i = 0; i < 32; i++) {
+		buf[i] = i + 1;
+	}
+	msg.buf = buf;
+	msg.cnt = 31;
+	msg.sop_type = TCPCI_MSG_SOP;
+	zassert_equal(TCPCI_EMUL_TX_SUCCESS,
+		      tcpci_emul_add_rx_msg(emul, &msg, true),
+		      "Failed to setup emulator message");
+
+	/* Test fail on reading byte count */
+	i2c_common_emul_set_read_fail_reg(common_data, TCPC_REG_RX_BUFFER);
+	zassert_equal(EC_ERROR_UNKNOWN,
+		      drv->get_message_raw(port, payload, &head), NULL);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	/* Get raw message should always clean RX alerts */
+	rx_mask = TCPC_REG_ALERT_RX_BUF_OVF | TCPC_REG_ALERT_RX_STATUS;
+	check_tcpci_reg_with_mask(emul, TCPC_REG_ALERT, 0x0, rx_mask);
+
+	/* Test too short message */
+	msg.cnt = 1;
+	zassert_equal(TCPCI_EMUL_TX_SUCCESS,
+		      tcpci_emul_add_rx_msg(emul, &msg, true),
+		      "Failed to setup emulator message");
+	zassert_equal(EC_ERROR_UNKNOWN,
+		      drv->get_message_raw(port, payload, &head), NULL);
+	check_tcpci_reg_with_mask(emul, TCPC_REG_ALERT, 0x0, rx_mask);
+
+	/* Test too long message */
+	msg.cnt = 31;
+	zassert_equal(TCPCI_EMUL_TX_SUCCESS,
+		      tcpci_emul_add_rx_msg(emul, &msg, true),
+		      "Failed to setup emulator message");
+	zassert_equal(EC_ERROR_UNKNOWN,
+		      drv->get_message_raw(port, payload, &head), NULL);
+	check_tcpci_reg_with_mask(emul, TCPC_REG_ALERT, 0x0, rx_mask);
+
+	/* Test alert register and message payload on success */
+	size = 28;
+	msg.cnt = size + 2;
+	msg.sop_type = TCPCI_MSG_SOP_PRIME;
+	zassert_equal(TCPCI_EMUL_TX_SUCCESS,
+		      tcpci_emul_add_rx_msg(emul, &msg, true),
+		      "Failed to setup emulator message");
+	zassert_equal(EC_SUCCESS, drv->get_message_raw(port, payload, &head),
+		      NULL);
+	check_tcpci_reg_with_mask(emul, TCPC_REG_ALERT, 0x0, rx_mask);
+	/*
+	 * Type is in bits 31-28 of header, buf[0] is in bits 7-0,
+	 * buf[1] is in bits 15-8
+	 */
+	exp_head = (TCPCI_MSG_SOP_PRIME << 28) | (buf[1] << 8) | buf[0];
+	zassert_equal(exp_head, head,
+		      "Received header 0x%08lx, expected 0x%08lx", head,
+		      exp_head);
+	zassert_mem_equal(payload, buf + 2, size, NULL);
+}
+
+/** Test TCPCI transmitting message from TCPC */
+void test_tcpci_transmit(const struct emul *emul,
+			 struct i2c_common_emul_data *common_data,
+			 enum usbc_port port)
+{
+	const struct tcpm_drv *drv = tcpc_config[port].drv;
+	struct tcpci_emul_msg *msg;
+	uint32_t data[6];
+	uint16_t header;
+	int i;
+
+	msg = tcpci_emul_get_tx_msg(emul);
+
+	/* Fill transmit data with pattern */
+	for (i = 0; i < 6 * sizeof(uint32_t); i++) {
+		((uint8_t *)data)[i] = i;
+	}
+
+	/* Test transmit hard reset fail */
+	i2c_common_emul_set_write_fail_reg(common_data, TCPC_REG_TRANSMIT);
+	zassert_equal(EC_ERROR_INVAL,
+		      drv->transmit(port, TCPCI_MSG_TX_HARD_RESET, 0, NULL),
+		      NULL);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test transmit cabel reset */
+	zassert_equal(EC_SUCCESS,
+		      drv->transmit(port, TCPCI_MSG_CABLE_RESET, 0, NULL),
+		      NULL);
+	zassert_equal(TCPCI_MSG_CABLE_RESET, msg->sop_type);
+
+	/* Test transmit hard reset */
+	zassert_equal(EC_SUCCESS,
+		      drv->transmit(port, TCPCI_MSG_TX_HARD_RESET, 0, NULL),
+		      NULL);
+	zassert_equal(TCPCI_MSG_TX_HARD_RESET, msg->sop_type);
+
+	/* Test transmit fail on rx buffer */
+	i2c_common_emul_set_write_fail_reg(common_data, TCPC_REG_TX_BUFFER);
+	zassert_equal(EC_ERROR_INVAL,
+		      drv->transmit(port, TCPCI_MSG_SOP_PRIME, 0, data), NULL);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test transmit only header */
+	/* Build random header with count 0 */
+	header = PD_HEADER(PD_CTRL_PING, PD_ROLE_SOURCE, PD_ROLE_UFP, 0, 0,
+			   PD_REV20, 0);
+	zassert_equal(EC_SUCCESS,
+		      drv->transmit(port, TCPCI_MSG_SOP_PRIME, header, data),
+		      NULL);
+	zassert_equal(TCPCI_MSG_SOP_PRIME, msg->sop_type);
+	zassert_mem_equal(msg->buf, &header, 2, NULL);
+	zassert_equal(2, msg->cnt);
+
+	/* Test transmit message */
+	/* Build random header with count 6 */
+	header = PD_HEADER(PD_CTRL_PING, PD_ROLE_SOURCE, PD_ROLE_UFP, 0, 6,
+			   PD_REV20, 0);
+	zassert_equal(EC_SUCCESS,
+		      drv->transmit(port, TCPCI_MSG_SOP_PRIME, header, data),
+		      NULL);
+	zassert_equal(TCPCI_MSG_SOP_PRIME, msg->sop_type);
+	zassert_mem_equal(msg->buf, &header, 2, NULL);
+	zassert_mem_equal(msg->buf + 2, data, 6 * sizeof(uint32_t), NULL);
+	zassert_equal(2 + 6 * sizeof(uint32_t), msg->cnt);
+}
+
+/** Test TCPCI alert */
+void test_tcpci_alert(const struct emul *emul,
+		      struct i2c_common_emul_data *common_data,
+		      enum usbc_port port)
+{
+	const struct tcpm_drv *drv = tcpc_config[port].drv;
+
+	/* Test alert read fail */
+	i2c_common_emul_set_read_fail_reg(common_data, TCPC_REG_ALERT);
+	drv->tcpc_alert(port);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Handle overcurrent */
+	tcpci_emul_set_reg(emul, TCPC_REG_ALERT, TCPC_REG_ALERT_FAULT);
+	tcpci_emul_set_reg(emul, TCPC_REG_FAULT_STATUS,
+			   TCPC_REG_FAULT_STATUS_VCONN_OVER_CURRENT);
+	drv->tcpc_alert(port);
+	check_tcpci_reg(emul, TCPC_REG_ALERT, 0x0);
+	check_tcpci_reg(emul, TCPC_REG_FAULT_STATUS, 0x0);
+
+	/* Test TX complete */
+	tcpci_emul_set_reg(emul, TCPC_REG_ALERT, TCPC_REG_ALERT_TX_COMPLETE);
+	drv->tcpc_alert(port);
+
+	/* Test clear alert and ext_alert */
+	tcpci_emul_set_reg(emul, TCPC_REG_ALERT, TCPC_REG_ALERT_ALERT_EXT);
+	tcpci_emul_set_reg(emul, TCPC_REG_ALERT_EXT,
+			   TCPC_REG_ALERT_EXT_TIMER_EXPIRED);
+	drv->tcpc_alert(port);
+	check_tcpci_reg(emul, TCPC_REG_ALERT, 0x0);
+	check_tcpci_reg(emul, TCPC_REG_FAULT_STATUS, 0x0);
+
+	/* Test CC changed, CC status chosen arbitrary */
+	tcpci_emul_set_reg(emul, TCPC_REG_CC_STATUS,
+			   TCPC_REG_CC_STATUS_SET(1, TYPEC_CC_VOLT_RP_1_5,
+						  TYPEC_CC_VOLT_RP_3_0));
+	tcpci_emul_set_reg(emul, TCPC_REG_ALERT, TCPC_REG_ALERT_CC_STATUS);
+	drv->tcpc_alert(port);
+
+	/* Test Hard reset */
+	tcpci_emul_set_reg(emul, TCPC_REG_ALERT, TCPC_REG_ALERT_RX_HARD_RST);
+	drv->tcpc_alert(port);
+}
+
+/** Test TCPCI alert RX message */
+void test_tcpci_alert_rx_message(const struct emul *emul,
+				 struct i2c_common_emul_data *common_data,
+				 enum usbc_port port)
+{
+	const struct tcpm_drv *drv = tcpc_config[port].drv;
+	struct tcpci_emul_msg msg1, msg2;
+	uint8_t buf1[32], buf2[32];
+	uint32_t payload[7];
+	int exp_head;
+	int i, head;
+	int size;
+
+	tcpci_emul_set_reg(emul, TCPC_REG_DEV_CAP_2,
+			   TCPC_REG_DEV_CAP_2_LONG_MSG);
+	tcpci_emul_set_reg(emul, TCPC_REG_RX_DETECT,
+			   TCPC_REG_RX_DETECT_SOP | TCPC_REG_RX_DETECT_SOPP);
+
+	for (i = 0; i < 32; i++) {
+		buf1[i] = i + 1;
+		buf2[i] = i + 33;
+	}
+	size = 23;
+	msg1.buf = buf1;
+	msg1.cnt = size + 3;
+	msg1.sop_type = TCPCI_MSG_SOP;
+
+	msg2.buf = buf2;
+	msg2.cnt = size + 3;
+	msg2.sop_type = TCPCI_MSG_SOP_PRIME;
+
+	/* Test receiving one message */
+	zassert_equal(TCPCI_EMUL_TX_SUCCESS,
+		      tcpci_emul_add_rx_msg(emul, &msg1, true),
+		      "Failed to setup emulator message");
+	drv->tcpc_alert(port);
+	check_tcpci_reg(emul, TCPC_REG_ALERT, 0x0);
+
+	/* Check if msg1 is in queue */
+	zassert_true(tcpm_has_pending_message(port));
+	zassert_equal(EC_SUCCESS, tcpm_dequeue_message(port, payload, &head),
+		      NULL);
+	exp_head = (TCPCI_MSG_SOP << 28) | (buf1[1] << 8) | buf1[0];
+	zassert_equal(exp_head, head,
+		      "Received header 0x%08lx, expected 0x%08lx", head,
+		      exp_head);
+	zassert_mem_equal(payload, buf1 + 2, size, NULL);
+	zassert_false(tcpm_has_pending_message(port));
+
+	/* Test receiving two messages */
+	zassert_equal(TCPCI_EMUL_TX_SUCCESS,
+		      tcpci_emul_add_rx_msg(emul, &msg1, true),
+		      "Failed to setup emulator message");
+	zassert_equal(TCPCI_EMUL_TX_SUCCESS,
+		      tcpci_emul_add_rx_msg(emul, &msg2, true),
+		      "Failed to setup emulator message");
+	drv->tcpc_alert(port);
+	check_tcpci_reg(emul, TCPC_REG_ALERT, 0x0);
+
+	/* Check if msg1 is in queue */
+	zassert_true(tcpm_has_pending_message(port));
+	zassert_equal(EC_SUCCESS, tcpm_dequeue_message(port, payload, &head),
+		      NULL);
+	exp_head = (TCPCI_MSG_SOP << 28) | (buf1[1] << 8) | buf1[0];
+	zassert_equal(exp_head, head,
+		      "Received header 0x%08lx, expected 0x%08lx", head,
+		      exp_head);
+	zassert_mem_equal(payload, buf1 + 2, size, NULL);
+	/* Check if msg2 is in queue */
+	zassert_true(tcpm_has_pending_message(port));
+	zassert_equal(EC_SUCCESS, tcpm_dequeue_message(port, payload, &head),
+		      NULL);
+	exp_head = (TCPCI_MSG_SOP_PRIME << 28) | (buf2[1] << 8) | buf2[0];
+	zassert_equal(exp_head, head,
+		      "Received header 0x%08lx, expected 0x%08lx", head,
+		      exp_head);
+	zassert_mem_equal(payload, buf2 + 2, size, NULL);
+	zassert_false(tcpm_has_pending_message(port));
+
+	/* Test with too long first message */
+	msg1.cnt = 32;
+	tcpci_emul_set_reg(emul, TCPC_REG_DEV_CAP_2,
+			   TCPC_REG_DEV_CAP_2_LONG_MSG);
+	zassert_equal(TCPCI_EMUL_TX_SUCCESS,
+		      tcpci_emul_add_rx_msg(emul, &msg1, true),
+		      "Failed to setup emulator message");
+	zassert_equal(TCPCI_EMUL_TX_SUCCESS,
+		      tcpci_emul_add_rx_msg(emul, &msg2, true),
+		      "Failed to setup emulator message");
+	drv->tcpc_alert(port);
+	check_tcpci_reg(emul, TCPC_REG_ALERT, 0x0);
+
+	/* Check if msg2 is in queue */
+	zassert_true(tcpm_has_pending_message(port));
+	zassert_equal(EC_SUCCESS, tcpm_dequeue_message(port, payload, &head),
+		      NULL);
+	exp_head = (TCPCI_MSG_SOP_PRIME << 28) | (buf2[1] << 8) | buf2[0];
+	zassert_equal(exp_head, head,
+		      "Received header 0x%08lx, expected 0x%08lx", head,
+		      exp_head);
+	zassert_mem_equal(payload, buf2 + 2, size, NULL);
+	zassert_false(tcpm_has_pending_message(port));
+
+	/* Test constant read message failure */
+	zassert_equal(TCPCI_EMUL_TX_SUCCESS,
+		      tcpci_emul_add_rx_msg(emul, &msg1, true),
+		      "Failed to setup emulator message");
+	/* Create loop with one message with wrong size */
+	msg1.next = &msg1;
+	drv->tcpc_alert(port);
+	/* Nothing should be in queue */
+	zassert_false(tcpm_has_pending_message(port));
+
+	/* Test constant correct messages stream */
+	msg1.cnt = size + 3;
+	drv->tcpc_alert(port);
+	msg1.next = NULL;
+
+	/* msg1 should be at least twice in queue */
+	exp_head = (TCPCI_MSG_SOP << 28) | (buf1[1] << 8) | buf1[0];
+	for (i = 0; i < 2; i++) {
+		zassert_true(tcpm_has_pending_message(port));
+		zassert_equal(EC_SUCCESS,
+			      tcpm_dequeue_message(port, payload, &head), NULL);
+		zassert_equal(exp_head, head,
+			      "Received header 0x%08lx, expected 0x%08lx", head,
+			      exp_head);
+		zassert_mem_equal(payload, buf1 + 2, size, NULL);
+	}
+	tcpm_clear_pending_messages(port);
+	zassert_false(tcpm_has_pending_message(port));
+
+	/* Read message that is left in TCPC buffer */
+	drv->tcpc_alert(port);
+	check_tcpci_reg(emul, TCPC_REG_ALERT, 0x0);
+
+	/* Check if msg1 is in queue */
+	zassert_true(tcpm_has_pending_message(port));
+	zassert_equal(EC_SUCCESS, tcpm_dequeue_message(port, payload, &head),
+		      NULL);
+	exp_head = (TCPCI_MSG_SOP << 28) | (buf1[1] << 8) | buf1[0];
+	zassert_equal(exp_head, head,
+		      "Received header 0x%08lx, expected 0x%08lx", head,
+		      exp_head);
+	zassert_mem_equal(payload, buf1 + 2, size, NULL);
+	zassert_false(tcpm_has_pending_message(port));
+}
+
+/** Test TCPCI auto discharge on disconnect */
+void test_tcpci_auto_discharge(const struct emul *emul,
+			       struct i2c_common_emul_data *common_data,
+			       enum usbc_port port)
+{
+	const struct tcpm_drv *drv = tcpc_config[port].drv;
+	uint8_t initial_ctrl;
+	uint8_t exp_ctrl;
+
+	/* Set initial value for POWER ctrl register. Chosen arbitrary. */
+	initial_ctrl = TCPC_REG_POWER_CTRL_VBUS_VOL_MONITOR_DIS |
+		       TCPC_REG_POWER_CTRL_FORCE_DISCHARGE;
+	tcpci_emul_set_reg(emul, TCPC_REG_POWER_CTRL, initial_ctrl);
+
+	/* Test discharge enable */
+	exp_ctrl = initial_ctrl | TCPC_REG_POWER_CTRL_AUTO_DISCHARGE_DISCONNECT;
+	drv->tcpc_enable_auto_discharge_disconnect(port, 1);
+	check_tcpci_reg(emul, TCPC_REG_POWER_CTRL, exp_ctrl);
+
+	/* Test discharge disable */
+	exp_ctrl = initial_ctrl &
+		   ~TCPC_REG_POWER_CTRL_AUTO_DISCHARGE_DISCONNECT;
+	drv->tcpc_enable_auto_discharge_disconnect(port, 0);
+	check_tcpci_reg(emul, TCPC_REG_POWER_CTRL, exp_ctrl);
+}
+
+/** Test TCPCI drp toggle */
+void test_tcpci_drp_toggle(const struct emul *emul,
+			   struct i2c_common_emul_data *common_data,
+			   enum usbc_port port)
+{
+	const struct tcpm_drv *drv = tcpc_config[port].drv;
+	uint8_t exp_tcpc_ctrl, exp_role_ctrl, initial_tcpc_ctrl;
+
+	/* Test error on failed role CTRL set */
+	i2c_common_emul_set_write_fail_reg(common_data, TCPC_REG_ROLE_CTRL);
+	zassert_equal(EC_ERROR_INVAL, drv->drp_toggle(port));
+
+	/* Test error on failed TCPC CTRL set */
+	i2c_common_emul_set_write_fail_reg(common_data, TCPC_REG_TCPC_CTRL);
+	zassert_equal(EC_ERROR_INVAL, drv->drp_toggle(port));
+
+	/* Test error on failed command set */
+	i2c_common_emul_set_write_fail_reg(common_data, TCPC_REG_COMMAND);
+	zassert_equal(EC_ERROR_INVAL, drv->drp_toggle(port));
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Set initial value for TCPC ctrl register. Chosen arbitrary. */
+	initial_tcpc_ctrl = TCPC_REG_TCPC_CTRL_DEBUG_ACC_CONTROL |
+			    TCPC_REG_TCPC_CTRL_BIST_TEST_MODE;
+	tcpci_emul_set_reg(emul, TCPC_REG_TCPC_CTRL, initial_tcpc_ctrl);
+
+	/*
+	 * Test correct registers values for rev 2.0. Role control CC lines
+	 * have to be set to RP with DRP enabled and smallest RP value.
+	 */
+	exp_tcpc_ctrl = initial_tcpc_ctrl |
+			TCPC_REG_TCPC_CTRL_EN_LOOK4CONNECTION_ALERT;
+	exp_role_ctrl = TCPC_REG_ROLE_CTRL_SET(TYPEC_DRP, TYPEC_RP_USB,
+					       TYPEC_CC_RP, TYPEC_CC_RP);
+	zassert_equal(EC_SUCCESS, drv->drp_toggle(port));
+	check_tcpci_reg(emul, TCPC_REG_TCPC_CTRL, exp_tcpc_ctrl);
+	check_tcpci_reg(emul, TCPC_REG_ROLE_CTRL, exp_role_ctrl);
+	check_tcpci_reg(emul, TCPC_REG_COMMAND,
+			TCPC_REG_COMMAND_LOOK4CONNECTION);
+
+	/* Set TCPCI to revision 1 */
+	tcpc_config[port].flags = 0;
+	tcpci_emul_set_rev(emul, TCPCI_EMUL_REV1_0_VER1_0);
+
+	/* Set initial value for TCPC ctrl register. Chosen arbitrary. */
+	initial_tcpc_ctrl = TCPC_REG_TCPC_CTRL_DEBUG_ACC_CONTROL |
+			    TCPC_REG_TCPC_CTRL_BIST_TEST_MODE;
+	tcpci_emul_set_reg(emul, TCPC_REG_TCPC_CTRL, initial_tcpc_ctrl);
+
+	/*
+	 * Test correct registers values for rev 1.0. Role control CC lines
+	 * have to be set to RD with DRP enabled and smallest RP value.
+	 * Only CC lines setting is different from rev 2.0
+	 */
+	exp_tcpc_ctrl = initial_tcpc_ctrl |
+			TCPC_REG_TCPC_CTRL_EN_LOOK4CONNECTION_ALERT;
+	exp_role_ctrl = TCPC_REG_ROLE_CTRL_SET(TYPEC_DRP, TYPEC_RP_USB,
+					       TYPEC_CC_RD, TYPEC_CC_RD);
+	zassert_equal(EC_SUCCESS, drv->drp_toggle(port));
+	check_tcpci_reg(emul, TCPC_REG_TCPC_CTRL, exp_tcpc_ctrl);
+	check_tcpci_reg(emul, TCPC_REG_ROLE_CTRL, exp_role_ctrl);
+	check_tcpci_reg(emul, TCPC_REG_COMMAND,
+			TCPC_REG_COMMAND_LOOK4CONNECTION);
+}
+
+static int test_tcpci_get_chip_info_mutator_device_id(
+	int port, bool live, struct ec_response_pd_chip_info_v1 *cached)
+{
+	cached->device_id = 0xbeef;
+	return EC_SUCCESS;
+}
+
+static int test_tcpci_get_chip_info_mutator_fail(
+	int port, bool live, struct ec_response_pd_chip_info_v1 *cached)
+{
+	return EC_ERROR_UNCHANGED;
+}
+
+/** Test TCPCI get chip info */
+void test_tcpci_get_chip_info(const struct emul *emul,
+			      struct i2c_common_emul_data *common_data,
+			      enum usbc_port port)
+{
+	const struct tcpm_drv *drv = tcpc_config[port].drv;
+	struct ec_response_pd_chip_info_v1 info;
+	uint16_t vendor, product, bcd;
+
+	/* Test error on failed vendor id get */
+	i2c_common_emul_set_read_fail_reg(common_data, TCPC_REG_VENDOR_ID);
+	zassert_equal(EC_ERROR_INVAL, drv->get_chip_info(port, 1, &info));
+
+	/*
+	 * Test error on failed product id get. Cache should not be valid
+	 * because the previous call to get_chip_info failed.
+	 */
+	i2c_common_emul_set_read_fail_reg(common_data, TCPC_REG_PRODUCT_ID);
+	zassert_equal(EC_ERROR_INVAL, drv->get_chip_info(port, 0, &info));
+
+	/* Test error on failed BCD get */
+	i2c_common_emul_set_read_fail_reg(common_data, TCPC_REG_BCD_DEV);
+	zassert_equal(EC_ERROR_INVAL, drv->get_chip_info(port, 0, &info));
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test reading chip info. Values chosen arbitrary. */
+	vendor = 0x1234;
+	product = 0x5678;
+	bcd = 0x9876;
+	tcpci_emul_set_reg(emul, TCPC_REG_VENDOR_ID, vendor);
+	tcpci_emul_set_reg(emul, TCPC_REG_PRODUCT_ID, product);
+	tcpci_emul_set_reg(emul, TCPC_REG_BCD_DEV, bcd);
+	zassert_equal(EC_SUCCESS, drv->get_chip_info(port, 1, &info));
+	zassert_equal(vendor, info.vendor_id);
+	zassert_equal(product, info.product_id);
+	zassert_equal(bcd, info.device_id);
+
+	/* Test reading cached chip info */
+	info.vendor_id = 0;
+	info.product_id = 0;
+	info.device_id = 0;
+	/* Make sure, that TCPC is not accessed */
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_FAIL_ALL_REG);
+	zassert_equal(EC_SUCCESS, drv->get_chip_info(port, 0, &info));
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	zassert_equal(vendor, info.vendor_id);
+	zassert_equal(product, info.product_id);
+	zassert_equal(bcd, info.device_id);
+
+	/* Test providing a callback to modify cached data. */
+	zassert_equal(EC_SUCCESS,
+		      tcpci_get_chip_info_mutable(
+			      port, 1, &info,
+			      test_tcpci_get_chip_info_mutator_device_id));
+	zassert_equal(0xbeef, info.device_id);
+
+	/* Errors from the mutator get bubbled up. */
+	zassert_equal(EC_ERROR_UNCHANGED,
+		      tcpci_get_chip_info_mutable(
+			      port, 1, &info,
+			      test_tcpci_get_chip_info_mutator_fail));
+}
+
+void test_tcpci_get_vbus_voltage(const struct emul *emul,
+				 struct i2c_common_emul_data *common_data,
+				 enum usbc_port port)
+{
+	const struct tcpm_drv *drv = tcpc_config[port].drv;
+	const int fake_vbus[] = { 0,	 25,	1500,  5000,  12000, 16000,
+				  20000, 25575, 25600, 51150, 51200, 102300 };
+	const int fake_meas[] = { 0, 1, 2, 3, 4, 5, 128, 256, 512, 1023 };
+	const int fake_scl[] = { 0, 1 << 10, 2 << 10 };
+	int vbus = 0;
+
+	/* Test dev_cap_1 unsupported */
+	tcpci_emul_set_reg(emul, TCPC_REG_DEV_CAP_1, 0);
+	zassert_equal(EC_ERROR_UNIMPLEMENTED,
+		      drv->get_vbus_voltage(port, &vbus));
+
+	tcpci_emul_set_reg(emul, TCPC_REG_DEV_CAP_1,
+			   TCPC_REG_DEV_CAP_1_VBUS_MEASURE_ALARM_CAPABLE);
+
+	/* Refresh cached dev_cap_1 */
+	zassert_equal(EC_SUCCESS, drv->init(port), NULL);
+
+	/* Test error on failed command get */
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_FAIL_ALL_REG);
+	zassert_equal(EC_ERROR_INVAL, drv->get_vbus_voltage(port, &vbus));
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test by setting vbus */
+	for (int i = 0; i < ARRAY_SIZE(fake_vbus); i++) {
+		tcpci_emul_set_vbus_voltage(emul, fake_vbus[i]);
+		zassert_equal(EC_SUCCESS, drv->get_vbus_voltage(port, &vbus));
+		zassert_equal(vbus, fake_vbus[i]);
+	}
+
+	/* Test by setting the register */
+	for (int i = 0; i < ARRAY_SIZE(fake_meas); i++) {
+		for (int j = 0; j < ARRAY_SIZE(fake_scl); j++) {
+			tcpci_emul_set_reg(emul, TCPC_REG_VBUS_VOLTAGE,
+					   (fake_meas[i] | fake_scl[j]));
+			zassert_equal(EC_SUCCESS,
+				      drv->get_vbus_voltage(port, &vbus));
+			zassert_equal(vbus, BIT(j) * fake_meas[i] *
+						    TCPC_REG_VBUS_VOLTAGE_LSB);
+		}
+	}
+}
+
+/** Test TCPCI enter low power mode */
+void test_tcpci_low_power_mode(const struct emul *emul,
+			       struct i2c_common_emul_data *common_data,
+			       enum usbc_port port)
+{
+	const struct tcpm_drv *drv = tcpc_config[port].drv;
+
+	/* Test error on failed command set */
+	i2c_common_emul_set_write_fail_reg(common_data, TCPC_REG_COMMAND);
+	zassert_equal(EC_ERROR_INVAL, drv->enter_low_power_mode(port));
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test correct command is issued */
+	zassert_equal(EC_SUCCESS, drv->enter_low_power_mode(port));
+	check_tcpci_reg(emul, TCPC_REG_COMMAND, TCPC_REG_COMMAND_I2CIDLE);
+}
+
+/** Test TCPCI set bist test mode */
+void test_tcpci_set_bist_mode(const struct emul *emul,
+			      struct i2c_common_emul_data *common_data,
+			      enum usbc_port port)
+{
+	const struct tcpm_drv *drv = tcpc_config[port].drv;
+	uint16_t exp_mask, initial_mask;
+	uint8_t exp_ctrl, initial_ctrl;
+
+	/* Test error on TCPC CTRL set */
+	i2c_common_emul_set_write_fail_reg(common_data, TCPC_REG_TCPC_CTRL);
+	zassert_equal(EC_ERROR_INVAL, drv->set_bist_test_mode(port, 1));
+
+	/* Test error on alert mask set */
+	i2c_common_emul_set_write_fail_reg(common_data, TCPC_REG_ALERT_MASK);
+	zassert_equal(EC_ERROR_INVAL, drv->set_bist_test_mode(port, 1));
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Set initial value for alert mask register. Chosen arbitrary. */
+	initial_mask = TCPC_REG_ALERT_MASK_ALL;
+	tcpci_emul_set_reg(emul, TCPC_REG_ALERT_MASK, initial_mask);
+
+	/* Set initial value for TCPC ctrl register. Chosen arbitrary. */
+	initial_ctrl = TCPC_REG_TCPC_CTRL_DEBUG_ACC_CONTROL |
+		       TCPC_REG_TCPC_CTRL_EN_LOOK4CONNECTION_ALERT;
+	tcpci_emul_set_reg(emul, TCPC_REG_TCPC_CTRL, initial_ctrl);
+
+	/* Test enabling bist test mode */
+	exp_mask = initial_mask & ~TCPC_REG_ALERT_RX_STATUS;
+	exp_ctrl = initial_ctrl | TCPC_REG_TCPC_CTRL_BIST_TEST_MODE;
+	zassert_equal(EC_SUCCESS, drv->set_bist_test_mode(port, 1));
+	check_tcpci_reg(emul, TCPC_REG_TCPC_CTRL, exp_ctrl);
+	check_tcpci_reg(emul, TCPC_REG_ALERT_MASK, exp_mask);
+
+	/* Test disabling bist test mode */
+	exp_mask = initial_mask | TCPC_REG_ALERT_RX_STATUS;
+	exp_ctrl = initial_ctrl & ~TCPC_REG_TCPC_CTRL_BIST_TEST_MODE;
+	zassert_equal(EC_SUCCESS, drv->set_bist_test_mode(port, 0));
+	check_tcpci_reg(emul, TCPC_REG_TCPC_CTRL, exp_ctrl);
+	check_tcpci_reg(emul, TCPC_REG_ALERT_MASK, exp_mask);
+}
+
+void test_tcpci_hard_reset_reinit(const struct emul *emul,
+				  struct i2c_common_emul_data *common_data,
+				  enum usbc_port port)
+{
+	const struct tcpm_drv *drv = tcpc_config[port].drv;
+	uint16_t power_status_mask;
+	uint16_t alert_mask;
+
+	zassert_equal(EC_SUCCESS, drv->init(port), NULL);
+	tcpci_emul_get_reg(emul, TCPC_REG_POWER_STATUS_MASK,
+			   &power_status_mask);
+	tcpci_emul_get_reg(emul, TCPC_REG_ALERT_MASK, &alert_mask);
+	zassert_ok(tcpci_hard_reset_reinit(USBC_PORT_C0), NULL);
+	check_tcpci_reg(emul, TCPC_REG_POWER_STATUS_MASK, power_status_mask);
+	check_tcpci_reg(emul, TCPC_REG_ALERT_MASK, alert_mask);
+}
diff --git a/zephyr/test/drivers/default/src/tcpm_header.c b/zephyr/test/drivers/default/src/tcpm_header.c
new file mode 100644
index 0000000000..e03e09aaa5
--- /dev/null
+++ b/zephyr/test/drivers/default/src/tcpm_header.c
@@ -0,0 +1,235 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "tcpm/tcpm.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+#define TCPM_TEST_PORT USBC_PORT_C0
+
+FAKE_VALUE_FUNC(int, set_vconn, int, int);
+FAKE_VALUE_FUNC(int, reset_bist_type_2, int);
+FAKE_VALUE_FUNC(int, debug_accessory, int, bool);
+FAKE_VALUE_FUNC(int, debug_detach, int);
+FAKE_VALUE_FUNC(int, hard_reset_reinit, int);
+FAKE_VALUE_FUNC(int, set_frs_enable, int, int);
+FAKE_VOID_FUNC(tcpc_dump_std_registers, int);
+
+struct tcpm_header_fixture {
+	/* The original driver pointer that gets restored after the tests */
+	const struct tcpm_drv *saved_driver_ptr;
+	/* Mock driver that gets substituted */
+	struct tcpm_drv mock_driver;
+	/* Saved tcpc config flags that get restored after the tests */
+	uint32_t saved_tcpc_flags;
+};
+
+ZTEST_F(tcpm_header, test_tcpm_header_drv_set_vconn_failure)
+{
+	int res;
+
+	tcpc_config[TCPM_TEST_PORT].flags = TCPC_FLAGS_CONTROL_VCONN;
+
+	fixture->mock_driver.set_vconn = set_vconn;
+	set_vconn_fake.return_val = -1;
+
+	res = tcpm_set_vconn(TCPM_TEST_PORT, true);
+
+	zassert_true(set_vconn_fake.call_count > 0);
+	zassert_equal(-1, res);
+}
+
+ZTEST_F(tcpm_header, test_tcpm_header_reset_bist_type_2__unimplemented)
+{
+	zassert_ok(tcpm_reset_bist_type_2(TCPM_TEST_PORT));
+}
+
+ZTEST_F(tcpm_header, test_tcpm_header_reset_bist_type_2__implemented)
+{
+	int res;
+	const int driver_return_code = 7458; /* arbitrary */
+
+	fixture->mock_driver.reset_bist_type_2 = reset_bist_type_2;
+	reset_bist_type_2_fake.return_val = driver_return_code;
+	res = tcpm_reset_bist_type_2(TCPM_TEST_PORT);
+
+	zassert_equal(1, reset_bist_type_2_fake.call_count);
+	zassert_equal(TCPM_TEST_PORT, reset_bist_type_2_fake.arg0_history[0]);
+	zassert_equal(driver_return_code, res);
+}
+
+ZTEST_F(tcpm_header, test_tcpm_header_debug_accessory__unimplemented)
+{
+	zassert_ok(tcpm_debug_accessory(TCPM_TEST_PORT, true));
+	zassert_ok(tcpm_debug_accessory(TCPM_TEST_PORT, false));
+}
+
+ZTEST_F(tcpm_header, test_tcpm_header_debug_accessory__implemented)
+{
+	int res;
+	const int driver_return_code = 7458; /* arbitrary */
+
+	fixture->mock_driver.debug_accessory = debug_accessory;
+	debug_accessory_fake.return_val = driver_return_code;
+	res = tcpm_debug_accessory(TCPM_TEST_PORT, true);
+
+	zassert_equal(1, debug_accessory_fake.call_count);
+	zassert_equal(TCPM_TEST_PORT, debug_accessory_fake.arg0_history[0]);
+	zassert_true(debug_accessory_fake.arg1_history[0]);
+	zassert_equal(driver_return_code, res);
+}
+
+ZTEST_F(tcpm_header, test_tcpm_header_debug_detach__unimplemented)
+{
+	zassert_ok(tcpm_debug_detach(TCPM_TEST_PORT));
+}
+
+ZTEST_F(tcpm_header, test_tcpm_header_debug_detach__implemented)
+{
+	int res;
+	const int driver_return_code = 7458; /* arbitrary */
+
+	fixture->mock_driver.debug_detach = debug_detach;
+	debug_detach_fake.return_val = driver_return_code;
+	res = tcpm_debug_detach(TCPM_TEST_PORT);
+
+	zassert_equal(1, debug_detach_fake.call_count);
+	zassert_equal(TCPM_TEST_PORT, debug_detach_fake.arg0_history[0]);
+	zassert_equal(driver_return_code, res);
+}
+
+ZTEST_F(tcpm_header, test_tcpm_header_hard_reset_reinit__unimplemented)
+{
+	int res;
+
+	res = tcpm_hard_reset_reinit(TCPM_TEST_PORT);
+
+	zassert_equal(EC_ERROR_UNIMPLEMENTED, res);
+}
+
+ZTEST_F(tcpm_header, test_tcpm_header_hard_reset_reinit__implemented)
+{
+	int res;
+	const int driver_return_code = 7458; /* arbitrary */
+
+	fixture->mock_driver.hard_reset_reinit = hard_reset_reinit;
+	hard_reset_reinit_fake.return_val = driver_return_code;
+	res = tcpm_hard_reset_reinit(TCPM_TEST_PORT);
+
+	zassert_equal(1, hard_reset_reinit_fake.call_count);
+	zassert_equal(TCPM_TEST_PORT, hard_reset_reinit_fake.arg0_history[0]);
+	zassert_equal(driver_return_code, res);
+}
+
+ZTEST_F(tcpm_header, test_tcpm_header_tcpc_has_frs_control__flag)
+{
+	Z_TEST_SKIP_IFNDEF(CONFIG_PLATFORM_EC_USB_PD_FRS);
+	Z_TEST_SKIP_IFDEF(CONFIG_PLATFORM_EC_USB_PD_FRS_TCPC);
+
+	/* Determined by tcpc flag when USB_PD_FRS_TCPC is not set. */
+
+	tcpc_config[TCPM_TEST_PORT].flags = 0;
+	zassert_equal(0, tcpm_tcpc_has_frs_control(TCPM_TEST_PORT));
+
+	tcpc_config[TCPM_TEST_PORT].flags = TCPC_FLAGS_CONTROL_FRS;
+	zassert_equal(1, tcpm_tcpc_has_frs_control(TCPM_TEST_PORT));
+}
+
+ZTEST_F(tcpm_header, test_tcpm_header_set_frs_enable__unimplemented)
+{
+	Z_TEST_SKIP_IFNDEF(CONFIG_PLATFORM_EC_USB_PD_FRS);
+
+	zassert_ok(tcpm_set_frs_enable(TCPM_TEST_PORT, 1));
+	zassert_ok(tcpm_set_frs_enable(TCPM_TEST_PORT, 0));
+}
+
+ZTEST_F(tcpm_header, test_tcpm_header_set_frs_enable__implemented)
+{
+	int res;
+	const int driver_return_code = 7458; /* arbitrary */
+
+	Z_TEST_SKIP_IFNDEF(CONFIG_PLATFORM_EC_USB_PD_FRS);
+
+	fixture->mock_driver.set_frs_enable = set_frs_enable;
+	set_frs_enable_fake.return_val = driver_return_code;
+	res = tcpm_set_frs_enable(TCPM_TEST_PORT, 1);
+
+	zassert_equal(1, set_frs_enable_fake.call_count);
+	zassert_equal(TCPM_TEST_PORT, set_frs_enable_fake.arg0_history[0]);
+	zassert_equal(1, set_frs_enable_fake.arg1_history[0]);
+	zassert_equal(driver_return_code, res);
+}
+
+ZTEST_F(tcpm_header, test_tcpm_header_tcpc_get_bist_test_mode__unimplemented)
+{
+	int res;
+	bool enabled = true; /* Should be overwritten to false */
+
+	res = tcpc_get_bist_test_mode(TCPM_TEST_PORT, &enabled);
+
+	zassert_equal(EC_ERROR_UNIMPLEMENTED, res);
+	zassert_false(enabled);
+}
+
+ZTEST_F(tcpm_header, test_tcpm_header_get_chip_info__unimplemented)
+{
+	zassert_equal(EC_ERROR_UNIMPLEMENTED,
+		      tcpm_get_chip_info(TCPM_TEST_PORT, 0, NULL));
+}
+
+ZTEST_F(tcpm_header, test_tcpm_header_dump_registers__std)
+{
+	Z_TEST_SKIP_IFNDEF(CONFIG_PLATFORM_EC_CONSOLE_CMD_TCPC_DUMP);
+
+	/*
+	 * The driver does not implement dump_registers, so the
+	 * standard ones should be dumped instead.
+	 */
+	tcpm_dump_registers(TCPM_TEST_PORT);
+
+	zassert_equal(1, tcpc_dump_std_registers_fake.call_count);
+	zassert_equal(TCPM_TEST_PORT,
+		      tcpc_dump_std_registers_fake.arg0_history[0]);
+}
+
+static void *tcpm_header_setup(void)
+{
+	static struct tcpm_header_fixture fixture;
+
+	return &fixture;
+}
+
+static void tcpm_header_before(void *state)
+{
+	struct tcpm_header_fixture *fixture = state;
+
+	RESET_FAKE(set_vconn);
+	RESET_FAKE(reset_bist_type_2);
+	RESET_FAKE(debug_accessory);
+	RESET_FAKE(debug_detach);
+	RESET_FAKE(hard_reset_reinit);
+	RESET_FAKE(set_frs_enable);
+	RESET_FAKE(tcpc_dump_std_registers);
+
+	fixture->mock_driver = (struct tcpm_drv){ 0 };
+	fixture->saved_driver_ptr = tcpc_config[TCPM_TEST_PORT].drv;
+	tcpc_config[TCPM_TEST_PORT].drv = &fixture->mock_driver;
+
+	fixture->saved_tcpc_flags = tcpc_config[TCPM_TEST_PORT].flags;
+}
+
+static void tcpm_header_after(void *state)
+{
+	struct tcpm_header_fixture *fixture = state;
+
+	tcpc_config[TCPM_TEST_PORT].drv = fixture->saved_driver_ptr;
+	tcpc_config[TCPM_TEST_PORT].flags = fixture->saved_tcpc_flags;
+}
+
+ZTEST_SUITE(tcpm_header, drivers_predicate_pre_main, tcpm_header_setup,
+	    tcpm_header_before, tcpm_header_after, NULL);
diff --git a/zephyr/test/drivers/default/src/tcs3400.c b/zephyr/test/drivers/default/src/tcs3400.c
new file mode 100644
index 0000000000..dba8dc5c56
--- /dev/null
+++ b/zephyr/test/drivers/default/src/tcs3400.c
@@ -0,0 +1,686 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "driver/als_tcs3400.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_tcs3400.h"
+#include "i2c.h"
+#include "motion_sense.h"
+#include "motion_sense_fifo.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+#define TCS_NODE DT_NODELABEL(tcs_emul)
+#define TCS_CLR_SENSOR_ID SENSOR_ID(DT_NODELABEL(tcs3400_clear))
+#define TCS_RGB_SENSOR_ID SENSOR_ID(DT_NODELABEL(tcs3400_rgb))
+#define TCS_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(SENSOR_ID(DT_ALIAS(tcs3400_int)))
+
+/** How accurate comparision of rgb sensors should be */
+#define V_EPS 8
+
+/** Test initialization of light sensor driver and device */
+ZTEST_USER(tcs3400, test_tcs_init)
+{
+	struct motion_sensor_t *ms, *ms_rgb;
+	const struct emul *emul = EMUL_DT_GET(TCS_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcs3400_get_i2c_common_data(emul);
+
+	ms = &motion_sensors[TCS_CLR_SENSOR_ID];
+	ms_rgb = &motion_sensors[TCS_RGB_SENSOR_ID];
+
+	/* RGB sensor initialization is always successful */
+	zassert_equal(EC_SUCCESS, ms_rgb->drv->init(ms_rgb));
+
+	/* Fail init on communication errors */
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_FAIL_ALL_REG);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->init(ms));
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Fail on bad ID */
+	tcs_emul_set_reg(emul, TCS_I2C_ID, 0);
+	zassert_equal(EC_ERROR_ACCESS_DENIED, ms->drv->init(ms));
+	/* Restore ID */
+	tcs_emul_set_reg(emul, TCS_I2C_ID,
+			 DT_STRING_TOKEN(DT_NODELABEL(tcs_emul), device_id));
+
+	/* Test successful init. ATIME and AGAIN should be changed on init */
+	zassert_equal(EC_SUCCESS, ms->drv->init(ms));
+	zassert_equal(TCS_DEFAULT_ATIME, tcs_emul_get_reg(emul, TCS_I2C_ATIME),
+		      NULL);
+	zassert_equal(TCS_DEFAULT_AGAIN,
+		      tcs_emul_get_reg(emul, TCS_I2C_CONTROL), NULL);
+}
+
+/** Test if read function leaves device in correct mode to accuire data */
+ZTEST_USER(tcs3400, test_tcs_read)
+{
+	struct motion_sensor_t *ms;
+	const struct emul *emul = EMUL_DT_GET(TCS_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcs3400_get_i2c_common_data(emul);
+	uint8_t enable;
+	intv3_t v;
+
+	ms = &motion_sensors[TCS_CLR_SENSOR_ID];
+
+	/* Test error on writing registers */
+	i2c_common_emul_set_write_fail_reg(common_data, TCS_I2C_ATIME);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, v));
+	i2c_common_emul_set_write_fail_reg(common_data, TCS_I2C_CONTROL);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, v));
+	i2c_common_emul_set_write_fail_reg(common_data, TCS_I2C_ENABLE);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, v));
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test starting read with calibration */
+	tcs_emul_set_reg(emul, TCS_I2C_ATIME, 0);
+	tcs_emul_set_reg(emul, TCS_I2C_CONTROL, 0);
+	tcs_emul_set_reg(emul, TCS_I2C_ENABLE, 0);
+	zassert_equal(EC_SUCCESS, ms->drv->perform_calib(ms, 1));
+	zassert_equal(EC_RES_IN_PROGRESS, ms->drv->read(ms, v));
+	zassert_equal(TCS_CALIBRATION_ATIME,
+		      tcs_emul_get_reg(emul, TCS_I2C_ATIME), NULL);
+	zassert_equal(TCS_CALIBRATION_AGAIN,
+		      tcs_emul_get_reg(emul, TCS_I2C_CONTROL), NULL);
+	enable = tcs_emul_get_reg(emul, TCS_I2C_ENABLE);
+	zassert_true(enable & TCS_I2C_ENABLE_POWER_ON);
+	zassert_true(enable & TCS_I2C_ENABLE_ADC_ENABLE);
+	zassert_true(enable & TCS_I2C_ENABLE_INT_ENABLE);
+
+	/* Test starting read without calibration */
+	tcs_emul_set_reg(emul, TCS_I2C_ATIME, 0);
+	tcs_emul_set_reg(emul, TCS_I2C_CONTROL, 0);
+	tcs_emul_set_reg(emul, TCS_I2C_ENABLE, 0);
+	zassert_equal(EC_SUCCESS, ms->drv->perform_calib(ms, 0));
+	zassert_equal(EC_RES_IN_PROGRESS, ms->drv->read(ms, v));
+	enable = tcs_emul_get_reg(emul, TCS_I2C_ENABLE);
+	zassert_true(enable & TCS_I2C_ENABLE_POWER_ON);
+	zassert_true(enable & TCS_I2C_ENABLE_ADC_ENABLE);
+	zassert_true(enable & TCS_I2C_ENABLE_INT_ENABLE);
+
+	ms = &motion_sensors[TCS_RGB_SENSOR_ID];
+
+	zassert_ok(ms->drv->read(ms, NULL));
+}
+
+ZTEST_USER(tcs3400, test_tcs_get_set_offset)
+{
+	struct motion_sensor_t *ms;
+	int16_t offset[3] = { 0, 5, 10 };
+	int16_t new_offset[3] = { 5, -1, 17 };
+	int16_t temperature = 0;
+
+	ms = &motion_sensors[TCS_CLR_SENSOR_ID];
+	zassert_ok(ms->drv->get_offset(ms, offset, &temperature));
+	zassert_equal(TCS3400_DRV_DATA(ms)->als_cal.offset, offset[0]);
+	zassert_equal(0, offset[1]);
+	zassert_equal(0, offset[2]);
+	zassert_equal(EC_MOTION_SENSE_INVALID_CALIB_TEMP, temperature);
+
+	/* Try to change the offset and make sure it doesn't change
+	 * (tcs3400's offset cannot be configured at runtime)
+	 */
+	zassert_ok(ms->drv->set_offset(ms, new_offset, 20));
+	zassert_ok(ms->drv->get_offset(ms, new_offset, &temperature));
+	zassert_mem_equal(offset, new_offset, sizeof(offset));
+	zassert_equal(EC_MOTION_SENSE_INVALID_CALIB_TEMP, temperature);
+
+	ms = &motion_sensors[TCS_RGB_SENSOR_ID];
+	zassert_ok(ms->drv->get_offset(ms, offset, &temperature));
+	zassert_equal(TCS3400_RGB_DRV_DATA(ms)->calibration.rgb_cal[0].offset,
+		      offset[0]);
+	zassert_equal(TCS3400_RGB_DRV_DATA(ms)->calibration.rgb_cal[1].offset,
+		      offset[1]);
+	zassert_equal(TCS3400_RGB_DRV_DATA(ms)->calibration.rgb_cal[2].offset,
+		      offset[2]);
+	zassert_equal(EC_MOTION_SENSE_INVALID_CALIB_TEMP, temperature);
+
+	/* Try to change the offset and make sure it didn't change */
+	new_offset[0] = 5;
+	new_offset[1] = -1;
+	new_offset[2] = 17;
+	zassert_ok(ms->drv->set_offset(ms, new_offset, 20));
+	zassert_ok(ms->drv->get_offset(ms, new_offset, &temperature));
+	zassert_mem_equal(offset, new_offset, sizeof(offset));
+	zassert_equal(EC_MOTION_SENSE_INVALID_CALIB_TEMP, temperature);
+}
+
+/** Check if FIFO for RGB and clear sensor is empty */
+static void check_fifo_empty_f(struct motion_sensor_t *ms,
+			       struct motion_sensor_t *ms_rgb, int line)
+{
+	struct ec_response_motion_sensor_data vector;
+	uint16_t size;
+
+	/* Read all data committed to FIFO */
+	while (motion_sense_fifo_read(sizeof(vector), 1, &vector, &size)) {
+		/* Ignore timestamp frames */
+		if (vector.flags == MOTIONSENSE_SENSOR_FLAG_TIMESTAMP) {
+			continue;
+		}
+
+		if (ms - motion_sensors == vector.sensor_num) {
+			zassert_unreachable(
+				"Unexpected frame for clear sensor @line: %d",
+				line);
+		}
+
+		if (ms_rgb - motion_sensors == vector.sensor_num) {
+			zassert_unreachable(
+				"Unexpected frame for rgb sensor @line: %d",
+				line);
+		}
+	}
+}
+#define check_fifo_empty(ms, ms_rgb) check_fifo_empty_f(ms, ms_rgb, __LINE__)
+
+/**
+ * Test different conditions where irq handler fail or commit no data
+ * to fifo
+ */
+ZTEST_USER(tcs3400, test_tcs_irq_handler_fail)
+{
+	struct motion_sensor_t *ms, *ms_rgb;
+	const struct emul *emul = EMUL_DT_GET(TCS_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcs3400_get_i2c_common_data(emul);
+	uint32_t event;
+
+	ms = &motion_sensors[TCS_CLR_SENSOR_ID];
+	ms_rgb = &motion_sensors[TCS_RGB_SENSOR_ID];
+
+	/* Fail on wrong event */
+	event = 0x1234 & ~TCS_INT_EVENT;
+	zassert_equal(EC_ERROR_NOT_HANDLED, ms->drv->irq_handler(ms, &event),
+		      NULL);
+	check_fifo_empty(ms, ms_rgb);
+
+	event = TCS_INT_EVENT;
+	/* Test error on reading status */
+	i2c_common_emul_set_read_fail_reg(common_data, TCS_I2C_STATUS);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->irq_handler(ms, &event));
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	check_fifo_empty(ms, ms_rgb);
+
+	/* Test fail on changing device power state */
+	i2c_common_emul_set_write_fail_reg(common_data, TCS_I2C_ENABLE);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->irq_handler(ms, &event));
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+	check_fifo_empty(ms, ms_rgb);
+
+	/* Test that no data is committed when status is 0 */
+	tcs_emul_set_reg(emul, TCS_I2C_STATUS, 0);
+	zassert_equal(EC_SUCCESS, ms->drv->irq_handler(ms, &event));
+	check_fifo_empty(ms, ms_rgb);
+}
+
+/**
+ * Check if last data committed to FIFO for RGB and clear sensor equals to
+ * expected value.
+ */
+static void check_fifo_f(struct motion_sensor_t *ms,
+			 struct motion_sensor_t *ms_rgb, int *exp_v, int eps,
+			 int line)
+{
+	struct ec_response_motion_sensor_data vector;
+	uint16_t size;
+	int ret_v[4] = { -1, -1, -1, -1 };
+	int i;
+
+	/* Read all data committed to FIFO */
+	while (motion_sense_fifo_read(sizeof(vector), 1, &vector, &size)) {
+		/* Ignore timestamp frames */
+		if (vector.flags == MOTIONSENSE_SENSOR_FLAG_TIMESTAMP) {
+			continue;
+		}
+
+		/* Get clear frame */
+		if (ms - motion_sensors == vector.sensor_num) {
+			ret_v[0] = vector.udata[0];
+		}
+
+		/* Get rgb frame */
+		if (ms_rgb - motion_sensors == vector.sensor_num) {
+			ret_v[1] = vector.udata[0];
+			ret_v[2] = vector.udata[1];
+			ret_v[3] = vector.udata[2];
+		}
+	}
+
+	if (ret_v[0] == -1) {
+		zassert_unreachable("No frame for clear sensor, line %d", line);
+	}
+
+	if (ret_v[1] == -1) {
+		zassert_unreachable("No frame for rgb sensor, line %d", line);
+	}
+
+	/* Compare with last committed data */
+	for (i = 0; i < 4; i++) {
+		zassert_within(
+			exp_v[i], ret_v[i], eps,
+			"Expected [%d; %d; %d; %d], got [%d; %d; %d; %d]; line: %d",
+			exp_v[0], exp_v[1], exp_v[2], exp_v[3], ret_v[0],
+			ret_v[1], ret_v[2], ret_v[3], line);
+	}
+}
+#define check_fifo(ms, ms_rgb, exp_v, eps) \
+	check_fifo_f(ms, ms_rgb, exp_v, eps, __LINE__)
+
+/** Test calibration mode reading of light sensor values */
+ZTEST_USER(tcs3400, test_tcs_read_calibration)
+{
+	struct motion_sensor_t *ms, *ms_rgb;
+	const struct emul *emul = EMUL_DT_GET(TCS_NODE);
+	uint32_t event = TCS_INT_EVENT;
+	int emul_v[4];
+	int exp_v[4];
+	intv3_t v;
+
+	ms = &motion_sensors[TCS_CLR_SENSOR_ID];
+	ms_rgb = &motion_sensors[TCS_RGB_SENSOR_ID];
+
+	/* Need to be set to collect all data in FIFO */
+	ms->oversampling_ratio = 1;
+	ms_rgb->oversampling_ratio = 1;
+	/* Enable calibration mode */
+	zassert_equal(EC_SUCCESS, ms->drv->perform_calib(ms, 1));
+	/* Setup AGAIN and ATIME for calibration */
+	zassert_equal(EC_RES_IN_PROGRESS, ms->drv->read(ms, v));
+
+	/* Test data that are in calibration range */
+	exp_v[0] = 12;
+	exp_v[1] = 123;
+	exp_v[2] = 1234;
+	exp_v[3] = 12345;
+	/*
+	 * Emulator value is with gain 64, while expected value is
+	 * with gain 16
+	 */
+	emul_v[0] = exp_v[0] * 64 / 16;
+	emul_v[1] = exp_v[1] * 64 / 16;
+	emul_v[2] = exp_v[2] * 64 / 16;
+	emul_v[3] = exp_v[3] * 64 / 16;
+	tcs_emul_set_val(emul, TCS_EMUL_C, emul_v[0]);
+	tcs_emul_set_val(emul, TCS_EMUL_R, emul_v[1]);
+	tcs_emul_set_val(emul, TCS_EMUL_G, emul_v[2]);
+	tcs_emul_set_val(emul, TCS_EMUL_B, emul_v[3]);
+	/* Set status to show valid data */
+	tcs_emul_set_reg(emul, TCS_I2C_STATUS, TCS_I2C_STATUS_RGBC_VALID);
+
+	zassert_equal(EC_SUCCESS, ms->drv->irq_handler(ms, &event));
+	/* In calibration mode check for exact match */
+	check_fifo(ms, ms_rgb, exp_v, 1);
+
+	/* Test data that are outside of calibration range */
+	exp_v[0] = 0;
+	exp_v[1] = UINT16_MAX;
+	exp_v[2] = UINT16_MAX;
+	exp_v[3] = 213;
+	/*
+	 * Emulator value is with gain 64, while expected value is
+	 * with gain 16
+	 */
+	emul_v[0] = 0;
+	emul_v[1] = exp_v[1] * 64 / 16;
+	emul_v[2] = (UINT16_MAX + 23) * 64 / 16;
+	emul_v[3] = exp_v[3] * 64 / 16;
+	tcs_emul_set_val(emul, TCS_EMUL_C, emul_v[0]);
+	tcs_emul_set_val(emul, TCS_EMUL_R, emul_v[1]);
+	tcs_emul_set_val(emul, TCS_EMUL_G, emul_v[2]);
+	tcs_emul_set_val(emul, TCS_EMUL_B, emul_v[3]);
+	/* Set status to show valid data */
+	tcs_emul_set_reg(emul, TCS_I2C_STATUS, TCS_I2C_STATUS_RGBC_VALID);
+
+	zassert_equal(EC_SUCCESS, ms->drv->irq_handler(ms, &event));
+	/* In calibration mode check for exact match */
+	check_fifo(ms, ms_rgb, exp_v, 1);
+}
+
+/**
+ * Set emulator internal value using expected output value returned by
+ * the driver. First element of expected vector is IR value used in
+ * calculations. Based on that clear light value is calculated.
+ * First element of expected vector is updated by this function.
+ */
+static void set_emul_val_from_exp(int *exp_v, uint16_t *scale,
+				  const struct emul *emul)
+{
+	int emul_v[4];
+	int ir;
+
+	/* We use exp_v[0] as IR value */
+	ir = exp_v[0];
+	/* Driver will return lux value as calculated blue light value */
+	exp_v[0] = exp_v[2];
+
+	/*
+	 * Driver takes care of different ATIME and AGAIN value, so expected
+	 * value is always normalized to ATIME 256 and AGAIN 16. Convert it
+	 * to internal emulator value (ATIME 256, AGAIN 64) and add expected IR
+	 * value. Clear light is the sum of rgb light and IR component.
+	 */
+	emul_v[1] = (exp_v[1] + ir) * 64 / 16;
+	emul_v[2] = (exp_v[2] + ir) * 64 / 16;
+	emul_v[3] = (exp_v[3] + ir) * 64 / 16;
+	emul_v[0] = (exp_v[1] + exp_v[2] + exp_v[3] + ir) * 64 / 16;
+
+	/* Apply scale, driver should divide by this value */
+	emul_v[0] = SENSOR_APPLY_SCALE(emul_v[0], scale[0]);
+	emul_v[1] = SENSOR_APPLY_SCALE(emul_v[1], scale[1]);
+	emul_v[2] = SENSOR_APPLY_SCALE(emul_v[2], scale[2]);
+	emul_v[3] = SENSOR_APPLY_SCALE(emul_v[3], scale[3]);
+
+	/* Set emulator values */
+	tcs_emul_set_val(emul, TCS_EMUL_C, emul_v[0]);
+	tcs_emul_set_val(emul, TCS_EMUL_R, emul_v[1]);
+	tcs_emul_set_val(emul, TCS_EMUL_G, emul_v[2]);
+	tcs_emul_set_val(emul, TCS_EMUL_B, emul_v[3]);
+}
+
+/** Test normal mode reading of light sensor values */
+ZTEST_USER(tcs3400, test_tcs_read_xyz)
+{
+	struct motion_sensor_t *ms, *ms_rgb;
+	const struct emul *emul = EMUL_DT_GET(TCS_NODE);
+	uint32_t event = TCS_INT_EVENT;
+	/* Expected data to test: IR, R, G, B */
+	int exp_v[][4] = {
+		{ 200, 1110, 870, 850 },       { 300, 1110, 10000, 8500 },
+		{ 600, 50000, 40000, 30000 },  { 1000, 3000, 40000, 2000 },
+		{ 1000, 65000, 65000, 65000 }, { 100, 214, 541, 516 },
+		{ 143, 2141, 5414, 5163 },     { 100, 50000, 40000, 30000 },
+		{ 1430, 2141, 5414, 5163 },    { 10000, 50000, 40000, 30000 },
+		{ 10000, 214, 541, 516 },      { 15000, 50000, 40000, 30000 },
+	};
+	uint16_t scale[4] = { MOTION_SENSE_DEFAULT_SCALE,
+			      MOTION_SENSE_DEFAULT_SCALE,
+			      MOTION_SENSE_DEFAULT_SCALE,
+			      MOTION_SENSE_DEFAULT_SCALE };
+	int i, test;
+	intv3_t v;
+
+	ms = &motion_sensors[TCS_CLR_SENSOR_ID];
+	ms_rgb = &motion_sensors[TCS_RGB_SENSOR_ID];
+
+	/* Need to be set to collect all data in FIFO */
+	ms->oversampling_ratio = 1;
+	ms_rgb->oversampling_ratio = 1;
+	/* Disable calibration mode */
+	zassert_equal(EC_SUCCESS, ms->drv->perform_calib(ms, 0));
+	/* Setup AGAIN and ATIME for normal mode */
+	zassert_equal(EC_RES_IN_PROGRESS, ms->drv->read(ms, v));
+
+	/* Test different data in supported range */
+	for (test = 0; test < ARRAY_SIZE(exp_v); test++) {
+		set_emul_val_from_exp(exp_v[test], scale, emul);
+
+		/* Run few times to allow driver change gain */
+		for (i = 0; i < 5; i++) {
+			tcs_emul_set_reg(emul, TCS_I2C_STATUS,
+					 TCS_I2C_STATUS_RGBC_VALID);
+			zassert_equal(EC_SUCCESS,
+				      ms->drv->irq_handler(ms, &event), NULL);
+		}
+		check_fifo(ms, ms_rgb, exp_v[test], V_EPS);
+	}
+
+	/* Test data that are outside of supported range */
+	exp_v[0][0] = 3000;
+	exp_v[0][1] = UINT16_MAX;
+	exp_v[0][2] = UINT16_MAX * 32;
+	exp_v[0][3] = 200;
+	set_emul_val_from_exp(exp_v[0], scale, emul);
+
+	/* Run few times to allow driver change gain */
+	for (i = 0; i < 10; i++) {
+		tcs_emul_set_reg(emul, TCS_I2C_STATUS,
+				 TCS_I2C_STATUS_RGBC_VALID);
+		zassert_equal(EC_SUCCESS, ms->drv->irq_handler(ms, &event),
+			      NULL);
+	}
+	/*
+	 * If saturation value is exceeded on any rgb sensor, than data
+	 * shouldn't be committed to FIFO.
+	 */
+	check_fifo_empty(ms, ms_rgb);
+}
+
+/**
+ * Test getting and setting scale of light sensor. Checks if collected values
+ * are scaled properly.
+ */
+ZTEST_USER(tcs3400, test_tcs_scale)
+{
+	struct motion_sensor_t *ms, *ms_rgb;
+	const struct emul *emul = EMUL_DT_GET(TCS_NODE);
+	uint32_t event = TCS_INT_EVENT;
+	/* Expected data to test: IR, R, G, B */
+	int exp_v[][4] = {
+		{ 200, 1110, 870, 850 },   { 300, 1110, 10000, 8500 },
+		{ 600, 5000, 4000, 3000 }, { 100, 3000, 4000, 2000 },
+		{ 100, 1000, 1000, 1000 },
+	};
+	/* Scale for each test */
+	uint16_t exp_scale[][4] = {
+		{ MOTION_SENSE_DEFAULT_SCALE, MOTION_SENSE_DEFAULT_SCALE,
+		  MOTION_SENSE_DEFAULT_SCALE, MOTION_SENSE_DEFAULT_SCALE },
+		{ MOTION_SENSE_DEFAULT_SCALE + 300,
+		  MOTION_SENSE_DEFAULT_SCALE + 300,
+		  MOTION_SENSE_DEFAULT_SCALE + 300,
+		  MOTION_SENSE_DEFAULT_SCALE + 300 },
+		{ MOTION_SENSE_DEFAULT_SCALE - 300,
+		  MOTION_SENSE_DEFAULT_SCALE - 300,
+		  MOTION_SENSE_DEFAULT_SCALE - 300,
+		  MOTION_SENSE_DEFAULT_SCALE - 300 },
+		{ MOTION_SENSE_DEFAULT_SCALE + 345,
+		  MOTION_SENSE_DEFAULT_SCALE - 5423,
+		  MOTION_SENSE_DEFAULT_SCALE - 30,
+		  MOTION_SENSE_DEFAULT_SCALE + 400 },
+		{ MOTION_SENSE_DEFAULT_SCALE - 345,
+		  MOTION_SENSE_DEFAULT_SCALE + 5423,
+		  MOTION_SENSE_DEFAULT_SCALE + 30,
+		  MOTION_SENSE_DEFAULT_SCALE - 400 },
+		{ MOTION_SENSE_DEFAULT_SCALE, MOTION_SENSE_DEFAULT_SCALE,
+		  MOTION_SENSE_DEFAULT_SCALE, MOTION_SENSE_DEFAULT_SCALE }
+	};
+	uint16_t scale[3];
+	int16_t temp;
+	int i, test;
+	intv3_t v;
+
+	ms = &motion_sensors[TCS_CLR_SENSOR_ID];
+	ms_rgb = &motion_sensors[TCS_RGB_SENSOR_ID];
+
+	/* Need to be set to collect all data in FIFO */
+	ms->oversampling_ratio = 1;
+	ms_rgb->oversampling_ratio = 1;
+	/* Disable calibration mode */
+	zassert_equal(EC_SUCCESS, ms->drv->perform_calib(ms, 0));
+	/* Setup AGAIN and ATIME for normal mode */
+	zassert_equal(EC_RES_IN_PROGRESS, ms->drv->read(ms, v));
+
+	/* Test different data in supported range */
+	for (test = 0; test < ARRAY_SIZE(exp_v); test++) {
+		/* Set and test clear sensor scale */
+		zassert_equal(EC_SUCCESS,
+			      ms->drv->set_scale(ms, exp_scale[test], 0),
+			      "test %d", test);
+		zassert_equal(EC_SUCCESS, ms->drv->get_scale(ms, scale, &temp),
+			      "test %d", test);
+		zassert_equal((int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP, temp,
+			      "test %d, %d", test, temp);
+		zassert_equal(exp_scale[test][0], scale[0], "test %d", test);
+
+		/* Set and test RGB sensor scale */
+		zassert_equal(EC_SUCCESS,
+			      ms_rgb->drv->set_scale(ms_rgb,
+						     &(exp_scale[test][1]), 0),
+			      "test %d", test);
+		zassert_equal(EC_SUCCESS,
+			      ms_rgb->drv->get_scale(ms_rgb, scale, &temp),
+			      "test %d", test);
+		zassert_equal((int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP, temp,
+			      "test %d", test);
+		zassert_equal(exp_scale[test][1], scale[0], "test %d", test);
+		zassert_equal(exp_scale[test][2], scale[1], "test %d", test);
+		zassert_equal(exp_scale[test][3], scale[2], "test %d", test);
+
+		set_emul_val_from_exp(exp_v[test], exp_scale[test], emul);
+
+		/* Run few times to allow driver change gain */
+		for (i = 0; i < 5; i++) {
+			tcs_emul_set_reg(emul, TCS_I2C_STATUS,
+					 TCS_I2C_STATUS_RGBC_VALID);
+			zassert_equal(EC_SUCCESS,
+				      ms->drv->irq_handler(ms, &event), NULL);
+		}
+		check_fifo(ms, ms_rgb, exp_v[test], V_EPS);
+	}
+
+	/* Test fail if scale equals 0 */
+	scale[0] = 0;
+	scale[1] = MOTION_SENSE_DEFAULT_SCALE;
+	scale[2] = MOTION_SENSE_DEFAULT_SCALE;
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_scale(ms, scale, 0));
+
+	zassert_equal(EC_ERROR_INVAL, ms_rgb->drv->set_scale(ms_rgb, scale, 0),
+		      NULL);
+	scale[0] = MOTION_SENSE_DEFAULT_SCALE;
+	scale[1] = 0;
+	scale[2] = MOTION_SENSE_DEFAULT_SCALE;
+	zassert_equal(EC_ERROR_INVAL, ms_rgb->drv->set_scale(ms_rgb, scale, 0),
+		      NULL);
+	scale[0] = MOTION_SENSE_DEFAULT_SCALE;
+	scale[1] = MOTION_SENSE_DEFAULT_SCALE;
+	scale[2] = 0;
+	zassert_equal(EC_ERROR_INVAL, ms_rgb->drv->set_scale(ms_rgb, scale, 0),
+		      NULL);
+}
+
+/** Test setting and getting data rate of light sensor */
+ZTEST_USER(tcs3400, test_tcs_data_rate)
+{
+	struct motion_sensor_t *ms, *ms_rgb;
+	const struct emul *emul = EMUL_DT_GET(TCS_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcs3400_get_i2c_common_data(emul);
+	uint8_t enable;
+
+	ms = &motion_sensors[TCS_CLR_SENSOR_ID];
+	/* RGB sensor doesn't set rate, but return rate of clear sesnor */
+	ms_rgb = &motion_sensors[TCS_RGB_SENSOR_ID];
+
+	/* Test fail on reading device power state */
+	i2c_common_emul_set_read_fail_reg(common_data, TCS_I2C_ENABLE);
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 0, 0));
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 0, 1));
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 100, 0));
+	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 100, 1));
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* Test setting 0 rate disables device */
+	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, 0, 0));
+	zassert_equal(0, tcs_emul_get_reg(emul, TCS_I2C_ENABLE));
+	zassert_equal(0, ms->drv->get_data_rate(ms));
+	zassert_equal(0, ms_rgb->drv->get_data_rate(ms_rgb));
+
+	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, 0, 1));
+	zassert_equal(0, tcs_emul_get_reg(emul, TCS_I2C_ENABLE));
+	zassert_equal(0, tcs_emul_get_reg(emul, TCS_I2C_ENABLE));
+	zassert_equal(0, ms->drv->get_data_rate(ms));
+	zassert_equal(0, ms_rgb->drv->get_data_rate(ms_rgb));
+
+	/* Test setting non-zero rate enables device */
+	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, 100, 0));
+	enable = tcs_emul_get_reg(emul, TCS_I2C_ENABLE);
+	zassert_true(enable & TCS_I2C_ENABLE_POWER_ON);
+	zassert_true(enable & TCS_I2C_ENABLE_ADC_ENABLE);
+	zassert_true(enable & TCS_I2C_ENABLE_INT_ENABLE);
+	zassert_equal(100, ms->drv->get_data_rate(ms));
+	zassert_equal(100, ms_rgb->drv->get_data_rate(ms_rgb));
+
+	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, 100, 1));
+	enable = tcs_emul_get_reg(emul, TCS_I2C_ENABLE);
+	zassert_true(enable & TCS_I2C_ENABLE_POWER_ON);
+	zassert_true(enable & TCS_I2C_ENABLE_ADC_ENABLE);
+	zassert_true(enable & TCS_I2C_ENABLE_INT_ENABLE);
+	zassert_equal(100, ms->drv->get_data_rate(ms));
+	zassert_equal(100, ms_rgb->drv->get_data_rate(ms_rgb));
+
+	/* Test RGB sensor doesn't change data rate */
+	zassert_equal(EC_SUCCESS, ms_rgb->drv->set_data_rate(ms_rgb, 300, 0),
+		      NULL);
+	zassert_equal(100, ms->drv->get_data_rate(ms));
+	zassert_equal(100, ms_rgb->drv->get_data_rate(ms_rgb));
+
+	zassert_equal(EC_SUCCESS, ms_rgb->drv->set_data_rate(ms_rgb, 300, 1),
+		      NULL);
+	zassert_equal(100, ms->drv->get_data_rate(ms));
+	zassert_equal(100, ms_rgb->drv->get_data_rate(ms_rgb));
+}
+
+/** Test set range function of clear and RGB sensors */
+ZTEST_USER(tcs3400, test_tcs_set_range)
+{
+	struct motion_sensor_t *ms, *ms_rgb;
+
+	ms = &motion_sensors[TCS_CLR_SENSOR_ID];
+	ms_rgb = &motion_sensors[TCS_RGB_SENSOR_ID];
+
+	/* RGB sensor doesn't set anything */
+	zassert_equal(EC_SUCCESS, ms_rgb->drv->set_range(ms_rgb, 1, 0));
+
+	/* Clear sensor doesn't change anything on device to set range */
+	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, 0x12300, 1));
+	zassert_equal(0x12300, ms->current_range);
+
+	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, 0x10000, 0));
+	zassert_equal(0x10000, ms->current_range);
+}
+
+struct tcs3400_test_fixture {
+	struct als_drv_data_t drv_data;
+	struct tcs3400_rgb_drv_data_t rgb_drv_data;
+};
+
+static void tcs3400_before(void *state)
+{
+	struct tcs3400_test_fixture *f = state;
+
+	f->drv_data = *TCS3400_DRV_DATA(&motion_sensors[TCS_CLR_SENSOR_ID]);
+	f->rgb_drv_data =
+		*TCS3400_RGB_DRV_DATA(&motion_sensors[TCS_RGB_SENSOR_ID]);
+}
+
+static void tcs3400_after(void *state)
+{
+	struct tcs3400_test_fixture *f = state;
+
+	*TCS3400_DRV_DATA(&motion_sensors[TCS_CLR_SENSOR_ID]) = f->drv_data;
+	*TCS3400_RGB_DRV_DATA(&motion_sensors[TCS_RGB_SENSOR_ID]) =
+		f->rgb_drv_data;
+}
+
+static void *tcs3400_setup(void)
+{
+	static struct tcs3400_test_fixture tcs3400_fixture = { 0 };
+
+	return &tcs3400_fixture;
+}
+
+ZTEST_SUITE(tcs3400, drivers_predicate_post_main, tcs3400_setup, tcs3400_before,
+	    tcs3400_after, NULL);
diff --git a/zephyr/test/drivers/default/src/temp_sensor.c b/zephyr/test/drivers/default/src/temp_sensor.c
new file mode 100644
index 0000000000..fd092e37cb
--- /dev/null
+++ b/zephyr/test/drivers/default/src/temp_sensor.c
@@ -0,0 +1,293 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "driver/temp_sensor/pct2075.h"
+#include "emul/emul_pct2075.h"
+#include "math_util.h"
+#include "temp_sensor.h"
+#include "temp_sensor/temp_sensor.h"
+#include "test/drivers/test_state.h"
+#include "timer.h"
+
+#include <math.h>
+
+#include <zephyr/drivers/adc.h>
+#include <zephyr/drivers/adc/adc_emul.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+#define GPIO_PG_EC_DSW_PWROK_PATH NAMED_GPIOS_GPIO_NODE(pg_ec_dsw_pwrok)
+#define GPIO_PG_EC_DSW_PWROK_PORT DT_GPIO_PIN(GPIO_PG_EC_DSW_PWROK_PATH, gpios)
+
+#define GPIO_EC_PG_PIN_TEMP_PATH NAMED_GPIOS_GPIO_NODE(ec_pg_pin_temp)
+#define GPIO_EC_PG_PIN_TEMP_PORT DT_GPIO_PIN(GPIO_EC_PG_PIN_TEMP_PATH, gpios)
+
+#define ADC_DEVICE_NODE DT_NODELABEL(adc0)
+#define ADC_CHANNELS_NUM DT_PROP(DT_NODELABEL(adc0), nchannels)
+
+/** Test error code when invalid sensor is passed to temp_sensor_read() */
+ZTEST_USER(temp_sensor, test_temp_sensor_wrong_id)
+{
+	int temp;
+
+	zassert_equal(EC_ERROR_INVAL,
+		      temp_sensor_read(TEMP_SENSOR_COUNT, &temp), NULL);
+}
+
+/** Test error code when temp_sensor_read() is called with powered off ADC */
+ZTEST_USER(temp_sensor, test_temp_sensor_adc_error)
+{
+	const struct device *gpio_dev =
+		DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_PG_EC_DSW_PWROK_PATH, gpios));
+	int temp;
+
+	zassert_not_null(gpio_dev, "Cannot get GPIO device");
+
+	/*
+	 * pg_ec_dsw_pwrok = 0 means ADC is not powered.
+	 * adc_read will return error
+	 */
+	zassert_ok(gpio_emul_input_set(gpio_dev, GPIO_PG_EC_DSW_PWROK_PORT, 0),
+		   NULL);
+
+	zassert_equal(EC_ERROR_NOT_POWERED,
+		      temp_sensor_read(
+			      TEMP_SENSOR_ID(DT_NODELABEL(named_temp_charger)),
+			      &temp),
+		      NULL);
+	zassert_equal(EC_ERROR_NOT_POWERED,
+		      temp_sensor_read(
+			      TEMP_SENSOR_ID(DT_NODELABEL(named_temp_ddr_soc)),
+			      &temp),
+		      NULL);
+	zassert_equal(
+		EC_ERROR_NOT_POWERED,
+		temp_sensor_read(TEMP_SENSOR_ID(DT_NODELABEL(named_temp_fan)),
+				 &temp),
+		NULL);
+	zassert_equal(EC_ERROR_NOT_POWERED,
+		      temp_sensor_read(TEMP_SENSOR_ID(DT_NODELABEL(
+					       named_temp_pp3300_regulator)),
+				       &temp),
+		      NULL);
+
+	/* power ADC */
+	zassert_ok(gpio_emul_input_set(gpio_dev, GPIO_PG_EC_DSW_PWROK_PORT, 1),
+		   NULL);
+}
+
+/** Test error code when temp_sensor_read() is called power-good-pin low */
+ZTEST_USER(temp_sensor, test_temp_sensor_pg_pin)
+{
+	const struct device *gpio_dev =
+		DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_EC_PG_PIN_TEMP_PATH, gpios));
+	int temp;
+
+	zassert_not_null(gpio_dev, "Cannot get GPIO device");
+
+	/* ec_pg_pin_temp = 0 means temperature sensors are not powered. */
+	zassert_ok(gpio_emul_input_set(gpio_dev, GPIO_EC_PG_PIN_TEMP_PORT, 0),
+		   NULL);
+
+	zassert_equal(EC_ERROR_NOT_POWERED,
+		      temp_sensor_read(
+			      TEMP_SENSOR_ID(DT_NODELABEL(named_temp_charger)),
+			      &temp),
+		      NULL);
+	zassert_equal(EC_ERROR_NOT_POWERED,
+		      temp_sensor_read(
+			      TEMP_SENSOR_ID(DT_NODELABEL(named_temp_ddr_soc)),
+			      &temp),
+		      NULL);
+	zassert_equal(
+		EC_ERROR_NOT_POWERED,
+		temp_sensor_read(TEMP_SENSOR_ID(DT_NODELABEL(named_temp_fan)),
+				 &temp),
+		NULL);
+	zassert_equal(EC_ERROR_NOT_POWERED,
+		      temp_sensor_read(TEMP_SENSOR_ID(DT_NODELABEL(
+					       named_temp_pp3300_regulator)),
+				       &temp),
+		      NULL);
+	zassert_equal(
+		EC_ERROR_NOT_POWERED,
+		temp_sensor_read(TEMP_SENSOR_ID(DT_NODELABEL(named_pct2075)),
+				 &temp),
+		NULL);
+
+	/* power ADC */
+	zassert_ok(gpio_emul_input_set(gpio_dev, GPIO_EC_PG_PIN_TEMP_PORT, 1),
+		   NULL);
+}
+
+/** Simple ADC emulator custom function which always return error */
+static int adc_error_func(const struct device *dev, unsigned int channel,
+			  void *param, uint32_t *result)
+{
+	return -EINVAL;
+}
+
+/**
+ * Set valid response only for ADC channel connected with tested sensor.
+ * Check if temp_sensor_read() from tested sensor returns EC_SUCCESS and
+ * valid temperature. Set invalid response on ADC channel for next test.
+ */
+static void check_valid_temperature(const struct device *adc_dev, int sensor)
+{
+	int temp;
+
+	/* ADC channel of tested sensor return valid value */
+	zassert_ok(adc_emul_const_value_set(adc_dev, temp_sensors[sensor].idx,
+					    1000),
+		   "adc_emul_const_value_set() failed (sensor %d)", sensor);
+	zassert_equal(EC_SUCCESS, temp_sensor_read(sensor, &temp));
+	zassert_within(
+		temp, 273 + 50, 51,
+		"Expected temperature in 0*C-100*C, got %d*C (sensor %d)",
+		temp - 273, sensor);
+	/* Return error on ADC channel of tested sensor */
+	zassert_ok(adc_emul_value_func_set(adc_dev, temp_sensors[sensor].idx,
+					   adc_error_func, NULL),
+		   "adc_emul_value_func_set() failed (sensor %d)", sensor);
+}
+
+/** Test if temp_sensor_read() returns temperature on success */
+ZTEST_USER(temp_sensor, test_temp_sensor_read)
+{
+	const struct device *adc_dev = DEVICE_DT_GET(ADC_DEVICE_NODE);
+	int chan;
+
+	zassert_not_null(adc_dev, "Cannot get ADC device");
+
+	/* Return error on all ADC channels */
+	for (chan = 0; chan < ADC_CHANNELS_NUM; chan++) {
+		zassert_ok(adc_emul_value_func_set(adc_dev, chan,
+						   adc_error_func, NULL),
+			   "channel %d adc_emul_value_func_set() failed", chan);
+	}
+
+	check_valid_temperature(
+		adc_dev, TEMP_SENSOR_ID(DT_NODELABEL(named_temp_charger)));
+	check_valid_temperature(
+		adc_dev, TEMP_SENSOR_ID(DT_NODELABEL(named_temp_ddr_soc)));
+	check_valid_temperature(adc_dev,
+				TEMP_SENSOR_ID(DT_NODELABEL(named_temp_fan)));
+	check_valid_temperature(adc_dev, TEMP_SENSOR_ID(DT_NODELABEL(
+						 named_temp_pp3300_regulator)));
+
+	/* Return correct value on all ADC channels */
+	for (chan = 0; chan < ADC_CHANNELS_NUM; chan++) {
+		zassert_ok(adc_emul_const_value_set(adc_dev, chan, 1000),
+			   "channel %d adc_emul_const_value_set() failed",
+			   chan);
+	}
+}
+
+/** Test if temp_sensor_read() returns temperature on success for PCT2075 */
+ZTEST_USER(temp_sensor, test_temp_sensor_pct2075)
+{
+	int temp;
+	const struct emul *dev = EMUL_DT_GET(DT_NODELABEL(pct2075_emul));
+	int mk[] = {
+		MILLI_CELSIUS_TO_MILLI_KELVIN(127000),
+		MILLI_CELSIUS_TO_MILLI_KELVIN(126850),
+		MILLI_CELSIUS_TO_MILLI_KELVIN(125),
+		MILLI_CELSIUS_TO_MILLI_KELVIN(0),
+		MILLI_CELSIUS_TO_MILLI_KELVIN(-125),
+		MILLI_CELSIUS_TO_MILLI_KELVIN(-54875),
+		MILLI_CELSIUS_TO_MILLI_KELVIN(-55000),
+	};
+
+	for (int i = 0; i < ARRAY_SIZE(mk); i++) {
+		pct2075_emul_set_temp(dev, mk[i]);
+		/* Highly dependent on current implementation. The sensor
+		 * update temperature in the 1 second periodic hook, so
+		 * we need to wait for it.
+		 */
+		msleep(1100);
+		zassert_equal(EC_SUCCESS,
+			      temp_sensor_read(TEMP_SENSOR_ID(DT_NODELABEL(
+						       named_pct2075)),
+					       &temp));
+		zassert_equal(MILLI_KELVIN_TO_KELVIN(mk[i]), temp);
+	}
+}
+
+/** Test if temperature is not updated on I2C read fail.
+ *  The test highly dependent on current implementation - temp_sensor_read
+ *  doesn't return an error on the i2c read fail, which can/should be changed
+ *  in the future.
+ */
+ZTEST_USER(temp_sensor, test_temp_sensor_pct2075_fail)
+{
+	const struct emul *dev = EMUL_DT_GET(DT_NODELABEL(pct2075_emul));
+	struct pct2075_data *data = (struct pct2075_data *)dev->data;
+	int mk1 = 373000, mk2 = 273000;
+	int temp;
+
+	/* Set initial temperature */
+	pct2075_emul_set_temp(dev, mk1);
+	msleep(1100);
+
+	zassert_equal(EC_SUCCESS, temp_sensor_read(TEMP_SENSOR_ID(DT_NODELABEL(
+							   named_pct2075)),
+						   &temp));
+	/* Make sure the temperature is read correctly */
+	zassert_equal(MILLI_KELVIN_TO_KELVIN(mk1), temp);
+
+	/* Set I2C fail on the temperature register */
+	i2c_common_emul_set_read_fail_reg(&data->common, PCT2075_REG_TEMP);
+	pct2075_emul_set_temp(dev, mk2);
+	/* Wait for potential update */
+	msleep(1100);
+
+	/* Make sure the temperature is not changed */
+	zassert_equal(EC_SUCCESS, temp_sensor_read(TEMP_SENSOR_ID(DT_NODELABEL(
+							   named_pct2075)),
+						   &temp));
+	zassert_equal(MILLI_KELVIN_TO_KELVIN(mk1), temp);
+
+	/* Restore I2C */
+	i2c_common_emul_set_read_fail_reg(&data->common,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	/* Wait for update */
+	msleep(1100);
+	/* Make sure the temperature is updated */
+	zassert_equal(EC_SUCCESS, temp_sensor_read(TEMP_SENSOR_ID(DT_NODELABEL(
+							   named_pct2075)),
+						   &temp));
+	zassert_equal(MILLI_KELVIN_TO_KELVIN(mk2), temp);
+}
+
+static void *temp_sensor_setup(void)
+{
+	const struct device *dev =
+		DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_PG_EC_DSW_PWROK_PATH, gpios));
+	const struct device *dev_pin =
+		DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_EC_PG_PIN_TEMP_PATH, gpios));
+	const struct emul *pct2075_dev =
+		EMUL_DT_GET(DT_NODELABEL(pct2075_emul));
+	struct pct2075_data *pct2075_data =
+		(struct pct2075_data *)pct2075_dev->data;
+
+	zassert_not_null(dev, NULL);
+	/* Before tests make sure that power pins are set. */
+	zassert_ok(gpio_emul_input_set(dev, GPIO_PG_EC_DSW_PWROK_PORT, 1),
+		   NULL);
+	zassert_ok(gpio_emul_input_set(dev_pin, GPIO_EC_PG_PIN_TEMP_PORT, 1),
+		   NULL);
+
+	i2c_common_emul_set_read_fail_reg(&pct2075_data->common,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	return NULL;
+}
+
+ZTEST_SUITE(temp_sensor, drivers_predicate_post_main, temp_sensor_setup, NULL,
+	    NULL, NULL);
diff --git a/zephyr/test/drivers/default/src/thermistor.c b/zephyr/test/drivers/default/src/thermistor.c
new file mode 100644
index 0000000000..359b14ade9
--- /dev/null
+++ b/zephyr/test/drivers/default/src/thermistor.c
@@ -0,0 +1,358 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "../driver/temp_sensor/thermistor.h"
+#include "common.h"
+#include "temp_sensor/temp_sensor.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/drivers/adc.h>
+#include <zephyr/drivers/adc/adc_emul.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+#include <temp_sensor.h>
+
+#define GPIO_PG_EC_DSW_PWROK_PATH NAMED_GPIOS_GPIO_NODE(pg_ec_dsw_pwrok)
+#define GPIO_PG_EC_DSW_PWROK_PORT DT_GPIO_PIN(GPIO_PG_EC_DSW_PWROK_PATH, gpios)
+
+#define GPIO_EC_PG_PIN_TEMP_PATH NAMED_GPIOS_GPIO_NODE(ec_pg_pin_temp)
+#define GPIO_EC_PG_PIN_TEMP_PORT DT_GPIO_PIN(GPIO_EC_PG_PIN_TEMP_PATH, gpios)
+
+#define ADC_DEVICE_NODE DT_NODELABEL(adc0)
+
+/* TODO replace counting macros with DT macro when
+ * https://github.com/zephyrproject-rtos/zephyr/issues/38715 lands
+ */
+#define _ACCUMULATOR(x) 1 +
+#define NAMED_TEMP_SENSORS_SIZE \
+	DT_FOREACH_CHILD(TEMP_SENSORS_NODEID, _ACCUMULATOR) 0
+
+#define TEMP_SENSORS_ENABLED_SIZE FOREACH_TEMP_SENSOR(_ACCUMULATOR) 0
+
+/* Conversion of temperature doesn't need to be 100% accurate */
+#define TEMP_EPS 2
+
+#define A_VALID_VOLTAGE 1000
+/**
+ * Test if get temp function return expected error when ADC is not powered
+ * (indicated as GPIO pin set to low) and return success after powering on ADC.
+ */
+ZTEST_USER(thermistor, test_thermistor_power_pin)
+{
+	int temp;
+	int sensor_idx;
+
+	const struct device *gpio_dev =
+		DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_PG_EC_DSW_PWROK_PATH, gpios));
+	const struct device *adc_dev = DEVICE_DT_GET(ADC_DEVICE_NODE);
+
+	zassert_not_null(gpio_dev, "Cannot get GPIO device");
+	zassert_not_null(adc_dev, "Cannot get ADC device");
+
+	/* Make sure that ADC return a valid value */
+	for (sensor_idx = 0; sensor_idx < NAMED_TEMP_SENSORS_SIZE;
+	     sensor_idx++) {
+		const struct temp_sensor_t *sensor = &temp_sensors[sensor_idx];
+
+		/* Skip for sensors that are not thermistors */
+		if (sensor->zephyr_info->thermistor == NULL)
+			continue;
+
+		zassert_ok(adc_emul_const_value_set(adc_dev, sensor->idx,
+						    A_VALID_VOLTAGE),
+			   "adc_emul_value_func_set() failed on %s",
+			   sensor->name);
+	}
+
+	/* pg_ec_dsw_pwrok = 0 means ADC is not powered. */
+	zassert_ok(gpio_emul_input_set(gpio_dev, GPIO_PG_EC_DSW_PWROK_PORT, 0),
+		   NULL);
+
+	for (sensor_idx = 0; sensor_idx < NAMED_TEMP_SENSORS_SIZE;
+	     sensor_idx++) {
+		const struct temp_sensor_t *sensor = &temp_sensors[sensor_idx];
+
+		/* Skip for sensors that are not thermistors */
+		if (sensor->zephyr_info->thermistor == NULL)
+			continue;
+
+		zassert_equal(EC_ERROR_NOT_POWERED,
+			      sensor->zephyr_info->read(sensor, &temp),
+			      "%s failed", sensor->name);
+	}
+
+	/* pg_ec_dsw_pwrok = 1 means ADC is powered. */
+	zassert_ok(gpio_emul_input_set(gpio_dev, GPIO_PG_EC_DSW_PWROK_PORT, 1),
+		   NULL);
+
+	for (sensor_idx = 0; sensor_idx < NAMED_TEMP_SENSORS_SIZE;
+	     sensor_idx++) {
+		const struct temp_sensor_t *sensor = &temp_sensors[sensor_idx];
+
+		/* Skip for sensors that are not thermistors */
+		if (sensor->zephyr_info->thermistor == NULL)
+			continue;
+
+		zassert_equal(EC_SUCCESS,
+			      sensor->zephyr_info->read(sensor, &temp),
+			      "%s failed", sensor->name);
+	}
+}
+
+/* Simple ADC emulator custom function which always return error */
+static int adc_error_func(const struct device *dev, unsigned int channel,
+			  void *param, uint32_t *result)
+{
+	return -EINVAL;
+}
+
+/** Test if get temp function return expected error on ADC malfunction */
+ZTEST_USER(thermistor, test_thermistor_adc_read_error)
+{
+	int temp;
+	int sensor_idx;
+
+	const struct device *adc_dev = DEVICE_DT_GET(ADC_DEVICE_NODE);
+
+	zassert_not_null(adc_dev, "Cannot get ADC device");
+
+	/* Return error on all ADC channels */
+	for (sensor_idx = 0; sensor_idx < NAMED_TEMP_SENSORS_SIZE;
+	     sensor_idx++) {
+		const struct temp_sensor_t *sensor = &temp_sensors[sensor_idx];
+
+		/* Skip for sensors that are not thermistors */
+		if (sensor->zephyr_info->thermistor == NULL)
+			continue;
+
+		zassert_ok(adc_emul_value_func_set(adc_dev, sensor->idx,
+						   adc_error_func, NULL),
+			   "adc_emul_value_func_set() failed on %s",
+			   sensor->name);
+	}
+
+	for (sensor_idx = 0; sensor_idx < NAMED_TEMP_SENSORS_SIZE;
+	     sensor_idx++) {
+		const struct temp_sensor_t *sensor = &temp_sensors[sensor_idx];
+
+		/* Skip for sensors that are not thermistors */
+		if (sensor->zephyr_info->thermistor == NULL)
+			continue;
+
+		zassert_equal(EC_ERROR_UNKNOWN,
+			      sensor->zephyr_info->read(sensor, &temp),
+			      "%s failed", sensor->name);
+	}
+}
+
+/** Get resistance of thermistor for given temperature */
+static int resistance_47kohm_B4050(int t)
+{
+	/* Thermistor manufacturer resistance lookup table*/
+	int r_table[] = {
+		155700, 147900, 140600, 133700, 127200, /* 0*C  - 4*C */
+		121000, 115100, 109600, 104300, 99310, /* 5*C  - 9*C */
+		94600,	90130,	85890,	81870,	78070, /* 10*C - 14*C */
+		74450,	71020,	67770,	64680,	61750, /* 15*C - 19*C */
+		58970,	56320,	53810,	51430,	49160, /* 20*C - 24*C */
+		47000,	44950,	42990,	41130,	39360, /* 25*C - 29*C */
+		37680,	36070,	34540,	33080,	31690, /* 30*C - 34*C */
+		30360,	29100,	27900,	26750,	25650, /* 35*C - 39*C */
+		24610,	23610,	22660,	21750,	20880, /* 40*C - 44*C */
+		20050,	19260,	18500,	17780,	17090, /* 45*C - 49*C */
+		16430,	15800,	15200,	14620,	14070, /* 50*C - 54*C */
+		13540,	13030,	12550,	12090,	11640, /* 55*C - 59*C */
+		11210,	10800,	10410,	10040,	9676, /* 60*C - 64*C */
+		9331,	8999,	8680,	8374,	8081, /* 65*C - 69*C */
+		7799,	7528,	7268,	7018,	6777, /* 70*C - 74*C */
+		6546,	6324,	6111,	5906,	5708, /* 75*C - 79*C */
+		5518,	5335,	5160,	4990,	4827, /* 80*C - 84*C */
+		4671,	4519,	4374,	4233,	4098, /* 85*C - 89*C */
+		3968,	3842,	3721,	3605,	3492, /* 90*C - 94*C */
+		3384,	3279,	3179,	3082,	2988, /* 95*C - 99*C */
+		2898 /* 100*C */
+	};
+
+	t -= 273;
+	if (t < 0)
+		return r_table[0] + 10000;
+
+	if (t >= ARRAY_SIZE(r_table))
+		return r_table[ARRAY_SIZE(r_table) - 1] - 100;
+
+	return r_table[t];
+}
+
+/**
+ * Calculate output voltage in voltage divider circuit using formula
+ * Vout = Vs * r2 / (r1 + r2)
+ */
+static int volt_divider(int vs, int r1, int r2)
+{
+	return vs * r2 / (r1 + r2);
+}
+
+struct thermistor_state {
+	const int v;
+	const int r;
+	int temp_expected;
+};
+
+/** ADC emulator function which calculate output voltage for given thermistor */
+static int adc_temperature_func(const struct device *dev, unsigned int channel,
+				void *param, uint32_t *result)
+{
+	struct thermistor_state *s = (struct thermistor_state *)param;
+
+	*result = volt_divider(s->v, s->r,
+			       resistance_47kohm_B4050(s->temp_expected));
+
+	return 0;
+}
+
+/** Test conversion from ADC raw value to temperature */
+static void do_thermistor_test(const struct temp_sensor_t *temp_sensor,
+			       int reference_mv, int reference_ohms)
+{
+	int temp_expected;
+	int temp;
+
+	const struct device *adc_dev = DEVICE_DT_GET(ADC_DEVICE_NODE);
+	struct thermistor_state state = {
+		.v = reference_mv,
+		.r = reference_ohms,
+	};
+
+	zassert_not_null(adc_dev, "Cannot get ADC device");
+
+	/* Setup ADC channel */
+	zassert_ok(adc_emul_value_func_set(adc_dev, temp_sensor->idx,
+					   adc_temperature_func, &state),
+		   "adc_emul_value_func_set() failed on %s", temp_sensor->name);
+
+	/* Makes sure that reference voltage is correct for given thermistor */
+	zassert_ok(adc_emul_ref_voltage_set(adc_dev, ADC_REF_INTERNAL, state.v),
+		   "adc_emul_ref_voltage_set() failed %s on ",
+		   temp_sensor->name);
+
+	/* Test whole supported range from 0*C to 100*C (273*K to 373*K) */
+	for (temp_expected = 273; temp_expected <= 373; temp_expected++) {
+		state.temp_expected = temp_expected;
+		zassert_equal(EC_SUCCESS,
+			      temp_sensor->zephyr_info->read(temp_sensor,
+							     &temp),
+			      "failed on %s", temp_sensor->name);
+		zassert_within(temp_expected, temp, TEMP_EPS,
+			       "Expected %d*K, got %d*K on %s", temp_expected,
+			       temp, temp_sensor->name);
+	}
+
+	/* Temperatures below 0*C should be reported as 0*C */
+	state.temp_expected = -15 + 273;
+	zassert_equal(EC_SUCCESS,
+		      temp_sensor->zephyr_info->read(temp_sensor, &temp),
+		      "failed on %s", temp_sensor->name);
+	zassert_equal(273, temp, "Expected %d*K, got %d*K on %s", 273, temp,
+		      temp_sensor->name);
+
+	/* Temperatures above 100*C should be reported as 100*C */
+	state.temp_expected = 115 + 273;
+	zassert_equal(EC_SUCCESS,
+		      temp_sensor->zephyr_info->read(temp_sensor, &temp),
+		      "failed on %s", temp_sensor->name);
+	zassert_equal(373, temp, "Expected %d*K, got %d*K on %s", 373, temp,
+		      temp_sensor->name);
+}
+
+#define GET_THERMISTOR_REF_MV(node_id)              \
+	[TEMP_SENSOR_ID_BY_DEV(node_id)] = DT_PROP( \
+		DT_PHANDLE(node_id, thermistor), steinhart_reference_mv),
+
+#define GET_THERMISTOR_REF_RES(node_id)             \
+	[TEMP_SENSOR_ID_BY_DEV(node_id)] = DT_PROP( \
+		DT_PHANDLE(node_id, thermistor), steinhart_reference_res),
+
+ZTEST_USER(thermistor, test_thermistors_adc_temperature_conversion)
+{
+	int sensor_idx;
+
+	const static int reference_mv_arr[] = { DT_FOREACH_STATUS_OKAY(
+		THERMISTOR_COMPAT, GET_THERMISTOR_REF_MV) };
+	const static int reference_res_arr[] = { DT_FOREACH_STATUS_OKAY(
+		THERMISTOR_COMPAT, GET_THERMISTOR_REF_RES) };
+
+	for (sensor_idx = 0; sensor_idx < NAMED_TEMP_SENSORS_SIZE;
+	     sensor_idx++) {
+		/* Skip for sensors that are not thermistors */
+		if (temp_sensors[sensor_idx].zephyr_info->thermistor == NULL)
+			continue;
+
+		do_thermistor_test(&temp_sensors[sensor_idx],
+				   reference_mv_arr[sensor_idx],
+				   reference_res_arr[sensor_idx]);
+	}
+}
+
+ZTEST_USER(thermistor, test_device_nodes_enabled)
+{
+	zassert_equal(NAMED_TEMP_SENSORS_SIZE, TEMP_SENSORS_ENABLED_SIZE,
+		      "Temperature sensors in device tree and "
+		      "those enabled for test differ");
+
+	/* Thermistor nodes being enabled are already tested by compilation. */
+}
+
+static void *thermistor_setup(void)
+{
+	const struct device *dev =
+		DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_PG_EC_DSW_PWROK_PATH, gpios));
+	const struct device *dev_pin =
+		DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_EC_PG_PIN_TEMP_PATH, gpios));
+
+	zassert_not_null(dev, NULL);
+	/* Before tests make sure that power pins are set. */
+	zassert_ok(gpio_emul_input_set(dev, GPIO_PG_EC_DSW_PWROK_PORT, 1),
+		   NULL);
+	zassert_ok(gpio_emul_input_set(dev_pin, GPIO_EC_PG_PIN_TEMP_PORT, 1),
+		   NULL);
+
+	return NULL;
+}
+
+static void thermistor_cleanup(void *state)
+{
+	int sensor_idx;
+	const struct device *adc_dev = DEVICE_DT_GET(ADC_DEVICE_NODE);
+
+	const static int reference_mv_arr[] = { DT_FOREACH_STATUS_OKAY(
+		THERMISTOR_COMPAT, GET_THERMISTOR_REF_MV) };
+	const static int reference_res_arr[] = { DT_FOREACH_STATUS_OKAY(
+		THERMISTOR_COMPAT, GET_THERMISTOR_REF_RES) };
+
+	if (adc_dev == NULL)
+		TC_ERROR("Cannot get ADC device");
+
+	for (sensor_idx = 0; sensor_idx < NAMED_TEMP_SENSORS_SIZE;
+	     sensor_idx++) {
+		/* Skip for sensors that are not thermistors */
+		if (temp_sensors[sensor_idx].zephyr_info->thermistor == NULL)
+			continue;
+
+		/* Setup ADC to return 27*C (300K) which is reasonable value */
+		adc_emul_const_value_set(
+			adc_dev, temp_sensors[sensor_idx].idx,
+			volt_divider(reference_mv_arr[sensor_idx],
+				     reference_res_arr[sensor_idx],
+				     resistance_47kohm_B4050(300)));
+		adc_emul_ref_voltage_set(adc_dev, ADC_REF_INTERNAL,
+					 reference_mv_arr[sensor_idx]);
+	}
+}
+
+ZTEST_SUITE(thermistor, drivers_predicate_post_main, thermistor_setup, NULL,
+	    NULL, thermistor_cleanup);
diff --git a/zephyr/test/drivers/default/src/uart_hostcmd.c b/zephyr/test/drivers/default/src/uart_hostcmd.c
new file mode 100644
index 0000000000..5e45d98980
--- /dev/null
+++ b/zephyr/test/drivers/default/src/uart_hostcmd.c
@@ -0,0 +1,225 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "host_command.h"
+#include "test/drivers/test_state.h"
+#include "uart.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+/** Messages used in test */
+static const char msg1[] = "test";
+static const char msg2[] = "uart_hostcmd";
+static const char msg3[] = "message3";
+
+/** Length of message excluding NULL char at the end */
+#define MSG_LEN(msg) (sizeof(msg) - 1)
+
+/**
+ * Write message 1 before first snapshot. Read everything from buffer. Create
+ * second snapshot. Write message 2 after it.
+ */
+static void setup_snapshots_and_messages(void *unused)
+{
+	char response[1024];
+	struct host_cmd_handler_args read_args =
+		BUILD_HOST_COMMAND_RESPONSE(EC_CMD_CONSOLE_READ, 0, response);
+
+	/* Set first snapshot before first message */
+	zassert_equal(EC_RES_SUCCESS, ec_cmd_console_snapshot(NULL));
+	cputs(CC_COMMAND, msg1);
+
+	/* Read everything from buffer */
+	do {
+		/* Clear response size before executing command */
+		read_args.response_size = 0;
+		zassert_equal(EC_RES_SUCCESS, host_command_process(&read_args),
+			      NULL);
+	} while (read_args.response_size != 0);
+
+	/* Set second snapshot after first message */
+	zassert_equal(EC_RES_SUCCESS, ec_cmd_console_snapshot(NULL));
+	cputs(CC_COMMAND, msg2);
+}
+
+/**
+ * Test if read next variant of console read host command is working. ver
+ * argument allows to change version of command. In case of version 1, parameter
+ * with sub command is provided.
+ */
+static void test_uart_hc_read_next(int ver)
+{
+	/* Should be able to read whole buffer in one command */
+	char response[CONFIG_PLATFORM_EC_HOSTCMD_CONSOLE_BUF_SIZE + 1];
+	struct ec_params_console_read_v1 params;
+	struct host_cmd_handler_args read_args =
+		BUILD_HOST_COMMAND_RESPONSE(EC_CMD_CONSOLE_READ, ver, response);
+	char *msg1_start;
+	char *msg2_start;
+	char *msg3_start;
+
+	/* Set up host command parameters */
+	if (ver == 1) {
+		read_args.params = &params;
+		read_args.params_size = sizeof(params);
+		params.subcmd = CONSOLE_READ_NEXT;
+	}
+
+	read_args.response_size = 0;
+	zassert_equal(EC_RES_SUCCESS, host_command_process(&read_args));
+	zassert_equal('\0', response[read_args.response_size],
+		      "Last byte of response is not '\\0' (got 0x%x)",
+		      response[read_args.response_size]);
+
+	/*
+	 * Whole buffer until snapshot should be in response, check if it ends
+	 * with message 1 which should start at the end of response excluding
+	 * NULL char.
+	 */
+	msg1_start = response + read_args.response_size - 1 - MSG_LEN(msg1);
+	zassert_mem_equal(msg1, msg1_start, MSG_LEN(msg1),
+			  "expected \"%s\", got \"%.*s\"", msg1, MSG_LEN(msg1),
+			  msg1_start);
+
+	/* Set new snapshot which should include message 2 */
+	zassert_equal(EC_RES_SUCCESS, ec_cmd_console_snapshot(NULL));
+
+	read_args.response_size = 0;
+	zassert_equal(EC_RES_SUCCESS, host_command_process(&read_args));
+	zassert_equal('\0', response[read_args.response_size],
+		      "Last byte of response is not '\\0' (got 0x%x)",
+		      response[read_args.response_size]);
+
+	/*
+	 * Whole buffer should be in response, check if it ends with both
+	 * messages. Message 2 should start at the end of response excluding
+	 * NULL char.
+	 */
+	msg2_start = response + read_args.response_size - 1 - MSG_LEN(msg2);
+	msg1_start = msg2_start - MSG_LEN(msg1);
+	zassert_mem_equal(msg2, msg2_start, MSG_LEN(msg2),
+			  "expected \"%s\", got \"%.*s\"", msg2, MSG_LEN(msg2),
+			  msg2_start);
+	zassert_mem_equal(msg1, msg1_start, MSG_LEN(msg1),
+			  "expected \"%s\", got \"%.*s\"", msg1, MSG_LEN(msg1),
+			  msg1_start);
+
+	/* Append third message */
+	cputs(CC_COMMAND, msg3);
+
+	/* Check read next without new snapshot, no data should be read */
+	read_args.response_size = 0;
+	zassert_equal(EC_RES_SUCCESS, host_command_process(&read_args));
+	zassert_equal(0, read_args.response_size,
+		      "expected message length 0, got %d",
+		      read_args.response_size);
+
+	/* Set new snapshot which should include message 3 */
+	zassert_equal(EC_RES_SUCCESS, ec_cmd_console_snapshot(NULL));
+
+	read_args.response_size = 0;
+	zassert_equal(EC_RES_SUCCESS, host_command_process(&read_args));
+	zassert_equal('\0', response[read_args.response_size],
+		      "Last byte of response is not '\\0' (got 0x%x)",
+		      response[read_args.response_size]);
+
+	msg3_start = response + read_args.response_size - 1 - MSG_LEN(msg3);
+	msg2_start = msg3_start - MSG_LEN(msg2);
+	msg1_start = msg2_start - MSG_LEN(msg1);
+	zassert_mem_equal(msg3, msg3_start, MSG_LEN(msg3),
+			  "expected \"%s\", got \"%.*s\"", msg3, MSG_LEN(msg3),
+			  msg3_start);
+	zassert_mem_equal(msg2, msg2_start, MSG_LEN(msg2),
+			  "expected \"%s\", got \"%.*s\"", msg2, MSG_LEN(msg2),
+			  msg2_start);
+	zassert_mem_equal(msg1, msg1_start, MSG_LEN(msg1),
+			  "expected \"%s\", got \"%.*s\"", msg1, MSG_LEN(msg1),
+			  msg1_start);
+}
+
+ZTEST_USER(uart_hostcmd, test_uart_hc_read_next_v0)
+{
+	test_uart_hc_read_next(0);
+}
+
+ZTEST_USER(uart_hostcmd, test_uart_hc_read_next_v1)
+{
+	test_uart_hc_read_next(1);
+}
+
+/** Test if read recent variant of console read host command is working */
+ZTEST_USER(uart_hostcmd, test_uart_hc_read_recent_v1)
+{
+	/* Should be able to read whole buffer in one command */
+	char response[CONFIG_PLATFORM_EC_HOSTCMD_CONSOLE_BUF_SIZE + 1];
+	struct ec_params_console_read_v1 params;
+	struct host_cmd_handler_args read_args =
+		BUILD_HOST_COMMAND(EC_CMD_CONSOLE_READ, 1, response, params);
+
+	params.subcmd = CONSOLE_READ_RECENT;
+
+	/* Only message 1 which is between two last snapshots should be read */
+	read_args.response_size = 0;
+	zassert_equal(EC_RES_SUCCESS, host_command_process(&read_args));
+	zassert_equal('\0', response[read_args.response_size],
+		      "Last byte of response is not '\\0' (got 0x%x)",
+		      response[read_args.response_size]);
+	/* Account additional NULL char at the end */
+	zassert_equal(MSG_LEN(msg1) + 1, read_args.response_size,
+		      "expected message length %d, got %d", MSG_LEN(msg1) + 1,
+		      read_args.response_size);
+	zassert_mem_equal(msg1, response, MSG_LEN(msg1),
+			  "expected \"%s\", got \"%.*s\"", msg1, MSG_LEN(msg1),
+			  response);
+
+	/* Set new snapshot after second message */
+	zassert_equal(EC_RES_SUCCESS, ec_cmd_console_snapshot(NULL));
+
+	/* Only message between two last snapshots should be read */
+	read_args.response_size = 0;
+	zassert_equal(EC_RES_SUCCESS, host_command_process(&read_args));
+	zassert_equal('\0', response[read_args.response_size],
+		      "Last byte of response is not '\\0' (got 0x%x)",
+		      response[read_args.response_size]);
+	/* Account additional NULL char at the end */
+	zassert_equal(MSG_LEN(msg2) + 1, read_args.response_size,
+		      "expected message length %d, got %d", MSG_LEN(msg2) + 1,
+		      read_args.response_size);
+	zassert_mem_equal(msg2, response, MSG_LEN(msg2),
+			  "expected \"%s\", got \"%.*s\"", msg2, MSG_LEN(msg2),
+			  response);
+
+	/* Append third message */
+	cputs(CC_COMMAND, msg3);
+
+	/* Check that message is not read without setting snapshot */
+	read_args.response_size = 0;
+	zassert_equal(EC_RES_SUCCESS, host_command_process(&read_args));
+	zassert_equal(0, read_args.response_size,
+		      "expected message length 0, got %d",
+		      read_args.response_size);
+
+	/* Set new snapshot */
+	zassert_equal(EC_RES_SUCCESS, ec_cmd_console_snapshot(NULL));
+
+	/* This time only third message should be read */
+	read_args.response_size = 0;
+	zassert_equal(EC_RES_SUCCESS, host_command_process(&read_args));
+	zassert_equal('\0', response[read_args.response_size],
+		      "Last byte of response is not '\\0' (got 0x%x)",
+		      response[read_args.response_size]);
+	/* Account additional NULL char at the end */
+	zassert_equal(MSG_LEN(msg3) + 1, read_args.response_size,
+		      "expected message length %d, got %d", MSG_LEN(msg3) + 1,
+		      read_args.response_size);
+	zassert_mem_equal(msg3, response, MSG_LEN(msg3),
+			  "expected \"%s\", got \"%.*s\"", msg3, MSG_LEN(msg3),
+			  response);
+}
+
+ZTEST_SUITE(uart_hostcmd, drivers_predicate_post_main, NULL,
+	    setup_snapshots_and_messages, NULL, NULL);
diff --git a/zephyr/test/drivers/default/src/usb_mux.c b/zephyr/test/drivers/default/src/usb_mux.c
new file mode 100644
index 0000000000..cad47c75a7
--- /dev/null
+++ b/zephyr/test/drivers/default/src/usb_mux.c
@@ -0,0 +1,981 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "ec_commands.h"
+#include "ec_tasks.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "i2c.h"
+#include "task.h"
+#include "tcpm/ps8xxx_public.h"
+#include "tcpm/tcpci.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "usb_mux.h"
+#include "usb_prl_sm.h"
+#include "usb_tc_sm.h"
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/fff.h>
+#include <zephyr/kernel.h>
+#include <zephyr/shell/shell.h>
+#include <zephyr/shell/shell_uart.h>
+#include <zephyr/ztest.h>
+
+/** Copy of original usb_muxes[USB_PORT_C1] */
+static struct usb_mux_chain usb_mux_c1;
+static struct usb_mux *usbc1_virtual_usb_mux;
+
+/** Number of usb mux proxies in chain */
+#define NUM_OF_PROXY 3
+/** Number of usb mux proxies in chain that CAN_IDLE */
+#define NUM_OF_PROXY_CAN_IDLE 1
+
+/** Pointers to original usb muxes chain of port c1 */
+const struct usb_mux *org_mux[NUM_OF_PROXY];
+
+/** Proxy function which check calls from usb_mux framework to driver */
+FAKE_VALUE_FUNC(int, proxy_init, const struct usb_mux *);
+static int proxy_init_custom(const struct usb_mux *me)
+{
+	int i = me->i2c_addr_flags;
+	int ec = EC_SUCCESS;
+
+	zassert_true(i < NUM_OF_PROXY, "Proxy called for non proxy usb_mux");
+
+	if (org_mux[i] != NULL && org_mux[i]->driver->init != NULL) {
+		ec = org_mux[i]->driver->init(org_mux[i]);
+	}
+
+	if (task_get_current() == TASK_ID_TEST_RUNNER) {
+		RETURN_FAKE_RESULT(proxy_init);
+	}
+
+	/* Discard this call if made from different thread */
+	proxy_init_fake.call_count--;
+
+	return ec;
+}
+
+/** Proxy function which check calls from usb_mux framework to driver */
+FAKE_VALUE_FUNC(int, proxy_set, const struct usb_mux *, mux_state_t, bool *);
+static int proxy_set_custom(const struct usb_mux *me, mux_state_t mux_state,
+			    bool *ack_required)
+{
+	int i = me->i2c_addr_flags;
+	int ec = EC_SUCCESS;
+
+	zassert_true(i < NUM_OF_PROXY, "Proxy called for non proxy usb_mux");
+
+	if (org_mux[i] != NULL && org_mux[i]->driver->set != NULL) {
+		ec = org_mux[i]->driver->set(org_mux[i], mux_state,
+					     ack_required);
+		/* Disable waiting for ACK in tests */
+		*ack_required = false;
+	}
+
+	if (task_get_current() == TASK_ID_TEST_RUNNER) {
+		RETURN_FAKE_RESULT(proxy_set);
+	}
+
+	/* Discard this call if made from different thread */
+	proxy_set_fake.call_count--;
+
+	return ec;
+}
+
+/** Proxy function which check calls from usb_mux framework to driver */
+FAKE_VALUE_FUNC(int, proxy_get, const struct usb_mux *, mux_state_t *);
+/** Sequence of mux_state values returned by proxy_get function */
+static mux_state_t proxy_get_mux_state_seq[NUM_OF_PROXY];
+/** Index of next mux_state to return from proxy_get_function */
+static int proxy_get_mux_state_seq_idx;
+/** Set all mux_state in sequence to the same state value */
+static void set_proxy_get_mux_state_seq(mux_state_t state)
+{
+	proxy_get_mux_state_seq_idx = 0;
+	for (int i = 0; i < NUM_OF_PROXY; i++) {
+		proxy_get_mux_state_seq[i] = state;
+	}
+}
+
+static int proxy_get_custom(const struct usb_mux *me, mux_state_t *mux_state)
+{
+	int i = me->i2c_addr_flags;
+	int ec = EC_SUCCESS;
+
+	zassert_true(i < NUM_OF_PROXY, "Proxy called for non proxy usb_mux");
+
+	if (org_mux[i] != NULL && org_mux[i]->driver->get != NULL) {
+		ec = org_mux[i]->driver->get(org_mux[i], mux_state);
+	}
+
+	if (task_get_current() == TASK_ID_TEST_RUNNER) {
+		zassert_true(proxy_get_mux_state_seq_idx < NUM_OF_PROXY,
+			     "%s called too many times without resetting "
+			     "mux_state_seq",
+			     __func__);
+		*mux_state =
+			proxy_get_mux_state_seq[proxy_get_mux_state_seq_idx];
+		proxy_get_mux_state_seq_idx++;
+		RETURN_FAKE_RESULT(proxy_get);
+	}
+
+	/* Discard this call if made from different thread */
+	proxy_get_fake.call_count--;
+
+	return ec;
+}
+
+/** Proxy function which check calls from usb_mux framework to driver */
+FAKE_VALUE_FUNC(int, proxy_enter_low_power_mode, const struct usb_mux *);
+static int proxy_enter_low_power_mode_custom(const struct usb_mux *me)
+{
+	int i = me->i2c_addr_flags;
+	int ec = EC_SUCCESS;
+
+	zassert_true(i < NUM_OF_PROXY, "Proxy called for non proxy usb_mux");
+
+	if (org_mux[i] != NULL &&
+	    org_mux[i]->driver->enter_low_power_mode != NULL) {
+		ec = org_mux[i]->driver->enter_low_power_mode(org_mux[i]);
+	}
+
+	if (task_get_current() == TASK_ID_TEST_RUNNER) {
+		RETURN_FAKE_RESULT(proxy_enter_low_power_mode);
+	}
+
+	/* Discard this call if made from different thread */
+	proxy_enter_low_power_mode_fake.call_count--;
+
+	return ec;
+}
+
+/** Proxy function which check calls from usb_mux framework to driver */
+FAKE_VALUE_FUNC(int, proxy_chipset_reset, const struct usb_mux *);
+static int proxy_chipset_reset_custom(const struct usb_mux *me)
+{
+	int i = me->i2c_addr_flags;
+	int ec = EC_SUCCESS;
+
+	zassert_true(i < NUM_OF_PROXY, "Proxy called for non proxy usb_mux");
+
+	if (org_mux[i] != NULL && org_mux[i]->driver->chipset_reset != NULL) {
+		ec = org_mux[i]->driver->chipset_reset(org_mux[i]);
+	}
+
+	if (task_get_current() == TASK_ID_TEST_RUNNER) {
+		RETURN_FAKE_RESULT(proxy_chipset_reset);
+	}
+
+	/* Discard this call if made from different thread */
+	proxy_chipset_reset_fake.call_count--;
+
+	return ec;
+}
+
+/** Proxy function which check calls from usb_mux framework to driver */
+FAKE_VALUE_FUNC(int, proxy_set_idle_mode, const struct usb_mux *, bool);
+static int proxy_set_idle_mode_custom(const struct usb_mux *me, bool idle)
+{
+	int i = me->i2c_addr_flags;
+	int ec = EC_SUCCESS;
+
+	zassert_true(i < NUM_OF_PROXY, "Proxy called for non proxy usb_mux");
+
+	if (org_mux[i] != NULL && org_mux[i]->driver->set_idle_mode != NULL) {
+		ec = org_mux[i]->driver->set_idle_mode(org_mux[i], idle);
+	}
+
+	if (task_get_current() == TASK_ID_TEST_RUNNER) {
+		RETURN_FAKE_RESULT(proxy_set_idle_mode);
+	}
+
+	/* Discard this call if made from different thread */
+	proxy_set_idle_mode_fake.call_count--;
+
+	return ec;
+}
+
+/** Proxy function for fw update capability */
+static bool proxy_fw_update_cap(void)
+{
+	return true;
+}
+
+/** Proxy function which check calls from usb_mux framework to driver */
+FAKE_VOID_FUNC(proxy_hpd_update, const struct usb_mux *, mux_state_t, bool *);
+static void proxy_hpd_update_custom(const struct usb_mux *me,
+				    mux_state_t mux_state, bool *ack_required)
+{
+	int i = me->i2c_addr_flags;
+
+	zassert_true(i < NUM_OF_PROXY, "Proxy called for non proxy usb_mux");
+
+	if (org_mux[i] != NULL && org_mux[i]->hpd_update != NULL) {
+		org_mux[i]->hpd_update(org_mux[i], mux_state, ack_required);
+		/* Disable waiting for ACK in tests */
+		*ack_required = false;
+	}
+
+	if (task_get_current() != TASK_ID_TEST_RUNNER) {
+		/* Discard this call if made from different thread */
+		proxy_hpd_update_fake.call_count--;
+	}
+}
+
+/** Usb mux driver with proxy functions */
+const struct usb_mux_driver proxy_usb_mux = {
+	.init = &proxy_init,
+	.set = &proxy_set,
+	.get = &proxy_get,
+	.enter_low_power_mode = &proxy_enter_low_power_mode,
+	.chipset_reset = &proxy_chipset_reset,
+	.set_idle_mode = &proxy_set_idle_mode,
+	.is_retimer_fw_update_capable = &proxy_fw_update_cap,
+};
+
+/** Mock function used in init test */
+FAKE_VALUE_FUNC(int, mock_board_init, const struct usb_mux *);
+static int mock_board_init_custom(const struct usb_mux *me)
+{
+	if (task_get_current() == TASK_ID_TEST_RUNNER) {
+		RETURN_FAKE_RESULT(mock_board_init);
+	}
+
+	/* Discard this call if made from different thread */
+	mock_board_init_fake.call_count--;
+
+	return EC_SUCCESS;
+}
+
+/** Mock function used in set test */
+FAKE_VALUE_FUNC(int, mock_board_set, const struct usb_mux *, mux_state_t);
+static int mock_board_set_custom(const struct usb_mux *me,
+				 mux_state_t mux_state)
+{
+	if (task_get_current() == TASK_ID_TEST_RUNNER) {
+		RETURN_FAKE_RESULT(mock_board_set);
+	}
+
+	/* Discard this call if made from different thread */
+	mock_board_set_fake.call_count--;
+
+	return EC_SUCCESS;
+}
+
+/**
+ * Reset state of all fake functions, setup custom fake functions and set
+ * default return value to EC_SUCCESS (all functions which has return value)
+ */
+static void reset_proxy_fakes(void)
+{
+	RESET_FAKE(proxy_init);
+	RESET_FAKE(proxy_set);
+	RESET_FAKE(proxy_get);
+	RESET_FAKE(proxy_enter_low_power_mode);
+	RESET_FAKE(proxy_chipset_reset);
+	RESET_FAKE(proxy_set_idle_mode);
+	RESET_FAKE(proxy_hpd_update);
+	RESET_FAKE(mock_board_init);
+	RESET_FAKE(mock_board_set);
+
+	/* Setup proxy functions */
+	proxy_init_fake.custom_fake = proxy_init_custom;
+	proxy_set_fake.custom_fake = proxy_set_custom;
+	proxy_get_fake.custom_fake = proxy_get_custom;
+	proxy_enter_low_power_mode_fake.custom_fake =
+		proxy_enter_low_power_mode_custom;
+	proxy_chipset_reset_fake.custom_fake = proxy_chipset_reset_custom;
+	proxy_set_idle_mode_fake.custom_fake = proxy_set_idle_mode_custom;
+	proxy_hpd_update_fake.custom_fake = proxy_hpd_update_custom;
+	mock_board_init_fake.custom_fake = mock_board_init_custom;
+	mock_board_set_fake.custom_fake = mock_board_set_custom;
+
+	/* Set default return value */
+	proxy_init_fake.return_val = EC_SUCCESS;
+	proxy_set_fake.return_val = EC_SUCCESS;
+	proxy_get_fake.return_val = EC_SUCCESS;
+	proxy_enter_low_power_mode_fake.return_val = EC_SUCCESS;
+	proxy_chipset_reset_fake.return_val = EC_SUCCESS;
+	proxy_set_idle_mode_fake.return_val = EC_SUCCESS;
+	mock_board_init_fake.return_val = EC_SUCCESS;
+	mock_board_set_fake.return_val = EC_SUCCESS;
+}
+
+/** Chain of 3 proxy usb muxes */
+struct usb_mux proxy_mux_2 = {
+	.usb_port = USBC_PORT_C1,
+	.driver = &proxy_usb_mux,
+	.i2c_addr_flags = 2,
+	.hpd_update = &proxy_hpd_update,
+};
+
+struct usb_mux_chain proxy_chain_2 = {
+	.mux = &proxy_mux_2,
+};
+
+struct usb_mux proxy_mux_1 = {
+	.usb_port = USBC_PORT_C1,
+	.driver = &proxy_usb_mux,
+	.i2c_addr_flags = 1,
+	.hpd_update = &proxy_hpd_update,
+};
+
+struct usb_mux_chain proxy_chain_1 = {
+	.mux = &proxy_mux_1,
+	.next = &proxy_chain_2,
+};
+
+struct usb_mux proxy_mux_0 = {
+	.usb_port = USBC_PORT_C1,
+	.driver = &proxy_usb_mux,
+	.i2c_addr_flags = 0,
+	.hpd_update = &proxy_hpd_update,
+};
+
+struct usb_mux_chain proxy_chain_0 = {
+	.mux = &proxy_mux_0,
+	.next = &proxy_chain_1,
+};
+
+static void find_virtual_mux(void)
+{
+	const struct usb_mux_chain *mux_chain;
+
+	mux_chain = &usb_muxes[1];
+	usbc1_virtual_usb_mux = NULL;
+	while (mux_chain) {
+		if (mux_chain->mux &&
+		    mux_chain->mux->driver == &virtual_usb_mux_driver) {
+			usbc1_virtual_usb_mux =
+				(struct usb_mux *)mux_chain->mux;
+			break;
+		}
+		mux_chain = mux_chain->next;
+	}
+
+	__ASSERT(usbc1_virtual_usb_mux,
+		 "USB-C port 1 must contain a virtual mux");
+}
+
+/** Setup first 3 usb muxes of port 1 with proxy */
+static void setup_usb_mux_proxy_chain(void)
+{
+	const struct usb_mux_chain *t;
+	int i;
+
+	memcpy(&usb_mux_c1, &usb_muxes[USBC_PORT_C1],
+	       sizeof(struct usb_mux_chain));
+	memcpy(&usb_muxes[USBC_PORT_C1], &proxy_chain_0,
+	       sizeof(struct usb_mux_chain));
+
+	/*
+	 * Setup org_mux array to point real driver which should be called by
+	 * each proxy
+	 */
+	t = &usb_mux_c1;
+	for (i = 0; i < NUM_OF_PROXY; i++) {
+		if (t != NULL) {
+			org_mux[i] = t->mux;
+			t = t->next;
+		} else {
+			org_mux[i] = NULL;
+		}
+	}
+
+	if (t != NULL) {
+		proxy_chain_2.next = t;
+	} else {
+		proxy_chain_2.next = NULL;
+	}
+}
+
+/** Restore original usb_mux chain without proxy */
+static void restore_usb_mux_chain(void)
+{
+	memcpy(&usb_muxes[USBC_PORT_C1], &usb_mux_c1,
+	       sizeof(struct usb_mux_chain));
+
+	/* Reset flags to default */
+	proxy_mux_0.flags = 0;
+	proxy_mux_1.flags = 0;
+	proxy_mux_2.flags = 0;
+}
+
+/**
+ * Check if given proxy function was called num times and if first argument was
+ * pointer to the right proxy chain element. First argument is
+ * const struct usb_mux * for all struct usb_mux_driver callbacks.
+ */
+#define CHECK_PROXY_FAKE_CALL_CNT(proxy, num)                                \
+	do {                                                                 \
+		zassert_equal(num, proxy##_fake.call_count, "%d != %d", num, \
+			      proxy##_fake.call_count);                      \
+		if (num >= 1) {                                              \
+			zassert_equal(usb_muxes[USBC_PORT_C1].mux,           \
+				      proxy##_fake.arg0_history[0], NULL);   \
+		}                                                            \
+		if (num >= 2) {                                              \
+			zassert_equal(proxy_chain_1.mux,                     \
+				      proxy##_fake.arg0_history[1], NULL);   \
+		}                                                            \
+		if (num >= 3) {                                              \
+			zassert_equal(proxy_chain_2.mux,                     \
+				      proxy##_fake.arg0_history[2], NULL);   \
+		}                                                            \
+	} while (0)
+
+/**
+ * Do the same thing as CHECK_PROXY_FAKE_CALL_CNT and check if second argument
+ * was the same as given state. hpd_update and set callback have mux_state_t
+ * as second argument.
+ */
+#define CHECK_PROXY_FAKE_CALL_CNT_MUX_STATE(proxy, num, state)             \
+	do {                                                               \
+		CHECK_PROXY_FAKE_CALL_CNT(proxy, num);                     \
+		if (num >= 1) {                                            \
+			zassert_equal(state, proxy##_fake.arg1_history[0], \
+				      "0x%x != 0x%x", state,               \
+				      proxy##_fake.arg1_history[0]);       \
+		}                                                          \
+		if (num >= 2) {                                            \
+			zassert_equal(state, proxy##_fake.arg1_history[1], \
+				      "0x%x != 0x%x", state,               \
+				      proxy##_fake.arg1_history[1]);       \
+		}                                                          \
+		if (num >= 3) {                                            \
+			zassert_equal(state, proxy##_fake.arg1_history[2], \
+				      "0x%x != 0x%x", state,               \
+				      proxy##_fake.arg1_history[2]);       \
+		}                                                          \
+	} while (0)
+
+/** Test usb_mux init */
+ZTEST(usb_uninit_mux, test_usb_mux_init)
+{
+	int fail_on_2nd_ret[] = { EC_SUCCESS, EC_ERROR_NOT_POWERED };
+
+	/* Set AP to normal state to init BB retimer */
+	test_set_chipset_to_s0();
+
+	/* Test successful initialisation */
+	usb_mux_init(USBC_PORT_C1);
+	CHECK_PROXY_FAKE_CALL_CNT(proxy_init, NUM_OF_PROXY);
+
+	/*
+	 * Test failed initialisation. Muxes that are in chain after
+	 * the one which fails shouldn't be called
+	 */
+	reset_proxy_fakes();
+	SET_RETURN_SEQ(proxy_init, fail_on_2nd_ret, 2);
+	usb_mux_init(USBC_PORT_C1);
+	CHECK_PROXY_FAKE_CALL_CNT(proxy_init, 2);
+
+	/* Test board init callback */
+	proxy_mux_1.board_init = &mock_board_init;
+	reset_proxy_fakes();
+	usb_mux_init(USBC_PORT_C1);
+	CHECK_PROXY_FAKE_CALL_CNT(proxy_init, NUM_OF_PROXY);
+	/* Check if board_init was called for proxy 1 */
+	zassert_equal(1, mock_board_init_fake.call_count);
+	zassert_equal(proxy_chain_1.mux, mock_board_init_fake.arg0_history[0]);
+
+	proxy_mux_1.board_init = NULL;
+}
+
+/** Test usb_mux setting mux mode */
+ZTEST(usb_uninit_mux, test_usb_mux_set)
+{
+	int fail_on_2nd_ret[] = { EC_SUCCESS, EC_ERROR_UNKNOWN };
+	mux_state_t exp_mode;
+
+	/* Set flag for usb mux 1 to disable polarity setting */
+	proxy_mux_1.flags = USB_MUX_FLAG_SET_WITHOUT_FLIP;
+
+	/* Test setting mux mode without polarity inversion */
+	reset_proxy_fakes();
+	exp_mode = USB_PD_MUX_USB_ENABLED;
+	usb_mux_set(USBC_PORT_C1, exp_mode, USB_SWITCH_CONNECT,
+		    0 /* = polarity */);
+	CHECK_PROXY_FAKE_CALL_CNT(proxy_init, NUM_OF_PROXY);
+	/* All muxes should have the same mode */
+	CHECK_PROXY_FAKE_CALL_CNT_MUX_STATE(proxy_set, NUM_OF_PROXY, exp_mode);
+
+	/* Test setting mux mode with polarity inversion */
+	reset_proxy_fakes();
+	exp_mode = USB_PD_MUX_TBT_COMPAT_ENABLED;
+	usb_mux_set(USBC_PORT_C1, exp_mode, USB_SWITCH_CONNECT,
+		    1 /* = polarity */);
+	CHECK_PROXY_FAKE_CALL_CNT(proxy_init, 0);
+	CHECK_PROXY_FAKE_CALL_CNT(proxy_set, NUM_OF_PROXY);
+	/* usb mux 1 shouldn't be set with polarity mode, because of flag */
+	zassert_equal(exp_mode | USB_PD_MUX_POLARITY_INVERTED,
+		      proxy_set_fake.arg1_history[0], NULL);
+	zassert_equal(exp_mode, proxy_set_fake.arg1_history[1]);
+	zassert_equal(exp_mode | USB_PD_MUX_POLARITY_INVERTED,
+		      proxy_set_fake.arg1_history[2], NULL);
+
+	/* Test board set callback */
+	reset_proxy_fakes();
+	proxy_mux_1.board_set = &mock_board_set;
+	usb_mux_set(USBC_PORT_C1, exp_mode, USB_SWITCH_CONNECT,
+		    0 /* = polarity */);
+	CHECK_PROXY_FAKE_CALL_CNT(proxy_init, 0);
+	CHECK_PROXY_FAKE_CALL_CNT_MUX_STATE(proxy_set, NUM_OF_PROXY, exp_mode);
+	/* Check if board_set was called for proxy 1 */
+	zassert_equal(1, mock_board_set_fake.call_count);
+	zassert_equal(proxy_chain_1.mux, mock_board_set_fake.arg0_history[0]);
+	zassert_equal(exp_mode, mock_board_set_fake.arg1_history[0]);
+
+	/* Test set function with error in usb_mux */
+	reset_proxy_fakes();
+	SET_RETURN_SEQ(proxy_set, fail_on_2nd_ret, 2);
+	usb_mux_set(USBC_PORT_C1, exp_mode, USB_SWITCH_CONNECT,
+		    0 /* = polarity */);
+	CHECK_PROXY_FAKE_CALL_CNT(proxy_init, 0);
+	CHECK_PROXY_FAKE_CALL_CNT_MUX_STATE(proxy_set, 2, exp_mode);
+	/* board_set shouldn't be called after fail */
+	zassert_equal(0, mock_board_set_fake.call_count);
+
+	proxy_mux_1.board_set = NULL;
+}
+
+/** Test usb_mux reset in g3 when required flag is set */
+ZTEST(usb_uninit_mux, test_usb_mux_reset_in_g3)
+{
+	mux_state_t exp_mode = USB_PD_MUX_USB_ENABLED;
+
+	/* Test that init is called */
+	reset_proxy_fakes();
+	usb_mux_set(USBC_PORT_C1, exp_mode, USB_SWITCH_CONNECT,
+		    0 /* = polarity */);
+	CHECK_PROXY_FAKE_CALL_CNT(proxy_init, NUM_OF_PROXY);
+	CHECK_PROXY_FAKE_CALL_CNT_MUX_STATE(proxy_set, NUM_OF_PROXY, exp_mode);
+
+	/* Usb muxes of port 1 should stay initialised */
+	proxy_mux_0.flags = 0;
+	hook_notify(HOOK_CHIPSET_HARD_OFF);
+
+	/* Test that init is not called */
+	reset_proxy_fakes();
+	usb_mux_set(USBC_PORT_C1, exp_mode, USB_SWITCH_CONNECT,
+		    0 /* = polarity */);
+	CHECK_PROXY_FAKE_CALL_CNT(proxy_init, 0);
+	CHECK_PROXY_FAKE_CALL_CNT_MUX_STATE(proxy_set, NUM_OF_PROXY, exp_mode);
+}
+
+/** Test usb_mux getting mux mode */
+ZTEST(usb_uninit_mux, test_usb_mux_get)
+{
+	int fail_on_2nd_ret[] = { EC_SUCCESS, EC_ERROR_UNKNOWN };
+	mux_state_t exp_mode, mode;
+
+	/* Test getting mux mode */
+	exp_mode = USB_PD_MUX_USB_ENABLED;
+	set_proxy_get_mux_state_seq(exp_mode);
+	mode = usb_mux_get(USBC_PORT_C1);
+	zassert_equal(exp_mode, mode, "mode is 0x%x (!= 0x%x)", mode, exp_mode);
+	CHECK_PROXY_FAKE_CALL_CNT(proxy_init, NUM_OF_PROXY);
+	CHECK_PROXY_FAKE_CALL_CNT(proxy_get, NUM_OF_PROXY);
+
+	/* Test getting mux mode with inverted polarisation in one mux */
+	reset_proxy_fakes();
+	exp_mode = USB_PD_MUX_TBT_COMPAT_ENABLED;
+	set_proxy_get_mux_state_seq(exp_mode);
+	/* Set polarisation in usb mux 1 state */
+	proxy_get_mux_state_seq[1] |= USB_PD_MUX_POLARITY_INVERTED;
+	exp_mode |= USB_PD_MUX_POLARITY_INVERTED;
+	mode = usb_mux_get(USBC_PORT_C1);
+	zassert_equal(exp_mode, mode, "mode is 0x%x (!= 0x%x)", mode, exp_mode);
+	CHECK_PROXY_FAKE_CALL_CNT(proxy_init, 0);
+	CHECK_PROXY_FAKE_CALL_CNT(proxy_get, NUM_OF_PROXY);
+
+	/* Test get function with error in usb_mux */
+	reset_proxy_fakes();
+	SET_RETURN_SEQ(proxy_get, fail_on_2nd_ret, 2);
+	set_proxy_get_mux_state_seq(USB_PD_MUX_TBT_COMPAT_ENABLED);
+	exp_mode = USB_PD_MUX_NONE;
+	mode = usb_mux_get(USBC_PORT_C1);
+	zassert_equal(exp_mode, mode, "mode is 0x%x (!= 0x%x)", mode, exp_mode);
+	CHECK_PROXY_FAKE_CALL_CNT(proxy_init, 0);
+	CHECK_PROXY_FAKE_CALL_CNT(proxy_get, 2);
+}
+
+/** Test usb_mux entering and exiting low power mode */
+ZTEST(usb_init_mux, test_usb_mux_low_power_mode)
+{
+	int fail_on_2nd_ret[] = { EC_SUCCESS, EC_ERROR_NOT_POWERED };
+	mux_state_t exp_mode, mode;
+
+	/* Test enter to low power mode */
+	exp_mode = USB_PD_MUX_NONE;
+	usb_mux_set(USBC_PORT_C1, exp_mode, USB_SWITCH_DISCONNECT,
+		    0 /* = polarity */);
+	CHECK_PROXY_FAKE_CALL_CNT(proxy_enter_low_power_mode, NUM_OF_PROXY);
+	CHECK_PROXY_FAKE_CALL_CNT_MUX_STATE(proxy_set, NUM_OF_PROXY, exp_mode);
+
+	/* Test that nothing is changed when already in low power mode */
+	reset_proxy_fakes();
+	exp_mode = USB_PD_MUX_NONE;
+	usb_mux_set(USBC_PORT_C1, exp_mode, USB_SWITCH_DISCONNECT,
+		    0 /* = polarity */);
+	CHECK_PROXY_FAKE_CALL_CNT(proxy_enter_low_power_mode, 0);
+	CHECK_PROXY_FAKE_CALL_CNT(proxy_set, 0);
+
+	/* Test that get return USB_PD_MUX_NONE in low power mode */
+	exp_mode = USB_PD_MUX_NONE;
+	mode = usb_mux_get(USBC_PORT_C1);
+	zassert_equal(exp_mode, mode, "mode is 0x%x (!= 0x%x)", mode, exp_mode);
+	CHECK_PROXY_FAKE_CALL_CNT(proxy_get, 0);
+
+	/* Test exiting from low power mode */
+	reset_proxy_fakes();
+	exp_mode = USB_PD_MUX_USB_ENABLED;
+	usb_mux_set(USBC_PORT_C1, exp_mode, USB_SWITCH_CONNECT,
+		    0 /* = polarity */);
+	CHECK_PROXY_FAKE_CALL_CNT(proxy_init, NUM_OF_PROXY);
+	CHECK_PROXY_FAKE_CALL_CNT_MUX_STATE(proxy_set, NUM_OF_PROXY, exp_mode);
+
+	/* Test exiting from lpm, when init end with EC_ERROR_NOT_POWERED */
+	reset_proxy_fakes();
+	SET_RETURN_SEQ(proxy_init, fail_on_2nd_ret, 2);
+	usb_mux_init(USBC_PORT_C1);
+	CHECK_PROXY_FAKE_CALL_CNT(proxy_init, 2);
+
+	reset_proxy_fakes();
+	exp_mode = USB_PD_MUX_USB_ENABLED;
+	usb_mux_set(USBC_PORT_C1, exp_mode, USB_SWITCH_CONNECT,
+		    0 /* = polarity */);
+	CHECK_PROXY_FAKE_CALL_CNT(proxy_init, NUM_OF_PROXY);
+	CHECK_PROXY_FAKE_CALL_CNT_MUX_STATE(proxy_set, NUM_OF_PROXY, exp_mode);
+
+	/* Test enter to low power mode with polarity */
+	reset_proxy_fakes();
+	exp_mode = USB_PD_MUX_NONE;
+	usb_mux_set(USBC_PORT_C1, exp_mode, USB_SWITCH_DISCONNECT,
+		    1 /* = polarity */);
+	CHECK_PROXY_FAKE_CALL_CNT(proxy_enter_low_power_mode, NUM_OF_PROXY);
+	CHECK_PROXY_FAKE_CALL_CNT_MUX_STATE(proxy_set, NUM_OF_PROXY, exp_mode);
+
+	/* Test that nothing is changed on lpm exit error */
+	reset_proxy_fakes();
+	SET_RETURN_SEQ(proxy_init, fail_on_2nd_ret, 2);
+	exp_mode = USB_PD_MUX_USB_ENABLED;
+	usb_mux_set(USBC_PORT_C1, exp_mode, USB_SWITCH_CONNECT,
+		    0 /* = polarity */);
+	CHECK_PROXY_FAKE_CALL_CNT(proxy_init, 2);
+	CHECK_PROXY_FAKE_CALL_CNT(proxy_set, 0);
+}
+
+/** Test usb_mux flip */
+ZTEST(usb_uninit_mux, test_usb_mux_flip)
+{
+	mux_state_t exp_mode;
+
+	/* Set flag for usb mux 1 to disable polarity setting */
+	proxy_mux_1.flags = USB_MUX_FLAG_SET_WITHOUT_FLIP;
+
+	/* Test flip port without polarity inverted */
+	exp_mode = USB_PD_MUX_USB_ENABLED;
+	set_proxy_get_mux_state_seq(exp_mode);
+	usb_mux_flip(USBC_PORT_C1);
+	CHECK_PROXY_FAKE_CALL_CNT(proxy_init, NUM_OF_PROXY);
+	CHECK_PROXY_FAKE_CALL_CNT(proxy_get, NUM_OF_PROXY);
+	CHECK_PROXY_FAKE_CALL_CNT(proxy_set, NUM_OF_PROXY);
+	/* usb mux 1 shouldn't be set with polarity mode, because of flag */
+	zassert_equal(exp_mode | USB_PD_MUX_POLARITY_INVERTED,
+		      proxy_set_fake.arg1_history[0], NULL);
+	zassert_equal(exp_mode, proxy_set_fake.arg1_history[1]);
+	zassert_equal(exp_mode | USB_PD_MUX_POLARITY_INVERTED,
+		      proxy_set_fake.arg1_history[2], NULL);
+
+	/* Test flip port with polarity inverted */
+	reset_proxy_fakes();
+	exp_mode |= USB_PD_MUX_POLARITY_INVERTED;
+	set_proxy_get_mux_state_seq(exp_mode);
+	/* Clear polarity bit from usb mux 1 */
+	proxy_get_mux_state_seq[1] &= ~USB_PD_MUX_POLARITY_INVERTED;
+	exp_mode &= ~USB_PD_MUX_POLARITY_INVERTED;
+	usb_mux_flip(USBC_PORT_C1);
+	CHECK_PROXY_FAKE_CALL_CNT(proxy_init, 0);
+	CHECK_PROXY_FAKE_CALL_CNT(proxy_get, NUM_OF_PROXY);
+	CHECK_PROXY_FAKE_CALL_CNT_MUX_STATE(proxy_set, NUM_OF_PROXY, exp_mode);
+}
+
+ZTEST(usb_uninit_mux, test_usb_mux_hpd_update)
+{
+	mux_state_t exp_mode, mode, virt_mode;
+
+	/* Get current state of virtual usb mux and set mock */
+	usbc1_virtual_usb_mux->driver->get(usbc1_virtual_usb_mux, &virt_mode);
+
+	/* Test no hpd level and no irq */
+	exp_mode = virt_mode;
+	usb_mux_hpd_update(USBC_PORT_C1, exp_mode);
+	/* Check if virtual usb mux mode is updated correctly */
+	usbc1_virtual_usb_mux->driver->get(usbc1_virtual_usb_mux, &mode);
+	zassert_equal(exp_mode, mode, "virtual mux mode is 0x%x (!= 0x%x)",
+		      mode, exp_mode);
+	CHECK_PROXY_FAKE_CALL_CNT(proxy_init, NUM_OF_PROXY);
+	CHECK_PROXY_FAKE_CALL_CNT_MUX_STATE(proxy_hpd_update, NUM_OF_PROXY,
+					    exp_mode);
+
+	/* Test hpd level and irq */
+	reset_proxy_fakes();
+	exp_mode = virt_mode | USB_PD_MUX_HPD_LVL | USB_PD_MUX_HPD_IRQ;
+	usb_mux_hpd_update(USBC_PORT_C1, exp_mode);
+	/* Check if virtual usb mux mode is updated correctly */
+	usbc1_virtual_usb_mux->driver->get(usbc1_virtual_usb_mux, &mode);
+	zassert_equal(exp_mode, mode, "virtual mux mode is 0x%x (!= 0x%x)",
+		      mode, exp_mode);
+	CHECK_PROXY_FAKE_CALL_CNT(proxy_init, 0);
+	CHECK_PROXY_FAKE_CALL_CNT_MUX_STATE(proxy_hpd_update, NUM_OF_PROXY,
+					    exp_mode);
+
+	/* Test no hpd level and irq */
+	reset_proxy_fakes();
+	exp_mode = virt_mode | USB_PD_MUX_HPD_IRQ;
+	usb_mux_hpd_update(USBC_PORT_C1, exp_mode);
+	/* Check if virtual usb mux mode is updated correctly */
+	usbc1_virtual_usb_mux->driver->get(usbc1_virtual_usb_mux, &mode);
+	zassert_equal(exp_mode, mode, "virtual mux mode is 0x%x (!= 0x%x)",
+		      mode, exp_mode);
+	CHECK_PROXY_FAKE_CALL_CNT(proxy_init, 0);
+	CHECK_PROXY_FAKE_CALL_CNT_MUX_STATE(proxy_hpd_update, NUM_OF_PROXY,
+					    exp_mode);
+
+	/* Test hpd level and no irq */
+	reset_proxy_fakes();
+	exp_mode = virt_mode | USB_PD_MUX_HPD_LVL;
+	usb_mux_hpd_update(USBC_PORT_C1, exp_mode);
+	/* Check if virtual usb mux mode is updated correctly */
+	usbc1_virtual_usb_mux->driver->get(usbc1_virtual_usb_mux, &mode);
+	zassert_equal(exp_mode, mode, "virtual mux mode is 0x%x (!= 0x%x)",
+		      mode, exp_mode);
+	CHECK_PROXY_FAKE_CALL_CNT(proxy_init, 0);
+	CHECK_PROXY_FAKE_CALL_CNT_MUX_STATE(proxy_hpd_update, NUM_OF_PROXY,
+					    exp_mode);
+
+	/* Test ps8xxx hpd update */
+	proxy_mux_0.usb_port = 1;
+	proxy_mux_0.driver = &tcpci_tcpm_usb_mux_driver;
+	proxy_mux_0.hpd_update = &ps8xxx_tcpc_update_hpd_status;
+
+	reset_proxy_fakes();
+	exp_mode = virt_mode | USB_PD_MUX_HPD_LVL | USB_PD_MUX_HPD_IRQ;
+	usb_mux_hpd_update(USBC_PORT_C1, exp_mode);
+	/* Check if PS8xxx mux mode is updated correctly */
+	tcpci_tcpm_usb_mux_driver.get(usb_muxes[USBC_PORT_C1].mux, &mode);
+
+	/* Restore proxy chain 0 */
+	proxy_mux_0.usb_port = USBC_PORT_C1;
+	proxy_mux_0.driver = &proxy_usb_mux;
+	proxy_mux_0.hpd_update = &proxy_hpd_update;
+
+	zassert_equal(0, mode, "mux mode is 0x%x (!= 0x%x)", mode, 0);
+}
+
+ZTEST(usb_init_mux, test_usb_mux_fw_update_port_info)
+{
+	int port_info;
+
+	port_info = usb_mux_retimer_fw_update_port_info();
+	zassert_true(port_info & BIT(USBC_PORT_C1),
+		     "fw update for port C1 should be set");
+}
+
+ZTEST(usb_init_mux, test_usb_mux_chipset_reset)
+{
+	/* After this hook chipset reset functions should be called */
+	hook_notify(HOOK_CHIPSET_RESET);
+	CHECK_PROXY_FAKE_CALL_CNT(proxy_chipset_reset, NUM_OF_PROXY);
+}
+
+ZTEST(usb_init_mux, test_usb_mux_set_idle_mode)
+{
+	/* After the SUSPEND hook, set_idle_mode functions should be called */
+	proxy_mux_0.flags |= USB_MUX_FLAG_CAN_IDLE;
+	hook_notify(HOOK_CHIPSET_SUSPEND);
+	CHECK_PROXY_FAKE_CALL_CNT(proxy_set_idle_mode, NUM_OF_PROXY_CAN_IDLE);
+
+	/*
+	 * Other tests will fail if we leave the chipset in SUSPEND,
+	 * so we test the RESUME case here.
+	 */
+	proxy_set_idle_mode_fake.call_count = 0;
+	/* After the RESUME hook, set_idle_mode functions should be called */
+	hook_notify(HOOK_CHIPSET_RESUME);
+	CHECK_PROXY_FAKE_CALL_CNT(proxy_set_idle_mode, NUM_OF_PROXY_CAN_IDLE);
+}
+
+/* Test host command get mux info */
+ZTEST(usb_init_mux, test_usb_mux_hc_mux_info)
+{
+	struct ec_response_usb_pd_mux_info response;
+	struct ec_params_usb_pd_mux_info params;
+	struct host_cmd_handler_args args;
+	mux_state_t exp_mode;
+
+	/* Test invalid port parameter */
+	params.port = 5;
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      ec_cmd_usb_pd_mux_info(NULL, &params, &response));
+
+	/* Set correct port for rest of the test */
+	params.port = USBC_PORT_C1;
+
+	/* Test error on getting mux mode */
+	set_proxy_get_mux_state_seq(USB_PD_MUX_USB_ENABLED);
+	proxy_get_fake.return_val = EC_ERROR_UNKNOWN;
+	zassert_equal(EC_RES_ERROR,
+		      ec_cmd_usb_pd_mux_info(NULL, &params, &response));
+
+	/* Test getting mux mode */
+	reset_proxy_fakes();
+	exp_mode = USB_PD_MUX_USB_ENABLED;
+	set_proxy_get_mux_state_seq(exp_mode);
+	zassert_equal(EC_RES_SUCCESS,
+		      ec_cmd_usb_pd_mux_info(&args, &params, &response));
+	zassert_equal(args.response_size, sizeof(response));
+	zassert_equal(exp_mode, response.flags, "mode is 0x%x (!= 0x%x)",
+		      response.flags, exp_mode);
+	CHECK_PROXY_FAKE_CALL_CNT(proxy_get, NUM_OF_PROXY);
+
+	/* Test clearing HPD IRQ */
+	reset_proxy_fakes();
+	exp_mode = USB_PD_MUX_USB_ENABLED | USB_PD_MUX_HPD_LVL |
+		   USB_PD_MUX_HPD_IRQ;
+	set_proxy_get_mux_state_seq(exp_mode);
+	zassert_equal(EC_RES_SUCCESS,
+		      ec_cmd_usb_pd_mux_info(&args, &params, &response));
+	zassert_equal(args.response_size, sizeof(response));
+	zassert_equal(exp_mode, response.flags, "mode is 0x%x (!= 0x%x)",
+		      response.flags, exp_mode);
+	CHECK_PROXY_FAKE_CALL_CNT(proxy_get, NUM_OF_PROXY);
+	CHECK_PROXY_FAKE_CALL_CNT_MUX_STATE(proxy_hpd_update, NUM_OF_PROXY,
+					    USB_PD_MUX_HPD_LVL);
+}
+
+/** Test typec console command */
+ZTEST(usb_init_mux, test_usb_mux_typec_command)
+{
+	mux_state_t polarity;
+	mux_state_t exp_mode;
+
+	/* Test error on command with no argument */
+	zassert_equal(EC_ERROR_PARAM_COUNT,
+		      shell_execute_cmd(get_ec_shell(), "typec"), NULL);
+
+	/*
+	 * Test success on passing "debug" as first argument. This will enable
+	 * debug prints, but it is not possible to test that in unit test
+	 * without accessing cprints output.
+	 */
+	zassert_equal(EC_SUCCESS,
+		      shell_execute_cmd(get_ec_shell(), "typec debug"), NULL);
+
+	/* Test error on port argument that is not a number */
+	zassert_equal(EC_ERROR_PARAM1,
+		      shell_execute_cmd(get_ec_shell(), "typec test1"), NULL);
+
+	/* Test error on invalid port number */
+	zassert_equal(EC_ERROR_PARAM1,
+		      shell_execute_cmd(get_ec_shell(), "typec 5"), NULL);
+
+	/*
+	 * Test success on correct port number. Command should print mux state
+	 * on console, but it is not possible to check that in unit test.
+	 */
+	set_proxy_get_mux_state_seq(USB_PD_MUX_TBT_COMPAT_ENABLED);
+	zassert_equal(EC_SUCCESS, shell_execute_cmd(get_ec_shell(), "typec 1"),
+		      NULL);
+	CHECK_PROXY_FAKE_CALL_CNT(proxy_get, NUM_OF_PROXY);
+
+	/* Test setting none mode */
+	reset_proxy_fakes();
+	exp_mode = USB_PD_MUX_NONE;
+	zassert_equal(EC_SUCCESS,
+		      shell_execute_cmd(get_ec_shell(), "typec 1 none"), NULL);
+	CHECK_PROXY_FAKE_CALL_CNT_MUX_STATE(proxy_set, NUM_OF_PROXY, exp_mode);
+	/* Mux will enter low power mode */
+	CHECK_PROXY_FAKE_CALL_CNT(proxy_enter_low_power_mode, NUM_OF_PROXY);
+
+	/* Polarity is set based on PD */
+	polarity = polarity_rm_dts(pd_get_polarity(USBC_PORT_C1)) ?
+			   USB_PD_MUX_POLARITY_INVERTED :
+			   0;
+
+	/* Test setting USB mode */
+	reset_proxy_fakes();
+	exp_mode = USB_PD_MUX_USB_ENABLED | polarity;
+	zassert_equal(EC_SUCCESS,
+		      shell_execute_cmd(get_ec_shell(), "typec 1 usb"), NULL);
+	CHECK_PROXY_FAKE_CALL_CNT_MUX_STATE(proxy_set, NUM_OF_PROXY, exp_mode);
+	/* Mux will exit low power mode */
+	CHECK_PROXY_FAKE_CALL_CNT(proxy_init, NUM_OF_PROXY);
+
+	/* Test setting DP mode */
+	reset_proxy_fakes();
+	exp_mode = USB_PD_MUX_DP_ENABLED | polarity;
+	zassert_equal(EC_SUCCESS,
+		      shell_execute_cmd(get_ec_shell(), "typec 1 dp"), NULL);
+	CHECK_PROXY_FAKE_CALL_CNT_MUX_STATE(proxy_set, NUM_OF_PROXY, exp_mode);
+
+	/* Test setting dock mode */
+	reset_proxy_fakes();
+	exp_mode = USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED | polarity;
+	zassert_equal(EC_SUCCESS,
+		      shell_execute_cmd(get_ec_shell(), "typec 1 dock"), NULL);
+	CHECK_PROXY_FAKE_CALL_CNT_MUX_STATE(proxy_set, NUM_OF_PROXY, exp_mode);
+}
+
+/** Setup proxy chain and uninit usb muxes */
+void usb_uninit_mux_before(void *state)
+{
+	ARG_UNUSED(state);
+	find_virtual_mux();
+	setup_usb_mux_proxy_chain();
+	set_test_runner_tid();
+
+	/* Makes sure that usb muxes of port 1 are not init */
+	proxy_mux_0.flags = USB_MUX_FLAG_RESETS_IN_G3;
+	hook_notify(HOOK_CHIPSET_HARD_OFF);
+	reset_proxy_fakes();
+}
+
+void usb_uninit_mux_after(void *state)
+{
+	ARG_UNUSED(state);
+	restore_usb_mux_chain();
+}
+
+/** Setup proxy chain and init usb muxes */
+void usb_init_mux_before(void *state)
+{
+	ARG_UNUSED(state);
+	find_virtual_mux();
+	setup_usb_mux_proxy_chain();
+	set_test_runner_tid();
+
+	/* Makes sure that usb muxes of port 1 are init */
+	usb_mux_init(USBC_PORT_C1);
+	reset_proxy_fakes();
+}
+
+void usb_init_mux_after(void *state)
+{
+	ARG_UNUSED(state);
+	restore_usb_mux_chain();
+}
+
+ZTEST_SUITE(usb_uninit_mux, drivers_predicate_post_main, NULL,
+	    usb_uninit_mux_before, usb_uninit_mux_after, NULL);
+
+ZTEST_SUITE(usb_init_mux, drivers_predicate_post_main, NULL,
+	    usb_init_mux_before, usb_init_mux_after, NULL);
diff --git a/zephyr/test/drivers/default/src/util.c b/zephyr/test/drivers/default/src/util.c
new file mode 100644
index 0000000000..ac5aed9736
--- /dev/null
+++ b/zephyr/test/drivers/default/src/util.c
@@ -0,0 +1,97 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "test/drivers/test_state.h"
+#include "util.h"
+
+#include <zephyr/fff.h>
+#include <zephyr/ztest.h>
+
+ZTEST(util, test_reverse)
+{
+	uint8_t input[] = { 0, 1, 2, 3, 4 };
+	uint8_t expected[] = { 4, 3, 2, 1, 0 };
+
+	reverse(input, sizeof(input));
+
+	zassert_mem_equal(input, expected, sizeof(input), NULL);
+}
+
+ZTEST(util, test_parse_offset_size__normal)
+{
+	const char *argv[] = { "cmd", "123", "456" };
+	int argc = ARRAY_SIZE(argv);
+	int offset = 0, size = 0;
+
+	/* shift=1 is the position of the "123" CLI arg */
+	zassert_ok(parse_offset_size(argc, argv, 1, &offset, &size), NULL);
+	zassert_equal(123, offset, NULL);
+	zassert_equal(456, size, NULL);
+}
+
+ZTEST(util, test_parse_offset_size__invalid_param1)
+{
+	const char *argv[] = { "cmd", "xyz" /* <- bad */, "456" };
+	int argc = ARRAY_SIZE(argv);
+	int offset = 0, size = 0;
+
+	/* shift=1 is the position of the "123" CLI arg */
+	zassert_equal(EC_ERROR_PARAM1,
+		      parse_offset_size(argc, argv, 1, &offset, &size), NULL);
+}
+
+ZTEST(util, test_parse_offset_size__invalid_param2)
+{
+	const char *argv[] = { "cmd", "123", "xyz" /* <- bad */ };
+	int argc = ARRAY_SIZE(argv);
+	int offset = 0, size = 0;
+
+	/* shift=1 is the position of the "123" CLI arg */
+	zassert_equal(EC_ERROR_PARAM2,
+		      parse_offset_size(argc, argv, 1, &offset, &size), NULL);
+}
+
+ZTEST(util, test_wait_for_ready)
+{
+	uint32_t reg;
+
+	/* These calls should immediately exit. If not, the test will fail by
+	 * virtue of timing out.
+	 */
+	reg = 1;
+	wait_for_ready(&reg, 0, 1);
+
+	reg = 0;
+	wait_for_ready(&reg, 1, 1);
+}
+
+ZTEST(util, test_binary_from_bits)
+{
+	int input[] = {
+		0,
+		1,
+		0,
+		1,
+	};
+
+	zassert_equal(0xA, binary_from_bits(input, ARRAY_SIZE(input)), NULL);
+	zassert_equal(0, binary_from_bits(NULL, 0), NULL);
+}
+
+ZTEST(util, test_ternary_from_bits)
+{
+	int input[] = {
+		0,
+		1,
+		2,
+		3,
+	};
+
+	/* Base 3 digits: 0*(3^0) + 1*(3^1) + 2*(3^2) + 3*(3^3) = 102 */
+
+	zassert_equal(102, ternary_from_bits(input, ARRAY_SIZE(input)), NULL);
+	zassert_equal(0, ternary_from_bits(NULL, 0), NULL);
+}
+
+ZTEST_SUITE(util, drivers_predicate_post_main, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/drivers/default/src/vboot_hash.c b/zephyr/test/drivers/default/src/vboot_hash.c
new file mode 100644
index 0000000000..101fc2f6dc
--- /dev/null
+++ b/zephyr/test/drivers/default/src/vboot_hash.c
@@ -0,0 +1,94 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+#include "host_command.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+#include <sha256.h>
+
+ZTEST_USER(vboot_hash, test_hostcmd_abort)
+{
+	struct ec_response_vboot_hash response;
+	struct ec_params_vboot_hash start_params = {
+		.cmd = EC_VBOOT_HASH_START,
+		.hash_type = EC_VBOOT_HASH_TYPE_SHA256,
+		.offset = EC_VBOOT_HASH_OFFSET_RO,
+		.size = 0,
+	};
+	struct host_cmd_handler_args start_args;
+	struct ec_params_vboot_hash abort_params = {
+		.cmd = EC_VBOOT_HASH_ABORT,
+	};
+	struct ec_params_vboot_hash get_params = {
+		.cmd = EC_VBOOT_HASH_GET,
+	};
+	struct host_cmd_handler_args get_args;
+
+	/* Start hashing. The command doesn't wait to finish. */
+	zassert_ok(ec_cmd_vboot_hash(&start_args, &start_params, &response));
+	zassert_equal(start_args.response_size, sizeof(response));
+	zassert_equal(response.status, EC_VBOOT_HASH_STATUS_BUSY,
+		      "response.status = %d", response.status);
+
+	/* Abort it immediately */
+	zassert_ok(ec_cmd_vboot_hash(NULL, &abort_params, &response));
+
+	/* Give it a bit time. The abort is being processed in the background */
+	k_msleep(20);
+
+	/* Get the hash result. Should be NONE. */
+	zassert_ok(ec_cmd_vboot_hash(&get_args, &get_params, &response));
+	zassert_equal(get_args.response_size, sizeof(response));
+	zassert_equal(response.status, EC_VBOOT_HASH_STATUS_NONE,
+		      "response.status = %d", response.status);
+}
+
+ZTEST_USER(vboot_hash, test_hostcmd_recalc)
+{
+	struct ec_response_vboot_hash response;
+	struct ec_params_vboot_hash recalc_params = {
+		.cmd = EC_VBOOT_HASH_RECALC,
+		.hash_type = EC_VBOOT_HASH_TYPE_SHA256,
+		.offset = EC_VBOOT_HASH_OFFSET_RO,
+		.size = 0,
+	};
+	struct host_cmd_handler_args recalc_args;
+
+	/* Recalculate the hash. The command waits to finish. */
+	zassert_ok(ec_cmd_vboot_hash(&recalc_args, &recalc_params, &response));
+	zassert_equal(recalc_args.response_size, sizeof(response));
+	zassert_equal(response.status, EC_VBOOT_HASH_STATUS_DONE,
+		      "response.status = %d", response.status);
+	zassert_equal(response.digest_size, SHA256_DIGEST_SIZE,
+		      "response.digest_size = %d", response.digest_size);
+}
+
+ZTEST_USER(vboot_hash, test_hostcmd_hash_arbitrary_size)
+{
+	struct ec_response_vboot_hash response;
+	struct ec_params_vboot_hash recalc_params = {
+		.cmd = EC_VBOOT_HASH_RECALC,
+		.hash_type = EC_VBOOT_HASH_TYPE_SHA256,
+		.offset = 0,
+		/* arbitrary size */
+		.size = 0x12345,
+	};
+	struct host_cmd_handler_args recalc_args;
+
+	/* Recalculate the hash. The command waits to finish. */
+	zassert_ok(ec_cmd_vboot_hash(&recalc_args, &recalc_params, &response),
+		   NULL);
+	zassert_equal(recalc_args.response_size, sizeof(response), NULL);
+	zassert_equal(response.status, EC_VBOOT_HASH_STATUS_DONE,
+		      "response.status = %d", response.status);
+	zassert_equal(response.digest_size, SHA256_DIGEST_SIZE,
+		      "response.digest_size = %d", response.digest_size);
+}
+
+ZTEST_SUITE(vboot_hash, drivers_predicate_post_main, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/drivers/default/src/virtual_battery.c b/zephyr/test/drivers/default/src/virtual_battery.c
new file mode 100644
index 0000000000..e74a816c52
--- /dev/null
+++ b/zephyr/test/drivers/default/src/virtual_battery.c
@@ -0,0 +1,432 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "battery_smart.h"
+#include "ec_commands.h"
+#include "emul/emul_smart_battery.h"
+#include "gpio.h"
+#include "host_command.h"
+#include "test/drivers/test_state.h"
+#include "virtual_battery.h"
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+void copy_memmap_string(uint8_t *dest, int offset, int len);
+
+/* The param buffer has at most 2 msg's (write + read) and 1 byte write len. */
+static uint8_t param_buf[sizeof(struct ec_params_i2c_passthru) +
+			 sizeof(struct ec_params_i2c_passthru_msg) * 2 + 1];
+
+/* The response buffer has at most 32 bytes returned result. */
+static uint8_t response_buf[sizeof(struct ec_response_i2c_passthru) + 32];
+
+static void i2c_passthru_xfer(uint8_t port, uint8_t addr, uint8_t *write_buf,
+			      int write_len, uint8_t **read_buf, int read_len)
+{
+	struct ec_params_i2c_passthru *params =
+		(struct ec_params_i2c_passthru *)&param_buf;
+	struct ec_response_i2c_passthru *response =
+		(struct ec_response_i2c_passthru *)&response_buf;
+	struct ec_params_i2c_passthru_msg *msg = params->msg;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_SIMPLE(EC_CMD_I2C_PASSTHRU, 0);
+	uint8_t *pdata;
+	int size;
+
+	params->port = port;
+	params->num_msgs = (read_len != 0) + (write_len != 0);
+
+	size = sizeof(*params) + params->num_msgs * sizeof(*msg);
+	pdata = (uint8_t *)params + size;
+
+	if (write_len) {
+		msg->addr_flags = addr;
+		msg->len = write_len;
+		memcpy(pdata, write_buf, write_len);
+		msg++;
+	}
+
+	if (read_len) {
+		msg->addr_flags = addr | EC_I2C_FLAG_READ;
+		msg->len = read_len;
+	}
+
+	args.params = params;
+	args.params_size = size + write_len;
+	args.response = response;
+	args.response_max = sizeof(*response) + read_len;
+
+	/* Execute the I2C passthru host command */
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_ok(args.result, NULL);
+	zassert_ok(response->i2c_status, NULL);
+	zassert_equal(args.response_size, sizeof(*response) + read_len, NULL);
+
+	/* Return the data portion */
+	if (read_len)
+		*read_buf = response->data;
+}
+
+static inline void virtual_battery_xfer(uint8_t *write_buf, int write_len,
+					uint8_t **read_buf, int read_len)
+{
+	i2c_passthru_xfer(I2C_PORT_VIRTUAL_BATTERY, VIRTUAL_BATTERY_ADDR_FLAGS,
+			  write_buf, write_len, read_buf, read_len);
+}
+
+static uint16_t virtual_battery_read16(uint8_t command)
+{
+	uint8_t write_buf[1] = { command };
+	uint8_t *read_buf;
+
+	virtual_battery_xfer(write_buf, 1, &read_buf, 2);
+
+	/* Little endian */
+	return ((int)read_buf[1] << 8) | read_buf[0];
+}
+
+static void virtual_battery_write16(uint8_t command, uint16_t data)
+{
+	uint8_t write_buf[3] = { command };
+
+	*((uint16_t *)&write_buf[1]) = data;
+
+	virtual_battery_xfer(write_buf, 3, NULL, 0);
+}
+
+static int virtual_battery_read_str(uint8_t command, char **read_buf,
+				    int read_len)
+{
+	uint8_t write_buf[1] = { command };
+	int len;
+
+	virtual_battery_xfer(write_buf, 1, (uint8_t **)read_buf, read_len);
+
+	/* Battery v2 embeds the strlen in the first byte so shift 1 byte. */
+	len = **read_buf;
+	(*read_buf)++;
+
+	return len;
+}
+
+static void virtual_battery_read_data(uint8_t command, char **read_buf,
+				      int read_len)
+{
+	uint8_t write_buf[1] = { command };
+
+	virtual_battery_xfer(write_buf, 1, (uint8_t **)read_buf, read_len);
+}
+
+#define BATTERY_NODE DT_NODELABEL(battery)
+
+ZTEST_USER(virtual_battery, test_read_regs)
+{
+	const struct emul *emul = EMUL_DT_GET(BATTERY_NODE);
+	struct sbat_emul_bat_data *bat = sbat_emul_get_bat_data(emul);
+	int16_t int16;
+	uint16_t word;
+	int expected;
+	char *str;
+	int len;
+
+	/*
+	 * Iterate all the registers, which issues the I2C passthru host
+	 * command to query the emulated smart battery. Most of the values
+	 * are the same as the emulated battery, but with some exceptions.
+	 */
+	word = virtual_battery_read16(SB_BATTERY_MODE);
+	zassert_equal(bat->mode, word, "%d != %d", bat->mode, word);
+
+	word = virtual_battery_read16(SB_SERIAL_NUMBER);
+	zassert_equal(bat->sn, word, "%d != %d", bat->sn, word);
+
+	word = virtual_battery_read16(SB_VOLTAGE);
+	zassert_equal(bat->volt, word, "%d != %d", bat->volt, word);
+
+	/* The expected value is calculated */
+	expected = 100 * bat->cap / bat->full_cap;
+	word = virtual_battery_read16(SB_RELATIVE_STATE_OF_CHARGE);
+
+	zassert_equal(expected, word, "%d != %d", expected, word);
+
+	word = virtual_battery_read16(SB_TEMPERATURE);
+	zassert_equal(bat->temp, word, "%d != %d", bat->temp, word);
+
+	int16 = virtual_battery_read16(SB_CURRENT);
+	zassert_equal(bat->cur, int16, "%d != %d", bat->cur, int16);
+
+	int16 = virtual_battery_read16(SB_AVERAGE_CURRENT);
+	zassert_equal(bat->avg_cur, int16, "%d != %d", bat->avg_cur, int16);
+
+	/* The virtual battery modifies the return value to make kernel happy */
+	expected = BATTERY_LEVEL_SHUTDOWN;
+	word = virtual_battery_read16(SB_MAX_ERROR);
+	zassert_equal(expected, word, "%d != %d", expected, word);
+
+	word = virtual_battery_read16(SB_FULL_CHARGE_CAPACITY);
+	zassert_equal(bat->full_cap, word, "%d != %d", bat->full_cap, word);
+
+	word = virtual_battery_read16(SB_CYCLE_COUNT);
+	zassert_equal(bat->cycle_count, word, "%d != %d", bat->cycle_count,
+		      word);
+
+	word = virtual_battery_read16(SB_DESIGN_CAPACITY);
+	zassert_equal(bat->design_cap, word, "%d != %d", bat->design_cap, word);
+
+	word = virtual_battery_read16(SB_REMAINING_CAPACITY);
+	zassert_equal(bat->cap, word, "%d != %d", bat->cap, word);
+
+	len = virtual_battery_read_str(SB_MANUFACTURER_NAME, &str,
+				       SB_MAX_STR_SIZE);
+	zassert_equal(bat->mf_name_len, len, "%d != %d", bat->mf_name_len, len);
+	zassert_mem_equal(str, bat->mf_name, bat->mf_name_len, "%s != %s", str,
+			  bat->mf_name);
+
+	len = virtual_battery_read_str(SB_DEVICE_NAME, &str, SB_MAX_STR_SIZE);
+	zassert_equal(bat->dev_name_len, len, "%d != %d", bat->dev_name_len,
+		      len);
+	zassert_mem_equal(str, bat->dev_name, bat->dev_name_len, "%s != %s",
+			  str, bat->dev_name);
+
+	len = virtual_battery_read_str(SB_DEVICE_CHEMISTRY, &str,
+				       SB_MAX_STR_SIZE);
+	zassert_equal(bat->dev_chem_len, len, "%d != %d", bat->dev_chem_len,
+		      len);
+	zassert_mem_equal(str, bat->dev_chem, bat->dev_chem_len, "%s != %s",
+			  str, bat->dev_chem);
+
+	/* Use the API to query the expected value */
+	battery_time_to_full(&expected);
+	word = virtual_battery_read16(SB_AVERAGE_TIME_TO_FULL);
+	zassert_equal(expected, word, "%d != %d", expected, word);
+
+	battery_time_to_empty(&expected);
+	word = virtual_battery_read16(SB_AVERAGE_TIME_TO_EMPTY);
+	zassert_equal(expected, word, "%d != %d", expected, word);
+
+	battery_run_time_to_empty(&expected);
+	word = virtual_battery_read16(SB_RUN_TIME_TO_EMPTY);
+	zassert_equal(expected, word, "%d != %d", expected, word);
+
+	word = virtual_battery_read16(SB_CHARGING_CURRENT);
+	zassert_equal(bat->desired_charg_cur, word, "%d != %d",
+		      bat->desired_charg_cur, word);
+
+	word = virtual_battery_read16(SB_CHARGING_VOLTAGE);
+	zassert_equal(bat->desired_charg_volt, word, "%d != %d",
+		      bat->desired_charg_volt, word);
+
+	word = virtual_battery_read16(SB_MANUFACTURE_DATE);
+	zassert_equal(bat->mf_date, word, "%d != %d", bat->mf_date, word);
+
+	/* Hard-coded return value: v1.1 without PEC */
+	expected = 0x0011;
+	word = virtual_battery_read16(SB_SPECIFICATION_INFO);
+	zassert_equal(expected, word, "%d != %d", expected, word);
+
+	zassert_ok(battery_status(&expected));
+	word = virtual_battery_read16(SB_BATTERY_STATUS);
+	zassert_equal(expected, word, "%d != %d", expected, word);
+
+	zassert_ok(battery_design_voltage(&expected));
+	word = virtual_battery_read16(SB_DESIGN_VOLTAGE);
+	zassert_equal(expected, word, "%d != %d", expected, word);
+
+	virtual_battery_read_data(SB_MANUFACTURER_DATA, &str, bat->mf_data_len);
+	zassert_mem_equal(str, bat->mf_data, bat->mf_data_len, "%s != %s", str,
+			  bat->mf_data);
+
+	/* At present, this command is used nowhere in our codebase. */
+	virtual_battery_read_data(SB_MANUFACTURE_INFO, &str, bat->mf_info_len);
+	zassert_mem_equal(str, bat->mf_info, bat->mf_info_len, "%s != %s", str,
+			  bat->mf_info);
+}
+
+ZTEST_USER(virtual_battery, test_write_mfgacc)
+{
+	struct sbat_emul_bat_data *bat;
+	const struct emul *emul = EMUL_DT_GET(BATTERY_NODE);
+	uint16_t cmd = PARAM_OPERATION_STATUS;
+
+	bat = sbat_emul_get_bat_data(emul);
+
+	/* Write the command to the SB_MANUFACTURER_ACCESS and check */
+	virtual_battery_write16(SB_MANUFACTURER_ACCESS, cmd);
+	zassert_equal(bat->mf_access, cmd, "%d != %d", bat->mf_access, cmd);
+}
+
+ZTEST(virtual_battery, test_read_nothing_from_host_memmap)
+{
+	const uint8_t expected[EC_MEMMAP_TEXT_MAX] = { 0 };
+	uint8_t buffer[EC_MEMMAP_TEXT_MAX] = { 0 };
+	uint8_t *memmap_ptr = host_get_memmap(EC_MEMMAP_BATT_MFGR);
+
+	zassert_not_null(memmap_ptr);
+	memcpy(memmap_ptr, "TEST", 5);
+	copy_memmap_string(buffer, EC_MEMMAP_BATT_MFGR, 0);
+
+	zassert_mem_equal(expected, buffer, EC_MEMMAP_TEXT_MAX);
+}
+
+ZTEST(virtual_battery, test_read_data_from_host_memmap)
+{
+	uint8_t buffer[EC_MEMMAP_TEXT_MAX] = { 0 };
+	uint8_t *memmap_ptr = host_get_memmap(EC_MEMMAP_BATT_MFGR);
+
+	zassert_not_null(memmap_ptr);
+	memcpy(memmap_ptr, "TEST\0\0\0\0", 8);
+	copy_memmap_string(buffer, EC_MEMMAP_BATT_MFGR, 5);
+
+	zassert_equal(4, buffer[0]);
+	zassert_mem_equal("TEST", buffer + 1, 4);
+}
+
+ZTEST_SUITE(virtual_battery, drivers_predicate_post_main, NULL, NULL, NULL,
+	    NULL);
+
+ZTEST(virtual_battery_direct, test_bad_reg_write)
+{
+	struct ec_response_i2c_passthru resp;
+
+	/* Start with a zero-length write. The state machine is expecting a
+	 * register address to be written, so this will fail.
+	 */
+	zassert_equal(EC_ERROR_INVAL,
+		      virtual_battery_handler(&resp, 0, NULL, 0, 0,
+					      /* write_len = */ 0, NULL));
+
+	zassert_equal(EC_I2C_STATUS_NAK, resp.i2c_status);
+}
+
+ZTEST(virtual_battery_direct, test_aborted_write)
+{
+	struct ec_response_i2c_passthru resp;
+	int error_code;
+
+	/* Arbitrary packet of bytes */
+	const uint8_t packet[] = { 0xAA, 0xBB, 0xCC };
+
+	/* Start with a length 1 write to set a register address. */
+	zassert_ok(virtual_battery_handler(&resp, 0, &error_code, 0, 0,
+					   /* write_len = */ 1, &packet[0]));
+
+	/* Now write two more bytes successfully... */
+	zassert_ok(virtual_battery_handler(&resp, 0, &error_code, 0, 0,
+					   /* write_len = */ 1, &packet[1]));
+	zassert_ok(error_code);
+
+	zassert_ok(virtual_battery_handler(&resp, 0, &error_code, 0, 0,
+					   /* write_len = */ 1, &packet[2]));
+	zassert_ok(error_code);
+
+	/* ...and abruptly write 0 bytes. This will cause an error */
+	zassert_equal(EC_ERROR_INVAL,
+		      virtual_battery_handler(&resp, 0, &error_code, 0, 0,
+					      /* write_len = */ 0, NULL));
+
+	zassert_equal(EC_I2C_STATUS_NAK, resp.i2c_status);
+}
+
+ZTEST(virtual_battery_direct, test_aborted_read)
+{
+	struct ec_response_i2c_passthru resp;
+	int error_code;
+
+	/* Arbitrary packet to set a register plus a buffer to read to */
+	const uint8_t write_packet[] = { SB_MANUFACTURER_NAME };
+	uint8_t read_packet[3] = { 0 };
+
+	/* Start with a length 1 write to set a register address. */
+	zassert_ok(virtual_battery_handler(&resp, 0, &error_code, 0, 0,
+					   /* write_len = */ 1,
+					   &write_packet[0]));
+
+	/* Now read two bytes successfully... */
+	zassert_ok(virtual_battery_handler(&resp, 0, &error_code, 0,
+					   /* read_len = */ 1, 0,
+					   &read_packet[0]));
+	zassert_ok(error_code);
+
+	zassert_ok(virtual_battery_handler(&resp, 0, &error_code, 0,
+					   /* read_len = */ 1, 0,
+					   &read_packet[1]));
+	zassert_ok(error_code);
+
+	/* ...and abruptly read 0 bytes. This will cause an error */
+	zassert_equal(EC_ERROR_INVAL,
+		      virtual_battery_handler(&resp, 0, &error_code, 0,
+					      /* read_len = */ 0, 0,
+					      &read_packet[2]));
+
+	zassert_equal(EC_I2C_STATUS_NAK, resp.i2c_status);
+}
+
+ZTEST(virtual_battery_direct, test_read_bad_reg)
+{
+	struct ec_response_i2c_passthru resp;
+	int error_code;
+
+	/* Try to read from an invalid register */
+	const uint8_t write_packet[] = { 0xFF };
+	uint8_t read_packet[3] = { 0 };
+
+	/* Start with a length 1 write to set a register address. */
+	zassert_ok(virtual_battery_handler(&resp, 0, &error_code, 0, 0,
+					   /* write_len = */ 1,
+					   &write_packet[0]));
+
+	/* Now try to read */
+	zassert_equal(EC_ERROR_INVAL,
+		      virtual_battery_handler(&resp, 0, &error_code, 0,
+					      /* read_len = */ 1, 0,
+					      &read_packet[0]));
+	zassert_equal(EC_ERROR_INVAL, error_code);
+}
+
+#define GPIO_BATT_PRES_ODL_PATH NAMED_GPIOS_GPIO_NODE(ec_batt_pres_odl)
+#define GPIO_BATT_PRES_ODL_PORT DT_GPIO_PIN(GPIO_BATT_PRES_ODL_PATH, gpios)
+
+static int set_battery_present(bool batt_present)
+{
+	const struct device *batt_pres_dev =
+		DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_BATT_PRES_ODL_PATH, gpios));
+
+	return gpio_emul_input_set(batt_pres_dev, GPIO_BATT_PRES_ODL_PORT,
+				   !batt_present);
+}
+
+ZTEST(virtual_battery_direct, test_no_battery)
+{
+	struct ec_response_i2c_passthru resp;
+
+	set_battery_present(false);
+
+	/* Arbitrary packet of bytes */
+	const uint8_t packet[] = { 0xAA, 0xBB, 0xCC };
+
+	/* Attempt a valid write operation, which will fail due to no battery */
+	zassert_equal(EC_ERROR_INVAL,
+		      virtual_battery_handler(&resp, 0, NULL, 0, 0,
+					      /* write_len = */ 1, &packet[0]));
+
+	zassert_equal(EC_I2C_STATUS_NAK, resp.i2c_status);
+}
+
+static void virtual_battery_direct_reset(void *arg)
+{
+	reset_parse_state();
+
+	set_battery_present(true);
+}
+
+/* The virtual_battery_direct suite tests the virtual battery handler directly
+ * without performing I2C ops. This makes it easier to test certain corner-cases
+ */
+ZTEST_SUITE(virtual_battery_direct, drivers_predicate_post_main, NULL,
+	    virtual_battery_direct_reset, virtual_battery_direct_reset, NULL);
diff --git a/zephyr/test/drivers/default/src/vstore.c b/zephyr/test/drivers/default/src/vstore.c
new file mode 100644
index 0000000000..876655f66a
--- /dev/null
+++ b/zephyr/test/drivers/default/src/vstore.c
@@ -0,0 +1,224 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+#include "host_command.h"
+#include "system.h"
+#include "system_fake.h"
+#include "test/drivers/test_state.h"
+#include "vstore.h"
+
+#include <setjmp.h>
+
+#include <zephyr/fff.h>
+#include <zephyr/shell/shell_dummy.h>
+#include <zephyr/ztest.h>
+
+#include <console.h>
+
+ZTEST_SUITE(vstore, drivers_predicate_post_main, NULL, NULL, NULL, NULL);
+
+ZTEST_USER(vstore, test_vstore_info)
+{
+	struct ec_response_vstore_info response;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_RESPONSE(EC_CMD_VSTORE_INFO, 0, response);
+
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_ok(args.result, NULL);
+	zassert_equal(args.response_size, sizeof(response), NULL);
+	zassert_equal(response.slot_count, CONFIG_VSTORE_SLOT_COUNT,
+		      "response.slot_count = %d", response.slot_count);
+	zassert_equal(response.slot_locked, 0, "response.slot_locked = %#x",
+		      response.slot_locked);
+}
+
+ZTEST_USER(vstore, test_vstore_read)
+{
+	struct ec_params_vstore_read params = {
+		.slot = 0,
+	};
+	struct ec_response_vstore_read response;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_VSTORE_READ, 0, response, params);
+	uint8_t expect[EC_VSTORE_SLOT_SIZE] = {}; /* data should start as 0 */
+
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_ok(args.result, NULL);
+	zassert_equal(args.response_size, sizeof(response), NULL);
+	zassert_mem_equal(expect, response.data, EC_VSTORE_SLOT_SIZE,
+			  "response.data did not match");
+}
+
+ZTEST_USER(vstore, test_vstore_read_bad_slot)
+{
+	struct ec_params_vstore_read params = {
+		.slot = CONFIG_VSTORE_SLOT_COUNT,
+	};
+	struct ec_response_vstore_read response;
+
+	zassert_equal(ec_cmd_vstore_read(NULL, &params, &response),
+		      EC_RES_INVALID_PARAM, "Failed to fail on invalid slot %d",
+		      params.slot);
+}
+
+ZTEST_USER(vstore, test_vstore_write_bad_slot)
+{
+	struct ec_params_vstore_write params = {
+		.slot = CONFIG_VSTORE_SLOT_COUNT,
+		.data = {},
+	};
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_PARAMS(EC_CMD_VSTORE_WRITE, 0, params);
+
+	zassert_equal(host_command_process(&args), EC_RES_INVALID_PARAM,
+		      "Failed to fail on invalid slot %d", params.slot);
+}
+
+static void do_vstore_write_read(unsigned int slot)
+{
+	struct ec_params_vstore_write write_params = {
+		.slot = slot,
+		/* .data is set up below */
+	};
+	struct ec_params_vstore_read read_params = {
+		.slot = slot,
+	};
+	struct ec_response_vstore_read read_response;
+	struct host_cmd_handler_args read_args = BUILD_HOST_COMMAND(
+		EC_CMD_VSTORE_READ, 0, read_response, read_params);
+	struct ec_response_vstore_info info_response;
+	struct host_cmd_handler_args info_args = BUILD_HOST_COMMAND_RESPONSE(
+		EC_CMD_VSTORE_INFO, 0, info_response);
+	int i;
+
+	for (i = 0; i < EC_VSTORE_SLOT_SIZE; i++)
+		write_params.data[i] = i + 1;
+
+	/* Write to a slot */
+	zassert_ok(ec_cmd_vstore_write(NULL, &write_params), NULL);
+
+	/* Check that it is now locked */
+	zassert_ok(host_command_process(&info_args), NULL);
+	zassert_ok(info_args.result, NULL);
+	zassert_equal(info_args.response_size, sizeof(info_response), NULL);
+	zassert_equal(info_response.slot_count, CONFIG_VSTORE_SLOT_COUNT,
+		      "response.slot_count = %d", info_response.slot_count);
+	zassert_equal(info_response.slot_locked, 1 << slot,
+		      "response.slot_locked = %#x", info_response.slot_locked);
+
+	/* Read to check data */
+	zassert_ok(host_command_process(&read_args), NULL);
+	zassert_ok(read_args.result, NULL);
+	zassert_equal(read_args.response_size, sizeof(read_response), NULL);
+	zassert_mem_equal(write_params.data, read_response.data,
+			  EC_VSTORE_SLOT_SIZE, "response.data did not match");
+
+	/* Try to write to it again */
+	zassert_equal(ec_cmd_vstore_write(NULL, &write_params),
+		      EC_RES_ACCESS_DENIED,
+		      "Failed to fail on writing locked slot %d",
+		      write_params.slot);
+
+	/* Check that it is still locked after that attempt */
+	zassert_ok(host_command_process(&info_args), NULL);
+	zassert_ok(info_args.result, NULL);
+	zassert_equal(info_args.response_size, sizeof(info_response), NULL);
+	zassert_equal(info_response.slot_count, CONFIG_VSTORE_SLOT_COUNT,
+		      "response.slot_count = %d", info_response.slot_count);
+	zassert_equal(info_response.slot_locked, 1 << slot,
+		      "response.slot_locked = %#x", info_response.slot_locked);
+
+	/* Read to check the data didn't change */
+	zassert_ok(host_command_process(&read_args), NULL);
+	zassert_ok(read_args.result, NULL);
+	zassert_equal(read_args.response_size, sizeof(read_response), NULL);
+	zassert_mem_equal(write_params.data, read_response.data,
+			  EC_VSTORE_SLOT_SIZE, "response.data did not match");
+
+	/* Clear locks and try the write again, this time with zero bytes  */
+	vstore_clear_lock();
+	memset(write_params.data, '\0', EC_VSTORE_SLOT_SIZE);
+	zassert_ok(ec_cmd_vstore_write(NULL, &write_params), NULL);
+
+	/* Check that it is now locked */
+	zassert_ok(host_command_process(&info_args), NULL);
+	zassert_ok(info_args.result, NULL);
+	zassert_equal(info_args.response_size, sizeof(info_response), NULL);
+	zassert_equal(info_response.slot_count, CONFIG_VSTORE_SLOT_COUNT,
+		      "response.slot_count = %d", info_response.slot_count);
+	zassert_equal(info_response.slot_locked, 1 << slot,
+		      "response.slot_locked = %#x", info_response.slot_locked);
+
+	/* Read to check the data changed */
+	zassert_ok(host_command_process(&read_args), NULL);
+	zassert_ok(read_args.result, NULL);
+	zassert_equal(read_args.response_size, sizeof(read_response), NULL);
+	zassert_mem_equal(write_params.data, read_response.data,
+			  EC_VSTORE_SLOT_SIZE, "response.data did not match");
+
+	/* Clear locks to put things into a normal state */
+	vstore_clear_lock();
+}
+
+ZTEST_USER(vstore, test_vstore_write_read)
+{
+	/* Try on two different slots */
+	zassert_true(CONFIG_VSTORE_SLOT_COUNT >= 2,
+		     "Please set CONFIG_VSTORE_SLOT_COUNT to >= 2");
+	do_vstore_write_read(0);
+	do_vstore_write_read(1);
+}
+
+ZTEST_USER(vstore, test_vstore_state)
+{
+	struct ec_params_vstore_write write_params = {
+		.slot = 0,
+		/* .data is set up below */
+	};
+
+	struct ec_params_reboot_ec reboot_params = {
+		.cmd = EC_REBOOT_JUMP_RW,
+	};
+	struct host_cmd_handler_args reboot_args =
+		BUILD_HOST_COMMAND_PARAMS(EC_CMD_REBOOT_EC, 0, reboot_params);
+	struct ec_response_vstore_info info_response;
+	struct host_cmd_handler_args info_args = BUILD_HOST_COMMAND_RESPONSE(
+		EC_CMD_VSTORE_INFO, 0, info_response);
+	jmp_buf env;
+	int i;
+
+	shell_backend_dummy_clear_output(get_ec_shell());
+	system_common_pre_init();
+
+	for (i = 0; i < EC_VSTORE_SLOT_SIZE; i++)
+		write_params.data[i] = i + 1;
+
+	/* Write to a slot */
+	zassert_ok(ec_cmd_vstore_write(NULL, &write_params), NULL);
+
+	/* Set up so we get back to this test on a reboot */
+	if (!setjmp(env)) {
+		system_fake_setenv(&env);
+
+		/* Reboot to RW  */
+		zassert_ok(host_command_process(&reboot_args), NULL);
+
+		/* Does not return unless something went wrong */
+		zassert_unreachable("Failed to reboot");
+	}
+
+	/* the reboot should end up here: check the slot is still locked */
+	zassert_ok(host_command_process(&info_args), NULL);
+	zassert_ok(info_args.result, NULL);
+	zassert_equal(info_args.response_size, sizeof(info_response), NULL);
+	zassert_equal(info_response.slot_count, CONFIG_VSTORE_SLOT_COUNT,
+		      "response.slot_count = %d", info_response.slot_count);
+	zassert_equal(info_response.slot_locked, 1 << 0,
+		      "response.slot_locked = %#x", info_response.slot_locked);
+
+	/* Clear locks to put things into a normal state */
+	vstore_clear_lock();
+}
diff --git a/zephyr/test/drivers/default/src/watchdog.c b/zephyr/test/drivers/default/src/watchdog.c
new file mode 100644
index 0000000000..46e981e2b5
--- /dev/null
+++ b/zephyr/test/drivers/default/src/watchdog.c
@@ -0,0 +1,135 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ * @brief Unit Tests for watchdog.
+ */
+
+#include "common.h"
+#include "ec_tasks.h"
+#include "hooks.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "watchdog.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/watchdog.h>
+#include <zephyr/fff.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/ztest.h>
+
+#define wdt DEVICE_DT_GET(DT_CHOSEN(cros_ec_watchdog))
+
+/**
+ * @brief Default watchdog timeout plus some time for it to expire.
+ */
+#define DEFAULT_WDT_EXPIRY_MS \
+	(CONFIG_AUX_TIMER_PERIOD_MS + (CONFIG_AUX_TIMER_PERIOD_MS / 2))
+
+/**
+ * @brief Boolean to indicate watchdog alert triggered
+ */
+extern bool wdt_warning_triggered;
+bool wdt_initialized;
+
+/**
+ * @brief timer to used to validate watchdog expiries.
+ */
+K_TIMER_DEFINE(ktimer, NULL, NULL);
+
+/**
+ * @brief Watchdog test setup handler.
+ */
+static void watchdog_before(void *state)
+{
+	ARG_UNUSED(state);
+	set_test_runner_tid();
+	wdt_warning_triggered = false;
+
+	/* When shuffling need watchdog initialized and running
+	 * for other tests.
+	 */
+	if (!wdt_initialized) {
+		(void)watchdog_init();
+		wdt_initialized = true;
+	}
+}
+
+/**
+ * @brief TestPurpose: Verify watchdog initialization.
+ *
+ * @details
+ * Validate watchdog initialization.
+ *
+ * Expected Results
+ *  - Successful on first init.
+ *  - Failure on second init.
+ */
+ZTEST(watchdog, test_watchdog_init)
+{
+	int retval = EC_SUCCESS;
+
+	/* Test already initialized (initialized in watchdog_before) */
+	retval = watchdog_init();
+	zassert_equal(-EBUSY, retval, "Expected -EBUSY, returned %d.", retval);
+}
+
+/**
+ * @brief TestPurpose: Verify watchdog reload.
+ *
+ * @details
+ * Validate watchdog is fed.
+ *
+ * Expected Results
+ *  - watchdog warning handler function is never triggered
+ */
+ZTEST(watchdog, test_watchdog_reload)
+{
+	int i;
+	int safe_wait_ms = DEFAULT_WDT_EXPIRY_MS / 2;
+
+	zassert_false(wdt_warning_triggered, "Watchdog timer expired early.");
+	watchdog_reload();
+	for (i = 0; i < 10; i++) {
+		k_timer_start(&ktimer, K_MSEC(safe_wait_ms), K_NO_WAIT);
+		k_busy_wait(safe_wait_ms * 1000);
+		k_timer_stop(&ktimer);
+		watchdog_reload();
+		zassert_false(wdt_warning_triggered,
+			      "Watchdog timer expired unexpectedly on loop=%d",
+			      i);
+	}
+}
+
+/**
+ * @brief TestPurpose: Verify watchdog timer expires.
+ *
+ * @details
+ * Validate watchdog timer expiry occurs after busy wait
+ *
+ * Expected Results
+ *  - Validate watchdog warning handler function is triggered.
+ */
+ZTEST(watchdog, test_wdt_warning_handler)
+{
+	/* Feed the dog so timer is reset */
+	watchdog_reload();
+
+	zassert_false(wdt_warning_triggered, "Watchdog timer expired early.");
+
+	k_timer_start(&ktimer, K_MSEC(DEFAULT_WDT_EXPIRY_MS), K_NO_WAIT);
+	k_busy_wait(DEFAULT_WDT_EXPIRY_MS * 1000);
+	k_timer_stop(&ktimer);
+
+	zassert_true(wdt_warning_triggered, "Watchdog timer did not expire.");
+}
+
+/**
+ * @brief Test Suite: Verifies watchdog functionality.
+ */
+ZTEST_SUITE(watchdog, drivers_predicate_post_main, NULL, watchdog_before, NULL,
+	    NULL);
diff --git a/zephyr/test/drivers/dps/CMakeLists.txt b/zephyr/test/drivers/dps/CMakeLists.txt
new file mode 100644
index 0000000000..0433fe951b
--- /dev/null
+++ b/zephyr/test/drivers/dps/CMakeLists.txt
@@ -0,0 +1,5 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_sources(app PRIVATE src/dps_config.c src/dps_selection.c)
diff --git a/zephyr/test/drivers/dps/prj.conf b/zephyr/test/drivers/dps/prj.conf
new file mode 100644
index 0000000000..1f1e1c5d0e
--- /dev/null
+++ b/zephyr/test/drivers/dps/prj.conf
@@ -0,0 +1,5 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_PLATFORM_EC_USB_PD_DPS=y
diff --git a/zephyr/test/drivers/dps/src/dps_config.c b/zephyr/test/drivers/dps/src/dps_config.c
new file mode 100644
index 0000000000..aaa3ac14ff
--- /dev/null
+++ b/zephyr/test/drivers/dps/src/dps_config.c
@@ -0,0 +1,262 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "builtin/stdio.h"
+#include "console.h"
+#include "dps.h"
+#include "test/drivers/test_state.h"
+#include "timer.h"
+
+#include <zephyr/ztest.h>
+
+struct dps_config_fixture {
+	struct dps_config_t saved_config;
+	int saved_debug_level;
+};
+
+static void *dps_config_setup(void)
+{
+	static struct dps_config_fixture fixture;
+
+	fixture.saved_config = *dps_get_config();
+	fixture.saved_debug_level = *dps_get_debug_level();
+
+	return &fixture;
+}
+
+static void dps_config_before(void *data)
+{
+	dps_enable(true);
+}
+
+static void dps_config_after(void *data)
+{
+	struct dps_config_fixture *f = (struct dps_config_fixture *)data;
+
+	*dps_get_config() = f->saved_config;
+	*dps_get_debug_level() = f->saved_debug_level;
+	dps_enable(true);
+}
+
+ZTEST_F(dps_config, test_enable)
+{
+	zassert_true(dps_is_enabled(), NULL);
+	dps_enable(false);
+	zassert_false(dps_is_enabled(), NULL);
+	dps_enable(true);
+	zassert_true(dps_is_enabled(), NULL);
+}
+
+ZTEST_F(dps_config, test_config)
+{
+	struct dps_config_t *config = dps_get_config();
+
+	zassert_true(config->k_less_pwr <= config->k_more_pwr, NULL);
+	zassert_true(config->k_less_pwr > 0 && config->k_less_pwr < 100, NULL);
+	zassert_true(config->k_more_pwr > 0 && config->k_more_pwr < 100, NULL);
+
+	zassert_ok(dps_init(), NULL);
+	*config = fixture->saved_config;
+
+	config->k_less_pwr = config->k_more_pwr + 1;
+	zassert_equal(dps_init(), EC_ERROR_INVALID_CONFIG, NULL);
+	*config = fixture->saved_config;
+
+	config->k_more_pwr = 101;
+	zassert_equal(dps_init(), EC_ERROR_INVALID_CONFIG, NULL);
+	*config = fixture->saved_config;
+}
+
+ZTEST(dps_config, test_console_cmd__print_info)
+{
+	/* Print current status to console */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "dps"), NULL);
+}
+
+ZTEST(dps_config, test_console_cmd__enable)
+{
+	/* Disable DPS first, then try enabling */
+	dps_enable(false);
+	zassert_false(dps_is_enabled(), NULL);
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "dps en"), NULL);
+
+	zassert_true(dps_is_enabled(), NULL);
+}
+
+ZTEST(dps_config, test_console_cmd__disable)
+{
+	/* Should already by enabled due to before() function */
+	zassert_true(dps_is_enabled(), NULL);
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "dps dis"), NULL);
+
+	zassert_false(dps_is_enabled(), NULL);
+}
+
+ZTEST(dps_config, test_console_cmd__fakepwr_print)
+{
+	/* Print current fake power status to console */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "dps fakepwr"), NULL);
+}
+
+ZTEST(dps_config, test_console_cmd__fakepwr_enable_disable)
+{
+	zassert_false(dps_is_fake_enabled(),
+		      "fakepwr shouldn't be enabled by default");
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "dps fakepwr 100 200"),
+		   NULL);
+	zassert_true(dps_is_fake_enabled(), NULL);
+	zassert_equal(100, dps_get_fake_mv(), "Got fake_mv=%d",
+		      dps_get_fake_mv());
+	zassert_equal(200, dps_get_fake_ma(), "Got fake_ma=%d",
+		      dps_get_fake_ma());
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "dps fakepwr dis"), NULL);
+	zassert_false(dps_is_fake_enabled(), NULL);
+}
+
+ZTEST(dps_config, test_console_cmd__fakepwr_invalid)
+{
+	/* Various invalid parameters */
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "dps fakepwr 100"), NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "dps fakepwr -100 -200"),
+		   NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "dps fakepwr 100 -200"),
+		   NULL);
+}
+
+ZTEST(dps_config, test_console_cmd__debuglevel)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "dps debug 999"), NULL);
+
+	zassert_equal(999, *dps_get_debug_level(), "Debug level is %d",
+		      *dps_get_debug_level());
+}
+
+ZTEST(dps_config, test_console_cmd__setkmore)
+{
+	struct dps_config_t *config = dps_get_config();
+	char cmd[32];
+
+	/* Try some invalid requests first */
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "dps setkmore"), NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "dps setkmore 101"),
+		   NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "dps setkmore 0"), NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "dps setkmore -1"), NULL);
+
+	zassert_true(crec_snprintf(cmd, sizeof(cmd), "dps setkmore %d",
+				   config->k_less_pwr - 1) > 0,
+		     NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), cmd), NULL);
+
+	/* Adjust k_more_pwr to be one over k_less_pwr */
+	zassert_true(crec_snprintf(cmd, sizeof(cmd), "dps setkmore %d",
+				   config->k_less_pwr + 1) > 0,
+		     NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), cmd), NULL);
+
+	zassert_equal(config->k_less_pwr + 1, config->k_more_pwr,
+		      "k_more_pwr is %d but should be %d", config->k_more_pwr,
+		      config->k_less_pwr + 1);
+}
+
+ZTEST(dps_config, test_console_cmd__setkless)
+{
+	struct dps_config_t *config = dps_get_config();
+	char cmd[32];
+
+	/* Try some invalid requests first */
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "dps setkless"), NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "dps setkless 101"),
+		   NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "dps setkless 0"), NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "dps setkless -1"), NULL);
+
+	zassert_true(crec_snprintf(cmd, sizeof(cmd), "dps setkless %d",
+				   config->k_more_pwr + 1) > 0,
+		     NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), cmd), NULL);
+
+	/* Adjust k_less_pwr to be one under k_more_pwr */
+	zassert_true(crec_snprintf(cmd, sizeof(cmd), "dps setkless %d",
+				   config->k_more_pwr - 1) > 0,
+		     NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), cmd), NULL);
+
+	zassert_equal(config->k_more_pwr - 1, config->k_less_pwr,
+		      "k_less_pwr is %d but should be %d", config->k_less_pwr,
+		      config->k_more_pwr - 1);
+}
+
+ZTEST(dps_config, test_console_cmd__setksample)
+{
+	struct dps_config_t *config = dps_get_config();
+
+	/* Try some invalid requests first */
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "dps setksample"), NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "dps setksample -1"),
+		   NULL);
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "dps setksample 999"),
+		   NULL);
+
+	zassert_equal(999, config->k_sample, "k_sample is %d",
+		      config->k_sample);
+}
+
+ZTEST(dps_config, test_console_cmd__setkwindow)
+{
+	struct dps_config_t *config = dps_get_config();
+
+	/* Try some invalid requests first */
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "dps setkwin"), NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "dps setkwin -1"), NULL);
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "dps setkwin 4"), NULL);
+
+	zassert_equal(4, config->k_window, "k_window is %d", config->k_window);
+}
+
+ZTEST(dps_config, test_console_cmd__settcheck)
+{
+	struct dps_config_t *config = dps_get_config();
+
+	/* Try some invalid requests first */
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "dps settcheck"), NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "dps settcheck -1"),
+		   NULL);
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "dps settcheck 5"), NULL);
+
+	zassert_equal(5 * SECOND, config->t_check, "t_check is %d",
+		      config->t_check);
+}
+
+ZTEST(dps_config, test_console_cmd__settstable)
+{
+	struct dps_config_t *config = dps_get_config();
+
+	/* Try some invalid requests first */
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "dps settstable"), NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "dps settstable -1"),
+		   NULL);
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "dps settstable 6"), NULL);
+
+	zassert_equal(6 * SECOND, config->t_stable, "t_stable is %d",
+		      config->t_stable);
+}
+
+ZTEST(dps_config, test_console_cmd__invalid)
+{
+	/* Non-existent subcommand should fail */
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "dps foobar xyz"), NULL);
+}
+
+ZTEST_SUITE(dps_config, drivers_predicate_pre_main, dps_config_setup,
+	    dps_config_before, dps_config_after, NULL);
diff --git a/zephyr/test/drivers/dps/src/dps_selection.c b/zephyr/test/drivers/dps/src/dps_selection.c
new file mode 100644
index 0000000000..bc897ae0bb
--- /dev/null
+++ b/zephyr/test/drivers/dps/src/dps_selection.c
@@ -0,0 +1,238 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "charge_state.h"
+#include "console.h"
+#include "dps.h"
+#include "ec_commands.h"
+#include "ec_tasks.h"
+#include "emul/emul_isl923x.h"
+#include "emul/tcpc/emul_tcpci.h"
+#include "emul/tcpc/emul_tcpci_partner_common.h"
+#include "emul/tcpc/emul_tcpci_partner_drp.h"
+#include "emul/tcpc/emul_tcpci_partner_src.h"
+#include "host_command.h"
+#include "tcpm/tcpci.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "usb_pd.h"
+
+#include <stdint.h>
+
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/fff.h>
+#include <zephyr/kernel.h>
+#include <zephyr/shell/shell_dummy.h>
+#include <zephyr/ztest.h>
+
+#define TEST_PORT 0
+
+FAKE_VALUE_FUNC(int, get_batt_charge_power, int *);
+FAKE_VALUE_FUNC(int, get_battery_target_voltage, int *);
+FAKE_VALUE_FUNC(int, get_desired_input_power, int *, int *);
+
+struct common_fixture {
+	const struct emul *tcpci_emul;
+	const struct emul *charger_emul;
+	struct tcpci_partner_data partner;
+	struct tcpci_snk_emul_data snk_ext;
+	struct tcpci_src_emul_data src_ext;
+	struct tcpci_drp_emul_data drp_ext;
+};
+
+struct dps_selection_fixture {
+	struct common_fixture common;
+};
+
+/* FFF fakes for driver functions. These get assigned to members of the
+ * charger_drv struct
+ */
+static int target_mv_custom_fake;
+static int get_battery_target_voltage_custom_fake(int *target_mv)
+{
+	*target_mv = target_mv_custom_fake;
+
+	return EC_SUCCESS;
+}
+
+static int vbus_custom_fake;
+static int input_current_custom_fake;
+static int get_desired_input_power_custom_fake(int *vbus, int *input_current)
+{
+	*vbus = vbus_custom_fake;
+	*input_current = input_current_custom_fake;
+
+	return vbus_custom_fake * input_current_custom_fake / 1000;
+}
+
+static void reset(void)
+{
+	/* Reset fakes */
+	RESET_FAKE(get_batt_charge_power);
+	RESET_FAKE(get_battery_target_voltage);
+	RESET_FAKE(get_desired_input_power);
+}
+
+static void connect_partner_to_port(const struct emul *tcpc_emul,
+				    const struct emul *charger_emul,
+				    struct tcpci_partner_data *partner_emul,
+				    const struct tcpci_src_emul_data *src_ext)
+{
+	/*
+	 * TODO(b/221439302): Updating the TCPCI emulator registers, updating
+	 * the charger, and alerting should all be a part of the connect
+	 * function.
+	 */
+	set_ac_enabled(true);
+	zassert_ok(tcpci_partner_connect_to_tcpci(partner_emul, tcpc_emul),
+		   NULL);
+
+	isl923x_emul_set_adc_vbus(charger_emul,
+				  PDO_FIXED_GET_VOLT(src_ext->pdo[0]));
+
+	/* Wait for PD negotiation and current ramp. */
+	k_sleep(K_SECONDS(10));
+}
+
+static void disconnect_partner_from_port(const struct emul *tcpc_emul,
+					 const struct emul *charger_emul)
+{
+	zassert_ok(tcpci_emul_disconnect_partner(tcpc_emul), NULL);
+	isl923x_emul_set_adc_vbus(charger_emul, 0);
+	k_sleep(K_SECONDS(1));
+}
+
+static void *common_setup(void)
+{
+	static struct dps_selection_fixture outer_fixture;
+	struct common_fixture *fixture = &outer_fixture.common;
+	struct tcpci_partner_data *partner = &fixture->partner;
+	struct tcpci_src_emul_data *src_ext = &fixture->src_ext;
+	struct tcpci_snk_emul_data *snk_ext = &fixture->snk_ext;
+
+	tcpci_partner_init(partner, PD_REV30);
+	fixture->partner.extensions = tcpci_drp_emul_init(
+		&fixture->drp_ext, partner, PD_ROLE_SOURCE,
+		tcpci_src_emul_init(src_ext, partner, NULL),
+		tcpci_snk_emul_init(snk_ext, partner, NULL));
+
+	/* Get references for the emulators */
+	fixture->tcpci_emul = EMUL_GET_USBC_BINDING(TEST_PORT, tcpc);
+	fixture->charger_emul = EMUL_GET_USBC_BINDING(TEST_PORT, chg);
+
+	return &outer_fixture;
+}
+
+static void *dps_selection_setup(void)
+{
+	return common_setup();
+}
+
+static void common_before(struct common_fixture *fixture)
+{
+	/* Set chipset to ON, this will set TCPM to DRP */
+	test_set_chipset_to_s0();
+
+	/* TODO(b/214401892): Check why need to give time TCPM to spin */
+	k_sleep(K_SECONDS(1));
+}
+
+static void dps_selection_before(void *data)
+{
+	struct dps_selection_fixture *outer = data;
+
+	common_before(&outer->common);
+
+	reset();
+}
+
+static void common_after(struct common_fixture *fixture)
+{
+	if (pd_is_connected(TEST_PORT)) {
+		disconnect_partner_from_port(fixture->tcpci_emul,
+					     fixture->charger_emul);
+	}
+}
+
+static void dps_selection_after(void *data)
+{
+	struct dps_selection_fixture *outer = data;
+
+	common_after(&outer->common);
+
+	reset();
+}
+
+ZTEST_USER_F(dps_selection, test_dps_pdo_switch)
+{
+	struct common_fixture *common = &fixture->common;
+	struct tcpci_src_emul_data *src_ext = &common->src_ext;
+	uint32_t *partner_pdo = src_ext->pdo;
+
+	/* Attach a partner with all of the Source Capability attributes that
+	 * "pd <port> srccaps" checks for.
+	 */
+	partner_pdo[0] =
+		PDO_FIXED(5000, 3000,
+			  PDO_FIXED_DUAL_ROLE | PDO_FIXED_UNCONSTRAINED |
+				  PDO_FIXED_COMM_CAP | PDO_FIXED_DATA_SWAP |
+				  PDO_FIXED_FRS_CURR_MASK);
+	partner_pdo[1] = PDO_FIXED(9000, 3000, PDO_FIXED_UNCONSTRAINED);
+	partner_pdo[2] = PDO_FIXED(10000, 3000, PDO_FIXED_UNCONSTRAINED);
+	partner_pdo[3] = PDO_FIXED(12000, 3000, PDO_FIXED_UNCONSTRAINED);
+	partner_pdo[4] = PDO_FIXED(15000, 3000, PDO_FIXED_UNCONSTRAINED);
+	partner_pdo[5] = PDO_FIXED(20000, 3000, PDO_FIXED_UNCONSTRAINED);
+	connect_partner_to_port(common->tcpci_emul, common->charger_emul,
+				&common->partner, &common->src_ext);
+
+	get_battery_target_voltage_fake.custom_fake =
+		get_battery_target_voltage_custom_fake;
+	get_desired_input_power_fake.custom_fake =
+		get_desired_input_power_custom_fake;
+
+	/* This value is not used if not have board overridden.  */
+	get_batt_charge_power_fake.return_val = 5566;
+
+	/* Assume the charge targeting at 9V. */
+	target_mv_custom_fake = 9000;
+
+	k_sleep(K_SECONDS(1));
+	/* Assumes the system sinks 15W. */
+	vbus_custom_fake = 20000;
+	input_current_custom_fake = 750;
+
+	/* DPS should request the PDO with the highest voltage at first. */
+	zassert_equal(pd_get_requested_voltage(TEST_PORT), 20000, NULL);
+
+	/* Wait for DPS to changing voltage */
+	k_sleep(K_SECONDS(20));
+
+	/* DPS should switch to 9V. */
+	zassert_equal(pd_get_requested_voltage(TEST_PORT), 9000, NULL);
+
+	/* Assumes the system sinks 27W/9V/3A. */
+	vbus_custom_fake = 9000;
+	input_current_custom_fake = 3000;
+	k_sleep(K_SECONDS(20));
+	/* PDO 10V/3A should be requested. */
+	zassert_equal(pd_get_requested_voltage(TEST_PORT), 10000, NULL);
+
+	/* Assumes the system sinks 30W/10V/3A. */
+	vbus_custom_fake = 10000;
+	k_sleep(K_SECONDS(20));
+	/* PDO 12V/3A should be requested. */
+	zassert_equal(pd_get_requested_voltage(TEST_PORT), 12000, NULL);
+
+	/* Assumes the system sinks 36W/12V/3A. */
+	vbus_custom_fake = 12000;
+	k_sleep(K_SECONDS(20));
+	/* PDO 15V/3A should be requested. */
+	zassert_equal(pd_get_requested_voltage(TEST_PORT), 15000, NULL);
+}
+
+ZTEST_SUITE(dps_selection, drivers_predicate_post_main, dps_selection_setup,
+	    dps_selection_before, dps_selection_after, NULL);
diff --git a/zephyr/test/drivers/flash/CMakeLists.txt b/zephyr/test/drivers/flash/CMakeLists.txt
new file mode 100644
index 0000000000..aa90d98629
--- /dev/null
+++ b/zephyr/test/drivers/flash/CMakeLists.txt
@@ -0,0 +1,11 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_sources(app PRIVATE
+	src/flash.c
+)
+
+target_sources_ifdef(CONFIG_PLATFORM_EC_USE_ZEPHYR_FLASH_PAGE_LAYOUT
+	app PRIVATE src/flash_bank_api.c
+)
diff --git a/zephyr/test/drivers/flash/src/flash.c b/zephyr/test/drivers/flash/src/flash.c
new file mode 100644
index 0000000000..dfbb2d2d15
--- /dev/null
+++ b/zephyr/test/drivers/flash/src/flash.c
@@ -0,0 +1,1031 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+#include "emul/emul_flash.h"
+#include "flash.h"
+#include "host_command.h"
+#include "system.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/kernel.h>
+#include <zephyr/shell/shell_dummy.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/ztest.h>
+
+#define WP_L_GPIO_PATH NAMED_GPIOS_GPIO_NODE(wp_l)
+
+static int gpio_wp_l_set(int value)
+{
+	const struct device *wp_l_gpio_dev =
+		DEVICE_DT_GET(DT_GPIO_CTLR(WP_L_GPIO_PATH, gpios));
+
+	return gpio_emul_input_set(wp_l_gpio_dev,
+				   DT_GPIO_PIN(WP_L_GPIO_PATH, gpios), value);
+}
+
+ZTEST_USER(flash, test_hostcmd_flash_protect_wp_asserted)
+{
+	struct ec_response_flash_protect response;
+	struct ec_params_flash_protect params = {
+		.mask = 0,
+		.flags = 0,
+	};
+	/* The original flags not 0 as GPIO WP_L asserted */
+	uint32_t expected_flags = EC_FLASH_PROTECT_GPIO_ASSERTED;
+
+	/* Get the flash protect */
+	zassert_ok(ec_cmd_flash_protect_v1(NULL, &params, &response), NULL);
+	zassert_equal(response.flags, expected_flags, "response.flags = %d",
+		      response.flags);
+
+	/* Enable RO_AT_BOOT */
+	params.mask = EC_FLASH_PROTECT_RO_AT_BOOT;
+	params.flags = EC_FLASH_PROTECT_RO_AT_BOOT;
+	expected_flags |= EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW;
+	zassert_ok(ec_cmd_flash_protect_v1(NULL, &params, &response), NULL);
+	zassert_equal(response.flags, expected_flags, "response.flags = %d",
+		      response.flags);
+
+	/* Disable RO_AT_BOOT; should change nothing as GPIO WP_L is asserted */
+	params.mask = EC_FLASH_PROTECT_RO_AT_BOOT;
+	params.flags = 0;
+	zassert_ok(ec_cmd_flash_protect_v1(NULL, &params, &response), NULL);
+	zassert_equal(response.flags, expected_flags, "response.flags = %d",
+		      response.flags);
+
+	/* Enable ALL_NOW */
+	params.mask = EC_FLASH_PROTECT_ALL_NOW;
+	params.flags = EC_FLASH_PROTECT_ALL_NOW;
+	expected_flags |= EC_FLASH_PROTECT_ALL_NOW;
+	zassert_ok(ec_cmd_flash_protect_v1(NULL, &params, &response), NULL);
+	zassert_equal(response.flags, expected_flags, "response.flags = %d",
+		      response.flags);
+
+	/* Disable ALL_NOW; should change nothing as GPIO WP_L is asserted */
+	params.mask = EC_FLASH_PROTECT_ALL_NOW;
+	params.flags = 0;
+	zassert_ok(ec_cmd_flash_protect_v1(NULL, &params, &response), NULL);
+	zassert_equal(response.flags, expected_flags, "response.flags = %d",
+		      response.flags);
+
+	/* Disable RO_AT_BOOT; should change nothing as GPIO WP_L is asserted */
+	params.mask = EC_FLASH_PROTECT_RO_AT_BOOT;
+	params.flags = 0;
+	zassert_ok(ec_cmd_flash_protect_v1(NULL, &params, &response), NULL);
+	zassert_equal(response.flags, expected_flags, "response.flags = %d",
+		      response.flags);
+}
+
+ZTEST_USER(flash, test_hostcmd_flash_protect_wp_deasserted)
+{
+	struct ec_response_flash_protect response;
+	struct ec_params_flash_protect params = {
+		.mask = 0,
+		.flags = 0,
+	};
+	/* The original flags 0 as GPIO WP_L deasserted */
+	uint32_t expected_flags = 0;
+
+	zassert_ok(gpio_wp_l_set(1), NULL);
+
+	/* Get the flash protect */
+	zassert_ok(ec_cmd_flash_protect_v1(NULL, &params, &response), NULL);
+	zassert_equal(response.flags, expected_flags, "response.flags = %d",
+		      response.flags);
+
+	/* Enable RO_AT_BOOT */
+	params.mask = EC_FLASH_PROTECT_RO_AT_BOOT;
+	params.flags = EC_FLASH_PROTECT_RO_AT_BOOT;
+	expected_flags |= EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW;
+	zassert_ok(ec_cmd_flash_protect_v1(NULL, &params, &response), NULL);
+	zassert_equal(response.flags, expected_flags, "response.flags = %d",
+		      response.flags);
+
+	/* Disable RO_AT_BOOT */
+	params.mask = EC_FLASH_PROTECT_RO_AT_BOOT;
+	params.flags = 0;
+	expected_flags &=
+		~(EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW);
+	zassert_ok(ec_cmd_flash_protect_v1(NULL, &params, &response), NULL);
+	zassert_equal(response.flags, expected_flags, "response.flags = %d",
+		      response.flags);
+
+	/* Enable RO_AT_BOOT */
+	params.mask = EC_FLASH_PROTECT_RO_AT_BOOT;
+	params.flags = EC_FLASH_PROTECT_RO_AT_BOOT;
+	expected_flags |= EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW;
+	zassert_ok(ec_cmd_flash_protect_v1(NULL, &params, &response), NULL);
+	zassert_equal(response.flags, expected_flags, "response.flags = %d",
+		      response.flags);
+
+	/* Enable ALL_NOW; should change nothing as GPIO WP_L is deasserted */
+	params.mask = EC_FLASH_PROTECT_ALL_NOW;
+	params.flags = EC_FLASH_PROTECT_ALL_NOW;
+	zassert_ok(ec_cmd_flash_protect_v1(NULL, &params, &response), NULL);
+	zassert_equal(response.flags, expected_flags, "response.flags = %d",
+		      response.flags);
+}
+
+ZTEST_USER(flash, test_hostcmd_flash_read__overflow)
+{
+	struct ec_params_flash_read params = {
+		.size = 32,
+	};
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_PARAMS(EC_CMD_FLASH_READ, 0, params);
+
+	zassert_equal(EC_RES_OVERFLOW, host_command_process(&args));
+}
+
+#define TEST_BUF_SIZE 0x100
+
+ZTEST_USER(flash, test_hostcmd_flash_write_and_erase)
+{
+	uint8_t in_buf[TEST_BUF_SIZE];
+	uint8_t out_buf[sizeof(struct ec_params_flash_write) + TEST_BUF_SIZE];
+
+	struct ec_params_flash_read read_params = {
+		.offset = 0x10000,
+		.size = TEST_BUF_SIZE,
+	};
+	struct host_cmd_handler_args read_args =
+		BUILD_HOST_COMMAND(EC_CMD_FLASH_READ, 0, in_buf, read_params);
+
+	struct ec_params_flash_erase erase_params = {
+		.offset = 0x10000,
+		.size = 0x10000,
+	};
+
+	/* The write host command structs need to be filled run-time */
+	struct ec_params_flash_write *write_params =
+		(struct ec_params_flash_write *)out_buf;
+	struct host_cmd_handler_args write_args =
+		BUILD_HOST_COMMAND_SIMPLE(EC_CMD_FLASH_WRITE, 0);
+
+	write_params->offset = 0x10000;
+	write_params->size = TEST_BUF_SIZE;
+	write_args.params = write_params;
+	write_args.params_size = sizeof(*write_params) + TEST_BUF_SIZE;
+
+	/* Flash write to all 0xec */
+	memset(write_params + 1, 0xec, TEST_BUF_SIZE);
+	zassert_ok(host_command_process(&write_args), NULL);
+
+	/* Flash read and compare the readback data */
+	zassert_ok(host_command_process(&read_args), NULL);
+	zassert_equal(read_args.response_size, TEST_BUF_SIZE, NULL);
+	zassert_equal(in_buf[0], 0xec, "readback data not expected: 0x%x",
+		      in_buf[0]);
+	zassert_equal(in_buf[TEST_BUF_SIZE - 1], 0xec,
+		      "readback data not expected: 0x%x", in_buf[0]);
+
+	/* Flash erase */
+	zassert_ok(ec_cmd_flash_erase(NULL, &erase_params), NULL);
+
+	/* Flash read and compare the readback data */
+	zassert_ok(host_command_process(&read_args), NULL);
+	zassert_equal(in_buf[0], 0xff, "readback data not expected: 0x%x",
+		      in_buf[0]);
+	zassert_equal(in_buf[TEST_BUF_SIZE - 1], 0xff,
+		      "readback data not expected: 0x%x", in_buf[0]);
+}
+
+#define EC_FLASH_REGION_START \
+	MIN(CONFIG_EC_PROTECTED_STORAGE_OFF, CONFIG_EC_WRITABLE_STORAGE_OFF)
+
+static void test_region_info(uint32_t region, uint32_t expected_offset,
+			     uint32_t expected_size)
+{
+	struct ec_response_flash_region_info response;
+	struct ec_params_flash_region_info params = {
+		.region = region,
+	};
+
+	zassert_ok(ec_cmd_flash_region_info_v1(NULL, &params, &response), NULL);
+	zassert_equal(response.offset, expected_offset, NULL);
+	zassert_equal(response.size, expected_size, NULL);
+}
+
+ZTEST_USER(flash, test_hostcmd_flash_region_info_ro)
+{
+	test_region_info(EC_FLASH_REGION_RO,
+			 CONFIG_EC_PROTECTED_STORAGE_OFF +
+				 CONFIG_RO_STORAGE_OFF - EC_FLASH_REGION_START,
+			 EC_FLASH_REGION_RO_SIZE);
+}
+
+ZTEST_USER(flash, test_hostcmd_flash_region_info_active)
+{
+	test_region_info(EC_FLASH_REGION_ACTIVE,
+			 flash_get_rw_offset(system_get_active_copy()) -
+				 EC_FLASH_REGION_START,
+			 CONFIG_EC_WRITABLE_STORAGE_SIZE);
+}
+
+ZTEST_USER(flash, test_hostcmd_flash_region_info_active_wp_ro)
+{
+	test_region_info(EC_FLASH_REGION_WP_RO,
+			 CONFIG_WP_STORAGE_OFF - EC_FLASH_REGION_START,
+			 CONFIG_WP_STORAGE_SIZE);
+}
+
+ZTEST_USER(flash, test_hostcmd_flash_region_info_active_update)
+{
+	test_region_info(EC_FLASH_REGION_UPDATE,
+			 flash_get_rw_offset(system_get_update_copy()) -
+				 EC_FLASH_REGION_START,
+			 CONFIG_EC_WRITABLE_STORAGE_SIZE);
+}
+
+ZTEST_USER(flash, test_hostcmd_flash_region_info_active_invalid)
+{
+	struct ec_response_flash_region_info response;
+	struct ec_params_flash_region_info params = {
+		/* Get an invalid region */
+		.region = 10,
+	};
+
+	zassert_equal(ec_cmd_flash_region_info_v1(NULL, &params, &response),
+		      EC_RES_INVALID_PARAM, NULL);
+}
+
+ZTEST_USER(flash, test_hostcmd_flash_info_1)
+{
+	struct ec_response_flash_info_1 response;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_RESPONSE(EC_CMD_FLASH_INFO, 1, response);
+
+	if (!IS_ENABLED(CONFIG_PLATFORM_EC_USE_ZEPHYR_FLASH_PAGE_LAYOUT)) {
+		/* Get the flash info. */
+		zassert_ok(host_command_process(&args), NULL);
+		zassert_equal(response.flash_size,
+			      CONFIG_FLASH_SIZE_BYTES - EC_FLASH_REGION_START,
+			      "response.flash_size = %d", response.flash_size);
+		zassert_equal(response.flags, 0, "response.flags = %d",
+			      response.flags);
+		zassert_equal(response.write_block_size,
+			      CONFIG_FLASH_WRITE_SIZE,
+			      "response.write_block_size = %d",
+			      response.write_block_size);
+		zassert_equal(response.erase_block_size,
+			      CONFIG_FLASH_ERASE_SIZE,
+			      "response.erase_block_size = %d",
+			      response.erase_block_size);
+		zassert_equal(response.protect_block_size,
+			      CONFIG_FLASH_BANK_SIZE,
+			      "response.protect_block_size = %d",
+			      response.protect_block_size);
+		zassert_equal(response.write_ideal_size,
+			      (args.response_max -
+			       sizeof(struct ec_params_flash_write)) &
+				      ~(CONFIG_FLASH_WRITE_SIZE - 1),
+			      "response.write_ideal_size = %d",
+			      response.write_ideal_size);
+	} else {
+		/*
+		 * Flash sector description not supported in FLASH_INFO
+		 * version 1 command
+		 */
+		zassert_equal(ec_cmd_flash_info_v1(NULL, &response),
+			      EC_RES_INVALID_VERSION, NULL);
+	}
+}
+
+ZTEST_USER(flash, test_hostcmd_flash_info_2_zero_bank)
+{
+	struct ec_response_flash_info_2 response = {};
+	struct ec_params_flash_info_2 params = {
+		.num_banks_desc = 0,
+	};
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_FLASH_INFO, 2, response, params);
+
+	/* Get the flash info. */
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_equal(response.flash_size,
+		      CONFIG_FLASH_SIZE_BYTES - EC_FLASH_REGION_START, "got %d",
+		      response.flash_size);
+	zassert_equal(response.flags, 0, "got %d", response.flags);
+	zassert_equal(
+		response.write_ideal_size,
+		(args.response_max - sizeof(struct ec_params_flash_write)) &
+			~(CONFIG_FLASH_WRITE_SIZE - 1),
+		"got %d", response.write_ideal_size);
+	zassert_equal(response.num_banks_total, 1, "got %d",
+		      response.num_banks_total);
+	zassert_equal(response.num_banks_desc, 0, "got %d",
+		      response.num_banks_desc);
+}
+
+ZTEST_USER(flash, test_hostcmd_flash_info_2)
+{
+	uint8_t response_buffer[sizeof(struct ec_response_flash_info_2) +
+				sizeof(struct ec_flash_bank)];
+	struct ec_response_flash_info_2 *response =
+		(struct ec_response_flash_info_2 *)response_buffer;
+	struct ec_params_flash_info_2 params = {
+		.num_banks_desc = 1,
+	};
+	struct host_cmd_handler_args args = BUILD_HOST_COMMAND(
+		EC_CMD_FLASH_INFO, 2, response_buffer, params);
+
+	/* Get the flash info. */
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_equal(response->flash_size,
+		      CONFIG_FLASH_SIZE_BYTES - EC_FLASH_REGION_START, "got %d",
+		      response->flash_size);
+	zassert_equal(response->flags, 0, "got %d", response->flags);
+	zassert_equal(
+		response->write_ideal_size,
+		(args.response_max - sizeof(struct ec_params_flash_write)) &
+			~(CONFIG_FLASH_WRITE_SIZE - 1),
+		"got %d", response->write_ideal_size);
+	zassert_equal(response->num_banks_total, 1, "got %d",
+		      response->num_banks_total);
+	zassert_equal(response->num_banks_desc, 1, "got %d",
+		      response->num_banks_desc);
+	zassert_equal(response->banks[0].count,
+		      CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE,
+		      "got %d", response->banks[0].count);
+	zassert_equal(response->banks[0].size_exp,
+		      __fls(CONFIG_FLASH_BANK_SIZE), "got %d",
+		      response->banks[0].size_exp);
+	zassert_equal(response->banks[0].write_size_exp,
+		      __fls(CONFIG_FLASH_WRITE_SIZE), "got %d",
+		      response->banks[0].write_size_exp);
+	zassert_equal(response->banks[0].erase_size_exp,
+		      __fls(CONFIG_FLASH_ERASE_SIZE), "got %d",
+		      response->banks[0].erase_size_exp);
+	zassert_equal(response->banks[0].protect_size_exp,
+		      __fls(CONFIG_FLASH_BANK_SIZE), "got %d",
+		      response->banks[0].protect_size_exp);
+}
+
+ZTEST_USER(flash, test_console_cmd_flash_info)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+	const char *outbuffer;
+	size_t buffer_size;
+	/* Arbitrary array size for sprintf should not need this amount */
+	char format_buffer[100];
+
+	shell_backend_dummy_clear_output(shell_zephyr);
+
+	zassert_ok(shell_execute_cmd(shell_zephyr, "flashinfo"));
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+
+	zassert_true(buffer_size > 0, NULL);
+
+	sprintf(format_buffer, "Usable:  %4d KB",
+		CONFIG_FLASH_SIZE_BYTES / 1024);
+	zassert_not_null(strstr(outbuffer, format_buffer));
+
+	sprintf(format_buffer, "Write:   %4d B (ideal %d B)",
+		CONFIG_FLASH_WRITE_SIZE, CONFIG_FLASH_WRITE_IDEAL_SIZE);
+	zassert_not_null(strstr(outbuffer, format_buffer));
+
+	if (IS_ENABLED(CONFIG_PLATFORM_EC_USE_ZEPHYR_FLASH_PAGE_LAYOUT)) {
+		sprintf(format_buffer, "%d regions", crec_flash_total_banks());
+		zassert_not_null(strstr(outbuffer, format_buffer));
+	}
+
+	sprintf(format_buffer, "Erase:   %4d B", CONFIG_FLASH_ERASE_SIZE);
+	zassert_not_null(strstr(outbuffer, format_buffer));
+
+	sprintf(format_buffer, "Protect: %4d B", CONFIG_FLASH_BANK_SIZE);
+	zassert_not_null(strstr(outbuffer, format_buffer));
+
+	zassert_not_null(strstr(outbuffer, "wp_gpio_asserted: ON"));
+	zassert_not_null(strstr(outbuffer, "ro_at_boot: OFF"));
+	zassert_not_null(strstr(outbuffer, "all_at_boot: OFF"));
+	zassert_not_null(strstr(outbuffer, "ro_now: OFF"));
+	zassert_not_null(strstr(outbuffer, "all_now: OFF"));
+	zassert_not_null(strstr(outbuffer, "STUCK: OFF"));
+	zassert_not_null(strstr(outbuffer, "INCONSISTENT: OFF"));
+	zassert_not_null(strstr(outbuffer, "UNKNOWN_ERROR: OFF"));
+	zassert_not_null(strstr(outbuffer, "Protected now"));
+}
+
+ZTEST_USER(flash, test_console_cmd_flashwp__invalid)
+{
+	/* Command requires a 2nd CLI arg */
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "flashwp"), NULL);
+}
+
+ZTEST_USER(flash, test_console_cmd_flashwp__now)
+{
+	uint32_t current;
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "flashwp true"), NULL);
+
+	current = crec_flash_get_protect();
+	zassert_true(EC_FLASH_PROTECT_GPIO_ASSERTED & current, "current = %08x",
+		     current);
+	zassert_true(EC_FLASH_PROTECT_RO_AT_BOOT & current, "current = %08x",
+		     current);
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "flashwp now"), NULL);
+
+	current = crec_flash_get_protect();
+	zassert_true(current & EC_FLASH_PROTECT_ALL_NOW, "current = %08x",
+		     current);
+}
+
+ZTEST_USER(flash, test_console_cmd_flashwp__all)
+{
+	uint32_t current;
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "flashwp true"), NULL);
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "flashwp all"), NULL);
+
+	current = crec_flash_get_protect();
+	zassert_true(EC_FLASH_PROTECT_ALL_NOW & current, "current = %08x",
+		     current);
+}
+
+ZTEST_USER(flash, test_console_cmd_flashwp__bool_false)
+{
+	uint32_t current;
+
+	/* Set RO_AT_BOOT and verify */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "flashwp true"), NULL);
+
+	current = crec_flash_get_protect();
+	zassert_true(current & EC_FLASH_PROTECT_RO_AT_BOOT, "current = %08x",
+		     current);
+
+	gpio_wp_l_set(1);
+
+	/* Now clear it */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "flashwp false"), NULL);
+
+	current = crec_flash_get_protect();
+	zassert_false(current & EC_FLASH_PROTECT_RO_AT_BOOT, "current = %08x",
+		      current);
+}
+
+ZTEST_USER(flash, test_console_cmd_flashwp__bool_true)
+{
+	uint32_t current;
+
+	gpio_wp_l_set(1);
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "flashwp true"), NULL);
+
+	current = crec_flash_get_protect();
+	zassert_equal(EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW,
+		      current, "current = %08x", current);
+}
+
+ZTEST_USER(flash, test_console_cmd_flashwp__bad_param)
+{
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "flashwp xyz"), NULL);
+}
+
+ZTEST_USER(flash, test_console_cmd_flash_erase__flash_locked)
+{
+	/* Force write protection on */
+	zassert_ok(crec_flash_physical_protect_now(1));
+
+	CHECK_CONSOLE_CMD("flasherase 0x1000 0x1000", NULL,
+			  EC_ERROR_ACCESS_DENIED);
+}
+
+ZTEST_USER(flash, test_console_cmd_flash_erase__bad_args)
+{
+	/* No args*/
+	CHECK_CONSOLE_CMD("flasherase", NULL, EC_ERROR_PARAM_COUNT);
+
+	/* Check for 1 of 2 required args */
+	CHECK_CONSOLE_CMD("flasherase 0x1000", NULL, EC_ERROR_PARAM_COUNT);
+
+	/* Check for alpha arg instead of number*/
+	CHECK_CONSOLE_CMD("flasherase xyz 100", NULL, EC_ERROR_PARAM1);
+	CHECK_CONSOLE_CMD("flasherase 100 xyz", NULL, EC_ERROR_PARAM2);
+}
+
+/**
+ * @brief Writes a 32-bit word at a specific location in flash memory. Uses Host
+ *        Command interface to communicate with flash driver.
+ *
+ * @param offset Address to begin writing at.
+ * @param data A 32-bit word to write.
+ * @return uint16_t Host command return status.
+ */
+static uint16_t write_flash_helper32(uint32_t offset, uint32_t data)
+{
+	uint8_t out_buf[sizeof(struct ec_params_flash_write) + sizeof(data)];
+
+	/* The write host command structs need to be filled run-time */
+	struct ec_params_flash_write *write_params =
+		(struct ec_params_flash_write *)out_buf;
+	struct host_cmd_handler_args write_args =
+		BUILD_HOST_COMMAND_SIMPLE(EC_CMD_FLASH_WRITE, 0);
+
+	write_params->offset = offset;
+	write_params->size = sizeof(data);
+	write_args.params = write_params;
+	write_args.params_size = sizeof(*write_params) + sizeof(data);
+
+	/* Flash write `data` */
+	memcpy(write_params + 1, &data, sizeof(data));
+	return host_command_process(&write_args);
+}
+
+/**
+ * @brief Reads a 32-bit word at a specific location in flash memory. Uses Host
+ *        Command interface to communicate with flash driver.
+ *
+ * @param offset Address to begin reading from.
+ * @param data Output param for 32-bit read data.
+ * @return uint16_t Host command return status.
+ */
+static uint16_t read_flash_helper32(uint32_t offset, uint32_t *output)
+{
+	struct ec_params_flash_read read_params = {
+		.offset = offset,
+		.size = sizeof(*output),
+	};
+	struct host_cmd_handler_args read_args =
+		BUILD_HOST_COMMAND(EC_CMD_FLASH_READ, 0, *output, read_params);
+
+	/* Flash read and compare the readback data */
+	return host_command_process(&read_args);
+}
+
+ZTEST_USER(flash, test_console_cmd_flash_erase__happy)
+{
+	/* Immediately before the region to erase */
+	zassert_ok(write_flash_helper32(0x10000 - 4, 0x5A5A5A5A));
+
+	/* Start and end of the region we will erase */
+	zassert_ok(write_flash_helper32(0x10000, 0xA1B2C3D4));
+	zassert_ok(write_flash_helper32(0x20000 - 4, 0x1A2B3C4D));
+
+	/* Immediately after the region to erase */
+	zassert_ok(write_flash_helper32(0x20000, 0xA5A5A5A5));
+
+	CHECK_CONSOLE_CMD("flasherase 0x10000 0x10000", NULL, EC_SUCCESS);
+
+	uint32_t output;
+
+	/* These should remain untouched */
+	zassert_ok(read_flash_helper32(0x10000 - 4, &output));
+	zassert_equal(output, 0x5A5A5A5A, "Got %08x", output);
+	zassert_ok(read_flash_helper32(0x20000, &output));
+	zassert_equal(output, 0xA5A5A5A5, "Got %08x", output);
+
+	/* These are within the erase region and should be reset to all FF */
+	zassert_ok(read_flash_helper32(0x10000, &output));
+	zassert_equal(output, 0xFFFFFFFF, "Got %08x", output);
+	zassert_ok(read_flash_helper32(0x20000 - 4, &output));
+	zassert_equal(output, 0xFFFFFFFF, "Got %08x", output);
+}
+
+#ifdef CONFIG_PLATFORM_EC_CBI_FLASH
+ZTEST_USER(flash, test_console_cmd_flash_erase__cbi_overlap_0)
+{
+	uint32_t output;
+
+	/* Immediately before the region to erase */
+	zassert_ok(write_flash_helper32(0x3F000 - 4, 0x5A5A5A5A));
+	/* Immediately after the region to erase */
+	zassert_ok(write_flash_helper32(0x40000, 0xA5A5A5A5));
+
+	/* The CBI region */
+	zassert_ok(read_flash_helper32(0x3F000, &output));
+	zassert_equal(output, 0xFFFFFFFF, "Got %08x", output);
+	zassert_ok(read_flash_helper32(0x40000 - 4, &output));
+	zassert_equal(output, 0xFFFFFFFF, "Got %08x", output);
+
+	CHECK_CONSOLE_CMD("flasherase 0x3F000 0x1000", NULL, EC_SUCCESS);
+
+	/* These should remain untouched */
+	zassert_ok(read_flash_helper32(0x3F000 - 4, &output));
+	zassert_equal(output, 0x5A5A5A5A, "Got %08x", output);
+	zassert_ok(read_flash_helper32(0x40000, &output));
+	zassert_equal(output, 0xA5A5A5A5, "Got %08x", output);
+
+	/* These are within the erase region and should be reset to all FF */
+	zassert_ok(read_flash_helper32(0x3F000, &output));
+	zassert_equal(output, 0xFFFFFFFF, "Got %08x", output);
+	zassert_ok(read_flash_helper32(0x40000 - 4, &output));
+	zassert_equal(output, 0xFFFFFFFF, "Got %08x", output);
+}
+
+ZTEST_USER(flash, test_console_cmd_flash_erase__cbi_overlap_left)
+{
+	uint32_t output;
+
+	/* Immediately before the region to erase */
+	zassert_ok(write_flash_helper32(0x3F000 - 4, 0x5A5A5A5A));
+	/* Immediately after the region to erase */
+	zassert_ok(write_flash_helper32(0x50000, 0x5A5A5A5A));
+	/* Immediately after the CBI region */
+	zassert_ok(write_flash_helper32(0x40000, 0xA5A5A5A5));
+	zassert_ok(read_flash_helper32(0x40000, &output));
+	zassert_equal(output, 0xA5A5A5A5, "Got %08x", output);
+
+	/* The CBI region */
+	zassert_ok(read_flash_helper32(0x3F000, &output));
+	zassert_equal(output, 0xFFFFFFFF, "Got %08x", output);
+	zassert_ok(read_flash_helper32(0x40000 - 4, &output));
+	zassert_equal(output, 0xFFFFFFFF, "Got %08x", output);
+
+	CHECK_CONSOLE_CMD("flasherase 0x3F000 0x11000", NULL, EC_SUCCESS);
+
+	/* These should remain untouched */
+	zassert_ok(read_flash_helper32(0x3F000 - 4, &output));
+	zassert_equal(output, 0x5A5A5A5A, "Got %08x", output);
+	zassert_ok(read_flash_helper32(0x50000, &output));
+	zassert_equal(output, 0x5A5A5A5A, "Got %08x", output);
+
+	/* These are within the erase region and should be reset to all FF */
+	zassert_ok(read_flash_helper32(0x3F000, &output));
+	zassert_equal(output, 0xFFFFFFFF, "Got %08x", output);
+	zassert_ok(read_flash_helper32(0x40000, &output));
+	zassert_equal(output, 0xFFFFFFFF, "Got %08x", output);
+	zassert_ok(read_flash_helper32(0x40000 - 4, &output));
+	zassert_equal(output, 0xFFFFFFFF, "Got %08x", output);
+	zassert_ok(read_flash_helper32(0x50000 - 4, &output));
+	zassert_equal(output, 0xFFFFFFFF, "Got %08x", output);
+}
+
+ZTEST_USER(flash, test_console_cmd_flash_erase__cbi_overlap_right)
+{
+	uint32_t output;
+
+	/* Immediately before the region to erase */
+	zassert_ok(write_flash_helper32(0x2F000 - 4, 0x5A5A5A5A));
+	/* Immediately after the region to erase */
+	zassert_ok(write_flash_helper32(0x40000, 0xA5A5A5A5));
+	/* Immediately before the CBI region */
+	zassert_ok(write_flash_helper32(0x3F000 - 4, 0xA5A5A5AA));
+	zassert_ok(read_flash_helper32(0x3F000 - 4, &output));
+	zassert_equal(output, 0xA5A5A5AA, "Got %08x", output);
+
+	/* The CBI region */
+	zassert_ok(read_flash_helper32(0x3F000, &output));
+	zassert_equal(output, 0xFFFFFFFF, "Got %08x", output);
+	zassert_ok(read_flash_helper32(0x40000 - 4, &output));
+	zassert_equal(output, 0xFFFFFFFF, "Got %08x", output);
+
+	CHECK_CONSOLE_CMD("flasherase 0x2F000 0x11000", NULL, EC_SUCCESS);
+
+	/* These should remain untouched */
+	zassert_ok(read_flash_helper32(0x2F000 - 4, &output));
+	zassert_equal(output, 0x5A5A5A5A, "Got %08x", output);
+	zassert_ok(read_flash_helper32(0x40000, &output));
+	zassert_equal(output, 0xA5A5A5A5, "Got %08x", output);
+
+	/* These are within the erase region and should be reset to all FF */
+	zassert_ok(read_flash_helper32(0x2F000, &output));
+	zassert_equal(output, 0xFFFFFFFF, "Got %08x", output);
+	zassert_ok(read_flash_helper32(0x3F000, &output));
+	zassert_equal(output, 0xFFFFFFFF, "Got %08x", output);
+	zassert_ok(read_flash_helper32(0x3F000 - 4, &output));
+	zassert_equal(output, 0xFFFFFFFF, "Got %08x", output);
+	zassert_ok(read_flash_helper32(0x40000 - 4, &output));
+	zassert_equal(output, 0xFFFFFFFF, "Got %08x", output);
+}
+
+ZTEST_USER(flash, test_console_cmd_flash_erase__left)
+{
+	uint32_t output;
+
+	/* Immediately before the region to erase */
+	zassert_ok(write_flash_helper32(0x3E000 - 4, 0x5A5A5A5A));
+	zassert_ok(write_flash_helper32(0x3E000, 0x5A5AAA5A));
+	/* Immediately before the CBI region */
+	zassert_ok(write_flash_helper32(0x3F000 - 4, 0x5A5A5AAA));
+	/* Immediately after the CBI region */
+	zassert_ok(write_flash_helper32(0x40000, 0xA5A5A5A5));
+
+	/* The CBI region */
+	zassert_ok(read_flash_helper32(0x3F000, &output));
+	zassert_equal(output, 0xFFFFFFFF, "Got %08x", output);
+	zassert_ok(read_flash_helper32(0x40000 - 4, &output));
+	zassert_equal(output, 0xFFFFFFFF, "Got %08x", output);
+
+	CHECK_CONSOLE_CMD("flasherase 0x3E000 0x1000", NULL, EC_SUCCESS);
+
+	/* These should remain untouched */
+	zassert_ok(read_flash_helper32(0x3E000 - 4, &output));
+	zassert_equal(output, 0x5A5A5A5A, "Got %08x", output);
+	zassert_ok(read_flash_helper32(0x3F000, &output));
+	zassert_equal(output, 0xFFFFFFFF, "Got %08x", output);
+	zassert_ok(read_flash_helper32(0x40000, &output));
+	zassert_equal(output, 0xA5A5A5A5, "Got %08x", output);
+
+	/* These are within the erase region and should be reset to all FF */
+	zassert_ok(read_flash_helper32(0x3E000, &output));
+	zassert_equal(output, 0xFFFFFFFF, "Got %08x", output);
+	zassert_ok(read_flash_helper32(0x3F000 - 4, &output));
+	zassert_equal(output, 0xFFFFFFFF, "Got %08x", output);
+}
+
+ZTEST_USER(flash, test_console_cmd_flash_erase__right)
+{
+	uint32_t output;
+
+	/* Immediately before the CBI region */
+	zassert_ok(write_flash_helper32(0x3F000 - 4, 0x5A5A5AAA));
+	/* Immediately after the CBI region */
+	zassert_ok(write_flash_helper32(0x40000, 0xA5A5A5A5));
+	zassert_ok(write_flash_helper32(0x41000 - 4, 0x555A5A5A));
+	/* Immediately after the region to erase */
+	zassert_ok(write_flash_helper32(0x41000, 0x5A5A5A5A));
+
+	/* The CBI region */
+	zassert_ok(read_flash_helper32(0x3F000, &output));
+	zassert_equal(output, 0xFFFFFFFF, "Got %08x", output);
+	zassert_ok(read_flash_helper32(0x40000 - 4, &output));
+	zassert_equal(output, 0xFFFFFFFF, "Got %08x", output);
+
+	CHECK_CONSOLE_CMD("flasherase 0x40000 0x1000", NULL, EC_SUCCESS);
+
+	/* These should remain untouched */
+	zassert_ok(read_flash_helper32(0x3F000 - 4, &output));
+	zassert_equal(output, 0x5A5A5AAA, "Got %08x", output);
+	zassert_ok(read_flash_helper32(0x41000, &output));
+	zassert_equal(output, 0x5A5A5A5A, "Got %08x", output);
+
+	/* These are within the erase region and should be reset to all FF */
+	zassert_ok(read_flash_helper32(0x40000, &output));
+	zassert_equal(output, 0xFFFFFFFF, "Got %08x", output);
+	zassert_ok(read_flash_helper32(0x41000 - 4, &output));
+	zassert_equal(output, 0xFFFFFFFF, "Got %08x", output);
+}
+
+ZTEST_USER(flash, test_console_cmd_flash_erase__cbi_overlap_1)
+{
+	uint32_t output;
+
+	/* Immediately before the region to erase */
+	zassert_ok(write_flash_helper32(0x20000 - 4, 0x5A5A5A5A));
+	/* Immediately after the region to erase */
+	zassert_ok(write_flash_helper32(0x50000, 0xA5A5A5A5));
+	/* Immediately before the CBI region */
+	zassert_ok(write_flash_helper32(0x3F000 - 4, 0x555A5A5A));
+	/* Immediately after the CBI region */
+	zassert_ok(write_flash_helper32(0x40000, 0xA5A555A5));
+
+	/* The CBI region */
+	zassert_ok(read_flash_helper32(0x3F000 - 4, &output));
+	zassert_equal(output, 0x555A5A5A, "Got %08x", output);
+	zassert_ok(read_flash_helper32(0x3F000, &output));
+	zassert_equal(output, 0xFFFFFFFF, "Got %08x", output);
+	zassert_ok(read_flash_helper32(0x40000 - 4, &output));
+	zassert_equal(output, 0xFFFFFFFF, "Got %08x", output);
+	zassert_ok(read_flash_helper32(0x40000, &output));
+	zassert_equal(output, 0xA5A555A5, "Got %08x", output);
+
+	CHECK_CONSOLE_CMD("flasherase 0x20000 0x30000", NULL, EC_SUCCESS);
+
+	/* These should remain untouched */
+	zassert_ok(read_flash_helper32(0x20000 - 4, &output));
+	zassert_equal(output, 0x5A5A5A5A, "Got %08x", output);
+	zassert_ok(read_flash_helper32(0x50000, &output));
+	zassert_equal(output, 0xA5A5A5A5, "Got %08x", output);
+
+	/* These are within the erase region and should be reset to all FF */
+	zassert_ok(read_flash_helper32(0x20000, &output));
+	zassert_equal(output, 0xFFFFFFFF, "Got %08x", output);
+	zassert_ok(read_flash_helper32(0x3F000 - 4, &output));
+	zassert_equal(output, 0xFFFFFFFF, "Got %08x", output);
+	zassert_ok(read_flash_helper32(0x40000, &output));
+	zassert_equal(output, 0xFFFFFFFF, "Got %08x", output);
+	zassert_ok(read_flash_helper32(0x50000 - 4, &output));
+	zassert_equal(output, 0xFFFFFFFF, "Got %08x", output);
+}
+
+ZTEST_USER(flash, test_console_cmd_flash_write__cbi_0)
+{
+	uint32_t output;
+
+	/* Immediately before the CBI region */
+	zassert_ok(write_flash_helper32(0x3F000 - 4, 0x555A5A5A));
+	zassert_ok(read_flash_helper32(0x3F000 - 4, &output));
+	zassert_equal(output, 0x555A5A5A, "Got %08x", output);
+	/* Immediately after the CBI region */
+	zassert_ok(write_flash_helper32(0x40000, 0xA5A555A5));
+	zassert_ok(read_flash_helper32(0x40000, &output));
+	zassert_equal(output, 0xA5A555A5, "Got %08x", output);
+
+	/* The CBI region */
+	zassert_ok(read_flash_helper32(0x3F000, &output));
+	zassert_equal(output, 0xFFFFFFFF, "Got %08x", output);
+	zassert_ok(read_flash_helper32(0x40000 - 4, &output));
+	zassert_equal(output, 0xFFFFFFFF, "Got %08x", output);
+
+	zassert_ok(write_flash_helper32(0x10000, 0x5A5A5A5A));
+	zassert_ok(read_flash_helper32(0x10000, &output));
+	zassert_equal(output, 0x5A5A5A5A, "Got %08x", output);
+
+	zassert_ok(write_flash_helper32(0x50000, 0x5AAA5A5A));
+	zassert_ok(read_flash_helper32(0x50000, &output));
+	zassert_equal(output, 0x5AAA5A5A, "Got %08x", output);
+
+	zassert_ok(write_flash_helper32(0x3F000, 0x5A5A5A5A));
+	zassert_ok(read_flash_helper32(0x3F000, &output));
+	zassert_equal(output, 0xFFFFFFFF, "Got %08x", output);
+
+	zassert_ok(write_flash_helper32(0x40000 - 4, 0x5AAA5A5A));
+	zassert_ok(read_flash_helper32(0x40000 - 4, &output));
+	zassert_equal(output, 0xFFFFFFFF, "Got %08x", output);
+}
+
+ZTEST_USER(flash, test_console_cmd_flash_write__cbi_1)
+{
+	uint32_t output;
+
+	/* At the start of CBI region */
+	zassert_ok(write_flash_helper32(0x3F000 - 2, 0x555A5A5A));
+	zassert_ok(read_flash_helper32(0x3F000 - 2, &output));
+	zassert_equal(output, 0xFFFF5A5A, "Got %08x", output);
+
+	/* At the end of CBI region */
+	zassert_ok(write_flash_helper32(0x40000 - 2, 0xA5A555A5));
+	zassert_ok(read_flash_helper32(0x40000 - 2, &output));
+	zassert_equal(output, 0xA5A5FFFF, "Got %08x", output);
+}
+#endif
+
+ZTEST_USER(flash, test_console_cmd_flash_write__flash_locked)
+{
+	/* Force write protection on */
+	zassert_ok(crec_flash_physical_protect_now(1));
+
+	CHECK_CONSOLE_CMD("flashwrite 0x1000 0x1000", NULL,
+			  EC_ERROR_ACCESS_DENIED);
+}
+
+ZTEST_USER(flash, test_console_cmd_flash_write__bad_args)
+{
+	/* No args*/
+	CHECK_CONSOLE_CMD("flashwrite", NULL, EC_ERROR_PARAM_COUNT);
+
+	/* Check for 1 of 2 required args */
+	CHECK_CONSOLE_CMD("flashwrite 0x1000", NULL, EC_ERROR_PARAM_COUNT);
+
+	/* Check for alpha arg instead of number*/
+	CHECK_CONSOLE_CMD("flashwrite xyz 100", NULL, EC_ERROR_PARAM1);
+	CHECK_CONSOLE_CMD("flashwrite 100 xyz", NULL, EC_ERROR_PARAM2);
+}
+
+ZTEST_USER(flash, test_console_cmd_flash_write__too_big)
+{
+	CHECK_CONSOLE_CMD("flashwrite 0x10000 " STRINGIFY(INT_MAX), NULL,
+			  EC_ERROR_INVAL);
+}
+
+ZTEST_USER(flash, test_console_cmd_flash_write__happy)
+{
+	/* Write 4 bytes. The bytes written are autogenerated and just the
+	 * pattern 00 01 02 03.
+	 */
+	CHECK_CONSOLE_CMD("flashwrite 0x10000 4", NULL, EC_SUCCESS);
+
+	uint32_t output;
+	static const uint8_t expected[] = { 0x00, 0x01, 0x02, 0x03 };
+
+	/* Check for pattern */
+	zassert_ok(read_flash_helper32(0x10000, &output));
+	zassert_mem_equal(&output, &expected, sizeof(expected));
+
+	/* Check the space after to ensure it is still erased. */
+	zassert_ok(read_flash_helper32(0x10000 + 4, &output));
+	zassert_equal(output, 0xFFFFFFFF, "Got %08x", output);
+}
+
+ZTEST_USER(flash, test_console_cmd_flash_read__bad_args)
+{
+	/* No args*/
+	CHECK_CONSOLE_CMD("flashread", NULL, EC_ERROR_PARAM_COUNT);
+
+	/* Check for alpha arg instead of number*/
+	CHECK_CONSOLE_CMD("flashread xyz 100", NULL, EC_ERROR_PARAM1);
+	CHECK_CONSOLE_CMD("flashread 100 xyz", NULL, EC_ERROR_PARAM2);
+}
+
+ZTEST_USER(flash, test_console_cmd_flash_read__too_big)
+{
+	CHECK_CONSOLE_CMD("flashread 0x10000 " STRINGIFY(INT_MAX), NULL,
+			  EC_ERROR_INVAL);
+}
+
+ZTEST_USER(flash, test_console_cmd_flash_read__happy_4_bytes)
+{
+	/* Write some bytes to read */
+	zassert_ok(write_flash_helper32(0x10000, sys_cpu_to_be32(0xA1B2C3D4)));
+
+	static const char *expected = "\r\n\r\n"
+				      "00010000: a1 b2 c3 d4\r\n";
+	CHECK_CONSOLE_CMD("flashread 0x10000 4", expected, EC_SUCCESS);
+}
+
+ZTEST_USER(flash, test_console_cmd_flash_read__happy_17_bytes)
+{
+	/* Test 16-byte column wrapping behavior */
+
+	/* Write some bytes to read */
+	zassert_ok(write_flash_helper32(0x10000, sys_cpu_to_be32(0xA1B2C3D4)));
+
+	static const char *expected =
+		"\r\n\r\n"
+		"00010000: a1 b2 c3 d4 ff ff ff ff ff ff ff ff ff ff ff ff\r\n"
+		"00010010: ff\r\n";
+
+	CHECK_CONSOLE_CMD("flashread 0x10000 17", expected, EC_SUCCESS);
+}
+
+/**
+ * @brief Prepare a region of flash for the test_crec_flash_is_erased* tests
+ *
+ * @param offset Offset to write bytes at.
+ * @param size Number of bytes to erase.
+ * @param make_write If true, write an arbitrary byte after erase so the region
+ *                   is no longer fully erased.
+ */
+static void setup_flash_region_helper(uint32_t offset, uint32_t size,
+				      bool make_write)
+{
+	struct ec_params_flash_erase erase_params = {
+		.offset = offset,
+		.size = size,
+	};
+	int rv;
+
+	rv = ec_cmd_flash_erase(NULL, &erase_params);
+	zassert_ok(rv, "Got %d", rv);
+
+	if (make_write) {
+		/* Sized for flash_write header plus one byte of data */
+		uint8_t out_buf[sizeof(struct ec_params_flash_write) +
+				sizeof(uint8_t)];
+
+		struct ec_params_flash_write *write_params =
+			(struct ec_params_flash_write *)out_buf;
+		struct host_cmd_handler_args write_args =
+			BUILD_HOST_COMMAND_SIMPLE(EC_CMD_FLASH_WRITE, 0);
+
+		write_params->offset = offset;
+		write_params->size = 1;
+		write_args.params = write_params;
+		write_args.params_size = sizeof(out_buf);
+
+		/* Write one byte at start of region */
+		out_buf[sizeof(*write_params)] = 0xec;
+
+		zassert_ok(host_command_process(&write_args), NULL);
+	}
+}
+
+ZTEST_USER(flash, test_crec_flash_is_erased__happy)
+{
+	uint32_t offset = 0x10000;
+
+	setup_flash_region_helper(offset, CONFIG_FLASH_ERASE_SIZE, false);
+
+	zassert_true(crec_flash_is_erased(offset, CONFIG_FLASH_ERASE_SIZE),
+		     NULL);
+}
+
+ZTEST_USER(flash, test_crec_flash_is_erased__not_erased)
+{
+	uint32_t offset = 0x10000;
+
+	setup_flash_region_helper(offset, CONFIG_FLASH_ERASE_SIZE, true);
+
+	zassert_true(!crec_flash_is_erased(offset, CONFIG_FLASH_ERASE_SIZE),
+		     NULL);
+}
+
+static void flash_reset(void *data)
+{
+	ARG_UNUSED(data);
+
+	/* Set the GPIO WP_L to default */
+	zassert_ok(gpio_wp_l_set(0));
+
+	/* Reset the protection flags */
+	cros_flash_emul_protect_reset();
+	zassert_ok(crec_flash_physical_protect_now(0));
+
+	/* Tests modify these banks. Erase them. */
+	zassert_ok(crec_flash_erase(0x10000, 0x10000));
+	zassert_ok(crec_flash_erase(0x30000, 0x10000));
+	zassert_ok(crec_flash_erase(0x40000, 0x10000));
+	zassert_ok(crec_flash_erase(0x50000, 0x10000));
+}
+
+ZTEST_SUITE(flash, drivers_predicate_post_main, NULL, flash_reset, flash_reset,
+	    NULL);
diff --git a/zephyr/test/drivers/flash/src/flash_bank_api.c b/zephyr/test/drivers/flash/src/flash_bank_api.c
new file mode 100644
index 0000000000..d12ddfd416
--- /dev/null
+++ b/zephyr/test/drivers/flash/src/flash_bank_api.c
@@ -0,0 +1,102 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "flash.h"
+
+#include <zephyr/ztest.h>
+
+ZTEST_USER(flash, test_bank_size)
+{
+	for (int i = 0; i < crec_flash_total_banks(); i++) {
+		zassert_equal(crec_flash_bank_size(i), CONFIG_FLASH_BANK_SIZE,
+			      "crec_flash_bank_size(%d) = %d", i,
+			      crec_flash_bank_size(i));
+	}
+}
+
+ZTEST_USER(flash, test_bank_erase_size)
+{
+	for (int i = 0; i < crec_flash_total_banks(); i++) {
+		zassert_equal(crec_flash_bank_erase_size(i),
+			      CONFIG_FLASH_ERASE_SIZE,
+			      "crec_flash_bank_erase_size(%d) = %d", i,
+			      crec_flash_bank_erase_size(i));
+	}
+}
+
+ZTEST_USER(flash, test_bank_start_offset)
+{
+	for (int i = 0; i < crec_flash_total_banks(); i++) {
+		zassert_equal(crec_flash_bank_start_offset(i),
+			      CONFIG_FLASH_BANK_SIZE * i,
+			      "crec_flash_bank_start_offset(%d) = %d", i,
+			      crec_flash_bank_start_offset(i));
+	}
+}
+
+ZTEST_USER(flash, test_bank_size_invalid)
+{
+	int invalid_bank = crec_flash_total_banks() + 1;
+
+	zassert_equal(crec_flash_bank_size(invalid_bank), -1, NULL);
+}
+
+ZTEST_USER(flash, test_bank_erase_size_invalid)
+{
+	int invalid_bank = crec_flash_total_banks() + 1;
+
+	zassert_equal(crec_flash_bank_erase_size(invalid_bank), -1, NULL);
+}
+
+ZTEST_USER(flash, test_bank_start_offset_invalid)
+{
+	int invalid_bank = crec_flash_total_banks() + 1;
+
+	zassert_equal(crec_flash_bank_start_offset(invalid_bank), -1, NULL);
+}
+
+ZTEST_USER(flash, test_bank_index_invalid)
+{
+	int invalid_offset = 2 * CONFIG_FLASH_SIZE_BYTES;
+
+	zassert_equal(crec_flash_bank_index(invalid_offset), -1, NULL);
+}
+
+ZTEST_USER(flash, test_bank_count)
+{
+	zassert_equal(crec_flash_bank_count(0, 1), 1, NULL);
+	zassert_equal(crec_flash_bank_count(0, CONFIG_FLASH_BANK_SIZE), 1,
+		      NULL);
+	zassert_equal(crec_flash_bank_count(0, CONFIG_FLASH_BANK_SIZE + 1), 2,
+		      NULL);
+	zassert_equal(crec_flash_bank_count(1, CONFIG_FLASH_BANK_SIZE), 2,
+		      NULL);
+	zassert_equal(crec_flash_bank_count(CONFIG_FLASH_BANK_SIZE - 1, 2), 2,
+		      NULL);
+	zassert_equal(crec_flash_bank_count(0, CONFIG_FLASH_SIZE_BYTES),
+		      crec_flash_total_banks(), NULL);
+}
+
+ZTEST_USER(flash, test_bank_count_invalid)
+{
+	zassert_equal(crec_flash_bank_count(0, 0), -1, NULL);
+	zassert_equal(crec_flash_bank_count(CONFIG_FLASH_SIZE_BYTES + 1, 0), -1,
+		      NULL);
+	zassert_equal(crec_flash_bank_count(0, CONFIG_FLASH_SIZE_BYTES + 1), -1,
+		      NULL);
+	zassert_equal(crec_flash_bank_count(1, CONFIG_FLASH_SIZE_BYTES), -1,
+		      NULL);
+}
+
+ZTEST_USER(flash, test_offset_to_sector_conversion)
+{
+	int offset = 123456;
+	int sector = crec_flash_bank_index(offset);
+	int sector_offset = crec_flash_bank_start_offset(sector);
+	int sector_size = crec_flash_bank_size(sector);
+
+	zassert_between_inclusive(offset, sector_offset,
+				  sector_offset + sector_size, NULL);
+}
diff --git a/zephyr/test/drivers/gpio_unhook/CMakeLists.txt b/zephyr/test/drivers/gpio_unhook/CMakeLists.txt
new file mode 100644
index 0000000000..7487caac88
--- /dev/null
+++ b/zephyr/test/drivers/gpio_unhook/CMakeLists.txt
@@ -0,0 +1,7 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Add source files
+target_sources(app PRIVATE src/un_init_hooks.c)
+target_sources(app PRIVATE src/is_not_ready.c)
diff --git a/zephyr/test/drivers/gpio_unhook/src/is_not_ready.c b/zephyr/test/drivers/gpio_unhook/src/is_not_ready.c
new file mode 100644
index 0000000000..b0b6e627b0
--- /dev/null
+++ b/zephyr/test/drivers/gpio_unhook/src/is_not_ready.c
@@ -0,0 +1,30 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/tcpm/tcpci.h"
+#include "tcpm/tcpm.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/ztest.h>
+
+ZTEST_SUITE(not_ready, drivers_predicate_post_main, NULL, NULL, NULL, NULL);
+
+ZTEST(not_ready, test_bad_tcpc)
+{
+	for (int i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		gpio_flags_t flags;
+
+		zassert_ok(gpio_pin_get_config_dt(&tcpc_config[i].irq_gpio,
+						  &flags),
+			   "error accessing tcpc port %i", i);
+
+		zassert_false(
+			flags & GPIO_INT_ENABLE,
+			"error port %i flag should not be enabled but is 0x%X",
+			i, flags);
+	}
+}
diff --git a/zephyr/test/drivers/gpio_unhook/src/un_init_hooks.c b/zephyr/test/drivers/gpio_unhook/src/un_init_hooks.c
new file mode 100644
index 0000000000..d4c999df38
--- /dev/null
+++ b/zephyr/test/drivers/gpio_unhook/src/un_init_hooks.c
@@ -0,0 +1,15 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/tcpm/tcpci.h"
+#include "hooks.h"
+#include "tcpm/tcpm.h"
+#include "test/drivers/stubs.h"
+
+void tcpc_un_init(void)
+{
+	tcpc_config[USBC_PORT_C0].irq_gpio.port->state->initialized = 0;
+}
+DECLARE_HOOK(HOOK_INIT, tcpc_un_init, HOOK_PRIO_INIT_I2C);
diff --git a/zephyr/test/drivers/host_cmd/CMakeLists.txt b/zephyr/test/drivers/host_cmd/CMakeLists.txt
new file mode 100644
index 0000000000..6e6cf0f48a
--- /dev/null
+++ b/zephyr/test/drivers/host_cmd/CMakeLists.txt
@@ -0,0 +1,32 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_sources(app PRIVATE
+    src/adc.c
+    src/battery_cut_off.c
+    src/battery_display_soc.c
+    src/battery_v2.c
+    src/charge_manager.c
+    src/get_cmd_versions.c
+    src/get_panic_info.c
+    src/get_pd_port_caps.c
+    src/host_command_test_protocol.c
+    src/host_command.c
+    src/host_event_commands.c
+    src/host_event_commands_deprecated.c
+    src/host_request_expected_size.c
+    src/keyboard_mkbp.c
+    src/motion_sense.c
+    src/pd_chip_info.c
+    src/pd_control.c
+    src/pd_log.c
+    src/tablet_mode.c
+    src/usb_pd_control.c
+    src/usb_pd_host_cmd.c
+)
+
+add_subdirectory(
+    ${PLATFORM_EC}/zephyr/test/drivers/mock_panic_output
+    mock_panic_output
+)
diff --git a/zephyr/test/drivers/host_cmd/src/adc.c b/zephyr/test/drivers/host_cmd/src/adc.c
new file mode 100644
index 0000000000..0931f667d3
--- /dev/null
+++ b/zephyr/test/drivers/host_cmd/src/adc.c
@@ -0,0 +1,55 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc.h"
+#include "host_command.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/fff.h>
+#include <zephyr/ztest.h>
+
+FAKE_VALUE_FUNC(int, adc_read_channel, enum adc_channel);
+
+ZTEST(hc_adc, test_normal_path)
+{
+	struct ec_params_adc_read params = {
+		.adc_channel = ADC_TEMP_SENSOR_CHARGER,
+	};
+	struct ec_response_adc_read response;
+	uint16_t ret;
+
+	adc_read_channel_fake.return_val = 123;
+
+	ret = ec_cmd_adc_read(NULL, &params, &response);
+
+	zassert_ok(ret, "Host command returned %u", ret);
+	zassert_equal(1, adc_read_channel_fake.call_count);
+	zassert_equal(123, response.adc_value);
+}
+
+ZTEST(hc_adc, test_bad_ch_number)
+{
+	struct ec_params_adc_read params = {
+		.adc_channel = ADC_CH_COUNT + 1, /* Invalid */
+	};
+	struct ec_response_adc_read response;
+	uint16_t ret;
+
+	ret = ec_cmd_adc_read(NULL, &params, &response);
+
+	zassert_equal(EC_RES_INVALID_PARAM, ret, "Host command returned %u",
+		      ret);
+}
+
+static void reset(void *data)
+{
+	ARG_UNUSED(data);
+
+	RESET_FAKE(adc_read_channel);
+}
+
+ZTEST_SUITE(hc_adc, drivers_predicate_post_main, NULL, reset, reset, NULL);
diff --git a/zephyr/test/drivers/host_cmd/src/battery_cut_off.c b/zephyr/test/drivers/host_cmd/src/battery_cut_off.c
new file mode 100644
index 0000000000..2960823592
--- /dev/null
+++ b/zephyr/test/drivers/host_cmd/src/battery_cut_off.c
@@ -0,0 +1,99 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_smart_battery.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/ztest.h>
+
+struct host_cmd_battery_cut_off_fixture {
+	const struct emul *emul;
+	struct i2c_common_emul_data *i2c_emul;
+};
+
+static void *host_cmd_battery_cut_off_setup(void)
+{
+	static struct host_cmd_battery_cut_off_fixture fixture = {
+		.emul = EMUL_DT_GET(DT_NODELABEL(battery)),
+	};
+
+	fixture.i2c_emul = emul_smart_battery_get_i2c_common_data(fixture.emul);
+
+	return &fixture;
+}
+
+static void host_cmd_battery_cut_off_before(void *f)
+{
+	ARG_UNUSED(f);
+	test_set_battery_level(75);
+}
+
+static void host_cmd_battery_cut_off_after(void *f)
+{
+	struct host_cmd_battery_cut_off_fixture *fixture = f;
+
+	i2c_common_emul_set_write_fail_reg(fixture->i2c_emul,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+	set_ac_enabled(true);
+	hook_notify(HOOK_AC_CHANGE);
+	k_msleep(500);
+}
+
+ZTEST_SUITE(host_cmd_battery_cut_off, drivers_predicate_post_main,
+	    host_cmd_battery_cut_off_setup, host_cmd_battery_cut_off_before,
+	    host_cmd_battery_cut_off_after, NULL);
+
+ZTEST_USER_F(host_cmd_battery_cut_off, test_fail_sb_write)
+{
+	int rv;
+
+	/* Force a failure on the battery i2c write to 0x00 */
+	i2c_common_emul_set_write_fail_reg(fixture->i2c_emul, 0);
+
+	rv = ec_cmd_battery_cut_off(NULL);
+	zassert_equal(EC_RES_ERROR, rv, "Expected 0, but got %d", rv);
+}
+
+ZTEST_USER(host_cmd_battery_cut_off, test_cutoff_battery)
+{
+	int rv;
+
+	rv = ec_cmd_battery_cut_off(NULL);
+	zassert_equal(EC_RES_SUCCESS, rv, "Expected 0, but got %d", rv);
+	zassert_true(battery_is_cut_off(), NULL);
+}
+
+ZTEST_USER(host_cmd_battery_cut_off, test_cutoff_v1)
+{
+	int rv;
+	struct ec_params_battery_cutoff params = {
+		.flags = 0,
+	};
+
+	rv = ec_cmd_battery_cut_off_v1(NULL, &params);
+	zassert_equal(EC_RES_SUCCESS, rv, "Expected 0, but got %d", rv);
+	zassert_true(battery_is_cut_off(), NULL);
+}
+
+ZTEST_USER(host_cmd_battery_cut_off, test_cutoff_at_shutdown)
+{
+	int rv;
+	struct ec_params_battery_cutoff params = {
+		.flags = EC_BATTERY_CUTOFF_FLAG_AT_SHUTDOWN,
+	};
+
+	rv = ec_cmd_battery_cut_off_v1(NULL, &params);
+	zassert_equal(EC_RES_SUCCESS, rv, "Expected 0, but got %d", rv);
+	zassert_false(battery_is_cut_off(), NULL);
+	hook_notify(HOOK_CHIPSET_SHUTDOWN);
+	zassert_true(WAIT_FOR(battery_is_cut_off(), 1500000, k_msleep(250)),
+		     NULL);
+}
diff --git a/zephyr/test/drivers/host_cmd/src/battery_display_soc.c b/zephyr/test/drivers/host_cmd/src/battery_display_soc.c
new file mode 100644
index 0000000000..b158051195
--- /dev/null
+++ b/zephyr/test/drivers/host_cmd/src/battery_display_soc.c
@@ -0,0 +1,31 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "charge_state.h"
+#include "host_command.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/ztest.h>
+
+ZTEST_USER(battery_display_soc, test_happy_path)
+{
+	const uint32_t full_charge_as_tenths =
+		CONFIG_BATT_HOST_FULL_FACTOR * 10;
+	const uint32_t host_shutdown_charge_as_tenths =
+		CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE * 10;
+	struct ec_response_display_soc response;
+	struct host_cmd_handler_args args;
+
+	zassert_ok(ec_cmd_display_soc(&args, &response));
+
+	zassert_equal(args.response_size, sizeof(response));
+	zassert_equal(response.display_soc, charge_get_display_charge());
+	zassert_equal(response.full_factor, full_charge_as_tenths);
+	zassert_equal(response.shutdown_soc, host_shutdown_charge_as_tenths);
+}
+
+ZTEST_SUITE(battery_display_soc, drivers_predicate_post_main, NULL, NULL, NULL,
+	    NULL);
diff --git a/zephyr/test/drivers/host_cmd/src/battery_v2.c b/zephyr/test/drivers/host_cmd/src/battery_v2.c
new file mode 100644
index 0000000000..3b0d54e7ee
--- /dev/null
+++ b/zephyr/test/drivers/host_cmd/src/battery_v2.c
@@ -0,0 +1,145 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "ec_commands.h"
+#include "host_command.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/ztest.h>
+
+ZTEST(host_cmd_battery_v2, test_get_static__invalid_index)
+{
+	struct ec_response_battery_static_info response;
+	struct ec_params_battery_static_info params = {
+		/* Index is out of range */
+		.index = CONFIG_BATTERY_COUNT + 1,
+	};
+	int rv;
+
+	rv = ec_cmd_battery_get_static(NULL, &params, &response);
+	zassert_equal(EC_RES_INVALID_PARAM, rv, "Got %d", rv);
+}
+
+ZTEST(host_cmd_battery_v2, test_get_static__v0)
+{
+	struct ec_params_battery_static_info params = {
+		.index = 0,
+	};
+	struct ec_response_battery_static_info response;
+	int rv;
+
+	rv = ec_cmd_battery_get_static(NULL, &params, &response);
+	zassert_ok(rv, "Got %d", rv);
+
+	/* Validate all of the fields */
+	struct battery_static_info *batt = &battery_static[0];
+
+	zassert_equal(batt->design_capacity, response.design_capacity);
+	zassert_equal(batt->design_voltage, response.design_voltage);
+	zassert_equal(batt->cycle_count, response.cycle_count);
+	zassert_mem_equal(batt->manufacturer_ext, response.manufacturer,
+			  sizeof(response.manufacturer));
+	zassert_mem_equal(batt->model_ext, response.model,
+			  sizeof(response.model));
+	zassert_mem_equal(batt->serial_ext, response.serial,
+			  sizeof(response.serial));
+	zassert_mem_equal(batt->type_ext, response.type, sizeof(response.type));
+}
+
+ZTEST(host_cmd_battery_v2, test_get_static__v1)
+{
+	/* Basically a repeat of the above test, but use the version 1 response
+	 * struct, which allows for longer string fields
+	 */
+
+	struct ec_params_battery_static_info params = {
+		.index = 0,
+	};
+	struct ec_response_battery_static_info_v1 response;
+	int rv;
+
+	rv = ec_cmd_battery_get_static_v1(NULL, &params, &response);
+	zassert_ok(rv, "Got %d", rv);
+
+	/* Validate all of the fields */
+	struct battery_static_info *batt = &battery_static[0];
+
+	zassert_equal(batt->design_capacity, response.design_capacity);
+	zassert_equal(batt->design_voltage, response.design_voltage);
+	zassert_equal(batt->cycle_count, response.cycle_count);
+	zassert_mem_equal(batt->manufacturer_ext, response.manufacturer_ext,
+			  sizeof(response.manufacturer_ext));
+	zassert_mem_equal(batt->model_ext, response.model_ext,
+			  sizeof(response.model_ext));
+	zassert_mem_equal(batt->serial_ext, response.serial_ext,
+			  sizeof(response.serial_ext));
+	zassert_mem_equal(batt->type_ext, response.type_ext,
+			  sizeof(response.type_ext));
+}
+
+ZTEST(host_cmd_battery_v2, test_get_static__v2)
+{
+	/* As above, now using the v2 response for longer strings yet. */
+	struct ec_params_battery_static_info params = {
+		.index = 0,
+	};
+	struct ec_response_battery_static_info_v2 response;
+	int rv;
+
+	struct host_cmd_handler_args args = BUILD_HOST_COMMAND(
+		EC_CMD_BATTERY_GET_STATIC, 2, response, params);
+
+	rv = host_command_process(&args);
+	zassert_ok(rv, "Got %d", rv);
+
+	/* Validate all of the fields */
+	struct battery_static_info *batt = &battery_static[0];
+
+	zassert_equal(batt->design_capacity, response.design_capacity);
+	zassert_equal(batt->design_voltage, response.design_voltage);
+	zassert_equal(batt->cycle_count, response.cycle_count);
+	zassert_mem_equal(batt->manufacturer_ext, response.manufacturer,
+			  sizeof(response.manufacturer));
+	zassert_mem_equal(batt->model_ext, response.device_name,
+			  sizeof(response.device_name));
+	zassert_mem_equal(batt->serial_ext, response.serial,
+			  sizeof(response.serial));
+	zassert_mem_equal(batt->type_ext, response.chemistry,
+			  sizeof(response.chemistry));
+}
+
+ZTEST(host_cmd_battery_v2, test_get_dynamic__invalid_index)
+{
+	struct ec_response_battery_dynamic_info response;
+	struct ec_params_battery_dynamic_info params = {
+		/* Index is out of range */
+		.index = CONFIG_BATTERY_COUNT + 1,
+	};
+	int rv;
+
+	rv = ec_cmd_battery_get_dynamic(NULL, &params, &response);
+	zassert_equal(EC_RES_INVALID_PARAM, rv, "Got %d", rv);
+}
+
+ZTEST(host_cmd_battery_v2, test_get_dynamic)
+{
+	struct ec_response_battery_dynamic_info response;
+	struct ec_params_battery_dynamic_info params = {
+		.index = 0,
+	};
+	int rv;
+
+	rv = ec_cmd_battery_get_dynamic(NULL, &params, &response);
+	zassert_ok(rv, "Got %d", rv);
+
+	/* Validate the data */
+	struct ec_response_battery_dynamic_info *batt = &battery_dynamic[0];
+
+	zassert_mem_equal(batt, &response, sizeof(*batt));
+}
+
+ZTEST_SUITE(host_cmd_battery_v2, drivers_predicate_post_main, NULL, NULL, NULL,
+	    NULL);
diff --git a/zephyr/test/drivers/host_cmd/src/charge_manager.c b/zephyr/test/drivers/host_cmd/src/charge_manager.c
new file mode 100644
index 0000000000..d947b5653f
--- /dev/null
+++ b/zephyr/test/drivers/host_cmd/src/charge_manager.c
@@ -0,0 +1,87 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "host_command.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/ztest.h>
+
+ZTEST_USER(charge_manager, test_port_count)
+{
+	struct ec_response_charge_port_count response = { 0 };
+
+	zassert_ok(ec_cmd_charge_port_count(NULL, &response));
+	zassert_equal(CHARGE_PORT_COUNT, response.port_count,
+		      "Expected %d, but got %d", CHARGE_PORT_COUNT,
+		      response.port_count);
+}
+
+ZTEST_USER(charge_manager, test_port_override__port_out_of_bounds)
+{
+	struct ec_params_charge_port_override params = { 0 };
+
+	params.override_port = OVERRIDE_DONT_CHARGE - 1;
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      ec_cmd_pd_charge_port_override(NULL, &params));
+
+	params.override_port = CHARGE_PORT_COUNT;
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      ec_cmd_pd_charge_port_override(NULL, &params));
+}
+
+ZTEST_USER(charge_manager, test_port_override__0_from_off)
+{
+	struct ec_params_charge_port_override params = { 0 };
+
+	params.override_port = 0;
+	zassert_ok(ec_cmd_pd_charge_port_override(NULL, &params));
+}
+
+ZTEST_USER(charge_manager, test_charge_state_get_debug_params)
+{
+	struct ec_params_charge_state params = {
+		.cmd = CHARGE_STATE_CMD_GET_PARAM,
+	};
+	struct ec_response_charge_state response = { 0 };
+
+	/* Check that the following get commands work on these debug parameters.
+	 * The values being asserted are the default values when nothing is
+	 * plugged in. This should be enough since the test only needs to verify
+	 * that the command gets the current value. Tests that verify the
+	 * charging behavior exist elsewhere (under
+	 * default/src/integration/usbc).
+	 */
+	params.get_param.param = CS_PARAM_DEBUG_CTL_MODE;
+	zassert_ok(ec_cmd_charge_state(NULL, &params, &response));
+	zassert_equal(0, response.get_param.value);
+
+	params.get_param.param = CS_PARAM_DEBUG_MANUAL_CURRENT;
+	zassert_ok(ec_cmd_charge_state(NULL, &params, &response));
+	zassert_equal(0xffffffff, response.get_param.value);
+
+	params.get_param.param = CS_PARAM_DEBUG_MANUAL_VOLTAGE;
+	zassert_ok(ec_cmd_charge_state(NULL, &params, &response));
+	zassert_equal(0xffffffff, response.get_param.value);
+
+	params.get_param.param = CS_PARAM_DEBUG_SEEMS_DEAD;
+	zassert_ok(ec_cmd_charge_state(NULL, &params, &response));
+	zassert_equal(0, response.get_param.value);
+
+	params.get_param.param = CS_PARAM_DEBUG_SEEMS_DISCONNECTED;
+	zassert_ok(ec_cmd_charge_state(NULL, &params, &response));
+	zassert_equal(0, response.get_param.value);
+
+	params.get_param.param = CS_PARAM_DEBUG_BATT_REMOVED;
+	zassert_ok(ec_cmd_charge_state(NULL, &params, &response));
+	zassert_equal(0, response.get_param.value);
+
+	params.get_param.param = CS_PARAM_DEBUG_MAX;
+	zassert_equal(EC_ERROR_INVAL,
+		      ec_cmd_charge_state(NULL, &params, &response));
+}
+
+ZTEST_SUITE(charge_manager, drivers_predicate_post_main, NULL, NULL, NULL,
+	    NULL);
diff --git a/zephyr/test/drivers/host_cmd/src/get_cmd_versions.c b/zephyr/test/drivers/host_cmd/src/get_cmd_versions.c
new file mode 100644
index 0000000000..0a6aba7cbc
--- /dev/null
+++ b/zephyr/test/drivers/host_cmd/src/get_cmd_versions.c
@@ -0,0 +1,52 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "charge_state.h"
+#include "host_command.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/ztest.h>
+
+ZTEST_USER(hc_get_cmd_versions, test_v0__both_versions)
+{
+	struct ec_params_get_cmd_versions params = {
+		.cmd = EC_CMD_GET_CMD_VERSIONS,
+	};
+	struct ec_response_get_cmd_versions response;
+	struct host_cmd_handler_args args;
+
+	zassert_ok(ec_cmd_get_cmd_versions(&args, &params, &response));
+	zassert_equal(args.response_size, sizeof(response));
+	zassert_equal(response.version_mask, EC_VER_MASK(0) | EC_VER_MASK(1));
+}
+
+ZTEST_USER(hc_get_cmd_versions, test_v1__only_v0)
+{
+	struct ec_params_get_cmd_versions_v1 params = {
+		.cmd = EC_CMD_HELLO,
+	};
+	struct ec_response_get_cmd_versions response;
+	struct host_cmd_handler_args args;
+
+	zassert_ok(ec_cmd_get_cmd_versions_v1(&args, &params, &response));
+	zassert_equal(args.response_size, sizeof(response));
+	zassert_equal(response.version_mask, EC_VER_MASK(0));
+}
+
+ZTEST_USER(hc_get_cmd_versions, test_v1__bad_cmd)
+{
+	struct ec_params_get_cmd_versions_v1 params = {
+		/* Non-existent host-command */
+		.cmd = UINT16_MAX,
+	};
+	struct ec_response_get_cmd_versions response;
+
+	zassert_equal(ec_cmd_get_cmd_versions_v1(NULL, &params, &response),
+		      EC_RES_INVALID_PARAM);
+}
+
+ZTEST_SUITE(hc_get_cmd_versions, drivers_predicate_post_main, NULL, NULL, NULL,
+	    NULL);
diff --git a/zephyr/test/drivers/host_cmd/src/get_panic_info.c b/zephyr/test/drivers/host_cmd/src/get_panic_info.c
new file mode 100644
index 0000000000..85d5fdd6f2
--- /dev/null
+++ b/zephyr/test/drivers/host_cmd/src/get_panic_info.c
@@ -0,0 +1,120 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "host_command.h"
+#include "panic.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/ztest.h>
+
+struct host_cmd_get_panic_info_fixture {
+	struct panic_data saved_pdata;
+};
+
+static void *host_cmd_get_panic_info_setup(void)
+{
+	static struct host_cmd_get_panic_info_fixture fixture = { 0 };
+
+	return &fixture;
+}
+
+static void host_cmd_get_panic_info_before(void *f)
+{
+	struct host_cmd_get_panic_info_fixture *fixture = f;
+	struct panic_data *pdata = get_panic_data_write();
+
+	fixture->saved_pdata = *pdata;
+}
+
+static void host_cmd_get_panic_info_after(void *f)
+{
+	struct host_cmd_get_panic_info_fixture *fixture = f;
+	struct panic_data *pdata = get_panic_data_write();
+
+	*pdata = fixture->saved_pdata;
+}
+
+ZTEST_SUITE(host_cmd_get_panic_info, drivers_predicate_post_main,
+	    host_cmd_get_panic_info_setup, host_cmd_get_panic_info_before,
+	    host_cmd_get_panic_info_after, NULL);
+
+ZTEST_USER(host_cmd_get_panic_info, test_get_panic_info)
+{
+	struct panic_data *pdata = get_panic_data_write();
+	struct panic_data response = { 0 };
+	struct host_cmd_handler_args args = BUILD_HOST_COMMAND_RESPONSE(
+		EC_CMD_GET_PANIC_INFO, UINT8_C(0), response);
+
+	pdata->arch = 0;
+	pdata->struct_version = 1;
+	pdata->flags = 2;
+	pdata->reserved = 3;
+	pdata->struct_size = sizeof(struct panic_data);
+	pdata->magic = PANIC_DATA_MAGIC;
+
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_equal(sizeof(struct panic_data), args.response_size, NULL);
+	zassert_equal(0, response.arch, NULL);
+	zassert_equal(1, response.struct_version, NULL);
+	zassert_equal(2, response.flags, NULL);
+	zassert_equal(3, response.reserved, NULL);
+	zassert_equal(sizeof(struct panic_data), response.struct_size, NULL);
+	zassert_equal(PANIC_DATA_MAGIC, response.magic, NULL);
+	zassert_equal(pdata->flags & PANIC_DATA_FLAG_OLD_HOSTCMD,
+		      PANIC_DATA_FLAG_OLD_HOSTCMD, NULL);
+}
+
+ZTEST_USER(host_cmd_get_panic_info, test_get_panic_info_bad_magic)
+{
+	struct panic_data *pdata = get_panic_data_write();
+	struct panic_data expected = { 0 };
+	struct panic_data response = { 0 };
+	struct host_cmd_handler_args args = BUILD_HOST_COMMAND_RESPONSE(
+		EC_CMD_GET_PANIC_INFO, UINT8_C(0), response);
+
+	pdata->magic = PANIC_DATA_MAGIC + 1;
+	zassert_ok(host_command_process(&args), NULL);
+	/* Check that nothing was written to response */
+	zassert_mem_equal(&response, &expected, sizeof(struct panic_data),
+			  NULL);
+}
+
+ZTEST_USER(host_cmd_get_panic_info, test_get_panic_info_size_is_zero)
+{
+	struct panic_data *pdata = get_panic_data_write();
+	struct panic_data expected = { 0 };
+	struct panic_data response = { 0 };
+	struct host_cmd_handler_args args = BUILD_HOST_COMMAND_RESPONSE(
+		EC_CMD_GET_PANIC_INFO, UINT8_C(0), response);
+
+	pdata->magic = PANIC_DATA_MAGIC;
+	pdata->struct_size = 0;
+	zassert_ok(host_command_process(&args), NULL);
+	/* Check that nothing was written to response */
+	zassert_mem_equal(&response, &expected, sizeof(struct panic_data),
+			  NULL);
+}
+
+ZTEST_USER(host_cmd_get_panic_info, test_get_panic_info_truncate)
+{
+	struct panic_data *pdata = get_panic_data_write();
+	struct panic_data response = { 0 };
+	struct host_cmd_handler_args args = BUILD_HOST_COMMAND_RESPONSE(
+		EC_CMD_GET_PANIC_INFO, UINT8_C(0), response);
+
+	/* Panic data is bigger than max response size, should be truncated */
+	args.response_max = sizeof(struct panic_data) - 2;
+
+	pdata->flags = 0;
+	pdata->magic = PANIC_DATA_MAGIC;
+	pdata->struct_size = sizeof(struct panic_data);
+
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_equal(sizeof(struct panic_data) - 2, args.response_size, NULL);
+	/* Truncation flag must be set */
+	zassert_equal(response.flags & PANIC_DATA_FLAG_TRUNCATED,
+		      PANIC_DATA_FLAG_TRUNCATED, NULL);
+	zassert_equal(sizeof(struct panic_data), response.struct_size, NULL);
+}
diff --git a/zephyr/test/drivers/host_cmd/src/get_pd_port_caps.c b/zephyr/test/drivers/host_cmd/src/get_pd_port_caps.c
new file mode 100644
index 0000000000..3071749821
--- /dev/null
+++ b/zephyr/test/drivers/host_cmd/src/get_pd_port_caps.c
@@ -0,0 +1,55 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "ec_commands.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+ZTEST_USER(host_cmd_get_pd_port_caps, test_good_index)
+{
+	struct ec_params_get_pd_port_caps params = { .port = 0 };
+	struct ec_response_get_pd_port_caps response;
+
+	zassert_ok(ec_cmd_get_pd_port_caps(NULL, &params, &response),
+		   "Failed to process get_pd_port_caps for port %d",
+		   params.port);
+
+	/* Verify standard Chromebook responses for these fields */
+	zassert_equal(response.pd_power_role_cap, EC_PD_POWER_ROLE_DUAL,
+		      "Bad dual role");
+	zassert_equal(response.pd_try_power_role_cap,
+		      EC_PD_TRY_POWER_ROLE_SOURCE, "Bad try role");
+	zassert_equal(response.pd_data_role_cap, EC_PD_DATA_ROLE_DUAL,
+		      "Bad data role");
+	zassert_equal(response.pd_port_location, EC_PD_PORT_LOCATION_UNKNOWN,
+		      "Unexpected port location");
+}
+
+ZTEST_USER(host_cmd_get_pd_port_caps, test_bad_index)
+{
+	struct ec_params_get_pd_port_caps params = { .port = 32 };
+	struct ec_response_get_pd_port_caps response;
+
+	zassert_equal(ec_cmd_get_pd_port_caps(NULL, &params, &response),
+		      EC_RES_INVALID_PARAM,
+		      "Failed to fail get_pd_port_caps for port %d",
+		      params.port);
+}
+
+static void host_cmd_get_pd_port_caps_begin(void *data)
+{
+	ARG_UNUSED(data);
+
+	/* Assume we have at least one USB-C port */
+	zassert_true(board_get_usb_pd_port_count() > 0,
+		     "Insufficient TCPCs found");
+}
+
+ZTEST_SUITE(host_cmd_get_pd_port_caps, drivers_predicate_post_main, NULL,
+	    host_cmd_get_pd_port_caps_begin, NULL, NULL);
diff --git a/zephyr/test/drivers/host_cmd/src/host_command.c b/zephyr/test/drivers/host_cmd/src/host_command.c
new file mode 100644
index 0000000000..7118fbaab1
--- /dev/null
+++ b/zephyr/test/drivers/host_cmd/src/host_command.c
@@ -0,0 +1,88 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+#include "host_command.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/ztest.h>
+
+ZTEST(host_cmd_host_commands, test_get_command_versions__v1)
+{
+	struct ec_response_get_cmd_versions response;
+	struct ec_params_get_cmd_versions_v1 params = {
+		.cmd = EC_CMD_GET_CMD_VERSIONS
+	};
+	int rv;
+
+	rv = ec_cmd_get_cmd_versions_v1(NULL, &params, &response);
+
+	zassert_ok(rv, "Got %d", rv);
+	zassert_equal(EC_VER_MASK(0) | EC_VER_MASK(1), response.version_mask);
+}
+
+ZTEST(host_cmd_host_commands, test_get_command_versions__invalid_cmd)
+{
+	struct ec_response_get_cmd_versions response;
+	struct ec_params_get_cmd_versions_v1 params = {
+		/* Host command doesn't exist */
+		.cmd = UINT16_MAX,
+	};
+	int rv;
+
+	rv = ec_cmd_get_cmd_versions_v1(NULL, &params, &response);
+
+	zassert_equal(EC_RES_INVALID_PARAM, rv, "Got %d", rv);
+}
+
+ZTEST(host_cmd_host_commands, test_get_comms_status)
+{
+	struct ec_response_get_comms_status response;
+	int rv;
+
+	rv = ec_cmd_get_comms_status(NULL, &response);
+
+	zassert_ok(rv, "Got %d", rv);
+
+	/* Unit test host commands are processed synchronously, so always expect
+	 * the EC to be not busy processing another.
+	 */
+	zassert_false(response.flags);
+}
+
+ZTEST(host_cmd_host_commands, test_resend_response)
+{
+	struct host_cmd_handler_args args =
+		(struct host_cmd_handler_args)BUILD_HOST_COMMAND_SIMPLE(
+			EC_CMD_RESEND_RESPONSE, 0);
+	int rv;
+
+	rv = host_command_process(&args);
+	zassert_ok(rv);
+
+	/* The way we trigger host commands in tests doesn't cause results to
+	 * get saved (it happens outside of host_command_process), so we cannot
+	 * verify the resent response itself.
+	 *
+	 * TODO: test at least one host command through the ESPI interface.
+	 */
+}
+
+ZTEST(host_cmd_host_commands, test_get_proto_version)
+{
+	struct ec_response_proto_version response;
+	int rv;
+
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_RESPONSE(EC_CMD_PROTO_VERSION, 0, response);
+
+	rv = host_command_process(&args);
+
+	zassert_ok(rv, "Got %d", rv);
+	zassert_equal(EC_PROTO_VERSION, response.version);
+}
+
+ZTEST_SUITE(host_cmd_host_commands, drivers_predicate_post_main, NULL, NULL,
+	    NULL, NULL);
diff --git a/zephyr/test/drivers/host_cmd/src/host_command_test_protocol.c b/zephyr/test/drivers/host_cmd/src/host_command_test_protocol.c
new file mode 100644
index 0000000000..cdabe3044d
--- /dev/null
+++ b/zephyr/test/drivers/host_cmd/src/host_command_test_protocol.c
@@ -0,0 +1,62 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "host_command.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/ztest.h>
+
+ZTEST_USER(hc_test_protocol, test_echo_max_buffer_size)
+{
+	struct ec_params_test_protocol params = {
+		/* Actual return length will only be sizeof(response) */
+		.ret_len = UINT32_MAX,
+		.buf = { 0 },
+		.ec_result = EC_SUCCESS,
+	};
+	struct ec_response_test_protocol response;
+	struct host_cmd_handler_args args;
+
+	/* Set first and last bytes of input array */
+	params.buf[0] = 0x1;
+	params.buf[ARRAY_SIZE(params.buf) - 1] = 0x2;
+
+	zassert_ok(ec_cmd_test_protocol(&args, &params, &response));
+	zassert_equal(args.response_size, sizeof(response));
+
+	/* Check contents are echoed back in response */
+	zassert_mem_equal(params.buf, response.buf, sizeof(params.buf));
+}
+
+ZTEST_USER(hc_test_protocol, test_echo_min_buffer_size_failing_command)
+{
+	struct ec_params_test_protocol params = {
+		/* Don't want to have anything echoed back to us */
+		.ret_len = 0,
+		.buf = { 0 },
+		.ec_result = EC_ERROR_TRY_AGAIN,
+	};
+	struct ec_response_test_protocol response;
+	struct host_cmd_handler_args args;
+
+	/*
+	 * Set first and last bytes of input array, neither will be written to
+	 * response
+	 */
+	params.buf[0] = 0x1;
+	params.buf[ARRAY_SIZE(params.buf) - 1] = 0x2;
+
+	zassert_equal(ec_cmd_test_protocol(&args, &params, &response),
+		      params.ec_result);
+	zassert_equal(args.response_size, params.ret_len);
+
+	/* Check contents were never echoed back as intended */
+	zassert_not_equal(response.buf[0], params.buf[0]);
+	zassert_not_equal(response.buf[ARRAY_SIZE(response.buf) - 1],
+			  params.buf[ARRAY_SIZE(params.buf) - 1]);
+}
+
+ZTEST_SUITE(hc_test_protocol, drivers_predicate_post_main, NULL, NULL, NULL,
+	    NULL);
diff --git a/zephyr/test/drivers/host_cmd/src/host_event_commands.c b/zephyr/test/drivers/host_cmd/src/host_event_commands.c
new file mode 100644
index 0000000000..2367fcf451
--- /dev/null
+++ b/zephyr/test/drivers/host_cmd/src/host_event_commands.c
@@ -0,0 +1,225 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "include/lpc.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/ztest.h>
+
+struct host_cmd_host_event_commands_fixture {
+	struct host_events_ctx ctx;
+};
+
+static void *host_cmd_host_event_commands_setup(void)
+{
+	static struct host_cmd_host_event_commands_fixture fixture = { 0 };
+
+	return &fixture;
+}
+
+static void host_cmd_host_event_commands_before(void *fixture)
+{
+	struct host_cmd_host_event_commands_fixture *f = fixture;
+
+	host_events_save(&f->ctx);
+}
+
+static void host_cmd_host_event_commands_after(void *fixture)
+{
+	struct host_cmd_host_event_commands_fixture *f = fixture;
+
+	host_events_restore(&f->ctx);
+}
+
+ZTEST_SUITE(host_cmd_host_event_commands, drivers_predicate_post_main,
+	    host_cmd_host_event_commands_setup,
+	    host_cmd_host_event_commands_before,
+	    host_cmd_host_event_commands_after, NULL);
+
+/**
+ * @brief TestPurpose: Verify EC_CMD_HOST_EVENT invalid host command.
+ */
+ZTEST_USER(host_cmd_host_event_commands, test_host_event_invalid_cmd)
+{
+	enum ec_status ret_val;
+	struct ec_response_host_event result = { 0 };
+
+	ret_val = host_cmd_host_event(0xFF, 0, &result);
+
+	zassert_equal(ret_val, EC_RES_INVALID_PARAM, "Expected=%d, returned=%d",
+		      EC_RES_INVALID_PARAM, ret_val);
+}
+
+/**
+ * @brief TestPurpose: Verify EC_CMD_HOST_EVENT get host command.
+ */
+ZTEST_USER(host_cmd_host_event_commands, test_host_event_get_cmd)
+{
+	enum ec_status ret_val;
+	struct ec_response_host_event result = { 0 };
+	struct {
+		uint8_t mask;
+		enum ec_status result;
+	} event_get[] = {
+		{ EC_HOST_EVENT_MAIN, EC_RES_ACCESS_DENIED },
+		{ EC_HOST_EVENT_B, EC_RES_SUCCESS },
+#ifdef CONFIG_HOSTCMD_X86
+		{ EC_HOST_EVENT_SCI_MASK, EC_RES_SUCCESS },
+		{ EC_HOST_EVENT_SMI_MASK, EC_RES_SUCCESS },
+		{ EC_HOST_EVENT_ALWAYS_REPORT_MASK, EC_RES_SUCCESS },
+		{ EC_HOST_EVENT_ACTIVE_WAKE_MASK, EC_RES_SUCCESS },
+#ifdef CONFIG_POWER_S0IX
+		{ EC_HOST_EVENT_LAZY_WAKE_MASK_S0IX, EC_RES_SUCCESS },
+#endif /* CONFIG_POWER_S0IX */
+		{ EC_HOST_EVENT_LAZY_WAKE_MASK_S3, EC_RES_SUCCESS },
+		{ EC_HOST_EVENT_LAZY_WAKE_MASK_S5, EC_RES_SUCCESS },
+#endif /* CONFIG_HOSTCMD_X86 */
+		{ 0xFF, EC_RES_INVALID_PARAM },
+	};
+
+	for (int i = 0; i < ARRAY_SIZE(event_get); i++) {
+		ret_val = host_cmd_host_event(EC_HOST_EVENT_GET,
+					      event_get[i].mask, &result);
+		zassert_equal(ret_val, event_get[i].result,
+			      "[%d] Expected=%d, returned=%d", i,
+			      event_get[i].result, ret_val);
+	}
+}
+
+/**
+ * @brief TestPurpose: Verify EC_CMD_HOST_EVENT set host command.
+ */
+ZTEST_USER(host_cmd_host_event_commands, test_host_event_set_cmd)
+{
+	enum ec_status ret_val;
+	struct ec_response_host_event result = { 0 };
+	struct {
+		uint8_t mask;
+		enum ec_status result;
+	} event_set[] = {
+		{ EC_HOST_EVENT_MAIN, EC_RES_ACCESS_DENIED },
+		{ EC_HOST_EVENT_B, EC_RES_ACCESS_DENIED },
+#ifdef CONFIG_HOSTCMD_X86
+		{ EC_HOST_EVENT_SCI_MASK, EC_RES_SUCCESS },
+		{ EC_HOST_EVENT_SMI_MASK, EC_RES_SUCCESS },
+		{ EC_HOST_EVENT_ALWAYS_REPORT_MASK, EC_RES_SUCCESS },
+		{ EC_HOST_EVENT_ACTIVE_WAKE_MASK, EC_RES_SUCCESS },
+#ifdef CONFIG_POWER_S0IX
+		{ EC_HOST_EVENT_LAZY_WAKE_MASK_S0IX, EC_RES_SUCCESS },
+#endif /* CONFIG_POWER_S0IX */
+		{ EC_HOST_EVENT_LAZY_WAKE_MASK_S3, EC_RES_SUCCESS },
+		{ EC_HOST_EVENT_LAZY_WAKE_MASK_S5, EC_RES_SUCCESS },
+#endif /* CONFIG_HOSTCMD_X86 */
+		{ 0xFF, EC_RES_INVALID_PARAM },
+	};
+
+	for (int i = 0; i < ARRAY_SIZE(event_set); i++) {
+		ret_val = host_cmd_host_event(EC_HOST_EVENT_SET,
+					      event_set[i].mask, &result);
+		zassert_equal(ret_val, event_set[i].result,
+			      "[%d] Expected=%d, returned=%d", i,
+			      event_set[i].result, ret_val);
+	}
+}
+
+/**
+ * @brief TestPurpose: Verify EC_CMD_HOST_EVENT clear host command.
+ */
+ZTEST_USER(host_cmd_host_event_commands, test_host_event_clear_cmd)
+{
+	enum ec_status ret_val;
+	struct ec_response_host_event result = { 0 };
+	struct {
+		uint8_t mask;
+		enum ec_status result;
+	} event_set[] = {
+		{ EC_HOST_EVENT_MAIN, EC_RES_SUCCESS },
+		{ EC_HOST_EVENT_B, EC_RES_SUCCESS },
+#ifdef CONFIG_HOSTCMD_X86
+		{ EC_HOST_EVENT_SCI_MASK, EC_RES_ACCESS_DENIED },
+		{ EC_HOST_EVENT_SMI_MASK, EC_RES_ACCESS_DENIED },
+		{ EC_HOST_EVENT_ALWAYS_REPORT_MASK, EC_RES_ACCESS_DENIED },
+		{ EC_HOST_EVENT_ACTIVE_WAKE_MASK, EC_RES_ACCESS_DENIED },
+#ifdef CONFIG_POWER_S0IX
+		{ EC_HOST_EVENT_LAZY_WAKE_MASK_S0IX, EC_RES_ACCESS_DENIED },
+#endif /* CONFIG_POWER_S0IX */
+		{ EC_HOST_EVENT_LAZY_WAKE_MASK_S3, EC_RES_ACCESS_DENIED },
+		{ EC_HOST_EVENT_LAZY_WAKE_MASK_S5, EC_RES_ACCESS_DENIED },
+#endif /* CONFIG_HOSTCMD_X86 */
+		{ 0xFF, EC_RES_INVALID_PARAM },
+	};
+
+	for (int i = 0; i < ARRAY_SIZE(event_set); i++) {
+		ret_val = host_cmd_host_event(EC_HOST_EVENT_CLEAR,
+					      event_set[i].mask, &result);
+		zassert_equal(ret_val, event_set[i].result,
+			      "Expected [%d] result=%d, returned=%d", i,
+			      event_set[i].result, ret_val);
+	}
+}
+
+/**
+ * @brief TestPurpose: Verify EC_CMD_HOST_EVENT_CLEAR clear host command.
+ */
+ZTEST_USER(host_cmd_host_event_commands, test_host_event_clear__cmd)
+{
+	enum ec_status ret_val;
+	host_event_t events;
+	host_event_t mask = EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY);
+	host_event_t lpc_event_mask;
+
+	lpc_event_mask = lpc_get_host_event_mask(LPC_HOST_EVENT_SMI);
+	lpc_set_host_event_mask(LPC_HOST_EVENT_SMI, lpc_event_mask | mask);
+
+	host_set_single_event(EC_HOST_EVENT_KEYBOARD_RECOVERY);
+	events = host_get_events();
+
+	zassert_true(events & mask, "events=0x%X", events);
+
+	ret_val = ec_cmd_host_event_clear(NULL,
+					  &(struct ec_params_host_event_mask){
+						  .mask = mask,
+					  });
+
+	zassert_equal(ret_val, EC_RES_SUCCESS, "Expected %d, returned %d",
+		      EC_RES_SUCCESS, ret_val);
+
+	events = host_get_events();
+	zassert_false(events & mask, "events=0x%X", events);
+}
+
+/**
+ * @brief TestPurpose: Verify EC_CMD_HOST_EVENT_CLEAR_B clear host command.
+ */
+ZTEST_USER(host_cmd_host_event_commands, test_host_event_clear_b_cmd)
+{
+	enum ec_status ret_val;
+	host_event_t events_b;
+	host_event_t mask = EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY);
+	host_event_t lpc_event_mask;
+	struct ec_response_host_event result = { 0 };
+
+	lpc_event_mask = lpc_get_host_event_mask(LPC_HOST_EVENT_SMI);
+	lpc_set_host_event_mask(LPC_HOST_EVENT_SMI, lpc_event_mask | mask);
+
+	host_set_single_event(EC_HOST_EVENT_KEYBOARD_RECOVERY);
+
+	host_cmd_host_event(EC_HOST_EVENT_GET, EC_HOST_EVENT_B, &result);
+	events_b = result.value;
+	zassert_true(events_b & mask, "events_b=0x%X", events_b);
+
+	ret_val = ec_cmd_host_event_clear_b(NULL,
+					    &(struct ec_params_host_event_mask){
+						    .mask = mask,
+					    });
+
+	zassert_equal(ret_val, EC_RES_SUCCESS, "Expected %d, returned %d",
+		      EC_RES_SUCCESS, ret_val);
+
+	host_cmd_host_event(EC_HOST_EVENT_GET, EC_HOST_EVENT_B, &result);
+	events_b = result.value;
+	zassert_false(events_b & mask, "events_b=0x%X", events_b);
+}
diff --git a/zephyr/test/drivers/host_cmd/src/host_event_commands_deprecated.c b/zephyr/test/drivers/host_cmd/src/host_event_commands_deprecated.c
new file mode 100644
index 0000000000..3183636c44
--- /dev/null
+++ b/zephyr/test/drivers/host_cmd/src/host_event_commands_deprecated.c
@@ -0,0 +1,227 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Tests for deprecated EC_CMD_HOST_EVENT_* commands */
+
+#include "include/lpc.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/ztest.h>
+
+#define HOST_EVENT_TEST_MASK_VAL EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)
+
+static enum ec_status host_event_set_wake_mask_helper(uint32_t mask)
+{
+	struct ec_params_host_event_mask params = { .mask = mask };
+
+	return ec_cmd_host_event_set_wake_mask(NULL, &params);
+}
+
+/**
+ * @brief TestPurpose: Verify EC_CMD_HOST_EVENT_GET_WAKE_MASK host command.
+ */
+ZTEST_USER(host_cmd_host_event_commands, test_host_event_get_wake_mask)
+{
+	enum ec_status rv;
+	struct ec_response_host_event_mask result = { 0 };
+
+	rv = ec_cmd_host_event_get_wake_mask(NULL, &result);
+	if (IS_ENABLED(CONFIG_HOSTCMD_X86)) {
+		zassert_ok(rv, "Expected %d, returned %d", EC_RES_SUCCESS, rv);
+	} else {
+		zassert_equal(EC_RES_INVALID_COMMAND, rv,
+			      "Expected %d, returned %d",
+			      EC_RES_INVALID_COMMAND, rv);
+	}
+}
+
+/**
+ * @brief TestPurpose: Verify EC_CMD_HOST_EVENT_SET_WAKE_MASK host command.
+ */
+ZTEST_USER(host_cmd_host_event_commands, test_host_event_set_wake_mask)
+{
+	enum ec_status rv;
+	struct ec_response_host_event_mask result = { 0 };
+
+	/* Read the current mask */
+	rv = ec_cmd_host_event_get_wake_mask(NULL, &result);
+	if (IS_ENABLED(CONFIG_HOSTCMD_X86)) {
+		zassert_ok(rv, "Expected %d, returned %d", EC_RES_SUCCESS, rv);
+	} else {
+		zassert_equal(EC_RES_INVALID_COMMAND, rv,
+			      "Expected %d, returned %d",
+			      EC_RES_INVALID_COMMAND, rv);
+		return;
+	}
+
+	/* Default mask is expected to be clear */
+	zassert_false(result.mask, "Default host event wake mask is not clear");
+
+	zassert_ok(host_event_set_wake_mask_helper(HOST_EVENT_TEST_MASK_VAL));
+
+	/* Verify the mask changed */
+	ec_cmd_host_event_get_wake_mask(NULL, &result);
+
+	zassert_equal(result.mask, HOST_EVENT_TEST_MASK_VAL,
+		      "Expected wake mask 0x%08x, returned mask 0x%08x",
+		      HOST_EVENT_TEST_MASK_VAL, result.mask);
+
+	/* Clean up the mask */
+	zassert_ok(host_event_set_wake_mask_helper(0));
+}
+
+static enum ec_status host_event_set_smi_mask_helper(uint32_t mask)
+{
+	struct ec_params_host_event_mask params = { .mask = mask };
+
+	return ec_cmd_host_event_set_smi_mask(NULL, &params);
+}
+
+/**
+ * @brief TestPurpose: Verify EC_CMD_HOST_EVENT_GET_SMI_MASK host command.
+ */
+ZTEST_USER(host_cmd_host_event_commands, test_host_event_get_smi_mask)
+{
+	enum ec_status rv;
+	struct ec_response_host_event_mask result = { 0 };
+
+	rv = ec_cmd_host_event_get_smi_mask(NULL, &result);
+	if (IS_ENABLED(CONFIG_HOSTCMD_X86)) {
+		zassert_ok(rv, "Expected %d, returned %d", EC_RES_SUCCESS, rv);
+	} else {
+		zassert_equal(EC_RES_INVALID_COMMAND, rv,
+			      "Expected %d, returned %d",
+			      EC_RES_INVALID_COMMAND, rv);
+		return;
+	}
+}
+
+/**
+ * @brief TestPurpose: Verify EC_CMD_HOST_EVENT_SET_SMI_MASK host command.
+ */
+ZTEST_USER(host_cmd_host_event_commands, test_host_event_set_smi_mask)
+{
+	enum ec_status rv;
+	struct ec_response_host_event_mask result = { 0 };
+
+	/* Read the current mask */
+	rv = ec_cmd_host_event_get_smi_mask(NULL, &result);
+	if (IS_ENABLED(CONFIG_HOSTCMD_X86)) {
+		zassert_ok(rv, "Expected %d, returned %d", EC_RES_SUCCESS, rv);
+	} else {
+		zassert_equal(EC_RES_INVALID_COMMAND, rv,
+			      "Expected %d, returned %d",
+			      EC_RES_INVALID_COMMAND, rv);
+		return;
+	}
+
+	/* Default mask is expected to be clear */
+	zassert_false(result.mask, "Default host event SMI mask is not clear");
+
+	zassert_ok(host_event_set_smi_mask_helper(HOST_EVENT_TEST_MASK_VAL));
+
+	/* Verify the mask changed */
+	zassert_ok(ec_cmd_host_event_get_smi_mask(NULL, &result));
+
+	zassert_equal(result.mask, HOST_EVENT_TEST_MASK_VAL,
+		      "Expected SMI mask 0x%08x, returned mask 0x%08x",
+		      HOST_EVENT_TEST_MASK_VAL, result.mask);
+
+	/* Clean up the mask */
+	zassert_ok(host_event_set_smi_mask_helper(0));
+}
+
+static enum ec_status
+host_event_get_b_helper(struct ec_response_host_event_mask *r)
+{
+	return ec_cmd_host_event_get_b(NULL, r);
+}
+
+/**
+ * @brief TestPurpose: Verify EC_CMD_HOST_EVENT_GET_B host command.
+ */
+ZTEST_USER(host_cmd_host_event_commands, test_host_event_get_b)
+{
+	enum ec_status rv;
+	struct ec_response_host_event_mask result = { 0 };
+
+	rv = host_event_get_b_helper(&result);
+	if (IS_ENABLED(CONFIG_HOSTCMD_X86)) {
+		zassert_ok(rv, "Expected %d, returned %d", EC_RES_SUCCESS, rv);
+	} else {
+		zassert_equal(EC_RES_INVALID_COMMAND, rv,
+			      "Expected %d, returned %d",
+			      EC_RES_INVALID_COMMAND, rv);
+		return;
+	}
+}
+
+static enum ec_status
+host_event_get_sci_mask_helper(struct ec_response_host_event_mask *r)
+{
+	return ec_cmd_host_event_get_sci_mask(NULL, r);
+}
+
+static enum ec_status host_event_set_sci_mask_helper(uint32_t mask)
+{
+	struct ec_params_host_event_mask params = { .mask = mask };
+
+	return ec_cmd_host_event_set_sci_mask(NULL, &params);
+}
+
+/**
+ * @brief TestPurpose: Verify EC_CMD_HOST_EVENT_GET_SCI_MASK host command.
+ */
+ZTEST_USER(host_cmd_host_event_commands, test_host_event_get_sci_mask)
+{
+	enum ec_status rv;
+	struct ec_response_host_event_mask result = { 0 };
+
+	rv = host_event_get_sci_mask_helper(&result);
+	if (IS_ENABLED(CONFIG_HOSTCMD_X86)) {
+		zassert_ok(rv, "Expected %d, returned %d", EC_RES_SUCCESS, rv);
+	} else {
+		zassert_equal(EC_RES_INVALID_COMMAND, rv,
+			      "Expected %d, returned %d",
+			      EC_RES_INVALID_COMMAND, rv);
+		return;
+	}
+}
+
+/**
+ * @brief TestPurpose: Verify EC_CMD_HOST_EVENT_SET_SCI_MASK host command.
+ */
+ZTEST_USER(host_cmd_host_event_commands, test_host_event_set_sci_mask)
+{
+	enum ec_status rv;
+	struct ec_response_host_event_mask result = { 0 };
+
+	/* Read the current mask */
+	rv = host_event_get_sci_mask_helper(&result);
+	if (IS_ENABLED(CONFIG_HOSTCMD_X86)) {
+		zassert_ok(rv, "Expected %d, returned %d", EC_RES_SUCCESS, rv);
+	} else {
+		zassert_equal(EC_RES_INVALID_COMMAND, rv,
+			      "Expected %d, returned %d",
+			      EC_RES_INVALID_COMMAND, rv);
+		return;
+	}
+
+	/* Default mask is expected to be clear */
+	zassert_false(result.mask, "Default host event SCI mask is not clear");
+
+	zassert_ok(host_event_set_sci_mask_helper(HOST_EVENT_TEST_MASK_VAL));
+
+	/* Verify the mask changed */
+	zassert_ok(host_event_get_sci_mask_helper(&result));
+
+	zassert_equal(result.mask, HOST_EVENT_TEST_MASK_VAL,
+		      "Expected SCI mask 0x%08x, returned mask 0x%08x",
+		      HOST_EVENT_TEST_MASK_VAL, result.mask);
+
+	/* Clean up the mask */
+	zassert_ok(host_event_set_sci_mask_helper(0));
+}
diff --git a/zephyr/test/drivers/host_cmd/src/host_request_expected_size.c b/zephyr/test/drivers/host_cmd/src/host_request_expected_size.c
new file mode 100644
index 0000000000..19fdd9ea4a
--- /dev/null
+++ b/zephyr/test/drivers/host_cmd/src/host_request_expected_size.c
@@ -0,0 +1,51 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "host_command.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/ztest.h>
+
+ZTEST(host_request_expected_size, test_mismatched_host_request_version)
+{
+	const struct ec_host_request request = {
+		/* Make version mismatch */
+		.struct_version = EC_HOST_REQUEST_VERSION + 1,
+	};
+	int ret = host_request_expected_size(&request);
+
+	zassert_equal(ret, 0);
+}
+
+ZTEST(host_request_expected_size, test_nonzero_reserved_bytes)
+{
+	const struct ec_host_request request = {
+		/* Make version match */
+		.struct_version = EC_HOST_REQUEST_VERSION,
+		/* Set lsb to reserved bytes */
+		.reserved = 1,
+	};
+	int ret = host_request_expected_size(&request);
+
+	zassert_equal(ret, 0);
+}
+
+ZTEST(host_request_expected_size, test_data_len_added_to_response_size)
+{
+	const struct ec_host_request request = {
+		/* Make version match */
+		.struct_version = EC_HOST_REQUEST_VERSION,
+		/* Set reserved bytes to 0 (required) */
+		.reserved = 0,
+		/* Test data length max value to see changes in M/LSB */
+		.data_len = UINT16_MAX,
+	};
+	int ret = host_request_expected_size(&request);
+
+	zassert_equal(ret, sizeof(request) + request.data_len);
+}
+
+ZTEST_SUITE(host_request_expected_size, drivers_predicate_post_main, NULL, NULL,
+	    NULL, NULL);
diff --git a/zephyr/test/drivers/host_cmd/src/keyboard_mkbp.c b/zephyr/test/drivers/host_cmd/src/keyboard_mkbp.c
new file mode 100644
index 0000000000..7c1d3a8500
--- /dev/null
+++ b/zephyr/test/drivers/host_cmd/src/keyboard_mkbp.c
@@ -0,0 +1,75 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "include/keyboard_mkbp.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/ztest.h>
+
+struct keyboard_mkbp_commands_fixture {
+	struct ec_mkbp_config config;
+};
+
+static void *keyboard_mkbp_setup(void)
+{
+	static struct keyboard_mkbp_commands_fixture fixture = { 0 };
+
+	return &fixture;
+}
+
+static void keyboard_mkbp_before(void *fixture)
+{
+	struct keyboard_mkbp_commands_fixture *f = fixture;
+
+	get_keyscan_config(&f->config);
+}
+
+static void keyboard_mkbp_after(void *fixture)
+{
+	struct keyboard_mkbp_commands_fixture *f = fixture;
+	struct ec_params_mkbp_set_config req = { 0 };
+
+	req.config = f->config;
+	ec_cmd_mkbp_set_config(NULL, &req);
+}
+
+ZTEST_SUITE(keyboard_mkbp_commands, drivers_predicate_post_main,
+	    keyboard_mkbp_setup, keyboard_mkbp_before, keyboard_mkbp_after,
+	    NULL);
+
+/**
+ * @brief TestPurpose: Verify EC_CMD_MKBP_GET_CONFIG host command.
+ */
+ZTEST_USER(keyboard_mkbp_commands, test_mkbp_get_config_cmd)
+{
+	enum ec_status ret_val;
+	struct ec_response_mkbp_get_config resp;
+
+	ret_val = ec_cmd_mkbp_get_config(NULL, &resp);
+
+	zassert_ok(ret_val, "Expected=%d, returned=%d", EC_SUCCESS, ret_val);
+}
+
+/**
+ * @brief TestPurpose: Verify EC_CMD_MKBP_SET_CONFIG host command.
+ */
+ZTEST_USER(keyboard_mkbp_commands, test_mkbp_set_config_cmd)
+{
+	enum ec_status ret_val;
+	struct ec_params_mkbp_set_config req = { 0 };
+
+	get_keyscan_config(&req.config);
+
+	req.config.valid_mask =
+		EC_MKBP_VALID_SCAN_PERIOD | EC_MKBP_VALID_POLL_TIMEOUT |
+		EC_MKBP_VALID_MIN_POST_SCAN_DELAY |
+		EC_MKBP_VALID_OUTPUT_SETTLE | EC_MKBP_VALID_DEBOUNCE_DOWN |
+		EC_MKBP_VALID_DEBOUNCE_UP | EC_MKBP_VALID_FIFO_MAX_DEPTH;
+
+	ret_val = ec_cmd_mkbp_set_config(NULL, &req);
+
+	zassert_ok(ret_val, "Expected=%d, returned=%d", EC_SUCCESS, ret_val);
+}
diff --git a/zephyr/test/drivers/host_cmd/src/motion_sense.c b/zephyr/test/drivers/host_cmd/src/motion_sense.c
new file mode 100644
index 0000000000..f793b2f858
--- /dev/null
+++ b/zephyr/test/drivers/host_cmd/src/motion_sense.c
@@ -0,0 +1,938 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "atomic.h"
+#include "console.h"
+#include "driver/accel_bma2x2.h"
+#include "lid_angle.h"
+#include "motion_lid.h"
+#include "motion_sense.h"
+#include "motion_sense_fifo.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/fff.h>
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+FAKE_VALUE_FUNC(int, mock_set_range, struct motion_sensor_t *, int, int);
+FAKE_VALUE_FUNC(int, mock_set_offset, const struct motion_sensor_t *,
+		const int16_t *, int16_t);
+FAKE_VALUE_FUNC(int, mock_get_offset, const struct motion_sensor_t *, int16_t *,
+		int16_t *);
+FAKE_VALUE_FUNC(int, mock_set_scale, const struct motion_sensor_t *,
+		const uint16_t *, int16_t);
+FAKE_VALUE_FUNC(int, mock_get_scale, const struct motion_sensor_t *, uint16_t *,
+		int16_t *);
+FAKE_VALUE_FUNC(int, mock_perform_calib, struct motion_sensor_t *, int);
+
+/**
+ * Get the size needed for a struct ec_response_motion_sense
+ */
+#define RESPONSE_MOTION_SENSE_BUFFER_SIZE(n)       \
+	(sizeof(struct ec_response_motion_sense) + \
+	 n * sizeof(struct ec_response_motion_sensor_data))
+
+#define RESPONSE_SENSOR_FIFO_SIZE(n) \
+	(sizeof(struct ec_response_motion_sense) + n * sizeof(uint16_t))
+
+struct host_cmd_motion_sense_fixture {
+	const struct accelgyro_drv *sensor_0_drv;
+	struct accelgyro_drv mock_drv;
+};
+
+static void *host_cmd_motion_sense_setup(void)
+{
+	static struct host_cmd_motion_sense_fixture fixture = {
+		.mock_drv = {
+			.set_range = mock_set_range,
+			.set_offset = mock_set_offset,
+			.get_offset = mock_get_offset,
+			.set_scale = mock_set_scale,
+			.get_scale = mock_get_scale,
+			.perform_calib = mock_perform_calib,
+		},
+	};
+
+	fixture.sensor_0_drv = motion_sensors[0].drv;
+
+	return &fixture;
+}
+
+static void host_cmd_motion_sense_before(void *fixture)
+{
+	ARG_UNUSED(fixture);
+	RESET_FAKE(mock_set_range);
+	RESET_FAKE(mock_set_offset);
+	RESET_FAKE(mock_get_offset);
+	RESET_FAKE(mock_set_scale);
+	RESET_FAKE(mock_get_scale);
+	RESET_FAKE(mock_perform_calib);
+	FFF_RESET_HISTORY();
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "accelinit 0"));
+
+	atomic_clear(&motion_sensors[0].flush_pending);
+	motion_sensors[0].config[SENSOR_CONFIG_AP].odr = 0;
+	motion_sensors[0].config[SENSOR_CONFIG_AP].ec_rate = 1000 * MSEC;
+
+	/* Reset the lid wake angle to 0 degrees. */
+	lid_angle_set_wake_angle(0);
+}
+
+static void host_cmd_motion_sense_after(void *fixture)
+{
+	struct host_cmd_motion_sense_fixture *this = fixture;
+	struct ec_response_motion_sense response;
+
+	motion_sensors[0].drv = this->sensor_0_drv;
+	host_cmd_motion_sense_int_enable(0, &response);
+	motion_sensors[0].flags &= ~MOTIONSENSE_FLAG_IN_SPOOF_MODE;
+	motion_sensors[0].config[SENSOR_CONFIG_AP].odr = 0;
+	motion_sensors[0].config[SENSOR_CONFIG_AP].ec_rate = 1000 * MSEC;
+}
+
+ZTEST_SUITE(host_cmd_motion_sense, drivers_predicate_post_main,
+	    host_cmd_motion_sense_setup, host_cmd_motion_sense_before,
+	    host_cmd_motion_sense_after, NULL);
+
+ZTEST_USER(host_cmd_motion_sense, test_dump)
+{
+	uint8_t response_buffer[RESPONSE_MOTION_SENSE_BUFFER_SIZE(
+		ALL_MOTION_SENSORS)];
+	struct ec_response_motion_sense *result =
+		(struct ec_response_motion_sense *)response_buffer;
+
+	/* Set up the motion sensor data */
+	for (int i = 0; i < ALL_MOTION_SENSORS; ++i) {
+		motion_sensors[i].xyz[0] = i;
+		motion_sensors[i].xyz[1] = i + 1;
+		motion_sensors[i].xyz[2] = i + 2;
+	}
+
+	/* Make sure that the accelerometer status presence bit is off */
+	*host_get_memmap(EC_MEMMAP_ACC_STATUS) &=
+		~(EC_MEMMAP_ACC_STATUS_PRESENCE_BIT);
+
+	/* Dump all the sensors info */
+	host_cmd_motion_sense_dump(ALL_MOTION_SENSORS, result,
+				   sizeof(response_buffer));
+
+	zassert_equal(result->dump.module_flags, 0);
+	zassert_equal(result->dump.sensor_count, ALL_MOTION_SENSORS);
+
+	/*
+	 * Test the values returned in the dump. Normally we shouldn't be doing
+	 * tests in a loop, but since the number of sensors (as well as the
+	 * order) is adjustable by devicetree, it would be too difficult to hard
+	 * code here.
+	 * When CONFIG_GESTURE_HOST_DETECTION is enabled, ALL_MOTION_SENSORS is
+	 * increased by 1 (see include/motion_sense.h). Additionally,
+	 * host_cmd_motion_sense() only fills in |motion_sensor_count| worth of
+	 * data (not ALL_MOTION_SENSORS+1), and zeroes out the rest, so only
+	 * validate |motion_sensor_count| worth of data and that the rest is
+	 * zeroed out.
+	 */
+	for (int i = 0; i < ALL_MOTION_SENSORS; ++i) {
+		if (i < motion_sensor_count) {
+			zassert_equal(result->dump.sensor[i].flags,
+				      MOTIONSENSE_SENSOR_FLAG_PRESENT, NULL);
+			zassert_equal(result->dump.sensor[i].data[0], i);
+			zassert_equal(result->dump.sensor[i].data[1], i + 1);
+			zassert_equal(result->dump.sensor[i].data[2], i + 2);
+		} else {
+			zassert_equal(result->dump.sensor[i].data[0], 0);
+			zassert_equal(result->dump.sensor[i].data[1], 0);
+			zassert_equal(result->dump.sensor[i].data[2], 0);
+		}
+	}
+
+	/* Make sure that the accelerometer status presence bit is on */
+	*host_get_memmap(EC_MEMMAP_ACC_STATUS) |=
+		EC_MEMMAP_ACC_STATUS_PRESENCE_BIT;
+
+	/* Dump all the sensors info */
+	host_cmd_motion_sense_dump(ALL_MOTION_SENSORS, result,
+				   sizeof(response_buffer));
+
+	zassert_equal(result->dump.module_flags, MOTIONSENSE_MODULE_FLAG_ACTIVE,
+		      NULL);
+}
+
+ZTEST_USER(host_cmd_motion_sense, test_dump__large_max_sensor_count)
+{
+	uint8_t response_buffer[RESPONSE_MOTION_SENSE_BUFFER_SIZE(
+		ALL_MOTION_SENSORS)];
+	struct ec_response_motion_sense *result =
+		(struct ec_response_motion_sense *)response_buffer;
+
+	host_cmd_motion_sense_dump(ALL_MOTION_SENSORS + 1, result,
+				   sizeof(response_buffer));
+
+	zassert_equal(result->dump.sensor_count, ALL_MOTION_SENSORS);
+}
+
+ZTEST_USER(host_cmd_motion_sense, test_read_data__invalid_sensor_num)
+{
+	struct ec_response_motion_sense response;
+
+	zassert_equal(host_cmd_motion_sense_data(UINT8_MAX, &response),
+		      EC_RES_INVALID_PARAM, NULL);
+}
+
+ZTEST_USER(host_cmd_motion_sense, test_read_data)
+{
+	struct ec_response_motion_sense response;
+
+	motion_sensors[0].xyz[0] = 1;
+	motion_sensors[0].xyz[1] = 2;
+	motion_sensors[0].xyz[2] = 3;
+
+	zassert_ok(host_cmd_motion_sense_data(0, &response));
+	zassert_equal(response.data.flags, 0);
+	zassert_equal(response.data.data[0], 1);
+	zassert_equal(response.data.data[1], 2);
+	zassert_equal(response.data.data[2], 3);
+}
+
+ZTEST_USER(host_cmd_motion_sense, test_get_info__invalid_sensor_num)
+{
+	struct ec_response_motion_sense response;
+
+	zassert_equal(host_cmd_motion_sense_info(/*cmd_version=*/1,
+						 /*sensor_num=*/UINT8_MAX,
+						 &response),
+		      EC_RES_INVALID_PARAM, NULL);
+}
+
+ZTEST_USER(host_cmd_motion_sense, test_get_info_v1)
+{
+	struct ec_response_motion_sense response;
+
+	zassert_ok(host_cmd_motion_sense_info(/*cmd_version=*/1,
+					      /*sensor_num=*/0, &response),
+		   NULL);
+	zassert_equal(response.info.type, motion_sensors[0].type);
+	zassert_equal(response.info.location, motion_sensors[0].location);
+	zassert_equal(response.info.chip, motion_sensors[0].chip);
+}
+
+ZTEST_USER(host_cmd_motion_sense, test_get_info_v3)
+{
+	struct ec_response_motion_sense response;
+
+	zassert_ok(host_cmd_motion_sense_info(/*cmd_version=*/3,
+					      /*sensor_num=*/0, &response),
+		   NULL);
+	zassert_equal(response.info.type, motion_sensors[0].type);
+	zassert_equal(response.info.location, motion_sensors[0].location);
+	zassert_equal(response.info.chip, motion_sensors[0].chip);
+	zassert_equal(response.info_3.min_frequency,
+		      motion_sensors[0].min_frequency, NULL);
+	zassert_equal(response.info_3.max_frequency,
+		      motion_sensors[0].max_frequency, NULL);
+	zassert_equal(response.info_3.fifo_max_event_count,
+		      CONFIG_ACCEL_FIFO_SIZE, NULL);
+}
+
+ZTEST_USER(host_cmd_motion_sense, test_get_info_v4__no_read_temp)
+{
+	struct ec_response_motion_sense response;
+
+	zassert_ok(host_cmd_motion_sense_info(/*cmd_version=*/4,
+					      /*sensor_num=*/0, &response),
+		   NULL);
+	zassert_equal(response.info.type, motion_sensors[0].type);
+	zassert_equal(response.info.location, motion_sensors[0].location);
+	zassert_equal(response.info.chip, motion_sensors[0].chip);
+	if (IS_ENABLED(CONFIG_ONLINE_CALIB)) {
+		zassert_true(response.info_4.flags &
+				     MOTION_SENSE_CMD_INFO_FLAG_ONLINE_CALIB,
+			     NULL);
+	} else {
+		zassert_false(response.info_4.flags &
+				      MOTION_SENSE_CMD_INFO_FLAG_ONLINE_CALIB,
+			      NULL);
+	}
+}
+
+ZTEST_USER(host_cmd_motion_sense, test_get_ec_rate__invalid_sensor_num)
+{
+	struct ec_response_motion_sense response;
+
+	zassert_equal(host_cmd_motion_sense_ec_rate(
+			      /*sensor_num=*/0xff,
+			      /*data_rate_ms=*/EC_MOTION_SENSE_NO_VALUE,
+			      &response),
+		      EC_RES_INVALID_PARAM, NULL);
+}
+
+ZTEST_USER(host_cmd_motion_sense, test_get_ec_rate)
+{
+	struct ec_response_motion_sense response;
+
+	/* Set the power level to S3, the default config from device-tree is for
+	 * 100ms
+	 */
+	test_set_chipset_to_power_level(POWER_S3);
+	zassert_ok(host_cmd_motion_sense_ec_rate(
+			   /*sensor_num=*/0,
+			   /*data_rate_ms=*/EC_MOTION_SENSE_NO_VALUE,
+			   &response),
+		   NULL);
+	zassert_equal(response.ec_rate.ret, 1000);
+}
+
+ZTEST_USER(host_cmd_motion_sense, test_set_ec_rate)
+{
+	struct ec_response_motion_sense response;
+
+	/* Set the power level to S3, the default config from device-tree is for
+	 * 100ms
+	 */
+	test_set_chipset_to_power_level(POWER_S3);
+	zassert_ok(host_cmd_motion_sense_ec_rate(
+			   /*sensor_num=*/0, /*data_rate_ms=*/2000, &response),
+		   NULL);
+	/* The command should return the new rate */
+	zassert_equal(response.ec_rate.ret, 2000, "Expected 2000, but got %d",
+		      response.ec_rate.ret);
+	/* The sensor's AP config value should be updated */
+	zassert_equal(motion_sensors[0].config[SENSOR_CONFIG_AP].ec_rate,
+		      2000 * MSEC, NULL);
+}
+
+ZTEST_USER(host_cmd_motion_sense, test_odr_invalid_sensor_num)
+{
+	struct ec_response_motion_sense response;
+
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      host_cmd_motion_sense_odr(
+			      /*sensor_num=*/0xff,
+			      /*odr=*/EC_MOTION_SENSE_NO_VALUE,
+			      /*round_up=*/false, &response),
+		      NULL);
+}
+
+ZTEST_USER(host_cmd_motion_sense, test_odr_get)
+{
+	struct ec_response_motion_sense response;
+
+	zassert_ok(motion_sensors[0].drv->set_data_rate(&motion_sensors[0],
+							1000000, false),
+		   NULL);
+	zassert_ok(host_cmd_motion_sense_odr(/*sensor_num=*/0,
+					     /*odr=*/EC_MOTION_SENSE_NO_VALUE,
+					     /*round_up=*/false, &response),
+		   NULL);
+	zassert_equal(BMA2x2_REG_TO_BW(BMA2x2_BW_1000HZ),
+		      response.sensor_odr.ret, "Expected %d, but got %d",
+		      BMA2x2_REG_TO_BW(BMA2x2_BW_1000HZ),
+		      response.sensor_odr.ret);
+}
+
+ZTEST_USER(host_cmd_motion_sense, test_odr_set)
+{
+	struct ec_response_motion_sense response;
+
+	zassert_ok(motion_sensors[0].drv->set_data_rate(&motion_sensors[0], 0,
+							false),
+		   NULL);
+	zassert_ok(host_cmd_motion_sense_odr(/*sensor_num=*/0,
+					     /*odr=*/1000000,
+					     /*round_up=*/true, &response),
+		   NULL);
+	/* Check the set value */
+	zassert_equal(1000000 | ROUND_UP_FLAG,
+		      motion_sensors[0].config[SENSOR_CONFIG_AP].odr,
+		      "Expected %d, but got %d", 1000000 | ROUND_UP_FLAG,
+		      motion_sensors[0].config[SENSOR_CONFIG_AP].odr);
+	/* Check the returned value */
+	zassert_equal(BMA2x2_REG_TO_BW(BMA2x2_BW_7_81HZ),
+		      response.sensor_odr.ret, "Expected %d, but got %d",
+		      BMA2x2_REG_TO_BW(BMA2x2_BW_7_81HZ),
+		      response.sensor_odr.ret);
+}
+
+ZTEST_USER(host_cmd_motion_sense, test_range_invalid_sensor_num)
+{
+	struct ec_response_motion_sense response;
+
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      host_cmd_motion_sense_range(
+			      /*sensor_num=*/0xff,
+			      /*range=*/EC_MOTION_SENSE_NO_VALUE,
+			      /*round_up=*/false, &response),
+		      NULL);
+}
+
+ZTEST_USER(host_cmd_motion_sense, test_get_range)
+{
+	struct ec_response_motion_sense response;
+
+	zassert_ok(host_cmd_motion_sense_range(
+			   /*sensor_num=*/0, /*range=*/EC_MOTION_SENSE_NO_VALUE,
+			   /*round_up=*/false, &response),
+		   NULL);
+	zassert_equal(motion_sensors[0].current_range,
+		      response.sensor_range.ret, "Expected %d, but got %d",
+		      motion_sensors[0].current_range,
+		      response.sensor_range.ret);
+}
+
+ZTEST_USER(host_cmd_motion_sense, test_null_set_range_in_driver)
+{
+	struct ec_response_motion_sense response;
+	struct accelgyro_drv drv = { 0 };
+
+	motion_sensors[0].drv = &drv;
+	zassert_equal(EC_RES_INVALID_COMMAND,
+		      host_cmd_motion_sense_range(/*sensor_num=*/0, /*range=*/4,
+						  /*round_up=*/false,
+						  &response),
+		      NULL);
+}
+
+ZTEST_USER_F(host_cmd_motion_sense, test_set_range_error)
+{
+	struct ec_response_motion_sense response;
+
+	mock_set_range_fake.return_val = 1;
+	motion_sensors[0].drv = &fixture->mock_drv;
+
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      host_cmd_motion_sense_range(/*sensor_num=*/0, /*range=*/4,
+						  /*round_up=*/false,
+						  &response),
+		      NULL);
+	zassert_equal(1, mock_set_range_fake.call_count);
+}
+
+ZTEST_USER_F(host_cmd_motion_sense, test_set_range)
+{
+	struct ec_response_motion_sense response;
+
+	mock_set_range_fake.return_val = 0;
+	motion_sensors[0].drv = &fixture->mock_drv;
+
+	zassert_ok(host_cmd_motion_sense_range(/*sensor_num=*/0, /*range=*/4,
+					       /*round_up=*/false, &response),
+		   NULL);
+	zassert_equal(1, mock_set_range_fake.call_count);
+	zassert_equal(4, mock_set_range_fake.arg1_history[0]);
+	zassert_equal(0, mock_set_range_fake.arg2_history[0]);
+}
+
+ZTEST_USER(host_cmd_motion_sense, test_offset_invalid_sensor_num)
+{
+	struct ec_response_motion_sense response;
+
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      host_cmd_motion_sense_offset(
+			      /*sensor_num=*/0xff, /*flags=*/0,
+			      /*temperature=*/0, /*offset_x=*/0,
+			      /*offset_y=*/0, /*offset_z=*/0, &response),
+		      NULL);
+}
+
+ZTEST_USER(host_cmd_motion_sense, test_offset_missing_get_offset_in_driver)
+{
+	struct ec_response_motion_sense response;
+	struct accelgyro_drv drv = { 0 };
+
+	motion_sensors[0].drv = &drv;
+
+	zassert_equal(EC_RES_INVALID_COMMAND,
+		      host_cmd_motion_sense_offset(
+			      /*sensor_num=*/0, /*flags=*/0,
+			      /*temperature=*/0, /*offset_x=*/0,
+			      /*offset_y=*/0, /*offset_z=*/0, &response),
+		      NULL);
+}
+
+ZTEST_USER(host_cmd_motion_sense, test_offset_missing_set_offset_in_driver)
+{
+	struct ec_response_motion_sense response;
+	struct accelgyro_drv drv = { 0 };
+
+	motion_sensors[0].drv = &drv;
+
+	zassert_equal(EC_RES_INVALID_COMMAND,
+		      host_cmd_motion_sense_offset(
+			      /*sensor_num=*/0,
+			      /*flags=*/MOTION_SENSE_SET_OFFSET,
+			      /*temperature=*/0, /*offset_x=*/0,
+			      /*offset_y=*/0, /*offset_z=*/0, &response),
+		      NULL);
+}
+
+ZTEST_USER_F(host_cmd_motion_sense, test_offset_fail_to_set)
+{
+	struct ec_response_motion_sense response;
+
+	motion_sensors[0].drv = &fixture->mock_drv;
+	mock_set_offset_fake.return_val = EC_RES_ERROR;
+
+	zassert_equal(EC_RES_ERROR,
+		      host_cmd_motion_sense_offset(
+			      /*sensor_num=*/0,
+			      /*flags=*/MOTION_SENSE_SET_OFFSET,
+			      /*temperature=*/0, /*offset_x=*/0,
+			      /*offset_y=*/0, /*offset_z=*/0, &response),
+		      NULL);
+	zassert_equal(1, mock_set_offset_fake.call_count);
+}
+
+ZTEST_USER_F(host_cmd_motion_sense, test_offset_fail_to_get)
+{
+	struct ec_response_motion_sense response;
+
+	motion_sensors[0].drv = &fixture->mock_drv;
+	mock_set_offset_fake.return_val = EC_RES_SUCCESS;
+	mock_get_offset_fake.return_val = EC_RES_ERROR;
+
+	zassert_equal(EC_RES_ERROR,
+		      host_cmd_motion_sense_offset(
+			      /*sensor_num=*/0,
+			      /*flags=*/MOTION_SENSE_SET_OFFSET,
+			      /*temperature=*/0, /*offset_x=*/0,
+			      /*offset_y=*/0, /*offset_z=*/0, &response),
+		      NULL);
+	zassert_equal(1, mock_set_offset_fake.call_count);
+	zassert_equal(1, mock_get_offset_fake.call_count);
+	zassert_equal((int16_t *)&response.sensor_offset.offset,
+		      mock_get_offset_fake.arg1_history[0], NULL);
+}
+
+ZTEST_USER_F(host_cmd_motion_sense, test_get_offset)
+{
+	struct ec_response_motion_sense response;
+
+	motion_sensors[0].drv = &fixture->mock_drv;
+	mock_get_offset_fake.return_val = EC_RES_SUCCESS;
+	mock_set_offset_fake.return_val = EC_RES_SUCCESS;
+
+	zassert_ok(host_cmd_motion_sense_offset(
+			   /*sensor_num=*/0,
+			   /*flags=*/MOTION_SENSE_SET_OFFSET,
+			   /*temperature=*/1, /*offset_x=*/2,
+			   /*offset_y=*/3, /*offset_z=*/4, &response),
+		   NULL);
+	zassert_equal(1, mock_set_offset_fake.call_count);
+	zassert_equal(1, mock_get_offset_fake.call_count);
+	zassert_equal((int16_t *)&response.sensor_offset.offset,
+		      mock_get_offset_fake.arg1_history[0], NULL);
+	zassert_equal(1, mock_set_offset_fake.arg2_history[0]);
+}
+
+ZTEST_USER(host_cmd_motion_sense, test_scale_invalid_sensor_num)
+{
+	struct ec_response_motion_sense response;
+
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      host_cmd_motion_sense_scale(
+			      /*sensor_num=*/0xff,
+			      /*flags=*/0,
+			      /*temperature=*/1, /*scale_x=*/2,
+			      /*scale_y=*/3, /*scale_z=*/4, &response),
+		      NULL);
+}
+
+ZTEST_USER(host_cmd_motion_sense, test_get_scale_not_in_driver)
+{
+	struct ec_response_motion_sense response;
+	struct accelgyro_drv drv = *motion_sensors[0].drv;
+
+	drv.get_scale = NULL;
+	motion_sensors[0].drv = &drv;
+
+	zassert_equal(EC_RES_INVALID_COMMAND,
+		      host_cmd_motion_sense_scale(
+			      /*sensor_num=*/0,
+			      /*flags=*/0,
+			      /*temperature=*/1, /*scale_x=*/2,
+			      /*scale_y=*/3, /*scale_z=*/4, &response),
+		      NULL);
+}
+
+ZTEST_USER(host_cmd_motion_sense, test_set_scale_not_in_driver)
+{
+	struct ec_response_motion_sense response;
+	struct accelgyro_drv drv = *motion_sensors[0].drv;
+
+	drv.set_scale = NULL;
+	motion_sensors[0].drv = &drv;
+
+	zassert_equal(EC_RES_INVALID_COMMAND,
+		      host_cmd_motion_sense_scale(
+			      /*sensor_num=*/0,
+			      /*flags=*/MOTION_SENSE_SET_OFFSET,
+			      /*temperature=*/1, /*scale_x=*/2,
+			      /*scale_y=*/3, /*scale_z=*/4, &response),
+		      NULL);
+}
+
+ZTEST_USER_F(host_cmd_motion_sense, test_get_scale_fail)
+{
+	struct ec_response_motion_sense response;
+
+	motion_sensors[0].drv = &fixture->mock_drv;
+	mock_get_scale_fake.return_val = 1;
+
+	zassert_equal(1,
+		      host_cmd_motion_sense_scale(
+			      /*sensor_num=*/0,
+			      /*flags=*/0,
+			      /*temperature=*/1, /*scale_x=*/2,
+			      /*scale_y=*/3, /*scale_z=*/4, &response),
+		      NULL);
+	zassert_equal(1, mock_get_scale_fake.call_count);
+}
+
+ZTEST_USER_F(host_cmd_motion_sense, test_set_scale_fail)
+{
+	struct ec_response_motion_sense response;
+
+	motion_sensors[0].drv = &fixture->mock_drv;
+	mock_set_scale_fake.return_val = 1;
+
+	zassert_equal(1,
+		      host_cmd_motion_sense_scale(
+			      /*sensor_num=*/0,
+			      /*flags=*/MOTION_SENSE_SET_OFFSET,
+			      /*temperature=*/1, /*scale_x=*/2,
+			      /*scale_y=*/3, /*scale_z=*/4, &response),
+		      NULL);
+	zassert_equal(1, mock_set_scale_fake.call_count);
+}
+
+ZTEST_USER_F(host_cmd_motion_sense, test_set_get_scale)
+{
+	struct ec_response_motion_sense response;
+
+	motion_sensors[0].drv = &fixture->mock_drv;
+	mock_set_scale_fake.return_val = 0;
+	mock_get_scale_fake.return_val = 0;
+
+	zassert_ok(host_cmd_motion_sense_scale(
+			   /*sensor_num=*/0,
+			   /*flags=*/MOTION_SENSE_SET_OFFSET,
+			   /*temperature=*/1, /*scale_x=*/2,
+			   /*scale_y=*/3, /*scale_z=*/4, &response),
+		   NULL);
+	zassert_equal(1, mock_set_scale_fake.call_count);
+	zassert_equal(1, mock_get_scale_fake.call_count);
+	zassert_equal(1, mock_set_scale_fake.arg2_history[0]);
+}
+
+ZTEST_USER(host_cmd_motion_sense, test_calib_invalid_sensor_num)
+{
+	struct ec_response_motion_sense response;
+
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      host_cmd_motion_sense_calib(/*sensor_num=*/0xff,
+						  /*enable=*/false, &response),
+		      NULL);
+}
+
+ZTEST_USER(host_cmd_motion_sense, test_calib_not_in_driver)
+{
+	struct ec_response_motion_sense response;
+	struct accelgyro_drv drv = { 0 };
+
+	motion_sensors[0].drv = &drv;
+	zassert_equal(EC_RES_INVALID_COMMAND,
+		      host_cmd_motion_sense_calib(/*sensor_num=*/0,
+						  /*enable=*/false, &response),
+		      NULL);
+}
+
+ZTEST_USER_F(host_cmd_motion_sense, test_calib_fail)
+{
+	struct ec_response_motion_sense response;
+
+	motion_sensors[0].drv = &fixture->mock_drv;
+	mock_perform_calib_fake.return_val = 1;
+
+	zassert_equal(1,
+		      host_cmd_motion_sense_calib(/*sensor_num=*/0,
+						  /*enable=*/false, &response),
+		      NULL);
+	zassert_equal(1, mock_perform_calib_fake.call_count);
+	zassert_false(mock_perform_calib_fake.arg1_history[0]);
+}
+
+ZTEST_USER_F(host_cmd_motion_sense, test_calib_success__fail_get_offset)
+{
+	struct ec_response_motion_sense response;
+
+	motion_sensors[0].drv = &fixture->mock_drv;
+	mock_perform_calib_fake.return_val = 0;
+	mock_get_offset_fake.return_val = 1;
+
+	zassert_equal(1,
+		      host_cmd_motion_sense_calib(/*sensor_num=*/0,
+						  /*enable=*/false, &response),
+		      NULL);
+	zassert_equal(1, mock_perform_calib_fake.call_count);
+	zassert_equal(1, mock_get_offset_fake.call_count);
+	zassert_false(mock_perform_calib_fake.arg1_history[0]);
+}
+
+ZTEST_USER_F(host_cmd_motion_sense, test_calib)
+{
+	struct ec_response_motion_sense response;
+
+	motion_sensors[0].drv = &fixture->mock_drv;
+	mock_perform_calib_fake.return_val = 0;
+	mock_get_offset_fake.return_val = 0;
+
+	zassert_ok(host_cmd_motion_sense_calib(/*sensor_num=*/0,
+					       /*enable=*/true, &response),
+		   NULL);
+	zassert_equal(1, mock_perform_calib_fake.call_count);
+	zassert_equal(1, mock_get_offset_fake.call_count);
+	zassert_true(mock_perform_calib_fake.arg1_history[0]);
+}
+
+ZTEST(host_cmd_motion_sense, test_fifo_flush__invalid_sensor_num)
+{
+	int rv;
+	struct ec_response_motion_sense response;
+
+	rv = host_cmd_motion_sense_fifo_flush(/*sensor_num=*/0xff, &response,
+					      sizeof(response));
+	zassert_equal(rv, EC_RES_INVALID_PARAM);
+}
+
+ZTEST(host_cmd_motion_sense, test_fifo_flush)
+{
+	uint8_t response_buffer[RESPONSE_SENSOR_FIFO_SIZE(ALL_MOTION_SENSORS)];
+	struct ec_response_motion_sense *response =
+		(struct ec_response_motion_sense *)response_buffer;
+
+	zassert_ok(host_cmd_motion_sense_fifo_flush(/*sensor_num=*/0, response,
+						    sizeof(response_buffer)),
+		   NULL);
+	zassert_equal(1, motion_sensors[0].flush_pending);
+}
+
+ZTEST(host_cmd_motion_sense, test_fifo_info)
+{
+	uint8_t response_buffer[RESPONSE_SENSOR_FIFO_SIZE(ALL_MOTION_SENSORS)];
+	struct ec_response_motion_sense *response =
+		(struct ec_response_motion_sense *)response_buffer;
+
+	zassert_ok(host_cmd_motion_sense_fifo_info(response,
+						   sizeof(response_buffer)));
+}
+
+ZTEST(host_cmd_motion_sense, test_fifo_read)
+{
+	struct ec_response_motion_sensor_data data;
+	uint8_t response_buffer[RESPONSE_MOTION_SENSE_BUFFER_SIZE(2)];
+	struct ec_response_motion_sense *response =
+		(struct ec_response_motion_sense *)response_buffer;
+
+	motion_sensors[0].oversampling_ratio = 1;
+	motion_sensors[1].oversampling_ratio = 1;
+
+	data = (struct ec_response_motion_sensor_data){
+		.flags = 0,
+		.sensor_num = 0,
+		.data = { 0, 1, 2 },
+	};
+	motion_sense_fifo_stage_data(&data, &motion_sensors[0], 1, 0);
+
+	data = (struct ec_response_motion_sensor_data){
+		.flags = 0,
+		.sensor_num = 1,
+		.data = { 3, 4, 5 },
+	};
+	motion_sense_fifo_stage_data(&data, &motion_sensors[1], 1, 5);
+	motion_sense_fifo_commit_data();
+
+	/* Read 2 samples */
+	zassert_ok(host_cmd_motion_sense_fifo_read(4, response));
+	zassert_equal(2, response->fifo_read.number_data);
+
+	zassert_equal(MOTIONSENSE_SENSOR_FLAG_TIMESTAMP,
+		      response->fifo_read.data[0].flags, NULL);
+	zassert_equal(0, response->fifo_read.data[0].sensor_num);
+	zassert_equal(0, response->fifo_read.data[0].timestamp);
+
+	zassert_equal(0, response->fifo_read.data[1].flags);
+	zassert_equal(0, response->fifo_read.data[1].sensor_num);
+	zassert_equal(0, response->fifo_read.data[1].data[0]);
+	zassert_equal(1, response->fifo_read.data[1].data[1]);
+	zassert_equal(2, response->fifo_read.data[1].data[2]);
+
+	/* Read the next 2 samples */
+	zassert_ok(host_cmd_motion_sense_fifo_read(4, response));
+	zassert_equal(2, response->fifo_read.number_data);
+	zassert_equal(MOTIONSENSE_SENSOR_FLAG_TIMESTAMP,
+		      response->fifo_read.data[0].flags, NULL);
+	zassert_equal(1, response->fifo_read.data[0].sensor_num);
+	zassert_equal(5, response->fifo_read.data[0].timestamp);
+
+	zassert_equal(0, response->fifo_read.data[1].flags);
+	zassert_equal(1, response->fifo_read.data[1].sensor_num);
+	zassert_equal(3, response->fifo_read.data[1].data[0]);
+	zassert_equal(4, response->fifo_read.data[1].data[1]);
+	zassert_equal(5, response->fifo_read.data[1].data[2]);
+}
+
+ZTEST(host_cmd_motion_sense, test_int_enable)
+{
+	struct ec_response_motion_sense response;
+
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      host_cmd_motion_sense_int_enable(2, &response), NULL);
+
+	/* Make sure we start off disabled */
+	zassert_ok(host_cmd_motion_sense_int_enable(0, &response));
+
+	/* Test enable */
+	zassert_ok(host_cmd_motion_sense_int_enable(1, &response));
+	zassert_ok(host_cmd_motion_sense_int_enable(EC_MOTION_SENSE_NO_VALUE,
+						    &response),
+		   NULL);
+	zassert_equal(1, response.fifo_int_enable.ret);
+
+	/* Test disable */
+	zassert_ok(host_cmd_motion_sense_int_enable(0, &response));
+	zassert_ok(host_cmd_motion_sense_int_enable(EC_MOTION_SENSE_NO_VALUE,
+						    &response),
+		   NULL);
+	zassert_equal(0, response.fifo_int_enable.ret);
+}
+
+ZTEST(host_cmd_motion_sense, test_spoof_invalid_sensor_num)
+{
+	struct ec_response_motion_sense response;
+
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      host_cmd_motion_sense_spoof(0xff, 0, 0, 0, 0, &response),
+		      NULL);
+}
+
+ZTEST(host_cmd_motion_sense, test_spoof_disable)
+{
+	struct ec_response_motion_sense response;
+
+	motion_sensors[0].flags |= MOTIONSENSE_FLAG_IN_SPOOF_MODE;
+	zassert_ok(host_cmd_motion_sense_spoof(0,
+					       MOTIONSENSE_SPOOF_MODE_DISABLE,
+					       0, 0, 0, &response),
+		   NULL);
+	zassert_equal(0,
+		      motion_sensors[0].flags & MOTIONSENSE_FLAG_IN_SPOOF_MODE,
+		      NULL);
+
+	zassert_ok(host_cmd_motion_sense_spoof(0, MOTIONSENSE_SPOOF_MODE_QUERY,
+					       0, 0, 0, &response),
+		   NULL);
+	zassert_false(response.spoof.ret);
+}
+
+ZTEST(host_cmd_motion_sense, test_spoof_custom)
+{
+	struct ec_response_motion_sense response;
+
+	zassert_ok(host_cmd_motion_sense_spoof(0, MOTIONSENSE_SPOOF_MODE_CUSTOM,
+					       -8, 16, -32, &response),
+		   NULL);
+	zassert_equal(MOTIONSENSE_FLAG_IN_SPOOF_MODE,
+		      motion_sensors[0].flags & MOTIONSENSE_FLAG_IN_SPOOF_MODE,
+		      NULL);
+	zassert_equal(-8, motion_sensors[0].spoof_xyz[0]);
+	zassert_equal(16, motion_sensors[0].spoof_xyz[1]);
+	zassert_equal(-32, motion_sensors[0].spoof_xyz[2]);
+
+	zassert_ok(host_cmd_motion_sense_spoof(0, MOTIONSENSE_SPOOF_MODE_QUERY,
+					       0, 0, 0, &response),
+		   NULL);
+	zassert_true(response.spoof.ret);
+}
+
+ZTEST(host_cmd_motion_sense, test_spoof_lock_current)
+{
+	struct ec_response_motion_sense response;
+
+	motion_sensors[0].raw_xyz[0] = 64;
+	motion_sensors[0].raw_xyz[1] = 48;
+	motion_sensors[0].raw_xyz[2] = 32;
+	zassert_ok(host_cmd_motion_sense_spoof(
+			   0, MOTIONSENSE_SPOOF_MODE_LOCK_CURRENT, 0, 0, 0,
+			   &response),
+		   NULL);
+	zassert_equal(MOTIONSENSE_FLAG_IN_SPOOF_MODE,
+		      motion_sensors[0].flags & MOTIONSENSE_FLAG_IN_SPOOF_MODE,
+		      NULL);
+	zassert_equal(64, motion_sensors[0].spoof_xyz[0]);
+	zassert_equal(48, motion_sensors[0].spoof_xyz[1]);
+	zassert_equal(32, motion_sensors[0].spoof_xyz[2]);
+
+	zassert_ok(host_cmd_motion_sense_spoof(0, MOTIONSENSE_SPOOF_MODE_QUERY,
+					       0, 0, 0, &response),
+		   NULL);
+	zassert_true(response.spoof.ret);
+}
+
+ZTEST(host_cmd_motion_sense, test_spoof_invalid_mode)
+{
+	struct ec_response_motion_sense response;
+
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      host_cmd_motion_sense_spoof(0, 0xff, 0, 0, 0, &response),
+		      NULL);
+}
+
+ZTEST(host_cmd_motion_sense, test_set_kb_wake_lid_angle)
+{
+	struct ec_response_motion_sense response;
+	int16_t expected_lid_angle = 45;
+	int rv;
+
+	rv = host_cmd_motion_sense_kb_wake_angle(expected_lid_angle, &response);
+
+	zassert_ok(rv, "Got %d", rv);
+	zassert_equal(expected_lid_angle, lid_angle_get_wake_angle());
+	zassert_equal(expected_lid_angle, response.kb_wake_angle.ret);
+}
+
+ZTEST(host_cmd_motion_sense, test_get_lid_angle)
+{
+	struct ec_response_motion_sense response;
+	int rv;
+
+	rv = host_cmd_motion_sense_lid_angle(&response);
+
+	zassert_ok(rv, "Got %d", rv);
+	zassert_equal(motion_lid_get_angle(), response.lid_angle.value);
+}
+
+ZTEST(host_cmd_motion_sense, test_tablet_mode_lid_angle)
+{
+	struct ec_response_motion_sense response;
+	int16_t expected_angle = 45;
+	int16_t expected_hys = 3;
+	int rv;
+
+	rv = host_cmd_motion_sense_tablet_mode_lid_angle(
+		expected_angle, expected_hys, &response);
+
+	zassert_ok(rv, "Got %d", rv);
+	zassert_equal(expected_angle, response.tablet_mode_threshold.lid_angle);
+	zassert_equal(expected_hys, response.tablet_mode_threshold.hys_degree);
+}
+
+ZTEST(host_cmd_motion_sense, test_tablet_mode_lid_angle__invalid)
+{
+	struct ec_response_motion_sense response;
+
+	zassert_ok(!host_cmd_motion_sense_tablet_mode_lid_angle(-100, -100,
+								&response));
+}
diff --git a/zephyr/test/drivers/host_cmd/src/pd_chip_info.c b/zephyr/test/drivers/host_cmd/src/pd_chip_info.c
new file mode 100644
index 0000000000..12d426fa30
--- /dev/null
+++ b/zephyr/test/drivers/host_cmd/src/pd_chip_info.c
@@ -0,0 +1,65 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "driver/tcpm/tcpci.h"
+#include "ec_commands.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+#define BAD_PORT 65
+
+static enum ec_status run_pd_chip_info(int port,
+				       struct ec_response_pd_chip_info_v1 *resp)
+{
+	struct ec_params_pd_chip_info params = { .port = port, .live = true };
+
+	return ec_cmd_pd_chip_info_v1(NULL, &params, resp);
+}
+
+ZTEST_USER(host_cmd_pd_chip_info, test_good_index)
+{
+	for (enum usbc_port p = USBC_PORT_C0; p < USBC_PORT_COUNT; p++) {
+		struct ec_response_pd_chip_info_v1 response;
+
+		zassert_ok(run_pd_chip_info(p, &response),
+			   "Failed to process pd_get_chip_info for port %d", p);
+	}
+	/*
+	 * Note: verification of the specific fields depends on the chips used
+	 * and therefore would belong in a driver-level test
+	 */
+}
+
+ZTEST_USER(host_cmd_pd_chip_info, test_bad_index)
+{
+	struct ec_response_pd_chip_info_v1 response;
+
+	zassert_true(board_get_usb_pd_port_count() < BAD_PORT,
+		     "Intended bad port exists");
+	zassert_equal(run_pd_chip_info(BAD_PORT, &response),
+		      EC_RES_INVALID_PARAM,
+		      "Failed to fail pd_chip_info for port %d", BAD_PORT);
+}
+
+static void host_cmd_pd_chip_info_begin(void *data)
+{
+	ARG_UNUSED(data);
+
+	/* Assume we have at least one USB-C port */
+	zassert_true(board_get_usb_pd_port_count() > 0,
+		     "Insufficient TCPCs found");
+
+	/* Set the system into S0, since the AP would drive these commands */
+	test_set_chipset_to_s0();
+	k_sleep(K_SECONDS(1));
+}
+
+ZTEST_SUITE(host_cmd_pd_chip_info, drivers_predicate_post_main, NULL,
+	    host_cmd_pd_chip_info_begin, NULL, NULL);
diff --git a/zephyr/test/drivers/host_cmd/src/pd_control.c b/zephyr/test/drivers/host_cmd/src/pd_control.c
new file mode 100644
index 0000000000..701e8e7be2
--- /dev/null
+++ b/zephyr/test/drivers/host_cmd/src/pd_control.c
@@ -0,0 +1,135 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "ec_commands.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/fff.h>
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+#define TEST_PORT USBC_PORT_C0
+#define BAD_PORT 82
+
+ZTEST_USER(host_cmd_pd_control, test_bad_index)
+{
+	struct ec_params_pd_control params = { .chip = BAD_PORT,
+					       .subcmd = PD_RESET };
+
+	zassert_true(board_get_usb_pd_port_count() < BAD_PORT,
+		     "Intended bad port exists");
+	zassert_equal(ec_cmd_pd_control(NULL, &params), EC_RES_INVALID_PARAM,
+		      "Failed to fail pd_control for port %d", params.chip);
+}
+
+ZTEST_USER(host_cmd_pd_control, test_unimplemented_command)
+{
+	struct ec_params_pd_control params = { .chip = TEST_PORT,
+					       .subcmd = PD_CHIP_ON };
+
+	zassert_equal(ec_cmd_pd_control(NULL, &params), EC_RES_INVALID_COMMAND,
+		      "Failed to fail pd_control for port %d", params.chip);
+}
+
+ZTEST_USER(host_cmd_pd_control, test_pd_reset_resume)
+{
+	/*
+	 * Note: this would ideally be a host command interface check, but
+	 * the only HC return which would cover this is a state string, which
+	 * could be brittle.
+	 */
+	zassert_true(pd_is_port_enabled(TEST_PORT), "Port not up at beginning");
+
+	host_cmd_pd_control(TEST_PORT, PD_RESET);
+
+	zassert_equal(1, board_reset_pd_mcu_fake.call_count,
+		      "Failed to see board reset");
+
+	/* Give some PD task processing time */
+	k_sleep(K_SECONDS(1));
+
+	zassert_false(pd_is_port_enabled(TEST_PORT), "Port failed to suspend");
+
+	host_cmd_pd_control(TEST_PORT, PD_RESUME);
+
+	/* Give some PD task processing time */
+	k_sleep(K_SECONDS(1));
+
+	zassert_true(pd_is_port_enabled(TEST_PORT), "Port failed to resume");
+
+	RESET_FAKE(board_reset_pd_mcu);
+}
+
+ZTEST_USER(host_cmd_pd_control, test_suspend_resume)
+{
+	/*
+	 * Note: this would ideally be a host command interface check, but
+	 * the only HC return which would cover this is a state string, which
+	 * could be brittle.
+	 */
+	zassert_true(pd_is_port_enabled(TEST_PORT), "Port not up at beginning");
+
+	host_cmd_pd_control(TEST_PORT, PD_SUSPEND);
+
+	/* Give some PD task processing time */
+	k_sleep(K_SECONDS(1));
+
+	zassert_false(pd_is_port_enabled(TEST_PORT), "Port failed to suspend");
+
+	host_cmd_pd_control(TEST_PORT, PD_RESUME);
+
+	/* Give some PD task processing time */
+	k_sleep(K_SECONDS(1));
+
+	zassert_true(pd_is_port_enabled(TEST_PORT), "Port failed to resume");
+}
+
+ZTEST_USER(host_cmd_pd_control, test_suspend_low_battery)
+{
+	struct ec_params_pd_control params = { .chip = TEST_PORT,
+					       .subcmd = PD_SUSPEND };
+
+	/* Suspending the port for firmware update should fail at critical low
+	 * battery.
+	 */
+	test_set_battery_level(1);
+	zassert_equal(ec_cmd_pd_control(NULL, &params), EC_RES_BUSY);
+}
+
+ZTEST_USER(host_cmd_pd_control, test_control_disable)
+{
+	struct ec_params_pd_control params = { .chip = TEST_PORT,
+					       .subcmd = PD_RESET };
+
+	host_cmd_pd_control(TEST_PORT, PD_CONTROL_DISABLE);
+
+	zassert_equal(ec_cmd_pd_control(NULL, &params), EC_RES_ACCESS_DENIED,
+		      "Access was not denied for port %d", params.chip);
+
+	/*
+	 * Disable lasts as long as the EC is booted.  Use a test hook to
+	 * restore our state to a normal one
+	 */
+	pd_control_port_enable(TEST_PORT);
+}
+
+static void host_cmd_pd_control_begin(void *data)
+{
+	ARG_UNUSED(data);
+
+	/* Assume we have at least one USB-C port */
+	zassert_true(board_get_usb_pd_port_count() > 0,
+		     "Insufficient TCPCs found");
+
+	/* Set the system into S0, since the AP would drive these commands */
+	test_set_chipset_to_s0();
+	k_sleep(K_SECONDS(1));
+}
+
+ZTEST_SUITE(host_cmd_pd_control, drivers_predicate_post_main, NULL,
+	    host_cmd_pd_control_begin, NULL, NULL);
diff --git a/zephyr/test/drivers/host_cmd/src/pd_log.c b/zephyr/test/drivers/host_cmd/src/pd_log.c
new file mode 100644
index 0000000000..75873ac7dd
--- /dev/null
+++ b/zephyr/test/drivers/host_cmd/src/pd_log.c
@@ -0,0 +1,160 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "event_log.h"
+#include "host_command.h"
+#include "test/drivers/test_state.h"
+#include "usb_pd.h"
+#include "util.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+/**
+ * @brief This is the maximum size of a single log entry.
+ *
+ * Each entry must contain some common data + up to 16 bytes of additional type
+ * specific data.
+ */
+#define MAX_EVENT_LOG_ENTRY_SIZE (sizeof(struct event_log_entry) + 16)
+
+/**
+ * @brief This is the maximum size of a response pd log entry.
+ *
+ * Each entry must contain some common data + up to 16 bytes of additional type
+ * specific data.
+ */
+#define MAX_RESPONSE_PD_LOG_ENTRY_SIZE (sizeof(struct ec_response_pd_log) + 16)
+
+/**
+ * @brief The size of the PD log entry data
+ *
+ * Logs from the PD include an additional 8 bytes of data to be sent to the AP.
+ */
+#define PD_LOG_ENTRY_DATA_SIZE (8)
+
+struct pd_log_fixture {
+	union {
+		uint8_t event_log_buffer[MAX_EVENT_LOG_ENTRY_SIZE];
+		struct event_log_entry log_entry;
+	};
+};
+
+static void *pd_log_setup(void)
+{
+	static struct pd_log_fixture fixture;
+
+	return &fixture;
+}
+
+static void pd_log_before(void *f)
+{
+	struct pd_log_fixture *fixture = f;
+
+	while (log_dequeue_event(&fixture->log_entry) != 0) {
+		if (fixture->log_entry.type == EVENT_LOG_NO_ENTRY) {
+			break;
+		}
+	}
+}
+
+ZTEST_SUITE(pd_log, drivers_predicate_post_main, pd_log_setup, pd_log_before,
+	    NULL, NULL);
+
+ZTEST_USER(pd_log, test_bad_type)
+{
+	struct ec_params_pd_write_log_entry params = {
+		.type = PD_EVENT_ACC_BASE,
+	};
+
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      ec_cmd_pd_write_log_entry(NULL, &params), NULL);
+}
+
+ZTEST_USER(pd_log, test_bad_port)
+{
+	struct ec_params_pd_write_log_entry params = {
+		.type = PD_EVENT_MCU_BASE,
+	};
+
+	params.port = board_get_usb_pd_port_count() + 1;
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      ec_cmd_pd_write_log_entry(NULL, &params), NULL);
+}
+
+ZTEST_USER_F(pd_log, test_mcu_charge)
+{
+	struct ec_params_pd_write_log_entry params = {
+		.type = PD_EVENT_MCU_CHARGE,
+		.port = 0,
+	};
+
+	zassert_ok(ec_cmd_pd_write_log_entry(NULL, &params), NULL);
+	zassert_equal(sizeof(struct event_log_entry) + PD_LOG_ENTRY_DATA_SIZE,
+		      log_dequeue_event(&fixture->log_entry), NULL);
+	zassert_equal(params.type, fixture->log_entry.type, NULL);
+	zassert_equal(PD_LOG_ENTRY_DATA_SIZE, fixture->log_entry.size, NULL);
+	zassert_equal(0, fixture->log_entry.data, NULL);
+	zassert_within(0, (int64_t)fixture->log_entry.timestamp, 10,
+		       "Expected timestamp %" PRIi64
+		       " to be within 10 ms of now",
+		       (int64_t)fixture->log_entry.timestamp);
+}
+ZTEST_USER_F(pd_log, test_mcu_connect)
+{
+	struct ec_params_pd_write_log_entry params = {
+		.type = PD_EVENT_MCU_CONNECT,
+		.port = 0,
+	};
+
+	zassert_ok(ec_cmd_pd_write_log_entry(NULL, &params), NULL);
+	zassert_equal(sizeof(struct event_log_entry),
+		      log_dequeue_event(&fixture->log_entry), NULL);
+	zassert_equal(params.type, fixture->log_entry.type, NULL);
+	zassert_equal(0, fixture->log_entry.size, NULL);
+	zassert_equal(0, fixture->log_entry.data, NULL);
+	zassert_within(0, (int64_t)fixture->log_entry.timestamp, 10,
+		       "Expected timestamp %" PRIi64
+		       " to be within 10 ms of now",
+		       (int64_t)fixture->log_entry.timestamp);
+}
+
+ZTEST_USER_F(pd_log, test_read_log_entry)
+{
+	uint8_t response_buffer[MAX_RESPONSE_PD_LOG_ENTRY_SIZE];
+	struct ec_response_pd_log *response =
+		(struct ec_response_pd_log *)response_buffer;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_SIMPLE(EC_CMD_PD_GET_LOG_ENTRY, UINT8_C(0));
+
+	args.response = response;
+	args.response_max = sizeof(response_buffer);
+
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_equal(sizeof(struct event_log_entry), args.response_size, NULL);
+	zassert_equal(PD_EVENT_NO_ENTRY, response->type, NULL);
+}
+
+ZTEST_USER_F(pd_log, test_log_recv_vdm)
+{
+	uint8_t response_buffer[MAX_RESPONSE_PD_LOG_ENTRY_SIZE];
+	uint32_t *payload = (uint32_t *)response_buffer;
+	struct ec_response_pd_log *response =
+		(struct ec_response_pd_log *)&payload[1];
+
+	memset(response_buffer, 0, sizeof(response_buffer));
+	payload[0] |= VDO_SRC_RESPONDER;
+	response->type = PD_EVENT_MCU_CONNECT;
+	response->size_port = 8;
+	int cnt = DIV_ROUND_UP(response->size_port, sizeof(uint32_t)) + 2;
+
+	pd_log_recv_vdm(0, cnt, payload);
+
+	(void)log_dequeue_event(&fixture->log_entry);
+
+	zassert_equal(response->type, fixture->log_entry.type,
+		      "type=%d, received=%d", response->type,
+		      fixture->log_entry.type);
+}
diff --git a/zephyr/test/drivers/host_cmd/src/tablet_mode.c b/zephyr/test/drivers/host_cmd/src/tablet_mode.c
new file mode 100644
index 0000000000..4e7f0cd0f1
--- /dev/null
+++ b/zephyr/test/drivers/host_cmd/src/tablet_mode.c
@@ -0,0 +1,99 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_smart_battery.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "tablet_mode.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/ztest.h>
+
+struct host_cmd_tablet_mode_fixture {
+	const struct emul *emul;
+	struct i2c_common_emul_data *i2c_emul;
+};
+
+static void host_cmd_tablet_mode_before(void *f)
+{
+	ARG_UNUSED(f);
+	tablet_reset();
+}
+
+static void host_cmd_tablet_mode_after(void *f)
+{
+	ARG_UNUSED(f);
+	tablet_reset();
+}
+
+ZTEST_SUITE(host_cmd_tablet_mode, drivers_predicate_post_main, NULL,
+	    host_cmd_tablet_mode_before, host_cmd_tablet_mode_after, NULL);
+
+/* Test tablet mode can be enabled with a host command. */
+ZTEST_USER_F(host_cmd_tablet_mode, test_tablet_mode_on)
+{
+	int rv;
+	struct ec_params_set_tablet_mode params = {
+		.tablet_mode = TABLET_MODE_FORCE_TABLET
+	};
+
+	rv = ec_cmd_set_tablet_mode(NULL, &params);
+	zassert_equal(EC_RES_SUCCESS, rv, "Expected EC_RES_SUCCESS, but got %d",
+		      rv);
+	/* Return 1 if in tablet mode, 0 otherwise */
+	rv = tablet_get_mode();
+	zassert_equal(rv, 1, "unexpected tablet mode: %d", rv);
+}
+
+/* Test tablet mode can be disabled with a host command. */
+ZTEST_USER_F(host_cmd_tablet_mode, test_tablet_mode_off)
+{
+	int rv;
+	struct ec_params_set_tablet_mode params = {
+		.tablet_mode = TABLET_MODE_FORCE_CLAMSHELL
+	};
+
+	rv = ec_cmd_set_tablet_mode(NULL, &params);
+	zassert_equal(EC_RES_SUCCESS, rv, "Expected EC_RES_SUCCESS, but got %d",
+		      rv);
+	/* Return 1 if in tablet mode, 0 otherwise */
+	rv = tablet_get_mode();
+	zassert_equal(rv, 0, "unexpected tablet mode: %d", rv);
+}
+
+/* Test tablet mode can be reset with a host command. */
+ZTEST_USER_F(host_cmd_tablet_mode, test_tablet_mode_reset)
+{
+	int rv;
+	struct ec_params_set_tablet_mode params = {
+		.tablet_mode = TABLET_MODE_DEFAULT
+	};
+
+	rv = ec_cmd_set_tablet_mode(NULL, &params);
+	zassert_equal(EC_RES_SUCCESS, rv, "Expected EC_RES_SUCCESS, but got %d",
+		      rv);
+	/* Return 1 if in tablet mode, 0 otherwise */
+	rv = tablet_get_mode();
+	zassert_equal(rv, 0, "unexpected tablet mode: %d", rv);
+}
+
+/* Test tablet mode can handle invalid host command parameters. */
+ZTEST_USER_F(host_cmd_tablet_mode, test_tablet_mode_invalid_parameter)
+{
+	int rv;
+	struct ec_params_set_tablet_mode params = {
+		.tablet_mode = 0xEE /* Sufficiently random, bad value.*/
+	};
+
+	rv = ec_cmd_set_tablet_mode(NULL, &params);
+	zassert_equal(EC_RES_INVALID_PARAM, rv,
+		      "Expected EC_RES_INVALID_PARAM, but got %d", rv);
+	/* Return 1 if in tablet mode, 0 otherwise */
+	rv = tablet_get_mode();
+	zassert_equal(rv, 0, "unexpected tablet mode: %d", rv);
+}
diff --git a/zephyr/test/drivers/host_cmd/src/usb_pd_control.c b/zephyr/test/drivers/host_cmd/src/usb_pd_control.c
new file mode 100644
index 0000000000..93aeb33a45
--- /dev/null
+++ b/zephyr/test/drivers/host_cmd/src/usb_pd_control.c
@@ -0,0 +1,149 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "ec_commands.h"
+#include "emul/emul_isl923x.h"
+#include "emul/tcpc/emul_ps8xxx.h"
+#include "emul/tcpc/emul_tcpci.h"
+#include "emul/tcpc/emul_tcpci_partner_snk.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+#define TEST_PORT USBC_PORT_C0
+#define BAD_PORT 42
+
+struct host_cmd_usb_pd_control_fixture {
+	const struct emul *tcpci_emul;
+	const struct emul *charger_emul;
+	struct tcpci_partner_data partner;
+	struct tcpci_snk_emul_data snk_ext;
+};
+
+static enum ec_status
+run_usb_pd_control(int port, struct ec_response_usb_pd_control_v2 *resp)
+{
+	/*
+	 * Note: while arguments exist to change the PD state, their use is
+	 * discouraged as that causes the response to have non-deterministic
+	 * results.  The kernel only uses the "no change" parameters, so that is
+	 * what we shall test here.
+	 */
+	struct ec_params_usb_pd_control params = {
+		.port = port,
+		.role = USB_PD_CTRL_ROLE_NO_CHANGE,
+		.mux = USB_PD_CTRL_MUX_NO_CHANGE,
+		.swap = USB_PD_CTRL_SWAP_NONE
+	};
+
+	return ec_cmd_usb_pd_control_v2(NULL, &params, resp);
+}
+
+ZTEST_USER(host_cmd_usb_pd_control, test_good_index_no_partner)
+{
+	struct ec_response_usb_pd_control_v2 response;
+
+	zassert_ok(run_usb_pd_control(TEST_PORT, &response),
+		   "Failed to process usb_pd_control for port %d", TEST_PORT);
+
+	/* Verify basic not-connected expectations */
+	zassert_equal(response.enabled, 0,
+		      "Failed to find nothing enabled: 0x%02x",
+		      response.enabled);
+	/* Don't verify role, cc, or polarity as it isn't meaningful */
+	zassert_equal(response.control_flags, 0, "Failed to see flags cleared");
+}
+
+ZTEST_USER_F(host_cmd_usb_pd_control, test_good_index_sink_partner)
+{
+	struct ec_response_usb_pd_control_v2 response;
+
+	/* Attach simple sink that shouldn't do any swaps */
+	connect_sink_to_port(&fixture->partner, fixture->tcpci_emul,
+			     fixture->charger_emul);
+
+	/* Wait for connection to settle */
+	k_sleep(K_SECONDS(1));
+
+	zassert_ok(run_usb_pd_control(TEST_PORT, &response),
+		   "Failed to process usb_pd_control for port %d", TEST_PORT);
+
+	/* Verify basic sink expectations */
+	zassert_equal(
+		response.enabled,
+		(PD_CTRL_RESP_ENABLED_COMMS | PD_CTRL_RESP_ENABLED_CONNECTED |
+		 PD_CTRL_RESP_ENABLED_PD_CAPABLE),
+		"Failed to see full connection: 0x%02x", response.enabled);
+	/*
+	 * We should be source, DFP, Vconn source, and we set our sink caps
+	 * to USB comms
+	 */
+	zassert_equal(response.role,
+		      (PD_CTRL_RESP_ROLE_USB_COMM | PD_CTRL_RESP_ROLE_POWER |
+		       PD_CTRL_RESP_ROLE_DATA | PD_CTRL_RESP_ROLE_VCONN),
+		      "Failed to see expected role: 0x%02x", response.role);
+	zassert_equal(response.cc_state, PD_CC_UFP_ATTACHED,
+		      "Failed to see UFP attached");
+	zassert_equal(response.control_flags, 0, "Failed to see flags cleared");
+}
+
+ZTEST_USER(host_cmd_usb_pd_control, test_bad_index)
+{
+	struct ec_response_usb_pd_control_v2 response;
+
+	zassert_true(board_get_usb_pd_port_count() < BAD_PORT,
+		     "Intended bad port exists");
+	zassert_equal(run_usb_pd_control(BAD_PORT, &response),
+		      EC_RES_INVALID_PARAM,
+		      "Failed to fail usb_pd_control for port %d", BAD_PORT);
+}
+
+static void *host_cmd_usb_pd_control_setup(void)
+{
+	static struct host_cmd_usb_pd_control_fixture fixture;
+	struct tcpci_partner_data *partner = &fixture.partner;
+	struct tcpci_snk_emul_data *snk_ext = &fixture.snk_ext;
+
+	tcpci_partner_init(partner, PD_REV30);
+	partner->extensions = tcpci_snk_emul_init(snk_ext, partner, NULL);
+
+	/* Get references for the emulators */
+	fixture.tcpci_emul = EMUL_DT_GET(DT_NODELABEL(tcpci_emul));
+	fixture.charger_emul = EMUL_DT_GET(DT_NODELABEL(isl923x_emul));
+
+	/* Sink 5V 3A. */
+	snk_ext->pdo[0] = PDO_FIXED(5000, 3000, PDO_FIXED_COMM_CAP);
+
+	return &fixture;
+}
+
+static void host_cmd_usb_pd_control_before(void *data)
+{
+	ARG_UNUSED(data);
+
+	/* Assume we have at least one USB-C port */
+	zassert_true(board_get_usb_pd_port_count() > 0,
+		     "Insufficient TCPCs found");
+
+	/* Set the system into S0, since the AP would drive these commands */
+	test_set_chipset_to_s0();
+	k_sleep(K_SECONDS(1));
+}
+
+static void host_cmd_usb_pd_control_after(void *data)
+{
+	struct host_cmd_usb_pd_control_fixture *fixture = data;
+
+	disconnect_sink_from_port(fixture->tcpci_emul);
+	k_sleep(K_SECONDS(1));
+}
+
+ZTEST_SUITE(host_cmd_usb_pd_control, drivers_predicate_post_main,
+	    host_cmd_usb_pd_control_setup, host_cmd_usb_pd_control_before,
+	    host_cmd_usb_pd_control_after, NULL);
diff --git a/zephyr/test/drivers/host_cmd/src/usb_pd_host_cmd.c b/zephyr/test/drivers/host_cmd/src/usb_pd_host_cmd.c
new file mode 100644
index 0000000000..c197175b01
--- /dev/null
+++ b/zephyr/test/drivers/host_cmd/src/usb_pd_host_cmd.c
@@ -0,0 +1,171 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+#include "host_command.h"
+#include "test/drivers/test_state.h"
+#include "usb_pd.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+ZTEST_USER(usb_pd_host_cmd, test_hc_pd_host_event_status)
+{
+	struct ec_response_host_event_status response;
+	struct host_cmd_handler_args args;
+
+	/* Clear events */
+	zassert_ok(ec_cmd_pd_host_event_status(&args, &response));
+
+	/* Send arbitrary event */
+	pd_send_host_event(1);
+
+	zassert_ok(ec_cmd_pd_host_event_status(&args, &response));
+	zassert_equal(args.response_size, sizeof(response));
+	zassert_true(response.status & 1);
+
+	/* Send again to make sure the host command cleared the event */
+	zassert_ok(ec_cmd_pd_host_event_status(&args, &response));
+	zassert_equal(args.response_size, sizeof(response));
+	zassert_equal(response.status, 0);
+}
+
+static struct ec_params_usb_pd_rw_hash_entry *
+test_find_hc_remote_hash_entry(int dev_id)
+{
+	for (int i = 0; i < RW_HASH_ENTRIES; i++) {
+		if (rw_hash_table[i].dev_id == dev_id) {
+			return &rw_hash_table[i];
+		}
+	}
+
+	return NULL;
+}
+
+ZTEST_USER(usb_pd_host_cmd, test_hc_remote_hash_entry__bad_dev_id)
+{
+	struct ec_params_usb_pd_rw_hash_entry params = {
+		/* Dev ID can't be 0 */
+		.dev_id = 0,
+	};
+
+	zassert_equal(ec_cmd_usb_pd_rw_hash_entry(NULL, &params),
+		      EC_RES_INVALID_PARAM);
+}
+
+ZTEST_USER(usb_pd_host_cmd, test_hc_remote_hash_entry__add_entry)
+{
+	struct ec_params_usb_pd_rw_hash_entry params = {
+		/* Arbitrary dev_id */
+		.dev_id = 1,
+	};
+
+	memset(rw_hash_table, 0,
+	       RW_HASH_ENTRIES * sizeof(struct ec_params_usb_pd_rw_hash_entry));
+
+	zassert_ok(ec_cmd_usb_pd_rw_hash_entry(NULL, &params));
+	zassert_mem_equal(test_find_hc_remote_hash_entry(params.dev_id),
+			  &params, sizeof(params));
+}
+
+ZTEST_USER(usb_pd_host_cmd, test_hc_remote_hash_entry__update_entry)
+{
+	int arbitrary_dev_id = 1;
+	struct ec_params_usb_pd_rw_hash_entry initial_entry = {
+		.dev_id = arbitrary_dev_id,
+		/* Arbitrary reserved bytes */
+		.reserved = 7,
+	};
+	struct ec_params_usb_pd_rw_hash_entry update_entry = {
+		.dev_id = arbitrary_dev_id,
+		/* Arbitrary different reserved bytes */
+		.reserved = 3,
+	};
+
+	memset(rw_hash_table, 0,
+	       RW_HASH_ENTRIES * sizeof(struct ec_params_usb_pd_rw_hash_entry));
+
+	zassert_ok(ec_cmd_usb_pd_rw_hash_entry(NULL, &initial_entry));
+	zassert_mem_equal(test_find_hc_remote_hash_entry(initial_entry.dev_id),
+			  &initial_entry, sizeof(initial_entry));
+
+	zassert_ok(ec_cmd_usb_pd_rw_hash_entry(NULL, &update_entry));
+	zassert_mem_equal(test_find_hc_remote_hash_entry(update_entry.dev_id),
+			  &update_entry, sizeof(update_entry));
+}
+
+ZTEST_USER(usb_pd_host_cmd, test_host_command_hc_pd_ports)
+{
+	struct ec_response_usb_pd_ports response;
+	struct host_cmd_handler_args args;
+
+	zassert_ok(ec_cmd_usb_pd_ports(&args, &response));
+	zassert_equal(args.response_size, sizeof(response));
+	zassert_equal(response.num_ports, CONFIG_USB_PD_PORT_MAX_COUNT);
+}
+
+ZTEST_USER(usb_pd_host_cmd, test_typec_discovery_invalid_args)
+{
+	struct ec_params_typec_discovery params = {
+		.port = 100,
+		.partner_type = TYPEC_PARTNER_SOP,
+	};
+	struct ec_response_typec_discovery response;
+	/* A successful EC_CMD_TYPEC_DISCOVERY requires response to be larger
+	 * than ec_params_typec_discovery, but this one is expected to fail, so
+	 * the response size is irrelevant.
+	 */
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_TYPEC_DISCOVERY, 0, response, params);
+
+	zassert_equal(host_command_process(&args), EC_RES_INVALID_PARAM);
+
+	params.port = 0;
+	/* This is not a valid enum value but should be representable. */
+	params.partner_type = 5;
+	zassert_equal(host_command_process(&args), EC_RES_INVALID_PARAM);
+}
+
+ZTEST_USER(usb_pd_host_cmd, test_typec_control_invalid_args)
+{
+	struct ec_params_typec_control params = {
+		.port = 0,
+		.command = TYPEC_CONTROL_COMMAND_TBT_UFP_REPLY,
+	};
+
+	/* Setting the TBT UFP responses is not supported by default. */
+	zassert_equal(ec_cmd_typec_control(NULL, &params), EC_RES_UNAVAILABLE);
+
+	/* Neither is mux setting. */
+	params.command = TYPEC_CONTROL_COMMAND_USB_MUX_SET;
+	zassert_equal(ec_cmd_typec_control(NULL, &params),
+		      EC_RES_INVALID_PARAM);
+
+	/* This is not a valid enum value but should be representable. */
+	params.command = 0xff;
+	zassert_equal(ec_cmd_typec_control(NULL, &params),
+		      EC_RES_INVALID_PARAM);
+}
+
+ZTEST_USER(usb_pd_host_cmd, test_typec_status_invalid_args)
+{
+	struct ec_params_typec_status params = {
+		.port = 100,
+	};
+	struct ec_response_typec_status response;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_TYPEC_STATUS, 0, response, params);
+
+	/* An invalid port should result in an error. */
+	zassert_equal(ec_cmd_typec_status(NULL, &params, &response),
+		      EC_RES_INVALID_PARAM);
+
+	params.port = 0;
+	args.response_max = sizeof(struct ec_response_typec_status) - 1;
+	zassert_equal(host_command_process(&args), EC_RES_RESPONSE_TOO_BIG);
+}
+
+ZTEST_SUITE(usb_pd_host_cmd, drivers_predicate_post_main, NULL, NULL, NULL,
+	    NULL);
diff --git a/zephyr/test/drivers/host_cmd_read_memmap/CMakeLists.txt b/zephyr/test/drivers/host_cmd_read_memmap/CMakeLists.txt
new file mode 100644
index 0000000000..dedb9f801f
--- /dev/null
+++ b/zephyr/test/drivers/host_cmd_read_memmap/CMakeLists.txt
@@ -0,0 +1,7 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_sources(app PRIVATE
+    src/read_memmap.c
+)
diff --git a/zephyr/test/drivers/host_cmd_read_memmap/src/read_memmap.c b/zephyr/test/drivers/host_cmd_read_memmap/src/read_memmap.c
new file mode 100644
index 0000000000..88472a3467
--- /dev/null
+++ b/zephyr/test/drivers/host_cmd_read_memmap/src/read_memmap.c
@@ -0,0 +1,96 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+#include "host_command.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/fff.h>
+#include <zephyr/ztest.h>
+
+#ifndef CONFIG_PLATFORM_EC_SWITCH
+FAKE_VOID_FUNC(switch_interrupt, int);
+#endif
+
+ZTEST(ec_cmd_read_memmap, test_id)
+{
+	struct ec_params_read_memmap params = {
+		.offset = EC_MEMMAP_ID,
+		.size = 2,
+	};
+	uint8_t response[2];
+	int rv;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_READ_MEMMAP, 0, response, params);
+
+	rv = host_command_process(&args);
+
+	if (IS_ENABLED(CONFIG_HOSTCMD_X86)) {
+		zassert_equal(rv, EC_RES_INVALID_COMMAND, "Got %d", rv);
+		return;
+	}
+
+	zassert_ok(rv, "Got %d", rv);
+	/* Response should be 'E' 'C' */
+	zassert_equal('E', response[0]);
+	zassert_equal('C', response[1]);
+}
+
+ZTEST(ec_cmd_read_memmap, test_switches)
+{
+	struct ec_params_read_memmap params = {
+		.offset = EC_MEMMAP_SWITCHES,
+		.size = 1,
+	};
+	uint8_t response[1];
+	int rv;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_READ_MEMMAP, 0, response, params);
+
+	rv = host_command_process(&args);
+
+	if (IS_ENABLED(CONFIG_HOSTCMD_X86)) {
+		zassert_equal(rv, EC_RES_INVALID_COMMAND, "Got %d", rv);
+		return;
+	}
+
+	/* This test suite is run with CONFIG_PLATFORM_EC_SWITCH enabled
+	 * and disabled.
+	 */
+	if (IS_ENABLED(CONFIG_PLATFORM_EC_SWITCH)) {
+		zassert_ok(rv, "Got %d", rv);
+	} else {
+		zassert_equal(rv, EC_RES_UNAVAILABLE, "Got %d", rv);
+	}
+}
+
+ZTEST(ec_cmd_read_memmap, test_invalid)
+{
+	struct ec_params_read_memmap params = {
+		.offset = EC_MEMMAP_ID,
+		.size = UINT8_MAX,
+	};
+	uint8_t response[2];
+	int rv;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_READ_MEMMAP, 0, response, params);
+
+	rv = host_command_process(&args);
+
+	if (IS_ENABLED(CONFIG_HOSTCMD_X86)) {
+		zassert_equal(rv, EC_RES_INVALID_COMMAND, "Got %d", rv);
+		return;
+	}
+
+	/* Verify offset+size exceeding max fails */
+	zassert_equal(rv, EC_RES_INVALID_PARAM, "Got %d", rv);
+
+	/* Verify params.size > response_max fails */
+	params.size = 4;
+	zassert_equal(host_command_process(&args), EC_RES_INVALID_PARAM);
+}
+
+ZTEST_SUITE(ec_cmd_read_memmap, drivers_predicate_post_main, NULL, NULL, NULL,
+	    NULL);
diff --git a/zephyr/test/drivers/host_command_memory_dump/CMakeLists.txt b/zephyr/test/drivers/host_command_memory_dump/CMakeLists.txt
new file mode 100644
index 0000000000..b0fef92c10
--- /dev/null
+++ b/zephyr/test/drivers/host_command_memory_dump/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Add source files
+target_sources(app PRIVATE src/host_command_memory_dump.c)
diff --git a/zephyr/test/drivers/host_command_memory_dump/src/host_command_memory_dump.c b/zephyr/test/drivers/host_command_memory_dump/src/host_command_memory_dump.c
new file mode 100644
index 0000000000..373c066a3c
--- /dev/null
+++ b/zephyr/test/drivers/host_command_memory_dump/src/host_command_memory_dump.c
@@ -0,0 +1,364 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+#include "ec_tasks.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "host_command_memory_dump.h"
+#include "test/drivers/test_state.h"
+
+#include <stdlib.h>
+
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+#include <zephyr/ztest_assert.h>
+
+void register_thread_memory_dump(k_tid_t thread);
+
+/* Simple local structs for storing a memory dump */
+struct mem_dump {
+	uint16_t count;
+	struct mem_segment *segments;
+};
+struct mem_segment {
+	uint32_t addr;
+	uint32_t size;
+	uint8_t *mem;
+};
+
+/* Utility function for sending a host command.
+ * Provides more fine grained control over parameters compared to
+ * common host command macros.
+ */
+static enum ec_status send_host_command(int command, int version,
+					const void *params, int params_size,
+					void *resp, int resp_max,
+					int *resp_size)
+{
+	int rv;
+	struct host_cmd_handler_args args;
+
+	args.version = version;
+	args.command = command;
+	args.params = params;
+	args.params_size = params_size;
+	args.response = resp;
+	args.response_max = resp_max;
+	args.response_size = 0;
+
+	rv = host_command_process(&args);
+
+	if (rv == EC_RES_SUCCESS && resp_size) {
+		*resp_size = args.response_size;
+	}
+
+	return rv;
+}
+
+static void before(void *data)
+{
+	clear_memory_dump();
+}
+
+K_THREAD_STACK_DEFINE(test_stack, 256);
+
+static void test_thread_entry(void *a, void *b, void *c)
+{
+	while (true) {
+		k_msleep(1000);
+	}
+}
+
+/* Check if a buffer contains a given value */
+static bool buffer_contains(const void *buffer, size_t buffer_size,
+			    const void *value, size_t value_size)
+{
+	if (buffer == NULL || value == NULL) {
+		return false;
+	}
+
+	if (value_size > buffer_size) {
+		return false;
+	}
+
+	for (size_t i = 0; i <= buffer_size - value_size; i++) {
+		if (memcmp((const char *)buffer + i, value, value_size) == 0) {
+			return true;
+		}
+	}
+	return false;
+}
+
+/* Free a malloc'd memory dump structure */
+static void free_mem_dump(struct mem_dump *dump)
+{
+	for (int i = 0; i < dump->count; i++) {
+		free(dump->segments[i].mem);
+	}
+	free(dump->segments);
+}
+
+/*
+ * This utility function is similar to memcpy, but uses a mem_dump struct
+ * as the source memory. The requested memory may span multiple memory segments.
+ * The memory segments are not ordered.
+ */
+static void *memcpy_from_dump(struct mem_dump *dump, void *dest,
+			      const uint32_t src_addr, size_t size)
+{
+	size_t offset = 0;
+
+	while (offset < size) {
+		int seg;
+		/* Find the memory segment that contains the source
+		 * address + offset.
+		 */
+		for (seg = 0; seg < dump->count; seg++) {
+			if (src_addr + offset >= dump->segments[seg].addr &&
+			    src_addr + offset <
+				    dump->segments[seg].addr +
+					    dump->segments[seg].size) {
+				break;
+			}
+		}
+		/* Requested memory not found */
+		if (seg >= dump->count) {
+			return NULL;
+		}
+		/* Size of the memory segment, starting from the source address
+		 */
+		size_t segment_size =
+			dump->segments[seg].size -
+			(src_addr + offset - dump->segments[seg].addr);
+		/* Clamp copy size to min of remaining size and segment_size */
+		size_t copy_size = MIN(size - offset, segment_size);
+
+		zassert_not_null(memcpy(((uint8_t *)dest + offset),
+					dump->segments[seg].mem + offset,
+					copy_size));
+		offset += copy_size;
+	}
+
+	return dest;
+}
+
+/* Util function for fetching a memory dump using host commands. */
+static enum ec_status fetch_memory_dump(struct mem_dump *dump)
+{
+	struct ec_response_memory_dump_get_metadata metadata_response;
+	struct ec_response_get_protocol_info protocol_info_response;
+
+	zassert_ok(send_host_command(EC_CMD_GET_PROTOCOL_INFO, 0, NULL, 0,
+				     &protocol_info_response,
+				     sizeof(protocol_info_response), NULL));
+
+	zassert_ok(send_host_command(EC_CMD_MEMORY_DUMP_GET_METADATA, 0, NULL,
+				     0, &metadata_response,
+				     sizeof(metadata_response), NULL));
+
+	dump->count = metadata_response.memory_dump_entry_count;
+	dump->segments = (struct mem_segment *)malloc(
+		sizeof(struct mem_segment) *
+		metadata_response.memory_dump_entry_count);
+
+	for (int seg = 0; seg < metadata_response.memory_dump_entry_count;
+	     seg++) {
+		struct ec_params_memory_dump_get_entry_info entry_info_params = {
+			.memory_dump_entry_index = seg
+		};
+		struct ec_response_memory_dump_get_entry_info
+			entry_info_response;
+
+		zassert_ok(send_host_command(
+			EC_CMD_MEMORY_DUMP_GET_ENTRY_INFO, 0,
+			&entry_info_params, sizeof(entry_info_params),
+			&entry_info_response, sizeof(entry_info_response),
+			NULL));
+
+		dump->segments[seg].addr = entry_info_response.address;
+		dump->segments[seg].size = entry_info_response.size;
+		dump->segments[seg].mem =
+			(uint8_t *)malloc(entry_info_response.size);
+
+		uint32_t offset = 0;
+
+		while (offset < entry_info_response.size) {
+			struct ec_params_memory_dump_read_memory
+				read_mem_params = {
+					.memory_dump_entry_index = seg,
+					.address = entry_info_response.address +
+						   offset,
+					.size = entry_info_response.size -
+						offset,
+				};
+			uint16_t response_max =
+				protocol_info_response.max_response_packet_size;
+			uint8_t *read_mem_response = malloc(response_max);
+			int response_size = 0;
+
+			zassert_ok(send_host_command(
+				EC_CMD_MEMORY_DUMP_READ_MEMORY, 0,
+				&read_mem_params, sizeof(read_mem_params),
+				read_mem_response, response_max,
+				&response_size));
+
+			zassert_true(response_size > 0 &&
+				     response_size < response_max);
+
+			zassert_not_null(
+				memcpy(dump->segments[seg].mem + offset,
+				       read_mem_response, response_size));
+
+			offset += response_size;
+		};
+	}
+	return EC_RES_SUCCESS;
+}
+
+/*
+ * Ensure that a memory dump returns empty list if requested before being
+ * initialized.
+ */
+ZTEST_USER(memory_dump, test_dump_before_registered)
+{
+	struct ec_response_memory_dump_get_metadata metadata_response;
+	int rv;
+
+	struct host_cmd_handler_args args = BUILD_HOST_COMMAND_RESPONSE(
+		EC_CMD_MEMORY_DUMP_GET_METADATA, 0, metadata_response);
+
+	rv = host_command_process(&args);
+
+	zassert_equal(metadata_response.memory_dump_entry_count, 0);
+}
+
+/* Check if thread stack is included in memory dump */
+ZTEST_USER(memory_dump, test_dump_thread_stack)
+{
+	const uint32_t magic_val_1 = 0x11111111;
+	const uint32_t magic_val_2 = 0x22222222;
+	const uint32_t magic_val_3 = 0x33333333;
+	struct mem_dump dump;
+	uint8_t *test_stack_from_dump;
+	struct k_thread test_thread_data;
+
+	/* Create a new thread and pass magic values as initial parameters */
+	k_tid_t test_thread = k_thread_create(
+		&test_thread_data, test_stack,
+		K_THREAD_STACK_SIZEOF(test_stack), test_thread_entry,
+		(void *)magic_val_1, (void *)magic_val_2, (void *)magic_val_3,
+		1, 0, K_NO_WAIT);
+
+	/* Wait for the thread to start */
+	k_msleep(100);
+
+	zassert_true(buffer_contains((uint8_t *)test_thread->stack_info.start,
+				     test_thread->stack_info.size, &magic_val_1,
+				     4));
+	zassert_true(buffer_contains((uint8_t *)test_thread->stack_info.start,
+				     test_thread->stack_info.size, &magic_val_2,
+				     4));
+	zassert_true(buffer_contains((uint8_t *)test_thread->stack_info.start,
+				     test_thread->stack_info.size, &magic_val_3,
+				     4));
+
+	/* Test thread isn't a known thread, so add it here */
+	register_thread_memory_dump(test_thread);
+
+	/* Stop test thread */
+	k_thread_abort(test_thread);
+
+	/* Fetch memory dump */
+	fetch_memory_dump(&dump);
+
+	/* Allocate buffer for thread stack */
+	test_stack_from_dump = (uint8_t *)malloc(test_thread->stack_info.size);
+
+	zassert_not_null(test_stack_from_dump);
+
+	/* Copy stack from memory dump */
+	zassert_not_null(memcpy_from_dump(&dump, test_stack_from_dump,
+					  test_thread->stack_info.start,
+					  test_thread->stack_info.size));
+
+	/* Search for magic values in fetched stack memory */
+	zassert_true(buffer_contains(test_stack_from_dump,
+				     test_thread->stack_info.size, &magic_val_1,
+				     4));
+	zassert_true(buffer_contains(test_stack_from_dump,
+				     test_thread->stack_info.size, &magic_val_2,
+				     4));
+	zassert_true(buffer_contains(test_stack_from_dump,
+				     test_thread->stack_info.size, &magic_val_3,
+				     4));
+
+	/* Cleanup */
+	free(test_stack_from_dump);
+	free_mem_dump(&dump);
+}
+
+/* Check if keyscan thread stack is included in memory dump */
+ZTEST_USER(memory_dump, test_verify_excluded_threads_not_dumped)
+{
+	struct mem_dump dump;
+	k_tid_t main_thread;
+	k_tid_t keyscan_thread;
+	k_tid_t keyproto_thread;
+	__maybe_unused k_tid_t wov_thread;
+	bool main_stack_found;
+
+	main_thread = get_main_thread();
+	zassert_not_null(main_thread);
+	keyscan_thread = task_id_to_thread_id(TASK_ID_KEYSCAN);
+	zassert_not_null(keyscan_thread);
+	keyproto_thread = task_id_to_thread_id(TASK_ID_KEYPROTO);
+	zassert_not_null(keyproto_thread);
+#ifdef HAS_TASK_WOV
+	wov_thread = task_id_to_thread_id(TASK_ID_WOV);
+	zassert_not_null(wov_thread);
+#endif /* HAS_TASK_WOV */
+
+	/* Thread memory should be registered after HOOK_INIT */
+	hook_notify(HOOK_INIT);
+	/* Fetch memory dump */
+	fetch_memory_dump(&dump);
+
+	/*
+	 * Verify KEYSCAN and KEYPROTO thread stacks are NOT in dump.
+	 * Also verify main thread stack IS in dump (i.e. not empty).
+	 */
+	main_stack_found = false;
+	for (int i = 0; i < dump.count; i++) {
+		struct mem_segment seg = dump.segments[i];
+
+		zassert_false(
+			seg.addr < keyscan_thread->stack_info.start +
+					   keyscan_thread->stack_info.size &&
+			seg.addr + seg.size > keyscan_thread->stack_info.start);
+		zassert_false(
+			seg.addr < keyproto_thread->stack_info.start +
+					   keyproto_thread->stack_info.size &&
+			seg.addr + seg.size >
+				keyproto_thread->stack_info.start);
+#ifdef HAS_TASK_WOV
+		zassert_false(seg.addr < wov_thread->stack_info.start +
+						 wov_thread->stack_info.size &&
+			      seg.addr + seg.size >
+				      wov_thread->stack_info.start);
+#endif /* HAS_TASK_WOV */
+		if (seg.addr < main_thread->stack_info.start +
+				       main_thread->stack_info.size &&
+		    seg.addr + seg.size > main_thread->stack_info.start) {
+			main_stack_found = true;
+		}
+	}
+	zassert_true(main_stack_found);
+
+	/* Cleanup */
+	free_mem_dump(&dump);
+}
+
+ZTEST_SUITE(memory_dump, NULL, NULL, before, NULL, NULL);
diff --git a/zephyr/test/drivers/host_command_thread/CMakeLists.txt b/zephyr/test/drivers/host_command_thread/CMakeLists.txt
new file mode 100644
index 0000000000..9386414deb
--- /dev/null
+++ b/zephyr/test/drivers/host_command_thread/CMakeLists.txt
@@ -0,0 +1,5 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_sources(app PRIVATE src/main.c)
diff --git a/zephyr/test/drivers/host_command_thread/src/main.c b/zephyr/test/drivers/host_command_thread/src/main.c
new file mode 100644
index 0000000000..8cf0cfc958
--- /dev/null
+++ b/zephyr/test/drivers/host_command_thread/src/main.c
@@ -0,0 +1,94 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file main.c
+ *
+ * WARNING:
+ *   Do not add tests to this binary. This test messes with the main thread and
+ *   can only run a single test function.
+ */
+#include "host_command.h"
+#include "task.h"
+#include "test/drivers/test_state.h"
+
+#include <string.h>
+
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+#define CUSTOM_COMMAND_ID 0x8888
+
+/* Thread id of fake main thread */
+static k_tid_t fake_main_tid;
+
+/* 0 - did not run, 1 - true, -1 - false */
+static int last_check_main_thread_result;
+
+static enum ec_status check_main_thread(struct host_cmd_handler_args *args)
+{
+	last_check_main_thread_result =
+		(k_current_get() == get_main_thread() ? 1 : -1);
+	return EC_RES_SUCCESS;
+}
+
+DECLARE_HOST_COMMAND(CUSTOM_COMMAND_ID, check_main_thread, EC_VER_MASK(0));
+
+static void fake_main_thread(void *a, void *b, void *c)
+{
+	host_command_main();
+}
+
+K_THREAD_STACK_DEFINE(fake_main_thread_stack, 4000);
+
+/* Override get_hostcmd_thread() from shim/src/tasks.c so
+ * task_get_current() returns TASK_ID_HOSTCMD when fake main thread
+ * is running.
+ */
+k_tid_t get_hostcmd_thread(void)
+{
+	return fake_main_tid;
+}
+
+ZTEST_SUITE(host_cmd_thread, drivers_predicate_post_main, NULL, NULL, NULL,
+	    NULL);
+
+ZTEST(host_cmd_thread, test_takeover)
+{
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_SIMPLE(CUSTOM_COMMAND_ID, 0);
+	const char expected_thread_name[] = "HOSTCMD";
+	struct k_thread fake_main_thread_data;
+
+	fake_main_tid = k_thread_create(
+		&fake_main_thread_data, fake_main_thread_stack,
+		K_THREAD_STACK_SIZEOF(fake_main_thread_stack), fake_main_thread,
+		NULL, NULL, NULL, 1, 0, K_NO_WAIT);
+
+	/* Wait for the thread to start */
+	k_msleep(500);
+
+	/* Get the name of the thread (must be done after the sleep) */
+	const char *main_thread_name = k_thread_name_get(get_main_thread());
+
+	/* Verify that the thread is not the hostcmd thread */
+	zassert_equal(EC_TASK_PRIORITY(EC_TASK_HOSTCMD_PRIO),
+		      k_thread_priority_get(get_main_thread()));
+	zassert_equal(strlen(expected_thread_name), strlen(main_thread_name));
+	zassert_mem_equal(expected_thread_name, main_thread_name,
+			  strlen(expected_thread_name));
+
+	/* Try running a host command */
+	host_command_received(&args);
+	k_msleep(1000);
+
+	/* Make sure that the host command ran, the result should be -1 because
+	 * it's not the original main thread.
+	 */
+	zassert_equal(-1, last_check_main_thread_result);
+
+	/* Kill the extra thread */
+	k_thread_abort(fake_main_tid);
+}
diff --git a/zephyr/test/drivers/i2c_controller/CMakeLists.txt b/zephyr/test/drivers/i2c_controller/CMakeLists.txt
new file mode 100644
index 0000000000..995146f493
--- /dev/null
+++ b/zephyr/test/drivers/i2c_controller/CMakeLists.txt
@@ -0,0 +1,10 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}/include")
+
+target_sources(app PRIVATE
+  src/basic_i2c_device_emul.c
+  src/i2c_controller.c
+)
diff --git a/zephyr/test/drivers/i2c_controller/i2c.dts b/zephyr/test/drivers/i2c_controller/i2c.dts
new file mode 100644
index 0000000000..e36a6484c8
--- /dev/null
+++ b/zephyr/test/drivers/i2c_controller/i2c.dts
@@ -0,0 +1,13 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+&i2c0 {
+	/* Add a test I2C define */
+	basic_i2c_device: basic_i2c_device@ec {
+		compatible = "basic-i2c-device";
+		status = "okay";
+		reg = <0xec>;
+	};
+};
diff --git a/zephyr/test/drivers/i2c_controller/include/basic_i2c_device_emul.h b/zephyr/test/drivers/i2c_controller/include/basic_i2c_device_emul.h
new file mode 100644
index 0000000000..c235d64825
--- /dev/null
+++ b/zephyr/test/drivers/i2c_controller/include/basic_i2c_device_emul.h
@@ -0,0 +1,27 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "emul/emul_common_i2c.h"
+
+#include <stdint.h>
+
+#define BASIC_I2C_DEV_EXT_ACCESS_REG 0xFF
+
+/**
+ * @brief Emulator state struct
+ *
+ */
+struct basic_i2c_device_data {
+	struct i2c_common_emul_data common;
+	uint8_t regs[256];
+	uint8_t extended_regs[256];
+};
+
+/**
+ * @brief Resets the internal register store to default
+ *
+ * @param emul Pointer to the emulator object
+ */
+void basic_i2c_device_reset(const struct emul *emul);
diff --git a/zephyr/test/drivers/i2c_controller/src/basic_i2c_device_emul.c b/zephyr/test/drivers/i2c_controller/src/basic_i2c_device_emul.c
new file mode 100644
index 0000000000..926fa6152f
--- /dev/null
+++ b/zephyr/test/drivers/i2c_controller/src/basic_i2c_device_emul.c
@@ -0,0 +1,112 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "basic_i2c_device_emul.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_stub_device.h"
+
+#include <string.h>
+
+#include <zephyr/device.h>
+
+#define DT_DRV_COMPAT basic_i2c_device
+
+void basic_i2c_device_reset(const struct emul *emul)
+{
+	struct basic_i2c_device_data *data =
+		(struct basic_i2c_device_data *)emul->data;
+
+	memset(data->regs, 0, sizeof(data->regs));
+	memset(data->extended_regs, 0, sizeof(data->extended_regs));
+}
+
+static int basic_i2c_device_write(const struct emul *emul, int reg, uint8_t val,
+				  int bytes, void *unused_data)
+{
+	struct basic_i2c_device_data *data =
+		(struct basic_i2c_device_data *)emul->data;
+
+	uint8_t *regs;
+
+	if (data->regs[BASIC_I2C_DEV_EXT_ACCESS_REG]) {
+		/* Accessing the extended register set */
+		regs = data->extended_regs;
+
+		/* Decrement one to account for the extended access reg byte */
+		reg = data->regs[BASIC_I2C_DEV_EXT_ACCESS_REG] - 1;
+	} else {
+		regs = data->regs;
+	}
+
+	int pos = reg + bytes - 1;
+
+	if (!IN_RANGE(pos, 0, sizeof(data->regs) - 1)) {
+		return -1;
+	}
+	regs[pos] = val;
+
+	return 0;
+}
+
+static int basic_i2c_device_read(const struct emul *emul, int reg, uint8_t *val,
+				 int bytes, void *unused_data)
+{
+	struct basic_i2c_device_data *data =
+		(struct basic_i2c_device_data *)emul->data;
+
+	uint8_t *regs;
+
+	if (data->regs[BASIC_I2C_DEV_EXT_ACCESS_REG]) {
+		/* Accessing the extended register set */
+		regs = data->extended_regs;
+		reg = data->regs[BASIC_I2C_DEV_EXT_ACCESS_REG];
+	} else {
+		regs = data->regs;
+	}
+
+	int pos = reg + bytes;
+
+	if (!IN_RANGE(pos, 0, sizeof(data->regs) - 1)) {
+		return -1;
+	}
+	*val = regs[pos];
+
+	return 0;
+}
+
+static int basic_i2c_device_init(const struct emul *emul,
+				 const struct device *parent)
+{
+	struct basic_i2c_device_data *data =
+		(struct basic_i2c_device_data *)emul->data;
+	struct i2c_common_emul_data *common_data = &data->common;
+
+	i2c_common_emul_init(common_data);
+	i2c_common_emul_set_read_func(common_data, basic_i2c_device_read, NULL);
+	i2c_common_emul_set_write_func(common_data, basic_i2c_device_write,
+				       NULL);
+
+	basic_i2c_device_reset(emul);
+
+	return 0;
+}
+
+#define INIT_BASIC_I2C_DEVICE_EMUL(n)                                     \
+	static struct i2c_common_emul_cfg common_cfg_##n;                 \
+	static struct basic_i2c_device_data basic_i2c_device_data_##n;    \
+	static struct i2c_common_emul_cfg common_cfg_##n = {              \
+		.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)),           \
+		.data = &basic_i2c_device_data_##n.common,                \
+		.addr = DT_INST_REG_ADDR(n)                               \
+	};                                                                \
+	static struct basic_i2c_device_data basic_i2c_device_data_##n = { \
+		.common = { .cfg = &common_cfg_##n }                      \
+	};                                                                \
+	EMUL_DT_INST_DEFINE(n, basic_i2c_device_init,                     \
+			    &basic_i2c_device_data_##n, &common_cfg_##n,  \
+			    &i2c_common_emul_api, NULL)
+
+DT_INST_FOREACH_STATUS_OKAY(INIT_BASIC_I2C_DEVICE_EMUL);
+
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
diff --git a/zephyr/test/drivers/i2c_controller/src/i2c_controller.c b/zephyr/test/drivers/i2c_controller/src/i2c_controller.c
new file mode 100644
index 0000000000..1044d14cd7
--- /dev/null
+++ b/zephyr/test/drivers/i2c_controller/src/i2c_controller.c
@@ -0,0 +1,421 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "basic_i2c_device_emul.h"
+#include "i2c.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/device.h>
+#include <zephyr/fff.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/ztest.h>
+
+struct i2c_controller_fixture {
+	int port;
+	int addr;
+	const struct emul *emul;
+	struct basic_i2c_device_data *emul_data;
+};
+
+ZTEST_F(i2c_controller, test_write_read32_le)
+{
+	uint32_t expected = 0xAABBCCDD;
+	uint32_t actual;
+
+	zassert_ok(i2c_write32(fixture->port, fixture->addr, 0, expected));
+
+	/* Get the first four bytes of the register space as a uint32_t */
+	actual = *((uint32_t *)&fixture->emul_data->regs[0]);
+
+	zassert_equal(expected, actual, "got %08x, expected %08x", actual,
+		      expected);
+
+	/* Now read back through I2C API */
+	zassert_ok(i2c_read32(fixture->port, fixture->addr, 0, &actual));
+
+	zassert_equal(expected, actual, "got %08x, expected %08x", actual,
+		      expected);
+}
+
+ZTEST_F(i2c_controller, test_write_read32_be)
+{
+	uint32_t expected = 0xAABBCCDD;
+	uint32_t actual;
+
+	zassert_ok(i2c_write32(fixture->port,
+			       fixture->addr | I2C_FLAG_BIG_ENDIAN, 0,
+			       expected));
+
+	/* Get the first four bytes of the register space as a uint32_t */
+	actual = __bswap_32(*((uint32_t *)&fixture->emul_data->regs[0]));
+
+	zassert_equal(expected, actual, "got %08x, expected %08x", actual,
+		      expected);
+
+	/* Now read back through I2C API */
+	zassert_ok(i2c_read32(fixture->port,
+			      fixture->addr | I2C_FLAG_BIG_ENDIAN, 0, &actual));
+
+	zassert_equal(expected, actual, "got %08x, expected %08x", actual,
+		      expected);
+}
+
+ZTEST_F(i2c_controller, test_write_read16_be)
+{
+	uint16_t expected = 0x1122;
+	int actual;
+
+	zassert_ok(i2c_write16(fixture->port,
+			       fixture->addr | I2C_FLAG_BIG_ENDIAN, 0,
+			       expected));
+
+	/* Get the first two bytes of the register space as a uint16_t */
+	actual = __bswap_16(*((uint16_t *)&fixture->emul_data->regs[0]));
+
+	zassert_equal(expected, actual, "got %04x, expected %08x", actual,
+		      expected);
+
+	/* Now read back through I2C API */
+	zassert_ok(i2c_read16(fixture->port,
+			      fixture->addr | I2C_FLAG_BIG_ENDIAN, 0, &actual));
+
+	zassert_equal(expected, actual, "got %04x, expected %04x",
+		      (uint16_t)actual, expected);
+}
+
+ZTEST_F(i2c_controller, test_read32_fail)
+{
+	int ret;
+	uint32_t data;
+
+	/* Fail by reading from wrong address */
+	ret = i2c_read32(fixture->port, fixture->addr + 1, 0, &data);
+
+	zassert_equal(EC_ERROR_INVAL, ret, "Got %d", ret);
+}
+
+ZTEST_F(i2c_controller, test_write32_fail)
+{
+	int ret;
+
+	/* Fail by writing to wrong address */
+	ret = i2c_write32(fixture->port, fixture->addr + 1, 0, 0x00000000);
+
+	zassert_equal(EC_ERROR_INVAL, ret, "Got %d", ret);
+}
+
+ZTEST_F(i2c_controller, test_field_update16)
+{
+	/* Write a 16-bit value with mask */
+
+	uint16_t mask = 0xFFFF;
+	uint16_t set_value = 0x1234;
+	uint16_t actual;
+
+	zassert_ok(i2c_field_update16(fixture->port, fixture->addr, 0, mask,
+				      set_value));
+
+	/* Get the first two bytes of the register space as a uint16_t */
+	actual = *((uint16_t *)&fixture->emul_data->regs[0]);
+
+	zassert_equal(set_value, actual, "got %04x, expected %04x", actual,
+		      set_value);
+
+	/* Force a failure */
+	set_value = 0x0001;
+	mask = 0x0001;
+	i2c_common_emul_set_read_fail_reg(&fixture->emul_data->common, 0);
+	zassert_equal(i2c_field_update16(fixture->port, fixture->addr, 0, mask,
+					 set_value),
+		      EC_ERROR_INVAL);
+}
+
+ZTEST_F(i2c_controller, test_read_offset16__one_byte)
+{
+	/* Read 1 byte from a 16-bit register offset, which will cause us to
+	 * access the extended register space of our i2c device
+	 */
+	int data = 0;
+	uint16_t reg = 0xFF01;
+	uint8_t expected = 0xAB;
+
+	fixture->emul_data->extended_regs[reg & 0xFF] = expected;
+
+	zassert_ok(
+		i2c_read_offset16(fixture->port, fixture->addr, reg, &data, 1));
+
+	zassert_equal(expected, data, "got %02x, expected %02x", data,
+		      expected);
+}
+
+ZTEST_F(i2c_controller, test_read_offset16__two_bytes)
+{
+	/* Read 2 bytes from a 16-bit register offset, which will cause us to
+	 * access the extended register space of our i2c device
+	 */
+	int data = 0;
+	uint16_t reg = 0xFF01;
+	uint16_t expected = 0xABCD;
+
+	*((uint16_t *)&fixture->emul_data->extended_regs[reg & 0xFF]) =
+		expected;
+
+	zassert_ok(
+		i2c_read_offset16(fixture->port, fixture->addr, reg, &data, 2));
+
+	zassert_equal(expected, data, "got %04x, expected %04x", data,
+		      expected);
+}
+
+ZTEST_F(i2c_controller, test_read_offset16__two_bytes_be)
+{
+	/* Read 2 bytes from a 16-bit register offset, which will cause us to
+	 * access the extended register space of our i2c device
+	 */
+	int data = 0;
+	uint16_t reg = 0xFF01;
+	uint16_t expected = 0xABCD;
+
+	*((uint16_t *)&fixture->emul_data->extended_regs[reg & 0xFF]) =
+		expected;
+
+	zassert_ok(i2c_read_offset16(fixture->port,
+				     fixture->addr | I2C_FLAG_BIG_ENDIAN, reg,
+				     &data, 2));
+
+	uint16_t data16 = __bswap_16((uint16_t)data);
+
+	zassert_equal(expected, data16, "got %04x, expected %04x", data16,
+		      expected);
+}
+
+ZTEST_F(i2c_controller, test_read_offset16__invalid)
+{
+	/* Check length limits */
+	zassert_ok(
+		!i2c_read_offset16(fixture->port, fixture->addr, 0, NULL, 3));
+	zassert_ok(
+		!i2c_read_offset16(fixture->port, fixture->addr, 0, NULL, -1));
+
+	/* Failed intermediate write due to bad address */
+	zassert_ok(!i2c_read_offset16(fixture->port, fixture->addr + 1, 0, NULL,
+				      1));
+}
+
+ZTEST_F(i2c_controller, test_write_offset16__one_byte)
+{
+	/* Write 1 byte to a 16-bit register offset, which will cause us to
+	 * access the extended register space of our i2c device
+	 */
+	int expected = 0xAB;
+	uint16_t reg = 0xFF01;
+	uint8_t actual;
+
+	zassert_ok(i2c_write_offset16(fixture->port, fixture->addr, reg,
+				      expected, 1));
+
+	actual = fixture->emul_data->extended_regs[reg & 0xFF];
+
+	zassert_equal(expected, actual, "got %02x, expected %02x", actual,
+		      expected);
+}
+
+ZTEST_F(i2c_controller, test_write_offset16__two_bytes)
+{
+	/* Write 2 bytes to a 16-bit register offset, which will cause us to
+	 * access the extended register space of our i2c device
+	 */
+	int expected = 0xABCD;
+	uint16_t reg = 0xFF01;
+	uint16_t actual;
+
+	zassert_ok(i2c_write_offset16(fixture->port, fixture->addr, reg,
+				      expected, 2));
+
+	actual = *((uint16_t *)&fixture->emul_data->extended_regs[reg & 0xFF]);
+
+	zassert_equal(expected, actual, "got %04x, expected %04x", actual,
+		      expected);
+}
+
+ZTEST_F(i2c_controller, test_write_offset16__two_bytes_be)
+{
+	/* Write 2 bytes to a 16-bit register offset, which will cause us to
+	 * access the extended register space of our i2c device
+	 */
+	int expected = 0xABCD;
+	uint16_t reg = 0xFF01;
+	uint16_t actual;
+
+	zassert_ok(i2c_write_offset16(fixture->port,
+				      fixture->addr | I2C_FLAG_BIG_ENDIAN, reg,
+				      expected, 2));
+
+	actual = __bswap_16(
+		*((uint16_t *)&fixture->emul_data->extended_regs[reg & 0xFF]));
+
+	zassert_equal(expected, actual, "got %04x, expected %04x", actual,
+		      expected);
+}
+
+ZTEST_F(i2c_controller, test_write_offset16__invalid)
+{
+	/* Check length limits */
+	zassert_ok(!i2c_write_offset16(fixture->port, fixture->addr, 0, 0, 3));
+	zassert_ok(!i2c_write_offset16(fixture->port, fixture->addr, 0, 0, -1));
+}
+
+ZTEST_F(i2c_controller, test_read_offset16_block)
+{
+	/* Read 4 bytes from a 16-bit register offset, which will cause us to
+	 * access the extended register space of our i2c device
+	 */
+	uint32_t data;
+	uint16_t reg = 0xFF01;
+	uint32_t expected = 0xAABBCCDD;
+
+	*((uint32_t *)&fixture->emul_data->extended_regs[reg & 0xFF]) =
+		expected;
+
+	zassert_ok(i2c_read_offset16_block(fixture->port, fixture->addr, reg,
+					   (uint8_t *)&data, sizeof(data)));
+
+	zassert_equal(expected, data, "got %08x, expected %08x", data,
+		      expected);
+}
+
+ZTEST_F(i2c_controller, test_write_offset16_block)
+{
+	/* Write 4 bytes to a 16-bit register offset, which will cause us to
+	 * access the extended register space of our i2c device
+	 */
+	uint32_t expected = 0xAABBCCDD;
+	uint16_t reg = 0xFF01;
+	uint32_t actual;
+
+	zassert_ok(i2c_write_offset16_block(fixture->port, fixture->addr, reg,
+					    (uint8_t *)&expected,
+					    sizeof(expected)));
+
+	actual = *((uint32_t *)&fixture->emul_data->extended_regs[reg & 0xFF]);
+
+	zassert_equal(expected, actual, "got %08x, expected %08x", actual,
+		      expected);
+}
+
+ZTEST_F(i2c_controller, test_pec_disabled)
+{
+	uint16_t addr_flags;
+	uint8_t write_data[] = {
+		0xAA,
+		0xBB,
+		0xCC,
+		0xDD,
+	};
+	int write_data32 = 0x11223344;
+	uint8_t read_data[4];
+	int actual_read_len;
+	uint16_t reg = 0x01;
+
+	/*
+	 * Verify I2C reads and writes through the various APIs fail when
+	 * CONFIG_PLATFORM_EC_SMBUS_PEC=n
+	 */
+	if (IS_ENABLED(CONFIG_PLATFORM_EC_SMBUS_PEC)) {
+		ztest_test_skip();
+		return;
+	}
+
+	addr_flags = fixture->addr | I2C_FLAG_PEC;
+
+	zassert_equal(i2c_read32(fixture->port, addr_flags, reg,
+				 (int *)read_data),
+		      EC_ERROR_UNIMPLEMENTED);
+	zassert_equal(i2c_write32(fixture->port, addr_flags, reg, write_data32),
+		      EC_ERROR_UNIMPLEMENTED);
+	zassert_equal(i2c_read_sized_block(fixture->port, addr_flags, reg,
+					   read_data, sizeof(read_data),
+					   &actual_read_len),
+		      EC_ERROR_UNIMPLEMENTED);
+	zassert_equal(i2c_read_sized_block(fixture->port, addr_flags, reg,
+					   read_data, 0, &actual_read_len),
+		      EC_ERROR_INVAL);
+	zassert_equal(i2c_write_block(fixture->port, addr_flags, reg,
+				      write_data, sizeof(write_data)),
+		      EC_ERROR_UNIMPLEMENTED);
+}
+
+ZTEST_F(i2c_controller, test_i2c_xfer_unlocked__error_paths)
+{
+	uint8_t out_buffer[1];
+	int out_size;
+	uint8_t in_buffer[1];
+	int in_size;
+	int flags;
+
+	/* First confirm i2c_xfer_unlocked() works with a lock. */
+	out_buffer[0] = 0;
+	out_size = 1;
+	in_size = 1;
+	flags = I2C_XFER_STOP;
+
+	i2c_lock(fixture->port, 1);
+	zassert_equal(i2c_port_is_locked(fixture->port), 1,
+		      "Port %d not locked", fixture->port);
+	zassert_ok(i2c_xfer_unlocked(fixture->port, fixture->addr, out_buffer,
+				     out_size, in_buffer, in_size, flags));
+	i2c_lock(fixture->port, 0);
+	zassert_equal(i2c_port_is_locked(fixture->port), 0, "Port %d is locked",
+		      fixture->port);
+
+	/* Try the transfer without a lock. */
+	zassert_equal(i2c_xfer_unlocked(fixture->port, fixture->addr,
+					out_buffer, out_size, in_buffer,
+					in_size, flags),
+		      EC_ERROR_INVAL);
+
+	/* Set an invalid flag on the transfer, expected to still pass */
+	i2c_lock(fixture->port, 1);
+	zassert_equal(i2c_port_is_locked(fixture->port), 1,
+		      "Port %d not locked", fixture->port);
+	zassert_ok(i2c_xfer_unlocked(
+		fixture->port, fixture->addr | I2C_FLAG_ADDR_IS_SPI, out_buffer,
+		out_size, in_buffer, in_size, flags));
+	i2c_lock(fixture->port, 0);
+	zassert_equal(i2c_port_is_locked(fixture->port), 0, "Port %d is locked",
+		      fixture->port);
+}
+
+static struct i2c_controller_fixture i2c_controller_fixture;
+
+static void *setup(void)
+{
+	const struct emul *emul = EMUL_DT_GET(DT_NODELABEL(basic_i2c_device));
+	struct basic_i2c_device_data *emul_data =
+		(struct basic_i2c_device_data *)emul->data;
+
+	i2c_controller_fixture.port =
+		I2C_PORT_BY_DEV(DT_NODELABEL(basic_i2c_device));
+	i2c_controller_fixture.addr = emul_data->common.cfg->addr;
+	i2c_controller_fixture.emul = emul;
+	i2c_controller_fixture.emul_data = emul_data;
+
+	return &i2c_controller_fixture;
+}
+
+static void reset(void *data)
+{
+	struct i2c_controller_fixture *f =
+		(struct i2c_controller_fixture *)data;
+
+	basic_i2c_device_reset(f->emul);
+
+	i2c_common_emul_set_read_fail_reg(&f->emul_data->common,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(&f->emul_data->common,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+}
+
+ZTEST_SUITE(i2c_controller, drivers_predicate_post_main, setup, reset, reset,
+	    NULL);
diff --git a/zephyr/test/drivers/icm42607/CMakeLists.txt b/zephyr/test/drivers/icm42607/CMakeLists.txt
new file mode 100644
index 0000000000..6b4b8a083b
--- /dev/null
+++ b/zephyr/test/drivers/icm42607/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Add source files
+target_sources(app PRIVATE src/icm42607.c)
diff --git a/zephyr/test/drivers/icm42607/prj.conf b/zephyr/test/drivers/icm42607/prj.conf
new file mode 100644
index 0000000000..16c1ae7c03
--- /dev/null
+++ b/zephyr/test/drivers/icm42607/prj.conf
@@ -0,0 +1,6 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_PLATFORM_EC_ACCELGYRO_ICM42607=y
+CONFIG_PLATFORM_EC_ACCELGYRO_ICM_COMM_I2C=y
diff --git a/zephyr/test/drivers/icm42607/sensor.dts b/zephyr/test/drivers/icm42607/sensor.dts
new file mode 100644
index 0000000000..8734ce001a
--- /dev/null
+++ b/zephyr/test/drivers/icm42607/sensor.dts
@@ -0,0 +1,74 @@
+/ {
+	aliases {
+		icm42607-int = &ms_icm42607_accel;
+	};
+
+	motionsense-mutex {
+		mutex_icm42607: icm42607-mutex {
+		};
+	};
+
+	motionsense-sensor-data {
+		icm42607_data: icm42607-drv-data {
+			compatible = "cros-ec,drvdata-icm42607";
+			status = "okay";
+		};
+	};
+
+	motionsense-sensor {
+		ms_icm42607_accel: ms-icm42607-accel {
+			compatible = "cros-ec,icm42607-accel";
+			status = "okay";
+
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&mutex_icm42607>;
+			port = <&named_i2c1>;
+			drv-data = <&icm42607_data>;
+			i2c-spi-addr-flags = "ICM42607_ADDR1_FLAGS";
+			active-mask = "SENSOR_ACTIVE_S0_S3_S5";
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <10000>;
+				};
+				ec-s3 {
+					odr = <10000>;
+				};
+				ec-s5 {
+					odr = <10000>;
+				};
+			};
+		};
+
+		ms_icm42607_gyro: ms-icm42607-gryo {
+			compatible = "cros-ec,icm42607-gyro";
+			status = "okay";
+
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&mutex_icm42607>;
+			port = <&named_i2c1>;
+			drv-data = <&icm42607_data>;
+			i2c-spi-addr-flags = "ICM42607_ADDR1_FLAGS";
+			active-mask = "SENSOR_ACTIVE_S0_S3_S5";
+		};
+	};
+};
+
+&i2c1 {
+		icm42607_emul: icm42607@69 {
+			compatible = "zephyr,icm42607-emul";
+			status = "okay";
+			reg = <0x69>;
+		};
+};
+
+/* motionsense framework supports at most 8 sensors, remove two so we can add
+ * our test target.
+ */
+&ms_bmi160_accel {
+	status = "disabled";
+};
+&ms_bmi160_gyro {
+	status = "disabled";
+};
diff --git a/zephyr/test/drivers/icm42607/src/icm42607.c b/zephyr/test/drivers/icm42607/src/icm42607.c
new file mode 100644
index 0000000000..20d2736063
--- /dev/null
+++ b/zephyr/test/drivers/icm42607/src/icm42607.c
@@ -0,0 +1,466 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "accelgyro.h"
+#include "driver/accelgyro_icm42607.h"
+#include "driver/accelgyro_icm_common.h"
+#include "emul/emul_icm42607.h"
+#include "motion_sense.h"
+#include "motion_sense_fifo.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+#define ICM42607_NODE DT_NODELABEL(icm42607_emul)
+#define ACC_SENSOR_ID SENSOR_ID(DT_NODELABEL(ms_icm42607_accel))
+#define GYR_SENSOR_ID SENSOR_ID(DT_NODELABEL(ms_icm42607_gyro))
+
+static const struct emul *emul = EMUL_DT_GET(ICM42607_NODE);
+static struct motion_sensor_t *acc = &motion_sensors[ACC_SENSOR_ID];
+static struct motion_sensor_t *gyr = &motion_sensors[GYR_SENSOR_ID];
+
+static void icm42607_set_temp(uint16_t val)
+{
+	icm42607_emul_write_reg(emul, ICM42607_REG_TEMP_DATA, val >> 8);
+	icm42607_emul_write_reg(emul, ICM42607_REG_TEMP_DATA + 1, val & 0xFF);
+}
+
+static bool check_sensor_enabled(enum motionsensor_type type)
+{
+	int reg = icm42607_emul_peek_reg(emul, ICM42607_REG_PWR_MGMT0);
+
+	if (type == MOTIONSENSE_TYPE_ACCEL) {
+		int mode = reg & 3;
+
+		return mode == 2;
+	} else if (type == MOTIONSENSE_TYPE_GYRO) {
+		int mode = (reg >> 2) & 3;
+
+		return mode == 3;
+	}
+
+	return false;
+}
+
+static void icm42607_push_packet(const int16_t *acc, const int16_t *gyr)
+{
+	uint8_t buf[16];
+	int packet_size = 0;
+
+	if (acc && gyr) {
+		buf[0] = BIT(6) | BIT(5); /* acc + gyr */
+		memcpy(buf + 1, acc, 6);
+		memcpy(buf + 7, gyr, 6);
+		packet_size = 16;
+	} else if (acc) {
+		buf[0] = BIT(6); /* acc */
+		memcpy(buf + 1, acc, 6);
+		packet_size = 8;
+	} else if (gyr) {
+		buf[0] = BIT(5); /* gyr */
+		memcpy(buf + 1, gyr, 6);
+		packet_size = 8;
+	}
+
+	icm42607_emul_write_reg(emul, ICM42607_REG_INT_STATUS, BIT(2));
+	icm42607_emul_push_fifo(emul, buf, packet_size);
+}
+
+static int motion_sense_fifo_pop(int *sensor_num, int16_t *data)
+{
+	struct ec_response_motion_sensor_data resp = {};
+	uint16_t resp_size;
+
+	while (motion_sense_fifo_read(sizeof(resp), 1, &resp, &resp_size)) {
+		if (resp.flags & MOTIONSENSE_SENSOR_FLAG_TIMESTAMP) {
+			continue;
+		}
+
+		*sensor_num = resp.sensor_num;
+		memcpy(data, resp.data, sizeof(resp.data));
+
+		return 0;
+	}
+
+	return -1;
+}
+
+static void test_fifo(const int16_t *acc_expected, const int16_t *gyr_expected)
+{
+	int sensor_num = -1;
+	int16_t data[3] = {};
+
+	motion_sense_fifo_reset();
+	acc->oversampling_ratio = 1;
+	gyr->oversampling_ratio = 1;
+
+	icm42607_push_packet(acc_expected, gyr_expected);
+	icm42607_interrupt(0);
+	k_sleep(K_SECONDS(1));
+
+	if (acc_expected) {
+		zassert_equal(motion_sense_fifo_pop(&sensor_num, data), 0);
+		zassert_equal(sensor_num, ACC_SENSOR_ID);
+		zassert_equal(acc_expected[0], data[0]);
+		zassert_equal(acc_expected[1], data[1]);
+		zassert_equal(acc_expected[2], data[2]);
+	}
+
+	if (gyr_expected) {
+		zassert_equal(motion_sense_fifo_pop(&sensor_num, data), 0);
+		zassert_equal(sensor_num, GYR_SENSOR_ID);
+		zassert_equal(gyr_expected[0], data[0]);
+		zassert_equal(gyr_expected[1], data[1]);
+		zassert_equal(gyr_expected[2], data[2]);
+	}
+}
+
+/* verify that icm42607 driver returns error when too many data in fifo */
+ZTEST_USER(icm42607, test_fifo_full)
+{
+	const uint8_t junk[512] = {};
+	int sensor_num = -1;
+	int16_t data[3] = {};
+
+	icm42607_push_packet((int16_t[]){ -32768, -32768, -32768 }, NULL);
+	icm42607_emul_push_fifo(emul, junk, sizeof(junk));
+	icm42607_interrupt(0);
+	k_sleep(K_SECONDS(1));
+
+	zassert_not_equal(motion_sense_fifo_pop(&sensor_num, data), 0);
+}
+
+ZTEST_USER(icm42607, test_invalid_packet)
+{
+	const uint8_t junk[16] = {
+		0x80,
+	}; /* bad packet header */
+	int sensor_num = -1;
+	int16_t data[3] = {};
+
+	icm42607_emul_push_fifo(emul, junk, sizeof(junk));
+	icm42607_interrupt(0);
+	k_sleep(K_SECONDS(1));
+
+	zassert_not_equal(motion_sense_fifo_pop(&sensor_num, data), 0);
+}
+
+/* verify that icm42607 driver doesn't send bad data to motionsense fifo */
+ZTEST_USER(icm42607, test_invalid_sensor_data)
+{
+	int sensor_num = -1;
+	int16_t data[3] = {};
+
+	icm42607_push_packet((int16_t[]){ -32768, -32768, -32768 }, NULL);
+	icm42607_interrupt(0);
+	k_sleep(K_SECONDS(1));
+
+	zassert_not_equal(motion_sense_fifo_pop(&sensor_num, data), 0);
+}
+
+ZTEST_USER(icm42607, test_fifo_read)
+{
+	/* 2 sensor packet */
+	test_fifo((int16_t[]){ 1111, 2222, 3333 },
+		  (int16_t[]){ 4444, 5555, 6666 });
+
+	/* acc only */
+	test_fifo((int16_t[]){ 1111, 2222, 3333 }, NULL);
+
+	/* gyr only */
+	test_fifo(NULL, (int16_t[]){ 4444, 5555, 6666 });
+}
+
+ZTEST_USER(icm42607, test_resolution)
+{
+	zassert_equal(acc->drv->get_resolution(acc), 16);
+}
+
+/* verify that set_data_rate enables or disables the sensor */
+ZTEST_USER(icm42607, test_sensor_enable)
+{
+	zassert_false(check_sensor_enabled(MOTIONSENSE_TYPE_ACCEL));
+	zassert_false(check_sensor_enabled(MOTIONSENSE_TYPE_GYRO));
+
+	zassert_ok(acc->drv->set_data_rate(acc, 12500, 1));
+	zassert_true(check_sensor_enabled(MOTIONSENSE_TYPE_ACCEL));
+	zassert_false(check_sensor_enabled(MOTIONSENSE_TYPE_GYRO));
+
+	zassert_ok(acc->drv->set_data_rate(gyr, 12500, 1));
+	zassert_true(check_sensor_enabled(MOTIONSENSE_TYPE_ACCEL));
+	zassert_true(check_sensor_enabled(MOTIONSENSE_TYPE_GYRO));
+
+	zassert_ok(acc->drv->set_data_rate(gyr, 0, 1));
+	zassert_true(check_sensor_enabled(MOTIONSENSE_TYPE_ACCEL));
+	zassert_false(check_sensor_enabled(MOTIONSENSE_TYPE_GYRO));
+
+	zassert_ok(acc->drv->set_data_rate(acc, 0, 1));
+	zassert_false(check_sensor_enabled(MOTIONSENSE_TYPE_ACCEL));
+	zassert_false(check_sensor_enabled(MOTIONSENSE_TYPE_GYRO));
+}
+
+ZTEST_USER(icm42607, test_data_rate)
+{
+	zassert_ok(acc->drv->set_data_rate(acc, 12500, 1));
+	zassert_equal(acc->drv->get_data_rate(acc), 12500);
+	zassert_equal(icm42607_emul_peek_reg(emul, ICM42607_REG_ACCEL_CONFIG0) &
+			      0xF,
+		      0xC);
+
+	/* 24Hz should round up to 25Hz */
+	zassert_ok(gyr->drv->set_data_rate(gyr, 24000, 1));
+	zassert_equal(gyr->drv->get_data_rate(gyr), 25000);
+	zassert_equal(icm42607_emul_peek_reg(emul, ICM42607_REG_GYRO_CONFIG0) &
+			      0xF,
+		      0xB);
+
+	/* return error if data rate is out of supported range */
+	zassert_not_equal(gyr->drv->set_data_rate(gyr, 6250, 0), 0);
+	zassert_not_equal(acc->drv->set_data_rate(acc, 1600000, 0), 0);
+}
+
+ZTEST_USER(icm42607, test_offset_out_of_range)
+{
+	int16_t acc_offset[3];
+	int16_t acc_offset_input[3] = { 10000, -10000, 0 };
+	int16_t acc_temp;
+
+	zassert_ok(acc->drv->init(acc));
+
+	zassert_ok(acc->drv->set_offset(acc, acc_offset_input, 40));
+	zassert_ok(acc->drv->get_offset(acc, acc_offset, &acc_temp));
+
+	/* icm42607 internally stores offset in 12bit signed integer,
+	 * input is clamped into range [2047, -2048], and then scaled to
+	 * ec unit, so the result is [1023.5, -1024] => [1024, -1024]
+	 */
+	zassert_equal(acc_offset[0], 1024);
+	zassert_equal(acc_offset[1], -1024, "got %d", acc_offset[1]);
+	zassert_equal(acc_offset[2], 0);
+	zassert_equal(acc_temp, EC_MOTION_SENSE_INVALID_CALIB_TEMP);
+}
+
+ZTEST_USER(icm42607, test_offset)
+{
+	int16_t acc_offset[3], gyr_offset[3];
+	/* use multiplies of 32 to avoid rounding error */
+	int16_t acc_offset_expected[3] = { 32, 32 * 2, 32 * 3 };
+	int16_t gyr_offset_expected[3] = { 32 * 4, 32 * 5, 32 * 6 };
+	int16_t acc_temp, gyr_temp;
+
+	zassert_ok(acc->drv->init(acc));
+	zassert_ok(gyr->drv->init(gyr));
+
+	zassert_ok(acc->drv->set_offset(acc, acc_offset_expected, 40));
+	zassert_ok(gyr->drv->set_offset(gyr, gyr_offset_expected, 80));
+	zassert_ok(acc->drv->get_offset(acc, acc_offset, &acc_temp));
+	zassert_ok(gyr->drv->get_offset(gyr, gyr_offset, &gyr_temp));
+
+	zassert_equal(acc_offset[0], acc_offset_expected[0]);
+	zassert_equal(acc_offset[1], acc_offset_expected[1]);
+	zassert_equal(acc_offset[2], acc_offset_expected[2]);
+	zassert_equal(acc_temp, EC_MOTION_SENSE_INVALID_CALIB_TEMP);
+	zassert_equal(gyr_offset[0], gyr_offset_expected[0]);
+	zassert_equal(gyr_offset[1], gyr_offset_expected[1]);
+	zassert_equal(gyr_offset[2], gyr_offset_expected[2]);
+	zassert_equal(gyr_temp, EC_MOTION_SENSE_INVALID_CALIB_TEMP);
+}
+
+ZTEST_USER(icm42607, test_scale)
+{
+	uint16_t acc_scale[3], gyr_scale[3];
+	int16_t acc_temp, gyr_temp;
+
+	zassert_ok(acc->drv->init(acc));
+	zassert_ok(gyr->drv->init(gyr));
+
+	zassert_ok(acc->drv->set_scale(acc, (uint16_t[3]){ 1, 2, 3 }, 4));
+	zassert_ok(gyr->drv->set_scale(gyr, (uint16_t[3]){ 5, 6, 7 }, 8));
+	zassert_ok(gyr->drv->get_scale(acc, acc_scale, &acc_temp));
+	zassert_ok(gyr->drv->get_scale(gyr, gyr_scale, &gyr_temp));
+
+	zassert_equal(acc_scale[0], 1);
+	zassert_equal(acc_scale[1], 2);
+	zassert_equal(acc_scale[2], 3);
+	zassert_equal(acc_temp, EC_MOTION_SENSE_INVALID_CALIB_TEMP);
+	zassert_equal(gyr_scale[0], 5);
+	zassert_equal(gyr_scale[1], 6);
+	zassert_equal(gyr_scale[2], 7);
+	zassert_equal(gyr_temp, EC_MOTION_SENSE_INVALID_CALIB_TEMP);
+}
+
+ZTEST_USER(icm42607, test_invalid_read)
+{
+	intv3_t v;
+
+	zassert_ok(acc->drv->init(acc));
+	zassert_ok(gyr->drv->init(gyr));
+
+	icm42607_emul_write_reg(emul, ICM42607_REG_ACCEL_DATA_XYZ, 0x00);
+	icm42607_emul_write_reg(emul, ICM42607_REG_ACCEL_DATA_XYZ + 1, 0x80);
+	icm42607_emul_write_reg(emul, ICM42607_REG_ACCEL_DATA_XYZ + 2, 0x00);
+	icm42607_emul_write_reg(emul, ICM42607_REG_ACCEL_DATA_XYZ + 3, 0x80);
+	icm42607_emul_write_reg(emul, ICM42607_REG_ACCEL_DATA_XYZ + 4, 0x00);
+	icm42607_emul_write_reg(emul, ICM42607_REG_ACCEL_DATA_XYZ + 5, 0x80);
+
+	/* return cached value (raw_xyz) on invalid data */
+	zassert_ok(acc->drv->read(acc, v));
+	zassert_equal(v[0], 0);
+	zassert_equal(v[1], 0);
+	zassert_equal(v[2], 0);
+}
+
+/* verify that read() works correctly, and scale is applied */
+ZTEST_USER(icm42607, test_read)
+{
+	intv3_t v;
+	const uint16_t scale[3] = { 16384, 16384, 16384 }; /* 0.5x scale */
+
+	zassert_ok(acc->drv->init(acc));
+	zassert_ok(gyr->drv->init(gyr));
+
+	/* verify that sensor data format is configured to little endian */
+	int intf_config0 =
+		icm42607_emul_peek_reg(emul, ICM42607_REG_INTF_CONFIG0);
+	zassert_equal(intf_config0 & ICM42607_SENSOR_DATA_ENDIAN, 0);
+	zassert_ok(acc->drv->set_scale(acc, scale, 0));
+
+	/* test accel read, 16bit LE */
+	icm42607_emul_write_reg(emul, ICM42607_REG_ACCEL_DATA_XYZ, 0x01);
+	icm42607_emul_write_reg(emul, ICM42607_REG_ACCEL_DATA_XYZ + 1, 0x02);
+	icm42607_emul_write_reg(emul, ICM42607_REG_ACCEL_DATA_XYZ + 2, 0x03);
+	icm42607_emul_write_reg(emul, ICM42607_REG_ACCEL_DATA_XYZ + 3, 0x04);
+	icm42607_emul_write_reg(emul, ICM42607_REG_ACCEL_DATA_XYZ + 4, 0x05);
+	icm42607_emul_write_reg(emul, ICM42607_REG_ACCEL_DATA_XYZ + 5, 0x06);
+
+	zassert_ok(acc->drv->read(acc, v));
+	zassert_equal(v[0], 0x0201 / 2);
+	zassert_equal(v[1], 0x0403 / 2);
+	zassert_equal(v[2], 0x0605 / 2);
+
+	/* test gyro read, 16bit LE */
+	icm42607_emul_write_reg(emul, ICM42607_REG_GYRO_DATA_XYZ, 0x0A);
+	icm42607_emul_write_reg(emul, ICM42607_REG_GYRO_DATA_XYZ + 1, 0x0B);
+	icm42607_emul_write_reg(emul, ICM42607_REG_GYRO_DATA_XYZ + 2, 0x0C);
+	icm42607_emul_write_reg(emul, ICM42607_REG_GYRO_DATA_XYZ + 3, 0x0D);
+	icm42607_emul_write_reg(emul, ICM42607_REG_GYRO_DATA_XYZ + 4, 0x0E);
+	icm42607_emul_write_reg(emul, ICM42607_REG_GYRO_DATA_XYZ + 5, 0x0F);
+
+	zassert_ok(gyr->drv->read(gyr, v));
+	zassert_equal(v[0], 0x0B0A);
+	zassert_equal(v[1], 0x0D0C);
+	zassert_equal(v[2], 0x0F0E);
+}
+
+/* read() immediately after sensor enabled should fail */
+ZTEST_USER(icm42607, test_read_not_stabilized)
+{
+	intv3_t v;
+
+	zassert_ok(acc->drv->set_data_rate(acc, 0, 1));
+	zassert_ok(acc->drv->set_data_rate(acc, 10000, 1));
+	zassert_not_equal(acc->drv->read(acc, v), 0);
+
+	sleep(1);
+	zassert_equal(acc->drv->read(acc, v), 0);
+}
+
+ZTEST_USER(icm42607, test_set_range)
+{
+	int reg_val;
+
+	/* set 5G, round down to 4G, expect reg val = 2 */
+	zassert_ok(acc->drv->set_range(acc, 5, 0));
+	reg_val = (icm42607_emul_peek_reg(emul, ICM42607_REG_ACCEL_CONFIG0) >>
+		   5) &
+		  3;
+	zassert_equal(reg_val, 2);
+
+	/* set 5G, round up to 8G, expect reg val = 1 */
+	zassert_ok(acc->drv->set_range(acc, 5, 1));
+	reg_val = (icm42607_emul_peek_reg(emul, ICM42607_REG_ACCEL_CONFIG0) >>
+		   5) &
+		  3;
+	zassert_equal(reg_val, 1);
+
+	/* set 1500dps, round down to 1000dps, expect reg val = 1 */
+	zassert_ok(gyr->drv->set_range(gyr, 1500, 0));
+	reg_val =
+		(icm42607_emul_peek_reg(emul, ICM42607_REG_GYRO_CONFIG0) >> 5) &
+		3;
+	zassert_equal(reg_val, 1);
+
+	/* set 1500dps, round down to 2000dps, expect reg val = 0 */
+	zassert_ok(gyr->drv->set_range(gyr, 1500, 1));
+	reg_val =
+		(icm42607_emul_peek_reg(emul, ICM42607_REG_GYRO_CONFIG0) >> 5) &
+		3;
+	zassert_equal(reg_val, 0);
+}
+
+/* Verify the temperature matches following formula:
+ * Temperature in C = (REG_DATA / 128) + 25
+ */
+ZTEST_USER(icm42607, test_read_temp)
+{
+	int temp;
+
+	/* expect 0C = 273.15K */
+	icm42607_set_temp(-25 * 128);
+	zassert_ok(acc->drv->read_temp(acc, &temp));
+	zassert_equal(temp, 273);
+
+	/* expect 100C = 373.15K */
+	icm42607_set_temp(75 * 128);
+	zassert_ok(acc->drv->read_temp(acc, &temp));
+	zassert_equal(temp, 373);
+
+	/* expect 25C = 298K */
+	icm42607_set_temp(0);
+	zassert_ok(acc->drv->read_temp(acc, &temp));
+	zassert_equal(temp, 298);
+
+	/* reset value */
+	icm42607_set_temp(-32768);
+	zassert_not_equal(acc->drv->read_temp(acc, &temp), 0);
+}
+
+ZTEST_USER(icm42607, test_init)
+{
+	struct i2c_common_emul_data *common_data =
+		emul_icm42607_get_i2c_common_data(emul);
+
+	icm42607_emul_write_reg(emul, ICM42607_REG_WHO_AM_I,
+				ICM42607_CHIP_ICM42607P);
+	zassert_ok(acc->drv->init(acc));
+
+	icm42607_emul_write_reg(emul, ICM42607_REG_WHO_AM_I, 0x87);
+	zassert_not_equal(acc->drv->init(acc), 0);
+
+	i2c_common_emul_set_read_fail_reg(common_data, ICM42607_REG_WHO_AM_I);
+	zassert_not_equal(acc->drv->init(acc), 0);
+}
+
+static void icm42607_before(void *fixture)
+{
+	struct i2c_common_emul_data *common_data =
+		emul_icm42607_get_i2c_common_data(emul);
+
+	ARG_UNUSED(fixture);
+
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	icm42607_emul_reset(emul);
+	icm_reset_stabilize_ts(acc);
+	icm_reset_stabilize_ts(gyr);
+	memset(acc->raw_xyz, 0, sizeof(intv3_t));
+	memset(gyr->raw_xyz, 0, sizeof(intv3_t));
+	motion_sense_fifo_reset();
+	acc->oversampling_ratio = 1;
+	gyr->oversampling_ratio = 1;
+}
+
+ZTEST_SUITE(icm42607, drivers_predicate_post_main, NULL, icm42607_before, NULL,
+	    NULL);
diff --git a/zephyr/test/drivers/isl923x/CMakeLists.txt b/zephyr/test/drivers/isl923x/CMakeLists.txt
new file mode 100644
index 0000000000..734742c6b6
--- /dev/null
+++ b/zephyr/test/drivers/isl923x/CMakeLists.txt
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Add source files
+target_sources_ifdef(CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_ADC_AMON_BMON
+			app PRIVATE src/console_cmd_amon_bmon.c)
+target_sources_ifdef(CONFIG_PLATFORM_EC_CHARGE_RAMP_HW
+			app PRIVATE src/charge_ramp_hw.c)
diff --git a/zephyr/test/drivers/isl923x/src/charge_ramp_hw.c b/zephyr/test/drivers/isl923x/src/charge_ramp_hw.c
new file mode 100644
index 0000000000..a4e326bcec
--- /dev/null
+++ b/zephyr/test/drivers/isl923x/src/charge_ramp_hw.c
@@ -0,0 +1,51 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/charger/isl923x.h"
+#include "driver/charger/isl923x_public.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_isl923x.h"
+#include "test/drivers/charger_utils.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/ztest.h>
+
+#define CHARGER_NUM get_charger_num(&isl923x_drv)
+#define ISL923X_EMUL EMUL_DT_GET(DT_NODELABEL(isl923x_emul))
+
+ZTEST_SUITE(charge_ramp_hw, drivers_predicate_post_main, NULL, NULL, NULL,
+	    NULL);
+
+ZTEST(charge_ramp_hw, test_charge_ramp_hw_ramp)
+{
+	zassert_ok(isl923x_drv.set_hw_ramp(CHARGER_NUM, 1));
+
+	zassert_ok(isl923x_drv.ramp_is_stable(CHARGER_NUM));
+	zassert_true(isl923x_drv.ramp_is_detected(CHARGER_NUM));
+
+	zassert_ok(isl923x_drv.set_input_current_limit(CHARGER_NUM, 512));
+	zassert_equal(512, isl923x_drv.ramp_get_current_limit(CHARGER_NUM),
+		      NULL);
+}
+
+ZTEST(charge_ramp_hw, test_charge_ramp_hw_ramp_read_fail_reg0)
+{
+	struct i2c_common_emul_data *common_data =
+		emul_isl923x_get_i2c_common_data(ISL923X_EMUL);
+
+	i2c_common_emul_set_read_fail_reg(common_data, ISL923X_REG_CONTROL0);
+	zassert_equal(EC_ERROR_INVAL, isl923x_drv.set_hw_ramp(CHARGER_NUM, 1),
+		      NULL);
+}
+
+ZTEST(charge_ramp_hw, test_charge_ramp_hw_ramp_read_fail_acl1)
+{
+	struct i2c_common_emul_data *common_data =
+		emul_isl923x_get_i2c_common_data(ISL923X_EMUL);
+
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  ISL923X_REG_ADAPTER_CURRENT_LIMIT1);
+	zassert_equal(0, isl923x_drv.ramp_get_current_limit(CHARGER_NUM));
+}
diff --git a/zephyr/test/drivers/isl923x/src/console_cmd_amon_bmon.c b/zephyr/test/drivers/isl923x/src/console_cmd_amon_bmon.c
new file mode 100644
index 0000000000..8eef7ea748
--- /dev/null
+++ b/zephyr/test/drivers/isl923x/src/console_cmd_amon_bmon.c
@@ -0,0 +1,122 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc.h"
+#include "console.h"
+#include "driver/charger/isl923x.h"
+#include "driver/charger/isl923x_public.h"
+#include "ec_commands.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_isl923x.h"
+#include "test/drivers/charger_utils.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/drivers/adc.h>
+#include <zephyr/drivers/adc/adc_emul.h>
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+#define ADC_DEVICE_NODE DT_NODELABEL(adc0)
+#define CHARGER_NUM get_charger_num(&isl923x_drv)
+#define ISL923X_EMUL EMUL_DT_GET(DT_NODELABEL(isl923x_emul))
+
+ZTEST_SUITE(console_cmd_amon_bmon, drivers_predicate_post_main, NULL, NULL,
+	    NULL, NULL);
+
+ZTEST(console_cmd_amon_bmon, test_isl923x_amonbmon_shell_cmd)
+{
+	/* Validate combinations of well formed shell commands */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "amonbmon a 0"));
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "amonbmon ac 0"));
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "amonbmon ad 0"));
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "amonbmon b 0"));
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "amonbmon bc 0"));
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "amonbmon bd 0"));
+
+	/* Check error returned for malformed shell command */
+	zassert_equal(EC_ERROR_PARAM2,
+		      shell_execute_cmd(get_ec_shell(), "amonbmon a x"), NULL);
+}
+
+ZTEST(console_cmd_amon_bmon, test_isl923x_amonbmon_get_input_current)
+{
+	const struct device *adc_dev = DEVICE_DT_GET(ADC_DEVICE_NODE);
+	const uint16_t input_mv = 1000;
+	int current_milli_amps, ret;
+
+	ret = adc_emul_const_value_set(adc_dev, ADC_AMON_BMON, input_mv);
+	zassert_ok(ret, "adc_emul_const_value_set() failed with code %d", ret);
+
+	zassert_ok(isl923x_drv.get_input_current(CHARGER_NUM,
+						 &current_milli_amps),
+		   NULL);
+	zassert_within(current_milli_amps, 5000, 10,
+		       "Expected input current %dmA but got %dmA", 5000,
+		       current_milli_amps);
+}
+
+ZTEST(console_cmd_amon_bmon,
+      test_isl923x_amonbmon_get_input_current_read_fail_req1)
+{
+	const struct emul *isl923x_emul = ISL923X_EMUL;
+	struct i2c_common_emul_data *common_data =
+		emul_isl923x_get_i2c_common_data(isl923x_emul);
+	int current_milli_amps;
+
+	i2c_common_emul_set_read_fail_reg(common_data, ISL923X_REG_CONTROL1);
+	zassert_equal(EC_ERROR_INVAL,
+		      isl923x_drv.get_input_current(CHARGER_NUM,
+						    &current_milli_amps),
+		      NULL);
+	zassert_equal(EC_ERROR_INVAL,
+		      shell_execute_cmd(get_ec_shell(), "amonbmon a 0"), NULL);
+}
+
+ZTEST(console_cmd_amon_bmon,
+      test_isl923x_amonbmon_get_input_current_read_fail_req3)
+{
+	const struct emul *isl923x_emul = ISL923X_EMUL;
+	struct i2c_common_emul_data *common_data =
+		emul_isl923x_get_i2c_common_data(isl923x_emul);
+	int current_milli_amps;
+
+	i2c_common_emul_set_read_fail_reg(common_data, ISL9238_REG_CONTROL3);
+	zassert_equal(EC_ERROR_INVAL,
+		      isl923x_drv.get_input_current(CHARGER_NUM,
+						    &current_milli_amps),
+		      NULL);
+}
+
+ZTEST(console_cmd_amon_bmon,
+      test_isl923x_amonbmon_get_input_current_write_fail_req1)
+{
+	const struct emul *isl923x_emul = ISL923X_EMUL;
+	struct i2c_common_emul_data *common_data =
+		emul_isl923x_get_i2c_common_data(isl923x_emul);
+	int current_milli_amps;
+
+	i2c_common_emul_set_write_fail_reg(common_data, ISL923X_REG_CONTROL1);
+	zassert_equal(EC_ERROR_INVAL,
+		      isl923x_drv.get_input_current(CHARGER_NUM,
+						    &current_milli_amps),
+		      NULL);
+}
+
+ZTEST(console_cmd_amon_bmon,
+      test_isl923x_amonbmon_get_input_current_write_fail_req3)
+{
+	const struct emul *isl923x_emul = ISL923X_EMUL;
+	struct i2c_common_emul_data *common_data =
+		emul_isl923x_get_i2c_common_data(isl923x_emul);
+	int current_milli_amps;
+
+	i2c_common_emul_set_write_fail_reg(common_data, ISL9238_REG_CONTROL3);
+	zassert_equal(EC_ERROR_INVAL,
+		      isl923x_drv.get_input_current(CHARGER_NUM,
+						    &current_milli_amps),
+		      NULL);
+}
diff --git a/zephyr/test/drivers/isl9241/CMakeLists.txt b/zephyr/test/drivers/isl9241/CMakeLists.txt
new file mode 100644
index 0000000000..387fe2b85b
--- /dev/null
+++ b/zephyr/test/drivers/isl9241/CMakeLists.txt
@@ -0,0 +1,5 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_sources(app PRIVATE src/isl9241.c)
diff --git a/zephyr/test/drivers/isl9241/src/isl9241.c b/zephyr/test/drivers/isl9241/src/isl9241.c
new file mode 100644
index 0000000000..57f7169919
--- /dev/null
+++ b/zephyr/test/drivers/isl9241/src/isl9241.c
@@ -0,0 +1,232 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery_smart.h"
+#include "charger.h"
+#include "driver/charger/isl9241.h"
+#include "driver/charger/isl9241_public.h"
+#include "emul/emul_isl9241.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+#define ISL9241_NODE DT_NODELABEL(isl9241_emul)
+
+struct isl9241_driver_fixture {
+	const struct emul *isl9241_emul;
+};
+
+static void *isl9241_driver_setup(void)
+{
+	static struct isl9241_driver_fixture fix;
+
+	fix.isl9241_emul = EMUL_DT_GET(ISL9241_NODE);
+
+	return &fix;
+}
+
+ZTEST_SUITE(isl9241_driver, drivers_predicate_post_main, isl9241_driver_setup,
+	    NULL, NULL, NULL);
+
+ZTEST(isl9241_driver, test_input_current_limit)
+{
+	int input_current = 3000;
+	int temp;
+
+	zassert_ok(
+		charger_set_input_current_limit(CHARGER_SOLO, input_current));
+	zassert_ok(charger_get_input_current_limit(CHARGER_SOLO, &temp));
+	zassert_equal(input_current, temp);
+}
+
+ZTEST(isl9241_driver, test_device_id)
+{
+	int id;
+
+	zassert_ok(charger_device_id(&id));
+	zassert_equal(id, 0x000E);
+}
+
+ZTEST(isl9241_driver, test_manuf_id)
+{
+	int id;
+
+	zassert_ok(charger_manufacturer_id(&id));
+	zassert_equal(id, 0x0049);
+}
+
+/*
+ * Unforuntely, there is no "get frequency" API, so we'll directly compare
+ * expected register contents for this test
+ */
+struct frequency_test {
+	int khz;
+	uint16_t reg;
+};
+
+struct frequency_test frequency_table[] = {
+	{ .khz = 1420, .reg = ISL9241_CONTROL1_SWITCHING_FREQ_1420KHZ },
+	{ .khz = 1180, .reg = ISL9241_CONTROL1_SWITCHING_FREQ_1180KHZ },
+	{ .khz = 1020, .reg = ISL9241_CONTROL1_SWITCHING_FREQ_1020KHZ },
+	{ .khz = 890, .reg = ISL9241_CONTROL1_SWITCHING_FREQ_890KHZ },
+	{ .khz = 808, .reg = ISL9241_CONTROL1_SWITCHING_FREQ_808KHZ },
+	{ .khz = 724, .reg = ISL9241_CONTROL1_SWITCHING_FREQ_724KHZ },
+	{ .khz = 656, .reg = ISL9241_CONTROL1_SWITCHING_FREQ_656KHZ },
+	{ .khz = 600, .reg = ISL9241_CONTROL1_SWITCHING_FREQ_600KHZ },
+};
+
+ZTEST_F(isl9241_driver, test_frequency)
+{
+	for (int i = 0; i < ARRAY_SIZE(frequency_table); i++) {
+		uint16_t register_peek;
+		struct frequency_test *t = &frequency_table[i];
+
+		zassert_ok(charger_set_frequency(t->khz));
+		register_peek = isl9241_emul_peek(fixture->isl9241_emul,
+						  ISL9241_REG_CONTROL1);
+		zassert_equal(
+			(register_peek &
+			 ISL9241_CONTROL1_SWITCHING_FREQ_MASK) >>
+				7,
+			t->reg,
+			"Failed to see correct register for %d kHz (0x%04x)\n",
+			t->khz, register_peek);
+	}
+}
+
+ZTEST(isl9241_driver, test_options)
+{
+	/* We're free to set whatever we want in CONTROL0 15:0 */
+	int option = ISL9241_CONTROL0_EN_CHARGE_PUMPS |
+		     ISL9241_CONTROL0_EN_BYPASS_GATE;
+	int temp;
+
+	zassert_ok(charger_set_option(option));
+	zassert_ok(charger_get_option(&temp));
+	zassert_equal(option, temp);
+}
+
+ZTEST(isl9241_driver, test_inhibit_charge)
+{
+	int status;
+
+	zassert_ok(charger_set_mode(CHARGE_FLAG_INHIBIT_CHARGE));
+	zassert_ok(charger_get_status(&status));
+	zassert_equal((status & CHARGER_CHARGE_INHIBITED),
+		      CHARGER_CHARGE_INHIBITED);
+}
+
+ZTEST_F(isl9241_driver, test_por_reset)
+{
+	zassert_ok(charger_set_mode(CHARGE_FLAG_POR_RESET));
+	zassert_equal(isl9241_emul_peek(fixture->isl9241_emul,
+					ISL9241_REG_CONTROL3),
+		      ISL9241_CONTROL3_DIGITAL_RESET);
+}
+
+ZTEST(isl9241_driver, test_current)
+{
+	int current = 4000;
+	int temp;
+
+	zassert_ok(charger_set_current(CHARGER_SOLO, current));
+	zassert_ok(charger_get_current(CHARGER_SOLO, &temp));
+	zassert_equal(temp, current);
+}
+
+ZTEST(isl9241_driver, test_voltage)
+{
+	int voltage = 12000;
+	int temp;
+
+	zassert_ok(charger_set_voltage(CHARGER_SOLO, voltage));
+	zassert_ok(charger_get_voltage(CHARGER_SOLO, &temp));
+	zassert_equal(temp, voltage);
+}
+
+ZTEST_F(isl9241_driver, test_vbus_voltage)
+{
+	int voltage = 5088; /* ADC is in 96 mV steps */
+	int status;
+
+	isl9241_emul_set_vbus(fixture->isl9241_emul, voltage);
+	zassert_ok(charger_get_status(&status));
+	zassert_equal((status & CHARGER_AC_PRESENT), CHARGER_AC_PRESENT);
+
+	zassert_ok(charger_get_vbus_voltage(0, &status));
+	zassert_equal(voltage, status);
+}
+
+ZTEST_F(isl9241_driver, test_vsys_voltage)
+{
+	int voltage = 9984; /* ADC is in 96 mV steps */
+	int temp;
+
+	isl9241_emul_set_vsys(fixture->isl9241_emul, voltage);
+	zassert_ok(charger_get_vsys_voltage(0, &temp));
+	zassert_equal(voltage, temp);
+}
+
+ZTEST(isl9241_driver, test_post_init)
+{
+	/* Note: function is a no-op for this chip */
+	zassert_ok(charger_post_init());
+}
+
+ZTEST_F(isl9241_driver, test_ac_prochot)
+{
+	/* Test bounds settings for allowed currents */
+	/* Note: AC currents are scaled by the default of 20 */
+	int scale = 20 / CONFIG_CHARGER_SENSE_RESISTOR_AC;
+	int cur = (ISL9241_AC_PROCHOT_CURRENT_MAX + 100) * scale;
+
+	printf("cur %d ", cur);
+	zassert_ok(isl9241_set_ac_prochot(CHARGER_SOLO, cur));
+	printf("%d\n", isl9241_emul_peek(fixture->isl9241_emul,
+					 ISL9241_REG_AC_PROCHOT));
+	zassert_equal(isl9241_emul_peek(fixture->isl9241_emul,
+					ISL9241_REG_AC_PROCHOT),
+		      AC_CURRENT_TO_REG(ISL9241_AC_PROCHOT_CURRENT_MAX));
+
+	cur = (ISL9241_AC_PROCHOT_CURRENT_MIN - 100) * scale;
+	printf("cur %d ", cur);
+	zassert_ok(isl9241_set_ac_prochot(CHARGER_SOLO, cur));
+	printf("%d\n", isl9241_emul_peek(fixture->isl9241_emul,
+					 ISL9241_REG_AC_PROCHOT));
+	zassert_equal(isl9241_emul_peek(fixture->isl9241_emul,
+					ISL9241_REG_AC_PROCHOT),
+		      AC_CURRENT_TO_REG(ISL9241_AC_PROCHOT_CURRENT_MIN));
+}
+
+ZTEST_F(isl9241_driver, test_dc_prochot)
+{
+	/* Test bounds settings for allowed currents */
+	/* Note: DC currents are scaled by default of 10 */
+	int scale = 10 / CONFIG_CHARGER_SENSE_RESISTOR;
+	int cur = (ISL9241_DC_PROCHOT_CURRENT_MAX + 100) * scale;
+
+	zassert_ok(isl9241_set_dc_prochot(CHARGER_SOLO, cur));
+	zassert_equal(isl9241_emul_peek(fixture->isl9241_emul,
+					ISL9241_REG_DC_PROCHOT),
+		      ISL9241_DC_PROCHOT_CURRENT_MAX);
+
+	cur = (ISL9241_DC_PROCHOT_CURRENT_MIN - 100) * scale;
+	zassert_ok(isl9241_set_dc_prochot(CHARGER_SOLO, cur));
+	zassert_equal(isl9241_emul_peek(fixture->isl9241_emul,
+					ISL9241_REG_DC_PROCHOT),
+		      ISL9241_DC_PROCHOT_CURRENT_MIN);
+}
+
+ZTEST(isl9241_driver, test_prochot_dump)
+{
+	/*
+	 * Note: this function's purpose is to print register contents to the
+	 * console for debugging
+	 */
+	print_charger_prochot(CHARGER_SOLO);
+}
diff --git a/zephyr/test/drivers/isl9241/usbc.dts b/zephyr/test/drivers/isl9241/usbc.dts
new file mode 100644
index 0000000000..94ddccb7d3
--- /dev/null
+++ b/zephyr/test/drivers/isl9241/usbc.dts
@@ -0,0 +1,27 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/usb_pd_tcpm.h>
+
+/ {
+	usbc {
+		port0@0 {
+			compatible = "named-usbc-port";
+			chg = <&isl9241_emul>;
+		};
+	};
+};
+
+&i2c0 {
+	status="okay";
+
+	/delete-node/ isl923x@9;
+
+	isl9241_emul: isl9241_emul@9 {
+		compatible = "intersil,isl9241";
+		status = "okay";
+		reg = <0x9>;
+	};
+};
diff --git a/zephyr/test/drivers/it8xxx2_hw_sha256/CMakeLists.txt b/zephyr/test/drivers/it8xxx2_hw_sha256/CMakeLists.txt
new file mode 100644
index 0000000000..5a6ec53f39
--- /dev/null
+++ b/zephyr/test/drivers/it8xxx2_hw_sha256/CMakeLists.txt
@@ -0,0 +1,8 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+zephyr_include_directories("${PLATFORM_EC}/zephyr/shim/chip/it8xxx2/include")
+zephyr_library_sources("${PLATFORM_EC}/driver/sha256/sha256_it8xxx2.c")
+# Include the test source and the file under test
+target_sources(app PRIVATE src/main.c)
diff --git a/zephyr/test/drivers/it8xxx2_hw_sha256/src/main.c b/zephyr/test/drivers/it8xxx2_hw_sha256/src/main.c
new file mode 100644
index 0000000000..14d4bcc8ee
--- /dev/null
+++ b/zephyr/test/drivers/it8xxx2_hw_sha256/src/main.c
@@ -0,0 +1,43 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/ztest_assert.h>
+#include <zephyr/ztest_test_new.h>
+
+#include <sha256.h>
+
+static const uint8_t sha256_input[] = { 0xaa, 0xaa, 0x55, 0x55 };
+static const uint32_t sha256_output_no_caculated[8] = {
+	0x67e6096a, 0x85ae67bb, 0x72f36e3c, 0x3af54fa5,
+	0x7f520e51, 0x8c68059b, 0xabd9831f, 0x19cde05b
+};
+
+ZTEST_SUITE(it8xxx2_hw_sha256_driver, NULL, NULL, NULL, NULL, NULL);
+
+ZTEST(it8xxx2_hw_sha256_driver, test_it8xxx2_hw_sha256)
+{
+	static struct sha256_ctx ctx __aligned(256);
+	uint8_t *hash;
+	uint8_t reg_addr, expected_addr;
+
+	SHA256_init(&ctx);
+	/* Verify hardware sha256 registers are configured as we want. */
+	expected_addr = ((uint32_t)&ctx >> 6) & 0xffc;
+	reg_addr = it8xxx2_sha256_get_sha1hbaddr();
+	zassert_equal(reg_addr, expected_addr, "sha1hbaddr: 0x%x vs 0x%x",
+		      reg_addr, expected_addr);
+	expected_addr = ((uint32_t)&ctx.k >> 6) & 0xffc;
+	reg_addr = it8xxx2_sha256_get_sha2hbaddr();
+	zassert_equal(reg_addr, expected_addr, "sha2hbaddr: 0x%x vs 0x%x",
+		      reg_addr, expected_addr);
+	SHA256_update(&ctx, sha256_input, sizeof(sha256_input));
+	hash = SHA256_final(&ctx);
+	/*
+	 * Since hash is not actually calculated, the byte order of h0~h7 is
+	 * verified here.
+	 */
+	zassert_mem_equal(hash, sha256_output_no_caculated,
+			  sizeof(sha256_output_no_caculated), NULL);
+}
diff --git a/zephyr/test/drivers/keyboard_8042/CMakeLists.txt b/zephyr/test/drivers/keyboard_8042/CMakeLists.txt
new file mode 100644
index 0000000000..ed131ec38e
--- /dev/null
+++ b/zephyr/test/drivers/keyboard_8042/CMakeLists.txt
@@ -0,0 +1,8 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_sources(app PRIVATE
+  src/keyboard_8042.c
+)
+
diff --git a/zephyr/test/drivers/keyboard_8042/src/keyboard_8042.c b/zephyr/test/drivers/keyboard_8042/src/keyboard_8042.c
new file mode 100644
index 0000000000..fd6355abf0
--- /dev/null
+++ b/zephyr/test/drivers/keyboard_8042/src/keyboard_8042.c
@@ -0,0 +1,382 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "atkbd_protocol.h"
+#include "console.h"
+#include "i8042_protocol.h"
+#include "keyboard_8042.h"
+#include "test/drivers/test_mocks.h"
+#include "test/drivers/test_state.h"
+
+#include <string.h>
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/fff.h>
+#include <zephyr/shell/shell_dummy.h>
+#include <zephyr/ztest.h>
+
+ZTEST(keyboard_8042, test_console_cmd__typematic__status)
+{
+	const char *outbuffer;
+	size_t buffer_size;
+
+	/* Set a typematic scan code to verify */
+	const uint8_t scan_code[] = { 0x01, 0x02, 0x03 };
+
+	set_typematic_key(scan_code, ARRAY_SIZE(scan_code));
+
+	/* With no args, print current state */
+	shell_backend_dummy_clear_output(get_ec_shell());
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "8042 typematic"));
+	outbuffer =
+		shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+
+	/* Check for some expected lines based off default typematic state */
+	zassert_true(buffer_size > 0);
+	zassert_ok(!strstr(outbuffer, "From host:   0x2b"));
+	zassert_ok(!strstr(outbuffer, "First delay: 500 ms"));
+	zassert_ok(!strstr(outbuffer, "Inter delay:  91 ms"));
+	zassert_ok(
+		!strstr(outbuffer, "Repeat scan code: {0x01, 0x02, 0x03, }"));
+}
+
+ZTEST(keyboard_8042, test_console_cmd__typematic__set_delays)
+{
+	const char *outbuffer;
+	size_t buffer_size;
+
+	/* Set first delay and inter delay */
+	shell_backend_dummy_clear_output(get_ec_shell());
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "8042 typematic 123 456"));
+	outbuffer =
+		shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+
+	/* Check for some expected lines */
+	zassert_true(buffer_size > 0);
+	zassert_ok(!strstr(outbuffer, "First delay: 123 ms"));
+	zassert_ok(!strstr(outbuffer, "Inter delay: 456 ms"));
+}
+
+ZTEST(keyboard_8042, test_console_cmd__codeset__set_codeset1)
+{
+	const char *outbuffer;
+	size_t buffer_size;
+
+	/* Switch to codeset 1 and verify output */
+	shell_backend_dummy_clear_output(get_ec_shell());
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "8042 codeset 1"));
+	outbuffer =
+		shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+
+	zassert_true(buffer_size > 0);
+	zassert_ok(!strstr(outbuffer, "Set: 1"));
+}
+
+ZTEST(keyboard_8042, test_console_cmd__codeset__set_invalid)
+{
+	zassert_equal(EC_ERROR_PARAM1,
+		      shell_execute_cmd(get_ec_shell(), "8042 codeset 999"));
+}
+
+ZTEST(keyboard_8042, test_console_cmd__ram__writeread)
+{
+	const char *outbuffer;
+	size_t buffer_size;
+
+	/* Write a byte and verify the readback in console output */
+	shell_backend_dummy_clear_output(get_ec_shell());
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "8042 ctrlram 0x1f 0xaa"));
+	outbuffer =
+		shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+
+	zassert_true(buffer_size > 0);
+	zassert_ok(!strstr(outbuffer, "31 = 0xaa"));
+}
+
+ZTEST(keyboard_8042, test_console_cmd__ram__invalid)
+{
+	/* Missing args */
+	zassert_equal(EC_ERROR_PARAM_COUNT,
+		      shell_execute_cmd(get_ec_shell(), "8042 ctrlram"));
+
+	/* Address out of bounds */
+	zassert_equal(EC_ERROR_PARAM1,
+		      shell_execute_cmd(get_ec_shell(), "8042 ctrlram 9999"));
+}
+
+ZTEST(keyboard_8042, test_console_cmd__enable__true)
+{
+	const char *outbuffer;
+	size_t buffer_size;
+
+	/* Enable the keyboard and verify in console output */
+	shell_backend_dummy_clear_output(get_ec_shell());
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "8042 kbd y"));
+	outbuffer =
+		shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+
+	zassert_true(buffer_size > 0);
+	zassert_ok(!strstr(outbuffer, "Enabled: 1"));
+}
+
+ZTEST(keyboard_8042, test_console_cmd__enable__invalid)
+{
+	/* Non-bool arg */
+	zassert_equal(EC_ERROR_PARAM1,
+		      shell_execute_cmd(get_ec_shell(), "8042 kbd abc"));
+}
+
+ZTEST(keyboard_8042, test_console_cmd__internal)
+{
+	const char *outbuffer;
+	size_t buffer_size;
+
+	uint8_t resend_command[] = { 7, 8, 9 };
+
+	test_keyboard_8042_set_resend_command(resend_command,
+					      ARRAY_SIZE(resend_command));
+
+	/* Dump the internal state of the keyboard driver */
+	shell_backend_dummy_clear_output(get_ec_shell());
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "8042 internal"));
+	outbuffer =
+		shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+
+	zassert_true(buffer_size > 0);
+	zassert_ok(!strstr(outbuffer, "keyboard_enabled=0"));
+	zassert_ok(!strstr(outbuffer, "i8042_keyboard_irq_enabled=0"));
+	zassert_ok(!strstr(outbuffer, "i8042_aux_irq_enabled=0"));
+	zassert_ok(!strstr(outbuffer, "keyboard_enabled=0"));
+	zassert_ok(!strstr(outbuffer, "keystroke_enabled=0"));
+	zassert_ok(!strstr(outbuffer, "aux_chan_enabled=0"));
+	zassert_ok(!strstr(outbuffer, "controller_ram_address=0x00"));
+	zassert_ok(!strstr(outbuffer, "resend_command[]={0x07, 0x08, 0x09, }"));
+	zassert_ok(!strstr(outbuffer, "A20_status=0"));
+}
+
+ZTEST(keyboard_8042, test_console_cmd__invalid)
+{
+	/* Non-existent subcommand */
+	zassert_equal(EC_ERROR_PARAM1,
+		      shell_execute_cmd(get_ec_shell(), "8042 foobar"));
+}
+
+ZTEST(keyboard_8042, test_console_cmd__all)
+{
+	const char *outbuffer;
+	size_t buffer_size;
+
+	/* Run all the subcommands */
+	shell_backend_dummy_clear_output(get_ec_shell());
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "8042"));
+	outbuffer =
+		shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+
+	/* Just look for the headers since we already tested the individual
+	 * subcommands
+	 */
+
+	zassert_true(buffer_size > 0);
+	zassert_ok(!strstr(outbuffer, "- Typematic:"));
+	zassert_ok(!strstr(outbuffer, "- Codeset:"));
+	zassert_ok(!strstr(outbuffer, "- Control RAM:"));
+	zassert_ok(!strstr(outbuffer, "- Keyboard:"));
+	zassert_ok(!strstr(outbuffer, "- Internal:"));
+}
+
+FAKE_VOID_FUNC(chipset_reset, enum chipset_shutdown_reason);
+
+ZTEST(keyboard_8042, test_command__system_reset)
+{
+	keyboard_host_write(I8042_SYSTEM_RESET, true);
+
+	/* Pause a bit to allow the KB task to process */
+	k_sleep(K_MSEC(100));
+
+	zassert_equal(1, chipset_reset_fake.call_count);
+}
+
+FAKE_VOID_FUNC(lpc_keyboard_put_char, uint8_t, int);
+
+ZTEST(keyboard_8042, test_command__read_control_ram)
+{
+	/* Put test data (0x55) into control RAM */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "8042 ctrlram 0x1 0x55"));
+
+	/* Read offset 0 in the control RAM, which is actually address 0x01.
+	 * (address 0x00, the command register, is skipped over)
+	 */
+	keyboard_host_write(I8042_READ_CTL_RAM + 0, true);
+
+	/* Pause a bit to allow the KB task to process */
+	k_sleep(K_MSEC(100));
+
+	/* Check the correct byte was reported to the host. */
+	zassert_equal(1, lpc_keyboard_put_char_fake.call_count);
+	zassert_equal(0x55, lpc_keyboard_put_char_fake.arg0_history[0]);
+}
+
+ZTEST(keyboard_8042, test_command__a20)
+{
+	const char *outbuffer;
+	size_t buffer_size;
+
+	/* Enable A20 */
+	keyboard_host_write(I8042_ENABLE_A20, true);
+
+	/* Pause a bit to allow the KB task to process */
+	k_sleep(K_MSEC(100));
+
+	/* Verify A20 enabled */
+	shell_backend_dummy_clear_output(get_ec_shell());
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "8042 internal"));
+	outbuffer =
+		shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+
+	zassert_true(buffer_size > 0);
+	zassert_ok(!strstr(outbuffer, "A20_status=1"));
+
+	/* Disable A20 */
+	keyboard_host_write(I8042_DISABLE_A20, true);
+
+	/* Pause a bit to allow the KB task to process */
+	k_sleep(K_MSEC(100));
+
+	/* Verify A20 is not off */
+	shell_backend_dummy_clear_output(get_ec_shell());
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "8042 internal"));
+	outbuffer =
+		shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+
+	zassert_true(buffer_size > 0);
+	zassert_ok(!strstr(outbuffer, "A20_status=0"));
+}
+
+ZTEST(keyboard_8042, test_command__pulse)
+{
+	const char *outbuffer;
+	size_t buffer_size;
+
+	/* Sending this pulse command should enable A20 */
+	keyboard_host_write(I8042_PULSE_START | BIT(1), true);
+
+	/* Pause a bit to allow the KB task to process */
+	k_sleep(K_MSEC(100));
+
+	/* Verify A20 enabled */
+	shell_backend_dummy_clear_output(get_ec_shell());
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "8042 internal"));
+	outbuffer =
+		shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+
+	zassert_true(buffer_size > 0);
+	zassert_ok(!strstr(outbuffer, "A20_status=1"));
+}
+
+ZTEST(keyboard_8042, test_command__invalid)
+{
+	/* Unsupported command */
+	keyboard_host_write(0x00, true);
+
+	/* Pause a bit to allow the KB task to process */
+	k_sleep(K_MSEC(100));
+
+	/* Check for NAK sent back to host */
+	zassert_equal(1, lpc_keyboard_put_char_fake.call_count);
+	zassert_equal(I8042_RET_NAK,
+		      lpc_keyboard_put_char_fake.arg0_history[0]);
+}
+
+ZTEST(keyboard_8042, test_atkbdcommand__resend)
+{
+	uint8_t resend_data[] = { 0xAA, 0xBB, 0xCC };
+
+	/* Fill in test data to the resend buffer */
+	test_keyboard_8042_set_resend_command(resend_data,
+					      ARRAY_SIZE(resend_data));
+
+	/* Request a resend */
+	keyboard_host_write(ATKBD_CMD_RESEND, false);
+
+	/* Pause a bit to allow the KB task to process */
+	k_sleep(K_MSEC(100));
+
+	/* Check for above data being sent back to host */
+	zassert_equal(3, lpc_keyboard_put_char_fake.call_count);
+	zassert_equal(resend_data[0],
+		      lpc_keyboard_put_char_fake.arg0_history[0]);
+	zassert_equal(resend_data[1],
+		      lpc_keyboard_put_char_fake.arg0_history[1]);
+	zassert_equal(resend_data[2],
+		      lpc_keyboard_put_char_fake.arg0_history[2]);
+}
+
+ZTEST(keyboard_8042, test_atkbdcommand__unsupported__setall_mb)
+{
+	keyboard_host_write(ATKBD_CMD_SETALL_MB, false);
+
+	/* Pause a bit to allow the KB task to process */
+	k_sleep(K_MSEC(100));
+
+	/* Should respond with a resend request */
+	zassert_equal(1, lpc_keyboard_put_char_fake.call_count);
+	zassert_equal(ATKBD_RET_RESEND,
+		      lpc_keyboard_put_char_fake.arg0_history[0]);
+}
+
+ZTEST(keyboard_8042, test_atkbdcommand__unsupported__setall_mbr)
+{
+	keyboard_host_write(ATKBD_CMD_SETALL_MBR, false);
+
+	/* Pause a bit to allow the KB task to process */
+	k_sleep(K_MSEC(100));
+
+	/* Should respond with a resend request */
+	zassert_equal(1, lpc_keyboard_put_char_fake.call_count);
+	zassert_equal(ATKBD_RET_RESEND,
+		      lpc_keyboard_put_char_fake.arg0_history[0]);
+}
+
+ZTEST(keyboard_8042, test_atkbdcommand__unsupported__ex_enable)
+{
+	keyboard_host_write(ATKBD_CMD_EX_ENABLE, false);
+
+	/* Pause a bit to allow the KB task to process */
+	k_sleep(K_MSEC(100));
+
+	/* Should respond with a resend request */
+	zassert_equal(1, lpc_keyboard_put_char_fake.call_count);
+	zassert_equal(ATKBD_RET_RESEND,
+		      lpc_keyboard_put_char_fake.arg0_history[0]);
+}
+
+ZTEST(keyboard_8042, test_atkbdcommand__unsupported__bad_cmd)
+{
+	/* Non-existent ATKBD command */
+	keyboard_host_write(0x00, false);
+
+	/* Pause a bit to allow the KB task to process */
+	k_sleep(K_MSEC(100));
+
+	/* Should respond with a resend request */
+	zassert_equal(1, lpc_keyboard_put_char_fake.call_count);
+	zassert_equal(ATKBD_RET_RESEND,
+		      lpc_keyboard_put_char_fake.arg0_history[0]);
+}
+
+static void reset(void *fixture)
+{
+	ARG_UNUSED(fixture);
+
+	test_keyboard_8042_reset();
+
+	/* Fakes reset */
+	RESET_FAKE(chipset_reset);
+	RESET_FAKE(lpc_keyboard_put_char);
+}
+
+ZTEST_SUITE(keyboard_8042, drivers_predicate_post_main, NULL, reset, reset,
+	    NULL);
diff --git a/zephyr/test/drivers/keyboard_scan/CMakeLists.txt b/zephyr/test/drivers/keyboard_scan/CMakeLists.txt
new file mode 100644
index 0000000000..07040187f2
--- /dev/null
+++ b/zephyr/test/drivers/keyboard_scan/CMakeLists.txt
@@ -0,0 +1,15 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_sources(app PRIVATE
+  src/keyboard_backlight.c
+  src/keyboard_scan.c
+  src/keyboard_test_utils.c
+  src/mkbp_event.c
+  src/mkbp_info.c
+)
+
+target_include_directories(app PRIVATE
+    ${CMAKE_CURRENT_SOURCE_DIR}/include
+)
diff --git a/zephyr/test/drivers/keyboard_scan/include/keyboard_test_utils.h b/zephyr/test/drivers/keyboard_scan/include/keyboard_test_utils.h
new file mode 100644
index 0000000000..c8b127ca70
--- /dev/null
+++ b/zephyr/test/drivers/keyboard_scan/include/keyboard_test_utils.h
@@ -0,0 +1,19 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @brief Press or release a key through the keyboard emulator
+ *
+ * @param row Key row
+ * @param col Key column
+ * @param pressed 1 if pressed, 0 otherwise
+ * @return int 0 if successful
+ */
+int emulate_keystate(int row, int col, int pressed);
+
+/**
+ * @brief Clears any pressed keys in the keyboard emulator
+ */
+void clear_emulated_keys(void);
diff --git a/zephyr/test/drivers/keyboard_scan/src/keyboard_backlight.c b/zephyr/test/drivers/keyboard_scan/src/keyboard_backlight.c
new file mode 100644
index 0000000000..0f07b2fbcd
--- /dev/null
+++ b/zephyr/test/drivers/keyboard_scan/src/keyboard_backlight.c
@@ -0,0 +1,157 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "host_command.h"
+#include "keyboard_backlight.h"
+#include "pwm_mock.h"
+#include "test/drivers/test_state.h"
+
+#include <stdint.h>
+#include <string.h>
+
+#include <zephyr/drivers/pwm.h>
+#include <zephyr/kernel.h>
+#include <zephyr/shell/shell_dummy.h>
+#include <zephyr/ztest.h>
+#include <zephyr/ztest_assert.h>
+
+#define KBLIGHT_PWM_NODE DT_COMPAT_GET_ANY_STATUS_OKAY(cros_ec_kblight_pwm)
+
+extern const struct kblight_drv kblight_pwm;
+
+/**
+ * @brief Send host command to set the backlight percentage
+ *
+ * @param percent Backlight intensity, from 0 to 100 (inclusive).
+ * @return uint16_t Host command return code
+ */
+static uint16_t set_backlight_percent_helper(uint8_t percent)
+{
+	struct ec_params_pwm_set_keyboard_backlight params = {
+		.percent = percent
+	};
+
+	return ec_cmd_pwm_set_keyboard_backlight(NULL, &params);
+}
+
+ZTEST(keyboard_backlight, test_host_command_set_backlight__normal)
+{
+	/* Set the backlight intensity level to this and verify */
+	uint8_t expected_percentage = 50;
+
+	zassert_ok(set_backlight_percent_helper(expected_percentage), NULL);
+	zassert_equal(expected_percentage, kblight_get(), NULL);
+}
+
+ZTEST(keyboard_backlight, test_host_command_set_backlight__out_of_range)
+{
+	/* Too high */
+	uint8_t expected_percentage = 101;
+
+	zassert_equal(EC_RES_ERROR,
+		      set_backlight_percent_helper(expected_percentage), NULL);
+}
+
+ZTEST(keyboard_backlight, test_host_command_get_backlight__normal)
+{
+	/* Set this backlight intensity and verify via host command */
+	uint8_t expected_percentage = 50;
+	int ret;
+
+	zassert_ok(set_backlight_percent_helper(expected_percentage), NULL);
+
+	/* Brief delay to allow a deferred function to enable the backlight */
+	k_sleep(K_MSEC(50));
+
+	struct ec_response_pwm_get_keyboard_backlight response;
+
+	ret = ec_cmd_pwm_get_keyboard_backlight(NULL, &response);
+	zassert_ok(ret, "Host command failed: %d", ret);
+	zassert_equal(expected_percentage, response.percent, NULL);
+	zassert_equal(1, response.enabled, "Got 0x%02x", response.enabled);
+}
+
+ZTEST(keyboard_backlight, test_console_command__noargs)
+{
+	/* Command should print current status. Set backlight on and to 70% */
+
+	const char *outbuffer;
+	size_t buffer_size;
+
+	zassert_ok(set_backlight_percent_helper(70), NULL);
+	k_sleep(K_MSEC(50));
+
+	/* With no args, print current state */
+	shell_backend_dummy_clear_output(get_ec_shell());
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "kblight"), NULL);
+	outbuffer =
+		shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+
+	zassert_ok(!strstr(outbuffer, "Keyboard backlight: 70% enabled: 1"),
+		   "Actual string: `%s`", outbuffer);
+}
+
+ZTEST(keyboard_backlight, test_console_command__set_on)
+{
+	/* Command should enable backlight to given intensity */
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "kblight 65"), NULL);
+	zassert_equal(65, kblight_get(), NULL);
+	zassert_equal(1, kblight_get_current_enable(), NULL);
+}
+
+ZTEST(keyboard_backlight, test_console_command__set_off)
+{
+	zassert_ok(set_backlight_percent_helper(40), NULL);
+	k_sleep(K_MSEC(50));
+
+	/* Turn back off */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "kblight 0"), NULL);
+	zassert_equal(0, kblight_get(), NULL);
+	zassert_equal(0, kblight_get_current_enable(), NULL);
+}
+
+ZTEST(keyboard_backlight, test_console_command__bad_params)
+{
+	zassert_equal(EC_ERROR_PARAM1,
+		      shell_execute_cmd(get_ec_shell(), "kblight NaN"), NULL);
+	zassert_equal(EC_ERROR_PARAM1,
+		      shell_execute_cmd(get_ec_shell(), "kblight -1"), NULL);
+	zassert_equal(EC_ERROR_PARAM1,
+		      shell_execute_cmd(get_ec_shell(), "kblight 101"), NULL);
+}
+
+ZTEST(keyboard_backlight, test_set_backlight__device_not_ready)
+{
+	const struct pwm_dt_spec kblight_pwm_dt =
+		PWM_DT_SPEC_GET(KBLIGHT_PWM_NODE);
+	const struct device *pwm_dev = kblight_pwm_dt.dev;
+	int initial_duty;
+	int initialized_saved;
+
+	initial_duty = pwm_mock_get_duty(pwm_dev, kblight_pwm_dt.channel);
+
+	initialized_saved = pwm_dev->state->initialized;
+	pwm_dev->state->initialized = 0;
+
+	zassert_ok(kblight_pwm.set(initial_duty + 10), NULL);
+	zassert_equal(initial_duty,
+		      pwm_mock_get_duty(pwm_dev, kblight_pwm_dt.channel), NULL);
+
+	pwm_dev->state->initialized = initialized_saved;
+}
+
+static void reset(void *data)
+{
+	ARG_UNUSED(data);
+
+	/* Reset the backlight to off and 0% brightness */
+	kblight_set(0);
+	kblight_enable(0);
+}
+
+ZTEST_SUITE(keyboard_backlight, drivers_predicate_post_main, NULL, reset, reset,
+	    NULL);
diff --git a/zephyr/test/drivers/keyboard_scan/src/keyboard_scan.c b/zephyr/test/drivers/keyboard_scan/src/keyboard_scan.c
new file mode 100644
index 0000000000..fdae74cac1
--- /dev/null
+++ b/zephyr/test/drivers/keyboard_scan/src/keyboard_scan.c
@@ -0,0 +1,410 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "console.h"
+#include "host_command.h"
+#include "keyboard_scan.h"
+#include "keyboard_test_utils.h"
+#include "test/drivers/test_mocks.h"
+#include "test/drivers/test_state.h"
+
+#include <string.h>
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/fff.h>
+#include <zephyr/shell/shell_dummy.h>
+#include <zephyr/ztest.h>
+
+#include <emul/emul_kb_raw.h>
+
+ZTEST(keyboard_scan, test_boot_key)
+{
+	const struct device *dev = DEVICE_DT_GET(DT_NODELABEL(cros_kb_raw));
+	const int kb_cols = DT_PROP(DT_NODELABEL(cros_kb_raw), cols);
+
+	emul_kb_raw_reset(dev);
+	zassert_equal(keyboard_scan_get_boot_keys(), BOOT_KEY_NONE, NULL);
+
+	/* Case 1: refresh + esc -> BOOT_KEY_ESC */
+	emul_kb_raw_reset(dev);
+	zassert_ok(emulate_keystate(KEYBOARD_ROW_REFRESH, KEYBOARD_COL_REFRESH,
+				    true));
+	zassert_ok(emulate_keystate(KEYBOARD_ROW_ESC, KEYBOARD_COL_ESC, true));
+	keyboard_scan_init();
+	zassert_equal(keyboard_scan_get_boot_keys(), BOOT_KEY_ESC);
+
+	/*
+	 * Case 1.5:
+	 * GSC may hold ksi2 when power button is pressed, simulate this
+	 * behavior and verify boot key detection again.
+	 */
+	zassert_true(IS_ENABLED(CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2), NULL);
+	for (int i = 0; i < kb_cols; i++) {
+		zassert_ok(emulate_keystate(KEYBOARD_ROW_REFRESH, i, true));
+	}
+	keyboard_scan_init();
+	zassert_equal(keyboard_scan_get_boot_keys(), BOOT_KEY_ESC);
+
+	/* Case 2: esc only -> BOOT_KEY_NONE */
+	emul_kb_raw_reset(dev);
+	zassert_ok(emulate_keystate(KEYBOARD_ROW_ESC, KEYBOARD_COL_ESC, true));
+	keyboard_scan_init();
+	zassert_equal(keyboard_scan_get_boot_keys(), BOOT_KEY_NONE);
+
+	/* Case 3: refresh + arrow down -> BOOT_KEY_DOWN_ARROW */
+	emul_kb_raw_reset(dev);
+	zassert_ok(emulate_keystate(KEYBOARD_ROW_REFRESH, KEYBOARD_COL_REFRESH,
+				    true));
+	zassert_ok(
+		emulate_keystate(KEYBOARD_ROW_DOWN, KEYBOARD_COL_DOWN, true));
+	keyboard_scan_init();
+	zassert_equal(keyboard_scan_get_boot_keys(), BOOT_KEY_DOWN_ARROW);
+
+	/* Case 4: refresh + L shift -> BOOT_KEY_LEFT_SHIFT */
+	emul_kb_raw_reset(dev);
+	zassert_ok(emulate_keystate(KEYBOARD_ROW_REFRESH, KEYBOARD_COL_REFRESH,
+				    true));
+	zassert_ok(emulate_keystate(KEYBOARD_ROW_LEFT_SHIFT,
+				    KEYBOARD_COL_LEFT_SHIFT, true));
+	keyboard_scan_init();
+	zassert_equal(keyboard_scan_get_boot_keys(), BOOT_KEY_LEFT_SHIFT);
+
+	/* Case 5: refresh + esc + other random key -> BOOT_KEY_NONE */
+	emul_kb_raw_reset(dev);
+	zassert_ok(emulate_keystate(KEYBOARD_ROW_REFRESH, KEYBOARD_COL_REFRESH,
+				    true));
+	zassert_ok(emulate_keystate(KEYBOARD_ROW_ESC, KEYBOARD_COL_ESC, true));
+	zassert_ok(
+		emulate_keystate(KEYBOARD_ROW_KEY_0, KEYBOARD_COL_KEY_0, true));
+	keyboard_scan_init();
+	zassert_equal(keyboard_scan_get_boot_keys(), BOOT_KEY_NONE);
+
+	/* Case 6: BOOT_KEY_NONE after late sysjump */
+	system_jumped_late_fake.return_val = 1;
+	emul_kb_raw_reset(dev);
+	zassert_ok(emulate_keystate(KEYBOARD_ROW_REFRESH, KEYBOARD_COL_REFRESH,
+				    true));
+	zassert_ok(emulate_keystate(KEYBOARD_ROW_LEFT_SHIFT,
+				    KEYBOARD_COL_LEFT_SHIFT, true));
+	keyboard_scan_init();
+	zassert_equal(keyboard_scan_get_boot_keys(), BOOT_KEY_NONE);
+}
+
+ZTEST(keyboard_scan, test_press_enter)
+{
+	zassert_ok(emulate_keystate(4, 11, true));
+	k_sleep(K_MSEC(100));
+	/* TODO(jbettis): Check espi_emul to verify the AP was notified. */
+	zassert_ok(emulate_keystate(4, 11, false));
+	k_sleep(K_MSEC(100));
+}
+
+ZTEST(keyboard_scan, test_console_command_ksstate__noargs)
+{
+	const char *outbuffer;
+	size_t buffer_size;
+
+	/* With no args, print current state */
+	shell_backend_dummy_clear_output(get_ec_shell());
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "ksstate"));
+	outbuffer =
+		shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+
+	/* Check for some expected lines */
+	zassert_true(buffer_size > 0);
+	zassert_ok(!strstr(outbuffer, "Keyboard scan disable mask: 0x00000000"),
+		   "Output was: `%s`", outbuffer);
+	zassert_ok(!strstr(outbuffer, "Keyboard scan state printing off"),
+		   "Output was: `%s`", outbuffer);
+
+	/* Ensure we are still scanning */
+	zassert_true(keyboard_scan_is_enabled());
+}
+
+ZTEST(keyboard_scan, test_console_command_ksstate__force)
+{
+	/* This command forces the keyboard to start scanning (if not already)
+	 * and enable state change printing. To test: turn scanning off, run
+	 * command, and verify we are scanning and printing state
+	 */
+
+	keyboard_scan_enable(false, -1);
+	zassert_false(keyboard_scan_is_enabled());
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "ksstate force"));
+
+	zassert_true(keyboard_scan_is_enabled());
+	zassert_true(keyboard_scan_get_print_state_changes());
+}
+
+ZTEST(keyboard_scan, test_console_command_ksstate__on_off)
+{
+	/* This command turns state change printing on/off */
+
+	zassert_false(keyboard_scan_get_print_state_changes());
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "ksstate on"));
+	zassert_true(keyboard_scan_get_print_state_changes());
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "ksstate off"));
+	zassert_false(keyboard_scan_get_print_state_changes());
+}
+
+ZTEST(keyboard_scan, test_console_command_ksstate__invalid)
+{
+	/* Pass a string that cannot be parsed as a bool */
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "ksstate xyz"));
+}
+
+ZTEST(keyboard_scan, test_console_command_kbpress__noargs)
+{
+	const char *outbuffer;
+	size_t buffer_size;
+
+	/* With no args, print list of simulated keys */
+	shell_backend_dummy_clear_output(get_ec_shell());
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "kbpress"));
+	outbuffer =
+		shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+
+	/* Check for an expected line */
+	zassert_true(buffer_size > 0);
+	zassert_ok(!strstr(outbuffer, "Simulated keys:"), "Output was: `%s`",
+		   outbuffer);
+}
+
+ZTEST(keyboard_scan, test_console_command_kbpress__invalid)
+{
+	/* Row or column number out of range, or wrong type */
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "kbpress -1 0"));
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "kbpress foo 0"));
+	zassert_ok(!shell_execute_cmd(
+		get_ec_shell(), "kbpress " STRINGIFY(KEYBOARD_COLS_MAX) " 0"));
+
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "kbpress 0 -1"));
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "kbpress 0 foo"));
+	zassert_ok(!shell_execute_cmd(
+		get_ec_shell(), "kbpress 0 " STRINGIFY(KEYBOARD_COLS_MAX)));
+}
+
+/* Mock the key_state_changed callback that the key scan task invokes whenever
+ * a key event occurs. This will capture a history of key presses.
+ */
+FAKE_VOID_FUNC(key_state_changed, int, int, uint8_t);
+
+ZTEST(keyboard_scan, test_console_command_kbpress__press)
+{
+	/* Press and release a key */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "kbpress 1 2"));
+
+	/* Pause a bit to allow the key scan task to process. */
+	k_sleep(K_MSEC(500));
+
+	/* Expect two key events */
+	zassert_equal(2, key_state_changed_fake.call_count);
+
+	/* Press col=1,row=2 (state==1) */
+	zassert_equal(1, key_state_changed_fake.arg1_history[0]);
+	zassert_equal(2, key_state_changed_fake.arg0_history[0]);
+	zassert_true(key_state_changed_fake.arg2_history[0]);
+
+	/* Release col=1,row=2 (state==0) */
+	zassert_equal(1, key_state_changed_fake.arg1_history[1]);
+	zassert_equal(2, key_state_changed_fake.arg0_history[1]);
+	zassert_false(key_state_changed_fake.arg2_history[1]);
+}
+
+ZTEST(keyboard_scan, test_console_command_kbpress__down_and_up)
+{
+	/* Hold a key down */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "kbpress 3 4 1"));
+
+	/* Release the key */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "kbpress 3 4 0"));
+
+	/* Pause a bit to allow the key scan task to process. */
+	k_sleep(K_MSEC(500));
+
+	/* Expect two key events */
+	zassert_equal(2, key_state_changed_fake.call_count,
+		      "Actual call_count=%d",
+		      key_state_changed_fake.call_count);
+
+	/* Press col=3,row=4 (state==1) */
+	zassert_equal(3, key_state_changed_fake.arg1_history[0]);
+	zassert_equal(4, key_state_changed_fake.arg0_history[0]);
+	zassert_true(key_state_changed_fake.arg2_history[0]);
+
+	/* Release col=3,row=4 (state==0) */
+	zassert_equal(3, key_state_changed_fake.arg1_history[1]);
+	zassert_equal(4, key_state_changed_fake.arg0_history[1]);
+	zassert_false(key_state_changed_fake.arg2_history[1]);
+}
+
+ZTEST(keyboard_scan, test_host_command_simulate_key__locked)
+{
+	uint16_t ret;
+
+	zassert_true(system_is_locked(), "Expecting locked system.");
+
+	struct ec_params_mkbp_simulate_key params;
+
+	ret = ec_cmd_mkbp_simulate_key(NULL, &params);
+	zassert_equal(EC_RES_ACCESS_DENIED, ret, "Command returned %u", ret);
+}
+
+ZTEST(keyboard_scan, test_host_command_simulate_key__bad_params)
+{
+	uint16_t ret;
+
+	system_is_locked_fake.return_val = 0;
+	zassert_false(system_is_locked(), "Expecting unlocked system.");
+
+	struct ec_params_mkbp_simulate_key params = {
+		.col = KEYBOARD_COLS_MAX,
+		.row = KEYBOARD_ROWS,
+	};
+
+	ret = ec_cmd_mkbp_simulate_key(NULL, &params);
+	zassert_equal(EC_RES_INVALID_PARAM, ret, "Command returned %u", ret);
+}
+
+/**
+ * @brief Helper function that sends a host command to press or release the
+ *        specified key.
+ *
+ * @param col Key column
+ * @param row Key row
+ * @param pressed 1=press, 0=release
+ * @return uint16_t Host command return code.
+ */
+static uint16_t send_keypress_host_command(uint8_t col, uint8_t row,
+					   uint8_t pressed)
+{
+	struct ec_params_mkbp_simulate_key params = {
+		.col = col,
+		.row = row,
+		.pressed = pressed,
+	};
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_PARAMS(EC_CMD_MKBP_SIMULATE_KEY, 0, params);
+
+	return host_command_process(&args);
+}
+
+ZTEST(keyboard_scan, test_host_command_simulate__key_press)
+{
+	uint16_t ret;
+
+	system_is_locked_fake.return_val = 0;
+	zassert_false(system_is_locked(), "Expecting unlocked system.");
+
+	ret = send_keypress_host_command(1, 2, 1);
+	zassert_equal(EC_RES_SUCCESS, ret, "Command returned %u", ret);
+
+	/* Release the key */
+	ret = send_keypress_host_command(1, 2, 0);
+	zassert_equal(EC_RES_SUCCESS, ret, "Command returned %u", ret);
+
+	/* Verify key events happened */
+
+	zassert_equal(2, key_state_changed_fake.call_count);
+
+	/* Press col=1,row=2 (state==1) */
+	zassert_equal(1, key_state_changed_fake.arg1_history[0]);
+	zassert_equal(2, key_state_changed_fake.arg0_history[0]);
+	zassert_true(key_state_changed_fake.arg2_history[0]);
+
+	/* Release col=1,row=2 (state==0) */
+	zassert_equal(1, key_state_changed_fake.arg1_history[1]);
+	zassert_equal(2, key_state_changed_fake.arg0_history[1]);
+	zassert_false(key_state_changed_fake.arg2_history[1]);
+}
+
+FAKE_VOID_FUNC(system_enter_hibernate, uint32_t, uint32_t);
+FAKE_VOID_FUNC(chipset_reset, int);
+
+ZTEST(keyboard_scan, test_special_key_combos)
+{
+	system_is_locked_fake.return_val = 0;
+	zassert_false(system_is_locked(), "Expecting unlocked system.");
+
+	/* Set the volume up key coordinates to something arbitrary */
+	int vol_up_col = 1;
+	int vol_up_row = 2;
+
+	set_vol_up_key(vol_up_row, vol_up_col);
+
+	/* Vol up and the alt keys must be in different columns */
+	zassert_false(vol_up_col == KEYBOARD_COL_LEFT_ALT, NULL);
+
+	/* Hold down volume up, left alt (either alt key works), and R */
+	zassert_ok(send_keypress_host_command(vol_up_col, vol_up_row, 1));
+	zassert_ok(send_keypress_host_command(KEYBOARD_COL_LEFT_ALT,
+					      KEYBOARD_ROW_LEFT_ALT, 1));
+	zassert_ok(send_keypress_host_command(KEYBOARD_COL_KEY_R,
+					      KEYBOARD_ROW_KEY_R, 1));
+
+	k_sleep(K_MSEC(100));
+
+	/* Release R and the press H */
+	zassert_ok(send_keypress_host_command(KEYBOARD_COL_KEY_R,
+					      KEYBOARD_ROW_KEY_R, 0));
+	zassert_ok(send_keypress_host_command(KEYBOARD_COL_KEY_H,
+					      KEYBOARD_ROW_KEY_H, 1));
+
+	k_sleep(K_MSEC(100));
+
+	/* Release all */
+	zassert_ok(send_keypress_host_command(vol_up_col, vol_up_row, 0));
+	zassert_ok(send_keypress_host_command(KEYBOARD_COL_LEFT_ALT,
+					      KEYBOARD_ROW_LEFT_ALT, 0));
+	zassert_ok(send_keypress_host_command(KEYBOARD_COL_KEY_H,
+					      KEYBOARD_ROW_KEY_H, 0));
+
+	/* Check that a reboot was requested (VOLUP + ALT + R) */
+	zassert_equal(1, chipset_reset_fake.call_count,
+		      "Did not try to reboot");
+	zassert_equal(CHIPSET_RESET_KB_WARM_REBOOT,
+		      chipset_reset_fake.arg0_history[0]);
+
+	/* Check that we called system_enter_hibernate (VOLUP + ALT + H) */
+	zassert_equal(1, system_enter_hibernate_fake.call_count,
+		      "Did not enter hibernate");
+}
+
+static void reset_keyboard(void *data)
+{
+	ARG_UNUSED(data);
+
+	/* Enable scanning and clear all reason bits (reason bits explain why
+	 * scanning was disabled -- see `enum kb_scan_disable_masks`)
+	 */
+	keyboard_scan_enable(true, -1);
+
+	/* Turn off key state change printing */
+	keyboard_scan_set_print_state_changes(0);
+
+	/* Reset KB emulator */
+	clear_emulated_keys();
+
+	/* Clear debouncing state to prevent latent key presses from appearing
+	 * in a later test.
+	 */
+	test_keyboard_scan_debounce_reset();
+
+	/* Reset all mocks. */
+	RESET_FAKE(key_state_changed);
+	RESET_FAKE(system_is_locked);
+	RESET_FAKE(system_enter_hibernate);
+	RESET_FAKE(chipset_reset);
+
+	/* Be locked by default */
+	system_is_locked_fake.return_val = 1;
+}
+
+ZTEST_SUITE(keyboard_scan, drivers_predicate_post_main, NULL, reset_keyboard,
+	    reset_keyboard, NULL);
diff --git a/zephyr/test/drivers/keyboard_scan/src/keyboard_test_utils.c b/zephyr/test/drivers/keyboard_scan/src/keyboard_test_utils.c
new file mode 100644
index 0000000000..4141028408
--- /dev/null
+++ b/zephyr/test/drivers/keyboard_scan/src/keyboard_test_utils.c
@@ -0,0 +1,20 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/drivers/emul.h>
+
+#include <emul/emul_kb_raw.h>
+
+const static struct device *dev = DEVICE_DT_GET(DT_NODELABEL(cros_kb_raw));
+
+int emulate_keystate(int row, int col, int pressed)
+{
+	return emul_kb_raw_set_kbstate(dev, row, col, pressed);
+}
+
+void clear_emulated_keys(void)
+{
+	emul_kb_raw_reset(dev);
+}
diff --git a/zephyr/test/drivers/keyboard_scan/src/mkbp_event.c b/zephyr/test/drivers/keyboard_scan/src/mkbp_event.c
new file mode 100644
index 0000000000..5184158cef
--- /dev/null
+++ b/zephyr/test/drivers/keyboard_scan/src/mkbp_event.c
@@ -0,0 +1,339 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "chipset.h"
+#include "console.h"
+#include "host_command.h"
+#include "mkbp_event.h"
+#include "mkbp_fifo.h"
+#include "test/drivers/test_mocks.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/fff.h>
+#include <zephyr/ztest.h>
+
+#include <emul/emul_kb_raw.h>
+
+/**
+ * @brief FFF fake that will be registered as a callback to monitor the EC->AP
+ *        interrupt pin. Implements `gpio_callback_handler_t`.
+ */
+FAKE_VOID_FUNC(interrupt_gpio_monitor, const struct device *,
+	       struct gpio_callback *, gpio_port_pins_t);
+
+/**
+ * @brief Fixture to hold state while the suite is running.
+ */
+struct event_fixture {
+	/** Configuration for the interrupt pin change callback */
+	struct gpio_callback callback_config;
+};
+
+static struct event_fixture fixture;
+
+ZTEST(mkbp_event, test_host_command_get_events__empty)
+{
+	/* Issue a host command to get the next event (from any source) */
+	uint16_t ret;
+	struct ec_response_get_next_event response;
+
+	ret = ec_cmd_get_next_event(NULL, &response);
+	zassert_equal(EC_RES_UNAVAILABLE, ret,
+		      "Expected EC_RES_UNAVAILABLE but got %d", ret);
+}
+
+ZTEST(mkbp_event, test_activate_with_events)
+{
+	const struct device *gpio_dev = DEVICE_DT_GET(
+		DT_GPIO_CTLR(DT_NODELABEL(gpio_ap_ec_int_l), gpios));
+	const int gpio_pin = DT_GPIO_PIN(DT_NODELABEL(gpio_ap_ec_int_l), gpios);
+
+	/* Put the chipset to sleep */
+	chipset_force_shutdown(CHIPSET_SHUTDOWN_BUTTON);
+	k_sleep(K_SECONDS(15));
+
+	/* Activate with no events, should not trigger an interrupt */
+	activate_mkbp_with_events(0);
+
+	/* Check that GPIO is still 1 */
+	zassert_equal(1, gpio_emul_output_get(gpio_dev, gpio_pin));
+}
+
+ZTEST(mkbp_event, test_host_command_host_event_wake_mask)
+{
+	struct ec_response_mkbp_event_wake_mask response = { 0 };
+	struct ec_params_mkbp_event_wake_mask params = { 0 };
+
+	/* Set the wake mask to 0x12345678 */
+	params.action = SET_WAKE_MASK;
+	params.mask_type = EC_MKBP_HOST_EVENT_WAKE_MASK;
+	params.new_wake_mask = 0x12345678;
+
+	zassert_ok(ec_cmd_mkbp_wake_mask(NULL, &params, &response));
+
+	/* Get the wake mask */
+	params.action = GET_WAKE_MASK;
+
+	zassert_ok(ec_cmd_mkbp_wake_mask(NULL, &params, &response));
+	zassert_equal(0x12345678, response.wake_mask);
+}
+
+ZTEST(mkbp_event, test_host_command_event_wake_mask)
+{
+	struct ec_response_mkbp_event_wake_mask response = { 0 };
+	struct ec_params_mkbp_event_wake_mask params = { 0 };
+
+	/* Set the wake mask to 0x87654321 */
+	params.action = SET_WAKE_MASK;
+	params.mask_type = EC_MKBP_EVENT_WAKE_MASK;
+	params.new_wake_mask = 0x87654321;
+
+	zassert_ok(ec_cmd_mkbp_wake_mask(NULL, &params, &response));
+
+	/* Get the wake mask */
+	params.action = GET_WAKE_MASK;
+
+	zassert_ok(ec_cmd_mkbp_wake_mask(NULL, &params, &response));
+	zassert_equal(0x87654321, response.wake_mask);
+}
+
+ZTEST(mkbp_event, test_host_command_wake_mask__invalid_args)
+{
+	struct ec_response_mkbp_event_wake_mask response = { 0 };
+	struct ec_params_mkbp_event_wake_mask params = {
+		.action = -1,
+		.mask_type = -1,
+	};
+
+	/* Check invalid action */
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      ec_cmd_mkbp_wake_mask(NULL, &params, &response));
+
+	/* Check invalid mask type in getter */
+	params.action = GET_WAKE_MASK;
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      ec_cmd_mkbp_wake_mask(NULL, &params, &response));
+
+	/* Check invalid mask type in setter */
+	params.action = SET_WAKE_MASK;
+	zassert_equal(EC_RES_INVALID_PARAM,
+		      ec_cmd_mkbp_wake_mask(NULL, &params, &response));
+}
+
+ZTEST(mkbp_event, test_console_command_wake_mask_event)
+{
+	check_console_cmd("mkbpwakemask event 500",
+			  "MKBP event wake mask: 0x000001f4", 0, __FILE__,
+			  __LINE__);
+	check_console_cmd("mkbpwakemask hostevent 7934",
+			  "MKBP host event wake mask: 0x00001efe", 0, __FILE__,
+			  __LINE__);
+	check_console_cmd("mkbpwakemask event f", NULL, EC_ERROR_PARAM2,
+			  __FILE__, __LINE__);
+	check_console_cmd("mkbpwakemask event", NULL, EC_ERROR_PARAM_COUNT,
+			  __FILE__, __LINE__);
+}
+
+ZTEST(mkbp_event, test_host_command_get_events__get_event)
+{
+	/* Dispatch a fake keyboard event and ensure it gets returned by the
+	 * host command.
+	 */
+	int ret;
+
+	struct ec_response_get_next_event expected_event = {
+		.event_type = EC_MKBP_EVENT_KEY_MATRIX,
+		.data.key_matrix = {
+			/* Arbitrary key matrix data (uint8_t[13]) */
+			0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0xb,
+			0xc, 0xd
+		},
+	};
+
+	/* Add the above event to the MKBP keyboard FIFO and raise the event */
+
+	ret = mkbp_fifo_add(expected_event.event_type,
+			    (const uint8_t *)&expected_event.data.key_matrix);
+	activate_mkbp_with_events(BIT(expected_event.event_type));
+
+	zassert_equal(EC_SUCCESS, ret, "Got %d when adding to FIFO", ret);
+
+	/* Retrieve this event via host command */
+
+	struct ec_response_get_next_event response;
+
+	ret = ec_cmd_get_next_event(NULL, &response);
+	zassert_equal(EC_RES_SUCCESS, ret, "Expected EC_RES_SUCCESS but got %d",
+		      ret);
+
+	/* Compare event data in response */
+	zassert_equal(expected_event.event_type, response.event_type,
+		      "Got event type 0x%02x", response.event_type);
+	zassert_mem_equal(&expected_event.data.key_matrix,
+			  &response.data.key_matrix,
+			  sizeof(expected_event.data.key_matrix),
+			  "Event data payload does not match.");
+
+	/* Check for two pin change events (initial assertion when the event
+	 * was sent, and a de-assertion once we retrieved it through the host
+	 * command)
+	 */
+
+	zassert_equal(2, interrupt_gpio_monitor_fake.call_count,
+		      "Only %d pin events",
+		      interrupt_gpio_monitor_fake.call_count);
+}
+
+ZTEST(mkbp_event, test_host_command_get_events__get_event_v2)
+{
+	/*
+	 * Dispatch some fake events and ensure they get returned by the
+	 * host command. Event types must be different.
+	 */
+
+	const struct ec_response_get_next_event expected_event = {
+		.event_type = EC_MKBP_EVENT_KEY_MATRIX,
+		.data.key_matrix = {
+			/* Arbitrary key matrix data (uint8_t[13]) */
+			0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0xb,
+			0xc, 0xd
+		},
+	};
+	const struct ec_response_get_next_event expected_event2 = {
+		.event_type = EC_MKBP_EVENT_BUTTON,
+		.data.buttons = BIT(EC_MKBP_VOL_UP) | BIT(EC_MKBP_VOL_DOWN),
+	};
+	int ret;
+
+	/*
+	 * Add the above events to the MKBP keyboard FIFO and raise the
+	 * events
+	 */
+
+	ret = mkbp_fifo_add(expected_event.event_type,
+			    expected_event.data.key_matrix);
+	zassert_equal(EC_SUCCESS, ret, "Got %d when adding to FIFO", ret);
+
+	ret = mkbp_fifo_add(expected_event2.event_type,
+			    expected_event2.data.key_matrix);
+	zassert_equal(EC_SUCCESS, ret, "Got %d when adding to FIFO", ret);
+
+	activate_mkbp_with_events(BIT(expected_event.event_type));
+	activate_mkbp_with_events(BIT(expected_event2.event_type));
+
+	/* Retrieve these events via host commands */
+
+	struct ec_response_get_next_event response;
+
+	ret = ec_cmd_get_next_event_v2(NULL, &response);
+	zassert_equal(EC_RES_SUCCESS, ret, "Expected EC_RES_SUCCESS but got %d",
+		      ret);
+	zassert_true((response.event_type & EC_MKBP_HAS_MORE_EVENTS) != 0,
+		     "Expected EC_MKBP_HAS_MORE_EVENTS but got 0x%x",
+		     response.event_type);
+
+	ret = ec_cmd_get_next_event_v2(NULL, &response);
+	zassert_equal(EC_RES_SUCCESS, ret, "Expected EC_RES_SUCCESS but got %d",
+		      ret);
+	zassert_true((response.event_type & EC_MKBP_HAS_MORE_EVENTS) == 0,
+		     "Expected no EC_MKBP_HAS_MORE_EVENTS but got 0x%x",
+		     response.event_type);
+}
+
+ZTEST(mkbp_event, test_no_ap_response)
+{
+	/* Cause an event but do not send any host commands. This should cause
+	 * the EC to send the interrupt to the AP 3 times before giving up.
+	 * Use the GPIO emulator to monitor for interrupts.
+	 */
+
+	int ret;
+
+	struct ec_response_get_next_event expected_event = {
+		.event_type = EC_MKBP_EVENT_KEY_MATRIX,
+	};
+
+	ret = mkbp_fifo_add(expected_event.event_type,
+			    (uint8_t *)&expected_event.data.key_matrix);
+	activate_mkbp_with_events(BIT(expected_event.event_type));
+	zassert_equal(EC_SUCCESS, ret, "Got %d when adding to FIFO", ret);
+
+	/* EC will attempt to signal the interrupt 3 times. Each attempt lasts
+	 * 1 second, so sleep for 5 and then count the number of times the
+	 * interrupt pin was asserted. (It does not get de-asserted)
+	 */
+
+	k_sleep(K_SECONDS(5));
+
+	zassert_equal(3, interrupt_gpio_monitor_fake.call_count,
+		      "Interrupt pin asserted only %d times.",
+		      interrupt_gpio_monitor_fake.call_count);
+}
+
+/* Set up a mock for mkbp_send_event(). This function is called by the MKBP
+ * event sources to signal that a new event is available for servicing. Since we
+ * are unit testing just event handling code, we do not want the various event
+ * source tasks to raise unexpected events during testing and throw us off.
+ * This mock will essentially cause mkbp_send_event() to become a no-op and
+ * block the reset of the EC code from raising events and interfering. The test
+ * code will bypass this by calling mkbp_event.c's internal
+ * `activate_mkbp_with_events()` directly.
+ */
+FAKE_VALUE_FUNC(int, mkbp_send_event, uint8_t);
+
+static void *setup(void)
+{
+	/* Add a callback to the EC->AP interrupt pin so we can log interrupt
+	 * attempts with an FFF fake.
+	 */
+
+	const struct gpio_dt_spec *interrupt_pin =
+		GPIO_DT_FROM_NODELABEL(gpio_ap_ec_int_l);
+
+	fixture.callback_config = (struct gpio_callback){
+		.pin_mask = BIT(interrupt_pin->pin),
+		.handler = interrupt_gpio_monitor,
+	};
+
+	zassert_ok(gpio_add_callback(interrupt_pin->port,
+				     &fixture.callback_config),
+		   "Could not configure GPIO callback.");
+
+	return &fixture;
+}
+
+static void teardown(void *data)
+{
+	/* Remove the GPIO callback on the interrupt pin */
+
+	struct event_fixture *f = (struct event_fixture *)data;
+	const struct gpio_dt_spec *interrupt_pin =
+		GPIO_DT_FROM_NODELABEL(gpio_ap_ec_int_l);
+
+	gpio_remove_callback(interrupt_pin->port, &f->callback_config);
+}
+
+static void reset_events(void *data)
+{
+	/* Clear any keyboard scan events (type EC_MKBP_EVENT_KEY_MATRIX) */
+	mkbp_clear_fifo();
+
+	/* Clear pending events */
+	mkbp_event_clear_all();
+
+	/* Mock reset */
+	RESET_FAKE(interrupt_gpio_monitor);
+	RESET_FAKE(mkbp_send_event);
+	mkbp_send_event_fake.return_val = 1;
+
+	test_set_chipset_to_s0();
+}
+
+ZTEST_SUITE(mkbp_event, drivers_predicate_post_main, setup, reset_events,
+	    reset_events, teardown);
diff --git a/zephyr/test/drivers/keyboard_scan/src/mkbp_info.c b/zephyr/test/drivers/keyboard_scan/src/mkbp_info.c
new file mode 100644
index 0000000000..0588324c91
--- /dev/null
+++ b/zephyr/test/drivers/keyboard_scan/src/mkbp_info.c
@@ -0,0 +1,200 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "console.h"
+#include "host_command.h"
+#include "keyboard_scan.h"
+#include "keyboard_test_utils.h"
+#include "mkbp_info.h"
+#include "mkbp_input_devices.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/fff.h>
+#include <zephyr/ztest.h>
+
+#include <emul/emul_kb_raw.h>
+
+ZTEST(mkbp_info, test_host_command_mkbp_info__keyboard_info)
+{
+	/* Get the number of keyboard rows and columns */
+
+	int ret;
+	struct ec_response_mkbp_info response;
+	struct ec_params_mkbp_info request = {
+		.info_type = EC_MKBP_INFO_KBD,
+	};
+
+	ret = ec_cmd_mkbp_info(NULL, &request, &response);
+	zassert_equal(EC_SUCCESS, ret, "Host command failed: %d", ret);
+	zassert_equal(KEYBOARD_ROWS, response.rows, NULL);
+	zassert_equal(KEYBOARD_COLS_MAX, response.cols, NULL);
+}
+
+ZTEST(mkbp_info, test_host_command_mkbp_info__supported_buttons)
+{
+	/* Get the set of supported buttons */
+
+	int ret;
+	union ec_response_get_next_data response;
+	struct ec_params_mkbp_info request = {
+		.info_type = EC_MKBP_INFO_SUPPORTED,
+		.event_type = EC_MKBP_EVENT_BUTTON,
+	};
+
+	ret = ec_cmd_mkbp_info_get_next_data(NULL, &request, &response);
+	zassert_equal(EC_SUCCESS, ret, "Host command failed: %d", ret);
+	zassert_equal(get_supported_buttons(), response.buttons, NULL);
+}
+
+ZTEST(mkbp_info, test_host_command_mkbp_info__supported_switches)
+{
+	/* Get the set of supported switches */
+
+	int ret;
+	union ec_response_get_next_data response;
+	struct ec_params_mkbp_info request = {
+		.info_type = EC_MKBP_INFO_SUPPORTED,
+		.event_type = EC_MKBP_EVENT_SWITCH,
+	};
+
+	ret = ec_cmd_mkbp_info_get_next_data(NULL, &request, &response);
+	zassert_equal(EC_SUCCESS, ret, "Host command failed: %d", ret);
+	zassert_equal(get_supported_switches(), response.switches, NULL);
+}
+
+ZTEST(mkbp_info, test_host_command_mkbp_info__supported_invalid)
+{
+	/* Request support info on a non-existent type of input device. */
+
+	int ret;
+	union ec_response_get_next_data response;
+	struct ec_params_mkbp_info request = {
+		.info_type = EC_MKBP_INFO_SUPPORTED,
+		.event_type = EC_MKBP_EVENT_COUNT, /* Unsupported */
+	};
+
+	ret = ec_cmd_mkbp_info_get_next_data(NULL, &request, &response);
+	zassert_equal(EC_RES_INVALID_PARAM, ret,
+		      "Host command didn't fail properly: %d", ret);
+}
+
+ZTEST(mkbp_info, test_host_command_mkbp_info__current_keyboard_matrix)
+{
+	/* Hold down a key so we can validate the returned keyboard matrix state
+	 */
+	const struct device *dev = DEVICE_DT_GET(DT_NODELABEL(cros_kb_raw));
+
+	emul_kb_raw_set_kbstate(dev, KEYBOARD_ROW_KEY_R, KEYBOARD_COL_KEY_R, 1);
+	keyboard_scan_init();
+
+	k_sleep(K_MSEC(100));
+
+	/* Get the current keyboard matrix state */
+
+	int ret;
+	union ec_response_get_next_data response;
+	struct ec_params_mkbp_info request = {
+		.info_type = EC_MKBP_INFO_CURRENT,
+		.event_type = EC_MKBP_EVENT_KEY_MATRIX,
+	};
+
+	ret = ec_cmd_mkbp_info_get_next_data(NULL, &request, &response);
+	zassert_equal(EC_SUCCESS, ret, "Host command failed: %d", ret);
+
+	zassert_true(response.key_matrix[KEYBOARD_COL_KEY_R] &
+			     KEYBOARD_MASK_KEY_R,
+		     "Expected key is not pressed");
+}
+
+ZTEST(mkbp_info, test_host_command_mkbp_info__current_host_events)
+{
+	int ret;
+	union ec_response_get_next_data response;
+	struct ec_params_mkbp_info request = {
+		.info_type = EC_MKBP_INFO_CURRENT,
+		.event_type = EC_MKBP_EVENT_HOST_EVENT,
+	};
+
+	ret = ec_cmd_mkbp_info_get_next_data(NULL, &request, &response);
+	zassert_equal(EC_SUCCESS, ret, "Host command failed: %d", ret);
+	zassert_equal((uint32_t)host_get_events(), response.host_event, NULL);
+}
+
+ZTEST(mkbp_info, test_host_command_mkbp_info__current_host_events64)
+{
+	int ret;
+	union ec_response_get_next_data response;
+	struct ec_params_mkbp_info request = {
+		.info_type = EC_MKBP_INFO_CURRENT,
+		.event_type = EC_MKBP_EVENT_HOST_EVENT64,
+	};
+
+	ret = ec_cmd_mkbp_info_get_next_data(NULL, &request, &response);
+	zassert_equal(EC_SUCCESS, ret, "Host command failed: %d", ret);
+	zassert_equal(host_get_events(), response.host_event64, NULL);
+}
+
+ZTEST(mkbp_info, test_host_command_mkbp_info__current_buttons)
+{
+	int ret;
+	union ec_response_get_next_data response;
+	struct ec_params_mkbp_info request = {
+		.info_type = EC_MKBP_INFO_CURRENT,
+		.event_type = EC_MKBP_EVENT_BUTTON,
+	};
+
+	ret = ec_cmd_mkbp_info_get_next_data(NULL, &request, &response);
+	zassert_equal(EC_SUCCESS, ret, "Host command failed: %d", ret);
+	zassert_equal(mkbp_get_button_state(), response.buttons, NULL);
+}
+
+ZTEST(mkbp_info, test_host_command_mkbp_info__current_switches)
+{
+	int ret;
+	union ec_response_get_next_data response;
+	struct ec_params_mkbp_info request = {
+		.info_type = EC_MKBP_INFO_CURRENT,
+		.event_type = EC_MKBP_EVENT_SWITCH,
+	};
+
+	ret = ec_cmd_mkbp_info_get_next_data(NULL, &request, &response);
+	zassert_equal(EC_SUCCESS, ret, "Host command failed: %d", ret);
+	zassert_equal(mkbp_get_switch_state(), response.switches, NULL);
+}
+
+ZTEST(mkbp_info, test_host_command_mkbp_info__current_invalid)
+{
+	int ret;
+	union ec_response_get_next_data response;
+	struct ec_params_mkbp_info request = {
+		.info_type = EC_MKBP_INFO_CURRENT,
+		.event_type = EC_MKBP_EVENT_COUNT, /* Unsupported */
+	};
+
+	ret = ec_cmd_mkbp_info_get_next_data(NULL, &request, &response);
+	zassert_equal(EC_RES_INVALID_PARAM, ret, "Host command failed: %d",
+		      ret);
+}
+
+ZTEST(mkbp_info, test_host_command_mkbp_info__invalid)
+{
+	int ret;
+	union ec_response_get_next_data response;
+	struct ec_params_mkbp_info request = {
+		.info_type = -1, /* Unsupported */
+	};
+
+	ret = ec_cmd_mkbp_info_get_next_data(NULL, &request, &response);
+	zassert_equal(EC_RES_ERROR, ret, "Host command failed: %d", ret);
+}
+
+static void reset(void *data)
+{
+	ARG_UNUSED(data);
+
+	/* Release any pressed keys in the emulator */
+	clear_emulated_keys();
+}
+
+ZTEST_SUITE(mkbp_info, drivers_predicate_post_main, NULL, reset, reset, NULL);
diff --git a/zephyr/test/drivers/led_common/CMakeLists.txt b/zephyr/test/drivers/led_common/CMakeLists.txt
new file mode 100644
index 0000000000..9386414deb
--- /dev/null
+++ b/zephyr/test/drivers/led_common/CMakeLists.txt
@@ -0,0 +1,5 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_sources(app PRIVATE src/main.c)
diff --git a/zephyr/test/drivers/led_common/src/main.c b/zephyr/test/drivers/led_common/src/main.c
new file mode 100644
index 0000000000..4a712a3779
--- /dev/null
+++ b/zephyr/test/drivers/led_common/src/main.c
@@ -0,0 +1,31 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "led_common.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/fff.h>
+#include <zephyr/ztest.h>
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+FAKE_VOID_FUNC(led_get_brightness_range, enum ec_led_id, uint8_t *);
+FAKE_VALUE_FUNC(int, led_set_brightness, enum ec_led_id, const uint8_t *);
+
+ZTEST_SUITE(led_common, drivers_predicate_post_main, NULL, NULL, NULL, NULL);
+
+ZTEST(led_common, test_led_is_supported)
+{
+	zassert_true(led_is_supported(EC_LED_ID_BATTERY_LED));
+	zassert_true(led_is_supported(EC_LED_ID_POWER_LED));
+
+	zassert_false(led_is_supported(EC_LED_ID_ADAPTER_LED));
+	zassert_false(led_is_supported(EC_LED_ID_LEFT_LED));
+	zassert_false(led_is_supported(EC_LED_ID_RIGHT_LED));
+	zassert_false(led_is_supported(EC_LED_ID_RECOVERY_HW_REINIT_LED));
+	zassert_false(led_is_supported(EC_LED_ID_SYSRQ_DEBUG_LED));
+}
diff --git a/zephyr/test/drivers/led_driver/CMakeLists.txt b/zephyr/test/drivers/led_driver/CMakeLists.txt
new file mode 100644
index 0000000000..c378d34425
--- /dev/null
+++ b/zephyr/test/drivers/led_driver/CMakeLists.txt
@@ -0,0 +1,13 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Add include paths
+target_include_directories(app PRIVATE
+    "${PLATFORM_EC}/zephyr/shim/src/led_driver")
+
+# Add source files
+target_sources(app PRIVATE
+  src/led_common.c
+  src/led.c
+)
diff --git a/zephyr/test/drivers/led_driver/led_pins.dts b/zephyr/test/drivers/led_driver/led_pins.dts
new file mode 100644
index 0000000000..dc672f56cd
--- /dev/null
+++ b/zephyr/test/drivers/led_driver/led_pins.dts
@@ -0,0 +1,57 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+ /* Based off of `ec/zephyr/program/herobrine/led_pins_herobrine.dts`
+  * Modified led-colors to obtain better test coverage.
+  */
+/ {
+	pwm-led-pins {
+		status = "disabled";
+	};
+
+	gpio-led-pins {
+		compatible = "cros-ec,gpio-led-pins";
+
+		left-led {
+			led-id = "EC_LED_ID_SYSRQ_DEBUG_LED";
+			led-pins = <&gpio_ec_chg_led_y_c1
+				    &gpio_ec_chg_led_w_c1>;
+			color_off_left: color-off-left {
+				led-color = "LED_OFF";
+				led-values = <0 0>;
+			};
+			color_blue_left: color-blue-left {
+				led-color = "LED_BLUE";
+				br-color = "EC_LED_COLOR_BLUE";
+				led-values = <1 0>;
+			};
+			color_white_left: color-white-left {
+				led-color = "LED_WHITE";
+				br-color = "EC_LED_COLOR_WHITE";
+				led-values = <0 1>;
+			};
+		};
+
+		right-led {
+			led-id = "EC_LED_ID_RIGHT_LED";
+			led-pins = <&gpio_ec_chg_led_y_c0
+				    &gpio_ec_chg_led_w_c0>;
+			color_off_right: color-off-right {
+				led-color = "LED_OFF";
+				led-values = <0 0>;
+			};
+			color_blue_right: color-blue-right {
+				led-color = "LED_BLUE";
+				br-color = "EC_LED_COLOR_BLUE";
+				led-values = <1 0>;
+			};
+			color_white_right: color-white-right {
+				led-color = "LED_WHITE";
+				br-color = "EC_LED_COLOR_WHITE";
+				led-values = <0 1>;
+			};
+		};
+	};
+};
diff --git a/zephyr/test/drivers/led_driver/led_policy.dts b/zephyr/test/drivers/led_driver/led_policy.dts
new file mode 100644
index 0000000000..a205e94ded
--- /dev/null
+++ b/zephyr/test/drivers/led_driver/led_policy.dts
@@ -0,0 +1,231 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Based off of `ec/zephyr/program/herobrine/led_policy_herobrine.dts`
+ * Modified led-colors to obtain better test coverage.
+ */
+
+#include <dt-bindings/battery.h>
+
+/ {
+	led-colors {
+		compatible = "cros-ec,led-policy";
+
+		power-state-charge-left {
+			charge-state = "LED_PWRS_CHARGE";
+			charge-port = <1>; /* Left port */
+
+			/* Turn off the right LED */
+			color-0 {
+				led-color = <&color_off_right>;
+			};
+			/* Left LED to Blue */
+			color-1 {
+				led-color = <&color_blue_left>;
+			};
+		};
+
+		power-state-charge-right {
+			charge-state = "LED_PWRS_CHARGE";
+			charge-port = <0>; /* Right port */
+			/* Battery is charging */
+			batt-state-mask = <SB_STATUS_DISCHARGING>;
+			batt-state = <0>;
+
+			/* Turn off the left LED */
+			color-0 {
+				led-color = <&color_off_left>;
+			};
+			/* Right LED to Blue */
+			color-1 {
+				led-color = <&color_blue_right>;
+			};
+		};
+
+		power-state-charge-idle-right {
+			charge-state = "LED_PWRS_CHARGE";
+			charge-port = <0>; /* Right port */
+			/* Battery is discharging */
+			batt-state-mask = <SB_STATUS_DISCHARGING>;
+			batt-state = <SB_STATUS_DISCHARGING>;
+
+			/* Turn off the left LED */
+			color-0 {
+				led-color = <&color_off_left>;
+			};
+			/* Turn off the right LED */
+			color-1 {
+				led-color = <&color_off_right>;
+			};
+		};
+
+		power-state-discharge-right-low {
+			charge-state = "LED_PWRS_DISCHARGE";
+			/* Battery percent range (>= Empty, <= Low) */
+			batt-lvl = <BATTERY_LEVEL_EMPTY BATTERY_LEVEL_LOW>;
+
+			/* Turn off the left LED */
+			color-0 {
+				led-color = <&color_off_left>;
+			};
+			/* Right LED - White 1 sec, off 3 sec */
+			color-1 {
+				led-color = <&color_white_right>;
+				period-ms = <1000>;
+			};
+			color-2 {
+				led-color = <&color_off_right>;
+				period-ms = <3000>;
+			};
+		};
+
+		power-state-discharge-right {
+			charge-state = "LED_PWRS_DISCHARGE";
+			/* Battery percent range (> Low, <= Full) */
+			batt-lvl = <(BATTERY_LEVEL_LOW + 1) BATTERY_LEVEL_FULL>;
+
+			/* Turn off the left LED */
+			color-0 {
+				led-color = <&color_off_left>;
+			};
+			/* Turn off the right LED */
+			color-1 {
+				led-color = <&color_off_right>;
+			};
+		};
+
+		power-state-error-left {
+			charge-state = "LED_PWRS_ERROR";
+			charge-port = <1>; /* Left port */
+
+			/* Turn off the right LED */
+			color-0 {
+				led-color = <&color_off_right>;
+			};
+			/* Left LED - White 2 sec, off 2 sec */
+			color-1 {
+				led-color = <&color_white_left>;
+				period-ms = <2000>;
+			};
+			color-2 {
+				led-color = <&color_off_right>;
+				period-ms = <2000>;
+			};
+		};
+
+		power-state-error-right {
+			charge-state = "LED_PWRS_ERROR";
+			charge-port = <0>; /* Right port */
+
+			/* Turn off the left LED */
+			color-0 {
+				led-color = <&color_off_left>;
+			};
+			/* Right LED - White 2 sec, off 2 sec */
+			color-1 {
+				led-color = <&color_white_right>;
+				period-ms = <2000>;
+			};
+			color-2 {
+				led-color = <&color_off_right>;
+				period-ms = <2000>;
+			};
+		};
+
+		power-state-near-full-left {
+			charge-state = "LED_PWRS_CHARGE_NEAR_FULL";
+			charge-port = <1>; /* Left port */
+
+			/* Turn off the right LED */
+			color-0 {
+				led-color = <&color_off_right>;
+			};
+			/* Left LED to White */
+			color-1 {
+				led-color = <&color_white_left>;
+			};
+		};
+
+		power-state-near-full-right {
+			charge-state = "LED_PWRS_CHARGE_NEAR_FULL";
+			charge-port = <0>; /* Right port */
+
+			/* Turn off the left LED */
+			color-0 {
+				led-color = <&color_off_left>;
+			};
+			/* Right LED to White */
+			color-1 {
+				led-color = <&color_white_right>;
+			};
+		};
+
+		power-state-forced-idle-left {
+			charge-state = "LED_PWRS_FORCED_IDLE";
+			charge-port = <1>; /* Left port */
+
+			/* Turn off the right LED */
+			color-0 {
+				led-color = <&color_off_right>;
+			};
+			/* Left LED - Blue 3 sec, Off 1 sec */
+			color-1 {
+				led-color = <&color_blue_left>;
+				period-ms = <3000>;
+			};
+			color-2 {
+				led-color = <&color_off_left>;
+				period-ms = <1000>;
+			};
+		};
+
+		power-state-forced-idle-right {
+			charge-state = "LED_PWRS_FORCED_IDLE";
+			charge-port = <0>; /* Right port */
+
+			/* Turn off the left LED */
+			color-0 {
+				led-color = <&color_off_left>;
+			};
+			/* Right LED - Blue 3 sec, Off 1 sec */
+			color-1 {
+				led-color = <&color_blue_right>;
+				period-ms = <3000>;
+			};
+			color-2 {
+				led-color = <&color_off_right>;
+				period-ms = <1000>;
+			};
+		};
+
+		power-state-idle-left {
+			charge-state = "LED_PWRS_IDLE";
+			charge-port = <1>; /* Left port */
+
+			/* Turn off the right LED */
+			color-0 {
+				led-color = <&color_off_right>;
+			};
+			/* Left LED to White */
+			color-1 {
+				led-color = <&color_white_left>;
+			};
+		};
+
+		power-state-idle-right {
+			charge-state = "LED_PWRS_IDLE";
+			charge-port = <0>; /* Right port */
+
+			/* Turn off the left LED */
+			color-0 {
+				led-color = <&color_off_left>;
+			};
+			/* Right LED to White */
+			color-1 {
+				led-color = <&color_white_right>;
+			};
+		};
+	};
+};
diff --git a/zephyr/test/drivers/led_driver/prj.conf b/zephyr/test/drivers/led_driver/prj.conf
new file mode 100644
index 0000000000..01bb9df535
--- /dev/null
+++ b/zephyr/test/drivers/led_driver/prj.conf
@@ -0,0 +1,3 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
diff --git a/zephyr/test/drivers/led_driver/src/led.c b/zephyr/test/drivers/led_driver/src/led.c
new file mode 100644
index 0000000000..161ac57213
--- /dev/null
+++ b/zephyr/test/drivers/led_driver/src/led.c
@@ -0,0 +1,171 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery_smart.h"
+#include "ec_commands.h"
+#include "emul/emul_isl923x.h"
+#include "emul/emul_smart_battery.h"
+#include "emul/tcpc/emul_tcpci_partner_src.h"
+#include "gpio.h"
+#include "include/power.h"
+#include "led.h"
+#include "led_common.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "usb_pd.h"
+
+#include <zephyr/ztest.h>
+
+#include <dt-bindings/battery.h>
+
+#define BATTERY_NODE DT_NODELABEL(battery)
+
+#define VERIFY_LED_COLOR(color, led_id)                                    \
+	{                                                                  \
+		const struct led_pins_node_t *pin_node =                   \
+			led_get_node(color, led_id);                       \
+		for (int j = 0; j < pin_node->pins_count; j++) {           \
+			int val = gpio_pin_get_dt(gpio_get_dt_spec(        \
+				pin_node->gpio_pins[j].signal));           \
+			int expecting = pin_node->gpio_pins[j].val;        \
+			zassert_equal(expecting, val, "[%d]: %d != %d", j, \
+				      expecting, val);                     \
+		}                                                          \
+	}
+
+ZTEST(led_driver, test_led_control)
+{
+	test_set_chipset_to_power_level(POWER_S5);
+
+	/* Exercise valid led_id, set to RESET state */
+	led_control(EC_LED_ID_SYSRQ_DEBUG_LED, LED_STATE_RESET);
+	VERIFY_LED_COLOR(LED_OFF, EC_LED_ID_SYSRQ_DEBUG_LED);
+
+	/* Exercise valid led_id, set to OFF state.
+	 * Verify matches OFF color defined in device tree
+	 */
+	led_control(EC_LED_ID_SYSRQ_DEBUG_LED, LED_STATE_OFF);
+	VERIFY_LED_COLOR(LED_OFF, EC_LED_ID_SYSRQ_DEBUG_LED);
+
+	/* Exercise valid led_id, set to ON state.
+	 * Verify matches ON color defined in device tree
+	 */
+	led_control(EC_LED_ID_SYSRQ_DEBUG_LED, LED_STATE_ON);
+	VERIFY_LED_COLOR(LED_BLUE, EC_LED_ID_SYSRQ_DEBUG_LED);
+
+	/* Exercise invalid led_id -- no change to led color */
+	led_control(EC_LED_ID_LEFT_LED, LED_STATE_RESET);
+	VERIFY_LED_COLOR(LED_BLUE, EC_LED_ID_SYSRQ_DEBUG_LED);
+}
+
+ZTEST(led_driver, test_led_brightness)
+{
+	uint8_t brightness[EC_LED_COLOR_COUNT] = { -1 };
+
+	/* Verify LED set to OFF */
+	led_set_brightness(EC_LED_ID_SYSRQ_DEBUG_LED, brightness);
+	VERIFY_LED_COLOR(LED_OFF, EC_LED_ID_SYSRQ_DEBUG_LED);
+
+	/* Verify LED colors defined in device tree are reflected in the
+	 * brightness array.
+	 */
+	led_get_brightness_range(EC_LED_ID_SYSRQ_DEBUG_LED, brightness);
+	zassert_equal(brightness[EC_LED_COLOR_BLUE], 1);
+	zassert_equal(brightness[EC_LED_COLOR_WHITE], 1);
+
+	/* Verify LED set to WHITE */
+	led_set_brightness(EC_LED_ID_SYSRQ_DEBUG_LED, brightness);
+	VERIFY_LED_COLOR(LED_WHITE, EC_LED_ID_SYSRQ_DEBUG_LED);
+}
+
+ZTEST(led_driver, test_get_chipset_state)
+{
+	enum power_state pwr_state;
+
+	test_set_chipset_to_g3();
+	pwr_state = get_chipset_state();
+	zassert_equal(pwr_state, POWER_S5, "expected=%d, returned=%d", POWER_S5,
+		      pwr_state);
+
+	test_set_chipset_to_s0();
+	pwr_state = get_chipset_state();
+	zassert_equal(pwr_state, POWER_S0, "expected=%d, returned=%d", POWER_S0,
+		      pwr_state);
+
+	test_set_chipset_to_power_level(POWER_S3);
+	pwr_state = get_chipset_state();
+	zassert_equal(pwr_state, POWER_S3, "expected=%d, returned=%d", POWER_S3,
+		      pwr_state);
+}
+
+struct led_driver_fixture {
+	struct tcpci_partner_data source_20v_3a;
+	struct tcpci_src_emul_data src_ext;
+	const struct emul *tcpci_emul;
+	const struct emul *charger_emul;
+};
+
+static inline void connect_charger_to_port(struct led_driver_fixture *fixture)
+{
+	set_ac_enabled(true);
+	zassert_ok(tcpci_partner_connect_to_tcpci(&fixture->source_20v_3a,
+						  fixture->tcpci_emul),
+		   NULL);
+	isl923x_emul_set_adc_vbus(fixture->charger_emul,
+				  PDO_FIXED_GET_VOLT(fixture->src_ext.pdo[1]));
+	k_sleep(K_SECONDS(10));
+}
+
+static inline void
+disconnect_charger_from_port(struct led_driver_fixture *fixture)
+{
+	set_ac_enabled(false);
+	zassert_ok(tcpci_emul_disconnect_partner(fixture->tcpci_emul));
+	isl923x_emul_set_adc_vbus(fixture->charger_emul, 0);
+	k_sleep(K_SECONDS(1));
+}
+
+static void *led_driver_setup(void)
+{
+	static struct led_driver_fixture fixture;
+
+	/* Get references for the emulators */
+	fixture.tcpci_emul = EMUL_GET_USBC_BINDING(0, tcpc);
+	fixture.charger_emul = EMUL_GET_USBC_BINDING(0, chg);
+
+	/* Initialized the source to supply 20V and 3A */
+	tcpci_partner_init(&fixture.source_20v_3a, PD_REV20);
+	fixture.source_20v_3a.extensions = tcpci_src_emul_init(
+		&fixture.src_ext, &fixture.source_20v_3a, NULL);
+	fixture.src_ext.pdo[1] =
+		PDO_FIXED(20000, 3000, PDO_FIXED_UNCONSTRAINED);
+
+	return &fixture;
+}
+
+static void led_driver_before(void *data)
+{
+	connect_charger_to_port((struct led_driver_fixture *)data);
+}
+
+static void led_driver_after(void *data)
+{
+	disconnect_charger_from_port((struct led_driver_fixture *)data);
+}
+
+ZTEST_SUITE(led_driver, drivers_predicate_post_main, led_driver_setup,
+	    led_driver_before, led_driver_after, NULL);
+
+ZTEST(led_driver, test_get_battery_state)
+{
+	const struct emul *emul = EMUL_DT_GET(BATTERY_NODE);
+	uint16_t battery_status;
+
+	zassert_ok(sbat_emul_get_word_val(emul, SB_BATTERY_STATUS,
+					  &battery_status),
+		   NULL);
+	zassert_equal(battery_status & SB_STATUS_DISCHARGING, 0,
+		      "Battery is discharging: %d", battery_status);
+}
diff --git a/zephyr/test/drivers/led_driver/src/led_common.c b/zephyr/test/drivers/led_driver/src/led_common.c
new file mode 100644
index 0000000000..d865aba8e0
--- /dev/null
+++ b/zephyr/test/drivers/led_driver/src/led_common.c
@@ -0,0 +1,128 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "host_command.h"
+#include "led_common.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/fff.h>
+#include <zephyr/ztest.h>
+
+ZTEST(led_common, test_host_command__query)
+{
+	/* Gets the brightness range for an LED */
+
+	int ret;
+	struct ec_response_led_control response;
+	struct ec_params_led_control params = {
+		.led_id = EC_LED_ID_RIGHT_LED,
+		.flags = EC_LED_FLAGS_QUERY,
+	};
+
+	/* Expected brightness levels per color channel for this LED */
+	uint8_t expected_brightness_ranges[] = {
+		[EC_LED_COLOR_RED] = 0,	  [EC_LED_COLOR_GREEN] = 0,
+		[EC_LED_COLOR_BLUE] = 1,  [EC_LED_COLOR_YELLOW] = 0,
+		[EC_LED_COLOR_WHITE] = 1, [EC_LED_COLOR_AMBER] = 0,
+	};
+
+	ret = ec_cmd_led_control_v1(NULL, &params, &response);
+
+	zassert_ok(ret, "Host command returned %d", ret);
+	zassert_mem_equal(expected_brightness_ranges, response.brightness_range,
+			  sizeof(expected_brightness_ranges), NULL);
+}
+
+ZTEST(led_common, test_host_command__invalid_led)
+{
+	/* Try accessing info on a non-existent LED */
+
+	int ret;
+	struct ec_response_led_control response;
+	struct ec_params_led_control params = {
+		.led_id = EC_LED_ID_COUNT, /* Non-existent */
+		.flags = EC_LED_FLAGS_QUERY,
+	};
+
+	ret = ec_cmd_led_control_v1(NULL, &params, &response);
+
+	zassert_equal(EC_RES_INVALID_PARAM, ret, "Host command returned %d",
+		      ret);
+}
+
+ZTEST(led_common, test_host_command__supported_channel)
+{
+	/* Try setting brightness on a color channel that is not supported */
+
+	int ret;
+	struct ec_response_led_control response;
+	struct ec_params_led_control params = {
+		.led_id = EC_LED_ID_RIGHT_LED,
+		.flags = 0x00,
+		.brightness = {
+			/* This LED does not have a red channel */
+			[EC_LED_COLOR_RED] = 100,
+		},
+	};
+
+	ret = ec_cmd_led_control_v1(NULL, &params, &response);
+
+	zassert_equal(EC_RES_INVALID_PARAM, ret, "Host command returned %d",
+		      ret);
+}
+
+ZTEST(led_common, test_host_command__manual_control)
+{
+	/* Set brightness for an LED directly */
+
+	int ret;
+	struct ec_response_led_control response;
+	struct ec_params_led_control params = {
+		.led_id = EC_LED_ID_RIGHT_LED,
+		.flags = 0x00,
+		.brightness = {
+			[EC_LED_COLOR_BLUE] = 1,
+			/* All other color channels off */
+		},
+	};
+
+	ret = ec_cmd_led_control_v1(NULL, &params, &response);
+
+	zassert_equal(EC_RES_SUCCESS, ret, "Host command returned %d", ret);
+	zassert_true(
+		gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_chg_led_y_c0)),
+		"LED blue channel is not on");
+	zassert_false(
+		gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_chg_led_w_c0)),
+		"LED white channel is not off");
+}
+
+FAKE_VOID_FUNC(board_led_auto_control);
+
+ZTEST(led_common, test_host_command__auto_control)
+{
+	/* Configure an LED for automatic control */
+
+	int ret;
+	struct ec_response_led_control response;
+	struct ec_params_led_control params = {
+		.led_id = EC_LED_ID_RIGHT_LED,
+		.flags = EC_LED_FLAGS_AUTO,
+	};
+
+	ret = ec_cmd_led_control_v1(NULL, &params, &response);
+
+	zassert_equal(EC_RES_SUCCESS, ret, "Host command returned %d", ret);
+	zassert_equal(1, board_led_auto_control_fake.call_count,
+		      "Did not call auto control function.");
+}
+
+static void reset(void *data)
+{
+	ARG_UNUSED(data);
+
+	RESET_FAKE(board_led_auto_control);
+}
+
+ZTEST_SUITE(led_common, drivers_predicate_post_main, NULL, reset, reset, NULL);
diff --git a/zephyr/test/drivers/locate_chip/CMakeLists.txt b/zephyr/test/drivers/locate_chip/CMakeLists.txt
new file mode 100644
index 0000000000..44ea341f5d
--- /dev/null
+++ b/zephyr/test/drivers/locate_chip/CMakeLists.txt
@@ -0,0 +1,7 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_sources(app PRIVATE
+    src/locate_chip.c
+)
diff --git a/zephyr/test/drivers/locate_chip/src/locate_chip.c b/zephyr/test/drivers/locate_chip/src/locate_chip.c
new file mode 100644
index 0000000000..3cb9a9f3bc
--- /dev/null
+++ b/zephyr/test/drivers/locate_chip/src/locate_chip.c
@@ -0,0 +1,25 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "host_command.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/ztest.h>
+
+ZTEST_SUITE(locate_chip, drivers_predicate_post_main, NULL, NULL, NULL, NULL);
+
+ZTEST_USER(locate_chip, test_invalid_request_for_eeprom)
+{
+	int ret;
+	struct ec_params_locate_chip p = {
+		.type = EC_CHIP_TYPE_CBI_EEPROM,
+	};
+	struct ec_response_locate_chip r;
+
+	ret = ec_cmd_locate_chip(NULL, &p, &r);
+
+	zassert_equal(ret, EC_RES_UNAVAILABLE, "Unexpected return value: %d",
+		      ret);
+}
diff --git a/zephyr/test/drivers/memmap/CMakeLists.txt b/zephyr/test/drivers/memmap/CMakeLists.txt
new file mode 100644
index 0000000000..9386414deb
--- /dev/null
+++ b/zephyr/test/drivers/memmap/CMakeLists.txt
@@ -0,0 +1,5 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_sources(app PRIVATE src/main.c)
diff --git a/zephyr/test/drivers/memmap/src/main.c b/zephyr/test/drivers/memmap/src/main.c
new file mode 100644
index 0000000000..89ea2c52cd
--- /dev/null
+++ b/zephyr/test/drivers/memmap/src/main.c
@@ -0,0 +1,89 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "flash.h"
+#include "host_command.h"
+#include "test/drivers/test_state.h"
+
+#include <stdio.h>
+#include <string.h>
+
+#include <zephyr/ztest.h>
+
+extern const char *flash_physical_dataptr_override;
+
+static char flash[CONFIG_FLASH_SIZE_BYTES];
+
+static void after(void *f)
+{
+	ARG_UNUSED(f);
+	flash_physical_dataptr_override = NULL;
+}
+
+ZTEST_SUITE(memmap, drivers_predicate_post_main, NULL, NULL, after, NULL);
+
+ZTEST(memmap, test_crec_flash_dataptr__invalid)
+{
+	zassert_equal(-1, crec_flash_dataptr(/*offset=*/-1, /*size_req=*/1,
+					     /*align=*/1, /*ptrp=*/NULL));
+}
+
+ZTEST(memmap, test_crec_flash_dataptr)
+{
+	const char *ptr = NULL;
+
+	zassert_equal(CONFIG_PLATFORM_EC_FLASH_SIZE_BYTES,
+		      crec_flash_dataptr(0, 1, 1, &ptr));
+	zassert_equal(CONFIG_PLATFORM_EC_MAPPED_STORAGE_BASE, (uintptr_t)ptr);
+}
+
+ZTEST(memmap, test_crec_flash_is_erased__invalid_args)
+{
+	zassert_equal(0, crec_flash_is_erased(/*offset=*/0, /*size=*/-1));
+}
+
+ZTEST(memmap, test_crec_flash_is_erased__fail)
+{
+	sprintf(flash, "non empty data");
+	flash_physical_dataptr_override = flash;
+	zassert_equal(0, crec_flash_is_erased(/*offset=*/0, /*size=*/8));
+}
+
+ZTEST(memmap, test_crec_flash_is_erased__pass)
+{
+	memset(flash, 0xff, 32);
+	flash_physical_dataptr_override = flash;
+	zassert_equal(1, crec_flash_is_erased(/*offset=*/0, /*size=*/32));
+}
+
+ZTEST(memmap, test_crec_flash_read__invalid_args)
+{
+	zassert_equal(EC_ERROR_INVAL, crec_flash_read(/*offset=*/-1, /*size=*/0,
+						      /*data=*/NULL));
+}
+
+ZTEST(memmap, test_crec_flash_read)
+{
+	char output[16] = { 0 };
+
+	sprintf(flash, "0123456789abcdef");
+	flash_physical_dataptr_override = flash;
+
+	zassert_ok(crec_flash_read(/*offset=*/0, ARRAY_SIZE(output), output));
+	zassert_mem_equal(output, flash, ARRAY_SIZE(output));
+}
+
+ZTEST(memmap, test_crec_flash_write__invalid_args)
+{
+	zassert_equal(EC_ERROR_INVAL,
+		      crec_flash_write(/*offset=*/-1, /*size=*/0,
+				       /*data=*/NULL));
+}
+
+ZTEST(memmap, test_crec_flash_erase__invalid_args)
+{
+	zassert_equal(EC_ERROR_INVAL,
+		      crec_flash_erase(/*offset=*/-1, /*size=*/0));
+}
diff --git a/zephyr/test/drivers/mkbp/CMakeLists.txt b/zephyr/test/drivers/mkbp/CMakeLists.txt
new file mode 100644
index 0000000000..decd3ec0a7
--- /dev/null
+++ b/zephyr/test/drivers/mkbp/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Add source files
+target_sources(app PRIVATE src/mkbp_fifo.c)
diff --git a/zephyr/test/drivers/mkbp/src/mkbp_fifo.c b/zephyr/test/drivers/mkbp/src/mkbp_fifo.c
new file mode 100644
index 0000000000..2991c4ff7f
--- /dev/null
+++ b/zephyr/test/drivers/mkbp/src/mkbp_fifo.c
@@ -0,0 +1,149 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "keyboard_config.h"
+#include "mkbp_fifo.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/i2c_emul.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+#include <zephyr/ztest_assert.h>
+
+/* Tests for Matrix Keyboard Protocol (MKBP) */
+
+/* Largest event size that we support */
+#define KEY_MATRIX_EVENT_DATA_SIZE KEYBOARD_COLS_MAX
+
+#define KEY_HOST_EVENT64_DATA_SIZE sizeof(uint64_t)
+
+#define MAX_EVENT_DATA_SIZE KEY_MATRIX_EVENT_DATA_SIZE
+
+struct mkbp_fifo_fixture {
+	uint8_t input_event_data[MAX_EVENT_DATA_SIZE];
+};
+
+static void *mkbp_fifo_setup(void)
+{
+	static struct mkbp_fifo_fixture fixture;
+
+	return &fixture;
+}
+
+static void mkbp_fifo_before(void *data)
+{
+	struct mkbp_fifo_fixture *fixture = data;
+
+	mkbp_clear_fifo();
+	memset(fixture->input_event_data, 0, MAX_EVENT_DATA_SIZE);
+	mkbp_fifo_depth_update(FIFO_DEPTH);
+}
+
+static void mkbp_fifo_after(void *data)
+{
+	mkbp_clear_fifo();
+	mkbp_fifo_depth_update(FIFO_DEPTH);
+}
+
+static void fill_array_with_incrementing_numbers(int8_t *dst, int size)
+{
+	for (int i = 0; i < size; i++) {
+		dst[i] = i;
+	}
+}
+
+ZTEST_F(mkbp_fifo, test_fifo_add_keyboard_key_matrix_event)
+{
+	uint8_t out[KEY_MATRIX_EVENT_DATA_SIZE + 1];
+
+	memset(out, 0, sizeof(out));
+
+	fill_array_with_incrementing_numbers(fixture->input_event_data,
+					     KEY_MATRIX_EVENT_DATA_SIZE);
+
+	/* Keyboard Key Matrix Event
+	 * Push twice to verify their buffers do not overlap.
+	 */
+	zassert_ok(mkbp_fifo_add(EC_MKBP_EVENT_KEY_MATRIX,
+				 fixture->input_event_data),
+		   NULL);
+	zassert_ok(mkbp_fifo_add(EC_MKBP_EVENT_KEY_MATRIX,
+				 fixture->input_event_data),
+		   NULL);
+
+	int dequeued_data_size =
+		mkbp_fifo_get_next_event(out, EC_MKBP_EVENT_KEY_MATRIX);
+
+	zassert_equal(dequeued_data_size, KEY_MATRIX_EVENT_DATA_SIZE, NULL);
+	zassert_mem_equal(fixture->input_event_data, out,
+			  KEY_MATRIX_EVENT_DATA_SIZE, NULL);
+	zassert_equal(out[KEY_MATRIX_EVENT_DATA_SIZE], 0, NULL);
+}
+
+ZTEST_F(mkbp_fifo, test_fifo_add_unknown_event)
+{
+	uint8_t out[KEY_MATRIX_EVENT_DATA_SIZE + 1];
+
+	memset(out, 0, sizeof(out));
+
+	fill_array_with_incrementing_numbers(fixture->input_event_data,
+					     KEY_MATRIX_EVENT_DATA_SIZE);
+
+	/* Keyboard Key Matrix Event */
+	zassert_ok(mkbp_fifo_add(EC_MKBP_EVENT_COUNT,
+				 fixture->input_event_data),
+		   NULL);
+
+	zassert_equal(mkbp_fifo_get_next_event(out, EC_MKBP_EVENT_COUNT),
+		      -EC_ERROR_UNKNOWN);
+}
+
+ZTEST_F(mkbp_fifo, test_fifo_add_keyboard_host_event64)
+{
+	uint8_t out[KEY_MATRIX_EVENT_DATA_SIZE + 1];
+
+	memset(out, 0, sizeof(out));
+
+	fill_array_with_incrementing_numbers(fixture->input_event_data,
+					     KEY_HOST_EVENT64_DATA_SIZE);
+
+	zassert_ok(mkbp_fifo_add(EC_MKBP_EVENT_HOST_EVENT64,
+				 fixture->input_event_data),
+		   NULL);
+
+	int dequeued_data_size =
+		mkbp_fifo_get_next_event(out, EC_MKBP_EVENT_HOST_EVENT64);
+
+	zassert_equal(dequeued_data_size, KEY_HOST_EVENT64_DATA_SIZE, NULL);
+	zassert_mem_equal(fixture->input_event_data, out,
+			  KEY_HOST_EVENT64_DATA_SIZE, NULL);
+	zassert_equal(out[KEY_HOST_EVENT64_DATA_SIZE], 0, NULL);
+}
+
+ZTEST_F(mkbp_fifo, test_fifo_depth_update)
+{
+	uint8_t out[KEY_MATRIX_EVENT_DATA_SIZE + 1];
+	uint8_t new_depth = 0;
+
+	mkbp_fifo_depth_update(new_depth);
+	fill_array_with_incrementing_numbers(fixture->input_event_data,
+					     MAX_EVENT_DATA_SIZE);
+	zassert_equal(EC_ERROR_OVERFLOW,
+		      mkbp_fifo_add(EC_MKBP_EVENT_KEY_MATRIX,
+				    fixture->input_event_data),
+		      NULL);
+	zassert_equal(-1, /* get_next_event explicitly returns -1 */
+		      mkbp_fifo_get_next_event(out, EC_MKBP_EVENT_KEY_MATRIX),
+		      NULL);
+
+	mkbp_fifo_depth_update(FIFO_DEPTH);
+	zassert_ok(mkbp_fifo_add(EC_MKBP_EVENT_KEY_MATRIX,
+				 fixture->input_event_data),
+		   NULL);
+}
+
+ZTEST_SUITE(mkbp_fifo, drivers_predicate_post_main, mkbp_fifo_setup,
+	    mkbp_fifo_before, mkbp_fifo_after, NULL);
diff --git a/zephyr/test/drivers/mock_panic_output/CMakeLists.txt b/zephyr/test/drivers/mock_panic_output/CMakeLists.txt
new file mode 100644
index 0000000000..2e3b959805
--- /dev/null
+++ b/zephyr/test/drivers/mock_panic_output/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Add source files
+target_sources(app PRIVATE src/test_get_panic_data_write.c)
diff --git a/zephyr/test/drivers/mock_panic_output/src/test_get_panic_data_write.c b/zephyr/test/drivers/mock_panic_output/src/test_get_panic_data_write.c
new file mode 100644
index 0000000000..5d7bcf9010
--- /dev/null
+++ b/zephyr/test/drivers/mock_panic_output/src/test_get_panic_data_write.c
@@ -0,0 +1,18 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "panic.h"
+
+/**
+ * @brief Override for testing. This method simply returns `pdata_ptr` and
+ *        bypasses the usual logic in `common/panic_output.c`
+ *
+ * @return struct panic_data* Pointer to the pdata_ptr object
+ */
+struct panic_data *get_panic_data_write(void)
+{
+	/* Test-only helper method to access `pdata_ptr` in `panic_output.c` */
+	return test_get_panic_data_pointer();
+}
diff --git a/zephyr/test/drivers/nct38xx/CMakeLists.txt b/zephyr/test/drivers/nct38xx/CMakeLists.txt
new file mode 100644
index 0000000000..d14a0f4b28
--- /dev/null
+++ b/zephyr/test/drivers/nct38xx/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Add source files
+target_sources(app PRIVATE src/nct38xx.c)
diff --git a/zephyr/test/drivers/nct38xx/src/nct38xx.c b/zephyr/test/drivers/nct38xx/src/nct38xx.c
new file mode 100644
index 0000000000..107b9a91d5
--- /dev/null
+++ b/zephyr/test/drivers/nct38xx/src/nct38xx.c
@@ -0,0 +1,525 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "common.h"
+#include "driver/tcpm/nct38xx.h"
+#include "driver/tcpm/tcpci.h"
+#include "driver/tcpm/tcpm.h"
+#include "emul/tcpc/emul_nct38xx.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/ztest.h>
+
+#define ALERT_TEST_VAL 0xffff
+
+#define NCT38XX_PORT 0
+#define NCT38XX_EMUL EMUL_DT_GET(DT_NODELABEL(nct38xx_emul))
+
+int nct38xx_tcpm_init(int port);
+int nct38xx_tcpm_set_snk_ctrl(int port, int enable);
+int nct38xx_set_frs_enable(int port, int enable);
+int nct3807_handle_fault(int port, int fault);
+int nct38xx_tcpm_set_cc(int port, int pull);
+
+/* Helper functions to make tests cleaner. */
+static int nct38xx_emul_test_get_reg(int r, uint16_t *val)
+{
+	return nct38xx_emul_get_reg(NCT38XX_EMUL, r, val);
+}
+
+static int nct38xx_emul_test_set_reg(int r, uint16_t val)
+{
+	return nct38xx_emul_set_reg(NCT38XX_EMUL, r, val);
+}
+
+static void nct38xx_test_reset(void *fixture)
+{
+	ARG_UNUSED(fixture);
+
+	nct38xx_reset_notify(NCT38XX_PORT);
+}
+
+ZTEST_SUITE(nct38xx, NULL, NULL, nct38xx_test_reset, NULL, NULL);
+
+/* Validate reading and writing emulator registers. */
+ZTEST(nct38xx, test_emul_registers_rw)
+{
+	int rv;
+	uint8_t expected;
+	uint16_t val;
+
+	/* Check vendor-defined registers. */
+	expected = (uint8_t)(NCT38XX_REG_CTRL_OUT_EN_RESERVED_MASK &
+			     NCT38XX_REG_CTRL_OUT_EN_DEFAULT);
+	expected |= (uint8_t)(~NCT38XX_REG_CTRL_OUT_EN_RESERVED_MASK);
+	rv = nct38xx_emul_test_set_reg(NCT38XX_REG_CTRL_OUT_EN, expected);
+	zassert_ok(rv);
+	rv = nct38xx_emul_test_get_reg(NCT38XX_REG_CTRL_OUT_EN, &val);
+	zassert_equal(val, expected);
+
+	expected = (uint8_t)(NCT38XX_REG_VBC_FAULT_CTL_RESERVED_MASK &
+			     NCT38XX_REG_VBC_FAULT_CTL_DEFAULT);
+	expected |= (uint8_t)(~NCT38XX_REG_VBC_FAULT_CTL_RESERVED_MASK);
+	rv = nct38xx_emul_test_set_reg(NCT38XX_REG_VBC_FAULT_CTL, expected);
+	zassert_ok(rv);
+	rv = nct38xx_emul_test_get_reg(NCT38XX_REG_VBC_FAULT_CTL, &val);
+	zassert_ok(rv);
+	zassert_equal(val, expected);
+
+	/*
+	 * Check that access to general TCPC registers passes through the
+	 * underlying TCPC emulator.
+	 */
+	rv = nct38xx_emul_test_set_reg(TCPC_REG_ALERT, ALERT_TEST_VAL);
+	zassert_ok(rv);
+	rv = nct38xx_emul_test_get_reg(TCPC_REG_ALERT, &val);
+	zassert_ok(rv);
+	zassert_equal(val, ALERT_TEST_VAL);
+}
+
+/* Validate that changing reserved bits fails. */
+ZTEST(nct38xx, test_emul_registers_reserved)
+{
+	int rv;
+	uint8_t expected;
+
+	expected = (uint8_t)(NCT38XX_REG_CTRL_OUT_EN_RESERVED_MASK &
+			     NCT38XX_REG_CTRL_OUT_EN_DEFAULT);
+	expected |= (uint8_t)(~NCT38XX_REG_CTRL_OUT_EN_RESERVED_MASK);
+	rv = nct38xx_emul_test_set_reg(NCT38XX_REG_CTRL_OUT_EN, ~expected);
+	zassert_true(rv);
+
+	expected = (uint8_t)(NCT38XX_REG_VBC_FAULT_CTL_RESERVED_MASK &
+			     NCT38XX_REG_VBC_FAULT_CTL_DEFAULT);
+	expected |= (uint8_t)(~NCT38XX_REG_VBC_FAULT_CTL_RESERVED_MASK);
+	rv = nct38xx_emul_test_set_reg(NCT38XX_REG_VBC_FAULT_CTL, ~expected);
+	zassert_true(rv);
+}
+
+/* Validate the emulator's reset function. */
+ZTEST(nct38xx, test_emul_reset)
+{
+	int rv;
+	uint16_t val;
+
+	/*
+	 * Clear the fault status register then check if the registers reset
+	 * flag is set.
+	 */
+	nct38xx_emul_test_set_reg(TCPC_REG_FAULT_STATUS, 0);
+	nct38xx_emul_reset(NCT38XX_EMUL);
+
+	rv = nct38xx_emul_test_get_reg(TCPC_REG_FAULT_STATUS, &val);
+	zassert_ok(rv);
+	zassert_true(val & TCPC_REG_FAULT_STATUS_ALL_REGS_RESET);
+
+	/* Test vendor-specific registers. */
+	rv = nct38xx_emul_test_get_reg(NCT38XX_REG_CTRL_OUT_EN, &val);
+	zassert_ok(rv);
+	zassert_equal(val, NCT38XX_REG_CTRL_OUT_EN_DEFAULT);
+
+	rv = nct38xx_emul_test_get_reg(NCT38XX_REG_VBC_FAULT_CTL, &val);
+	zassert_ok(rv);
+	zassert_equal(val, NCT38XX_REG_VBC_FAULT_CTL_DEFAULT);
+}
+
+static void validate_init(void)
+{
+	int rv;
+	uint16_t val;
+
+	/* Validate REG_CTRL_OUT_EN flags.*/
+	rv = nct38xx_emul_test_get_reg(NCT38XX_REG_CTRL_OUT_EN, &val);
+	zassert_ok(rv);
+	zassert_true(val & (NCT38XX_REG_CTRL_OUT_EN_SRCEN |
+			    NCT38XX_REG_CTRL_OUT_EN_SNKEN |
+			    NCT38XX_REG_CTRL_OUT_EN_CONNDIREN));
+
+	/* Validate that OVP is disabled. */
+	rv = nct38xx_emul_test_get_reg(TCPC_REG_FAULT_CTRL, &val);
+	zassert_ok(rv);
+	zassert_true(val & TCPC_REG_FAULT_CTRL_VBUS_OVP_FAULT_DIS);
+
+	/* Validate that VBus monitor is enabled and FRS is disabled. */
+	rv = nct38xx_emul_test_get_reg(TCPC_REG_POWER_CTRL, &val);
+	zassert_ok(rv);
+	zassert_false(val & (TCPC_REG_POWER_CTRL_VBUS_VOL_MONITOR_DIS |
+			     TCPC_REG_POWER_CTRL_FRS_ENABLE));
+
+	/* Validate FRS direction. */
+	rv = nct38xx_emul_test_get_reg(TCPC_REG_CONFIG_EXT_1, &val);
+	zassert_ok(rv);
+	zassert_equal(val, TCPC_REG_CONFIG_EXT_1_FR_SWAP_SNK_DIR);
+
+	/* Validate alert config. */
+	rv = nct38xx_emul_test_get_reg(TCPC_REG_ALERT_MASK, &val);
+	zassert_ok(rv);
+	zassert_true(val & TCPC_REG_ALERT_FAULT);
+
+	/* Validate VBC_FAULT_CTL flags. */
+	rv = nct38xx_emul_test_get_reg(NCT38XX_REG_VBC_FAULT_CTL, &val);
+	zassert_ok(rv);
+	zassert_true(val & (NCT38XX_REG_VBC_FAULT_CTL_VC_OCP_EN |
+			    NCT38XX_REG_VBC_FAULT_CTL_VC_SCP_EN |
+			    NCT38XX_REG_VBC_FAULT_CTL_FAULT_VC_OFF));
+}
+
+/* Tests nct38xx_tcpm_init from a non-dead battery. */
+ZTEST(nct38xx, test_init)
+{
+	int rv;
+	uint16_t val;
+
+	rv = nct38xx_emul_test_set_reg(TCPC_REG_ROLE_CTRL,
+				       NCT38XX_ROLE_CTRL_GOOD_BATTERY);
+	zassert_ok(rv);
+
+	rv = nct38xx_tcpm_init(NCT38XX_PORT);
+	zassert_ok(rv);
+	zassert_equal(nct38xx_get_boot_type(NCT38XX_PORT), NCT38XX_BOOT_NORMAL);
+
+	/*
+	 * TCPC_CONTROL.DebugAccessoryControl should be enabled after a normal
+	 * boot.
+	 */
+	rv = nct38xx_emul_test_get_reg(TCPC_REG_TCPC_CTRL, &val);
+	zassert_ok(rv);
+	zassert_true(val & TCPC_REG_TCPC_CTRL_DEBUG_ACC_CONTROL);
+
+	validate_init();
+}
+
+/* Tests nct38xx_tcpm_init from a dead battery with a debug accessory. */
+ZTEST(nct38xx, test_dead_init_accessory)
+{
+	int rv;
+	uint16_t val;
+
+	/*
+	 * TCPC_CONTROL.DebugAccessoryControl should stay enabled after a dead
+	 * battery boot.
+	 */
+	rv = nct38xx_emul_test_set_reg(TCPC_REG_ROLE_CTRL,
+				       NCT38XX_ROLE_CTRL_DEAD_BATTERY);
+	zassert_ok(rv);
+
+	rv = nct38xx_tcpm_init(NCT38XX_PORT);
+	zassert_ok(rv);
+	zassert_equal(nct38xx_get_boot_type(NCT38XX_PORT),
+		      NCT38XX_BOOT_DEAD_BATTERY);
+
+	rv = nct38xx_emul_test_get_reg(TCPC_REG_TCPC_CTRL, &val);
+	zassert_ok(rv);
+	zassert_true(val & TCPC_REG_TCPC_CTRL_DEBUG_ACC_CONTROL);
+
+	validate_init();
+}
+
+/* Tests nct38xx_tcpm_init from a dead battery without a debug accessory. */
+ZTEST(nct38xx, test_dead_init_no_accessory)
+{
+	int rv;
+	uint16_t val;
+
+	/*
+	 * TCPC_CONTROL.DebugAccessoryControl should be enabled after a dead
+	 * battery boot if it wasn't.
+	 */
+	rv = nct38xx_emul_test_set_reg(TCPC_REG_ROLE_CTRL,
+				       NCT38XX_ROLE_CTRL_DEAD_BATTERY);
+	zassert_ok(rv);
+
+	rv = nct38xx_emul_test_set_reg(TCPC_REG_TCPC_CTRL, &val);
+	zassert_ok(rv);
+	rv = nct38xx_emul_test_set_reg(
+		TCPC_REG_TCPC_CTRL,
+		val & ~TCPC_REG_TCPC_CTRL_DEBUG_ACC_CONTROL);
+	zassert_ok(rv);
+
+	rv = nct38xx_tcpm_init(NCT38XX_PORT);
+	zassert_ok(rv);
+	zassert_equal(nct38xx_get_boot_type(NCT38XX_PORT),
+		      NCT38XX_BOOT_DEAD_BATTERY);
+
+	rv = nct38xx_emul_test_get_reg(TCPC_REG_TCPC_CTRL, &val);
+	zassert_ok(rv);
+	zassert_true(val & TCPC_REG_TCPC_CTRL_DEBUG_ACC_CONTROL);
+
+	validate_init();
+}
+
+/* Test nct38xx_reset_notify. */
+ZTEST(nct38xx, test_reset_notify)
+{
+	int rv;
+
+	rv = nct38xx_tcpm_init(NCT38XX_PORT);
+	zassert_ok(rv);
+
+	nct38xx_reset_notify(NCT38XX_PORT);
+	zassert_equal(nct38xx_get_boot_type(NCT38XX_PORT),
+		      NCT38XX_BOOT_UNKNOWN);
+}
+
+/* Test nct38xx_tcpm_set_snk_ctrl. */
+ZTEST(nct38xx, test_tcpm_set_snk_ctrl)
+{
+	int rv;
+	uint16_t val;
+
+	rv = nct38xx_tcpm_init(NCT38XX_PORT);
+	zassert_ok(rv);
+
+	/* Validate disable */
+	rv = nct38xx_tcpm_set_snk_ctrl(NCT38XX_PORT, 0);
+	zassert_ok(rv);
+	rv = nct38xx_emul_test_get_reg(NCT38XX_REG_CTRL_OUT_EN, &val);
+	zassert_ok(rv);
+	zassert_true(val & NCT38XX_REG_CTRL_OUT_EN_SNKEN);
+	zassert_false(tcpci_tcpm_get_snk_ctrl(NCT38XX_PORT));
+
+	/* Enable shouldn't change the SNKEN bit. Check with bit cleared. */
+	rv = nct38xx_emul_test_get_reg(NCT38XX_REG_CTRL_OUT_EN, &val);
+	zassert_ok(rv);
+	rv = nct38xx_emul_test_set_reg(NCT38XX_REG_CTRL_OUT_EN,
+				       val | NCT38XX_REG_CTRL_OUT_EN_SNKEN);
+	zassert_ok(rv);
+
+	rv = nct38xx_tcpm_set_snk_ctrl(NCT38XX_PORT, 1);
+	zassert_ok(rv);
+	rv = nct38xx_emul_test_get_reg(NCT38XX_REG_CTRL_OUT_EN, &val);
+	zassert_ok(rv);
+	zassert_true(val & NCT38XX_REG_CTRL_OUT_EN_SNKEN);
+	zassert_true(tcpci_tcpm_get_snk_ctrl(NCT38XX_PORT));
+
+	/* Verify that the SNKEN bit doesn't get cleared. */
+	rv = nct38xx_tcpm_set_snk_ctrl(NCT38XX_PORT, 1);
+	zassert_ok(rv);
+	rv = nct38xx_emul_test_get_reg(NCT38XX_REG_CTRL_OUT_EN, &val);
+	zassert_ok(rv);
+	zassert_true(val & NCT38XX_REG_CTRL_OUT_EN_SNKEN);
+	zassert_true(tcpci_tcpm_get_snk_ctrl(NCT38XX_PORT));
+}
+
+/* Test nct38xx_tcpm_set_cc. */
+ZTEST(nct38xx, test_tcpm_set_cc)
+{
+	int rv;
+	uint16_t val;
+
+	/*
+	 * Test with sinking enabled. Only TYPEC_CC_OPEN should result in
+	 * snken being disabled
+	 */
+	rv = nct38xx_emul_test_get_reg(TCPC_REG_POWER_STATUS, &val);
+	zassert_ok(rv);
+	rv = nct38xx_emul_test_set_reg(
+		TCPC_REG_POWER_STATUS,
+		val | TCPC_REG_POWER_STATUS_SINKING_VBUS);
+	zassert_ok(rv);
+
+	/* Test that tcpci_tcpm_set_cc is being called. */
+	/* CC Open */
+	rv = nct38xx_tcpm_set_cc(NCT38XX_PORT, TYPEC_CC_OPEN);
+	zassert_ok(rv);
+	rv = nct38xx_emul_test_get_reg(NCT38XX_REG_CTRL_OUT_EN, &val);
+	zassert_ok(rv);
+	zassert_false(val & NCT38XX_REG_CTRL_OUT_EN_SNKEN);
+
+	rv = nct38xx_emul_test_get_reg(TCPC_REG_ROLE_CTRL, &val);
+	zassert_ok(rv);
+	zassert_equal(TCPC_REG_ROLE_CTRL_CC1(val), TYPEC_CC_OPEN);
+	zassert_equal(TCPC_REG_ROLE_CTRL_CC2(val), TYPEC_CC_OPEN);
+
+	/* CC RA */
+	rv = nct38xx_tcpm_set_cc(NCT38XX_PORT, TYPEC_CC_RA);
+	zassert_ok(rv);
+	rv = nct38xx_emul_test_get_reg(NCT38XX_REG_CTRL_OUT_EN, &val);
+	zassert_ok(rv);
+	zassert_true(val & NCT38XX_REG_CTRL_OUT_EN_SNKEN);
+
+	rv = nct38xx_emul_test_get_reg(TCPC_REG_ROLE_CTRL, &val);
+	zassert_ok(rv);
+	zassert_equal(TCPC_REG_ROLE_CTRL_CC1(val), TYPEC_CC_RA);
+	zassert_equal(TCPC_REG_ROLE_CTRL_CC2(val), TYPEC_CC_RA);
+
+	/* CC RP */
+	rv = nct38xx_tcpm_set_cc(NCT38XX_PORT, TYPEC_CC_RP);
+	zassert_ok(rv);
+	rv = nct38xx_emul_test_get_reg(NCT38XX_REG_CTRL_OUT_EN, &val);
+	zassert_ok(rv);
+	zassert_true(val & NCT38XX_REG_CTRL_OUT_EN_SNKEN);
+
+	rv = nct38xx_emul_test_get_reg(TCPC_REG_ROLE_CTRL, &val);
+	zassert_ok(rv);
+	zassert_equal(TCPC_REG_ROLE_CTRL_CC1(val), TYPEC_CC_RP);
+	zassert_equal(TCPC_REG_ROLE_CTRL_CC2(val), TYPEC_CC_RP);
+
+	/* CC RD */
+	rv = nct38xx_tcpm_set_cc(NCT38XX_PORT, TYPEC_CC_RD);
+	zassert_ok(rv);
+	rv = nct38xx_emul_test_get_reg(NCT38XX_REG_CTRL_OUT_EN, &val);
+	zassert_ok(rv);
+	zassert_true(val & NCT38XX_REG_CTRL_OUT_EN_SNKEN);
+
+	rv = nct38xx_emul_test_get_reg(TCPC_REG_ROLE_CTRL, &val);
+	zassert_ok(rv);
+	zassert_equal(TCPC_REG_ROLE_CTRL_CC1(val), TYPEC_CC_RD);
+	zassert_equal(TCPC_REG_ROLE_CTRL_CC2(val), TYPEC_CC_RD);
+
+	/* CC RA RD */
+	rv = nct38xx_tcpm_set_cc(NCT38XX_PORT, TYPEC_CC_RA_RD);
+	zassert_ok(rv);
+	rv = nct38xx_emul_test_get_reg(NCT38XX_REG_CTRL_OUT_EN, &val);
+	zassert_ok(rv);
+	zassert_true(val & NCT38XX_REG_CTRL_OUT_EN_SNKEN);
+
+	rv = nct38xx_emul_test_get_reg(TCPC_REG_ROLE_CTRL, &val);
+	zassert_ok(rv);
+	zassert_equal(TCPC_REG_ROLE_CTRL_CC1(val), TYPEC_CC_RA);
+	zassert_equal(TCPC_REG_ROLE_CTRL_CC2(val), TYPEC_CC_RA);
+
+	/*
+	 * Test with sinking disabled. NCT38XX_REG_CTRL_OUT_EN_SNKEN
+	 * should always be set.
+	 */
+	rv = nct38xx_emul_test_get_reg(TCPC_REG_POWER_STATUS, &val);
+	zassert_ok(rv);
+	rv = nct38xx_emul_test_set_reg(
+		TCPC_REG_POWER_STATUS,
+		val & ~TCPC_REG_POWER_STATUS_SINKING_VBUS);
+	zassert_ok(rv);
+
+	/* Test that tcpci_tcpm_set_cc is being called. */
+	/* CC Open */
+	rv = nct38xx_tcpm_set_cc(NCT38XX_PORT, TYPEC_CC_OPEN);
+	zassert_ok(rv);
+	rv = nct38xx_emul_test_get_reg(NCT38XX_REG_CTRL_OUT_EN, &val);
+	zassert_ok(rv);
+	zassert_true(val & NCT38XX_REG_CTRL_OUT_EN_SNKEN);
+
+	rv = nct38xx_emul_test_get_reg(TCPC_REG_ROLE_CTRL, &val);
+	zassert_ok(rv);
+	zassert_equal(TCPC_REG_ROLE_CTRL_CC1(val), TYPEC_CC_OPEN);
+	zassert_equal(TCPC_REG_ROLE_CTRL_CC2(val), TYPEC_CC_OPEN);
+
+	/* CC RA */
+	rv = nct38xx_tcpm_set_cc(NCT38XX_PORT, TYPEC_CC_RA);
+	zassert_ok(rv);
+	rv = nct38xx_emul_test_get_reg(NCT38XX_REG_CTRL_OUT_EN, &val);
+	zassert_ok(rv);
+	zassert_true(val & NCT38XX_REG_CTRL_OUT_EN_SNKEN);
+
+	zassert_equal(TCPC_REG_ROLE_CTRL_CC1(val), TYPEC_CC_RA);
+	zassert_equal(TCPC_REG_ROLE_CTRL_CC2(val), TYPEC_CC_RP);
+
+	/* CC RP */
+	rv = nct38xx_tcpm_set_cc(NCT38XX_PORT, TYPEC_CC_RP);
+	zassert_ok(rv);
+	rv = nct38xx_emul_test_get_reg(NCT38XX_REG_CTRL_OUT_EN, &val);
+	zassert_ok(rv);
+	zassert_true(val & NCT38XX_REG_CTRL_OUT_EN_SNKEN);
+
+	zassert_equal(TCPC_REG_ROLE_CTRL_CC1(val), TYPEC_CC_RA);
+	zassert_equal(TCPC_REG_ROLE_CTRL_CC2(val), TYPEC_CC_RP);
+
+	/* CC RD */
+	rv = nct38xx_tcpm_set_cc(NCT38XX_PORT, TYPEC_CC_RD);
+	zassert_ok(rv);
+	rv = nct38xx_emul_test_get_reg(NCT38XX_REG_CTRL_OUT_EN, &val);
+	zassert_ok(rv);
+	zassert_true(val & NCT38XX_REG_CTRL_OUT_EN_SNKEN);
+
+	/* CC RA RD */
+	rv = nct38xx_tcpm_set_cc(NCT38XX_PORT, TYPEC_CC_RA_RD);
+	zassert_ok(rv);
+	rv = nct38xx_emul_test_get_reg(NCT38XX_REG_CTRL_OUT_EN, &val);
+	zassert_ok(rv);
+	zassert_true(val & NCT38XX_REG_CTRL_OUT_EN_SNKEN);
+
+	zassert_equal(TCPC_REG_ROLE_CTRL_CC1(val), TYPEC_CC_RA);
+	zassert_equal(TCPC_REG_ROLE_CTRL_CC2(val), TYPEC_CC_RP);
+}
+
+/* Test nct38xx_set_frs_enable. */
+ZTEST(nct38xx, test_set_frs_enable)
+{
+	int rv;
+	uint16_t val;
+
+	rv = nct38xx_tcpm_init(NCT38XX_PORT);
+	zassert_ok(rv);
+
+	/* Test disable */
+	rv = nct38xx_set_frs_enable(NCT38XX_PORT, 0);
+	zassert_ok(rv);
+
+	rv = nct38xx_emul_test_get_reg(TCPC_REG_VBUS_SINK_DISCONNECT_THRESH,
+				       &val);
+	zassert_ok(rv);
+	zassert_equal(val, TCPC_REG_VBUS_SINK_DISCONNECT_THRESH_DEFAULT);
+
+	rv = nct38xx_emul_test_get_reg(TCPC_REG_POWER_CTRL, &val);
+	zassert_ok(rv);
+	zassert_false(val & TCPC_REG_POWER_CTRL_FRS_ENABLE);
+
+	/* Test enable */
+	rv = nct38xx_set_frs_enable(NCT38XX_PORT, 1);
+	zassert_ok(rv);
+
+	rv = nct38xx_emul_test_get_reg(TCPC_REG_VBUS_SINK_DISCONNECT_THRESH,
+				       &val);
+	zassert_ok(rv);
+	zassert_equal(val, 0);
+
+	rv = nct38xx_emul_test_get_reg(TCPC_REG_POWER_CTRL, &val);
+	zassert_ok(rv);
+	zassert_true(val & TCPC_REG_POWER_CTRL_FRS_ENABLE);
+}
+
+ZTEST(nct38xx, test_nct3807_handle_fault)
+{
+	uint16_t val;
+	int rv;
+
+	/* Verify that the nct38xx init function gets called. */
+	rv = nct3807_handle_fault(NCT38XX_PORT,
+				  TCPC_REG_FAULT_STATUS_ALL_REGS_RESET);
+	zassert_ok(rv);
+	validate_init();
+
+	/* Verify that OVP gets disabled. */
+	rv = nct38xx_emul_test_get_reg(TCPC_REG_FAULT_CTRL, &val);
+	zassert_ok(rv);
+	rv = nct38xx_emul_test_set_reg(
+		TCPC_REG_FAULT_CTRL,
+		val & ~TCPC_REG_FAULT_CTRL_VBUS_OVP_FAULT_DIS);
+	zassert_ok(rv);
+
+	rv = nct3807_handle_fault(NCT38XX_PORT,
+				  TCPC_REG_FAULT_STATUS_VBUS_OVER_VOLTAGE);
+	zassert_ok(rv);
+
+	rv = nct38xx_emul_test_get_reg(TCPC_REG_FAULT_CTRL, &val);
+	zassert_ok(rv);
+	zassert_true(val & TCPC_REG_FAULT_CTRL_VBUS_OVP_FAULT_DIS);
+
+	/* Test auto discharge failure. */
+	rv = nct38xx_emul_test_get_reg(
+		TCPC_REG_POWER_CTRL_AUTO_DISCHARGE_DISCONNECT, &val);
+	zassert_ok(rv);
+	rv = nct38xx_emul_test_set_reg(
+		TCPC_REG_FAULT_CTRL,
+		val & TCPC_REG_POWER_CTRL_AUTO_DISCHARGE_DISCONNECT);
+	zassert_ok(rv);
+
+	rv = nct3807_handle_fault(NCT38XX_PORT,
+				  TCPC_REG_FAULT_STATUS_AUTO_DISCHARGE_FAIL);
+	zassert_ok(rv);
+
+	rv = nct38xx_emul_test_get_reg(TCPC_REG_POWER_CTRL, &val);
+	zassert_ok(rv);
+	zassert_false(val & TCPC_REG_POWER_CTRL_AUTO_DISCHARGE_DISCONNECT);
+}
diff --git a/zephyr/test/drivers/nct38xx/tcpc_policy.dts b/zephyr/test/drivers/nct38xx/tcpc_policy.dts
new file mode 100644
index 0000000000..861deb566c
--- /dev/null
+++ b/zephyr/test/drivers/nct38xx/tcpc_policy.dts
@@ -0,0 +1,30 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/usb_pd_tcpm.h>
+
+/ {
+	usbc {
+		port0@0 {
+			compatible = "named-usbc-port";
+			tcpc = <&nct38xx_emul>;
+		};
+	};
+};
+
+&i2c3 {
+	status="okay";
+
+	nct38xx_emul: nct38xx_emul@e0 {
+		compatible = "nuvoton,nct38xx";
+		reg = <0xe0>;
+		tcpc-flags = <(
+			TCPC_FLAGS_VBUS_MONITOR |
+			TCPC_FLAGS_ALERT_OD |
+			TCPC_FLAGS_CONTROL_VCONN |
+			TCPC_FLAGS_CONTROL_FRS)>;
+	};
+};
+
diff --git a/zephyr/test/drivers/nx20p348x/CMakeLists.txt b/zephyr/test/drivers/nx20p348x/CMakeLists.txt
new file mode 100644
index 0000000000..b2c202bd5b
--- /dev/null
+++ b/zephyr/test/drivers/nx20p348x/CMakeLists.txt
@@ -0,0 +1,9 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_include_directories(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/include)
+
+target_sources(app PRIVATE src/nx20p348x.c)
+target_sources_ifdef(CONFIG_PLATFORM_EC_USBC_PPC_NX20P3481 app PRIVATE src/nx20p3481.c)
+target_sources_ifdef(CONFIG_PLATFORM_EC_USBC_PPC_NX20P3483 app PRIVATE src/nx20p3483.c)
diff --git a/zephyr/test/drivers/nx20p348x/include/nx20p348x_test_shared.h b/zephyr/test/drivers/nx20p348x/include/nx20p348x_test_shared.h
new file mode 100644
index 0000000000..633dd2e700
--- /dev/null
+++ b/zephyr/test/drivers/nx20p348x/include/nx20p348x_test_shared.h
@@ -0,0 +1,17 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef ZEPHYR_TEST_DRIVERS_NX20_348X_TEST_SHARED_H_
+#define ZEPHYR_TEST_DRIVERS_NX20_348X_TEST_SHARED_H_
+
+#include "emul/emul_nx20p348x.h"
+
+#define TEST_PORT USBC_PORT_C0
+
+struct nx20p348x_driver_fixture {
+	const struct emul *nx20p348x_emul;
+};
+
+#endif /* ZEPHYR_TEST_DRIVERS_NX20_348X_TEST_SHARED_H_ */
diff --git a/zephyr/test/drivers/nx20p348x/src/nx20p3481.c b/zephyr/test/drivers/nx20p348x/src/nx20p3481.c
new file mode 100644
index 0000000000..0897c3e8d1
--- /dev/null
+++ b/zephyr/test/drivers/nx20p348x/src/nx20p3481.c
@@ -0,0 +1,49 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/ppc/nx20p348x.h"
+#include "nx20p348x_test_shared.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "usbc_ppc.h"
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/shell/shell_dummy.h>
+#include <zephyr/ztest.h>
+
+ZTEST_F(nx20p348x_driver, test_sink_enable)
+{
+	uint8_t reg;
+
+	zassert_ok(ppc_vbus_sink_enable(TEST_PORT, true));
+	reg = nx20p348x_emul_peek(fixture->nx20p348x_emul,
+				  NX20P348X_SWITCH_CONTROL_REG);
+	zassert_equal(reg & NX20P3481_SWITCH_CONTROL_HVSNK,
+		      NX20P3481_SWITCH_CONTROL_HVSNK);
+
+	zassert_ok(ppc_vbus_sink_enable(TEST_PORT, false));
+	reg = nx20p348x_emul_peek(fixture->nx20p348x_emul,
+				  NX20P348X_SWITCH_CONTROL_REG);
+	zassert_not_equal(reg & NX20P3481_SWITCH_CONTROL_HVSNK,
+			  NX20P3481_SWITCH_CONTROL_HVSNK);
+}
+
+ZTEST_F(nx20p348x_driver, test_source_enable)
+{
+	uint8_t reg;
+
+	zassert_ok(ppc_vbus_source_enable(TEST_PORT, true));
+	reg = nx20p348x_emul_peek(fixture->nx20p348x_emul,
+				  NX20P348X_SWITCH_CONTROL_REG);
+	zassert_equal(reg & NX20P3481_SWITCH_CONTROL_5VSRC,
+		      NX20P3481_SWITCH_CONTROL_5VSRC);
+
+	zassert_ok(ppc_vbus_source_enable(TEST_PORT, false));
+	reg = nx20p348x_emul_peek(fixture->nx20p348x_emul,
+				  NX20P348X_SWITCH_CONTROL_REG);
+	zassert_not_equal(reg & NX20P3481_SWITCH_CONTROL_5VSRC,
+			  NX20P3481_SWITCH_CONTROL_5VSRC);
+}
diff --git a/zephyr/test/drivers/nx20p348x/src/nx20p3483.c b/zephyr/test/drivers/nx20p348x/src/nx20p3483.c
new file mode 100644
index 0000000000..225fd1c04c
--- /dev/null
+++ b/zephyr/test/drivers/nx20p348x/src/nx20p3483.c
@@ -0,0 +1,45 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "nx20p348x_test_shared.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "usbc_ppc.h"
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/shell/shell_dummy.h>
+#include <zephyr/ztest.h>
+
+ZTEST(nx20p348x_driver, test_sink_enable_success)
+{
+	/* Note: PPC requires a TCPC GPIO to enable its sinking.
+	 * We check if the TCPC's POWER_STATUS is set properly.
+	 */
+	zassert_equal(ppc_vbus_sink_enable(TEST_PORT, true), EC_SUCCESS);
+}
+
+ZTEST(nx20p348x_driver, test_source_enable_success)
+{
+	/* Note: PPC requires a TCPC GPIO to enable its sinking.
+	 * We check if the TCPC's POWER_STATUS is set properly.
+	 */
+	zassert_equal(ppc_vbus_source_enable(TEST_PORT, true), EC_SUCCESS);
+}
+
+ZTEST_F(nx20p348x_driver, test_sink_enable_timeout_failure)
+{
+	nx20p348x_emul_set_tcpc_interact(fixture->nx20p348x_emul, false);
+	/* Note: PPC requires a TCPC GPIO to enable its sinking */
+	zassert_equal(ppc_vbus_sink_enable(TEST_PORT, true), EC_ERROR_TIMEOUT);
+}
+
+ZTEST_F(nx20p348x_driver, test_source_enable_timeout_failure)
+{
+	nx20p348x_emul_set_tcpc_interact(fixture->nx20p348x_emul, false);
+	/* Note: PPC requires a TCPC GPIO to enable its sourcing */
+	zassert_equal(ppc_vbus_source_enable(TEST_PORT, true),
+		      EC_ERROR_TIMEOUT);
+}
diff --git a/zephyr/test/drivers/nx20p348x/src/nx20p348x.c b/zephyr/test/drivers/nx20p348x/src/nx20p348x.c
new file mode 100644
index 0000000000..5ec7ba5ae1
--- /dev/null
+++ b/zephyr/test/drivers/nx20p348x/src/nx20p348x.c
@@ -0,0 +1,227 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery_smart.h"
+#include "charger.h"
+#include "console.h"
+#include "driver/ppc/nx20p348x.h"
+#include "driver/ppc/nx20p348x_public.h"
+#include "nx20p348x_test_shared.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "usb_pd_tcpm.h"
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/shell/shell_dummy.h>
+#include <zephyr/ztest.h>
+
+#define NX20P383X_NODE DT_NODELABEL(nx20p348x_emul)
+
+static void *nx20p348x_driver_setup(void)
+{
+	static struct nx20p348x_driver_fixture fix;
+
+	fix.nx20p348x_emul = EMUL_DT_GET(NX20P383X_NODE);
+
+	return &fix;
+}
+
+ZTEST_SUITE(nx20p348x_driver, drivers_predicate_post_main,
+	    nx20p348x_driver_setup, NULL, NULL, NULL);
+
+struct curr_limit_pair {
+	enum tcpc_rp_value rp;
+	uint8_t reg;
+};
+
+/* Note: Register values are slightly higher to account for overshoot */
+static struct curr_limit_pair currents[] = {
+	{ .rp = TYPEC_RP_3A0, .reg = NX20P348X_ILIM_3_200 },
+	{ .rp = TYPEC_RP_1A5, .reg = NX20P348X_ILIM_1_600 },
+	{ .rp = TYPEC_RP_USB, .reg = NX20P348X_ILIM_0_600 },
+};
+
+ZTEST_F(nx20p348x_driver, test_source_curr_limits)
+{
+	for (int i = 0; i < ARRAY_SIZE(currents); i++) {
+		uint8_t read;
+
+		ppc_set_vbus_source_current_limit(TEST_PORT, currents[i].rp);
+		read = nx20p348x_emul_peek(fixture->nx20p348x_emul,
+					   NX20P348X_5V_SRC_OCP_THRESHOLD_REG);
+		zassert_equal(
+			(read & NX20P348X_ILIM_MASK), currents[i].reg,
+			"Failed to see correct threshold for Rp %d (reg: 0x%02x)",
+			currents[i].rp, read);
+	}
+}
+
+ZTEST_F(nx20p348x_driver, test_discharge_vbus)
+{
+	uint8_t reg;
+
+	zassert_ok(ppc_discharge_vbus(TEST_PORT, true));
+	reg = nx20p348x_emul_peek(fixture->nx20p348x_emul,
+				  NX20P348X_DEVICE_CONTROL_REG);
+	zassert_equal((reg & NX20P348X_CTRL_VBUSDIS_EN),
+		      NX20P348X_CTRL_VBUSDIS_EN);
+
+	zassert_ok(ppc_discharge_vbus(TEST_PORT, false));
+	reg = nx20p348x_emul_peek(fixture->nx20p348x_emul,
+				  NX20P348X_DEVICE_CONTROL_REG);
+	zassert_not_equal((reg & NX20P348X_CTRL_VBUSDIS_EN),
+			  NX20P348X_CTRL_VBUSDIS_EN);
+}
+
+ZTEST(nx20p348x_driver, test_ppc_dump)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+	const char *outbuffer;
+	size_t buffer_size;
+
+	shell_backend_dummy_clear_output(shell_zephyr);
+
+	/* This chip supports PPC dump, so should return success */
+	zassert_ok(shell_execute_cmd(shell_zephyr, "ppc_dump 0"));
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+
+	zassert_true(buffer_size > 0);
+
+	/* Weakly verify something reasonable was output to console */
+	zassert_not_null(strstr(outbuffer, "]: 0x"));
+}
+
+ZTEST_F(nx20p348x_driver, test_db_exit_err)
+{
+	uint8_t reg;
+
+	/* Test an error to exit dead battery mode */
+	nx20p348x_emul_set_interrupt1(fixture->nx20p348x_emul,
+				      NX20P348X_INT1_DBEXIT_ERR);
+
+	/* Give the interrupt time to process */
+	k_sleep(K_MSEC(500));
+
+	/* Interrupt should have set DB exit in the control register */
+	reg = nx20p348x_emul_peek(fixture->nx20p348x_emul,
+				  NX20P348X_DEVICE_CONTROL_REG);
+	zassert_equal((reg & NX20P348X_CTRL_DB_EXIT), NX20P348X_CTRL_DB_EXIT);
+}
+
+ZTEST_F(nx20p348x_driver, test_db_exit_err_max)
+{
+	uint8_t reg;
+
+	/* Set a DB exit error 10 times */
+	for (int i = 0; i < 10; i++) {
+		nx20p348x_emul_set_interrupt1(fixture->nx20p348x_emul,
+					      NX20P348X_INT1_DBEXIT_ERR);
+		k_sleep(K_MSEC(500));
+	}
+
+	/* Interrupt should now be masked by the driver */
+	reg = nx20p348x_emul_peek(fixture->nx20p348x_emul,
+				  NX20P348X_INTERRUPT1_MASK_REG);
+	zassert_equal((reg & NX20P348X_INT1_DBEXIT_ERR),
+		      NX20P348X_INT1_DBEXIT_ERR);
+}
+
+/* Add filler in case of event data */
+#define MAX_RESPONSE_PD_LOG_ENTRY_SIZE (sizeof(struct ec_response_pd_log) + 16)
+
+static void flush_pd_log(void)
+{
+	uint8_t response_buffer[MAX_RESPONSE_PD_LOG_ENTRY_SIZE];
+	struct ec_response_pd_log *response =
+		(struct ec_response_pd_log *)response_buffer;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_SIMPLE(EC_CMD_PD_GET_LOG_ENTRY, 0);
+
+	args.response = response;
+	args.response_max = sizeof(response_buffer);
+
+	for (int i = 0; i < 10; i++) {
+		zassert_ok(host_command_process(&args));
+
+		if (response->type == PD_EVENT_NO_ENTRY)
+			return;
+
+		k_sleep(K_MSEC(500));
+	}
+
+	zassert_unreachable("Failed to flush PD log");
+}
+
+ZTEST_F(nx20p348x_driver, test_vbus_overcurrent)
+{
+	uint8_t response_buffer[MAX_RESPONSE_PD_LOG_ENTRY_SIZE];
+	struct ec_response_pd_log *response =
+		(struct ec_response_pd_log *)response_buffer;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_SIMPLE(EC_CMD_PD_GET_LOG_ENTRY, 0);
+
+	flush_pd_log();
+
+	/* Set up overcurrent */
+	nx20p348x_emul_set_interrupt1(fixture->nx20p348x_emul,
+				      NX20P348X_INT1_OC_5VSRC);
+	k_sleep(K_MSEC(500));
+
+	args.response = response;
+	args.response_max = sizeof(response_buffer);
+
+	zassert_ok(host_command_process(&args));
+	zassert_equal(TEST_PORT, PD_LOG_PORT(response->size_port));
+	zassert_equal(0, PD_LOG_SIZE(response->size_port));
+	zassert_equal(PD_EVENT_PS_FAULT, response->type);
+	zassert_equal(PS_FAULT_OCP, response->data);
+}
+
+ZTEST_F(nx20p348x_driver, test_vbus_reverse_current)
+{
+	uint8_t response_buffer[MAX_RESPONSE_PD_LOG_ENTRY_SIZE];
+	struct ec_response_pd_log *response =
+		(struct ec_response_pd_log *)response_buffer;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_SIMPLE(EC_CMD_PD_GET_LOG_ENTRY, 0);
+
+	flush_pd_log();
+
+	/* Set up reverse current */
+	nx20p348x_emul_set_interrupt1(fixture->nx20p348x_emul,
+				      NX20P348X_INT1_RCP_5VSRC);
+	k_sleep(K_MSEC(500));
+
+	args.response = response;
+	args.response_max = sizeof(response_buffer);
+
+	zassert_ok(host_command_process(&args));
+	zassert_equal(TEST_PORT, PD_LOG_PORT(response->size_port));
+	zassert_equal(0, PD_LOG_SIZE(response->size_port));
+	zassert_equal(PD_EVENT_PS_FAULT, response->type);
+	zassert_equal(PS_FAULT_OCP, response->data);
+}
+
+ZTEST_F(nx20p348x_driver, test_vbus_short)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+	const char *outbuffer;
+	size_t buffer_size;
+
+	shell_backend_dummy_clear_output(shell_zephyr);
+
+	/* Set up Vbus short, which we only report in the console */
+	nx20p348x_emul_set_interrupt1(fixture->nx20p348x_emul,
+				      NX20P348X_INT1_SC_5VSRC);
+	k_sleep(K_MSEC(500));
+
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+
+	zassert_true(buffer_size > 0);
+
+	/* Weakly verify something reasonable was output to console */
+	zassert_not_null(strstr(outbuffer, "short"));
+}
diff --git a/zephyr/test/drivers/nx20p348x/usbc.dts b/zephyr/test/drivers/nx20p348x/usbc.dts
new file mode 100644
index 0000000000..86fb5781d6
--- /dev/null
+++ b/zephyr/test/drivers/nx20p348x/usbc.dts
@@ -0,0 +1,26 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/usb_pd_tcpm.h>
+
+/ {
+	usbc {
+		port0@0 {
+			compatible = "named-usbc-port";
+			ppc = <&nx20p348x_emul>;
+		};
+	};
+};
+
+&i2c2 {
+	status="okay";
+
+	nx20p348x_emul: nx20p348x_emul@9 {
+		compatible = "nxp,nx20p348x";
+		status = "okay";
+		reg = <0x71>;
+		irq-gpios = < &gpio0 14 GPIO_ACTIVE_LOW >;
+	};
+};
diff --git a/zephyr/test/drivers/panic_output/CMakeLists.txt b/zephyr/test/drivers/panic_output/CMakeLists.txt
new file mode 100644
index 0000000000..c9b50b0365
--- /dev/null
+++ b/zephyr/test/drivers/panic_output/CMakeLists.txt
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Add source files
+target_sources(app PRIVATE
+  src/panic_output_crash_cmd.c
+  src/panic_output_get_panic_data_write.c
+)
diff --git a/zephyr/test/drivers/panic_output/src/panic_output_crash_cmd.c b/zephyr/test/drivers/panic_output/src/panic_output_crash_cmd.c
new file mode 100644
index 0000000000..d2f169d261
--- /dev/null
+++ b/zephyr/test/drivers/panic_output/src/panic_output_crash_cmd.c
@@ -0,0 +1,190 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "panic.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <signal.h>
+#include <stdint.h>
+#include <stdio.h>
+
+#include <zephyr/kernel.h>
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+#include <zephyr/ztest_assert.h>
+
+/* Special return codes for run_crash_command() */
+#define RETURN_CODE_CRASHED (-1)
+#define RETURN_CODE_TIMEOUT (-2)
+
+/** Create a new thread for running the `crash` console command. As its name
+ * suggests, this command causes a number of fatal errors (e.g. divide by zero).
+ * Run it in a separate thread so that we can observe these crashes without
+ * causing the ztest thread that runs the test functions to get aborted.
+ */
+static struct k_thread crash_thread;
+
+/* Create a stack for the crash thread */
+K_THREAD_STACK_DEFINE(crash_thread_stack, 1024);
+
+/** Captures the last signal number received by `handle_signal()`. */
+static int signal_received;
+
+/**
+ * @brief Handler for signals sent to the process. Log the signal number and
+ *        abort the crash test.
+ *
+ * @param sig Signal number, from signal.h
+ */
+void handle_signal(int sig)
+{
+	signal_received = sig;
+
+	k_thread_abort(&crash_thread);
+}
+
+/**
+ * @brief Worker function for the crash thread that calls the `crash` console
+ *        command.
+ *
+ * @param a The value of `argc` (forced as a pointer type).
+ * @param b `argv` pointer.
+ * @param c Pointer to location to write the return value.
+ */
+static void crash_thread_worker(void *a, void *b, void *c)
+{
+	int argc = (int)a;
+	const char **argv = (const char **)b;
+	int *return_val = c;
+
+	/* If the return value remains RETURN_CODE_CRASHED, then the command
+	 * did not return.
+	 */
+	*return_val = RETURN_CODE_CRASHED;
+	signal_received = 0;
+
+	*return_val = test_command_crash(argc, argv);
+}
+
+/**
+ * @brief Helper function to spawn a new thread that runs the `crash` console
+ *        command. Waits for the command to exit/fail.
+ *
+ * @param argc Number of elements in `argv`
+ * @param argv CLI arguments to pass to command. Include the command name.
+ * @param timeout Time to wait for the thread to exit, in milliseconds.
+ * @return int Console command's return value, or RETURN_CODE_CRASHED if caused
+ *         a fatal error, or RETURN_CODE_TIMEOUT if it hung.
+ */
+static int run_crash_command(int argc, const char **argv, k_timeout_t timeout)
+{
+	static int return_val;
+
+	k_thread_create(&crash_thread, crash_thread_stack,
+			K_THREAD_STACK_SIZEOF(crash_thread_stack),
+			(k_thread_entry_t)crash_thread_worker, (void *)argc,
+			argv, &return_val, CONFIG_ZTEST_THREAD_PRIORITY + 1,
+			K_INHERIT_PERMS, K_NO_WAIT);
+
+	if (k_thread_join(&crash_thread, timeout) == -EAGAIN) {
+		k_thread_abort(&crash_thread);
+		return RETURN_CODE_TIMEOUT;
+	}
+
+	return return_val;
+}
+
+ZTEST(panic_output, test_feature_present)
+{
+	struct ec_response_get_features feat = host_cmd_get_features();
+
+	zassert_true(feat.flags[1] &
+			     EC_FEATURE_MASK_1(EC_FEATURE_ASSERT_REBOOTS),
+		     "Failed to see feature present");
+}
+
+ZTEST(panic_output, test_console_cmd__unaligned)
+{
+	int rv;
+	const char *cmd[] = { "crash", "unaligned" };
+
+	rv = run_crash_command(2, cmd, K_FOREVER);
+
+	zassert_equal(RETURN_CODE_CRASHED, rv,
+		      "Command returned %d but shouldn't have exited", rv);
+	zassert_equal(SIGSEGV, signal_received);
+}
+
+ZTEST(panic_output, test_console_cmd__watchdog)
+{
+	/* Note: this does not verify that the watchdog fired, but that is
+	 * covered in a different test suite.
+	 */
+
+	int rv;
+	const char *cmd[] = { "crash", "watchdog" };
+
+	rv = run_crash_command(2, cmd, K_MSEC(100));
+
+	zassert_equal(RETURN_CODE_TIMEOUT, rv,
+		      "Command returned %d but shouldn't have exited", rv);
+}
+
+ZTEST(panic_output, test_console_cmd__hang)
+{
+	int rv;
+	const char *cmd[] = { "crash", "hang" };
+
+	rv = run_crash_command(2, cmd, K_MSEC(100));
+
+	zassert_equal(RETURN_CODE_TIMEOUT, rv,
+		      "Command returned %d but shouldn't have exited", rv);
+}
+
+ZTEST(panic_output, test_console_cmd__null)
+{
+	int rv;
+	const char *cmd[] = { "crash", "null" };
+
+	rv = run_crash_command(2, cmd, K_FOREVER);
+
+	zassert_equal(RETURN_CODE_CRASHED, rv,
+		      "Command returned %d but shouldn't have exited", rv);
+	zassert_equal(SIGSEGV, signal_received);
+}
+
+ZTEST(panic_output, test_console_cmd__bad_param)
+{
+	int rv;
+	const char *cmd[] = { "crash", "xyz" };
+
+	rv = run_crash_command(2, cmd, K_FOREVER);
+
+	zassert_equal(EC_ERROR_PARAM1, rv, "Command returned %d", rv);
+}
+
+ZTEST(panic_output, test_console_cmd__no_param)
+{
+	int rv;
+	const char *cmd[] = { "crash" };
+
+	rv = run_crash_command(1, cmd, K_FOREVER);
+
+	zassert_equal(EC_ERROR_PARAM1, rv, "Command returned %d", rv);
+}
+
+static void reset(void *data)
+{
+	ARG_UNUSED(data);
+
+	signal(SIGSEGV, handle_signal);
+	signal(SIGFPE, handle_signal);
+	signal_received = 0;
+}
+
+ZTEST_SUITE(panic_output, drivers_predicate_post_main, NULL, reset, reset,
+	    NULL);
diff --git a/zephyr/test/drivers/panic_output/src/panic_output_get_panic_data_write.c b/zephyr/test/drivers/panic_output/src/panic_output_get_panic_data_write.c
new file mode 100644
index 0000000000..b691099b32
--- /dev/null
+++ b/zephyr/test/drivers/panic_output/src/panic_output_get_panic_data_write.c
@@ -0,0 +1,210 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "panic.h"
+#include "sysjump.h"
+#include "test/drivers/test_state.h"
+
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+
+#include <zephyr/ztest.h>
+#include <zephyr/ztest_assert.h>
+
+/**
+ * @brief Returns a pointer to an object (such as a struct jump_data) of type
+ *        TYPE at the end of the mock_jump_data memory region, plus an optional,
+ *        additional offset of OFFSET bytes. OFFSET can be used to help get the
+ *        pointer after jump data has been moved by get_panic_data_write(), or
+ *        left as zero to get the pre-move location.
+ */
+#define GET_JUMP_DATA_PTR(TYPE, OFFSET)                                    \
+	((TYPE *)(mock_jump_data + sizeof(mock_jump_data) - sizeof(TYPE) + \
+		  (OFFSET)))
+
+ZTEST(panic_output_get_panic_data_write, test_existing_panic_data)
+{
+	struct panic_data *pdata_actual = test_get_panic_data_pointer();
+
+	/* Pretend panic data exists by setting the magic header and setting its
+	 * size.
+	 */
+	pdata_actual->magic = PANIC_DATA_MAGIC;
+	pdata_actual->struct_size = CONFIG_PANIC_DATA_SIZE;
+
+	/* Verify that pdata_ptr is returned */
+	zassert_equal(pdata_actual, get_panic_data_write());
+}
+
+ZTEST(panic_output_get_panic_data_write, test_no_panic_data__no_jump_data)
+{
+	struct panic_data *pdata_actual = test_get_panic_data_pointer();
+	struct panic_data pdata_expected = {
+		.magic = PANIC_DATA_MAGIC,
+		.struct_size = CONFIG_PANIC_DATA_SIZE,
+	};
+
+	/* Don't fill in any panic data, but add some fake data so we can ensure
+	 * it gets reset to zero.
+	 */
+	pdata_actual->flags = 0xFF;
+
+	/* Verify that pdata_ptr is returned */
+	zassert_equal(pdata_actual, get_panic_data_write());
+
+	/* Verify the pdata struct has correct fields filled out. */
+	zassert_mem_equal(&pdata_expected, pdata_actual,
+			  sizeof(struct panic_data));
+}
+
+/**
+ * @brief Implements the fields of a version 1 jump_data header.
+ *
+ */
+struct jump_data_v1 {
+	/** V1 Jump data header, always goes at end. See sysjump.h for info */
+
+	uint32_t reset_flags;
+	int version;
+	int magic;
+};
+
+/* Test that V1 jump data is moved correctly. */
+ZTEST(panic_output_get_panic_data_write, test_no_panic_data__jump_data_v1)
+{
+	struct panic_data *pdata_actual = test_get_panic_data_pointer();
+	struct jump_data_v1 jdata_expected = {
+		.magic = JUMP_DATA_MAGIC,
+		.version = 1,
+		.reset_flags = 0xAABBCCDD,
+	};
+
+	/* Set up some jump data. Version 1 does not have any jump tags, only
+	 * the magic, version number, and reset_flags so it is constant size.
+	 */
+	*GET_JUMP_DATA_PTR(struct jump_data_v1, 0) = jdata_expected;
+
+	/* Verify that pdata_ptr is returned */
+	zassert_equal(pdata_actual, get_panic_data_write());
+
+	/* Verify that jump data has been moved to its new location */
+	ssize_t expected_move_delta = -1 * sizeof(struct panic_data);
+	struct jump_data_v1 *jdata_moved =
+		GET_JUMP_DATA_PTR(struct jump_data_v1, expected_move_delta);
+
+	zassert_mem_equal(&jdata_expected, jdata_moved,
+			  sizeof(struct jump_data_v1));
+}
+
+/**
+ * @brief Implements a V2 jump_data header plus some extra bytes in front that
+ *        represent jump tag data. This reflects how they are stored in the EC's
+ *        memory. The jump_tag_total field in jdata stored how many bytes of
+ *        preceding jump tag data exists.
+ */
+struct jump_data_v2_plus_tags {
+	/** Arbitrary amount of jump tag data. */
+	uint8_t tag_data[8];
+	/** V2 Jump data header, always goes at end. See sysjump.h for info */
+	struct {
+		int jump_tag_total;
+		uint32_t reset_flags;
+		int version;
+		int magic;
+	} jdata;
+};
+
+/* Test that V2 jump data is moved correctly. */
+ZTEST(panic_output_get_panic_data_write, test_no_panic_data__jump_data_v2)
+{
+	struct panic_data *pdata_actual = test_get_panic_data_pointer();
+	struct jump_data_v2_plus_tags jdata_expected = {
+		/* Arbitrary jump tag data */
+		.tag_data = {1, 2, 3, 4, 5, 6, 7, 8},
+		.jdata = {
+			.magic = JUMP_DATA_MAGIC,
+			.version = 2,
+			.reset_flags = 0xAABBCCDD,
+			.jump_tag_total = sizeof(jdata_expected.tag_data),
+		},
+	};
+
+	/* Set up some jump data and preceding tags */
+	*GET_JUMP_DATA_PTR(struct jump_data_v2_plus_tags, 0) = jdata_expected;
+
+	/* Verify that pdata_ptr is returned */
+	zassert_equal(pdata_actual, get_panic_data_write());
+
+	/* Verify that jump data and tags moved to their new location */
+	ssize_t expected_move_delta = -1 * sizeof(struct panic_data);
+	struct jump_data_v2_plus_tags *jdata_moved = GET_JUMP_DATA_PTR(
+		struct jump_data_v2_plus_tags, expected_move_delta);
+
+	zassert_mem_equal(&jdata_expected, jdata_moved,
+			  sizeof(struct jump_data_v2_plus_tags));
+}
+
+/**
+ * @brief Implements a V3 jump_data header with space in front for jump tag data
+ */
+struct jump_data_v3_plus_tags {
+	/** Arbitrary amount of jump tag data. */
+	uint8_t tag_data[8];
+	/** V3 Jump data header, always goes at end. See sysjump.h for info */
+	struct {
+		uint8_t reserved0;
+		int struct_size;
+		int jump_tag_total;
+		uint32_t reset_flags;
+		int version;
+		int magic;
+	} jdata;
+};
+
+/* Test that V3 jump data is moved correctly. */
+ZTEST(panic_output_get_panic_data_write, test_no_panic_data__jump_data_v3)
+{
+	struct panic_data *pdata_actual = test_get_panic_data_pointer();
+	struct jump_data_v3_plus_tags jdata_expected = {
+		/* Arbitrary jump tag data */
+		.tag_data = {1, 2, 3, 4, 5, 6, 7, 8},
+		.jdata = {
+			.magic = JUMP_DATA_MAGIC,
+			.version = 3,
+			.reset_flags = 0xAABBCCDD,
+			.jump_tag_total = sizeof(jdata_expected.tag_data),
+			.struct_size = sizeof(jdata_expected.jdata),
+			.reserved0 = 0xFF,
+		},
+	};
+
+	/* Set up some jump data and preceding tags */
+	*GET_JUMP_DATA_PTR(struct jump_data_v3_plus_tags, 0) = jdata_expected;
+
+	/* Verify that pdata_ptr is returned */
+	zassert_equal(pdata_actual, get_panic_data_write());
+
+	/* Verify that jump data and tags moved to their new location */
+	ssize_t expected_move_delta = -1 * sizeof(struct panic_data);
+	struct jump_data_v3_plus_tags *jdata_moved = GET_JUMP_DATA_PTR(
+		struct jump_data_v3_plus_tags, expected_move_delta);
+
+	zassert_mem_equal(&jdata_expected, jdata_moved,
+			  sizeof(struct jump_data_v3_plus_tags));
+}
+
+static void reset(void *data)
+{
+	ARG_UNUSED(data);
+
+	struct panic_data *pdata = test_get_panic_data_pointer();
+
+	memset(pdata, 0, sizeof(struct panic_data));
+	memset(mock_jump_data, 0, sizeof(mock_jump_data));
+}
+
+ZTEST_SUITE(panic_output_get_panic_data_write, drivers_predicate_post_main,
+	    NULL, reset, reset, NULL);
diff --git a/zephyr/test/drivers/power_host_sleep/CMakeLists.txt b/zephyr/test/drivers/power_host_sleep/CMakeLists.txt
new file mode 100644
index 0000000000..8b5f356719
--- /dev/null
+++ b/zephyr/test/drivers/power_host_sleep/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Add source files
+target_sources(app PRIVATE src/test_power_host_sleep.c)
diff --git a/zephyr/test/drivers/power_host_sleep/src/test_power_host_sleep.c b/zephyr/test/drivers/power_host_sleep/src/test_power_host_sleep.c
new file mode 100644
index 0000000000..46ff0cef65
--- /dev/null
+++ b/zephyr/test/drivers/power_host_sleep/src/test_power_host_sleep.c
@@ -0,0 +1,429 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "power.h"
+#include "test/drivers/test_mocks.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+#include <zephyr/ztest_assert.h>
+
+#define ARBITRARY_SLEEP_TRANSITIONS 1
+
+/*
+ * TODO(b/253224061): Reorganize fakes by public interface
+ */
+/* Fake to allow full linking */
+FAKE_VOID_FUNC(chipset_reset, enum chipset_shutdown_reason);
+FAKE_VALUE_FUNC(enum power_state, power_chipset_init);
+const struct power_signal_info power_signal_list[] = {};
+
+FAKE_VOID_FUNC(power_chipset_handle_host_sleep_event, enum host_sleep_event,
+	       struct host_sleep_event_context *);
+FAKE_VOID_FUNC(power_chipset_handle_sleep_hang, enum sleep_hang_type);
+FAKE_VOID_FUNC(power_board_handle_sleep_hang, enum sleep_hang_type);
+
+/* Per-Test storage of host_sleep_event_context to validate argument values */
+static struct host_sleep_event_context test_saved_context;
+
+/* Test-specific custom fake */
+static void _test_power_chipset_handle_host_sleep_event(
+	enum host_sleep_event state, struct host_sleep_event_context *ctx)
+{
+	switch (state) {
+	case HOST_SLEEP_EVENT_S0IX_RESUME:
+	case HOST_SLEEP_EVENT_S3_RESUME:
+		ctx->sleep_transitions = ARBITRARY_SLEEP_TRANSITIONS;
+		break;
+
+	case HOST_SLEEP_EVENT_S3_SUSPEND:
+	case HOST_SLEEP_EVENT_S0IX_SUSPEND:
+	case HOST_SLEEP_EVENT_S3_WAKEABLE_SUSPEND:
+		break;
+	}
+
+	memcpy(&test_saved_context, ctx,
+	       sizeof(struct host_sleep_event_context));
+}
+
+static void power_host_sleep_before_after(void *test_data)
+{
+	ARG_UNUSED(test_data);
+
+	RESET_FAKE(power_chipset_handle_host_sleep_event);
+	RESET_FAKE(power_chipset_handle_sleep_hang);
+	RESET_FAKE(power_board_handle_sleep_hang);
+	memset(&test_saved_context, 0, sizeof(struct host_sleep_event_context));
+
+	sleep_reset_tracking();
+}
+
+ZTEST_USER(power_host_sleep, test_non_existent_sleep_event_v1__bad_event)
+{
+	struct ec_params_host_sleep_event_v1 p = {
+		/* No such sleep event */
+		.sleep_event = UINT8_MAX,
+		/* Non-existent sleep event, so suspend params don't matter */
+		.suspend_params = { 0 },
+	};
+	struct ec_response_host_sleep_event_v1 r;
+	struct host_cmd_handler_args args;
+
+	/* Clear garbage for verifiable value */
+	r.resume_response.sleep_transitions = 0;
+
+	power_chipset_handle_host_sleep_event_fake.custom_fake =
+		_test_power_chipset_handle_host_sleep_event;
+
+	zassert_ok(ec_cmd_host_sleep_event_v1(&args, &p, &r));
+	zassert_equal(args.response_size, 0);
+	zassert_equal(power_chipset_handle_host_sleep_event_fake.call_count, 1);
+	zassert_equal(power_chipset_handle_host_sleep_event_fake.arg0_val,
+		      p.sleep_event);
+
+	/*
+	 * Unknown host sleep events don't retrieve sleep transitions from
+	 * chip-specific handler.
+	 */
+	zassert_equal(r.resume_response.sleep_transitions, 0);
+}
+
+ZTEST_USER(power_host_sleep, test_non_existent_sleep_event_v1__s3_suspend)
+{
+	struct ec_params_host_sleep_event_v1 p = {
+		.sleep_event = HOST_SLEEP_EVENT_S3_SUSPEND,
+	};
+	struct ec_response_host_sleep_event_v1 r;
+	struct host_cmd_handler_args args;
+
+	/* Set m/lsb of uint16_t to check for type coercion errors */
+	p.suspend_params.sleep_timeout_ms = BIT(15) + 1;
+
+	power_chipset_handle_host_sleep_event_fake.custom_fake =
+		_test_power_chipset_handle_host_sleep_event;
+
+	zassert_ok(ec_cmd_host_sleep_event_v1(&args, &p, &r));
+	zassert_equal(args.response_size, 0);
+	zassert_equal(power_chipset_handle_host_sleep_event_fake.call_count, 1);
+	zassert_equal(power_chipset_handle_host_sleep_event_fake.arg0_val,
+		      p.sleep_event);
+
+	/*
+	 * Verify sleep timeout propagated to chip-specific handler to use.
+	 */
+	zassert_equal(test_saved_context.sleep_timeout_ms,
+		      p.suspend_params.sleep_timeout_ms);
+}
+
+ZTEST_USER(power_host_sleep, test_non_existent_sleep_event_v1__s3_resume)
+{
+	struct ec_params_host_sleep_event_v1 p = {
+		.sleep_event = HOST_SLEEP_EVENT_S3_RESUME,
+	};
+	struct ec_response_host_sleep_event_v1 r;
+	struct host_cmd_handler_args args;
+
+	power_chipset_handle_host_sleep_event_fake.custom_fake =
+		_test_power_chipset_handle_host_sleep_event;
+
+	zassert_ok(ec_cmd_host_sleep_event_v1(&args, &p, &r));
+	zassert_equal(args.response_size, sizeof(r));
+	zassert_equal(power_chipset_handle_host_sleep_event_fake.call_count, 1);
+	zassert_equal(power_chipset_handle_host_sleep_event_fake.arg0_val,
+		      p.sleep_event);
+
+	/*
+	 * Verify sleep context propagated from chip-specific handler.
+	 */
+	zassert_equal(r.resume_response.sleep_transitions,
+		      ARBITRARY_SLEEP_TRANSITIONS);
+}
+
+ZTEST(power_host_sleep, test_sleep_start_suspend_custom_timeout)
+{
+	struct host_sleep_event_context context = {
+		/* Arbitrary 5ms timeout */
+		.sleep_timeout_ms = 5,
+	};
+
+	sleep_start_suspend(&context);
+	/*
+	 * Validate that function idempotent wrt calling chip-specific handlers
+	 */
+	sleep_start_suspend(&context);
+
+	/* Verify handlers not called because timeout didn't occur yet */
+	zassert_equal(power_chipset_handle_sleep_hang_fake.call_count, 0);
+	zassert_equal(power_board_handle_sleep_hang_fake.call_count, 0);
+
+	/* Allow timeout to occur */
+	/*
+	 * TODO(b/253284635): Why can't we just wait 5ms?
+	 */
+	k_sleep(K_SECONDS(1));
+
+	/* Check timeout handlers fired only *once* after multiple calls */
+	zassert_equal(power_chipset_handle_sleep_hang_fake.call_count, 1);
+	zassert_equal(power_board_handle_sleep_hang_fake.call_count, 1);
+
+	zassert_equal(power_chipset_handle_sleep_hang_fake.arg0_val,
+		      SLEEP_HANG_S0IX_SUSPEND);
+	zassert_equal(power_board_handle_sleep_hang_fake.arg0_val,
+		      SLEEP_HANG_S0IX_SUSPEND);
+}
+
+ZTEST(power_host_sleep, test_sleep_start_suspend_default_timeout)
+{
+	struct host_sleep_event_context context = {
+		.sleep_timeout_ms = EC_HOST_SLEEP_TIMEOUT_DEFAULT,
+	};
+
+	sleep_start_suspend(&context);
+
+	/*
+	 * TODO(b/253284635): Why can't we just wait CONFIG_SLEEP_TIMEOUT_MS?
+	 */
+	k_msleep(CONFIG_SLEEP_TIMEOUT_MS * 2);
+
+	zassert_equal(power_chipset_handle_sleep_hang_fake.call_count, 1);
+	zassert_equal(power_board_handle_sleep_hang_fake.call_count, 1);
+
+	zassert_equal(power_chipset_handle_sleep_hang_fake.arg0_val,
+		      SLEEP_HANG_S0IX_SUSPEND);
+	zassert_equal(power_board_handle_sleep_hang_fake.arg0_val,
+		      SLEEP_HANG_S0IX_SUSPEND);
+}
+
+ZTEST(power_host_sleep, test_sleep_start_suspend_infinite_timeout)
+{
+	struct host_sleep_event_context context = {
+		.sleep_timeout_ms = EC_HOST_SLEEP_TIMEOUT_INFINITE,
+	};
+
+	sleep_start_suspend(&context);
+
+	k_sleep(K_MSEC(CONFIG_SLEEP_TIMEOUT_MS * 2));
+
+	/* Verify that default handlers were never called */
+	zassert_equal(power_chipset_handle_sleep_hang_fake.call_count, 0);
+	zassert_equal(power_board_handle_sleep_hang_fake.call_count, 0);
+}
+
+ZTEST(power_host_sleep, test_suspend_then_resume_with_timeout)
+{
+	struct host_sleep_event_context context = {
+		.sleep_timeout_ms = EC_HOST_SLEEP_TIMEOUT_DEFAULT,
+		.sleep_transitions = 0.
+	};
+
+	/* Start then suspend process with deferred hook call */
+	sleep_start_suspend(&context);
+	/* Register the suspend transition (cancels timeout hook) */
+	sleep_suspend_transition();
+	k_sleep(K_MSEC(CONFIG_SLEEP_TIMEOUT_MS * 2));
+
+	/* No timeout hooks should've fired */
+	zassert_equal(power_chipset_handle_sleep_hang_fake.call_count, 0);
+	zassert_equal(power_board_handle_sleep_hang_fake.call_count, 0);
+
+	/* Transition to resume state and wait for hang timeout */
+	sleep_resume_transition();
+	k_sleep(K_MSEC(CONFIG_SLEEP_TIMEOUT_MS * 2));
+
+	/* Resume state transition timeout hook should've fired */
+	zassert_equal(power_chipset_handle_sleep_hang_fake.call_count, 1);
+	zassert_equal(power_board_handle_sleep_hang_fake.call_count, 1);
+	zassert_equal(power_chipset_handle_sleep_hang_fake.arg0_val,
+		      SLEEP_HANG_S0IX_RESUME);
+	zassert_equal(power_board_handle_sleep_hang_fake.arg0_val,
+		      SLEEP_HANG_S0IX_RESUME);
+
+	/* Complete resume so we can inspect the state transitions */
+	sleep_complete_resume(&context);
+
+	/* Transitioned to suspend and then to resume state. */
+	zassert_equal(context.sleep_transitions &
+			      EC_HOST_RESUME_SLEEP_TRANSITIONS_MASK,
+		      2);
+	/* There was a timeout */
+	zassert_true(context.sleep_transitions & EC_HOST_RESUME_SLEEP_TIMEOUT);
+}
+
+ZTEST(power_host_sleep, test_suspend_then_resume_with_reboot)
+{
+	struct ec_params_host_sleep_event_v1 p;
+	struct ec_response_host_sleep_event_v1 r;
+	struct host_cmd_handler_args args;
+	struct host_sleep_event_context context = {
+		.sleep_timeout_ms = EC_HOST_SLEEP_TIMEOUT_DEFAULT,
+		.sleep_transitions = 0.
+	};
+
+	/* Start then suspend process like the OS would */
+	p.sleep_event = HOST_SLEEP_EVENT_S0IX_SUSPEND;
+	zassert_ok(ec_cmd_host_sleep_event_v1(&args, &p, &r));
+
+	/* Verify we notified the chipset */
+	zassert_equal(power_chipset_handle_host_sleep_event_fake.call_count, 1);
+	zassert_equal(power_chipset_handle_host_sleep_event_fake.arg0_val,
+		      p.sleep_event);
+
+	/* Now kick the internals as if we suspend and then fail to resume */
+	sleep_start_suspend(&context);
+	/* Register the suspend transition (cancels timeout hook) */
+	sleep_suspend_transition();
+	k_sleep(K_MSEC(CONFIG_SLEEP_TIMEOUT_MS * 2));
+
+	/* No timeout hooks should've fired */
+	zassert_equal(power_chipset_handle_sleep_hang_fake.call_count, 0);
+	zassert_equal(power_board_handle_sleep_hang_fake.call_count, 0);
+
+	/* Transition to resume state and wait for hang timeout */
+	sleep_resume_transition();
+	k_sleep(K_MSEC(CONFIG_SLEEP_TIMEOUT_MS * 2));
+
+	/* Resume state transition timeout hook should've fired */
+	zassert_equal(power_chipset_handle_sleep_hang_fake.call_count, 1);
+	zassert_equal(power_board_handle_sleep_hang_fake.call_count, 1);
+	zassert_equal(power_chipset_handle_sleep_hang_fake.arg0_val,
+		      SLEEP_HANG_S0IX_RESUME);
+	zassert_equal(power_board_handle_sleep_hang_fake.arg0_val,
+		      SLEEP_HANG_S0IX_RESUME);
+
+	/* But now the OS says it's actually rebooted */
+	p.sleep_event = 0;
+	zassert_ok(ec_cmd_host_sleep_event_v1(&args, &p, &r));
+
+	/* Verify we alerted as if this was a resume */
+	zassert_equal(power_chipset_handle_host_sleep_event_fake.call_count, 2);
+	zassert_equal(power_chipset_handle_host_sleep_event_fake.arg0_val,
+		      HOST_SLEEP_EVENT_S0IX_RESUME);
+}
+
+ZTEST(power_host_sleep, test_suspend_then_reboot)
+{
+	struct ec_params_host_sleep_event_v1 p;
+	struct ec_response_host_sleep_event_v1 r;
+	struct host_cmd_handler_args args;
+	struct host_sleep_event_context context = {
+		.sleep_timeout_ms = EC_HOST_SLEEP_TIMEOUT_DEFAULT,
+		.sleep_transitions = 0.
+	};
+
+	/* Start then suspend process like the OS would */
+	p.sleep_event = HOST_SLEEP_EVENT_S0IX_SUSPEND;
+	zassert_ok(ec_cmd_host_sleep_event_v1(&args, &p, &r));
+
+	/* Verify we notified the chipset */
+	zassert_equal(power_chipset_handle_host_sleep_event_fake.call_count, 1);
+	zassert_equal(power_chipset_handle_host_sleep_event_fake.arg0_val,
+		      p.sleep_event);
+
+	/* Now kick the internals as if we suspend and then fail to resume */
+	sleep_start_suspend(&context);
+	/* Register the suspend transition (cancels timeout hook) */
+	sleep_suspend_transition();
+	k_sleep(K_MSEC(CONFIG_SLEEP_TIMEOUT_MS * 2));
+
+	/* No timeout hooks should've fired */
+	zassert_equal(power_chipset_handle_sleep_hang_fake.call_count, 0);
+	zassert_equal(power_board_handle_sleep_hang_fake.call_count, 0);
+
+	/* Transition to resume state and then send that we rebooted instead */
+	sleep_resume_transition();
+	p.sleep_event = 0;
+	zassert_ok(ec_cmd_host_sleep_event_v1(&args, &p, &r));
+
+	/* Verify we alerted as if this was a resume */
+	zassert_equal(power_chipset_handle_host_sleep_event_fake.call_count, 2);
+	zassert_equal(power_chipset_handle_host_sleep_event_fake.arg0_val,
+		      HOST_SLEEP_EVENT_S0IX_RESUME);
+}
+
+/* Only used in test_sleep_set_notify */
+static bool _test_host_sleep_hook_called;
+
+static void _test_sleep_notify_hook(void)
+{
+	_test_host_sleep_hook_called = true;
+}
+DECLARE_HOOK(HOOK_TEST_1, _test_sleep_notify_hook, HOOK_PRIO_DEFAULT);
+
+ZTEST(power_host_sleep, test_sleep_set_notify)
+{
+	/* Init as none */
+	sleep_set_notify(SLEEP_NOTIFY_NONE);
+
+	/* Verify hook may be notified for a specific NOTIFY state */
+	_test_host_sleep_hook_called = false;
+	sleep_set_notify(SLEEP_NOTIFY_SUSPEND);
+	sleep_notify_transition(SLEEP_NOTIFY_SUSPEND, HOOK_TEST_1);
+	k_sleep(K_SECONDS(1));
+
+	zassert_true(_test_host_sleep_hook_called);
+
+	/* Verify NOTIFY state is reset after firing hook */
+	_test_host_sleep_hook_called = false;
+	sleep_notify_transition(SLEEP_NOTIFY_SUSPEND, HOOK_TEST_1);
+	k_sleep(K_SECONDS(1));
+
+	zassert_false(_test_host_sleep_hook_called);
+
+	/*
+	 * Verify that SLEEP_NOTIFY_NONE is a potential hook state to fire
+	 * TODO(b/253480505) Should this really be allowed?
+	 */
+	_test_host_sleep_hook_called = false;
+	sleep_notify_transition(SLEEP_NOTIFY_NONE, HOOK_TEST_1);
+	k_sleep(K_SECONDS(1));
+
+	zassert_true(_test_host_sleep_hook_called);
+}
+
+ZTEST(power_host_sleep, test_set_get_host_sleep_state)
+{
+	power_set_host_sleep_state(HOST_SLEEP_EVENT_S3_RESUME);
+	zassert_equal(power_get_host_sleep_state(), HOST_SLEEP_EVENT_S3_RESUME);
+
+	power_set_host_sleep_state(HOST_SLEEP_EVENT_S0IX_RESUME);
+	zassert_equal(power_get_host_sleep_state(),
+		      HOST_SLEEP_EVENT_S0IX_RESUME);
+}
+
+ZTEST(power_host_sleep, verify_increment_change_state)
+{
+	struct ec_params_s0ix_cnt params = { .flags = EC_S0IX_COUNTER_RESET };
+	struct ec_response_s0ix_cnt rsp;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_GET_S0IX_COUNTER, 0, rsp, params);
+
+	/* Verify that counter is set to 0 */
+	zassert_ok(host_command_process(&args), "Failed to get sleep counter");
+	zassert_equal(rsp.s0ix_counter, 0);
+
+	/* Simulate S0ix state */
+	sleep_set_notify(SLEEP_NOTIFY_SUSPEND);
+	sleep_notify_transition(SLEEP_NOTIFY_SUSPEND, HOOK_CHIPSET_SUSPEND);
+
+	/* Confirm counter incrementation */
+	params.flags = 0;
+	zassert_ok(host_command_process(&args), "Failed to get sleep counter");
+	zassert_equal(rsp.s0ix_counter, 1);
+
+	/* Reset counter and re-fetch it to verify that reset works */
+	params.flags = EC_S0IX_COUNTER_RESET;
+	zassert_ok(host_command_process(&args), "Failed to get sleep counter");
+	params.flags = 0;
+	zassert_ok(host_command_process(&args), "Failed to get sleep counter");
+	zassert_equal(rsp.s0ix_counter, 0);
+}
+
+ZTEST_SUITE(power_host_sleep, drivers_predicate_post_main, NULL,
+	    power_host_sleep_before_after, power_host_sleep_before_after, NULL);
diff --git a/zephyr/test/drivers/prj.conf b/zephyr/test/drivers/prj.conf
new file mode 100644
index 0000000000..4800c15784
--- /dev/null
+++ b/zephyr/test/drivers/prj.conf
@@ -0,0 +1,167 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Enabling this config will show all I2C traffic, do not commit with this line
+# uncommented, it is here to make it easy to find/enable.
+# CONFIG_I2C_LOG_LEVEL_DBG=y
+
+CONFIG_ZTEST=y
+CONFIG_ZTEST_ASSERT_VERBOSE=1
+CONFIG_ZTEST_MOCKING=y
+CONFIG_ZTEST_NEW_API=y
+CONFIG_ZTEST_PARAMETER_COUNT=24
+CONFIG_TEST=y
+CONFIG_PLATFORM_EC_DEBUG_ASSERT=y
+# Do not set CONFIG_ASSERT_TEST=y here, it will mask assert failures.
+# Instead set CONFIG_ASSERT_TEST=y only on specific tests that require it.
+CONFIG_ASSERT_TEST=n
+CONFIG_SHELL_VT100_COMMANDS=n
+
+# Print logs from Zephyr LOG_MODULE to stdout
+CONFIG_NATIVE_UART_0_ON_STDINOUT=y
+
+# Simulate 10 ticks per ms
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=10000
+CONFIG_TASKS_SET_TEST_RUNNER_TID_RULE=y
+
+# Enable exception stack traces for better errors
+CONFIG_EXCEPTION_STACK_TRACE=y
+
+# Enable debugging features
+CONFIG_DEBUG=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_OPTIMIZATIONS=y
+CONFIG_PLATFORM_EC_CONSOLE_DEBUG=y
+CONFIG_SHELL_BACKEND_DUMMY=y
+CONFIG_SHELL_BACKEND_SERIAL=n
+CONFIG_SHELL_HELP=y
+# We aren't using the serial console, but there is still a lot of code that
+# assumes that a serial port exists.
+CONFIG_SERIAL=y
+CONFIG_RING_BUFFER=y
+CONFIG_PLATFORM_EC_I2C_DEBUG_PASSTHRU=y
+
+CONFIG_PLATFORM_EC=y
+CONFIG_CROS_EC=y
+CONFIG_SHIMMED_TASKS=y
+CONFIG_EMUL=y
+CONFIG_GPIO=y
+CONFIG_PLATFORM_EC_GPIO_INIT_PRIORITY=49
+CONFIG_EEPROM=y
+CONFIG_EEPROM_SIMULATOR=n
+CONFIG_EMUL_EEPROM_AT2X=y
+CONFIG_EMUL_TCPCI_PARTNER_DRP=y
+CONFIG_EMUL_TCPCI_PARTNER_FAULTY_EXT=y
+CONFIG_PLATFORM_EC_CHARGE_MANAGER=y
+CONFIG_PLATFORM_EC_CHARGE_RAMP_SW=y
+CONFIG_PLATFORM_EC_CHARGESPLASH=y
+
+CONFIG_PLATFORM_EC_POWERSEQ=y
+CONFIG_PLATFORM_EC_CMD_PWR_AVG=y
+
+CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y
+
+CONFIG_PLATFORM_EC_USB_PID=0x5000
+CONFIG_PLATFORM_EC_USBC=y
+CONFIG_PLATFORM_EC_USB_CHARGER=y
+CONFIG_PLATFORM_EC_USB_POWER_DELIVERY=y
+CONFIG_PLATFORM_EC_USB_PD_5V_EN_CUSTOM=y
+CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y
+CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC_CHARGER=y
+CONFIG_PLATFORM_EC_I2C_VIRTUAL_BATTERY=y
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=10
+CONFIG_PLATFORM_EC_CHARGER_ISL9238=y
+CONFIG_PLATFORM_EC_CHIP_INIT_ROM_REGION=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_CHARGER=y
+CONFIG_PLATFORM_EC_USB_PD_FRS=y
+CONFIG_PLATFORM_EC_USB_PD_FRS_PPC=y
+CONFIG_PLATFORM_EC_USB_PD_REV30=y
+CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y
+CONFIG_PLATFORM_EC_HOSTCMD=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_TUSB422=y
+CONFIG_PLATFORM_EC_USB_MUX_RUNTIME_CONFIG=y
+CONFIG_PLATFORM_EC_TEMP_SENSOR_POWER=y
+CONFIG_PLATFORM_EC_SWITCH=y
+CONFIG_PLATFORM_EC_SWITCHCAP_LN9310=y
+CONFIG_PLATFORM_EC_ACCEL_BMA255=y
+CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI160=y
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI260=y
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y
+CONFIG_PLATFORM_EC_ACCEL_FIFO=y
+CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=y
+CONFIG_PLATFORM_EC_ALS_TCS3400=y
+CONFIG_PLATFORM_EC_USB_PD_DISCHARGE=n
+CONFIG_PLATFORM_EC_USB_PD_TCPM_MUX=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8805=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8805_FORCE_DID=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8815=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8815_FORCE_DID=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8745=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8745_FORCE_ID=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_MULTI_PS8XXX=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y
+CONFIG_PLATFORM_EC_USB_PD_REQUIRE_AP_MODE_ENTRY=y
+CONFIG_PLATFORM_EC_USB_PD_CLEAR_HARD_RESET_STATUS=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_WAITMS=y
+CONFIG_PLATFORM_EC_POWER_SLEEP_FAILURE_DETECTION=y
+CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK=y
+
+CONFIG_ESPI=y
+CONFIG_EMUL_ESPI_HOST=y
+CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION=y
+CONFIG_ESPI_PERIPHERAL_CUSTOM_OPCODE=y
+CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD=y
+
+# Things that default to on, but aren't working yet
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
+CONFIG_PLATFORM_EC_VBOOT_HASH=n
+CONFIG_PLATFORM_EC_POWERSEQ_INTEL=n
+CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n
+
+# USB-C
+CONFIG_PLATFORM_EC_USBC_PPC_SYV682C=y
+CONFIG_PLATFORM_EC_USBC_PPC_SYV682X=y
+
+# Chipset for Herobrine
+CONFIG_AP_ARM_QUALCOMM_SC7280=y
+CONFIG_PLATFORM_EC_POWERSEQ_HOST_SLEEP=y
+
+CONFIG_PLATFORM_EC_LID_SWITCH=y
+CONFIG_PLATFORM_EC_POWER_BUTTON=y
+CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI=y
+CONFIG_PLATFORM_EC_PORT80=y
+CONFIG_PLATFORM_EC_VSTORE_SLOT_COUNT=2
+
+CONFIG_WATCHDOG=y
+CONFIG_WDT_DISABLE_AT_BOOT=y
+CONFIG_PLATFORM_EC_USB_PD_HOST_CMD=y
+CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_MKBP=y
+CONFIG_PLATFORM_EC_MKBP_EVENT=y
+CONFIG_PLATFORM_EC_MKBP_USE_GPIO=y
+CONFIG_PLATFORM_EC_MKBP_INPUT_DEVICES=y
+CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI2=y
+CONFIG_FLASH=y
+CONFIG_PLATFORM_EC_VBOOT_HASH=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_ADC_AMON_BMON=y
+CONFIG_PLATFORM_EC_CHARGER_PSYS=y
+CONFIG_PLATFORM_EC_CHARGER_PSYS_READ=y
+CONFIG_PLATFORM_EC_CHARGE_RAMP_HW=y
+
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=y
+
+CONFIG_PLATFORM_EC_ACCEL_SPOOF_MODE=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_SPOOF=y
+
+CONFIG_PLATFORM_EC_CONSOLE_CMD_MD=y
+
+CONFIG_PLATFORM_EC_LID_ANGLE=y
+CONFIG_PLATFORM_EC_TABLET_MODE=y
+
+# Power Management (Herobrine arch enables this)
+CONFIG_PM=y
+
+CONFIG_INPUT=y
diff --git a/zephyr/test/drivers/ps8xxx/CMakeLists.txt b/zephyr/test/drivers/ps8xxx/CMakeLists.txt
new file mode 100644
index 0000000000..2d15560cf0
--- /dev/null
+++ b/zephyr/test/drivers/ps8xxx/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Add source files
+target_sources(app PRIVATE src/multi_port.c)
diff --git a/zephyr/test/drivers/ps8xxx/prj.conf b/zephyr/test/drivers/ps8xxx/prj.conf
new file mode 100644
index 0000000000..1914f331ef
--- /dev/null
+++ b/zephyr/test/drivers/ps8xxx/prj.conf
@@ -0,0 +1,11 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_PLATFORM_EC_USB_PD_TCPC_LOW_POWER=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8745=n
+CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8745_FORCE_ID=n
+CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8805=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8805_FORCE_DID=n
+CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8815=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8815_FORCE_DID=n
diff --git a/zephyr/test/drivers/ps8xxx/src/multi_port.c b/zephyr/test/drivers/ps8xxx/src/multi_port.c
new file mode 100644
index 0000000000..76bcbb4c38
--- /dev/null
+++ b/zephyr/test/drivers/ps8xxx/src/multi_port.c
@@ -0,0 +1,70 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/tcpm/tcpci.h"
+#include "emul/tcpc/emul_ps8xxx.h"
+#include "tcpm/tcpm.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+#define PS8XXX_NODE_0 DT_NODELABEL(ps8xxx_emul0)
+#define PS8XXX_NODE_1 DT_NODELABEL(ps8xxx_emul1)
+
+ZTEST_SUITE(multi_port, drivers_predicate_post_main, NULL, NULL, NULL, NULL);
+
+const struct emul *ps8xxx_emul_0 = EMUL_DT_GET(PS8XXX_NODE_0);
+const struct emul *ps8xxx_emul_1 = EMUL_DT_GET(PS8XXX_NODE_1);
+
+ZTEST(multi_port, test_multiple_ports)
+{
+	zassert_ok(tcpci_emul_set_reg(ps8xxx_emul_0, TCPC_REG_BCD_DEV, 2),
+		   "Unable to set device id for emulator 0.\n");
+	zassert_ok(tcpci_emul_set_reg(ps8xxx_emul_1, TCPC_REG_BCD_DEV, 3),
+		   "Unable to set device id for emulator 1.\n");
+
+	struct ec_response_pd_chip_info_v1 info[USBC_PORT_COUNT];
+
+	for (enum usbc_port p = USBC_PORT_C0; p < USBC_PORT_COUNT; p++) {
+		zassert_ok(tcpm_get_chip_info(p, true, &info[p]),
+			   "Failed to process tcpm_get_chip_info for port %d",
+			   p);
+	}
+
+	zassert_true(info[USBC_PORT_C0].device_id !=
+			     info[USBC_PORT_C1].device_id,
+		     "port 0 and port 1 contains duplicate information.\n");
+}
+
+ZTEST(multi_port, test_fw_version_cache)
+{
+	zassert_ok(tcpci_emul_set_reg(ps8xxx_emul_0, PS8XXX_REG_FW_REV, 0x12),
+		   "Unable to set firmware rev for emulator 0.\n");
+	zassert_ok(tcpci_emul_set_reg(ps8xxx_emul_1, PS8XXX_REG_FW_REV, 0x13),
+		   "Unable to set firmware rev for emulator 1.\n");
+
+	struct ec_response_pd_chip_info_v1 info[USBC_PORT_COUNT];
+
+	for (enum usbc_port p = USBC_PORT_C0; p < USBC_PORT_COUNT; p++) {
+		zassert_ok(tcpm_get_chip_info(p, true, &info[p]),
+			   "Failed to process tcpm_get_chip_info for port %d",
+			   p);
+	}
+
+	/* info is read from the cache the second time */
+	for (enum usbc_port p = USBC_PORT_C0; p < USBC_PORT_COUNT; p++) {
+		zassert_ok(tcpm_get_chip_info(p, false, &info[p]),
+			   "Failed to process tcpm_get_chip_info for port %d",
+			   p);
+	}
+
+	zassert_true(info[USBC_PORT_C0].fw_version_number == 0x12,
+		     "port 0 fw version cache is incorrect.\n");
+	zassert_true(info[USBC_PORT_C1].fw_version_number == 0x13,
+		     "port 1 fw version cache is incorrect.\n");
+}
diff --git a/zephyr/test/drivers/ps8xxx/usbc.dts b/zephyr/test/drivers/ps8xxx/usbc.dts
new file mode 100644
index 0000000000..5bdf9b1696
--- /dev/null
+++ b/zephyr/test/drivers/ps8xxx/usbc.dts
@@ -0,0 +1,46 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/usb_pd_tcpm.h>
+
+/ {
+	usbc {
+		port0@0 {
+			compatible = "named-usbc-port";
+			tcpc = <&ps8xxx_emul0>;
+		};
+		port1@1 {
+			compatible = "named-usbc-port";
+			tcpc = <&ps8xxx_emul1>;
+		};
+	};
+};
+
+&i2c2 {
+	status="okay";
+
+	ps8xxx_emul0: ps8xxx_emul@c {
+		compatible = "cros,ps8xxx-emul";
+		reg = <0xc>;
+		p0-i2c-addr = <0x10>;
+		p1-i2c-addr = <0x11>;
+		gpio-i2c-addr = <0x1b>;
+	};
+};
+
+&i2c3 {
+	status="okay";
+
+	/delete-node/ ps8xxx_emul@b;
+
+	ps8xxx_emul1: ps8xxx_emul@b {
+		compatible = "cros,ps8xxx-emul";
+		reg = <0xb>;
+		p0-i2c-addr = <0x8>;
+		p1-i2c-addr = <0x9>;
+		gpio-i2c-addr = <0x1a>;
+	};
+
+};
diff --git a/zephyr/test/drivers/random/CMakeLists.txt b/zephyr/test/drivers/random/CMakeLists.txt
new file mode 100644
index 0000000000..0858abf2f6
--- /dev/null
+++ b/zephyr/test/drivers/random/CMakeLists.txt
@@ -0,0 +1,5 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_sources(app PRIVATE src/random.c)
diff --git a/zephyr/test/drivers/random/src/random.c b/zephyr/test/drivers/random/src/random.c
new file mode 100644
index 0000000000..f8849c839c
--- /dev/null
+++ b/zephyr/test/drivers/random/src/random.c
@@ -0,0 +1,96 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "ec_commands.h"
+#include "host_command.h"
+#include "test/drivers/test_mocks.h"
+#include "test/drivers/test_state.h"
+#include "trng.h"
+
+#include <zephyr/shell/shell_dummy.h>
+#include <zephyr/ztest.h>
+
+ZTEST_USER(random, test_hostcmd_rand)
+{
+	uint8_t rand_response1[16];
+	uint8_t rand_response2[16];
+	struct ec_params_rand_num params = {
+		.num_rand_bytes = 16,
+	};
+	struct host_cmd_handler_args args1 = BUILD_HOST_COMMAND(
+		EC_CMD_RAND_NUM, EC_VER_RAND_NUM, rand_response1, params);
+	struct host_cmd_handler_args args2 = BUILD_HOST_COMMAND(
+		EC_CMD_RAND_NUM, EC_VER_RAND_NUM, rand_response2, params);
+
+	/*
+	 * It's necessary to set response_max, because 'ec_response_rand_num'
+	 * structure has flexible array member.
+	 */
+	args1.response_max = 16;
+	args2.response_max = 16;
+	system_is_locked_fake.return_val = 0;
+
+	zassert_ok(host_command_process(&args1), NULL);
+	zassert_ok(host_command_process(&args2), NULL);
+	zassert_equal(args1.response_size, params.num_rand_bytes);
+	zassert_equal(args2.response_size, params.num_rand_bytes);
+	zassert_true(memcmp(rand_response1, rand_response2,
+			    params.num_rand_bytes) != 0);
+	zassert_equal(system_is_locked_fake.call_count, 2);
+}
+
+ZTEST_USER(random, test_hostcmd_rand_overflow)
+{
+	uint8_t rand_response[16];
+	struct ec_params_rand_num params = {
+		.num_rand_bytes = 16,
+	};
+	struct host_cmd_handler_args args = BUILD_HOST_COMMAND(
+		EC_CMD_RAND_NUM, EC_VER_RAND_NUM, rand_response, params);
+
+	/* Change maximum response size to small value. */
+	args.response_max = 8;
+	system_is_locked_fake.return_val = 0;
+
+	zassert_equal(host_command_process(&args), EC_RES_OVERFLOW);
+}
+
+ZTEST_USER(random, test_hostcmd_rand_access_denied)
+{
+	uint8_t rand_response[16];
+	struct ec_params_rand_num params = {
+		.num_rand_bytes = 16,
+	};
+
+	system_is_locked_fake.return_val = 1;
+
+	zassert_equal(
+		ec_cmd_rand_num(NULL, &params,
+				(struct ec_response_rand_num *)rand_response),
+		EC_RES_ACCESS_DENIED, NULL);
+	zassert_equal(system_is_locked_fake.call_count, 1);
+}
+
+ZTEST_USER(random, test_console_cmd_rand)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+	const char *outbuffer;
+	size_t buffer_size;
+
+	shell_backend_dummy_clear_output(shell_zephyr);
+
+	zassert_ok(shell_execute_cmd(shell_zephyr, "rand"));
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+
+	/*
+	 * Output has "rand 64_random_characters" format, so buffer should have
+	 * at least 69 characters.
+	 */
+	zassert_true(buffer_size >= 69, "buffer size is %d", buffer_size);
+	zassert_not_null(strstr(outbuffer, "rand "));
+}
+
+ZTEST_SUITE(random, drivers_predicate_post_main, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/drivers/rt1718s/CMakeLists.txt b/zephyr/test/drivers/rt1718s/CMakeLists.txt
new file mode 100644
index 0000000000..d285a94fa4
--- /dev/null
+++ b/zephyr/test/drivers/rt1718s/CMakeLists.txt
@@ -0,0 +1,12 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}/include")
+
+# Add source files
+target_sources(app PRIVATE
+  src/test_common.c
+  src/tcpc.c
+  src/gpio.c
+)
diff --git a/zephyr/test/drivers/rt1718s/include/test_common.h b/zephyr/test/drivers/rt1718s/include/test_common.h
new file mode 100644
index 0000000000..e742d2b34d
--- /dev/null
+++ b/zephyr/test/drivers/rt1718s/include/test_common.h
@@ -0,0 +1,19 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef _RT1718S_TEST_COMMON_
+#define _RT1718S_TEST_COMMON_
+
+#include <zephyr/drivers/emul.h>
+
+extern const int tcpm_rt1718s_port;
+extern const struct emul *rt1718s_emul;
+
+void rt1718s_clear_set_reg_history(void *f);
+
+void compare_reg_val_with_mask(const struct emul *emul, int reg,
+			       uint16_t expected, uint16_t mask);
+
+#endif /* _RT1718S_TEST_COMMON_ */
diff --git a/zephyr/test/drivers/rt1718s/ppc_tcpc.dts b/zephyr/test/drivers/rt1718s/ppc_tcpc.dts
new file mode 100644
index 0000000000..34df3596b5
--- /dev/null
+++ b/zephyr/test/drivers/rt1718s/ppc_tcpc.dts
@@ -0,0 +1,39 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/usb_pd_tcpm.h>
+
+/ {
+	usbc {
+		port0@0 {
+			compatible = "named-usbc-port";
+			bc12 = <&bc12_port0>;
+			tcpc = <&rt1718s_emul>;
+		};
+	};
+};
+
+&i2c0 {
+	status="okay";
+
+	rt1718s_emul: rt1718s_emul@2c {
+		compatible = "cros,rt1718s-tcpc-emul", "richtek,rt1718s-tcpc";
+
+		status = "okay";
+
+		reg = <0x2c>;
+		tcpc-flags = <(
+			TCPC_FLAGS_ALERT_OD |
+			TCPC_FLAGS_CONTROL_VCONN |
+			TCPC_FLAGS_CONTROL_FRS)>;
+	};
+
+	bc12_port0: rt1718s@2c {
+		compatible = "richtek,rt1718s-bc12", "cros,i2c-mock";
+		status = "okay";
+		reg = <0x2c>;
+	};
+
+};
diff --git a/zephyr/test/drivers/rt1718s/prj.conf b/zephyr/test/drivers/rt1718s/prj.conf
new file mode 100644
index 0000000000..a38bde7b92
--- /dev/null
+++ b/zephyr/test/drivers/rt1718s/prj.conf
@@ -0,0 +1,7 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_PLATFORM_EC_USB_PD_TCPC_LOW_POWER=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_SBU=y
+CONFIG_PLATFORM_EC_USB_PD_FRS_TCPC=y
diff --git a/zephyr/test/drivers/rt1718s/src/gpio.c b/zephyr/test/drivers/rt1718s/src/gpio.c
new file mode 100644
index 0000000000..2c9a29cf3e
--- /dev/null
+++ b/zephyr/test/drivers/rt1718s/src/gpio.c
@@ -0,0 +1,118 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/tcpm/rt1718s.h"
+#include "emul/tcpc/emul_rt1718s.h"
+#include "gpio.h"
+#include "test/drivers/test_state.h"
+#include "test_common.h"
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+ZTEST_SUITE(rt1718s_gpio, drivers_predicate_post_main, NULL,
+	    rt1718s_clear_set_reg_history, rt1718s_clear_set_reg_history, NULL);
+
+ZTEST(rt1718s_gpio, test_set_gpio_flags)
+{
+	struct {
+		int gpio_config;
+		int expected_reg_val;
+	} testdata[] = {
+		{
+			/* output high with open drain */
+			GPIO_OUTPUT | GPIO_HIGH | GPIO_OPEN_DRAIN,
+			RT1718S_GPIO_CTRL_OE | RT1718S_GPIO_CTRL_O,
+		},
+		{
+			/* output high with push pull  */
+			GPIO_OUTPUT | GPIO_HIGH,
+			RT1718S_GPIO_CTRL_OE | RT1718S_GPIO_CTRL_O |
+				RT1718S_GPIO_CTRL_OD_N,
+		},
+		{
+			/* output low with open drain */
+			GPIO_OUTPUT | GPIO_LOW | GPIO_OPEN_DRAIN,
+			RT1718S_GPIO_CTRL_OE,
+		},
+		{
+			/* output low with push pull */
+			GPIO_OUTPUT | GPIO_LOW,
+			RT1718S_GPIO_CTRL_OE | RT1718S_GPIO_CTRL_OD_N,
+		},
+		{
+			/* input with floating */
+			GPIO_INPUT,
+			RT1718S_GPIO_CTRL_OD_N,
+		},
+		{
+			/* input with pull up */
+			GPIO_INPUT | GPIO_PULL_UP,
+			RT1718S_GPIO_CTRL_PU | RT1718S_GPIO_CTRL_OD_N,
+		},
+		{
+			/* input with pull down */
+			GPIO_INPUT | GPIO_PULL_DOWN,
+			RT1718S_GPIO_CTRL_PD | RT1718S_GPIO_CTRL_OD_N,
+		},
+		{
+			/* input with pull up and down */
+			GPIO_INPUT | GPIO_PULL_UP | GPIO_PULL_DOWN,
+			RT1718S_GPIO_CTRL_PU | RT1718S_GPIO_CTRL_PD |
+				RT1718S_GPIO_CTRL_OD_N,
+		},
+	};
+
+	for (int gpio_num = RT1718S_GPIO1; gpio_num < RT1718S_GPIO_COUNT;
+	     gpio_num++) {
+		for (int i = 0; i < ARRAY_SIZE(testdata); i++) {
+			rt1718s_gpio_set_flags(tcpm_rt1718s_port, gpio_num,
+					       testdata[i].gpio_config);
+			compare_reg_val_with_mask(rt1718s_emul,
+						  RT1718S_GPIO_CTRL(gpio_num),
+						  testdata[i].expected_reg_val,
+						  0xFF);
+		}
+	}
+}
+
+ZTEST(rt1718s_gpio, test_set_level)
+{
+	for (int gpio_num = RT1718S_GPIO1; gpio_num < RT1718S_GPIO_COUNT;
+	     gpio_num++) {
+		rt1718s_gpio_set_level(tcpm_rt1718s_port, gpio_num, 0);
+		compare_reg_val_with_mask(rt1718s_emul,
+					  RT1718S_GPIO_CTRL(gpio_num), 0,
+					  RT1718S_GPIO_CTRL_O);
+		rt1718s_gpio_set_level(tcpm_rt1718s_port, gpio_num, 1);
+		compare_reg_val_with_mask(rt1718s_emul,
+					  RT1718S_GPIO_CTRL(gpio_num), 0xFF,
+					  RT1718S_GPIO_CTRL_O);
+	}
+}
+
+ZTEST(rt1718s_gpio, test_get_level)
+{
+	for (int gpio_num = RT1718S_GPIO1; gpio_num < RT1718S_GPIO_COUNT;
+	     gpio_num++) {
+		zassert_ok(rt1718s_emul_set_reg(
+			rt1718s_emul, RT1718S_GPIO_CTRL(gpio_num), 0));
+		compare_reg_val_with_mask(rt1718s_emul,
+					  RT1718S_GPIO_CTRL(gpio_num), 0,
+					  RT1718S_GPIO_CTRL_I);
+		zassert_ok(rt1718s_emul_set_reg(rt1718s_emul,
+						RT1718S_GPIO_CTRL(gpio_num),
+						RT1718S_GPIO_CTRL_I));
+		compare_reg_val_with_mask(rt1718s_emul,
+					  RT1718S_GPIO_CTRL(gpio_num), 0xFF,
+					  RT1718S_GPIO_CTRL_I);
+	}
+}
+
+ZTEST(rt1718s_gpio, test_command_rt1718s_gpio)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "rt1718s_gpio"),
+		   "Cannot execute command to get gpio on rt1718s");
+}
diff --git a/zephyr/test/drivers/rt1718s/src/tcpc.c b/zephyr/test/drivers/rt1718s/src/tcpc.c
new file mode 100644
index 0000000000..6db90b32c9
--- /dev/null
+++ b/zephyr/test/drivers/rt1718s/src/tcpc.c
@@ -0,0 +1,225 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/tcpm/rt1718s.h"
+#include "driver/tcpm/rt1718s_public.h"
+#include "driver/tcpm/tcpci.h"
+#include "emul/tcpc/emul_rt1718s.h"
+#include "test/drivers/test_state.h"
+#include "test_common.h"
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/sys/slist.h>
+#include <zephyr/ztest.h>
+
+ZTEST_SUITE(rt1718s_tcpc, drivers_predicate_post_main, NULL,
+	    rt1718s_clear_set_reg_history, rt1718s_clear_set_reg_history, NULL);
+
+static void test_bc12_reg_init_settings(const struct emul *emul)
+{
+	/* Vendor defined BC12 function is enabled */
+	compare_reg_val_with_mask(emul, RT1718S_RT_MASK6,
+				  RT1718S_RT_MASK6_M_BC12_SNK_DONE |
+					  RT1718S_RT_MASK6_M_BC12_TA_CHG,
+				  0xFF);
+	compare_reg_val_with_mask(emul, RT1718S_RT2_SBU_CTRL_01,
+				  RT1718S_RT2_SBU_CTRL_01_DPDM_VIEN |
+					  RT1718S_RT2_SBU_CTRL_01_DM_SWEN |
+					  RT1718S_RT2_SBU_CTRL_01_DP_SWEN,
+				  0xFF);
+	/* 2.7v mode is disabled */
+	compare_reg_val_with_mask(emul, RT1718S_RT2_BC12_SNK_FUNC, 0,
+				  RT1718S_RT2_BC12_SNK_FUNC_SPEC_TA_EN);
+	/* DCDT is set to 600ms timeout */
+	compare_reg_val_with_mask(emul, RT1718S_RT2_BC12_SNK_FUNC,
+				  RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_600MS,
+				  RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_MASK);
+	/* vlgc option is disabled */
+	compare_reg_val_with_mask(emul, RT1718S_RT2_BC12_SNK_FUNC, 0,
+				  RT1718S_RT2_BC12_SNK_FUNC_VLGC_OPT);
+	/* DPDM voltage selection is set to 65V */
+	compare_reg_val_with_mask(
+		emul, RT1718S_RT2_DPDM_CTR1_DPDM_SET,
+		RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_0_65V,
+		RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_MASK);
+	/* Sink wait vbus is disabled */
+	compare_reg_val_with_mask(emul, RT1718S_RT2_BC12_SNK_FUNC, 0,
+				  RT1718S_RT2_BC12_SNK_FUNC_BC12_WAIT_VBUS);
+}
+
+static void test_common_reg_init_settings(const struct emul *emul)
+{
+	/* VBUS_VOL_SEL is set to 20V */
+	compare_reg_val_with_mask(emul, RT1718S_RT2_VBUS_VOL_CTRL,
+				  RT1718S_VBUS_VOL_TO_REG(20),
+				  RT1718S_RT2_VBUS_VOL_CTRL_VOL_SEL);
+	/* VCONN_OCP_SEL is set to 400mA */
+	compare_reg_val_with_mask(emul, RT1718S_VCONN_CONTROL_3, 0x7F,
+				  RT1718S_VCONN_CONTROL_3_VCONN_OCP_SEL);
+	/* Vconn OCP shoot detection is increased from 200ns to 3~5us */
+	compare_reg_val_with_mask(emul, RT1718S_VCON_CTRL4, 0,
+				  RT1718S_VCON_CTRL4_OCP_CP_EN);
+	/* FOD function is disabled */
+	compare_reg_val_with_mask(emul, 0xCF, 0, 0x40);
+	/* Exit shipping mode request is set */
+	compare_reg_val_with_mask(emul, RT1718S_SYS_CTRL1, 0,
+				  RT1718S_SYS_CTRL1_TCPC_CONN_INVALID);
+	compare_reg_val_with_mask(emul, RT1718S_SYS_CTRL1, 0xFF,
+				  RT1718S_SYS_CTRL1_SHIPPING_OFF);
+	/* Alert and fault is cleared */
+	compare_reg_val_with_mask(emul, TCPC_REG_FAULT_STATUS, 0, 0xFF);
+	compare_reg_val_with_mask(emul, TCPC_REG_ALERT, 0, 0xFFFF);
+	/*
+	 * TODO Validate vendor defined alert mask is set once tcpci emul fix.
+	 */
+	/* FRS settings: Rx frs and valid vbus fall is set to unmasked */
+	compare_reg_val_with_mask(emul, RT1718S_RT_MASK1, 0xFF,
+				  RT1718S_RT_MASK1_M_RX_FRS |
+					  RT1718S_RT_MASK1_M_VBUS_FRS_LOW);
+}
+
+ZTEST(rt1718s_tcpc, test_init_with_device_id_es1)
+{
+	rt1718s_emul_set_device_id(rt1718s_emul, RT1718S_DEVICE_ID_ES1);
+	zassert_ok(rt1718s_tcpm_drv.init(tcpm_rt1718s_port),
+		   "Cannot initialize rt1718s");
+	test_bc12_reg_init_settings(rt1718s_emul);
+	test_common_reg_init_settings(rt1718s_emul);
+
+	compare_reg_val_with_mask(rt1718s_emul, RT1718S_VCONN_CONTROL_3, 0xFF,
+				  RT1718S_VCONN_CONTROL_3_VCONN_OVP_DEG);
+}
+
+ZTEST(rt1718s_tcpc, test_init_with_device_id_es2)
+{
+	rt1718s_emul_set_device_id(rt1718s_emul, RT1718S_DEVICE_ID_ES2);
+	zassert_ok(rt1718s_tcpm_drv.init(tcpm_rt1718s_port),
+		   "Cannot initialize rt1718s");
+	test_bc12_reg_init_settings(rt1718s_emul);
+	test_common_reg_init_settings(rt1718s_emul);
+
+	compare_reg_val_with_mask(rt1718s_emul, TCPC_REG_FAULT_CTRL, 0xFF,
+				  TCPC_REG_FAULT_CTRL_VCONN_OCP_FAULT_DIS);
+	compare_reg_val_with_mask(rt1718s_emul, RT1718S_VCON_CTRL4, 0,
+				  RT1718S_VCON_CTRL4_UVP_CP_EN |
+					  RT1718S_VCON_CTRL4_OCP_CP_EN);
+	compare_reg_val_with_mask(rt1718s_emul, RT1718S_VCONN_CONTROL_2, 0xFF,
+				  RT1718S_VCONN_CONTROL_2_OVP_EN_CC1 |
+					  RT1718S_VCONN_CONTROL_2_OVP_EN_CC2);
+}
+
+ZTEST(rt1718s_tcpc, test_set_vconn_enable)
+{
+	struct _snode *iter_node = NULL;
+	struct set_reg_entry_t *iter_entry = NULL;
+	struct set_reg_entry_t *set_vconn_limit_on_entry = NULL;
+	struct set_reg_entry_t *set_vconn_limit_off_entry = NULL;
+	struct rt1718s_emul_data *rt1718s_data = rt1718s_emul->data;
+	struct _slist *set_private_reg_history =
+		&rt1718s_data->set_private_reg_history;
+
+	zassert_ok(rt1718s_tcpm_drv.set_vconn(tcpm_rt1718s_port, true));
+
+	iter_node = sys_slist_peek_head(set_private_reg_history);
+	while (iter_node != NULL) {
+		iter_entry = SYS_SLIST_CONTAINER(iter_node, iter_entry, node);
+		if (iter_entry->reg == RT1718S_VCON_CTRL3 &&
+		    (iter_entry->val & RT1718S_VCON_LIMIT_MODE) == 1) {
+			set_vconn_limit_on_entry = iter_entry;
+			break;
+		}
+		iter_node = iter_node->next;
+	}
+	/* b/233698718#comment9 workaround should applied */
+	zassert_not_null(set_vconn_limit_on_entry,
+			 "No entry for setting RT1718S_VCON_CTRL3");
+	while (iter_node != NULL) {
+		iter_entry = SYS_SLIST_CONTAINER(iter_node, iter_entry, node);
+		if (iter_entry->reg == RT1718S_VCON_CTRL3 &&
+		    (iter_entry->val & RT1718S_VCON_LIMIT_MODE) == 0) {
+			set_vconn_limit_off_entry = iter_entry;
+			break;
+		}
+		iter_node = iter_node->next;
+	}
+	zassert_not_null(set_vconn_limit_off_entry,
+			 "No entry for setting RT1718S_VCON_CTRL3");
+	zassert_true(
+		(set_vconn_limit_off_entry->access_time -
+		 set_vconn_limit_on_entry->access_time) >= 10,
+		"Workaround for two setting Vconn limit is smaller than 10ms");
+
+	/* rt1718s should be in shutdown mode. */
+	compare_reg_val_with_mask(rt1718s_emul, RT1718S_VCON_CTRL3, 0x0,
+				  RT1718S_VCON_LIMIT_MODE);
+	/* Vconn RVP should be enabled. */
+	compare_reg_val_with_mask(rt1718s_emul, RT1718S_VCONN_CONTROL_2, 0xFF,
+				  RT1718S_VCONN_CONTROL_2_RVP_EN);
+}
+
+ZTEST(rt1718s_tcpc, test_set_vconn_disable)
+{
+	zassert_ok(rt1718s_tcpm_drv.set_vconn(tcpm_rt1718s_port, false));
+	/* Vconn RVP should be disabled. */
+	compare_reg_val_with_mask(rt1718s_emul, RT1718S_VCONN_CONTROL_2, 0,
+				  RT1718S_VCONN_CONTROL_2_RVP_EN);
+}
+
+ZTEST(rt1718s_tcpc, test_enter_low_power_mode)
+{
+	zassert_ok(rt1718s_tcpm_drv.enter_low_power_mode(tcpm_rt1718s_port));
+	compare_reg_val_with_mask(
+		rt1718s_emul, RT1718S_SYS_CTRL2, RT1718S_SYS_CTRL2_LPWR_EN,
+		RT1718S_SYS_CTRL2_LPWR_EN | RT1718S_SYS_CTRL2_BMCIO_OSC_EN);
+	compare_reg_val_with_mask(rt1718s_emul, RT1718S_RT2_SBU_CTRL_01, 0,
+				  0xFF);
+}
+
+ZTEST(rt1718s_tcpc, test_set_sbu)
+{
+	uint8_t mask = RT1718S_RT2_SBU_CTRL_01_SBU_VIEN |
+		       RT1718S_RT2_SBU_CTRL_01_SBU1_SWEN |
+		       RT1718S_RT2_SBU_CTRL_01_SBU2_SWEN;
+
+	zassert_ok(rt1718s_tcpm_drv.set_sbu(tcpm_rt1718s_port, true));
+	compare_reg_val_with_mask(rt1718s_emul, RT1718S_RT2_SBU_CTRL_01, 0xFF,
+				  mask);
+
+	zassert_ok(rt1718s_tcpm_drv.set_sbu(tcpm_rt1718s_port, false));
+	compare_reg_val_with_mask(rt1718s_emul, RT1718S_RT2_SBU_CTRL_01, 0,
+				  mask);
+}
+
+ZTEST(rt1718s_tcpc, test_set_frs)
+{
+	zassert_ok(rt1718s_tcpm_drv.set_frs_enable(tcpm_rt1718s_port, true));
+	compare_reg_val_with_mask(rt1718s_emul, RT1718S_FRS_CTRL2,
+				  RT1718S_FRS_CTRL2_RX_FRS_EN |
+					  RT1718S_FRS_CTRL2_VBUS_FRS_EN | 0x10,
+				  0xFF);
+	compare_reg_val_with_mask(
+		rt1718s_emul, RT1718S_VBUS_CTRL_EN,
+		RT1718S_VBUS_CTRL_EN_GPIO2_VBUS_PATH_EN |
+			RT1718S_VBUS_CTRL_EN_GPIO1_VBUS_PATH_EN | 0x3F,
+		0xFF);
+
+	zassert_ok(rt1718s_tcpm_drv.set_frs_enable(tcpm_rt1718s_port, false));
+	compare_reg_val_with_mask(rt1718s_emul, RT1718S_FRS_CTRL2, 0x10, 0xFF);
+	compare_reg_val_with_mask(rt1718s_emul, RT1718S_VBUS_CTRL_EN, 0x3F,
+				  0xFF);
+}
+
+ZTEST(rt1718s_tcpc, test_set_snk_ctrl)
+{
+	zassert_ok(rt1718s_tcpm_drv.set_snk_ctrl(tcpm_rt1718s_port, true));
+	compare_reg_val_with_mask(
+		rt1718s_emul, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_HIGH,
+		TCPC_REG_COMMAND_SNK_CTRL_HIGH | TCPC_REG_COMMAND_SNK_CTRL_LOW);
+
+	zassert_ok(rt1718s_tcpm_drv.set_snk_ctrl(tcpm_rt1718s_port, false));
+	compare_reg_val_with_mask(
+		rt1718s_emul, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW,
+		TCPC_REG_COMMAND_SNK_CTRL_HIGH | TCPC_REG_COMMAND_SNK_CTRL_LOW);
+}
diff --git a/zephyr/test/drivers/rt1718s/src/test_common.c b/zephyr/test/drivers/rt1718s/src/test_common.c
new file mode 100644
index 0000000000..23357236ca
--- /dev/null
+++ b/zephyr/test/drivers/rt1718s/src/test_common.c
@@ -0,0 +1,40 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "emul/tcpc/emul_rt1718s.h"
+#include "test/drivers/stubs.h"
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/ztest.h>
+
+#define RT1718S_NODE DT_NODELABEL(rt1718s_emul)
+
+const int tcpm_rt1718s_port = USBC_PORT_C0;
+const struct emul *rt1718s_emul = EMUL_DT_GET(RT1718S_NODE);
+
+void rt1718s_clear_set_reg_history(void *f)
+{
+	rt1718s_emul_reset_set_history(rt1718s_emul);
+}
+
+static uint16_t get_emul_reg(const struct emul *emul, int reg)
+{
+	uint16_t val;
+
+	zassert_ok(rt1718s_emul_get_reg(emul, reg, &val),
+		   "Cannot get reg %x on rt1718s emul", reg);
+	return val;
+}
+
+void compare_reg_val_with_mask(const struct emul *emul, int reg,
+			       uint16_t expected, uint16_t mask)
+{
+	uint16_t masked_val = get_emul_reg(emul, reg) & mask;
+	uint16_t masked_expected = expected & mask;
+
+	zassert_equal(masked_val, masked_expected,
+		      "expected register %x with mask %x should be %x, get %x",
+		      reg, mask, masked_expected, masked_val);
+}
diff --git a/zephyr/test/drivers/rt9490/CMakeLists.txt b/zephyr/test/drivers/rt9490/CMakeLists.txt
new file mode 100644
index 0000000000..441b54ef4c
--- /dev/null
+++ b/zephyr/test/drivers/rt9490/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Add source files
+target_sources(app PRIVATE src/charger.c src/bc12.c)
diff --git a/zephyr/test/drivers/rt9490/charger.dts b/zephyr/test/drivers/rt9490/charger.dts
new file mode 100644
index 0000000000..1714e157f1
--- /dev/null
+++ b/zephyr/test/drivers/rt9490/charger.dts
@@ -0,0 +1,25 @@
+/ {
+	usbc {
+		port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+			chg = <&rt9490>;
+			bc12 = <&rt9490>;
+			tcpc = <&tcpci_emul>;
+		};
+
+		port1@1 {
+			bc12 = <&rt9490>;
+		};
+	};
+};
+
+&i2c0 {
+	status = "okay";
+
+	rt9490: rt9490@53 {
+		compatible = "richtek,rt9490", "zephyr,rt9490-emul";
+		status = "okay";
+		reg = <0x53>;
+	};
+};
diff --git a/zephyr/test/drivers/rt9490/prj.conf b/zephyr/test/drivers/rt9490/prj.conf
new file mode 100644
index 0000000000..1d1b6c4c71
--- /dev/null
+++ b/zephyr/test/drivers/rt9490/prj.conf
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_PLATFORM_EC_BC12_SINGLE_DRIVER=n
+CONFIG_PLATFORM_EC_CHARGER_OTG=y
+CONFIG_PLATFORM_EC_CHARGE_RAMP_HW=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_DUMP=y
+CONFIG_PLATFORM_EC_HOOKS=y
diff --git a/zephyr/test/drivers/rt9490/src/bc12.c b/zephyr/test/drivers/rt9490/src/bc12.c
new file mode 100644
index 0000000000..276ce82f0e
--- /dev/null
+++ b/zephyr/test/drivers/rt9490/src/bc12.c
@@ -0,0 +1,112 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "charger.h"
+#include "driver/charger/rt9490.h"
+#include "driver/tcpm/tcpci.h"
+#include "emul/emul_rt9490.h"
+#include "emul/tcpc/emul_tcpci.h"
+#include "i2c.h"
+#include "test/drivers/test_state.h"
+#include "timer.h"
+#include "usb_charge.h"
+
+#include <zephyr/fff.h>
+#include <zephyr/ztest.h>
+
+FAKE_VALUE_FUNC(int, board_tcpc_post_init, int);
+
+static const struct emul *emul = EMUL_DT_GET(DT_NODELABEL(rt9490));
+static const struct emul *tcpci_emul = EMUL_DT_GET(DT_NODELABEL(tcpci_emul));
+static const int chgnum = CHARGER_SOLO;
+
+static void run_bc12_test(int reg_value, enum charge_supplier expected_result)
+{
+	int port = 0;
+
+	/* simulate plug, expect bc12 detection starting. */
+	zassert_ok(tcpci_emul_set_vbus_level(tcpci_emul, VBUS_PRESENT));
+
+	/* This is the same as calling tcpc_config[port].drv->init(port) but
+	 * also calls our board_tcpc_post_init_fake stub. During the init, the
+	 * other tasks are also running and will at times also call the same
+	 * function. So the verification just checks that the call count
+	 * increased and that the first history element matches the port we
+	 * provided.
+	 */
+	RESET_FAKE(board_tcpc_post_init);
+	zassert_ok(tcpm_init(port));
+	zassert_true(board_tcpc_post_init_fake.call_count > 0);
+	zassert_equal(port, board_tcpc_post_init_fake.arg0_history[0]);
+
+	zassert_true(tcpc_config[port].drv->check_vbus_level(port,
+							     VBUS_PRESENT),
+		     NULL);
+
+	usb_charger_task_set_event(port, USB_CHG_EVENT_VBUS);
+	msleep(1);
+	zassert_true(rt9490_emul_peek_reg(emul, RT9490_REG_CHG_CTRL2) &
+			     RT9490_BC12_EN,
+		     NULL);
+
+	/*
+	 * simulate triggering interrupt on bc12 detection done, and verify the
+	 * result.
+	 */
+	zassert_ok(rt9490_emul_write_reg(emul, RT9490_REG_CHG_IRQ_FLAG1,
+					 RT9490_BC12_DONE_FLAG));
+	zassert_ok(
+		rt9490_emul_write_reg(emul, RT9490_REG_CHG_STATUS1, reg_value));
+	rt9490_interrupt(port);
+	/* wait for deferred task scheduled, this takes longer. */
+	msleep(500);
+	zassert_false(rt9490_emul_peek_reg(emul, RT9490_REG_CHG_CTRL2) &
+			      RT9490_BC12_EN,
+		      NULL);
+	zassert_equal(charge_manager_get_supplier(), expected_result, NULL);
+
+	/* simulate unplug */
+	zassert_ok(tcpci_emul_set_vbus_level(tcpci_emul, VBUS_REMOVED));
+	zassert_ok(tcpc_config[port].drv->init(port), NULL);
+	zassert_false(tcpc_config[port].drv->check_vbus_level(port,
+							      VBUS_PRESENT),
+		      NULL);
+
+	usb_charger_task_set_event(port, USB_CHG_EVENT_VBUS);
+	msleep(1);
+	zassert_equal(charge_manager_get_supplier(), CHARGE_SUPPLIER_NONE,
+		      NULL);
+}
+
+ZTEST(rt9490_bc12, test_detection_flow)
+{
+	int port = 0;
+
+	/* make charge manager thinks port 0 is chargable */
+	msleep(500);
+	usb_charger_task_set_event(port, USB_CHG_EVENT_DR_UFP);
+	charge_manager_update_dualrole(port, CAP_DEDICATED);
+	zassert_equal(charge_manager_get_supplier(), CHARGE_SUPPLIER_NONE,
+		      NULL);
+	msleep(1);
+
+	run_bc12_test(RT9490_DCP << RT9490_VBUS_STAT_SHIFT,
+		      CHARGE_SUPPLIER_BC12_DCP);
+	run_bc12_test(RT9490_CDP << RT9490_VBUS_STAT_SHIFT,
+		      CHARGE_SUPPLIER_BC12_CDP);
+	run_bc12_test(RT9490_SDP << RT9490_VBUS_STAT_SHIFT,
+		      CHARGE_SUPPLIER_BC12_SDP);
+	run_bc12_test(0xA, CHARGE_SUPPLIER_VBUS); /* unknown type */
+}
+
+static void reset_emul(void *fixture)
+{
+	rt9490_emul_reset_regs(emul);
+	rt9490_drv.init(chgnum);
+}
+
+ZTEST_SUITE(rt9490_bc12, drivers_predicate_post_main, NULL, reset_emul, NULL,
+	    NULL);
diff --git a/zephyr/test/drivers/rt9490/src/charger.c b/zephyr/test/drivers/rt9490/src/charger.c
new file mode 100644
index 0000000000..4c08065e09
--- /dev/null
+++ b/zephyr/test/drivers/rt9490/src/charger.c
@@ -0,0 +1,251 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery_smart.h"
+#include "charger.h"
+#include "driver/charger/rt9490.h"
+#include "emul/emul_rt9490.h"
+#include "i2c.h"
+
+#include <zephyr/ztest.h>
+
+static const struct emul *emul = EMUL_DT_GET(DT_NODELABEL(rt9490));
+static const int chgnum = CHARGER_SOLO;
+
+ZTEST(rt9490_chg, test_current)
+{
+	struct {
+		int reg;
+		int expected; /* expected current in mA */
+	} testdata[] = { { 0xF, 150 },	 { 0x10, 160 },	  { 0x64, 1000 },
+			 { 0xC8, 2000 }, { 0x1F3, 4990 }, { 0x1F4, 5000 } };
+
+	for (int i = 0; i < ARRAY_SIZE(testdata); i++) {
+		int current = -1;
+
+		zassert_ok(rt9490_drv.set_current(chgnum, testdata[i].expected),
+			   "case %d failed", i);
+		zassert_equal(rt9490_emul_peek_reg(emul, RT9490_REG_ICHG_CTRL),
+			      testdata[i].reg >> 8, "case %d failed", i);
+		zassert_equal(rt9490_emul_peek_reg(emul,
+						   RT9490_REG_ICHG_CTRL + 1),
+			      testdata[i].reg & 0xFF, "case %d failed", i);
+
+		zassert_ok(rt9490_drv.get_current(chgnum, &current),
+			   "case %d failed", i);
+		zassert_equal(testdata[i].expected, current, "case %d failed",
+			      i);
+	}
+
+	/* special case: set_current(0) means 150mA */
+	zassert_ok(rt9490_drv.set_current(chgnum, 0), NULL);
+	zassert_equal(rt9490_emul_peek_reg(emul, RT9490_REG_ICHG_CTRL), 0,
+		      NULL);
+	zassert_equal(rt9490_emul_peek_reg(emul, RT9490_REG_ICHG_CTRL + 1), 0xF,
+		      NULL);
+
+	/* values outside (150mA, 5000mA) are illegal */
+	zassert_not_equal(rt9490_drv.set_current(chgnum, 140), 0, NULL);
+	zassert_not_equal(rt9490_drv.set_current(chgnum, 5001), 0, NULL);
+}
+
+ZTEST(rt9490_chg, test_voltage)
+{
+	struct {
+		int reg;
+		int expected; /* expected voltage in mV */
+	} testdata[] = { { 0x12C, 3000 },  { 0x12D, 3010 },  { 0x12E, 3020 },
+			 { 0x1A4, 4200 },  { 0x348, 8400 },  { 0x4EC, 12600 },
+			 { 0x690, 16800 }, { 0x757, 18790 }, { 0x758, 18800 } };
+
+	for (int i = 0; i < ARRAY_SIZE(testdata); i++) {
+		int voltage = -1;
+
+		zassert_ok(rt9490_drv.set_voltage(chgnum, testdata[i].expected),
+			   "case %d failed", i);
+		zassert_equal(rt9490_emul_peek_reg(emul, RT9490_REG_VCHG_CTRL),
+			      testdata[i].reg >> 8, "case %d failed", i);
+		zassert_equal(rt9490_emul_peek_reg(emul,
+						   RT9490_REG_VCHG_CTRL + 1),
+			      testdata[i].reg & 0xFF, "case %d failed", i);
+
+		zassert_ok(rt9490_drv.get_voltage(chgnum, &voltage),
+			   "case %d failed", i);
+		zassert_equal(testdata[i].expected, voltage, "case %d failed",
+			      i);
+	}
+
+	/* special case: set_voltage(0) means 3.0V */
+	zassert_ok(rt9490_drv.set_voltage(chgnum, 0), NULL);
+	zassert_equal(rt9490_emul_peek_reg(emul, RT9490_REG_VCHG_CTRL), 0x1,
+		      NULL);
+	zassert_equal(rt9490_emul_peek_reg(emul, RT9490_REG_VCHG_CTRL + 1),
+		      0x2C, NULL);
+
+	/* values outside (3V, 18.8V) are illegal */
+	zassert_not_equal(rt9490_drv.set_voltage(chgnum, 2999), 0, NULL);
+	zassert_not_equal(rt9490_drv.set_voltage(chgnum, 18801), 0, NULL);
+}
+
+ZTEST(rt9490_chg, test_otg)
+{
+	struct {
+		int reg_v, reg_c, expected_v, expected_c;
+	} testdata[] = { { 0x0, 0x3, 2800, 120 },
+			 { 0x1, 0x4, 2810, 160 },
+			 { 0xDC, 0x4B, 5000, 3000 },
+			 { 0x77F, 0x52, 21990, 3280 },
+			 { 0x780, 0x53, 22000, 3320 } };
+
+	for (int i = 0; i < ARRAY_SIZE(testdata); i++) {
+		zassert_ok(rt9490_drv.set_otg_current_voltage(
+				   chgnum, testdata[i].expected_c,
+				   testdata[i].expected_v),
+			   "case %d failed", i);
+		zassert_equal(rt9490_emul_peek_reg(emul, RT9490_REG_VOTG_REGU),
+			      testdata[i].reg_v >> 8, "case %d failed", i);
+		zassert_equal(rt9490_emul_peek_reg(emul,
+						   RT9490_REG_VOTG_REGU + 1),
+			      testdata[i].reg_v & 0xFF, "case %d failed", i);
+		zassert_equal(rt9490_emul_peek_reg(emul, RT9490_REG_IOTG_REGU),
+			      testdata[i].reg_c, "case %d failed", i);
+		break;
+	}
+
+	/* check out-of-range inputs */
+	zassert_not_equal(rt9490_drv.set_otg_current_voltage(chgnum, 119, 5000),
+			  0, NULL);
+	zassert_not_equal(rt9490_drv.set_otg_current_voltage(chgnum, 3330,
+							     5000),
+			  0, NULL);
+	zassert_not_equal(rt9490_drv.set_otg_current_voltage(chgnum, 3000,
+							     2700),
+			  0, NULL);
+	zassert_not_equal(rt9490_drv.set_otg_current_voltage(chgnum, 3000,
+							     23000),
+			  0, NULL);
+
+	/* check enable/disable functions */
+	zassert_equal(rt9490_drv.enable_otg_power(chgnum, true), 0, NULL);
+	zassert_equal(rt9490_drv.is_sourcing_otg_power(chgnum, 0), true, NULL);
+	zassert_equal(rt9490_drv.enable_otg_power(chgnum, false), 0, NULL);
+	zassert_equal(rt9490_drv.is_sourcing_otg_power(chgnum, 0), false, NULL);
+}
+
+ZTEST(rt9490_chg, test_aicr)
+{
+	struct {
+		int reg;
+		int expected; /* expected current in mA */
+	} testdata[] = { { 0xA, 100 },
+			 { 0xB, 110 },
+			 { 0x32, 500 },
+			 { 0x12C, 3000 },
+			 { 0x14A, 3300 } };
+	int current = -1;
+
+	for (int i = 0; i < ARRAY_SIZE(testdata); i++) {
+		zassert_ok(rt9490_drv.set_input_current_limit(
+
+				   chgnum, testdata[i].expected),
+			   "case %d failed", i);
+		zassert_equal(rt9490_emul_peek_reg(emul, RT9490_REG_AICR_CTRL),
+			      testdata[i].reg >> 8, "case %d failed", i);
+		zassert_equal(rt9490_emul_peek_reg(emul,
+						   RT9490_REG_AICR_CTRL + 1),
+			      testdata[i].reg & 0xFF, "case %d failed", i);
+
+		zassert_ok(rt9490_drv.get_input_current_limit(chgnum, &current),
+			   "case %d failed", i);
+		zassert_equal(testdata[i].expected, current, "case %d failed",
+			      i);
+	}
+
+	/*
+	 * test values outside the designed range.
+	 * returns 100mA if input < 100mA, and 3300mA if greater than 3300mA.
+	 */
+	zassert_ok(rt9490_drv.set_input_current_limit(chgnum, 90), NULL);
+	zassert_ok(rt9490_drv.get_input_current_limit(chgnum, &current), "");
+	zassert_equal(100, current, "");
+
+	zassert_ok(rt9490_drv.set_input_current_limit(chgnum, 3400), NULL);
+	zassert_ok(rt9490_drv.get_input_current_limit(chgnum, &current), "");
+	zassert_equal(3300, current, "");
+}
+
+ZTEST(rt9490_chg, test_charge_ramp_hw_ramp)
+{
+	zassert_ok(rt9490_drv.set_hw_ramp(chgnum, 1), NULL);
+	zassert_true(rt9490_emul_peek_reg(emul, RT9490_REG_CHG_CTRL0) &
+			     RT9490_EN_AICC,
+		     NULL);
+
+	zassert_ok(rt9490_drv.ramp_is_stable(chgnum), NULL);
+	zassert_true(rt9490_drv.ramp_is_detected(chgnum), NULL);
+
+	zassert_ok(rt9490_drv.set_input_current_limit(chgnum, 500), NULL);
+	zassert_equal(500, rt9490_drv.ramp_get_current_limit(chgnum), NULL);
+
+	zassert_ok(rt9490_drv.set_hw_ramp(chgnum, 0), NULL);
+	zassert_false(rt9490_emul_peek_reg(emul, RT9490_REG_CHG_CTRL0) &
+			      RT9490_EN_AICC,
+		      NULL);
+}
+
+ZTEST(rt9490_chg, test_option)
+{
+	int opt;
+
+	zassert_ok(rt9490_drv.get_option(CHARGER_NUM, &opt), NULL);
+	zassert_true(opt == 0, NULL);
+	zassert_ok(rt9490_drv.set_option(CHARGER_NUM, 5566), NULL);
+	zassert_ok(rt9490_drv.get_option(CHARGER_NUM, &opt), NULL);
+	zassert_true(opt == 0, NULL);
+}
+
+ZTEST(rt9490_chg, test_misc_info)
+{
+	int status;
+	int device_id;
+
+	rt9490_drv.dump_registers(chgnum);
+
+	zassert_ok(rt9490_drv.device_id(chgnum, &device_id), NULL);
+	zassert_equal((device_id >> 3) & 0xF, 0xC, NULL);
+
+	zassert_ok(rt9490_drv.get_status(chgnum, &status), NULL);
+	zassert_equal(status, 0, NULL);
+
+	/* check the mapping from jeita status to smart battery charger status
+	 */
+	zassert_ok(rt9490_emul_write_reg(emul, RT9490_REG_CHG_STATUS4,
+					 RT9490_JEITA_HOT_MASK));
+	zassert_ok(rt9490_drv.get_status(chgnum, &status), NULL);
+	zassert_equal(status, CHARGER_RES_HOT | CHARGER_RES_OR, NULL);
+
+	zassert_ok(rt9490_emul_write_reg(emul, RT9490_REG_CHG_STATUS4,
+					 RT9490_JEITA_WARM_MASK));
+	zassert_ok(rt9490_drv.get_status(chgnum, &status), NULL);
+	zassert_equal(status, CHARGER_RES_HOT, NULL);
+
+	zassert_ok(rt9490_emul_write_reg(emul, RT9490_REG_CHG_STATUS4,
+					 RT9490_JEITA_COOL_MASK));
+	zassert_ok(rt9490_drv.get_status(chgnum, &status), NULL);
+	zassert_equal(status, CHARGER_RES_COLD, NULL);
+
+	zassert_ok(rt9490_emul_write_reg(emul, RT9490_REG_CHG_STATUS4,
+					 RT9490_JEITA_COLD_MASK));
+	zassert_ok(rt9490_drv.get_status(chgnum, &status), NULL);
+	zassert_equal(status, CHARGER_RES_COLD | CHARGER_RES_UR, NULL);
+}
+
+static void reset_emul(void *fixture)
+{
+	rt9490_emul_reset_regs(emul);
+	rt9490_drv.init(chgnum);
+}
+
+ZTEST_SUITE(rt9490_chg, NULL, NULL, reset_emul, NULL, NULL);
diff --git a/zephyr/test/drivers/shim_gpio_id/CMakeLists.txt b/zephyr/test/drivers/shim_gpio_id/CMakeLists.txt
new file mode 100644
index 0000000000..c839d92734
--- /dev/null
+++ b/zephyr/test/drivers/shim_gpio_id/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Add source files
+target_sources(app PRIVATE src/test_shim_gpio_id.c)
diff --git a/zephyr/test/drivers/shim_gpio_id/gpio_id.dts b/zephyr/test/drivers/shim_gpio_id/gpio_id.dts
new file mode 100644
index 0000000000..cd2303cfa9
--- /dev/null
+++ b/zephyr/test/drivers/shim_gpio_id/gpio_id.dts
@@ -0,0 +1,20 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	/* Required to compile board_get_sku_id() from shim/gpio_id.c */
+	gpio_id_sku: sku {
+		compatible = "cros-ec,gpio-id";
+		bits  = <&gpio_sku_id0>;
+		system = "ternary";
+	};
+
+	/* Required to compile board_get_version() from shim/gpio_id.c */
+	gpio_id_board: board {
+		compatible = "cros-ec,gpio-id";
+		bits  = <&gpio_brd_id0>;
+		system = "ternary";
+	};
+};
diff --git a/zephyr/test/drivers/shim_gpio_id/src/test_shim_gpio_id.c b/zephyr/test/drivers/shim_gpio_id/src/test_shim_gpio_id.c
new file mode 100644
index 0000000000..5e9381c2a5
--- /dev/null
+++ b/zephyr/test/drivers/shim_gpio_id/src/test_shim_gpio_id.c
@@ -0,0 +1,39 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "system.h"
+#include "test/drivers/test_state.h"
+#include "util.h"
+
+#include <zephyr/ztest.h>
+
+/*
+ * TODO(b/254924012): Test alternative GPIO when emulated gpio tristate is
+ * supported upstream.
+ */
+
+ZTEST(gpio_id, test_board_get_sku_id__default_value)
+{
+	int bits[] = {
+		/* Default Hi-Z value */
+		2,
+	};
+
+	zassert_equal(board_get_sku_id(),
+		      ternary_from_bits(bits, ARRAY_SIZE(bits)));
+}
+
+ZTEST(gpio_id, test_board_get_version__default_value)
+{
+	int bits[] = {
+		/* Default Hi-Z value */
+		2,
+	};
+
+	zassert_equal(board_get_version(),
+		      ternary_from_bits(bits, ARRAY_SIZE(bits)));
+}
+
+ZTEST_SUITE(gpio_id, drivers_predicate_post_main, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/drivers/shim_pwm_hc/CMakeLists.txt b/zephyr/test/drivers/shim_pwm_hc/CMakeLists.txt
new file mode 100644
index 0000000000..d20d965d2d
--- /dev/null
+++ b/zephyr/test/drivers/shim_pwm_hc/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Add source files
+target_sources(app PRIVATE src/test_shim_pwm_hc.c)
diff --git a/zephyr/test/drivers/shim_pwm_hc/src/test_shim_pwm_hc.c b/zephyr/test/drivers/shim_pwm_hc/src/test_shim_pwm_hc.c
new file mode 100644
index 0000000000..ac8c88adbe
--- /dev/null
+++ b/zephyr/test/drivers/shim_pwm_hc/src/test_shim_pwm_hc.c
@@ -0,0 +1,93 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "drivers/cros_displight.h"
+#include "ec_commands.h"
+#include "host_command.h"
+#include "keyboard_backlight.h"
+#include "pwm.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/i2c_emul.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+#include <zephyr/ztest_assert.h>
+
+ZTEST(shim_pwm_hc, test_pwm_set_duty_hc__kblight)
+{
+	struct ec_params_pwm_set_duty p = {
+		.index = DT_REG_ADDR(DT_NODELABEL(pwm_kblight)),
+		.pwm_type = EC_PWM_TYPE_KB_LIGHT,
+		/* Arbitrary 56% */
+		.duty = PWM_PERCENT_TO_RAW(56),
+	};
+
+	zassert_ok(ec_cmd_pwm_set_duty(NULL, &p));
+	zassert_equal(kblight_get(), PWM_RAW_TO_PERCENT(p.duty));
+}
+
+ZTEST(shim_pwm_hc, test_pwm_set_duty_hc__displight)
+{
+	struct ec_params_pwm_set_duty p = {
+		.index = DT_REG_ADDR(DT_NODELABEL(pwm_displight)),
+		.pwm_type = EC_PWM_TYPE_DISPLAY_LIGHT,
+		/* Arbitrary 72% */
+		.duty = PWM_PERCENT_TO_RAW(72)
+	};
+
+	zassert_ok(ec_cmd_pwm_set_duty(NULL, &p));
+	zassert_equal(displight_get(), PWM_RAW_TO_PERCENT(p.duty));
+}
+
+ZTEST(shim_pwm_hc, test_pwm_set_duty_hc__bad_pwm_type)
+{
+	struct ec_params_pwm_set_duty p = {
+		/* Arbitrary, don't care */
+		p.index = 0,
+		/* PWM Type doesn't actually exist */
+		p.pwm_type = EC_PWM_TYPE_COUNT,
+	};
+
+	zassert_equal(EC_RES_INVALID_PARAM, ec_cmd_pwm_set_duty(NULL, &p));
+}
+
+ZTEST(shim_pwm_hc, test_pwm_get_duty_hc__kblight)
+{
+	struct ec_params_pwm_get_duty p = {
+		.index = DT_REG_ADDR(DT_NODELABEL(pwm_kblight)),
+		.pwm_type = EC_PWM_TYPE_KB_LIGHT,
+	};
+
+	struct ec_response_pwm_get_duty r;
+	struct host_cmd_handler_args args;
+
+	/* Set kblight percentage to arbitrary 56% */
+	kblight_set(56);
+
+	zassert_ok(ec_cmd_pwm_get_duty(&args, &p, &r));
+	zassert_equal(args.response_size, sizeof(r));
+	zassert_equal(r.duty, PWM_PERCENT_TO_RAW(56));
+}
+
+ZTEST(shim_pwm_hc, test_pwm_get_duty_hc__displight)
+{
+	struct ec_params_pwm_get_duty p = {
+		p.index = DT_REG_ADDR(DT_NODELABEL(pwm_displight)),
+		p.pwm_type = EC_PWM_TYPE_DISPLAY_LIGHT,
+	};
+
+	struct ec_response_pwm_get_duty r;
+	struct host_cmd_handler_args args;
+
+	/* Set displight percentage to arbitrary 72% */
+	displight_set(72);
+
+	zassert_ok(ec_cmd_pwm_get_duty(&args, &p, &r));
+	zassert_equal(args.response_size, sizeof(r));
+	zassert_equal(r.duty, PWM_PERCENT_TO_RAW(72));
+}
+
+ZTEST_SUITE(shim_pwm_hc, drivers_predicate_post_main, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/drivers/shim_rtc/CMakeLists.txt b/zephyr/test/drivers/shim_rtc/CMakeLists.txt
new file mode 100644
index 0000000000..e0f5f2de41
--- /dev/null
+++ b/zephyr/test/drivers/shim_rtc/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Add source files
+target_sources(app PRIVATE src/test_shim_rtc.c)
diff --git a/zephyr/test/drivers/shim_rtc/src/test_shim_rtc.c b/zephyr/test/drivers/shim_rtc/src/test_shim_rtc.c
new file mode 100644
index 0000000000..432ad1d4f4
--- /dev/null
+++ b/zephyr/test/drivers/shim_rtc/src/test_shim_rtc.c
@@ -0,0 +1,97 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+#include "host_command.h"
+#include "lpc.h"
+#include "system.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/drivers/i2c_emul.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+#include <zephyr/ztest_assert.h>
+
+ZTEST_USER(rtc_shim, test_hc_rtc_set_get_value)
+{
+	struct ec_params_rtc set_value;
+	struct ec_response_rtc get_value;
+
+	/* Initially set/get arbitrary value */
+	set_value.time = 1337;
+	zassert_ok(ec_cmd_rtc_set_value(NULL, &set_value));
+	zassert_ok(ec_cmd_rtc_get_value(NULL, &get_value));
+	zassert_equal(get_value.time, set_value.time);
+
+	/* One more time to be sure the test is creating the value change */
+	set_value.time = 1776;
+	zassert_ok(ec_cmd_rtc_set_value(NULL, &set_value));
+	zassert_ok(ec_cmd_rtc_get_value(NULL, &get_value));
+	zassert_equal(get_value.time, set_value.time);
+}
+
+ZTEST_USER(rtc_shim, test_hc_rtc_set_get_alarm)
+{
+	struct ec_params_rtc set_value;
+	struct ec_response_rtc get_value;
+
+	/* Initially set/get zero value */
+	set_value.time = 0;
+	zassert_ok(ec_cmd_rtc_set_alarm(NULL, &set_value));
+	zassert_ok(ec_cmd_rtc_get_alarm(NULL, &get_value));
+	zassert_equal(get_value.time, set_value.time);
+
+	/* One more time to be sure the test is creating the value change */
+	set_value.time = 1776;
+	zassert_ok(ec_cmd_rtc_set_alarm(NULL, &set_value));
+	zassert_ok(ec_cmd_rtc_get_alarm(NULL, &get_value));
+	/*
+	 * The RTC driver adds 1 second to the alarm time to compensate for
+	 * truncation error. For example, 7 seconds is returned when the
+	 * actual time is 7.9 seconds. "get_value.time - 1" removes the
+	 * additional seconded for this test.
+	 */
+	zassert_equal(get_value.time - 1, set_value.time);
+}
+
+ZTEST(rtc_shim, test_hc_rtc_set_alarm_can_fire_cb)
+{
+	struct ec_params_rtc set_value;
+
+#ifdef CONFIG_HOSTCMD_X86
+	/* Enable the RTC event to fire */
+	host_event_t lpc_event_mask;
+	host_event_t mask = EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC);
+
+	lpc_event_mask = lpc_get_host_event_mask(LPC_HOST_EVENT_SMI);
+	lpc_set_host_event_mask(LPC_HOST_EVENT_SMI, lpc_event_mask | mask);
+#endif
+
+	/* Arbitrary value of 2 */
+	system_set_rtc(2);
+
+	/* Clear events so we can check that RTC event happened */
+	host_clear_events(CONFIG_HOST_EVENT_REPORT_MASK);
+	zassert_false(host_is_event_set(EC_HOST_EVENT_RTC));
+
+	/* Initially set arbitrary value of alarm in 2 seconds*/
+	set_value.time = 2;
+	zassert_ok(ec_cmd_rtc_set_alarm(NULL, &set_value));
+	/* Set fake driver time forward to hit the alarm in 2 seconds */
+
+	/*
+	 * The RTC driver adds 1 second to the alarm time to compensate for
+	 * truncation error. For example, 7 seconds is returned when the
+	 * actual time is 7.9 seconds. So, RTC seconds is set to 5 instead
+	 * of 4.
+	 */
+	system_set_rtc(5);
+
+	/* Wait for irq to finish */
+	k_sleep(K_SECONDS(1));
+	zassert_true(host_is_event_set(EC_HOST_EVENT_RTC));
+}
+
+ZTEST_SUITE(rtc_shim, drivers_predicate_post_main, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/drivers/sm5803/CMakeLists.txt b/zephyr/test/drivers/sm5803/CMakeLists.txt
new file mode 100644
index 0000000000..f7dfa41b4c
--- /dev/null
+++ b/zephyr/test/drivers/sm5803/CMakeLists.txt
@@ -0,0 +1,5 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_sources(app PRIVATE src/sm5803.c src/usbc.c)
diff --git a/zephyr/test/drivers/sm5803/prj.conf b/zephyr/test/drivers/sm5803/prj.conf
new file mode 100644
index 0000000000..88fc64bc9e
--- /dev/null
+++ b/zephyr/test/drivers/sm5803/prj.conf
@@ -0,0 +1,10 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_PLATFORM_EC_CHARGER_SM5803=y
+CONFIG_PLATFORM_EC_CHARGER_ISL9238=n
+CONFIG_PLATFORM_EC_PD_MAX_VOLTAGE_MV=15000
+CONFIG_PLATFORM_EC_OCPC=y
+CONFIG_PLATFORM_EC_OCPC_DEF_RBATT_MOHMS=20
+CONFIG_PLATFORM_EC_THROTTLE_AP=y
\ No newline at end of file
diff --git a/zephyr/test/drivers/sm5803/sm5803.dts b/zephyr/test/drivers/sm5803/sm5803.dts
new file mode 100644
index 0000000000..32c4cd342c
--- /dev/null
+++ b/zephyr/test/drivers/sm5803/sm5803.dts
@@ -0,0 +1,49 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	usbc {
+		port0@0 {
+			compatible = "named-usbc-port";
+			chg = <&sm5803_emul>;
+		};
+
+		port1@1 {
+		  compatible = "named-usbc-port";
+		  chg = <&sm5803_emul_secondary>;
+		};
+	};
+
+	gpio2: gpio@2000 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0x2000 0x4>;
+		falling-edge;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <1>;
+	};
+};
+
+&i2c0 {
+	sm5803_emul: sm5803@32 {
+		compatible = "cros,sm5803-emul", "siliconmitus,sm5803";
+		status = "okay";
+		reg = <0x32>;
+		interrupt-gpios = <&gpio2 0 (GPIO_ACTIVE_LOW)>;
+	};
+};
+
+&i2c1 {
+  sm5803_emul_secondary: sm5803-secondary@32 {
+		compatible = "cros,sm5803-emul", "siliconmitus,sm5803";
+		status = "okay";
+		reg = <0x32>;
+	};
+};
+
+&default_battery {
+	ship_mode_reg_data = <0x2000>;
+};
diff --git a/zephyr/test/drivers/sm5803/src/sm5803.c b/zephyr/test/drivers/sm5803/src/sm5803.c
new file mode 100644
index 0000000000..721653e9a2
--- /dev/null
+++ b/zephyr/test/drivers/sm5803/src/sm5803.c
@@ -0,0 +1,1521 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "battery_smart.h"
+#include "charger.h"
+#include "driver/charger/sm5803.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_sm5803.h"
+#include "emul/tcpc/emul_tcpci_partner_snk.h"
+#include "emul/tcpc/emul_tcpci_partner_src.h"
+#include "hooks.h"
+#include "tcpm/tcpci.h"
+#include "test/drivers/charger_utils.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/fff.h>
+#include <zephyr/ztest.h>
+
+struct sm5803_fixture {
+	const struct emul *tcpci_emul;
+	struct tcpci_partner_data partner;
+	struct tcpci_src_emul_data src_ext;
+	struct tcpci_snk_emul_data snk_ext;
+};
+
+static void pd_connect_source(struct sm5803_fixture *fixture);
+static void pd_disconnect(struct sm5803_fixture *fixture);
+
+LOG_MODULE_REGISTER(sm5803_driver_test, LOG_LEVEL_INF);
+
+static void *sm5803_test_setup(void);
+static void sm5803_before_test(void *fixture);
+static void sm5803_after_test(void *fixture);
+
+ZTEST_SUITE(sm5803, drivers_predicate_post_main, sm5803_test_setup,
+	    sm5803_before_test, sm5803_after_test, NULL);
+
+ZTEST(sm5803, test_sensible_ocpc_configuration)
+{
+	/*
+	 * A lot of OCPC-related code assumes there are exactly two chargers,
+	 * with IDs 0 and 1. Verify that this test's configuration yields
+	 * compatible configuration, since the driver contains some OCPC-related
+	 * code that we want to test.
+	 */
+	zassert_equal(chg_chips[CHARGER_PRIMARY].drv, &sm5803_drv);
+	zassert_equal(chg_chips[CHARGER_SECONDARY].drv, &sm5803_drv);
+}
+
+#define CHARGER_NUM CHARGER_PRIMARY
+#define SM5803_EMUL EMUL_DT_GET(DT_NODELABEL(sm5803_emul))
+#define SM5803_EMUL_SECONDARY EMUL_DT_GET(DT_NODELABEL(sm5803_emul_secondary))
+
+ZTEST(sm5803, test_chip_id)
+{
+	int id;
+
+	/* Emulator only implements chip revision 3. */
+	zassert_ok(sm5803_drv.device_id(CHARGER_NUM, &id));
+	zassert_equal(id, 3);
+
+	/* After a successful read, the value is cached. */
+	i2c_common_emul_set_read_fail_reg(sm5803_emul_get_i2c_main(SM5803_EMUL),
+					  SM5803_REG_CHIP_ID);
+	zassert_ok(sm5803_drv.device_id(CHARGER_NUM, &id));
+}
+
+struct i2c_log_entry {
+	bool write;
+	uint8_t i2c_addr;
+	uint8_t reg_addr;
+	uint8_t value;
+};
+
+struct i2c_log {
+	struct i2c_log_entry entries[128];
+	size_t entries_used;
+	size_t entries_asserted;
+};
+
+#define LOG_ASSERT(_write, _i2c_addr, _reg_addr, _value)                    \
+	do {                                                                \
+		zassert_true(log_ptr->entries_asserted <                    \
+				     log_ptr->entries_used,                 \
+			     "No more I2C transactions to verify "          \
+			     "(logged %d)",                                 \
+			     log_ptr->entries_used);                        \
+		size_t i = log_ptr->entries_asserted++;                     \
+		struct i2c_log_entry *entry = &log_ptr->entries[i];         \
+                                                                            \
+		zassert(entry->write == _write &&                           \
+				entry->i2c_addr == _i2c_addr &&             \
+				entry->reg_addr == _reg_addr &&             \
+				(!_write || entry->value == _value),        \
+			"I2C log mismatch",                                 \
+			"Transaction %d did not match expectations:\n"      \
+			"expected %5s of address %#04x register"            \
+			" %#04x with value %#04x\n"                         \
+			"   found %s of address %#04x register"             \
+			" %#04x with value %#04x",                          \
+			i, _write ? "write" : "read", _i2c_addr, _reg_addr, \
+			_value, entry->write ? "write" : "read",            \
+			entry->i2c_addr, entry->reg_addr, entry->value);    \
+	} while (0)
+
+#define LOG_ASSERT_R(_i2c_addr, _reg_addr) \
+	LOG_ASSERT(false, _i2c_addr, _reg_addr, 0)
+#define LOG_ASSERT_W(_i2c_addr, _reg_addr, _value) \
+	LOG_ASSERT(true, _i2c_addr, _reg_addr, _value)
+#define LOG_ASSERT_RW(_i2c_addr, _reg_addr, _value)         \
+	do {                                                \
+		LOG_ASSERT_R(_i2c_addr, _reg_addr);         \
+		LOG_ASSERT_W(_i2c_addr, _reg_addr, _value); \
+	} while (0)
+
+/*
+ * Generate a function for each I2C address to log the correct address, because
+ * the target pointer is the same for each I2C address and there's no way to
+ * determine from parameters what address we're meant to be.
+ */
+#define DEFINE_LOG_FNS(name, addr)                                          \
+	static int i2c_log_write_##name(const struct emul *target, int reg, \
+					uint8_t val, int bytes, void *ctx)  \
+	{                                                                   \
+		struct i2c_log *log = ctx;                                  \
+                                                                            \
+		if (log->entries_used >= ARRAY_SIZE(log->entries)) {        \
+			LOG_ERR("No space to log I2C write to " #name       \
+				" page");                                   \
+			return -ENOSPC;                                     \
+		}                                                           \
+                                                                            \
+		zassert_equal(target->bus_type, EMUL_BUS_TYPE_I2C);         \
+		log->entries[log->entries_used++] = (struct i2c_log_entry){ \
+			.write = true,                                      \
+			.i2c_addr = addr,                                   \
+			.reg_addr = reg,                                    \
+			.value = val,                                       \
+		};                                                          \
+                                                                            \
+		/* Discard write. */                                        \
+		return 0;                                                   \
+	}                                                                   \
+                                                                            \
+	static int i2c_log_read_##name(const struct emul *target, int reg,  \
+				       uint8_t *val, int bytes, void *ctx)  \
+	{                                                                   \
+		struct i2c_log *log = ctx;                                  \
+                                                                            \
+		if (log->entries_used >= ARRAY_SIZE(log->entries)) {        \
+			LOG_ERR("No space to log I2C read from " #name      \
+				" page");                                   \
+			return -ENOSPC;                                     \
+		}                                                           \
+                                                                            \
+		zassert_equal(target->bus_type, EMUL_BUS_TYPE_I2C);         \
+		log->entries[log->entries_used++] = (struct i2c_log_entry){ \
+			.write = false,                                     \
+			.i2c_addr = addr,                                   \
+			.reg_addr = reg,                                    \
+		};                                                          \
+                                                                            \
+		/* Fall through to emulator read. */                        \
+		return 1;                                                   \
+	}
+
+DEFINE_LOG_FNS(main, SM5803_ADDR_MAIN_FLAGS);
+DEFINE_LOG_FNS(meas, SM5803_ADDR_MEAS_FLAGS);
+DEFINE_LOG_FNS(chg, SM5803_ADDR_CHARGER_FLAGS);
+DEFINE_LOG_FNS(test, SM5803_ADDR_TEST_FLAGS);
+
+static void configure_i2c_log(const struct emul *emul, struct i2c_log *log)
+{
+	i2c_common_emul_set_read_func(sm5803_emul_get_i2c_main(emul),
+				      i2c_log_read_main, log);
+	i2c_common_emul_set_write_func(sm5803_emul_get_i2c_main(emul),
+				       i2c_log_write_main, log);
+	i2c_common_emul_set_read_func(sm5803_emul_get_i2c_meas(emul),
+				      i2c_log_read_meas, log);
+	i2c_common_emul_set_write_func(sm5803_emul_get_i2c_meas(emul),
+				       i2c_log_write_meas, log);
+	i2c_common_emul_set_read_func(sm5803_emul_get_i2c_chg(emul),
+				      i2c_log_read_chg, log);
+	i2c_common_emul_set_write_func(sm5803_emul_get_i2c_chg(emul),
+				       i2c_log_write_chg, log);
+	i2c_common_emul_set_read_func(sm5803_emul_get_i2c_test(emul),
+				      i2c_log_read_test, log);
+	i2c_common_emul_set_write_func(sm5803_emul_get_i2c_test(emul),
+				       i2c_log_write_test, log);
+}
+
+static void verify_init_common(struct i2c_log *const log_ptr)
+{
+	/* Enable LDOs */
+	LOG_ASSERT_RW(SM5803_ADDR_MAIN_FLAGS, SM5803_REG_REFERENCE, 0);
+	/* Psys DAC */
+	LOG_ASSERT_RW(SM5803_ADDR_MEAS_FLAGS, SM5803_REG_PSYS1, 0x05);
+	/* ADC sigma delta */
+	LOG_ASSERT_RW(SM5803_ADDR_CHARGER_FLAGS, SM5803_REG_CC_CONFIG1, 0x09);
+	/* PROCHOT comparators */
+	LOG_ASSERT_RW(SM5803_ADDR_CHARGER_FLAGS, SM5803_REG_PHOT1, 0x2d);
+	/* DPM voltage */
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, SM5803_REG_DPM_VL_SET_MSB,
+		     0x12);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, SM5803_REG_DPM_VL_SET_LSB,
+		     0x04);
+	/* Default input current limit */
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, SM5803_REG_CHG_ILIM, 0x05);
+	/* Interrupts */
+	LOG_ASSERT_W(SM5803_ADDR_MAIN_FLAGS, SM5803_REG_INT1_EN, 0x04);
+	LOG_ASSERT_W(SM5803_ADDR_MAIN_FLAGS, SM5803_REG_INT4_EN, 0x13);
+	LOG_ASSERT_W(SM5803_ADDR_MEAS_FLAGS, SM5803_REG_TINT_HIGH_TH, 0xd1);
+	LOG_ASSERT_W(SM5803_ADDR_MEAS_FLAGS, SM5803_REG_TINT_LOW_TH, 0);
+	LOG_ASSERT_RW(SM5803_ADDR_MAIN_FLAGS, SM5803_REG_INT2_EN, 0x81);
+	/* Charging is exclusively EC-controlled */
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, SM5803_REG_FLOW2, 0x40);
+	/* Battery parameters */
+	LOG_ASSERT_RW(SM5803_ADDR_CHARGER_FLAGS, SM5803_REG_FAST_CONF5, 0x02);
+	LOG_ASSERT_RW(SM5803_ADDR_CHARGER_FLAGS, SM5803_REG_PRE_FAST_CONF_REG1,
+		      0);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, SM5803_REG_PRECHG, 0x02);
+	/* BFET limits */
+	LOG_ASSERT_W(SM5803_ADDR_MEAS_FLAGS, SM5803_REG_BFET_PWR_MAX_TH, 0x33);
+	LOG_ASSERT_W(SM5803_ADDR_MEAS_FLAGS, SM5803_REG_BFET_PWR_HWSAFE_MAX_TH,
+		     0xcd);
+	LOG_ASSERT_RW(SM5803_ADDR_MAIN_FLAGS, SM5803_REG_INT3_EN, 0x06);
+	LOG_ASSERT_RW(SM5803_ADDR_CHARGER_FLAGS, SM5803_REG_FLOW3, 0);
+	LOG_ASSERT_RW(SM5803_ADDR_CHARGER_FLAGS, SM5803_REG_SWITCHER_CONF,
+		      0x01);
+}
+
+/**
+ * Driver internal "init completed" flag needs to be cleared to actually run
+ * init.
+ */
+extern bool chip_inited[2];
+/** Driver internal cached value of chip device ID. */
+extern int dev_id;
+
+ZTEST(sm5803, test_init_2s)
+{
+	struct i2c_log log = {};
+	struct i2c_log *const log_ptr = &log;
+
+	/* Hook up logging functions for each I2C address. */
+	configure_i2c_log(SM5803_EMUL, &log);
+
+	/* Emulator defaults to 2S PMODE so we don't need to set it. */
+	chip_inited[0] = false;
+	sm5803_drv.init(CHARGER_NUM);
+	sm5803_drv.post_init(CHARGER_NUM);
+
+	/* Ensures we're in a safe state for operation. */
+	LOG_ASSERT_R(SM5803_ADDR_MAIN_FLAGS, SM5803_REG_CLOCK_SEL);
+	LOG_ASSERT_W(SM5803_ADDR_MEAS_FLAGS, SM5803_REG_GPADC_CONFIG1, 0xf7);
+	/* Checks VBUS presence and disables charger. */
+	LOG_ASSERT_R(SM5803_ADDR_MEAS_FLAGS, SM5803_REG_GPADC_CONFIG1);
+	LOG_ASSERT_R(SM5803_ADDR_MEAS_FLAGS, SM5803_REG_VBUS_MEAS_MSB);
+	LOG_ASSERT_R(SM5803_ADDR_MEAS_FLAGS, SM5803_REG_VBUS_MEAS_LSB);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, SM5803_REG_FLOW1, 0);
+	/* Gets chip ID (already cached) and PMODE. */
+	LOG_ASSERT_R(SM5803_ADDR_MAIN_FLAGS, SM5803_REG_PLATFORM);
+	/* Writes a lot of registers for presumably important reasons. */
+	LOG_ASSERT_W(SM5803_ADDR_MEAS_FLAGS, 0x26, 0xdc);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x21, 0x9b);
+	LOG_ASSERT_W(SM5803_ADDR_MAIN_FLAGS, 0x30, 0xc0);
+	LOG_ASSERT_W(SM5803_ADDR_MAIN_FLAGS, 0x80, 0x01);
+	LOG_ASSERT_W(SM5803_ADDR_MAIN_FLAGS, 0x1a, 0x08);
+	LOG_ASSERT_W(SM5803_ADDR_MEAS_FLAGS, 0x08, 0xc2);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x1d, 0x40);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x22, 0xb3);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x3e, 0x3c);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x4f, 0xbf);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x52, 0x77);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x53, 0xD2);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x54, 0x02);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x55, 0xD1);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x56, 0x7F);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x57, 0x01);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x58, 0x50);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x59, 0x7F);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x5A, 0x13);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x5B, 0x52);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x5D, 0xD0);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x60, 0x44);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x65, 0x35);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x66, 0x29);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x7D, 0x97);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x7E, 0x07);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x33, 0x3C);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x5C, 0x7A);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x73, 0x22);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x50, 0x88);
+	LOG_ASSERT_RW(SM5803_ADDR_CHARGER_FLAGS, 0x34, 0x80);
+	LOG_ASSERT_W(SM5803_ADDR_MAIN_FLAGS, 0x1f, 0x01);
+	LOG_ASSERT_W(SM5803_ADDR_TEST_FLAGS, 0x43, 0x10);
+	LOG_ASSERT_W(SM5803_ADDR_TEST_FLAGS, 0x47, 0x10);
+	LOG_ASSERT_W(SM5803_ADDR_TEST_FLAGS, 0x48, 0x04);
+	LOG_ASSERT_W(SM5803_ADDR_MAIN_FLAGS, 0x1f, 0);
+	verify_init_common(log_ptr);
+
+	zassert_equal(log.entries_asserted, log.entries_used,
+		      "recorded %d transactions but only verified %d",
+		      log.entries_used, log.entries_asserted);
+
+	/*
+	 * Running init again should check and update VBUS presence but not
+	 * re-run complete initialization. Doing more than that probably means
+	 * the first init failed.
+	 */
+	log.entries_used = 0;
+	sm5803_drv.init(CHARGER_NUM);
+	zassert_equal(log.entries_used, 6);
+}
+
+ZTEST(sm5803, test_init_3s)
+{
+	struct i2c_log log = {};
+	struct i2c_log *const log_ptr = &log;
+
+	/* Hook up logging functions for each I2C address. */
+	configure_i2c_log(SM5803_EMUL, &log);
+
+	/* Set 3S PMODE and run init */
+	chip_inited[0] = false;
+	sm5803_emul_set_pmode(SM5803_EMUL, 0x14);
+	sm5803_drv.init(CHARGER_NUM);
+	sm5803_drv.post_init(CHARGER_NUM);
+
+	/* Ensures we're in a safe state for operation. */
+	LOG_ASSERT_R(SM5803_ADDR_MAIN_FLAGS, SM5803_REG_CLOCK_SEL);
+	LOG_ASSERT_W(SM5803_ADDR_MEAS_FLAGS, SM5803_REG_GPADC_CONFIG1, 0xf7);
+	/* Checks VBUS presence and disables charger. */
+	LOG_ASSERT_R(SM5803_ADDR_MEAS_FLAGS, SM5803_REG_GPADC_CONFIG1);
+	LOG_ASSERT_R(SM5803_ADDR_MEAS_FLAGS, SM5803_REG_VBUS_MEAS_MSB);
+	LOG_ASSERT_R(SM5803_ADDR_MEAS_FLAGS, SM5803_REG_VBUS_MEAS_LSB);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, SM5803_REG_FLOW1, 0);
+	/* Gets chip ID (already cached) and PMODE. */
+	LOG_ASSERT_R(SM5803_ADDR_MAIN_FLAGS, SM5803_REG_PLATFORM);
+	/* Writes a lot of registers for presumably important reasons. */
+	LOG_ASSERT_W(SM5803_ADDR_MEAS_FLAGS, 0x26, 0xd8);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x21, 0x9b);
+	LOG_ASSERT_W(SM5803_ADDR_MAIN_FLAGS, 0x30, 0xc0);
+	LOG_ASSERT_W(SM5803_ADDR_MAIN_FLAGS, 0x80, 0x01);
+	LOG_ASSERT_W(SM5803_ADDR_MAIN_FLAGS, 0x1a, 0x08);
+	LOG_ASSERT_W(SM5803_ADDR_MEAS_FLAGS, 0x08, 0xc2);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x1d, 0x40);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x22, 0xb3);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x3e, 0x3c);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x4b, 0xa6);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x4f, 0xbf);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x52, 0x77);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x53, 0xD2);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x54, 0x02);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x55, 0xD1);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x56, 0x7F);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x57, 0x01);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x58, 0x50);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x59, 0x7F);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x5A, 0x13);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x5B, 0x50);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x5D, 0xB0);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x60, 0x44);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x65, 0x35);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x66, 0x29);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x7D, 0x67);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x7E, 0x04);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x33, 0x3C);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x5C, 0x7A);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x73, 0x22);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x50, 0x88);
+	LOG_ASSERT_RW(SM5803_ADDR_CHARGER_FLAGS, 0x34, 0x80);
+	LOG_ASSERT_W(SM5803_ADDR_MAIN_FLAGS, 0x1f, 0x01);
+	LOG_ASSERT_W(SM5803_ADDR_TEST_FLAGS, 0x43, 0x10);
+	LOG_ASSERT_W(SM5803_ADDR_TEST_FLAGS, 0x47, 0x10);
+	LOG_ASSERT_W(SM5803_ADDR_TEST_FLAGS, 0x48, 0x04);
+	LOG_ASSERT_W(SM5803_ADDR_MAIN_FLAGS, 0x1f, 0);
+	verify_init_common(log_ptr);
+
+	zassert_equal(log.entries_asserted, log.entries_used,
+		      "recorded %d transactions but only verified %d",
+		      log.entries_used, log.entries_asserted);
+}
+
+ZTEST(sm5803, test_init_rev2)
+{
+	struct i2c_log log = {};
+	struct i2c_log *const log_ptr = &log;
+
+	/* Hook up logging functions for each I2C address. */
+	configure_i2c_log(SM5803_EMUL, &log);
+
+	chip_inited[0] = false;
+	dev_id = -1;
+	sm5803_emul_set_device_id(SM5803_EMUL, 2);
+	sm5803_drv.init(CHARGER_NUM);
+	sm5803_drv.post_init(CHARGER_NUM);
+
+	/* Ensures we're in a safe state for operation. */
+	LOG_ASSERT_R(SM5803_ADDR_MAIN_FLAGS, SM5803_REG_CLOCK_SEL);
+	LOG_ASSERT_W(SM5803_ADDR_MEAS_FLAGS, SM5803_REG_GPADC_CONFIG1, 0xf7);
+	/* Checks VBUS presence and disables charger. */
+	LOG_ASSERT_R(SM5803_ADDR_MEAS_FLAGS, SM5803_REG_GPADC_CONFIG1);
+	LOG_ASSERT_R(SM5803_ADDR_MEAS_FLAGS, SM5803_REG_VBUS_MEAS_MSB);
+	LOG_ASSERT_R(SM5803_ADDR_MEAS_FLAGS, SM5803_REG_VBUS_MEAS_LSB);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, SM5803_REG_FLOW1, 0);
+	/* Gets chip ID */
+	LOG_ASSERT_R(SM5803_ADDR_MAIN_FLAGS, SM5803_REG_CHIP_ID);
+	/* Writes a lot of registers for presumably important reasons. */
+	LOG_ASSERT_W(SM5803_ADDR_MAIN_FLAGS, 0x20, 0x08);
+	LOG_ASSERT_W(SM5803_ADDR_MAIN_FLAGS, 0x30, 0xc0);
+	LOG_ASSERT_W(SM5803_ADDR_MAIN_FLAGS, 0x80, 0x01);
+	LOG_ASSERT_W(SM5803_ADDR_MEAS_FLAGS, 0x08, 0xc2);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x1d, 0x40);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x1f, 0x09);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x22, 0xb3);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x23, 0x81);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x28, 0xb7);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x4a, 0x82);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x4b, 0xa3);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x4c, 0xa8);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x4d, 0xca);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x4e, 0x07);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x4f, 0xff);
+
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x50, 0x98);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x51, 0);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x52, 0x77);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x53, 0xd2);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x54, 0x02);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x55, 0xd1);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x56, 0x7f);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x57, 0x02);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x58, 0xd1);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x59, 0x7f);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x5a, 0x13);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x5b, 0x50);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x5c, 0x5b);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x5d, 0xb0);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x5e, 0x3c);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x5f, 0x3c);
+
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x60, 0x44);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x61, 0x20);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x65, 0x35);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x66, 0x29);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x67, 0x64);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x68, 0x88);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, 0x69, 0xc7);
+
+	LOG_ASSERT_W(SM5803_ADDR_MAIN_FLAGS, 0x1f, 1);
+	LOG_ASSERT_RW(SM5803_ADDR_TEST_FLAGS, 0x8e, 0x20);
+	LOG_ASSERT_W(SM5803_ADDR_MAIN_FLAGS, 0x1f, 0);
+
+	verify_init_common(log_ptr);
+
+	zassert_equal(log.entries_asserted, log.entries_used,
+		      "recorded %d transactions but only verified %d",
+		      log.entries_used, log.entries_asserted);
+}
+
+FAKE_VALUE_FUNC(const uint8_t *, system_get_jump_tag, uint16_t, int *, int *);
+
+static const uint8_t *get_fake_inited_jump_tag(uint16_t tag, int *version,
+					       int *size)
+{
+	static const bool bbram_inited[] = { true, true };
+
+	BUILD_ASSERT(sizeof(bbram_inited) == sizeof(chip_inited));
+	*version = 1;
+	*size = sizeof(bbram_inited);
+	return (uint8_t *)bbram_inited;
+}
+
+ZTEST(sm5803, test_init_status_preserve)
+{
+	/* run init_status_preserve() */
+	chip_inited[0] = true;
+	chip_inited[1] = true;
+	hook_notify(HOOK_SYSJUMP);
+
+	/* pretend we rebooted and reset init state */
+	chip_inited[0] = false;
+	chip_inited[1] = false;
+	system_get_jump_tag_fake.custom_fake = get_fake_inited_jump_tag;
+	/*
+	 * init_status_retrieve() should restore chip_inited before charger
+	 * init runs, which would fail since we haven't mocked a number of the
+	 * registers it writes.
+	 */
+	hook_notify(HOOK_INIT);
+	zassert_true(chip_inited[0]);
+	zassert_true(chip_inited[1]);
+}
+
+ZTEST(sm5803, test_fast_charge_current)
+{
+	int ma;
+
+	/*
+	 * Can set and read back charge current limit,
+	 * which is adjusted when 0.
+	 */
+	zassert_ok(charger_set_current(CHARGER_NUM, 0));
+	zassert_equal(1, sm5803_emul_get_fast_charge_current_limit(SM5803_EMUL),
+		      "Zero current limit should be converted to nonzero");
+	zassert_ok(charger_get_current(CHARGER_NUM, &ma));
+	zassert_equal(ma, 100,
+		      "Actual current should be 100 mA times register value");
+
+	/* Errors are propagated. */
+	i2c_common_emul_set_read_fail_reg(sm5803_emul_get_i2c_chg(SM5803_EMUL),
+					  SM5803_REG_FAST_CONF4);
+	zassert_not_equal(
+		0, charger_set_current(CHARGER_NUM, 1000),
+		"set_current should fail if FAST_CONF4 is unreadable");
+	zassert_not_equal(
+		0, charger_get_current(CHARGER_NUM, &ma),
+		"get_current should fail if FAST_CONF4 is unreadable");
+}
+
+ZTEST(sm5803, test_measure_input_current)
+{
+	int ma;
+
+	sm5803_emul_set_input_current(SM5803_EMUL, 852);
+	zassert_ok(charger_get_input_current(CHARGER_NUM, &ma));
+	zassert_equal(ma, 849, "actual returned input current was %d", ma);
+
+	/* Communication errors bubble up */
+	i2c_common_emul_set_read_fail_reg(sm5803_emul_get_i2c_meas(SM5803_EMUL),
+					  SM5803_REG_IBUS_CHG_MEAS_LSB);
+	zassert_not_equal(0, charger_get_input_current(CHARGER_NUM, &ma));
+	i2c_common_emul_set_read_fail_reg(sm5803_emul_get_i2c_meas(SM5803_EMUL),
+					  SM5803_REG_IBUS_CHG_MEAS_MSB);
+	zassert_not_equal(0, charger_get_input_current(CHARGER_NUM, &ma));
+}
+
+ZTEST(sm5803, test_input_current_limit)
+{
+	int icl;
+	bool reached;
+
+	/* Can set and read back the input current limit. */
+	zassert_ok(charger_set_input_current_limit(CHARGER_NUM, 2150));
+	zassert_equal(21, sm5803_emul_read_chg_reg(SM5803_EMUL,
+						   SM5803_REG_CHG_ILIM));
+	zassert_ok(charger_get_input_current_limit(CHARGER_NUM, &icl));
+	zassert_equal(2100, icl,
+		      "expected 2100 mA input current limit, but was %d", icl);
+
+	/* Can also check whether input current is limited. */
+	zassert_ok(charger_is_icl_reached(CHARGER_NUM, &reached));
+	zassert_false(reached);
+	sm5803_emul_set_input_current(SM5803_EMUL, 2400);
+	zassert_ok(charger_is_icl_reached(CHARGER_NUM, &reached));
+	zassert_true(reached);
+
+	/* Communication errors bubble up. */
+	i2c_common_emul_set_read_fail_reg(sm5803_emul_get_i2c_chg(SM5803_EMUL),
+					  SM5803_REG_CHG_ILIM);
+	zassert_not_equal(0,
+			  charger_get_input_current_limit(CHARGER_NUM, &icl));
+	i2c_common_emul_set_write_fail_reg(sm5803_emul_get_i2c_chg(SM5803_EMUL),
+					   SM5803_REG_CHG_ILIM);
+	zassert_not_equal(0,
+			  charger_set_input_current_limit(CHARGER_NUM, 1400));
+}
+
+/* Analog measurement of VBUS. */
+ZTEST(sm5803, test_get_vbus_voltage)
+{
+	int mv;
+
+	/* Regular measurement with VBUS ADC enabled works. */
+	sm5803_emul_set_vbus_voltage(SM5803_EMUL, 5032);
+	zassert_ok(charger_get_vbus_voltage(CHARGER_NUM, &mv));
+	/* 5.031 is the nearest value representable by the VBUS ADC. */
+	zassert_equal(mv, 5031, "driver reported %d mV VBUS", mv);
+
+	/* Communication errors for ADC value bubble up. */
+	i2c_common_emul_set_read_fail_reg(sm5803_emul_get_i2c_meas(SM5803_EMUL),
+					  SM5803_REG_VBUS_MEAS_LSB);
+	zassert_not_equal(0, charger_get_vbus_voltage(CHARGER_NUM, &mv));
+	i2c_common_emul_set_read_fail_reg(sm5803_emul_get_i2c_meas(SM5803_EMUL),
+					  SM5803_REG_VBUS_MEAS_MSB);
+	zassert_not_equal(0, charger_get_vbus_voltage(CHARGER_NUM, &mv));
+
+	/* Returns a NOT_POWERED error if the VBUS ADC is disabled. */
+	sm5803_emul_set_gpadc_conf(SM5803_EMUL,
+				   (uint8_t)~SM5803_GPADCC1_VBUS_EN, 0);
+	zassert_equal(EC_ERROR_NOT_POWERED,
+		      charger_get_vbus_voltage(CHARGER_NUM, &mv));
+}
+
+ZTEST(sm5803, test_get_battery_current)
+{
+	int ma;
+
+	sm5803_emul_set_battery_current(SM5803_EMUL, 1234);
+	zassert_ok(charger_get_actual_current(CHARGER_NUM, &ma));
+	/* 1229 mA is nearest value representable at ADC resolution */
+	zassert_equal(ma, 1229, "read value was %d", ma);
+
+	/* Communication errors bubble up. */
+	i2c_common_emul_set_read_fail_reg(sm5803_emul_get_i2c_meas(SM5803_EMUL),
+					  SM5803_REG_IBAT_CHG_AVG_MEAS_LSB);
+	zassert_not_equal(0, charger_get_actual_current(CHARGER_NUM, &ma));
+	i2c_common_emul_set_read_fail_reg(sm5803_emul_get_i2c_meas(SM5803_EMUL),
+					  SM5803_REG_IBAT_CHG_AVG_MEAS_MSB);
+	zassert_not_equal(0, charger_get_actual_current(CHARGER_NUM, &ma));
+}
+
+/* Digital VBUS presence detection derived from DHG_DET. */
+ZTEST(sm5803, test_digital_vbus_presence_detect)
+{
+	/*
+	 * CHG_DET going high (from VBUS presence) triggers an interrupt and
+	 * presence update.
+	 */
+	sm5803_emul_set_vbus_voltage(SM5803_EMUL, 5000);
+	k_sleep(K_SECONDS(1)); /* Allow interrupt to be serviced. */
+	zassert_true(sm5803_is_vbus_present(CHARGER_NUM));
+
+	/* VBUS going away triggers another interrupt and update. */
+	sm5803_emul_set_vbus_voltage(SM5803_EMUL, 0);
+	k_sleep(K_SECONDS(1)); /* Allow interrupt to be serviced. */
+	zassert_false(sm5803_is_vbus_present(CHARGER_NUM));
+}
+
+/* VBUS detection for PD, analog or digital depending on chip state. */
+ZTEST(sm5803, test_check_vbus_level)
+{
+	/* Default state with VBUS ADC enabled: uses analog value */
+	zassert_true(sm5803_check_vbus_level(CHARGER_NUM, VBUS_REMOVED));
+	sm5803_emul_set_vbus_voltage(SM5803_EMUL, 5000);
+	zassert_true(sm5803_check_vbus_level(CHARGER_NUM, VBUS_PRESENT));
+
+	/* 4.6V is less than vSafe5V */
+	sm5803_emul_set_vbus_voltage(SM5803_EMUL, 4600);
+	k_sleep(K_SECONDS(1));
+	zassert_false(sm5803_check_vbus_level(CHARGER_NUM, VBUS_PRESENT));
+
+	/* Unrecognized levels are never matched */
+	zassert_false(sm5803_check_vbus_level(CHARGER_NUM, -1));
+
+	/*
+	 * With ADC disabled, uses digital presence only. 4.6V is high enough
+	 * to trip CHG_DET but wasn't enough to count as present with the analog
+	 * reading.
+	 */
+	sm5803_emul_set_gpadc_conf(SM5803_EMUL, 0, 0);
+	zassert_true(sm5803_check_vbus_level(CHARGER_NUM, VBUS_PRESENT));
+
+	/* 0.4V is !CHG_DET */
+	sm5803_emul_set_vbus_voltage(SM5803_EMUL, 400);
+	k_sleep(K_SECONDS(1));
+	zassert_true(sm5803_check_vbus_level(CHARGER_NUM, VBUS_REMOVED));
+
+	/* Unrecognized levels are never matched */
+	zassert_false(sm5803_check_vbus_level(CHARGER_NUM, -1));
+}
+
+ZTEST_F(sm5803, test_lpm)
+{
+	uint8_t gpadc1, gpadc2;
+	uint8_t cc_conf1;
+	uint8_t flow1, flow2, flow3;
+
+	pd_connect_source(fixture);
+
+	/* Charger should now have exited runtime LPM. */
+	zassert_false(sm5803_emul_is_clock_slowed(SM5803_EMUL));
+	sm5803_emul_get_gpadc_conf(SM5803_EMUL, &gpadc1, &gpadc2);
+	/* All except IBAT_DISCHG enabled. */
+	zassert_equal(gpadc1, 0xf7, "actual value was %#x", gpadc1);
+	/* Default value. */
+	zassert_equal(gpadc2, 1, "actual value was %#x", gpadc2);
+	/* Sigma-delta for Coulomb Counter is enabled. */
+	cc_conf1 = sm5803_emul_get_cc_config(SM5803_EMUL);
+	zassert_equal(cc_conf1, 0x09, "actual value was %#x", cc_conf1);
+	/* Charger is sinking. */
+	sm5803_emul_get_flow_regs(SM5803_EMUL, &flow1, &flow2, &flow3);
+	zassert_equal(flow1, 0x01, "FLOW1 should be set for sinking, was %#x",
+		      flow1);
+
+	/* Disconnect source, causing charger to go to runtime LPM. */
+	pd_disconnect(fixture);
+
+	zassert_true(sm5803_emul_is_clock_slowed(SM5803_EMUL));
+	/* Sigma delta was disabled. */
+	cc_conf1 = sm5803_emul_get_cc_config(SM5803_EMUL);
+	zassert_equal(sm5803_emul_get_cc_config(SM5803_EMUL), 0x01,
+		      "actual value was %#x", cc_conf1);
+	/*
+	 * Runtime LPM hook runs before the charge manager updates, so we expect
+	 * the GPADCs to be left on because the charger is still set for sinking
+	 * when it goes to runtime LPM.
+	 */
+	sm5803_emul_get_gpadc_conf(SM5803_EMUL, &gpadc1, &gpadc2);
+	zassert_equal(gpadc1, 0xf7, "actual value was %#x", gpadc1);
+	zassert_equal(gpadc2, 1, "actual value was %#x", gpadc2);
+
+	/*
+	 * Reconnect the source and inhibit charging, so GPADCs can be disabled
+	 * when we disconnect it.
+	 */
+	pd_connect_source(fixture);
+	zassert_ok(charger_set_mode(CHARGE_FLAG_INHIBIT_CHARGE));
+	pd_disconnect(fixture);
+
+	/* This time LPM actually did disable the GPADCs. */
+	sm5803_emul_get_gpadc_conf(SM5803_EMUL, &gpadc1, &gpadc2);
+	zassert_equal(gpadc1, 0, "actual value was %#x", gpadc1);
+	zassert_equal(gpadc2, 0, "actual value was %#x", gpadc2);
+}
+
+ZTEST(sm5803, test_get_battery_cells)
+{
+	int cells;
+
+	/* Default PMODE reports 2s */
+	zassert_ok(sm5803_drv.get_battery_cells(CHARGER_NUM, &cells));
+	zassert_equal(cells, 2);
+
+	/* 3s PMODE is 3s */
+	sm5803_emul_set_pmode(SM5803_EMUL, 0x14);
+	zassert_ok(sm5803_drv.get_battery_cells(CHARGER_NUM, &cells));
+	zassert_equal(cells, 3);
+
+	/* Unrecognized PMODE is an error */
+	sm5803_emul_set_pmode(SM5803_EMUL, 0x1f);
+	zassert_not_equal(sm5803_drv.get_battery_cells(CHARGER_NUM, &cells), 0);
+	zassert_equal(cells, -1);
+
+	/* Communication error bubbles up */
+	i2c_common_emul_set_read_fail_reg(sm5803_emul_get_i2c_main(SM5803_EMUL),
+					  SM5803_REG_PLATFORM);
+	zassert_not_equal(sm5803_drv.get_battery_cells(CHARGER_NUM, &cells), 0);
+}
+
+ZTEST(sm5803, test_gpio)
+{
+	/* Open drain output */
+	zassert_ok(sm5803_configure_gpio0(CHARGER_NUM, GPIO0_MODE_OUTPUT, 1));
+	zassert_equal(sm5803_emul_get_gpio_ctrl(SM5803_EMUL), 0x42);
+	/* Set output high, from default of low. */
+	zassert_ok(sm5803_set_gpio0_level(CHARGER_NUM, 1));
+	zassert_equal(sm5803_emul_get_gpio_ctrl(SM5803_EMUL), 0x43);
+	/* Set it low again. */
+	zassert_ok(sm5803_set_gpio0_level(CHARGER_NUM, 0));
+	zassert_equal(sm5803_emul_get_gpio_ctrl(SM5803_EMUL), 0x42);
+
+	/* Push-pull prochot. */
+	zassert_ok(sm5803_configure_gpio0(CHARGER_NUM, GPIO0_MODE_PROCHOT, 0));
+	zassert_equal(sm5803_emul_get_gpio_ctrl(SM5803_EMUL), 0x00);
+
+	/* CHG_DET output enable lives in this register too */
+	zassert_ok(sm5803_configure_chg_det_od(CHARGER_NUM, 1));
+	zassert_equal(sm5803_emul_get_gpio_ctrl(SM5803_EMUL), 0x80);
+	zassert_ok(sm5803_configure_chg_det_od(CHARGER_NUM, 0));
+	zassert_equal(sm5803_emul_get_gpio_ctrl(SM5803_EMUL), 0x00);
+
+	/* Communication errors bubble up */
+	i2c_common_emul_set_read_fail_reg(sm5803_emul_get_i2c_main(SM5803_EMUL),
+					  SM5803_REG_GPIO0_CTRL);
+	zassert_not_equal(
+		sm5803_configure_gpio0(CHARGER_NUM, GPIO0_MODE_INPUT, 0), 0);
+	zassert_not_equal(sm5803_set_gpio0_level(CHARGER_NUM, 0), 0);
+	zassert_not_equal(sm5803_configure_chg_det_od(CHARGER_NUM, 1), 0);
+}
+
+ZTEST(sm5803, test_vsys_compensation)
+{
+	struct ocpc_data ocpc;
+
+	/* Minimum possible resistance */
+	ocpc.combined_rsys_rbatt_mo = 0;
+	zassert_equal(sm5803_drv.set_vsys_compensation(CHARGER_NUM, &ocpc, 0,
+						       0),
+		      EC_ERROR_UNIMPLEMENTED);
+	zassert_equal(sm5803_emul_get_ir_comp(SM5803_EMUL), 0x2100,
+		      "actual IR_COMP value was %#x",
+		      sm5803_emul_get_ir_comp(SM5803_EMUL));
+
+	/* Maximum resistance supported by SM5803 (1.67 mOhm * 0x3FF) */
+	ocpc.combined_rsys_rbatt_mo = 1709;
+	zassert_equal(sm5803_drv.set_vsys_compensation(CHARGER_NUM, &ocpc, 0,
+						       0),
+		      EC_ERROR_UNIMPLEMENTED);
+	zassert_equal(sm5803_emul_get_ir_comp(SM5803_EMUL), 0xE1FF,
+		      "actual IR_COMP value was %#x",
+		      sm5803_emul_get_ir_comp(SM5803_EMUL));
+
+	/* Typical actual resistance */
+	ocpc.combined_rsys_rbatt_mo = 42;
+	zassert_equal(sm5803_drv.set_vsys_compensation(CHARGER_NUM, &ocpc, 0,
+						       0),
+		      EC_ERROR_UNIMPLEMENTED);
+	zassert_equal(sm5803_emul_get_ir_comp(SM5803_EMUL), 0x2119,
+		      "actual IR_COMP value was %#x",
+		      sm5803_emul_get_ir_comp(SM5803_EMUL));
+
+	/* Communication errors bubble up */
+	i2c_common_emul_set_read_fail_reg(sm5803_emul_get_i2c_chg(SM5803_EMUL),
+					  SM5803_REG_IR_COMP1);
+	zassert_not_equal(sm5803_drv.set_vsys_compensation(CHARGER_NUM, &ocpc,
+							   0, 0),
+			  EC_ERROR_UNIMPLEMENTED);
+}
+
+ZTEST(sm5803, test_vbus_sink_enable)
+{
+	uint8_t flow1, flow2, flow3;
+
+	zassert_ok(sm5803_vbus_sink_enable(CHARGER_NUM, 1));
+	sm5803_emul_get_flow_regs(SM5803_EMUL, &flow1, &flow2, &flow3);
+	zassert_equal(flow1, 0x01, "FLOW1 should be set to sink mode; was %#x",
+		      flow1);
+	zassert_equal(
+		flow2, 0x07,
+		"FLOW2 should enable automatic charge management; was %#x",
+		flow2);
+
+	/*
+	 * TODO(b:283026626): exercise the branch for disconnected battery
+	 * in sm5803_vbus_sink_enable.
+	 */
+
+	zassert_ok(sm5803_vbus_sink_enable(CHARGER_NUM, 0));
+	sm5803_emul_get_flow_regs(SM5803_EMUL, &flow1, &flow2, &flow3);
+	zassert_equal(flow1, 0, "FLOW1 should disable sinking; was %#x", flow1);
+	zassert_equal(flow2, 0, "FLOW2 should disable auto charge; was %#x",
+		      flow2);
+
+	/* Secondary charger has slightly different operation. */
+	zassert_ok(sm5803_vbus_sink_enable(CHARGER_SECONDARY, 1));
+	sm5803_emul_get_flow_regs(SM5803_EMUL_SECONDARY, &flow1, &flow2,
+				  &flow3);
+	zassert_equal(flow1, 0x01, "FLOW1 should be set to sink mode; was %#x",
+		      flow1);
+
+	zassert_ok(sm5803_vbus_sink_enable(CHARGER_SECONDARY, 0));
+	sm5803_emul_get_flow_regs(SM5803_EMUL_SECONDARY, &flow1, &flow2,
+				  &flow3);
+	zassert_equal(flow1, 0, "FLOW1 should disable sinking; was %#x", flow1);
+}
+
+ZTEST(sm5803, test_charge_ramp)
+{
+	int icl;
+
+	/* Enables DPM loop when ramp is requested */
+	zassert_ok(sm5803_drv.set_hw_ramp(CHARGER_NUM, 1));
+	zassert_equal(sm5803_emul_get_chg_mon(SM5803_EMUL), 1);
+	/* These functions always report these values */
+	zassert_equal(sm5803_drv.ramp_is_stable(CHARGER_NUM), 0);
+	zassert_equal(sm5803_drv.ramp_is_detected(CHARGER_NUM), 1);
+	/* Ramp limit is always the same as regular ICL */
+	zassert_ok(charger_get_input_current_limit(CHARGER_NUM, &icl));
+	zassert_equal(sm5803_drv.ramp_get_current_limit(CHARGER_NUM), icl);
+
+	/* Requesting disable turns off the DPM loop */
+	zassert_ok(sm5803_drv.set_hw_ramp(CHARGER_NUM, 0));
+	zassert_equal(sm5803_emul_get_chg_mon(SM5803_EMUL), 0);
+}
+
+/** Get the source mode voltage target, in mV. */
+static uint32_t get_source_voltage(void)
+{
+	return 2720 + 10 * ((sm5803_emul_get_disch_conf1(SM5803_EMUL) << 3) |
+			    (sm5803_emul_get_disch_conf2(SM5803_EMUL) & 7));
+}
+
+ZTEST(sm5803, test_configure_sourcing)
+{
+	/* Typical configuration, 5V @ 1.5A */
+	zassert_ok(sm5803_drv.set_otg_current_voltage(CHARGER_NUM, 1500, 5000));
+	zassert_equal(sm5803_emul_get_disch_conf5(SM5803_EMUL), 30,
+		      "Current limit should be 30 * 50 mA, but"
+		      " register value is %#x",
+		      sm5803_emul_get_disch_conf5(SM5803_EMUL));
+	zassert_equal(get_source_voltage(), 5000,
+		      "actual source voltage was set to %d mV",
+		      get_source_voltage());
+
+	/* Very large currents don't write bits they shouldn't */
+	zassert_ok(sm5803_drv.set_otg_current_voltage(CHARGER_NUM, 6500, 5000));
+	zassert_equal(
+		sm5803_emul_get_disch_conf5(SM5803_EMUL), 0x7F,
+		"current limit should be maximum, but register value is %#x",
+		sm5803_emul_get_disch_conf5(SM5803_EMUL));
+
+	/* Small voltages don't underflow */
+	zassert_ok(sm5803_drv.set_otg_current_voltage(CHARGER_NUM, 1000, 2000));
+	zassert_equal(
+		get_source_voltage(), 2720,
+		"small voltages should clamp to minimum, but is set to %d mV",
+		get_source_voltage());
+
+	/* Errors bubble up */
+	i2c_common_emul_set_read_fail_reg(sm5803_emul_get_i2c_chg(SM5803_EMUL),
+					  SM5803_REG_DISCH_CONF5);
+	zassert_not_equal(
+		sm5803_drv.set_otg_current_voltage(CHARGER_NUM, 1500, 5000), 0);
+}
+
+ZTEST(sm5803, test_sourcing)
+{
+	uint8_t gpadc1, gpadc2;
+	uint8_t flow1, flow2, flow3;
+
+	/* Preset source current limit */
+	sm5803_drv.set_otg_current_voltage(CHARGER_NUM, 1000, 0);
+	/* Turn off GPADCs so we can check they get turned on */
+	sm5803_emul_set_gpadc_conf(SM5803_EMUL, 0, 0);
+
+	zassert_ok(sm5803_drv.enable_otg_power(CHARGER_NUM, 1));
+	zassert_true(sm5803_drv.is_sourcing_otg_power(CHARGER_NUM, 0));
+	/* GPADCs got turned on as needed. */
+	sm5803_emul_get_gpadc_conf(SM5803_EMUL, &gpadc1, &gpadc2);
+	zassert_equal(gpadc1, 0xf7,
+		      "GPADCs should be set to active state, but CONF1 = %#x",
+		      gpadc1);
+	zassert_equal(gpadc2, 0,
+		      "GPADCs should be set to active state, but CONF2 = %#x",
+		      gpadc2);
+	/* Source current limit is turned on */
+	zassert_equal(sm5803_emul_get_ana_en1(SM5803_EMUL), 0x19,
+		      "CLS_DISABLE should be cleared, but ANA_EN1 = %#x",
+		      sm5803_emul_get_ana_en1(SM5803_EMUL));
+	/* Source current ramp was disabled */
+	zassert_equal(sm5803_emul_get_disch_conf6(SM5803_EMUL), 0x01);
+	/* FLOW1 was set to sourcing with current regulation */
+	sm5803_emul_get_flow_regs(SM5803_EMUL, &flow1, &flow2, &flow3);
+	zassert_equal(flow1, 0x07);
+	/* Source voltage is 5V and current limit is retained from previous */
+	zassert_equal(get_source_voltage(), 5000);
+
+	/* Status polling function works */
+	zassert_true(sm5803_drv.is_sourcing_otg_power(CHARGER_NUM, 0));
+
+	/* Now turn off source mode */
+	sm5803_emul_set_disch_status(SM5803_EMUL, 0x18);
+	zassert_ok(sm5803_drv.enable_otg_power(CHARGER_NUM, 0));
+	zassert_equal(sm5803_emul_get_disch_status(SM5803_EMUL), 0,
+		      "discharge status flags should be cleared but were not");
+	zassert_equal(sm5803_emul_get_disch_conf6(SM5803_EMUL), 0,
+		      "DISCH_CONF6 should be cleared, but is now %#x",
+		      sm5803_emul_get_disch_conf6(SM5803_EMUL));
+	/* Source mode is disabled */
+	sm5803_emul_get_flow_regs(SM5803_EMUL, &flow1, &flow2, &flow3);
+	zassert_equal(flow1, 0);
+
+	/* Assorted errors bubble up */
+	i2c_common_emul_set_read_fail_reg(sm5803_emul_get_i2c_chg(SM5803_EMUL),
+					  SM5803_REG_DISCH_CONF5);
+	zassert_not_equal(sm5803_drv.enable_otg_power(CHARGER_NUM, 1), 0);
+	i2c_common_emul_set_read_fail_reg(sm5803_emul_get_i2c_chg(SM5803_EMUL),
+					  SM5803_REG_ANA_EN1);
+	zassert_not_equal(sm5803_drv.enable_otg_power(CHARGER_NUM, 1), 0);
+	i2c_common_emul_set_read_fail_reg(sm5803_emul_get_i2c_chg(SM5803_EMUL),
+					  SM5803_REG_FLOW1);
+	zassert_not_equal(sm5803_drv.enable_otg_power(CHARGER_NUM, 0), 0);
+	i2c_common_emul_set_read_fail_reg(sm5803_emul_get_i2c_chg(SM5803_EMUL),
+					  SM5803_REG_STATUS_DISCHG);
+	zassert_not_equal(sm5803_drv.enable_otg_power(CHARGER_NUM, 0), 0);
+}
+
+ZTEST(sm5803, test_set_option)
+{
+	uint8_t flow1, flow2, flow3;
+
+	/* set_option() writes all three flow registers */
+	zassert_ok(sm5803_drv.set_option(CHARGER_NUM, 0xE54321));
+	sm5803_emul_get_flow_regs(SM5803_EMUL, &flow1, &flow2, &flow3);
+	/* FLOW1 bits 4-6 always read 0 */
+	zassert_equal(flow1, 0x01, "actual value was %#x", flow1);
+	zassert_equal(flow2, 0x43, "actual value was %#x", flow2);
+	/* FLOW3 bit 7 is unimplemented */
+	zassert_equal(flow3, 0x65, "actual value was %#x", flow3);
+
+	/* and I2C errors are returned */
+	i2c_common_emul_set_write_fail_reg(sm5803_emul_get_i2c_chg(SM5803_EMUL),
+					   SM5803_REG_FLOW3);
+	zassert_not_equal(sm5803_drv.set_option(CHARGER_NUM, 0), 0);
+	i2c_common_emul_set_write_fail_reg(sm5803_emul_get_i2c_chg(SM5803_EMUL),
+					   SM5803_REG_FLOW2);
+	zassert_not_equal(sm5803_drv.set_option(CHARGER_NUM, 0), 0);
+	i2c_common_emul_set_write_fail_reg(sm5803_emul_get_i2c_chg(SM5803_EMUL),
+					   SM5803_REG_FLOW1);
+	zassert_not_equal(sm5803_drv.set_option(CHARGER_NUM, 0), 0);
+}
+
+ZTEST(sm5803, test_acok)
+{
+	bool acok;
+
+	zassert_ok(sm5803_is_acok(CHARGER_NUM, &acok));
+	zassert_false(acok);
+
+	sm5803_emul_set_vbus_voltage(SM5803_EMUL, 4986);
+	zassert_ok(sm5803_is_acok(CHARGER_NUM, &acok));
+	zassert_true(acok);
+
+	i2c_common_emul_set_read_fail_reg(sm5803_emul_get_i2c_meas(SM5803_EMUL),
+					  SM5803_REG_VBUS_MEAS_MSB);
+	zassert_not_equal(sm5803_is_acok(CHARGER_NUM, &acok), 0);
+	i2c_common_emul_set_read_fail_reg(sm5803_emul_get_i2c_main(SM5803_EMUL),
+					  SM5803_REG_STATUS1);
+	zassert_not_equal(sm5803_is_acok(CHARGER_NUM, &acok), 0);
+}
+
+ZTEST(sm5803, test_chg_det)
+{
+	int chg_det;
+
+	zassert_ok(sm5803_get_chg_det(CHARGER_NUM, &chg_det));
+	zassert_false(chg_det);
+
+	sm5803_emul_set_vbus_voltage(SM5803_EMUL, 9001);
+	zassert_ok(sm5803_get_chg_det(CHARGER_NUM, &chg_det));
+	zassert_true(chg_det);
+
+	i2c_common_emul_set_read_fail_reg(sm5803_emul_get_i2c_main(SM5803_EMUL),
+					  SM5803_REG_STATUS1);
+	zassert_not_equal(sm5803_get_chg_det(CHARGER_NUM, &chg_det), 0);
+}
+
+ZTEST(sm5803, test_vbus_discharge)
+{
+	/* Enabling VBUS discharge sets the discharge enable bit */
+	zassert_ok(sm5803_set_vbus_disch(CHARGER_NUM, 1));
+	zassert_equal(sm5803_emul_get_ports_ctrl(SM5803_EMUL), 1,
+		      "actual value was %#x",
+		      sm5803_emul_get_ports_ctrl(SM5803_EMUL));
+
+	/* And we can clear it */
+	zassert_ok(sm5803_set_vbus_disch(CHARGER_NUM, 0));
+	zassert_equal(sm5803_emul_get_ports_ctrl(SM5803_EMUL), 0,
+		      "actual value was %#x",
+		      sm5803_emul_get_ports_ctrl(SM5803_EMUL));
+
+	/* Errors are returned */
+	i2c_common_emul_set_read_fail_reg(sm5803_emul_get_i2c_main(SM5803_EMUL),
+					  SM5803_REG_PORTS_CTRL);
+	zassert_not_equal(sm5803_set_vbus_disch(CHARGER_NUM, 0), 0);
+}
+
+ZTEST(sm5803, test_hibernate)
+{
+	uint8_t gpadc1, gpadc2;
+
+	/*
+	 * Assorted registers get programmed on hibernate; use the secondary
+	 * charger because it has some extra handling.
+	 */
+	sm5803_hibernate(CHARGER_SECONDARY);
+	zassert_equal(
+		sm5803_emul_get_reference_reg(SM5803_EMUL_SECONDARY), 0x03,
+		"REFERENCE1 should disable LDOs, but actual value was %#x",
+		sm5803_emul_get_reference_reg(SM5803_EMUL_SECONDARY));
+	zassert_true(sm5803_emul_is_clock_slowed(SM5803_EMUL_SECONDARY));
+
+	sm5803_emul_get_gpadc_conf(SM5803_EMUL_SECONDARY, &gpadc1, &gpadc2);
+	zassert_equal(gpadc1, 0,
+		      "GPADCs should be disabled, but GPADC1 was %#x", gpadc1);
+	zassert_equal(gpadc2, 0,
+		      "GPADCs should be disabled, but GPADC2 was %#x", gpadc2);
+
+	zassert_false(sm5803_emul_is_psys_dac_enabled(SM5803_EMUL_SECONDARY));
+
+	zassert_equal(sm5803_emul_get_cc_config(SM5803_EMUL_SECONDARY), 0x01,
+		      "Sigma-delta should be disabled, but CC_CONFIG1 was %#x",
+		      sm5803_emul_get_cc_config(SM5803_EMUL_SECONDARY));
+
+	zassert_equal(sm5803_emul_get_phot1(SM5803_EMUL_SECONDARY), 0x20,
+		      "PHOT1 should disable comparators, but value was %#x",
+		      sm5803_emul_get_phot1(SM5803_EMUL_SECONDARY));
+
+	/* Primary charger doesn't disable LDOs. */
+	sm5803_hibernate(CHARGER_PRIMARY);
+	zassert_equal(
+		sm5803_emul_get_reference_reg(SM5803_EMUL), 0,
+		"REFERENCE1 should not disable LDOs, but actual value was %#x",
+		sm5803_emul_get_reference_reg(SM5803_EMUL));
+
+	/* Error paths don't do anything catastrophically bad */
+	i2c_common_emul_set_write_fail_reg(
+		sm5803_emul_get_i2c_main(SM5803_EMUL_SECONDARY),
+		SM5803_REG_REFERENCE);
+	sm5803_hibernate(CHARGER_SECONDARY);
+
+	i2c_common_emul_set_read_fail_reg(
+		sm5803_emul_get_i2c_main(SM5803_EMUL_SECONDARY),
+		SM5803_REG_REFERENCE);
+	sm5803_hibernate(CHARGER_SECONDARY);
+}
+
+ZTEST(sm5803, test_set_voltage)
+{
+	struct i2c_log log = {};
+	struct i2c_log *const log_ptr = &log;
+
+	i2c_common_emul_set_read_func(sm5803_emul_get_i2c_chg(SM5803_EMUL),
+				      i2c_log_read_chg, log_ptr);
+	i2c_common_emul_set_write_func(sm5803_emul_get_i2c_chg(SM5803_EMUL),
+				       i2c_log_write_chg, log_ptr);
+
+	test_sm5803_set_fast_charge_disabled(true);
+	zassert_ok(sm5803_drv.set_voltage(CHARGER_NUM, 12000));
+	/* VSYS and VBAT were programmed to the requested voltage */
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, SM5803_REG_VSYS_PREREG_MSB,
+		     0x74);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, SM5803_REG_VSYS_PREREG_LSB, 0);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, SM5803_REG_VBAT_FAST_MSB, 0x74);
+	LOG_ASSERT_W(SM5803_ADDR_CHARGER_FLAGS, SM5803_REG_VBAT_FAST_LSB, 0);
+	/* Fast charge was enabled */
+	zassert_false(test_sm5803_get_fast_charge_disabled());
+	LOG_ASSERT_RW(SM5803_ADDR_CHARGER_FLAGS, SM5803_REG_FLOW2, 0x07);
+}
+
+ZTEST(sm5803, test_get_actual_voltage)
+{
+	int mv;
+
+	sm5803_emul_set_vsys_measured_mv(SM5803_EMUL, 7450);
+	zassert_ok(sm5803_drv.get_actual_voltage(CHARGER_NUM, &mv));
+	/* Nearest value representable by the measurement registers. */
+	zassert_equal(mv, 7441, "actual reported value was %d mV", mv);
+
+	/* Communication errors bubble up */
+	i2c_common_emul_set_read_fail_reg(sm5803_emul_get_i2c_meas(SM5803_EMUL),
+					  SM5803_REG_VSYS_AVG_MEAS_LSB);
+	zassert_not_equal(sm5803_drv.get_actual_voltage(CHARGER_NUM, &mv), 0);
+	i2c_common_emul_set_read_fail_reg(sm5803_emul_get_i2c_meas(SM5803_EMUL),
+					  SM5803_REG_VSYS_AVG_MEAS_MSB);
+	zassert_not_equal(sm5803_drv.get_actual_voltage(CHARGER_NUM, &mv), 0);
+}
+
+ZTEST(sm5803, test_linear_charge)
+{
+	uint8_t flow1, flow3;
+
+	/* Initial attempt is rebuffed because BFET is disabled. */
+	zassert_equal(sm5803_drv.enable_linear_charge(CHARGER_SECONDARY, 1),
+		      EC_ERROR_TRY_AGAIN);
+	/* Set target voltage, kicking the primary charger's BFET on. */
+	zassert_ok(sm5803_drv.set_voltage(CHARGER_SECONDARY, 10600));
+	sm5803_emul_get_flow_regs(SM5803_EMUL, &flow1, NULL, NULL);
+	zassert_equal(flow1, 0x01,
+		      "Primary charger FLOW1 should be sinking, but was %#x",
+		      flow1);
+	zassert_equal(sm5803_emul_get_log1(SM5803_EMUL), 0x04,
+		      "Primary charger BFET should be on, but LOG1 was %#x",
+		      sm5803_emul_get_log1(SM5803_EMUL));
+
+	/* Now linear charge enable is permitted. */
+	zassert_ok(sm5803_drv.enable_linear_charge(CHARGER_SECONDARY, 1));
+	sm5803_emul_get_flow_regs(SM5803_EMUL_SECONDARY, &flow1, NULL, &flow3);
+	zassert_equal(flow1, 0x09,
+		      "secondary charger should be sinking in linear mode,"
+		      " but FLOW1 was %#x",
+		      flow1);
+	zassert_equal(flow3, 0x70,
+		      "mystery bits 4-6 of FLOW3 should have been set, but"
+		      " value was %#x",
+		      flow3);
+
+	/* Disables when requested. */
+	zassert_ok(sm5803_drv.enable_linear_charge(CHARGER_SECONDARY, 0));
+	sm5803_emul_get_flow_regs(SM5803_EMUL_SECONDARY, &flow1, NULL, &flow3);
+	zassert_equal(flow1, 0x01,
+		      "secondary charger linear mode should be disabled, but"
+		      " FLOW1 was %#x",
+		      flow1);
+	zassert_equal(flow3, 0,
+		      "FLOW3 mystery bits should be cleared, but value was %#x",
+		      flow3);
+}
+
+ZTEST(sm5803, test_explicit_lpm)
+{
+	/* Enter LPM */
+	sm5803_enable_low_power_mode(CHARGER_NUM);
+	zassert_false(sm5803_emul_is_psys_dac_enabled(SM5803_EMUL));
+	zassert_equal(
+		sm5803_emul_get_phot1(SM5803_EMUL), 0x20,
+		"PROCHOT comparators should be disabled, but PHOT1 was %#x",
+		sm5803_emul_get_phot1(SM5803_EMUL));
+
+	/* Exit LPM */
+	sm5803_disable_low_power_mode(CHARGER_NUM);
+	zassert_true(sm5803_emul_is_psys_dac_enabled(SM5803_EMUL));
+	zassert_equal(
+		sm5803_emul_get_phot1(SM5803_EMUL), 0x2d,
+		"PROCHOT comparators should be enabled, but PHOT1 was %#x",
+		sm5803_emul_get_phot1(SM5803_EMUL));
+
+	/* Errors are handled */
+	i2c_common_emul_set_read_fail_reg(sm5803_emul_get_i2c_chg(SM5803_EMUL),
+					  SM5803_REG_PHOT1);
+	sm5803_enable_low_power_mode(CHARGER_NUM);
+	sm5803_disable_low_power_mode(CHARGER_NUM);
+	i2c_common_emul_set_read_fail_reg(sm5803_emul_get_i2c_meas(SM5803_EMUL),
+					  SM5803_REG_PSYS1);
+	sm5803_enable_low_power_mode(CHARGER_NUM);
+	sm5803_disable_low_power_mode(CHARGER_NUM);
+	i2c_common_emul_set_read_fail_reg(sm5803_emul_get_i2c_main(SM5803_EMUL),
+					  SM5803_REG_REFERENCE);
+	sm5803_enable_low_power_mode(CHARGER_NUM);
+	sm5803_disable_low_power_mode(CHARGER_NUM);
+}
+
+ZTEST_F(sm5803, test_explicit_lpm_connected)
+{
+	pd_connect_source(fixture);
+
+	/* Going to explicit LPM leaves VBUS comparator enabled. */
+	sm5803_enable_low_power_mode(CHARGER_NUM);
+	zassert_equal(sm5803_emul_get_phot1(SM5803_EMUL), 0x28,
+		      "Comparators other than VBUS should be disabled,"
+		      " but PHOT1 was %#x",
+		      sm5803_emul_get_phot1(SM5803_EMUL));
+}
+
+ZTEST_F(sm5803, test_vbat_overvoltage_2s)
+{
+	struct i2c_log log = {};
+	struct i2c_log *const log_ptr = &log;
+	uint8_t flow1;
+
+	pd_connect_source(fixture);
+	sm5803_emul_get_flow_regs(SM5803_EMUL, &flow1, NULL, NULL);
+	zassert_equal(flow1, 1, "charger should be sinking, but FLOW1 was %#x",
+		      flow1);
+
+	/* Log accesses to sense parameters to verify they're as expected. */
+	i2c_common_emul_set_read_func(sm5803_emul_get_i2c_meas(SM5803_EMUL),
+				      i2c_log_read_meas, log_ptr);
+	i2c_common_emul_set_write_func(sm5803_emul_get_i2c_meas(SM5803_EMUL),
+				       i2c_log_write_meas, log_ptr);
+
+	/*
+	 * Trigger VBAT_SNS overvoltage interrupt. Default threshold for 2S is
+	 * 9V.
+	 */
+	sm5803_emul_set_vbat_sns_mv(SM5803_EMUL, 9050);
+	sm5803_emul_set_irqs(SM5803_EMUL, 0, SM5803_INT2_VBATSNSP, 0, 0);
+	/* Allow interrupt to be serviced */
+	k_sleep(K_SECONDS(0.1));
+
+	/*
+	 * Interrupt handler logged voltages, then reset the threshold to reset
+	 * the interrupt, and programmed the expected threshold back.
+	 */
+	LOG_ASSERT_R(SM5803_ADDR_MEAS_FLAGS, SM5803_REG_VBATSNSP_MEAS_MSB);
+	LOG_ASSERT_R(SM5803_ADDR_MEAS_FLAGS, SM5803_REG_VBATSNSP_MEAS_LSB);
+	LOG_ASSERT_R(SM5803_ADDR_MEAS_FLAGS, SM5803_REG_VBATSNSP_MAX_TH);
+	LOG_ASSERT_W(SM5803_ADDR_MEAS_FLAGS, SM5803_REG_VBATSNSP_MAX_TH, 0xff);
+	LOG_ASSERT_W(SM5803_ADDR_MEAS_FLAGS, SM5803_REG_VBATSNSP_MAX_TH, 0xdc);
+	/* Interrupt handler also stopped sinking. */
+	sm5803_emul_get_flow_regs(SM5803_EMUL, &flow1, NULL, NULL);
+	zassert_equal(flow1, 0,
+		      "FLOW1 should disable charger, but value was %#x", flow1);
+
+	/*
+	 * Charger will now attempt to re-enable sinking automatically. Stop
+	 * logging because we don't care anymore and there will be a lot of
+	 * accesses in the background while we wait.
+	 */
+	i2c_common_emul_set_read_func(sm5803_emul_get_i2c_meas(SM5803_EMUL),
+				      NULL, NULL);
+	i2c_common_emul_set_write_func(sm5803_emul_get_i2c_meas(SM5803_EMUL),
+				       NULL, NULL);
+	k_sleep(K_SECONDS(2));
+	sm5803_emul_get_flow_regs(SM5803_EMUL, &flow1, NULL, NULL);
+	zassert_equal(flow1, 1,
+		      "FLOW1 should resume sinking, but value was %#x", flow1);
+
+	/* Assorted error paths in the interrupt. */
+	i2c_common_emul_set_read_fail_reg(sm5803_emul_get_i2c_meas(SM5803_EMUL),
+					  SM5803_REG_VBATSNSP_MAX_TH);
+	sm5803_emul_set_irqs(SM5803_EMUL, 0, SM5803_INT2_VBATSNSP, 0, 0);
+	sm5803_handle_interrupt(CHARGER_NUM);
+	i2c_common_emul_set_read_fail_reg(sm5803_emul_get_i2c_meas(SM5803_EMUL),
+					  SM5803_REG_VBATSNSP_MEAS_LSB);
+	sm5803_emul_set_irqs(SM5803_EMUL, 0, SM5803_INT2_VBATSNSP, 0, 0);
+	sm5803_handle_interrupt(CHARGER_NUM);
+	i2c_common_emul_set_read_fail_reg(sm5803_emul_get_i2c_meas(SM5803_EMUL),
+					  SM5803_REG_VBATSNSP_MEAS_MSB);
+	sm5803_emul_set_irqs(SM5803_EMUL, 0, SM5803_INT2_VBATSNSP, 0, 0);
+	sm5803_handle_interrupt(CHARGER_NUM);
+	i2c_common_emul_set_read_fail_reg(sm5803_emul_get_i2c_main(SM5803_EMUL),
+					  SM5803_REG_PLATFORM);
+	sm5803_emul_set_irqs(SM5803_EMUL, 0, SM5803_INT2_VBATSNSP, 0, 0);
+	sm5803_handle_interrupt(CHARGER_NUM);
+}
+
+ZTEST_F(sm5803, test_vbat_overvoltage_3s)
+{
+	/*
+	 * This test case is nearly identical to test_vbat_overvoltage_2s but
+	 * expects different thresholds.
+	 */
+	struct i2c_log log = {};
+	struct i2c_log *const log_ptr = &log;
+	uint8_t flow1;
+
+	/* Set 3S PMODE */
+	sm5803_emul_set_pmode(SM5803_EMUL, 0x14);
+
+	/* Connect PD source and begin charging. */
+	pd_connect_source(fixture);
+	sm5803_emul_get_flow_regs(SM5803_EMUL, &flow1, NULL, NULL);
+	zassert_equal(flow1, 1, "charger should be sinking, but FLOW1 was %#x",
+		      flow1);
+
+	/* Log accesses to sense parameters to verify they're as expected. */
+	i2c_common_emul_set_read_func(sm5803_emul_get_i2c_meas(SM5803_EMUL),
+				      i2c_log_read_meas, log_ptr);
+	i2c_common_emul_set_write_func(sm5803_emul_get_i2c_meas(SM5803_EMUL),
+				       i2c_log_write_meas, log_ptr);
+
+	/*
+	 * Trigger VBAT_SNS overvoltage interrupt. Default threshold for 3S is
+	 * 13.3V.
+	 */
+	sm5803_emul_set_vbat_sns_mv(SM5803_EMUL, 13450);
+	sm5803_emul_set_irqs(SM5803_EMUL, 0, SM5803_INT2_VBATSNSP, 0, 0);
+	/* Allow interrupt to be serviced */
+	k_sleep(K_SECONDS(0.1));
+	zassert_false(
+		gpio_pin_get_dt(sm5803_emul_get_interrupt_gpio(SM5803_EMUL)),
+		"IRQ is still asserted");
+
+	/*
+	 * Interrupt handler logged voltages, then reset the threshold to reset
+	 * the interrupt, and programmed the expected threshold back.
+	 */
+	LOG_ASSERT_R(SM5803_ADDR_MEAS_FLAGS, SM5803_REG_VBATSNSP_MEAS_MSB);
+	LOG_ASSERT_R(SM5803_ADDR_MEAS_FLAGS, SM5803_REG_VBATSNSP_MEAS_LSB);
+	LOG_ASSERT_R(SM5803_ADDR_MEAS_FLAGS, SM5803_REG_VBATSNSP_MAX_TH);
+	LOG_ASSERT_W(SM5803_ADDR_MEAS_FLAGS, SM5803_REG_VBATSNSP_MAX_TH, 0xff);
+	LOG_ASSERT_W(SM5803_ADDR_MEAS_FLAGS, SM5803_REG_VBATSNSP_MAX_TH, 0xd8);
+	/* Interrupt handler also stopped sinking. */
+	sm5803_emul_get_flow_regs(SM5803_EMUL, &flow1, NULL, NULL);
+	zassert_equal(flow1, 0,
+		      "FLOW1 should disable charger, but value was %#x", flow1);
+}
+
+FAKE_VOID_FUNC(chipset_throttle_cpu, int);
+
+ZTEST(sm5803, test_thermal_throttle)
+{
+	/* Above 360K, charger throttles AP. */
+	sm5803_emul_set_internal_temperature(SM5803_EMUL, 362);
+	sm5803_emul_set_irqs(SM5803_EMUL, 0, SM5803_INT2_TINT, 0, 0);
+	sm5803_handle_interrupt(CHARGER_NUM);
+	zassert_equal(chipset_throttle_cpu_fake.call_count, 1);
+	zassert_equal(chipset_throttle_cpu_fake.arg0_val, 1);
+
+	/* Next watching only for temperature to drop below 330K. */
+	zassert_equal(sm5803_emul_get_tint_high_th(SM5803_EMUL), 0xff,
+		      "TINT_HIGH_TH should be set to maximum, but was %#x",
+		      sm5803_emul_get_tint_high_th(SM5803_EMUL));
+	zassert_equal(sm5803_emul_get_tint_low_th(SM5803_EMUL), 0xbf,
+		      "TINT_LOW_TH should be set to 330K, but was %#x",
+		      sm5803_emul_get_tint_low_th(SM5803_EMUL));
+
+	/* Falling below 330K, releases throttle. */
+	sm5803_emul_set_internal_temperature(SM5803_EMUL, 328);
+	sm5803_emul_set_irqs(SM5803_EMUL, 0, SM5803_INT2_TINT, 0, 0);
+	sm5803_handle_interrupt(CHARGER_NUM);
+	zassert_equal(chipset_throttle_cpu_fake.call_count, 2);
+	zassert_equal(chipset_throttle_cpu_fake.arg0_val, 0);
+
+	/* Watches for temperatures rising above 360K again. */
+	zassert_equal(sm5803_emul_get_tint_high_th(SM5803_EMUL), 0xd1,
+		      "TINT_HIGH_TH should be set to 360K, but was %#x",
+		      sm5803_emul_get_tint_high_th(SM5803_EMUL));
+	zassert_equal(sm5803_emul_get_tint_low_th(SM5803_EMUL), 0,
+		      "TINT_LOW_TH should be set to minimum, but was %#x",
+		      sm5803_emul_get_tint_low_th(SM5803_EMUL));
+}
+
+ZTEST(sm5803, test_bfet_limit_interrupt)
+{
+	/*
+	 * BFET limit interrupts don't take any action,
+	 * but do log some messages.
+	 */
+	sm5803_emul_set_irqs(SM5803_EMUL, 0, 0, SM5803_INT3_BFET_PWR_LIMIT, 0);
+	sm5803_handle_interrupt(CHARGER_NUM);
+	zassert_false(
+		gpio_pin_get_dt(sm5803_emul_get_interrupt_gpio(SM5803_EMUL)),
+		"IRQ is still asserted");
+}
+
+ZTEST_F(sm5803, test_chg_fail_interrupt)
+{
+	uint8_t flow1;
+
+	pd_connect_source(fixture);
+	sm5803_emul_get_flow_regs(SM5803_EMUL, &flow1, NULL, NULL);
+	zassert_equal(flow1, 1, "charger should be sinking, but FLOW1 was %#x",
+		      flow1);
+
+	/*
+	 * Overtemperature stops charging automatically and restarts after
+	 * 30 seconds.
+	 */
+	sm5803_emul_set_chg_status(SM5803_EMUL, SM5803_STATUS_CHG_OV_ITEMP);
+	sm5803_emul_set_irqs(SM5803_EMUL, 0, 0, 0, SM5803_INT4_CHG_FAIL);
+	sm5803_handle_interrupt(CHARGER_NUM);
+	/* Fault flag was cleared */
+	zassert_equal(sm5803_emul_get_chg_status(SM5803_EMUL), 0);
+	k_sleep(K_SECONDS(35));
+
+	/* Battery overvoltage is the same but restarts more quickly. */
+	sm5803_emul_set_chg_status(SM5803_EMUL, SM5803_STATUS_CHG_OV_VBAT);
+	sm5803_emul_set_irqs(SM5803_EMUL, 0, 0, 0, SM5803_INT4_CHG_FAIL);
+	sm5803_handle_interrupt(CHARGER_NUM);
+	zassert_equal(sm5803_emul_get_chg_status(SM5803_EMUL), 0);
+	k_sleep(K_SECONDS(5));
+}
+
+ZTEST(sm5803, test_chg_done_interrupt)
+{
+	/* CHG_DONE just logs a message and takes no further action. */
+	sm5803_emul_set_irqs(SM5803_EMUL, 0, 0, 0, SM5803_INT4_CHG_DONE);
+	sm5803_handle_interrupt(CHARGER_NUM);
+}
+
+FAKE_VOID_FUNC(board_overcurrent_event, int, int);
+
+ZTEST_F(sm5803, test_otg_fail_interrupt)
+{
+	sm5803_emul_set_disch_status(SM5803_EMUL,
+				     SM5803_STATUS_DISCHG_VBUS_SHORT);
+	sm5803_emul_set_irqs(SM5803_EMUL, 0, 0, 0, SM5803_INT4_OTG_FAIL);
+	sm5803_handle_interrupt(CHARGER_NUM);
+
+	/*
+	 * TODO(b/223901282): actually connect a sink so the overcurrent event
+	 * gets logged and we can verify that source mode got disabled.
+	 */
+	zassert_equal(board_overcurrent_event_fake.call_count, 0,
+		      "actual call count was %d",
+		      board_overcurrent_event_fake.call_count);
+}
+
+static void pd_disconnect(struct sm5803_fixture *fixture)
+{
+	if (pd_is_connected(CHARGER_NUM)) {
+		switch (pd_get_power_role(CHARGER_NUM)) {
+		case PD_ROLE_SOURCE:
+			zassert_ok(tcpci_emul_disconnect_partner(
+				fixture->tcpci_emul));
+			break;
+		case PD_ROLE_SINK:
+			set_ac_enabled(false);
+			zassert_ok(tcpci_emul_disconnect_partner(
+				fixture->tcpci_emul));
+			sm5803_emul_set_vbus_voltage(SM5803_EMUL, 0);
+			break;
+		}
+
+		k_sleep(K_SECONDS(1));
+	}
+}
+
+static void pd_connect_source(struct sm5803_fixture *fixture)
+{
+	fixture->partner.extensions =
+		tcpci_src_emul_init(&fixture->src_ext, &fixture->partner, NULL);
+
+	zassert_ok(tcpci_partner_connect_to_tcpci(&fixture->partner,
+						  fixture->tcpci_emul));
+	sm5803_emul_set_vbus_voltage(SM5803_EMUL, 5000);
+	k_sleep(K_SECONDS(10));
+	zassert_true(pd_is_connected(CHARGER_NUM));
+}
+
+static void *sm5803_test_setup(void)
+{
+	static struct sm5803_fixture fixture = {
+		.tcpci_emul = EMUL_GET_USBC_BINDING(0, tcpc),
+	};
+
+	return &fixture;
+}
+
+static void sm5803_before_test(void *data)
+{
+	struct sm5803_fixture *fixture = data;
+
+	/* Turn AP on so we're allowed to source on type-C. */
+	test_set_chipset_to_s0();
+	k_sleep(K_SECONDS(1));
+
+	tcpci_partner_init(&fixture->partner, PD_REV30);
+
+	/* Ensure the driver's cached device ID is a "typical" chip. */
+	dev_id = 3;
+
+	system_get_jump_tag_fake.custom_fake = NULL;
+	RESET_FAKE(board_overcurrent_event);
+}
+
+static void sm5803_after_test(void *data)
+{
+	struct sm5803_fixture *fixture = data;
+
+	pd_disconnect(fixture);
+}
diff --git a/zephyr/test/drivers/sm5803/src/usbc.c b/zephyr/test/drivers/sm5803/src/usbc.c
new file mode 100644
index 0000000000..8028842a04
--- /dev/null
+++ b/zephyr/test/drivers/sm5803/src/usbc.c
@@ -0,0 +1,42 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "driver/charger/sm5803.h"
+#include "driver/tcpm/tcpci.h"
+#include "emul/emul_sm5803.h"
+#include "test/drivers/charger_utils.h"
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+
+__override bool pd_check_vbus_level(int port, enum vbus_level level)
+{
+	return sm5803_check_vbus_level(port, level);
+}
+
+static void pin_interrupt_handler(const struct device *gpio,
+				  struct gpio_callback *const cb,
+				  gpio_port_pins_t pins)
+{
+	sm5803_interrupt(get_charger_num(&sm5803_drv));
+}
+
+static int configure_charger_interrupt(void)
+{
+	const struct gpio_dt_spec *gpio = sm5803_emul_get_interrupt_gpio(
+		EMUL_DT_GET(DT_NODELABEL(sm5803_emul)));
+	static struct gpio_callback callback;
+
+	if (!device_is_ready(gpio->port))
+		k_oops();
+
+	gpio_emul_input_set(gpio->port, gpio->pin, 1);
+	gpio_pin_configure_dt(gpio, GPIO_INPUT | GPIO_ACTIVE_LOW);
+	gpio_init_callback(&callback, pin_interrupt_handler, BIT(gpio->pin));
+	gpio_add_callback(gpio->port, &callback);
+	gpio_pin_interrupt_configure_dt(gpio, GPIO_INT_EDGE_TO_ACTIVE);
+
+	return 0;
+}
+SYS_INIT(configure_charger_interrupt, APPLICATION, 10);
diff --git a/zephyr/test/drivers/system/CMakeLists.txt b/zephyr/test/drivers/system/CMakeLists.txt
new file mode 100644
index 0000000000..c6fc144eae
--- /dev/null
+++ b/zephyr/test/drivers/system/CMakeLists.txt
@@ -0,0 +1,15 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Add source files
+target_sources(app PRIVATE src/system.c)
+
+target_sources_ifdef(CONFIG_PLATFORM_EC_BOARD_VERSION_CBI app PRIVATE
+src/system_board_version_cbi.c)
+
+target_sources_ifndef(CONFIG_PLATFORM_EC_BOARD_VERSION_CBI app PRIVATE
+src/system_board_version_default.c)
+
+target_sources_ifndef(CONFIG_HOST_CMD_AP_SET_SKUID app PRIVATE
+src/system_not_board_ap_set_sku_id.c)
diff --git a/zephyr/test/drivers/system/src/system.c b/zephyr/test/drivers/system/src/system.c
new file mode 100644
index 0000000000..051723f194
--- /dev/null
+++ b/zephyr/test/drivers/system/src/system.c
@@ -0,0 +1,313 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+#include "host_command.h"
+#include "mock/power.h"
+#include "panic.h"
+#include "system.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_mocks.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/shell/shell_dummy.h>
+#include <zephyr/ztest.h>
+
+FAKE_VALUE_FUNC(int, system_run_image_copy_with_flags, enum ec_image, int);
+FAKE_VOID_FUNC(system_disable_jump);
+FAKE_VOID_FUNC(jump_to_image, uintptr_t);
+
+/* System Host Commands */
+
+ZTEST_USER(system, test_hostcmd_sysinfo)
+{
+	struct ec_response_sysinfo response;
+	struct host_cmd_handler_args args;
+
+	/* Simply issue the command and get the results */
+	zassert_ok(ec_cmd_sysinfo(&args, &response), NULL);
+	zassert_equal(args.response_size, sizeof(response), NULL);
+	zassert_equal(response.reset_flags, 0, "response.reset_flags = %d",
+		      response.reset_flags);
+	zassert_equal(response.current_image, EC_IMAGE_RO,
+		      "response.current_image = %d", response.current_image);
+	zassert_equal(response.flags, 0, "response.flags = %d", response.flags);
+}
+
+/* System Function Testing */
+
+static void system_before_after(void *data)
+{
+	ARG_UNUSED(data);
+	system_clear_reset_flags(-1);
+
+	RESET_FAKE(system_run_image_copy_with_flags);
+	RESET_FAKE(system_disable_jump);
+	RESET_FAKE(jump_to_image);
+}
+
+ZTEST(system, test_system_enter_hibernate__at_g3)
+{
+	set_ac_enabled(false);
+	test_set_chipset_to_g3();
+
+	/* Reset after set to g3 */
+	chipset_force_shutdown_fake.call_count = 0;
+
+	/* Arbitrary Args */
+	system_enter_hibernate(0x12, 0x34);
+	zassert_equal(chipset_force_shutdown_fake.call_count, 0);
+	zassert_equal(system_hibernate_fake.call_count, 1);
+}
+
+ZTEST(system, test_system_enter_hibernate__ac_on)
+{
+	test_set_chipset_to_s0();
+	set_ac_enabled(true);
+
+	/* Arbitrary Args */
+	system_enter_hibernate(0x12, 0x34);
+	zassert_equal(chipset_force_shutdown_fake.call_count, 0);
+}
+
+ZTEST(system, test_system_enter_hibernate__at_s0)
+{
+	test_set_chipset_to_s0();
+	set_ac_enabled(false);
+
+	/* Arbitrary Args */
+	system_enter_hibernate(0x12, 0x34);
+
+	zassert_equal(chipset_force_shutdown_fake.call_count, 1);
+	zassert_equal(chipset_force_shutdown_fake.arg0_val,
+		      CHIPSET_SHUTDOWN_CONSOLE_CMD);
+}
+
+ZTEST(system, test_get_program_memory_addr_bad_args)
+{
+	zassert_equal(get_program_memory_addr(-1), INVALID_ADDR);
+}
+
+ZTEST(system, test_system_common_pre_init__watch_dog_panic)
+{
+	uint32_t reason;
+	uint32_t info;
+	uint8_t exception;
+
+	/* Watchdog reset should result in any existing panic data being
+	 * overwritten
+	 */
+	panic_set_reason(PANIC_SW_DIV_ZERO, 0x12, 0x34);
+
+	/* Clear all reset flags and set them arbitrarily */
+	system_set_reset_flags(EC_RESET_FLAG_WATCHDOG);
+	system_common_pre_init();
+	panic_get_reason(&reason, &info, &exception);
+	zassert_equal(reason, PANIC_SW_WATCHDOG);
+	zassert_equal(info, 0);
+	zassert_equal(exception, 0);
+}
+
+ZTEST(system, test_system_common_pre_init__watch_dog_panic_already_initialized)
+{
+	uint32_t reason;
+	uint32_t info;
+	uint8_t exception;
+
+	/* Watchdog reset should not overwrite panic info if already filled
+	 * in with watchdog panic info that HAS NOT been read by host
+	 */
+	panic_set_reason(PANIC_SW_WATCHDOG, 0x12, 0x34);
+
+	/* Clear all reset flags and set them arbitrarily */
+	system_set_reset_flags(EC_RESET_FLAG_WATCHDOG);
+	system_common_pre_init();
+	panic_get_reason(&reason, &info, &exception);
+	zassert_equal(reason, PANIC_SW_WATCHDOG);
+	zassert_equal(info, 0x12);
+	zassert_equal(exception, 0x34);
+}
+
+ZTEST(system, test_system_common_pre_init__watch_dog_panic_already_read)
+{
+	uint32_t reason;
+	uint32_t info;
+	uint8_t exception;
+	struct panic_data *pdata;
+
+	/* Watchdog reset should overwrite panic info if already filled
+	 * in with watchdog panic info that HAS been read by host
+	 */
+	panic_set_reason(PANIC_SW_WATCHDOG, 0x12, 0x34);
+	pdata = get_panic_data_write();
+	pdata->flags |= PANIC_DATA_FLAG_OLD_HOSTCMD;
+
+	/* Clear all reset flags and set them arbitrarily */
+	system_set_reset_flags(EC_RESET_FLAG_WATCHDOG);
+	system_common_pre_init();
+	panic_get_reason(&reason, &info, &exception);
+	zassert_equal(reason, PANIC_SW_WATCHDOG);
+	zassert_equal(info, 0);
+	zassert_equal(exception, 0);
+}
+
+ZTEST(system, test_system_encode_save_flags)
+{
+	int flags_to_save = 0;
+	uint32_t saved_flags = 0;
+	int arbitrary_reset_flags = 1;
+
+	/* Save all possible flags */
+	flags_to_save = -1;
+
+	/* Clear all reset flags and set them arbitrarily */
+	system_set_reset_flags(arbitrary_reset_flags);
+
+	system_encode_save_flags(flags_to_save, &saved_flags);
+
+	/* Verify all non-mutually exclusive flags */
+	zassert_equal(1, saved_flags & system_get_reset_flags(), NULL);
+	zassert_not_equal(0, saved_flags & EC_RESET_FLAG_AP_OFF, NULL);
+	zassert_not_equal(0, saved_flags & EC_RESET_FLAG_STAY_IN_RO, NULL);
+	zassert_not_equal(0, saved_flags & EC_RESET_FLAG_AP_WATCHDOG, NULL);
+}
+
+ZTEST(system, test_system_encode_save_flags_mutually_exclusive_reset_flags)
+{
+	int flags_to_save = 0;
+	uint32_t saved_flags = 0;
+
+	/* Verify reset hard takes precedence over hibernate/soft */
+	flags_to_save = SYSTEM_RESET_HARD | SYSTEM_RESET_HIBERNATE;
+
+	system_encode_save_flags(flags_to_save, &saved_flags);
+
+	zassert_not_equal(0, saved_flags & EC_RESET_FLAG_HARD, NULL);
+	zassert_equal(0, saved_flags & EC_RESET_FLAG_HIBERNATE, NULL);
+	zassert_equal(0, saved_flags & EC_RESET_FLAG_SOFT, NULL);
+
+	/* Verify reset hibernate takes precedence over soft */
+	flags_to_save = SYSTEM_RESET_HIBERNATE;
+
+	system_encode_save_flags(flags_to_save, &saved_flags);
+
+	zassert_equal(0, saved_flags & EC_RESET_FLAG_HARD, NULL);
+	zassert_not_equal(0, saved_flags & EC_RESET_FLAG_HIBERNATE, NULL);
+	zassert_equal(0, saved_flags & EC_RESET_FLAG_SOFT, NULL);
+
+	/* Verify reset soft is always saved given no other flags */
+	flags_to_save = 0;
+
+	system_encode_save_flags(flags_to_save, &saved_flags);
+
+	zassert_equal(0, saved_flags & EC_RESET_FLAG_HARD, NULL);
+	zassert_equal(0, saved_flags & EC_RESET_FLAG_HIBERNATE, NULL);
+	zassert_not_equal(0, saved_flags & EC_RESET_FLAG_SOFT, NULL);
+}
+
+/* System Console Commands */
+
+ZTEST_USER(system, test_console_cmd_sysjump__no_args)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+
+	/* No output from no-arg commands, so just test failure */
+	zassert_equal(shell_execute_cmd(shell_zephyr, "sysjump"),
+		      EC_ERROR_PARAM_COUNT);
+}
+
+ZTEST_USER(system, test_console_cmd_sysjump__RO)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+
+	/* Since we start at RO this acts as NOOP */
+	zassert_ok(shell_execute_cmd(shell_zephyr, "sysjump RO"));
+
+	zassert_equal(system_run_image_copy_with_flags_fake.call_count, 1);
+	zassert_equal(system_run_image_copy_with_flags_fake.arg0_val,
+		      EC_IMAGE_RO);
+	zassert_equal(system_run_image_copy_with_flags_fake.arg1_val,
+		      EC_RESET_FLAG_STAY_IN_RO);
+}
+
+ZTEST_USER(system, test_console_cmd_sysjump__RW)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+
+	zassert_ok(shell_execute_cmd(shell_zephyr, "sysjump RW"));
+	zassert_equal(system_run_image_copy_with_flags_fake.call_count, 1);
+	zassert_equal(system_run_image_copy_with_flags_fake.arg0_val,
+		      EC_IMAGE_RW);
+	zassert_equal(system_run_image_copy_with_flags_fake.arg1_val, 0);
+}
+
+ZTEST_USER(system, test_console_cmd_sysjump__A)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+
+	zassert_ok(shell_execute_cmd(shell_zephyr, "sysjump A"));
+	zassert_equal(system_run_image_copy_with_flags_fake.call_count, 1);
+	zassert_equal(system_run_image_copy_with_flags_fake.arg0_val,
+		      EC_IMAGE_RW);
+	zassert_equal(system_run_image_copy_with_flags_fake.arg1_val, 0);
+}
+
+ZTEST_USER(system, test_console_cmd_sysjump__B)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+
+	/* Downstream Zephyr isn't setup with A/B images */
+	zassert_equal(shell_execute_cmd(shell_zephyr, "sysjump B"),
+		      EC_ERROR_PARAM1);
+	zassert_equal(system_run_image_copy_with_flags_fake.call_count, 0);
+}
+
+ZTEST_USER(system, test_console_cmd_sysjump__disable)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+
+	zassert_ok(shell_execute_cmd(shell_zephyr, "sysjump disable"));
+	zassert_equal(system_run_image_copy_with_flags_fake.call_count, 0);
+	zassert_equal(system_disable_jump_fake.call_count, 1);
+}
+
+ZTEST_USER(system, test_console_cmd_sysjump__addr_while_sys_locked)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+
+	system_is_locked_fake.return_val = true;
+
+	/* No output to test against */
+	zassert_equal(shell_execute_cmd(shell_zephyr, "sysjump 0x1234"),
+		      EC_ERROR_ACCESS_DENIED);
+	zassert_equal(system_is_locked_fake.call_count, 1);
+}
+
+ZTEST_USER(system, test_console_cmd_sysjump__addr)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+
+	/* No output to test against */
+	zassert_ok(shell_execute_cmd(shell_zephyr, "sysjump 0x1234"));
+	zassert_equal(system_is_locked_fake.call_count, 1);
+	zassert_equal(jump_to_image_fake.call_count, 1);
+	zassert_equal(jump_to_image_fake.arg0_val, 0x1234);
+}
+
+ZTEST_USER(system, test_console_cmd_sysjump__addr_bad_number)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+
+	/* No output to test against */
+	zassert_equal(shell_execute_cmd(shell_zephyr, "sysjump O___o"),
+		      EC_ERROR_PARAM1);
+	zassert_equal(system_is_locked_fake.call_count, 1);
+	zassert_equal(jump_to_image_fake.call_count, 0);
+}
+
+ZTEST_SUITE(system, drivers_predicate_post_main, NULL, system_before_after,
+	    system_before_after, NULL);
diff --git a/zephyr/test/drivers/system/src/system_board_version_cbi.c b/zephyr/test/drivers/system/src/system_board_version_cbi.c
new file mode 100644
index 0000000000..cd4e40eef2
--- /dev/null
+++ b/zephyr/test/drivers/system/src/system_board_version_cbi.c
@@ -0,0 +1,41 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+#include "host_command.h"
+#include "system.h"
+#include "test/drivers/test_mocks.h"
+#include "test/drivers/test_state.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+FAKE_VALUE_FUNC(int, cbi_get_board_version, uint32_t *);
+
+#define ARBITRARY_VERSION 0x1234
+
+static int system_test_cbi_get_board_version(uint32_t *ver)
+{
+	*ver = ARBITRARY_VERSION;
+
+	return 0;
+}
+
+ZTEST(system, test_system_get_board_version)
+{
+	RESET_FAKE(cbi_get_board_version);
+	cbi_get_board_version_fake.custom_fake =
+		system_test_cbi_get_board_version;
+
+	zassert_equal(system_get_board_version(), ARBITRARY_VERSION);
+}
+
+ZTEST(system, test_system_get_board_version__bad_cbi_read)
+{
+	RESET_FAKE(cbi_get_board_version);
+	cbi_get_board_version_fake.return_val = EC_ERROR_BUSY;
+
+	zassert_equal(system_get_board_version(), -EC_ERROR_BUSY);
+}
diff --git a/zephyr/test/drivers/system/src/system_board_version_default.c b/zephyr/test/drivers/system/src/system_board_version_default.c
new file mode 100644
index 0000000000..d6fe399988
--- /dev/null
+++ b/zephyr/test/drivers/system/src/system_board_version_default.c
@@ -0,0 +1,21 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+#include "host_command.h"
+
+#include <zephyr/ztest.h>
+
+ZTEST_USER(system, test_hostcmd_board_version)
+{
+	struct ec_response_board_version response;
+	struct host_cmd_handler_args args;
+
+	/* Get the board version, which is default 0. */
+	zassert_ok(ec_cmd_get_board_version(&args, &response), NULL);
+	zassert_equal(args.response_size, sizeof(response), NULL);
+	zassert_equal(response.board_version, 0, "response.board_version = %d",
+		      response.board_version);
+}
diff --git a/zephyr/test/drivers/system/src/system_not_board_ap_set_sku_id.c b/zephyr/test/drivers/system/src/system_not_board_ap_set_sku_id.c
new file mode 100644
index 0000000000..2d4e60fdcb
--- /dev/null
+++ b/zephyr/test/drivers/system/src/system_not_board_ap_set_sku_id.c
@@ -0,0 +1,18 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "system.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+/* Tests for !CONFIG_HOST_CMD_AP_SET_SKUID */
+
+#define DEFAULT_BOARD_PROVIDED_SKU_ID 0
+
+ZTEST(system, test_system_get_sku_id_default_board_provided_value)
+{
+	zassert_equal(system_get_sku_id(), DEFAULT_BOARD_PROVIDED_SKU_ID);
+}
diff --git a/zephyr/test/drivers/testcase.yaml b/zephyr/test/drivers/testcase.yaml
new file mode 100644
index 0000000000..d1f00ff689
--- /dev/null
+++ b/zephyr/test/drivers/testcase.yaml
@@ -0,0 +1,542 @@
+common:
+  platform_allow: native_posix
+tests:
+  drivers.default:
+    timeout: 360
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_DEFAULT=y
+    - CONFIG_LINK_TEST_SUITE_USB_MALFUNCTION_SINK=y
+    - CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y
+    - CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y
+    - CONFIG_PLATFORM_EC_USB_PD_DPS=y
+    - CONFIG_PLATFORM_EC_I2C_PASSTHRU_RESTRICTED=y
+    - CONFIG_PLATFORM_EC_CONSOLE_CMD_TCPC_DUMP=y
+    extra_conf_files:
+    - prj.conf
+    - default/prj.conf
+    extra_dtc_overlay_files:
+    - default/boards/native_posix.overlay
+  drivers.default.bring_up:
+    timeout: 360
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_DEFAULT=y
+    - CONFIG_LINK_TEST_SUITE_USB_MALFUNCTION_SINK=y
+    - CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y
+    - CONFIG_PLATFORM_EC_BRINGUP=y
+    - CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y
+    - CONFIG_PLATFORM_EC_USB_PD_DPS=y
+    - CONFIG_PLATFORM_EC_I2C_PASSTHRU_RESTRICTED=y
+    extra_conf_files:
+    - prj.conf
+    - default/prj.conf
+    extra_dtc_overlay_files:
+    - default/boards/native_posix.overlay
+  drivers.default.console_cmds:
+    timeout: 360
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_DEFAULT_CONSOLE_CMDS=y
+    - CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y
+    extra_conf_files:
+    - prj.conf
+    - default/prj.conf
+    extra_dtc_overlay_files:
+    - default/boards/native_posix.overlay
+  drivers.default.console_cmds.gpio_keys:
+    timeout: 360
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_DEFAULT_CONSOLE_CMDS=y
+    - CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y
+    - CONFIG_PLATFORM_EC_POWER_BUTTON=n
+    extra_conf_files:
+    - prj.conf
+    - default/prj.conf
+    extra_dtc_overlay_files:
+    - default/boards/native_posix.overlay
+    - default/boards/power_button.dtsi
+  drivers.default.mock_power:
+    timeout: 360
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_DEFAULT=y
+    - CONFIG_LINK_TEST_SUITE_USB_MALFUNCTION_SINK=y
+    - CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y
+    - CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y
+    - CONFIG_POWER_SEQUENCE_MOCK=y
+    - CONFIG_PLATFORM_EC_USB_PD_DPS=y
+    - CONFIG_PLATFORM_EC_I2C_PASSTHRU_RESTRICTED=y
+    extra_conf_files:
+    - prj.conf
+    - default/prj.conf
+    extra_dtc_overlay_files:
+    - default/boards/native_posix.overlay
+  drivers.amd_fp6_usb_mux:
+    extra_dtc_overlay_files:
+    - ./boards/native_posix.overlay
+    - ./amd_fp6_usb_mux/usbc.dts
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_AMD_FP6_USB_MUX=y
+  drivers.anx7447:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_ANX7447=y
+    extra_conf_files:
+    - prj.conf
+    - anx7447/prj.conf
+    extra_dtc_overlay_files:
+    - ./boards/native_posix.overlay
+    - ./anx7447/tcpc_policy.dts
+  drivers.ap_mux_control:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_AP_MUX_CONTROL=y
+    extra_conf_files:
+    - prj.conf
+    - ap_mux_control/prj.conf
+  drivers.ap_vdm_control:
+    timeout: 360
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_AP_VDM_CONTROL=y
+    extra_conf_files:
+    - prj.conf
+    - ap_vdm_control/prj.conf
+  drivers.ap_vdm_control_disabled:
+    extra_configs:
+    - CONFIG_PLATFORM_EC_USB_PD_VDM_AP_CONTROL=n
+    - CONFIG_LINK_TEST_SUITE_AP_VDM_CONTROL=y
+    extra_conf_files:
+    - prj.conf
+    - ap_vdm_control/prj.conf
+  drivers.button:
+    timeout: 360
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_BUTTON=y
+    - CONFIG_PLATFORM_EC_CMD_BUTTON=y
+    - CONFIG_PLATFORM_EC_VOLUME_BUTTONS=y
+    - CONFIG_PLATFORM_EC_EMULATED_SYSRQ=y
+  drivers.cbi_flash:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_CBI_FLASH=y
+    - CONFIG_PLATFORM_EC_CBI_FLASH=y
+    - CONFIG_PLATFORM_EC_FLASH_SIZE_BYTES=0x80000
+    extra_dtc_overlay_files:
+    - ./boards/native_posix.overlay
+    - ./cbi_flash/binman.dts
+  drivers.common_cbi:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_COMMON_CBI=y
+    - CONFIG_PLATFORM_EC_EEPROM_CBI_WP=y
+  drivers.common_cbi_gpio:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_COMMON_CBI_GPIO=y
+    - CONFIG_PLATFORM_EC_CBI_GPIO=y
+  drivers.common_charger:
+    extra_configs:
+    - CONFIG_PLATFORM_EC_CHARGER_INPUT_CURRENT_DERATE_PCT=5
+    - CONFIG_PLATFORM_EC_CHARGER_MIN_INPUT_CURRENT_LIMIT=100
+    - CONFIG_LINK_TEST_SUITE_COMMON_CHARGER=y
+    # Set to focus testing for Herobrine
+    # Config is y only in nissa
+    - CONFIG_PLATFORM_EC_CHARGER_RAA489000=n
+    - CONFIG_PLATFORM_EC_CHARGER_RUNTIME_CONFIG=y
+  drivers.chargesplash:
+    timeout: 360
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_CHARGESPLASH=y
+  drivers.chargesplash.mock_power:
+    timeout: 360
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_CHARGESPLASH=y
+    - CONFIG_POWER_SEQUENCE_MOCK=y
+  drivers.console:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_CONSOLE=y
+  drivers.console_cmd_crash:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_CONSOLE_CMD_CRASH=y
+    - CONFIG_PLATFORM_EC_CONSOLE_CMD_CRASH=y
+    - CONFIG_ASSERT_TEST=y
+    extra_conf_files:
+    - prj.conf
+    - default/prj.conf
+    extra_dtc_overlay_files:
+    - default/boards/native_posix.overlay
+  drivers.console_cmd_mfallow:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_CONSOLE_CMD_MFALLOW=y
+    extra_conf_files:
+    - prj.conf
+    - console_cmd_mfallow/prj.conf
+  drivers.cros_flash:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_CROS_FLASH=y
+    - CONFIG_CROS_FLASH_BACKEND_FAKE=y
+    - CONFIG_CROS_FLASH_READOUT_PROTECTION=y
+    - CONFIG_PLATFORM_EC_INTERNAL_STORAGE=y
+    - CONFIG_PLATFORM_EC_FLASH_INIT_PRIORITY=60
+    - CONFIG_PLATFORM_EC_SYSTEM_PRE_INIT_PRIORITY=72
+    extra_dtc_overlay_files:
+    - cros_flash/boards/native_posix.overlay
+  drivers.dps:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_USB_PD_DPS=y
+    extra_conf_files:
+    - prj.conf
+    - dps/prj.conf
+  drivers.flash:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_FLASH=y
+    - CONFIG_PLATFORM_EC_CONSOLE_CMD_FLASH=y
+  drivers.flash.page_layout:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_FLASH=y
+    - CONFIG_SHELL_BACKEND_DUMMY_BUF_SIZE=500
+    - CONFIG_PLATFORM_EC_CONSOLE_CMD_FLASH=y
+    - CONFIG_PLATFORM_EC_USE_ZEPHYR_FLASH_PAGE_LAYOUT=y
+  drivers.gpio_unhook:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_GPIO_UNHOOK=y
+    - CONFIG_GPIO_GET_CONFIG=y
+  drivers.host_cmd:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_HOST_COMMANDS=y
+    - CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y
+    - CONFIG_PLATFORM_EC_USB_PD_LOGGING=y
+    - CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y
+    - CONFIG_PLATFORM_EC_HOST_COMMAND_STATUS=y
+  drivers.host_cmd_read_memmap:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_HOST_COMMAND_READ_MEMMAP=y
+    - CONFIG_PLATFORM_EC_HOST_COMMAND_STATUS=y
+    - CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI=n
+    - CONFIG_PLATFORM_EC_HOST_INTERFACE_SHI=y
+  drivers.host_cmd_read_memmap.no_switches:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_HOST_COMMAND_READ_MEMMAP=y
+    - CONFIG_PLATFORM_EC_HOST_COMMAND_STATUS=y
+    - CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI=n
+    - CONFIG_PLATFORM_EC_HOST_INTERFACE_SHI=y
+    - CONFIG_PLATFORM_EC_SWITCH=n
+  drivers.icm42607:
+    extra_configs:
+    - CONFIG_PLATFORM_EC_ACCELGYRO_BMI160=n
+    - CONFIG_LINK_TEST_SUITE_ICM42607=y
+    - CONFIG_PLATFORM_EC_ACCELGYRO_ICM42607=y
+    - CONFIG_PLATFORM_EC_ACCELGYRO_ICM_COMM_I2C=y
+    extra_dtc_overlay_files:
+    - ./boards/native_posix.overlay
+    - ./icm42607/sensor.dts
+  drivers.isl923x:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_ISL923X=y
+  drivers.isl923x.mock_power:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_ISL923X=y
+    - CONFIG_POWER_SEQUENCE_MOCK=y
+  drivers.isl9241:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_ISL9241=y
+    - CONFIG_PLATFORM_EC_CHARGER_DUMP_PROCHOT=y
+    - CONFIG_PLATFORM_EC_CHARGER_ISL9241=y
+    extra_dtc_overlay_files:
+    - ./boards/native_posix.overlay
+    - ./isl9241/usbc.dts
+  drivers.i2c_controller:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_I2C_CONTROLLER=y
+    extra_dtc_overlay_files:
+    - ./boards/native_posix.overlay
+    - i2c_controller/i2c.dts
+  drivers.it8xxx2_hw_sha256:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_IT8XXX2_HW_SHA256=y
+    - CONFIG_PLATFORM_EC_SHA256_HW_ACCELERATE=y
+  drivers.keyboard_8042:
+    extra_configs:
+    - CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_MKBP=n
+    - CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_8042=y
+    - CONFIG_LINK_TEST_SUITE_KEYBOARD_8042=y
+  drivers.keyboard_scan:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_KEYBOARD_SCAN=y
+  drivers.led_driver:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_LED_DRIVER=y
+    extra_conf_files:
+    - prj.conf
+    - led_driver/prj.conf
+    extra_dtc_overlay_files:
+    - ./boards/native_posix.overlay
+    - ./led_driver/led_pins.dts
+    - ./led_driver/led_policy.dts
+  drivers.led_common:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_LED_COMMON=y
+    - CONFIG_PLATFORM_EC_LED_DT=n
+  drivers.locate_chip:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_LOCATE_CHIP_ALTS=y
+    - CONFIG_PLATFORM_EC_CBI=n
+  drivers.mkbp:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_MKBP=y
+    - CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_MKBP=y
+    - CONFIG_PLATFORM_EC_MKBP_INPUT_DEVICES=y
+    - CONFIG_PLATFORM_EC_MKBP_EVENT=y
+    - CONFIG_PLATFORM_EC_MKBP_USE_GPIO=y
+    - CONFIG_PLATFORM_EC_KEYBOARD_KEYPAD=y
+    tags: common mkbp
+  drivers.nct38xx:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_NCT38XX=y
+    - CONFIG_PLATFORM_EC_USB_PD_TCPC_LOW_POWER=y
+    extra_dtc_overlay_files:
+    - ./boards/native_posix.overlay
+    - ./nct38xx/tcpc_policy.dts
+  drivers.nx20p3481:
+    extra_dtc_overlay_files:
+    - ./boards/native_posix.overlay
+    - ./nx20p348x/usbc.dts
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_NX20P348X=y
+    - CONFIG_PLATFORM_EC_USBC_PPC_NX20P3481=y
+    - CONFIG_PLATFORM_EC_USBC_PPC_NX20P3483=n
+  drivers.nx20p3483:
+    extra_dtc_overlay_files:
+    - ./boards/native_posix.overlay
+    - ./nx20p348x/usbc.dts
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_NX20P348X=y
+    - CONFIG_PLATFORM_EC_USBC_PPC_NX20P3483=y
+  drivers.panic_output:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_PANIC_OUTPUT=y
+    - CONFIG_PLATFORM_EC_CONSOLE_CMD_CRASH=y
+    - CONFIG_PLATFORM_EC_DEBUG_ASSERT_REBOOTS=y
+    - CONFIG_ZTEST_THREAD_PRIORITY=1
+  drivers.power_host_sleep:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_POWER_HOST_SLEEP=y
+    # Make tests independent of chipset specific code
+    - CONFIG_AP_ARM_QUALCOMM_SC7280=n
+    - CONFIG_PLATFORM_EC_POWERSEQ_SC7280=n
+    - CONFIG_POWER_SEQUENCE_MOCK=y
+    - CONFIG_PLATFORM_EC_POWERSEQ_HOST_SLEEP=y
+    - CONFIG_PLATFORM_EC_POWERSEQ_S0IX=y
+  drivers.ps8xxx:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_PS8XXX=y
+    extra_conf_files:
+    - prj.conf
+    - ps8xxx/prj.conf
+    extra_dtc_overlay_files:
+    - ./boards/native_posix.overlay
+    - ./ps8xxx/usbc.dts"
+  drivers.rt1718s:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_RT1718S=y
+    extra_conf_files:
+    - prj.conf
+    - rt1718s/prj.conf
+    extra_dtc_overlay_files:
+    - ./boards/native_posix.overlay
+    - ./rt1718s/ppc_tcpc.dts
+  drivers.rt9490:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_RT9490=y
+    extra_conf_files:
+    - prj.conf
+    - rt9490/prj.conf
+    extra_dtc_overlay_files:
+    - ./boards/native_posix.overlay
+    - ./rt9490/charger.dts
+  drivers.random:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_RANDOM=y
+    - CONFIG_PLATFORM_EC_RANDOM=y
+    - CONFIG_PLATFORM_EC_HOSTCMD_RAND=y
+    - CONFIG_PLATFORM_EC_CONSOLE_CMD_RAND=y
+    extra_dtc_overlay_files:
+    - ./boards/native_posix.overlay
+  drivers.shim_gpio_id:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_SHIM_GPIO_ID=y
+    extra_conf_files:
+    - prj.conf
+    extra_dtc_overlay_files:
+    - boards/native_posix.overlay
+    - shim_gpio_id/gpio_id.dts
+  drivers.shim_pwm_hc:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_SHIM_PWM_HC=y
+  drivers.shim_rtc:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_SHIM_RTC=y
+    - CONFIG_PLATFORM_EC_RTC=y
+    - CONFIG_PLATFORM_EC_HOSTCMD=y
+    - CONFIG_PLATFORM_EC_HOSTCMD_RTC=y
+  drivers.sm5803:
+    extra_conf_files:
+    - prj.conf
+    - sm5803/prj.conf
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_SM5803=y
+    extra_dtc_overlay_files:
+    - boards/native_posix.overlay
+    - sm5803/sm5803.dts
+  drivers.system:
+    tags: common system
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_SYSTEM=y
+    - CONFIG_POWER_SEQUENCE_MOCK=y
+  drivers.system_board_version_cbi:
+    tags: common system
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_SYSTEM=y
+    - CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=y
+    - CONFIG_POWER_SEQUENCE_MOCK=y
+  drivers.timer:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_TIMER=y
+  drivers.usb_common:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_USB_COMMON=y
+  drivers.usb_port_power_dumb:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_USB_PORT_POWER_DUMB=y
+    - CONFIG_PLATFORM_EC_USB_PORT_POWER_DUMB=y
+    extra_dtc_overlay_files:
+    - ./boards/native_posix.overlay
+    - ./usb_port_power_dumb/usba.dts
+  drivers.usb_pd_discharge:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_USB_COMMON=y
+    - CONFIG_PLATFORM_EC_USB_PD_DISCHARGE=y
+    - CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y
+    - CONFIG_PLATFORM_EC_USB_PD_FLAGS=y
+  drivers.usb_pd_discovery:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_USB_PD_DISCOVERY=y
+  drivers.usb_pd_flags:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_USB_COMMON=y
+    - CONFIG_PLATFORM_EC_USB_PD_FLAGS=y
+    - CONFIG_PLATFORM_EC_USB_PD_RUNTIME_FLAGS=y
+  drivers.usb_retimer_fw_update:
+    timeout: 120
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_USB_RETIMER_FW_UPDATE=y
+    extra_conf_files:
+    - prj.conf
+    - usb_retimer_fw_update/prj.conf
+  drivers.usbc_alt_mode:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_USBC_ALT_MODE=y
+    timeout: 120
+    extra_conf_files:
+    - prj.conf
+    - usbc_alt_mode/prj.conf
+  drivers.usbc_alt_mode_ec_entry:
+    timeout: 120
+    extra_configs:
+    - CONFIG_PLATFORM_EC_USB_PD_REQUIRE_AP_MODE_ENTRY=n
+    - CONFIG_LINK_TEST_SUITE_USBC_ALT_MODE=y
+    - CONFIG_POWER_SEQUENCE_MOCK=y
+    extra_conf_files:
+    - prj.conf
+    - usbc_alt_mode/prj.conf
+  drivers.usbc_console_pd:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_USBC_CONSOLE_PD=y
+  drivers.usbc_console_pd_legacy:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_USBC_CONSOLE_PD=y
+    - CONFIG_PLATFORM_EC_TCPC_INTERRUPT=n
+    extra_dtc_overlay_files:
+    - default/boards/native_posix.overlay
+    - ./usbc_console_pd/usbc_legacy.dts
+  drivers.usbc_ctvpd:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_USBC_CTVPD=y
+  drivers.usbc_frs:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_USBC_FRS=y
+    - CONFIG_PLATFORM_EC_USB_PD_FRS_TCPC=y
+  drivers.usbc_ocp:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_USBC_OCP=y
+  drivers.usbc_ppc:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_USBC_PPC=y
+    - CONFIG_PLATFORM_EC_BC12_SINGLE_DRIVER=n
+    extra_dtc_overlay_files:
+    - default/boards/native_posix.overlay
+    - ./usbc_ppc/ppc_alts.dts
+  drivers.usbc_tcpc:
+    extra_dtc_overlay_files:
+    - default/boards/native_posix.overlay
+    - usbc_tcpc/tcpc_alts.dts
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_USBC_TCPC=y
+    - CONFIG_PLATFORM_EC_USB_PD_DUAL_ROLE_AUTO_TOGGLE=n
+    - CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_TCPC=n
+  drivers.usbc_retimer.anx7483:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_USBC_RETIMER_ANX7483=y
+  drivers.usbc_retimer.ps8811:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_USBC_RETIMER_PS8811=y
+  drivers.usbc_svdm_dfp_only:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_USBC_SVDM_DFP_ONLY=y
+    extra_conf_files:
+    - prj.conf
+    - usbc_svdm_dfp_only/prj.conf
+    extra_dtc_overlay_files:
+    - usbc_svdm_dfp_only/boards/native_posix.overlay
+  drivers.usbc_tbt_mode:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_USBC_TBT_MODE=y
+  drivers.usbc_usb4_mode:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_USBC_USB4_MODE=y
+    - CONFIG_PLATFORM_EC_USB_PD_DATA_RESET_MSG=y
+  drivers.usbc_vconn_swap:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_USBC_VCONN_SWAP=y
+  drivers.host_cmd_thread:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_HOST_CMD_THREAD=y
+    - CONFIG_TASK_HOSTCMD_THREAD_MAIN=y
+  drivers.pi3usb9201:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_PI3USB9201=y
+  drivers.memmap:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_MEMMAP=y
+  drivers.host_command_memory_dump:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_HOST_COMMAND_MEMORY_DUMP=y
+    - CONFIG_PLATFORM_EC_HOST_COMMAND_MEMORY_DUMP=y
+    - CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_8042=y
+  drivers.anx7452:
+    extra_conf_files:
+    - prj.conf
+    - anx7452/prj.conf
+    extra_dtc_overlay_files:
+    - boards/native_posix.overlay
+    - anx7452/usbc.dts
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_ANX7452=y
+  drivers.flash_cbi:
+    extra_dtc_overlay_files:
+    - boards/native_posix.overlay
+    - cbi_flash/binman.dts
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_FLASH=y
+    - CONFIG_PLATFORM_EC_CONSOLE_CMD_FLASH=y
+    - CONFIG_PLATFORM_EC_FLASH_SIZE_BYTES=0x80000
+    - CONFIG_PLATFORM_EC_CBI_FLASH=y
+  drivers.body_detection:
+    extra_configs:
+    - CONFIG_LINK_TEST_SUITE_BODY_DETECTION=y
+    - CONFIG_PLATFORM_EC_BODY_DETECTION=y
+    - CONFIG_PLATFORM_EC_BODY_DETECTION_ALWAYS_ENABLE_IN_S0=y
+    - CONFIG_PLATFORM_EC_BODY_DETECTION_NOTIFY_MODE_CHANGE=y
+    - CONFIG_PLATFORM_EC_GESTURE_HOST_DETECTION=y
diff --git a/zephyr/test/drivers/timer/CMakeLists.txt b/zephyr/test/drivers/timer/CMakeLists.txt
new file mode 100644
index 0000000000..8327ccdafb
--- /dev/null
+++ b/zephyr/test/drivers/timer/CMakeLists.txt
@@ -0,0 +1,7 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_sources(app PRIVATE
+  src/timer.c
+)
diff --git a/zephyr/test/drivers/timer/src/timer.c b/zephyr/test/drivers/timer/src/timer.c
new file mode 100644
index 0000000000..abc5d0a88f
--- /dev/null
+++ b/zephyr/test/drivers/timer/src/timer.c
@@ -0,0 +1,139 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "console.h"
+#include "host_command.h"
+#include "test/drivers/test_state.h"
+#include "timer.h"
+
+#include <zephyr/fff.h>
+#include <zephyr/shell/shell_dummy.h>
+#include <zephyr/ztest.h>
+
+BUILD_ASSERT(IS_ENABLED(CONFIG_HWTIMER_64BIT),
+	     "Tests expect the 64-bit HW timer");
+
+/**
+ * @brief Sets the timestamp returned by the system_get_jump_tag mock. Set to
+ *        UNIT64_MAX to make the mock return NULL.
+ */
+static uint64_t jump_tag_time;
+
+/* Sets the initial timer value */
+FAKE_VALUE_FUNC(int, __hw_clock_source_init64, uint64_t);
+
+FAKE_VALUE_FUNC(uint8_t *, system_get_jump_tag, uint16_t, int *, int *);
+
+ZTEST(timer, test_init_from_jump_tag)
+{
+	/* When initializing after a system jump, the timer should get set to
+	 * the time before the jump (stored in a jump tag)
+	 */
+
+	/* Set up mock to return this time */
+	jump_tag_time = 0x0123456789abcdef;
+
+	timer_init();
+
+	zassert_equal(1, system_get_jump_tag_fake.call_count, NULL);
+	zassert_equal(1, __hw_clock_source_init64_fake.call_count, NULL);
+	zassert_equal(jump_tag_time,
+		      __hw_clock_source_init64_fake.arg0_history[0], NULL);
+}
+
+ZTEST(timer, test_init_from_zero)
+{
+	/* When there is no jump tag, the timer should initialize to zero. */
+
+	/* Simulate no jump tag stored */
+	jump_tag_time = UINT64_MAX;
+
+	timer_init();
+
+	zassert_equal(1, system_get_jump_tag_fake.call_count, NULL);
+	zassert_equal(1, __hw_clock_source_init64_fake.call_count, NULL);
+	zassert_equal(0, __hw_clock_source_init64_fake.arg0_history[0], NULL);
+}
+
+ZTEST(timer, test_console_cmd_gettime)
+{
+	/* Should print the current time */
+	timestamp_t fake_time;
+	const char *outbuffer;
+	size_t buffer_size;
+
+	/* Make get_time() return a mocked value */
+	fake_time.val = 100;
+	get_time_mock = &fake_time;
+
+	shell_backend_dummy_clear_output(get_ec_shell());
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "gettime"), NULL);
+	outbuffer =
+		shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+
+	zassert_ok(!strstr(outbuffer, "Time: 0x0000000000000064 = 0.000100 s"),
+		   "Actual: '%s'", outbuffer);
+}
+
+ZTEST(timer, test_console_cmd_timerinfo)
+{
+	/* Prints current time and info on running timers. */
+	timestamp_t fake_time;
+	const char *outbuffer;
+	size_t buffer_size;
+
+	/* Make get_time() return a mocked value */
+	fake_time.val = 100;
+	get_time_mock = &fake_time;
+
+	shell_backend_dummy_clear_output(get_ec_shell());
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "timerinfo"), NULL);
+	outbuffer =
+		shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+
+	zassert_ok(!strstr(outbuffer,
+			   "Time:     0x0000000000000064 us,    0.000100 s"),
+		   "Actual: '%s'", outbuffer);
+
+	/* Task timer information not printed here if running in a Zephyr EC */
+}
+
+/**
+ * @brief Custom fake for system_get_jump_tag
+ *
+ * @param tag Which jump tag to retrieve, ignored in this application.
+ * @param version Output param to write jump tag version
+ * @param size Output param to write tag size
+ * @return uint8_t* Pointer to tag data
+ */
+static uint8_t *system_get_jump_tag_custom_fake(uint16_t tag, int *version,
+						int *size)
+{
+	ARG_UNUSED(tag);
+
+	/* Pretend the tag doesn't exist if set to this value */
+	if (jump_tag_time == UINT64_MAX) {
+		return NULL;
+	}
+
+	if (version)
+		*version = 1;
+	if (size)
+		*size = sizeof(jump_tag_time);
+	return (uint8_t *)&jump_tag_time;
+}
+
+static void reset(void *data)
+{
+	ARG_UNUSED(data);
+
+	/* Disable get_time() mocked return value */
+	get_time_mock = NULL;
+
+	RESET_FAKE(__hw_clock_source_init64);
+	RESET_FAKE(system_get_jump_tag)
+	system_get_jump_tag_fake.custom_fake = system_get_jump_tag_custom_fake;
+}
+
+ZTEST_SUITE(timer, drivers_predicate_post_main, NULL, reset, reset, NULL);
diff --git a/zephyr/test/drivers/usb_common/CMakeLists.txt b/zephyr/test/drivers/usb_common/CMakeLists.txt
new file mode 100644
index 0000000000..0f05eb1e54
--- /dev/null
+++ b/zephyr/test/drivers/usb_common/CMakeLists.txt
@@ -0,0 +1,15 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(usb_flags)
+
+target_include_directories(app PRIVATE "include")
+
+target_sources(app PRIVATE "src/suite.c" "src/usb_common.c")
+target_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_RUNTIME_FLAGS app PRIVATE
+	"src/usb_pd_flags.c")
+target_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_DISCHARGE app PRIVATE
+	"src/usb_pd_discharge.c")
diff --git a/zephyr/test/drivers/usb_common/include/suite.h b/zephyr/test/drivers/usb_common/include/suite.h
new file mode 100644
index 0000000000..d76fca46b9
--- /dev/null
+++ b/zephyr/test/drivers/usb_common/include/suite.h
@@ -0,0 +1,9 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/fff.h>
+
+DECLARE_FAKE_VALUE_FUNC(int, board_vbus_source_enabled, int);
+DECLARE_FAKE_VALUE_FUNC(int, ppc_discharge_vbus, int, int);
diff --git a/zephyr/test/drivers/usb_common/src/suite.c b/zephyr/test/drivers/usb_common/src/suite.c
new file mode 100644
index 0000000000..36d3031881
--- /dev/null
+++ b/zephyr/test/drivers/usb_common/src/suite.c
@@ -0,0 +1,23 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "suite.h"
+
+#include <zephyr/fff.h>
+#include <zephyr/ztest_test_new.h>
+
+DEFINE_FAKE_VALUE_FUNC(int, board_vbus_source_enabled, int);
+DEFINE_FAKE_VALUE_FUNC(int, ppc_discharge_vbus, int, int);
+
+static void usb_pd_flags_after(void *fixture)
+{
+	RESET_FAKE(board_vbus_source_enabled);
+	RESET_FAKE(ppc_discharge_vbus);
+}
+
+/* TODO(b/255413715): Convert this suite to use the unit testing framework when
+ * practical.
+ */
+ZTEST_SUITE(usb_common, NULL, NULL, usb_pd_flags_after, NULL, NULL);
diff --git a/zephyr/test/drivers/usb_common/src/usb_common.c b/zephyr/test/drivers/usb_common/src/usb_common.c
new file mode 100644
index 0000000000..f286a4ffc9
--- /dev/null
+++ b/zephyr/test/drivers/usb_common/src/usb_common.c
@@ -0,0 +1,298 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+#include "suite.h"
+#include "timer.h"
+#include "usb_common.h"
+#include "usb_pd.h"
+
+#include <stdint.h>
+
+#include <zephyr/fff.h>
+#include <zephyr/ztest_assert.h>
+#include <zephyr/ztest_test_new.h>
+
+#define TEST_PORT 0
+
+ZTEST_USER(usb_common, test_get_typec_current_limit_detached)
+{
+	/* If both CC lines are open, current limit should be 0 A. */
+	typec_current_t current = usb_get_typec_current_limit(
+		POLARITY_CC1, TYPEC_CC_VOLT_OPEN, TYPEC_CC_VOLT_OPEN);
+	zassert_equal(current & TYPEC_CURRENT_ILIM_MASK, 0);
+	zassert_equal(current & TYPEC_CURRENT_DTS_MASK, 0);
+}
+
+ZTEST_USER(usb_common, test_get_typec_current_limit_rp_default)
+{
+	/* USB Default current is 500 mA. */
+	typec_current_t current = usb_get_typec_current_limit(
+		POLARITY_CC1, TYPEC_CC_VOLT_RP_DEF, TYPEC_CC_VOLT_OPEN);
+	zassert_equal(current & TYPEC_CURRENT_ILIM_MASK, 500);
+	zassert_equal(current & TYPEC_CURRENT_DTS_MASK, 0);
+}
+
+ZTEST_USER(usb_common, test_get_typec_current_limit_rp_1500)
+{
+	typec_current_t current = usb_get_typec_current_limit(
+		POLARITY_CC1, TYPEC_CC_VOLT_RP_1_5, TYPEC_CC_VOLT_OPEN);
+	zassert_equal(current & TYPEC_CURRENT_ILIM_MASK, 1500);
+	zassert_equal(current & TYPEC_CURRENT_DTS_MASK, 0);
+}
+
+ZTEST_USER(usb_common, test_get_typec_current_limit_rp_3000)
+{
+	typec_current_t current = usb_get_typec_current_limit(
+		POLARITY_CC1, TYPEC_CC_VOLT_RP_3_0, TYPEC_CC_VOLT_OPEN);
+	zassert_equal(current & TYPEC_CURRENT_ILIM_MASK, 3000);
+	zassert_equal(current & TYPEC_CURRENT_DTS_MASK, 0);
+}
+
+ZTEST_USER(usb_common, test_get_typec_current_limit_rp_dts)
+{
+	/* For a DTS source, Rp 3A/Rp 1.5A indicates USB default current. The
+	 * DTS flag should be set.
+	 */
+	typec_current_t current = usb_get_typec_current_limit(
+		POLARITY_CC1, TYPEC_CC_VOLT_RP_3_0, TYPEC_CC_VOLT_RP_1_5);
+	zassert_equal(current & TYPEC_CURRENT_ILIM_MASK, 500);
+	zassert_equal(current & TYPEC_CURRENT_DTS_MASK, TYPEC_CURRENT_DTS_MASK);
+}
+
+ZTEST_USER(usb_common, test_get_snk_polarity)
+{
+	zassert_equal(get_snk_polarity(TYPEC_CC_VOLT_RP_3_0,
+				       TYPEC_CC_VOLT_OPEN),
+		      POLARITY_CC1);
+	zassert_equal(get_snk_polarity(TYPEC_CC_VOLT_OPEN,
+				       TYPEC_CC_VOLT_RP_3_0),
+		      POLARITY_CC2);
+}
+
+ZTEST_USER(usb_common, test_get_snk_polarity_dts)
+{
+	zassert_equal(get_snk_polarity(TYPEC_CC_VOLT_RP_3_0,
+				       TYPEC_CC_VOLT_RP_DEF),
+		      POLARITY_CC1_DTS);
+	zassert_equal(get_snk_polarity(TYPEC_CC_VOLT_RP_DEF,
+				       TYPEC_CC_VOLT_RP_3_0),
+		      POLARITY_CC2_DTS);
+}
+
+ZTEST_USER(usb_common, test_get_src_polarity)
+{
+	zassert_equal(get_src_polarity(TYPEC_CC_VOLT_RD, TYPEC_CC_VOLT_OPEN),
+		      POLARITY_CC1);
+	zassert_equal(get_src_polarity(TYPEC_CC_VOLT_OPEN, TYPEC_CC_VOLT_RD),
+		      POLARITY_CC2);
+}
+
+ZTEST_USER(usb_common, test_pd_get_cc_state)
+{
+	zassert_equal(pd_get_cc_state(TYPEC_CC_VOLT_RD, TYPEC_CC_VOLT_RD),
+		      PD_CC_UFP_DEBUG_ACC);
+	zassert_equal(pd_get_cc_state(TYPEC_CC_VOLT_RD, TYPEC_CC_VOLT_OPEN),
+		      PD_CC_UFP_ATTACHED);
+	zassert_equal(pd_get_cc_state(TYPEC_CC_VOLT_RA, TYPEC_CC_VOLT_RA),
+		      PD_CC_UFP_AUDIO_ACC);
+
+	zassert_equal(pd_get_cc_state(TYPEC_CC_VOLT_RP_3_0,
+				      TYPEC_CC_VOLT_RP_DEF),
+		      PD_CC_DFP_DEBUG_ACC);
+	zassert_equal(pd_get_cc_state(TYPEC_CC_VOLT_RP_3_0, TYPEC_CC_VOLT_OPEN),
+		      PD_CC_DFP_ATTACHED);
+
+	zassert_equal(pd_get_cc_state(TYPEC_CC_VOLT_OPEN, TYPEC_CC_VOLT_OPEN),
+		      PD_CC_NONE);
+}
+
+ZTEST_USER(usb_common, test_pd_board_check_request_default)
+{
+	/* The default implementation accepts any RDO. Just use a basic one. */
+	zassert_ok(pd_board_check_request(RDO_FIXED(0, 3000, 3000, 0), 1));
+}
+
+ZTEST_USER(usb_common, test_pd_check_requested_voltage)
+{
+	uint32_t rdo;
+
+	rdo = RDO_FIXED(1, 1000, 1500, 0);
+	zassert_ok(pd_check_requested_voltage(rdo, 0));
+
+	/* An index of 0 is invalid. */
+	rdo = RDO_FIXED(0, 1000, 1500, 0);
+	zassert_equal(pd_check_requested_voltage(rdo, 0), EC_ERROR_INVAL);
+	/* So is an index larger than the number of source PDOs, which is 1 by
+	 * default.
+	 */
+	rdo = RDO_FIXED(5, 1000, 1500, 0);
+	zassert_equal(pd_check_requested_voltage(rdo, 0), EC_ERROR_INVAL);
+
+	/* So is operating current too high. (This RDO doesn't make sense.) */
+	rdo = RDO_FIXED(1, 1800, 1500, 0);
+	zassert_equal(pd_check_requested_voltage(rdo, 0), EC_ERROR_INVAL);
+	/* So is maximum current too high. */
+	rdo = RDO_FIXED(1, 1000, 1800, 0);
+	zassert_equal(pd_check_requested_voltage(rdo, 0), EC_ERROR_INVAL);
+}
+
+ZTEST_USER(usb_common, test_board_is_usb_pd_port_present)
+{
+	zassert_true(board_is_usb_pd_port_present(TEST_PORT));
+	zassert_false(board_is_usb_pd_port_present(-1));
+	zassert_false(board_is_usb_pd_port_present(100));
+}
+
+ZTEST_USER(usb_common, test_board_is_dts_port)
+{
+	zassert_true(board_is_dts_port(TEST_PORT));
+}
+
+ZTEST_USER(usb_common, test_drp_auto_toggle_next_state_detached)
+{
+	uint64_t drp_sink_time = 0;
+
+	/* If the port is detached and toggle is disabled, the next state should
+	 * be the configured default state.
+	 */
+	zassert_equal(drp_auto_toggle_next_state(
+			      &drp_sink_time, PD_ROLE_SINK, PD_DRP_TOGGLE_OFF,
+			      TYPEC_CC_VOLT_OPEN, TYPEC_CC_VOLT_OPEN, true),
+		      DRP_TC_DEFAULT);
+
+	/* If toggle is frozen, the next state should be the current state. */
+	zassert_equal(drp_auto_toggle_next_state(
+			      &drp_sink_time, PD_ROLE_SINK, PD_DRP_FREEZE,
+			      TYPEC_CC_VOLT_OPEN, TYPEC_CC_VOLT_OPEN, true),
+		      DRP_TC_UNATTACHED_SNK);
+	zassert_equal(drp_auto_toggle_next_state(
+			      &drp_sink_time, PD_ROLE_SOURCE, PD_DRP_FREEZE,
+			      TYPEC_CC_VOLT_OPEN, TYPEC_CC_VOLT_OPEN, true),
+		      DRP_TC_UNATTACHED_SRC);
+
+	/* If role is forced, the next state should be the forced state. */
+	zassert_equal(drp_auto_toggle_next_state(
+			      &drp_sink_time, PD_ROLE_SINK, PD_DRP_FORCE_SINK,
+			      TYPEC_CC_VOLT_OPEN, TYPEC_CC_VOLT_OPEN, true),
+		      DRP_TC_UNATTACHED_SNK);
+	zassert_equal(drp_auto_toggle_next_state(&drp_sink_time, PD_ROLE_SOURCE,
+						 PD_DRP_FORCE_SOURCE,
+						 TYPEC_CC_VOLT_OPEN,
+						 TYPEC_CC_VOLT_OPEN, true),
+		      DRP_TC_UNATTACHED_SRC);
+
+	/* If toggle is enabled but auto-toggle is not supported, the next state
+	 * should be based on the power role. If auto-toggle is supported, the
+	 * next state should be auto-toggle.
+	 */
+	zassert_equal(drp_auto_toggle_next_state(
+			      &drp_sink_time, PD_ROLE_SINK, PD_DRP_TOGGLE_ON,
+			      TYPEC_CC_VOLT_OPEN, TYPEC_CC_VOLT_OPEN, false),
+		      DRP_TC_UNATTACHED_SNK);
+	zassert_equal(drp_auto_toggle_next_state(
+			      &drp_sink_time, PD_ROLE_SOURCE, PD_DRP_TOGGLE_ON,
+			      TYPEC_CC_VOLT_OPEN, TYPEC_CC_VOLT_OPEN, false),
+		      DRP_TC_UNATTACHED_SRC);
+	zassert_equal(drp_auto_toggle_next_state(
+			      &drp_sink_time, PD_ROLE_SOURCE, PD_DRP_TOGGLE_ON,
+			      TYPEC_CC_VOLT_OPEN, TYPEC_CC_VOLT_OPEN, true),
+		      DRP_TC_DRP_AUTO_TOGGLE);
+}
+
+ZTEST_USER(usb_common, test_drp_auto_toggle_next_state_attached_to_source)
+{
+	uint64_t drp_sink_time = 0;
+
+	/* If the CC lines show a source attached, then the next state should be
+	 * a sink state. If auto-toggle is enabled, then the next state should
+	 * assume that the TCPC is already in AttachWait.SNK.
+	 */
+	zassert_equal(drp_auto_toggle_next_state(
+			      &drp_sink_time, PD_ROLE_SINK, PD_DRP_TOGGLE_ON,
+			      TYPEC_CC_VOLT_RP_3_0, TYPEC_CC_VOLT_OPEN, false),
+		      DRP_TC_UNATTACHED_SNK);
+	zassert_equal(drp_auto_toggle_next_state(
+			      &drp_sink_time, PD_ROLE_SINK, PD_DRP_TOGGLE_ON,
+			      TYPEC_CC_VOLT_OPEN, TYPEC_CC_VOLT_RP_3_0, false),
+		      DRP_TC_UNATTACHED_SNK);
+	zassert_equal(drp_auto_toggle_next_state(
+			      &drp_sink_time, PD_ROLE_SINK, PD_DRP_TOGGLE_ON,
+			      TYPEC_CC_VOLT_RP_3_0, TYPEC_CC_VOLT_OPEN, true),
+		      DRP_TC_ATTACHED_WAIT_SNK);
+
+	/* If the DRP state is force-source, keep toggling. */
+	zassert_equal(drp_auto_toggle_next_state(
+			      &drp_sink_time, PD_ROLE_SINK, PD_DRP_FORCE_SOURCE,
+			      TYPEC_CC_VOLT_RP_3_0, TYPEC_CC_VOLT_OPEN, false),
+		      DRP_TC_UNATTACHED_SNK);
+	zassert_equal(drp_auto_toggle_next_state(&drp_sink_time, PD_ROLE_SOURCE,
+						 PD_DRP_FORCE_SOURCE,
+						 TYPEC_CC_VOLT_RP_3_0,
+						 TYPEC_CC_VOLT_OPEN, false),
+		      DRP_TC_UNATTACHED_SRC);
+	zassert_equal(drp_auto_toggle_next_state(&drp_sink_time, PD_ROLE_SOURCE,
+						 PD_DRP_FORCE_SOURCE,
+						 TYPEC_CC_VOLT_RP_3_0,
+						 TYPEC_CC_VOLT_OPEN, true),
+		      DRP_TC_DRP_AUTO_TOGGLE);
+}
+
+ZTEST_USER(usb_common, test_drp_auto_toggle_next_state_attached_to_sink)
+{
+	uint64_t drp_sink_time = 0;
+	timestamp_t fake_time;
+
+	/* If the CC lines show a sink, then the next state should be a source
+	 * state. If auto-toggle is enabled, then the next state should assume
+	 * that the TCPC is already in AttachWait.SRC.
+	 */
+	zassert_equal(drp_auto_toggle_next_state(
+			      &drp_sink_time, PD_ROLE_SOURCE, PD_DRP_TOGGLE_ON,
+			      TYPEC_CC_VOLT_RD, TYPEC_CC_VOLT_OPEN, false),
+		      DRP_TC_UNATTACHED_SRC);
+	zassert_equal(drp_auto_toggle_next_state(
+			      &drp_sink_time, PD_ROLE_SOURCE, PD_DRP_TOGGLE_ON,
+			      TYPEC_CC_VOLT_RA, TYPEC_CC_VOLT_OPEN, false),
+		      DRP_TC_UNATTACHED_SRC);
+	zassert_equal(drp_auto_toggle_next_state(
+			      &drp_sink_time, PD_ROLE_SINK, PD_DRP_TOGGLE_ON,
+			      TYPEC_CC_VOLT_RD, TYPEC_CC_VOLT_OPEN, true),
+		      DRP_TC_ATTACHED_WAIT_SRC);
+
+	/* If the DRP state is off or force-sink, the TCPC might be in
+	 * auto-toggle anyway. If the CC lines have been in this state for less
+	 * than 100 ms, the TCPM should stay in Unattached.SNK and wait for the
+	 * partner to toggle.
+	 */
+	drp_sink_time = 0;
+	fake_time.val = drp_sink_time;
+	get_time_mock = &fake_time;
+	zassert_equal(drp_auto_toggle_next_state(
+			      &drp_sink_time, PD_ROLE_SINK, PD_DRP_TOGGLE_OFF,
+			      TYPEC_CC_VOLT_RD, TYPEC_CC_VOLT_OPEN, true),
+		      DRP_TC_UNATTACHED_SNK);
+	/* After 100 ms, the next state should be auto-toggle. */
+	drp_sink_time = 0;
+	fake_time.val = drp_sink_time + 105 * MSEC;
+	get_time_mock = &fake_time;
+	zassert_equal(drp_auto_toggle_next_state(
+			      &drp_sink_time, PD_ROLE_SINK, PD_DRP_TOGGLE_OFF,
+			      TYPEC_CC_VOLT_RD, TYPEC_CC_VOLT_OPEN, true),
+		      DRP_TC_DRP_AUTO_TOGGLE);
+	/* After 200 ms, the next state should be Unattached.SNK, and
+	 * drp_sink_time should be updated.
+	 */
+	drp_sink_time = 0;
+	fake_time.val = drp_sink_time + 205 * MSEC;
+	get_time_mock = &fake_time;
+	zassert_equal(drp_auto_toggle_next_state(
+			      &drp_sink_time, PD_ROLE_SINK, PD_DRP_TOGGLE_OFF,
+			      TYPEC_CC_VOLT_RD, TYPEC_CC_VOLT_OPEN, true),
+		      DRP_TC_UNATTACHED_SNK);
+	zassert_equal(drp_sink_time, fake_time.val);
+
+	get_time_mock = NULL;
+}
diff --git a/zephyr/test/drivers/usb_common/src/usb_pd_discharge.c b/zephyr/test/drivers/usb_common/src/usb_pd_discharge.c
new file mode 100644
index 0000000000..847840e3e5
--- /dev/null
+++ b/zephyr/test/drivers/usb_common/src/usb_pd_discharge.c
@@ -0,0 +1,29 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "suite.h"
+#include "usb_pd.h"
+#include "usb_pd_flags.h"
+
+#include <zephyr/fff.h>
+#include <zephyr/ztest_assert.h>
+#include <zephyr/ztest_test_new.h>
+
+#define TEST_PORT 0
+
+ZTEST_USER(usb_common, test_pd_set_vbus_discharge)
+{
+	board_vbus_source_enabled_fake.return_val = 0;
+
+	pd_set_vbus_discharge(TEST_PORT, true);
+	zassert_equal(ppc_discharge_vbus_fake.arg0_history[0], TEST_PORT);
+	zassert_equal(ppc_discharge_vbus_fake.arg1_history[0], 1);
+}
+
+ZTEST_USER(usb_common, test_pd_set_vbus_discharge_wrong_args)
+{
+	pd_set_vbus_discharge(100, true);
+	zassert_equal(ppc_discharge_vbus_fake.call_count, 0);
+}
diff --git a/zephyr/test/drivers/usb_common/src/usb_pd_flags.c b/zephyr/test/drivers/usb_common/src/usb_pd_flags.c
new file mode 100644
index 0000000000..05765da7b8
--- /dev/null
+++ b/zephyr/test/drivers/usb_common/src/usb_pd_flags.c
@@ -0,0 +1,37 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "usb_pd.h"
+#include "usb_pd_flags.h"
+
+#include <zephyr/ztest_assert.h>
+#include <zephyr/ztest_test_new.h>
+
+ZTEST_USER(usb_common, test_usb_pd_charger_otg)
+{
+	set_usb_pd_charger_otg(USB_PD_CHARGER_OTG_ENABLED);
+	zassert_equal(get_usb_pd_charger_otg(), USB_PD_CHARGER_OTG_ENABLED);
+
+	set_usb_pd_charger_otg(USB_PD_CHARGER_OTG_DISABLED);
+	zassert_equal(get_usb_pd_charger_otg(), USB_PD_CHARGER_OTG_DISABLED);
+}
+
+ZTEST_USER(usb_common, test_usb_pd_vbus_detect)
+{
+	set_usb_pd_vbus_detect(USB_PD_VBUS_DETECT_TCPC);
+	zassert_equal(get_usb_pd_vbus_detect(), USB_PD_VBUS_DETECT_TCPC);
+
+	set_usb_pd_vbus_detect(USB_PD_VBUS_DETECT_CHARGER);
+	zassert_equal(get_usb_pd_vbus_detect(), USB_PD_VBUS_DETECT_CHARGER);
+}
+
+ZTEST_USER(usb_common, test_usb_pd_discharge)
+{
+	set_usb_pd_discharge(USB_PD_DISCHARGE_PPC);
+	zassert_equal(get_usb_pd_discharge(), USB_PD_DISCHARGE_PPC);
+
+	set_usb_pd_discharge(USB_PD_DISCHARGE_GPIO);
+	zassert_equal(get_usb_pd_discharge(), USB_PD_DISCHARGE_GPIO);
+}
diff --git a/zephyr/test/drivers/usb_malfunction_sink/CMakeLists.txt b/zephyr/test/drivers/usb_malfunction_sink/CMakeLists.txt
new file mode 100644
index 0000000000..2e247726f0
--- /dev/null
+++ b/zephyr/test/drivers/usb_malfunction_sink/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Add source files
+target_sources(app PRIVATE src/usb_malfunction_sink.c)
diff --git a/zephyr/test/drivers/usb_malfunction_sink/src/usb_malfunction_sink.c b/zephyr/test/drivers/usb_malfunction_sink/src/usb_malfunction_sink.c
new file mode 100644
index 0000000000..dd50f2b35b
--- /dev/null
+++ b/zephyr/test/drivers/usb_malfunction_sink/src/usb_malfunction_sink.c
@@ -0,0 +1,327 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery_smart.h"
+#include "emul/emul_isl923x.h"
+#include "emul/emul_smart_battery.h"
+#include "emul/tcpc/emul_tcpci_partner_faulty_ext.h"
+#include "emul/tcpc/emul_tcpci_partner_snk.h"
+#include "tcpm/tcpci.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "timer.h"
+#include "usb_pd.h"
+#include "usb_tc_sm.h"
+
+#include <stdint.h>
+
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/ztest.h>
+
+/* USB-C port used to connect port partner in this testsuite */
+#define TEST_PORT 0
+BUILD_ASSERT(TEST_PORT == USBC_PORT_C0);
+
+struct usb_malfunction_sink_fixture {
+	struct tcpci_partner_data sink;
+	struct tcpci_faulty_ext_data faulty_snk_ext;
+	struct tcpci_snk_emul_data snk_ext;
+	const struct emul *tcpci_emul;
+	const struct emul *charger_emul;
+	struct tcpci_faulty_ext_action actions[2];
+	enum usbc_port port;
+};
+
+static void *usb_malfunction_sink_setup(void)
+{
+	static struct usb_malfunction_sink_fixture test_fixture;
+
+	test_fixture.port = TEST_PORT;
+
+	/* Get references for the emulators */
+	test_fixture.tcpci_emul = EMUL_GET_USBC_BINDING(TEST_PORT, tcpc);
+	test_fixture.charger_emul = EMUL_GET_USBC_BINDING(TEST_PORT, chg);
+
+	/* Initialized the sink to request 5V and 3A */
+	tcpci_partner_init(&test_fixture.sink, PD_REV20);
+	test_fixture.sink.extensions = tcpci_faulty_ext_init(
+		&test_fixture.faulty_snk_ext, &test_fixture.sink,
+		tcpci_snk_emul_init(&test_fixture.snk_ext, &test_fixture.sink,
+				    NULL));
+	test_fixture.snk_ext.pdo[1] =
+		PDO_FIXED(5000, 3000, PDO_FIXED_UNCONSTRAINED);
+
+	return &test_fixture;
+}
+
+static void usb_malfunction_sink_before(void *data)
+{
+	/* Set chipset to ON, this will set TCPM to DRP */
+	test_set_chipset_to_s0();
+
+	/* TODO(b/214401892): Check why need to give time TCPM to spin */
+	k_sleep(K_SECONDS(1));
+}
+
+static void usb_malfunction_sink_after(void *data)
+{
+	struct usb_malfunction_sink_fixture *fixture = data;
+
+	tcpci_faulty_ext_clear_actions_list(&fixture->faulty_snk_ext);
+	disconnect_sink_from_port(fixture->tcpci_emul);
+	tcpci_partner_common_clear_logged_msgs(&fixture->sink);
+}
+
+ZTEST_SUITE(usb_malfunction_sink, drivers_predicate_post_main,
+	    usb_malfunction_sink_setup, usb_malfunction_sink_before,
+	    usb_malfunction_sink_after, NULL);
+
+ZTEST_F(usb_malfunction_sink, test_fail_source_cap_and_pd_disable)
+{
+	struct ec_response_typec_status typec_status;
+
+	/*
+	 * Fail on SourceCapabilities message to make TCPM change PD port state
+	 * to disabled
+	 */
+	fixture->actions[0].action_mask = TCPCI_FAULTY_EXT_FAIL_SRC_CAP;
+	fixture->actions[0].count = TCPCI_FAULTY_EXT_INFINITE_ACTION;
+	tcpci_faulty_ext_append_action(&fixture->faulty_snk_ext,
+				       &fixture->actions[0]);
+
+	connect_sink_to_port(&fixture->sink, fixture->tcpci_emul,
+			     fixture->charger_emul);
+
+	typec_status = host_cmd_typec_status(0);
+
+	/* Device is connected, but PD wasn't able to establish contract */
+	zassert_true(typec_status.pd_enabled);
+	zassert_true(typec_status.dev_connected);
+	zassert_false(typec_status.sop_connected);
+}
+
+ZTEST_F(usb_malfunction_sink, test_fail_source_cap_and_pd_connect)
+{
+	struct ec_response_usb_pd_power_info info;
+	struct ec_response_typec_status typec_status;
+
+	/*
+	 * Fail only few times on SourceCapabilities message to prevent entering
+	 * PE_SRC_Disabled state by TCPM
+	 */
+	fixture->actions[0].action_mask = TCPCI_FAULTY_EXT_FAIL_SRC_CAP;
+	fixture->actions[0].count = 3;
+	tcpci_faulty_ext_append_action(&fixture->faulty_snk_ext,
+				       &fixture->actions[0]);
+
+	connect_sink_to_port(&fixture->sink, fixture->tcpci_emul,
+			     fixture->charger_emul);
+
+	typec_status = host_cmd_typec_status(0);
+
+	zassert_true(typec_status.pd_enabled);
+	zassert_true(typec_status.dev_connected);
+	zassert_true(typec_status.sop_connected);
+
+	info = host_cmd_power_info(0);
+
+	zassert_equal(info.role, USB_PD_PORT_POWER_SOURCE,
+		      "Expected role to be %d, but got %d",
+		      USB_PD_PORT_POWER_SOURCE, info.role);
+	zassert_equal(info.type, USB_CHG_TYPE_NONE,
+		      "Expected type to be %d, but got %d", USB_CHG_TYPE_NONE,
+		      info.type);
+	zassert_equal(info.meas.voltage_max, 0,
+		      "Expected charge voltage max of 0mV, but got %dmV",
+		      info.meas.voltage_max);
+	zassert_within(
+		info.meas.voltage_now, 5000, 500,
+		"Charging voltage expected to be near 5000mV, but was %dmV",
+		info.meas.voltage_now);
+	zassert_equal(info.meas.current_max, 1500,
+		      "Current max expected to be 1500mV, but was %dmV",
+		      info.meas.current_max);
+	zassert_equal(info.meas.current_lim, 0,
+		      "VBUS max is set to 0mA, but PD is reporting %dmA",
+		      info.meas.current_lim);
+	zassert_equal(info.max_power, 0,
+		      "Charging expected to be at %duW, but PD max is %duW", 0,
+		      info.max_power);
+}
+
+ZTEST_F(usb_malfunction_sink, test_ignore_source_cap)
+{
+	struct tcpci_partner_log_msg *msg;
+	uint16_t header;
+	bool expect_hard_reset = false;
+	int msg_cnt = 0;
+
+	fixture->actions[0].action_mask = TCPCI_FAULTY_EXT_IGNORE_SRC_CAP;
+	fixture->actions[0].count = TCPCI_FAULTY_EXT_INFINITE_ACTION;
+	tcpci_faulty_ext_append_action(&fixture->faulty_snk_ext,
+				       &fixture->actions[0]);
+
+	tcpci_partner_common_enable_pd_logging(&fixture->sink, true);
+	connect_sink_to_port(&fixture->sink, fixture->tcpci_emul,
+			     fixture->charger_emul);
+	tcpci_partner_common_enable_pd_logging(&fixture->sink, false);
+
+	/*
+	 * If test is failing, printing logged message may be useful to diagnose
+	 * problem:
+	 * tcpci_partner_common_print_logged_msgs(&fixture->sink);
+	 */
+
+	/* Check if SourceCapability message alternate with HardReset */
+	SYS_SLIST_FOR_EACH_CONTAINER(&fixture->sink.msg_log, msg, node)
+	{
+		if (expect_hard_reset) {
+			zassert_equal(msg->sop, TCPCI_MSG_TX_HARD_RESET,
+				      "Expected message %d to be hard reset",
+				      msg_cnt);
+		} else {
+			header = sys_get_le16(msg->buf);
+			zassert_equal(
+				msg->sop, TCPCI_MSG_SOP,
+				"Expected message %d to be SOP message, not 0x%x",
+				msg_cnt, msg->sop);
+			zassert_not_equal(
+				PD_HEADER_CNT(header), 0,
+				"Expected message %d to has at least one data object",
+				msg_cnt);
+			zassert_equal(
+				PD_HEADER_TYPE(header), PD_DATA_SOURCE_CAP,
+				"Expected message %d to be SourceCapabilities, not 0x%x",
+				msg_cnt, PD_HEADER_TYPE(header));
+		}
+
+		msg_cnt++;
+		expect_hard_reset = !expect_hard_reset;
+	}
+}
+
+ZTEST_F(usb_malfunction_sink, test_hard_reset_disconnect)
+{
+	struct ec_response_typec_status typec_status;
+	int try_count;
+
+	/*
+	 * Test if disconnection during the power sequence doesn't have impact
+	 * on next tries
+	 */
+	for (try_count = 1; try_count < 5; try_count++) {
+		/* Connect port partner and check Vconn state */
+		connect_sink_to_port(&fixture->sink, fixture->tcpci_emul,
+				     fixture->charger_emul);
+		typec_status = host_cmd_typec_status(fixture->port);
+		zassert_equal(typec_status.vconn_role, PD_ROLE_VCONN_SRC,
+			      "Vconn should be present after connection (%d)",
+			      try_count);
+
+		/* Send hard reset to trigger power sequence on source side */
+		tcpci_partner_common_send_hard_reset(&fixture->sink);
+
+		/*
+		 * Wait for start of power sequence after hard reset and half
+		 * the time of source recovery (first step of power sequence
+		 * when vconn should be disabled)
+		 */
+		k_sleep(K_USEC(PD_T_PS_HARD_RESET + PD_T_SRC_RECOVER / 2));
+
+		typec_status = host_cmd_typec_status(fixture->port);
+		zassert_equal(typec_status.vconn_role, PD_ROLE_VCONN_OFF,
+			      "Vconn should be disabled at power sequence (%d)",
+			      try_count);
+		zassert_true(typec_status.events & PD_STATUS_EVENT_HARD_RESET,
+			     "Hard reset status should be set (%d)", try_count);
+
+		/* Disconnect partner at the middle of power sequence */
+		disconnect_sink_from_port(fixture->tcpci_emul);
+	}
+}
+
+ZTEST_F(usb_malfunction_sink, test_ignore_source_cap_and_pd_disable)
+{
+	struct ec_response_typec_status typec_status;
+
+	/*
+	 * Ignore first SourceCapabilities message and failed others.
+	 * This will lead to PD disable.
+	 */
+	fixture->actions[0].action_mask = TCPCI_FAULTY_EXT_IGNORE_SRC_CAP;
+	fixture->actions[0].count = 1;
+	tcpci_faulty_ext_append_action(&fixture->faulty_snk_ext,
+				       &fixture->actions[0]);
+	fixture->actions[1].action_mask = TCPCI_FAULTY_EXT_FAIL_SRC_CAP;
+	fixture->actions[1].count = TCPCI_FAULTY_EXT_INFINITE_ACTION;
+	tcpci_faulty_ext_append_action(&fixture->faulty_snk_ext,
+				       &fixture->actions[1]);
+
+	connect_sink_to_port(&fixture->sink, fixture->tcpci_emul,
+			     fixture->charger_emul);
+
+	typec_status = host_cmd_typec_status(0);
+
+	/* Device is connected, but PD wasn't able to establish contract */
+	zassert_true(typec_status.pd_enabled);
+	zassert_true(typec_status.dev_connected);
+	zassert_false(typec_status.sop_connected);
+}
+
+ZTEST_F(usb_malfunction_sink, test_discard_source_cap)
+{
+	struct tcpci_partner_log_msg *msg;
+	uint16_t header;
+	int msg_cnt = 0;
+
+	/*
+	 * Discard SourceCapabilities messages, this will lead to SoftReset.
+	 */
+	fixture->actions[0].action_mask = TCPCI_FAULTY_EXT_DISCARD_SRC_CAP;
+	fixture->actions[0].count = TCPCI_FAULTY_EXT_INFINITE_ACTION;
+	tcpci_faulty_ext_append_action(&fixture->faulty_snk_ext,
+				       &fixture->actions[0]);
+
+	tcpci_partner_common_enable_pd_logging(&fixture->sink, true);
+	connect_sink_to_port(&fixture->sink, fixture->tcpci_emul,
+			     fixture->charger_emul);
+	tcpci_partner_common_enable_pd_logging(&fixture->sink, false);
+
+	/*
+	 * Check if SourceCapability message alternate with Accept and
+	 * SoftReset.
+	 * The sequence will be
+	 * TCPM: SourceCapability -> TCPC: Accept -> TCPM: SoftReset ->
+	 * TCPC: Accept
+	 */
+	SYS_SLIST_FOR_EACH_CONTAINER(&fixture->sink.msg_log, msg, node)
+	{
+		header = sys_get_le16(msg->buf);
+
+		switch (msg_cnt % 4) {
+		case 0:
+			zassert_equal(
+				PD_HEADER_TYPE(header), PD_DATA_SOURCE_CAP,
+				"Expected message %d to be SourceCapabilities, not 0x%x",
+				msg_cnt, PD_HEADER_TYPE(header));
+			break;
+		case 1:
+		case 3:
+			zassert_equal(
+				PD_HEADER_TYPE(header), PD_CTRL_ACCEPT,
+				"Expected message %d to be Accept, not 0x%x",
+				msg_cnt, PD_HEADER_TYPE(header));
+			break;
+		case 2:
+			zassert_equal(
+				PD_HEADER_TYPE(header), PD_CTRL_SOFT_RESET,
+				"Expected message %d to be SoftReset, not 0x%x",
+				msg_cnt, PD_HEADER_TYPE(header));
+			break;
+		}
+		msg_cnt++;
+	}
+}
diff --git a/zephyr/test/drivers/usb_pd_discovery/CMakeLists.txt b/zephyr/test/drivers/usb_pd_discovery/CMakeLists.txt
new file mode 100644
index 0000000000..6c02382202
--- /dev/null
+++ b/zephyr/test/drivers/usb_pd_discovery/CMakeLists.txt
@@ -0,0 +1,15 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Create library name based on current directory
+zephyr_library_get_current_dir_lib_name(${ZEPHYR_BASE} lib_name)
+
+# Create interface library
+zephyr_interface_library_named(${lib_name})
+
+# Add source files
+zephyr_library_sources("${CMAKE_CURRENT_SOURCE_DIR}/src/usb_pd_discovery.c")
+
+# Link in the library
+zephyr_library_link_libraries(${lib_name})
diff --git a/zephyr/test/drivers/usb_pd_discovery/src/usb_pd_discovery.c b/zephyr/test/drivers/usb_pd_discovery/src/usb_pd_discovery.c
new file mode 100644
index 0000000000..fb466d66ab
--- /dev/null
+++ b/zephyr/test/drivers/usb_pd_discovery/src/usb_pd_discovery.c
@@ -0,0 +1,397 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+#include "emul/emul_isl923x.h"
+#include "emul/tcpc/emul_ps8xxx.h"
+#include "emul/tcpc/emul_tcpci.h"
+#include "emul/tcpc/emul_tcpci_partner_snk.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "usb_dp_alt_mode.h"
+#include "usb_mux.h"
+#include "usb_pd_vdo.h"
+
+#include <stdint.h>
+
+#include <zephyr/kernel.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/ztest.h>
+
+#define TEST_PORT USBC_PORT_C0
+
+struct usb_pd_discovery_fixture {
+	const struct emul *tcpci_emul;
+	const struct emul *charger_emul;
+	struct tcpci_partner_data partner;
+	struct tcpci_snk_emul_data snk_ext;
+};
+
+static void *usb_pd_discovery_setup(void)
+{
+	static struct usb_pd_discovery_fixture fixture;
+	struct tcpci_partner_data *partner = &fixture.partner;
+	struct tcpci_snk_emul_data *snk_ext = &fixture.snk_ext;
+
+	tcpci_partner_init(partner, PD_REV30);
+	partner->extensions = tcpci_snk_emul_init(snk_ext, partner, NULL);
+
+	/* Get references for the emulators */
+	fixture.tcpci_emul = EMUL_DT_GET(DT_NODELABEL(tcpci_emul));
+	fixture.charger_emul = EMUL_DT_GET(DT_NODELABEL(isl923x_emul));
+
+	return &fixture;
+}
+
+static void usb_pd_discovery_before(void *data)
+{
+	/* Set chipset on so we'll connect to a sink partner */
+	test_set_chipset_to_s0();
+
+	/*
+	 * Test cases will attach the port partner themselves, since they need
+	 * to set up their own unique discovery replies
+	 */
+}
+
+static void usb_pd_discovery_after(void *data)
+{
+	struct usb_pd_discovery_fixture *fix = data;
+
+	disconnect_sink_from_port(fix->tcpci_emul);
+}
+
+ZTEST_SUITE(usb_pd_discovery, drivers_predicate_post_main,
+	    usb_pd_discovery_setup, usb_pd_discovery_before,
+	    usb_pd_discovery_after, NULL);
+
+/* First up: Plain and correct DP response */
+ZTEST_F(usb_pd_discovery, test_verify_discovery)
+{
+	struct tcpci_partner_data *partner = &fixture->partner;
+	uint8_t response_buffer[EC_LPC_HOST_PACKET_SIZE];
+	struct ec_response_typec_discovery *discovery =
+		(struct ec_response_typec_discovery *)response_buffer;
+
+	/* Add Discover Identity response */
+	partner->identity_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_PD, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_IDENT) |
+		VDO_SVDM_VERS(VDM_VER20);
+	partner->identity_vdm[VDO_INDEX_IDH] = VDO_IDH(
+		/* USB host */ false, /* USB device */ true, IDH_PTYPE_HUB,
+		/* modal operation */ true, USB_VID_GOOGLE);
+	partner->identity_vdm[VDO_INDEX_CSTAT] = 0;
+	partner->identity_vdm[VDO_INDEX_PRODUCT] = VDO_PRODUCT(0xBEAD, 0x1001);
+	/* Hardware version 1, firmware version 2 */
+	partner->identity_vdm[VDO_INDEX_PTYPE_UFP1_VDO] = VDO_UFP1(
+		(VDO_UFP1_CAPABILITY_USB20 | VDO_UFP1_CAPABILITY_USB32),
+		USB_TYPEC_RECEPTACLE, VDO_UFP1_ALT_MODE_RECONFIGURE,
+		USB_R30_SS_U32_U40_GEN2);
+	partner->identity_vdos = VDO_INDEX_PTYPE_UFP1_VDO + 1;
+
+	/* Add Discover Modes response with just DP */
+	partner->modes_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_DISPLAYPORT, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_MODES) |
+		VDO_SVDM_VERS(VDM_VER20);
+	partner->modes_vdm[VDO_INDEX_HDR + 1] =
+		VDO_MODE_DP(MODE_DP_PIN_E, 0, 1, CABLE_RECEPTACLE, MODE_DP_V13,
+			    MODE_DP_SNK);
+	partner->modes_vdos = VDO_INDEX_HDR + 2;
+
+	/* Add Discover SVIDs response for DP */
+	partner->svids_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_PD, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_SVID) |
+		VDO_SVDM_VERS(VDM_VER20);
+	partner->svids_vdm[VDO_INDEX_HDR + 1] =
+		VDO_SVID(USB_SID_DISPLAYPORT, 0);
+	partner->svids_vdos = VDO_INDEX_HDR + 2;
+
+	connect_sink_to_port(&fixture->partner, fixture->tcpci_emul,
+			     fixture->charger_emul);
+
+	host_cmd_typec_discovery(TEST_PORT, TYPEC_PARTNER_SOP, response_buffer,
+				 sizeof(response_buffer));
+
+	/* The host command does not count the VDM header in identity_count. */
+	zassert_equal(discovery->identity_count,
+		      fixture->partner.identity_vdos - 1);
+	zassert_mem_equal(
+		discovery->discovery_vdo, fixture->partner.identity_vdm + 1,
+		discovery->identity_count * sizeof(*discovery->discovery_vdo));
+	zassert_equal(discovery->svid_count, 1);
+	zassert_equal(discovery->svids[0].svid, USB_SID_DISPLAYPORT);
+	zassert_equal(discovery->svids[0].mode_count, 1);
+	zassert_equal(discovery->svids[0].mode_vdo[0],
+		      fixture->partner.modes_vdm[1]);
+}
+
+/* Now: Duplicate the DP SID */
+ZTEST_F(usb_pd_discovery, test_verify_svid_duplicate)
+{
+	struct tcpci_partner_data *partner = &fixture->partner;
+	uint8_t response_buffer[EC_LPC_HOST_PACKET_SIZE];
+	struct ec_response_typec_discovery *discovery =
+		(struct ec_response_typec_discovery *)response_buffer;
+
+	/* Add Discover Identity response */
+	partner->identity_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_PD, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_IDENT) |
+		VDO_SVDM_VERS(VDM_VER20);
+	partner->identity_vdm[VDO_INDEX_IDH] = VDO_IDH(
+		/* USB host */ false, /* USB device */ true, IDH_PTYPE_HUB,
+		/* modal operation */ true, USB_VID_GOOGLE);
+	partner->identity_vdm[VDO_INDEX_CSTAT] = 0;
+	partner->identity_vdm[VDO_INDEX_PRODUCT] = VDO_PRODUCT(0xBEAD, 0x1001);
+	/* Hardware version 1, firmware version 2 */
+	partner->identity_vdm[VDO_INDEX_PTYPE_UFP1_VDO] = VDO_UFP1(
+		(VDO_UFP1_CAPABILITY_USB20 | VDO_UFP1_CAPABILITY_USB32),
+		USB_TYPEC_RECEPTACLE, VDO_UFP1_ALT_MODE_RECONFIGURE,
+		USB_R30_SS_U32_U40_GEN2);
+	partner->identity_vdos = VDO_INDEX_PTYPE_UFP1_VDO + 1;
+
+	/* Add Discover SVIDs response for DP twice */
+	partner->svids_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_PD, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_SVID) |
+		VDO_SVDM_VERS(VDM_VER20);
+	partner->svids_vdm[VDO_INDEX_HDR + 1] =
+		VDO_SVID(USB_SID_DISPLAYPORT, USB_SID_DISPLAYPORT);
+	partner->svids_vdm[VDO_INDEX_HDR + 2] = 0;
+	partner->svids_vdos = VDO_INDEX_HDR + 3;
+
+	/* Add Discover Modes response with just DP */
+	partner->modes_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_DISPLAYPORT, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_MODES) |
+		VDO_SVDM_VERS(VDM_VER20);
+	partner->modes_vdm[VDO_INDEX_HDR + 1] =
+		VDO_MODE_DP(MODE_DP_PIN_E, 0, 1, CABLE_RECEPTACLE, MODE_DP_V13,
+			    MODE_DP_SNK);
+	partner->modes_vdos = VDO_INDEX_HDR + 2;
+
+	connect_sink_to_port(&fixture->partner, fixture->tcpci_emul,
+			     fixture->charger_emul);
+
+	host_cmd_typec_discovery(TEST_PORT, TYPEC_PARTNER_SOP, response_buffer,
+				 sizeof(response_buffer));
+
+	/* We should have but one SVID reported */
+	zassert_equal(discovery->svid_count, 1);
+	zassert_equal(discovery->svids[0].svid, USB_SID_DISPLAYPORT);
+}
+
+/* Forget to 0 terminate the SVIDs */
+ZTEST_F(usb_pd_discovery, test_verify_bad_termination)
+{
+	struct tcpci_partner_data *partner = &fixture->partner;
+	uint8_t response_buffer[EC_LPC_HOST_PACKET_SIZE];
+	struct ec_response_typec_discovery *discovery =
+		(struct ec_response_typec_discovery *)response_buffer;
+
+	/* Add Discover Identity response */
+	partner->identity_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_PD, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_IDENT) |
+		VDO_SVDM_VERS(VDM_VER20);
+	partner->identity_vdm[VDO_INDEX_IDH] = VDO_IDH(
+		/* USB host */ false, /* USB device */ true, IDH_PTYPE_HUB,
+		/* modal operation */ true, USB_VID_GOOGLE);
+	partner->identity_vdm[VDO_INDEX_CSTAT] = 0;
+	partner->identity_vdm[VDO_INDEX_PRODUCT] = VDO_PRODUCT(0xBEAD, 0x1001);
+	/* Hardware version 1, firmware version 2 */
+	partner->identity_vdm[VDO_INDEX_PTYPE_UFP1_VDO] = VDO_UFP1(
+		(VDO_UFP1_CAPABILITY_USB20 | VDO_UFP1_CAPABILITY_USB32),
+		USB_TYPEC_RECEPTACLE, VDO_UFP1_ALT_MODE_RECONFIGURE,
+		USB_R30_SS_U32_U40_GEN2);
+	partner->identity_vdos = VDO_INDEX_PTYPE_UFP1_VDO + 1;
+
+	/* Add Discover SVIDs response for DP and TBT with no NULL */
+	partner->svids_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_PD, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_SVID) |
+		VDO_SVDM_VERS(VDM_VER20);
+	partner->svids_vdm[VDO_INDEX_HDR + 1] =
+		VDO_SVID(USB_SID_DISPLAYPORT, USB_VID_INTEL);
+	partner->svids_vdos = VDO_INDEX_HDR + 2;
+
+	/* Add Discover Modes response with just DP */
+	partner->modes_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_DISPLAYPORT, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_MODES) |
+		VDO_SVDM_VERS(VDM_VER20);
+	partner->modes_vdm[VDO_INDEX_HDR + 1] =
+		VDO_MODE_DP(MODE_DP_PIN_E, 0, 1, CABLE_RECEPTACLE, MODE_DP_V13,
+			    MODE_DP_SNK);
+	partner->modes_vdos = VDO_INDEX_HDR + 2;
+
+	connect_sink_to_port(&fixture->partner, fixture->tcpci_emul,
+			     fixture->charger_emul);
+
+	host_cmd_typec_discovery(TEST_PORT, TYPEC_PARTNER_SOP, response_buffer,
+				 sizeof(response_buffer));
+
+	/* We should have both SVIDs and no nonsense */
+	zassert_equal(discovery->svid_count, 2);
+	zassert_equal(discovery->svids[0].svid, USB_SID_DISPLAYPORT);
+	zassert_equal(discovery->svids[1].svid, USB_VID_INTEL);
+}
+
+/* Reply with a NAK to DiscoverModes */
+ZTEST_F(usb_pd_discovery, test_verify_modes_nak)
+{
+	struct tcpci_partner_data *partner = &fixture->partner;
+	uint8_t response_buffer[EC_LPC_HOST_PACKET_SIZE];
+	struct ec_response_typec_discovery *discovery =
+		(struct ec_response_typec_discovery *)response_buffer;
+
+	/* Add Discover Identity response */
+	partner->identity_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_PD, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_IDENT) |
+		VDO_SVDM_VERS(VDM_VER20);
+	partner->identity_vdm[VDO_INDEX_IDH] = VDO_IDH(
+		/* USB host */ false, /* USB device */ true, IDH_PTYPE_HUB,
+		/* modal operation */ true, USB_VID_GOOGLE);
+	partner->identity_vdm[VDO_INDEX_CSTAT] = 0;
+	partner->identity_vdm[VDO_INDEX_PRODUCT] = VDO_PRODUCT(0xBEAD, 0x1001);
+	/* Hardware version 1, firmware version 2 */
+	partner->identity_vdm[VDO_INDEX_PTYPE_UFP1_VDO] = VDO_UFP1(
+		(VDO_UFP1_CAPABILITY_USB20 | VDO_UFP1_CAPABILITY_USB32),
+		USB_TYPEC_RECEPTACLE, VDO_UFP1_ALT_MODE_RECONFIGURE,
+		USB_R30_SS_U32_U40_GEN2);
+	partner->identity_vdos = VDO_INDEX_PTYPE_UFP1_VDO + 1;
+
+	/* Add Discover SVIDs response for TBT */
+	partner->svids_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_PD, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_SVID) |
+		VDO_SVDM_VERS(VDM_VER20);
+	partner->svids_vdm[VDO_INDEX_HDR + 1] = VDO_SVID(USB_VID_INTEL, 0);
+	partner->svids_vdos = VDO_INDEX_HDR + 2;
+
+	/* Add Discover Modes NAK */
+	partner->modes_vdm[VDO_INDEX_HDR] =
+		VDO(USB_VID_INTEL, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_NAK) | CMD_DISCOVER_MODES) |
+		VDO_SVDM_VERS(VDM_VER20);
+	partner->modes_vdos = 1;
+
+	connect_sink_to_port(&fixture->partner, fixture->tcpci_emul,
+			     fixture->charger_emul);
+
+	host_cmd_typec_discovery(TEST_PORT, TYPEC_PARTNER_SOP, response_buffer,
+				 sizeof(response_buffer));
+
+	/* No SVID reported up to the AP because it didn't report any data */
+	zassert_equal(discovery->svid_count, 0);
+}
+
+/* Reply with the wrong SVID to DiscoverModes */
+ZTEST_F(usb_pd_discovery, test_verify_bad_mode)
+{
+	struct tcpci_partner_data *partner = &fixture->partner;
+	uint8_t response_buffer[EC_LPC_HOST_PACKET_SIZE];
+	struct ec_response_typec_discovery *discovery =
+		(struct ec_response_typec_discovery *)response_buffer;
+
+	/* Add Discover Identity response */
+	partner->identity_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_PD, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_IDENT) |
+		VDO_SVDM_VERS(VDM_VER20);
+	partner->identity_vdm[VDO_INDEX_IDH] = VDO_IDH(
+		/* USB host */ false, /* USB device */ true, IDH_PTYPE_HUB,
+		/* modal operation */ true, USB_VID_GOOGLE);
+	partner->identity_vdm[VDO_INDEX_CSTAT] = 0;
+	partner->identity_vdm[VDO_INDEX_PRODUCT] = VDO_PRODUCT(0xBEAD, 0x1001);
+	/* Hardware version 1, firmware version 2 */
+	partner->identity_vdm[VDO_INDEX_PTYPE_UFP1_VDO] = VDO_UFP1(
+		(VDO_UFP1_CAPABILITY_USB20 | VDO_UFP1_CAPABILITY_USB32),
+		USB_TYPEC_RECEPTACLE, VDO_UFP1_ALT_MODE_RECONFIGURE,
+		USB_R30_SS_U32_U40_GEN2);
+	partner->identity_vdos = VDO_INDEX_PTYPE_UFP1_VDO + 1;
+
+	/* Add Discover SVIDs response for TBT */
+	partner->svids_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_PD, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_SVID) |
+		VDO_SVDM_VERS(VDM_VER20);
+	partner->svids_vdm[VDO_INDEX_HDR + 1] = VDO_SVID(USB_VID_INTEL, 0);
+	partner->svids_vdos = VDO_INDEX_HDR + 2;
+
+	/* Add Discover Modes for DP, which we didn't report in DiscoverSVIDs */
+	partner->modes_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_DISPLAYPORT, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_MODES) |
+		VDO_SVDM_VERS(VDM_VER20);
+	partner->modes_vdm[VDO_INDEX_HDR + 1] =
+		VDO_MODE_DP(MODE_DP_PIN_E, 0, 1, CABLE_RECEPTACLE, MODE_DP_V13,
+			    MODE_DP_SNK);
+	partner->modes_vdos = VDO_INDEX_HDR + 2;
+
+	connect_sink_to_port(&fixture->partner, fixture->tcpci_emul,
+			     fixture->charger_emul);
+
+	host_cmd_typec_discovery(TEST_PORT, TYPEC_PARTNER_SOP, response_buffer,
+				 sizeof(response_buffer));
+
+	/* No SVID reported up to the AP because it didn't report any data */
+	zassert_equal(discovery->svid_count, 0);
+}
+
+/* Reply without required mode VDO */
+ZTEST_F(usb_pd_discovery, test_verify_modes_missing)
+{
+	struct tcpci_partner_data *partner = &fixture->partner;
+	uint8_t response_buffer[EC_LPC_HOST_PACKET_SIZE];
+	struct ec_response_typec_discovery *discovery =
+		(struct ec_response_typec_discovery *)response_buffer;
+
+	/* Add Discover Identity response */
+	partner->identity_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_PD, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_IDENT) |
+		VDO_SVDM_VERS(VDM_VER20);
+	partner->identity_vdm[VDO_INDEX_IDH] = VDO_IDH(
+		/* USB host */ false, /* USB device */ true, IDH_PTYPE_HUB,
+		/* modal operation */ true, USB_VID_GOOGLE);
+	partner->identity_vdm[VDO_INDEX_CSTAT] = 0;
+	partner->identity_vdm[VDO_INDEX_PRODUCT] = VDO_PRODUCT(0xBEAD, 0x1001);
+	/* Hardware version 1, firmware version 2 */
+	partner->identity_vdm[VDO_INDEX_PTYPE_UFP1_VDO] = VDO_UFP1(
+		(VDO_UFP1_CAPABILITY_USB20 | VDO_UFP1_CAPABILITY_USB32),
+		USB_TYPEC_RECEPTACLE, VDO_UFP1_ALT_MODE_RECONFIGURE,
+		USB_R30_SS_U32_U40_GEN2);
+	partner->identity_vdos = VDO_INDEX_PTYPE_UFP1_VDO + 1;
+
+	/* Add Discover SVIDs response for TBT */
+	partner->svids_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_PD, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_SVID) |
+		VDO_SVDM_VERS(VDM_VER20);
+	partner->svids_vdm[VDO_INDEX_HDR + 1] = VDO_SVID(USB_VID_INTEL, 0);
+	partner->svids_vdos = VDO_INDEX_HDR + 2;
+
+	/* Add Discover Modes ACK with no data */
+	partner->modes_vdm[VDO_INDEX_HDR] =
+		VDO(USB_VID_INTEL, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_MODES) |
+		VDO_SVDM_VERS(VDM_VER20);
+	partner->modes_vdos = 1;
+
+	connect_sink_to_port(&fixture->partner, fixture->tcpci_emul,
+			     fixture->charger_emul);
+
+	host_cmd_typec_discovery(TEST_PORT, TYPEC_PARTNER_SOP, response_buffer,
+				 sizeof(response_buffer));
+
+	/* No SVID reported up to the AP because it didn't report any data */
+	zassert_equal(discovery->svid_count, 0);
+}
diff --git a/zephyr/test/drivers/usb_port_power_dumb/CMakeLists.txt b/zephyr/test/drivers/usb_port_power_dumb/CMakeLists.txt
new file mode 100644
index 0000000000..902a5b4a2d
--- /dev/null
+++ b/zephyr/test/drivers/usb_port_power_dumb/CMakeLists.txt
@@ -0,0 +1,7 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_sources(app PRIVATE
+  src/usb_port_power_dumb.c
+)
diff --git a/zephyr/test/drivers/usb_port_power_dumb/src/usb_port_power_dumb.c b/zephyr/test/drivers/usb_port_power_dumb/src/usb_port_power_dumb.c
new file mode 100644
index 0000000000..67bf48453e
--- /dev/null
+++ b/zephyr/test/drivers/usb_port_power_dumb/src/usb_port_power_dumb.c
@@ -0,0 +1,145 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "gpio.h"
+#include "host_command.h"
+#include "test/drivers/test_state.h"
+#include "usb_charge.h"
+
+#include <stdint.h>
+#include <string.h>
+
+#include <zephyr/kernel.h>
+#include <zephyr/shell/shell_dummy.h>
+#include <zephyr/ztest.h>
+#include <zephyr/ztest_assert.h>
+
+/* Expecting at least one port */
+BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) >= 1);
+BUILD_ASSERT(USB_PORT_COUNT >= 1);
+
+/* Index of the USB-A port under test */
+#define PORT_ID 0
+
+static int check_gpio_status_for_port(int port_id)
+{
+	/* Ensure we don't make any invalid inquiries. These should only trip in
+	 * the case of developer error.
+	 */
+	zassert_true(port_id < ARRAY_SIZE(usb_port_enable),
+		     "Out of bounds port_id");
+	zassert_true(usb_port_enable[port_id] >= 0,
+		     "No valid pin number for this port");
+
+	return gpio_get_level(usb_port_enable[port_id]);
+}
+
+ZTEST(usb_port_power_dumb, test_console_command__noargs)
+{
+	const char *outbuffer;
+	size_t buffer_size;
+
+	/* With no args, print current state */
+	shell_backend_dummy_clear_output(get_ec_shell());
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "usbchargemode"), NULL);
+	outbuffer =
+		shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+
+	zassert_ok(!strstr(outbuffer, "Port " STRINGIFY(PORT_ID) ": off"),
+		   "Actual: '%s'", outbuffer);
+
+	zassert_false(check_gpio_status_for_port(PORT_ID), NULL);
+}
+
+ZTEST(usb_port_power_dumb, test_console_command__modify_port_status)
+{
+	const char *outbuffer;
+	size_t buffer_size;
+
+	/* Change the port status to on */
+	shell_backend_dummy_clear_output(get_ec_shell());
+	zassert_ok(shell_execute_cmd(get_ec_shell(),
+				     "usbchargemode " STRINGIFY(PORT_ID) " on"),
+		   NULL);
+	outbuffer =
+		shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+
+	zassert_ok(!strstr(outbuffer, "Port " STRINGIFY(PORT_ID) ": on"),
+		   "Actual: '%s'", outbuffer);
+
+	zassert_true(check_gpio_status_for_port(PORT_ID), NULL);
+}
+
+ZTEST(usb_port_power_dumb, test_console_command__invalid)
+{
+	/* Various bad input */
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "usbchargemode NaN"),
+		   NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "usbchargemode -1"),
+		   NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "usbchargemode 10000"),
+		   NULL);
+	zassert_ok(
+		!shell_execute_cmd(get_ec_shell(),
+				   "usbchargemode " STRINGIFY(PORT_ID) " abc"),
+		NULL);
+}
+
+ZTEST(usb_port_power_dumb, test_host_command__enable)
+{
+	int ret;
+	struct ec_params_usb_charge_set_mode params = {
+		.mode = USB_CHARGE_MODE_ENABLED,
+		.usb_port_id = PORT_ID,
+	};
+
+	ret = ec_cmd_usb_charge_set_mode(NULL, &params);
+
+	zassert_ok(ret, "Host command returned %d", ret);
+	zassert_true(check_gpio_status_for_port(PORT_ID), NULL);
+}
+
+ZTEST(usb_port_power_dumb, test_host_command__invalid_port_id)
+{
+	int ret;
+	struct ec_params_usb_charge_set_mode params = {
+		.mode = USB_CHARGE_MODE_ENABLED,
+		/* This port ID does not exist */
+		.usb_port_id = UINT8_MAX,
+	};
+
+	ret = ec_cmd_usb_charge_set_mode(NULL, &params);
+
+	zassert_equal(EC_RES_ERROR, ret, "Host command returned %d", ret);
+	zassert_false(check_gpio_status_for_port(PORT_ID), NULL);
+}
+
+ZTEST(usb_port_power_dumb, test_host_command__invalid_mode)
+{
+	int ret;
+	struct ec_params_usb_charge_set_mode params = {
+		.mode = USB_CHARGE_MODE_COUNT, /* Invalid */
+		.usb_port_id = PORT_ID,
+	};
+
+	ret = ec_cmd_usb_charge_set_mode(NULL, &params);
+
+	zassert_equal(EC_RES_ERROR, ret, "Host command returned %d", ret);
+	zassert_false(check_gpio_status_for_port(PORT_ID), NULL);
+}
+
+static void reset(void *data)
+{
+	ARG_UNUSED(data);
+
+	/* Turn the port off */
+	zassert_ok(usb_charge_set_mode(PORT_ID, USB_CHARGE_MODE_DISABLED,
+				       USB_DISALLOW_SUSPEND_CHARGE),
+		   NULL);
+}
+
+ZTEST_SUITE(usb_port_power_dumb, drivers_predicate_post_main, NULL, reset,
+	    reset, NULL);
diff --git a/zephyr/test/drivers/usb_port_power_dumb/usba.dts b/zephyr/test/drivers/usb_port_power_dumb/usba.dts
new file mode 100644
index 0000000000..ff700d03fc
--- /dev/null
+++ b/zephyr/test/drivers/usb_port_power_dumb/usba.dts
@@ -0,0 +1,14 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	/* Add a USB-A port to the board. Uses a GPIO pin defined in
+	 * zephyr/test/drivers/boards/native_posix.overlay
+	 */
+	usba-port-enable-list {
+		compatible = "cros-ec,usba-port-enable-pins";
+		enable-pins = <&gpio_en_pp5000_usba_r>;
+	};
+};
diff --git a/zephyr/test/drivers/usb_retimer_fw_update/CMakeLists.txt b/zephyr/test/drivers/usb_retimer_fw_update/CMakeLists.txt
new file mode 100644
index 0000000000..786726414b
--- /dev/null
+++ b/zephyr/test/drivers/usb_retimer_fw_update/CMakeLists.txt
@@ -0,0 +1,19 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Create library name based on current directory
+zephyr_library_get_current_dir_lib_name(${ZEPHYR_BASE} lib_name)
+
+# Create interface library
+zephyr_interface_library_named(${lib_name})
+
+# Add include paths
+zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}")
+zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}/include")
+
+# Add source files
+zephyr_library_sources("${CMAKE_CURRENT_SOURCE_DIR}/src/usb_retimer_fw_update.c")
+
+# Link in the library
+zephyr_library_link_libraries(${lib_name})
diff --git a/zephyr/test/drivers/usb_retimer_fw_update/prj.conf b/zephyr/test/drivers/usb_retimer_fw_update/prj.conf
new file mode 100644
index 0000000000..de54617e71
--- /dev/null
+++ b/zephyr/test/drivers/usb_retimer_fw_update/prj.conf
@@ -0,0 +1,6 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_PLATFORM_EC_ACPI=y
+CONFIG_PLATFORM_EC_USB_MUX_TASK=y
diff --git a/zephyr/test/drivers/usb_retimer_fw_update/src/usb_retimer_fw_update.c b/zephyr/test/drivers/usb_retimer_fw_update/src/usb_retimer_fw_update.c
new file mode 100644
index 0000000000..e5f6c23ed6
--- /dev/null
+++ b/zephyr/test/drivers/usb_retimer_fw_update/src/usb_retimer_fw_update.c
@@ -0,0 +1,269 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "usb_common.h"
+#include "usb_pd.h"
+
+#include <zephyr/ztest.h>
+
+#define BB_RETIMER_NODE DT_NODELABEL(usb_c1_bb_retimer_emul)
+#define TEST_PORT USBC_PORT_C1
+
+/* Note: for API details, see common/usbc/usb_retimer_fw_update.c */
+
+/* Helpers */
+static uint8_t acpi_read_and_verify(void)
+{
+	uint8_t read_result = acpi_read(EC_ACPI_MEM_USB_RETIMER_FW_UPDATE);
+
+	zassert_not_equal(read_result, USB_RETIMER_FW_UPDATE_ERR,
+			  "Command returned unexpected err");
+	zassert_not_equal(read_result, USB_RETIMER_FW_UPDATE_INVALID_MUX,
+			  "Command returned invalid mux");
+
+	return read_result;
+}
+
+static void usb_retimer_fw_update_suspend_port(void)
+{
+	/* Write our command to suspend the port first */
+	acpi_write(EC_ACPI_MEM_USB_RETIMER_FW_UPDATE,
+		   USB_RETIMER_FW_UPDATE_SUSPEND_PD
+				   << USB_RETIMER_FW_UPDATE_OP_SHIFT |
+			   TEST_PORT);
+
+	/* Give PD task time to suspend port */
+	k_sleep(K_SECONDS(1));
+
+	zassert_true(acpi_read_and_verify() == 0,
+		     "Failed to see successful suspend");
+}
+
+/* Test configuration */
+static void usb_retimer_fw_update_before(void *data)
+{
+	ARG_UNUSED(data);
+
+	/* Assume our common setup of a BB retimer on C1 */
+	zassert_true(EMUL_DT_GET(BB_RETIMER_NODE) != NULL,
+		     "No BB retimer found on C1");
+
+	/* Set chipset to ON, since AP would drive this process */
+	test_set_chipset_to_s0();
+
+	/* TODO(b/214401892): Check why need to give time TCPM to spin */
+	k_sleep(K_SECONDS(1));
+}
+
+static void usb_retimer_fw_update_after(void *data)
+{
+	ARG_UNUSED(data);
+
+	/* Unsuspend the port */
+	acpi_write(EC_ACPI_MEM_USB_RETIMER_FW_UPDATE,
+		   USB_RETIMER_FW_UPDATE_DISCONNECT
+				   << USB_RETIMER_FW_UPDATE_OP_SHIFT |
+			   TEST_PORT);
+
+	/* Port should resume after at least 7 seconds */
+	k_sleep(K_SECONDS(8));
+}
+
+ZTEST_SUITE(usb_retimer_fw_update, drivers_predicate_post_main, NULL,
+	    usb_retimer_fw_update_before, usb_retimer_fw_update_after, NULL);
+
+ZTEST(usb_retimer_fw_update, test_verify_query_port)
+{
+	/* Write our command to query ports */
+	acpi_write(EC_ACPI_MEM_USB_RETIMER_FW_UPDATE,
+		   USB_RETIMER_FW_UPDATE_QUERY_PORT
+			   << USB_RETIMER_FW_UPDATE_OP_SHIFT);
+
+	zassert_true(acpi_read_and_verify() & BIT(TEST_PORT),
+		     "Failed to see port in query");
+}
+
+ZTEST(usb_retimer_fw_update, test_verify_suspend_port)
+{
+	/* Write our command to suspend the port */
+	acpi_write(EC_ACPI_MEM_USB_RETIMER_FW_UPDATE,
+		   USB_RETIMER_FW_UPDATE_SUSPEND_PD
+				   << USB_RETIMER_FW_UPDATE_OP_SHIFT |
+			   TEST_PORT);
+
+	/* Give PD task time to suspend port */
+	k_sleep(K_SECONDS(1));
+
+	/* Return of 0 indicates the command succeeded */
+	zassert_true(acpi_read_and_verify() == 0,
+		     "Failed to see successful suspend");
+}
+
+ZTEST(usb_retimer_fw_update, test_verify_resume_port)
+{
+	usb_retimer_fw_update_suspend_port();
+
+	/* And now resume it */
+	acpi_write(EC_ACPI_MEM_USB_RETIMER_FW_UPDATE,
+		   USB_RETIMER_FW_UPDATE_RESUME_PD
+				   << USB_RETIMER_FW_UPDATE_OP_SHIFT |
+			   TEST_PORT);
+
+	/* Give PD task time to resume port */
+	k_sleep(K_SECONDS(1));
+
+	/* Note: return indicates whether the port is enabled */
+	zassert_true(acpi_read_and_verify() == 1,
+		     "Failed to see successful resume");
+}
+
+ZTEST(usb_retimer_fw_update, test_verify_get_mux)
+{
+	struct ec_response_typec_status typec_status;
+
+	/* Write our command to get the mux state for a port */
+	acpi_write(EC_ACPI_MEM_USB_RETIMER_FW_UPDATE,
+		   USB_RETIMER_FW_UPDATE_GET_MUX
+				   << USB_RETIMER_FW_UPDATE_OP_SHIFT |
+			   TEST_PORT);
+
+	/* Give PD task time to process */
+	k_sleep(K_SECONDS(1));
+
+	typec_status = host_cmd_typec_status(TEST_PORT);
+	zassert_true(acpi_read_and_verify() == typec_status.mux_state,
+		     "Failed to match mux state");
+}
+
+/* Commands which first require suspend to be run */
+ZTEST(usb_retimer_fw_update, test_verify_set_mux_usb)
+{
+	struct ec_response_typec_status typec_status;
+
+	usb_retimer_fw_update_suspend_port();
+
+	/* And now set the mux to USB */
+	acpi_write(EC_ACPI_MEM_USB_RETIMER_FW_UPDATE,
+		   USB_RETIMER_FW_UPDATE_SET_USB
+				   << USB_RETIMER_FW_UPDATE_OP_SHIFT |
+			   TEST_PORT);
+
+	/* Give PD task time to set the mux */
+	k_sleep(K_SECONDS(1));
+
+	/* Note: return indicates filtered mux state */
+	zassert_true(acpi_read_and_verify() == USB_PD_MUX_USB_ENABLED,
+		     "Failed to set mux usb");
+
+	typec_status = host_cmd_typec_status(TEST_PORT);
+	zassert_equal(typec_status.mux_state & USB_RETIMER_FW_UPDATE_MUX_MASK,
+		      USB_PD_MUX_USB_ENABLED, "Status mux disagreement");
+}
+
+ZTEST(usb_retimer_fw_update, test_verify_set_mux_safe)
+{
+	struct ec_response_typec_status typec_status;
+
+	usb_retimer_fw_update_suspend_port();
+
+	/* And now set the mux to safe */
+	acpi_write(EC_ACPI_MEM_USB_RETIMER_FW_UPDATE,
+		   USB_RETIMER_FW_UPDATE_SET_SAFE
+				   << USB_RETIMER_FW_UPDATE_OP_SHIFT |
+			   TEST_PORT);
+
+	/* Give PD task time to set the mux */
+	k_sleep(K_SECONDS(1));
+
+	/* Note: return indicates filtered mux state */
+	zassert_true(acpi_read_and_verify() == USB_PD_MUX_SAFE_MODE,
+		     "Failed to set mux safe");
+
+	typec_status = host_cmd_typec_status(TEST_PORT);
+	zassert_equal(typec_status.mux_state & USB_RETIMER_FW_UPDATE_MUX_MASK,
+		      USB_PD_MUX_SAFE_MODE, "Status mux disagreement");
+}
+
+ZTEST(usb_retimer_fw_update, test_verify_set_mux_tbt)
+{
+	struct ec_response_typec_status typec_status;
+
+	usb_retimer_fw_update_suspend_port();
+
+	/* And now set the mux to TBT */
+	acpi_write(EC_ACPI_MEM_USB_RETIMER_FW_UPDATE,
+		   USB_RETIMER_FW_UPDATE_SET_TBT
+				   << USB_RETIMER_FW_UPDATE_OP_SHIFT |
+			   TEST_PORT);
+
+	/* Give PD task time to set the mux */
+	k_sleep(K_SECONDS(1));
+
+	/* Note: return indicates filtered mux state */
+	zassert_true(acpi_read_and_verify() == USB_PD_MUX_TBT_COMPAT_ENABLED,
+		     "Failed to set mux tbt");
+
+	typec_status = host_cmd_typec_status(TEST_PORT);
+	zassert_equal(typec_status.mux_state & USB_RETIMER_FW_UPDATE_MUX_MASK,
+		      USB_PD_MUX_TBT_COMPAT_ENABLED, "Status mux disagreement");
+}
+
+ZTEST(usb_retimer_fw_update, test_verify_update_disconnect)
+{
+	uint64_t command_start;
+
+	usb_retimer_fw_update_suspend_port();
+
+	/* And now set the process to disconnect */
+	acpi_write(EC_ACPI_MEM_USB_RETIMER_FW_UPDATE,
+		   USB_RETIMER_FW_UPDATE_DISCONNECT
+				   << USB_RETIMER_FW_UPDATE_OP_SHIFT |
+			   TEST_PORT);
+	command_start = k_uptime_get();
+
+	/* Give PD task time to set the mux */
+	k_sleep(K_SECONDS(1));
+
+	/* Note: return indicates filtered mux state */
+	zassert_true(acpi_read_and_verify() == USB_PD_MUX_NONE,
+		     "Failed to set mux disconnect");
+
+	/*
+	 * Note: this would ideally be a host command interface check, but
+	 * the only HC return which would cover this is a state string, which
+	 * could be brittle.
+	 */
+	/* Port shouldn't be up or at least 5 seconds */
+	for (int i = 0; i < 10; i++) {
+		if (pd_is_port_enabled(TEST_PORT)) {
+			zassert_true((k_uptime_get() - command_start) > 5000,
+				     "Port resumed too soon");
+			break;
+		}
+		k_sleep(K_SECONDS(1));
+	}
+
+	zassert_true(pd_is_port_enabled(TEST_PORT), "Port not resuemd");
+}
+
+/* Verify we get an error if port isn't suspended */
+ZTEST(usb_retimer_fw_update, test_verify_mux_usb_error)
+{
+	/* Set the mux to USB  on unsuspended port */
+	acpi_write(EC_ACPI_MEM_USB_RETIMER_FW_UPDATE,
+		   USB_RETIMER_FW_UPDATE_SET_USB
+				   << USB_RETIMER_FW_UPDATE_OP_SHIFT |
+			   TEST_PORT);
+
+	/* Give PD task time to set the mux */
+	k_sleep(K_SECONDS(1));
+
+	zassert_true(acpi_read(EC_ACPI_MEM_USB_RETIMER_FW_UPDATE) ==
+			     USB_RETIMER_FW_UPDATE_ERR,
+		     "Failed to fail mux set");
+}
diff --git a/zephyr/test/drivers/usbc_alt_mode/CMakeLists.txt b/zephyr/test/drivers/usbc_alt_mode/CMakeLists.txt
new file mode 100644
index 0000000000..a00bc17512
--- /dev/null
+++ b/zephyr/test/drivers/usbc_alt_mode/CMakeLists.txt
@@ -0,0 +1,10 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_include_directories(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/include)
+
+target_sources(app PRIVATE src/usbc_alt_mode.c)
+target_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_REQUIRE_AP_MODE_ENTRY app PRIVATE src/usbc_alt_mode__require_ap_mode_entry.c)
+target_sources_ifndef(CONFIG_PLATFORM_EC_USB_PD_REQUIRE_AP_MODE_ENTRY
+	app PRIVATE src/usbc_alt_mode_ec_mode_entry.c)
diff --git a/zephyr/test/drivers/usbc_alt_mode/include/test_usbc_alt_mode.h b/zephyr/test/drivers/usbc_alt_mode/include/test_usbc_alt_mode.h
new file mode 100644
index 0000000000..15b3f07d40
--- /dev/null
+++ b/zephyr/test/drivers/usbc_alt_mode/include/test_usbc_alt_mode.h
@@ -0,0 +1,50 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef ZEPHYR_TEST_DRIVERS_USBC_ALT_MODE_TEST_USBC_ALT_MODE_H_
+#define ZEPHYR_TEST_DRIVERS_USBC_ALT_MODE_TEST_USBC_ALT_MODE_H_
+
+#include "compile_time_macros.h"
+#include "emul/tcpc/emul_tcpci.h"
+#include "emul/tcpc/emul_tcpci_partner_snk.h"
+#include "test/drivers/stubs.h"
+
+#define TEST_PORT 0
+
+/* Arbitrary */
+#define PARTNER_PRODUCT_ID 0x1234
+#define PARTNER_DEV_BINARY_CODED_DECIMAL 0x5678
+
+BUILD_ASSERT(TEST_PORT == USBC_PORT_C0);
+
+struct usbc_alt_mode_fixture {
+	const struct emul *tcpci_emul;
+	const struct emul *charger_emul;
+	struct tcpci_partner_data partner;
+	struct tcpci_src_emul_data src_ext;
+};
+
+struct usbc_alt_mode_dp_unsupported_fixture {
+	const struct emul *tcpci_emul;
+	const struct emul *charger_emul;
+	struct tcpci_partner_data partner;
+	struct tcpci_src_emul_data src_ext;
+};
+
+struct usbc_alt_mode_minus_dp_configure_fixture {
+	const struct emul *tcpci_emul;
+	const struct emul *charger_emul;
+	struct tcpci_partner_data partner;
+	struct tcpci_src_emul_data src_ext;
+};
+
+struct usbc_discovery_no_drs_fixture {
+	const struct emul *tcpci_emul;
+	const struct emul *charger_emul;
+	struct tcpci_partner_data partner;
+	struct tcpci_src_emul_data src_ext;
+};
+
+#endif /* ZEPHYR_TEST_DRIVERS_USBC_ALT_MODE_TEST_USBC_ALT_MODE_H_ */
diff --git a/zephyr/test/drivers/usbc_alt_mode/prj.conf b/zephyr/test/drivers/usbc_alt_mode/prj.conf
new file mode 100644
index 0000000000..ce0e7f18a6
--- /dev/null
+++ b/zephyr/test/drivers/usbc_alt_mode/prj.conf
@@ -0,0 +1,5 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_PLATFORM_EC_USB_PD_DP_HPD_GPIO=y
diff --git a/zephyr/test/drivers/usbc_alt_mode/src/usbc_alt_mode.c b/zephyr/test/drivers/usbc_alt_mode/src/usbc_alt_mode.c
new file mode 100644
index 0000000000..17959e185a
--- /dev/null
+++ b/zephyr/test/drivers/usbc_alt_mode/src/usbc_alt_mode.c
@@ -0,0 +1,713 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+#include "ec_tasks.h"
+#include "emul/emul_isl923x.h"
+#include "emul/tcpc/emul_ps8xxx.h"
+#include "emul/tcpc/emul_tcpci.h"
+#include "emul/tcpc/emul_tcpci_partner_common.h"
+#include "emul/tcpc/emul_tcpci_partner_snk.h"
+#include "host_command.h"
+#include "tcpm/tcpci.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "test_usbc_alt_mode.h"
+
+#include <stdint.h>
+
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+#include <gpio.h>
+
+#define TEST_PORT 0
+
+/* Arbitrary */
+#define PARTNER_PRODUCT_ID 0x1234
+#define PARTNER_DEV_BINARY_CODED_DECIMAL 0x5678
+
+BUILD_ASSERT(TEST_PORT == USBC_PORT_C0);
+
+static void connect_partner_to_port(const struct emul *tcpc_emul,
+				    const struct emul *charger_emul,
+				    struct tcpci_partner_data *partner_emul,
+				    const struct tcpci_src_emul_data *src_ext)
+{
+	/*
+	 * TODO(b/221439302) Updating the TCPCI emulator registers, updating the
+	 *   vbus, as well as alerting should all be a part of the connect
+	 *   function.
+	 */
+	set_ac_enabled(true);
+	zassert_ok(tcpci_partner_connect_to_tcpci(partner_emul, tcpc_emul),
+		   NULL);
+
+	isl923x_emul_set_adc_vbus(charger_emul,
+				  PDO_FIXED_GET_VOLT(src_ext->pdo[0]));
+
+	/* Wait for PD negotiation and current ramp. */
+	k_sleep(K_SECONDS(10));
+}
+
+static void disconnect_partner_from_port(const struct emul *tcpc_emul,
+					 const struct emul *charger_emul)
+{
+	zassert_ok(tcpci_emul_disconnect_partner(tcpc_emul));
+	isl923x_emul_set_adc_vbus(charger_emul, 0);
+	k_sleep(K_SECONDS(1));
+}
+
+static void add_discovery_responses(struct tcpci_partner_data *partner)
+{
+	/* Add Discover Identity response */
+	partner->identity_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_PD, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_IDENT);
+	partner->identity_vdm[VDO_INDEX_IDH] = VDO_IDH(
+		/* USB host */ false, /* USB device */ false, IDH_PTYPE_AMA,
+		/* modal operation */ true, USB_VID_GOOGLE);
+	partner->identity_vdm[VDO_INDEX_CSTAT] = 0xabcdabcd;
+	partner->identity_vdm[VDO_INDEX_PRODUCT] = VDO_PRODUCT(
+		PARTNER_PRODUCT_ID, PARTNER_DEV_BINARY_CODED_DECIMAL);
+	/* Hardware version 1, firmware version 2 */
+	partner->identity_vdm[VDO_INDEX_AMA] = 0x12000000;
+	partner->identity_vdos = VDO_INDEX_AMA + 1;
+
+	/* Add Discover Modes response */
+	/* Support one mode for DisplayPort VID. Copied from Hoho. */
+	partner->modes_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_DISPLAYPORT, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_MODES);
+	partner->modes_vdm[VDO_INDEX_HDR + 1] = VDO_MODE_DP(
+		0, MODE_DP_PIN_C, 1, CABLE_PLUG, MODE_DP_V13, MODE_DP_SNK);
+	partner->modes_vdos = VDO_INDEX_HDR + 2;
+
+	/* Add Discover SVIDs response */
+	/* Support DisplayPort VID. */
+	partner->svids_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_PD, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_SVID);
+	partner->svids_vdm[VDO_INDEX_HDR + 1] =
+		VDO_SVID(USB_SID_DISPLAYPORT, 0);
+	partner->svids_vdos = VDO_INDEX_HDR + 2;
+}
+
+static void add_displayport_mode_responses(struct tcpci_partner_data *partner)
+{
+	/* DisplayPort alt mode setup remains in the same suite as discovery
+	 * setup because DisplayPort is picked from the Discovery VDOs offered.
+	 */
+
+	/* Add DisplayPort EnterMode response */
+	partner->enter_mode_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_DISPLAYPORT, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_ENTER_MODE);
+	partner->enter_mode_vdos = VDO_INDEX_HDR + 1;
+
+	/* Add DisplayPort StatusUpdate response */
+	partner->dp_status_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_DISPLAYPORT, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DP_STATUS);
+	partner->dp_status_vdm[VDO_INDEX_HDR + 1] =
+		/* Mainly copied from hoho */
+		VDO_DP_STATUS(0, /* IRQ_HPD */
+			      false, /* HPD_HI|LOW - Changed*/
+			      0, /* request exit DP */
+			      0, /* request exit USB */
+			      0, /* MF pref */
+			      true, /* DP Enabled */
+			      0, /* power low e.g. normal */
+			      0x2 /* Connected as Sink */);
+	partner->dp_status_vdos = VDO_INDEX_HDR + 2;
+
+	/* Add DisplayPort Configure Response */
+	partner->dp_config_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_DISPLAYPORT, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DP_CONFIG);
+	partner->dp_config_vdos = VDO_INDEX_HDR + 1;
+}
+
+static void add_displayport_mode_responses__minus_configure_responses(
+	struct tcpci_partner_data *partner)
+{
+	/*
+	 * This is the same function as add_displayport_mode_responses() but
+	 * does not include the configure response so as to induce a failure to
+	 * enter dp alt mode
+	 */
+
+	/* Add DisplayPort EnterMode response */
+	partner->enter_mode_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_DISPLAYPORT, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_ENTER_MODE);
+	partner->enter_mode_vdos = VDO_INDEX_HDR + 1;
+
+	/* Add DisplayPort StatusUpdate response */
+	partner->dp_status_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_DISPLAYPORT, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DP_STATUS);
+	partner->dp_status_vdm[VDO_INDEX_HDR + 1] =
+		/* Mainly copied from hoho */
+		VDO_DP_STATUS(0, /* IRQ_HPD */
+			      false, /* HPD_HI|LOW - Changed*/
+			      0, /* request exit DP */
+			      0, /* request exit USB */
+			      0, /* MF pref */
+			      true, /* DP Enabled */
+			      0, /* power low e.g. normal */
+			      0x2 /* Connected as Sink */);
+	partner->dp_status_vdos = VDO_INDEX_HDR + 2;
+
+	/* NO DisplayPort Configure Response */
+}
+
+static void *usbc_alt_mode_setup(void)
+{
+	static struct usbc_alt_mode_fixture fixture;
+	struct tcpci_partner_data *partner = &fixture.partner;
+	struct tcpci_src_emul_data *src_ext = &fixture.src_ext;
+
+	tcpci_partner_init(partner, PD_REV20);
+	partner->extensions = tcpci_src_emul_init(src_ext, partner, NULL);
+
+	/* Get references for the emulators */
+	fixture.tcpci_emul = EMUL_GET_USBC_BINDING(TEST_PORT, tcpc);
+	fixture.charger_emul = EMUL_GET_USBC_BINDING(TEST_PORT, chg);
+
+	add_discovery_responses(partner);
+
+	return &fixture;
+}
+
+static void usbc_alt_mode_before(void *data)
+{
+	/* Set chipset to ON, this will set TCPM to DRP */
+	test_set_chipset_to_s0();
+
+	/* TODO(b/214401892): Check why need to give time TCPM to spin */
+	k_sleep(K_SECONDS(1));
+
+	struct usbc_alt_mode_fixture *fixture = data;
+
+	/* Re-populate our usual responses in case a test overrode them */
+	add_displayport_mode_responses(&fixture->partner);
+	connect_partner_to_port(fixture->tcpci_emul, fixture->charger_emul,
+				&fixture->partner, &fixture->src_ext);
+}
+
+static void usbc_alt_mode_after(void *data)
+{
+	struct usbc_alt_mode_fixture *fixture = data;
+
+	disconnect_partner_from_port(fixture->tcpci_emul,
+				     fixture->charger_emul);
+}
+
+ZTEST_F(usbc_alt_mode, test_verify_discovery)
+{
+	uint8_t response_buffer[EC_LPC_HOST_PACKET_SIZE];
+	struct ec_response_typec_discovery *discovery =
+		(struct ec_response_typec_discovery *)response_buffer;
+	host_cmd_typec_discovery(TEST_PORT, TYPEC_PARTNER_SOP, response_buffer,
+				 sizeof(response_buffer));
+
+	/* The host command does not count the VDM header in identity_count. */
+	zassert_equal(discovery->identity_count,
+		      fixture->partner.identity_vdos - 1,
+		      "Expected %d identity VDOs, got %d",
+		      fixture->partner.identity_vdos - 1,
+		      discovery->identity_count);
+	zassert_mem_equal(
+		discovery->discovery_vdo, fixture->partner.identity_vdm + 1,
+		discovery->identity_count * sizeof(*discovery->discovery_vdo),
+		"Discovered SOP identity ACK did not match");
+	zassert_equal(discovery->svid_count, 1, "Expected 1 SVID, got %d",
+		      discovery->svid_count);
+	zassert_equal(discovery->svids[0].svid, USB_SID_DISPLAYPORT,
+		      "Expected SVID 0x%0000x, got 0x%0000x",
+		      USB_SID_DISPLAYPORT, discovery->svids[0].svid);
+	zassert_equal(discovery->svids[0].mode_count, 1,
+		      "Expected 1 DP mode, got %d",
+		      discovery->svids[0].mode_count);
+	zassert_equal(discovery->svids[0].mode_vdo[0],
+		      fixture->partner.modes_vdm[1],
+		      "DP mode VDOs did not match");
+}
+
+ZTEST_F(usbc_alt_mode, test_verify_discovery_params_too_small)
+{
+	struct ec_response_typec_discovery discovery;
+
+	/* The expected size of the response buffer is larger than struct
+	 * ec_response_typec_discovery. With only that amount of space, the
+	 * command should succeed but not return any of the discovered SVIDs.
+	 */
+	host_cmd_typec_discovery(TEST_PORT, TYPEC_PARTNER_SOP, &discovery,
+				 sizeof(discovery));
+	zassert_equal(discovery.svid_count, 0);
+}
+
+ZTEST_F(usbc_alt_mode, test_verify_displayport_mode_entry)
+{
+	const struct gpio_dt_spec *gpio =
+		GPIO_DT_FROM_NODELABEL(gpio_usb_c0_hpd);
+
+	if (IS_ENABLED(CONFIG_PLATFORM_EC_USB_PD_REQUIRE_AP_MODE_ENTRY)) {
+		host_cmd_typec_control_enter_mode(TEST_PORT, TYPEC_MODE_DP);
+		k_sleep(K_SECONDS(1));
+	}
+
+	/* Verify host command when VDOs are present. */
+	struct ec_response_typec_status status;
+
+	/* DPM configures the partner on DP mode entry */
+	/* Verify port partner thinks its configured for DisplayPort */
+	zassert_true(fixture->partner.displayport_configured);
+	/* Verify we also set up DP on our mux */
+	status = host_cmd_typec_status(TEST_PORT);
+	zassert_equal((status.mux_state & USB_PD_MUX_DP_ENABLED),
+		      USB_PD_MUX_DP_ENABLED, "Failed to see DP set in mux");
+
+	/*
+	 * DP alt mode partner sends HPD through VDM:Attention, which uses the
+	 * same format as the DP Status data
+	 */
+	uint32_t vdm_attention_data[2];
+
+	vdm_attention_data[0] =
+		VDO(USB_SID_DISPLAYPORT, 1,
+		    VDO_OPOS(1) | VDO_CMDT(CMDT_INIT) | CMD_ATTENTION);
+	vdm_attention_data[1] = VDO_DP_STATUS(1, /* IRQ_HPD */
+					      true, /* HPD_HI|LOW - Changed*/
+					      0, /* request exit DP */
+					      0, /* request exit USB */
+					      0, /* MF pref */
+					      true, /* DP Enabled */
+					      0, /* power low e.g. normal */
+					      0x2 /* Connected as Sink */);
+	tcpci_partner_send_data_msg(&fixture->partner, PD_DATA_VENDOR_DEF,
+				    vdm_attention_data, 2, 0);
+
+	k_sleep(K_SECONDS(1));
+	/* Verify the board's HPD notification triggered */
+	status = host_cmd_typec_status(TEST_PORT);
+	zassert_equal((status.mux_state & USB_PD_MUX_HPD_LVL),
+		      USB_PD_MUX_HPD_LVL, "Failed to set HPD level in mux");
+	zassert_equal((status.mux_state & USB_PD_MUX_HPD_IRQ),
+		      USB_PD_MUX_HPD_IRQ, "Failed to set HPD IRQ in mux");
+	zassert_equal(gpio_emul_output_get(gpio->port, gpio->pin), 1);
+}
+
+ZTEST_F(usbc_alt_mode, test_verify_bad_hpd_irq_reject)
+{
+	const struct gpio_dt_spec *gpio =
+		GPIO_DT_FROM_NODELABEL(gpio_usb_c0_hpd);
+
+	if (IS_ENABLED(CONFIG_PLATFORM_EC_USB_PD_REQUIRE_AP_MODE_ENTRY)) {
+		host_cmd_typec_control_enter_mode(TEST_PORT, TYPEC_MODE_DP);
+		k_sleep(K_SECONDS(1));
+	}
+
+	/*
+	 * Compose a bad Attention packet which sets IRQ with HPD low
+	 */
+	uint32_t vdm_attention_data[2];
+
+	vdm_attention_data[0] =
+		VDO(USB_SID_DISPLAYPORT, 1,
+		    VDO_OPOS(1) | VDO_CMDT(CMDT_INIT) | CMD_ATTENTION);
+	vdm_attention_data[1] = VDO_DP_STATUS(1, /* IRQ_HPD */
+					      false, /* HPD_HI|LOW - Changed*/
+					      0, /* request exit DP */
+					      0, /* request exit USB */
+					      0, /* MF pref */
+					      true, /* DP Enabled */
+					      0, /* power low e.g. normal */
+					      0x2 /* Connected as Sink */);
+	tcpci_partner_send_data_msg(&fixture->partner, PD_DATA_VENDOR_DEF,
+				    vdm_attention_data, 2, 0);
+	k_sleep(K_SECONDS(1));
+
+	/* Verify that no HPD notification triggered */
+	struct ec_response_typec_status status;
+
+	status = host_cmd_typec_status(TEST_PORT);
+	zassert_not_equal((status.mux_state & USB_PD_MUX_HPD_LVL),
+			  USB_PD_MUX_HPD_LVL);
+	zassert_not_equal((status.mux_state & USB_PD_MUX_HPD_IRQ),
+			  USB_PD_MUX_HPD_IRQ);
+	zassert_equal(gpio_emul_output_get(gpio->port, gpio->pin), 0);
+}
+
+ZTEST_F(usbc_alt_mode, test_verify_hpd_clear)
+{
+	const struct gpio_dt_spec *gpio =
+		GPIO_DT_FROM_NODELABEL(gpio_usb_c0_hpd);
+
+	if (IS_ENABLED(CONFIG_PLATFORM_EC_USB_PD_REQUIRE_AP_MODE_ENTRY)) {
+		host_cmd_typec_control_enter_mode(TEST_PORT, TYPEC_MODE_DP);
+		k_sleep(K_SECONDS(1));
+	}
+
+	/*
+	 * Set our HPD to high and then low, ensuring our HPD indicators
+	 * track this
+	 */
+	uint32_t vdm_attention_data[2];
+
+	vdm_attention_data[0] =
+		VDO(USB_SID_DISPLAYPORT, 1,
+		    VDO_OPOS(1) | VDO_CMDT(CMDT_INIT) | CMD_ATTENTION);
+	vdm_attention_data[1] = VDO_DP_STATUS(0, /* IRQ_HPD */
+					      true, /* HPD_HI|LOW - Changed*/
+					      0, /* request exit DP */
+					      0, /* request exit USB */
+					      0, /* MF pref */
+					      true, /* DP Enabled */
+					      0, /* power low e.g. normal */
+					      0x2 /* Connected as Sink */);
+	tcpci_partner_send_data_msg(&fixture->partner, PD_DATA_VENDOR_DEF,
+				    vdm_attention_data, 2, 0);
+	k_sleep(K_SECONDS(1));
+
+	/* Verify that HPD notification triggered */
+	struct ec_response_typec_status status;
+
+	status = host_cmd_typec_status(TEST_PORT);
+	zassert_equal((status.mux_state & USB_PD_MUX_HPD_LVL),
+		      USB_PD_MUX_HPD_LVL);
+	zassert_equal(gpio_emul_output_get(gpio->port, gpio->pin), 1);
+
+	vdm_attention_data[1] = VDO_DP_STATUS(0, /* IRQ_HPD */
+					      false, /* HPD_HI|LOW - Changed*/
+					      0, /* request exit DP */
+					      0, /* request exit USB */
+					      0, /* MF pref */
+					      true, /* DP Enabled */
+					      0, /* power low e.g. normal */
+					      0x2 /* Connected as Sink */);
+	tcpci_partner_send_data_msg(&fixture->partner, PD_DATA_VENDOR_DEF,
+				    vdm_attention_data, 2, 0);
+
+	k_sleep(K_SECONDS(1));
+	/* Verify that HPD cleared */
+	status = host_cmd_typec_status(TEST_PORT);
+	zassert_not_equal((status.mux_state & USB_PD_MUX_HPD_LVL),
+			  USB_PD_MUX_HPD_LVL);
+	zassert_equal(gpio_emul_output_get(gpio->port, gpio->pin), 0);
+}
+
+ZTEST_F(usbc_alt_mode, test_verify_hpd_irq_set)
+{
+	const struct gpio_dt_spec *gpio =
+		GPIO_DT_FROM_NODELABEL(gpio_usb_c0_hpd);
+
+	if (IS_ENABLED(CONFIG_PLATFORM_EC_USB_PD_REQUIRE_AP_MODE_ENTRY)) {
+		host_cmd_typec_control_enter_mode(TEST_PORT, TYPEC_MODE_DP);
+		k_sleep(K_SECONDS(1));
+	}
+
+	/*
+	 * Set our HPD to high and toggle the IRQ low to high
+	 */
+	uint32_t vdm_attention_data[2];
+
+	vdm_attention_data[0] =
+		VDO(USB_SID_DISPLAYPORT, 1,
+		    VDO_OPOS(1) | VDO_CMDT(CMDT_INIT) | CMD_ATTENTION);
+	vdm_attention_data[1] = VDO_DP_STATUS(0, /* IRQ_HPD */
+					      true, /* HPD_HI|LOW - Changed*/
+					      0, /* request exit DP */
+					      0, /* request exit USB */
+					      0, /* MF pref */
+					      true, /* DP Enabled */
+					      0, /* power low e.g. normal */
+					      0x2 /* Connected as Sink */);
+	tcpci_partner_send_data_msg(&fixture->partner, PD_DATA_VENDOR_DEF,
+				    vdm_attention_data, 2, 0);
+	k_sleep(K_SECONDS(1));
+
+	/* Verify that HPD notification triggered */
+	struct ec_response_typec_status status;
+
+	status = host_cmd_typec_status(TEST_PORT);
+	zassert_equal((status.mux_state & USB_PD_MUX_HPD_LVL),
+		      USB_PD_MUX_HPD_LVL);
+	zassert_not_equal((status.mux_state & USB_PD_MUX_HPD_IRQ),
+			  USB_PD_MUX_HPD_IRQ);
+	zassert_equal(gpio_emul_output_get(gpio->port, gpio->pin), 1);
+
+	vdm_attention_data[1] = VDO_DP_STATUS(1, /* IRQ_HPD */
+					      true, /* HPD_HI|LOW - Changed*/
+					      0, /* request exit DP */
+					      0, /* request exit USB */
+					      0, /* MF pref */
+					      true, /* DP Enabled */
+					      0, /* power low e.g. normal */
+					      0x2 /* Connected as Sink */);
+	tcpci_partner_send_data_msg(&fixture->partner, PD_DATA_VENDOR_DEF,
+				    vdm_attention_data, 2, 0);
+
+	k_sleep(K_SECONDS(1));
+	/* Verify that HPD IRQ set now */
+	status = host_cmd_typec_status(TEST_PORT);
+	zassert_equal((status.mux_state & USB_PD_MUX_HPD_LVL),
+		      USB_PD_MUX_HPD_LVL);
+	zassert_equal((status.mux_state & USB_PD_MUX_HPD_IRQ),
+		      USB_PD_MUX_HPD_IRQ);
+	zassert_equal(gpio_emul_output_get(gpio->port, gpio->pin), 1);
+}
+
+ZTEST_F(usbc_alt_mode, test_verify_discovery_via_pd_host_cmd)
+{
+	struct ec_params_usb_pd_info_request params = { .port = TEST_PORT };
+	struct ec_params_usb_pd_discovery_entry response;
+
+	struct host_cmd_handler_args args;
+
+	zassert_ok(ec_cmd_usb_pd_discovery(&args, &params, &response));
+	zassert_equal(args.response_size, sizeof(response));
+	zassert_equal(response.ptype, IDH_PTYPE_AMA);
+	zassert_equal(response.vid, USB_VID_GOOGLE);
+	zassert_equal(response.pid, PARTNER_PRODUCT_ID);
+}
+
+ZTEST_SUITE(usbc_alt_mode, drivers_predicate_post_main, usbc_alt_mode_setup,
+	    usbc_alt_mode_before, usbc_alt_mode_after, NULL);
+
+static void *usbc_alt_mode_dp_unsupported_setup(void)
+{
+	static struct usbc_alt_mode_dp_unsupported_fixture fixture;
+	struct tcpci_partner_data *partner = &fixture.partner;
+	struct tcpci_src_emul_data *src_ext = &fixture.src_ext;
+
+	tcpci_partner_init(partner, PD_REV20);
+	partner->extensions = tcpci_src_emul_init(src_ext, partner, NULL);
+
+	/* Get references for the emulators */
+	fixture.tcpci_emul = EMUL_GET_USBC_BINDING(TEST_PORT, tcpc);
+	fixture.charger_emul = EMUL_GET_USBC_BINDING(TEST_PORT, chg);
+
+	/*
+	 * Respond to discovery REQs to indicate DisplayPort support, but do not
+	 * respond to DisplayPort alt mode VDMs, including Enter Mode.
+	 */
+	add_discovery_responses(partner);
+
+	return &fixture;
+}
+
+static void usbc_alt_mode_dp_unsupported_before(void *data)
+{
+	/* Set chipset to ON, this will set TCPM to DRP */
+	test_set_chipset_to_s0();
+
+	/* TODO(b/214401892): Check why need to give time TCPM to spin */
+	k_sleep(K_SECONDS(1));
+
+	struct usbc_alt_mode_dp_unsupported_fixture *fixture = data;
+
+	connect_partner_to_port(fixture->tcpci_emul, fixture->charger_emul,
+				&fixture->partner, &fixture->src_ext);
+}
+
+static void usbc_alt_mode_dp_unsupported_after(void *data)
+{
+	struct usbc_alt_mode_dp_unsupported_fixture *fixture = data;
+
+	disconnect_partner_from_port(fixture->tcpci_emul,
+				     fixture->charger_emul);
+}
+
+/*
+ * When the partner advertises DP mode support but refuses to enter, discovery
+ * should still work as if the partner were compliant.
+ */
+ZTEST_F(usbc_alt_mode_dp_unsupported, test_verify_discovery)
+{
+	if (IS_ENABLED(CONFIG_PLATFORM_EC_USB_PD_REQUIRE_AP_MODE_ENTRY)) {
+		host_cmd_typec_control_enter_mode(TEST_PORT, TYPEC_MODE_DP);
+		k_sleep(K_SECONDS(1));
+	}
+
+	uint8_t response_buffer[EC_LPC_HOST_PACKET_SIZE];
+	struct ec_response_typec_discovery *discovery =
+		(struct ec_response_typec_discovery *)response_buffer;
+	host_cmd_typec_discovery(TEST_PORT, TYPEC_PARTNER_SOP, response_buffer,
+				 sizeof(response_buffer));
+
+	/* The host command does not count the VDM header in identity_count. */
+	zassert_equal(discovery->identity_count,
+		      fixture->partner.identity_vdos - 1,
+		      "Expected %d identity VDOs, got %d",
+		      fixture->partner.identity_vdos - 1,
+		      discovery->identity_count);
+	zassert_mem_equal(
+		discovery->discovery_vdo, fixture->partner.identity_vdm + 1,
+		discovery->identity_count * sizeof(*discovery->discovery_vdo),
+		"Discovered SOP identity ACK did not match");
+	zassert_equal(discovery->svid_count, 1, "Expected 1 SVID, got %d",
+		      discovery->svid_count);
+	zassert_equal(discovery->svids[0].svid, USB_SID_DISPLAYPORT,
+		      "Expected SVID 0x%0000x, got 0x%0000x",
+		      USB_SID_DISPLAYPORT, discovery->svids[0].svid);
+	zassert_equal(discovery->svids[0].mode_count, 1,
+		      "Expected 1 DP mode, got %d",
+		      discovery->svids[0].mode_count);
+	zassert_equal(discovery->svids[0].mode_vdo[0],
+		      fixture->partner.modes_vdm[1],
+		      "DP mode VDOs did not match");
+}
+
+/*
+ * When the partner advertises DP support but refuses to enter DP mode, the TCPM
+ * should try once and then give up.
+ */
+ZTEST_F(usbc_alt_mode_dp_unsupported, test_verify_displayport_mode_nonentry)
+{
+	if (IS_ENABLED(CONFIG_PLATFORM_EC_USB_PD_REQUIRE_AP_MODE_ENTRY)) {
+		host_cmd_typec_control_enter_mode(TEST_PORT, TYPEC_MODE_DP);
+		k_sleep(K_SECONDS(1));
+	}
+
+	zassert_false(fixture->partner.displayport_configured);
+	int dp_attempts = atomic_get(&fixture->partner.mode_enter_attempts);
+	zassert_equal(dp_attempts, 1, "Expected 1 DP attempt, got %d",
+		      dp_attempts);
+}
+
+ZTEST_SUITE(usbc_alt_mode_dp_unsupported, drivers_predicate_post_main,
+	    usbc_alt_mode_dp_unsupported_setup,
+	    usbc_alt_mode_dp_unsupported_before,
+	    usbc_alt_mode_dp_unsupported_after, NULL);
+
+static void *usbc_alt_mode_minus_dp_configure_setup(void)
+{
+	static struct usbc_alt_mode_minus_dp_configure_fixture fixture;
+	struct tcpci_partner_data *partner = &fixture.partner;
+	struct tcpci_src_emul_data *src_ext = &fixture.src_ext;
+
+	tcpci_partner_init(partner, PD_REV20);
+	partner->extensions = tcpci_src_emul_init(src_ext, partner, NULL);
+
+	/* Get references for the emulators */
+	fixture.tcpci_emul = EMUL_GET_USBC_BINDING(TEST_PORT, tcpc);
+	fixture.charger_emul = EMUL_GET_USBC_BINDING(TEST_PORT, chg);
+
+	add_discovery_responses(partner);
+	add_displayport_mode_responses__minus_configure_responses(partner);
+
+	return &fixture;
+}
+
+static void usbc_alt_mode_minus_dp_configure_before(void *data)
+{
+	/* Set chipset to ON, this will set TCPM to DRP */
+	test_set_chipset_to_s0();
+
+	/* TODO(b/214401892): Check why need to give time TCPM to spin */
+	k_sleep(K_SECONDS(1));
+
+	struct usbc_alt_mode_minus_dp_configure_fixture *fixture = data;
+
+	connect_partner_to_port(fixture->tcpci_emul, fixture->charger_emul,
+				&fixture->partner, &fixture->src_ext);
+}
+
+static void usbc_alt_mode_minus_dp_configure_after(void *data)
+{
+	struct usbc_alt_mode_fixture *fixture = data;
+
+	disconnect_partner_from_port(fixture->tcpci_emul,
+				     fixture->charger_emul);
+}
+
+ZTEST_F(usbc_alt_mode_minus_dp_configure, test_dp_mode_entry_minus_config)
+{
+	if (IS_ENABLED(CONFIG_PLATFORM_EC_USB_PD_REQUIRE_AP_MODE_ENTRY)) {
+		host_cmd_typec_control_enter_mode(TEST_PORT, TYPEC_MODE_DP);
+		k_sleep(K_SECONDS(1));
+	}
+
+	/* Verify host command when VDOs are present. */
+	struct ec_response_typec_status status;
+
+	/* DPM configures the partner on DP mode entry */
+	/* Verify port partner thinks it's *NOT* configured for DisplayPort */
+	zassert_false(fixture->partner.displayport_configured);
+	/* Also verify DP config is missing from mux */
+	status = host_cmd_typec_status(TEST_PORT);
+	zassert_not_equal((status.mux_state & USB_PD_MUX_DP_ENABLED),
+			  USB_PD_MUX_DP_ENABLED,
+			  "Failed to *NOT* see DP set in mux");
+}
+
+ZTEST_SUITE(usbc_alt_mode_minus_dp_configure, drivers_predicate_post_main,
+	    usbc_alt_mode_minus_dp_configure_setup,
+	    usbc_alt_mode_minus_dp_configure_before,
+	    usbc_alt_mode_minus_dp_configure_after, NULL);
+
+/* Set up the partner to refuse to swap to UFP, preventing discovery in PD 2.0.
+ * Configure DP alt mode responses to try to catch the TCPM entering DP mode
+ * anyway.
+ */
+static void *usbc_alt_mode_no_drs_setup(void)
+{
+	static struct usbc_alt_mode_fixture fixture;
+	struct tcpci_partner_data *partner = &fixture.partner;
+	struct tcpci_src_emul_data *src_ext = &fixture.src_ext;
+
+	tcpci_partner_init(partner, PD_REV20);
+	partner->extensions = tcpci_src_emul_init(src_ext, partner, NULL);
+	tcpci_partner_set_drs_support(partner, /*drs_to_ufp_supported=*/false,
+				      /*drs_to_dfp_supported=*/true);
+
+	/* Get references for the emulators */
+	fixture.tcpci_emul = EMUL_GET_USBC_BINDING(TEST_PORT, tcpc);
+	fixture.charger_emul = EMUL_GET_USBC_BINDING(TEST_PORT, chg);
+
+	add_discovery_responses(partner);
+
+	return &fixture;
+}
+
+ZTEST_F(usbc_discovery_no_drs, test_no_drs_no_discovery)
+{
+	/* Verify host command when VDOs are present. */
+	struct ec_response_typec_status status =
+		host_cmd_typec_status(TEST_PORT);
+	uint8_t response_buffer[EC_LPC_HOST_PACKET_SIZE];
+	struct ec_response_typec_discovery *discovery =
+		(struct ec_response_typec_discovery *)response_buffer;
+
+	/* Verify port partner does not think it's configured for DisplayPort */
+	zassert_false(fixture->partner.displayport_configured);
+
+	/* Verify TCPM reports discovery done with no data from partner. */
+	zassert_true(status.events & PD_STATUS_EVENT_SOP_DISC_DONE);
+	zassert_true(status.events & PD_STATUS_EVENT_SOP_PRIME_DISC_DONE);
+
+	host_cmd_typec_discovery(TEST_PORT, TYPEC_PARTNER_SOP, response_buffer,
+				 sizeof(response_buffer));
+	zassert_equal(discovery->identity_count, 0,
+		      "Expected 0 identity VDOs, got %d",
+		      discovery->identity_count);
+
+	/* Verify TCPM does not notify AP of discovery done again. */
+	host_cmd_typec_control_clear_events(
+		TEST_PORT, PD_STATUS_EVENT_SOP_DISC_DONE |
+				   PD_STATUS_EVENT_SOP_PRIME_DISC_DONE);
+	k_sleep(K_MSEC(100));
+	status = host_cmd_typec_status(TEST_PORT);
+	zassert_false(status.events & (PD_STATUS_EVENT_SOP_DISC_DONE |
+				       PD_STATUS_EVENT_SOP_PRIME_DISC_DONE));
+}
+
+ZTEST_SUITE(usbc_discovery_no_drs, drivers_predicate_post_main,
+	    usbc_alt_mode_no_drs_setup, usbc_alt_mode_before,
+	    usbc_alt_mode_after, NULL);
diff --git a/zephyr/test/drivers/usbc_alt_mode/src/usbc_alt_mode__require_ap_mode_entry.c b/zephyr/test/drivers/usbc_alt_mode/src/usbc_alt_mode__require_ap_mode_entry.c
new file mode 100644
index 0000000000..6d1286b2e5
--- /dev/null
+++ b/zephyr/test/drivers/usbc_alt_mode/src/usbc_alt_mode__require_ap_mode_entry.c
@@ -0,0 +1,126 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "test/drivers/utils.h"
+#include "test_usbc_alt_mode.h"
+
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+#include <gpio.h>
+
+/* Tests that require CONFIG_PLATFORM_EC_USB_PD_REQUIRE_AP_MODE_ENTRY enabled */
+
+ZTEST_F(usbc_alt_mode, test_verify_displayport_mode_reentry)
+{
+	if (!IS_ENABLED(CONFIG_PLATFORM_EC_USB_PD_REQUIRE_AP_MODE_ENTRY)) {
+		ztest_test_skip();
+	}
+
+	host_cmd_typec_control_enter_mode(TEST_PORT, TYPEC_MODE_DP);
+	k_sleep(K_SECONDS(1));
+
+	/* DPM configures the partner on DP mode entry */
+	/* Verify port partner thinks its configured for DisplayPort */
+	zassert_true(fixture->partner.displayport_configured);
+
+	host_cmd_typec_control_exit_modes(TEST_PORT);
+	k_sleep(K_SECONDS(1));
+	zassert_false(fixture->partner.displayport_configured);
+
+	host_cmd_typec_control_enter_mode(TEST_PORT, TYPEC_MODE_DP);
+	k_sleep(K_SECONDS(1));
+	zassert_true(fixture->partner.displayport_configured);
+
+	/*
+	 * Verify that DisplayPort is the active alternate mode by checking our
+	 * MUX settings
+	 */
+	struct ec_response_typec_status status;
+
+	status = host_cmd_typec_status(TEST_PORT);
+	zassert_equal((status.mux_state & USB_PD_MUX_DP_ENABLED),
+		      USB_PD_MUX_DP_ENABLED, "Failed to see DP mux set");
+}
+
+ZTEST_F(usbc_alt_mode, test_verify_mode_exit_via_pd_host_cmd)
+{
+	const struct gpio_dt_spec *gpio =
+		GPIO_DT_FROM_NODELABEL(gpio_usb_c0_hpd);
+
+	if (!IS_ENABLED(CONFIG_PLATFORM_EC_USB_PD_REQUIRE_AP_MODE_ENTRY)) {
+		ztest_test_skip();
+	}
+
+	host_cmd_typec_control_enter_mode(TEST_PORT, TYPEC_MODE_DP);
+	k_sleep(K_SECONDS(1));
+
+	/*
+	 * Set HPD so we can see it clear on Exit
+	 */
+	uint32_t vdm_attention_data[2];
+
+	vdm_attention_data[0] =
+		VDO(USB_SID_DISPLAYPORT, 1,
+		    VDO_OPOS(1) | VDO_CMDT(CMDT_INIT) | CMD_ATTENTION);
+	vdm_attention_data[1] = VDO_DP_STATUS(1, /* IRQ_HPD */
+					      true, /* HPD_HI|LOW - Changed*/
+					      0, /* request exit DP */
+					      0, /* request exit USB */
+					      0, /* MF pref */
+					      true, /* DP Enabled */
+					      0, /* power low e.g. normal */
+					      0x2 /* Connected as Sink */);
+	tcpci_partner_send_data_msg(&fixture->partner, PD_DATA_VENDOR_DEF,
+				    vdm_attention_data, 2, 0);
+
+	k_sleep(K_SECONDS(1));
+	zassert_equal(gpio_emul_output_get(gpio->port, gpio->pin), 1);
+
+	host_cmd_typec_control_exit_modes(TEST_PORT);
+	k_sleep(K_SECONDS(1));
+	zassert_false(fixture->partner.displayport_configured);
+	zassert_equal(gpio_emul_output_get(gpio->port, gpio->pin), 0);
+
+	/*
+	 * Verify that DisplayPort is no longer active by checking our
+	 * MUX settings
+	 */
+	struct ec_response_typec_status status;
+
+	status = host_cmd_typec_status(TEST_PORT);
+	zassert_equal((status.mux_state & USB_PD_MUX_DP_ENABLED), 0);
+}
+
+ZTEST_F(usbc_alt_mode, test_verify_early_status_hpd_set)
+{
+	const struct gpio_dt_spec *gpio =
+		GPIO_DT_FROM_NODELABEL(gpio_usb_c0_hpd);
+
+	if (!IS_ENABLED(CONFIG_PLATFORM_EC_USB_PD_REQUIRE_AP_MODE_ENTRY)) {
+		ztest_test_skip();
+	}
+
+	/*
+	 * Tweak our DP:Status reply to set HPD and ensure it's transmitted
+	 * through our HPD GPIO
+	 */
+	fixture->partner.dp_status_vdm[VDO_INDEX_HDR + 1] =
+		/* Mainly copied from hoho */
+		VDO_DP_STATUS(0, /* IRQ_HPD */
+			      true, /* HPD_HI|LOW - Changed*/
+			      0, /* request exit DP */
+			      0, /* request exit USB */
+			      0, /* MF pref */
+			      true, /* DP Enabled */
+			      0, /* power low e.g. normal */
+			      0x2 /* Connected as Sink */);
+
+	host_cmd_typec_control_enter_mode(TEST_PORT, TYPEC_MODE_DP);
+	k_sleep(K_SECONDS(1));
+
+	zassert_equal(gpio_emul_output_get(gpio->port, gpio->pin), 1);
+}
diff --git a/zephyr/test/drivers/usbc_alt_mode/src/usbc_alt_mode_ec_mode_entry.c b/zephyr/test/drivers/usbc_alt_mode/src/usbc_alt_mode_ec_mode_entry.c
new file mode 100644
index 0000000000..8344b37ee9
--- /dev/null
+++ b/zephyr/test/drivers/usbc_alt_mode/src/usbc_alt_mode_ec_mode_entry.c
@@ -0,0 +1,45 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+#include "emul/tcpc/emul_tcpci_partner_common.h"
+#include "mock/power.h"
+#include "test/drivers/utils.h"
+#include "test_usbc_alt_mode.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+#include <zephyr/ztest_assert.h>
+#include <zephyr/ztest_test_new.h>
+
+/* Tests that require CONFIG_PLATFORM_EC_USB_PD_REQUIRE_AP_MODE_ENTRY disabled
+ */
+
+ZTEST_F(usbc_alt_mode, test_verify_displayport_mode_power_cycle)
+{
+	struct ec_response_typec_status status;
+
+	/* Verify that the TCPM enters DP mode on attach, exits on AP power-off,
+	 * and enters again on AP power on.
+	 */
+
+	zassert_true(fixture->partner.displayport_configured, NULL);
+	status = host_cmd_typec_status(TEST_PORT);
+	zassert_equal((status.mux_state & USB_PD_MUX_DP_ENABLED),
+		      USB_PD_MUX_DP_ENABLED);
+
+	mock_power_request(POWER_REQ_SOFT_OFF);
+
+	zassert_false(fixture->partner.displayport_configured, NULL);
+	status = host_cmd_typec_status(TEST_PORT);
+	zassert_equal((status.mux_state & USB_PD_MUX_DP_ENABLED), 0);
+
+	mock_power_request(POWER_REQ_ON);
+
+	zassert_true(fixture->partner.displayport_configured, NULL);
+	status = host_cmd_typec_status(TEST_PORT);
+	zassert_equal((status.mux_state & USB_PD_MUX_DP_ENABLED),
+		      USB_PD_MUX_DP_ENABLED);
+}
diff --git a/zephyr/test/drivers/usbc_console_pd/CMakeLists.txt b/zephyr/test/drivers/usbc_console_pd/CMakeLists.txt
new file mode 100644
index 0000000000..7bd3e9e089
--- /dev/null
+++ b/zephyr/test/drivers/usbc_console_pd/CMakeLists.txt
@@ -0,0 +1,5 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_sources(app PRIVATE src/usbc_console_pd.c)
diff --git a/zephyr/test/drivers/usbc_console_pd/src/usbc_console_pd.c b/zephyr/test/drivers/usbc_console_pd/src/usbc_console_pd.c
new file mode 100644
index 0000000000..3e876052f9
--- /dev/null
+++ b/zephyr/test/drivers/usbc_console_pd/src/usbc_console_pd.c
@@ -0,0 +1,167 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "ec_commands.h"
+#include "ec_tasks.h"
+#include "emul/emul_isl923x.h"
+#include "emul/tcpc/emul_tcpci.h"
+#include "emul/tcpc/emul_tcpci_partner_common.h"
+#include "emul/tcpc/emul_tcpci_partner_drp.h"
+#include "emul/tcpc/emul_tcpci_partner_src.h"
+#include "host_command.h"
+#include "tcpm/tcpci.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "usb_pd.h"
+
+#include <stdint.h>
+
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/kernel.h>
+#include <zephyr/shell/shell_dummy.h>
+#include <zephyr/ztest.h>
+
+#define TEST_PORT 0
+
+struct common_fixture {
+	const struct emul *tcpci_emul;
+	const struct emul *charger_emul;
+	struct tcpci_partner_data partner;
+	struct tcpci_snk_emul_data snk_ext;
+	struct tcpci_src_emul_data src_ext;
+	struct tcpci_drp_emul_data drp_ext;
+};
+
+struct usbc_console_pd_fixture {
+	struct common_fixture common;
+};
+
+static void connect_partner_to_port(const struct emul *tcpc_emul,
+				    const struct emul *charger_emul,
+				    struct tcpci_partner_data *partner_emul,
+				    const struct tcpci_src_emul_data *src_ext)
+{
+	/*
+	 * TODO(b/221439302): Updating the TCPCI emulator registers, updating
+	 * the charger, and alerting should all be a part of the connect
+	 * function.
+	 */
+	set_ac_enabled(true);
+	zassert_ok(tcpci_partner_connect_to_tcpci(partner_emul, tcpc_emul),
+		   NULL);
+
+	isl923x_emul_set_adc_vbus(charger_emul,
+				  PDO_FIXED_GET_VOLT(src_ext->pdo[0]));
+
+	/* Wait for PD negotiation and current ramp. */
+	k_sleep(K_SECONDS(10));
+}
+
+static void disconnect_partner_from_port(const struct emul *tcpc_emul,
+					 const struct emul *charger_emul)
+{
+	zassert_ok(tcpci_emul_disconnect_partner(tcpc_emul), NULL);
+	isl923x_emul_set_adc_vbus(charger_emul, 0);
+	k_sleep(K_SECONDS(1));
+}
+
+static void *common_setup(void)
+{
+	static struct usbc_console_pd_fixture outer_fixture;
+	struct common_fixture *fixture = &outer_fixture.common;
+	struct tcpci_partner_data *partner = &fixture->partner;
+	struct tcpci_src_emul_data *src_ext = &fixture->src_ext;
+	struct tcpci_snk_emul_data *snk_ext = &fixture->snk_ext;
+
+	tcpci_partner_init(partner, PD_REV30);
+	fixture->partner.extensions = tcpci_drp_emul_init(
+		&fixture->drp_ext, partner, PD_ROLE_SOURCE,
+		tcpci_src_emul_init(src_ext, partner, NULL),
+		tcpci_snk_emul_init(snk_ext, partner, NULL));
+
+	/* Get references for the emulators */
+	fixture->tcpci_emul = EMUL_GET_USBC_BINDING(TEST_PORT, tcpc);
+	fixture->charger_emul = EMUL_GET_USBC_BINDING(TEST_PORT, chg);
+
+	return &outer_fixture;
+}
+
+static void *usbc_console_pd_setup(void)
+{
+	return common_setup();
+}
+
+static void common_before(struct common_fixture *fixture)
+{
+	/* Set chipset to ON, this will set TCPM to DRP */
+	test_set_chipset_to_s0();
+
+	/* TODO(b/214401892): Check why need to give time TCPM to spin */
+	k_sleep(K_SECONDS(1));
+}
+
+static void usbc_console_pd_before(void *data)
+{
+	struct usbc_console_pd_fixture *outer = data;
+
+	common_before(&outer->common);
+}
+
+static void common_after(struct common_fixture *fixture)
+{
+	disconnect_partner_from_port(fixture->tcpci_emul,
+				     fixture->charger_emul);
+}
+
+static void usbc_console_pd_after(void *data)
+{
+	struct usbc_console_pd_fixture *outer = data;
+
+	common_after(&outer->common);
+}
+
+ZTEST_USER_F(usbc_console_pd, test_pd_command)
+{
+	struct common_fixture *common = &fixture->common;
+	struct tcpci_src_emul_data *src_ext = &common->src_ext;
+	uint32_t *partner_pdo = src_ext->pdo;
+	int rv;
+	const char *cmd_output = NULL;
+	size_t output_size = 0;
+
+	/* Attach a partner with all of the Source Capability attributes that
+	 * "pd <port> srccaps" checks for.
+	 */
+	partner_pdo[0] =
+		PDO_FIXED(5000, 3000,
+			  PDO_FIXED_DUAL_ROLE | PDO_FIXED_UNCONSTRAINED |
+				  PDO_FIXED_COMM_CAP | PDO_FIXED_DATA_SWAP |
+				  PDO_FIXED_FRS_CURR_MASK);
+	partner_pdo[1] = PDO_BATT(1000, 5000, 15000);
+	partner_pdo[2] = PDO_VAR(3000, 5000, 15000);
+	partner_pdo[3] = PDO_AUG(1000, 5000, 3000);
+	connect_partner_to_port(common->tcpci_emul, common->charger_emul,
+				&common->partner, &common->src_ext);
+
+	shell_backend_dummy_clear_output(get_ec_shell());
+	rv = shell_execute_cmd(get_ec_shell(), "pd 0 srccaps");
+	cmd_output =
+		shell_backend_dummy_get_output(get_ec_shell(), &output_size);
+
+	zassert_ok(rv);
+	/* This output validation is intentionally fairly loose to keep it from
+	 * being overly sensitive to formatting.
+	 */
+	zassert_not_null(strstr(cmd_output, "Fixed"));
+	zassert_not_null(strstr(cmd_output, "Battery"));
+	zassert_not_null(strstr(cmd_output, "Variable"));
+	zassert_not_null(strstr(cmd_output, "Augmnt"));
+	zassert_not_null(strstr(cmd_output, "DRP UP USB DRD FRS"));
+}
+
+ZTEST_SUITE(usbc_console_pd, drivers_predicate_post_main, usbc_console_pd_setup,
+	    usbc_console_pd_before, usbc_console_pd_after, NULL);
diff --git a/zephyr/test/drivers/usbc_console_pd/usbc_legacy.dts b/zephyr/test/drivers/usbc_console_pd/usbc_legacy.dts
new file mode 100644
index 0000000000..c07f379f77
--- /dev/null
+++ b/zephyr/test/drivers/usbc_console_pd/usbc_legacy.dts
@@ -0,0 +1,25 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+&{/gpio-interrupts} {
+	int_usb_c0: usb_c0 {
+		irq-pin = <&usb_c0_tcpc_int_odl>;
+		flags = <GPIO_INT_EDGE_FALLING>;
+		handler = "tcpc_alert_event";
+	};
+	int_usb_c1: usb_c1 {
+		irq-pin = <&usb_c1_tcpc_int_odl>;
+		flags = <GPIO_INT_EDGE_FALLING>;
+		handler = "tcpc_alert_event";
+	};
+};
+
+&tcpci_emul {
+	int-pin = <&usb_c0_tcpc_int_odl>;
+};
+
+&ps8xxx_emul {
+	int-pin = <&usb_c1_tcpc_int_odl>;
+};
diff --git a/zephyr/test/drivers/usbc_ctvpd/CMakeLists.txt b/zephyr/test/drivers/usbc_ctvpd/CMakeLists.txt
new file mode 100644
index 0000000000..36f88dfcbb
--- /dev/null
+++ b/zephyr/test/drivers/usbc_ctvpd/CMakeLists.txt
@@ -0,0 +1,7 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_include_directories(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/include)
+
+target_sources(app PRIVATE src/main.c)
diff --git a/zephyr/test/drivers/usbc_ctvpd/include/test_usbc_ctvpd.h b/zephyr/test/drivers/usbc_ctvpd/include/test_usbc_ctvpd.h
new file mode 100644
index 0000000000..9ebb740da8
--- /dev/null
+++ b/zephyr/test/drivers/usbc_ctvpd/include/test_usbc_ctvpd.h
@@ -0,0 +1,29 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef ZEPHYR_TEST_DRIVERS_USBC_ALT_MODE_TEST_USBC_ALT_MODE_H_
+#define ZEPHYR_TEST_DRIVERS_USBC_ALT_MODE_TEST_USBC_ALT_MODE_H_
+
+#include "compile_time_macros.h"
+#include "emul/tcpc/emul_tcpci.h"
+#include "emul/tcpc/emul_tcpci_partner_snk.h"
+#include "emul/tcpc/emul_tcpci_partner_src.h"
+#include "emul/tcpc/emul_tcpci_partner_vpd.h"
+#include "test/drivers/stubs.h"
+
+struct common_fixture {
+	const struct emul *tcpci_emul;
+	const struct emul *charger_emul;
+	struct tcpci_partner_data partner;
+	struct tcpci_src_emul_data src_ext;
+	struct tcpci_snk_emul_data snk_ext;
+	struct tcpci_vpd_emul_data vpd_ext;
+};
+
+struct usbc_ctvpd_fixture {
+	struct common_fixture common;
+};
+
+#endif /* ZEPHYR_TEST_DRIVERS_USBC_ALT_MODE_TEST_USBC_ALT_MODE_H_ */
diff --git a/zephyr/test/drivers/usbc_ctvpd/src/main.c b/zephyr/test/drivers/usbc_ctvpd/src/main.c
new file mode 100644
index 0000000000..909a52daa9
--- /dev/null
+++ b/zephyr/test/drivers/usbc_ctvpd/src/main.c
@@ -0,0 +1,169 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+#include "ec_tasks.h"
+#include "emul/emul_isl923x.h"
+#include "emul/tcpc/emul_tcpci.h"
+#include "emul/tcpc/emul_tcpci_partner_common.h"
+#include "emul/tcpc/emul_tcpci_partner_snk.h"
+#include "emul/tcpc/emul_tcpci_partner_src.h"
+#include "host_command.h"
+#include "tcpm/tcpci.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "test_usbc_ctvpd.h"
+#include "usb_pd_vdo.h"
+
+#include <stdint.h>
+
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+#define TEST_PORT 0
+BUILD_ASSERT(TEST_PORT == USBC_PORT_C0);
+
+struct tcpci_cable_data charge_through_vpd = {
+	.identity_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_PD, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_IDENT),
+	.identity_vdm[VDO_INDEX_IDH] = VDO_IDH(
+		/* USB host */ false, /* USB device */ false, IDH_PTYPE_VPD,
+		/* modal operation */ false, USB_VID_GOOGLE),
+	.identity_vdm[VDO_INDEX_CSTAT] = 0xabcdabcd,
+	.identity_vdm[VDO_INDEX_PRODUCT] = VDO_PRODUCT(0x1234, 0xabcd),
+	/* Hardware version 1, firmware version 2 */
+	.identity_vdm[VDO_INDEX_PTYPE_UFP1_VDO] =
+		VDO_VPD(1, 2, VPD_MAX_VBUS_20V, VPD_CT_CURRENT_3A,
+			VPD_VBUS_IMP(10), VPD_GND_IMP(10), VPD_CTS_SUPPORTED),
+	.identity_vdos = VDO_INDEX_PTYPE_UFP1_VDO + 1,
+};
+
+static void disconnect_partner_from_port(const struct emul *tcpc_emul,
+					 const struct emul *charger_emul)
+{
+	zassert_ok(tcpci_emul_disconnect_partner(tcpc_emul));
+	isl923x_emul_set_adc_vbus(charger_emul, 0);
+	k_sleep(K_SECONDS(1));
+}
+
+static void add_discovery_responses(struct tcpci_partner_data *partner)
+{
+	partner->cable = &charge_through_vpd;
+	struct tcpci_cable_data *cable = partner->cable;
+
+	/* Add Discover Identity response */
+	cable->identity_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_PD, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_IDENT);
+	cable->identity_vdm[VDO_INDEX_IDH] = VDO_IDH(
+		/* USB host */ false, /* USB device */ false, IDH_PTYPE_VPD,
+		/* modal operation */ false, USB_VID_GOOGLE);
+	cable->identity_vdm[VDO_INDEX_CSTAT] = 0xabcdabcd;
+	cable->identity_vdm[VDO_INDEX_PRODUCT] = VDO_PRODUCT(0x1234, 0x5678);
+	/* Hardware version 1, firmware version 2 */
+	cable->identity_vdm[VDO_INDEX_PTYPE_UFP1_VDO] =
+		VDO_VPD(1, 2, VPD_MAX_VBUS_20V, VPD_CT_CURRENT_3A,
+			VPD_VBUS_IMP(10), VPD_GND_IMP(10), VPD_CTS_SUPPORTED);
+	cable->identity_vdos = VDO_INDEX_PTYPE_UFP1_VDO + 1;
+}
+
+static void common_before(struct common_fixture *common)
+{
+	/* Set chipset to ON, this will set TCPM to DRP */
+	test_set_chipset_to_s0();
+
+	/* TODO(b/214401892): Check why need to give time TCPM to spin */
+	k_sleep(K_SECONDS(1));
+
+	connect_sink_to_port(&common->partner, common->tcpci_emul,
+			     common->charger_emul);
+}
+
+static void common_after(struct common_fixture *common)
+{
+	disconnect_partner_from_port(common->tcpci_emul, common->charger_emul);
+}
+
+static void *usbc_ctvpd_setup(void)
+{
+	static struct usbc_ctvpd_fixture fixture;
+	struct common_fixture *common = &fixture.common;
+	struct tcpci_partner_data *partner = &common->partner;
+	struct tcpci_vpd_emul_data *vpd_ext = &common->vpd_ext;
+
+	tcpci_partner_init(partner, PD_REV30);
+	partner->extensions = tcpci_vpd_emul_init(vpd_ext, partner, NULL);
+
+	/* Get references for the emulators */
+	common->tcpci_emul = EMUL_GET_USBC_BINDING(TEST_PORT, tcpc);
+	common->charger_emul = EMUL_GET_USBC_BINDING(TEST_PORT, chg);
+
+	add_discovery_responses(partner);
+
+	return &fixture;
+}
+
+static void usbc_ctvpd_before(void *data)
+{
+	struct usbc_ctvpd_fixture *fixture = data;
+
+	common_before(&fixture->common);
+}
+
+static void usbc_ctvpd_after(void *data)
+{
+	struct usbc_ctvpd_fixture *fixture = data;
+
+	common_after(&fixture->common);
+}
+
+ZTEST_SUITE(usbc_ctvpd, drivers_predicate_post_main, usbc_ctvpd_setup,
+	    usbc_ctvpd_before, usbc_ctvpd_after, NULL);
+
+ZTEST_USER_F(usbc_ctvpd, test_verify_discovery)
+{
+	uint8_t response_buffer[EC_LPC_HOST_PACKET_SIZE];
+	struct ec_response_typec_discovery *discovery =
+		(struct ec_response_typec_discovery *)response_buffer;
+	struct common_fixture *common = &fixture->common;
+
+	host_cmd_typec_discovery(TEST_PORT, TYPEC_PARTNER_SOP_PRIME,
+				 response_buffer, sizeof(response_buffer));
+
+	/* The host command does not count the VDM header in identity_count. */
+	zassert_equal(discovery->identity_count,
+		      common->partner.cable->identity_vdos - 1,
+		      "Expected %d identity VDOs, got %d",
+		      common->partner.cable->identity_vdos - 1,
+		      discovery->identity_count);
+	zassert_mem_equal(discovery->discovery_vdo,
+			  common->partner.cable->identity_vdm + 1,
+			  discovery->identity_count *
+				  sizeof(*discovery->discovery_vdo),
+			  "Discovered SOP identity ACK did not match");
+}
+
+ZTEST_USER_F(usbc_ctvpd, test_verify_no_vconn_swap)
+{
+	struct ec_response_typec_status status =
+		host_cmd_typec_status(TEST_PORT);
+	enum pd_vconn_role initial_vconn_role = status.vconn_role;
+
+	/* Upon initial attachment to the host port of a CT-VPD, the host (TCPM)
+	 * should be Source and thus VCONN Source. After entry into
+	 * CTAttached.SNK, the host should remain VCONN Source.
+	 */
+	zassert_equal(initial_vconn_role, PD_ROLE_VCONN_SRC);
+
+	/* The TCPM should refuse to VCONN Swap while in CTAttached.SNK. */
+	zassert_ok(tcpci_partner_send_control_msg(&fixture->common.partner,
+						  PD_CTRL_VCONN_SWAP, 0));
+	k_sleep(K_SECONDS(1));
+	status = host_cmd_typec_status(TEST_PORT);
+	zassert_equal(status.vconn_role, initial_vconn_role);
+}
diff --git a/zephyr/test/drivers/usbc_frs/CMakeLists.txt b/zephyr/test/drivers/usbc_frs/CMakeLists.txt
new file mode 100644
index 0000000000..36f88dfcbb
--- /dev/null
+++ b/zephyr/test/drivers/usbc_frs/CMakeLists.txt
@@ -0,0 +1,7 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_include_directories(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/include)
+
+target_sources(app PRIVATE src/main.c)
diff --git a/zephyr/test/drivers/usbc_frs/src/main.c b/zephyr/test/drivers/usbc_frs/src/main.c
new file mode 100644
index 0000000000..67fc6a1a8d
--- /dev/null
+++ b/zephyr/test/drivers/usbc_frs/src/main.c
@@ -0,0 +1,116 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+#include "ec_tasks.h"
+#include "emul/emul_isl923x.h"
+#include "emul/tcpc/emul_tcpci.h"
+#include "emul/tcpc/emul_tcpci_partner_common.h"
+#include "emul/tcpc/emul_tcpci_partner_drp.h"
+#include "emul/tcpc/emul_tcpci_partner_snk.h"
+#include "emul/tcpc/emul_tcpci_partner_src.h"
+#include "host_command.h"
+#include "tcpm/tcpci.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "usb_pd_vdo.h"
+
+#include <stdint.h>
+
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+struct common_fixture {
+	const struct emul *tcpci_emul;
+	const struct emul *charger_emul;
+	struct tcpci_partner_data partner;
+	struct tcpci_src_emul_data src_ext;
+	struct tcpci_snk_emul_data snk_ext;
+	struct tcpci_drp_emul_data drp_ext;
+};
+
+struct usbc_frs_fixture {
+	struct common_fixture common;
+};
+
+#define TEST_PORT 0
+BUILD_ASSERT(TEST_PORT == USBC_PORT_C0);
+
+static void disconnect_partner_from_port(const struct emul *tcpc_emul,
+					 const struct emul *charger_emul)
+{
+	zassert_ok(tcpci_emul_disconnect_partner(tcpc_emul));
+	isl923x_emul_set_adc_vbus(charger_emul, 0);
+	k_sleep(K_SECONDS(1));
+}
+
+static void common_before(struct common_fixture *common)
+{
+	/* Set chipset to ON, this will set TCPM to DRP */
+	test_set_chipset_to_s0();
+
+	/* TODO(b/214401892): Check why need to give time TCPM to spin */
+	k_sleep(K_SECONDS(1));
+
+	connect_sink_to_port(&common->partner, common->tcpci_emul,
+			     common->charger_emul);
+}
+
+static void common_after(struct common_fixture *common)
+{
+	disconnect_partner_from_port(common->tcpci_emul, common->charger_emul);
+}
+
+static void *usbc_frs_setup(void)
+{
+	static struct usbc_frs_fixture fixture;
+	struct common_fixture *common = &fixture.common;
+	struct tcpci_partner_data *partner = &common->partner;
+	struct tcpci_drp_emul_data *drp_ext = &common->drp_ext;
+
+	tcpci_partner_init(partner, PD_REV30);
+	partner->extensions = tcpci_drp_emul_init(
+		drp_ext, partner, PD_ROLE_SOURCE,
+		tcpci_src_emul_init(&common->src_ext, partner, NULL),
+		tcpci_snk_emul_init(&common->snk_ext, partner, NULL));
+	/* Configure the partner to support FRS as initial source. */
+	common->snk_ext.pdo[0] |= PDO_FIXED_FRS_CURR_DFLT_USB_POWER;
+
+	/* Get references for the emulators */
+	common->tcpci_emul = EMUL_GET_USBC_BINDING(TEST_PORT, tcpc);
+	common->charger_emul = EMUL_GET_USBC_BINDING(TEST_PORT, chg);
+
+	return &fixture;
+}
+
+static void usbc_frs_before(void *data)
+{
+	struct usbc_frs_fixture *fixture = data;
+
+	common_before(&fixture->common);
+}
+
+static void usbc_frs_after(void *data)
+{
+	struct usbc_frs_fixture *fixture = data;
+
+	common_after(&fixture->common);
+}
+
+ZTEST_SUITE(usbc_frs, drivers_predicate_post_main, usbc_frs_setup,
+	    usbc_frs_before, usbc_frs_after, NULL);
+
+ZTEST_USER_F(usbc_frs, test_frs_enable)
+{
+	struct common_fixture *common = &fixture->common;
+	uint16_t power_control;
+
+	zassert_ok(tcpci_emul_get_reg(common->tcpci_emul, TCPC_REG_POWER_CTRL,
+				      &power_control));
+	zassert_equal(power_control & TCPC_REG_POWER_CTRL_FRS_ENABLE,
+		      TCPC_REG_POWER_CTRL_FRS_ENABLE);
+}
diff --git a/zephyr/test/drivers/usbc_ocp/CMakeLists.txt b/zephyr/test/drivers/usbc_ocp/CMakeLists.txt
new file mode 100644
index 0000000000..8453bed73c
--- /dev/null
+++ b/zephyr/test/drivers/usbc_ocp/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Add source files
+target_sources(app PRIVATE src/usbc_ocp.c)
diff --git a/zephyr/test/drivers/usbc_ocp/src/usbc_ocp.c b/zephyr/test/drivers/usbc_ocp/src/usbc_ocp.c
new file mode 100644
index 0000000000..a7828eb878
--- /dev/null
+++ b/zephyr/test/drivers/usbc_ocp/src/usbc_ocp.c
@@ -0,0 +1,64 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "test/drivers/test_state.h"
+#include "timer.h"
+#include "usbc_ocp.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+#include <zephyr/ztest_assert.h>
+
+/* Tests for USBC OCP (Overcurrent Protection) Common Code */
+
+#define TEST_PORT 0
+
+/* Returns non-zero if state never reached */
+static int wait_for_port_latched_off_state(bool state)
+{
+	WAIT_FOR(state == usbc_ocp_is_port_latched_off(TEST_PORT),
+		 5000000, /* 5 Second */
+		 k_sleep(K_MSEC(1)));
+
+	return !(state == usbc_ocp_is_port_latched_off(TEST_PORT));
+}
+
+static void usbc_ocpc_suite_before_after(void *data)
+{
+	ARG_UNUSED(data);
+
+	usbc_ocp_clear_event_counter(TEST_PORT);
+	zassert_ok(wait_for_port_latched_off_state(false));
+}
+
+ZTEST(usbc_ocp, test_events_add_then_clear)
+{
+	for (int i = 0; i < OCP_MAX_CNT - 1; i++) {
+		zassert_ok(usbc_ocp_add_event(TEST_PORT),
+			   "Could not add ocp event %d", i);
+
+		zassert_ok(wait_for_port_latched_off_state(false),
+			   "Max OC events too soon");
+	}
+
+	zassert_ok(usbc_ocp_add_event(TEST_PORT));
+	zassert_ok(wait_for_port_latched_off_state(true),
+		   "Max OC events too soon");
+
+	zassert_ok(usbc_ocp_clear_event_counter(TEST_PORT));
+	zassert_ok(wait_for_port_latched_off_state(false),
+		   "Max OC events too soon");
+}
+
+ZTEST(usbc_ocp, test_bad_port_arguments)
+{
+	zassert_ok(usbc_ocp_is_port_latched_off(-1));
+
+	zassert_equal(EC_ERROR_INVAL, usbc_ocp_clear_event_counter(-1));
+	zassert_equal(EC_ERROR_INVAL, usbc_ocp_add_event(-1));
+}
+
+ZTEST_SUITE(usbc_ocp, drivers_predicate_post_main, NULL,
+	    usbc_ocpc_suite_before_after, usbc_ocpc_suite_before_after, NULL);
diff --git a/zephyr/test/drivers/usbc_ppc/CMakeLists.txt b/zephyr/test/drivers/usbc_ppc/CMakeLists.txt
new file mode 100644
index 0000000000..47102a0628
--- /dev/null
+++ b/zephyr/test/drivers/usbc_ppc/CMakeLists.txt
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Add source files
+target_sources(app PRIVATE
+  src/usbc_ppc.c
+  src/ppc_shim.c
+)
\ No newline at end of file
diff --git a/zephyr/test/drivers/usbc_ppc/ppc_alts.dts b/zephyr/test/drivers/usbc_ppc/ppc_alts.dts
new file mode 100644
index 0000000000..ed84ff0662
--- /dev/null
+++ b/zephyr/test/drivers/usbc_ppc/ppc_alts.dts
@@ -0,0 +1,48 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+ /* Defint nodes with the "is-alt" property set. Used by the PPC shim
+  * test to validate the runtime replacement of the PPC driver.
+  */
+
+/ {
+	ppc_aoz1380_alt: ppc-aoz1380-alt{
+		compatible = "aoz,aoz1380";
+		status = "okay";
+		is-alt;
+	};
+};
+
+&i2c0 {
+	ppc_nx20p348x_alt: nx20p348x@77 {
+		compatible = "nxp,nx20p348x";
+		status = "okay";
+		reg = <0x77>;
+		irq-gpios = < &gpio0 14 GPIO_ACTIVE_LOW >;
+		is-alt;
+	};
+
+	ppc_rt1739_alt: rt1739@70 {
+		compatible = "richtek,rt1739-ppc", "cros,i2c-mock";
+		status = "okay";
+		reg = <0x70>;
+		is-alt;
+	};
+
+	ppc_syv682x_alt: syv682x@43 {
+		compatible = "silergy,syv682x", "cros,i2c-mock";
+		status = "okay";
+		reg = <0x43>;
+		frs_en_gpio = <&gpio_usb_c1_frs_en>;
+		is-alt;
+	};
+
+	ppc_sn5s330_alt: sn5s330@49 {
+		compatible = "ti,sn5s330", "cros,i2c-mock";
+		status = "okay";
+		reg = <0x49>;
+		is-alt;
+	};
+};
diff --git a/zephyr/test/drivers/usbc_ppc/src/ppc_shim.c b/zephyr/test/drivers/usbc_ppc/src/ppc_shim.c
new file mode 100644
index 0000000000..9625a783f9
--- /dev/null
+++ b/zephyr/test/drivers/usbc_ppc/src/ppc_shim.c
@@ -0,0 +1,60 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "usbc/ppc.h"
+
+#include <zephyr/logging/log.h>
+#include <zephyr/ztest.h>
+
+LOG_MODULE_REGISTER(test_drivers_ppc, LOG_LEVEL_DBG);
+
+#define PPC_CHIP_STUB(node_id) {},
+
+static struct ppc_config_t ppc_chips_saved[] = { DT_FOREACH_STATUS_OKAY(
+	named_usbc_port, PPC_CHIP_STUB) };
+
+ZTEST(ppc_shim, test_ppc_alts_exist)
+{
+	/* Verify all PPC types are able to create an alternate PPC entry */
+	zassert_not_null(&PPC_ALT_FROM_NODELABEL(ppc_aoz1380_alt));
+	zassert_not_null(&PPC_ALT_FROM_NODELABEL(ppc_nx20p348x_alt));
+	zassert_not_null(&PPC_ALT_FROM_NODELABEL(ppc_rt1739_alt));
+	zassert_not_null(&PPC_ALT_FROM_NODELABEL(ppc_syv682x_alt));
+	zassert_not_null(&PPC_ALT_FROM_NODELABEL(ppc_sn5s330_alt));
+}
+
+ZTEST(ppc_shim, test_ppc_alt_enable)
+{
+	/* Enable an alternate PPC on each USB-C port */
+	PPC_ENABLE_ALTERNATE_BY_NODELABEL(0, ppc_syv682x_alt);
+	PPC_ENABLE_ALTERNATE_BY_NODELABEL(1, ppc_rt1739_alt);
+
+	zassert_mem_equal(&ppc_chips[0],
+			  &PPC_ALT_FROM_NODELABEL(ppc_syv682x_alt),
+			  sizeof(struct ppc_config_t));
+	zassert_mem_equal(&ppc_chips[1],
+			  &PPC_ALT_FROM_NODELABEL(ppc_rt1739_alt),
+			  sizeof(struct ppc_config_t));
+
+	PPC_ENABLE_ALTERNATE_BY_NODELABEL(0, ppc_nx20p348x_alt);
+	zassert_mem_equal(&ppc_chips[0],
+			  &PPC_ALT_FROM_NODELABEL(ppc_nx20p348x_alt),
+			  sizeof(struct ppc_config_t));
+}
+
+void ppc_shim_before_test(void *data)
+{
+	memcpy(ppc_chips_saved, ppc_chips,
+	       sizeof(struct ppc_config_t) * ARRAY_SIZE(ppc_chips_saved));
+}
+
+void ppc_shim_after_test(void *data)
+{
+	memcpy(ppc_chips, ppc_chips_saved,
+	       sizeof(struct ppc_config_t) * ARRAY_SIZE(ppc_chips_saved));
+}
+
+ZTEST_SUITE(ppc_shim, NULL, NULL, ppc_shim_before_test, ppc_shim_after_test,
+	    NULL);
diff --git a/zephyr/test/drivers/usbc_ppc/src/usbc_ppc.c b/zephyr/test/drivers/usbc_ppc/src/usbc_ppc.c
new file mode 100644
index 0000000000..c0cd438511
--- /dev/null
+++ b/zephyr/test/drivers/usbc_ppc/src/usbc_ppc.c
@@ -0,0 +1,121 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "test/drivers/test_state.h"
+#include "timer.h"
+#include "usbc_ppc.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/shell/shell_dummy.h>
+#include <zephyr/ztest.h>
+#include <zephyr/ztest_assert.h>
+
+/* Tests for USBC PPC Common Code */
+
+ZTEST(usbc_ppc, test_ppc_dump__no_args)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+
+	/* There's no output from the cmd given < 2 args */
+	zassert_equal(shell_execute_cmd(shell_zephyr, "ppc_dump"),
+		      EC_ERROR_PARAM_COUNT);
+}
+
+ZTEST(usbc_ppc, test_ppc_dump__bad_args)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+	const char *outbuffer;
+	size_t buffer_size;
+
+	shell_backend_dummy_clear_output(shell_zephyr);
+
+	zassert_equal(shell_execute_cmd(shell_zephyr, "ppc_dump -1"),
+		      EC_ERROR_INVAL);
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+
+	zassert_true(buffer_size > 0);
+	zassert_not_null(strstr(outbuffer, "Invalid port!"));
+}
+
+ZTEST(usbc_ppc, test_ppc_dump__good_args)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+	const char *outbuffer;
+	size_t buffer_size;
+
+	shell_backend_dummy_clear_output(shell_zephyr);
+
+	zassert_ok(shell_execute_cmd(shell_zephyr, "ppc_dump 0"));
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+
+	zassert_true(buffer_size > 0);
+
+	/* Weakly verify something reasonable was output to console */
+	zassert_not_null(strstr(outbuffer, " = 0x"));
+}
+
+ZTEST(usbc_ppc, test_ppc_init__bad_args)
+{
+	zassert_equal(ppc_init(-1), EC_ERROR_INVAL);
+}
+
+ZTEST(usbc_ppc, test_ppc_is_sourcing_vbus__bad_args)
+{
+	zassert_false(ppc_is_sourcing_vbus(-1));
+}
+
+ZTEST(usbc_ppc, test_ppc_set_polarity__bad_args)
+{
+	zassert_equal(ppc_set_polarity(-1, -1), EC_ERROR_INVAL);
+}
+
+ZTEST(usbc_ppc, test_ppc_set_vbus_source_current_limit__bad_args)
+{
+	zassert_equal(ppc_set_vbus_source_current_limit(-1, -1),
+		      EC_ERROR_INVAL);
+}
+
+ZTEST(usbc_ppc, test_ppc_discharge_vbus__bad_args)
+{
+	zassert_equal(ppc_discharge_vbus(-1, -1), EC_ERROR_INVAL);
+}
+
+ZTEST(usbc_ppc, test_ppc_set_sbu__bad_args)
+{
+	zassert_equal(ppc_set_sbu(-1, -1), EC_ERROR_INVAL);
+}
+
+ZTEST(usbc_ppc, test_ppc_set_vconn__bad_args)
+{
+	zassert_equal(ppc_set_vconn(-1, -1), EC_ERROR_INVAL);
+}
+
+ZTEST(usbc_ppc, test_ppc_dev_is_connected__bad_args)
+{
+	zassert_equal(ppc_dev_is_connected(-1, -1), EC_ERROR_INVAL);
+}
+
+ZTEST(usbc_ppc, test_ppc_vbus_sink_enable__bad_args)
+{
+	zassert_equal(ppc_vbus_sink_enable(-1, -1), EC_ERROR_INVAL);
+}
+
+ZTEST(usbc_ppc, test_ppc_enter_low_power_mode__bad_args)
+{
+	zassert_equal(ppc_enter_low_power_mode(-1), EC_ERROR_INVAL);
+}
+
+ZTEST(usbc_ppc, test_ppc_vbus_source_enable__bad_args)
+{
+	zassert_equal(ppc_vbus_source_enable(-1, -1), EC_ERROR_INVAL);
+}
+
+ZTEST(usbc_ppc, test_ppc_set_frs_enable__bad_args)
+{
+	zassert_equal(ppc_set_frs_enable(-1, -1), EC_ERROR_INVAL);
+}
+
+ZTEST_SUITE(usbc_ppc, drivers_predicate_post_main, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/drivers/usbc_retimer/CMakeLists.txt b/zephyr/test/drivers/usbc_retimer/CMakeLists.txt
new file mode 100644
index 0000000000..5c3253328d
--- /dev/null
+++ b/zephyr/test/drivers/usbc_retimer/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_sources_ifdef(CONFIG_LINK_TEST_SUITE_USBC_RETIMER_ANX7483 app PRIVATE src/anx7483.c)
+target_sources_ifdef(CONFIG_LINK_TEST_SUITE_USBC_RETIMER_PS8811 app PRIVATE src/ps8811.c)
diff --git a/zephyr/test/drivers/usbc_retimer/i2c.dts b/zephyr/test/drivers/usbc_retimer/i2c.dts
new file mode 100644
index 0000000000..5bdf9b1696
--- /dev/null
+++ b/zephyr/test/drivers/usbc_retimer/i2c.dts
@@ -0,0 +1,46 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/usb_pd_tcpm.h>
+
+/ {
+	usbc {
+		port0@0 {
+			compatible = "named-usbc-port";
+			tcpc = <&ps8xxx_emul0>;
+		};
+		port1@1 {
+			compatible = "named-usbc-port";
+			tcpc = <&ps8xxx_emul1>;
+		};
+	};
+};
+
+&i2c2 {
+	status="okay";
+
+	ps8xxx_emul0: ps8xxx_emul@c {
+		compatible = "cros,ps8xxx-emul";
+		reg = <0xc>;
+		p0-i2c-addr = <0x10>;
+		p1-i2c-addr = <0x11>;
+		gpio-i2c-addr = <0x1b>;
+	};
+};
+
+&i2c3 {
+	status="okay";
+
+	/delete-node/ ps8xxx_emul@b;
+
+	ps8xxx_emul1: ps8xxx_emul@b {
+		compatible = "cros,ps8xxx-emul";
+		reg = <0xb>;
+		p0-i2c-addr = <0x8>;
+		p1-i2c-addr = <0x9>;
+		gpio-i2c-addr = <0x1a>;
+	};
+
+};
diff --git a/zephyr/test/drivers/usbc_retimer/prj.conf b/zephyr/test/drivers/usbc_retimer/prj.conf
new file mode 100644
index 0000000000..96bb372274
--- /dev/null
+++ b/zephyr/test/drivers/usbc_retimer/prj.conf
@@ -0,0 +1,3 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
diff --git a/zephyr/test/drivers/usbc_retimer/src/anx7483.c b/zephyr/test/drivers/usbc_retimer/src/anx7483.c
new file mode 100644
index 0000000000..1d0d034c14
--- /dev/null
+++ b/zephyr/test/drivers/usbc_retimer/src/anx7483.c
@@ -0,0 +1,1182 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/retimer/anx7483.h"
+#include "driver/retimer/anx7483_public.h"
+#include "emul/retimer/emul_anx7483.h"
+#include "i2c.h"
+#include "power.h"
+#include "usb_mux.h"
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/ztest.h>
+
+#define ANX7483_EMUL EMUL_DT_GET(DT_NODELABEL(anx7483_emul))
+
+int anx7483_init(const struct usb_mux *me);
+int anx7483_set(const struct usb_mux *me, mux_state_t mux_state,
+		bool *ack_required);
+int anx7483_get(const struct usb_mux *me, mux_state_t *mux_state);
+int anx7483_read(const struct usb_mux *me, uint8_t reg, int *val);
+int anx7483_write(const struct usb_mux *me, uint8_t reg, uint8_t val);
+
+extern const struct anx7483_tuning_set anx7483_usb_enabled[];
+extern const struct anx7483_tuning_set anx7483_dp_enabled[];
+extern const struct anx7483_tuning_set anx7483_dock_noflip[];
+extern const struct anx7483_tuning_set anx7483_dock_flip[];
+
+extern const size_t anx7483_usb_enabled_count;
+extern const size_t anx7483_dp_enabled_count;
+extern const size_t anx7483_dock_noflip_count;
+extern const size_t anx7483_dock_flip_count;
+
+static struct usb_mux mux = {
+	.i2c_port = I2C_PORT_NODELABEL(i2c3),
+	.i2c_addr_flags = 0x3e,
+};
+
+/* Helper functions to make tests clearer. */
+static int anx7483_emul_test_get_reg(int reg, uint8_t *val)
+{
+	return anx7483_emul_get_reg(ANX7483_EMUL, reg, val);
+}
+
+static int anx7483_emul_test_set_mask(int reg, uint8_t val, uint8_t def)
+{
+	return anx7483_emul_set_reg_reserved_mask(ANX7483_EMUL, reg, val, def);
+}
+
+static int anx7483_emul_test_set_reg(int reg, uint8_t val)
+{
+	return anx7483_emul_set_reg(ANX7483_EMUL, reg, val);
+}
+
+static int anx7483_emul_test_get_eq(enum anx7483_tune_pin pin,
+				    enum anx7483_eq_setting *eq)
+{
+	return anx7483_emul_get_eq(ANX7483_EMUL, pin, eq);
+}
+
+static int anx7483_test_set_eq(enum anx7483_tune_pin pin,
+			       enum anx7483_eq_setting eq)
+{
+	return anx7483_set_eq(&mux, pin, eq);
+}
+
+static int anx7483_i2c_read(int reg, int *data)
+{
+	return anx7483_read(&mux, reg, data);
+}
+
+static int anx7483_i2c_write(int reg, int data)
+{
+	return anx7483_write(&mux, reg, data);
+}
+
+static void anx7483_before(void *fixture)
+{
+	ARG_UNUSED(fixture);
+
+	/* Ensure the ANX7483 is on. */
+	power_set_state(POWER_S0);
+}
+
+ZTEST_SUITE(anx7483, NULL, NULL, anx7483_before, NULL, NULL);
+
+/* Verify that the reset values for all registers are correct. */
+ZTEST(anx7483, test_emul_reset)
+{
+	uint8_t val;
+	int rv;
+
+	rv = anx7483_emul_test_get_reg(ANX7483_LFPS_TIMER_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_LFPS_TIMER_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_ANALOG_STATUS_CTRL_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_ANALOG_STATUS_CTRL_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_ENABLE_EQ_FLAT_SWING_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_ENABLE_EQ_FLAT_SWING_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_AUX_SNOOPING_CTRL_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_AUX_SNOOPING_CTRL_REG_DEFAULT);
+
+	/* CFG0 */
+	rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG0_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_UTX1_PORT_CFG0_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG0_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_UTX2_PORT_CFG0_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG0_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_URX1_PORT_CFG0_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG0_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_URX2_PORT_CFG0_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG0_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_DRX1_PORT_CFG0_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG0_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_DRX2_PORT_CFG0_REG_DEFAULT);
+
+	/* CFG1 */
+	rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG1_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_UTX1_PORT_CFG1_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG1_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_UTX2_PORT_CFG1_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG1_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_URX1_PORT_CFG1_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG1_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_URX2_PORT_CFG1_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG1_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_DRX1_PORT_CFG1_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG1_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_DRX2_PORT_CFG1_REG_DEFAULT);
+
+	/* CFG2 */
+	rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG2_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_UTX1_PORT_CFG2_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG2_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_UTX2_PORT_CFG2_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG2_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_URX1_PORT_CFG2_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG2_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_URX2_PORT_CFG2_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG2_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_DRX1_PORT_CFG2_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG2_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_DRX2_PORT_CFG2_REG_DEFAULT);
+
+	/* CFG3 */
+	rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_UTX1_PORT_CFG3_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_UTX2_PORT_CFG3_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_URX1_PORT_CFG3_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_URX2_PORT_CFG3_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_DRX1_PORT_CFG3_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_DRX2_PORT_CFG3_REG_DEFAULT);
+
+	/* CFG4 */
+	rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_UTX1_PORT_CFG4_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_UTX2_PORT_CFG4_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_URX1_PORT_CFG4_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_URX2_PORT_CFG4_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_DRX1_PORT_CFG4_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_DRX2_PORT_CFG4_REG_DEFAULT);
+}
+
+/* Test the ANX7483 driver's initialization function. */
+ZTEST(anx7483, test_init)
+{
+	int rv;
+	uint8_t val;
+
+	rv = anx7483_init(&mux);
+	zexpect_ok(rv);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_ANALOG_STATUS_CTRL_REG, &val);
+	zexpect_ok(rv);
+	zexpect_true(val & ANX7483_CTRL_REG_EN);
+}
+
+/*
+ * Test the ANX7483 driver's anx7483_set_eq, function  which sets the
+ * equalization for a pin.
+ */
+
+ZTEST(anx7483, test_set_eq_func)
+{
+	int rv;
+	enum anx7483_eq_setting eq;
+
+	rv = anx7483_test_set_eq(ANX7483_PIN_UTX1, ANX7483_EQ_SETTING_12_5DB);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_get_eq(ANX7483_PIN_UTX1, &eq);
+	zexpect_ok(rv);
+	zexpect_equal(eq, ANX7483_EQ_SETTING_12_5DB);
+
+	rv = anx7483_test_set_eq(ANX7483_PIN_UTX2, ANX7483_EQ_SETTING_12_5DB);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_get_eq(ANX7483_PIN_UTX2, &eq);
+	zexpect_ok(rv);
+	zexpect_equal(eq, ANX7483_EQ_SETTING_12_5DB);
+
+	rv = anx7483_test_set_eq(ANX7483_PIN_URX1, ANX7483_EQ_SETTING_12_5DB);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_get_eq(ANX7483_PIN_URX1, &eq);
+	zexpect_ok(rv);
+	zexpect_equal(eq, ANX7483_EQ_SETTING_12_5DB);
+
+	rv = anx7483_test_set_eq(ANX7483_PIN_URX2, ANX7483_EQ_SETTING_12_5DB);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_get_eq(ANX7483_PIN_URX2, &eq);
+	zexpect_ok(rv);
+	zexpect_equal(eq, ANX7483_EQ_SETTING_12_5DB);
+
+	rv = anx7483_test_set_eq(ANX7483_PIN_DRX1, ANX7483_EQ_SETTING_12_5DB);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_get_eq(ANX7483_PIN_DRX1, &eq);
+	zexpect_ok(rv);
+	zexpect_equal(eq, ANX7483_EQ_SETTING_12_5DB);
+
+	rv = anx7483_test_set_eq(ANX7483_PIN_DRX2, ANX7483_EQ_SETTING_12_5DB);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_get_eq(ANX7483_PIN_DRX2, &eq);
+	zexpect_ok(rv);
+	zexpect_equal(eq, ANX7483_EQ_SETTING_12_5DB);
+
+	/* Test invalid pin. */
+	rv = anx7483_test_set_eq(0xff, ANX7483_EQ_SETTING_12_5DB);
+	zexpect_not_equal(rv, 0);
+}
+
+/*
+ * Test the ANX7483 driver's anx7483_set_fg, function  which sets the flat gain
+ * for a pin.
+ */
+ZTEST(anx7483, test_set_fg)
+{
+	int rv;
+	uint8_t val;
+
+	rv = anx7483_set_fg(&mux, ANX7483_PIN_UTX1, ANX7483_FG_SETTING_1_2DB);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG2_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal((val >> ANX7483_CFG2_FG_SHIFT) & 0x3,
+		      ANX7483_FG_SETTING_1_2DB);
+
+	rv = anx7483_set_fg(&mux, ANX7483_PIN_UTX2, ANX7483_FG_SETTING_1_2DB);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG2_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal((val >> ANX7483_CFG2_FG_SHIFT) & 0x3,
+		      ANX7483_FG_SETTING_1_2DB);
+
+	rv = anx7483_set_fg(&mux, ANX7483_PIN_URX1, ANX7483_FG_SETTING_1_2DB);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG2_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal((val >> ANX7483_CFG2_FG_SHIFT) & 0x3,
+		      ANX7483_FG_SETTING_1_2DB);
+
+	rv = anx7483_set_fg(&mux, ANX7483_PIN_URX2, ANX7483_FG_SETTING_1_2DB);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG2_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal((val >> ANX7483_CFG2_FG_SHIFT) & 0x3,
+		      ANX7483_FG_SETTING_1_2DB);
+
+	rv = anx7483_set_fg(&mux, ANX7483_PIN_DRX1, ANX7483_FG_SETTING_1_2DB);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG2_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal((val >> ANX7483_CFG2_FG_SHIFT) & 0x3,
+		      ANX7483_FG_SETTING_1_2DB);
+
+	rv = anx7483_set_fg(&mux, ANX7483_PIN_DRX2, ANX7483_FG_SETTING_1_2DB);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG2_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal((val >> ANX7483_CFG2_FG_SHIFT) & 0x3,
+		      ANX7483_FG_SETTING_1_2DB);
+
+	/* Test invalid pin. */
+	rv = anx7483_set_fg(&mux, 0xff, ANX7483_FG_SETTING_1_2DB);
+	zexpect_not_equal(rv, 0);
+}
+
+/* Validate that accessing the emulator's registers through I2C works. */
+ZTEST(anx7483, test_emul_registers_rw)
+{
+	int rv;
+	uint8_t expected;
+	int val;
+
+	expected = (uint8_t)(ANX7483_LFPS_TIMER_REG_RESERVED_MASK &
+			     ANX7483_LFPS_TIMER_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_LFPS_TIMER_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_LFPS_TIMER_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_LFPS_TIMER_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = (uint8_t)(ANX7483_ANALOG_STATUS_CTRL_REG_RESERVED_MASK &
+			     ANX7483_ANALOG_STATUS_CTRL_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_ANALOG_STATUS_CTRL_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_ANALOG_STATUS_CTRL_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_ANALOG_STATUS_CTRL_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = (uint8_t)(ANX7483_ENABLE_EQ_FLAT_SWING_REG_RESERVED_MASK &
+			     ANX7483_ENABLE_EQ_FLAT_SWING_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_ENABLE_EQ_FLAT_SWING_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_ENABLE_EQ_FLAT_SWING_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_ENABLE_EQ_FLAT_SWING_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = (uint8_t)(ANX7483_AUX_SNOOPING_CTRL_REG_RESERVED_MASK &
+			     ANX7483_AUX_SNOOPING_CTRL_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_AUX_SNOOPING_CTRL_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_AUX_SNOOPING_CTRL_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_AUX_SNOOPING_CTRL_REG, &val);
+	zexpect_equal(val, expected);
+
+	/* CFG0 */
+	expected = (uint8_t)(ANX7483_UTX1_PORT_CFG0_REG_RESERVED_MASK &
+			     ANX7483_UTX1_PORT_CFG0_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_UTX1_PORT_CFG0_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_UTX1_PORT_CFG0_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_UTX1_PORT_CFG0_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = (uint8_t)(ANX7483_UTX2_PORT_CFG0_REG_RESERVED_MASK &
+			     ANX7483_UTX2_PORT_CFG0_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_UTX2_PORT_CFG0_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_UTX2_PORT_CFG0_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_UTX2_PORT_CFG0_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = (uint8_t)(ANX7483_URX1_PORT_CFG0_REG_RESERVED_MASK &
+			     ANX7483_URX1_PORT_CFG0_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_URX1_PORT_CFG0_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_URX1_PORT_CFG0_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_URX1_PORT_CFG0_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = (uint8_t)(ANX7483_URX2_PORT_CFG0_REG_RESERVED_MASK &
+			     ANX7483_URX1_PORT_CFG0_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_URX2_PORT_CFG0_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_URX2_PORT_CFG0_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_URX2_PORT_CFG0_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = (uint8_t)(ANX7483_DRX1_PORT_CFG0_REG_RESERVED_MASK &
+			     ANX7483_DRX1_PORT_CFG0_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_DRX1_PORT_CFG0_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_DRX1_PORT_CFG0_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_DRX1_PORT_CFG0_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = (uint8_t)(ANX7483_DRX2_PORT_CFG0_REG_RESERVED_MASK &
+			     ANX7483_DRX2_PORT_CFG0_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_DRX2_PORT_CFG0_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_DRX2_PORT_CFG0_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_DRX2_PORT_CFG0_REG, &val);
+	zexpect_equal(val, expected);
+
+	/* CFG1 */
+	expected = 0xff;
+	rv = anx7483_i2c_write(ANX7483_UTX1_PORT_CFG1_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_UTX1_PORT_CFG1_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = 0xff;
+	rv = anx7483_i2c_write(ANX7483_UTX2_PORT_CFG1_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_UTX2_PORT_CFG1_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = 0xff;
+	rv = anx7483_i2c_write(ANX7483_URX1_PORT_CFG1_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_URX1_PORT_CFG1_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = 0xff;
+	rv = anx7483_i2c_write(ANX7483_URX2_PORT_CFG1_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_URX2_PORT_CFG1_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = 0xff;
+	rv = anx7483_i2c_write(ANX7483_DRX1_PORT_CFG1_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_DRX1_PORT_CFG1_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = 0xff;
+	rv = anx7483_i2c_write(ANX7483_DRX2_PORT_CFG1_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_DRX2_PORT_CFG1_REG, &val);
+	zexpect_equal(val, expected);
+
+	/* CFG2 */
+	expected = (uint8_t)(ANX7483_UTX1_PORT_CFG2_REG_RESERVED_MASK &
+			     ANX7483_UTX1_PORT_CFG2_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_UTX1_PORT_CFG2_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_UTX1_PORT_CFG2_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_UTX1_PORT_CFG2_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = (uint8_t)(ANX7483_UTX2_PORT_CFG2_REG_RESERVED_MASK &
+			     ANX7483_UTX2_PORT_CFG2_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_UTX2_PORT_CFG2_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_UTX2_PORT_CFG2_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_UTX2_PORT_CFG2_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = (uint8_t)(ANX7483_URX1_PORT_CFG2_REG_RESERVED_MASK &
+			     ANX7483_URX1_PORT_CFG2_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_URX1_PORT_CFG2_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_URX1_PORT_CFG2_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_URX1_PORT_CFG2_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = (uint8_t)(ANX7483_URX2_PORT_CFG2_REG_RESERVED_MASK &
+			     ANX7483_URX1_PORT_CFG2_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_URX2_PORT_CFG2_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_URX2_PORT_CFG2_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_URX2_PORT_CFG2_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = (uint8_t)(ANX7483_DRX1_PORT_CFG2_REG_RESERVED_MASK &
+			     ANX7483_DRX1_PORT_CFG2_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_DRX1_PORT_CFG2_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_DRX1_PORT_CFG2_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_DRX1_PORT_CFG2_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = (uint8_t)(ANX7483_DRX2_PORT_CFG2_REG_RESERVED_MASK &
+			     ANX7483_DRX2_PORT_CFG2_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_DRX2_PORT_CFG2_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_DRX2_PORT_CFG2_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_DRX2_PORT_CFG2_REG, &val);
+	zexpect_equal(val, expected);
+
+	/* CFG3 */
+	expected = 0xff;
+	rv = anx7483_i2c_write(ANX7483_UTX1_PORT_CFG3_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_UTX1_PORT_CFG3_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = 0xff;
+	rv = anx7483_i2c_write(ANX7483_UTX2_PORT_CFG3_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_UTX2_PORT_CFG3_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = 0xff;
+	rv = anx7483_i2c_write(ANX7483_URX1_PORT_CFG3_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_URX1_PORT_CFG3_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = 0xff;
+	rv = anx7483_i2c_write(ANX7483_URX2_PORT_CFG3_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_URX2_PORT_CFG3_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = 0xff;
+	rv = anx7483_i2c_write(ANX7483_DRX1_PORT_CFG3_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_DRX1_PORT_CFG3_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = 0xff;
+	rv = anx7483_i2c_write(ANX7483_DRX2_PORT_CFG3_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_DRX2_PORT_CFG3_REG, &val);
+	zexpect_equal(val, expected);
+
+	/* CFG4 */
+	expected = (uint8_t)(ANX7483_UTX1_PORT_CFG4_REG_RESERVED_MASK &
+			     ANX7483_UTX1_PORT_CFG4_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_UTX1_PORT_CFG4_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_UTX1_PORT_CFG4_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_UTX1_PORT_CFG4_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = (uint8_t)(ANX7483_UTX2_PORT_CFG4_REG_RESERVED_MASK &
+			     ANX7483_UTX2_PORT_CFG4_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_UTX2_PORT_CFG4_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_UTX2_PORT_CFG4_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_UTX2_PORT_CFG4_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = (uint8_t)(ANX7483_URX1_PORT_CFG4_REG_RESERVED_MASK &
+			     ANX7483_URX1_PORT_CFG4_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_URX1_PORT_CFG4_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_URX1_PORT_CFG4_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_URX1_PORT_CFG4_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = (uint8_t)(ANX7483_URX2_PORT_CFG4_REG_RESERVED_MASK &
+			     ANX7483_URX1_PORT_CFG4_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_URX2_PORT_CFG4_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_URX2_PORT_CFG4_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_URX2_PORT_CFG4_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = (uint8_t)(ANX7483_DRX1_PORT_CFG4_REG_RESERVED_MASK &
+			     ANX7483_DRX1_PORT_CFG4_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_DRX1_PORT_CFG4_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_DRX1_PORT_CFG4_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_DRX1_PORT_CFG4_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = (uint8_t)(ANX7483_DRX2_PORT_CFG4_REG_RESERVED_MASK &
+			     ANX7483_DRX2_PORT_CFG4_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_DRX2_PORT_CFG4_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_DRX2_PORT_CFG4_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_DRX2_PORT_CFG4_REG, &val);
+	zexpect_equal(val, expected);
+
+	/* Ensure that reading/writing a non-existent register fails. */
+	rv = anx7483_i2c_read(0xff, &val);
+	zexpect_not_equal(rv, 0);
+	rv = anx7483_i2c_write(0xff, 0xff);
+	zexpect_not_equal(rv, 0);
+}
+
+/* Test that the ANX7483 driver correctly reports its state. */
+ZTEST(anx7483, test_mux_state_get)
+{
+	int rv;
+	uint8_t val;
+	mux_state_t state;
+
+	rv = anx7483_emul_test_get_reg(ANX7483_ANALOG_STATUS_CTRL_REG, &val);
+	zexpect_ok(rv);
+	val |= ANX7483_CTRL_USB_EN;
+	val |= ANX7483_CTRL_DP_EN;
+	val |= ANX7483_CTRL_FLIP_EN;
+	rv = anx7483_emul_test_set_reg(ANX7483_ANALOG_STATUS_CTRL_REG, val);
+	zexpect_ok(rv);
+
+	rv = anx7483_get(&mux, &state);
+	zexpect_ok(rv);
+	zexpect_true(val & USB_PD_MUX_USB_ENABLED);
+	zexpect_true(val & USB_PD_MUX_DP_ENABLED);
+	zexpect_true(val & USB_PD_MUX_POLARITY_INVERTED);
+}
+
+/* Test that the ANX7483 driver correctly sets the mux state. */
+ZTEST(anx7483, test_mux_state_set)
+{
+	int rv;
+	uint8_t val;
+	bool ack_required;
+
+	rv = anx7483_set(&mux,
+			 USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED |
+				 USB_PD_MUX_POLARITY_INVERTED,
+			 &ack_required);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_get_reg(ANX7483_ANALOG_STATUS_CTRL_REG, &val);
+	zexpect_ok(rv);
+	zexpect_true(val & ANX7483_CTRL_REG_EN);
+	zexpect_true(val & ANX7483_CTRL_USB_EN);
+	zexpect_true(val & ANX7483_CTRL_DP_EN);
+	zexpect_true(val & ANX7483_CTRL_FLIP_EN);
+}
+
+/* Validates that writing to a reserved register returns an error. */
+ZTEST(anx7483, test_emul_reserved)
+{
+	int rv;
+
+	rv = anx7483_emul_test_set_reg(ANX7483_LFPS_TIMER_REG,
+				       ANX7483_LFPS_TIMER_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+
+	rv = anx7483_emul_test_set_reg(
+		ANX7483_ANALOG_STATUS_CTRL_REG,
+		ANX7483_ANALOG_STATUS_CTRL_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+
+	rv = anx7483_emul_test_set_reg(
+		ANX7483_ENABLE_EQ_FLAT_SWING_REG,
+		ANX7483_ENABLE_EQ_FLAT_SWING_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+
+	rv = anx7483_emul_test_set_reg(
+		ANX7483_AUX_SNOOPING_CTRL_REG,
+		ANX7483_AUX_SNOOPING_CTRL_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+
+	/* CFG0 */
+	rv = anx7483_emul_test_set_reg(
+		ANX7483_UTX1_PORT_CFG0_REG,
+		ANX7483_UTX1_PORT_CFG0_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+
+	rv = anx7483_emul_test_set_reg(
+		ANX7483_UTX2_PORT_CFG0_REG,
+		ANX7483_UTX2_PORT_CFG0_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+
+	rv = anx7483_emul_test_set_reg(
+		ANX7483_URX1_PORT_CFG0_REG,
+		ANX7483_URX1_PORT_CFG0_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+
+	rv = anx7483_emul_test_set_reg(
+		ANX7483_URX2_PORT_CFG0_REG,
+		ANX7483_URX2_PORT_CFG0_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+
+	rv = anx7483_emul_test_set_reg(
+		ANX7483_DRX1_PORT_CFG0_REG,
+		ANX7483_DRX1_PORT_CFG0_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+
+	rv = anx7483_emul_test_set_reg(
+		ANX7483_DRX2_PORT_CFG0_REG,
+		ANX7483_DRX2_PORT_CFG0_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+
+	/* CFG2 */
+	rv = anx7483_emul_test_set_reg(
+		ANX7483_UTX1_PORT_CFG2_REG,
+		ANX7483_UTX1_PORT_CFG2_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+
+	rv = anx7483_emul_test_set_reg(
+		ANX7483_UTX2_PORT_CFG2_REG,
+		ANX7483_UTX2_PORT_CFG2_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+
+	rv = anx7483_emul_test_set_reg(
+		ANX7483_URX1_PORT_CFG2_REG,
+		ANX7483_URX1_PORT_CFG2_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+
+	rv = anx7483_emul_test_set_reg(
+		ANX7483_URX2_PORT_CFG2_REG,
+		ANX7483_URX2_PORT_CFG2_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+
+	rv = anx7483_emul_test_set_reg(
+		ANX7483_DRX1_PORT_CFG2_REG,
+		ANX7483_DRX1_PORT_CFG2_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+
+	rv = anx7483_emul_test_set_reg(
+		ANX7483_DRX2_PORT_CFG2_REG,
+		ANX7483_DRX2_PORT_CFG2_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+
+	/* CFG4 */
+	rv = anx7483_emul_test_set_reg(
+		ANX7483_UTX1_PORT_CFG4_REG,
+		ANX7483_UTX1_PORT_CFG4_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+
+	rv = anx7483_emul_test_set_reg(
+		ANX7483_UTX2_PORT_CFG4_REG,
+		ANX7483_UTX2_PORT_CFG4_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+
+	rv = anx7483_emul_test_set_reg(
+		ANX7483_URX1_PORT_CFG4_REG,
+		ANX7483_URX1_PORT_CFG4_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+
+	rv = anx7483_emul_test_set_reg(
+		ANX7483_URX2_PORT_CFG4_REG,
+		ANX7483_URX2_PORT_CFG4_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+
+	rv = anx7483_emul_test_set_reg(
+		ANX7483_DRX1_PORT_CFG4_REG,
+		ANX7483_DRX1_PORT_CFG4_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+
+	rv = anx7483_emul_test_set_reg(
+		ANX7483_DRX2_PORT_CFG4_REG,
+		ANX7483_DRX2_PORT_CFG4_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+}
+
+/*
+ * Verify that we can make changes to the reserved masks to allow board-specific
+ * tunings to be tested.
+ */
+ZTEST(anx7483, test_emul_update_reserved)
+{
+	int rv;
+	uint8_t antimask;
+
+	antimask = (uint8_t)(~ANX7483_LFPS_TIMER_REG_RESERVED_MASK);
+	rv = anx7483_emul_test_set_mask(ANX7483_LFPS_TIMER_REG, antimask, 0);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_set_reg(ANX7483_LFPS_TIMER_REG, ~antimask);
+	zexpect_ok(rv);
+
+	antimask = (uint8_t)(~ANX7483_ANALOG_STATUS_CTRL_REG_RESERVED_MASK);
+	rv = anx7483_emul_test_set_mask(ANX7483_ANALOG_STATUS_CTRL_REG,
+					antimask, 0);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_set_reg(ANX7483_ANALOG_STATUS_CTRL_REG,
+				       ~antimask);
+	zexpect_ok(rv);
+
+	antimask = (uint8_t)(~ANX7483_ENABLE_EQ_FLAT_SWING_REG_RESERVED_MASK);
+	rv = anx7483_emul_test_set_mask(ANX7483_ENABLE_EQ_FLAT_SWING_REG,
+					antimask, 0);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_set_reg(ANX7483_ENABLE_EQ_FLAT_SWING_REG,
+				       ~antimask);
+	zexpect_ok(rv);
+
+	antimask = (uint8_t)(~ANX7483_AUX_SNOOPING_CTRL_REG_RESERVED_MASK);
+	rv = anx7483_emul_test_set_mask(ANX7483_AUX_SNOOPING_CTRL_REG, antimask,
+					0);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_set_reg(ANX7483_AUX_SNOOPING_CTRL_REG,
+				       ~antimask);
+	zexpect_ok(rv);
+
+	/* CFG0 */
+	antimask = (uint8_t)(~ANX7483_UTX1_PORT_CFG0_REG_RESERVED_MASK);
+	rv = anx7483_emul_test_set_mask(ANX7483_UTX1_PORT_CFG0_REG, antimask,
+					0);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_set_reg(ANX7483_UTX1_PORT_CFG0_REG, ~antimask);
+	zexpect_ok(rv);
+
+	antimask = (uint8_t)(~ANX7483_UTX2_PORT_CFG0_REG_RESERVED_MASK);
+	rv = anx7483_emul_test_set_mask(ANX7483_UTX2_PORT_CFG0_REG, antimask,
+					0);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_set_reg(ANX7483_UTX2_PORT_CFG0_REG, ~antimask);
+	zexpect_ok(rv);
+
+	antimask = (uint8_t)(~ANX7483_URX1_PORT_CFG0_REG_RESERVED_MASK);
+	rv = anx7483_emul_test_set_mask(ANX7483_URX1_PORT_CFG0_REG, antimask,
+					0);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_set_reg(ANX7483_URX1_PORT_CFG0_REG, ~antimask);
+	zexpect_ok(rv);
+
+	antimask = (uint8_t)(~ANX7483_URX2_PORT_CFG0_REG_RESERVED_MASK);
+	rv = anx7483_emul_test_set_mask(ANX7483_URX2_PORT_CFG0_REG, antimask,
+					0);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_set_reg(ANX7483_URX2_PORT_CFG0_REG, ~antimask);
+	zexpect_ok(rv);
+
+	antimask = (uint8_t)(~ANX7483_DRX1_PORT_CFG0_REG_RESERVED_MASK);
+	rv = anx7483_emul_test_set_mask(ANX7483_DRX1_PORT_CFG0_REG, antimask,
+					0);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_set_reg(ANX7483_DRX1_PORT_CFG0_REG, ~antimask);
+	zexpect_ok(rv);
+
+	antimask = (uint8_t)(~ANX7483_DRX2_PORT_CFG0_REG_RESERVED_MASK);
+	rv = anx7483_emul_test_set_mask(ANX7483_DRX2_PORT_CFG0_REG, antimask,
+					0);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_set_reg(ANX7483_DRX2_PORT_CFG0_REG, ~antimask);
+	zexpect_ok(rv);
+
+	/* CFG2 */
+	antimask = (uint8_t)(~ANX7483_UTX1_PORT_CFG2_REG_RESERVED_MASK);
+	rv = anx7483_emul_test_set_mask(ANX7483_UTX1_PORT_CFG2_REG, antimask,
+					0);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_set_reg(ANX7483_UTX1_PORT_CFG2_REG, ~antimask);
+	zexpect_ok(rv);
+
+	antimask = (uint8_t)(~ANX7483_UTX2_PORT_CFG2_REG_RESERVED_MASK);
+	rv = anx7483_emul_test_set_mask(ANX7483_UTX2_PORT_CFG2_REG, antimask,
+					0);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_set_reg(ANX7483_UTX2_PORT_CFG2_REG, ~antimask);
+	zexpect_ok(rv);
+
+	antimask = (uint8_t)(~ANX7483_URX1_PORT_CFG2_REG_RESERVED_MASK);
+	rv = anx7483_emul_test_set_mask(ANX7483_URX1_PORT_CFG2_REG, antimask,
+					0);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_set_reg(ANX7483_URX1_PORT_CFG2_REG, ~antimask);
+	zexpect_ok(rv);
+
+	antimask = (uint8_t)(~ANX7483_URX2_PORT_CFG2_REG_RESERVED_MASK);
+	rv = anx7483_emul_test_set_mask(ANX7483_URX2_PORT_CFG2_REG, antimask,
+					0);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_set_reg(ANX7483_URX2_PORT_CFG2_REG, ~antimask);
+	zexpect_ok(rv);
+
+	antimask = (uint8_t)(~ANX7483_DRX1_PORT_CFG2_REG_RESERVED_MASK);
+	rv = anx7483_emul_test_set_mask(ANX7483_DRX1_PORT_CFG2_REG, antimask,
+					0);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_set_reg(ANX7483_DRX1_PORT_CFG2_REG, ~antimask);
+	zexpect_ok(rv);
+
+	antimask = (uint8_t)(~ANX7483_DRX2_PORT_CFG2_REG_RESERVED_MASK);
+	rv = anx7483_emul_test_set_mask(ANX7483_DRX2_PORT_CFG2_REG, antimask,
+					0);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_set_reg(ANX7483_DRX2_PORT_CFG2_REG, ~antimask);
+	zexpect_ok(rv);
+
+	/* CFG4 */
+	antimask = (uint8_t)(~ANX7483_UTX1_PORT_CFG4_REG_RESERVED_MASK);
+	rv = anx7483_emul_test_set_mask(ANX7483_UTX1_PORT_CFG4_REG, antimask,
+					0);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_set_reg(ANX7483_UTX1_PORT_CFG4_REG, ~antimask);
+	zexpect_ok(rv);
+
+	antimask = (uint8_t)(~ANX7483_UTX2_PORT_CFG4_REG_RESERVED_MASK);
+	rv = anx7483_emul_test_set_mask(ANX7483_UTX2_PORT_CFG4_REG, antimask,
+					0);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_set_reg(ANX7483_UTX2_PORT_CFG4_REG, ~antimask);
+	zexpect_ok(rv);
+
+	antimask = (uint8_t)(~ANX7483_URX1_PORT_CFG4_REG_RESERVED_MASK);
+	rv = anx7483_emul_test_set_mask(ANX7483_URX1_PORT_CFG4_REG, antimask,
+					0);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_set_reg(ANX7483_URX1_PORT_CFG4_REG, ~antimask);
+	zexpect_ok(rv);
+
+	antimask = (uint8_t)(~ANX7483_URX2_PORT_CFG4_REG_RESERVED_MASK);
+	rv = anx7483_emul_test_set_mask(ANX7483_URX2_PORT_CFG4_REG, antimask,
+					0);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_set_reg(ANX7483_URX2_PORT_CFG4_REG, ~antimask);
+	zexpect_ok(rv);
+
+	antimask = (uint8_t)(~ANX7483_DRX1_PORT_CFG4_REG_RESERVED_MASK);
+	rv = anx7483_emul_test_set_mask(ANX7483_DRX1_PORT_CFG4_REG, antimask,
+					0);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_set_reg(ANX7483_DRX1_PORT_CFG4_REG, ~antimask);
+	zexpect_ok(rv);
+
+	antimask = (uint8_t)(~ANX7483_DRX2_PORT_CFG4_REG_RESERVED_MASK);
+	rv = anx7483_emul_test_set_mask(ANX7483_DRX2_PORT_CFG4_REG, antimask,
+					0);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_set_reg(ANX7483_DRX2_PORT_CFG4_REG, ~antimask);
+	zexpect_ok(rv);
+}
+
+/*
+ * Tests that the ANX7483 driver correctly configures the default tuning for
+ * USB.
+ */
+ZTEST(anx7483, test_tuning_usb)
+{
+	/*
+	 * Vendor defined tuning settings, these should match those in the
+	 * anx7483_usb_enabled struct within the driver.
+	 */
+	const struct anx7483_tuning_set usb_enabled[] = {
+		{ ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+		{ ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+		{ ANX7483_DRX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+		{ ANX7483_DRX2_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+
+		{ ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+		{ ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+		{ ANX7483_DRX1_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+		{ ANX7483_DRX2_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+
+		{ ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE },
+		{ ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE },
+		{ ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE },
+		{ ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE },
+
+		{ ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+		{ ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+		{ ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+		{ ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+
+		{ ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+		{ ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+		{ ANX7483_DRX1_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+		{ ANX7483_DRX2_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+
+		{ ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT },
+		{ ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT },
+		{ ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT },
+		{ ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT },
+
+		{ ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+		{ ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+		{ ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+		{ ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+	};
+	int rv;
+
+	rv = anx7483_set_default_tuning(&mux, USB_PD_MUX_USB_ENABLED);
+	zexpect_ok(rv);
+
+	zassert_equal(ARRAY_SIZE(usb_enabled), anx7483_usb_enabled_count);
+	rv = anx7483_emul_validate_tuning(ANX7483_EMUL, usb_enabled,
+					  ARRAY_SIZE(usb_enabled));
+	zexpect_ok(rv);
+}
+
+/*
+ * Tests that the ANX7483 driver correctly configures the default tuning for
+ * DisplayPort.
+ */
+ZTEST(anx7483, test_tuning_dp)
+{
+	/*
+	 * Vendor defined tuning settings, these should match those in the
+	 * anx7483_dp_enabled struct within the driver.
+	 */
+	const struct anx7483_tuning_set dp_enabled[] = {
+		{ ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF },
+
+		{ ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+		{ ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+		{ ANX7483_UTX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+		{ ANX7483_UTX2_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+
+		{ ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+		{ ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+		{ ANX7483_UTX1_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+		{ ANX7483_UTX2_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+
+		{ ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+		{ ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+		{ ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+		{ ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+		{ ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+		{ ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+		{ ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+		{ ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+
+		{ ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+		{ ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+		{ ANX7483_UTX1_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+		{ ANX7483_UTX2_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+
+		{ ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+		{ ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+		{ ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+		{ ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+		{ ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+		{ ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+		{ ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+		{ ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+	};
+	int rv;
+
+	rv = anx7483_set_default_tuning(&mux, USB_PD_MUX_DP_ENABLED);
+	zexpect_ok(rv);
+
+	zassert_equal(ARRAY_SIZE(dp_enabled), anx7483_dp_enabled_count);
+	rv = anx7483_emul_validate_tuning(ANX7483_EMUL, dp_enabled,
+					  ARRAY_SIZE(dp_enabled));
+	zexpect_ok(rv);
+}
+
+/*
+ * Tests that the ANX7483 driver correctly configures the default tuning for
+ * dock mode in a non-flipped state.
+ */
+ZTEST(anx7483, test_tuning_dock_noflip)
+{
+	/*
+	 * Vendor defined tuning settings, these should match those in the
+	 * anx7483_dock_noflip struct within the driver.
+	 */
+	const test_export_static struct anx7483_tuning_set dock_noflip[] = {
+		{ ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF },
+
+		{ ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+		{ ANX7483_DRX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+		{ ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+		{ ANX7483_UTX2_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+
+		{ ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+		{ ANX7483_DRX1_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+		{ ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+		{ ANX7483_UTX2_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+
+		{ ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE },
+		{ ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE },
+
+		{ ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+		{ ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+		{ ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+		{ ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+		{ ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+		{ ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+
+		{ ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+		{ ANX7483_DRX1_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+		{ ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+		{ ANX7483_UTX2_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+
+		{ ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+		{ ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+		{ ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+		{ ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+		{ ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+		{ ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+		{ ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+		{ ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+	};
+	int rv;
+
+	rv = anx7483_set_default_tuning(&mux, USB_PD_MUX_DOCK);
+	zexpect_ok(rv);
+
+	zassert_equal(ARRAY_SIZE(dock_noflip), anx7483_dock_noflip_count);
+	rv = anx7483_emul_validate_tuning(ANX7483_EMUL, dock_noflip,
+					  ARRAY_SIZE(dock_noflip));
+	zexpect_ok(rv);
+}
+
+/*
+ * Tests that the ANX7483 driver correctly configures the default tuning for
+ * dock mode in a flipped state.
+ */
+ZTEST(anx7483, test_tuning_dock_flip)
+{
+	/*
+	 * Vendor defined tuning settings, these should match those in the
+	 * anx7483_dock_flip struct within the driver.
+	 */
+	const test_export_static struct anx7483_tuning_set dock_flip[] = {
+		{ ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF },
+
+		{ ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+		{ ANX7483_DRX2_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+		{ ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+		{ ANX7483_UTX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+
+		{ ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+		{ ANX7483_DRX2_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+		{ ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+		{ ANX7483_UTX1_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+
+		{ ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE },
+		{ ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE },
+
+		{ ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+		{ ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+		{ ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+		{ ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+		{ ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+		{ ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+
+		{ ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+		{ ANX7483_UTX1_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+		{ ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+		{ ANX7483_DRX2_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+
+		{ ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+		{ ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+		{ ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+		{ ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+		{ ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+		{ ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+		{ ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+		{ ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+	};
+	int rv;
+
+	rv = anx7483_set_default_tuning(
+		&mux, USB_PD_MUX_DOCK | USB_PD_MUX_POLARITY_INVERTED);
+	zexpect_ok(rv);
+
+	zassert_equal(ARRAY_SIZE(dock_flip), anx7483_dock_flip_count);
+	rv = anx7483_emul_validate_tuning(ANX7483_EMUL, dock_flip,
+					  ARRAY_SIZE(dock_flip));
+	zexpect_ok(rv);
+}
diff --git a/zephyr/test/drivers/usbc_retimer/src/ps8811.c b/zephyr/test/drivers/usbc_retimer/src/ps8811.c
new file mode 100644
index 0000000000..5c76f49964
--- /dev/null
+++ b/zephyr/test/drivers/usbc_retimer/src/ps8811.c
@@ -0,0 +1,344 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/retimer/ps8811.h"
+#include "emul/retimer/emul_ps8811.h"
+#include "i2c.h"
+#include "usb_mux.h"
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/ztest.h>
+
+#define PS811_EMUL EMUL_DT_GET(DT_NODELABEL(ps8811_emul))
+
+static struct usb_mux mux = {
+	.i2c_port = I2C_PORT_NODELABEL(i2c3),
+	.i2c_addr_flags = PS8811_I2C_ADDR_FLAGS3,
+};
+
+ZTEST_SUITE(ps8811, NULL, NULL, NULL, NULL, NULL);
+
+/* Helper functions to make tests clearer. */
+static int ps8811_emul_test_read0(int reg, int *val)
+{
+	return ps8811_i2c_read(&mux, PS8811_REG_PAGE0, reg, val);
+}
+
+static int ps8811_emul_test_write0(int reg, int val)
+{
+	return ps8811_i2c_write(&mux, PS8811_REG_PAGE0, reg, val);
+}
+
+static int ps8811_emul_test_update0(int reg, uint8_t mask, uint8_t val)
+{
+	return ps8811_i2c_field_update(&mux, PS8811_REG_PAGE0, reg, mask, val);
+}
+
+static int ps8811_emul_test_read1(int reg, int *val)
+{
+	return ps8811_i2c_read(&mux, PS8811_REG_PAGE1, reg, val);
+}
+
+static int ps8811_emul_test_write1(int reg, int val)
+{
+	return ps8811_i2c_write(&mux, PS8811_REG_PAGE1, reg, val);
+}
+
+static int ps8811_emul_test_update1(int reg, uint8_t mask, uint8_t val)
+{
+	return ps8811_i2c_field_update(&mux, PS8811_REG_PAGE1, reg, mask, val);
+}
+
+static int ps8811_emul_test_get_reg1(int reg, uint8_t *val)
+{
+	return ps8811_emul_get_reg1(PS811_EMUL, reg, val);
+}
+
+static int ps8811_emul_test_set_reg1(int reg, uint8_t val)
+{
+	return ps8811_emul_set_reg1(PS811_EMUL, reg, val);
+}
+
+/* Verify that the reset values for all registers are correct. */
+ZTEST(ps8811, test_emul_reset)
+{
+	uint8_t val;
+	int rv;
+
+	rv = ps8811_emul_test_get_reg1(PS8811_REG1_USB_AEQ_LEVEL, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, PS8811_REG1_USB_AEQ_LEVEL_DEFAULT);
+
+	rv = ps8811_emul_test_get_reg1(PS8811_REG1_USB_ADE_CONFIG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, PS8811_REG1_USB_ADE_CONFIG_DEFAULT);
+
+	rv = ps8811_emul_test_get_reg1(PS8811_REG1_USB_BEQ_LEVEL, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, PS8811_REG1_USB_BEQ_LEVEL_DEFAULT);
+
+	rv = ps8811_emul_test_get_reg1(PS8811_REG1_USB_BDE_CONFIG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, PS8811_REG1_USB_BDE_CONFIG_DEFAULT);
+
+	rv = ps8811_emul_test_get_reg1(PS8811_REG1_USB_CHAN_A_SWING, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, PS8811_REG1_USB_CHAN_A_SWING_DEFAULT);
+
+	rv = ps8811_emul_test_get_reg1(PS8811_REG1_50OHM_ADJUST_CHAN_B, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, PS8811_REG1_50OHM_ADJUST_CHAN_B_DEFAULT);
+
+	rv = ps8811_emul_test_get_reg1(PS8811_REG1_USB_CHAN_B_SWING, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, PS8811_REG1_USB_CHAN_B_SWING_DEFAULT);
+
+	rv = ps8811_emul_test_get_reg1(PS8811_REG1_USB_CHAN_B_DE_PS_LSB, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, PS8811_REG1_USB_CHAN_B_DE_PS_LSB_DEFAULT);
+
+	ps8811_emul_test_get_reg1(PS8811_REG1_USB_CHAN_B_DE_PS_MSB, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, PS8811_REG1_USB_CHAN_B_DE_PS_MSB_DEFAULT);
+}
+
+/*
+ * P0 registers aren't currently implemented,
+ * ensure access results in an error.
+ */
+ZTEST(ps8811, test_emul_page0_registers)
+{
+	int rv;
+	int val;
+
+	rv = ps8811_emul_test_write0(0, 0);
+	zexpect_not_equal(rv, EC_SUCCESS);
+	rv = ps8811_emul_test_read0(0, &val);
+	zexpect_not_equal(rv, EC_SUCCESS);
+	rv = ps8811_emul_test_update0(0, 0xff, 0xff);
+	zexpect_not_equal(rv, EC_SUCCESS);
+}
+
+/*
+ * Verify that writing/reading all our registers through I2C works. But
+ * don't attempt to verify errors when writing reserved bits.
+ */
+ZTEST(ps8811, test_emul_page1_registers_rw)
+{
+	int val;
+	int rv;
+	uint8_t expected;
+
+	expected = 0xff;
+	rv = ps8811_emul_test_write1(PS8811_REG1_USB_AEQ_LEVEL, expected);
+	zexpect_ok(rv, EC_SUCCESS);
+	rv = ps8811_emul_test_read1(PS8811_REG1_USB_AEQ_LEVEL, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, expected);
+
+	expected = 0xff;
+	rv = ps8811_emul_test_write1(PS8811_REG1_USB_ADE_CONFIG, expected);
+	zexpect_ok(rv);
+	rv = ps8811_emul_test_read1(PS8811_REG1_USB_ADE_CONFIG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, expected);
+
+	expected = 0xff;
+	rv = ps8811_emul_test_write1(PS8811_REG1_USB_BEQ_LEVEL, expected);
+	zexpect_ok(rv);
+	rv = ps8811_emul_test_read1(PS8811_REG1_USB_BEQ_LEVEL, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, expected);
+
+	expected = 0xff;
+	rv = ps8811_emul_test_write1(PS8811_REG1_USB_BDE_CONFIG, expected);
+	zexpect_ok(rv);
+	rv = ps8811_emul_test_read1(PS8811_REG1_USB_BDE_CONFIG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, expected);
+
+	expected = (uint8_t)(PS8811_REG1_USB_CHAN_A_SWING_RESERVED_MASK &
+			     PS8811_REG1_USB_CHAN_A_SWING_DEFAULT);
+	expected |= (uint8_t)(~PS8811_REG1_USB_CHAN_A_SWING_RESERVED_MASK);
+	rv = ps8811_emul_test_write1(PS8811_REG1_USB_CHAN_A_SWING, expected);
+	zexpect_ok(rv);
+	rv = ps8811_emul_test_read1(PS8811_REG1_USB_CHAN_A_SWING, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, expected);
+
+	expected = (uint8_t)(PS8811_REG1_50OHM_ADJUST_CHAN_B_RESERVED_MASK &
+			     PS8811_REG1_50OHM_ADJUST_CHAN_B_DEFAULT);
+	expected |= (uint8_t)(~PS8811_REG1_50OHM_ADJUST_CHAN_B_RESERVED_MASK);
+	rv = ps8811_emul_test_write1(PS8811_REG1_50OHM_ADJUST_CHAN_B, expected);
+	zexpect_ok(rv);
+	rv = ps8811_emul_test_read1(PS8811_REG1_50OHM_ADJUST_CHAN_B, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, expected);
+
+	expected = (uint8_t)(PS8811_REG1_USB_CHAN_B_SWING_RESERVED_MASK &
+			     PS8811_REG1_USB_CHAN_B_SWING_DEFAULT);
+	expected |= (uint8_t)(~PS8811_REG1_USB_CHAN_B_SWING_RESERVED_MASK);
+	rv = ps8811_emul_test_write1(PS8811_REG1_USB_CHAN_B_SWING, expected);
+	zexpect_ok(rv);
+	rv = ps8811_emul_test_read1(PS8811_REG1_USB_CHAN_B_SWING, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, expected);
+
+	expected = (uint8_t)(PS8811_REG1_USB_CHAN_B_DE_PS_LSB_RESERVED_MASK &
+			     PS8811_REG1_USB_CHAN_B_DE_PS_LSB_DEFAULT);
+	expected |= (uint8_t)(~PS8811_REG1_USB_CHAN_B_DE_PS_LSB_RESERVED_MASK);
+	rv = ps8811_emul_test_write1(PS8811_REG1_USB_CHAN_B_DE_PS_LSB,
+				     expected);
+	zexpect_ok(rv);
+	rv = ps8811_emul_test_read1(PS8811_REG1_USB_CHAN_B_DE_PS_LSB, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, expected);
+
+	expected = (uint8_t)(PS8811_REG1_USB_CHAN_B_DE_PS_MSB_RESERVED_MASK &
+			     PS8811_REG1_USB_CHAN_B_DE_PS_MSB_DEFAULT);
+	expected |= (uint8_t)(~PS8811_REG1_USB_CHAN_B_DE_PS_MSB_RESERVED_MASK);
+	rv = ps8811_emul_test_write1(PS8811_REG1_USB_CHAN_B_DE_PS_MSB,
+				     expected);
+	zexpect_ok(rv);
+	rv = ps8811_emul_test_read1(PS8811_REG1_USB_CHAN_B_DE_PS_MSB, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, expected);
+
+	/* Verify that accessing a non-existent register fails. */
+	rv = ps8811_emul_test_write1(0xff, 0xff);
+	zexpect_not_equal(rv, EC_SUCCESS);
+	rv = ps8811_emul_test_read1(0xff, &val);
+	zexpect_not_equal(rv, EC_SUCCESS);
+}
+
+/* Verify that I2C register updates work. */
+ZTEST(ps8811, test_emul_page1_registers_update)
+{
+	int rv;
+	uint8_t val;
+
+	rv = ps8811_emul_test_set_reg1(PS8811_REG1_USB_AEQ_LEVEL, 0xff);
+	zexpect_ok(rv);
+	rv = ps8811_emul_test_update1(PS8811_REG1_USB_AEQ_LEVEL, 0x0f, 0x00);
+	zexpect_ok(rv);
+	rv = ps8811_emul_test_get_reg1(PS8811_REG1_USB_AEQ_LEVEL, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, 0xf0);
+
+	rv = ps8811_emul_test_set_reg1(PS8811_REG1_USB_ADE_CONFIG, 0xff);
+	zexpect_ok(rv);
+	rv = ps8811_emul_test_update1(PS8811_REG1_USB_ADE_CONFIG, 0x0f, 0x00);
+	zexpect_ok(rv);
+	rv = ps8811_emul_test_get_reg1(PS8811_REG1_USB_ADE_CONFIG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, 0xf0);
+
+	rv = ps8811_emul_test_set_reg1(PS8811_REG1_USB_BEQ_LEVEL, 0xff);
+	zexpect_ok(rv);
+	rv = ps8811_emul_test_update1(PS8811_REG1_USB_BEQ_LEVEL, 0x0f, 0x00);
+	zexpect_ok(rv);
+	rv = ps8811_emul_test_get_reg1(PS8811_REG1_USB_BEQ_LEVEL, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, 0xf0);
+
+	rv = ps8811_emul_test_set_reg1(PS8811_REG1_USB_BDE_CONFIG, 0xff);
+	zexpect_ok(rv);
+	rv = ps8811_emul_test_update1(PS8811_REG1_USB_BDE_CONFIG, 0x0f, 0x0);
+	zexpect_ok(rv);
+	rv = ps8811_emul_test_get_reg1(PS8811_REG1_USB_BDE_CONFIG, &val);
+	zexpect_equal(val, 0xf0);
+
+	const uint8_t a_swing_mask =
+		(uint8_t)(~PS8811_REG1_USB_CHAN_A_SWING_RESERVED_MASK);
+	rv = ps8811_emul_test_set_reg1(PS8811_REG1_USB_CHAN_A_SWING,
+				       a_swing_mask);
+	zexpect_ok(rv);
+	rv = ps8811_emul_test_update1(PS8811_REG1_USB_CHAN_A_SWING,
+				      a_swing_mask, 0x0);
+	zexpect_ok(rv);
+	rv = ps8811_emul_test_get_reg1(PS8811_REG1_USB_CHAN_A_SWING, &val);
+	zexpect_equal(val, 0x00);
+
+	const uint8_t adjust_b_50ohm_mask =
+		(uint8_t)(~PS8811_REG1_50OHM_ADJUST_CHAN_B_RESERVED_MASK);
+	rv = ps8811_emul_test_set_reg1(PS8811_REG1_50OHM_ADJUST_CHAN_B,
+				       adjust_b_50ohm_mask);
+	zexpect_ok(rv);
+	rv = ps8811_emul_test_update1(PS8811_REG1_50OHM_ADJUST_CHAN_B,
+				      adjust_b_50ohm_mask, 0x0);
+	zexpect_ok(rv);
+	rv = ps8811_emul_test_get_reg1(PS8811_REG1_50OHM_ADJUST_CHAN_B, &val);
+	zexpect_equal(val, 0x00);
+
+	const uint8_t b_swing_mask =
+		(uint8_t)(~PS8811_REG1_USB_CHAN_B_SWING_RESERVED_MASK);
+	rv = ps8811_emul_test_set_reg1(PS8811_REG1_USB_CHAN_B_SWING,
+				       b_swing_mask);
+	zexpect_ok(rv);
+	rv = ps8811_emul_test_update1(PS8811_REG1_USB_CHAN_B_SWING,
+				      b_swing_mask, 0x0);
+	zexpect_ok(rv);
+	rv = ps8811_emul_test_get_reg1(PS8811_REG1_USB_CHAN_B_SWING, &val);
+	zexpect_equal(val, 0x00);
+
+	/* This register has its highest reserved bit set by default. */
+	const uint8_t b_de_ps_lsb_mask =
+		(uint8_t)(~PS8811_REG1_USB_CHAN_B_DE_PS_LSB_RESERVED_MASK) |
+		0x80;
+	rv = ps8811_emul_test_set_reg1(PS8811_REG1_USB_CHAN_B_DE_PS_LSB,
+				       b_de_ps_lsb_mask);
+	zexpect_ok(rv);
+	rv = ps8811_emul_test_update1(PS8811_REG1_USB_CHAN_B_DE_PS_LSB,
+				      b_de_ps_lsb_mask, 0x80);
+	zexpect_ok(rv);
+	rv = ps8811_emul_test_get_reg1(PS8811_REG1_USB_CHAN_B_DE_PS_LSB, &val);
+	zexpect_equal(val, 0x80);
+
+	const uint8_t b_de_ps_msb_mask =
+		(uint8_t)(~PS8811_REG1_USB_CHAN_B_DE_PS_MSB_RESERVED_MASK);
+	rv = ps8811_emul_test_set_reg1(PS8811_REG1_USB_CHAN_B_DE_PS_MSB,
+				       b_de_ps_msb_mask);
+	zexpect_ok(rv);
+	rv = ps8811_emul_test_update1(PS8811_REG1_USB_CHAN_B_DE_PS_MSB,
+				      b_de_ps_msb_mask, 0x0);
+	zexpect_ok(rv);
+	rv = ps8811_emul_test_get_reg1(PS8811_REG1_USB_CHAN_B_DE_PS_MSB, &val);
+	zexpect_equal(val, 0x00);
+
+	/* Verify that updating a non-existent register fails. */
+	rv = ps8811_emul_test_update1(0xff, 0xff, 0xff);
+	zexpect_not_equal(rv, EC_SUCCESS);
+}
+
+/* Verify that writing to reserved bits results in an error. */
+ZTEST(ps8811, test_emul_reserved)
+{
+	int rv;
+
+	rv = ps8811_emul_test_write1(
+		PS8811_REG1_USB_CHAN_A_SWING,
+		PS8811_REG1_USB_CHAN_A_SWING_RESERVED_MASK);
+	zexpect_not_equal(rv, EC_SUCCESS);
+
+	rv = ps8811_emul_test_write1(
+		PS8811_REG1_50OHM_ADJUST_CHAN_B,
+		PS8811_REG1_50OHM_ADJUST_CHAN_B_RESERVED_MASK);
+	zexpect_not_equal(rv, EC_SUCCESS);
+
+	rv = ps8811_emul_test_write1(
+		PS8811_REG1_USB_CHAN_B_SWING,
+		PS8811_REG1_USB_CHAN_B_SWING_RESERVED_MASK);
+	zexpect_not_equal(rv, EC_SUCCESS);
+
+	rv = ps8811_emul_test_write1(
+		PS8811_REG1_USB_CHAN_B_DE_PS_LSB,
+		PS8811_REG1_USB_CHAN_B_DE_PS_LSB_RESERVED_MASK);
+	zexpect_not_equal(rv, EC_SUCCESS);
+
+	rv = ps8811_emul_test_write1(
+		PS8811_REG1_USB_CHAN_B_DE_PS_MSB,
+		PS8811_REG1_USB_CHAN_B_DE_PS_MSB_RESERVED_MASK);
+	zexpect_not_equal(rv, EC_SUCCESS);
+}
diff --git a/zephyr/test/drivers/usbc_svdm_dfp_only/CMakeLists.txt b/zephyr/test/drivers/usbc_svdm_dfp_only/CMakeLists.txt
new file mode 100644
index 0000000000..7f30212d6f
--- /dev/null
+++ b/zephyr/test/drivers/usbc_svdm_dfp_only/CMakeLists.txt
@@ -0,0 +1,5 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_sources(app PRIVATE src/usbc_svdm_dfp_only.c)
diff --git a/zephyr/test/drivers/usbc_svdm_dfp_only/boards/native_posix.overlay b/zephyr/test/drivers/usbc_svdm_dfp_only/boards/native_posix.overlay
new file mode 100644
index 0000000000..0e428e271a
--- /dev/null
+++ b/zephyr/test/drivers/usbc_svdm_dfp_only/boards/native_posix.overlay
@@ -0,0 +1,23 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "../../boards/native_posix.overlay"
+
+/*
+ * The SVDM DFP only tests explicitly do not support USB4/TBT which
+ * automatically get turned on if the Burnside Bridge retimer is used.
+ * Remove this device from the devicetree.
+ */
+ /delete-node/ &usb_c1_bb_retimer_emul;
+
+ / {
+	usbc {
+		port1@1 {
+			usb-mux-chain-1 {
+				usb-muxes = <&virtual_mux_c1>;
+			};
+		};
+	};
+};
diff --git a/zephyr/test/drivers/usbc_svdm_dfp_only/prj.conf b/zephyr/test/drivers/usbc_svdm_dfp_only/prj.conf
new file mode 100644
index 0000000000..98cac2ca80
--- /dev/null
+++ b/zephyr/test/drivers/usbc_svdm_dfp_only/prj.conf
@@ -0,0 +1,8 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_BB=n
+CONFIG_PLATFORM_EC_USB_PD_USB4=n
+CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=n
+CONFIG_SVDM_RSP_DFP_ONLY=y
diff --git a/zephyr/test/drivers/usbc_svdm_dfp_only/src/usbc_svdm_dfp_only.c b/zephyr/test/drivers/usbc_svdm_dfp_only/src/usbc_svdm_dfp_only.c
new file mode 100644
index 0000000000..5e55042d33
--- /dev/null
+++ b/zephyr/test/drivers/usbc_svdm_dfp_only/src/usbc_svdm_dfp_only.c
@@ -0,0 +1,185 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * This test exercises the SVDM_RSP_DFP_ONLY option, causing the device to
+ * respond appropriately to SVDM Discover Identity requests when operating as
+ * DFP.
+ *
+ * The tests correspond to TEST.PD.PVDM.SRC.1 Discovery Process and Enter Mode
+ * as defined by the USB Power Delivery Compliance Test Specification.
+ */
+#include "emul/tcpc/emul_tcpci.h"
+#include "emul/tcpc/emul_tcpci_partner_common.h"
+#include "emul/tcpc/emul_tcpci_partner_src.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "usb_pd.h"
+
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/ztest.h>
+
+struct usbc_svdm_dfp_only_fixture {
+	const struct emul *tcpci_emul;
+	struct tcpci_partner_data partner;
+	const struct emul *charger_emul;
+	struct tcpci_src_emul_data src_emul_data;
+};
+
+struct identity_response {
+	uint16_t header;
+	uint32_t n_vdos;
+	uint32_t vdos[5];
+};
+
+/**
+ * Send a Discover Identity SVDM request from the emulated partner, returning
+ * the response and failing if the response has an unexpected type or size, or
+ * if too few PD messages are sent.
+ */
+static struct identity_response
+get_identity_response(struct usbc_svdm_dfp_only_fixture *fixture)
+{
+	uint32_t discover_identity[] = {
+		VDO(USB_SID_PD, 1,
+		    VDO_SVDM_VERS(VDM_VER20) | CMD_DISCOVER_IDENT),
+	};
+
+	/* Send a discover identity command from the partner */
+	tcpci_partner_common_clear_logged_msgs(&fixture->partner);
+	tcpci_partner_common_enable_pd_logging(&fixture->partner, true);
+	tcpci_partner_send_data_msg(&fixture->partner, PD_DATA_VENDOR_DEF,
+				    discover_identity,
+				    ARRAY_SIZE(discover_identity), 0);
+	k_sleep(K_SECONDS(1));
+	tcpci_partner_common_enable_pd_logging(&fixture->partner, false);
+
+	tcpci_partner_common_print_logged_msgs(&fixture->partner);
+
+	/* First message is the one we sent */
+	zassert_not_null(sys_slist_get(&fixture->partner.msg_log),
+			 "should have logged Discover_Identity request");
+	/* Second should be the response */
+	sys_snode_t *response_node = sys_slist_get(&fixture->partner.msg_log);
+
+	zassert_not_null(response_node, "should have logged a PD response");
+
+	struct tcpci_partner_log_msg *msg =
+		SYS_SLIST_CONTAINER(response_node, msg, node);
+	zassert_equal(msg->sop, TCPCI_MSG_SOP);
+
+	struct identity_response out;
+
+	out.header = sys_get_le16(msg->buf);
+	out.n_vdos = (msg->cnt - sizeof(out.header)) / sizeof(*out.vdos);
+	/*
+	 * Header size must agree with the actual message size and fit in the
+	 * vdos buffer.
+	 */
+	zassert_equal(PD_HEADER_CNT(out.header), out.n_vdos);
+	zassert_true(out.n_vdos <= ARRAY_SIZE(out.vdos),
+		     "response containing %d VDOs is too large", out.n_vdos);
+
+	for (int i = 0; i < out.n_vdos; i++) {
+		out.vdos[i] = sys_get_le32(
+			&msg->buf[sizeof(*out.vdos) * i + sizeof(out.header)]);
+	}
+
+	return out;
+}
+
+/**
+ * Verify that the header of the provided response describes a VDM response
+ * for the given PD version.
+ */
+static void verify_response_header(const struct identity_response response,
+				   enum pd_rev_type pd_rev)
+{
+	zassert_equal(PD_HEADER_TYPE(response.header), PD_DATA_VENDOR_DEF);
+	zassert_equal(PD_HEADER_REV(response.header), pd_rev);
+}
+
+ZTEST_F(usbc_svdm_dfp_only, test_verify_identity)
+{
+	fixture->partner.rev = PD_REV30;
+	connect_source_to_port(&fixture->partner, &fixture->src_emul_data, 0,
+			       fixture->tcpci_emul, fixture->charger_emul);
+
+	struct identity_response response = get_identity_response(fixture);
+
+	verify_response_header(response, PD_REV30);
+	zassert_equal(response.n_vdos, 5);
+
+	/* SVDM header: ACKing Discover_Identity */
+	zassert_equal(response.vdos[0],
+		      VDO(USB_SID_PD, 1,
+			  VDO_SVDM_VERS(1) | VDO_OPOS(0) |
+				  VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_IDENT),
+		      "VDM Header value unexpected: %#x", response.vdos[0]);
+	/* ID Header VDO per PD 3.0 */
+	zassert_equal(response.vdos[1],
+		      VDO_IDH_REV30(1 /* is a USB host */,
+				    0 /* not a USB device */,
+				    IDH_PTYPE_UNDEF /* not a UFP */,
+				    0 /* no modes supported */,
+				    IDH_PTYPE_DFP_HOST /* PDUSB host */,
+				    USB_TYPEC_RECEPTACLE, CONFIG_USB_VID));
+	/* Cert Stat VDO */
+	zassert_equal(response.vdos[2], CONFIG_USB_PD_XID,
+		      "Cert Stat VDO value unexpected: %#x", response.vdos[2]);
+	/* Product VDO */
+	zassert_equal(response.vdos[3],
+		      (CONFIG_USB_PID << 16) | CONFIG_USB_BCD_DEV,
+		      "Product VDO value unexpected: %#x", response.vdos[3]);
+	/* DFP Product Type VDO: version 1.1, USB3.2 capable, receptacle */
+	zassert_equal(response.vdos[4], 0x22800000,
+		      "DFP VDO had unexpected value %#x", response.vdos[4]);
+}
+
+ZTEST_F(usbc_svdm_dfp_only, test_verify_pd20_nak)
+{
+	fixture->partner.rev = PD_REV20;
+	connect_source_to_port(&fixture->partner, &fixture->src_emul_data, 0,
+			       fixture->tcpci_emul, fixture->charger_emul);
+
+	struct identity_response response = get_identity_response(fixture);
+
+	verify_response_header(response, PD_REV20);
+	/* In PD 2.0 DFPs are required to nack a Discover Identity request */
+	zassert_equal(response.n_vdos, 1);
+	zassert_equal(response.vdos[0],
+		      VDO(USB_SID_PD, 1,
+			  VDO_SVDM_VERS(0) | VDO_OPOS(0) |
+				  VDO_CMDT(CMDT_RSP_NAK) | CMD_DISCOVER_IDENT),
+		      "VDM Header value unexpected: %#x", response.vdos[0]);
+}
+
+static void *usbc_svdm_dfp_only_setup()
+{
+	static struct usbc_svdm_dfp_only_fixture fixture = {
+		.tcpci_emul = EMUL_DT_GET(DT_NODELABEL(tcpci_emul)),
+		.charger_emul = EMUL_DT_GET(DT_NODELABEL(isl923x_emul)),
+	};
+
+	tcpci_partner_init(&fixture.partner, PD_REV30);
+	fixture.partner.extensions = tcpci_src_emul_init(
+		&fixture.src_emul_data, &fixture.partner, NULL);
+	fixture.src_emul_data.pdo[0] =
+		PDO_FIXED(5000, 3000, PDO_FIXED_UNCONSTRAINED);
+
+	/* The first connect_source_to_port() fails if we don't do this */
+	test_set_chipset_to_s0();
+
+	return &fixture;
+}
+
+static void usbc_svdm_dfp_only_after(void *data)
+{
+	struct usbc_svdm_dfp_only_fixture *fixture = data;
+
+	disconnect_source_from_port(fixture->tcpci_emul, fixture->charger_emul);
+	tcpci_partner_common_clear_logged_msgs(&fixture->partner);
+}
+
+ZTEST_SUITE(usbc_svdm_dfp_only, drivers_predicate_post_main,
+	    usbc_svdm_dfp_only_setup, NULL, usbc_svdm_dfp_only_after, NULL);
diff --git a/zephyr/test/drivers/usbc_tbt_mode/CMakeLists.txt b/zephyr/test/drivers/usbc_tbt_mode/CMakeLists.txt
new file mode 100644
index 0000000000..05eddf9c69
--- /dev/null
+++ b/zephyr/test/drivers/usbc_tbt_mode/CMakeLists.txt
@@ -0,0 +1,5 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_sources(app PRIVATE src/usbc_tbt_mode.c)
diff --git a/zephyr/test/drivers/usbc_tbt_mode/src/usbc_tbt_mode.c b/zephyr/test/drivers/usbc_tbt_mode/src/usbc_tbt_mode.c
new file mode 100644
index 0000000000..38476eb36c
--- /dev/null
+++ b/zephyr/test/drivers/usbc_tbt_mode/src/usbc_tbt_mode.c
@@ -0,0 +1,337 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+#include "ec_tasks.h"
+#include "emul/emul_isl923x.h"
+#include "emul/tcpc/emul_ps8xxx.h"
+#include "emul/tcpc/emul_tcpci.h"
+#include "emul/tcpc/emul_tcpci_partner_snk.h"
+#include "host_command.h"
+#include "tcpm/tcpci.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "usb_pd_vdo.h"
+
+#include <stdint.h>
+
+#include <zephyr/kernel.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/ztest.h>
+
+#define TEST_PORT USBC_PORT_C0
+/* Remove polarity for any mux checks */
+#define USB_MUX_CHECK_MASK ~USB_PD_MUX_POLARITY_INVERTED
+
+struct usbc_tbt_mode_fixture {
+	const struct emul *tcpci_emul;
+	const struct emul *charger_emul;
+	struct tcpci_partner_data partner;
+	struct tcpci_snk_emul_data snk_ext;
+};
+
+/* Passive USB3 cable */
+struct tcpci_cable_data passive_usb3 = {
+	.identity_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_PD, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_IDENT),
+	.identity_vdm[VDO_INDEX_IDH] = VDO_IDH(
+		/* USB host */ false, /* USB device */ false, IDH_PTYPE_PCABLE,
+		/* modal operation */ false, USB_VID_GOOGLE),
+	.identity_vdm[VDO_INDEX_CSTAT] = 0,
+	.identity_vdm[VDO_INDEX_PRODUCT] = VDO_PRODUCT(0x1234, 0xABCD),
+	.identity_vdm[VDO_INDEX_PTYPE_CABLE1] =
+		VDO_REV30_PASSIVE(USB_R30_SS_U32_U40_GEN2, USB_VBUS_CUR_3A,
+				  USB_REV30_LATENCY_1m, USB_REV30_TYPE_C),
+	.identity_vdos = VDO_INDEX_PTYPE_CABLE1 + 1,
+
+};
+
+static void add_sop_vdm_responses(struct tcpci_partner_data *partner)
+{
+	/* Add Discover Identity response */
+	partner->identity_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_PD, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_IDENT);
+	partner->identity_vdm[VDO_INDEX_IDH] = VDO_IDH(
+		/* USB host */ false, /* USB device */ true, IDH_PTYPE_DFP_HUB,
+		/* modal operation */ true, USB_VID_GOOGLE);
+	partner->identity_vdm[VDO_INDEX_CSTAT] = 0;
+	partner->identity_vdm[VDO_INDEX_PRODUCT] = VDO_PRODUCT(0x1234, 0x5678);
+	partner->identity_vdm[VDO_INDEX_PTYPE_UFP1_VDO] = VDO_UFP1(
+		(VDO_UFP1_CAPABILITY_USB20 | VDO_UFP1_CAPABILITY_USB32),
+		USB_TYPEC_RECEPTACLE, VDO_UFP1_ALT_MODE_TBT3,
+		USB_R30_SS_U40_GEN3);
+	partner->identity_vdm[VDO_INDEX_PTYPE_UFP2_VDO] = 0;
+	partner->identity_vdos = VDO_INDEX_PTYPE_UFP2_VDO + 1;
+
+	/* Add Discover SVIDs response */
+	/* Support TBT (Intel) VID. */
+	partner->svids_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_PD, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_SVID);
+	partner->svids_vdm[VDO_INDEX_HDR + 1] = VDO_SVID(USB_VID_INTEL, 0);
+	partner->svids_vdos = VDO_INDEX_HDR + 2;
+
+	/* Add Discover Modes response */
+	/* Support one mode for TBT (Intel) VID */
+	partner->modes_vdm[VDO_INDEX_HDR] =
+		VDO(USB_VID_INTEL, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_MODES);
+	partner->modes_vdm[VDO_INDEX_HDR + 1] = TBT_ALTERNATE_MODE;
+	partner->modes_vdos = VDO_INDEX_HDR + 2;
+
+	/* Add affirmative mode entry */
+	partner->enter_mode_vdm[VDO_INDEX_HDR] =
+		VDO(USB_VID_INTEL, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_ENTER_MODE);
+	partner->enter_mode_vdos = VDO_INDEX_HDR + 1;
+}
+
+/* How many EnterModes were we expecting? */
+enum msg_check {
+	NO_MSG,
+	SOP_EXPECTED,
+};
+
+static void verify_vdm_messages(struct usbc_tbt_mode_fixture *fixture,
+				enum msg_check check, int cmd_type)
+{
+	struct tcpci_partner_log_msg *msg;
+	enum tcpci_msg_type types_seen[3];
+	int messages_seen = 0;
+
+	SYS_SLIST_FOR_EACH_CONTAINER(&fixture->partner.msg_log, msg, node)
+	{
+		uint16_t header = sys_get_le16(msg->buf);
+
+		/* Ignore messages from ourselves */
+		if (msg->sender == TCPCI_PARTNER_SENDER_PARTNER) {
+			continue;
+		}
+
+		/*
+		 * Control messages, non-VDMs, and extended messages are not of
+		 * interest
+		 */
+		if ((PD_HEADER_CNT(header) == 0) ||
+		    (PD_HEADER_TYPE(header) != PD_DATA_VENDOR_DEF) ||
+		    (PD_HEADER_EXT(header) != 0)) {
+			continue;
+		}
+
+		/* We have a VDM, check entry we're interested in */
+		uint32_t vdm_header = sys_get_le32(msg->buf + sizeof(header));
+
+		if (PD_VDO_CMD(vdm_header) != cmd_type) {
+			continue;
+		}
+
+		types_seen[messages_seen] = PD_HEADER_GET_SOP(header);
+		messages_seen++;
+	}
+
+	/*
+	 * Processing done, now verify message ordering.  See Type-C
+	 * specification 6.7 Active Cables That Support Alternate Modes
+	 */
+	if (check == NO_MSG) {
+		zassert_equal(messages_seen, 0,
+			      "Unexpected messages (cmd %d, num %d)", cmd_type,
+			      messages_seen);
+	} else if (check == SOP_EXPECTED) {
+		zassert_equal(messages_seen, 1,
+			      "Unexpected messages (cmd %d, num %d)", cmd_type,
+			      messages_seen);
+		zassert_equal(types_seen[0], TCPCI_MSG_SOP,
+			      "Unexpected SOP type: %d", types_seen[0]);
+	}
+}
+
+static void verify_cable_found(struct tcpci_cable_data *cable)
+{
+	uint8_t response_buffer[EC_LPC_HOST_PACKET_SIZE];
+	struct ec_response_typec_discovery *discovery =
+		(struct ec_response_typec_discovery *)response_buffer;
+
+	host_cmd_typec_discovery(TEST_PORT, TYPEC_PARTNER_SOP_PRIME,
+				 response_buffer, sizeof(response_buffer));
+
+	/* The host command does not count the VDM header in identity_count. */
+	zassert_equal(discovery->identity_count, cable->identity_vdos - 1,
+		      "Expected %d identity VDOs, got %d",
+		      cable->identity_vdos - 1, discovery->identity_count);
+	zassert_mem_equal(discovery->discovery_vdo, cable->identity_vdm + 1,
+			  discovery->identity_count *
+				  sizeof(*discovery->discovery_vdo),
+			  "Discovered SOP' identity ACK did not match");
+}
+
+static void *usbc_tbt_mode_setup(void)
+{
+	static struct usbc_tbt_mode_fixture fixture;
+	struct tcpci_partner_data *partner = &fixture.partner;
+	struct tcpci_snk_emul_data *snk_ext = &fixture.snk_ext;
+
+	tcpci_partner_init(partner, PD_REV30);
+	partner->extensions = tcpci_snk_emul_init(snk_ext, partner, NULL);
+
+	/* Get references for the emulators */
+	fixture.tcpci_emul = EMUL_DT_GET(DT_NODELABEL(tcpci_emul));
+	fixture.charger_emul = EMUL_DT_GET(DT_NODELABEL(isl923x_emul));
+
+	add_sop_vdm_responses(partner);
+	/* Note: cable behavior will vary by test case */
+
+	/* Sink 5V 3A. */
+	snk_ext->pdo[0] = PDO_FIXED(5000, 3000, PDO_FIXED_COMM_CAP);
+
+	return &fixture;
+}
+
+static void usbc_tbt_mode_before(void *data)
+{
+	ARG_UNUSED(data);
+
+	/* Set chipset to ON, this will set TCPM to DRP */
+	test_set_chipset_to_s0();
+
+	/* TODO(b/214401892): Check why need to give time TCPM to spin */
+	k_sleep(K_SECONDS(1));
+}
+
+static void usbc_tbt_mode_after(void *data)
+{
+	struct usbc_tbt_mode_fixture *fix = data;
+
+	disconnect_sink_from_port(fix->tcpci_emul);
+	tcpci_partner_common_clear_logged_msgs(&fix->partner);
+}
+
+ZTEST_F(usbc_tbt_mode, test_verify_discovery)
+{
+	uint8_t response_buffer[EC_LPC_HOST_PACKET_SIZE];
+	struct ec_response_typec_discovery *discovery =
+		(struct ec_response_typec_discovery *)response_buffer;
+
+	connect_sink_to_port(&fixture->partner, fixture->tcpci_emul,
+			     fixture->charger_emul);
+
+	host_cmd_typec_discovery(TEST_PORT, TYPEC_PARTNER_SOP, response_buffer,
+				 sizeof(response_buffer));
+
+	/* The host command does not count the VDM header in identity_count. */
+	zassert_equal(discovery->identity_count,
+		      fixture->partner.identity_vdos - 1,
+		      "Expected %d identity VDOs, got %d",
+		      fixture->partner.identity_vdos - 1,
+		      discovery->identity_count);
+	zassert_mem_equal(
+		discovery->discovery_vdo, fixture->partner.identity_vdm + 1,
+		discovery->identity_count * sizeof(*discovery->discovery_vdo),
+		"Discovered SOP identity ACK did not match");
+	zassert_equal(discovery->svid_count, 1, "Expected 1 SVID, got %d",
+		      discovery->svid_count);
+	zassert_equal(discovery->svids[0].svid, USB_VID_INTEL,
+		      "Expected SVID 0x%04x, got 0x%04x", USB_VID_INTEL,
+		      discovery->svids[0].svid);
+	zassert_equal(discovery->svids[0].mode_count, 1,
+		      "Expected 1 TBT mode, got %d",
+		      discovery->svids[0].mode_count);
+	zassert_equal(discovery->svids[0].mode_vdo[0],
+		      fixture->partner.modes_vdm[1],
+		      "TBT mode VDOs did not match");
+}
+
+/* Without an e-marked cable, TBT mode cannot be entered */
+ZTEST_F(usbc_tbt_mode, test_verify_tbt_entry_fail)
+{
+	struct ec_response_typec_status status;
+
+	fixture->partner.cable = NULL;
+	connect_sink_to_port(&fixture->partner, fixture->tcpci_emul,
+			     fixture->charger_emul);
+
+	status = host_cmd_typec_status(TEST_PORT);
+	zassert_equal((status.mux_state & USB_MUX_CHECK_MASK),
+		      USB_PD_MUX_USB_ENABLED, "Unexpected starting mux: 0x%02x",
+		      status.mux_state);
+
+	/* TODO(b/237553647): Test EC-driven mode entry (requires a separate
+	 * config).
+	 */
+	tcpci_partner_common_enable_pd_logging(&fixture->partner, true);
+	host_cmd_typec_control_enter_mode(TEST_PORT, TYPEC_MODE_TBT);
+	k_sleep(K_SECONDS(1));
+
+	/*
+	 * TODO(b/168030639): Notify the AP that the enter mode request
+	 * failed.
+	 */
+
+	/* Verify we refrained from sending TBT EnterMode. */
+	tcpci_partner_common_enable_pd_logging(&fixture->partner, false);
+	verify_vdm_messages(fixture, NO_MSG, CMD_ENTER_MODE);
+
+	status = host_cmd_typec_status(TEST_PORT);
+	zassert_equal((status.mux_state & USB_MUX_CHECK_MASK),
+		      USB_PD_MUX_USB_ENABLED, "Failed to see USB still set");
+	zassert_not_equal((status.mux_state & USB_MUX_CHECK_MASK),
+			  USB_PD_MUX_TBT_COMPAT_ENABLED,
+			  "Unexpected TBT mode set");
+}
+
+/* With passive e-marked cable, TBT mode can be entered on SOP only */
+ZTEST_F(usbc_tbt_mode, test_verify_tbt_passive_entry_exit)
+{
+	struct ec_response_typec_status status;
+
+	fixture->partner.cable = &passive_usb3;
+	connect_sink_to_port(&fixture->partner, fixture->tcpci_emul,
+			     fixture->charger_emul);
+
+	verify_cable_found(fixture->partner.cable);
+
+	status = host_cmd_typec_status(TEST_PORT);
+	zassert_equal((status.mux_state & USB_MUX_CHECK_MASK),
+		      USB_PD_MUX_USB_ENABLED, "Unexpected starting mux: 0x%02x",
+		      status.mux_state);
+
+	/* TODO(b/237553647): Test EC-driven mode entry (requires a separate
+	 * config).
+	 */
+	tcpci_partner_common_enable_pd_logging(&fixture->partner, true);
+	host_cmd_typec_control_enter_mode(TEST_PORT, TYPEC_MODE_TBT);
+	k_sleep(K_SECONDS(1));
+
+	/*
+	 * TODO(b/168030639): Notify the AP that the enter mode request
+	 * succeeded.
+	 */
+
+	/* Verify we sent a single TBT SOP EnterMode. */
+	tcpci_partner_common_enable_pd_logging(&fixture->partner, false);
+	verify_vdm_messages(fixture, SOP_EXPECTED, CMD_ENTER_MODE);
+	status = host_cmd_typec_status(TEST_PORT);
+	zassert_equal((status.mux_state & USB_MUX_CHECK_MASK),
+		      USB_PD_MUX_TBT_COMPAT_ENABLED, "Failed to see TBT set");
+
+	/* Exit modes now */
+	tcpci_partner_common_clear_logged_msgs(&fixture->partner);
+	tcpci_partner_common_enable_pd_logging(&fixture->partner, true);
+	host_cmd_typec_control_exit_modes(TEST_PORT);
+	k_sleep(K_SECONDS(1));
+
+	/* Verify we sent a single TBT SOP ExitMode. */
+	tcpci_partner_common_enable_pd_logging(&fixture->partner, false);
+	verify_vdm_messages(fixture, SOP_EXPECTED, CMD_EXIT_MODE);
+	status = host_cmd_typec_status(TEST_PORT);
+	zassert_equal((status.mux_state & USB_MUX_CHECK_MASK),
+		      USB_PD_MUX_USB_ENABLED, "Failed to see USB set");
+}
+
+ZTEST_SUITE(usbc_tbt_mode, drivers_predicate_post_main, usbc_tbt_mode_setup,
+	    usbc_tbt_mode_before, usbc_tbt_mode_after, NULL);
diff --git a/zephyr/test/drivers/usbc_tcpc/CMakeLists.txt b/zephyr/test/drivers/usbc_tcpc/CMakeLists.txt
new file mode 100644
index 0000000000..3a6d12cdd6
--- /dev/null
+++ b/zephyr/test/drivers/usbc_tcpc/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Add source files
+target_sources(app PRIVATE src/tcpc_shim.c)
diff --git a/zephyr/test/drivers/usbc_tcpc/src/tcpc_shim.c b/zephyr/test/drivers/usbc_tcpc/src/tcpc_shim.c
new file mode 100644
index 0000000000..a947682a11
--- /dev/null
+++ b/zephyr/test/drivers/usbc_tcpc/src/tcpc_shim.c
@@ -0,0 +1,64 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "usbc/tcpci.h"
+
+#include <zephyr/logging/log.h>
+#include <zephyr/ztest.h>
+
+LOG_MODULE_REGISTER(test_drivers_tcpc, LOG_LEVEL_DBG);
+
+#define TCPC_CHIP_STUB(node_id) {},
+
+static struct tcpc_config_t tcpc_config_saved[] = { DT_FOREACH_STATUS_OKAY(
+	named_usbc_port, TCPC_CHIP_STUB) };
+
+ZTEST(tcpc_shim, test_tcpc_alts_exist)
+{
+	/* Verify all TCPC types are able to create an alternate TCPC entry */
+	zassert_not_null(&TCPC_ALT_FROM_NODELABEL(tcpc_anx7447_alt));
+	zassert_not_null(&TCPC_ALT_FROM_NODELABEL(tcpc_ccgxxf_alt));
+	zassert_not_null(&TCPC_ALT_FROM_NODELABEL(tcpc_fusb302_alt));
+	zassert_not_null(&TCPC_ALT_FROM_NODELABEL(tcpc_ps8xxx_alt));
+	zassert_not_null(&TCPC_ALT_FROM_NODELABEL(tcpc_raa489000_alt));
+	zassert_not_null(&TCPC_ALT_FROM_NODELABEL(tcpc_nct38xx_alt));
+	zassert_not_null(&TCPC_ALT_FROM_NODELABEL(tcpc_rt1715_alt));
+	zassert_not_null(&TCPC_ALT_FROM_NODELABEL(tcpc_rt1718s_alt));
+	zassert_not_null(&TCPC_ALT_FROM_NODELABEL(tcpc_alt));
+}
+
+ZTEST(tcpc_shim, test_tcpc_alt_enable)
+{
+	/* Enable an alternate TCPC on each USB-C port */
+	TCPC_ENABLE_ALTERNATE_BY_NODELABEL(0, tcpc_ps8xxx_alt);
+	TCPC_ENABLE_ALTERNATE_BY_NODELABEL(1, tcpc_rt1715_alt);
+
+	zassert_mem_equal(&tcpc_config[0],
+			  &TCPC_ALT_FROM_NODELABEL(tcpc_ps8xxx_alt),
+			  sizeof(struct tcpc_config_t));
+	zassert_mem_equal(&tcpc_config[1],
+			  &TCPC_ALT_FROM_NODELABEL(tcpc_rt1715_alt),
+			  sizeof(struct tcpc_config_t));
+
+	TCPC_ENABLE_ALTERNATE_BY_NODELABEL(0, tcpc_anx7447_alt);
+	zassert_mem_equal(&tcpc_config[0],
+			  &TCPC_ALT_FROM_NODELABEL(tcpc_anx7447_alt),
+			  sizeof(struct tcpc_config_t));
+}
+
+void tcpc_shim_before_test(void *data)
+{
+	memcpy(tcpc_config_saved, tcpc_config,
+	       sizeof(struct tcpc_config_t) * ARRAY_SIZE(tcpc_config_saved));
+}
+
+void tcpc_shim_after_test(void *data)
+{
+	memcpy(tcpc_config, tcpc_config_saved,
+	       sizeof(struct tcpc_config_t) * ARRAY_SIZE(tcpc_config_saved));
+}
+
+ZTEST_SUITE(tcpc_shim, NULL, NULL, tcpc_shim_before_test, tcpc_shim_after_test,
+	    NULL);
diff --git a/zephyr/test/drivers/usbc_tcpc/tcpc_alts.dts b/zephyr/test/drivers/usbc_tcpc/tcpc_alts.dts
new file mode 100644
index 0000000000..903fdf18d9
--- /dev/null
+++ b/zephyr/test/drivers/usbc_tcpc/tcpc_alts.dts
@@ -0,0 +1,88 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+ /* Define nodes with the "is-alt" property set. Used by the TCPC shim
+  * test to validate the runtime replacement of the TCPC driver.
+  */
+
+#include <dt-bindings/usb_pd_tcpm.h>
+
+&i2c0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	tcpc_anx7447_alt: tcpc-anx7447-alt@2c {
+		compatible = "analogix,anx7447-tcpc", "cros,i2c-mock";
+		reg = <0x2c>;
+		tcpc-flags = <(
+			TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_VBUS_MONITOR)>;
+		is-alt;
+	};
+
+	tcpc_ccgxxf_alt: tcpc-ccgxxf-alt@11 {
+		compatible = "cypress,ccgxxf", "cros,i2c-mock";
+		reg = <0x11>;
+		is-alt;
+	};
+
+	tcpc_fusb302_alt: tcpc-fusb302-alt@22 {
+		compatible = "fairchild,fusb302", "cros,i2c-mock";
+		reg = <0x22>;
+		is-alt;
+	};
+
+	tcpc_ps8xxx_alt: tcpc-ps8xxx-alt@b {
+		compatible = "parade,ps8xxx", "cros,i2c-mock";
+		reg = < 0xb >;
+		tcpc-flags = < 0xd8 >;
+		is-alt;
+	};
+
+	tcpc_raa489000_alt: tcpc-raa489000-alt@e {
+		compatible = "renesas,raa489000", "cros,i2c-mock";
+		reg = <0xe>;
+		tcpc-flags = <(
+			TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_VBUS_MONITOR)>;
+		is-alt;
+	};
+
+	tcpc_nct38xx_alt: tcpc-nct38xx-alt@73 {
+		compatible = "nuvoton,nct38xx";
+		reg = <0x73>;
+		tcpc-flags = <(
+			TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_NO_DEBUG_ACC_CONTROL)>;
+		is-alt;
+	};
+
+
+	tcpc_rt1715_alt: tcpc-rt1715-alt@a{
+		compatible = "richtek,rt1715-tcpc", "cros,i2c-mock";
+		reg = <0xa>;
+		tcpc-flags = <(
+			TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_VBUS_MONITOR)>;
+		is-alt;
+	};
+
+	tcpc_rt1718s_alt: tcpc-rt1718s-alt@40 {
+		compatible = "richtek,rt1718s-tcpc", "cros,i2c-mock";
+		reg = <0x40>;
+		tcpc-flags = <(
+			TCPC_FLAGS_ALERT_OD |
+			TCPC_FLAGS_CONTROL_VCONN |
+			TCPC_FLAGS_CONTROL_FRS)>;
+		is-alt;
+	};
+
+	tcpc_alt: tcpc-alt@41 {
+		compatible = "cros-ec,tcpci", "cros,i2c-mock";
+		reg = <0x41>;
+		is-alt;
+	};
+};
diff --git a/zephyr/test/drivers/usbc_usb4_mode/CMakeLists.txt b/zephyr/test/drivers/usbc_usb4_mode/CMakeLists.txt
new file mode 100644
index 0000000000..dcf03ae2f6
--- /dev/null
+++ b/zephyr/test/drivers/usbc_usb4_mode/CMakeLists.txt
@@ -0,0 +1,5 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_sources(app PRIVATE src/usbc_usb4_mode.c)
diff --git a/zephyr/test/drivers/usbc_usb4_mode/src/usbc_usb4_mode.c b/zephyr/test/drivers/usbc_usb4_mode/src/usbc_usb4_mode.c
new file mode 100644
index 0000000000..25fcff61e1
--- /dev/null
+++ b/zephyr/test/drivers/usbc_usb4_mode/src/usbc_usb4_mode.c
@@ -0,0 +1,307 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+#include "ec_tasks.h"
+#include "emul/tcpc/emul_tcpci.h"
+#include "emul/tcpc/emul_tcpci_partner_snk.h"
+#include "host_command.h"
+#include "tcpm/tcpci.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "usb_pd_vdo.h"
+
+#include <stdint.h>
+
+#include <zephyr/kernel.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/ztest.h>
+
+#define TEST_PORT USBC_PORT_C0
+/* Remove polarity for any mux checks */
+#define USB_MUX_CHECK_MASK ~USB_PD_MUX_POLARITY_INVERTED
+
+struct usbc_usb4_mode_fixture {
+	const struct emul *tcpci_emul;
+	const struct emul *charger_emul;
+	struct tcpci_partner_data partner;
+	struct tcpci_snk_emul_data snk_ext;
+};
+
+/* Passive USB4 cable */
+struct tcpci_cable_data passive_usb4 = {
+	.identity_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_PD, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_IDENT),
+	.identity_vdm[VDO_INDEX_IDH] = VDO_IDH(
+		/* USB host */ false, /* USB device */ false, IDH_PTYPE_PCABLE,
+		/* modal operation */ false, USB_VID_GOOGLE),
+	.identity_vdm[VDO_INDEX_CSTAT] = 0,
+	.identity_vdm[VDO_INDEX_PRODUCT] = VDO_PRODUCT(0x1234, 0xABCD),
+	.identity_vdm[VDO_INDEX_PTYPE_CABLE1] =
+		VDO_REV30_PASSIVE(USB_R30_SS_U40_GEN3, USB_VBUS_CUR_3A,
+				  USB_REV30_LATENCY_1m, USB_REV30_TYPE_C),
+	.identity_vdos = VDO_INDEX_PTYPE_CABLE1 + 1,
+
+};
+
+static void add_sop_vdm_responses(struct tcpci_partner_data *partner)
+{
+	/* Add Discover Identity response */
+	partner->identity_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_PD, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_IDENT);
+	partner->identity_vdm[VDO_INDEX_IDH] = VDO_IDH_REV30(
+		/* USB host */ false, /* USB device */ true,
+		/* ptype_u */ IDH_PTYPE_HUB, /* modal */ false,
+		/* ptype_d */ IDH_PTYPE_UNDEF, /* ctype */ USB_TYPEC_RECEPTACLE,
+		USB_VID_GOOGLE);
+	partner->identity_vdm[VDO_INDEX_CSTAT] = 0;
+	partner->identity_vdm[VDO_INDEX_PRODUCT] = VDO_PRODUCT(0x1234, 0x5678);
+	partner->identity_vdm[VDO_INDEX_PTYPE_UFP1_VDO] = VDO_UFP1(
+		/* capability */ (VDO_UFP1_CAPABILITY_USB20 |
+				  VDO_UFP1_CAPABILITY_USB32 |
+				  VDO_UFP1_CAPABILITY_USB4),
+		/* ctype */ USB_TYPEC_RECEPTACLE,
+		/* alt modes */ VDO_UFP1_ALT_MODE_TBT3,
+		/* speed */ USB_R30_SS_U40_GEN3);
+	partner->identity_vdm[VDO_INDEX_PTYPE_UFP2_VDO] = 0;
+	partner->identity_vdos = VDO_INDEX_PTYPE_UFP2_VDO + 1;
+
+	/* Add Discover SVIDs response */
+	/*
+	 * TODO(b/260095516): USB4 entry does not depend on the contents of
+	 * Discover SVIDs, but a valid Discover SVID response needs to to exist
+	 * to ensure that discovery completes as that's a dependency in the DPM
+	 * module to attempt either Enter_USB or DATA_RESET.
+	 */
+	partner->svids_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_PD, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_SVID);
+	partner->svids_vdm[VDO_INDEX_HDR + 1] = VDO_SVID(USB_VID_INTEL, 0);
+	partner->svids_vdos = VDO_INDEX_HDR + 2;
+
+	/* Add Discover Modes response */
+	/*
+	 * TODO(b/260095516): USB4 entry does not depend on the contents of
+	 * Discover Modes, but a valid Discover Modes response needs to to exist
+	 * to ensure that discovery completes as that's a dependency in the DPM
+	 * module to attempt either Enter_USB or DATA_RESET.
+	 */
+	/* Support one mode for TBT (Intel) VID */
+	partner->modes_vdm[VDO_INDEX_HDR] =
+		VDO(USB_VID_INTEL, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_MODES);
+	partner->modes_vdm[VDO_INDEX_HDR + 1] = TBT_ALTERNATE_MODE;
+	partner->modes_vdos = VDO_INDEX_HDR + 2;
+}
+
+static void verify_cable_found(struct tcpci_cable_data *cable)
+{
+	uint8_t response_buffer[EC_LPC_HOST_PACKET_SIZE];
+	struct ec_response_typec_discovery *discovery =
+		(struct ec_response_typec_discovery *)response_buffer;
+
+	host_cmd_typec_discovery(TEST_PORT, TYPEC_PARTNER_SOP_PRIME,
+				 response_buffer, sizeof(response_buffer));
+
+	/* The host command does not count the VDM header in identity_count. */
+	zassert_equal(discovery->identity_count, cable->identity_vdos - 1,
+		      "Expected %d identity VDOs, got %d",
+		      cable->identity_vdos - 1, discovery->identity_count);
+	zassert_mem_equal(discovery->discovery_vdo, cable->identity_vdm + 1,
+			  discovery->identity_count *
+				  sizeof(*discovery->discovery_vdo),
+			  "Discovered SOP' identity ACK did not match");
+}
+
+static void *usbc_usb4_mode_setup(void)
+{
+	static struct usbc_usb4_mode_fixture fixture;
+	struct tcpci_partner_data *partner = &fixture.partner;
+	struct tcpci_snk_emul_data *snk_ext = &fixture.snk_ext;
+
+	tcpci_partner_init(partner, PD_REV30);
+	partner->extensions = tcpci_snk_emul_init(snk_ext, partner, NULL);
+
+	/* Get references for the emulators */
+	fixture.tcpci_emul = EMUL_DT_GET(DT_NODELABEL(tcpci_emul));
+	fixture.charger_emul = EMUL_DT_GET(DT_NODELABEL(isl923x_emul));
+
+	add_sop_vdm_responses(partner);
+	/* Note: cable behavior will vary by test case */
+
+	return &fixture;
+}
+
+static void usbc_usb4_mode_before(void *data)
+{
+	struct usbc_usb4_mode_fixture *fix = data;
+
+	/* Set chipset to ON, this will set TCPM to DRP */
+	test_set_chipset_to_s0();
+
+	/* TODO(b/214401892): Check why need to give TCPM time to spin */
+	k_sleep(K_SECONDS(1));
+
+	/* Enable message logging after TCPM spin */
+	tcpci_partner_common_enable_pd_logging(&fix->partner, true);
+
+	/* Initialize parter port Enter_USB msg accept/reject state */
+	fix->partner.enter_usb_accept = false;
+}
+
+static void usbc_usb4_mode_after(void *data)
+{
+	struct usbc_usb4_mode_fixture *fix = data;
+
+	disconnect_sink_from_port(fix->tcpci_emul);
+	tcpci_partner_common_enable_pd_logging(&fix->partner, false);
+	tcpci_partner_common_clear_logged_msgs(&fix->partner);
+}
+
+ZTEST_F(usbc_usb4_mode, test_verify_discovery)
+{
+	uint8_t response_buffer[EC_LPC_HOST_PACKET_SIZE];
+	struct ec_response_typec_discovery *discovery =
+		(struct ec_response_typec_discovery *)response_buffer;
+
+	connect_sink_to_port(&fixture->partner, fixture->tcpci_emul,
+			     fixture->charger_emul);
+
+	host_cmd_typec_discovery(TEST_PORT, TYPEC_PARTNER_SOP, response_buffer,
+				 sizeof(response_buffer));
+
+	/* The host command does not count the VDM header in identity_count. */
+	zassert_equal(discovery->identity_count,
+		      fixture->partner.identity_vdos - 1,
+		      "Expected %d identity VDOs, got %d",
+		      fixture->partner.identity_vdos - 1,
+		      discovery->identity_count);
+	zassert_mem_equal(
+		discovery->discovery_vdo, fixture->partner.identity_vdm + 1,
+		discovery->identity_count * sizeof(*discovery->discovery_vdo),
+		"Discovered SOP identity ACK did not match");
+}
+
+/* Without an e-marked cable, USB4 mode cannot be entered */
+ZTEST_F(usbc_usb4_mode, test_verify_usb4_entry_fail)
+{
+	struct ec_response_typec_status status;
+
+	fixture->partner.cable = NULL;
+	connect_sink_to_port(&fixture->partner, fixture->tcpci_emul,
+			     fixture->charger_emul);
+
+	status = host_cmd_typec_status(TEST_PORT);
+	zassert_equal((status.mux_state & USB_MUX_CHECK_MASK),
+		      USB_PD_MUX_USB_ENABLED, "Unexpected starting mux: 0x%02x",
+		      status.mux_state);
+
+	host_cmd_typec_control_enter_mode(TEST_PORT, TYPEC_MODE_USB4);
+	k_sleep(K_SECONDS(1));
+
+	/*
+	 * TODO(b/260095516): Notify the AP that the enter mode request
+	 * failed.
+	 */
+
+	status = host_cmd_typec_status(TEST_PORT);
+	zassert_equal((status.mux_state & USB_MUX_CHECK_MASK),
+		      USB_PD_MUX_USB_ENABLED, "Failed to see USB still set");
+	zassert_not_equal((status.mux_state & USB_MUX_CHECK_MASK),
+			  USB_PD_MUX_USB4_ENABLED, "Unexpected USB4 mode set");
+}
+
+/* With passive e-marked cable, USB4 mode can be entered on SOP only */
+ZTEST_F(usbc_usb4_mode, test_verify_usb4_passive_entry_exit)
+{
+	struct ec_response_typec_status status;
+
+	fixture->partner.cable = &passive_usb4;
+	connect_sink_to_port(&fixture->partner, fixture->tcpci_emul,
+			     fixture->charger_emul);
+
+	/* Instruct partner port to accept Enter_USB message */
+	fixture->partner.enter_usb_accept = true;
+
+	/* Verify that we properly identify a USB4 capable passive cable */
+	verify_cable_found(fixture->partner.cable);
+
+	status = host_cmd_typec_status(TEST_PORT);
+	zassert_equal((status.mux_state & USB_MUX_CHECK_MASK),
+		      USB_PD_MUX_USB_ENABLED, "Unexpected starting mux: 0x%02x",
+		      status.mux_state);
+
+	host_cmd_typec_control_enter_mode(TEST_PORT, TYPEC_MODE_USB4);
+	k_sleep(K_SECONDS(2));
+
+	/*
+	 * TODO(b/260095516): Notify the AP that the enter mode request
+	 * succeeded.
+	 */
+
+	/* Verify we entered USB4 mode */
+	status = host_cmd_typec_status(TEST_PORT);
+	zassert_equal((status.mux_state & USB_MUX_CHECK_MASK),
+		      USB_PD_MUX_USB4_ENABLED, "Failed to see USB4 set");
+
+	/* Exit modes now */
+	host_cmd_typec_control_exit_modes(TEST_PORT);
+	k_sleep(K_SECONDS(1));
+
+	/* Verify that USB4 mode was exited by checking current mux state. */
+	status = host_cmd_typec_status(TEST_PORT);
+	zassert_equal((status.mux_state & USB_MUX_CHECK_MASK),
+		      USB_PD_MUX_USB_ENABLED, "Failed to see USB set");
+}
+
+/* If the partner claims to support USB4, but communication is only PD 2.0, the
+ * EC should disregard a request to enter USB4 from the host.
+ */
+ZTEST_F(usbc_usb4_mode, test_verify_usb4_pd2_no_entry)
+{
+	struct ec_response_typec_status status;
+
+	tcpci_partner_init(&fixture->partner, PD_REV20);
+	fixture->partner.cable = &passive_usb4;
+	connect_sink_to_port(&fixture->partner, fixture->tcpci_emul,
+			     fixture->charger_emul);
+
+	/* Instruct partner port to accept Enter_USB message */
+	fixture->partner.enter_usb_accept = true;
+
+	/* Verify that we properly identify a USB4 capable passive cable */
+	verify_cable_found(fixture->partner.cable);
+
+	status = host_cmd_typec_status(TEST_PORT);
+	zassert_equal((status.mux_state & USB_MUX_CHECK_MASK),
+		      USB_PD_MUX_USB_ENABLED, "Unexpected starting mux: 0x%02x",
+		      status.mux_state);
+
+	host_cmd_typec_control_enter_mode(TEST_PORT, TYPEC_MODE_USB4);
+	k_sleep(K_SECONDS(1));
+
+	/* PD 2.0 doesn't include Enter_USB, so it's not possible to enter USB4
+	 * mode. A Discover Identity ACK indicating support for USB4 isn't even
+	 * valid under PD 2.0. If the host nevertheless commands the EC to enter
+	 * USB4, the EC should not attempt to do so.
+	 */
+	status = host_cmd_typec_status(TEST_PORT);
+	zassert_equal((status.mux_state & USB_MUX_CHECK_MASK),
+		      USB_PD_MUX_USB_ENABLED, "Failed to see USB still set");
+	zassert_not_equal((status.mux_state & USB_MUX_CHECK_MASK),
+			  USB_PD_MUX_USB4_ENABLED, "Unexpected USB4 mode set");
+}
+
+/*
+ * TODO(b/260095516): This test suite is only testing the default good case, and
+ * one error case where the cable doesn't support USB4. This suite needs to be
+ * expanded to cover cases where the port partner rejects Enter_USB along with
+ * active cable cases.
+ */
+ZTEST_SUITE(usbc_usb4_mode, drivers_predicate_post_main, usbc_usb4_mode_setup,
+	    usbc_usb4_mode_before, usbc_usb4_mode_after, NULL);
diff --git a/zephyr/test/drivers/usbc_vconn_swap/CMakeLists.txt b/zephyr/test/drivers/usbc_vconn_swap/CMakeLists.txt
new file mode 100644
index 0000000000..78c97ce952
--- /dev/null
+++ b/zephyr/test/drivers/usbc_vconn_swap/CMakeLists.txt
@@ -0,0 +1,7 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_include_directories(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/include)
+
+target_sources(app PRIVATE src/usbc_vconn_swap.c)
diff --git a/zephyr/test/drivers/usbc_vconn_swap/include/usbc_vconn_swap.h b/zephyr/test/drivers/usbc_vconn_swap/include/usbc_vconn_swap.h
new file mode 100644
index 0000000000..83c88c4f6c
--- /dev/null
+++ b/zephyr/test/drivers/usbc_vconn_swap/include/usbc_vconn_swap.h
@@ -0,0 +1,14 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef ZEPHYR_TEST_DRIVERS_USBC_VCONN_SWAP_USBC_VCONN_SWAP_H_
+#define ZEPHYR_TEST_DRIVERS_USBC_VCONN_SWAP_USBC_VCONN_SWAP_H_
+
+#include "compile_time_macros.h"
+#include "emul/tcpc/emul_tcpci.h"
+#include "emul/tcpc/emul_tcpci_partner_snk.h"
+#include "test/drivers/stubs.h"
+
+#endif /* ZEPHYR_TEST_DRIVERS_USBC_VCONN_SWAP_USBC_VCONN_SWAP_H_ */
diff --git a/zephyr/test/drivers/usbc_vconn_swap/src/usbc_vconn_swap.c b/zephyr/test/drivers/usbc_vconn_swap/src/usbc_vconn_swap.c
new file mode 100644
index 0000000000..ab5a33e0dd
--- /dev/null
+++ b/zephyr/test/drivers/usbc_vconn_swap/src/usbc_vconn_swap.c
@@ -0,0 +1,313 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+#include "ec_tasks.h"
+#include "emul/emul_isl923x.h"
+#include "emul/tcpc/emul_ps8xxx.h"
+#include "emul/tcpc/emul_tcpci.h"
+#include "emul/tcpc/emul_tcpci_partner_common.h"
+#include "emul/tcpc/emul_tcpci_partner_drp.h"
+#include "emul/tcpc/emul_tcpci_partner_snk.h"
+#include "host_command.h"
+#include "tcpm/tcpci.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "usb_tc_sm.h"
+
+#include <stdint.h>
+
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/fff.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+#define TEST_PORT 0
+
+FAKE_VALUE_FUNC(bool, port_discovery_vconn_swap_policy, int, bool);
+
+/* This is the same as the real function. */
+static bool port_discovery_vconn_swap_policy_custom(int port,
+						    bool vconn_swap_flag)
+{
+	if (IS_ENABLED(CONFIG_USBC_VCONN) && vconn_swap_flag &&
+	    !tc_is_vconn_src(port) && tc_check_vconn_swap(port))
+		return true;
+
+	/* Do not perform a VCONN swap */
+	return false;
+}
+
+static bool port_discovery_vconn_swap_policy_nope(int port,
+						  bool vconn_swap_flag)
+{
+	return false;
+}
+
+struct common_fixture {
+	const struct emul *tcpci_emul;
+	const struct emul *charger_emul;
+	struct tcpci_partner_data partner;
+	struct tcpci_snk_emul_data snk_ext;
+	struct tcpci_src_emul_data src_ext;
+	struct tcpci_drp_emul_data drp_ext;
+};
+
+struct usbc_vconn_swap_fixture {
+	struct common_fixture common;
+};
+
+struct usbc_vconn_swap_late_fixture {
+	struct common_fixture common;
+};
+
+struct usbc_vconn_swap_not_supported_fixture {
+	struct common_fixture common;
+};
+
+struct usbc_vconn_swap_reject_fixture {
+	struct common_fixture common;
+};
+
+static void connect_partner_to_port(const struct emul *tcpc_emul,
+				    const struct emul *charger_emul,
+				    struct tcpci_partner_data *partner_emul,
+				    const struct tcpci_src_emul_data *src_ext)
+{
+	/*
+	 * TODO(b/221439302): Updating the TCPCI emulator registers, updating
+	 * the charger, and alerting should all be a part of the connect
+	 * function.
+	 */
+	set_ac_enabled(true);
+	zassert_ok(tcpci_partner_connect_to_tcpci(partner_emul, tcpc_emul),
+		   NULL);
+
+	isl923x_emul_set_adc_vbus(charger_emul,
+				  PDO_FIXED_GET_VOLT(src_ext->pdo[0]));
+
+	/* Wait for PD negotiation and current ramp. */
+	k_sleep(K_SECONDS(10));
+}
+
+static void disconnect_partner_from_port(const struct emul *tcpc_emul,
+					 const struct emul *charger_emul)
+{
+	zassert_ok(tcpci_emul_disconnect_partner(tcpc_emul), NULL);
+	isl923x_emul_set_adc_vbus(charger_emul, 0);
+	k_sleep(K_SECONDS(1));
+}
+
+/** Sets the partner as initial source, which should cause a VCONN swap to be
+ * performed on connect.
+ */
+static void *common_setup(void)
+{
+	static struct usbc_vconn_swap_fixture outer_fixture;
+	struct common_fixture *fixture = &outer_fixture.common;
+	struct tcpci_partner_data *partner = &fixture->partner;
+	struct tcpci_src_emul_data *src_ext = &fixture->src_ext;
+	struct tcpci_snk_emul_data *snk_ext = &fixture->snk_ext;
+
+	tcpci_partner_init(partner, PD_REV30);
+	fixture->partner.extensions = tcpci_drp_emul_init(
+		&fixture->drp_ext, partner, PD_ROLE_SOURCE,
+		tcpci_src_emul_init(src_ext, partner, NULL),
+		tcpci_snk_emul_init(snk_ext, partner, NULL));
+
+	/* Get references for the emulators */
+	fixture->tcpci_emul = EMUL_GET_USBC_BINDING(TEST_PORT, tcpc);
+	fixture->charger_emul = EMUL_GET_USBC_BINDING(TEST_PORT, chg);
+
+	return &outer_fixture;
+}
+
+static void *usbc_vconn_swap_setup(void)
+{
+	return common_setup();
+}
+
+static void *usbc_vconn_swap_not_supported_setup(void)
+{
+	struct usbc_vconn_swap_fixture *fixture = common_setup();
+
+	/* The partner will respond to VCONN_Swap with Not_Supported. */
+	tcpci_partner_set_vcs_response(&fixture->common.partner,
+				       PD_CTRL_NOT_SUPPORTED);
+	return fixture;
+}
+
+static void *usbc_vconn_swap_reject_setup(void)
+{
+	struct usbc_vconn_swap_fixture *fixture = common_setup();
+
+	/* The partner will respond to VCONN_Swap with Reject. */
+	tcpci_partner_set_vcs_response(&fixture->common.partner,
+				       PD_CTRL_REJECT);
+	return fixture;
+}
+
+static void common_before(struct common_fixture *fixture)
+{
+	/* Set chipset to ON, this will set TCPM to DRP */
+	test_set_chipset_to_s0();
+
+	/* TODO(b/214401892): Check why need to give time TCPM to spin */
+	k_sleep(K_SECONDS(1));
+
+	connect_partner_to_port(fixture->tcpci_emul, fixture->charger_emul,
+				&fixture->partner, &fixture->src_ext);
+	k_sleep(K_SECONDS(1));
+}
+
+static void usbc_vconn_swap_before(void *data)
+{
+	struct usbc_vconn_swap_fixture *outer = data;
+
+	RESET_FAKE(port_discovery_vconn_swap_policy);
+	port_discovery_vconn_swap_policy_fake.custom_fake =
+		port_discovery_vconn_swap_policy_custom;
+
+	common_before(&outer->common);
+}
+
+static void usbc_vconn_swap_late_before(void *data)
+{
+	struct usbc_vconn_swap_fixture *outer = data;
+
+	static bool (*custom_fakes[])(
+		int, bool) = { port_discovery_vconn_swap_policy_nope,
+			       port_discovery_vconn_swap_policy_custom };
+
+	RESET_FAKE(port_discovery_vconn_swap_policy);
+	SET_CUSTOM_FAKE_SEQ(port_discovery_vconn_swap_policy, custom_fakes, 2);
+
+	common_before(&outer->common);
+}
+
+static void usbc_vconn_swap_not_supported_before(void *data)
+{
+	struct usbc_vconn_swap_not_supported_fixture *outer = data;
+
+	RESET_FAKE(port_discovery_vconn_swap_policy);
+	port_discovery_vconn_swap_policy_fake.custom_fake =
+		port_discovery_vconn_swap_policy_custom;
+
+	common_before(&outer->common);
+}
+
+static void usbc_vconn_swap_reject_before(void *data)
+{
+	struct usbc_vconn_swap_reject_fixture *outer = data;
+
+	RESET_FAKE(port_discovery_vconn_swap_policy);
+	port_discovery_vconn_swap_policy_fake.custom_fake =
+		port_discovery_vconn_swap_policy_custom;
+
+	common_before(&outer->common);
+}
+
+static void common_after(struct common_fixture *fixture)
+{
+	disconnect_partner_from_port(fixture->tcpci_emul,
+				     fixture->charger_emul);
+	RESET_FAKE(port_discovery_vconn_swap_policy);
+	port_discovery_vconn_swap_policy_fake.custom_fake =
+		port_discovery_vconn_swap_policy_custom;
+}
+
+static void usbc_vconn_swap_after(void *data)
+{
+	struct usbc_vconn_swap_fixture *outer = data;
+
+	common_after(&outer->common);
+}
+
+static void usbc_vconn_swap_not_supported_after(void *data)
+{
+	struct usbc_vconn_swap_not_supported_fixture *outer = data;
+
+	common_after(&outer->common);
+}
+
+static void usbc_vconn_swap_reject_after(void *data)
+{
+	struct usbc_vconn_swap_reject_fixture *outer = data;
+
+	common_after(&outer->common);
+}
+
+ZTEST_F(usbc_vconn_swap, test_vconn_swap_before_discovery)
+{
+	struct ec_response_typec_status status =
+		host_cmd_typec_status(TEST_PORT);
+
+	zassert_equal(status.vconn_role, PD_ROLE_VCONN_SRC,
+		      "TCPM did not initiate VCONN Swap after attach");
+}
+
+ZTEST_F(usbc_vconn_swap, test_vconn_swap_via_host_command)
+{
+	struct ec_response_typec_status status =
+		host_cmd_typec_status(TEST_PORT);
+
+	zassert_equal(status.vconn_role, PD_ROLE_VCONN_SRC,
+		      "TCPM did not initiate VCONN Swap after attach");
+
+	host_cmd_usb_pd_control(TEST_PORT, USB_PD_CTRL_SWAP_VCONN);
+	k_sleep(K_SECONDS(1));
+
+	status = host_cmd_typec_status(TEST_PORT);
+	zassert_equal(status.vconn_role, PD_ROLE_VCONN_OFF,
+		      "TCPM did not initiate VCONN Swap after host command");
+}
+
+ZTEST_SUITE(usbc_vconn_swap, drivers_predicate_post_main, usbc_vconn_swap_setup,
+	    usbc_vconn_swap_before, usbc_vconn_swap_after, NULL);
+
+ZTEST_F(usbc_vconn_swap_not_supported, test_vconn_swap_force_vconn)
+{
+	struct ec_response_typec_status status =
+		host_cmd_typec_status(TEST_PORT);
+
+	zassert_equal(status.vconn_role, PD_ROLE_VCONN_SRC,
+		      "TCPM did not initiate VCONN Swap after attach");
+}
+
+ZTEST_SUITE(usbc_vconn_swap_not_supported, drivers_predicate_post_main,
+	    usbc_vconn_swap_not_supported_setup,
+	    usbc_vconn_swap_not_supported_before,
+	    usbc_vconn_swap_not_supported_after, NULL);
+
+/** Tests if the board's port_discovery_vconn_swap_policy doesn't allow a
+ *  vconn immediately, that it will still work eventually. See fake
+ *  setup in usbc_vconn_swap_late_before().
+ */
+ZTEST_F(usbc_vconn_swap_late, test_vconn_swap_before_discovery)
+{
+	struct ec_response_typec_status status;
+
+	status = host_cmd_typec_status(TEST_PORT);
+
+	zassert_equal(status.vconn_role, PD_ROLE_VCONN_SRC,
+		      "TCPM did not initiate VCONN Swap after attach");
+}
+
+ZTEST_SUITE(usbc_vconn_swap_late, drivers_predicate_post_main,
+	    usbc_vconn_swap_setup, usbc_vconn_swap_late_before,
+	    usbc_vconn_swap_after, NULL);
+
+ZTEST_F(usbc_vconn_swap_reject, test_vconn_swap_force_vconn)
+{
+	struct ec_response_typec_status status =
+		host_cmd_typec_status(TEST_PORT);
+
+	zassert_equal(status.vconn_role, PD_ROLE_VCONN_OFF);
+}
+
+ZTEST_SUITE(usbc_vconn_swap_reject, drivers_predicate_post_main,
+	    usbc_vconn_swap_reject_setup, usbc_vconn_swap_reject_before,
+	    usbc_vconn_swap_reject_after, NULL);
diff --git a/zephyr/test/ec_app/CMakeLists.txt b/zephyr/test/ec_app/CMakeLists.txt
new file mode 100644
index 0000000000..83daf93e67
--- /dev/null
+++ b/zephyr/test/ec_app/CMakeLists.txt
@@ -0,0 +1,10 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(ec_app)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
diff --git a/zephyr/test/ec_app/boards/native_posix.overlay b/zephyr/test/ec_app/boards/native_posix.overlay
new file mode 100644
index 0000000000..1afbdd4f4c
--- /dev/null
+++ b/zephyr/test/ec_app/boards/native_posix.overlay
@@ -0,0 +1,53 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <board-overlays/native_posix.dts>
+#include <cros/binman.dtsi>
+
+/ {
+	chosen {
+		cros-ec,flash = &flash1;
+		cros-ec,flash-controller = &cros_flash;
+	};
+	aliases {
+		gpio-wp = &gpio_wp_l;
+	};
+	named-gpios {
+		compatible = "named-gpios";
+		ec_gsc_packet_mode {
+			gpios = <&gpio0 2 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_PACKET_MODE_EN";
+		};
+		gpio_wp_l: wp_l {
+			gpios = <&gpio0 3 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+	};
+	cros_flash: cros-flash {
+		compatible = "cros-ec,flash-emul";
+	};
+	flash1: flash@64000000 {
+		reg = <0x64000000 DT_SIZE_K(512)>;
+	};
+
+	power-states {
+		suspend_to_idle_instant: suspend_to_idle_instant {
+			compatible = "zephyr,power-state";
+			power-state-name = "suspend-to-idle";
+			substate-id = <0>;
+			min-residency-us = <500>;
+		};
+
+		suspend_to_idle_normal: suspend_to_idle_normal {
+			compatible = "zephyr,power-state";
+			power-state-name = "suspend-to-idle";
+			substate-id = <1>;
+			min-residency-us = <200100>;
+		};
+	};
+};
+
+&gpio0 {
+	ngpios = <4>;
+};
diff --git a/zephyr/test/ec_app/prj.conf b/zephyr/test/ec_app/prj.conf
new file mode 100644
index 0000000000..74f49af023
--- /dev/null
+++ b/zephyr/test/ec_app/prj.conf
@@ -0,0 +1,22 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_ZTEST=y
+CONFIG_ZTEST_NEW_API=y
+CONFIG_PLATFORM_EC=y
+CONFIG_CROS_EC=y
+CONFIG_FLASH=y
+CONFIG_SHELL_BACKEND_DUMMY=y
+CONFIG_SHELL_BACKEND_SERIAL=n
+CONFIG_SERIAL=y
+CONFIG_RING_BUFFER=y
+
+CONFIG_PM=y
+CONFIG_PLATFORM_EC_VBOOT_EFS2=y
+CONFIG_PLATFORM_EC_VBOOT_HASH=y
+CONFIG_PLATFORM_EC_HOSTCMD=y
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
+CONFIG_PLATFORM_EC_SWITCH=n
+CONFIG_PLATFORM_EC_BOOT_NO_SLEEP=y
+CONFIG_PLATFORM_EC_BOOT_NO_SLEEP_MS=1000
\ No newline at end of file
diff --git a/zephyr/test/ec_app/src/main.c b/zephyr/test/ec_app/src/main.c
new file mode 100644
index 0000000000..2e3cd7efa9
--- /dev/null
+++ b/zephyr/test/ec_app/src/main.c
@@ -0,0 +1,125 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_app_main.h"
+#include "hooks.h"
+#include "task.h"
+#include "timer.h"
+
+#include <zephyr/pm/policy.h>
+#include <zephyr/shell/shell_dummy.h>
+#include <zephyr/ztest_assert.h>
+#include <zephyr/ztest_test_new.h>
+
+#ifdef CONFIG_CMD_AP_RESET_LOG
+ZTEST(ec_app_tests, test_init_reset_log)
+{
+	zassert_unreachable("TODO: Implement this test.");
+}
+#endif
+
+#ifdef CONFIG_HOSTCMD_X86
+ZTEST(ec_app_tests, test_lpc_init_mask)
+{
+	zassert_unreachable("TODO: Implement this test.");
+}
+#endif
+
+#ifdef HAS_TASK_KEYSCAN
+ZTEST(ec_app_tests, test_keyboard_scan_init)
+{
+	zassert_unreachable("TODO: Implement this test.");
+}
+#endif
+
+#if defined(CONFIG_DEDICATED_RECOVERY_BUTTON) || defined(CONFIG_VOLUME_BUTTONS)
+ZTEST(ec_app_tests, test_button_init)
+{
+	zassert_unreachable("TODO: Implement this test.");
+}
+#endif
+
+#ifdef CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI
+ZTEST(ec_app_tests, test_setup_espi)
+{
+	zassert_unreachable("TODO: Implement this test.");
+}
+#endif
+
+#ifdef CONFIG_WATCHDOG
+ZTEST(ec_app_tests, test_watchdog_init)
+{
+	zassert_unreachable("TODO: Implement this test.");
+}
+#endif
+
+#ifdef CONFIG_PLATFORM_EC_VBOOT_EFS2
+ZTEST(ec_app_tests, test_vboot_main)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+	const char *outbuffer;
+	size_t buffer_size;
+
+	/* vboot_main logs the message "VB Verifying hash" */
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+	zassert_true(strstr(outbuffer, "VB Verifying hash") != NULL,
+		     "'VB Verifying hash' not found in %s", outbuffer);
+}
+#endif
+
+#ifdef CONFIG_PLATFORM_EC_HOOKS
+static int sample_init_hook_count;
+/**
+ * Just a sample hook.
+ */
+static void sample_init_hook(void)
+{
+	printk("Running hook.\n");
+	sample_init_hook_count++;
+}
+DECLARE_HOOK(HOOK_INIT, sample_init_hook, HOOK_PRIO_DEFAULT);
+
+/**
+ * @brief Test EC App main runs hooks of type HOOK_INIT.
+ *
+ * This test installs a hook, runs main and verifies that the hook ran.
+ *
+ */
+ZTEST(ec_app_tests, test_hook_notify_init)
+{
+	zassert_equal(1, sample_init_hook_count,
+		      "Expected sample_init_hook to run once.");
+}
+#endif
+
+#ifdef CONFIG_SHIMMED_TASKS
+ZTEST(ec_app_tests, test_start_ec_tasks)
+{
+	zassert_equal(task_start_called(), 1, "Tasks did not start.");
+}
+#endif
+
+ZTEST(ec_app_tests, test_ec_boot_sleep_disable)
+{
+#ifdef CONFIG_PLATFORM_EC_BOOT_NO_SLEEP_MS
+	zassert_true(pm_policy_state_lock_is_active(PM_STATE_SUSPEND_TO_IDLE,
+						    PM_ALL_SUBSTATES));
+	k_msleep(2 * CONFIG_PLATFORM_EC_BOOT_NO_SLEEP_MS);
+#endif
+	zassert_false(pm_policy_state_lock_is_active(PM_STATE_SUSPEND_TO_IDLE,
+						     PM_ALL_SUBSTATES));
+}
+
+/* Does setup for all of the test cases. */
+void *ec_app_setup(void)
+{
+#ifdef CONFIG_SHIMMED_TASKS
+	zassert_equal(task_start_called(), 0, "Tasks have already started.");
+#endif
+	ec_app_main();
+	return NULL;
+}
+
+ZTEST_SUITE(ec_app_tests, NULL, ec_app_setup, NULL, NULL, NULL);
diff --git a/zephyr/test/ec_app/testcase.yaml b/zephyr/test/ec_app/testcase.yaml
new file mode 100644
index 0000000000..4f21d64207
--- /dev/null
+++ b/zephyr/test/ec_app/testcase.yaml
@@ -0,0 +1,4 @@
+common:
+  platform_allow: native_posix
+tests:
+  ec_app.default: {}
diff --git a/zephyr/test/herobrine/CMakeLists.txt b/zephyr/test/herobrine/CMakeLists.txt
new file mode 100644
index 0000000000..17b3d973a1
--- /dev/null
+++ b/zephyr/test/herobrine/CMakeLists.txt
@@ -0,0 +1,14 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(herobrine)
+
+zephyr_include_directories("${PLATFORM_EC_PROGRAM_DIR}/herobrine/include")
+
+target_sources_ifdef(CONFIG_TEST_BOARD_CHIPSET
+	app PRIVATE src/board_chipset.c)
+target_sources_ifdef(CONFIG_TEST_BOARD_CHIPSET
+	app PRIVATE ${PLATFORM_EC_PROGRAM_DIR}/herobrine/src/board_chipset.c)
diff --git a/zephyr/test/herobrine/Kconfig b/zephyr/test/herobrine/Kconfig
new file mode 100644
index 0000000000..8c3dc24727
--- /dev/null
+++ b/zephyr/test/herobrine/Kconfig
@@ -0,0 +1,12 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config TEST_BOARD_CHIPSET
+	bool "Run the tests intended for board_chipset"
+	help
+	  Include board_chipset.c into the binary. Test their functions in
+	  different combinations: good battery vs low battery, normal boot
+	  vs delayed boot, etc.
+
+source "Kconfig.zephyr"
diff --git a/zephyr/test/herobrine/README.md b/zephyr/test/herobrine/README.md
new file mode 100644
index 0000000000..646c7ad985
--- /dev/null
+++ b/zephyr/test/herobrine/README.md
@@ -0,0 +1,3 @@
+Tests for board specific code under `zephyr/program/herobrine/src`.
+
+Run with ./twister -T zephyr/test/herobrine
diff --git a/zephyr/test/herobrine/boards/native_posix.overlay b/zephyr/test/herobrine/boards/native_posix.overlay
new file mode 100644
index 0000000000..37febb9516
--- /dev/null
+++ b/zephyr/test/herobrine/boards/native_posix.overlay
@@ -0,0 +1,26 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <board-overlays/native_posix.dts>
+
+/ {
+        /*
+         * Keep these GPIOs in pin order.
+         * If you need to add one, make sure you increase
+         * ngpios in the gpio0 node further down.
+         */
+        named-gpios {
+                compatible = "named-gpios";
+
+                gpio_en_pp5000_s5: en_pp5000_s5 {
+                        gpios = <&gpio0 2 GPIO_OUTPUT_LOW>;
+                        enum-name = "GPIO_EN_PP5000";
+                };
+	};
+};
+
+&gpio0 {
+        ngpios = <3>;
+};
diff --git a/zephyr/test/herobrine/prj.conf b/zephyr/test/herobrine/prj.conf
new file mode 100644
index 0000000000..89165e36a8
--- /dev/null
+++ b/zephyr/test/herobrine/prj.conf
@@ -0,0 +1,11 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_ZTEST=y
+CONFIG_ZTEST_ASSERT_VERBOSE=1
+CONFIG_ZTEST_NEW_API=y
+CONFIG_ASSERT=y
+
+CONFIG_CROS_EC=y
+CONFIG_PLATFORM_EC=y
diff --git a/zephyr/test/herobrine/src/board_chipset.c b/zephyr/test/herobrine/src/board_chipset.c
new file mode 100644
index 0000000000..0e45de2547
--- /dev/null
+++ b/zephyr/test/herobrine/src/board_chipset.c
@@ -0,0 +1,126 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "battery_fuel_gauge.h"
+#include "board_chipset.h"
+#include "ec_commands.h"
+#include "hooks.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+extern int test_disconnect_state;
+static int battery_soc_abs_value = 50;
+
+int battery_state_of_charge_abs(int *percent)
+{
+	*percent = battery_soc_abs_value;
+	return EC_SUCCESS;
+}
+
+int charger_get_min_bat_pct_for_power_on(void)
+{
+	return 2;
+}
+
+int ppc_init(int port)
+{
+	return EC_SUCCESS;
+}
+
+enum pd_cc_states pd_get_task_cc_state(int port)
+{
+	return PD_CC_NONE;
+}
+
+int test_disconnect_state = -1;
+
+enum battery_disconnect_state battery_get_disconnect_state(void)
+{
+	return test_disconnect_state;
+}
+
+ZTEST_USER(board_chipset, test_good_battery_normal_boot)
+{
+	timestamp_t start_time;
+	uint64_t time_diff_us;
+
+	battery_soc_abs_value = 50;
+
+	start_time = get_time();
+	hook_notify(HOOK_CHIPSET_PRE_INIT);
+	time_diff_us = get_time().val - start_time.val;
+
+	printk("%s: time_diff_us: %d\n", __func__, time_diff_us);
+
+	zassert_true(time_diff_us <= 20000, "CHIPSET_PRE_INIT hook delayed",
+		     NULL);
+}
+
+ZTEST_USER(board_chipset, test_low_battery_with_pd_delayed_boot)
+{
+	timestamp_t start_time;
+	uint64_t time_diff_us;
+
+	battery_soc_abs_value = 1;
+
+	start_time = get_time();
+	hook_notify(HOOK_CHIPSET_PRE_INIT);
+	time_diff_us = get_time().val - start_time.val;
+
+	printk("%s: time_diff_us: %d\n", __func__, time_diff_us);
+
+	zassert_true(time_diff_us > 500000, "CHIPSET_PRE_INIT hook delayed",
+		     NULL);
+}
+
+ZTEST_USER(board_chipset, test_low_battery_delayed_boot)
+{
+	timestamp_t start_time;
+	uint64_t time_diff_us;
+
+	battery_soc_abs_value = 1;
+	/* The PD connect event delays the power on sequence */
+	hook_notify(HOOK_USB_PD_CONNECT);
+
+	start_time = get_time();
+	hook_notify(HOOK_CHIPSET_PRE_INIT);
+	time_diff_us = get_time().val - start_time.val;
+
+	printk("%s: time_diff_us: %d\n", __func__, time_diff_us);
+
+	zassert_true(time_diff_us > 500000, "CHIPSET_PRE_INIT hook not delayed",
+		     NULL);
+}
+
+ZTEST_USER(board_chipset, test_disconnect_battery_delayed_boot)
+{
+	timestamp_t start_time;
+	uint64_t time_diff_us;
+
+	battery_soc_abs_value = 50;
+	test_disconnect_state = BATTERY_DISCONNECTED;
+
+	start_time = get_time();
+	hook_notify(HOOK_CHIPSET_PRE_INIT);
+	time_diff_us = get_time().val - start_time.val;
+
+	printk("%s: time_diff_us: %d\n", __func__, time_diff_us);
+
+	zassert_true(time_diff_us > 500000, "CHIPSET_PRE_INIT hook delayed",
+		     NULL);
+}
+
+static void test_before(void *data)
+{
+	ARG_UNUSED(data);
+	reset_pp5000_inited();
+	test_disconnect_state = BATTERY_NOT_DISCONNECTED;
+}
+
+ZTEST_SUITE(board_chipset, NULL, NULL, test_before, NULL, NULL);
diff --git a/zephyr/test/herobrine/testcase.yaml b/zephyr/test/herobrine/testcase.yaml
new file mode 100644
index 0000000000..1ccb56582f
--- /dev/null
+++ b/zephyr/test/herobrine/testcase.yaml
@@ -0,0 +1,10 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+common:
+  platform_allow: native_posix
+tests:
+  herobrine.board_chipset:
+    extra_configs:
+      - CONFIG_TEST_BOARD_CHIPSET=y
diff --git a/zephyr/test/hooks/CMakeLists.txt b/zephyr/test/hooks/CMakeLists.txt
new file mode 100644
index 0000000000..99b0b3f430
--- /dev/null
+++ b/zephyr/test/hooks/CMakeLists.txt
@@ -0,0 +1,9 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(hooks)
+
+target_sources(app PRIVATE hooks.c)
diff --git a/zephyr/test/hooks/boards/native_posix.overlay b/zephyr/test/hooks/boards/native_posix.overlay
new file mode 100644
index 0000000000..90c864d2fd
--- /dev/null
+++ b/zephyr/test/hooks/boards/native_posix.overlay
@@ -0,0 +1,6 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <board-overlays/native_posix.dts>
diff --git a/zephyr/test/hooks/hooks.c b/zephyr/test/hooks/hooks.c
new file mode 100644
index 0000000000..bc2840eae5
--- /dev/null
+++ b/zephyr/test/hooks/hooks.c
@@ -0,0 +1,203 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ap_power/ap_power.h"
+#include "hooks.h"
+
+#include <stdbool.h>
+
+#include <zephyr/ztest.h>
+
+static bool h1_called;
+static bool h2_called;
+static bool h3_called;
+
+static void h1(void)
+{
+	zassert_false(h1_called, "h1 was called, but should not have been");
+	zassert_false(h2_called, "h2 was called, but should not have been");
+	zassert_false(h3_called, "h3 was called, but should not have been");
+	h1_called = true;
+}
+DECLARE_HOOK(HOOK_TEST_1, h1, HOOK_PRIO_FIRST);
+
+static void h2(void)
+{
+	zassert_true(h1_called, "h1 was not called, but should have been");
+	zassert_false(h2_called, "h2 was called, but should not have been");
+	zassert_false(h3_called, "h3 was called, but should not have been");
+	h2_called = true;
+}
+DECLARE_HOOK(HOOK_TEST_1, h2, HOOK_PRIO_DEFAULT);
+
+static void h3(void)
+{
+	zassert_true(h1_called, "h1 was not called, but should have been");
+	zassert_true(h2_called, "h2 was not called, but should have been");
+	zassert_false(h3_called, "h3 was called, but should not have been");
+	h3_called = true;
+}
+DECLARE_HOOK(HOOK_TEST_1, h3, HOOK_PRIO_LAST);
+
+ZTEST(hooks_tests, test_hook_list_multiple)
+{
+	hook_notify(HOOK_TEST_1);
+	zassert_true(h1_called, "h1 was not called, but should have been");
+	zassert_true(h2_called, "h2 was not called, but should have been");
+	zassert_true(h3_called, "h3 was not called, but should have been");
+}
+
+static bool h4_called;
+
+static void h4(void)
+{
+	zassert_false(h4_called, "h4 was called, but should not have been");
+	h4_called = true;
+}
+DECLARE_HOOK(HOOK_TEST_2, h4, HOOK_PRIO_DEFAULT);
+
+ZTEST(hooks_tests, test_hook_list_single)
+{
+	hook_notify(HOOK_TEST_2);
+	zassert_true(h4_called, "h4 was not called, but should have been");
+}
+
+ZTEST(hooks_tests, test_hook_list_empty)
+{
+	hook_notify(HOOK_TEST_3);
+}
+
+static bool deferred_func_called;
+
+#define DEFERRED_DELAY_US (500 * 1000)
+static void deferred_func(void)
+{
+	deferred_func_called = true;
+}
+DECLARE_DEFERRED(deferred_func);
+
+ZTEST(hooks_tests, test_deferred_func)
+{
+	zassert_false(
+		deferred_func_called,
+		"The deferred function was called, but should not have been");
+	hook_call_deferred(&deferred_func_data, DEFERRED_DELAY_US);
+	zassert_false(
+		deferred_func_called,
+		"The deferred function was called, but should not have been");
+	k_usleep(DEFERRED_DELAY_US * 2);
+	zassert_true(
+		deferred_func_called,
+		"The deferred function was not called, but should have been");
+}
+
+static bool deferred_func_2_called;
+
+static void deferred_func_2(void)
+{
+	deferred_func_2_called = true;
+}
+DECLARE_DEFERRED(deferred_func_2);
+
+/*
+ * Test that repeated calls to hook_call_deferred result in the
+ * function being pushed out.
+ */
+ZTEST(hooks_tests, test_deferred_func_push_out)
+{
+	zassert_false(
+		deferred_func_2_called,
+		"The deferred function was called, but should not have been");
+	hook_call_deferred(&deferred_func_2_data, DEFERRED_DELAY_US);
+	hook_call_deferred(&deferred_func_2_data, DEFERRED_DELAY_US * 3);
+	k_usleep(DEFERRED_DELAY_US * 2);
+	zassert_false(
+		deferred_func_2_called,
+		"The deferred function was called, but should not have been");
+	k_usleep(DEFERRED_DELAY_US * 2);
+	zassert_true(
+		deferred_func_called,
+		"The deferred function was not called, but should have been");
+}
+
+static bool deferred_func_3_called;
+
+static void deferred_func_3(void)
+{
+	deferred_func_3_called = true;
+}
+DECLARE_DEFERRED(deferred_func_3);
+
+ZTEST(hooks_tests, test_deferred_func_cancel)
+{
+	zassert_false(
+		deferred_func_3_called,
+		"The deferred function was called, but should not have been");
+	hook_call_deferred(&deferred_func_3_data, DEFERRED_DELAY_US);
+	hook_call_deferred(&deferred_func_3_data, -1);
+	k_usleep(DEFERRED_DELAY_US * 2);
+	zassert_false(
+		deferred_func_3_called,
+		"The deferred function was called, but should not have been");
+}
+
+/*
+ * Structure passed to event listeners.
+ */
+struct events {
+	struct ap_power_ev_callback cb;
+	enum ap_power_events event;
+	int count;
+};
+
+/*
+ * Common handler.
+ * Increment count, and store event received.
+ */
+static void ev_handler(struct ap_power_ev_callback *callback,
+		       struct ap_power_ev_data data)
+{
+	struct events *ev = CONTAINER_OF(callback, struct events, cb);
+
+	ev->count++;
+	ev->event = data.event;
+}
+
+ZTEST(hooks_tests, test_hook_ap_power_events)
+{
+	static struct events cb;
+
+	ap_power_ev_init_callback(&cb.cb, ev_handler, AP_POWER_SUSPEND);
+	ap_power_ev_add_callback(&cb.cb);
+	hook_notify(HOOK_CHIPSET_SUSPEND);
+	zassert_equal(1, cb.count, "Callback not called");
+	zassert_equal(AP_POWER_SUSPEND, cb.event, "Wrong event");
+	ap_power_ev_remove_callback(&cb.cb);
+	hook_notify(HOOK_CHIPSET_SUSPEND);
+	zassert_equal(1, cb.count, "Callback called");
+
+	cb.count = 0;
+	ap_power_ev_init_callback(&cb.cb, ev_handler,
+				  AP_POWER_SUSPEND | AP_POWER_RESUME);
+	ap_power_ev_add_callback(&cb.cb);
+	hook_notify(HOOK_CHIPSET_SUSPEND);
+	zassert_equal(1, cb.count, "Callbacks not called");
+	zassert_equal(AP_POWER_SUSPEND, cb.event, "Wrong event");
+	hook_notify(HOOK_CHIPSET_RESUME);
+	zassert_equal(2, cb.count, "Callbacks not called");
+	zassert_equal(AP_POWER_RESUME, cb.event, "Wrong event");
+
+	ap_power_ev_remove_events(&cb.cb, AP_POWER_SUSPEND);
+	hook_notify(HOOK_CHIPSET_SUSPEND);
+	zassert_equal(2, cb.count, "Suspend allback called");
+
+	hook_notify(HOOK_CHIPSET_STARTUP);
+	zassert_equal(2, cb.count, "Startup callback called");
+	ap_power_ev_add_events(&cb.cb, AP_POWER_STARTUP);
+	hook_notify(HOOK_CHIPSET_STARTUP);
+	zassert_equal(3, cb.count, "Startup callback not called");
+}
+
+ZTEST_SUITE(hooks_tests, NULL, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/hooks/prj.conf b/zephyr/test/hooks/prj.conf
new file mode 100644
index 0000000000..cab9107094
--- /dev/null
+++ b/zephyr/test/hooks/prj.conf
@@ -0,0 +1,9 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_ZTEST=y
+CONFIG_ZTEST_NEW_API=y
+CONFIG_PLATFORM_EC=y
+CONFIG_PLATFORM_EC_HOOKS=y
+CONFIG_CROS_EC=y
diff --git a/zephyr/test/hooks/testcase.yaml b/zephyr/test/hooks/testcase.yaml
new file mode 100644
index 0000000000..f35baae16b
--- /dev/null
+++ b/zephyr/test/hooks/testcase.yaml
@@ -0,0 +1,4 @@
+common:
+  platform_allow: native_posix
+tests:
+  hooks.default: {}
diff --git a/zephyr/test/i2c/CMakeLists.txt b/zephyr/test/i2c/CMakeLists.txt
new file mode 100644
index 0000000000..4b355c4932
--- /dev/null
+++ b/zephyr/test/i2c/CMakeLists.txt
@@ -0,0 +1,9 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(i2c)
+
+target_sources(app PRIVATE src/main.c)
diff --git a/zephyr/test/i2c/boards/native_posix.overlay b/zephyr/test/i2c/boards/native_posix.overlay
new file mode 100644
index 0000000000..e78c5d0faa
--- /dev/null
+++ b/zephyr/test/i2c/boards/native_posix.overlay
@@ -0,0 +1,37 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <board-overlays/native_posix.dts>
+
+/ {
+	i2c1: i2c@400 {
+		status = "okay";
+		compatible = "zephyr,i2c-emul-controller";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x400 4>;
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+		accel-0 {
+			i2c-port = <&i2c0>;
+			enum-names = "I2C_PORT_ACCEL",
+				"I2C_PORT_EEPROM";
+		};
+		usb-c1 {
+			i2c-port = <&i2c1>;
+			enum-names = "I2C_PORT_USB_C1";
+		};
+	};
+};
+
+&i2c0 {
+	bmi_i2c: bmi@68 {
+		compatible = "bosch,bmi160";
+		reg = <0x68>;
+	};
+};
diff --git a/zephyr/test/i2c/prj.conf b/zephyr/test/i2c/prj.conf
new file mode 100644
index 0000000000..abf7d7e113
--- /dev/null
+++ b/zephyr/test/i2c/prj.conf
@@ -0,0 +1,17 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_ZTEST=y
+CONFIG_ZTEST_NEW_API=y
+
+CONFIG_EMUL=y
+CONFIG_EMUL_BMI160=y
+CONFIG_SENSOR=y
+CONFIG_BMI160_TRIGGER_NONE=y
+
+CONFIG_PLATFORM_EC=y
+CONFIG_CROS_EC=y
+
+# TODO(b/173711210) figure out why SPI is required here when we're not using it.
+CONFIG_SPI=y
diff --git a/zephyr/test/i2c/src/main.c b/zephyr/test/i2c/src/main.c
new file mode 100644
index 0000000000..759fe01151
--- /dev/null
+++ b/zephyr/test/i2c/src/main.c
@@ -0,0 +1,68 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "i2c.h"
+#include "i2c/i2c.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/ztest.h>
+
+/* Unused: required for shimming i2c. */
+void watchdog_reload(void)
+{
+}
+
+ZTEST_USER(i2c, test_i2c_port_count)
+{
+	zassert_equal(I2C_PORT_COUNT, 2,
+		      "I2C_PORT_COUNT expected to be 2 but was %d",
+		      I2C_PORT_COUNT);
+}
+
+ZTEST_USER(i2c, test_i2c_lock_invalid_port)
+{
+	i2c_lock(-1, 1);
+	zassert_equal(i2c_port_is_locked(-1), 0,
+		      "Negative I2C port locked, but should have failed");
+
+	i2c_lock(INT_MAX, 1);
+	zassert_equal(i2c_port_is_locked(INT_MAX), 0,
+		      "MAX_INT I2C port locked, but should have failed");
+}
+
+ZTEST_USER(i2c, test_i2c_lock)
+{
+	i2c_lock(I2C_PORT_ACCEL, 1);
+	zassert_equal(i2c_port_is_locked(I2C_PORT_EEPROM), 1,
+		      "I2C_PORT_EEPROM not locked");
+	zassert_equal(i2c_port_is_locked(I2C_PORT_ACCEL), 1,
+		      "I2C_PORT_ACCEL not locked");
+
+	/* Unlock different enum pointing the same i2c device */
+	i2c_lock(I2C_PORT_EEPROM, 0);
+	zassert_equal(i2c_port_is_locked(I2C_PORT_EEPROM), 0,
+		      "I2C_PORT_EEPROM not locked");
+	zassert_equal(i2c_port_is_locked(I2C_PORT_ACCEL), 0,
+		      "I2C_PORT_ACCEL not locked");
+
+	i2c_lock(I2C_PORT_EEPROM, 1);
+	/* Verify different i2c device */
+	zassert_equal(i2c_port_is_locked(I2C_PORT_USB_C1), 0,
+		      "I2C_PORT_USB_C1 locked");
+
+	i2c_lock(I2C_PORT_USB_C1, 1);
+	/* Make sure i2c device is locked*/
+	zassert_equal(i2c_port_is_locked(I2C_PORT_USB_C1), 1,
+		      "I2C_PORT_USB_C1 locked");
+
+	/* Another i2c device is still locked */
+	i2c_lock(I2C_PORT_USB_C1, 0);
+	zassert_equal(i2c_port_is_locked(I2C_PORT_EEPROM), 1,
+		      "I2C_PORT_EEPROM not locked");
+	i2c_lock(I2C_PORT_EEPROM, 0);
+}
+
+ZTEST_SUITE(i2c, NULL, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/i2c/testcase.yaml b/zephyr/test/i2c/testcase.yaml
new file mode 100644
index 0000000000..4e111ea13f
--- /dev/null
+++ b/zephyr/test/i2c/testcase.yaml
@@ -0,0 +1,4 @@
+common:
+  platform_allow: native_posix
+tests:
+  i2c.default: {}
diff --git a/zephyr/test/i2c_dts/CMakeLists.txt b/zephyr/test/i2c_dts/CMakeLists.txt
new file mode 100644
index 0000000000..3e36468a33
--- /dev/null
+++ b/zephyr/test/i2c_dts/CMakeLists.txt
@@ -0,0 +1,10 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(i2c_test)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
diff --git a/zephyr/test/i2c_dts/boards/native_posix.overlay b/zephyr/test/i2c_dts/boards/native_posix.overlay
new file mode 100644
index 0000000000..0abd2f1f31
--- /dev/null
+++ b/zephyr/test/i2c_dts/boards/native_posix.overlay
@@ -0,0 +1,23 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <board-overlays/native_posix.dts>
+
+/ {
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+		accel-0 {
+			i2c-port = <&i2c0>;
+			enum-names = "I2C_PORT_ACCEL";
+		};
+	};
+};
+
+&i2c0 {
+	bmi_i2c: bmi@68 {
+		compatible = "bosch,bmi160";
+		reg = <0x68>;
+	};
+};
diff --git a/zephyr/test/i2c_dts/prj.conf b/zephyr/test/i2c_dts/prj.conf
new file mode 100644
index 0000000000..e2075400e8
--- /dev/null
+++ b/zephyr/test/i2c_dts/prj.conf
@@ -0,0 +1,17 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_ZTEST=y
+CONFIG_ZTEST_NEW_API=y
+
+CONFIG_PLATFORM_EC=y
+CONFIG_CROS_EC=y
+
+CONFIG_EMUL=y
+CONFIG_EMUL_BMI160=y
+CONFIG_SENSOR=y
+CONFIG_BMI160_TRIGGER_NONE=y
+
+# TODO(b/173711210) figure out why SPI is required here when we're not using it.
+CONFIG_SPI=y
diff --git a/zephyr/test/i2c_dts/src/main.c b/zephyr/test/i2c_dts/src/main.c
new file mode 100644
index 0000000000..3f24bbfd9c
--- /dev/null
+++ b/zephyr/test/i2c_dts/src/main.c
@@ -0,0 +1,25 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "i2c.h"
+
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/ztest.h>
+
+ZTEST(i2c_bindings, test_i2c_get_device)
+{
+	const struct device *accel0 = DEVICE_DT_GET(
+		DT_PHANDLE(DT_CHILD(NAMED_I2C_PORTS_NODE, accel_0), i2c_port));
+	const struct device *bmi_i2c = DEVICE_DT_GET(DT_NODELABEL(i2c0));
+
+	zassert_not_null(accel0, "accel0 was NULL");
+	zassert_not_null(bmi_i2c, "bmi_i2c was NULL");
+	zassert_equal(
+		accel0, bmi_i2c,
+		"named_i2c_ports/accel0 and bmi_i2c should resolve to the same device");
+}
+
+ZTEST_SUITE(i2c_bindings, NULL, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/i2c_dts/testcase.yaml b/zephyr/test/i2c_dts/testcase.yaml
new file mode 100644
index 0000000000..7b3d133a27
--- /dev/null
+++ b/zephyr/test/i2c_dts/testcase.yaml
@@ -0,0 +1,4 @@
+common:
+  platform_allow: native_posix
+tests:
+  i2c_dts.default: {}
diff --git a/zephyr/test/jump_tags/CMakeLists.txt b/zephyr/test/jump_tags/CMakeLists.txt
new file mode 100644
index 0000000000..710195275e
--- /dev/null
+++ b/zephyr/test/jump_tags/CMakeLists.txt
@@ -0,0 +1,13 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(jump_tags)
+
+# Include FFF fakes
+add_subdirectory(${PLATFORM_EC}/zephyr/test/test_utils test_utils)
+
+FILE(GLOB test_sources src/*.c)
+target_sources(app PRIVATE ${test_sources})
diff --git a/zephyr/test/jump_tags/boards/native_posix.overlay b/zephyr/test/jump_tags/boards/native_posix.overlay
new file mode 100644
index 0000000000..9f3238d076
--- /dev/null
+++ b/zephyr/test/jump_tags/boards/native_posix.overlay
@@ -0,0 +1,33 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <board-overlays/native_posix.dts>
+#include <cros/binman.dtsi>
+
+/ {
+	chosen {
+		cros-ec,flash = &flash1;
+		cros-ec,flash-controller = &cros_flash;
+	};
+	aliases {
+		gpio-wp = &gpio_wp_l;
+	};
+	named-gpios {
+		compatible = "named-gpios";
+		gpio_wp_l: wp_l {
+			gpios = <&gpio0 3 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+	};
+	cros_flash: cros-flash {
+		compatible = "cros-ec,flash-emul";
+	};
+	flash1: flash@64000000 {
+		reg = <0x64000000 DT_SIZE_K(512)>;
+	};
+};
+
+&gpio0 {
+	ngpios = <4>;
+};
diff --git a/zephyr/test/jump_tags/prj.conf b/zephyr/test/jump_tags/prj.conf
new file mode 100644
index 0000000000..4e39830c0a
--- /dev/null
+++ b/zephyr/test/jump_tags/prj.conf
@@ -0,0 +1,14 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_CROS_EC=y
+CONFIG_FLASH=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGEN=n
+CONFIG_PLATFORM_EC=y
+CONFIG_SERIAL=y
+CONFIG_SHELL_BACKEND_DUMMY=y
+CONFIG_SHELL_BACKEND_SERIAL=n
+CONFIG_SHIMMED_TASKS=y
+CONFIG_ZTEST_NEW_API=y
+CONFIG_ZTEST=y
diff --git a/zephyr/test/jump_tags/src/jump_tags.c b/zephyr/test/jump_tags/src/jump_tags.c
new file mode 100644
index 0000000000..a2a377bb35
--- /dev/null
+++ b/zephyr/test/jump_tags/src/jump_tags.c
@@ -0,0 +1,176 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "sysjump.h"
+#include "system.h"
+#include "system_fake.h"
+
+#include <setjmp.h>
+
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+#define TEST_BASIC_JUMP_TAG 0x9901
+#define TEST_MISSING_JUMP_TAG 0x9902
+#define TEST_MAX_JUMP_TAG 0x9903
+#define TEST_TOO_BIG_JUMP_TAG 0x9904
+
+#define TEST_JUMP_TAG_VERSION 1
+
+#define SOME_STR_VAL "JumpTagTest"
+
+void (*add_tag_func)(void);
+
+struct test_basic_jump_data_struct {
+	char some_str[32];
+};
+
+struct test_max_jump_data_struct {
+	char some_str[JUMP_TAG_MAX_SIZE];
+};
+
+struct test_too_big_jump_data_struct {
+	char some_str[JUMP_TAG_MAX_SIZE + 1];
+};
+
+static void system_before(void *data)
+{
+	add_tag_func = NULL;
+	system_common_pre_init();
+	system_set_shrspi_image_copy(EC_IMAGE_RO);
+}
+
+static void do_fake_sysjump(void)
+{
+	jmp_buf env;
+	enum ec_image target_image = system_get_image_copy() == EC_IMAGE_RO ?
+					     EC_IMAGE_RW :
+					     EC_IMAGE_RO;
+
+	if (!setjmp(env)) {
+		system_fake_setenv(&env);
+		system_run_image_copy(target_image);
+		zassert_unreachable();
+	}
+
+	system_set_shrspi_image_copy(target_image);
+	zassert_equal(system_get_image_copy(), target_image);
+}
+
+static void add_max_jump_tag(void)
+{
+	struct test_max_jump_data_struct max_tag = {
+		.some_str = SOME_STR_VAL,
+	};
+	zassert_ok(system_add_jump_tag(TEST_MAX_JUMP_TAG, TEST_JUMP_TAG_VERSION,
+				       sizeof(max_tag), &max_tag));
+}
+
+static void add_too_big_jump_tag(void)
+{
+	struct test_too_big_jump_data_struct too_big_tag = {
+		.some_str = SOME_STR_VAL,
+	};
+	zassert_equal(system_add_jump_tag(TEST_TOO_BIG_JUMP_TAG,
+					  TEST_JUMP_TAG_VERSION,
+					  sizeof(too_big_tag), &too_big_tag),
+		      EC_ERROR_INVAL);
+}
+
+static void add_too_many_jump_tags(void)
+{
+	int rv;
+	struct test_max_jump_data_struct max_tag = {
+		.some_str = SOME_STR_VAL,
+	};
+	/* Ensure at least one tag can be added, but not 10 */
+	for (int i = 0; i < 10; i++) {
+		rv = system_add_jump_tag(TEST_MAX_JUMP_TAG,
+					 TEST_JUMP_TAG_VERSION, sizeof(max_tag),
+					 &max_tag);
+		if (rv != 0) {
+			zassert_equal(rv, EC_ERROR_INVAL);
+			zassert_true(i > 0);
+			return;
+		}
+	}
+	zassert_unreachable(
+		"Adding too many jump tags failed to result in an error");
+}
+
+static void add_basic_jump_tag(void)
+{
+	struct test_basic_jump_data_struct basic_tag = {
+		.some_str = SOME_STR_VAL,
+	};
+	zassert_ok(system_add_jump_tag(TEST_BASIC_JUMP_TAG,
+				       TEST_JUMP_TAG_VERSION, sizeof(basic_tag),
+				       &basic_tag));
+}
+
+static void test_sysjump_hook(void)
+{
+	if (add_tag_func)
+		add_tag_func();
+}
+DECLARE_HOOK(HOOK_SYSJUMP, test_sysjump_hook, HOOK_PRIO_DEFAULT);
+
+static void check_for_jump_tag(int jump_tag, int expected_size)
+{
+	int version;
+	int size;
+	const unsigned char *data;
+
+	data = system_get_jump_tag(jump_tag, &version, &size);
+	zassert_equal(size, expected_size);
+	zassert_equal(version, TEST_JUMP_TAG_VERSION);
+	zassert_equal(strcmp(data, SOME_STR_VAL), 0);
+}
+
+ZTEST(jump_tags, test_get_missing_jump_tag)
+{
+	int version;
+	int size;
+	struct test_jump_data_struct *data;
+
+	data = (struct test_jump_data_struct *)system_get_jump_tag(
+		TEST_MISSING_JUMP_TAG, &version, &size);
+	zassert_equal(data, NULL);
+}
+
+ZTEST(jump_tags, test_add_max_jump_tag)
+{
+	add_tag_func = add_max_jump_tag;
+	do_fake_sysjump();
+	check_for_jump_tag(TEST_MAX_JUMP_TAG,
+			   sizeof(struct test_max_jump_data_struct));
+}
+
+ZTEST(jump_tags, test_too_big_jump_tag)
+{
+	add_tag_func = add_too_big_jump_tag;
+	do_fake_sysjump();
+}
+
+ZTEST(jump_tags, test_too_many_jump_tags)
+{
+	add_tag_func = add_too_many_jump_tags;
+	do_fake_sysjump();
+	check_for_jump_tag(TEST_MAX_JUMP_TAG,
+			   sizeof(struct test_max_jump_data_struct));
+}
+
+ZTEST(jump_tags, test_add_basic_jump_tag)
+{
+	add_tag_func = add_basic_jump_tag;
+	do_fake_sysjump();
+	check_for_jump_tag(TEST_BASIC_JUMP_TAG,
+			   sizeof(struct test_basic_jump_data_struct));
+}
+
+ZTEST_SUITE(jump_tags, NULL, NULL, system_before, NULL, NULL);
diff --git a/zephyr/test/jump_tags/testcase.yaml b/zephyr/test/jump_tags/testcase.yaml
new file mode 100644
index 0000000000..f00b53410c
--- /dev/null
+++ b/zephyr/test/jump_tags/testcase.yaml
@@ -0,0 +1,13 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+common:
+  platform_allow: native_posix
+tests:
+  jump_tags.default:
+    extra_configs:
+      - CONFIG_PLATFORM_EC_PRESERVED_END_OF_RAM_SIZE=1024
+    tags:
+      common
+      system
diff --git a/zephyr/test/kingler/CMakeLists.txt b/zephyr/test/kingler/CMakeLists.txt
new file mode 100644
index 0000000000..31f7b9cc2c
--- /dev/null
+++ b/zephyr/test/kingler/CMakeLists.txt
@@ -0,0 +1,55 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(kingler)
+
+add_subdirectory(${PLATFORM_EC}/zephyr/test/test_utils test_utils)
+
+zephyr_include_directories("${PLATFORM_EC_PROGRAM_DIR}/corsola/include")
+
+target_sources(app PRIVATE src/fakes.c)
+
+target_sources_ifdef(
+        CONFIG_TEST_KINGLER_USBC
+        app
+        PRIVATE
+        ${PLATFORM_EC_PROGRAM_DIR}/corsola/src/npcx_usbc.c
+        ${PLATFORM_EC_PROGRAM_DIR}/corsola/src/npcx_usb_pd_policy.c
+        ${PLATFORM_EC_PROGRAM_DIR}/corsola/src/usb_pd_policy.c
+        ${PLATFORM_EC_PROGRAM_DIR}/corsola/src/usbc.c
+        src/kingler_usbc.c)
+target_sources_ifdef(CONFIG_TEST_STEELIX_RUSTY app PRIVATE
+                     ${PLATFORM_EC_PROGRAM_DIR}/corsola/steelix/src/board.c)
+target_sources_ifdef(CONFIG_TEST_FORM_FACTOR_CONVERTIBLE app PRIVATE
+                     src/tablet.c)
+target_sources_ifdef(CONFIG_TEST_FORM_FACTOR_CLAMSHELL app PRIVATE
+                     src/clamshell.c)
+target_sources_ifdef(
+        CONFIG_VARIANT_CORSOLA_DB_DETECTION app PRIVATE
+        ${PLATFORM_EC_PROGRAM_DIR}/corsola/src/variant_db_detection.c)
+target_sources_ifdef(CONFIG_TEST_DB_DETECT_TYPEC app PRIVATE
+                     src/db_detect_typec.c)
+target_sources_ifdef(
+        CONFIG_TEST_DB_DETECT_HDMI
+        app
+        PRIVATE
+        src/db_detect_hdmi.c
+        ${PLATFORM_EC}/zephyr/shim/src/usb_muxes.c
+        ${PLATFORM_EC}/driver/usb_mux/usb_mux.c
+        ${PLATFORM_EC}/driver/usb_mux/virtual.c)
+target_sources_ifdef(CONFIG_TEST_DB_DETECT_NONE app PRIVATE
+                     src/db_detect_none.c)
+target_sources_ifdef(CONFIG_TEST_ALT_SENSOR_PROBE app PRIVATE src/alt_sensor.c)
+target_sources_ifdef(CONFIG_TEST_KINGLER_CCD app PRIVATE src/ccd.c
+                     ${PLATFORM_EC_PROGRAM_DIR}/corsola/src/board.c)
+target_sources_ifdef(CONFIG_TEST_VOLTORB app PRIVATE src/voltorb_usbc.c
+                     ${PLATFORM_EC_PROGRAM_DIR}/corsola/voltorb/src/usbc.c)
+target_sources_ifdef(
+        CONFIG_TEST_DB_DETECTION_USB_COUNT
+        app
+        PRIVATE
+        ${PLATFORM_EC_PROGRAM_DIR}/corsola/src/usbc.c
+        src/usb_port_count.c)
diff --git a/zephyr/test/kingler/Kconfig b/zephyr/test/kingler/Kconfig
new file mode 100644
index 0000000000..77c1f25253
--- /dev/null
+++ b/zephyr/test/kingler/Kconfig
@@ -0,0 +1,80 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config TEST_KINGLER_USBC
+	bool "Run the tests intended for kingler"
+	help
+	  Include USB-C tests into the binary.
+
+config TEST_STEELIX_RUSTY
+	bool "Run the tests intended for steelix and rusty"
+	help
+	  Include board_steelix.c into the binary to test the clamshell and
+	  convertible.
+
+config TEST_FORM_FACTOR_CLAMSHELL
+	bool "Run the tests intended for clamshells"
+	help
+	  Include clamshell tests into the binary.
+
+config TEST_FORM_FACTOR_CONVERTIBLE
+	bool "Run the tests intended for convertibles"
+	help
+	  Include convertible tests into the binary.
+
+config VARIANT_CORSOLA_DB_DETECTION
+	bool "Run the tests intended for corsola DB detection"
+	help
+	  Include variant_db_detection.c into the binary to test the type-c DB
+	  tests, HDMI DB tests and none DB tests.
+
+config TEST_DB_DETECT_TYPEC
+	bool "Run the tests intended for type-c DB"
+	help
+	  Include type-c DB tests into the binary.
+	  test for DB GPIOs and interrupt.
+
+config TEST_DB_DETECT_HDMI
+	bool "Run the tests intended for HDMI DB"
+	help
+	  Include HDMI DB tests into the binary.
+	  test for DB GPIOs and interrupt.
+
+config TEST_DB_DETECT_NONE
+	bool "Run the tests intended for none DB"
+	help
+	  Include none DB tests into the binary.
+	  test for DB GPIOs and interrupt.
+
+config TEST_ALT_SENSOR_PROBE
+	bool "Run the tests intended for alt sensor probe"
+	help
+	  Include alt_sensor.c into the binary to test the alt sensor probe via
+	  SSFC.
+
+config TEST_KINGLER_CCD
+	bool "Run the tests intended for alt sensor probe"
+	help
+	  Include alt_sensor.c into the binary to test the alt sensor probe via
+	  SSFC.
+
+config TEST_VOLTORB
+	bool "Run the tests intended for voltorb"
+	help
+	  Include voltorb_usbc.c into the binary to test the type-c output
+	  current limit function.
+
+config TEST_USB_PD_POLICY
+	bool "Run the tests intended for voltorb usb policy"
+	help
+	  Include voltorb_usbc.c into the binary to test the type-c output
+	  current limit function.
+
+config TEST_DB_DETECTION_USB_COUNT
+	bool "Run the tests intended for db detection"
+	help
+	  Include USB-C tests into the binary for testing the reported port
+	  count with db detection.
+
+source "Kconfig.zephyr"
diff --git a/zephyr/test/kingler/README.md b/zephyr/test/kingler/README.md
new file mode 100644
index 0000000000..84dadc105b
--- /dev/null
+++ b/zephyr/test/kingler/README.md
@@ -0,0 +1,3 @@
+Tests for board specific code under `zephyr/program/corsola/src/kingler`.
+
+Run with ./twister -T zephyr/test/kingler
diff --git a/zephyr/test/kingler/common.dtsi b/zephyr/test/kingler/common.dtsi
new file mode 100644
index 0000000000..e3b03c57a8
--- /dev/null
+++ b/zephyr/test/kingler/common.dtsi
@@ -0,0 +1,202 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <board-overlays/native_posix.dts>
+#include <dt-bindings/usb_pd_tcpm.h>
+#include <npcx_emul.dts>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+
+/ {
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_0>;
+			};
+		};
+		port1@1 {
+			compatible = "named-usbc-port";
+			reg = <1>;
+			usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_1>;
+			};
+			usb_mux_chain_1_hdmi_db: usb-mux-chain-1-hdmi-db {
+				compatible = "cros-ec,usb-mux-chain";
+				alternative-chain;
+				usb-muxes = <&virtual_mux_1>;
+			};
+		};
+		port0-muxes {
+			virtual_mux_0: virtual-mux-0 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+		port1-muxes {
+			virtual_mux_1: virtual-mux-1 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+	};
+
+	adc0: adc {
+		compatible = "zephyr,adc-emul";
+		nchannels = <6>;
+		ref-internal-mv = <3300>;
+		#io-channel-cells = <1>;
+		status = "okay";
+	};
+
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		adc_charger_pmon_r {
+			enum-name = "ADC_PSYS";
+			io-channels = <&adc0 0>;
+			/*
+			 * ISL9238C PSYS output is 1.44 uA/W over 33K resistor.
+			 */
+			mul = <21043>;
+		};
+		adc_ec_id0 {
+			enum-name = "ADC_ID_0";
+			io-channels = <&adc0 1>;
+		};
+		adc_ec_id1 {
+			enum-name = "ADC_ID_1";
+			io-channels = <&adc0 2>;
+		};
+		adc_charger_amon_r {
+			enum-name = "ADC_AMON_BMON";
+			io-channels = <&adc0 3>;
+			mul = <1000>;
+			div = <18>;
+		};
+	};
+
+	/* These are temporary just to get the test to build.
+	 * Should be replaced with the correct accel drivers,
+	 * but we're not testing that code right now anyway.
+	 */
+	motionsense-sensor-data {
+		bmi160_data: bmi160-drv-data {
+			compatible = "cros-ec,drvdata-bmi160";
+			status = "okay";
+		};
+	};
+	motionsense-sensor {
+		base_accel: ms-bmi160-accel {
+			compatible = "cros-ec,bmi160-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3_S5";
+			location = "MOTIONSENSE_LOC_BASE";
+			drv-data = <&bmi160_data>;
+			default-range = <4>;
+			i2c-spi-addr-flags = "BMI160_ADDR0_FLAGS";
+		};
+		lid_accel: ms-bmi160-accel2 {
+			compatible = "cros-ec,bmi160-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3_S5";
+			location = "MOTIONSENSE_LOC_BASE";
+			drv-data = <&bmi160_data>;
+			default-range = <4>;
+			i2c-spi-addr-flags = "BMI160_ADDR0_FLAGS";
+		};
+	};
+	motionsense-sensor-info {
+		compatible = "cros-ec,motionsense-sensor-info";
+
+		/*
+		 * list of GPIO interrupts that have to
+		 * be enabled at initial stage
+		 */
+		sensor-irqs = <&int_base_imu>;
+		/* list of sensors in force mode */
+		accel-force-mode-sensors = <&lid_accel>;
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+		i2c_sensor: i2c-sensor {
+			i2c-port = <&i2c_ctrl0>;
+			enum-names = "I2C_PORT_SENSOR";
+		};
+		i2c_eeprom: i2c-eeprom {
+			i2c-port = <&i2c_ctrl3>;
+			enum-names = "I2C_PORT_EEPROM", "I2C_PORT_BATTERY",
+					"I2C_PORT_CHARGER";
+		};
+	};
+	pinctrl: pinctrl {
+		compatible = "nuvoton,npcx-pinctrl";
+		status = "okay";
+		/* I2C peripheral interfaces */
+		/omit-if-no-ref/ i2c0_0_sda_scl_gpb4_b5: periph-i2c0-0 {
+			pinmux = <&alt2_i2c0_0_sl>;
+			periph-pupd = <0x00 0>;
+		};
+		/omit-if-no-ref/ i2c3_0_sda_scl_gpd0_d1: periph-i2c3-0 {
+			pinmux = <&alt2_i2c3_0_sl>;
+			periph-pupd = <0x00 6>;
+		};
+	};
+	npcx-alts-map {
+		compatible = "nuvoton,npcx-pinctrl-conf";
+		/* SCFG DEVALT 2 */
+		alt2_i2c0_0_sl: alt20 {
+			alts = <&scfg 0x02 0x0 0>;
+		};
+		alt2_i2c3_0_sl: alt26 {
+			alts = <&scfg 0x02 0x6 0>;
+		};
+	};
+};
+
+&i2c_ctrl0 {
+	status = "okay";
+
+
+	battery: sb@b {
+		compatible = "zephyr,smart-battery-emul";
+		status = "okay";
+		reg = <0xb>;
+		cycle-count = <99>;
+		version = "BATTERY_SPEC_VER_1_1_WITH_PEC";
+		/* Real battery voltages are multiples of 4.4V. */
+		desired-charg-volt = <5000>;
+		desired-charg-cur = <1000>;
+		mf-name = "LGC";
+		dev-name = "AC17A8M";
+	};
+};
+
+&i2c_ctrl2 {
+	status = "okay";
+};
+
+&i2c_ctrl3 {
+	status = "okay";
+
+	cbi_eeprom: eeprom@50 {
+		compatible = "atmel,at24";
+		reg = <0x50>;
+		size = <2048>;
+		pagesize = <16>;
+		address-width = <8>;
+		timeout = <5>;
+	};
+};
+
+&i2c_ctrl5 {
+	status = "okay";
+};
+
diff --git a/zephyr/test/kingler/kingler.default.overlay b/zephyr/test/kingler/kingler.default.overlay
new file mode 100644
index 0000000000..adc3f89451
--- /dev/null
+++ b/zephyr/test/kingler/kingler.default.overlay
@@ -0,0 +1,9 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.dtsi"
+#include "../program/corsola/npcx_interrupts.dtsi"
+#include "../program/corsola/npcx_gpio.dtsi"
+#include "../program/corsola/usba.dtsi"
diff --git a/zephyr/test/kingler/kingler.steelix.overlay b/zephyr/test/kingler/kingler.steelix.overlay
new file mode 100644
index 0000000000..f033ae92b7
--- /dev/null
+++ b/zephyr/test/kingler/kingler.steelix.overlay
@@ -0,0 +1,21 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.dtsi"
+#include "../program/corsola/npcx_interrupts.dtsi"
+#include "../program/corsola/npcx_gpio.dtsi"
+#include "../program/corsola/steelix/cbi.dtsi"
+#include "../program/corsola/steelix/interrupts.dtsi"
+
+/ {
+	aliases {
+		/*
+		 * motion sense's <>_INT_EVENT is handled
+		 * by alias. Using the alias, each driver creates
+		 * its own <>_INT_EVENT.
+		 */
+		lsm6dsm-int = &base_accel;
+	};
+};
diff --git a/zephyr/test/kingler/kingler.usbc.conf b/zephyr/test/kingler/kingler.usbc.conf
new file mode 100644
index 0000000000..cb04e5c550
--- /dev/null
+++ b/zephyr/test/kingler/kingler.usbc.conf
@@ -0,0 +1,28 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_PLATFORM_EC_TCPC_INTERRUPT=y
+CONFIG_PLATFORM_EC_USB_PORT_POWER_DUMB=y
+CONFIG_PLATFORM_EC_USBC=y
+CONFIG_PLATFORM_EC_USB_PORT_POWER_DUMB_CUSTOM_HOOK=y
+CONFIG_PLATFORM_EC_USBC_PPC=y
+CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y
+CONFIG_PLATFORM_EC_VBOOT_HASH=n
+CONFIG_PLATFORM_EC_SWITCH=n
+CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_BY_BOARD=y
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=20
+CONFIG_PLATFORM_EC_EXTPOWER=y
+CONFIG_PLATFORM_EC_HOSTCMD=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_ANX7447=y
+CONFIG_VARIANT_CORSOLA_DB_DETECTION=n
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
+CONFIG_PLATFORM_EC_CHARGER_ISL9238C=y
+CONFIG_PLATFORM_EC_CHARGE_MANAGER=y
+CONFIG_PLATFORM_EC_CHARGER=y
+CONFIG_PLATFORM_EC_LID_SWITCH=y
+CONFIG_PLATFORM_EC_CHARGE_RAMP_HW=y
+CONFIG_PLATFORM_EC_USB_CHARGER=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_ANX7447=y
diff --git a/zephyr/test/kingler/kingler.usbc.overlay b/zephyr/test/kingler/kingler.usbc.overlay
new file mode 100644
index 0000000000..60d10e2eb3
--- /dev/null
+++ b/zephyr/test/kingler/kingler.usbc.overlay
@@ -0,0 +1,125 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <dt-bindings/usb_pd_tcpm.h>
+
+#include "common.dtsi"
+#include "../program/corsola/npcx_interrupts.dtsi"
+#include "../program/corsola/npcx_gpio.dtsi"
+#include "../program/corsola/usba.dtsi"
+
+/ {
+	usbc {
+		port0@0 {
+			bc12 = <&pi3usb9201_emul0>;
+			tcpc = <&anx7447_emul0>;
+			ppc = <&nx20p348x_emul0>;
+			chg = <&charger_emul>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_0>;
+			};
+		};
+
+		port1@1 {
+			/* We have rt1718s emulator, but use tcpci_emul instead
+			 * for better test integration of the GPIO pin control.
+			 */
+			bc12 = <&bc12_port1>;
+			tcpc = <&rt1718s_emul1>;
+			ppc = <&nx20p348x_emul1>;
+			usb_mux_chain_1_hdmi_db: usb-mux-chain-1-hdmi-db {
+				compatible = "cros-ec,usb-mux-chain";
+				alternative-chain;
+				usb-muxes = <&virtual_mux_1>;
+			};
+		};
+	};
+
+	batteries {
+		default_battery: lgc_ac17a8m {
+			compatible = "lgc,ac17a8m", "battery-smart";
+			/**
+			 * this has to be strictly lower than the desired
+			 * voltage in smart battery emulator (5000mV).
+			 */
+			voltage_min = <4000>;
+		};
+	};
+};
+
+&i2c_ctrl0 {
+	anx7447_emul0: anx7447_emul@2c {
+		compatible = "cros,anx7447-tcpc-emul";
+		status = "okay";
+		reg = <0x2c>;
+		tcpc-flags = <(
+			TCPC_FLAGS_VBUS_MONITOR |
+			TCPC_FLAGS_ALERT_OD |
+			TCPC_FLAGS_CONTROL_VCONN |
+			TCPC_FLAGS_CONTROL_FRS)>;
+	};
+
+	/* TODO: drop this node when the Kconfig dependency is fixed. */
+	tcpci_emul0: tcpci_emul@82 {
+		compatible = "cros,tcpci-generic-emul";
+		status = "okay";
+		reg = <0x82>;
+	};
+
+	nx20p348x_emul0: nx20p348x_emul@71 {
+		compatible = "nxp,nx20p348x";
+		status = "okay";
+		reg = <0x71>;
+		irq-gpios = < &gpio6 7 GPIO_ACTIVE_HIGH>;
+	};
+
+	pi3usb9201_emul0: pi3usb9201@5d {
+		compatible = "pericom,pi3usb9201";
+		reg = <0x5d>;
+		irq = <&int_usb_c0_bc12>;
+	};
+};
+
+&i2c_ctrl3 {
+	status = "okay";
+
+	charger_emul: isl923x@9 {
+		compatible = "cros,isl923x-emul";
+		status = "okay";
+		reg = <0x9>;
+		battery = <&battery>;
+	};
+
+	rt1718s_emul1: rt1718s_emul@2c {
+		compatible = "cros,rt1718s-tcpc-emul", "richtek,rt1718s-tcpc";
+		status = "okay";
+		reg = <0x2c>;
+		tcpc-flags = <(TCPC_FLAGS_ALERT_OD |
+			TCPC_FLAGS_CONTROL_VCONN |
+			TCPC_FLAGS_CONTROL_FRS)>;
+	};
+
+	bc12_port1: rt1718s@2c {
+		compatible = "richtek,rt1718s-bc12", "cros,i2c-mock";
+		status = "okay";
+		reg = <0x2c>;
+	};
+
+	/* TODO: drop this node when the Kconfig dependency is fixed. */
+	tcpci_emul1: tcpci_emul@82 {
+		compatible = "cros,tcpci-generic-emul";
+		status = "okay";
+		reg = <0x82>;
+	};
+
+	nx20p348x_emul1: nx20p348x_emul@71 {
+	        compatible = "nxp,nx20p348x";
+	        status = "okay";
+	        reg = <0x71>;
+		irq-gpios = < &gpiod 4 GPIO_ACTIVE_HIGH >;
+	};
+};
diff --git a/zephyr/test/kingler/prj.conf b/zephyr/test/kingler/prj.conf
new file mode 100644
index 0000000000..bfa73043cd
--- /dev/null
+++ b/zephyr/test/kingler/prj.conf
@@ -0,0 +1,29 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_ZTEST=y
+CONFIG_ZTEST_ASSERT_VERBOSE=1
+CONFIG_ZTEST_NEW_API=y
+CONFIG_ASSERT=y
+CONFIG_EMUL=y
+CONFIG_PLATFORM_EC_HOOKS=y
+
+CONFIG_CROS_EC=y
+CONFIG_PLATFORM_EC=y
+
+CONFIG_PLATFORM_EC_GPIO_INIT_PRIORITY=49
+CONFIG_PLATFORM_EC_DYNAMIC_MOTION_SENSOR_COUNT=y
+CONFIG_PLATFORM_EC_GMR_TABLET_MODE=y
+CONFIG_PLATFORM_EC_TABLET_MODE=y
+CONFIG_PLATFORM_EC_LID_ANGLE=y
+
+CONFIG_I2C_NPCX=n
+
+CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=y
+CONFIG_EEPROM=y
+CONFIG_EEPROM_SIMULATOR=n
+CONFIG_EMUL_EEPROM_AT2X=y
+
+CONFIG_LOG=y
+CONFIG_LOG_MODE_MINIMAL=y
diff --git a/zephyr/test/kingler/src/alt_sensor.c b/zephyr/test/kingler/src/alt_sensor.c
new file mode 100644
index 0000000000..7cd0ceddfa
--- /dev/null
+++ b/zephyr/test/kingler/src/alt_sensor.c
@@ -0,0 +1,101 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "zephyr/kernel.h"
+
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/ztest.h>
+
+/* SSFC field defined in zephyr/program/corsola/cbi_steelix.dts */
+#define SSFC_BASE_MAIN_SENSOR (0x1)
+#define SSFC_BASE_ALT_SENSOR (0x1 << 1)
+
+#define SSFC_LID_MAIN_SENSOR (0x1 << 3)
+#define SSFC_LID_ALT_SENSOR (0x1 << 4)
+
+#define SSFC_MAIM_SENSORS (SSFC_LID_MAIN_SENSOR | SSFC_BASE_MAIN_SENSOR)
+#define SSFC_ALT_SENSORS (SSFC_LID_ALT_SENSOR | SSFC_BASE_ALT_SENSOR)
+
+static void *use_alt_sensor_setup(void)
+{
+	const struct device *wp_gpio =
+		DEVICE_DT_GET(DT_GPIO_CTLR(DT_ALIAS(gpio_wp), gpios));
+	const gpio_port_pins_t wp_pin = DT_GPIO_PIN(DT_ALIAS(gpio_wp), gpios);
+
+	/* Make sure that write protect is disabled */
+	zassert_ok(gpio_emul_input_set(wp_gpio, wp_pin, 1), NULL);
+	/* Set SSFC to enable alt sensors. */
+	zassert_ok(cbi_set_ssfc(SSFC_ALT_SENSORS), NULL);
+	/* Run init hooks to initialize cbi. */
+	hook_notify(HOOK_INIT);
+
+	return NULL;
+}
+
+ZTEST_SUITE(use_alt_sensor, NULL, use_alt_sensor_setup, NULL, NULL, NULL);
+
+static void *no_alt_sensor_setup(void)
+{
+	const struct device *wp_gpio =
+		DEVICE_DT_GET(DT_GPIO_CTLR(DT_ALIAS(gpio_wp), gpios));
+	const gpio_port_pins_t wp_pin = DT_GPIO_PIN(DT_ALIAS(gpio_wp), gpios);
+
+	/* Make sure that write protect is disabled */
+	zassert_ok(gpio_emul_input_set(wp_gpio, wp_pin, 1), NULL);
+	/* Set SSFC to disable alt sensors. */
+	zassert_ok(cbi_set_ssfc(SSFC_MAIM_SENSORS), NULL);
+	/* Run init hooks to initialize cbi. */
+	hook_notify(HOOK_INIT);
+
+	return NULL;
+}
+
+ZTEST_SUITE(no_alt_sensor, NULL, no_alt_sensor_setup, NULL, NULL, NULL);
+
+static int interrupt_id;
+
+void bmi3xx_interrupt(enum gpio_signal signal)
+{
+	interrupt_id = 1;
+}
+
+void lsm6dsm_interrupt(enum gpio_signal signal)
+{
+	interrupt_id = 2;
+}
+
+ZTEST(use_alt_sensor, test_use_alt_sensor)
+{
+	const struct device *base_imu_gpio = DEVICE_DT_GET(
+		DT_GPIO_CTLR(DT_NODELABEL(base_imu_int_l), gpios));
+	const gpio_port_pins_t base_imu_pin =
+		DT_GPIO_PIN(DT_NODELABEL(base_imu_int_l), gpios);
+
+	zassert_ok(gpio_emul_input_set(base_imu_gpio, base_imu_pin, 1), NULL);
+	k_sleep(K_MSEC(100));
+	zassert_ok(gpio_emul_input_set(base_imu_gpio, base_imu_pin, 0), NULL);
+	k_sleep(K_MSEC(100));
+
+	zassert_equal(interrupt_id, 2, "interrupt_id=%d", interrupt_id);
+}
+
+ZTEST(no_alt_sensor, test_no_alt_sensor)
+{
+	const struct device *base_imu_gpio = DEVICE_DT_GET(
+		DT_GPIO_CTLR(DT_NODELABEL(base_imu_int_l), gpios));
+	const gpio_port_pins_t base_imu_pin =
+		DT_GPIO_PIN(DT_NODELABEL(base_imu_int_l), gpios);
+
+	zassert_ok(gpio_emul_input_set(base_imu_gpio, base_imu_pin, 1), NULL);
+	k_sleep(K_MSEC(100));
+	zassert_ok(gpio_emul_input_set(base_imu_gpio, base_imu_pin, 0), NULL);
+	k_sleep(K_MSEC(100));
+
+	zassert_equal(interrupt_id, 1, "interrupt_id=%d", interrupt_id);
+}
diff --git a/zephyr/test/kingler/src/ccd.c b/zephyr/test/kingler/src/ccd.c
new file mode 100644
index 0000000000..eb375fcfe7
--- /dev/null
+++ b/zephyr/test/kingler/src/ccd.c
@@ -0,0 +1,110 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "gpio/gpio_int.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/fff.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+FAKE_VOID_FUNC(typec_set_sbu, int, bool);
+/* fake definitions to pass build */
+FAKE_VOID_FUNC(bmi3xx_interrupt, enum gpio_signal);
+FAKE_VOID_FUNC(x_ec_interrupt, enum gpio_signal);
+
+#define FFF_FAKES_LIST(FAKE)   \
+	FAKE(typec_set_sbu)    \
+	FAKE(bmi3xx_interrupt) \
+	FAKE(x_ec_interrupt)
+
+struct kingler_ccd_fixture {
+	int default_ccd_lvl;
+	int default_aux_path_lvl;
+};
+
+static void *ccd_setup(void)
+{
+	static struct kingler_ccd_fixture f;
+
+	return &f;
+}
+
+static void kingler_ccd_reset_rule_before(const struct ztest_unit_test *test,
+					  void *data)
+{
+	ARG_UNUSED(test);
+	ARG_UNUSED(data);
+	FFF_FAKES_LIST(RESET_FAKE);
+	FFF_RESET_HISTORY();
+}
+ZTEST_RULE(kingler_ccd_reset_rule, kingler_ccd_reset_rule_before, NULL);
+
+static void kingler_ccd_before(void *data)
+{
+	struct kingler_ccd_fixture *f = (struct kingler_ccd_fixture *)data;
+
+	f->default_ccd_lvl =
+		gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_ccd_mode_odl));
+	f->default_aux_path_lvl =
+		gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(dp_aux_path_sel));
+
+	zassert_ok(gpio_enable_dt_interrupt(
+		GPIO_INT_FROM_NODELABEL(int_ccd_mode_odl)));
+}
+
+static void kingler_ccd_after(void *data)
+{
+	struct kingler_ccd_fixture *f = (struct kingler_ccd_fixture *)data;
+
+	zassert_ok(gpio_disable_dt_interrupt(
+		GPIO_INT_FROM_NODELABEL(int_ccd_mode_odl)));
+	zassert_ok(gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ccd_mode_odl),
+				   f->default_ccd_lvl));
+	zassert_ok(gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(dp_aux_path_sel),
+				   f->default_aux_path_lvl));
+}
+
+ZTEST_SUITE(kingler_ccd, NULL, ccd_setup, kingler_ccd_before, kingler_ccd_after,
+	    NULL);
+
+ZTEST_F(kingler_ccd, test_dp_aux_path)
+{
+	const struct device *ccd_mode_odl_gpio = DEVICE_DT_GET(
+		DT_GPIO_CTLR(DT_NODELABEL(gpio_ccd_mode_odl), gpios));
+	const gpio_port_pins_t ccd_mode_odl_pin =
+		DT_GPIO_PIN(DT_NODELABEL(gpio_ccd_mode_odl), gpios);
+	const struct device *dp_aux_gpio = DEVICE_DT_GET(
+		DT_GPIO_CTLR(DT_NODELABEL(dp_aux_path_sel), gpios));
+	const gpio_port_pins_t dp_aux_pin =
+		DT_GPIO_PIN(DT_NODELABEL(dp_aux_path_sel), gpios);
+
+	/* reset CCD mode and mux AUX path to CCD port by default */
+	zassert_ok(gpio_emul_input_set(ccd_mode_odl_gpio, ccd_mode_odl_pin, 1),
+		   NULL);
+	zassert_ok(gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(dp_aux_path_sel), 0),
+		   NULL);
+	zassert_equal(0, gpio_emul_output_get(dp_aux_gpio, dp_aux_pin), NULL);
+
+	/* CCD asserts and trigger ccd_interrupt */
+	zassert_ok(gpio_emul_input_set(ccd_mode_odl_gpio, ccd_mode_odl_pin, 0),
+		   NULL);
+	k_sleep(K_MSEC(100));
+
+	zassert_equal(1, typec_set_sbu_fake.call_count, NULL);
+	/* CCD triggered, aux path has to be muxed to port 1 */
+	zassert_equal(1, gpio_emul_output_get(dp_aux_gpio, dp_aux_pin), NULL);
+
+	/* CCD deasserts */
+	zassert_ok(gpio_emul_input_set(ccd_mode_odl_gpio, ccd_mode_odl_pin, 1),
+		   NULL);
+
+	k_sleep(K_MSEC(100));
+	/* do not touch dp aux path when CCD deasserted */
+	zassert_equal(1, gpio_emul_output_get(dp_aux_gpio, dp_aux_pin), NULL);
+	zassert_equal(1, typec_set_sbu_fake.call_count, NULL);
+}
diff --git a/zephyr/test/kingler/src/clamshell.c b/zephyr/test/kingler/src/clamshell.c
new file mode 100644
index 0000000000..9871db1ca0
--- /dev/null
+++ b/zephyr/test/kingler/src/clamshell.c
@@ -0,0 +1,89 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "tablet_mode.h"
+#include "zephyr/kernel.h"
+
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/ztest.h>
+
+static void *clamshell_setup(void)
+{
+	uint32_t val;
+	const struct device *wp_gpio =
+		DEVICE_DT_GET(DT_GPIO_CTLR(DT_ALIAS(gpio_wp), gpios));
+	const gpio_port_pins_t wp_pin = DT_GPIO_PIN(DT_ALIAS(gpio_wp), gpios);
+
+	/* Make sure that write protect is disabled */
+	zassert_ok(gpio_emul_input_set(wp_gpio, wp_pin, 1), NULL);
+	/* Set CBI form factor to CONVERTIBLE. */
+	zassert_ok(cbi_set_fw_config(CLAMSHELL << 13), NULL);
+	/* Run init hooks to initialize cbi. */
+	hook_notify(HOOK_INIT);
+
+	/* Check if CBI write worked. */
+	zassert_ok(cros_cbi_get_fw_config(FORM_FACTOR, &val), NULL);
+	zassert_equal(CLAMSHELL, val, "val=%d", val);
+
+	return NULL;
+}
+
+ZTEST_SUITE(steelix_clamshell, NULL, clamshell_setup, NULL, NULL, NULL);
+
+ZTEST(steelix_clamshell, test_gmr_tablet_switch_disabled)
+{
+	const struct device *tablet_mode_gpio = DEVICE_DT_GET(
+		DT_GPIO_CTLR(DT_NODELABEL(gpio_tablet_mode_l), gpios));
+	const gpio_port_pins_t tablet_mode_pin =
+		DT_GPIO_PIN(DT_NODELABEL(gpio_tablet_mode_l), gpios);
+
+	/* Verify gmr_tablet_switch is disabled, by checking the side effects
+	 * of calling tablet_set_mode, and setting gpio_tablet_mode_l.
+	 */
+	zassert_ok(gpio_emul_input_set(tablet_mode_gpio, tablet_mode_pin, 0),
+		   NULL);
+	k_sleep(K_MSEC(100));
+	tablet_set_mode(1, TABLET_TRIGGER_LID);
+	zassert_equal(0, tablet_get_mode(), NULL);
+	zassert_ok(gpio_emul_input_set(tablet_mode_gpio, tablet_mode_pin, 1),
+		   NULL);
+	k_sleep(K_MSEC(100));
+	tablet_set_mode(0, TABLET_TRIGGER_LID);
+	zassert_equal(0, tablet_get_mode(), NULL);
+	zassert_ok(gpio_emul_input_set(tablet_mode_gpio, tablet_mode_pin, 0),
+		   NULL);
+	k_sleep(K_MSEC(100));
+	tablet_set_mode(1, TABLET_TRIGGER_LID);
+	zassert_equal(0, tablet_get_mode(), NULL);
+}
+
+static int interrupt_count;
+
+void bmi3xx_interrupt(enum gpio_signal signal)
+{
+	interrupt_count++;
+}
+
+ZTEST(steelix_clamshell, test_base_imu_irq_disabled)
+{
+	const struct device *base_imu_gpio = DEVICE_DT_GET(
+		DT_GPIO_CTLR(DT_NODELABEL(base_imu_int_l), gpios));
+	const gpio_port_pins_t base_imu_pin =
+		DT_GPIO_PIN(DT_NODELABEL(base_imu_int_l), gpios);
+
+	/* Verify base_imu_irq is disabled. */
+	interrupt_count = 0;
+	zassert_ok(gpio_emul_input_set(base_imu_gpio, base_imu_pin, 1), NULL);
+	k_sleep(K_MSEC(100));
+	zassert_ok(gpio_emul_input_set(base_imu_gpio, base_imu_pin, 0), NULL);
+	k_sleep(K_MSEC(100));
+
+	zassert_equal(interrupt_count, 0, "interrupt_count=%d",
+		      interrupt_count);
+}
diff --git a/zephyr/test/kingler/src/db_detect_hdmi.c b/zephyr/test/kingler/src/db_detect_hdmi.c
new file mode 100644
index 0000000000..04a65269ad
--- /dev/null
+++ b/zephyr/test/kingler/src/db_detect_hdmi.c
@@ -0,0 +1,133 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "baseboard_usbc_config.h"
+#include "ec_commands.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "usb_mux.h"
+#include "variant_db_detection.h"
+#include "zephyr/kernel.h"
+
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/fff.h>
+#include <zephyr/ztest.h>
+
+FAKE_VALUE_FUNC(int, corsola_is_dp_muxable, int);
+FAKE_VOID_FUNC(svdm_set_hpd_gpio, int, int);
+
+#define FFF_FAKES_LIST(FAKE)        \
+	FAKE(corsola_is_dp_muxable) \
+	FAKE(svdm_set_hpd_gpio)
+
+static void db_hdmi_rule_before(const struct ztest_unit_test *test, void *data)
+{
+	ARG_UNUSED(test);
+	ARG_UNUSED(data);
+	FFF_FAKES_LIST(RESET_FAKE);
+	FFF_RESET_HISTORY();
+}
+ZTEST_RULE(db_hdmi_rule, db_hdmi_rule_before, NULL);
+
+uint8_t board_get_usb_pd_port_count(void)
+{
+	return 2;
+}
+
+enum tcpc_cc_polarity pd_get_polarity(int port)
+{
+	return 0;
+}
+
+static void *db_detection_setup(void)
+{
+	const struct device *hdmi_prsnt_gpio = DEVICE_DT_GET(
+		DT_GPIO_CTLR(DT_NODELABEL(gpio_hdmi_prsnt_odl), gpios));
+	const gpio_port_pins_t hdmi_prsnt_pin =
+		DT_GPIO_PIN(DT_NODELABEL(gpio_hdmi_prsnt_odl), gpios);
+	/* Set the GPIO to low to indicate the DB is HDMI */
+	zassert_ok(gpio_emul_input_set(hdmi_prsnt_gpio, hdmi_prsnt_pin, 0),
+		   NULL);
+
+	hook_notify(HOOK_INIT);
+
+	return NULL;
+}
+
+ZTEST_SUITE(db_detection, NULL, db_detection_setup, NULL, NULL, NULL);
+
+static int interrupt_count;
+void x_ec_interrupt(enum gpio_signal signal)
+{
+	interrupt_count++;
+}
+
+/* test hdmi db case */
+ZTEST(db_detection, test_db_detect_hdmi)
+{
+	const struct device *en_hdmi_gpio =
+		DEVICE_DT_GET(DT_GPIO_CTLR(DT_ALIAS(gpio_en_hdmi_pwr), gpios));
+	const gpio_port_pins_t en_hdmi_pin =
+		DT_GPIO_PIN(DT_ALIAS(gpio_en_hdmi_pwr), gpios);
+	const struct device *ps185_pwrdn_gpio = DEVICE_DT_GET(
+		DT_GPIO_CTLR(DT_ALIAS(gpio_ps185_pwrdn_odl), gpios));
+	const gpio_port_pins_t ps185_pwrdn_pin =
+		DT_GPIO_PIN(DT_ALIAS(gpio_ps185_pwrdn_odl), gpios);
+	const struct device *int_x_ec_gpio = DEVICE_DT_GET(
+		DT_GPIO_CTLR(DT_NODELABEL(gpio_x_ec_gpio2), gpios));
+	const gpio_port_pins_t int_x_ec_pin =
+		DT_GPIO_PIN(DT_NODELABEL(gpio_x_ec_gpio2), gpios);
+
+	/* Check the DB type is HDMI */
+	zassert_equal(CORSOLA_DB_HDMI, corsola_get_db_type(), NULL);
+
+	/* Verify we can enable or disable hdmi power */
+	zassert_ok(gpio_pin_set_dt(GPIO_DT_FROM_ALIAS(gpio_en_hdmi_pwr), 1),
+		   NULL);
+	zassert_equal(1, gpio_emul_output_get(en_hdmi_gpio, en_hdmi_pin), NULL);
+	zassert_ok(gpio_pin_set_dt(GPIO_DT_FROM_ALIAS(gpio_en_hdmi_pwr), 0),
+		   NULL);
+	zassert_equal(0, gpio_emul_output_get(en_hdmi_gpio, en_hdmi_pin), NULL);
+
+	/* Verify we can change the gpio_ps185_pwrdn_odl state */
+	zassert_ok(gpio_pin_set_dt(GPIO_DT_FROM_ALIAS(gpio_ps185_pwrdn_odl), 1),
+		   NULL);
+	zassert_equal(1,
+		      gpio_emul_output_get(ps185_pwrdn_gpio, ps185_pwrdn_pin),
+		      NULL);
+	zassert_ok(gpio_pin_set_dt(GPIO_DT_FROM_ALIAS(gpio_ps185_pwrdn_odl), 0),
+		   NULL);
+	zassert_equal(0,
+		      gpio_emul_output_get(ps185_pwrdn_gpio, ps185_pwrdn_pin),
+		      NULL);
+
+	/* Verify x_ec_interrupt is enabled, and plug */
+	interrupt_count = 0;
+	zassert_ok(gpio_emul_input_set(int_x_ec_gpio, int_x_ec_pin, 1), NULL);
+	k_sleep(K_MSEC(100));
+
+	corsola_is_dp_muxable_fake.return_val = 1;
+
+	zassert_equal(interrupt_count, 1, "interrupt_count=%d",
+		      interrupt_count);
+
+	zassert_false(usb_mux_get(USBC_PORT_C1) & USB_PD_MUX_DP_ENABLED, NULL);
+
+	/* invoke hdmi interrupt, the argument doesn't care, just pass 0 */
+	hdmi_hpd_interrupt(0);
+
+	k_sleep(K_MSEC(500));
+
+	zassert_equal(svdm_set_hpd_gpio_fake.call_count, 1);
+	zassert_true(usb_mux_get(USBC_PORT_C1) & USB_PD_MUX_DP_ENABLED, NULL);
+
+	/* unplug */
+	zassert_ok(gpio_emul_input_set(int_x_ec_gpio, int_x_ec_pin, 0), NULL);
+
+	hdmi_hpd_interrupt(0);
+	k_sleep(K_MSEC(500));
+
+	zassert_false(usb_mux_get(USBC_PORT_C1) & USB_PD_MUX_DP_ENABLED, NULL);
+}
diff --git a/zephyr/test/kingler/src/db_detect_none.c b/zephyr/test/kingler/src/db_detect_none.c
new file mode 100644
index 0000000000..1bf9c05701
--- /dev/null
+++ b/zephyr/test/kingler/src/db_detect_none.c
@@ -0,0 +1,80 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "variant_db_detection.h"
+
+#include <stdlib.h>
+
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+static void *db_detection_setup(void)
+{
+	const struct device *wp_gpio =
+		DEVICE_DT_GET(DT_GPIO_CTLR(DT_ALIAS(gpio_wp), gpios));
+	const gpio_port_pins_t wp_pin = DT_GPIO_PIN(DT_ALIAS(gpio_wp), gpios);
+
+	/* Make sure that write protect is disabled */
+	zassert_ok(gpio_emul_input_set(wp_gpio, wp_pin, 1), NULL);
+	/* Set CBI db_config to DB_NONE. */
+	zassert_ok(cbi_set_fw_config(DB_NONE << 0), NULL);
+	/* Run init hooks to initialize cbi. */
+	hook_notify(HOOK_INIT);
+	return NULL;
+}
+
+ZTEST_SUITE(db_detection, NULL, db_detection_setup, NULL, NULL, NULL);
+
+static int interrupt_count;
+void x_ec_interrupt(enum gpio_signal signal)
+{
+	interrupt_count++;
+}
+
+/* test none db case */
+ZTEST(db_detection, test_db_detect_none)
+{
+	gpio_flags_t *flags = (gpio_flags_t *)malloc(sizeof(gpio_flags_t));
+
+	const struct device *ec_x_gpio1 = DEVICE_DT_GET(
+		DT_GPIO_CTLR(DT_NODELABEL(gpio_ec_x_gpio1), gpios));
+	gpio_pin_t ec_x_pin1 =
+		DT_GPIO_PIN(DT_NODELABEL(gpio_ec_x_gpio1), gpios);
+	const struct device *x_ec_gpio2 = DEVICE_DT_GET(
+		DT_GPIO_CTLR(DT_NODELABEL(gpio_x_ec_gpio2), gpios));
+	gpio_pin_t x_ec_pin2 =
+		DT_GPIO_PIN(DT_NODELABEL(gpio_x_ec_gpio2), gpios);
+	const struct device *ec_x_gpio3 = DEVICE_DT_GET(
+		DT_GPIO_CTLR(DT_NODELABEL(gpio_ec_x_gpio3), gpios));
+	gpio_pin_t ec_x_pin3 =
+		DT_GPIO_PIN(DT_NODELABEL(gpio_ec_x_gpio3), gpios);
+
+	/* Check the DB type is NONE */
+	zassert_equal(CORSOLA_DB_NONE, corsola_get_db_type(), NULL);
+
+	/* Verify the floating pins are input with PU to prevent leakage */
+	zassert_ok(gpio_emul_flags_get(ec_x_gpio1, ec_x_pin1, flags), NULL);
+	zassert_equal(*flags, (GPIO_INPUT | GPIO_PULL_UP), "flags=%d", *flags);
+	zassert_ok(gpio_emul_flags_get(x_ec_gpio2, x_ec_pin2, flags), NULL);
+	zassert_equal(*flags, (GPIO_INPUT | GPIO_PULL_UP), "flags=%d", *flags);
+	zassert_ok(gpio_emul_flags_get(ec_x_gpio3, ec_x_pin3, flags), NULL);
+	zassert_equal(*flags, (GPIO_INPUT | GPIO_PULL_UP), "flags=%d", *flags);
+	free(flags);
+
+	/* Verify x_ec_interrupt is disabled */
+	interrupt_count = 0;
+	zassert_ok(gpio_emul_input_set(x_ec_gpio2, x_ec_pin2, 0), NULL);
+	k_sleep(K_MSEC(100));
+	zassert_ok(gpio_emul_input_set(x_ec_gpio2, x_ec_pin2, 1), NULL);
+	k_sleep(K_MSEC(100));
+
+	zassert_equal(interrupt_count, 0, "interrupt_count=%d",
+		      interrupt_count);
+}
diff --git a/zephyr/test/kingler/src/db_detect_typec.c b/zephyr/test/kingler/src/db_detect_typec.c
new file mode 100644
index 0000000000..6662f485bc
--- /dev/null
+++ b/zephyr/test/kingler/src/db_detect_typec.c
@@ -0,0 +1,85 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "variant_db_detection.h"
+#include "zephyr/kernel.h"
+
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/ztest.h>
+
+static void *db_detection_setup(void)
+{
+	const struct device *hdmi_prsnt_gpio = DEVICE_DT_GET(
+		DT_GPIO_CTLR(DT_NODELABEL(gpio_hdmi_prsnt_odl), gpios));
+	const gpio_port_pins_t hdmi_prsnt_pin =
+		DT_GPIO_PIN(DT_NODELABEL(gpio_hdmi_prsnt_odl), gpios);
+	/* Set the GPIO to high to indicate the DB is type-c */
+	zassert_ok(gpio_emul_input_set(hdmi_prsnt_gpio, hdmi_prsnt_pin, 1),
+		   NULL);
+
+	hook_notify(HOOK_INIT);
+
+	return NULL;
+}
+
+ZTEST_SUITE(db_detection, NULL, db_detection_setup, NULL, NULL, NULL);
+
+static int interrupt_count;
+void x_ec_interrupt(enum gpio_signal signal)
+{
+	interrupt_count++;
+}
+
+/* test typec db case */
+ZTEST(db_detection, test_db_detect_typec)
+{
+	const struct device *en_frs_gpio = DEVICE_DT_GET(
+		DT_GPIO_CTLR(DT_ALIAS(gpio_usb_c1_frs_en), gpios));
+	const gpio_port_pins_t en_frs_pin =
+		DT_GPIO_PIN(DT_ALIAS(gpio_usb_c1_frs_en), gpios);
+	const struct device *c1_dp_in_hpd_gpio = DEVICE_DT_GET(
+		DT_GPIO_CTLR(DT_ALIAS(gpio_usb_c1_dp_in_hpd), gpios));
+	const gpio_port_pins_t c1_dp_in_hpd_pin =
+		DT_GPIO_PIN(DT_ALIAS(gpio_usb_c1_dp_in_hpd), gpios);
+	const struct device *int_x_ec_gpio = DEVICE_DT_GET(
+		DT_GPIO_CTLR(DT_NODELABEL(gpio_x_ec_gpio2), gpios));
+	const gpio_port_pins_t int_x_ec_pin =
+		DT_GPIO_PIN(DT_NODELABEL(gpio_x_ec_gpio2), gpios);
+
+	/* Check the DB type is type-c */
+	zassert_equal(CORSOLA_DB_TYPEC, corsola_get_db_type(), NULL);
+
+	/* Verify we can enable or disable FRS by setting gpio_usb_c1_frs_en */
+	zassert_ok(gpio_pin_set_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_frs_en), 1),
+		   NULL);
+	zassert_equal(1, gpio_emul_output_get(en_frs_gpio, en_frs_pin), NULL);
+	zassert_ok(gpio_pin_set_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_frs_en), 0),
+		   NULL);
+	zassert_equal(0, gpio_emul_output_get(en_frs_gpio, en_frs_pin), NULL);
+
+	/* Verify we can change the gpio_usb_c1_dp_in_hpd state */
+	zassert_ok(gpio_pin_set_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_dp_in_hpd),
+				   1),
+		   NULL);
+	zassert_equal(1,
+		      gpio_emul_output_get(c1_dp_in_hpd_gpio, c1_dp_in_hpd_pin),
+		      NULL);
+	zassert_ok(gpio_pin_set_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_dp_in_hpd),
+				   0),
+		   NULL);
+	zassert_equal(0,
+		      gpio_emul_output_get(c1_dp_in_hpd_gpio, c1_dp_in_hpd_pin),
+		      NULL);
+
+	/* Verify x_ec_interrupt is enabled */
+	interrupt_count = 0;
+	zassert_ok(gpio_emul_input_set(int_x_ec_gpio, int_x_ec_pin, 0), NULL);
+	k_sleep(K_MSEC(100));
+
+	zassert_equal(interrupt_count, 1, "interrupt_count=%d",
+		      interrupt_count);
+}
diff --git a/zephyr/test/kingler/src/fakes.c b/zephyr/test/kingler/src/fakes.c
new file mode 100644
index 0000000000..c4a7cf0a6d
--- /dev/null
+++ b/zephyr/test/kingler/src/fakes.c
@@ -0,0 +1,47 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "gpio_signal.h"
+
+#include <zephyr/fff.h>
+
+FAKE_VOID_FUNC(power_button_interrupt, enum gpio_signal);
+FAKE_VOID_FUNC(button_interrupt, enum gpio_signal);
+FAKE_VOID_FUNC(chipset_reset_request_interrupt, enum gpio_signal);
+FAKE_VOID_FUNC(power_signal_interrupt, enum gpio_signal);
+FAKE_VOID_FUNC(chipset_watchdog_interrupt, enum gpio_signal);
+FAKE_VOID_FUNC(extpower_interrupt, enum gpio_signal);
+FAKE_VOID_FUNC(switch_interrupt, enum gpio_signal);
+#if !(defined(CONFIG_TEST_KINGLER_USBC) || \
+      defined(CONFIG_TEST_DB_DETECTION_USB_COUNT))
+FAKE_VOID_FUNC(xhci_interrupt, enum gpio_signal);
+#endif
+#ifndef CONFIG_TEST_KINGLER_USBC
+FAKE_VOID_FUNC(lid_interrupt, enum gpio_signal);
+FAKE_VOID_FUNC(usb_a0_interrupt, enum gpio_signal);
+FAKE_VOID_FUNC(tcpc_alert_event, enum gpio_signal);
+FAKE_VOID_FUNC(ppc_interrupt, enum gpio_signal);
+FAKE_VOID_FUNC(bc12_interrupt, enum gpio_signal);
+FAKE_VOID_FUNC(pd_power_supply_reset, int);
+FAKE_VOID_FUNC(pd_set_power_supply_ready, int);
+FAKE_VALUE_FUNC(int, board_set_active_charge_port, int);
+FAKE_VALUE_FUNC(int, pd_snk_is_vbus_provided, int);
+FAKE_VALUE_FUNC(int, pd_check_vconn_swap, int);
+#endif
+FAKE_VOID_FUNC(chipset_warm_reset_interrupt, enum gpio_signal);
+#ifndef CONFIG_TEST_KINGLER_CCD
+FAKE_VOID_FUNC(ccd_interrupt, enum gpio_signal);
+#endif
+
+#ifdef CONFIG_TEST_STEELIX_RUSTY
+FAKE_VOID_FUNC(x_ec_interrupt, enum gpio_signal);
+FAKE_VOID_FUNC(motion_sensors_check_ssfc);
+#else
+FAKE_VOID_FUNC(motion_interrupt, enum gpio_signal);
+#endif
+
+#ifdef CONFIG_VARIANT_CORSOLA_DB_DETECTION
+FAKE_VOID_FUNC(bmi3xx_interrupt, enum gpio_signal);
+#endif
diff --git a/zephyr/test/kingler/src/kingler_usbc.c b/zephyr/test/kingler/src/kingler_usbc.c
new file mode 100644
index 0000000000..afd8cdbccd
--- /dev/null
+++ b/zephyr/test/kingler/src/kingler_usbc.c
@@ -0,0 +1,78 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/tcpm/tcpm.h"
+#include "ec_app_main.h"
+#include "usb_charge.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+#include "variant_db_detection.h"
+
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/fff.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/ztest.h>
+
+#define LOG_LEVEL 0
+LOG_MODULE_REGISTER(npcx_usbc);
+
+FAKE_VALUE_FUNC(enum corsola_db_type, corsola_get_db_type);
+FAKE_VALUE_FUNC(bool, in_interrupt_context);
+FAKE_VOID_FUNC(bmi3xx_interrupt);
+FAKE_VOID_FUNC(hdmi_hpd_interrupt);
+FAKE_VOID_FUNC(ps185_hdmi_hpd_mux_set);
+FAKE_VALUE_FUNC(bool, ps8743_field_update, const struct usb_mux *, uint8_t,
+		uint8_t, uint8_t);
+
+#define FFF_FAKES_LIST(FAKE)         \
+	FAKE(corsola_get_db_type)    \
+	FAKE(in_interrupt_context)   \
+	FAKE(bmi3xx_interrupt)       \
+	FAKE(hdmi_hpd_interrupt)     \
+	FAKE(ps185_hdmi_hpd_mux_set) \
+	FAKE(ps8743_field_update)
+
+struct kingler_usbc_fixture {
+	int place_holder;
+};
+
+static void *kingler_usbc_setup(void)
+{
+	static struct kingler_usbc_fixture f;
+
+	return &f;
+}
+
+static void kingler_usbc_reset_rule_before(const struct ztest_unit_test *test,
+					   void *data)
+{
+	ARG_UNUSED(test);
+	ARG_UNUSED(data);
+	FFF_FAKES_LIST(RESET_FAKE);
+	FFF_RESET_HISTORY();
+}
+
+ZTEST_RULE(kingler_usbc_reset_rule, kingler_usbc_reset_rule_before, NULL);
+ZTEST_SUITE(kingler_usbc, NULL, kingler_usbc_setup, NULL, NULL, NULL);
+
+ZTEST_F(kingler_usbc, test_power_supply)
+{
+	pd_power_supply_reset(0);
+	zassert_equal(0, ppc_is_sourcing_vbus(0));
+	zassert_equal(0, ppc_is_sourcing_vbus(1));
+
+	zassert_equal(EC_SUCCESS, pd_set_power_supply_ready(0));
+	zassert_equal(1, ppc_is_sourcing_vbus(0));
+	zassert_equal(0, ppc_is_sourcing_vbus(1));
+
+	pd_power_supply_reset(0);
+	zassert_equal(0, ppc_is_sourcing_vbus(0));
+	zassert_equal(0, ppc_is_sourcing_vbus(1));
+
+	/* TODO: test C1 port after resolve the PPC emulator always accessing
+	 * the same one with different index.
+	 */
+}
diff --git a/zephyr/test/kingler/src/tablet.c b/zephyr/test/kingler/src/tablet.c
new file mode 100644
index 0000000000..a2355e2b9d
--- /dev/null
+++ b/zephyr/test/kingler/src/tablet.c
@@ -0,0 +1,91 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "tablet_mode.h"
+#include "zephyr/kernel.h"
+
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/ztest.h>
+
+static void *tablet_setup(void)
+{
+	uint32_t val;
+	const struct device *wp_gpio =
+		DEVICE_DT_GET(DT_GPIO_CTLR(DT_ALIAS(gpio_wp), gpios));
+	const gpio_port_pins_t wp_pin = DT_GPIO_PIN(DT_ALIAS(gpio_wp), gpios);
+
+	/* Make sure that write protect is disabled */
+	zassert_ok(gpio_emul_input_set(wp_gpio, wp_pin, 1), NULL);
+	/* Set CBI form factor to CONVERTIBLE. */
+	zassert_ok(cbi_set_fw_config(CONVERTIBLE << 13), NULL);
+	/* Run init hooks to initialize cbi. */
+	hook_notify(HOOK_INIT);
+
+	/* Check if CBI write worked. */
+	zassert_ok(cros_cbi_get_fw_config(FORM_FACTOR, &val), NULL);
+	zassert_equal(CONVERTIBLE, val, "val=%d", val);
+
+	return NULL;
+}
+
+ZTEST_SUITE(steelix_tablet, NULL, tablet_setup, NULL, NULL, NULL);
+
+ZTEST(steelix_tablet, test_gmr_tablet_switch_enabled)
+{
+	const struct device *tablet_mode_gpio = DEVICE_DT_GET(
+		DT_GPIO_CTLR(DT_NODELABEL(gpio_tablet_mode_l), gpios));
+	const gpio_port_pins_t tablet_mode_pin =
+		DT_GPIO_PIN(DT_NODELABEL(gpio_tablet_mode_l), gpios);
+
+	/* Verify gmr_tablet_switch is enabled, by checking the side effects
+	 * of calling tablet_set_mode, and setting gpio_tablet_mode_l.
+	 */
+	zassert_ok(gpio_emul_input_set(tablet_mode_gpio, tablet_mode_pin, 0),
+		   NULL);
+	k_sleep(K_MSEC(100));
+	tablet_set_mode(1, TABLET_TRIGGER_LID);
+	zassert_equal(1, tablet_get_mode(), NULL);
+	zassert_ok(gpio_emul_input_set(tablet_mode_gpio, tablet_mode_pin, 1),
+		   NULL);
+	k_sleep(K_MSEC(100));
+	tablet_set_mode(0, TABLET_TRIGGER_LID);
+	zassert_equal(0, tablet_get_mode(), NULL);
+	zassert_ok(gpio_emul_input_set(tablet_mode_gpio, tablet_mode_pin, 0),
+		   NULL);
+	k_sleep(K_MSEC(100));
+	tablet_set_mode(1, TABLET_TRIGGER_LID);
+	zassert_equal(1, tablet_get_mode(), NULL);
+}
+
+static int interrupt_count;
+
+void bmi3xx_interrupt(enum gpio_signal signal)
+{
+	interrupt_count++;
+}
+
+ZTEST(steelix_tablet, test_base_imu_irq_enabled)
+{
+	const struct device *base_imu_gpio = DEVICE_DT_GET(
+		DT_GPIO_CTLR(DT_NODELABEL(base_imu_int_l), gpios));
+	const gpio_port_pins_t base_imu_pin =
+		DT_GPIO_PIN(DT_NODELABEL(base_imu_int_l), gpios);
+
+	/* Verify base_imu_irq is enabled. Interrupt is configured
+	 * GPIO_INT_EDGE_FALLING, so set high, then set low.
+	 */
+	interrupt_count = 0;
+	zassert_ok(gpio_emul_input_set(base_imu_gpio, base_imu_pin, 1), NULL);
+	k_sleep(K_MSEC(100));
+	zassert_ok(gpio_emul_input_set(base_imu_gpio, base_imu_pin, 0), NULL);
+	k_sleep(K_MSEC(100));
+
+	zassert_equal(interrupt_count, 1, "interrupt_count=%d",
+		      interrupt_count);
+}
diff --git a/zephyr/test/kingler/src/usb_port_count.c b/zephyr/test/kingler/src/usb_port_count.c
new file mode 100644
index 0000000000..4f55bdc693
--- /dev/null
+++ b/zephyr/test/kingler/src/usb_port_count.c
@@ -0,0 +1,90 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/tcpm/tcpm.h"
+#include "ec_app_main.h"
+#include "usb_charge.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+#include "variant_db_detection.h"
+
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/fff.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/ztest.h>
+
+#define LOG_LEVEL 0
+LOG_MODULE_REGISTER(usb_port_count);
+
+FAKE_VALUE_FUNC(enum corsola_db_type, corsola_get_db_type);
+FAKE_VALUE_FUNC(bool, in_interrupt_context);
+FAKE_VOID_FUNC(bmi3xx_interrupt);
+FAKE_VOID_FUNC(hdmi_hpd_interrupt);
+FAKE_VOID_FUNC(ps185_hdmi_hpd_mux_set);
+FAKE_VALUE_FUNC(bool, ps8743_field_update, const struct usb_mux *, uint8_t,
+		uint8_t, uint8_t);
+FAKE_VOID_FUNC(pd_set_dual_role, int, enum pd_dual_role_states);
+FAKE_VALUE_FUNC(int, tc_is_attached_src, int);
+
+#define FFF_FAKES_LIST(FAKE)         \
+	FAKE(corsola_get_db_type)    \
+	FAKE(in_interrupt_context)   \
+	FAKE(bmi3xx_interrupt)       \
+	FAKE(hdmi_hpd_interrupt)     \
+	FAKE(ps185_hdmi_hpd_mux_set) \
+	FAKE(ps8743_field_update)    \
+	FAKE(pd_set_dual_role)       \
+	FAKE(tc_is_attached_src)
+
+struct usb_port_count_fixture {
+	int place_holder;
+};
+
+static void *usb_port_count_setup(void)
+{
+	static struct usb_port_count_fixture f;
+
+	return &f;
+}
+
+static void usb_port_count_reset_rule_before(const struct ztest_unit_test *test,
+					     void *data)
+{
+	ARG_UNUSED(test);
+	ARG_UNUSED(data);
+	FFF_FAKES_LIST(RESET_FAKE);
+	FFF_RESET_HISTORY();
+}
+
+ZTEST_RULE(usb_port_count_reset_rule, usb_port_count_reset_rule_before, NULL);
+ZTEST_SUITE(usb_port_count, NULL, usb_port_count_setup, NULL, NULL, NULL);
+
+ZTEST_F(usb_port_count, test_detect_db)
+{
+	struct {
+		enum corsola_db_type test_type;
+		int expected_board_get_port_count;
+		int expected_board_get_adjusted_port_count;
+	} testdata[] = { { CORSOLA_DB_UNINIT, CONFIG_USB_PD_PORT_MAX_COUNT,
+			   CONFIG_USB_PD_PORT_MAX_COUNT - 1 },
+			 { CORSOLA_DB_NO_DETECTION,
+			   CONFIG_USB_PD_PORT_MAX_COUNT,
+			   CONFIG_USB_PD_PORT_MAX_COUNT },
+			 { CORSOLA_DB_NONE, CONFIG_USB_PD_PORT_MAX_COUNT - 1,
+			   CONFIG_USB_PD_PORT_MAX_COUNT - 1 },
+			 { CORSOLA_DB_TYPEC, CONFIG_USB_PD_PORT_MAX_COUNT,
+			   CONFIG_USB_PD_PORT_MAX_COUNT },
+			 { CORSOLA_DB_HDMI, CONFIG_USB_PD_PORT_MAX_COUNT - 1,
+			   CONFIG_USB_PD_PORT_MAX_COUNT - 1 } };
+	for (int i = 0; i < ARRAY_SIZE(testdata); i++) {
+		corsola_get_db_type_fake.return_val = testdata[i].test_type;
+		zassert_equal(board_get_usb_pd_port_count(),
+			      testdata[i].expected_board_get_port_count);
+		zassert_equal(
+			board_get_adjusted_usb_pd_port_count(),
+			testdata[i].expected_board_get_adjusted_port_count);
+	}
+}
diff --git a/zephyr/test/kingler/src/voltorb_usbc.c b/zephyr/test/kingler/src/voltorb_usbc.c
new file mode 100644
index 0000000000..c325f86221
--- /dev/null
+++ b/zephyr/test/kingler/src/voltorb_usbc.c
@@ -0,0 +1,93 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "chipset.h"
+#include "hooks.h"
+#include "usb_pd.h"
+#include "usb_pd_dpm_sm.h"
+
+#include <zephyr/fff.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+#define PDO_FIXED_FLAGS \
+	(PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP | PDO_FIXED_COMM_CAP)
+
+FAKE_VALUE_FUNC(int, charge_get_percent);
+FAKE_VALUE_FUNC(int, chipset_in_state, int);
+FAKE_VALUE_FUNC(int, tc_is_attached_src, int);
+
+FAKE_VOID_FUNC(x_ec_interrupt);
+FAKE_VOID_FUNC(bmi3xx_interrupt);
+FAKE_VOID_FUNC(pd_update_contract, int);
+FAKE_VOID_FUNC(check_src_port);
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, check_src_port, HOOK_PRIO_DEFAULT);
+FAKE_VOID_FUNC(resume_src_port);
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, resume_src_port, HOOK_PRIO_DEFAULT);
+
+enum chipset_state_mask fake_chipset_state;
+
+int chipset_in_state_mock(int state_mask)
+{
+	return state_mask & fake_chipset_state;
+}
+
+int tc_is_attached_src_mock(int port)
+{
+	/* Assume type-c port role is source */
+	return 1;
+}
+
+uint8_t board_get_usb_pd_port_count(void)
+{
+	return 2;
+}
+
+ZTEST(current_limit, test_check_src_port)
+{
+	const int fake_port = 0;
+	const uint32_t *fake_pdo;
+
+	tc_is_attached_src_fake.custom_fake = tc_is_attached_src_mock;
+	chipset_in_state_fake.custom_fake = chipset_in_state_mock;
+
+	charge_get_percent_fake.return_val = 20;
+	fake_chipset_state = CHIPSET_STATE_SUSPEND;
+	hook_notify(HOOK_CHIPSET_SUSPEND);
+	k_sleep(K_SECONDS(3));
+	zassert_equal(1, check_src_port_fake.call_count);
+	zassert_equal(1, dpm_get_source_pdo(&fake_pdo, fake_port));
+
+	charge_get_percent_fake.return_val = 40;
+	fake_chipset_state = CHIPSET_STATE_SUSPEND;
+	hook_notify(HOOK_CHIPSET_SUSPEND);
+	k_sleep(K_SECONDS(3));
+	zassert_equal(2, check_src_port_fake.call_count);
+
+	fake_chipset_state = CHIPSET_STATE_SOFT_OFF;
+	hook_notify(HOOK_CHIPSET_SUSPEND);
+	k_sleep(K_SECONDS(33));
+	zassert_equal(3, check_src_port_fake.call_count);
+	zassert_equal(1, dpm_get_source_pdo(&fake_pdo, fake_port));
+
+	/* Assume type-c port role is sink */
+	tc_is_attached_src_fake.custom_fake = NULL;
+	tc_is_attached_src_fake.return_val = 0;
+	hook_notify(HOOK_CHIPSET_SUSPEND);
+	k_sleep(K_SECONDS(3));
+	zassert_equal(4, check_src_port_fake.call_count);
+}
+
+ZTEST(current_limit, test_resume_src_port)
+{
+	tc_is_attached_src_fake.custom_fake = tc_is_attached_src_mock;
+	chipset_in_state_fake.custom_fake = chipset_in_state_mock;
+	fake_chipset_state = CHIPSET_STATE_ON;
+	hook_notify(HOOK_CHIPSET_RESUME);
+	k_sleep(K_SECONDS(3));
+	zassert_equal(1, resume_src_port_fake.call_count);
+}
+
+ZTEST_SUITE(current_limit, NULL, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/kingler/testcase.yaml b/zephyr/test/kingler/testcase.yaml
new file mode 100644
index 0000000000..8012c7dc4f
--- /dev/null
+++ b/zephyr/test/kingler/testcase.yaml
@@ -0,0 +1,65 @@
+common:
+  platform_allow: native_posix
+tests:
+  kingler.usbc:
+    extra_configs:
+    - CONFIG_TEST_KINGLER_USBC=y
+    extra_conf_files:
+    - prj.conf
+    - kingler.usbc.conf
+    extra_dtc_overlay_files:
+    - kingler.usbc.overlay
+  kingler.steelix:
+    extra_configs:
+    - CONFIG_TEST_STEELIX_RUSTY=y
+    - CONFIG_TEST_FORM_FACTOR_CONVERTIBLE=y
+    - CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSM=y
+    extra_dtc_overlay_files:
+    - kingler.steelix.overlay
+  kingler.rusty:
+    extra_configs:
+    - CONFIG_TEST_STEELIX_RUSTY=y
+    - CONFIG_TEST_FORM_FACTOR_CLAMSHELL=y
+    - CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSM=y
+    extra_dtc_overlay_files:
+    - kingler.steelix.overlay
+  kingler.db_detect_typec:
+    extra_configs:
+    - CONFIG_TEST_DB_DETECT_TYPEC=y
+    - CONFIG_VARIANT_CORSOLA_DB_DETECTION=y
+    extra_dtc_overlay_files:
+    - kingler.default.overlay
+  kingler.db_detect_hdmi:
+    extra_configs:
+    - CONFIG_TEST_DB_DETECT_HDMI=y
+    - CONFIG_VARIANT_CORSOLA_DB_DETECTION=y
+    extra_dtc_overlay_files:
+    - kingler.default.overlay
+  kingler.db_detect_none:
+    extra_configs:
+    - CONFIG_TEST_DB_DETECT_NONE=y
+    - CONFIG_VARIANT_CORSOLA_DB_DETECTION=y
+    extra_dtc_overlay_files:
+    - kingler.steelix.overlay
+  kingler.ccd:
+    extra_configs:
+    - CONFIG_TEST_KINGLER_CCD=y
+    extra_dtc_overlay_files:
+    - kingler.default.overlay
+  kingler.alt_sensor:
+    extra_configs:
+    - CONFIG_TEST_STEELIX_RUSTY=y
+    - CONFIG_TEST_ALT_SENSOR_PROBE=y
+    extra_dtc_overlay_files:
+    - kingler.steelix.overlay
+  kingler.voltorb:
+    extra_configs:
+    - CONFIG_TEST_VOLTORB=y
+    - CONFIG_TEST_USB_PD_POLICY=y
+    extra_dtc_overlay_files:
+    - kingler.default.overlay
+  kingler.usb_port_count:
+    extra_configs:
+    - CONFIG_TEST_DB_DETECTION_USB_COUNT=y
+    extra_dtc_overlay_files:
+    - kingler.default.overlay
diff --git a/zephyr/test/krabby/CMakeLists.txt b/zephyr/test/krabby/CMakeLists.txt
new file mode 100644
index 0000000000..529bb24682
--- /dev/null
+++ b/zephyr/test/krabby/CMakeLists.txt
@@ -0,0 +1,39 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(krabby)
+
+add_subdirectory(${PLATFORM_EC}/zephyr/test/test_utils test_utils)
+
+zephyr_include_directories(
+	"${PLATFORM_EC_PROGRAM_DIR}/corsola/include"
+	include)
+
+target_sources(app PRIVATE
+	src/stubs.c
+	${PLATFORM_EC_PROGRAM_DIR}/corsola/src/ite_usbc.c
+	${PLATFORM_EC_PROGRAM_DIR}/corsola/src/ite_usb_pd_policy.c
+	${PLATFORM_EC_PROGRAM_DIR}/corsola/src/usb_pd_policy.c)
+
+target_sources_ifdef(CONFIG_TEST_KRABBY
+	app PRIVATE
+	src/charger_workaround.c
+	src/main.c
+	src/power_seq.c
+	src/usb_mux_init.c
+	src/usbc_config.c
+	${PLATFORM_EC_PROGRAM_DIR}/corsola/src/ite_charger_workaround.c)
+
+target_sources_ifdef(CONFIG_TEST_TENTACRUEL
+	app PRIVATE
+	src/fake.c
+	src/ppc_tentacruel.c
+	src/temp_tentacruel.c
+	src/fwconfig_tentacruel.c
+	src/usb_mux_tentacruel.c
+	${PLATFORM_EC_PROGRAM_DIR}/corsola/tentacruel/src/ppc.c
+	${PLATFORM_EC_PROGRAM_DIR}/corsola/tentacruel/src/temp.c
+	${PLATFORM_EC_PROGRAM_DIR}/corsola/tentacruel/src/sensor.c)
diff --git a/zephyr/test/krabby/Kconfig b/zephyr/test/krabby/Kconfig
new file mode 100644
index 0000000000..6edd1f67ff
--- /dev/null
+++ b/zephyr/test/krabby/Kconfig
@@ -0,0 +1,27 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config MUX_INIT_ADC
+	bool "Run the tests intended for usb_nux_init adc"
+	help
+	  Include stubs.c with const struct adc_t adc_channels[] function
+	  into the binary to test.
+
+choice
+	prompt "select the test suite"
+
+config TEST_KRABBY
+	bool "Run the tests intended for krabby"
+	help
+	  Run the tests for krabby common code.
+
+config TEST_TENTACRUEL
+	bool "Run the tests intended for tentacruel"
+	help
+	  Include temp_tentacruel test into the binary to test temperature
+	  threshold trigger current control.
+
+endchoice
+
+source "Kconfig.zephyr"
diff --git a/zephyr/test/krabby/README.md b/zephyr/test/krabby/README.md
new file mode 100644
index 0000000000..027cdec4a4
--- /dev/null
+++ b/zephyr/test/krabby/README.md
@@ -0,0 +1,3 @@
+Tests for board specific code under `zephyr/program/corsola/src/krabby`.
+
+Run with ./twister -T zephyr/test/krabby
diff --git a/zephyr/test/krabby/common.dtsi b/zephyr/test/krabby/common.dtsi
new file mode 100644
index 0000000000..d719cd8fda
--- /dev/null
+++ b/zephyr/test/krabby/common.dtsi
@@ -0,0 +1,170 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <it8xxx2_emul.dts>
+
+/ {
+	pinctrl: pinctrl {
+		compatible = "ite,it8xxx2-pinctrl";
+		status = "disabled";
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		i2c_charger: charger {
+			i2c-port = <&i2c_ctrl0>;
+			enum-names = "I2C_PORT_CHARGER",
+				"I2C_PORT_BATTERY";
+		};
+	};
+
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port0@0 {
+			compatible = "named-usbc-port";
+			status = "okay";
+			reg = <0>;
+			chg = <&charger>;
+			tcpc = <&tcpci_emul>;
+			ppc = <&ppc0_emul>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_0>;
+			};
+		};
+		port0-muxes {
+			virtual_mux_0: virtual-mux-0 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+
+		port1@1 {
+			compatible = "named-usbc-port";
+			status = "okay";
+			reg = <1>;
+			tcpc = <&rt1718s_emul>;
+			ppc = <&ppc1_emul>;
+			usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&tusb1064_mux_1>;
+			};
+		};
+		port1-muxes {
+			virtual_mux_1: virtual-mux-1 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+	};
+
+	batteries {
+		default_battery: lgc_ac17a8m {
+			compatible = "lgc,ac17a8m", "battery-smart";
+			/**
+			 * this has to be strictly lower than the desired
+			 * voltage in smart battery emulator (5000mV).
+			 */
+			voltage_min = <4000>;
+		};
+	};
+
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		adc_vbus_c0 {
+			enum-name = "ADC_VBUS_C0";
+			io-channels = <&adc0 0>;
+			mul = <10>;
+		};
+		adc_board_id0 {
+			enum-name = "ADC_BOARD_ID_0";
+			io-channels = <&adc0 1>;
+		};
+		adc_board_id1 {
+			enum-name = "ADC_BOARD_ID_1";
+			io-channels = <&adc0 2>;
+		};
+		adc_vbus_c1 {
+			enum-name = "ADC_VBUS_C1";
+			io-channels = <&adc0 7>;
+			mul = <10>;
+		};
+		adc_charger: charger {
+			enum-name = "ADC_TEMP_SENSOR_CHARGER";
+			io-channels = <&adc0 5>;
+		};
+	};
+};
+
+&i2c_ctrl0 {
+	status="okay";
+
+	charger: rt9490@53 {
+		compatible = "richtek,rt9490", "zephyr,rt9490-emul";
+		status = "okay";
+		reg = <0x53>;
+	};
+
+	battery: sb@b {
+		compatible = "zephyr,smart-battery-emul";
+		reg = <0xb>;
+		cycle-count = <99>;
+		version = "BATTERY_SPEC_VER_1_1_WITH_PEC";
+		/* Real battery voltages are multiples of 4.4V. */
+		desired-charg-volt = <5000>;
+		desired-charg-cur = <1000>;
+		mf-name = "LGC";
+		dev-name = "AC17A8M";
+	};
+
+	tcpci_emul: tcpci_emul@82 {
+		compatible = "cros,tcpci-generic-emul";
+		status = "okay";
+		reg = <0x82>;
+	};
+
+	ppc0_emul: syv682x@42 {
+		compatible = "zephyr,syv682x-emul";
+		status = "okay";
+		reg = <0x42>;
+		frs_en_gpio = <&gpio_ec_x_gpio1>;
+		alert_gpio = <&gpio_x_ec_gpio2>;
+	};
+
+	ppc1_emul: syv682x@43 {
+		compatible = "zephyr,syv682x-emul";
+		status = "okay";
+		reg = <0x43>;
+		/*
+		 * the gpio pins are intentionally reused in both ppc emuls, to
+		 * avoid handling different frs-en pin names on krabby and
+		 * tentacruel.
+		 */
+		frs_en_gpio = <&gpio_ec_x_gpio1>;
+		alert_gpio = <&gpio_x_ec_gpio2>;
+	};
+
+	rt1718s_emul: rt1718s@2c {
+		compatible = "cros,rt1718s-tcpc-emul", "richtek,rt1718s-tcpc";
+		status = "okay";
+		reg = <0x2c>;
+	};
+};
+
+&adc0 {
+	status = "okay";
+};
+
+&i2c_ctrl4 {
+	status="okay";
+
+	tusb1064_mux_1: tusb1064-mux-1@44 {
+		compatible = "zephyr,tusb1064-emul";
+		reg = <0x44>;
+		board-init = "tusb1064_mux_1_board_init";
+	};
+};
diff --git a/zephyr/test/krabby/include/test_state.h b/zephyr/test/krabby/include/test_state.h
new file mode 100644
index 0000000000..6a2ff6654f
--- /dev/null
+++ b/zephyr/test/krabby/include/test_state.h
@@ -0,0 +1,17 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef ZEPHYR_TEST_KRABBY_INCLUDE_TEST_STATE_H_
+#define ZEPHYR_TEST_KRABBY_INCLUDE_TEST_STATE_H_
+
+#include <stdbool.h>
+
+struct test_state {
+	bool ec_app_main_run;
+};
+
+bool krabby_predicate_post_main(const void *state);
+
+#endif /* ZEPHYR_TEST_AP_POWER_INCLUDE_TEST_STATE_H_ */
diff --git a/zephyr/test/krabby/krabby.default.overlay b/zephyr/test/krabby/krabby.default.overlay
new file mode 100644
index 0000000000..f6892b8fc2
--- /dev/null
+++ b/zephyr/test/krabby/krabby.default.overlay
@@ -0,0 +1,41 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.dtsi"
+#include "../program/corsola/ite_gpio.dtsi"
+#include "../program/corsola/ite_interrupts.dtsi"
+#include "../program/corsola/power_signal.dtsi"
+
+/* remove pinctrl to avoid pull in too many unwanted dependency */
+/delete-node/ &pinctrl;
+
+/delete-node/ &int_usb_c0_ppc_bc12;
+/delete-node/ &int_volume_up;
+/delete-node/ &int_volume_down;
+/delete-node/ &int_tablet_mode;
+/delete-node/ &int_xhci;
+/delete-node/ &int_wp;
+/delete-node/ &int_spi0_cs;
+/delete-node/ &int_x_ec_gpio2;
+/delete-node/ &int_ccd_mode_odl;
+/delete-node/ &int_base_imu;
+/delete-node/ &int_lid_imu;
+
+&{/aliases} {
+	/delete-property/ int-wp;
+};
+
+/* open-drain is not supported in gpio emul, re-config to push-pull  */
+&ec_pmic_en_odl {
+	gpios = <&gpiod 0 (GPIO_OUTPUT_HIGH | GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+};
+&sys_rst_odl {
+	gpios = <&gpiog 1 GPIO_OUTPUT_LOW>;
+};
+
+/* set default gpio-emul state */
+&power_button_l {
+	gpios = <&gpioe 4 (GPIO_INPUT | GPIO_PULL_UP)>;
+};
diff --git a/zephyr/test/krabby/krabby.tentacruel.overlay b/zephyr/test/krabby/krabby.tentacruel.overlay
new file mode 100644
index 0000000000..8183d3826c
--- /dev/null
+++ b/zephyr/test/krabby/krabby.tentacruel.overlay
@@ -0,0 +1,245 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.dtsi"
+#include "../program/corsola/ite_gpio.dtsi"
+#include "../program/corsola/ite_interrupts.dtsi"
+#include "../program/corsola/ite_motionsense.dtsi"
+#include "../program/corsola/tentacruel/cbi.dtsi"
+#include "../program/corsola/tentacruel/thermistor.dtsi"
+
+/* remove pinctrl to avoid pull in too many unwanted dependency */
+/delete-node/ &pinctrl;
+
+/delete-node/ &{/hibernate-wake-pins};
+
+/*
+ * The unused-pins functionality is not currently tested. Remove
+ * to avoid mismatches in the GPIO flags configuration.
+ */
+/delete-node/ &{/unused-pins};
+
+/ {
+	name_temp_charger: charger {
+		compatible = "cros-ec,temp-sensor-thermistor";
+
+		thermistor = <&thermistor_rt9490>;
+		adc = <&adc_charger>;
+	};
+
+	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
+		temp_charger: charger {
+			status = "okay";
+			sensor = <&name_temp_charger>;
+		};
+	};
+
+	named-gpios {
+		/delete-node/ usb_c0_ppc_bc12_int_odl;
+
+		usb_c0_ppc_int_odl: usb_c0_ppc_int_odl {
+			gpios = <&gpiod 1 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C0_PPC_INT_ODL";
+		};
+
+		usb_c0_bc12_int_odl: usb_c0_bc12_int_odl {
+			gpios = <&gpiof 1 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C0_BC12_INT_ODL";
+		};
+
+		/delete-node/ usb_c0_ppc_frsinfo;
+
+		usb_c0_frs_en: usb_c0_frs_en {
+			gpios = <&gpiof 0 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_USB_C0_FRS_EN";
+		};
+	};
+
+	gpio-interrupts {
+		/delete-node/ usb_c0_ppc_bc12;
+	};
+
+	aliases {
+		/*
+		 * motion sense's <>_INT_EVENT is handled
+		 * by alias. Using the alias, each driver creates
+		 * its own <>_INT_EVENT.
+		 */
+		bmi3xx-int = &base_accel;
+		bma4xx-int = &lid_accel;
+	};
+
+	named-i2c-ports {
+	    compatible = "named-i2c-ports";
+
+	    i2c_sensor: i2c-sensor {
+		    i2c-port = <&i2c_ctrl0>;
+		    enum-names = "I2C_PORT_SENSOR";
+	    };
+	    i2c_eeprom: i2c-eeprom {
+		    i2c-port = <&i2c_ctrl0>;
+		    enum-names = "I2C_PORT_EEPROM";
+	    };
+	};
+
+	gpio-interrupts {
+		int_base_imu: base_imu {
+			handler = "base_sensor_interrupt";
+		};
+
+		int_lid_imu: lid_imu {
+			handler = "lid_sensor_interrupt";
+		};
+
+		int_usb_c0_ppc: usb_c0_ppc {
+			irq-pin = <&usb_c0_ppc_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "ppc_interrupt";
+		};
+
+		int_usb_c0_bc12: usb_c0_bc12 {
+			 irq-pin = <&usb_c0_bc12_int_odl>;
+			 flags = <GPIO_INT_EDGE_FALLING>;
+			 handler = "bc12_interrupt";
+		};
+
+		int_x_ec_gpio2: x_ec_gpio2 {
+			/* We have bypassed the db detection, so link
+			 * int_x_ec_gpio2 to ppc_interrupt directly.
+			 */
+			handler = "ppc_interrupt";
+		};
+	};
+
+	/*
+	 * change all underlying sensor drivers to bmi260 to have a easier way
+	 * to mock interrupt handlers.
+	 */
+	motionsense-sensor-data {
+		bmi323_data: bmi323-drv-data {
+			compatible = "cros-ec,drvdata-bmi260";
+			status = "okay";
+		};
+
+		bma422_data: bma422-drv-data {
+			compatible = "cros-ec,drvdata-bmi260";
+			status = "okay";
+		};
+	};
+
+	motionsense-sensor-alt {
+		alt_lid_accel: alt-lid-accel {
+			compatible = "cros-ec,bmi260-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_LID";
+			port = <&i2c_sensor>;
+			drv-data = <&bma422_data>;
+			alternate-for = <&lid_accel>;
+			mutex = <&lid_mutex>;
+		};
+
+		alt_base_accel: alt-base-accel {
+			compatible = "cros-ec,bmi260-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			port = <&i2c_sensor>;
+			drv-data = <&bmi323_data>;
+			alternate-for = <&base_accel>;
+			mutex = <&base_mutex>;
+		};
+
+		alt_base_gyro: alt-base-gyro {
+			compatible = "cros-ec,bmi260-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			port = <&i2c_sensor>;
+			drv-data = <&bmi323_data>;
+			alternate-for = <&base_gyro>;
+			mutex = <&base_mutex>;
+		};
+	};
+
+	usbc {
+		port0@0 {
+			ppc = <&bc12_ppc_port0>;
+			ppc_alt = <&ppc_port0>;
+		};
+		port1@1 {
+			ppc = <&ppc_port1>;
+			usb-mux-chain-1 {
+				usb-muxes = <&ps8743_mux_1>;
+			};
+		};
+	};
+};
+
+&i2c_ctrl0 {
+	status="okay";
+
+	cbi_eeprom: eeprom@50 {
+		compatible = "atmel,at24";
+		reg = <0x50>;
+		size = <2048>;
+		pagesize = <16>;
+		address-width = <8>;
+		timeout = <5>;
+	};
+
+	ppc_port0: syv682x@44 {
+		compatible = "silergy,syv682x", "cros,i2c-mock";
+		status = "okay";
+		reg = <0x44>;
+	};
+
+	ppc_port1: syv682x@443 {
+		compatible = "silergy,syv682x", "cros,i2c-mock";
+		status = "okay";
+		reg = <0x43>;
+	};
+
+	bc12_ppc_port0: rt1739@70 {
+		compatible = "richtek,rt1739-ppc", "richtek,rt1739-bc12",
+			     "cros,i2c-mock";
+		status = "okay";
+		reg = <0x70>;
+	};
+};
+
+&lid_accel {
+	compatible = "cros-ec,bmi260-accel";
+};
+
+&base_accel {
+	compatible = "cros-ec,bmi260-accel";
+};
+
+&base_gyro {
+	compatible = "cros-ec,bmi260-gyro";
+};
+
+&icm42607_data {
+	compatible = "cros-ec,drvdata-bmi260";
+};
+
+&lis2dw12_data {
+	compatible = "cros-ec,drvdata-bmi260";
+};
+
+&i2c_ctrl4 {
+	/delete-node/ tusb1064-mux-1@44;
+
+	ps8743_mux_1: ps8743-mux-1@10 {
+		compatible = "zephyr,ps8743-emul";
+		reg = <0x10>;
+		board-init = "ps8743_eq_c1_setting";
+	};
+};
diff --git a/zephyr/test/krabby/prj.conf b/zephyr/test/krabby/prj.conf
new file mode 100644
index 0000000000..abc6b1323a
--- /dev/null
+++ b/zephyr/test/krabby/prj.conf
@@ -0,0 +1,44 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_ZTEST=y
+CONFIG_ZTEST_ASSERT_VERBOSE=1
+CONFIG_ZTEST_NEW_API=y
+
+CONFIG_ASSERT=y
+CONFIG_ADC=y
+CONFIG_CROS_EC=y
+CONFIG_EMUL=y
+
+CONFIG_SHIMMED_TASKS=n
+
+CONFIG_PLATFORM_EC=y
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
+CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y
+CONFIG_PLATFORM_EC_CHARGER=y
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=20
+CONFIG_PLATFORM_EC_CHARGE_MANAGER=y
+CONFIG_PLATFORM_EC_CHARGE_RAMP_HW=y
+CONFIG_PLATFORM_EC_GPIO_INIT_PRIORITY=49
+CONFIG_PLATFORM_EC_HOOKS=y
+CONFIG_PLATFORM_EC_HOSTCMD=y
+CONFIG_PLATFORM_EC_LID_SWITCH=y
+CONFIG_PLATFORM_EC_POWERSEQ_HOST_SLEEP=y
+CONFIG_PLATFORM_EC_POWER_BUTTON=y
+CONFIG_PLATFORM_EC_POWER_SLEEP_FAILURE_DETECTION=y
+CONFIG_PLATFORM_EC_SWITCH=n
+CONFIG_PLATFORM_EC_USBC=y
+CONFIG_PLATFORM_EC_USB_CHARGER=y
+CONFIG_PLATFORM_EC_USB_DRP_ACC_TRYSRC=y
+CONFIG_PLATFORM_EC_USB_MUX_TUSB546=y
+CONFIG_PLATFORM_EC_USB_PD_DISCHARGE=y
+CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_ADC_EACH_PORT=y
+CONFIG_PLATFORM_EC_USB_POWER_DELIVERY=y
+CONFIG_PLATFORM_EC_VBOOT_HASH=n
+
+CONFIG_PLATFORM_EC_USBC_PPC=y
+
+CONFIG_NATIVE_UART_0_ON_STDINOUT=y
diff --git a/zephyr/test/krabby/src/charger_workaround.c b/zephyr/test/krabby/src/charger_workaround.c
new file mode 100644
index 0000000000..5582fe5c64
--- /dev/null
+++ b/zephyr/test/krabby/src/charger_workaround.c
@@ -0,0 +1,96 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charger.h"
+#include "driver/charger/rt9490.h"
+#include "emul/emul_rt9490.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "system.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/fff.h>
+#include <zephyr/ztest.h>
+
+FAKE_VALUE_FUNC(int, board_get_version);
+
+const struct emul *emul = EMUL_DT_GET(DT_NODELABEL(charger));
+
+static bool ibus_adc_workaround_called(void)
+{
+	return rt9490_emul_peek_reg(emul, 0x52) == 0xC4;
+}
+
+static bool i2c_speed_workaround_called(void)
+{
+	return rt9490_emul_peek_reg(emul, 0x71) == 0x22;
+}
+
+static bool eoc_deglitch_workaround_called(void)
+{
+	return !(rt9490_emul_peek_reg(emul, RT9490_REG_ADD_CTRL0) &
+		 RT9490_TD_EOC);
+}
+
+static bool disable_safety_timer_called(void)
+{
+	return rt9490_emul_peek_reg(emul, RT9490_REG_SAFETY_TMR_CTRL) ==
+	       (RT9490_EN_TRICHG_TMR | RT9490_EN_PRECHG_TMR |
+		RT9490_EN_FASTCHG_TMR);
+}
+
+ZTEST(charger_workaround, test_board_version_0)
+{
+	board_get_version_fake.return_val = 0;
+
+	hook_notify(HOOK_INIT);
+	zassert_true(ibus_adc_workaround_called(), NULL);
+	zassert_true(i2c_speed_workaround_called(), NULL);
+	zassert_false(eoc_deglitch_workaround_called(), NULL);
+	zassert_true(disable_safety_timer_called(), NULL);
+}
+
+ZTEST(charger_workaround, test_board_version_1)
+{
+	board_get_version_fake.return_val = 1;
+
+	hook_notify(HOOK_INIT);
+	zassert_false(ibus_adc_workaround_called(), NULL);
+	zassert_true(i2c_speed_workaround_called(), NULL);
+	zassert_true(eoc_deglitch_workaround_called(), NULL);
+	zassert_true(disable_safety_timer_called(), NULL);
+}
+
+ZTEST(charger_workaround, test_board_version_2)
+{
+	board_get_version_fake.return_val = 2;
+
+	hook_notify(HOOK_INIT);
+	zassert_false(ibus_adc_workaround_called(), NULL);
+	zassert_true(i2c_speed_workaround_called(), NULL);
+	zassert_false(eoc_deglitch_workaround_called(), NULL);
+	zassert_false(disable_safety_timer_called(), NULL);
+}
+
+ZTEST(charger_workaround, test_board_version_3)
+{
+	board_get_version_fake.return_val = 3;
+
+	hook_notify(HOOK_INIT);
+	zassert_false(ibus_adc_workaround_called(), NULL);
+	zassert_false(i2c_speed_workaround_called(), NULL);
+	zassert_false(eoc_deglitch_workaround_called(), NULL);
+	zassert_false(disable_safety_timer_called(), NULL);
+}
+
+static void charge_workaround_before(void *fixture)
+{
+	RESET_FAKE(board_get_version);
+	rt9490_emul_reset_regs(emul);
+}
+
+ZTEST_SUITE(charger_workaround, NULL, NULL, charge_workaround_before, NULL,
+	    NULL);
diff --git a/zephyr/test/krabby/src/fake.c b/zephyr/test/krabby/src/fake.c
new file mode 100644
index 0000000000..5b2d34608c
--- /dev/null
+++ b/zephyr/test/krabby/src/fake.c
@@ -0,0 +1,24 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "gpio_signal.h"
+
+#include <zephyr/fff.h>
+
+/* LCOV_EXCL_START */
+
+FAKE_VOID_FUNC(button_interrupt, enum gpio_signal);
+FAKE_VOID_FUNC(chipset_reset_request_interrupt, enum gpio_signal);
+FAKE_VOID_FUNC(power_signal_interrupt, enum gpio_signal);
+FAKE_VOID_FUNC(chipset_warm_reset_interrupt, enum gpio_signal);
+FAKE_VOID_FUNC(chipset_watchdog_interrupt, enum gpio_signal);
+FAKE_VOID_FUNC(extpower_interrupt, enum gpio_signal);
+FAKE_VOID_FUNC(xhci_interrupt, enum gpio_signal);
+FAKE_VOID_FUNC(switch_interrupt, enum gpio_signal);
+FAKE_VOID_FUNC(spi_event, enum gpio_signal);
+FAKE_VOID_FUNC(ccd_interrupt, enum gpio_signal);
+FAKE_VOID_FUNC(x_ec_interrupt, enum gpio_signal);
+
+/* LCOV_EXCL_STOP */
diff --git a/zephyr/test/krabby/src/fwconfig_tentacruel.c b/zephyr/test/krabby/src/fwconfig_tentacruel.c
new file mode 100644
index 0000000000..f1f2222ca3
--- /dev/null
+++ b/zephyr/test/krabby/src/fwconfig_tentacruel.c
@@ -0,0 +1,253 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "tablet_mode.h"
+#include "zephyr/kernel.h"
+
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/ztest.h>
+
+#define BOARD_CLAMSHELL (0 << 7)
+#define BOARD_CONVERTIBLE (1 << 7)
+#define MAIN_BASE_SENSOR (1 << 8)
+#define ALT_BASE_SENSOR (2 << 8)
+#define MAIN_LID_SENSOR (1 << 10)
+#define ALT_LID_SENSOR (2 << 10)
+
+#define MAIN_FWCONFIG (BOARD_CONVERTIBLE | MAIN_BASE_SENSOR | MAIN_LID_SENSOR)
+#define ALT_FWCONFIG (BOARD_CONVERTIBLE | ALT_BASE_SENSOR | ALT_LID_SENSOR)
+
+static int base_interrupt_id;
+static int lid_interrupt_id;
+
+static void *clamshell_setup(void)
+{
+	uint32_t val;
+	const struct device *wp_gpio =
+		DEVICE_DT_GET(DT_GPIO_CTLR(DT_ALIAS(gpio_wp), gpios));
+	const gpio_port_pins_t wp_pin = DT_GPIO_PIN(DT_ALIAS(gpio_wp), gpios);
+
+	base_interrupt_id = 0;
+	lid_interrupt_id = 0;
+
+	/* Make sure that write protect is disabled */
+	zassert_ok(gpio_emul_input_set(wp_gpio, wp_pin, 1), NULL);
+	/* Set CBI to BOARD_CLAMSHELL */
+	zassert_ok(cbi_set_fw_config(BOARD_CLAMSHELL), NULL);
+	/* Run init hooks to initialize cbi. */
+	hook_notify(HOOK_INIT);
+
+	/* Check if CBI write worked. */
+	zassert_ok(cros_cbi_get_fw_config(FORM_FACTOR, &val), NULL);
+	zassert_equal(CLAMSHELL, val, "val=%d", val);
+	zassert_ok(cros_cbi_get_fw_config(BASE_SENSOR, &val), NULL);
+	zassert_equal(BASE_NONE, val, "val=%d", val);
+	zassert_ok(cros_cbi_get_fw_config(LID_SENSOR, &val), NULL);
+	zassert_equal(LID_NONE, val, "val=%d", val);
+
+	return NULL;
+}
+
+ZTEST_SUITE(tentacruel_clamshell, NULL, clamshell_setup, NULL, NULL, NULL);
+
+static void *main_sensor_setup(void)
+{
+	uint32_t val;
+	const struct device *wp_gpio =
+		DEVICE_DT_GET(DT_GPIO_CTLR(DT_ALIAS(gpio_wp), gpios));
+	const gpio_port_pins_t wp_pin = DT_GPIO_PIN(DT_ALIAS(gpio_wp), gpios);
+
+	base_interrupt_id = 0;
+	lid_interrupt_id = 0;
+
+	/* Make sure that write protect is disabled */
+	zassert_ok(gpio_emul_input_set(wp_gpio, wp_pin, 1), NULL);
+	/* Set CBI to main sensor config */
+	zassert_ok(cbi_set_fw_config(MAIN_FWCONFIG), NULL);
+	/* Run init hooks to initialize cbi. */
+	hook_notify(HOOK_INIT);
+
+	/* Check if CBI write worked. */
+	zassert_ok(cros_cbi_get_fw_config(FORM_FACTOR, &val), NULL);
+	zassert_equal(CONVERTIBLE, val, "val=%d", val);
+	zassert_ok(cros_cbi_get_fw_config(BASE_SENSOR, &val), NULL);
+	zassert_equal(BASE_ICM42607, val, "val=%d", val);
+	zassert_ok(cros_cbi_get_fw_config(LID_SENSOR, &val), NULL);
+	zassert_equal(LID_LIS2DWLTR, val, "val=%d", val);
+
+	return NULL;
+}
+
+ZTEST_SUITE(tentacruel_main_sensor, NULL, main_sensor_setup, NULL, NULL, NULL);
+
+static void *alt_sensor_setup(void)
+{
+	uint32_t val;
+	const struct device *wp_gpio =
+		DEVICE_DT_GET(DT_GPIO_CTLR(DT_ALIAS(gpio_wp), gpios));
+	const gpio_port_pins_t wp_pin = DT_GPIO_PIN(DT_ALIAS(gpio_wp), gpios);
+
+	base_interrupt_id = 0;
+	lid_interrupt_id = 0;
+
+	/* Make sure that write protect is disabled */
+	zassert_ok(gpio_emul_input_set(wp_gpio, wp_pin, 1), NULL);
+	/* Set CBI to alt sensor config */
+	zassert_ok(cbi_set_fw_config(ALT_FWCONFIG), NULL);
+	/* Run init hooks to initialize cbi. */
+	hook_notify(HOOK_INIT);
+
+	/* Check if CBI write worked. */
+	zassert_ok(cros_cbi_get_fw_config(FORM_FACTOR, &val), NULL);
+	zassert_equal(CONVERTIBLE, val, "val=%d", val);
+	zassert_ok(cros_cbi_get_fw_config(BASE_SENSOR, &val), NULL);
+	zassert_equal(BASE_BMI323, val, "val=%d", val);
+	zassert_ok(cros_cbi_get_fw_config(LID_SENSOR, &val), NULL);
+	zassert_equal(LID_BMA422, val, "val=%d", val);
+
+	return NULL;
+}
+
+ZTEST_SUITE(tentacruel_alt_sensor, NULL, alt_sensor_setup, NULL, NULL, NULL);
+
+/* Main gyro sensor. */
+void icm42607_interrupt(enum gpio_signal signal)
+{
+	base_interrupt_id = 1;
+}
+
+void bmi3xx_interrupt(enum gpio_signal signal)
+{
+	base_interrupt_id = 2;
+}
+
+/* Main lid sensor. */
+void lis2dw12_interrupt(enum gpio_signal signal)
+{
+	lid_interrupt_id = 1;
+}
+
+void bma4xx_interrupt(enum gpio_signal signal)
+{
+	lid_interrupt_id = 2;
+}
+
+ZTEST(tentacruel_clamshell, test_tabletmode_disable)
+{
+	const struct device *tablet_mode_gpio =
+		DEVICE_DT_GET(DT_GPIO_CTLR(DT_NODELABEL(tablet_mode_l), gpios));
+	const gpio_port_pins_t tablet_mode_pin =
+		DT_GPIO_PIN(DT_NODELABEL(tablet_mode_l), gpios);
+
+	/* Verify gmr_tablet_switch is disabled, by checking the side effects
+	 * of calling tablet_set_mode, and setting gpio_tablet_mode_l.
+	 */
+	zassert_ok(gpio_emul_input_set(tablet_mode_gpio, tablet_mode_pin, 0),
+		   NULL);
+	k_sleep(K_MSEC(100));
+	tablet_set_mode(1, TABLET_TRIGGER_LID);
+	zassert_equal(0, tablet_get_mode(), NULL);
+	zassert_ok(gpio_emul_input_set(tablet_mode_gpio, tablet_mode_pin, 1),
+		   NULL);
+	k_sleep(K_MSEC(100));
+	tablet_set_mode(0, TABLET_TRIGGER_LID);
+	zassert_equal(0, tablet_get_mode(), NULL);
+	zassert_ok(gpio_emul_input_set(tablet_mode_gpio, tablet_mode_pin, 0),
+		   NULL);
+	k_sleep(K_MSEC(100));
+	tablet_set_mode(1, TABLET_TRIGGER_LID);
+	zassert_equal(0, tablet_get_mode(), NULL);
+}
+
+ZTEST(tentacruel_clamshell, test_irq_disable)
+{
+	const struct device *base_imu_gpio = DEVICE_DT_GET(
+		DT_GPIO_CTLR(DT_NODELABEL(base_imu_int_l), gpios));
+	const gpio_port_pins_t base_imu_pin =
+		DT_GPIO_PIN(DT_NODELABEL(base_imu_int_l), gpios);
+
+	zassert_ok(gpio_emul_input_set(base_imu_gpio, base_imu_pin, 1), NULL);
+	k_sleep(K_MSEC(100));
+	zassert_ok(gpio_emul_input_set(base_imu_gpio, base_imu_pin, 0), NULL);
+	k_sleep(K_MSEC(100));
+
+	zassert_equal(base_interrupt_id, 0, "base_interrupt_id=%d",
+		      base_interrupt_id);
+
+	const struct device *lid_imu_gpio = DEVICE_DT_GET(
+		DT_GPIO_CTLR(DT_NODELABEL(lid_accel_int_l), gpios));
+	const gpio_port_pins_t lid_imu_pin =
+		DT_GPIO_PIN(DT_NODELABEL(lid_accel_int_l), gpios);
+
+	zassert_ok(gpio_emul_input_set(lid_imu_gpio, lid_imu_pin, 1), NULL);
+	k_sleep(K_MSEC(100));
+	zassert_ok(gpio_emul_input_set(lid_imu_gpio, lid_imu_pin, 0), NULL);
+	k_sleep(K_MSEC(100));
+
+	zassert_equal(lid_interrupt_id, 0, "lid_interrupt_id=%d",
+		      lid_interrupt_id);
+}
+
+ZTEST(tentacruel_main_sensor, test_tentacruel_main_sensor)
+{
+	const struct device *base_imu_gpio = DEVICE_DT_GET(
+		DT_GPIO_CTLR(DT_NODELABEL(base_imu_int_l), gpios));
+	const gpio_port_pins_t base_imu_pin =
+		DT_GPIO_PIN(DT_NODELABEL(base_imu_int_l), gpios);
+
+	zassert_ok(gpio_emul_input_set(base_imu_gpio, base_imu_pin, 1), NULL);
+	k_sleep(K_MSEC(100));
+	zassert_ok(gpio_emul_input_set(base_imu_gpio, base_imu_pin, 0), NULL);
+	k_sleep(K_MSEC(100));
+
+	zassert_equal(base_interrupt_id, 1, "base_interrupt_id=%d",
+		      base_interrupt_id);
+
+	const struct device *lid_imu_gpio = DEVICE_DT_GET(
+		DT_GPIO_CTLR(DT_NODELABEL(lid_accel_int_l), gpios));
+	const gpio_port_pins_t lid_imu_pin =
+		DT_GPIO_PIN(DT_NODELABEL(lid_accel_int_l), gpios);
+
+	zassert_ok(gpio_emul_input_set(lid_imu_gpio, lid_imu_pin, 1), NULL);
+	k_sleep(K_MSEC(100));
+	zassert_ok(gpio_emul_input_set(lid_imu_gpio, lid_imu_pin, 0), NULL);
+	k_sleep(K_MSEC(100));
+
+	zassert_equal(lid_interrupt_id, 1, "lid_interrupt_id=%d",
+		      lid_interrupt_id);
+}
+
+ZTEST(tentacruel_alt_sensor, test_tentacruel_alt_sensor)
+{
+	const struct device *base_imu_gpio = DEVICE_DT_GET(
+		DT_GPIO_CTLR(DT_NODELABEL(base_imu_int_l), gpios));
+	const gpio_port_pins_t base_imu_pin =
+		DT_GPIO_PIN(DT_NODELABEL(base_imu_int_l), gpios);
+
+	zassert_ok(gpio_emul_input_set(base_imu_gpio, base_imu_pin, 1), NULL);
+	k_sleep(K_MSEC(100));
+	zassert_ok(gpio_emul_input_set(base_imu_gpio, base_imu_pin, 0), NULL);
+	k_sleep(K_MSEC(100));
+
+	zassert_equal(base_interrupt_id, 2, "base_interrupt_id=%d",
+		      base_interrupt_id);
+
+	const struct device *lid_imu_gpio = DEVICE_DT_GET(
+		DT_GPIO_CTLR(DT_NODELABEL(lid_accel_int_l), gpios));
+	const gpio_port_pins_t lid_imu_pin =
+		DT_GPIO_PIN(DT_NODELABEL(lid_accel_int_l), gpios);
+
+	zassert_ok(gpio_emul_input_set(lid_imu_gpio, lid_imu_pin, 1), NULL);
+	k_sleep(K_MSEC(100));
+	zassert_ok(gpio_emul_input_set(lid_imu_gpio, lid_imu_pin, 0), NULL);
+	k_sleep(K_MSEC(100));
+
+	zassert_equal(lid_interrupt_id, 2, "lid_interrupt_id=%d",
+		      lid_interrupt_id);
+}
diff --git a/zephyr/test/krabby/src/main.c b/zephyr/test/krabby/src/main.c
new file mode 100644
index 0000000000..2df530be93
--- /dev/null
+++ b/zephyr/test/krabby/src/main.c
@@ -0,0 +1,35 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_app_main.h"
+#include "test_state.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+bool krabby_predicate_post_main(const void *state)
+{
+	return ((struct test_state *)state)->ec_app_main_run;
+}
+
+void test_main(void)
+{
+	struct test_state state = {
+		.ec_app_main_run = false,
+	};
+
+	/* Run all the suites that depend on main not being called yet */
+	ztest_run_test_suites(&state);
+
+	ec_app_main();
+
+	state.ec_app_main_run = true;
+
+	/* Run all the suites that depend on main being called */
+	ztest_run_test_suites(&state);
+
+	/* Check that every suite ran */
+	ztest_verify_all_test_suites_ran();
+}
diff --git a/zephyr/test/krabby/src/power_seq.c b/zephyr/test/krabby/src/power_seq.c
new file mode 100644
index 0000000000..200eb0e987
--- /dev/null
+++ b/zephyr/test/krabby/src/power_seq.c
@@ -0,0 +1,452 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "ec_tasks.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "power.h"
+#include "power_button.h"
+#include "system.h"
+#include "task.h"
+#include "test_state.h"
+#include "timer.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/fff.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+FAKE_VOID_FUNC(chipset_pre_init_hook);
+DECLARE_HOOK(HOOK_CHIPSET_PRE_INIT, chipset_pre_init_hook, HOOK_PRIO_DEFAULT);
+FAKE_VOID_FUNC(chipset_startup_hook);
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, chipset_startup_hook, HOOK_PRIO_DEFAULT);
+FAKE_VOID_FUNC(chipset_resume_hook);
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, chipset_resume_hook, HOOK_PRIO_DEFAULT);
+FAKE_VALUE_FUNC(int, system_jumped_late);
+
+#define S5_INACTIVE_SEC 11
+
+/* mt8186 is_held flag */
+extern bool is_held;
+
+static void set_signal_state(enum power_state state)
+{
+	const struct gpio_dt_spec *ap_ec_sysrst_odl =
+		gpio_get_dt_spec(GPIO_AP_EC_SYSRST_ODL);
+	const struct gpio_dt_spec *ap_in_sleep_l =
+		gpio_get_dt_spec(GPIO_AP_IN_SLEEP_L);
+
+	switch (state) {
+	case POWER_S0:
+		gpio_emul_input_set(ap_in_sleep_l->port, ap_in_sleep_l->pin, 1);
+		gpio_emul_input_set(ap_ec_sysrst_odl->port,
+				    ap_ec_sysrst_odl->pin, 1);
+		break;
+	case POWER_S3:
+		gpio_emul_input_set(ap_in_sleep_l->port, ap_in_sleep_l->pin, 0);
+		gpio_emul_input_set(ap_ec_sysrst_odl->port,
+				    ap_ec_sysrst_odl->pin, 1);
+		break;
+	case POWER_G3:
+		gpio_emul_input_set(ap_in_sleep_l->port, ap_in_sleep_l->pin, 0);
+		gpio_emul_input_set(ap_ec_sysrst_odl->port,
+				    ap_ec_sysrst_odl->pin, 0);
+		break;
+	default:
+		zassert_unreachable("state %d not supported", state);
+	}
+
+	/* reset is_held flag */
+	is_held = false;
+	task_wake(TASK_ID_CHIPSET);
+	k_sleep(K_SECONDS(1));
+}
+
+static void power_seq_before(void *f)
+{
+	/* Required for deferred callbacks to work */
+	set_test_runner_tid();
+
+	/* Start from G3 */
+	power_set_state(POWER_G3);
+	set_signal_state(POWER_G3);
+	k_sleep(K_SECONDS(S5_INACTIVE_SEC));
+
+	RESET_FAKE(chipset_pre_init_hook);
+	RESET_FAKE(chipset_startup_hook);
+	RESET_FAKE(chipset_resume_hook);
+	RESET_FAKE(system_jumped_late);
+	FFF_RESET_HISTORY();
+}
+
+/* Normal boot sequence, G3 -> S3 -> S0 */
+ZTEST(power_seq, test_power_state_machine)
+{
+	/* G3 -> S3 */
+	power_set_state(POWER_G3);
+	set_signal_state(POWER_S3);
+	zassert_equal(power_get_state(), POWER_S3);
+
+	/* S3 -> S0 */
+	power_set_state(POWER_S3);
+	set_signal_state(POWER_S0);
+	zassert_equal(power_get_state(), POWER_S0);
+
+	/* S0 -> G3 */
+	power_set_state(POWER_S0);
+	set_signal_state(POWER_G3);
+	zassert_equal(power_get_state(), POWER_S5);
+	k_sleep(K_SECONDS(S5_INACTIVE_SEC));
+	zassert_equal(power_get_state(), POWER_G3);
+}
+
+/* Verify power btn short press can boot the device */
+ZTEST(power_seq, test_power_btn_short_press)
+{
+	zassert_equal(power_get_state(), POWER_G3);
+
+	power_button_simulate_press(100);
+	k_sleep(K_SECONDS(1));
+
+	/* Verify that power state machine is able to reach S5S3, and back to G3
+	 * because power signal is not changed
+	 */
+	zassert_equal(chipset_pre_init_hook_fake.call_count, 1);
+	zassert_equal(chipset_startup_hook_fake.call_count, 0);
+	k_sleep(K_SECONDS(S5_INACTIVE_SEC));
+	zassert_equal(power_get_state(), POWER_G3);
+}
+
+/* Verify lid open can boot the device */
+ZTEST(power_seq, test_lid_open)
+{
+	const struct gpio_dt_spec *lid_open = gpio_get_dt_spec(GPIO_LID_OPEN);
+
+	gpio_emul_input_set(lid_open->port, lid_open->pin, 0);
+	k_sleep(K_SECONDS(1));
+	zassert_equal(power_get_state(), POWER_G3);
+
+	gpio_emul_input_set(lid_open->port, lid_open->pin, 1);
+	k_sleep(K_SECONDS(1));
+
+	/* Verify that power state machine is able to reach S5S3, and back to G3
+	 * because power signal is not changed
+	 */
+	zassert_equal(chipset_pre_init_hook_fake.call_count, 1);
+	zassert_equal(chipset_startup_hook_fake.call_count, 0);
+	k_sleep(K_SECONDS(S5_INACTIVE_SEC));
+	zassert_equal(power_get_state(), POWER_G3);
+}
+
+/* Suspend, S0 -> S3 -> S0 */
+ZTEST(power_seq, test_host_sleep_success)
+{
+	host_clear_events(EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT));
+
+	/* Boot AP */
+	set_signal_state(POWER_S0);
+	zassert_equal(power_get_state(), POWER_S0);
+
+	/* Suspend for 30 seconds */
+	zassert_ok(ec_cmd_host_sleep_event(
+		NULL, &(struct ec_params_host_sleep_event){
+			      .sleep_event = HOST_SLEEP_EVENT_S3_SUSPEND }));
+	k_sleep(K_MSEC(1));
+	set_signal_state(POWER_S3);
+	k_sleep(K_SECONDS(30));
+	zassert_equal(power_get_state(), POWER_S3);
+
+	/* Resume */
+	set_signal_state(POWER_S0);
+	zassert_ok(ec_cmd_host_sleep_event(
+		NULL, &(struct ec_params_host_sleep_event){
+			      .sleep_event = HOST_SLEEP_EVENT_S3_RESUME }));
+	zassert_equal(power_get_state(), POWER_S0);
+
+	/* Verify that EC_HOST_EVENT_HANG_DETECT is not triggered */
+	zassert_false(host_is_event_set(EC_HOST_EVENT_HANG_DETECT));
+}
+
+/* Sleep hang, send EC_HOST_EVENT_HANG_DETECT */
+ZTEST(power_seq, test_host_sleep_hang)
+{
+	host_clear_events(EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT));
+
+	/* Boot AP */
+	set_signal_state(POWER_S0);
+	zassert_equal(power_get_state(), POWER_S0);
+
+	/* Send HOST_SLEEP_EVENT_S3_SUSPEND and hang for 30 seconds */
+	zassert_ok(ec_cmd_host_sleep_event(
+		NULL, &(struct ec_params_host_sleep_event){
+			      .sleep_event = HOST_SLEEP_EVENT_S3_SUSPEND }));
+	k_sleep(K_SECONDS(30));
+
+	/* Verify that EC_HOST_EVENT_HANG_DETECT is triggered */
+	zassert_true(host_is_event_set(EC_HOST_EVENT_HANG_DETECT));
+}
+
+/* Shutdown from EC, S0 -> power key press (8 secs) -> S3S5 (8 secs) -> S5 -> G3
+ */
+ZTEST(power_seq, test_force_shutdown)
+{
+	const struct gpio_dt_spec *sys_rst_odl =
+		gpio_get_dt_spec(GPIO_SYS_RST_ODL);
+	const struct gpio_dt_spec *ec_pmic_en_odl =
+		gpio_get_dt_spec(GPIO_EC_PMIC_EN_ODL);
+
+	gpio_set_level(GPIO_SYS_RST_ODL, 1);
+	gpio_set_level(GPIO_EC_PMIC_EN_ODL, 1);
+
+	/* Boot AP */
+	set_signal_state(POWER_S0);
+	zassert_equal(power_get_state(), POWER_S0);
+
+	/* Verify that ec resets ap and holds power button */
+	chipset_force_shutdown(CHIPSET_SHUTDOWN_CONSOLE_CMD);
+	k_sleep(K_SECONDS(1));
+	zassert_equal(gpio_emul_output_get(sys_rst_odl->port, sys_rst_odl->pin),
+		      0);
+
+	/* Emulate AP power down (hw state G3, sw state unchanged),
+	 * Verify power state stops at S5
+	 */
+	set_signal_state(POWER_G3);
+	zassert_equal(power_get_state(), POWER_S3S5);
+	zassert_equal(gpio_emul_output_get(ec_pmic_en_odl->port,
+					   ec_pmic_en_odl->pin),
+		      0);
+
+	/* Wait 10 seconds for EC_PMIC_EN_ODL release and drop to S5 then G3 */
+	k_sleep(K_SECONDS(10));
+	zassert_equal(gpio_emul_output_get(sys_rst_odl->port, sys_rst_odl->pin),
+		      0);
+	zassert_equal(gpio_emul_output_get(ec_pmic_en_odl->port,
+					   ec_pmic_en_odl->pin),
+		      1);
+	zassert_equal(power_get_state(), POWER_S5);
+	k_sleep(K_SECONDS(S5_INACTIVE_SEC));
+	zassert_equal(power_get_state(), POWER_G3);
+}
+
+/* Shutdown from AP, S0 -> powerkey hold (8 secs) -> S3S5 (8 secs) -> G3 */
+ZTEST(power_seq, test_force_shutdown_button)
+{
+	const struct gpio_dt_spec *sys_rst_odl =
+		gpio_get_dt_spec(GPIO_SYS_RST_ODL);
+	const struct gpio_dt_spec *ec_pmic_en_odl =
+		gpio_get_dt_spec(GPIO_EC_PMIC_EN_ODL);
+
+	gpio_set_level(GPIO_SYS_RST_ODL, 1);
+	gpio_set_level(GPIO_EC_PMIC_EN_ODL, 1);
+
+	/* Boot AP */
+	set_signal_state(POWER_S0);
+	zassert_equal(power_get_state(), POWER_S0);
+
+	power_button_simulate_press(10000); /* 10 seconds */
+	zassert_equal(power_get_state(), POWER_S0);
+	k_sleep(K_SECONDS(9)); /* AP off after 8 seconds */
+	zassert_equal(gpio_emul_output_get(sys_rst_odl->port, sys_rst_odl->pin),
+		      0);
+	zassert_equal(gpio_emul_output_get(ec_pmic_en_odl->port,
+					   ec_pmic_en_odl->pin),
+		      0);
+
+	zassert_equal(power_get_state(), POWER_S3S5);
+	zassert_equal(gpio_emul_output_get(sys_rst_odl->port, sys_rst_odl->pin),
+		      0);
+	zassert_equal(gpio_emul_output_get(ec_pmic_en_odl->port,
+					   ec_pmic_en_odl->pin),
+		      0);
+
+	k_sleep(K_SECONDS(5)); /* Wait for power button release */
+	/* Signal has dropped, but PMIC_EN is still held */
+	set_signal_state(POWER_G3);
+	zassert_equal(power_get_state(), POWER_S3S5);
+	zassert_equal(gpio_emul_output_get(ec_pmic_en_odl->port,
+					   ec_pmic_en_odl->pin),
+		      0);
+
+	k_sleep(K_SECONDS(3)); /* Wait for S5 */
+
+	/* PMIC_EN released */
+	zassert_equal(power_get_state(), POWER_S5);
+	zassert_equal(gpio_emul_output_get(ec_pmic_en_odl->port,
+					   ec_pmic_en_odl->pin),
+		      1);
+	k_sleep(K_SECONDS(S5_INACTIVE_SEC)); /* Wait for G3 */
+	zassert_equal(power_get_state(), POWER_G3);
+}
+
+/* AP reset (S0 -> S0).
+ * Verify power state doesn't change during reset.
+ */
+ZTEST(power_seq, test_chipset_reset)
+{
+	const struct gpio_dt_spec *ap_ec_warm_rst_req =
+		gpio_get_dt_spec(GPIO_AP_EC_WARM_RST_REQ);
+	const struct gpio_dt_spec *ap_ec_sysrst_odl =
+		gpio_get_dt_spec(GPIO_AP_EC_SYSRST_ODL);
+
+	/* Boot AP */
+	set_signal_state(POWER_S0);
+	zassert_equal(power_get_state(), POWER_S0);
+	RESET_FAKE(chipset_resume_hook);
+	/* Clear reset reason */
+	report_ap_reset(CHIPSET_RESET_UNKNOWN);
+
+	/* Trigger AP reboot */
+	gpio_emul_input_set(ap_ec_warm_rst_req->port, ap_ec_warm_rst_req->pin,
+			    0);
+	gpio_emul_input_set(ap_ec_warm_rst_req->port, ap_ec_warm_rst_req->pin,
+			    1);
+
+	/* Simulate sysrst toggle */
+	gpio_emul_input_set(ap_ec_sysrst_odl->port, ap_ec_sysrst_odl->pin, 0);
+	gpio_emul_input_set(ap_ec_sysrst_odl->port, ap_ec_sysrst_odl->pin, 1);
+	k_sleep(K_SECONDS(1));
+
+	/* Back to S0, verify that resume hook is not triggered */
+	zassert_equal(power_get_state(), POWER_S0);
+	zassert_equal(chipset_resume_hook_fake.call_count, 0);
+	/* Also verify that chipset_reset_request_interrupt is called by
+	 * checking its side-effect
+	 */
+	zassert_equal(chipset_get_shutdown_reason(), CHIPSET_RESET_AP_REQ);
+}
+
+/* AP reset during suspend (S3 -> S0).
+ * Verify state reaches S0 with resume hook triggered.
+ */
+ZTEST(power_seq, test_chipset_reset_in_s3)
+{
+	const struct gpio_dt_spec *ap_ec_warm_rst_req =
+		gpio_get_dt_spec(GPIO_AP_EC_WARM_RST_REQ);
+	const struct gpio_dt_spec *ap_ec_sysrst_odl =
+		gpio_get_dt_spec(GPIO_AP_EC_SYSRST_ODL);
+
+	/* Boot AP */
+	set_signal_state(POWER_S3);
+	zassert_equal(power_get_state(), POWER_S3);
+	RESET_FAKE(chipset_resume_hook);
+	/* Clear reset reason */
+	report_ap_reset(CHIPSET_RESET_UNKNOWN);
+
+	/* Trigger AP reboot */
+	gpio_emul_input_set(ap_ec_warm_rst_req->port, ap_ec_warm_rst_req->pin,
+			    0);
+	gpio_emul_input_set(ap_ec_warm_rst_req->port, ap_ec_warm_rst_req->pin,
+			    1);
+
+	/* Simulate sysrst toggle */
+	gpio_emul_input_set(ap_ec_sysrst_odl->port, ap_ec_sysrst_odl->pin, 0);
+	gpio_emul_input_set(ap_ec_sysrst_odl->port, ap_ec_sysrst_odl->pin, 1);
+	set_signal_state(POWER_S0);
+
+	/* Back to S0, verify that resume hook is triggered */
+	zassert_equal(power_get_state(), POWER_S0);
+	zassert_equal(chipset_resume_hook_fake.call_count, 1);
+	/* Also verify that chipset_reset_request_interrupt is called by
+	 * checking its side-effect
+	 */
+	zassert_equal(chipset_get_shutdown_reason(), CHIPSET_RESET_AP_REQ);
+}
+
+static void power_chipset_init_subtest(enum power_state signal_state,
+				       bool jumped_late, uint32_t reset_flags,
+				       enum power_state expected_state,
+				       int line)
+{
+	const struct gpio_dt_spec *sys_rst_odl =
+		gpio_get_dt_spec(GPIO_SYS_RST_ODL);
+
+	set_signal_state(signal_state);
+
+	system_jumped_late_fake.return_val = jumped_late;
+	system_common_reset_state();
+	system_set_reset_flags(reset_flags);
+
+	power_set_state(power_chipset_init());
+
+	RESET_FAKE(chipset_pre_init_hook);
+	task_wake(TASK_ID_CHIPSET);
+	k_sleep(K_SECONDS(1));
+
+	if (signal_state == expected_state) {
+		/* need 10 seconds to drop from s5 to g3 */
+		k_sleep(K_SECONDS(S5_INACTIVE_SEC));
+
+		/* Expect nothing changed */
+		zassert_equal(chipset_pre_init_hook_fake.call_count, 0,
+			      "test_power_chipset_init line %d failed", line);
+		zassert_equal(power_get_state(), expected_state);
+	} else if (expected_state == POWER_S0 && signal_state == POWER_G3) {
+		/* Expect boot to S0 and fail at S5->S3 */
+		zassert_equal(chipset_pre_init_hook_fake.call_count, 1,
+			      "test_power_chipset_init line %d failed", line);
+	} else if (expected_state == POWER_G3 && signal_state == POWER_S0) {
+		zassert_equal(gpio_emul_output_get(sys_rst_odl->port,
+						   sys_rst_odl->pin),
+			      0, "test_power_chipset_init line %d failed",
+			      line);
+	} else {
+		zassert_unreachable();
+	}
+}
+
+/* Verify initial state decision logic.
+ * Combination that don't make sense (e.g. wake from hibernate but signal
+ * state is already S0) are skipped.
+ */
+ZTEST(power_seq, test_power_chipset_init)
+{
+	const struct gpio_dt_spec *ac_present =
+		gpio_get_dt_spec(GPIO_AC_PRESENT);
+
+	/* system_jumped_late => ignore all flags and boot to S0 */
+	power_chipset_init_subtest(POWER_G3, true, 0, POWER_S0, __LINE__);
+	power_chipset_init_subtest(POWER_S0, true, 0, POWER_S0, __LINE__);
+	power_chipset_init_subtest(POWER_G3, true, EC_RESET_FLAG_AP_OFF,
+				   POWER_S0, __LINE__);
+	power_chipset_init_subtest(POWER_S0, true, EC_RESET_FLAG_AP_OFF,
+				   POWER_S0, __LINE__);
+	power_chipset_init_subtest(POWER_G3, true, EC_RESET_FLAG_HIBERNATE,
+				   POWER_S0, __LINE__);
+	power_chipset_init_subtest(POWER_S0, true, EC_RESET_FLAG_HIBERNATE,
+				   POWER_S0, __LINE__);
+	power_chipset_init_subtest(POWER_G3, true, EC_RESET_FLAG_AP_IDLE,
+				   POWER_G3, __LINE__);
+	power_chipset_init_subtest(POWER_S0, true, EC_RESET_FLAG_AP_IDLE,
+				   POWER_S0, __LINE__);
+
+	/* No reset flag => always boot to S0 */
+	power_chipset_init_subtest(POWER_G3, false, 0, POWER_S0, __LINE__);
+	power_chipset_init_subtest(POWER_S0, false, 0, POWER_S0, __LINE__);
+
+	/* AP off => stay at G3 */
+	power_chipset_init_subtest(POWER_G3, false, EC_RESET_FLAG_AP_OFF,
+				   POWER_G3, __LINE__);
+	power_chipset_init_subtest(POWER_S0, false, EC_RESET_FLAG_AP_OFF,
+				   POWER_G3, __LINE__);
+
+	/* Boot from hibernate => stay at G3 */
+	gpio_emul_input_set(ac_present->port, ac_present->pin, 1);
+	power_chipset_init_subtest(POWER_G3, false, EC_RESET_FLAG_HIBERNATE,
+				   POWER_G3, __LINE__);
+
+	/* AP_IDLE => keep current state */
+	power_chipset_init_subtest(POWER_G3, false, EC_RESET_FLAG_AP_IDLE,
+				   POWER_G3, __LINE__);
+	power_chipset_init_subtest(POWER_S0, false, EC_RESET_FLAG_AP_IDLE,
+				   POWER_S0, __LINE__);
+}
+
+ZTEST_SUITE(power_seq, krabby_predicate_post_main, NULL, power_seq_before, NULL,
+	    NULL);
diff --git a/zephyr/test/krabby/src/ppc_tentacruel.c b/zephyr/test/krabby/src/ppc_tentacruel.c
new file mode 100644
index 0000000000..fb6a88cefd
--- /dev/null
+++ b/zephyr/test/krabby/src/ppc_tentacruel.c
@@ -0,0 +1,138 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "gpio.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "usbc/ppc.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/fff.h>
+#include <zephyr/ztest.h>
+
+FAKE_VALUE_FUNC(int, cbi_get_board_version, uint32_t *);
+
+static int fake_board_version;
+
+static int fake_cbi_get_board_version(uint32_t *ver)
+{
+	*ver = fake_board_version;
+	return 0;
+}
+
+FAKE_VOID_FUNC(ppc_chip_0_interrupt, int);
+FAKE_VOID_FUNC(ppc_chip_alt_interrupt, int);
+FAKE_VOID_FUNC(ppc_chip_1_interrupt, int);
+
+ZTEST(ppc_tentacruel, test_ppc_init)
+{
+	const struct device *ppc_int_gpio = DEVICE_DT_GET(
+		DT_GPIO_CTLR(DT_NODELABEL(usb_c0_ppc_int_odl), gpios));
+	const gpio_port_pins_t ppc_int_pin =
+		DT_GPIO_PIN(DT_NODELABEL(usb_c0_ppc_int_odl), gpios);
+
+	/* Board version 0, expect that main ppc is enabled. */
+	RESET_FAKE(cbi_get_board_version);
+	cbi_get_board_version_fake.custom_fake = fake_cbi_get_board_version;
+	fake_board_version = 0;
+	hook_notify(HOOK_INIT);
+	zassert_ok(gpio_emul_input_set(ppc_int_gpio, ppc_int_pin, 1), NULL);
+	k_sleep(K_MSEC(100));
+	zassert_ok(gpio_emul_input_set(ppc_int_gpio, ppc_int_pin, 0), NULL);
+	k_sleep(K_MSEC(100));
+
+	zassert_equal(ppc_chip_0_interrupt_fake.call_count, 1);
+	zassert_equal(ppc_chip_alt_interrupt_fake.call_count, 0);
+	zassert_equal(ppc_chip_1_interrupt_fake.call_count, 0);
+
+	/* CBI access fail, fallback to board version 0 */
+	RESET_FAKE(cbi_get_board_version);
+	cbi_get_board_version_fake.return_val = -1;
+	fake_board_version = 0;
+	hook_notify(HOOK_INIT);
+	zassert_ok(gpio_emul_input_set(ppc_int_gpio, ppc_int_pin, 1), NULL);
+	k_sleep(K_MSEC(100));
+	zassert_ok(gpio_emul_input_set(ppc_int_gpio, ppc_int_pin, 0), NULL);
+	k_sleep(K_MSEC(100));
+
+	zassert_equal(ppc_chip_0_interrupt_fake.call_count, 2);
+	zassert_equal(ppc_chip_alt_interrupt_fake.call_count, 0);
+	zassert_equal(ppc_chip_1_interrupt_fake.call_count, 0);
+
+	/* Board version 3, expect that alt ppc is enabled.
+	 * Since PPC_ENABLE_ALTERNATE() is not reversible, we must test this
+	 * after the board version 0 test.
+	 */
+	RESET_FAKE(cbi_get_board_version);
+	cbi_get_board_version_fake.custom_fake = fake_cbi_get_board_version;
+	fake_board_version = 3;
+	hook_notify(HOOK_INIT);
+	zassert_ok(gpio_emul_input_set(ppc_int_gpio, ppc_int_pin, 1), NULL);
+	k_sleep(K_MSEC(100));
+	zassert_ok(gpio_emul_input_set(ppc_int_gpio, ppc_int_pin, 0), NULL);
+	k_sleep(K_MSEC(100));
+
+	zassert_equal(ppc_chip_0_interrupt_fake.call_count, 2);
+	zassert_equal(ppc_chip_alt_interrupt_fake.call_count, 1);
+	zassert_equal(ppc_chip_1_interrupt_fake.call_count, 0);
+}
+
+ZTEST(ppc_tentacruel, test_ppc_1_int)
+{
+	const struct device *x_ec_gpio2 = DEVICE_DT_GET(
+		DT_GPIO_CTLR(DT_NODELABEL(gpio_x_ec_gpio2), gpios));
+	const gpio_port_pins_t x_ec_gpio2_pin =
+		DT_GPIO_PIN(DT_NODELABEL(gpio_x_ec_gpio2), gpios);
+
+	zassert_ok(gpio_emul_input_set(x_ec_gpio2, x_ec_gpio2_pin, 1), NULL);
+	k_sleep(K_MSEC(100));
+	zassert_ok(gpio_emul_input_set(x_ec_gpio2, x_ec_gpio2_pin, 0), NULL);
+	k_sleep(K_MSEC(100));
+
+	zassert_equal(ppc_chip_0_interrupt_fake.call_count, 0);
+	zassert_equal(ppc_chip_alt_interrupt_fake.call_count, 0);
+	zassert_equal(ppc_chip_1_interrupt_fake.call_count, 1);
+}
+
+static void *ppc_tentacruel_init(void)
+{
+	static struct ppc_drv fake_ppc_drv_0;
+	static struct ppc_drv fake_ppc_drv_1;
+	static struct ppc_drv fake_ppc_drv_alt;
+
+	zassert_equal(ppc_cnt, 2);
+
+	/* inject mocked interrupt handlers into ppc_drv and ppc_drv_alt */
+	fake_ppc_drv_0 = *ppc_chips[0].drv;
+	fake_ppc_drv_0.interrupt = ppc_chip_0_interrupt;
+	ppc_chips[0].drv = &fake_ppc_drv_0;
+
+	fake_ppc_drv_alt = *ppc_chips_alt[0].drv;
+	fake_ppc_drv_alt.interrupt = ppc_chip_alt_interrupt;
+	ppc_chips_alt[0].drv = &fake_ppc_drv_alt;
+
+	fake_ppc_drv_1 = *ppc_chips[1].drv;
+	fake_ppc_drv_1.interrupt = ppc_chip_1_interrupt;
+	ppc_chips[1].drv = &fake_ppc_drv_1;
+
+	return NULL;
+}
+
+static void ppc_tentacruel_before(void *fixture)
+{
+	RESET_FAKE(cbi_get_board_version);
+	RESET_FAKE(ppc_chip_0_interrupt);
+	RESET_FAKE(ppc_chip_alt_interrupt);
+	RESET_FAKE(ppc_chip_1_interrupt);
+
+	/* We have bypassed the db detection, so we force enabling the
+	 * int_x_ec_gpio2.
+	 */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_x_ec_gpio2));
+}
+ZTEST_SUITE(ppc_tentacruel, NULL, ppc_tentacruel_init, ppc_tentacruel_before,
+	    NULL, NULL);
diff --git a/zephyr/test/krabby/src/stubs.c b/zephyr/test/krabby/src/stubs.c
new file mode 100644
index 0000000000..6e1bcc3b7f
--- /dev/null
+++ b/zephyr/test/krabby/src/stubs.c
@@ -0,0 +1,19 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc.h"
+#include "charge_ramp.h"
+#include "charge_state.h"
+#include "usbc_ppc.h"
+
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
+{
+}
+
+int board_get_adjusted_usb_pd_port_count(int port)
+{
+	return 2;
+}
diff --git a/zephyr/test/krabby/src/temp_tentacruel.c b/zephyr/test/krabby/src/temp_tentacruel.c
new file mode 100644
index 0000000000..1eaefad988
--- /dev/null
+++ b/zephyr/test/krabby/src/temp_tentacruel.c
@@ -0,0 +1,106 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_state.h"
+#include "charger.h"
+#include "charger_profile_override.h"
+#include "common.h"
+#include "config.h"
+#include "hooks.h"
+#include "temp_sensor.h"
+#include "temp_sensor/temp_sensor.h"
+#include "util.h"
+
+#include <zephyr/drivers/adc.h>
+#include <zephyr/drivers/adc/adc_emul.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+#define ADC_DEVICE_NODE DT_NODELABEL(adc0)
+#define CHARGER_TEMP TEMP_SENSOR_ID(DT_NODELABEL(temp_charger))
+#define ORIGINAL_CURRENT 5000
+
+struct charge_state_data curr;
+static int fake_voltage;
+int count;
+
+/* Limit charging current table : 3600/3000/2400/1800
+ * note this should be in descending order.
+ */
+static uint16_t current_table[] = {
+	3600,
+	3000,
+	2400,
+	1600,
+};
+
+int setup_faketemp(int fake_voltage)
+{
+	const struct device *adc_dev = DEVICE_DT_GET(ADC_DEVICE_NODE);
+	const uint8_t channel_id =
+		DT_IO_CHANNELS_INPUT(DT_NODELABEL(adc_charger));
+	int emul_temp;
+
+	emul_temp = adc_emul_const_value_set(adc_dev, channel_id, fake_voltage);
+	return emul_temp;
+}
+
+static void ignore_first_minute(void)
+{
+	for (int i = 0; i < 60; i++) {
+		hook_notify(HOOK_SECOND);
+	}
+}
+
+ZTEST(temp_tentacruel, test_decrease_current)
+{
+	fake_voltage = 411;
+	curr.batt.flags |= BATT_FLAG_RESPONSIVE;
+	count = 0;
+
+	setup_faketemp(fake_voltage);
+	/* Calculate per minute temperature.
+	 * It's expected low temperature when the first 60 seconds.
+	 */
+	ignore_first_minute();
+	for (int i = 1; i < 26; i++) {
+		hook_notify(HOOK_SECOND);
+		curr.requested_current = ORIGINAL_CURRENT;
+		charger_profile_override(&curr);
+		if (i % 6 == 0) {
+			zassert_equal(current_table[count],
+				      curr.requested_current, NULL);
+			count++;
+		}
+	}
+	zassert_equal(count, 4, NULL);
+}
+
+ZTEST(temp_tentacruel, test_increase_current)
+{
+	fake_voltage = 446;
+	curr.batt.flags |= BATT_FLAG_RESPONSIVE;
+	count = 3;
+
+	setup_faketemp(fake_voltage);
+	for (int i = 1; i < 26; i++) {
+		hook_notify(HOOK_SECOND);
+		curr.requested_current = ORIGINAL_CURRENT;
+		charger_profile_override(&curr);
+		if (i % 5 == 0) {
+			if (curr.requested_current == ORIGINAL_CURRENT) {
+				zassert_equal(ORIGINAL_CURRENT,
+					      curr.requested_current, NULL);
+			} else {
+				zassert_equal(current_table[count],
+					      curr.requested_current, NULL);
+				count--;
+			}
+		}
+	}
+	zassert_equal(count, -1, NULL);
+}
+
+ZTEST_SUITE(temp_tentacruel, NULL, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/krabby/src/usb_mux_init.c b/zephyr/test/krabby/src/usb_mux_init.c
new file mode 100644
index 0000000000..8d1e4e81eb
--- /dev/null
+++ b/zephyr/test/krabby/src/usb_mux_init.c
@@ -0,0 +1,28 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/usb_mux/tusb1064.h"
+#include "emul/emul_tusb1064.h"
+#include "usb_mux.h"
+#include "usbc/usb_muxes.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/ztest.h>
+
+const static struct emul *emul = EMUL_DT_GET(DT_NODELABEL(tusb1064_mux_1));
+
+const static int tusb1064_port = USB_MUX_PORT(DT_NODELABEL(tusb1064_mux_1));
+
+ZTEST(usb_mux_init, test_mux_init_value)
+{
+	usb_mux_set(tusb1064_port, USB_PD_MUX_DP_ENABLED, USB_SWITCH_CONNECT,
+		    0);
+	zassert_equal(tusb1064_emul_peek_reg(emul, TUSB1064_REG_DP1DP3EQ_SEL),
+		      TUSB1064_DP1EQ(TUSB1064_DP_EQ_RX_8_9_DB) |
+			      TUSB1064_DP3EQ(TUSB1064_DP_EQ_RX_5_4_DB));
+}
+
+ZTEST_SUITE(usb_mux_init, NULL, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/krabby/src/usb_mux_tentacruel.c b/zephyr/test/krabby/src/usb_mux_tentacruel.c
new file mode 100644
index 0000000000..2e8ed6714e
--- /dev/null
+++ b/zephyr/test/krabby/src/usb_mux_tentacruel.c
@@ -0,0 +1,23 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "baseboard_usbc_config.h"
+#include "driver/usb_mux/ps8743.h"
+#include "emul/emul_ps8743.h"
+#include "usb_mux.h"
+#include "usbc/usb_muxes.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/ztest.h>
+
+const static struct emul *emul = EMUL_DT_GET(DT_NODELABEL(ps8743_mux_1));
+
+ZTEST(usb_mux_tentacruel_init, test_mux_init_value)
+{
+	ps8743_eq_c1_setting();
+	zassert_equal(ps8743_emul_peek_reg(emul, PS8743_REG_USB_EQ_RX), 0x90);
+}
+
+ZTEST_SUITE(usb_mux_tentacruel_init, NULL, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/krabby/src/usbc_config.c b/zephyr/test/krabby/src/usbc_config.c
new file mode 100644
index 0000000000..16d31d20de
--- /dev/null
+++ b/zephyr/test/krabby/src/usbc_config.c
@@ -0,0 +1,134 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc.h"
+#include "baseboard_usbc_config.h"
+#include "charge_manager.h"
+#include "driver/ppc/syv682x.h"
+#include "driver/ppc/syv682x_public.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_syv682x.h"
+#include "i2c/i2c.h"
+#include "test_state.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/ztest.h>
+
+static bool ppc_sink_enabled(int port)
+{
+	const struct emul *emul = (port == 0) ?
+					  EMUL_DT_GET(DT_NODELABEL(ppc0_emul)) :
+					  EMUL_DT_GET(DT_NODELABEL(ppc1_emul));
+	uint8_t val = 0;
+
+	syv682x_emul_get_reg(emul, SYV682X_CONTROL_1_REG, &val);
+
+	return !(val & (SYV682X_CONTROL_1_PWR_ENB | SYV682X_CONTROL_1_HV_DR));
+}
+
+ZTEST(usbc_config, test_set_active_charge_port)
+{
+	/* reset ppc state */
+	zassert_ok(board_set_active_charge_port(CHARGE_PORT_NONE), NULL);
+	zassert_false(ppc_sink_enabled(0), NULL);
+	zassert_false(ppc_sink_enabled(1), NULL);
+
+	/* sourcing port 0, expect port 0 not sinkable */
+	zassert_ok(pd_set_power_supply_ready(0));
+	zassert_not_equal(board_set_active_charge_port(0), 0, NULL);
+	zassert_true(board_vbus_source_enabled(0), NULL);
+	zassert_false(board_vbus_source_enabled(1), NULL);
+	zassert_false(ppc_sink_enabled(0), NULL);
+	zassert_false(ppc_sink_enabled(1), NULL);
+
+	/* sinking port 1 */
+	zassert_ok(board_set_active_charge_port(1), NULL);
+	zassert_false(ppc_sink_enabled(0), NULL);
+	zassert_true(ppc_sink_enabled(1), NULL);
+
+	/*
+	 * sinking an invalid port should return error and doesn't change
+	 * any state
+	 */
+	zassert_not_equal(board_set_active_charge_port(2), 0, NULL);
+	zassert_true(board_vbus_source_enabled(0), NULL);
+	zassert_false(board_vbus_source_enabled(1), NULL);
+	zassert_false(ppc_sink_enabled(0), NULL);
+	zassert_true(ppc_sink_enabled(1), NULL);
+
+	/* turn off sourcing, sinking port 0 */
+	pd_power_supply_reset(0);
+	zassert_ok(board_set_active_charge_port(0), NULL);
+	zassert_true(ppc_sink_enabled(0), NULL);
+	zassert_false(ppc_sink_enabled(1), NULL);
+
+	/* sinking port 1 */
+	zassert_ok(board_set_active_charge_port(1), NULL);
+	zassert_false(ppc_sink_enabled(0), NULL);
+	zassert_true(ppc_sink_enabled(1), NULL);
+
+	/* back to port 0 */
+	zassert_ok(board_set_active_charge_port(0), NULL);
+	zassert_true(ppc_sink_enabled(0), NULL);
+	zassert_false(ppc_sink_enabled(1), NULL);
+
+	/* reset */
+	zassert_ok(board_set_active_charge_port(CHARGE_PORT_NONE), NULL);
+	zassert_false(board_vbus_source_enabled(0), NULL);
+	zassert_false(board_vbus_source_enabled(1), NULL);
+	zassert_false(ppc_sink_enabled(0), NULL);
+	zassert_false(ppc_sink_enabled(1), NULL);
+}
+
+ZTEST(usbc_config, test_set_active_charge_port_fail)
+{
+	const struct emul *ppc0 = EMUL_DT_GET(DT_NODELABEL(ppc0_emul));
+
+	/* Verify that failure on ppc0 doesn't affect ppc1 */
+	i2c_common_emul_set_write_fail_reg(
+		emul_syv682x_get_i2c_common_data(ppc0),
+		I2C_COMMON_EMUL_FAIL_ALL_REG);
+
+	zassert_ok(board_set_active_charge_port(1), NULL);
+	zassert_true(ppc_sink_enabled(1), NULL);
+	zassert_ok(board_set_active_charge_port(CHARGE_PORT_NONE), NULL);
+	zassert_false(ppc_sink_enabled(1), NULL);
+	zassert_ok(board_set_active_charge_port(1), NULL);
+	zassert_true(ppc_sink_enabled(1), NULL);
+
+	/* trying to enable ppc0 results in error */
+	zassert_not_equal(board_set_active_charge_port(0), 0, NULL);
+	zassert_false(ppc_sink_enabled(1), NULL);
+}
+
+ZTEST(usbc_config, test_adc_channel)
+{
+	zassert_equal(board_get_vbus_adc(0), ADC_VBUS_C0, NULL);
+	zassert_equal(board_get_vbus_adc(1), ADC_VBUS_C1, NULL);
+	zassert_equal(board_get_vbus_adc(99), ADC_VBUS_C0, NULL);
+}
+
+static void reset_ppc_state(void *fixture)
+{
+	const struct emul *ppc0 = EMUL_DT_GET(DT_NODELABEL(ppc0_emul));
+	const struct emul *ppc1 = EMUL_DT_GET(DT_NODELABEL(ppc1_emul));
+
+	i2c_common_emul_set_write_fail_reg(
+		emul_syv682x_get_i2c_common_data(ppc0),
+		I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(
+		emul_syv682x_get_i2c_common_data(ppc1),
+		I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	ppc_vbus_source_enable(0, false);
+	ppc_vbus_source_enable(1, false);
+	board_set_active_charge_port(CHARGE_PORT_NONE);
+}
+
+ZTEST_SUITE(usbc_config, krabby_predicate_post_main, NULL, reset_ppc_state,
+	    NULL, NULL);
diff --git a/zephyr/test/krabby/testcase.yaml b/zephyr/test/krabby/testcase.yaml
new file mode 100644
index 0000000000..c9a683f316
--- /dev/null
+++ b/zephyr/test/krabby/testcase.yaml
@@ -0,0 +1,33 @@
+common:
+  platform_allow: native_posix
+tests:
+  krabby.default:
+    extra_configs:
+    - CONFIG_TEST_KRABBY=y
+    - CONFIG_AP_ARM_MTK_MT8186=y
+    - CONFIG_MUX_INIT_ADC=y
+    - CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK=y
+    - CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y
+    - CONFIG_PLATFORM_EC_POWERSEQ=y
+    - CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n
+    - CONFIG_SHIMMED_TASKS=y
+    extra_dtc_overlay_files:
+    - krabby.default.overlay
+  krabby.tentacruel:
+    extra_configs:
+    - CONFIG_TEST_TENTACRUEL=y
+    - CONFIG_PLATFORM_EC_CHARGER_PROFILE_OVERRIDE=y
+    - CONFIG_EEPROM=y
+    - CONFIG_EEPROM_SIMULATOR=n
+    - CONFIG_EMUL_EEPROM_AT2X=y
+    - CONFIG_PLATFORM_EC_MOTIONSENSE=y
+    - CONFIG_PLATFORM_EC_DYNAMIC_MOTION_SENSOR_COUNT=y
+    - CONFIG_PLATFORM_EC_GMR_TABLET_MODE=y
+    - CONFIG_PLATFORM_EC_TABLET_MODE=y
+    - CONFIG_PLATFORM_EC_LID_ANGLE=y
+    - CONFIG_PLATFORM_EC_ACCELGYRO_BMI260=y
+    - CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y
+    - CONFIG_PLATFORM_EC_USBC_PPC_RT1739=y
+    - CONFIG_PLATFORM_EC_BC12_SINGLE_DRIVER=n
+    extra_dtc_overlay_files:
+    - krabby.tentacruel.overlay
diff --git a/zephyr/test/math/CMakeLists.txt b/zephyr/test/math/CMakeLists.txt
new file mode 100644
index 0000000000..57fe7e389f
--- /dev/null
+++ b/zephyr/test/math/CMakeLists.txt
@@ -0,0 +1,20 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(math)
+
+target_sources(app PRIVATE ${PLATFORM_EC}/common/math_util.c)
+
+target_sources(
+	app PRIVATE
+		src/suite.c
+		src/math_util.c
+		src/vector.c
+		src/mask.c
+)
+
+# Fixed point specific tests
+target_sources_ifndef(CONFIG_FPU app PRIVATE src/fixed_point_int_sqrtf.c)
diff --git a/zephyr/test/math/boards/native_posix.overlay b/zephyr/test/math/boards/native_posix.overlay
new file mode 120000
index 0000000000..7b75ea9967
--- /dev/null
+++ b/zephyr/test/math/boards/native_posix.overlay
@@ -0,0 +1 @@
+../../../dts/board-overlays/native_posix.dts
\ No newline at end of file
diff --git a/zephyr/test/math/fixed_point.conf b/zephyr/test/math/fixed_point.conf
new file mode 100644
index 0000000000..c1ddcc0911
--- /dev/null
+++ b/zephyr/test/math/fixed_point.conf
@@ -0,0 +1,5 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_FPU=n
diff --git a/zephyr/test/math/floating_point.conf b/zephyr/test/math/floating_point.conf
new file mode 100644
index 0000000000..c6b8f58176
--- /dev/null
+++ b/zephyr/test/math/floating_point.conf
@@ -0,0 +1,5 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_FPU=y
diff --git a/zephyr/test/math/prj.conf b/zephyr/test/math/prj.conf
new file mode 100644
index 0000000000..7c5ef483a2
--- /dev/null
+++ b/zephyr/test/math/prj.conf
@@ -0,0 +1,12 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_ZTEST=y
+CONFIG_ZTEST_ASSERT_VERBOSE=1
+CONFIG_ZTEST_NEW_API=y
+CONFIG_ASSERT=y
+
+CONFIG_PLATFORM_EC=y
+CONFIG_CROS_EC=y
+CONFIG_PLATFORM_EC_MATH_UTIL=y
diff --git a/zephyr/test/math/src/fixed_point_int_sqrtf.c b/zephyr/test/math/src/fixed_point_int_sqrtf.c
new file mode 100644
index 0000000000..f949084f28
--- /dev/null
+++ b/zephyr/test/math/src/fixed_point_int_sqrtf.c
@@ -0,0 +1,19 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "math.h"
+#include "math_util.h"
+
+#include <zephyr/ztest.h>
+
+ZTEST_USER(math, test_int_sqrtf_negative)
+{
+	zassert_equal(int_sqrtf(-100), 0);
+}
+
+ZTEST_USER(math, test_int_sqrtf_overflow)
+{
+	zassert_equal(int_sqrtf(INT64_MAX), INT32_MAX);
+}
diff --git a/zephyr/test/math/src/mask.c b/zephyr/test/math/src/mask.c
new file mode 100644
index 0000000000..e3bce982a5
--- /dev/null
+++ b/zephyr/test/math/src/mask.c
@@ -0,0 +1,21 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "math.h"
+#include "math_util.h"
+
+#include <inttypes.h>
+
+#include <zephyr/ztest.h>
+
+ZTEST_USER(math, test_bitmask_uint64)
+{
+	zassert_equal(bitmask_uint64(-1), 0);
+	zassert_equal(bitmask_uint64(64), 0);
+	zassert_equal(bitmask_uint64(1), UINT64_C(1) << 1);
+	zassert_equal(bitmask_uint64(15), UINT64_C(1) << 15);
+	zassert_equal(bitmask_uint64(35), UINT64_C(1) << 35);
+	zassert_equal(bitmask_uint64(60), UINT64_C(1) << 60);
+}
diff --git a/zephyr/test/math/src/math_util.c b/zephyr/test/math/src/math_util.c
new file mode 100644
index 0000000000..e5d9d8c9f2
--- /dev/null
+++ b/zephyr/test/math/src/math_util.c
@@ -0,0 +1,70 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "builtin/stdio.h"
+#include "common.h"
+#include "math.h"
+#include "math_util.h"
+
+#include <zephyr/ztest.h>
+
+ZTEST_USER(math, test_arc_cos__x_below_range)
+{
+	fp_t result = arc_cos(FLOAT_TO_FP(-1.1));
+
+	zassert_within(result, FLOAT_TO_FP(180.0), FLOAT_TO_FP(1.0),
+		       "arc_cos(-1.1) was %d", FP_TO_INT(result));
+}
+
+ZTEST_USER(math, test_arc_cos__x_above_range)
+{
+	fp_t result = arc_cos(FLOAT_TO_FP(1.1));
+
+	zassert_within(result, FLOAT_TO_FP(0), FLOAT_TO_FP(1.0),
+		       "arc_cos(1.1) was %d", FP_TO_INT(result));
+}
+
+ZTEST_USER(math, test_int_sqrtf)
+{
+	zassert_equal(int_sqrtf(0), 0);
+	zassert_equal(int_sqrtf(15), 3);
+	zassert_equal(int_sqrtf(25), 5);
+	zassert_equal(int_sqrtf(1111088889), 33333);
+	zassert_equal(int_sqrtf(123456789), 11111);
+	zassert_equal(int_sqrtf(1000000000000000005), 1000000000);
+}
+
+ZTEST_USER(math, test_fp_sqrtf)
+{
+	zassert_within(fp_sqrtf(FLOAT_TO_FP(15)), FLOAT_TO_FP(3.872983),
+		       FLOAT_TO_FP(0.001), NULL);
+}
+
+ZTEST_USER(math, test_print_ints)
+{
+	char buffer[10];
+
+	/* Fixed point. */
+	zassert_true(crec_snprintf(buffer, sizeof(buffer), "%.5d", 123) > 0,
+		     NULL);
+	zassert_equal(0, strcmp(buffer, "0.00123"), "got '%s'", buffer);
+	zassert_true(crec_snprintf(buffer, sizeof(buffer), "%2.1d", 123) > 0,
+		     NULL);
+	zassert_equal(0, strcmp(buffer, "12.3"), "got '%s'", buffer);
+
+	/* Precision or width larger than buffer should fail. */
+	zassert_equal(-EC_ERROR_OVERFLOW, crec_snprintf(buffer, 4, "%5d", 123),
+		      NULL);
+	zassert_equal(0, strcmp(buffer, "  1"), "got '%s'", buffer);
+	zassert_equal(-EC_ERROR_OVERFLOW, crec_snprintf(buffer, 4, "%10d", 123),
+		      NULL);
+	zassert_equal(0, strcmp(buffer, "   "), "got '%s'", buffer);
+	zassert_equal(-EC_ERROR_OVERFLOW,
+		      crec_snprintf(buffer, 4, "%-10d", 123), NULL);
+	zassert_equal(0, strcmp(buffer, "123"), "got '%s'", buffer);
+	zassert_equal(-EC_ERROR_OVERFLOW,
+		      crec_snprintf(buffer, 4, "%.10d", 123), NULL);
+	zassert_equal(0, strcmp(buffer, "0.0"), "got '%s'", buffer);
+}
diff --git a/zephyr/test/math/src/suite.c b/zephyr/test/math/src/suite.c
new file mode 100644
index 0000000000..95da93b113
--- /dev/null
+++ b/zephyr/test/math/src/suite.c
@@ -0,0 +1,8 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/ztest.h>
+
+ZTEST_SUITE(math, NULL, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/math/src/vector.c b/zephyr/test/math/src/vector.c
new file mode 100644
index 0000000000..344cb80f48
--- /dev/null
+++ b/zephyr/test/math/src/vector.c
@@ -0,0 +1,29 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "math.h"
+#include "math_util.h"
+
+#include <zephyr/ztest.h>
+
+ZTEST_USER(math, test_cosine_of_angle_diff__zero_magnitude_vector)
+{
+	intv3_t v0 = { 0, 0, 0 };
+	intv3_t v1 = { 1, 1, 1 };
+
+	zassert_equal(cosine_of_angle_diff(v0, v1), 0);
+	zassert_equal(cosine_of_angle_diff(v1, v0), 0);
+}
+
+ZTEST_USER(math, test_rotate_inv__null_matrix)
+{
+	intv3_t v = { 1, 2, 3 };
+	intv3_t r = { 4, 5, 6 };
+
+	rotate_inv(v, NULL, r);
+	zassert_equal(v[0], r[0]);
+	zassert_equal(v[1], r[1]);
+	zassert_equal(v[2], r[2]);
+}
diff --git a/zephyr/test/math/testcase.yaml b/zephyr/test/math/testcase.yaml
new file mode 100644
index 0000000000..465591e5a0
--- /dev/null
+++ b/zephyr/test/math/testcase.yaml
@@ -0,0 +1,9 @@
+common:
+  platform_allow: native_posix
+tests:
+  util.math.fixed_point:
+    extra_overlay_confs:
+    - ./fixed_point.conf
+  util.math.floating_point:
+    extra_overlay_confs:
+    - ./floating_point.conf
diff --git a/zephyr/test/nissa/CMakeLists.txt b/zephyr/test/nissa/CMakeLists.txt
new file mode 100644
index 0000000000..d6453a3fef
--- /dev/null
+++ b/zephyr/test/nissa/CMakeLists.txt
@@ -0,0 +1,58 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(nissa)
+
+add_subdirectory(${PLATFORM_EC}/zephyr/test/test_utils test_utils)
+
+zephyr_include_directories("${PLATFORM_EC_PROGRAM_DIR}/nissa/include")
+
+target_sources(app PRIVATE src/stubs.c)
+
+target_sources_ifdef(
+        CONFIG_TEST_NISSA_SUB_BOARD
+        app PRIVATE
+        src/sub_board.c
+        src/log_module.c
+        ${PLATFORM_EC_PROGRAM_DIR}/nissa/src/sub_board.c)
+
+target_sources_ifdef(
+        CONFIG_TEST_NISSA_COMMON
+        app PRIVATE
+        src/common.c
+        ${PLATFORM_EC_PROGRAM_DIR}/nissa/src/common.c)
+
+target_sources_ifdef(
+        CONFIG_TEST_NISSA_NIVVIKS
+        app PRIVATE
+        src/nivviks.c
+        ${PLATFORM_EC_PROGRAM_DIR}/nissa/nivviks/src/fan.c
+        ${PLATFORM_EC_PROGRAM_DIR}/nissa/nivviks/src/form_factor.c
+        ${PLATFORM_EC_PROGRAM_DIR}/nissa/nivviks/src/keyboard.c
+        ${PLATFORM_EC_PROGRAM_DIR}/nissa/nivviks/src/led.c
+)
+
+if(CONFIG_TEST_NISSA_NIVVIKS_CHARGER)
+    target_compile_definitions(app PRIVATE CHARGER_PRIMARY=0 CHARGER_SECONDARY=1)
+    target_sources(
+            app PRIVATE
+            src/nivviks_charger.c
+            ${PLATFORM_EC_PROGRAM_DIR}/nissa/nivviks/src/usbc.c
+            ${PLATFORM_EC_PROGRAM_DIR}/nissa/nivviks/src/charger.c
+    )
+endif()
+
+if(CONFIG_TEST_NISSA_NEREID)
+    target_compile_definitions(app PRIVATE CHARGER_PRIMARY=0 CHARGER_SECONDARY=1)
+    target_sources(
+            app PRIVATE
+            src/nereid.c
+            ${PLATFORM_EC_PROGRAM_DIR}/nissa/nereid/src/charger.c
+            ${PLATFORM_EC_PROGRAM_DIR}/nissa/nereid/src/hdmi.c
+            ${PLATFORM_EC_PROGRAM_DIR}/nissa/nereid/src/keyboard.c
+            ${PLATFORM_EC_PROGRAM_DIR}/nissa/nereid/src/usbc.c
+    )
+endif()
diff --git a/zephyr/test/nissa/Kconfig b/zephyr/test/nissa/Kconfig
new file mode 100644
index 0000000000..01519a9101
--- /dev/null
+++ b/zephyr/test/nissa/Kconfig
@@ -0,0 +1,48 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+choice TEST_TARGET
+	prompt "Select test target to build"
+	help
+	  Select the build target for a given test. Each test target must select
+	  exactly one, because some tests assume configuration that conflicts with
+	  others.
+
+	config TEST_NISSA_SUB_BOARD
+		bool "Tests for sub_board.c"
+		help
+		  The test target that exercises nissa/src/sub_board.c.
+
+	config TEST_NISSA_COMMON
+		bool "Tests for common.c"
+		help
+		  The test target that exercises nissa/src/common.c.
+
+	config TEST_NISSA_NIVVIKS
+	  bool "Tests for Nivviks-specific code"
+	  help
+	    The test target that exercises nissa/nivviks/*.c
+
+	config TEST_NISSA_NIVVIKS_CHARGER
+	  bool "Tests for Nivviks-specific charger/USB-C code"
+	  select TEST_USB_PD_POLICY
+	  help
+	    The test target that exercises nissa/nivviks/{charger,usbc}.c
+
+	config TEST_NISSA_NEREID
+	  bool "Tests for Nereid-specific code"
+	  help
+		The test target that exercises nissa/nereid/*.c
+endchoice
+
+config TEST_USB_PD_POLICY
+	bool
+	help
+	  Enable mocking of chipset_in_state() for PD policy testing.
+
+module = NISSA
+module-str = Nissa board-specific code (unit tests)
+source "subsys/logging/Kconfig.template.log_config"
+
+source "Kconfig.zephyr"
diff --git a/zephyr/test/nissa/README.md b/zephyr/test/nissa/README.md
new file mode 100644
index 0000000000..17737fcba5
--- /dev/null
+++ b/zephyr/test/nissa/README.md
@@ -0,0 +1,3 @@
+Tests for board specific code under `zephyr/program/nissa/`
+
+Run with ./twister -T zephyr/test/nissa
diff --git a/zephyr/test/nissa/boards/battery.dts b/zephyr/test/nissa/boards/battery.dts
new file mode 100644
index 0000000000..b2259c0463
--- /dev/null
+++ b/zephyr/test/nissa/boards/battery.dts
@@ -0,0 +1,12 @@
+&i2c_ctrl7 {
+	battery: sb@b {
+		compatible = "zephyr,smart-battery-emul";
+		reg = <0xb>;
+		cycle-count = <6>;
+		version = "BATTERY_SPEC_VER_1_1_WITH_PEC";
+		desired-charg-volt = <11250>;
+		desired-charg-cur = <2400>;
+		mf-name = "LGC";
+		dev-name = "AP18C8K";
+	};
+};
diff --git a/zephyr/test/nissa/boards/chargers.dts b/zephyr/test/nissa/boards/chargers.dts
new file mode 100644
index 0000000000..82235784d8
--- /dev/null
+++ b/zephyr/test/nissa/boards/chargers.dts
@@ -0,0 +1,42 @@
+/ {
+	named-i2c-ports {
+		i2c_ec_i2c_batt: ec_i2c_batt {
+			i2c-port = <&i2c_ctrl7>;
+			enum-names = "I2C_PORT_BATTERY";
+		};
+	};
+
+	usbc {
+		port0@0 {
+			chg = <&chg_port0>;
+		};
+		port1@1 {
+			chg = <&chg_port1>;
+		};
+	};
+
+	batteries {
+		default_battery: lgc {
+			compatible = "lgc,ap18c8k", "battery-smart";
+		};
+	};
+};
+
+&i2c_ctrl3 {
+	chg_port0: sm5803_primary@32 {
+		compatible = "cros,sm5803-emul", "siliconmitus,sm5803";
+		status = "okay";
+		reg = <0x32>;
+		interrupt-gpios = <&gpio0 1 GPIO_INPUT_PULL_UP>;
+	};
+};
+
+&i2c_ctrl5 {
+	chg_port1: sm5803_secondary@32 {
+		compatible = "cros,sm5803-emul", "siliconmitus,sm5803";
+		status = "okay";
+		reg = <0x32>;
+		interrupt-gpios = <&gpio0 2 GPIO_INPUT_PULL_UP>;
+	};
+};
+
diff --git a/zephyr/test/nissa/boards/generic_npcx.dts b/zephyr/test/nissa/boards/generic_npcx.dts
new file mode 100644
index 0000000000..f08e2caebb
--- /dev/null
+++ b/zephyr/test/nissa/boards/generic_npcx.dts
@@ -0,0 +1,185 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Device tree for a generic Nissa device based on a NPCX EC, suitable for board
+ * unit tests.
+ */
+#include <npcx_emul.dts>
+#include "../program/nissa/cbi.dtsi"
+
+/ {
+	aliases {
+		/* type-C */
+		gpio-usb-c1-int-odl = &gpio_sb_1;
+		/* type-A */
+		gpio-en-usb-a1-vbus = &gpio_sb_2;
+		/* HDMI */
+		gpio-en-rails-odl = &gpio_sb_1;
+		gpio-hdmi-en-odl = &gpio_sb_3;
+		gpio-hpd-odl = &gpio_sb_4;
+		/* LTE */
+		gpio-en-sub-s5-rails = &gpio_sb_2;
+
+		gpio-wp = &gpio_ec_wp_odl;
+	};
+
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_usb_c0: usb_c0 {
+			irq-pin = <&gpio_usb_c0_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "usb_interrupt_c0";
+		};
+
+		int_usb_c1: usb_c1 {
+			irq-pin = <&gpio_sb_1>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "usb_interrupt_c1";
+		};
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		gpio_ec_soc_dsw_pwrok: ec_soc_dsw_pwrok {
+			gpios = <&gpio6 1 GPIO_OUTPUT>;
+		};
+
+		gpio_ec_soc_hdmi_hpd: ec_soc_hdmi_hpd {
+			gpios = <&gpioe 4 GPIO_OUTPUT>;
+		};
+
+		gpio_ec_wp_odl: ec_wp_odl {
+			gpios = <&gpioa 1 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+
+		entering_rw {
+			gpios = <&gpio0 3 GPIO_OUTPUT>;
+			enum-name = "GPIO_ENTERING_RW";
+		};
+
+		gpio_en_pp5000_pen_x: en_pp5000_pen_x {
+			gpios = <&gpioe 2 GPIO_OUTPUT>;
+		};
+
+		gpio_en_slp_z: en_slp_z {
+			gpios = <&gpioe 1 GPIO_OUTPUT>;
+		};
+
+		gpio_hdmi_sel: hdmi_sel {
+			gpios = <&gpioc 6 GPIO_OUTPUT>;
+		};
+
+		gpio_usb_a0_enable: usb_a0_enable {
+			gpios = <&gpio1 0 GPIO_OUTPUT>;
+		};
+
+		gpio_usb_a0_ilimit_sdp: usb_a0_ilimit_sdp {
+			gpios = <&gpio1 2 GPIO_OUTPUT>;
+			enum-name = "GPIO_USB1_ILIM_SEL";
+		};
+
+		gpio_sub_usb_a1_ilimit_sdp: usb_a1_ilimit_sdp {
+			gpios = <&gpio1 3 GPIO_OUTPUT>;
+			enum-name = "GPIO_USB2_ILIM_SEL";
+		};
+
+		gpio_usb_c0_int_odl: usb_c0_int_odl {
+			gpios = <&gpio0 1 GPIO_INPUT_PULL_UP>;
+		};
+
+		gpio_sb_1: sb-1 {
+			gpios = <&gpio0 2 GPIO_PULL_UP>;
+			no-auto-init;
+		};
+
+		gpio_sb_2: sb-2 {
+			gpios = <&gpiod 4 GPIO_OUTPUT>;
+			no-auto-init;
+		};
+
+		gpio_sb_3: sb-3 {
+			gpios = <&gpiof 4 0>;
+			no-auto-init;
+		};
+
+		gpio_sb_4: sb-4 {
+			gpios = <&gpiof 5 GPIO_INPUT>;
+			no-auto-init;
+		};
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+		i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 {
+			i2c-port = <&i2c_ctrl0>;
+			enum-names = "I2C_PORT_USB_C0_TCPC";
+		};
+		i2c_ec_i2c_sub_usb_c1: ec_i2c_sub_usb_c1 {
+			i2c-port = <&i2c_ctrl1>;
+			enum-names = "I2C_PORT_USB_C1_TCPC";
+		};
+	};
+
+	usba {
+		compatible = "cros-ec,usba-port-enable-pins";
+		enable-pins = <&gpio_usb_a0_enable &gpio_sb_2>;
+		status = "okay";
+	};
+
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+			tcpc = <&tcpci_emul_0>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_0>;
+			};
+		};
+		port1@1 {
+			compatible = "named-usbc-port";
+			reg = <1>;
+			tcpc = <&tcpci_emul_1>;
+			usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_1>;
+			};
+			usb_mux_chain_1_no_mux: usb-mux-chain-1-alternate {
+				compatible = "cros-ec,usb-mux-chain";
+				alternative-chain;
+				usb-muxes = <&virtual_mux_1>;
+			};
+		};
+		port0-muxes {
+			virtual_mux_0: virtual-mux-0 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+		port1-muxes {
+			virtual_mux_1: virtual-mux-1 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+	};
+};
+
+&i2c_ctrl0 {
+	tcpci_emul_0: tcpci_emul@82 {
+		compatible = "cros,tcpci-generic-emul";
+		status = "okay";
+		reg = <0x82>;
+	};
+};
+
+&i2c_ctrl1 {
+	tcpci_emul_1: tcpci_emul@84 {
+		compatible = "cros,tcpci-generic-emul";
+		status = "okay";
+		reg = <0x84>;
+	};
+};
diff --git a/zephyr/test/nissa/boards/nereid.dts b/zephyr/test/nissa/boards/nereid.dts
new file mode 100644
index 0000000000..272ea07d63
--- /dev/null
+++ b/zephyr/test/nissa/boards/nereid.dts
@@ -0,0 +1,91 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include <it8xxx2_emul.dts>
+
+/ {
+	aliases {
+		gpio-usb-c1-int-odl = &gpio_sb_1;
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		gpio_ec_entering_rw: ec_entering_rw {
+			gpios = <&gpioc 7 GPIO_OUTPUT>;
+			enum-name = "GPIO_ENTERING_RW";
+		};
+		gpio_en_usb_c0_cc1_vconn: en_usb_c0_cc1_vconn {
+			gpios = <&gpioh 4 GPIO_OUTPUT>;
+		};
+		gpio_en_usb_c0_cc2_vconn: en_usb_c0_cc2_vconn {
+			gpios = <&gpioh 6 GPIO_OUTPUT>;
+		};
+		gpio_usb_c0_int_odl: usb_c0_int_odl {
+			gpios = <&gpiok 0 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_sb_1: sb_1 {
+			gpios = <&gpioe 6 0>;
+			no-auto-init;
+		};
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		i2c_ec_i2c_batt: ec_i2c_batt {
+			i2c-port = <&i2c_ctrl0>;
+			enum-names = "I2C_PORT_BATTERY";
+		};
+	};
+
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+			tcpc = <&tcpci_emul_0>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_0>;
+			};
+		};
+		port1@1 {
+			compatible = "named-usbc-port";
+			reg = <1>;
+			tcpc = <&tcpci_emul_1>;
+			usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_1>;
+			};
+		};
+		port0-muxes {
+			virtual_mux_0: virtual-mux-0 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+		port1-muxes {
+			virtual_mux_1: virtual-mux-1 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+	};
+};
+
+&i2c_ctrl4 {
+	tcpci_emul_0: tcpci_emul@82 {
+		compatible = "cros,tcpci-generic-emul";
+		status = "okay";
+		reg = <0x82>;
+	};
+};
+
+&i2c_ctrl4 {
+	tcpci_emul_1: tcpci_emul@84 {
+		compatible = "cros,tcpci-generic-emul";
+		status = "okay";
+		reg = <0x84>;
+	};
+};
diff --git a/zephyr/test/nissa/boards/nivviks.dts b/zephyr/test/nissa/boards/nivviks.dts
new file mode 100644
index 0000000000..9d0da09e15
--- /dev/null
+++ b/zephyr/test/nissa/boards/nivviks.dts
@@ -0,0 +1,61 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/pwm/pwm.h>
+
+#include "../program/nissa/nivviks/cbi.dtsi"
+#include "../program/nissa/nivviks/motionsense.dtsi"
+
+/ {
+	named-gpios {
+		gpio_fan_enable: fan-enable {
+			gpios = <&gpio6 3 GPIO_OUTPUT>;
+			no-auto-init;
+		};
+	};
+
+	named-i2c-ports {
+		i2c_ec_i2c_sensor: ec_i2c_sensor {
+			i2c-port = <&i2c_ctrl1>;
+			enum-names = "I2C_PORT_SENSOR";
+		};
+	};
+
+	/* LEDs need to exist for testing, but aren't actually used. */
+	led-pwms {
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		pwm_red: pwm@0 {
+			compatible = "cros,pwm-mock";
+			reg = <0 1>;
+			#pwm-cells = <3>;
+		};
+	};
+
+	pwm-leds {
+		compatible = "pwm-leds";
+
+		pwm_led0: led0 {
+			pwms = <&pwm_red 0 PWM_HZ(324) PWM_POLARITY_INVERTED>;
+		};
+	};
+
+	cros-pwmleds {
+		compatible = "cros-ec,pwm-leds";
+		leds = <&pwm_led0>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pwm_led_0@0 {
+			reg = <0>;
+			ec-led-name = "EC_LED_ID_BATTERY_LED";
+		};
+	};
+
+	/* Sensors need to exist for this test but aren't actually used. */
+	/delete-node/ motionsense-sensor-info;
+};
diff --git a/zephyr/test/nissa/charger.conf b/zephyr/test/nissa/charger.conf
new file mode 100644
index 0000000000..d96973deb5
--- /dev/null
+++ b/zephyr/test/nissa/charger.conf
@@ -0,0 +1,24 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Additional configuration for emulated Nissa boards where tests require
+# charger-related code.
+
+CONFIG_PLATFORM_EC_HOSTCMD=y
+CONFIG_PLATFORM_EC_CHARGER=y
+CONFIG_PLATFORM_EC_OCPC=y
+CONFIG_PLATFORM_EC_CHARGER_SM5803=y
+CONFIG_PLATFORM_EC_CHARGER_RAA489000=y
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=10
+CONFIG_PLATFORM_EC_OCPC_DEF_RBATT_MOHMS=22
+CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_ADC_AMON_BMON=n
+CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_CHARGER=y
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
+CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y
+# charger_get_system_power() in RAA489000 driver
+CONFIG_PLATFORM_EC_CHARGER_PSYS_READ=n
+CONFIG_ADC_SHELL=n
+CONFIG_PLATFORM_EC_PD_MAX_VOLTAGE_MV=15000
+CONFIG_PLATFORM_EC_VBOOT_HASH=n
diff --git a/zephyr/test/nissa/prj.conf b/zephyr/test/nissa/prj.conf
new file mode 100644
index 0000000000..6bdc18671c
--- /dev/null
+++ b/zephyr/test/nissa/prj.conf
@@ -0,0 +1,27 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_ZTEST=y
+CONFIG_ZTEST_ASSERT_VERBOSE=1
+CONFIG_ZTEST_NEW_API=y
+CONFIG_ASSERT=y
+
+CONFIG_CROS_EC=y
+CONFIG_PLATFORM_EC=y
+
+# Configuration used for Nissa boards, with some items that aren't relevant
+# disabled so they don't depend on us defining items they want.
+CONFIG_PLATFORM_EC_USBC=y
+CONFIG_PLATFORM_EC_USBC_PPC=n
+CONFIG_PLATFORM_EC_USB_MUX_RUNTIME_CONFIG=y
+CONFIG_PLATFORM_EC_USB_PD_DISCHARGE=n
+CONFIG_PLATFORM_EC_USB_CHARGER=n
+CONFIG_PLATFORM_EC_USB_PD_HOST_CMD=n
+CONFIG_PLATFORM_EC_USB_PORT_ENABLE_DYNAMIC=y
+CONFIG_PLATFORM_EC_SWITCH=n
+
+# Allow the test fixture to use k_malloc
+CONFIG_HEAP_MEM_POOL_SIZE=1024
+
+CONFIG_GPIO_GET_CONFIG=y
\ No newline at end of file
diff --git a/zephyr/test/nissa/src/common.c b/zephyr/test/nissa/src/common.c
new file mode 100644
index 0000000000..2c97fb4e76
--- /dev/null
+++ b/zephyr/test/nissa/src/common.c
@@ -0,0 +1,128 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ap_power/ap_power_events.h"
+#include "battery.h"
+#include "charger.h"
+#include "emul/emul_sm5803.h"
+#include "hooks.h"
+#include "ocpc.h"
+#include "usb_pd.h"
+
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/fff.h>
+#include <zephyr/ztest.h>
+
+FAKE_VALUE_FUNC(enum battery_present, battery_is_present);
+FAKE_VALUE_FUNC(int, board_set_active_charge_port, int);
+FAKE_VALUE_FUNC(uint8_t, board_get_usb_pd_port_count);
+FAKE_VALUE_FUNC(int, power_button_is_pressed);
+
+static void suite_before(void *fixture)
+{
+	RESET_FAKE(battery_is_present);
+	RESET_FAKE(board_get_usb_pd_port_count);
+	board_get_usb_pd_port_count_fake.return_val = 2;
+	RESET_FAKE(board_set_active_charge_port);
+	RESET_FAKE(power_button_is_pressed);
+}
+
+ZTEST_SUITE(nissa_common, NULL, NULL, suite_before, NULL, NULL);
+
+ZTEST(nissa_common, test_pen_power_control)
+{
+	const struct gpio_dt_spec *const pen_power =
+		GPIO_DT_FROM_NODELABEL(gpio_en_pp5000_pen_x);
+
+	hook_notify(HOOK_INIT);
+	zassert_false(gpio_emul_output_get(pen_power->port, pen_power->pin),
+		      "Pen power should be off by default");
+
+	ap_power_ev_send_callbacks(AP_POWER_STARTUP);
+	zassert_true(gpio_emul_output_get(pen_power->port, pen_power->pin),
+		     "Pen power should be on after AP startup");
+
+	ap_power_ev_send_callbacks(AP_POWER_SHUTDOWN);
+	zassert_false(gpio_emul_output_get(pen_power->port, pen_power->pin),
+		      "Pen power should be off after AP shutdown");
+}
+
+ZTEST(nissa_common, test_hibernate)
+{
+	const struct gpio_dt_spec *const hibernate_enable =
+		GPIO_DT_FROM_NODELABEL(gpio_en_slp_z);
+
+	zassert_false(gpio_emul_output_get(hibernate_enable->port,
+					   hibernate_enable->pin),
+		      "Hibernate pin should be low by default");
+	board_hibernate_late();
+	zassert_true(gpio_emul_output_get(hibernate_enable->port,
+					  hibernate_enable->pin),
+		     "Hibernate pin should go high to hibernate");
+}
+
+ZTEST(nissa_common, test_vconn_swap)
+{
+	const struct gpio_dt_spec *const dsw_pwrok =
+		GPIO_DT_FROM_NODELABEL(gpio_ec_soc_dsw_pwrok);
+
+	/* AP 5V rail is off. */
+	zassert_false(gpio_pin_get_dt(dsw_pwrok));
+	zassert_false(pd_check_vconn_swap(0));
+	zassert_false(pd_check_vconn_swap(1));
+
+	/*
+	 * Case with the rail on is untestable because emulated GPIOs don't
+	 * allow getting the current value of output pins.
+	 */
+}
+
+ZTEST(nissa_common, test_ocpc_configuration)
+{
+	int kp, kp_div;
+	int ki, ki_div;
+	int kd, kd_div;
+	struct ocpc_data ocpc_data = {};
+
+	ocpc_get_pid_constants(&kp, &kp_div, &ki, &ki_div, &kd, &kd_div);
+
+	/*
+	 * Only proportional control is used, at 1/32 gain. Gain of integral and
+	 * derivative terms is zero.
+	 */
+	zassert_equal(kp, 1);
+	zassert_equal(kp_div, 32);
+	zassert_equal(ki, 0);
+	zassert_not_equal(ki_div, 0);
+	zassert_equal(kd, 0);
+	zassert_not_equal(kd_div, 0);
+
+	/* With two chargers, we note that Isys can't be measured. */
+	zassert_equal(CONFIG_USB_PD_PORT_MAX_COUNT, 2);
+	board_get_usb_pd_port_count_fake.return_val = 2;
+	board_ocpc_init(&ocpc_data);
+	zassert_equal(ocpc_data.chg_flags[1], OCPC_NO_ISYS_MEAS_CAP);
+}
+
+void board_get_battery_cells(void);
+
+ZTEST(nissa_common, test_sm5803_buck_boost_forbidden)
+{
+	const struct emul *const charger_emul =
+		EMUL_DT_GET(DT_NODELABEL(chg_port0));
+	int cells;
+
+	/* Default 2S PMODE allows 12V charging. */
+	zassert_ok(charger_get_battery_cells(0, &cells));
+	zassert_equal(cells, 2);
+	zassert_true(pd_is_valid_input_voltage(12000));
+
+	/* 3S forbids 12V charging. */
+	sm5803_emul_set_pmode(charger_emul, 0x16 /* 3S, 1.5A with BFET */);
+	zassert_ok(charger_get_battery_cells(0, &cells));
+	zassert_equal(cells, 3);
+	board_get_battery_cells(); /* Refresh cached cell count */
+	zassert_false(pd_is_valid_input_voltage(12000));
+}
diff --git a/zephyr/test/nissa/src/log_module.c b/zephyr/test/nissa/src/log_module.c
new file mode 100644
index 0000000000..e8556a5886
--- /dev/null
+++ b/zephyr/test/nissa/src/log_module.c
@@ -0,0 +1,8 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(nissa, CONFIG_NISSA_LOG_LEVEL);
diff --git a/zephyr/test/nissa/src/nereid.c b/zephyr/test/nissa/src/nereid.c
new file mode 100644
index 0000000000..e5eb655225
--- /dev/null
+++ b/zephyr/test/nissa/src/nereid.c
@@ -0,0 +1,418 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ap_power/ap_power_events.h"
+#include "charge_manager.h"
+#include "emul/tcpc/emul_tcpci.h"
+#include "extpower.h"
+#include "keyboard_protocol.h"
+#include "nissa_hdmi.h"
+#include "system.h"
+#include "tcpm/tcpci.h"
+#include "typec_control.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/fff.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/ztest.h>
+
+LOG_MODULE_REGISTER(nissa, LOG_LEVEL_INF);
+
+extern const struct ec_response_keybd_config nereid_kb_legacy;
+
+FAKE_VOID_FUNC(nissa_configure_hdmi_rails);
+FAKE_VOID_FUNC(nissa_configure_hdmi_vcc);
+FAKE_VALUE_FUNC(int, cbi_get_board_version, uint32_t *);
+
+FAKE_VALUE_FUNC(enum ec_error_list, sm5803_is_acok, int, bool *);
+FAKE_VALUE_FUNC(bool, sm5803_check_vbus_level, int, enum vbus_level);
+FAKE_VOID_FUNC(sm5803_disable_low_power_mode, int);
+FAKE_VOID_FUNC(sm5803_enable_low_power_mode, int);
+FAKE_VALUE_FUNC(enum ec_error_list, sm5803_vbus_sink_enable, int, int);
+FAKE_VALUE_FUNC(enum ec_error_list, sm5803_set_vbus_disch, int, int);
+FAKE_VOID_FUNC(sm5803_hibernate, int);
+FAKE_VOID_FUNC(sm5803_interrupt, int);
+FAKE_VOID_FUNC(sm5803_handle_interrupt, int);
+FAKE_VALUE_FUNC(enum ec_error_list, sm5803_get_chg_det, int, int *);
+
+FAKE_VALUE_FUNC(enum ec_error_list, charger_set_otg_current_voltage, int, int,
+		int);
+FAKE_VALUE_FUNC(enum ec_error_list, charger_enable_otg_power, int, int);
+FAKE_VALUE_FUNC(int, charger_is_sourcing_otg_power, int);
+FAKE_VOID_FUNC(extpower_handle_update, int);
+FAKE_VOID_FUNC(charger_discharge_on_ac, int);
+FAKE_VALUE_FUNC(int, charge_manager_get_active_charge_port);
+FAKE_VOID_FUNC(usb_charger_task_set_event, int, uint8_t);
+FAKE_VOID_FUNC(usb_charger_task_set_event_sync, int, uint8_t);
+
+uint8_t board_get_charger_chip_count(void)
+{
+	return 2;
+}
+
+static void test_before(void *fixture)
+{
+	RESET_FAKE(nissa_configure_hdmi_rails);
+	RESET_FAKE(nissa_configure_hdmi_vcc);
+	RESET_FAKE(cbi_get_board_version);
+
+	RESET_FAKE(sm5803_is_acok);
+	RESET_FAKE(sm5803_check_vbus_level);
+	RESET_FAKE(sm5803_disable_low_power_mode);
+	RESET_FAKE(sm5803_enable_low_power_mode);
+	RESET_FAKE(sm5803_vbus_sink_enable);
+	RESET_FAKE(sm5803_set_vbus_disch);
+	RESET_FAKE(sm5803_hibernate);
+	RESET_FAKE(sm5803_interrupt);
+	RESET_FAKE(sm5803_handle_interrupt);
+	RESET_FAKE(sm5803_get_chg_det);
+
+	RESET_FAKE(charger_set_otg_current_voltage);
+	RESET_FAKE(charger_enable_otg_power);
+	RESET_FAKE(charger_is_sourcing_otg_power);
+	RESET_FAKE(extpower_handle_update);
+	RESET_FAKE(charger_discharge_on_ac);
+	RESET_FAKE(charge_manager_get_active_charge_port);
+	RESET_FAKE(usb_charger_task_set_event);
+	RESET_FAKE(usb_charger_task_set_event_sync);
+}
+
+ZTEST_SUITE(nereid, NULL, NULL, test_before, NULL, NULL);
+
+ZTEST(nereid, test_keyboard_config)
+{
+	zassert_equal_ptr(board_vivaldi_keybd_config(), &nereid_kb_legacy);
+}
+
+static int cbi_get_board_version_1(uint32_t *version)
+{
+	*version = 1;
+	return 0;
+}
+
+static int cbi_get_board_version_2(uint32_t *version)
+{
+	*version = 2;
+	return 0;
+}
+
+ZTEST(nereid, test_hdmi_power)
+{
+	/* Board version less than 2 configures both */
+	cbi_get_board_version_fake.custom_fake = cbi_get_board_version_1;
+	nissa_configure_hdmi_power_gpios();
+	zassert_equal(nissa_configure_hdmi_vcc_fake.call_count, 1);
+	zassert_equal(nissa_configure_hdmi_rails_fake.call_count, 1);
+
+	/* Later versions only enable core rails */
+	cbi_get_board_version_fake.custom_fake = cbi_get_board_version_2;
+	nissa_configure_hdmi_power_gpios();
+	zassert_equal(nissa_configure_hdmi_vcc_fake.call_count, 1);
+	zassert_equal(nissa_configure_hdmi_rails_fake.call_count, 2);
+}
+
+static enum ec_error_list sm5803_is_acok_fake_no(int chgnum, bool *acok)
+{
+	*acok = false;
+	return EC_SUCCESS;
+}
+
+static enum ec_error_list sm5803_is_acok_fake_yes(int chgnum, bool *acok)
+{
+	*acok = true;
+	return EC_SUCCESS;
+}
+
+ZTEST(nereid, test_extpower_is_present)
+{
+	/* Errors are not-OK */
+	sm5803_is_acok_fake.return_val = EC_ERROR_UNKNOWN;
+	zassert_false(extpower_is_present());
+	zassert_equal(sm5803_is_acok_fake.call_count, 2);
+
+	/* When neither charger is connected, we check both and return no. */
+	sm5803_is_acok_fake.custom_fake = sm5803_is_acok_fake_no;
+	zassert_false(extpower_is_present());
+	zassert_equal(sm5803_is_acok_fake.call_count, 4);
+
+	/* If one is connected, AC is present */
+	sm5803_is_acok_fake.custom_fake = sm5803_is_acok_fake_yes;
+	zassert_true(extpower_is_present());
+	zassert_equal(sm5803_is_acok_fake.call_count, 5);
+}
+
+ZTEST(nereid, test_board_check_extpower)
+{
+	/* Initial state is stable not-present */
+	sm5803_is_acok_fake.custom_fake = sm5803_is_acok_fake_no;
+	board_check_extpower();
+	RESET_FAKE(extpower_handle_update);
+
+	/* Unchanged state does nothing */
+	board_check_extpower();
+	zassert_equal(extpower_handle_update_fake.call_count, 0);
+
+	/* Changing the state triggers extpower_handle_update() */
+	sm5803_is_acok_fake.custom_fake = sm5803_is_acok_fake_yes;
+	board_check_extpower();
+	zassert_equal(extpower_handle_update_fake.call_count, 1);
+}
+
+ZTEST(nereid, test_board_hibernate)
+{
+	board_hibernate();
+	zassert_equal(sm5803_hibernate_fake.call_count, 2);
+}
+
+ZTEST(nereid, test_board_vconn_control)
+{
+	const struct gpio_dt_spec *cc1 =
+		GPIO_DT_FROM_NODELABEL(gpio_en_usb_c0_cc1_vconn);
+	const struct gpio_dt_spec *cc2 =
+		GPIO_DT_FROM_NODELABEL(gpio_en_usb_c0_cc2_vconn);
+
+	/* Both off initially */
+	gpio_pin_set_dt(cc1, 0);
+	gpio_pin_set_dt(cc2, 0);
+
+	/* Port 1 isn't managed through this function */
+	board_pd_vconn_ctrl(1, USBPD_CC_PIN_1, 1);
+	zassert_false(gpio_emul_output_get(cc1->port, cc1->pin));
+
+	/* We can enable or disable CC1 */
+	board_pd_vconn_ctrl(0, USBPD_CC_PIN_1, 1);
+	zassert_true(gpio_emul_output_get(cc1->port, cc1->pin));
+	board_pd_vconn_ctrl(0, USBPD_CC_PIN_1, 0);
+	zassert_false(gpio_emul_output_get(cc1->port, cc1->pin));
+
+	/* .. or CC2 */
+	board_pd_vconn_ctrl(0, USBPD_CC_PIN_2, 1);
+	zassert_true(gpio_emul_output_get(cc2->port, cc2->pin));
+	board_pd_vconn_ctrl(0, USBPD_CC_PIN_2, 0);
+	zassert_false(gpio_emul_output_get(cc2->port, cc2->pin));
+}
+
+ZTEST(nereid, test_pd_check_vbus_level)
+{
+	/* pd_check_vbus_level delegates directly to sm5803_check_vbus_level */
+	pd_check_vbus_level(1, VBUS_PRESENT);
+	zassert_equal(sm5803_check_vbus_level_fake.call_count, 1);
+	zassert_equal(sm5803_check_vbus_level_fake.arg0_val, 1);
+	zassert_equal(sm5803_check_vbus_level_fake.arg1_val, VBUS_PRESENT);
+}
+
+ZTEST(nereid, test_chargers_suspend)
+{
+	ap_power_ev_send_callbacks(AP_POWER_RESUME);
+	zassert_equal(sm5803_disable_low_power_mode_fake.call_count, 2);
+
+	ap_power_ev_send_callbacks(AP_POWER_SUSPEND);
+	zassert_equal(sm5803_enable_low_power_mode_fake.call_count, 2);
+}
+
+ZTEST(nereid, test_set_active_charge_port)
+{
+	/* Asking for an invalid port is an error */
+	zassert_equal(board_set_active_charge_port(3), EC_ERROR_INVAL);
+
+	/* A port that's sourcing won't sink */
+	charger_is_sourcing_otg_power_fake.return_val = true;
+	zassert_equal(board_set_active_charge_port(0), EC_ERROR_INVAL);
+	RESET_FAKE(charger_is_sourcing_otg_power);
+
+	/* Enabling a port disables the other one then enables it */
+	charge_manager_get_active_charge_port_fake.return_val = 1;
+	zassert_ok(board_set_active_charge_port(0));
+	zassert_equal(sm5803_vbus_sink_enable_fake.call_count, 2);
+	zassert_equal(sm5803_vbus_sink_enable_fake.arg0_history[0], 1);
+	zassert_equal(sm5803_vbus_sink_enable_fake.arg1_history[0], 0);
+	zassert_equal(sm5803_vbus_sink_enable_fake.arg0_history[1], 0);
+	zassert_equal(sm5803_vbus_sink_enable_fake.arg1_history[1], 1);
+	/* It also temporarily requested discharge on AC */
+	zassert_equal(charger_discharge_on_ac_fake.call_count, 2);
+	zassert_equal(charger_discharge_on_ac_fake.arg0_history[0], 1);
+	zassert_equal(charger_discharge_on_ac_fake.arg0_history[1], 0);
+	RESET_FAKE(charger_discharge_on_ac);
+
+	/* Requesting no port skips the enable step */
+	RESET_FAKE(sm5803_vbus_sink_enable);
+	zassert_ok(board_set_active_charge_port(CHARGE_PORT_NONE));
+	zassert_equal(sm5803_vbus_sink_enable_fake.call_count, 2);
+	zassert_equal(sm5803_vbus_sink_enable_fake.arg0_history[0], 0);
+	zassert_equal(sm5803_vbus_sink_enable_fake.arg1_history[0], 0);
+	zassert_equal(sm5803_vbus_sink_enable_fake.arg0_history[1], 1);
+	zassert_equal(sm5803_vbus_sink_enable_fake.arg1_history[1], 0);
+
+	/* Errors bubble up */
+	sm5803_vbus_sink_enable_fake.return_val = EC_ERROR_UNKNOWN;
+	zassert_equal(board_set_active_charge_port(0), EC_ERROR_UNKNOWN);
+}
+
+ZTEST(nereid, test_tcpc_get_alert_status)
+{
+	const struct gpio_dt_spec *c1_int =
+		GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl);
+	/* GPIO is normally configured by code not tested in this case */
+	zassert_ok(gpio_pin_configure_dt(c1_int, GPIO_INPUT));
+
+	tcpci_emul_set_reg(EMUL_DT_GET(DT_NODELABEL(tcpci_emul_1)),
+			   TCPC_REG_ALERT, TCPC_REG_ALERT_CC_STATUS);
+
+	/* Nothing if the IRQ line isn't asserted */
+	zassert_ok(gpio_emul_input_set(c1_int->port, c1_int->pin, 1));
+	zassert_equal(tcpc_get_alert_status(), 0);
+
+	/* Alert active if it is and the alert register has bits set */
+	zassert_ok(gpio_emul_input_set(c1_int->port, c1_int->pin, 0));
+	zassert_equal(tcpc_get_alert_status(), PD_STATUS_TCPC_ALERT_1);
+}
+
+ZTEST(nereid, test_pd_power_supply_reset)
+{
+	charger_is_sourcing_otg_power_fake.return_val = 1;
+
+	/* Disables sourcing and discharges VBUS on active port */
+	pd_power_supply_reset(0);
+	zassert_equal(charger_enable_otg_power_fake.call_count, 1);
+	zassert_equal(charger_enable_otg_power_fake.arg0_val, 0);
+	zassert_equal(charger_enable_otg_power_fake.arg1_val, 0);
+	zassert_equal(sm5803_set_vbus_disch_fake.call_count, 1);
+	zassert_equal(sm5803_set_vbus_disch_fake.arg0_val, 0);
+	zassert_equal(sm5803_set_vbus_disch_fake.arg1_val, 1);
+
+	/* Invalid port does nothing */
+	pd_power_supply_reset(2);
+	zassert_equal(charger_is_sourcing_otg_power_fake.call_count, 1);
+}
+
+ZTEST(nereid, test_pd_set_power_supply_ready)
+{
+	zassert_ok(pd_set_power_supply_ready(0));
+	/* Disabled sinking */
+	zassert_equal(sm5803_vbus_sink_enable_fake.call_count, 1);
+	zassert_equal(sm5803_vbus_sink_enable_fake.arg0_val, 0);
+	zassert_false(sm5803_vbus_sink_enable_fake.arg1_val);
+	/* Disabled VBUS discharge */
+	zassert_equal(sm5803_set_vbus_disch_fake.call_count, 1);
+	zassert_equal(sm5803_set_vbus_disch_fake.arg0_val, 0);
+	zassert_false(sm5803_set_vbus_disch_fake.arg1_val);
+	/* Enabled sourcing */
+	zassert_equal(charger_enable_otg_power_fake.call_count, 1);
+	zassert_equal(charger_enable_otg_power_fake.arg0_val, 0);
+	zassert_true(charger_enable_otg_power_fake.arg1_val);
+
+	/* Errors cause early return */
+	charger_enable_otg_power_fake.return_val = EC_ERROR_UNKNOWN;
+	zassert_equal(pd_set_power_supply_ready(0), EC_ERROR_UNKNOWN);
+
+	sm5803_set_vbus_disch_fake.return_val = EC_ERROR_UNKNOWN;
+	zassert_equal(pd_set_power_supply_ready(0), EC_ERROR_UNKNOWN);
+
+	sm5803_vbus_sink_enable_fake.return_val = EC_ERROR_UNKNOWN;
+	zassert_equal(pd_set_power_supply_ready(0), EC_ERROR_UNKNOWN);
+
+	zassert_equal(pd_set_power_supply_ready(31), EC_ERROR_INVAL);
+}
+
+ZTEST(nereid, test_typec_set_source_current_limit)
+{
+	typec_set_source_current_limit(0, TYPEC_RP_3A0);
+
+	zassert_equal(charger_set_otg_current_voltage_fake.call_count, 1);
+	zassert_equal(charger_set_otg_current_voltage_fake.arg0_val, 0);
+	zassert_equal(charger_set_otg_current_voltage_fake.arg1_val, 3000);
+	zassert_equal(charger_set_otg_current_voltage_fake.arg2_val, 5000);
+
+	/* Errors are logged but otherwise ignored */
+	charger_set_otg_current_voltage_fake.return_val = EC_ERROR_UNKNOWN;
+	typec_set_source_current_limit(1, TYPEC_RP_1A5);
+	zassert_equal(charger_set_otg_current_voltage_fake.call_count, 2);
+}
+
+void usb_c0_interrupt(enum gpio_signal unused);
+
+ZTEST(nereid, test_c0_interrupt)
+{
+	const struct gpio_dt_spec *const c0_irq =
+		GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl);
+
+	gpio_emul_input_set(c0_irq->port, c0_irq->pin, 0);
+	usb_c0_interrupt(0);
+
+	/* Immediately notifies driver tasks */
+	zassert_equal(usb_charger_task_set_event_fake.call_count, 1);
+	zassert_equal(usb_charger_task_set_event_fake.arg0_val, 0);
+	zassert_equal(usb_charger_task_set_event_fake.arg1_val,
+		      USB_CHG_EVENT_BC12);
+	zassert_equal(sm5803_interrupt_fake.call_count, 1);
+	zassert_equal(sm5803_interrupt_fake.arg0_val, 0);
+
+	/*
+	 * Notifies again 5ms later if the IRQ is still asserted. It may take
+	 * more than 5ms to actually run the handler, so only ensure that it
+	 * gets run at least once in 100ms (which seems reliable).
+	 */
+	k_sleep(K_MSEC(100));
+	zassert_equal(sm5803_interrupt_fake.call_count,
+		      usb_charger_task_set_event_fake.call_count);
+	zassert_true(usb_charger_task_set_event_fake.call_count > 1,
+		     "handlers were notified %d time(s)",
+		     usb_charger_task_set_event_fake.call_count);
+
+	/*
+	 * Stops notifying once the IRQ is deasserted, even if
+	 * polls were pending.
+	 */
+	unsigned int notify_count = sm5803_interrupt_fake.call_count;
+
+	gpio_emul_input_set(c0_irq->port, c0_irq->pin, 1);
+	k_sleep(K_MSEC(100));
+	zassert_equal(usb_charger_task_set_event_fake.call_count, notify_count);
+	zassert_equal(sm5803_interrupt_fake.call_count,
+		      usb_charger_task_set_event_fake.call_count);
+}
+
+ZTEST(nereid, test_usb_c1_interrupt)
+{
+	const struct gpio_dt_spec *const c1_irq =
+		GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl);
+
+	gpio_emul_input_set(c1_irq->port, c1_irq->pin, 0);
+	board_process_pd_alert(1);
+	zassert_equal(sm5803_handle_interrupt_fake.call_count, 1);
+	zassert_equal(sm5803_handle_interrupt_fake.arg0_val, 1);
+	zassert_equal(usb_charger_task_set_event_sync_fake.call_count, 1);
+	zassert_equal(usb_charger_task_set_event_sync_fake.arg0_val, 1);
+	zassert_equal(usb_charger_task_set_event_sync_fake.arg1_val,
+		      USB_CHG_EVENT_BC12);
+
+	/* Does nothing if IRQ is not asserted */
+	gpio_emul_input_set(c1_irq->port, c1_irq->pin, 1);
+	board_process_pd_alert(1);
+	zassert_equal(sm5803_handle_interrupt_fake.call_count, 1);
+	zassert_equal(usb_charger_task_set_event_sync_fake.call_count, 1);
+
+	/* Does nothing for port 0 */
+	board_process_pd_alert(0);
+	zassert_equal(sm5803_handle_interrupt_fake.call_count, 1);
+	zassert_equal(usb_charger_task_set_event_sync_fake.call_count, 1);
+}
+
+static enum ec_error_list sm5803_get_chg_det_present(int port, int *present)
+{
+	*present = 1;
+	return EC_SUCCESS;
+}
+
+ZTEST(nereid, test_pd_snk_is_vbus_provided)
+{
+	/* pd_snk_is_vbus_provided just delegates to sm5803_get_chg_det */
+	sm5803_get_chg_det_fake.custom_fake = sm5803_get_chg_det_present;
+	zassert_true(pd_snk_is_vbus_provided(0));
+	zassert_equal(sm5803_get_chg_det_fake.call_count, 1);
+	zassert_equal(sm5803_get_chg_det_fake.arg0_val, 0);
+}
diff --git a/zephyr/test/nissa/src/nivviks.c b/zephyr/test/nissa/src/nivviks.c
new file mode 100644
index 0000000000..c0968d18d4
--- /dev/null
+++ b/zephyr/test/nissa/src/nivviks.c
@@ -0,0 +1,173 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "battery.h"
+#include "cros_cbi.h"
+#include "hooks.h"
+#include "keyboard_protocol.h"
+#include "led_pwm.h"
+#include "motionsense_sensors.h"
+#include "pwm_mock.h"
+
+#include <zephyr/fff.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/ztest.h>
+
+LOG_MODULE_REGISTER(nissa, LOG_LEVEL_INF);
+
+void fan_init(void);
+void form_factor_init(void);
+
+FAKE_VALUE_FUNC(int, cros_cbi_get_fw_config, enum cbi_fw_config_field_id,
+		uint32_t *);
+FAKE_VALUE_FUNC(enum battery_present, battery_is_present);
+FAKE_VOID_FUNC(board_set_active_charge_port, int);
+FAKE_VOID_FUNC(fan_set_count, int);
+FAKE_VOID_FUNC(set_pwm_led_color, enum pwm_led_id, int);
+
+static void nivviks_test_before(void *fixture)
+{
+	RESET_FAKE(cros_cbi_get_fw_config);
+	RESET_FAKE(battery_is_present);
+	RESET_FAKE(board_set_active_charge_port);
+	RESET_FAKE(fan_set_count);
+	RESET_FAKE(set_pwm_led_color);
+}
+
+ZTEST_SUITE(nivviks, NULL, NULL, nivviks_test_before, NULL, NULL);
+
+static int get_fan_config_present(enum cbi_fw_config_field_id field,
+				  uint32_t *value)
+{
+	zassert_equal(field, FW_FAN);
+	*value = FW_FAN_PRESENT;
+	return 0;
+}
+
+static int get_fan_config_absent(enum cbi_fw_config_field_id field,
+				 uint32_t *value)
+{
+	zassert_equal(field, FW_FAN);
+	*value = FW_FAN_NOT_PRESENT;
+	return 0;
+}
+
+ZTEST(nivviks, test_fan_present)
+{
+	int flags;
+
+	cros_cbi_get_fw_config_fake.custom_fake = get_fan_config_present;
+	fan_init();
+
+	zassert_equal(fan_set_count_fake.call_count, 0);
+	zassert_ok(gpio_pin_get_config_dt(
+		GPIO_DT_FROM_NODELABEL(gpio_fan_enable), &flags));
+	zassert_equal(flags, GPIO_OUTPUT | GPIO_OUTPUT_INIT_LOW,
+		      "actual GPIO flags were %#x", flags);
+}
+
+ZTEST(nivviks, test_fan_absent)
+{
+	int flags;
+
+	cros_cbi_get_fw_config_fake.custom_fake = get_fan_config_absent;
+	fan_init();
+
+	zassert_equal(fan_set_count_fake.call_count, 1,
+		      "function actually called %d times",
+		      fan_set_count_fake.call_count);
+	zassert_equal(fan_set_count_fake.arg0_val, 0, "parameter value was %d",
+		      fan_set_count_fake.arg0_val);
+
+	/* Fan enable is left unconfigured */
+	zassert_ok(gpio_pin_get_config_dt(
+		GPIO_DT_FROM_NODELABEL(gpio_fan_enable), &flags));
+	zassert_equal(flags, 0, "actual GPIO flags were %#x", flags);
+}
+
+ZTEST(nivviks, test_fan_cbi_error)
+{
+	int flags;
+
+	cros_cbi_get_fw_config_fake.return_val = EINVAL;
+	fan_init();
+
+	zassert_equal(fan_set_count_fake.call_count, 0);
+	zassert_ok(gpio_pin_get_config_dt(
+		GPIO_DT_FROM_NODELABEL(gpio_fan_enable), &flags));
+	zassert_equal(flags, 0, "actual GPIO flags were %#x", flags);
+}
+
+static int get_base_orientation_normal(enum cbi_fw_config_field_id field,
+				       uint32_t *value)
+{
+	zassert_equal(field, FW_BASE_INVERSION);
+	*value = FW_BASE_REGULAR;
+	return 0;
+}
+
+static int get_base_orientation_inverted(enum cbi_fw_config_field_id field,
+					 uint32_t *value)
+{
+	zassert_equal(field, FW_BASE_INVERSION);
+	*value = FW_BASE_INVERTED;
+	return 0;
+}
+
+ZTEST(nivviks, test_base_inversion)
+{
+	const int BASE_ACCEL = SENSOR_ID(DT_NODELABEL(base_accel));
+	const void *const normal_rotation =
+		&SENSOR_ROT_STD_REF_NAME(DT_NODELABEL(base_rot_ref));
+	const void *const inverted_rotation =
+		&SENSOR_ROT_STD_REF_NAME(DT_NODELABEL(base_rot_inverted));
+
+	/*
+	 * Normally this gets set to rot-standard-ref during other init,
+	 * which we aren't running in this test.
+	 */
+	motion_sensors[BASE_ACCEL].rot_standard_ref = normal_rotation;
+
+	cros_cbi_get_fw_config_fake.custom_fake = get_base_orientation_normal;
+	form_factor_init();
+	zassert_equal_ptr(
+		motion_sensors[BASE_ACCEL].rot_standard_ref, normal_rotation,
+		"normal orientation should use the standard rotation matrix");
+
+	RESET_FAKE(cros_cbi_get_fw_config);
+	cros_cbi_get_fw_config_fake.return_val = EINVAL;
+	form_factor_init();
+	zassert_equal_ptr(motion_sensors[BASE_ACCEL].rot_standard_ref,
+			  normal_rotation,
+			  "errors should leave the rotation unchanged");
+
+	cros_cbi_get_fw_config_fake.custom_fake = get_base_orientation_inverted;
+	form_factor_init();
+	zassert_equal_ptr(
+		motion_sensors[BASE_ACCEL].rot_standard_ref, inverted_rotation,
+		"inverted orientation should use the inverted rotation matrix");
+}
+
+ZTEST(nivviks, test_keyboard_configuration)
+{
+	extern const struct ec_response_keybd_config nivviks_kb;
+
+	zassert_equal_ptr(board_vivaldi_keybd_config(), &nivviks_kb);
+}
+
+ZTEST(nivviks, test_led_pwm)
+{
+	led_set_color_battery(EC_LED_COLOR_BLUE);
+	zassert_equal(set_pwm_led_color_fake.arg0_val, PWM_LED0);
+	zassert_equal(set_pwm_led_color_fake.arg1_val, EC_LED_COLOR_BLUE);
+
+	led_set_color_battery(EC_LED_COLOR_AMBER);
+	zassert_equal(set_pwm_led_color_fake.arg0_val, PWM_LED0);
+	zassert_equal(set_pwm_led_color_fake.arg1_val, EC_LED_COLOR_AMBER);
+
+	led_set_color_battery(EC_LED_COLOR_GREEN);
+	zassert_equal(set_pwm_led_color_fake.arg0_val, PWM_LED0);
+	zassert_equal(set_pwm_led_color_fake.arg1_val, -1);
+}
diff --git a/zephyr/test/nissa/src/nivviks_charger.c b/zephyr/test/nissa/src/nivviks_charger.c
new file mode 100644
index 0000000000..7324a87da1
--- /dev/null
+++ b/zephyr/test/nissa/src/nivviks_charger.c
@@ -0,0 +1,335 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/charger/isl923x_public.h"
+#include "driver/tcpm/raa489000.h"
+#include "emul/tcpc/emul_tcpci.h"
+#include "extpower.h"
+#include "system.h"
+#include "tcpm/tcpci.h"
+#include "usb_charge.h"
+
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/fff.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/ztest.h>
+
+#include <dt-bindings/gpio_defines.h>
+#include <typec_control.h>
+
+#define TCPC0 EMUL_DT_GET(DT_NODELABEL(tcpci_emul_0))
+#define TCPC1 EMUL_DT_GET(DT_NODELABEL(tcpci_emul_1))
+
+LOG_MODULE_REGISTER(nissa, LOG_LEVEL_INF);
+
+FAKE_VALUE_FUNC(int, raa489000_enable_asgate, int, bool);
+FAKE_VALUE_FUNC(int, raa489000_set_output_current, int, enum tcpc_rp_value);
+FAKE_VOID_FUNC(raa489000_hibernate, int, bool);
+FAKE_VALUE_FUNC(enum ec_error_list, raa489000_is_acok, int, bool *);
+FAKE_VOID_FUNC(extpower_handle_update, int);
+FAKE_VALUE_FUNC(int, charge_manager_get_active_charge_port);
+FAKE_VALUE_FUNC(enum ec_error_list, charger_discharge_on_ac, int);
+FAKE_VALUE_FUNC(int, chipset_in_state, int);
+FAKE_VOID_FUNC(usb_charger_task_set_event_sync, int, uint8_t);
+
+static enum ec_error_list raa489000_is_acok_absent(int charger, bool *acok);
+
+static void test_before(void *fixture)
+{
+	RESET_FAKE(raa489000_enable_asgate);
+	RESET_FAKE(raa489000_set_output_current);
+	RESET_FAKE(raa489000_hibernate);
+	RESET_FAKE(raa489000_is_acok);
+	RESET_FAKE(extpower_handle_update);
+	RESET_FAKE(charge_manager_get_active_charge_port);
+	RESET_FAKE(charger_discharge_on_ac);
+	RESET_FAKE(chipset_in_state);
+
+	raa489000_is_acok_fake.custom_fake = raa489000_is_acok_absent;
+
+	i2c_common_emul_set_write_fail_reg(
+		emul_tcpci_generic_get_i2c_common_data(TCPC0),
+		I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(
+		emul_tcpci_generic_get_i2c_common_data(TCPC1),
+		I2C_COMMON_EMUL_NO_FAIL_REG);
+}
+
+ZTEST_SUITE(nivviks_charger, NULL, NULL, test_before, NULL, NULL);
+
+ZTEST(nivviks_charger, test_charger_hibernate)
+{
+	/* board_hibernate() asks the chargers to hibernate. */
+	board_hibernate();
+
+	zassert_equal(raa489000_hibernate_fake.call_count, 2);
+	zassert_equal(raa489000_hibernate_fake.arg0_history[0],
+		      CHARGER_SECONDARY);
+	zassert_true(raa489000_hibernate_fake.arg1_history[0]);
+	zassert_equal(raa489000_hibernate_fake.arg0_history[1],
+		      CHARGER_PRIMARY);
+	zassert_true(raa489000_hibernate_fake.arg1_history[1]);
+}
+
+static enum ec_error_list raa489000_is_acok_absent(int charger, bool *acok)
+{
+	*acok = false;
+	return EC_SUCCESS;
+}
+
+static enum ec_error_list raa489000_is_acok_present(int charger, bool *acok)
+{
+	*acok = true;
+	return EC_SUCCESS;
+}
+
+static enum ec_error_list raa489000_is_acok_error(int charger, bool *acok)
+{
+	return EC_ERROR_UNIMPLEMENTED;
+}
+
+ZTEST(nivviks_charger, test_check_extpower)
+{
+	/* Ensure initial state is no expower present */
+	board_check_extpower();
+	RESET_FAKE(extpower_handle_update);
+
+	/* Update with no change does nothing. */
+	board_check_extpower();
+	zassert_equal(extpower_handle_update_fake.call_count, 0);
+
+	/* Becoming present updates */
+	raa489000_is_acok_fake.custom_fake = raa489000_is_acok_present;
+	board_check_extpower();
+	zassert_equal(extpower_handle_update_fake.call_count, 1);
+	zassert_equal(extpower_handle_update_fake.arg0_val, 1);
+
+	/* Errors are treated as not plugged in */
+	raa489000_is_acok_fake.custom_fake = raa489000_is_acok_error;
+	board_check_extpower();
+	zassert_equal(extpower_handle_update_fake.call_count, 2);
+	zassert_equal(extpower_handle_update_fake.arg0_val, 0);
+}
+
+ZTEST(nivviks_charger, test_is_sourcing_vbus)
+{
+	tcpci_emul_set_reg(TCPC0, TCPC_REG_POWER_STATUS,
+			   TCPC_REG_POWER_STATUS_SOURCING_VBUS |
+				   TCPC_REG_POWER_STATUS_VBUS_PRES);
+	zassert_true(board_is_sourcing_vbus(0));
+
+	tcpci_emul_set_reg(TCPC1, TCPC_REG_POWER_STATUS,
+			   TCPC_REG_POWER_STATUS_SINKING_VBUS |
+				   TCPC_REG_POWER_STATUS_VBUS_PRES);
+	zassert_false(board_is_sourcing_vbus(1));
+}
+
+ZTEST(nivviks_charger, test_set_active_charge_port_none)
+{
+	uint16_t reg;
+
+	/* Setting CHARGE_PORT_NONE disables sinking on all ports */
+	zassert_ok(board_set_active_charge_port(CHARGE_PORT_NONE));
+	zassert_equal(raa489000_enable_asgate_fake.call_count, 2);
+	zassert_equal(raa489000_enable_asgate_fake.arg0_history[0], 0);
+	zassert_equal(raa489000_enable_asgate_fake.arg1_history[0], false);
+	zassert_equal(raa489000_enable_asgate_fake.arg0_history[1], 1);
+	zassert_equal(raa489000_enable_asgate_fake.arg1_history[1], false);
+	tcpci_emul_get_reg(TCPC0, TCPC_REG_COMMAND, &reg);
+	zassert_equal(reg, TCPC_REG_COMMAND_SNK_CTRL_LOW);
+	tcpci_emul_get_reg(TCPC1, TCPC_REG_COMMAND, &reg);
+	zassert_equal(reg, TCPC_REG_COMMAND_SNK_CTRL_LOW);
+}
+
+ZTEST(nivviks_charger, test_set_active_charge_port_invalid_port)
+{
+	zassert_equal(board_set_active_charge_port(4), EC_ERROR_INVAL,
+		      "port 4 doesn't exist, should return error");
+}
+
+ZTEST(nivviks_charger, test_set_active_charge_port_currently_sourcing)
+{
+	/* Attempting to sink on a port that's sourcing is an error */
+	tcpci_emul_set_reg(TCPC1, TCPC_REG_POWER_STATUS,
+			   TCPC_REG_POWER_STATUS_SOURCING_VBUS);
+	zassert_equal(board_set_active_charge_port(1), EC_ERROR_INVAL);
+}
+
+ZTEST(nivviks_charger, test_set_active_charge_port)
+{
+	uint16_t reg;
+
+	/* We can successfully start sinking on a port */
+	zassert_ok(board_set_active_charge_port(0));
+	zassert_equal(raa489000_enable_asgate_fake.call_count, 2);
+	zassert_equal(charger_discharge_on_ac_fake.call_count, 2);
+
+	/* Requested charging stop initially */
+	zassert_equal(charger_discharge_on_ac_fake.arg0_history[0], 1);
+	/* Sinking on the other port was disabled */
+	tcpci_emul_get_reg(TCPC1, TCPC_REG_COMMAND, &reg);
+	zassert_equal(reg, TCPC_REG_COMMAND_SNK_CTRL_LOW);
+	zassert_equal(raa489000_enable_asgate_fake.arg0_history[0], 1);
+	zassert_equal(raa489000_enable_asgate_fake.arg1_history[0], false);
+	/* Sinking was enabled on the new port */
+	tcpci_emul_get_reg(TCPC0, TCPC_REG_COMMAND, &reg);
+	zassert_equal(reg, TCPC_REG_COMMAND_SNK_CTRL_HIGH);
+	zassert_equal(raa489000_enable_asgate_fake.arg0_history[1], 0);
+	zassert_equal(raa489000_enable_asgate_fake.arg1_history[1], true);
+	/* Resumed charging */
+	zassert_equal(charger_discharge_on_ac_fake.arg0_history[1], 0);
+}
+
+ZTEST(nivviks_charger, test_set_active_charge_port_enable_fail)
+{
+	i2c_common_emul_set_write_fail_reg(
+		emul_tcpci_generic_get_i2c_common_data(TCPC0),
+		TCPC_REG_COMMAND);
+	zassert_equal(board_set_active_charge_port(0), EC_ERROR_UNKNOWN);
+
+	/* Charging was enabled again after the error */
+	zassert_equal(charger_discharge_on_ac_fake.arg0_val, 0);
+}
+
+ZTEST(nivviks_charger, test_set_active_charge_port_disable_fail)
+{
+	/* Failing to disable sinking on the other port isn't fatal */
+	i2c_common_emul_set_write_fail_reg(
+		emul_tcpci_generic_get_i2c_common_data(TCPC1),
+		TCPC_REG_COMMAND);
+	zassert_ok(board_set_active_charge_port(0));
+}
+
+ZTEST(nivviks_charger, test_tcpc_get_alert_status)
+{
+	const struct gpio_dt_spec *c0_int =
+		GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl);
+	const struct gpio_dt_spec *c1_int =
+		GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl);
+
+	/* Sub-board IO configuration is handled by other inits */
+	gpio_pin_configure_dt(c1_int, GPIO_INPUT_PULL_UP);
+
+	/* Both IRQs are asserted */
+	gpio_emul_input_set(c0_int->port, c0_int->pin, 0);
+	gpio_emul_input_set(c1_int->port, c1_int->pin, 0);
+
+	tcpci_emul_set_reg(TCPC0, TCPC_REG_ALERT, 1);
+	zassert_equal(tcpc_get_alert_status(), PD_STATUS_TCPC_ALERT_0);
+
+	/* Bit 14 is ignored */
+	tcpci_emul_set_reg(TCPC0, TCPC_REG_ALERT, 0x4000);
+	zassert_equal(tcpc_get_alert_status(), 0);
+
+	/* Port 1 works too */
+	tcpci_emul_set_reg(TCPC1, TCPC_REG_ALERT, 0x8000);
+	zassert_equal(tcpc_get_alert_status(), PD_STATUS_TCPC_ALERT_1);
+}
+
+ZTEST(nivviks_charger, test_pd_power_supply_reset)
+{
+	uint16_t reg;
+
+	/* Stops any active sourcing on the given port */
+	pd_power_supply_reset(0);
+	tcpci_emul_get_reg(TCPC0, TCPC_REG_COMMAND, &reg);
+	zassert_equal(reg, TCPC_REG_COMMAND_SRC_CTRL_LOW);
+}
+
+ZTEST(nivviks_charger, test_set_source_current_limit)
+{
+	/* Args pass through raa489000_set_output_current() */
+	typec_set_source_current_limit(0, TYPEC_RP_3A0);
+	zassert_equal(raa489000_set_output_current_fake.call_count, 1);
+	zassert_equal(raa489000_set_output_current_fake.arg0_val, 0);
+	zassert_equal(raa489000_set_output_current_fake.arg1_val, TYPEC_RP_3A0);
+
+	/* A port that doesn't exist does nothing */
+	typec_set_source_current_limit(3, TYPEC_RP_USB);
+	zassert_equal(raa489000_set_output_current_fake.call_count, 1);
+}
+
+static int chipset_in_state_break_tcpc_command(int state_mask)
+{
+	i2c_common_emul_set_write_fail_reg(
+		emul_tcpci_generic_get_i2c_common_data(TCPC0),
+		TCPC_REG_COMMAND);
+	return 0;
+}
+
+ZTEST(nivviks_charger, test_pd_set_power_supply_ready)
+{
+	uint16_t reg;
+
+	/* Initially sinking VBUS so we can see that gets disabled */
+	tcpci_emul_set_reg(TCPC0, TCPC_REG_POWER_STATUS,
+			   TCPC_REG_POWER_STATUS_SINKING_VBUS);
+
+	zassert_ok(pd_set_power_supply_ready(0));
+	tcpci_emul_get_reg(TCPC0, TCPC_REG_POWER_STATUS, &reg);
+	zassert_equal(reg, TCPC_REG_POWER_STATUS_SOURCING_VBUS);
+	zassert_equal(raa489000_enable_asgate_fake.call_count, 1);
+	zassert_equal(raa489000_enable_asgate_fake.arg0_val, 0);
+	zassert_equal(raa489000_enable_asgate_fake.arg1_val, true);
+
+	/* Assorted errors are propagated: enable_asgate() fails */
+	raa489000_enable_asgate_fake.return_val = EC_ERROR_UNIMPLEMENTED;
+	zassert_not_equal(pd_set_power_supply_ready(0), EC_SUCCESS);
+
+	/* Write to enable VBUS fails */
+	chipset_in_state_fake.custom_fake = chipset_in_state_break_tcpc_command;
+	zassert_not_equal(pd_set_power_supply_ready(0), EC_SUCCESS);
+	chipset_in_state_fake.custom_fake = NULL;
+
+	/* Write to disable sinking fails */
+	i2c_common_emul_set_write_fail_reg(
+		emul_tcpci_generic_get_i2c_common_data(TCPC0),
+		TCPC_REG_COMMAND);
+	zassert_not_equal(pd_set_power_supply_ready(0), EC_SUCCESS);
+	i2c_common_emul_set_write_fail_reg(
+		emul_tcpci_generic_get_i2c_common_data(TCPC0),
+		I2C_COMMON_EMUL_NO_FAIL_REG);
+
+	/* AP is off */
+	chipset_in_state_fake.return_val = 1;
+	zassert_equal(pd_set_power_supply_ready(0), EC_ERROR_NOT_POWERED);
+
+	/* Invalid port number requested */
+	zassert_equal(pd_set_power_supply_ready(2), EC_ERROR_INVAL);
+}
+
+ZTEST(nivviks_charger, test_reset_pd_mcu)
+{
+	/* Doesn't do anything */
+	board_reset_pd_mcu();
+}
+
+ZTEST(nivviks_charger, test_process_pd_alert)
+{
+	const struct gpio_dt_spec *c0_int =
+		GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl);
+	const struct gpio_dt_spec *c1_int =
+		GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl);
+
+	gpio_emul_input_set(c0_int->port, c0_int->pin, 0);
+	board_process_pd_alert(0);
+	/* We ran BC1.2 processing inline */
+	zassert_equal(usb_charger_task_set_event_sync_fake.call_count, 1);
+	zassert_equal(usb_charger_task_set_event_sync_fake.arg0_val, 0);
+	zassert_equal(usb_charger_task_set_event_sync_fake.arg1_val,
+		      USB_CHG_EVENT_BC12);
+	/*
+	 * This should also call schedule_deferred_pd_interrupt() again, but
+	 * there's no good way to verify that.
+	 */
+
+	/* Port 1 also works */
+	gpio_emul_input_set(c1_int->port, c1_int->pin, 0);
+	board_process_pd_alert(1);
+	zassert_equal(usb_charger_task_set_event_sync_fake.call_count, 2);
+	zassert_equal(usb_charger_task_set_event_sync_fake.arg0_val, 1);
+	zassert_equal(usb_charger_task_set_event_sync_fake.arg1_val,
+		      USB_CHG_EVENT_BC12);
+}
diff --git a/zephyr/test/nissa/src/stubs.c b/zephyr/test/nissa/src/stubs.c
new file mode 100644
index 0000000000..0e45fefc17
--- /dev/null
+++ b/zephyr/test/nissa/src/stubs.c
@@ -0,0 +1,34 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Function stubs needed for building Nissa board code, but that aren't
+ * meaningful to testing.
+ */
+
+#include "common.h"
+
+#include <zephyr/fff.h>
+
+__overridable void pd_power_supply_reset(int port)
+{
+}
+
+__overridable int pd_set_power_supply_ready(int port)
+{
+	return 0;
+}
+
+__overridable void pd_set_input_current_limit(int port, uint32_t max_ma,
+					      uint32_t supply_voltage)
+{
+}
+
+__overridable int pd_check_vconn_swap(int port)
+{
+	return 0;
+}
+
+__overridable void usb_interrupt_c0(enum gpio_signal signal)
+{
+}
diff --git a/zephyr/test/nissa/src/sub_board.c b/zephyr/test/nissa/src/sub_board.c
new file mode 100644
index 0000000000..78b5b19143
--- /dev/null
+++ b/zephyr/test/nissa/src/sub_board.c
@@ -0,0 +1,245 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Unit tests for program/nissa/src/sub_board.c.
+ */
+#include "cros_cbi.h"
+#include "hooks.h"
+#include "nissa_hdmi.h"
+#include "nissa_sub_board.h"
+#include "usb_pd.h"
+
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/fff.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+#include <ap_power/ap_power.h>
+#include <ap_power/ap_power_events.h>
+
+FAKE_VALUE_FUNC(int, cros_cbi_get_fw_config, enum cbi_fw_config_field_id,
+		uint32_t *);
+FAKE_VOID_FUNC(usb_interrupt_c1, enum gpio_signal);
+
+/*
+ * Private bits of board code that are visible for testing.
+ *
+ * The cached sub-board ID needs to be cleared by tests so we can run multiple
+ * tests per process, and usb_pd_count_init() needs to run following each update
+ * of reported sub-board.
+ */
+extern enum nissa_sub_board_type nissa_cached_sub_board;
+void board_usb_pd_count_init(void);
+
+/* Shim GPIO initialization from devicetree. */
+int init_gpios(const struct device *unused);
+
+static uint32_t fw_config_value;
+
+/** Set the value of the CBI fw_config field returned by the fake. */
+static void set_fw_config_value(uint32_t value)
+{
+	fw_config_value = value;
+	board_usb_pd_count_init();
+}
+
+/** Custom fake for cros_cgi_get_fw_config(). */
+static int get_fake_fw_config_field(enum cbi_fw_config_field_id field_id,
+				    uint32_t *value)
+{
+	*value = fw_config_value;
+	return 0;
+}
+
+#define ASSERT_GPIO_FLAGS(spec, expected)                                  \
+	do {                                                               \
+		gpio_flags_t flags;                                        \
+		zassert_ok(gpio_emul_flags_get((spec)->port, (spec)->pin,  \
+					       &flags));                   \
+		zassert_equal(flags, expected,                             \
+			      "actual value was %#x; expected %#x", flags, \
+			      expected);                                   \
+	} while (0)
+
+static int get_gpio_output(const struct gpio_dt_spec *const spec)
+{
+	return gpio_emul_output_get(spec->port, spec->pin);
+}
+
+struct nissa_sub_board_fixture {
+	const struct gpio_dt_spec *sb_1;
+	const struct gpio_dt_spec *sb_2;
+	const struct gpio_dt_spec *sb_3;
+	const struct gpio_dt_spec *sb_4;
+};
+
+static void *suite_setup_fn()
+{
+	struct nissa_sub_board_fixture *fixture =
+		k_malloc(sizeof(struct nissa_sub_board_fixture));
+
+	zassume_not_null(fixture);
+	fixture->sb_1 = GPIO_DT_FROM_NODELABEL(gpio_sb_1);
+	fixture->sb_2 = GPIO_DT_FROM_NODELABEL(gpio_sb_2);
+	fixture->sb_3 = GPIO_DT_FROM_NODELABEL(gpio_sb_3);
+	fixture->sb_4 = GPIO_DT_FROM_NODELABEL(gpio_sb_4);
+
+	return fixture;
+}
+
+static void test_before_fn(void *fixture_)
+{
+	struct nissa_sub_board_fixture *fixture = fixture_;
+
+	/* Reset cached global state. */
+	nissa_cached_sub_board = NISSA_SB_UNKNOWN;
+	fw_config_value = -1;
+
+	/* Return the fake fw_config value. */
+	RESET_FAKE(cros_cbi_get_fw_config);
+	cros_cbi_get_fw_config_fake.custom_fake = get_fake_fw_config_field;
+
+	/* Unconfigure sub-board GPIOs. */
+	gpio_pin_configure_dt(fixture->sb_1, GPIO_DISCONNECTED);
+	gpio_pin_configure_dt(fixture->sb_2, GPIO_DISCONNECTED);
+	gpio_pin_configure_dt(fixture->sb_3, GPIO_DISCONNECTED);
+	gpio_pin_configure_dt(fixture->sb_4, GPIO_DISCONNECTED);
+	/* Reset C1 interrupt to deasserted. */
+	gpio_emul_input_set(fixture->sb_1->port, fixture->sb_1->pin, 1);
+
+	RESET_FAKE(usb_interrupt_c1);
+}
+
+ZTEST_SUITE(nissa_sub_board, NULL, suite_setup_fn, test_before_fn, NULL, NULL);
+
+ZTEST_F(nissa_sub_board, test_usb_c_a)
+{
+	/* Set the sub-board, reported configuration is correct. */
+	set_fw_config_value(FW_SUB_BOARD_1);
+	zassert_equal(nissa_get_sb_type(), NISSA_SB_C_A);
+	zassert_equal(board_get_usb_pd_port_count(), 2);
+
+	/* Should have fetched CBI exactly once, asking for the sub-board. */
+	zassert_equal(cros_cbi_get_fw_config_fake.call_count, 1);
+	zassert_equal(cros_cbi_get_fw_config_fake.arg0_history[0],
+		      FW_SUB_BOARD);
+
+	/* Run IO configuration in init. */
+	init_gpios(NULL);
+	hook_notify(HOOK_INIT);
+
+	/* Check that the sub-board GPIOs are configured correctly. */
+	ASSERT_GPIO_FLAGS(fixture->sb_2 /* A1 VBUS enable */, GPIO_OUTPUT);
+	ASSERT_GPIO_FLAGS(fixture->sb_1 /* C1 interrupt */,
+			  GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_EDGE_FALLING);
+
+	/* USB-C1 interrupt is handled. */
+	RESET_FAKE(usb_interrupt_c1);
+	gpio_emul_input_set(fixture->sb_1->port, fixture->sb_1->pin, 0);
+	zassert_equal(usb_interrupt_c1_fake.call_count, 1,
+		      "usb_interrupt was called %d times",
+		      usb_interrupt_c1_fake.call_count);
+}
+
+ZTEST_F(nissa_sub_board, test_usb_c_lte)
+{
+	set_fw_config_value(FW_SUB_BOARD_2);
+	zassert_equal(nissa_get_sb_type(), NISSA_SB_C_LTE);
+	zassert_equal(board_get_usb_pd_port_count(), 2);
+
+	init_gpios(NULL);
+	hook_notify(HOOK_INIT);
+
+	/* GPIOs are configured as expected. */
+	ASSERT_GPIO_FLAGS(fixture->sb_2 /* Standby power enable */,
+			  GPIO_OUTPUT | GPIO_OUTPUT_INIT_LOW);
+	ASSERT_GPIO_FLAGS(fixture->sb_1 /* C1 interrupt */,
+			  GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_EDGE_FALLING);
+
+	/* USB interrupt is handled. */
+	RESET_FAKE(usb_interrupt_c1);
+	gpio_emul_input_set(fixture->sb_1->port, fixture->sb_1->pin, 0);
+	zassert_equal(usb_interrupt_c1_fake.call_count, 1,
+		      "usb_interrupt was called %d times",
+		      usb_interrupt_c1_fake.call_count);
+
+	/* LTE power gets enabled on S5. */
+	ap_power_ev_send_callbacks(AP_POWER_PRE_INIT);
+	zassert_equal(get_gpio_output(fixture->sb_2), 1);
+	/* And disabled on G3. */
+	ap_power_ev_send_callbacks(AP_POWER_HARD_OFF);
+	zassert_equal(get_gpio_output(fixture->sb_2), 0);
+}
+
+ZTEST_F(nissa_sub_board, test_usb_a_hdmi)
+{
+	set_fw_config_value(FW_SUB_BOARD_3);
+	zassert_equal(nissa_get_sb_type(), NISSA_SB_HDMI_A);
+	zassert_equal(board_get_usb_pd_port_count(), 1);
+
+	init_gpios(NULL);
+	hook_notify(HOOK_INIT);
+
+	/* USB-A controls are enabled. */
+	ASSERT_GPIO_FLAGS(fixture->sb_2 /* A1 VBUS enable */, GPIO_OUTPUT);
+
+	/*
+	 * HDMI IOs configured as expected. The HDMI power enable and DDC select
+	 * pins are impossible to test because emulated GPIOs don't support
+	 * open-drain mode, so this only checks HPD.
+	 */
+	ASSERT_GPIO_FLAGS(fixture->sb_4,
+			  GPIO_INPUT | GPIO_ACTIVE_LOW | GPIO_INT_EDGE_BOTH);
+
+	/* Power events adjust HDMI port power as expected. */
+	ap_power_ev_send_callbacks(AP_POWER_PRE_INIT);
+	zassert_equal(get_gpio_output(GPIO_DT_FROM_NODELABEL(gpio_hdmi_sel)),
+		      1);
+	ap_power_ev_send_callbacks(AP_POWER_STARTUP);
+	ap_power_ev_send_callbacks(AP_POWER_SHUTDOWN);
+	ap_power_ev_send_callbacks(AP_POWER_HARD_OFF);
+	zassert_equal(get_gpio_output(GPIO_DT_FROM_NODELABEL(gpio_hdmi_sel)),
+		      0);
+
+	/* HPD input gets copied through to the output, and inverted. */
+	gpio_emul_input_set(fixture->sb_4->port, fixture->sb_4->pin, 1);
+	zassert_equal(
+		get_gpio_output(GPIO_DT_FROM_NODELABEL(gpio_ec_soc_hdmi_hpd)),
+		0);
+	gpio_emul_input_set(fixture->sb_4->port, fixture->sb_4->pin, 0);
+	zassert_equal(
+		get_gpio_output(GPIO_DT_FROM_NODELABEL(gpio_ec_soc_hdmi_hpd)),
+		1);
+}
+
+ZTEST(nissa_sub_board, test_unset_board)
+{
+	/* fw_config with an unset sub-board means none is present. */
+	set_fw_config_value(0);
+	zassert_equal(nissa_get_sb_type(), NISSA_SB_NONE);
+	zassert_equal(board_get_usb_pd_port_count(), 1);
+}
+
+static int get_fw_config_error(enum cbi_fw_config_field_id field,
+			       uint32_t *value)
+{
+	return EC_ERROR_UNKNOWN;
+}
+
+ZTEST(nissa_sub_board, test_cbi_error)
+{
+	/*
+	 * Reading fw_config from CBI returns an error, so sub-board is treated
+	 * as absent.
+	 */
+	cros_cbi_get_fw_config_fake.custom_fake = get_fw_config_error;
+	zassert_equal(nissa_get_sb_type(), NISSA_SB_NONE);
+}
+
+/** Override default HDMI configuration to exercise the power enable as well. */
+__override void nissa_configure_hdmi_power_gpios(void)
+{
+	nissa_configure_hdmi_rails();
+	nissa_configure_hdmi_vcc();
+}
diff --git a/zephyr/test/nissa/testcase.yaml b/zephyr/test/nissa/testcase.yaml
new file mode 100644
index 0000000000..f2818b7e75
--- /dev/null
+++ b/zephyr/test/nissa/testcase.yaml
@@ -0,0 +1,48 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+common:
+  platform_allow: native_posix
+tests:
+  nissa.sub_board:
+    extra_dtc_overlay_files:
+    - "boards/generic_npcx.dts"
+    extra_configs:
+    - CONFIG_TEST_NISSA_SUB_BOARD=y
+  nissa.common:
+    extra_dtc_overlay_files:
+    - "boards/generic_npcx.dts"
+    - "boards/chargers.dts"
+    extra_conf_files:
+    - "prj.conf"
+    - "charger.conf"
+    extra_configs:
+    - CONFIG_TEST_NISSA_COMMON=y
+  nissa.nivviks:
+    extra_dtc_overlay_files:
+    - "boards/generic_npcx.dts"
+    - "boards/chargers.dts"
+    - "boards/nivviks.dts"
+    extra_conf_files:
+    - "prj.conf"
+    - "charger.conf"
+    extra_configs:
+    - CONFIG_TEST_NISSA_NIVVIKS=y
+    - CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSO=y
+    - CONFIG_PLATFORM_EC_ACCEL_LIS2DW12=y
+  nissa.nivviks.charger:
+    extra_dtc_overlay_files:
+    - "boards/generic_npcx.dts"
+    - "boards/battery.dts"
+    extra_conf_files:
+    - "prj.conf"
+    extra_configs:
+    - CONFIG_TEST_NISSA_NIVVIKS_CHARGER=y
+    - CONFIG_PLATFORM_EC_TCPC_INTERRUPT=n
+  nissa.nereid:
+    extra_configs:
+    - CONFIG_TEST_NISSA_NEREID=y
+    - CONFIG_PLATFORM_EC_TCPC_INTERRUPT=n
+    extra_dtc_overlay_files:
+    - "boards/nereid.dts"
diff --git a/zephyr/test/ocpc/CMakeLists.txt b/zephyr/test/ocpc/CMakeLists.txt
new file mode 100644
index 0000000000..2a46e14245
--- /dev/null
+++ b/zephyr/test/ocpc/CMakeLists.txt
@@ -0,0 +1,14 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(ocpc)
+
+# Include FFF fakes
+add_subdirectory(${PLATFORM_EC}/zephyr/test/test_utils test_utils)
+
+target_sources(app PRIVATE src/fakes.c)
+target_sources(app PRIVATE src/main.c)
+target_sources(app PRIVATE src/ocpc.c)
diff --git a/zephyr/test/ocpc/boards/native_posix.overlay b/zephyr/test/ocpc/boards/native_posix.overlay
new file mode 100644
index 0000000000..d581c38af1
--- /dev/null
+++ b/zephyr/test/ocpc/boards/native_posix.overlay
@@ -0,0 +1,171 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <board-overlays/native_posix.dts>
+#include <npcx_emul.dts>
+#include <dt-bindings/usb_pd_tcpm.h>
+#include <dt-bindings/usbc_mux.h>
+
+/ {
+	batteries {
+		default_battery: lgc {
+			compatible = "lgc,ac17a8m", "battery-smart";
+		};
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 {
+			i2c-port = <&i2c_ctrl3>;
+			enum-names = "I2C_PORT_USB_C0_TCPC";
+		};
+		i2c_ec_i2c_sub_usb_c1: ec_i2c_sub_usb_c1 {
+			i2c-port = <&i2c_ctrl5>;
+			enum-names = "I2C_PORT_USB_C1_TCPC";
+		};
+		i2c_ec_i2c_batt: ec_i2c_batt {
+			i2c-port = <&i2c_ctrl7>;
+			enum-names = "I2C_PORT_BATTERY", "I2C_PORT_VIRTUAL_BATTERY";
+		};
+	};
+
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		vbus {
+			enum-name = "ADC_VBUS";
+			io-channels = <&adc0 1>;
+			/* Measure VBUS through a 1/10 voltage divider */
+			mul = <10>;
+		};
+	};
+
+	aliases {
+		gpio-wp = &gpio_wp;
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		gpio_wp: ec-flash-wp-odl {
+			gpios = <&gpio0 0 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_ec_edp_bl_en_od: ec_edp_bl_en_od {
+			gpios = <&gpio0 1 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_ENABLE_BACKLIGHT";
+		};
+		gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl {
+			gpios = <&gpio0 2 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		gpio_lid_open: lid_open {
+			gpios = <&gpio0 3 GPIO_INPUT>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+
+	};
+
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_power_button: power_button {
+			irq-pin = <&gpio_gsc_ec_pwr_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_button_interrupt";
+		};
+	};
+
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+			chg = <&isl923x_emul_0>;
+			tcpc = <&tcpci_emul_0>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_0>;
+			};
+		};
+		port0-muxes {
+			virtual_mux_0: virtual-mux-0 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+		port1@1 {
+			compatible = "named-usbc-port";
+			reg = <1>;
+			chg = <&isl923x_emul_1>;
+			tcpc = <&tcpci_emul_1>;
+			usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_1>;
+			};
+			usb_mux_chain_1_no_mux: usb-mux-chain-1-no-mux {
+				compatible = "cros-ec,usb-mux-chain";
+				alternative-chain;
+				usb-muxes = <&virtual_mux_1>;
+			};
+		};
+		port1-muxes {
+			virtual_mux_1: virtual-mux-1 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+	};
+
+	adc0: adc {
+		compatible = "zephyr,adc-emul";
+		nchannels = <6>;
+		ref-internal-mv = <3300>;
+		#io-channel-cells = <1>;
+		status = "okay";
+	};
+};
+
+&i2c_ctrl7 {
+	battery: sb@b {
+		compatible = "zephyr,smart-battery-emul";
+		reg = <0xb>;
+		cycle-count = <99>;
+		version = "BATTERY_SPEC_VER_1_1_WITH_PEC";
+		/* Real battery voltages are multiples of 4.4V. */
+		desired-charg-volt = <5000>;
+		desired-charg-cur = <1000>;
+		mf-name = "LGC";
+		dev-name = "AC17A8M";
+	};
+};
+
+&i2c_ctrl3 {
+	tcpci_emul_0: tcpci_emul@82 {
+		compatible = "renesas,raa489000", "cros,i2c-mock";
+		status = "okay";
+		reg = <0x82>;
+	};
+	isl923x_emul_0: isl923x@9 {
+		compatible = "cros,isl923x-emul";
+		status = "okay";
+		reg = <0x9>;
+		battery = <&battery>;
+	};
+};
+
+&i2c_ctrl5 {
+	tcpci_emul_1: tcpci_emul@82 {
+		compatible = "renesas,raa489000", "cros,i2c-mock";
+		status = "okay";
+		reg = <0x82>;
+	};
+	isl923x_emul_1: isl923x@9 {
+		compatible = "cros,isl923x-emul";
+		status = "okay";
+		reg = <0x9>;
+		battery = <&battery>;
+	};
+};
\ No newline at end of file
diff --git a/zephyr/test/ocpc/prj.conf b/zephyr/test/ocpc/prj.conf
new file mode 100644
index 0000000000..adfb4b5fae
--- /dev/null
+++ b/zephyr/test/ocpc/prj.conf
@@ -0,0 +1,40 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_ZTEST=y
+CONFIG_ZTEST_NEW_API=y
+
+# Basic EC functions
+CONFIG_SHIMMED_TASKS=y
+CONFIG_CROS_EC=y
+CONFIG_PLATFORM_EC=y
+CONFIG_PLATFORM_EC_HOOKS=y
+CONFIG_PLATFORM_EC_HOSTCMD=y
+
+# Unwanted features
+CONFIG_PLATFORM_EC_VBOOT_HASH=n
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
+CONFIG_PLATFORM_EC_USBC_PPC=n
+CONFIG_PLATFORM_EC_USB_CHARGER=n
+
+# Power and charger-related
+CONFIG_PLATFORM_EC_POWER_BUTTON=y
+CONFIG_PLATFORM_EC_CHARGER=y
+CONFIG_PLATFORM_EC_OCPC=y
+CONFIG_PLATFORM_EC_OCPC_DEF_RBATT_MOHMS=22
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=10
+CONFIG_PLATFORM_EC_USB_PD_DISCHARGE=n
+CONFIG_PLATFORM_EC_USB_PD_5V_EN_CUSTOM=y
+CONFIG_PLATFORM_EC_OCPC_DEF_DRIVELIMIT_MILLIVOLTS=200
+CONFIG_PLATFORM_EC_I2C_VIRTUAL_BATTERY=y
+CONFIG_PLATFORM_EC_CHARGER_RAA489000=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_RAA489000=y
+CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y
+
+# Console
+CONFIG_SHELL_BACKEND_DUMMY=y
+CONFIG_SHELL_BACKEND_SERIAL=n
+CONFIG_SERIAL=y
+CONFIG_RING_BUFFER=y
diff --git a/zephyr/test/ocpc/src/fakes.c b/zephyr/test/ocpc/src/fakes.c
new file mode 100644
index 0000000000..0ff17ecddc
--- /dev/null
+++ b/zephyr/test/ocpc/src/fakes.c
@@ -0,0 +1,43 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+int battery_is_present(void)
+{
+	return 1;
+}
+
+int board_set_active_charge_port(int port)
+{
+	return 0;
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	return 0;
+}
+
+void pd_power_supply_reset(int port)
+{
+}
+
+int board_is_sourcing_vbus(int port)
+{
+	return 0;
+}
+
+int pd_check_vconn_swap(int port)
+{
+	return 0;
+}
+
+int extpower_is_present(void)
+{
+	return 0;
+}
+
+int lid_is_open(void)
+{
+	return 0;
+}
diff --git a/zephyr/test/ocpc/src/main.c b/zephyr/test/ocpc/src/main.c
new file mode 100644
index 0000000000..5fa0a3b080
--- /dev/null
+++ b/zephyr/test/ocpc/src/main.c
@@ -0,0 +1,23 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_app_main.h"
+#include "hooks.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+void test_main(void)
+{
+	ec_app_main();
+
+	k_sleep(K_MSEC(1000));
+
+	/* Run all the suites that depend on main being called */
+	ztest_run_test_suites(NULL);
+
+	/* Check that every suite ran */
+	ztest_verify_all_test_suites_ran();
+}
diff --git a/zephyr/test/ocpc/src/ocpc.c b/zephyr/test/ocpc/src/ocpc.c
new file mode 100644
index 0000000000..5d0da0c117
--- /dev/null
+++ b/zephyr/test/ocpc/src/ocpc.c
@@ -0,0 +1,383 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "charge_state.h"
+#include "console.h"
+#include "host_command.h"
+#include "ocpc.h"
+
+#include <string.h>
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/fff.h>
+#include <zephyr/shell/shell_dummy.h>
+#include <zephyr/ztest.h>
+
+FAKE_VOID_FUNC(ocpc_get_pid_constants, int *, int *, int *, int *, int *,
+	       int *);
+
+static int test_kp, test_kp_div, test_ki, test_ki_div, test_kd, test_kd_div;
+
+static void get_pid_constants_custom_fake(int *kp, int *kp_div, int *ki,
+					  int *ki_div, int *kd, int *kd_div)
+{
+	*kp = test_kp;
+	*kp_div = test_kp_div;
+	*ki = test_ki;
+	*ki_div = test_ki_div;
+	*kd = test_kd;
+	*kd_div = test_kd_div;
+}
+
+ZTEST_USER(ocpc, test_consolecmd_ocpcpid__read)
+{
+	const char *outbuffer;
+	size_t buffer_size;
+
+	/* With no args, print current state */
+	shell_backend_dummy_clear_output(get_ec_shell());
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "ocpcpid"));
+	outbuffer =
+		shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+
+	/* Check for some expected lines */
+	zassert_true(buffer_size > 0);
+	zassert_ok(!strstr(outbuffer, "Kp = 1 / 4"), "Output was: `%s`",
+		   outbuffer);
+	zassert_ok(!strstr(outbuffer, "Ki = 1 / 15"), "Output was: `%s`",
+		   outbuffer);
+	zassert_ok(!strstr(outbuffer, "Kd = 1 / 10"), "Output was: `%s`",
+		   outbuffer);
+}
+
+ZTEST_USER(ocpc, test_consolecmd_ocpcpid__write)
+{
+	const char *outbuffer;
+	size_t buffer_size;
+
+	/* Call a few times to change each parameter and examine output of final
+	 * command.
+	 */
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "ocpcpid p 2 3"));
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "ocpcpid i 4 5"));
+	shell_backend_dummy_clear_output(get_ec_shell());
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "ocpcpid d 6 7"));
+	outbuffer =
+		shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+
+	zassert_true(buffer_size > 0);
+	zassert_ok(!strstr(outbuffer, "Kp = 2 / 3"), "Output was: `%s`",
+		   outbuffer);
+	zassert_ok(!strstr(outbuffer, "Ki = 4 / 5"), "Output was: `%s`",
+		   outbuffer);
+	zassert_ok(!strstr(outbuffer, "Kd = 6 / 7"), "Output was: `%s`",
+		   outbuffer);
+}
+
+ZTEST_USER(ocpc, test_consolecmd_ocpcpid__bad_param)
+{
+	zassert_equal(EC_ERROR_PARAM1,
+		      shell_execute_cmd(get_ec_shell(), "ocpcpid y 0 0"));
+}
+
+ZTEST_USER(ocpc, test_consolecmd_ocpcdrvlmt)
+{
+	const char *outbuffer;
+	size_t buffer_size;
+
+	/* Set to 100mV */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "ocpcdrvlmt 100"));
+
+	/* Read back and verify */
+	shell_backend_dummy_clear_output(get_ec_shell());
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "ocpcdrvlmt"));
+	outbuffer =
+		shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+
+	zassert_true(buffer_size > 0);
+	zassert_ok(!strstr(outbuffer, "Drive Limit = 100"), "Output was: `%s`",
+		   outbuffer);
+}
+
+ZTEST_USER(ocpc, test_consolecmd_ocpcdebug)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "ocpcdebug ena"));
+	zassert_true(test_ocpc_get_debug_output());
+	zassert_false(test_ocpc_get_viz_output());
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "ocpcdebug dis"));
+	zassert_false(test_ocpc_get_debug_output());
+	zassert_false(test_ocpc_get_viz_output());
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "ocpcdebug viz"));
+	zassert_false(test_ocpc_get_debug_output());
+	zassert_true(test_ocpc_get_viz_output());
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "ocpcdebug all"));
+	zassert_true(test_ocpc_get_debug_output());
+	zassert_true(test_ocpc_get_viz_output());
+
+	/* Bad param */
+	zassert_equal(EC_ERROR_PARAM1,
+		      shell_execute_cmd(get_ec_shell(), "ocpcdebug foo"));
+
+	/* Missing param */
+	zassert_equal(EC_ERROR_PARAM_COUNT,
+		      shell_execute_cmd(get_ec_shell(), "ocpcdebug"));
+}
+
+ZTEST(ocpc, test_ocpc_config_secondary_charger__with_primary_charger)
+{
+	/* Should immediately return if a non-secondary charger is active,
+	 * which is the default.
+	 */
+
+	charge_set_active_chg_chip(CHARGER_PRIMARY);
+
+	zassert_equal(EC_ERROR_INVAL,
+		      ocpc_config_secondary_charger(NULL, NULL, 0, 0));
+}
+
+ZTEST(ocpc, test_ocpc_config_secondary_charger__zero_desired_batt_curr)
+{
+	int expected_vsys_voltage = battery_get_info()->voltage_min;
+	int desired_vsys_voltage = expected_vsys_voltage - 1;
+	struct ocpc_data test_ocpc = {
+		.last_vsys = expected_vsys_voltage - 10,
+	};
+
+	charge_set_active_chg_chip(CHARGER_SECONDARY);
+
+	zassert_equal(EC_SUCCESS,
+		      ocpc_config_secondary_charger(NULL, &test_ocpc,
+						    desired_vsys_voltage, 0));
+
+	/* Vsys should have been clamped to voltage_min */
+	zassert_equal(test_ocpc.last_vsys, expected_vsys_voltage);
+}
+
+FAKE_VALUE_FUNC(int, battery_is_charge_fet_disabled);
+
+ZTEST(ocpc, test_ocpc_config_secondary_charger__fet_disabled)
+{
+	charge_set_active_chg_chip(CHARGER_SECONDARY);
+
+	/* A disabled FET should cause the function to abort */
+	battery_is_charge_fet_disabled_fake.return_val = true;
+
+	/* Use an arbitrary non-zero desired_batt_current_ma */
+	zassert_equal(EC_ERROR_INVALID_CONFIG,
+		      ocpc_config_secondary_charger(NULL, NULL, 0, 1000));
+
+	/* Try again and we should hit the rate limiter */
+	battery_is_charge_fet_disabled_fake.return_val = false;
+
+	zassert_equal(EC_ERROR_BUSY,
+		      ocpc_config_secondary_charger(NULL, NULL, 0, 1000));
+
+	/* Allow the block to expire */
+	k_sleep(K_SECONDS(6));
+}
+
+FAKE_VALUE_FUNC(enum ec_error_list, charger_set_vsys_compensation, int,
+		struct ocpc_data *, int, int);
+
+ZTEST(ocpc, test_ocpc_config_secondary_charger__happy)
+{
+	int desired_batt_voltage_mv = 123;
+	int desired_batt_current_ma = 456;
+
+	charge_set_active_chg_chip(CHARGER_SECONDARY);
+
+	charger_set_vsys_compensation_fake.return_val = EC_SUCCESS;
+
+	/* charger_set_vsys_compensation() will succeed and we will be
+	 * done. Again use an arbitrary non-zero desired_current.
+	 */
+	zassert_equal(EC_SUCCESS, ocpc_config_secondary_charger(
+					  NULL, NULL, desired_batt_voltage_mv,
+					  desired_batt_current_ma));
+
+	zassert_equal(1, charger_set_vsys_compensation_fake.call_count);
+	zassert_equal(desired_batt_current_ma,
+		      charger_set_vsys_compensation_fake.arg2_history[0]);
+	zassert_equal(desired_batt_voltage_mv,
+		      charger_set_vsys_compensation_fake.arg3_history[0]);
+}
+
+ZTEST(ocpc, test_ocpc_config_secondary_charger__unknown_return_code)
+{
+	charge_set_active_chg_chip(CHARGER_SECONDARY);
+
+	charger_set_vsys_compensation_fake.return_val = 999;
+
+	/* charger_set_vsys_compensation() will return an unhandled return
+	 * value.
+	 */
+	zassert_equal(999, ocpc_config_secondary_charger(NULL, NULL, 123, 456));
+}
+
+ZTEST(ocpc, test_ocpc_config_secondary_charger__unimpl)
+{
+	int desired_charger_input_current;
+	int desired_batt_voltage_mv = 10000;
+	int desired_batt_current_ma = 1000;
+	struct ocpc_data test_ocpc = {
+		/* First run through loop */
+		.last_vsys = OCPC_UNINIT,
+	};
+
+	charge_set_active_chg_chip(CHARGER_SECONDARY);
+
+	/* Need to manually adjust Vsys */
+	charger_set_vsys_compensation_fake.return_val = EC_ERROR_UNIMPLEMENTED;
+
+	/* charger_set_vsys_compensation() will succeed and we will be
+	 * done. Again use an arbitrary non-zero desired_current.
+	 */
+	zassert_equal(EC_SUCCESS, ocpc_config_secondary_charger(
+					  &desired_charger_input_current,
+					  &test_ocpc, desired_batt_voltage_mv,
+					  desired_batt_current_ma));
+}
+
+ZTEST(ocpc, test_ocpc_config_secondary_charger__second_loop)
+{
+	int desired_charger_input_current = 2;
+	int desired_batt_voltage_mv = 10000;
+	int desired_batt_current_ma = 1000;
+	int initial_integral = 123;
+	struct ocpc_data test_ocpc = {
+		/* Non-first run through loop */
+		.last_vsys = 0,
+		.integral = initial_integral,
+	};
+
+	/* Proportional controller only */
+	test_ki = 0;
+	test_ki_div = 1;
+	test_kd = 0;
+	test_kd_div = 1;
+	ocpc_set_pid_constants();
+
+	charge_set_active_chg_chip(CHARGER_SECONDARY);
+
+	/* Need to manually adjust Vsys */
+	charger_set_vsys_compensation_fake.return_val = EC_ERROR_UNIMPLEMENTED;
+
+	/* charger_set_vsys_compensation() will succeed and we will be
+	 * done. Again use an arbitrary non-zero desired_current.
+	 */
+	zassert_equal(EC_SUCCESS, ocpc_config_secondary_charger(
+					  &desired_charger_input_current,
+					  &test_ocpc, desired_batt_voltage_mv,
+					  desired_batt_current_ma));
+
+	/* Make sure the integral got updated */
+	int expected_last_error =
+		desired_charger_input_current - test_ocpc.secondary_ibus_ma;
+
+	zassert_equal(expected_last_error, test_ocpc.last_error,
+		      "Actual: %d, expected: %d", test_ocpc.last_error,
+		      expected_last_error);
+	zassert_equal(expected_last_error + initial_integral,
+		      test_ocpc.integral, "Actual: %d, expected: %d",
+		      test_ocpc.integral,
+		      expected_last_error + initial_integral);
+}
+
+ZTEST(ocpc, test_ocpc_calc_resistances__not_charging)
+{
+	struct ocpc_data test_ocpc;
+	struct batt_params test_batt_params;
+
+	/* There are multiple conditions to exercise that qualify as charging */
+
+	/* Battery current below 1666 */
+	test_ocpc = (struct ocpc_data){ 0 };
+	test_batt_params = (struct batt_params){
+		.current = 0,
+	};
+	zassert_equal(EC_ERROR_INVALID_CONFIG,
+		      ocpc_calc_resistances(&test_ocpc, &test_batt_params));
+
+	/* Isys <= 0 */
+	test_ocpc = (struct ocpc_data){ 0 };
+	test_batt_params = (struct batt_params){
+		.current = 1667,
+	};
+	zassert_equal(EC_ERROR_INVALID_CONFIG,
+		      ocpc_calc_resistances(&test_ocpc, &test_batt_params));
+}
+
+ZTEST(ocpc, test_ocpc_calc_resistances__separate)
+{
+	struct ocpc_data test_ocpc;
+	struct batt_params test_batt_params;
+
+	/* Make Rsys = 1, Rbatt = 2 */
+	test_ocpc = (struct ocpc_data){
+		.vsys_aux_mv = 2005,
+		.vsys_mv = 2000,
+		.isys_ma = 1000,
+	};
+	test_batt_params = (struct batt_params){
+		.current = 2000,
+		.voltage = 1950,
+	};
+
+	/* Run enough times to become seeded. */
+	for (int i = 0; i < 17; i++) {
+		zassert_equal(EC_SUCCESS,
+			      ocpc_calc_resistances(&test_ocpc,
+						    &test_batt_params));
+	}
+
+	int expected_rbatt = (test_ocpc.vsys_mv - test_batt_params.voltage) *
+			     1000 / test_batt_params.current;
+
+	zassert_equal(expected_rbatt, test_ocpc.rbatt_mo,
+		      "Actual: %d, expected: %d", test_ocpc.rbatt_mo,
+		      expected_rbatt);
+
+	int expected_rsys = (test_ocpc.vsys_aux_mv - test_ocpc.vsys_mv) * 1000 /
+			    test_ocpc.isys_ma;
+
+	zassert_equal(expected_rsys, test_ocpc.rsys_mo,
+		      "Actual: %d, expected: %d", test_ocpc.rsys_mo,
+		      expected_rsys);
+}
+
+static void reset(void *fixture)
+{
+	ARG_UNUSED(fixture);
+
+	charge_set_active_chg_chip(CHARGER_PRIMARY);
+	trigger_ocpc_reset();
+
+	/* Reset fakes */
+	RESET_FAKE(ocpc_get_pid_constants);
+	RESET_FAKE(battery_is_charge_fet_disabled);
+	RESET_FAKE(charger_set_vsys_compensation);
+
+	/* Load values that match ocpc.c's defaults */
+	test_kp = 1;
+	test_kp_div = 4;
+	test_ki = 1;
+	test_ki_div = 15;
+	test_kd = 1;
+	test_kd_div = 10;
+
+	ocpc_get_pid_constants_fake.custom_fake = get_pid_constants_custom_fake;
+
+	/* Force an update which will use the above parameters. */
+	ocpc_set_pid_constants();
+
+	/* Reset the resistance calculation state */
+	ocpc_calc_resistances(NULL, NULL);
+	test_ocpc_reset_resistance_state();
+}
+
+ZTEST_SUITE(ocpc, NULL, NULL, reset, reset, NULL);
diff --git a/zephyr/test/ocpc/testcase.yaml b/zephyr/test/ocpc/testcase.yaml
new file mode 100644
index 0000000000..31fa165ef1
--- /dev/null
+++ b/zephyr/test/ocpc/testcase.yaml
@@ -0,0 +1,4 @@
+common:
+  platform_allow: native_posix
+tests:
+  ocpc.default: {}
diff --git a/zephyr/test/qcom_power/CMakeLists.txt b/zephyr/test/qcom_power/CMakeLists.txt
new file mode 100644
index 0000000000..4a211dcc85
--- /dev/null
+++ b/zephyr/test/qcom_power/CMakeLists.txt
@@ -0,0 +1,13 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(qcom_power)
+
+# Include the local test directory for shimmed_test_tasks.h
+zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}")
+
+FILE(GLOB_RECURSE test_sources src/*.c)
+target_sources(app PRIVATE ${test_sources})
diff --git a/zephyr/test/qcom_power/Kconfig b/zephyr/test/qcom_power/Kconfig
new file mode 100644
index 0000000000..ac7b264855
--- /dev/null
+++ b/zephyr/test/qcom_power/Kconfig
@@ -0,0 +1,5 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+source "Kconfig.zephyr"
diff --git a/zephyr/test/qcom_power/boards/native_posix.overlay b/zephyr/test/qcom_power/boards/native_posix.overlay
new file mode 100644
index 0000000000..c1ad516b79
--- /dev/null
+++ b/zephyr/test/qcom_power/boards/native_posix.overlay
@@ -0,0 +1,152 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <board-overlays/native_posix.dts>
+#include <dt-bindings/gpio_defines.h>
+#include <cros/binman.dtsi>
+
+/ {
+	chosen {
+		cros-ec,flash-controller = &cros_flash;
+	};
+	aliases {
+		gpio-wp = &gpio_wp_l;
+	};
+	cros_flash: cros-flash {
+		compatible = "cros-ec,flash-emul";
+	};
+
+	/*
+	 * Keep these GPIOs in pin order.
+	 * If you need to add one, make sure you increase
+	 * ngpios in the gpio0 node further down.
+	 */
+	named-gpios {
+		compatible = "named-gpios";
+
+		gpio_acok_od: acok_od {
+			gpios = <&gpio0 0 GPIO_INPUT>;
+			enum-name = "GPIO_AC_PRESENT";
+		};
+		ec_bl_disable_l {
+			gpios = <&gpio0 1 GPIO_INPUT>;
+			enum-name = "GPIO_ENABLE_BACKLIGHT";
+		};
+		gpio_en_pp5000_s5: en_pp5000_s5 {
+			gpios = <&gpio0 2 GPIO_OUTPUT_HIGH>;
+			enum-name = "GPIO_EN_PP5000";
+		};
+		gpio_wp_l: wp_l {
+			gpios = <&gpio0 3 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_switchcap_pg_int_l: switchcap_pg_int_l {
+			gpios = <&gpio0 15 (GPIO_OUTPUT | GPIO_INPUT)>;
+		};
+		gpio_ap_rst_l: ap_rst_l {
+			gpios = <&gpio0 16 GPIO_INPUT>;
+			enum-name = "GPIO_AP_RST_L";
+		};
+		gpio_ps_hold: ps_hold {
+			gpios = <&gpio0 17 (GPIO_INPUT | GPIO_PULL_DOWN)>;
+			enum-name = "GPIO_PS_HOLD";
+		};
+		gpio_mb_power_good: mb_power_good {
+			gpios = <&gpio0 18 (GPIO_INPUT | GPIO_PULL_DOWN)>;
+			enum-name = "GPIO_POWER_GOOD";
+		};
+		gpio_ap_suspend: ap_suspend {
+			gpios = <&gpio0 19 GPIO_INPUT>;
+			enum-name = "GPIO_AP_SUSPEND";
+		};
+		gpio_pmic_kpd_pwr_odl: pmic_kpd_pwr_odl {
+			gpios = <&gpio0 20 GPIO_OUTPUT_HIGH>;
+			enum-name = "GPIO_PMIC_KPD_PWR_ODL";
+		};
+		gpio_pmic_resin_l: pmic_resin_l {
+			/* Real hardware will allow reading even if GPIO_INPUT
+			 * is not set, but the gpio_emul will not.
+			 */
+			gpios = <&gpio0 21 (GPIO_INPUT | GPIO_OUTPUT_HIGH)>;
+			enum-name = "GPIO_PMIC_RESIN_L";
+		};
+		gpio_warm_reset_l: warm_reset_l {
+			gpios = <&gpio0 22 GPIO_INPUT>;
+			enum-name = "GPIO_WARM_RESET_L";
+		};
+		gpio_lid_open_ec: lid_open_ec {
+			/* GPIO_PULL_UP will cause this start asserted. */
+			gpios = <&gpio0 23 (GPIO_INPUT | GPIO_PULL_UP)>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+		gpio_switchcap_on: switchcap_on {
+			gpios = <&gpio0 24 (GPIO_INPUT | GPIO_OUTPUT_LOW)>;
+		};
+		gpio_ec_pwr_btn_odl: ec_pwr_btn_odl {
+			/* GPIO_PULL_UP will cause this start asserted,
+			 * i.e. not pressed.
+			 */
+			gpios = <&gpio0 25 (GPIO_INPUT | GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		gpio_switchcap_pg: src_vph_pwr_pg {
+			gpios = <&gpio0 26 GPIO_INPUT_PULL_DOWN>;
+			enum-name = "GPIO_SWITCHCAP_PG";
+		};
+	};
+
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_ap_rst: ap_rst {
+			irq-pin = <&gpio_ap_rst_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "chipset_ap_rst_interrupt";
+		};
+		int_lid_open_ec: lid_open_ec {
+			irq-pin = <&gpio_lid_open_ec>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "lid_interrupt";
+		};
+		int_mb_power_good: mb_power_good {
+			irq-pin = <&gpio_mb_power_good>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_ap_suspend: ap_suspend {
+			irq-pin = <&gpio_ap_suspend>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_power_button: power_button {
+			irq-pin = <&gpio_ec_pwr_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_button_interrupt";
+		};
+	};
+
+	gpio1: gpio@101 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0x101 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <7>;
+	};
+
+	switchcap {
+		compatible = "cros-ec,switchcap-gpio";
+		enable-pin = <&gpio_switchcap_on>;
+		power-good-pin = <&gpio_switchcap_pg>;
+		poff-delay-ms = <1>;
+	};
+};
+
+&gpio0 {
+	ngpios = <32>;
+};
diff --git a/zephyr/test/qcom_power/boards/power_button.dtsi b/zephyr/test/qcom_power/boards/power_button.dtsi
new file mode 100644
index 0000000000..0edbaa3e5b
--- /dev/null
+++ b/zephyr/test/qcom_power/boards/power_button.dtsi
@@ -0,0 +1,26 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include <dt-bindings/buttons.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	gpio-keys {
+		compatible = "zephyr,gpio-keys";
+		debounce-interval-ms = <30>;
+		power_button: power_button {
+			gpios = <&gpio0 25 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			/* TODO: use an INPUT_KEY code here. */
+			zephyr,code = <BUTTON_POWER>;
+		};
+	};
+
+};
+
+/* interrupt overrides */
+/{
+	gpio-interrupts {
+		/delete-node/ power_button;
+	};
+};
diff --git a/zephyr/test/qcom_power/prj.conf b/zephyr/test/qcom_power/prj.conf
new file mode 100644
index 0000000000..688ce4ac1f
--- /dev/null
+++ b/zephyr/test/qcom_power/prj.conf
@@ -0,0 +1,41 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_ASSERT=y
+CONFIG_TEST=y
+CONFIG_ZTEST=y
+CONFIG_ZTEST_ASSERT_VERBOSE=1
+CONFIG_ZTEST_MOCKING=y
+CONFIG_ZTEST_NEW_API=y
+
+CONFIG_INPUT=y
+
+# Print logs from Zephyr LOG_MODULE to stdout
+CONFIG_NATIVE_UART_0_ON_STDINOUT=y
+
+CONFIG_CROS_EC=y
+CONFIG_EMUL=y
+CONFIG_FLASH=y
+CONFIG_GPIO=y
+CONFIG_GPIO_GET_CONFIG=y
+CONFIG_PLATFORM_EC=y
+CONFIG_RING_BUFFER=y
+CONFIG_SERIAL=y
+CONFIG_SHELL_BACKEND_DUMMY=y
+CONFIG_SHELL_BACKEND_DUMMY_BUF_SIZE=2000
+CONFIG_SHELL_BACKEND_SERIAL=n
+CONFIG_SHIMMED_TASKS=y
+
+# QCom power sequencing
+CONFIG_AP_ARM_QUALCOMM_SC7280=y
+CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK=y
+CONFIG_PLATFORM_EC_EXTPOWER=y
+CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y
+CONFIG_PLATFORM_EC_HOSTCMD=y
+CONFIG_PLATFORM_EC_LID_SWITCH=y
+CONFIG_PLATFORM_EC_POWERSEQ=y
+CONFIG_PLATFORM_EC_POWERSEQ_HOST_SLEEP=y
+CONFIG_PLATFORM_EC_POWERSEQ_SC7280=y
+CONFIG_PLATFORM_EC_POWER_BUTTON=y
+CONFIG_PLATFORM_EC_POWER_SLEEP_FAILURE_DETECTION=y
diff --git a/zephyr/test/qcom_power/src/main.c b/zephyr/test/qcom_power/src/main.c
new file mode 100644
index 0000000000..c5c3953208
--- /dev/null
+++ b/zephyr/test/qcom_power/src/main.c
@@ -0,0 +1,695 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "ec_app_main.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "include/power_button.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power/qcom.h"
+#include "task.h"
+
+#include <setjmp.h>
+
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/fff.h>
+#include <zephyr/input/input.h>
+#include <zephyr/kernel.h>
+#include <zephyr/shell/shell_dummy.h>
+#include <zephyr/ztest.h>
+
+#include <dt-bindings/buttons.h>
+
+/* For simplicity, enforce that all the gpios are on the same controller. */
+#define GPIO_DEVICE \
+	DEVICE_DT_GET(DT_GPIO_CTLR(NAMED_GPIOS_GPIO_NODE(ap_rst_l), gpios))
+#define ASSERT_SAME_CONTROLLER(x)                                        \
+	BUILD_ASSERT(                                                    \
+		DT_DEP_ORD(DT_GPIO_CTLR(NAMED_GPIOS_GPIO_NODE(ap_rst_l), \
+					gpios)) ==                       \
+		DT_DEP_ORD(DT_GPIO_CTLR(NAMED_GPIOS_GPIO_NODE(x), gpios)))
+
+#define AP_RST_L_PIN DT_GPIO_PIN(NAMED_GPIOS_GPIO_NODE(ap_rst_l), gpios)
+ASSERT_SAME_CONTROLLER(ap_rst_l);
+#define POWER_GOOD_PIN DT_GPIO_PIN(NAMED_GPIOS_GPIO_NODE(mb_power_good), gpios)
+ASSERT_SAME_CONTROLLER(mb_power_good);
+#define AP_SUSPEND_PIN DT_GPIO_PIN(NAMED_GPIOS_GPIO_NODE(ap_suspend), gpios)
+ASSERT_SAME_CONTROLLER(ap_suspend);
+#define SWITCHCAP_PG_PIN \
+	DT_GPIO_PIN(NAMED_GPIOS_GPIO_NODE(src_vph_pwr_pg), gpios)
+ASSERT_SAME_CONTROLLER(src_vph_pwr_pg);
+#define PMIC_RESIN_L_PIN DT_GPIO_PIN(NAMED_GPIOS_GPIO_NODE(pmic_resin_l), gpios)
+ASSERT_SAME_CONTROLLER(pmic_resin_l);
+#define EC_PWR_BTN_ODL_PIN \
+	DT_GPIO_PIN(NAMED_GPIOS_GPIO_NODE(ec_pwr_btn_odl), gpios)
+ASSERT_SAME_CONTROLLER(ec_pwr_btn_odl);
+#define LID_OPEN_EC_PIN DT_GPIO_PIN(NAMED_GPIOS_GPIO_NODE(lid_open_ec), gpios)
+ASSERT_SAME_CONTROLLER(lid_open_ec);
+#define PMIC_KPD_PWR_ODL_PIN \
+	DT_GPIO_PIN(NAMED_GPIOS_GPIO_NODE(pmic_kpd_pwr_odl), gpios)
+ASSERT_SAME_CONTROLLER(pmic_kpd_pwr_odl);
+
+static int chipset_reset_count;
+static bool set_power_good_on_reset;
+
+static void do_chipset_reset(void)
+{
+	chipset_reset_count++;
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESET, do_chipset_reset, HOOK_PRIO_DEFAULT);
+
+static void do_chipset_shutdown(void)
+{
+	if (set_power_good_on_reset) {
+		static const struct device *gpio_dev = GPIO_DEVICE;
+
+		gpio_emul_input_set(gpio_dev, POWER_GOOD_PIN, 1);
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, do_chipset_shutdown, HOOK_PRIO_DEFAULT);
+
+DEFINE_FFF_GLOBALS;
+
+FAKE_VALUE_FUNC(int, system_can_boot_ap);
+FAKE_VALUE_FUNC(int, battery_wait_for_stable);
+int battery_is_present(void)
+{
+	return 1;
+}
+
+/* Tests the chipset_ap_rst_interrupt() handler when in S3.
+ *
+ * When the system is in S3, and ap_rst_l is pulsed 1-3 times then
+ * HOOK_CHIPSET_RESET hooks will run, and interrupts will be disabled for
+ * ap_suspend (see power_chipset_handle_host_sleep_event). This may be
+ * artificial, since I'm not sure that this scenario can actually ever happen.
+ */
+static void do_chipset_ap_rst_interrupt_in_s3(int times)
+{
+	static const struct device *gpio_dev = GPIO_DEVICE;
+
+	/* Preconditions */
+	power_signal_enable_interrupt(GPIO_AP_SUSPEND);
+	zassert_ok(gpio_emul_input_set(gpio_dev, AP_SUSPEND_PIN, 1));
+	power_set_state(POWER_S3);
+	task_wake(TASK_ID_CHIPSET);
+	k_sleep(K_MSEC(10));
+	zassert_equal(power_get_state(), POWER_S3);
+
+	shell_backend_dummy_clear_output(get_ec_shell());
+	chipset_reset_count = 0;
+
+	/* Pulse gpio_ap_rst_l `times` */
+	for (int i = 0; i < times; ++i) {
+		zassert_ok(gpio_emul_input_set(gpio_dev, AP_RST_L_PIN, 0));
+		zassert_ok(gpio_emul_input_set(gpio_dev, AP_RST_L_PIN, 1));
+	}
+
+	/* Wait for timeout AP_RST_TRANSITION_TIMEOUT. */
+	k_sleep(K_MSEC(500));
+
+	/* Verify that gpio_ap_suspend is ignored. */
+	zassert_ok(gpio_emul_input_set(gpio_dev, AP_SUSPEND_PIN, 0));
+	k_sleep(K_MSEC(10));
+	zassert_equal(power_get_state(), POWER_S3);
+	/* Verify that HOOK_CHIPSET_RESET was called once. */
+	zassert_equal(chipset_reset_count, 1);
+}
+
+ZTEST(qcom_power, test_notify_chipset_reset_s3_timeout)
+{
+	const char *buffer;
+	size_t buffer_size;
+
+	do_chipset_ap_rst_interrupt_in_s3(1);
+	buffer = shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+	zassert_true(strstr(buffer, "AP_RST_L transitions not expected: 1") !=
+			     NULL,
+		     "Invalid console output %s", buffer);
+	zassert_true(strstr(buffer, "Chipset reset: exit s3") != NULL,
+		     "Invalid console output %s", buffer);
+}
+
+ZTEST(qcom_power, test_notify_chipset_reset_s3)
+{
+	const char *buffer;
+	size_t buffer_size;
+
+	do_chipset_ap_rst_interrupt_in_s3(3);
+	buffer = shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+	zassert_false(strstr(buffer, "AP_RST_L transitions not expected") !=
+			      NULL,
+		      "Invalid console output %s", buffer);
+	zassert_true(strstr(buffer, "Chipset reset: exit s3") != NULL,
+		     "Invalid console output %s", buffer);
+}
+
+/* Tests the chipset_ap_rst_interrupt() handler when in S0.
+ *
+ * When the system is in S0, and ap_rst_l is pulsed 1-3 times then
+ * HOOK_CHIPSET_RESET hooks will run, and that is pretty much all that happens.
+ */
+static void do_chipset_ap_rst_interrupt_in_s0(int times)
+{
+	static const struct device *gpio_dev = GPIO_DEVICE;
+
+	shell_backend_dummy_clear_output(get_ec_shell());
+	chipset_reset_count = 0;
+
+	/* Pulse gpio_ap_rst_l `times` */
+	for (int i = 0; i < times; ++i) {
+		zassert_ok(gpio_emul_input_set(gpio_dev, AP_RST_L_PIN, 0));
+		zassert_ok(gpio_emul_input_set(gpio_dev, AP_RST_L_PIN, 1));
+	}
+
+	/* Wait for timeout AP_RST_TRANSITION_TIMEOUT. */
+	k_sleep(K_MSEC(500));
+
+	/* Verify that HOOK_CHIPSET_RESET was called once. */
+	zassert_equal(chipset_reset_count, 1);
+}
+
+ZTEST(qcom_power, test_notify_chipset_reset_s0_timeout)
+{
+	const char *buffer;
+	size_t buffer_size;
+
+	do_chipset_ap_rst_interrupt_in_s0(1);
+	buffer = shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+	zassert_true(strstr(buffer, "AP_RST_L transitions not expected: 1") !=
+			     NULL,
+		     "Invalid console output %s", buffer);
+	zassert_false(strstr(buffer, "Chipset reset: exit s3") != NULL,
+		      "Invalid console output %s", buffer);
+}
+
+ZTEST(qcom_power, test_notify_chipset_reset_s0)
+{
+	const char *buffer;
+	size_t buffer_size;
+
+	do_chipset_ap_rst_interrupt_in_s0(3);
+	buffer = shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+	zassert_false(strstr(buffer, "AP_RST_L transitions not expected") !=
+			      NULL,
+		      "Invalid console output %s", buffer);
+	zassert_false(strstr(buffer, "Chipset reset: exit s3") != NULL,
+		      "Invalid console output %s", buffer);
+}
+
+/* Call chipset_reset, don't provide signals from AP. Verify logs. */
+ZTEST(qcom_power, test_chipset_reset_timeout)
+{
+	const char *buffer;
+	size_t buffer_size;
+
+	/* Reset. The reason doesn't really matter. */
+	shell_backend_dummy_clear_output(get_ec_shell());
+	chipset_reset(CHIPSET_RESET_KB_WARM_REBOOT);
+	/* Long enough for the cold reset. */
+	k_sleep(K_SECONDS(10));
+
+	/* Verify logged messages. */
+	buffer = shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+	zassert_true(strstr(buffer,
+			    "AP refuses to warm reset. Cold resetting") != NULL,
+		     "Invalid console output %s", buffer);
+	zassert_true(strstr(buffer, "power state 1 = S5") != NULL,
+		     "Invalid console output %s", buffer);
+	zassert_equal(power_get_state(), POWER_S0);
+}
+
+static struct gpio_callback gpio_callback;
+
+/* warm_reset_seq pulses PMIC_RESIN_L, at the end of that pulse set AP_RST_L. */
+void warm_reset_callback(const struct device *gpio_dev,
+			 struct gpio_callback *callback_struct,
+			 gpio_port_pins_t pins)
+{
+	if ((pins & BIT(PMIC_RESIN_L_PIN)) == 0) {
+		return;
+	}
+	if (gpio_emul_output_get(gpio_dev, PMIC_RESIN_L_PIN)) {
+		gpio_emul_input_set(gpio_dev, AP_RST_L_PIN, 0);
+	}
+}
+
+static void set_power_good(struct k_work *work)
+{
+	static const struct device *gpio_dev = GPIO_DEVICE;
+
+	gpio_emul_input_set(gpio_dev, POWER_GOOD_PIN, 1);
+}
+K_WORK_DEFINE(set_power_good_work, set_power_good);
+
+/* PMIC_KPD_PWR_ODL is a signal to turn the power on. The signal that
+ * it worked is POWER_GOOD.
+ */
+void power_good_callback(const struct device *gpio_dev,
+			 struct gpio_callback *callback_struct,
+			 gpio_port_pins_t pins)
+{
+	if ((pins & BIT(PMIC_KPD_PWR_ODL_PIN)) == 0) {
+		return;
+	}
+	if (!gpio_emul_output_get(gpio_dev, PMIC_KPD_PWR_ODL_PIN)) {
+		/* Set power good in the work queue, instead of now. */
+		k_work_submit(&set_power_good_work);
+	}
+}
+
+/* Call chipset_reset, wait for PMIC_RESIN_L, pulse ap_rsl_l. */
+ZTEST(qcom_power, test_chipset_reset_success)
+{
+	static const struct device *gpio_dev = GPIO_DEVICE;
+	const char *buffer;
+	size_t buffer_size;
+
+	/* Setup callback. */
+	gpio_init_callback(&gpio_callback, warm_reset_callback,
+			   BIT(PMIC_RESIN_L_PIN));
+	zassert_ok(gpio_add_callback(gpio_dev, &gpio_callback));
+	zassert_ok(gpio_pin_interrupt_configure(gpio_dev, PMIC_RESIN_L_PIN,
+						GPIO_INT_EDGE_BOTH));
+
+	/* Reset. The reason doesn't really matter. */
+	shell_backend_dummy_clear_output(get_ec_shell());
+	chipset_reset(CHIPSET_RESET_KB_WARM_REBOOT);
+	k_sleep(K_MSEC(100));
+	gpio_emul_input_set(gpio_dev, AP_RST_L_PIN, 1);
+	/* Long enough for a cold reset, although we don't expect one. */
+	k_sleep(K_MSEC(1000));
+
+	/* Verify logged messages. */
+	buffer = shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+	zassert_false(strstr(buffer,
+			     "AP refuses to warm reset. Cold resetting") !=
+			      NULL,
+		      "Invalid console output %s", buffer);
+	zassert_false(strstr(buffer, "power state 1 = S5") != NULL,
+		      "Invalid console output %s", buffer);
+	zassert_equal(power_get_state(), POWER_S0);
+}
+
+/* Sent the host command, set the gpio, wait for transition to S3. */
+ZTEST(qcom_power, test_request_sleep)
+{
+	static const struct device *gpio_dev = GPIO_DEVICE;
+	struct ec_params_host_sleep_event params = {
+		.sleep_event = HOST_SLEEP_EVENT_S3_SUSPEND,
+	};
+
+	zassert_ok(ec_cmd_host_sleep_event(NULL, &params));
+	zassert_ok(gpio_emul_input_set(gpio_dev, AP_SUSPEND_PIN, 1));
+	k_sleep(K_SECONDS(16));
+	zassert_equal(power_get_state(), POWER_S3);
+	zassert_false(host_is_event_set(EC_HOST_EVENT_HANG_DETECT));
+}
+
+/* Sent the host command, don't set the gpio, look for host event. */
+ZTEST(qcom_power, test_request_sleep_timeout)
+{
+	const char *buffer;
+	size_t buffer_size;
+	struct ec_params_host_sleep_event params = {
+		.sleep_event = HOST_SLEEP_EVENT_S3_SUSPEND,
+	};
+
+	shell_backend_dummy_clear_output(get_ec_shell());
+	zassert_ok(ec_cmd_host_sleep_event(NULL, &params));
+	k_sleep(K_SECONDS(16));
+	zassert_equal(power_get_state(), POWER_S0);
+	buffer = shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+	zassert_true(strstr(buffer, "Detected sleep hang!") != NULL,
+		     "Invalid console output %s", buffer);
+	zassert_true(host_is_event_set(EC_HOST_EVENT_HANG_DETECT));
+}
+
+ZTEST(qcom_power, test_chipset_force_shutdown)
+{
+	chipset_force_shutdown(CHIPSET_SHUTDOWN_G3);
+	k_sleep(K_SECONDS(11));
+	zassert_equal(power_get_state(), POWER_G3);
+}
+
+ZTEST(qcom_power, test_power_button)
+{
+	static const struct device *gpio_dev = GPIO_DEVICE;
+
+	/* Setup callback. */
+	gpio_init_callback(&gpio_callback, power_good_callback,
+			   BIT(PMIC_KPD_PWR_ODL_PIN));
+	zassert_ok(gpio_add_callback(gpio_dev, &gpio_callback));
+
+	power_set_state(POWER_G3);
+	zassert_ok(gpio_emul_input_set(gpio_dev, POWER_GOOD_PIN, 0));
+	zassert_ok(gpio_emul_input_set(gpio_dev, PMIC_RESIN_L_PIN, 1));
+	k_sleep(K_MSEC(10));
+	zassert_equal(power_get_state(), POWER_G3);
+
+	zassert_ok(gpio_emul_input_set(gpio_dev, EC_PWR_BTN_ODL_PIN, 0));
+	k_sleep(K_MSEC(100));
+	zassert_equal(power_button_signal_asserted(), 1);
+	zassert_ok(gpio_emul_input_set(gpio_dev, EC_PWR_BTN_ODL_PIN, 1));
+	k_sleep(K_MSEC(500));
+	zassert_equal(power_button_signal_asserted(), 0);
+	zassert_equal(power_get_state(), POWER_S0);
+}
+
+#ifdef CONFIG_INPUT_GPIO_KEYS
+
+ZTEST(qcom_power, test_power_button_input_event)
+{
+	const struct device *dev = DEVICE_DT_GET_ONE(zephyr_gpio_keys);
+
+	zassert_equal(power_button_is_pressed(), 0);
+
+	input_report_key(dev, BUTTON_POWER, 1, true, K_FOREVER);
+	zassert_equal(power_button_is_pressed(), 1);
+
+	input_report_key(dev, BUTTON_RECOVERY, 1, true, K_FOREVER);
+	zassert_equal(power_button_is_pressed(), 1);
+
+	input_report_abs(dev, INPUT_ABS_X, 1, true, K_FOREVER);
+	zassert_equal(power_button_is_pressed(), 1);
+
+	input_report_key(dev, BUTTON_POWER, 0, true, K_FOREVER);
+	zassert_equal(power_button_is_pressed(), 0);
+}
+
+#endif
+
+ZTEST(qcom_power, test_power_button_no_power_good)
+{
+	static const struct device *gpio_dev = GPIO_DEVICE;
+
+	zassert_ok(gpio_emul_input_set(gpio_dev, POWER_GOOD_PIN, 0));
+	power_set_state(POWER_G3);
+	k_sleep(K_MSEC(10));
+	zassert_equal(power_get_state(), POWER_G3);
+
+	zassert_ok(gpio_emul_input_set(gpio_dev, EC_PWR_BTN_ODL_PIN, 0));
+	k_sleep(K_MSEC(100));
+	zassert_ok(gpio_emul_input_set(gpio_dev, EC_PWR_BTN_ODL_PIN, 1));
+	k_sleep(K_MSEC(1500));
+	zassert_equal(power_get_state(), POWER_S5, "power_state=%d",
+		      power_get_state());
+}
+
+ZTEST(qcom_power, test_power_button_no_switchcap_good)
+{
+	static const struct device *gpio_dev = GPIO_DEVICE;
+
+	zassert_ok(gpio_emul_input_set(gpio_dev, SWITCHCAP_PG_PIN, 0));
+	power_set_state(POWER_G3);
+	k_sleep(K_MSEC(10));
+	zassert_equal(power_get_state(), POWER_G3);
+
+	zassert_ok(gpio_emul_input_set(gpio_dev, EC_PWR_BTN_ODL_PIN, 0));
+	k_sleep(K_MSEC(100));
+	zassert_ok(gpio_emul_input_set(gpio_dev, EC_PWR_BTN_ODL_PIN, 1));
+	k_sleep(K_SECONDS(10));
+	zassert_equal(power_get_state(), POWER_S5, "power_state=%d",
+		      power_get_state());
+}
+
+ZTEST(qcom_power, test_power_button_no_pmic_resin_pullup)
+{
+	const char *buffer;
+	size_t buffer_size;
+	static const struct device *gpio_dev = GPIO_DEVICE;
+
+	power_set_state(POWER_G3);
+	k_sleep(K_MSEC(10));
+	zassert_equal(power_get_state(), POWER_G3);
+
+	shell_backend_dummy_clear_output(get_ec_shell());
+	zassert_ok(gpio_emul_input_set(gpio_dev, POWER_GOOD_PIN, 0));
+	zassert_ok(gpio_emul_input_set(gpio_dev, PMIC_RESIN_L_PIN, 0));
+	zassert_ok(gpio_emul_input_set(gpio_dev, EC_PWR_BTN_ODL_PIN, 0));
+	k_sleep(K_MSEC(100));
+	zassert_ok(gpio_emul_input_set(gpio_dev, EC_PWR_BTN_ODL_PIN, 1));
+	k_sleep(K_SECONDS(10));
+	zassert_equal(power_get_state(), POWER_S5, "power_state=%d",
+		      power_get_state());
+
+	buffer = shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+	zassert_not_null(strstr(buffer, "PMIC_RESIN_L not pulled up by PMIC"),
+			 "Invalid console output %s", buffer);
+}
+
+ZTEST(qcom_power, test_power_button_battery_low)
+{
+	static const struct device *gpio_dev = GPIO_DEVICE;
+
+	RESET_FAKE(system_can_boot_ap);
+	system_can_boot_ap_fake.return_val = 0;
+
+	power_set_state(POWER_G3);
+	k_sleep(K_MSEC(10));
+	zassert_equal(power_get_state(), POWER_G3);
+
+	zassert_ok(gpio_emul_input_set(gpio_dev, EC_PWR_BTN_ODL_PIN, 0));
+	k_sleep(K_MSEC(100));
+	zassert_ok(gpio_emul_input_set(gpio_dev, EC_PWR_BTN_ODL_PIN, 1));
+	/* > CAN_BOOT_AP_CHECK_TIMEOUT + CAN_BOOT_AP_CHECK_WAIT */
+	k_sleep(K_MSEC(1800));
+	zassert_equal(power_get_state(), POWER_S5);
+}
+
+ZTEST(qcom_power, test_host_sleep_event_resume)
+{
+	static const struct device *gpio_dev = GPIO_DEVICE;
+	struct ec_params_host_sleep_event params = {
+		.sleep_event = HOST_SLEEP_EVENT_S3_RESUME,
+	};
+
+	/* Get into S3 first */
+	power_signal_enable_interrupt(GPIO_AP_SUSPEND);
+	zassert_ok(gpio_emul_input_set(gpio_dev, AP_SUSPEND_PIN, 1));
+	power_set_state(POWER_S3);
+	task_wake(TASK_ID_CHIPSET);
+	k_sleep(K_MSEC(10));
+	zassert_equal(power_get_state(), POWER_S3);
+
+	/* Exit suspend via gpio. */
+	zassert_ok(gpio_emul_input_set(gpio_dev, AP_SUSPEND_PIN, 0));
+	k_sleep(K_MSEC(100));
+	zassert_equal(power_get_state(), POWER_S0, "power_state=%d",
+		      power_get_state());
+
+	/* Call host command to notify ec resume is done. */
+	zassert_ok(ec_cmd_host_sleep_event(NULL, &params));
+	k_sleep(K_MSEC(10));
+	zassert_equal(power_get_state(), POWER_S0, "power_state=%d",
+		      power_get_state());
+
+	/* Check that AP_SUSPEND interrupts are disabled & we are in S0. */
+	zassert_ok(gpio_emul_input_set(gpio_dev, AP_SUSPEND_PIN, 1));
+	k_sleep(K_MSEC(100));
+	zassert_equal(power_get_state(), POWER_S0);
+}
+
+ZTEST(qcom_power, test_power_button_off)
+{
+	static const struct device *gpio_dev = GPIO_DEVICE;
+
+	zassert_ok(gpio_emul_input_set(gpio_dev, EC_PWR_BTN_ODL_PIN, 0));
+	k_sleep(K_SECONDS(9));
+	zassert_ok(gpio_emul_input_set(gpio_dev, EC_PWR_BTN_ODL_PIN, 1));
+	k_sleep(K_MSEC(500));
+	zassert_equal(power_get_state(), POWER_S5);
+}
+
+ZTEST(qcom_power, test_power_button_off_cancel)
+{
+	static const struct device *gpio_dev = GPIO_DEVICE;
+
+	zassert_ok(gpio_emul_input_set(gpio_dev, EC_PWR_BTN_ODL_PIN, 0));
+	k_sleep(K_SECONDS(4));
+	zassert_ok(gpio_emul_input_set(gpio_dev, EC_PWR_BTN_ODL_PIN, 1));
+	k_sleep(K_MSEC(500));
+	zassert_equal(power_get_state(), POWER_S0);
+}
+
+ZTEST(qcom_power, test_no_power_good)
+{
+	const char *buffer;
+	size_t buffer_size;
+	static const struct device *gpio_dev = GPIO_DEVICE;
+
+	shell_backend_dummy_clear_output(get_ec_shell());
+	zassert_ok(gpio_emul_input_set(gpio_dev, POWER_GOOD_PIN, 0));
+	k_sleep(K_MSEC(500));
+	zassert_equal(power_get_state(), POWER_S5, "power_state=%d",
+		      power_get_state());
+	buffer = shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+	zassert_true(strstr(buffer, "POWER_GOOD is lost") != NULL,
+		     "Invalid console output %s", buffer);
+}
+
+ZTEST(qcom_power, test_no_power_good_then_good)
+{
+	const char *buffer;
+	size_t buffer_size;
+	static const struct device *gpio_dev = GPIO_DEVICE;
+
+	shell_backend_dummy_clear_output(get_ec_shell());
+	zassert_ok(gpio_emul_input_set(gpio_dev, POWER_GOOD_PIN, 0));
+	set_power_good_on_reset = true;
+	k_sleep(K_MSEC(500));
+	zassert_equal(power_get_state(), POWER_S5, "power_state=%d",
+		      power_get_state());
+	buffer = shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+	zassert_true(strstr(buffer, "POWER_GOOD is lost") != NULL,
+		     "Invalid console output %s", buffer);
+	zassert_true(strstr(buffer, "POWER_GOOD up again after lost") != NULL,
+		     "Invalid console output %s", buffer);
+}
+
+ZTEST(qcom_power, test_lid_open_power_on)
+{
+	static const struct device *gpio_dev = GPIO_DEVICE;
+
+	zassert_ok(gpio_emul_input_set(gpio_dev, LID_OPEN_EC_PIN, 0));
+	power_set_state(POWER_G3);
+	k_sleep(K_MSEC(100));
+	zassert_equal(power_get_state(), POWER_G3);
+	zassert_false(lid_is_open());
+
+	zassert_ok(gpio_emul_input_set(gpio_dev, LID_OPEN_EC_PIN, 1));
+	k_sleep(K_MSEC(500));
+	zassert_equal(power_get_state(), POWER_S0, "power_state=%d",
+		      power_get_state());
+}
+
+/* chipset_power_on is called by USB code on dock power button release. */
+ZTEST(qcom_power, test_chipset_power_on)
+{
+	power_set_state(POWER_G3);
+	k_sleep(K_MSEC(100));
+	zassert_equal(power_get_state(), POWER_G3);
+
+	chipset_power_on();
+	k_sleep(K_MSEC(500));
+	zassert_equal(power_get_state(), POWER_S0, "power_state=%d",
+		      power_get_state());
+}
+
+static jmp_buf assert_jumpdata;
+static int num_asserts;
+
+void assert_post_action(const char *file, unsigned int line)
+{
+	++num_asserts;
+	longjmp(assert_jumpdata, 1);
+}
+
+ZTEST(qcom_power, test_invalid_power_state)
+{
+	if (setjmp(assert_jumpdata) == 0) {
+		power_handle_state(POWER_S4);
+		zassert_unreachable();
+	}
+	zassert_equal(num_asserts, 1);
+}
+
+ZTEST(qcom_power, test_power_chipset_init_sysjump_power_good)
+{
+	system_set_reset_flags(EC_RESET_FLAG_SYSJUMP);
+	zassert_equal(power_chipset_init(), POWER_S0);
+	power_set_state(POWER_S0);
+
+	task_wake(TASK_ID_CHIPSET);
+	k_sleep(K_MSEC(500));
+	zassert_equal(power_get_state(), POWER_S0, "power_state=%d",
+		      power_get_state());
+	zassert_equal(power_has_signals(POWER_SIGNAL_MASK(0)), 0);
+}
+
+ZTEST(qcom_power, test_power_chipset_init_sysjump_power_off)
+{
+	static const struct device *gpio_dev = GPIO_DEVICE;
+
+	zassert_ok(gpio_emul_input_set(gpio_dev, POWER_GOOD_PIN, 0));
+	system_set_reset_flags(EC_RESET_FLAG_SYSJUMP);
+	zassert_equal(power_chipset_init(), POWER_G3);
+	power_set_state(POWER_G3);
+
+	task_wake(TASK_ID_CHIPSET);
+	k_sleep(K_MSEC(500));
+	zassert_equal(power_get_state(), POWER_G3, "power_state=%d",
+		      power_get_state());
+}
+
+ZTEST(qcom_power, test_power_chipset_init_ap_off)
+{
+	system_set_reset_flags(EC_RESET_FLAG_AP_OFF);
+	zassert_equal(power_chipset_init(), POWER_G3);
+	power_set_state(POWER_G3);
+
+	task_wake(TASK_ID_CHIPSET);
+	k_sleep(K_MSEC(500));
+	zassert_equal(power_get_state(), POWER_G3, "power_state=%d",
+		      power_get_state());
+}
+
+void start_in_s0(void *fixture)
+{
+	static const struct device *gpio_dev = GPIO_DEVICE;
+
+	RESET_FAKE(system_can_boot_ap);
+	system_can_boot_ap_fake.return_val = 1;
+	set_power_good_on_reset = false;
+
+	power_signal_disable_interrupt(GPIO_AP_SUSPEND);
+	power_signal_enable_interrupt(GPIO_AP_RST_L);
+	zassert_ok(gpio_emul_input_set(gpio_dev, POWER_GOOD_PIN, 1));
+	zassert_ok(gpio_emul_input_set(gpio_dev, AP_SUSPEND_PIN, 0));
+	zassert_ok(gpio_emul_input_set(gpio_dev, AP_RST_L_PIN, 1));
+	zassert_ok(gpio_emul_input_set(gpio_dev, SWITCHCAP_PG_PIN, 1));
+	zassert_ok(gpio_pin_set(gpio_dev, PMIC_RESIN_L_PIN, 1));
+	zassert_ok(gpio_emul_input_set(gpio_dev, LID_OPEN_EC_PIN, 1));
+	power_set_state(POWER_S0);
+	power_signal_interrupt(GPIO_AP_SUSPEND);
+	task_wake(TASK_ID_CHIPSET);
+	/* Wait for timeout AP_RST_TRANSITION_TIMEOUT. */
+	k_sleep(K_MSEC(500));
+	zassert_equal(power_get_state(), POWER_S0, "power_state=%d",
+		      power_get_state());
+	zassert_equal(power_has_signals(POWER_SIGNAL_MASK(0)), 0);
+}
+
+void qcom_cleanup(void *fixture)
+{
+	if (gpio_callback.handler != NULL) {
+		static const struct device *gpio_dev = GPIO_DEVICE;
+
+		gpio_remove_callback(gpio_dev, &gpio_callback);
+		gpio_callback.handler = NULL;
+	}
+	host_clear_events(EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT));
+	system_clear_reset_flags(EC_RESET_FLAG_SYSJUMP | EC_RESET_FLAG_AP_OFF);
+}
+
+ZTEST_SUITE(qcom_power, NULL, NULL, start_in_s0, qcom_cleanup, NULL);
+
+void test_main(void)
+{
+	ec_app_main();
+	/* Fake sleep long enough to go to S5 and back to G3 again. */
+	k_sleep(K_SECONDS(11));
+
+	ztest_run_test_suites(NULL);
+
+	ztest_verify_all_test_suites_ran();
+}
diff --git a/zephyr/test/qcom_power/testcase.yaml b/zephyr/test/qcom_power/testcase.yaml
new file mode 100644
index 0000000000..026032d06b
--- /dev/null
+++ b/zephyr/test/qcom_power/testcase.yaml
@@ -0,0 +1,10 @@
+common:
+  platform_allow: native_posix
+tests:
+  qcom_power.default: {}
+  qcom_power.power_gpio_keys:
+    extra_configs:
+    - CONFIG_PLATFORM_EC_POWER_BUTTON=n
+    extra_dtc_overlay_files:
+    - ./boards/native_posix.overlay
+    - ./boards/power_button.dtsi
diff --git a/zephyr/test/rex/CMakeLists.txt b/zephyr/test/rex/CMakeLists.txt
new file mode 100644
index 0000000000..e6cb418c79
--- /dev/null
+++ b/zephyr/test/rex/CMakeLists.txt
@@ -0,0 +1,21 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(rex)
+
+zephyr_include_directories("${PLATFORM_EC_PROGRAM_DIR}/rex/include")
+zephyr_include_directories("${PLATFORM_EC_PROGRAM_DIR}/rex/rex/include")
+
+add_subdirectory(${PLATFORM_EC}/zephyr/test/test_utils test_utils)
+
+target_sources_ifdef(CONFIG_TEST_USB_PD_POLICY app PRIVATE src/usb_pd_policy.c)
+target_sources_ifdef(CONFIG_TEST_USB_PD_POLICY app PRIVATE ${PLATFORM_EC_PROGRAM_DIR}/rex/src/usb_pd_policy.c)
+
+target_sources_ifdef(CONFIG_TEST_BOARD_POWER app PRIVATE src/board_power.c)
+target_sources_ifdef(CONFIG_TEST_BOARD_POWER app PRIVATE ${PLATFORM_EC_PROGRAM_DIR}/rex/src/board_power.c)
+
+target_sources_ifdef(CONFIG_TEST_BOARD_USB_MUX_CONFIG app PRIVATE src/usb_mux_config.c)
+target_sources_ifdef(CONFIG_TEST_BOARD_USB_MUX_CONFIG app PRIVATE ${PLATFORM_EC_PROGRAM_DIR}/rex/rex/src/usb_mux_config.c)
diff --git a/zephyr/test/rex/Kconfig b/zephyr/test/rex/Kconfig
new file mode 100644
index 0000000000..ee844046be
--- /dev/null
+++ b/zephyr/test/rex/Kconfig
@@ -0,0 +1,51 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config TEST_BOARD_USB_MUX_CONFIG
+	bool "Run the tests intended for usb_mux_config"
+	help
+	  Include usb_mux_config.c into the binary and test their
+	  functions.
+
+config TEST_USB_PD_POLICY
+	bool "Run the tests intended for usb_pd_policy"
+	help
+	  Include usb_pd_policy.c into the binary and test their functions.
+
+config TEST_ENABLE_USB_PD_DISCHARGE
+	bool "Enable CONFIG_USB_PD_DISCHARGE"
+	help
+	  This is used to define CONFIG_USB_PD_DISCHARGE for testing purposes
+	  directly.
+
+config TEST_ENABLE_USB_PD_HOST_CMD
+	bool "Enable CONFIG_USB_PD_HOST_CMD"
+	help
+	  This is used to define CONFIG_USB_PD_HOST_CMD for testing purposes
+	  directly.
+
+config TEST_BOARD_POWER
+	bool "Run the tests intended for board_power"
+	help
+	  Include board_power.c into the binary and test
+	  their functions.
+
+config TEST_X86_NON_DSX_PWRSEQ_MTL
+	bool "Replace CONFIG_X86_NON_DSX_PWRSEQ_MTL for testing"
+	help
+	  This is used to replace CONFIG_X86_NON_DSX_PWRSEQ_MTL for testing
+	  purposes directly.
+
+config TEST_DISABLE_AP_PWRSEQ
+	bool "Disable CONFIG_AP_PWRSEQ"
+	default n
+	help
+	  This is used to disable CONFIG_AP_PWRSEQ for testing purposes
+	  directly.
+
+module = REX
+module-str = Rex board-specific code
+source "subsys/logging/Kconfig.template.log_config"
+
+source "Kconfig.zephyr"
diff --git a/zephyr/test/rex/README.md b/zephyr/test/rex/README.md
new file mode 100644
index 0000000000..454ed6ebb8
--- /dev/null
+++ b/zephyr/test/rex/README.md
@@ -0,0 +1,3 @@
+Tests for board specific code under `zephyr/program/rex/src`.
+
+Run with ./twister -T zephyr/test/rex
diff --git a/zephyr/test/rex/board_power.dtsi b/zephyr/test/rex/board_power.dtsi
new file mode 100644
index 0000000000..beb1fbb700
--- /dev/null
+++ b/zephyr/test/rex/board_power.dtsi
@@ -0,0 +1,135 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/gpio_defines.h>
+
+/ {
+	common-pwrseq {
+		compatible = "intel,ap-pwrseq";
+	};
+	named-gpios {
+		compatible = "named-gpios";
+		ec_bl_disable_l {
+			gpios = <&gpio0 1 GPIO_INPUT>;
+			enum-name = "GPIO_ENABLE_BACKLIGHT";
+		};
+		gpio_pch_pwrbtn_l: pch_pwrbtn_l {
+			gpios = <&gpio0 2 GPIO_OUTPUT>;
+			enum-name = "GPIO_PCH_PWRBTN_L";
+		};
+		gpio_ec_pwr_btn_odl: ec_pwr_btn_odl {
+			/* GPIO_PULL_UP will cause this start asserted,
+			 * i.e. not pressed.
+			 */
+			gpios = <&gpio0 3 (GPIO_INPUT | GPIO_PULL_UP)>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		gpio_wp_l: wp_l {
+			gpios = <&gpio0 4 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		entering-rw {
+			gpios = <&gpio0 5 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_ENTERING_RW";
+		};
+	};
+	en_pp5000: pwr-en-pp5000-s5 {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PP5000_S5 enable output to regulator";
+		enum-name = "PWR_EN_PP5000_A";
+		gpios = <&gpio0 10 0>;
+		output;
+	};
+	en_pp3300: pwr-en-pp3300-s5 {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PP3300_S5 enable output to LS";
+		enum-name = "PWR_EN_PP3300_A";
+		gpios = <&gpio0 11 0>;
+		output;
+	};
+	rsmrst: pwr-pg-ec-rsmrst-odl {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST power good from regulator";
+		enum-name = "PWR_RSMRST";
+		gpios = <&gpio0 12 0>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	ec_pch_rsmrst: pwr-ec-pch-rsmrst-odl {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST output to PCH";
+		enum-name = "PWR_EC_PCH_RSMRST";
+		gpios = <&gpio0 13 0>;
+		output;
+	};
+	slp_s0: pwr-slp-s0-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_S0_L input from PCH";
+		enum-name = "PWR_SLP_S0";
+		gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+		no-enable;
+	};
+	slp_s3: pwr-slp-s3-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_S3_L input from PCH";
+		enum-name = "PWR_SLP_S3";
+		gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	slp_sus: pwr-slp-sus-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_SUS_L input from PCH";
+		enum-name = "PWR_SLP_SUS";
+		gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	ec_soc_dsw_pwrok: pwr-ec-soc-dsw-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "DSW_PWROK output to PCH";
+		enum-name = "PWR_EC_SOC_DSW_PWROK";
+		gpios = <&gpio0 17 0>;
+		output;
+	};
+	pwr-vccst-pwrgd-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "VCCST_PWRGD output to PCH";
+		enum-name = "PWR_VCCST_PWRGD";
+		gpios = <&gpio0 18 0>;
+		output;
+	};
+	pwr-imvp9-vrrdy-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "VRRDY input from IMVP9";
+		enum-name = "PWR_IMVP9_VRRDY";
+		gpios = <&gpio0 19 0>;
+	};
+	pch_pwrok: pwr-pch-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PCH_PWROK output to PCH";
+		enum-name = "PWR_PCH_PWROK";
+		gpios = <&gpio0 20 0>;
+		output;
+	};
+	pwr-ec-pch-sys-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_PWROK output to PCH";
+		enum-name = "PWR_EC_PCH_SYS_PWROK";
+		gpios = <&gpio0 21 0>;
+		output;
+	};
+	pwr-sys-rst-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_RESET# output to PCH";
+		enum-name = "PWR_SYS_RST";
+		gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
+		output;
+	};
+	pwr-all-sys-pwrgd {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "all power good";
+		enum-name = "PWR_ALL_SYS_PWRGD";
+		gpios = <&gpio0 23 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+};
diff --git a/zephyr/test/rex/boards/native_posix.overlay b/zephyr/test/rex/boards/native_posix.overlay
new file mode 100644
index 0000000000..df9ec071d3
--- /dev/null
+++ b/zephyr/test/rex/boards/native_posix.overlay
@@ -0,0 +1,30 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <board-overlays/native_posix.dts>
+#include <dt-bindings/gpio_defines.h>
+
+/ {
+	/* GPIOs shared by all boards */
+	named-gpios {
+		compatible = "named-gpios";
+
+		gpio_usb_c1_rst_odl: usb_c1_rst_odl {
+			gpios = <&gpio0 1 GPIO_ODR_LOW>;
+		};
+		gpio_usb_c1_rt_int_odl: usb_c1_rt_int_odl {
+			gpios = <&gpio0 2 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_usb_c1_rt_rst_r_odl: usb_c1_rt_rst_r_odl {
+			gpios = <&gpio0 3 GPIO_ODR_HIGH>;
+		};
+		gpio_usb_c1_frs_en: usb_c1_frs_en {
+			gpios = <&gpio0 4 GPIO_ODR_HIGH>;
+		};
+		gpio_en_z1_rails: en_z1_rails {
+			gpios = <&gpio0 5 GPIO_OUTPUT>;
+		};
+	};
+};
diff --git a/zephyr/test/rex/boards/rex/rex.dtsi b/zephyr/test/rex/boards/rex/rex.dtsi
new file mode 100644
index 0000000000..cfdcfc887a
--- /dev/null
+++ b/zephyr/test/rex/boards/rex/rex.dtsi
@@ -0,0 +1,49 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "../native_posix.overlay"
+#include "../../../../program/rex/rex/cbi.dtsi"
+
+/ {
+	/* Unused Stub */
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		named_i2c0: i2c0 {
+			i2c-port = <&i2c0>;
+			enum-names = "I2C_PORT_USB_MUX";
+		};
+	};
+
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		usbc_port0: port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+		};
+		usbc_port1: port1@1 {
+			compatible = "named-usbc-port";
+			reg = <1>;
+		};
+	};
+
+	aliases {
+		kb-usb-c1-rst-odl = &gpio_usb_c1_rst_odl;
+		anx-usb-c1-rt-hpd-in = &gpio_usb_c1_rst_odl;
+
+		kb-usb-c1-dp-mode = &gpio_usb_c1_rt_int_odl;
+		anx-usb-c1-rt-dp-en = &gpio_usb_c1_rt_int_odl;
+
+		ps-usb-c1-rt-rst-odl = &gpio_usb_c1_rt_rst_r_odl;
+		kb-usb-c1-rt-rst-odl = &gpio_usb_c1_rt_rst_r_odl;
+		anx-usb-c1-rt-usb-en = &gpio_usb_c1_rt_rst_r_odl;
+
+		kb-usb-c1-frs-alert = &gpio_usb_c1_frs_en;
+		anx-usb-c1-frs-en = &gpio_usb_c1_frs_en;
+	};
+
+};
diff --git a/zephyr/test/rex/prj.conf b/zephyr/test/rex/prj.conf
new file mode 100644
index 0000000000..0fe26fc39e
--- /dev/null
+++ b/zephyr/test/rex/prj.conf
@@ -0,0 +1,19 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_ZTEST=y
+CONFIG_ZTEST_ASSERT_VERBOSE=1
+CONFIG_ZTEST_NEW_API=y
+CONFIG_ASSERT=y
+
+CONFIG_CROS_EC=y
+CONFIG_PLATFORM_EC=y
+
+CONFIG_LOG=y
+CONFIG_LOG_MODE_MINIMAL=y
+
+CONFIG_AP_X86_INTEL_MTL=y
+CONFIG_TEST_DISABLE_AP_PWRSEQ=y
+
+CONFIG_EMUL_COMMON_I2C=y
diff --git a/zephyr/test/rex/src/board_power.c b/zephyr/test/rex/src/board_power.c
new file mode 100644
index 0000000000..bb3729dc3b
--- /dev/null
+++ b/zephyr/test/rex/src/board_power.c
@@ -0,0 +1,213 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "gpio/gpio.h"
+#include "gpio_signal.h"
+#include "timer.h"
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/fff.h>
+#include <zephyr/ztest.h>
+
+#include <ap_power/ap_power.h>
+#include <ap_power/ap_power_events.h>
+#include <ap_power/ap_power_interface.h>
+#include <ap_power_override_functions.h>
+#include <mock/ap_power_events.h>
+#include <mock/power_signals.h>
+#include <power_signals.h>
+#include <x86_power_signals.h>
+
+#define X86_NON_DSX_MTL_FORCE_SHUTDOWN_TO_MS 50
+
+DEFINE_FAKE_VALUE_FUNC(int, power_signal_set, enum power_signal, int);
+DEFINE_FAKE_VALUE_FUNC(int, power_signal_get, enum power_signal);
+DEFINE_FAKE_VALUE_FUNC(int, power_wait_mask_signals_timeout,
+		       power_signal_mask_t, power_signal_mask_t, int);
+DEFINE_FAKE_VOID_FUNC(ap_power_ev_send_callbacks, enum ap_power_events);
+
+int mock_power_signal_set_ap_force_shutdown(enum power_signal signal, int value)
+{
+	if (power_signal_set_fake.call_count == 1) {
+		zassert_true(signal == PWR_EC_PCH_RSMRST && value == 0,
+			     "First call signal: %d, value: %d", signal, value);
+		return 0;
+	} else if (power_signal_set_fake.call_count == 2) {
+		zassert_true(signal == PWR_EN_PP3300_A && value == 0,
+			     "Second call signal: %d, value: %d", signal,
+			     value);
+		return 0;
+	}
+
+	zassert_unreachable("Wrong input received");
+	return -1;
+}
+
+int mock_power_signal_set_ap_power_action_g3_s5(enum power_signal signal,
+						int value)
+{
+	if ((signal == PWR_EN_PP3300_A) && (value == 1)) {
+		return 0;
+	}
+
+	zassert_unreachable("Wrong input received");
+	return -1;
+}
+
+int mock_power_signal_get_ap_force_shutdown_retries(enum power_signal signal)
+{
+	if (signal == PWR_RSMRST) {
+		return 1;
+	}
+	zassert_unreachable("Wrong input received");
+	return -1;
+}
+
+int mock_power_signal_get_ap_force_shutdown(enum power_signal signal)
+{
+	if (signal == PWR_RSMRST) {
+		if (power_signal_get_fake.call_count <= 5) {
+			return 1;
+		}
+		return 0;
+	}
+	zassert_unreachable("Wrong input received");
+	return -1;
+}
+
+int mock_power_signal_get_check_power_rails_enabled_0(enum power_signal signal)
+{
+	if (signal == PWR_EN_PP3300_A) {
+		return 0;
+	}
+	zassert_unreachable("Wrong input received");
+	return -1;
+}
+
+int mock_power_signal_get_check_power_rails_enabled_1(enum power_signal signal)
+{
+	if (signal == PWR_EN_PP3300_A) {
+		return 1;
+	}
+	zassert_unreachable("Wrong input received");
+	return -1;
+}
+
+int mock_power_wait_mask_signals_timeout_0(power_signal_mask_t want,
+					   power_signal_mask_t mask,
+					   int timeout)
+{
+	zassert_equal(want, IN_PGOOD_ALL_CORE);
+	zassert_equal(mask, IN_PGOOD_ALL_CORE);
+	zassert_equal(timeout, AP_PWRSEQ_DT_VALUE(wait_signal_timeout));
+	return 0;
+}
+
+int mock_power_wait_mask_signals_timeout_1(power_signal_mask_t want,
+					   power_signal_mask_t mask,
+					   int timeout)
+{
+	zassert_equal(want, IN_PGOOD_ALL_CORE);
+	zassert_equal(mask, IN_PGOOD_ALL_CORE);
+	zassert_equal(timeout, AP_PWRSEQ_DT_VALUE(wait_signal_timeout));
+	return 1;
+}
+
+void mock_ap_power_ev_send_callbacks(enum ap_power_events event)
+{
+	zassert_equal(event, AP_POWER_PRE_INIT);
+}
+
+static void board_power_before(void *fixture)
+{
+	ARG_UNUSED(fixture);
+	RESET_FAKE(power_signal_set);
+	RESET_FAKE(power_signal_get);
+	RESET_FAKE(power_wait_mask_signals_timeout);
+	RESET_FAKE(ap_power_ev_send_callbacks);
+}
+
+ZTEST_USER(board_power, test_board_ap_power_force_shutdown)
+{
+	power_signal_set_fake.custom_fake =
+		mock_power_signal_set_ap_force_shutdown;
+	power_signal_get_fake.custom_fake =
+		mock_power_signal_get_ap_force_shutdown;
+	board_ap_power_force_shutdown();
+
+	zassert_equal(2, power_signal_set_fake.call_count);
+	zassert_equal(7, power_signal_get_fake.call_count);
+}
+
+ZTEST_USER(board_power, test_board_ap_power_force_shutdown_timeout)
+{
+	power_signal_set_fake.custom_fake =
+		mock_power_signal_set_ap_force_shutdown;
+	power_signal_get_fake.custom_fake =
+		mock_power_signal_get_ap_force_shutdown_retries;
+
+	const uint32_t start_ms = k_uptime_get();
+
+	board_ap_power_force_shutdown();
+
+	const uint32_t end_ms = k_uptime_get();
+
+	zassert_equal(power_signal_set_fake.call_count, 2);
+	zassert_true((end_ms - start_ms) >=
+		     X86_NON_DSX_MTL_FORCE_SHUTDOWN_TO_MS);
+	zassert_true(power_signal_get_fake.call_count > 2);
+}
+
+ZTEST_USER(board_power, test_board_ap_power_check_power_rails_enabled_0)
+{
+	power_signal_get_fake.custom_fake =
+		mock_power_signal_get_check_power_rails_enabled_0;
+
+	zassert_equal(0, board_ap_power_check_power_rails_enabled());
+	zassert_equal(1, power_signal_get_fake.call_count);
+}
+
+ZTEST_USER(board_power, test_board_ap_power_check_power_rails_enabled_1)
+{
+	power_signal_get_fake.custom_fake =
+		mock_power_signal_get_check_power_rails_enabled_1;
+
+	zassert_equal(1, board_ap_power_check_power_rails_enabled());
+	zassert_equal(1, power_signal_get_fake.call_count);
+}
+
+ZTEST_USER(board_power, test_board_ap_power_action_g3_s5_0)
+{
+	power_signal_set_fake.custom_fake =
+		mock_power_signal_set_ap_power_action_g3_s5;
+	power_wait_mask_signals_timeout_fake.custom_fake =
+		mock_power_wait_mask_signals_timeout_0;
+	ap_power_ev_send_callbacks_fake.custom_fake =
+		mock_ap_power_ev_send_callbacks;
+
+	board_ap_power_action_g3_s5();
+
+	zassert_equal(1, power_signal_set_fake.call_count);
+	zassert_equal(1, power_wait_mask_signals_timeout_fake.call_count);
+	zassert_equal(1, ap_power_ev_send_callbacks_fake.call_count);
+}
+
+ZTEST_USER(board_power, test_board_ap_power_action_g3_s5_1)
+{
+	power_signal_set_fake.custom_fake =
+		mock_power_signal_set_ap_power_action_g3_s5;
+	power_wait_mask_signals_timeout_fake.custom_fake =
+		mock_power_wait_mask_signals_timeout_1;
+	ap_power_ev_send_callbacks_fake.custom_fake =
+		mock_ap_power_ev_send_callbacks;
+
+	board_ap_power_action_g3_s5();
+
+	zassert_equal(1, power_signal_set_fake.call_count);
+	zassert_equal(1, power_wait_mask_signals_timeout_fake.call_count);
+	zassert_equal(0, ap_power_ev_send_callbacks_fake.call_count);
+}
+
+ZTEST_SUITE(board_power, NULL, NULL, board_power_before, NULL, NULL);
diff --git a/zephyr/test/rex/src/usb_mux_config.c b/zephyr/test/rex/src/usb_mux_config.c
new file mode 100644
index 0000000000..2b86732bef
--- /dev/null
+++ b/zephyr/test/rex/src/usb_mux_config.c
@@ -0,0 +1,97 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cros_cbi.h"
+#include "hooks.h"
+#include "usb_mux.h"
+#include "usb_mux_config.h"
+#include "usbc/usb_muxes.h"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/fff.h>
+#include <zephyr/ztest.h>
+
+FAKE_VALUE_FUNC(int, cros_cbi_get_fw_config, enum cbi_fw_config_field_id,
+		uint32_t *);
+
+int mock_cros_cbi_get_fw_config(enum cbi_fw_config_field_id field_id,
+				uint32_t *value)
+{
+	*value = FW_USB_DB_USB3;
+	return 0;
+}
+
+int mock_cros_cbi_get_fw_config_anx7452(enum cbi_fw_config_field_id field_id,
+					uint32_t *value)
+{
+	*value = FW_USB_DB_USB4_ANX7452;
+	return 0;
+}
+
+int mock_cros_cbi_get_fw_config_no_usb_db(enum cbi_fw_config_field_id field_id,
+					  uint32_t *value)
+{
+	*value = FW_USB_DB_NOT_CONNECTED;
+	return 0;
+}
+
+int mock_cros_cbi_get_fw_config_error(enum cbi_fw_config_field_id field_id,
+				      uint32_t *value)
+{
+	*value = FW_USB_DB_NOT_CONNECTED;
+	return -1;
+}
+
+static void usb_mux_config_before(void *fixture)
+{
+	ARG_UNUSED(fixture);
+
+	RESET_FAKE(cros_cbi_get_fw_config);
+}
+
+ZTEST_USER(usb_mux_config, test_setup_usb_db)
+{
+	cros_cbi_get_fw_config_fake.custom_fake = mock_cros_cbi_get_fw_config;
+
+	hook_notify(HOOK_INIT);
+
+	zassert_equal(1, cros_cbi_get_fw_config_fake.call_count);
+	zassert_equal(1, usb_db_type);
+}
+
+ZTEST_USER(usb_mux_config, test_setup_usb_db_anx7452)
+{
+	cros_cbi_get_fw_config_fake.custom_fake =
+		mock_cros_cbi_get_fw_config_anx7452;
+
+	hook_notify(HOOK_INIT);
+
+	zassert_equal(1, cros_cbi_get_fw_config_fake.call_count);
+	zassert_equal(3, usb_db_type);
+}
+
+ZTEST_USER(usb_mux_config, test_setup_usb_db_no_usb_db)
+{
+	cros_cbi_get_fw_config_fake.custom_fake =
+		mock_cros_cbi_get_fw_config_no_usb_db;
+
+	hook_notify(HOOK_INIT);
+
+	zassert_equal(1, cros_cbi_get_fw_config_fake.call_count);
+	zassert_equal(0, usb_db_type);
+}
+
+ZTEST_USER(usb_mux_config, test_setup_usb_db_error_reading_cbi)
+{
+	cros_cbi_get_fw_config_fake.custom_fake =
+		mock_cros_cbi_get_fw_config_error;
+
+	hook_notify(HOOK_INIT);
+
+	zassert_equal(1, cros_cbi_get_fw_config_fake.call_count);
+	zassert_equal(0, usb_db_type);
+}
+
+ZTEST_SUITE(usb_mux_config, NULL, NULL, usb_mux_config_before, NULL, NULL);
diff --git a/zephyr/test/rex/src/usb_pd_policy.c b/zephyr/test/rex/src/usb_pd_policy.c
new file mode 100644
index 0000000000..5383ff12af
--- /dev/null
+++ b/zephyr/test/rex/src/usb_pd_policy.c
@@ -0,0 +1,225 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "chipset.h"
+#include "ec_commands.h"
+#include "usb_charge.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/fff.h>
+#include <zephyr/ztest.h>
+
+FAKE_VALUE_FUNC(int, chipset_in_state, int);
+FAKE_VALUE_FUNC(int, ppc_vbus_source_enable, int, int);
+FAKE_VOID_FUNC(pd_set_vbus_discharge, int, int);
+FAKE_VOID_FUNC(pd_send_host_event, int);
+FAKE_VALUE_FUNC(int, ppc_vbus_sink_enable, int, int);
+FAKE_VALUE_FUNC(int, ppc_is_sourcing_vbus, int);
+
+int ppc_vbus_source_enable_0_mock(int port, int enable)
+{
+	zassert_equal(0, pd_set_vbus_discharge_fake.call_count);
+	zassert_equal(0, pd_send_host_event_fake.call_count);
+	return (port == 0) && (enable == 0);
+}
+
+int ppc_vbus_source_enable_1_mock(int port, int enable)
+{
+	zassert_equal(1, enable, NULL);
+	switch (port) {
+	case 0:
+		return EC_SUCCESS;
+	case 3:
+		return EC_ERROR_UNIMPLEMENTED;
+	case 4:
+		return EC_ERROR_INVAL;
+	default:
+		zassert_unreachable("Unknown port");
+	}
+	return -1;
+}
+
+void pd_set_vbus_discharge_enable_0_mock(int port, int enable)
+{
+	zassert_equal(0, port, NULL);
+	zassert_equal(0, enable, NULL);
+}
+
+void pd_set_vbus_discharge_port_3_enable_0_mock(int port, int enable)
+{
+	zassert_equal(3, port, NULL);
+	zassert_equal(0, enable, NULL);
+}
+
+void pd_set_vbus_discharge_port_4_enable_0_mock(int port, int enable)
+{
+	zassert_equal(4, port, NULL);
+	zassert_equal(0, enable, NULL);
+}
+
+void pd_set_vbus_discharge_enable_1_mock(int port, int enable)
+{
+	zassert_equal(0, pd_send_host_event_fake.call_count);
+	zassert_equal(0, port, NULL);
+	zassert_equal(1, enable, NULL);
+}
+
+void pd_send_host_event_mock(int mask)
+{
+	zassert_equal(PD_EVENT_POWER_CHANGE, mask, NULL);
+}
+
+int ppc_is_sourcing_vbus_mock(int port)
+{
+	return port == 0;
+}
+
+int ppc_vbus_sink_enable_mock(int port, int enable)
+{
+	zassert_equal(0, enable, NULL);
+	switch (port) {
+	case 0:
+	case 3:
+	case 4:
+		return EC_SUCCESS;
+	case 1:
+		return EC_ERROR_UNIMPLEMENTED;
+	case 2:
+		return EC_ERROR_INVAL;
+	default:
+		zassert_unreachable("Unknown port");
+	}
+	return -1;
+}
+
+static void usb_pd_policy_before(void *fixture)
+{
+	ARG_UNUSED(fixture);
+	RESET_FAKE(chipset_in_state);
+	RESET_FAKE(ppc_vbus_source_enable);
+	RESET_FAKE(pd_set_vbus_discharge);
+	RESET_FAKE(pd_send_host_event);
+	RESET_FAKE(ppc_is_sourcing_vbus);
+	RESET_FAKE(ppc_vbus_sink_enable);
+}
+
+ZTEST_USER(usb_pd_policy, test_pd_check_vconn_swap)
+{
+	const struct gpio_dt_spec *const en_z1_rails =
+		GPIO_DT_FROM_NODELABEL(gpio_en_z1_rails);
+
+	/* AP 5V rail is off. */
+	zassert_false(gpio_pin_get_dt(en_z1_rails));
+	zassert_false(pd_check_vconn_swap(0));
+	zassert_false(pd_check_vconn_swap(1));
+
+	/*
+	 * Case with the rail on is untestable because emulated GPIOs don't
+	 * allow getting the current value of output pins.
+	 */
+}
+
+ZTEST_USER(usb_pd_policy, test_pd_power_supply_reset)
+{
+	ppc_vbus_source_enable_fake.custom_fake = ppc_vbus_source_enable_0_mock;
+	pd_set_vbus_discharge_fake.custom_fake =
+		pd_set_vbus_discharge_enable_1_mock;
+	pd_send_host_event_fake.custom_fake = pd_send_host_event_mock;
+	pd_power_supply_reset(0);
+	zassert_equal(1, ppc_vbus_source_enable_fake.call_count);
+	zassert_equal(1, pd_set_vbus_discharge_fake.call_count);
+	zassert_equal(1, pd_send_host_event_fake.call_count);
+}
+
+ZTEST_USER(usb_pd_policy, test_pd_set_power_supply_ready_case_0)
+{
+	ppc_vbus_sink_enable_fake.custom_fake = ppc_vbus_sink_enable_mock;
+	pd_set_vbus_discharge_fake.custom_fake =
+		pd_set_vbus_discharge_enable_0_mock;
+	ppc_vbus_source_enable_fake.custom_fake = ppc_vbus_source_enable_1_mock;
+	pd_send_host_event_fake.custom_fake = pd_send_host_event_mock;
+	zassert_equal(EC_SUCCESS, pd_set_power_supply_ready(0), NULL);
+	zassert_equal(1, ppc_vbus_sink_enable_fake.call_count);
+	zassert_equal(1, pd_set_vbus_discharge_fake.call_count);
+	zassert_equal(1, ppc_vbus_source_enable_fake.call_count);
+	zassert_equal(1, pd_send_host_event_fake.call_count);
+}
+
+ZTEST_USER(usb_pd_policy, test_pd_set_power_supply_ready_case_1)
+{
+	ppc_vbus_sink_enable_fake.custom_fake = ppc_vbus_sink_enable_mock;
+	pd_set_vbus_discharge_fake.custom_fake =
+		pd_set_vbus_discharge_enable_0_mock;
+	ppc_vbus_source_enable_fake.custom_fake = ppc_vbus_source_enable_1_mock;
+	pd_send_host_event_fake.custom_fake = pd_send_host_event_mock;
+	zassert_equal(EC_ERROR_UNIMPLEMENTED, pd_set_power_supply_ready(1),
+		      NULL);
+	zassert_equal(1, ppc_vbus_sink_enable_fake.call_count);
+	zassert_equal(0, pd_set_vbus_discharge_fake.call_count);
+	zassert_equal(0, ppc_vbus_source_enable_fake.call_count);
+	zassert_equal(0, pd_send_host_event_fake.call_count);
+}
+
+ZTEST_USER(usb_pd_policy, test_pd_set_power_supply_ready_case_2)
+{
+	ppc_vbus_sink_enable_fake.custom_fake = ppc_vbus_sink_enable_mock;
+	pd_set_vbus_discharge_fake.custom_fake =
+		pd_set_vbus_discharge_enable_0_mock;
+	ppc_vbus_source_enable_fake.custom_fake = ppc_vbus_source_enable_1_mock;
+	pd_send_host_event_fake.custom_fake = pd_send_host_event_mock;
+	zassert_equal(EC_ERROR_INVAL, pd_set_power_supply_ready(2), NULL);
+	zassert_equal(1, ppc_vbus_sink_enable_fake.call_count);
+	zassert_equal(0, pd_set_vbus_discharge_fake.call_count);
+	zassert_equal(0, ppc_vbus_source_enable_fake.call_count);
+	zassert_equal(0, pd_send_host_event_fake.call_count);
+}
+
+ZTEST_USER(usb_pd_policy, test_pd_set_power_supply_ready_case_3)
+{
+	ppc_vbus_sink_enable_fake.custom_fake = ppc_vbus_sink_enable_mock;
+	pd_set_vbus_discharge_fake.custom_fake =
+		pd_set_vbus_discharge_port_3_enable_0_mock;
+	ppc_vbus_source_enable_fake.custom_fake = ppc_vbus_source_enable_1_mock;
+	pd_send_host_event_fake.custom_fake = pd_send_host_event_mock;
+	zassert_equal(EC_ERROR_UNIMPLEMENTED, pd_set_power_supply_ready(3),
+		      NULL);
+	zassert_equal(1, ppc_vbus_sink_enable_fake.call_count);
+	zassert_equal(1, pd_set_vbus_discharge_fake.call_count);
+	zassert_equal(1, ppc_vbus_source_enable_fake.call_count);
+	zassert_equal(0, pd_send_host_event_fake.call_count);
+}
+
+ZTEST_USER(usb_pd_policy, test_pd_set_power_supply_ready_case_4)
+{
+	ppc_vbus_sink_enable_fake.custom_fake = ppc_vbus_sink_enable_mock;
+	pd_set_vbus_discharge_fake.custom_fake =
+		pd_set_vbus_discharge_port_4_enable_0_mock;
+	ppc_vbus_source_enable_fake.custom_fake = ppc_vbus_source_enable_1_mock;
+	pd_send_host_event_fake.custom_fake = pd_send_host_event_mock;
+	zassert_equal(EC_ERROR_INVAL, pd_set_power_supply_ready(4), NULL);
+	zassert_equal(1, ppc_vbus_sink_enable_fake.call_count);
+	zassert_equal(1, pd_set_vbus_discharge_fake.call_count);
+	zassert_equal(1, ppc_vbus_source_enable_fake.call_count);
+	zassert_equal(0, pd_send_host_event_fake.call_count);
+}
+
+ZTEST_USER(usb_pd_policy, test_board_vbus_source_enabled)
+{
+	ppc_is_sourcing_vbus_fake.custom_fake = ppc_is_sourcing_vbus_mock;
+	zassert_true(board_vbus_source_enabled(0), NULL, NULL);
+	zassert_equal(1, ppc_is_sourcing_vbus_fake.call_count);
+}
+
+ZTEST_USER(usb_pd_policy, test_board_is_sourcing_vbus)
+{
+	ppc_is_sourcing_vbus_fake.custom_fake = ppc_is_sourcing_vbus_mock;
+	zassert_true(board_is_sourcing_vbus(0), NULL, NULL);
+	zassert_equal(1, ppc_is_sourcing_vbus_fake.call_count);
+}
+
+ZTEST_SUITE(usb_pd_policy, NULL, NULL, usb_pd_policy_before, NULL, NULL);
diff --git a/zephyr/test/rex/testcase.yaml b/zephyr/test/rex/testcase.yaml
new file mode 100644
index 0000000000..06ee29982a
--- /dev/null
+++ b/zephyr/test/rex/testcase.yaml
@@ -0,0 +1,30 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+common:
+  platform_allow: native_posix
+tests:
+  rex.usb_pd_policy:
+    extra_dtc_overlay_files:
+      - boards/native_posix.overlay
+    extra_configs:
+      - CONFIG_TEST_USB_PD_POLICY=y
+      - CONFIG_TEST_ENABLE_USB_PD_DISCHARGE=y
+      - CONFIG_TEST_ENABLE_USB_PD_HOST_CMD=y
+
+  rex.board_power:
+    extra_dtc_overlay_files:
+      - board_power.dtsi
+    extra_configs:
+      - CONFIG_TEST_BOARD_POWER=y
+      - CONFIG_TEST_X86_NON_DSX_PWRSEQ_MTL=y
+      - CONFIG_AP_POWER_EVENTS_MOCK=y
+      - CONFIG_POWER_SIGNALS_MOCK=y
+      - CONFIG_AP_EVENTS=n
+
+  rex.rex.usb_mux_config:
+    extra_dtc_overlay_files:
+      - boards/rex/rex.dtsi
+    extra_configs:
+      - CONFIG_TEST_BOARD_USB_MUX_CONFIG=y
diff --git a/zephyr/test/shared_mem/CMakeLists.txt b/zephyr/test/shared_mem/CMakeLists.txt
new file mode 100644
index 0000000000..bb9dd7554c
--- /dev/null
+++ b/zephyr/test/shared_mem/CMakeLists.txt
@@ -0,0 +1,9 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(shared_mem)
+target_sources(app PRIVATE main.c)
+
diff --git a/zephyr/test/shared_mem/boards/native_posix.overlay b/zephyr/test/shared_mem/boards/native_posix.overlay
new file mode 100644
index 0000000000..17890e69f8
--- /dev/null
+++ b/zephyr/test/shared_mem/boards/native_posix.overlay
@@ -0,0 +1,6 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <board-overlays/native_posix.dts>
diff --git a/zephyr/test/shared_mem/main.c b/zephyr/test/shared_mem/main.c
new file mode 100644
index 0000000000..7080d87243
--- /dev/null
+++ b/zephyr/test/shared_mem/main.c
@@ -0,0 +1,15 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "shared_mem.h"
+
+#include <zephyr/ztest_test_new.h>
+
+ZTEST_SUITE(shared_mem, NULL, NULL, NULL, NULL, NULL);
+
+ZTEST(shared_mem, test_release_null)
+{
+	/* This should be a no-op. We can't do much to test it directly. */
+	shared_mem_release(NULL);
+}
diff --git a/zephyr/test/shared_mem/prj.conf b/zephyr/test/shared_mem/prj.conf
new file mode 100644
index 0000000000..27ab16fcb2
--- /dev/null
+++ b/zephyr/test/shared_mem/prj.conf
@@ -0,0 +1,8 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_ZTEST=y
+CONFIG_ZTEST_NEW_API=y
+CONFIG_PLATFORM_EC=y
+CONFIG_CROS_EC=y
diff --git a/zephyr/test/shared_mem/testcase.yaml b/zephyr/test/shared_mem/testcase.yaml
new file mode 100644
index 0000000000..59f050e197
--- /dev/null
+++ b/zephyr/test/shared_mem/testcase.yaml
@@ -0,0 +1,4 @@
+common:
+  platform_allow: native_posix
+tests:
+  shared_mem.default: {}
diff --git a/zephyr/test/skyrim/CMakeLists.txt b/zephyr/test/skyrim/CMakeLists.txt
new file mode 100644
index 0000000000..e7a3c4fdb3
--- /dev/null
+++ b/zephyr/test/skyrim/CMakeLists.txt
@@ -0,0 +1,19 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(skyrim)
+
+zephyr_include_directories("${PLATFORM_EC_PROGRAM_DIR}/skyrim/include")
+
+add_subdirectory(${PLATFORM_EC}/zephyr/test/test_utils test_utils)
+
+add_subdirectory(tests/common)
+add_subdirectory_ifdef(CONFIG_TEST_BOARD_BASEBOARD tests/baseboard)
+add_subdirectory_ifdef(CONFIG_TEST_BOARD_CRYSTALDRIFT tests/crystaldrift)
+add_subdirectory_ifdef(CONFIG_TEST_BOARD_FROSTFLOW tests/frostflow)
+add_subdirectory_ifdef(CONFIG_TEST_BOARD_MARKARTH tests/markarth)
+add_subdirectory_ifdef(CONFIG_TEST_BOARD_SKYRIM tests/skyrim)
+add_subdirectory_ifdef(CONFIG_TEST_BOARD_WINTERHOLD tests/winterhold)
diff --git a/zephyr/test/skyrim/Kconfig b/zephyr/test/skyrim/Kconfig
new file mode 100644
index 0000000000..ca6c1d5e21
--- /dev/null
+++ b/zephyr/test/skyrim/Kconfig
@@ -0,0 +1,120 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+choice TEST_BOARD_VARIANT
+	prompt "Select board variant for tests"
+	help
+	  Board variant to use for tests
+
+	config TEST_BOARD_BASEBOARD
+		bool "Enable baseboard-specific tests"
+		help
+		Enable baseboard tests.
+
+	config TEST_BOARD_CRYSTALDRIFT
+		bool "Enable crystaldrift-specific tests"
+		help
+		Enable tests for crystaldrift variant.
+
+	config TEST_BOARD_FROSTFLOW
+		bool "Enable frostflow-specific tests"
+		help
+		Enable tests for frostflow variant.
+
+	config TEST_BOARD_MARKARTH
+		bool "Enable markarth-specific tests"
+		help
+		Enable tests for markarth variant.
+
+	config TEST_BOARD_SKYRIM
+		bool "Enable skyrim-specific tests"
+		help
+		Enable tests for skyrim variant.
+
+	config TEST_BOARD_WINTERHOLD
+		bool "Enable winterhold-specific tests"
+		help
+		Enable tests for winterhold variant.
+
+endchoice # TEST_BOARD_VARIANT
+
+config TEST_BOARD_NAME
+	string "Board name"
+	default "baseboard" if TEST_BOARD_BASEBOARD
+	default "crystaldrift" if TEST_BOARD_CRYSTALDRIFT
+	default "frostflow" if TEST_BOARD_FROSTFLOW
+	default "markarth" if TEST_BOARD_MARKARTH
+	default "skyrim" if TEST_BOARD_SKYRIM
+	default "winterhold" if TEST_BOARD_WINTERHOLD
+
+config TEST_BOARD_ALT_CHARGER
+	bool "Enable alt charger specific tests"
+
+config TEST_BOARD_ALT_CHARGER_CUSTOM
+	bool "ENable alt charger tests with a variant-specific test file"
+	select TEST_BOARD_ALT_CHARGER
+
+config TEST_BOARD_FAN
+	bool "Enable fan tests"
+
+config TEST_BOARD_FAN_CUSTOM
+	bool "ENable fan tests with a variant-specific test file"
+	select TEST_BOARD_FAN
+
+config TEST_BOARD_FORM_FACTOR
+	select PLATFORM_EC_DYNAMIC_MOTION_SENSOR_COUNT
+	select PLATFORM_EC_GMR_TABLET_MODE
+	select PLATFORM_EC_TABLET_MODE
+	bool "Run the tests intended for form factor testing"
+	help
+	  Include tests which checks accelerometer
+	  interrupt and tablet mode.
+
+config TEST_BOARD_USB_PD_POLICY
+	bool "Enable USB PD policy specific tests"
+	select TEST_ENABLE_USB_PD_HOST_CMD
+
+config TEST_BOARD_POWER_SIGNALS
+	bool "Enable power signals tests"
+	select AP_POWER_CONTROL
+	select BOARD_USB_HUB_RESET
+
+config TEST_BOARD_PPC_CONFIG
+	bool "Enable PPC config tests"
+
+config TEST_BOARD_PPC_CONFIG_CUSTOM
+	bool "ENable PPC config tests with a variant-specific test file"
+	select TEST_BOARD_PPC_CONFIG
+
+config TEST_BOARD_USB_MUX_CONFIG
+	bool "Enable USB mux config tests"
+	select AP_POWER_CONTROL
+	select PLATFORM_EC_USB_MUX_MOCK
+	select PLATFORM_EC_USBC_RETIMER_PS8811
+	select PLATFORM_EC_USB_MUX_RUNTIME_CONFIG
+
+config TEST_BOARD_USB_MUX_CONFIG_CUSTOM
+	bool "Enable USB mux config tests with a variant-specific test file"
+	select TEST_BOARD_USB_MUX_CONFIG
+
+config SKYRIM_LOG_LEVEL
+	int "Fake config to allow building"
+	default 4 # Log level debug by default
+
+config AP_POWER_CONTROL
+	bool "Fake config to enable this feature"
+
+config TEST_ENABLE_USB_PD_HOST_CMD
+	bool "Fake config to enable this feature"
+
+config USB_PD_DISCHARGE
+	bool "Fake config to enable this feature"
+
+config PLATFORM_EC_USB_MUX_RUNTIME_CONFIG
+	bool "Fake config to enable this feature"
+
+config BOARD_USB_HUB_RESET
+	bool "Fake config to enable this feature"
+
+source "Kconfig.zephyr"
diff --git a/zephyr/test/skyrim/boards/native_posix.overlay b/zephyr/test/skyrim/boards/native_posix.overlay
new file mode 100644
index 0000000000..84a9698770
--- /dev/null
+++ b/zephyr/test/skyrim/boards/native_posix.overlay
@@ -0,0 +1,403 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <board-overlays/native_posix.dts>
+#include <dt-bindings/gpio_defines.h>
+
+/ {
+	/* GPIOs shared by all boards */
+	named-gpios {
+		compatible = "named-gpios";
+
+		gpio_pg_pwr_s5: pg_pwr_s5 {
+			gpios = <&gpio0 0 GPIO_INPUT>;
+			enum-name = "GPIO_S5_PGOOD";
+		};
+
+		gpio_usb_c0_tcpc_fastsw_ctl_en: usb_c0_tcpc_fastsw_ctl_en {
+			gpios = <&gpio0 1 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C0_TCPC_FASTSW_CTL_EN";
+		};
+
+		gpio_usb_c1_tcpc_fastsw_ctl_en: usb_c1_tcpc_fastsw_ctl_en {
+			gpios = <&gpio0 2 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C1_TCPC_FASTSW_CTL_EN";
+		};
+
+		gpio_usb_c0_ppc_int_odl: usb_c0_ppc_int_odl {
+			gpios = <&gpio0 3 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C0_PPC_INT_ODL";
+		};
+		gpio_usb_c1_ppc_int_odl: usb_c1_ppc_int_odl {
+			gpios = <&gpio0 4 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C1_PPC_INT_ODL";
+		};
+
+		ioex_usb_c0_ilim_3a_en: usb_c0_ppc_ilim_3a_en {
+			gpios = <&gpio0 5 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C0_PPC_ILIM_3A_EN";
+		};
+
+		gpio_usb_c1_in_hpd: usb_c1_in_hpd {
+			gpios = <&gpio0 6 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C1_HPD_IN_DB";
+		};
+
+		ioex_usb_c1_sbu_flip: usb_c1_sbu_flip {
+			gpios = <&gpio0 7 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C1_SBU_FLIP";
+		};
+
+		ioex_usb_c0_sbu_flip: usb_c0_sbu_flip {
+			gpios = <&gpio0 8 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C0_SBU_FLIP";
+		};
+
+		gpio_accel_gyro_int_l: accel_gyro_int_l {
+			gpios = <&gpio0 9 GPIO_INPUT>;
+		};
+
+		gpio_lid_accel_int_l: lid_accel_int_l {
+			gpios = <&gpio0 10 GPIO_INPUT>;
+		};
+
+		tablet_mode_l: tablet_mode_l {
+			gpios = <&gpio0 11 GPIO_INPUT>;
+			enum-name = "GPIO_TABLET_MODE_L";
+		};
+
+		/* Power signals */
+		usb_a1_retimer_en: usb_a1_retimer_en {
+			gpios = <&gpio0 12 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_A1_RETIMER_EN";
+		};
+
+		gpio_ec_disable_disp_bl: ec_disable_disp_bl {
+			gpios = <&gpio0 13 GPIO_OUTPUT_HIGH>;
+			enum-name = "GPIO_ENABLE_BACKLIGHT_L";
+		};
+
+		gpio_slp_s3_l: slp_s3_l {
+			gpios = <&gpio0 14 GPIO_INPUT>;
+			enum-name = "GPIO_PCH_SLP_S3_L";
+			alias = "GPIO_PCH_SLP_S0_L";
+		};
+
+		gpio_slp_s5_l: slp_s5_l {
+			gpios = <&gpio0 15 GPIO_INPUT>;
+			enum-name = "GPIO_PCH_SLP_S5_L";
+		};
+
+		gpio_s0_pgood: pg_pcore_s0_r_od {
+			gpios = <&gpio0 16 GPIO_INPUT>;
+			enum-name = "GPIO_S0_PGOOD";
+		};
+
+		gpio_prochot_odl: prochot_odl {
+			gpios = <&gpio0 17 GPIO_INPUT>;
+			enum-name = "GPIO_CPU_PROCHOT";
+		};
+
+		gpio_pg_lpddr5_s0_od: pg_lpddr5_s0_od {
+			gpios = <&gpio0 18 GPIO_INPUT>;
+		};
+
+		gpio_pg_lpddr5_s3_od: pg_lpddr5_s3_od {
+			gpios = <&gpio0 19 GPIO_INPUT>;
+		};
+
+		gpio_en_pwr_s3: en_pwr_s3 {
+			gpios = <&gpio0 20 GPIO_OUTPUT_LOW>;
+		};
+
+		gpio_en_pwr_s0_r: en_pwr_s0_r {
+			/*
+			 * Needs to be configured as I/O to allow tested code to
+			 * read this pin.
+			 */
+			gpios = <&gpio0 21 (GPIO_OUTPUT_LOW | GPIO_INPUT)>;
+		};
+
+		gpio_pg_groupc_s0_od: pg_groupc_s0_od {
+			gpios = <&gpio0 22 GPIO_INPUT>;
+		};
+
+		gpio_en_pwr_pcore_s0_r: en_pwr_pcore_s0_r {
+			/*
+			 * Needs to be configured as I/O to allow tested code to
+			 * read this pin.
+			 */
+			gpios = <&gpio0 23 (GPIO_OUTPUT_LOW | GPIO_INPUT)>;
+		};
+
+		gpio_pcore_ocp_r_l: pcore_ocp_r_l {
+			gpios = <&gpio0 24 GPIO_INPUT>;
+		};
+
+		/* STB dumping GPIOs */
+		gpio_ec_sfh_int_h: ec_sfh_int_h {
+			gpios = <&gpio0 25 GPIO_OUTPUT_LOW>;
+		};
+		gpio_sfh_ec_int_h: sfh_ec_int_h {
+			gpios = <&gpio0 26 GPIO_INPUT>;
+		};
+
+		gpio_ec_soc_pwr_good: ec_soc_pwr_good {
+			gpios = <&gpio0 27 GPIO_OUTPUT_LOW>;
+		};
+
+		gpio_ec_soc_pwr_btn_l: ec_soc_pwr_btn_l {
+			gpios = <&gpio0 28 GPIO_OUTPUT_HIGH>;
+			enum-name = "GPIO_PCH_PWRBTN_L";
+		};
+
+		gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l {
+			/*
+			 * Needs to be configured as I/O to allow tested code to
+			 * read this pin.
+			 */
+			gpios = <&gpio0 29 (GPIO_OUTPUT_LOW | GPIO_INPUT)>;
+			enum-name = "GPIO_PCH_RSMRST_L";
+		};
+
+		gpio_soc_thermtrip_odl: soc_thermtrip_odl {
+			gpios = <&gpio0 30 GPIO_INPUT>;
+		};
+
+		gpio_hub_rst: hub_rst {
+			gpios = <&gpio0 31 GPIO_OUTPUT_HIGH>;
+		};
+	};
+
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_accel_gyro: accel_gyro {
+			irq-pin = <&gpio_accel_gyro_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "bmi3xx_interrupt";
+		};
+
+		int_lid_accel: lid_accel {
+			irq-pin = <&gpio_lid_accel_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "bma4xx_interrupt";
+		};
+
+		int_pg_groupc_s0: pg_groupc_s0 {
+			irq-pin = <&gpio_pg_groupc_s0_od>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_interrupt_handler";
+		};
+
+		int_pg_lpddr_s0: pg_lpddr_s0 {
+			irq-pin = <&gpio_pg_lpddr5_s0_od>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_interrupt_handler";
+		};
+
+		int_pg_lpddr_s3: pg_lpddr_s3 {
+			irq-pin = <&gpio_pg_lpddr5_s3_od>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_interrupt_handler";
+		};
+
+		int_prochot: prochot {
+			irq-pin = <&gpio_prochot_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "throttle_ap_prochot_input_interrupt";
+		};
+
+		int_soc_pcore_ocp: soc_pcore_ocp {
+			irq-pin = <&gpio_pcore_ocp_r_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "baseboard_soc_pcore_ocp";
+		};
+
+		int_soc_thermtrip: soc_thermtrip {
+			irq-pin = <&gpio_soc_thermtrip_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "baseboard_soc_thermtrip";
+		};
+
+		int_stb_dump: stb_dump {
+			irq-pin = <&gpio_sfh_ec_int_h>;
+			flags = <GPIO_INT_EDGE_RISING>;
+			handler = "power_interrupt_handler";
+		};
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		i2c_tcpc0: tcpc0 {
+			i2c-port = <&i2c0_0>;
+			enum-names = "I2C_PORT_TCPC0";
+		};
+
+		i2c_tcpc1: tcpc1 {
+			i2c-port = <&i2c1_0>;
+			enum-names = "I2C_PORT_TCPC1";
+		};
+
+		i2c_sensor: sensor {
+			i2c-port = <&i2c6_1>;
+			enum-names = "I2C_PORT_SENSOR";
+		};
+	};
+
+	i2c0_0: i2c@400 {
+		status = "okay";
+		compatible = "zephyr,i2c-emul-controller";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x400 4>;
+
+		anx7483_port0: anx7483_emul0@3e {
+			compatible = "cros,anx7483-emul", "analogix,anx7483";
+			reg = <0x3e>;
+			board-set = "board_anx7483_c0_mux_set";
+		};
+	};
+
+	i2c1_0: i2c@500 {
+		status = "okay";
+		compatible = "zephyr,i2c-emul-controller";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x500 4>;
+
+		anx7483_port1: anx7483_emul1@3e {
+			compatible = "cros,anx7483-emul", "analogix,anx7483";
+			reg = <0x3e>;
+			board-set = "board_anx7483_c1_mux_set";
+		};
+
+		ps8811_port1: ps8811_emul@72 {
+			compatible = "cros,ps8811-emul";
+			reg = <0x72>;
+		};
+	};
+
+	i2c6_1: i2c@600 {
+		status = "okay";
+		compatible = "zephyr,i2c-emul-controller";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x600 4>;
+	};
+
+	skyrim-fw-config {
+		compatible = "cros-ec,cbi-fw-config";
+
+		form-factor {
+			enum-name = "FW_FORM_FACTOR";
+			start = <0>;
+			size = <1>;
+
+			ff-clamshell {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FF_CLAMSHELL";
+				value = <0>;
+			};
+			ff-convertible {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FF_CONVERTIBLE";
+				value = <1>;
+				default;
+			};
+		};
+
+		io-db {
+			enum-name = "FW_IO_DB";
+			start = <6>;
+			size = <2>;
+
+			io-db-ps8811-ps8818 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_IO_DB_PS8811_PS8818";
+				value = <0>;
+			};
+			io-db-none-anx7483 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_IO_DB_NONE_ANX7483";
+				value = <1>;
+				default;
+			};
+		};
+
+		fan {
+			enum-name = "FW_FAN";
+			start = <10>;
+			size = <1>;
+
+			no-fan {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FAN_NOT_PRESENT";
+				value = <0>;
+			};
+			fan-present {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FAN_PRESENT";
+				value = <1>;
+				/*
+				 * Set as default so that unprovisioned
+				 * configs will run the fan regardless.
+				 */
+				default;
+			};
+		};
+
+		charger-option {
+			enum-name = "FW_CHARGER";
+			start = <11>;
+			size = <2>;
+
+			charger-option-isl9241 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_CHARGER_ISL9241";
+				value = <0>;
+				default;
+			};
+			charger-option-isl9538 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_CHARGER_ISL9538";
+				value = <1>;
+			};
+		};
+	};
+
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		usbc_port0: port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&anx7483_port0>;
+			};
+		};
+
+		usbc_port1: port1@1 {
+			compatible = "named-usbc-port";
+			reg = <1>;
+
+			usb-mux-chain-1-anx {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&anx7483_port1>;
+			};
+		};
+	};
+};
+
+&gpio0 {
+	ngpios = <32>;
+};
diff --git a/zephyr/test/skyrim/boards/skyrim/skyrim.dtsi b/zephyr/test/skyrim/boards/skyrim/skyrim.dtsi
new file mode 100644
index 0000000000..e5f846c3ce
--- /dev/null
+++ b/zephyr/test/skyrim/boards/skyrim/skyrim.dtsi
@@ -0,0 +1,30 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "../native_posix.overlay"
+#include "../../../../program/skyrim/skyrim/motionsense.dtsi"
+
+/ {
+	/* Rotation matrices for motion sensors. */
+	motionsense-rotation-ref {
+		compatible = "cros-ec,motionsense-rotation-ref";
+		lid_rot_ref: lid-rotation-ref {
+			mat33 = <0 (-1) 0
+				 1 0 0
+				 0 0 1>;
+		};
+
+		lid_rot_ref1: lid-rotation-ref1 {
+			mat33 = <0 1 0
+				 (-1) 0 0
+				 0 0 1>;
+		};
+
+		base_rot_ref: base-rotation-ref {
+			mat33 = <0 1 0
+				 (-1) 0 0
+				 0 0 1>;
+		};
+	};
+};
diff --git a/zephyr/test/skyrim/prj.conf b/zephyr/test/skyrim/prj.conf
new file mode 100644
index 0000000000..a20cf94249
--- /dev/null
+++ b/zephyr/test/skyrim/prj.conf
@@ -0,0 +1,19 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_ZTEST=y
+CONFIG_ZTEST_ASSERT_VERBOSE=1
+CONFIG_ZTEST_NEW_API=y
+CONFIG_ASSERT=y
+
+CONFIG_PLATFORM_EC_CBI=y
+CONFIG_CROS_EC=y
+CONFIG_PLATFORM_EC=y
+CONFIG_PLATFORM_EC_HOOKS=y
+CONFIG_TEST_DISABLE_PLATFORM_EC_USBC=y
+CONFIG_EMUL=y
+CONFIG_GPIO=y
+CONFIG_EMUL_COMMON_I2C=y
+
+CONFIG_AP_X86_AMD=y
diff --git a/zephyr/test/skyrim/testcase.yaml b/zephyr/test/skyrim/testcase.yaml
new file mode 100644
index 0000000000..1dfae464cf
--- /dev/null
+++ b/zephyr/test/skyrim/testcase.yaml
@@ -0,0 +1,134 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+common:
+  platform_allow: native_posix
+tests:
+  # Baseboard tests TEST_BOARD_POWER_SIGNALS
+  skyrim.baseboard:
+    extra_configs:
+    - CONFIG_TEST_BOARD_BASEBOARD=y
+
+  skyrim.baseboard.power_signals:
+    extra_configs:
+    - CONFIG_TEST_BOARD_BASEBOARD=y
+    - CONFIG_TEST_BOARD_POWER_SIGNALS=y
+    - CONFIG_PLATFORM_EC_AMD_STB_DUMP=y
+    - CONFIG_PLATFORM_EC_THROTTLE_AP=y
+    - CONFIG_PLATFORM_EC_THROTTLE_AP_NO_FAN=y
+    - CONFIG_PLATFORM_EC_THROTTLE_AP_SINGLE_PIN=y
+
+  skyrim.baseboard.usb_pd_policy:
+    extra_configs:
+    - CONFIG_TEST_BOARD_BASEBOARD=y
+    - CONFIG_TEST_BOARD_USB_PD_POLICY=y
+
+  skyrim.baseboard.usb_pd_policy.discharge:
+    extra_configs:
+    - CONFIG_TEST_BOARD_BASEBOARD=y
+    - CONFIG_TEST_BOARD_USB_PD_POLICY=y
+    - CONFIG_USB_PD_DISCHARGE=y
+
+  # Crystaldrift tests
+  skyrim.crystaldrift:
+    extra_configs:
+    - CONFIG_TEST_BOARD_CRYSTALDRIFT=y
+
+  skyrim.crystaldrift.fan:
+    extra_configs:
+    - CONFIG_TEST_BOARD_CRYSTALDRIFT=y
+    - CONFIG_TEST_BOARD_FAN=y
+
+  skyrim.crystaldrift.ppc_config:
+    extra_configs:
+    - CONFIG_TEST_BOARD_CRYSTALDRIFT=y
+    - CONFIG_TEST_BOARD_PPC_CONFIG_CUSTOM=y
+
+  skyrim.crystaldrift.usb_mux_config:
+    extra_configs:
+    - CONFIG_TEST_BOARD_CRYSTALDRIFT=y
+    - CONFIG_TEST_BOARD_USB_MUX_CONFIG_CUSTOM=y
+
+  # Frostflow tests
+  skyrim.frostflow:
+    extra_configs:
+    - CONFIG_TEST_BOARD_FROSTFLOW=y
+
+  skyrim.frostflow.ppc_config:
+    extra_configs:
+    - CONFIG_TEST_BOARD_FROSTFLOW=y
+    - CONFIG_TEST_BOARD_PPC_CONFIG=y
+
+  skyrim.frostflow.usb_mux_config:
+    extra_configs:
+    - CONFIG_TEST_BOARD_FROSTFLOW=y
+    - CONFIG_TEST_BOARD_USB_MUX_CONFIG_CUSTOM=y
+
+  # Markarth tests
+  skyrim.markarth:
+    extra_configs:
+    - CONFIG_TEST_BOARD_MARKARTH=y
+
+  skyrim.markarth.ppc_config:
+    extra_configs:
+    - CONFIG_TEST_BOARD_MARKARTH=y
+    - CONFIG_TEST_BOARD_PPC_CONFIG=y
+
+  skyrim.markarth.usb_mux_config:
+    extra_configs:
+    - CONFIG_TEST_BOARD_MARKARTH=y
+    - CONFIG_TEST_BOARD_USB_MUX_CONFIG_CUSTOM=y
+
+  # Skyrim tests
+  skyrim.skyrim:
+    extra_configs:
+    - CONFIG_TEST_BOARD_SKYRIM=y
+
+  skyrim.skyrim.alt_charger:
+    extra_configs:
+    - CONFIG_TEST_BOARD_SKYRIM=y
+    - CONFIG_TEST_BOARD_ALT_CHARGER=y
+
+  skyrim.skyrim.fan:
+    extra_configs:
+    - CONFIG_TEST_BOARD_SKYRIM=y
+    - CONFIG_TEST_BOARD_FAN=y
+
+  skyrim.skyrim.form_factor:
+    extra_configs:
+    - CONFIG_TEST_BOARD_SKYRIM=y
+    - CONFIG_TEST_BOARD_FORM_FACTOR=y
+    extra_dtc_overlay_files:
+    - ./boards/skyrim/skyrim.dtsi
+
+  skyrim.skyrim.ppc_config:
+    extra_configs:
+    - CONFIG_TEST_BOARD_SKYRIM=y
+    - CONFIG_TEST_BOARD_PPC_CONFIG=y
+
+  skyrim.skyrim.usb_mux_config:
+    extra_configs:
+    - CONFIG_TEST_BOARD_SKYRIM=y
+    - CONFIG_TEST_BOARD_USB_MUX_CONFIG_CUSTOM=y
+
+  # Winterhold tests
+  skyrim.winterhold:
+    extra_configs:
+    - CONFIG_TEST_BOARD_WINTERHOLD=y
+
+  skyrim.winterhold.ppc_config:
+    extra_configs:
+    - CONFIG_TEST_BOARD_WINTERHOLD=y
+    - CONFIG_TEST_BOARD_PPC_CONFIG_CUSTOM=y
+
+  skyrim.winterhold.usb_mux_config:
+    extra_configs:
+    - CONFIG_TEST_BOARD_WINTERHOLD=y
+    - CONFIG_TEST_BOARD_USB_MUX_CONFIG_CUSTOM=y
+
+  skyrim.winterhold.fan:
+    extra_configs:
+    - CONFIG_TEST_BOARD_WINTERHOLD=y
+    - CONFIG_TEST_BOARD_FAN=y
+    - CONFIG_TEST_BOARD_FAN_CUSTOM=y
diff --git a/zephyr/test/skyrim/tests/baseboard/CMakeLists.txt b/zephyr/test/skyrim/tests/baseboard/CMakeLists.txt
new file mode 100644
index 0000000000..cad84421a9
--- /dev/null
+++ b/zephyr/test/skyrim/tests/baseboard/CMakeLists.txt
@@ -0,0 +1,7 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_sources(app PRIVATE src/common.c)
+target_sources_ifdef(CONFIG_TEST_BOARD_USB_PD_POLICY app PRIVATE src/usb_pd_policy.c ${PLATFORM_EC_PROGRAM_DIR}/skyrim/src/usb_pd_policy.c)
+target_sources_ifdef(CONFIG_TEST_BOARD_POWER_SIGNALS app PRIVATE src/power_signals ${PLATFORM_EC_PROGRAM_DIR}/skyrim/src/power_signals.c)
\ No newline at end of file
diff --git a/zephyr/test/skyrim/tests/baseboard/src/common.c b/zephyr/test/skyrim/tests/baseboard/src/common.c
new file mode 100644
index 0000000000..841b7db140
--- /dev/null
+++ b/zephyr/test/skyrim/tests/baseboard/src/common.c
@@ -0,0 +1,7 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include <zephyr/ztest.h>
+
+ZTEST_SUITE(common, NULL, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/skyrim/tests/baseboard/src/power_signals.c b/zephyr/test/skyrim/tests/baseboard/src/power_signals.c
new file mode 100644
index 0000000000..82e42acaa1
--- /dev/null
+++ b/zephyr/test/skyrim/tests/baseboard/src/power_signals.c
@@ -0,0 +1,400 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "ap_power/ap_power.h"
+#include "charger.h"
+#include "gpio.h"
+#include "gpio/gpio_int.h"
+#include "ioexpander.h"
+#include "power.h"
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/fff.h>
+#include <zephyr/ztest.h>
+
+void baseboard_suspend_change(struct ap_power_ev_callback *cb,
+			      struct ap_power_ev_data data);
+void baseboard_init(void);
+void baseboard_set_soc_pwr_pgood(enum gpio_signal unused);
+bool board_supports_pcore_ocp(void);
+void board_pwrbtn_to_pch(int level);
+void baseboard_s0_pgood(enum gpio_signal signal);
+void baseboard_set_en_pwr_pcore(enum gpio_signal unused);
+void baseboard_en_pwr_s0(enum gpio_signal signal);
+void baseboard_set_en_pwr_s3(enum gpio_signal signal);
+void baseboard_s5_pgood(enum gpio_signal signal);
+
+void baseboard_soc_thermtrip(enum gpio_signal signal);
+void baseboard_soc_pcore_ocp(enum gpio_signal signal);
+
+FAKE_VOID_FUNC(chipset_force_shutdown, enum chipset_shutdown_reason);
+FAKE_VALUE_FUNC(int, extpower_is_present);
+FAKE_VOID_FUNC(print_charger_prochot, int);
+FAKE_VOID_FUNC(power_signal_interrupt, enum gpio_signal);
+FAKE_VOID_FUNC(power_interrupt_handler, enum gpio_signal);
+
+int chipset_in_state(int mask)
+{
+	return mask & CHIPSET_STATE_ON;
+}
+
+static int gpio_emul_output_get_dt(const struct gpio_dt_spec *dt)
+{
+	return gpio_emul_output_get(dt->port, dt->pin);
+}
+
+static int gpio_emul_input_set_dt(const struct gpio_dt_spec *dt, int value)
+{
+	return gpio_emul_input_set(dt->port, dt->pin, value);
+}
+
+/* Toggles the pin and checks that the interrupt handler was called. */
+int test_interrupt(const struct gpio_dt_spec *dt)
+{
+	int rv;
+	int old_count = power_interrupt_handler_fake.call_count;
+
+	rv = gpio_emul_input_set_dt(dt, 0);
+	if (rv)
+		return rv;
+
+	rv = gpio_emul_input_set_dt(dt, 1);
+	if (rv)
+		return rv;
+
+	rv = gpio_emul_input_set_dt(dt, 1);
+	if (rv)
+		return rv;
+
+	return power_interrupt_handler_fake.call_count <= old_count;
+}
+
+static void power_signals_before(void *fixture)
+{
+	ARG_UNUSED(fixture);
+	RESET_FAKE(chipset_force_shutdown);
+	RESET_FAKE(extpower_is_present);
+	RESET_FAKE(print_charger_prochot);
+	RESET_FAKE(power_signal_interrupt);
+	RESET_FAKE(power_interrupt_handler);
+}
+
+ZTEST_SUITE(power_signals, NULL, NULL, power_signals_before, NULL, NULL);
+
+ZTEST(power_signals, test_baseboard_suspend_change)
+{
+	const struct gpio_dt_spec *gpio_ec_disable_disp_bl =
+		GPIO_DT_FROM_NODELABEL(gpio_ec_disable_disp_bl);
+
+	struct ap_power_ev_data data;
+
+	data.event = AP_POWER_SUSPEND;
+	baseboard_suspend_change(NULL, data);
+	zassert_true(gpio_emul_output_get_dt(gpio_ec_disable_disp_bl));
+
+	data.event = AP_POWER_RESUME;
+	baseboard_suspend_change(NULL, data);
+	zassert_false(gpio_emul_output_get_dt(gpio_ec_disable_disp_bl));
+}
+
+ZTEST(power_signals, test_baseboard_shutdown_change)
+{
+	const struct gpio_dt_spec *usb_a1_retimer_en =
+		GPIO_DT_FROM_NODELABEL(usb_a1_retimer_en);
+
+	struct ap_power_ev_data data;
+
+	data.event = AP_POWER_SHUTDOWN;
+	baseboard_suspend_change(NULL, data);
+	zassert_false(gpio_emul_output_get_dt(usb_a1_retimer_en));
+
+	data.event = AP_POWER_STARTUP;
+	baseboard_suspend_change(NULL, data);
+	zassert_true(gpio_emul_output_get_dt(usb_a1_retimer_en));
+}
+
+ZTEST(power_signals, test_baseboard_init)
+{
+	const struct gpio_dt_spec *gpio_pg_groupc_s0_od =
+		GPIO_DT_FROM_NODELABEL(gpio_pg_groupc_s0_od);
+	const struct gpio_dt_spec *gpio_pg_lpddr5_s0_od =
+		GPIO_DT_FROM_NODELABEL(gpio_pg_lpddr5_s0_od);
+	const struct gpio_dt_spec *gpio_pg_lpddr5_s3_od =
+		GPIO_DT_FROM_NODELABEL(gpio_pg_lpddr5_s3_od);
+	const struct gpio_dt_spec *gpio_soc_thermtrip_odl =
+		GPIO_DT_FROM_NODELABEL(gpio_soc_thermtrip_odl);
+	const struct gpio_dt_spec *gpio_sfh_ec_int_h =
+		GPIO_DT_FROM_NODELABEL(gpio_sfh_ec_int_h);
+	const struct gpio_dt_spec *gpio_prochot_odl =
+		GPIO_DT_FROM_NODELABEL(gpio_prochot_odl);
+
+	baseboard_init();
+
+	/* Trigger interrupts to validate that they've been enabled. */
+	/* These interrupts use the generic test handler. */
+	zassert_ok(test_interrupt(gpio_pg_groupc_s0_od));
+	zassert_ok(test_interrupt(gpio_pg_lpddr5_s0_od));
+	zassert_ok(test_interrupt(gpio_pg_lpddr5_s3_od));
+	zassert_ok(test_interrupt(gpio_sfh_ec_int_h));
+
+	/* Verify that the thermal trip interrupt triggers a shutdown. */
+	zassert_ok(gpio_emul_input_set_dt(gpio_soc_thermtrip_odl, 1));
+	zassert_ok(gpio_emul_input_set_dt(gpio_soc_thermtrip_odl, 0));
+	zassert_equal(chipset_force_shutdown_fake.call_count, 1);
+	zassert_equal(chipset_force_shutdown_fake.arg0_val,
+		      CHIPSET_SHUTDOWN_THERMAL);
+
+	/* Test that our prochot handler prints out charger info. */
+	zassert_ok(gpio_emul_input_set_dt(gpio_prochot_odl, 1));
+	zassert_ok(gpio_emul_input_set_dt(gpio_prochot_odl, 0));
+	zassert_ok(gpio_emul_input_set_dt(gpio_prochot_odl, 1));
+	/* Give plenty of time for the deferred logic to run. */
+	k_msleep(500);
+	zassert_equal(print_charger_prochot_fake.call_count, 1);
+}
+
+ZTEST(power_signals, test_baseboard_set_soc_pwr_pgood)
+{
+	const struct gpio_dt_spec *gpio_en_pwr_pcore_s0_r =
+		GPIO_DT_FROM_NODELABEL(gpio_en_pwr_pcore_s0_r);
+	const struct gpio_dt_spec *gpio_pg_lpddr5_s0_od =
+		GPIO_DT_FROM_NODELABEL(gpio_pg_lpddr5_s0_od);
+	const struct gpio_dt_spec *gpio_s0_pgood =
+		GPIO_DT_FROM_NODELABEL(gpio_s0_pgood);
+
+	const struct gpio_dt_spec *gpio_ec_soc_pwr_good =
+		GPIO_DT_FROM_NODELABEL(gpio_ec_soc_pwr_good);
+
+	/* Test all combinations of these power pins. */
+	zassert_ok(gpio_pin_set_dt(gpio_en_pwr_pcore_s0_r, 0));
+	zassert_ok(gpio_emul_input_set_dt(gpio_pg_lpddr5_s0_od, 0));
+	zassert_ok(gpio_emul_input_set_dt(gpio_s0_pgood, 0));
+	baseboard_set_soc_pwr_pgood(0);
+	zassert_false(gpio_emul_output_get_dt(gpio_ec_soc_pwr_good));
+
+	zassert_ok(gpio_pin_set_dt(gpio_en_pwr_pcore_s0_r, 1));
+	zassert_ok(gpio_emul_input_set_dt(gpio_pg_lpddr5_s0_od, 0));
+	zassert_ok(gpio_emul_input_set_dt(gpio_s0_pgood, 0));
+	baseboard_set_soc_pwr_pgood(0);
+	zassert_false(gpio_emul_output_get_dt(gpio_ec_soc_pwr_good));
+
+	zassert_ok(gpio_pin_set_dt(gpio_en_pwr_pcore_s0_r, 0));
+	zassert_ok(gpio_emul_input_set_dt(gpio_pg_lpddr5_s0_od, 1));
+	zassert_ok(gpio_emul_input_set_dt(gpio_s0_pgood, 0));
+	baseboard_set_soc_pwr_pgood(0);
+	zassert_false(gpio_emul_output_get_dt(gpio_ec_soc_pwr_good));
+
+	zassert_ok(gpio_pin_set_dt(gpio_en_pwr_pcore_s0_r, 1));
+	zassert_ok(gpio_emul_input_set_dt(gpio_pg_lpddr5_s0_od, 1));
+	zassert_ok(gpio_emul_input_set_dt(gpio_s0_pgood, 0));
+	baseboard_set_soc_pwr_pgood(0);
+	zassert_false(gpio_emul_output_get_dt(gpio_ec_soc_pwr_good));
+
+	zassert_ok(gpio_pin_set_dt(gpio_en_pwr_pcore_s0_r, 0));
+	zassert_ok(gpio_emul_input_set_dt(gpio_pg_lpddr5_s0_od, 0));
+	zassert_ok(gpio_emul_input_set_dt(gpio_s0_pgood, 1));
+	baseboard_set_soc_pwr_pgood(0);
+	zassert_false(gpio_emul_output_get_dt(gpio_ec_soc_pwr_good));
+
+	zassert_ok(gpio_pin_set_dt(gpio_en_pwr_pcore_s0_r, 1));
+	zassert_ok(gpio_emul_input_set_dt(gpio_pg_lpddr5_s0_od, 0));
+	zassert_ok(gpio_emul_input_set_dt(gpio_s0_pgood, 1));
+	baseboard_set_soc_pwr_pgood(0);
+	zassert_false(gpio_emul_output_get_dt(gpio_ec_soc_pwr_good));
+
+	zassert_ok(gpio_pin_set_dt(gpio_en_pwr_pcore_s0_r, 0));
+	zassert_ok(gpio_emul_input_set_dt(gpio_pg_lpddr5_s0_od, 1));
+	zassert_ok(gpio_emul_input_set_dt(gpio_s0_pgood, 1));
+	baseboard_set_soc_pwr_pgood(0);
+	zassert_false(gpio_emul_output_get_dt(gpio_ec_soc_pwr_good));
+
+	zassert_ok(gpio_pin_set_dt(gpio_en_pwr_pcore_s0_r, 1));
+	zassert_ok(gpio_emul_input_set_dt(gpio_pg_lpddr5_s0_od, 1));
+	zassert_ok(gpio_emul_input_set_dt(gpio_s0_pgood, 1));
+	baseboard_set_soc_pwr_pgood(0);
+	zassert_true(gpio_emul_output_get_dt(gpio_ec_soc_pwr_good));
+}
+
+ZTEST(power_signals, test_board_supports_pcore_ocp)
+{
+	zassert_true(board_supports_pcore_ocp());
+}
+
+ZTEST(power_signals, test_baseboard_set_en_pwr_pcore)
+{
+	const struct gpio_dt_spec *gpio_pg_lpddr5_s3_od =
+		GPIO_DT_FROM_NODELABEL(gpio_pg_lpddr5_s3_od);
+	const struct gpio_dt_spec *gpio_pg_groupc_s0_od =
+		GPIO_DT_FROM_NODELABEL(gpio_pg_groupc_s0_od);
+	const struct gpio_dt_spec *gpio_en_pwr_s0_r =
+		GPIO_DT_FROM_NODELABEL(gpio_en_pwr_s0_r);
+
+	const struct gpio_dt_spec *gpio_en_pwr_pcore_s0_r =
+		GPIO_DT_FROM_NODELABEL(gpio_en_pwr_pcore_s0_r);
+
+	/* Test all combinations of these power pins. */
+	zassert_ok(gpio_emul_input_set_dt(gpio_pg_lpddr5_s3_od, 0));
+	zassert_ok(gpio_emul_input_set_dt(gpio_pg_groupc_s0_od, 0));
+	zassert_ok(gpio_emul_input_set_dt(gpio_en_pwr_s0_r, 0));
+	baseboard_set_en_pwr_pcore(0);
+	zassert_false(gpio_emul_output_get_dt(gpio_en_pwr_pcore_s0_r));
+
+	zassert_ok(gpio_emul_input_set_dt(gpio_pg_lpddr5_s3_od, 1));
+	zassert_ok(gpio_emul_input_set_dt(gpio_pg_groupc_s0_od, 0));
+	zassert_ok(gpio_emul_input_set_dt(gpio_en_pwr_s0_r, 0));
+	baseboard_set_en_pwr_pcore(0);
+	zassert_false(gpio_emul_output_get_dt(gpio_en_pwr_pcore_s0_r));
+
+	zassert_ok(gpio_emul_input_set_dt(gpio_pg_lpddr5_s3_od, 0));
+	zassert_ok(gpio_emul_input_set_dt(gpio_pg_groupc_s0_od, 1));
+	zassert_ok(gpio_emul_input_set_dt(gpio_en_pwr_s0_r, 0));
+	baseboard_set_en_pwr_pcore(0);
+	zassert_false(gpio_emul_output_get_dt(gpio_en_pwr_pcore_s0_r));
+
+	zassert_ok(gpio_emul_input_set_dt(gpio_pg_lpddr5_s3_od, 1));
+	zassert_ok(gpio_emul_input_set_dt(gpio_pg_groupc_s0_od, 1));
+	zassert_ok(gpio_emul_input_set_dt(gpio_en_pwr_s0_r, 0));
+	baseboard_set_en_pwr_pcore(0);
+	zassert_false(gpio_emul_output_get_dt(gpio_en_pwr_pcore_s0_r));
+
+	zassert_ok(gpio_emul_input_set_dt(gpio_pg_lpddr5_s3_od, 0));
+	zassert_ok(gpio_emul_input_set_dt(gpio_pg_groupc_s0_od, 0));
+	zassert_ok(gpio_emul_input_set_dt(gpio_en_pwr_s0_r, 1));
+	baseboard_set_en_pwr_pcore(0);
+	zassert_false(gpio_emul_output_get_dt(gpio_en_pwr_pcore_s0_r));
+
+	zassert_ok(gpio_emul_input_set_dt(gpio_pg_lpddr5_s3_od, 1));
+	zassert_ok(gpio_emul_input_set_dt(gpio_pg_groupc_s0_od, 0));
+	zassert_ok(gpio_emul_input_set_dt(gpio_en_pwr_s0_r, 1));
+	baseboard_set_en_pwr_pcore(0);
+	zassert_false(gpio_emul_output_get_dt(gpio_en_pwr_pcore_s0_r));
+
+	zassert_ok(gpio_emul_input_set_dt(gpio_pg_lpddr5_s3_od, 0));
+	zassert_ok(gpio_emul_input_set_dt(gpio_pg_groupc_s0_od, 1));
+	zassert_ok(gpio_emul_input_set_dt(gpio_en_pwr_s0_r, 1));
+	baseboard_set_en_pwr_pcore(0);
+	zassert_false(gpio_emul_output_get_dt(gpio_en_pwr_pcore_s0_r));
+
+	zassert_ok(gpio_emul_input_set_dt(gpio_pg_lpddr5_s3_od, 1));
+	zassert_ok(gpio_emul_input_set_dt(gpio_pg_groupc_s0_od, 1));
+	zassert_ok(gpio_emul_input_set_dt(gpio_en_pwr_s0_r, 1));
+	baseboard_set_en_pwr_pcore(0);
+	zassert_true(gpio_emul_output_get_dt(gpio_en_pwr_pcore_s0_r));
+}
+
+ZTEST(power_signals, test_baseboard_en_pwr_s0)
+{
+	const struct gpio_dt_spec *gpio_slp_s3_l =
+		GPIO_DT_FROM_NODELABEL(gpio_slp_s3_l);
+	const struct gpio_dt_spec *gpio_pg_pwr_s5 =
+		GPIO_DT_FROM_NODELABEL(gpio_pg_pwr_s5);
+
+	const struct gpio_dt_spec *gpio_en_pwr_s0_r =
+		GPIO_DT_FROM_NODELABEL(gpio_en_pwr_s0_r);
+
+	/* Test all combinations of these power pins. */
+	zassert_ok(gpio_emul_input_set_dt(gpio_slp_s3_l, 0));
+	zassert_ok(gpio_emul_input_set_dt(gpio_pg_pwr_s5, 0));
+	baseboard_en_pwr_s0(0);
+	zassert_false(gpio_emul_output_get_dt(gpio_en_pwr_s0_r));
+
+	zassert_ok(gpio_emul_input_set_dt(gpio_slp_s3_l, 1));
+	zassert_ok(gpio_emul_input_set_dt(gpio_pg_pwr_s5, 0));
+	baseboard_en_pwr_s0(0);
+	zassert_false(gpio_emul_output_get_dt(gpio_en_pwr_s0_r));
+
+	zassert_ok(gpio_emul_input_set_dt(gpio_slp_s3_l, 0));
+	zassert_ok(gpio_emul_input_set_dt(gpio_pg_pwr_s5, 1));
+	baseboard_en_pwr_s0(0);
+	zassert_false(gpio_emul_output_get_dt(gpio_en_pwr_s0_r));
+
+	zassert_ok(gpio_emul_input_set_dt(gpio_slp_s3_l, 1));
+	zassert_ok(gpio_emul_input_set_dt(gpio_pg_pwr_s5, 1));
+	baseboard_en_pwr_s0(0);
+	zassert_true(gpio_emul_output_get_dt(gpio_en_pwr_s0_r));
+
+	/* Ensure we always are chaining off the normal handler. */
+	zassert_equal(power_signal_interrupt_fake.call_count, 4);
+}
+
+ZTEST(power_signals, test_baseboard_set_en_pwr_s3)
+{
+	const struct gpio_dt_spec *gpio_slp_s5_l =
+		GPIO_DT_FROM_NODELABEL(gpio_slp_s5_l);
+
+	const struct gpio_dt_spec *gpio_en_pwr_s3 =
+		GPIO_DT_FROM_NODELABEL(gpio_en_pwr_s3);
+
+	zassert_ok(gpio_emul_input_set_dt(gpio_slp_s5_l, 0));
+	baseboard_set_en_pwr_s3(0);
+	zassert_false(gpio_emul_output_get_dt(gpio_en_pwr_s3));
+
+	zassert_ok(gpio_emul_input_set_dt(gpio_slp_s5_l, 1));
+	baseboard_set_en_pwr_s3(0);
+	zassert_true(gpio_emul_output_get_dt(gpio_en_pwr_s3));
+
+	/* Ensure we always are chaining off the normal handler. */
+	zassert_equal(power_signal_interrupt_fake.call_count, 2);
+}
+
+ZTEST(power_signals, test_baseboard_s5_pgood)
+{
+	const struct gpio_dt_spec *gpio_pg_pwr_s5 =
+		GPIO_DT_FROM_NODELABEL(gpio_pg_pwr_s5);
+	const struct gpio_dt_spec *gpio_hub_rst =
+		GPIO_DT_FROM_NODELABEL(gpio_hub_rst);
+
+	/* Test the path that waits 30 ms after S5 PGOOD. */
+	zassert_ok(gpio_emul_input_set_dt(gpio_pg_pwr_s5, 1));
+	baseboard_s5_pgood(0);
+	k_msleep(300);
+	zassert_false(gpio_emul_output_get_dt(gpio_hub_rst));
+
+	/* Test other path. */
+	zassert_ok(gpio_emul_input_set_dt(gpio_pg_pwr_s5, 0));
+	baseboard_s5_pgood(0);
+	zassert_true(gpio_emul_output_get_dt(gpio_hub_rst));
+}
+
+static void set_rsmrst_l(struct k_work *work)
+{
+	const struct gpio_dt_spec *gpio_ec_soc_rsmrst_l =
+		GPIO_DT_FROM_NODELABEL(gpio_ec_soc_rsmrst_l);
+
+	k_msleep(10);
+	gpio_emul_input_set_dt(gpio_ec_soc_rsmrst_l, 1);
+}
+K_WORK_DEFINE(set_rsmrst_l_work, set_rsmrst_l);
+
+ZTEST(power_signals, test_board_pwrbtn_to_pch)
+{
+	const struct gpio_dt_spec *gpio_ec_soc_rsmrst_l =
+		GPIO_DT_FROM_NODELABEL(gpio_ec_soc_rsmrst_l);
+	const struct gpio_dt_spec *gpio_ec_soc_pwr_btn_l =
+		GPIO_DT_FROM_NODELABEL(gpio_ec_soc_pwr_btn_l);
+
+	/* Test delay when asserting PWRBTN_L and RSMRST_L are low. */
+	zassert_ok(gpio_emul_input_set_dt(gpio_ec_soc_rsmrst_l, 0));
+	k_work_submit(&set_rsmrst_l_work);
+	board_pwrbtn_to_pch(0);
+	zassert_false(gpio_emul_output_get_dt(gpio_ec_soc_pwr_btn_l));
+
+	/* Test timeout. */
+	zassert_ok(gpio_emul_input_set_dt(gpio_ec_soc_rsmrst_l, 0));
+	board_pwrbtn_to_pch(0);
+	zassert_false(gpio_emul_output_get_dt(gpio_ec_soc_pwr_btn_l));
+
+	/* Test when PWRBTN_L is not asserted. */
+	board_pwrbtn_to_pch(1);
+	zassert_true(gpio_emul_output_get_dt(gpio_ec_soc_pwr_btn_l));
+}
+
+ZTEST(power_signals, test_baseboard_soc_pcore_ocp)
+{
+	baseboard_soc_pcore_ocp(0);
+	zassert_equal(chipset_force_shutdown_fake.call_count, 1);
+	zassert_equal(chipset_force_shutdown_fake.arg0_val,
+		      CHIPSET_SHUTDOWN_BOARD_CUSTOM);
+}
diff --git a/zephyr/test/skyrim/tests/baseboard/src/usb_pd_policy.c b/zephyr/test/skyrim/tests/baseboard/src/usb_pd_policy.c
new file mode 100644
index 0000000000..10c9e93b1a
--- /dev/null
+++ b/zephyr/test/skyrim/tests/baseboard/src/usb_pd_policy.c
@@ -0,0 +1,263 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/fff.h>
+#include <zephyr/ztest.h>
+
+#include <gpio.h>
+#include <ioexpander.h>
+#include <usb_pd.h>
+
+FAKE_VALUE_FUNC(int, ppc_vbus_source_enable, int, int);
+FAKE_VOID_FUNC(pd_set_vbus_discharge, int, int);
+FAKE_VOID_FUNC(pd_send_host_event, int);
+FAKE_VALUE_FUNC(bool, tcpm_get_src_ctrl, int);
+FAKE_VALUE_FUNC(int, ppc_vbus_sink_enable, int, int);
+
+int board_is_sourcing_vbus(int port);
+
+ZTEST(usb_pd_policy, test_pd_check_vconn_swap)
+{
+	const struct gpio_dt_spec *gpio =
+		GPIO_DT_FROM_NODELABEL(gpio_pg_pwr_s5);
+
+	/*
+	 * The value of pd_check_vconn_swap should follow gpio_pg_pwr_s5
+	 * for all ports.
+	 */
+	zassert_ok(gpio_emul_input_set(gpio->port, gpio->pin, true));
+	zassert_true(pd_check_vconn_swap(0));
+	zassert_true(pd_check_vconn_swap(1));
+
+	zassert_ok(gpio_emul_input_set(gpio->port, gpio->pin, false));
+	zassert_false(pd_check_vconn_swap(0));
+	zassert_false(pd_check_vconn_swap(1));
+}
+
+ZTEST(usb_pd_policy, test_pd_power_supply_reset_c0_success)
+{
+	ppc_vbus_source_enable_fake.return_val = EC_SUCCESS;
+	ppc_vbus_sink_enable_fake.return_val = EC_SUCCESS;
+
+	pd_power_supply_reset(0);
+
+	zassert_equal(ppc_vbus_source_enable_fake.call_count, 1);
+	/* port */
+	zassert_equal(ppc_vbus_source_enable_fake.arg0_val, 0);
+	/* enable */
+	zassert_equal(ppc_vbus_source_enable_fake.arg1_val, 0);
+
+	if (IS_ENABLED(CONFIG_USB_PD_DISCHARGE)) {
+		zassert_equal(pd_set_vbus_discharge_fake.call_count, 1);
+		/* port */
+		zassert_equal(pd_set_vbus_discharge_fake.arg0_val, 0);
+		/* enable */
+		zassert_equal(pd_set_vbus_discharge_fake.arg1_val, 1);
+	}
+
+	zassert_equal(pd_send_host_event_fake.call_count, 1);
+}
+
+ZTEST(usb_pd_policy, test_pd_power_supply_reset_c1_success)
+{
+	ppc_vbus_source_enable_fake.return_val = EC_SUCCESS;
+	ppc_vbus_sink_enable_fake.return_val = EC_SUCCESS;
+
+	pd_power_supply_reset(1);
+
+	zassert_equal(ppc_vbus_source_enable_fake.call_count, 1);
+	/* port */
+	zassert_equal(ppc_vbus_source_enable_fake.arg0_val, 1);
+	/* enable */
+	zassert_equal(ppc_vbus_source_enable_fake.arg1_val, 0);
+
+	if (IS_ENABLED(CONFIG_USB_PD_DISCHARGE)) {
+		zassert_equal(pd_set_vbus_discharge_fake.call_count, 1);
+		/* port */
+		zassert_equal(pd_set_vbus_discharge_fake.arg0_val, 1);
+		/* enable */
+		zassert_equal(pd_set_vbus_discharge_fake.arg1_val, 1);
+	}
+
+	zassert_equal(pd_send_host_event_fake.call_count, 1);
+}
+
+ZTEST(usb_pd_policy, test_pd_set_power_supply_ready_c0_success)
+{
+	ppc_vbus_source_enable_fake.return_val = EC_SUCCESS;
+	ppc_vbus_sink_enable_fake.return_val = EC_SUCCESS;
+
+	zassert_equal(pd_set_power_supply_ready(0), EC_SUCCESS);
+
+	zassert_equal(ppc_vbus_sink_enable_fake.call_count, 1);
+	/* port */
+	zassert_equal(ppc_vbus_sink_enable_fake.arg0_val, 0);
+	/* enable */
+	zassert_equal(ppc_vbus_sink_enable_fake.arg1_val, 0);
+
+	if (IS_ENABLED(CONFIG_USB_PD_DISCHARGE)) {
+		zassert_equal(pd_set_vbus_discharge_fake.call_count, 1);
+		/* port */
+		zassert_equal(pd_set_vbus_discharge_fake.arg0_val, 0);
+		/* enable */
+		zassert_equal(pd_set_vbus_discharge_fake.arg1_val, 0);
+	}
+
+	zassert_equal(ppc_vbus_source_enable_fake.call_count, 1);
+	/* port */
+	zassert_equal(ppc_vbus_source_enable_fake.arg0_val, 0);
+	/* enable */
+	zassert_equal(ppc_vbus_source_enable_fake.arg1_val, 1);
+
+	zassert_equal(pd_send_host_event_fake.call_count, 1);
+}
+
+ZTEST(usb_pd_policy, test_pd_set_power_supply_ready_c1_success)
+{
+	ppc_vbus_source_enable_fake.return_val = EC_SUCCESS;
+	ppc_vbus_sink_enable_fake.return_val = EC_SUCCESS;
+
+	zassert_equal(pd_set_power_supply_ready(1), EC_SUCCESS);
+
+	zassert_equal(ppc_vbus_sink_enable_fake.call_count, 1);
+	/* port */
+	zassert_equal(ppc_vbus_sink_enable_fake.arg0_val, 1);
+	/* enable */
+	zassert_equal(ppc_vbus_sink_enable_fake.arg1_val, 0);
+
+	if (IS_ENABLED(CONFIG_USB_PD_DISCHARGE)) {
+		zassert_equal(pd_set_vbus_discharge_fake.call_count, 1);
+		/* port */
+		zassert_equal(pd_set_vbus_discharge_fake.arg0_val, 1);
+		/* enable */
+		zassert_equal(pd_set_vbus_discharge_fake.arg1_val, 0);
+	}
+
+	zassert_equal(ppc_vbus_source_enable_fake.call_count, 1);
+	/* port */
+	zassert_equal(ppc_vbus_source_enable_fake.arg0_val, 1);
+	/* enable */
+	zassert_equal(ppc_vbus_source_enable_fake.arg1_val, 1);
+
+	zassert_equal(pd_send_host_event_fake.call_count, 1);
+}
+
+ZTEST(usb_pd_policy, test_pd_set_power_supply_ready_c0_failure)
+{
+	/* Test with ppc_vbus_sink_enable_fake failing. */
+	ppc_vbus_sink_enable_fake.return_val = EC_ERROR_INVAL;
+	zassert_not_equal(pd_set_power_supply_ready(0), EC_SUCCESS);
+	zassert_equal(ppc_vbus_sink_enable_fake.call_count, 1);
+	/* port */
+	zassert_equal(ppc_vbus_sink_enable_fake.arg0_val, 0);
+	/* enable */
+	zassert_equal(ppc_vbus_sink_enable_fake.arg1_val, 0);
+
+	/* Test with ppc_vbus_source_enable failing. */
+	ppc_vbus_sink_enable_fake.return_val = EC_SUCCESS;
+	ppc_vbus_source_enable_fake.return_val = EC_ERROR_INVAL;
+	zassert_not_equal(pd_set_power_supply_ready(0), EC_SUCCESS);
+	zassert_equal(ppc_vbus_source_enable_fake.call_count, 1);
+	/* port */
+	zassert_equal(ppc_vbus_source_enable_fake.arg0_val, 0);
+	/* enable */
+	zassert_equal(ppc_vbus_source_enable_fake.arg1_val, 1);
+
+	zassert_equal(pd_send_host_event_fake.call_count, 0);
+}
+
+ZTEST(usb_pd_policy, test_pd_set_power_supply_ready_c1_failure)
+{
+	/* Test with ppc_vbus_sink_enable_fake failing. */
+	ppc_vbus_sink_enable_fake.return_val = EC_ERROR_INVAL;
+	zassert_not_equal(pd_set_power_supply_ready(1), EC_SUCCESS);
+	zassert_equal(ppc_vbus_sink_enable_fake.call_count, 1);
+	/* port */
+	zassert_equal(ppc_vbus_sink_enable_fake.arg0_val, 1);
+	/* enable */
+	zassert_equal(ppc_vbus_sink_enable_fake.arg1_val, 0);
+
+	/* Test with ppc_vbus_source_enable failing. */
+	ppc_vbus_sink_enable_fake.return_val = EC_SUCCESS;
+	ppc_vbus_source_enable_fake.return_val = EC_ERROR_INVAL;
+	zassert_not_equal(pd_set_power_supply_ready(1), EC_SUCCESS);
+	zassert_equal(ppc_vbus_source_enable_fake.call_count, 1);
+	/* port */
+	zassert_equal(ppc_vbus_source_enable_fake.arg0_val, 1);
+	/* enable */
+	zassert_equal(ppc_vbus_source_enable_fake.arg1_val, 1);
+
+	zassert_equal(pd_send_host_event_fake.call_count, 0);
+}
+
+ZTEST(usb_pd_policy, test_board_pd_set_frs_enable)
+{
+	const struct gpio_dt_spec *c0 =
+		GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_fastsw_ctl_en);
+	const struct gpio_dt_spec *c1 =
+		GPIO_DT_FROM_NODELABEL(gpio_usb_c1_tcpc_fastsw_ctl_en);
+
+	/* Enables to each port should just change the corresponding GPIO. */
+	zassert_equal(board_pd_set_frs_enable(0, true), EC_SUCCESS);
+	zassert_equal(gpio_emul_output_get(c0->port, c0->pin), 1);
+
+	zassert_equal(board_pd_set_frs_enable(0, false), EC_SUCCESS);
+	zassert_equal(gpio_emul_output_get(c0->port, c0->pin), 0);
+
+	zassert_equal(board_pd_set_frs_enable(1, true), EC_SUCCESS);
+	zassert_equal(gpio_emul_output_get(c1->port, c1->pin), 1);
+
+	zassert_equal(board_pd_set_frs_enable(1, false), EC_SUCCESS);
+	zassert_equal(gpio_emul_output_get(c1->port, c1->pin), 0);
+}
+
+ZTEST(usb_pd_policy, test_board_is_sourcing_vbus_c0_true)
+{
+	tcpm_get_src_ctrl_fake.return_val = true;
+	zassert_true(board_is_sourcing_vbus(0));
+	zassert_equal(tcpm_get_src_ctrl_fake.call_count, 1);
+	/* port */
+	zassert_equal(tcpm_get_src_ctrl_fake.arg0_val, 0);
+}
+
+ZTEST(usb_pd_policy, test_board_is_sourcing_vbus_c0_false)
+{
+	tcpm_get_src_ctrl_fake.return_val = false;
+	zassert_false(board_is_sourcing_vbus(0));
+	zassert_equal(tcpm_get_src_ctrl_fake.call_count, 1);
+	/* port */
+	zassert_equal(tcpm_get_src_ctrl_fake.arg0_val, 0);
+}
+
+ZTEST(usb_pd_policy, test_board_is_sourcing_vbus_c1_true)
+{
+	tcpm_get_src_ctrl_fake.return_val = true;
+	zassert_true(board_is_sourcing_vbus(1));
+	zassert_equal(tcpm_get_src_ctrl_fake.call_count, 1);
+	/* port */
+	zassert_equal(tcpm_get_src_ctrl_fake.arg0_val, 1);
+}
+
+ZTEST(usb_pd_policy, test_board_is_sourcing_vbus_c1_false)
+{
+	tcpm_get_src_ctrl_fake.return_val = false;
+	zassert_false(board_is_sourcing_vbus(1));
+	zassert_equal(tcpm_get_src_ctrl_fake.call_count, 1);
+	/* port */
+	zassert_equal(tcpm_get_src_ctrl_fake.arg0_val, 1);
+}
+
+static void usb_pd_policy_before(void *fixture)
+{
+	ARG_UNUSED(fixture);
+	RESET_FAKE(ppc_vbus_source_enable);
+	RESET_FAKE(pd_set_vbus_discharge);
+	RESET_FAKE(pd_send_host_event);
+	RESET_FAKE(tcpm_get_src_ctrl);
+	RESET_FAKE(ppc_vbus_sink_enable);
+}
+
+ZTEST_SUITE(usb_pd_policy, NULL, NULL, usb_pd_policy_before, NULL, NULL);
diff --git a/zephyr/test/skyrim/tests/common/CMakeLists.txt b/zephyr/test/skyrim/tests/common/CMakeLists.txt
new file mode 100644
index 0000000000..53dd9da3c4
--- /dev/null
+++ b/zephyr/test/skyrim/tests/common/CMakeLists.txt
@@ -0,0 +1,39 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_sources(app PRIVATE src/common.c)
+
+# Alt charger
+if (DEFINED CONFIG_TEST_BOARD_ALT_CHARGER)
+	target_sources(app PRIVATE ${PLATFORM_EC_PROGRAM_DIR}/skyrim/${CONFIG_TEST_BOARD_NAME}/src/alt_charger.c)
+	if (NOT DEFINED CONFIG_TEST_BOARD_ALT_CHARGER_CUSTOM)
+		target_sources(app PRIVATE src/alt_charger.c)
+	endif()
+endif()
+
+# Fan
+if (DEFINED CONFIG_TEST_BOARD_FAN)
+	target_sources(app PRIVATE ${PLATFORM_EC_PROGRAM_DIR}/skyrim/${CONFIG_TEST_BOARD_NAME}/src/fan.c)
+	if (NOT DEFINED CONFIG_TEST_BOARD_FAN_CUSTOM)
+		target_sources(app PRIVATE src/fan.c)
+	endif()
+endif()
+
+# PPC config
+if (DEFINED CONFIG_TEST_BOARD_PPC_CONFIG)
+	target_sources(app PRIVATE ${PLATFORM_EC_PROGRAM_DIR}/skyrim/${CONFIG_TEST_BOARD_NAME}/src/ppc_config.c)
+	if (NOT DEFINED CONFIG_TEST_BOARD_PPC_CONFIG_CUSTOM)
+		target_sources(app PRIVATE src/ppc_config.c)
+	endif()
+endif()
+
+# USB mux config
+if (DEFINED CONFIG_TEST_BOARD_USB_MUX_CONFIG)
+	target_sources(app PRIVATE
+		${PLATFORM_EC}/driver/usb_mux/usb_mux.c
+		${PLATFORM_EC}/zephyr/shim/src/usb_muxes.c
+		src/usb_mux_config.c
+		${PLATFORM_EC_PROGRAM_DIR}/skyrim/${CONFIG_TEST_BOARD_NAME}/src/usb_mux_config.c
+	)
+endif()
\ No newline at end of file
diff --git a/zephyr/test/skyrim/tests/common/src/alt_charger.c b/zephyr/test/skyrim/tests/common/src/alt_charger.c
new file mode 100644
index 0000000000..0bd641fad0
--- /dev/null
+++ b/zephyr/test/skyrim/tests/common/src/alt_charger.c
@@ -0,0 +1,55 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include <zephyr/devicetree.h>
+#include <zephyr/fff.h>
+#include <zephyr/ztest.h>
+
+#include <charger.h>
+#include <cros_cbi.h>
+#include <hooks.h>
+
+FAKE_VALUE_FUNC(int, cros_cbi_get_fw_config, enum cbi_fw_config_field_id,
+		uint32_t *);
+FAKE_VOID_FUNC(chg_enable_alternate_test, int);
+
+void alt_charger_init(void);
+
+static bool alt_charger;
+static int cros_cbi_get_fw_config_mock(enum cbi_fw_config_field_id field_id,
+				       uint32_t *value)
+{
+	if (field_id != FW_CHARGER)
+		return -EINVAL;
+
+	*value = alt_charger ? FW_CHARGER_ISL9538 : FW_CHARGER_ISL9241;
+	return 0;
+}
+
+static void alt_charger_before(void *fixture)
+{
+	ARG_UNUSED(fixture);
+	RESET_FAKE(cros_cbi_get_fw_config);
+	RESET_FAKE(chg_enable_alternate_test);
+
+	cros_cbi_get_fw_config_fake.custom_fake = cros_cbi_get_fw_config_mock;
+}
+
+ZTEST_SUITE(alt_charger, NULL, NULL, alt_charger_before, NULL, NULL);
+
+ZTEST(alt_charger, test_normal_charger)
+{
+	alt_charger = false;
+	alt_charger_init();
+	/* Test that the alternative charger wasn't enabled. */
+	zassert_equal(chg_enable_alternate_test_fake.call_count, 0);
+}
+
+ZTEST(alt_charger, test_alt_charger)
+{
+	alt_charger = true;
+	alt_charger_init();
+	zassert_equal(chg_enable_alternate_test_fake.call_count, 1);
+	zassert_equal(chg_enable_alternate_test_fake.arg0_val, 0);
+}
diff --git a/zephyr/test/skyrim/tests/common/src/common.c b/zephyr/test/skyrim/tests/common/src/common.c
new file mode 100644
index 0000000000..770414c786
--- /dev/null
+++ b/zephyr/test/skyrim/tests/common/src/common.c
@@ -0,0 +1,54 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "common.h"
+#include "usbc/usb_muxes.h"
+
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(skyrim, CONFIG_SKYRIM_LOG_LEVEL);
+
+/*
+ * Provide weak definitons for interrupt handlers. This minimizes the number
+ * of test-specific device tree overrides needed.
+ */
+
+test_mockable void baseboard_soc_pcore_ocp(enum gpio_signal signal)
+{
+}
+
+test_mockable void baseboard_soc_thermtrip(enum gpio_signal signal)
+{
+}
+
+test_mockable int bmi3xx_interrupt(enum gpio_signal signal)
+{
+	return -EINVAL;
+}
+
+test_mockable int bma4xx_interrupt(enum gpio_signal signal)
+{
+	return -EINVAL;
+}
+
+test_mockable int board_anx7483_c0_mux_set(const struct usb_mux *me,
+					   mux_state_t mux_state)
+{
+	return -EINVAL;
+}
+
+test_mockable int board_anx7483_c1_mux_set(const struct usb_mux *me,
+					   mux_state_t mux_state)
+{
+	return -EINVAL;
+}
+
+test_mockable int power_interrupt_handler(const struct gpio_dt_spec *dt)
+{
+	return -EINVAL;
+}
+
+test_mockable void throttle_ap_prochot_input_interrupt(enum gpio_signal signal)
+{
+}
diff --git a/zephyr/test/skyrim/tests/common/src/fan.c b/zephyr/test/skyrim/tests/common/src/fan.c
new file mode 100644
index 0000000000..275a7f1463
--- /dev/null
+++ b/zephyr/test/skyrim/tests/common/src/fan.c
@@ -0,0 +1,92 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include <zephyr/devicetree.h>
+#include <zephyr/fff.h>
+#include <zephyr/ztest.h>
+
+#include <cros_board_info.h>
+#include <cros_cbi.h>
+#include <fan.h>
+#include <hooks.h>
+
+FAKE_VOID_FUNC(fan_set_count, int);
+FAKE_VALUE_FUNC(int, cros_cbi_get_fw_config, enum cbi_fw_config_field_id,
+		uint32_t *);
+FAKE_VALUE_FUNC(int, cbi_get_board_version, uint32_t *);
+
+void fan_init(void);
+bool board_supports_pcore_ocp(void);
+
+static bool fan_present;
+static int board_version;
+
+static int cros_cbi_get_fw_config_mock(enum cbi_fw_config_field_id field_id,
+				       uint32_t *value)
+{
+	if (field_id != FW_FAN)
+		return -EINVAL;
+
+	*value = fan_present ? FW_FAN_PRESENT : FW_FAN_NOT_PRESENT;
+	return 0;
+}
+
+static int cbi_get_board_version_mock(uint32_t *value)
+{
+	*value = board_version;
+	return EC_SUCCESS;
+}
+
+static void fan_before(void *fixture)
+{
+	ARG_UNUSED(fixture);
+	RESET_FAKE(fan_set_count);
+	RESET_FAKE(cros_cbi_get_fw_config);
+	RESET_FAKE(cbi_get_board_version);
+
+	cros_cbi_get_fw_config_fake.custom_fake = cros_cbi_get_fw_config_mock;
+	cbi_get_board_version_fake.custom_fake = cbi_get_board_version_mock;
+}
+
+ZTEST_SUITE(fan, NULL, NULL, fan_before, NULL, NULL);
+
+ZTEST(fan, test_board_supports_pcore_ocp)
+{
+	/* Only supported for board version > 3. */
+	board_version = 2;
+	zassert_false(board_supports_pcore_ocp());
+	board_version = 3;
+	zassert_false(board_supports_pcore_ocp());
+	board_version = 4;
+	zassert_true(board_supports_pcore_ocp());
+}
+
+ZTEST(fan, test_fan_init)
+{
+	/* Only disable fans on board version >= 3. */
+	fan_present = false;
+	board_version = 2;
+	fan_init();
+	zassert_equal(fan_set_count_fake.call_count, 0);
+
+	fan_present = true;
+	board_version = 3;
+	fan_init();
+	zassert_equal(fan_set_count_fake.call_count, 0);
+
+	fan_present = true;
+	board_version = 4;
+	fan_init();
+	zassert_equal(fan_set_count_fake.call_count, 0);
+
+	fan_present = false;
+	board_version = 3;
+	fan_init();
+	zassert_equal(fan_set_count_fake.call_count, 1);
+
+	fan_present = false;
+	board_version = 4;
+	fan_init();
+	zassert_equal(fan_set_count_fake.call_count, 2);
+}
diff --git a/zephyr/test/skyrim/tests/common/src/ppc_config.c b/zephyr/test/skyrim/tests/common/src/ppc_config.c
new file mode 100644
index 0000000000..0527520413
--- /dev/null
+++ b/zephyr/test/skyrim/tests/common/src/ppc_config.c
@@ -0,0 +1,62 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/fff.h>
+#include <zephyr/ztest.h>
+
+#include <gpio.h>
+#include <usbc_ppc.h>
+
+FAKE_VOID_FUNC(aoz1380_interrupt, int);
+FAKE_VOID_FUNC(nx20p348x_interrupt, int);
+
+static void ppc_config_before(void *fixture)
+{
+	ARG_UNUSED(fixture);
+	RESET_FAKE(aoz1380_interrupt);
+	RESET_FAKE(nx20p348x_interrupt);
+}
+
+void ppc_interrupt(enum gpio_signal signal);
+int board_aoz1380_set_vbus_source_current_limit(int port,
+						enum tcpc_rp_value rp);
+
+ZTEST_SUITE(ppc_config, NULL, NULL, ppc_config_before, NULL, NULL);
+
+ZTEST(ppc_config, test_board_aoz1380_set_vbus_source_current_limit)
+{
+	int rv;
+	const struct gpio_dt_spec *gpio =
+		GPIO_DT_FROM_NODELABEL(ioex_usb_c0_ilim_3a_en);
+
+	/*
+	 * board_aoz1380_set_vbus_source_current_limit should set
+	 * ioex_usb_c0_ilim_3a_en to 1 for 3A, 0 otherwise.
+	 */
+	rv = board_aoz1380_set_vbus_source_current_limit(0, TYPEC_RP_3A0);
+	zassert_equal(rv, EC_SUCCESS);
+	zassert_equal(gpio_emul_output_get(gpio->port, gpio->pin), 1);
+
+	rv = board_aoz1380_set_vbus_source_current_limit(0, TYPEC_RP_1A5);
+	zassert_equal(rv, EC_SUCCESS);
+	zassert_equal(gpio_emul_output_get(gpio->port, gpio->pin), 0);
+
+	/* Only port0 is supported. */
+	rv = board_aoz1380_set_vbus_source_current_limit(1, TYPEC_RP_1A5);
+	zassert_equal(rv, EC_ERROR_INVAL);
+}
+
+ZTEST(ppc_config, test_ppc_interrupt)
+{
+	ppc_interrupt(GPIO_USB_C0_PPC_INT_ODL);
+	zassert_equal(aoz1380_interrupt_fake.call_count, 1);
+	/* port */
+	zassert_equal(aoz1380_interrupt_fake.arg0_val, 0);
+
+	ppc_interrupt(GPIO_USB_C1_PPC_INT_ODL);
+	zassert_equal(nx20p348x_interrupt_fake.call_count, 1);
+	/* port */
+	zassert_equal(nx20p348x_interrupt_fake.arg0_val, 1);
+}
diff --git a/zephyr/test/skyrim/tests/common/src/usb_mux_config.c b/zephyr/test/skyrim/tests/common/src/usb_mux_config.c
new file mode 100644
index 0000000000..ea663ba2cb
--- /dev/null
+++ b/zephyr/test/skyrim/tests/common/src/usb_mux_config.c
@@ -0,0 +1,62 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "chipset.h"
+#include "usbc/usb_muxes.h"
+#include "ztest/usb_mux_config.h"
+
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/fff.h>
+#include <zephyr/ztest.h>
+
+int ioex_set_flip(int port, mux_state_t mux_state);
+int board_c1_ps8818_mux_set(const struct usb_mux *me, mux_state_t mux_state);
+
+DEFINE_FAKE_VOID_FUNC(usb_mux_enable_alternative);
+
+__override uint8_t board_get_usb_pd_port_count(void)
+{
+	return CONFIG_USB_PD_PORT_MAX_COUNT;
+}
+
+enum tcpc_cc_polarity pd_get_polarity(int port)
+{
+	return 0;
+}
+
+FAKE_VOID_FUNC(chipset_force_shutdown, enum chipset_shutdown_reason);
+FAKE_VALUE_FUNC(int, extpower_is_present);
+
+int chipset_in_state(int mask)
+{
+	return mask & CHIPSET_STATE_ON;
+}
+
+ZTEST_SUITE(usb_mux_config_common, NULL, NULL, NULL, NULL, NULL);
+
+ZTEST(usb_mux_config_common, test_ioex_set_flip)
+{
+	const struct gpio_dt_spec *c0 =
+		GPIO_DT_FROM_NODELABEL(ioex_usb_c0_sbu_flip);
+	const struct gpio_dt_spec *c1 =
+		GPIO_DT_FROM_NODELABEL(ioex_usb_c1_sbu_flip);
+	int rv;
+
+	/* Value of the corresponding pin should match flipped status. */
+	rv = ioex_set_flip(0, 0);
+	zassert_ok(rv);
+	zassert_equal(gpio_emul_output_get(c0->port, c0->pin), 0);
+
+	rv = ioex_set_flip(0, USB_PD_MUX_POLARITY_INVERTED);
+	zassert_ok(rv);
+	zassert_equal(gpio_emul_output_get(c0->port, c0->pin), 1);
+
+	rv = ioex_set_flip(1, 0);
+	zassert_ok(rv);
+	zassert_equal(gpio_emul_output_get(c1->port, c1->pin), 0);
+
+	rv = ioex_set_flip(1, USB_PD_MUX_POLARITY_INVERTED);
+	zassert_ok(rv);
+	zassert_equal(gpio_emul_output_get(c1->port, c1->pin), 1);
+}
diff --git a/zephyr/test/skyrim/tests/crystaldrift/CMakeLists.txt b/zephyr/test/skyrim/tests/crystaldrift/CMakeLists.txt
new file mode 100644
index 0000000000..cec3317f7f
--- /dev/null
+++ b/zephyr/test/skyrim/tests/crystaldrift/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_sources(app PRIVATE src/common.c)
+target_sources_ifdef(CONFIG_TEST_BOARD_PPC_CONFIG app PRIVATE src/ppc_config.c)
diff --git a/zephyr/test/skyrim/tests/crystaldrift/src/common.c b/zephyr/test/skyrim/tests/crystaldrift/src/common.c
new file mode 100644
index 0000000000..9fa7864859
--- /dev/null
+++ b/zephyr/test/skyrim/tests/crystaldrift/src/common.c
@@ -0,0 +1,10 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include <zephyr/logging/log.h>
+#include <zephyr/ztest.h>
+
+LOG_MODULE_REGISTER(crystaldrift, CONFIG_SKYRIM_LOG_LEVEL);
+
+ZTEST_SUITE(common, NULL, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/skyrim/tests/crystaldrift/src/ppc_config.c b/zephyr/test/skyrim/tests/crystaldrift/src/ppc_config.c
new file mode 100644
index 0000000000..0f319d8ea4
--- /dev/null
+++ b/zephyr/test/skyrim/tests/crystaldrift/src/ppc_config.c
@@ -0,0 +1,37 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include <zephyr/fff.h>
+#include <zephyr/ztest.h>
+
+#include <gpio.h>
+#include <usbc_ppc.h>
+
+FAKE_VOID_FUNC(nx20p348x_interrupt, int);
+
+static void ppc_config_before(void *fixture)
+{
+	ARG_UNUSED(fixture);
+	RESET_FAKE(nx20p348x_interrupt);
+}
+
+void ppc_interrupt(enum gpio_signal signal);
+
+ZTEST_SUITE(ppc_config, NULL, NULL, ppc_config_before, NULL, NULL);
+
+ZTEST(ppc_config, test_ppc_interrupt_c0)
+{
+	ppc_interrupt(GPIO_USB_C0_PPC_INT_ODL);
+	zassert_equal(nx20p348x_interrupt_fake.call_count, 1);
+	/* port */
+	zassert_equal(nx20p348x_interrupt_fake.arg0_val, 0);
+}
+
+ZTEST(ppc_config, test_ppc_interrupt_c1)
+{
+	ppc_interrupt(GPIO_USB_C1_PPC_INT_ODL);
+	zassert_equal(nx20p348x_interrupt_fake.call_count, 1);
+	/* port */
+	zassert_equal(nx20p348x_interrupt_fake.arg0_val, 1);
+}
diff --git a/zephyr/test/skyrim/tests/frostflow/CMakeLists.txt b/zephyr/test/skyrim/tests/frostflow/CMakeLists.txt
new file mode 100644
index 0000000000..539890dcd7
--- /dev/null
+++ b/zephyr/test/skyrim/tests/frostflow/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_sources(app PRIVATE src/common.c)
+target_sources_ifdef(CONFIG_TEST_BOARD_USB_MUX_CONFIG app PRIVATE src/usb_mux_config.c)
\ No newline at end of file
diff --git a/zephyr/test/skyrim/tests/frostflow/src/common.c b/zephyr/test/skyrim/tests/frostflow/src/common.c
new file mode 100644
index 0000000000..841b7db140
--- /dev/null
+++ b/zephyr/test/skyrim/tests/frostflow/src/common.c
@@ -0,0 +1,7 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include <zephyr/ztest.h>
+
+ZTEST_SUITE(common, NULL, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/skyrim/tests/frostflow/src/usb_mux_config.c b/zephyr/test/skyrim/tests/frostflow/src/usb_mux_config.c
new file mode 100644
index 0000000000..24e7e78dbf
--- /dev/null
+++ b/zephyr/test/skyrim/tests/frostflow/src/usb_mux_config.c
@@ -0,0 +1,44 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/fff.h>
+#include <zephyr/ztest.h>
+
+#include <driver/retimer/ps8811.h>
+#include <usbc/usb_muxes.h>
+
+int board_c0_amd_fp6_mux_set(const struct usb_mux *me, mux_state_t mux_state);
+int board_c1_ps8818_mux_set(const struct usb_mux *me, mux_state_t mux_state);
+
+ZTEST_SUITE(usb_mux_config, NULL, NULL, NULL, NULL, NULL);
+
+ZTEST(usb_mux_config, test_board_c0_amd_fp6_mux_set)
+{
+	const struct gpio_dt_spec *c0 =
+		GPIO_DT_FROM_NODELABEL(ioex_usb_c0_sbu_flip);
+	const struct gpio_dt_spec *c1 =
+		GPIO_DT_FROM_NODELABEL(ioex_usb_c1_sbu_flip);
+	struct usb_mux mux;
+	int rv;
+
+	/* Output for each port should match inverted status. */
+	mux.usb_port = 0;
+	rv = board_c0_amd_fp6_mux_set(&mux, 0);
+	zassert_equal(rv, EC_SUCCESS);
+	zassert_equal(gpio_emul_output_get(c0->port, c0->pin), 0);
+
+	rv = board_c0_amd_fp6_mux_set(&mux, USB_PD_MUX_POLARITY_INVERTED);
+	zassert_equal(rv, EC_SUCCESS);
+	zassert_equal(gpio_emul_output_get(c0->port, c0->pin), 1);
+
+	mux.usb_port = 1;
+	rv = board_c0_amd_fp6_mux_set(&mux, 0);
+	zassert_equal(rv, EC_SUCCESS);
+	zassert_equal(gpio_emul_output_get(c1->port, c1->pin), 0);
+
+	rv = board_c0_amd_fp6_mux_set(&mux, USB_PD_MUX_POLARITY_INVERTED);
+	zassert_equal(rv, EC_SUCCESS);
+	zassert_equal(gpio_emul_output_get(c1->port, c1->pin), 1);
+}
diff --git a/zephyr/test/skyrim/tests/markarth/CMakeLists.txt b/zephyr/test/skyrim/tests/markarth/CMakeLists.txt
new file mode 100644
index 0000000000..e78711fed2
--- /dev/null
+++ b/zephyr/test/skyrim/tests/markarth/CMakeLists.txt
@@ -0,0 +1,5 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_sources(app PRIVATE src/common.c)
diff --git a/zephyr/test/skyrim/tests/markarth/src/common.c b/zephyr/test/skyrim/tests/markarth/src/common.c
new file mode 100644
index 0000000000..b302042761
--- /dev/null
+++ b/zephyr/test/skyrim/tests/markarth/src/common.c
@@ -0,0 +1,10 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include <zephyr/logging/log.h>
+#include <zephyr/ztest.h>
+
+LOG_MODULE_REGISTER(markarth, CONFIG_SKYRIM_LOG_LEVEL);
+
+ZTEST_SUITE(common, NULL, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/skyrim/tests/skyrim/CMakeLists.txt b/zephyr/test/skyrim/tests/skyrim/CMakeLists.txt
new file mode 100644
index 0000000000..adf1708004
--- /dev/null
+++ b/zephyr/test/skyrim/tests/skyrim/CMakeLists.txt
@@ -0,0 +1,9 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_sources(app PRIVATE src/common.c)
+target_sources_ifdef(CONFIG_TEST_BOARD_FORM_FACTOR app PRIVATE
+	src/form_factor.c ${PLATFORM_EC_PROGRAM_DIR}/skyrim/${CONFIG_TEST_BOARD_NAME}/src/form_factor.c)
+
+target_sources_ifdef(CONFIG_TEST_BOARD_USB_MUX_CONFIG app PRIVATE src/usb_mux_config.c)
diff --git a/zephyr/test/skyrim/tests/skyrim/src/common.c b/zephyr/test/skyrim/tests/skyrim/src/common.c
new file mode 100644
index 0000000000..841b7db140
--- /dev/null
+++ b/zephyr/test/skyrim/tests/skyrim/src/common.c
@@ -0,0 +1,7 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include <zephyr/ztest.h>
+
+ZTEST_SUITE(common, NULL, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/skyrim/tests/skyrim/src/form_factor.c b/zephyr/test/skyrim/tests/skyrim/src/form_factor.c
new file mode 100644
index 0000000000..af71a61be6
--- /dev/null
+++ b/zephyr/test/skyrim/tests/skyrim/src/form_factor.c
@@ -0,0 +1,164 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "tablet_mode.h"
+#include "zephyr/kernel.h"
+
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/fff.h>
+#include <zephyr/ztest.h>
+
+void clamshell_init(void);
+
+FAKE_VALUE_FUNC(int, cros_cbi_get_fw_config, enum cbi_fw_config_field_id,
+		uint32_t *);
+
+static bool clamshell_mode;
+static int interrupt_count;
+
+void bmi3xx_interrupt(enum gpio_signal signal)
+{
+	interrupt_count++;
+}
+
+static int cros_cbi_get_fw_config_mock(enum cbi_fw_config_field_id field_id,
+				       uint32_t *value)
+{
+	if (field_id != FW_FORM_FACTOR)
+		return -EINVAL;
+
+	*value = clamshell_mode ? FW_FF_CLAMSHELL : FW_FF_CONVERTIBLE;
+	return 0;
+}
+
+static void *form_factor_setup(void)
+{
+	const struct device *tablet_mode_gpio =
+		DEVICE_DT_GET(DT_GPIO_CTLR(DT_NODELABEL(tablet_mode_l), gpios));
+	const gpio_port_pins_t tablet_mode_pin =
+		DT_GPIO_PIN(DT_NODELABEL(tablet_mode_l), gpios);
+
+	/* Set default value of TABLET_MODE_L */
+	gpio_emul_input_set(tablet_mode_gpio, tablet_mode_pin, 1);
+
+	clamshell_mode = 0;
+
+	RESET_FAKE(cros_cbi_get_fw_config);
+	cros_cbi_get_fw_config_fake.custom_fake = cros_cbi_get_fw_config_mock;
+
+	hook_notify(HOOK_INIT);
+
+	return NULL;
+}
+
+ZTEST_SUITE(skyrim_form_factor, NULL, form_factor_setup, NULL, NULL, NULL);
+
+ZTEST(skyrim_form_factor, test_03_clamshell_gmr_tablet_switch_disabled)
+{
+	const struct device *tablet_mode_gpio =
+		DEVICE_DT_GET(DT_GPIO_CTLR(DT_NODELABEL(tablet_mode_l), gpios));
+	const gpio_port_pins_t tablet_mode_pin =
+		DT_GPIO_PIN(DT_NODELABEL(tablet_mode_l), gpios);
+
+	clamshell_mode = 1;
+	clamshell_init();
+
+	/* Verify gmr_tablet_switch is disabled, by checking the side effects
+	 * of calling tablet_set_mode, and setting gpio_tablet_mode_l.
+	 */
+	zassert_ok(gpio_emul_input_set(tablet_mode_gpio, tablet_mode_pin, 0),
+		   NULL);
+	k_sleep(K_MSEC(100));
+	tablet_set_mode(1, TABLET_TRIGGER_LID);
+	zassert_equal(0, tablet_get_mode(), NULL);
+	zassert_ok(gpio_emul_input_set(tablet_mode_gpio, tablet_mode_pin, 1),
+		   NULL);
+	k_sleep(K_MSEC(100));
+	tablet_set_mode(0, TABLET_TRIGGER_LID);
+	zassert_equal(0, tablet_get_mode(), NULL);
+	zassert_ok(gpio_emul_input_set(tablet_mode_gpio, tablet_mode_pin, 0),
+		   NULL);
+	k_sleep(K_MSEC(100));
+	tablet_set_mode(1, TABLET_TRIGGER_LID);
+	zassert_equal(0, tablet_get_mode(), NULL);
+}
+
+ZTEST(skyrim_form_factor, test_04_clamshell_base_imu_irq_disabled)
+{
+	const struct device *base_imu_gpio = DEVICE_DT_GET(
+		DT_GPIO_CTLR(DT_NODELABEL(gpio_accel_gyro_int_l), gpios));
+	const gpio_port_pins_t base_imu_pin =
+		DT_GPIO_PIN(DT_NODELABEL(gpio_accel_gyro_int_l), gpios);
+
+	clamshell_mode = 1;
+	clamshell_init();
+
+	/* Verify base_imu_irq is disabled. */
+	interrupt_count = 0;
+	zassert_ok(gpio_emul_input_set(base_imu_gpio, base_imu_pin, 1), NULL);
+	k_sleep(K_MSEC(100));
+	zassert_ok(gpio_emul_input_set(base_imu_gpio, base_imu_pin, 0), NULL);
+	k_sleep(K_MSEC(100));
+
+	zassert_equal(interrupt_count, 0, "interrupt_count=%d",
+		      interrupt_count);
+}
+
+ZTEST(skyrim_form_factor, test_01_convertible_gmr_tablet_switch_enabled)
+{
+	const struct device *tablet_mode_gpio =
+		DEVICE_DT_GET(DT_GPIO_CTLR(DT_NODELABEL(tablet_mode_l), gpios));
+	const gpio_port_pins_t tablet_mode_pin =
+		DT_GPIO_PIN(DT_NODELABEL(tablet_mode_l), gpios);
+
+	clamshell_mode = 0;
+	clamshell_init();
+
+	/* Verify gmr_tablet_switch is enabled, by checking the side effects
+	 * of calling tablet_set_mode, and setting gpio_tablet_mode_l.
+	 */
+	zassert_ok(gpio_emul_input_set(tablet_mode_gpio, tablet_mode_pin, 0),
+		   NULL);
+	k_sleep(K_MSEC(100));
+	tablet_set_mode(1, TABLET_TRIGGER_LID);
+	zassert_equal(1, tablet_get_mode(), NULL);
+	zassert_ok(gpio_emul_input_set(tablet_mode_gpio, tablet_mode_pin, 1),
+		   NULL);
+	k_sleep(K_MSEC(100));
+	tablet_set_mode(0, TABLET_TRIGGER_LID);
+	zassert_equal(0, tablet_get_mode(), NULL);
+	zassert_ok(gpio_emul_input_set(tablet_mode_gpio, tablet_mode_pin, 0),
+		   NULL);
+	k_sleep(K_MSEC(100));
+	tablet_set_mode(1, TABLET_TRIGGER_LID);
+	zassert_equal(1, tablet_get_mode(), NULL);
+}
+
+ZTEST(skyrim_form_factor, test_02_convertible_base_imu_irq_enabled)
+{
+	const struct device *base_imu_gpio = DEVICE_DT_GET(
+		DT_GPIO_CTLR(DT_NODELABEL(gpio_accel_gyro_int_l), gpios));
+	const gpio_port_pins_t base_imu_pin =
+		DT_GPIO_PIN(DT_NODELABEL(gpio_accel_gyro_int_l), gpios);
+
+	clamshell_mode = 0;
+	clamshell_init();
+
+	/* Verify base_imu_irq is enabled. Interrupt is configured
+	 * GPIO_INT_EDGE_FALLING, so set high, then set low.
+	 */
+	interrupt_count = 0;
+	zassert_ok(gpio_emul_input_set(base_imu_gpio, base_imu_pin, 1), NULL);
+	k_sleep(K_MSEC(100));
+	zassert_ok(gpio_emul_input_set(base_imu_gpio, base_imu_pin, 0), NULL);
+	k_sleep(K_MSEC(100));
+
+	zassert_equal(interrupt_count, 1, "interrupt_count=%d",
+		      interrupt_count);
+}
diff --git a/zephyr/test/skyrim/tests/skyrim/src/usb_mux_config.c b/zephyr/test/skyrim/tests/skyrim/src/usb_mux_config.c
new file mode 100644
index 0000000000..91aafad1b2
--- /dev/null
+++ b/zephyr/test/skyrim/tests/skyrim/src/usb_mux_config.c
@@ -0,0 +1,194 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "cros_cbi.h"
+#include "emul/retimer/emul_anx7483.h"
+#include "usbc/usb_muxes.h"
+#include "ztest/usb_mux_config.h"
+
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/fff.h>
+#include <zephyr/ztest.h>
+
+#define ANX7483_EMUL0 EMUL_DT_GET(DT_NODELABEL(anx7483_port0))
+#define ANX7483_EMUL1 EMUL_DT_GET(DT_NODELABEL(anx7483_port1))
+
+int board_c1_ps8818_mux_set(const struct usb_mux *me, mux_state_t mux_state);
+void setup_mux(void);
+
+extern const struct anx7483_tuning_set anx7483_usb_enabled[];
+extern const struct anx7483_tuning_set anx7483_dp_enabled[];
+extern const struct anx7483_tuning_set anx7483_dock_noflip[];
+extern const struct anx7483_tuning_set anx7483_dock_flip[];
+
+extern const size_t anx7483_usb_enabled_count;
+extern const size_t anx7483_dp_enabled_count;
+extern const size_t anx7483_dock_noflip_count;
+extern const size_t anx7483_dock_flip_count;
+
+FAKE_VALUE_FUNC(int, cros_cbi_get_fw_config, enum cbi_fw_config_field_id,
+		uint32_t *);
+
+static bool alt_retimer;
+static int cros_cbi_get_fw_config_mock(enum cbi_fw_config_field_id field_id,
+				       uint32_t *value)
+{
+	if (field_id != FW_IO_DB)
+		return -EINVAL;
+
+	*value = alt_retimer ? FW_IO_DB_PS8811_PS8818 : FW_IO_DB_NONE_ANX7483;
+	return 0;
+}
+
+static void usb_mux_config_before(void *fixture)
+{
+	ARG_UNUSED(fixture);
+	RESET_FAKE(cros_cbi_get_fw_config);
+
+	cros_cbi_get_fw_config_fake.custom_fake = cros_cbi_get_fw_config_mock;
+}
+
+ZTEST_SUITE(usb_mux_config, NULL, NULL, usb_mux_config_before, NULL, NULL);
+
+ZTEST(usb_mux_config, test_board_anx7483_c0_mux_set)
+{
+	int rv;
+
+	usb_mux_init(0);
+
+	usb_mux_set(0, USB_PD_MUX_USB_ENABLED, USB_SWITCH_CONNECT, 0);
+	rv = anx7483_emul_validate_tuning(ANX7483_EMUL0, anx7483_usb_enabled,
+					  anx7483_usb_enabled_count);
+	zexpect_ok(rv);
+
+	usb_mux_set(0, USB_PD_MUX_DP_ENABLED, USB_SWITCH_CONNECT, 0);
+	rv = anx7483_emul_validate_tuning(ANX7483_EMUL0, anx7483_dp_enabled,
+					  anx7483_dp_enabled_count);
+	zexpect_ok(rv);
+
+	usb_mux_set(0, USB_PD_MUX_DOCK, USB_SWITCH_CONNECT, 0);
+	rv = anx7483_emul_validate_tuning(ANX7483_EMUL0, anx7483_dock_noflip,
+					  anx7483_dock_noflip_count);
+	zexpect_ok(rv);
+
+	usb_mux_set(0, USB_PD_MUX_DOCK | USB_PD_MUX_POLARITY_INVERTED,
+		    USB_SWITCH_CONNECT, 0);
+	rv = anx7483_emul_validate_tuning(ANX7483_EMUL0, anx7483_dock_flip,
+					  anx7483_dock_flip_count);
+	zexpect_ok(rv);
+}
+
+ZTEST(usb_mux_config, test_board_anx7483_c1_mux_set)
+{
+	int rv;
+	enum anx7483_eq_setting eq;
+
+	alt_retimer = false;
+	setup_mux();
+
+	usb_mux_init(1);
+
+	/* Test USB mux state. */
+	usb_mux_set(1, USB_PD_MUX_USB_ENABLED, USB_SWITCH_CONNECT, 0);
+
+	rv = anx7483_emul_get_eq(ANX7483_EMUL1, ANX7483_PIN_URX1, &eq);
+	zassert_ok(rv);
+	zassert_equal(eq, ANX7483_EQ_SETTING_12_5DB);
+
+	rv = anx7483_emul_get_eq(ANX7483_EMUL1, ANX7483_PIN_URX2, &eq);
+	zassert_ok(rv);
+	zassert_equal(eq, ANX7483_EQ_SETTING_12_5DB);
+
+	rv = anx7483_emul_get_eq(ANX7483_EMUL1, ANX7483_PIN_DRX1, &eq);
+	zassert_ok(rv);
+	zassert_equal(eq, ANX7483_EQ_SETTING_12_5DB);
+
+	rv = anx7483_emul_get_eq(ANX7483_EMUL1, ANX7483_PIN_DRX2, &eq);
+	zassert_ok(rv);
+	zassert_equal(eq, ANX7483_EQ_SETTING_12_5DB);
+
+	/* Test DP mux state. */
+	usb_mux_set(1, USB_PD_MUX_DP_ENABLED, USB_SWITCH_CONNECT, 0);
+
+	rv = anx7483_emul_get_eq(ANX7483_EMUL1, ANX7483_PIN_URX1, &eq);
+	zassert_ok(rv);
+	zassert_equal(eq, ANX7483_EQ_SETTING_12_5DB);
+
+	rv = anx7483_emul_get_eq(ANX7483_EMUL1, ANX7483_PIN_URX2, &eq);
+	zassert_ok(rv);
+	zassert_equal(eq, ANX7483_EQ_SETTING_12_5DB);
+
+	rv = anx7483_emul_get_eq(ANX7483_EMUL1, ANX7483_PIN_UTX1, &eq);
+	zassert_ok(rv);
+	zassert_equal(eq, ANX7483_EQ_SETTING_12_5DB);
+
+	rv = anx7483_emul_get_eq(ANX7483_EMUL1, ANX7483_PIN_UTX2, &eq);
+	zassert_ok(rv);
+	zassert_equal(eq, ANX7483_EQ_SETTING_12_5DB);
+
+	/* Test dock mux state. */
+	usb_mux_set(1, USB_PD_MUX_DOCK, USB_SWITCH_CONNECT, 0);
+
+	rv = anx7483_emul_get_eq(ANX7483_EMUL1, ANX7483_PIN_URX1, &eq);
+	zassert_ok(rv);
+	zassert_equal(eq, ANX7483_EQ_SETTING_12_5DB);
+
+	rv = anx7483_emul_get_eq(ANX7483_EMUL1, ANX7483_PIN_URX2, &eq);
+	zassert_ok(rv);
+	zassert_equal(eq, ANX7483_EQ_SETTING_12_5DB);
+
+	rv = anx7483_emul_get_eq(ANX7483_EMUL1, ANX7483_PIN_DRX1, &eq);
+	zassert_ok(rv);
+	zassert_equal(eq, ANX7483_EQ_SETTING_12_5DB);
+
+	rv = anx7483_emul_get_eq(ANX7483_EMUL1, ANX7483_PIN_UTX2, &eq);
+	zassert_ok(rv);
+	zassert_equal(eq, ANX7483_EQ_SETTING_12_5DB);
+
+	/* Test flipped dock mux state. */
+	usb_mux_set(1, USB_PD_MUX_DOCK | USB_PD_MUX_POLARITY_INVERTED,
+		    USB_SWITCH_CONNECT, 0);
+
+	rv = anx7483_emul_get_eq(ANX7483_EMUL1, ANX7483_PIN_URX1, &eq);
+	zassert_ok(rv);
+	zassert_equal(eq, ANX7483_EQ_SETTING_12_5DB);
+
+	rv = anx7483_emul_get_eq(ANX7483_EMUL1, ANX7483_PIN_URX2, &eq);
+	zassert_ok(rv);
+	zassert_equal(eq, ANX7483_EQ_SETTING_12_5DB);
+
+	rv = anx7483_emul_get_eq(ANX7483_EMUL1, ANX7483_PIN_UTX1, &eq);
+	zassert_ok(rv);
+	zassert_equal(eq, ANX7483_EQ_SETTING_12_5DB);
+
+	rv = anx7483_emul_get_eq(ANX7483_EMUL1, ANX7483_PIN_DRX2, &eq);
+	zassert_ok(rv);
+	zassert_equal(eq, ANX7483_EQ_SETTING_12_5DB);
+}
+
+ZTEST(usb_mux_config, test_board_c1_ps8818_mux_set)
+{
+	const struct gpio_dt_spec *c1 =
+		GPIO_DT_FROM_NODELABEL(gpio_usb_c1_in_hpd);
+	const struct usb_mux mux = {
+		.usb_port = 1,
+	};
+
+	board_c1_ps8818_mux_set(&mux, USB_PD_MUX_USB_ENABLED);
+	zassert_false(gpio_emul_output_get(c1->port, c1->pin));
+
+	board_c1_ps8818_mux_set(&mux, USB_PD_MUX_DP_ENABLED);
+	zassert_true(gpio_emul_output_get(c1->port, c1->pin));
+}
+
+ZTEST(usb_mux_config, test_setup_mux)
+{
+	alt_retimer = false;
+	setup_mux();
+	zassert_equal(usb_mux_enable_alternative_fake.call_count, 0);
+
+	alt_retimer = true;
+	setup_mux();
+	zassert_equal(usb_mux_enable_alternative_fake.call_count, 1);
+}
diff --git a/zephyr/test/skyrim/tests/winterhold/CMakeLists.txt b/zephyr/test/skyrim/tests/winterhold/CMakeLists.txt
new file mode 100644
index 0000000000..39ded69058
--- /dev/null
+++ b/zephyr/test/skyrim/tests/winterhold/CMakeLists.txt
@@ -0,0 +1,7 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_sources(app PRIVATE src/common.c)
+target_sources_ifdef(CONFIG_TEST_BOARD_PPC_CONFIG app PRIVATE src/ppc_config.c)
+target_sources_ifdef(CONFIG_TEST_BOARD_FAN_CUSTOM app PRIVATE src/fan.c)
diff --git a/zephyr/test/skyrim/tests/winterhold/src/common.c b/zephyr/test/skyrim/tests/winterhold/src/common.c
new file mode 100644
index 0000000000..841b7db140
--- /dev/null
+++ b/zephyr/test/skyrim/tests/winterhold/src/common.c
@@ -0,0 +1,7 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include <zephyr/ztest.h>
+
+ZTEST_SUITE(common, NULL, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/skyrim/tests/winterhold/src/fan.c b/zephyr/test/skyrim/tests/winterhold/src/fan.c
new file mode 100644
index 0000000000..a7af0d2da1
--- /dev/null
+++ b/zephyr/test/skyrim/tests/winterhold/src/fan.c
@@ -0,0 +1,165 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include <zephyr/fff.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/ztest.h>
+
+#include <cros_board_info.h>
+#include <cros_cbi.h>
+#include <fan.h>
+#include <hooks.h>
+
+FAKE_VOID_FUNC(fan_set_duty, int, int);
+FAKE_VALUE_FUNC(int, fan_get_duty, int);
+
+struct fan_conf conf;
+struct fan_rpm rpm;
+
+const struct fan_t fans[1] = { { .conf = &conf, .rpm = &rpm } };
+struct fan_data fan_data[1];
+
+K_TIMER_DEFINE(ktimer, NULL, NULL);
+
+static void fan_set_duty_mock(int ch, int duty)
+{
+	zassert_equal(ch, 0);
+	zassert_between_inclusive(duty, 0, 100);
+
+	fan_data[ch].pwm_percent = duty;
+}
+
+static int fan_get_duty_mock(int ch)
+{
+	zassert_equal(ch, 0);
+	zassert_between_inclusive(fan_data[ch].pwm_percent, 0, 100);
+
+	return fan_data[ch].pwm_percent;
+}
+
+static int duty_to_rpm(int duty)
+{
+	const float ratio = 0.015;
+
+	zassert_between_inclusive(duty, 0, 100);
+
+	return (int)((float)duty / ratio);
+}
+
+static void fan_tick(void)
+{
+	int rpm_diff;
+	int duty;
+
+	duty = fan_data[0].pwm_percent;
+
+	rpm_diff = duty_to_rpm(duty) - fan_data[0].rpm_actual;
+
+	/* Clamp rpm_diff. This essentially emulates fan inertia. */
+	if (rpm_diff > 0)
+		rpm_diff = MIN(rpm_diff, 500);
+	if (rpm_diff < 0)
+		rpm_diff = MAX(rpm_diff, -500);
+
+	fan_data[0].rpm_actual += rpm_diff;
+}
+
+static void fan_test_begin(void *fixture)
+{
+	ARG_UNUSED(fixture);
+	RESET_FAKE(fan_set_duty);
+	RESET_FAKE(fan_get_duty);
+
+	fan_set_duty_fake.custom_fake = fan_set_duty_mock;
+	fan_get_duty_fake.custom_fake = fan_get_duty_mock;
+
+	/*
+	 * This is normally read from DT.
+	 * The problem is that we don't want to pull the entire fan framework
+	 * for this test. Instead initialize it here.
+	 * All the values come from
+	 * zephyr/program/skyrim/winterhold/project.overlay.
+	 */
+	memset(&conf, 0, sizeof(conf));
+	memset(&rpm, 0, sizeof(rpm));
+
+	rpm.rpm_max = 4800;
+	rpm.rpm_deviation = 3;
+
+	memset(&fan_data[0], 0, sizeof(fan_data[0]));
+}
+
+/* Only FAN 0 should be supported. */
+ZTEST(fan, test_fan_invalid_arg)
+{
+	enum fan_status status;
+
+	status = board_override_fan_control_duty(1);
+	zassert_equal(status, FAN_STATUS_FRUSTRATED);
+}
+
+/*
+ * Check whether we can ramp up into rpm_max in 5s.
+ * The time limit is selected on a per board basis.
+ * It depends on the thermal capacity of the radiator and CPU TDP.
+ * Basically we want to ensure that fan ramps up fast enough
+ * to prevent the CPU from thermal throttling.
+ */
+ZTEST(fan, test_fan_max_rpm)
+{
+	enum fan_status status;
+	int deviation;
+
+	fan_data[0].rpm_target = rpm.rpm_max;
+	k_timer_start(&ktimer, K_SECONDS(5), K_NO_WAIT);
+
+	while (k_timer_remaining_ticks(&ktimer) != 0) {
+		status = board_override_fan_control_duty(0);
+		zassert_not_equal(status, FAN_STATUS_FRUSTRATED);
+		fan_tick();
+		k_sleep(K_TICKS(1));
+	}
+
+	deviation = rpm.rpm_deviation * rpm.rpm_max / 100;
+	zassert_true(fan_set_duty_fake.call_count > 1);
+	zassert_within(fan_data[0].rpm_actual, rpm.rpm_max, deviation);
+	zassert_equal(status, FAN_STATUS_LOCKED);
+}
+
+/* Check for FAN_STATUS_STOPPED when the fan is in fact stopped. */
+ZTEST(fan, test_fan_off)
+{
+	enum fan_status status;
+
+	status = board_override_fan_control_duty(0);
+	zassert_equal(status, FAN_STATUS_STOPPED);
+	zassert_equal(fan_set_duty_fake.call_count, 0);
+}
+
+/* If we can't achieve selected RPM, FAN_STATUS_FRUSTRATED is expected. */
+ZTEST(fan, test_fan_frustrated_max)
+{
+	enum fan_status status;
+
+	/*
+	 * 10 seconds should be more than enough for implementation to realize
+	 * that it can't get up to 10k RPM
+	 */
+	fan_data[0].rpm_target = 10000;
+	k_timer_start(&ktimer, K_SECONDS(10), K_NO_WAIT);
+
+	while (k_timer_remaining_ticks(&ktimer) != 0) {
+		status = board_override_fan_control_duty(0);
+		if (status == FAN_STATUS_FRUSTRATED)
+			break;
+
+		fan_tick();
+		k_sleep(K_TICKS(1));
+	}
+	zassert_true(fan_set_duty_fake.call_count > 1);
+	zassert_equal(status, FAN_STATUS_FRUSTRATED);
+}
+
+ZTEST_SUITE(fan, NULL, NULL, fan_test_begin, NULL, NULL);
diff --git a/zephyr/test/skyrim/tests/winterhold/src/ppc_config.c b/zephyr/test/skyrim/tests/winterhold/src/ppc_config.c
new file mode 100644
index 0000000000..0f319d8ea4
--- /dev/null
+++ b/zephyr/test/skyrim/tests/winterhold/src/ppc_config.c
@@ -0,0 +1,37 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include <zephyr/fff.h>
+#include <zephyr/ztest.h>
+
+#include <gpio.h>
+#include <usbc_ppc.h>
+
+FAKE_VOID_FUNC(nx20p348x_interrupt, int);
+
+static void ppc_config_before(void *fixture)
+{
+	ARG_UNUSED(fixture);
+	RESET_FAKE(nx20p348x_interrupt);
+}
+
+void ppc_interrupt(enum gpio_signal signal);
+
+ZTEST_SUITE(ppc_config, NULL, NULL, ppc_config_before, NULL, NULL);
+
+ZTEST(ppc_config, test_ppc_interrupt_c0)
+{
+	ppc_interrupt(GPIO_USB_C0_PPC_INT_ODL);
+	zassert_equal(nx20p348x_interrupt_fake.call_count, 1);
+	/* port */
+	zassert_equal(nx20p348x_interrupt_fake.arg0_val, 0);
+}
+
+ZTEST(ppc_config, test_ppc_interrupt_c1)
+{
+	ppc_interrupt(GPIO_USB_C1_PPC_INT_ODL);
+	zassert_equal(nx20p348x_interrupt_fake.call_count, 1);
+	/* port */
+	zassert_equal(nx20p348x_interrupt_fake.arg0_val, 1);
+}
diff --git a/zephyr/test/system_common/CMakeLists.txt b/zephyr/test/system_common/CMakeLists.txt
new file mode 100644
index 0000000000..305d056068
--- /dev/null
+++ b/zephyr/test/system_common/CMakeLists.txt
@@ -0,0 +1,13 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(system_common_test)
+
+# Include FFF fakes
+add_subdirectory(${PLATFORM_EC}/zephyr/test/test_utils test_utils)
+
+FILE(GLOB test_sources src/*.c)
+target_sources(app PRIVATE ${test_sources})
diff --git a/zephyr/test/system_common/boards/native_posix.overlay b/zephyr/test/system_common/boards/native_posix.overlay
new file mode 100644
index 0000000000..c6325f6ecc
--- /dev/null
+++ b/zephyr/test/system_common/boards/native_posix.overlay
@@ -0,0 +1,9 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <board-overlays/native_posix.dts>
+
+/ {
+};
diff --git a/zephyr/test/system_common/prj.conf b/zephyr/test/system_common/prj.conf
new file mode 100644
index 0000000000..dafd50345b
--- /dev/null
+++ b/zephyr/test/system_common/prj.conf
@@ -0,0 +1,17 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_ZTEST=y
+CONFIG_ZTEST_NEW_API=y
+CONFIG_CROS_EC=y
+
+CONFIG_PLATFORM_EC_CROS_FWID_VERSION=y
+CONFIG_PLATFORM_EC=y
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
+CONFIG_PLATFORM_EC_HOSTCMD=y
+CONFIG_PLATFORM_EC_LID_SWITCH=n
+CONFIG_PLATFORM_EC_PANIC=n
+CONFIG_PLATFORM_EC_SWITCH=n
+CONFIG_PLATFORM_EC_VBOOT_HASH=n
+CONFIG_SYSTEM_BOOT_TIME_LOGGING=y
diff --git a/zephyr/test/system_common/src/build_info.c b/zephyr/test/system_common/src/build_info.c
new file mode 100644
index 0000000000..1057a3c013
--- /dev/null
+++ b/zephyr/test/system_common/src/build_info.c
@@ -0,0 +1,56 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "host_command.h"
+#include "system.h"
+
+#include <zephyr/device.h>
+#include <zephyr/fff.h>
+#include <zephyr/ztest_assert.h>
+#include <zephyr/ztest_test_new.h>
+
+ZTEST_SUITE(host_cmd_get_build_info, NULL, NULL, NULL, NULL, NULL);
+
+FAKE_VALUE_FUNC(const char *, system_get_build_info);
+
+ZTEST(host_cmd_get_build_info, test_get_build_info)
+{
+	int ret;
+	char resp[1024];
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_RESPONSE(EC_CMD_GET_BUILD_INFO, 0, resp);
+
+	RESET_FAKE(system_get_build_info);
+	system_get_build_info_fake.return_val = "i-am-a-version";
+
+	ret = host_command_process(&args);
+
+	zassert_equal(ret, EC_SUCCESS, "Unexpected return value: %d", ret);
+	zassert_equal(strcmp(resp, "i-am-a-version"), 0,
+		      "Unexpected response: %s", resp);
+	zassert_equal(system_get_build_info_fake.call_count, 1,
+		      "Unexpected call count: %d",
+		      system_get_build_info_fake.call_count);
+}
+
+ZTEST(host_cmd_get_build_info, test_get_build_info_truncated)
+{
+	int ret;
+	char resp[8];
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_RESPONSE(EC_CMD_GET_BUILD_INFO, 0, resp);
+
+	RESET_FAKE(system_get_build_info);
+	system_get_build_info_fake.return_val = "i-am-a-long-version";
+
+	ret = host_command_process(&args);
+
+	zassert_equal(ret, EC_SUCCESS, "Unexpected return value: %d", ret);
+	zassert_equal(strcmp(resp, "i-am-a-"), 0, "Unexpected response: %s",
+		      resp);
+	zassert_equal(system_get_build_info_fake.call_count, 1,
+		      "Unexpected call count: %d",
+		      system_get_build_info_fake.call_count);
+}
diff --git a/zephyr/test/system_common/src/get_boot_time.c b/zephyr/test/system_common/src/get_boot_time.c
new file mode 100644
index 0000000000..7cf7c6fffd
--- /dev/null
+++ b/zephyr/test/system_common/src/get_boot_time.c
@@ -0,0 +1,45 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "hooks.h"
+#include "host_command.h"
+#include "system.h"
+#include "system_boot_time.h"
+
+#include <zephyr/device.h>
+#include <zephyr/fff.h>
+#include <zephyr/ztest_assert.h>
+#include <zephyr/ztest_test_new.h>
+
+ZTEST_SUITE(host_cmd_get_boot_time, NULL, NULL, NULL, NULL, NULL);
+
+ZTEST(host_cmd_get_boot_time, test_get_boot_time)
+{
+	int ret;
+	struct ec_response_get_boot_time r;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_RESPONSE(EC_CMD_GET_BOOT_TIME, 0, r);
+
+	update_ap_boot_time(ARAIL);
+	update_ap_boot_time(RSMRST);
+	update_ap_boot_time(ESPIRST);
+	update_ap_boot_time(PLTRST_LOW);
+	update_ap_boot_time(PLTRST_HIGH);
+	update_ap_boot_time(EC_CUR_TIME);
+	/* trigger update_ap_boot_time(RESET_CNT) */
+	hook_notify(HOOK_CHIPSET_SHUTDOWN_COMPLETE);
+
+	ret = host_command_process(&args);
+
+	zassert_equal(ret, EC_SUCCESS, "Unexpected return value: %d", ret);
+
+	ccprintf("arail: %" PRIu64 "\n", r.timestamp[ARAIL]);
+	ccprintf("rsmrst: %" PRIu64 "\n", r.timestamp[RSMRST]);
+	ccprintf("espirst: %" PRIu64 "\n", r.timestamp[ESPIRST]);
+	ccprintf("pltrst_low: %" PRIu64 "\n", r.timestamp[PLTRST_LOW]);
+	ccprintf("pltrst_high: %" PRIu64 "\n", r.timestamp[PLTRST_HIGH]);
+	ccprintf("cnt: %" PRIu16 "\n", r.cnt);
+	ccprintf("ec_cur_time: %" PRIu64 "\n", r.timestamp[EC_CUR_TIME]);
+}
diff --git a/zephyr/test/system_common/src/get_version.c b/zephyr/test/system_common/src/get_version.c
new file mode 100644
index 0000000000..073c9a0662
--- /dev/null
+++ b/zephyr/test/system_common/src/get_version.c
@@ -0,0 +1,70 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "host_command.h"
+#include "system.h"
+
+#include <zephyr/device.h>
+#include <zephyr/fff.h>
+#include <zephyr/ztest_assert.h>
+#include <zephyr/ztest_test_new.h>
+
+ZTEST_SUITE(host_cmd_get_version, NULL, NULL, NULL, NULL, NULL);
+
+__override const char *system_get_version(enum ec_image copy)
+{
+	switch (copy) {
+	case EC_IMAGE_RO:
+		return "version-ro";
+	case EC_IMAGE_RW:
+		return "version-rw";
+	default:
+		return "unknown";
+	}
+}
+
+ZTEST(host_cmd_get_version, test_get_version_v1)
+{
+	int ret;
+	struct ec_response_get_version_v1 r;
+	struct host_cmd_handler_args args;
+
+	ret = ec_cmd_get_version_v1(&args, &r);
+
+	zassert_equal(ret, EC_SUCCESS, "Unexpected return value: %d", ret);
+
+	zassert_equal(strcmp(r.version_string_ro, "version-ro"), 0,
+		      "version_string_ro: %s", r.version_string_ro);
+	zassert_equal(args.response_size, sizeof(r), "response_size: %d",
+		      args.response_size);
+	zassert_equal(strcmp(r.version_string_rw, "version-rw"), 0,
+		      "version_string_rw: %s", r.version_string_rw);
+	zassert_equal(strcmp(r.cros_fwid_ro, "CROS_FWID_MISSING"), 0,
+		      "cros_fwid_ro: %s", r.cros_fwid_ro);
+	zassert_equal(strcmp(r.cros_fwid_rw, "CROS_FWID_MISSING"), 0,
+		      "cros_fwid_ro: %s", r.cros_fwid_rw);
+	zassert_equal(r.current_image, EC_IMAGE_UNKNOWN, "current_image: %s",
+		      r.current_image);
+}
+
+ZTEST(host_cmd_get_version, test_get_version_v0)
+{
+	int ret;
+	struct ec_response_get_version r;
+	struct host_cmd_handler_args args;
+
+	ret = ec_cmd_get_version(&args, &r);
+
+	zassert_equal(ret, EC_SUCCESS, "Unexpected return value: %d", ret);
+
+	zassert_equal(strcmp(r.version_string_ro, "version-ro"), 0,
+		      "version_string_ro: %s", r.version_string_ro);
+	zassert_equal(args.response_size, sizeof(r), "response_size: %d",
+		      args.response_size);
+	zassert_equal(strcmp(r.version_string_rw, "version-rw"), 0,
+		      "version_string_rw: %s", r.version_string_rw);
+	zassert_equal(r.current_image, EC_IMAGE_UNKNOWN, "current_image: %s",
+		      r.current_image);
+}
diff --git a/zephyr/test/system_common/src/reboot.c b/zephyr/test/system_common/src/reboot.c
new file mode 100644
index 0000000000..e5d494cd4c
--- /dev/null
+++ b/zephyr/test/system_common/src/reboot.c
@@ -0,0 +1,287 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "host_command.h"
+#include "system.h"
+
+#include <zephyr/device.h>
+#include <zephyr/fff.h>
+#include <zephyr/ztest_assert.h>
+#include <zephyr/ztest_test_new.h>
+
+FAKE_VOID_FUNC(system_reset, int);
+FAKE_VOID_FUNC(system_hibernate, uint32_t, uint32_t);
+
+ZTEST_SUITE(console_cmd_reboot, NULL, NULL, NULL, NULL, NULL);
+
+ZTEST(console_cmd_reboot, test_reboot_valid)
+{
+	int ret;
+	int i;
+
+	struct {
+		char *cmd;
+		int expect_called;
+		int expect_flags;
+	} tests[] = {
+		{
+			.cmd = "reboot hard",
+			.expect_called = 1,
+			.expect_flags = SYSTEM_RESET_MANUALLY_TRIGGERED |
+					SYSTEM_RESET_HARD,
+		},
+		{
+			.cmd = "reboot cold",
+			.expect_called = 1,
+			.expect_flags = SYSTEM_RESET_MANUALLY_TRIGGERED |
+					SYSTEM_RESET_HARD,
+		},
+		{
+			.cmd = "reboot soft",
+			.expect_called = 1,
+			.expect_flags = SYSTEM_RESET_MANUALLY_TRIGGERED,
+		},
+		{
+			.cmd = "reboot ap-off",
+			.expect_called = 1,
+			.expect_flags = SYSTEM_RESET_MANUALLY_TRIGGERED |
+					SYSTEM_RESET_LEAVE_AP_OFF,
+		},
+		{
+			.cmd = "reboot ap-off-in-ro",
+			.expect_called = 1,
+			.expect_flags = SYSTEM_RESET_MANUALLY_TRIGGERED |
+					SYSTEM_RESET_LEAVE_AP_OFF |
+					SYSTEM_RESET_STAY_IN_RO,
+		},
+		{
+			.cmd = "reboot ro",
+			.expect_called = 1,
+			.expect_flags = SYSTEM_RESET_MANUALLY_TRIGGERED |
+					SYSTEM_RESET_STAY_IN_RO,
+		},
+		{
+			.cmd = "reboot cancel",
+			.expect_called = 0,
+			.expect_flags = 0,
+		},
+		{
+			.cmd = "reboot preserve",
+			.expect_called = 1,
+			.expect_flags = SYSTEM_RESET_MANUALLY_TRIGGERED |
+					SYSTEM_RESET_PRESERVE_FLAGS,
+		},
+		{
+			.cmd = "reboot wait-ext",
+			.expect_called = 1,
+			.expect_flags = SYSTEM_RESET_MANUALLY_TRIGGERED |
+					SYSTEM_RESET_WAIT_EXT,
+		},
+	};
+
+	for (i = 0; i < ARRAY_SIZE(tests); i++) {
+		char *cmd = tests[i].cmd;
+
+		RESET_FAKE(system_reset);
+		RESET_FAKE(system_hibernate);
+
+		ret = shell_execute_cmd(get_ec_shell(), cmd);
+
+		zassert_equal(ret, EC_SUCCESS,
+			      "Unexpected return value for '%s': %d", cmd, ret);
+		zassert_equal(system_reset_fake.call_count,
+			      tests[i].expect_called,
+			      "Unexpected call count for '%s': %d", cmd,
+			      system_reset_fake.call_count);
+		zassert_equal(system_reset_fake.arg0_history[0],
+			      tests[i].expect_flags,
+			      "Unexpected flags for '%s': %x", cmd,
+			      system_reset_fake.arg0_history[0]);
+	}
+}
+
+ZTEST(console_cmd_reboot, test_reboot_invalid)
+{
+	int ret;
+
+	ret = shell_execute_cmd(get_ec_shell(), "reboot i-am-not-an-argument");
+
+	zassert_equal(ret, EC_ERROR_PARAM1, "invalid return value: %d", ret);
+	zassert_equal(system_reset_fake.call_count, 0,
+		      "Unexpected call count: %d",
+		      system_reset_fake.call_count);
+}
+
+ZTEST_SUITE(host_cmd_reboot, NULL, NULL, NULL, NULL, NULL);
+
+ZTEST(host_cmd_reboot, test_reboot)
+{
+	int ret;
+	int i;
+	struct ec_params_reboot_ec p;
+	int reboot_at_shutdown;
+
+	struct {
+		uint8_t cmd;
+		uint8_t flags;
+		int expect_return;
+		int expect_reboot_at_shutdown;
+		int expect_reset_called;
+		int expect_reset_flags;
+		int expect_hibernate_called;
+	} tests[] = {
+		{
+			.cmd = EC_REBOOT_CANCEL,
+			.flags = 0,
+			.expect_return = EC_RES_SUCCESS,
+			.expect_reboot_at_shutdown = EC_REBOOT_CANCEL,
+			.expect_reset_called = 0,
+			.expect_reset_flags = 0,
+			.expect_hibernate_called = 0,
+		},
+		{
+			.cmd = EC_REBOOT_COLD,
+			.flags = EC_REBOOT_FLAG_SWITCH_RW_SLOT,
+			.expect_return = EC_RES_INVALID_PARAM,
+			.expect_reboot_at_shutdown = 0,
+			.expect_reset_called = 0,
+			.expect_reset_flags = 0,
+			.expect_hibernate_called = 0,
+		},
+		{
+			.cmd = 0xaa, /* cmd passed unmodified */
+			.flags = EC_REBOOT_FLAG_ON_AP_SHUTDOWN,
+			.expect_return = EC_RES_SUCCESS,
+			.expect_reboot_at_shutdown = 0xaa,
+			.expect_reset_called = 0,
+			.expect_reset_flags = 0,
+			.expect_hibernate_called = 0,
+		},
+		{
+			.cmd = 0x55, /* cmd passed unmodified */
+			.flags = EC_REBOOT_FLAG_ON_AP_SHUTDOWN,
+			.expect_return = EC_RES_SUCCESS,
+			.expect_reboot_at_shutdown = 0x55,
+			.expect_reset_called = 0,
+			.expect_reset_flags = 0,
+			.expect_hibernate_called = 0,
+		},
+		{
+			.cmd = EC_REBOOT_COLD,
+			.flags = 0,
+			.expect_return = EC_RES_ERROR,
+			.expect_reboot_at_shutdown = EC_REBOOT_CANCEL,
+			.expect_reset_called = 1,
+			.expect_reset_flags = SYSTEM_RESET_HARD,
+			.expect_hibernate_called = 0,
+		},
+		{
+			.cmd = EC_REBOOT_HIBERNATE,
+			.flags = 0,
+			.expect_return = EC_RES_ERROR,
+			.expect_reboot_at_shutdown = EC_REBOOT_CANCEL,
+			.expect_reset_called = 0,
+			.expect_reset_flags = 0,
+			.expect_hibernate_called = 1,
+		},
+		{
+			.cmd = EC_REBOOT_COLD_AP_OFF,
+			.flags = 0,
+			.expect_return = EC_RES_ERROR,
+			.expect_reboot_at_shutdown = EC_REBOOT_CANCEL,
+			.expect_reset_called = 1,
+			.expect_reset_flags = SYSTEM_RESET_HARD |
+					      SYSTEM_RESET_LEAVE_AP_OFF,
+			.expect_hibernate_called = 0,
+		},
+		{
+			.cmd = 0xff,
+			.flags = 0,
+			.expect_return = EC_RES_INVALID_PARAM,
+			.expect_reboot_at_shutdown = EC_REBOOT_CANCEL,
+			.expect_reset_called = 0,
+			.expect_reset_flags = 0,
+			.expect_hibernate_called = 0,
+		},
+	};
+
+	for (i = 0; i < ARRAY_SIZE(tests); i++) {
+		p.cmd = tests[i].cmd;
+		p.flags = tests[i].flags;
+
+		RESET_FAKE(system_reset);
+		RESET_FAKE(system_hibernate);
+
+		ret = ec_cmd_reboot_ec(NULL, &p);
+
+		zassert_equal(ret, tests[i].expect_return,
+			      "Unexpected return value (%d): %d", i, ret);
+		reboot_at_shutdown =
+			system_common_get_reset_reboot_at_shutdown();
+		zassert_equal(
+			reboot_at_shutdown, tests[i].expect_reboot_at_shutdown,
+			"Unexpected value for reboot_at_shutdown (%d): %d", i,
+			reboot_at_shutdown);
+		zassert_equal(system_reset_fake.call_count,
+			      tests[i].expect_reset_called,
+			      "Unexpected reset call count (%d): %d", i,
+			      system_reset_fake.call_count);
+		zassert_equal(system_reset_fake.arg0_history[0],
+			      tests[i].expect_reset_flags,
+			      "Unexpected flags (%d): %x", i,
+			      system_reset_fake.arg0_history[0]);
+		zassert_equal(system_hibernate_fake.call_count,
+			      tests[i].expect_hibernate_called,
+			      "Unexpected hibernate call count (%d): %d", i,
+			      system_hibernate_fake.call_count);
+	}
+}
+
+ZTEST_SUITE(console_cmd_hibernate, NULL, NULL, NULL, NULL, NULL);
+
+int chipset_in_state(int state_mask)
+{
+	return 0;
+}
+
+ZTEST(console_cmd_hibernate, test_hibernate_default)
+{
+	int ret;
+
+	RESET_FAKE(system_hibernate);
+
+	ret = shell_execute_cmd(get_ec_shell(), "hibernate");
+
+	zassert_equal(ret, EC_SUCCESS, "Unexpected return value: %d", ret);
+	zassert_equal(system_hibernate_fake.call_count, 1,
+		      "Unexpected hibernate call count: %d",
+		      system_hibernate_fake.call_count);
+	zassert_equal(system_hibernate_fake.arg0_history[0], 0,
+		      "Unexpected hibernate_secondst: %d",
+		      system_hibernate_fake.arg0_history[0]);
+	zassert_equal(system_hibernate_fake.arg1_history[0], 0,
+		      "Unexpected hibernate_secondst: %d",
+		      system_hibernate_fake.arg1_history[0]);
+}
+
+ZTEST(console_cmd_hibernate, test_hibernate_args)
+{
+	int ret;
+
+	RESET_FAKE(system_hibernate);
+
+	ret = shell_execute_cmd(get_ec_shell(), "hibernate 123 456");
+
+	zassert_equal(ret, EC_SUCCESS, "Unexpected return value: %d", ret);
+	zassert_equal(system_hibernate_fake.call_count, 1,
+		      "Unexpected hibernate call count: %d",
+		      system_hibernate_fake.call_count);
+	zassert_equal(system_hibernate_fake.arg0_history[0], 123,
+		      "Unexpected hibernate_secondst: %d",
+		      system_hibernate_fake.arg0_history[0]);
+	zassert_equal(system_hibernate_fake.arg1_history[0], 456,
+		      "Unexpected hibernate_secondst: %d",
+		      system_hibernate_fake.arg1_history[0]);
+}
diff --git a/zephyr/test/system_common/src/system_is_locked.c b/zephyr/test/system_common/src/system_is_locked.c
new file mode 100644
index 0000000000..d880e4e117
--- /dev/null
+++ b/zephyr/test/system_common/src/system_is_locked.c
@@ -0,0 +1,31 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "system.h"
+
+#include <zephyr/shell/shell_dummy.h>
+#include <zephyr/ztest_assert.h>
+#include <zephyr/ztest_test_new.h>
+
+ZTEST_USER(system_is_locked, test_syslock_console_cmd)
+{
+	/*
+	 * Integration test that validates the syslock console command forces
+	 * the system_is_locked command to return true
+	 */
+
+	const struct shell *shell_zephyr = get_ec_shell();
+
+	shell_backend_dummy_clear_output(shell_zephyr);
+
+	zassert_false(system_is_locked());
+	/*
+	 * TODO(b/249373175): Use CHECK_CONSOLE_CMD() macro
+	 */
+	zassert_ok(shell_execute_cmd(shell_zephyr, "syslock"), NULL);
+	zassert_true(system_is_locked());
+}
+
+ZTEST_SUITE(system_is_locked, NULL, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/system_common/testcase.yaml b/zephyr/test/system_common/testcase.yaml
new file mode 100644
index 0000000000..f30d0e52f1
--- /dev/null
+++ b/zephyr/test/system_common/testcase.yaml
@@ -0,0 +1,11 @@
+common:
+  platform_allow: native_posix
+tests:
+  system.default:
+    extra_configs:
+      - CONFIG_SHELL_BACKEND_DUMMY=y
+      - CONFIG_SHELL_BACKEND_DUMMY_BUF_SIZE=1000
+      - CONFIG_SHELL_BACKEND_SERIAL=n
+    tags:
+      common
+      system
diff --git a/zephyr/test/system_safe_mode/CMakeLists.txt b/zephyr/test/system_safe_mode/CMakeLists.txt
new file mode 100644
index 0000000000..3e358951db
--- /dev/null
+++ b/zephyr/test/system_safe_mode/CMakeLists.txt
@@ -0,0 +1,13 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(system_safe_mode)
+
+# Include FFF fakes
+add_subdirectory(${PLATFORM_EC}/zephyr/test/test_utils test_utils)
+
+target_sources_ifdef(CONFIG_PLATFORM_EC_SYSTEM_SAFE_MODE app PRIVATE "src/system_safe_mode.c")
+target_sources_ifndef(CONFIG_PLATFORM_EC_SYSTEM_SAFE_MODE app PRIVATE "src/system_safe_mode_disabled.c")
diff --git a/zephyr/test/system_safe_mode/boards/native_posix.overlay b/zephyr/test/system_safe_mode/boards/native_posix.overlay
new file mode 100644
index 0000000000..9f3238d076
--- /dev/null
+++ b/zephyr/test/system_safe_mode/boards/native_posix.overlay
@@ -0,0 +1,33 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <board-overlays/native_posix.dts>
+#include <cros/binman.dtsi>
+
+/ {
+	chosen {
+		cros-ec,flash = &flash1;
+		cros-ec,flash-controller = &cros_flash;
+	};
+	aliases {
+		gpio-wp = &gpio_wp_l;
+	};
+	named-gpios {
+		compatible = "named-gpios";
+		gpio_wp_l: wp_l {
+			gpios = <&gpio0 3 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+	};
+	cros_flash: cros-flash {
+		compatible = "cros-ec,flash-emul";
+	};
+	flash1: flash@64000000 {
+		reg = <0x64000000 DT_SIZE_K(512)>;
+	};
+};
+
+&gpio0 {
+	ngpios = <4>;
+};
diff --git a/zephyr/test/system_safe_mode/prj.conf b/zephyr/test/system_safe_mode/prj.conf
new file mode 100644
index 0000000000..bb6c6906c8
--- /dev/null
+++ b/zephyr/test/system_safe_mode/prj.conf
@@ -0,0 +1,22 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_ZTEST=y
+CONFIG_ZTEST_NEW_API=y
+CONFIG_PLATFORM_EC=y
+CONFIG_CROS_EC=y
+CONFIG_FLASH=y
+CONFIG_SYSTEM_FAKE=y
+CONFIG_PLATFORM_EC_SYSTEM_SAFE_MODE=y
+CONFIG_PLATFORM_EC_SYSTEM_SAFE_MODE_PRINT_STACK=y
+CONFIG_TASK_HOSTCMD_THREAD_DEDICATED=y
+CONFIG_PLATFORM_EC_HOSTCMD=y
+CONFIG_ASSERT_TEST=y
+CONFIG_SHIMMED_TASKS=y
+CONFIG_TASKS_SET_TEST_RUNNER_TID_RULE=y
+
+# Disable because not needed
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
+CONFIG_PLATFORM_EC_SWITCH=n
+CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGEN=n
diff --git a/zephyr/test/system_safe_mode/src/system_safe_mode.c b/zephyr/test/system_safe_mode/src/system_safe_mode.c
new file mode 100644
index 0000000000..4351805a39
--- /dev/null
+++ b/zephyr/test/system_safe_mode/src/system_safe_mode.c
@@ -0,0 +1,224 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "ec_commands.h"
+#include "ec_tasks.h"
+#include "host_command.h"
+#include "panic.h"
+#include "system.h"
+#include "system_fake.h"
+#include "system_safe_mode.h"
+#include "uart.h"
+
+#include <zephyr/fff.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+#include <regex.h>
+
+FAKE_VOID_FUNC(system_reset, int);
+
+static void system_before(void *data)
+{
+	RESET_FAKE(system_reset);
+	set_system_safe_mode(false);
+	get_panic_data_write()->flags = 0;
+	system_set_shrspi_image_copy(EC_IMAGE_RW);
+	shell_start(get_ec_shell());
+}
+
+static void enter_safe_mode_cb(struct k_timer *unused)
+{
+	k_sys_fatal_error_handler(K_ERR_CPU_EXCEPTION, NULL);
+}
+K_TIMER_DEFINE(enter_safe_mode, enter_safe_mode_cb, NULL);
+
+ZTEST_USER(system_safe_mode, test_feature_present)
+{
+	struct ec_response_get_features feat;
+
+	zassert_ok(ec_cmd_get_features(NULL, &feat), "Failed to get features");
+
+	zassert_true(feat.flags[1] &
+		     EC_FEATURE_MASK_1(EC_FEATURE_SYSTEM_SAFE_MODE));
+}
+
+ZTEST_USER(system_safe_mode, test_safe_mode_from_critical_task)
+{
+	/**
+	 * Timer callback will run in sysworkq, which is a critical
+	 * thread, so safe mode should not run.
+	 */
+	k_timer_start(&enter_safe_mode, K_NO_WAIT, K_NO_WAIT);
+	/* Short wait to ensure enter_safe_mode_cb has a chance to run */
+	k_msleep(100);
+	zassert_false(system_is_in_safe_mode());
+	zassert_false(get_panic_data_write()->flags &
+		      PANIC_DATA_FLAG_SAFE_MODE_STARTED);
+	zassert_true(get_panic_data_write()->flags &
+		     PANIC_DATA_FLAG_SAFE_MODE_FAIL_PRECONDITIONS);
+	zassert_equal(1, system_reset_fake.call_count);
+}
+
+ZTEST_USER(system_safe_mode, test_enter_safe_mode_from_ro)
+{
+	system_set_shrspi_image_copy(EC_IMAGE_RO);
+	k_sys_fatal_error_handler(K_ERR_CPU_EXCEPTION, NULL);
+	zassert_false(system_is_in_safe_mode());
+	zassert_false(get_panic_data_write()->flags &
+		      PANIC_DATA_FLAG_SAFE_MODE_STARTED);
+	zassert_true(get_panic_data_write()->flags &
+		     PANIC_DATA_FLAG_SAFE_MODE_FAIL_PRECONDITIONS);
+	zassert_equal(1, system_reset_fake.call_count);
+}
+
+ZTEST_USER(system_safe_mode, test_enter_safe_mode_from_kernel_panic)
+{
+	system_set_shrspi_image_copy(EC_IMAGE_RO);
+	k_sys_fatal_error_handler(K_ERR_KERNEL_PANIC, NULL);
+	zassert_false(system_is_in_safe_mode());
+	zassert_false(get_panic_data_write()->flags &
+		      PANIC_DATA_FLAG_SAFE_MODE_STARTED);
+	zassert_true(get_panic_data_write()->flags &
+		     PANIC_DATA_FLAG_SAFE_MODE_FAIL_PRECONDITIONS);
+	zassert_equal(1, system_reset_fake.call_count);
+}
+
+ZTEST_USER(system_safe_mode, test_enter_safe_mode_twice)
+{
+	zassert_false(system_is_in_safe_mode());
+
+	k_sys_fatal_error_handler(K_ERR_CPU_EXCEPTION, NULL);
+	zassert_true(system_is_in_safe_mode());
+	zassert_true(get_panic_data_write()->flags &
+		     PANIC_DATA_FLAG_SAFE_MODE_STARTED);
+	zassert_false(get_panic_data_write()->flags &
+		      PANIC_DATA_FLAG_SAFE_MODE_FAIL_PRECONDITIONS);
+	zassert_equal(0, system_reset_fake.call_count);
+
+	k_sys_fatal_error_handler(K_ERR_CPU_EXCEPTION, NULL);
+	zassert_true(system_is_in_safe_mode());
+	zassert_true(get_panic_data_write()->flags &
+		     PANIC_DATA_FLAG_SAFE_MODE_STARTED);
+	zassert_true(get_panic_data_write()->flags &
+		     PANIC_DATA_FLAG_SAFE_MODE_FAIL_PRECONDITIONS);
+	zassert_equal(1, system_reset_fake.call_count);
+}
+
+ZTEST_USER(system_safe_mode, test_enter_safe_mode)
+{
+	zassert_false(system_is_in_safe_mode());
+
+	k_sys_fatal_error_handler(K_ERR_CPU_EXCEPTION, NULL);
+	zassert_equal(0, system_reset_fake.call_count);
+	zassert_true(system_is_in_safe_mode());
+	zassert_true(get_panic_data_write()->flags &
+		     PANIC_DATA_FLAG_SAFE_MODE_STARTED);
+	zassert_false(get_panic_data_write()->flags &
+		      PANIC_DATA_FLAG_SAFE_MODE_FAIL_PRECONDITIONS);
+}
+
+ZTEST_USER(system_safe_mode, test_safe_mode_reboot)
+{
+	zassert_false(system_is_in_safe_mode());
+	k_sys_fatal_error_handler(0, NULL);
+	zassert_true(system_is_in_safe_mode());
+	zassert_equal(0, system_reset_fake.call_count);
+
+	/* Wait half of timeout and system hasn't rebooted yet */
+	k_msleep(CONFIG_PLATFORM_EC_SYSTEM_SAFE_MODE_TIMEOUT_MSEC / 2);
+	zassert_equal(0, system_reset_fake.call_count);
+
+	k_msleep(CONFIG_PLATFORM_EC_SYSTEM_SAFE_MODE_TIMEOUT_MSEC / 2);
+	zassert_equal(1, system_reset_fake.call_count);
+}
+
+ZTEST_USER(system_safe_mode, test_blocked_command_in_safe_mode)
+{
+	struct ec_params_gpio_get cmd_params = {
+		.name = "wp_l",
+	};
+	struct ec_response_gpio_get cmd_response;
+
+	zassert_false(system_is_in_safe_mode());
+	zassert_ok(ec_cmd_gpio_get(NULL, &cmd_params, &cmd_response));
+
+	k_sys_fatal_error_handler(K_ERR_CPU_EXCEPTION, NULL);
+
+	zassert_true(system_is_in_safe_mode());
+	zassert_true(ec_cmd_gpio_get(NULL, &cmd_params, &cmd_response));
+}
+
+ZTEST_USER(system_safe_mode, test_panic_event_notify)
+{
+#ifdef CONFIG_HOSTCMD_X86
+	/* Enable the EC_HOST_EVENT_PANIC event in the lpc mask */
+	host_event_t lpc_event_mask;
+	host_event_t mask = EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC);
+
+	lpc_event_mask = lpc_get_host_event_mask(LPC_HOST_EVENT_SCI);
+	lpc_set_host_event_mask(LPC_HOST_EVENT_SCI, lpc_event_mask | mask);
+#endif
+
+	zassert_false(host_is_event_set(EC_HOST_EVENT_PANIC));
+	k_sys_fatal_error_handler(K_ERR_CPU_EXCEPTION, NULL);
+	/* Short sleep to allow hook task to run */
+	k_msleep(1);
+	zassert_true(host_is_event_set(EC_HOST_EVENT_PANIC));
+}
+
+static uint32_t fake_stack[] = {
+	0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a,
+	0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15,
+	0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
+};
+
+uint32_t get_panic_stack_pointer(const struct panic_data *pdata)
+{
+	return (uint32_t)fake_stack;
+}
+
+ZTEST_USER(system_safe_mode, test_print_stack_contents)
+{
+	char buffer[1024];
+	uint16_t write_count;
+	regex_t regex;
+
+	char *regex_str = "Stack Contents\n"
+			  "[0-9a-f]{8}: 00000000 00000001 00000002 00000003\n"
+			  "[0-9a-f]{8}: 00000004 00000005 00000006 00000007\n"
+			  "[0-9a-f]{8}: 00000008 00000009 0000000a 0000000b\n"
+			  "[0-9a-f]{8}: 0000000c 0000000d 0000000e 0000000f\n"
+			  "[0-9a-f]{8}: 00000010 00000011 00000012 00000013\n"
+			  "[0-9a-f]{8}: 00000014 00000015 00000016 00000017\n"
+			  "[0-9a-f]{8}: 00000018 00000019 0000001a 0000001b\n"
+			  "[0-9a-f]{8}: 0000001c 0000001d 0000001e 0000001f\n";
+
+	zassert_ok(regcomp(&regex, regex_str, REG_EXTENDED));
+
+	/* Snapshot console before panic */
+	zassert_ok(uart_console_read_buffer_init(), NULL);
+
+	k_sys_fatal_error_handler(K_ERR_CPU_EXCEPTION, NULL);
+	/* Short sleep to allow hook task to run */
+	k_msleep(1);
+	zassert_true(system_is_in_safe_mode());
+
+	/* Snapshot console after panic */
+	zassert_ok(uart_console_read_buffer_init(), NULL);
+
+	zassert_ok(uart_console_read_buffer(CONSOLE_READ_RECENT, buffer,
+					    sizeof(buffer), &write_count),
+		   NULL);
+	/* Need at least 405 bytes for match */
+	zassert_true(write_count >= 405);
+
+	/* Check for expected stack print in console buffer */
+	zassert_ok(regexec(&regex, buffer, 0, NULL, 0));
+	regfree(&regex);
+}
+
+ZTEST_SUITE(system_safe_mode, NULL, NULL, system_before, NULL, NULL);
diff --git a/zephyr/test/system_safe_mode/src/system_safe_mode_disabled.c b/zephyr/test/system_safe_mode/src/system_safe_mode_disabled.c
new file mode 100644
index 0000000000..43c59dd0ee
--- /dev/null
+++ b/zephyr/test/system_safe_mode/src/system_safe_mode_disabled.c
@@ -0,0 +1,25 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+#include "host_command.h"
+#include "system.h"
+#include "system_fake.h"
+#include "system_safe_mode.h"
+
+#include <zephyr/fff.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+ZTEST_USER(system_safe_mode_disabled, test_feature_not_present)
+{
+	struct ec_response_get_features feat;
+
+	zassert_ok(ec_cmd_get_features(NULL, &feat), "Failed to get features");
+
+	zassert_false(feat.flags[1] &
+		      EC_FEATURE_MASK_1(EC_FEATURE_SYSTEM_SAFE_MODE));
+}
+ZTEST_SUITE(system_safe_mode_disabled, NULL, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/system_safe_mode/testcase.yaml b/zephyr/test/system_safe_mode/testcase.yaml
new file mode 100644
index 0000000000..97fad3abef
--- /dev/null
+++ b/zephyr/test/system_safe_mode/testcase.yaml
@@ -0,0 +1,14 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+common:
+  platform_allow: native_posix
+tests:
+  system_safe_mode.default:
+    tags:
+      common
+      system
+  system_safe_mode.disabled:
+    extra_configs:
+      - CONFIG_PLATFORM_EC_SYSTEM_SAFE_MODE=n
diff --git a/zephyr/test/system_shim/CMakeLists.txt b/zephyr/test/system_shim/CMakeLists.txt
new file mode 100644
index 0000000000..1e8ae4a6ff
--- /dev/null
+++ b/zephyr/test/system_shim/CMakeLists.txt
@@ -0,0 +1,16 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(system_shim_test)
+
+# Include FFF fakes
+add_subdirectory(${PLATFORM_EC}/zephyr/test/test_utils test_utils)
+
+if(CONFIG_SYSTEM_SHIM_TEST_ISH)
+  include("${CMAKE_CURRENT_LIST_DIR}/test_ish.cmake")
+elseif(CONFIG_SYSTEM_SHIM_TEST_DEFAULT)
+  include("${CMAKE_CURRENT_LIST_DIR}/test_default.cmake")
+endif()
diff --git a/zephyr/test/system_shim/Kconfig b/zephyr/test/system_shim/Kconfig
new file mode 100644
index 0000000000..50e9767b6f
--- /dev/null
+++ b/zephyr/test/system_shim/Kconfig
@@ -0,0 +1,28 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config TEST_USB_PD_POLICY
+  bool
+  help
+    Stub config that's used in chipset.h to control the definition of
+    `chipset_in_state()` in tests. Each test must define this currently.
+
+choice SYSTEM_SHIM_TEST
+  prompt "Which shim to test"
+  default SYSTEM_SHIM_TEST_DEFAULT
+
+config SYSTEM_SHIM_TEST_DEFAULT
+  bool "Use the normal shim"
+  help
+    Build and run the default shim/src/system.c tests.
+
+config SYSTEM_SHIM_TEST_ISH
+  bool "Use the ISH shim"
+  select TEST_USB_PD_POLICY
+  help
+    Build and run the shim/src/ish_system.c tests.
+
+endchoice
+
+source "Kconfig.zephyr"
diff --git a/zephyr/test/system_shim/boards/native_posix.overlay b/zephyr/test/system_shim/boards/native_posix.overlay
new file mode 100644
index 0000000000..b08ea4bf7a
--- /dev/null
+++ b/zephyr/test/system_shim/boards/native_posix.overlay
@@ -0,0 +1,42 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <board-overlays/native_posix.dts>
+
+/ {
+
+	bbram: test-bbram-dev {
+		compatible = "zephyr,bbram-emul";
+		size = <64>;
+	};
+
+	named-bbram-regions {
+		compatible = "named-bbram-regions";
+		pd0 {
+			offset = <0x00>;
+			size = <0x01>;
+		};
+		pd1 {
+			offset = <0x01>;
+			size = <0x02>;
+		};
+		try_slot {
+			offset = <0x03>;
+			size = <0x04>;
+		};
+		pd2 {
+			offset = <0x07>;
+			size = <0x05>;
+		};
+		scratchpad: scratchpad {
+			offset = <0x0c>;
+			size = <0x04>;
+		};
+		saved-reset-flags {
+			offset = <0x10>;
+			size = <0x04>;
+		};
+	};
+};
diff --git a/zephyr/test/system_shim/default.overlay b/zephyr/test/system_shim/default.overlay
new file mode 100644
index 0000000000..13ceee9c19
--- /dev/null
+++ b/zephyr/test/system_shim/default.overlay
@@ -0,0 +1,12 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "boards/native_posix.overlay"
+
+/ {
+	chosen {
+		cros-ec,bbram = &bbram;
+	};
+};
diff --git a/zephyr/test/system_shim/include/fakes.h b/zephyr/test/system_shim/include/fakes.h
new file mode 100644
index 0000000000..29031a10b7
--- /dev/null
+++ b/zephyr/test/system_shim/include/fakes.h
@@ -0,0 +1,31 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef ZEPHYR_TEST_SYSTEM_SHIM_INCLUDE_FAKES_H_
+#define ZEPHYR_TEST_SYSTEM_SHIM_INCLUDE_FAKES_H_
+
+#include <stdint.h>
+
+#include <zephyr/fff.h>
+
+DECLARE_FAKE_VALUE_FUNC(int, cros_system_native_posix_get_reset_cause,
+			const struct device *);
+DECLARE_FAKE_VALUE_FUNC(uint64_t, cros_system_native_posix_deep_sleep_ticks,
+			const struct device *);
+DECLARE_FAKE_VALUE_FUNC(int, cros_system_native_posix_hibernate,
+			const struct device *, uint32_t, uint32_t);
+DECLARE_FAKE_VALUE_FUNC(const char *, cros_system_native_posix_get_chip_vendor,
+			const struct device *);
+DECLARE_FAKE_VALUE_FUNC(const char *, cros_system_native_posix_get_chip_name,
+			const struct device *);
+DECLARE_FAKE_VALUE_FUNC(const char *,
+			cros_system_native_posix_get_chip_revision,
+			const struct device *);
+DECLARE_FAKE_VALUE_FUNC(int, cros_system_native_posix_soc_reset,
+			const struct device *);
+DECLARE_FAKE_VOID_FUNC(watchdog_reload);
+DECLARE_FAKE_VOID_FUNC(board_hibernate);
+
+#endif /* ZEPHYR_TEST_SYSTEM_SHIM_INCLUDE_FAKES_H_ */
diff --git a/zephyr/test/system_shim/prj.conf b/zephyr/test/system_shim/prj.conf
new file mode 100644
index 0000000000..6de45ead48
--- /dev/null
+++ b/zephyr/test/system_shim/prj.conf
@@ -0,0 +1,21 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_ZTEST=y
+CONFIG_ZTEST_NEW_API=y
+CONFIG_PLATFORM_EC=y
+CONFIG_CROS_EC=y
+CONFIG_BBRAM=y
+
+CONFIG_PLATFORM_EC_BOARD_RESET_AFTER_POWER_ON=y
+
+# Make console work
+CONFIG_SERIAL=y
+CONFIG_SHELL_BACKEND_DUMMY=y
+CONFIG_SHELL_BACKEND_DUMMY_BUF_SIZE=1000
+CONFIG_SHELL_BACKEND_SERIAL=n
+
+# Make cros_system driver work
+CONFIG_PM=y
+CONFIG_CROS_SYSTEM_NATIVE_POSIX=y
diff --git a/zephyr/test/system_shim/src/no_chosen.c b/zephyr/test/system_shim/src/no_chosen.c
new file mode 100644
index 0000000000..0e41d562b9
--- /dev/null
+++ b/zephyr/test/system_shim/src/no_chosen.c
@@ -0,0 +1,24 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "fakes.h"
+#include "system.h"
+
+#include <zephyr/ztest.h>
+
+ZTEST(system, test_fail_get_bbram_no_device)
+{
+	zassert_equal(EC_ERROR_INVAL, system_get_bbram(0, NULL));
+}
+
+ZTEST(system, test_fail_set_scratchpad)
+{
+	zassert_equal(-EC_ERROR_INVAL, system_set_scratchpad(0));
+}
+
+ZTEST(system, test_fail_get_scratchpad)
+{
+	zassert_equal(-EC_ERROR_INVAL, system_get_scratchpad(NULL));
+}
diff --git a/zephyr/test/system_shim/src/suite.c b/zephyr/test/system_shim/src/suite.c
new file mode 100644
index 0000000000..b430780d0a
--- /dev/null
+++ b/zephyr/test/system_shim/src/suite.c
@@ -0,0 +1,50 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "fakes.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/bbram.h>
+#include <zephyr/fff.h>
+#include <zephyr/ztest.h>
+
+DEFINE_FAKE_VALUE_FUNC(int, cros_system_native_posix_get_reset_cause,
+		       const struct device *);
+DEFINE_FAKE_VALUE_FUNC(uint64_t, cros_system_native_posix_deep_sleep_ticks,
+		       const struct device *);
+DEFINE_FAKE_VALUE_FUNC(int, cros_system_native_posix_hibernate,
+		       const struct device *, uint32_t, uint32_t);
+DEFINE_FAKE_VALUE_FUNC(const char *, cros_system_native_posix_get_chip_vendor,
+		       const struct device *);
+DEFINE_FAKE_VALUE_FUNC(const char *, cros_system_native_posix_get_chip_name,
+		       const struct device *);
+DEFINE_FAKE_VALUE_FUNC(const char *, cros_system_native_posix_get_chip_revision,
+		       const struct device *);
+DEFINE_FAKE_VALUE_FUNC(int, cros_system_native_posix_soc_reset,
+		       const struct device *);
+DEFINE_FAKE_VOID_FUNC(watchdog_reload);
+DEFINE_FAKE_VOID_FUNC(board_hibernate);
+
+static void system_before_after(void *test_data)
+{
+	const struct device *bbram_dev =
+		DEVICE_DT_GET_OR_NULL(DT_CHOSEN(cros_ec_bbram));
+
+	RESET_FAKE(cros_system_native_posix_get_reset_cause);
+	RESET_FAKE(cros_system_native_posix_deep_sleep_ticks);
+	RESET_FAKE(cros_system_native_posix_hibernate);
+	RESET_FAKE(cros_system_native_posix_get_chip_vendor);
+	RESET_FAKE(cros_system_native_posix_get_chip_name);
+	RESET_FAKE(cros_system_native_posix_get_chip_revision);
+	RESET_FAKE(cros_system_native_posix_soc_reset);
+	RESET_FAKE(watchdog_reload);
+	RESET_FAKE(board_hibernate);
+
+	if (bbram_dev != NULL) {
+		bbram_emul_set_invalid(bbram_dev, false);
+	}
+}
+
+ZTEST_SUITE(system, NULL, NULL, system_before_after, system_before_after, NULL);
diff --git a/zephyr/test/system_shim/src/test_ish_system.c b/zephyr/test/system_shim/src/test_ish_system.c
new file mode 100644
index 0000000000..ef50b59b2a
--- /dev/null
+++ b/zephyr/test/system_shim/src/test_ish_system.c
@@ -0,0 +1,64 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "chipset.h"
+#include "system.h"
+
+#include <zephyr/device.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/shell/shell_dummy.h>
+#include <zephyr/ztest_assert.h>
+#include <zephyr/ztest_test_new.h>
+
+LOG_MODULE_REGISTER(test);
+
+ZTEST_SUITE(system, NULL, NULL, NULL, NULL, NULL);
+
+ZTEST(system, test_chipset_in_state)
+{
+	zassert_equal(CHIPSET_STATE_ON, chipset_in_state(CHIPSET_STATE_ON));
+	zassert_equal(0, chipset_in_state(CHIPSET_STATE_SUSPEND));
+}
+
+ZTEST(system, test_bbram_get)
+{
+	zassert_equal(EC_ERROR_UNIMPLEMENTED,
+		      system_get_bbram(SYSTEM_BBRAM_IDX_TRY_SLOT, NULL));
+}
+
+ZTEST(system, test_bbram_set)
+{
+	zassert_equal(EC_ERROR_UNIMPLEMENTED,
+		      system_set_bbram(SYSTEM_BBRAM_IDX_TRY_SLOT, 0));
+}
+
+ZTEST(system, test_save_read_chip_reset_flags)
+{
+	chip_save_reset_flags(0);
+	zassert_equal(chip_read_reset_flags(), EC_RESET_FLAG_POWER_ON);
+}
+
+ZTEST(system, test_set_get_scratchpad)
+{
+	uint32_t set_value = 0x1234;
+	uint32_t read_value;
+
+	zassert_equal(EC_ERROR_UNIMPLEMENTED, system_set_scratchpad(set_value));
+	zassert_equal(EC_ERROR_UNIMPLEMENTED,
+		      system_get_scratchpad(&read_value));
+}
+
+ZTEST(system, test_ish_system_get_chip_values)
+{
+	/* Vendor */
+	zassert_mem_equal(system_get_chip_vendor(), "Intel", sizeof("Intel"));
+
+	/* Name */
+	zassert_mem_equal(system_get_chip_name(), "Intel x86",
+			  sizeof("Intel x86"));
+
+	/* Revision */
+	zassert_mem_equal(system_get_chip_revision(), "", sizeof(""));
+}
diff --git a/zephyr/test/system_shim/src/test_system.c b/zephyr/test/system_shim/src/test_system.c
new file mode 100644
index 0000000000..cd58fcf604
--- /dev/null
+++ b/zephyr/test/system_shim/src/test_system.c
@@ -0,0 +1,295 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "bbram.h"
+#include "drivers/cros_system.h"
+#include "fakes.h"
+#include "system.h"
+
+#include <setjmp.h>
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/bbram.h>
+#include <zephyr/fff.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/shell/shell_dummy.h>
+#include <zephyr/ztest_assert.h>
+#include <zephyr/ztest_test_new.h>
+
+LOG_MODULE_REGISTER(test);
+
+static char mock_data[64] =
+	"abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789!@";
+
+int system_preinitialize(const struct device *unused);
+
+ZTEST(system, test_invalid_bbram_index)
+{
+	zassert_equal(EC_ERROR_INVAL,
+		      system_get_bbram(SYSTEM_BBRAM_IDX_TRY_SLOT + 1, NULL));
+}
+
+ZTEST(system, test_bbram_get)
+{
+	const struct device *const bbram_dev =
+		DEVICE_DT_GET(DT_CHOSEN(cros_ec_bbram));
+	uint8_t output[10];
+	int rc;
+
+	/* Write expected data to read back */
+	rc = bbram_write(bbram_dev, 0, ARRAY_SIZE(mock_data), mock_data);
+	zassert_ok(rc);
+
+	rc = system_get_bbram(SYSTEM_BBRAM_IDX_PD0, output);
+	zassert_ok(rc);
+	zassert_mem_equal(output, mock_data + BBRAM_REGION_OFFSET(pd0),
+			  BBRAM_REGION_SIZE(pd0), NULL);
+
+	rc = system_get_bbram(SYSTEM_BBRAM_IDX_PD1, output);
+	zassert_ok(rc);
+	zassert_mem_equal(output, mock_data + BBRAM_REGION_OFFSET(pd1),
+			  BBRAM_REGION_SIZE(pd1), NULL);
+
+	rc = system_get_bbram(SYSTEM_BBRAM_IDX_PD2, output);
+	zassert_ok(rc);
+	zassert_mem_equal(output, mock_data + BBRAM_REGION_OFFSET(pd2),
+			  BBRAM_REGION_SIZE(pd2), NULL);
+
+	rc = system_get_bbram(SYSTEM_BBRAM_IDX_TRY_SLOT, output);
+	zassert_ok(rc);
+	zassert_mem_equal(output, mock_data + BBRAM_REGION_OFFSET(try_slot),
+			  BBRAM_REGION_SIZE(try_slot), NULL);
+}
+
+ZTEST(system, test_save_read_chip_reset_flags)
+{
+	uint32_t arbitrary_flags = 0x1234;
+
+	chip_save_reset_flags(0);
+	chip_save_reset_flags(arbitrary_flags);
+	zassert_equal(chip_read_reset_flags(), arbitrary_flags);
+}
+
+ZTEST(system, test_system_set_get_scratchpad)
+{
+	/* Arbitrary values */
+	uint32_t scratch_set = 0x1234;
+	uint32_t scratch_read;
+
+	system_set_scratchpad(scratch_set);
+	system_get_scratchpad(&scratch_read);
+	zassert_equal(scratch_read, scratch_set);
+}
+
+ZTEST(system, test_system_get_scratchpad_fail)
+{
+	const struct device *bbram_dev =
+		DEVICE_DT_GET(DT_CHOSEN(cros_ec_bbram));
+
+	zassert_ok(bbram_emul_set_invalid(bbram_dev, true));
+	zassert_equal(-EC_ERROR_INVAL, system_get_scratchpad(NULL));
+}
+
+static jmp_buf jmp_hibernate;
+
+static int _test_cros_system_native_posix_hibernate(const struct device *dev,
+						    uint32_t seconds,
+						    uint32_t microseconds)
+{
+	longjmp(jmp_hibernate, 1);
+
+	return 0;
+}
+
+ZTEST(system, test_system_hibernate)
+{
+	/*
+	 * Due to setjmp usage, this test provides no coverage, but does
+	 * actually cover the code. This is due to a bug in LCOV.
+	 */
+	const struct device *sys_dev = device_get_binding("CROS_SYSTEM");
+	int ret = setjmp(jmp_hibernate);
+	/* Validate 0th and last bit preserved*/
+	uint32_t secs = BIT(31) + 1;
+	uint32_t msecs = BIT(31) + 3;
+
+	zassert_not_null(sys_dev);
+
+	cros_system_native_posix_hibernate_fake.custom_fake =
+		_test_cros_system_native_posix_hibernate;
+
+	if (ret == 0) {
+		system_hibernate(secs, msecs);
+	}
+
+	zassert_not_equal(ret, 0);
+
+	zassert_equal(cros_system_native_posix_hibernate_fake.call_count, 1);
+	zassert_equal(cros_system_native_posix_hibernate_fake.arg0_val,
+		      sys_dev);
+	zassert_equal(cros_system_native_posix_hibernate_fake.arg1_val, secs);
+	zassert_equal(cros_system_native_posix_hibernate_fake.arg2_val, msecs);
+	zassert_equal(board_hibernate_fake.call_count, 1);
+}
+
+ZTEST(system, test_system_hibernate__failure)
+{
+	const struct device *sys_dev = device_get_binding("CROS_SYSTEM");
+	/* Validate 0th and last bit preserved*/
+	uint32_t secs = BIT(31) + 1;
+	uint32_t msecs = BIT(31) + 3;
+
+	zassert_not_null(sys_dev);
+
+	cros_system_native_posix_hibernate_fake.return_val = -1;
+
+	system_hibernate(secs, msecs);
+
+	zassert_equal(cros_system_native_posix_hibernate_fake.call_count, 1);
+	zassert_equal(cros_system_native_posix_hibernate_fake.arg0_val,
+		      sys_dev);
+	zassert_equal(cros_system_native_posix_hibernate_fake.arg1_val, secs);
+	zassert_equal(cros_system_native_posix_hibernate_fake.arg2_val, msecs);
+}
+
+ZTEST(system, test_system_get_chip_values)
+{
+	const struct device *sys_dev = device_get_binding("CROS_SYSTEM");
+
+	zassert_not_null(sys_dev);
+
+	/* Vendor */
+	cros_system_native_posix_get_chip_vendor_fake.return_val = "a";
+	zassert_mem_equal(system_get_chip_vendor(), "a", sizeof("a"));
+	zassert_equal(cros_system_native_posix_get_chip_vendor_fake.call_count,
+		      1);
+	zassert_equal(cros_system_native_posix_get_chip_vendor_fake.arg0_val,
+		      sys_dev);
+
+	/* Name */
+	cros_system_native_posix_get_chip_name_fake.return_val = "b";
+	zassert_mem_equal(system_get_chip_name(), "b", sizeof("b"));
+	zassert_equal(cros_system_native_posix_get_chip_name_fake.call_count,
+		      1);
+	zassert_equal(cros_system_native_posix_get_chip_name_fake.arg0_val,
+		      sys_dev);
+
+	/* Revision */
+	cros_system_native_posix_get_chip_revision_fake.return_val = "c";
+	zassert_mem_equal(system_get_chip_revision(), "c", sizeof("c"));
+	zassert_equal(
+		cros_system_native_posix_get_chip_revision_fake.call_count, 1);
+	zassert_equal(cros_system_native_posix_get_chip_revision_fake.arg0_val,
+		      sys_dev);
+}
+
+static int _test_cros_system_native_posix_soc_reset(const struct device *dev)
+{
+	printf("called from soc reset");
+	longjmp(jmp_hibernate, 1);
+
+	return 0;
+}
+
+ZTEST(system, test_system_reset)
+{
+	/*
+	 * Despite using setjmp this test consistently covers the code under
+	 * test. Context: https://github.com/llvm/llvm-project/issues/50119
+	 */
+	const struct device *sys_dev = device_get_binding("CROS_SYSTEM");
+	int ret = setjmp(jmp_hibernate);
+	uint32_t arbitrary_flags_w_reset_wait_ext = 0x1234 |
+						    SYSTEM_RESET_WAIT_EXT;
+	uint32_t encoded_arbitrary_flags_w_reset_wait_ext;
+
+	system_encode_save_flags(arbitrary_flags_w_reset_wait_ext,
+				 &encoded_arbitrary_flags_w_reset_wait_ext);
+
+	zassert_not_null(sys_dev);
+
+	cros_system_native_posix_soc_reset_fake.custom_fake =
+		_test_cros_system_native_posix_soc_reset;
+
+	if (ret == 0) {
+		system_reset(arbitrary_flags_w_reset_wait_ext);
+	}
+
+	zassert_not_null(sys_dev);
+
+	zassert_equal(chip_read_reset_flags(),
+		      encoded_arbitrary_flags_w_reset_wait_ext);
+
+	zassert_equal(watchdog_reload_fake.call_count, 1000);
+	zassert_equal(cros_system_native_posix_soc_reset_fake.call_count, 1);
+	zassert_equal(cros_system_native_posix_soc_reset_fake.arg0_val,
+		      sys_dev);
+}
+
+ZTEST_USER(system, test_system_console_cmd__idlestats)
+{
+	const struct device *sys_dev = device_get_binding("CROS_SYSTEM");
+	const struct shell *shell_zephyr = get_ec_shell();
+	const char *outbuffer;
+	size_t buffer_size;
+
+	zassert_not_null(sys_dev);
+
+	shell_backend_dummy_clear_output(shell_zephyr);
+
+	k_sleep(K_SECONDS(1));
+	zassert_ok(shell_execute_cmd(shell_zephyr, "idlestats"), NULL);
+
+	/* Weakly verify contents */
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+	zassert_not_equal(buffer_size, 0);
+	zassert_not_null(strstr(outbuffer, "Time spent in deep-sleep:"));
+	zassert_not_null(strstr(outbuffer, "Total time on:"));
+
+	zassert_equal(cros_system_native_posix_deep_sleep_ticks_fake.call_count,
+		      1);
+}
+
+ZTEST(system, test_init_invalid_reset_cause)
+{
+	cros_system_native_posix_get_reset_cause_fake.return_val = -1;
+	zassert_equal(-1, system_preinitialize(NULL));
+}
+
+ZTEST(system, test_init_cause_vcc1_rst_pin)
+{
+	cros_system_native_posix_get_reset_cause_fake.return_val = VCC1_RST_PIN;
+	chip_save_reset_flags(0);
+	system_clear_reset_flags(0xffffffff);
+
+	zassert_ok(system_preinitialize(NULL));
+	zassert_equal(EC_RESET_FLAG_RESET_PIN, system_get_reset_flags());
+
+	chip_save_reset_flags(EC_RESET_FLAG_INITIAL_PWR);
+	zassert_ok(system_preinitialize(NULL));
+	zassert_equal(EC_RESET_FLAG_RESET_PIN | EC_RESET_FLAG_POWER_ON |
+			      EC_RESET_FLAG_POWER_ON,
+		      system_get_reset_flags());
+}
+
+ZTEST(system, test_init_cause_debug_rst)
+{
+	cros_system_native_posix_get_reset_cause_fake.return_val = DEBUG_RST;
+	chip_save_reset_flags(0);
+	system_clear_reset_flags(0xffffffff);
+
+	zassert_ok(system_preinitialize(NULL));
+	zassert_equal(EC_RESET_FLAG_SOFT, system_get_reset_flags());
+}
+
+ZTEST(system, test_init_cause_watchdog_rst)
+{
+	cros_system_native_posix_get_reset_cause_fake.return_val = WATCHDOG_RST;
+	chip_save_reset_flags(0);
+	system_clear_reset_flags(0xffffffff);
+
+	zassert_ok(system_preinitialize(NULL));
+	zassert_equal(EC_RESET_FLAG_WATCHDOG, system_get_reset_flags());
+}
diff --git a/zephyr/test/system_shim/test_default.cmake b/zephyr/test/system_shim/test_default.cmake
new file mode 100644
index 0000000000..0f2eb25177
--- /dev/null
+++ b/zephyr/test/system_shim/test_default.cmake
@@ -0,0 +1,18 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_sources(app
+  PRIVATE
+    src/suite.c
+    ${PLATFORM_EC}/zephyr/shim/src/system.c
+)
+
+target_include_directories(app PRIVATE include)
+
+dt_has_chosen(has_bbram PROPERTY "cros-ec,bbram")
+if(has_bbram)
+  target_sources(app PRIVATE src/test_system.c)
+else()
+  target_sources(app PRIVATE src/no_chosen.c)
+endif()
diff --git a/zephyr/test/system_shim/test_ish.cmake b/zephyr/test/system_shim/test_ish.cmake
new file mode 100644
index 0000000000..26bfe41c47
--- /dev/null
+++ b/zephyr/test/system_shim/test_ish.cmake
@@ -0,0 +1,9 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_sources(app
+  PRIVATE
+    src/test_ish_system.c
+    ${PLATFORM_EC}/zephyr/shim/src/ish_system.c
+)
diff --git a/zephyr/test/system_shim/testcase.yaml b/zephyr/test/system_shim/testcase.yaml
new file mode 100644
index 0000000000..ce58a09640
--- /dev/null
+++ b/zephyr/test/system_shim/testcase.yaml
@@ -0,0 +1,11 @@
+common:
+  platform_allow: native_posix
+  tags:
+    system
+tests:
+  system_shim.default:
+    extra_dtc_overlay_files:
+    - ./default.overlay
+  system_shim.ish:
+    extra_configs:
+    - CONFIG_SYSTEM_SHIM_TEST_ISH=y
diff --git a/zephyr/test/tasks/CMakeLists.txt b/zephyr/test/tasks/CMakeLists.txt
new file mode 100644
index 0000000000..52e6723652
--- /dev/null
+++ b/zephyr/test/tasks/CMakeLists.txt
@@ -0,0 +1,17 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(tasks)
+
+# Include the local test directory for shimmed_test_tasks.h
+zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}")
+
+target_sources_ifdef(CONFIG_HAS_TEST_TASKS app PRIVATE
+	main.c
+	"${CMAKE_CURRENT_SOURCE_DIR}/../../shim/src/tasks.c")
+
+target_sources_ifdef(CONFIG_SHIMMED_TASKS app PRIVATE
+	extra_tasks.c)
diff --git a/zephyr/test/tasks/boards/native_posix.overlay b/zephyr/test/tasks/boards/native_posix.overlay
new file mode 100644
index 0000000000..2e36118442
--- /dev/null
+++ b/zephyr/test/tasks/boards/native_posix.overlay
@@ -0,0 +1,8 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <board-overlays/native_posix.dts>
+
+/* No additional nodes to the native_posix overlay */
diff --git a/zephyr/test/tasks/extra_tasks.c b/zephyr/test/tasks/extra_tasks.c
new file mode 100644
index 0000000000..da89eac316
--- /dev/null
+++ b/zephyr/test/tasks/extra_tasks.c
@@ -0,0 +1,161 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_tasks.h"
+#include "host_command.h"
+#include "task.h"
+#include "zephyr_console_shim.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/kernel/thread.h>
+#include <zephyr/ztest.h>
+
+k_tid_t get_sysworkq_thread(void);
+k_tid_t get_idle_thread(void);
+
+/* Utilities for finding a Zephyr thread by name */
+static k_tid_t found_thread;
+static void find_thread_by_name_cb(const struct k_thread *thread,
+				   void *user_data)
+{
+	const char *name = (const char *)user_data;
+
+	if (strcmp(k_thread_name_get((k_tid_t)thread), name) == 0) {
+		found_thread = (k_tid_t)thread;
+	}
+}
+
+static k_tid_t find_thread_by_name(const char *name)
+{
+	found_thread = NULL;
+	k_thread_foreach_unlocked(find_thread_by_name_cb, (void *)name);
+	return found_thread;
+}
+
+/* Utilities for checking asserts */
+static bool expect_assert;
+static int num_asserts;
+void assert_post_action(const char *file, unsigned int line)
+{
+	num_asserts += 1;
+	if (!expect_assert) {
+		ztest_test_fail();
+	}
+}
+
+#define EXPECT_ASSERT(test)                    \
+	do {                                   \
+		expect_assert = true;          \
+		num_asserts = 0;               \
+		(test);                        \
+		expect_assert = false;         \
+		zassert_equal(num_asserts, 1); \
+	} while (0)
+
+ZTEST_USER(extra_tasks, test_hostcmd_thread_mapping)
+{
+	k_tid_t hostcmd_thread;
+	k_tid_t main_thread;
+
+#ifdef HAS_TASK_HOSTCMD
+#ifdef CONFIG_TASK_HOSTCMD_THREAD_MAIN
+	k_thread_name_set(get_main_thread(), "HOSTCMD");
+#endif /* CONFIG_TASK_HOSTCMD_THREAD_MAIN */
+
+	hostcmd_thread = find_thread_by_name("HOSTCMD");
+	zassert_not_null(hostcmd_thread);
+	zassert_equal(hostcmd_thread, get_hostcmd_thread());
+	zassert_equal(TASK_ID_HOSTCMD, thread_id_to_task_id(hostcmd_thread));
+	zassert_equal(task_id_to_thread_id(TASK_ID_HOSTCMD), hostcmd_thread);
+
+#ifdef CONFIG_TASK_HOSTCMD_THREAD_DEDICATED
+	main_thread = find_thread_by_name("main");
+	zassert_not_null(main_thread);
+	zassert_equal(main_thread, get_main_thread());
+	zassert_not_equal(main_thread, hostcmd_thread);
+	zassert_equal(TASK_ID_MAIN, thread_id_to_task_id(main_thread));
+	zassert_equal(task_id_to_thread_id(TASK_ID_MAIN), main_thread);
+#else
+	main_thread = get_main_thread();
+	zassert_not_null(main_thread);
+	zassert_equal(main_thread, hostcmd_thread);
+#endif /* CONFIG_TASK_HOSTCMD_THREAD_DEDICATED */
+
+#else /* !HAS_TASK_HOSTCMD */
+	hostcmd_thread = find_thread_by_name("HOSTCMD");
+	zassert_is_null(hostcmd_thread);
+	EXPECT_ASSERT(hostcmd_thread = get_hostcmd_thread());
+	zassert_is_null(hostcmd_thread);
+
+	main_thread = find_thread_by_name("main");
+	zassert_not_null(main_thread);
+	zassert_equal(main_thread, get_main_thread());
+#endif /* HAS_TASK_HOSTCMD */
+}
+
+ZTEST_USER(extra_tasks, test_sysworkq_thread_mapping)
+{
+	k_tid_t sysworkq_thread;
+
+	sysworkq_thread = find_thread_by_name("sysworkq");
+	zassert_not_null(sysworkq_thread);
+	zassert_equal(sysworkq_thread, get_sysworkq_thread());
+	zassert_equal(TASK_ID_SYSWORKQ, thread_id_to_task_id(sysworkq_thread));
+	zassert_equal(task_id_to_thread_id(TASK_ID_SYSWORKQ), sysworkq_thread);
+}
+
+ZTEST_USER(extra_tasks, test_idle_thread_mapping)
+{
+	k_tid_t idle_thread;
+
+	idle_thread = find_thread_by_name("idle");
+	zassert_not_null(idle_thread);
+	zassert_equal(idle_thread, get_idle_thread());
+	zassert_equal(TASK_ID_IDLE, thread_id_to_task_id(idle_thread));
+	zassert_equal(task_id_to_thread_id(TASK_ID_IDLE), idle_thread);
+}
+
+ZTEST_USER(extra_tasks, test_shell_thread_to_task_mapping)
+{
+	k_tid_t shell_thread;
+
+	shell_thread = find_thread_by_name("shell_uart");
+	zassert_not_null(shell_thread);
+	zassert_equal(shell_thread, get_shell_thread());
+	zassert_equal(TASK_ID_SHELL, thread_id_to_task_id(shell_thread));
+	zassert_equal(task_id_to_thread_id(TASK_ID_SHELL), shell_thread);
+}
+
+ZTEST_USER(extra_tasks, test_invalid_task_id)
+{
+	k_tid_t thread_id;
+
+	EXPECT_ASSERT(thread_id = task_id_to_thread_id(TASK_ID_INVALID));
+	zassert_is_null(thread_id);
+
+	EXPECT_ASSERT(thread_id = task_id_to_thread_id(-1));
+	zassert_is_null(thread_id);
+}
+
+ZTEST_USER(extra_tasks, test_invalid_thread_id)
+{
+	task_id_t task_id;
+
+	EXPECT_ASSERT(task_id = thread_id_to_task_id(NULL));
+	zassert_equal(task_id, TASK_ID_INVALID);
+
+	EXPECT_ASSERT(task_id = thread_id_to_task_id((k_tid_t)0x1234));
+	zassert_equal(task_id, TASK_ID_INVALID);
+}
+
+ZTEST_USER(extra_tasks, test_extra_task_enumeration)
+{
+	for (task_id_t task_id = 0; task_id < TASK_ID_COUNT + EXTRA_TASK_COUNT;
+	     task_id++) {
+		zassert_not_null(task_id_to_thread_id(task_id));
+	}
+}
+
+ZTEST_SUITE(extra_tasks, NULL, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/tasks/main.c b/zephyr/test/tasks/main.c
new file mode 100644
index 0000000000..dc3df59ca7
--- /dev/null
+++ b/zephyr/test/tasks/main.c
@@ -0,0 +1,313 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_tasks.h"
+#include "task.h"
+#include "timer.h"
+
+#include <stdbool.h>
+
+#include <zephyr/kernel.h>
+#include <zephyr/kernel/thread.h>
+#include <zephyr/ztest.h>
+
+/* Second for platform/ec task API (in microseconds). */
+#define TASK_SEC(s) (s * 1000 * 1000)
+
+K_SEM_DEFINE(task_done1, 0, 1);
+K_SEM_DEFINE(task_done2, 0, 1);
+K_SEM_DEFINE(test_ready1, 0, 1);
+K_SEM_DEFINE(test_ready2, 0, 1);
+
+static void (*task1)(void);
+static void (*task2)(void);
+
+static void run_test(void (*task1_run)(void), void (*task2_run)(void))
+{
+	task1 = task1_run;
+	task2 = task2_run;
+	k_sem_give(&test_ready1);
+	k_sem_give(&test_ready2);
+	k_sem_take(&task_done1, K_FOREVER);
+	k_sem_take(&task_done2, K_FOREVER);
+}
+
+void task1_entry(void *p)
+{
+	while (1) {
+		k_sem_take(&test_ready1, K_FOREVER);
+		task1();
+		k_sem_give(&task_done1);
+	}
+}
+
+void task2_entry(void *p)
+{
+	while (1) {
+		k_sem_take(&test_ready2, K_FOREVER);
+		task2();
+		k_sem_give(&task_done2);
+	}
+}
+
+/*
+ * Unlike Tasks 1 & 2, it is allowed to run Task 3 more than once per
+ * call to run_test().  It will call task3_entry_func if set, and wait
+ * for the next event.  This is useful to test things like timers,
+ * which you are expecting the event to fire at some point in the
+ * future, and you want to test that it happens.
+ */
+static void (*task3_entry_func)(uint32_t event_mask);
+
+void task3_entry(void *p)
+{
+	uint32_t events = 0;
+
+	for (;;) {
+		if (task3_entry_func)
+			task3_entry_func(events);
+		events = task_wait_event(-1);
+	}
+}
+
+static void set_event_before_task_start1(void)
+{
+	const uint32_t events = task_wait_event(TASK_SEC(2));
+
+	zassert_equal(events, 0xAAAA, "Should have 0xAAAA events");
+}
+
+static void set_event_before_task_start2(void)
+{
+	/* Do nothing */
+}
+
+static void test_set_event_before_task_start(void)
+{
+	/* Send event before tasks start */
+	task_set_event(TASK_ID_TASK_1, 0xAAAA);
+
+	start_ec_tasks();
+
+	run_test(set_event_before_task_start1, set_event_before_task_start2);
+}
+
+static void task_get_current1(void)
+{
+	zassert_equal(task_get_current(), TASK_ID_TASK_1, "ID matches");
+}
+
+static void task_get_current2(void)
+{
+	zassert_equal(task_get_current(), TASK_ID_TASK_2, "ID matches");
+}
+
+static void test_task_get_current(void)
+{
+	run_test(&task_get_current1, &task_get_current2);
+}
+
+static void timeout1(void)
+{
+	const uint32_t start_ms = k_uptime_get();
+	const uint32_t events = task_wait_event(TASK_SEC(2));
+	const uint32_t end_ms = k_uptime_get();
+
+	zassert_equal(events, TASK_EVENT_TIMER, "Should have timeout event");
+	zassert_within(end_ms - start_ms, 2000, 100, "Timeout for 2 seconds");
+}
+
+static void timeout2(void)
+{
+	/* Do nothing */
+}
+
+static void test_timeout(void)
+{
+	run_test(&timeout1, &timeout2);
+}
+
+/*
+ * Timer test:
+ *   1. Task 1 arms a timer for Task 3 in expiring 2 seconds.
+ *   2. Task 2 does nothing.
+ *   3. Task 3 validates that the it receives a TASK_EVENT_TIMER event
+ *      2 seconds after Task 1 armed the timer (within 100ms
+ *      tolerance).
+ */
+static timestamp_t timer_armed_at;
+K_SEM_DEFINE(check_timer_finished, 0, 1);
+
+static void check_timer(uint32_t event_mask)
+{
+	timestamp_t now = get_time();
+
+	zassert_equal(event_mask & TASK_EVENT_TIMER, TASK_EVENT_TIMER,
+		      "Timer event mask should be set");
+	zassert_within(now.val - timer_armed_at.val, TASK_SEC(2),
+		       TASK_SEC(1) / 10,
+		       "Timer should expire at 2 seconds from arm time");
+	k_sem_give(&check_timer_finished);
+}
+
+static void timer_task_1(void)
+{
+	timestamp_t timer_timeout;
+
+	timer_armed_at = get_time();
+
+	timer_timeout.val = timer_armed_at.val + TASK_SEC(2);
+
+	task3_entry_func = check_timer;
+	zassert_equal(timer_arm(timer_timeout, TASK_ID_TASK_3), EC_SUCCESS,
+		      "Setting timer should succeed");
+}
+
+static void timer_task_2(void)
+{
+	/* Do nothing */
+}
+
+static void test_timer(void)
+{
+	run_test(timer_task_1, timer_task_2);
+	zassert_equal(k_sem_take(&check_timer_finished, K_SECONDS(4 * 1000)), 0,
+		      "Task 3 did not finish within timeout");
+	zassert_equal(task3_entry_func, check_timer,
+		      "check_timer should have been enabled");
+	task3_entry_func = NULL;
+}
+
+static void event_delivered1(void)
+{
+	const uint32_t start_ms = k_uptime_get();
+	const uint32_t events = task_wait_event(-1);
+	const uint32_t end_ms = k_uptime_get();
+
+	zassert_equal(events, 0x1234, "Verify event bits");
+	zassert_within(end_ms - start_ms, 5000, 100, "Waited for 5 seconds");
+}
+
+static void event_delivered2(void)
+{
+	k_sleep(K_SECONDS(5));
+
+	task_set_event(TASK_ID_TASK_1, 0x1234);
+}
+
+static void test_event_delivered(void)
+{
+	run_test(&event_delivered1, &event_delivered2);
+}
+
+static void event_mask_not_delivered1(void)
+{
+	task_set_event(TASK_ID_TASK_2, 0x007F);
+}
+
+static void event_mask_not_delivered2(void)
+{
+	const uint32_t start_ms = k_uptime_get();
+	const uint32_t events = task_wait_event_mask(0x0080, TASK_SEC(7));
+	const uint32_t end_ms = k_uptime_get();
+
+	zassert_equal(events, TASK_EVENT_TIMER, "Should have timeout event");
+	zassert_within(end_ms - start_ms, 7000, 100, "Timeout for 7 seconds");
+
+	const uint32_t leftover_events = task_wait_event(0);
+
+	zassert_equal(leftover_events, 0x007F, "All events should be waiting");
+}
+
+static void test_event_mask_not_delivered(void)
+{
+	run_test(&event_mask_not_delivered1, &event_mask_not_delivered2);
+}
+
+static void event_mask_extra1(void)
+{
+	k_sleep(K_SECONDS(1));
+
+	task_set_event(TASK_ID_TASK_2, 0x00FF);
+}
+
+static void event_mask_extra2(void)
+{
+	const uint32_t start_ms = k_uptime_get();
+	const uint32_t events = task_wait_event_mask(0x0001, TASK_SEC(10));
+	const uint32_t end_ms = k_uptime_get();
+
+	zassert_equal(events, 0x0001, "Verify only waited for event");
+	zassert_within(end_ms - start_ms, 1000, 100, "Timeout for 1 second");
+
+	const uint32_t leftover_events = task_wait_event(0);
+
+	zassert_equal(leftover_events, 0x00FE, "All events should be waiting");
+}
+
+static void test_event_mask_extra(void)
+{
+	run_test(&event_mask_extra1, &event_mask_extra2);
+}
+
+static void empty_set_mask1(void)
+{
+	k_sleep(K_SECONDS(1));
+	/*
+	 * It is generally invalid to set a 0 event, but this simulates a race
+	 * condition and exercises fallback code in task_wait_event
+	 */
+	task_set_event(TASK_ID_TASK_2, 0);
+	k_sleep(K_SECONDS(1));
+	task_set_event(TASK_ID_TASK_2, 0x1234);
+}
+
+static void empty_set_mask2(void)
+{
+	const uint32_t start_ms = k_uptime_get();
+	const uint32_t events = task_wait_event_mask(0x1234, TASK_SEC(10));
+	const uint32_t end_ms = k_uptime_get();
+
+	zassert_equal(events, 0x1234, "Verify only waited for event");
+	zassert_within(end_ms - start_ms, 2000, 100, "Timeout for 2 seconds");
+}
+
+static void check_task_1_mapping(void)
+{
+	zassert_equal(TASK_ID_TASK_1, thread_id_to_task_id(k_current_get()));
+	zassert_equal(k_current_get(), task_id_to_thread_id(TASK_ID_TASK_1));
+}
+
+static void check_task_2_mapping(void)
+{
+	zassert_equal(TASK_ID_TASK_2, thread_id_to_task_id(k_current_get()));
+	zassert_equal(k_current_get(), task_id_to_thread_id(TASK_ID_TASK_2));
+}
+
+static void test_thread_to_task_mapping(void)
+{
+	run_test(&check_task_1_mapping, &check_task_2_mapping);
+}
+
+static void test_empty_set_mask(void)
+{
+	run_test(&empty_set_mask1, &empty_set_mask2);
+}
+
+void test_main(void)
+{
+	/* Note that test_set_event_before_task_start calls start_ec_tasks */
+	ztest_test_suite(test_task_shim,
+			 ztest_unit_test(test_set_event_before_task_start),
+			 ztest_unit_test(test_task_get_current),
+			 ztest_unit_test(test_timeout),
+			 ztest_unit_test(test_timer),
+			 ztest_unit_test(test_event_delivered),
+			 ztest_unit_test(test_event_mask_not_delivered),
+			 ztest_unit_test(test_event_mask_extra),
+			 ztest_unit_test(test_empty_set_mask),
+			 ztest_unit_test(test_thread_to_task_mapping));
+	ztest_run_test_suite(test_task_shim);
+}
diff --git a/zephyr/test/tasks/prj.conf b/zephyr/test/tasks/prj.conf
new file mode 100644
index 0000000000..67deb38144
--- /dev/null
+++ b/zephyr/test/tasks/prj.conf
@@ -0,0 +1,11 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_ZTEST=y
+CONFIG_PLATFORM_EC=y
+CONFIG_CROS_EC=y
+CONFIG_TASKS_SET_TEST_RUNNER_TID_RULE=y
+CONFIG_PLATFORM_EC_VBOOT_HASH=n
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
+CONFIG_PLATFORM_EC_SWITCH=n
diff --git a/zephyr/test/tasks/shimmed_test_tasks.h b/zephyr/test/tasks/shimmed_test_tasks.h
new file mode 100644
index 0000000000..ebd1215446
--- /dev/null
+++ b/zephyr/test/tasks/shimmed_test_tasks.h
@@ -0,0 +1,22 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_SHIMMED_TEST_TASKS_H
+#define __CROS_EC_SHIMMED_TEST_TASKS_H
+
+/*
+ * Manually define these HAS_TASK_* defines. There is a build time assert
+ * to at least verify we have the minimum set defined correctly. */
+#define HAS_TASK_TASK_1 1
+#define HAS_TASK_TASK_2 1
+#define HAS_TASK_TASK_3 1
+
+/* Highest priority on bottom same as in platform/ec */
+#define CROS_EC_TASK_LIST                            \
+	CROS_EC_TASK(TASK_1, task1_entry, 0, 512, 2) \
+	CROS_EC_TASK(TASK_2, task2_entry, 0, 512, 1) \
+	CROS_EC_TASK(TASK_3, task3_entry, 0, 512, 0)
+
+#endif /* __CROS_EC_SHIMMED_TEST_TASKS_H */
diff --git a/zephyr/test/tasks/testcase.yaml b/zephyr/test/tasks/testcase.yaml
new file mode 100644
index 0000000000..c079930c6c
--- /dev/null
+++ b/zephyr/test/tasks/testcase.yaml
@@ -0,0 +1,30 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+common:
+  platform_allow: native_posix
+tests:
+  tasks.default:
+    extra_configs:
+      - CONFIG_HAS_TEST_TASKS=y
+  tasks.extra_tasks:
+    extra_configs:
+      - CONFIG_ZTEST_NEW_API=y
+      - CONFIG_SHIMMED_TASKS=y
+      - CONFIG_ASSERT_TEST=y
+      - CONFIG_PLATFORM_EC_HOSTCMD=n
+  tasks.extra_tasks.hostcmd_main:
+    extra_configs:
+      - CONFIG_ZTEST_NEW_API=y
+      - CONFIG_SHIMMED_TASKS=y
+      - CONFIG_ASSERT_TEST=y
+      - CONFIG_PLATFORM_EC_HOSTCMD=y
+      - CONFIG_TASK_HOSTCMD_THREAD_MAIN=y
+  tasks.extra_tasks.hostcmd_dedicated:
+    extra_configs:
+      - CONFIG_ZTEST_NEW_API=y
+      - CONFIG_SHIMMED_TASKS=y
+      - CONFIG_ASSERT_TEST=y
+      - CONFIG_PLATFORM_EC_HOSTCMD=y
+      - CONFIG_TASK_HOSTCMD_THREAD_DEDICATED=y
diff --git a/zephyr/test/test_utils/CMakeLists.txt b/zephyr/test/test_utils/CMakeLists.txt
new file mode 100644
index 0000000000..be5ec575a9
--- /dev/null
+++ b/zephyr/test/test_utils/CMakeLists.txt
@@ -0,0 +1,17 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+zephyr_interface_library_named(test_utils)
+
+zephyr_library_sources(fff.c)
+
+if (NOT CONFIG_SHIMMED_TASKS AND NOT CONFIG_HAS_TEST_TASKS)
+  zephyr_include_directories("${PLATFORM_EC}/include"
+                             "${PLATFORM_EC}/fuzz"
+                             "${PLATFORM_EC}/test"
+                             "${PLATFORM_EC}/zephyr/shim/include")
+  zephyr_library_sources(tasks_fakes.c)
+endif()
+
+zephyr_library_link_libraries(test_utils)
diff --git a/zephyr/test/test_utils/fff.c b/zephyr/test/test_utils/fff.c
new file mode 100644
index 0000000000..3b10dc3706
--- /dev/null
+++ b/zephyr/test/test_utils/fff.c
@@ -0,0 +1,8 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/fff.h>
+
+DEFINE_FFF_GLOBALS;
diff --git a/zephyr/test/test_utils/tasks_fakes.c b/zephyr/test/test_utils/tasks_fakes.c
new file mode 100644
index 0000000000..d688c6cc24
--- /dev/null
+++ b/zephyr/test/test_utils/tasks_fakes.c
@@ -0,0 +1,32 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "task_id.h"
+
+#include <zephyr/fff.h>
+#include <zephyr/sys/atomic.h>
+
+/*
+ * The fakes below are needed to satisfy the final link, but are never
+ * actually called at runtime. Exclude from the coverage report to avoid
+ * false positives on the low-coverage check.
+ */
+/* LCOV_EXCL_START */
+FAKE_VALUE_FUNC(task_id_t, task_get_current);
+FAKE_VALUE_FUNC(atomic_t *, task_get_event_bitmap, task_id_t);
+FAKE_VOID_FUNC(task_set_event, task_id_t, uint32_t);
+FAKE_VALUE_FUNC(int, task_start_called);
+FAKE_VALUE_FUNC(uint32_t, task_wait_event, int);
+FAKE_VALUE_FUNC(uint32_t, task_wait_event_mask, uint32_t, int);
+
+/*
+ * If cros-ec tasks aren't enabled, always indicate we are in a deferred
+ * context.
+ */
+bool in_deferred_context(void)
+{
+	return true;
+}
+/* LCOV_EXCL_STOP */
diff --git a/zephyr/test/throttle_ap/CMakeLists.txt b/zephyr/test/throttle_ap/CMakeLists.txt
new file mode 100644
index 0000000000..da4ebdba20
--- /dev/null
+++ b/zephyr/test/throttle_ap/CMakeLists.txt
@@ -0,0 +1,15 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(throttle_ap)
+
+add_subdirectory(${PLATFORM_EC}/zephyr/test/test_utils test_utils)
+
+zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}/include")
+
+target_sources_ifdef(CONFIG_TEST_INTERRUPT app PRIVATE src/interrupt.c)
+target_sources_ifdef(CONFIG_TEST_THROTTLE_AP app PRIVATE src/throttle_ap.c)
+target_sources(app PRIVATE src/common.c)
diff --git a/zephyr/test/throttle_ap/Kconfig b/zephyr/test/throttle_ap/Kconfig
new file mode 100644
index 0000000000..06071cded5
--- /dev/null
+++ b/zephyr/test/throttle_ap/Kconfig
@@ -0,0 +1,17 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+source "Kconfig.zephyr"
+
+config AP_POWER_CONTROL
+	bool "Allows the test to mock various chipset functions"
+	default y
+
+config TEST_INTERRUPT
+	bool "Enable testing of prochot interrupts"
+	default n
+
+config TEST_THROTTLE_AP
+	bool "Enable testing of AP throttling functions"
+	default n
diff --git a/zephyr/test/throttle_ap/boards/native_posix.overlay b/zephyr/test/throttle_ap/boards/native_posix.overlay
new file mode 100644
index 0000000000..941c469695
--- /dev/null
+++ b/zephyr/test/throttle_ap/boards/native_posix.overlay
@@ -0,0 +1,39 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <board-overlays/native_posix.dts>
+#include <dt-bindings/gpio_defines.h>
+
+/ {
+	aliases {
+		gpio-prochot-l = &gpio_prochot_l;
+	};
+	/*
+	 * Keep these GPIOs in pin order.
+	 * If you need to add one, make sure you increase
+	 * ngpios in the gpio0 node further down.
+	 */
+	named-gpios {
+		compatible = "named-gpios";
+
+		gpio_prochot_l: prochot_l {
+			gpios = <&gpio0 0 GPIO_INPUT>;
+			enum-name = "GPIO_CPU_PROCHOT";
+		};
+	};
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_prochot: prochot {
+			irq-pin = <&gpio_prochot_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "throttle_ap_prochot_input_interrupt";
+		};
+	};
+};
+
+&gpio0 {
+	ngpios = <2>;
+};
diff --git a/zephyr/test/throttle_ap/prj.conf b/zephyr/test/throttle_ap/prj.conf
new file mode 100644
index 0000000000..8a835017e8
--- /dev/null
+++ b/zephyr/test/throttle_ap/prj.conf
@@ -0,0 +1,43 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_ZTEST=y
+CONFIG_ZTEST_ASSERT_VERBOSE=1
+CONFIG_ZTEST_MOCKING=y
+CONFIG_ZTEST_NEW_API=y
+CONFIG_ZTEST_PARAMETER_COUNT=24
+CONFIG_TEST=y
+CONFIG_ASSERT=y
+
+# Print logs from Zephyr LOG_MODULE to stdout
+CONFIG_NATIVE_UART_0_ON_STDINOUT=y
+
+# Simulate 10 ticks per ms
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=10000
+CONFIG_TASKS_SET_TEST_RUNNER_TID_RULE=y
+
+# Enable exception stack traces for better errors
+CONFIG_EXCEPTION_STACK_TRACE=y
+
+# Enable debugging features
+CONFIG_DEBUG=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_OPTIMIZATIONS=y
+CONFIG_PLATFORM_EC_CONSOLE_DEBUG=y
+CONFIG_SHELL_BACKEND_DUMMY=y
+CONFIG_SHELL_BACKEND_SERIAL=n
+# We aren't using the serial console, but there is still a lot of code that
+# assumes that a serial port exists.
+CONFIG_SERIAL=y
+
+CONFIG_PLATFORM_EC=y
+CONFIG_CROS_EC=y
+CONFIG_SHIMMED_TASKS=y
+CONFIG_EMUL=y
+CONFIG_GPIO=y
+CONFIG_HEAP_MEM_POOL_SIZE=1024
+
+CONFIG_PLATFORM_EC_THROTTLE_AP=y
+CONFIG_PLATFORM_EC_THROTTLE_AP_SINGLE_PIN=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_APTHROTTLE=n
diff --git a/zephyr/test/throttle_ap/src/common.c b/zephyr/test/throttle_ap/src/common.c
new file mode 100644
index 0000000000..7bf2add972
--- /dev/null
+++ b/zephyr/test/throttle_ap/src/common.c
@@ -0,0 +1,29 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include <zephyr/ztest.h>
+
+#include <chipset.h>
+#include <console.h>
+#include <throttle_ap.h>
+
+ZTEST_SUITE(throttle_ap, NULL, NULL, NULL, NULL, NULL);
+
+/*
+ * The prochot interrupt handler will return early if the chipset is
+ * off or suspended.
+ */
+int chipset_in_state(int state_mask)
+{
+	return state_mask & CHIPSET_STATE_ON;
+}
+
+void chipset_force_shutdown(enum chipset_shutdown_reason reason)
+{
+}
+
+int extpower_is_present(void)
+{
+	return 1;
+}
diff --git a/zephyr/test/throttle_ap/src/interrupt.c b/zephyr/test/throttle_ap/src/interrupt.c
new file mode 100644
index 0000000000..92447bff9c
--- /dev/null
+++ b/zephyr/test/throttle_ap/src/interrupt.c
@@ -0,0 +1,58 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include <stdint.h>
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+#include <gpio.h>
+#include <throttle_ap.h>
+#include <timer.h>
+
+#define PROCHOT_ASSERTED \
+	!IS_ENABLED(PLATFORM_EC_POWERSEQ_CPU_PROCHOT_ACTIVE_LOW)
+
+/* Waits for the debouncing logic to finish. */
+static void debounce_wait(void)
+{
+	k_usleep(PROCHOT_IN_DEBOUNCE_US);
+	k_msleep(1);
+}
+
+static bool was_asserted;
+static void callback(bool asserted, void *data)
+{
+	was_asserted = asserted;
+}
+
+const struct prochot_cfg cfg = {
+	.gpio_prochot_in = GPIO_CPU_PROCHOT,
+	.callback = &callback,
+
+};
+
+ZTEST_USER(throttle_ap, test_interrupts)
+{
+	const struct device *dev =
+		DEVICE_DT_GET(DT_GPIO_CTLR(DT_ALIAS(gpio_prochot_l), gpios));
+	const gpio_port_pins_t pin =
+		DT_GPIO_PIN(DT_ALIAS(gpio_prochot_l), gpios);
+
+	/* Start the test with the interrupt deasserted. */
+	zassert_ok(gpio_emul_input_set(dev, pin, !PROCHOT_ASSERTED));
+
+	throttle_ap_config_prochot(&cfg);
+	gpio_enable_interrupt(cfg.gpio_prochot_in);
+
+	zassert_ok(gpio_emul_input_set(dev, pin, PROCHOT_ASSERTED));
+	debounce_wait();
+	zassert_true(was_asserted);
+
+	zassert_ok(gpio_emul_input_set(dev, pin, !PROCHOT_ASSERTED));
+	debounce_wait();
+	zassert_false(was_asserted);
+}
diff --git a/zephyr/test/throttle_ap/src/throttle_ap.c b/zephyr/test/throttle_ap/src/throttle_ap.c
new file mode 100644
index 0000000000..0b9fe9ae4c
--- /dev/null
+++ b/zephyr/test/throttle_ap/src/throttle_ap.c
@@ -0,0 +1,27 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "common.h"
+
+#include <zephyr/ztest.h>
+
+#include <chipset.h>
+#include <console.h>
+#include <gpio.h>
+#include <throttle_ap.h>
+
+static bool is_throttled;
+void chipset_throttle_cpu(int throttle)
+{
+	is_throttled = throttle;
+}
+
+ZTEST_USER(throttle_ap, test_throttle_ap)
+{
+	throttle_ap(THROTTLE_ON, THROTTLE_HARD, THROTTLE_SRC_AC);
+	zassert_true(is_throttled);
+
+	throttle_ap(THROTTLE_OFF, THROTTLE_HARD, THROTTLE_SRC_AC);
+	zassert_false(is_throttled);
+}
diff --git a/zephyr/test/throttle_ap/testcase.yaml b/zephyr/test/throttle_ap/testcase.yaml
new file mode 100644
index 0000000000..ebddc652f0
--- /dev/null
+++ b/zephyr/test/throttle_ap/testcase.yaml
@@ -0,0 +1,14 @@
+common:
+  platform_allow: native_posix
+tests:
+  throttle_ap.interrupt.active_low:
+    extra_configs:
+      - CONFIG_PLATFORM_EC_POWERSEQ_CPU_PROCHOT_ACTIVE_LOW=n
+      - CONFIG_TEST_INTERRUPT=y
+  throttle_ap.interrupt.active_high:
+    extra_configs:
+      - CONFIG_PLATFORM_EC_POWERSEQ_CPU_PROCHOT_ACTIVE_LOW=y
+      - CONFIG_TEST_INTERRUPT=y
+  thottle_ap.throttle_ap:
+    extra_configs:
+      - CONFIG_TEST_THROTTLE_AP=y
diff --git a/zephyr/test/uart_printf/CMakeLists.txt b/zephyr/test/uart_printf/CMakeLists.txt
new file mode 100644
index 0000000000..8844bfb7be
--- /dev/null
+++ b/zephyr/test/uart_printf/CMakeLists.txt
@@ -0,0 +1,20 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr COMPONENTS unittest REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(uart_printf)
+
+target_sources(testbinary
+  PRIVATE
+    ../../../common/uart_printf.c
+    src/fakes.cc
+    src/main.cc
+)
+
+target_include_directories(testbinary
+  PRIVATE
+    include
+)
diff --git a/zephyr/test/uart_printf/include/common.h b/zephyr/test/uart_printf/include/common.h
new file mode 100644
index 0000000000..79af9594b3
--- /dev/null
+++ b/zephyr/test/uart_printf/include/common.h
@@ -0,0 +1,12 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef ZEPHYR_TEST_UART_PRINTF_INCLUDE_COMMON_H_
+#define ZEPHYR_TEST_UART_PRINTF_INCLUDE_COMMON_H_
+
+#define EC_SUCCESS 0
+#define EC_ERROR_OVERFLOW -1
+
+#endif /* ZEPHYR_TEST_UART_PRINTF_INCLUDE_COMMON_H_ */
diff --git a/zephyr/test/uart_printf/include/printf.h b/zephyr/test/uart_printf/include/printf.h
new file mode 100644
index 0000000000..b6fcf6337d
--- /dev/null
+++ b/zephyr/test/uart_printf/include/printf.h
@@ -0,0 +1,23 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef ZEPHYR_TEST_UART_PRINTF_INCLUDE_PRINTF_H_
+#define ZEPHYR_TEST_UART_PRINTF_INCLUDE_PRINTF_H_
+
+#include <zephyr/fff.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef int (*vfnprintf_addchar_t)(void *, int);
+DECLARE_FAKE_VALUE_FUNC(int, vfnprintf, vfnprintf_addchar_t, void *,
+			const char *, va_list);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZEPHYR_TEST_UART_PRINTF_INCLUDE_PRINTF_H_ */
diff --git a/zephyr/test/uart_printf/include/uart.h b/zephyr/test/uart_printf/include/uart.h
new file mode 100644
index 0000000000..51fd42a17e
--- /dev/null
+++ b/zephyr/test/uart_printf/include/uart.h
@@ -0,0 +1,28 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef ZEPHYR_TEST_UART_PRINTF_INCLUDE_UART_H_
+#define ZEPHYR_TEST_UART_PRINTF_INCLUDE_UART_H_
+
+#include <zephyr/fff.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int uart_putc(int c);
+int uart_puts(const char *outstr);
+int uart_put(const char *out, int len);
+int uart_put_raw(const char *out, int len);
+int uart_printf(const char *format, ...);
+
+DECLARE_FAKE_VALUE_FUNC(int, uart_tx_char_raw, void *, int);
+DECLARE_FAKE_VOID_FUNC(uart_tx_start);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZEPHYR_TEST_UART_PRINTF_INCLUDE_UART_H_ */
diff --git a/zephyr/test/uart_printf/prj.conf b/zephyr/test/uart_printf/prj.conf
new file mode 100644
index 0000000000..744afcce87
--- /dev/null
+++ b/zephyr/test/uart_printf/prj.conf
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_ZTEST=y
+CONFIG_ZTEST_NEW_API=y
+CONFIG_CPLUSPLUS=y
+CONFIG_STD_CPP20=y
+CONFIG_LIB_CPLUSPLUS=y
diff --git a/zephyr/test/uart_printf/src/fakes.cc b/zephyr/test/uart_printf/src/fakes.cc
new file mode 100644
index 0000000000..6cfdacaaa0
--- /dev/null
+++ b/zephyr/test/uart_printf/src/fakes.cc
@@ -0,0 +1,36 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "printf.h"
+#include "uart.h"
+
+#include <zephyr/fff.h>
+#include <zephyr/ztest.h>
+
+DEFINE_FFF_GLOBALS;
+
+/* printf.h */
+DEFINE_FAKE_VALUE_FUNC(int, vfnprintf, vfnprintf_addchar_t, void *,
+		       const char *, va_list);
+
+/* uart.h */
+DEFINE_FAKE_VALUE_FUNC(int, uart_tx_char_raw, void *, int);
+DEFINE_FAKE_VOID_FUNC(uart_tx_start);
+
+static void fake_reset_rule_before(const struct ztest_unit_test *test,
+				   void *data)
+{
+	ARG_UNUSED(test);
+	ARG_UNUSED(data);
+
+	/* printf.h */
+	RESET_FAKE(vfnprintf);
+
+	/* uart.h */
+	RESET_FAKE(uart_tx_char_raw);
+	RESET_FAKE(uart_tx_start);
+}
+
+ZTEST_RULE(fake_reset, fake_reset_rule_before, nullptr);
diff --git a/zephyr/test/uart_printf/src/main.cc b/zephyr/test/uart_printf/src/main.cc
new file mode 100644
index 0000000000..1633e6edc5
--- /dev/null
+++ b/zephyr/test/uart_printf/src/main.cc
@@ -0,0 +1,101 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "printf.h"
+#include "uart.h"
+
+#include <zephyr/ztest.h>
+
+#include <cstring>
+#include <string>
+
+ZTEST_SUITE(uart_printf, nullptr, nullptr, nullptr, nullptr, nullptr);
+
+ZTEST(uart_printf, test_uart_putc)
+{
+	int return_vals[] = { 0, -1 };
+
+	SET_RETURN_SEQ(uart_tx_char_raw, return_vals, 2);
+
+	zassert_ok(uart_putc(5));
+	zassert_equal(EC_ERROR_OVERFLOW, uart_putc(5));
+}
+
+ZTEST(uart_printf, test_uart_put_success)
+{
+	const std::string test_string = "test string";
+	std::string output_string;
+
+	/* Print the whole string */
+	zassert_equal(test_string.size(),
+		      static_cast<size_t>(uart_put(test_string.c_str(),
+						   test_string.size())));
+	zassert_equal(test_string.size(), uart_tx_char_raw_fake.call_count);
+
+	/* Copy the history so it's easier to assert */
+	for (size_t i = 0; i < test_string.size(); ++i) {
+		output_string += uart_tx_char_raw_fake.arg1_history[i];
+	}
+
+	/* Verify that the string was passed to uart_tx_char_raw() */
+	zassert_equal(test_string, output_string);
+}
+
+ZTEST(uart_printf, test_uart_put_fail_tx)
+{
+	const char test_string[] = "\n";
+
+	uart_tx_char_raw_fake.return_val = -1;
+
+	/* Try printing the newline */
+	zassert_equal(0, uart_put(test_string, 1));
+	zassert_equal(1, uart_tx_char_raw_fake.call_count);
+	zassert_equal('\r', uart_tx_char_raw_fake.arg1_val);
+}
+
+ZTEST(uart_printf, test_uart_puts_fail_tx)
+{
+	const char test_string[] = "\n\0";
+
+	uart_tx_char_raw_fake.return_val = -1;
+
+	/* Try printing the newline */
+	zassert_equal(EC_ERROR_OVERFLOW, uart_puts(test_string));
+	zassert_equal(1, uart_tx_char_raw_fake.call_count);
+	zassert_equal('\r', uart_tx_char_raw_fake.arg1_val);
+}
+
+ZTEST(uart_printf, test_uart_put_raw_fail_tx)
+{
+	const char test_string[] = "\n";
+
+	uart_tx_char_raw_fake.return_val = -1;
+
+	/* Try printing the newline */
+	zassert_equal(0, uart_put_raw(test_string, 1));
+	zassert_equal(1, uart_tx_char_raw_fake.call_count);
+	zassert_equal('\n', uart_tx_char_raw_fake.arg1_val);
+}
+
+static int vfnprintf_custom_fake_expect_int_arg;
+static int vfnprintf_custom_fake(vfnprintf_addchar_t, void *, const char *,
+				 va_list alist)
+{
+	zassert_equal(vfnprintf_custom_fake_expect_int_arg, va_arg(alist, int));
+	return 0;
+}
+ZTEST(uart_printf, test_uart_printf)
+{
+	const char test_format[] = "d=%d";
+
+	vfnprintf_custom_fake_expect_int_arg = 5;
+	vfnprintf_fake.custom_fake = vfnprintf_custom_fake;
+
+	zassert_ok(
+		uart_printf(test_format, vfnprintf_custom_fake_expect_int_arg));
+	zassert_equal(1, vfnprintf_fake.call_count);
+	zassert_equal(test_format, vfnprintf_fake.arg2_val);
+}
diff --git a/zephyr/test/uart_printf/testcase.yaml b/zephyr/test/uart_printf/testcase.yaml
new file mode 100644
index 0000000000..0315abab6f
--- /dev/null
+++ b/zephyr/test/uart_printf/testcase.yaml
@@ -0,0 +1,8 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+tests:
+  uart.printf:
+    tags: uart
+    type: unit
diff --git a/zephyr/test/unblocked_terms.txt b/zephyr/test/unblocked_terms.txt
new file mode 100644
index 0000000000..cf2ed1052f
--- /dev/null
+++ b/zephyr/test/unblocked_terms.txt
@@ -0,0 +1,2 @@
+SHELL_BACKEND_DUMMY
+shell_dummy
diff --git a/zephyr/test/vboot_efs2/CMakeLists.txt b/zephyr/test/vboot_efs2/CMakeLists.txt
new file mode 100644
index 0000000000..2d38c7baf7
--- /dev/null
+++ b/zephyr/test/vboot_efs2/CMakeLists.txt
@@ -0,0 +1,12 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(vboot_efs2)
+
+add_subdirectory(${PLATFORM_EC}/zephyr/test/test_utils test_utils)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
diff --git a/zephyr/test/vboot_efs2/boards/native_posix.overlay b/zephyr/test/vboot_efs2/boards/native_posix.overlay
new file mode 100644
index 0000000000..157ca70510
--- /dev/null
+++ b/zephyr/test/vboot_efs2/boards/native_posix.overlay
@@ -0,0 +1,146 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <board-overlays/native_posix.dts>
+#include <cros/binman.dtsi>
+
+/ {
+	chosen {
+		cros-ec,flash = &flash1;
+		cros-ec,flash-controller = &cros_flash;
+		zephyr,shell-uart = &test_uart;
+	};
+	aliases {
+		gpio-wp = &gpio_wp_l;
+	};
+	named-gpios {
+		compatible = "named-gpios";
+		ec_gsc_packet_mode {
+			gpios = <&gpio0 2 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_PACKET_MODE_EN";
+		};
+		gpio_wp_l: wp_l {
+			gpios = <&gpio0 3 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		usb_c0_tcpc_int_odl: usb_c0_tcpc_int_odl {
+			gpios = <&gpio0 4 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		ec_batt_pres_odl {
+			gpios = <&gpio0 5 GPIO_INPUT>;
+			enum-name = "GPIO_BATT_PRES_ODL";
+		};
+	};
+	cros_flash: cros-flash {
+		compatible = "cros-ec,flash-emul";
+	};
+	flash1: flash@64000000 {
+		reg = <0x64000000 DT_SIZE_K(512)>;
+	};
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		named_i2c0: i2c0 {
+			i2c-port = <&i2c0>;
+			enum-names = "I2C_PORT_BATTERY",
+				"I2C_PORT_CHARGER";
+		};
+		named_i2c2: i2c2 {
+			i2c-port = <&i2c2>;
+			dynamic-speed;
+			enum-names = "I2C_PORT_USB_C0";
+		};
+	};
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+			bc12 = <&pi3usb9201_emul>;
+			chg = <&isl923x_emul>;
+			tcpc = <&tcpci_emul>;
+			usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&tcpci_mux_c0>;
+			};
+		};
+		port0-muxes {
+			tcpci_mux_c0: tcpci-mux-c0 {
+				compatible = "cros-ec,usbc-mux-tcpci";
+			};
+		};
+	};
+	i2c2: i2c@500 {
+		status = "okay";
+		compatible = "zephyr,i2c-emul-controller";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x500 4>;
+
+		pi3usb9201_emul: pi3usb9201@5f {
+			compatible = "pericom,pi3usb9201";
+			reg = <0x5f>;
+		};
+		tcpci_emul: tcpci_emul@82 {
+			compatible = "cros,tcpci-generic-emul";
+			status = "okay";
+			reg = <0x82>;
+			irq-gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
+		};
+	};
+	adc0: adc {
+		compatible = "zephyr,adc-emul";
+		nchannels = <6>;
+		ref-internal-mv = <3300>;
+		#io-channel-cells = <1>;
+		status = "okay";
+	};
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		adc_charger: charger {
+			enum-name = "ADC_TEMP_SENSOR_CHARGER";
+			io-channels = <&adc0 0>;
+		};
+	};
+	batteries {
+		default_battery: lgc_ac17a8m {
+			compatible = "lgc,ac17a8m", "battery-smart";
+		};
+	};
+	test_uart: uart@55556666 {
+		compatible = "vnd,serial";
+		reg = <0x55556666 0x1000>;
+		status = "okay";
+		buffer-size = <200>;
+	};
+};
+
+&gpio0 {
+	ngpios = <6>;
+};
+
+&i2c0 {
+	battery: sb@b {
+		compatible = "zephyr,smart-battery-emul";
+		reg = <0xb>;
+		cycle-count = <99>;
+		version = "BATTERY_SPEC_VER_1_1_WITH_PEC";
+		/* Real battery voltages are multiples of 4.4V. */
+		desired-charg-volt = <5000>;
+		desired-charg-cur = <1000>;
+		mf-name = "LGC";
+		dev-name = "AC17A8M";
+	};
+
+	isl923x_emul: isl923x@9 {
+		compatible = "cros,isl923x-emul";
+		status = "okay";
+		reg = <0x9>;
+		battery = <&battery>;
+	};
+};
diff --git a/zephyr/test/vboot_efs2/prj.conf b/zephyr/test/vboot_efs2/prj.conf
new file mode 100644
index 0000000000..431cdfa97c
--- /dev/null
+++ b/zephyr/test/vboot_efs2/prj.conf
@@ -0,0 +1,30 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_CROS_EC=y
+CONFIG_FLASH=y
+CONFIG_PLATFORM_EC=y
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
+CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y
+CONFIG_PLATFORM_EC_CHARGER_ISL9238=y
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=10
+CONFIG_PLATFORM_EC_CHARGE_RAMP_SW=y
+CONFIG_PLATFORM_EC_HOSTCMD=y
+CONFIG_PLATFORM_EC_SWITCH=n
+CONFIG_PLATFORM_EC_USBC=y
+CONFIG_PLATFORM_EC_USB_CHARGER=y
+CONFIG_PLATFORM_EC_USB_PD_DISCHARGE=n
+CONFIG_PLATFORM_EC_USB_PD_TCPM_MUX=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_CHARGER=y
+CONFIG_PLATFORM_EC_VBOOT_EFS2=y
+CONFIG_PLATFORM_EC_VBOOT_HASH=y
+CONFIG_RING_BUFFER=y
+CONFIG_SERIAL=y
+CONFIG_SHELL_BACKEND_DUMMY=y
+CONFIG_SHELL_BACKEND_DUMMY_BUF_SIZE=1000
+CONFIG_SHELL_BACKEND_SERIAL=n
+CONFIG_ZTEST=y
+CONFIG_ZTEST_NEW_API=y
diff --git a/zephyr/test/vboot_efs2/src/main.c b/zephyr/test/vboot_efs2/src/main.c
new file mode 100644
index 0000000000..7ad843e931
--- /dev/null
+++ b/zephyr/test/vboot_efs2/src/main.c
@@ -0,0 +1,393 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/bc12/pi3usb9201_public.h"
+#include "driver/tcpm/tcpci.h"
+#include "ec_app_main.h"
+#include "emul/emul_flash.h"
+#include "hooks.h"
+#include "ppc/sn5s330_public.h"
+#include "system_fake.h"
+#include "task.h"
+#include "usb_mux.h"
+#include "usbc_ppc.h"
+#include "vboot.h"
+#include "zephyr/devicetree.h"
+
+#include <stdint.h>
+
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/drivers/uart/serial_test.h>
+#include <zephyr/kernel.h>
+#include <zephyr/shell/shell_dummy.h>
+#include <zephyr/ztest_assert.h>
+#include <zephyr/ztest_test_new.h>
+
+#define SERIAL_BUFFER_SIZE DT_PROP(DT_NODELABEL(test_uart), buffer_size)
+
+static int show_power_shortage_called;
+void show_power_shortage(void)
+{
+	show_power_shortage_called++;
+}
+
+static int show_critical_error_called;
+void show_critical_error(void)
+{
+	show_critical_error_called++;
+}
+
+ZTEST(vboot_efs2, test_vboot_main_system_is_in_rw)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+	const char *outbuffer;
+	size_t buffer_size;
+
+	/* Set system_is_in_rw */
+	system_set_shrspi_image_copy(EC_IMAGE_RW);
+
+	shell_backend_dummy_clear_output(shell_zephyr);
+	vboot_main();
+
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+	zassert_equal(show_power_shortage_called, 1, NULL);
+
+	zassert_true(strstr(outbuffer, "VB Already in RW") != NULL,
+		     "Expected msg not in %s", outbuffer);
+
+	/* Verify some things we don't expect also. */
+	zassert_true(strstr(outbuffer, "VB Ping Cr50") == NULL,
+		     "Unexpected msg in %s", outbuffer);
+	zassert_true(strstr(outbuffer, "VB Exit") == NULL,
+		     "Unexpected msg in %s", outbuffer);
+	zassert_false(vboot_allow_usb_pd(), NULL);
+	zassert_equal(show_critical_error_called, 0, NULL);
+}
+
+ZTEST(vboot_efs2, test_vboot_main_system_is_manual_recovery)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+	const char *outbuffer;
+	size_t buffer_size;
+
+	system_enter_manual_recovery();
+
+	shell_backend_dummy_clear_output(shell_zephyr);
+	vboot_main();
+
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+	zassert_equal(show_power_shortage_called, 0, NULL);
+	zassert_true(strstr(outbuffer, "VB In recovery mode") != NULL,
+		     "Expected msg not in %s", outbuffer);
+
+	/* Verify some things we don't expect also. */
+	zassert_true(strstr(outbuffer, "VB Ping Cr50") == NULL,
+		     "Unexpected msg in %s", outbuffer);
+	zassert_true(strstr(outbuffer, "VB Exit") == NULL,
+		     "Unexpected msg in %s", outbuffer);
+	zassert_false(vboot_allow_usb_pd(), NULL);
+	zassert_equal(show_critical_error_called, 0, NULL);
+}
+
+ZTEST(vboot_efs2, test_vboot_main_stay_in_ro)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+	const char *outbuffer;
+	size_t buffer_size;
+
+	system_set_reset_flags(EC_RESET_FLAG_STAY_IN_RO);
+
+	shell_backend_dummy_clear_output(shell_zephyr);
+	vboot_main();
+
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+	zassert_equal(show_power_shortage_called, 0, NULL);
+
+	/* Verify some things we don't expect also. */
+	zassert_true(strstr(outbuffer, "VB In recovery mode") == NULL,
+		     "Expected msg not in %s", outbuffer);
+	zassert_true(strstr(outbuffer, "VB Ping Cr50") == NULL,
+		     "Unexpected msg in %s", outbuffer);
+	zassert_true(strstr(outbuffer, "VB Exit") == NULL,
+		     "Unexpected msg in %s", outbuffer);
+	zassert_false(vboot_allow_usb_pd(), NULL);
+	zassert_equal(show_critical_error_called, 0, NULL);
+}
+
+ZTEST(vboot_efs2, test_vboot_main_jump_timeout)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+	const char *outbuffer;
+	size_t buffer_size;
+
+	shell_backend_dummy_clear_output(shell_zephyr);
+	vboot_main();
+
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+	zassert_equal(show_critical_error_called, 1, NULL);
+
+	zassert_true(strstr(outbuffer, "VB Ping Cr50") != NULL,
+		     "Expected msg not in %s", outbuffer);
+	zassert_false(vboot_allow_usb_pd(), NULL);
+	zassert_equal(show_power_shortage_called, 0, NULL);
+}
+
+#define PACKET_MODE_GPIO NAMED_GPIOS_GPIO_NODE(ec_gsc_packet_mode)
+
+static const struct device *uart_shell_dev =
+	DEVICE_DT_GET(DT_CHOSEN(zephyr_shell_uart));
+static const struct device *gpio_dev =
+	DEVICE_DT_GET(DT_GPIO_CTLR(PACKET_MODE_GPIO, gpios));
+
+static void reply_cr50_payload(const struct device *dev, void *user_data)
+{
+	if (gpio_emul_output_get(gpio_dev,
+				 DT_GPIO_PIN(PACKET_MODE_GPIO, gpios))) {
+		struct cr50_comm_request req;
+		uint32_t bytes_read;
+
+		bytes_read = serial_vnd_peek_out_data(
+			uart_shell_dev, (void *)&req, sizeof(req));
+		/* If ! valid cr50_comm_request header, read 1 byte. */
+		while (bytes_read == sizeof(req) &&
+		       req.magic != CR50_PACKET_MAGIC) {
+			/* Consume one byte and then peek again. */
+			serial_vnd_read_out_data(uart_shell_dev, NULL, 1);
+			bytes_read = serial_vnd_peek_out_data(
+				uart_shell_dev, (void *)&req, sizeof(req));
+		}
+		if (bytes_read == sizeof(req)) {
+			/* If we have a full packet, consume it, and reply
+			 * with whatever is in user_data which holds a cr50
+			 * reply.
+			 */
+			if (req.size + sizeof(req) <=
+			    serial_vnd_out_data_size_get(uart_shell_dev)) {
+				serial_vnd_read_out_data(uart_shell_dev, NULL,
+							 req.size +
+								 sizeof(req));
+				serial_vnd_queue_in_data(
+					uart_shell_dev, user_data,
+					sizeof(struct cr50_comm_response));
+			}
+		}
+	} else {
+		/* Packet mode is off, so just consume enough bytes from the out
+		 * buffer to clear it.
+		 */
+		serial_vnd_read_out_data(uart_shell_dev, NULL,
+					 SERIAL_BUFFER_SIZE);
+	}
+}
+
+ZTEST(vboot_efs2, test_vboot_main_jump_bad_payload)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+	const char *outbuffer;
+	size_t buffer_size;
+	struct cr50_comm_response resp = {
+		.error = CR50_COMM_ERR_BAD_PAYLOAD,
+	};
+
+	serial_vnd_set_callback(uart_shell_dev, reply_cr50_payload, &resp);
+
+	shell_backend_dummy_clear_output(shell_zephyr);
+	vboot_main();
+
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+
+	zassert_true(strstr(outbuffer, "VB Ping Cr50") != NULL,
+		     "Expected msg not in %s", outbuffer);
+	zassert_true(vboot_allow_usb_pd(), NULL);
+	zassert_equal(show_power_shortage_called, 0, NULL);
+	zassert_equal(show_critical_error_called, 0, NULL);
+}
+
+/* This hits the default case in verify_and_jump. */
+ZTEST(vboot_efs2, test_vboot_main_jump_bad_crc)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+	const char *outbuffer;
+	size_t buffer_size;
+	struct cr50_comm_response resp = {
+		.error = CR50_COMM_ERR_CRC,
+	};
+
+	serial_vnd_set_callback(uart_shell_dev, reply_cr50_payload, &resp);
+
+	shell_backend_dummy_clear_output(shell_zephyr);
+	vboot_main();
+
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+
+	zassert_true(strstr(outbuffer, "VB Ping Cr50") != NULL,
+		     "Expected msg not in %s", outbuffer);
+	zassert_true(strstr(outbuffer, "VB Failed to verify RW (0xec03)") !=
+			     NULL,
+		     "Expected msg not in %s", outbuffer);
+	zassert_false(vboot_allow_usb_pd(), NULL);
+	zassert_equal(show_power_shortage_called, 0, NULL);
+	zassert_equal(show_critical_error_called, 1, NULL);
+}
+
+ZTEST(vboot_efs2, test_vboot_main_vboot_get_rw_hash_fail)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+	const char *outbuffer;
+	size_t buffer_size;
+	struct ec_response_vboot_hash response;
+	struct ec_params_vboot_hash hash_start_params = {
+		.cmd = EC_VBOOT_HASH_START,
+		.hash_type = EC_VBOOT_HASH_TYPE_SHA256,
+		.offset = 0,
+		.size = 0x12345,
+	};
+
+	shell_backend_dummy_clear_output(shell_zephyr);
+
+	zassert_ok(ec_cmd_vboot_hash(NULL, &hash_start_params, &response),
+		   NULL);
+	vboot_main();
+
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+
+	zassert_true(strstr(outbuffer, "VB Ping Cr50") != NULL,
+		     "Expected msg not in %s", outbuffer);
+	zassert_true(strstr(outbuffer, "VB Failed to verify RW (0x6)") != NULL,
+		     "Expected msg not in %s", outbuffer);
+	zassert_false(vboot_allow_usb_pd(), NULL);
+	zassert_equal(show_power_shortage_called, 0, NULL);
+	zassert_equal(show_critical_error_called, 1, NULL);
+}
+
+ZTEST(vboot_efs2, test_vboot_main_jump_success)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+	const char *outbuffer;
+	size_t buffer_size;
+	struct cr50_comm_response resp = {
+		.error = CR50_COMM_SUCCESS,
+	};
+
+	serial_vnd_set_callback(uart_shell_dev, reply_cr50_payload, &resp);
+
+	shell_backend_dummy_clear_output(shell_zephyr);
+	vboot_main();
+
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+
+	zassert_true(strstr(outbuffer, "VB Ping Cr50") != NULL,
+		     "Expected msg not in %s", outbuffer);
+	zassert_false(vboot_allow_usb_pd(), NULL);
+	zassert_equal(show_power_shortage_called, 0, NULL);
+	zassert_equal(show_critical_error_called, 1, NULL);
+	zassert_equal(system_get_reset_flags(), 0, NULL);
+}
+
+ZTEST(vboot_efs2, test_shutdown_hook_in_rw)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+	const char *outbuffer;
+	size_t buffer_size;
+
+	/* Set system_is_in_rw */
+	system_set_shrspi_image_copy(EC_IMAGE_RW);
+
+	shell_backend_dummy_clear_output(shell_zephyr);
+	hook_notify(HOOK_CHIPSET_SHUTDOWN_COMPLETE);
+
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+
+	zassert_true(strstr(outbuffer, "VB hook_shutdown") != NULL,
+		     "Expected msg not in %s", outbuffer);
+	zassert_equal(system_get_reset_flags(), 0, NULL);
+
+	/* Verify some things we don't expect also. */
+	zassert_true(strstr(outbuffer, "VB Ping Cr50") == NULL,
+		     "Unexpected msg in %s", outbuffer);
+	zassert_false(vboot_allow_usb_pd(), NULL);
+	zassert_equal(show_critical_error_called, 0, NULL);
+	zassert_equal(show_power_shortage_called, 0, NULL);
+}
+
+ZTEST(vboot_efs2, test_shutdown_hook_in_ro)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+	const char *outbuffer;
+	size_t buffer_size;
+
+	/* Set system_is_in_rw */
+	system_set_shrspi_image_copy(EC_IMAGE_RO);
+
+	shell_backend_dummy_clear_output(shell_zephyr);
+	hook_notify(HOOK_CHIPSET_SHUTDOWN_COMPLETE);
+
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+
+	zassert_true(strstr(outbuffer, "VB hook_shutdown") != NULL,
+		     "Expected msg not in %s", outbuffer);
+	zassert_true(strstr(outbuffer, "VB Ping Cr50") != NULL,
+		     "Expected msg not in %s", outbuffer);
+	zassert_equal(system_get_reset_flags(), EC_RESET_FLAG_AP_IDLE, NULL);
+	zassert_equal(show_critical_error_called, 1, NULL);
+
+	/* Verify some things we don't expect also. */
+	zassert_false(vboot_allow_usb_pd(), NULL);
+	zassert_equal(show_power_shortage_called, 0, NULL);
+}
+
+void *vboot_efs2_setup(void)
+{
+	/* Wait for the shell to start. */
+	k_sleep(K_MSEC(1));
+	zassert_equal(get_ec_shell()->ctx->state, SHELL_STATE_ACTIVE, NULL);
+
+	system_common_pre_init();
+
+	return NULL;
+}
+
+void vboot_efs2_cleanup(void *fixture)
+{
+	ARG_UNUSED(fixture);
+
+	system_set_shrspi_image_copy(EC_IMAGE_RO);
+	show_power_shortage_called = 0;
+	show_critical_error_called = 0;
+	system_exit_manual_recovery();
+	system_clear_reset_flags(EC_RESET_FLAG_STAY_IN_RO | EC_RESET_FLAG_EFS |
+				 EC_RESET_FLAG_AP_IDLE);
+	vboot_disable_pd();
+	serial_vnd_set_callback(uart_shell_dev, NULL, NULL);
+	serial_vnd_read_out_data(uart_shell_dev, NULL, SERIAL_BUFFER_SIZE);
+}
+
+ZTEST_SUITE(vboot_efs2, NULL, vboot_efs2_setup, NULL, vboot_efs2_cleanup, NULL);
+
+int board_set_active_charge_port(int port)
+{
+	return EC_ERROR_INVAL;
+}
+
+__override void board_set_charge_limit(int port, int supplier, int charge_ma,
+				       int max_ma, int charge_mv)
+{
+}
+
+void pd_power_supply_reset(int port)
+{
+}
+
+int pd_check_vconn_swap(int port)
+{
+	return 0;
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	return EC_SUCCESS;
+}
+
+enum usbc_port { USBC_PORT_COUNT };
diff --git a/zephyr/test/vboot_efs2/testcase.yaml b/zephyr/test/vboot_efs2/testcase.yaml
new file mode 100644
index 0000000000..59716f3fb2
--- /dev/null
+++ b/zephyr/test/vboot_efs2/testcase.yaml
@@ -0,0 +1,8 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+common:
+  platform_allow: native_posix
+tests:
+  vboot_efs2.default:
+    timeout: 120
diff --git a/zephyr/zmake/.pylintrc b/zephyr/zmake/.pylintrc
new file mode 100644
index 0000000000..a0f9ac790b
--- /dev/null
+++ b/zephyr/zmake/.pylintrc
@@ -0,0 +1,24 @@
+[MASTER]
+init-hook='import sys; sys.path.extend(["zephyr/zmake"])'
+
+[BASIC]
+good-names=
+    e,
+
+# cros lint doesn't inherit the pylintrc from the parent dir.
+# These settings are copied from platform/ec/pylintrc
+[MESSAGES CONTROL]
+
+disable=
+    bad-continuation,
+    bad-whitespace,
+    # These have nothing to do with black, they are just annoying
+    fixme,
+    too-many-arguments,
+    too-many-statements,
+    too-many-branches,
+    too-many-locals
+
+[format]
+
+string-quote=double
diff --git a/zephyr/zmake/.vpython3 b/zephyr/zmake/.vpython3
new file mode 100644
index 0000000000..cb48b07225
--- /dev/null
+++ b/zephyr/zmake/.vpython3
@@ -0,0 +1,71 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Include all packages needed to run the zmake unit tests.
+python_version: "3.8"
+
+wheel: <
+  name: "infra/python/wheels/attrs-py2_py3"
+  version: "version:21.4.0"
+>
+wheel: <
+  name: "infra/python/wheels/coverage/${vpython_platform}"
+  version: "version:5.5.chromium.3"
+>
+wheel: <
+  name: "infra/python/wheels/hypothesis-py3"
+  version: "version:6.9.1"
+>
+wheel: <
+  name: "infra/python/wheels/iniconfig-py3"
+  version: "version:1.1.1"
+>
+wheel: <
+  name: "infra/python/wheels/importlib-metadata-py2_py3"
+  version: "version:1.6.0"
+>
+wheel: <
+  name: "infra/python/wheels/packaging-py2_py3"
+  version: "version:16.8"
+>
+wheel: <
+  name: "infra/python/wheels/pluggy-py3"
+  version: "version:0.13.1"
+>
+wheel: <
+  name: "infra/python/wheels/py-py2_py3"
+  version: "version:1.10.0"
+>
+wheel: <
+  name: "infra/python/wheels/pyparsing-py3"
+  version: "version:3.0.7"
+>
+wheel: <
+  name: "infra/python/wheels/pytest-py3"
+  version: "version:6.2.2"
+>
+wheel: <
+  name: "infra/python/wheels/pytest-cov-py2_py3"
+  version: "version:2.11.1"
+>
+wheel: <
+  name: "infra/python/wheels/six-py2_py3"
+  version: "version:1.16.0"
+>
+wheel: <
+  name: "infra/python/wheels/sortedcontainers-py3"
+  version: "version:2.4.0"
+>
+wheel: <
+  name: "infra/python/wheels/testfixtures-py3"
+  version: "version:7.0.0"
+>
+wheel: <
+  name: "infra/python/wheels/toml-py3"
+  version: "version:0.10.1"
+>
+wheel: <
+  name: "infra/python/wheels/zipp-py3"
+  version: "version:3.7.0"
+>
diff --git a/zephyr/zmake/README.md b/zephyr/zmake/README.md
new file mode 100644
index 0000000000..c5de8c9b0f
--- /dev/null
+++ b/zephyr/zmake/README.md
@@ -0,0 +1,139 @@
+# Zmake
+
+<!-- Auto-generated contents!  Run "zmake generate-readme" to update. -->
+
+[TOC]
+
+## Usage
+
+**Usage:** `zmake [-h] [--checkout CHECKOUT] [-j JOBS] [--goma] [-l {DEBUG,INFO,WARNING,ERROR,CRITICAL} | -D] [-L] [--log-label] [--modules-dir MODULES_DIR] [--projects-dir PROJECTS_DIR] [--zephyr-base ZEPHYR_BASE] subcommand ...`
+
+Chromium OS's meta-build tool for Zephyr
+
+#### Positional Arguments
+
+|   |   |
+|---|---|
+| `subcommand` | Subcommand to run |
+
+#### Optional Arguments
+
+|   |   |
+|---|---|
+| `-h`, `--help` | show this help message and exit |
+| `--checkout CHECKOUT` | Path to ChromiumOS checkout |
+| `-j JOBS`, `--jobs JOBS` | Degree of multiprogramming to use |
+| `--goma` | Enable hyperspeed compilation with Goma! (Googlers only) |
+| `-l {DEBUG,INFO,WARNING,ERROR,CRITICAL}`, `--log-level {DEBUG,INFO,WARNING,ERROR,CRITICAL}` | Set the logging level (default=INFO) |
+| `-D`, `--debug` | Alias for --log-level=DEBUG |
+| `-L`, `--no-log-label` | Turn off logging labels |
+| `--log-label` | Turn on logging labels |
+| `--modules-dir MODULES_DIR` | The path to a directory containing all modules needed.  If unspecified, zmake will assume you have a Chrome OS checkout and try locating them in the checkout. |
+| `--projects-dir PROJECTS_DIR` | Base directory to search for BUILD.py files. |
+| `--zephyr-base ZEPHYR_BASE` | Path to Zephyr OS repository |
+
+## Subcommands
+
+### zmake configure
+
+**Usage:** `zmake configure [-h] [--bringup] [--clobber] [--static] [--save-temps] [--allow-warnings] [-B BUILD_DIR] [-c] [--delete-intermediates] [-D CMAKE_DEFS] [-t TOOLCHAIN] [--extra-cflags EXTRA_CFLAGS] (-a | project_name [project_name ...])`
+
+#### Positional Arguments
+
+|   |   |
+|---|---|
+| `project_name` | Name(s) of the project(s) to build |
+
+#### Optional Arguments
+
+|   |   |
+|---|---|
+| `-h`, `--help` | show this help message and exit |
+| `--bringup` | Enable bringup debugging features |
+| `--clobber` | Delete existing build directories, even if configuration is unchanged |
+| `--static` | Generate static version information for reproducible builds |
+| `--save-temps` | Save the temporary files containing preprocessor output |
+| `--allow-warnings` | Do not treat warnings as errors |
+| `-B BUILD_DIR`, `--build-dir BUILD_DIR` | Root build directory, project files will be in ${build_dir}/${project_name} |
+| `-c`, `--coverage` | Enable CONFIG_COVERAGE Kconfig. |
+| `--delete-intermediates` | Delete intermediate files to save disk space |
+| `-D CMAKE_DEFS`, `--cmake-define CMAKE_DEFS` | None |
+| `-t TOOLCHAIN`, `--toolchain TOOLCHAIN` | Name of toolchain to use |
+| `--extra-cflags EXTRA_CFLAGS` | Additional CFLAGS to use for target builds |
+| `-a`, `--all` | Select all projects |
+
+### zmake build
+
+**Usage:** `zmake build [-h] [--bringup] [--clobber] [--static] [--save-temps] [--allow-warnings] [-B BUILD_DIR] [-c] [--delete-intermediates] [-D CMAKE_DEFS] [-t TOOLCHAIN] [--extra-cflags EXTRA_CFLAGS] (-a | project_name [project_name ...])`
+
+#### Positional Arguments
+
+|   |   |
+|---|---|
+| `project_name` | Name(s) of the project(s) to build |
+
+#### Optional Arguments
+
+|   |   |
+|---|---|
+| `-h`, `--help` | show this help message and exit |
+| `--bringup` | Enable bringup debugging features |
+| `--clobber` | Delete existing build directories, even if configuration is unchanged |
+| `--static` | Generate static version information for reproducible builds |
+| `--save-temps` | Save the temporary files containing preprocessor output |
+| `--allow-warnings` | Do not treat warnings as errors |
+| `-B BUILD_DIR`, `--build-dir BUILD_DIR` | Root build directory, project files will be in ${build_dir}/${project_name} |
+| `-c`, `--coverage` | Enable CONFIG_COVERAGE Kconfig. |
+| `--delete-intermediates` | Delete intermediate files to save disk space |
+| `-D CMAKE_DEFS`, `--cmake-define CMAKE_DEFS` | None |
+| `-t TOOLCHAIN`, `--toolchain TOOLCHAIN` | Name of toolchain to use |
+| `--extra-cflags EXTRA_CFLAGS` | Additional CFLAGS to use for target builds |
+| `-a`, `--all` | Select all projects |
+
+### zmake compare-builds
+
+**Usage:** `zmake compare-builds [-h] [--ref1 REF1] [--ref2 REF2] [-k] [-n] [-b] [-d] [-t TOOLCHAIN] [--extra-cflags EXTRA_CFLAGS] (-a | project_name [project_name ...])`
+
+#### Positional Arguments
+
+|   |   |
+|---|---|
+| `project_name` | Name(s) of the project(s) to build |
+
+#### Optional Arguments
+
+|   |   |
+|---|---|
+| `-h`, `--help` | show this help message and exit |
+| `--ref1 REF1` | 1st git reference (commit, branch, etc), default=HEAD |
+| `--ref2 REF2` | 2nd git reference (commit, branch, etc), default=HEAD~ |
+| `-k`, `--keep-temps` | Keep temporary build directories on exit |
+| `-n`, `--compare-configs` | Compare configs of build outputs |
+| `-b`, `--compare-binaries-disable` | Don't compare binaries of build outputs |
+| `-d`, `--compare-devicetrees` | Compare devicetrees of build outputs |
+| `-t TOOLCHAIN`, `--toolchain TOOLCHAIN` | Name of toolchain to use |
+| `--extra-cflags EXTRA_CFLAGS` | Additional CFLAGS to use for target builds |
+| `-a`, `--all` | Select all projects |
+
+### zmake list-projects
+
+**Usage:** `zmake list-projects [-h] [--format FMT]`
+
+#### Optional Arguments
+
+|   |   |
+|---|---|
+| `-h`, `--help` | show this help message and exit |
+| `--format FMT` | Output format to print projects (str.format(config=project.config) is called on this for each project). |
+
+### zmake generate-readme
+
+**Usage:** `zmake generate-readme [-h] [-o OUTPUT_FILE] [--diff]`
+
+#### Optional Arguments
+
+|   |   |
+|---|---|
+| `-h`, `--help` | show this help message and exit |
+| `-o OUTPUT_FILE`, `--output-file OUTPUT_FILE` | File to write to.  It will only be written if changed. |
+| `--diff` | If specified, diff the README with the expected contents instead of writing out. |
diff --git a/zephyr/zmake/bazel_main.py b/zephyr/zmake/bazel_main.py
new file mode 100644
index 0000000000..3df8636c1a
--- /dev/null
+++ b/zephyr/zmake/bazel_main.py
@@ -0,0 +1,16 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Entry point for Bazel execution.
+
+Bazel can't use zmake/__main__.py as it puts the main in PYTHONPATH.
+"""
+
+import sys
+
+from zmake import __main__
+
+
+if __name__ == "__main__":
+    sys.exit(__main__.main())
diff --git a/zephyr/zmake/run_tests.sh b/zephyr/zmake/run_tests.sh
new file mode 100755
index 0000000000..4eb0667a4a
--- /dev/null
+++ b/zephyr/zmake/run_tests.sh
@@ -0,0 +1,57 @@
+#!/bin/bash
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Run tests for zmake itself (not including Zephyr builds).
+# You can run a single test with:
+# ./run_tests.sh tests/test_zmake.py::TestFilters::test_filter_normal
+# Or debug a test with:
+# ./run_tests.sh -- --pdb tests/test_zmake.py::TestFilters::test_filter_normal
+# Run with coverage
+# ./run_tests.sh --coverage
+
+# Exit if any command exits non-zero.
+set -e
+
+TEMP=$(getopt -o ch --long coverage,help -n 'run_tests.sh' -- "$@")
+eval set -- "${TEMP}"
+
+COVERAGE=false
+HELP="run_tests.sh [ -c | --coverage ] [ -h | --help ] pytest_args"
+while true; do
+  case "$1" in
+    -h | --help ) echo "${HELP}" ; exit 0 ;;
+    -c | --coverage ) COVERAGE=true; shift ;;
+    -- ) shift; break ;;
+    * ) break ;;
+  esac
+done
+
+PYTHON=python3
+if which vpython3; then
+  PYTHON="vpython3"
+fi
+
+# Show commands being run.
+set -x
+
+# cd to the directory containing this script.
+cd "$(dirname "$(realpath -e "${BASH_SOURCE[0]}")")"
+
+# Test the copy in-tree, instead of what setuptools or the ebuild
+# installed.
+export PYTHONPATH="${PWD}"
+
+# Run pytest.
+if "${COVERAGE}" ; then
+  ${PYTHON?} -m coverage erase
+  ${PYTHON?} -m coverage run --source=zmake -m pytest -v "$@"
+  ${PYTHON?} -m coverage report
+  ${PYTHON?} -m coverage html
+else
+  ${PYTHON?} -m pytest -v "$@"
+fi
+
+# Check auto-generated README.md is as expected.
+${PYTHON?} -m zmake generate-readme --diff
diff --git a/zephyr/zmake/setup.py b/zephyr/zmake/setup.py
new file mode 100644
index 0000000000..6e986ef8d0
--- /dev/null
+++ b/zephyr/zmake/setup.py
@@ -0,0 +1,48 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Configuration to allow pip install."""
+import setuptools
+
+
+setuptools.setup(
+    name="zephyr-chrome-utils",
+    version="0.1",
+    description="CrOS Zephyr Utilities",
+    long_description="Utilities used for working on a Zephyr-based EC",
+    url="https://chromium.googlesource.com/chromiumos/platform/ec",
+    author="ChromiumOS Authors",
+    author_email="chromiumos-dev@chromium.org",
+    license="BSD",
+    # What does your project relate to?
+    keywords="chromeos",
+    # You can just specify the packages manually here if your project is
+    # simple. Or you can use find_packages().
+    packages=["zmake", "zephyr_build_tools"],
+    python_requires=">=3.6, <4",
+    # List run-time dependencies here.  These will be installed by pip when
+    # your project is installed. For an analysis of "install_requires" vs pip's
+    # requirements files see:
+    # https://packaging.python.org/en/latest/requirements.html
+    install_requires=[
+        # Required until chroot upgrades to Python 3.7+.
+        "dataclasses>=0.6; python_version < '3.7'",
+    ],
+    # To provide executable scripts, use entry points in preference to the
+    # "scripts" keyword. Entry points provide cross-platform support and allow
+    # pip to create the appropriate form of executable for the target platform.
+    entry_points={
+        "console_scripts": [
+            "zmake=zmake.__main__:main",
+        ],
+    },
+    extras_require={
+        "tests": [
+            "coverage",
+            "pytest",
+            "hypothesis",
+            "testfixtures",
+        ],
+    },
+)
diff --git a/zephyr/zmake/tests/conftest.py b/zephyr/zmake/tests/conftest.py
new file mode 100644
index 0000000000..af56f794cc
--- /dev/null
+++ b/zephyr/zmake/tests/conftest.py
@@ -0,0 +1,59 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Common settings and fixtures for all tests."""
+
+import os
+import pathlib
+
+import hypothesis  # pylint:disable=import-error
+import pytest  # pylint:disable=import-error
+import zmake.zmake as zm
+
+
+hypothesis.settings.register_profile(
+    "cq", suppress_health_check=hypothesis.HealthCheck.all()
+)
+hypothesis.settings.load_profile("cq")
+
+# pylint: disable=redefined-outer-name,unused-argument
+
+
+@pytest.fixture
+def zmake_factory_from_dir(tmp_path):
+    """Creates module dirs and returns a Zmake object factory."""
+
+    os.mkdir(tmp_path / "ec")
+    os.mkdir(tmp_path / "ec" / "zephyr")
+    (tmp_path / "ec" / "zephyr" / "module.yml").write_text("")
+    zephyr_base = tmp_path / "zephyr_base"
+
+    def _zmake_factory(**kwargs):
+        return zm.Zmake(zephyr_base=zephyr_base, modules_dir=tmp_path, **kwargs)
+
+    return _zmake_factory
+
+
+@pytest.fixture
+def zmake_from_dir(zmake_factory_from_dir):
+    """Creates module dirs and returns a Zmake object."""
+    return zmake_factory_from_dir()
+
+
+@pytest.fixture
+def fake_checkout(tmp_path):
+    """Creates a fake checkout dir and returns the path to zmake."""
+
+    actual_zmake_src_path = pathlib.Path(__file__).parent.parent
+    fake_zmake_path = pathlib.Path(tmp_path) / "src/platform/ec/zephyr/zmake"
+    os.makedirs(fake_zmake_path.parent)
+    os.symlink(actual_zmake_src_path, fake_zmake_path)
+    return fake_zmake_path
+
+
+@pytest.fixture
+def zmake_from_checkout(tmp_path, fake_checkout):
+    """Creates a fake checkout dir and returns a Zmake object."""
+
+    return zm.Zmake(checkout=tmp_path)
diff --git a/zephyr/zmake/tests/files/sample_err.txt b/zephyr/zmake/tests/files/sample_err.txt
new file mode 100644
index 0000000000..44928afb0a
--- /dev/null
+++ b/zephyr/zmake/tests/files/sample_err.txt
@@ -0,0 +1,321 @@
+Building /tmp/z/vol:ro: /usr/bin/ninja -C /tmp/z/vol/build-ro
+Running /usr/bin/ninja -C /tmp/z/vol/build-ro
+ninja: Entering directory `/tmp/z/vol/build-ro'
+devicetree error: 'adc' is marked as required in 'properties:' in /home/sjg/c/src/platform/ec/zephyr/dts/bindings/temp/temp-3v3-30k9-47k-4050b.yaml, but does not appear in <Node /named-temp-sensors/ddr_soc in 'volteer.dts.pre.tmp'>
+[1/310] Preparing syscall dependency handling
+[2/310] Generating misc/generated/syscalls_subdirs.trigger
+[3/310] Generating ../../ec/include/generated/ec_version.h
+[4/310] Generating misc/generated/syscalls.json, misc/generated/struct_tags.json
+[5/310] Generating include/generated/syscall_dispatch.c, include/generated/syscall_list.h
+[6/310] Generating include/generated/kobj-types-enum.h, include/generated/otype-to-str.h
+[7/310] Generating include/generated/driver-validation.h
+[8/310] Building C object zephyr/CMakeFiles/offsets.dir/arch/arm/core/offsets/offsets.c.obj
+[9/310] Generating include/generated/offsets.h
+[10/310] Building C object CMakeFiles/app.dir/home/sjg/c/src/platform/ec/zephyr/app/ec/main_shim.c.obj
+[11/310] Building C object CMakeFiles/app.dir/home/sjg/c/src/platform/ec/zephyr/drivers/cros_bbram/cros_bbram_npcx.c.obj
+[12/310] Building C object CMakeFiles/app.dir/home/sjg/c/src/platform/ec/zephyr/app/ec/ec_app_main.c.obj
+[13/310] Building C object CMakeFiles/app.dir/home/sjg/c/src/platform/ec/zephyr/drivers/cros_flash/cros_flash_npcx.c.obj
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diff --git a/zephyr/zmake/tests/files/sample_rw_INFO.txt b/zephyr/zmake/tests/files/sample_rw_INFO.txt
new file mode 100644
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--- /dev/null
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diff --git a/zephyr/zmake/tests/test_build_config.py b/zephyr/zmake/tests/test_build_config.py
new file mode 100644
index 0000000000..6b4ab203b6
--- /dev/null
+++ b/zephyr/zmake/tests/test_build_config.py
@@ -0,0 +1,293 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Tests of zmake's build config system."""
+
+import argparse
+import os
+import pathlib
+import string
+import tempfile
+
+import hypothesis  # pylint:disable=import-error
+import hypothesis.strategies as st  # pylint:disable=import-error
+import pytest  # pylint:disable=import-error
+from zmake.build_config import BuildConfig
+import zmake.jobserver
+import zmake.util as util
+
+
+# pylint:disable=redefined-outer-name,unused-argument
+
+# Strategies for use with hypothesis
+filenames = st.text(
+    alphabet=set(string.printable) - {"/", ";"}, min_size=1, max_size=254
+).filter(lambda name: name not in (".", ".."))
+paths = st.builds(
+    lambda parts: pathlib.Path("/", *parts), st.iterables(filenames, min_size=1)
+)
+config_keys = st.text(alphabet=set(string.ascii_uppercase) | {"_"}, min_size=1)
+config_values = st.builds(str, st.just("y") | st.just("n") | st.integers())
+config_dicts = st.dictionaries(keys=config_keys, values=config_values)
+config_dicts_at_least_one_entry = st.dictionaries(
+    keys=config_keys, values=config_values, min_size=1
+)
+
+build_configs = st.builds(
+    BuildConfig,
+    cmake_defs=config_dicts,
+    kconfig_defs=config_dicts,
+    kconfig_files=st.lists(paths),
+)
+build_configs_no_kconfig = st.builds(BuildConfig, cmake_defs=config_dicts)
+build_configs_with_at_least_one_kconfig = st.builds(
+    BuildConfig,
+    cmake_defs=config_dicts,
+    kconfig_defs=config_dicts_at_least_one_entry,
+)
+
+
+@hypothesis.given(st.data(), build_configs)
+def test_merge(coins, combined):
+    """Test that when splitting a config in half and merging the two
+    halves, we get the original config back.
+    """
+
+    def split(iterable):
+        left = []
+        right = []
+        bools = st.booleans()
+        for item in iterable:
+            if coins.draw(bools):
+                left.append(item)
+            else:
+                right.append(item)
+        return left, right
+
+    # Split the original config into two
+    cmake1, cmake2 = split(combined.cmake_defs.items())
+    kconf1, kconf2 = split(combined.kconfig_defs.items())
+    files1, files2 = split(combined.kconfig_files)
+
+    config1 = BuildConfig(
+        cmake_defs=dict(cmake1),
+        kconfig_defs=dict(kconf1),
+        kconfig_files=files1,
+    )
+    config2 = BuildConfig(
+        cmake_defs=dict(cmake2),
+        kconfig_defs=dict(kconf2),
+        kconfig_files=files2,
+    )
+
+    # Merge the split configs
+    merged = config1 | config2
+
+    # Assert that the merged split configs is the original config
+    assert merged.cmake_defs == combined.cmake_defs
+    assert merged.kconfig_defs == combined.kconfig_defs
+    assert set(merged.kconfig_files) == set(combined.kconfig_files)
+
+
+class FakeJobClient(zmake.jobserver.JobClient):
+    """Simple job client to capture argv/environ."""
+
+    def __init__(self):
+        self.captured_argv = []
+        self.captured_env = {}
+
+    def get_job(self):
+        return zmake.jobserver.JobHandle(lambda: None)
+
+    def popen(self, argv, **kwargs):
+        kwargs.setdefault("env", {})
+        self.captured_argv = [str(arg) for arg in argv]
+        self.captured_env = {str(k): str(v) for k, v in kwargs["env"].items()}
+
+
+def parse_cmake_args(argv):
+    """Parse command line arguments like cmake does.
+
+    This is an intenionally minimal implementation, which only
+    understands the subset of arguments actually used by zmake.
+
+    Args:
+        argv: The argument list.
+
+    Returns:
+        A 2-tuple of a namespace from argparse and the corresponding
+        parsed Cmake definitions.
+    """
+    assert argv[0] == "/usr/bin/cmake"
+
+    parser = argparse.ArgumentParser(add_help=False)
+    parser.add_argument("-S", dest="source_dir", type=pathlib.Path)
+    parser.add_argument("-B", dest="build_dir", type=pathlib.Path)
+    parser.add_argument("-G", dest="generator")
+    parser.add_argument("-D", dest="defs", action="append", default=[])
+    args = parser.parse_args(argv[1:])
+
+    build_cfg = BuildConfig.from_args(args.defs)
+    return args, build_cfg.cmake_defs
+
+
+@hypothesis.given(build_configs_no_kconfig, paths, paths)
+@hypothesis.settings(deadline=60000)
+def test_popen_cmake_no_kconfig(conf: BuildConfig, project_dir, build_dir):
+    """Test popen_cmake for a config with no kconfig definitions."""
+    job_client = FakeJobClient()
+    conf.popen_cmake(job_client, project_dir, build_dir)
+
+    _, cmake_defs = parse_cmake_args(job_client.captured_argv)
+
+    assert cmake_defs == conf.cmake_defs
+
+
+@hypothesis.given(build_configs_with_at_least_one_kconfig, paths, paths)
+@hypothesis.settings(deadline=60000)
+def test_popen_cmake_kconfig_but_no_file(
+    conf: BuildConfig, project_dir, build_dir
+):
+    """Test that running popen_cmake with Kconfig definitions to write
+    out, but no path to do so, should raise an error.
+    """
+    job_client = FakeJobClient()
+
+    with pytest.raises(ValueError):
+        conf.popen_cmake(job_client, project_dir, build_dir)
+
+
+@hypothesis.given(build_configs, paths, paths)
+@hypothesis.settings(deadline=60000)
+def test_popen_cmake_kconfig(conf: BuildConfig, project_dir, build_dir):
+    """Test calling popen_cmake and verifying the kconfig_files."""
+    job_client = FakeJobClient()
+
+    with tempfile.NamedTemporaryFile("w", delete=False) as file:
+        temp_path = file.name
+
+    try:
+        conf.popen_cmake(
+            job_client,
+            project_dir,
+            build_dir,
+            kconfig_path=pathlib.Path(temp_path),
+        )
+
+        _, cmake_defs = parse_cmake_args(job_client.captured_argv)
+
+        expected_kconfig_files = set(str(f) for f in conf.kconfig_files)
+        expected_kconfig_files.add(temp_path)
+
+        if expected_kconfig_files:
+            kconfig_files = set(cmake_defs.pop("CONF_FILE").split(";"))
+        else:
+            assert "CONF_FILE" not in cmake_defs
+            kconfig_files = set()
+
+        assert cmake_defs == conf.cmake_defs
+        assert kconfig_files == expected_kconfig_files
+
+        kconfig_defs = util.read_kconfig_file(temp_path)
+        assert kconfig_defs == conf.kconfig_defs
+    finally:
+        os.unlink(temp_path)
+
+
+@pytest.fixture
+def fake_kconfig_files(tmp_path):
+    """Provide a list of 4 different fake kconfig file paths."""
+
+    paths = [tmp_path / f"{letter}.conf" for letter in "ABCD"]
+
+    for path, cfg_name in zip(paths, ("ONE", "TWO", "THREE", "FOUR")):
+        path.write_text(
+            f"# Fake kconfig file for testing.\nCONFIG_{cfg_name}=y\n"
+        )
+
+    return paths
+
+
+def test_build_config_json_stability(fake_kconfig_files):
+    """as_json() should return equivalent strings for two equivalent
+    build configs.
+    """
+    config_a = BuildConfig(
+        cmake_defs={
+            "Z": "Y",
+            "X": "W",
+        },
+        kconfig_defs={
+            "CONFIG_A": "y",
+            "CONFIG_B": "n",
+        },
+        kconfig_files=fake_kconfig_files,
+    )
+
+    # Dict ordering is intentionally reversed in b.
+    config_b = BuildConfig(
+        cmake_defs={
+            "X": "W",
+            "Z": "Y",
+        },
+        kconfig_defs={
+            "CONFIG_B": "n",
+            "CONFIG_A": "y",
+        },
+        kconfig_files=list(fake_kconfig_files),
+    )
+
+    assert config_a.as_json() == config_b.as_json()
+
+
+def test_build_config_json_inequality():
+    """Two differing build configs should not have the same json
+    representation.
+    """
+    config_a = BuildConfig(cmake_defs={"A": "B"})
+    config_b = BuildConfig(kconfig_defs={"CONFIG_A": "y"})
+
+    assert config_a.as_json() != config_b.as_json()
+
+
+def test_build_config_json_inequality_dtc_changes(tmp_path):
+    """When DTC overlay files change, so should the JSON."""
+    dts_file_1 = tmp_path / "overlay1.dts"
+    dts_file_1.write_text("/* blah */\n")
+
+    dts_file_2 = tmp_path / "overlay2.dts"
+    dts_file_2.write_text("/* zonks! */\n")
+
+    cfg = BuildConfig(
+        cmake_defs={
+            "DTC_OVERLAY_FILE": f"{dts_file_1};{dts_file_2}",
+        },
+    )
+
+    orig_json = cfg.as_json()
+
+    # Now, change dts_file_2!
+    dts_file_2.write_text("/* I changed!! */\n")
+
+    new_json = cfg.as_json()
+
+    assert orig_json != new_json
+
+
+def test_kconfig_file_duplicates(fake_kconfig_files):
+    """Kconfig files should be like the "uniq" command.  Repeats should
+    be removed, but not duplicates."""
+    cfg = BuildConfig(
+        kconfig_files=[
+            fake_kconfig_files[0],
+            fake_kconfig_files[0],
+            fake_kconfig_files[1],
+            fake_kconfig_files[0],
+        ]
+    )
+    assert cfg.kconfig_files == [
+        fake_kconfig_files[0],
+        fake_kconfig_files[1],
+        fake_kconfig_files[0],
+    ]
diff --git a/zephyr/zmake/tests/test_generate_readme.py b/zephyr/zmake/tests/test_generate_readme.py
new file mode 100644
index 0000000000..290d6d7b31
--- /dev/null
+++ b/zephyr/zmake/tests/test_generate_readme.py
@@ -0,0 +1,65 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""
+Tests for the generate_readme.py file.
+"""
+
+import pytest  # pylint:disable=import-error
+import zmake.generate_readme as gen_readme
+
+
+def test_generate_readme_contents():
+    """Verify the readme contains at least one known line."""
+    readme = gen_readme.generate_readme()
+
+    # Look for a string we know should appear in the README.
+    assert "### zmake build\n" in readme
+
+
+@pytest.mark.parametrize(
+    ["expected_contents", "actual_contents", "return_code"],
+    [
+        ("abc\ndef\nghi\n", "abc\nghi\n", 1),
+        ("abc\ndef\nghi\n", "abc\ndef\nghi\n", 0),
+        ("abc\ndef\nghi\n", None, 1),
+    ],
+)
+def test_generate_readme_diff(
+    monkeypatch,
+    tmp_path,
+    zmake_from_dir,
+    expected_contents,
+    actual_contents,
+    return_code,
+):
+    """Verify that the diff function can detect different text."""
+
+    def generate_readme():
+        return expected_contents
+
+    monkeypatch.setattr(gen_readme, "generate_readme", generate_readme)
+
+    readme_file = tmp_path / "README.md"
+    if actual_contents is not None:
+        readme_file.write_text(actual_contents)
+
+    assert zmake_from_dir.generate_readme(readme_file, diff=True) == return_code
+
+
+@pytest.mark.parametrize("exist", [False, True])
+def test_generate_readme_file(monkeypatch, tmp_path, exist, zmake_from_dir):
+    """Verify that README.md can be created if it exists already or not."""
+
+    def generate_readme():
+        return "hello\n"
+
+    monkeypatch.setattr(gen_readme, "generate_readme", generate_readme)
+
+    readme_file = tmp_path / "README.md"
+    if exist:
+        readme_file.write_text("some existing contents\n")
+
+    assert zmake_from_dir.generate_readme(readme_file) == 0
+    assert readme_file.read_text() == "hello\n"
diff --git a/zephyr/zmake/tests/test_jobserver.py b/zephyr/zmake/tests/test_jobserver.py
new file mode 100644
index 0000000000..d9f4f63163
--- /dev/null
+++ b/zephyr/zmake/tests/test_jobserver.py
@@ -0,0 +1,201 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Test jobserver functionality."""
+
+from asyncio import subprocess
+import logging
+import os
+import threading
+
+import pytest  # pylint:disable=import-error
+import zmake.jobserver
+
+
+def _do_test_jobserver(
+    jobs, commandline_jobs=0, use_client=False, open_pipe=True
+):
+    """Test a jobserver configured with a specified number of jobs."""
+
+    effective_jobs = jobs
+    pipe = None
+    if use_client:
+        makeflags = f" -j{jobs}"
+        if jobs > 1:
+            pipe = os.pipe()
+            # GNU make puts one less job in the pipe than allowed, since you
+            # get one job "for free" without contacting the jobserver. Or
+            # another way of looking at is that make consumes one slot for you
+            # before calling your job just in case you aren't jobserver aware.
+            os.write(pipe[1], b"A" * (jobs - 1))
+            os.set_inheritable(pipe[0], True)
+            os.set_inheritable(pipe[1], True)
+            makeflags += f" --jobserver-auth={pipe[0]},{pipe[1]}"
+            if not open_pipe:
+                os.close(pipe[0])
+                os.close(pipe[1])
+                effective_jobs = 1
+        jobserver = zmake.jobserver.GNUMakeJobClient.from_environ(
+            env={"MAKEFLAGS": makeflags}, jobs=commandline_jobs
+        )
+    else:
+        jobserver = zmake.jobserver.GNUMakeJobServer(jobs=jobs)
+        pipe = jobserver._inheritable_pipe  # pylint:disable=protected-access
+        if jobs == 1:
+            makeflags = " -j1"
+        else:
+            makeflags = f" -j{jobs} --jobserver-auth={pipe[0]},{pipe[1]}"
+
+    lock = threading.Condition()
+    started_threads = 0
+    ended_threads = 0
+    active_threads = 0
+    please_exit = threading.Semaphore(0)
+    thread_count = jobs + 5
+    if commandline_jobs:
+        effective_jobs = commandline_jobs
+
+    def _my_thread():
+        nonlocal started_threads
+        nonlocal active_threads
+        nonlocal ended_threads
+        nonlocal pipe
+
+        with lock:
+            started_threads += 1
+            lock.notify_all()
+        with jobserver.get_job():
+            with lock:
+                active_threads += 1
+                lock.notify_all()
+            proc = jobserver.popen(
+                [
+                    "sh",
+                    "-c",
+                    'echo "MAKEFLAGS=${MAKEFLAGS}"; ls /proc/self/fd',
+                ],
+                stdout=subprocess.PIPE,
+                universal_newlines=True,
+            )
+            proc.wait()
+            output = proc.stdout.readlines()
+            assert output[0] == f"MAKEFLAGS={makeflags}\n"
+            if pipe:
+                if effective_jobs > 1:
+                    assert f"{pipe[0]}\n" in output
+                    assert f"{pipe[1]}\n" in output
+                else:
+                    assert f"{pipe[0]}\n" not in output
+                    assert f"{pipe[1]}\n" not in output
+
+            please_exit.acquire()  # pylint:disable=consider-using-with
+            with lock:
+                active_threads -= 1
+                ended_threads += 1
+                lock.notify_all()
+
+    logging.debug("Starting %s threads", thread_count)
+    for _ in range(thread_count):
+        threading.Thread(target=_my_thread, daemon=True).start()
+
+    with lock:
+        lock.wait_for(
+            lambda: started_threads == thread_count
+            and active_threads == effective_jobs,
+            10,
+        )
+        logging.debug("Asserting %s active_threads", effective_jobs)
+        assert started_threads == thread_count
+        assert active_threads == effective_jobs
+        assert ended_threads == 0
+
+    logging.debug("Ending %s threads", 5)
+    for _ in range(5):
+        please_exit.release()
+
+    with lock:
+        lock.wait_for(
+            lambda: active_threads == effective_jobs and ended_threads == 5, 10
+        )
+        logging.debug("Asserting %s active_threads", effective_jobs)
+        assert started_threads == thread_count
+        assert active_threads == effective_jobs
+        assert ended_threads == 5
+
+    logging.debug("Ending %s threads", thread_count - 5)
+    for _ in range(thread_count - 5):
+        please_exit.release()
+
+    with lock:
+        lock.wait_for(lambda: ended_threads == thread_count, 10)
+        logging.debug("Asserting %s active_threads", 0)
+        assert started_threads == thread_count
+        assert active_threads == 0
+        assert ended_threads == thread_count
+
+
+def test_jobserver_10():
+    """Test a jobserver configured with 10 jobs."""
+    _do_test_jobserver(10)
+
+
+def test_jobserver_2():
+    """Test a jobserver configured with 2 jobs."""
+    _do_test_jobserver(2)
+
+
+def test_jobserver_1():
+    """Test a jobserver configured with 1 job."""
+    _do_test_jobserver(1)
+
+
+def test_jobclient_10():
+    """Test a jobclient configured with 10 jobs."""
+    _do_test_jobserver(10, use_client=True)
+
+
+def test_jobclient_2():
+    """Test a jobserver configured with 2 jobs."""
+    _do_test_jobserver(2, use_client=True)
+
+
+def test_jobclient_1():
+    """Test a jobserver configured with 1 job."""
+    _do_test_jobserver(1, use_client=True)
+
+
+def test_jobclient_10_j1():
+    """Test a jobclient configured with 10 jobs but zmake -j1 was called."""
+    _do_test_jobserver(10, commandline_jobs=1, use_client=True)
+
+
+def test_jobclient_1_j1():
+    """Test a jobserver configured with 1 job but zmake -j1 was called."""
+    _do_test_jobserver(1, commandline_jobs=1, use_client=True)
+
+
+def test_jobclient_missing():
+    """Test a jobclient with no MAKEFLAGS."""
+    jobserver = zmake.jobserver.GNUMakeJobClient.from_environ(env={})
+    assert jobserver is None
+
+
+def test_jobclient_dryrun():
+    """Test a jobclient make dryrun in MAKEFLAGS."""
+    with pytest.raises(SystemExit) as pytest_wrapped_e:
+        zmake.jobserver.GNUMakeJobClient.from_environ(
+            env={"MAKEFLAGS": "n -j1"}
+        )
+    assert pytest_wrapped_e.type == SystemExit
+    assert pytest_wrapped_e.value.code == 0
+
+
+def test_jobclient_10_no_pipes():
+    """Test a jobclient configured with 10 jobs but the file descriptors are missing."""
+    _do_test_jobserver(10, use_client=True, open_pipe=False)
+
+
+def test_jobclient_1_no_pipes():
+    """Test a jobclient configured with 1 job but the file descriptors are missing."""
+    _do_test_jobserver(1, use_client=True, open_pipe=False)
diff --git a/zephyr/zmake/tests/test_modules.py b/zephyr/zmake/tests/test_modules.py
new file mode 100644
index 0000000000..a42192d789
--- /dev/null
+++ b/zephyr/zmake/tests/test_modules.py
@@ -0,0 +1,42 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Test zmake modules module."""
+
+import pathlib
+import tempfile
+
+import hypothesis  # pylint:disable=import-error
+import hypothesis.strategies as st  # pylint:disable=import-error
+import zmake.modules
+
+
+module_lists = st.lists(
+    st.one_of(*map(st.just, zmake.modules.known_modules)), unique=True
+)
+
+
+@hypothesis.given(module_lists)
+@hypothesis.settings(deadline=None)
+def test_locate_in_directory(modules):
+    """Test the basic functionality of locate_from_directory"""
+
+    with tempfile.TemporaryDirectory() as modules_dir:
+        modules_dir = pathlib.Path(modules_dir).resolve()
+
+        expected_modules = {}
+
+        for module in modules:
+            module_dir = modules_dir / module
+            zephyr_dir = module_dir / "zephyr"
+            zephyr_dir.mkdir(parents=True)
+
+            module_yml = zephyr_dir / "module.yml"
+            module_yml.write_bytes(b"")
+
+            expected_modules[module] = module_dir
+
+        assert (
+            zmake.modules.locate_from_directory(modules_dir) == expected_modules
+        )
diff --git a/zephyr/zmake/tests/test_multiproc_executor.py b/zephyr/zmake/tests/test_multiproc_executor.py
new file mode 100644
index 0000000000..ff443e2f4b
--- /dev/null
+++ b/zephyr/zmake/tests/test_multiproc_executor.py
@@ -0,0 +1,62 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Tests for zmake multiproc."""
+
+import threading
+
+import zmake.multiproc
+
+
+def test_single_function_executor_success():
+    """Test single function success."""
+    executor = zmake.multiproc.Executor()
+    executor.append(lambda: 0)
+    assert executor.wait() == 0
+
+
+def test_single_function_executor_fail():
+    """Test single function fail."""
+    executor = zmake.multiproc.Executor()
+    executor.append(lambda: -2)
+    assert executor.wait() == -2
+
+
+def test_single_function_executor_raise():
+    """Test single function raising an exception."""
+    executor = zmake.multiproc.Executor()
+    executor.append(lambda: 1 / 0)
+    assert executor.wait() != 0
+
+
+def _lock_step(cond, predicate, step, return_value=0):
+    with cond:
+        cond.wait_for(predicate=lambda: step[0] == predicate)
+        step[0] += 1
+        cond.notify_all()
+    return return_value
+
+
+def test_two_function_executor_wait_for_both():
+    """Test two functions in executor."""
+    cond = threading.Condition()
+    step = [0]
+    executor = zmake.multiproc.Executor()
+    executor.append(lambda: _lock_step(cond=cond, predicate=0, step=step))
+    executor.append(lambda: _lock_step(cond=cond, predicate=1, step=step))
+    assert executor.wait() == 0
+    assert step[0] == 2
+
+
+def test_two_function_executor_one_fails():
+    """Test two functions in executor, when one fails."""
+    cond = threading.Condition()
+    step = [0]
+    executor = zmake.multiproc.Executor()
+    executor.append(
+        lambda: _lock_step(cond=cond, predicate=0, step=step, return_value=-1)
+    )
+    executor.append(lambda: _lock_step(cond=cond, predicate=1, step=step))
+    assert executor.wait() == -1
+    assert step[0] == 2
diff --git a/zephyr/zmake/tests/test_multiproc_logging.py b/zephyr/zmake/tests/test_multiproc_logging.py
new file mode 100644
index 0000000000..88d029675b
--- /dev/null
+++ b/zephyr/zmake/tests/test_multiproc_logging.py
@@ -0,0 +1,121 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Tests for zmake multiproc logging code."""
+
+import io
+import logging
+import os
+import threading
+import unittest.mock as mock
+
+import zmake.multiproc
+
+
+def test_read_output_from_pipe():
+    """Test reading output from a pipe."""
+    semaphore = threading.Semaphore(0)
+    pipe = os.pipe()
+    file_desc = io.TextIOWrapper(os.fdopen(pipe[0], "rb"), encoding="utf-8")
+    logger = mock.Mock(spec=logging.Logger)
+    logger.log.side_effect = lambda log_lvl, line: semaphore.release()
+    zmake.multiproc.LogWriter.log_output(
+        logger, logging.DEBUG, file_desc, job_id=""
+    )
+    os.write(pipe[1], "Hello\n".encode("utf-8"))
+    semaphore.acquire()
+    logger.log.assert_called_with(logging.DEBUG, "Hello")
+
+
+def test_read_output_change_log_level():
+    """Test changing the log level."""
+    semaphore = threading.Semaphore(0)
+    pipe = os.pipe()
+    file_desc = io.TextIOWrapper(os.fdopen(pipe[0], "rb"), encoding="utf-8")
+    logger = mock.Mock(spec=logging.Logger)
+    logger.log.side_effect = lambda log_lvl, line: semaphore.release()
+    # This call will log output from fd (the file descriptor) to DEBUG, though
+    # when the line starts with 'World', the logging level will be switched to
+    # CRITICAL (see the content of the log_lvl_override_func).
+    zmake.multiproc.LogWriter.log_output(
+        logger=logger,
+        log_level=logging.DEBUG,
+        file_descriptor=file_desc,
+        log_level_override_func=lambda line, lvl: logging.CRITICAL
+        if line.startswith("World")
+        else lvl,
+        job_id="",
+    )
+    os.write(pipe[1], "Hello\n".encode("utf-8"))
+    semaphore.acquire()
+    os.write(pipe[1], "World\n".encode("utf-8"))
+    semaphore.acquire()
+    os.write(pipe[1], "Bye\n".encode("utf-8"))
+    semaphore.acquire()
+    logger.log.assert_has_calls(
+        [
+            mock.call(logging.DEBUG, "Hello"),
+            mock.call(logging.CRITICAL, "World"),
+            mock.call(logging.CRITICAL, "Bye"),
+        ]
+    )
+
+
+def test_read_output_from_second_pipe():
+    """Test that we can read from more than one pipe.
+
+    This is particularly important since we will block on a read/select once we
+    have a file descriptor. It is important that we break from the select and
+    start it again with the updated list when a new one is added.
+    """
+    semaphore = threading.Semaphore(0)
+    pipes = [os.pipe(), os.pipe()]
+    fds = [
+        io.TextIOWrapper(os.fdopen(pipes[0][0], "rb"), encoding="utf-8"),
+        io.TextIOWrapper(os.fdopen(pipes[1][0], "rb"), encoding="utf-8"),
+    ]
+
+    logger = mock.Mock(spec=logging.Logger)
+    logger.log.side_effect = lambda log_lvl, fmt, id, line: semaphore.release()
+
+    zmake.multiproc.LogWriter.log_output(
+        logger, logging.DEBUG, fds[0], job_id="0"
+    )
+    zmake.multiproc.LogWriter.log_output(
+        logger, logging.ERROR, fds[1], job_id="1"
+    )
+
+    os.write(pipes[1][1], "Hello\n".encode("utf-8"))
+    semaphore.acquire()
+    logger.log.assert_called_with(logging.ERROR, "[%s]%s", "1", "Hello")
+
+
+def test_read_output_after_another_pipe_closed():
+    """Test processing output from a pipe after closing another.
+
+    Since we don't want to complicate the API. File descriptors are
+    automatically pruned away when closed. Make sure that the other descriptors
+    remain functional when that happens.
+    """
+    semaphore = threading.Semaphore(0)
+    pipes = [os.pipe(), os.pipe()]
+    fds = [
+        io.TextIOWrapper(os.fdopen(pipes[0][0], "rb"), encoding="utf-8"),
+        io.TextIOWrapper(os.fdopen(pipes[1][0], "rb"), encoding="utf-8"),
+    ]
+
+    logger = mock.Mock(spec=logging.Logger)
+    logger.log.side_effect = lambda log_lvl, fmt, id, line: semaphore.release()
+
+    zmake.multiproc.LogWriter.log_output(
+        logger, logging.DEBUG, fds[0], job_id="0"
+    )
+    zmake.multiproc.LogWriter.log_output(
+        logger, logging.ERROR, fds[1], job_id="1"
+    )
+
+    fds[0].close()
+    os.write(pipes[1][1], "Hello\n".encode("utf-8"))
+    semaphore.acquire()
+    logger.log.assert_called_with(logging.ERROR, "[%s]%s", "1", "Hello")
diff --git a/zephyr/zmake/tests/test_packers.py b/zephyr/zmake/tests/test_packers.py
new file mode 100644
index 0000000000..441e5db7e6
--- /dev/null
+++ b/zephyr/zmake/tests/test_packers.py
@@ -0,0 +1,73 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Tests for zmake packers."""
+
+import pathlib
+import tempfile
+
+import hypothesis  # pylint:disable=import-error
+import hypothesis.strategies as st  # pylint:disable=import-error
+import pytest  # pylint:disable=import-error
+import zmake.output_packers as packers
+
+
+# Strategies for use with hypothesis
+absolute_path = st.from_regex(regex=r"\A/[\w/]*\Z")
+
+
+class FakePacker(packers.BasePacker):
+    """Fake packer to expose protected methods."""
+
+    def __init__(self, max_size):
+        super().__init__(project=None)
+        self.max_size = max_size
+
+    def check_packed_file_size(self, file, dir_map):
+        """Expose the _check_packed_file_size method."""
+        return self._check_packed_file_size(file, dir_map)
+
+    def _get_max_image_bytes(self, dir_map):
+        return self.max_size
+
+    def pack_firmware(self, work_dir, jobclient, dir_map, version_string=""):
+        del version_string
+        assert False
+
+
+@hypothesis.given(st.binary(min_size=101, max_size=200))
+@hypothesis.settings(deadline=60000)
+def test_file_size_unbounded(data):
+    """Test with file size unbounded."""
+    packer = FakePacker(None)
+    with tempfile.TemporaryDirectory() as temp_dir_name:
+        file = pathlib.Path(temp_dir_name) / "zephyr.elf"
+        with open(file, "wb") as outfile:
+            outfile.write(data)
+        assert packer.check_packed_file_size(file=file, dir_map={}) == file
+
+
+@hypothesis.given(st.binary(min_size=5, max_size=100))
+@hypothesis.settings(deadline=60000)
+def test_file_size_in_bounds(data):
+    """Test with file size limited."""
+    packer = FakePacker(100)
+    with tempfile.TemporaryDirectory() as temp_dir_name:
+        file = pathlib.Path(temp_dir_name) / "ec.bin"
+        with open(file, "wb") as outfile:
+            outfile.write(data)
+        assert packer.check_packed_file_size(file=file, dir_map={}) == file
+
+
+@hypothesis.given(st.binary(min_size=101, max_size=200))
+@hypothesis.settings(deadline=60000)
+def test_file_size_out_of_bounds(data):
+    """Test with file size limited, and file exceeds limit."""
+    packer = FakePacker(100)
+    with tempfile.TemporaryDirectory() as temp_dir_name:
+        file = pathlib.Path(temp_dir_name) / "ec.bin"
+        with open(file, "wb") as outfile:
+            outfile.write(data)
+        with pytest.raises(RuntimeError):
+            packer.check_packed_file_size(file=file, dir_map={})
diff --git a/zephyr/zmake/tests/test_project.py b/zephyr/zmake/tests/test_project.py
new file mode 100644
index 0000000000..6acde6a48b
--- /dev/null
+++ b/zephyr/zmake/tests/test_project.py
@@ -0,0 +1,272 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Test zmake project module."""
+
+import pathlib
+import string
+import tempfile
+
+import hypothesis  # pylint:disable=import-error
+import hypothesis.strategies as st  # pylint:disable=import-error
+import pytest  # pylint:disable=import-error
+import zmake.modules
+import zmake.output_packers
+import zmake.project
+
+
+board_names = st.text(alphabet=set(string.ascii_lowercase) | {"_"}, min_size=1)
+sets_of_board_names = st.lists(st.lists(board_names, unique=True))
+
+
+@hypothesis.given(sets_of_board_names)
+@hypothesis.settings(deadline=None)
+def test_find_dts_overlays(modules):
+    """Test the functionality of find_dts_overlays with multiple
+    modules, each with sets of board names."""
+
+    # Recursive function to wind up all the temporary directories and
+    # call the actual test.
+    def setup_modules_and_dispatch(modules, test_fn, module_list=()):
+        if modules:
+            boards = modules[0]
+            with tempfile.TemporaryDirectory() as modpath:
+                modpath = pathlib.Path(modpath)
+                for board in boards:
+                    dts_path = zmake.project.module_dts_overlay_name(
+                        modpath, board
+                    )
+                    dts_path.parent.mkdir(parents=True, exist_ok=True)
+                    dts_path.touch()
+                setup_modules_and_dispatch(
+                    modules[1:], test_fn, module_list=module_list + (modpath,)
+                )
+        else:
+            test_fn(module_list)
+
+    # The actual test case, once temp modules have been setup.
+    def testcase(module_paths):
+        # Maps board_name→overlay_files
+        board_file_mapping = {}
+        for modpath, board_list in zip(module_paths, modules):
+            for board in board_list:
+                file_name = zmake.project.module_dts_overlay_name(
+                    modpath, board
+                )
+                files = board_file_mapping.get(board, set())
+                board_file_mapping[board] = files | {file_name}
+
+        for board, expected_dts_files in board_file_mapping.items():
+            project = zmake.project.Project(
+                zmake.project.ProjectConfig(
+                    project_name=board,
+                    zephyr_board=board,
+                    output_packer=zmake.output_packers.ElfPacker,
+                    supported_toolchains=["llvm"],
+                    project_dir=pathlib.Path("/fakebuild"),
+                )
+            )
+            config = project.find_dts_overlays(dict(enumerate(module_paths)))
+            actual_dts_files = set(
+                config.cmake_defs.get("DTC_OVERLAY_FILE", "").split(";")
+            )
+
+            assert actual_dts_files == set(map(str, expected_dts_files))
+
+    setup_modules_and_dispatch(modules, testcase)
+
+
+module_lists = st.lists(
+    st.one_of(*map(st.just, zmake.modules.known_modules)), unique=True
+)
+
+
+@hypothesis.given(module_lists)
+@hypothesis.settings(deadline=None)
+def test_prune_modules(modules):
+    """Test the Project.prune_modules method in the usual case (all
+    modules available)."""
+    module_paths = {
+        name: pathlib.Path("/fake/module/path", name)
+        for name in zmake.modules.known_modules
+    }
+
+    project = zmake.project.Project(
+        zmake.project.ProjectConfig(
+            project_name="prunetest",
+            zephyr_board="native_posix",
+            output_packer=zmake.output_packers.ElfPacker,
+            supported_toolchains=["coreboot-sdk"],
+            project_dir=pathlib.Path("/fake"),
+            modules=modules,
+        ),
+    )
+    assert set(project.prune_modules(module_paths)) == set(modules)
+
+
+def test_prune_modules_unavailable():
+    """The Project.prune_modules method should raise a KeyError when
+    not all modules are available."""
+
+    # Missing 'cmsis'
+    module_paths = {
+        "hal_stm32": pathlib.Path("/mod/halstm"),
+    }
+
+    project = zmake.project.Project(
+        zmake.project.ProjectConfig(
+            project_name="prunetest",
+            zephyr_board="native_posix",
+            output_packer=zmake.output_packers.ElfPacker,
+            supported_toolchains=["coreboot-sdk"],
+            project_dir=pathlib.Path("/fake"),
+            modules=["hal_stm32", "cmsis"],
+        ),
+    )
+    with pytest.raises(KeyError):
+        project.prune_modules(module_paths)
+
+
+def test_find_projects_empty(tmp_path):
+    """Test the find_projects method when there are no projects."""
+    projects = list(zmake.project.find_projects(tmp_path))
+    assert len(projects) == 0
+
+
+CONFIG_FILE_1 = """
+register_raw_project(project_name="one", zephyr_board="one")
+register_host_project(project_name="two")
+register_npcx_project(project_name="three", zephyr_board="three")
+register_binman_project(
+    project_name="four",
+    zephyr_board="four",
+    inherited_from="baseboard"
+)
+"""
+
+CONFIG_FILE_2 = """
+register_raw_project(
+    project_name="five",
+    zephyr_board="foo",
+    dts_overlays=[here / "gpio.dts"],
+    inherited_from=["root", "myboard"],
+)
+"""
+
+
+def test_find_projects(tmp_path):
+    """Test the find_projects method when there are projects."""
+    cf1_dir = tmp_path / "cf1"
+    cf1_dir.mkdir()
+    (cf1_dir / "BUILD.py").write_text(CONFIG_FILE_1)
+
+    cf2_bb_dir = tmp_path / "cf2_bb"
+    cf2_bb_dir.mkdir()
+    cf2_dir = cf2_bb_dir / "cf2"
+    cf2_dir.mkdir()
+    (cf2_dir / "BUILD.py").write_text(CONFIG_FILE_2)
+
+    projects = zmake.project.find_projects(tmp_path)
+    assert len(projects) == 5
+    assert projects["one"].config.project_dir == cf1_dir
+
+    assert projects["two"].config.project_dir == cf1_dir
+    assert projects["two"].config.zephyr_board == "native_posix"
+
+    assert projects["three"].config.project_dir == cf1_dir
+    assert projects["three"].config.zephyr_board == "three"
+
+    assert projects["four"].config.project_dir == cf1_dir
+    assert projects["four"].config.zephyr_board == "four"
+    assert projects["four"].config.full_name == "baseboard.four"
+
+    assert projects["five"].config.project_dir == cf2_dir
+    assert projects["five"].config.zephyr_board == "foo"
+    assert projects["five"].config.full_name == "root.myboard.five"
+
+
+def test_find_projects_name_conflict(tmp_path):
+    """When two projects define the same name, that should be an error."""
+    cf1_dir = tmp_path / "cf1"
+    cf1_dir.mkdir()
+    (cf1_dir / "BUILD.py").write_text(CONFIG_FILE_2)
+
+    cf2_dir = tmp_path / "cf2"
+    cf2_dir.mkdir()
+    (cf2_dir / "BUILD.py").write_text(CONFIG_FILE_2)
+
+    with pytest.raises(KeyError):
+        zmake.project.find_projects(tmp_path)
+
+
+def test_register_variant(tmp_path):
+    """Test registering a variant."""
+    (tmp_path / "BUILD.py").write_text(
+        """
+some = register_raw_project(
+    project_name="some",
+    zephyr_board="foo",
+    dts_overlays=[here / "gpio.dts"],
+)
+
+some_variant = some.variant(project_name="some-variant", zephyr_board="bar")
+another = some_variant.variant(
+    project_name="another",
+    dts_overlays=[here / "another.dts"],
+)
+    """
+    )
+    projects = zmake.project.find_projects(tmp_path)
+    assert projects["some"].config.zephyr_board == "foo"
+    assert projects["some-variant"].config.zephyr_board == "bar"
+    assert projects["another"].config.zephyr_board == "bar"
+    assert projects["another"].config.dts_overlays == [
+        tmp_path / "gpio.dts",
+        tmp_path / "another.dts",
+    ]
+    assert projects["some"].config.full_name == "some"
+    assert projects["some-variant"].config.full_name == "some.some-variant"
+    assert projects["another"].config.full_name == "some.some-variant.another"
+
+
+@pytest.mark.parametrize(
+    ("actual_files", "config_files", "expected_files"),
+    [
+        (["prj_link.conf"], [], []),
+        (["prj.conf"], [], ["prj.conf"]),
+        (
+            ["prj.conf", "cfg.conf"],
+            ["prj.conf", "cfg.conf"],
+            ["prj.conf", "cfg.conf"],
+        ),
+        (
+            ["prj.conf", "prj_samus.conf", "prj_link.conf"],
+            ["prj_link.conf"],
+            ["prj.conf", "prj_link.conf"],
+        ),
+    ],
+)
+def test_kconfig_files(tmp_path, actual_files, config_files, expected_files):
+    """Test for setting kconfig_files property."""
+    for name in actual_files:
+        (tmp_path / name).write_text("")
+
+    project = zmake.project.Project(
+        zmake.project.ProjectConfig(
+            project_name="samus",
+            zephyr_board="lm4",
+            output_packer=zmake.output_packers.RawBinPacker,
+            supported_toolchains=["coreboot-sdk"],
+            project_dir=tmp_path,
+            kconfig_files=[tmp_path / name for name in config_files],
+        ),
+    )
+
+    builds = list(project.iter_builds())
+    assert len(builds) == 1
+
+    _, config = builds[0]
+    assert sorted(f.name for f in config.kconfig_files) == sorted(
+        expected_files
+    )
diff --git a/zephyr/zmake/tests/test_reexec.py b/zephyr/zmake/tests/test_reexec.py
new file mode 100644
index 0000000000..63aa76cb70
--- /dev/null
+++ b/zephyr/zmake/tests/test_reexec.py
@@ -0,0 +1,61 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+"""Test the zmake re-exec functionality."""
+
+import os
+import sys
+import unittest.mock as mock
+
+import pytest  # pylint:disable=import-error
+import zmake.__main__ as main
+
+
+@pytest.fixture(name="fake_env")
+def fixture_fake_env(monkeypatch):
+    """A test fixture that creates fake env variables."""
+    environ = {}
+    monkeypatch.setattr(os, "environ", environ)
+    return environ
+
+
+@pytest.fixture(name="mock_execve")
+def fixture_mock_execve():
+    """A test fixture that mocks the os.execve function."""
+    with mock.patch("os.execve", autospec=True) as mocked_function:
+        yield mocked_function
+
+
+@pytest.mark.usefixtures("fake_env")
+def test_out_of_chroot(mock_execve):
+    """When CROS_WORKON_SRCROOT is not set, we should not re-exec."""
+    main.maybe_reexec(["--help"])
+    mock_execve.assert_not_called()
+
+
+def test_pythonpath_set(fake_env, mock_execve):
+    """With PYTHONPATH set, we should not re-exec."""
+    fake_env["CROS_WORKON_SRCROOT"] = "/mnt/host/source"
+    fake_env["PYTHONPATH"] = "/foo/bar/baz"
+    main.maybe_reexec(["--help"])
+    mock_execve.assert_not_called()
+
+
+def test_zmake_does_not_exist(fake_env, mock_execve):
+    """When zmake is not at src/platform/ec/zephyr/zmake, don't re-exec."""
+    fake_env["CROS_WORKON_SRCROOT"] = "/this/does/not/exist"
+    main.maybe_reexec(["--help"])
+    mock_execve.assert_not_called()
+
+
+def test_zmake_reexec(fake_env, mock_execve, tmp_path, fake_checkout):
+    """Nothing else applies?  The re-exec should happen, when in a checkout."""
+    fake_env["CROS_WORKON_SRCROOT"] = tmp_path
+    main.maybe_reexec(["--help"])
+    new_env = dict(fake_env)
+    new_env["PYTHONPATH"] = str(fake_checkout.resolve())
+    mock_execve.assert_called_once_with(
+        sys.executable,
+        [sys.executable, "-m", "zmake", "--help"],
+        new_env,
+    )
diff --git a/zephyr/zmake/tests/test_toolchains.py b/zephyr/zmake/tests/test_toolchains.py
new file mode 100644
index 0000000000..2a71fd0d60
--- /dev/null
+++ b/zephyr/zmake/tests/test_toolchains.py
@@ -0,0 +1,204 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Tests for toolchains.py."""
+
+import os
+import pathlib
+
+import pytest  # pylint:disable=import-error
+import zmake.output_packers
+import zmake.project as project
+import zmake.toolchains as toolchains
+
+
+# pylint:disable=redefined-outer-name,unused-argument
+
+
+@pytest.fixture
+def mockfs(monkeypatch, tmp_path: pathlib.Path):
+    """Setup a fake fs root for pathlib objects at tmp_path/mockfs."""
+    mockfs_dir = tmp_path / "mockfs"
+    mockfs_dir.mkdir()
+
+    def map_path(path):
+        try:
+            rel_path = path.relative_to(mockfs_dir)
+            fake = mockfs_dir.joinpath(rel_path)
+            return fake
+        except ValueError:
+            fake = mockfs_dir.joinpath(*path.parts[1:])
+            return fake
+
+    real_stat = pathlib.Path.stat
+
+    def stat(path):
+        return real_stat(map_path(path))
+
+    monkeypatch.setattr(pathlib.Path, "stat", stat)
+    return mockfs_dir
+
+
+@pytest.fixture
+def coreboot_sdk_exists(mockfs):
+    """Provide a mock coreboot-sdk."""
+    coreboot_sdk_dir = mockfs / "opt" / "coreboot-sdk"
+    coreboot_sdk_dir.mkdir(parents=True)
+
+
+@pytest.fixture
+def llvm_exists(mockfs):
+    """Provide a mock llvm."""
+    llvm_file = mockfs / "usr" / "bin" / "x86_64-pc-linux-gnu-clang"
+    llvm_file.parent.mkdir(parents=True)
+    llvm_file.write_text("")
+
+
+@pytest.fixture
+def host_toolchain_exists(mockfs, monkeypatch):
+    """Provide a mock host toolchain."""
+    monkeypatch.setattr(os, "environ", {})
+
+    gcc_file = mockfs / "usr" / "bin" / "gcc"
+    gcc_file.parent.mkdir(parents=True)
+    gcc_file.write_text("")
+
+
+@pytest.fixture
+def zephyr_exists(mockfs):
+    """Provide a mock zephyr sdk."""
+    zephyr_sdk_version_file = mockfs / "opt" / "zephyr-sdk" / "sdk_version"
+    zephyr_sdk_version_file.parent.mkdir(parents=True)
+    zephyr_sdk_version_file.write_text("")
+
+
+@pytest.fixture
+def no_environ(monkeypatch):
+    """Clear all environment variables."""
+    environ = {}
+    monkeypatch.setattr(os, "environ", environ)
+
+
+@pytest.fixture
+def fake_project(tmp_path):
+    """Create a project that can be used in all the tests."""
+    return project.Project(
+        project.ProjectConfig(
+            project_name="foo",
+            zephyr_board="foo",
+            supported_toolchains=[
+                "coreboot-sdk",
+                "host",
+                "llvm",
+                "zephyr",
+            ],
+            output_packer=zmake.output_packers.RawBinPacker,
+            project_dir=tmp_path,
+        ),
+    )
+
+
+module_paths = {
+    "ec": pathlib.Path("/mnt/host/source/src/platform/ec"),
+}
+
+
+def test_coreboot_sdk(fake_project: project.Project, coreboot_sdk_exists):
+    """Test that the corebook sdk can be found."""
+    chain = fake_project.get_toolchain(module_paths)
+    assert isinstance(chain, toolchains.CorebootSdkToolchain)
+
+    config = chain.get_build_config()
+    assert config.cmake_defs == {
+        "ZEPHYR_TOOLCHAIN_VARIANT": "coreboot-sdk",
+        "TOOLCHAIN_ROOT": "/mnt/host/source/src/platform/ec/zephyr",
+        "COREBOOT_SDK_ROOT": "/opt/coreboot-sdk",
+    }
+
+
+def test_llvm(fake_project, llvm_exists):
+    """Test that llvm can be found."""
+    chain = fake_project.get_toolchain(module_paths)
+    assert isinstance(chain, toolchains.LlvmToolchain)
+
+    config = chain.get_build_config()
+    assert config.cmake_defs == {
+        "ZEPHYR_TOOLCHAIN_VARIANT": "llvm",
+        "TOOLCHAIN_ROOT": "/mnt/host/source/src/platform/ec/zephyr",
+    }
+
+
+def test_zephyr(fake_project: project.Project, zephyr_exists, no_environ):
+    """Test that the zephyr sdk can be found in a standard location."""
+    chain = fake_project.get_toolchain(module_paths)
+    assert isinstance(chain, toolchains.ZephyrToolchain)
+
+    config = chain.get_build_config()
+    assert config.cmake_defs == {
+        "ZEPHYR_TOOLCHAIN_VARIANT": "zephyr",
+        "ZEPHYR_SDK_INSTALL_DIR": str(pathlib.Path("/opt/zephyr-sdk")),
+    }
+
+
+def test_zephyr_from_env(mockfs, monkeypatch, fake_project):
+    """Test that the zephyr sdk can be found from env variable."""
+    zephyr_sdk_path = mockfs / "zsdk"
+    zephyr_sdk_path.mkdir()
+
+    environ = {"ZEPHYR_SDK_INSTALL_DIR": str(zephyr_sdk_path)}
+    monkeypatch.setattr(os, "environ", environ)
+
+    chain = fake_project.get_toolchain(module_paths)
+    assert isinstance(chain, toolchains.ZephyrToolchain)
+
+    config = chain.get_build_config()
+    assert config.cmake_defs == {
+        "ZEPHYR_TOOLCHAIN_VARIANT": "zephyr",
+        "ZEPHYR_SDK_INSTALL_DIR": str(zephyr_sdk_path),
+    }
+
+
+def test_host_toolchain(fake_project, host_toolchain_exists):
+    """Test that the host toolchain can be found."""
+    chain = fake_project.get_toolchain(module_paths)
+    assert isinstance(chain, toolchains.HostToolchain)
+
+    config = chain.get_build_config()
+    assert config.cmake_defs == {
+        "ZEPHYR_TOOLCHAIN_VARIANT": "host",
+    }
+
+
+def test_toolchain_override(mockfs, fake_project):
+    """Test that the toolchain can be overridden."""
+    chain = fake_project.get_toolchain(module_paths, override="foo")
+    config = chain.get_build_config()
+    assert isinstance(chain, toolchains.GenericToolchain)
+    assert config.cmake_defs == {"ZEPHYR_TOOLCHAIN_VARIANT": "foo"}
+
+
+def test_generic_toolchain():
+    """Verify that GenericToolchain.probe() returns False."""
+    chain = toolchains.GenericToolchain("name")
+    assert not chain.probe()
+
+
+def test_no_toolchains(fake_project: project.Project, mockfs, no_environ):
+    """Check for error when there are no toolchains."""
+    with pytest.raises(
+        OSError, match=r"No supported toolchains could be found on your system"
+    ):
+        fake_project.get_toolchain(module_paths)
+
+
+def test_override_without_sdk(
+    fake_project: project.Project, mockfs, no_environ
+):
+    """Check for error override is set to zephyr, but it can't be found."""
+    chain = fake_project.get_toolchain(module_paths, override="zephyr")
+
+    with pytest.raises(
+        RuntimeError, match=r"No installed Zephyr SDK was found"
+    ):
+        chain.get_build_config()
diff --git a/zephyr/zmake/tests/test_util.py b/zephyr/zmake/tests/test_util.py
new file mode 100644
index 0000000000..70378073d4
--- /dev/null
+++ b/zephyr/zmake/tests/test_util.py
@@ -0,0 +1,60 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Tests for zmake util."""
+
+import pathlib
+import tempfile
+
+import hypothesis  # pylint:disable=import-error
+import hypothesis.strategies as st  # pylint:disable=import-error
+import pytest  # pylint:disable=import-error
+import zmake.util as util
+
+
+# Strategies for use with hypothesis
+version_integers = st.integers(min_value=0)
+version_tuples = st.tuples(version_integers, version_integers, version_integers)
+
+
+@hypothesis.given(version_tuples)
+@hypothesis.settings(deadline=60000)
+def test_read_zephyr_version(version_tuple):
+    """Test reading the zephyr version."""
+    with tempfile.TemporaryDirectory() as zephyr_base:
+        with open(pathlib.Path(zephyr_base) / "VERSION", "w") as file:
+            for name, value in zip(
+                ("VERSION_MAJOR", "VERSION_MINOR", "PATCHLEVEL"), version_tuple
+            ):
+                file.write("{} = {}\n".format(name, value))
+
+        assert util.read_zephyr_version(zephyr_base) == version_tuple
+
+
+@hypothesis.given(st.integers())
+@hypothesis.settings(deadline=60000)
+def test_read_kconfig_autoconf_value(value):
+    """Test reading the kconfig autoconf."""
+    with tempfile.TemporaryDirectory() as temp_dir:
+        path = pathlib.Path(temp_dir)
+        with open(path / "autoconf.h", "w") as file:
+            file.write("#define TEST {}".format(value))
+        read_value = util.read_kconfig_autoconf_value(path, "TEST")
+        assert int(read_value) == value
+
+
+@pytest.mark.parametrize(
+    ["input_str", "expected_result"],
+    [
+        ("", '""'),
+        ("TROGDOR ABC-123", '"TROGDOR ABC-123"'),
+        ("hello world", '"hello world"'),
+        ("hello\nworld", r'"hello\nworld"'),
+        ('hello"world', r'"hello\"world"'),
+        ("hello\\world", '"hello\\\\world"'),
+    ],
+)
+def test_c_str(input_str, expected_result):
+    """Test the util.c_str function."""
+    assert util.c_str(input_str) == expected_result
diff --git a/zephyr/zmake/tests/test_version.py b/zephyr/zmake/tests/test_version.py
new file mode 100644
index 0000000000..8881522e4b
--- /dev/null
+++ b/zephyr/zmake/tests/test_version.py
@@ -0,0 +1,206 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Tests for zmake version code."""
+
+import datetime
+import subprocess
+import unittest.mock as mock
+
+import pytest  # pylint: disable=import-error
+import zmake.output_packers
+import zmake.project
+import zmake.version as version
+
+
+# pylint:disable=redefined-outer-name,unused-argument
+
+
+def _git_init(repo):
+    """Create a new git repository."""
+    repo.mkdir()
+    subprocess.run(
+        ["git", "-c", "init.defaultBranch=main", "-C", repo, "init"], check=True
+    )
+
+
+def _git_add(repo, path, contents="example!\n"):
+    """Write contents and stage a file."""
+    path.write_text(contents)
+    subprocess.run(["git", "-C", repo, "add", path], check=True)
+
+
+def _git_commit(repo, message="message!"):
+    env = {
+        "GIT_AUTHOR_NAME": "Alyssa P. Hacker",
+        "GIT_AUTHOR_EMAIL": "aphacker@example.org",
+        "GIT_AUTHOR_DATE": "Thu, 07 Apr 2005 22:13:13 +0200",
+        "GIT_COMMITTER_NAME": "Ben Bitdiddle",
+        "GIT_COMMITTER_EMAIL": "bitdiddle@example.org",
+        "GIT_COMMITTER_DATE": "Tue, 30 Aug 2005 10:50:30 -0700",
+    }
+    subprocess.run(
+        ["git", "-C", repo, "commit", "-m", message], check=True, env=env
+    )
+
+
+def _setup_example_repos(tmp_path):
+    """Setup temporary project, zephyr base, and module repos.
+
+    Args:
+        tmp_path: Directory to set up files in.
+
+    Returns:
+        A 3-tuple of project, zephyr_base, modules_dict.
+    """
+    project_path = tmp_path / "prj"
+    project_path.mkdir()
+
+    project = zmake.project.Project(
+        zmake.project.ProjectConfig(
+            project_name="prj",
+            zephyr_board="foo",
+            output_packer=zmake.output_packers.RawBinPacker,
+            supported_toolchains=["coreboot-sdk"],
+            project_dir=project_path,
+        ),
+    )
+    # Has one commit.
+    zephyr_base = tmp_path / "zephyr_base"
+    _git_init(zephyr_base)
+    _git_add(
+        zephyr_base,
+        zephyr_base / "VERSION",
+        "VERSION_MAJOR=2\nVERSION_MINOR=6\nPATCHLEVEL=99\n",
+    )
+    _git_commit(zephyr_base, "Added version file")
+
+    # Has one commit.
+    mod1 = tmp_path / "mod1"
+    _git_init(mod1)
+    _git_add(mod1, mod1 / "file1")
+    _git_commit(mod1)
+
+    # Has two commits.
+    mod2 = tmp_path / "ec"
+    _git_init(mod2)
+    _git_add(mod2, mod2 / "file2")
+    _git_commit(mod2)
+    _git_add(mod2, mod2 / "file3")
+    _git_commit(mod2)
+
+    return project, zephyr_base, {"mod1": mod1, "ec": mod2}
+
+
+def test_version_string(tmp_path):
+    """Test a that version string is as expected."""
+    project, zephyr_base, modules = _setup_example_repos(tmp_path)
+    assert (
+        version.get_version_string(
+            project.config.project_name, zephyr_base, modules
+        )
+        == "prj_v2.6.4-ec:b5991f,os:377d26,mod1:02fd7a"
+    )
+
+
+def test_version_string_static(tmp_path):
+    """Test a that version string with no git hashes."""
+    project, zephyr_base, modules = _setup_example_repos(tmp_path)
+    assert (
+        version.get_version_string(
+            project.config.project_name, zephyr_base, modules, static=True
+        )
+        == "prj_v2.6.0-STATIC"
+    )
+
+
+@pytest.fixture
+def fake_user_hostname():
+    """Fixture to provide a fake user and hostname."""
+    with mock.patch("getpass.getuser", return_value="toukmond", autospec=True):
+        with mock.patch("platform.node", return_value="pokey", autospec=True):
+            yield
+
+
+@pytest.fixture
+def fake_date():
+    """Fixture to provide a fake date."""
+    fixed_date = datetime.datetime(2021, 6, 28, 3, 18, 53)
+    with mock.patch("datetime.datetime") as mock_datetime:
+        mock_datetime.now.return_value = fixed_date
+        yield
+
+
+HEADER_VERSION_STR = "trogdor_v2.6.1004-cmsis:0dead0,hal_stm32:0beef0,os:ad00da"
+EXPECTED_HEADER = (
+    "/* This file is automatically generated by zmake_tests */\n"
+    '#define VERSION "trogdor_v2.6.1004-cmsis:0dead0,hal_stm32:0beef0,os:ad00da"\n'
+    '#define CROS_EC_VERSION32 "trogdor_v2.6.1004-cmsis:0dead0,"\n'
+    '#define BUILDER "toukmond@pokey"\n'
+    '#define DATE "2021-06-28 03:18:53"\n'
+    "#define CROS_FWID32 CROS_FWID_MISSING_STR\n"
+)
+HEADER_VERSION_STR_STATIC = "trogdor_v2.6.0-STATIC"
+EXPECTED_HEADER_STATIC = (
+    "/* This file is automatically generated by zmake_tests */\n"
+    '#define VERSION "trogdor_v2.6.0-STATIC"\n'
+    '#define CROS_EC_VERSION32 "trogdor_v2.6.0-STATIC"\n'
+    '#define BUILDER "reproducible@build"\n'
+    '#define DATE "STATIC_VERSION_DATE"\n'
+    "#define CROS_FWID32 CROS_FWID_MISSING_STR\n"
+)
+
+
+def test_header_gen(fake_user_hostname, fake_date, tmp_path):
+    """Test generating the version header."""
+    # Test the simple case (static=False, no existing header).
+    output_file = tmp_path / "ec_version.h"
+    version.write_version_header(HEADER_VERSION_STR, output_file, "zmake_tests")
+    assert output_file.read_text() == EXPECTED_HEADER
+
+
+def test_header_gen_reproducible_build(tmp_path):
+    """Test that reproducible builds produce the right header."""
+    # With static=True this time.
+    output_file = tmp_path / "ec_version.h"
+    version.write_version_header(
+        HEADER_VERSION_STR_STATIC, output_file, "zmake_tests", static=True
+    )
+    assert output_file.read_text() == EXPECTED_HEADER_STATIC
+
+
+def test_header_gen_exists_not_changed(fake_user_hostname, fake_date, tmp_path):
+    """Test that the version file is not changed."""
+    # Test we don't overwrite if no changes needed.
+    output_file = tmp_path / "ec_version.h"
+
+    # First time, write and record mtime.
+    version.write_version_header(HEADER_VERSION_STR, output_file, "zmake_tests")
+    expected_mtime = output_file.stat().st_mtime
+
+    # Do another write (contents should be unchanged).
+    version.write_version_header(HEADER_VERSION_STR, output_file, "zmake_tests")
+
+    # Assert we didn't write again.
+    assert output_file.stat().st_mtime == expected_mtime
+
+
+def test_header_gen_exists_needs_changes(
+    fake_user_hostname, fake_date, tmp_path
+):
+    """Test that the version file is changed, when needed."""
+    # Test we overwrite when it exists already and changes are needed.
+    output_file = tmp_path / "ec_version.h"
+
+    # First time, write and save contents.
+    version.write_version_header(HEADER_VERSION_STR, output_file, "zmake_tests")
+    original_contents = output_file.read_text()
+
+    # Do another write (contents should be changed).
+    version.write_version_header(
+        HEADER_VERSION_STR_STATIC, output_file, "zmake_tests", static=True
+    )
+
+    # Assert we overwrote.
+    assert output_file.read_text() != original_contents
diff --git a/zephyr/zmake/tests/test_zmake.py b/zephyr/zmake/tests/test_zmake.py
new file mode 100644
index 0000000000..54ecad076a
--- /dev/null
+++ b/zephyr/zmake/tests/test_zmake.py
@@ -0,0 +1,316 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Do a run of 'zmake build' and check the output"""
+
+import logging
+import os
+import pathlib
+import re
+import unittest.mock
+
+import pytest  # pylint:disable=import-error
+from testfixtures import LogCapture  # pylint:disable=import-error
+import zmake.build_config
+import zmake.jobserver
+import zmake.multiproc as multiproc
+import zmake.output_packers
+import zmake.project
+import zmake.toolchains
+
+
+OUR_PATH = os.path.dirname(os.path.realpath(__file__))
+
+
+class FakeProject:
+    """A fake project which requests two builds and does no packing"""
+
+    def __init__(self):
+        self.packer = unittest.mock.Mock()
+        self.packer.pack_firmware = unittest.mock.Mock(return_value=[])
+
+        self.config = zmake.project.ProjectConfig(
+            project_name="fakeproject",
+            zephyr_board="fakeboard",
+            supported_toolchains=["llvm"],
+            output_packer=zmake.output_packers.ElfPacker,
+            project_dir=pathlib.Path("FakeProjectDir"),
+        )
+
+    @staticmethod
+    def iter_builds():
+        """Yield the two builds that zmake normally does"""
+        yield "ro", zmake.build_config.BuildConfig()
+        yield "rw", zmake.build_config.BuildConfig()
+
+    @staticmethod
+    def prune_modules(_):
+        """Fake implementation of prune_modules."""
+        return {}  # pathlib.Path('path')]
+
+    @staticmethod
+    def find_dts_overlays(_):
+        """Fake implementation of find_dts_overlays."""
+        return zmake.build_config.BuildConfig()
+
+    @staticmethod
+    def get_toolchain(module_paths, override=None):
+        """Fake implementation of get_toolchain."""
+        return zmake.toolchains.GenericToolchain(
+            override or "foo",
+            modules=module_paths,
+        )
+
+
+class FakeJobserver(zmake.jobserver.GNUMakeJobServer):
+    """A fake jobserver which just runs 'cat' on the provided files"""
+
+    def __init__(self, fnames):
+        """Start up a jobserver with two jobs
+
+        Args:
+            fnames: Dict of regexp to filename. If the regexp matches the
+            command, then the filename will be returned as the output.
+        """
+        super().__init__(jobs=2)
+        self.fnames = fnames
+
+    def get_job(self):
+        """Fake implementation of get_job(), which returns a real JobHandle()"""
+        return zmake.jobserver.JobHandle(unittest.mock.Mock())
+
+    # pylint: disable=arguments-differ
+    def popen(self, cmd, *args, **kwargs):
+        """Ignores the provided command and just runs 'cat' instead"""
+        for pattern, filename in self.fnames.items():
+            # Convert to a list of strings
+            cmd = [
+                isinstance(c, pathlib.PosixPath) and c.as_posix() or c
+                for c in cmd
+            ]
+            if pattern.match(" ".join(cmd)):
+                new_cmd = ["cat", filename]
+                break
+        else:
+            raise Exception('No pattern matched "%s"' % " ".join(cmd))
+        kwargs["env"] = {}
+        return super().popen(new_cmd, *args, **kwargs)
+
+    def env(self):
+        """Runs test commands with an empty environment for simpler logs."""
+        return {}
+
+
+def get_test_filepath(suffix):
+    """Get the filepath for a particular test file
+
+    Args:
+        suffix: Suffix of the file to read, e.g. 'ro' or 'ro_INFO'
+
+    Returns:
+        Full path to the test file
+    """
+    return os.path.join(OUR_PATH, "files", "sample_{}.txt".format(suffix))
+
+
+def do_test_with_log_level(zmake_factory_from_dir, log_level, fnames=None):
+    """Test filtering using a particular log level
+
+    Args:
+        log_level: Level to use
+        use_configure: Run the 'configure' subcommand instead of 'build'
+        fnames: Dict of regexp to filename. If the regexp matches the
+            command, then the filename will be returned as the output.
+            (None to use default ro/rw output)
+
+    Returns:
+        - List of log strings obtained from the run
+    """
+    if fnames is None:
+        fnames = {
+            re.compile(r".*build-ro"): get_test_filepath("ro"),
+            re.compile(r".*build-rw"): get_test_filepath("rw"),
+        }
+
+    zmk = zmake_factory_from_dir(jobserver=FakeJobserver(fnames))
+    with LogCapture(level=log_level) as cap:
+        with unittest.mock.patch(
+            "zmake.version.get_version_string", return_value="123"
+        ), unittest.mock.patch.object(
+            zmake.project,
+            "find_projects",
+            return_value={"fakeproject": FakeProject()},
+        ), unittest.mock.patch(
+            "zmake.version.write_version_header", autospec=True
+        ):
+            zmk.build(
+                ["fakeproject"],
+                clobber=True,
+            )
+        multiproc.LogWriter.wait_for_log_end()
+
+    recs = [rec.getMessage() for rec in cap.records]
+    return recs
+
+
+class TestFilters:
+    """Test filtering of stdout and stderr"""
+
+    @staticmethod
+    def test_filter_normal(zmake_factory_from_dir):
+        """Test filtering of a normal build (with no errors)"""
+        recs = do_test_with_log_level(zmake_factory_from_dir, logging.ERROR)
+        assert not recs
+
+    @staticmethod
+    def test_filter_info(zmake_factory_from_dir, tmp_path, monkeypatch):
+        """Test what appears on the INFO level"""
+        monkeypatch.setattr(
+            os, "environ", {"TOOL_PATH_ninja": "/usr/bin/ninja"}
+        )
+        recs = do_test_with_log_level(zmake_factory_from_dir, logging.INFO)
+        # TODO: Remove sets and figure out how to check the lines are in the
+        # right order.
+        expected = {
+            "Configuring fakeproject:rw.",
+            "Configuring fakeproject:ro.",
+            "Building fakeproject in {}/ec/build/zephyr/fakeproject.".format(
+                tmp_path
+            ),
+            "Building fakeproject:ro: /usr/bin/ninja -C {}-ro".format(
+                tmp_path / "ec/build/zephyr/fakeproject/build"
+            ),
+            "Building fakeproject:rw: /usr/bin/ninja -C {}-rw".format(
+                tmp_path / "ec/build/zephyr/fakeproject/build"
+            ),
+        }
+        for suffix in ["ro", "rw"]:
+            with open(get_test_filepath("%s_INFO" % suffix)) as file:
+                for line in file:
+                    expected.add(
+                        "[fakeproject:{}]{}".format(suffix, line.strip())
+                    )
+        # This produces an easy-to-read diff if there is a difference
+        assert expected == set(recs)
+
+    @staticmethod
+    def test_filter_debug(zmake_factory_from_dir, tmp_path, monkeypatch):
+        """Test what appears on the DEBUG level"""
+        monkeypatch.setattr(
+            os, "environ", {"TOOL_PATH_ninja": "/usr/bin/ninja"}
+        )
+        recs = do_test_with_log_level(zmake_factory_from_dir, logging.DEBUG)
+        # TODO: Remove sets and figure out how to check the lines are in the
+        # right order.
+        expected = {
+            "Configuring fakeproject:rw.",
+            "Configuring fakeproject:ro.",
+            "Building fakeproject in {}/ec/build/zephyr/fakeproject.".format(
+                tmp_path
+            ),
+            "Building fakeproject:ro: /usr/bin/ninja -C {}-ro".format(
+                tmp_path / "ec/build/zephyr/fakeproject/build"
+            ),
+            "Building fakeproject:rw: /usr/bin/ninja -C {}-rw".format(
+                tmp_path / "ec/build/zephyr/fakeproject/build"
+            ),
+            "Running `env -i cat {}/files/sample_ro.txt`".format(OUR_PATH),
+            "Running `env -i cat {}/files/sample_rw.txt`".format(OUR_PATH),
+        }
+        for suffix in ["ro", "rw"]:
+            with open(get_test_filepath(suffix)) as file:
+                for line in file:
+                    expected.add(
+                        "[fakeproject:{}]{}".format(suffix, line.strip())
+                    )
+        # This produces an easy-to-read diff if there is a difference
+        assert expected == set(recs)
+
+    @staticmethod
+    def test_filter_devicetree_error(zmake_factory_from_dir):
+        """Test that devicetree errors appear"""
+        recs = do_test_with_log_level(
+            zmake_factory_from_dir,
+            logging.ERROR,
+            {re.compile(r".*"): get_test_filepath("err")},
+        )
+
+        dt_errs = [rec for rec in recs if "adc" in rec]
+        assert (
+            "devicetree error: 'adc' is marked as required" in list(dt_errs)[0]
+        )
+
+
+@pytest.mark.parametrize(
+    ["project_names", "fmt", "search_dir", "expected_output"],
+    [
+        (
+            ["link", "samus"],
+            "{config.project_name}\n",
+            None,
+            "link\nsamus\n",
+        ),
+        (
+            ["link", "samus"],
+            "{config.project_name}\n",
+            pathlib.Path("/foo/bar"),
+            "link\nsamus\n",
+        ),
+        (
+            [],
+            "{config.project_name}\n",
+            None,
+            "",
+        ),
+        (
+            ["link"],
+            "",
+            None,
+            "",
+        ),
+        (
+            ["link"],
+            "{config.zephyr_board}\n",
+            None,
+            "some_board\n",
+        ),
+        (
+            ["link"],
+            "{config.project_name} {config.zephyr_board}\n",
+            None,
+            "link some_board\n",
+        ),
+    ],
+)
+def test_list_projects(
+    project_names,
+    fmt,
+    search_dir,
+    expected_output,
+    capsys,
+    zmake_factory_from_dir,
+):
+    """Test listing projects with default directory."""
+    fake_projects = {
+        name: zmake.project.Project(
+            zmake.project.ProjectConfig(
+                project_name=name,
+                zephyr_board="some_board",
+                supported_toolchains=["coreboot-sdk"],
+                output_packer=zmake.output_packers.RawBinPacker,
+            )
+        )
+        for name in project_names
+    }
+
+    zmk = zmake_factory_from_dir(projects_dir=search_dir)
+    with unittest.mock.patch(
+        "zmake.project.find_projects",
+        autospec=True,
+        return_value=fake_projects,
+    ):
+        zmk.list_projects(fmt=fmt)
+
+    captured = capsys.readouterr()
+    assert captured.out == expected_output
diff --git a/zephyr/zmake/zephyr_build_tools/__init__.py b/zephyr/zmake/zephyr_build_tools/__init__.py
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/zephyr/zmake/zephyr_build_tools/generate_ec_version.py b/zephyr/zmake/zephyr_build_tools/generate_ec_version.py
new file mode 100755
index 0000000000..7d3a9450ee
--- /dev/null
+++ b/zephyr/zmake/zephyr_build_tools/generate_ec_version.py
@@ -0,0 +1,169 @@
+#!/usr/bin/env python3
+
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Code to generate the ec_version.h file."""
+
+import argparse
+import logging
+import os.path
+import pathlib
+import sys
+
+import zmake.version
+
+
+def convert_module_list_to_dict(modules: list) -> dict:
+    """Convert a list of string paths to modules in to a dict of module
+    names to paths."""
+
+    if not modules:
+        return {}
+
+    dict_out = {}
+    for mod in modules:
+        if not mod.is_dir():
+            raise FileNotFoundError(f"Module '{mod}' not found")
+
+        dict_out[mod.name] = mod
+
+    return dict_out
+
+
+def main():
+    """CLI entry point for generating the ec_version.h header"""
+    logging.basicConfig(level=logging.INFO, stream=sys.stderr)
+
+    parser = argparse.ArgumentParser()
+
+    parser.add_argument("header_path", help="Path to write ec_version.h to")
+    parser.add_argument(
+        "-s",
+        "--static",
+        action="store_true",
+        help="If set, generate a header which does not include information "
+        "like the username, hostname, or date, allowing the build to be"
+        "reproducible.",
+    )
+    parser.add_argument(
+        "--base",
+        default=os.environ.get("ZEPHYR_BASE"),
+        help="Path to Zephyr base directory. Uses ZEPHYR_BASE env var if unset.",
+    )
+    parser.add_argument(
+        "-m",
+        "--module",
+        action="append",
+        help="Specify modules paths to include in version hash. Uses "
+        "ZEPHYR_MODULES env var if unset",
+    )
+    parser.add_argument(
+        "-n", "--name", required=True, type=str, help="Project name"
+    )
+
+    args = parser.parse_args()
+
+    if args.base is None:
+        logging.error(
+            "No Zephyr base is defined. Pass --base or set env var ZEPHYR_BASE"
+        )
+        return 1
+
+    logging.info("Zephyr Base: %s", args.base)
+
+    if args.static:
+        logging.info("Using a static version string")
+
+    # Make a dict of modules from the list. Modules can be added one at a time
+    # by repeating the -m flag, or once as a semicolon-separated list. In the
+    # later case, we need to expand the modules list.
+
+    if args.module is None:
+        # No modules specified on command line. Default to environment variable.
+        env_modules = os.environ.get("ZEPHYR_MODULES")
+        args.module = env_modules.split(";") if env_modules else []
+        logging.info(
+            "No modules passed via CLI. Getting list from ZEPHYR_MODULES"
+        )
+
+    elif len(args.module) == 1:
+        # In case of a single -m flag, treat value as a semicolon-delimited
+        # list.
+        args.module = args.module[0].split(";")
+
+    try:
+        module_dict = convert_module_list_to_dict(
+            map(pathlib.Path, args.module)
+        )
+    except FileNotFoundError as err:
+        logging.error("Cannot find module: %s", str(err))
+        return 1
+
+    logging.info("Including modules: [%s]", ", ".join(args.module))
+
+    # Generate the version string that gets inserted in to the header. Will get
+    # commit IDs from Git
+    ver = zmake.version.get_version_string(
+        args.name, args.base, module_dict, args.static
+    )
+    logging.info("Version string: %s", ver)
+
+    # Now write the actual header file or put version string in stdout
+    if args.header_path == "-":
+        print(ver)
+    else:
+        output_path = pathlib.Path(args.header_path)
+        output_path.parent.mkdir(parents=True, exist_ok=True)
+
+        logging.info("Writing header to %s", args.header_path)
+        zmake.version.write_version_header(
+            ver, output_path, sys.argv[0], args.static
+        )
+
+    return 0
+
+
+def maybe_reexec():
+    """Re-exec using the zmake package from the EC source tree, as
+    opposed to the system's copy of zmake. This is useful for
+    development when engineers need to make changes to zmake. This
+    script relies on the zmake package for version string generation
+    logic.
+
+    Returns:
+        None, if the re-exec did not happen, or never returns if the
+        re-exec did happen.
+    """
+    # We only re-exec if we are inside of a chroot (since if installed
+    # standalone using pip, there's already an "editable install"
+    # feature for that in pip.)
+    env = dict(os.environ)
+    srcroot = env.get("CROS_WORKON_SRCROOT")
+    if not srcroot:
+        return
+
+    # If for some reason we decide to move zmake in the future, then
+    # we don't want to use the re-exec logic.
+    zmake_path = (
+        pathlib.Path(srcroot) / "src" / "platform" / "ec" / "zephyr" / "zmake"
+    ).resolve()
+    if not zmake_path.is_dir():
+        return
+
+    # If PYTHONPATH is set, it is either because we just did a
+    # re-exec, or because the user wants to run a specific copy of
+    # zmake.  In either case, we don't want to re-exec.
+    if "PYTHONPATH" in env:
+        return
+
+    # Set PYTHONPATH so that we run zmake from source.
+    env["PYTHONPATH"] = str(zmake_path)
+
+    os.execve(sys.argv[0], sys.argv, env)
+
+
+if __name__ == "__main__":
+    maybe_reexec()
+    sys.exit(main())
diff --git a/zephyr/zmake/zmake/__init__.py b/zephyr/zmake/zmake/__init__.py
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/zephyr/zmake/zmake/__main__.py b/zephyr/zmake/zmake/__main__.py
new file mode 100644
index 0000000000..b34922271f
--- /dev/null
+++ b/zephyr/zmake/zmake/__main__.py
@@ -0,0 +1,408 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""The entry point into zmake."""
+import argparse
+import inspect
+import logging
+import os
+import pathlib
+import sys
+
+import zmake.jobserver as jobserver
+import zmake.multiproc as multiproc
+import zmake.zmake as zm
+
+
+def maybe_reexec(argv):
+    """Re-exec zmake from the EC source tree, if possible and desired.
+
+    Zmake installs into the users' chroot, which makes it convenient
+    to execute, but can sometimes become tedious when zmake changes
+    land and users haven't upgraded their chroots yet.
+
+    We can partially subvert this problem by re-execing zmake from the
+    source if it's available.  This won't make it so developers never
+    need to upgrade their chroots (e.g., a toolchain upgrade could
+    require chroot upgrades), but at least makes it slightly more
+    convenient for an average repo sync.
+
+    Args:
+        argv: The argument list passed to the main function, not
+            including the executable path.
+
+    Returns:
+        None, if the re-exec did not happen, or never returns if the
+        re-exec did happen.
+    """
+    # We only re-exec if we are inside of a chroot (since if installed
+    # standalone using pip, there's already an "editable install"
+    # feature for that in pip.)
+    env = dict(os.environ)
+    srcroot = env.get("CROS_WORKON_SRCROOT")
+    if not srcroot:
+        return
+
+    # If for some reason we decide to move zmake in the future, then
+    # we don't want to use the re-exec logic.
+    zmake_path = (
+        pathlib.Path(srcroot) / "src" / "platform" / "ec" / "zephyr" / "zmake"
+    ).resolve()
+    if not zmake_path.is_dir():
+        return
+
+    # If PYTHONPATH is set, it is either because we just did a
+    # re-exec, or because the user wants to run a specific copy of
+    # zmake.  In either case, we don't want to re-exec.
+    if "PYTHONPATH" in env:
+        return
+
+    # Set PYTHONPATH so that we run zmake from source.
+    env["PYTHONPATH"] = str(zmake_path)
+
+    os.execve(sys.executable, [sys.executable, "-m", "zmake", *argv], env)
+
+
+def call_with_namespace(func, namespace, **kwds):
+    """Call a function with arguments applied from a Namespace.
+
+    Args:
+        func: The callable to call.
+        namespace: The namespace to apply to the callable.
+
+    Returns:
+        The result of calling the callable.
+    """
+    sig = inspect.signature(func)
+    names = [p.name for p in sig.parameters.values()]
+    for name, value in vars(namespace).items():
+        pyname = name.replace("-", "_")
+        if pyname in names:
+            kwds[pyname] = value
+    return func(**kwds)
+
+
+# Dictionary used to map log level strings to their corresponding int values.
+log_level_map = {
+    "DEBUG": logging.DEBUG,
+    "INFO": logging.INFO,
+    "WARNING": logging.WARNING,
+    "ERROR": logging.ERROR,
+    "CRITICAL": logging.CRITICAL,
+}
+
+
+def get_argparser():
+    """Get the argument parser.
+
+    Returns:
+        A two tuple, the argument parser, and the subcommand action.
+    """
+    parser = argparse.ArgumentParser(
+        prog="zmake",
+        description="Chromium OS's meta-build tool for Zephyr",
+    )
+    parser.add_argument(
+        "--checkout", type=pathlib.Path, help="Path to ChromiumOS checkout"
+    )
+    parser.add_argument(
+        "-j",
+        "--jobs",
+        type=int,
+        help="Degree of multiprogramming to use",
+    )
+    parser.add_argument(
+        "--goma",
+        action="store_true",
+        dest="goma",
+        help="Enable hyperspeed compilation with Goma! (Googlers only)",
+    )
+
+    log_level_group = parser.add_mutually_exclusive_group()
+    log_level_group.add_argument(
+        "-l",
+        "--log-level",
+        choices=log_level_map.values(),
+        metavar=f"{{{','.join(log_level_map)}}}",
+        type=lambda x: log_level_map[x],
+        default=logging.INFO,
+        help="Set the logging level (default=INFO)",
+    )
+    log_level_group.add_argument(
+        "-D",
+        "--debug",
+        dest="log_level",
+        action="store_const",
+        const=logging.DEBUG,
+        help="Alias for --log-level=DEBUG",
+    )
+
+    parser.add_argument(
+        "-L",
+        "--no-log-label",
+        action="store_false",
+        help="Turn off logging labels",
+        dest="log_label",
+        default=None,
+    )
+    parser.add_argument(
+        "--log-label",
+        action="store_true",
+        help="Turn on logging labels",
+        dest="log_label",
+        default=None,
+    )
+    parser.add_argument(
+        "--modules-dir",
+        type=pathlib.Path,
+        help="The path to a directory containing all modules "
+        "needed.  If unspecified, zmake will assume you have "
+        "a Chrome OS checkout and try locating them in the "
+        "checkout.",
+    )
+    parser.add_argument(
+        "--projects-dir",
+        type=pathlib.Path,
+        help="Base directory to search for BUILD.py files.",
+    )
+    parser.add_argument(
+        "--zephyr-base", type=pathlib.Path, help="Path to Zephyr OS repository"
+    )
+
+    sub = parser.add_subparsers(
+        dest="subcommand",
+        metavar="subcommand",
+        help="Subcommand to run",
+    )
+    sub.required = True
+
+    configure = sub.add_parser(
+        "configure",
+        help="Set up a build directory to be built later by the build subcommand",
+    )
+    add_common_configure_args(configure)
+    add_common_build_args(configure)
+
+    build = sub.add_parser(
+        "build",
+        help="Configure and build projects",
+    )
+    add_common_configure_args(build)
+    add_common_build_args(build)
+
+    compare_builds = sub.add_parser(
+        "compare-builds", help="Compare output binaries from two commits"
+    )
+    compare_builds.add_argument(
+        "--ref1",
+        default="HEAD",
+        help="1st git reference (commit, branch, etc), default=HEAD",
+    )
+    compare_builds.add_argument(
+        "--ref2",
+        default="HEAD~",
+        help="2nd git reference (commit, branch, etc), default=HEAD~",
+    )
+    compare_builds.add_argument(
+        "-k",
+        "--keep-temps",
+        action="store_true",
+        help="Keep temporary build directories on exit",
+    )
+    compare_builds.add_argument(
+        "-n",
+        "--compare-configs",
+        action="store_true",
+        help="Compare configs of build outputs",
+    )
+    compare_builds.add_argument(
+        "-b",
+        "--compare-binaries-disable",
+        action="store_true",
+        help="Don't compare binaries of build outputs",
+    )
+    compare_builds.add_argument(
+        "-d",
+        "--compare-devicetrees",
+        action="store_true",
+        help="Compare devicetrees of build outputs",
+    )
+    add_common_build_args(compare_builds)
+
+    list_projects = sub.add_parser(
+        "list-projects",
+        help="List projects known to zmake.",
+    )
+    list_projects.add_argument(
+        "--format",
+        default="{config.project_name}\n",
+        dest="fmt",
+        help=(
+            "Output format to print projects (str.format(config=project.config) is "
+            "called on this for each project)."
+        ),
+    )
+
+    generate_readme = sub.add_parser(
+        "generate-readme",
+        help="Update the auto-generated markdown documentation",
+    )
+    generate_readme.add_argument(
+        "-o",
+        "--output-file",
+        default=pathlib.Path(__file__).parent.parent / "README.md",
+        help="File to write to.  It will only be written if changed.",
+    )
+    generate_readme.add_argument(
+        "--diff",
+        action="store_true",
+        help=(
+            "If specified, diff the README with the expected contents instead of "
+            "writing out."
+        ),
+    )
+
+    return parser, sub
+
+
+def add_common_build_args(sub_parser: argparse.ArgumentParser):
+    """Adds common arguments used by build-like subcommands"""
+    sub_parser.add_argument(
+        "-t", "--toolchain", help="Name of toolchain to use"
+    )
+    sub_parser.add_argument(
+        "--extra-cflags",
+        help="Additional CFLAGS to use for target builds",
+    )
+    group = sub_parser.add_mutually_exclusive_group(required=True)
+    group.add_argument(
+        "-a",
+        "--all",
+        action="store_true",
+        dest="all_projects",
+        help="Select all projects",
+    )
+    group.add_argument(
+        "project_names",
+        nargs="*",
+        metavar="project_name",
+        help="Name(s) of the project(s) to build",
+        default=[],
+    )
+
+
+def add_common_configure_args(sub_parser: argparse.ArgumentParser):
+    """Adds common arguments used by configure-like subcommands."""
+    sub_parser.add_argument(
+        "--bringup",
+        action="store_true",
+        dest="bringup",
+        help="Enable bringup debugging features",
+    )
+    sub_parser.add_argument(
+        "--clobber",
+        action="store_true",
+        dest="clobber",
+        help="Delete existing build directories, even if configuration is unchanged",
+    )
+    sub_parser.add_argument(
+        "--static",
+        action="store_true",
+        dest="static_version",
+        help="Generate static version information for reproducible builds",
+    )
+    sub_parser.add_argument(
+        "--save-temps",
+        action="store_true",
+        dest="save_temps",
+        help="Save the temporary files containing preprocessor output",
+    )
+    sub_parser.add_argument(
+        "--allow-warnings",
+        action="store_true",
+        default=False,
+        help="Do not treat warnings as errors",
+    )
+    sub_parser.add_argument(
+        "-B",
+        "--build-dir",
+        type=pathlib.Path,
+        help="Root build directory, project files will be in "
+        "${build_dir}/${project_name}",
+    )
+    sub_parser.add_argument(
+        "-c",
+        "--coverage",
+        action="store_true",
+        dest="coverage",
+        help="Enable CONFIG_COVERAGE Kconfig.",
+    )
+    sub_parser.add_argument(
+        "--delete-intermediates",
+        action="store_true",
+        dest="delete_intermediates",
+        help="Delete intermediate files to save disk space",
+    )
+    sub_parser.add_argument(
+        "-D",
+        "--cmake-define",
+        action="append",
+        dest="cmake_defs",
+    )
+
+
+def main(argv=None):
+    """The main function.
+
+    Args:
+        argv: Optionally, the command-line to parse, not including argv[0].
+
+    Returns:
+        Zero upon success, or non-zero upon failure.
+    """
+    if argv is None:
+        argv = sys.argv[1:]
+
+    maybe_reexec(argv)
+
+    parser, _ = get_argparser()
+    opts = parser.parse_args(argv)
+
+    # Default logging
+    log_label = False
+
+    if opts.log_label is not None:
+        log_label = opts.log_label
+    if log_label:
+        log_format = "%(levelname)s: %(message)s"
+    else:
+        log_format = "%(message)s"
+        multiproc.LOG_JOB_NAMES = False
+
+    logging.basicConfig(format=log_format, level=opts.log_level)
+    # Create the jobserver client BEFORE any pipes get opened in LogWriter
+    jobserver_client = jobserver.GNUMakeJobClient.from_environ(jobs=opts.jobs)
+    multiproc.LogWriter.reset()
+
+    zmake = call_with_namespace(zm.Zmake, opts, jobserver=jobserver_client)
+    try:
+        subcommand_method = getattr(zmake, opts.subcommand.replace("-", "_"))
+        result = call_with_namespace(subcommand_method, opts)
+        wait_rv = zmake.executor.wait()
+        return result or wait_rv
+    finally:
+        multiproc.LogWriter.wait_for_log_end()
+        for file, failed_projects in zmake.cmp_failed_projects.items():
+            if failed_projects:
+                logging.error(
+                    "Failed projects by diff in %s: %s",
+                    file,
+                    ", ".join(failed_projects),
+                )
+        if zmake.failed_projects:
+            logging.error("All failed projects: %s", zmake.failed_projects)
+
+
+if __name__ == "__main__":
+    sys.exit(main())
diff --git a/zephyr/zmake/zmake/build_config.py b/zephyr/zmake/zmake/build_config.py
new file mode 100644
index 0000000000..1b2b6efff1
--- /dev/null
+++ b/zephyr/zmake/zmake/build_config.py
@@ -0,0 +1,178 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+"""Encapsulation of a build configuration."""
+
+import hashlib
+import json
+import pathlib
+
+import zmake.jobserver
+import zmake.util as util
+
+
+class BuildConfig:
+    """A container for build configurations.
+
+    A build config is a tuple of cmake variables, kconfig definitions,
+    and kconfig files.
+    """
+
+    def __init__(
+        self,
+        cmake_defs=None,
+        kconfig_defs=None,
+        kconfig_files=None,
+    ):
+        self.cmake_defs = dict(cmake_defs or {})
+        self.kconfig_defs = dict(kconfig_defs or {})
+
+        def _remove_duplicate_paths(files):
+            # Remove multiple of the same kconfig file in a row.
+            result = []
+            for path in files:
+                if not result or path != result[-1]:
+                    result.append(path)
+            return result
+
+        self.kconfig_files = _remove_duplicate_paths(kconfig_files or [])
+
+    @classmethod
+    def from_args(cls, args):
+        """Convert CLI arguments (from -D) to a build config.
+
+        Args:
+            args: The command line arguments to parse.
+
+        Returns:
+            A BuildConfig.
+        """
+        defs_dict = {}
+        for arg in args:
+            key, sep, value = arg.partition("=")
+            if not sep:
+                value = "1"
+            defs_dict[key] = value
+        return cls(cmake_defs=defs_dict)
+
+    def popen_cmake(
+        self,
+        jobclient: zmake.jobserver.JobClient,
+        project_dir,
+        build_dir,
+        kconfig_path=None,
+        **kwargs
+    ):
+        """Run Cmake with this config using a jobclient.
+
+        Args:
+            jobclient: A JobClient instance.
+            project_dir: The project directory.
+            build_dir: Directory to use for Cmake build.
+            kconfig_path: The path to write out Kconfig definitions.
+            kwargs: forwarded to popen.
+        """
+        kconfig_files = list(self.kconfig_files)
+        if kconfig_path:
+            util.write_kconfig_file(kconfig_path, self.kconfig_defs)
+            kconfig_files.append(kconfig_path)
+        elif self.kconfig_defs:
+            raise ValueError(
+                "Cannot start Cmake on a config with Kconfig items without a "
+                "kconfig_path"
+            )
+
+        if kconfig_files:
+            base_config = BuildConfig(cmake_defs=self.cmake_defs)
+            conf_file_config = BuildConfig(
+                cmake_defs={
+                    "CONF_FILE": ";".join(
+                        str(p.resolve()) for p in kconfig_files
+                    )
+                }
+            )
+            return (base_config | conf_file_config).popen_cmake(
+                jobclient, project_dir, build_dir, **kwargs
+            )
+
+        return jobclient.popen(
+            [
+                util.get_tool_path("cmake"),
+                "-S",
+                project_dir,
+                "-B",
+                build_dir,
+                "-GNinja",
+                *("-D{}={}".format(*pair) for pair in self.cmake_defs.items()),
+            ],
+            **kwargs
+        )
+
+    def __or__(self, other):
+        """Combine two BuildConfig instances."""
+        if not isinstance(other, BuildConfig):
+            raise TypeError(
+                "Unsupported operation | for {} and {}".format(
+                    type(self), type(other)
+                )
+            )
+
+        return BuildConfig(
+            cmake_defs=dict(**self.cmake_defs, **other.cmake_defs),
+            kconfig_defs=dict(**self.kconfig_defs, **other.kconfig_defs),
+            kconfig_files=[*self.kconfig_files, *other.kconfig_files],
+        )
+
+    def __repr__(self):
+        return "BuildConfig({})".format(
+            ", ".join(
+                "{}={!r}".format(name, getattr(self, name))
+                for name in [
+                    "cmake_defs",
+                    "kconfig_defs",
+                    "kconfig_files",
+                ]
+                if getattr(self, name)
+            )
+        )
+
+    def _get_paths_for_hashing(self):
+        # Zephyr's CMake system won't detect that CMake needs to be
+        # re-run to regenerate Kconfig headers or merge DTS files.
+        # We can work around this in Zmake by hashing the file
+        # contents of known problematic paths, and forcing a clobber
+        # when any hash is changed.
+        #
+        # TODO(b/215560602): Delete this code when Zephyr's Cmake
+        # system is fixed.
+        paths_for_hashing = set()
+
+        for path in self.cmake_defs.get("DTC_OVERLAY_FILE", "").split(";"):
+            if not path:
+                continue
+            paths_for_hashing.add(pathlib.Path(path).resolve())
+
+        for path in self.kconfig_files:
+            paths_for_hashing.add(path.resolve())
+
+        return paths_for_hashing
+
+    def _get_file_hashes(self):
+        result = {}
+
+        for path in self._get_paths_for_hashing():
+            result[str(path)] = hashlib.sha224(path.read_bytes()).hexdigest()
+
+        return result
+
+    def as_json(self):
+        """Provide a stable JSON representation of the build config."""
+        return json.dumps(
+            {
+                "cmake_defs": self.cmake_defs,
+                "kconfig_defs": self.kconfig_defs,
+                "kconfig_files": [str(p.resolve()) for p in self.kconfig_files],
+                "file_hashes": self._get_file_hashes(),
+            },
+            sort_keys=True,
+        )
diff --git a/zephyr/zmake/zmake/compare_builds.py b/zephyr/zmake/zmake/compare_builds.py
new file mode 100644
index 0000000000..80b7b59b12
--- /dev/null
+++ b/zephyr/zmake/zmake/compare_builds.py
@@ -0,0 +1,336 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Module to compare Zephyr EC builds"""
+
+import dataclasses
+import logging
+import os
+import pathlib
+import shlex
+import subprocess
+import sys
+
+from zmake.output_packers import packer_registry
+
+
+def get_git_hash(ref):
+    """Get the full git commit hash for a git reference
+
+    Args:
+        ref: Git reference (e.g. HEAD, m/main, sha256)
+
+    Returns:
+        A string, with the full hash of the git reference
+    """
+
+    try:
+        result = subprocess.run(
+            ["git", "rev-parse", ref],
+            check=True,
+            stdout=subprocess.PIPE,
+            stderr=subprocess.DEVNULL,
+            encoding="utf-8",
+        )
+    except subprocess.CalledProcessError:
+        logging.error("Failed to determine hash for git reference %s", ref)
+        sys.exit(1)
+    else:
+        full_reference = result.stdout.strip()
+
+    return full_reference
+
+
+def git_do_checkout(module_name, work_dir, git_source, dst_dir, git_ref):
+    """Clone a repository and perform a checkout.
+
+    Args:
+        module_name: The module name to checkout.
+        work_dir: Root directory for the checktout.
+        git_source: Path to the repository for the module.
+        dst_dir: Destination directory for the checkout, relative to the work_dir.
+        git_ref: Git reference to checkout.
+    """
+    cmd = [
+        "git",
+        "clone",
+        "--quiet",
+        "--no-checkout",
+        "file://" + str(git_source),
+        str(dst_dir),
+    ]
+
+    try:
+        subprocess.run(
+            cmd,
+            cwd=work_dir,
+            check=True,
+            stdout=subprocess.DEVNULL,
+            stderr=subprocess.DEVNULL,
+        )
+    except subprocess.CalledProcessError:
+        logging.error("Clone failed for %s: %s", module_name, shlex.join(cmd))
+        sys.exit(1)
+
+    cmd = ["git", "-C", dst_dir, "checkout", "--quiet", git_ref]
+    try:
+        subprocess.run(
+            cmd,
+            cwd=work_dir,
+            check=True,
+            stdout=subprocess.DEVNULL,
+            stderr=subprocess.DEVNULL,
+        )
+    except subprocess.CalledProcessError:
+        logging.error(
+            "Checkout of %s failed for %s: %s",
+            git_ref,
+            module_name,
+            shlex.join(cmd),
+        )
+        sys.exit(1)
+
+
+def create_bin_from_elf(elf_input, bin_output):
+    """Create a plain binary from an ELF executable
+
+    Args:
+        elf_input - ELF output file, created by zmake
+        bin_output - Output binary filename. Created by this function.
+    """
+
+    cmd = ["objcopy", "-O", "binary"]
+    # Some native-posix builds include a GNU build ID, which is guaranteed
+    # unique from build to build. Remove this section during conversion
+    # binary format.
+    cmd.extend(["-R", ".note.gnu.build-id"])
+    cmd.extend([elf_input, bin_output])
+    try:
+        subprocess.run(
+            cmd,
+            check=True,
+            stdout=subprocess.DEVNULL,
+            stderr=subprocess.DEVNULL,
+        )
+    except subprocess.CalledProcessError:
+        logging.error("Failed to create binary: %s", bin_output)
+        sys.exit(1)
+
+
+def _compare_non_test_projects(projects, cmp_method, *args):
+    failed_projects = []
+    for project in projects:
+        if not cmp_method(project, *args):
+            failed_projects.append(project.config.project_name)
+
+    return failed_projects
+
+
+@dataclasses.dataclass
+class CheckoutConfig:
+    """All the information needed to build the EC at a specific checkout."""
+
+    temp_dir: str
+    ref: str
+    full_ref: str = dataclasses.field(default_factory=str)
+    work_dir: pathlib.Path = dataclasses.field(default_factory=pathlib.Path)
+    zephyr_dir: pathlib.Path = dataclasses.field(default_factory=pathlib.Path)
+    modules_dir: pathlib.Path = dataclasses.field(default_factory=pathlib.Path)
+    projects_dir: pathlib.Path = dataclasses.field(default_factory=pathlib.Path)
+
+    def __post_init__(self):
+        self.full_ref = get_git_hash(self.ref)
+        self.work_dir = pathlib.Path(self.temp_dir) / self.full_ref
+        self.zephyr_dir = self.work_dir / "zephyr-base"
+        self.modules_dir = self.work_dir / "modules"
+        self.projects_dir = self.modules_dir / "ec" / "zephyr"
+
+        os.mkdir(self.work_dir)
+
+
+class CompareBuilds:
+    """Information required to build Zephyr EC projects at a specific EC git
+        commit reference.
+
+    Args:
+        temp_dir: Temporary directory where all sources will be checked out
+            and built.
+        ref1: 1st git reference for the EC repository.  May be a partial hash,
+            local branch name, or remote branch name.
+        ref2: 2nd git reference for the EC repository.
+
+    Attributes:
+        checkouts: list of CheckoutConfig objects containing information
+            about the code checkout at each EC git reference.
+    """
+
+    def __init__(self, temp_dir, ref1, ref2):
+        self.checkouts = []
+        self.checkouts.append(CheckoutConfig(temp_dir, ref1))
+        self.checkouts.append(CheckoutConfig(temp_dir, ref2))
+
+    def do_checkouts(self, zephyr_base, module_paths):
+        """Checkout all EC sources at a specific commit.
+
+        Args:
+            zephyr_base: The location of the zephyr sources.
+            module_paths: The location of the module sources.
+        """
+
+        for checkout in self.checkouts:
+            for module_name, git_source in module_paths.items():
+                dst_dir = checkout.modules_dir / module_name
+                git_ref = checkout.full_ref if module_name == "ec" else "HEAD"
+                git_do_checkout(
+                    module_name=module_name,
+                    work_dir=checkout.work_dir,
+                    git_source=git_source,
+                    dst_dir=dst_dir,
+                    git_ref=git_ref,
+                )
+
+            git_do_checkout(
+                module_name="zephyr",
+                work_dir=checkout.work_dir,
+                git_source=zephyr_base,
+                dst_dir="zephyr-base",
+                git_ref="HEAD",
+            )
+
+    def _compare_binaries(self, project):
+        output_path = (
+            pathlib.Path("ec")
+            / "build"
+            / "zephyr"
+            / pathlib.Path(project.config.project_name)
+            / "output"
+        )
+
+        output_dir1 = self.checkouts[0].modules_dir / output_path
+        output_dir2 = self.checkouts[1].modules_dir / output_path
+
+        bin_output1 = output_dir1 / "ec.bin"
+        bin_output2 = output_dir2 / "ec.bin"
+
+        # ELF executables don't compare due to meta data.  Convert to a binary
+        # for the comparison
+        if project.config.output_packer == packer_registry["elf"]:
+            create_bin_from_elf(
+                elf_input=output_dir1 / "zephyr.elf", bin_output=bin_output1
+            )
+            create_bin_from_elf(
+                elf_input=output_dir2 / "zephyr.elf", bin_output=bin_output2
+            )
+
+        bin1_path = pathlib.Path(bin_output1)
+        bin2_path = pathlib.Path(bin_output2)
+        if not os.path.isfile(bin1_path) or not os.path.isfile(bin2_path):
+            logging.error(
+                "Zephyr EC binary not found for project %s",
+                project.config.project_name,
+            )
+            return False
+
+        try:
+            subprocess.run(
+                ["cmp", bin_output1, bin_output2],
+                check=True,
+                stdout=subprocess.DEVNULL,
+                stderr=subprocess.DEVNULL,
+            )
+        except subprocess.CalledProcessError:
+            return False
+        return True
+
+    def check_binaries(self, projects):
+        """Compare Zephyr EC binaries for two different source trees
+
+        Args:
+            projects: List of projects to compare the output binaries.
+
+        Returns:
+            A list of projects that failed to compare.  An empty list indicates that
+            all projects compared successfully.
+        """
+
+        failed_projects = _compare_non_test_projects(
+            projects, self._compare_binaries
+        )
+        return failed_projects
+
+    def _compare_build_files(self, project, build_mode, file):
+        build_path = (
+            pathlib.Path("ec")
+            / "build"
+            / "zephyr"
+            / pathlib.Path(project.config.project_name)
+            / f"build-{build_mode}"
+            / "zephyr"
+        )
+
+        build_dir1 = self.checkouts[0].modules_dir / build_path
+        build_dir2 = self.checkouts[1].modules_dir / build_path
+
+        file1 = build_dir1 / file
+        file2 = build_dir2 / file
+
+        try:
+            data1 = ""
+            data2 = ""
+            with open(file1) as fp1, open(file2) as fp2:
+                data1 = fp1.read()
+                data2 = fp2.read()
+            data1 = data1.replace(self.checkouts[0].full_ref, "")
+            data2 = data2.replace(self.checkouts[1].full_ref, "")
+            return data1 == data2
+        except FileNotFoundError as err:
+            logging.error(
+                "Zephyr build-%s %s file not found for project %s: %s",
+                build_mode,
+                file,
+                project.config.project_name,
+                err,
+            )
+        return False
+
+    def _check_build_files(self, project, file):
+        return self._compare_build_files(
+            project, "ro", file
+        ) and self._compare_build_files(project, "rw", file)
+
+    def check_configs(self, projects):
+        """Compare Zephyr EC Config files for two different source trees
+
+        Args:
+            projects: List of projects to compare the .config files.
+
+        Returns:
+            A list of projects that failed to compare.  An empty list indicates that
+            all projects compared successfully.
+        """
+
+        failed_projects = _compare_non_test_projects(
+            projects,
+            self._check_build_files,
+            ".config",
+        )
+        return failed_projects
+
+    def check_devicetrees(self, projects):
+        """Compare Zephyr EC devicetree files for two different source trees
+
+        Args:
+            projects: List of projects to compare the zephyr.dts files.
+
+        Returns:
+            A list of projects that failed to compare.  An empty list indicates that
+            all projects compared successfully.
+        """
+
+        failed_projects = _compare_non_test_projects(
+            projects,
+            self._check_build_files,
+            "zephyr.dts",
+        )
+        return failed_projects
diff --git a/zephyr/zmake/zmake/configlib.py b/zephyr/zmake/zmake/configlib.py
new file mode 100644
index 0000000000..327e159d6a
--- /dev/null
+++ b/zephyr/zmake/zmake/configlib.py
@@ -0,0 +1,58 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""This module defines helpers accessible to all BUILD.py files."""
+
+import zmake.output_packers
+
+
+def _register_project(**kwargs):
+    kwargs.setdefault(
+        "project_dir", here  # noqa: F821 pylint: disable=undefined-variable
+    )
+    return register_project(
+        **kwargs
+    )  # noqa: F821 pylint: disable=undefined-variable
+
+
+def register_host_project(**kwargs):
+    """Register a project that runs on a posix host."""
+    kwargs.setdefault("zephyr_board", "native_posix")
+    kwargs.setdefault("supported_toolchains", ["llvm", "host"])
+    kwargs.setdefault("output_packer", zmake.output_packers.ElfPacker)
+    return _register_project(**kwargs)
+
+
+def register_raw_project(**kwargs):
+    """Register a project that uses RawBinPacker."""
+    kwargs.setdefault("supported_toolchains", ["coreboot-sdk", "zephyr"])
+    kwargs.setdefault("output_packer", zmake.output_packers.RawBinPacker)
+    return _register_project(**kwargs)
+
+
+def register_binman_project(**kwargs):
+    """Register a project that uses BinmanPacker."""
+    kwargs.setdefault("output_packer", zmake.output_packers.BinmanPacker)
+    return register_raw_project(**kwargs)
+
+
+def register_npcx_project(**kwargs):
+    """Register a project that uses NpcxPacker."""
+    kwargs.setdefault("output_packer", zmake.output_packers.NpcxPacker)
+    kwargs.setdefault("modules", ["ec", "cmsis"])
+    return register_binman_project(**kwargs)
+
+
+def register_mchp_project(**kwargs):
+    kwargs.setdefault("output_packer", zmake.output_packers.MchpPacker)
+    kwargs.setdefault("modules", ["ec", "cmsis"])
+    return register_binman_project(**kwargs)
+
+
+def register_ish_project(**kwargs):
+    """Register a project that uses IshBinPacker."""
+    kwargs.setdefault("supported_toolchains", ["coreboot-sdk", "zephyr"])
+    kwargs.setdefault("output_packer", zmake.output_packers.IshBinPacker)
+    kwargs.setdefault("modules", ["ec", "ish", "cmsis", "hal_intel"])
+    return _register_project(**kwargs)
diff --git a/zephyr/zmake/zmake/generate_readme.py b/zephyr/zmake/zmake/generate_readme.py
new file mode 100644
index 0000000000..f309a104ba
--- /dev/null
+++ b/zephyr/zmake/zmake/generate_readme.py
@@ -0,0 +1,126 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Code for auto-generating README.md."""
+
+import argparse
+import io
+
+
+class MarkdownHelpFormatter(argparse.HelpFormatter):
+    """Callbacks to format help output as Markdown."""
+
+    def __init__(self, prog):
+        self._prog = prog
+        self._section_title = None
+        self._section_contents = []
+        self._paragraphs = []
+        super().__init__(prog=prog)
+
+    def add_text(self, text):
+        if text and text is not argparse.SUPPRESS:
+            lst = self._paragraphs
+            if self._section_title:
+                lst = self._section_contents
+            lst.append(text)
+
+    def start_section(self, heading):
+        self._section_title = heading.title()
+        self._section_contents = []
+
+    def end_section(self):
+        if self._section_contents:
+            self._paragraphs.append(f"#### {self._section_title}")
+            self._paragraphs.extend(self._section_contents)
+        self._section_title = None
+
+    def add_usage(self, usage, actions, groups, prefix=None):
+        if not usage:
+            usage = self._prog
+        self.add_text(
+            f"**Usage:** `{usage} {self._format_actions_usage(actions, groups)}`"
+        )
+
+    def add_arguments(self, actions):
+        def _get_metavar(action):
+            return action.metavar or action.dest
+
+        def _format_invocation(action):
+            if action.option_strings:
+                parts = []
+                for option_string in action.option_strings:
+                    if action.nargs == 0:
+                        parts.append(option_string)
+                    else:
+                        parts.append(
+                            f"{option_string} {_get_metavar(action).upper()}"
+                        )
+                return ", ".join(f"`{part}`" for part in parts)
+            return f"`{_get_metavar(action)}`"
+
+        def _get_table_line(action):
+            return f"| {_format_invocation(action)} | {action.help} |"
+
+        table_lines = [
+            "|   |   |",
+            "|---|---|",
+            *(
+                _get_table_line(action)
+                for action in actions
+                if action.help is not argparse.SUPPRESS
+            ),
+        ]
+
+        # Don't want a table with no rows.
+        if len(table_lines) > 2:
+            self.add_text("\n".join(table_lines))
+
+    def format_help(self):
+        return "\n\n".join(self._paragraphs)
+
+
+def generate_readme():
+    """Generate the README.md file.
+
+    Returns:
+        A string with the README contents.
+    """
+    # Deferred import position to avoid circular dependency.
+    # Normally, this would not be required, since we don't use from
+    # imports.  But runpy's import machinery essentially does the
+    # equivalent of a from import on __main__.py.
+    import zmake.__main__  # pylint: disable=import-outside-toplevel
+
+    output = io.StringIO()
+    parser, sub_action = zmake.__main__.get_argparser()
+
+    def _append(*args, **kwargs):
+        kwargs.setdefault("file", output)
+        print(*args, **kwargs)
+
+    def _append_argparse_help(parser):
+        parser.formatter_class = MarkdownHelpFormatter
+        _append(parser.format_help())
+
+    _append("# Zmake")
+    _append()
+    _append(
+        '<!-- Auto-generated contents!  Run "zmake generate-readme" to update. -->'
+    )
+    _append()
+    _append("[TOC]")
+    _append()
+    _append("## Usage")
+    _append()
+    _append_argparse_help(parser)
+    _append()
+    _append("## Subcommands")
+
+    for sub_name, sub_parser in sub_action.choices.items():
+        _append()
+        _append(f"### zmake {sub_name}")
+        _append()
+        _append_argparse_help(sub_parser)
+
+    return output.getvalue()
diff --git a/zephyr/zmake/zmake/jobserver.py b/zephyr/zmake/zmake/jobserver.py
new file mode 100644
index 0000000000..23a45c5e07
--- /dev/null
+++ b/zephyr/zmake/zmake/jobserver.py
@@ -0,0 +1,246 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Module for job counters, limiting the amount of concurrent executions."""
+
+import fcntl
+import functools
+import logging
+import multiprocessing
+import os
+import re
+import select
+import selectors
+import shlex
+import subprocess
+import sys
+
+import zmake
+
+
+class JobHandle:
+    """Small object to handle claim of a job."""
+
+    def __init__(self, release_func, *args, **kwargs):
+        self.release_func = release_func
+        self.args = args
+        self.kwargs = kwargs
+
+    def __enter__(self):
+        pass
+
+    def __exit__(self, exc_type, exc_value, traceback):
+        if self.release_func:
+            self.release_func(*self.args, **self.kwargs)
+
+
+class JobClient:
+    """Abstract base class for all job clients."""
+
+    def get_job(self):
+        """Claim a job."""
+        raise NotImplementedError("Abstract method not implemented")
+
+    @staticmethod
+    def env():
+        """Get the environment variables necessary to share the job server."""
+        return {}
+
+    @staticmethod
+    def is_sequential():
+        """Returns True if the jobserver is using -j1."""
+        return False
+
+    @staticmethod
+    def pass_fds():
+        """Returns the file descriptors that should be passed to subprocesses."""
+        return []
+
+    def popen(self, argv, **kwargs):
+        """Start a process using subprocess.Popen
+
+        All other arguments are passed to subprocess.Popen.
+
+        Returns:
+            A Popen object.
+        """
+        # By default, we scrub the environment for all commands we run, setting
+        # the bare minimum (PATH only).  This prevents us from building obscure
+        # dependencies on the environment variables.
+        kwargs.setdefault(
+            "env", {"PATH": "/bin:/usr/bin", "PYTHONPATH": ":".join(sys.path)}
+        )
+        kwargs.setdefault("pass_fds", [])
+        kwargs["env"].update(self.env())
+        kwargs["pass_fds"] += self.pass_fds()
+
+        logger = logging.getLogger(self.__class__.__name__)
+        logger.debug(
+            "Running `env -i %s%s%s`",
+            " ".join(f"{k}={shlex.quote(v)}" for k, v in kwargs["env"].items()),
+            " " if kwargs["env"] else "",
+            zmake.util.repr_command(argv),
+        )
+        return subprocess.Popen(  # pylint:disable=consider-using-with
+            argv, **kwargs
+        )
+
+
+class GNUMakeJobClient(JobClient):
+    """A job client for GNU make.
+
+    A client of jobserver is allowed to run 1 job without contacting the
+    jobserver, so maintain an optional self._internal_pipe to hold that
+    job.
+    """
+
+    def __init__(self, inheritable_pipe, jobs, internal_jobs=0, makeflags=None):
+        self._makeflags = makeflags
+        self._inheritable_pipe = inheritable_pipe
+        self.jobs = jobs
+        self._selector = selectors.DefaultSelector()
+        if internal_jobs:
+            self._internal_pipe = os.pipe()
+            os.write(self._internal_pipe[1], b"+" * internal_jobs)
+            os.set_blocking(self._internal_pipe[0], False)
+            self._selector.register(
+                self._internal_pipe[0],
+                selectors.EVENT_READ,
+                self._internal_pipe[1],
+            )
+        else:
+            self._internal_pipe = None
+        if self._inheritable_pipe is not None:
+            os.set_blocking(self._inheritable_pipe[0], False)
+            self._selector.register(
+                self._inheritable_pipe[0],
+                selectors.EVENT_READ,
+                self._inheritable_pipe[1],
+            )
+
+    def __del__(self):
+        if self._inheritable_pipe:
+            os.close(self._inheritable_pipe[0])
+            os.close(self._inheritable_pipe[1])
+        if self._internal_pipe:
+            os.close(self._internal_pipe[0])
+            os.close(self._internal_pipe[1])
+
+    @classmethod
+    def from_environ(cls, env=None, jobs=0):
+        """Create a job client from an environment with the MAKEFLAGS variable.
+
+        If we are started under a GNU Make Job Server, we can search
+        the environment for a string "--jobserver-auth=R,W", where R
+        and W will be the read and write file descriptors to the pipe
+        respectively.  If we don't find this environment variable (or
+        the string inside of it), this will raise an OSError.
+
+        The specification for MAKEFLAGS is:
+          * If the first char is "n", this is a dry run, just exit.
+          * If the flags contains -j1, go to sequential mode.
+          * If the flags contains --jobserver-auth=R,W AND those file
+            descriptors are valid, use the jobserver. Otherwise output a
+            warning.
+
+        Args:
+            env: Optionally, the environment to search.
+            jobs: The number of jobs set by the user on the command line.
+
+        Returns:
+            A GNUMakeJobClient configured appropriately or None if there is
+            no MAKEFLAGS environment variable.
+        """
+        if env is None:
+            env = os.environ
+        makeflags = env.get("MAKEFLAGS")
+        if not makeflags:
+            return None
+        match = re.search(r"--jobserver-auth=(\d+),(\d+)", makeflags)
+        if match:
+            pipe = [int(x) for x in match.groups()]
+            if jobs:
+                pipe = None
+                logging.warning(
+                    "-jN forced on command line; ignoring GNU make jobserver"
+                )
+            else:
+                try:
+                    # Use F_GETFD to see if file descriptors are valid
+                    fcntl.fcntl(pipe[0], fcntl.F_GETFD)
+                    fcntl.fcntl(pipe[1], fcntl.F_GETFD)
+                    logging.info("using GNU make jobserver")
+                except OSError:
+                    pipe = None
+                    logging.warning(
+                        "No file descriptors; ignoring GNU make jobserver"
+                    )
+        else:
+            pipe = None
+        if not jobs:
+            match = re.search(r"-j(\d+)", makeflags)
+            if match:
+                jobs = int(match.group(1))
+                if jobs == 1:
+                    logging.info("Running in sequential mode (-j1)")
+        if makeflags[0] == "n":
+            logging.info("MAKEFLAGS contained dry-run flag")
+            sys.exit(0)
+        return cls(pipe, jobs, internal_jobs=1, makeflags=makeflags)
+
+    def get_job(self):
+        """Claim a job.
+
+        Returns:
+            A JobHandle object.
+        """
+        while True:
+            ready_items = self._selector.select()
+            if len(ready_items) > 0:
+                read_fd = ready_items[0][0].fd
+                write_fd = ready_items[0][0].data
+                try:
+                    byte = os.read(read_fd, 1)
+                    return JobHandle(
+                        functools.partial(os.write, write_fd, byte)
+                    )
+                except BlockingIOError:
+                    pass
+
+    def env(self):
+        """Get the environment variables necessary to share the job server."""
+        if self._makeflags:
+            return {"MAKEFLAGS": self._makeflags}
+        flag = ""
+        if self.jobs:
+            flag += f" -j{self.jobs}"
+        if self.jobs != 1 and self._inheritable_pipe is not None:
+            flag += " --jobserver-auth={},{}".format(*self._inheritable_pipe)
+        return {"MAKEFLAGS": flag}
+
+    def is_sequential(self):
+        return self.jobs == 1
+
+    def pass_fds(self):
+        """Returns the file descriptors that should be passed to subprocesses."""
+        if self.jobs != 1 and self._inheritable_pipe is not None:
+            return self._inheritable_pipe
+        return []
+
+
+class GNUMakeJobServer(GNUMakeJobClient):
+    """Implements a GNU Make POSIX Job Server.
+
+    See https://www.gnu.org/software/make/manual/html_node/POSIX-Jobserver.html
+    for specification.
+    """
+
+    def __init__(self, jobs=0):
+        if not jobs:
+            jobs = multiprocessing.cpu_count()
+        elif jobs > select.PIPE_BUF:
+            jobs = select.PIPE_BUF
+        super().__init__(os.pipe(), jobs)
+
+        os.write(self._inheritable_pipe[1], b"+" * jobs)
diff --git a/zephyr/zmake/zmake/modules.py b/zephyr/zmake/zmake/modules.py
new file mode 100644
index 0000000000..717fdced50
--- /dev/null
+++ b/zephyr/zmake/zmake/modules.py
@@ -0,0 +1,102 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Registry of known Zephyr modules."""
+
+import zmake.build_config as build_config
+import zmake.util as util
+
+
+def third_party_module(name, checkout):
+    """Common callback in registry for all third_party/zephyr modules.
+
+    Args:
+        name: The name of the module.
+        checkout: The path to the chromiumos source.
+
+    Return:
+        The path to the module module.
+    """
+    return checkout / "src" / "third_party" / "zephyr" / name
+
+
+known_modules = {
+    "hal_stm32": third_party_module,
+    "cmsis": third_party_module,
+    "ec": lambda name, checkout: (checkout / "src" / "platform" / "ec"),
+    "nanopb": third_party_module,
+    "pigweed": lambda name, checkout: (checkout / "src" / "third_party" / name),
+    "hal_intel": third_party_module,
+    "ish": third_party_module,
+}
+
+
+def locate_from_checkout(checkout_dir):
+    """Find modules from a Chrome OS checkout.
+
+    Important: this function should only conditionally be called if a
+    checkout exists.  Zmake *can* be used without a Chrome OS source
+    tree.  You should call locate_from_directory if outside of a
+    Chrome OS source tree.
+
+    Args:
+        checkout_dir: The path to the chromiumos source.
+
+    Returns:
+        A dictionary mapping module names to paths.
+    """
+    result = {}
+    for name, locator in known_modules.items():
+        result[name] = locator(name, checkout_dir)
+    return result
+
+
+def locate_from_directory(directory):
+    """Create a modules dictionary from a directory.
+
+    This takes a directory, and searches for the known module names
+    located in it.
+
+    Args:
+        directory: the directory to search in.
+
+    Returns:
+        A dictionary mapping module names to paths.
+    """
+    result = {}
+
+    for name in known_modules:
+        modpath = (directory / name).resolve()
+        if (modpath / "zephyr" / "module.yml").is_file():
+            result[name] = modpath
+
+    return result
+
+
+def setup_module_symlinks(output_dir, modules):
+    """Setup a directory with symlinks to modules.
+
+    Args:
+        output_dir: The directory to place the symlinks in.
+        modules: A dictionary of module names mapping to paths.
+
+    Returns:
+        The resultant BuildConfig that should be applied to use each
+        of these modules.
+    """
+    if not output_dir.exists():
+        output_dir.mkdir(parents=True)
+
+    module_links = []
+
+    for name, path in modules.items():
+        link_path = output_dir.resolve() / name
+        util.update_symlink(path, link_path)
+        module_links.append(link_path)
+
+    if module_links:
+        return build_config.BuildConfig(
+            cmake_defs={"ZEPHYR_MODULES": ";".join(map(str, module_links))}
+        )
+    return build_config.BuildConfig()
diff --git a/zephyr/zmake/zmake/multiproc.py b/zephyr/zmake/zmake/multiproc.py
new file mode 100644
index 0000000000..87bae0f02c
--- /dev/null
+++ b/zephyr/zmake/zmake/multiproc.py
@@ -0,0 +1,409 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Zmake multiprocessing utility module.
+
+This module is used to aid in zmake's multiprocessing. It contains tools
+available to log output from multiple processes on the fly. This means that a
+process does not need to finish before the output is available to the developer
+on the screen.
+"""
+
+import collections
+import io
+import logging
+import os
+import select
+import threading
+from typing import Any, ClassVar, Dict, List
+
+
+# Should we log job names or not
+LOG_JOB_NAMES = True
+
+
+class LogWriter:
+    """Contains information about a file descriptor that is producing output
+
+    There is typically one of these for each file descriptor that a process is
+    writing to while running (stdout and stderr).
+
+    Properties:
+        _logger: The logger object to use.
+        _log_level: The logging level to use.
+        _override_func: A function used to override the log level. The
+            function will be called once per line prior to logging and will be
+            passed the arguments of the line and the default log level.
+        _written_at_level: dict:
+            key: log_level
+            value: True if output was written at that level
+        _job_id: The name to prepend to logged lines
+        _file_descriptor: The file descriptor being logged.
+    """
+
+    # A local pipe use to signal the look that a new file descriptor was added and
+    # should be included in the select statement.
+    _logging_interrupt_pipe = []
+
+    # A condition variable used to synchronize logging operations.
+    _logging_cv = threading.Condition()
+    # A map of file descriptors to their LogWriter
+    _logging_map: ClassVar[Dict[io.TextIOBase, "LogWriter"]] = {}
+    # The thread that handles the reading from pipes and writing to log.
+    _logging_thread = None
+
+    @classmethod
+    def reset(cls):
+        """Reset this module to its starting state (useful for tests)"""
+        with LogWriter._logging_cv:
+            LogWriter._logging_map.clear()
+            if len(LogWriter._logging_interrupt_pipe) > 1:
+                os.write(LogWriter._logging_interrupt_pipe[1], b"x")
+            else:
+                cls._logging_interrupt_pipe = os.pipe()
+            LogWriter._logging_thread = None
+            LogWriter._logging_cv.notify_all()
+
+    def __init__(
+        self,
+        logger,
+        log_level,
+        log_level_override_func,
+        job_id,
+        file_descriptor,
+        tee_output=None,
+    ):
+        self._logger = logger
+        self._log_level = log_level
+        self._override_func = log_level_override_func
+        # A map whether output was printed at each logging level
+        self._written_at_level = collections.defaultdict(lambda: False)
+        self._job_id = job_id
+        self._file_descriptor = file_descriptor
+        self._tee_output = tee_output
+
+    def log_line(self, line):
+        """Log a line of output
+
+        If the log-level override function requests a change in log level, that
+        causes self._log_level to be updated accordingly.
+
+        Args:
+            line: Text line to log
+        """
+        if self._tee_output:
+            self._tee_output.write(line)
+            self._tee_output.write("\n")
+        if self._override_func:
+            # Get the new log level and update the default. The reason we
+            # want to update the default is that if we hit an error, all
+            # future logging should be moved to the new logging level. This
+            # greatly simplifies the logic that is needed to update the log
+            # level.
+            self._log_level = self._override_func(line, self._log_level)
+        if self._job_id and LOG_JOB_NAMES:
+            self._logger.log(self._log_level, "[%s]%s", self._job_id, line)
+        else:
+            self._logger.log(self._log_level, line)
+        self._written_at_level[self._log_level] = True
+
+    def has_written(self, log_level):
+        """Check if output was written at a certain log level
+
+        Args:
+            log_level: log level to check
+
+        Returns:
+            True if any output was written at that log level, False if not
+        """
+        return self._written_at_level[log_level]
+
+    def wait(self):
+        """Wait for this LogWriter to finish.
+
+        This method will block execution until all the logs have been flushed out.
+        """
+        with LogWriter._logging_cv:
+            LogWriter._logging_cv.wait_for(
+                lambda: self._file_descriptor not in LogWriter._logging_map
+            )
+        if self._tee_output:
+            self._tee_output.close()
+            self._tee_output = None
+
+    @classmethod
+    def _log_fd(cls, file_descriptor: io.TextIOBase):
+        """Log information from a single file descriptor.
+
+        This function is BLOCKING. It will read from the given file descriptor until
+        either the end of line is read or EOF. Once EOF is read it will remove the
+        file descriptor from _logging_map so it will no longer be used.
+        Additionally, in some cases, the file descriptor will be closed (caused by
+        a call to Popen.wait()). In these cases, the file descriptor will also be
+        removed from the map as it is no longer valid.
+        """
+        with LogWriter._logging_cv:
+            if file_descriptor in LogWriter._logging_map:
+                writer = LogWriter._logging_map[file_descriptor]
+                if file_descriptor.closed:
+                    del LogWriter._logging_map[file_descriptor]
+                    LogWriter._logging_cv.notify_all()
+                    return
+                line = file_descriptor.readline()
+                if not line:
+                    # EOF
+                    del LogWriter._logging_map[file_descriptor]
+                    LogWriter._logging_cv.notify_all()
+                    return
+                line = line.rstrip("\n")
+                if line:
+                    writer.log_line(line)
+
+    @classmethod
+    def _prune_logging_fds(cls):
+        """Prune the current file descriptors under _logging_map.
+
+        This function will iterate over the logging map and check for closed file
+        descriptors. Every closed file descriptor will be removed.
+        """
+        with LogWriter._logging_cv:
+            remove = [
+                file_descriptor
+                for file_descriptor in LogWriter._logging_map
+                if file_descriptor.closed
+            ]
+            for file_descriptor in remove:
+                del LogWriter._logging_map[file_descriptor]
+            if remove:
+                LogWriter._logging_cv.notify_all()
+
+    @classmethod
+    def _logging_loop(cls):
+        """The primary logging thread loop.
+
+        This is the entry point of the logging thread. It will listen for (1) any
+        new data on the output file descriptors that were added via log_output() and
+        (2) any new file descriptors being added by log_output(). Once a file
+        descriptor is ready to be read, this function will call _log_fd to perform
+        the actual read and logging.
+        """
+        while True:
+            with LogWriter._logging_cv:
+                LogWriter._logging_cv.wait_for(lambda: LogWriter._logging_map)
+                keys: List[Any] = list(LogWriter._logging_map.keys())
+                keys.append(LogWriter._logging_interrupt_pipe[0])
+            try:
+                fds, _, _ = select.select(keys, [], [])
+            except ValueError:
+                # One of the file descriptors must be closed, prune them and try
+                # again.
+                LogWriter._prune_logging_fds()
+                continue
+            if LogWriter._logging_interrupt_pipe[0] in fds:
+                # We got a sentinel byte sent by log_output(), this is a signal used to
+                # break out of the blocking select.select call to tell us that the
+                # file descriptor set has changed. We just need to read the byte and
+                # remove this descriptor from the list. If we actually have data
+                # that should be read it will be read in the for loop below.
+                os.read(LogWriter._logging_interrupt_pipe[0], 1)
+                fds.remove(LogWriter._logging_interrupt_pipe[0])
+            for file in fds:
+                LogWriter._log_fd(file)
+
+    @classmethod
+    def log_output(
+        cls,
+        logger,
+        log_level,
+        file_descriptor,
+        log_level_override_func=None,
+        job_id=None,
+        tee_output=None,
+    ):
+        """Log the output from the given file descriptor.
+
+        Args:
+            logger: The logger object to use.
+            log_level: The logging level to use.
+            file_descriptor: The file descriptor to read from.
+            log_level_override_func: A function used to override the log level. The
+            function will be called once per line prior to logging and will be
+            passed the arguments of the line and the default log level.
+
+        Returns:
+            LogWriter object for the resulting output
+        """
+        with LogWriter._logging_cv:
+            if (
+                LogWriter._logging_thread is None
+                or not LogWriter._logging_thread.is_alive()
+            ):
+                # First pass or thread must have died, create a new one.
+                LogWriter._logging_thread = threading.Thread(
+                    target=LogWriter._logging_loop, daemon=True
+                )
+                LogWriter._logging_thread.start()
+
+            writer = LogWriter(
+                logger,
+                log_level,
+                log_level_override_func,
+                job_id,
+                file_descriptor,
+                tee_output=tee_output,
+            )
+            LogWriter._logging_map[file_descriptor] = writer
+            # Write a sentinel byte to the pipe to break the select so we can add the
+            # new fd.
+            os.write(LogWriter._logging_interrupt_pipe[1], b"x")
+            # Notify the condition so we can run the select on the current fds.
+            LogWriter._logging_cv.notify_all()
+        return writer
+
+    @classmethod
+    def wait_for_log_end(cls):
+        """Wait for all the logs to be printed.
+
+        This method will block execution until all the logs have been flushed out.
+        """
+        with LogWriter._logging_cv:
+            LogWriter._logging_cv.wait_for(lambda: not LogWriter._logging_map)
+
+
+class ThreadWithResult(threading.Thread):
+    """Subclass to create a thread and return the result from the target"""
+
+    def __init__(
+        self,
+        group=None,
+        target=None,
+        name=None,
+        args=(),
+        kwargs=None,
+        *,
+        daemon=None
+    ):
+        threading.Thread.__init__(
+            self,
+            group=group,
+            target=target,
+            name=name,
+            args=args,
+            kwargs=kwargs,
+            daemon=daemon,
+        )
+        self._return = None
+
+    def run(self):
+        if self._target is not None:
+            self._return = self._target(*self._args, **self._kwargs)
+
+    def join(self, timeout=None):
+        threading.Thread.join(self, timeout=timeout)
+        return self._return
+
+
+class Executor:
+    """Parallel executor helper class.
+
+    This class is used to run multiple functions in parallel. The functions MUST
+    return an integer result code (or throw an exception). This class will start
+    a thread per operation and wait() for all the threads to resolve.
+
+    Attributes:
+        lock: The condition variable used to synchronize across threads.
+        threads: A list of threading.Thread objects currently under this
+         Executor.
+        results: A list of result codes returned by each of the functions called
+         by this Executor.
+    """
+
+    def __init__(self):
+        self.lock = threading.Condition()
+        self.threads = []
+        self.results = []
+        self.logger = logging.getLogger(self.__class__.__name__)
+
+    def append(self, func):
+        """Append the given function to the wait list.
+
+        Once added, the function's return value will be used to determine the
+        Executor's final result value. The function must return an int result
+        code or throw an exception. For example: If two functions were added
+        to the Executor, they will both be run in parallel and their results
+        will determine whether or not the Executor succeeded. If both functions
+        returned 0, then the Executor's wait function will also return 0.
+
+        Args:
+            func: A function which returns an int result code or throws an
+             exception.
+
+        Returns:
+            A join function which will wait until this task is finished.
+        """
+        with self.lock:
+            thread = ThreadWithResult(
+                target=lambda: self._run_fn(func), daemon=True
+            )
+            thread.start()
+            self.threads.append(thread)
+            return thread.join
+
+    def wait(self):
+        """Wait for a result to be available.
+
+        This function waits for the executor to resolve (i.e., all
+        threads have finished).
+
+        Returns:
+            An integer result code of either the first failed function or 0 if
+            they all succeeded.
+        """
+        with self.lock:
+            self.lock.wait_for(predicate=lambda: self._is_finished)
+            return self._result
+
+    def _run_fn(self, func):
+        """Entry point to each running thread.
+
+        This function will run the function provided in the append() function.
+        The result value of the function will be used to determine the
+        Executor's result value. If the function throws any exception it will be
+        caught and -1 will be used as the assumed result value.
+
+        Args:
+            func: The function to run.
+        """
+        try:
+            result = func()
+        except Exception as e:  # pylint: disable=broad-except
+            self.logger.exception(e)
+            result = -1
+        with self.lock:
+            self.results.append(result)
+            self.lock.notify_all()
+
+        return result
+
+    @property
+    def _is_finished(self):
+        """Whether or not the Executor is considered to be done.
+
+        Returns:
+            True if the Executor is considered done.
+        """
+        if len(self.threads) == len(self.results):
+            return True
+        return False
+
+    @property
+    def _result(self):
+        """The result code of the Executor.
+
+        Note that _is_finished must be True for this to have any meaning.
+
+        Returns:
+            An int representing the result value of the underlying functions.
+        """
+        return next((result for result in self.results if result), 0)
diff --git a/zephyr/zmake/zmake/output_packers.py b/zephyr/zmake/zmake/output_packers.py
new file mode 100644
index 0000000000..abf9e3bf20
--- /dev/null
+++ b/zephyr/zmake/zmake/output_packers.py
@@ -0,0 +1,283 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Types which provide many builds and composite them into a single binary."""
+import logging
+from pathlib import Path
+import shutil
+import subprocess
+import sys
+from typing import Dict, Optional
+
+import zmake.build_config as build_config
+import zmake.jobserver
+import zmake.multiproc
+import zmake.util as util
+
+
+class BasePacker:
+    """Abstract base for all packers."""
+
+    def __init__(self, project):
+        self.project = project
+
+    @staticmethod
+    def configs():
+        """Get all of the build configurations necessary.
+
+        Yields:
+            2-tuples of config name and a BuildConfig.
+        """
+        yield "singleimage", build_config.BuildConfig()
+
+    def pack_firmware(
+        self,
+        work_dir,
+        jobclient: zmake.jobserver.JobClient,
+        dir_map: Dict[str, Path],
+        version_string="",
+    ):
+        """Pack a firmware image.
+
+        Config names from the configs generator are passed as keyword
+        arguments, with each argument being set to the path of the
+        build directory.
+
+        Args:
+            work_dir: A directory to write outputs and temporary files
+            into.
+            jobclient: A JobClient object to use.
+            dir_map: A dict of build dirs such as {'ro': path_to_ro_dir}.
+            version_string: The version string, which may end up in
+               certain parts of the outputs.
+
+        Yields:
+            2-tuples of the path of each file in the work_dir (or any
+            other directory) which should be copied into the output
+            directory, and the output filename.
+        """
+        raise NotImplementedError("Abstract method not implemented")
+
+    @staticmethod
+    def _get_max_image_bytes(dir_map) -> Optional[int]:
+        """Get the maximum allowed image size (in bytes).
+
+        This value will generally be found in CONFIG_FLASH_SIZE but may vary
+        depending on the specific way things are being packed.
+
+        Args:
+            file: A file to test.
+            dir_map: A dict of build dirs such as {'ro': path_to_ro_dir}.
+
+        Returns:
+            The maximum allowed size of the image in bytes, or None if the size
+            is not limited.
+        """
+        del dir_map
+
+    def _check_packed_file_size(self, file, dir_map):
+        """Check that a packed file passes size constraints.
+
+        Args:
+            file: A file to test.
+            dir_map: A dict of build dirs such as {'ro': path_to_ro_dir}.
+
+
+        Returns:
+            The file if it passes the test.
+        """
+        max_size = (
+            self._get_max_image_bytes(  # pylint: disable=assignment-from-none
+                dir_map
+            )
+        )
+        if max_size is None or file.stat().st_size <= max_size:
+            return file
+        raise RuntimeError("Output file ({}) too large".format(file))
+
+
+class ElfPacker(BasePacker):
+    """Raw proxy for ELF output of a single build."""
+
+    def pack_firmware(self, work_dir, jobclient, dir_map, version_string=""):
+        del version_string
+        yield dir_map["singleimage"] / "zephyr" / "zephyr.elf", "zephyr.elf"
+
+
+class RawBinPacker(BasePacker):
+    """Raw proxy for zephyr.bin output of a single build."""
+
+    def pack_firmware(self, work_dir, jobclient, dir_map, version_string=""):
+        del version_string
+        yield dir_map["singleimage"] / "zephyr" / "zephyr.bin", "ec.bin"
+
+
+class IshBinPacker(BasePacker):
+    """Raw proxy for ish_fw.bin output of a single build."""
+
+    def pack_firmware(self, work_dir, jobclient, dir_map, version_string=""):
+        del version_string
+        yield dir_map["singleimage"] / "zephyr" / "ish_fw.bin", "ish_fw.bin"
+
+
+class BinmanPacker(BasePacker):
+    """Packer for RO/RW image to generate a .bin build using FMAP."""
+
+    ro_file = "zephyr.bin"
+    rw_file = "zephyr.bin"
+
+    def __init__(self, project):
+        self.logger = logging.getLogger(self.__class__.__name__)
+        super().__init__(project)
+
+    def configs(self):
+        yield "ro", build_config.BuildConfig(
+            kconfig_defs={"CONFIG_CROS_EC_RO": "y"}
+        )
+        yield "rw", build_config.BuildConfig(
+            kconfig_defs={"CONFIG_CROS_EC_RW": "y"}
+        )
+
+    def pack_firmware(
+        self,
+        work_dir,
+        jobclient: zmake.jobserver.JobClient,
+        dir_map,
+        version_string="",
+    ):
+        """Pack RO and RW sections using Binman.
+
+        Binman configuration is expected to be found in the RO build
+        device-tree configuration.
+
+        Args:
+            work_dir: The directory used for packing.
+            jobclient: The client used to run subprocesses.
+            dir_map: A dict of build dirs such as {'ro': path_to_ro_dir}.
+            version_string: The version string to use in FRID/FWID.
+
+        Yields:
+            2-tuples of the path of each file in the work_dir that
+            should be copied into the output directory, and the output
+            filename.
+        """
+        ro_dir = dir_map["ro"]
+        rw_dir = dir_map["rw"]
+        dts_file_path = ro_dir / "zephyr" / "zephyr.dts"
+
+        # Copy the inputs into the work directory so that Binman can
+        # find them under a hard-coded name.
+        shutil.copy2(
+            ro_dir / "zephyr" / self.ro_file, work_dir / "zephyr_ro.bin"
+        )
+        shutil.copy2(
+            rw_dir / "zephyr" / self.rw_file, work_dir / "zephyr_rw.bin"
+        )
+
+        # Version in FRID/FWID can be at most 31 bytes long (32, minus
+        # one for null character).
+        if len(version_string) > 31:
+            version_string = version_string[:31]
+
+        proc = jobclient.popen(
+            [
+                sys.executable,
+                util.get_tool_path("binman"),
+                "-v",
+                "5",
+                "build",
+                "-a",
+                "version={}".format(version_string),
+                "-d",
+                dts_file_path,
+                "-m",
+                "-O",
+                work_dir,
+            ],
+            cwd=work_dir,
+            stdout=subprocess.PIPE,
+            stderr=subprocess.PIPE,
+            encoding="utf-8",
+        )
+
+        zmake.multiproc.LogWriter.log_output(
+            self.logger, logging.DEBUG, proc.stdout
+        )
+        zmake.multiproc.LogWriter.log_output(
+            self.logger, logging.ERROR, proc.stderr
+        )
+        if proc.wait(timeout=60):
+            raise OSError("Failed to run binman")
+
+        yield work_dir / "ec.bin", "ec.bin"
+        yield ro_dir / "zephyr" / "zephyr.elf", "zephyr.ro.elf"
+        yield rw_dir / "zephyr" / "zephyr.elf", "zephyr.rw.elf"
+
+
+class NpcxPacker(BinmanPacker):
+    """Packer for RO/RW image to generate a .bin build using FMAP.
+
+    This expects that the build is setup to generate a
+    zephyr.npcx.bin for the RO image, which should be packed using
+    Nuvoton's loader format.
+    """
+
+    ro_file = "zephyr.npcx.bin"
+    npcx_monitor = "npcx_monitor.bin"
+
+    def _get_max_image_bytes(self, dir_map):
+        ro_dir = dir_map["ro"]
+        rw_dir = dir_map["rw"]
+        ro_size = util.read_kconfig_autoconf_value(
+            ro_dir / "zephyr" / "include" / "generated",
+            "CONFIG_PLATFORM_EC_FLASH_SIZE_BYTES",
+        )
+        rw_size = util.read_kconfig_autoconf_value(
+            rw_dir / "zephyr" / "include" / "generated",
+            "CONFIG_PLATFORM_EC_FLASH_SIZE_BYTES",
+        )
+        return max(int(ro_size, 0), int(rw_size, 0))
+
+    # This can probably be removed too and just rely on binman to
+    # check the sizes... see the comment above.
+    def pack_firmware(self, work_dir, jobclient, dir_map, version_string=""):
+        ro_dir = dir_map["ro"]
+        for path, output_file in super().pack_firmware(
+            work_dir,
+            jobclient,
+            dir_map,
+            version_string=version_string,
+        ):
+            if output_file == "ec.bin":
+                yield (
+                    self._check_packed_file_size(path, dir_map),
+                    "ec.bin",
+                )
+            else:
+                yield path, output_file
+
+        # Include the NPCX monitor file as an output artifact.
+        yield ro_dir / self.npcx_monitor, self.npcx_monitor
+
+
+# MCHP all we do is set binman's ro file to zephyr.mchp.bin
+class MchpPacker(BinmanPacker):
+    """Packer for RO/RW image to generate a .bin build using FMAP.
+
+    This expects that the build is setup to generate a
+    zephyr.mchp.bin for the RO image, which should be packed using
+    Microchip's loader format.
+    """
+
+    ro_file = "zephyr.mchp.bin"
+
+
+# A dictionary mapping packer config names to classes.
+packer_registry = {
+    "binman": BinmanPacker,
+    "elf": ElfPacker,
+    "npcx": NpcxPacker,
+    "raw": RawBinPacker,
+    "mchp": MchpPacker,
+}
diff --git a/zephyr/zmake/zmake/project.py b/zephyr/zmake/zmake/project.py
new file mode 100644
index 0000000000..2c91e27ba7
--- /dev/null
+++ b/zephyr/zmake/zmake/project.py
@@ -0,0 +1,289 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Module for project config wrapper object."""
+
+import dataclasses
+import logging
+import pathlib
+import typing
+
+import zmake.build_config as build_config
+import zmake.configlib as configlib
+import zmake.modules
+import zmake.output_packers
+import zmake.toolchains as toolchains
+
+
+def module_dts_overlay_name(modpath, board_name):
+    """Given a board name, return the expected DTS overlay path.
+
+    Args:
+        modpath: the module path as a pathlib.Path object
+        board_name: the name of the board
+
+    Returns:
+        A pathlib.Path object to the expected overlay path.
+    """
+    return (
+        modpath
+        / "zephyr"
+        / "dts"
+        / "board-overlays"
+        / "{}.dts".format(board_name)
+    )
+
+
+@dataclasses.dataclass
+class ProjectConfig:
+    """All the information needed to define a project."""
+
+    # pylint: disable=too-many-instance-attributes
+    project_name: str
+    zephyr_board: str
+    supported_toolchains: "list[str]"
+    output_packer: type
+    modules: typing.Iterable[str] = dataclasses.field(
+        default_factory=lambda: ["ec"],
+    )
+    dts_overlays: "list[str]" = dataclasses.field(default_factory=list)
+    kconfig_files: "list[pathlib.Path]" = dataclasses.field(
+        default_factory=list
+    )
+    project_dir: pathlib.Path = dataclasses.field(default_factory=pathlib.Path)
+    inherited_from: typing.Iterable[str] = dataclasses.field(
+        default_factory=list
+    )
+
+    @property
+    def full_name(self) -> str:
+        """Get the full project name, e.g. baseboard.variant"""
+        inherited_from = (
+            [self.inherited_from]
+            if isinstance(self.inherited_from, str)
+            else self.inherited_from
+        )
+
+        return ".".join([*inherited_from, self.project_name])
+
+
+class Project:
+    """An object encapsulating a project directory."""
+
+    def __init__(self, config: ProjectConfig):
+        self.config = config
+        self.packer: zmake.output_packers.BasePacker = (
+            self.config.output_packer(self)
+        )
+
+    def iter_builds(self):
+        """Iterate thru the build combinations provided by the project's packer.
+
+        Yields:
+            2-tuples of a build configuration name and a BuildConfig.
+        """
+        conf = build_config.BuildConfig(
+            cmake_defs={"BOARD": self.config.zephyr_board}
+        )
+
+        kconfig_files = []
+        prj_conf = self.config.project_dir / "prj.conf"
+        if prj_conf.is_file():
+            kconfig_files.append(prj_conf)
+        kconfig_files.extend(self.config.kconfig_files)
+        conf |= build_config.BuildConfig(kconfig_files=kconfig_files)
+
+        for build_name, packer_config in self.packer.configs():
+            yield build_name, conf | packer_config
+
+    def find_dts_overlays(self, modules):
+        """Find appropriate dts overlays from registered modules.
+
+        Args:
+            modules: A dictionary of module names mapping to paths.
+
+        Returns:
+            A BuildConfig with relevant configurations to enable the
+            found DTS overlay files.
+        """
+        overlays = []
+        for module_path in modules.values():
+            dts_path = module_dts_overlay_name(
+                module_path, self.config.zephyr_board
+            )
+            if dts_path.is_file():
+                overlays.append(dts_path.resolve())
+
+        for path in self.config.dts_overlays:
+            # Support configs which don't explicitly put "here" in front.
+            if isinstance(path, str):
+                path = self.config.project_dir / path
+            overlays.append(path.resolve())
+
+        if overlays:
+            return build_config.BuildConfig(
+                cmake_defs={"DTC_OVERLAY_FILE": ";".join(map(str, overlays))}
+            )
+        return build_config.BuildConfig()
+
+    def prune_modules(self, module_paths):
+        """Reduce a modules dict to the ones required by this project.
+
+        If this project does not define a modules list in the
+        configuration, it is assumed that all known modules to Zmake
+        are required.  This is typically inconsequential as Zephyr
+        module design conventions require a Kconfig option to actually
+        enable most modules.
+
+        Args:
+            module_paths: A dictionary mapping module names to their
+                paths.  This dictionary is not modified.
+
+        Returns:
+            A new module_paths dictionary with only the modules
+            required by this project.
+
+        Raises:
+            A KeyError, if a required module is unavailable.
+        """
+        result = {}
+        for module in self.config.modules:
+            try:
+                result[module] = module_paths[module]
+            except KeyError as e:
+                raise KeyError(
+                    "The {!r} module is required by the {} project, but is not "
+                    "available.".format(module, self.config.project_dir)
+                ) from e
+        return result
+
+    def get_toolchain(self, module_paths, override=None):
+        """Get the first supported toolchain that is actually available."""
+        if override:
+            if override not in self.config.supported_toolchains:
+                logging.warning(
+                    "Toolchain %r isn't supported by this project. You're on your own.",
+                    override,
+                )
+            support_class = toolchains.support_classes.get(
+                override, toolchains.GenericToolchain
+            )
+            return support_class(name=override, modules=module_paths)
+        for name in self.config.supported_toolchains:
+            support_class = toolchains.support_classes[name]
+            toolchain = support_class(name=name, modules=module_paths)
+            if toolchain.probe():
+                logging.info(
+                    "Toolchain %r selected by probe function.", toolchain
+                )
+                return toolchain
+        raise OSError(
+            "No supported toolchains could be found on your system. If you see "
+            "this message in the chroot, it indicates a bug. Otherwise, you'll "
+            "either want to setup your system with a supported toolchain, or "
+            "manually select an unsupported toolchain with the -t flag."
+        )
+
+
+@dataclasses.dataclass
+class ProjectRegistrationHandler:
+    """Return value of register_project.
+
+    This is intended to be used to create simple variants of a project
+    like so::
+
+        brd = register_project(project_name="brd", ...)
+        brd_changed = brd.variant(project_name="brd-changed", ...)
+        brd_changed_again = brd_changed.variant(project_name="brd-changed-again", ...)
+    """
+
+    base_config: ProjectConfig
+    register_func: typing.Callable[[], "ProjectRegistrationHandler"]
+
+    def variant(self, **kwargs) -> "ProjectRegistrationHandler":
+        """Register a new variant based on the base config.
+
+        Args:
+            kwargs: Any project config changes.  Note lists will be
+                concatenated.
+
+        Returns:
+            Another ProjectRegistrationHandler.
+        """
+        new_config = dataclasses.asdict(self.base_config)
+        new_config["inherited_from"] = [
+            *self.base_config.inherited_from,
+            self.base_config.project_name,
+        ]
+
+        for key, value in kwargs.items():
+            if isinstance(value, list):
+                new_config[key] = [*new_config[key], *value]
+            else:
+                new_config[key] = value
+        return self.register_func(**new_config)
+
+
+def load_config_file(path) -> typing.List[Project]:
+    """Load a BUILD.py config file and create associated projects.
+
+    Args:
+        path: A pathlib.Path to the BUILD.py file.
+
+    Returns:
+        A list of Project objects specified by the file.
+    """
+    projects: typing.List[Project] = []
+
+    def register_project(**kwargs) -> ProjectRegistrationHandler:
+        config = ProjectConfig(**kwargs)
+        projects.append(Project(config))
+        return ProjectRegistrationHandler(
+            base_config=config,
+            register_func=register_project,
+        )
+
+    # The Python environment passed to the config file.
+    config_globals = {
+        "register_project": register_project,
+        "here": path.parent.resolve(),
+    }
+
+    # First, load the global helper functions.
+    code = compile(
+        pathlib.Path(configlib.__file__).read_bytes(),
+        configlib.__file__,
+        "exec",
+    )
+    exec(code, config_globals)  # pylint: disable=exec-used
+
+    # Next, load the BUILD.py
+    logging.debug("Loading config file %s", path)
+    code = compile(path.read_bytes(), str(path), "exec")
+    exec(code, config_globals)  # pylint: disable=exec-used
+    logging.debug("Config file %s defines %s projects", path, len(projects))
+    return projects
+
+
+def find_projects(root_dir) -> typing.Dict[str, Project]:
+    """Finds all zmake projects in root_dir.
+
+    Args:
+        root_dir: the root dir as a pathlib.Path object
+
+    Returns:
+        A dictionary mapping project names to Project objects.
+    """
+    logging.debug("Finding zmake targets under '%s'.", root_dir)
+    found_projects = {}
+    for path in pathlib.Path(root_dir).rglob("BUILD.py"):
+        for project in load_config_file(path):
+            if project.config.project_name in found_projects:
+                raise KeyError(
+                    "Duplicate project defined: {} (in {})".format(
+                        project.config.project_name, path
+                    )
+                )
+            found_projects[project.config.project_name] = project
+    return found_projects
diff --git a/zephyr/zmake/zmake/toolchains.py b/zephyr/zmake/zmake/toolchains.py
new file mode 100644
index 0000000000..a92baf2a3e
--- /dev/null
+++ b/zephyr/zmake/zmake/toolchains.py
@@ -0,0 +1,179 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Definitions of toolchain variables."""
+
+import os
+import pathlib
+
+import zmake.build_config as build_config
+
+
+class GenericToolchain:
+    """Default toolchain if not known to zmake.
+
+    Simply pass ZEPHYR_TOOLCHAIN_VARIANT=name to the build, with
+    nothing extra.
+    """
+
+    def __init__(self, name, modules=None):
+        self.name = name
+        self.modules = modules or {}
+
+    @staticmethod
+    def probe():
+        """Probe if the toolchain is available on the system."""
+        # Since the toolchain is not known to zmake, we have no way to
+        # know if it's installed.  Simply return False to indicate not
+        # installed.  An unknown toolchain would only be used if -t
+        # was manually passed to zmake, and is not valid to put in a
+        # BUILD.py file.
+        return False
+
+    def get_build_config(self):
+        """Get the build configuration for the toolchain.
+
+        Returns:
+            A build_config.BuildConfig to be applied to the build.
+        """
+        return build_config.BuildConfig(
+            cmake_defs={
+                "ZEPHYR_TOOLCHAIN_VARIANT": self.name,
+            },
+        )
+
+
+class CorebootSdkToolchain(GenericToolchain):
+    """Coreboot SDK toolchain installed in default location."""
+
+    @staticmethod
+    def _find_coreboot_sdk():
+        """Find coreboot-sdk, if available.
+
+        Returns:
+            The path to coreboot-sdk, or None if unavailable.
+        """
+        path = pathlib.Path(
+            os.environ.get("COREBOOT_SDK_ROOT", "/opt/coreboot-sdk")
+        ).resolve()
+        if path.is_dir():
+            return path
+        return None
+
+    def probe(self):
+        return bool(self._find_coreboot_sdk())
+
+    def get_build_config(self):
+        return (
+            build_config.BuildConfig(
+                cmake_defs={
+                    "TOOLCHAIN_ROOT": str(self.modules["ec"] / "zephyr"),
+                    "COREBOOT_SDK_ROOT": str(self._find_coreboot_sdk()),
+                },
+            )
+            | super().get_build_config()
+        )
+
+
+class ZephyrToolchain(GenericToolchain):
+    """Zephyr SDK toolchain.
+
+    Either set the environment var ZEPHYR_SDK_INSTALL_DIR, or install
+    the SDK in one of the common known locations.
+    """
+
+    def __init__(self, *args, **kwargs):
+        self.zephyr_sdk_install_dir = self._find_zephyr_sdk()
+        super().__init__(*args, **kwargs)
+
+    @staticmethod
+    def _find_zephyr_sdk():
+        """Find the Zephyr SDK, if it's installed.
+
+        Returns:
+            The path to the Zephyr SDK, using the search rules defined by
+            https://docs.zephyrproject.org/latest/getting_started/installation_linux.html,
+            or None, if one cannot be found on the system.
+        """
+        from_env = os.getenv("ZEPHYR_SDK_INSTALL_DIR")
+        if from_env:
+            return pathlib.Path(from_env)
+
+        def _gen_sdk_paths():
+            for prefix in (
+                "~",
+                "~/.local",
+                "~/.local/opt",
+                "~/bin",
+                "/opt",
+                "/usr",
+                "/usr/local",
+            ):
+                prefix = pathlib.Path(os.path.expanduser(prefix))
+                yield prefix / "zephyr-sdk"
+                yield from prefix.glob("zephyr-sdk-*")
+
+        for path in _gen_sdk_paths():
+            if (path / "sdk_version").is_file():
+                return path
+
+        return None
+
+    def probe(self):
+        return bool(self.zephyr_sdk_install_dir)
+
+    def get_build_config(self):
+        if not self.zephyr_sdk_install_dir:
+            raise RuntimeError(
+                "No installed Zephyr SDK was found"
+                " (see docs/zephyr/zephyr_build.md for documentation)"
+            )
+        tc_vars = {
+            "ZEPHYR_SDK_INSTALL_DIR": str(self.zephyr_sdk_install_dir),
+        }
+        return (
+            build_config.BuildConfig(cmake_defs=tc_vars)
+            | super().get_build_config()
+        )
+
+
+class LlvmToolchain(GenericToolchain):
+    """LLVM toolchain as used in the chroot."""
+
+    def probe(self):
+        # TODO: differentiate chroot llvm path vs. something more
+        # generic?
+        return pathlib.Path("/usr/bin/x86_64-pc-linux-gnu-clang").exists()
+
+    def get_build_config(self):
+        # TODO: this contains custom settings for the chroot.  Plumb a
+        # toolchain for "generic-llvm" for external uses?
+        return (
+            build_config.BuildConfig(
+                cmake_defs={
+                    "TOOLCHAIN_ROOT": str(self.modules["ec"] / "zephyr"),
+                },
+            )
+            | super().get_build_config()
+        )
+
+
+class HostToolchain(GenericToolchain):
+    """GCC toolchain found in the PATH."""
+
+    def probe(self):
+        # "host" toolchain for Zephyr means GCC.
+        for search_path in os.getenv("PATH", "/usr/bin").split(":"):
+            if (pathlib.Path(search_path) / "gcc").exists():
+                return True
+        return False
+
+
+# Mapping of toolchain names -> support class
+support_classes = {
+    "coreboot-sdk": CorebootSdkToolchain,
+    "host": HostToolchain,
+    "llvm": LlvmToolchain,
+    "zephyr": ZephyrToolchain,
+}
diff --git a/zephyr/zmake/zmake/util.py b/zephyr/zmake/zmake/util.py
new file mode 100644
index 0000000000..6d5905e60c
--- /dev/null
+++ b/zephyr/zmake/zmake/util.py
@@ -0,0 +1,208 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Common miscellaneous utility functions for zmake."""
+
+import os
+import pathlib
+import re
+import shlex
+import shutil
+
+
+def c_str(input_str):
+    """Make a string that can be included as a literal in C source code.
+
+    Args:
+        input_str: The string to process.
+
+    Returns:
+        A string which can be included in C source code.
+    """
+
+    def c_chr(char):
+        # Convert a char in a string to the C representation.  Per the
+        # C standard, we can use all characters but quote, newline,
+        # and backslash directly with no replacements.
+        return {
+            '"': r"\"",
+            "\n": r"\n",
+            "\\": "\\\\",
+        }.get(char, char)
+
+    return '"{}"'.format("".join(map(c_chr, input_str)))
+
+
+def locate_cros_checkout():
+    """Find the path to the ChromiumOS checkout.
+
+    Returns:
+        The first directory found with a .repo directory in it,
+        starting by checking the CROS_WORKON_SRCROOT environment
+        variable, then scanning upwards from the current directory,
+        and finally from a known set of common paths.
+    """
+
+    def propose_checkouts():
+        yield os.getenv("CROS_WORKON_SRCROOT")
+
+        path = pathlib.Path.cwd()
+        while path.resolve() != pathlib.Path("/"):
+            yield path
+            path = path / ".."
+
+        yield "/mnt/host/source"
+        yield pathlib.Path.home() / "trunk"
+        yield pathlib.Path.home() / "chromiumos"
+
+    for path in propose_checkouts():
+        if not path:
+            continue
+        path = pathlib.Path(path)
+        if (path / ".repo").is_dir():
+            return path.resolve()
+
+    raise FileNotFoundError("Unable to locate a ChromiumOS checkout")
+
+
+def read_kconfig_file(path):
+    """Parse a Kconfig file.
+
+    Args:
+        path: The path to open.
+
+    Returns:
+        A dictionary of kconfig items to their values.
+    """
+    result = {}
+    with open(path) as file:
+        for line in file:
+            line, _, _ = line.partition("#")
+            line = line.strip()
+            if line:
+                name, _, value = line.partition("=")
+                result[name.strip()] = value.strip()
+    return result
+
+
+def read_kconfig_autoconf_value(path, key):
+    """Parse an autoconf.h file for a resolved kconfig value
+
+    Args:
+        path: The path to the autoconf.h file.
+        key: The define key to lookup.
+
+    Returns:
+        The value associated with the key or nothing if the key wasn't found.
+    """
+    prog = re.compile(r"^#define\s{}\s(\S+)$".format(key))
+    with open(path / "autoconf.h") as file:
+        for line in file:
+            match = prog.match(line)
+            if match:
+                return match.group(1)
+    return None
+
+
+def write_kconfig_file(path, config, only_if_changed=True):
+    """Write out a dictionary to Kconfig format.
+
+    Args:
+        path: The path to write to.
+        config: The dictionary to write.
+        only_if_changed: Set to True if the file should not be written
+            unless it has changed.
+    """
+    if only_if_changed:
+        if path.exists() and read_kconfig_file(path) == config:
+            return
+    with open(path, "w") as file:
+        for name, value in config.items():
+            file.write("{}={}\n".format(name, value))
+
+
+def read_zephyr_version(zephyr_base):
+    """Read the Zephyr version from a Zephyr OS checkout.
+
+    Args:
+         zephyr_base: path to the Zephyr OS repository.
+
+    Returns:
+         A 3-tuple of the version number (major, minor, patchset).
+    """
+    version_file = pathlib.Path(zephyr_base) / "VERSION"
+
+    file_vars = {}
+    with open(version_file) as file:
+        for line in file:
+            key, _, value = line.partition("=")
+            file_vars[key.strip()] = value.strip()
+
+    return (
+        int(file_vars["VERSION_MAJOR"]),
+        int(file_vars["VERSION_MINOR"]),
+        int(file_vars["PATCHLEVEL"]),
+    )
+
+
+def repr_command(argv):
+    """Represent an argument array as a string.
+
+    Args:
+        argv: The arguments of the command.
+
+    Returns:
+        A string which could be pasted into a shell for execution.
+    """
+    return " ".join(shlex.quote(str(arg)) for arg in argv)
+
+
+def update_symlink(target_path, link_path):
+    """Create a symlink if it does not exist, or links to a different path.
+
+    Args:
+        target_path: A Path-like object of the desired symlink path.
+        link_path: A Path-like object of the symlink.
+    """
+    target = target_path.resolve()
+    if (
+        not link_path.is_symlink()
+        or pathlib.Path(os.readlink(link_path)).resolve() != target
+    ):
+        if link_path.exists():
+            link_path.unlink()
+        link_path.symlink_to(target)
+
+
+def log_multi_line(logger, level, message):
+    """Log a potentially multi-line message to the logger.
+
+    Args:
+        logger: The Logger object to log to.
+        level: The logging level to use when logging.
+        message: The (potentially) multi-line message to log.
+    """
+    for line in message.splitlines():
+        if line:
+            logger.log(level, line)
+
+
+def get_tool_path(program):
+    """Get the path to a program.
+
+    First, the TOOL_PATH_${program} environment variable is checked,
+    and if unspecified, the PATH environment variable is searched.
+
+    This allows callers to customize which tools zmake uses.
+
+    Args:
+        program: The program to locate
+
+    Returns:
+        The Path to the program.
+    """
+    path = os.environ.get(f"TOOL_PATH_{program}")
+    if path:
+        return pathlib.Path(path).resolve()
+    return pathlib.Path(shutil.which(program))
diff --git a/zephyr/zmake/zmake/version.py b/zephyr/zmake/zmake/version.py
new file mode 100644
index 0000000000..ee857db209
--- /dev/null
+++ b/zephyr/zmake/zmake/version.py
@@ -0,0 +1,173 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Code to generate the ec_version.h file."""
+
+import datetime
+import getpass
+import io
+import os
+import platform
+import subprocess
+
+import zmake.util as util
+
+
+def _get_num_commits(repo):
+    """Get the number of commits that have been made.
+
+    If a Git repository is available, return the number of commits that have
+    been made. Otherwise return a fixed count.
+
+    Args:
+        repo: The path to the git repo.
+
+    Returns:
+        An integer, the number of commits that have been made.
+    """
+    try:
+        result = subprocess.run(
+            ["git", "-C", repo, "rev-list", "HEAD", "--count"],
+            check=True,
+            stdout=subprocess.PIPE,
+            stderr=subprocess.DEVNULL,
+            encoding="utf-8",
+        )
+    except subprocess.CalledProcessError:
+        commits = "9999"
+    else:
+        commits = result.stdout
+
+    return int(commits)
+
+
+def _get_revision(repo):
+    """Get the current revision hash.
+
+    If a Git repository is available, return the hash of the current index.
+    Otherwise return the hash of the VCSID environment variable provided by
+    the packaging system.
+
+    Args:
+        repo: The path to the git repo.
+
+    Returns:
+        A string, of the current revision.
+    """
+    try:
+        result = subprocess.run(
+            ["git", "-C", repo, "log", "-n1", "--format=%H"],
+            check=True,
+            stdout=subprocess.PIPE,
+            stderr=subprocess.DEVNULL,
+            encoding="utf-8",
+        )
+    except subprocess.CalledProcessError:
+        # Fall back to the VCSID provided by the packaging system.
+        # Format is 0.0.1-r425-032666c418782c14fe912ba6d9f98ffdf0b941e9 for
+        # releases and 9999-032666c418782c14fe912ba6d9f98ffdf0b941e9 for
+        # 9999 ebuilds.
+        vcsid = os.environ.get("VCSID", "9999-unknown")
+        revision = vcsid.rsplit("-", 1)[1]
+    else:
+        revision = result.stdout
+
+    return revision
+
+
+def get_version_string(project, zephyr_base, modules, static=False):
+    """Get the version string associated with a build.
+
+    Args:
+        project: a string project name
+        zephyr_base: the path to the zephyr directory
+        modules: a dictionary mapping module names to module paths
+        static: if set, create a version string not dependent on git
+            commits, thus allowing binaries to be compared between two
+            commits.
+
+    Returns:
+        A version string which can be placed in FRID, FWID, or used in
+        the build for the OS.
+    """
+    major_version, minor_version, *_ = util.read_zephyr_version(zephyr_base)
+    num_commits = 0
+
+    if static:
+        vcs_hashes = "STATIC"
+    else:
+        repos = {
+            "os": zephyr_base,
+            **modules,
+        }
+
+        for repo in repos.values():
+            num_commits += _get_num_commits(repo)
+
+        vcs_hashes = ",".join(
+            "{}:{}".format(name, _get_revision(repo)[:6])
+            for name, repo in sorted(
+                repos.items(),
+                # Put the EC module first, then Zephyr OS kernel, as
+                # these are probably the most important hashes to
+                # developers.
+                key=lambda p: (p[0] != "ec", p[0] != "os", p),
+            )
+        )
+
+    return "{}_v{}.{}.{}-{}".format(
+        project,
+        major_version,
+        minor_version,
+        num_commits,
+        vcs_hashes,
+    )
+
+
+def write_version_header(version_str, output_path, tool, static=False):
+    """Generate a version header and write it to the specified path.
+
+    Generate a version header in the format expected by the EC build
+    system, and write it out only if the version header does not exist
+    or changes.  We don't write in the case that the version header
+    does exist and was unchanged, which allows "zmake build" commands
+    on an unchanged tree to be an effective no-op.
+
+    Args:
+        version_str: The version string to be used in the header, such
+            as one generated by get_version_string.
+        output_path: The file path to write at (a pathlib.Path
+            object).
+        tool: Name of the tool that is invoking this function ("zmake",
+            "generate_ec_version.py", etc). Included in a comment in the
+            header.
+        static: If true, generate a header which does not include
+            information like the username, hostname, or date, allowing
+            the build to be reproducible.
+    """
+    output = io.StringIO()
+    output.write(f"/* This file is automatically generated by {tool} */\n")
+
+    def add_def(name, value):
+        output.write("#define {} {}\n".format(name, util.c_str(value)))
+
+    def add_def_unquoted(name, value):
+        output.write("#define {} {}\n".format(name, value))
+
+    add_def("VERSION", version_str)
+    add_def("CROS_EC_VERSION32", version_str[:31])
+
+    if static:
+        add_def("BUILDER", "reproducible@build")
+        add_def("DATE", "STATIC_VERSION_DATE")
+    else:
+        add_def("BUILDER", "{}@{}".format(getpass.getuser(), platform.node()))
+        add_def("DATE", datetime.datetime.now().strftime("%Y-%m-%d %H:%M:%S"))
+
+    # TODO(b/198475757): Add zmake support for getting CROS_FWID32
+    add_def_unquoted("CROS_FWID32", "CROS_FWID_MISSING_STR")
+
+    contents = output.getvalue()
+    if not output_path.exists() or output_path.read_text() != contents:
+        output_path.write_text(contents)
diff --git a/zephyr/zmake/zmake/zmake.py b/zephyr/zmake/zmake/zmake.py
new file mode 100644
index 0000000000..ee9c1aedae
--- /dev/null
+++ b/zephyr/zmake/zmake/zmake.py
@@ -0,0 +1,959 @@
+# Copyright 2020 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Module encapsulating Zmake wrapper object."""
+import atexit
+import difflib
+import functools
+import logging
+import os
+import pathlib
+import re
+import shutil
+import subprocess
+import sys
+import tempfile
+from typing import Dict, Optional, Set, Union
+
+import zmake.build_config
+import zmake.compare_builds
+import zmake.generate_readme
+import zmake.jobserver
+import zmake.modules
+import zmake.multiproc
+import zmake.project
+import zmake.util as util
+import zmake.version
+
+
+ninja_warnings = re.compile(r"^(\S*: )?warning:.*")
+ninja_errors = re.compile(r"error:.*")
+
+
+def ninja_stdout_log_level_override(line, current_log_level):
+    """Update the log level for ninja builds if we hit an error.
+
+    Ninja builds prints everything to stdout, but really we want to start
+    logging things to CRITICAL
+
+    Args:
+        line: The line that is about to be logged.
+        current_log_level: The active logging level that would be used for the
+          line.
+    """
+    # pylint: disable=too-many-return-statements
+    # Output lines from Zephyr that are not normally useful
+    # Send any lines that start with these strings to INFO
+    cmake_suppress = [
+        "-- ",  # device tree messages
+        "Loaded configuration",
+        "Including boilerplate",
+        "Parsing ",
+        "No change to configuration",
+        "No change to Kconfig header",
+    ]
+
+    # Herewith a long list of things which are really for debugging, not
+    # development. Return logging.DEBUG for each of these.
+
+    # ninja puts progress information on stdout
+    if line.startswith("["):
+        return logging.DEBUG
+    # we don't care about entering directories since it happens every time
+    if line.startswith("ninja: Entering directory"):
+        return logging.DEBUG
+    # we know the build stops from the compiler messages and ninja return code
+    if line.startswith("ninja: build stopped"):
+        return logging.DEBUG
+    # someone prints a *** SUCCESS *** message which we don't need
+    if line.startswith("***"):
+        return logging.DEBUG
+    # dopey ninja puts errors on stdout, so fix that. It does not look
+    # likely that it will be fixed upstream:
+    # https://github.com/ninja-build/ninja/issues/1537
+    # Try to drop output about the device tree
+    if any(line.startswith(x) for x in cmake_suppress):
+        return logging.INFO
+    # this message is a bit like make failing. We already got the error output.
+    if line.startswith("FAILED: CMakeFiles"):
+        return logging.INFO
+    # if a particular file fails it shows the build line used, but that is not
+    # useful except for debugging.
+    if line.startswith("ccache"):
+        return logging.DEBUG
+    if ninja_warnings.match(line):
+        return logging.WARNING
+    if ninja_errors.match(line):
+        return logging.ERROR
+    # When we see "Memory region" go into INFO, and stay there as long as the
+    # line starts with \S+:
+    if line.startswith("Memory region"):
+        return logging.INFO
+    if current_log_level == logging.INFO and line.split()[0].endswith(":"):
+        return current_log_level
+    if current_log_level == logging.WARNING:
+        return current_log_level
+    return logging.ERROR
+
+
+def cmake_log_level_override(line, default_log_level):
+    """Update the log level for cmake output if we hit an error.
+
+    Cmake prints some messages that are less than useful during
+    development.
+
+    Args:
+        line: The line that is about to be logged.
+        default_log_level: The default logging level that will be used for the
+          line.
+    """
+    # Strange output from Zephyr that we normally ignore
+    if line.startswith("Including boilerplate"):
+        return logging.DEBUG
+    if line.startswith("devicetree error:"):
+        return logging.ERROR
+    if ninja_warnings.match(line):
+        return logging.WARNING
+    if ninja_errors.match(line):
+        return logging.ERROR
+    return default_log_level
+
+
+def get_process_failure_msg(proc):
+    """Creates a suitable failure message if something exits badly
+
+    Args:
+        proc: subprocess.Popen object containing the thing that failed
+
+    Returns:
+        Failure message as a string:
+    """
+    return "Execution failed (return code={}): {}\n".format(
+        proc.returncode, util.repr_command(proc.args)
+    )
+
+
+class Zmake:
+    """Wrapper class encapsulating zmake's supported operations.
+
+    The invocations of the constructor and the methods actually comes
+    from the main function.  The command line arguments are translated
+    such that dashes are replaced with underscores and applied as
+    keyword arguments to the constructor and the method, and the
+    subcommand invoked becomes the method run.
+
+    As such, you won't find documentation for each method's parameters
+    here, as it would be duplicate of the help strings from the
+    command line.  Run "zmake --help" for full documentation of each
+    parameter.
+
+    Properties:
+        executor: a zmake.multiproc.Executor object for submitting
+            tasks to.
+        _sequential: True to check the results of each build job sequentially,
+            before launching more, False to just do this after all jobs complete
+    """
+
+    # pylint: disable=too-many-instance-attributes
+
+    def __init__(
+        self,
+        checkout=None,
+        jobserver: Optional[zmake.jobserver.JobClient] = None,
+        jobs=0,
+        goma=False,
+        gomacc="/mnt/host/depot_tools/.cipd_bin/gomacc",
+        modules_dir=None,
+        projects_dir=None,
+        zephyr_base=None,
+    ):
+        zmake.multiproc.LogWriter.reset()
+        self.logger = logging.getLogger(self.__class__.__name__)
+        self._checkout = checkout
+        self.goma = goma
+        self.gomacc = gomacc
+        if zephyr_base:
+            self.zephyr_base = zephyr_base
+        else:
+            self.zephyr_base = (
+                self.checkout / "src" / "third_party" / "zephyr" / "main"
+            )
+        self.zephyr_base = self.zephyr_base.resolve()
+
+        if modules_dir:
+            self.module_paths = zmake.modules.locate_from_directory(modules_dir)
+        else:
+            self.module_paths = zmake.modules.locate_from_checkout(
+                self.checkout
+            )
+
+        if projects_dir:
+            self.projects_dir = projects_dir.resolve()
+        else:
+            self.projects_dir = self.module_paths["ec"] / "zephyr"
+
+        if jobserver:
+            self.jobserver = jobserver
+        else:
+            self.jobserver = zmake.jobserver.GNUMakeJobServer(jobs=jobs)
+
+        self.executor = zmake.multiproc.Executor()
+        self._sequential = self.jobserver.is_sequential() and not goma
+        self.cmp_failed_projects = {}
+        self.failed_projects = []
+
+    @property
+    def checkout(self):
+        """Returns the location of the cros checkout."""
+        if not self._checkout:
+            self._checkout = util.locate_cros_checkout()
+        return self._checkout.resolve()
+
+    def _resolve_projects(
+        self,
+        project_names,
+        all_projects=False,
+    ) -> Set[zmake.project.Project]:
+        """Finds all projects for the specified command line flags.
+
+        Returns a list of projects.
+        """
+        found_projects = zmake.project.find_projects(self.projects_dir)
+        if all_projects:
+            projects = set(found_projects.values())
+        else:
+            projects = set()
+            for project_name in project_names:
+                try:
+                    projects.add(found_projects[project_name])
+                except KeyError as e:
+                    raise KeyError(
+                        "No project named {}".format(project_name)
+                    ) from e
+        return projects
+
+    def configure(
+        self,
+        project_names,
+        build_dir=None,
+        toolchain=None,
+        build_after_configure=False,
+        clobber=False,
+        bringup=False,
+        coverage=False,
+        cmake_defs=None,
+        allow_warnings=False,
+        all_projects=False,
+        extra_cflags=None,
+        delete_intermediates=False,
+        static_version=False,
+        save_temps=False,
+        wait_for_executor=True,
+    ):
+        """Locate and configure the specified projects."""
+        # Resolve build_dir if needed.
+        if not build_dir:
+            build_dir = self.module_paths["ec"] / "build" / "zephyr"
+
+        projects = self._resolve_projects(
+            project_names,
+            all_projects=all_projects,
+        )
+        for project in projects:
+            project_build_dir = (
+                pathlib.Path(build_dir) / project.config.project_name
+            )
+            self.executor.append(
+                func=functools.partial(
+                    self._configure,
+                    project=project,
+                    build_dir=project_build_dir,
+                    toolchain=toolchain,
+                    build_after_configure=build_after_configure,
+                    clobber=clobber,
+                    bringup=bringup,
+                    coverage=coverage,
+                    cmake_defs=cmake_defs,
+                    allow_warnings=allow_warnings,
+                    extra_cflags=extra_cflags,
+                    delete_intermediates=delete_intermediates,
+                    static_version=static_version,
+                    save_temps=save_temps,
+                )
+            )
+            if self._sequential:
+                result = self.executor.wait()
+                if result:
+                    return result
+        if coverage and build_after_configure:
+            result = self.executor.wait()
+            if result:
+                return result
+            result = self._merge_lcov_files(
+                projects=projects,
+                build_dir=build_dir,
+                output_file=build_dir / "all_builds.info",
+            )
+            if result:
+                self.failed_projects.append(str(build_dir / "all_builds.info"))
+                return result
+        elif wait_for_executor:
+            result = self.executor.wait()
+            if result:
+                return result
+
+        return 0
+
+    def build(
+        self,
+        project_names,
+        build_dir=None,
+        toolchain=None,
+        clobber=False,
+        bringup=False,
+        coverage=False,
+        cmake_defs=None,
+        allow_warnings=False,
+        all_projects=False,
+        extra_cflags=None,
+        delete_intermediates=False,
+        static_version=False,
+        save_temps=False,
+    ):
+        """Locate and build the specified projects."""
+        return self.configure(
+            project_names,
+            build_dir=build_dir,
+            toolchain=toolchain,
+            clobber=clobber,
+            bringup=bringup,
+            coverage=coverage,
+            cmake_defs=cmake_defs,
+            allow_warnings=allow_warnings,
+            all_projects=all_projects,
+            extra_cflags=extra_cflags,
+            build_after_configure=True,
+            delete_intermediates=delete_intermediates,
+            static_version=static_version,
+            save_temps=save_temps,
+        )
+
+    def compare_builds(
+        self,
+        ref1,
+        ref2,
+        project_names,
+        toolchain=None,
+        all_projects=False,
+        extra_cflags=None,
+        keep_temps=False,
+        cmake_defs=None,
+        compare_configs=False,
+        compare_binaries_disable=False,
+        compare_devicetrees=False,
+    ):
+        """Compare EC builds at two commits."""
+        temp_dir = tempfile.mkdtemp(prefix="zcompare-")
+        if not keep_temps:
+            atexit.register(shutil.rmtree, temp_dir)
+        else:
+            self.logger.info("Temporary dir %s will be retained", temp_dir)
+
+        projects = self._resolve_projects(
+            project_names,
+            all_projects=all_projects,
+        )
+
+        self.logger.info("Compare zephyr builds")
+
+        cmp_builds = zmake.compare_builds.CompareBuilds(temp_dir, ref1, ref2)
+
+        for checkout in cmp_builds.checkouts:
+            self.logger.info(
+                "Checkout %s: full hash %s", checkout.ref, checkout.full_ref
+            )
+
+        cmp_builds.do_checkouts(self.zephyr_base, self.module_paths)
+
+        for checkout in cmp_builds.checkouts:
+            # Now that the sources have been checked out, transform the
+            # zephyr-base and module-paths to use the temporary directory
+            # created by BuildInfo.
+            for module_name in self.module_paths.keys():
+                new_path = checkout.modules_dir / module_name
+                transformed_module = {module_name: new_path}
+                self.module_paths.update(transformed_module)
+
+            self.projects_dir = checkout.projects_dir
+            self.zephyr_base = checkout.zephyr_dir
+
+            self.logger.info("Building projects at %s", checkout.ref)
+            result = self.configure(
+                project_names,
+                build_dir=None,
+                toolchain=toolchain,
+                clobber=False,
+                bringup=False,
+                coverage=False,
+                cmake_defs=cmake_defs,
+                allow_warnings=False,
+                all_projects=all_projects,
+                extra_cflags=extra_cflags,
+                build_after_configure=True,
+                delete_intermediates=False,
+                static_version=True,
+                save_temps=False,
+                wait_for_executor=False,
+            )
+            if not result:
+                result = self.executor.wait()
+            if result:
+                self.logger.error(
+                    "compare-builds failed to build all projects at %s",
+                    checkout.ref,
+                )
+                return result
+        if not compare_binaries_disable:
+            failed_projects = cmp_builds.check_binaries(projects)
+            self.cmp_failed_projects["binary"] = failed_projects
+            self.failed_projects.extend(failed_projects)
+        if compare_configs:
+            failed_projects = cmp_builds.check_configs(projects)
+            self.cmp_failed_projects["config"] = failed_projects
+            self.failed_projects.extend(failed_projects)
+        if compare_devicetrees:
+            failed_projects = cmp_builds.check_devicetrees(projects)
+            self.cmp_failed_projects["devicetree"] = failed_projects
+            self.failed_projects.extend(failed_projects)
+
+        self.failed_projects = list(set(self.failed_projects))
+        if len(self.failed_projects) == 0:
+            self.logger.info("Zephyr compare builds successful:")
+            for checkout in cmp_builds.checkouts:
+                self.logger.info("   %s: %s", checkout.ref, checkout.full_ref)
+
+        return len(self.failed_projects)
+
+    def _configure(
+        self,
+        project,
+        build_dir: pathlib.Path,
+        toolchain=None,
+        build_after_configure=False,
+        clobber=False,
+        bringup=False,
+        coverage=False,
+        cmake_defs=None,
+        allow_warnings=False,
+        extra_cflags=None,
+        delete_intermediates=False,
+        static_version=False,
+        save_temps=False,
+    ):
+        """Set up a build directory to later be built by "zmake build"."""
+        try:
+            with self.jobserver.get_job():
+                # Clobber build directory if requested.
+                if clobber and build_dir.exists():
+                    self.logger.info(
+                        "Clearing build directory %s due to --clobber",
+                        build_dir,
+                    )
+                    shutil.rmtree(build_dir)
+
+                generated_include_dir = (build_dir / "include").resolve()
+                base_config = zmake.build_config.BuildConfig(
+                    cmake_defs={
+                        "CMAKE_EXPORT_COMPILE_COMMANDS": "ON",
+                        "DTS_ROOT": str(self.module_paths["ec"] / "zephyr"),
+                        "SYSCALL_INCLUDE_DIRS": str(
+                            self.module_paths["ec"]
+                            / "zephyr"
+                            / "include"
+                            / "drivers"
+                        ),
+                        "USER_CACHE_DIR": str(
+                            self.module_paths["ec"]
+                            / "build"
+                            / "zephyr"
+                            / "user-cache"
+                        ),
+                        "ZEPHYR_BASE": str(self.zephyr_base),
+                        "ZMAKE_INCLUDE_DIR": str(generated_include_dir),
+                        "PYTHON_PREFER": sys.executable,
+                        **(
+                            {"EXTRA_EC_VERSION_FLAGS": "--static"}
+                            if static_version
+                            else {}
+                        ),
+                    },
+                )
+                if cmake_defs:
+                    base_config |= zmake.build_config.BuildConfig.from_args(
+                        cmake_defs
+                    )
+
+                # Prune the module paths to just those required by the project.
+                module_paths = project.prune_modules(self.module_paths)
+
+                module_config = zmake.modules.setup_module_symlinks(
+                    build_dir / "modules", module_paths
+                )
+
+                # Symlink the Zephyr base into the build directory so it can
+                # be used in the build phase.
+                util.update_symlink(self.zephyr_base, build_dir / "zephyr_base")
+
+                dts_overlay_config = project.find_dts_overlays(module_paths)
+
+                toolchain_support = project.get_toolchain(
+                    self.module_paths, override=toolchain
+                )
+                toolchain_config = toolchain_support.get_build_config()
+
+                if bringup:
+                    base_config |= zmake.build_config.BuildConfig(
+                        kconfig_defs={"CONFIG_PLATFORM_EC_BRINGUP": "y"}
+                    )
+                if coverage:
+                    base_config |= zmake.build_config.BuildConfig(
+                        kconfig_defs={"CONFIG_COVERAGE": "y"}
+                    )
+                if save_temps:
+                    base_config |= zmake.build_config.BuildConfig(
+                        kconfig_defs={"CONFIG_COMPILER_SAVE_TEMPS": "y"}
+                    )
+                if not allow_warnings:
+                    base_config |= zmake.build_config.BuildConfig(
+                        kconfig_defs={"CONFIG_COMPILER_WARNINGS_AS_ERRORS": "y"}
+                    )
+                if extra_cflags:
+                    base_config |= zmake.build_config.BuildConfig(
+                        cmake_defs={"EXTRA_CFLAGS": extra_cflags},
+                    )
+                if self.goma:
+                    base_config |= zmake.build_config.BuildConfig(
+                        cmake_defs={
+                            "CMAKE_C_COMPILER_LAUNCHER": self.gomacc,
+                            "CMAKE_CXX_COMPILER_LAUNCHER": self.gomacc,
+                        },
+                    )
+
+                if not build_dir.exists():
+                    build_dir.mkdir()
+                if not generated_include_dir.exists():
+                    generated_include_dir.mkdir()
+                self.logger.info(
+                    "Building %s in %s.", project.config.project_name, build_dir
+                )
+                # To reconstruct a Project object later, we need to know the
+                # name and project directory.
+                (build_dir / "project_name.txt").write_text(
+                    project.config.project_name
+                )
+                util.update_symlink(
+                    project.config.project_dir, build_dir / "project"
+                )
+
+                wait_funcs = []
+                for build_name, build_config in project.iter_builds():
+                    config: zmake.build_config.BuildConfig = (
+                        base_config
+                        | toolchain_config
+                        | module_config
+                        | dts_overlay_config
+                        | build_config
+                    )
+
+                    wait_func = self.executor.append(
+                        func=functools.partial(
+                            self._configure_one_build,
+                            config=config,
+                            build_dir=build_dir,
+                            build_name=build_name,
+                            project=project,
+                        )
+                    )
+                    wait_funcs.append(wait_func)
+            # Outside the with...get_job above.
+            result = 0
+            for wait_func in wait_funcs:
+                if wait_func():
+                    result = 1
+            if result:
+                self.failed_projects.append(project.config.project_name)
+                return 1
+
+            if build_after_configure:
+                self._build(
+                    build_dir=build_dir,
+                    project=project,
+                    coverage=coverage,
+                    static_version=static_version,
+                    delete_intermediates=delete_intermediates,
+                )
+            return 0
+        except Exception:
+            self.failed_projects.append(project.config.project_name)
+            raise
+
+    def _configure_one_build(
+        self,
+        config,
+        build_dir,
+        build_name,
+        project,
+    ):
+        """Run cmake and maybe ninja on one build dir."""
+        with self.jobserver.get_job():
+            config_json = config.as_json()
+            config_json_file = build_dir / f"cfg-{build_name}.json"
+            if config_json_file.is_file():
+                if config_json_file.read_text() == config_json:
+                    self.logger.info(
+                        "Skip reconfiguring %s:%s due to previous cmake run of "
+                        "equivalent configuration.  Run with --clobber if this "
+                        "optimization is undesired.",
+                        project.config.project_name,
+                        build_name,
+                    )
+                    return 0
+                config_json_file.unlink()
+
+            output_dir = build_dir / "build-{}".format(build_name)
+            if output_dir.exists():
+                self.logger.info(
+                    "Clobber %s due to configuration changes.",
+                    output_dir,
+                )
+                shutil.rmtree(output_dir)
+
+            self.logger.info(
+                "Configuring %s:%s.",
+                project.config.project_name,
+                build_name,
+            )
+
+            kconfig_file = build_dir / "kconfig-{}.conf".format(build_name)
+            proc = config.popen_cmake(
+                self.jobserver,
+                project.config.project_dir,
+                output_dir,
+                kconfig_file,
+                stdin=subprocess.DEVNULL,
+                stdout=subprocess.PIPE,
+                stderr=subprocess.PIPE,
+                encoding="utf-8",
+                errors="replace",
+            )
+            job_id = "{}:{}".format(project.config.project_name, build_name)
+            zmake.multiproc.LogWriter.log_output(
+                self.logger,
+                logging.DEBUG,
+                proc.stdout,
+                log_level_override_func=cmake_log_level_override,
+                job_id=job_id,
+            )
+            zmake.multiproc.LogWriter.log_output(
+                self.logger,
+                logging.ERROR,
+                proc.stderr,
+                log_level_override_func=cmake_log_level_override,
+                job_id=job_id,
+            )
+            if proc.wait():
+                raise OSError(get_process_failure_msg(proc))
+            config_json_file.write_text(config_json)
+            return 0
+
+    def _build(
+        self,
+        build_dir,
+        project: zmake.project.Project,
+        coverage=False,
+        static_version=False,
+        delete_intermediates=False,
+    ):
+        """Build a pre-configured build directory."""
+
+        with self.jobserver.get_job():
+            dirs: Dict[str, pathlib.Path] = {}
+
+            build_dir = build_dir.resolve()
+
+            # Compute the version string.
+            version_string = zmake.version.get_version_string(
+                project.config.project_name,
+                build_dir / "zephyr_base",
+                zmake.modules.locate_from_directory(build_dir / "modules"),
+                static=static_version,
+            )
+
+            # The version header needs to generated during the build phase
+            # instead of configure, as the tree may have changed since
+            # configure was run.
+            zmake.version.write_version_header(
+                version_string,
+                build_dir / "include" / "ec_version.h",
+                "zmake",
+                static=static_version,
+            )
+
+            gcov = "gcov.sh-not-found"
+            wait_funcs = []
+            for build_name, _ in project.iter_builds():
+                dirs[build_name] = build_dir / "build-{}".format(build_name)
+                gcov = dirs[build_name] / "gcov.sh"
+                wait_func = self.executor.append(
+                    func=functools.partial(
+                        self._build_one_dir,
+                        build_name=build_name,
+                        dirs=dirs,
+                        coverage=coverage,
+                        project=project,
+                    )
+                )
+                wait_funcs.append(wait_func)
+        # Outside the with...get_job above.
+        result = 0
+        for wait_func in wait_funcs:
+            if wait_func():
+                result = 1
+        if result:
+            self.failed_projects.append(project.config.project_name)
+            return 1
+
+        with self.jobserver.get_job():
+            # Run the packer.
+            packer_work_dir = build_dir / "packer"
+            output_dir = build_dir / "output"
+            for newdir in output_dir, packer_work_dir:
+                if not newdir.exists():
+                    newdir.mkdir()
+
+            # Projects won't link with coverage, so don't pack the firmware.
+            # Also generate a lcov file.
+            if coverage:
+                self._run_lcov(
+                    build_dir,
+                    output_dir / "zephyr.info",
+                    initial=True,
+                    gcov=gcov,
+                )
+            else:
+                for output_file, output_name in project.packer.pack_firmware(
+                    packer_work_dir,
+                    self.jobserver,
+                    dirs,
+                    version_string=version_string,
+                ):
+                    shutil.copy2(output_file, output_dir / output_name)
+                    self.logger.debug("Output file '%s' created.", output_file)
+
+            if delete_intermediates:
+                outdir = build_dir / "output"
+                for child in build_dir.iterdir():
+                    if child != outdir:
+                        logging.debug("Deleting %s", child)
+                        if not child.is_symlink() and child.is_dir():
+                            shutil.rmtree(child)
+                        else:
+                            child.unlink()
+            return 0
+
+    def _build_one_dir(self, build_name, dirs, coverage, project):
+        """Builds one sub-dir of a configured project (build-ro, etc)."""
+
+        with self.jobserver.get_job():
+            cmd = [
+                util.get_tool_path("ninja"),
+                "-C",
+                dirs[build_name].as_posix(),
+            ]
+            if self.goma:
+                # Go nuts ninja, goma does the heavy lifting!
+                cmd.append("-j1024")
+            elif self._sequential:
+                cmd.append("-j1")
+            if coverage:
+                cmd.append("all.libraries")
+            self.logger.info(
+                "Building %s:%s: %s",
+                project.config.project_name,
+                build_name,
+                util.repr_command(cmd),
+            )
+            proc = self.jobserver.popen(
+                cmd,
+                stdout=subprocess.PIPE,
+                stderr=subprocess.PIPE,
+                encoding="utf-8",
+                errors="replace",
+                # TODO(b/239619222): Filter os.environ for ninja.
+                env=os.environ,
+            )
+            job_id = "{}:{}".format(project.config.project_name, build_name)
+            dirs[build_name].mkdir(parents=True, exist_ok=True)
+            build_log = open(  # pylint:disable=consider-using-with
+                dirs[build_name] / "build.log",
+                "w",
+            )
+            out = zmake.multiproc.LogWriter.log_output(
+                logger=self.logger,
+                log_level=logging.INFO,
+                file_descriptor=proc.stdout,
+                log_level_override_func=ninja_stdout_log_level_override,
+                job_id=job_id,
+                tee_output=build_log,
+            )
+            err = zmake.multiproc.LogWriter.log_output(
+                self.logger,
+                logging.ERROR,
+                proc.stderr,
+                job_id=job_id,
+            )
+
+            if proc.wait():
+                raise OSError(get_process_failure_msg(proc))
+
+            # Let all output be produced before exiting
+            out.wait()
+            err.wait()
+            return 0
+
+    def _run_lcov(
+        self,
+        build_dir,
+        lcov_file,
+        initial=False,
+        gcov: Union[os.PathLike, str] = "",
+    ):
+        gcov = os.path.abspath(gcov)
+        if initial:
+            self.logger.info("Running (initial) lcov on %s.", build_dir)
+        else:
+            self.logger.info("Running lcov on %s.", build_dir)
+        cmd = [
+            util.get_tool_path("lcov"),
+            "--gcov-tool",
+            gcov,
+            "-q",
+            "-o",
+            "-",
+            "-c",
+            "-d",
+            build_dir,
+            "-t",
+            build_dir.stem,
+            "--rc",
+            "lcov_branch_coverage=1",
+        ]
+        if initial:
+            cmd += ["-i"]
+        proc = self.jobserver.popen(
+            cmd,
+            stdout=subprocess.PIPE,
+            stderr=subprocess.PIPE,
+            encoding="utf-8",
+            errors="replace",
+        )
+        zmake.multiproc.LogWriter.log_output(
+            self.logger,
+            logging.WARNING,
+            proc.stderr,
+            job_id="{}-lcov".format(build_dir),
+        )
+
+        with open(lcov_file, "w") as outfile:
+            for line in proc.stdout:
+                if line.startswith("SF:"):
+                    path = line[3:].rstrip()
+                    outfile.write("SF:%s\n" % os.path.realpath(path))
+                else:
+                    outfile.write(line)
+        if proc.wait():
+            raise OSError(get_process_failure_msg(proc))
+
+        return 0
+
+    def _merge_lcov_files(self, projects, build_dir, output_file):
+        all_lcov_files = []
+        for project in projects:
+            project_build_dir = (
+                pathlib.Path(build_dir) / project.config.project_name
+            )
+            all_lcov_files.append(project_build_dir / "output" / "zephyr.info")
+        # Merge info files into a single lcov.info
+        self.logger.info("Merging coverage data into %s.", output_file)
+        cmd = [
+            util.get_tool_path("lcov"),
+            "-o",
+            output_file,
+            "--rc",
+            "lcov_branch_coverage=1",
+        ]
+        for info in all_lcov_files:
+            cmd += ["-a", info]
+        proc = self.jobserver.popen(
+            cmd,
+            stdout=subprocess.PIPE,
+            stderr=subprocess.PIPE,
+            encoding="utf-8",
+            errors="replace",
+        )
+        zmake.multiproc.LogWriter.log_output(
+            self.logger, logging.ERROR, proc.stderr, job_id="lcov"
+        )
+        zmake.multiproc.LogWriter.log_output(
+            self.logger, logging.DEBUG, proc.stdout, job_id="lcov"
+        )
+        if proc.wait():
+            raise OSError(get_process_failure_msg(proc))
+        return 0
+
+    def list_projects(self, fmt):
+        """List project names known to zmake on stdout.
+
+        Args:
+            fmt: The formatting string to print projects with.
+        """
+        for project in zmake.project.find_projects(self.projects_dir).values():
+            print(fmt.format(config=project.config), end="")
+
+        return 0
+
+    def generate_readme(self, output_file, diff=False):
+        """Re-generate the auto-generated README file.
+
+        Args:
+            output_file: A pathlib.Path; to be written only if changed.
+            diff: Instead of writing out, report the diff.
+        """
+        expected_contents = zmake.generate_readme.generate_readme()
+
+        if output_file.is_file():
+            current_contents = output_file.read_text()
+            if expected_contents == current_contents:
+                return 0
+            if diff:
+                self.logger.error(
+                    "The auto-generated README.md differs from the expected contents:"
+                )
+                for line in difflib.unified_diff(
+                    current_contents.splitlines(keepends=True),
+                    expected_contents.splitlines(keepends=True),
+                    str(output_file),
+                ):
+                    self.logger.error(line.rstrip())
+                self.logger.error('Run "zmake generate-readme" to fix this.')
+                return 1
+
+        if diff:
+            self.logger.error(
+                'The README.md file does not exist.  Run "zmake generate-readme".'
+            )
+            return 1
+
+        output_file.write_text(expected_contents)
+        return 0